diff --git a/flow/Makefile b/flow/Makefile index 7bccdc8307..14f29b8a1f 100644 --- a/flow/Makefile +++ b/flow/Makefile @@ -44,6 +44,7 @@ # DESIGN_CONFIG=./designs/sky130hd/chameleon/config.mk # DESIGN_CONFIG=./designs/sky130hd/gcd/config.mk # DESIGN_CONFIG=./designs/sky130hd/ibex/config.mk +# DESIGN_CONFIG=./designs/sky130hd/counter/config.mk # DESIGN_CONFIG=./designs/sky130hd/jpeg/config.mk # DESIGN_CONFIG=./designs/sky130hd/microwatt/config.mk # DESIGN_CONFIG=./designs/sky130hd/riscv32i/config.mk @@ -77,8 +78,10 @@ # DESIGN_CONFIG=./designs/gf180/uart-blocks/config.mk #DESIGN_CONFIG=./designs/ihp-sg13g2/aes/config.mk +#DESIGN_CONFIG=./designs/ihp-sg13g2/counter/config.mk #DESIGN_CONFIG=./designs/ihp-sg13g2/ibex/config.mk #DESIGN_CONFIG=./designs/ihp-sg13g2/gcd/config.mk +#DESIGN_CONFIG=./designs/ihp-sg13g2/murax/config.mk #DESIGN_CONFIG=./designs/ihp-sg13g2/spi/config.mk #DESIGN_CONFIG=./designs/ihp-sg13g2/riscv32i/config.mk #DESIGN_CONFIG=./designs/ihp-sg13g2/i2c-gpio-expander/config.mk diff --git a/flow/designs/ihp-sg13g2/counter/config.mk b/flow/designs/ihp-sg13g2/counter/config.mk new file mode 100644 index 0000000000..9ed0c46a58 --- /dev/null +++ b/flow/designs/ihp-sg13g2/counter/config.mk @@ -0,0 +1,21 @@ +export DESIGN_NICKNAME = counter +export DESIGN_NAME = counter +export PLATFORM = ihp-sg13g2 + +export VHDL_FILES = $(sort $(wildcard $(DESIGN_HOME)/src/counter/*.vhd)) + +export SYNTH_HDL_FRONTEND = ghdl + +export SDC_FILE = $(DESIGN_HOME)/$(PLATFORM)/$(DESIGN_NICKNAME)/constraint.sdc + +export CORE_UTILIZATION = 20 +export CORE_ASPECT_RATIO = 1 + +export PLACE_DENSITY = 0.65 +export TNS_END_PERCENT = 100 + +export USE_FILL = 1 + +export REMOVE_ABC_BUFFERS = 1 + + diff --git a/flow/designs/ihp-sg13g2/counter/constraint.sdc b/flow/designs/ihp-sg13g2/counter/constraint.sdc new file mode 100644 index 0000000000..57701f459d --- /dev/null +++ b/flow/designs/ihp-sg13g2/counter/constraint.sdc @@ -0,0 +1,15 @@ +current_design counter + +set clk_name core_clock +set clk_port_name clk +set clk_period 10.0 +set clk_io_pct 0.2 + +set clk_port [get_ports $clk_port_name] + +create_clock -name $clk_name -period $clk_period $clk_port + +set non_clock_inputs [all_inputs -no_clocks] + +set_input_delay [expr $clk_period * $clk_io_pct] -clock $clk_name $non_clock_inputs +set_output_delay [expr $clk_period * $clk_io_pct] -clock $clk_name [all_outputs] diff --git a/flow/designs/ihp-sg13g2/murax/config.mk b/flow/designs/ihp-sg13g2/murax/config.mk new file mode 100644 index 0000000000..415ef2e98a --- /dev/null +++ b/flow/designs/ihp-sg13g2/murax/config.mk @@ -0,0 +1,29 @@ +export DESIGN_NICKNAME = murax +export DESIGN_NAME = de1_murax_franz +export PLATFORM = ihp-sg13g2 + +export VHDL_FILES = $(DESIGN_HOME)/src/murax/murax_pkg.vhd \ + $(DESIGN_HOME)/src/murax/murax_ram.vhd \ + $(DESIGN_HOME)/src/murax/de1_murax_franz.vhd + +export SYNTH_HDL_FRONTEND = ghdl + +export SDC_FILE = $(DESIGN_HOME)/$(PLATFORM)/$(DESIGN_NICKNAME)/constraint.sdc + +export CORE_UTILIZATION = 60 +export CORE_ASPECT_RATIO = 1 + +export ADDITIONAL_LEFS = $(PLATFORM_DIR)/lef/RM_IHPSG13_1P_1024x8_c2_bm_bist.lef +export ADDITIONAL_TYP_LIBS = $(PLATFORM_DIR)/lib/RM_IHPSG13_1P_1024x8_c2_bm_bist_typ_1p20V_25C.lib +export ADDITIONAL_SLOW_LIBS = $(PLATFORM_DIR)/lib/RM_IHPSG13_1P_1024x8_c2_bm_bist_slow_1p08V_125C.lib +export ADDITIONAL_FAST_LIBS = $(PLATFORM_DIR)/lib/RM_IHPSG13_1P_1024x8_c2_bm_bist_fast_1p32V_m55C.lib +export ADDITIONAL_GDS = $(PLATFORM_DIR)/gds/RM_IHPSG13_1P_1024x8_c2_bm_bist.gds + +export PLACE_DENSITY = 0.65 +export TNS_END_PERCENT = 100 + +export USE_FILL = 1 + +export REMOVE_ABC_BUFFERS = 1 + + diff --git a/flow/designs/ihp-sg13g2/murax/constraint.sdc b/flow/designs/ihp-sg13g2/murax/constraint.sdc new file mode 100644 index 0000000000..3be76867b7 --- /dev/null +++ b/flow/designs/ihp-sg13g2/murax/constraint.sdc @@ -0,0 +1,15 @@ +current_design counter + +set clk_name core_clock +set clk_port_name CLOCK_50 +set clk_period 10.0 +set clk_io_pct 0.2 + +set clk_port [get_ports $clk_port_name] + +create_clock -name $clk_name -period $clk_period $clk_port + +set non_clock_inputs [all_inputs -no_clocks] + +set_input_delay [expr $clk_period * $clk_io_pct] -clock $clk_name $non_clock_inputs +set_output_delay [expr $clk_period * $clk_io_pct] -clock $clk_name [all_outputs] diff --git a/flow/designs/sky130hd/counter/config.mk b/flow/designs/sky130hd/counter/config.mk new file mode 100644 index 0000000000..401955dac5 --- /dev/null +++ b/flow/designs/sky130hd/counter/config.mk @@ -0,0 +1,16 @@ +export DESIGN_NICKNAME = counter +export DESIGN_NAME = counter +export PLATFORM = sky130hd + +export VHDL_FILES = $(sort $(wildcard $(DESIGN_HOME)/src/counter/*.vhd)) + +export SYNTH_HDL_FRONTEND = ghdl + +export SDC_FILE = $(DESIGN_HOME)/$(PLATFORM)/$(DESIGN_NICKNAME)/constraint.sdc + +export CORE_UTILIZATION = 50 +export PLACE_DENSITY_LB_ADDON = 0.25 +export TNS_END_PERCENT = 100 + +export REMOVE_ABC_BUFFERS = 1 + diff --git a/flow/designs/sky130hd/counter/constraint.sdc b/flow/designs/sky130hd/counter/constraint.sdc new file mode 100644 index 0000000000..57701f459d --- /dev/null +++ b/flow/designs/sky130hd/counter/constraint.sdc @@ -0,0 +1,15 @@ +current_design counter + +set clk_name core_clock +set clk_port_name clk +set clk_period 10.0 +set clk_io_pct 0.2 + +set clk_port [get_ports $clk_port_name] + +create_clock -name $clk_name -period $clk_period $clk_port + +set non_clock_inputs [all_inputs -no_clocks] + +set_input_delay [expr $clk_period * $clk_io_pct] -clock $clk_name $non_clock_inputs +set_output_delay [expr $clk_period * $clk_io_pct] -clock $clk_name [all_outputs] diff --git a/flow/designs/src/counter/counter.vhd b/flow/designs/src/counter/counter.vhd new file mode 100644 index 0000000000..6503888626 --- /dev/null +++ b/flow/designs/src/counter/counter.vhd @@ -0,0 +1,19 @@ +library ieee; +use ieee.std_logic_1164.all; +use ieee.numeric_std.all; + +entity counter is + port( + en_i : in std_ulogic; + cnt_o : out unsigned(15 downto 0); + clk : in std_ulogic; + rst_n : in std_ulogic + ); +end counter; + +architecture rtl of counter is + signal cnt : unsigned(cnt_o'range); +begin + cnt <= (others => '0') when rst_n = '0' else cnt + 1 when en_i = '1' and rising_edge(clk); + cnt_o <= cnt; +end rtl; diff --git a/flow/designs/src/murax/de1_murax_franz.vhd b/flow/designs/src/murax/de1_murax_franz.vhd new file mode 100644 index 0000000000..250a9adbbf --- /dev/null +++ b/flow/designs/src/murax/de1_murax_franz.vhd @@ -0,0 +1,6414 @@ + + +library ieee; +use ieee.std_logic_1164.all; +use ieee.numeric_std.all; + +library work; +use work.pkg_scala2hdl.all; +use work.all; +use work.pkg_enum.all; + + +entity BufferCC is + port( + io_dataIn : in std_logic; + io_dataOut : out std_logic; + io_mainClk : in std_logic; + resetCtrl_systemReset : in std_logic + ); +end BufferCC; + +architecture arch of BufferCC is + attribute async_reg : string; + + signal buffers_0 : std_logic; + attribute async_reg of buffers_0 : signal is "true"; + signal buffers_1 : std_logic; + attribute async_reg of buffers_1 : signal is "true"; +begin + io_dataOut <= buffers_1; + process(io_mainClk, resetCtrl_systemReset) + begin + if resetCtrl_systemReset = '1' then + buffers_0 <= pkg_toStdLogic(false); + buffers_1 <= pkg_toStdLogic(false); + elsif rising_edge(io_mainClk) then + buffers_0 <= io_dataIn; + buffers_1 <= buffers_0; + end if; + end process; + +end arch; + +library ieee; +use ieee.std_logic_1164.all; +use ieee.numeric_std.all; + +library work; +use work.pkg_scala2hdl.all; +use work.all; +use work.pkg_enum.all; + + +entity BufferCC_1 is + port( + io_dataIn : in std_logic; + io_dataOut : out std_logic; + io_mainClk : in std_logic; + resetCtrl_mainClkReset : in std_logic + ); +end BufferCC_1; + +architecture arch of BufferCC_1 is + attribute async_reg : string; + + signal buffers_0 : std_logic := '0'; + attribute async_reg of buffers_0 : signal is "true"; + signal buffers_1 : std_logic := '0'; + attribute async_reg of buffers_1 : signal is "true"; +begin + io_dataOut <= buffers_1; + process(io_mainClk) + begin + if rising_edge(io_mainClk) then + buffers_0 <= io_dataIn; + buffers_1 <= buffers_0; + end if; + end process; + +end arch; + +library ieee; +use ieee.std_logic_1164.all; +use ieee.numeric_std.all; + +library work; +use work.pkg_scala2hdl.all; +use work.all; +use work.pkg_enum.all; + + +entity UartCtrlTx is + port( + io_configFrame_dataLength : in unsigned(2 downto 0); + io_configFrame_stop : in UartStopType_seq_type; + io_configFrame_parity : in UartParityType_seq_type; + io_samplingTick : in std_logic; + io_write_valid : in std_logic; + io_write_ready : out std_logic; + io_write_payload : in std_logic_vector(7 downto 0); + io_cts : in std_logic; + io_txd : out std_logic; + io_break : in std_logic; + io_mainClk : in std_logic; + resetCtrl_systemReset : in std_logic + ); +end UartCtrlTx; + +architecture arch of UartCtrlTx is + + signal clockDivider_counter_willIncrement : std_logic; + signal clockDivider_counter_willClear : std_logic; + signal clockDivider_counter_valueNext : unsigned(2 downto 0); + signal clockDivider_counter_value : unsigned(2 downto 0); + signal clockDivider_counter_willOverflowIfInc : std_logic; + signal clockDivider_counter_willOverflow : std_logic; + signal tickCounter_value : unsigned(2 downto 0); + signal stateMachine_state : UartCtrlTxState; + signal stateMachine_parity : std_logic; + signal stateMachine_txd : std_logic; + signal when_UartCtrlTx_l58 : std_logic; + signal when_UartCtrlTx_l73 : std_logic; + signal when_UartCtrlTx_l76 : std_logic; + signal when_UartCtrlTx_l93 : std_logic; + signal zz_stateMachine_state : UartCtrlTxState; + signal zz_io_txd : std_logic; +begin + process(io_samplingTick) + begin + clockDivider_counter_willIncrement <= pkg_toStdLogic(false); + if io_samplingTick = '1' then + clockDivider_counter_willIncrement <= pkg_toStdLogic(true); + end if; + end process; + + clockDivider_counter_willClear <= pkg_toStdLogic(false); + clockDivider_counter_willOverflowIfInc <= pkg_toStdLogic(clockDivider_counter_value = pkg_unsigned("100")); + clockDivider_counter_willOverflow <= (clockDivider_counter_willOverflowIfInc and clockDivider_counter_willIncrement); + process(clockDivider_counter_willOverflow,clockDivider_counter_value,clockDivider_counter_willIncrement,clockDivider_counter_willClear) + begin + if clockDivider_counter_willOverflow = '1' then + clockDivider_counter_valueNext <= pkg_unsigned("000"); + else + clockDivider_counter_valueNext <= (clockDivider_counter_value + pkg_resize(unsigned(pkg_toStdLogicVector(clockDivider_counter_willIncrement)),3)); + end if; + if clockDivider_counter_willClear = '1' then + clockDivider_counter_valueNext <= pkg_unsigned("000"); + end if; + end process; + + process(stateMachine_state,io_write_payload,tickCounter_value,stateMachine_parity) + begin + stateMachine_txd <= pkg_toStdLogic(true); + case stateMachine_state is + when pkg_enum.IDLE => + when pkg_enum.START => + stateMachine_txd <= pkg_toStdLogic(false); + when pkg_enum.DATA => + stateMachine_txd <= pkg_extract(io_write_payload,to_integer(tickCounter_value)); + when pkg_enum.PARITY => + stateMachine_txd <= stateMachine_parity; + when others => + end case; + end process; + + process(io_break,stateMachine_state,clockDivider_counter_willOverflow,when_UartCtrlTx_l73) + begin + io_write_ready <= io_break; + case stateMachine_state is + when pkg_enum.IDLE => + when pkg_enum.START => + when pkg_enum.DATA => + if clockDivider_counter_willOverflow = '1' then + if when_UartCtrlTx_l73 = '1' then + io_write_ready <= pkg_toStdLogic(true); + end if; + end if; + when pkg_enum.PARITY => + when others => + end case; + end process; + + when_UartCtrlTx_l58 <= ((io_write_valid and (not io_cts)) and clockDivider_counter_willOverflow); + when_UartCtrlTx_l73 <= pkg_toStdLogic(tickCounter_value = io_configFrame_dataLength); + when_UartCtrlTx_l76 <= pkg_toStdLogic(io_configFrame_parity = UartParityType_seq_NONE); + when_UartCtrlTx_l93 <= pkg_toStdLogic(tickCounter_value = pkg_resize(pkg_mux(pkg_toStdLogic(io_configFrame_stop = UartStopType_seq_ONE),pkg_unsigned("0"),pkg_unsigned("1")),3)); + zz_stateMachine_state <= pkg_mux(io_write_valid,pkg_enum.START,pkg_enum.IDLE); + io_txd <= zz_io_txd; + process(io_mainClk, resetCtrl_systemReset) + begin + if resetCtrl_systemReset = '1' then + clockDivider_counter_value <= pkg_unsigned("000"); + stateMachine_state <= pkg_enum.IDLE; + zz_io_txd <= pkg_toStdLogic(true); + elsif rising_edge(io_mainClk) then + clockDivider_counter_value <= clockDivider_counter_valueNext; + case stateMachine_state is + when pkg_enum.IDLE => + if when_UartCtrlTx_l58 = '1' then + stateMachine_state <= pkg_enum.START; + end if; + when pkg_enum.START => + if clockDivider_counter_willOverflow = '1' then + stateMachine_state <= pkg_enum.DATA; + end if; + when pkg_enum.DATA => + if clockDivider_counter_willOverflow = '1' then + if when_UartCtrlTx_l73 = '1' then + if when_UartCtrlTx_l76 = '1' then + stateMachine_state <= pkg_enum.STOP; + else + stateMachine_state <= pkg_enum.PARITY; + end if; + end if; + end if; + when pkg_enum.PARITY => + if clockDivider_counter_willOverflow = '1' then + stateMachine_state <= pkg_enum.STOP; + end if; + when others => + if clockDivider_counter_willOverflow = '1' then + if when_UartCtrlTx_l93 = '1' then + stateMachine_state <= zz_stateMachine_state; + end if; + end if; + end case; + zz_io_txd <= (stateMachine_txd and (not io_break)); + end if; + end process; + + process(io_mainClk) + begin + if rising_edge(io_mainClk) then + if clockDivider_counter_willOverflow = '1' then + tickCounter_value <= (tickCounter_value + pkg_unsigned("001")); + end if; + if clockDivider_counter_willOverflow = '1' then + stateMachine_parity <= (stateMachine_parity xor stateMachine_txd); + end if; + case stateMachine_state is + when pkg_enum.IDLE => + when pkg_enum.START => + if clockDivider_counter_willOverflow = '1' then + stateMachine_parity <= pkg_toStdLogic(io_configFrame_parity = UartParityType_seq_ODD); + tickCounter_value <= pkg_unsigned("000"); + end if; + when pkg_enum.DATA => + if clockDivider_counter_willOverflow = '1' then + if when_UartCtrlTx_l73 = '1' then + tickCounter_value <= pkg_unsigned("000"); + end if; + end if; + when pkg_enum.PARITY => + if clockDivider_counter_willOverflow = '1' then + tickCounter_value <= pkg_unsigned("000"); + end if; + when others => + end case; + end if; + end process; + +end arch; + +library ieee; +use ieee.std_logic_1164.all; +use ieee.numeric_std.all; + +library work; +use work.pkg_scala2hdl.all; +use work.all; +use work.pkg_enum.all; + + +entity UartCtrlRx is + port( + io_configFrame_dataLength : in unsigned(2 downto 0); + io_configFrame_stop : in UartStopType_seq_type; + io_configFrame_parity : in UartParityType_seq_type; + io_samplingTick : in std_logic; + io_read_valid : out std_logic; + io_read_ready : in std_logic; + io_read_payload : out std_logic_vector(7 downto 0); + io_rxd : in std_logic; + io_rts : out std_logic; + io_error : out std_logic; + io_break : out std_logic; + io_mainClk : in std_logic; + resetCtrl_systemReset : in std_logic + ); +end UartCtrlRx; + +architecture arch of UartCtrlRx is + signal io_rxd_buffercc_io_dataOut : std_logic; + + signal zz_io_rts : std_logic; + signal sampler_synchroniser : std_logic; + signal sampler_samples_0 : std_logic; + signal sampler_samples_1 : std_logic; + signal sampler_samples_2 : std_logic; + signal sampler_value : std_logic; + signal sampler_tick : std_logic; + signal bitTimer_counter : unsigned(2 downto 0); + signal bitTimer_tick : std_logic; + signal when_UartCtrlRx_l43 : std_logic; + signal bitCounter_value : unsigned(2 downto 0); + signal break_counter : unsigned(6 downto 0); + signal break_valid : std_logic; + signal when_UartCtrlRx_l69 : std_logic; + signal stateMachine_state : UartCtrlRxState; + signal stateMachine_parity : std_logic; + signal stateMachine_shifter : std_logic_vector(7 downto 0); + signal stateMachine_validReg : std_logic; + signal when_UartCtrlRx_l93 : std_logic; + signal when_UartCtrlRx_l103 : std_logic; + signal when_UartCtrlRx_l111 : std_logic; + signal when_UartCtrlRx_l113 : std_logic; + signal when_UartCtrlRx_l125 : std_logic; + signal when_UartCtrlRx_l136 : std_logic; + signal when_UartCtrlRx_l139 : std_logic; +begin + io_rxd_buffercc : entity work.BufferCC + port map ( + io_dataIn => io_rxd, + io_dataOut => io_rxd_buffercc_io_dataOut, + io_mainClk => io_mainClk, + resetCtrl_systemReset => resetCtrl_systemReset + ); + process(stateMachine_state,bitTimer_tick,when_UartCtrlRx_l125,when_UartCtrlRx_l136) + begin + io_error <= pkg_toStdLogic(false); + case stateMachine_state is + when pkg_enum.IDLE => + when pkg_enum.START => + when pkg_enum.DATA => + when pkg_enum.PARITY => + if bitTimer_tick = '1' then + if when_UartCtrlRx_l125 = '0' then + io_error <= pkg_toStdLogic(true); + end if; + end if; + when others => + if bitTimer_tick = '1' then + if when_UartCtrlRx_l136 = '1' then + io_error <= pkg_toStdLogic(true); + end if; + end if; + end case; + end process; + + io_rts <= zz_io_rts; + sampler_synchroniser <= io_rxd_buffercc_io_dataOut; + sampler_samples_0 <= sampler_synchroniser; + process(sampler_tick,when_UartCtrlRx_l43) + begin + bitTimer_tick <= pkg_toStdLogic(false); + if sampler_tick = '1' then + if when_UartCtrlRx_l43 = '1' then + bitTimer_tick <= pkg_toStdLogic(true); + end if; + end if; + end process; + + when_UartCtrlRx_l43 <= pkg_toStdLogic(bitTimer_counter = pkg_unsigned("000")); + break_valid <= pkg_toStdLogic(break_counter = pkg_unsigned("1000001")); + when_UartCtrlRx_l69 <= (io_samplingTick and (not break_valid)); + io_break <= break_valid; + io_read_valid <= stateMachine_validReg; + when_UartCtrlRx_l93 <= ((sampler_tick and (not sampler_value)) and (not break_valid)); + when_UartCtrlRx_l103 <= pkg_toStdLogic(sampler_value = pkg_toStdLogic(true)); + when_UartCtrlRx_l111 <= pkg_toStdLogic(bitCounter_value = io_configFrame_dataLength); + when_UartCtrlRx_l113 <= pkg_toStdLogic(io_configFrame_parity = UartParityType_seq_NONE); + when_UartCtrlRx_l125 <= pkg_toStdLogic(stateMachine_parity = sampler_value); + when_UartCtrlRx_l136 <= (not sampler_value); + when_UartCtrlRx_l139 <= pkg_toStdLogic(bitCounter_value = pkg_resize(pkg_mux(pkg_toStdLogic(io_configFrame_stop = UartStopType_seq_ONE),pkg_unsigned("0"),pkg_unsigned("1")),3)); + io_read_payload <= stateMachine_shifter; + process(io_mainClk, resetCtrl_systemReset) + begin + if resetCtrl_systemReset = '1' then + zz_io_rts <= pkg_toStdLogic(false); + sampler_samples_1 <= pkg_toStdLogic(true); + sampler_samples_2 <= pkg_toStdLogic(true); + sampler_value <= pkg_toStdLogic(true); + sampler_tick <= pkg_toStdLogic(false); + break_counter <= pkg_unsigned("0000000"); + stateMachine_state <= pkg_enum.IDLE; + stateMachine_validReg <= pkg_toStdLogic(false); + elsif rising_edge(io_mainClk) then + zz_io_rts <= (not io_read_ready); + if io_samplingTick = '1' then + sampler_samples_1 <= sampler_samples_0; + end if; + if io_samplingTick = '1' then + sampler_samples_2 <= sampler_samples_1; + end if; + sampler_value <= (((pkg_toStdLogic(false) or ((pkg_toStdLogic(true) and sampler_samples_0) and sampler_samples_1)) or ((pkg_toStdLogic(true) and sampler_samples_0) and sampler_samples_2)) or ((pkg_toStdLogic(true) and sampler_samples_1) and sampler_samples_2)); + sampler_tick <= io_samplingTick; + if sampler_value = '1' then + break_counter <= pkg_unsigned("0000000"); + else + if when_UartCtrlRx_l69 = '1' then + break_counter <= (break_counter + pkg_unsigned("0000001")); + end if; + end if; + stateMachine_validReg <= pkg_toStdLogic(false); + case stateMachine_state is + when pkg_enum.IDLE => + if when_UartCtrlRx_l93 = '1' then + stateMachine_state <= pkg_enum.START; + end if; + when pkg_enum.START => + if bitTimer_tick = '1' then + stateMachine_state <= pkg_enum.DATA; + if when_UartCtrlRx_l103 = '1' then + stateMachine_state <= pkg_enum.IDLE; + end if; + end if; + when pkg_enum.DATA => + if bitTimer_tick = '1' then + if when_UartCtrlRx_l111 = '1' then + if when_UartCtrlRx_l113 = '1' then + stateMachine_state <= pkg_enum.STOP; + stateMachine_validReg <= pkg_toStdLogic(true); + else + stateMachine_state <= pkg_enum.PARITY; + end if; + end if; + end if; + when pkg_enum.PARITY => + if bitTimer_tick = '1' then + if when_UartCtrlRx_l125 = '1' then + stateMachine_state <= pkg_enum.STOP; + stateMachine_validReg <= pkg_toStdLogic(true); + else + stateMachine_state <= pkg_enum.IDLE; + end if; + end if; + when others => + if bitTimer_tick = '1' then + if when_UartCtrlRx_l136 = '1' then + stateMachine_state <= pkg_enum.IDLE; + else + if when_UartCtrlRx_l139 = '1' then + stateMachine_state <= pkg_enum.IDLE; + end if; + end if; + end if; + end case; + end if; + end process; + + process(io_mainClk) + begin + if rising_edge(io_mainClk) then + if sampler_tick = '1' then + bitTimer_counter <= (bitTimer_counter - pkg_unsigned("001")); + if when_UartCtrlRx_l43 = '1' then + bitTimer_counter <= pkg_unsigned("100"); + end if; + end if; + if bitTimer_tick = '1' then + bitCounter_value <= (bitCounter_value + pkg_unsigned("001")); + end if; + if bitTimer_tick = '1' then + stateMachine_parity <= (stateMachine_parity xor sampler_value); + end if; + case stateMachine_state is + when pkg_enum.IDLE => + if when_UartCtrlRx_l93 = '1' then + bitTimer_counter <= pkg_unsigned("001"); + end if; + when pkg_enum.START => + if bitTimer_tick = '1' then + bitCounter_value <= pkg_unsigned("000"); + stateMachine_parity <= pkg_toStdLogic(io_configFrame_parity = UartParityType_seq_ODD); + end if; + when pkg_enum.DATA => + if bitTimer_tick = '1' then + stateMachine_shifter(to_integer(bitCounter_value)) <= sampler_value; + if when_UartCtrlRx_l111 = '1' then + bitCounter_value <= pkg_unsigned("000"); + end if; + end if; + when pkg_enum.PARITY => + if bitTimer_tick = '1' then + bitCounter_value <= pkg_unsigned("000"); + end if; + when others => + end case; + end if; + end process; + +end arch; + +library ieee; +use ieee.std_logic_1164.all; +use ieee.numeric_std.all; + +library work; +use work.pkg_scala2hdl.all; +use work.all; +use work.pkg_enum.all; + + +entity StreamFifoLowLatency is + port( + io_push_valid : in std_logic; + io_push_ready : out std_logic; + io_push_payload_error : in std_logic; + io_push_payload_inst : in std_logic_vector(31 downto 0); + io_pop_valid : out std_logic; + io_pop_ready : in std_logic; + io_pop_payload_error : out std_logic; + io_pop_payload_inst : out std_logic_vector(31 downto 0); + io_flush : in std_logic; + io_occupancy : out unsigned(0 downto 0); + io_mainClk : in std_logic; + resetCtrl_systemReset : in std_logic + ); +end StreamFifoLowLatency; + +architecture arch of StreamFifoLowLatency is + signal io_push_ready_read_buffer : std_logic; + signal io_pop_valid_read_buffer : std_logic; + + signal when_Phase_l649 : std_logic; + signal pushPtr_willIncrement : std_logic; + signal pushPtr_willClear : std_logic; + signal pushPtr_willOverflowIfInc : std_logic; + signal pushPtr_willOverflow : std_logic; + signal popPtr_willIncrement : std_logic; + signal popPtr_willClear : std_logic; + signal popPtr_willOverflowIfInc : std_logic; + signal popPtr_willOverflow : std_logic; + signal ptrMatch : std_logic; + signal risingOccupancy : std_logic; + signal empty : std_logic; + signal full : std_logic; + signal pushing : std_logic; + signal popping : std_logic; + signal readed_error : std_logic; + signal readed_inst : std_logic_vector(31 downto 0); + signal zz_readed_error : std_logic_vector(32 downto 0); + signal when_Stream_l1178 : std_logic; + signal when_Stream_l1191 : std_logic; + signal zz_readed_error_1 : std_logic_vector(32 downto 0); + signal zz_readed_error_2 : std_logic_vector(32 downto 0); +begin + io_push_ready <= io_push_ready_read_buffer; + io_pop_valid <= io_pop_valid_read_buffer; + process(pushing) + begin + when_Phase_l649 <= pkg_toStdLogic(false); + if pushing = '1' then + when_Phase_l649 <= pkg_toStdLogic(true); + end if; + end process; + + process(pushing) + begin + pushPtr_willIncrement <= pkg_toStdLogic(false); + if pushing = '1' then + pushPtr_willIncrement <= pkg_toStdLogic(true); + end if; + end process; + + process(io_flush) + begin + pushPtr_willClear <= pkg_toStdLogic(false); + if io_flush = '1' then + pushPtr_willClear <= pkg_toStdLogic(true); + end if; + end process; + + pushPtr_willOverflowIfInc <= pkg_toStdLogic(true); + pushPtr_willOverflow <= (pushPtr_willOverflowIfInc and pushPtr_willIncrement); + process(popping) + begin + popPtr_willIncrement <= pkg_toStdLogic(false); + if popping = '1' then + popPtr_willIncrement <= pkg_toStdLogic(true); + end if; + end process; + + process(io_flush) + begin + popPtr_willClear <= pkg_toStdLogic(false); + if io_flush = '1' then + popPtr_willClear <= pkg_toStdLogic(true); + end if; + end process; + + popPtr_willOverflowIfInc <= pkg_toStdLogic(true); + popPtr_willOverflow <= (popPtr_willOverflowIfInc and popPtr_willIncrement); + ptrMatch <= pkg_toStdLogic(true); + empty <= (ptrMatch and (not risingOccupancy)); + full <= (ptrMatch and risingOccupancy); + pushing <= (io_push_valid and io_push_ready_read_buffer); + popping <= (io_pop_valid_read_buffer and io_pop_ready); + io_push_ready_read_buffer <= (not full); + zz_readed_error <= zz_readed_error_1; + readed_error <= pkg_extract(zz_readed_error,0); + readed_inst <= pkg_extract(zz_readed_error,32,1); + when_Stream_l1178 <= (not empty); + process(when_Stream_l1178,io_push_valid) + begin + if when_Stream_l1178 = '1' then + io_pop_valid_read_buffer <= pkg_toStdLogic(true); + else + io_pop_valid_read_buffer <= io_push_valid; + end if; + end process; + + process(when_Stream_l1178,readed_error,io_push_payload_error) + begin + if when_Stream_l1178 = '1' then + io_pop_payload_error <= readed_error; + else + io_pop_payload_error <= io_push_payload_error; + end if; + end process; + + process(when_Stream_l1178,readed_inst,io_push_payload_inst) + begin + if when_Stream_l1178 = '1' then + io_pop_payload_inst <= readed_inst; + else + io_pop_payload_inst <= io_push_payload_inst; + end if; + end process; + + when_Stream_l1191 <= pkg_toStdLogic(pushing /= popping); + io_occupancy <= unsigned(pkg_toStdLogicVector((risingOccupancy and ptrMatch))); + zz_readed_error_1 <= zz_readed_error_2; + process(io_mainClk, resetCtrl_systemReset) + begin + if resetCtrl_systemReset = '1' then + risingOccupancy <= pkg_toStdLogic(false); + elsif rising_edge(io_mainClk) then + if when_Stream_l1191 = '1' then + risingOccupancy <= pushing; + end if; + if io_flush = '1' then + risingOccupancy <= pkg_toStdLogic(false); + end if; + end if; + end process; + + process(io_mainClk) + begin + if rising_edge(io_mainClk) then + if when_Phase_l649 = '1' then + zz_readed_error_2 <= pkg_cat(io_push_payload_inst,pkg_toStdLogicVector(io_push_payload_error)); + end if; + end if; + end process; + +end arch; + +library ieee; +use ieee.std_logic_1164.all; +use ieee.numeric_std.all; + +library work; +use work.pkg_scala2hdl.all; +use work.all; +use work.pkg_enum.all; + + +entity FlowCCByToggle is + port( + io_input_valid : in std_logic; + io_input_payload_last : in std_logic; + io_input_payload_fragment : in std_logic_vector(0 downto 0); + io_output_valid : out std_logic; + io_output_payload_last : out std_logic; + io_output_payload_fragment : out std_logic_vector(0 downto 0); + io_jtag_tck : in std_logic; + io_mainClk : in std_logic; + resetCtrl_mainClkReset : in std_logic + ); +end FlowCCByToggle; + +architecture arch of FlowCCByToggle is + signal inputArea_target_buffercc_io_dataOut : std_logic; + + signal inputArea_target : std_logic := '0'; + signal inputArea_data_last : std_logic; + signal inputArea_data_fragment : std_logic_vector(0 downto 0); + signal outputArea_target : std_logic; + signal outputArea_hit : std_logic := '0'; + signal outputArea_flow_valid : std_logic; + signal outputArea_flow_payload_last : std_logic; + signal outputArea_flow_payload_fragment : std_logic_vector(0 downto 0); + signal outputArea_flow_m2sPipe_valid : std_logic; + signal outputArea_flow_m2sPipe_payload_last : std_logic; + signal outputArea_flow_m2sPipe_payload_fragment : std_logic_vector(0 downto 0); +begin + inputArea_target_buffercc : entity work.BufferCC_1 + port map ( + io_dataIn => inputArea_target, + io_dataOut => inputArea_target_buffercc_io_dataOut, + io_mainClk => io_mainClk, + resetCtrl_mainClkReset => resetCtrl_mainClkReset + ); + outputArea_target <= inputArea_target_buffercc_io_dataOut; + outputArea_flow_valid <= pkg_toStdLogic(outputArea_target /= outputArea_hit); + outputArea_flow_payload_last <= inputArea_data_last; + outputArea_flow_payload_fragment <= inputArea_data_fragment; + io_output_valid <= outputArea_flow_m2sPipe_valid; + io_output_payload_last <= outputArea_flow_m2sPipe_payload_last; + io_output_payload_fragment <= outputArea_flow_m2sPipe_payload_fragment; + process(io_jtag_tck) + begin + if rising_edge(io_jtag_tck) then + if io_input_valid = '1' then + inputArea_target <= (not inputArea_target); + inputArea_data_last <= io_input_payload_last; + inputArea_data_fragment <= io_input_payload_fragment; + end if; + end if; + end process; + + process(io_mainClk) + begin + if rising_edge(io_mainClk) then + outputArea_hit <= outputArea_target; + if outputArea_flow_valid = '1' then + outputArea_flow_m2sPipe_payload_last <= outputArea_flow_payload_last; + outputArea_flow_m2sPipe_payload_fragment <= outputArea_flow_payload_fragment; + end if; + end if; + end process; + + process(io_mainClk, resetCtrl_mainClkReset) + begin + if resetCtrl_mainClkReset = '1' then + outputArea_flow_m2sPipe_valid <= pkg_toStdLogic(false); + elsif rising_edge(io_mainClk) then + outputArea_flow_m2sPipe_valid <= outputArea_flow_valid; + end if; + end process; + +end arch; + +library ieee; +use ieee.std_logic_1164.all; +use ieee.numeric_std.all; + +library work; +use work.pkg_scala2hdl.all; +use work.all; +use work.pkg_enum.all; + + +entity BufferCC_2 is + port( + io_dataIn : in std_logic_vector(31 downto 0); + io_dataOut : out std_logic_vector(31 downto 0); + io_mainClk : in std_logic; + resetCtrl_systemReset : in std_logic + ); +end BufferCC_2; + +architecture arch of BufferCC_2 is + attribute async_reg : string; + + signal buffers_0 : std_logic_vector(31 downto 0); + attribute async_reg of buffers_0 : signal is "true"; + signal buffers_1 : std_logic_vector(31 downto 0); + attribute async_reg of buffers_1 : signal is "true"; +begin + io_dataOut <= buffers_1; + process(io_mainClk) + begin + if rising_edge(io_mainClk) then + buffers_0 <= io_dataIn; + buffers_1 <= buffers_0; + end if; + end process; + +end arch; + +library ieee; +use ieee.std_logic_1164.all; +use ieee.numeric_std.all; + +library work; +use work.pkg_scala2hdl.all; +use work.all; +use work.pkg_enum.all; + + +entity UartCtrl is + port( + io_config_frame_dataLength : in unsigned(2 downto 0); + io_config_frame_stop : in UartStopType_seq_type; + io_config_frame_parity : in UartParityType_seq_type; + io_config_clockDivider : in unsigned(19 downto 0); + io_write_valid : in std_logic; + io_write_ready : out std_logic; + io_write_payload : in std_logic_vector(7 downto 0); + io_read_valid : out std_logic; + io_read_ready : in std_logic; + io_read_payload : out std_logic_vector(7 downto 0); + io_uart_txd : out std_logic; + io_uart_rxd : in std_logic; + io_readError : out std_logic; + io_writeBreak : in std_logic; + io_readBreak : out std_logic; + io_mainClk : in std_logic; + resetCtrl_systemReset : in std_logic + ); +end UartCtrl; + +architecture arch of UartCtrl is + signal tx_io_write_ready : std_logic; + signal tx_io_txd : std_logic; + signal rx_io_read_valid : std_logic; + signal rx_io_read_payload : std_logic_vector(7 downto 0); + signal rx_io_rts : std_logic; + signal rx_io_error : std_logic; + signal rx_io_break : std_logic; + + signal clockDivider_counter : unsigned(19 downto 0); + signal clockDivider_tick : std_logic; + signal clockDivider_tickReg : std_logic; + signal io_write_thrown_valid : std_logic; + signal io_write_thrown_ready : std_logic; + signal io_write_thrown_payload : std_logic_vector(7 downto 0); +begin + tx : entity work.UartCtrlTx + port map ( + io_configFrame_dataLength => io_config_frame_dataLength, + io_configFrame_stop => io_config_frame_stop, + io_configFrame_parity => io_config_frame_parity, + io_samplingTick => clockDivider_tickReg, + io_write_valid => io_write_thrown_valid, + io_write_ready => tx_io_write_ready, + io_write_payload => io_write_thrown_payload, + io_cts => pkg_toStdLogic(false), + io_txd => tx_io_txd, + io_break => io_writeBreak, + io_mainClk => io_mainClk, + resetCtrl_systemReset => resetCtrl_systemReset + ); + rx : entity work.UartCtrlRx + port map ( + io_configFrame_dataLength => io_config_frame_dataLength, + io_configFrame_stop => io_config_frame_stop, + io_configFrame_parity => io_config_frame_parity, + io_samplingTick => clockDivider_tickReg, + io_read_valid => rx_io_read_valid, + io_read_ready => io_read_ready, + io_read_payload => rx_io_read_payload, + io_rxd => io_uart_rxd, + io_rts => rx_io_rts, + io_error => rx_io_error, + io_break => rx_io_break, + io_mainClk => io_mainClk, + resetCtrl_systemReset => resetCtrl_systemReset + ); + clockDivider_tick <= pkg_toStdLogic(clockDivider_counter = pkg_unsigned("00000000000000000000")); + process(io_write_valid,rx_io_break) + begin + io_write_thrown_valid <= io_write_valid; + if rx_io_break = '1' then + io_write_thrown_valid <= pkg_toStdLogic(false); + end if; + end process; + + process(io_write_thrown_ready,rx_io_break) + begin + io_write_ready <= io_write_thrown_ready; + if rx_io_break = '1' then + io_write_ready <= pkg_toStdLogic(true); + end if; + end process; + + io_write_thrown_payload <= io_write_payload; + io_write_thrown_ready <= tx_io_write_ready; + io_read_valid <= rx_io_read_valid; + io_read_payload <= rx_io_read_payload; + io_uart_txd <= tx_io_txd; + io_readError <= rx_io_error; + io_readBreak <= rx_io_break; + process(io_mainClk, resetCtrl_systemReset) + begin + if resetCtrl_systemReset = '1' then + clockDivider_counter <= pkg_unsigned("00000000000000000000"); + clockDivider_tickReg <= pkg_toStdLogic(false); + elsif rising_edge(io_mainClk) then + clockDivider_tickReg <= clockDivider_tick; + clockDivider_counter <= (clockDivider_counter - pkg_unsigned("00000000000000000001")); + if clockDivider_tick = '1' then + clockDivider_counter <= io_config_clockDivider; + end if; + end if; + end process; + +end arch; + +library ieee; +use ieee.std_logic_1164.all; +use ieee.numeric_std.all; + +library work; +use work.pkg_scala2hdl.all; +use work.all; +use work.pkg_enum.all; + + +entity StreamFifo is + port( + io_push_valid : in std_logic; + io_push_ready : out std_logic; + io_push_payload : in std_logic_vector(7 downto 0); + io_pop_valid : out std_logic; + io_pop_ready : in std_logic; + io_pop_payload : out std_logic_vector(7 downto 0); + io_flush : in std_logic; + io_occupancy : out unsigned(4 downto 0); + io_availability : out unsigned(4 downto 0); + io_mainClk : in std_logic; + resetCtrl_systemReset : in std_logic + ); +end StreamFifo; + +architecture arch of StreamFifo is + signal zz_logic_ram_port0 : std_logic_vector(7 downto 0); + signal io_push_ready_read_buffer : std_logic; + signal io_pop_valid_read_buffer : std_logic; + signal zz_logic_ram_port : std_logic; + signal zz_io_pop_payload : std_logic; + + signal zz_1 : std_logic; + signal logic_pushPtr_willIncrement : std_logic; + signal logic_pushPtr_willClear : std_logic; + signal logic_pushPtr_valueNext : unsigned(3 downto 0); + signal logic_pushPtr_value : unsigned(3 downto 0); + signal logic_pushPtr_willOverflowIfInc : std_logic; + signal logic_pushPtr_willOverflow : std_logic; + signal logic_popPtr_willIncrement : std_logic; + signal logic_popPtr_willClear : std_logic; + signal logic_popPtr_valueNext : unsigned(3 downto 0); + signal logic_popPtr_value : unsigned(3 downto 0); + signal logic_popPtr_willOverflowIfInc : std_logic; + signal logic_popPtr_willOverflow : std_logic; + signal logic_ptrMatch : std_logic; + signal logic_risingOccupancy : std_logic; + signal logic_pushing : std_logic; + signal logic_popping : std_logic; + signal logic_empty : std_logic; + signal logic_full : std_logic; + signal zz_io_pop_valid : std_logic; + signal when_Stream_l1078 : std_logic; + signal logic_ptrDif : unsigned(3 downto 0); + type logic_ram_type is array (0 to 15) of std_logic_vector(7 downto 0); + signal logic_ram : logic_ram_type; +begin + io_push_ready <= io_push_ready_read_buffer; + io_pop_valid <= io_pop_valid_read_buffer; + zz_io_pop_payload <= pkg_toStdLogic(true); + process(io_mainClk) + begin + if rising_edge(io_mainClk) then + if zz_io_pop_payload = '1' then + zz_logic_ram_port0 <= logic_ram(to_integer(logic_popPtr_valueNext)); + end if; + end if; + end process; + + process(io_mainClk) + begin + if rising_edge(io_mainClk) then + if zz_1 = '1' then + logic_ram(to_integer(logic_pushPtr_value)) <= io_push_payload; + end if; + end if; + end process; + + process(logic_pushing) + begin + zz_1 <= pkg_toStdLogic(false); + if logic_pushing = '1' then + zz_1 <= pkg_toStdLogic(true); + end if; + end process; + + process(logic_pushing) + begin + logic_pushPtr_willIncrement <= pkg_toStdLogic(false); + if logic_pushing = '1' then + logic_pushPtr_willIncrement <= pkg_toStdLogic(true); + end if; + end process; + + process(io_flush) + begin + logic_pushPtr_willClear <= pkg_toStdLogic(false); + if io_flush = '1' then + logic_pushPtr_willClear <= pkg_toStdLogic(true); + end if; + end process; + + logic_pushPtr_willOverflowIfInc <= pkg_toStdLogic(logic_pushPtr_value = pkg_unsigned("1111")); + logic_pushPtr_willOverflow <= (logic_pushPtr_willOverflowIfInc and logic_pushPtr_willIncrement); + process(logic_pushPtr_value,logic_pushPtr_willIncrement,logic_pushPtr_willClear) + begin + logic_pushPtr_valueNext <= (logic_pushPtr_value + pkg_resize(unsigned(pkg_toStdLogicVector(logic_pushPtr_willIncrement)),4)); + if logic_pushPtr_willClear = '1' then + logic_pushPtr_valueNext <= pkg_unsigned("0000"); + end if; + end process; + + process(logic_popping) + begin + logic_popPtr_willIncrement <= pkg_toStdLogic(false); + if logic_popping = '1' then + logic_popPtr_willIncrement <= pkg_toStdLogic(true); + end if; + end process; + + process(io_flush) + begin + logic_popPtr_willClear <= pkg_toStdLogic(false); + if io_flush = '1' then + logic_popPtr_willClear <= pkg_toStdLogic(true); + end if; + end process; + + logic_popPtr_willOverflowIfInc <= pkg_toStdLogic(logic_popPtr_value = pkg_unsigned("1111")); + logic_popPtr_willOverflow <= (logic_popPtr_willOverflowIfInc and logic_popPtr_willIncrement); + process(logic_popPtr_value,logic_popPtr_willIncrement,logic_popPtr_willClear) + begin + logic_popPtr_valueNext <= (logic_popPtr_value + pkg_resize(unsigned(pkg_toStdLogicVector(logic_popPtr_willIncrement)),4)); + if logic_popPtr_willClear = '1' then + logic_popPtr_valueNext <= pkg_unsigned("0000"); + end if; + end process; + + logic_ptrMatch <= pkg_toStdLogic(logic_pushPtr_value = logic_popPtr_value); + logic_pushing <= (io_push_valid and io_push_ready_read_buffer); + logic_popping <= (io_pop_valid_read_buffer and io_pop_ready); + logic_empty <= (logic_ptrMatch and (not logic_risingOccupancy)); + logic_full <= (logic_ptrMatch and logic_risingOccupancy); + io_push_ready_read_buffer <= (not logic_full); + io_pop_valid_read_buffer <= ((not logic_empty) and (not (zz_io_pop_valid and (not logic_full)))); + io_pop_payload <= zz_logic_ram_port0; + when_Stream_l1078 <= pkg_toStdLogic(logic_pushing /= logic_popping); + logic_ptrDif <= (logic_pushPtr_value - logic_popPtr_value); + io_occupancy <= unsigned(pkg_cat(pkg_toStdLogicVector((logic_risingOccupancy and logic_ptrMatch)),std_logic_vector(logic_ptrDif))); + io_availability <= unsigned(pkg_cat(pkg_toStdLogicVector(((not logic_risingOccupancy) and logic_ptrMatch)),std_logic_vector((logic_popPtr_value - logic_pushPtr_value)))); + process(io_mainClk, resetCtrl_systemReset) + begin + if resetCtrl_systemReset = '1' then + logic_pushPtr_value <= pkg_unsigned("0000"); + logic_popPtr_value <= pkg_unsigned("0000"); + logic_risingOccupancy <= pkg_toStdLogic(false); + zz_io_pop_valid <= pkg_toStdLogic(false); + elsif rising_edge(io_mainClk) then + logic_pushPtr_value <= logic_pushPtr_valueNext; + logic_popPtr_value <= logic_popPtr_valueNext; + zz_io_pop_valid <= pkg_toStdLogic(logic_popPtr_valueNext = logic_pushPtr_value); + if when_Stream_l1078 = '1' then + logic_risingOccupancy <= logic_pushing; + end if; + if io_flush = '1' then + logic_risingOccupancy <= pkg_toStdLogic(false); + end if; + end if; + end process; + +end arch; + + +--StreamFifo_1 replaced by StreamFifo + +library ieee; +use ieee.std_logic_1164.all; +use ieee.numeric_std.all; + +library work; +use work.pkg_scala2hdl.all; +use work.all; +use work.pkg_enum.all; + + +entity Prescaler is + port( + io_clear : in std_logic; + io_limit : in unsigned(15 downto 0); + io_overflow : out std_logic; + io_mainClk : in std_logic; + resetCtrl_systemReset : in std_logic + ); +end Prescaler; + +architecture arch of Prescaler is + signal io_overflow_read_buffer : std_logic; + + signal counter : unsigned(15 downto 0); + signal when_Prescaler_l17 : std_logic; +begin + io_overflow <= io_overflow_read_buffer; + when_Prescaler_l17 <= (io_clear or io_overflow_read_buffer); + io_overflow_read_buffer <= pkg_toStdLogic(counter = io_limit); + process(io_mainClk) + begin + if rising_edge(io_mainClk) then + counter <= (counter + pkg_unsigned("0000000000000001")); + if when_Prescaler_l17 = '1' then + counter <= pkg_unsigned("0000000000000000"); + end if; + end if; + end process; + +end arch; + +library ieee; +use ieee.std_logic_1164.all; +use ieee.numeric_std.all; + +library work; +use work.pkg_scala2hdl.all; +use work.all; +use work.pkg_enum.all; + + +entity Timer is + port( + io_tick : in std_logic; + io_clear : in std_logic; + io_limit : in unsigned(15 downto 0); + io_full : out std_logic; + io_value : out unsigned(15 downto 0); + io_mainClk : in std_logic; + resetCtrl_systemReset : in std_logic + ); +end Timer; + +architecture arch of Timer is + + signal counter : unsigned(15 downto 0); + signal limitHit : std_logic; + signal inhibitFull : std_logic; +begin + limitHit <= pkg_toStdLogic(counter = io_limit); + io_full <= ((limitHit and io_tick) and (not inhibitFull)); + io_value <= counter; + process(io_mainClk, resetCtrl_systemReset) + begin + if resetCtrl_systemReset = '1' then + inhibitFull <= pkg_toStdLogic(false); + elsif rising_edge(io_mainClk) then + if io_tick = '1' then + inhibitFull <= limitHit; + end if; + if io_clear = '1' then + inhibitFull <= pkg_toStdLogic(false); + end if; + end if; + end process; + + process(io_mainClk) + begin + if rising_edge(io_mainClk) then + if io_tick = '1' then + counter <= (counter + pkg_resize(unsigned(pkg_toStdLogicVector((not limitHit))),16)); + end if; + if io_clear = '1' then + counter <= pkg_unsigned("0000000000000000"); + end if; + end if; + end process; + +end arch; + + +--Timer_1 replaced by Timer + +library ieee; +use ieee.std_logic_1164.all; +use ieee.numeric_std.all; + +library work; +use work.pkg_scala2hdl.all; +use work.all; +use work.pkg_enum.all; + + +entity InterruptCtrl is + port( + io_inputs : in std_logic_vector(1 downto 0); + io_clears : in std_logic_vector(1 downto 0); + io_masks : in std_logic_vector(1 downto 0); + io_pendings : out std_logic_vector(1 downto 0); + io_mainClk : in std_logic; + resetCtrl_systemReset : in std_logic + ); +end InterruptCtrl; + +architecture arch of InterruptCtrl is + + signal pendings : std_logic_vector(1 downto 0); +begin + io_pendings <= (pendings and io_masks); + process(io_mainClk, resetCtrl_systemReset) + begin + if resetCtrl_systemReset = '1' then + pendings <= pkg_stdLogicVector("00"); + elsif rising_edge(io_mainClk) then + pendings <= ((pendings and pkg_not(io_clears)) or io_inputs); + end if; + end process; + +end arch; + +library ieee; +use ieee.std_logic_1164.all; +use ieee.numeric_std.all; + +library work; +use work.pkg_scala2hdl.all; +use work.all; +use work.pkg_enum.all; + + +entity BufferCC_3 is + port( + io_dataIn : in std_logic; + io_dataOut : out std_logic; + io_mainClk : in std_logic + ); +end BufferCC_3; + +architecture arch of BufferCC_3 is + attribute async_reg : string; + + signal buffers_0 : std_logic; + attribute async_reg of buffers_0 : signal is "true"; + signal buffers_1 : std_logic; + attribute async_reg of buffers_1 : signal is "true"; +begin + io_dataOut <= buffers_1; + process(io_mainClk) + begin + if rising_edge(io_mainClk) then + buffers_0 <= io_dataIn; + buffers_1 <= buffers_0; + end if; + end process; + +end arch; + +library ieee; +use ieee.std_logic_1164.all; +use ieee.numeric_std.all; + +library work; +use work.pkg_scala2hdl.all; +use work.all; +use work.pkg_enum.all; + + +entity MuraxMasterArbiter is + port( + io_iBus_cmd_valid : in std_logic; + io_iBus_cmd_ready : out std_logic; + io_iBus_cmd_payload_pc : in unsigned(31 downto 0); + io_iBus_rsp_valid : out std_logic; + io_iBus_rsp_payload_error : out std_logic; + io_iBus_rsp_payload_inst : out std_logic_vector(31 downto 0); + io_dBus_cmd_valid : in std_logic; + io_dBus_cmd_ready : out std_logic; + io_dBus_cmd_payload_wr : in std_logic; + io_dBus_cmd_payload_address : in unsigned(31 downto 0); + io_dBus_cmd_payload_data : in std_logic_vector(31 downto 0); + io_dBus_cmd_payload_size : in unsigned(1 downto 0); + io_dBus_rsp_ready : out std_logic; + io_dBus_rsp_error : out std_logic; + io_dBus_rsp_data : out std_logic_vector(31 downto 0); + io_masterBus_cmd_valid : out std_logic; + io_masterBus_cmd_ready : in std_logic; + io_masterBus_cmd_payload_write : out std_logic; + io_masterBus_cmd_payload_address : out unsigned(31 downto 0); + io_masterBus_cmd_payload_data : out std_logic_vector(31 downto 0); + io_masterBus_cmd_payload_mask : out std_logic_vector(3 downto 0); + io_masterBus_rsp_valid : in std_logic; + io_masterBus_rsp_payload_data : in std_logic_vector(31 downto 0); + io_mainClk : in std_logic; + resetCtrl_systemReset : in std_logic + ); +end MuraxMasterArbiter; + +architecture arch of MuraxMasterArbiter is + signal io_masterBus_cmd_valid_read_buffer : std_logic; + signal io_masterBus_cmd_payload_write_read_buffer : std_logic; + + signal zz_io_masterBus_cmd_payload_mask : std_logic_vector(3 downto 0); + signal rspPending : std_logic; + signal rspTarget : std_logic; + signal io_masterBus_cmd_fire : std_logic; + signal when_MuraxUtiles_l31 : std_logic; + signal when_MuraxUtiles_l36 : std_logic; +begin + io_masterBus_cmd_valid <= io_masterBus_cmd_valid_read_buffer; + io_masterBus_cmd_payload_write <= io_masterBus_cmd_payload_write_read_buffer; + process(io_iBus_cmd_valid,io_dBus_cmd_valid,when_MuraxUtiles_l36) + begin + io_masterBus_cmd_valid_read_buffer <= (io_iBus_cmd_valid or io_dBus_cmd_valid); + if when_MuraxUtiles_l36 = '1' then + io_masterBus_cmd_valid_read_buffer <= pkg_toStdLogic(false); + end if; + end process; + + io_masterBus_cmd_payload_write_read_buffer <= (io_dBus_cmd_valid and io_dBus_cmd_payload_wr); + io_masterBus_cmd_payload_address <= pkg_mux(io_dBus_cmd_valid,io_dBus_cmd_payload_address,io_iBus_cmd_payload_pc); + io_masterBus_cmd_payload_data <= io_dBus_cmd_payload_data; + process(io_dBus_cmd_payload_size) + begin + case io_dBus_cmd_payload_size is + when "00" => + zz_io_masterBus_cmd_payload_mask <= pkg_stdLogicVector("0001"); + when "01" => + zz_io_masterBus_cmd_payload_mask <= pkg_stdLogicVector("0011"); + when others => + zz_io_masterBus_cmd_payload_mask <= pkg_stdLogicVector("1111"); + end case; + end process; + + io_masterBus_cmd_payload_mask <= std_logic_vector(shift_left(unsigned(zz_io_masterBus_cmd_payload_mask),to_integer(pkg_extract(io_dBus_cmd_payload_address,1,0)))); + process(io_masterBus_cmd_ready,io_dBus_cmd_valid,when_MuraxUtiles_l36) + begin + io_iBus_cmd_ready <= (io_masterBus_cmd_ready and (not io_dBus_cmd_valid)); + if when_MuraxUtiles_l36 = '1' then + io_iBus_cmd_ready <= pkg_toStdLogic(false); + end if; + end process; + + process(io_masterBus_cmd_ready,when_MuraxUtiles_l36) + begin + io_dBus_cmd_ready <= io_masterBus_cmd_ready; + if when_MuraxUtiles_l36 = '1' then + io_dBus_cmd_ready <= pkg_toStdLogic(false); + end if; + end process; + + io_masterBus_cmd_fire <= (io_masterBus_cmd_valid_read_buffer and io_masterBus_cmd_ready); + when_MuraxUtiles_l31 <= (io_masterBus_cmd_fire and (not io_masterBus_cmd_payload_write_read_buffer)); + when_MuraxUtiles_l36 <= (rspPending and (not io_masterBus_rsp_valid)); + io_iBus_rsp_valid <= (io_masterBus_rsp_valid and (not rspTarget)); + io_iBus_rsp_payload_inst <= io_masterBus_rsp_payload_data; + io_iBus_rsp_payload_error <= pkg_toStdLogic(false); + io_dBus_rsp_ready <= (io_masterBus_rsp_valid and rspTarget); + io_dBus_rsp_data <= io_masterBus_rsp_payload_data; + io_dBus_rsp_error <= pkg_toStdLogic(false); + process(io_mainClk, resetCtrl_systemReset) + begin + if resetCtrl_systemReset = '1' then + rspPending <= pkg_toStdLogic(false); + rspTarget <= pkg_toStdLogic(false); + elsif rising_edge(io_mainClk) then + if io_masterBus_rsp_valid = '1' then + rspPending <= pkg_toStdLogic(false); + end if; + if when_MuraxUtiles_l31 = '1' then + rspTarget <= io_dBus_cmd_valid; + rspPending <= pkg_toStdLogic(true); + end if; + end if; + end process; + +end arch; + +library ieee; +use ieee.std_logic_1164.all; +use ieee.numeric_std.all; + +library work; +use work.pkg_scala2hdl.all; +use work.all; +use work.pkg_enum.all; + + +entity VexRiscv is + port( + iBus_cmd_valid : out std_logic; + iBus_cmd_ready : in std_logic; + iBus_cmd_payload_pc : out unsigned(31 downto 0); + iBus_rsp_valid : in std_logic; + iBus_rsp_payload_error : in std_logic; + iBus_rsp_payload_inst : in std_logic_vector(31 downto 0); + timerInterrupt : in std_logic; + externalInterrupt : in std_logic; + softwareInterrupt : in std_logic; + debug_bus_cmd_valid : in std_logic; + debug_bus_cmd_ready : out std_logic; + debug_bus_cmd_payload_wr : in std_logic; + debug_bus_cmd_payload_address : in unsigned(7 downto 0); + debug_bus_cmd_payload_data : in std_logic_vector(31 downto 0); + debug_bus_rsp_data : out std_logic_vector(31 downto 0); + debug_resetOut : out std_logic; + dBus_cmd_valid : out std_logic; + dBus_cmd_ready : in std_logic; + dBus_cmd_payload_wr : out std_logic; + dBus_cmd_payload_address : out unsigned(31 downto 0); + dBus_cmd_payload_data : out std_logic_vector(31 downto 0); + dBus_cmd_payload_size : out unsigned(1 downto 0); + dBus_rsp_ready : in std_logic; + dBus_rsp_error : in std_logic; + dBus_rsp_data : in std_logic_vector(31 downto 0); + io_mainClk : in std_logic; + resetCtrl_systemReset : in std_logic; + resetCtrl_mainClkReset : in std_logic + ); +end VexRiscv; + +architecture arch of VexRiscv is + signal IBusSimplePlugin_rspJoin_rspBuffer_c_io_pop_ready : std_logic; + signal zz_RegFilePlugin_regFile_port0 : std_logic_vector(31 downto 0); + signal zz_RegFilePlugin_regFile_port0_1 : std_logic_vector(31 downto 0); + signal dBus_cmd_payload_address_read_buffer : unsigned(31 downto 0); + signal dBus_cmd_payload_size_read_buffer : unsigned(1 downto 0); + signal debug_bus_cmd_ready_read_buffer : std_logic; + signal IBusSimplePlugin_rspJoin_rspBuffer_c_io_push_ready : std_logic; + signal IBusSimplePlugin_rspJoin_rspBuffer_c_io_pop_valid : std_logic; + signal IBusSimplePlugin_rspJoin_rspBuffer_c_io_pop_payload_error : std_logic; + signal IBusSimplePlugin_rspJoin_rspBuffer_c_io_pop_payload_inst : std_logic_vector(31 downto 0); + signal IBusSimplePlugin_rspJoin_rspBuffer_c_io_occupancy : unsigned(0 downto 0); + signal zz_zz_decode_BRANCH_CTRL_2 : std_logic_vector(31 downto 0); + signal zz_zz_decode_BRANCH_CTRL_2_1 : std_logic; + signal zz_zz_decode_BRANCH_CTRL_2_2 : std_logic; + signal zz_zz_decode_BRANCH_CTRL_2_3 : std_logic_vector(0 downto 0); + signal zz_zz_decode_BRANCH_CTRL_2_4 : std_logic_vector(0 downto 0); + signal zz_zz_decode_BRANCH_CTRL_2_5 : std_logic; + signal zz_zz_decode_BRANCH_CTRL_2_6 : std_logic_vector(31 downto 0); + signal zz_zz_decode_BRANCH_CTRL_2_7 : std_logic_vector(31 downto 0); + signal zz_zz_decode_BRANCH_CTRL_2_8 : std_logic_vector(31 downto 0); + signal zz_zz_decode_BRANCH_CTRL_2_9 : std_logic_vector(31 downto 0); + signal zz_zz_decode_BRANCH_CTRL_2_10 : std_logic_vector(0 downto 0); + signal zz_zz_decode_BRANCH_CTRL_2_11 : std_logic; + signal zz_zz_decode_BRANCH_CTRL_2_12 : std_logic; + signal zz_zz_decode_BRANCH_CTRL_2_13 : std_logic_vector(19 downto 0); + signal zz_zz_decode_BRANCH_CTRL_2_14 : std_logic; + signal zz_zz_decode_BRANCH_CTRL_2_15 : std_logic_vector(0 downto 0); + signal zz_zz_decode_BRANCH_CTRL_2_16 : std_logic_vector(31 downto 0); + signal zz_zz_decode_BRANCH_CTRL_2_17 : std_logic_vector(0 downto 0); + signal zz_zz_decode_BRANCH_CTRL_2_18 : std_logic; + signal zz_zz_decode_BRANCH_CTRL_2_19 : std_logic; + signal zz_zz_decode_BRANCH_CTRL_2_20 : std_logic; + signal zz_zz_decode_BRANCH_CTRL_2_21 : std_logic_vector(0 downto 0); + signal zz_zz_decode_BRANCH_CTRL_2_22 : std_logic_vector(0 downto 0); + signal zz_zz_decode_BRANCH_CTRL_2_23 : std_logic_vector(31 downto 0); + signal zz_zz_decode_BRANCH_CTRL_2_24 : std_logic_vector(0 downto 0); + signal zz_zz_decode_BRANCH_CTRL_2_25 : std_logic_vector(31 downto 0); + signal zz_zz_decode_BRANCH_CTRL_2_26 : std_logic_vector(15 downto 0); + signal zz_zz_decode_BRANCH_CTRL_2_27 : std_logic_vector(0 downto 0); + signal zz_zz_decode_BRANCH_CTRL_2_28 : std_logic_vector(0 downto 0); + signal zz_zz_decode_BRANCH_CTRL_2_29 : std_logic; + signal zz_zz_decode_BRANCH_CTRL_2_30 : std_logic_vector(31 downto 0); + signal zz_zz_decode_BRANCH_CTRL_2_31 : std_logic_vector(31 downto 0); + signal zz_zz_decode_BRANCH_CTRL_2_32 : std_logic_vector(0 downto 0); + signal zz_zz_decode_BRANCH_CTRL_2_33 : std_logic_vector(0 downto 0); + signal zz_zz_decode_BRANCH_CTRL_2_34 : std_logic_vector(31 downto 0); + signal zz_zz_decode_BRANCH_CTRL_2_35 : std_logic_vector(0 downto 0); + signal zz_zz_decode_BRANCH_CTRL_2_36 : std_logic_vector(31 downto 0); + signal zz_zz_decode_BRANCH_CTRL_2_37 : std_logic_vector(12 downto 0); + signal zz_zz_decode_BRANCH_CTRL_2_38 : std_logic_vector(1 downto 0); + signal zz_zz_decode_BRANCH_CTRL_2_39 : std_logic_vector(31 downto 0); + signal zz_zz_decode_BRANCH_CTRL_2_40 : std_logic_vector(31 downto 0); + signal zz_zz_decode_BRANCH_CTRL_2_41 : std_logic_vector(31 downto 0); + signal zz_zz_decode_BRANCH_CTRL_2_42 : std_logic_vector(31 downto 0); + signal zz_zz_decode_BRANCH_CTRL_2_43 : std_logic_vector(1 downto 0); + signal zz_zz_decode_BRANCH_CTRL_2_44 : std_logic; + signal zz_zz_decode_BRANCH_CTRL_2_45 : std_logic; + signal zz_zz_decode_BRANCH_CTRL_2_46 : std_logic_vector(0 downto 0); + signal zz_zz_decode_BRANCH_CTRL_2_47 : std_logic_vector(0 downto 0); + signal zz_zz_decode_BRANCH_CTRL_2_48 : std_logic_vector(31 downto 0); + signal zz_zz_decode_BRANCH_CTRL_2_49 : std_logic_vector(0 downto 0); + signal zz_zz_decode_BRANCH_CTRL_2_50 : std_logic; + signal zz_zz_decode_BRANCH_CTRL_2_51 : std_logic_vector(9 downto 0); + signal zz_zz_decode_BRANCH_CTRL_2_52 : std_logic_vector(0 downto 0); + signal zz_zz_decode_BRANCH_CTRL_2_53 : std_logic_vector(31 downto 0); + signal zz_zz_decode_BRANCH_CTRL_2_54 : std_logic_vector(0 downto 0); + signal zz_zz_decode_BRANCH_CTRL_2_55 : std_logic; + signal zz_zz_decode_BRANCH_CTRL_2_56 : std_logic_vector(0 downto 0); + signal zz_zz_decode_BRANCH_CTRL_2_57 : std_logic_vector(0 downto 0); + signal zz_zz_decode_BRANCH_CTRL_2_58 : std_logic_vector(4 downto 0); + signal zz_zz_decode_BRANCH_CTRL_2_59 : std_logic_vector(31 downto 0); + signal zz_zz_decode_BRANCH_CTRL_2_60 : std_logic_vector(31 downto 0); + signal zz_zz_decode_BRANCH_CTRL_2_61 : std_logic; + signal zz_zz_decode_BRANCH_CTRL_2_62 : std_logic_vector(31 downto 0); + signal zz_zz_decode_BRANCH_CTRL_2_63 : std_logic_vector(0 downto 0); + signal zz_zz_decode_BRANCH_CTRL_2_64 : std_logic_vector(1 downto 0); + signal zz_zz_decode_BRANCH_CTRL_2_65 : std_logic; + signal zz_zz_decode_BRANCH_CTRL_2_66 : std_logic; + signal zz_zz_decode_BRANCH_CTRL_2_67 : std_logic_vector(6 downto 0); + signal zz_zz_decode_BRANCH_CTRL_2_68 : std_logic_vector(1 downto 0); + signal zz_zz_decode_BRANCH_CTRL_2_69 : std_logic_vector(31 downto 0); + signal zz_zz_decode_BRANCH_CTRL_2_70 : std_logic_vector(31 downto 0); + signal zz_zz_decode_BRANCH_CTRL_2_71 : std_logic_vector(1 downto 0); + signal zz_zz_decode_BRANCH_CTRL_2_72 : std_logic; + signal zz_zz_decode_BRANCH_CTRL_2_73 : std_logic; + signal zz_zz_decode_BRANCH_CTRL_2_74 : std_logic_vector(31 downto 0); + signal zz_zz_decode_BRANCH_CTRL_2_75 : std_logic_vector(0 downto 0); + signal zz_zz_decode_BRANCH_CTRL_2_76 : std_logic_vector(0 downto 0); + signal zz_zz_decode_BRANCH_CTRL_2_77 : std_logic_vector(31 downto 0); + signal zz_zz_decode_BRANCH_CTRL_2_78 : std_logic_vector(31 downto 0); + signal zz_zz_decode_BRANCH_CTRL_2_79 : std_logic_vector(2 downto 0); + signal zz_zz_decode_BRANCH_CTRL_2_80 : std_logic_vector(0 downto 0); + signal zz_zz_decode_BRANCH_CTRL_2_81 : std_logic_vector(0 downto 0); + signal zz_zz_decode_BRANCH_CTRL_2_82 : std_logic_vector(31 downto 0); + signal zz_zz_decode_BRANCH_CTRL_2_83 : std_logic_vector(3 downto 0); + signal zz_zz_decode_BRANCH_CTRL_2_84 : std_logic_vector(0 downto 0); + signal zz_zz_decode_BRANCH_CTRL_2_85 : std_logic_vector(31 downto 0); + signal zz_zz_decode_BRANCH_CTRL_2_86 : std_logic_vector(31 downto 0); + signal zz_zz_decode_BRANCH_CTRL_2_87 : std_logic_vector(0 downto 0); + signal zz_zz_decode_BRANCH_CTRL_2_88 : std_logic; + signal zz_zz_decode_BRANCH_CTRL_2_89 : std_logic_vector(0 downto 0); + signal zz_zz_decode_BRANCH_CTRL_2_90 : std_logic_vector(31 downto 0); + signal zz_zz_decode_BRANCH_CTRL_2_91 : std_logic_vector(1 downto 0); + signal zz_zz_decode_BRANCH_CTRL_2_92 : std_logic_vector(31 downto 0); + signal zz_zz_decode_BRANCH_CTRL_2_93 : std_logic_vector(31 downto 0); + signal zz_zz_decode_BRANCH_CTRL_2_94 : std_logic_vector(31 downto 0); + signal zz_zz_decode_BRANCH_CTRL_2_95 : std_logic_vector(31 downto 0); + signal zz_zz_decode_BRANCH_CTRL_2_96 : std_logic_vector(0 downto 0); + signal zz_zz_decode_BRANCH_CTRL_2_97 : std_logic_vector(1 downto 0); + signal zz_zz_decode_BRANCH_CTRL_2_98 : std_logic_vector(31 downto 0); + signal zz_zz_decode_BRANCH_CTRL_2_99 : std_logic_vector(31 downto 0); + signal zz_zz_decode_BRANCH_CTRL_2_100 : std_logic_vector(1 downto 0); + signal zz_zz_decode_BRANCH_CTRL_2_101 : std_logic_vector(0 downto 0); + signal zz_zz_decode_BRANCH_CTRL_2_102 : std_logic_vector(1 downto 0); + signal zz_zz_decode_BRANCH_CTRL_2_103 : std_logic_vector(31 downto 0); + signal zz_zz_decode_BRANCH_CTRL_2_104 : std_logic_vector(31 downto 0); + signal zz_zz_decode_BRANCH_CTRL_2_105 : std_logic_vector(1 downto 0); + signal zz_RegFilePlugin_regFile_port : std_logic; + signal zz_decode_RegFilePlugin_rs1Data : std_logic; + signal zz_RegFilePlugin_regFile_port_1 : std_logic; + signal zz_decode_RegFilePlugin_rs2Data : std_logic; + + signal memory_MEMORY_READ_DATA : std_logic_vector(31 downto 0); + signal execute_BRANCH_CALC : unsigned(31 downto 0); + signal execute_BRANCH_DO : std_logic; + signal writeBack_REGFILE_WRITE_DATA : std_logic_vector(31 downto 0); + signal execute_REGFILE_WRITE_DATA : std_logic_vector(31 downto 0); + signal memory_MEMORY_ADDRESS_LOW : unsigned(1 downto 0); + signal execute_MEMORY_ADDRESS_LOW : unsigned(1 downto 0); + signal decode_DO_EBREAK : std_logic; + signal decode_SRC2 : std_logic_vector(31 downto 0); + signal decode_SRC1 : std_logic_vector(31 downto 0); + signal decode_SRC2_FORCE_ZERO : std_logic; + signal decode_RS2 : std_logic_vector(31 downto 0); + signal decode_RS1 : std_logic_vector(31 downto 0); + signal decode_BRANCH_CTRL : BranchCtrlEnum_seq_type; + signal zz_decode_BRANCH_CTRL : BranchCtrlEnum_seq_type; + signal zz_decode_to_execute_BRANCH_CTRL : BranchCtrlEnum_seq_type; + signal zz_decode_to_execute_BRANCH_CTRL_1 : BranchCtrlEnum_seq_type; + signal decode_SHIFT_CTRL : ShiftCtrlEnum_seq_type; + signal zz_decode_SHIFT_CTRL : ShiftCtrlEnum_seq_type; + signal zz_decode_to_execute_SHIFT_CTRL : ShiftCtrlEnum_seq_type; + signal zz_decode_to_execute_SHIFT_CTRL_1 : ShiftCtrlEnum_seq_type; + signal decode_ALU_BITWISE_CTRL : AluBitwiseCtrlEnum_seq_type; + signal zz_decode_ALU_BITWISE_CTRL : AluBitwiseCtrlEnum_seq_type; + signal zz_decode_to_execute_ALU_BITWISE_CTRL : AluBitwiseCtrlEnum_seq_type; + signal zz_decode_to_execute_ALU_BITWISE_CTRL_1 : AluBitwiseCtrlEnum_seq_type; + signal decode_SRC_LESS_UNSIGNED : std_logic; + signal decode_ALU_CTRL : AluCtrlEnum_seq_type; + signal zz_decode_ALU_CTRL : AluCtrlEnum_seq_type; + signal zz_decode_to_execute_ALU_CTRL : AluCtrlEnum_seq_type; + signal zz_decode_to_execute_ALU_CTRL_1 : AluCtrlEnum_seq_type; + signal zz_memory_to_writeBack_ENV_CTRL : EnvCtrlEnum_seq_type; + signal zz_memory_to_writeBack_ENV_CTRL_1 : EnvCtrlEnum_seq_type; + signal zz_execute_to_memory_ENV_CTRL : EnvCtrlEnum_seq_type; + signal zz_execute_to_memory_ENV_CTRL_1 : EnvCtrlEnum_seq_type; + signal decode_ENV_CTRL : EnvCtrlEnum_seq_type; + signal zz_decode_ENV_CTRL : EnvCtrlEnum_seq_type; + signal zz_decode_to_execute_ENV_CTRL : EnvCtrlEnum_seq_type; + signal zz_decode_to_execute_ENV_CTRL_1 : EnvCtrlEnum_seq_type; + signal decode_IS_CSR : std_logic; + signal decode_MEMORY_STORE : std_logic; + signal execute_BYPASSABLE_MEMORY_STAGE : std_logic; + signal decode_BYPASSABLE_MEMORY_STAGE : std_logic; + signal decode_BYPASSABLE_EXECUTE_STAGE : std_logic; + signal decode_MEMORY_ENABLE : std_logic; + signal decode_CSR_READ_OPCODE : std_logic; + signal decode_CSR_WRITE_OPCODE : std_logic; + signal writeBack_FORMAL_PC_NEXT : unsigned(31 downto 0); + signal memory_FORMAL_PC_NEXT : unsigned(31 downto 0); + signal execute_FORMAL_PC_NEXT : unsigned(31 downto 0); + signal decode_FORMAL_PC_NEXT : unsigned(31 downto 0); + signal memory_PC : unsigned(31 downto 0); + signal execute_DO_EBREAK : std_logic; + signal decode_IS_EBREAK : std_logic; + signal memory_BRANCH_CALC : unsigned(31 downto 0); + signal memory_BRANCH_DO : std_logic; + signal execute_PC : unsigned(31 downto 0); + signal execute_RS1 : std_logic_vector(31 downto 0); + signal execute_BRANCH_CTRL : BranchCtrlEnum_seq_type; + signal zz_execute_BRANCH_CTRL : BranchCtrlEnum_seq_type; + signal decode_RS2_USE : std_logic; + signal decode_RS1_USE : std_logic; + signal execute_REGFILE_WRITE_VALID : std_logic; + signal execute_BYPASSABLE_EXECUTE_STAGE : std_logic; + signal memory_REGFILE_WRITE_VALID : std_logic; + signal memory_INSTRUCTION : std_logic_vector(31 downto 0); + signal memory_BYPASSABLE_MEMORY_STAGE : std_logic; + signal writeBack_REGFILE_WRITE_VALID : std_logic; + signal memory_REGFILE_WRITE_DATA : std_logic_vector(31 downto 0); + signal execute_SHIFT_CTRL : ShiftCtrlEnum_seq_type; + signal zz_execute_SHIFT_CTRL : ShiftCtrlEnum_seq_type; + signal execute_SRC_LESS_UNSIGNED : std_logic; + signal execute_SRC2_FORCE_ZERO : std_logic; + signal execute_SRC_USE_SUB_LESS : std_logic; + signal zz_decode_SRC2 : unsigned(31 downto 0); + signal zz_decode_SRC2_1 : std_logic_vector(31 downto 0); + signal decode_SRC2_CTRL : Src2CtrlEnum_seq_type; + signal zz_decode_SRC2_CTRL : Src2CtrlEnum_seq_type; + signal zz_decode_SRC1 : std_logic_vector(31 downto 0); + signal decode_SRC1_CTRL : Src1CtrlEnum_seq_type; + signal zz_decode_SRC1_CTRL : Src1CtrlEnum_seq_type; + signal decode_SRC_USE_SUB_LESS : std_logic; + signal decode_SRC_ADD_ZERO : std_logic; + signal execute_SRC_ADD_SUB : std_logic_vector(31 downto 0); + signal execute_SRC_LESS : std_logic; + signal execute_ALU_CTRL : AluCtrlEnum_seq_type; + signal zz_execute_ALU_CTRL : AluCtrlEnum_seq_type; + signal execute_SRC2 : std_logic_vector(31 downto 0); + signal execute_ALU_BITWISE_CTRL : AluBitwiseCtrlEnum_seq_type; + signal zz_execute_ALU_BITWISE_CTRL : AluBitwiseCtrlEnum_seq_type; + signal zz_lastStageRegFileWrite_payload_address : std_logic_vector(31 downto 0); + signal zz_lastStageRegFileWrite_valid : std_logic; + signal zz_1 : std_logic; + signal decode_INSTRUCTION_ANTICIPATED : std_logic_vector(31 downto 0); + signal decode_REGFILE_WRITE_VALID : std_logic; + signal zz_decode_BRANCH_CTRL_1 : BranchCtrlEnum_seq_type; + signal zz_decode_SHIFT_CTRL_1 : ShiftCtrlEnum_seq_type; + signal zz_decode_ALU_BITWISE_CTRL_1 : AluBitwiseCtrlEnum_seq_type; + signal zz_decode_ALU_CTRL_1 : AluCtrlEnum_seq_type; + signal zz_decode_ENV_CTRL_1 : EnvCtrlEnum_seq_type; + signal zz_decode_SRC2_CTRL_1 : Src2CtrlEnum_seq_type; + signal zz_decode_SRC1_CTRL_1 : Src1CtrlEnum_seq_type; + signal zz_execute_to_memory_REGFILE_WRITE_DATA : std_logic_vector(31 downto 0); + signal execute_SRC1 : std_logic_vector(31 downto 0); + signal execute_CSR_READ_OPCODE : std_logic; + signal execute_CSR_WRITE_OPCODE : std_logic; + signal execute_IS_CSR : std_logic; + signal memory_ENV_CTRL : EnvCtrlEnum_seq_type; + signal zz_memory_ENV_CTRL : EnvCtrlEnum_seq_type; + signal execute_ENV_CTRL : EnvCtrlEnum_seq_type; + signal zz_execute_ENV_CTRL : EnvCtrlEnum_seq_type; + signal writeBack_ENV_CTRL : EnvCtrlEnum_seq_type; + signal zz_writeBack_ENV_CTRL : EnvCtrlEnum_seq_type; + signal zz_lastStageRegFileWrite_payload_data : std_logic_vector(31 downto 0); + signal writeBack_MEMORY_ENABLE : std_logic; + signal writeBack_MEMORY_ADDRESS_LOW : unsigned(1 downto 0); + signal writeBack_MEMORY_READ_DATA : std_logic_vector(31 downto 0); + signal memory_MEMORY_STORE : std_logic; + signal memory_MEMORY_ENABLE : std_logic; + signal execute_SRC_ADD : std_logic_vector(31 downto 0); + signal execute_RS2 : std_logic_vector(31 downto 0); + signal execute_INSTRUCTION : std_logic_vector(31 downto 0); + signal execute_MEMORY_STORE : std_logic; + signal execute_MEMORY_ENABLE : std_logic; + signal execute_ALIGNEMENT_FAULT : std_logic; + signal zz_memory_to_writeBack_FORMAL_PC_NEXT : unsigned(31 downto 0); + signal decode_PC : unsigned(31 downto 0); + signal decode_INSTRUCTION : std_logic_vector(31 downto 0); + signal writeBack_PC : unsigned(31 downto 0); + signal writeBack_INSTRUCTION : std_logic_vector(31 downto 0); + signal decode_arbitration_haltItself : std_logic; + signal decode_arbitration_haltByOther : std_logic; + signal decode_arbitration_removeIt : std_logic; + signal decode_arbitration_flushIt : std_logic; + signal decode_arbitration_flushNext : std_logic; + signal decode_arbitration_isValid : std_logic; + signal decode_arbitration_isStuck : std_logic; + signal decode_arbitration_isStuckByOthers : std_logic; + signal decode_arbitration_isFlushed : std_logic; + signal decode_arbitration_isMoving : std_logic; + signal decode_arbitration_isFiring : std_logic; + signal execute_arbitration_haltItself : std_logic; + signal execute_arbitration_haltByOther : std_logic; + signal execute_arbitration_removeIt : std_logic; + signal execute_arbitration_flushIt : std_logic; + signal execute_arbitration_flushNext : std_logic; + signal execute_arbitration_isValid : std_logic; + signal execute_arbitration_isStuck : std_logic; + signal execute_arbitration_isStuckByOthers : std_logic; + signal execute_arbitration_isFlushed : std_logic; + signal execute_arbitration_isMoving : std_logic; + signal execute_arbitration_isFiring : std_logic; + signal memory_arbitration_haltItself : std_logic; + signal memory_arbitration_haltByOther : std_logic; + signal memory_arbitration_removeIt : std_logic; + signal memory_arbitration_flushIt : std_logic; + signal memory_arbitration_flushNext : std_logic; + signal memory_arbitration_isValid : std_logic; + signal memory_arbitration_isStuck : std_logic; + signal memory_arbitration_isStuckByOthers : std_logic; + signal memory_arbitration_isFlushed : std_logic; + signal memory_arbitration_isMoving : std_logic; + signal memory_arbitration_isFiring : std_logic; + signal writeBack_arbitration_haltItself : std_logic; + signal writeBack_arbitration_haltByOther : std_logic; + signal writeBack_arbitration_removeIt : std_logic; + signal writeBack_arbitration_flushIt : std_logic; + signal writeBack_arbitration_flushNext : std_logic; + signal writeBack_arbitration_isValid : std_logic; + signal writeBack_arbitration_isStuck : std_logic; + signal writeBack_arbitration_isStuckByOthers : std_logic; + signal writeBack_arbitration_isFlushed : std_logic; + signal writeBack_arbitration_isMoving : std_logic; + signal writeBack_arbitration_isFiring : std_logic; + signal lastStageInstruction : std_logic_vector(31 downto 0); + signal lastStagePc : unsigned(31 downto 0); + signal lastStageIsValid : std_logic; + signal lastStageIsFiring : std_logic; + signal IBusSimplePlugin_fetcherHalt : std_logic; + signal IBusSimplePlugin_forceNoDecodeCond : std_logic; + signal IBusSimplePlugin_incomingInstruction : std_logic; + signal IBusSimplePlugin_pcValids_0 : std_logic; + signal IBusSimplePlugin_pcValids_1 : std_logic; + signal IBusSimplePlugin_pcValids_2 : std_logic; + signal IBusSimplePlugin_pcValids_3 : std_logic; + signal CsrPlugin_csrMapping_readDataSignal : std_logic_vector(31 downto 0); + signal CsrPlugin_csrMapping_readDataInit : std_logic_vector(31 downto 0); + signal CsrPlugin_csrMapping_writeDataSignal : std_logic_vector(31 downto 0); + signal CsrPlugin_csrMapping_allowCsrSignal : std_logic; + signal CsrPlugin_csrMapping_hazardFree : std_logic; + signal CsrPlugin_inWfi : std_logic; + signal CsrPlugin_thirdPartyWake : std_logic; + signal CsrPlugin_jumpInterface_valid : std_logic; + signal CsrPlugin_jumpInterface_payload : unsigned(31 downto 0); + signal CsrPlugin_exceptionPendings_0 : std_logic; + signal CsrPlugin_exceptionPendings_1 : std_logic; + signal CsrPlugin_exceptionPendings_2 : std_logic; + signal CsrPlugin_exceptionPendings_3 : std_logic; + signal contextSwitching : std_logic; + signal CsrPlugin_privilege : unsigned(1 downto 0); + signal CsrPlugin_forceMachineWire : std_logic; + signal CsrPlugin_allowInterrupts : std_logic; + signal CsrPlugin_allowException : std_logic; + signal CsrPlugin_allowEbreakException : std_logic; + signal BranchPlugin_jumpInterface_valid : std_logic; + signal BranchPlugin_jumpInterface_payload : unsigned(31 downto 0); + signal BranchPlugin_inDebugNoFetchFlag : std_logic; + signal IBusSimplePlugin_injectionPort_valid : std_logic; + signal IBusSimplePlugin_injectionPort_ready : std_logic; + signal IBusSimplePlugin_injectionPort_payload : std_logic_vector(31 downto 0); + signal IBusSimplePlugin_externalFlush : std_logic; + signal IBusSimplePlugin_jump_pcLoad_valid : std_logic; + signal IBusSimplePlugin_jump_pcLoad_payload : unsigned(31 downto 0); + signal zz_IBusSimplePlugin_jump_pcLoad_payload : unsigned(1 downto 0); + signal IBusSimplePlugin_fetchPc_output_valid : std_logic; + signal IBusSimplePlugin_fetchPc_output_ready : std_logic; + signal IBusSimplePlugin_fetchPc_output_payload : unsigned(31 downto 0); + signal IBusSimplePlugin_fetchPc_pcReg : unsigned(31 downto 0); + signal IBusSimplePlugin_fetchPc_correction : std_logic; + signal IBusSimplePlugin_fetchPc_correctionReg : std_logic; + signal IBusSimplePlugin_fetchPc_output_fire : std_logic; + signal IBusSimplePlugin_fetchPc_corrected : std_logic; + signal IBusSimplePlugin_fetchPc_pcRegPropagate : std_logic; + signal IBusSimplePlugin_fetchPc_booted : std_logic; + signal IBusSimplePlugin_fetchPc_inc : std_logic; + signal when_Fetcher_l134 : std_logic; + signal IBusSimplePlugin_fetchPc_output_fire_1 : std_logic; + signal when_Fetcher_l134_1 : std_logic; + signal IBusSimplePlugin_fetchPc_pc : unsigned(31 downto 0); + signal IBusSimplePlugin_fetchPc_flushed : std_logic; + signal when_Fetcher_l161 : std_logic; + signal IBusSimplePlugin_iBusRsp_redoFetch : std_logic; + signal IBusSimplePlugin_iBusRsp_stages_0_input_valid : std_logic; + signal IBusSimplePlugin_iBusRsp_stages_0_input_ready : std_logic; + signal IBusSimplePlugin_iBusRsp_stages_0_input_payload : unsigned(31 downto 0); + signal IBusSimplePlugin_iBusRsp_stages_0_output_valid : std_logic; + signal IBusSimplePlugin_iBusRsp_stages_0_output_ready : std_logic; + signal IBusSimplePlugin_iBusRsp_stages_0_output_payload : unsigned(31 downto 0); + signal IBusSimplePlugin_iBusRsp_stages_0_halt : std_logic; + signal IBusSimplePlugin_iBusRsp_stages_1_input_valid : std_logic; + signal IBusSimplePlugin_iBusRsp_stages_1_input_ready : std_logic; + signal IBusSimplePlugin_iBusRsp_stages_1_input_payload : unsigned(31 downto 0); + signal IBusSimplePlugin_iBusRsp_stages_1_output_valid : std_logic; + signal IBusSimplePlugin_iBusRsp_stages_1_output_ready : std_logic; + signal IBusSimplePlugin_iBusRsp_stages_1_output_payload : unsigned(31 downto 0); + signal IBusSimplePlugin_iBusRsp_stages_1_halt : std_logic; + signal IBusSimplePlugin_iBusRsp_stages_2_input_valid : std_logic; + signal IBusSimplePlugin_iBusRsp_stages_2_input_ready : std_logic; + signal IBusSimplePlugin_iBusRsp_stages_2_input_payload : unsigned(31 downto 0); + signal IBusSimplePlugin_iBusRsp_stages_2_output_valid : std_logic; + signal IBusSimplePlugin_iBusRsp_stages_2_output_ready : std_logic; + signal IBusSimplePlugin_iBusRsp_stages_2_output_payload : unsigned(31 downto 0); + signal IBusSimplePlugin_iBusRsp_stages_2_halt : std_logic; + signal zz_IBusSimplePlugin_iBusRsp_stages_0_input_ready : std_logic; + signal zz_IBusSimplePlugin_iBusRsp_stages_1_input_ready : std_logic; + signal zz_IBusSimplePlugin_iBusRsp_stages_2_input_ready : std_logic; + signal IBusSimplePlugin_iBusRsp_flush : std_logic; + signal zz_IBusSimplePlugin_iBusRsp_stages_0_output_ready : std_logic; + signal zz_IBusSimplePlugin_iBusRsp_stages_0_output_ready_1 : std_logic; + signal zz_IBusSimplePlugin_iBusRsp_stages_0_output_ready_2 : std_logic; + signal IBusSimplePlugin_iBusRsp_stages_1_output_m2sPipe_valid : std_logic; + signal IBusSimplePlugin_iBusRsp_stages_1_output_m2sPipe_ready : std_logic; + signal IBusSimplePlugin_iBusRsp_stages_1_output_m2sPipe_payload : unsigned(31 downto 0); + signal zz_IBusSimplePlugin_iBusRsp_stages_1_output_m2sPipe_valid : std_logic; + signal zz_IBusSimplePlugin_iBusRsp_stages_1_output_m2sPipe_payload : unsigned(31 downto 0); + signal IBusSimplePlugin_iBusRsp_readyForError : std_logic; + signal IBusSimplePlugin_iBusRsp_output_valid : std_logic; + signal IBusSimplePlugin_iBusRsp_output_ready : std_logic; + signal IBusSimplePlugin_iBusRsp_output_payload_pc : unsigned(31 downto 0); + signal IBusSimplePlugin_iBusRsp_output_payload_rsp_error : std_logic; + signal IBusSimplePlugin_iBusRsp_output_payload_rsp_inst : std_logic_vector(31 downto 0); + signal IBusSimplePlugin_iBusRsp_output_payload_isRvc : std_logic; + signal when_Fetcher_l243 : std_logic; + signal IBusSimplePlugin_injector_decodeInput_valid : std_logic; + signal IBusSimplePlugin_injector_decodeInput_ready : std_logic; + signal IBusSimplePlugin_injector_decodeInput_payload_pc : unsigned(31 downto 0); + signal IBusSimplePlugin_injector_decodeInput_payload_rsp_error : std_logic; + signal IBusSimplePlugin_injector_decodeInput_payload_rsp_inst : std_logic_vector(31 downto 0); + signal IBusSimplePlugin_injector_decodeInput_payload_isRvc : std_logic; + signal zz_IBusSimplePlugin_injector_decodeInput_valid : std_logic; + signal zz_IBusSimplePlugin_injector_decodeInput_payload_pc : unsigned(31 downto 0); + signal zz_IBusSimplePlugin_injector_decodeInput_payload_rsp_error : std_logic; + signal zz_IBusSimplePlugin_injector_decodeInput_payload_rsp_inst : std_logic_vector(31 downto 0); + signal zz_IBusSimplePlugin_injector_decodeInput_payload_isRvc : std_logic; + signal when_Fetcher_l323 : std_logic; + signal IBusSimplePlugin_injector_nextPcCalc_valids_0 : std_logic; + signal when_Fetcher_l332 : std_logic; + signal IBusSimplePlugin_injector_nextPcCalc_valids_1 : std_logic; + signal when_Fetcher_l332_1 : std_logic; + signal IBusSimplePlugin_injector_nextPcCalc_valids_2 : std_logic; + signal when_Fetcher_l332_2 : std_logic; + signal IBusSimplePlugin_injector_nextPcCalc_valids_3 : std_logic; + signal when_Fetcher_l332_3 : std_logic; + signal IBusSimplePlugin_injector_nextPcCalc_valids_4 : std_logic; + signal when_Fetcher_l332_4 : std_logic; + signal IBusSimplePlugin_injector_nextPcCalc_valids_5 : std_logic; + signal when_Fetcher_l332_5 : std_logic; + signal IBusSimplePlugin_injector_formal_rawInDecode : std_logic_vector(31 downto 0); + signal IBusSimplePlugin_cmd_valid : std_logic; + signal IBusSimplePlugin_cmd_ready : std_logic; + signal IBusSimplePlugin_cmd_payload_pc : unsigned(31 downto 0); + signal IBusSimplePlugin_pending_inc : std_logic; + signal IBusSimplePlugin_pending_dec : std_logic; + signal IBusSimplePlugin_pending_value : unsigned(2 downto 0); + signal IBusSimplePlugin_pending_next : unsigned(2 downto 0); + signal IBusSimplePlugin_cmdFork_canEmit : std_logic; + signal when_IBusSimplePlugin_l305 : std_logic; + signal IBusSimplePlugin_cmd_fire : std_logic; + signal IBusSimplePlugin_rspJoin_rspBuffer_output_valid : std_logic; + signal IBusSimplePlugin_rspJoin_rspBuffer_output_ready : std_logic; + signal IBusSimplePlugin_rspJoin_rspBuffer_output_payload_error : std_logic; + signal IBusSimplePlugin_rspJoin_rspBuffer_output_payload_inst : std_logic_vector(31 downto 0); + signal IBusSimplePlugin_rspJoin_rspBuffer_discardCounter : unsigned(2 downto 0); + signal iBus_rsp_toStream_valid : std_logic; + signal iBus_rsp_toStream_ready : std_logic; + signal iBus_rsp_toStream_payload_error : std_logic; + signal iBus_rsp_toStream_payload_inst : std_logic_vector(31 downto 0); + signal IBusSimplePlugin_rspJoin_rspBuffer_flush : std_logic; + signal IBusSimplePlugin_rspJoin_rspBuffer_c_io_pop_fire : std_logic; + signal IBusSimplePlugin_rspJoin_fetchRsp_pc : unsigned(31 downto 0); + signal IBusSimplePlugin_rspJoin_fetchRsp_rsp_error : std_logic; + signal IBusSimplePlugin_rspJoin_fetchRsp_rsp_inst : std_logic_vector(31 downto 0); + signal IBusSimplePlugin_rspJoin_fetchRsp_isRvc : std_logic; + signal when_IBusSimplePlugin_l376 : std_logic; + signal IBusSimplePlugin_rspJoin_join_valid : std_logic; + signal IBusSimplePlugin_rspJoin_join_ready : std_logic; + signal IBusSimplePlugin_rspJoin_join_payload_pc : unsigned(31 downto 0); + signal IBusSimplePlugin_rspJoin_join_payload_rsp_error : std_logic; + signal IBusSimplePlugin_rspJoin_join_payload_rsp_inst : std_logic_vector(31 downto 0); + signal IBusSimplePlugin_rspJoin_join_payload_isRvc : std_logic; + signal IBusSimplePlugin_rspJoin_exceptionDetected : std_logic; + signal IBusSimplePlugin_rspJoin_join_fire : std_logic; + signal IBusSimplePlugin_rspJoin_join_fire_1 : std_logic; + signal zz_IBusSimplePlugin_iBusRsp_output_valid : std_logic; + signal zz_dBus_cmd_valid : std_logic; + signal execute_DBusSimplePlugin_skipCmd : std_logic; + signal zz_dBus_cmd_payload_data : std_logic_vector(31 downto 0); + signal when_DBusSimplePlugin_l428 : std_logic; + signal zz_execute_DBusSimplePlugin_formalMask : std_logic_vector(3 downto 0); + signal execute_DBusSimplePlugin_formalMask : std_logic_vector(3 downto 0); + signal when_DBusSimplePlugin_l482 : std_logic; + signal writeBack_DBusSimplePlugin_rspShifted : std_logic_vector(31 downto 0); + signal switch_Misc_l210 : std_logic_vector(1 downto 0); + signal zz_writeBack_DBusSimplePlugin_rspFormated : std_logic; + signal zz_writeBack_DBusSimplePlugin_rspFormated_1 : std_logic_vector(31 downto 0); + signal zz_writeBack_DBusSimplePlugin_rspFormated_2 : std_logic; + signal zz_writeBack_DBusSimplePlugin_rspFormated_3 : std_logic_vector(31 downto 0); + signal writeBack_DBusSimplePlugin_rspFormated : std_logic_vector(31 downto 0); + signal when_DBusSimplePlugin_l558 : std_logic; + signal CsrPlugin_misa_base : unsigned(1 downto 0); + signal CsrPlugin_misa_extensions : std_logic_vector(25 downto 0); + signal CsrPlugin_mtvec_mode : std_logic_vector(1 downto 0); + signal CsrPlugin_mtvec_base : unsigned(29 downto 0); + signal CsrPlugin_mepc : unsigned(31 downto 0); + signal CsrPlugin_mstatus_MIE : std_logic; + signal CsrPlugin_mstatus_MPIE : std_logic; + signal CsrPlugin_mstatus_MPP : unsigned(1 downto 0); + signal CsrPlugin_mip_MEIP : std_logic; + signal CsrPlugin_mip_MTIP : std_logic; + signal CsrPlugin_mip_MSIP : std_logic; + signal CsrPlugin_mie_MEIE : std_logic; + signal CsrPlugin_mie_MTIE : std_logic; + signal CsrPlugin_mie_MSIE : std_logic; + signal CsrPlugin_mcause_interrupt : std_logic; + signal CsrPlugin_mcause_exceptionCode : unsigned(3 downto 0); + signal CsrPlugin_mtval : unsigned(31 downto 0); + signal CsrPlugin_mcycle : unsigned(63 downto 0); + signal CsrPlugin_minstret : unsigned(63 downto 0); + signal zz_when_CsrPlugin_l965 : std_logic; + signal zz_when_CsrPlugin_l965_1 : std_logic; + signal zz_when_CsrPlugin_l965_2 : std_logic; + signal CsrPlugin_interrupt_valid : std_logic; + signal CsrPlugin_interrupt_code : unsigned(3 downto 0); + signal CsrPlugin_interrupt_targetPrivilege : unsigned(1 downto 0); + signal when_CsrPlugin_l959 : std_logic; + signal when_CsrPlugin_l965 : std_logic; + signal when_CsrPlugin_l965_1 : std_logic; + signal when_CsrPlugin_l965_2 : std_logic; + signal CsrPlugin_exception : std_logic; + signal CsrPlugin_lastStageWasWfi : std_logic; + signal CsrPlugin_pipelineLiberator_pcValids_0 : std_logic; + signal CsrPlugin_pipelineLiberator_pcValids_1 : std_logic; + signal CsrPlugin_pipelineLiberator_pcValids_2 : std_logic; + signal CsrPlugin_pipelineLiberator_active : std_logic; + signal when_CsrPlugin_l993 : std_logic; + signal when_CsrPlugin_l993_1 : std_logic; + signal when_CsrPlugin_l993_2 : std_logic; + signal when_CsrPlugin_l998 : std_logic; + signal CsrPlugin_pipelineLiberator_done : std_logic; + signal CsrPlugin_interruptJump : std_logic; + signal CsrPlugin_hadException : std_logic; + signal CsrPlugin_targetPrivilege : unsigned(1 downto 0); + signal CsrPlugin_trapCause : unsigned(3 downto 0); + signal CsrPlugin_xtvec_mode : std_logic_vector(1 downto 0); + signal CsrPlugin_xtvec_base : unsigned(29 downto 0); + signal when_CsrPlugin_l1032 : std_logic; + signal when_CsrPlugin_l1077 : std_logic; + signal switch_CsrPlugin_l1081 : std_logic_vector(1 downto 0); + signal execute_CsrPlugin_wfiWake : std_logic; + signal when_CsrPlugin_l1129 : std_logic; + signal execute_CsrPlugin_blockedBySideEffects : std_logic; + signal execute_CsrPlugin_illegalAccess : std_logic; + signal execute_CsrPlugin_illegalInstruction : std_logic; + signal when_CsrPlugin_l1149 : std_logic; + signal when_CsrPlugin_l1150 : std_logic; + signal execute_CsrPlugin_writeInstruction : std_logic; + signal execute_CsrPlugin_readInstruction : std_logic; + signal execute_CsrPlugin_writeEnable : std_logic; + signal execute_CsrPlugin_readEnable : std_logic; + signal execute_CsrPlugin_readToWriteData : std_logic_vector(31 downto 0); + signal switch_Misc_l210_1 : std_logic; + signal zz_CsrPlugin_csrMapping_writeDataSignal : std_logic_vector(31 downto 0); + signal when_CsrPlugin_l1189 : std_logic; + signal when_CsrPlugin_l1193 : std_logic; + signal execute_CsrPlugin_csrAddress : std_logic_vector(11 downto 0); + signal zz_decode_BRANCH_CTRL_2 : std_logic_vector(25 downto 0); + signal zz_decode_BRANCH_CTRL_3 : std_logic; + signal zz_decode_BRANCH_CTRL_4 : std_logic; + signal zz_decode_BRANCH_CTRL_5 : std_logic; + signal zz_decode_BRANCH_CTRL_6 : std_logic; + signal zz_decode_BRANCH_CTRL_7 : std_logic; + signal zz_decode_BRANCH_CTRL_8 : std_logic; + signal zz_decode_SRC1_CTRL_2 : Src1CtrlEnum_seq_type; + signal zz_decode_SRC2_CTRL_2 : Src2CtrlEnum_seq_type; + signal zz_decode_ENV_CTRL_2 : EnvCtrlEnum_seq_type; + signal zz_decode_ALU_CTRL_2 : AluCtrlEnum_seq_type; + signal zz_decode_ALU_BITWISE_CTRL_2 : AluBitwiseCtrlEnum_seq_type; + signal zz_decode_SHIFT_CTRL_2 : ShiftCtrlEnum_seq_type; + signal zz_decode_BRANCH_CTRL_9 : BranchCtrlEnum_seq_type; + signal when_RegFilePlugin_l63 : std_logic; + signal decode_RegFilePlugin_regFileReadAddress1 : unsigned(4 downto 0); + signal decode_RegFilePlugin_regFileReadAddress2 : unsigned(4 downto 0); + signal decode_RegFilePlugin_rs1Data : std_logic_vector(31 downto 0); + signal decode_RegFilePlugin_rs2Data : std_logic_vector(31 downto 0); + signal lastStageRegFileWrite_valid : std_logic; + signal lastStageRegFileWrite_payload_address : unsigned(4 downto 0); + signal lastStageRegFileWrite_payload_data : std_logic_vector(31 downto 0); + signal zz_2 : std_logic; + signal execute_IntAluPlugin_bitwise : std_logic_vector(31 downto 0); + signal zz_execute_REGFILE_WRITE_DATA : std_logic_vector(31 downto 0); + signal zz_decode_SRC1_1 : std_logic_vector(31 downto 0); + signal zz_decode_SRC2_2 : std_logic; + signal zz_decode_SRC2_3 : std_logic_vector(19 downto 0); + signal zz_decode_SRC2_4 : std_logic; + signal zz_decode_SRC2_5 : std_logic_vector(19 downto 0); + signal zz_decode_SRC2_6 : std_logic_vector(31 downto 0); + signal execute_SrcPlugin_addSub : std_logic_vector(31 downto 0); + signal execute_SrcPlugin_less : std_logic; + signal execute_LightShifterPlugin_isActive : std_logic; + signal execute_LightShifterPlugin_isShift : std_logic; + signal execute_LightShifterPlugin_amplitudeReg : unsigned(4 downto 0); + signal execute_LightShifterPlugin_amplitude : unsigned(4 downto 0); + signal execute_LightShifterPlugin_shiftInput : std_logic_vector(31 downto 0); + signal execute_LightShifterPlugin_done : std_logic; + signal when_ShiftPlugins_l169 : std_logic; + signal zz_execute_to_memory_REGFILE_WRITE_DATA_1 : std_logic_vector(31 downto 0); + signal when_ShiftPlugins_l175 : std_logic; + signal when_ShiftPlugins_l184 : std_logic; + signal HazardSimplePlugin_src0Hazard : std_logic; + signal HazardSimplePlugin_src1Hazard : std_logic; + signal HazardSimplePlugin_writeBackWrites_valid : std_logic; + signal HazardSimplePlugin_writeBackWrites_payload_address : std_logic_vector(4 downto 0); + signal HazardSimplePlugin_writeBackWrites_payload_data : std_logic_vector(31 downto 0); + signal HazardSimplePlugin_writeBackBuffer_valid : std_logic; + signal HazardSimplePlugin_writeBackBuffer_payload_address : std_logic_vector(4 downto 0); + signal HazardSimplePlugin_writeBackBuffer_payload_data : std_logic_vector(31 downto 0); + signal HazardSimplePlugin_addr0Match : std_logic; + signal HazardSimplePlugin_addr1Match : std_logic; + signal when_HazardSimplePlugin_l59 : std_logic; + signal when_HazardSimplePlugin_l62 : std_logic; + signal when_HazardSimplePlugin_l57 : std_logic; + signal when_HazardSimplePlugin_l58 : std_logic; + signal when_HazardSimplePlugin_l59_1 : std_logic; + signal when_HazardSimplePlugin_l62_1 : std_logic; + signal when_HazardSimplePlugin_l57_1 : std_logic; + signal when_HazardSimplePlugin_l58_1 : std_logic; + signal when_HazardSimplePlugin_l59_2 : std_logic; + signal when_HazardSimplePlugin_l62_2 : std_logic; + signal when_HazardSimplePlugin_l57_2 : std_logic; + signal when_HazardSimplePlugin_l58_2 : std_logic; + signal when_HazardSimplePlugin_l105 : std_logic; + signal when_HazardSimplePlugin_l108 : std_logic; + signal when_HazardSimplePlugin_l113 : std_logic; + signal execute_BranchPlugin_eq : std_logic; + signal switch_Misc_l210_2 : std_logic_vector(2 downto 0); + signal zz_execute_BRANCH_DO : std_logic; + signal zz_execute_BRANCH_DO_1 : std_logic; + signal execute_BranchPlugin_branch_src1 : unsigned(31 downto 0); + signal zz_execute_BranchPlugin_branch_src2 : std_logic; + signal zz_execute_BranchPlugin_branch_src2_1 : std_logic_vector(10 downto 0); + signal zz_execute_BranchPlugin_branch_src2_2 : std_logic; + signal zz_execute_BranchPlugin_branch_src2_3 : std_logic_vector(19 downto 0); + signal zz_execute_BranchPlugin_branch_src2_4 : std_logic; + signal zz_execute_BranchPlugin_branch_src2_5 : std_logic_vector(18 downto 0); + signal zz_execute_BranchPlugin_branch_src2_6 : std_logic_vector(31 downto 0); + signal execute_BranchPlugin_branch_src2 : unsigned(31 downto 0); + signal execute_BranchPlugin_branchAdder : unsigned(31 downto 0); + signal DebugPlugin_firstCycle : std_logic; + signal DebugPlugin_secondCycle : std_logic; + signal DebugPlugin_resetIt : std_logic; + signal DebugPlugin_haltIt : std_logic; + signal DebugPlugin_stepIt : std_logic; + signal DebugPlugin_isPipBusy : std_logic; + signal DebugPlugin_godmode : std_logic; + signal when_DebugPlugin_l225 : std_logic; + signal DebugPlugin_haltedByBreak : std_logic; + signal DebugPlugin_debugUsed : std_logic; + signal DebugPlugin_disableEbreak : std_logic; + signal DebugPlugin_allowEBreak : std_logic; + signal DebugPlugin_busReadDataReg : std_logic_vector(31 downto 0); + signal zz_when_DebugPlugin_l244 : std_logic; + signal when_DebugPlugin_l244 : std_logic; + signal switch_DebugPlugin_l267 : unsigned(5 downto 0); + signal when_DebugPlugin_l271 : std_logic; + signal when_DebugPlugin_l271_1 : std_logic; + signal when_DebugPlugin_l272 : std_logic; + signal when_DebugPlugin_l272_1 : std_logic; + signal when_DebugPlugin_l273 : std_logic; + signal when_DebugPlugin_l274 : std_logic; + signal when_DebugPlugin_l275 : std_logic; + signal when_DebugPlugin_l275_1 : std_logic; + signal when_DebugPlugin_l295 : std_logic; + signal when_DebugPlugin_l298 : std_logic; + signal when_DebugPlugin_l311 : std_logic; + signal DebugPlugin_resetIt_regNext : std_logic; + signal when_DebugPlugin_l331 : std_logic; + signal when_Pipeline_l124 : std_logic; + signal decode_to_execute_PC : unsigned(31 downto 0); + signal when_Pipeline_l124_1 : std_logic; + signal execute_to_memory_PC : unsigned(31 downto 0); + signal when_Pipeline_l124_2 : std_logic; + signal memory_to_writeBack_PC : unsigned(31 downto 0); + signal when_Pipeline_l124_3 : std_logic; + signal decode_to_execute_INSTRUCTION : std_logic_vector(31 downto 0); + signal when_Pipeline_l124_4 : std_logic; + signal execute_to_memory_INSTRUCTION : std_logic_vector(31 downto 0); + signal when_Pipeline_l124_5 : std_logic; + signal memory_to_writeBack_INSTRUCTION : std_logic_vector(31 downto 0); + signal when_Pipeline_l124_6 : std_logic; + signal decode_to_execute_FORMAL_PC_NEXT : unsigned(31 downto 0); + signal when_Pipeline_l124_7 : std_logic; + signal execute_to_memory_FORMAL_PC_NEXT : unsigned(31 downto 0); + signal when_Pipeline_l124_8 : std_logic; + signal memory_to_writeBack_FORMAL_PC_NEXT : unsigned(31 downto 0); + signal when_Pipeline_l124_9 : std_logic; + signal decode_to_execute_CSR_WRITE_OPCODE : std_logic; + signal when_Pipeline_l124_10 : std_logic; + signal decode_to_execute_CSR_READ_OPCODE : std_logic; + signal when_Pipeline_l124_11 : std_logic; + signal decode_to_execute_SRC_USE_SUB_LESS : std_logic; + signal when_Pipeline_l124_12 : std_logic; + signal decode_to_execute_MEMORY_ENABLE : std_logic; + signal when_Pipeline_l124_13 : std_logic; + signal execute_to_memory_MEMORY_ENABLE : std_logic; + signal when_Pipeline_l124_14 : std_logic; + signal memory_to_writeBack_MEMORY_ENABLE : std_logic; + signal when_Pipeline_l124_15 : std_logic; + signal decode_to_execute_REGFILE_WRITE_VALID : std_logic; + signal when_Pipeline_l124_16 : std_logic; + signal execute_to_memory_REGFILE_WRITE_VALID : std_logic; + signal when_Pipeline_l124_17 : std_logic; + signal memory_to_writeBack_REGFILE_WRITE_VALID : std_logic; + signal when_Pipeline_l124_18 : std_logic; + signal decode_to_execute_BYPASSABLE_EXECUTE_STAGE : std_logic; + signal when_Pipeline_l124_19 : std_logic; + signal decode_to_execute_BYPASSABLE_MEMORY_STAGE : std_logic; + signal when_Pipeline_l124_20 : std_logic; + signal execute_to_memory_BYPASSABLE_MEMORY_STAGE : std_logic; + signal when_Pipeline_l124_21 : std_logic; + signal decode_to_execute_MEMORY_STORE : std_logic; + signal when_Pipeline_l124_22 : std_logic; + signal execute_to_memory_MEMORY_STORE : std_logic; + signal when_Pipeline_l124_23 : std_logic; + signal decode_to_execute_IS_CSR : std_logic; + signal when_Pipeline_l124_24 : std_logic; + signal decode_to_execute_ENV_CTRL : EnvCtrlEnum_seq_type; + signal when_Pipeline_l124_25 : std_logic; + signal execute_to_memory_ENV_CTRL : EnvCtrlEnum_seq_type; + signal when_Pipeline_l124_26 : std_logic; + signal memory_to_writeBack_ENV_CTRL : EnvCtrlEnum_seq_type; + signal when_Pipeline_l124_27 : std_logic; + signal decode_to_execute_ALU_CTRL : AluCtrlEnum_seq_type; + signal when_Pipeline_l124_28 : std_logic; + signal decode_to_execute_SRC_LESS_UNSIGNED : std_logic; + signal when_Pipeline_l124_29 : std_logic; + signal decode_to_execute_ALU_BITWISE_CTRL : AluBitwiseCtrlEnum_seq_type; + signal when_Pipeline_l124_30 : std_logic; + signal decode_to_execute_SHIFT_CTRL : ShiftCtrlEnum_seq_type; + signal when_Pipeline_l124_31 : std_logic; + signal decode_to_execute_BRANCH_CTRL : BranchCtrlEnum_seq_type; + signal when_Pipeline_l124_32 : std_logic; + signal decode_to_execute_RS1 : std_logic_vector(31 downto 0); + signal when_Pipeline_l124_33 : std_logic; + signal decode_to_execute_RS2 : std_logic_vector(31 downto 0); + signal when_Pipeline_l124_34 : std_logic; + signal decode_to_execute_SRC2_FORCE_ZERO : std_logic; + signal when_Pipeline_l124_35 : std_logic; + signal decode_to_execute_SRC1 : std_logic_vector(31 downto 0); + signal when_Pipeline_l124_36 : std_logic; + signal decode_to_execute_SRC2 : std_logic_vector(31 downto 0); + signal when_Pipeline_l124_37 : std_logic; + signal decode_to_execute_DO_EBREAK : std_logic; + signal when_Pipeline_l124_38 : std_logic; + signal execute_to_memory_MEMORY_ADDRESS_LOW : unsigned(1 downto 0); + signal when_Pipeline_l124_39 : std_logic; + signal memory_to_writeBack_MEMORY_ADDRESS_LOW : unsigned(1 downto 0); + signal when_Pipeline_l124_40 : std_logic; + signal execute_to_memory_REGFILE_WRITE_DATA : std_logic_vector(31 downto 0); + signal when_Pipeline_l124_41 : std_logic; + signal memory_to_writeBack_REGFILE_WRITE_DATA : std_logic_vector(31 downto 0); + signal when_Pipeline_l124_42 : std_logic; + signal execute_to_memory_BRANCH_DO : std_logic; + signal when_Pipeline_l124_43 : std_logic; + signal execute_to_memory_BRANCH_CALC : unsigned(31 downto 0); + signal when_Pipeline_l124_44 : std_logic; + signal memory_to_writeBack_MEMORY_READ_DATA : std_logic_vector(31 downto 0); + signal when_Pipeline_l151 : std_logic; + signal when_Pipeline_l154 : std_logic; + signal when_Pipeline_l151_1 : std_logic; + signal when_Pipeline_l154_1 : std_logic; + signal when_Pipeline_l151_2 : std_logic; + signal when_Pipeline_l154_2 : std_logic; + signal switch_Fetcher_l365 : unsigned(2 downto 0); + signal when_Fetcher_l381 : std_logic; + signal when_Fetcher_l401 : std_logic; + signal when_CsrPlugin_l1277 : std_logic; + signal execute_CsrPlugin_csr_768 : std_logic; + signal when_CsrPlugin_l1277_1 : std_logic; + signal execute_CsrPlugin_csr_836 : std_logic; + signal when_CsrPlugin_l1277_2 : std_logic; + signal execute_CsrPlugin_csr_772 : std_logic; + signal when_CsrPlugin_l1277_3 : std_logic; + signal execute_CsrPlugin_csr_834 : std_logic; + signal switch_CsrPlugin_l723 : std_logic_vector(1 downto 0); + signal zz_CsrPlugin_csrMapping_readDataInit : std_logic_vector(31 downto 0); + signal zz_CsrPlugin_csrMapping_readDataInit_1 : std_logic_vector(31 downto 0); + signal zz_CsrPlugin_csrMapping_readDataInit_2 : std_logic_vector(31 downto 0); + signal zz_CsrPlugin_csrMapping_readDataInit_3 : std_logic_vector(31 downto 0); + signal when_CsrPlugin_l1310 : std_logic; + signal when_CsrPlugin_l1315 : std_logic; + type RegFilePlugin_regFile_type is array (0 to 31) of std_logic_vector(31 downto 0); + signal RegFilePlugin_regFile : RegFilePlugin_regFile_type; +begin + dBus_cmd_payload_address <= dBus_cmd_payload_address_read_buffer; + dBus_cmd_payload_size <= dBus_cmd_payload_size_read_buffer; + debug_bus_cmd_ready <= debug_bus_cmd_ready_read_buffer; + zz_decode_RegFilePlugin_rs1Data <= pkg_toStdLogic(true); + zz_decode_RegFilePlugin_rs2Data <= pkg_toStdLogic(true); + zz_zz_decode_BRANCH_CTRL_2 <= pkg_stdLogicVector("00010000000000000011000001010000"); + zz_zz_decode_BRANCH_CTRL_2_1 <= pkg_toStdLogic((decode_INSTRUCTION and pkg_stdLogicVector("00000000000000000000000000011100")) = pkg_stdLogicVector("00000000000000000000000000000100")); + zz_zz_decode_BRANCH_CTRL_2_2 <= pkg_toStdLogic((decode_INSTRUCTION and pkg_stdLogicVector("00000000000000000000000001011000")) = pkg_stdLogicVector("00000000000000000000000001000000")); + zz_zz_decode_BRANCH_CTRL_2_3 <= pkg_toStdLogicVector(pkg_toStdLogic((decode_INSTRUCTION and pkg_stdLogicVector("00000000000000000111000001010100")) = pkg_stdLogicVector("00000000000000000101000000010000"))); + zz_zz_decode_BRANCH_CTRL_2_4 <= pkg_stdLogicVector("0"); + zz_zz_decode_BRANCH_CTRL_2_5 <= pkg_toStdLogic(pkg_cat(pkg_toStdLogicVector(pkg_toStdLogic(zz_zz_decode_BRANCH_CTRL_2_6 = zz_zz_decode_BRANCH_CTRL_2_7)),pkg_toStdLogicVector(pkg_toStdLogic(zz_zz_decode_BRANCH_CTRL_2_8 = zz_zz_decode_BRANCH_CTRL_2_9))) /= pkg_stdLogicVector("00")); + zz_zz_decode_BRANCH_CTRL_2_10 <= pkg_toStdLogicVector(pkg_toStdLogic(pkg_cat(pkg_toStdLogicVector(zz_zz_decode_BRANCH_CTRL_2_11),pkg_toStdLogicVector(zz_zz_decode_BRANCH_CTRL_2_12)) /= pkg_stdLogicVector("00"))); + zz_zz_decode_BRANCH_CTRL_2_13 <= pkg_cat(pkg_toStdLogicVector(pkg_toStdLogic(pkg_toStdLogicVector(zz_zz_decode_BRANCH_CTRL_2_14) /= pkg_stdLogicVector("0"))),pkg_cat(pkg_toStdLogicVector(pkg_toStdLogic(zz_zz_decode_BRANCH_CTRL_2_15 /= zz_zz_decode_BRANCH_CTRL_2_17)),pkg_cat(pkg_toStdLogicVector(zz_zz_decode_BRANCH_CTRL_2_18),pkg_cat(zz_zz_decode_BRANCH_CTRL_2_21,zz_zz_decode_BRANCH_CTRL_2_26)))); + zz_zz_decode_BRANCH_CTRL_2_6 <= (decode_INSTRUCTION and pkg_stdLogicVector("01000000000000000011000001010100")); + zz_zz_decode_BRANCH_CTRL_2_7 <= pkg_stdLogicVector("01000000000000000001000000010000"); + zz_zz_decode_BRANCH_CTRL_2_8 <= (decode_INSTRUCTION and pkg_stdLogicVector("00000000000000000111000001010100")); + zz_zz_decode_BRANCH_CTRL_2_9 <= pkg_stdLogicVector("00000000000000000001000000010000"); + zz_zz_decode_BRANCH_CTRL_2_11 <= pkg_toStdLogic((decode_INSTRUCTION and pkg_stdLogicVector("00000000000000000000000001100100")) = pkg_stdLogicVector("00000000000000000000000000100100")); + zz_zz_decode_BRANCH_CTRL_2_12 <= pkg_toStdLogic((decode_INSTRUCTION and pkg_stdLogicVector("00000000000000000011000001010100")) = pkg_stdLogicVector("00000000000000000001000000010000")); + zz_zz_decode_BRANCH_CTRL_2_14 <= pkg_toStdLogic((decode_INSTRUCTION and pkg_stdLogicVector("00000000000000000001000000000000")) = pkg_stdLogicVector("00000000000000000001000000000000")); + zz_zz_decode_BRANCH_CTRL_2_15 <= pkg_toStdLogicVector(pkg_toStdLogic((decode_INSTRUCTION and zz_zz_decode_BRANCH_CTRL_2_16) = pkg_stdLogicVector("00000000000000000010000000000000"))); + zz_zz_decode_BRANCH_CTRL_2_17 <= pkg_stdLogicVector("0"); + zz_zz_decode_BRANCH_CTRL_2_18 <= pkg_toStdLogic(pkg_cat(pkg_toStdLogicVector(zz_zz_decode_BRANCH_CTRL_2_19),pkg_toStdLogicVector(zz_zz_decode_BRANCH_CTRL_2_20)) /= pkg_stdLogicVector("00")); + zz_zz_decode_BRANCH_CTRL_2_21 <= pkg_toStdLogicVector(pkg_toStdLogic(pkg_cat(zz_zz_decode_BRANCH_CTRL_2_22,zz_zz_decode_BRANCH_CTRL_2_24) /= pkg_stdLogicVector("00"))); + zz_zz_decode_BRANCH_CTRL_2_26 <= pkg_cat(pkg_toStdLogicVector(pkg_toStdLogic(zz_zz_decode_BRANCH_CTRL_2_27 /= zz_zz_decode_BRANCH_CTRL_2_28)),pkg_cat(pkg_toStdLogicVector(zz_zz_decode_BRANCH_CTRL_2_29),pkg_cat(zz_zz_decode_BRANCH_CTRL_2_32,zz_zz_decode_BRANCH_CTRL_2_37))); + zz_zz_decode_BRANCH_CTRL_2_16 <= pkg_stdLogicVector("00000000000000000011000000000000"); + zz_zz_decode_BRANCH_CTRL_2_19 <= pkg_toStdLogic((decode_INSTRUCTION and pkg_stdLogicVector("00000000000000000010000000010000")) = pkg_stdLogicVector("00000000000000000010000000000000")); + zz_zz_decode_BRANCH_CTRL_2_20 <= pkg_toStdLogic((decode_INSTRUCTION and pkg_stdLogicVector("00000000000000000101000000000000")) = pkg_stdLogicVector("00000000000000000001000000000000")); + zz_zz_decode_BRANCH_CTRL_2_22 <= pkg_toStdLogicVector(pkg_toStdLogic((decode_INSTRUCTION and zz_zz_decode_BRANCH_CTRL_2_23) = pkg_stdLogicVector("00000000000000000110000000000000"))); + zz_zz_decode_BRANCH_CTRL_2_24 <= pkg_toStdLogicVector(pkg_toStdLogic((decode_INSTRUCTION and zz_zz_decode_BRANCH_CTRL_2_25) = pkg_stdLogicVector("00000000000000000100000000000000"))); + zz_zz_decode_BRANCH_CTRL_2_27 <= pkg_toStdLogicVector(zz_decode_BRANCH_CTRL_4); + zz_zz_decode_BRANCH_CTRL_2_28 <= pkg_stdLogicVector("0"); + zz_zz_decode_BRANCH_CTRL_2_29 <= pkg_toStdLogic(pkg_toStdLogicVector(pkg_toStdLogic(zz_zz_decode_BRANCH_CTRL_2_30 = zz_zz_decode_BRANCH_CTRL_2_31)) /= pkg_stdLogicVector("0")); + zz_zz_decode_BRANCH_CTRL_2_32 <= pkg_toStdLogicVector(pkg_toStdLogic(pkg_cat(zz_zz_decode_BRANCH_CTRL_2_33,zz_zz_decode_BRANCH_CTRL_2_35) /= pkg_stdLogicVector("00"))); + zz_zz_decode_BRANCH_CTRL_2_37 <= pkg_cat(pkg_toStdLogicVector(pkg_toStdLogic(zz_zz_decode_BRANCH_CTRL_2_38 /= zz_zz_decode_BRANCH_CTRL_2_43)),pkg_cat(pkg_toStdLogicVector(zz_zz_decode_BRANCH_CTRL_2_44),pkg_cat(zz_zz_decode_BRANCH_CTRL_2_49,zz_zz_decode_BRANCH_CTRL_2_51))); + zz_zz_decode_BRANCH_CTRL_2_23 <= pkg_stdLogicVector("00000000000000000110000000000100"); + zz_zz_decode_BRANCH_CTRL_2_25 <= pkg_stdLogicVector("00000000000000000101000000000100"); + zz_zz_decode_BRANCH_CTRL_2_30 <= (decode_INSTRUCTION and pkg_stdLogicVector("00000000000100000011000001010000")); + zz_zz_decode_BRANCH_CTRL_2_31 <= pkg_stdLogicVector("00000000000000000000000001010000"); + zz_zz_decode_BRANCH_CTRL_2_33 <= pkg_toStdLogicVector(pkg_toStdLogic((decode_INSTRUCTION and zz_zz_decode_BRANCH_CTRL_2_34) = pkg_stdLogicVector("00000000000000000001000001010000"))); + zz_zz_decode_BRANCH_CTRL_2_35 <= pkg_toStdLogicVector(pkg_toStdLogic((decode_INSTRUCTION and zz_zz_decode_BRANCH_CTRL_2_36) = pkg_stdLogicVector("00000000000000000010000001010000"))); + zz_zz_decode_BRANCH_CTRL_2_38 <= pkg_cat(pkg_toStdLogicVector(pkg_toStdLogic(zz_zz_decode_BRANCH_CTRL_2_39 = zz_zz_decode_BRANCH_CTRL_2_40)),pkg_toStdLogicVector(pkg_toStdLogic(zz_zz_decode_BRANCH_CTRL_2_41 = zz_zz_decode_BRANCH_CTRL_2_42))); + zz_zz_decode_BRANCH_CTRL_2_43 <= pkg_stdLogicVector("00"); + zz_zz_decode_BRANCH_CTRL_2_44 <= pkg_toStdLogic(pkg_cat(pkg_toStdLogicVector(zz_zz_decode_BRANCH_CTRL_2_45),pkg_cat(zz_zz_decode_BRANCH_CTRL_2_46,zz_zz_decode_BRANCH_CTRL_2_47)) /= pkg_stdLogicVector("000")); + zz_zz_decode_BRANCH_CTRL_2_49 <= pkg_toStdLogicVector(pkg_toStdLogic(pkg_toStdLogicVector(zz_zz_decode_BRANCH_CTRL_2_50) /= pkg_stdLogicVector("0"))); + zz_zz_decode_BRANCH_CTRL_2_51 <= pkg_cat(pkg_toStdLogicVector(pkg_toStdLogic(zz_zz_decode_BRANCH_CTRL_2_52 /= zz_zz_decode_BRANCH_CTRL_2_54)),pkg_cat(pkg_toStdLogicVector(zz_zz_decode_BRANCH_CTRL_2_55),pkg_cat(zz_zz_decode_BRANCH_CTRL_2_56,zz_zz_decode_BRANCH_CTRL_2_67))); + zz_zz_decode_BRANCH_CTRL_2_34 <= pkg_stdLogicVector("00000000000000000001000001010000"); + zz_zz_decode_BRANCH_CTRL_2_36 <= pkg_stdLogicVector("00000000000000000010000001010000"); + zz_zz_decode_BRANCH_CTRL_2_39 <= (decode_INSTRUCTION and pkg_stdLogicVector("00000000000000000000000000110100")); + zz_zz_decode_BRANCH_CTRL_2_40 <= pkg_stdLogicVector("00000000000000000000000000100000"); + zz_zz_decode_BRANCH_CTRL_2_41 <= (decode_INSTRUCTION and pkg_stdLogicVector("00000000000000000000000001100100")); + zz_zz_decode_BRANCH_CTRL_2_42 <= pkg_stdLogicVector("00000000000000000000000000100000"); + zz_zz_decode_BRANCH_CTRL_2_45 <= pkg_toStdLogic((decode_INSTRUCTION and pkg_stdLogicVector("00000000000000000000000001010000")) = pkg_stdLogicVector("00000000000000000000000001000000")); + zz_zz_decode_BRANCH_CTRL_2_46 <= pkg_toStdLogicVector(zz_decode_BRANCH_CTRL_5); + zz_zz_decode_BRANCH_CTRL_2_47 <= pkg_toStdLogicVector(pkg_toStdLogic((decode_INSTRUCTION and zz_zz_decode_BRANCH_CTRL_2_48) = pkg_stdLogicVector("00000000000000000000000001000000"))); + zz_zz_decode_BRANCH_CTRL_2_50 <= pkg_toStdLogic((decode_INSTRUCTION and pkg_stdLogicVector("00000000000000000000000000100000")) = pkg_stdLogicVector("00000000000000000000000000100000")); + zz_zz_decode_BRANCH_CTRL_2_52 <= pkg_toStdLogicVector(pkg_toStdLogic((decode_INSTRUCTION and zz_zz_decode_BRANCH_CTRL_2_53) = pkg_stdLogicVector("00000000000000000000000000010000"))); + zz_zz_decode_BRANCH_CTRL_2_54 <= pkg_stdLogicVector("0"); + zz_zz_decode_BRANCH_CTRL_2_55 <= pkg_toStdLogic(pkg_toStdLogicVector(zz_decode_BRANCH_CTRL_7) /= pkg_stdLogicVector("0")); + zz_zz_decode_BRANCH_CTRL_2_56 <= pkg_toStdLogicVector(pkg_toStdLogic(pkg_cat(zz_zz_decode_BRANCH_CTRL_2_57,zz_zz_decode_BRANCH_CTRL_2_58) /= pkg_stdLogicVector("000000"))); + zz_zz_decode_BRANCH_CTRL_2_67 <= pkg_cat(pkg_toStdLogicVector(pkg_toStdLogic(zz_zz_decode_BRANCH_CTRL_2_68 /= zz_zz_decode_BRANCH_CTRL_2_71)),pkg_cat(pkg_toStdLogicVector(zz_zz_decode_BRANCH_CTRL_2_72),pkg_cat(zz_zz_decode_BRANCH_CTRL_2_75,zz_zz_decode_BRANCH_CTRL_2_83))); + zz_zz_decode_BRANCH_CTRL_2_48 <= pkg_stdLogicVector("00000000000100000011000001000000"); + zz_zz_decode_BRANCH_CTRL_2_53 <= pkg_stdLogicVector("00000000000000000000000000010000"); + zz_zz_decode_BRANCH_CTRL_2_57 <= pkg_toStdLogicVector(zz_decode_BRANCH_CTRL_8); + zz_zz_decode_BRANCH_CTRL_2_58 <= pkg_cat(pkg_toStdLogicVector(pkg_toStdLogic(zz_zz_decode_BRANCH_CTRL_2_59 = zz_zz_decode_BRANCH_CTRL_2_60)),pkg_cat(pkg_toStdLogicVector(zz_zz_decode_BRANCH_CTRL_2_61),pkg_cat(zz_zz_decode_BRANCH_CTRL_2_63,zz_zz_decode_BRANCH_CTRL_2_64))); + zz_zz_decode_BRANCH_CTRL_2_68 <= pkg_cat(pkg_toStdLogicVector(zz_decode_BRANCH_CTRL_6),pkg_toStdLogicVector(pkg_toStdLogic(zz_zz_decode_BRANCH_CTRL_2_69 = zz_zz_decode_BRANCH_CTRL_2_70))); + zz_zz_decode_BRANCH_CTRL_2_71 <= pkg_stdLogicVector("00"); + zz_zz_decode_BRANCH_CTRL_2_72 <= pkg_toStdLogic(pkg_cat(pkg_toStdLogicVector(zz_decode_BRANCH_CTRL_6),pkg_toStdLogicVector(zz_zz_decode_BRANCH_CTRL_2_73)) /= pkg_stdLogicVector("00")); + zz_zz_decode_BRANCH_CTRL_2_75 <= pkg_toStdLogicVector(pkg_toStdLogic(pkg_cat(zz_zz_decode_BRANCH_CTRL_2_76,zz_zz_decode_BRANCH_CTRL_2_79) /= pkg_stdLogicVector("0000"))); + zz_zz_decode_BRANCH_CTRL_2_83 <= pkg_cat(pkg_toStdLogicVector(pkg_toStdLogic(zz_zz_decode_BRANCH_CTRL_2_84 /= zz_zz_decode_BRANCH_CTRL_2_87)),pkg_cat(pkg_toStdLogicVector(zz_zz_decode_BRANCH_CTRL_2_88),pkg_cat(zz_zz_decode_BRANCH_CTRL_2_96,zz_zz_decode_BRANCH_CTRL_2_101))); + zz_zz_decode_BRANCH_CTRL_2_59 <= (decode_INSTRUCTION and pkg_stdLogicVector("00000000000000000001000000010000")); + zz_zz_decode_BRANCH_CTRL_2_60 <= pkg_stdLogicVector("00000000000000000001000000010000"); + zz_zz_decode_BRANCH_CTRL_2_61 <= pkg_toStdLogic((decode_INSTRUCTION and zz_zz_decode_BRANCH_CTRL_2_62) = pkg_stdLogicVector("00000000000000000010000000010000")); + zz_zz_decode_BRANCH_CTRL_2_63 <= pkg_toStdLogicVector(zz_decode_BRANCH_CTRL_7); + zz_zz_decode_BRANCH_CTRL_2_64 <= pkg_cat(pkg_toStdLogicVector(zz_zz_decode_BRANCH_CTRL_2_65),pkg_toStdLogicVector(zz_zz_decode_BRANCH_CTRL_2_66)); + zz_zz_decode_BRANCH_CTRL_2_69 <= (decode_INSTRUCTION and pkg_stdLogicVector("00000000000000000000000001110000")); + zz_zz_decode_BRANCH_CTRL_2_70 <= pkg_stdLogicVector("00000000000000000000000000100000"); + zz_zz_decode_BRANCH_CTRL_2_73 <= pkg_toStdLogic((decode_INSTRUCTION and zz_zz_decode_BRANCH_CTRL_2_74) = pkg_stdLogicVector("00000000000000000000000000000000")); + zz_zz_decode_BRANCH_CTRL_2_76 <= pkg_toStdLogicVector(pkg_toStdLogic(zz_zz_decode_BRANCH_CTRL_2_77 = zz_zz_decode_BRANCH_CTRL_2_78)); + zz_zz_decode_BRANCH_CTRL_2_79 <= pkg_cat(pkg_toStdLogicVector(zz_decode_BRANCH_CTRL_5),pkg_cat(zz_zz_decode_BRANCH_CTRL_2_80,zz_zz_decode_BRANCH_CTRL_2_81)); + zz_zz_decode_BRANCH_CTRL_2_84 <= pkg_toStdLogicVector(pkg_toStdLogic(zz_zz_decode_BRANCH_CTRL_2_85 = zz_zz_decode_BRANCH_CTRL_2_86)); + zz_zz_decode_BRANCH_CTRL_2_87 <= pkg_stdLogicVector("0"); + zz_zz_decode_BRANCH_CTRL_2_88 <= pkg_toStdLogic(pkg_cat(zz_zz_decode_BRANCH_CTRL_2_89,zz_zz_decode_BRANCH_CTRL_2_91) /= pkg_stdLogicVector("000")); + zz_zz_decode_BRANCH_CTRL_2_96 <= pkg_toStdLogicVector(pkg_toStdLogic(zz_zz_decode_BRANCH_CTRL_2_97 /= zz_zz_decode_BRANCH_CTRL_2_100)); + zz_zz_decode_BRANCH_CTRL_2_101 <= pkg_toStdLogicVector(pkg_toStdLogic(zz_zz_decode_BRANCH_CTRL_2_102 /= zz_zz_decode_BRANCH_CTRL_2_105)); + zz_zz_decode_BRANCH_CTRL_2_62 <= pkg_stdLogicVector("00000000000000000010000000010000"); + zz_zz_decode_BRANCH_CTRL_2_65 <= pkg_toStdLogic((decode_INSTRUCTION and pkg_stdLogicVector("00000000000000000000000000001100")) = pkg_stdLogicVector("00000000000000000000000000000100")); + zz_zz_decode_BRANCH_CTRL_2_66 <= pkg_toStdLogic((decode_INSTRUCTION and pkg_stdLogicVector("00000000000000000000000000101000")) = pkg_stdLogicVector("00000000000000000000000000000000")); + zz_zz_decode_BRANCH_CTRL_2_74 <= pkg_stdLogicVector("00000000000000000000000000100000"); + zz_zz_decode_BRANCH_CTRL_2_77 <= (decode_INSTRUCTION and pkg_stdLogicVector("00000000000000000000000001000100")); + zz_zz_decode_BRANCH_CTRL_2_78 <= pkg_stdLogicVector("00000000000000000000000000000000"); + zz_zz_decode_BRANCH_CTRL_2_80 <= pkg_toStdLogicVector(zz_decode_BRANCH_CTRL_4); + zz_zz_decode_BRANCH_CTRL_2_81 <= pkg_toStdLogicVector(pkg_toStdLogic((decode_INSTRUCTION and zz_zz_decode_BRANCH_CTRL_2_82) = pkg_stdLogicVector("00000000000000000001000000000000"))); + zz_zz_decode_BRANCH_CTRL_2_85 <= (decode_INSTRUCTION and pkg_stdLogicVector("00000000000000000000000001011000")); + zz_zz_decode_BRANCH_CTRL_2_86 <= pkg_stdLogicVector("00000000000000000000000000000000"); + zz_zz_decode_BRANCH_CTRL_2_89 <= pkg_toStdLogicVector(pkg_toStdLogic((decode_INSTRUCTION and zz_zz_decode_BRANCH_CTRL_2_90) = pkg_stdLogicVector("00000000000000000000000001000000"))); + zz_zz_decode_BRANCH_CTRL_2_91 <= pkg_cat(pkg_toStdLogicVector(pkg_toStdLogic(zz_zz_decode_BRANCH_CTRL_2_92 = zz_zz_decode_BRANCH_CTRL_2_93)),pkg_toStdLogicVector(pkg_toStdLogic(zz_zz_decode_BRANCH_CTRL_2_94 = zz_zz_decode_BRANCH_CTRL_2_95))); + zz_zz_decode_BRANCH_CTRL_2_97 <= pkg_cat(pkg_toStdLogicVector(pkg_toStdLogic(zz_zz_decode_BRANCH_CTRL_2_98 = zz_zz_decode_BRANCH_CTRL_2_99)),pkg_toStdLogicVector(zz_decode_BRANCH_CTRL_3)); + zz_zz_decode_BRANCH_CTRL_2_100 <= pkg_stdLogicVector("00"); + zz_zz_decode_BRANCH_CTRL_2_102 <= pkg_cat(pkg_toStdLogicVector(pkg_toStdLogic(zz_zz_decode_BRANCH_CTRL_2_103 = zz_zz_decode_BRANCH_CTRL_2_104)),pkg_toStdLogicVector(zz_decode_BRANCH_CTRL_3)); + zz_zz_decode_BRANCH_CTRL_2_105 <= pkg_stdLogicVector("00"); + zz_zz_decode_BRANCH_CTRL_2_82 <= pkg_stdLogicVector("00000000000000000101000000000100"); + zz_zz_decode_BRANCH_CTRL_2_90 <= pkg_stdLogicVector("00000000000000000000000001000100"); + zz_zz_decode_BRANCH_CTRL_2_92 <= (decode_INSTRUCTION and pkg_stdLogicVector("00000000000000000010000000010100")); + zz_zz_decode_BRANCH_CTRL_2_93 <= pkg_stdLogicVector("00000000000000000010000000010000"); + zz_zz_decode_BRANCH_CTRL_2_94 <= (decode_INSTRUCTION and pkg_stdLogicVector("01000000000000000100000000110100")); + zz_zz_decode_BRANCH_CTRL_2_95 <= pkg_stdLogicVector("01000000000000000000000000110000"); + zz_zz_decode_BRANCH_CTRL_2_98 <= (decode_INSTRUCTION and pkg_stdLogicVector("00000000000000000000000000010100")); + zz_zz_decode_BRANCH_CTRL_2_99 <= pkg_stdLogicVector("00000000000000000000000000000100"); + zz_zz_decode_BRANCH_CTRL_2_103 <= (decode_INSTRUCTION and pkg_stdLogicVector("00000000000000000000000001000100")); + zz_zz_decode_BRANCH_CTRL_2_104 <= pkg_stdLogicVector("00000000000000000000000000000100"); + process(io_mainClk) + begin + if rising_edge(io_mainClk) then + if zz_decode_RegFilePlugin_rs1Data = '1' then + zz_RegFilePlugin_regFile_port0 <= RegFilePlugin_regFile(to_integer(decode_RegFilePlugin_regFileReadAddress1)); + end if; + end if; + end process; + + process(io_mainClk) + begin + if rising_edge(io_mainClk) then + if zz_decode_RegFilePlugin_rs2Data = '1' then + zz_RegFilePlugin_regFile_port0_1 <= RegFilePlugin_regFile(to_integer(decode_RegFilePlugin_regFileReadAddress2)); + end if; + end if; + end process; + + process(io_mainClk) + begin + if rising_edge(io_mainClk) then + if zz_1 = '1' then + RegFilePlugin_regFile(to_integer(lastStageRegFileWrite_payload_address)) <= lastStageRegFileWrite_payload_data; + end if; + end if; + end process; + + IBusSimplePlugin_rspJoin_rspBuffer_c : entity work.StreamFifoLowLatency + port map ( + io_push_valid => iBus_rsp_toStream_valid, + io_push_ready => IBusSimplePlugin_rspJoin_rspBuffer_c_io_push_ready, + io_push_payload_error => iBus_rsp_toStream_payload_error, + io_push_payload_inst => iBus_rsp_toStream_payload_inst, + io_pop_valid => IBusSimplePlugin_rspJoin_rspBuffer_c_io_pop_valid, + io_pop_ready => IBusSimplePlugin_rspJoin_rspBuffer_c_io_pop_ready, + io_pop_payload_error => IBusSimplePlugin_rspJoin_rspBuffer_c_io_pop_payload_error, + io_pop_payload_inst => IBusSimplePlugin_rspJoin_rspBuffer_c_io_pop_payload_inst, + io_flush => pkg_toStdLogic(false), + io_occupancy => IBusSimplePlugin_rspJoin_rspBuffer_c_io_occupancy, + io_mainClk => io_mainClk, + resetCtrl_systemReset => resetCtrl_systemReset + ); + memory_MEMORY_READ_DATA <= dBus_rsp_data; + execute_BRANCH_CALC <= unsigned(pkg_cat(std_logic_vector(pkg_extract(execute_BranchPlugin_branchAdder,31,1)),std_logic_vector(pkg_unsigned("0")))); + execute_BRANCH_DO <= zz_execute_BRANCH_DO_1; + writeBack_REGFILE_WRITE_DATA <= memory_to_writeBack_REGFILE_WRITE_DATA; + execute_REGFILE_WRITE_DATA <= zz_execute_REGFILE_WRITE_DATA; + memory_MEMORY_ADDRESS_LOW <= execute_to_memory_MEMORY_ADDRESS_LOW; + execute_MEMORY_ADDRESS_LOW <= pkg_extract(dBus_cmd_payload_address_read_buffer,1,0); + decode_DO_EBREAK <= (((not DebugPlugin_haltIt) and (decode_IS_EBREAK or pkg_toStdLogic(false))) and DebugPlugin_allowEBreak); + decode_SRC2 <= zz_decode_SRC2_6; + decode_SRC1 <= zz_decode_SRC1_1; + decode_SRC2_FORCE_ZERO <= (decode_SRC_ADD_ZERO and (not decode_SRC_USE_SUB_LESS)); + decode_RS2 <= decode_RegFilePlugin_rs2Data; + decode_RS1 <= decode_RegFilePlugin_rs1Data; + decode_BRANCH_CTRL <= zz_decode_BRANCH_CTRL; + zz_decode_to_execute_BRANCH_CTRL <= zz_decode_to_execute_BRANCH_CTRL_1; + decode_SHIFT_CTRL <= zz_decode_SHIFT_CTRL; + zz_decode_to_execute_SHIFT_CTRL <= zz_decode_to_execute_SHIFT_CTRL_1; + decode_ALU_BITWISE_CTRL <= zz_decode_ALU_BITWISE_CTRL; + zz_decode_to_execute_ALU_BITWISE_CTRL <= zz_decode_to_execute_ALU_BITWISE_CTRL_1; + decode_SRC_LESS_UNSIGNED <= pkg_extract(zz_decode_BRANCH_CTRL_2,17); + decode_ALU_CTRL <= zz_decode_ALU_CTRL; + zz_decode_to_execute_ALU_CTRL <= zz_decode_to_execute_ALU_CTRL_1; + zz_memory_to_writeBack_ENV_CTRL <= zz_memory_to_writeBack_ENV_CTRL_1; + zz_execute_to_memory_ENV_CTRL <= zz_execute_to_memory_ENV_CTRL_1; + decode_ENV_CTRL <= zz_decode_ENV_CTRL; + zz_decode_to_execute_ENV_CTRL <= zz_decode_to_execute_ENV_CTRL_1; + decode_IS_CSR <= pkg_extract(zz_decode_BRANCH_CTRL_2,13); + decode_MEMORY_STORE <= pkg_extract(zz_decode_BRANCH_CTRL_2,10); + execute_BYPASSABLE_MEMORY_STAGE <= decode_to_execute_BYPASSABLE_MEMORY_STAGE; + decode_BYPASSABLE_MEMORY_STAGE <= pkg_extract(zz_decode_BRANCH_CTRL_2,9); + decode_BYPASSABLE_EXECUTE_STAGE <= pkg_extract(zz_decode_BRANCH_CTRL_2,8); + decode_MEMORY_ENABLE <= pkg_extract(zz_decode_BRANCH_CTRL_2,3); + decode_CSR_READ_OPCODE <= pkg_toStdLogic(pkg_extract(decode_INSTRUCTION,13,7) /= pkg_stdLogicVector("0100000")); + decode_CSR_WRITE_OPCODE <= (not ((pkg_toStdLogic(pkg_extract(decode_INSTRUCTION,14,13) = pkg_stdLogicVector("01")) and pkg_toStdLogic(pkg_extract(decode_INSTRUCTION,19,15) = pkg_stdLogicVector("00000"))) or (pkg_toStdLogic(pkg_extract(decode_INSTRUCTION,14,13) = pkg_stdLogicVector("11")) and pkg_toStdLogic(pkg_extract(decode_INSTRUCTION,19,15) = pkg_stdLogicVector("00000"))))); + writeBack_FORMAL_PC_NEXT <= memory_to_writeBack_FORMAL_PC_NEXT; + memory_FORMAL_PC_NEXT <= execute_to_memory_FORMAL_PC_NEXT; + execute_FORMAL_PC_NEXT <= decode_to_execute_FORMAL_PC_NEXT; + decode_FORMAL_PC_NEXT <= (decode_PC + pkg_unsigned("00000000000000000000000000000100")); + memory_PC <= execute_to_memory_PC; + execute_DO_EBREAK <= decode_to_execute_DO_EBREAK; + decode_IS_EBREAK <= pkg_extract(zz_decode_BRANCH_CTRL_2,25); + memory_BRANCH_CALC <= execute_to_memory_BRANCH_CALC; + memory_BRANCH_DO <= execute_to_memory_BRANCH_DO; + execute_PC <= decode_to_execute_PC; + execute_RS1 <= decode_to_execute_RS1; + execute_BRANCH_CTRL <= zz_execute_BRANCH_CTRL; + decode_RS2_USE <= pkg_extract(zz_decode_BRANCH_CTRL_2,12); + decode_RS1_USE <= pkg_extract(zz_decode_BRANCH_CTRL_2,4); + execute_REGFILE_WRITE_VALID <= decode_to_execute_REGFILE_WRITE_VALID; + execute_BYPASSABLE_EXECUTE_STAGE <= decode_to_execute_BYPASSABLE_EXECUTE_STAGE; + memory_REGFILE_WRITE_VALID <= execute_to_memory_REGFILE_WRITE_VALID; + memory_INSTRUCTION <= execute_to_memory_INSTRUCTION; + memory_BYPASSABLE_MEMORY_STAGE <= execute_to_memory_BYPASSABLE_MEMORY_STAGE; + writeBack_REGFILE_WRITE_VALID <= memory_to_writeBack_REGFILE_WRITE_VALID; + memory_REGFILE_WRITE_DATA <= execute_to_memory_REGFILE_WRITE_DATA; + execute_SHIFT_CTRL <= zz_execute_SHIFT_CTRL; + execute_SRC_LESS_UNSIGNED <= decode_to_execute_SRC_LESS_UNSIGNED; + execute_SRC2_FORCE_ZERO <= decode_to_execute_SRC2_FORCE_ZERO; + execute_SRC_USE_SUB_LESS <= decode_to_execute_SRC_USE_SUB_LESS; + zz_decode_SRC2 <= decode_PC; + zz_decode_SRC2_1 <= decode_RS2; + decode_SRC2_CTRL <= zz_decode_SRC2_CTRL; + zz_decode_SRC1 <= decode_RS1; + decode_SRC1_CTRL <= zz_decode_SRC1_CTRL; + decode_SRC_USE_SUB_LESS <= pkg_extract(zz_decode_BRANCH_CTRL_2,2); + decode_SRC_ADD_ZERO <= pkg_extract(zz_decode_BRANCH_CTRL_2,20); + execute_SRC_ADD_SUB <= execute_SrcPlugin_addSub; + execute_SRC_LESS <= execute_SrcPlugin_less; + execute_ALU_CTRL <= zz_execute_ALU_CTRL; + execute_SRC2 <= decode_to_execute_SRC2; + execute_ALU_BITWISE_CTRL <= zz_execute_ALU_BITWISE_CTRL; + zz_lastStageRegFileWrite_payload_address <= writeBack_INSTRUCTION; + zz_lastStageRegFileWrite_valid <= writeBack_REGFILE_WRITE_VALID; + process(lastStageRegFileWrite_valid) + begin + zz_1 <= pkg_toStdLogic(false); + if lastStageRegFileWrite_valid = '1' then + zz_1 <= pkg_toStdLogic(true); + end if; + end process; + + decode_INSTRUCTION_ANTICIPATED <= pkg_mux(decode_arbitration_isStuck,decode_INSTRUCTION,IBusSimplePlugin_iBusRsp_output_payload_rsp_inst); + process(zz_decode_BRANCH_CTRL_2,when_RegFilePlugin_l63) + begin + decode_REGFILE_WRITE_VALID <= pkg_extract(zz_decode_BRANCH_CTRL_2,7); + if when_RegFilePlugin_l63 = '1' then + decode_REGFILE_WRITE_VALID <= pkg_toStdLogic(false); + end if; + end process; + + process(execute_REGFILE_WRITE_DATA,when_CsrPlugin_l1189,CsrPlugin_csrMapping_readDataSignal,when_ShiftPlugins_l169,zz_execute_to_memory_REGFILE_WRITE_DATA_1) + begin + zz_execute_to_memory_REGFILE_WRITE_DATA <= execute_REGFILE_WRITE_DATA; + if when_CsrPlugin_l1189 = '1' then + zz_execute_to_memory_REGFILE_WRITE_DATA <= CsrPlugin_csrMapping_readDataSignal; + end if; + if when_ShiftPlugins_l169 = '1' then + zz_execute_to_memory_REGFILE_WRITE_DATA <= zz_execute_to_memory_REGFILE_WRITE_DATA_1; + end if; + end process; + + execute_SRC1 <= decode_to_execute_SRC1; + execute_CSR_READ_OPCODE <= decode_to_execute_CSR_READ_OPCODE; + execute_CSR_WRITE_OPCODE <= decode_to_execute_CSR_WRITE_OPCODE; + execute_IS_CSR <= decode_to_execute_IS_CSR; + memory_ENV_CTRL <= zz_memory_ENV_CTRL; + execute_ENV_CTRL <= zz_execute_ENV_CTRL; + writeBack_ENV_CTRL <= zz_writeBack_ENV_CTRL; + process(writeBack_REGFILE_WRITE_DATA,when_DBusSimplePlugin_l558,writeBack_DBusSimplePlugin_rspFormated) + begin + zz_lastStageRegFileWrite_payload_data <= writeBack_REGFILE_WRITE_DATA; + if when_DBusSimplePlugin_l558 = '1' then + zz_lastStageRegFileWrite_payload_data <= writeBack_DBusSimplePlugin_rspFormated; + end if; + end process; + + writeBack_MEMORY_ENABLE <= memory_to_writeBack_MEMORY_ENABLE; + writeBack_MEMORY_ADDRESS_LOW <= memory_to_writeBack_MEMORY_ADDRESS_LOW; + writeBack_MEMORY_READ_DATA <= memory_to_writeBack_MEMORY_READ_DATA; + memory_MEMORY_STORE <= execute_to_memory_MEMORY_STORE; + memory_MEMORY_ENABLE <= execute_to_memory_MEMORY_ENABLE; + execute_SRC_ADD <= execute_SrcPlugin_addSub; + execute_RS2 <= decode_to_execute_RS2; + execute_INSTRUCTION <= decode_to_execute_INSTRUCTION; + execute_MEMORY_STORE <= decode_to_execute_MEMORY_STORE; + execute_MEMORY_ENABLE <= decode_to_execute_MEMORY_ENABLE; + execute_ALIGNEMENT_FAULT <= pkg_toStdLogic(false); + process(memory_FORMAL_PC_NEXT,BranchPlugin_jumpInterface_valid,BranchPlugin_jumpInterface_payload) + begin + zz_memory_to_writeBack_FORMAL_PC_NEXT <= memory_FORMAL_PC_NEXT; + if BranchPlugin_jumpInterface_valid = '1' then + zz_memory_to_writeBack_FORMAL_PC_NEXT <= BranchPlugin_jumpInterface_payload; + end if; + end process; + + decode_PC <= IBusSimplePlugin_injector_decodeInput_payload_pc; + decode_INSTRUCTION <= IBusSimplePlugin_injector_decodeInput_payload_rsp_inst; + writeBack_PC <= memory_to_writeBack_PC; + writeBack_INSTRUCTION <= memory_to_writeBack_INSTRUCTION; + process(switch_Fetcher_l365) + begin + decode_arbitration_haltItself <= pkg_toStdLogic(false); + case switch_Fetcher_l365 is + when "010" => + decode_arbitration_haltItself <= pkg_toStdLogic(true); + when others => + end case; + end process; + + process(CsrPlugin_pipelineLiberator_active,when_CsrPlugin_l1129,when_HazardSimplePlugin_l113) + begin + decode_arbitration_haltByOther <= pkg_toStdLogic(false); + if CsrPlugin_pipelineLiberator_active = '1' then + decode_arbitration_haltByOther <= pkg_toStdLogic(true); + end if; + if when_CsrPlugin_l1129 = '1' then + decode_arbitration_haltByOther <= pkg_toStdLogic(true); + end if; + if when_HazardSimplePlugin_l113 = '1' then + decode_arbitration_haltByOther <= pkg_toStdLogic(true); + end if; + end process; + + process(decode_arbitration_isFlushed) + begin + decode_arbitration_removeIt <= pkg_toStdLogic(false); + if decode_arbitration_isFlushed = '1' then + decode_arbitration_removeIt <= pkg_toStdLogic(true); + end if; + end process; + + decode_arbitration_flushIt <= pkg_toStdLogic(false); + decode_arbitration_flushNext <= pkg_toStdLogic(false); + process(when_DBusSimplePlugin_l428,when_CsrPlugin_l1193,execute_CsrPlugin_blockedBySideEffects,when_ShiftPlugins_l169,when_ShiftPlugins_l184) + begin + execute_arbitration_haltItself <= pkg_toStdLogic(false); + if when_DBusSimplePlugin_l428 = '1' then + execute_arbitration_haltItself <= pkg_toStdLogic(true); + end if; + if when_CsrPlugin_l1193 = '1' then + if execute_CsrPlugin_blockedBySideEffects = '1' then + execute_arbitration_haltItself <= pkg_toStdLogic(true); + end if; + end if; + if when_ShiftPlugins_l169 = '1' then + if when_ShiftPlugins_l184 = '1' then + execute_arbitration_haltItself <= pkg_toStdLogic(true); + end if; + end if; + end process; + + process(when_DebugPlugin_l295) + begin + execute_arbitration_haltByOther <= pkg_toStdLogic(false); + if when_DebugPlugin_l295 = '1' then + execute_arbitration_haltByOther <= pkg_toStdLogic(true); + end if; + end process; + + process(execute_arbitration_isFlushed) + begin + execute_arbitration_removeIt <= pkg_toStdLogic(false); + if execute_arbitration_isFlushed = '1' then + execute_arbitration_removeIt <= pkg_toStdLogic(true); + end if; + end process; + + process(when_DebugPlugin_l295,when_DebugPlugin_l298) + begin + execute_arbitration_flushIt <= pkg_toStdLogic(false); + if when_DebugPlugin_l295 = '1' then + if when_DebugPlugin_l298 = '1' then + execute_arbitration_flushIt <= pkg_toStdLogic(true); + end if; + end if; + end process; + + process(when_DebugPlugin_l295,when_DebugPlugin_l298) + begin + execute_arbitration_flushNext <= pkg_toStdLogic(false); + if when_DebugPlugin_l295 = '1' then + if when_DebugPlugin_l298 = '1' then + execute_arbitration_flushNext <= pkg_toStdLogic(true); + end if; + end if; + end process; + + process(when_DBusSimplePlugin_l482) + begin + memory_arbitration_haltItself <= pkg_toStdLogic(false); + if when_DBusSimplePlugin_l482 = '1' then + memory_arbitration_haltItself <= pkg_toStdLogic(true); + end if; + end process; + + memory_arbitration_haltByOther <= pkg_toStdLogic(false); + process(memory_arbitration_isFlushed) + begin + memory_arbitration_removeIt <= pkg_toStdLogic(false); + if memory_arbitration_isFlushed = '1' then + memory_arbitration_removeIt <= pkg_toStdLogic(true); + end if; + end process; + + memory_arbitration_flushIt <= pkg_toStdLogic(false); + process(BranchPlugin_jumpInterface_valid) + begin + memory_arbitration_flushNext <= pkg_toStdLogic(false); + if BranchPlugin_jumpInterface_valid = '1' then + memory_arbitration_flushNext <= pkg_toStdLogic(true); + end if; + end process; + + writeBack_arbitration_haltItself <= pkg_toStdLogic(false); + writeBack_arbitration_haltByOther <= pkg_toStdLogic(false); + process(writeBack_arbitration_isFlushed) + begin + writeBack_arbitration_removeIt <= pkg_toStdLogic(false); + if writeBack_arbitration_isFlushed = '1' then + writeBack_arbitration_removeIt <= pkg_toStdLogic(true); + end if; + end process; + + writeBack_arbitration_flushIt <= pkg_toStdLogic(false); + process(when_CsrPlugin_l1032,when_CsrPlugin_l1077) + begin + writeBack_arbitration_flushNext <= pkg_toStdLogic(false); + if when_CsrPlugin_l1032 = '1' then + writeBack_arbitration_flushNext <= pkg_toStdLogic(true); + end if; + if when_CsrPlugin_l1077 = '1' then + writeBack_arbitration_flushNext <= pkg_toStdLogic(true); + end if; + end process; + + lastStageInstruction <= writeBack_INSTRUCTION; + lastStagePc <= writeBack_PC; + lastStageIsValid <= writeBack_arbitration_isValid; + lastStageIsFiring <= writeBack_arbitration_isFiring; + process(when_CsrPlugin_l1032,when_CsrPlugin_l1077,when_DebugPlugin_l295,when_DebugPlugin_l298,DebugPlugin_haltIt,when_DebugPlugin_l311) + begin + IBusSimplePlugin_fetcherHalt <= pkg_toStdLogic(false); + if when_CsrPlugin_l1032 = '1' then + IBusSimplePlugin_fetcherHalt <= pkg_toStdLogic(true); + end if; + if when_CsrPlugin_l1077 = '1' then + IBusSimplePlugin_fetcherHalt <= pkg_toStdLogic(true); + end if; + if when_DebugPlugin_l295 = '1' then + if when_DebugPlugin_l298 = '1' then + IBusSimplePlugin_fetcherHalt <= pkg_toStdLogic(true); + end if; + end if; + if DebugPlugin_haltIt = '1' then + IBusSimplePlugin_fetcherHalt <= pkg_toStdLogic(true); + end if; + if when_DebugPlugin_l311 = '1' then + IBusSimplePlugin_fetcherHalt <= pkg_toStdLogic(true); + end if; + end process; + + IBusSimplePlugin_forceNoDecodeCond <= pkg_toStdLogic(false); + process(when_Fetcher_l243,IBusSimplePlugin_injector_decodeInput_valid) + begin + IBusSimplePlugin_incomingInstruction <= pkg_toStdLogic(false); + if when_Fetcher_l243 = '1' then + IBusSimplePlugin_incomingInstruction <= pkg_toStdLogic(true); + end if; + if IBusSimplePlugin_injector_decodeInput_valid = '1' then + IBusSimplePlugin_incomingInstruction <= pkg_toStdLogic(true); + end if; + end process; + + CsrPlugin_csrMapping_allowCsrSignal <= pkg_toStdLogic(false); + CsrPlugin_csrMapping_readDataSignal <= CsrPlugin_csrMapping_readDataInit; + CsrPlugin_inWfi <= pkg_toStdLogic(false); + process(DebugPlugin_haltIt) + begin + CsrPlugin_thirdPartyWake <= pkg_toStdLogic(false); + if DebugPlugin_haltIt = '1' then + CsrPlugin_thirdPartyWake <= pkg_toStdLogic(true); + end if; + end process; + + process(when_CsrPlugin_l1032,when_CsrPlugin_l1077) + begin + CsrPlugin_jumpInterface_valid <= pkg_toStdLogic(false); + if when_CsrPlugin_l1032 = '1' then + CsrPlugin_jumpInterface_valid <= pkg_toStdLogic(true); + end if; + if when_CsrPlugin_l1077 = '1' then + CsrPlugin_jumpInterface_valid <= pkg_toStdLogic(true); + end if; + end process; + + process(when_CsrPlugin_l1032,CsrPlugin_xtvec_base,when_CsrPlugin_l1077,switch_CsrPlugin_l1081,CsrPlugin_mepc) + begin + CsrPlugin_jumpInterface_payload <= pkg_unsigned("XXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX"); + if when_CsrPlugin_l1032 = '1' then + CsrPlugin_jumpInterface_payload <= unsigned(pkg_cat(std_logic_vector(CsrPlugin_xtvec_base),std_logic_vector(pkg_unsigned("00")))); + end if; + if when_CsrPlugin_l1077 = '1' then + case switch_CsrPlugin_l1081 is + when "11" => + CsrPlugin_jumpInterface_payload <= CsrPlugin_mepc; + when others => + end case; + end if; + end process; + + process(DebugPlugin_godmode) + begin + CsrPlugin_forceMachineWire <= pkg_toStdLogic(false); + if DebugPlugin_godmode = '1' then + CsrPlugin_forceMachineWire <= pkg_toStdLogic(true); + end if; + end process; + + process(when_DebugPlugin_l331) + begin + CsrPlugin_allowInterrupts <= pkg_toStdLogic(true); + if when_DebugPlugin_l331 = '1' then + CsrPlugin_allowInterrupts <= pkg_toStdLogic(false); + end if; + end process; + + process(DebugPlugin_godmode) + begin + CsrPlugin_allowException <= pkg_toStdLogic(true); + if DebugPlugin_godmode = '1' then + CsrPlugin_allowException <= pkg_toStdLogic(false); + end if; + end process; + + process(DebugPlugin_allowEBreak) + begin + CsrPlugin_allowEbreakException <= pkg_toStdLogic(true); + if DebugPlugin_allowEBreak = '1' then + CsrPlugin_allowEbreakException <= pkg_toStdLogic(false); + end if; + end process; + + process(DebugPlugin_godmode) + begin + BranchPlugin_inDebugNoFetchFlag <= pkg_toStdLogic(false); + if DebugPlugin_godmode = '1' then + BranchPlugin_inDebugNoFetchFlag <= pkg_toStdLogic(true); + end if; + end process; + + IBusSimplePlugin_externalFlush <= pkg_toStdLogic(pkg_cat(pkg_toStdLogicVector(writeBack_arbitration_flushNext),pkg_cat(pkg_toStdLogicVector(memory_arbitration_flushNext),pkg_cat(pkg_toStdLogicVector(execute_arbitration_flushNext),pkg_toStdLogicVector(decode_arbitration_flushNext)))) /= pkg_stdLogicVector("0000")); + IBusSimplePlugin_jump_pcLoad_valid <= pkg_toStdLogic(pkg_cat(pkg_toStdLogicVector(BranchPlugin_jumpInterface_valid),pkg_toStdLogicVector(CsrPlugin_jumpInterface_valid)) /= pkg_stdLogicVector("00")); + zz_IBusSimplePlugin_jump_pcLoad_payload <= unsigned(pkg_cat(pkg_toStdLogicVector(BranchPlugin_jumpInterface_valid),pkg_toStdLogicVector(CsrPlugin_jumpInterface_valid))); + IBusSimplePlugin_jump_pcLoad_payload <= pkg_mux(pkg_extract(std_logic_vector((zz_IBusSimplePlugin_jump_pcLoad_payload and pkg_not((zz_IBusSimplePlugin_jump_pcLoad_payload - pkg_unsigned("01"))))),0),CsrPlugin_jumpInterface_payload,BranchPlugin_jumpInterface_payload); + process(IBusSimplePlugin_jump_pcLoad_valid) + begin + IBusSimplePlugin_fetchPc_correction <= pkg_toStdLogic(false); + if IBusSimplePlugin_jump_pcLoad_valid = '1' then + IBusSimplePlugin_fetchPc_correction <= pkg_toStdLogic(true); + end if; + end process; + + IBusSimplePlugin_fetchPc_output_fire <= (IBusSimplePlugin_fetchPc_output_valid and IBusSimplePlugin_fetchPc_output_ready); + IBusSimplePlugin_fetchPc_corrected <= (IBusSimplePlugin_fetchPc_correction or IBusSimplePlugin_fetchPc_correctionReg); + process(IBusSimplePlugin_iBusRsp_stages_1_input_ready) + begin + IBusSimplePlugin_fetchPc_pcRegPropagate <= pkg_toStdLogic(false); + if IBusSimplePlugin_iBusRsp_stages_1_input_ready = '1' then + IBusSimplePlugin_fetchPc_pcRegPropagate <= pkg_toStdLogic(true); + end if; + end process; + + when_Fetcher_l134 <= (IBusSimplePlugin_fetchPc_correction or IBusSimplePlugin_fetchPc_pcRegPropagate); + IBusSimplePlugin_fetchPc_output_fire_1 <= (IBusSimplePlugin_fetchPc_output_valid and IBusSimplePlugin_fetchPc_output_ready); + when_Fetcher_l134_1 <= ((not IBusSimplePlugin_fetchPc_output_valid) and IBusSimplePlugin_fetchPc_output_ready); + process(IBusSimplePlugin_fetchPc_pcReg,IBusSimplePlugin_fetchPc_inc,IBusSimplePlugin_jump_pcLoad_valid,IBusSimplePlugin_jump_pcLoad_payload) + begin + IBusSimplePlugin_fetchPc_pc <= (IBusSimplePlugin_fetchPc_pcReg + pkg_resize(unsigned(pkg_cat(pkg_toStdLogicVector(IBusSimplePlugin_fetchPc_inc),pkg_stdLogicVector("00"))),32)); + if IBusSimplePlugin_jump_pcLoad_valid = '1' then + IBusSimplePlugin_fetchPc_pc <= IBusSimplePlugin_jump_pcLoad_payload; + end if; + IBusSimplePlugin_fetchPc_pc(0) <= pkg_toStdLogic(false); + IBusSimplePlugin_fetchPc_pc(1) <= pkg_toStdLogic(false); + end process; + + process(IBusSimplePlugin_jump_pcLoad_valid) + begin + IBusSimplePlugin_fetchPc_flushed <= pkg_toStdLogic(false); + if IBusSimplePlugin_jump_pcLoad_valid = '1' then + IBusSimplePlugin_fetchPc_flushed <= pkg_toStdLogic(true); + end if; + end process; + + when_Fetcher_l161 <= (IBusSimplePlugin_fetchPc_booted and ((IBusSimplePlugin_fetchPc_output_ready or IBusSimplePlugin_fetchPc_correction) or IBusSimplePlugin_fetchPc_pcRegPropagate)); + IBusSimplePlugin_fetchPc_output_valid <= ((not IBusSimplePlugin_fetcherHalt) and IBusSimplePlugin_fetchPc_booted); + IBusSimplePlugin_fetchPc_output_payload <= IBusSimplePlugin_fetchPc_pc; + IBusSimplePlugin_iBusRsp_redoFetch <= pkg_toStdLogic(false); + IBusSimplePlugin_iBusRsp_stages_0_input_valid <= IBusSimplePlugin_fetchPc_output_valid; + IBusSimplePlugin_fetchPc_output_ready <= IBusSimplePlugin_iBusRsp_stages_0_input_ready; + IBusSimplePlugin_iBusRsp_stages_0_input_payload <= IBusSimplePlugin_fetchPc_output_payload; + IBusSimplePlugin_iBusRsp_stages_0_halt <= pkg_toStdLogic(false); + zz_IBusSimplePlugin_iBusRsp_stages_0_input_ready <= (not IBusSimplePlugin_iBusRsp_stages_0_halt); + IBusSimplePlugin_iBusRsp_stages_0_input_ready <= (IBusSimplePlugin_iBusRsp_stages_0_output_ready and zz_IBusSimplePlugin_iBusRsp_stages_0_input_ready); + IBusSimplePlugin_iBusRsp_stages_0_output_valid <= (IBusSimplePlugin_iBusRsp_stages_0_input_valid and zz_IBusSimplePlugin_iBusRsp_stages_0_input_ready); + IBusSimplePlugin_iBusRsp_stages_0_output_payload <= IBusSimplePlugin_iBusRsp_stages_0_input_payload; + process(when_IBusSimplePlugin_l305) + begin + IBusSimplePlugin_iBusRsp_stages_1_halt <= pkg_toStdLogic(false); + if when_IBusSimplePlugin_l305 = '1' then + IBusSimplePlugin_iBusRsp_stages_1_halt <= pkg_toStdLogic(true); + end if; + end process; + + zz_IBusSimplePlugin_iBusRsp_stages_1_input_ready <= (not IBusSimplePlugin_iBusRsp_stages_1_halt); + IBusSimplePlugin_iBusRsp_stages_1_input_ready <= (IBusSimplePlugin_iBusRsp_stages_1_output_ready and zz_IBusSimplePlugin_iBusRsp_stages_1_input_ready); + IBusSimplePlugin_iBusRsp_stages_1_output_valid <= (IBusSimplePlugin_iBusRsp_stages_1_input_valid and zz_IBusSimplePlugin_iBusRsp_stages_1_input_ready); + IBusSimplePlugin_iBusRsp_stages_1_output_payload <= IBusSimplePlugin_iBusRsp_stages_1_input_payload; + IBusSimplePlugin_iBusRsp_stages_2_halt <= pkg_toStdLogic(false); + zz_IBusSimplePlugin_iBusRsp_stages_2_input_ready <= (not IBusSimplePlugin_iBusRsp_stages_2_halt); + IBusSimplePlugin_iBusRsp_stages_2_input_ready <= (IBusSimplePlugin_iBusRsp_stages_2_output_ready and zz_IBusSimplePlugin_iBusRsp_stages_2_input_ready); + IBusSimplePlugin_iBusRsp_stages_2_output_valid <= (IBusSimplePlugin_iBusRsp_stages_2_input_valid and zz_IBusSimplePlugin_iBusRsp_stages_2_input_ready); + IBusSimplePlugin_iBusRsp_stages_2_output_payload <= IBusSimplePlugin_iBusRsp_stages_2_input_payload; + IBusSimplePlugin_iBusRsp_flush <= (IBusSimplePlugin_externalFlush or IBusSimplePlugin_iBusRsp_redoFetch); + IBusSimplePlugin_iBusRsp_stages_0_output_ready <= zz_IBusSimplePlugin_iBusRsp_stages_0_output_ready; + zz_IBusSimplePlugin_iBusRsp_stages_0_output_ready <= ((pkg_toStdLogic(false) and (not zz_IBusSimplePlugin_iBusRsp_stages_0_output_ready_1)) or IBusSimplePlugin_iBusRsp_stages_1_input_ready); + zz_IBusSimplePlugin_iBusRsp_stages_0_output_ready_1 <= zz_IBusSimplePlugin_iBusRsp_stages_0_output_ready_2; + IBusSimplePlugin_iBusRsp_stages_1_input_valid <= zz_IBusSimplePlugin_iBusRsp_stages_0_output_ready_1; + IBusSimplePlugin_iBusRsp_stages_1_input_payload <= IBusSimplePlugin_fetchPc_pcReg; + IBusSimplePlugin_iBusRsp_stages_1_output_ready <= ((pkg_toStdLogic(false) and (not IBusSimplePlugin_iBusRsp_stages_1_output_m2sPipe_valid)) or IBusSimplePlugin_iBusRsp_stages_1_output_m2sPipe_ready); + IBusSimplePlugin_iBusRsp_stages_1_output_m2sPipe_valid <= zz_IBusSimplePlugin_iBusRsp_stages_1_output_m2sPipe_valid; + IBusSimplePlugin_iBusRsp_stages_1_output_m2sPipe_payload <= zz_IBusSimplePlugin_iBusRsp_stages_1_output_m2sPipe_payload; + IBusSimplePlugin_iBusRsp_stages_2_input_valid <= IBusSimplePlugin_iBusRsp_stages_1_output_m2sPipe_valid; + IBusSimplePlugin_iBusRsp_stages_1_output_m2sPipe_ready <= IBusSimplePlugin_iBusRsp_stages_2_input_ready; + IBusSimplePlugin_iBusRsp_stages_2_input_payload <= IBusSimplePlugin_iBusRsp_stages_1_output_m2sPipe_payload; + process(IBusSimplePlugin_injector_decodeInput_valid,when_Fetcher_l323) + begin + IBusSimplePlugin_iBusRsp_readyForError <= pkg_toStdLogic(true); + if IBusSimplePlugin_injector_decodeInput_valid = '1' then + IBusSimplePlugin_iBusRsp_readyForError <= pkg_toStdLogic(false); + end if; + if when_Fetcher_l323 = '1' then + IBusSimplePlugin_iBusRsp_readyForError <= pkg_toStdLogic(false); + end if; + end process; + + when_Fetcher_l243 <= (IBusSimplePlugin_iBusRsp_stages_1_input_valid or IBusSimplePlugin_iBusRsp_stages_2_input_valid); + IBusSimplePlugin_iBusRsp_output_ready <= ((pkg_toStdLogic(false) and (not IBusSimplePlugin_injector_decodeInput_valid)) or IBusSimplePlugin_injector_decodeInput_ready); + IBusSimplePlugin_injector_decodeInput_valid <= zz_IBusSimplePlugin_injector_decodeInput_valid; + IBusSimplePlugin_injector_decodeInput_payload_pc <= zz_IBusSimplePlugin_injector_decodeInput_payload_pc; + IBusSimplePlugin_injector_decodeInput_payload_rsp_error <= zz_IBusSimplePlugin_injector_decodeInput_payload_rsp_error; + IBusSimplePlugin_injector_decodeInput_payload_rsp_inst <= zz_IBusSimplePlugin_injector_decodeInput_payload_rsp_inst; + IBusSimplePlugin_injector_decodeInput_payload_isRvc <= zz_IBusSimplePlugin_injector_decodeInput_payload_isRvc; + when_Fetcher_l323 <= (not IBusSimplePlugin_pcValids_0); + when_Fetcher_l332 <= (not (not IBusSimplePlugin_iBusRsp_stages_1_input_ready)); + when_Fetcher_l332_1 <= (not (not IBusSimplePlugin_iBusRsp_stages_2_input_ready)); + when_Fetcher_l332_2 <= (not (not IBusSimplePlugin_injector_decodeInput_ready)); + when_Fetcher_l332_3 <= (not execute_arbitration_isStuck); + when_Fetcher_l332_4 <= (not memory_arbitration_isStuck); + when_Fetcher_l332_5 <= (not writeBack_arbitration_isStuck); + IBusSimplePlugin_pcValids_0 <= IBusSimplePlugin_injector_nextPcCalc_valids_2; + IBusSimplePlugin_pcValids_1 <= IBusSimplePlugin_injector_nextPcCalc_valids_3; + IBusSimplePlugin_pcValids_2 <= IBusSimplePlugin_injector_nextPcCalc_valids_4; + IBusSimplePlugin_pcValids_3 <= IBusSimplePlugin_injector_nextPcCalc_valids_5; + IBusSimplePlugin_injector_decodeInput_ready <= (not decode_arbitration_isStuck); + process(IBusSimplePlugin_injector_decodeInput_valid,switch_Fetcher_l365,IBusSimplePlugin_forceNoDecodeCond) + begin + decode_arbitration_isValid <= IBusSimplePlugin_injector_decodeInput_valid; + case switch_Fetcher_l365 is + when "010" => + decode_arbitration_isValid <= pkg_toStdLogic(true); + when "011" => + decode_arbitration_isValid <= pkg_toStdLogic(true); + when others => + end case; + if IBusSimplePlugin_forceNoDecodeCond = '1' then + decode_arbitration_isValid <= pkg_toStdLogic(false); + end if; + end process; + + iBus_cmd_valid <= IBusSimplePlugin_cmd_valid; + IBusSimplePlugin_cmd_ready <= iBus_cmd_ready; + iBus_cmd_payload_pc <= IBusSimplePlugin_cmd_payload_pc; + IBusSimplePlugin_pending_next <= ((IBusSimplePlugin_pending_value + pkg_resize(unsigned(pkg_toStdLogicVector(IBusSimplePlugin_pending_inc)),3)) - pkg_resize(unsigned(pkg_toStdLogicVector(IBusSimplePlugin_pending_dec)),3)); + IBusSimplePlugin_cmdFork_canEmit <= (IBusSimplePlugin_iBusRsp_stages_1_output_ready and pkg_toStdLogic(IBusSimplePlugin_pending_value /= pkg_unsigned("111"))); + when_IBusSimplePlugin_l305 <= (IBusSimplePlugin_iBusRsp_stages_1_input_valid and ((not IBusSimplePlugin_cmdFork_canEmit) or (not IBusSimplePlugin_cmd_ready))); + IBusSimplePlugin_cmd_valid <= (IBusSimplePlugin_iBusRsp_stages_1_input_valid and IBusSimplePlugin_cmdFork_canEmit); + IBusSimplePlugin_cmd_fire <= (IBusSimplePlugin_cmd_valid and IBusSimplePlugin_cmd_ready); + IBusSimplePlugin_pending_inc <= IBusSimplePlugin_cmd_fire; + IBusSimplePlugin_cmd_payload_pc <= unsigned(pkg_cat(std_logic_vector(pkg_extract(IBusSimplePlugin_iBusRsp_stages_1_input_payload,31,2)),std_logic_vector(pkg_unsigned("00")))); + iBus_rsp_toStream_valid <= iBus_rsp_valid; + iBus_rsp_toStream_payload_error <= iBus_rsp_payload_error; + iBus_rsp_toStream_payload_inst <= iBus_rsp_payload_inst; + iBus_rsp_toStream_ready <= IBusSimplePlugin_rspJoin_rspBuffer_c_io_push_ready; + IBusSimplePlugin_rspJoin_rspBuffer_flush <= (pkg_toStdLogic(IBusSimplePlugin_rspJoin_rspBuffer_discardCounter /= pkg_unsigned("000")) or IBusSimplePlugin_iBusRsp_flush); + IBusSimplePlugin_rspJoin_rspBuffer_output_valid <= (IBusSimplePlugin_rspJoin_rspBuffer_c_io_pop_valid and pkg_toStdLogic(IBusSimplePlugin_rspJoin_rspBuffer_discardCounter = pkg_unsigned("000"))); + IBusSimplePlugin_rspJoin_rspBuffer_output_payload_error <= IBusSimplePlugin_rspJoin_rspBuffer_c_io_pop_payload_error; + IBusSimplePlugin_rspJoin_rspBuffer_output_payload_inst <= IBusSimplePlugin_rspJoin_rspBuffer_c_io_pop_payload_inst; + IBusSimplePlugin_rspJoin_rspBuffer_c_io_pop_ready <= (IBusSimplePlugin_rspJoin_rspBuffer_output_ready or IBusSimplePlugin_rspJoin_rspBuffer_flush); + IBusSimplePlugin_rspJoin_rspBuffer_c_io_pop_fire <= (IBusSimplePlugin_rspJoin_rspBuffer_c_io_pop_valid and IBusSimplePlugin_rspJoin_rspBuffer_c_io_pop_ready); + IBusSimplePlugin_pending_dec <= IBusSimplePlugin_rspJoin_rspBuffer_c_io_pop_fire; + IBusSimplePlugin_rspJoin_fetchRsp_pc <= IBusSimplePlugin_iBusRsp_stages_2_output_payload; + process(IBusSimplePlugin_rspJoin_rspBuffer_output_payload_error,when_IBusSimplePlugin_l376) + begin + IBusSimplePlugin_rspJoin_fetchRsp_rsp_error <= IBusSimplePlugin_rspJoin_rspBuffer_output_payload_error; + if when_IBusSimplePlugin_l376 = '1' then + IBusSimplePlugin_rspJoin_fetchRsp_rsp_error <= pkg_toStdLogic(false); + end if; + end process; + + IBusSimplePlugin_rspJoin_fetchRsp_rsp_inst <= IBusSimplePlugin_rspJoin_rspBuffer_output_payload_inst; + when_IBusSimplePlugin_l376 <= (not IBusSimplePlugin_rspJoin_rspBuffer_output_valid); + IBusSimplePlugin_rspJoin_exceptionDetected <= pkg_toStdLogic(false); + IBusSimplePlugin_rspJoin_join_valid <= (IBusSimplePlugin_iBusRsp_stages_2_output_valid and IBusSimplePlugin_rspJoin_rspBuffer_output_valid); + IBusSimplePlugin_rspJoin_join_payload_pc <= IBusSimplePlugin_rspJoin_fetchRsp_pc; + IBusSimplePlugin_rspJoin_join_payload_rsp_error <= IBusSimplePlugin_rspJoin_fetchRsp_rsp_error; + IBusSimplePlugin_rspJoin_join_payload_rsp_inst <= IBusSimplePlugin_rspJoin_fetchRsp_rsp_inst; + IBusSimplePlugin_rspJoin_join_payload_isRvc <= IBusSimplePlugin_rspJoin_fetchRsp_isRvc; + IBusSimplePlugin_rspJoin_join_fire <= (IBusSimplePlugin_rspJoin_join_valid and IBusSimplePlugin_rspJoin_join_ready); + IBusSimplePlugin_iBusRsp_stages_2_output_ready <= pkg_mux(IBusSimplePlugin_iBusRsp_stages_2_output_valid,IBusSimplePlugin_rspJoin_join_fire,IBusSimplePlugin_rspJoin_join_ready); + IBusSimplePlugin_rspJoin_join_fire_1 <= (IBusSimplePlugin_rspJoin_join_valid and IBusSimplePlugin_rspJoin_join_ready); + IBusSimplePlugin_rspJoin_rspBuffer_output_ready <= IBusSimplePlugin_rspJoin_join_fire_1; + zz_IBusSimplePlugin_iBusRsp_output_valid <= (not IBusSimplePlugin_rspJoin_exceptionDetected); + IBusSimplePlugin_rspJoin_join_ready <= (IBusSimplePlugin_iBusRsp_output_ready and zz_IBusSimplePlugin_iBusRsp_output_valid); + IBusSimplePlugin_iBusRsp_output_valid <= (IBusSimplePlugin_rspJoin_join_valid and zz_IBusSimplePlugin_iBusRsp_output_valid); + IBusSimplePlugin_iBusRsp_output_payload_pc <= IBusSimplePlugin_rspJoin_join_payload_pc; + IBusSimplePlugin_iBusRsp_output_payload_rsp_error <= IBusSimplePlugin_rspJoin_join_payload_rsp_error; + IBusSimplePlugin_iBusRsp_output_payload_rsp_inst <= IBusSimplePlugin_rspJoin_join_payload_rsp_inst; + IBusSimplePlugin_iBusRsp_output_payload_isRvc <= IBusSimplePlugin_rspJoin_join_payload_isRvc; + zz_dBus_cmd_valid <= pkg_toStdLogic(false); + process(execute_ALIGNEMENT_FAULT) + begin + execute_DBusSimplePlugin_skipCmd <= pkg_toStdLogic(false); + if execute_ALIGNEMENT_FAULT = '1' then + execute_DBusSimplePlugin_skipCmd <= pkg_toStdLogic(true); + end if; + end process; + + dBus_cmd_valid <= (((((execute_arbitration_isValid and execute_MEMORY_ENABLE) and (not execute_arbitration_isStuckByOthers)) and (not execute_arbitration_isFlushed)) and (not execute_DBusSimplePlugin_skipCmd)) and (not zz_dBus_cmd_valid)); + dBus_cmd_payload_wr <= execute_MEMORY_STORE; + dBus_cmd_payload_size_read_buffer <= unsigned(pkg_extract(execute_INSTRUCTION,13,12)); + process(dBus_cmd_payload_size_read_buffer,execute_RS2) + begin + case dBus_cmd_payload_size_read_buffer is + when "00" => + zz_dBus_cmd_payload_data <= pkg_cat(pkg_cat(pkg_cat(pkg_extract(execute_RS2,7,0),pkg_extract(execute_RS2,7,0)),pkg_extract(execute_RS2,7,0)),pkg_extract(execute_RS2,7,0)); + when "01" => + zz_dBus_cmd_payload_data <= pkg_cat(pkg_extract(execute_RS2,15,0),pkg_extract(execute_RS2,15,0)); + when others => + zz_dBus_cmd_payload_data <= pkg_extract(execute_RS2,31,0); + end case; + end process; + + dBus_cmd_payload_data <= zz_dBus_cmd_payload_data; + when_DBusSimplePlugin_l428 <= ((((execute_arbitration_isValid and execute_MEMORY_ENABLE) and (not dBus_cmd_ready)) and (not execute_DBusSimplePlugin_skipCmd)) and (not zz_dBus_cmd_valid)); + process(dBus_cmd_payload_size_read_buffer) + begin + case dBus_cmd_payload_size_read_buffer is + when "00" => + zz_execute_DBusSimplePlugin_formalMask <= pkg_stdLogicVector("0001"); + when "01" => + zz_execute_DBusSimplePlugin_formalMask <= pkg_stdLogicVector("0011"); + when others => + zz_execute_DBusSimplePlugin_formalMask <= pkg_stdLogicVector("1111"); + end case; + end process; + + execute_DBusSimplePlugin_formalMask <= std_logic_vector(shift_left(unsigned(zz_execute_DBusSimplePlugin_formalMask),to_integer(pkg_extract(dBus_cmd_payload_address_read_buffer,1,0)))); + dBus_cmd_payload_address_read_buffer <= unsigned(execute_SRC_ADD); + when_DBusSimplePlugin_l482 <= (((memory_arbitration_isValid and memory_MEMORY_ENABLE) and (not memory_MEMORY_STORE)) and ((not dBus_rsp_ready) or pkg_toStdLogic(false))); + process(writeBack_MEMORY_READ_DATA,writeBack_MEMORY_ADDRESS_LOW) + begin + writeBack_DBusSimplePlugin_rspShifted <= writeBack_MEMORY_READ_DATA; + case writeBack_MEMORY_ADDRESS_LOW is + when "01" => + writeBack_DBusSimplePlugin_rspShifted(7 downto 0) <= pkg_extract(writeBack_MEMORY_READ_DATA,15,8); + when "10" => + writeBack_DBusSimplePlugin_rspShifted(15 downto 0) <= pkg_extract(writeBack_MEMORY_READ_DATA,31,16); + when "11" => + writeBack_DBusSimplePlugin_rspShifted(7 downto 0) <= pkg_extract(writeBack_MEMORY_READ_DATA,31,24); + when others => + end case; + end process; + + switch_Misc_l210 <= pkg_extract(writeBack_INSTRUCTION,13,12); + zz_writeBack_DBusSimplePlugin_rspFormated <= (pkg_extract(writeBack_DBusSimplePlugin_rspShifted,7) and (not pkg_extract(writeBack_INSTRUCTION,14))); + process(zz_writeBack_DBusSimplePlugin_rspFormated,writeBack_DBusSimplePlugin_rspShifted) + begin + zz_writeBack_DBusSimplePlugin_rspFormated_1(31) <= zz_writeBack_DBusSimplePlugin_rspFormated; + zz_writeBack_DBusSimplePlugin_rspFormated_1(30) <= zz_writeBack_DBusSimplePlugin_rspFormated; + zz_writeBack_DBusSimplePlugin_rspFormated_1(29) <= zz_writeBack_DBusSimplePlugin_rspFormated; + zz_writeBack_DBusSimplePlugin_rspFormated_1(28) <= zz_writeBack_DBusSimplePlugin_rspFormated; + zz_writeBack_DBusSimplePlugin_rspFormated_1(27) <= zz_writeBack_DBusSimplePlugin_rspFormated; + zz_writeBack_DBusSimplePlugin_rspFormated_1(26) <= zz_writeBack_DBusSimplePlugin_rspFormated; + zz_writeBack_DBusSimplePlugin_rspFormated_1(25) <= zz_writeBack_DBusSimplePlugin_rspFormated; + zz_writeBack_DBusSimplePlugin_rspFormated_1(24) <= zz_writeBack_DBusSimplePlugin_rspFormated; + zz_writeBack_DBusSimplePlugin_rspFormated_1(23) <= zz_writeBack_DBusSimplePlugin_rspFormated; + zz_writeBack_DBusSimplePlugin_rspFormated_1(22) <= zz_writeBack_DBusSimplePlugin_rspFormated; + zz_writeBack_DBusSimplePlugin_rspFormated_1(21) <= zz_writeBack_DBusSimplePlugin_rspFormated; + zz_writeBack_DBusSimplePlugin_rspFormated_1(20) <= zz_writeBack_DBusSimplePlugin_rspFormated; + zz_writeBack_DBusSimplePlugin_rspFormated_1(19) <= zz_writeBack_DBusSimplePlugin_rspFormated; + zz_writeBack_DBusSimplePlugin_rspFormated_1(18) <= zz_writeBack_DBusSimplePlugin_rspFormated; + zz_writeBack_DBusSimplePlugin_rspFormated_1(17) <= zz_writeBack_DBusSimplePlugin_rspFormated; + zz_writeBack_DBusSimplePlugin_rspFormated_1(16) <= zz_writeBack_DBusSimplePlugin_rspFormated; + zz_writeBack_DBusSimplePlugin_rspFormated_1(15) <= zz_writeBack_DBusSimplePlugin_rspFormated; + zz_writeBack_DBusSimplePlugin_rspFormated_1(14) <= zz_writeBack_DBusSimplePlugin_rspFormated; + zz_writeBack_DBusSimplePlugin_rspFormated_1(13) <= zz_writeBack_DBusSimplePlugin_rspFormated; + zz_writeBack_DBusSimplePlugin_rspFormated_1(12) <= zz_writeBack_DBusSimplePlugin_rspFormated; + zz_writeBack_DBusSimplePlugin_rspFormated_1(11) <= zz_writeBack_DBusSimplePlugin_rspFormated; + zz_writeBack_DBusSimplePlugin_rspFormated_1(10) <= zz_writeBack_DBusSimplePlugin_rspFormated; + zz_writeBack_DBusSimplePlugin_rspFormated_1(9) <= zz_writeBack_DBusSimplePlugin_rspFormated; + zz_writeBack_DBusSimplePlugin_rspFormated_1(8) <= zz_writeBack_DBusSimplePlugin_rspFormated; + zz_writeBack_DBusSimplePlugin_rspFormated_1(7 downto 0) <= pkg_extract(writeBack_DBusSimplePlugin_rspShifted,7,0); + end process; + + zz_writeBack_DBusSimplePlugin_rspFormated_2 <= (pkg_extract(writeBack_DBusSimplePlugin_rspShifted,15) and (not pkg_extract(writeBack_INSTRUCTION,14))); + process(zz_writeBack_DBusSimplePlugin_rspFormated_2,writeBack_DBusSimplePlugin_rspShifted) + begin + zz_writeBack_DBusSimplePlugin_rspFormated_3(31) <= zz_writeBack_DBusSimplePlugin_rspFormated_2; + zz_writeBack_DBusSimplePlugin_rspFormated_3(30) <= zz_writeBack_DBusSimplePlugin_rspFormated_2; + zz_writeBack_DBusSimplePlugin_rspFormated_3(29) <= zz_writeBack_DBusSimplePlugin_rspFormated_2; + zz_writeBack_DBusSimplePlugin_rspFormated_3(28) <= zz_writeBack_DBusSimplePlugin_rspFormated_2; + zz_writeBack_DBusSimplePlugin_rspFormated_3(27) <= zz_writeBack_DBusSimplePlugin_rspFormated_2; + zz_writeBack_DBusSimplePlugin_rspFormated_3(26) <= zz_writeBack_DBusSimplePlugin_rspFormated_2; + zz_writeBack_DBusSimplePlugin_rspFormated_3(25) <= zz_writeBack_DBusSimplePlugin_rspFormated_2; + zz_writeBack_DBusSimplePlugin_rspFormated_3(24) <= zz_writeBack_DBusSimplePlugin_rspFormated_2; + zz_writeBack_DBusSimplePlugin_rspFormated_3(23) <= zz_writeBack_DBusSimplePlugin_rspFormated_2; + zz_writeBack_DBusSimplePlugin_rspFormated_3(22) <= zz_writeBack_DBusSimplePlugin_rspFormated_2; + zz_writeBack_DBusSimplePlugin_rspFormated_3(21) <= zz_writeBack_DBusSimplePlugin_rspFormated_2; + zz_writeBack_DBusSimplePlugin_rspFormated_3(20) <= zz_writeBack_DBusSimplePlugin_rspFormated_2; + zz_writeBack_DBusSimplePlugin_rspFormated_3(19) <= zz_writeBack_DBusSimplePlugin_rspFormated_2; + zz_writeBack_DBusSimplePlugin_rspFormated_3(18) <= zz_writeBack_DBusSimplePlugin_rspFormated_2; + zz_writeBack_DBusSimplePlugin_rspFormated_3(17) <= zz_writeBack_DBusSimplePlugin_rspFormated_2; + zz_writeBack_DBusSimplePlugin_rspFormated_3(16) <= zz_writeBack_DBusSimplePlugin_rspFormated_2; + zz_writeBack_DBusSimplePlugin_rspFormated_3(15 downto 0) <= pkg_extract(writeBack_DBusSimplePlugin_rspShifted,15,0); + end process; + + process(switch_Misc_l210,zz_writeBack_DBusSimplePlugin_rspFormated_1,zz_writeBack_DBusSimplePlugin_rspFormated_3,writeBack_DBusSimplePlugin_rspShifted) + begin + case switch_Misc_l210 is + when "00" => + writeBack_DBusSimplePlugin_rspFormated <= zz_writeBack_DBusSimplePlugin_rspFormated_1; + when "01" => + writeBack_DBusSimplePlugin_rspFormated <= zz_writeBack_DBusSimplePlugin_rspFormated_3; + when others => + writeBack_DBusSimplePlugin_rspFormated <= writeBack_DBusSimplePlugin_rspShifted; + end case; + end process; + + when_DBusSimplePlugin_l558 <= (writeBack_arbitration_isValid and writeBack_MEMORY_ENABLE); + process(CsrPlugin_forceMachineWire) + begin + CsrPlugin_privilege <= pkg_unsigned("11"); + if CsrPlugin_forceMachineWire = '1' then + CsrPlugin_privilege <= pkg_unsigned("11"); + end if; + end process; + + CsrPlugin_misa_base <= pkg_unsigned("01"); + CsrPlugin_misa_extensions <= pkg_stdLogicVector("00000000000000000001000010"); + CsrPlugin_mtvec_mode <= pkg_stdLogicVector("00"); + CsrPlugin_mtvec_base <= pkg_unsigned("100000000000000000000000001000"); + zz_when_CsrPlugin_l965 <= (CsrPlugin_mip_MTIP and CsrPlugin_mie_MTIE); + zz_when_CsrPlugin_l965_1 <= (CsrPlugin_mip_MSIP and CsrPlugin_mie_MSIE); + zz_when_CsrPlugin_l965_2 <= (CsrPlugin_mip_MEIP and CsrPlugin_mie_MEIE); + when_CsrPlugin_l959 <= (CsrPlugin_mstatus_MIE or pkg_toStdLogic(CsrPlugin_privilege < pkg_unsigned("11"))); + when_CsrPlugin_l965 <= ((zz_when_CsrPlugin_l965 and pkg_toStdLogic(true)) and (not pkg_toStdLogic(false))); + when_CsrPlugin_l965_1 <= ((zz_when_CsrPlugin_l965_1 and pkg_toStdLogic(true)) and (not pkg_toStdLogic(false))); + when_CsrPlugin_l965_2 <= ((zz_when_CsrPlugin_l965_2 and pkg_toStdLogic(true)) and (not pkg_toStdLogic(false))); + CsrPlugin_exception <= pkg_toStdLogic(false); + CsrPlugin_lastStageWasWfi <= pkg_toStdLogic(false); + CsrPlugin_pipelineLiberator_active <= ((CsrPlugin_interrupt_valid and CsrPlugin_allowInterrupts) and decode_arbitration_isValid); + when_CsrPlugin_l993 <= (not execute_arbitration_isStuck); + when_CsrPlugin_l993_1 <= (not memory_arbitration_isStuck); + when_CsrPlugin_l993_2 <= (not writeBack_arbitration_isStuck); + when_CsrPlugin_l998 <= ((not CsrPlugin_pipelineLiberator_active) or decode_arbitration_removeIt); + process(CsrPlugin_pipelineLiberator_pcValids_2,CsrPlugin_hadException) + begin + CsrPlugin_pipelineLiberator_done <= CsrPlugin_pipelineLiberator_pcValids_2; + if CsrPlugin_hadException = '1' then + CsrPlugin_pipelineLiberator_done <= pkg_toStdLogic(false); + end if; + end process; + + CsrPlugin_interruptJump <= ((CsrPlugin_interrupt_valid and CsrPlugin_pipelineLiberator_done) and CsrPlugin_allowInterrupts); + CsrPlugin_targetPrivilege <= CsrPlugin_interrupt_targetPrivilege; + CsrPlugin_trapCause <= pkg_resize(CsrPlugin_interrupt_code,4); + process(CsrPlugin_targetPrivilege,CsrPlugin_mtvec_mode) + begin + CsrPlugin_xtvec_mode <= pkg_stdLogicVector("XX"); + case CsrPlugin_targetPrivilege is + when "11" => + CsrPlugin_xtvec_mode <= CsrPlugin_mtvec_mode; + when others => + end case; + end process; + + process(CsrPlugin_targetPrivilege,CsrPlugin_mtvec_base) + begin + CsrPlugin_xtvec_base <= pkg_unsigned("XXXXXXXXXXXXXXXXXXXXXXXXXXXXXX"); + case CsrPlugin_targetPrivilege is + when "11" => + CsrPlugin_xtvec_base <= CsrPlugin_mtvec_base; + when others => + end case; + end process; + + when_CsrPlugin_l1032 <= (CsrPlugin_hadException or CsrPlugin_interruptJump); + when_CsrPlugin_l1077 <= (writeBack_arbitration_isValid and pkg_toStdLogic(writeBack_ENV_CTRL = EnvCtrlEnum_seq_XRET)); + switch_CsrPlugin_l1081 <= pkg_extract(writeBack_INSTRUCTION,29,28); + contextSwitching <= CsrPlugin_jumpInterface_valid; + when_CsrPlugin_l1129 <= pkg_toStdLogic(pkg_cat(pkg_toStdLogicVector((writeBack_arbitration_isValid and pkg_toStdLogic(writeBack_ENV_CTRL = EnvCtrlEnum_seq_XRET))),pkg_cat(pkg_toStdLogicVector((memory_arbitration_isValid and pkg_toStdLogic(memory_ENV_CTRL = EnvCtrlEnum_seq_XRET))),pkg_toStdLogicVector((execute_arbitration_isValid and pkg_toStdLogic(execute_ENV_CTRL = EnvCtrlEnum_seq_XRET))))) /= pkg_stdLogicVector("000")); + execute_CsrPlugin_blockedBySideEffects <= (pkg_toStdLogic(pkg_cat(pkg_toStdLogicVector(writeBack_arbitration_isValid),pkg_toStdLogicVector(memory_arbitration_isValid)) /= pkg_stdLogicVector("00")) or pkg_toStdLogic(false)); + process(execute_CsrPlugin_csr_768,execute_CsrPlugin_csr_836,execute_CsrPlugin_csr_772,execute_CsrPlugin_csr_834,execute_CSR_READ_OPCODE,CsrPlugin_csrMapping_allowCsrSignal,when_CsrPlugin_l1310,when_CsrPlugin_l1315) + begin + execute_CsrPlugin_illegalAccess <= pkg_toStdLogic(true); + if execute_CsrPlugin_csr_768 = '1' then + execute_CsrPlugin_illegalAccess <= pkg_toStdLogic(false); + end if; + if execute_CsrPlugin_csr_836 = '1' then + execute_CsrPlugin_illegalAccess <= pkg_toStdLogic(false); + end if; + if execute_CsrPlugin_csr_772 = '1' then + execute_CsrPlugin_illegalAccess <= pkg_toStdLogic(false); + end if; + if execute_CsrPlugin_csr_834 = '1' then + if execute_CSR_READ_OPCODE = '1' then + execute_CsrPlugin_illegalAccess <= pkg_toStdLogic(false); + end if; + end if; + if CsrPlugin_csrMapping_allowCsrSignal = '1' then + execute_CsrPlugin_illegalAccess <= pkg_toStdLogic(false); + end if; + if when_CsrPlugin_l1310 = '1' then + execute_CsrPlugin_illegalAccess <= pkg_toStdLogic(true); + end if; + if when_CsrPlugin_l1315 = '1' then + execute_CsrPlugin_illegalAccess <= pkg_toStdLogic(false); + end if; + end process; + + process(when_CsrPlugin_l1149,when_CsrPlugin_l1150) + begin + execute_CsrPlugin_illegalInstruction <= pkg_toStdLogic(false); + if when_CsrPlugin_l1149 = '1' then + if when_CsrPlugin_l1150 = '1' then + execute_CsrPlugin_illegalInstruction <= pkg_toStdLogic(true); + end if; + end if; + end process; + + when_CsrPlugin_l1149 <= (execute_arbitration_isValid and pkg_toStdLogic(execute_ENV_CTRL = EnvCtrlEnum_seq_XRET)); + when_CsrPlugin_l1150 <= pkg_toStdLogic(CsrPlugin_privilege < unsigned(pkg_extract(execute_INSTRUCTION,29,28))); + process(execute_arbitration_isValid,execute_IS_CSR,execute_CSR_WRITE_OPCODE,when_CsrPlugin_l1310) + begin + execute_CsrPlugin_writeInstruction <= ((execute_arbitration_isValid and execute_IS_CSR) and execute_CSR_WRITE_OPCODE); + if when_CsrPlugin_l1310 = '1' then + execute_CsrPlugin_writeInstruction <= pkg_toStdLogic(false); + end if; + end process; + + process(execute_arbitration_isValid,execute_IS_CSR,execute_CSR_READ_OPCODE,when_CsrPlugin_l1310) + begin + execute_CsrPlugin_readInstruction <= ((execute_arbitration_isValid and execute_IS_CSR) and execute_CSR_READ_OPCODE); + if when_CsrPlugin_l1310 = '1' then + execute_CsrPlugin_readInstruction <= pkg_toStdLogic(false); + end if; + end process; + + execute_CsrPlugin_writeEnable <= (execute_CsrPlugin_writeInstruction and (not execute_arbitration_isStuck)); + execute_CsrPlugin_readEnable <= (execute_CsrPlugin_readInstruction and (not execute_arbitration_isStuck)); + CsrPlugin_csrMapping_hazardFree <= (not execute_CsrPlugin_blockedBySideEffects); + execute_CsrPlugin_readToWriteData <= CsrPlugin_csrMapping_readDataSignal; + switch_Misc_l210_1 <= pkg_extract(execute_INSTRUCTION,13); + process(switch_Misc_l210_1,execute_SRC1,execute_INSTRUCTION,execute_CsrPlugin_readToWriteData) + begin + case switch_Misc_l210_1 is + when '0' => + zz_CsrPlugin_csrMapping_writeDataSignal <= execute_SRC1; + when others => + zz_CsrPlugin_csrMapping_writeDataSignal <= pkg_mux(pkg_extract(execute_INSTRUCTION,12),(execute_CsrPlugin_readToWriteData and pkg_not(execute_SRC1)),(execute_CsrPlugin_readToWriteData or execute_SRC1)); + end case; + end process; + + CsrPlugin_csrMapping_writeDataSignal <= zz_CsrPlugin_csrMapping_writeDataSignal; + when_CsrPlugin_l1189 <= (execute_arbitration_isValid and execute_IS_CSR); + when_CsrPlugin_l1193 <= (execute_arbitration_isValid and (execute_IS_CSR or pkg_toStdLogic(false))); + execute_CsrPlugin_csrAddress <= pkg_extract(execute_INSTRUCTION,31,20); + zz_decode_BRANCH_CTRL_3 <= pkg_toStdLogic((decode_INSTRUCTION and pkg_stdLogicVector("00000000000000000100000001010000")) = pkg_stdLogicVector("00000000000000000100000001010000")); + zz_decode_BRANCH_CTRL_4 <= pkg_toStdLogic((decode_INSTRUCTION and pkg_stdLogicVector("00000000000000000110000000000100")) = pkg_stdLogicVector("00000000000000000010000000000000")); + zz_decode_BRANCH_CTRL_5 <= pkg_toStdLogic((decode_INSTRUCTION and pkg_stdLogicVector("00000000000000000000000000011000")) = pkg_stdLogicVector("00000000000000000000000000000000")); + zz_decode_BRANCH_CTRL_6 <= pkg_toStdLogic((decode_INSTRUCTION and pkg_stdLogicVector("00000000000000000000000000000100")) = pkg_stdLogicVector("00000000000000000000000000000100")); + zz_decode_BRANCH_CTRL_7 <= pkg_toStdLogic((decode_INSTRUCTION and pkg_stdLogicVector("00000000000000000000000001010000")) = pkg_stdLogicVector("00000000000000000000000000010000")); + zz_decode_BRANCH_CTRL_8 <= pkg_toStdLogic((decode_INSTRUCTION and pkg_stdLogicVector("00000000000000000000000001001000")) = pkg_stdLogicVector("00000000000000000000000001001000")); + zz_decode_BRANCH_CTRL_2 <= pkg_cat(pkg_toStdLogicVector(pkg_toStdLogic(pkg_toStdLogicVector(pkg_toStdLogic((decode_INSTRUCTION and zz_zz_decode_BRANCH_CTRL_2) = pkg_stdLogicVector("00000000000000000000000001010000"))) /= pkg_stdLogicVector("0"))),pkg_cat(pkg_toStdLogicVector(pkg_toStdLogic(pkg_cat(pkg_toStdLogicVector(zz_decode_BRANCH_CTRL_8),pkg_toStdLogicVector(zz_zz_decode_BRANCH_CTRL_2_1)) /= pkg_stdLogicVector("00"))),pkg_cat(pkg_toStdLogicVector(pkg_toStdLogic(pkg_toStdLogicVector(zz_zz_decode_BRANCH_CTRL_2_2) /= pkg_stdLogicVector("0"))),pkg_cat(pkg_toStdLogicVector(pkg_toStdLogic(zz_zz_decode_BRANCH_CTRL_2_3 /= zz_zz_decode_BRANCH_CTRL_2_4)),pkg_cat(pkg_toStdLogicVector(zz_zz_decode_BRANCH_CTRL_2_5),pkg_cat(zz_zz_decode_BRANCH_CTRL_2_10,zz_zz_decode_BRANCH_CTRL_2_13)))))); + zz_decode_SRC1_CTRL_2 <= pkg_extract(zz_decode_BRANCH_CTRL_2,1,0); + zz_decode_SRC1_CTRL_1 <= zz_decode_SRC1_CTRL_2; + zz_decode_SRC2_CTRL_2 <= pkg_extract(zz_decode_BRANCH_CTRL_2,6,5); + zz_decode_SRC2_CTRL_1 <= zz_decode_SRC2_CTRL_2; + zz_decode_ENV_CTRL_2 <= pkg_extract(zz_decode_BRANCH_CTRL_2,14,14); + zz_decode_ENV_CTRL_1 <= zz_decode_ENV_CTRL_2; + zz_decode_ALU_CTRL_2 <= pkg_extract(zz_decode_BRANCH_CTRL_2,16,15); + zz_decode_ALU_CTRL_1 <= zz_decode_ALU_CTRL_2; + zz_decode_ALU_BITWISE_CTRL_2 <= pkg_extract(zz_decode_BRANCH_CTRL_2,19,18); + zz_decode_ALU_BITWISE_CTRL_1 <= zz_decode_ALU_BITWISE_CTRL_2; + zz_decode_SHIFT_CTRL_2 <= pkg_extract(zz_decode_BRANCH_CTRL_2,22,21); + zz_decode_SHIFT_CTRL_1 <= zz_decode_SHIFT_CTRL_2; + zz_decode_BRANCH_CTRL_9 <= pkg_extract(zz_decode_BRANCH_CTRL_2,24,23); + zz_decode_BRANCH_CTRL_1 <= zz_decode_BRANCH_CTRL_9; + when_RegFilePlugin_l63 <= pkg_toStdLogic(pkg_extract(decode_INSTRUCTION,11,7) = pkg_stdLogicVector("00000")); + decode_RegFilePlugin_regFileReadAddress1 <= unsigned(pkg_extract(decode_INSTRUCTION_ANTICIPATED,19,15)); + decode_RegFilePlugin_regFileReadAddress2 <= unsigned(pkg_extract(decode_INSTRUCTION_ANTICIPATED,24,20)); + decode_RegFilePlugin_rs1Data <= zz_RegFilePlugin_regFile_port0; + decode_RegFilePlugin_rs2Data <= zz_RegFilePlugin_regFile_port0_1; + process(zz_lastStageRegFileWrite_valid,writeBack_arbitration_isFiring,zz_2) + begin + lastStageRegFileWrite_valid <= (zz_lastStageRegFileWrite_valid and writeBack_arbitration_isFiring); + if zz_2 = '1' then + lastStageRegFileWrite_valid <= pkg_toStdLogic(true); + end if; + end process; + + process(zz_lastStageRegFileWrite_payload_address,zz_2) + begin + lastStageRegFileWrite_payload_address <= unsigned(pkg_extract(zz_lastStageRegFileWrite_payload_address,11,7)); + if zz_2 = '1' then + lastStageRegFileWrite_payload_address <= pkg_unsigned("00000"); + end if; + end process; + + process(zz_lastStageRegFileWrite_payload_data,zz_2) + begin + lastStageRegFileWrite_payload_data <= zz_lastStageRegFileWrite_payload_data; + if zz_2 = '1' then + lastStageRegFileWrite_payload_data <= pkg_stdLogicVector("00000000000000000000000000000000"); + end if; + end process; + + process(execute_ALU_BITWISE_CTRL,execute_SRC1,execute_SRC2) + begin + case execute_ALU_BITWISE_CTRL is + when AluBitwiseCtrlEnum_seq_AND_1 => + execute_IntAluPlugin_bitwise <= (execute_SRC1 and execute_SRC2); + when AluBitwiseCtrlEnum_seq_OR_1 => + execute_IntAluPlugin_bitwise <= (execute_SRC1 or execute_SRC2); + when others => + execute_IntAluPlugin_bitwise <= (execute_SRC1 xor execute_SRC2); + end case; + end process; + + process(execute_ALU_CTRL,execute_IntAluPlugin_bitwise,execute_SRC_LESS,execute_SRC_ADD_SUB) + begin + case execute_ALU_CTRL is + when AluCtrlEnum_seq_BITWISE => + zz_execute_REGFILE_WRITE_DATA <= execute_IntAluPlugin_bitwise; + when AluCtrlEnum_seq_SLT_SLTU => + zz_execute_REGFILE_WRITE_DATA <= pkg_resize(pkg_toStdLogicVector(execute_SRC_LESS),32); + when others => + zz_execute_REGFILE_WRITE_DATA <= execute_SRC_ADD_SUB; + end case; + end process; + + process(decode_SRC1_CTRL,zz_decode_SRC1,decode_INSTRUCTION) + begin + case decode_SRC1_CTRL is + when Src1CtrlEnum_seq_RS => + zz_decode_SRC1_1 <= zz_decode_SRC1; + when Src1CtrlEnum_seq_PC_INCREMENT => + zz_decode_SRC1_1 <= pkg_resize(pkg_stdLogicVector("100"),32); + when Src1CtrlEnum_seq_IMU => + zz_decode_SRC1_1 <= pkg_cat(pkg_extract(decode_INSTRUCTION,31,12),std_logic_vector(pkg_unsigned("000000000000"))); + when others => + zz_decode_SRC1_1 <= pkg_resize(pkg_extract(decode_INSTRUCTION,19,15),32); + end case; + end process; + + zz_decode_SRC2_2 <= pkg_extract(decode_INSTRUCTION,31); + process(zz_decode_SRC2_2) + begin + zz_decode_SRC2_3(19) <= zz_decode_SRC2_2; + zz_decode_SRC2_3(18) <= zz_decode_SRC2_2; + zz_decode_SRC2_3(17) <= zz_decode_SRC2_2; + zz_decode_SRC2_3(16) <= zz_decode_SRC2_2; + zz_decode_SRC2_3(15) <= zz_decode_SRC2_2; + zz_decode_SRC2_3(14) <= zz_decode_SRC2_2; + zz_decode_SRC2_3(13) <= zz_decode_SRC2_2; + zz_decode_SRC2_3(12) <= zz_decode_SRC2_2; + zz_decode_SRC2_3(11) <= zz_decode_SRC2_2; + zz_decode_SRC2_3(10) <= zz_decode_SRC2_2; + zz_decode_SRC2_3(9) <= zz_decode_SRC2_2; + zz_decode_SRC2_3(8) <= zz_decode_SRC2_2; + zz_decode_SRC2_3(7) <= zz_decode_SRC2_2; + zz_decode_SRC2_3(6) <= zz_decode_SRC2_2; + zz_decode_SRC2_3(5) <= zz_decode_SRC2_2; + zz_decode_SRC2_3(4) <= zz_decode_SRC2_2; + zz_decode_SRC2_3(3) <= zz_decode_SRC2_2; + zz_decode_SRC2_3(2) <= zz_decode_SRC2_2; + zz_decode_SRC2_3(1) <= zz_decode_SRC2_2; + zz_decode_SRC2_3(0) <= zz_decode_SRC2_2; + end process; + + zz_decode_SRC2_4 <= pkg_extract(pkg_cat(pkg_extract(decode_INSTRUCTION,31,25),pkg_extract(decode_INSTRUCTION,11,7)),11); + process(zz_decode_SRC2_4) + begin + zz_decode_SRC2_5(19) <= zz_decode_SRC2_4; + zz_decode_SRC2_5(18) <= zz_decode_SRC2_4; + zz_decode_SRC2_5(17) <= zz_decode_SRC2_4; + zz_decode_SRC2_5(16) <= zz_decode_SRC2_4; + zz_decode_SRC2_5(15) <= zz_decode_SRC2_4; + zz_decode_SRC2_5(14) <= zz_decode_SRC2_4; + zz_decode_SRC2_5(13) <= zz_decode_SRC2_4; + zz_decode_SRC2_5(12) <= zz_decode_SRC2_4; + zz_decode_SRC2_5(11) <= zz_decode_SRC2_4; + zz_decode_SRC2_5(10) <= zz_decode_SRC2_4; + zz_decode_SRC2_5(9) <= zz_decode_SRC2_4; + zz_decode_SRC2_5(8) <= zz_decode_SRC2_4; + zz_decode_SRC2_5(7) <= zz_decode_SRC2_4; + zz_decode_SRC2_5(6) <= zz_decode_SRC2_4; + zz_decode_SRC2_5(5) <= zz_decode_SRC2_4; + zz_decode_SRC2_5(4) <= zz_decode_SRC2_4; + zz_decode_SRC2_5(3) <= zz_decode_SRC2_4; + zz_decode_SRC2_5(2) <= zz_decode_SRC2_4; + zz_decode_SRC2_5(1) <= zz_decode_SRC2_4; + zz_decode_SRC2_5(0) <= zz_decode_SRC2_4; + end process; + + process(decode_SRC2_CTRL,zz_decode_SRC2_1,zz_decode_SRC2_3,decode_INSTRUCTION,zz_decode_SRC2_5,zz_decode_SRC2) + begin + case decode_SRC2_CTRL is + when Src2CtrlEnum_seq_RS => + zz_decode_SRC2_6 <= zz_decode_SRC2_1; + when Src2CtrlEnum_seq_IMI => + zz_decode_SRC2_6 <= pkg_cat(zz_decode_SRC2_3,pkg_extract(decode_INSTRUCTION,31,20)); + when Src2CtrlEnum_seq_IMS => + zz_decode_SRC2_6 <= pkg_cat(zz_decode_SRC2_5,pkg_cat(pkg_extract(decode_INSTRUCTION,31,25),pkg_extract(decode_INSTRUCTION,11,7))); + when others => + zz_decode_SRC2_6 <= std_logic_vector(zz_decode_SRC2); + end case; + end process; + + process(execute_SRC1,execute_SRC_USE_SUB_LESS,execute_SRC2,execute_SRC2_FORCE_ZERO) + begin + execute_SrcPlugin_addSub <= std_logic_vector(((signed(execute_SRC1) + signed(pkg_mux(execute_SRC_USE_SUB_LESS,pkg_not(execute_SRC2),execute_SRC2))) + pkg_mux(execute_SRC_USE_SUB_LESS,pkg_signed("00000000000000000000000000000001"),pkg_signed("00000000000000000000000000000000")))); + if execute_SRC2_FORCE_ZERO = '1' then + execute_SrcPlugin_addSub <= execute_SRC1; + end if; + end process; + + execute_SrcPlugin_less <= pkg_mux(pkg_toStdLogic(pkg_extract(execute_SRC1,31) = pkg_extract(execute_SRC2,31)),pkg_extract(execute_SrcPlugin_addSub,31),pkg_mux(execute_SRC_LESS_UNSIGNED,pkg_extract(execute_SRC2,31),pkg_extract(execute_SRC1,31))); + execute_LightShifterPlugin_isShift <= pkg_toStdLogic(execute_SHIFT_CTRL /= ShiftCtrlEnum_seq_DISABLE_1); + execute_LightShifterPlugin_amplitude <= pkg_mux(execute_LightShifterPlugin_isActive,execute_LightShifterPlugin_amplitudeReg,unsigned(pkg_extract(execute_SRC2,4,0))); + execute_LightShifterPlugin_shiftInput <= pkg_mux(execute_LightShifterPlugin_isActive,memory_REGFILE_WRITE_DATA,execute_SRC1); + execute_LightShifterPlugin_done <= pkg_toStdLogic(pkg_extract(execute_LightShifterPlugin_amplitude,4,1) = pkg_unsigned("0000")); + when_ShiftPlugins_l169 <= ((execute_arbitration_isValid and execute_LightShifterPlugin_isShift) and pkg_toStdLogic(pkg_extract(execute_SRC2,4,0) /= pkg_stdLogicVector("00000"))); + process(execute_SHIFT_CTRL,execute_LightShifterPlugin_shiftInput) + begin + case execute_SHIFT_CTRL is + when ShiftCtrlEnum_seq_SLL_1 => + zz_execute_to_memory_REGFILE_WRITE_DATA_1 <= std_logic_vector(shift_left(unsigned(execute_LightShifterPlugin_shiftInput),1)); + when others => + zz_execute_to_memory_REGFILE_WRITE_DATA_1 <= std_logic_vector(pkg_shiftRight(signed(pkg_cat(pkg_toStdLogicVector((pkg_toStdLogic(execute_SHIFT_CTRL = ShiftCtrlEnum_seq_SRA_1) and pkg_extract(execute_LightShifterPlugin_shiftInput,31))),execute_LightShifterPlugin_shiftInput)),1)); + end case; + end process; + + when_ShiftPlugins_l175 <= (not execute_arbitration_isStuckByOthers); + when_ShiftPlugins_l184 <= (not execute_LightShifterPlugin_done); + process(HazardSimplePlugin_writeBackBuffer_valid,HazardSimplePlugin_addr0Match,when_HazardSimplePlugin_l57,when_HazardSimplePlugin_l58,when_HazardSimplePlugin_l59,when_HazardSimplePlugin_l57_1,when_HazardSimplePlugin_l58_1,when_HazardSimplePlugin_l59_1,when_HazardSimplePlugin_l57_2,when_HazardSimplePlugin_l58_2,when_HazardSimplePlugin_l59_2,when_HazardSimplePlugin_l105) + begin + HazardSimplePlugin_src0Hazard <= pkg_toStdLogic(false); + if HazardSimplePlugin_writeBackBuffer_valid = '1' then + if HazardSimplePlugin_addr0Match = '1' then + HazardSimplePlugin_src0Hazard <= pkg_toStdLogic(true); + end if; + end if; + if when_HazardSimplePlugin_l57 = '1' then + if when_HazardSimplePlugin_l58 = '1' then + if when_HazardSimplePlugin_l59 = '1' then + HazardSimplePlugin_src0Hazard <= pkg_toStdLogic(true); + end if; + end if; + end if; + if when_HazardSimplePlugin_l57_1 = '1' then + if when_HazardSimplePlugin_l58_1 = '1' then + if when_HazardSimplePlugin_l59_1 = '1' then + HazardSimplePlugin_src0Hazard <= pkg_toStdLogic(true); + end if; + end if; + end if; + if when_HazardSimplePlugin_l57_2 = '1' then + if when_HazardSimplePlugin_l58_2 = '1' then + if when_HazardSimplePlugin_l59_2 = '1' then + HazardSimplePlugin_src0Hazard <= pkg_toStdLogic(true); + end if; + end if; + end if; + if when_HazardSimplePlugin_l105 = '1' then + HazardSimplePlugin_src0Hazard <= pkg_toStdLogic(false); + end if; + end process; + + process(HazardSimplePlugin_writeBackBuffer_valid,HazardSimplePlugin_addr1Match,when_HazardSimplePlugin_l57,when_HazardSimplePlugin_l58,when_HazardSimplePlugin_l62,when_HazardSimplePlugin_l57_1,when_HazardSimplePlugin_l58_1,when_HazardSimplePlugin_l62_1,when_HazardSimplePlugin_l57_2,when_HazardSimplePlugin_l58_2,when_HazardSimplePlugin_l62_2,when_HazardSimplePlugin_l108) + begin + HazardSimplePlugin_src1Hazard <= pkg_toStdLogic(false); + if HazardSimplePlugin_writeBackBuffer_valid = '1' then + if HazardSimplePlugin_addr1Match = '1' then + HazardSimplePlugin_src1Hazard <= pkg_toStdLogic(true); + end if; + end if; + if when_HazardSimplePlugin_l57 = '1' then + if when_HazardSimplePlugin_l58 = '1' then + if when_HazardSimplePlugin_l62 = '1' then + HazardSimplePlugin_src1Hazard <= pkg_toStdLogic(true); + end if; + end if; + end if; + if when_HazardSimplePlugin_l57_1 = '1' then + if when_HazardSimplePlugin_l58_1 = '1' then + if when_HazardSimplePlugin_l62_1 = '1' then + HazardSimplePlugin_src1Hazard <= pkg_toStdLogic(true); + end if; + end if; + end if; + if when_HazardSimplePlugin_l57_2 = '1' then + if when_HazardSimplePlugin_l58_2 = '1' then + if when_HazardSimplePlugin_l62_2 = '1' then + HazardSimplePlugin_src1Hazard <= pkg_toStdLogic(true); + end if; + end if; + end if; + if when_HazardSimplePlugin_l108 = '1' then + HazardSimplePlugin_src1Hazard <= pkg_toStdLogic(false); + end if; + end process; + + HazardSimplePlugin_writeBackWrites_valid <= (zz_lastStageRegFileWrite_valid and writeBack_arbitration_isFiring); + HazardSimplePlugin_writeBackWrites_payload_address <= pkg_extract(zz_lastStageRegFileWrite_payload_address,11,7); + HazardSimplePlugin_writeBackWrites_payload_data <= zz_lastStageRegFileWrite_payload_data; + HazardSimplePlugin_addr0Match <= pkg_toStdLogic(HazardSimplePlugin_writeBackBuffer_payload_address = pkg_extract(decode_INSTRUCTION,19,15)); + HazardSimplePlugin_addr1Match <= pkg_toStdLogic(HazardSimplePlugin_writeBackBuffer_payload_address = pkg_extract(decode_INSTRUCTION,24,20)); + when_HazardSimplePlugin_l59 <= pkg_toStdLogic(pkg_extract(writeBack_INSTRUCTION,11,7) = pkg_extract(decode_INSTRUCTION,19,15)); + when_HazardSimplePlugin_l62 <= pkg_toStdLogic(pkg_extract(writeBack_INSTRUCTION,11,7) = pkg_extract(decode_INSTRUCTION,24,20)); + when_HazardSimplePlugin_l57 <= (writeBack_arbitration_isValid and writeBack_REGFILE_WRITE_VALID); + when_HazardSimplePlugin_l58 <= (pkg_toStdLogic(true) or (not pkg_toStdLogic(true))); + when_HazardSimplePlugin_l59_1 <= pkg_toStdLogic(pkg_extract(memory_INSTRUCTION,11,7) = pkg_extract(decode_INSTRUCTION,19,15)); + when_HazardSimplePlugin_l62_1 <= pkg_toStdLogic(pkg_extract(memory_INSTRUCTION,11,7) = pkg_extract(decode_INSTRUCTION,24,20)); + when_HazardSimplePlugin_l57_1 <= (memory_arbitration_isValid and memory_REGFILE_WRITE_VALID); + when_HazardSimplePlugin_l58_1 <= (pkg_toStdLogic(true) or (not memory_BYPASSABLE_MEMORY_STAGE)); + when_HazardSimplePlugin_l59_2 <= pkg_toStdLogic(pkg_extract(execute_INSTRUCTION,11,7) = pkg_extract(decode_INSTRUCTION,19,15)); + when_HazardSimplePlugin_l62_2 <= pkg_toStdLogic(pkg_extract(execute_INSTRUCTION,11,7) = pkg_extract(decode_INSTRUCTION,24,20)); + when_HazardSimplePlugin_l57_2 <= (execute_arbitration_isValid and execute_REGFILE_WRITE_VALID); + when_HazardSimplePlugin_l58_2 <= (pkg_toStdLogic(true) or (not execute_BYPASSABLE_EXECUTE_STAGE)); + when_HazardSimplePlugin_l105 <= (not decode_RS1_USE); + when_HazardSimplePlugin_l108 <= (not decode_RS2_USE); + when_HazardSimplePlugin_l113 <= (decode_arbitration_isValid and (HazardSimplePlugin_src0Hazard or HazardSimplePlugin_src1Hazard)); + execute_BranchPlugin_eq <= pkg_toStdLogic(execute_SRC1 = execute_SRC2); + switch_Misc_l210_2 <= pkg_extract(execute_INSTRUCTION,14,12); + process(switch_Misc_l210_2,execute_BranchPlugin_eq,execute_SRC_LESS) + begin + if (switch_Misc_l210_2 = pkg_stdLogicVector("000")) then + zz_execute_BRANCH_DO <= execute_BranchPlugin_eq; + elsif (switch_Misc_l210_2 = pkg_stdLogicVector("001")) then + zz_execute_BRANCH_DO <= (not execute_BranchPlugin_eq); + elsif (pkg_toStdLogic((switch_Misc_l210_2 and pkg_stdLogicVector("101")) = pkg_stdLogicVector("101")) = '1') then + zz_execute_BRANCH_DO <= (not execute_SRC_LESS); + else + zz_execute_BRANCH_DO <= execute_SRC_LESS; + end if; + end process; + + process(execute_BRANCH_CTRL,zz_execute_BRANCH_DO) + begin + case execute_BRANCH_CTRL is + when BranchCtrlEnum_seq_INC => + zz_execute_BRANCH_DO_1 <= pkg_toStdLogic(false); + when BranchCtrlEnum_seq_JAL => + zz_execute_BRANCH_DO_1 <= pkg_toStdLogic(true); + when BranchCtrlEnum_seq_JALR => + zz_execute_BRANCH_DO_1 <= pkg_toStdLogic(true); + when others => + zz_execute_BRANCH_DO_1 <= zz_execute_BRANCH_DO; + end case; + end process; + + execute_BranchPlugin_branch_src1 <= pkg_mux(pkg_toStdLogic(execute_BRANCH_CTRL = BranchCtrlEnum_seq_JALR),unsigned(execute_RS1),execute_PC); + zz_execute_BranchPlugin_branch_src2 <= pkg_extract(pkg_cat(pkg_cat(pkg_cat(pkg_toStdLogicVector(pkg_extract(execute_INSTRUCTION,31)),pkg_extract(execute_INSTRUCTION,19,12)),pkg_toStdLogicVector(pkg_extract(execute_INSTRUCTION,20))),pkg_extract(execute_INSTRUCTION,30,21)),19); + process(zz_execute_BranchPlugin_branch_src2) + begin + zz_execute_BranchPlugin_branch_src2_1(10) <= zz_execute_BranchPlugin_branch_src2; + zz_execute_BranchPlugin_branch_src2_1(9) <= zz_execute_BranchPlugin_branch_src2; + zz_execute_BranchPlugin_branch_src2_1(8) <= zz_execute_BranchPlugin_branch_src2; + zz_execute_BranchPlugin_branch_src2_1(7) <= zz_execute_BranchPlugin_branch_src2; + zz_execute_BranchPlugin_branch_src2_1(6) <= zz_execute_BranchPlugin_branch_src2; + zz_execute_BranchPlugin_branch_src2_1(5) <= zz_execute_BranchPlugin_branch_src2; + zz_execute_BranchPlugin_branch_src2_1(4) <= zz_execute_BranchPlugin_branch_src2; + zz_execute_BranchPlugin_branch_src2_1(3) <= zz_execute_BranchPlugin_branch_src2; + zz_execute_BranchPlugin_branch_src2_1(2) <= zz_execute_BranchPlugin_branch_src2; + zz_execute_BranchPlugin_branch_src2_1(1) <= zz_execute_BranchPlugin_branch_src2; + zz_execute_BranchPlugin_branch_src2_1(0) <= zz_execute_BranchPlugin_branch_src2; + end process; + + zz_execute_BranchPlugin_branch_src2_2 <= pkg_extract(execute_INSTRUCTION,31); + process(zz_execute_BranchPlugin_branch_src2_2) + begin + zz_execute_BranchPlugin_branch_src2_3(19) <= zz_execute_BranchPlugin_branch_src2_2; + zz_execute_BranchPlugin_branch_src2_3(18) <= zz_execute_BranchPlugin_branch_src2_2; + zz_execute_BranchPlugin_branch_src2_3(17) <= zz_execute_BranchPlugin_branch_src2_2; + zz_execute_BranchPlugin_branch_src2_3(16) <= zz_execute_BranchPlugin_branch_src2_2; + zz_execute_BranchPlugin_branch_src2_3(15) <= zz_execute_BranchPlugin_branch_src2_2; + zz_execute_BranchPlugin_branch_src2_3(14) <= zz_execute_BranchPlugin_branch_src2_2; + zz_execute_BranchPlugin_branch_src2_3(13) <= zz_execute_BranchPlugin_branch_src2_2; + zz_execute_BranchPlugin_branch_src2_3(12) <= zz_execute_BranchPlugin_branch_src2_2; + zz_execute_BranchPlugin_branch_src2_3(11) <= zz_execute_BranchPlugin_branch_src2_2; + zz_execute_BranchPlugin_branch_src2_3(10) <= zz_execute_BranchPlugin_branch_src2_2; + zz_execute_BranchPlugin_branch_src2_3(9) <= zz_execute_BranchPlugin_branch_src2_2; + zz_execute_BranchPlugin_branch_src2_3(8) <= zz_execute_BranchPlugin_branch_src2_2; + zz_execute_BranchPlugin_branch_src2_3(7) <= zz_execute_BranchPlugin_branch_src2_2; + zz_execute_BranchPlugin_branch_src2_3(6) <= zz_execute_BranchPlugin_branch_src2_2; + zz_execute_BranchPlugin_branch_src2_3(5) <= zz_execute_BranchPlugin_branch_src2_2; + zz_execute_BranchPlugin_branch_src2_3(4) <= zz_execute_BranchPlugin_branch_src2_2; + zz_execute_BranchPlugin_branch_src2_3(3) <= zz_execute_BranchPlugin_branch_src2_2; + zz_execute_BranchPlugin_branch_src2_3(2) <= zz_execute_BranchPlugin_branch_src2_2; + zz_execute_BranchPlugin_branch_src2_3(1) <= zz_execute_BranchPlugin_branch_src2_2; + zz_execute_BranchPlugin_branch_src2_3(0) <= zz_execute_BranchPlugin_branch_src2_2; + end process; + + zz_execute_BranchPlugin_branch_src2_4 <= pkg_extract(pkg_cat(pkg_cat(pkg_cat(pkg_toStdLogicVector(pkg_extract(execute_INSTRUCTION,31)),pkg_toStdLogicVector(pkg_extract(execute_INSTRUCTION,7))),pkg_extract(execute_INSTRUCTION,30,25)),pkg_extract(execute_INSTRUCTION,11,8)),11); + process(zz_execute_BranchPlugin_branch_src2_4) + begin + zz_execute_BranchPlugin_branch_src2_5(18) <= zz_execute_BranchPlugin_branch_src2_4; + zz_execute_BranchPlugin_branch_src2_5(17) <= zz_execute_BranchPlugin_branch_src2_4; + zz_execute_BranchPlugin_branch_src2_5(16) <= zz_execute_BranchPlugin_branch_src2_4; + zz_execute_BranchPlugin_branch_src2_5(15) <= zz_execute_BranchPlugin_branch_src2_4; + zz_execute_BranchPlugin_branch_src2_5(14) <= zz_execute_BranchPlugin_branch_src2_4; + zz_execute_BranchPlugin_branch_src2_5(13) <= zz_execute_BranchPlugin_branch_src2_4; + zz_execute_BranchPlugin_branch_src2_5(12) <= zz_execute_BranchPlugin_branch_src2_4; + zz_execute_BranchPlugin_branch_src2_5(11) <= zz_execute_BranchPlugin_branch_src2_4; + zz_execute_BranchPlugin_branch_src2_5(10) <= zz_execute_BranchPlugin_branch_src2_4; + zz_execute_BranchPlugin_branch_src2_5(9) <= zz_execute_BranchPlugin_branch_src2_4; + zz_execute_BranchPlugin_branch_src2_5(8) <= zz_execute_BranchPlugin_branch_src2_4; + zz_execute_BranchPlugin_branch_src2_5(7) <= zz_execute_BranchPlugin_branch_src2_4; + zz_execute_BranchPlugin_branch_src2_5(6) <= zz_execute_BranchPlugin_branch_src2_4; + zz_execute_BranchPlugin_branch_src2_5(5) <= zz_execute_BranchPlugin_branch_src2_4; + zz_execute_BranchPlugin_branch_src2_5(4) <= zz_execute_BranchPlugin_branch_src2_4; + zz_execute_BranchPlugin_branch_src2_5(3) <= zz_execute_BranchPlugin_branch_src2_4; + zz_execute_BranchPlugin_branch_src2_5(2) <= zz_execute_BranchPlugin_branch_src2_4; + zz_execute_BranchPlugin_branch_src2_5(1) <= zz_execute_BranchPlugin_branch_src2_4; + zz_execute_BranchPlugin_branch_src2_5(0) <= zz_execute_BranchPlugin_branch_src2_4; + end process; + + process(execute_BRANCH_CTRL,zz_execute_BranchPlugin_branch_src2_1,execute_INSTRUCTION,zz_execute_BranchPlugin_branch_src2_3,zz_execute_BranchPlugin_branch_src2_5) + begin + case execute_BRANCH_CTRL is + when BranchCtrlEnum_seq_JAL => + zz_execute_BranchPlugin_branch_src2_6 <= pkg_cat(pkg_cat(zz_execute_BranchPlugin_branch_src2_1,pkg_cat(pkg_cat(pkg_cat(pkg_toStdLogicVector(pkg_extract(execute_INSTRUCTION,31)),pkg_extract(execute_INSTRUCTION,19,12)),pkg_toStdLogicVector(pkg_extract(execute_INSTRUCTION,20))),pkg_extract(execute_INSTRUCTION,30,21))),pkg_toStdLogicVector(pkg_toStdLogic(false))); + when BranchCtrlEnum_seq_JALR => + zz_execute_BranchPlugin_branch_src2_6 <= pkg_cat(zz_execute_BranchPlugin_branch_src2_3,pkg_extract(execute_INSTRUCTION,31,20)); + when others => + zz_execute_BranchPlugin_branch_src2_6 <= pkg_cat(pkg_cat(zz_execute_BranchPlugin_branch_src2_5,pkg_cat(pkg_cat(pkg_cat(pkg_toStdLogicVector(pkg_extract(execute_INSTRUCTION,31)),pkg_toStdLogicVector(pkg_extract(execute_INSTRUCTION,7))),pkg_extract(execute_INSTRUCTION,30,25)),pkg_extract(execute_INSTRUCTION,11,8))),pkg_toStdLogicVector(pkg_toStdLogic(false))); + end case; + end process; + + execute_BranchPlugin_branch_src2 <= unsigned(zz_execute_BranchPlugin_branch_src2_6); + execute_BranchPlugin_branchAdder <= (execute_BranchPlugin_branch_src1 + execute_BranchPlugin_branch_src2); + BranchPlugin_jumpInterface_valid <= ((memory_arbitration_isValid and memory_BRANCH_DO) and (not pkg_toStdLogic(false))); + BranchPlugin_jumpInterface_payload <= memory_BRANCH_CALC; + when_DebugPlugin_l225 <= (DebugPlugin_haltIt and (not DebugPlugin_isPipBusy)); + DebugPlugin_allowEBreak <= (DebugPlugin_debugUsed and (not DebugPlugin_disableEbreak)); + process(debug_bus_cmd_valid,switch_DebugPlugin_l267,debug_bus_cmd_payload_wr,IBusSimplePlugin_injectionPort_ready) + begin + debug_bus_cmd_ready_read_buffer <= pkg_toStdLogic(true); + if debug_bus_cmd_valid = '1' then + case switch_DebugPlugin_l267 is + when "000001" => + if debug_bus_cmd_payload_wr = '1' then + debug_bus_cmd_ready_read_buffer <= IBusSimplePlugin_injectionPort_ready; + end if; + when others => + end case; + end if; + end process; + + process(DebugPlugin_busReadDataReg,when_DebugPlugin_l244,DebugPlugin_resetIt,DebugPlugin_haltIt,DebugPlugin_isPipBusy,DebugPlugin_haltedByBreak,DebugPlugin_stepIt) + begin + debug_bus_rsp_data <= DebugPlugin_busReadDataReg; + if when_DebugPlugin_l244 = '1' then + debug_bus_rsp_data(0) <= DebugPlugin_resetIt; + debug_bus_rsp_data(1) <= DebugPlugin_haltIt; + debug_bus_rsp_data(2) <= DebugPlugin_isPipBusy; + debug_bus_rsp_data(3) <= DebugPlugin_haltedByBreak; + debug_bus_rsp_data(4) <= DebugPlugin_stepIt; + end if; + end process; + + when_DebugPlugin_l244 <= (not zz_when_DebugPlugin_l244); + process(debug_bus_cmd_valid,switch_DebugPlugin_l267,debug_bus_cmd_payload_wr) + begin + IBusSimplePlugin_injectionPort_valid <= pkg_toStdLogic(false); + if debug_bus_cmd_valid = '1' then + case switch_DebugPlugin_l267 is + when "000001" => + if debug_bus_cmd_payload_wr = '1' then + IBusSimplePlugin_injectionPort_valid <= pkg_toStdLogic(true); + end if; + when others => + end case; + end if; + end process; + + IBusSimplePlugin_injectionPort_payload <= debug_bus_cmd_payload_data; + switch_DebugPlugin_l267 <= pkg_extract(debug_bus_cmd_payload_address,7,2); + when_DebugPlugin_l271 <= pkg_extract(debug_bus_cmd_payload_data,16); + when_DebugPlugin_l271_1 <= pkg_extract(debug_bus_cmd_payload_data,24); + when_DebugPlugin_l272 <= pkg_extract(debug_bus_cmd_payload_data,17); + when_DebugPlugin_l272_1 <= pkg_extract(debug_bus_cmd_payload_data,25); + when_DebugPlugin_l273 <= pkg_extract(debug_bus_cmd_payload_data,25); + when_DebugPlugin_l274 <= pkg_extract(debug_bus_cmd_payload_data,25); + when_DebugPlugin_l275 <= pkg_extract(debug_bus_cmd_payload_data,18); + when_DebugPlugin_l275_1 <= pkg_extract(debug_bus_cmd_payload_data,26); + when_DebugPlugin_l295 <= (execute_arbitration_isValid and execute_DO_EBREAK); + when_DebugPlugin_l298 <= pkg_toStdLogic(pkg_toStdLogic(pkg_cat(pkg_toStdLogicVector(writeBack_arbitration_isValid),pkg_toStdLogicVector(memory_arbitration_isValid)) /= pkg_stdLogicVector("00")) = pkg_toStdLogic(false)); + when_DebugPlugin_l311 <= (DebugPlugin_stepIt and IBusSimplePlugin_incomingInstruction); + debug_resetOut <= DebugPlugin_resetIt_regNext; + when_DebugPlugin_l331 <= (DebugPlugin_haltIt or DebugPlugin_stepIt); + when_Pipeline_l124 <= (not execute_arbitration_isStuck); + when_Pipeline_l124_1 <= (not memory_arbitration_isStuck); + when_Pipeline_l124_2 <= (not writeBack_arbitration_isStuck); + when_Pipeline_l124_3 <= (not execute_arbitration_isStuck); + when_Pipeline_l124_4 <= (not memory_arbitration_isStuck); + when_Pipeline_l124_5 <= (not writeBack_arbitration_isStuck); + when_Pipeline_l124_6 <= (not execute_arbitration_isStuck); + when_Pipeline_l124_7 <= (not memory_arbitration_isStuck); + when_Pipeline_l124_8 <= (not writeBack_arbitration_isStuck); + when_Pipeline_l124_9 <= (not execute_arbitration_isStuck); + when_Pipeline_l124_10 <= (not execute_arbitration_isStuck); + zz_decode_SRC1_CTRL <= zz_decode_SRC1_CTRL_1; + when_Pipeline_l124_11 <= (not execute_arbitration_isStuck); + when_Pipeline_l124_12 <= (not execute_arbitration_isStuck); + when_Pipeline_l124_13 <= (not memory_arbitration_isStuck); + when_Pipeline_l124_14 <= (not writeBack_arbitration_isStuck); + zz_decode_SRC2_CTRL <= zz_decode_SRC2_CTRL_1; + when_Pipeline_l124_15 <= (not execute_arbitration_isStuck); + when_Pipeline_l124_16 <= (not memory_arbitration_isStuck); + when_Pipeline_l124_17 <= (not writeBack_arbitration_isStuck); + when_Pipeline_l124_18 <= (not execute_arbitration_isStuck); + when_Pipeline_l124_19 <= (not execute_arbitration_isStuck); + when_Pipeline_l124_20 <= (not memory_arbitration_isStuck); + when_Pipeline_l124_21 <= (not execute_arbitration_isStuck); + when_Pipeline_l124_22 <= (not memory_arbitration_isStuck); + when_Pipeline_l124_23 <= (not execute_arbitration_isStuck); + zz_decode_to_execute_ENV_CTRL_1 <= decode_ENV_CTRL; + zz_execute_to_memory_ENV_CTRL_1 <= execute_ENV_CTRL; + zz_memory_to_writeBack_ENV_CTRL_1 <= memory_ENV_CTRL; + zz_decode_ENV_CTRL <= zz_decode_ENV_CTRL_1; + when_Pipeline_l124_24 <= (not execute_arbitration_isStuck); + zz_execute_ENV_CTRL <= decode_to_execute_ENV_CTRL; + when_Pipeline_l124_25 <= (not memory_arbitration_isStuck); + zz_memory_ENV_CTRL <= execute_to_memory_ENV_CTRL; + when_Pipeline_l124_26 <= (not writeBack_arbitration_isStuck); + zz_writeBack_ENV_CTRL <= memory_to_writeBack_ENV_CTRL; + zz_decode_to_execute_ALU_CTRL_1 <= decode_ALU_CTRL; + zz_decode_ALU_CTRL <= zz_decode_ALU_CTRL_1; + when_Pipeline_l124_27 <= (not execute_arbitration_isStuck); + zz_execute_ALU_CTRL <= decode_to_execute_ALU_CTRL; + when_Pipeline_l124_28 <= (not execute_arbitration_isStuck); + zz_decode_to_execute_ALU_BITWISE_CTRL_1 <= decode_ALU_BITWISE_CTRL; + zz_decode_ALU_BITWISE_CTRL <= zz_decode_ALU_BITWISE_CTRL_1; + when_Pipeline_l124_29 <= (not execute_arbitration_isStuck); + zz_execute_ALU_BITWISE_CTRL <= decode_to_execute_ALU_BITWISE_CTRL; + zz_decode_to_execute_SHIFT_CTRL_1 <= decode_SHIFT_CTRL; + zz_decode_SHIFT_CTRL <= zz_decode_SHIFT_CTRL_1; + when_Pipeline_l124_30 <= (not execute_arbitration_isStuck); + zz_execute_SHIFT_CTRL <= decode_to_execute_SHIFT_CTRL; + zz_decode_to_execute_BRANCH_CTRL_1 <= decode_BRANCH_CTRL; + zz_decode_BRANCH_CTRL <= zz_decode_BRANCH_CTRL_1; + when_Pipeline_l124_31 <= (not execute_arbitration_isStuck); + zz_execute_BRANCH_CTRL <= decode_to_execute_BRANCH_CTRL; + when_Pipeline_l124_32 <= (not execute_arbitration_isStuck); + when_Pipeline_l124_33 <= (not execute_arbitration_isStuck); + when_Pipeline_l124_34 <= (not execute_arbitration_isStuck); + when_Pipeline_l124_35 <= (not execute_arbitration_isStuck); + when_Pipeline_l124_36 <= (not execute_arbitration_isStuck); + when_Pipeline_l124_37 <= (not execute_arbitration_isStuck); + when_Pipeline_l124_38 <= (not memory_arbitration_isStuck); + when_Pipeline_l124_39 <= (not writeBack_arbitration_isStuck); + when_Pipeline_l124_40 <= ((not memory_arbitration_isStuck) and (not execute_arbitration_isStuckByOthers)); + when_Pipeline_l124_41 <= (not writeBack_arbitration_isStuck); + when_Pipeline_l124_42 <= (not memory_arbitration_isStuck); + when_Pipeline_l124_43 <= (not memory_arbitration_isStuck); + when_Pipeline_l124_44 <= (not writeBack_arbitration_isStuck); + decode_arbitration_isFlushed <= (pkg_toStdLogic(pkg_cat(pkg_toStdLogicVector(writeBack_arbitration_flushNext),pkg_cat(pkg_toStdLogicVector(memory_arbitration_flushNext),pkg_toStdLogicVector(execute_arbitration_flushNext))) /= pkg_stdLogicVector("000")) or pkg_toStdLogic(pkg_cat(pkg_toStdLogicVector(writeBack_arbitration_flushIt),pkg_cat(pkg_toStdLogicVector(memory_arbitration_flushIt),pkg_cat(pkg_toStdLogicVector(execute_arbitration_flushIt),pkg_toStdLogicVector(decode_arbitration_flushIt)))) /= pkg_stdLogicVector("0000"))); + execute_arbitration_isFlushed <= (pkg_toStdLogic(pkg_cat(pkg_toStdLogicVector(writeBack_arbitration_flushNext),pkg_toStdLogicVector(memory_arbitration_flushNext)) /= pkg_stdLogicVector("00")) or pkg_toStdLogic(pkg_cat(pkg_toStdLogicVector(writeBack_arbitration_flushIt),pkg_cat(pkg_toStdLogicVector(memory_arbitration_flushIt),pkg_toStdLogicVector(execute_arbitration_flushIt))) /= pkg_stdLogicVector("000"))); + memory_arbitration_isFlushed <= (pkg_toStdLogic(pkg_toStdLogicVector(writeBack_arbitration_flushNext) /= pkg_stdLogicVector("0")) or pkg_toStdLogic(pkg_cat(pkg_toStdLogicVector(writeBack_arbitration_flushIt),pkg_toStdLogicVector(memory_arbitration_flushIt)) /= pkg_stdLogicVector("00"))); + writeBack_arbitration_isFlushed <= (pkg_toStdLogic(false) or pkg_toStdLogic(pkg_toStdLogicVector(writeBack_arbitration_flushIt) /= pkg_stdLogicVector("0"))); + decode_arbitration_isStuckByOthers <= (decode_arbitration_haltByOther or (((pkg_toStdLogic(false) or execute_arbitration_isStuck) or memory_arbitration_isStuck) or writeBack_arbitration_isStuck)); + decode_arbitration_isStuck <= (decode_arbitration_haltItself or decode_arbitration_isStuckByOthers); + decode_arbitration_isMoving <= ((not decode_arbitration_isStuck) and (not decode_arbitration_removeIt)); + decode_arbitration_isFiring <= ((decode_arbitration_isValid and (not decode_arbitration_isStuck)) and (not decode_arbitration_removeIt)); + execute_arbitration_isStuckByOthers <= (execute_arbitration_haltByOther or ((pkg_toStdLogic(false) or memory_arbitration_isStuck) or writeBack_arbitration_isStuck)); + execute_arbitration_isStuck <= (execute_arbitration_haltItself or execute_arbitration_isStuckByOthers); + execute_arbitration_isMoving <= ((not execute_arbitration_isStuck) and (not execute_arbitration_removeIt)); + execute_arbitration_isFiring <= ((execute_arbitration_isValid and (not execute_arbitration_isStuck)) and (not execute_arbitration_removeIt)); + memory_arbitration_isStuckByOthers <= (memory_arbitration_haltByOther or (pkg_toStdLogic(false) or writeBack_arbitration_isStuck)); + memory_arbitration_isStuck <= (memory_arbitration_haltItself or memory_arbitration_isStuckByOthers); + memory_arbitration_isMoving <= ((not memory_arbitration_isStuck) and (not memory_arbitration_removeIt)); + memory_arbitration_isFiring <= ((memory_arbitration_isValid and (not memory_arbitration_isStuck)) and (not memory_arbitration_removeIt)); + writeBack_arbitration_isStuckByOthers <= (writeBack_arbitration_haltByOther or pkg_toStdLogic(false)); + writeBack_arbitration_isStuck <= (writeBack_arbitration_haltItself or writeBack_arbitration_isStuckByOthers); + writeBack_arbitration_isMoving <= ((not writeBack_arbitration_isStuck) and (not writeBack_arbitration_removeIt)); + writeBack_arbitration_isFiring <= ((writeBack_arbitration_isValid and (not writeBack_arbitration_isStuck)) and (not writeBack_arbitration_removeIt)); + when_Pipeline_l151 <= ((not execute_arbitration_isStuck) or execute_arbitration_removeIt); + when_Pipeline_l154 <= ((not decode_arbitration_isStuck) and (not decode_arbitration_removeIt)); + when_Pipeline_l151_1 <= ((not memory_arbitration_isStuck) or memory_arbitration_removeIt); + when_Pipeline_l154_1 <= ((not execute_arbitration_isStuck) and (not execute_arbitration_removeIt)); + when_Pipeline_l151_2 <= ((not writeBack_arbitration_isStuck) or writeBack_arbitration_removeIt); + when_Pipeline_l154_2 <= ((not memory_arbitration_isStuck) and (not memory_arbitration_removeIt)); + process(switch_Fetcher_l365) + begin + IBusSimplePlugin_injectionPort_ready <= pkg_toStdLogic(false); + case switch_Fetcher_l365 is + when "100" => + IBusSimplePlugin_injectionPort_ready <= pkg_toStdLogic(true); + when others => + end case; + end process; + + when_Fetcher_l381 <= (not decode_arbitration_isStuck); + when_Fetcher_l401 <= pkg_toStdLogic(switch_Fetcher_l365 /= pkg_unsigned("000")); + when_CsrPlugin_l1277 <= (not execute_arbitration_isStuck); + when_CsrPlugin_l1277_1 <= (not execute_arbitration_isStuck); + when_CsrPlugin_l1277_2 <= (not execute_arbitration_isStuck); + when_CsrPlugin_l1277_3 <= (not execute_arbitration_isStuck); + switch_CsrPlugin_l723 <= pkg_extract(CsrPlugin_csrMapping_writeDataSignal,12,11); + process(execute_CsrPlugin_csr_768,CsrPlugin_mstatus_MPIE,CsrPlugin_mstatus_MIE,CsrPlugin_mstatus_MPP) + begin + zz_CsrPlugin_csrMapping_readDataInit <= pkg_stdLogicVector("00000000000000000000000000000000"); + if execute_CsrPlugin_csr_768 = '1' then + zz_CsrPlugin_csrMapping_readDataInit(7 downto 7) <= pkg_toStdLogicVector(CsrPlugin_mstatus_MPIE); + zz_CsrPlugin_csrMapping_readDataInit(3 downto 3) <= pkg_toStdLogicVector(CsrPlugin_mstatus_MIE); + zz_CsrPlugin_csrMapping_readDataInit(12 downto 11) <= std_logic_vector(CsrPlugin_mstatus_MPP); + end if; + end process; + + process(execute_CsrPlugin_csr_836,CsrPlugin_mip_MEIP,CsrPlugin_mip_MTIP,CsrPlugin_mip_MSIP) + begin + zz_CsrPlugin_csrMapping_readDataInit_1 <= pkg_stdLogicVector("00000000000000000000000000000000"); + if execute_CsrPlugin_csr_836 = '1' then + zz_CsrPlugin_csrMapping_readDataInit_1(11 downto 11) <= pkg_toStdLogicVector(CsrPlugin_mip_MEIP); + zz_CsrPlugin_csrMapping_readDataInit_1(7 downto 7) <= pkg_toStdLogicVector(CsrPlugin_mip_MTIP); + zz_CsrPlugin_csrMapping_readDataInit_1(3 downto 3) <= pkg_toStdLogicVector(CsrPlugin_mip_MSIP); + end if; + end process; + + process(execute_CsrPlugin_csr_772,CsrPlugin_mie_MEIE,CsrPlugin_mie_MTIE,CsrPlugin_mie_MSIE) + begin + zz_CsrPlugin_csrMapping_readDataInit_2 <= pkg_stdLogicVector("00000000000000000000000000000000"); + if execute_CsrPlugin_csr_772 = '1' then + zz_CsrPlugin_csrMapping_readDataInit_2(11 downto 11) <= pkg_toStdLogicVector(CsrPlugin_mie_MEIE); + zz_CsrPlugin_csrMapping_readDataInit_2(7 downto 7) <= pkg_toStdLogicVector(CsrPlugin_mie_MTIE); + zz_CsrPlugin_csrMapping_readDataInit_2(3 downto 3) <= pkg_toStdLogicVector(CsrPlugin_mie_MSIE); + end if; + end process; + + process(execute_CsrPlugin_csr_834,CsrPlugin_mcause_interrupt,CsrPlugin_mcause_exceptionCode) + begin + zz_CsrPlugin_csrMapping_readDataInit_3 <= pkg_stdLogicVector("00000000000000000000000000000000"); + if execute_CsrPlugin_csr_834 = '1' then + zz_CsrPlugin_csrMapping_readDataInit_3(31 downto 31) <= pkg_toStdLogicVector(CsrPlugin_mcause_interrupt); + zz_CsrPlugin_csrMapping_readDataInit_3(3 downto 0) <= std_logic_vector(CsrPlugin_mcause_exceptionCode); + end if; + end process; + + CsrPlugin_csrMapping_readDataInit <= ((zz_CsrPlugin_csrMapping_readDataInit or zz_CsrPlugin_csrMapping_readDataInit_1) or (zz_CsrPlugin_csrMapping_readDataInit_2 or zz_CsrPlugin_csrMapping_readDataInit_3)); + when_CsrPlugin_l1310 <= pkg_toStdLogic(CsrPlugin_privilege < unsigned(pkg_extract(execute_CsrPlugin_csrAddress,9,8))); + when_CsrPlugin_l1315 <= ((not execute_arbitration_isValid) or (not execute_IS_CSR)); + process(io_mainClk, resetCtrl_systemReset) + begin + if resetCtrl_systemReset = '1' then + IBusSimplePlugin_fetchPc_pcReg <= pkg_unsigned("10000000000000000000000000000000"); + IBusSimplePlugin_fetchPc_correctionReg <= pkg_toStdLogic(false); + IBusSimplePlugin_fetchPc_booted <= pkg_toStdLogic(false); + IBusSimplePlugin_fetchPc_inc <= pkg_toStdLogic(false); + zz_IBusSimplePlugin_iBusRsp_stages_0_output_ready_2 <= pkg_toStdLogic(false); + zz_IBusSimplePlugin_iBusRsp_stages_1_output_m2sPipe_valid <= pkg_toStdLogic(false); + zz_IBusSimplePlugin_injector_decodeInput_valid <= pkg_toStdLogic(false); + IBusSimplePlugin_injector_nextPcCalc_valids_0 <= pkg_toStdLogic(false); + IBusSimplePlugin_injector_nextPcCalc_valids_1 <= pkg_toStdLogic(false); + IBusSimplePlugin_injector_nextPcCalc_valids_2 <= pkg_toStdLogic(false); + IBusSimplePlugin_injector_nextPcCalc_valids_3 <= pkg_toStdLogic(false); + IBusSimplePlugin_injector_nextPcCalc_valids_4 <= pkg_toStdLogic(false); + IBusSimplePlugin_injector_nextPcCalc_valids_5 <= pkg_toStdLogic(false); + IBusSimplePlugin_pending_value <= pkg_unsigned("000"); + IBusSimplePlugin_rspJoin_rspBuffer_discardCounter <= pkg_unsigned("000"); + CsrPlugin_mstatus_MIE <= pkg_toStdLogic(false); + CsrPlugin_mstatus_MPIE <= pkg_toStdLogic(false); + CsrPlugin_mstatus_MPP <= pkg_unsigned("11"); + CsrPlugin_mie_MEIE <= pkg_toStdLogic(false); + CsrPlugin_mie_MTIE <= pkg_toStdLogic(false); + CsrPlugin_mie_MSIE <= pkg_toStdLogic(false); + CsrPlugin_mcycle <= pkg_unsigned("0000000000000000000000000000000000000000000000000000000000000000"); + CsrPlugin_minstret <= pkg_unsigned("0000000000000000000000000000000000000000000000000000000000000000"); + CsrPlugin_interrupt_valid <= pkg_toStdLogic(false); + CsrPlugin_pipelineLiberator_pcValids_0 <= pkg_toStdLogic(false); + CsrPlugin_pipelineLiberator_pcValids_1 <= pkg_toStdLogic(false); + CsrPlugin_pipelineLiberator_pcValids_2 <= pkg_toStdLogic(false); + CsrPlugin_hadException <= pkg_toStdLogic(false); + execute_CsrPlugin_wfiWake <= pkg_toStdLogic(false); + zz_2 <= pkg_toStdLogic(true); + execute_LightShifterPlugin_isActive <= pkg_toStdLogic(false); + HazardSimplePlugin_writeBackBuffer_valid <= pkg_toStdLogic(false); + execute_arbitration_isValid <= pkg_toStdLogic(false); + memory_arbitration_isValid <= pkg_toStdLogic(false); + writeBack_arbitration_isValid <= pkg_toStdLogic(false); + switch_Fetcher_l365 <= pkg_unsigned("000"); + elsif rising_edge(io_mainClk) then + if IBusSimplePlugin_fetchPc_correction = '1' then + IBusSimplePlugin_fetchPc_correctionReg <= pkg_toStdLogic(true); + end if; + if IBusSimplePlugin_fetchPc_output_fire = '1' then + IBusSimplePlugin_fetchPc_correctionReg <= pkg_toStdLogic(false); + end if; + IBusSimplePlugin_fetchPc_booted <= pkg_toStdLogic(true); + if when_Fetcher_l134 = '1' then + IBusSimplePlugin_fetchPc_inc <= pkg_toStdLogic(false); + end if; + if IBusSimplePlugin_fetchPc_output_fire_1 = '1' then + IBusSimplePlugin_fetchPc_inc <= pkg_toStdLogic(true); + end if; + if when_Fetcher_l134_1 = '1' then + IBusSimplePlugin_fetchPc_inc <= pkg_toStdLogic(false); + end if; + if when_Fetcher_l161 = '1' then + IBusSimplePlugin_fetchPc_pcReg <= IBusSimplePlugin_fetchPc_pc; + end if; + if IBusSimplePlugin_iBusRsp_flush = '1' then + zz_IBusSimplePlugin_iBusRsp_stages_0_output_ready_2 <= pkg_toStdLogic(false); + end if; + if zz_IBusSimplePlugin_iBusRsp_stages_0_output_ready = '1' then + zz_IBusSimplePlugin_iBusRsp_stages_0_output_ready_2 <= (IBusSimplePlugin_iBusRsp_stages_0_output_valid and (not pkg_toStdLogic(false))); + end if; + if IBusSimplePlugin_iBusRsp_flush = '1' then + zz_IBusSimplePlugin_iBusRsp_stages_1_output_m2sPipe_valid <= pkg_toStdLogic(false); + end if; + if IBusSimplePlugin_iBusRsp_stages_1_output_ready = '1' then + zz_IBusSimplePlugin_iBusRsp_stages_1_output_m2sPipe_valid <= (IBusSimplePlugin_iBusRsp_stages_1_output_valid and (not IBusSimplePlugin_iBusRsp_flush)); + end if; + if decode_arbitration_removeIt = '1' then + zz_IBusSimplePlugin_injector_decodeInput_valid <= pkg_toStdLogic(false); + end if; + if IBusSimplePlugin_iBusRsp_output_ready = '1' then + zz_IBusSimplePlugin_injector_decodeInput_valid <= (IBusSimplePlugin_iBusRsp_output_valid and (not IBusSimplePlugin_externalFlush)); + end if; + if IBusSimplePlugin_fetchPc_flushed = '1' then + IBusSimplePlugin_injector_nextPcCalc_valids_0 <= pkg_toStdLogic(false); + end if; + if when_Fetcher_l332 = '1' then + IBusSimplePlugin_injector_nextPcCalc_valids_0 <= pkg_toStdLogic(true); + end if; + if IBusSimplePlugin_fetchPc_flushed = '1' then + IBusSimplePlugin_injector_nextPcCalc_valids_1 <= pkg_toStdLogic(false); + end if; + if when_Fetcher_l332_1 = '1' then + IBusSimplePlugin_injector_nextPcCalc_valids_1 <= IBusSimplePlugin_injector_nextPcCalc_valids_0; + end if; + if IBusSimplePlugin_fetchPc_flushed = '1' then + IBusSimplePlugin_injector_nextPcCalc_valids_1 <= pkg_toStdLogic(false); + end if; + if IBusSimplePlugin_fetchPc_flushed = '1' then + IBusSimplePlugin_injector_nextPcCalc_valids_2 <= pkg_toStdLogic(false); + end if; + if when_Fetcher_l332_2 = '1' then + IBusSimplePlugin_injector_nextPcCalc_valids_2 <= IBusSimplePlugin_injector_nextPcCalc_valids_1; + end if; + if IBusSimplePlugin_fetchPc_flushed = '1' then + IBusSimplePlugin_injector_nextPcCalc_valids_2 <= pkg_toStdLogic(false); + end if; + if IBusSimplePlugin_fetchPc_flushed = '1' then + IBusSimplePlugin_injector_nextPcCalc_valids_3 <= pkg_toStdLogic(false); + end if; + if when_Fetcher_l332_3 = '1' then + IBusSimplePlugin_injector_nextPcCalc_valids_3 <= IBusSimplePlugin_injector_nextPcCalc_valids_2; + end if; + if IBusSimplePlugin_fetchPc_flushed = '1' then + IBusSimplePlugin_injector_nextPcCalc_valids_3 <= pkg_toStdLogic(false); + end if; + if IBusSimplePlugin_fetchPc_flushed = '1' then + IBusSimplePlugin_injector_nextPcCalc_valids_4 <= pkg_toStdLogic(false); + end if; + if when_Fetcher_l332_4 = '1' then + IBusSimplePlugin_injector_nextPcCalc_valids_4 <= IBusSimplePlugin_injector_nextPcCalc_valids_3; + end if; + if IBusSimplePlugin_fetchPc_flushed = '1' then + IBusSimplePlugin_injector_nextPcCalc_valids_4 <= pkg_toStdLogic(false); + end if; + if IBusSimplePlugin_fetchPc_flushed = '1' then + IBusSimplePlugin_injector_nextPcCalc_valids_5 <= pkg_toStdLogic(false); + end if; + if when_Fetcher_l332_5 = '1' then + IBusSimplePlugin_injector_nextPcCalc_valids_5 <= IBusSimplePlugin_injector_nextPcCalc_valids_4; + end if; + if IBusSimplePlugin_fetchPc_flushed = '1' then + IBusSimplePlugin_injector_nextPcCalc_valids_5 <= pkg_toStdLogic(false); + end if; + IBusSimplePlugin_pending_value <= IBusSimplePlugin_pending_next; + IBusSimplePlugin_rspJoin_rspBuffer_discardCounter <= (IBusSimplePlugin_rspJoin_rspBuffer_discardCounter - pkg_resize(unsigned(pkg_toStdLogicVector((IBusSimplePlugin_rspJoin_rspBuffer_c_io_pop_valid and pkg_toStdLogic(IBusSimplePlugin_rspJoin_rspBuffer_discardCounter /= pkg_unsigned("000"))))),3)); + if IBusSimplePlugin_iBusRsp_flush = '1' then + IBusSimplePlugin_rspJoin_rspBuffer_discardCounter <= IBusSimplePlugin_pending_next; + end if; + CsrPlugin_mcycle <= (CsrPlugin_mcycle + pkg_unsigned("0000000000000000000000000000000000000000000000000000000000000001")); + if writeBack_arbitration_isFiring = '1' then + CsrPlugin_minstret <= (CsrPlugin_minstret + pkg_unsigned("0000000000000000000000000000000000000000000000000000000000000001")); + end if; + CsrPlugin_interrupt_valid <= pkg_toStdLogic(false); + if when_CsrPlugin_l959 = '1' then + if when_CsrPlugin_l965 = '1' then + CsrPlugin_interrupt_valid <= pkg_toStdLogic(true); + end if; + if when_CsrPlugin_l965_1 = '1' then + CsrPlugin_interrupt_valid <= pkg_toStdLogic(true); + end if; + if when_CsrPlugin_l965_2 = '1' then + CsrPlugin_interrupt_valid <= pkg_toStdLogic(true); + end if; + end if; + if CsrPlugin_pipelineLiberator_active = '1' then + if when_CsrPlugin_l993 = '1' then + CsrPlugin_pipelineLiberator_pcValids_0 <= pkg_toStdLogic(true); + end if; + if when_CsrPlugin_l993_1 = '1' then + CsrPlugin_pipelineLiberator_pcValids_1 <= CsrPlugin_pipelineLiberator_pcValids_0; + end if; + if when_CsrPlugin_l993_2 = '1' then + CsrPlugin_pipelineLiberator_pcValids_2 <= CsrPlugin_pipelineLiberator_pcValids_1; + end if; + end if; + if when_CsrPlugin_l998 = '1' then + CsrPlugin_pipelineLiberator_pcValids_0 <= pkg_toStdLogic(false); + CsrPlugin_pipelineLiberator_pcValids_1 <= pkg_toStdLogic(false); + CsrPlugin_pipelineLiberator_pcValids_2 <= pkg_toStdLogic(false); + end if; + if CsrPlugin_interruptJump = '1' then + CsrPlugin_interrupt_valid <= pkg_toStdLogic(false); + end if; + CsrPlugin_hadException <= CsrPlugin_exception; + if when_CsrPlugin_l1032 = '1' then + case CsrPlugin_targetPrivilege is + when "11" => + CsrPlugin_mstatus_MIE <= pkg_toStdLogic(false); + CsrPlugin_mstatus_MPIE <= CsrPlugin_mstatus_MIE; + CsrPlugin_mstatus_MPP <= CsrPlugin_privilege; + when others => + end case; + end if; + if when_CsrPlugin_l1077 = '1' then + case switch_CsrPlugin_l1081 is + when "11" => + CsrPlugin_mstatus_MPP <= pkg_unsigned("00"); + CsrPlugin_mstatus_MIE <= CsrPlugin_mstatus_MPIE; + CsrPlugin_mstatus_MPIE <= pkg_toStdLogic(true); + when others => + end case; + end if; + execute_CsrPlugin_wfiWake <= (pkg_toStdLogic(pkg_cat(pkg_toStdLogicVector(zz_when_CsrPlugin_l965_2),pkg_cat(pkg_toStdLogicVector(zz_when_CsrPlugin_l965_1),pkg_toStdLogicVector(zz_when_CsrPlugin_l965))) /= pkg_stdLogicVector("000")) or CsrPlugin_thirdPartyWake); + zz_2 <= pkg_toStdLogic(false); + if when_ShiftPlugins_l169 = '1' then + if when_ShiftPlugins_l175 = '1' then + execute_LightShifterPlugin_isActive <= pkg_toStdLogic(true); + if execute_LightShifterPlugin_done = '1' then + execute_LightShifterPlugin_isActive <= pkg_toStdLogic(false); + end if; + end if; + end if; + if execute_arbitration_removeIt = '1' then + execute_LightShifterPlugin_isActive <= pkg_toStdLogic(false); + end if; + HazardSimplePlugin_writeBackBuffer_valid <= HazardSimplePlugin_writeBackWrites_valid; + if when_Pipeline_l151 = '1' then + execute_arbitration_isValid <= pkg_toStdLogic(false); + end if; + if when_Pipeline_l154 = '1' then + execute_arbitration_isValid <= decode_arbitration_isValid; + end if; + if when_Pipeline_l151_1 = '1' then + memory_arbitration_isValid <= pkg_toStdLogic(false); + end if; + if when_Pipeline_l154_1 = '1' then + memory_arbitration_isValid <= execute_arbitration_isValid; + end if; + if when_Pipeline_l151_2 = '1' then + writeBack_arbitration_isValid <= pkg_toStdLogic(false); + end if; + if when_Pipeline_l154_2 = '1' then + writeBack_arbitration_isValid <= memory_arbitration_isValid; + end if; + case switch_Fetcher_l365 is + when "000" => + if IBusSimplePlugin_injectionPort_valid = '1' then + switch_Fetcher_l365 <= pkg_unsigned("001"); + end if; + when "001" => + switch_Fetcher_l365 <= pkg_unsigned("010"); + when "010" => + switch_Fetcher_l365 <= pkg_unsigned("011"); + when "011" => + if when_Fetcher_l381 = '1' then + switch_Fetcher_l365 <= pkg_unsigned("100"); + end if; + when "100" => + switch_Fetcher_l365 <= pkg_unsigned("000"); + when others => + end case; + if execute_CsrPlugin_csr_768 = '1' then + if execute_CsrPlugin_writeEnable = '1' then + CsrPlugin_mstatus_MPIE <= pkg_extract(CsrPlugin_csrMapping_writeDataSignal,7); + CsrPlugin_mstatus_MIE <= pkg_extract(CsrPlugin_csrMapping_writeDataSignal,3); + case switch_CsrPlugin_l723 is + when "11" => + CsrPlugin_mstatus_MPP <= pkg_unsigned("11"); + when others => + end case; + end if; + end if; + if execute_CsrPlugin_csr_772 = '1' then + if execute_CsrPlugin_writeEnable = '1' then + CsrPlugin_mie_MEIE <= pkg_extract(CsrPlugin_csrMapping_writeDataSignal,11); + CsrPlugin_mie_MTIE <= pkg_extract(CsrPlugin_csrMapping_writeDataSignal,7); + CsrPlugin_mie_MSIE <= pkg_extract(CsrPlugin_csrMapping_writeDataSignal,3); + end if; + end if; + end if; + end process; + + process(io_mainClk) + begin + if rising_edge(io_mainClk) then + if IBusSimplePlugin_iBusRsp_stages_1_output_ready = '1' then + zz_IBusSimplePlugin_iBusRsp_stages_1_output_m2sPipe_payload <= IBusSimplePlugin_iBusRsp_stages_1_output_payload; + end if; + if IBusSimplePlugin_iBusRsp_output_ready = '1' then + zz_IBusSimplePlugin_injector_decodeInput_payload_pc <= IBusSimplePlugin_iBusRsp_output_payload_pc; + zz_IBusSimplePlugin_injector_decodeInput_payload_rsp_error <= IBusSimplePlugin_iBusRsp_output_payload_rsp_error; + zz_IBusSimplePlugin_injector_decodeInput_payload_rsp_inst <= IBusSimplePlugin_iBusRsp_output_payload_rsp_inst; + zz_IBusSimplePlugin_injector_decodeInput_payload_isRvc <= IBusSimplePlugin_iBusRsp_output_payload_isRvc; + end if; + if IBusSimplePlugin_injector_decodeInput_ready = '1' then + IBusSimplePlugin_injector_formal_rawInDecode <= IBusSimplePlugin_iBusRsp_output_payload_rsp_inst; + end if; + CsrPlugin_mip_MEIP <= externalInterrupt; + CsrPlugin_mip_MTIP <= timerInterrupt; + CsrPlugin_mip_MSIP <= softwareInterrupt; + if when_CsrPlugin_l959 = '1' then + if when_CsrPlugin_l965 = '1' then + CsrPlugin_interrupt_code <= pkg_unsigned("0111"); + CsrPlugin_interrupt_targetPrivilege <= pkg_unsigned("11"); + end if; + if when_CsrPlugin_l965_1 = '1' then + CsrPlugin_interrupt_code <= pkg_unsigned("0011"); + CsrPlugin_interrupt_targetPrivilege <= pkg_unsigned("11"); + end if; + if when_CsrPlugin_l965_2 = '1' then + CsrPlugin_interrupt_code <= pkg_unsigned("1011"); + CsrPlugin_interrupt_targetPrivilege <= pkg_unsigned("11"); + end if; + end if; + if when_CsrPlugin_l1032 = '1' then + case CsrPlugin_targetPrivilege is + when "11" => + CsrPlugin_mcause_interrupt <= (not CsrPlugin_hadException); + CsrPlugin_mcause_exceptionCode <= CsrPlugin_trapCause; + CsrPlugin_mepc <= decode_PC; + when others => + end case; + end if; + if when_ShiftPlugins_l169 = '1' then + if when_ShiftPlugins_l175 = '1' then + execute_LightShifterPlugin_amplitudeReg <= (execute_LightShifterPlugin_amplitude - pkg_unsigned("00001")); + end if; + end if; + HazardSimplePlugin_writeBackBuffer_payload_address <= HazardSimplePlugin_writeBackWrites_payload_address; + HazardSimplePlugin_writeBackBuffer_payload_data <= HazardSimplePlugin_writeBackWrites_payload_data; + if when_Pipeline_l124 = '1' then + decode_to_execute_PC <= zz_decode_SRC2; + end if; + if when_Pipeline_l124_1 = '1' then + execute_to_memory_PC <= execute_PC; + end if; + if when_Pipeline_l124_2 = '1' then + memory_to_writeBack_PC <= memory_PC; + end if; + if when_Pipeline_l124_3 = '1' then + decode_to_execute_INSTRUCTION <= decode_INSTRUCTION; + end if; + if when_Pipeline_l124_4 = '1' then + execute_to_memory_INSTRUCTION <= execute_INSTRUCTION; + end if; + if when_Pipeline_l124_5 = '1' then + memory_to_writeBack_INSTRUCTION <= memory_INSTRUCTION; + end if; + if when_Pipeline_l124_6 = '1' then + decode_to_execute_FORMAL_PC_NEXT <= decode_FORMAL_PC_NEXT; + end if; + if when_Pipeline_l124_7 = '1' then + execute_to_memory_FORMAL_PC_NEXT <= execute_FORMAL_PC_NEXT; + end if; + if when_Pipeline_l124_8 = '1' then + memory_to_writeBack_FORMAL_PC_NEXT <= zz_memory_to_writeBack_FORMAL_PC_NEXT; + end if; + if when_Pipeline_l124_9 = '1' then + decode_to_execute_CSR_WRITE_OPCODE <= decode_CSR_WRITE_OPCODE; + end if; + if when_Pipeline_l124_10 = '1' then + decode_to_execute_CSR_READ_OPCODE <= decode_CSR_READ_OPCODE; + end if; + if when_Pipeline_l124_11 = '1' then + decode_to_execute_SRC_USE_SUB_LESS <= decode_SRC_USE_SUB_LESS; + end if; + if when_Pipeline_l124_12 = '1' then + decode_to_execute_MEMORY_ENABLE <= decode_MEMORY_ENABLE; + end if; + if when_Pipeline_l124_13 = '1' then + execute_to_memory_MEMORY_ENABLE <= execute_MEMORY_ENABLE; + end if; + if when_Pipeline_l124_14 = '1' then + memory_to_writeBack_MEMORY_ENABLE <= memory_MEMORY_ENABLE; + end if; + if when_Pipeline_l124_15 = '1' then + decode_to_execute_REGFILE_WRITE_VALID <= decode_REGFILE_WRITE_VALID; + end if; + if when_Pipeline_l124_16 = '1' then + execute_to_memory_REGFILE_WRITE_VALID <= execute_REGFILE_WRITE_VALID; + end if; + if when_Pipeline_l124_17 = '1' then + memory_to_writeBack_REGFILE_WRITE_VALID <= memory_REGFILE_WRITE_VALID; + end if; + if when_Pipeline_l124_18 = '1' then + decode_to_execute_BYPASSABLE_EXECUTE_STAGE <= decode_BYPASSABLE_EXECUTE_STAGE; + end if; + if when_Pipeline_l124_19 = '1' then + decode_to_execute_BYPASSABLE_MEMORY_STAGE <= decode_BYPASSABLE_MEMORY_STAGE; + end if; + if when_Pipeline_l124_20 = '1' then + execute_to_memory_BYPASSABLE_MEMORY_STAGE <= execute_BYPASSABLE_MEMORY_STAGE; + end if; + if when_Pipeline_l124_21 = '1' then + decode_to_execute_MEMORY_STORE <= decode_MEMORY_STORE; + end if; + if when_Pipeline_l124_22 = '1' then + execute_to_memory_MEMORY_STORE <= execute_MEMORY_STORE; + end if; + if when_Pipeline_l124_23 = '1' then + decode_to_execute_IS_CSR <= decode_IS_CSR; + end if; + if when_Pipeline_l124_24 = '1' then + decode_to_execute_ENV_CTRL <= zz_decode_to_execute_ENV_CTRL; + end if; + if when_Pipeline_l124_25 = '1' then + execute_to_memory_ENV_CTRL <= zz_execute_to_memory_ENV_CTRL; + end if; + if when_Pipeline_l124_26 = '1' then + memory_to_writeBack_ENV_CTRL <= zz_memory_to_writeBack_ENV_CTRL; + end if; + if when_Pipeline_l124_27 = '1' then + decode_to_execute_ALU_CTRL <= zz_decode_to_execute_ALU_CTRL; + end if; + if when_Pipeline_l124_28 = '1' then + decode_to_execute_SRC_LESS_UNSIGNED <= decode_SRC_LESS_UNSIGNED; + end if; + if when_Pipeline_l124_29 = '1' then + decode_to_execute_ALU_BITWISE_CTRL <= zz_decode_to_execute_ALU_BITWISE_CTRL; + end if; + if when_Pipeline_l124_30 = '1' then + decode_to_execute_SHIFT_CTRL <= zz_decode_to_execute_SHIFT_CTRL; + end if; + if when_Pipeline_l124_31 = '1' then + decode_to_execute_BRANCH_CTRL <= zz_decode_to_execute_BRANCH_CTRL; + end if; + if when_Pipeline_l124_32 = '1' then + decode_to_execute_RS1 <= zz_decode_SRC1; + end if; + if when_Pipeline_l124_33 = '1' then + decode_to_execute_RS2 <= zz_decode_SRC2_1; + end if; + if when_Pipeline_l124_34 = '1' then + decode_to_execute_SRC2_FORCE_ZERO <= decode_SRC2_FORCE_ZERO; + end if; + if when_Pipeline_l124_35 = '1' then + decode_to_execute_SRC1 <= decode_SRC1; + end if; + if when_Pipeline_l124_36 = '1' then + decode_to_execute_SRC2 <= decode_SRC2; + end if; + if when_Pipeline_l124_37 = '1' then + decode_to_execute_DO_EBREAK <= decode_DO_EBREAK; + end if; + if when_Pipeline_l124_38 = '1' then + execute_to_memory_MEMORY_ADDRESS_LOW <= execute_MEMORY_ADDRESS_LOW; + end if; + if when_Pipeline_l124_39 = '1' then + memory_to_writeBack_MEMORY_ADDRESS_LOW <= memory_MEMORY_ADDRESS_LOW; + end if; + if when_Pipeline_l124_40 = '1' then + execute_to_memory_REGFILE_WRITE_DATA <= zz_execute_to_memory_REGFILE_WRITE_DATA; + end if; + if when_Pipeline_l124_41 = '1' then + memory_to_writeBack_REGFILE_WRITE_DATA <= memory_REGFILE_WRITE_DATA; + end if; + if when_Pipeline_l124_42 = '1' then + execute_to_memory_BRANCH_DO <= execute_BRANCH_DO; + end if; + if when_Pipeline_l124_43 = '1' then + execute_to_memory_BRANCH_CALC <= execute_BRANCH_CALC; + end if; + if when_Pipeline_l124_44 = '1' then + memory_to_writeBack_MEMORY_READ_DATA <= memory_MEMORY_READ_DATA; + end if; + if when_Fetcher_l401 = '1' then + zz_IBusSimplePlugin_injector_decodeInput_payload_rsp_inst <= IBusSimplePlugin_injectionPort_payload; + end if; + if when_CsrPlugin_l1277 = '1' then + execute_CsrPlugin_csr_768 <= pkg_toStdLogic(pkg_extract(decode_INSTRUCTION,31,20) = pkg_stdLogicVector("001100000000")); + end if; + if when_CsrPlugin_l1277_1 = '1' then + execute_CsrPlugin_csr_836 <= pkg_toStdLogic(pkg_extract(decode_INSTRUCTION,31,20) = pkg_stdLogicVector("001101000100")); + end if; + if when_CsrPlugin_l1277_2 = '1' then + execute_CsrPlugin_csr_772 <= pkg_toStdLogic(pkg_extract(decode_INSTRUCTION,31,20) = pkg_stdLogicVector("001100000100")); + end if; + if when_CsrPlugin_l1277_3 = '1' then + execute_CsrPlugin_csr_834 <= pkg_toStdLogic(pkg_extract(decode_INSTRUCTION,31,20) = pkg_stdLogicVector("001101000010")); + end if; + if execute_CsrPlugin_csr_836 = '1' then + if execute_CsrPlugin_writeEnable = '1' then + CsrPlugin_mip_MSIP <= pkg_extract(CsrPlugin_csrMapping_writeDataSignal,3); + end if; + end if; + end if; + end process; + + process(io_mainClk) + begin + if rising_edge(io_mainClk) then + DebugPlugin_firstCycle <= pkg_toStdLogic(false); + if debug_bus_cmd_ready_read_buffer = '1' then + DebugPlugin_firstCycle <= pkg_toStdLogic(true); + end if; + DebugPlugin_secondCycle <= DebugPlugin_firstCycle; + DebugPlugin_isPipBusy <= (pkg_toStdLogic(pkg_cat(pkg_toStdLogicVector(writeBack_arbitration_isValid),pkg_cat(pkg_toStdLogicVector(memory_arbitration_isValid),pkg_cat(pkg_toStdLogicVector(execute_arbitration_isValid),pkg_toStdLogicVector(decode_arbitration_isValid)))) /= pkg_stdLogicVector("0000")) or IBusSimplePlugin_incomingInstruction); + if writeBack_arbitration_isValid = '1' then + DebugPlugin_busReadDataReg <= zz_lastStageRegFileWrite_payload_data; + end if; + zz_when_DebugPlugin_l244 <= pkg_extract(debug_bus_cmd_payload_address,2); + if when_DebugPlugin_l295 = '1' then + DebugPlugin_busReadDataReg <= std_logic_vector(execute_PC); + end if; + DebugPlugin_resetIt_regNext <= DebugPlugin_resetIt; + end if; + end process; + + process(io_mainClk, resetCtrl_mainClkReset) + begin + if resetCtrl_mainClkReset = '1' then + DebugPlugin_resetIt <= pkg_toStdLogic(false); + DebugPlugin_haltIt <= pkg_toStdLogic(false); + DebugPlugin_stepIt <= pkg_toStdLogic(false); + DebugPlugin_godmode <= pkg_toStdLogic(false); + DebugPlugin_haltedByBreak <= pkg_toStdLogic(false); + DebugPlugin_debugUsed <= pkg_toStdLogic(false); + DebugPlugin_disableEbreak <= pkg_toStdLogic(false); + elsif rising_edge(io_mainClk) then + if when_DebugPlugin_l225 = '1' then + DebugPlugin_godmode <= pkg_toStdLogic(true); + end if; + if debug_bus_cmd_valid = '1' then + DebugPlugin_debugUsed <= pkg_toStdLogic(true); + end if; + if debug_bus_cmd_valid = '1' then + case switch_DebugPlugin_l267 is + when "000000" => + if debug_bus_cmd_payload_wr = '1' then + DebugPlugin_stepIt <= pkg_extract(debug_bus_cmd_payload_data,4); + if when_DebugPlugin_l271 = '1' then + DebugPlugin_resetIt <= pkg_toStdLogic(true); + end if; + if when_DebugPlugin_l271_1 = '1' then + DebugPlugin_resetIt <= pkg_toStdLogic(false); + end if; + if when_DebugPlugin_l272 = '1' then + DebugPlugin_haltIt <= pkg_toStdLogic(true); + end if; + if when_DebugPlugin_l272_1 = '1' then + DebugPlugin_haltIt <= pkg_toStdLogic(false); + end if; + if when_DebugPlugin_l273 = '1' then + DebugPlugin_haltedByBreak <= pkg_toStdLogic(false); + end if; + if when_DebugPlugin_l274 = '1' then + DebugPlugin_godmode <= pkg_toStdLogic(false); + end if; + if when_DebugPlugin_l275 = '1' then + DebugPlugin_disableEbreak <= pkg_toStdLogic(true); + end if; + if when_DebugPlugin_l275_1 = '1' then + DebugPlugin_disableEbreak <= pkg_toStdLogic(false); + end if; + end if; + when others => + end case; + end if; + if when_DebugPlugin_l295 = '1' then + if when_DebugPlugin_l298 = '1' then + DebugPlugin_haltIt <= pkg_toStdLogic(true); + DebugPlugin_haltedByBreak <= pkg_toStdLogic(true); + end if; + end if; + if when_DebugPlugin_l311 = '1' then + if decode_arbitration_isValid = '1' then + DebugPlugin_haltIt <= pkg_toStdLogic(true); + end if; + end if; + end if; + end process; + +end arch; + +library ieee; +use ieee.std_logic_1164.all; +use ieee.numeric_std.all; + +library work; +use work.pkg_scala2hdl.all; +use work.all; +use work.pkg_enum.all; + + +entity JtagBridge is + port( + io_jtag_tms : in std_logic; + io_jtag_tdi : in std_logic; + io_jtag_tdo : out std_logic; + io_jtag_tck : in std_logic; + io_remote_cmd_valid : out std_logic; + io_remote_cmd_ready : in std_logic; + io_remote_cmd_payload_last : out std_logic; + io_remote_cmd_payload_fragment : out std_logic_vector(0 downto 0); + io_remote_rsp_valid : in std_logic; + io_remote_rsp_ready : out std_logic; + io_remote_rsp_payload_error : in std_logic; + io_remote_rsp_payload_data : in std_logic_vector(31 downto 0); + io_mainClk : in std_logic; + resetCtrl_mainClkReset : in std_logic + ); +end JtagBridge; + +architecture arch of JtagBridge is + signal io_remote_cmd_valid_read_buffer : std_logic; + signal io_remote_rsp_ready_read_buffer : std_logic; + signal flowCCByToggle_1_io_output_valid : std_logic; + signal flowCCByToggle_1_io_output_payload_last : std_logic; + signal flowCCByToggle_1_io_output_payload_fragment : std_logic_vector(0 downto 0); + attribute async_reg : string; + + signal system_cmd_valid : std_logic; + signal system_cmd_payload_last : std_logic; + signal system_cmd_payload_fragment : std_logic_vector(0 downto 0); + signal system_cmd_toStream_valid : std_logic; + signal system_cmd_toStream_ready : std_logic; + signal system_cmd_toStream_payload_last : std_logic; + signal system_cmd_toStream_payload_fragment : std_logic_vector(0 downto 0); + signal system_rsp_valid : std_logic; + attribute async_reg of system_rsp_valid : signal is "true"; + signal system_rsp_payload_error : std_logic; + attribute async_reg of system_rsp_payload_error : signal is "true"; + signal system_rsp_payload_data : std_logic_vector(31 downto 0); + attribute async_reg of system_rsp_payload_data : signal is "true"; + signal io_remote_rsp_fire : std_logic; + signal jtag_tap_fsm_stateNext : JtagState; + signal jtag_tap_fsm_state : JtagState := pkg_enum.RESET; + signal zz_jtag_tap_fsm_stateNext : JtagState; + signal zz_jtag_tap_fsm_stateNext_1 : JtagState; + signal zz_jtag_tap_fsm_stateNext_2 : JtagState; + signal zz_jtag_tap_fsm_stateNext_3 : JtagState; + signal zz_jtag_tap_fsm_stateNext_4 : JtagState; + signal zz_jtag_tap_fsm_stateNext_5 : JtagState; + signal zz_jtag_tap_fsm_stateNext_6 : JtagState; + signal zz_jtag_tap_fsm_stateNext_7 : JtagState; + signal zz_jtag_tap_fsm_stateNext_8 : JtagState; + signal zz_jtag_tap_fsm_stateNext_9 : JtagState; + signal zz_jtag_tap_fsm_stateNext_10 : JtagState; + signal zz_jtag_tap_fsm_stateNext_11 : JtagState; + signal zz_jtag_tap_fsm_stateNext_12 : JtagState; + signal zz_jtag_tap_fsm_stateNext_13 : JtagState; + signal zz_jtag_tap_fsm_stateNext_14 : JtagState; + signal zz_jtag_tap_fsm_stateNext_15 : JtagState; + signal zz_jtag_tap_fsm_stateNext_16 : JtagState; + signal jtag_tap_instruction : std_logic_vector(3 downto 0); + signal jtag_tap_instructionShift : std_logic_vector(3 downto 0); + signal jtag_tap_bypass : std_logic; + signal jtag_tap_tdoUnbufferd : std_logic; + signal jtag_tap_tdoDr : std_logic; + signal jtag_tap_tdoIr : std_logic; + signal jtag_tap_isBypass : std_logic; + signal jtag_tap_tdoUnbufferd_regNext : std_logic; + signal jtag_idcodeArea_ctrl_tdi : std_logic; + signal jtag_idcodeArea_ctrl_enable : std_logic; + signal jtag_idcodeArea_ctrl_capture : std_logic; + signal jtag_idcodeArea_ctrl_shift : std_logic; + signal jtag_idcodeArea_ctrl_update : std_logic; + signal jtag_idcodeArea_ctrl_reset : std_logic; + signal jtag_idcodeArea_ctrl_tdo : std_logic; + signal jtag_idcodeArea_shifter : std_logic_vector(31 downto 0); + signal when_JtagTap_l120 : std_logic; + signal jtag_writeArea_ctrl_tdi : std_logic; + signal jtag_writeArea_ctrl_enable : std_logic; + signal jtag_writeArea_ctrl_capture : std_logic; + signal jtag_writeArea_ctrl_shift : std_logic; + signal jtag_writeArea_ctrl_update : std_logic; + signal jtag_writeArea_ctrl_reset : std_logic; + signal jtag_writeArea_ctrl_tdo : std_logic; + signal jtag_writeArea_source_valid : std_logic; + signal jtag_writeArea_source_payload_last : std_logic; + signal jtag_writeArea_source_payload_fragment : std_logic_vector(0 downto 0); + signal jtag_writeArea_valid : std_logic; + signal jtag_writeArea_data : std_logic; + signal jtag_readArea_ctrl_tdi : std_logic; + signal jtag_readArea_ctrl_enable : std_logic; + signal jtag_readArea_ctrl_capture : std_logic; + signal jtag_readArea_ctrl_shift : std_logic; + signal jtag_readArea_ctrl_update : std_logic; + signal jtag_readArea_ctrl_reset : std_logic; + signal jtag_readArea_ctrl_tdo : std_logic; + signal jtag_readArea_full_shifter : std_logic_vector(33 downto 0); +begin + io_remote_cmd_valid <= io_remote_cmd_valid_read_buffer; + io_remote_rsp_ready <= io_remote_rsp_ready_read_buffer; + flowCCByToggle_1 : entity work.FlowCCByToggle + port map ( + io_input_valid => jtag_writeArea_source_valid, + io_input_payload_last => jtag_writeArea_source_payload_last, + io_input_payload_fragment => jtag_writeArea_source_payload_fragment, + io_output_valid => flowCCByToggle_1_io_output_valid, + io_output_payload_last => flowCCByToggle_1_io_output_payload_last, + io_output_payload_fragment => flowCCByToggle_1_io_output_payload_fragment, + io_jtag_tck => io_jtag_tck, + io_mainClk => io_mainClk, + resetCtrl_mainClkReset => resetCtrl_mainClkReset + ); + system_cmd_toStream_valid <= system_cmd_valid; + system_cmd_toStream_payload_last <= system_cmd_payload_last; + system_cmd_toStream_payload_fragment <= system_cmd_payload_fragment; + io_remote_cmd_valid_read_buffer <= system_cmd_toStream_valid; + system_cmd_toStream_ready <= io_remote_cmd_ready; + io_remote_cmd_payload_last <= system_cmd_toStream_payload_last; + io_remote_cmd_payload_fragment <= system_cmd_toStream_payload_fragment; + io_remote_rsp_fire <= (io_remote_rsp_valid and io_remote_rsp_ready_read_buffer); + io_remote_rsp_ready_read_buffer <= pkg_toStdLogic(true); + zz_jtag_tap_fsm_stateNext <= pkg_mux(io_jtag_tms,pkg_enum.RESET,pkg_enum.IDLE); + zz_jtag_tap_fsm_stateNext_1 <= pkg_mux(io_jtag_tms,pkg_enum.DR_SELECT,pkg_enum.IDLE); + zz_jtag_tap_fsm_stateNext_2 <= pkg_mux(io_jtag_tms,pkg_enum.RESET,pkg_enum.IR_CAPTURE); + zz_jtag_tap_fsm_stateNext_3 <= pkg_mux(io_jtag_tms,pkg_enum.IR_EXIT1,pkg_enum.IR_SHIFT); + zz_jtag_tap_fsm_stateNext_4 <= pkg_mux(io_jtag_tms,pkg_enum.IR_EXIT1,pkg_enum.IR_SHIFT); + zz_jtag_tap_fsm_stateNext_5 <= pkg_mux(io_jtag_tms,pkg_enum.IR_UPDATE,pkg_enum.IR_PAUSE); + zz_jtag_tap_fsm_stateNext_6 <= pkg_mux(io_jtag_tms,pkg_enum.IR_EXIT2,pkg_enum.IR_PAUSE); + zz_jtag_tap_fsm_stateNext_7 <= pkg_mux(io_jtag_tms,pkg_enum.IR_UPDATE,pkg_enum.IR_SHIFT); + zz_jtag_tap_fsm_stateNext_8 <= pkg_mux(io_jtag_tms,pkg_enum.DR_SELECT,pkg_enum.IDLE); + zz_jtag_tap_fsm_stateNext_9 <= pkg_mux(io_jtag_tms,pkg_enum.IR_SELECT,pkg_enum.DR_CAPTURE); + zz_jtag_tap_fsm_stateNext_10 <= pkg_mux(io_jtag_tms,pkg_enum.DR_EXIT1,pkg_enum.DR_SHIFT); + zz_jtag_tap_fsm_stateNext_11 <= pkg_mux(io_jtag_tms,pkg_enum.DR_EXIT1,pkg_enum.DR_SHIFT); + zz_jtag_tap_fsm_stateNext_12 <= pkg_mux(io_jtag_tms,pkg_enum.DR_UPDATE,pkg_enum.DR_PAUSE); + zz_jtag_tap_fsm_stateNext_13 <= pkg_mux(io_jtag_tms,pkg_enum.DR_EXIT2,pkg_enum.DR_PAUSE); + zz_jtag_tap_fsm_stateNext_14 <= pkg_mux(io_jtag_tms,pkg_enum.DR_UPDATE,pkg_enum.DR_SHIFT); + zz_jtag_tap_fsm_stateNext_15 <= pkg_mux(io_jtag_tms,pkg_enum.DR_SELECT,pkg_enum.IDLE); + process(jtag_tap_fsm_state,zz_jtag_tap_fsm_stateNext_1,zz_jtag_tap_fsm_stateNext_2,zz_jtag_tap_fsm_stateNext_3,zz_jtag_tap_fsm_stateNext_4,zz_jtag_tap_fsm_stateNext_5,zz_jtag_tap_fsm_stateNext_6,zz_jtag_tap_fsm_stateNext_7,zz_jtag_tap_fsm_stateNext_8,zz_jtag_tap_fsm_stateNext_9,zz_jtag_tap_fsm_stateNext_10,zz_jtag_tap_fsm_stateNext_11,zz_jtag_tap_fsm_stateNext_12,zz_jtag_tap_fsm_stateNext_13,zz_jtag_tap_fsm_stateNext_14,zz_jtag_tap_fsm_stateNext_15,zz_jtag_tap_fsm_stateNext) + begin + case jtag_tap_fsm_state is + when pkg_enum.IDLE => + zz_jtag_tap_fsm_stateNext_16 <= zz_jtag_tap_fsm_stateNext_1; + when pkg_enum.IR_SELECT => + zz_jtag_tap_fsm_stateNext_16 <= zz_jtag_tap_fsm_stateNext_2; + when pkg_enum.IR_CAPTURE => + zz_jtag_tap_fsm_stateNext_16 <= zz_jtag_tap_fsm_stateNext_3; + when pkg_enum.IR_SHIFT => + zz_jtag_tap_fsm_stateNext_16 <= zz_jtag_tap_fsm_stateNext_4; + when pkg_enum.IR_EXIT1 => + zz_jtag_tap_fsm_stateNext_16 <= zz_jtag_tap_fsm_stateNext_5; + when pkg_enum.IR_PAUSE => + zz_jtag_tap_fsm_stateNext_16 <= zz_jtag_tap_fsm_stateNext_6; + when pkg_enum.IR_EXIT2 => + zz_jtag_tap_fsm_stateNext_16 <= zz_jtag_tap_fsm_stateNext_7; + when pkg_enum.IR_UPDATE => + zz_jtag_tap_fsm_stateNext_16 <= zz_jtag_tap_fsm_stateNext_8; + when pkg_enum.DR_SELECT => + zz_jtag_tap_fsm_stateNext_16 <= zz_jtag_tap_fsm_stateNext_9; + when pkg_enum.DR_CAPTURE => + zz_jtag_tap_fsm_stateNext_16 <= zz_jtag_tap_fsm_stateNext_10; + when pkg_enum.DR_SHIFT => + zz_jtag_tap_fsm_stateNext_16 <= zz_jtag_tap_fsm_stateNext_11; + when pkg_enum.DR_EXIT1 => + zz_jtag_tap_fsm_stateNext_16 <= zz_jtag_tap_fsm_stateNext_12; + when pkg_enum.DR_PAUSE => + zz_jtag_tap_fsm_stateNext_16 <= zz_jtag_tap_fsm_stateNext_13; + when pkg_enum.DR_EXIT2 => + zz_jtag_tap_fsm_stateNext_16 <= zz_jtag_tap_fsm_stateNext_14; + when pkg_enum.DR_UPDATE => + zz_jtag_tap_fsm_stateNext_16 <= zz_jtag_tap_fsm_stateNext_15; + when others => + zz_jtag_tap_fsm_stateNext_16 <= zz_jtag_tap_fsm_stateNext; + end case; + end process; + + jtag_tap_fsm_stateNext <= zz_jtag_tap_fsm_stateNext_16; + process(jtag_tap_bypass,jtag_tap_fsm_state,jtag_tap_tdoIr,jtag_tap_isBypass,jtag_tap_tdoDr) + begin + jtag_tap_tdoUnbufferd <= jtag_tap_bypass; + case jtag_tap_fsm_state is + when pkg_enum.IR_SHIFT => + jtag_tap_tdoUnbufferd <= jtag_tap_tdoIr; + when pkg_enum.DR_SHIFT => + if jtag_tap_isBypass = '1' then + jtag_tap_tdoUnbufferd <= jtag_tap_bypass; + else + jtag_tap_tdoUnbufferd <= jtag_tap_tdoDr; + end if; + when others => + end case; + end process; + + process(jtag_idcodeArea_ctrl_enable,jtag_idcodeArea_ctrl_tdo,jtag_writeArea_ctrl_enable,jtag_writeArea_ctrl_tdo,jtag_readArea_ctrl_enable,jtag_readArea_ctrl_tdo) + begin + jtag_tap_tdoDr <= pkg_toStdLogic(false); + if jtag_idcodeArea_ctrl_enable = '1' then + jtag_tap_tdoDr <= jtag_idcodeArea_ctrl_tdo; + end if; + if jtag_writeArea_ctrl_enable = '1' then + jtag_tap_tdoDr <= jtag_writeArea_ctrl_tdo; + end if; + if jtag_readArea_ctrl_enable = '1' then + jtag_tap_tdoDr <= jtag_readArea_ctrl_tdo; + end if; + end process; + + jtag_tap_tdoIr <= pkg_extract(jtag_tap_instructionShift,0); + jtag_tap_isBypass <= pkg_toStdLogic(signed(jtag_tap_instruction) = pkg_signed("1111")); + io_jtag_tdo <= jtag_tap_tdoUnbufferd_regNext; + jtag_idcodeArea_ctrl_tdo <= pkg_extract(jtag_idcodeArea_shifter,0); + jtag_idcodeArea_ctrl_tdi <= io_jtag_tdi; + jtag_idcodeArea_ctrl_enable <= pkg_toStdLogic(jtag_tap_instruction = pkg_stdLogicVector("0001")); + jtag_idcodeArea_ctrl_capture <= pkg_toStdLogic(jtag_tap_fsm_state = pkg_enum.DR_CAPTURE); + jtag_idcodeArea_ctrl_shift <= pkg_toStdLogic(jtag_tap_fsm_state = pkg_enum.DR_SHIFT); + jtag_idcodeArea_ctrl_update <= pkg_toStdLogic(jtag_tap_fsm_state = pkg_enum.DR_UPDATE); + jtag_idcodeArea_ctrl_reset <= pkg_toStdLogic(jtag_tap_fsm_state = pkg_enum.RESET); + when_JtagTap_l120 <= pkg_toStdLogic(jtag_tap_fsm_state = pkg_enum.RESET); + jtag_writeArea_source_valid <= jtag_writeArea_valid; + jtag_writeArea_source_payload_last <= (not (jtag_writeArea_ctrl_enable and jtag_writeArea_ctrl_shift)); + jtag_writeArea_source_payload_fragment(0) <= jtag_writeArea_data; + system_cmd_valid <= flowCCByToggle_1_io_output_valid; + system_cmd_payload_last <= flowCCByToggle_1_io_output_payload_last; + system_cmd_payload_fragment <= flowCCByToggle_1_io_output_payload_fragment; + jtag_writeArea_ctrl_tdo <= pkg_toStdLogic(false); + jtag_writeArea_ctrl_tdi <= io_jtag_tdi; + jtag_writeArea_ctrl_enable <= pkg_toStdLogic(jtag_tap_instruction = pkg_stdLogicVector("0010")); + jtag_writeArea_ctrl_capture <= pkg_toStdLogic(jtag_tap_fsm_state = pkg_enum.DR_CAPTURE); + jtag_writeArea_ctrl_shift <= pkg_toStdLogic(jtag_tap_fsm_state = pkg_enum.DR_SHIFT); + jtag_writeArea_ctrl_update <= pkg_toStdLogic(jtag_tap_fsm_state = pkg_enum.DR_UPDATE); + jtag_writeArea_ctrl_reset <= pkg_toStdLogic(jtag_tap_fsm_state = pkg_enum.RESET); + jtag_readArea_ctrl_tdo <= pkg_extract(jtag_readArea_full_shifter,0); + jtag_readArea_ctrl_tdi <= io_jtag_tdi; + jtag_readArea_ctrl_enable <= pkg_toStdLogic(jtag_tap_instruction = pkg_stdLogicVector("0011")); + jtag_readArea_ctrl_capture <= pkg_toStdLogic(jtag_tap_fsm_state = pkg_enum.DR_CAPTURE); + jtag_readArea_ctrl_shift <= pkg_toStdLogic(jtag_tap_fsm_state = pkg_enum.DR_SHIFT); + jtag_readArea_ctrl_update <= pkg_toStdLogic(jtag_tap_fsm_state = pkg_enum.DR_UPDATE); + jtag_readArea_ctrl_reset <= pkg_toStdLogic(jtag_tap_fsm_state = pkg_enum.RESET); + process(io_mainClk) + begin + if rising_edge(io_mainClk) then + if io_remote_cmd_valid_read_buffer = '1' then + system_rsp_valid <= pkg_toStdLogic(false); + end if; + if io_remote_rsp_fire = '1' then + system_rsp_valid <= pkg_toStdLogic(true); + system_rsp_payload_error <= io_remote_rsp_payload_error; + system_rsp_payload_data <= io_remote_rsp_payload_data; + end if; + end if; + end process; + + process(io_jtag_tck) + begin + if rising_edge(io_jtag_tck) then + jtag_tap_fsm_state <= jtag_tap_fsm_stateNext; + jtag_tap_bypass <= io_jtag_tdi; + case jtag_tap_fsm_state is + when pkg_enum.IR_CAPTURE => + jtag_tap_instructionShift <= pkg_resize(pkg_stdLogicVector("01"),4); + when pkg_enum.IR_SHIFT => + jtag_tap_instructionShift <= pkg_shiftRight(pkg_cat(pkg_toStdLogicVector(io_jtag_tdi),jtag_tap_instructionShift),1); + when pkg_enum.IR_UPDATE => + jtag_tap_instruction <= jtag_tap_instructionShift; + when pkg_enum.DR_SHIFT => + jtag_tap_instructionShift <= pkg_shiftRight(pkg_cat(pkg_toStdLogicVector(io_jtag_tdi),jtag_tap_instructionShift),1); + when others => + end case; + if jtag_idcodeArea_ctrl_enable = '1' then + if jtag_idcodeArea_ctrl_shift = '1' then + jtag_idcodeArea_shifter <= pkg_shiftRight(pkg_cat(pkg_toStdLogicVector(jtag_idcodeArea_ctrl_tdi),jtag_idcodeArea_shifter),1); + end if; + end if; + if jtag_idcodeArea_ctrl_capture = '1' then + jtag_idcodeArea_shifter <= pkg_stdLogicVector("00010000000000000001111111111111"); + end if; + if when_JtagTap_l120 = '1' then + jtag_tap_instruction <= pkg_stdLogicVector("0001"); + end if; + jtag_writeArea_valid <= (jtag_writeArea_ctrl_enable and jtag_writeArea_ctrl_shift); + jtag_writeArea_data <= jtag_writeArea_ctrl_tdi; + if jtag_readArea_ctrl_enable = '1' then + if jtag_readArea_ctrl_capture = '1' then + jtag_readArea_full_shifter <= pkg_cat(pkg_cat(system_rsp_payload_data,pkg_toStdLogicVector(system_rsp_payload_error)),pkg_toStdLogicVector(system_rsp_valid)); + end if; + if jtag_readArea_ctrl_shift = '1' then + jtag_readArea_full_shifter <= pkg_shiftRight(pkg_cat(pkg_toStdLogicVector(jtag_readArea_ctrl_tdi),jtag_readArea_full_shifter),1); + end if; + end if; + end if; + end process; + + process(io_jtag_tck) + begin + if falling_edge(io_jtag_tck) then + jtag_tap_tdoUnbufferd_regNext <= jtag_tap_tdoUnbufferd; + end if; + end process; + +end arch; + +library ieee; +use ieee.std_logic_1164.all; +use ieee.numeric_std.all; + +library work; +use work.pkg_scala2hdl.all; +use work.all; +use work.pkg_enum.all; + + +entity SystemDebugger is + port( + io_remote_cmd_valid : in std_logic; + io_remote_cmd_ready : out std_logic; + io_remote_cmd_payload_last : in std_logic; + io_remote_cmd_payload_fragment : in std_logic_vector(0 downto 0); + io_remote_rsp_valid : out std_logic; + io_remote_rsp_ready : in std_logic; + io_remote_rsp_payload_error : out std_logic; + io_remote_rsp_payload_data : out std_logic_vector(31 downto 0); + io_mem_cmd_valid : out std_logic; + io_mem_cmd_ready : in std_logic; + io_mem_cmd_payload_address : out unsigned(31 downto 0); + io_mem_cmd_payload_data : out std_logic_vector(31 downto 0); + io_mem_cmd_payload_wr : out std_logic; + io_mem_cmd_payload_size : out unsigned(1 downto 0); + io_mem_rsp_valid : in std_logic; + io_mem_rsp_payload : in std_logic_vector(31 downto 0); + io_mainClk : in std_logic; + resetCtrl_mainClkReset : in std_logic + ); +end SystemDebugger; + +architecture arch of SystemDebugger is + signal io_mem_cmd_valid_read_buffer : std_logic; + + signal dispatcher_dataShifter : std_logic_vector(66 downto 0); + signal dispatcher_dataLoaded : std_logic; + signal dispatcher_headerShifter : std_logic_vector(7 downto 0); + signal dispatcher_header : std_logic_vector(7 downto 0); + signal dispatcher_headerLoaded : std_logic; + signal dispatcher_counter : unsigned(2 downto 0); + signal when_Fragment_l346 : std_logic; + signal when_Fragment_l349 : std_logic; + signal zz_io_mem_cmd_payload_address : std_logic_vector(66 downto 0); + signal io_mem_cmd_isStall : std_logic; + signal when_Fragment_l372 : std_logic; +begin + io_mem_cmd_valid <= io_mem_cmd_valid_read_buffer; + dispatcher_header <= pkg_extract(dispatcher_headerShifter,7,0); + when_Fragment_l346 <= pkg_toStdLogic(dispatcher_headerLoaded = pkg_toStdLogic(false)); + when_Fragment_l349 <= pkg_toStdLogic(dispatcher_counter = pkg_unsigned("111")); + io_remote_cmd_ready <= (not dispatcher_dataLoaded); + zz_io_mem_cmd_payload_address <= pkg_extract(dispatcher_dataShifter,66,0); + io_mem_cmd_payload_address <= unsigned(pkg_extract(zz_io_mem_cmd_payload_address,31,0)); + io_mem_cmd_payload_data <= pkg_extract(zz_io_mem_cmd_payload_address,63,32); + io_mem_cmd_payload_wr <= pkg_extract(zz_io_mem_cmd_payload_address,64); + io_mem_cmd_payload_size <= unsigned(pkg_extract(zz_io_mem_cmd_payload_address,66,65)); + io_mem_cmd_valid_read_buffer <= (dispatcher_dataLoaded and pkg_toStdLogic(dispatcher_header = pkg_stdLogicVector("00000000"))); + io_mem_cmd_isStall <= (io_mem_cmd_valid_read_buffer and (not io_mem_cmd_ready)); + when_Fragment_l372 <= ((dispatcher_headerLoaded and dispatcher_dataLoaded) and (not io_mem_cmd_isStall)); + io_remote_rsp_valid <= io_mem_rsp_valid; + io_remote_rsp_payload_error <= pkg_toStdLogic(false); + io_remote_rsp_payload_data <= io_mem_rsp_payload; + process(io_mainClk, resetCtrl_mainClkReset) + begin + if resetCtrl_mainClkReset = '1' then + dispatcher_dataLoaded <= pkg_toStdLogic(false); + dispatcher_headerLoaded <= pkg_toStdLogic(false); + dispatcher_counter <= pkg_unsigned("000"); + elsif rising_edge(io_mainClk) then + if io_remote_cmd_valid = '1' then + if when_Fragment_l346 = '1' then + dispatcher_counter <= (dispatcher_counter + pkg_unsigned("001")); + if when_Fragment_l349 = '1' then + dispatcher_headerLoaded <= pkg_toStdLogic(true); + end if; + end if; + if io_remote_cmd_payload_last = '1' then + dispatcher_headerLoaded <= pkg_toStdLogic(true); + dispatcher_dataLoaded <= pkg_toStdLogic(true); + dispatcher_counter <= pkg_unsigned("000"); + end if; + end if; + if when_Fragment_l372 = '1' then + dispatcher_headerLoaded <= pkg_toStdLogic(false); + dispatcher_dataLoaded <= pkg_toStdLogic(false); + end if; + end if; + end process; + + process(io_mainClk) + begin + if rising_edge(io_mainClk) then + if io_remote_cmd_valid = '1' then + if when_Fragment_l346 = '1' then + dispatcher_headerShifter <= pkg_shiftRight(pkg_cat(io_remote_cmd_payload_fragment,dispatcher_headerShifter),1); + else + dispatcher_dataShifter <= pkg_shiftRight(pkg_cat(io_remote_cmd_payload_fragment,dispatcher_dataShifter),1); + end if; + end if; + end if; + end process; + +end arch; + + +library ieee; +use ieee.std_logic_1164.all; +use ieee.numeric_std.all; + +library work; +use work.pkg_scala2hdl.all; +use work.all; +use work.pkg_enum.all; + + +entity PipelinedMemoryBusToApbBridge is + port( + io_pipelinedMemoryBus_cmd_valid : in std_logic; + io_pipelinedMemoryBus_cmd_ready : out std_logic; + io_pipelinedMemoryBus_cmd_payload_write : in std_logic; + io_pipelinedMemoryBus_cmd_payload_address : in unsigned(31 downto 0); + io_pipelinedMemoryBus_cmd_payload_data : in std_logic_vector(31 downto 0); + io_pipelinedMemoryBus_cmd_payload_mask : in std_logic_vector(3 downto 0); + io_pipelinedMemoryBus_rsp_valid : out std_logic; + io_pipelinedMemoryBus_rsp_payload_data : out std_logic_vector(31 downto 0); + io_apb_PADDR : out unsigned(19 downto 0); + io_apb_PSEL : out std_logic_vector(0 downto 0); + io_apb_PENABLE : out std_logic; + io_apb_PREADY : in std_logic; + io_apb_PWRITE : out std_logic; + io_apb_PWDATA : out std_logic_vector(31 downto 0); + io_apb_PRDATA : in std_logic_vector(31 downto 0); + io_apb_PSLVERROR : in std_logic; + io_mainClk : in std_logic; + resetCtrl_systemReset : in std_logic + ); +end PipelinedMemoryBusToApbBridge; + +architecture arch of PipelinedMemoryBusToApbBridge is + signal io_pipelinedMemoryBus_cmd_ready_read_buffer : std_logic; + + signal pipelinedMemoryBusStage_cmd_valid : std_logic; + signal pipelinedMemoryBusStage_cmd_ready : std_logic; + signal pipelinedMemoryBusStage_cmd_payload_write : std_logic; + signal pipelinedMemoryBusStage_cmd_payload_address : unsigned(31 downto 0); + signal pipelinedMemoryBusStage_cmd_payload_data : std_logic_vector(31 downto 0); + signal pipelinedMemoryBusStage_cmd_payload_mask : std_logic_vector(3 downto 0); + signal pipelinedMemoryBusStage_rsp_valid : std_logic; + signal pipelinedMemoryBusStage_rsp_payload_data : std_logic_vector(31 downto 0); + signal io_pipelinedMemoryBus_cmd_halfPipe_valid : std_logic; + signal io_pipelinedMemoryBus_cmd_halfPipe_ready : std_logic; + signal io_pipelinedMemoryBus_cmd_halfPipe_payload_write : std_logic; + signal io_pipelinedMemoryBus_cmd_halfPipe_payload_address : unsigned(31 downto 0); + signal io_pipelinedMemoryBus_cmd_halfPipe_payload_data : std_logic_vector(31 downto 0); + signal io_pipelinedMemoryBus_cmd_halfPipe_payload_mask : std_logic_vector(3 downto 0); + signal io_pipelinedMemoryBus_cmd_rValid : std_logic; + signal io_pipelinedMemoryBus_cmd_halfPipe_fire : std_logic; + signal io_pipelinedMemoryBus_cmd_rData_write : std_logic; + signal io_pipelinedMemoryBus_cmd_rData_address : unsigned(31 downto 0); + signal io_pipelinedMemoryBus_cmd_rData_data : std_logic_vector(31 downto 0); + signal io_pipelinedMemoryBus_cmd_rData_mask : std_logic_vector(3 downto 0); + signal pipelinedMemoryBusStage_rsp_regNext_valid : std_logic; + signal pipelinedMemoryBusStage_rsp_regNext_payload_data : std_logic_vector(31 downto 0); + signal state : std_logic; + signal when_PipelinedMemoryBus_l369 : std_logic; +begin + io_pipelinedMemoryBus_cmd_ready <= io_pipelinedMemoryBus_cmd_ready_read_buffer; + io_pipelinedMemoryBus_cmd_halfPipe_fire <= (io_pipelinedMemoryBus_cmd_halfPipe_valid and io_pipelinedMemoryBus_cmd_halfPipe_ready); + io_pipelinedMemoryBus_cmd_ready_read_buffer <= (not io_pipelinedMemoryBus_cmd_rValid); + io_pipelinedMemoryBus_cmd_halfPipe_valid <= io_pipelinedMemoryBus_cmd_rValid; + io_pipelinedMemoryBus_cmd_halfPipe_payload_write <= io_pipelinedMemoryBus_cmd_rData_write; + io_pipelinedMemoryBus_cmd_halfPipe_payload_address <= io_pipelinedMemoryBus_cmd_rData_address; + io_pipelinedMemoryBus_cmd_halfPipe_payload_data <= io_pipelinedMemoryBus_cmd_rData_data; + io_pipelinedMemoryBus_cmd_halfPipe_payload_mask <= io_pipelinedMemoryBus_cmd_rData_mask; + pipelinedMemoryBusStage_cmd_valid <= io_pipelinedMemoryBus_cmd_halfPipe_valid; + io_pipelinedMemoryBus_cmd_halfPipe_ready <= pipelinedMemoryBusStage_cmd_ready; + pipelinedMemoryBusStage_cmd_payload_write <= io_pipelinedMemoryBus_cmd_halfPipe_payload_write; + pipelinedMemoryBusStage_cmd_payload_address <= io_pipelinedMemoryBus_cmd_halfPipe_payload_address; + pipelinedMemoryBusStage_cmd_payload_data <= io_pipelinedMemoryBus_cmd_halfPipe_payload_data; + pipelinedMemoryBusStage_cmd_payload_mask <= io_pipelinedMemoryBus_cmd_halfPipe_payload_mask; + io_pipelinedMemoryBus_rsp_valid <= pipelinedMemoryBusStage_rsp_regNext_valid; + io_pipelinedMemoryBus_rsp_payload_data <= pipelinedMemoryBusStage_rsp_regNext_payload_data; + process(when_PipelinedMemoryBus_l369,io_apb_PREADY) + begin + pipelinedMemoryBusStage_cmd_ready <= pkg_toStdLogic(false); + if when_PipelinedMemoryBus_l369 = '0' then + if io_apb_PREADY = '1' then + pipelinedMemoryBusStage_cmd_ready <= pkg_toStdLogic(true); + end if; + end if; + end process; + + io_apb_PSEL(0) <= pipelinedMemoryBusStage_cmd_valid; + io_apb_PENABLE <= state; + io_apb_PWRITE <= pipelinedMemoryBusStage_cmd_payload_write; + io_apb_PADDR <= pkg_resize(pipelinedMemoryBusStage_cmd_payload_address,20); + io_apb_PWDATA <= pipelinedMemoryBusStage_cmd_payload_data; + process(when_PipelinedMemoryBus_l369,io_apb_PREADY,pipelinedMemoryBusStage_cmd_payload_write) + begin + pipelinedMemoryBusStage_rsp_valid <= pkg_toStdLogic(false); + if when_PipelinedMemoryBus_l369 = '0' then + if io_apb_PREADY = '1' then + pipelinedMemoryBusStage_rsp_valid <= (not pipelinedMemoryBusStage_cmd_payload_write); + end if; + end if; + end process; + + pipelinedMemoryBusStage_rsp_payload_data <= io_apb_PRDATA; + when_PipelinedMemoryBus_l369 <= (not state); + process(io_mainClk, resetCtrl_systemReset) + begin + if resetCtrl_systemReset = '1' then + io_pipelinedMemoryBus_cmd_rValid <= pkg_toStdLogic(false); + pipelinedMemoryBusStage_rsp_regNext_valid <= pkg_toStdLogic(false); + state <= pkg_toStdLogic(false); + elsif rising_edge(io_mainClk) then + if io_pipelinedMemoryBus_cmd_valid = '1' then + io_pipelinedMemoryBus_cmd_rValid <= pkg_toStdLogic(true); + end if; + if io_pipelinedMemoryBus_cmd_halfPipe_fire = '1' then + io_pipelinedMemoryBus_cmd_rValid <= pkg_toStdLogic(false); + end if; + pipelinedMemoryBusStage_rsp_regNext_valid <= pipelinedMemoryBusStage_rsp_valid; + if when_PipelinedMemoryBus_l369 = '1' then + state <= pipelinedMemoryBusStage_cmd_valid; + else + if io_apb_PREADY = '1' then + state <= pkg_toStdLogic(false); + end if; + end if; + end if; + end process; + + process(io_mainClk) + begin + if rising_edge(io_mainClk) then + if io_pipelinedMemoryBus_cmd_ready_read_buffer = '1' then + io_pipelinedMemoryBus_cmd_rData_write <= io_pipelinedMemoryBus_cmd_payload_write; + io_pipelinedMemoryBus_cmd_rData_address <= io_pipelinedMemoryBus_cmd_payload_address; + io_pipelinedMemoryBus_cmd_rData_data <= io_pipelinedMemoryBus_cmd_payload_data; + io_pipelinedMemoryBus_cmd_rData_mask <= io_pipelinedMemoryBus_cmd_payload_mask; + end if; + pipelinedMemoryBusStage_rsp_regNext_payload_data <= pipelinedMemoryBusStage_rsp_payload_data; + end if; + end process; + +end arch; + +library ieee; +use ieee.std_logic_1164.all; +use ieee.numeric_std.all; + +library work; +use work.pkg_scala2hdl.all; +use work.all; +use work.pkg_enum.all; + + +entity Apb3Gpio is + port( + io_apb_PADDR : in unsigned(3 downto 0); + io_apb_PSEL : in std_logic_vector(0 downto 0); + io_apb_PENABLE : in std_logic; + io_apb_PREADY : out std_logic; + io_apb_PWRITE : in std_logic; + io_apb_PWDATA : in std_logic_vector(31 downto 0); + io_apb_PRDATA : out std_logic_vector(31 downto 0); + io_apb_PSLVERROR : out std_logic; + io_gpio_read : in std_logic_vector(31 downto 0); + io_gpio_write : out std_logic_vector(31 downto 0); + io_gpio_writeEnable : out std_logic_vector(31 downto 0); + io_value : out std_logic_vector(31 downto 0); + io_mainClk : in std_logic; + resetCtrl_systemReset : in std_logic + ); +end Apb3Gpio; + +architecture arch of Apb3Gpio is + signal io_apb_PREADY_read_buffer : std_logic; + signal io_value_read_buffer : std_logic_vector(31 downto 0); + signal io_gpio_read_buffercc_io_dataOut : std_logic_vector(31 downto 0); + + signal ctrl_askWrite : std_logic; + signal ctrl_askRead : std_logic; + signal ctrl_doWrite : std_logic; + signal ctrl_doRead : std_logic; + signal io_gpio_write_driver : std_logic_vector(31 downto 0); + signal io_gpio_writeEnable_driver : std_logic_vector(31 downto 0); +begin + io_apb_PREADY <= io_apb_PREADY_read_buffer; + io_value <= io_value_read_buffer; + io_gpio_read_buffercc : entity work.BufferCC_2 + port map ( + io_dataIn => io_gpio_read, + io_dataOut => io_gpio_read_buffercc_io_dataOut, + io_mainClk => io_mainClk, + resetCtrl_systemReset => resetCtrl_systemReset + ); + io_value_read_buffer <= io_gpio_read_buffercc_io_dataOut; + io_apb_PREADY_read_buffer <= pkg_toStdLogic(true); + process(io_apb_PADDR,io_value_read_buffer,io_gpio_write_driver,io_gpio_writeEnable_driver) + begin + io_apb_PRDATA <= pkg_stdLogicVector("00000000000000000000000000000000"); + case io_apb_PADDR is + when "0000" => + io_apb_PRDATA(31 downto 0) <= io_value_read_buffer; + when "0100" => + io_apb_PRDATA(31 downto 0) <= io_gpio_write_driver; + when "1000" => + io_apb_PRDATA(31 downto 0) <= io_gpio_writeEnable_driver; + when others => + end case; + end process; + + io_apb_PSLVERROR <= pkg_toStdLogic(false); + ctrl_askWrite <= ((pkg_extract(io_apb_PSEL,0) and io_apb_PENABLE) and io_apb_PWRITE); + ctrl_askRead <= ((pkg_extract(io_apb_PSEL,0) and io_apb_PENABLE) and (not io_apb_PWRITE)); + ctrl_doWrite <= (((pkg_extract(io_apb_PSEL,0) and io_apb_PENABLE) and io_apb_PREADY_read_buffer) and io_apb_PWRITE); + ctrl_doRead <= (((pkg_extract(io_apb_PSEL,0) and io_apb_PENABLE) and io_apb_PREADY_read_buffer) and (not io_apb_PWRITE)); + io_gpio_write <= io_gpio_write_driver; + io_gpio_writeEnable <= io_gpio_writeEnable_driver; + process(io_mainClk, resetCtrl_systemReset) + begin + if resetCtrl_systemReset = '1' then + io_gpio_writeEnable_driver <= pkg_stdLogicVector("00000000000000000000000000000000"); + elsif rising_edge(io_mainClk) then + case io_apb_PADDR is + when "1000" => + if ctrl_doWrite = '1' then + io_gpio_writeEnable_driver <= pkg_extract(io_apb_PWDATA,31,0); + end if; + when others => + end case; + end if; + end process; + + process(io_mainClk) + begin + if rising_edge(io_mainClk) then + case io_apb_PADDR is + when "0100" => + if ctrl_doWrite = '1' then + io_gpio_write_driver <= pkg_extract(io_apb_PWDATA,31,0); + end if; + when others => + end case; + end if; + end process; + +end arch; + +library ieee; +use ieee.std_logic_1164.all; +use ieee.numeric_std.all; + +library work; +use work.pkg_scala2hdl.all; +use work.all; +use work.pkg_enum.all; + + +entity Apb3UartCtrl is + port( + io_apb_PADDR : in unsigned(4 downto 0); + io_apb_PSEL : in std_logic_vector(0 downto 0); + io_apb_PENABLE : in std_logic; + io_apb_PREADY : out std_logic; + io_apb_PWRITE : in std_logic; + io_apb_PWDATA : in std_logic_vector(31 downto 0); + io_apb_PRDATA : out std_logic_vector(31 downto 0); + io_uart_txd : out std_logic; + io_uart_rxd : in std_logic; + io_interrupt : out std_logic; + io_mainClk : in std_logic; + resetCtrl_systemReset : in std_logic + ); +end Apb3UartCtrl; + +architecture arch of Apb3UartCtrl is + signal uartCtrl_1_io_read_queueWithOccupancy_io_pop_ready : std_logic; + signal io_apb_PREADY_read_buffer : std_logic; + signal uartCtrl_1_io_write_ready : std_logic; + signal uartCtrl_1_io_read_valid : std_logic; + signal uartCtrl_1_io_read_payload : std_logic_vector(7 downto 0); + signal uartCtrl_1_io_uart_txd : std_logic; + signal uartCtrl_1_io_readError : std_logic; + signal uartCtrl_1_io_readBreak : std_logic; + signal bridge_write_streamUnbuffered_queueWithOccupancy_io_push_ready : std_logic; + signal bridge_write_streamUnbuffered_queueWithOccupancy_io_pop_valid : std_logic; + signal bridge_write_streamUnbuffered_queueWithOccupancy_io_pop_payload : std_logic_vector(7 downto 0); + signal bridge_write_streamUnbuffered_queueWithOccupancy_io_occupancy : unsigned(4 downto 0); + signal bridge_write_streamUnbuffered_queueWithOccupancy_io_availability : unsigned(4 downto 0); + signal uartCtrl_1_io_read_queueWithOccupancy_io_push_ready : std_logic; + signal uartCtrl_1_io_read_queueWithOccupancy_io_pop_valid : std_logic; + signal uartCtrl_1_io_read_queueWithOccupancy_io_pop_payload : std_logic_vector(7 downto 0); + signal uartCtrl_1_io_read_queueWithOccupancy_io_occupancy : unsigned(4 downto 0); + signal uartCtrl_1_io_read_queueWithOccupancy_io_availability : unsigned(4 downto 0); + + signal busCtrl_askWrite : std_logic; + signal busCtrl_askRead : std_logic; + signal busCtrl_doWrite : std_logic; + signal busCtrl_doRead : std_logic; + signal bridge_uartConfigReg_frame_dataLength : unsigned(2 downto 0); + signal bridge_uartConfigReg_frame_stop : UartStopType_seq_type; + signal bridge_uartConfigReg_frame_parity : UartParityType_seq_type; + signal bridge_uartConfigReg_clockDivider : unsigned(19 downto 0); + signal zz_bridge_write_streamUnbuffered_valid : std_logic; + signal bridge_write_streamUnbuffered_valid : std_logic; + signal bridge_write_streamUnbuffered_ready : std_logic; + signal bridge_write_streamUnbuffered_payload : std_logic_vector(7 downto 0); + signal bridge_read_streamBreaked_valid : std_logic; + signal bridge_read_streamBreaked_ready : std_logic; + signal bridge_read_streamBreaked_payload : std_logic_vector(7 downto 0); + signal bridge_interruptCtrl_writeIntEnable : std_logic; + signal bridge_interruptCtrl_readIntEnable : std_logic; + signal bridge_interruptCtrl_readInt : std_logic; + signal bridge_interruptCtrl_writeInt : std_logic; + signal bridge_interruptCtrl_interrupt : std_logic; + signal bridge_misc_readError : std_logic; + signal when_BusSlaveFactory_l335 : std_logic; + signal when_BusSlaveFactory_l341 : std_logic; + signal bridge_misc_readOverflowError : std_logic; + signal when_BusSlaveFactory_l335_1 : std_logic; + signal when_BusSlaveFactory_l341_1 : std_logic; + signal uartCtrl_1_io_read_isStall : std_logic; + signal bridge_misc_breakDetected : std_logic; + signal uartCtrl_1_io_readBreak_regNext : std_logic; + signal when_UartCtrl_l155 : std_logic; + signal when_BusSlaveFactory_l335_2 : std_logic; + signal when_BusSlaveFactory_l341_2 : std_logic; + signal bridge_misc_doBreak : std_logic; + signal when_BusSlaveFactory_l371 : std_logic; + signal when_BusSlaveFactory_l373 : std_logic; + signal when_BusSlaveFactory_l335_3 : std_logic; + signal when_BusSlaveFactory_l341_3 : std_logic; + function zz_bridge_uartConfigReg_clockDivider return unsigned is + variable bridge_uartConfigReg_clockDivider_v : unsigned(19 downto 0); + begin + bridge_uartConfigReg_clockDivider_v := pkg_unsigned("00000000000000000000"); + bridge_uartConfigReg_clockDivider_v := pkg_unsigned("00000000000001010101"); + return bridge_uartConfigReg_clockDivider_v; + end function; +begin + io_apb_PREADY <= io_apb_PREADY_read_buffer; + uartCtrl_1 : entity work.UartCtrl + port map ( + io_config_frame_dataLength => bridge_uartConfigReg_frame_dataLength, + io_config_frame_stop => bridge_uartConfigReg_frame_stop, + io_config_frame_parity => bridge_uartConfigReg_frame_parity, + io_config_clockDivider => bridge_uartConfigReg_clockDivider, + io_write_valid => bridge_write_streamUnbuffered_queueWithOccupancy_io_pop_valid, + io_write_ready => uartCtrl_1_io_write_ready, + io_write_payload => bridge_write_streamUnbuffered_queueWithOccupancy_io_pop_payload, + io_read_valid => uartCtrl_1_io_read_valid, + io_read_ready => uartCtrl_1_io_read_queueWithOccupancy_io_push_ready, + io_read_payload => uartCtrl_1_io_read_payload, + io_uart_txd => uartCtrl_1_io_uart_txd, + io_uart_rxd => io_uart_rxd, + io_readError => uartCtrl_1_io_readError, + io_writeBreak => bridge_misc_doBreak, + io_readBreak => uartCtrl_1_io_readBreak, + io_mainClk => io_mainClk, + resetCtrl_systemReset => resetCtrl_systemReset + ); + bridge_write_streamUnbuffered_queueWithOccupancy : entity work.StreamFifo + port map ( + io_push_valid => bridge_write_streamUnbuffered_valid, + io_push_ready => bridge_write_streamUnbuffered_queueWithOccupancy_io_push_ready, + io_push_payload => bridge_write_streamUnbuffered_payload, + io_pop_valid => bridge_write_streamUnbuffered_queueWithOccupancy_io_pop_valid, + io_pop_ready => uartCtrl_1_io_write_ready, + io_pop_payload => bridge_write_streamUnbuffered_queueWithOccupancy_io_pop_payload, + io_flush => pkg_toStdLogic(false), + io_occupancy => bridge_write_streamUnbuffered_queueWithOccupancy_io_occupancy, + io_availability => bridge_write_streamUnbuffered_queueWithOccupancy_io_availability, + io_mainClk => io_mainClk, + resetCtrl_systemReset => resetCtrl_systemReset + ); + uartCtrl_1_io_read_queueWithOccupancy : entity work.StreamFifo + port map ( + io_push_valid => uartCtrl_1_io_read_valid, + io_push_ready => uartCtrl_1_io_read_queueWithOccupancy_io_push_ready, + io_push_payload => uartCtrl_1_io_read_payload, + io_pop_valid => uartCtrl_1_io_read_queueWithOccupancy_io_pop_valid, + io_pop_ready => uartCtrl_1_io_read_queueWithOccupancy_io_pop_ready, + io_pop_payload => uartCtrl_1_io_read_queueWithOccupancy_io_pop_payload, + io_flush => pkg_toStdLogic(false), + io_occupancy => uartCtrl_1_io_read_queueWithOccupancy_io_occupancy, + io_availability => uartCtrl_1_io_read_queueWithOccupancy_io_availability, + io_mainClk => io_mainClk, + resetCtrl_systemReset => resetCtrl_systemReset + ); + io_uart_txd <= uartCtrl_1_io_uart_txd; + io_apb_PREADY_read_buffer <= pkg_toStdLogic(true); + process(io_apb_PADDR,bridge_read_streamBreaked_valid,bridge_read_streamBreaked_payload,bridge_write_streamUnbuffered_queueWithOccupancy_io_occupancy,bridge_write_streamUnbuffered_queueWithOccupancy_io_pop_valid,uartCtrl_1_io_read_queueWithOccupancy_io_occupancy,bridge_interruptCtrl_writeIntEnable,bridge_interruptCtrl_readIntEnable,bridge_interruptCtrl_writeInt,bridge_interruptCtrl_readInt,bridge_misc_readError,bridge_misc_readOverflowError,uartCtrl_1_io_readBreak,bridge_misc_breakDetected) + begin + io_apb_PRDATA <= pkg_stdLogicVector("00000000000000000000000000000000"); + case io_apb_PADDR is + when "00000" => + io_apb_PRDATA(16 downto 16) <= pkg_toStdLogicVector((bridge_read_streamBreaked_valid xor pkg_toStdLogic(false))); + io_apb_PRDATA(7 downto 0) <= bridge_read_streamBreaked_payload; + when "00100" => + io_apb_PRDATA(20 downto 16) <= std_logic_vector((pkg_unsigned("10000") - bridge_write_streamUnbuffered_queueWithOccupancy_io_occupancy)); + io_apb_PRDATA(15 downto 15) <= pkg_toStdLogicVector(bridge_write_streamUnbuffered_queueWithOccupancy_io_pop_valid); + io_apb_PRDATA(28 downto 24) <= std_logic_vector(uartCtrl_1_io_read_queueWithOccupancy_io_occupancy); + io_apb_PRDATA(0 downto 0) <= pkg_toStdLogicVector(bridge_interruptCtrl_writeIntEnable); + io_apb_PRDATA(1 downto 1) <= pkg_toStdLogicVector(bridge_interruptCtrl_readIntEnable); + io_apb_PRDATA(8 downto 8) <= pkg_toStdLogicVector(bridge_interruptCtrl_writeInt); + io_apb_PRDATA(9 downto 9) <= pkg_toStdLogicVector(bridge_interruptCtrl_readInt); + when "10000" => + io_apb_PRDATA(0 downto 0) <= pkg_toStdLogicVector(bridge_misc_readError); + io_apb_PRDATA(1 downto 1) <= pkg_toStdLogicVector(bridge_misc_readOverflowError); + io_apb_PRDATA(8 downto 8) <= pkg_toStdLogicVector(uartCtrl_1_io_readBreak); + io_apb_PRDATA(9 downto 9) <= pkg_toStdLogicVector(bridge_misc_breakDetected); + when others => + end case; + end process; + + busCtrl_askWrite <= ((pkg_extract(io_apb_PSEL,0) and io_apb_PENABLE) and io_apb_PWRITE); + busCtrl_askRead <= ((pkg_extract(io_apb_PSEL,0) and io_apb_PENABLE) and (not io_apb_PWRITE)); + busCtrl_doWrite <= (((pkg_extract(io_apb_PSEL,0) and io_apb_PENABLE) and io_apb_PREADY_read_buffer) and io_apb_PWRITE); + busCtrl_doRead <= (((pkg_extract(io_apb_PSEL,0) and io_apb_PENABLE) and io_apb_PREADY_read_buffer) and (not io_apb_PWRITE)); + bridge_uartConfigReg_clockDivider <= zz_bridge_uartConfigReg_clockDivider; + bridge_uartConfigReg_frame_dataLength <= pkg_unsigned("111"); + bridge_uartConfigReg_frame_parity <= UartParityType_seq_NONE; + bridge_uartConfigReg_frame_stop <= UartStopType_seq_ONE; + process(io_apb_PADDR,busCtrl_doWrite) + begin + zz_bridge_write_streamUnbuffered_valid <= pkg_toStdLogic(false); + case io_apb_PADDR is + when "00000" => + if busCtrl_doWrite = '1' then + zz_bridge_write_streamUnbuffered_valid <= pkg_toStdLogic(true); + end if; + when others => + end case; + end process; + + bridge_write_streamUnbuffered_valid <= zz_bridge_write_streamUnbuffered_valid; + bridge_write_streamUnbuffered_payload <= pkg_extract(io_apb_PWDATA,7,0); + bridge_write_streamUnbuffered_ready <= bridge_write_streamUnbuffered_queueWithOccupancy_io_push_ready; + process(uartCtrl_1_io_read_queueWithOccupancy_io_pop_valid,uartCtrl_1_io_readBreak) + begin + bridge_read_streamBreaked_valid <= uartCtrl_1_io_read_queueWithOccupancy_io_pop_valid; + if uartCtrl_1_io_readBreak = '1' then + bridge_read_streamBreaked_valid <= pkg_toStdLogic(false); + end if; + end process; + + process(bridge_read_streamBreaked_ready,uartCtrl_1_io_readBreak) + begin + uartCtrl_1_io_read_queueWithOccupancy_io_pop_ready <= bridge_read_streamBreaked_ready; + if uartCtrl_1_io_readBreak = '1' then + uartCtrl_1_io_read_queueWithOccupancy_io_pop_ready <= pkg_toStdLogic(true); + end if; + end process; + + bridge_read_streamBreaked_payload <= uartCtrl_1_io_read_queueWithOccupancy_io_pop_payload; + process(io_apb_PADDR,busCtrl_doRead) + begin + bridge_read_streamBreaked_ready <= pkg_toStdLogic(false); + case io_apb_PADDR is + when "00000" => + if busCtrl_doRead = '1' then + bridge_read_streamBreaked_ready <= pkg_toStdLogic(true); + end if; + when others => + end case; + end process; + + bridge_interruptCtrl_readInt <= (bridge_interruptCtrl_readIntEnable and bridge_read_streamBreaked_valid); + bridge_interruptCtrl_writeInt <= (bridge_interruptCtrl_writeIntEnable and (not bridge_write_streamUnbuffered_queueWithOccupancy_io_pop_valid)); + bridge_interruptCtrl_interrupt <= (bridge_interruptCtrl_readInt or bridge_interruptCtrl_writeInt); + process(io_apb_PADDR,busCtrl_doWrite) + begin + when_BusSlaveFactory_l335 <= pkg_toStdLogic(false); + case io_apb_PADDR is + when "10000" => + if busCtrl_doWrite = '1' then + when_BusSlaveFactory_l335 <= pkg_toStdLogic(true); + end if; + when others => + end case; + end process; + + when_BusSlaveFactory_l341 <= pkg_extract(io_apb_PWDATA,0); + process(io_apb_PADDR,busCtrl_doWrite) + begin + when_BusSlaveFactory_l335_1 <= pkg_toStdLogic(false); + case io_apb_PADDR is + when "10000" => + if busCtrl_doWrite = '1' then + when_BusSlaveFactory_l335_1 <= pkg_toStdLogic(true); + end if; + when others => + end case; + end process; + + when_BusSlaveFactory_l341_1 <= pkg_extract(io_apb_PWDATA,1); + uartCtrl_1_io_read_isStall <= (uartCtrl_1_io_read_valid and (not uartCtrl_1_io_read_queueWithOccupancy_io_push_ready)); + when_UartCtrl_l155 <= (uartCtrl_1_io_readBreak and (not uartCtrl_1_io_readBreak_regNext)); + process(io_apb_PADDR,busCtrl_doWrite) + begin + when_BusSlaveFactory_l335_2 <= pkg_toStdLogic(false); + case io_apb_PADDR is + when "10000" => + if busCtrl_doWrite = '1' then + when_BusSlaveFactory_l335_2 <= pkg_toStdLogic(true); + end if; + when others => + end case; + end process; + + when_BusSlaveFactory_l341_2 <= pkg_extract(io_apb_PWDATA,9); + process(io_apb_PADDR,busCtrl_doWrite) + begin + when_BusSlaveFactory_l371 <= pkg_toStdLogic(false); + case io_apb_PADDR is + when "10000" => + if busCtrl_doWrite = '1' then + when_BusSlaveFactory_l371 <= pkg_toStdLogic(true); + end if; + when others => + end case; + end process; + + when_BusSlaveFactory_l373 <= pkg_extract(io_apb_PWDATA,10); + process(io_apb_PADDR,busCtrl_doWrite) + begin + when_BusSlaveFactory_l335_3 <= pkg_toStdLogic(false); + case io_apb_PADDR is + when "10000" => + if busCtrl_doWrite = '1' then + when_BusSlaveFactory_l335_3 <= pkg_toStdLogic(true); + end if; + when others => + end case; + end process; + + when_BusSlaveFactory_l341_3 <= pkg_extract(io_apb_PWDATA,11); + io_interrupt <= bridge_interruptCtrl_interrupt; + process(io_mainClk, resetCtrl_systemReset) + begin + if resetCtrl_systemReset = '1' then + bridge_interruptCtrl_writeIntEnable <= pkg_toStdLogic(false); + bridge_interruptCtrl_readIntEnable <= pkg_toStdLogic(false); + bridge_misc_readError <= pkg_toStdLogic(false); + bridge_misc_readOverflowError <= pkg_toStdLogic(false); + bridge_misc_breakDetected <= pkg_toStdLogic(false); + bridge_misc_doBreak <= pkg_toStdLogic(false); + elsif rising_edge(io_mainClk) then + if when_BusSlaveFactory_l335 = '1' then + if when_BusSlaveFactory_l341 = '1' then + bridge_misc_readError <= pkg_extract(pkg_stdLogicVector("0"),0); + end if; + end if; + if uartCtrl_1_io_readError = '1' then + bridge_misc_readError <= pkg_toStdLogic(true); + end if; + if when_BusSlaveFactory_l335_1 = '1' then + if when_BusSlaveFactory_l341_1 = '1' then + bridge_misc_readOverflowError <= pkg_extract(pkg_stdLogicVector("0"),0); + end if; + end if; + if uartCtrl_1_io_read_isStall = '1' then + bridge_misc_readOverflowError <= pkg_toStdLogic(true); + end if; + if when_UartCtrl_l155 = '1' then + bridge_misc_breakDetected <= pkg_toStdLogic(true); + end if; + if when_BusSlaveFactory_l335_2 = '1' then + if when_BusSlaveFactory_l341_2 = '1' then + bridge_misc_breakDetected <= pkg_extract(pkg_stdLogicVector("0"),0); + end if; + end if; + if when_BusSlaveFactory_l371 = '1' then + if when_BusSlaveFactory_l373 = '1' then + bridge_misc_doBreak <= pkg_extract(pkg_stdLogicVector("1"),0); + end if; + end if; + if when_BusSlaveFactory_l335_3 = '1' then + if when_BusSlaveFactory_l341_3 = '1' then + bridge_misc_doBreak <= pkg_extract(pkg_stdLogicVector("0"),0); + end if; + end if; + case io_apb_PADDR is + when "00100" => + if busCtrl_doWrite = '1' then + bridge_interruptCtrl_writeIntEnable <= pkg_extract(io_apb_PWDATA,0); + bridge_interruptCtrl_readIntEnable <= pkg_extract(io_apb_PWDATA,1); + end if; + when others => + end case; + end if; + end process; + + process(io_mainClk) + begin + if rising_edge(io_mainClk) then + uartCtrl_1_io_readBreak_regNext <= uartCtrl_1_io_readBreak; + end if; + end process; + +end arch; + +library ieee; +use ieee.std_logic_1164.all; +use ieee.numeric_std.all; + +library work; +use work.pkg_scala2hdl.all; +use work.all; +use work.pkg_enum.all; + + +entity MuraxApb3Timer is + port( + io_apb_PADDR : in unsigned(7 downto 0); + io_apb_PSEL : in std_logic_vector(0 downto 0); + io_apb_PENABLE : in std_logic; + io_apb_PREADY : out std_logic; + io_apb_PWRITE : in std_logic; + io_apb_PWDATA : in std_logic_vector(31 downto 0); + io_apb_PRDATA : out std_logic_vector(31 downto 0); + io_apb_PSLVERROR : out std_logic; + io_interrupt : out std_logic; + io_mainClk : in std_logic; + resetCtrl_systemReset : in std_logic + ); +end MuraxApb3Timer; + +architecture arch of MuraxApb3Timer is + signal timerA_io_tick : std_logic; + signal timerA_io_clear : std_logic; + signal timerB_io_tick : std_logic; + signal timerB_io_clear : std_logic; + signal interruptCtrl_1_io_inputs : std_logic_vector(1 downto 0); + signal interruptCtrl_1_io_clears : std_logic_vector(1 downto 0); + signal io_apb_PREADY_read_buffer : std_logic; + signal prescaler_1_io_overflow : std_logic; + signal timerA_io_full : std_logic; + signal timerA_io_value : unsigned(15 downto 0); + signal timerB_io_full : std_logic; + signal timerB_io_value : unsigned(15 downto 0); + signal interruptCtrl_1_io_pendings : std_logic_vector(1 downto 0); + + signal busCtrl_askWrite : std_logic; + signal busCtrl_askRead : std_logic; + signal busCtrl_doWrite : std_logic; + signal busCtrl_doRead : std_logic; + signal zz_io_limit : unsigned(15 downto 0); + signal zz_io_clear : std_logic; + signal timerABridge_ticksEnable : std_logic_vector(1 downto 0); + signal timerABridge_clearsEnable : std_logic_vector(0 downto 0); + signal timerABridge_busClearing : std_logic; + signal timerA_io_limit_driver : unsigned(15 downto 0); + signal when_Timer_l40 : std_logic; + signal when_Timer_l44 : std_logic; + signal timerBBridge_ticksEnable : std_logic_vector(1 downto 0); + signal timerBBridge_clearsEnable : std_logic_vector(0 downto 0); + signal timerBBridge_busClearing : std_logic; + signal timerB_io_limit_driver : unsigned(15 downto 0); + signal when_Timer_l40_1 : std_logic; + signal when_Timer_l44_1 : std_logic; + signal interruptCtrl_1_io_masks_driver : std_logic_vector(1 downto 0); +begin + io_apb_PREADY <= io_apb_PREADY_read_buffer; + prescaler_1 : entity work.Prescaler + port map ( + io_clear => zz_io_clear, + io_limit => zz_io_limit, + io_overflow => prescaler_1_io_overflow, + io_mainClk => io_mainClk, + resetCtrl_systemReset => resetCtrl_systemReset + ); + timerA : entity work.Timer + port map ( + io_tick => timerA_io_tick, + io_clear => timerA_io_clear, + io_limit => timerA_io_limit_driver, + io_full => timerA_io_full, + io_value => timerA_io_value, + io_mainClk => io_mainClk, + resetCtrl_systemReset => resetCtrl_systemReset + ); + timerB : entity work.Timer + port map ( + io_tick => timerB_io_tick, + io_clear => timerB_io_clear, + io_limit => timerB_io_limit_driver, + io_full => timerB_io_full, + io_value => timerB_io_value, + io_mainClk => io_mainClk, + resetCtrl_systemReset => resetCtrl_systemReset + ); + interruptCtrl_1 : entity work.InterruptCtrl + port map ( + io_inputs => interruptCtrl_1_io_inputs, + io_clears => interruptCtrl_1_io_clears, + io_masks => interruptCtrl_1_io_masks_driver, + io_pendings => interruptCtrl_1_io_pendings, + io_mainClk => io_mainClk, + resetCtrl_systemReset => resetCtrl_systemReset + ); + io_apb_PREADY_read_buffer <= pkg_toStdLogic(true); + process(io_apb_PADDR,zz_io_limit,timerABridge_ticksEnable,timerABridge_clearsEnable,timerA_io_limit_driver,timerA_io_value,timerBBridge_ticksEnable,timerBBridge_clearsEnable,timerB_io_limit_driver,timerB_io_value,interruptCtrl_1_io_pendings,interruptCtrl_1_io_masks_driver) + begin + io_apb_PRDATA <= pkg_stdLogicVector("00000000000000000000000000000000"); + case io_apb_PADDR is + when "00000000" => + io_apb_PRDATA(15 downto 0) <= std_logic_vector(zz_io_limit); + when "01000000" => + io_apb_PRDATA(1 downto 0) <= timerABridge_ticksEnable; + io_apb_PRDATA(16 downto 16) <= timerABridge_clearsEnable; + when "01000100" => + io_apb_PRDATA(15 downto 0) <= std_logic_vector(timerA_io_limit_driver); + when "01001000" => + io_apb_PRDATA(15 downto 0) <= std_logic_vector(timerA_io_value); + when "01010000" => + io_apb_PRDATA(1 downto 0) <= timerBBridge_ticksEnable; + io_apb_PRDATA(16 downto 16) <= timerBBridge_clearsEnable; + when "01010100" => + io_apb_PRDATA(15 downto 0) <= std_logic_vector(timerB_io_limit_driver); + when "01011000" => + io_apb_PRDATA(15 downto 0) <= std_logic_vector(timerB_io_value); + when "00010000" => + io_apb_PRDATA(1 downto 0) <= interruptCtrl_1_io_pendings; + when "00010100" => + io_apb_PRDATA(1 downto 0) <= interruptCtrl_1_io_masks_driver; + when others => + end case; + end process; + + io_apb_PSLVERROR <= pkg_toStdLogic(false); + busCtrl_askWrite <= ((pkg_extract(io_apb_PSEL,0) and io_apb_PENABLE) and io_apb_PWRITE); + busCtrl_askRead <= ((pkg_extract(io_apb_PSEL,0) and io_apb_PENABLE) and (not io_apb_PWRITE)); + busCtrl_doWrite <= (((pkg_extract(io_apb_PSEL,0) and io_apb_PENABLE) and io_apb_PREADY_read_buffer) and io_apb_PWRITE); + busCtrl_doRead <= (((pkg_extract(io_apb_PSEL,0) and io_apb_PENABLE) and io_apb_PREADY_read_buffer) and (not io_apb_PWRITE)); + process(io_apb_PADDR,busCtrl_doWrite) + begin + zz_io_clear <= pkg_toStdLogic(false); + case io_apb_PADDR is + when "00000000" => + if busCtrl_doWrite = '1' then + zz_io_clear <= pkg_toStdLogic(true); + end if; + when others => + end case; + end process; + + process(when_Timer_l40,when_Timer_l44) + begin + timerABridge_busClearing <= pkg_toStdLogic(false); + if when_Timer_l40 = '1' then + timerABridge_busClearing <= pkg_toStdLogic(true); + end if; + if when_Timer_l44 = '1' then + timerABridge_busClearing <= pkg_toStdLogic(true); + end if; + end process; + + process(io_apb_PADDR,busCtrl_doWrite) + begin + when_Timer_l40 <= pkg_toStdLogic(false); + case io_apb_PADDR is + when "01000100" => + if busCtrl_doWrite = '1' then + when_Timer_l40 <= pkg_toStdLogic(true); + end if; + when others => + end case; + end process; + + process(io_apb_PADDR,busCtrl_doWrite) + begin + when_Timer_l44 <= pkg_toStdLogic(false); + case io_apb_PADDR is + when "01001000" => + if busCtrl_doWrite = '1' then + when_Timer_l44 <= pkg_toStdLogic(true); + end if; + when others => + end case; + end process; + + timerA_io_clear <= (pkg_toStdLogic((timerABridge_clearsEnable and pkg_toStdLogicVector(timerA_io_full)) /= pkg_stdLogicVector("0")) or timerABridge_busClearing); + timerA_io_tick <= pkg_toStdLogic((timerABridge_ticksEnable and pkg_cat(pkg_toStdLogicVector(prescaler_1_io_overflow),pkg_toStdLogicVector(pkg_toStdLogic(true)))) /= pkg_stdLogicVector("00")); + process(when_Timer_l40_1,when_Timer_l44_1) + begin + timerBBridge_busClearing <= pkg_toStdLogic(false); + if when_Timer_l40_1 = '1' then + timerBBridge_busClearing <= pkg_toStdLogic(true); + end if; + if when_Timer_l44_1 = '1' then + timerBBridge_busClearing <= pkg_toStdLogic(true); + end if; + end process; + + process(io_apb_PADDR,busCtrl_doWrite) + begin + when_Timer_l40_1 <= pkg_toStdLogic(false); + case io_apb_PADDR is + when "01010100" => + if busCtrl_doWrite = '1' then + when_Timer_l40_1 <= pkg_toStdLogic(true); + end if; + when others => + end case; + end process; + + process(io_apb_PADDR,busCtrl_doWrite) + begin + when_Timer_l44_1 <= pkg_toStdLogic(false); + case io_apb_PADDR is + when "01011000" => + if busCtrl_doWrite = '1' then + when_Timer_l44_1 <= pkg_toStdLogic(true); + end if; + when others => + end case; + end process; + + timerB_io_clear <= (pkg_toStdLogic((timerBBridge_clearsEnable and pkg_toStdLogicVector(timerB_io_full)) /= pkg_stdLogicVector("0")) or timerBBridge_busClearing); + timerB_io_tick <= pkg_toStdLogic((timerBBridge_ticksEnable and pkg_cat(pkg_toStdLogicVector(prescaler_1_io_overflow),pkg_toStdLogicVector(pkg_toStdLogic(true)))) /= pkg_stdLogicVector("00")); + process(io_apb_PADDR,busCtrl_doWrite,io_apb_PWDATA) + begin + interruptCtrl_1_io_clears <= pkg_stdLogicVector("00"); + case io_apb_PADDR is + when "00010000" => + if busCtrl_doWrite = '1' then + interruptCtrl_1_io_clears <= pkg_extract(io_apb_PWDATA,1,0); + end if; + when others => + end case; + end process; + + process(timerA_io_full,timerB_io_full) + begin + interruptCtrl_1_io_inputs(0) <= timerA_io_full; + interruptCtrl_1_io_inputs(1) <= timerB_io_full; + end process; + + io_interrupt <= pkg_toStdLogic(interruptCtrl_1_io_pendings /= pkg_stdLogicVector("00")); + process(io_mainClk, resetCtrl_systemReset) + begin + if resetCtrl_systemReset = '1' then + timerABridge_ticksEnable <= pkg_stdLogicVector("00"); + timerABridge_clearsEnable <= pkg_stdLogicVector("0"); + timerBBridge_ticksEnable <= pkg_stdLogicVector("00"); + timerBBridge_clearsEnable <= pkg_stdLogicVector("0"); + interruptCtrl_1_io_masks_driver <= pkg_stdLogicVector("00"); + elsif rising_edge(io_mainClk) then + case io_apb_PADDR is + when "01000000" => + if busCtrl_doWrite = '1' then + timerABridge_ticksEnable <= pkg_extract(io_apb_PWDATA,1,0); + timerABridge_clearsEnable <= pkg_extract(io_apb_PWDATA,16,16); + end if; + when "01010000" => + if busCtrl_doWrite = '1' then + timerBBridge_ticksEnable <= pkg_extract(io_apb_PWDATA,1,0); + timerBBridge_clearsEnable <= pkg_extract(io_apb_PWDATA,16,16); + end if; + when "00010100" => + if busCtrl_doWrite = '1' then + interruptCtrl_1_io_masks_driver <= pkg_extract(io_apb_PWDATA,1,0); + end if; + when others => + end case; + end if; + end process; + + process(io_mainClk) + begin + if rising_edge(io_mainClk) then + case io_apb_PADDR is + when "00000000" => + if busCtrl_doWrite = '1' then + zz_io_limit <= unsigned(pkg_extract(io_apb_PWDATA,15,0)); + end if; + when "01000100" => + if busCtrl_doWrite = '1' then + timerA_io_limit_driver <= unsigned(pkg_extract(io_apb_PWDATA,15,0)); + end if; + when "01010100" => + if busCtrl_doWrite = '1' then + timerB_io_limit_driver <= unsigned(pkg_extract(io_apb_PWDATA,15,0)); + end if; + when others => + end case; + end if; + end process; + +end arch; + +library ieee; +use ieee.std_logic_1164.all; +use ieee.numeric_std.all; + +library work; +use work.pkg_scala2hdl.all; +use work.all; +use work.pkg_enum.all; + + +entity Apb3Decoder is + port( + io_input_PADDR : in unsigned(19 downto 0); + io_input_PSEL : in std_logic_vector(0 downto 0); + io_input_PENABLE : in std_logic; + io_input_PREADY : out std_logic; + io_input_PWRITE : in std_logic; + io_input_PWDATA : in std_logic_vector(31 downto 0); + io_input_PRDATA : out std_logic_vector(31 downto 0); + io_input_PSLVERROR : out std_logic; + io_output_PADDR : out unsigned(19 downto 0); + io_output_PSEL : out std_logic_vector(2 downto 0); + io_output_PENABLE : out std_logic; + io_output_PREADY : in std_logic; + io_output_PWRITE : out std_logic; + io_output_PWDATA : out std_logic_vector(31 downto 0); + io_output_PRDATA : in std_logic_vector(31 downto 0); + io_output_PSLVERROR : in std_logic + ); +end Apb3Decoder; + +architecture arch of Apb3Decoder is + signal io_output_PSEL_read_buffer : std_logic_vector(2 downto 0); + + signal when_Apb3Decoder_l88 : std_logic; +begin + io_output_PSEL <= io_output_PSEL_read_buffer; + io_output_PADDR <= io_input_PADDR; + io_output_PENABLE <= io_input_PENABLE; + io_output_PWRITE <= io_input_PWRITE; + io_output_PWDATA <= io_input_PWDATA; + process(io_input_PADDR,io_input_PSEL) + begin + io_output_PSEL_read_buffer(0) <= (pkg_toStdLogic((io_input_PADDR and pkg_not(pkg_unsigned("00000000111111111111"))) = pkg_unsigned("00000000000000000000")) and pkg_extract(io_input_PSEL,0)); + io_output_PSEL_read_buffer(1) <= (pkg_toStdLogic((io_input_PADDR and pkg_not(pkg_unsigned("00000000111111111111"))) = pkg_unsigned("00010000000000000000")) and pkg_extract(io_input_PSEL,0)); + io_output_PSEL_read_buffer(2) <= (pkg_toStdLogic((io_input_PADDR and pkg_not(pkg_unsigned("00000000111111111111"))) = pkg_unsigned("00100000000000000000")) and pkg_extract(io_input_PSEL,0)); + end process; + + process(io_output_PREADY,when_Apb3Decoder_l88) + begin + io_input_PREADY <= io_output_PREADY; + if when_Apb3Decoder_l88 = '1' then + io_input_PREADY <= pkg_toStdLogic(true); + end if; + end process; + + io_input_PRDATA <= io_output_PRDATA; + process(io_output_PSLVERROR,when_Apb3Decoder_l88) + begin + io_input_PSLVERROR <= io_output_PSLVERROR; + if when_Apb3Decoder_l88 = '1' then + io_input_PSLVERROR <= pkg_toStdLogic(true); + end if; + end process; + + when_Apb3Decoder_l88 <= (pkg_extract(io_input_PSEL,0) and pkg_toStdLogic(io_output_PSEL_read_buffer = pkg_stdLogicVector("000"))); +end arch; + +library ieee; +use ieee.std_logic_1164.all; +use ieee.numeric_std.all; + +library work; +use work.pkg_scala2hdl.all; +use work.all; +use work.pkg_enum.all; + + +entity Apb3Router is + port( + io_input_PADDR : in unsigned(19 downto 0); + io_input_PSEL : in std_logic_vector(2 downto 0); + io_input_PENABLE : in std_logic; + io_input_PREADY : out std_logic; + io_input_PWRITE : in std_logic; + io_input_PWDATA : in std_logic_vector(31 downto 0); + io_input_PRDATA : out std_logic_vector(31 downto 0); + io_input_PSLVERROR : out std_logic; + io_outputs_0_PADDR : out unsigned(19 downto 0); + io_outputs_0_PSEL : out std_logic_vector(0 downto 0); + io_outputs_0_PENABLE : out std_logic; + io_outputs_0_PREADY : in std_logic; + io_outputs_0_PWRITE : out std_logic; + io_outputs_0_PWDATA : out std_logic_vector(31 downto 0); + io_outputs_0_PRDATA : in std_logic_vector(31 downto 0); + io_outputs_0_PSLVERROR : in std_logic; + io_outputs_1_PADDR : out unsigned(19 downto 0); + io_outputs_1_PSEL : out std_logic_vector(0 downto 0); + io_outputs_1_PENABLE : out std_logic; + io_outputs_1_PREADY : in std_logic; + io_outputs_1_PWRITE : out std_logic; + io_outputs_1_PWDATA : out std_logic_vector(31 downto 0); + io_outputs_1_PRDATA : in std_logic_vector(31 downto 0); + io_outputs_1_PSLVERROR : in std_logic; + io_outputs_2_PADDR : out unsigned(19 downto 0); + io_outputs_2_PSEL : out std_logic_vector(0 downto 0); + io_outputs_2_PENABLE : out std_logic; + io_outputs_2_PREADY : in std_logic; + io_outputs_2_PWRITE : out std_logic; + io_outputs_2_PWDATA : out std_logic_vector(31 downto 0); + io_outputs_2_PRDATA : in std_logic_vector(31 downto 0); + io_outputs_2_PSLVERROR : in std_logic; + io_mainClk : in std_logic; + resetCtrl_systemReset : in std_logic + ); +end Apb3Router; + +architecture arch of Apb3Router is + signal zz_io_input_PREADY : std_logic; + signal zz_io_input_PRDATA : std_logic_vector(31 downto 0); + signal zz_io_input_PSLVERROR : std_logic; + + signal zz_selIndex : std_logic; + signal zz_selIndex_1 : std_logic; + signal selIndex : unsigned(1 downto 0); +begin + process(selIndex,io_outputs_0_PREADY,io_outputs_0_PRDATA,io_outputs_0_PSLVERROR,io_outputs_1_PREADY,io_outputs_1_PRDATA,io_outputs_1_PSLVERROR,io_outputs_2_PREADY,io_outputs_2_PRDATA,io_outputs_2_PSLVERROR) + begin + case selIndex is + when "00" => + zz_io_input_PREADY <= io_outputs_0_PREADY; + zz_io_input_PRDATA <= io_outputs_0_PRDATA; + zz_io_input_PSLVERROR <= io_outputs_0_PSLVERROR; + when "01" => + zz_io_input_PREADY <= io_outputs_1_PREADY; + zz_io_input_PRDATA <= io_outputs_1_PRDATA; + zz_io_input_PSLVERROR <= io_outputs_1_PSLVERROR; + when others => + zz_io_input_PREADY <= io_outputs_2_PREADY; + zz_io_input_PRDATA <= io_outputs_2_PRDATA; + zz_io_input_PSLVERROR <= io_outputs_2_PSLVERROR; + end case; + end process; + + io_outputs_0_PADDR <= io_input_PADDR; + io_outputs_0_PENABLE <= io_input_PENABLE; + io_outputs_0_PSEL(0) <= pkg_extract(io_input_PSEL,0); + io_outputs_0_PWRITE <= io_input_PWRITE; + io_outputs_0_PWDATA <= io_input_PWDATA; + io_outputs_1_PADDR <= io_input_PADDR; + io_outputs_1_PENABLE <= io_input_PENABLE; + io_outputs_1_PSEL(0) <= pkg_extract(io_input_PSEL,1); + io_outputs_1_PWRITE <= io_input_PWRITE; + io_outputs_1_PWDATA <= io_input_PWDATA; + io_outputs_2_PADDR <= io_input_PADDR; + io_outputs_2_PENABLE <= io_input_PENABLE; + io_outputs_2_PSEL(0) <= pkg_extract(io_input_PSEL,2); + io_outputs_2_PWRITE <= io_input_PWRITE; + io_outputs_2_PWDATA <= io_input_PWDATA; + zz_selIndex <= pkg_extract(io_input_PSEL,1); + zz_selIndex_1 <= pkg_extract(io_input_PSEL,2); + io_input_PREADY <= zz_io_input_PREADY; + io_input_PRDATA <= zz_io_input_PRDATA; + io_input_PSLVERROR <= zz_io_input_PSLVERROR; + process(io_mainClk) + begin + if rising_edge(io_mainClk) then + selIndex <= unsigned(pkg_cat(pkg_toStdLogicVector(zz_selIndex_1),pkg_toStdLogicVector(zz_selIndex))); + end if; + end process; + +end arch; + +library ieee; +use ieee.std_logic_1164.all; +use ieee.numeric_std.all; + +library work; +use work.pkg_scala2hdl.all; +use work.all; +use work.pkg_enum.all; + + +entity Murax is + port( + io_asyncReset : in std_logic; + io_mainClk : in std_logic; + io_jtag_tms : in std_logic; + io_jtag_tdi : in std_logic; + io_jtag_tdo : out std_logic; + io_jtag_tck : in std_logic; + io_gpioA_read : in std_logic_vector(31 downto 0); + io_gpioA_write : out std_logic_vector(31 downto 0); + io_gpioA_writeEnable : out std_logic_vector(31 downto 0); + io_uart_txd : out std_logic; + io_uart_rxd : in std_logic + ); +end Murax; + +architecture arch of Murax is + signal system_cpu_debug_bus_cmd_payload_address : unsigned(7 downto 0); + signal system_cpu_dBus_cmd_ready : std_logic; + signal system_ram_io_bus_cmd_valid : std_logic; + signal system_apbBridge_io_pipelinedMemoryBus_cmd_valid : std_logic; + signal system_gpioACtrl_io_apb_PADDR : unsigned(3 downto 0); + signal system_uartCtrl_io_apb_PADDR : unsigned(4 downto 0); + signal system_timer_io_apb_PADDR : unsigned(7 downto 0); + signal io_asyncReset_buffercc_io_dataOut : std_logic; + signal system_mainBusArbiter_io_iBus_cmd_ready : std_logic; + signal system_mainBusArbiter_io_iBus_rsp_valid : std_logic; + signal system_mainBusArbiter_io_iBus_rsp_payload_error : std_logic; + signal system_mainBusArbiter_io_iBus_rsp_payload_inst : std_logic_vector(31 downto 0); + signal system_mainBusArbiter_io_dBus_cmd_ready : std_logic; + signal system_mainBusArbiter_io_dBus_rsp_ready : std_logic; + signal system_mainBusArbiter_io_dBus_rsp_error : std_logic; + signal system_mainBusArbiter_io_dBus_rsp_data : std_logic_vector(31 downto 0); + signal system_mainBusArbiter_io_masterBus_cmd_valid : std_logic; + signal system_mainBusArbiter_io_masterBus_cmd_payload_write : std_logic; + signal system_mainBusArbiter_io_masterBus_cmd_payload_address : unsigned(31 downto 0); + signal system_mainBusArbiter_io_masterBus_cmd_payload_data : std_logic_vector(31 downto 0); + signal system_mainBusArbiter_io_masterBus_cmd_payload_mask : std_logic_vector(3 downto 0); + signal system_cpu_iBus_cmd_valid : std_logic; + signal system_cpu_iBus_cmd_payload_pc : unsigned(31 downto 0); + signal system_cpu_debug_bus_cmd_ready : std_logic; + signal system_cpu_debug_bus_rsp_data : std_logic_vector(31 downto 0); + signal system_cpu_debug_resetOut : std_logic; + signal system_cpu_dBus_cmd_valid : std_logic; + signal system_cpu_dBus_cmd_payload_wr : std_logic; + signal system_cpu_dBus_cmd_payload_address : unsigned(31 downto 0); + signal system_cpu_dBus_cmd_payload_data : std_logic_vector(31 downto 0); + signal system_cpu_dBus_cmd_payload_size : unsigned(1 downto 0); + signal jtagBridge_1_io_jtag_tdo : std_logic; + signal jtagBridge_1_io_remote_cmd_valid : std_logic; + signal jtagBridge_1_io_remote_cmd_payload_last : std_logic; + signal jtagBridge_1_io_remote_cmd_payload_fragment : std_logic_vector(0 downto 0); + signal jtagBridge_1_io_remote_rsp_ready : std_logic; + signal systemDebugger_1_io_remote_cmd_ready : std_logic; + signal systemDebugger_1_io_remote_rsp_valid : std_logic; + signal systemDebugger_1_io_remote_rsp_payload_error : std_logic; + signal systemDebugger_1_io_remote_rsp_payload_data : std_logic_vector(31 downto 0); + signal systemDebugger_1_io_mem_cmd_valid : std_logic; + signal systemDebugger_1_io_mem_cmd_payload_address : unsigned(31 downto 0); + signal systemDebugger_1_io_mem_cmd_payload_data : std_logic_vector(31 downto 0); + signal systemDebugger_1_io_mem_cmd_payload_wr : std_logic; + signal systemDebugger_1_io_mem_cmd_payload_size : unsigned(1 downto 0); + signal system_ram_io_bus_cmd_ready : std_logic; + signal system_ram_io_bus_rsp_valid : std_logic; + signal system_ram_io_bus_rsp_payload_data : std_logic_vector(31 downto 0); + signal system_apbBridge_io_pipelinedMemoryBus_cmd_ready : std_logic; + signal system_apbBridge_io_pipelinedMemoryBus_rsp_valid : std_logic; + signal system_apbBridge_io_pipelinedMemoryBus_rsp_payload_data : std_logic_vector(31 downto 0); + signal system_apbBridge_io_apb_PADDR : unsigned(19 downto 0); + signal system_apbBridge_io_apb_PSEL : std_logic_vector(0 downto 0); + signal system_apbBridge_io_apb_PENABLE : std_logic; + signal system_apbBridge_io_apb_PWRITE : std_logic; + signal system_apbBridge_io_apb_PWDATA : std_logic_vector(31 downto 0); + signal system_gpioACtrl_io_apb_PREADY : std_logic; + signal system_gpioACtrl_io_apb_PRDATA : std_logic_vector(31 downto 0); + signal system_gpioACtrl_io_apb_PSLVERROR : std_logic; + signal system_gpioACtrl_io_gpio_write : std_logic_vector(31 downto 0); + signal system_gpioACtrl_io_gpio_writeEnable : std_logic_vector(31 downto 0); + signal system_gpioACtrl_io_value : std_logic_vector(31 downto 0); + signal system_uartCtrl_io_apb_PREADY : std_logic; + signal system_uartCtrl_io_apb_PRDATA : std_logic_vector(31 downto 0); + signal system_uartCtrl_io_uart_txd : std_logic; + signal system_uartCtrl_io_interrupt : std_logic; + signal system_timer_io_apb_PREADY : std_logic; + signal system_timer_io_apb_PRDATA : std_logic_vector(31 downto 0); + signal system_timer_io_apb_PSLVERROR : std_logic; + signal system_timer_io_interrupt : std_logic; + signal io_apb_decoder_io_input_PREADY : std_logic; + signal io_apb_decoder_io_input_PRDATA : std_logic_vector(31 downto 0); + signal io_apb_decoder_io_input_PSLVERROR : std_logic; + signal io_apb_decoder_io_output_PADDR : unsigned(19 downto 0); + signal io_apb_decoder_io_output_PSEL : std_logic_vector(2 downto 0); + signal io_apb_decoder_io_output_PENABLE : std_logic; + signal io_apb_decoder_io_output_PWRITE : std_logic; + signal io_apb_decoder_io_output_PWDATA : std_logic_vector(31 downto 0); + signal apb3Router_1_io_input_PREADY : std_logic; + signal apb3Router_1_io_input_PRDATA : std_logic_vector(31 downto 0); + signal apb3Router_1_io_input_PSLVERROR : std_logic; + signal apb3Router_1_io_outputs_0_PADDR : unsigned(19 downto 0); + signal apb3Router_1_io_outputs_0_PSEL : std_logic_vector(0 downto 0); + signal apb3Router_1_io_outputs_0_PENABLE : std_logic; + signal apb3Router_1_io_outputs_0_PWRITE : std_logic; + signal apb3Router_1_io_outputs_0_PWDATA : std_logic_vector(31 downto 0); + signal apb3Router_1_io_outputs_1_PADDR : unsigned(19 downto 0); + signal apb3Router_1_io_outputs_1_PSEL : std_logic_vector(0 downto 0); + signal apb3Router_1_io_outputs_1_PENABLE : std_logic; + signal apb3Router_1_io_outputs_1_PWRITE : std_logic; + signal apb3Router_1_io_outputs_1_PWDATA : std_logic_vector(31 downto 0); + signal apb3Router_1_io_outputs_2_PADDR : unsigned(19 downto 0); + signal apb3Router_1_io_outputs_2_PSEL : std_logic_vector(0 downto 0); + signal apb3Router_1_io_outputs_2_PENABLE : std_logic; + signal apb3Router_1_io_outputs_2_PWRITE : std_logic; + signal apb3Router_1_io_outputs_2_PWDATA : std_logic_vector(31 downto 0); + signal zz_system_mainBusDecoder_logic_masterPipelined_rsp_payload_data : std_logic_vector(31 downto 0); + + signal resetCtrl_mainClkResetUnbuffered : std_logic; + signal resetCtrl_systemClkResetCounter : unsigned(5 downto 0) := pkg_unsigned("000000"); + signal zz_when_Murax_l188 : unsigned(5 downto 0); + signal when_Murax_l188 : std_logic; + signal when_Murax_l192 : std_logic; + signal resetCtrl_mainClkReset : std_logic; + signal resetCtrl_systemReset : std_logic; + signal system_timerInterrupt : std_logic; + signal system_externalInterrupt : std_logic; + signal system_cpu_dBus_cmd_halfPipe_valid : std_logic; + signal system_cpu_dBus_cmd_halfPipe_ready : std_logic; + signal system_cpu_dBus_cmd_halfPipe_payload_wr : std_logic; + signal system_cpu_dBus_cmd_halfPipe_payload_address : unsigned(31 downto 0); + signal system_cpu_dBus_cmd_halfPipe_payload_data : std_logic_vector(31 downto 0); + signal system_cpu_dBus_cmd_halfPipe_payload_size : unsigned(1 downto 0); + signal system_cpu_dBus_cmd_rValid : std_logic; + signal system_cpu_dBus_cmd_halfPipe_fire : std_logic; + signal system_cpu_dBus_cmd_rData_wr : std_logic; + signal system_cpu_dBus_cmd_rData_address : unsigned(31 downto 0); + signal system_cpu_dBus_cmd_rData_data : std_logic_vector(31 downto 0); + signal system_cpu_dBus_cmd_rData_size : unsigned(1 downto 0); + signal system_cpu_debug_resetOut_regNext : std_logic; + signal system_cpu_debug_bus_cmd_fire : std_logic; + signal system_cpu_debug_bus_cmd_fire_regNext : std_logic; + signal system_mainBusDecoder_logic_masterPipelined_cmd_valid : std_logic; + signal system_mainBusDecoder_logic_masterPipelined_cmd_ready : std_logic; + signal system_mainBusDecoder_logic_masterPipelined_cmd_payload_write : std_logic; + signal system_mainBusDecoder_logic_masterPipelined_cmd_payload_address : unsigned(31 downto 0); + signal system_mainBusDecoder_logic_masterPipelined_cmd_payload_data : std_logic_vector(31 downto 0); + signal system_mainBusDecoder_logic_masterPipelined_cmd_payload_mask : std_logic_vector(3 downto 0); + signal system_mainBusDecoder_logic_masterPipelined_rsp_valid : std_logic; + signal system_mainBusDecoder_logic_masterPipelined_rsp_payload_data : std_logic_vector(31 downto 0); + signal system_mainBusDecoder_logic_hits_0 : std_logic; + signal zz_io_bus_cmd_payload_write : std_logic; + signal system_mainBusDecoder_logic_hits_1 : std_logic; + signal zz_io_pipelinedMemoryBus_cmd_payload_write : std_logic; + signal system_mainBusDecoder_logic_noHit : std_logic; + signal system_mainBusDecoder_logic_rspPending : std_logic; + signal system_mainBusDecoder_logic_masterPipelined_cmd_fire : std_logic; + signal when_MuraxUtiles_l127 : std_logic; + signal system_mainBusDecoder_logic_rspNoHit : std_logic; + signal system_mainBusDecoder_logic_masterPipelined_cmd_fire_1 : std_logic; + signal system_mainBusDecoder_logic_rspSourceId : unsigned(0 downto 0); + signal when_MuraxUtiles_l133 : std_logic; +begin + io_asyncReset_buffercc : entity work.BufferCC_3 + port map ( + io_dataIn => io_asyncReset, + io_dataOut => io_asyncReset_buffercc_io_dataOut, + io_mainClk => io_mainClk + ); + system_mainBusArbiter : entity work.MuraxMasterArbiter + port map ( + io_iBus_cmd_valid => system_cpu_iBus_cmd_valid, + io_iBus_cmd_ready => system_mainBusArbiter_io_iBus_cmd_ready, + io_iBus_cmd_payload_pc => system_cpu_iBus_cmd_payload_pc, + io_iBus_rsp_valid => system_mainBusArbiter_io_iBus_rsp_valid, + io_iBus_rsp_payload_error => system_mainBusArbiter_io_iBus_rsp_payload_error, + io_iBus_rsp_payload_inst => system_mainBusArbiter_io_iBus_rsp_payload_inst, + io_dBus_cmd_valid => system_cpu_dBus_cmd_halfPipe_valid, + io_dBus_cmd_ready => system_mainBusArbiter_io_dBus_cmd_ready, + io_dBus_cmd_payload_wr => system_cpu_dBus_cmd_halfPipe_payload_wr, + io_dBus_cmd_payload_address => system_cpu_dBus_cmd_halfPipe_payload_address, + io_dBus_cmd_payload_data => system_cpu_dBus_cmd_halfPipe_payload_data, + io_dBus_cmd_payload_size => system_cpu_dBus_cmd_halfPipe_payload_size, + io_dBus_rsp_ready => system_mainBusArbiter_io_dBus_rsp_ready, + io_dBus_rsp_error => system_mainBusArbiter_io_dBus_rsp_error, + io_dBus_rsp_data => system_mainBusArbiter_io_dBus_rsp_data, + io_masterBus_cmd_valid => system_mainBusArbiter_io_masterBus_cmd_valid, + io_masterBus_cmd_ready => system_mainBusDecoder_logic_masterPipelined_cmd_ready, + io_masterBus_cmd_payload_write => system_mainBusArbiter_io_masterBus_cmd_payload_write, + io_masterBus_cmd_payload_address => system_mainBusArbiter_io_masterBus_cmd_payload_address, + io_masterBus_cmd_payload_data => system_mainBusArbiter_io_masterBus_cmd_payload_data, + io_masterBus_cmd_payload_mask => system_mainBusArbiter_io_masterBus_cmd_payload_mask, + io_masterBus_rsp_valid => system_mainBusDecoder_logic_masterPipelined_rsp_valid, + io_masterBus_rsp_payload_data => system_mainBusDecoder_logic_masterPipelined_rsp_payload_data, + io_mainClk => io_mainClk, + resetCtrl_systemReset => resetCtrl_systemReset + ); + system_cpu : entity work.VexRiscv + port map ( + iBus_cmd_valid => system_cpu_iBus_cmd_valid, + iBus_cmd_ready => system_mainBusArbiter_io_iBus_cmd_ready, + iBus_cmd_payload_pc => system_cpu_iBus_cmd_payload_pc, + iBus_rsp_valid => system_mainBusArbiter_io_iBus_rsp_valid, + iBus_rsp_payload_error => system_mainBusArbiter_io_iBus_rsp_payload_error, + iBus_rsp_payload_inst => system_mainBusArbiter_io_iBus_rsp_payload_inst, + timerInterrupt => system_timerInterrupt, + externalInterrupt => system_externalInterrupt, + softwareInterrupt => pkg_toStdLogic(false), + debug_bus_cmd_valid => systemDebugger_1_io_mem_cmd_valid, + debug_bus_cmd_ready => system_cpu_debug_bus_cmd_ready, + debug_bus_cmd_payload_wr => systemDebugger_1_io_mem_cmd_payload_wr, + debug_bus_cmd_payload_address => system_cpu_debug_bus_cmd_payload_address, + debug_bus_cmd_payload_data => systemDebugger_1_io_mem_cmd_payload_data, + debug_bus_rsp_data => system_cpu_debug_bus_rsp_data, + debug_resetOut => system_cpu_debug_resetOut, + dBus_cmd_valid => system_cpu_dBus_cmd_valid, + dBus_cmd_ready => system_cpu_dBus_cmd_ready, + dBus_cmd_payload_wr => system_cpu_dBus_cmd_payload_wr, + dBus_cmd_payload_address => system_cpu_dBus_cmd_payload_address, + dBus_cmd_payload_data => system_cpu_dBus_cmd_payload_data, + dBus_cmd_payload_size => system_cpu_dBus_cmd_payload_size, + dBus_rsp_ready => system_mainBusArbiter_io_dBus_rsp_ready, + dBus_rsp_error => system_mainBusArbiter_io_dBus_rsp_error, + dBus_rsp_data => system_mainBusArbiter_io_dBus_rsp_data, + io_mainClk => io_mainClk, + resetCtrl_systemReset => resetCtrl_systemReset, + resetCtrl_mainClkReset => resetCtrl_mainClkReset + ); + jtagBridge_1 : entity work.JtagBridge + port map ( + io_jtag_tms => io_jtag_tms, + io_jtag_tdi => io_jtag_tdi, + io_jtag_tdo => jtagBridge_1_io_jtag_tdo, + io_jtag_tck => io_jtag_tck, + io_remote_cmd_valid => jtagBridge_1_io_remote_cmd_valid, + io_remote_cmd_ready => systemDebugger_1_io_remote_cmd_ready, + io_remote_cmd_payload_last => jtagBridge_1_io_remote_cmd_payload_last, + io_remote_cmd_payload_fragment => jtagBridge_1_io_remote_cmd_payload_fragment, + io_remote_rsp_valid => systemDebugger_1_io_remote_rsp_valid, + io_remote_rsp_ready => jtagBridge_1_io_remote_rsp_ready, + io_remote_rsp_payload_error => systemDebugger_1_io_remote_rsp_payload_error, + io_remote_rsp_payload_data => systemDebugger_1_io_remote_rsp_payload_data, + io_mainClk => io_mainClk, + resetCtrl_mainClkReset => resetCtrl_mainClkReset + ); + systemDebugger_1 : entity work.SystemDebugger + port map ( + io_remote_cmd_valid => jtagBridge_1_io_remote_cmd_valid, + io_remote_cmd_ready => systemDebugger_1_io_remote_cmd_ready, + io_remote_cmd_payload_last => jtagBridge_1_io_remote_cmd_payload_last, + io_remote_cmd_payload_fragment => jtagBridge_1_io_remote_cmd_payload_fragment, + io_remote_rsp_valid => systemDebugger_1_io_remote_rsp_valid, + io_remote_rsp_ready => jtagBridge_1_io_remote_rsp_ready, + io_remote_rsp_payload_error => systemDebugger_1_io_remote_rsp_payload_error, + io_remote_rsp_payload_data => systemDebugger_1_io_remote_rsp_payload_data, + io_mem_cmd_valid => systemDebugger_1_io_mem_cmd_valid, + io_mem_cmd_ready => system_cpu_debug_bus_cmd_ready, + io_mem_cmd_payload_address => systemDebugger_1_io_mem_cmd_payload_address, + io_mem_cmd_payload_data => systemDebugger_1_io_mem_cmd_payload_data, + io_mem_cmd_payload_wr => systemDebugger_1_io_mem_cmd_payload_wr, + io_mem_cmd_payload_size => systemDebugger_1_io_mem_cmd_payload_size, + io_mem_rsp_valid => system_cpu_debug_bus_cmd_fire_regNext, + io_mem_rsp_payload => system_cpu_debug_bus_rsp_data, + io_mainClk => io_mainClk, + resetCtrl_mainClkReset => resetCtrl_mainClkReset + ); + system_ram : entity work.MuraxPipelinedMemoryBusRam + port map ( + io_bus_cmd_valid => system_ram_io_bus_cmd_valid, + io_bus_cmd_ready => system_ram_io_bus_cmd_ready, + io_bus_cmd_payload_write => zz_io_bus_cmd_payload_write, + io_bus_cmd_payload_address => system_mainBusDecoder_logic_masterPipelined_cmd_payload_address, + io_bus_cmd_payload_data => system_mainBusDecoder_logic_masterPipelined_cmd_payload_data, + io_bus_cmd_payload_mask => system_mainBusDecoder_logic_masterPipelined_cmd_payload_mask, + io_bus_rsp_valid => system_ram_io_bus_rsp_valid, + io_bus_rsp_payload_data => system_ram_io_bus_rsp_payload_data, + io_mainClk => io_mainClk, + resetCtrl_systemReset => resetCtrl_systemReset + ); + system_apbBridge : entity work.PipelinedMemoryBusToApbBridge + port map ( + io_pipelinedMemoryBus_cmd_valid => system_apbBridge_io_pipelinedMemoryBus_cmd_valid, + io_pipelinedMemoryBus_cmd_ready => system_apbBridge_io_pipelinedMemoryBus_cmd_ready, + io_pipelinedMemoryBus_cmd_payload_write => zz_io_pipelinedMemoryBus_cmd_payload_write, + io_pipelinedMemoryBus_cmd_payload_address => system_mainBusDecoder_logic_masterPipelined_cmd_payload_address, + io_pipelinedMemoryBus_cmd_payload_data => system_mainBusDecoder_logic_masterPipelined_cmd_payload_data, + io_pipelinedMemoryBus_cmd_payload_mask => system_mainBusDecoder_logic_masterPipelined_cmd_payload_mask, + io_pipelinedMemoryBus_rsp_valid => system_apbBridge_io_pipelinedMemoryBus_rsp_valid, + io_pipelinedMemoryBus_rsp_payload_data => system_apbBridge_io_pipelinedMemoryBus_rsp_payload_data, + io_apb_PADDR => system_apbBridge_io_apb_PADDR, + io_apb_PSEL => system_apbBridge_io_apb_PSEL, + io_apb_PENABLE => system_apbBridge_io_apb_PENABLE, + io_apb_PREADY => io_apb_decoder_io_input_PREADY, + io_apb_PWRITE => system_apbBridge_io_apb_PWRITE, + io_apb_PWDATA => system_apbBridge_io_apb_PWDATA, + io_apb_PRDATA => io_apb_decoder_io_input_PRDATA, + io_apb_PSLVERROR => io_apb_decoder_io_input_PSLVERROR, + io_mainClk => io_mainClk, + resetCtrl_systemReset => resetCtrl_systemReset + ); + system_gpioACtrl : entity work.Apb3Gpio + port map ( + io_apb_PADDR => system_gpioACtrl_io_apb_PADDR, + io_apb_PSEL => apb3Router_1_io_outputs_0_PSEL, + io_apb_PENABLE => apb3Router_1_io_outputs_0_PENABLE, + io_apb_PREADY => system_gpioACtrl_io_apb_PREADY, + io_apb_PWRITE => apb3Router_1_io_outputs_0_PWRITE, + io_apb_PWDATA => apb3Router_1_io_outputs_0_PWDATA, + io_apb_PRDATA => system_gpioACtrl_io_apb_PRDATA, + io_apb_PSLVERROR => system_gpioACtrl_io_apb_PSLVERROR, + io_gpio_read => io_gpioA_read, + io_gpio_write => system_gpioACtrl_io_gpio_write, + io_gpio_writeEnable => system_gpioACtrl_io_gpio_writeEnable, + io_value => system_gpioACtrl_io_value, + io_mainClk => io_mainClk, + resetCtrl_systemReset => resetCtrl_systemReset + ); + system_uartCtrl : entity work.Apb3UartCtrl + port map ( + io_apb_PADDR => system_uartCtrl_io_apb_PADDR, + io_apb_PSEL => apb3Router_1_io_outputs_1_PSEL, + io_apb_PENABLE => apb3Router_1_io_outputs_1_PENABLE, + io_apb_PREADY => system_uartCtrl_io_apb_PREADY, + io_apb_PWRITE => apb3Router_1_io_outputs_1_PWRITE, + io_apb_PWDATA => apb3Router_1_io_outputs_1_PWDATA, + io_apb_PRDATA => system_uartCtrl_io_apb_PRDATA, + io_uart_txd => system_uartCtrl_io_uart_txd, + io_uart_rxd => io_uart_rxd, + io_interrupt => system_uartCtrl_io_interrupt, + io_mainClk => io_mainClk, + resetCtrl_systemReset => resetCtrl_systemReset + ); + system_timer : entity work.MuraxApb3Timer + port map ( + io_apb_PADDR => system_timer_io_apb_PADDR, + io_apb_PSEL => apb3Router_1_io_outputs_2_PSEL, + io_apb_PENABLE => apb3Router_1_io_outputs_2_PENABLE, + io_apb_PREADY => system_timer_io_apb_PREADY, + io_apb_PWRITE => apb3Router_1_io_outputs_2_PWRITE, + io_apb_PWDATA => apb3Router_1_io_outputs_2_PWDATA, + io_apb_PRDATA => system_timer_io_apb_PRDATA, + io_apb_PSLVERROR => system_timer_io_apb_PSLVERROR, + io_interrupt => system_timer_io_interrupt, + io_mainClk => io_mainClk, + resetCtrl_systemReset => resetCtrl_systemReset + ); + io_apb_decoder : entity work.Apb3Decoder + port map ( + io_input_PADDR => system_apbBridge_io_apb_PADDR, + io_input_PSEL => system_apbBridge_io_apb_PSEL, + io_input_PENABLE => system_apbBridge_io_apb_PENABLE, + io_input_PREADY => io_apb_decoder_io_input_PREADY, + io_input_PWRITE => system_apbBridge_io_apb_PWRITE, + io_input_PWDATA => system_apbBridge_io_apb_PWDATA, + io_input_PRDATA => io_apb_decoder_io_input_PRDATA, + io_input_PSLVERROR => io_apb_decoder_io_input_PSLVERROR, + io_output_PADDR => io_apb_decoder_io_output_PADDR, + io_output_PSEL => io_apb_decoder_io_output_PSEL, + io_output_PENABLE => io_apb_decoder_io_output_PENABLE, + io_output_PREADY => apb3Router_1_io_input_PREADY, + io_output_PWRITE => io_apb_decoder_io_output_PWRITE, + io_output_PWDATA => io_apb_decoder_io_output_PWDATA, + io_output_PRDATA => apb3Router_1_io_input_PRDATA, + io_output_PSLVERROR => apb3Router_1_io_input_PSLVERROR + ); + apb3Router_1 : entity work.Apb3Router + port map ( + io_input_PADDR => io_apb_decoder_io_output_PADDR, + io_input_PSEL => io_apb_decoder_io_output_PSEL, + io_input_PENABLE => io_apb_decoder_io_output_PENABLE, + io_input_PREADY => apb3Router_1_io_input_PREADY, + io_input_PWRITE => io_apb_decoder_io_output_PWRITE, + io_input_PWDATA => io_apb_decoder_io_output_PWDATA, + io_input_PRDATA => apb3Router_1_io_input_PRDATA, + io_input_PSLVERROR => apb3Router_1_io_input_PSLVERROR, + io_outputs_0_PADDR => apb3Router_1_io_outputs_0_PADDR, + io_outputs_0_PSEL => apb3Router_1_io_outputs_0_PSEL, + io_outputs_0_PENABLE => apb3Router_1_io_outputs_0_PENABLE, + io_outputs_0_PREADY => system_gpioACtrl_io_apb_PREADY, + io_outputs_0_PWRITE => apb3Router_1_io_outputs_0_PWRITE, + io_outputs_0_PWDATA => apb3Router_1_io_outputs_0_PWDATA, + io_outputs_0_PRDATA => system_gpioACtrl_io_apb_PRDATA, + io_outputs_0_PSLVERROR => system_gpioACtrl_io_apb_PSLVERROR, + io_outputs_1_PADDR => apb3Router_1_io_outputs_1_PADDR, + io_outputs_1_PSEL => apb3Router_1_io_outputs_1_PSEL, + io_outputs_1_PENABLE => apb3Router_1_io_outputs_1_PENABLE, + io_outputs_1_PREADY => system_uartCtrl_io_apb_PREADY, + io_outputs_1_PWRITE => apb3Router_1_io_outputs_1_PWRITE, + io_outputs_1_PWDATA => apb3Router_1_io_outputs_1_PWDATA, + io_outputs_1_PRDATA => system_uartCtrl_io_apb_PRDATA, + io_outputs_1_PSLVERROR => pkg_toStdLogic(false), + io_outputs_2_PADDR => apb3Router_1_io_outputs_2_PADDR, + io_outputs_2_PSEL => apb3Router_1_io_outputs_2_PSEL, + io_outputs_2_PENABLE => apb3Router_1_io_outputs_2_PENABLE, + io_outputs_2_PREADY => system_timer_io_apb_PREADY, + io_outputs_2_PWRITE => apb3Router_1_io_outputs_2_PWRITE, + io_outputs_2_PWDATA => apb3Router_1_io_outputs_2_PWDATA, + io_outputs_2_PRDATA => system_timer_io_apb_PRDATA, + io_outputs_2_PSLVERROR => system_timer_io_apb_PSLVERROR, + io_mainClk => io_mainClk, + resetCtrl_systemReset => resetCtrl_systemReset + ); + process(system_mainBusDecoder_logic_rspSourceId,system_ram_io_bus_rsp_payload_data,system_apbBridge_io_pipelinedMemoryBus_rsp_payload_data) + begin + case system_mainBusDecoder_logic_rspSourceId is + when "0" => + zz_system_mainBusDecoder_logic_masterPipelined_rsp_payload_data <= system_ram_io_bus_rsp_payload_data; + when others => + zz_system_mainBusDecoder_logic_masterPipelined_rsp_payload_data <= system_apbBridge_io_pipelinedMemoryBus_rsp_payload_data; + end case; + end process; + + process(when_Murax_l188) + begin + resetCtrl_mainClkResetUnbuffered <= pkg_toStdLogic(false); + if when_Murax_l188 = '1' then + resetCtrl_mainClkResetUnbuffered <= pkg_toStdLogic(true); + end if; + end process; + + zz_when_Murax_l188(5 downto 0) <= pkg_unsigned("111111"); + when_Murax_l188 <= pkg_toStdLogic(resetCtrl_systemClkResetCounter /= zz_when_Murax_l188); + when_Murax_l192 <= io_asyncReset_buffercc_io_dataOut; + process(system_timer_io_interrupt) + begin + system_timerInterrupt <= pkg_toStdLogic(false); + if system_timer_io_interrupt = '1' then + system_timerInterrupt <= pkg_toStdLogic(true); + end if; + end process; + + process(system_uartCtrl_io_interrupt) + begin + system_externalInterrupt <= pkg_toStdLogic(false); + if system_uartCtrl_io_interrupt = '1' then + system_externalInterrupt <= pkg_toStdLogic(true); + end if; + end process; + + system_cpu_dBus_cmd_halfPipe_fire <= (system_cpu_dBus_cmd_halfPipe_valid and system_cpu_dBus_cmd_halfPipe_ready); + system_cpu_dBus_cmd_ready <= (not system_cpu_dBus_cmd_rValid); + system_cpu_dBus_cmd_halfPipe_valid <= system_cpu_dBus_cmd_rValid; + system_cpu_dBus_cmd_halfPipe_payload_wr <= system_cpu_dBus_cmd_rData_wr; + system_cpu_dBus_cmd_halfPipe_payload_address <= system_cpu_dBus_cmd_rData_address; + system_cpu_dBus_cmd_halfPipe_payload_data <= system_cpu_dBus_cmd_rData_data; + system_cpu_dBus_cmd_halfPipe_payload_size <= system_cpu_dBus_cmd_rData_size; + system_cpu_dBus_cmd_halfPipe_ready <= system_mainBusArbiter_io_dBus_cmd_ready; + system_cpu_debug_bus_cmd_payload_address <= pkg_resize(systemDebugger_1_io_mem_cmd_payload_address,8); + system_cpu_debug_bus_cmd_fire <= (systemDebugger_1_io_mem_cmd_valid and system_cpu_debug_bus_cmd_ready); + io_jtag_tdo <= jtagBridge_1_io_jtag_tdo; + io_gpioA_write <= system_gpioACtrl_io_gpio_write; + io_gpioA_writeEnable <= system_gpioACtrl_io_gpio_writeEnable; + io_uart_txd <= system_uartCtrl_io_uart_txd; + system_gpioACtrl_io_apb_PADDR <= pkg_resize(apb3Router_1_io_outputs_0_PADDR,4); + system_uartCtrl_io_apb_PADDR <= pkg_resize(apb3Router_1_io_outputs_1_PADDR,5); + system_timer_io_apb_PADDR <= pkg_resize(apb3Router_1_io_outputs_2_PADDR,8); + system_mainBusDecoder_logic_masterPipelined_cmd_valid <= system_mainBusArbiter_io_masterBus_cmd_valid; + system_mainBusDecoder_logic_masterPipelined_cmd_payload_write <= system_mainBusArbiter_io_masterBus_cmd_payload_write; + system_mainBusDecoder_logic_masterPipelined_cmd_payload_address <= system_mainBusArbiter_io_masterBus_cmd_payload_address; + system_mainBusDecoder_logic_masterPipelined_cmd_payload_data <= system_mainBusArbiter_io_masterBus_cmd_payload_data; + system_mainBusDecoder_logic_masterPipelined_cmd_payload_mask <= system_mainBusArbiter_io_masterBus_cmd_payload_mask; + system_mainBusDecoder_logic_hits_0 <= pkg_toStdLogic((system_mainBusDecoder_logic_masterPipelined_cmd_payload_address and pkg_not(pkg_unsigned("00000000000000000000111111111111"))) = pkg_unsigned("10000000000000000000000000000000")); + process(system_mainBusDecoder_logic_masterPipelined_cmd_valid,system_mainBusDecoder_logic_hits_0,when_MuraxUtiles_l133) + begin + system_ram_io_bus_cmd_valid <= (system_mainBusDecoder_logic_masterPipelined_cmd_valid and system_mainBusDecoder_logic_hits_0); + if when_MuraxUtiles_l133 = '1' then + system_ram_io_bus_cmd_valid <= pkg_toStdLogic(false); + end if; + end process; + + zz_io_bus_cmd_payload_write <= system_mainBusDecoder_logic_masterPipelined_cmd_payload_write; + system_mainBusDecoder_logic_hits_1 <= pkg_toStdLogic((system_mainBusDecoder_logic_masterPipelined_cmd_payload_address and pkg_not(pkg_unsigned("00000000000011111111111111111111"))) = pkg_unsigned("11110000000000000000000000000000")); + process(system_mainBusDecoder_logic_masterPipelined_cmd_valid,system_mainBusDecoder_logic_hits_1,when_MuraxUtiles_l133) + begin + system_apbBridge_io_pipelinedMemoryBus_cmd_valid <= (system_mainBusDecoder_logic_masterPipelined_cmd_valid and system_mainBusDecoder_logic_hits_1); + if when_MuraxUtiles_l133 = '1' then + system_apbBridge_io_pipelinedMemoryBus_cmd_valid <= pkg_toStdLogic(false); + end if; + end process; + + zz_io_pipelinedMemoryBus_cmd_payload_write <= system_mainBusDecoder_logic_masterPipelined_cmd_payload_write; + system_mainBusDecoder_logic_noHit <= (not pkg_toStdLogic(pkg_cat(pkg_toStdLogicVector(system_mainBusDecoder_logic_hits_1),pkg_toStdLogicVector(system_mainBusDecoder_logic_hits_0)) /= pkg_stdLogicVector("00"))); + process(system_mainBusDecoder_logic_hits_1,system_apbBridge_io_pipelinedMemoryBus_cmd_ready,system_mainBusDecoder_logic_hits_0,system_ram_io_bus_cmd_ready,system_mainBusDecoder_logic_noHit,when_MuraxUtiles_l133) + begin + system_mainBusDecoder_logic_masterPipelined_cmd_ready <= (pkg_toStdLogic(pkg_cat(pkg_toStdLogicVector((system_mainBusDecoder_logic_hits_1 and system_apbBridge_io_pipelinedMemoryBus_cmd_ready)),pkg_toStdLogicVector((system_mainBusDecoder_logic_hits_0 and system_ram_io_bus_cmd_ready))) /= pkg_stdLogicVector("00")) or system_mainBusDecoder_logic_noHit); + if when_MuraxUtiles_l133 = '1' then + system_mainBusDecoder_logic_masterPipelined_cmd_ready <= pkg_toStdLogic(false); + end if; + end process; + + system_mainBusDecoder_logic_masterPipelined_cmd_fire <= (system_mainBusDecoder_logic_masterPipelined_cmd_valid and system_mainBusDecoder_logic_masterPipelined_cmd_ready); + when_MuraxUtiles_l127 <= (system_mainBusDecoder_logic_masterPipelined_cmd_fire and (not system_mainBusDecoder_logic_masterPipelined_cmd_payload_write)); + system_mainBusDecoder_logic_masterPipelined_cmd_fire_1 <= (system_mainBusDecoder_logic_masterPipelined_cmd_valid and system_mainBusDecoder_logic_masterPipelined_cmd_ready); + system_mainBusDecoder_logic_masterPipelined_rsp_valid <= (pkg_toStdLogic(pkg_cat(pkg_toStdLogicVector(system_apbBridge_io_pipelinedMemoryBus_rsp_valid),pkg_toStdLogicVector(system_ram_io_bus_rsp_valid)) /= pkg_stdLogicVector("00")) or (system_mainBusDecoder_logic_rspPending and system_mainBusDecoder_logic_rspNoHit)); + system_mainBusDecoder_logic_masterPipelined_rsp_payload_data <= zz_system_mainBusDecoder_logic_masterPipelined_rsp_payload_data; + when_MuraxUtiles_l133 <= (system_mainBusDecoder_logic_rspPending and (not system_mainBusDecoder_logic_masterPipelined_rsp_valid)); + process(io_mainClk) + begin + if rising_edge(io_mainClk) then + if when_Murax_l188 = '1' then + resetCtrl_systemClkResetCounter <= (resetCtrl_systemClkResetCounter + pkg_unsigned("000001")); + end if; + if when_Murax_l192 = '1' then + resetCtrl_systemClkResetCounter <= pkg_unsigned("000000"); + end if; + end if; + end process; + + process(io_mainClk) + begin + if rising_edge(io_mainClk) then + resetCtrl_mainClkReset <= resetCtrl_mainClkResetUnbuffered; + resetCtrl_systemReset <= resetCtrl_mainClkResetUnbuffered; + if system_cpu_debug_resetOut_regNext = '1' then + resetCtrl_systemReset <= pkg_toStdLogic(true); + end if; + end if; + end process; + + process(io_mainClk, resetCtrl_systemReset) + begin + if resetCtrl_systemReset = '1' then + system_cpu_dBus_cmd_rValid <= pkg_toStdLogic(false); + system_mainBusDecoder_logic_rspPending <= pkg_toStdLogic(false); + system_mainBusDecoder_logic_rspNoHit <= pkg_toStdLogic(false); + elsif rising_edge(io_mainClk) then + if system_cpu_dBus_cmd_valid = '1' then + system_cpu_dBus_cmd_rValid <= pkg_toStdLogic(true); + end if; + if system_cpu_dBus_cmd_halfPipe_fire = '1' then + system_cpu_dBus_cmd_rValid <= pkg_toStdLogic(false); + end if; + if system_mainBusDecoder_logic_masterPipelined_rsp_valid = '1' then + system_mainBusDecoder_logic_rspPending <= pkg_toStdLogic(false); + end if; + if when_MuraxUtiles_l127 = '1' then + system_mainBusDecoder_logic_rspPending <= pkg_toStdLogic(true); + end if; + system_mainBusDecoder_logic_rspNoHit <= pkg_toStdLogic(false); + if system_mainBusDecoder_logic_noHit = '1' then + system_mainBusDecoder_logic_rspNoHit <= pkg_toStdLogic(true); + end if; + end if; + end process; + + process(io_mainClk) + begin + if rising_edge(io_mainClk) then + if system_cpu_dBus_cmd_ready = '1' then + system_cpu_dBus_cmd_rData_wr <= system_cpu_dBus_cmd_payload_wr; + system_cpu_dBus_cmd_rData_address <= system_cpu_dBus_cmd_payload_address; + system_cpu_dBus_cmd_rData_data <= system_cpu_dBus_cmd_payload_data; + system_cpu_dBus_cmd_rData_size <= system_cpu_dBus_cmd_payload_size; + end if; + if system_mainBusDecoder_logic_masterPipelined_cmd_fire_1 = '1' then + system_mainBusDecoder_logic_rspSourceId <= unsigned(pkg_toStdLogicVector(system_mainBusDecoder_logic_hits_1)); + end if; + end if; + end process; + + process(io_mainClk) + begin + if rising_edge(io_mainClk) then + system_cpu_debug_resetOut_regNext <= system_cpu_debug_resetOut; + end if; + end process; + + process(io_mainClk, resetCtrl_mainClkReset) + begin + if resetCtrl_mainClkReset = '1' then + system_cpu_debug_bus_cmd_fire_regNext <= pkg_toStdLogic(false); + elsif rising_edge(io_mainClk) then + system_cpu_debug_bus_cmd_fire_regNext <= system_cpu_debug_bus_cmd_fire; + end if; + end process; + +end arch; + +library ieee; +use ieee.std_logic_1164.all; +use ieee.numeric_std.all; + +library work; +use work.pkg_scala2hdl.all; +use work.all; +use work.pkg_enum.all; + + +entity de1_murax_franz is + port( + jtag_tck : in std_logic; + jtag_tdi : in std_logic; + jtag_tdo : out std_logic; + jtag_tms : in std_logic; + uart_txd : out std_logic; + uart_rxd : in std_logic; + KEY0 : in std_logic; + CLOCK_50 : in std_logic; + LEDR : out std_logic_vector(7 downto 0) + ); +end de1_murax_franz; + +architecture arch of de1_murax_franz is + signal murax_1_io_asyncReset : std_logic; + signal murax_1_io_jtag_tdo : std_logic; + signal murax_1_io_gpioA_write : std_logic_vector(31 downto 0); + signal murax_1_io_gpioA_writeEnable : std_logic_vector(31 downto 0); + signal murax_1_io_uart_txd : std_logic; + +begin + murax_1 : entity work.Murax + port map ( + io_asyncReset => murax_1_io_asyncReset, + io_mainClk => CLOCK_50, + io_jtag_tms => jtag_tms, + io_jtag_tdi => jtag_tdi, + io_jtag_tdo => murax_1_io_jtag_tdo, + io_jtag_tck => jtag_tck, + io_gpioA_read => pkg_stdLogicVector("00000000000000000000000000000000"), + io_gpioA_write => murax_1_io_gpioA_write, + io_gpioA_writeEnable => murax_1_io_gpioA_writeEnable, + io_uart_txd => murax_1_io_uart_txd, + io_uart_rxd => uart_rxd + ); + LEDR <= pkg_extract(murax_1_io_gpioA_write,7,0); + jtag_tdo <= murax_1_io_jtag_tdo; + uart_txd <= murax_1_io_uart_txd; + murax_1_io_asyncReset <= (not KEY0); +end arch; + diff --git a/flow/designs/src/murax/murax_pkg.vhd b/flow/designs/src/murax/murax_pkg.vhd new file mode 100644 index 0000000000..3130086417 --- /dev/null +++ b/flow/designs/src/murax/murax_pkg.vhd @@ -0,0 +1,673 @@ +-- Generator : SpinalHDL v1.7.1 git head : 0444bb76ab1d6e19f0ec46bc03c4769776deb7d5 +-- Component : de1_murax_franz +-- Git hash : 24795ef09b88defe2ee1bb335e5caaf7e07e64ff + +library IEEE; +use IEEE.STD_LOGIC_1164.ALL; +use IEEE.NUMERIC_STD.all; + +package pkg_enum is + type BranchCtrlEnum is (INC,B,JAL,JALR); + type ShiftCtrlEnum is (DISABLE_1,SLL_1,SRL_1,SRA_1); + type AluBitwiseCtrlEnum is (XOR_1,OR_1,AND_1); + type AluCtrlEnum is (ADD_SUB,SLT_SLTU,BITWISE); + type EnvCtrlEnum is (NONE,XRET); + type Src2CtrlEnum is (RS,IMI,IMS,PC); + type Src1CtrlEnum is (RS,IMU,PC_INCREMENT,URS1); + type JtagState is (RESET,IDLE,IR_SELECT,IR_CAPTURE,IR_SHIFT,IR_EXIT1,IR_PAUSE,IR_EXIT2,IR_UPDATE,DR_SELECT,DR_CAPTURE,DR_SHIFT,DR_EXIT1,DR_PAUSE,DR_EXIT2,DR_UPDATE); + type UartStopType is (UART_ONE,TWO); + type UartParityType is (NONE,EVEN,ODD); + type UartCtrlTxState is (IDLE,START,DATA,PARITY,STOP); + type UartCtrlRxState is (IDLE,START,DATA,PARITY,STOP); + + function pkg_mux (sel : std_logic; one : BranchCtrlEnum; zero : BranchCtrlEnum) return BranchCtrlEnum; + subtype BranchCtrlEnum_seq_type is std_logic_vector(1 downto 0); + constant BranchCtrlEnum_seq_INC : BranchCtrlEnum_seq_type := "00"; + constant BranchCtrlEnum_seq_B : BranchCtrlEnum_seq_type := "01"; + constant BranchCtrlEnum_seq_JAL : BranchCtrlEnum_seq_type := "10"; + constant BranchCtrlEnum_seq_JALR : BranchCtrlEnum_seq_type := "11"; + + function pkg_mux (sel : std_logic; one : ShiftCtrlEnum; zero : ShiftCtrlEnum) return ShiftCtrlEnum; + subtype ShiftCtrlEnum_seq_type is std_logic_vector(1 downto 0); + constant ShiftCtrlEnum_seq_DISABLE_1 : ShiftCtrlEnum_seq_type := "00"; + constant ShiftCtrlEnum_seq_SLL_1 : ShiftCtrlEnum_seq_type := "01"; + constant ShiftCtrlEnum_seq_SRL_1 : ShiftCtrlEnum_seq_type := "10"; + constant ShiftCtrlEnum_seq_SRA_1 : ShiftCtrlEnum_seq_type := "11"; + + function pkg_mux (sel : std_logic; one : AluBitwiseCtrlEnum; zero : AluBitwiseCtrlEnum) return AluBitwiseCtrlEnum; + subtype AluBitwiseCtrlEnum_seq_type is std_logic_vector(1 downto 0); + constant AluBitwiseCtrlEnum_seq_XOR_1 : AluBitwiseCtrlEnum_seq_type := "00"; + constant AluBitwiseCtrlEnum_seq_OR_1 : AluBitwiseCtrlEnum_seq_type := "01"; + constant AluBitwiseCtrlEnum_seq_AND_1 : AluBitwiseCtrlEnum_seq_type := "10"; + + function pkg_mux (sel : std_logic; one : AluCtrlEnum; zero : AluCtrlEnum) return AluCtrlEnum; + subtype AluCtrlEnum_seq_type is std_logic_vector(1 downto 0); + constant AluCtrlEnum_seq_ADD_SUB : AluCtrlEnum_seq_type := "00"; + constant AluCtrlEnum_seq_SLT_SLTU : AluCtrlEnum_seq_type := "01"; + constant AluCtrlEnum_seq_BITWISE : AluCtrlEnum_seq_type := "10"; + + function pkg_mux (sel : std_logic; one : EnvCtrlEnum; zero : EnvCtrlEnum) return EnvCtrlEnum; + subtype EnvCtrlEnum_seq_type is std_logic_vector(0 downto 0); + constant EnvCtrlEnum_seq_NONE : EnvCtrlEnum_seq_type := "0"; + constant EnvCtrlEnum_seq_XRET : EnvCtrlEnum_seq_type := "1"; + + function pkg_mux (sel : std_logic; one : Src2CtrlEnum; zero : Src2CtrlEnum) return Src2CtrlEnum; + subtype Src2CtrlEnum_seq_type is std_logic_vector(1 downto 0); + constant Src2CtrlEnum_seq_RS : Src2CtrlEnum_seq_type := "00"; + constant Src2CtrlEnum_seq_IMI : Src2CtrlEnum_seq_type := "01"; + constant Src2CtrlEnum_seq_IMS : Src2CtrlEnum_seq_type := "10"; + constant Src2CtrlEnum_seq_PC : Src2CtrlEnum_seq_type := "11"; + + function pkg_mux (sel : std_logic; one : Src1CtrlEnum; zero : Src1CtrlEnum) return Src1CtrlEnum; + subtype Src1CtrlEnum_seq_type is std_logic_vector(1 downto 0); + constant Src1CtrlEnum_seq_RS : Src1CtrlEnum_seq_type := "00"; + constant Src1CtrlEnum_seq_IMU : Src1CtrlEnum_seq_type := "01"; + constant Src1CtrlEnum_seq_PC_INCREMENT : Src1CtrlEnum_seq_type := "10"; + constant Src1CtrlEnum_seq_URS1 : Src1CtrlEnum_seq_type := "11"; + + function pkg_mux (sel : std_logic; one : JtagState; zero : JtagState) return JtagState; + function pkg_toStdLogicVector_native (value : JtagState) return std_logic_vector; + function pkg_toJtagState_native (value : std_logic_vector(3 downto 0)) return JtagState; + function pkg_mux (sel : std_logic; one : UartStopType; zero : UartStopType) return UartStopType; + subtype UartStopType_seq_type is std_logic_vector(0 downto 0); + constant UartStopType_seq_ONE : UartStopType_seq_type := "0"; + constant UartStopType_seq_TWO : UartStopType_seq_type := "1"; + + function pkg_mux (sel : std_logic; one : UartParityType; zero : UartParityType) return UartParityType; + subtype UartParityType_seq_type is std_logic_vector(1 downto 0); + constant UartParityType_seq_NONE : UartParityType_seq_type := "00"; + constant UartParityType_seq_EVEN : UartParityType_seq_type := "01"; + constant UartParityType_seq_ODD : UartParityType_seq_type := "10"; + + function pkg_mux (sel : std_logic; one : UartCtrlTxState; zero : UartCtrlTxState) return UartCtrlTxState; + function pkg_toStdLogicVector_native (value : UartCtrlTxState) return std_logic_vector; + function pkg_toUartCtrlTxState_native (value : std_logic_vector(2 downto 0)) return UartCtrlTxState; + function pkg_mux (sel : std_logic; one : UartCtrlRxState; zero : UartCtrlRxState) return UartCtrlRxState; + function pkg_toStdLogicVector_native (value : UartCtrlRxState) return std_logic_vector; + function pkg_toUartCtrlRxState_native (value : std_logic_vector(2 downto 0)) return UartCtrlRxState; +end pkg_enum; + +package body pkg_enum is + function pkg_mux (sel : std_logic; one : BranchCtrlEnum; zero : BranchCtrlEnum) return BranchCtrlEnum is + begin + if sel = '1' then + return one; + else + return zero; + end if; + end pkg_mux; + + function pkg_mux (sel : std_logic; one : ShiftCtrlEnum; zero : ShiftCtrlEnum) return ShiftCtrlEnum is + begin + if sel = '1' then + return one; + else + return zero; + end if; + end pkg_mux; + + function pkg_mux (sel : std_logic; one : AluBitwiseCtrlEnum; zero : AluBitwiseCtrlEnum) return AluBitwiseCtrlEnum is + begin + if sel = '1' then + return one; + else + return zero; + end if; + end pkg_mux; + + function pkg_mux (sel : std_logic; one : AluCtrlEnum; zero : AluCtrlEnum) return AluCtrlEnum is + begin + if sel = '1' then + return one; + else + return zero; + end if; + end pkg_mux; + + function pkg_mux (sel : std_logic; one : EnvCtrlEnum; zero : EnvCtrlEnum) return EnvCtrlEnum is + begin + if sel = '1' then + return one; + else + return zero; + end if; + end pkg_mux; + + function pkg_mux (sel : std_logic; one : Src2CtrlEnum; zero : Src2CtrlEnum) return Src2CtrlEnum is + begin + if sel = '1' then + return one; + else + return zero; + end if; + end pkg_mux; + + function pkg_mux (sel : std_logic; one : Src1CtrlEnum; zero : Src1CtrlEnum) return Src1CtrlEnum is + begin + if sel = '1' then + return one; + else + return zero; + end if; + end pkg_mux; + + function pkg_mux (sel : std_logic; one : JtagState; zero : JtagState) return JtagState is + begin + if sel = '1' then + return one; + else + return zero; + end if; + end pkg_mux; + + function pkg_toJtagState_native (value : std_logic_vector(3 downto 0)) return JtagState is + begin + case value is + when "0000" => return RESET; + when "0001" => return IDLE; + when "0010" => return IR_SELECT; + when "0011" => return IR_CAPTURE; + when "0100" => return IR_SHIFT; + when "0101" => return IR_EXIT1; + when "0110" => return IR_PAUSE; + when "0111" => return IR_EXIT2; + when "1000" => return IR_UPDATE; + when "1001" => return DR_SELECT; + when "1010" => return DR_CAPTURE; + when "1011" => return DR_SHIFT; + when "1100" => return DR_EXIT1; + when "1101" => return DR_PAUSE; + when "1110" => return DR_EXIT2; + when "1111" => return DR_UPDATE; + when others => return RESET; + end case; + end; + function pkg_toStdLogicVector_native (value : JtagState) return std_logic_vector is + begin + case value is + when RESET => return "0000"; + when IDLE => return "0001"; + when IR_SELECT => return "0010"; + when IR_CAPTURE => return "0011"; + when IR_SHIFT => return "0100"; + when IR_EXIT1 => return "0101"; + when IR_PAUSE => return "0110"; + when IR_EXIT2 => return "0111"; + when IR_UPDATE => return "1000"; + when DR_SELECT => return "1001"; + when DR_CAPTURE => return "1010"; + when DR_SHIFT => return "1011"; + when DR_EXIT1 => return "1100"; + when DR_PAUSE => return "1101"; + when DR_EXIT2 => return "1110"; + when DR_UPDATE => return "1111"; + when others => return "0000"; + end case; + end; + function pkg_mux (sel : std_logic; one : UartStopType; zero : UartStopType) return UartStopType is + begin + if sel = '1' then + return one; + else + return zero; + end if; + end pkg_mux; + + function pkg_mux (sel : std_logic; one : UartParityType; zero : UartParityType) return UartParityType is + begin + if sel = '1' then + return one; + else + return zero; + end if; + end pkg_mux; + + function pkg_mux (sel : std_logic; one : UartCtrlTxState; zero : UartCtrlTxState) return UartCtrlTxState is + begin + if sel = '1' then + return one; + else + return zero; + end if; + end pkg_mux; + + function pkg_toUartCtrlTxState_native (value : std_logic_vector(2 downto 0)) return UartCtrlTxState is + begin + case value is + when "000" => return IDLE; + when "001" => return START; + when "010" => return DATA; + when "011" => return PARITY; + when "100" => return STOP; + when others => return IDLE; + end case; + end; + function pkg_toStdLogicVector_native (value : UartCtrlTxState) return std_logic_vector is + begin + case value is + when IDLE => return "000"; + when START => return "001"; + when DATA => return "010"; + when PARITY => return "011"; + when STOP => return "100"; + when others => return "000"; + end case; + end; + function pkg_mux (sel : std_logic; one : UartCtrlRxState; zero : UartCtrlRxState) return UartCtrlRxState is + begin + if sel = '1' then + return one; + else + return zero; + end if; + end pkg_mux; + + function pkg_toUartCtrlRxState_native (value : std_logic_vector(2 downto 0)) return UartCtrlRxState is + begin + case value is + when "000" => return IDLE; + when "001" => return START; + when "010" => return DATA; + when "011" => return PARITY; + when "100" => return STOP; + when others => return IDLE; + end case; + end; + function pkg_toStdLogicVector_native (value : UartCtrlRxState) return std_logic_vector is + begin + case value is + when IDLE => return "000"; + when START => return "001"; + when DATA => return "010"; + when PARITY => return "011"; + when STOP => return "100"; + when others => return "000"; + end case; + end; +end pkg_enum; + + +library IEEE; +use ieee.std_logic_1164.all; +use ieee.numeric_std.all; +use ieee.math_real.all; + +package pkg_scala2hdl is + function pkg_extract (that : std_logic_vector; bitId : integer) return std_logic; + function pkg_extract (that : std_logic_vector; base : unsigned; size : integer) return std_logic_vector; + function pkg_cat (a : std_logic_vector; b : std_logic_vector) return std_logic_vector; + function pkg_not (value : std_logic_vector) return std_logic_vector; + function pkg_extract (that : unsigned; bitId : integer) return std_logic; + function pkg_extract (that : unsigned; base : unsigned; size : integer) return unsigned; + function pkg_cat (a : unsigned; b : unsigned) return unsigned; + function pkg_not (value : unsigned) return unsigned; + function pkg_extract (that : signed; bitId : integer) return std_logic; + function pkg_extract (that : signed; base : unsigned; size : integer) return signed; + function pkg_cat (a : signed; b : signed) return signed; + function pkg_not (value : signed) return signed; + + function pkg_mux (sel : std_logic; one : std_logic; zero : std_logic) return std_logic; + function pkg_mux (sel : std_logic; one : std_logic_vector; zero : std_logic_vector) return std_logic_vector; + function pkg_mux (sel : std_logic; one : unsigned; zero : unsigned) return unsigned; + function pkg_mux (sel : std_logic; one : signed; zero : signed) return signed; + + function pkg_toStdLogic (value : boolean) return std_logic; + function pkg_toStdLogicVector (value : std_logic) return std_logic_vector; + function pkg_toUnsigned (value : std_logic) return unsigned; + function pkg_toSigned (value : std_logic) return signed; + function pkg_stdLogicVector (lit : std_logic_vector) return std_logic_vector; + function pkg_unsigned (lit : unsigned) return unsigned; + function pkg_signed (lit : signed) return signed; + + function pkg_resize (that : std_logic_vector; width : integer) return std_logic_vector; + function pkg_resize (that : unsigned; width : integer) return unsigned; + function pkg_resize (that : signed; width : integer) return signed; + + function pkg_extract (that : std_logic_vector; high : integer; low : integer) return std_logic_vector; + function pkg_extract (that : unsigned; high : integer; low : integer) return unsigned; + function pkg_extract (that : signed; high : integer; low : integer) return signed; + + function pkg_shiftRight (that : std_logic_vector; size : natural) return std_logic_vector; + function pkg_shiftRight (that : std_logic_vector; size : unsigned) return std_logic_vector; + function pkg_shiftLeft (that : std_logic_vector; size : natural) return std_logic_vector; + function pkg_shiftLeft (that : std_logic_vector; size : unsigned) return std_logic_vector; + + function pkg_shiftRight (that : unsigned; size : natural) return unsigned; + function pkg_shiftRight (that : unsigned; size : unsigned) return unsigned; + function pkg_shiftLeft (that : unsigned; size : natural) return unsigned; + function pkg_shiftLeft (that : unsigned; size : unsigned) return unsigned; + + function pkg_shiftRight (that : signed; size : natural) return signed; + function pkg_shiftRight (that : signed; size : unsigned) return signed; + function pkg_shiftLeft (that : signed; size : natural) return signed; + function pkg_shiftLeft (that : signed; size : unsigned; w : integer) return signed; + + function pkg_rotateLeft (that : std_logic_vector; size : unsigned) return std_logic_vector; +end pkg_scala2hdl; + +package body pkg_scala2hdl is + function pkg_extract (that : std_logic_vector; bitId : integer) return std_logic is + alias temp : std_logic_vector(that'length-1 downto 0) is that; + begin + if bitId >= temp'length then + return 'U'; + end if; + return temp(bitId); + end pkg_extract; + + function pkg_extract (that : std_logic_vector; base : unsigned; size : integer) return std_logic_vector is + alias temp : std_logic_vector(that'length-1 downto 0) is that; constant elementCount : integer := temp'length - size + 1; + type tableType is array (0 to elementCount-1) of std_logic_vector(size-1 downto 0); + variable table : tableType; + begin + for i in 0 to elementCount-1 loop + table(i) := temp(i + size - 1 downto i); + end loop; + if base + size >= elementCount then + return (size-1 downto 0 => 'U'); + end if; + return table(to_integer(base)); + end pkg_extract; + + function pkg_cat (a : std_logic_vector; b : std_logic_vector) return std_logic_vector is + variable cat : std_logic_vector(a'length + b'length-1 downto 0); + begin + cat := a & b; + return cat; + end pkg_cat; + + function pkg_not (value : std_logic_vector) return std_logic_vector is + variable ret : std_logic_vector(value'length-1 downto 0); + begin + ret := not value; + return ret; + end pkg_not; + + function pkg_extract (that : unsigned; bitId : integer) return std_logic is + alias temp : unsigned(that'length-1 downto 0) is that; + begin + if bitId >= temp'length then + return 'U'; + end if; + return temp(bitId); + end pkg_extract; + + function pkg_extract (that : unsigned; base : unsigned; size : integer) return unsigned is + alias temp : unsigned(that'length-1 downto 0) is that; constant elementCount : integer := temp'length - size + 1; + type tableType is array (0 to elementCount-1) of unsigned(size-1 downto 0); + variable table : tableType; + begin + for i in 0 to elementCount-1 loop + table(i) := temp(i + size - 1 downto i); + end loop; + if base + size >= elementCount then + return (size-1 downto 0 => 'U'); + end if; + return table(to_integer(base)); + end pkg_extract; + + function pkg_cat (a : unsigned; b : unsigned) return unsigned is + variable cat : unsigned(a'length + b'length-1 downto 0); + begin + cat := a & b; + return cat; + end pkg_cat; + + function pkg_not (value : unsigned) return unsigned is + variable ret : unsigned(value'length-1 downto 0); + begin + ret := not value; + return ret; + end pkg_not; + + function pkg_extract (that : signed; bitId : integer) return std_logic is + alias temp : signed(that'length-1 downto 0) is that; + begin + if bitId >= temp'length then + return 'U'; + end if; + return temp(bitId); + end pkg_extract; + + function pkg_extract (that : signed; base : unsigned; size : integer) return signed is + alias temp : signed(that'length-1 downto 0) is that; constant elementCount : integer := temp'length - size + 1; + type tableType is array (0 to elementCount-1) of signed(size-1 downto 0); + variable table : tableType; + begin + for i in 0 to elementCount-1 loop + table(i) := temp(i + size - 1 downto i); + end loop; + if base + size >= elementCount then + return (size-1 downto 0 => 'U'); + end if; + return table(to_integer(base)); + end pkg_extract; + + function pkg_cat (a : signed; b : signed) return signed is + variable cat : signed(a'length + b'length-1 downto 0); + begin + cat := a & b; + return cat; + end pkg_cat; + + function pkg_not (value : signed) return signed is + variable ret : signed(value'length-1 downto 0); + begin + ret := not value; + return ret; + end pkg_not; + + + -- unsigned shifts + function pkg_shiftRight (that : unsigned; size : natural) return unsigned is + variable ret : unsigned(that'length-1 downto 0); + begin + if size >= that'length then + return ""; + else + ret := shift_right(that,size); + return ret(that'length-1-size downto 0); + end if; + end pkg_shiftRight; + + function pkg_shiftRight (that : unsigned; size : unsigned) return unsigned is + variable ret : unsigned(that'length-1 downto 0); + begin + ret := shift_right(that,to_integer(size)); + return ret; + end pkg_shiftRight; + + function pkg_shiftLeft (that : unsigned; size : natural) return unsigned is + begin + return shift_left(resize(that,that'length + size),size); + end pkg_shiftLeft; + + function pkg_shiftLeft (that : unsigned; size : unsigned) return unsigned is + begin + return shift_left(resize(that,that'length + 2**size'length - 1),to_integer(size)); + end pkg_shiftLeft; + + -- std_logic_vector shifts + function pkg_shiftRight (that : std_logic_vector; size : natural) return std_logic_vector is + begin + return std_logic_vector(pkg_shiftRight(unsigned(that),size)); + end pkg_shiftRight; + + function pkg_shiftRight (that : std_logic_vector; size : unsigned) return std_logic_vector is + begin + return std_logic_vector(pkg_shiftRight(unsigned(that),size)); + end pkg_shiftRight; + + function pkg_shiftLeft (that : std_logic_vector; size : natural) return std_logic_vector is + begin + return std_logic_vector(pkg_shiftLeft(unsigned(that),size)); + end pkg_shiftLeft; + + function pkg_shiftLeft (that : std_logic_vector; size : unsigned) return std_logic_vector is + begin + return std_logic_vector(pkg_shiftLeft(unsigned(that),size)); + end pkg_shiftLeft; + + -- signed shifts + function pkg_shiftRight (that : signed; size : natural) return signed is + begin + return signed(pkg_shiftRight(unsigned(that),size)); + end pkg_shiftRight; + + function pkg_shiftRight (that : signed; size : unsigned) return signed is + begin + return shift_right(that,to_integer(size)); + end pkg_shiftRight; + + function pkg_shiftLeft (that : signed; size : natural) return signed is + begin + return signed(pkg_shiftLeft(unsigned(that),size)); + end pkg_shiftLeft; + + function pkg_shiftLeft (that : signed; size : unsigned; w : integer) return signed is + begin + return shift_left(resize(that,w),to_integer(size)); + end pkg_shiftLeft; + + function pkg_rotateLeft (that : std_logic_vector; size : unsigned) return std_logic_vector is + begin + return std_logic_vector(rotate_left(unsigned(that),to_integer(size))); + end pkg_rotateLeft; + + function pkg_extract (that : std_logic_vector; high : integer; low : integer) return std_logic_vector is + alias temp : std_logic_vector(that'length-1 downto 0) is that; + begin + return temp(high downto low); + end pkg_extract; + + function pkg_extract (that : unsigned; high : integer; low : integer) return unsigned is + alias temp : unsigned(that'length-1 downto 0) is that; + begin + return temp(high downto low); + end pkg_extract; + + function pkg_extract (that : signed; high : integer; low : integer) return signed is + alias temp : signed(that'length-1 downto 0) is that; + begin + return temp(high downto low); + end pkg_extract; + + function pkg_mux (sel : std_logic; one : std_logic; zero : std_logic) return std_logic is + begin + if sel = '1' then + return one; + else + return zero; + end if; + end pkg_mux; + + function pkg_mux (sel : std_logic; one : std_logic_vector; zero : std_logic_vector) return std_logic_vector is + variable ret : std_logic_vector(zero'range); + begin + if sel = '1' then + ret := one; + else + ret := zero; + end if; + return ret; + end pkg_mux; + + function pkg_mux (sel : std_logic; one : unsigned; zero : unsigned) return unsigned is + variable ret : unsigned(zero'range); + begin + if sel = '1' then + ret := one; + else + ret := zero; + end if; + return ret; + end pkg_mux; + + function pkg_mux (sel : std_logic; one : signed; zero : signed) return signed is + variable ret : signed(zero'range); + begin + if sel = '1' then + ret := one; + else + ret := zero; + end if; + return ret; + end pkg_mux; + + function pkg_toStdLogic (value : boolean) return std_logic is + begin + if value = true then + return '1'; + else + return '0'; + end if; + end pkg_toStdLogic; + + function pkg_toStdLogicVector (value : std_logic) return std_logic_vector is + variable ret : std_logic_vector(0 downto 0); + begin + ret(0) := value; + return ret; + end pkg_toStdLogicVector; + + function pkg_toUnsigned (value : std_logic) return unsigned is + variable ret : unsigned(0 downto 0); + begin + ret(0) := value; + return ret; + end pkg_toUnsigned; + + function pkg_toSigned (value : std_logic) return signed is + variable ret : signed(0 downto 0); + begin + ret(0) := value; + return ret; + end pkg_toSigned; + + function pkg_stdLogicVector (lit : std_logic_vector) return std_logic_vector is + alias ret : std_logic_vector(lit'length-1 downto 0) is lit; + begin + return ret; + end pkg_stdLogicVector; + + function pkg_unsigned (lit : unsigned) return unsigned is + alias ret : unsigned(lit'length-1 downto 0) is lit; + begin + return ret; + end pkg_unsigned; + + function pkg_signed (lit : signed) return signed is + alias ret : signed(lit'length-1 downto 0) is lit; + begin + return ret; + end pkg_signed; + + function pkg_resize (that : std_logic_vector; width : integer) return std_logic_vector is + begin + return std_logic_vector(resize(unsigned(that),width)); + end pkg_resize; + + function pkg_resize (that : unsigned; width : integer) return unsigned is + variable ret : unsigned(width-1 downto 0); + begin + if that'length = 0 then + ret := (others => '0'); + else + ret := resize(that,width); + end if; + return ret; + end pkg_resize; + function pkg_resize (that : signed; width : integer) return signed is + alias temp : signed(that'length-1 downto 0) is that; + variable ret : signed(width-1 downto 0); + begin + if temp'length = 0 then + ret := (others => '0'); + elsif temp'length >= width then + ret := temp(width-1 downto 0); + else + ret := resize(temp,width); + end if; + return ret; + end pkg_resize; +end pkg_scala2hdl; diff --git a/flow/designs/src/murax/murax_ram.vhd b/flow/designs/src/murax/murax_ram.vhd new file mode 100644 index 0000000000..212b9580ea --- /dev/null +++ b/flow/designs/src/murax/murax_ram.vhd @@ -0,0 +1,166 @@ +library ieee; +use ieee.std_logic_1164.all; +use ieee.numeric_std.all; + +library work; +use work.pkg_scala2hdl.all; +use work.all; +use work.pkg_enum.all; + + +entity MuraxPipelinedMemoryBusRam is + port( + io_bus_cmd_valid : in std_logic; + io_bus_cmd_ready : out std_logic; + io_bus_cmd_payload_write : in std_logic; + io_bus_cmd_payload_address : in unsigned(31 downto 0); + io_bus_cmd_payload_data : in std_logic_vector(31 downto 0); + io_bus_cmd_payload_mask : in std_logic_vector(3 downto 0); + io_bus_rsp_valid : out std_logic; + io_bus_rsp_payload_data : out std_logic_vector(31 downto 0); + io_mainClk : in std_logic; + resetCtrl_systemReset : in std_logic + ); +end MuraxPipelinedMemoryBusRam; + +architecture ihp of MuraxPipelinedMemoryBusRam is + + component RM_IHPSG13_1P_1024x8_c2_bm_bist is + port( + A_CLK : in std_logic; + A_MEN : in std_logic; + A_WEN : in std_logic; + A_REN : in std_logic; + A_ADDR : in std_logic_vector(9 downto 0); + A_DIN : in std_logic_vector(7 downto 0); + A_DLY : in std_logic; + A_DOUT : out std_logic_vector(7 downto 0); + A_BM : in std_logic_vector(7 downto 0); + A_BIST_CLK : in std_logic; + A_BIST_EN : in std_logic; + A_BIST_MEN : in std_logic; + A_BIST_WEN : in std_logic; + A_BIST_REN : in std_logic; + A_BIST_ADDR : in std_logic_vector(9 downto 0); + A_BIST_DIN : in std_logic_vector(7 downto 0); + A_BIST_BM : in std_logic_vector(7 downto 0) + ); + end component; + + signal io_bus_cmd_fire : std_logic; + signal io_bus_cmd_ready_read_buffer : std_logic; + signal zz_io_bus_rsp_valid : std_logic; + signal word_addr : std_logic_vector(9 downto 0); + signal dout0, dout1, dout2, dout3 : std_logic_vector(7 downto 0); + signal wen0, wen1, wen2, wen3 : std_logic; + signal ren : std_logic; + +begin + + word_addr <= std_logic_vector(io_bus_cmd_payload_address(11 downto 2)); + wen0 <= io_bus_cmd_payload_write and io_bus_cmd_payload_mask(0); + wen1 <= io_bus_cmd_payload_write and io_bus_cmd_payload_mask(1); + wen2 <= io_bus_cmd_payload_write and io_bus_cmd_payload_mask(2); + wen3 <= io_bus_cmd_payload_write and io_bus_cmd_payload_mask(3); + ren <= not io_bus_cmd_payload_write; + + ram_byte0 : RM_IHPSG13_1P_1024x8_c2_bm_bist + port map( + A_CLK => io_mainClk, + A_MEN => io_bus_cmd_valid, + A_WEN => wen0, + A_REN => ren, + A_ADDR => word_addr, + A_DIN => io_bus_cmd_payload_data(7 downto 0), + A_DLY => '1', + A_DOUT => dout0, + A_BM => (others => '1'), + A_BIST_CLK => '0', + A_BIST_EN => '0', + A_BIST_MEN => '0', + A_BIST_WEN => '0', + A_BIST_REN => '0', + A_BIST_ADDR => (others => '0'), + A_BIST_DIN => (others => '0'), + A_BIST_BM => (others => '0') + ); + + ram_byte1 : RM_IHPSG13_1P_1024x8_c2_bm_bist + port map( + A_CLK => io_mainClk, + A_MEN => io_bus_cmd_valid, + A_WEN => wen1, + A_REN => ren, + A_ADDR => word_addr, + A_DIN => io_bus_cmd_payload_data(15 downto 8), + A_DLY => '1', + A_DOUT => dout1, + A_BM => (others => '1'), + A_BIST_CLK => '0', + A_BIST_EN => '0', + A_BIST_MEN => '0', + A_BIST_WEN => '0', + A_BIST_REN => '0', + A_BIST_ADDR => (others => '0'), + A_BIST_DIN => (others => '0'), + A_BIST_BM => (others => '0') + ); + + ram_byte2 : RM_IHPSG13_1P_1024x8_c2_bm_bist + port map( + A_CLK => io_mainClk, + A_MEN => io_bus_cmd_valid, + A_WEN => wen2, + A_REN => ren, + A_ADDR => word_addr, + A_DIN => io_bus_cmd_payload_data(23 downto 16), + A_DLY => '1', + A_DOUT => dout2, + A_BM => (others => '1'), + A_BIST_CLK => '0', + A_BIST_EN => '0', + A_BIST_MEN => '0', + A_BIST_WEN => '0', + A_BIST_REN => '0', + A_BIST_ADDR => (others => '0'), + A_BIST_DIN => (others => '0'), + A_BIST_BM => (others => '0') + ); + + ram_byte3 : RM_IHPSG13_1P_1024x8_c2_bm_bist + port map( + A_CLK => io_mainClk, + A_MEN => io_bus_cmd_valid, + A_WEN => wen3, + A_REN => ren, + A_ADDR => word_addr, + A_DIN => io_bus_cmd_payload_data(31 downto 24), + A_DLY => '1', + A_DOUT => dout3, + A_BM => (others => '1'), + A_BIST_CLK => '0', + A_BIST_EN => '0', + A_BIST_MEN => '0', + A_BIST_WEN => '0', + A_BIST_REN => '0', + A_BIST_ADDR => (others => '0'), + A_BIST_DIN => (others => '0'), + A_BIST_BM => (others => '0') + ); + + io_bus_cmd_ready_read_buffer <= '1'; + io_bus_cmd_ready <= io_bus_cmd_ready_read_buffer; + io_bus_cmd_fire <= io_bus_cmd_valid and io_bus_cmd_ready_read_buffer; + io_bus_rsp_payload_data <= dout3 & dout2 & dout1 & dout0; + io_bus_rsp_valid <= zz_io_bus_rsp_valid; + + process(io_mainClk, resetCtrl_systemReset) + begin + if resetCtrl_systemReset = '1' then + zz_io_bus_rsp_valid <= '0'; + elsif rising_edge(io_mainClk) then + zz_io_bus_rsp_valid <= io_bus_cmd_fire and (not io_bus_cmd_payload_write); + end if; + end process; + +end architecture ihp; diff --git a/flow/designs/src/murax/murax_ram_rtl.vhd b/flow/designs/src/murax/murax_ram_rtl.vhd new file mode 100644 index 0000000000..02e9061a3b --- /dev/null +++ b/flow/designs/src/murax/murax_ram_rtl.vhd @@ -0,0 +1,353 @@ +library ieee; +use ieee.std_logic_1164.all; +use ieee.numeric_std.all; + +library work; +use work.pkg_scala2hdl.all; +use work.all; +use work.pkg_enum.all; + + +entity MuraxPipelinedMemoryBusRam is + port( + io_bus_cmd_valid : in std_logic; + io_bus_cmd_ready : out std_logic; + io_bus_cmd_payload_write : in std_logic; + io_bus_cmd_payload_address : in unsigned(31 downto 0); + io_bus_cmd_payload_data : in std_logic_vector(31 downto 0); + io_bus_cmd_payload_mask : in std_logic_vector(3 downto 0); + io_bus_rsp_valid : out std_logic; + io_bus_rsp_payload_data : out std_logic_vector(31 downto 0); + io_mainClk : in std_logic; + resetCtrl_systemReset : in std_logic + ); +end MuraxPipelinedMemoryBusRam; + +architecture arch of MuraxPipelinedMemoryBusRam is + signal zz_ram_port0 : std_logic_vector(31 downto 0); + signal io_bus_cmd_ready_read_buffer : std_logic; + signal zz_ram_port : unsigned(9 downto 0); + signal zz_io_bus_rsp_payload_data_2 : unsigned(9 downto 0); + + signal io_bus_cmd_fire : std_logic; + signal zz_io_bus_rsp_valid : std_logic; + signal zz_io_bus_rsp_payload_data : unsigned(29 downto 0); + signal zz_io_bus_rsp_payload_data_1 : std_logic_vector(31 downto 0); + type ram_type is array (0 to 1023) of std_logic_vector(7 downto 0); + signal ram_symbol0 : ram_type := ( + "01101111","00010011","00010011","00010011","00010011","00010011","00010011","00010011","00100011","00100011","00100011","00100011","00100011","00100011","00100011","00100011", + "00100011","00100011","00100011","00100011","00100011","00100011","00100011","00100011","00010011","11101111","10000011","10000011","00000011","10000011","00000011","10000011", + "00000011","10000011","00000011","10000011","00000011","10000011","00000011","10000011","00000011","10000011","00010011","01110011","10010111","10010011","00010011","00010111", + "00010011","10010111","10010011","01100011","00100011","00010011","01101111","00010111","00010011","00010011","10010111","10010011","01100011","10000011","00010011","00100011", + "11100111","00000011","01101111","00010011","00110111","00010011","01110011","00110111","00010011","01110011","11101111","01101111","00010011","00100011","00010011","00100011", + "10000011","00100011","10000011","00100011","00010011","00000011","00010011","01100111","00010011","00100011","00010011","00100011","00010011","00000011","00010011","01100111", + "00010011","00100011","00010011","00100011","10000011","00100011","10000011","00010011","00100011","00010011","00000011","00010011","01100111","00010011","00100011","00010011", + "00100011","10000011","10000011","10010011","10010011","00010011","00000011","00010011","01100111","00010011","00100011","00010011","00100011","10000011","10000011","10010011", + "00010011","00000011","00010011","01100111","00010011","00100011","00100011","00010011","00100011","00100011","00010011","00000011","11101111","10010011","11100011","10000011", + "00000011","00100011","00010011","10000011","00000011","00010011","01100111","00010011","00100011","00010011","00100011","00100011","10000011","00000011","10000011","00100011", + "10000011","10000011","00010011","10000011","10000011","10010011","00110011","10000011","10000011","10010011","00110011","10000011","00100011","00010011","00000011","00010011", + "01100111","00010011","00100011","00100011","00010011","10010011","00100011","10010011","00100011","10010011","00100011","00100011","10110111","10010011","00000011","10000011", + "00000011","00000011","10000011","00000011","00000011","10000011","00000011","10000011","00000011","10000011","00100011","00100011","00100011","00100011","00100011","00100011", + "00100011","00100011","00100011","00100011","00100011","00100011","00100011","10110111","00010011","11101111","00110111","11101111","10110111","00010011","11101111","10110111", + "00110111","00010011","00100011","10110111","10010011","00010011","00100011","10110111","10010011","00110111","00010011","00100011","10110111","10010011","00010011","00100011", + "10110111","10010011","00010011","00100011","10110111","00010011","00100011","10110111","00100011","10110111","00010011","00100011","10110111","00010011","00100011","10000011", + "00000011","10110011","00100011","00000011","10000011","10110011","00000011","10110011","00100011","00100011","01101111","10000011","10010011","00100011","00000011","10110111", + "10010011","11100011","00000011","10010011","01100011","00100011","01101111","10000011","10010011","00100011","10000011","00010011","10110011","00000011","10110111","00100011", + "10110111","10000011","10010011","10110111","10000011","10010011","00010011","10110111","00110011","00100011","01101111","00010011","00100011","00010011","10110111","10010011", + "10000011","10010011","01100011","10110111","00000011","10110111","00010011","00100011","10110111","10010011","00010011","00100011","01101111","10110111","00000011","10110111", + "00010011","00100011","10110111","10000011","10010011","11100011","00010011","00010011","00000011","00010011","01100111","01001100","01100101","01110010","00100001","01110010", + "10111100","01101000","01000100","01100101","00100000","01100101","01101001","00000000","00000000","00000000","00000000","00000000","00000000","00000000","00000000","00000000", + "00000000","00000000","00000000","00000000","00000000","00000000","00000000","00000000","00000000","00000000","00000000","00000000","00000000","00000000","00000000","00000000", + "00000000","00000000","00000000","00000000","00000000","00000000","00000000","00000000","00000000","00000000","00000000","00000000","00000000","00000000","00000000","00000000", + "00000000","00000000","00000000","00000000","00000000","00000000","00000000","00000000","00000000","00000000","00000000","00000000","00000000","00000000","00000000","00000000", + "00000000","00000000","00000000","00000000","00000000","00000000","00000000","00000000","00000000","00000000","00000000","00000000","00000000","00000000","00000000","00000000", + "00000000","00000000","00000000","00000000","00000000","00000000","00000000","00000000","00000000","00000000","00000000","00000000","00000000","00000000","00000000","00000000", + "00000000","00000000","00000000","00000000","00000000","00000000","00000000","00000000","00000000","00000000","00000000","00000000","00000000","00000000","00000000","00000000", + "00000000","00000000","00000000","00000000","00000000","00000000","00000000","00000000","00000000","00000000","00000000","00000000","00000000","00000000","00000000","00000000", + "00000000","00000000","00000000","00000000","00000000","00000000","00000000","00000000","00000000","00000000","00000000","00000000","00000000","00000000","00000000","00000000", + "00000000","00000000","00000000","00000000","00000000","00000000","00000000","00000000","00000000","00000000","00000000","00000000","00000000","00000000","00000000","00000000", + "00000000","00000000","00000000","00000000","00000000","00000000","00000000","00000000","00000000","00000000","00000000","00000000","00000000","00000000","00000000","00000000", + "00000000","00000000","00000000","00000000","00000000","00000000","00000000","00000000","00000000","00000000","00000000","00000000","00000000","00000000","00000000","00000000", + "00000000","00000000","00000000","00000000","00000000","00000000","00000000","00000000","00000000","00000000","00000000","00000000","00000000","00000000","00000000","00000000", + "00000000","00000000","00000000","00000000","00000000","00000000","00000000","00000000","00000000","00000000","00000000","00000000","00000000","00000000","00000000","00000000", + "00000000","00000000","00000000","00000000","00000000","00000000","00000000","00000000","00000000","00000000","00000000","00000000","00000000","00000000","00000000","00000000", + "00000000","00000000","00000000","00000000","00000000","00000000","00000000","00000000","00000000","00000000","00000000","00000000","00000000","00000000","00000000","00000000", + "00000000","00000000","00000000","00000000","00000000","00000000","00000000","00000000","00000000","00000000","00000000","00000000","00000000","00000000","00000000","00000000", + "00000000","00000000","00000000","00000000","00000000","00000000","00000000","00000000","00000000","00000000","00000000","00000000","00000000","00000000","00000000","00000000", + "00000000","00000000","00000000","00000000","00000000","00000000","00000000","00000000","00000000","00000000","00000000","00000000","00000000","00000000","00000000","00000000", + "00000000","00000000","00000000","00000000","00000000","00000000","00000000","00000000","00000000","00000000","00000000","00000000","00000000","00000000","00000000","00000000", + "00000000","00000000","00000000","00000000","00000000","00000000","00000000","00000000","00000000","00000000","00000000","00000000","00000000","00000000","00000000","00000000", + "00000000","00000000","00000000","00000000","00000000","00000000","00000000","00000000","00000000","00000000","00000000","00000000","00000000","00000000","00000000","00000000", + "00000000","00000000","00000000","00000000","00000000","00000000","00000000","00000000","00000000","00000000","00000000","00000000","00000000","00000000","00000000","00000000", + "00000000","00000000","00000000","00000000","00000000","00000000","00000000","00000000","00000000","00000000","00000000","00000000","00000000","00000000","00000000","00000000", + "00000000","00000000","00000000","00000000","00000000","00000000","00000000","00000000","00000000","00000000","00000000","00000000","00000000","00000000","00000000","00000000", + "00000000","00000000","00000000","00000000","00000000","00000000","00000000","00000000","00000000","00000000","00000000","00000000","00000000","00000000","00000000","00000000", + "00000000","00000000","00000000","00000000","00000000","00000000","00000000","00000000","00000000","00000000","00000000","00000000","00000000","00000000","00000000","00000000", + "00000000","00000000","00000000","00000000","00000000","00000000","00000000","00000000","00000000","00000000","00000000","00000000","00000000","00000000","00000000","00000000", + "00000000","00000000","00000000","00000000","00000000","00000000","00000000","00000000","00000000","00000000","00000000","00000000","00000000","00000000","00000000","00000000", + "00000000","00000000","00000000","00000000","00000000","00000000","00000000","00000000","00000000","00000000","00000000","00000000","00000000","00000000","00000000","00000000", + "00000000","00000000","00000000","00000000","00000000","00000000","00000000","00000000","00000000","00000000","00000000","00000000","00000000","00000000","00000000","00000000", + "00000000","00000000","00000000","00000000","00000000","00000000","00000000","00000000","00000000","00000000","00000000","00000000","00000000","00000000","00000000","00000000", + "00000000","00000000","00000000","00000000","00000000","00000000","00000000","00000000","00000000","00000000","00000000","00000000","00000000","00000000","00000000","00000000", + "00000000","00000000","00000000","00000000","00000000","00000000","00000000","00000000","00000000","00000000","00000000","00000000","00000000","00000000","00000000","00000000", + "00000000","00000000","00000000","00000000","00000000","00000000","00000000","00000000","00000000","00000000","00000000","00000000","00000000","00000000","00000000","00000000", + "00000000","00000000","00000000","00000000","00000000","00000000","00000000","00000000","00000000","00000000","00000000","00000000","00000000","00000000","00000000","00000000", + "00000000","00000000","00000000","00000000","00000000","00000000","00000000","00000000","00000000","00000000","00000000","00000000","00000000","00000000","00000000","00000000", + "00000000","00000000","00000000","00000000","00000000","00000000","00000000","00000000","00000000","00000000","00000000","00000000","00000000","00000000","00000000","00000000", + "00000000","00000000","00000000","00000000","00000000","00000000","00000000","00000000","00000000","00000000","00000000","00000000","00000000","00000000","00000000","00000000", + "00000000","00000000","00000000","00000000","00000000","00000000","00000000","00000000","00000000","00000000","00000000","00000000","00000000","00000000","00000000","00000000", + "00000000","00000000","00000000","00000000","00000000","00000000","00000000","00000000","00000000","00000000","00000000","00000000","00000000","00000000","00000000","00000000", + "00000000","00000000","00000000","00000000","00000000","00000000","00000000","00000000","00000000","00000000","00000000","00000000","00000000","00000000","00000000","00000000", + "00000000","00000000","00000000","00000000","00000000","00000000","00000000","00000000","00000000","00000000","00000000","00000000","00000000","00000000","00000000","00000000"); + signal ram_symbol1 : ram_type := ( + "00000000","00000000","00000000","00000000","00000000","00000000","00000000","00000000","00101110","00101100","00101010","00101000","00100110","00100100","00100010","00100000", + "00101110","00101100","00101010","00101000","00100110","00100100","00100010","00100000","00000001","00000000","00100000","00100010","00100011","00100011","00100101","00100101", + "00100110","00100110","00100111","00100111","00101000","00101000","00101110","00101110","00101111","00101111","00000001","00000000","00010001","10000001","10000001","00000101", + "00000101","00000101","10000101","00001000","00100000","00000101","11110000","00000101","00000101","00000001","00000101","10000101","00001110","00100110","00000101","00100000", + "10000000","00100101","11110000","00000001","00010101","00000101","00010000","00100101","00000101","00010000","00000000","00000000","00000001","00101110","00000100","00100110", + "00100111","10100000","00100111","10100100","00000000","00100100","00000001","10000000","00000001","00101110","00000100","00100110","00000000","00100100","00000001","10000000", + "00000001","00101110","00000100","00100110","00100111","10100010","00100111","00000111","10100000","00000000","00100100","00000001","10000000","00000001","00101110","00000100", + "00100110","00100111","10100111","11010111","11110111","10000101","00100100","00000001","10000000","00000001","00101110","00000100","00100110","00100111","10100111","11010111", + "10000101","00100100","00000001","10000000","00000001","00101110","00101100","00000100","00100110","00100100","00000000","00100101","11110000","00000111","10001010","00100111", + "00100111","10100000","00000000","00100000","00100100","00000001","10000000","00000001","00101110","00000100","00100110","00100100","00100111","10100111","00100111","10100100", + "00100111","10100111","10000111","00100111","10100111","10010111","01100111","00100111","10100111","10010111","01100111","00100111","10100110","00000000","00100100","00000001", + "10000000","00000001","00101110","00101100","00000100","00000111","00100000","00000111","00101110","00000111","00101100","00100110","00000111","10000111","10101111","10101110", + "10101110","10100011","10101000","10101000","10100101","10100101","10100110","10100110","10100111","10100111","00100100","00100110","00101000","00101010","00101100","00101110", + "00100000","00100010","00100100","00100110","00101000","00101010","00100100","00000111","10000101","11110000","00000101","11110000","00000111","10000101","11110000","00000111", + "11000111","00000111","10100000","00000111","10000111","00000111","10100010","00000111","10000111","00000111","00000111","10100000","00000111","10000111","00000111","10100000", + "00000111","10000111","00000111","10100010","00000111","00000111","10100100","00000111","10100010","00000111","00000111","10100010","00000111","00000111","10100000","00100111", + "00100111","00000111","00100110","00100111","00100111","00000111","00100111","00000111","00100110","00100010","00000000","00100111","10000111","00100010","00100111","00010111", + "10000111","11110100","00100111","00000111","00010110","00100100","00000000","00100111","10000111","00100100","00100111","00000111","00000111","11000111","00000111","10100000", + "00000111","10100111","11110110","00000111","10100111","10000111","11110111","00000111","11100111","10100010","11110000","00000001","00100110","00000100","00000111","10000111", + "10100111","11110111","10000000","00000111","10100111","00000111","01000111","10100010","00000111","10000111","00000111","10100000","00000000","00000111","10100111","00000111", + "01110111","10100000","00000111","10100111","11110111","10010000","00000000","00000000","00100100","00000001","10000000","01101001","01110010","01100001","00100000","00100000", + "01101110","01100101","01101001","01101001","01100111","00100000","01110100","00000000","00000000","00000000","00000000","00000000","00000000","00000000","00000000","00000000", + "00000000","00000000","00000000","00000000","00000000","00000000","00000000","00000000","00000000","00000000","00000000","00000000","00000000","00000000","00000000","00000000", + "00000000","00000000","00000000","00000000","00000000","00000000","00000000","00000000","00000000","00000000","00000000","00000000","00000000","00000000","00000000","00000000", + "00000000","00000000","00000000","00000000","00000000","00000000","00000000","00000000","00000000","00000000","00000000","00000000","00000000","00000000","00000000","00000000", + "00000000","00000000","00000000","00000000","00000000","00000000","00000000","00000000","00000000","00000000","00000000","00000000","00000000","00000000","00000000","00000000", + "00000000","00000000","00000000","00000000","00000000","00000000","00000000","00000000","00000000","00000000","00000000","00000000","00000000","00000000","00000000","00000000", + "00000000","00000000","00000000","00000000","00000000","00000000","00000000","00000000","00000000","00000000","00000000","00000000","00000000","00000000","00000000","00000000", + "00000000","00000000","00000000","00000000","00000000","00000000","00000000","00000000","00000000","00000000","00000000","00000000","00000000","00000000","00000000","00000000", + "00000000","00000000","00000000","00000000","00000000","00000000","00000000","00000000","00000000","00000000","00000000","00000000","00000000","00000000","00000000","00000000", + "00000000","00000000","00000000","00000000","00000000","00000000","00000000","00000000","00000000","00000000","00000000","00000000","00000000","00000000","00000000","00000000", + "00000000","00000000","00000000","00000000","00000000","00000000","00000000","00000000","00000000","00000000","00000000","00000000","00000000","00000000","00000000","00000000", + "00000000","00000000","00000000","00000000","00000000","00000000","00000000","00000000","00000000","00000000","00000000","00000000","00000000","00000000","00000000","00000000", + "00000000","00000000","00000000","00000000","00000000","00000000","00000000","00000000","00000000","00000000","00000000","00000000","00000000","00000000","00000000","00000000", + "00000000","00000000","00000000","00000000","00000000","00000000","00000000","00000000","00000000","00000000","00000000","00000000","00000000","00000000","00000000","00000000", + "00000000","00000000","00000000","00000000","00000000","00000000","00000000","00000000","00000000","00000000","00000000","00000000","00000000","00000000","00000000","00000000", + "00000000","00000000","00000000","00000000","00000000","00000000","00000000","00000000","00000000","00000000","00000000","00000000","00000000","00000000","00000000","00000000", + "00000000","00000000","00000000","00000000","00000000","00000000","00000000","00000000","00000000","00000000","00000000","00000000","00000000","00000000","00000000","00000000", + "00000000","00000000","00000000","00000000","00000000","00000000","00000000","00000000","00000000","00000000","00000000","00000000","00000000","00000000","00000000","00000000", + "00000000","00000000","00000000","00000000","00000000","00000000","00000000","00000000","00000000","00000000","00000000","00000000","00000000","00000000","00000000","00000000", + "00000000","00000000","00000000","00000000","00000000","00000000","00000000","00000000","00000000","00000000","00000000","00000000","00000000","00000000","00000000","00000000", + "00000000","00000000","00000000","00000000","00000000","00000000","00000000","00000000","00000000","00000000","00000000","00000000","00000000","00000000","00000000","00000000", + "00000000","00000000","00000000","00000000","00000000","00000000","00000000","00000000","00000000","00000000","00000000","00000000","00000000","00000000","00000000","00000000", + "00000000","00000000","00000000","00000000","00000000","00000000","00000000","00000000","00000000","00000000","00000000","00000000","00000000","00000000","00000000","00000000", + "00000000","00000000","00000000","00000000","00000000","00000000","00000000","00000000","00000000","00000000","00000000","00000000","00000000","00000000","00000000","00000000", + "00000000","00000000","00000000","00000000","00000000","00000000","00000000","00000000","00000000","00000000","00000000","00000000","00000000","00000000","00000000","00000000", + "00000000","00000000","00000000","00000000","00000000","00000000","00000000","00000000","00000000","00000000","00000000","00000000","00000000","00000000","00000000","00000000", + "00000000","00000000","00000000","00000000","00000000","00000000","00000000","00000000","00000000","00000000","00000000","00000000","00000000","00000000","00000000","00000000", + "00000000","00000000","00000000","00000000","00000000","00000000","00000000","00000000","00000000","00000000","00000000","00000000","00000000","00000000","00000000","00000000", + "00000000","00000000","00000000","00000000","00000000","00000000","00000000","00000000","00000000","00000000","00000000","00000000","00000000","00000000","00000000","00000000", + "00000000","00000000","00000000","00000000","00000000","00000000","00000000","00000000","00000000","00000000","00000000","00000000","00000000","00000000","00000000","00000000", + "00000000","00000000","00000000","00000000","00000000","00000000","00000000","00000000","00000000","00000000","00000000","00000000","00000000","00000000","00000000","00000000", + "00000000","00000000","00000000","00000000","00000000","00000000","00000000","00000000","00000000","00000000","00000000","00000000","00000000","00000000","00000000","00000000", + "00000000","00000000","00000000","00000000","00000000","00000000","00000000","00000000","00000000","00000000","00000000","00000000","00000000","00000000","00000000","00000000", + "00000000","00000000","00000000","00000000","00000000","00000000","00000000","00000000","00000000","00000000","00000000","00000000","00000000","00000000","00000000","00000000", + "00000000","00000000","00000000","00000000","00000000","00000000","00000000","00000000","00000000","00000000","00000000","00000000","00000000","00000000","00000000","00000000", + "00000000","00000000","00000000","00000000","00000000","00000000","00000000","00000000","00000000","00000000","00000000","00000000","00000000","00000000","00000000","00000000", + "00000000","00000000","00000000","00000000","00000000","00000000","00000000","00000000","00000000","00000000","00000000","00000000","00000000","00000000","00000000","00000000", + "00000000","00000000","00000000","00000000","00000000","00000000","00000000","00000000","00000000","00000000","00000000","00000000","00000000","00000000","00000000","00000000", + "00000000","00000000","00000000","00000000","00000000","00000000","00000000","00000000","00000000","00000000","00000000","00000000","00000000","00000000","00000000","00000000", + "00000000","00000000","00000000","00000000","00000000","00000000","00000000","00000000","00000000","00000000","00000000","00000000","00000000","00000000","00000000","00000000", + "00000000","00000000","00000000","00000000","00000000","00000000","00000000","00000000","00000000","00000000","00000000","00000000","00000000","00000000","00000000","00000000", + "00000000","00000000","00000000","00000000","00000000","00000000","00000000","00000000","00000000","00000000","00000000","00000000","00000000","00000000","00000000","00000000", + "00000000","00000000","00000000","00000000","00000000","00000000","00000000","00000000","00000000","00000000","00000000","00000000","00000000","00000000","00000000","00000000"); + signal ram_symbol2 : ram_type := ( + "00000000","00000000","00000000","00000000","00000000","00000000","00000000","00000000","00010001","01010001","01100001","01110001","10100001","10110001","11000001","11010001", + "11100001","11110001","00000001","00010001","11000001","11010001","11100001","11110001","00000001","10000000","11000001","10000001","01000001","00000001","11000001","10000001", + "01000001","00000001","11000001","10000001","01000001","00000001","11000001","10000001","01000001","00000001","00000001","00100000","00000000","00000001","00000001","00000000", + "01000101","00000000","11000101","10110101","00000101","01000101","01011111","00000000","00000101","11000001","00000000","01000101","10110101","00000101","01000101","10100001", + "00000110","00000001","00011111","01000001","00000000","00000101","01000101","00000000","10000101","00000101","11000000","00000000","00000001","10000001","00000001","10100100", + "11000100","00000111","11000100","00000111","00000000","11000001","00000001","00000000","00000001","10000001","00000001","10100100","00000000","11000001","00000001","00000000", + "00000001","10000001","00000001","10100100","11000100","00000111","11000100","11110000","11100111","00000000","11000001","00000001","00000000","00000001","10000001","00000001", + "10100100","11000100","01000111","00000111","11110111","00000111","11000001","00000001","00000000","00000001","10000001","00000001","10100100","11000100","01000111","10000111", + "00000111","11000001","00000001","00000000","00000001","00010001","10000001","00000001","10100100","10110100","00000000","11000100","01011111","00000101","00000111","11000100", + "10000100","11100111","00000000","11000001","10000001","00000001","00000000","00000001","10000001","00000001","10100100","10110100","10000100","11000111","11000100","11100111", + "10000100","00000111","11110111","10000100","01000111","10000111","11110111","10000100","10000111","00000111","11110111","11000100","11100111","00000000","11000001","00000001", + "00000000","00000001","00010001","10000001","00000001","00010000","11110100","00100000","11110100","00110000","11110100","00000100","00000000","11000111","00000111","01000111", + "10000111","11000111","00000111","01000111","10000111","11000111","00000111","01000111","10000111","11000111","11100100","11010100","11000100","01100100","00010100","00000100", + "10100100","10110100","11000100","11010100","11100100","11110100","00000100","00000010","00000111","11011111","00000010","01011111","00000010","00000111","10011111","00000010", + "00000000","11110111","11100111","00000010","00000111","01110000","11100111","00000010","00000111","00000001","00100111","11100111","00000010","00000111","11110000","11100111", + "00000010","00000111","00010000","11100111","00000000","11110000","11100111","00000000","00000111","00000001","00100000","11100111","00000001","00010000","11100111","00000100", + "11000100","11110111","11110100","11000100","10000100","11110111","11000100","11110111","11110100","00000100","00000000","01000100","00010111","11110100","01000100","00000011", + "11110111","11100111","10000100","11110000","11110111","00000100","00000000","10000100","00010111","11110100","10000100","00000100","11110111","10000111","00000001","11100111", + "00000000","01000111","00000111","00000000","01000111","00010111","11110111","00000000","11100110","11100111","01011111","00000001","10000001","00000001","00000010","00000111", + "00000111","00010111","00000111","00000000","01000111","00000000","00000111","11100111","00000010","00000111","00010000","11100111","10000000","00000001","00000111","00000001", + "11110111","11100111","00000001","01000111","00000111","00000111","00000000","00000000","11000001","00000001","00000000","01100101","00100000","01101110","01010111","01110111", + "01110011","01101110","01110010","01101110","01110101","01011010","00100001","00000000","00000000","00000000","00000000","00000000","00000000","00000000","00000000","00000000", + "00000000","00000000","00000000","00000000","00000000","00000000","00000000","00000000","00000000","00000000","00000000","00000000","00000000","00000000","00000000","00000000", + "00000000","00000000","00000000","00000000","00000000","00000000","00000000","00000000","00000000","00000000","00000000","00000000","00000000","00000000","00000000","00000000", + "00000000","00000000","00000000","00000000","00000000","00000000","00000000","00000000","00000000","00000000","00000000","00000000","00000000","00000000","00000000","00000000", + "00000000","00000000","00000000","00000000","00000000","00000000","00000000","00000000","00000000","00000000","00000000","00000000","00000000","00000000","00000000","00000000", + "00000000","00000000","00000000","00000000","00000000","00000000","00000000","00000000","00000000","00000000","00000000","00000000","00000000","00000000","00000000","00000000", + "00000000","00000000","00000000","00000000","00000000","00000000","00000000","00000000","00000000","00000000","00000000","00000000","00000000","00000000","00000000","00000000", + "00000000","00000000","00000000","00000000","00000000","00000000","00000000","00000000","00000000","00000000","00000000","00000000","00000000","00000000","00000000","00000000", + "00000000","00000000","00000000","00000000","00000000","00000000","00000000","00000000","00000000","00000000","00000000","00000000","00000000","00000000","00000000","00000000", + "00000000","00000000","00000000","00000000","00000000","00000000","00000000","00000000","00000000","00000000","00000000","00000000","00000000","00000000","00000000","00000000", + "00000000","00000000","00000000","00000000","00000000","00000000","00000000","00000000","00000000","00000000","00000000","00000000","00000000","00000000","00000000","00000000", + "00000000","00000000","00000000","00000000","00000000","00000000","00000000","00000000","00000000","00000000","00000000","00000000","00000000","00000000","00000000","00000000", + "00000000","00000000","00000000","00000000","00000000","00000000","00000000","00000000","00000000","00000000","00000000","00000000","00000000","00000000","00000000","00000000", + "00000000","00000000","00000000","00000000","00000000","00000000","00000000","00000000","00000000","00000000","00000000","00000000","00000000","00000000","00000000","00000000", + "00000000","00000000","00000000","00000000","00000000","00000000","00000000","00000000","00000000","00000000","00000000","00000000","00000000","00000000","00000000","00000000", + "00000000","00000000","00000000","00000000","00000000","00000000","00000000","00000000","00000000","00000000","00000000","00000000","00000000","00000000","00000000","00000000", + "00000000","00000000","00000000","00000000","00000000","00000000","00000000","00000000","00000000","00000000","00000000","00000000","00000000","00000000","00000000","00000000", + "00000000","00000000","00000000","00000000","00000000","00000000","00000000","00000000","00000000","00000000","00000000","00000000","00000000","00000000","00000000","00000000", + "00000000","00000000","00000000","00000000","00000000","00000000","00000000","00000000","00000000","00000000","00000000","00000000","00000000","00000000","00000000","00000000", + "00000000","00000000","00000000","00000000","00000000","00000000","00000000","00000000","00000000","00000000","00000000","00000000","00000000","00000000","00000000","00000000", + "00000000","00000000","00000000","00000000","00000000","00000000","00000000","00000000","00000000","00000000","00000000","00000000","00000000","00000000","00000000","00000000", + "00000000","00000000","00000000","00000000","00000000","00000000","00000000","00000000","00000000","00000000","00000000","00000000","00000000","00000000","00000000","00000000", + "00000000","00000000","00000000","00000000","00000000","00000000","00000000","00000000","00000000","00000000","00000000","00000000","00000000","00000000","00000000","00000000", + "00000000","00000000","00000000","00000000","00000000","00000000","00000000","00000000","00000000","00000000","00000000","00000000","00000000","00000000","00000000","00000000", + "00000000","00000000","00000000","00000000","00000000","00000000","00000000","00000000","00000000","00000000","00000000","00000000","00000000","00000000","00000000","00000000", + "00000000","00000000","00000000","00000000","00000000","00000000","00000000","00000000","00000000","00000000","00000000","00000000","00000000","00000000","00000000","00000000", + "00000000","00000000","00000000","00000000","00000000","00000000","00000000","00000000","00000000","00000000","00000000","00000000","00000000","00000000","00000000","00000000", + "00000000","00000000","00000000","00000000","00000000","00000000","00000000","00000000","00000000","00000000","00000000","00000000","00000000","00000000","00000000","00000000", + "00000000","00000000","00000000","00000000","00000000","00000000","00000000","00000000","00000000","00000000","00000000","00000000","00000000","00000000","00000000","00000000", + "00000000","00000000","00000000","00000000","00000000","00000000","00000000","00000000","00000000","00000000","00000000","00000000","00000000","00000000","00000000","00000000", + "00000000","00000000","00000000","00000000","00000000","00000000","00000000","00000000","00000000","00000000","00000000","00000000","00000000","00000000","00000000","00000000", + "00000000","00000000","00000000","00000000","00000000","00000000","00000000","00000000","00000000","00000000","00000000","00000000","00000000","00000000","00000000","00000000", + "00000000","00000000","00000000","00000000","00000000","00000000","00000000","00000000","00000000","00000000","00000000","00000000","00000000","00000000","00000000","00000000", + "00000000","00000000","00000000","00000000","00000000","00000000","00000000","00000000","00000000","00000000","00000000","00000000","00000000","00000000","00000000","00000000", + "00000000","00000000","00000000","00000000","00000000","00000000","00000000","00000000","00000000","00000000","00000000","00000000","00000000","00000000","00000000","00000000", + "00000000","00000000","00000000","00000000","00000000","00000000","00000000","00000000","00000000","00000000","00000000","00000000","00000000","00000000","00000000","00000000", + "00000000","00000000","00000000","00000000","00000000","00000000","00000000","00000000","00000000","00000000","00000000","00000000","00000000","00000000","00000000","00000000", + "00000000","00000000","00000000","00000000","00000000","00000000","00000000","00000000","00000000","00000000","00000000","00000000","00000000","00000000","00000000","00000000", + "00000000","00000000","00000000","00000000","00000000","00000000","00000000","00000000","00000000","00000000","00000000","00000000","00000000","00000000","00000000","00000000", + "00000000","00000000","00000000","00000000","00000000","00000000","00000000","00000000","00000000","00000000","00000000","00000000","00000000","00000000","00000000","00000000", + "00000000","00000000","00000000","00000000","00000000","00000000","00000000","00000000","00000000","00000000","00000000","00000000","00000000","00000000","00000000","00000000", + "00000000","00000000","00000000","00000000","00000000","00000000","00000000","00000000","00000000","00000000","00000000","00000000","00000000","00000000","00000000","00000000", + "00000000","00000000","00000000","00000000","00000000","00000000","00000000","00000000","00000000","00000000","00000000","00000000","00000000","00000000","00000000","00000000"); + signal ram_symbol3 : ram_type := ( + "00001011","00000000","00000000","00000000","00000000","00000000","00000000","00000000","11111110","11111110","11111110","11111110","11111110","11111110","11111110","11111110", + "11111100","11111100","11111101","11111101","11111101","11111101","11111101","11111101","11111100","01000100","00000011","00000011","00000011","00000011","00000010","00000010", + "00000010","00000010","00000001","00000001","00000001","00000001","00000000","00000000","00000000","00000000","00000100","00110000","00000000","11001011","10100000","00000000", + "01001010","00000000","01001001","00000000","00000000","00000000","11111111","00000000","01001000","11111111","00000000","01000111","00000000","00000000","00000000","00000000", + "00000000","00000000","11111110","00000000","00000000","10001000","00110000","00000000","10000000","00110000","00011001","00000000","11111110","00000000","00000010","11111110", + "11111110","00000000","11111110","00000000","00000000","00000001","00000010","00000000","11111110","00000000","00000010","11111110","00000000","00000001","00000010","00000000", + "11111110","00000000","00000010","11111110","11111110","00000000","11111110","11111111","00000000","00000000","00000001","00000010","00000000","11111110","00000000","00000010", + "11111110","11111110","00000000","00000001","00001111","00000000","00000001","00000010","00000000","11111110","00000000","00000010","11111110","11111110","00000000","00000001", + "00000000","00000001","00000010","00000000","11111110","00000000","00000000","00000010","11111110","11111110","00000000","11111110","11111000","00000000","11111110","11111110", + "11111110","00000000","00000000","00000001","00000001","00000010","00000000","11111110","00000000","00000010","11111110","11111110","11111110","00000000","11111110","00000000", + "11111110","00000000","11111111","11111110","00000000","00000000","00000000","11111110","00000000","00000001","00000000","11111110","00000000","00000000","00000001","00000010", + "00000000","11111010","00000100","00000100","00000110","00000000","11111110","00000000","11111100","00000000","11111100","11111110","10000000","01010010","00000000","00000000", + "00000000","00000000","00000001","00000001","00000001","00000001","00000010","00000010","00000010","00000010","11111011","11111011","11111011","11111010","11111011","11111011", + "11111100","11111100","11111100","11111100","11111100","11111100","11111110","11110000","00000001","11100001","11110000","11011111","11110000","00000100","11011011","11110000", + "00000000","00110100","00000000","11110000","00000100","00111110","00000000","11110000","00000100","00000000","00000000","00000000","11110000","00000001","00000000","00000000", + "11110000","00000001","00000000","00000000","11110000","00001111","00000000","11110000","00000000","11110000","00000000","00000000","11110000","00000100","00000000","11111110", + "11111110","00000000","11111110","11111101","11111101","00000000","11111110","00000000","11111110","11111110","00000001","11111110","00000000","11111110","11111110","00000000", + "11010011","11111110","11111110","00000010","00000000","11111110","00000001","11111110","00000000","11111110","11111110","11111111","00000000","11111011","11110000","00000000", + "11110000","00000000","11111100","11110000","00000000","00000000","00000011","11110000","00000000","00000000","11110101","11111111","00000000","00000001","11110000","00000001", + "00000000","00000000","00000100","11110000","00000000","11110000","00001000","00000000","11110000","00000001","00000000","00000000","00000001","11110000","00000000","11110000", + "00001111","00000000","11110000","00000000","00100000","11111110","00000000","00000000","00000000","00000001","00000000","01100010","01000110","01111010","01101001","11000011", + "01100011","00100000","00100000","01100101","01110100","01100101","00000000","00000000","00000000","00000000","00000000","00000000","00000000","00000000","00000000","00000000", + "00000000","00000000","00000000","00000000","00000000","00000000","00000000","00000000","00000000","00000000","00000000","00000000","00000000","00000000","00000000","00000000", + "00000000","00000000","00000000","00000000","00000000","00000000","00000000","00000000","00000000","00000000","00000000","00000000","00000000","00000000","00000000","00000000", + "00000000","00000000","00000000","00000000","00000000","00000000","00000000","00000000","00000000","00000000","00000000","00000000","00000000","00000000","00000000","00000000", + "00000000","00000000","00000000","00000000","00000000","00000000","00000000","00000000","00000000","00000000","00000000","00000000","00000000","00000000","00000000","00000000", + "00000000","00000000","00000000","00000000","00000000","00000000","00000000","00000000","00000000","00000000","00000000","00000000","00000000","00000000","00000000","00000000", + "00000000","00000000","00000000","00000000","00000000","00000000","00000000","00000000","00000000","00000000","00000000","00000000","00000000","00000000","00000000","00000000", + "00000000","00000000","00000000","00000000","00000000","00000000","00000000","00000000","00000000","00000000","00000000","00000000","00000000","00000000","00000000","00000000", + "00000000","00000000","00000000","00000000","00000000","00000000","00000000","00000000","00000000","00000000","00000000","00000000","00000000","00000000","00000000","00000000", + "00000000","00000000","00000000","00000000","00000000","00000000","00000000","00000000","00000000","00000000","00000000","00000000","00000000","00000000","00000000","00000000", + "00000000","00000000","00000000","00000000","00000000","00000000","00000000","00000000","00000000","00000000","00000000","00000000","00000000","00000000","00000000","00000000", + "00000000","00000000","00000000","00000000","00000000","00000000","00000000","00000000","00000000","00000000","00000000","00000000","00000000","00000000","00000000","00000000", + "00000000","00000000","00000000","00000000","00000000","00000000","00000000","00000000","00000000","00000000","00000000","00000000","00000000","00000000","00000000","00000000", + "00000000","00000000","00000000","00000000","00000000","00000000","00000000","00000000","00000000","00000000","00000000","00000000","00000000","00000000","00000000","00000000", + "00000000","00000000","00000000","00000000","00000000","00000000","00000000","00000000","00000000","00000000","00000000","00000000","00000000","00000000","00000000","00000000", + "00000000","00000000","00000000","00000000","00000000","00000000","00000000","00000000","00000000","00000000","00000000","00000000","00000000","00000000","00000000","00000000", + "00000000","00000000","00000000","00000000","00000000","00000000","00000000","00000000","00000000","00000000","00000000","00000000","00000000","00000000","00000000","00000000", + "00000000","00000000","00000000","00000000","00000000","00000000","00000000","00000000","00000000","00000000","00000000","00000000","00000000","00000000","00000000","00000000", + "00000000","00000000","00000000","00000000","00000000","00000000","00000000","00000000","00000000","00000000","00000000","00000000","00000000","00000000","00000000","00000000", + "00000000","00000000","00000000","00000000","00000000","00000000","00000000","00000000","00000000","00000000","00000000","00000000","00000000","00000000","00000000","00000000", + "00000000","00000000","00000000","00000000","00000000","00000000","00000000","00000000","00000000","00000000","00000000","00000000","00000000","00000000","00000000","00000000", + "00000000","00000000","00000000","00000000","00000000","00000000","00000000","00000000","00000000","00000000","00000000","00000000","00000000","00000000","00000000","00000000", + "00000000","00000000","00000000","00000000","00000000","00000000","00000000","00000000","00000000","00000000","00000000","00000000","00000000","00000000","00000000","00000000", + "00000000","00000000","00000000","00000000","00000000","00000000","00000000","00000000","00000000","00000000","00000000","00000000","00000000","00000000","00000000","00000000", + "00000000","00000000","00000000","00000000","00000000","00000000","00000000","00000000","00000000","00000000","00000000","00000000","00000000","00000000","00000000","00000000", + "00000000","00000000","00000000","00000000","00000000","00000000","00000000","00000000","00000000","00000000","00000000","00000000","00000000","00000000","00000000","00000000", + "00000000","00000000","00000000","00000000","00000000","00000000","00000000","00000000","00000000","00000000","00000000","00000000","00000000","00000000","00000000","00000000", + "00000000","00000000","00000000","00000000","00000000","00000000","00000000","00000000","00000000","00000000","00000000","00000000","00000000","00000000","00000000","00000000", + "00000000","00000000","00000000","00000000","00000000","00000000","00000000","00000000","00000000","00000000","00000000","00000000","00000000","00000000","00000000","00000000", + "00000000","00000000","00000000","00000000","00000000","00000000","00000000","00000000","00000000","00000000","00000000","00000000","00000000","00000000","00000000","00000000", + "00000000","00000000","00000000","00000000","00000000","00000000","00000000","00000000","00000000","00000000","00000000","00000000","00000000","00000000","00000000","00000000", + "00000000","00000000","00000000","00000000","00000000","00000000","00000000","00000000","00000000","00000000","00000000","00000000","00000000","00000000","00000000","00000000", + "00000000","00000000","00000000","00000000","00000000","00000000","00000000","00000000","00000000","00000000","00000000","00000000","00000000","00000000","00000000","00000000", + "00000000","00000000","00000000","00000000","00000000","00000000","00000000","00000000","00000000","00000000","00000000","00000000","00000000","00000000","00000000","00000000", + "00000000","00000000","00000000","00000000","00000000","00000000","00000000","00000000","00000000","00000000","00000000","00000000","00000000","00000000","00000000","00000000", + "00000000","00000000","00000000","00000000","00000000","00000000","00000000","00000000","00000000","00000000","00000000","00000000","00000000","00000000","00000000","00000000", + "00000000","00000000","00000000","00000000","00000000","00000000","00000000","00000000","00000000","00000000","00000000","00000000","00000000","00000000","00000000","00000000", + "00000000","00000000","00000000","00000000","00000000","00000000","00000000","00000000","00000000","00000000","00000000","00000000","00000000","00000000","00000000","00000000", + "00000000","00000000","00000000","00000000","00000000","00000000","00000000","00000000","00000000","00000000","00000000","00000000","00000000","00000000","00000000","00000000", + "00000000","00000000","00000000","00000000","00000000","00000000","00000000","00000000","00000000","00000000","00000000","00000000","00000000","00000000","00000000","00000000", + "00000000","00000000","00000000","00000000","00000000","00000000","00000000","00000000","00000000","00000000","00000000","00000000","00000000","00000000","00000000","00000000", + "00000000","00000000","00000000","00000000","00000000","00000000","00000000","00000000","00000000","00000000","00000000","00000000","00000000","00000000","00000000","00000000", + "00000000","00000000","00000000","00000000","00000000","00000000","00000000","00000000","00000000","00000000","00000000","00000000","00000000","00000000","00000000","00000000"); + signal zz_1 : std_logic_vector(7 downto 0); + signal zz_2 : std_logic_vector(7 downto 0); + signal zz_3 : std_logic_vector(7 downto 0); + signal zz_4 : std_logic_vector(7 downto 0); +begin + io_bus_cmd_ready <= io_bus_cmd_ready_read_buffer; + zz_io_bus_rsp_payload_data_2 <= pkg_resize(zz_io_bus_rsp_payload_data,10); + process (zz_1, zz_2, zz_3, zz_4) + begin + zz_ram_port0 <= zz_4 & zz_3 & zz_2 & zz_1; + end process; + process(io_mainClk) + begin + if rising_edge(io_mainClk) then + if io_bus_cmd_valid = '1' then + zz_1 <= ram_symbol0(to_integer(zz_io_bus_rsp_payload_data_2)); + zz_2 <= ram_symbol1(to_integer(zz_io_bus_rsp_payload_data_2)); + zz_3 <= ram_symbol2(to_integer(zz_io_bus_rsp_payload_data_2)); + zz_4 <= ram_symbol3(to_integer(zz_io_bus_rsp_payload_data_2)); + end if; + end if; + end process; + + process(io_mainClk) + begin + if rising_edge(io_mainClk) then + if io_bus_cmd_payload_mask(0) = '1' and io_bus_cmd_valid = '1' and io_bus_cmd_payload_write = '1' then + ram_symbol0(to_integer(zz_io_bus_rsp_payload_data_2)) <= zz_io_bus_rsp_payload_data_1(7 downto 0); + end if; + if io_bus_cmd_payload_mask(1) = '1' and io_bus_cmd_valid = '1' and io_bus_cmd_payload_write = '1' then + ram_symbol1(to_integer(zz_io_bus_rsp_payload_data_2)) <= zz_io_bus_rsp_payload_data_1(15 downto 8); + end if; + if io_bus_cmd_payload_mask(2) = '1' and io_bus_cmd_valid = '1' and io_bus_cmd_payload_write = '1' then + ram_symbol2(to_integer(zz_io_bus_rsp_payload_data_2)) <= zz_io_bus_rsp_payload_data_1(23 downto 16); + end if; + if io_bus_cmd_payload_mask(3) = '1' and io_bus_cmd_valid = '1' and io_bus_cmd_payload_write = '1' then + ram_symbol3(to_integer(zz_io_bus_rsp_payload_data_2)) <= zz_io_bus_rsp_payload_data_1(31 downto 24); + end if; + end if; + end process; + + io_bus_cmd_fire <= (io_bus_cmd_valid and io_bus_cmd_ready_read_buffer); + io_bus_rsp_valid <= zz_io_bus_rsp_valid; + zz_io_bus_rsp_payload_data <= pkg_shiftRight(io_bus_cmd_payload_address,2); + zz_io_bus_rsp_payload_data_1 <= io_bus_cmd_payload_data; + io_bus_rsp_payload_data <= zz_ram_port0; + io_bus_cmd_ready_read_buffer <= pkg_toStdLogic(true); + process(io_mainClk, resetCtrl_systemReset) + begin + if resetCtrl_systemReset = '1' then + zz_io_bus_rsp_valid <= pkg_toStdLogic(false); + elsif rising_edge(io_mainClk) then + zz_io_bus_rsp_valid <= (io_bus_cmd_fire and (not io_bus_cmd_payload_write)); + end if; + end process; + +end arch; diff --git a/flow/platforms/ihp-sg13g2/cdl/RM_IHPSG13_1P_1024x32_c2_bm_bist.cdl b/flow/platforms/ihp-sg13g2/cdl/RM_IHPSG13_1P_1024x32_c2_bm_bist.cdl new file mode 100644 index 0000000000..b35e6fad6d --- /dev/null +++ b/flow/platforms/ihp-sg13g2/cdl/RM_IHPSG13_1P_1024x32_c2_bm_bist.cdl @@ -0,0 +1,6423 @@ +* ------------------------------------------------------ +* +* Copyright 2025 IHP PDK Authors +* +* Licensed under the Apache License, Version 2.0 (the "License"); +* you may not use this file except in compliance with the License. +* You may obtain a copy of the License at +* +* https://www.apache.org/licenses/LICENSE-2.0 +* +* Unless required by applicable law or agreed to in writing, software +* distributed under the License is distributed on an "AS IS" BASIS, +* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +* See the License for the specific language governing permissions and +* limitations under the License. +* +* Generated on Thu Aug 21 20:48:28 2025 +* +* ------------------------------------------------------ + +.SUBCKT RM_IHPSG13_1024x32_c2_1P_BITKIT_CORNER NW PW VDD VSS +.ENDS +.SUBCKT RM_IHPSG13_1024x32_c2_1P_BITKIT_16x2_CORNER VDD_CORE VSS +XI16 VDD_CORE VSS VDD_CORE VSS / ++ RM_IHPSG13_1024x32_c2_1P_BITKIT_CORNER +.ENDS +.SUBCKT RM_IHPSG13_1024x32_c2_1P_BITKIT_EDGE_LR LWL NW PW VDD VSS +MN1 VSS LWL VSS VSS sg13_lv_nmos m=1 w=300.0n l=130.00n ng=1 nrd=0 nrs=0 +MN0 VSS net9 VSS VSS sg13_lv_nmos m=1 w=300.0n l=130.00n ng=1 nrd=0 nrs=0 +.ENDS +.SUBCKT RM_IHPSG13_1024x32_c2_1P_BITKIT_16x2_EDGE_LR A_WL<15> A_WL<14> A_WL<13> A_WL<12> ++ A_WL<11> A_WL<10> A_WL<9> A_WL<8> A_WL<7> A_WL<6> A_WL<5> A_WL<4> A_WL<3> ++ A_WL<2> A_WL<1> A_WL<0> VDD_CORE VSS +XI0<15> A_WL<15> VDD_CORE VSS VDD_CORE VSS / ++ RM_IHPSG13_1024x32_c2_1P_BITKIT_EDGE_LR +XI0<14> A_WL<14> VDD_CORE VSS VDD_CORE VSS / ++ RM_IHPSG13_1024x32_c2_1P_BITKIT_EDGE_LR +XI0<13> A_WL<13> VDD_CORE VSS VDD_CORE VSS / ++ RM_IHPSG13_1024x32_c2_1P_BITKIT_EDGE_LR +XI0<12> A_WL<12> VDD_CORE VSS VDD_CORE VSS / ++ RM_IHPSG13_1024x32_c2_1P_BITKIT_EDGE_LR +XI0<11> A_WL<11> VDD_CORE VSS VDD_CORE VSS / ++ RM_IHPSG13_1024x32_c2_1P_BITKIT_EDGE_LR +XI0<10> A_WL<10> VDD_CORE VSS VDD_CORE VSS / ++ RM_IHPSG13_1024x32_c2_1P_BITKIT_EDGE_LR +XI0<9> A_WL<9> VDD_CORE VSS VDD_CORE VSS / ++ RM_IHPSG13_1024x32_c2_1P_BITKIT_EDGE_LR +XI0<8> A_WL<8> VDD_CORE VSS VDD_CORE VSS / ++ RM_IHPSG13_1024x32_c2_1P_BITKIT_EDGE_LR +XI0<7> A_WL<7> VDD_CORE VSS VDD_CORE VSS / ++ RM_IHPSG13_1024x32_c2_1P_BITKIT_EDGE_LR +XI0<6> A_WL<6> VDD_CORE VSS VDD_CORE VSS / ++ RM_IHPSG13_1024x32_c2_1P_BITKIT_EDGE_LR +XI0<5> A_WL<5> VDD_CORE VSS VDD_CORE VSS / ++ RM_IHPSG13_1024x32_c2_1P_BITKIT_EDGE_LR +XI0<4> A_WL<4> VDD_CORE VSS VDD_CORE VSS / ++ RM_IHPSG13_1024x32_c2_1P_BITKIT_EDGE_LR +XI0<3> A_WL<3> VDD_CORE VSS VDD_CORE VSS / ++ RM_IHPSG13_1024x32_c2_1P_BITKIT_EDGE_LR +XI0<2> A_WL<2> VDD_CORE VSS VDD_CORE VSS / ++ RM_IHPSG13_1024x32_c2_1P_BITKIT_EDGE_LR +XI0<1> A_WL<1> VDD_CORE VSS VDD_CORE VSS / ++ RM_IHPSG13_1024x32_c2_1P_BITKIT_EDGE_LR +XI0<0> A_WL<0> VDD_CORE VSS VDD_CORE VSS / ++ RM_IHPSG13_1024x32_c2_1P_BITKIT_EDGE_LR +.ENDS +.SUBCKT RM_IHPSG13_1024x32_c2_1P_BITKIT_CELL BLC_BOT BLC_TOP BLT_BOT BLT_TOP LWL NW PW ++ RWL VDD VSS +MN0 NC NT VSS PW sg13_lv_nmos m=1 w=300.0n l=130.00n ng=1 nrd=0 nrs=0 +MN1 NT NC VSS PW sg13_lv_nmos m=1 w=300.0n l=130.00n ng=1 nrd=0 nrs=0 +MN3 NC RWL BLC_TOP PW sg13_lv_nmos m=1 w=300.0n l=130.00n ng=1 nrd=0 nrs=0 +MN2 BLT_BOT LWL NT PW sg13_lv_nmos m=1 w=300.0n l=130.00n ng=1 nrd=0 nrs=0 +MP1 NT NC VDD NW sg13_lv_pmos m=1 w=150.00n l=130.00n ng=1 nrd=0 nrs=0 +MP0 NC NT VDD NW sg13_lv_pmos m=1 w=150.00n l=130.00n ng=1 nrd=0 nrs=0 +R1 BLC_BOT BLC_TOP lvsres w=2.6e-07 l=6e-07 +R0 BLT_BOT BLT_TOP lvsres w=2.6e-07 l=6e-07 +R2 RWL LWL lvsres w=2.6e-07 l=6e-07 +.ENDS +.SUBCKT RM_IHPSG13_1024x32_c2_1P_BITKIT_16x2_SRAM A_BLC_BOT<1> A_BLC_BOT<0> A_BLC_TOP<1> ++ A_BLC_TOP<0> A_BLT_BOT<1> A_BLT_BOT<0> A_BLT_TOP<1> A_BLT_TOP<0> A_LWL<15> ++ A_LWL<14> A_LWL<13> A_LWL<12> A_LWL<11> A_LWL<10> A_LWL<9> A_LWL<8> A_LWL<7> ++ A_LWL<6> A_LWL<5> A_LWL<4> A_LWL<3> A_LWL<2> A_LWL<1> A_LWL<0> A_RWL<15> ++ A_RWL<14> A_RWL<13> A_RWL<12> A_RWL<11> A_RWL<10> A_RWL<9> A_RWL<8> A_RWL<7> ++ A_RWL<6> A_RWL<5> A_RWL<4> A_RWL<3> A_RWL<2> A_RWL<1> A_RWL<0> VDD_CORE ++ VSS +XCELL<31> A_BLC_TOP<1> A_RBLC<15> A_BLT_TOP<1> A_RBLT<15> A_RWL<15> ++ VDD_CORE VSS A_XWL<15> VDD_CORE VSS / ++ RM_IHPSG13_1024x32_c2_1P_BITKIT_CELL +XCELL<30> A_RBLC<14> A_RBLC<15> A_RBLT<14> A_RBLT<15> A_RWL<14> VDD_CORE ++ VSS A_XWL<14> VDD_CORE VSS / RM_IHPSG13_1024x32_c2_1P_BITKIT_CELL +XCELL<29> A_RBLC<14> A_RBLC<13> A_RBLT<14> A_RBLT<13> A_RWL<13> VDD_CORE ++ VSS A_XWL<13> VDD_CORE VSS / RM_IHPSG13_1024x32_c2_1P_BITKIT_CELL +XCELL<28> A_RBLC<12> A_RBLC<13> A_RBLT<12> A_RBLT<13> A_RWL<12> VDD_CORE ++ VSS A_XWL<12> VDD_CORE VSS / RM_IHPSG13_1024x32_c2_1P_BITKIT_CELL +XCELL<27> A_RBLC<12> A_RBLC<11> A_RBLT<12> A_RBLT<11> A_RWL<11> VDD_CORE ++ VSS A_XWL<11> VDD_CORE VSS / RM_IHPSG13_1024x32_c2_1P_BITKIT_CELL +XCELL<26> A_RBLC<10> A_RBLC<11> A_RBLT<10> A_RBLT<11> A_RWL<10> VDD_CORE ++ VSS A_XWL<10> VDD_CORE VSS / RM_IHPSG13_1024x32_c2_1P_BITKIT_CELL +XCELL<25> A_RBLC<10> A_RBLC<9> A_RBLT<10> A_RBLT<9> A_RWL<9> VDD_CORE ++ VSS A_XWL<9> VDD_CORE VSS / RM_IHPSG13_1024x32_c2_1P_BITKIT_CELL +XCELL<24> A_RBLC<8> A_RBLC<9> A_RBLT<8> A_RBLT<9> A_RWL<8> VDD_CORE ++ VSS A_XWL<8> VDD_CORE VSS / RM_IHPSG13_1024x32_c2_1P_BITKIT_CELL +XCELL<23> A_RBLC<8> A_RBLC<7> A_RBLT<8> A_RBLT<7> A_RWL<7> VDD_CORE ++ VSS A_XWL<7> VDD_CORE VSS / RM_IHPSG13_1024x32_c2_1P_BITKIT_CELL +XCELL<22> A_RBLC<6> A_RBLC<7> A_RBLT<6> A_RBLT<7> A_RWL<6> VDD_CORE ++ VSS A_XWL<6> VDD_CORE VSS / RM_IHPSG13_1024x32_c2_1P_BITKIT_CELL +XCELL<21> A_RBLC<6> A_RBLC<5> A_RBLT<6> A_RBLT<5> A_RWL<5> VDD_CORE ++ VSS A_XWL<5> VDD_CORE VSS / RM_IHPSG13_1024x32_c2_1P_BITKIT_CELL +XCELL<20> A_RBLC<4> A_RBLC<5> A_RBLT<4> A_RBLT<5> A_RWL<4> VDD_CORE ++ VSS A_XWL<4> VDD_CORE VSS / RM_IHPSG13_1024x32_c2_1P_BITKIT_CELL +XCELL<19> A_RBLC<4> A_RBLC<3> A_RBLT<4> A_RBLT<3> A_RWL<3> VDD_CORE ++ VSS A_XWL<3> VDD_CORE VSS / RM_IHPSG13_1024x32_c2_1P_BITKIT_CELL +XCELL<18> A_RBLC<2> A_RBLC<3> A_RBLT<2> A_RBLT<3> A_RWL<2> VDD_CORE ++ VSS A_XWL<2> VDD_CORE VSS / RM_IHPSG13_1024x32_c2_1P_BITKIT_CELL +XCELL<17> A_RBLC<2> A_RBLC<1> A_RBLT<2> A_RBLT<1> A_RWL<1> VDD_CORE ++ VSS A_XWL<1> VDD_CORE VSS / RM_IHPSG13_1024x32_c2_1P_BITKIT_CELL +XCELL<16> A_BLC_BOT<1> A_RBLC<1> A_BLT_BOT<1> A_RBLT<1> A_RWL<0> VDD_CORE ++ VSS A_XWL<0> VDD_CORE VSS / RM_IHPSG13_1024x32_c2_1P_BITKIT_CELL +XCELL<15> A_BLC_TOP<0> A_LBLC<15> A_BLT_TOP<0> A_LBLT<15> A_LWL<15> ++ VDD_CORE VSS A_XWL<15> VDD_CORE VSS / ++ RM_IHPSG13_1024x32_c2_1P_BITKIT_CELL +XCELL<14> A_LBLC<14> A_LBLC<15> A_LBLT<14> A_LBLT<15> A_LWL<14> VDD_CORE ++ VSS A_XWL<14> VDD_CORE VSS / RM_IHPSG13_1024x32_c2_1P_BITKIT_CELL +XCELL<13> A_LBLC<14> A_LBLC<13> A_LBLT<14> A_LBLT<13> A_LWL<13> VDD_CORE ++ VSS A_XWL<13> VDD_CORE VSS / RM_IHPSG13_1024x32_c2_1P_BITKIT_CELL +XCELL<12> A_LBLC<12> A_LBLC<13> A_LBLT<12> A_LBLT<13> A_LWL<12> VDD_CORE ++ VSS A_XWL<12> VDD_CORE VSS / RM_IHPSG13_1024x32_c2_1P_BITKIT_CELL +XCELL<11> A_LBLC<12> A_LBLC<11> A_LBLT<12> A_LBLT<11> A_LWL<11> VDD_CORE ++ VSS A_XWL<11> VDD_CORE VSS / RM_IHPSG13_1024x32_c2_1P_BITKIT_CELL +XCELL<10> A_LBLC<10> A_LBLC<11> A_LBLT<10> A_LBLT<11> A_LWL<10> VDD_CORE ++ VSS A_XWL<10> VDD_CORE VSS / RM_IHPSG13_1024x32_c2_1P_BITKIT_CELL +XCELL<9> A_LBLC<10> A_LBLC<9> A_LBLT<10> A_LBLT<9> A_LWL<9> VDD_CORE ++ VSS A_XWL<9> VDD_CORE VSS / RM_IHPSG13_1024x32_c2_1P_BITKIT_CELL +XCELL<8> A_LBLC<8> A_LBLC<9> A_LBLT<8> A_LBLT<9> A_LWL<8> VDD_CORE ++ VSS A_XWL<8> VDD_CORE VSS / RM_IHPSG13_1024x32_c2_1P_BITKIT_CELL +XCELL<7> A_LBLC<8> A_LBLC<7> A_LBLT<8> A_LBLT<7> A_LWL<7> VDD_CORE ++ VSS A_XWL<7> VDD_CORE VSS / RM_IHPSG13_1024x32_c2_1P_BITKIT_CELL +XCELL<6> A_LBLC<6> A_LBLC<7> A_LBLT<6> A_LBLT<7> A_LWL<6> VDD_CORE ++ VSS A_XWL<6> VDD_CORE VSS / RM_IHPSG13_1024x32_c2_1P_BITKIT_CELL +XCELL<5> A_LBLC<6> A_LBLC<5> A_LBLT<6> A_LBLT<5> A_LWL<5> VDD_CORE ++ VSS A_XWL<5> VDD_CORE VSS / RM_IHPSG13_1024x32_c2_1P_BITKIT_CELL +XCELL<4> A_LBLC<4> A_LBLC<5> A_LBLT<4> A_LBLT<5> A_LWL<4> VDD_CORE ++ VSS A_XWL<4> VDD_CORE VSS / RM_IHPSG13_1024x32_c2_1P_BITKIT_CELL +XCELL<3> A_LBLC<4> A_LBLC<3> A_LBLT<4> A_LBLT<3> A_LWL<3> VDD_CORE ++ VSS A_XWL<3> VDD_CORE VSS / RM_IHPSG13_1024x32_c2_1P_BITKIT_CELL +XCELL<2> A_LBLC<2> A_LBLC<3> A_LBLT<2> A_LBLT<3> A_LWL<2> VDD_CORE ++ VSS A_XWL<2> VDD_CORE VSS / RM_IHPSG13_1024x32_c2_1P_BITKIT_CELL +XCELL<1> A_LBLC<2> A_LBLC<1> A_LBLT<2> A_LBLT<1> A_LWL<1> VDD_CORE ++ VSS A_XWL<1> VDD_CORE VSS / RM_IHPSG13_1024x32_c2_1P_BITKIT_CELL +XCELL<0> A_BLC_BOT<0> A_LBLC<1> A_BLT_BOT<0> A_LBLT<1> A_LWL<0> VDD_CORE ++ VSS A_XWL<0> VDD_CORE VSS / RM_IHPSG13_1024x32_c2_1P_BITKIT_CELL +.ENDS +.SUBCKT RM_IHPSG13_1024x32_c2_1P_BITKIT_EDGE_TB BLC BLT NW PW VDD VSS +.ENDS +.SUBCKT RM_IHPSG13_1024x32_c2_1P_BITKIT_16x2_EDGE_TB A_BLC<1> A_BLC<0> A_BLT<1> A_BLT<0> ++ VDD_CORE VSS +XEDGE<1> A_BLC<1> A_BLT<1> VDD_CORE VSS VDD_CORE VSS ++ / RM_IHPSG13_1024x32_c2_1P_BITKIT_EDGE_TB +XEDGE<0> A_BLC<0> A_BLT<0> VDD_CORE VSS VDD_CORE VSS ++ / RM_IHPSG13_1024x32_c2_1P_BITKIT_EDGE_TB +.ENDS + +.SUBCKT RSC_IHPSG13_CBUFX4 A Z VDD VSS +MN0 net9 A VSS VSS sg13_lv_nmos m=1 w=705.000n l=130.00n ng=1 nrd=0 ++ nrs=0 +MN1 Z net9 VSS VSS sg13_lv_nmos m=1 w=1.41u l=130.00n ng=2 nrd=0 nrs=0 +MP0 net9 A VDD VDD sg13_lv_pmos m=1 w=1.62u l=130.00n ng=1 nrd=0 nrs=0 +MP1 Z net9 VDD VDD sg13_lv_pmos m=1 w=3.24u l=130.00n ng=2 nrd=0 nrs=0 +.ENDS +.SUBCKT RM_IHPSG13_1024x32_c2_1P_COLDRV13X4 ADDR_COL_I<1> ADDR_COL_I<0> ADDR_COL_O<1> ++ ADDR_COL_O<0> ADDR_DEC_I<7> ADDR_DEC_I<6> ADDR_DEC_I<5> ADDR_DEC_I<4> ++ ADDR_DEC_I<3> ADDR_DEC_I<2> ADDR_DEC_I<1> ADDR_DEC_I<0> ADDR_DEC_O<7> ++ ADDR_DEC_O<6> ADDR_DEC_O<5> ADDR_DEC_O<4> ADDR_DEC_O<3> ADDR_DEC_O<2> ++ ADDR_DEC_O<1> ADDR_DEC_O<0> DCLK_I DCLK_O RCLK_I RCLK_O WCLK_I WCLK_O ++ VDD VSS +XADDR_COL_DRV<1> ADDR_COL_I<1> ADDR_COL_O<1> VDD VSS / ++ RSC_IHPSG13_CBUFX4 +XADDR_COL_DRV<0> ADDR_COL_I<0> ADDR_COL_O<0> VDD VSS / ++ RSC_IHPSG13_CBUFX4 +XADDR_DEC_DRV<7> ADDR_DEC_I<7> ADDR_DEC_O<7> VDD VSS / ++ RSC_IHPSG13_CBUFX4 +XADDR_DEC_DRV<6> ADDR_DEC_I<6> ADDR_DEC_O<6> VDD VSS / ++ RSC_IHPSG13_CBUFX4 +XADDR_DEC_DRV<5> ADDR_DEC_I<5> ADDR_DEC_O<5> VDD VSS / ++ RSC_IHPSG13_CBUFX4 +XADDR_DEC_DRV<4> ADDR_DEC_I<4> ADDR_DEC_O<4> VDD VSS / ++ RSC_IHPSG13_CBUFX4 +XADDR_DEC_DRV<3> ADDR_DEC_I<3> ADDR_DEC_O<3> VDD VSS / ++ RSC_IHPSG13_CBUFX4 +XADDR_DEC_DRV<2> ADDR_DEC_I<2> ADDR_DEC_O<2> VDD VSS / ++ RSC_IHPSG13_CBUFX4 +XADDR_DEC_DRV<1> ADDR_DEC_I<1> ADDR_DEC_O<1> VDD VSS / ++ RSC_IHPSG13_CBUFX4 +XADDR_DEC_DRV<0> ADDR_DEC_I<0> ADDR_DEC_O<0> VDD VSS / ++ RSC_IHPSG13_CBUFX4 +XDCLK_DRV DCLK_I DCLK_O VDD VSS / RSC_IHPSG13_CBUFX4 +XRCLK_DRV RCLK_I RCLK_O VDD VSS / RSC_IHPSG13_CBUFX4 +XWCLK_DRV WCLK_I WCLK_O VDD VSS / RSC_IHPSG13_CBUFX4 +.ENDS +.SUBCKT RSC_IHPSG13_WLDRVX4 A Z VDD VSS +MN1 Z net6 VSS VSS sg13_lv_nmos m=1 w=705.000n l=130.00n ng=1 nrd=0 ++ nrs=0 +MN0 net6 A VSS VSS sg13_lv_nmos m=1 w=900.0n l=130.00n ng=1 nrd=0 nrs=0 +MP1 Z net6 VDD VDD sg13_lv_pmos m=1 w=3.24u l=130.00n ng=2 nrd=0 nrs=0 +MP0 net6 A VDD VDD sg13_lv_pmos m=1 w=900.0n l=130.00n ng=1 nrd=0 nrs=0 +.ENDS +.SUBCKT RM_IHPSG13_1024x32_c2_1P_WLDRV16X4 A<15> A<14> A<13> A<12> A<11> A<10> A<9> A<8> ++ A<7> A<6> A<5> A<4> A<3> A<2> A<1> A<0> Z<15> Z<14> Z<13> Z<12> Z<11> Z<10> ++ Z<9> Z<8> Z<7> Z<6> Z<5> Z<4> Z<3> Z<2> Z<1> Z<0> VDD VSS +XBUF<15> A<15> Z<15> VDD VSS / RSC_IHPSG13_WLDRVX4 +XBUF<14> A<14> Z<14> VDD VSS / RSC_IHPSG13_WLDRVX4 +XBUF<13> A<13> Z<13> VDD VSS / RSC_IHPSG13_WLDRVX4 +XBUF<12> A<12> Z<12> VDD VSS / RSC_IHPSG13_WLDRVX4 +XBUF<11> A<11> Z<11> VDD VSS / RSC_IHPSG13_WLDRVX4 +XBUF<10> A<10> Z<10> VDD VSS / RSC_IHPSG13_WLDRVX4 +XBUF<9> A<9> Z<9> VDD VSS / RSC_IHPSG13_WLDRVX4 +XBUF<8> A<8> Z<8> VDD VSS / RSC_IHPSG13_WLDRVX4 +XBUF<7> A<7> Z<7> VDD VSS / RSC_IHPSG13_WLDRVX4 +XBUF<6> A<6> Z<6> VDD VSS / RSC_IHPSG13_WLDRVX4 +XBUF<5> A<5> Z<5> VDD VSS / RSC_IHPSG13_WLDRVX4 +XBUF<4> A<4> Z<4> VDD VSS / RSC_IHPSG13_WLDRVX4 +XBUF<3> A<3> Z<3> VDD VSS / RSC_IHPSG13_WLDRVX4 +XBUF<2> A<2> Z<2> VDD VSS / RSC_IHPSG13_WLDRVX4 +XBUF<1> A<1> Z<1> VDD VSS / RSC_IHPSG13_WLDRVX4 +XBUF<0> A<0> Z<0> VDD VSS / RSC_IHPSG13_WLDRVX4 +.ENDS +.SUBCKT RSC_IHPSG13_FILLCAP8 VDD VSS +MN0 vss_r vdd_r VSS VSS sg13_lv_nmos m=1 w=4.98u l=130.00n ng=6 nrd=0 ++ nrs=0 +MP0 vdd_r vss_r VDD VDD sg13_lv_pmos m=1 w=6.48u l=385.000n ng=4 nrd=0 ++ nrs=0 +.ENDS +.SUBCKT RSC_IHPSG13_LHPQX2 CP D Q VDD VSS +MN3 QIN CPN net14 VSS sg13_lv_nmos m=1 w=480.00n l=130.00n ng=1 nrd=0 nrs=0 +MN2 net14 net10 VSS VSS sg13_lv_nmos m=1 w=480.00n l=130.00n ng=1 ++ nrd=0 nrs=0 +MN5 net21 D VSS VSS sg13_lv_nmos m=1 w=870.00n l=130.00n ng=1 nrd=0 ++ nrs=0 +MN6 QIN CP net21 VSS sg13_lv_nmos m=1 w=870.00n l=130.00n ng=1 nrd=0 nrs=0 +MN1 net10 QIN VSS VSS sg13_lv_nmos m=1 w=480.00n l=130.00n ng=1 nrd=0 ++ nrs=0 +MN0 CPN CP VSS VSS sg13_lv_nmos m=1 w=480.00n l=130.00n ng=1 nrd=0 ++ nrs=0 +MN4 Q QIN VSS VSS sg13_lv_nmos m=1 w=980.00n l=130.00n ng=1 nrd=0 nrs=0 +MP2 QIN CP net16 VDD sg13_lv_pmos m=1 w=480.00n l=130.00n ng=1 nrd=0 nrs=0 +MP0 CPN CP VDD VDD sg13_lv_pmos m=1 w=480.00n l=130.00n ng=1 nrd=0 ++ nrs=0 +MP4 Q QIN VDD VDD sg13_lv_pmos m=1 w=1.62u l=130.00n ng=1 nrd=0 nrs=0 +MP3 net10 QIN VDD VDD sg13_lv_pmos m=1 w=480.00n l=130.00n ng=1 nrd=0 ++ nrs=0 +MP1 net16 net10 VDD VDD sg13_lv_pmos m=1 w=480.00n l=130.00n ng=1 ++ nrd=0 nrs=0 +MP6 QIN CPN net20 VDD sg13_lv_pmos m=1 w=975.000n l=130.00n ng=1 nrd=0 ++ nrs=0 +MP5 net20 D VDD VDD sg13_lv_pmos m=1 w=975.000n l=130.00n ng=1 nrd=0 ++ nrs=0 +.ENDS +.SUBCKT RSC_IHPSG13_NAND2X2 A B Z VDD VSS +MP1 Z B VDD VDD sg13_lv_pmos m=1 w=1.62u l=130.00n ng=1 nrd=0 nrs=0 +MP0 Z A VDD VDD sg13_lv_pmos m=1 w=1.62u l=130.00n ng=1 nrd=0 nrs=0 +MN0 Z B net7 VSS sg13_lv_nmos m=1 w=980.00n l=130.00n ng=1 nrd=0 nrs=0 +MN1 net7 A VSS VSS sg13_lv_nmos m=1 w=980.00n l=130.00n ng=1 nrd=0 ++ nrs=0 +.ENDS +.SUBCKT RSC_IHPSG13_CINVX4 A Z VDD VSS +MN0 Z A VSS VSS sg13_lv_nmos m=1 w=1.41u l=130.00n ng=2 nrd=0 nrs=0 +MP0 Z A VDD VDD sg13_lv_pmos m=1 w=3.24u l=130.00n ng=2 nrd=0 nrs=0 +.ENDS +.SUBCKT RSC_IHPSG13_CINVX2 A Z VDD VSS +MN0 Z A VSS VSS sg13_lv_nmos m=1 w=705.000n l=130.00n ng=1 nrd=0 nrs=0 +MP0 Z A VDD VDD sg13_lv_pmos m=1 w=1.62u l=130.00n ng=1 nrd=0 nrs=0 +.ENDS +.SUBCKT RSC_IHPSG13_INVX2 A Z VDD VSS +MN0 Z A VSS VSS sg13_lv_nmos m=1 w=980.00n l=130.00n ng=1 nrd=0 nrs=0 +MP0 Z A VDD VDD sg13_lv_pmos m=1 w=1.62u l=130.00n ng=1 nrd=0 nrs=0 +.ENDS +.SUBCKT RSC_IHPSG13_NAND3X2 A B C Z VDD VSS +MP2 Z A VDD VDD sg13_lv_pmos m=1 w=1.62u l=130.00n ng=1 nrd=0 nrs=0 +MP1 Z B VDD VDD sg13_lv_pmos m=1 w=1.62u l=130.00n ng=1 nrd=0 nrs=0 +MP0 Z C VDD VDD sg13_lv_pmos m=1 w=1.62u l=130.00n ng=1 nrd=0 nrs=0 +MN1 net12 B net16 VSS sg13_lv_nmos m=1 w=980.00n l=130.00n ng=1 nrd=0 nrs=0 +MN0 Z C net12 VSS sg13_lv_nmos m=1 w=980.00n l=130.00n ng=1 nrd=0 nrs=0 +MN2 net16 A VSS VSS sg13_lv_nmos m=1 w=980.00n l=130.00n ng=1 nrd=0 ++ nrs=0 +.ENDS +.SUBCKT RSC_IHPSG13_NOR3X2 A B C Z VDD VSS +MP0 net13 A VDD VDD sg13_lv_pmos m=1 w=1.62u l=130.00n ng=1 nrd=0 nrs=0 +MP2 Z C net10 VDD sg13_lv_pmos m=1 w=1.62u l=130.00n ng=1 nrd=0 nrs=0 +MP1 net10 B net13 VDD sg13_lv_pmos m=1 w=1.62u l=130.00n ng=1 nrd=0 nrs=0 +MN1 Z B VSS VSS sg13_lv_nmos m=1 w=875.000n l=130.00n ng=1 nrd=0 nrs=0 +MN0 Z C VSS VSS sg13_lv_nmos m=1 w=875.000n l=130.00n ng=1 nrd=0 nrs=0 +MN2 Z A VSS VSS sg13_lv_nmos m=1 w=875.000n l=130.00n ng=1 nrd=0 nrs=0 +.ENDS +.SUBCKT RSC_IHPSG13_FILLCAP4 VDD VSS +MN0 vss_r vdd_r VSS VSS sg13_lv_nmos m=1 w=2.49u l=130.00n ng=3 nrd=0 ++ nrs=0 +MP0 vdd_r vss_r VDD VDD sg13_lv_pmos m=1 w=3.24u l=385.000n ng=2 nrd=0 ++ nrs=0 +.ENDS +.SUBCKT RSC_IHPSG13_MET2RES A B +R0 B A lvsres w=2.6e-07 l=6e-07 +.ENDS +.SUBCKT RM_IHPSG13_1024x32_c2_1P_DEC04 ADDR<3> ADDR<2> ADDR<1> ADDR<0> CS ECLK_H_BOT ++ ECLK_H_TOP ECLK_L_BOT ECLK_L_TOP WL<15> WL<14> WL<13> WL<12> WL<11> WL<10> ++ WL<9> WL<8> WL<7> WL<6> WL<5> WL<4> WL<3> WL<2> WL<1> WL<0> VDD VSS +XLATCH<3> CS ADDR<3> PADR<3> VDD VSS / RSC_IHPSG13_LHPQX2 +XLATCH<2> CS ADDR<2> PADR<2> VDD VSS / RSC_IHPSG13_LHPQX2 +XLATCH<1> CS ADDR<1> PADR<1> VDD VSS / RSC_IHPSG13_LHPQX2 +XLATCH<0> CS ADDR<0> PADR<0> VDD VSS / RSC_IHPSG13_LHPQX2 +XI0<3> PADR<1> PADR<0> sel01<3> VDD VSS / RSC_IHPSG13_NAND2X2 +XI0<2> PADR<1> NADR<0> sel01<2> VDD VSS / RSC_IHPSG13_NAND2X2 +XI0<1> NADR<1> PADR<0> sel01<1> VDD VSS / RSC_IHPSG13_NAND2X2 +XI0<0> NADR<1> NADR<0> sel01<0> VDD VSS / RSC_IHPSG13_NAND2X2 +XI4 ECLK_L_BOT EN VDD VSS / RSC_IHPSG13_CINVX4 +XI5 ECLK_H_BOT ECLK_L_BOT VDD VSS / RSC_IHPSG13_CINVX2 +XI3<3> PADR<3> NADR<3> VDD VSS / RSC_IHPSG13_INVX2 +XI3<2> PADR<2> NADR<2> VDD VSS / RSC_IHPSG13_INVX2 +XI3<1> PADR<1> NADR<1> VDD VSS / RSC_IHPSG13_INVX2 +XI3<0> PADR<0> NADR<0> VDD VSS / RSC_IHPSG13_INVX2 +XI1<3> PADR<2> PADR<3> CS sel23<3> VDD VSS / RSC_IHPSG13_NAND3X2 +XI1<2> NADR<2> PADR<3> CS sel23<2> VDD VSS / RSC_IHPSG13_NAND3X2 +XI1<1> PADR<2> NADR<3> CS sel23<1> VDD VSS / RSC_IHPSG13_NAND3X2 +XI1<0> NADR<2> NADR<3> CS sel23<0> VDD VSS / RSC_IHPSG13_NAND3X2 +XI2<15> sel23<3> sel01<3> EN WL<15> VDD VSS / RSC_IHPSG13_NOR3X2 +XI2<14> sel23<3> sel01<2> EN WL<14> VDD VSS / RSC_IHPSG13_NOR3X2 +XI2<13> sel23<3> sel01<1> EN WL<13> VDD VSS / RSC_IHPSG13_NOR3X2 +XI2<12> sel23<3> sel01<0> EN WL<12> VDD VSS / RSC_IHPSG13_NOR3X2 +XI2<11> sel23<2> sel01<3> EN WL<11> VDD VSS / RSC_IHPSG13_NOR3X2 +XI2<10> sel23<2> sel01<2> EN WL<10> VDD VSS / RSC_IHPSG13_NOR3X2 +XI2<9> sel23<2> sel01<1> EN WL<9> VDD VSS / RSC_IHPSG13_NOR3X2 +XI2<8> sel23<2> sel01<0> EN WL<8> VDD VSS / RSC_IHPSG13_NOR3X2 +XI2<7> sel23<1> sel01<3> EN WL<7> VDD VSS / RSC_IHPSG13_NOR3X2 +XI2<6> sel23<1> sel01<2> EN WL<6> VDD VSS / RSC_IHPSG13_NOR3X2 +XI2<5> sel23<1> sel01<1> EN WL<5> VDD VSS / RSC_IHPSG13_NOR3X2 +XI2<4> sel23<1> sel01<0> EN WL<4> VDD VSS / RSC_IHPSG13_NOR3X2 +XI2<3> sel23<0> sel01<3> EN WL<3> VDD VSS / RSC_IHPSG13_NOR3X2 +XI2<2> sel23<0> sel01<2> EN WL<2> VDD VSS / RSC_IHPSG13_NOR3X2 +XI2<1> sel23<0> sel01<1> EN WL<1> VDD VSS / RSC_IHPSG13_NOR3X2 +XI2<0> sel23<0> sel01<0> EN WL<0> VDD VSS / RSC_IHPSG13_NOR3X2 +XCAPS4 VDD VSS / RSC_IHPSG13_FILLCAP4 +XI11 ECLK_L_BOT ECLK_L_TOP / RSC_IHPSG13_MET2RES +XR0 ECLK_H_BOT ECLK_H_TOP / RSC_IHPSG13_MET2RES +.ENDS +.SUBCKT RM_IHPSG13_1024x32_c2_1P_ROWDEC4 ADDR_N_I<3> ADDR_N_I<2> ADDR_N_I<1> ADDR_N_I<0> ++ CS_I ECLK_I WL_O<15> WL_O<14> WL_O<13> WL_O<12> WL_O<11> WL_O<10> WL_O<9> ++ WL_O<8> WL_O<7> WL_O<6> WL_O<5> WL_O<4> WL_O<3> WL_O<2> WL_O<1> WL_O<0> ++ VDD VSS +XL2<8> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<7> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<6> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<5> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<4> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<3> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<2> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<1> VDD VSS / RSC_IHPSG13_FILLCAP8 +XSEL ADDR_N_I<3> ADDR_N_I<2> ADDR_N_I<1> ADDR_N_I<0> CS_I ECLK_I ECLK_H<1> ++ ECLK_B<0> ECLK_B<1> WL_O<15> WL_O<14> WL_O<13> WL_O<12> WL_O<11> WL_O<10> ++ WL_O<9> WL_O<8> WL_O<7> WL_O<6> WL_O<5> WL_O<4> WL_O<3> WL_O<2> WL_O<1> ++ WL_O<0> VDD VSS / RM_IHPSG13_1024x32_c2_1P_DEC04 +.ENDS +.SUBCKT RSC_IHPSG13_CINVX8 A Z VDD VSS +MN0 Z A VSS VSS sg13_lv_nmos m=1 w=2.82u l=130.00n ng=4 nrd=0 nrs=0 +MP0 Z A VDD VDD sg13_lv_pmos m=1 w=6.48u l=130.00n ng=4 nrd=0 nrs=0 +.ENDS +.SUBCKT RSC_IHPSG13_DFNQMX2IX1 BE BI CN D QI QIN VDD VSS +MN15 net026 BI VSS VSS sg13_lv_nmos m=1 w=560.00n l=130.00n ng=1 nrd=0 ++ nrs=0 +MN14 MXI_OUT BE net026 VSS sg13_lv_nmos m=1 w=560.00n l=130.00n ng=1 nrd=0 ++ nrs=0 +MN1 net025 D VSS VSS sg13_lv_nmos m=1 w=560.00n l=130.00n ng=1 nrd=0 ++ nrs=0 +MN0 MXI_OUT BEN net025 VSS sg13_lv_nmos m=1 w=560.00n l=130.00n ng=1 nrd=0 ++ nrs=0 +MN10 QI CNN net21 VSS sg13_lv_nmos m=1 w=850.00n l=130.00n ng=1 nrd=0 nrs=0 +MN11 net21 QI_MS VSS VSS sg13_lv_nmos m=1 w=850.00n l=130.00n ng=1 ++ nrd=0 nrs=0 +MN7 net30 QI_MS VSS VSS sg13_lv_nmos m=1 w=480.00n l=130.00n ng=1 ++ nrd=0 nrs=0 +MN6 QIN_MS CNN net30 VSS sg13_lv_nmos m=1 w=480.00n l=130.00n ng=1 nrd=0 ++ nrs=0 +MN3 QI_MS QIN_MS VSS VSS sg13_lv_nmos m=1 w=480.00n l=130.00n ng=1 ++ nrd=0 nrs=0 +MN12 CNN CN VSS VSS sg13_lv_nmos m=1 w=495.000n l=130.00n ng=1 nrd=0 ++ nrs=0 +MN9 net37 MXI_OUT VSS VSS sg13_lv_nmos m=1 w=870.00n l=130.00n ng=1 ++ nrd=0 nrs=0 +MN8 QIN_MS CN net37 VSS sg13_lv_nmos m=1 w=870.00n l=130.00n ng=1 nrd=0 ++ nrs=0 +MN5 QI CN net25 VSS sg13_lv_nmos m=1 w=480.00n l=130.00n ng=1 nrd=0 nrs=0 +MN4 net25 QIN VSS VSS sg13_lv_nmos m=1 w=480.00n l=130.00n ng=1 nrd=0 ++ nrs=0 +MN2 QIN QI VSS VSS sg13_lv_nmos m=1 w=480.00n l=130.00n ng=1 nrd=0 ++ nrs=0 +MN13 BEN BE VSS VSS sg13_lv_nmos m=1 w=560.00n l=130.00n ng=1 nrd=0 ++ nrs=0 +MP15 MXI_OUT BEN net027 VDD sg13_lv_pmos m=1 w=985.000n l=130.00n ng=1 ++ nrd=0 nrs=0 +MP14 net027 BI VDD VDD sg13_lv_pmos m=1 w=985.000n l=130.00n ng=1 ++ nrd=0 nrs=0 +MP1 MXI_OUT BE net024 VDD sg13_lv_pmos m=1 w=985.000n l=130.00n ng=1 nrd=0 ++ nrs=0 +MP0 net024 D VDD VDD sg13_lv_pmos m=1 w=985.000n l=130.00n ng=1 nrd=0 ++ nrs=0 +MP13 BEN BE VDD VDD sg13_lv_pmos m=1 w=645.000n l=130.00n ng=1 nrd=0 ++ nrs=0 +MP6 QI_MS QIN_MS VDD VDD sg13_lv_pmos m=1 w=480.00n l=130.00n ng=1 ++ nrd=0 nrs=0 +MP3 QI CNN net27 VDD sg13_lv_pmos m=1 w=480.00n l=130.00n ng=1 nrd=0 nrs=0 +MP2 net27 QIN VDD VDD sg13_lv_pmos m=1 w=480.00n l=130.00n ng=1 nrd=0 ++ nrs=0 +MP10 net36 MXI_OUT VDD VDD sg13_lv_pmos m=1 w=975.000n l=130.00n ng=1 ++ nrd=0 nrs=0 +MP11 QIN_MS CNN net36 VDD sg13_lv_pmos m=1 w=975.000n l=130.00n ng=1 nrd=0 ++ nrs=0 +MP4 net32 QI_MS VDD VDD sg13_lv_pmos m=1 w=480.00n l=130.00n ng=1 ++ nrd=0 nrs=0 +MP5 QIN_MS CN net32 VDD sg13_lv_pmos m=1 w=480.00n l=130.00n ng=1 nrd=0 ++ nrs=0 +MP7 QIN QI VDD VDD sg13_lv_pmos m=1 w=480.00n l=130.00n ng=1 nrd=0 ++ nrs=0 +MP12 CNN CN VDD VDD sg13_lv_pmos m=1 w=480.00n l=130.00n ng=1 nrd=0 ++ nrs=0 +MP9 QI CN net19 VDD sg13_lv_pmos m=1 w=990.00n l=130.00n ng=1 nrd=0 nrs=0 +MP8 net19 QI_MS VDD VDD sg13_lv_pmos m=1 w=990.00n l=130.00n ng=1 ++ nrd=0 nrs=0 +.ENDS +.SUBCKT RM_IHPSG13_1024x32_c2_1P_ROWREG4 ACLK_N_I ADDR_I<3> ADDR_I<2> ADDR_I<1> ADDR_I<0> ++ ADDR_N_O<3> ADDR_N_O<2> ADDR_N_O<1> ADDR_N_O<0> BIST_ADDR_I<3> ++ BIST_ADDR_I<2> BIST_ADDR_I<1> BIST_ADDR_I<0> BIST_EN_I VDD VSS +XINV<3> q_int<3> qn_int<3> VDD VSS / RSC_IHPSG13_CINVX2 +XINV<2> q_int<2> qn_int<2> VDD VSS / RSC_IHPSG13_CINVX2 +XINV<1> q_int<1> qn_int<1> VDD VSS / RSC_IHPSG13_CINVX2 +XINV<0> q_int<0> qn_int<0> VDD VSS / RSC_IHPSG13_CINVX2 +XDRV<3> qn_int<3> ADDR_N_O<3> VDD VSS / RSC_IHPSG13_CINVX8 +XDRV<2> qn_int<2> ADDR_N_O<2> VDD VSS / RSC_IHPSG13_CINVX8 +XDRV<1> qn_int<1> ADDR_N_O<1> VDD VSS / RSC_IHPSG13_CINVX8 +XDRV<0> qn_int<0> ADDR_N_O<0> VDD VSS / RSC_IHPSG13_CINVX8 +XDFF<3> BIST_EN_I BIST_ADDR_I<3> ACLK_N_I ADDR_I<3> q_int<3> net2<0> VDD ++ VSS / RSC_IHPSG13_DFNQMX2IX1 +XDFF<2> BIST_EN_I BIST_ADDR_I<2> ACLK_N_I ADDR_I<2> q_int<2> net2<1> VDD ++ VSS / RSC_IHPSG13_DFNQMX2IX1 +XDFF<1> BIST_EN_I BIST_ADDR_I<1> ACLK_N_I ADDR_I<1> q_int<1> net2<2> VDD ++ VSS / RSC_IHPSG13_DFNQMX2IX1 +XDFF<0> BIST_EN_I BIST_ADDR_I<0> ACLK_N_I ADDR_I<0> q_int<0> net2<3> VDD ++ VSS / RSC_IHPSG13_DFNQMX2IX1 +XI11<20> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI11<19> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI11<18> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI11<17> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI11<16> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI11<15> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI11<14> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI11<13> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI11<12> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI11<11> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI11<10> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI11<9> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI11<8> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI11<7> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI11<6> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI11<5> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI11<4> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI11<3> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI11<2> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI11<1> VDD VSS / RSC_IHPSG13_FILLCAP8 +.ENDS +.SUBCKT RSC_IHPSG13_CDLYX1 A Z VDD VSS +MN1 net010 net032 VSS VSS sg13_lv_nmos m=1 w=300.0n l=160.00n ng=1 ++ nrd=0 nrs=0 +MN2 net032 A net014 VSS sg13_lv_nmos m=1 w=300.0n l=160.00n ng=1 nrd=0 ++ nrs=0 +MN0 Z net032 net010 VSS sg13_lv_nmos m=1 w=300.0n l=160.00n ng=1 nrd=0 ++ nrs=0 +MN3 net014 A VSS VSS sg13_lv_nmos m=1 w=300.0n l=160.00n ng=1 nrd=0 ++ nrs=0 +MP1 Z net032 net07 VDD sg13_lv_pmos m=1 w=720.00n l=160.00n ng=1 nrd=0 ++ nrs=0 +MP3 net011 A VDD VDD sg13_lv_pmos m=1 w=720.00n l=160.00n ng=1 nrd=0 ++ nrs=0 +MP0 net07 net032 VDD VDD sg13_lv_pmos m=1 w=720.00n l=160.00n ng=1 ++ nrd=0 nrs=0 +MP2 net032 A net011 VDD sg13_lv_pmos m=1 w=720.00n l=160.00n ng=1 nrd=0 ++ nrs=0 +.ENDS +.SUBCKT RSC_IHPSG13_CDLYX1_DUMMY A Z VDD VSS +MN0 vss_r vdd_r VSS VSS sg13_lv_nmos m=1 w=2.49u l=300.0n ng=3 nrd=0 ++ nrs=0 +MP0 vdd_r vss_r VDD VDD sg13_lv_pmos m=1 w=3.24u l=640.00n ng=2 nrd=0 ++ nrs=0 +R0 Z A lvsres w=2.6e-07 l=6e-07 +.ENDS + +.SUBCKT RSC_IHPSG13_MX2IX1 A0 A1 S ZN VDD VSS +MP4 SN S VDD VDD sg13_lv_pmos m=1 w=645.000n l=130.00n ng=1 nrd=0 nrs=0 +MP3 ZN SN net12 VDD sg13_lv_pmos m=1 w=985.000n l=130.00n ng=1 nrd=0 nrs=0 +MP2 net12 A1 VDD VDD sg13_lv_pmos m=1 w=985.000n l=130.00n ng=1 nrd=0 ++ nrs=0 +MP1 ZN S net17 VDD sg13_lv_pmos m=1 w=985.000n l=130.00n ng=1 nrd=0 nrs=0 +MP0 net17 A0 VDD VDD sg13_lv_pmos m=1 w=985.000n l=130.00n ng=1 nrd=0 ++ nrs=0 +MN5 SN S VSS VSS sg13_lv_nmos m=1 w=480.00n l=130.00n ng=1 nrd=0 nrs=0 +MN3 net13 A1 VSS VSS sg13_lv_nmos m=1 w=480.00n l=130.00n ng=1 nrd=0 ++ nrs=0 +MN2 ZN S net13 VSS sg13_lv_nmos m=1 w=480.00n l=130.00n ng=1 nrd=0 nrs=0 +MN1 net15 A0 VSS VSS sg13_lv_nmos m=1 w=480.00n l=130.00n ng=1 nrd=0 ++ nrs=0 +MN0 ZN SN net15 VSS sg13_lv_nmos m=1 w=480.00n l=130.00n ng=1 nrd=0 nrs=0 +.ENDS +.SUBCKT RM_IHPSG13_1024x32_c2_1P_DLY_MUX A SEL Z VDD VSS +XI11 net4 Z VDD VSS / RSC_IHPSG13_CINVX2 +XI8 A D<3> SEL net4 VDD VSS / RSC_IHPSG13_MX2IX1 +XI20<3> D<2> D<3> VDD VSS / RSC_IHPSG13_CDLYX1 +XI20<2> D<1> D<2> VDD VSS / RSC_IHPSG13_CDLYX1 +XI20<1> A D<1> VDD VSS / RSC_IHPSG13_CDLYX1 +.ENDS +.SUBCKT RSC_IHPSG13_DFNQX2 CN D Q VDD VSS +MN0 Q QIN_SL VSS VSS sg13_lv_nmos m=1 w=980.00n l=130.00n ng=1 nrd=0 ++ nrs=0 +MN10 QIN_SL CNN net21 VSS sg13_lv_nmos m=1 w=850.00n l=130.00n ng=1 nrd=0 ++ nrs=0 +MN11 net21 QI_MS VSS VSS sg13_lv_nmos m=1 w=850.00n l=130.00n ng=1 ++ nrd=0 nrs=0 +MN7 net30 QI_MS VSS VSS sg13_lv_nmos m=1 w=480.00n l=130.00n ng=1 ++ nrd=0 nrs=0 +MN6 QIN_MS CNN net30 VSS sg13_lv_nmos m=1 w=480.00n l=130.00n ng=1 nrd=0 ++ nrs=0 +MN3 QI_MS QIN_MS VSS VSS sg13_lv_nmos m=1 w=480.00n l=130.00n ng=1 ++ nrd=0 nrs=0 +MN12 CNN CN VSS VSS sg13_lv_nmos m=1 w=495.000n l=130.00n ng=1 nrd=0 ++ nrs=0 +MN9 net37 D VSS VSS sg13_lv_nmos m=1 w=870.00n l=130.00n ng=1 nrd=0 ++ nrs=0 +MN8 QIN_MS CN net37 VSS sg13_lv_nmos m=1 w=870.00n l=130.00n ng=1 nrd=0 ++ nrs=0 +MN5 QIN_SL CN net25 VSS sg13_lv_nmos m=1 w=480.00n l=130.00n ng=1 nrd=0 ++ nrs=0 +MN4 net25 QI_SL VSS VSS sg13_lv_nmos m=1 w=480.00n l=130.00n ng=1 ++ nrd=0 nrs=0 +MN2 QI_SL QIN_SL VSS VSS sg13_lv_nmos m=1 w=480.00n l=130.00n ng=1 ++ nrd=0 nrs=0 +MP0 Q QIN_SL VDD VDD sg13_lv_pmos m=1 w=1.62u l=130.00n ng=1 nrd=0 ++ nrs=0 +MP6 QI_MS QIN_MS VDD VDD sg13_lv_pmos m=1 w=480.00n l=130.00n ng=1 ++ nrd=0 nrs=0 +MP3 QIN_SL CNN net27 VDD sg13_lv_pmos m=1 w=480.00n l=130.00n ng=1 nrd=0 ++ nrs=0 +MP2 net27 QI_SL VDD VDD sg13_lv_pmos m=1 w=480.00n l=130.00n ng=1 ++ nrd=0 nrs=0 +MP10 net36 D VDD VDD sg13_lv_pmos m=1 w=975.000n l=130.00n ng=1 nrd=0 ++ nrs=0 +MP11 QIN_MS CNN net36 VDD sg13_lv_pmos m=1 w=975.000n l=130.00n ng=1 nrd=0 ++ nrs=0 +MP4 net32 QI_MS VDD VDD sg13_lv_pmos m=1 w=480.00n l=130.00n ng=1 ++ nrd=0 nrs=0 +MP5 QIN_MS CN net32 VDD sg13_lv_pmos m=1 w=480.00n l=130.00n ng=1 nrd=0 ++ nrs=0 +MP7 QI_SL QIN_SL VDD VDD sg13_lv_pmos m=1 w=480.00n l=130.00n ng=1 ++ nrd=0 nrs=0 +MP12 CNN CN VDD VDD sg13_lv_pmos m=1 w=480.00n l=130.00n ng=1 nrd=0 ++ nrs=0 +MP9 QIN_SL CN net19 VDD sg13_lv_pmos m=1 w=990.00n l=130.00n ng=1 nrd=0 ++ nrs=0 +MP8 net19 QI_MS VDD VDD sg13_lv_pmos m=1 w=990.00n l=130.00n ng=1 ++ nrd=0 nrs=0 +.ENDS +.SUBCKT RSC_IHPSG13_CNAND2X2 A B Z VDD VSS +MN0 Z B net6 VSS sg13_lv_nmos m=1 w=980.00n l=130.00n ng=1 nrd=0 nrs=0 +MN1 net6 A VSS VSS sg13_lv_nmos m=1 w=980.00n l=130.00n ng=1 nrd=0 ++ nrs=0 +MP1 Z B VDD VDD sg13_lv_pmos m=1 w=1.62u l=130.00n ng=1 nrd=0 nrs=0 +MP0 Z A VDD VDD sg13_lv_pmos m=1 w=1.62u l=130.00n ng=1 nrd=0 nrs=0 +.ENDS +.SUBCKT RSC_IHPSG13_CGATEPX4 CP E Q VDD VSS +MN1 net08 QIN VSS VSS sg13_lv_nmos m=1 w=480.00n l=130.00n ng=1 nrd=0 ++ nrs=0 +MN2 net019 net08 VSS VSS sg13_lv_nmos m=1 w=480.00n l=130.00n ng=1 ++ nrd=0 nrs=0 +MN3 QIN CP net019 VSS sg13_lv_nmos m=1 w=480.00n l=130.00n ng=1 nrd=0 nrs=0 +MN6 Q net015 VSS VSS sg13_lv_nmos m=1 w=1.41u l=130.00n ng=2 nrd=0 ++ nrs=0 +MN5 net015 net08 net018 VSS sg13_lv_nmos m=1 w=980.00n l=130.00n ng=1 ++ nrd=0 nrs=0 +MN8 QIN CPN net023 VSS sg13_lv_nmos m=1 w=870.00n l=130.00n ng=1 nrd=0 ++ nrs=0 +MN7 net023 E VSS VSS sg13_lv_nmos m=1 w=870.00n l=130.00n ng=1 nrd=0 ++ nrs=0 +MN4 net018 CP VSS VSS sg13_lv_nmos m=1 w=980.00n l=130.00n ng=1 nrd=0 ++ nrs=0 +MN0 CPN CP VSS VSS sg13_lv_nmos m=1 w=500.0n l=130.00n ng=1 nrd=0 nrs=0 +MP3 net08 QIN VDD VDD sg13_lv_pmos m=1 w=480.00n l=130.00n ng=1 nrd=0 ++ nrs=0 +MP2 QIN CPN net017 VDD sg13_lv_pmos m=1 w=480.00n l=130.00n ng=1 nrd=0 ++ nrs=0 +MP1 net017 net08 VDD VDD sg13_lv_pmos m=1 w=480.00n l=130.00n ng=1 ++ nrd=0 nrs=0 +MP0 CPN CP VDD VDD sg13_lv_pmos m=1 w=500.0n l=130.00n ng=1 nrd=0 nrs=0 +MP8 QIN CP net024 VDD sg13_lv_pmos m=1 w=975.000n l=130.00n ng=1 nrd=0 ++ nrs=0 +MP7 net024 E VDD VDD sg13_lv_pmos m=1 w=975.000n l=130.00n ng=1 nrd=0 ++ nrs=0 +MP4 net015 CP VDD VDD sg13_lv_pmos m=1 w=1.27u l=130.00n ng=1 nrd=0 ++ nrs=0 +MP6 Q net015 VDD VDD sg13_lv_pmos m=1 w=3.24u l=130.00n ng=2 nrd=0 ++ nrs=0 +MP5 net015 net08 VDD VDD sg13_lv_pmos m=1 w=1.27u l=130.00n ng=1 nrd=0 ++ nrs=0 +.ENDS +.SUBCKT RSC_IHPSG13_CBUFX8 A Z VDD VSS +MP0 net4 A VDD VDD sg13_lv_pmos m=1 w=3.24u l=130.00n ng=2 nrd=0 nrs=0 +MP1 Z net4 VDD VDD sg13_lv_pmos m=1 w=6.48u l=130.00n ng=4 nrd=0 nrs=0 +MN1 Z net4 VSS VSS sg13_lv_nmos m=1 w=2.82u l=130.00n ng=4 nrd=0 nrs=0 +MN0 net4 A VSS VSS sg13_lv_nmos m=1 w=1.41u l=130.00n ng=2 nrd=0 nrs=0 +.ENDS +.SUBCKT RSC_IHPSG13_CDLYX2 A Z VDD VSS +MN2 net4 A net9 VSS sg13_lv_nmos m=1 w=320.00n l=200.0n ng=1 nrd=0 nrs=0 +MN0 Z net4 VSS VSS sg13_lv_nmos m=1 w=705.000n l=130.00n ng=1 nrd=0 ++ nrs=0 +MN1 net9 A VSS VSS sg13_lv_nmos m=1 w=320.00n l=200.0n ng=1 nrd=0 nrs=0 +MP2 net4 A net10 VDD sg13_lv_pmos m=1 w=1.2u l=200.0n ng=1 nrd=0 nrs=0 +MP1 net10 A VDD VDD sg13_lv_pmos m=1 w=1.2u l=200.0n ng=1 nrd=0 nrs=0 +MP0 Z net4 VDD VDD sg13_lv_pmos m=1 w=1.62u l=130.00n ng=1 nrd=0 nrs=0 +.ENDS +.SUBCKT RSC_IHPSG13_MX2X2 A0 A1 S Z VDD VSS +MP6 Z net010 VDD VDD sg13_lv_pmos m=1 w=1.62u l=130.00n ng=1 nrd=0 ++ nrs=0 +MP4 SN S VDD VDD sg13_lv_pmos m=1 w=645.000n l=130.00n ng=1 nrd=0 nrs=0 +MP3 net010 SN net12 VDD sg13_lv_pmos m=1 w=985.000n l=130.00n ng=1 nrd=0 ++ nrs=0 +MP2 net12 A1 VDD VDD sg13_lv_pmos m=1 w=985.000n l=130.00n ng=1 nrd=0 ++ nrs=0 +MP1 net010 S net17 VDD sg13_lv_pmos m=1 w=985.000n l=130.00n ng=1 nrd=0 ++ nrs=0 +MP0 net17 A0 VDD VDD sg13_lv_pmos m=1 w=985.000n l=130.00n ng=1 nrd=0 ++ nrs=0 +MN6 Z net010 VSS VSS sg13_lv_nmos m=1 w=705.000n l=130.00n ng=1 nrd=0 ++ nrs=0 +MN5 SN S VSS VSS sg13_lv_nmos m=1 w=560.00n l=130.00n ng=1 nrd=0 nrs=0 +MN3 net13 A1 VSS VSS sg13_lv_nmos m=1 w=560.00n l=130.00n ng=1 nrd=0 ++ nrs=0 +MN2 net010 S net13 VSS sg13_lv_nmos m=1 w=560.00n l=130.00n ng=1 nrd=0 ++ nrs=0 +MN1 net15 A0 VSS VSS sg13_lv_nmos m=1 w=560.00n l=130.00n ng=1 nrd=0 ++ nrs=0 +MN0 net010 SN net15 VSS sg13_lv_nmos m=1 w=560.00n l=130.00n ng=1 nrd=0 ++ nrs=0 +.ENDS +.SUBCKT RSC_IHPSG13_AND2X2 A B Z VDD VSS +MN3 Z net6 VSS VSS sg13_lv_nmos m=1 w=980.00n l=130.00n ng=1 nrd=0 ++ nrs=0 +MN4 net9 B VSS VSS sg13_lv_nmos m=1 w=500.0n l=130.00n ng=1 nrd=0 nrs=0 +MN6 net6 A net9 VSS sg13_lv_nmos m=1 w=500.0n l=130.00n ng=1 nrd=0 nrs=0 +MP2 Z net6 VDD VDD sg13_lv_pmos m=1 w=1.62u l=130.00n ng=1 nrd=0 nrs=0 +MP0 net6 B VDD VDD sg13_lv_pmos m=1 w=860.00n l=130.00n ng=1 nrd=0 ++ nrs=0 +MP1 net6 A VDD VDD sg13_lv_pmos m=1 w=860.00n l=130.00n ng=1 nrd=0 ++ nrs=0 +.ENDS +.SUBCKT RSC_IHPSG13_TIEL Z VDD VSS +MN0 Z net2 VSS VSS sg13_lv_nmos m=1 w=480.00n l=130.00n ng=1 nrd=0 ++ nrs=0 +MP0 net2 net2 VDD VDD sg13_lv_pmos m=1 w=480.00n l=130.00n ng=1 nrd=0 ++ nrs=0 +.ENDS +.SUBCKT RSC_IHPSG13_XOR2X2 A B Z VDD VSS +MP8 net012 B net7 VDD sg13_lv_pmos m=1 w=825.000n l=130.00n ng=1 nrd=0 ++ nrs=0 +MP7 net011 net3 net012 VDD sg13_lv_pmos m=1 w=825.000n l=130.00n ng=1 ++ nrd=0 nrs=0 +MP6 Z net012 VDD VDD sg13_lv_pmos m=1 w=1.535u l=130.00n ng=1 nrd=0 ++ nrs=0 +MP2 net7 A VDD VDD sg13_lv_pmos m=1 w=825.000n l=130.00n ng=1 nrd=0 ++ nrs=0 +MP4 net011 net7 VDD VDD sg13_lv_pmos m=1 w=825.000n l=130.00n ng=1 ++ nrd=0 nrs=0 +MP5 net3 B VDD VDD sg13_lv_pmos m=1 w=580.00n l=130.00n ng=1 nrd=0 ++ nrs=0 +MN7 net012 B net011 VSS sg13_lv_nmos m=1 w=555.000n l=130.00n ng=1 nrd=0 ++ nrs=0 +MN6 net7 net3 net012 VSS sg13_lv_nmos m=1 w=555.000n l=130.00n ng=1 nrd=0 ++ nrs=0 +MN5 Z net012 VSS VSS sg13_lv_nmos m=1 w=775.000n l=130.00n ng=1 nrd=0 ++ nrs=0 +MN2 net7 A VSS VSS sg13_lv_nmos m=1 w=555.000n l=130.00n ng=1 nrd=0 ++ nrs=0 +MN4 net3 B VSS VSS sg13_lv_nmos m=1 w=480.00n l=130.00n ng=1 nrd=0 ++ nrs=0 +MN3 net011 net7 VSS VSS sg13_lv_nmos m=1 w=555.000n l=130.00n ng=1 ++ nrd=0 nrs=0 +.ENDS +.SUBCKT RSC_IHPSG13_OA12X1 A B C Z VDD VSS +MN2 net7 C VSS VSS sg13_lv_nmos m=1 w=980.00n l=130.00n ng=1 nrd=0 ++ nrs=0 +MN3 Z net17 VSS VSS sg13_lv_nmos m=1 w=500.0n l=130.00n ng=1 nrd=0 ++ nrs=0 +MN1 net17 B net7 VSS sg13_lv_nmos m=1 w=980.00n l=130.00n ng=1 nrd=0 nrs=0 +MN0 net17 A net7 VSS sg13_lv_nmos m=1 w=980.00n l=130.00n ng=1 nrd=0 nrs=0 +MP0 net24 A VDD VDD sg13_lv_pmos m=1 w=1.62u l=130.00n ng=1 nrd=0 nrs=0 +MP3 Z net17 VDD VDD sg13_lv_pmos m=1 w=905.000n l=130.00n ng=1 nrd=0 ++ nrs=0 +MP1 net17 B net24 VDD sg13_lv_pmos m=1 w=1.62u l=130.00n ng=1 nrd=0 nrs=0 +MP2 net17 C VDD VDD sg13_lv_pmos m=1 w=905.000n l=130.00n ng=1 nrd=0 ++ nrs=0 +.ENDS +.SUBCKT RM_IHPSG13_1024x32_c2_1P_CTRL ACLK_N BIST_CK_I BIST_CS_I BIST_EN BIST_RE_I ++ BIST_WE_I B_TIEL_O CK_I CS_I DCLK ECLK PULSE_H PULSE_L PULSE_O RCLK RE_I ++ ROW_CS WCLK WE_I VDD VSS +XI17 ck_regs we col_we VDD VSS / RSC_IHPSG13_DFNQX2 +XI16 ck_regs re col_re VDD VSS / RSC_IHPSG13_DFNQX2 +XI18 ck_regs cs net7 VDD VSS / RSC_IHPSG13_DFNQX2 +XI71 ACLK_N net012 PULSE_O VDD VSS / RSC_IHPSG13_DFNQX2 +XI77 col_we net9 net016 VDD VSS / RSC_IHPSG13_CNAND2X2 +XI76 col_re net9 net018 VDD VSS / RSC_IHPSG13_CNAND2X2 +XI15 ck_dly WEorREandCS aclk VDD VSS / RSC_IHPSG13_CGATEPX4 +XI14 ck WEandCS DCLK VDD VSS / RSC_IHPSG13_CGATEPX4 +XI60 net7 ROW_CS VDD VSS / RSC_IHPSG13_CBUFX8 +XI73 PULSE_O net012 VDD VSS / RSC_IHPSG13_CINVX2 +XI8 net9 net8 VDD VSS / RSC_IHPSG13_CINVX2 +XI64 ck ck_dly VDD VSS / RSC_IHPSG13_CDLYX2 +XI86 CS_I BIST_CS_I BIST_EN cs VDD VSS / RSC_IHPSG13_MX2X2 +XI87 CK_I BIST_CK_I BIST_EN ck VDD VSS / RSC_IHPSG13_MX2X2 +XI85 WE_I BIST_WE_I BIST_EN we VDD VSS / RSC_IHPSG13_MX2X2 +XI84 RE_I BIST_RE_I BIST_EN re VDD VSS / RSC_IHPSG13_MX2X2 +XI22 we cs WEandCS VDD VSS / RSC_IHPSG13_AND2X2 +XBM_TIEL B_TIEL_O VDD VSS / RSC_IHPSG13_TIEL +XI48 ck_dly ck_regs VDD VSS / RSC_IHPSG13_CINVX4 +XI81 net016 WCLK VDD VSS / RSC_IHPSG13_CINVX4 +XI80 net018 RCLK VDD VSS / RSC_IHPSG13_CINVX4 +XI78 net8 net020 VDD VSS / RSC_IHPSG13_CINVX4 +XI6 PULSE_L PULSE_H net9 VDD VSS / RSC_IHPSG13_XOR2X2 +XI79 net020 ECLK VDD VSS / RSC_IHPSG13_CINVX8 +XI63 aclk ACLK_N VDD VSS / RSC_IHPSG13_CINVX8 +XI21 re we cs WEorREandCS VDD VSS / RSC_IHPSG13_OA12X1 +.ENDS +.SUBCKT RM_IHPSG13_1024x32_c2_1P_COLDEC2 ACLK_N ADDR<1> ADDR<0> ADDR_COL<1> ADDR_COL<0> ++ ADDR_DEC<7> ADDR_DEC<6> ADDR_DEC<5> ADDR_DEC<4> ADDR_DEC<3> ADDR_DEC<2> ++ ADDR_DEC<1> ADDR_DEC<0> BIST_ADDR<1> BIST_ADDR<0> BIST_EN_I VDD VSS +XI14<5> VDD VSS / RSC_IHPSG13_FILLCAP4 +XI14<4> VDD VSS / RSC_IHPSG13_FILLCAP4 +XI14<3> VDD VSS / RSC_IHPSG13_FILLCAP4 +XI14<2> VDD VSS / RSC_IHPSG13_FILLCAP4 +XI14<1> VDD VSS / RSC_IHPSG13_FILLCAP4 +XDFF<1> BIST_EN_I BIST_ADDR<1> ACLK_N ADDR<1> padr_int<1> net6<0> VDD ++ VSS / RSC_IHPSG13_DFNQMX2IX1 +XDFF<0> BIST_EN_I BIST_ADDR<0> ACLK_N ADDR<0> padr_int<0> net6<1> VDD ++ VSS / RSC_IHPSG13_DFNQMX2IX1 +XI1<3> PADR<1> PADR<0> addr_n<3> VDD VSS / RSC_IHPSG13_NAND2X2 +XI1<2> PADR<1> NADR<0> addr_n<2> VDD VSS / RSC_IHPSG13_NAND2X2 +XI1<1> NADR<1> PADR<0> addr_n<1> VDD VSS / RSC_IHPSG13_NAND2X2 +XI1<0> NADR<1> NADR<0> addr_n<0> VDD VSS / RSC_IHPSG13_NAND2X2 +XI16<37> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI16<36> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI16<35> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI16<34> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI16<33> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI16<32> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI16<31> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI16<30> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI16<29> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI16<28> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI16<27> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI16<26> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI16<25> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI16<24> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI16<23> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI16<22> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI16<21> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI16<20> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI16<19> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI16<18> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI16<17> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI16<16> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI16<15> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI16<14> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI16<13> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI16<12> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI16<11> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI16<10> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI16<9> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI16<8> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI16<7> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI16<6> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI16<5> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI16<4> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI16<3> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI16<2> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI16<1> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI3<1> padr_int<1> NADR<1> VDD VSS / RSC_IHPSG13_INVX2 +XI3<0> padr_int<0> NADR<0> VDD VSS / RSC_IHPSG13_INVX2 +XI13<1> NADR<1> PADR<1> VDD VSS / RSC_IHPSG13_INVX2 +XI13<0> NADR<0> PADR<0> VDD VSS / RSC_IHPSG13_INVX2 +XI2<3> addr_n<3> ADDR_DEC<3> VDD VSS / RSC_IHPSG13_INVX2 +XI2<2> addr_n<2> ADDR_DEC<2> VDD VSS / RSC_IHPSG13_INVX2 +XI2<1> addr_n<1> ADDR_DEC<1> VDD VSS / RSC_IHPSG13_INVX2 +XI2<0> addr_n<0> ADDR_DEC<0> VDD VSS / RSC_IHPSG13_INVX2 +XI15<1> ADDR_COL<1> VDD VSS / RSC_IHPSG13_TIEL +XI15<0> ADDR_COL<0> VDD VSS / RSC_IHPSG13_TIEL +XI17<3> ADDR_DEC<7> VDD VSS / RSC_IHPSG13_TIEL +XI17<2> ADDR_DEC<6> VDD VSS / RSC_IHPSG13_TIEL +XI17<1> ADDR_DEC<5> VDD VSS / RSC_IHPSG13_TIEL +XI17<0> ADDR_DEC<4> VDD VSS / RSC_IHPSG13_TIEL +.ENDS +.SUBCKT RSC_IHPSG13_NOR2X2 A B Z VDD VSS +MP1 Z B net9 VDD sg13_lv_pmos m=1 w=1.62u l=130.00n ng=1 nrd=0 nrs=0 +MP0 net9 A VDD VDD sg13_lv_pmos m=1 w=1.62u l=130.00n ng=1 nrd=0 nrs=0 +MN0 Z B VSS VSS sg13_lv_nmos m=1 w=980.00n l=130.00n ng=1 nrd=0 nrs=0 +MN1 Z A VSS VSS sg13_lv_nmos m=1 w=980.00n l=130.00n ng=1 nrd=0 nrs=0 +.ENDS +.SUBCKT RSC_IHPSG13_CINVX4_WN A Z VDD VSS +MN0 Z A VSS VSS sg13_lv_nmos m=1 w=705.000n l=130.00n ng=1 nrd=0 nrs=0 +MP0 Z A VDD VDD sg13_lv_pmos m=1 w=3.24u l=130.00n ng=2 nrd=0 nrs=0 +.ENDS +.SUBCKT RM_IHPSG13_1024x32_c2_1P_BLDRV BLC BLC_SEL BLT BLT_SEL PRE_N SEL_P WR_ONE WR_ZERO ++ VDD VSS +XCDEC SEL_P WR_ZERO BLC_PMOS_DRIVE VDD VSS / RSC_IHPSG13_NAND2X2 +XTDEC SEL_P WR_ONE BLT_PMOS_DRIVE VDD VSS / RSC_IHPSG13_NAND2X2 +MTWN BLT BLT_NMOS_DRIVE VSS VSS sg13_lv_nmos m=1 w=4.82u l=130.00n ++ ng=2 nrd=0 nrs=0 +MCWN BLC BLC_NMOS_DRIVE VSS VSS sg13_lv_nmos m=1 w=4.82u l=130.00n ++ ng=2 nrd=0 nrs=0 +MCWP BLC BLC_PMOS_DRIVE VDD VDD sg13_lv_pmos m=1 w=1.5u l=130.00n ng=1 ++ nrd=0 nrs=0 +MTWP BLT BLT_PMOS_DRIVE VDD VDD sg13_lv_pmos m=1 w=1.5u l=130.00n ng=1 ++ nrd=0 nrs=0 +MTSP BLT_SEL SEL_N BLT VDD sg13_lv_pmos m=1 w=1.5u l=130.00n ng=1 nrd=0 ++ nrs=0 +MTPR BLT PRE_N VDD VDD sg13_lv_pmos m=1 w=3.000u l=130.00n ng=2 nrd=0 ++ nrs=0 +MCSP BLC_SEL SEL_N BLC VDD sg13_lv_pmos m=1 w=1.5u l=130.00n ng=1 nrd=0 ++ nrs=0 +MCPR BLC PRE_N VDD VDD sg13_lv_pmos m=1 w=3.000u l=130.00n ng=2 nrd=0 ++ nrs=0 +XI86 SEL_P SEL_N VDD VSS / RSC_IHPSG13_INVX2 +XTINV BLC_PMOS_DRIVE BLT_NMOS_DRIVE VDD VSS / RSC_IHPSG13_INVX2 +XCINV BLT_PMOS_DRIVE BLC_NMOS_DRIVE VDD VSS / RSC_IHPSG13_INVX2 +.ENDS +.SUBCKT RSC_IHPSG13_TIEH Z VDD VSS +MN0 net2 net2 VSS VSS sg13_lv_nmos m=1 w=480.00n l=130.00n ng=1 nrd=0 ++ nrs=0 +MP0 Z net2 VDD VDD sg13_lv_pmos m=1 w=480.00n l=130.00n ng=1 nrd=0 ++ nrs=0 +.ENDS +.SUBCKT RSC_IHPSG13_MET3RES A B +R0 B A lvsres w=2.6e-07 l=6e-07 +.ENDS +.SUBCKT RSC_IHPSG13_DFPQD_MSAFFX2 CP DN DP QN QP VDD VSS +MN12 SN RN DIFFP VSS sg13_lv_nmos m=1 w=2.4u l=200.0n ng=2 nrd=0 nrs=0 +MN13 TAIL CP VSS VSS sg13_lv_nmos m=1 w=2.4u l=130.00n ng=2 nrd=0 nrs=0 +MN9 DIFFP DP TAIL VSS sg13_lv_nmos m=1 w=2.4u l=200.0n ng=2 nrd=0 nrs=0 +MN10 DIFFN DN TAIL VSS sg13_lv_nmos m=1 w=2.4u l=200.0n ng=2 nrd=0 nrs=0 +MN11 RN SN DIFFN VSS sg13_lv_nmos m=1 w=2.4u l=200.0n ng=2 nrd=0 nrs=0 +MN19 net33 SN VSS VSS sg13_lv_nmos m=1 w=980.00n l=130.00n ng=1 nrd=0 ++ nrs=0 +MN20 QN QP net37 VSS sg13_lv_nmos m=1 w=980.00n l=130.00n ng=1 nrd=0 nrs=0 +MN18 net37 RN VSS VSS sg13_lv_nmos m=1 w=980.00n l=130.00n ng=1 nrd=0 ++ nrs=0 +MN17 QP QN net33 VSS sg13_lv_nmos m=1 w=980.00n l=130.00n ng=1 nrd=0 nrs=0 +MP15 SN RN VDD VDD sg13_lv_pmos m=1 w=800.0n l=130.00n ng=1 nrd=0 nrs=0 +MP16 RN CP VDD VDD sg13_lv_pmos m=1 w=800.0n l=130.00n ng=1 nrd=0 nrs=0 +MP14 DIFFP CP VDD VDD sg13_lv_pmos m=1 w=800.0n l=130.00n ng=1 nrd=0 ++ nrs=0 +MP12 RN SN VDD VDD sg13_lv_pmos m=1 w=800.0n l=130.00n ng=1 nrd=0 nrs=0 +MP13 DIFFN CP VDD VDD sg13_lv_pmos m=1 w=800.0n l=130.00n ng=1 nrd=0 ++ nrs=0 +MP11 SN CP VDD VDD sg13_lv_pmos m=1 w=800.0n l=130.00n ng=1 nrd=0 nrs=0 +MP19 QN QP VDD VDD sg13_lv_pmos m=1 w=900.0n l=130.00n ng=1 nrd=0 nrs=0 +MP20 QP SN VDD VDD sg13_lv_pmos m=1 w=1.8u l=130.00n ng=2 nrd=0 nrs=0 +MP18 QN RN VDD VDD sg13_lv_pmos m=1 w=1.8u l=130.00n ng=2 nrd=0 nrs=0 +MP17 QP QN VDD VDD sg13_lv_pmos m=1 w=900.0n l=130.00n ng=1 nrd=0 nrs=0 +.ENDS +.SUBCKT RSC_IHPSG13_CBUFX2 A Z VDD VSS +MN1 Z net4 VSS VSS sg13_lv_nmos m=1 w=705.000n l=130.00n ng=1 nrd=0 ++ nrs=0 +MN0 net4 A VSS VSS sg13_lv_nmos m=1 w=540.00n l=130.00n ng=1 nrd=0 ++ nrs=0 +MP1 Z net4 VDD VDD sg13_lv_pmos m=1 w=1.62u l=130.00n ng=1 nrd=0 nrs=0 +MP0 net4 A VDD VDD sg13_lv_pmos m=1 w=1.1u l=130.00n ng=1 nrd=0 nrs=0 +.ENDS +.SUBCKT RSC_IHPSG13_INVX4 A Z VDD VSS +MN0 Z A VSS VSS sg13_lv_nmos m=1 w=1.96u l=130.00n ng=2 nrd=0 nrs=0 +MP0 Z A VDD VDD sg13_lv_pmos m=1 w=3.24u l=130.00n ng=2 nrd=0 nrs=0 +.ENDS +.SUBCKT RM_IHPSG13_1024x32_c2_1P_COLCTRL2 A_ADDR_DEC<3> A_ADDR_DEC<2> A_ADDR_DEC<1> ++ A_ADDR_DEC<0> A_BIST_BM_I A_BIST_DW_I A_BIST_EN_I A_BLC<3> A_BLC<2> A_BLC<1> ++ A_BLC<0> A_BLT<3> A_BLT<2> A_BLT<1> A_BLT<0> A_BM_I A_DCLK_B_L A_DCLK_B_R ++ A_DCLK_L A_DCLK_R A_DR_O A_DW_I A_RCLK_B_L A_RCLK_B_R A_RCLK_L A_RCLK_R ++ A_TIEH_O A_WCLK_B_L A_WCLK_B_R A_WCLK_L A_WCLK_R VDD VSS +XA_DREG A_BIST_EN_I A_BIST_DW_I A_DCLK_B_L A_DW_I A_DI_R net22 VDD VSS ++ / RSC_IHPSG13_DFNQMX2IX1 +XA_BREG A_BIST_EN_I A_BIST_BM_I A_DCLK_B_L A_BM_I A_BM_R net23 VDD VSS ++ / RSC_IHPSG13_DFNQMX2IX1 +XA_CAPS<5> VDD VSS / RSC_IHPSG13_FILLCAP4 +XA_CAPS<4> VDD VSS / RSC_IHPSG13_FILLCAP4 +XA_CAPS<3> VDD VSS / RSC_IHPSG13_FILLCAP4 +XA_CAPS<2> VDD VSS / RSC_IHPSG13_FILLCAP4 +XA_CAPS<1> VDD VSS / RSC_IHPSG13_FILLCAP4 +XA_I80 A_WCLK_B_R A_RCLK_B_R net21 VDD VSS / RSC_IHPSG13_AND2X2 +XA_I75 A_DI_R A_DO_WRITE_P A_WR_ONE VDD VSS / RSC_IHPSG13_AND2X2 +XA_I76 A_DI_N A_DO_WRITE_P A_WR_ZERO VDD VSS / RSC_IHPSG13_AND2X2 +XA_I44 A_WCLK_B_R A_BM_N A_DO_WRITE_P VDD VSS / RSC_IHPSG13_NOR2X2 +XA_I81 net21 A_PRE_N VDD VSS / RSC_IHPSG13_CINVX4_WN +XA_BLTMUX<3> A_BLC<3> A_BLC_SEL A_BLT<3> A_BLT_SEL A_PRE_N A_ADDR_DEC<3> ++ A_WR_ONE A_WR_ZERO VDD VSS / RM_IHPSG13_1024x32_c2_1P_BLDRV +XA_BLTMUX<2> A_BLC<2> A_BLC_SEL A_BLT<2> A_BLT_SEL A_PRE_N A_ADDR_DEC<2> ++ A_WR_ONE A_WR_ZERO VDD VSS / RM_IHPSG13_1024x32_c2_1P_BLDRV +XA_BLTMUX<1> A_BLC<1> A_BLC_SEL A_BLT<1> A_BLT_SEL A_PRE_N A_ADDR_DEC<1> ++ A_WR_ONE A_WR_ZERO VDD VSS / RM_IHPSG13_1024x32_c2_1P_BLDRV +XA_BLTMUX<0> A_BLC<0> A_BLC_SEL A_BLT<0> A_BLT_SEL A_PRE_N A_ADDR_DEC<0> ++ A_WR_ONE A_WR_ZERO VDD VSS / RM_IHPSG13_1024x32_c2_1P_BLDRV +XA_BM_TIEH A_TIEH_O VDD VSS / RSC_IHPSG13_TIEH +XA_I89 A_DCLK_B_L A_DCLK_B_R / RSC_IHPSG13_MET3RES +XA_I88 A_DCLK_L A_DCLK_R / RSC_IHPSG13_MET3RES +XA_I87 A_WCLK_L A_WCLK_R / RSC_IHPSG13_MET3RES +XA_I91 A_RCLK_B_R A_RCLK_B_L / RSC_IHPSG13_MET3RES +XA_R2 A_RCLK_R A_RCLK_L / RSC_IHPSG13_MET3RES +XA_I90 A_WCLK_B_R A_WCLK_B_L / RSC_IHPSG13_MET3RES +XA_ISENSE A_SAE A_BLC_SEL A_BLT_SEL net19 net20 VDD VSS / ++ RSC_IHPSG13_DFPQD_MSAFFX2 +XA_I78 A_RCLK_B_R A_SAE VDD VSS / RSC_IHPSG13_CBUFX2 +XA_I83 A_BM_R A_BM_N VDD VSS / RSC_IHPSG13_INVX2 +XA_I49 A_DI_R A_DI_N VDD VSS / RSC_IHPSG13_INVX2 +XA_I51 net19 A_DR_O VDD VSS / RSC_IHPSG13_INVX4 +XA_I69 A_DCLK_L A_DCLK_B_L VDD VSS / RSC_IHPSG13_CINVX2 +XA_I50 A_WCLK_L A_WCLK_B_R VDD VSS / RSC_IHPSG13_CINVX2 +XA_EBUF A_RCLK_R A_RCLK_B_R VDD VSS / RSC_IHPSG13_CINVX2 +.ENDS +.SUBCKT RM_IHPSG13_1024x32_c2_1P_COLDRV13_FILL4 VDD VSS +XI0<9> VDD VSS / RSC_IHPSG13_FILLCAP4 +XI0<8> VDD VSS / RSC_IHPSG13_FILLCAP4 +XI0<7> VDD VSS / RSC_IHPSG13_FILLCAP4 +XI0<6> VDD VSS / RSC_IHPSG13_FILLCAP4 +XI0<5> VDD VSS / RSC_IHPSG13_FILLCAP4 +XI0<4> VDD VSS / RSC_IHPSG13_FILLCAP4 +XI0<3> VDD VSS / RSC_IHPSG13_FILLCAP4 +XI0<2> VDD VSS / RSC_IHPSG13_FILLCAP4 +XI0<1> VDD VSS / RSC_IHPSG13_FILLCAP4 +.ENDS +.SUBCKT RM_IHPSG13_1024x32_c2_1P_COLDRV13_FILL4C2 VDD VSS +XI0<2> VDD VSS / RSC_IHPSG13_FILLCAP4 +XI0<1> VDD VSS / RSC_IHPSG13_FILLCAP4 +.ENDS + + +.SUBCKT RM_IHPSG13_1024x32_c2_1P_COLDEC4 ACLK_N ADDR<3> ADDR<2> ADDR<1> ADDR<0> ++ ADDR_COL<1> ADDR_COL<0> ADDR_DEC<7> ADDR_DEC<6> ADDR_DEC<5> ADDR_DEC<4> ++ ADDR_DEC<3> ADDR_DEC<2> ADDR_DEC<1> ADDR_DEC<0> BIST_ADDR<3> BIST_ADDR<2> ++ BIST_ADDR<1> BIST_ADDR<0> BIST_EN_I VDD VSS +XI15 ADDR_COL<1> VDD VSS / RSC_IHPSG13_TIEL +XI14 addr_int ADDR_COL<0> VDD VSS / RSC_IHPSG13_CBUFX2 +XDFF<3> BIST_EN_I BIST_ADDR<3> ACLK_N ADDR<3> addr_int net7<0> VDD VSS ++ / RSC_IHPSG13_DFNQMX2IX1 +XDFF<2> BIST_EN_I BIST_ADDR<2> ACLK_N ADDR<2> padr_int<2> net7<1> VDD ++ VSS / RSC_IHPSG13_DFNQMX2IX1 +XDFF<1> BIST_EN_I BIST_ADDR<1> ACLK_N ADDR<1> padr_int<1> net7<2> VDD ++ VSS / RSC_IHPSG13_DFNQMX2IX1 +XDFF<0> BIST_EN_I BIST_ADDR<0> ACLK_N ADDR<0> padr_int<0> net7<3> VDD ++ VSS / RSC_IHPSG13_DFNQMX2IX1 +XI1<7> PADR<0> PADR<1> PADR<2> addr_n<7> VDD VSS / RSC_IHPSG13_NAND3X2 +XI1<6> NADR<0> PADR<1> PADR<2> addr_n<6> VDD VSS / RSC_IHPSG13_NAND3X2 +XI1<5> PADR<0> NADR<1> PADR<2> addr_n<5> VDD VSS / RSC_IHPSG13_NAND3X2 +XI1<4> NADR<0> NADR<1> PADR<2> addr_n<4> VDD VSS / RSC_IHPSG13_NAND3X2 +XI1<3> PADR<0> PADR<1> NADR<2> addr_n<3> VDD VSS / RSC_IHPSG13_NAND3X2 +XI1<2> NADR<0> PADR<1> NADR<2> addr_n<2> VDD VSS / RSC_IHPSG13_NAND3X2 +XI1<1> PADR<0> NADR<1> NADR<2> addr_n<1> VDD VSS / RSC_IHPSG13_NAND3X2 +XI1<0> NADR<0> NADR<1> NADR<2> addr_n<0> VDD VSS / RSC_IHPSG13_NAND3X2 +XI13<2> NADR<2> PADR<2> VDD VSS / RSC_IHPSG13_INVX2 +XI13<1> NADR<1> PADR<1> VDD VSS / RSC_IHPSG13_INVX2 +XI13<0> NADR<0> PADR<0> VDD VSS / RSC_IHPSG13_INVX2 +XI3<2> padr_int<2> NADR<2> VDD VSS / RSC_IHPSG13_INVX2 +XI3<1> padr_int<1> NADR<1> VDD VSS / RSC_IHPSG13_INVX2 +XI3<0> padr_int<0> NADR<0> VDD VSS / RSC_IHPSG13_INVX2 +XI2<7> addr_n<7> ADDR_DEC<7> VDD VSS / RSC_IHPSG13_INVX2 +XI2<6> addr_n<6> ADDR_DEC<6> VDD VSS / RSC_IHPSG13_INVX2 +XI2<5> addr_n<5> ADDR_DEC<5> VDD VSS / RSC_IHPSG13_INVX2 +XI2<4> addr_n<4> ADDR_DEC<4> VDD VSS / RSC_IHPSG13_INVX2 +XI2<3> addr_n<3> ADDR_DEC<3> VDD VSS / RSC_IHPSG13_INVX2 +XI2<2> addr_n<2> ADDR_DEC<2> VDD VSS / RSC_IHPSG13_INVX2 +XI2<1> addr_n<1> ADDR_DEC<1> VDD VSS / RSC_IHPSG13_INVX2 +XI2<0> addr_n<0> ADDR_DEC<0> VDD VSS / RSC_IHPSG13_INVX2 +XI16<3> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI16<2> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI16<1> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI17<2> VDD VSS / RSC_IHPSG13_FILLCAP4 +XI17<1> VDD VSS / RSC_IHPSG13_FILLCAP4 +.ENDS +.SUBCKT RSC_IHPSG13_AND2X4 A B Z VDD VSS +MN3 Z net6 VSS VSS sg13_lv_nmos m=1 w=1.96u l=130.00n ng=2 nrd=0 nrs=0 +MN4 net9 B VSS VSS sg13_lv_nmos m=1 w=500.0n l=130.00n ng=1 nrd=0 nrs=0 +MN6 net6 A net9 VSS sg13_lv_nmos m=1 w=500.0n l=130.00n ng=1 nrd=0 nrs=0 +MP2 Z net6 VDD VDD sg13_lv_pmos m=1 w=3.24u l=130.00n ng=2 nrd=0 nrs=0 +MP0 net6 B VDD VDD sg13_lv_pmos m=1 w=860.00n l=130.00n ng=1 nrd=0 ++ nrs=0 +MP1 net6 A VDD VDD sg13_lv_pmos m=1 w=860.00n l=130.00n ng=1 nrd=0 ++ nrs=0 +.ENDS +.SUBCKT RM_IHPSG13_1024x32_c2_1P_COLCTRL4 A_ADDR_COL A_ADDR_DEC<7> A_ADDR_DEC<6> ++ A_ADDR_DEC<5> A_ADDR_DEC<4> A_ADDR_DEC<3> A_ADDR_DEC<2> A_ADDR_DEC<1> ++ A_ADDR_DEC<0> A_BIST_BM_I A_BIST_DW_I A_BIST_EN_I A_BLC<15> A_BLC<14> ++ A_BLC<13> A_BLC<12> A_BLC<11> A_BLC<10> A_BLC<9> A_BLC<8> A_BLC<7> A_BLC<6> ++ A_BLC<5> A_BLC<4> A_BLC<3> A_BLC<2> A_BLC<1> A_BLC<0> A_BLT<15> A_BLT<14> ++ A_BLT<13> A_BLT<12> A_BLT<11> A_BLT<10> A_BLT<9> A_BLT<8> A_BLT<7> A_BLT<6> ++ A_BLT<5> A_BLT<4> A_BLT<3> A_BLT<2> A_BLT<1> A_BLT<0> A_BM_I A_DCLK_B_L ++ A_DCLK_B_R A_DCLK_L A_DCLK_R A_DR_O A_DW_I A_RCLK_B_L A_RCLK_B_R A_RCLK_L ++ A_RCLK_R A_TIEH_O A_WCLK_B_L A_WCLK_B_R A_WCLK_L A_WCLK_R VDD VSS +XA_I80 A_WCLK_B_L A_RCLK_B_L net21 VDD VSS / RSC_IHPSG13_AND2X2 +XA_I76 A_DO_WRITE_P A_DI_N A_WR_ZERO VDD VSS / RSC_IHPSG13_AND2X4 +XA_I75 A_DI_R A_DO_WRITE_P A_WR_ONE VDD VSS / RSC_IHPSG13_AND2X4 +XA_CAPS<8> VDD VSS / RSC_IHPSG13_FILLCAP4 +XA_CAPS<7> VDD VSS / RSC_IHPSG13_FILLCAP4 +XA_CAPS<6> VDD VSS / RSC_IHPSG13_FILLCAP4 +XA_CAPS<5> VDD VSS / RSC_IHPSG13_FILLCAP4 +XA_CAPS<4> VDD VSS / RSC_IHPSG13_FILLCAP4 +XA_CAPS<3> VDD VSS / RSC_IHPSG13_FILLCAP4 +XA_CAPS<2> VDD VSS / RSC_IHPSG13_FILLCAP4 +XA_CAPS<1> VDD VSS / RSC_IHPSG13_FILLCAP4 +XA_I69 A_DCLK_L A_DCLK_B_L VDD VSS / RSC_IHPSG13_CINVX4 +XA_I50 A_WCLK_L A_WCLK_B_L VDD VSS / RSC_IHPSG13_CINVX4 +XA_EBUF A_RCLK_L A_RCLK_B_L VDD VSS / RSC_IHPSG13_CINVX4 +XA_INV<1> A_N0 A_P0 VDD VSS / RSC_IHPSG13_CINVX4 +XA_INV<0> A_ADDR_COL A_N0 VDD VSS / RSC_IHPSG13_CINVX4 +XA_I81<1> net21 A_PRE_N VDD VSS / RSC_IHPSG13_CINVX4_WN +XA_I81<0> net21 A_PRE_N VDD VSS / RSC_IHPSG13_CINVX4_WN +XA_BLTMUX<15> A_BLC<15> A_BLC_SEL A_BLT<15> A_BLT_SEL A_PRE_N A_SEL_P<15> ++ A_WR_ONE A_WR_ZERO VDD VSS / RM_IHPSG13_1024x32_c2_1P_BLDRV +XA_BLTMUX<14> A_BLC<14> A_BLC_SEL A_BLT<14> A_BLT_SEL A_PRE_N A_SEL_P<14> ++ A_WR_ONE A_WR_ZERO VDD VSS / RM_IHPSG13_1024x32_c2_1P_BLDRV +XA_BLTMUX<13> A_BLC<13> A_BLC_SEL A_BLT<13> A_BLT_SEL A_PRE_N A_SEL_P<13> ++ A_WR_ONE A_WR_ZERO VDD VSS / RM_IHPSG13_1024x32_c2_1P_BLDRV +XA_BLTMUX<12> A_BLC<12> A_BLC_SEL A_BLT<12> A_BLT_SEL A_PRE_N A_SEL_P<12> ++ A_WR_ONE A_WR_ZERO VDD VSS / RM_IHPSG13_1024x32_c2_1P_BLDRV +XA_BLTMUX<11> A_BLC<11> A_BLC_SEL A_BLT<11> A_BLT_SEL A_PRE_N A_SEL_P<11> ++ A_WR_ONE A_WR_ZERO VDD VSS / RM_IHPSG13_1024x32_c2_1P_BLDRV +XA_BLTMUX<10> A_BLC<10> A_BLC_SEL A_BLT<10> A_BLT_SEL A_PRE_N A_SEL_P<10> ++ A_WR_ONE A_WR_ZERO VDD VSS / RM_IHPSG13_1024x32_c2_1P_BLDRV +XA_BLTMUX<9> A_BLC<9> A_BLC_SEL A_BLT<9> A_BLT_SEL A_PRE_N A_SEL_P<9> A_WR_ONE ++ A_WR_ZERO VDD VSS / RM_IHPSG13_1024x32_c2_1P_BLDRV +XA_BLTMUX<8> A_BLC<8> A_BLC_SEL A_BLT<8> A_BLT_SEL A_PRE_N A_SEL_P<8> A_WR_ONE ++ A_WR_ZERO VDD VSS / RM_IHPSG13_1024x32_c2_1P_BLDRV +XA_BLTMUX<7> A_BLC<7> A_BLC_SEL A_BLT<7> A_BLT_SEL A_PRE_N A_SEL_P<7> A_WR_ONE ++ A_WR_ZERO VDD VSS / RM_IHPSG13_1024x32_c2_1P_BLDRV +XA_BLTMUX<6> A_BLC<6> A_BLC_SEL A_BLT<6> A_BLT_SEL A_PRE_N A_SEL_P<6> A_WR_ONE ++ A_WR_ZERO VDD VSS / RM_IHPSG13_1024x32_c2_1P_BLDRV +XA_BLTMUX<5> A_BLC<5> A_BLC_SEL A_BLT<5> A_BLT_SEL A_PRE_N A_SEL_P<5> A_WR_ONE ++ A_WR_ZERO VDD VSS / RM_IHPSG13_1024x32_c2_1P_BLDRV +XA_BLTMUX<4> A_BLC<4> A_BLC_SEL A_BLT<4> A_BLT_SEL A_PRE_N A_SEL_P<4> A_WR_ONE ++ A_WR_ZERO VDD VSS / RM_IHPSG13_1024x32_c2_1P_BLDRV +XA_BLTMUX<3> A_BLC<3> A_BLC_SEL A_BLT<3> A_BLT_SEL A_PRE_N A_SEL_P<3> A_WR_ONE ++ A_WR_ZERO VDD VSS / RM_IHPSG13_1024x32_c2_1P_BLDRV +XA_BLTMUX<2> A_BLC<2> A_BLC_SEL A_BLT<2> A_BLT_SEL A_PRE_N A_SEL_P<2> A_WR_ONE ++ A_WR_ZERO VDD VSS / RM_IHPSG13_1024x32_c2_1P_BLDRV +XA_BLTMUX<1> A_BLC<1> A_BLC_SEL A_BLT<1> A_BLT_SEL A_PRE_N A_SEL_P<1> A_WR_ONE ++ A_WR_ZERO VDD VSS / RM_IHPSG13_1024x32_c2_1P_BLDRV +XA_BLTMUX<0> A_BLC<0> A_BLC_SEL A_BLT<0> A_BLT_SEL A_PRE_N A_SEL_P<0> A_WR_ONE ++ A_WR_ZERO VDD VSS / RM_IHPSG13_1024x32_c2_1P_BLDRV +XA_R2 A_RCLK_L A_RCLK_R / RSC_IHPSG13_MET3RES +XA_I87 A_WCLK_L A_WCLK_R / RSC_IHPSG13_MET3RES +XA_I88 A_DCLK_L A_DCLK_R / RSC_IHPSG13_MET3RES +XA_I89 A_DCLK_B_L A_DCLK_B_R / RSC_IHPSG13_MET3RES +XA_I90 A_WCLK_B_L A_WCLK_B_R / RSC_IHPSG13_MET3RES +XA_I91 A_RCLK_B_L A_RCLK_B_R / RSC_IHPSG13_MET3RES +XA_ISENSE A_SAE A_BLC_SEL A_BLT_SEL net19 net20 VDD VSS / ++ RSC_IHPSG13_DFPQD_MSAFFX2 +XA_I51 net19 A_DR_O VDD VSS / RSC_IHPSG13_INVX4 +XA_I78 A_RCLK_B_L A_SAE VDD VSS / RSC_IHPSG13_CBUFX2 +XA_DREG A_BIST_EN_I A_BIST_DW_I A_DCLK_B_L A_DW_I A_DI_R net22 VDD VSS ++ / RSC_IHPSG13_DFNQMX2IX1 +XA_BREG A_BIST_EN_I A_BIST_BM_I A_DCLK_B_L A_BM_I A_BM_R net24 VDD VSS ++ / RSC_IHPSG13_DFNQMX2IX1 +XA_DEC3INV<15> net23<0> A_SEL_P<15> VDD VSS / RSC_IHPSG13_INVX2 +XA_DEC3INV<14> net23<1> A_SEL_P<14> VDD VSS / RSC_IHPSG13_INVX2 +XA_DEC3INV<13> net23<2> A_SEL_P<13> VDD VSS / RSC_IHPSG13_INVX2 +XA_DEC3INV<12> net23<3> A_SEL_P<12> VDD VSS / RSC_IHPSG13_INVX2 +XA_DEC3INV<11> net23<4> A_SEL_P<11> VDD VSS / RSC_IHPSG13_INVX2 +XA_DEC3INV<10> net23<5> A_SEL_P<10> VDD VSS / RSC_IHPSG13_INVX2 +XA_DEC3INV<9> net23<6> A_SEL_P<9> VDD VSS / RSC_IHPSG13_INVX2 +XA_DEC3INV<8> net23<7> A_SEL_P<8> VDD VSS / RSC_IHPSG13_INVX2 +XA_DEC3INV<7> net23<8> A_SEL_P<7> VDD VSS / RSC_IHPSG13_INVX2 +XA_DEC3INV<6> net23<9> A_SEL_P<6> VDD VSS / RSC_IHPSG13_INVX2 +XA_DEC3INV<5> net23<10> A_SEL_P<5> VDD VSS / RSC_IHPSG13_INVX2 +XA_DEC3INV<4> net23<11> A_SEL_P<4> VDD VSS / RSC_IHPSG13_INVX2 +XA_DEC3INV<3> net23<12> A_SEL_P<3> VDD VSS / RSC_IHPSG13_INVX2 +XA_DEC3INV<2> net23<13> A_SEL_P<2> VDD VSS / RSC_IHPSG13_INVX2 +XA_DEC3INV<1> net23<14> A_SEL_P<1> VDD VSS / RSC_IHPSG13_INVX2 +XA_DEC3INV<0> net23<15> A_SEL_P<0> VDD VSS / RSC_IHPSG13_INVX2 +XA_I83 A_BM_R A_BM_N VDD VSS / RSC_IHPSG13_INVX2 +XA_I49 A_DI_R A_DI_N VDD VSS / RSC_IHPSG13_INVX2 +XA_I70<4> VDD VSS / RSC_IHPSG13_FILLCAP8 +XA_I70<3> VDD VSS / RSC_IHPSG13_FILLCAP8 +XA_I70<2> VDD VSS / RSC_IHPSG13_FILLCAP8 +XA_I70<1> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI73<14> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI73<13> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI73<12> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI73<11> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI73<10> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI73<9> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI73<8> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI73<7> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI73<6> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI73<5> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI73<4> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI73<3> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI73<2> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI73<1> VDD VSS / RSC_IHPSG13_FILLCAP8 +XA_I44 A_BM_N A_WCLK_B_L A_DO_WRITE_P VDD VSS / RSC_IHPSG13_NOR2X2 +XA_DEC3<15> A_P0 A_ADDR_DEC<7> net23<0> VDD VSS / RSC_IHPSG13_NAND2X2 +XA_DEC3<14> A_P0 A_ADDR_DEC<6> net23<1> VDD VSS / RSC_IHPSG13_NAND2X2 +XA_DEC3<13> A_P0 A_ADDR_DEC<5> net23<2> VDD VSS / RSC_IHPSG13_NAND2X2 +XA_DEC3<12> A_P0 A_ADDR_DEC<4> net23<3> VDD VSS / RSC_IHPSG13_NAND2X2 +XA_DEC3<11> A_P0 A_ADDR_DEC<3> net23<4> VDD VSS / RSC_IHPSG13_NAND2X2 +XA_DEC3<10> A_P0 A_ADDR_DEC<2> net23<5> VDD VSS / RSC_IHPSG13_NAND2X2 +XA_DEC3<9> A_P0 A_ADDR_DEC<1> net23<6> VDD VSS / RSC_IHPSG13_NAND2X2 +XA_DEC3<8> A_P0 A_ADDR_DEC<0> net23<7> VDD VSS / RSC_IHPSG13_NAND2X2 +XA_DEC3<7> A_N0 A_ADDR_DEC<7> net23<8> VDD VSS / RSC_IHPSG13_NAND2X2 +XA_DEC3<6> A_N0 A_ADDR_DEC<6> net23<9> VDD VSS / RSC_IHPSG13_NAND2X2 +XA_DEC3<5> A_N0 A_ADDR_DEC<5> net23<10> VDD VSS / RSC_IHPSG13_NAND2X2 +XA_DEC3<4> A_N0 A_ADDR_DEC<4> net23<11> VDD VSS / RSC_IHPSG13_NAND2X2 +XA_DEC3<3> A_N0 A_ADDR_DEC<3> net23<12> VDD VSS / RSC_IHPSG13_NAND2X2 +XA_DEC3<2> A_N0 A_ADDR_DEC<2> net23<13> VDD VSS / RSC_IHPSG13_NAND2X2 +XA_DEC3<1> A_N0 A_ADDR_DEC<1> net23<14> VDD VSS / RSC_IHPSG13_NAND2X2 +XA_DEC3<0> A_N0 A_ADDR_DEC<0> net23<15> VDD VSS / RSC_IHPSG13_NAND2X2 +XA_BM_TIEH A_TIEH_O VDD VSS / RSC_IHPSG13_TIEH +.ENDS + + +.SUBCKT RM_IHPSG13_1024x32_c2_1P_COLDEC3 ACLK_N ADDR<2> ADDR<1> ADDR<0> ADDR_COL<1> ++ ADDR_COL<0> ADDR_DEC<7> ADDR_DEC<6> ADDR_DEC<5> ADDR_DEC<4> ADDR_DEC<3> ++ ADDR_DEC<2> ADDR_DEC<1> ADDR_DEC<0> BIST_ADDR<2> BIST_ADDR<1> BIST_ADDR<0> ++ BIST_EN_I VDD VSS +XI15<1> ADDR_COL<1> VDD VSS / RSC_IHPSG13_TIEL +XI15<0> ADDR_COL<0> VDD VSS / RSC_IHPSG13_TIEL +XI1<7> PADR<0> PADR<1> PADR<2> addr_n<7> VDD VSS / RSC_IHPSG13_NAND3X2 +XI1<6> NADR<0> PADR<1> PADR<2> addr_n<6> VDD VSS / RSC_IHPSG13_NAND3X2 +XI1<5> PADR<0> NADR<1> PADR<2> addr_n<5> VDD VSS / RSC_IHPSG13_NAND3X2 +XI1<4> NADR<0> NADR<1> PADR<2> addr_n<4> VDD VSS / RSC_IHPSG13_NAND3X2 +XI1<3> PADR<0> PADR<1> NADR<2> addr_n<3> VDD VSS / RSC_IHPSG13_NAND3X2 +XI1<2> NADR<0> PADR<1> NADR<2> addr_n<2> VDD VSS / RSC_IHPSG13_NAND3X2 +XI1<1> PADR<0> NADR<1> NADR<2> addr_n<1> VDD VSS / RSC_IHPSG13_NAND3X2 +XI1<0> NADR<0> NADR<1> NADR<2> addr_n<0> VDD VSS / RSC_IHPSG13_NAND3X2 +XDFF<2> BIST_EN_I BIST_ADDR<2> ACLK_N ADDR<2> padr_int<2> net6<0> VDD ++ VSS / RSC_IHPSG13_DFNQMX2IX1 +XDFF<1> BIST_EN_I BIST_ADDR<1> ACLK_N ADDR<1> padr_int<1> net6<1> VDD ++ VSS / RSC_IHPSG13_DFNQMX2IX1 +XDFF<0> BIST_EN_I BIST_ADDR<0> ACLK_N ADDR<0> padr_int<0> net6<2> VDD ++ VSS / RSC_IHPSG13_DFNQMX2IX1 +XI17<2> VDD VSS / RSC_IHPSG13_FILLCAP4 +XI17<1> VDD VSS / RSC_IHPSG13_FILLCAP4 +XI13<2> NADR<2> PADR<2> VDD VSS / RSC_IHPSG13_INVX2 +XI13<1> NADR<1> PADR<1> VDD VSS / RSC_IHPSG13_INVX2 +XI13<0> NADR<0> PADR<0> VDD VSS / RSC_IHPSG13_INVX2 +XI3<2> padr_int<2> NADR<2> VDD VSS / RSC_IHPSG13_INVX2 +XI3<1> padr_int<1> NADR<1> VDD VSS / RSC_IHPSG13_INVX2 +XI3<0> padr_int<0> NADR<0> VDD VSS / RSC_IHPSG13_INVX2 +XI2<7> addr_n<7> ADDR_DEC<7> VDD VSS / RSC_IHPSG13_INVX2 +XI2<6> addr_n<6> ADDR_DEC<6> VDD VSS / RSC_IHPSG13_INVX2 +XI2<5> addr_n<5> ADDR_DEC<5> VDD VSS / RSC_IHPSG13_INVX2 +XI2<4> addr_n<4> ADDR_DEC<4> VDD VSS / RSC_IHPSG13_INVX2 +XI2<3> addr_n<3> ADDR_DEC<3> VDD VSS / RSC_IHPSG13_INVX2 +XI2<2> addr_n<2> ADDR_DEC<2> VDD VSS / RSC_IHPSG13_INVX2 +XI2<1> addr_n<1> ADDR_DEC<1> VDD VSS / RSC_IHPSG13_INVX2 +XI2<0> addr_n<0> ADDR_DEC<0> VDD VSS / RSC_IHPSG13_INVX2 +XI16<6> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI16<5> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI16<4> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI16<3> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI16<2> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI16<1> VDD VSS / RSC_IHPSG13_FILLCAP8 +.ENDS +.SUBCKT RM_IHPSG13_1024x32_c2_1P_COLCTRL3 A_ADDR_DEC<7> A_ADDR_DEC<6> A_ADDR_DEC<5> ++ A_ADDR_DEC<4> A_ADDR_DEC<3> A_ADDR_DEC<2> A_ADDR_DEC<1> A_ADDR_DEC<0> ++ A_BIST_BM_I A_BIST_DW_I A_BIST_EN_I A_BLC<7> A_BLC<6> A_BLC<5> A_BLC<4> ++ A_BLC<3> A_BLC<2> A_BLC<1> A_BLC<0> A_BLT<7> A_BLT<6> A_BLT<5> A_BLT<4> ++ A_BLT<3> A_BLT<2> A_BLT<1> A_BLT<0> A_BM_I A_DCLK_B_L A_DCLK_B_R A_DCLK_L ++ A_DCLK_R A_DR_O A_DW_I A_RCLK_B_L A_RCLK_B_R A_RCLK_L A_RCLK_R A_TIEH_O ++ A_WCLK_B_L A_WCLK_B_R A_WCLK_L A_WCLK_R VDD VSS +XA_DREG A_BIST_EN_I A_BIST_DW_I A_DCLK_B_L A_DW_I A_DI_R net22 VDD VSS ++ / RSC_IHPSG13_DFNQMX2IX1 +XA_BREG A_BIST_EN_I A_BIST_BM_I A_DCLK_B_R A_BM_I A_BM_R net23 VDD VSS ++ / RSC_IHPSG13_DFNQMX2IX1 +XA_I70<8> VDD VSS / RSC_IHPSG13_FILLCAP8 +XA_I70<7> VDD VSS / RSC_IHPSG13_FILLCAP8 +XA_I70<6> VDD VSS / RSC_IHPSG13_FILLCAP8 +XA_I70<5> VDD VSS / RSC_IHPSG13_FILLCAP8 +XA_I70<4> VDD VSS / RSC_IHPSG13_FILLCAP8 +XA_I70<3> VDD VSS / RSC_IHPSG13_FILLCAP8 +XA_I70<2> VDD VSS / RSC_IHPSG13_FILLCAP8 +XA_I70<1> VDD VSS / RSC_IHPSG13_FILLCAP8 +XA_I51 net19 A_DR_O VDD VSS / RSC_IHPSG13_INVX4 +XA_I44 A_BM_N A_WCLK_B_R A_DO_WRITE_P VDD VSS / RSC_IHPSG13_NOR2X2 +XA_BM_TIEH A_TIEH_O VDD VSS / RSC_IHPSG13_TIEH +XA_BLTMUX<7> A_BLC<7> A_BLC_SEL A_BLT<7> A_BLT_SEL A_PRE_N A_ADDR_DEC<7> ++ A_WR_ONE A_WR_ZERO VDD VSS / RM_IHPSG13_1024x32_c2_1P_BLDRV +XA_BLTMUX<6> A_BLC<6> A_BLC_SEL A_BLT<6> A_BLT_SEL A_PRE_N A_ADDR_DEC<6> ++ A_WR_ONE A_WR_ZERO VDD VSS / RM_IHPSG13_1024x32_c2_1P_BLDRV +XA_BLTMUX<5> A_BLC<5> A_BLC_SEL A_BLT<5> A_BLT_SEL A_PRE_N A_ADDR_DEC<5> ++ A_WR_ONE A_WR_ZERO VDD VSS / RM_IHPSG13_1024x32_c2_1P_BLDRV +XA_BLTMUX<4> A_BLC<4> A_BLC_SEL A_BLT<4> A_BLT_SEL A_PRE_N A_ADDR_DEC<4> ++ A_WR_ONE A_WR_ZERO VDD VSS / RM_IHPSG13_1024x32_c2_1P_BLDRV +XA_BLTMUX<3> A_BLC<3> A_BLC_SEL A_BLT<3> A_BLT_SEL A_PRE_N A_ADDR_DEC<3> ++ A_WR_ONE A_WR_ZERO VDD VSS / RM_IHPSG13_1024x32_c2_1P_BLDRV +XA_BLTMUX<2> A_BLC<2> A_BLC_SEL A_BLT<2> A_BLT_SEL A_PRE_N A_ADDR_DEC<2> ++ A_WR_ONE A_WR_ZERO VDD VSS / RM_IHPSG13_1024x32_c2_1P_BLDRV +XA_BLTMUX<1> A_BLC<1> A_BLC_SEL A_BLT<1> A_BLT_SEL A_PRE_N A_ADDR_DEC<1> ++ A_WR_ONE A_WR_ZERO VDD VSS / RM_IHPSG13_1024x32_c2_1P_BLDRV +XA_BLTMUX<0> A_BLC<0> A_BLC_SEL A_BLT<0> A_BLT_SEL A_PRE_N A_ADDR_DEC<0> ++ A_WR_ONE A_WR_ZERO VDD VSS / RM_IHPSG13_1024x32_c2_1P_BLDRV +XA_I49 A_DI_R A_DI_N VDD VSS / RSC_IHPSG13_INVX2 +XA_I83 A_BM_R A_BM_N VDD VSS / RSC_IHPSG13_INVX2 +XA_I69 A_DCLK_L A_DCLK_B_L VDD VSS / RSC_IHPSG13_CINVX2 +XA_I50 A_WCLK_L A_WCLK_B_L VDD VSS / RSC_IHPSG13_CINVX2 +XA_EBUF A_RCLK_L A_RCLK_B_L VDD VSS / RSC_IHPSG13_CINVX2 +XA_I78 A_RCLK_B_L A_SAE VDD VSS / RSC_IHPSG13_CBUFX2 +XA_I88 A_DCLK_L A_DCLK_R / RSC_IHPSG13_MET3RES +XA_I87 A_WCLK_L A_WCLK_R / RSC_IHPSG13_MET3RES +XA_R2 A_RCLK_L A_RCLK_R / RSC_IHPSG13_MET3RES +XA_I91 A_RCLK_B_L A_RCLK_B_R / RSC_IHPSG13_MET3RES +XA_I90 A_WCLK_B_L A_WCLK_B_R / RSC_IHPSG13_MET3RES +XA_I89 A_DCLK_B_L A_DCLK_B_R / RSC_IHPSG13_MET3RES +XA_I80 A_WCLK_B_R A_RCLK_B_R net21 VDD VSS / RSC_IHPSG13_AND2X2 +XA_I76 A_DI_N A_DO_WRITE_P A_WR_ZERO VDD VSS / RSC_IHPSG13_AND2X2 +XA_I75 A_DI_R A_DO_WRITE_P A_WR_ONE VDD VSS / RSC_IHPSG13_AND2X2 +XA_ISENSE A_SAE A_BLC_SEL A_BLT_SEL net19 net20 VDD VSS / ++ RSC_IHPSG13_DFPQD_MSAFFX2 +XA_I81 net21 A_PRE_N VDD VSS / RSC_IHPSG13_CINVX4_WN +XA_CAPS<5> VDD VSS / RSC_IHPSG13_FILLCAP4 +XA_CAPS<4> VDD VSS / RSC_IHPSG13_FILLCAP4 +XA_CAPS<3> VDD VSS / RSC_IHPSG13_FILLCAP4 +XA_CAPS<2> VDD VSS / RSC_IHPSG13_FILLCAP4 +XA_CAPS<1> VDD VSS / RSC_IHPSG13_FILLCAP4 +.ENDS + +.SUBCKT RM_IHPSG13_1024x32_c2_2P_BITKIT_16x2_CORNER VDD_CORE VSS +XI16 VDD_CORE VSS VDD_CORE VSS / ++ RM_IHPSG13_1024x32_c2_1P_BITKIT_CORNER +.ENDS +.SUBCKT RM_IHPSG13_1024x32_c2_2P_BITKIT_EDGE_LR A_WL B_WL NW PW VDD VSS +MN1 VSS A_WL VSS VSS sg13_lv_nmos m=1 w=300.0n l=130.00n ng=1 nrd=0 nrs=0 +MN0 VSS B_WL VSS VSS sg13_lv_nmos m=1 w=300.0n l=130.00n ng=1 nrd=0 nrs=0 +.ENDS +.SUBCKT RM_IHPSG13_1024x32_c2_2P_BITKIT_16x2_EDGE_LR A_WL<15> A_WL<14> A_WL<13> A_WL<12> ++ A_WL<11> A_WL<10> A_WL<9> A_WL<8> A_WL<7> A_WL<6> A_WL<5> A_WL<4> A_WL<3> ++ A_WL<2> A_WL<1> A_WL<0> B_WL<15> B_WL<14> B_WL<13> B_WL<12> B_WL<11> ++ B_WL<10> B_WL<9> B_WL<8> B_WL<7> B_WL<6> B_WL<5> B_WL<4> B_WL<3> B_WL<2> ++ B_WL<1> B_WL<0> VDD_CORE VSS +XI0<15> A_WL<15> B_WL<15> VDD_CORE VSS VDD_CORE VSS ++ / RM_IHPSG13_1024x32_c2_2P_BITKIT_EDGE_LR +XI0<14> A_WL<14> B_WL<14> VDD_CORE VSS VDD_CORE VSS ++ / RM_IHPSG13_1024x32_c2_2P_BITKIT_EDGE_LR +XI0<13> A_WL<13> B_WL<13> VDD_CORE VSS VDD_CORE VSS ++ / RM_IHPSG13_1024x32_c2_2P_BITKIT_EDGE_LR +XI0<12> A_WL<12> B_WL<12> VDD_CORE VSS VDD_CORE VSS ++ / RM_IHPSG13_1024x32_c2_2P_BITKIT_EDGE_LR +XI0<11> A_WL<11> B_WL<11> VDD_CORE VSS VDD_CORE VSS ++ / RM_IHPSG13_1024x32_c2_2P_BITKIT_EDGE_LR +XI0<10> A_WL<10> B_WL<10> VDD_CORE VSS VDD_CORE VSS ++ / RM_IHPSG13_1024x32_c2_2P_BITKIT_EDGE_LR +XI0<9> A_WL<9> B_WL<9> VDD_CORE VSS VDD_CORE VSS / ++ RM_IHPSG13_1024x32_c2_2P_BITKIT_EDGE_LR +XI0<8> A_WL<8> B_WL<8> VDD_CORE VSS VDD_CORE VSS / ++ RM_IHPSG13_1024x32_c2_2P_BITKIT_EDGE_LR +XI0<7> A_WL<7> B_WL<7> VDD_CORE VSS VDD_CORE VSS / ++ RM_IHPSG13_1024x32_c2_2P_BITKIT_EDGE_LR +XI0<6> A_WL<6> B_WL<6> VDD_CORE VSS VDD_CORE VSS / ++ RM_IHPSG13_1024x32_c2_2P_BITKIT_EDGE_LR +XI0<5> A_WL<5> B_WL<5> VDD_CORE VSS VDD_CORE VSS / ++ RM_IHPSG13_1024x32_c2_2P_BITKIT_EDGE_LR +XI0<4> A_WL<4> B_WL<4> VDD_CORE VSS VDD_CORE VSS / ++ RM_IHPSG13_1024x32_c2_2P_BITKIT_EDGE_LR +XI0<3> A_WL<3> B_WL<3> VDD_CORE VSS VDD_CORE VSS / ++ RM_IHPSG13_1024x32_c2_2P_BITKIT_EDGE_LR +XI0<2> A_WL<2> B_WL<2> VDD_CORE VSS VDD_CORE VSS / ++ RM_IHPSG13_1024x32_c2_2P_BITKIT_EDGE_LR +XI0<1> A_WL<1> B_WL<1> VDD_CORE VSS VDD_CORE VSS / ++ RM_IHPSG13_1024x32_c2_2P_BITKIT_EDGE_LR +XI0<0> A_WL<0> B_WL<0> VDD_CORE VSS VDD_CORE VSS / ++ RM_IHPSG13_1024x32_c2_2P_BITKIT_EDGE_LR +.ENDS +.SUBCKT RM_IHPSG13_1024x32_c2_2P_BITKIT_CELL A_BLC_BOT A_BLC_TOP A_BLT_BOT A_BLT_TOP ++ A_LWL A_RWL B_BLC_BOT B_BLC_TOP B_BLT_BOT B_BLT_TOP B_LWL B_RWL NW PW VDD VSS +MN5 NC B_RWL B_BLC_BOT PW sg13_lv_nmos m=1 w=300.0n l=130.00n ng=1 nrd=0 nrs=0 +MN4 B_BLT_BOT B_LWL NT PW sg13_lv_nmos m=1 w=300.0n l=130.00n ng=1 nrd=0 nrs=0 +MN0 NC NT VSS PW sg13_lv_nmos m=1 w=600.0n l=130.00n ng=2 nrd=0 nrs=0 +MN1 NT NC VSS PW sg13_lv_nmos m=1 w=600.0n l=130.00n ng=2 nrd=0 nrs=0 +MN3 NC A_RWL A_BLC_TOP PW sg13_lv_nmos m=1 w=300.0n l=130.00n ng=1 nrd=0 nrs=0 +MN2 A_BLT_TOP A_LWL NT PW sg13_lv_nmos m=1 w=300.0n l=130.00n ng=1 nrd=0 nrs=0 +MP1 NT NC VDD NW sg13_lv_pmos m=1 w=150.00n l=130.00n ng=1 nrd=0 nrs=0 +MP0 NC NT VDD NW sg13_lv_pmos m=1 w=150.00n l=130.00n ng=1 nrd=0 nrs=0 +R5 B_RWL B_LWL lvsres w=2.6e-07 l=6e-07 +R4 B_BLC_BOT B_BLC_TOP lvsres w=2.6e-07 l=6e-07 +R3 B_BLT_BOT B_BLT_TOP lvsres w=2.6e-07 l=6e-07 +R1 A_BLC_BOT A_BLC_TOP lvsres w=2.6e-07 l=6e-07 +R0 A_BLT_BOT A_BLT_TOP lvsres w=2.6e-07 l=6e-07 +R2 A_RWL A_LWL lvsres w=2.6e-07 l=6e-07 +.ENDS +.SUBCKT RM_IHPSG13_1024x32_c2_2P_BITKIT_16x2_SRAM A_BLC_BOT<1> A_BLC_BOT<0> A_BLC_TOP<1> ++ A_BLC_TOP<0> A_BLT_BOT<1> A_BLT_BOT<0> A_BLT_TOP<1> A_BLT_TOP<0> A_LWL<15> ++ A_LWL<14> A_LWL<13> A_LWL<12> A_LWL<11> A_LWL<10> A_LWL<9> A_LWL<8> A_LWL<7> ++ A_LWL<6> A_LWL<5> A_LWL<4> A_LWL<3> A_LWL<2> A_LWL<1> A_LWL<0> A_RWL<15> ++ A_RWL<14> A_RWL<13> A_RWL<12> A_RWL<11> A_RWL<10> A_RWL<9> A_RWL<8> A_RWL<7> ++ A_RWL<6> A_RWL<5> A_RWL<4> A_RWL<3> A_RWL<2> A_RWL<1> A_RWL<0> B_BLC_BOT<1> ++ B_BLC_BOT<0> B_BLC_TOP<1> B_BLC_TOP<0> B_BLT_BOT<1> B_BLT_BOT<0> ++ B_BLT_TOP<1> B_BLT_TOP<0> B_LWL<15> B_LWL<14> B_LWL<13> B_LWL<12> B_LWL<11> ++ B_LWL<10> B_LWL<9> B_LWL<8> B_LWL<7> B_LWL<6> B_LWL<5> B_LWL<4> B_LWL<3> ++ B_LWL<2> B_LWL<1> B_LWL<0> B_RWL<15> B_RWL<14> B_RWL<13> B_RWL<12> B_RWL<11> ++ B_RWL<10> B_RWL<9> B_RWL<8> B_RWL<7> B_RWL<6> B_RWL<5> B_RWL<4> B_RWL<3> ++ B_RWL<2> B_RWL<1> B_RWL<0> VDD_CORE VSS +XCELL<31> A_BLC_TOP<1> A_RBLC<15> A_BLT_TOP<1> A_RBLT<15> A_XWL<15> A_RWL<15> ++ B_BLC_TOP<1> B_RBLC<15> B_BLT_TOP<1> B_RBLT<15> B_XWL<15> B_RWL<15> ++ VDD_CORE VSS VDD_CORE VSS / ++ RM_IHPSG13_1024x32_c2_2P_BITKIT_CELL +XCELL<30> A_RBLC<14> A_RBLC<15> A_RBLT<14> A_RBLT<15> A_XWL<14> A_RWL<14> ++ B_RBLC<14> B_RBLC<15> B_RBLT<14> B_RBLT<15> B_XWL<14> B_RWL<14> VDD_CORE ++ VSS VDD_CORE VSS / RM_IHPSG13_1024x32_c2_2P_BITKIT_CELL +XCELL<29> A_RBLC<14> A_RBLC<13> A_RBLT<14> A_RBLT<13> A_XWL<13> A_RWL<13> ++ B_RBLC<14> B_RBLC<13> B_RBLT<14> B_RBLT<13> B_XWL<13> B_RWL<13> VDD_CORE ++ VSS VDD_CORE VSS / RM_IHPSG13_1024x32_c2_2P_BITKIT_CELL +XCELL<28> A_RBLC<12> A_RBLC<13> A_RBLT<12> A_RBLT<13> A_XWL<12> A_RWL<12> ++ B_RBLC<12> B_RBLC<13> B_RBLT<12> B_RBLT<13> B_XWL<12> B_RWL<12> VDD_CORE ++ VSS VDD_CORE VSS / RM_IHPSG13_1024x32_c2_2P_BITKIT_CELL +XCELL<27> A_RBLC<12> A_RBLC<11> A_RBLT<12> A_RBLT<11> A_XWL<11> A_RWL<11> ++ B_RBLC<12> B_RBLC<11> B_RBLT<12> B_RBLT<11> B_XWL<11> B_RWL<11> VDD_CORE ++ VSS VDD_CORE VSS / RM_IHPSG13_1024x32_c2_2P_BITKIT_CELL +XCELL<26> A_RBLC<10> A_RBLC<11> A_RBLT<10> A_RBLT<11> A_XWL<10> A_RWL<10> ++ B_RBLC<10> B_RBLC<11> B_RBLT<10> B_RBLT<11> B_XWL<10> B_RWL<10> VDD_CORE ++ VSS VDD_CORE VSS / RM_IHPSG13_1024x32_c2_2P_BITKIT_CELL +XCELL<25> A_RBLC<10> A_RBLC<9> A_RBLT<10> A_RBLT<9> A_XWL<9> A_RWL<9> ++ B_RBLC<10> B_RBLC<9> B_RBLT<10> B_RBLT<9> B_XWL<9> B_RWL<9> VDD_CORE ++ VSS VDD_CORE VSS / RM_IHPSG13_1024x32_c2_2P_BITKIT_CELL +XCELL<24> A_RBLC<8> A_RBLC<9> A_RBLT<8> A_RBLT<9> A_XWL<8> A_RWL<8> B_RBLC<8> ++ B_RBLC<9> B_RBLT<8> B_RBLT<9> B_XWL<8> B_RWL<8> VDD_CORE VSS ++ VDD_CORE VSS / RM_IHPSG13_1024x32_c2_2P_BITKIT_CELL +XCELL<23> A_RBLC<8> A_RBLC<7> A_RBLT<8> A_RBLT<7> A_XWL<7> A_RWL<7> B_RBLC<8> ++ B_RBLC<7> B_RBLT<8> B_RBLT<7> B_XWL<7> B_RWL<7> VDD_CORE VSS ++ VDD_CORE VSS / RM_IHPSG13_1024x32_c2_2P_BITKIT_CELL +XCELL<22> A_RBLC<6> A_RBLC<7> A_RBLT<6> A_RBLT<7> A_XWL<6> A_RWL<6> B_RBLC<6> ++ B_RBLC<7> B_RBLT<6> B_RBLT<7> B_XWL<6> B_RWL<6> VDD_CORE VSS ++ VDD_CORE VSS / RM_IHPSG13_1024x32_c2_2P_BITKIT_CELL +XCELL<21> A_RBLC<6> A_RBLC<5> A_RBLT<6> A_RBLT<5> A_XWL<5> A_RWL<5> B_RBLC<6> ++ B_RBLC<5> B_RBLT<6> B_RBLT<5> B_XWL<5> B_RWL<5> VDD_CORE VSS ++ VDD_CORE VSS / RM_IHPSG13_1024x32_c2_2P_BITKIT_CELL +XCELL<20> A_RBLC<4> A_RBLC<5> A_RBLT<4> A_RBLT<5> A_XWL<4> A_RWL<4> B_RBLC<4> ++ B_RBLC<5> B_RBLT<4> B_RBLT<5> B_XWL<4> B_RWL<4> VDD_CORE VSS ++ VDD_CORE VSS / RM_IHPSG13_1024x32_c2_2P_BITKIT_CELL +XCELL<19> A_RBLC<4> A_RBLC<3> A_RBLT<4> A_RBLT<3> A_XWL<3> A_RWL<3> B_RBLC<4> ++ B_RBLC<3> B_RBLT<4> B_RBLT<3> B_XWL<3> B_RWL<3> VDD_CORE VSS ++ VDD_CORE VSS / RM_IHPSG13_1024x32_c2_2P_BITKIT_CELL +XCELL<18> A_RBLC<2> A_RBLC<3> A_RBLT<2> A_RBLT<3> A_XWL<2> A_RWL<2> B_RBLC<2> ++ B_RBLC<3> B_RBLT<2> B_RBLT<3> B_XWL<2> B_RWL<2> VDD_CORE VSS ++ VDD_CORE VSS / RM_IHPSG13_1024x32_c2_2P_BITKIT_CELL +XCELL<17> A_RBLC<2> A_RBLC<1> A_RBLT<2> A_RBLT<1> A_XWL<1> A_RWL<1> B_RBLC<2> ++ B_RBLC<1> B_RBLT<2> B_RBLT<1> B_XWL<1> B_RWL<1> VDD_CORE VSS ++ VDD_CORE VSS / RM_IHPSG13_1024x32_c2_2P_BITKIT_CELL +XCELL<16> A_BLC_BOT<1> A_RBLC<1> A_BLT_BOT<1> A_RBLT<1> A_XWL<0> A_RWL<0> ++ B_BLC_BOT<1> B_RBLC<1> B_BLT_BOT<1> B_RBLT<1> B_XWL<0> B_RWL<0> VDD_CORE ++ VSS VDD_CORE VSS / RM_IHPSG13_1024x32_c2_2P_BITKIT_CELL +XCELL<15> A_BLC_TOP<0> A_LBLC<15> A_BLT_TOP<0> A_LBLT<15> A_LWL<15> A_XWL<15> ++ B_BLC_TOP<0> B_LBLC<15> B_BLT_TOP<0> B_LBLT<15> B_LWL<15> B_XWL<15> ++ VDD_CORE VSS VDD_CORE VSS / ++ RM_IHPSG13_1024x32_c2_2P_BITKIT_CELL +XCELL<14> A_LBLC<14> A_LBLC<15> A_LBLT<14> A_LBLT<15> A_LWL<14> A_XWL<14> ++ B_LBLC<14> B_LBLC<15> B_LBLT<14> B_LBLT<15> B_LWL<14> B_XWL<14> VDD_CORE ++ VSS VDD_CORE VSS / RM_IHPSG13_1024x32_c2_2P_BITKIT_CELL +XCELL<13> A_LBLC<14> A_LBLC<13> A_LBLT<14> A_LBLT<13> A_LWL<13> A_XWL<13> ++ B_LBLC<14> B_LBLC<13> B_LBLT<14> B_LBLT<13> B_LWL<13> B_XWL<13> VDD_CORE ++ VSS VDD_CORE VSS / RM_IHPSG13_1024x32_c2_2P_BITKIT_CELL +XCELL<12> A_LBLC<12> A_LBLC<13> A_LBLT<12> A_LBLT<13> A_LWL<12> A_XWL<12> ++ B_LBLC<12> B_LBLC<13> B_LBLT<12> B_LBLT<13> B_LWL<12> B_XWL<12> VDD_CORE ++ VSS VDD_CORE VSS / RM_IHPSG13_1024x32_c2_2P_BITKIT_CELL +XCELL<11> A_LBLC<12> A_LBLC<11> A_LBLT<12> A_LBLT<11> A_LWL<11> A_XWL<11> ++ B_LBLC<12> B_LBLC<11> B_LBLT<12> B_LBLT<11> B_LWL<11> B_XWL<11> VDD_CORE ++ VSS VDD_CORE VSS / RM_IHPSG13_1024x32_c2_2P_BITKIT_CELL +XCELL<10> A_LBLC<10> A_LBLC<11> A_LBLT<10> A_LBLT<11> A_LWL<10> A_XWL<10> ++ B_LBLC<10> B_LBLC<11> B_LBLT<10> B_LBLT<11> B_LWL<10> B_XWL<10> VDD_CORE ++ VSS VDD_CORE VSS / RM_IHPSG13_1024x32_c2_2P_BITKIT_CELL +XCELL<9> A_LBLC<10> A_LBLC<9> A_LBLT<10> A_LBLT<9> A_LWL<9> A_XWL<9> ++ B_LBLC<10> B_LBLC<9> B_LBLT<10> B_LBLT<9> B_LWL<9> B_XWL<9> VDD_CORE ++ VSS VDD_CORE VSS / RM_IHPSG13_1024x32_c2_2P_BITKIT_CELL +XCELL<8> A_LBLC<8> A_LBLC<9> A_LBLT<8> A_LBLT<9> A_LWL<8> A_XWL<8> B_LBLC<8> ++ B_LBLC<9> B_LBLT<8> B_LBLT<9> B_LWL<8> B_XWL<8> VDD_CORE VSS ++ VDD_CORE VSS / RM_IHPSG13_1024x32_c2_2P_BITKIT_CELL +XCELL<7> A_LBLC<8> A_LBLC<7> A_LBLT<8> A_LBLT<7> A_LWL<7> A_XWL<7> B_LBLC<8> ++ B_LBLC<7> B_LBLT<8> B_LBLT<7> B_LWL<7> B_XWL<7> VDD_CORE VSS ++ VDD_CORE VSS / RM_IHPSG13_1024x32_c2_2P_BITKIT_CELL +XCELL<6> A_LBLC<6> A_LBLC<7> A_LBLT<6> A_LBLT<7> A_LWL<6> A_XWL<6> B_LBLC<6> ++ B_LBLC<7> B_LBLT<6> B_LBLT<7> B_LWL<6> B_XWL<6> VDD_CORE VSS ++ VDD_CORE VSS / RM_IHPSG13_1024x32_c2_2P_BITKIT_CELL +XCELL<5> A_LBLC<6> A_LBLC<5> A_LBLT<6> A_LBLT<5> A_LWL<5> A_XWL<5> B_LBLC<6> ++ B_LBLC<5> B_LBLT<6> B_LBLT<5> B_LWL<5> B_XWL<5> VDD_CORE VSS ++ VDD_CORE VSS / RM_IHPSG13_1024x32_c2_2P_BITKIT_CELL +XCELL<4> A_LBLC<4> A_LBLC<5> A_LBLT<4> A_LBLT<5> A_LWL<4> A_XWL<4> B_LBLC<4> ++ B_LBLC<5> B_LBLT<4> B_LBLT<5> B_LWL<4> B_XWL<4> VDD_CORE VSS ++ VDD_CORE VSS / RM_IHPSG13_1024x32_c2_2P_BITKIT_CELL +XCELL<3> A_LBLC<4> A_LBLC<3> A_LBLT<4> A_LBLT<3> A_LWL<3> A_XWL<3> B_LBLC<4> ++ B_LBLC<3> B_LBLT<4> B_LBLT<3> B_LWL<3> B_XWL<3> VDD_CORE VSS ++ VDD_CORE VSS / RM_IHPSG13_1024x32_c2_2P_BITKIT_CELL +XCELL<2> A_LBLC<2> A_LBLC<3> A_LBLT<2> A_LBLT<3> A_LWL<2> A_XWL<2> B_LBLC<2> ++ B_LBLC<3> B_LBLT<2> B_LBLT<3> B_LWL<2> B_XWL<2> VDD_CORE VSS ++ VDD_CORE VSS / RM_IHPSG13_1024x32_c2_2P_BITKIT_CELL +XCELL<1> A_LBLC<2> A_LBLC<1> A_LBLT<2> A_LBLT<1> A_LWL<1> A_XWL<1> B_LBLC<2> ++ B_LBLC<1> B_LBLT<2> B_LBLT<1> B_LWL<1> B_XWL<1> VDD_CORE VSS ++ VDD_CORE VSS / RM_IHPSG13_1024x32_c2_2P_BITKIT_CELL +XCELL<0> A_BLC_BOT<0> A_LBLC<1> A_BLT_BOT<0> A_LBLT<1> A_LWL<0> A_XWL<0> ++ B_BLC_BOT<0> B_LBLC<1> B_BLT_BOT<0> B_LBLT<1> B_LWL<0> B_XWL<0> VDD_CORE ++ VSS VDD_CORE VSS / RM_IHPSG13_1024x32_c2_2P_BITKIT_CELL +.ENDS +.SUBCKT RM_IHPSG13_1024x32_c2_2P_BITKIT_EDGE_TB A_BLC A_BLT B_BLC B_BLT NW PW VDD VSS +.ENDS +.SUBCKT RM_IHPSG13_1024x32_c2_2P_BITKIT_16x2_EDGE_TB A_BLC<1> A_BLC<0> A_BLT<1> A_BLT<0> ++ B_BLC<1> B_BLC<0> B_BLT<1> B_BLT<0> VDD_CORE VSS +XEDGE<1> A_BLC<1> A_BLT<1> B_BLC<1> B_BLT<1> VDD_CORE VSS ++ VDD_CORE VSS / RM_IHPSG13_1024x32_c2_2P_BITKIT_EDGE_TB +XEDGE<0> A_BLC<0> A_BLT<0> B_BLC<0> B_BLT<0> VDD_CORE VSS ++ VDD_CORE VSS / RM_IHPSG13_1024x32_c2_2P_BITKIT_EDGE_TB +.ENDS +.SUBCKT RM_IHPSG13_1024x32_c2_2P_BITKIT_TAP A_BLC A_BLT B_BLC B_BLT NW PW VDD VSS +.ENDS +.SUBCKT RM_IHPSG13_1024x32_c2_2P_BITKIT_16x2_TAP A_BLC<1> A_BLC<0> A_BLT<1> A_BLT<0> ++ B_BLC<1> B_BLC<0> B_BLT<1> B_BLT<0> VDD_CORE VSS +XIEDGEBP_COL1<1> A_BLC<1> A_BLT<1> B_BLC<1> B_BLT<1> VDD_CORE VSS ++ VDD_CORE VSS / RM_IHPSG13_1024x32_c2_2P_BITKIT_EDGE_TB +XIEDGEBP_COL1<0> A_BLC<1> A_BLT<1> B_BLC<1> B_BLT<1> VDD_CORE VSS ++ VDD_CORE VSS / RM_IHPSG13_1024x32_c2_2P_BITKIT_EDGE_TB +XIEDGEBP_COL2<1> A_BLC<0> A_BLT<0> B_BLC<0> B_BLT<0> VDD_CORE VSS ++ VDD_CORE VSS / RM_IHPSG13_1024x32_c2_2P_BITKIT_EDGE_TB +XIEDGEBP_COL2<0> A_BLC<0> A_BLT<0> B_BLC<0> B_BLT<0> VDD_CORE VSS ++ VDD_CORE VSS / RM_IHPSG13_1024x32_c2_2P_BITKIT_EDGE_TB +XITAP<1> A_BLC<1> A_BLT<1> B_BLC<1> B_BLT<1> VDD_CORE VSS ++ VDD_CORE VSS / RM_IHPSG13_1024x32_c2_2P_BITKIT_TAP +XITAP<0> A_BLC<0> A_BLT<0> B_BLC<0> B_BLT<0> VDD_CORE VSS ++ VDD_CORE VSS / RM_IHPSG13_1024x32_c2_2P_BITKIT_TAP +.ENDS + + +.SUBCKT RM_IHPSG13_1024x32_c2_1P_BITKIT_TAP_LR NW PW VDD VSS +.ENDS +.SUBCKT RM_IHPSG13_1024x32_c2_2P_BITKIT_16x2_TAP_LR VDD_CORE VSS +XCORNER<1> VDD_CORE VSS VDD_CORE VSS / ++ RM_IHPSG13_1024x32_c2_1P_BITKIT_CORNER +XCORNER<0> VDD_CORE VSS VDD_CORE VSS / ++ RM_IHPSG13_1024x32_c2_1P_BITKIT_CORNER +XTAP_BORDER VDD_CORE VSS VDD_CORE VSS / ++ RM_IHPSG13_1024x32_c2_1P_BITKIT_TAP_LR +.ENDS + +.SUBCKT RSC_IHPSG13_CBUFX12 A Z VDD VSS +MN1 Z net6 VSS VSS sg13_lv_nmos m=1 w=4.23u l=130.00n ng=6 nrd=0 nrs=0 +MN0 net6 A VSS VSS sg13_lv_nmos m=1 w=1.41u l=130.00n ng=2 nrd=0 nrs=0 +MP1 Z net6 VDD VDD sg13_lv_pmos m=1 w=9.72u l=130.00n ng=6 nrd=0 nrs=0 +MP0 net6 A VDD VDD sg13_lv_pmos m=1 w=3.24u l=130.00n ng=2 nrd=0 nrs=0 +.ENDS +.SUBCKT RM_IHPSG13_1024x32_c2_2P_COLDRV13X12 ADDR_COL_I<1> ADDR_COL_I<0> ADDR_COL_O<1> ++ ADDR_COL_O<0> ADDR_DEC_I<7> ADDR_DEC_I<6> ADDR_DEC_I<5> ADDR_DEC_I<4> ++ ADDR_DEC_I<3> ADDR_DEC_I<2> ADDR_DEC_I<1> ADDR_DEC_I<0> ADDR_DEC_O<7> ++ ADDR_DEC_O<6> ADDR_DEC_O<5> ADDR_DEC_O<4> ADDR_DEC_O<3> ADDR_DEC_O<2> ++ ADDR_DEC_O<1> ADDR_DEC_O<0> DCLK_I DCLK_O RCLK_I RCLK_O WCLK_I WCLK_O ++ VDD VSS +XI1<3> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI1<2> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI1<1> VDD VSS / RSC_IHPSG13_FILLCAP8 +XWCLK_DRV WCLK_I WCLK_O VDD VSS / RSC_IHPSG13_CBUFX12 +XRCLK_DRV RCLK_I RCLK_O VDD VSS / RSC_IHPSG13_CBUFX12 +XDCLK_DRV DCLK_I DCLK_O VDD VSS / RSC_IHPSG13_CBUFX12 +XADDR_COL_DRV<1> ADDR_COL_I<1> ADDR_COL_O<1> VDD VSS / ++ RSC_IHPSG13_CBUFX12 +XADDR_COL_DRV<0> ADDR_COL_I<0> ADDR_COL_O<0> VDD VSS / ++ RSC_IHPSG13_CBUFX12 +XADDR_DEC_DRV<7> ADDR_DEC_I<7> ADDR_DEC_O<7> VDD VSS / ++ RSC_IHPSG13_CBUFX12 +XADDR_DEC_DRV<6> ADDR_DEC_I<6> ADDR_DEC_O<6> VDD VSS / ++ RSC_IHPSG13_CBUFX12 +XADDR_DEC_DRV<5> ADDR_DEC_I<5> ADDR_DEC_O<5> VDD VSS / ++ RSC_IHPSG13_CBUFX12 +XADDR_DEC_DRV<4> ADDR_DEC_I<4> ADDR_DEC_O<4> VDD VSS / ++ RSC_IHPSG13_CBUFX12 +XADDR_DEC_DRV<3> ADDR_DEC_I<3> ADDR_DEC_O<3> VDD VSS / ++ RSC_IHPSG13_CBUFX12 +XADDR_DEC_DRV<2> ADDR_DEC_I<2> ADDR_DEC_O<2> VDD VSS / ++ RSC_IHPSG13_CBUFX12 +XADDR_DEC_DRV<1> ADDR_DEC_I<1> ADDR_DEC_O<1> VDD VSS / ++ RSC_IHPSG13_CBUFX12 +XADDR_DEC_DRV<0> ADDR_DEC_I<0> ADDR_DEC_O<0> VDD VSS / ++ RSC_IHPSG13_CBUFX12 +XI0<6> VDD VSS / RSC_IHPSG13_FILLCAP4 +XI0<5> VDD VSS / RSC_IHPSG13_FILLCAP4 +XI0<4> VDD VSS / RSC_IHPSG13_FILLCAP4 +XI0<3> VDD VSS / RSC_IHPSG13_FILLCAP4 +XI0<2> VDD VSS / RSC_IHPSG13_FILLCAP4 +XI0<1> VDD VSS / RSC_IHPSG13_FILLCAP4 +.ENDS +.SUBCKT RSC_IHPSG13_WLDRVX12 A Z VDD VSS +MN1 Z net6 VSS VSS sg13_lv_nmos m=1 w=1.41u l=130.00n ng=2 nrd=0 nrs=0 +MN0 net6 A VSS VSS sg13_lv_nmos m=1 w=1.8u l=130.00n ng=2 nrd=0 nrs=0 +MP1 Z net6 VDD VDD sg13_lv_pmos m=1 w=9.72u l=130.00n ng=6 nrd=0 nrs=0 +MP0 net6 A VDD VDD sg13_lv_pmos m=1 w=900.0n l=130.00n ng=1 nrd=0 nrs=0 +.ENDS +.SUBCKT RM_IHPSG13_1024x32_c2_2P_WLDRV16X12 A<15> A<14> A<13> A<12> A<11> A<10> A<9> A<8> ++ A<7> A<6> A<5> A<4> A<3> A<2> A<1> A<0> Z<15> Z<14> Z<13> Z<12> Z<11> Z<10> ++ Z<9> Z<8> Z<7> Z<6> Z<5> Z<4> Z<3> Z<2> Z<1> Z<0> VDD VSS +XBUF<15> A<15> Z<15> VDD VSS / RSC_IHPSG13_WLDRVX12 +XBUF<14> A<14> Z<14> VDD VSS / RSC_IHPSG13_WLDRVX12 +XBUF<13> A<13> Z<13> VDD VSS / RSC_IHPSG13_WLDRVX12 +XBUF<12> A<12> Z<12> VDD VSS / RSC_IHPSG13_WLDRVX12 +XBUF<11> A<11> Z<11> VDD VSS / RSC_IHPSG13_WLDRVX12 +XBUF<10> A<10> Z<10> VDD VSS / RSC_IHPSG13_WLDRVX12 +XBUF<9> A<9> Z<9> VDD VSS / RSC_IHPSG13_WLDRVX12 +XBUF<8> A<8> Z<8> VDD VSS / RSC_IHPSG13_WLDRVX12 +XBUF<7> A<7> Z<7> VDD VSS / RSC_IHPSG13_WLDRVX12 +XBUF<6> A<6> Z<6> VDD VSS / RSC_IHPSG13_WLDRVX12 +XBUF<5> A<5> Z<5> VDD VSS / RSC_IHPSG13_WLDRVX12 +XBUF<4> A<4> Z<4> VDD VSS / RSC_IHPSG13_WLDRVX12 +XBUF<3> A<3> Z<3> VDD VSS / RSC_IHPSG13_WLDRVX12 +XBUF<2> A<2> Z<2> VDD VSS / RSC_IHPSG13_WLDRVX12 +XBUF<1> A<1> Z<1> VDD VSS / RSC_IHPSG13_WLDRVX12 +XBUF<0> A<0> Z<0> VDD VSS / RSC_IHPSG13_WLDRVX12 +.ENDS +.SUBCKT RM_IHPSG13_1024x32_c2_2P_DEC04 ADDR<3> ADDR<2> ADDR<1> ADDR<0> CS ECLK_H_BOT ++ ECLK_H_TOP ECLK_L_BOT ECLK_L_TOP WL<15> WL<14> WL<13> WL<12> WL<11> WL<10> ++ WL<9> WL<8> WL<7> WL<6> WL<5> WL<4> WL<3> WL<2> WL<1> WL<0> VDD VSS +XI0<3> PADR<1> PADR<0> sel01<3> VDD VSS / RSC_IHPSG13_NAND2X2 +XI0<2> PADR<1> NADR<0> sel01<2> VDD VSS / RSC_IHPSG13_NAND2X2 +XI0<1> NADR<1> PADR<0> sel01<1> VDD VSS / RSC_IHPSG13_NAND2X2 +XI0<0> NADR<1> NADR<0> sel01<0> VDD VSS / RSC_IHPSG13_NAND2X2 +XI4 ECLK_L_BOT EN VDD VSS / RSC_IHPSG13_CINVX4 +XI5 ECLK_H_BOT ECLK_L_BOT VDD VSS / RSC_IHPSG13_CINVX2 +XI3<3> PADR<3> NADR<3> VDD VSS / RSC_IHPSG13_INVX2 +XI3<2> PADR<2> NADR<2> VDD VSS / RSC_IHPSG13_INVX2 +XI3<1> PADR<1> NADR<1> VDD VSS / RSC_IHPSG13_INVX2 +XI3<0> PADR<0> NADR<0> VDD VSS / RSC_IHPSG13_INVX2 +XR0 ECLK_H_BOT ECLK_H_TOP / RSC_IHPSG13_MET2RES +XI11 ECLK_L_BOT ECLK_L_TOP / RSC_IHPSG13_MET2RES +XI1<3> PADR<2> PADR<3> CS sel23<3> VDD VSS / RSC_IHPSG13_NAND3X2 +XI1<2> NADR<2> PADR<3> CS sel23<2> VDD VSS / RSC_IHPSG13_NAND3X2 +XI1<1> PADR<2> NADR<3> CS sel23<1> VDD VSS / RSC_IHPSG13_NAND3X2 +XI1<0> NADR<2> NADR<3> CS sel23<0> VDD VSS / RSC_IHPSG13_NAND3X2 +XI2<15> sel23<3> sel01<3> EN WL<15> VDD VSS / RSC_IHPSG13_NOR3X2 +XI2<14> sel23<3> sel01<2> EN WL<14> VDD VSS / RSC_IHPSG13_NOR3X2 +XI2<13> sel23<3> sel01<1> EN WL<13> VDD VSS / RSC_IHPSG13_NOR3X2 +XI2<12> sel23<3> sel01<0> EN WL<12> VDD VSS / RSC_IHPSG13_NOR3X2 +XI2<11> sel23<2> sel01<3> EN WL<11> VDD VSS / RSC_IHPSG13_NOR3X2 +XI2<10> sel23<2> sel01<2> EN WL<10> VDD VSS / RSC_IHPSG13_NOR3X2 +XI2<9> sel23<2> sel01<1> EN WL<9> VDD VSS / RSC_IHPSG13_NOR3X2 +XI2<8> sel23<2> sel01<0> EN WL<8> VDD VSS / RSC_IHPSG13_NOR3X2 +XI2<7> sel23<1> sel01<3> EN WL<7> VDD VSS / RSC_IHPSG13_NOR3X2 +XI2<6> sel23<1> sel01<2> EN WL<6> VDD VSS / RSC_IHPSG13_NOR3X2 +XI2<5> sel23<1> sel01<1> EN WL<5> VDD VSS / RSC_IHPSG13_NOR3X2 +XI2<4> sel23<1> sel01<0> EN WL<4> VDD VSS / RSC_IHPSG13_NOR3X2 +XI2<3> sel23<0> sel01<3> EN WL<3> VDD VSS / RSC_IHPSG13_NOR3X2 +XI2<2> sel23<0> sel01<2> EN WL<2> VDD VSS / RSC_IHPSG13_NOR3X2 +XI2<1> sel23<0> sel01<1> EN WL<1> VDD VSS / RSC_IHPSG13_NOR3X2 +XI2<0> sel23<0> sel01<0> EN WL<0> VDD VSS / RSC_IHPSG13_NOR3X2 +XCAPS4 VDD VSS / RSC_IHPSG13_FILLCAP4 +XLATCH<3> CS ADDR<3> PADR<3> VDD VSS / RSC_IHPSG13_LHPQX2 +XLATCH<2> CS ADDR<2> PADR<2> VDD VSS / RSC_IHPSG13_LHPQX2 +XLATCH<1> CS ADDR<1> PADR<1> VDD VSS / RSC_IHPSG13_LHPQX2 +XLATCH<0> CS ADDR<0> PADR<0> VDD VSS / RSC_IHPSG13_LHPQX2 +.ENDS +.SUBCKT RM_IHPSG13_1024x32_c2_2P_DEC02 ADDR<1> ADDR<0> CS CS_OUT VDD VSS +XDEC ADDR<1> NADDR<0> CS net1 VDD VSS / RSC_IHPSG13_NAND3X2 +XADDRINV ADDR<0> NADDR<0> VDD VSS / RSC_IHPSG13_INVX2 +XDECINV net1 CS_OUT VDD VSS / RSC_IHPSG13_INVX4 +XI2<1> VDD VSS / RSC_IHPSG13_FILLCAP4 +XI2<0> VDD VSS / RSC_IHPSG13_FILLCAP4 +.ENDS +.SUBCKT RM_IHPSG13_1024x32_c2_2P_DEC01 ADDR<1> ADDR<0> CS CS_OUT VDD VSS +XDEC NADDR<1> ADDR<0> CS net1 VDD VSS / RSC_IHPSG13_NAND3X2 +XADDRINV ADDR<1> NADDR<1> VDD VSS / RSC_IHPSG13_INVX2 +XDECINV net1 CS_OUT VDD VSS / RSC_IHPSG13_INVX4 +XI2<1> VDD VSS / RSC_IHPSG13_FILLCAP4 +XI2<0> VDD VSS / RSC_IHPSG13_FILLCAP4 +.ENDS +.SUBCKT RM_IHPSG13_1024x32_c2_2P_DEC00 ADDR<1> ADDR<0> CS CS_OUT VDD VSS +XDEC NADDR<1> NADDR<0> CS net1 VDD VSS / RSC_IHPSG13_NAND3X2 +XADDRINV<1> ADDR<1> NADDR<1> VDD VSS / RSC_IHPSG13_INVX2 +XADDRINV<0> ADDR<0> NADDR<0> VDD VSS / RSC_IHPSG13_INVX2 +XI1<1> VDD VSS / RSC_IHPSG13_FILLCAP4 +XI1<0> VDD VSS / RSC_IHPSG13_FILLCAP4 +XDECINV net1 CS_OUT VDD VSS / RSC_IHPSG13_INVX4 +.ENDS +.SUBCKT RM_IHPSG13_1024x32_c2_2P_DEC03 ADDR<1> ADDR<0> CS CS_OUT VDD VSS +XDEC ADDR<1> ADDR<0> CS net1 VDD VSS / RSC_IHPSG13_NAND3X2 +XDECINV net1 CS_OUT VDD VSS / RSC_IHPSG13_INVX4 +XI0<1> VDD VSS / RSC_IHPSG13_FILLCAP4 +XI0<0> VDD VSS / RSC_IHPSG13_FILLCAP4 +.ENDS +.SUBCKT RM_IHPSG13_1024x32_c2_2P_ROWDEC9 ADDR_N_I<8> ADDR_N_I<7> ADDR_N_I<6> ADDR_N_I<5> ++ ADDR_N_I<4> ADDR_N_I<3> ADDR_N_I<2> ADDR_N_I<1> ADDR_N_I<0> CS_I ECLK_I ++ WL_O<511> WL_O<510> WL_O<509> WL_O<508> WL_O<507> WL_O<506> WL_O<505> ++ WL_O<504> WL_O<503> WL_O<502> WL_O<501> WL_O<500> WL_O<499> WL_O<498> ++ WL_O<497> WL_O<496> WL_O<495> WL_O<494> WL_O<493> WL_O<492> WL_O<491> ++ WL_O<490> WL_O<489> WL_O<488> WL_O<487> WL_O<486> WL_O<485> WL_O<484> ++ WL_O<483> WL_O<482> WL_O<481> WL_O<480> WL_O<479> WL_O<478> WL_O<477> ++ WL_O<476> WL_O<475> WL_O<474> WL_O<473> WL_O<472> WL_O<471> WL_O<470> ++ WL_O<469> WL_O<468> WL_O<467> WL_O<466> WL_O<465> WL_O<464> WL_O<463> ++ WL_O<462> WL_O<461> WL_O<460> WL_O<459> WL_O<458> WL_O<457> WL_O<456> ++ WL_O<455> WL_O<454> WL_O<453> WL_O<452> WL_O<451> WL_O<450> WL_O<449> ++ WL_O<448> WL_O<447> WL_O<446> WL_O<445> WL_O<444> WL_O<443> WL_O<442> ++ WL_O<441> WL_O<440> WL_O<439> WL_O<438> WL_O<437> WL_O<436> WL_O<435> ++ WL_O<434> WL_O<433> WL_O<432> WL_O<431> WL_O<430> WL_O<429> WL_O<428> ++ WL_O<427> WL_O<426> WL_O<425> WL_O<424> WL_O<423> WL_O<422> WL_O<421> ++ WL_O<420> WL_O<419> WL_O<418> WL_O<417> WL_O<416> WL_O<415> WL_O<414> ++ WL_O<413> WL_O<412> WL_O<411> WL_O<410> WL_O<409> WL_O<408> WL_O<407> ++ WL_O<406> WL_O<405> WL_O<404> WL_O<403> WL_O<402> WL_O<401> WL_O<400> ++ WL_O<399> WL_O<398> WL_O<397> WL_O<396> WL_O<395> WL_O<394> WL_O<393> ++ WL_O<392> WL_O<391> WL_O<390> WL_O<389> WL_O<388> WL_O<387> WL_O<386> ++ WL_O<385> WL_O<384> WL_O<383> WL_O<382> WL_O<381> WL_O<380> WL_O<379> ++ WL_O<378> WL_O<377> WL_O<376> WL_O<375> WL_O<374> WL_O<373> WL_O<372> ++ WL_O<371> WL_O<370> WL_O<369> WL_O<368> WL_O<367> WL_O<366> WL_O<365> ++ WL_O<364> WL_O<363> WL_O<362> WL_O<361> WL_O<360> WL_O<359> WL_O<358> ++ WL_O<357> WL_O<356> WL_O<355> WL_O<354> WL_O<353> WL_O<352> WL_O<351> ++ WL_O<350> WL_O<349> WL_O<348> WL_O<347> WL_O<346> WL_O<345> WL_O<344> ++ WL_O<343> WL_O<342> WL_O<341> WL_O<340> WL_O<339> WL_O<338> WL_O<337> ++ WL_O<336> WL_O<335> WL_O<334> WL_O<333> WL_O<332> WL_O<331> WL_O<330> ++ WL_O<329> WL_O<328> WL_O<327> WL_O<326> WL_O<325> WL_O<324> WL_O<323> ++ WL_O<322> WL_O<321> WL_O<320> WL_O<319> WL_O<318> WL_O<317> WL_O<316> ++ WL_O<315> WL_O<314> WL_O<313> WL_O<312> WL_O<311> WL_O<310> WL_O<309> ++ WL_O<308> WL_O<307> WL_O<306> WL_O<305> WL_O<304> WL_O<303> WL_O<302> ++ WL_O<301> WL_O<300> WL_O<299> WL_O<298> WL_O<297> WL_O<296> WL_O<295> ++ WL_O<294> WL_O<293> WL_O<292> WL_O<291> WL_O<290> WL_O<289> WL_O<288> ++ WL_O<287> WL_O<286> WL_O<285> WL_O<284> WL_O<283> WL_O<282> WL_O<281> ++ WL_O<280> WL_O<279> WL_O<278> WL_O<277> WL_O<276> WL_O<275> WL_O<274> ++ WL_O<273> WL_O<272> WL_O<271> WL_O<270> WL_O<269> WL_O<268> WL_O<267> ++ WL_O<266> WL_O<265> WL_O<264> WL_O<263> WL_O<262> WL_O<261> WL_O<260> ++ WL_O<259> WL_O<258> WL_O<257> WL_O<256> WL_O<255> WL_O<254> WL_O<253> ++ WL_O<252> WL_O<251> WL_O<250> WL_O<249> WL_O<248> WL_O<247> WL_O<246> ++ WL_O<245> WL_O<244> WL_O<243> WL_O<242> WL_O<241> WL_O<240> WL_O<239> ++ WL_O<238> WL_O<237> WL_O<236> WL_O<235> WL_O<234> WL_O<233> WL_O<232> ++ WL_O<231> WL_O<230> WL_O<229> WL_O<228> WL_O<227> WL_O<226> WL_O<225> ++ WL_O<224> WL_O<223> WL_O<222> WL_O<221> WL_O<220> WL_O<219> WL_O<218> ++ WL_O<217> WL_O<216> WL_O<215> WL_O<214> WL_O<213> WL_O<212> WL_O<211> ++ WL_O<210> WL_O<209> WL_O<208> WL_O<207> WL_O<206> WL_O<205> WL_O<204> ++ WL_O<203> WL_O<202> WL_O<201> WL_O<200> WL_O<199> WL_O<198> WL_O<197> ++ WL_O<196> WL_O<195> WL_O<194> WL_O<193> WL_O<192> WL_O<191> WL_O<190> ++ WL_O<189> WL_O<188> WL_O<187> WL_O<186> WL_O<185> WL_O<184> WL_O<183> ++ WL_O<182> WL_O<181> WL_O<180> WL_O<179> WL_O<178> WL_O<177> WL_O<176> ++ WL_O<175> WL_O<174> WL_O<173> WL_O<172> WL_O<171> WL_O<170> WL_O<169> ++ WL_O<168> WL_O<167> WL_O<166> WL_O<165> WL_O<164> WL_O<163> WL_O<162> ++ WL_O<161> WL_O<160> WL_O<159> WL_O<158> WL_O<157> WL_O<156> WL_O<155> ++ WL_O<154> WL_O<153> WL_O<152> WL_O<151> WL_O<150> WL_O<149> WL_O<148> ++ WL_O<147> WL_O<146> WL_O<145> WL_O<144> WL_O<143> WL_O<142> WL_O<141> ++ WL_O<140> WL_O<139> WL_O<138> WL_O<137> WL_O<136> WL_O<135> WL_O<134> ++ WL_O<133> WL_O<132> WL_O<131> WL_O<130> WL_O<129> WL_O<128> WL_O<127> ++ WL_O<126> WL_O<125> WL_O<124> WL_O<123> WL_O<122> WL_O<121> WL_O<120> ++ WL_O<119> WL_O<118> WL_O<117> WL_O<116> WL_O<115> WL_O<114> WL_O<113> ++ WL_O<112> WL_O<111> WL_O<110> WL_O<109> WL_O<108> WL_O<107> WL_O<106> ++ WL_O<105> WL_O<104> WL_O<103> WL_O<102> WL_O<101> WL_O<100> WL_O<99> ++ WL_O<98> WL_O<97> WL_O<96> WL_O<95> WL_O<94> WL_O<93> WL_O<92> WL_O<91> ++ WL_O<90> WL_O<89> WL_O<88> WL_O<87> WL_O<86> WL_O<85> WL_O<84> WL_O<83> ++ WL_O<82> WL_O<81> WL_O<80> WL_O<79> WL_O<78> WL_O<77> WL_O<76> WL_O<75> ++ WL_O<74> WL_O<73> WL_O<72> WL_O<71> WL_O<70> WL_O<69> WL_O<68> WL_O<67> ++ WL_O<66> WL_O<65> WL_O<64> WL_O<63> WL_O<62> WL_O<61> WL_O<60> WL_O<59> ++ WL_O<58> WL_O<57> WL_O<56> WL_O<55> WL_O<54> WL_O<53> WL_O<52> WL_O<51> ++ WL_O<50> WL_O<49> WL_O<48> WL_O<47> WL_O<46> WL_O<45> WL_O<44> WL_O<43> ++ WL_O<42> WL_O<41> WL_O<40> WL_O<39> WL_O<38> WL_O<37> WL_O<36> WL_O<35> ++ WL_O<34> WL_O<33> WL_O<32> WL_O<31> WL_O<30> WL_O<29> WL_O<28> WL_O<27> ++ WL_O<26> WL_O<25> WL_O<24> WL_O<23> WL_O<22> WL_O<21> WL_O<20> WL_O<19> ++ WL_O<18> WL_O<17> WL_O<16> WL_O<15> WL_O<14> WL_O<13> WL_O<12> WL_O<11> ++ WL_O<10> WL_O<9> WL_O<8> WL_O<7> WL_O<6> WL_O<5> WL_O<4> WL_O<3> WL_O<2> ++ WL_O<1> WL_O<0> VDD VSS +XSEL<31> ADDR_N_I<3> ADDR_N_I<2> ADDR_N_I<1> ADDR_N_I<0> CS00<31> ECLK_H<31> ++ ECLK_H<32> ECLK_B<31> ECLK_B<32> WL_O<511> WL_O<510> WL_O<509> WL_O<508> ++ WL_O<507> WL_O<506> WL_O<505> WL_O<504> WL_O<503> WL_O<502> WL_O<501> ++ WL_O<500> WL_O<499> WL_O<498> WL_O<497> WL_O<496> VDD VSS / ++ RM_IHPSG13_1024x32_c2_2P_DEC04 +XSEL<30> ADDR_N_I<3> ADDR_N_I<2> ADDR_N_I<1> ADDR_N_I<0> CS00<30> ECLK_H<30> ++ ECLK_H<31> ECLK_B<30> ECLK_B<31> WL_O<495> WL_O<494> WL_O<493> WL_O<492> ++ WL_O<491> WL_O<490> WL_O<489> WL_O<488> WL_O<487> WL_O<486> WL_O<485> ++ WL_O<484> WL_O<483> WL_O<482> WL_O<481> WL_O<480> VDD VSS / ++ RM_IHPSG13_1024x32_c2_2P_DEC04 +XSEL<29> ADDR_N_I<3> ADDR_N_I<2> ADDR_N_I<1> ADDR_N_I<0> CS00<29> ECLK_H<29> ++ ECLK_H<30> ECLK_B<29> ECLK_B<30> WL_O<479> WL_O<478> WL_O<477> WL_O<476> ++ WL_O<475> WL_O<474> WL_O<473> WL_O<472> WL_O<471> WL_O<470> WL_O<469> ++ WL_O<468> WL_O<467> WL_O<466> WL_O<465> WL_O<464> VDD VSS / ++ RM_IHPSG13_1024x32_c2_2P_DEC04 +XSEL<28> ADDR_N_I<3> ADDR_N_I<2> ADDR_N_I<1> ADDR_N_I<0> CS00<28> ECLK_H<28> ++ ECLK_H<29> ECLK_B<28> ECLK_B<29> WL_O<463> WL_O<462> WL_O<461> WL_O<460> ++ WL_O<459> WL_O<458> WL_O<457> WL_O<456> WL_O<455> WL_O<454> WL_O<453> ++ WL_O<452> WL_O<451> WL_O<450> WL_O<449> WL_O<448> VDD VSS / ++ RM_IHPSG13_1024x32_c2_2P_DEC04 +XSEL<27> ADDR_N_I<3> ADDR_N_I<2> ADDR_N_I<1> ADDR_N_I<0> CS00<27> ECLK_H<27> ++ ECLK_H<28> ECLK_B<27> ECLK_B<28> WL_O<447> WL_O<446> WL_O<445> WL_O<444> ++ WL_O<443> WL_O<442> WL_O<441> WL_O<440> WL_O<439> WL_O<438> WL_O<437> ++ WL_O<436> WL_O<435> WL_O<434> WL_O<433> WL_O<432> VDD VSS / ++ RM_IHPSG13_1024x32_c2_2P_DEC04 +XSEL<26> ADDR_N_I<3> ADDR_N_I<2> ADDR_N_I<1> ADDR_N_I<0> CS00<26> ECLK_H<26> ++ ECLK_H<27> ECLK_B<26> ECLK_B<27> WL_O<431> WL_O<430> WL_O<429> WL_O<428> ++ WL_O<427> WL_O<426> WL_O<425> WL_O<424> WL_O<423> WL_O<422> WL_O<421> ++ WL_O<420> WL_O<419> WL_O<418> WL_O<417> WL_O<416> VDD VSS / ++ RM_IHPSG13_1024x32_c2_2P_DEC04 +XSEL<25> ADDR_N_I<3> ADDR_N_I<2> ADDR_N_I<1> ADDR_N_I<0> CS00<25> ECLK_H<25> ++ ECLK_H<26> ECLK_B<25> ECLK_B<26> WL_O<415> WL_O<414> WL_O<413> WL_O<412> ++ WL_O<411> WL_O<410> WL_O<409> WL_O<408> WL_O<407> WL_O<406> WL_O<405> ++ WL_O<404> WL_O<403> WL_O<402> WL_O<401> WL_O<400> VDD VSS / ++ RM_IHPSG13_1024x32_c2_2P_DEC04 +XSEL<24> ADDR_N_I<3> ADDR_N_I<2> ADDR_N_I<1> ADDR_N_I<0> CS00<24> ECLK_H<24> ++ ECLK_H<25> ECLK_B<24> ECLK_B<25> WL_O<399> WL_O<398> WL_O<397> WL_O<396> ++ WL_O<395> WL_O<394> WL_O<393> WL_O<392> WL_O<391> WL_O<390> WL_O<389> ++ WL_O<388> WL_O<387> WL_O<386> WL_O<385> WL_O<384> VDD VSS / ++ RM_IHPSG13_1024x32_c2_2P_DEC04 +XSEL<23> ADDR_N_I<3> ADDR_N_I<2> ADDR_N_I<1> ADDR_N_I<0> CS00<23> ECLK_H<23> ++ ECLK_H<24> ECLK_B<23> ECLK_B<24> WL_O<383> WL_O<382> WL_O<381> WL_O<380> ++ WL_O<379> WL_O<378> WL_O<377> WL_O<376> WL_O<375> WL_O<374> WL_O<373> ++ WL_O<372> WL_O<371> WL_O<370> WL_O<369> WL_O<368> VDD VSS / ++ RM_IHPSG13_1024x32_c2_2P_DEC04 +XSEL<22> ADDR_N_I<3> ADDR_N_I<2> ADDR_N_I<1> ADDR_N_I<0> CS00<22> ECLK_H<22> ++ ECLK_H<23> ECLK_B<22> ECLK_B<23> WL_O<367> WL_O<366> WL_O<365> WL_O<364> ++ WL_O<363> WL_O<362> WL_O<361> WL_O<360> WL_O<359> WL_O<358> WL_O<357> ++ WL_O<356> WL_O<355> WL_O<354> WL_O<353> WL_O<352> VDD VSS / ++ RM_IHPSG13_1024x32_c2_2P_DEC04 +XSEL<21> ADDR_N_I<3> ADDR_N_I<2> ADDR_N_I<1> ADDR_N_I<0> CS00<21> ECLK_H<21> ++ ECLK_H<22> ECLK_B<21> ECLK_B<22> WL_O<351> WL_O<350> WL_O<349> WL_O<348> ++ WL_O<347> WL_O<346> WL_O<345> WL_O<344> WL_O<343> WL_O<342> WL_O<341> ++ WL_O<340> WL_O<339> WL_O<338> WL_O<337> WL_O<336> VDD VSS / ++ RM_IHPSG13_1024x32_c2_2P_DEC04 +XSEL<20> ADDR_N_I<3> ADDR_N_I<2> ADDR_N_I<1> ADDR_N_I<0> CS00<20> ECLK_H<20> ++ ECLK_H<21> ECLK_B<20> ECLK_B<21> WL_O<335> WL_O<334> WL_O<333> WL_O<332> ++ WL_O<331> WL_O<330> WL_O<329> WL_O<328> WL_O<327> WL_O<326> WL_O<325> ++ WL_O<324> WL_O<323> WL_O<322> WL_O<321> WL_O<320> VDD VSS / ++ RM_IHPSG13_1024x32_c2_2P_DEC04 +XSEL<19> ADDR_N_I<3> ADDR_N_I<2> ADDR_N_I<1> ADDR_N_I<0> CS00<19> ECLK_H<19> ++ ECLK_H<20> ECLK_B<19> ECLK_B<20> WL_O<319> WL_O<318> WL_O<317> WL_O<316> ++ WL_O<315> WL_O<314> WL_O<313> WL_O<312> WL_O<311> WL_O<310> WL_O<309> ++ WL_O<308> WL_O<307> WL_O<306> WL_O<305> WL_O<304> VDD VSS / ++ RM_IHPSG13_1024x32_c2_2P_DEC04 +XSEL<18> ADDR_N_I<3> ADDR_N_I<2> ADDR_N_I<1> ADDR_N_I<0> CS00<18> ECLK_H<18> ++ ECLK_H<19> ECLK_B<18> ECLK_B<19> WL_O<303> WL_O<302> WL_O<301> WL_O<300> ++ WL_O<299> WL_O<298> WL_O<297> WL_O<296> WL_O<295> WL_O<294> WL_O<293> ++ WL_O<292> WL_O<291> WL_O<290> WL_O<289> WL_O<288> VDD VSS / ++ RM_IHPSG13_1024x32_c2_2P_DEC04 +XSEL<17> ADDR_N_I<3> ADDR_N_I<2> ADDR_N_I<1> ADDR_N_I<0> CS00<17> ECLK_H<17> ++ ECLK_H<18> ECLK_B<17> ECLK_B<18> WL_O<287> WL_O<286> WL_O<285> WL_O<284> ++ WL_O<283> WL_O<282> WL_O<281> WL_O<280> WL_O<279> WL_O<278> WL_O<277> ++ WL_O<276> WL_O<275> WL_O<274> WL_O<273> WL_O<272> VDD VSS / ++ RM_IHPSG13_1024x32_c2_2P_DEC04 +XSEL<16> ADDR_N_I<3> ADDR_N_I<2> ADDR_N_I<1> ADDR_N_I<0> CS00<16> ECLK_H<16> ++ ECLK_H<17> ECLK_B<16> ECLK_B<17> WL_O<271> WL_O<270> WL_O<269> WL_O<268> ++ WL_O<267> WL_O<266> WL_O<265> WL_O<264> WL_O<263> WL_O<262> WL_O<261> ++ WL_O<260> WL_O<259> WL_O<258> WL_O<257> WL_O<256> VDD VSS / ++ RM_IHPSG13_1024x32_c2_2P_DEC04 +XSEL<15> ADDR_N_I<3> ADDR_N_I<2> ADDR_N_I<1> ADDR_N_I<0> CS00<15> ECLK_H<15> ++ ECLK_H<16> ECLK_B<15> ECLK_B<16> WL_O<255> WL_O<254> WL_O<253> WL_O<252> ++ WL_O<251> WL_O<250> WL_O<249> WL_O<248> WL_O<247> WL_O<246> WL_O<245> ++ WL_O<244> WL_O<243> WL_O<242> WL_O<241> WL_O<240> VDD VSS / ++ RM_IHPSG13_1024x32_c2_2P_DEC04 +XSEL<14> ADDR_N_I<3> ADDR_N_I<2> ADDR_N_I<1> ADDR_N_I<0> CS00<14> ECLK_H<14> ++ ECLK_H<15> ECLK_B<14> ECLK_B<15> WL_O<239> WL_O<238> WL_O<237> WL_O<236> ++ WL_O<235> WL_O<234> WL_O<233> WL_O<232> WL_O<231> WL_O<230> WL_O<229> ++ WL_O<228> WL_O<227> WL_O<226> WL_O<225> WL_O<224> VDD VSS / ++ RM_IHPSG13_1024x32_c2_2P_DEC04 +XSEL<13> ADDR_N_I<3> ADDR_N_I<2> ADDR_N_I<1> ADDR_N_I<0> CS00<13> ECLK_H<13> ++ ECLK_H<14> ECLK_B<13> ECLK_B<14> WL_O<223> WL_O<222> WL_O<221> WL_O<220> ++ WL_O<219> WL_O<218> WL_O<217> WL_O<216> WL_O<215> WL_O<214> WL_O<213> ++ WL_O<212> WL_O<211> WL_O<210> WL_O<209> WL_O<208> VDD VSS / ++ RM_IHPSG13_1024x32_c2_2P_DEC04 +XSEL<12> ADDR_N_I<3> ADDR_N_I<2> ADDR_N_I<1> ADDR_N_I<0> CS00<12> ECLK_H<12> ++ ECLK_H<13> ECLK_B<12> ECLK_B<13> WL_O<207> WL_O<206> WL_O<205> WL_O<204> ++ WL_O<203> WL_O<202> WL_O<201> WL_O<200> WL_O<199> WL_O<198> WL_O<197> ++ WL_O<196> WL_O<195> WL_O<194> WL_O<193> WL_O<192> VDD VSS / ++ RM_IHPSG13_1024x32_c2_2P_DEC04 +XSEL<11> ADDR_N_I<3> ADDR_N_I<2> ADDR_N_I<1> ADDR_N_I<0> CS00<11> ECLK_H<11> ++ ECLK_H<12> ECLK_B<11> ECLK_B<12> WL_O<191> WL_O<190> WL_O<189> WL_O<188> ++ WL_O<187> WL_O<186> WL_O<185> WL_O<184> WL_O<183> WL_O<182> WL_O<181> ++ WL_O<180> WL_O<179> WL_O<178> WL_O<177> WL_O<176> VDD VSS / ++ RM_IHPSG13_1024x32_c2_2P_DEC04 +XSEL<10> ADDR_N_I<3> ADDR_N_I<2> ADDR_N_I<1> ADDR_N_I<0> CS00<10> ECLK_H<10> ++ ECLK_H<11> ECLK_B<10> ECLK_B<11> WL_O<175> WL_O<174> WL_O<173> WL_O<172> ++ WL_O<171> WL_O<170> WL_O<169> WL_O<168> WL_O<167> WL_O<166> WL_O<165> ++ WL_O<164> WL_O<163> WL_O<162> WL_O<161> WL_O<160> VDD VSS / ++ RM_IHPSG13_1024x32_c2_2P_DEC04 +XSEL<9> ADDR_N_I<3> ADDR_N_I<2> ADDR_N_I<1> ADDR_N_I<0> CS00<9> ECLK_H<9> ++ ECLK_H<10> ECLK_B<9> ECLK_B<10> WL_O<159> WL_O<158> WL_O<157> WL_O<156> ++ WL_O<155> WL_O<154> WL_O<153> WL_O<152> WL_O<151> WL_O<150> WL_O<149> ++ WL_O<148> WL_O<147> WL_O<146> WL_O<145> WL_O<144> VDD VSS / ++ RM_IHPSG13_1024x32_c2_2P_DEC04 +XSEL<8> ADDR_N_I<3> ADDR_N_I<2> ADDR_N_I<1> ADDR_N_I<0> CS00<8> ECLK_H<8> ++ ECLK_H<9> ECLK_B<8> ECLK_B<9> WL_O<143> WL_O<142> WL_O<141> WL_O<140> ++ WL_O<139> WL_O<138> WL_O<137> WL_O<136> WL_O<135> WL_O<134> WL_O<133> ++ WL_O<132> WL_O<131> WL_O<130> WL_O<129> WL_O<128> VDD VSS / ++ RM_IHPSG13_1024x32_c2_2P_DEC04 +XSEL<7> ADDR_N_I<3> ADDR_N_I<2> ADDR_N_I<1> ADDR_N_I<0> CS00<7> ECLK_H<7> ++ ECLK_H<8> ECLK_B<7> ECLK_B<8> WL_O<127> WL_O<126> WL_O<125> WL_O<124> ++ WL_O<123> WL_O<122> WL_O<121> WL_O<120> WL_O<119> WL_O<118> WL_O<117> ++ WL_O<116> WL_O<115> WL_O<114> WL_O<113> WL_O<112> VDD VSS / ++ RM_IHPSG13_1024x32_c2_2P_DEC04 +XSEL<6> ADDR_N_I<3> ADDR_N_I<2> ADDR_N_I<1> ADDR_N_I<0> CS00<6> ECLK_H<6> ++ ECLK_H<7> ECLK_B<6> ECLK_B<7> WL_O<111> WL_O<110> WL_O<109> WL_O<108> ++ WL_O<107> WL_O<106> WL_O<105> WL_O<104> WL_O<103> WL_O<102> WL_O<101> ++ WL_O<100> WL_O<99> WL_O<98> WL_O<97> WL_O<96> VDD VSS / ++ RM_IHPSG13_1024x32_c2_2P_DEC04 +XSEL<5> ADDR_N_I<3> ADDR_N_I<2> ADDR_N_I<1> ADDR_N_I<0> CS00<5> ECLK_H<5> ++ ECLK_H<6> ECLK_B<5> ECLK_B<6> WL_O<95> WL_O<94> WL_O<93> WL_O<92> WL_O<91> ++ WL_O<90> WL_O<89> WL_O<88> WL_O<87> WL_O<86> WL_O<85> WL_O<84> WL_O<83> ++ WL_O<82> WL_O<81> WL_O<80> VDD VSS / RM_IHPSG13_1024x32_c2_2P_DEC04 +XSEL<4> ADDR_N_I<3> ADDR_N_I<2> ADDR_N_I<1> ADDR_N_I<0> CS00<4> ECLK_H<4> ++ ECLK_H<5> ECLK_B<4> ECLK_B<5> WL_O<79> WL_O<78> WL_O<77> WL_O<76> WL_O<75> ++ WL_O<74> WL_O<73> WL_O<72> WL_O<71> WL_O<70> WL_O<69> WL_O<68> WL_O<67> ++ WL_O<66> WL_O<65> WL_O<64> VDD VSS / RM_IHPSG13_1024x32_c2_2P_DEC04 +XSEL<3> ADDR_N_I<3> ADDR_N_I<2> ADDR_N_I<1> ADDR_N_I<0> CS00<3> ECLK_H<3> ++ ECLK_H<4> ECLK_B<3> ECLK_B<4> WL_O<63> WL_O<62> WL_O<61> WL_O<60> WL_O<59> ++ WL_O<58> WL_O<57> WL_O<56> WL_O<55> WL_O<54> WL_O<53> WL_O<52> WL_O<51> ++ WL_O<50> WL_O<49> WL_O<48> VDD VSS / RM_IHPSG13_1024x32_c2_2P_DEC04 +XSEL<2> ADDR_N_I<3> ADDR_N_I<2> ADDR_N_I<1> ADDR_N_I<0> CS00<2> ECLK_H<2> ++ ECLK_H<3> ECLK_B<2> ECLK_B<3> WL_O<47> WL_O<46> WL_O<45> WL_O<44> WL_O<43> ++ WL_O<42> WL_O<41> WL_O<40> WL_O<39> WL_O<38> WL_O<37> WL_O<36> WL_O<35> ++ WL_O<34> WL_O<33> WL_O<32> VDD VSS / RM_IHPSG13_1024x32_c2_2P_DEC04 +XSEL<1> ADDR_N_I<3> ADDR_N_I<2> ADDR_N_I<1> ADDR_N_I<0> CS00<1> ECLK_H<1> ++ ECLK_H<2> ECLK_B<1> ECLK_B<2> WL_O<31> WL_O<30> WL_O<29> WL_O<28> WL_O<27> ++ WL_O<26> WL_O<25> WL_O<24> WL_O<23> WL_O<22> WL_O<21> WL_O<20> WL_O<19> ++ WL_O<18> WL_O<17> WL_O<16> VDD VSS / RM_IHPSG13_1024x32_c2_2P_DEC04 +XSEL<0> ADDR_N_I<3> ADDR_N_I<2> ADDR_N_I<1> ADDR_N_I<0> CS00<0> ECLK_I ++ ECLK_H<1> ECLK_B<0> ECLK_B<1> WL_O<15> WL_O<14> WL_O<13> WL_O<12> WL_O<11> ++ WL_O<10> WL_O<9> WL_O<8> WL_O<7> WL_O<6> WL_O<5> WL_O<4> WL_O<3> WL_O<2> ++ WL_O<1> WL_O<0> VDD VSS / RM_IHPSG13_1024x32_c2_2P_DEC04 +XDEC10<9> ADDR_N_I<7> ADDR_N_I<6> CS04<1> CS02<6> VDD VSS / ++ RM_IHPSG13_1024x32_c2_2P_DEC02 +XDEC10<8> ADDR_N_I<7> ADDR_N_I<6> CS04<0> CS02<2> VDD VSS / ++ RM_IHPSG13_1024x32_c2_2P_DEC02 +XDEC10<7> ADDR_N_I<5> ADDR_N_I<4> CS02<7> CS00<30> VDD VSS / ++ RM_IHPSG13_1024x32_c2_2P_DEC02 +XDEC10<6> ADDR_N_I<5> ADDR_N_I<4> CS02<6> CS00<26> VDD VSS / ++ RM_IHPSG13_1024x32_c2_2P_DEC02 +XDEC10<5> ADDR_N_I<5> ADDR_N_I<4> CS02<5> CS00<22> VDD VSS / ++ RM_IHPSG13_1024x32_c2_2P_DEC02 +XDEC10<4> ADDR_N_I<5> ADDR_N_I<4> CS02<4> CS00<18> VDD VSS / ++ RM_IHPSG13_1024x32_c2_2P_DEC02 +XDEC10<3> ADDR_N_I<5> ADDR_N_I<4> CS02<3> CS00<14> VDD VSS / ++ RM_IHPSG13_1024x32_c2_2P_DEC02 +XDEC10<2> ADDR_N_I<5> ADDR_N_I<4> CS02<2> CS00<10> VDD VSS / ++ RM_IHPSG13_1024x32_c2_2P_DEC02 +XDEC10<1> ADDR_N_I<5> ADDR_N_I<4> CS02<1> CS00<6> VDD VSS / ++ RM_IHPSG13_1024x32_c2_2P_DEC02 +XDEC10<0> ADDR_N_I<5> ADDR_N_I<4> CS02<0> CS00<2> VDD VSS / ++ RM_IHPSG13_1024x32_c2_2P_DEC02 +XDEC01<10> ADDR_N_I<9> ADDR_N_I<8> CS_I CS04<1> VDD VSS / ++ RM_IHPSG13_1024x32_c2_2P_DEC01 +XDEC01<9> ADDR_N_I<7> ADDR_N_I<6> CS04<1> CS02<5> VDD VSS / ++ RM_IHPSG13_1024x32_c2_2P_DEC01 +XDEC01<8> ADDR_N_I<7> ADDR_N_I<6> CS04<0> CS02<1> VDD VSS / ++ RM_IHPSG13_1024x32_c2_2P_DEC01 +XDEC01<7> ADDR_N_I<5> ADDR_N_I<4> CS02<7> CS00<29> VDD VSS / ++ RM_IHPSG13_1024x32_c2_2P_DEC01 +XDEC01<6> ADDR_N_I<5> ADDR_N_I<4> CS02<6> CS00<25> VDD VSS / ++ RM_IHPSG13_1024x32_c2_2P_DEC01 +XDEC01<5> ADDR_N_I<5> ADDR_N_I<4> CS02<5> CS00<21> VDD VSS / ++ RM_IHPSG13_1024x32_c2_2P_DEC01 +XDEC01<4> ADDR_N_I<5> ADDR_N_I<4> CS02<4> CS00<17> VDD VSS / ++ RM_IHPSG13_1024x32_c2_2P_DEC01 +XDEC01<3> ADDR_N_I<5> ADDR_N_I<4> CS02<3> CS00<13> VDD VSS / ++ RM_IHPSG13_1024x32_c2_2P_DEC01 +XDEC01<2> ADDR_N_I<5> ADDR_N_I<4> CS02<2> CS00<9> VDD VSS / ++ RM_IHPSG13_1024x32_c2_2P_DEC01 +XDEC01<1> ADDR_N_I<5> ADDR_N_I<4> CS02<1> CS00<5> VDD VSS / ++ RM_IHPSG13_1024x32_c2_2P_DEC01 +XDEC01<0> ADDR_N_I<5> ADDR_N_I<4> CS02<0> CS00<1> VDD VSS / ++ RM_IHPSG13_1024x32_c2_2P_DEC01 +XL2<258> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<257> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<256> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<255> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<254> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<253> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<252> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<251> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<250> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<249> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<248> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<247> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<246> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<245> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<244> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<243> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<242> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<241> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<240> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<239> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<238> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<237> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<236> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<235> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<234> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<233> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<232> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<231> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<230> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<229> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<228> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<227> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<226> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<225> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<224> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<223> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<222> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<221> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<220> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<219> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<218> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<217> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<216> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<215> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<214> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<213> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<212> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<211> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<210> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<209> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<208> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<207> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<206> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<205> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<204> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<203> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<202> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<201> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<200> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<199> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<198> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<197> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<196> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<195> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<194> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<193> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<192> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<191> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<190> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<189> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<188> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<187> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<186> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<185> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<184> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<183> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<182> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<181> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<180> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<179> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<178> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<177> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<176> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<175> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<174> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<173> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<172> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<171> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<170> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<169> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<168> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<167> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<166> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<165> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<164> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<163> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<162> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<161> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<160> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<159> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<158> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<157> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<156> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<155> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<154> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<153> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<152> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<151> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<150> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<149> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<148> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<147> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<146> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<145> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<144> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<143> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<142> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<141> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<140> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<139> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<138> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<137> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<136> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<135> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<134> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<133> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<132> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<131> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<130> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<129> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<128> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<127> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<126> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<125> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<124> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<123> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<122> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<121> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<120> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<119> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<118> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<117> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<116> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<115> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<114> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<113> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<112> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<111> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<110> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<109> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<108> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<107> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<106> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<105> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<104> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<103> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<102> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<101> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<100> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<99> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<98> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<97> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<96> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<95> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<94> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<93> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<92> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<91> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<90> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<89> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<88> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<87> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<86> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<85> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<84> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<83> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<82> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<81> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<80> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<79> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<78> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<77> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<76> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<75> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<74> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<73> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<72> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<71> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<70> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<69> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<68> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<67> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<66> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<65> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<64> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<63> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<62> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<61> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<60> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<59> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<58> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<57> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<56> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<55> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<54> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<53> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<52> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<51> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<50> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<49> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<48> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<47> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<46> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<45> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<44> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<43> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<42> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<41> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<40> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<39> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<38> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<37> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<36> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<35> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<34> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<33> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<32> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<31> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<30> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<29> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<28> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<27> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<26> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<25> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<24> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<23> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<22> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<21> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<20> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<19> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<18> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<17> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<16> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<15> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<14> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<13> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<12> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<11> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<10> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<9> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<8> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<7> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<6> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<5> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<4> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<3> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<2> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<1> VDD VSS / RSC_IHPSG13_FILLCAP8 +XDEC00<10> ADDR_N_I<9> ADDR_N_I<8> CS_I CS04<0> VDD VSS / ++ RM_IHPSG13_1024x32_c2_2P_DEC00 +XDEC00<9> ADDR_N_I<7> ADDR_N_I<6> CS04<1> CS02<4> VDD VSS / ++ RM_IHPSG13_1024x32_c2_2P_DEC00 +XDEC00<8> ADDR_N_I<7> ADDR_N_I<6> CS04<0> CS02<0> VDD VSS / ++ RM_IHPSG13_1024x32_c2_2P_DEC00 +XDEC00<7> ADDR_N_I<5> ADDR_N_I<4> CS02<7> CS00<28> VDD VSS / ++ RM_IHPSG13_1024x32_c2_2P_DEC00 +XDEC00<6> ADDR_N_I<5> ADDR_N_I<4> CS02<6> CS00<24> VDD VSS / ++ RM_IHPSG13_1024x32_c2_2P_DEC00 +XDEC00<5> ADDR_N_I<5> ADDR_N_I<4> CS02<5> CS00<20> VDD VSS / ++ RM_IHPSG13_1024x32_c2_2P_DEC00 +XDEC00<4> ADDR_N_I<5> ADDR_N_I<4> CS02<4> CS00<16> VDD VSS / ++ RM_IHPSG13_1024x32_c2_2P_DEC00 +XDEC00<3> ADDR_N_I<5> ADDR_N_I<4> CS02<3> CS00<12> VDD VSS / ++ RM_IHPSG13_1024x32_c2_2P_DEC00 +XDEC00<2> ADDR_N_I<5> ADDR_N_I<4> CS02<2> CS00<8> VDD VSS / ++ RM_IHPSG13_1024x32_c2_2P_DEC00 +XDEC00<1> ADDR_N_I<5> ADDR_N_I<4> CS02<1> CS00<4> VDD VSS / ++ RM_IHPSG13_1024x32_c2_2P_DEC00 +XDEC00<0> ADDR_N_I<5> ADDR_N_I<4> CS02<0> CS00<0> VDD VSS / ++ RM_IHPSG13_1024x32_c2_2P_DEC00 +XDEC11<9> ADDR_N_I<7> ADDR_N_I<6> CS04<1> CS02<7> VDD VSS / ++ RM_IHPSG13_1024x32_c2_2P_DEC03 +XDEC11<8> ADDR_N_I<7> ADDR_N_I<6> CS04<0> CS02<3> VDD VSS / ++ RM_IHPSG13_1024x32_c2_2P_DEC03 +XDEC11<7> ADDR_N_I<5> ADDR_N_I<4> CS02<7> CS00<31> VDD VSS / ++ RM_IHPSG13_1024x32_c2_2P_DEC03 +XDEC11<6> ADDR_N_I<5> ADDR_N_I<4> CS02<6> CS00<27> VDD VSS / ++ RM_IHPSG13_1024x32_c2_2P_DEC03 +XDEC11<5> ADDR_N_I<5> ADDR_N_I<4> CS02<5> CS00<23> VDD VSS / ++ RM_IHPSG13_1024x32_c2_2P_DEC03 +XDEC11<4> ADDR_N_I<5> ADDR_N_I<4> CS02<4> CS00<19> VDD VSS / ++ RM_IHPSG13_1024x32_c2_2P_DEC03 +XDEC11<3> ADDR_N_I<5> ADDR_N_I<4> CS02<3> CS00<15> VDD VSS / ++ RM_IHPSG13_1024x32_c2_2P_DEC03 +XDEC11<2> ADDR_N_I<5> ADDR_N_I<4> CS02<2> CS00<11> VDD VSS / ++ RM_IHPSG13_1024x32_c2_2P_DEC03 +XDEC11<1> ADDR_N_I<5> ADDR_N_I<4> CS02<1> CS00<7> VDD VSS / ++ RM_IHPSG13_1024x32_c2_2P_DEC03 +XDEC11<0> ADDR_N_I<5> ADDR_N_I<4> CS02<0> CS00<3> VDD VSS / ++ RM_IHPSG13_1024x32_c2_2P_DEC03 +XI0 ADDR_N_I<9> VDD VSS / RSC_IHPSG13_TIEL +.ENDS +.SUBCKT RM_IHPSG13_1024x32_c2_2P_ROWREG9 ACLK_N_I ADDR_I<8> ADDR_I<7> ADDR_I<6> ADDR_I<5> ++ ADDR_I<4> ADDR_I<3> ADDR_I<2> ADDR_I<1> ADDR_I<0> ADDR_N_O<8> ADDR_N_O<7> ++ ADDR_N_O<6> ADDR_N_O<5> ADDR_N_O<4> ADDR_N_O<3> ADDR_N_O<2> ADDR_N_O<1> ++ ADDR_N_O<0> BIST_ADDR_I<8> BIST_ADDR_I<7> BIST_ADDR_I<6> BIST_ADDR_I<5> ++ BIST_ADDR_I<4> BIST_ADDR_I<3> BIST_ADDR_I<2> BIST_ADDR_I<1> BIST_ADDR_I<0> ++ BIST_EN_I VDD VSS +XDFF<8> BIST_EN_I BIST_ADDR_I<8> ACLK_N_I ADDR_I<8> q_int<8> net04<0> VDD ++ VSS / RSC_IHPSG13_DFNQMX2IX1 +XDFF<7> BIST_EN_I BIST_ADDR_I<7> ACLK_N_I ADDR_I<7> q_int<7> net04<1> VDD ++ VSS / RSC_IHPSG13_DFNQMX2IX1 +XDFF<6> BIST_EN_I BIST_ADDR_I<6> ACLK_N_I ADDR_I<6> q_int<6> net04<2> VDD ++ VSS / RSC_IHPSG13_DFNQMX2IX1 +XDFF<5> BIST_EN_I BIST_ADDR_I<5> ACLK_N_I ADDR_I<5> q_int<5> net04<3> VDD ++ VSS / RSC_IHPSG13_DFNQMX2IX1 +XDFF<4> BIST_EN_I BIST_ADDR_I<4> ACLK_N_I ADDR_I<4> q_int<4> net04<4> VDD ++ VSS / RSC_IHPSG13_DFNQMX2IX1 +XDFF<3> BIST_EN_I BIST_ADDR_I<3> ACLK_N_I ADDR_I<3> q_int<3> net04<5> VDD ++ VSS / RSC_IHPSG13_DFNQMX2IX1 +XDFF<2> BIST_EN_I BIST_ADDR_I<2> ACLK_N_I ADDR_I<2> q_int<2> net04<6> VDD ++ VSS / RSC_IHPSG13_DFNQMX2IX1 +XDFF<1> BIST_EN_I BIST_ADDR_I<1> ACLK_N_I ADDR_I<1> q_int<1> net04<7> VDD ++ VSS / RSC_IHPSG13_DFNQMX2IX1 +XDFF<0> BIST_EN_I BIST_ADDR_I<0> ACLK_N_I ADDR_I<0> q_int<0> net04<8> VDD ++ VSS / RSC_IHPSG13_DFNQMX2IX1 +XDRV<8> qn_int<8> ADDR_N_O<8> VDD VSS / RSC_IHPSG13_CINVX8 +XDRV<7> qn_int<7> ADDR_N_O<7> VDD VSS / RSC_IHPSG13_CINVX8 +XDRV<6> qn_int<6> ADDR_N_O<6> VDD VSS / RSC_IHPSG13_CINVX8 +XDRV<5> qn_int<5> ADDR_N_O<5> VDD VSS / RSC_IHPSG13_CINVX8 +XDRV<4> qn_int<4> ADDR_N_O<4> VDD VSS / RSC_IHPSG13_CINVX8 +XDRV<3> qn_int<3> ADDR_N_O<3> VDD VSS / RSC_IHPSG13_CINVX8 +XDRV<2> qn_int<2> ADDR_N_O<2> VDD VSS / RSC_IHPSG13_CINVX8 +XDRV<1> qn_int<1> ADDR_N_O<1> VDD VSS / RSC_IHPSG13_CINVX8 +XDRV<0> qn_int<0> ADDR_N_O<0> VDD VSS / RSC_IHPSG13_CINVX8 +XINV<8> q_int<8> qn_int<8> VDD VSS / RSC_IHPSG13_CINVX2 +XINV<7> q_int<7> qn_int<7> VDD VSS / RSC_IHPSG13_CINVX2 +XINV<6> q_int<6> qn_int<6> VDD VSS / RSC_IHPSG13_CINVX2 +XINV<5> q_int<5> qn_int<5> VDD VSS / RSC_IHPSG13_CINVX2 +XINV<4> q_int<4> qn_int<4> VDD VSS / RSC_IHPSG13_CINVX2 +XINV<3> q_int<3> qn_int<3> VDD VSS / RSC_IHPSG13_CINVX2 +XINV<2> q_int<2> qn_int<2> VDD VSS / RSC_IHPSG13_CINVX2 +XINV<1> q_int<1> qn_int<1> VDD VSS / RSC_IHPSG13_CINVX2 +XINV<0> q_int<0> qn_int<0> VDD VSS / RSC_IHPSG13_CINVX2 +.ENDS + +.SUBCKT RM_IHPSG13_1024x32_c2_2P_DLY_MUX A SEL Z VDD VSS +XI11 net4 Z VDD VSS / RSC_IHPSG13_CINVX2 +XI8 A D<3> SEL net4 VDD VSS / RSC_IHPSG13_MX2IX1 +XI20<3> D<2> D<3> VDD VSS / RSC_IHPSG13_CDLYX1 +XI20<2> D<1> D<2> VDD VSS / RSC_IHPSG13_CDLYX1 +XI20<1> A D<1> VDD VSS / RSC_IHPSG13_CDLYX1 +.ENDS +.SUBCKT RM_IHPSG13_1024x32_c2_2P_CTRL ACLK_N BIST_CK_I BIST_CS_I BIST_EN BIST_RE_I ++ BIST_WE_I B_TIEL_O CK_I CS_I DCLK ECLK PULSE_H PULSE_L PULSE_O RCLK RE_I ++ ROW_CS WCLK WE_I VDD VSS +XI17 ck_regs we col_we VDD VSS / RSC_IHPSG13_DFNQX2 +XI16 ck_regs re col_re VDD VSS / RSC_IHPSG13_DFNQX2 +XI18 ck_regs cs net7 VDD VSS / RSC_IHPSG13_DFNQX2 +XI71 ACLK_N net012 PULSE_O VDD VSS / RSC_IHPSG13_DFNQX2 +XI77 col_we net017 net016 VDD VSS / RSC_IHPSG13_CNAND2X2 +XI76 col_re net017 net018 VDD VSS / RSC_IHPSG13_CNAND2X2 +XI15 ck_dly WEorREandCS aclk VDD VSS / RSC_IHPSG13_CGATEPX4 +XI14 ck WEandCS DCLK VDD VSS / RSC_IHPSG13_CGATEPX4 +XI60 net7 ROW_CS VDD VSS / RSC_IHPSG13_CBUFX8 +XI73 PULSE_O net012 VDD VSS / RSC_IHPSG13_CINVX2 +XI8 net017 net8 VDD VSS / RSC_IHPSG13_CINVX2 +XCAPS4<7> VDD VSS / RSC_IHPSG13_FILLCAP4 +XCAPS4<6> VDD VSS / RSC_IHPSG13_FILLCAP4 +XCAPS4<5> VDD VSS / RSC_IHPSG13_FILLCAP4 +XCAPS4<4> VDD VSS / RSC_IHPSG13_FILLCAP4 +XCAPS4<3> VDD VSS / RSC_IHPSG13_FILLCAP4 +XCAPS4<2> VDD VSS / RSC_IHPSG13_FILLCAP4 +XCAPS4<1> VDD VSS / RSC_IHPSG13_FILLCAP4 +XBM_TIEL B_TIEL_O VDD VSS / RSC_IHPSG13_TIEL +XI64 ck ck_dly VDD VSS / RSC_IHPSG13_CDLYX2 +XI86 CS_I BIST_CS_I BIST_EN cs VDD VSS / RSC_IHPSG13_MX2X2 +XI87 CK_I BIST_CK_I BIST_EN ck VDD VSS / RSC_IHPSG13_MX2X2 +XI85 WE_I BIST_WE_I BIST_EN we VDD VSS / RSC_IHPSG13_MX2X2 +XI84 RE_I BIST_RE_I BIST_EN re VDD VSS / RSC_IHPSG13_MX2X2 +XI48 ck_dly ck_regs VDD VSS / RSC_IHPSG13_CINVX4 +XI81 net016 WCLK VDD VSS / RSC_IHPSG13_CINVX4 +XI80 net018 RCLK VDD VSS / RSC_IHPSG13_CINVX4 +XI78 net8 net020 VDD VSS / RSC_IHPSG13_CINVX4 +XCAPS8<7> VDD VSS / RSC_IHPSG13_FILLCAP8 +XCAPS8<6> VDD VSS / RSC_IHPSG13_FILLCAP8 +XCAPS8<5> VDD VSS / RSC_IHPSG13_FILLCAP8 +XCAPS8<4> VDD VSS / RSC_IHPSG13_FILLCAP8 +XCAPS8<3> VDD VSS / RSC_IHPSG13_FILLCAP8 +XCAPS8<2> VDD VSS / RSC_IHPSG13_FILLCAP8 +XCAPS8<1> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI6 PULSE_L PULSE_H net017 VDD VSS / RSC_IHPSG13_XOR2X2 +XI22 we cs WEandCS VDD VSS / RSC_IHPSG13_AND2X2 +XI79 net020 ECLK VDD VSS / RSC_IHPSG13_CINVX8 +XI63 aclk ACLK_N VDD VSS / RSC_IHPSG13_CINVX8 +XI21 re we cs WEorREandCS VDD VSS / RSC_IHPSG13_OA12X1 +.ENDS +.SUBCKT RM_IHPSG13_1024x32_c2_2P_COLDEC5 ACLK_N ADDR<4> ADDR<3> ADDR<2> ADDR<1> ADDR<0> ++ ADDR_COL<1> ADDR_COL<0> ADDR_DEC<7> ADDR_DEC<6> ADDR_DEC<5> ADDR_DEC<4> ++ ADDR_DEC<3> ADDR_DEC<2> ADDR_DEC<1> ADDR_DEC<0> BIST_ADDR<4> BIST_ADDR<3> ++ BIST_ADDR<2> BIST_ADDR<1> BIST_ADDR<0> BIST_EN_I VDD VSS +XI17<4> VDD VSS / RSC_IHPSG13_FILLCAP4 +XI17<3> VDD VSS / RSC_IHPSG13_FILLCAP4 +XI17<2> VDD VSS / RSC_IHPSG13_FILLCAP4 +XI17<1> VDD VSS / RSC_IHPSG13_FILLCAP4 +XI1<7> PADR<0> PADR<1> PADR<2> addr_n<7> VDD VSS / RSC_IHPSG13_NAND3X2 +XI1<6> NADR<0> PADR<1> PADR<2> addr_n<6> VDD VSS / RSC_IHPSG13_NAND3X2 +XI1<5> PADR<0> NADR<1> PADR<2> addr_n<5> VDD VSS / RSC_IHPSG13_NAND3X2 +XI1<4> NADR<0> NADR<1> PADR<2> addr_n<4> VDD VSS / RSC_IHPSG13_NAND3X2 +XI1<3> PADR<0> PADR<1> NADR<2> addr_n<3> VDD VSS / RSC_IHPSG13_NAND3X2 +XI1<2> NADR<0> PADR<1> NADR<2> addr_n<2> VDD VSS / RSC_IHPSG13_NAND3X2 +XI1<1> PADR<0> NADR<1> NADR<2> addr_n<1> VDD VSS / RSC_IHPSG13_NAND3X2 +XI1<0> NADR<0> NADR<1> NADR<2> addr_n<0> VDD VSS / RSC_IHPSG13_NAND3X2 +XDFF<4> BIST_EN_I BIST_ADDR<4> ACLK_N ADDR<4> addr_int<1> net13<0> VDD ++ VSS / RSC_IHPSG13_DFNQMX2IX1 +XDFF<3> BIST_EN_I BIST_ADDR<3> ACLK_N ADDR<3> addr_int<0> net13<1> VDD ++ VSS / RSC_IHPSG13_DFNQMX2IX1 +XDFF<2> BIST_EN_I BIST_ADDR<2> ACLK_N ADDR<2> padr_int<2> net13<2> VDD ++ VSS / RSC_IHPSG13_DFNQMX2IX1 +XDFF<1> BIST_EN_I BIST_ADDR<1> ACLK_N ADDR<1> padr_int<1> net13<3> VDD ++ VSS / RSC_IHPSG13_DFNQMX2IX1 +XDFF<0> BIST_EN_I BIST_ADDR<0> ACLK_N ADDR<0> padr_int<0> net13<4> VDD ++ VSS / RSC_IHPSG13_DFNQMX2IX1 +XI3<2> padr_int<2> NADR<2> VDD VSS / RSC_IHPSG13_INVX2 +XI3<1> padr_int<1> NADR<1> VDD VSS / RSC_IHPSG13_INVX2 +XI3<0> padr_int<0> NADR<0> VDD VSS / RSC_IHPSG13_INVX2 +XI2<7> addr_n<7> ADDR_DEC<7> VDD VSS / RSC_IHPSG13_INVX2 +XI2<6> addr_n<6> ADDR_DEC<6> VDD VSS / RSC_IHPSG13_INVX2 +XI2<5> addr_n<5> ADDR_DEC<5> VDD VSS / RSC_IHPSG13_INVX2 +XI2<4> addr_n<4> ADDR_DEC<4> VDD VSS / RSC_IHPSG13_INVX2 +XI2<3> addr_n<3> ADDR_DEC<3> VDD VSS / RSC_IHPSG13_INVX2 +XI2<2> addr_n<2> ADDR_DEC<2> VDD VSS / RSC_IHPSG13_INVX2 +XI2<1> addr_n<1> ADDR_DEC<1> VDD VSS / RSC_IHPSG13_INVX2 +XI2<0> addr_n<0> ADDR_DEC<0> VDD VSS / RSC_IHPSG13_INVX2 +XI15<2> NADR<2> PADR<2> VDD VSS / RSC_IHPSG13_INVX2 +XI15<1> NADR<1> PADR<1> VDD VSS / RSC_IHPSG13_INVX2 +XI15<0> NADR<0> PADR<0> VDD VSS / RSC_IHPSG13_INVX2 +XI13<1> addr_int<1> ADDR_COL<1> VDD VSS / RSC_IHPSG13_CBUFX2 +XI13<0> addr_int<0> ADDR_COL<0> VDD VSS / RSC_IHPSG13_CBUFX2 +XI14<5> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI14<4> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI14<3> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI14<2> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI14<1> VDD VSS / RSC_IHPSG13_FILLCAP8 +.ENDS +.SUBCKT RM_IHPSG13_1024x32_c2_2P_BLDRV A_BLC<3> A_BLC<2> A_BLC<1> A_BLC<0> A_BLC_SEL ++ A_BLT<3> A_BLT<2> A_BLT<1> A_BLT<0> A_BLT_SEL A_PRE_N A_SEL_P<3> A_SEL_P<2> ++ A_SEL_P<1> A_SEL_P<0> A_WR_ONE A_WR_ZERO B_BLC<3> B_BLC<2> B_BLC<1> B_BLC<0> ++ B_BLC_SEL B_BLT<3> B_BLT<2> B_BLT<1> B_BLT<0> B_BLT_SEL B_PRE_N B_SEL_P<3> ++ B_SEL_P<2> B_SEL_P<1> B_SEL_P<0> B_WR_ONE B_WR_ZERO VDD VSS +MA_CWN<3> A_BLC<3> A_BLC_NMOS_DRIVE<3> VSS VSS sg13_lv_nmos m=1 ++ w=4.82u l=130.00n ng=2 nrd=0 nrs=0 +MA_CWN<2> A_BLC<2> A_BLC_NMOS_DRIVE<2> VSS VSS sg13_lv_nmos m=1 ++ w=4.82u l=130.00n ng=2 nrd=0 nrs=0 +MA_CWN<1> A_BLC<1> A_BLC_NMOS_DRIVE<1> VSS VSS sg13_lv_nmos m=1 ++ w=4.82u l=130.00n ng=2 nrd=0 nrs=0 +MA_CWN<0> A_BLC<0> A_BLC_NMOS_DRIVE<0> VSS VSS sg13_lv_nmos m=1 ++ w=4.82u l=130.00n ng=2 nrd=0 nrs=0 +MA_TWN<3> A_BLT<3> A_BLT_NMOS_DRIVE<3> VSS VSS sg13_lv_nmos m=1 ++ w=4.82u l=130.00n ng=2 nrd=0 nrs=0 +MA_TWN<2> A_BLT<2> A_BLT_NMOS_DRIVE<2> VSS VSS sg13_lv_nmos m=1 ++ w=4.82u l=130.00n ng=2 nrd=0 nrs=0 +MA_TWN<1> A_BLT<1> A_BLT_NMOS_DRIVE<1> VSS VSS sg13_lv_nmos m=1 ++ w=4.82u l=130.00n ng=2 nrd=0 nrs=0 +MA_TWN<0> A_BLT<0> A_BLT_NMOS_DRIVE<0> VSS VSS sg13_lv_nmos m=1 ++ w=4.82u l=130.00n ng=2 nrd=0 nrs=0 +MB_TWN<3> B_BLT<3> B_BLT_NMOS_DRIVE<3> VSS VSS sg13_lv_nmos m=1 ++ w=4.82u l=130.00n ng=2 nrd=0 nrs=0 +MB_TWN<2> B_BLT<2> B_BLT_NMOS_DRIVE<2> VSS VSS sg13_lv_nmos m=1 ++ w=4.82u l=130.00n ng=2 nrd=0 nrs=0 +MB_TWN<1> B_BLT<1> B_BLT_NMOS_DRIVE<1> VSS VSS sg13_lv_nmos m=1 ++ w=4.82u l=130.00n ng=2 nrd=0 nrs=0 +MB_TWN<0> B_BLT<0> B_BLT_NMOS_DRIVE<0> VSS VSS sg13_lv_nmos m=1 ++ w=4.82u l=130.00n ng=2 nrd=0 nrs=0 +MB_CWN<3> B_BLC<3> B_BLC_NMOS_DRIVE<3> VSS VSS sg13_lv_nmos m=1 ++ w=4.82u l=130.00n ng=2 nrd=0 nrs=0 +MB_CWN<2> B_BLC<2> B_BLC_NMOS_DRIVE<2> VSS VSS sg13_lv_nmos m=1 ++ w=4.82u l=130.00n ng=2 nrd=0 nrs=0 +MB_CWN<1> B_BLC<1> B_BLC_NMOS_DRIVE<1> VSS VSS sg13_lv_nmos m=1 ++ w=4.82u l=130.00n ng=2 nrd=0 nrs=0 +MB_CWN<0> B_BLC<0> B_BLC_NMOS_DRIVE<0> VSS VSS sg13_lv_nmos m=1 ++ w=4.82u l=130.00n ng=2 nrd=0 nrs=0 +MA_CPR<3> A_BLC<3> A_PRE_N VDD VDD sg13_lv_pmos m=1 w=3.000u l=130.00n ++ ng=2 nrd=0 nrs=0 +MA_CPR<2> A_BLC<2> A_PRE_N VDD VDD sg13_lv_pmos m=1 w=3.000u l=130.00n ++ ng=2 nrd=0 nrs=0 +MA_CPR<1> A_BLC<1> A_PRE_N VDD VDD sg13_lv_pmos m=1 w=3.000u l=130.00n ++ ng=2 nrd=0 nrs=0 +MA_CPR<0> A_BLC<0> A_PRE_N VDD VDD sg13_lv_pmos m=1 w=3.000u l=130.00n ++ ng=2 nrd=0 nrs=0 +MA_TWP<3> A_BLT<3> A_BLT_PMOS_DRIVE<3> VDD VDD sg13_lv_pmos m=1 w=1.5u ++ l=130.00n ng=1 nrd=0 nrs=0 +MA_TWP<2> A_BLT<2> A_BLT_PMOS_DRIVE<2> VDD VDD sg13_lv_pmos m=1 w=1.5u ++ l=130.00n ng=1 nrd=0 nrs=0 +MA_TWP<1> A_BLT<1> A_BLT_PMOS_DRIVE<1> VDD VDD sg13_lv_pmos m=1 w=1.5u ++ l=130.00n ng=1 nrd=0 nrs=0 +MA_TWP<0> A_BLT<0> A_BLT_PMOS_DRIVE<0> VDD VDD sg13_lv_pmos m=1 w=1.5u ++ l=130.00n ng=1 nrd=0 nrs=0 +MA_CWP<3> A_BLC<3> A_BLC_PMOS_DRIVE<3> VDD VDD sg13_lv_pmos m=1 w=1.5u ++ l=130.00n ng=1 nrd=0 nrs=0 +MA_CWP<2> A_BLC<2> A_BLC_PMOS_DRIVE<2> VDD VDD sg13_lv_pmos m=1 w=1.5u ++ l=130.00n ng=1 nrd=0 nrs=0 +MA_CWP<1> A_BLC<1> A_BLC_PMOS_DRIVE<1> VDD VDD sg13_lv_pmos m=1 w=1.5u ++ l=130.00n ng=1 nrd=0 nrs=0 +MA_CWP<0> A_BLC<0> A_BLC_PMOS_DRIVE<0> VDD VDD sg13_lv_pmos m=1 w=1.5u ++ l=130.00n ng=1 nrd=0 nrs=0 +MA_TPR<3> A_BLT<3> A_PRE_N VDD VDD sg13_lv_pmos m=1 w=3.000u l=130.00n ++ ng=2 nrd=0 nrs=0 +MA_TPR<2> A_BLT<2> A_PRE_N VDD VDD sg13_lv_pmos m=1 w=3.000u l=130.00n ++ ng=2 nrd=0 nrs=0 +MA_TPR<1> A_BLT<1> A_PRE_N VDD VDD sg13_lv_pmos m=1 w=3.000u l=130.00n ++ ng=2 nrd=0 nrs=0 +MA_TPR<0> A_BLT<0> A_PRE_N VDD VDD sg13_lv_pmos m=1 w=3.000u l=130.00n ++ ng=2 nrd=0 nrs=0 +MA_TSP<3> A_BLT_SEL A_SEL_N<3> A_BLT<3> VDD sg13_lv_pmos m=1 w=1.5u ++ l=130.00n ng=1 nrd=0 nrs=0 +MA_TSP<2> A_BLT_SEL A_SEL_N<2> A_BLT<2> VDD sg13_lv_pmos m=1 w=1.5u ++ l=130.00n ng=1 nrd=0 nrs=0 +MA_TSP<1> A_BLT_SEL A_SEL_N<1> A_BLT<1> VDD sg13_lv_pmos m=1 w=1.5u ++ l=130.00n ng=1 nrd=0 nrs=0 +MA_TSP<0> A_BLT_SEL A_SEL_N<0> A_BLT<0> VDD sg13_lv_pmos m=1 w=1.5u ++ l=130.00n ng=1 nrd=0 nrs=0 +MA_CSP<3> A_BLC_SEL A_SEL_N<3> A_BLC<3> VDD sg13_lv_pmos m=1 w=1.5u ++ l=130.00n ng=1 nrd=0 nrs=0 +MA_CSP<2> A_BLC_SEL A_SEL_N<2> A_BLC<2> VDD sg13_lv_pmos m=1 w=1.5u ++ l=130.00n ng=1 nrd=0 nrs=0 +MA_CSP<1> A_BLC_SEL A_SEL_N<1> A_BLC<1> VDD sg13_lv_pmos m=1 w=1.5u ++ l=130.00n ng=1 nrd=0 nrs=0 +MA_CSP<0> A_BLC_SEL A_SEL_N<0> A_BLC<0> VDD sg13_lv_pmos m=1 w=1.5u ++ l=130.00n ng=1 nrd=0 nrs=0 +MB_CWP<3> B_BLC<3> B_BLC_PMOS_DRIVE<3> VDD VDD sg13_lv_pmos m=1 w=1.5u ++ l=130.00n ng=1 nrd=0 nrs=0 +MB_CWP<2> B_BLC<2> B_BLC_PMOS_DRIVE<2> VDD VDD sg13_lv_pmos m=1 w=1.5u ++ l=130.00n ng=1 nrd=0 nrs=0 +MB_CWP<1> B_BLC<1> B_BLC_PMOS_DRIVE<1> VDD VDD sg13_lv_pmos m=1 w=1.5u ++ l=130.00n ng=1 nrd=0 nrs=0 +MB_CWP<0> B_BLC<0> B_BLC_PMOS_DRIVE<0> VDD VDD sg13_lv_pmos m=1 w=1.5u ++ l=130.00n ng=1 nrd=0 nrs=0 +MB_TWP<3> B_BLT<3> B_BLT_PMOS_DRIVE<3> VDD VDD sg13_lv_pmos m=1 w=1.5u ++ l=130.00n ng=1 nrd=0 nrs=0 +MB_TWP<2> B_BLT<2> B_BLT_PMOS_DRIVE<2> VDD VDD sg13_lv_pmos m=1 w=1.5u ++ l=130.00n ng=1 nrd=0 nrs=0 +MB_TWP<1> B_BLT<1> B_BLT_PMOS_DRIVE<1> VDD VDD sg13_lv_pmos m=1 w=1.5u ++ l=130.00n ng=1 nrd=0 nrs=0 +MB_TWP<0> B_BLT<0> B_BLT_PMOS_DRIVE<0> VDD VDD sg13_lv_pmos m=1 w=1.5u ++ l=130.00n ng=1 nrd=0 nrs=0 +MB_TSP<3> B_BLT_SEL B_SEL_N<3> B_BLT<3> VDD sg13_lv_pmos m=1 w=1.5u ++ l=130.00n ng=1 nrd=0 nrs=0 +MB_TSP<2> B_BLT_SEL B_SEL_N<2> B_BLT<2> VDD sg13_lv_pmos m=1 w=1.5u ++ l=130.00n ng=1 nrd=0 nrs=0 +MB_TSP<1> B_BLT_SEL B_SEL_N<1> B_BLT<1> VDD sg13_lv_pmos m=1 w=1.5u ++ l=130.00n ng=1 nrd=0 nrs=0 +MB_TSP<0> B_BLT_SEL B_SEL_N<0> B_BLT<0> VDD sg13_lv_pmos m=1 w=1.5u ++ l=130.00n ng=1 nrd=0 nrs=0 +MB_TPR<3> B_BLT<3> B_PRE_N VDD VDD sg13_lv_pmos m=1 w=3.000u l=130.00n ++ ng=2 nrd=0 nrs=0 +MB_TPR<2> B_BLT<2> B_PRE_N VDD VDD sg13_lv_pmos m=1 w=3.000u l=130.00n ++ ng=2 nrd=0 nrs=0 +MB_TPR<1> B_BLT<1> B_PRE_N VDD VDD sg13_lv_pmos m=1 w=3.000u l=130.00n ++ ng=2 nrd=0 nrs=0 +MB_TPR<0> B_BLT<0> B_PRE_N VDD VDD sg13_lv_pmos m=1 w=3.000u l=130.00n ++ ng=2 nrd=0 nrs=0 +MB_CSP<3> B_BLC_SEL B_SEL_N<3> B_BLC<3> VDD sg13_lv_pmos m=1 w=1.5u ++ l=130.00n ng=1 nrd=0 nrs=0 +MB_CSP<2> B_BLC_SEL B_SEL_N<2> B_BLC<2> VDD sg13_lv_pmos m=1 w=1.5u ++ l=130.00n ng=1 nrd=0 nrs=0 +MB_CSP<1> B_BLC_SEL B_SEL_N<1> B_BLC<1> VDD sg13_lv_pmos m=1 w=1.5u ++ l=130.00n ng=1 nrd=0 nrs=0 +MB_CSP<0> B_BLC_SEL B_SEL_N<0> B_BLC<0> VDD sg13_lv_pmos m=1 w=1.5u ++ l=130.00n ng=1 nrd=0 nrs=0 +MB_CPR<3> B_BLC<3> B_PRE_N VDD VDD sg13_lv_pmos m=1 w=3.000u l=130.00n ++ ng=2 nrd=0 nrs=0 +MB_CPR<2> B_BLC<2> B_PRE_N VDD VDD sg13_lv_pmos m=1 w=3.000u l=130.00n ++ ng=2 nrd=0 nrs=0 +MB_CPR<1> B_BLC<1> B_PRE_N VDD VDD sg13_lv_pmos m=1 w=3.000u l=130.00n ++ ng=2 nrd=0 nrs=0 +MB_CPR<0> B_BLC<0> B_PRE_N VDD VDD sg13_lv_pmos m=1 w=3.000u l=130.00n ++ ng=2 nrd=0 nrs=0 +XA_SEL<3> A_SEL_P<3> A_SEL_N<3> VDD VSS / RSC_IHPSG13_INVX2 +XA_SEL<2> A_SEL_P<2> A_SEL_N<2> VDD VSS / RSC_IHPSG13_INVX2 +XA_SEL<1> A_SEL_P<1> A_SEL_N<1> VDD VSS / RSC_IHPSG13_INVX2 +XA_SEL<0> A_SEL_P<0> A_SEL_N<0> VDD VSS / RSC_IHPSG13_INVX2 +XA_CINV<3> A_BLT_PMOS_DRIVE<3> A_BLC_NMOS_DRIVE<3> VDD VSS / ++ RSC_IHPSG13_INVX2 +XA_CINV<2> A_BLT_PMOS_DRIVE<2> A_BLC_NMOS_DRIVE<2> VDD VSS / ++ RSC_IHPSG13_INVX2 +XA_CINV<1> A_BLT_PMOS_DRIVE<1> A_BLC_NMOS_DRIVE<1> VDD VSS / ++ RSC_IHPSG13_INVX2 +XA_CINV<0> A_BLT_PMOS_DRIVE<0> A_BLC_NMOS_DRIVE<0> VDD VSS / ++ RSC_IHPSG13_INVX2 +XA_TINV<3> A_BLC_PMOS_DRIVE<3> A_BLT_NMOS_DRIVE<3> VDD VSS / ++ RSC_IHPSG13_INVX2 +XA_TINV<2> A_BLC_PMOS_DRIVE<2> A_BLT_NMOS_DRIVE<2> VDD VSS / ++ RSC_IHPSG13_INVX2 +XA_TINV<1> A_BLC_PMOS_DRIVE<1> A_BLT_NMOS_DRIVE<1> VDD VSS / ++ RSC_IHPSG13_INVX2 +XA_TINV<0> A_BLC_PMOS_DRIVE<0> A_BLT_NMOS_DRIVE<0> VDD VSS / ++ RSC_IHPSG13_INVX2 +XB_SEL<3> B_SEL_P<3> B_SEL_N<3> VDD VSS / RSC_IHPSG13_INVX2 +XB_SEL<2> B_SEL_P<2> B_SEL_N<2> VDD VSS / RSC_IHPSG13_INVX2 +XB_SEL<1> B_SEL_P<1> B_SEL_N<1> VDD VSS / RSC_IHPSG13_INVX2 +XB_SEL<0> B_SEL_P<0> B_SEL_N<0> VDD VSS / RSC_IHPSG13_INVX2 +XB_TINV<3> B_BLC_PMOS_DRIVE<3> B_BLT_NMOS_DRIVE<3> VDD VSS / ++ RSC_IHPSG13_INVX2 +XB_TINV<2> B_BLC_PMOS_DRIVE<2> B_BLT_NMOS_DRIVE<2> VDD VSS / ++ RSC_IHPSG13_INVX2 +XB_TINV<1> B_BLC_PMOS_DRIVE<1> B_BLT_NMOS_DRIVE<1> VDD VSS / ++ RSC_IHPSG13_INVX2 +XB_TINV<0> B_BLC_PMOS_DRIVE<0> B_BLT_NMOS_DRIVE<0> VDD VSS / ++ RSC_IHPSG13_INVX2 +XB_CINV<3> B_BLT_PMOS_DRIVE<3> B_BLC_NMOS_DRIVE<3> VDD VSS / ++ RSC_IHPSG13_INVX2 +XB_CINV<2> B_BLT_PMOS_DRIVE<2> B_BLC_NMOS_DRIVE<2> VDD VSS / ++ RSC_IHPSG13_INVX2 +XB_CINV<1> B_BLT_PMOS_DRIVE<1> B_BLC_NMOS_DRIVE<1> VDD VSS / ++ RSC_IHPSG13_INVX2 +XB_CINV<0> B_BLT_PMOS_DRIVE<0> B_BLC_NMOS_DRIVE<0> VDD VSS / ++ RSC_IHPSG13_INVX2 +XA_TDEC<3> A_SEL_P<3> A_WR_ONE A_BLT_PMOS_DRIVE<3> VDD VSS / ++ RSC_IHPSG13_NAND2X2 +XA_TDEC<2> A_SEL_P<2> A_WR_ONE A_BLT_PMOS_DRIVE<2> VDD VSS / ++ RSC_IHPSG13_NAND2X2 +XA_TDEC<1> A_SEL_P<1> A_WR_ONE A_BLT_PMOS_DRIVE<1> VDD VSS / ++ RSC_IHPSG13_NAND2X2 +XA_TDEC<0> A_SEL_P<0> A_WR_ONE A_BLT_PMOS_DRIVE<0> VDD VSS / ++ RSC_IHPSG13_NAND2X2 +XA_CDEC<3> A_SEL_P<3> A_WR_ZERO A_BLC_PMOS_DRIVE<3> VDD VSS / ++ RSC_IHPSG13_NAND2X2 +XA_CDEC<2> A_SEL_P<2> A_WR_ZERO A_BLC_PMOS_DRIVE<2> VDD VSS / ++ RSC_IHPSG13_NAND2X2 +XA_CDEC<1> A_SEL_P<1> A_WR_ZERO A_BLC_PMOS_DRIVE<1> VDD VSS / ++ RSC_IHPSG13_NAND2X2 +XA_CDEC<0> A_SEL_P<0> A_WR_ZERO A_BLC_PMOS_DRIVE<0> VDD VSS / ++ RSC_IHPSG13_NAND2X2 +XB_CDEC<3> B_SEL_P<3> B_WR_ZERO B_BLC_PMOS_DRIVE<3> VDD VSS / ++ RSC_IHPSG13_NAND2X2 +XB_CDEC<2> B_SEL_P<2> B_WR_ZERO B_BLC_PMOS_DRIVE<2> VDD VSS / ++ RSC_IHPSG13_NAND2X2 +XB_CDEC<1> B_SEL_P<1> B_WR_ZERO B_BLC_PMOS_DRIVE<1> VDD VSS / ++ RSC_IHPSG13_NAND2X2 +XB_CDEC<0> B_SEL_P<0> B_WR_ZERO B_BLC_PMOS_DRIVE<0> VDD VSS / ++ RSC_IHPSG13_NAND2X2 +XB_TDEC<3> B_SEL_P<3> B_WR_ONE B_BLT_PMOS_DRIVE<3> VDD VSS / ++ RSC_IHPSG13_NAND2X2 +XB_TDEC<2> B_SEL_P<2> B_WR_ONE B_BLT_PMOS_DRIVE<2> VDD VSS / ++ RSC_IHPSG13_NAND2X2 +XB_TDEC<1> B_SEL_P<1> B_WR_ONE B_BLT_PMOS_DRIVE<1> VDD VSS / ++ RSC_IHPSG13_NAND2X2 +XB_TDEC<0> B_SEL_P<0> B_WR_ONE B_BLT_PMOS_DRIVE<0> VDD VSS / ++ RSC_IHPSG13_NAND2X2 +.ENDS +.SUBCKT RSC_IHPSG13_AND2X6 A B Z VDD VSS +MN3 Z net6 VSS VSS sg13_lv_nmos m=1 w=2.94u l=130.00n ng=3 nrd=0 nrs=0 +MN4 net9 B VSS VSS sg13_lv_nmos m=1 w=500.0n l=130.00n ng=1 nrd=0 nrs=0 +MN6 net6 A net9 VSS sg13_lv_nmos m=1 w=500.0n l=130.00n ng=1 nrd=0 nrs=0 +MP2 Z net6 VDD VDD sg13_lv_pmos m=1 w=4.86u l=130.00n ng=3 nrd=0 nrs=0 +MP0 net6 B VDD VDD sg13_lv_pmos m=1 w=860.00n l=130.00n ng=1 nrd=0 ++ nrs=0 +MP1 net6 A VDD VDD sg13_lv_pmos m=1 w=860.00n l=130.00n ng=1 nrd=0 ++ nrs=0 +.ENDS +.SUBCKT RM_IHPSG13_1024x32_c2_2P_COLCTRL5 A_ADDR_COL<1> A_ADDR_COL<0> A_ADDR_DEC<7> ++ A_ADDR_DEC<6> A_ADDR_DEC<5> A_ADDR_DEC<4> A_ADDR_DEC<3> A_ADDR_DEC<2> ++ A_ADDR_DEC<1> A_ADDR_DEC<0> A_BIST_BM_I A_BIST_DW_I A_BIST_EN_I A_BLC<31> ++ A_BLC<30> A_BLC<29> A_BLC<28> A_BLC<27> A_BLC<26> A_BLC<25> A_BLC<24> ++ A_BLC<23> A_BLC<22> A_BLC<21> A_BLC<20> A_BLC<19> A_BLC<18> A_BLC<17> ++ A_BLC<16> A_BLC<15> A_BLC<14> A_BLC<13> A_BLC<12> A_BLC<11> A_BLC<10> ++ A_BLC<9> A_BLC<8> A_BLC<7> A_BLC<6> A_BLC<5> A_BLC<4> A_BLC<3> A_BLC<2> ++ A_BLC<1> A_BLC<0> A_BLT<31> A_BLT<30> A_BLT<29> A_BLT<28> A_BLT<27> ++ A_BLT<26> A_BLT<25> A_BLT<24> A_BLT<23> A_BLT<22> A_BLT<21> A_BLT<20> ++ A_BLT<19> A_BLT<18> A_BLT<17> A_BLT<16> A_BLT<15> A_BLT<14> A_BLT<13> ++ A_BLT<12> A_BLT<11> A_BLT<10> A_BLT<9> A_BLT<8> A_BLT<7> A_BLT<6> A_BLT<5> ++ A_BLT<4> A_BLT<3> A_BLT<2> A_BLT<1> A_BLT<0> A_BM_I A_DCLK_B_L A_DCLK_B_R ++ A_DCLK_L A_DCLK_R A_DR_O A_DW_I A_RCLK_B_L A_RCLK_B_R A_RCLK_L A_RCLK_R ++ A_TIEH_O A_WCLK_B_L A_WCLK_B_R A_WCLK_L A_WCLK_R B_ADDR_COL<1> B_ADDR_COL<0> ++ B_ADDR_DEC<7> B_ADDR_DEC<6> B_ADDR_DEC<5> B_ADDR_DEC<4> B_ADDR_DEC<3> ++ B_ADDR_DEC<2> B_ADDR_DEC<1> B_ADDR_DEC<0> B_BIST_BM_I B_BIST_DW_I ++ B_BIST_EN_I B_BLC<31> B_BLC<30> B_BLC<29> B_BLC<28> B_BLC<27> B_BLC<26> ++ B_BLC<25> B_BLC<24> B_BLC<23> B_BLC<22> B_BLC<21> B_BLC<20> B_BLC<19> ++ B_BLC<18> B_BLC<17> B_BLC<16> B_BLC<15> B_BLC<14> B_BLC<13> B_BLC<12> ++ B_BLC<11> B_BLC<10> B_BLC<9> B_BLC<8> B_BLC<7> B_BLC<6> B_BLC<5> B_BLC<4> ++ B_BLC<3> B_BLC<2> B_BLC<1> B_BLC<0> B_BLT<31> B_BLT<30> B_BLT<29> B_BLT<28> ++ B_BLT<27> B_BLT<26> B_BLT<25> B_BLT<24> B_BLT<23> B_BLT<22> B_BLT<21> ++ B_BLT<20> B_BLT<19> B_BLT<18> B_BLT<17> B_BLT<16> B_BLT<15> B_BLT<14> ++ B_BLT<13> B_BLT<12> B_BLT<11> B_BLT<10> B_BLT<9> B_BLT<8> B_BLT<7> B_BLT<6> ++ B_BLT<5> B_BLT<4> B_BLT<3> B_BLT<2> B_BLT<1> B_BLT<0> B_BM_I B_DCLK_B_L ++ B_DCLK_B_R B_DCLK_L B_DCLK_R B_DR_O B_DW_I B_RCLK_B_L B_RCLK_B_R B_RCLK_L ++ B_RCLK_R B_TIEH_O B_WCLK_B_L B_WCLK_B_R B_WCLK_L B_WCLK_R VDD VSS +XB_I80<1> B_WCLK_B_L B_RCLK_B_L B_W_nor_R<1> VDD VSS / ++ RSC_IHPSG13_AND2X2 +XB_I80<0> B_WCLK_B_L B_RCLK_B_L B_W_nor_R<0> VDD VSS / ++ RSC_IHPSG13_AND2X2 +XA_I80<1> A_WCLK_B_L A_RCLK_B_L A_W_nor_R<1> VDD VSS / ++ RSC_IHPSG13_AND2X2 +XA_I80<0> A_WCLK_B_L A_RCLK_B_L A_W_nor_R<0> VDD VSS / ++ RSC_IHPSG13_AND2X2 +XB_I44 B_BM_N B_WCLK_B_L B_DO_WRITE_P VDD VSS / RSC_IHPSG13_NOR2X2 +XA_I44 A_BM_N A_WCLK_B_L A_DO_WRITE_P VDD VSS / RSC_IHPSG13_NOR2X2 +XI_FILL4<16> VDD VSS / RSC_IHPSG13_FILLCAP4 +XI_FILL4<15> VDD VSS / RSC_IHPSG13_FILLCAP4 +XI_FILL4<14> VDD VSS / RSC_IHPSG13_FILLCAP4 +XI_FILL4<13> VDD VSS / RSC_IHPSG13_FILLCAP4 +XI_FILL4<12> VDD VSS / RSC_IHPSG13_FILLCAP4 +XI_FILL4<11> VDD VSS / RSC_IHPSG13_FILLCAP4 +XI_FILL4<10> VDD VSS / RSC_IHPSG13_FILLCAP4 +XI_FILL4<9> VDD VSS / RSC_IHPSG13_FILLCAP4 +XI_FILL4<8> VDD VSS / RSC_IHPSG13_FILLCAP4 +XI_FILL4<7> VDD VSS / RSC_IHPSG13_FILLCAP4 +XI_FILL4<6> VDD VSS / RSC_IHPSG13_FILLCAP4 +XI_FILL4<5> VDD VSS / RSC_IHPSG13_FILLCAP4 +XI_FILL4<4> VDD VSS / RSC_IHPSG13_FILLCAP4 +XI_FILL4<3> VDD VSS / RSC_IHPSG13_FILLCAP4 +XI_FILL4<2> VDD VSS / RSC_IHPSG13_FILLCAP4 +XI_FILL4<1> VDD VSS / RSC_IHPSG13_FILLCAP4 +XB_INV<6> B_N1<1> B_P1<1> VDD VSS / RSC_IHPSG13_CINVX4 +XB_INV<5> B_N0<1> B_P0<1> VDD VSS / RSC_IHPSG13_CINVX4 +XB_INV<4> B_N0<0> B_P0<0> VDD VSS / RSC_IHPSG13_CINVX4 +XB_INV<3> B_ADDR_COL<1> B_N1<1> VDD VSS / RSC_IHPSG13_CINVX4 +XB_INV<2> B_ADDR_COL<1> B_N1<0> VDD VSS / RSC_IHPSG13_CINVX4 +XB_INV<1> B_ADDR_COL<0> B_N0<1> VDD VSS / RSC_IHPSG13_CINVX4 +XB_INV<0> B_ADDR_COL<0> B_N0<0> VDD VSS / RSC_IHPSG13_CINVX4 +XA_INV<6> A_N1<1> A_P1<1> VDD VSS / RSC_IHPSG13_CINVX4 +XA_INV<5> A_N0<1> A_P0<1> VDD VSS / RSC_IHPSG13_CINVX4 +XA_INV<4> A_N0<0> A_P0<0> VDD VSS / RSC_IHPSG13_CINVX4 +XA_INV<3> A_ADDR_COL<1> A_N1<1> VDD VSS / RSC_IHPSG13_CINVX4 +XA_INV<2> A_ADDR_COL<1> A_N1<0> VDD VSS / RSC_IHPSG13_CINVX4 +XA_INV<1> A_ADDR_COL<0> A_N0<1> VDD VSS / RSC_IHPSG13_CINVX4 +XA_INV<0> A_ADDR_COL<0> A_N0<0> VDD VSS / RSC_IHPSG13_CINVX4 +XB_I81<3> B_W_nor_R<1> B_PRE_N VDD VSS / RSC_IHPSG13_CINVX4_WN +XB_I81<2> B_W_nor_R<1> B_PRE_N VDD VSS / RSC_IHPSG13_CINVX4_WN +XB_I81<1> B_W_nor_R<0> B_PRE_N VDD VSS / RSC_IHPSG13_CINVX4_WN +XB_I81<0> B_W_nor_R<0> B_PRE_N VDD VSS / RSC_IHPSG13_CINVX4_WN +XA_I81<3> A_W_nor_R<1> A_PRE_N VDD VSS / RSC_IHPSG13_CINVX4_WN +XA_I81<2> A_W_nor_R<1> A_PRE_N VDD VSS / RSC_IHPSG13_CINVX4_WN +XA_I81<1> A_W_nor_R<0> A_PRE_N VDD VSS / RSC_IHPSG13_CINVX4_WN +XA_I81<0> A_W_nor_R<0> A_PRE_N VDD VSS / RSC_IHPSG13_CINVX4_WN +XI_FILL8<78> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI_FILL8<77> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI_FILL8<76> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI_FILL8<75> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI_FILL8<74> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI_FILL8<73> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI_FILL8<72> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI_FILL8<71> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI_FILL8<70> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI_FILL8<69> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI_FILL8<68> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI_FILL8<67> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI_FILL8<66> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI_FILL8<65> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI_FILL8<64> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI_FILL8<63> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI_FILL8<62> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI_FILL8<61> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI_FILL8<60> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI_FILL8<59> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI_FILL8<58> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI_FILL8<57> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI_FILL8<56> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI_FILL8<55> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI_FILL8<54> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI_FILL8<53> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI_FILL8<52> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI_FILL8<51> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI_FILL8<50> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI_FILL8<49> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI_FILL8<48> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI_FILL8<47> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI_FILL8<46> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI_FILL8<45> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI_FILL8<44> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI_FILL8<43> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI_FILL8<42> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI_FILL8<41> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI_FILL8<40> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI_FILL8<39> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI_FILL8<38> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI_FILL8<37> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI_FILL8<36> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI_FILL8<35> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI_FILL8<34> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI_FILL8<33> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI_FILL8<32> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI_FILL8<31> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI_FILL8<30> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI_FILL8<29> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI_FILL8<28> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI_FILL8<27> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI_FILL8<26> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI_FILL8<25> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI_FILL8<24> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI_FILL8<23> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI_FILL8<22> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI_FILL8<21> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI_FILL8<20> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI_FILL8<19> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI_FILL8<18> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI_FILL8<17> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI_FILL8<16> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI_FILL8<15> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI_FILL8<14> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI_FILL8<13> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI_FILL8<12> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI_FILL8<11> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI_FILL8<10> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI_FILL8<9> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI_FILL8<8> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI_FILL8<7> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI_FILL8<6> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI_FILL8<5> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI_FILL8<4> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI_FILL8<3> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI_FILL8<2> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI_FILL8<1> VDD VSS / RSC_IHPSG13_FILLCAP8 +XAB_BLMUX<7> A_BLC<31> A_BLC<30> A_BLC<29> A_BLC<28> A_BLC_SEL A_BLT<31> ++ A_BLT<30> A_BLT<29> A_BLT<28> A_BLT_SEL A_PRE_N A_SEL_P<31> A_SEL_P<30> ++ A_SEL_P<29> A_SEL_P<28> A_WR_ONE A_WR_ZERO B_BLC<31> B_BLC<30> B_BLC<29> ++ B_BLC<28> B_BLC_SEL B_BLT<31> B_BLT<30> B_BLT<29> B_BLT<28> B_BLT_SEL ++ B_PRE_N B_SEL_P<31> B_SEL_P<30> B_SEL_P<29> B_SEL_P<28> B_WR_ONE B_WR_ZERO ++ VDD VSS / RM_IHPSG13_1024x32_c2_2P_BLDRV +XAB_BLMUX<6> A_BLC<27> A_BLC<26> A_BLC<25> A_BLC<24> A_BLC_SEL A_BLT<27> ++ A_BLT<26> A_BLT<25> A_BLT<24> A_BLT_SEL A_PRE_N A_SEL_P<27> A_SEL_P<26> ++ A_SEL_P<25> A_SEL_P<24> A_WR_ONE A_WR_ZERO B_BLC<27> B_BLC<26> B_BLC<25> ++ B_BLC<24> B_BLC_SEL B_BLT<27> B_BLT<26> B_BLT<25> B_BLT<24> B_BLT_SEL ++ B_PRE_N B_SEL_P<27> B_SEL_P<26> B_SEL_P<25> B_SEL_P<24> B_WR_ONE B_WR_ZERO ++ VDD VSS / RM_IHPSG13_1024x32_c2_2P_BLDRV +XAB_BLMUX<5> A_BLC<23> A_BLC<22> A_BLC<21> A_BLC<20> A_BLC_SEL A_BLT<23> ++ A_BLT<22> A_BLT<21> A_BLT<20> A_BLT_SEL A_PRE_N A_SEL_P<23> A_SEL_P<22> ++ A_SEL_P<21> A_SEL_P<20> A_WR_ONE A_WR_ZERO B_BLC<23> B_BLC<22> B_BLC<21> ++ B_BLC<20> B_BLC_SEL B_BLT<23> B_BLT<22> B_BLT<21> B_BLT<20> B_BLT_SEL ++ B_PRE_N B_SEL_P<23> B_SEL_P<22> B_SEL_P<21> B_SEL_P<20> B_WR_ONE B_WR_ZERO ++ VDD VSS / RM_IHPSG13_1024x32_c2_2P_BLDRV +XAB_BLMUX<4> A_BLC<19> A_BLC<18> A_BLC<17> A_BLC<16> A_BLC_SEL A_BLT<19> ++ A_BLT<18> A_BLT<17> A_BLT<16> A_BLT_SEL A_PRE_N A_SEL_P<19> A_SEL_P<18> ++ A_SEL_P<17> A_SEL_P<16> A_WR_ONE A_WR_ZERO B_BLC<19> B_BLC<18> B_BLC<17> ++ B_BLC<16> B_BLC_SEL B_BLT<19> B_BLT<18> B_BLT<17> B_BLT<16> B_BLT_SEL ++ B_PRE_N B_SEL_P<19> B_SEL_P<18> B_SEL_P<17> B_SEL_P<16> B_WR_ONE B_WR_ZERO ++ VDD VSS / RM_IHPSG13_1024x32_c2_2P_BLDRV +XAB_BLMUX<3> A_BLC<15> A_BLC<14> A_BLC<13> A_BLC<12> A_BLC_SEL A_BLT<15> ++ A_BLT<14> A_BLT<13> A_BLT<12> A_BLT_SEL A_PRE_N A_SEL_P<15> A_SEL_P<14> ++ A_SEL_P<13> A_SEL_P<12> A_WR_ONE A_WR_ZERO B_BLC<15> B_BLC<14> B_BLC<13> ++ B_BLC<12> B_BLC_SEL B_BLT<15> B_BLT<14> B_BLT<13> B_BLT<12> B_BLT_SEL ++ B_PRE_N B_SEL_P<15> B_SEL_P<14> B_SEL_P<13> B_SEL_P<12> B_WR_ONE B_WR_ZERO ++ VDD VSS / RM_IHPSG13_1024x32_c2_2P_BLDRV +XAB_BLMUX<2> A_BLC<11> A_BLC<10> A_BLC<9> A_BLC<8> A_BLC_SEL A_BLT<11> ++ A_BLT<10> A_BLT<9> A_BLT<8> A_BLT_SEL A_PRE_N A_SEL_P<11> A_SEL_P<10> ++ A_SEL_P<9> A_SEL_P<8> A_WR_ONE A_WR_ZERO B_BLC<11> B_BLC<10> B_BLC<9> ++ B_BLC<8> B_BLC_SEL B_BLT<11> B_BLT<10> B_BLT<9> B_BLT<8> B_BLT_SEL B_PRE_N ++ B_SEL_P<11> B_SEL_P<10> B_SEL_P<9> B_SEL_P<8> B_WR_ONE B_WR_ZERO VDD ++ VSS / RM_IHPSG13_1024x32_c2_2P_BLDRV +XAB_BLMUX<1> A_BLC<7> A_BLC<6> A_BLC<5> A_BLC<4> A_BLC_SEL A_BLT<7> A_BLT<6> ++ A_BLT<5> A_BLT<4> A_BLT_SEL A_PRE_N A_SEL_P<7> A_SEL_P<6> A_SEL_P<5> ++ A_SEL_P<4> A_WR_ONE A_WR_ZERO B_BLC<7> B_BLC<6> B_BLC<5> B_BLC<4> B_BLC_SEL ++ B_BLT<7> B_BLT<6> B_BLT<5> B_BLT<4> B_BLT_SEL B_PRE_N B_SEL_P<7> B_SEL_P<6> ++ B_SEL_P<5> B_SEL_P<4> B_WR_ONE B_WR_ZERO VDD VSS / ++ RM_IHPSG13_1024x32_c2_2P_BLDRV +XAB_BLMUX<0> A_BLC<3> A_BLC<2> A_BLC<1> A_BLC<0> A_BLC_SEL A_BLT<3> A_BLT<2> ++ A_BLT<1> A_BLT<0> A_BLT_SEL A_PRE_N A_SEL_P<3> A_SEL_P<2> A_SEL_P<1> ++ A_SEL_P<0> A_WR_ONE A_WR_ZERO B_BLC<3> B_BLC<2> B_BLC<1> B_BLC<0> B_BLC_SEL ++ B_BLT<3> B_BLT<2> B_BLT<1> B_BLT<0> B_BLT_SEL B_PRE_N B_SEL_P<3> B_SEL_P<2> ++ B_SEL_P<1> B_SEL_P<0> B_WR_ONE B_WR_ZERO VDD VSS / ++ RM_IHPSG13_1024x32_c2_2P_BLDRV +XB_I51 net037 B_DR_O VDD VSS / RSC_IHPSG13_INVX4 +XA_I51 net19 A_DR_O VDD VSS / RSC_IHPSG13_INVX4 +XB_I78 B_RCLK_B_L B_SAE VDD VSS / RSC_IHPSG13_CBUFX2 +XA_I78 A_RCLK_B_L A_SAE VDD VSS / RSC_IHPSG13_CBUFX2 +XB_I69 B_DCLK_L B_DCLK_B_L VDD VSS / RSC_IHPSG13_CINVX8 +XB_I50 B_WCLK_L B_WCLK_B_L VDD VSS / RSC_IHPSG13_CINVX8 +XB_EBUF B_RCLK_L B_RCLK_B_L VDD VSS / RSC_IHPSG13_CINVX8 +XA_I69 A_DCLK_L A_DCLK_B_L VDD VSS / RSC_IHPSG13_CINVX8 +XA_I50 A_WCLK_L A_WCLK_B_L VDD VSS / RSC_IHPSG13_CINVX8 +XA_EBUF A_RCLK_L A_RCLK_B_L VDD VSS / RSC_IHPSG13_CINVX8 +XB_I76 B_DI_N B_DO_WRITE_P B_WR_ZERO VDD VSS / RSC_IHPSG13_AND2X6 +XB_I75 B_DI_R B_DO_WRITE_P B_WR_ONE VDD VSS / RSC_IHPSG13_AND2X6 +XA_I76 A_DI_N A_DO_WRITE_P A_WR_ZERO VDD VSS / RSC_IHPSG13_AND2X6 +XA_I75 A_DI_R A_DO_WRITE_P A_WR_ONE VDD VSS / RSC_IHPSG13_AND2X6 +XB_I83 B_BM_R B_BM_N VDD VSS / RSC_IHPSG13_INVX2 +XB_DEC3INV<31> net041<0> B_SEL_P<31> VDD VSS / RSC_IHPSG13_INVX2 +XB_DEC3INV<30> net041<1> B_SEL_P<30> VDD VSS / RSC_IHPSG13_INVX2 +XB_DEC3INV<29> net041<2> B_SEL_P<29> VDD VSS / RSC_IHPSG13_INVX2 +XB_DEC3INV<28> net041<3> B_SEL_P<28> VDD VSS / RSC_IHPSG13_INVX2 +XB_DEC3INV<27> net041<4> B_SEL_P<27> VDD VSS / RSC_IHPSG13_INVX2 +XB_DEC3INV<26> net041<5> B_SEL_P<26> VDD VSS / RSC_IHPSG13_INVX2 +XB_DEC3INV<25> net041<6> B_SEL_P<25> VDD VSS / RSC_IHPSG13_INVX2 +XB_DEC3INV<24> net041<7> B_SEL_P<24> VDD VSS / RSC_IHPSG13_INVX2 +XB_DEC3INV<23> net041<8> B_SEL_P<23> VDD VSS / RSC_IHPSG13_INVX2 +XB_DEC3INV<22> net041<9> B_SEL_P<22> VDD VSS / RSC_IHPSG13_INVX2 +XB_DEC3INV<21> net041<10> B_SEL_P<21> VDD VSS / RSC_IHPSG13_INVX2 +XB_DEC3INV<20> net041<11> B_SEL_P<20> VDD VSS / RSC_IHPSG13_INVX2 +XB_DEC3INV<19> net041<12> B_SEL_P<19> VDD VSS / RSC_IHPSG13_INVX2 +XB_DEC3INV<18> net041<13> B_SEL_P<18> VDD VSS / RSC_IHPSG13_INVX2 +XB_DEC3INV<17> net041<14> B_SEL_P<17> VDD VSS / RSC_IHPSG13_INVX2 +XB_DEC3INV<16> net041<15> B_SEL_P<16> VDD VSS / RSC_IHPSG13_INVX2 +XB_DEC3INV<15> net041<16> B_SEL_P<15> VDD VSS / RSC_IHPSG13_INVX2 +XB_DEC3INV<14> net041<17> B_SEL_P<14> VDD VSS / RSC_IHPSG13_INVX2 +XB_DEC3INV<13> net041<18> B_SEL_P<13> VDD VSS / RSC_IHPSG13_INVX2 +XB_DEC3INV<12> net041<19> B_SEL_P<12> VDD VSS / RSC_IHPSG13_INVX2 +XB_DEC3INV<11> net041<20> B_SEL_P<11> VDD VSS / RSC_IHPSG13_INVX2 +XB_DEC3INV<10> net041<21> B_SEL_P<10> VDD VSS / RSC_IHPSG13_INVX2 +XB_DEC3INV<9> net041<22> B_SEL_P<9> VDD VSS / RSC_IHPSG13_INVX2 +XB_DEC3INV<8> net041<23> B_SEL_P<8> VDD VSS / RSC_IHPSG13_INVX2 +XB_DEC3INV<7> net041<24> B_SEL_P<7> VDD VSS / RSC_IHPSG13_INVX2 +XB_DEC3INV<6> net041<25> B_SEL_P<6> VDD VSS / RSC_IHPSG13_INVX2 +XB_DEC3INV<5> net041<26> B_SEL_P<5> VDD VSS / RSC_IHPSG13_INVX2 +XB_DEC3INV<4> net041<27> B_SEL_P<4> VDD VSS / RSC_IHPSG13_INVX2 +XB_DEC3INV<3> net041<28> B_SEL_P<3> VDD VSS / RSC_IHPSG13_INVX2 +XB_DEC3INV<2> net041<29> B_SEL_P<2> VDD VSS / RSC_IHPSG13_INVX2 +XB_DEC3INV<1> net041<30> B_SEL_P<1> VDD VSS / RSC_IHPSG13_INVX2 +XB_DEC3INV<0> net041<31> B_SEL_P<0> VDD VSS / RSC_IHPSG13_INVX2 +XB_I49 B_DI_R B_DI_N VDD VSS / RSC_IHPSG13_INVX2 +XA_I83 A_BM_R A_BM_N VDD VSS / RSC_IHPSG13_INVX2 +XA_DEC3INV<31> net23<0> A_SEL_P<31> VDD VSS / RSC_IHPSG13_INVX2 +XA_DEC3INV<30> net23<1> A_SEL_P<30> VDD VSS / RSC_IHPSG13_INVX2 +XA_DEC3INV<29> net23<2> A_SEL_P<29> VDD VSS / RSC_IHPSG13_INVX2 +XA_DEC3INV<28> net23<3> A_SEL_P<28> VDD VSS / RSC_IHPSG13_INVX2 +XA_DEC3INV<27> net23<4> A_SEL_P<27> VDD VSS / RSC_IHPSG13_INVX2 +XA_DEC3INV<26> net23<5> A_SEL_P<26> VDD VSS / RSC_IHPSG13_INVX2 +XA_DEC3INV<25> net23<6> A_SEL_P<25> VDD VSS / RSC_IHPSG13_INVX2 +XA_DEC3INV<24> net23<7> A_SEL_P<24> VDD VSS / RSC_IHPSG13_INVX2 +XA_DEC3INV<23> net23<8> A_SEL_P<23> VDD VSS / RSC_IHPSG13_INVX2 +XA_DEC3INV<22> net23<9> A_SEL_P<22> VDD VSS / RSC_IHPSG13_INVX2 +XA_DEC3INV<21> net23<10> A_SEL_P<21> VDD VSS / RSC_IHPSG13_INVX2 +XA_DEC3INV<20> net23<11> A_SEL_P<20> VDD VSS / RSC_IHPSG13_INVX2 +XA_DEC3INV<19> net23<12> A_SEL_P<19> VDD VSS / RSC_IHPSG13_INVX2 +XA_DEC3INV<18> net23<13> A_SEL_P<18> VDD VSS / RSC_IHPSG13_INVX2 +XA_DEC3INV<17> net23<14> A_SEL_P<17> VDD VSS / RSC_IHPSG13_INVX2 +XA_DEC3INV<16> net23<15> A_SEL_P<16> VDD VSS / RSC_IHPSG13_INVX2 +XA_DEC3INV<15> net23<16> A_SEL_P<15> VDD VSS / RSC_IHPSG13_INVX2 +XA_DEC3INV<14> net23<17> A_SEL_P<14> VDD VSS / RSC_IHPSG13_INVX2 +XA_DEC3INV<13> net23<18> A_SEL_P<13> VDD VSS / RSC_IHPSG13_INVX2 +XA_DEC3INV<12> net23<19> A_SEL_P<12> VDD VSS / RSC_IHPSG13_INVX2 +XA_DEC3INV<11> net23<20> A_SEL_P<11> VDD VSS / RSC_IHPSG13_INVX2 +XA_DEC3INV<10> net23<21> A_SEL_P<10> VDD VSS / RSC_IHPSG13_INVX2 +XA_DEC3INV<9> net23<22> A_SEL_P<9> VDD VSS / RSC_IHPSG13_INVX2 +XA_DEC3INV<8> net23<23> A_SEL_P<8> VDD VSS / RSC_IHPSG13_INVX2 +XA_DEC3INV<7> net23<24> A_SEL_P<7> VDD VSS / RSC_IHPSG13_INVX2 +XA_DEC3INV<6> net23<25> A_SEL_P<6> VDD VSS / RSC_IHPSG13_INVX2 +XA_DEC3INV<5> net23<26> A_SEL_P<5> VDD VSS / RSC_IHPSG13_INVX2 +XA_DEC3INV<4> net23<27> A_SEL_P<4> VDD VSS / RSC_IHPSG13_INVX2 +XA_DEC3INV<3> net23<28> A_SEL_P<3> VDD VSS / RSC_IHPSG13_INVX2 +XA_DEC3INV<2> net23<29> A_SEL_P<2> VDD VSS / RSC_IHPSG13_INVX2 +XA_DEC3INV<1> net23<30> A_SEL_P<1> VDD VSS / RSC_IHPSG13_INVX2 +XA_DEC3INV<0> net23<31> A_SEL_P<0> VDD VSS / RSC_IHPSG13_INVX2 +XA_I49 A_DI_R A_DI_N VDD VSS / RSC_IHPSG13_INVX2 +XB_ISENSE B_SAE B_BLC_SEL B_BLT_SEL net037 net038 VDD VSS / ++ RSC_IHPSG13_DFPQD_MSAFFX2 +XA_ISENSE A_SAE A_BLC_SEL A_BLT_SEL net19 net20 VDD VSS / ++ RSC_IHPSG13_DFPQD_MSAFFX2 +XB_DREG B_BIST_EN_I B_BIST_DW_I B_DCLK_B_L B_DW_I B_DI_R net042 VDD ++ VSS / RSC_IHPSG13_DFNQMX2IX1 +XB_BREG B_BIST_EN_I B_BIST_BM_I B_DCLK_B_L B_BM_I B_BM_R net043 VDD ++ VSS / RSC_IHPSG13_DFNQMX2IX1 +XA_DREG A_BIST_EN_I A_BIST_DW_I A_DCLK_B_L A_DW_I A_DI_R net22 VDD VSS ++ / RSC_IHPSG13_DFNQMX2IX1 +XA_BREG A_BIST_EN_I A_BIST_BM_I A_DCLK_B_L A_BM_I A_BM_R net21 VDD VSS ++ / RSC_IHPSG13_DFNQMX2IX1 +XB_DEC3<31> B_P1<1> B_P0<1> B_ADDR_DEC<7> net041<0> VDD VSS / ++ RSC_IHPSG13_NAND3X2 +XB_DEC3<30> B_P1<1> B_P0<1> B_ADDR_DEC<6> net041<1> VDD VSS / ++ RSC_IHPSG13_NAND3X2 +XB_DEC3<29> B_P1<1> B_P0<1> B_ADDR_DEC<5> net041<2> VDD VSS / ++ RSC_IHPSG13_NAND3X2 +XB_DEC3<28> B_P1<1> B_P0<1> B_ADDR_DEC<4> net041<3> VDD VSS / ++ RSC_IHPSG13_NAND3X2 +XB_DEC3<27> B_P1<1> B_P0<1> B_ADDR_DEC<3> net041<4> VDD VSS / ++ RSC_IHPSG13_NAND3X2 +XB_DEC3<26> B_P1<1> B_P0<1> B_ADDR_DEC<2> net041<5> VDD VSS / ++ RSC_IHPSG13_NAND3X2 +XB_DEC3<25> B_P1<1> B_P0<1> B_ADDR_DEC<1> net041<6> VDD VSS / ++ RSC_IHPSG13_NAND3X2 +XB_DEC3<24> B_P1<1> B_P0<1> B_ADDR_DEC<0> net041<7> VDD VSS / ++ RSC_IHPSG13_NAND3X2 +XB_DEC3<23> B_P1<1> B_N0<1> B_ADDR_DEC<7> net041<8> VDD VSS / ++ RSC_IHPSG13_NAND3X2 +XB_DEC3<22> B_P1<1> B_N0<1> B_ADDR_DEC<6> net041<9> VDD VSS / ++ RSC_IHPSG13_NAND3X2 +XB_DEC3<21> B_P1<1> B_N0<1> B_ADDR_DEC<5> net041<10> VDD VSS / ++ RSC_IHPSG13_NAND3X2 +XB_DEC3<20> B_P1<1> B_N0<1> B_ADDR_DEC<4> net041<11> VDD VSS / ++ RSC_IHPSG13_NAND3X2 +XB_DEC3<19> B_P1<1> B_N0<1> B_ADDR_DEC<3> net041<12> VDD VSS / ++ RSC_IHPSG13_NAND3X2 +XB_DEC3<18> B_P1<1> B_N0<1> B_ADDR_DEC<2> net041<13> VDD VSS / ++ RSC_IHPSG13_NAND3X2 +XB_DEC3<17> B_P1<1> B_N0<1> B_ADDR_DEC<1> net041<14> VDD VSS / ++ RSC_IHPSG13_NAND3X2 +XB_DEC3<16> B_P1<1> B_N0<1> B_ADDR_DEC<0> net041<15> VDD VSS / ++ RSC_IHPSG13_NAND3X2 +XB_DEC3<15> B_N1<0> B_P0<0> B_ADDR_DEC<7> net041<16> VDD VSS / ++ RSC_IHPSG13_NAND3X2 +XB_DEC3<14> B_N1<0> B_P0<0> B_ADDR_DEC<6> net041<17> VDD VSS / ++ RSC_IHPSG13_NAND3X2 +XB_DEC3<13> B_N1<0> B_P0<0> B_ADDR_DEC<5> net041<18> VDD VSS / ++ RSC_IHPSG13_NAND3X2 +XB_DEC3<12> B_N1<0> B_P0<0> B_ADDR_DEC<4> net041<19> VDD VSS / ++ RSC_IHPSG13_NAND3X2 +XB_DEC3<11> B_N1<0> B_P0<0> B_ADDR_DEC<3> net041<20> VDD VSS / ++ RSC_IHPSG13_NAND3X2 +XB_DEC3<10> B_N1<0> B_P0<0> B_ADDR_DEC<2> net041<21> VDD VSS / ++ RSC_IHPSG13_NAND3X2 +XB_DEC3<9> B_N1<0> B_P0<0> B_ADDR_DEC<1> net041<22> VDD VSS / ++ RSC_IHPSG13_NAND3X2 +XB_DEC3<8> B_N1<0> B_P0<0> B_ADDR_DEC<0> net041<23> VDD VSS / ++ RSC_IHPSG13_NAND3X2 +XB_DEC3<7> B_N1<0> B_N0<0> B_ADDR_DEC<7> net041<24> VDD VSS / ++ RSC_IHPSG13_NAND3X2 +XB_DEC3<6> B_N1<0> B_N0<0> B_ADDR_DEC<6> net041<25> VDD VSS / ++ RSC_IHPSG13_NAND3X2 +XB_DEC3<5> B_N1<0> B_N0<0> B_ADDR_DEC<5> net041<26> VDD VSS / ++ RSC_IHPSG13_NAND3X2 +XB_DEC3<4> B_N1<0> B_N0<0> B_ADDR_DEC<4> net041<27> VDD VSS / ++ RSC_IHPSG13_NAND3X2 +XB_DEC3<3> B_N1<0> B_N0<0> B_ADDR_DEC<3> net041<28> VDD VSS / ++ RSC_IHPSG13_NAND3X2 +XB_DEC3<2> B_N1<0> B_N0<0> B_ADDR_DEC<2> net041<29> VDD VSS / ++ RSC_IHPSG13_NAND3X2 +XB_DEC3<1> B_N1<0> B_N0<0> B_ADDR_DEC<1> net041<30> VDD VSS / ++ RSC_IHPSG13_NAND3X2 +XB_DEC3<0> B_N1<0> B_N0<0> B_ADDR_DEC<0> net041<31> VDD VSS / ++ RSC_IHPSG13_NAND3X2 +XA_DEC3<31> A_P1<1> A_P0<1> A_ADDR_DEC<7> net23<0> VDD VSS / ++ RSC_IHPSG13_NAND3X2 +XA_DEC3<30> A_P1<1> A_P0<1> A_ADDR_DEC<6> net23<1> VDD VSS / ++ RSC_IHPSG13_NAND3X2 +XA_DEC3<29> A_P1<1> A_P0<1> A_ADDR_DEC<5> net23<2> VDD VSS / ++ RSC_IHPSG13_NAND3X2 +XA_DEC3<28> A_P1<1> A_P0<1> A_ADDR_DEC<4> net23<3> VDD VSS / ++ RSC_IHPSG13_NAND3X2 +XA_DEC3<27> A_P1<1> A_P0<1> A_ADDR_DEC<3> net23<4> VDD VSS / ++ RSC_IHPSG13_NAND3X2 +XA_DEC3<26> A_P1<1> A_P0<1> A_ADDR_DEC<2> net23<5> VDD VSS / ++ RSC_IHPSG13_NAND3X2 +XA_DEC3<25> A_P1<1> A_P0<1> A_ADDR_DEC<1> net23<6> VDD VSS / ++ RSC_IHPSG13_NAND3X2 +XA_DEC3<24> A_P1<1> A_P0<1> A_ADDR_DEC<0> net23<7> VDD VSS / ++ RSC_IHPSG13_NAND3X2 +XA_DEC3<23> A_P1<1> A_N0<1> A_ADDR_DEC<7> net23<8> VDD VSS / ++ RSC_IHPSG13_NAND3X2 +XA_DEC3<22> A_P1<1> A_N0<1> A_ADDR_DEC<6> net23<9> VDD VSS / ++ RSC_IHPSG13_NAND3X2 +XA_DEC3<21> A_P1<1> A_N0<1> A_ADDR_DEC<5> net23<10> VDD VSS / ++ RSC_IHPSG13_NAND3X2 +XA_DEC3<20> A_P1<1> A_N0<1> A_ADDR_DEC<4> net23<11> VDD VSS / ++ RSC_IHPSG13_NAND3X2 +XA_DEC3<19> A_P1<1> A_N0<1> A_ADDR_DEC<3> net23<12> VDD VSS / ++ RSC_IHPSG13_NAND3X2 +XA_DEC3<18> A_P1<1> A_N0<1> A_ADDR_DEC<2> net23<13> VDD VSS / ++ RSC_IHPSG13_NAND3X2 +XA_DEC3<17> A_P1<1> A_N0<1> A_ADDR_DEC<1> net23<14> VDD VSS / ++ RSC_IHPSG13_NAND3X2 +XA_DEC3<16> A_P1<1> A_N0<1> A_ADDR_DEC<0> net23<15> VDD VSS / ++ RSC_IHPSG13_NAND3X2 +XA_DEC3<15> A_N1<0> A_P0<0> A_ADDR_DEC<7> net23<16> VDD VSS / ++ RSC_IHPSG13_NAND3X2 +XA_DEC3<14> A_N1<0> A_P0<0> A_ADDR_DEC<6> net23<17> VDD VSS / ++ RSC_IHPSG13_NAND3X2 +XA_DEC3<13> A_N1<0> A_P0<0> A_ADDR_DEC<5> net23<18> VDD VSS / ++ RSC_IHPSG13_NAND3X2 +XA_DEC3<12> A_N1<0> A_P0<0> A_ADDR_DEC<4> net23<19> VDD VSS / ++ RSC_IHPSG13_NAND3X2 +XA_DEC3<11> A_N1<0> A_P0<0> A_ADDR_DEC<3> net23<20> VDD VSS / ++ RSC_IHPSG13_NAND3X2 +XA_DEC3<10> A_N1<0> A_P0<0> A_ADDR_DEC<2> net23<21> VDD VSS / ++ RSC_IHPSG13_NAND3X2 +XA_DEC3<9> A_N1<0> A_P0<0> A_ADDR_DEC<1> net23<22> VDD VSS / ++ RSC_IHPSG13_NAND3X2 +XA_DEC3<8> A_N1<0> A_P0<0> A_ADDR_DEC<0> net23<23> VDD VSS / ++ RSC_IHPSG13_NAND3X2 +XA_DEC3<7> A_N1<0> A_N0<0> A_ADDR_DEC<7> net23<24> VDD VSS / ++ RSC_IHPSG13_NAND3X2 +XA_DEC3<6> A_N1<0> A_N0<0> A_ADDR_DEC<6> net23<25> VDD VSS / ++ RSC_IHPSG13_NAND3X2 +XA_DEC3<5> A_N1<0> A_N0<0> A_ADDR_DEC<5> net23<26> VDD VSS / ++ RSC_IHPSG13_NAND3X2 +XA_DEC3<4> A_N1<0> A_N0<0> A_ADDR_DEC<4> net23<27> VDD VSS / ++ RSC_IHPSG13_NAND3X2 +XA_DEC3<3> A_N1<0> A_N0<0> A_ADDR_DEC<3> net23<28> VDD VSS / ++ RSC_IHPSG13_NAND3X2 +XA_DEC3<2> A_N1<0> A_N0<0> A_ADDR_DEC<2> net23<29> VDD VSS / ++ RSC_IHPSG13_NAND3X2 +XA_DEC3<1> A_N1<0> A_N0<0> A_ADDR_DEC<1> net23<30> VDD VSS / ++ RSC_IHPSG13_NAND3X2 +XA_DEC3<0> A_N1<0> A_N0<0> A_ADDR_DEC<0> net23<31> VDD VSS / ++ RSC_IHPSG13_NAND3X2 +XB_I89 B_DCLK_B_L B_DCLK_B_R / RSC_IHPSG13_MET3RES +XB_I91 B_RCLK_B_L B_RCLK_B_R / RSC_IHPSG13_MET3RES +XB_I90 B_WCLK_B_L B_WCLK_B_R / RSC_IHPSG13_MET3RES +XB_I88 B_DCLK_L B_DCLK_R / RSC_IHPSG13_MET3RES +XB_I87 B_WCLK_L B_WCLK_R / RSC_IHPSG13_MET3RES +XB_R2 B_RCLK_L B_RCLK_R / RSC_IHPSG13_MET3RES +XA_I89 A_DCLK_B_L A_DCLK_B_R / RSC_IHPSG13_MET3RES +XA_I91 A_RCLK_B_L A_RCLK_B_R / RSC_IHPSG13_MET3RES +XA_I90 A_WCLK_B_L A_WCLK_B_R / RSC_IHPSG13_MET3RES +XA_I88 A_DCLK_L A_DCLK_R / RSC_IHPSG13_MET3RES +XA_I87 A_WCLK_L A_WCLK_R / RSC_IHPSG13_MET3RES +XA_R2 A_RCLK_L A_RCLK_R / RSC_IHPSG13_MET3RES +XB_BM_TIEH B_TIEH_O VDD VSS / RSC_IHPSG13_TIEH +XA_BM_TIEH A_TIEH_O VDD VSS / RSC_IHPSG13_TIEH +.ENDS +.SUBCKT RM_IHPSG13_1024x32_c2_2P_COLDRV13_FILL4 VDD VSS +XI0<11> VDD VSS / RSC_IHPSG13_FILLCAP4 +XI0<10> VDD VSS / RSC_IHPSG13_FILLCAP4 +XI0<9> VDD VSS / RSC_IHPSG13_FILLCAP4 +XI0<8> VDD VSS / RSC_IHPSG13_FILLCAP4 +XI0<7> VDD VSS / RSC_IHPSG13_FILLCAP4 +XI0<6> VDD VSS / RSC_IHPSG13_FILLCAP4 +XI0<5> VDD VSS / RSC_IHPSG13_FILLCAP4 +XI0<4> VDD VSS / RSC_IHPSG13_FILLCAP4 +XI0<3> VDD VSS / RSC_IHPSG13_FILLCAP4 +XI0<2> VDD VSS / RSC_IHPSG13_FILLCAP4 +XI0<1> VDD VSS / RSC_IHPSG13_FILLCAP4 +.ENDS + + +.SUBCKT RSC_IHPSG13_CBUFX16 A Z VDD VSS +MN0 net4 A VSS VSS sg13_lv_nmos m=1 w=2.115u l=130.00n ng=3 nrd=0 nrs=0 +MN1 Z net4 VSS VSS sg13_lv_nmos m=1 w=5.64u l=130.00n ng=8 nrd=0 nrs=0 +MP1 Z net4 VDD VDD sg13_lv_pmos m=1 w=13.000u l=130.00n ng=8 nrd=0 ++ nrs=0 +MP0 net4 A VDD VDD sg13_lv_pmos m=1 w=4.89u l=130.00n ng=3 nrd=0 nrs=0 +.ENDS +.SUBCKT RM_IHPSG13_1024x32_c2_1P_COLDRV13X16 ADDR_COL_I<1> ADDR_COL_I<0> ADDR_COL_O<1> ++ ADDR_COL_O<0> ADDR_DEC_I<7> ADDR_DEC_I<6> ADDR_DEC_I<5> ADDR_DEC_I<4> ++ ADDR_DEC_I<3> ADDR_DEC_I<2> ADDR_DEC_I<1> ADDR_DEC_I<0> ADDR_DEC_O<7> ++ ADDR_DEC_O<6> ADDR_DEC_O<5> ADDR_DEC_O<4> ADDR_DEC_O<3> ADDR_DEC_O<2> ++ ADDR_DEC_O<1> ADDR_DEC_O<0> DCLK_I DCLK_O RCLK_I RCLK_O WCLK_I WCLK_O ++ VDD VSS +XI1<1> VDD VSS / RSC_IHPSG13_FILLCAP4 +XI1<0> VDD VSS / RSC_IHPSG13_FILLCAP4 +XI0<3> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI0<2> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI0<1> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI0<0> VDD VSS / RSC_IHPSG13_FILLCAP8 +XADDR_COL_DRV<1> ADDR_COL_I<1> ADDR_COL_O<1> VDD VSS / ++ RSC_IHPSG13_CBUFX16 +XADDR_COL_DRV<0> ADDR_COL_I<0> ADDR_COL_O<0> VDD VSS / ++ RSC_IHPSG13_CBUFX16 +XADDR_DEC_DRV<7> ADDR_DEC_I<7> ADDR_DEC_O<7> VDD VSS / ++ RSC_IHPSG13_CBUFX16 +XADDR_DEC_DRV<6> ADDR_DEC_I<6> ADDR_DEC_O<6> VDD VSS / ++ RSC_IHPSG13_CBUFX16 +XADDR_DEC_DRV<5> ADDR_DEC_I<5> ADDR_DEC_O<5> VDD VSS / ++ RSC_IHPSG13_CBUFX16 +XADDR_DEC_DRV<4> ADDR_DEC_I<4> ADDR_DEC_O<4> VDD VSS / ++ RSC_IHPSG13_CBUFX16 +XADDR_DEC_DRV<3> ADDR_DEC_I<3> ADDR_DEC_O<3> VDD VSS / ++ RSC_IHPSG13_CBUFX16 +XADDR_DEC_DRV<2> ADDR_DEC_I<2> ADDR_DEC_O<2> VDD VSS / ++ RSC_IHPSG13_CBUFX16 +XADDR_DEC_DRV<1> ADDR_DEC_I<1> ADDR_DEC_O<1> VDD VSS / ++ RSC_IHPSG13_CBUFX16 +XADDR_DEC_DRV<0> ADDR_DEC_I<0> ADDR_DEC_O<0> VDD VSS / ++ RSC_IHPSG13_CBUFX16 +XDCLK_DRV DCLK_I DCLK_O VDD VSS / RSC_IHPSG13_CBUFX16 +XRCLK_DRV RCLK_I RCLK_O VDD VSS / RSC_IHPSG13_CBUFX16 +XWCLK_DRV WCLK_I WCLK_O VDD VSS / RSC_IHPSG13_CBUFX16 +.ENDS +.SUBCKT RSC_IHPSG13_WLDRVX16 A Z VDD VSS +MN1 Z net6 VSS VSS sg13_lv_nmos m=1 w=1.41u l=130.00n ng=2 nrd=0 nrs=0 +MN0 net6 A VSS VSS sg13_lv_nmos m=1 w=1.8u l=130.00n ng=2 nrd=0 nrs=0 +MP1 Z net6 VDD VDD sg13_lv_pmos m=1 w=12.96u l=130.00n ng=8 nrd=0 nrs=0 +MP0 net6 A VDD VDD sg13_lv_pmos m=1 w=900.0n l=130.00n ng=1 nrd=0 nrs=0 +.ENDS +.SUBCKT RM_IHPSG13_1024x32_c2_1P_WLDRV16X16 A<15> A<14> A<13> A<12> A<11> A<10> A<9> A<8> ++ A<7> A<6> A<5> A<4> A<3> A<2> A<1> A<0> Z<15> Z<14> Z<13> Z<12> Z<11> Z<10> ++ Z<9> Z<8> Z<7> Z<6> Z<5> Z<4> Z<3> Z<2> Z<1> Z<0> VDD VSS +XBUF<15> A<15> Z<15> VDD VSS / RSC_IHPSG13_WLDRVX16 +XBUF<14> A<14> Z<14> VDD VSS / RSC_IHPSG13_WLDRVX16 +XBUF<13> A<13> Z<13> VDD VSS / RSC_IHPSG13_WLDRVX16 +XBUF<12> A<12> Z<12> VDD VSS / RSC_IHPSG13_WLDRVX16 +XBUF<11> A<11> Z<11> VDD VSS / RSC_IHPSG13_WLDRVX16 +XBUF<10> A<10> Z<10> VDD VSS / RSC_IHPSG13_WLDRVX16 +XBUF<9> A<9> Z<9> VDD VSS / RSC_IHPSG13_WLDRVX16 +XBUF<8> A<8> Z<8> VDD VSS / RSC_IHPSG13_WLDRVX16 +XBUF<7> A<7> Z<7> VDD VSS / RSC_IHPSG13_WLDRVX16 +XBUF<6> A<6> Z<6> VDD VSS / RSC_IHPSG13_WLDRVX16 +XBUF<5> A<5> Z<5> VDD VSS / RSC_IHPSG13_WLDRVX16 +XBUF<4> A<4> Z<4> VDD VSS / RSC_IHPSG13_WLDRVX16 +XBUF<3> A<3> Z<3> VDD VSS / RSC_IHPSG13_WLDRVX16 +XBUF<2> A<2> Z<2> VDD VSS / RSC_IHPSG13_WLDRVX16 +XBUF<1> A<1> Z<1> VDD VSS / RSC_IHPSG13_WLDRVX16 +XBUF<0> A<0> Z<0> VDD VSS / RSC_IHPSG13_WLDRVX16 +.ENDS + + +.SUBCKT RM_IHPSG13_1024x32_c2_2P_COLDRV13X4 ADDR_COL_I<1> ADDR_COL_I<0> ADDR_COL_O<1> ++ ADDR_COL_O<0> ADDR_DEC_I<7> ADDR_DEC_I<6> ADDR_DEC_I<5> ADDR_DEC_I<4> ++ ADDR_DEC_I<3> ADDR_DEC_I<2> ADDR_DEC_I<1> ADDR_DEC_I<0> ADDR_DEC_O<7> ++ ADDR_DEC_O<6> ADDR_DEC_O<5> ADDR_DEC_O<4> ADDR_DEC_O<3> ADDR_DEC_O<2> ++ ADDR_DEC_O<1> ADDR_DEC_O<0> DCLK_I DCLK_O RCLK_I RCLK_O WCLK_I WCLK_O ++ VDD VSS +XWCLK_DRV WCLK_I WCLK_O VDD VSS / RSC_IHPSG13_CBUFX4 +XRCLK_DRV RCLK_I RCLK_O VDD VSS / RSC_IHPSG13_CBUFX4 +XDCLK_DRV DCLK_I DCLK_O VDD VSS / RSC_IHPSG13_CBUFX4 +XADDR_COL_DRV<1> ADDR_COL_I<1> ADDR_COL_O<1> VDD VSS / ++ RSC_IHPSG13_CBUFX4 +XADDR_COL_DRV<0> ADDR_COL_I<0> ADDR_COL_O<0> VDD VSS / ++ RSC_IHPSG13_CBUFX4 +XADDR_DEC_DRV<7> ADDR_DEC_I<7> ADDR_DEC_O<7> VDD VSS / ++ RSC_IHPSG13_CBUFX4 +XADDR_DEC_DRV<6> ADDR_DEC_I<6> ADDR_DEC_O<6> VDD VSS / ++ RSC_IHPSG13_CBUFX4 +XADDR_DEC_DRV<5> ADDR_DEC_I<5> ADDR_DEC_O<5> VDD VSS / ++ RSC_IHPSG13_CBUFX4 +XADDR_DEC_DRV<4> ADDR_DEC_I<4> ADDR_DEC_O<4> VDD VSS / ++ RSC_IHPSG13_CBUFX4 +XADDR_DEC_DRV<3> ADDR_DEC_I<3> ADDR_DEC_O<3> VDD VSS / ++ RSC_IHPSG13_CBUFX4 +XADDR_DEC_DRV<2> ADDR_DEC_I<2> ADDR_DEC_O<2> VDD VSS / ++ RSC_IHPSG13_CBUFX4 +XADDR_DEC_DRV<1> ADDR_DEC_I<1> ADDR_DEC_O<1> VDD VSS / ++ RSC_IHPSG13_CBUFX4 +XADDR_DEC_DRV<0> ADDR_DEC_I<0> ADDR_DEC_O<0> VDD VSS / ++ RSC_IHPSG13_CBUFX4 +XI0<6> VDD VSS / RSC_IHPSG13_FILLCAP4 +XI0<5> VDD VSS / RSC_IHPSG13_FILLCAP4 +XI0<4> VDD VSS / RSC_IHPSG13_FILLCAP4 +XI0<3> VDD VSS / RSC_IHPSG13_FILLCAP4 +XI0<2> VDD VSS / RSC_IHPSG13_FILLCAP4 +XI0<1> VDD VSS / RSC_IHPSG13_FILLCAP4 +XI1 VDD VSS / RSC_IHPSG13_FILLCAP8 +.ENDS +.SUBCKT RM_IHPSG13_1024x32_c2_2P_WLDRV16X4 A<15> A<14> A<13> A<12> A<11> A<10> A<9> A<8> ++ A<7> A<6> A<5> A<4> A<3> A<2> A<1> A<0> Z<15> Z<14> Z<13> Z<12> Z<11> Z<10> ++ Z<9> Z<8> Z<7> Z<6> Z<5> Z<4> Z<3> Z<2> Z<1> Z<0> VDD VSS +XBUF<15> A<15> Z<15> VDD VSS / RSC_IHPSG13_WLDRVX4 +XBUF<14> A<14> Z<14> VDD VSS / RSC_IHPSG13_WLDRVX4 +XBUF<13> A<13> Z<13> VDD VSS / RSC_IHPSG13_WLDRVX4 +XBUF<12> A<12> Z<12> VDD VSS / RSC_IHPSG13_WLDRVX4 +XBUF<11> A<11> Z<11> VDD VSS / RSC_IHPSG13_WLDRVX4 +XBUF<10> A<10> Z<10> VDD VSS / RSC_IHPSG13_WLDRVX4 +XBUF<9> A<9> Z<9> VDD VSS / RSC_IHPSG13_WLDRVX4 +XBUF<8> A<8> Z<8> VDD VSS / RSC_IHPSG13_WLDRVX4 +XBUF<7> A<7> Z<7> VDD VSS / RSC_IHPSG13_WLDRVX4 +XBUF<6> A<6> Z<6> VDD VSS / RSC_IHPSG13_WLDRVX4 +XBUF<5> A<5> Z<5> VDD VSS / RSC_IHPSG13_WLDRVX4 +XBUF<4> A<4> Z<4> VDD VSS / RSC_IHPSG13_WLDRVX4 +XBUF<3> A<3> Z<3> VDD VSS / RSC_IHPSG13_WLDRVX4 +XBUF<2> A<2> Z<2> VDD VSS / RSC_IHPSG13_WLDRVX4 +XBUF<1> A<1> Z<1> VDD VSS / RSC_IHPSG13_WLDRVX4 +XBUF<0> A<0> Z<0> VDD VSS / RSC_IHPSG13_WLDRVX4 +.ENDS +.SUBCKT RM_IHPSG13_1024x32_c2_2P_ROWDEC8 ADDR_N_I<7> ADDR_N_I<6> ADDR_N_I<5> ADDR_N_I<4> ++ ADDR_N_I<3> ADDR_N_I<2> ADDR_N_I<1> ADDR_N_I<0> CS_I ECLK_I WL_O<255> ++ WL_O<254> WL_O<253> WL_O<252> WL_O<251> WL_O<250> WL_O<249> WL_O<248> ++ WL_O<247> WL_O<246> WL_O<245> WL_O<244> WL_O<243> WL_O<242> WL_O<241> ++ WL_O<240> WL_O<239> WL_O<238> WL_O<237> WL_O<236> WL_O<235> WL_O<234> ++ WL_O<233> WL_O<232> WL_O<231> WL_O<230> WL_O<229> WL_O<228> WL_O<227> ++ WL_O<226> WL_O<225> WL_O<224> WL_O<223> WL_O<222> WL_O<221> WL_O<220> ++ WL_O<219> WL_O<218> WL_O<217> WL_O<216> WL_O<215> WL_O<214> WL_O<213> ++ WL_O<212> WL_O<211> WL_O<210> WL_O<209> WL_O<208> WL_O<207> WL_O<206> ++ WL_O<205> WL_O<204> WL_O<203> WL_O<202> WL_O<201> WL_O<200> WL_O<199> ++ WL_O<198> WL_O<197> WL_O<196> WL_O<195> WL_O<194> WL_O<193> WL_O<192> ++ WL_O<191> WL_O<190> WL_O<189> WL_O<188> WL_O<187> WL_O<186> WL_O<185> ++ WL_O<184> WL_O<183> WL_O<182> WL_O<181> WL_O<180> WL_O<179> WL_O<178> ++ WL_O<177> WL_O<176> WL_O<175> WL_O<174> WL_O<173> WL_O<172> WL_O<171> ++ WL_O<170> WL_O<169> WL_O<168> WL_O<167> WL_O<166> WL_O<165> WL_O<164> ++ WL_O<163> WL_O<162> WL_O<161> WL_O<160> WL_O<159> WL_O<158> WL_O<157> ++ WL_O<156> WL_O<155> WL_O<154> WL_O<153> WL_O<152> WL_O<151> WL_O<150> ++ WL_O<149> WL_O<148> WL_O<147> WL_O<146> WL_O<145> WL_O<144> WL_O<143> ++ WL_O<142> WL_O<141> WL_O<140> WL_O<139> WL_O<138> WL_O<137> WL_O<136> ++ WL_O<135> WL_O<134> WL_O<133> WL_O<132> WL_O<131> WL_O<130> WL_O<129> ++ WL_O<128> WL_O<127> WL_O<126> WL_O<125> WL_O<124> WL_O<123> WL_O<122> ++ WL_O<121> WL_O<120> WL_O<119> WL_O<118> WL_O<117> WL_O<116> WL_O<115> ++ WL_O<114> WL_O<113> WL_O<112> WL_O<111> WL_O<110> WL_O<109> WL_O<108> ++ WL_O<107> WL_O<106> WL_O<105> WL_O<104> WL_O<103> WL_O<102> WL_O<101> ++ WL_O<100> WL_O<99> WL_O<98> WL_O<97> WL_O<96> WL_O<95> WL_O<94> WL_O<93> ++ WL_O<92> WL_O<91> WL_O<90> WL_O<89> WL_O<88> WL_O<87> WL_O<86> WL_O<85> ++ WL_O<84> WL_O<83> WL_O<82> WL_O<81> WL_O<80> WL_O<79> WL_O<78> WL_O<77> ++ WL_O<76> WL_O<75> WL_O<74> WL_O<73> WL_O<72> WL_O<71> WL_O<70> WL_O<69> ++ WL_O<68> WL_O<67> WL_O<66> WL_O<65> WL_O<64> WL_O<63> WL_O<62> WL_O<61> ++ WL_O<60> WL_O<59> WL_O<58> WL_O<57> WL_O<56> WL_O<55> WL_O<54> WL_O<53> ++ WL_O<52> WL_O<51> WL_O<50> WL_O<49> WL_O<48> WL_O<47> WL_O<46> WL_O<45> ++ WL_O<44> WL_O<43> WL_O<42> WL_O<41> WL_O<40> WL_O<39> WL_O<38> WL_O<37> ++ WL_O<36> WL_O<35> WL_O<34> WL_O<33> WL_O<32> WL_O<31> WL_O<30> WL_O<29> ++ WL_O<28> WL_O<27> WL_O<26> WL_O<25> WL_O<24> WL_O<23> WL_O<22> WL_O<21> ++ WL_O<20> WL_O<19> WL_O<18> WL_O<17> WL_O<16> WL_O<15> WL_O<14> WL_O<13> ++ WL_O<12> WL_O<11> WL_O<10> WL_O<9> WL_O<8> WL_O<7> WL_O<6> WL_O<5> WL_O<4> ++ WL_O<3> WL_O<2> WL_O<1> WL_O<0> VDD VSS +XDEC11<4> ADDR_N_I<7> ADDR_N_I<6> CS_I CS04<3> VDD VSS / ++ RM_IHPSG13_1024x32_c2_2P_DEC03 +XDEC11<3> ADDR_N_I<5> ADDR_N_I<4> CS04<3> CS00<15> VDD VSS / ++ RM_IHPSG13_1024x32_c2_2P_DEC03 +XDEC11<2> ADDR_N_I<5> ADDR_N_I<4> CS04<2> CS00<11> VDD VSS / ++ RM_IHPSG13_1024x32_c2_2P_DEC03 +XDEC11<1> ADDR_N_I<5> ADDR_N_I<4> CS04<1> CS00<7> VDD VSS / ++ RM_IHPSG13_1024x32_c2_2P_DEC03 +XDEC11<0> ADDR_N_I<5> ADDR_N_I<4> CS04<0> CS00<3> VDD VSS / ++ RM_IHPSG13_1024x32_c2_2P_DEC03 +XSEL<15> ADDR_N_I<3> ADDR_N_I<2> ADDR_N_I<1> ADDR_N_I<0> CS00<15> ECLK_H<15> ++ ECLK_H<16> ECLK_B<15> ECLK_B<16> WL_O<255> WL_O<254> WL_O<253> WL_O<252> ++ WL_O<251> WL_O<250> WL_O<249> WL_O<248> WL_O<247> WL_O<246> WL_O<245> ++ WL_O<244> WL_O<243> WL_O<242> WL_O<241> WL_O<240> VDD VSS / ++ RM_IHPSG13_1024x32_c2_2P_DEC04 +XSEL<14> ADDR_N_I<3> ADDR_N_I<2> ADDR_N_I<1> ADDR_N_I<0> CS00<14> ECLK_H<14> ++ ECLK_H<15> ECLK_B<14> ECLK_B<15> WL_O<239> WL_O<238> WL_O<237> WL_O<236> ++ WL_O<235> WL_O<234> WL_O<233> WL_O<232> WL_O<231> WL_O<230> WL_O<229> ++ WL_O<228> WL_O<227> WL_O<226> WL_O<225> WL_O<224> VDD VSS / ++ RM_IHPSG13_1024x32_c2_2P_DEC04 +XSEL<13> ADDR_N_I<3> ADDR_N_I<2> ADDR_N_I<1> ADDR_N_I<0> CS00<13> ECLK_H<13> ++ ECLK_H<14> ECLK_B<13> ECLK_B<14> WL_O<223> WL_O<222> WL_O<221> WL_O<220> ++ WL_O<219> WL_O<218> WL_O<217> WL_O<216> WL_O<215> WL_O<214> WL_O<213> ++ WL_O<212> WL_O<211> WL_O<210> WL_O<209> WL_O<208> VDD VSS / ++ RM_IHPSG13_1024x32_c2_2P_DEC04 +XSEL<12> ADDR_N_I<3> ADDR_N_I<2> ADDR_N_I<1> ADDR_N_I<0> CS00<12> ECLK_H<12> ++ ECLK_H<13> ECLK_B<12> ECLK_B<13> WL_O<207> WL_O<206> WL_O<205> WL_O<204> ++ WL_O<203> WL_O<202> WL_O<201> WL_O<200> WL_O<199> WL_O<198> WL_O<197> ++ WL_O<196> WL_O<195> WL_O<194> WL_O<193> WL_O<192> VDD VSS / ++ RM_IHPSG13_1024x32_c2_2P_DEC04 +XSEL<11> ADDR_N_I<3> ADDR_N_I<2> ADDR_N_I<1> ADDR_N_I<0> CS00<11> ECLK_H<11> ++ ECLK_H<12> ECLK_B<11> ECLK_B<12> WL_O<191> WL_O<190> WL_O<189> WL_O<188> ++ WL_O<187> WL_O<186> WL_O<185> WL_O<184> WL_O<183> WL_O<182> WL_O<181> ++ WL_O<180> WL_O<179> WL_O<178> WL_O<177> WL_O<176> VDD VSS / ++ RM_IHPSG13_1024x32_c2_2P_DEC04 +XSEL<10> ADDR_N_I<3> ADDR_N_I<2> ADDR_N_I<1> ADDR_N_I<0> CS00<10> ECLK_H<10> ++ ECLK_H<11> ECLK_B<10> ECLK_B<11> WL_O<175> WL_O<174> WL_O<173> WL_O<172> ++ WL_O<171> WL_O<170> WL_O<169> WL_O<168> WL_O<167> WL_O<166> WL_O<165> ++ WL_O<164> WL_O<163> WL_O<162> WL_O<161> WL_O<160> VDD VSS / ++ RM_IHPSG13_1024x32_c2_2P_DEC04 +XSEL<9> ADDR_N_I<3> ADDR_N_I<2> ADDR_N_I<1> ADDR_N_I<0> CS00<9> ECLK_H<9> ++ ECLK_H<10> ECLK_B<9> ECLK_B<10> WL_O<159> WL_O<158> WL_O<157> WL_O<156> ++ WL_O<155> WL_O<154> WL_O<153> WL_O<152> WL_O<151> WL_O<150> WL_O<149> ++ WL_O<148> WL_O<147> WL_O<146> WL_O<145> WL_O<144> VDD VSS / ++ RM_IHPSG13_1024x32_c2_2P_DEC04 +XSEL<8> ADDR_N_I<3> ADDR_N_I<2> ADDR_N_I<1> ADDR_N_I<0> CS00<8> ECLK_H<8> ++ ECLK_H<9> ECLK_B<8> ECLK_B<9> WL_O<143> WL_O<142> WL_O<141> WL_O<140> ++ WL_O<139> WL_O<138> WL_O<137> WL_O<136> WL_O<135> WL_O<134> WL_O<133> ++ WL_O<132> WL_O<131> WL_O<130> WL_O<129> WL_O<128> VDD VSS / ++ RM_IHPSG13_1024x32_c2_2P_DEC04 +XSEL<7> ADDR_N_I<3> ADDR_N_I<2> ADDR_N_I<1> ADDR_N_I<0> CS00<7> ECLK_H<7> ++ ECLK_H<8> ECLK_B<7> ECLK_B<8> WL_O<127> WL_O<126> WL_O<125> WL_O<124> ++ WL_O<123> WL_O<122> WL_O<121> WL_O<120> WL_O<119> WL_O<118> WL_O<117> ++ WL_O<116> WL_O<115> WL_O<114> WL_O<113> WL_O<112> VDD VSS / ++ RM_IHPSG13_1024x32_c2_2P_DEC04 +XSEL<6> ADDR_N_I<3> ADDR_N_I<2> ADDR_N_I<1> ADDR_N_I<0> CS00<6> ECLK_H<6> ++ ECLK_H<7> ECLK_B<6> ECLK_B<7> WL_O<111> WL_O<110> WL_O<109> WL_O<108> ++ WL_O<107> WL_O<106> WL_O<105> WL_O<104> WL_O<103> WL_O<102> WL_O<101> ++ WL_O<100> WL_O<99> WL_O<98> WL_O<97> WL_O<96> VDD VSS / ++ RM_IHPSG13_1024x32_c2_2P_DEC04 +XSEL<5> ADDR_N_I<3> ADDR_N_I<2> ADDR_N_I<1> ADDR_N_I<0> CS00<5> ECLK_H<5> ++ ECLK_H<6> ECLK_B<5> ECLK_B<6> WL_O<95> WL_O<94> WL_O<93> WL_O<92> WL_O<91> ++ WL_O<90> WL_O<89> WL_O<88> WL_O<87> WL_O<86> WL_O<85> WL_O<84> WL_O<83> ++ WL_O<82> WL_O<81> WL_O<80> VDD VSS / RM_IHPSG13_1024x32_c2_2P_DEC04 +XSEL<4> ADDR_N_I<3> ADDR_N_I<2> ADDR_N_I<1> ADDR_N_I<0> CS00<4> ECLK_H<4> ++ ECLK_H<5> ECLK_B<4> ECLK_B<5> WL_O<79> WL_O<78> WL_O<77> WL_O<76> WL_O<75> ++ WL_O<74> WL_O<73> WL_O<72> WL_O<71> WL_O<70> WL_O<69> WL_O<68> WL_O<67> ++ WL_O<66> WL_O<65> WL_O<64> VDD VSS / RM_IHPSG13_1024x32_c2_2P_DEC04 +XSEL<3> ADDR_N_I<3> ADDR_N_I<2> ADDR_N_I<1> ADDR_N_I<0> CS00<3> ECLK_H<3> ++ ECLK_H<4> ECLK_B<3> ECLK_B<4> WL_O<63> WL_O<62> WL_O<61> WL_O<60> WL_O<59> ++ WL_O<58> WL_O<57> WL_O<56> WL_O<55> WL_O<54> WL_O<53> WL_O<52> WL_O<51> ++ WL_O<50> WL_O<49> WL_O<48> VDD VSS / RM_IHPSG13_1024x32_c2_2P_DEC04 +XSEL<2> ADDR_N_I<3> ADDR_N_I<2> ADDR_N_I<1> ADDR_N_I<0> CS00<2> ECLK_H<2> ++ ECLK_H<3> ECLK_B<2> ECLK_B<3> WL_O<47> WL_O<46> WL_O<45> WL_O<44> WL_O<43> ++ WL_O<42> WL_O<41> WL_O<40> WL_O<39> WL_O<38> WL_O<37> WL_O<36> WL_O<35> ++ WL_O<34> WL_O<33> WL_O<32> VDD VSS / RM_IHPSG13_1024x32_c2_2P_DEC04 +XSEL<1> ADDR_N_I<3> ADDR_N_I<2> ADDR_N_I<1> ADDR_N_I<0> CS00<1> ECLK_H<1> ++ ECLK_H<2> ECLK_B<1> ECLK_B<2> WL_O<31> WL_O<30> WL_O<29> WL_O<28> WL_O<27> ++ WL_O<26> WL_O<25> WL_O<24> WL_O<23> WL_O<22> WL_O<21> WL_O<20> WL_O<19> ++ WL_O<18> WL_O<17> WL_O<16> VDD VSS / RM_IHPSG13_1024x32_c2_2P_DEC04 +XSEL<0> ADDR_N_I<3> ADDR_N_I<2> ADDR_N_I<1> ADDR_N_I<0> CS00<0> ECLK_I ++ ECLK_H<1> ECLK_B<0> ECLK_B<1> WL_O<15> WL_O<14> WL_O<13> WL_O<12> WL_O<11> ++ WL_O<10> WL_O<9> WL_O<8> WL_O<7> WL_O<6> WL_O<5> WL_O<4> WL_O<3> WL_O<2> ++ WL_O<1> WL_O<0> VDD VSS / RM_IHPSG13_1024x32_c2_2P_DEC04 +XDEC10<4> ADDR_N_I<7> ADDR_N_I<6> CS_I CS04<2> VDD VSS / ++ RM_IHPSG13_1024x32_c2_2P_DEC02 +XDEC10<3> ADDR_N_I<5> ADDR_N_I<4> CS04<3> CS00<14> VDD VSS / ++ RM_IHPSG13_1024x32_c2_2P_DEC02 +XDEC10<2> ADDR_N_I<5> ADDR_N_I<4> CS04<2> CS00<10> VDD VSS / ++ RM_IHPSG13_1024x32_c2_2P_DEC02 +XDEC10<1> ADDR_N_I<5> ADDR_N_I<4> CS04<1> CS00<6> VDD VSS / ++ RM_IHPSG13_1024x32_c2_2P_DEC02 +XDEC10<0> ADDR_N_I<5> ADDR_N_I<4> CS04<0> CS00<2> VDD VSS / ++ RM_IHPSG13_1024x32_c2_2P_DEC02 +XL2<132> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<131> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<130> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<129> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<128> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<127> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<126> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<125> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<124> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<123> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<122> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<121> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<120> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<119> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<118> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<117> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<116> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<115> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<114> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<113> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<112> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<111> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<110> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<109> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<108> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<107> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<106> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<105> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<104> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<103> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<102> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<101> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<100> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<99> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<98> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<97> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<96> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<95> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<94> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<93> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<92> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<91> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<90> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<89> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<88> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<87> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<86> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<85> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<84> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<83> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<82> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<81> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<80> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<79> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<78> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<77> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<76> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<75> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<74> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<73> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<72> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<71> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<70> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<69> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<68> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<67> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<66> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<65> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<64> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<63> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<62> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<61> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<60> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<59> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<58> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<57> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<56> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<55> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<54> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<53> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<52> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<51> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<50> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<49> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<48> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<47> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<46> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<45> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<44> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<43> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<42> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<41> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<40> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<39> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<38> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<37> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<36> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<35> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<34> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<33> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<32> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<31> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<30> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<29> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<28> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<27> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<26> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<25> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<24> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<23> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<22> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<21> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<20> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<19> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<18> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<17> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<16> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<15> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<14> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<13> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<12> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<11> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<10> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<9> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<8> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<7> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<6> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<5> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<4> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<3> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<2> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<1> VDD VSS / RSC_IHPSG13_FILLCAP8 +XDEC00<4> ADDR_N_I<7> ADDR_N_I<6> CS_I CS04<0> VDD VSS / ++ RM_IHPSG13_1024x32_c2_2P_DEC00 +XDEC00<3> ADDR_N_I<5> ADDR_N_I<4> CS04<3> CS00<12> VDD VSS / ++ RM_IHPSG13_1024x32_c2_2P_DEC00 +XDEC00<2> ADDR_N_I<5> ADDR_N_I<4> CS04<2> CS00<8> VDD VSS / ++ RM_IHPSG13_1024x32_c2_2P_DEC00 +XDEC00<1> ADDR_N_I<5> ADDR_N_I<4> CS04<1> CS00<4> VDD VSS / ++ RM_IHPSG13_1024x32_c2_2P_DEC00 +XDEC00<0> ADDR_N_I<5> ADDR_N_I<4> CS04<0> CS00<0> VDD VSS / ++ RM_IHPSG13_1024x32_c2_2P_DEC00 +XDEC01<4> ADDR_N_I<7> ADDR_N_I<6> CS_I CS04<1> VDD VSS / ++ RM_IHPSG13_1024x32_c2_2P_DEC01 +XDEC01<3> ADDR_N_I<5> ADDR_N_I<4> CS04<3> CS00<13> VDD VSS / ++ RM_IHPSG13_1024x32_c2_2P_DEC01 +XDEC01<2> ADDR_N_I<5> ADDR_N_I<4> CS04<2> CS00<9> VDD VSS / ++ RM_IHPSG13_1024x32_c2_2P_DEC01 +XDEC01<1> ADDR_N_I<5> ADDR_N_I<4> CS04<1> CS00<5> VDD VSS / ++ RM_IHPSG13_1024x32_c2_2P_DEC01 +XDEC01<0> ADDR_N_I<5> ADDR_N_I<4> CS04<0> CS00<1> VDD VSS / ++ RM_IHPSG13_1024x32_c2_2P_DEC01 +.ENDS +.SUBCKT RM_IHPSG13_1024x32_c2_2P_ROWREG8 ACLK_N_I ADDR_I<7> ADDR_I<6> ADDR_I<5> ADDR_I<4> ++ ADDR_I<3> ADDR_I<2> ADDR_I<1> ADDR_I<0> ADDR_N_O<7> ADDR_N_O<6> ADDR_N_O<5> ++ ADDR_N_O<4> ADDR_N_O<3> ADDR_N_O<2> ADDR_N_O<1> ADDR_N_O<0> BIST_ADDR_I<7> ++ BIST_ADDR_I<6> BIST_ADDR_I<5> BIST_ADDR_I<4> BIST_ADDR_I<3> BIST_ADDR_I<2> ++ BIST_ADDR_I<1> BIST_ADDR_I<0> BIST_EN_I VDD VSS +XINV<7> q_int<7> qn_int<7> VDD VSS / RSC_IHPSG13_CINVX2 +XINV<6> q_int<6> qn_int<6> VDD VSS / RSC_IHPSG13_CINVX2 +XINV<5> q_int<5> qn_int<5> VDD VSS / RSC_IHPSG13_CINVX2 +XINV<4> q_int<4> qn_int<4> VDD VSS / RSC_IHPSG13_CINVX2 +XINV<3> q_int<3> qn_int<3> VDD VSS / RSC_IHPSG13_CINVX2 +XINV<2> q_int<2> qn_int<2> VDD VSS / RSC_IHPSG13_CINVX2 +XINV<1> q_int<1> qn_int<1> VDD VSS / RSC_IHPSG13_CINVX2 +XINV<0> q_int<0> qn_int<0> VDD VSS / RSC_IHPSG13_CINVX2 +XDRV<7> qn_int<7> ADDR_N_O<7> VDD VSS / RSC_IHPSG13_CINVX8 +XDRV<6> qn_int<6> ADDR_N_O<6> VDD VSS / RSC_IHPSG13_CINVX8 +XDRV<5> qn_int<5> ADDR_N_O<5> VDD VSS / RSC_IHPSG13_CINVX8 +XDRV<4> qn_int<4> ADDR_N_O<4> VDD VSS / RSC_IHPSG13_CINVX8 +XDRV<3> qn_int<3> ADDR_N_O<3> VDD VSS / RSC_IHPSG13_CINVX8 +XDRV<2> qn_int<2> ADDR_N_O<2> VDD VSS / RSC_IHPSG13_CINVX8 +XDRV<1> qn_int<1> ADDR_N_O<1> VDD VSS / RSC_IHPSG13_CINVX8 +XDRV<0> qn_int<0> ADDR_N_O<0> VDD VSS / RSC_IHPSG13_CINVX8 +XDFF<7> BIST_EN_I BIST_ADDR_I<7> ACLK_N_I ADDR_I<7> q_int<7> net2<0> VDD ++ VSS / RSC_IHPSG13_DFNQMX2IX1 +XDFF<6> BIST_EN_I BIST_ADDR_I<6> ACLK_N_I ADDR_I<6> q_int<6> net2<1> VDD ++ VSS / RSC_IHPSG13_DFNQMX2IX1 +XDFF<5> BIST_EN_I BIST_ADDR_I<5> ACLK_N_I ADDR_I<5> q_int<5> net2<2> VDD ++ VSS / RSC_IHPSG13_DFNQMX2IX1 +XDFF<4> BIST_EN_I BIST_ADDR_I<4> ACLK_N_I ADDR_I<4> q_int<4> net2<3> VDD ++ VSS / RSC_IHPSG13_DFNQMX2IX1 +XDFF<3> BIST_EN_I BIST_ADDR_I<3> ACLK_N_I ADDR_I<3> q_int<3> net2<4> VDD ++ VSS / RSC_IHPSG13_DFNQMX2IX1 +XDFF<2> BIST_EN_I BIST_ADDR_I<2> ACLK_N_I ADDR_I<2> q_int<2> net2<5> VDD ++ VSS / RSC_IHPSG13_DFNQMX2IX1 +XDFF<1> BIST_EN_I BIST_ADDR_I<1> ACLK_N_I ADDR_I<1> q_int<1> net2<6> VDD ++ VSS / RSC_IHPSG13_DFNQMX2IX1 +XDFF<0> BIST_EN_I BIST_ADDR_I<0> ACLK_N_I ADDR_I<0> q_int<0> net2<7> VDD ++ VSS / RSC_IHPSG13_DFNQMX2IX1 +XI11<4> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI11<3> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI11<2> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI11<1> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI10 VDD VSS / RSC_IHPSG13_FILLCAP4 +.ENDS +.SUBCKT RM_IHPSG13_1024x32_c2_2P_COLDEC4 ACLK_N ADDR<3> ADDR<2> ADDR<1> ADDR<0> ++ ADDR_COL<1> ADDR_COL<0> ADDR_DEC<7> ADDR_DEC<6> ADDR_DEC<5> ADDR_DEC<4> ++ ADDR_DEC<3> ADDR_DEC<2> ADDR_DEC<1> ADDR_DEC<0> BIST_ADDR<3> BIST_ADDR<2> ++ BIST_ADDR<1> BIST_ADDR<0> BIST_EN_I VDD VSS +XI1<7> PADR<0> PADR<1> PADR<2> addr_n<7> VDD VSS / RSC_IHPSG13_NAND3X2 +XI1<6> NADR<0> PADR<1> PADR<2> addr_n<6> VDD VSS / RSC_IHPSG13_NAND3X2 +XI1<5> PADR<0> NADR<1> PADR<2> addr_n<5> VDD VSS / RSC_IHPSG13_NAND3X2 +XI1<4> NADR<0> NADR<1> PADR<2> addr_n<4> VDD VSS / RSC_IHPSG13_NAND3X2 +XI1<3> PADR<0> PADR<1> NADR<2> addr_n<3> VDD VSS / RSC_IHPSG13_NAND3X2 +XI1<2> NADR<0> PADR<1> NADR<2> addr_n<2> VDD VSS / RSC_IHPSG13_NAND3X2 +XI1<1> PADR<0> NADR<1> NADR<2> addr_n<1> VDD VSS / RSC_IHPSG13_NAND3X2 +XI1<0> NADR<0> NADR<1> NADR<2> addr_n<0> VDD VSS / RSC_IHPSG13_NAND3X2 +XDFF<3> BIST_EN_I BIST_ADDR<3> ACLK_N ADDR<3> addr_int net12<0> VDD ++ VSS / RSC_IHPSG13_DFNQMX2IX1 +XDFF<2> BIST_EN_I BIST_ADDR<2> ACLK_N ADDR<2> padr_int<2> net12<1> VDD ++ VSS / RSC_IHPSG13_DFNQMX2IX1 +XDFF<1> BIST_EN_I BIST_ADDR<1> ACLK_N ADDR<1> padr_int<1> net12<2> VDD ++ VSS / RSC_IHPSG13_DFNQMX2IX1 +XDFF<0> BIST_EN_I BIST_ADDR<0> ACLK_N ADDR<0> padr_int<0> net12<3> VDD ++ VSS / RSC_IHPSG13_DFNQMX2IX1 +XI17<4> VDD VSS / RSC_IHPSG13_FILLCAP4 +XI17<3> VDD VSS / RSC_IHPSG13_FILLCAP4 +XI17<2> VDD VSS / RSC_IHPSG13_FILLCAP4 +XI17<1> VDD VSS / RSC_IHPSG13_FILLCAP4 +XI13<2> NADR<2> PADR<2> VDD VSS / RSC_IHPSG13_INVX2 +XI13<1> NADR<1> PADR<1> VDD VSS / RSC_IHPSG13_INVX2 +XI13<0> NADR<0> PADR<0> VDD VSS / RSC_IHPSG13_INVX2 +XI2<7> addr_n<7> ADDR_DEC<7> VDD VSS / RSC_IHPSG13_INVX2 +XI2<6> addr_n<6> ADDR_DEC<6> VDD VSS / RSC_IHPSG13_INVX2 +XI2<5> addr_n<5> ADDR_DEC<5> VDD VSS / RSC_IHPSG13_INVX2 +XI2<4> addr_n<4> ADDR_DEC<4> VDD VSS / RSC_IHPSG13_INVX2 +XI2<3> addr_n<3> ADDR_DEC<3> VDD VSS / RSC_IHPSG13_INVX2 +XI2<2> addr_n<2> ADDR_DEC<2> VDD VSS / RSC_IHPSG13_INVX2 +XI2<1> addr_n<1> ADDR_DEC<1> VDD VSS / RSC_IHPSG13_INVX2 +XI2<0> addr_n<0> ADDR_DEC<0> VDD VSS / RSC_IHPSG13_INVX2 +XI3<2> padr_int<2> NADR<2> VDD VSS / RSC_IHPSG13_INVX2 +XI3<1> padr_int<1> NADR<1> VDD VSS / RSC_IHPSG13_INVX2 +XI3<0> padr_int<0> NADR<0> VDD VSS / RSC_IHPSG13_INVX2 +XI14 addr_int ADDR_COL<0> VDD VSS / RSC_IHPSG13_CBUFX2 +XI16<8> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI16<7> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI16<6> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI16<5> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI16<4> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI16<3> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI16<2> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI16<1> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI15 ADDR_COL<1> VDD VSS / RSC_IHPSG13_TIEL +.ENDS +.SUBCKT RM_IHPSG13_1024x32_c2_2P_COLCTRL4 A_ADDR_COL A_ADDR_DEC<7> A_ADDR_DEC<6> ++ A_ADDR_DEC<5> A_ADDR_DEC<4> A_ADDR_DEC<3> A_ADDR_DEC<2> A_ADDR_DEC<1> ++ A_ADDR_DEC<0> A_BIST_BM_I A_BIST_DW_I A_BIST_EN_I A_BLC<15> A_BLC<14> ++ A_BLC<13> A_BLC<12> A_BLC<11> A_BLC<10> A_BLC<9> A_BLC<8> A_BLC<7> A_BLC<6> ++ A_BLC<5> A_BLC<4> A_BLC<3> A_BLC<2> A_BLC<1> A_BLC<0> A_BLT<15> A_BLT<14> ++ A_BLT<13> A_BLT<12> A_BLT<11> A_BLT<10> A_BLT<9> A_BLT<8> A_BLT<7> A_BLT<6> ++ A_BLT<5> A_BLT<4> A_BLT<3> A_BLT<2> A_BLT<1> A_BLT<0> A_BM_I A_DCLK_B_L ++ A_DCLK_B_R A_DCLK_L A_DCLK_R A_DR_O A_DW_I A_RCLK_B_L A_RCLK_B_R A_RCLK_L ++ A_RCLK_R A_TIEH_O A_WCLK_B_L A_WCLK_B_R A_WCLK_L A_WCLK_R B_ADDR_COL ++ B_ADDR_DEC<7> B_ADDR_DEC<6> B_ADDR_DEC<5> B_ADDR_DEC<4> B_ADDR_DEC<3> ++ B_ADDR_DEC<2> B_ADDR_DEC<1> B_ADDR_DEC<0> B_BIST_BM_I B_BIST_DW_I ++ B_BIST_EN_I B_BLC<15> B_BLC<14> B_BLC<13> B_BLC<12> B_BLC<11> B_BLC<10> ++ B_BLC<9> B_BLC<8> B_BLC<7> B_BLC<6> B_BLC<5> B_BLC<4> B_BLC<3> B_BLC<2> ++ B_BLC<1> B_BLC<0> B_BLT<15> B_BLT<14> B_BLT<13> B_BLT<12> B_BLT<11> ++ B_BLT<10> B_BLT<9> B_BLT<8> B_BLT<7> B_BLT<6> B_BLT<5> B_BLT<4> B_BLT<3> ++ B_BLT<2> B_BLT<1> B_BLT<0> B_BM_I B_DCLK_B_L B_DCLK_B_R B_DCLK_L B_DCLK_R ++ B_DR_O B_DW_I B_RCLK_B_L B_RCLK_B_R B_RCLK_L B_RCLK_R B_TIEH_O B_WCLK_B_L ++ B_WCLK_B_R B_WCLK_L B_WCLK_R VDD VSS +XB_I80 B_RCLK_B_L B_WCLK_B_L net041 VDD VSS / RSC_IHPSG13_AND2X2 +XA_I80 A_RCLK_B_L A_WCLK_B_L net21 VDD VSS / RSC_IHPSG13_AND2X2 +XB_I76 B_DI_N B_DO_WRITE_P B_WR_ZERO VDD VSS / RSC_IHPSG13_AND2X4 +XB_I75 B_DI_R B_DO_WRITE_P B_WR_ONE VDD VSS / RSC_IHPSG13_AND2X4 +XA_I76 A_DI_N A_DO_WRITE_P A_WR_ZERO VDD VSS / RSC_IHPSG13_AND2X4 +XA_I75 A_DI_R A_DO_WRITE_P A_WR_ONE VDD VSS / RSC_IHPSG13_AND2X4 +XI_FILL4<26> VDD VSS / RSC_IHPSG13_FILLCAP4 +XI_FILL4<25> VDD VSS / RSC_IHPSG13_FILLCAP4 +XI_FILL4<24> VDD VSS / RSC_IHPSG13_FILLCAP4 +XI_FILL4<23> VDD VSS / RSC_IHPSG13_FILLCAP4 +XI_FILL4<22> VDD VSS / RSC_IHPSG13_FILLCAP4 +XI_FILL4<21> VDD VSS / RSC_IHPSG13_FILLCAP4 +XI_FILL4<20> VDD VSS / RSC_IHPSG13_FILLCAP4 +XI_FILL4<19> VDD VSS / RSC_IHPSG13_FILLCAP4 +XI_FILL4<18> VDD VSS / RSC_IHPSG13_FILLCAP4 +XI_FILL4<17> VDD VSS / RSC_IHPSG13_FILLCAP4 +XI_FILL4<16> VDD VSS / RSC_IHPSG13_FILLCAP4 +XI_FILL4<15> VDD VSS / RSC_IHPSG13_FILLCAP4 +XI_FILL4<14> VDD VSS / RSC_IHPSG13_FILLCAP4 +XI_FILL4<13> VDD VSS / RSC_IHPSG13_FILLCAP4 +XI_FILL4<12> VDD VSS / RSC_IHPSG13_FILLCAP4 +XI_FILL4<11> VDD VSS / RSC_IHPSG13_FILLCAP4 +XI_FILL4<10> VDD VSS / RSC_IHPSG13_FILLCAP4 +XI_FILL4<9> VDD VSS / RSC_IHPSG13_FILLCAP4 +XI_FILL4<8> VDD VSS / RSC_IHPSG13_FILLCAP4 +XI_FILL4<7> VDD VSS / RSC_IHPSG13_FILLCAP4 +XI_FILL4<6> VDD VSS / RSC_IHPSG13_FILLCAP4 +XI_FILL4<5> VDD VSS / RSC_IHPSG13_FILLCAP4 +XI_FILL4<4> VDD VSS / RSC_IHPSG13_FILLCAP4 +XI_FILL4<3> VDD VSS / RSC_IHPSG13_FILLCAP4 +XI_FILL4<2> VDD VSS / RSC_IHPSG13_FILLCAP4 +XI_FILL4<1> VDD VSS / RSC_IHPSG13_FILLCAP4 +XB_I69 B_DCLK_L B_DCLK_B_L VDD VSS / RSC_IHPSG13_CINVX4 +XB_I50 B_WCLK_L B_WCLK_B_L VDD VSS / RSC_IHPSG13_CINVX4 +XB_EBUF B_RCLK_L B_RCLK_B_L VDD VSS / RSC_IHPSG13_CINVX4 +XB_INV<1> B_N0 B_P0 VDD VSS / RSC_IHPSG13_CINVX4 +XB_INV<0> B_ADDR_COL B_N0 VDD VSS / RSC_IHPSG13_CINVX4 +XA_I69 A_DCLK_L A_DCLK_B_L VDD VSS / RSC_IHPSG13_CINVX4 +XA_I50 A_WCLK_L A_WCLK_B_L VDD VSS / RSC_IHPSG13_CINVX4 +XA_EBUF A_RCLK_L A_RCLK_B_L VDD VSS / RSC_IHPSG13_CINVX4 +XA_INV<1> A_N0 A_P0 VDD VSS / RSC_IHPSG13_CINVX4 +XA_INV<0> A_ADDR_COL A_N0 VDD VSS / RSC_IHPSG13_CINVX4 +XB_I81<1> net041 B_PRE_N VDD VSS / RSC_IHPSG13_CINVX4_WN +XB_I81<0> net041 B_PRE_N VDD VSS / RSC_IHPSG13_CINVX4_WN +XA_I81<1> net21 A_PRE_N VDD VSS / RSC_IHPSG13_CINVX4_WN +XA_I81<0> net21 A_PRE_N VDD VSS / RSC_IHPSG13_CINVX4_WN +XA_R2 A_RCLK_L A_RCLK_R / RSC_IHPSG13_MET3RES +XA_I87 A_WCLK_L A_WCLK_R / RSC_IHPSG13_MET3RES +XA_I88 A_DCLK_L A_DCLK_R / RSC_IHPSG13_MET3RES +XA_I89 A_DCLK_B_L A_DCLK_B_R / RSC_IHPSG13_MET3RES +XA_I90 A_WCLK_B_L A_WCLK_B_R / RSC_IHPSG13_MET3RES +XA_I91 A_RCLK_B_L A_RCLK_B_R / RSC_IHPSG13_MET3RES +XB_R2 B_RCLK_L B_RCLK_R / RSC_IHPSG13_MET3RES +XB_I87 B_WCLK_L B_WCLK_R / RSC_IHPSG13_MET3RES +XB_I88 B_DCLK_L B_DCLK_R / RSC_IHPSG13_MET3RES +XB_I89 B_DCLK_B_L B_DCLK_B_R / RSC_IHPSG13_MET3RES +XB_I90 B_WCLK_B_L B_WCLK_B_R / RSC_IHPSG13_MET3RES +XB_I91 B_RCLK_B_L B_RCLK_B_R / RSC_IHPSG13_MET3RES +XA_ISENSE A_SAE A_BLC_SEL A_BLT_SEL net19 net20 VDD VSS / ++ RSC_IHPSG13_DFPQD_MSAFFX2 +XB_ISENSE B_SAE B_BLC_SEL B_BLT_SEL net037 net038 VDD VSS / ++ RSC_IHPSG13_DFPQD_MSAFFX2 +XAB_BLMUX<3> A_BLC<15> A_BLC<14> A_BLC<13> A_BLC<12> A_BLC_SEL A_BLT<15> ++ A_BLT<14> A_BLT<13> A_BLT<12> A_BLT_SEL A_PRE_N A_SEL_P<15> A_SEL_P<14> ++ A_SEL_P<13> A_SEL_P<12> A_WR_ONE A_WR_ZERO B_BLC<15> B_BLC<14> B_BLC<13> ++ B_BLC<12> B_BLC_SEL B_BLT<15> B_BLT<14> B_BLT<13> B_BLT<12> B_BLT_SEL ++ B_PRE_N B_SEL_P<15> B_SEL_P<14> B_SEL_P<13> B_SEL_P<12> B_WR_ONE B_WR_ZERO ++ VDD VSS / RM_IHPSG13_1024x32_c2_2P_BLDRV +XAB_BLMUX<2> A_BLC<11> A_BLC<10> A_BLC<9> A_BLC<8> A_BLC_SEL A_BLT<11> ++ A_BLT<10> A_BLT<9> A_BLT<8> A_BLT_SEL A_PRE_N A_SEL_P<11> A_SEL_P<10> ++ A_SEL_P<9> A_SEL_P<8> A_WR_ONE A_WR_ZERO B_BLC<11> B_BLC<10> B_BLC<9> ++ B_BLC<8> B_BLC_SEL B_BLT<11> B_BLT<10> B_BLT<9> B_BLT<8> B_BLT_SEL B_PRE_N ++ B_SEL_P<11> B_SEL_P<10> B_SEL_P<9> B_SEL_P<8> B_WR_ONE B_WR_ZERO VDD ++ VSS / RM_IHPSG13_1024x32_c2_2P_BLDRV +XAB_BLMUX<1> A_BLC<7> A_BLC<6> A_BLC<5> A_BLC<4> A_BLC_SEL A_BLT<7> A_BLT<6> ++ A_BLT<5> A_BLT<4> A_BLT_SEL A_PRE_N A_SEL_P<7> A_SEL_P<6> A_SEL_P<5> ++ A_SEL_P<4> A_WR_ONE A_WR_ZERO B_BLC<7> B_BLC<6> B_BLC<5> B_BLC<4> B_BLC_SEL ++ B_BLT<7> B_BLT<6> B_BLT<5> B_BLT<4> B_BLT_SEL B_PRE_N B_SEL_P<7> B_SEL_P<6> ++ B_SEL_P<5> B_SEL_P<4> B_WR_ONE B_WR_ZERO VDD VSS / ++ RM_IHPSG13_1024x32_c2_2P_BLDRV +XAB_BLMUX<0> A_BLC<3> A_BLC<2> A_BLC<1> A_BLC<0> A_BLC_SEL A_BLT<3> A_BLT<2> ++ A_BLT<1> A_BLT<0> A_BLT_SEL A_PRE_N A_SEL_P<3> A_SEL_P<2> A_SEL_P<1> ++ A_SEL_P<0> A_WR_ONE A_WR_ZERO B_BLC<3> B_BLC<2> B_BLC<1> B_BLC<0> B_BLC_SEL ++ B_BLT<3> B_BLT<2> B_BLT<1> B_BLT<0> B_BLT_SEL B_PRE_N B_SEL_P<3> B_SEL_P<2> ++ B_SEL_P<1> B_SEL_P<0> B_WR_ONE B_WR_ZERO VDD VSS / ++ RM_IHPSG13_1024x32_c2_2P_BLDRV +XA_I51 net19 A_DR_O VDD VSS / RSC_IHPSG13_INVX4 +XB_I51 net037 B_DR_O VDD VSS / RSC_IHPSG13_INVX4 +XA_I78 A_RCLK_B_L A_SAE VDD VSS / RSC_IHPSG13_CBUFX2 +XB_I78 B_RCLK_B_L B_SAE VDD VSS / RSC_IHPSG13_CBUFX2 +XA_DREG A_BIST_EN_I A_BIST_DW_I A_DCLK_B_L A_DW_I A_DI_R net22 VDD VSS ++ / RSC_IHPSG13_DFNQMX2IX1 +XB_DREG B_BIST_EN_I B_BIST_DW_I B_DCLK_B_L B_DW_I B_DI_R net046 VDD ++ VSS / RSC_IHPSG13_DFNQMX2IX1 +XB_BREG B_BIST_EN_I B_BIST_BM_I B_DCLK_B_L B_BM_I B_BM_R net045 VDD ++ VSS / RSC_IHPSG13_DFNQMX2IX1 +XA_BREG A_BIST_EN_I A_BIST_BM_I A_DCLK_B_L A_BM_I A_BM_R net24 VDD VSS ++ / RSC_IHPSG13_DFNQMX2IX1 +XA_DEC3INV<15> net23<0> A_SEL_P<15> VDD VSS / RSC_IHPSG13_INVX2 +XA_DEC3INV<14> net23<1> A_SEL_P<14> VDD VSS / RSC_IHPSG13_INVX2 +XA_DEC3INV<13> net23<2> A_SEL_P<13> VDD VSS / RSC_IHPSG13_INVX2 +XA_DEC3INV<12> net23<3> A_SEL_P<12> VDD VSS / RSC_IHPSG13_INVX2 +XA_DEC3INV<11> net23<4> A_SEL_P<11> VDD VSS / RSC_IHPSG13_INVX2 +XA_DEC3INV<10> net23<5> A_SEL_P<10> VDD VSS / RSC_IHPSG13_INVX2 +XA_DEC3INV<9> net23<6> A_SEL_P<9> VDD VSS / RSC_IHPSG13_INVX2 +XA_DEC3INV<8> net23<7> A_SEL_P<8> VDD VSS / RSC_IHPSG13_INVX2 +XA_DEC3INV<7> net23<8> A_SEL_P<7> VDD VSS / RSC_IHPSG13_INVX2 +XA_DEC3INV<6> net23<9> A_SEL_P<6> VDD VSS / RSC_IHPSG13_INVX2 +XA_DEC3INV<5> net23<10> A_SEL_P<5> VDD VSS / RSC_IHPSG13_INVX2 +XA_DEC3INV<4> net23<11> A_SEL_P<4> VDD VSS / RSC_IHPSG13_INVX2 +XA_DEC3INV<3> net23<12> A_SEL_P<3> VDD VSS / RSC_IHPSG13_INVX2 +XA_DEC3INV<2> net23<13> A_SEL_P<2> VDD VSS / RSC_IHPSG13_INVX2 +XA_DEC3INV<1> net23<14> A_SEL_P<1> VDD VSS / RSC_IHPSG13_INVX2 +XA_DEC3INV<0> net23<15> A_SEL_P<0> VDD VSS / RSC_IHPSG13_INVX2 +XA_I83 A_BM_R A_BM_N VDD VSS / RSC_IHPSG13_INVX2 +XA_I49 A_DI_R A_DI_N VDD VSS / RSC_IHPSG13_INVX2 +XB_DEC3INV<15> net044<0> B_SEL_P<15> VDD VSS / RSC_IHPSG13_INVX2 +XB_DEC3INV<14> net044<1> B_SEL_P<14> VDD VSS / RSC_IHPSG13_INVX2 +XB_DEC3INV<13> net044<2> B_SEL_P<13> VDD VSS / RSC_IHPSG13_INVX2 +XB_DEC3INV<12> net044<3> B_SEL_P<12> VDD VSS / RSC_IHPSG13_INVX2 +XB_DEC3INV<11> net044<4> B_SEL_P<11> VDD VSS / RSC_IHPSG13_INVX2 +XB_DEC3INV<10> net044<5> B_SEL_P<10> VDD VSS / RSC_IHPSG13_INVX2 +XB_DEC3INV<9> net044<6> B_SEL_P<9> VDD VSS / RSC_IHPSG13_INVX2 +XB_DEC3INV<8> net044<7> B_SEL_P<8> VDD VSS / RSC_IHPSG13_INVX2 +XB_DEC3INV<7> net044<8> B_SEL_P<7> VDD VSS / RSC_IHPSG13_INVX2 +XB_DEC3INV<6> net044<9> B_SEL_P<6> VDD VSS / RSC_IHPSG13_INVX2 +XB_DEC3INV<5> net044<10> B_SEL_P<5> VDD VSS / RSC_IHPSG13_INVX2 +XB_DEC3INV<4> net044<11> B_SEL_P<4> VDD VSS / RSC_IHPSG13_INVX2 +XB_DEC3INV<3> net044<12> B_SEL_P<3> VDD VSS / RSC_IHPSG13_INVX2 +XB_DEC3INV<2> net044<13> B_SEL_P<2> VDD VSS / RSC_IHPSG13_INVX2 +XB_DEC3INV<1> net044<14> B_SEL_P<1> VDD VSS / RSC_IHPSG13_INVX2 +XB_DEC3INV<0> net044<15> B_SEL_P<0> VDD VSS / RSC_IHPSG13_INVX2 +XB_I83 B_BM_R B_BM_N VDD VSS / RSC_IHPSG13_INVX2 +XB_I49 B_DI_R B_DI_N VDD VSS / RSC_IHPSG13_INVX2 +XI_FILL8<20> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI_FILL8<19> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI_FILL8<18> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI_FILL8<17> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI_FILL8<16> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI_FILL8<15> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI_FILL8<14> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI_FILL8<13> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI_FILL8<12> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI_FILL8<11> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI_FILL8<10> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI_FILL8<9> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI_FILL8<8> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI_FILL8<7> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI_FILL8<6> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI_FILL8<5> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI_FILL8<4> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI_FILL8<3> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI_FILL8<2> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI_FILL8<1> VDD VSS / RSC_IHPSG13_FILLCAP8 +XA_I44 A_BM_N A_WCLK_B_L A_DO_WRITE_P VDD VSS / RSC_IHPSG13_NOR2X2 +XB_I44 B_BM_N B_WCLK_B_L B_DO_WRITE_P VDD VSS / RSC_IHPSG13_NOR2X2 +XA_DEC3<15> A_P0 A_ADDR_DEC<7> net23<0> VDD VSS / RSC_IHPSG13_NAND2X2 +XA_DEC3<14> A_P0 A_ADDR_DEC<6> net23<1> VDD VSS / RSC_IHPSG13_NAND2X2 +XA_DEC3<13> A_P0 A_ADDR_DEC<5> net23<2> VDD VSS / RSC_IHPSG13_NAND2X2 +XA_DEC3<12> A_P0 A_ADDR_DEC<4> net23<3> VDD VSS / RSC_IHPSG13_NAND2X2 +XA_DEC3<11> A_P0 A_ADDR_DEC<3> net23<4> VDD VSS / RSC_IHPSG13_NAND2X2 +XA_DEC3<10> A_P0 A_ADDR_DEC<2> net23<5> VDD VSS / RSC_IHPSG13_NAND2X2 +XA_DEC3<9> A_P0 A_ADDR_DEC<1> net23<6> VDD VSS / RSC_IHPSG13_NAND2X2 +XA_DEC3<8> A_P0 A_ADDR_DEC<0> net23<7> VDD VSS / RSC_IHPSG13_NAND2X2 +XA_DEC3<7> A_N0 A_ADDR_DEC<7> net23<8> VDD VSS / RSC_IHPSG13_NAND2X2 +XA_DEC3<6> A_N0 A_ADDR_DEC<6> net23<9> VDD VSS / RSC_IHPSG13_NAND2X2 +XA_DEC3<5> A_N0 A_ADDR_DEC<5> net23<10> VDD VSS / RSC_IHPSG13_NAND2X2 +XA_DEC3<4> A_N0 A_ADDR_DEC<4> net23<11> VDD VSS / RSC_IHPSG13_NAND2X2 +XA_DEC3<3> A_N0 A_ADDR_DEC<3> net23<12> VDD VSS / RSC_IHPSG13_NAND2X2 +XA_DEC3<2> A_N0 A_ADDR_DEC<2> net23<13> VDD VSS / RSC_IHPSG13_NAND2X2 +XA_DEC3<1> A_N0 A_ADDR_DEC<1> net23<14> VDD VSS / RSC_IHPSG13_NAND2X2 +XA_DEC3<0> A_N0 A_ADDR_DEC<0> net23<15> VDD VSS / RSC_IHPSG13_NAND2X2 +XB_DEC3<15> B_P0 B_ADDR_DEC<7> net044<0> VDD VSS / RSC_IHPSG13_NAND2X2 +XB_DEC3<14> B_P0 B_ADDR_DEC<6> net044<1> VDD VSS / RSC_IHPSG13_NAND2X2 +XB_DEC3<13> B_P0 B_ADDR_DEC<5> net044<2> VDD VSS / RSC_IHPSG13_NAND2X2 +XB_DEC3<12> B_P0 B_ADDR_DEC<4> net044<3> VDD VSS / RSC_IHPSG13_NAND2X2 +XB_DEC3<11> B_P0 B_ADDR_DEC<3> net044<4> VDD VSS / RSC_IHPSG13_NAND2X2 +XB_DEC3<10> B_P0 B_ADDR_DEC<2> net044<5> VDD VSS / RSC_IHPSG13_NAND2X2 +XB_DEC3<9> B_P0 B_ADDR_DEC<1> net044<6> VDD VSS / RSC_IHPSG13_NAND2X2 +XB_DEC3<8> B_P0 B_ADDR_DEC<0> net044<7> VDD VSS / RSC_IHPSG13_NAND2X2 +XB_DEC3<7> B_N0 B_ADDR_DEC<7> net044<8> VDD VSS / RSC_IHPSG13_NAND2X2 +XB_DEC3<6> B_N0 B_ADDR_DEC<6> net044<9> VDD VSS / RSC_IHPSG13_NAND2X2 +XB_DEC3<5> B_N0 B_ADDR_DEC<5> net044<10> VDD VSS / RSC_IHPSG13_NAND2X2 +XB_DEC3<4> B_N0 B_ADDR_DEC<4> net044<11> VDD VSS / RSC_IHPSG13_NAND2X2 +XB_DEC3<3> B_N0 B_ADDR_DEC<3> net044<12> VDD VSS / RSC_IHPSG13_NAND2X2 +XB_DEC3<2> B_N0 B_ADDR_DEC<2> net044<13> VDD VSS / RSC_IHPSG13_NAND2X2 +XB_DEC3<1> B_N0 B_ADDR_DEC<1> net044<14> VDD VSS / RSC_IHPSG13_NAND2X2 +XB_DEC3<0> B_N0 B_ADDR_DEC<0> net044<15> VDD VSS / RSC_IHPSG13_NAND2X2 +XB_BM_TIEH B_TIEH_O VDD VSS / RSC_IHPSG13_TIEH +XA_BM_TIEH A_TIEH_O VDD VSS / RSC_IHPSG13_TIEH +.ENDS + + +.SUBCKT RM_IHPSG13_1024x32_c2_2P_ROWDEC5 ADDR_N_I<4> ADDR_N_I<3> ADDR_N_I<2> ADDR_N_I<1> ++ ADDR_N_I<0> CS_I ECLK_I WL_O<31> WL_O<30> WL_O<29> WL_O<28> WL_O<27> ++ WL_O<26> WL_O<25> WL_O<24> WL_O<23> WL_O<22> WL_O<21> WL_O<20> WL_O<19> ++ WL_O<18> WL_O<17> WL_O<16> WL_O<15> WL_O<14> WL_O<13> WL_O<12> WL_O<11> ++ WL_O<10> WL_O<9> WL_O<8> WL_O<7> WL_O<6> WL_O<5> WL_O<4> WL_O<3> WL_O<2> ++ WL_O<1> WL_O<0> VDD VSS +XDEC00 ADDR_N_I<5> ADDR_N_I<4> CS_I CS00<0> VDD VSS / ++ RM_IHPSG13_1024x32_c2_2P_DEC00 +XSEL<1> ADDR_N_I<3> ADDR_N_I<2> ADDR_N_I<1> ADDR_N_I<0> CS00<1> ECLK_H<1> ++ ECLK_H<2> ECLK_B<1> ECLK_B<2> WL_O<31> WL_O<30> WL_O<29> WL_O<28> WL_O<27> ++ WL_O<26> WL_O<25> WL_O<24> WL_O<23> WL_O<22> WL_O<21> WL_O<20> WL_O<19> ++ WL_O<18> WL_O<17> WL_O<16> VDD VSS / RM_IHPSG13_1024x32_c2_2P_DEC04 +XSEL<0> ADDR_N_I<3> ADDR_N_I<2> ADDR_N_I<1> ADDR_N_I<0> CS00<0> ECLK_I ++ ECLK_H<1> ECLK_B<0> ECLK_B<1> WL_O<15> WL_O<14> WL_O<13> WL_O<12> WL_O<11> ++ WL_O<10> WL_O<9> WL_O<8> WL_O<7> WL_O<6> WL_O<5> WL_O<4> WL_O<3> WL_O<2> ++ WL_O<1> WL_O<0> VDD VSS / RM_IHPSG13_1024x32_c2_2P_DEC04 +XDEC01 ADDR_N_I<5> ADDR_N_I<4> CS_I CS00<1> VDD VSS / ++ RM_IHPSG13_1024x32_c2_2P_DEC01 +XL2<18> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<17> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<16> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<15> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<14> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<13> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<12> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<11> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<10> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<9> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<8> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<7> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<6> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<5> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<4> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<3> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<2> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<1> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI0 ADDR_N_I<5> VDD VSS / RSC_IHPSG13_TIEL +.ENDS +.SUBCKT RM_IHPSG13_1024x32_c2_2P_ROWREG5 ACLK_N_I ADDR_I<4> ADDR_I<3> ADDR_I<2> ADDR_I<1> ++ ADDR_I<0> ADDR_N_O<4> ADDR_N_O<3> ADDR_N_O<2> ADDR_N_O<1> ADDR_N_O<0> ++ BIST_ADDR_I<4> BIST_ADDR_I<3> BIST_ADDR_I<2> BIST_ADDR_I<1> BIST_ADDR_I<0> ++ BIST_EN_I VDD VSS +XINV<4> q_int<4> qn_int<4> VDD VSS / RSC_IHPSG13_CINVX2 +XINV<3> q_int<3> qn_int<3> VDD VSS / RSC_IHPSG13_CINVX2 +XINV<2> q_int<2> qn_int<2> VDD VSS / RSC_IHPSG13_CINVX2 +XINV<1> q_int<1> qn_int<1> VDD VSS / RSC_IHPSG13_CINVX2 +XINV<0> q_int<0> qn_int<0> VDD VSS / RSC_IHPSG13_CINVX2 +XDRV<4> qn_int<4> ADDR_N_O<4> VDD VSS / RSC_IHPSG13_CINVX8 +XDRV<3> qn_int<3> ADDR_N_O<3> VDD VSS / RSC_IHPSG13_CINVX8 +XDRV<2> qn_int<2> ADDR_N_O<2> VDD VSS / RSC_IHPSG13_CINVX8 +XDRV<1> qn_int<1> ADDR_N_O<1> VDD VSS / RSC_IHPSG13_CINVX8 +XDRV<0> qn_int<0> ADDR_N_O<0> VDD VSS / RSC_IHPSG13_CINVX8 +XDFF<4> BIST_EN_I BIST_ADDR_I<4> ACLK_N_I ADDR_I<4> q_int<4> net2<0> VDD ++ VSS / RSC_IHPSG13_DFNQMX2IX1 +XDFF<3> BIST_EN_I BIST_ADDR_I<3> ACLK_N_I ADDR_I<3> q_int<3> net2<1> VDD ++ VSS / RSC_IHPSG13_DFNQMX2IX1 +XDFF<2> BIST_EN_I BIST_ADDR_I<2> ACLK_N_I ADDR_I<2> q_int<2> net2<2> VDD ++ VSS / RSC_IHPSG13_DFNQMX2IX1 +XDFF<1> BIST_EN_I BIST_ADDR_I<1> ACLK_N_I ADDR_I<1> q_int<1> net2<3> VDD ++ VSS / RSC_IHPSG13_DFNQMX2IX1 +XDFF<0> BIST_EN_I BIST_ADDR_I<0> ACLK_N_I ADDR_I<0> q_int<0> net2<4> VDD ++ VSS / RSC_IHPSG13_DFNQMX2IX1 +XI11<16> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI11<15> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI11<14> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI11<13> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI11<12> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI11<11> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI11<10> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI11<9> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI11<8> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI11<7> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI11<6> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI11<5> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI11<4> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI11<3> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI11<2> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI11<1> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI12<3> VDD VSS / RSC_IHPSG13_FILLCAP4 +XI12<2> VDD VSS / RSC_IHPSG13_FILLCAP4 +XI12<1> VDD VSS / RSC_IHPSG13_FILLCAP4 +XI12<0> VDD VSS / RSC_IHPSG13_FILLCAP4 +.ENDS + + +.SUBCKT RM_IHPSG13_1024x32_c2_2P_COLDEC3 ACLK_N ADDR<2> ADDR<1> ADDR<0> ADDR_COL<1> ++ ADDR_COL<0> ADDR_DEC<7> ADDR_DEC<6> ADDR_DEC<5> ADDR_DEC<4> ADDR_DEC<3> ++ ADDR_DEC<2> ADDR_DEC<1> ADDR_DEC<0> BIST_ADDR<2> BIST_ADDR<1> BIST_ADDR<0> ++ BIST_EN_I VDD VSS +XI1<7> PADR<0> PADR<1> PADR<2> addr_n<7> VDD VSS / RSC_IHPSG13_NAND3X2 +XI1<6> NADR<0> PADR<1> PADR<2> addr_n<6> VDD VSS / RSC_IHPSG13_NAND3X2 +XI1<5> PADR<0> NADR<1> PADR<2> addr_n<5> VDD VSS / RSC_IHPSG13_NAND3X2 +XI1<4> NADR<0> NADR<1> PADR<2> addr_n<4> VDD VSS / RSC_IHPSG13_NAND3X2 +XI1<3> PADR<0> PADR<1> NADR<2> addr_n<3> VDD VSS / RSC_IHPSG13_NAND3X2 +XI1<2> NADR<0> PADR<1> NADR<2> addr_n<2> VDD VSS / RSC_IHPSG13_NAND3X2 +XI1<1> PADR<0> NADR<1> NADR<2> addr_n<1> VDD VSS / RSC_IHPSG13_NAND3X2 +XI1<0> NADR<0> NADR<1> NADR<2> addr_n<0> VDD VSS / RSC_IHPSG13_NAND3X2 +XDFF<2> BIST_EN_I BIST_ADDR<2> ACLK_N ADDR<2> padr_int<2> net13<0> VDD ++ VSS / RSC_IHPSG13_DFNQMX2IX1 +XDFF<1> BIST_EN_I BIST_ADDR<1> ACLK_N ADDR<1> padr_int<1> net13<1> VDD ++ VSS / RSC_IHPSG13_DFNQMX2IX1 +XDFF<0> BIST_EN_I BIST_ADDR<0> ACLK_N ADDR<0> padr_int<0> net13<2> VDD ++ VSS / RSC_IHPSG13_DFNQMX2IX1 +XI15<1> ADDR_COL<1> VDD VSS / RSC_IHPSG13_TIEL +XI15<0> ADDR_COL<0> VDD VSS / RSC_IHPSG13_TIEL +XI13<2> NADR<2> PADR<2> VDD VSS / RSC_IHPSG13_INVX2 +XI13<1> NADR<1> PADR<1> VDD VSS / RSC_IHPSG13_INVX2 +XI13<0> NADR<0> PADR<0> VDD VSS / RSC_IHPSG13_INVX2 +XI3<2> padr_int<2> NADR<2> VDD VSS / RSC_IHPSG13_INVX2 +XI3<1> padr_int<1> NADR<1> VDD VSS / RSC_IHPSG13_INVX2 +XI3<0> padr_int<0> NADR<0> VDD VSS / RSC_IHPSG13_INVX2 +XI2<7> addr_n<7> ADDR_DEC<7> VDD VSS / RSC_IHPSG13_INVX2 +XI2<6> addr_n<6> ADDR_DEC<6> VDD VSS / RSC_IHPSG13_INVX2 +XI2<5> addr_n<5> ADDR_DEC<5> VDD VSS / RSC_IHPSG13_INVX2 +XI2<4> addr_n<4> ADDR_DEC<4> VDD VSS / RSC_IHPSG13_INVX2 +XI2<3> addr_n<3> ADDR_DEC<3> VDD VSS / RSC_IHPSG13_INVX2 +XI2<2> addr_n<2> ADDR_DEC<2> VDD VSS / RSC_IHPSG13_INVX2 +XI2<1> addr_n<1> ADDR_DEC<1> VDD VSS / RSC_IHPSG13_INVX2 +XI2<0> addr_n<0> ADDR_DEC<0> VDD VSS / RSC_IHPSG13_INVX2 +XI17<4> VDD VSS / RSC_IHPSG13_FILLCAP4 +XI17<3> VDD VSS / RSC_IHPSG13_FILLCAP4 +XI17<2> VDD VSS / RSC_IHPSG13_FILLCAP4 +XI17<1> VDD VSS / RSC_IHPSG13_FILLCAP4 +XI16<11> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI16<10> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI16<9> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI16<8> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI16<7> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI16<6> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI16<5> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI16<4> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI16<3> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI16<2> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI16<1> VDD VSS / RSC_IHPSG13_FILLCAP8 +.ENDS +.SUBCKT RSC_IHPSG13_DFPQD_MSAFFX2P CP DN DP QN QP VDD VSS +XI_AMP CP DN DP QN QP VDD VSS / RSC_IHPSG13_DFPQD_MSAFFX2 +.ENDS +.SUBCKT RM_IHPSG13_1024x32_c2_2P_COLCTRL3 A_ADDR_DEC<7> A_ADDR_DEC<6> A_ADDR_DEC<5> ++ A_ADDR_DEC<4> A_ADDR_DEC<3> A_ADDR_DEC<2> A_ADDR_DEC<1> A_ADDR_DEC<0> ++ A_BIST_BM_I A_BIST_DW_I A_BIST_EN_I A_BLC<7> A_BLC<6> A_BLC<5> A_BLC<4> ++ A_BLC<3> A_BLC<2> A_BLC<1> A_BLC<0> A_BLT<7> A_BLT<6> A_BLT<5> A_BLT<4> ++ A_BLT<3> A_BLT<2> A_BLT<1> A_BLT<0> A_BM_I A_DCLK_B_L A_DCLK_B_R A_DCLK_L ++ A_DCLK_R A_DR_O A_DW_I A_RCLK_B_L A_RCLK_B_R A_RCLK_L A_RCLK_R A_TIEH_O ++ A_WCLK_B_L A_WCLK_B_R A_WCLK_L A_WCLK_R B_ADDR_DEC<7> B_ADDR_DEC<6> ++ B_ADDR_DEC<5> B_ADDR_DEC<4> B_ADDR_DEC<3> B_ADDR_DEC<2> B_ADDR_DEC<1> ++ B_ADDR_DEC<0> B_BIST_BM_I B_BIST_DW_I B_BIST_EN_I B_BLC<7> B_BLC<6> B_BLC<5> ++ B_BLC<4> B_BLC<3> B_BLC<2> B_BLC<1> B_BLC<0> B_BLT<7> B_BLT<6> B_BLT<5> ++ B_BLT<4> B_BLT<3> B_BLT<2> B_BLT<1> B_BLT<0> B_BM_I B_DCLK_B_L B_DCLK_B_R ++ B_DCLK_L B_DCLK_R B_DR_O B_DW_I B_RCLK_B_L B_RCLK_B_R B_RCLK_L B_RCLK_R ++ B_TIEH_O B_WCLK_B_L B_WCLK_B_R B_WCLK_L B_WCLK_R VDD VSS +XB_DREG B_BIST_EN_I B_BIST_DW_I B_DCLK_B_L B_DW_I B_DI_R net044 VDD ++ VSS / RSC_IHPSG13_DFNQMX2IX1 +XB_BREG B_BIST_EN_I B_BIST_BM_I B_DCLK_B_L B_BM_I B_BM_R net043 VDD ++ VSS / RSC_IHPSG13_DFNQMX2IX1 +XA_DREG A_BIST_EN_I A_BIST_DW_I A_DCLK_B_L A_DW_I A_DI_R net22 VDD VSS ++ / RSC_IHPSG13_DFNQMX2IX1 +XA_BREG A_BIST_EN_I A_BIST_BM_I A_DCLK_B_L A_BM_I A_BM_R net23 VDD VSS ++ / RSC_IHPSG13_DFNQMX2IX1 +XI_FILL8<11> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI_FILL8<10> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI_FILL8<9> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI_FILL8<8> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI_FILL8<7> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI_FILL8<6> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI_FILL8<5> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI_FILL8<4> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI_FILL8<3> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI_FILL8<2> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI_FILL8<1> VDD VSS / RSC_IHPSG13_FILLCAP8 +XB_I51 net037 B_DR_O VDD VSS / RSC_IHPSG13_INVX4 +XA_I51 net19 A_DR_O VDD VSS / RSC_IHPSG13_INVX4 +XB_I44 B_BM_N B_WCLK_B_L B_DO_WRITE_P VDD VSS / RSC_IHPSG13_NOR2X2 +XA_I44 A_BM_N A_WCLK_B_L A_DO_WRITE_P VDD VSS / RSC_IHPSG13_NOR2X2 +XB_BM_TIEH B_TIEH_O VDD VSS / RSC_IHPSG13_TIEH +XA_BM_TIEH A_TIEH_O VDD VSS / RSC_IHPSG13_TIEH +XB_ISENSE B_SAE B_BLC_SEL B_BLT_SEL net037 net038 VDD VSS / ++ RSC_IHPSG13_DFPQD_MSAFFX2P +XA_ISENSE A_SAE A_BLC_SEL A_BLT_SEL net19 net20 VDD VSS / ++ RSC_IHPSG13_DFPQD_MSAFFX2P +XB_I49 B_DI_R B_DI_N VDD VSS / RSC_IHPSG13_INVX2 +XB_I83 B_BM_R B_BM_N VDD VSS / RSC_IHPSG13_INVX2 +XA_I49 A_DI_R A_DI_N VDD VSS / RSC_IHPSG13_INVX2 +XA_I83 A_BM_R A_BM_N VDD VSS / RSC_IHPSG13_INVX2 +XB_I69 B_DCLK_L B_DCLK_B_L VDD VSS / RSC_IHPSG13_CINVX2 +XB_I50 B_WCLK_L B_WCLK_B_L VDD VSS / RSC_IHPSG13_CINVX2 +XB_EBUF B_RCLK_L B_RCLK_B_L VDD VSS / RSC_IHPSG13_CINVX2 +XA_I69 A_DCLK_L A_DCLK_B_L VDD VSS / RSC_IHPSG13_CINVX2 +XA_I50 A_WCLK_L A_WCLK_B_L VDD VSS / RSC_IHPSG13_CINVX2 +XA_EBUF A_RCLK_L A_RCLK_B_L VDD VSS / RSC_IHPSG13_CINVX2 +XAB_BLMUX<1> A_BLC<7> A_BLC<6> A_BLC<5> A_BLC<4> A_BLC_SEL A_BLT<7> A_BLT<6> ++ A_BLT<5> A_BLT<4> A_BLT_SEL A_PRE_N A_ADDR_DEC<7> A_ADDR_DEC<6> ++ A_ADDR_DEC<5> A_ADDR_DEC<4> A_WR_ONE A_WR_ZERO B_BLC<7> B_BLC<6> B_BLC<5> ++ B_BLC<4> B_BLC_SEL B_BLT<7> B_BLT<6> B_BLT<5> B_BLT<4> B_BLT_SEL B_PRE_N ++ B_ADDR_DEC<7> B_ADDR_DEC<6> B_ADDR_DEC<5> B_ADDR_DEC<4> B_WR_ONE B_WR_ZERO ++ VDD VSS / RM_IHPSG13_1024x32_c2_2P_BLDRV +XAB_BLMUX<0> A_BLC<3> A_BLC<2> A_BLC<1> A_BLC<0> A_BLC_SEL A_BLT<3> A_BLT<2> ++ A_BLT<1> A_BLT<0> A_BLT_SEL A_PRE_N A_ADDR_DEC<3> A_ADDR_DEC<2> ++ A_ADDR_DEC<1> A_ADDR_DEC<0> A_WR_ONE A_WR_ZERO B_BLC<3> B_BLC<2> B_BLC<1> ++ B_BLC<0> B_BLC_SEL B_BLT<3> B_BLT<2> B_BLT<1> B_BLT<0> B_BLT_SEL B_PRE_N ++ B_ADDR_DEC<3> B_ADDR_DEC<2> B_ADDR_DEC<1> B_ADDR_DEC<0> B_WR_ONE B_WR_ZERO ++ VDD VSS / RM_IHPSG13_1024x32_c2_2P_BLDRV +XB_I78 B_RCLK_B_L B_SAE VDD VSS / RSC_IHPSG13_CBUFX2 +XA_I78 A_RCLK_B_L A_SAE VDD VSS / RSC_IHPSG13_CBUFX2 +XB_I88 B_DCLK_L B_DCLK_R / RSC_IHPSG13_MET3RES +XB_I87 B_WCLK_L B_WCLK_R / RSC_IHPSG13_MET3RES +XB_R2 B_RCLK_L B_RCLK_R / RSC_IHPSG13_MET3RES +XB_I91 B_RCLK_B_L B_RCLK_B_R / RSC_IHPSG13_MET3RES +XB_I90 B_WCLK_B_L B_WCLK_B_R / RSC_IHPSG13_MET3RES +XB_I89 B_DCLK_B_L B_DCLK_B_R / RSC_IHPSG13_MET3RES +XA_I88 A_DCLK_L A_DCLK_R / RSC_IHPSG13_MET3RES +XA_I87 A_WCLK_L A_WCLK_R / RSC_IHPSG13_MET3RES +XA_R2 A_RCLK_L A_RCLK_R / RSC_IHPSG13_MET3RES +XA_I91 A_RCLK_B_L A_RCLK_B_R / RSC_IHPSG13_MET3RES +XA_I90 A_WCLK_B_L A_WCLK_B_R / RSC_IHPSG13_MET3RES +XA_I89 A_DCLK_B_L A_DCLK_B_R / RSC_IHPSG13_MET3RES +XB_I80 B_WCLK_B_L B_RCLK_B_L net041 VDD VSS / RSC_IHPSG13_AND2X2 +XB_I76 B_DO_WRITE_P B_DI_N B_WR_ZERO VDD VSS / RSC_IHPSG13_AND2X2 +XB_I75 B_DO_WRITE_P B_DI_R B_WR_ONE VDD VSS / RSC_IHPSG13_AND2X2 +XA_I80 A_WCLK_B_L A_RCLK_B_L net21 VDD VSS / RSC_IHPSG13_AND2X2 +XA_I76 A_DI_N A_DO_WRITE_P A_WR_ZERO VDD VSS / RSC_IHPSG13_AND2X2 +XA_I75 A_DI_R A_DO_WRITE_P A_WR_ONE VDD VSS / RSC_IHPSG13_AND2X2 +XB_I81 net041 B_PRE_N VDD VSS / RSC_IHPSG13_CINVX4_WN +XA_I81 net21 A_PRE_N VDD VSS / RSC_IHPSG13_CINVX4_WN +XI_FILL4<10> VDD VSS / RSC_IHPSG13_FILLCAP4 +XI_FILL4<9> VDD VSS / RSC_IHPSG13_FILLCAP4 +XI_FILL4<8> VDD VSS / RSC_IHPSG13_FILLCAP4 +XI_FILL4<7> VDD VSS / RSC_IHPSG13_FILLCAP4 +XI_FILL4<6> VDD VSS / RSC_IHPSG13_FILLCAP4 +XI_FILL4<5> VDD VSS / RSC_IHPSG13_FILLCAP4 +XI_FILL4<4> VDD VSS / RSC_IHPSG13_FILLCAP4 +XI_FILL4<3> VDD VSS / RSC_IHPSG13_FILLCAP4 +XI_FILL4<2> VDD VSS / RSC_IHPSG13_FILLCAP4 +XI_FILL4<1> VDD VSS / RSC_IHPSG13_FILLCAP4 +.ENDS + +.SUBCKT RM_IHPSG13_1024x32_c2_2P_ROWDEC6 ADDR_N_I<5> ADDR_N_I<4> ADDR_N_I<3> ADDR_N_I<2> ++ ADDR_N_I<1> ADDR_N_I<0> CS_I ECLK_I WL_O<63> WL_O<62> WL_O<61> WL_O<60> ++ WL_O<59> WL_O<58> WL_O<57> WL_O<56> WL_O<55> WL_O<54> WL_O<53> WL_O<52> ++ WL_O<51> WL_O<50> WL_O<49> WL_O<48> WL_O<47> WL_O<46> WL_O<45> WL_O<44> ++ WL_O<43> WL_O<42> WL_O<41> WL_O<40> WL_O<39> WL_O<38> WL_O<37> WL_O<36> ++ WL_O<35> WL_O<34> WL_O<33> WL_O<32> WL_O<31> WL_O<30> WL_O<29> WL_O<28> ++ WL_O<27> WL_O<26> WL_O<25> WL_O<24> WL_O<23> WL_O<22> WL_O<21> WL_O<20> ++ WL_O<19> WL_O<18> WL_O<17> WL_O<16> WL_O<15> WL_O<14> WL_O<13> WL_O<12> ++ WL_O<11> WL_O<10> WL_O<9> WL_O<8> WL_O<7> WL_O<6> WL_O<5> WL_O<4> WL_O<3> ++ WL_O<2> WL_O<1> WL_O<0> VDD VSS +XDEC10 ADDR_N_I<5> ADDR_N_I<4> CS_I CS00<2> VDD VSS / ++ RM_IHPSG13_1024x32_c2_2P_DEC02 +XDEC00 ADDR_N_I<5> ADDR_N_I<4> CS_I CS00<0> VDD VSS / ++ RM_IHPSG13_1024x32_c2_2P_DEC00 +XSEL<3> ADDR_N_I<3> ADDR_N_I<2> ADDR_N_I<1> ADDR_N_I<0> CS00<3> ECLK_H<3> ++ ECLK_H<4> ECLK_B<3> ECLK_B<4> WL_O<63> WL_O<62> WL_O<61> WL_O<60> WL_O<59> ++ WL_O<58> WL_O<57> WL_O<56> WL_O<55> WL_O<54> WL_O<53> WL_O<52> WL_O<51> ++ WL_O<50> WL_O<49> WL_O<48> VDD VSS / RM_IHPSG13_1024x32_c2_2P_DEC04 +XSEL<2> ADDR_N_I<3> ADDR_N_I<2> ADDR_N_I<1> ADDR_N_I<0> CS00<2> ECLK_H<2> ++ ECLK_H<3> ECLK_B<2> ECLK_B<3> WL_O<47> WL_O<46> WL_O<45> WL_O<44> WL_O<43> ++ WL_O<42> WL_O<41> WL_O<40> WL_O<39> WL_O<38> WL_O<37> WL_O<36> WL_O<35> ++ WL_O<34> WL_O<33> WL_O<32> VDD VSS / RM_IHPSG13_1024x32_c2_2P_DEC04 +XSEL<1> ADDR_N_I<3> ADDR_N_I<2> ADDR_N_I<1> ADDR_N_I<0> CS00<1> ECLK_H<1> ++ ECLK_H<2> ECLK_B<1> ECLK_B<2> WL_O<31> WL_O<30> WL_O<29> WL_O<28> WL_O<27> ++ WL_O<26> WL_O<25> WL_O<24> WL_O<23> WL_O<22> WL_O<21> WL_O<20> WL_O<19> ++ WL_O<18> WL_O<17> WL_O<16> VDD VSS / RM_IHPSG13_1024x32_c2_2P_DEC04 +XSEL<0> ADDR_N_I<3> ADDR_N_I<2> ADDR_N_I<1> ADDR_N_I<0> CS00<0> ECLK_I ++ ECLK_H<1> ECLK_B<0> ECLK_B<1> WL_O<15> WL_O<14> WL_O<13> WL_O<12> WL_O<11> ++ WL_O<10> WL_O<9> WL_O<8> WL_O<7> WL_O<6> WL_O<5> WL_O<4> WL_O<3> WL_O<2> ++ WL_O<1> WL_O<0> VDD VSS / RM_IHPSG13_1024x32_c2_2P_DEC04 +XDEC11 ADDR_N_I<5> ADDR_N_I<4> CS_I CS00<3> VDD VSS / ++ RM_IHPSG13_1024x32_c2_2P_DEC03 +XL2<36> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<35> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<34> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<33> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<32> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<31> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<30> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<29> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<28> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<27> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<26> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<25> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<24> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<23> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<22> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<21> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<20> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<19> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<18> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<17> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<16> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<15> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<14> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<13> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<12> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<11> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<10> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<9> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<8> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<7> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<6> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<5> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<4> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<3> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<2> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<1> VDD VSS / RSC_IHPSG13_FILLCAP8 +XDEC01 ADDR_N_I<5> ADDR_N_I<4> CS_I CS00<1> VDD VSS / ++ RM_IHPSG13_1024x32_c2_2P_DEC01 +.ENDS +.SUBCKT RM_IHPSG13_1024x32_c2_2P_ROWREG6 ACLK_N_I ADDR_I<5> ADDR_I<4> ADDR_I<3> ADDR_I<2> ++ ADDR_I<1> ADDR_I<0> ADDR_N_O<5> ADDR_N_O<4> ADDR_N_O<3> ADDR_N_O<2> ++ ADDR_N_O<1> ADDR_N_O<0> BIST_ADDR_I<5> BIST_ADDR_I<4> BIST_ADDR_I<3> ++ BIST_ADDR_I<2> BIST_ADDR_I<1> BIST_ADDR_I<0> BIST_EN_I VDD VSS +XINV<5> q_int<5> qn_int<5> VDD VSS / RSC_IHPSG13_CINVX2 +XINV<4> q_int<4> qn_int<4> VDD VSS / RSC_IHPSG13_CINVX2 +XINV<3> q_int<3> qn_int<3> VDD VSS / RSC_IHPSG13_CINVX2 +XINV<2> q_int<2> qn_int<2> VDD VSS / RSC_IHPSG13_CINVX2 +XINV<1> q_int<1> qn_int<1> VDD VSS / RSC_IHPSG13_CINVX2 +XINV<0> q_int<0> qn_int<0> VDD VSS / RSC_IHPSG13_CINVX2 +XDRV<5> qn_int<5> ADDR_N_O<5> VDD VSS / RSC_IHPSG13_CINVX8 +XDRV<4> qn_int<4> ADDR_N_O<4> VDD VSS / RSC_IHPSG13_CINVX8 +XDRV<3> qn_int<3> ADDR_N_O<3> VDD VSS / RSC_IHPSG13_CINVX8 +XDRV<2> qn_int<2> ADDR_N_O<2> VDD VSS / RSC_IHPSG13_CINVX8 +XDRV<1> qn_int<1> ADDR_N_O<1> VDD VSS / RSC_IHPSG13_CINVX8 +XDRV<0> qn_int<0> ADDR_N_O<0> VDD VSS / RSC_IHPSG13_CINVX8 +XDFF<5> BIST_EN_I BIST_ADDR_I<5> ACLK_N_I ADDR_I<5> q_int<5> net2<0> VDD ++ VSS / RSC_IHPSG13_DFNQMX2IX1 +XDFF<4> BIST_EN_I BIST_ADDR_I<4> ACLK_N_I ADDR_I<4> q_int<4> net2<1> VDD ++ VSS / RSC_IHPSG13_DFNQMX2IX1 +XDFF<3> BIST_EN_I BIST_ADDR_I<3> ACLK_N_I ADDR_I<3> q_int<3> net2<2> VDD ++ VSS / RSC_IHPSG13_DFNQMX2IX1 +XDFF<2> BIST_EN_I BIST_ADDR_I<2> ACLK_N_I ADDR_I<2> q_int<2> net2<3> VDD ++ VSS / RSC_IHPSG13_DFNQMX2IX1 +XDFF<1> BIST_EN_I BIST_ADDR_I<1> ACLK_N_I ADDR_I<1> q_int<1> net2<4> VDD ++ VSS / RSC_IHPSG13_DFNQMX2IX1 +XDFF<0> BIST_EN_I BIST_ADDR_I<0> ACLK_N_I ADDR_I<0> q_int<0> net2<5> VDD ++ VSS / RSC_IHPSG13_DFNQMX2IX1 +XI11<12> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI11<11> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI11<10> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI11<9> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI11<8> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI11<7> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI11<6> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI11<5> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI11<4> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI11<3> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI11<2> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI11<1> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI12<2> VDD VSS / RSC_IHPSG13_FILLCAP4 +XI12<1> VDD VSS / RSC_IHPSG13_FILLCAP4 +XI12<0> VDD VSS / RSC_IHPSG13_FILLCAP4 +.ENDS + +.SUBCKT RM_IHPSG13_1024x32_c2_2P_COLDRV13X16 ADDR_COL_I<1> ADDR_COL_I<0> ADDR_COL_O<1> ++ ADDR_COL_O<0> ADDR_DEC_I<7> ADDR_DEC_I<6> ADDR_DEC_I<5> ADDR_DEC_I<4> ++ ADDR_DEC_I<3> ADDR_DEC_I<2> ADDR_DEC_I<1> ADDR_DEC_I<0> ADDR_DEC_O<7> ++ ADDR_DEC_O<6> ADDR_DEC_O<5> ADDR_DEC_O<4> ADDR_DEC_O<3> ADDR_DEC_O<2> ++ ADDR_DEC_O<1> ADDR_DEC_O<0> DCLK_I DCLK_O RCLK_I RCLK_O WCLK_I WCLK_O ++ VDD VSS +XI0<7> VDD VSS / RSC_IHPSG13_FILLCAP4 +XI0<6> VDD VSS / RSC_IHPSG13_FILLCAP4 +XI0<5> VDD VSS / RSC_IHPSG13_FILLCAP4 +XI0<4> VDD VSS / RSC_IHPSG13_FILLCAP4 +XI0<3> VDD VSS / RSC_IHPSG13_FILLCAP4 +XI0<2> VDD VSS / RSC_IHPSG13_FILLCAP4 +XI0<1> VDD VSS / RSC_IHPSG13_FILLCAP4 +XWCLK_DRV WCLK_I WCLK_O VDD VSS / RSC_IHPSG13_CBUFX16 +XRCLK_DRV RCLK_I RCLK_O VDD VSS / RSC_IHPSG13_CBUFX16 +XDCLK_DRV DCLK_I DCLK_O VDD VSS / RSC_IHPSG13_CBUFX16 +XADDR_COL_DRV<1> ADDR_COL_I<1> ADDR_COL_O<1> VDD VSS / ++ RSC_IHPSG13_CBUFX16 +XADDR_COL_DRV<0> ADDR_COL_I<0> ADDR_COL_O<0> VDD VSS / ++ RSC_IHPSG13_CBUFX16 +XADDR_DEC_DRV<7> ADDR_DEC_I<7> ADDR_DEC_O<7> VDD VSS / ++ RSC_IHPSG13_CBUFX16 +XADDR_DEC_DRV<6> ADDR_DEC_I<6> ADDR_DEC_O<6> VDD VSS / ++ RSC_IHPSG13_CBUFX16 +XADDR_DEC_DRV<5> ADDR_DEC_I<5> ADDR_DEC_O<5> VDD VSS / ++ RSC_IHPSG13_CBUFX16 +XADDR_DEC_DRV<4> ADDR_DEC_I<4> ADDR_DEC_O<4> VDD VSS / ++ RSC_IHPSG13_CBUFX16 +XADDR_DEC_DRV<3> ADDR_DEC_I<3> ADDR_DEC_O<3> VDD VSS / ++ RSC_IHPSG13_CBUFX16 +XADDR_DEC_DRV<2> ADDR_DEC_I<2> ADDR_DEC_O<2> VDD VSS / ++ RSC_IHPSG13_CBUFX16 +XADDR_DEC_DRV<1> ADDR_DEC_I<1> ADDR_DEC_O<1> VDD VSS / ++ RSC_IHPSG13_CBUFX16 +XADDR_DEC_DRV<0> ADDR_DEC_I<0> ADDR_DEC_O<0> VDD VSS / ++ RSC_IHPSG13_CBUFX16 +XI1<5> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI1<4> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI1<3> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI1<2> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI1<1> VDD VSS / RSC_IHPSG13_FILLCAP8 +.ENDS +.SUBCKT RM_IHPSG13_1024x32_c2_2P_WLDRV16X16 A<15> A<14> A<13> A<12> A<11> A<10> A<9> A<8> ++ A<7> A<6> A<5> A<4> A<3> A<2> A<1> A<0> Z<15> Z<14> Z<13> Z<12> Z<11> Z<10> ++ Z<9> Z<8> Z<7> Z<6> Z<5> Z<4> Z<3> Z<2> Z<1> Z<0> VDD VSS +XBUF<15> A<15> Z<15> VDD VSS / RSC_IHPSG13_WLDRVX16 +XBUF<14> A<14> Z<14> VDD VSS / RSC_IHPSG13_WLDRVX16 +XBUF<13> A<13> Z<13> VDD VSS / RSC_IHPSG13_WLDRVX16 +XBUF<12> A<12> Z<12> VDD VSS / RSC_IHPSG13_WLDRVX16 +XBUF<11> A<11> Z<11> VDD VSS / RSC_IHPSG13_WLDRVX16 +XBUF<10> A<10> Z<10> VDD VSS / RSC_IHPSG13_WLDRVX16 +XBUF<9> A<9> Z<9> VDD VSS / RSC_IHPSG13_WLDRVX16 +XBUF<8> A<8> Z<8> VDD VSS / RSC_IHPSG13_WLDRVX16 +XBUF<7> A<7> Z<7> VDD VSS / RSC_IHPSG13_WLDRVX16 +XBUF<6> A<6> Z<6> VDD VSS / RSC_IHPSG13_WLDRVX16 +XBUF<5> A<5> Z<5> VDD VSS / RSC_IHPSG13_WLDRVX16 +XBUF<4> A<4> Z<4> VDD VSS / RSC_IHPSG13_WLDRVX16 +XBUF<3> A<3> Z<3> VDD VSS / RSC_IHPSG13_WLDRVX16 +XBUF<2> A<2> Z<2> VDD VSS / RSC_IHPSG13_WLDRVX16 +XBUF<1> A<1> Z<1> VDD VSS / RSC_IHPSG13_WLDRVX16 +XBUF<0> A<0> Z<0> VDD VSS / RSC_IHPSG13_WLDRVX16 +.ENDS + + +.SUBCKT RM_IHPSG13_1024x32_c2_1P_DEC01 ADDR<1> ADDR<0> CS CS_OUT VDD VSS +XDECINV net1 CS_OUT VDD VSS / RSC_IHPSG13_INVX4 +XDEC NADDR<1> ADDR<0> CS net1 VDD VSS / RSC_IHPSG13_NAND3X2 +XI2 VDD VSS / RSC_IHPSG13_FILLCAP4 +XADDRINV ADDR<1> NADDR<1> VDD VSS / RSC_IHPSG13_INVX2 +.ENDS +.SUBCKT RM_IHPSG13_1024x32_c2_1P_DEC00 ADDR<1> ADDR<0> CS CS_OUT VDD VSS +XDECINV net1 CS_OUT VDD VSS / RSC_IHPSG13_INVX4 +XDEC NADDR<1> NADDR<0> CS net1 VDD VSS / RSC_IHPSG13_NAND3X2 +XADDRINV<1> ADDR<1> NADDR<1> VDD VSS / RSC_IHPSG13_INVX2 +XADDRINV<0> ADDR<0> NADDR<0> VDD VSS / RSC_IHPSG13_INVX2 +XI1 VDD VSS / RSC_IHPSG13_FILLCAP4 +.ENDS +.SUBCKT RM_IHPSG13_1024x32_c2_1P_ROWDEC5 ADDR_N_I<4> ADDR_N_I<3> ADDR_N_I<2> ADDR_N_I<1> ++ ADDR_N_I<0> CS_I ECLK_I WL_O<31> WL_O<30> WL_O<29> WL_O<28> WL_O<27> ++ WL_O<26> WL_O<25> WL_O<24> WL_O<23> WL_O<22> WL_O<21> WL_O<20> WL_O<19> ++ WL_O<18> WL_O<17> WL_O<16> WL_O<15> WL_O<14> WL_O<13> WL_O<12> WL_O<11> ++ WL_O<10> WL_O<9> WL_O<8> WL_O<7> WL_O<6> WL_O<5> WL_O<4> WL_O<3> WL_O<2> ++ WL_O<1> WL_O<0> VDD VSS +XL2<12> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<11> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<10> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<9> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<8> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<7> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<6> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<5> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<4> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<3> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<2> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<1> VDD VSS / RSC_IHPSG13_FILLCAP8 +XDEC01 ADDR_N_I<5> ADDR_N_I<4> CS_I CS00<1> VDD VSS / ++ RM_IHPSG13_1024x32_c2_1P_DEC01 +XDEC00 ADDR_N_I<5> ADDR_N_I<4> CS_I CS00<0> VDD VSS / ++ RM_IHPSG13_1024x32_c2_1P_DEC00 +XSEL<1> ADDR_N_I<3> ADDR_N_I<2> ADDR_N_I<1> ADDR_N_I<0> CS00<1> ECLK_H<1> ++ ECLK_H<2> ECLK_B<1> ECLK_B<2> WL_O<31> WL_O<30> WL_O<29> WL_O<28> WL_O<27> ++ WL_O<26> WL_O<25> WL_O<24> WL_O<23> WL_O<22> WL_O<21> WL_O<20> WL_O<19> ++ WL_O<18> WL_O<17> WL_O<16> VDD VSS / RM_IHPSG13_1024x32_c2_1P_DEC04 +XSEL<0> ADDR_N_I<3> ADDR_N_I<2> ADDR_N_I<1> ADDR_N_I<0> CS00<0> ECLK_I ++ ECLK_H<1> ECLK_B<0> ECLK_B<1> WL_O<15> WL_O<14> WL_O<13> WL_O<12> WL_O<11> ++ WL_O<10> WL_O<9> WL_O<8> WL_O<7> WL_O<6> WL_O<5> WL_O<4> WL_O<3> WL_O<2> ++ WL_O<1> WL_O<0> VDD VSS / RM_IHPSG13_1024x32_c2_1P_DEC04 +XI0 ADDR_N_I<5> VDD VSS / RSC_IHPSG13_TIEL +.ENDS +.SUBCKT RM_IHPSG13_1024x32_c2_1P_ROWREG5 ACLK_N_I ADDR_I<4> ADDR_I<3> ADDR_I<2> ADDR_I<1> ++ ADDR_I<0> ADDR_N_O<4> ADDR_N_O<3> ADDR_N_O<2> ADDR_N_O<1> ADDR_N_O<0> ++ BIST_ADDR_I<4> BIST_ADDR_I<3> BIST_ADDR_I<2> BIST_ADDR_I<1> BIST_ADDR_I<0> ++ BIST_EN_I VDD VSS +XINV<4> q_int<4> qn_int<4> VDD VSS / RSC_IHPSG13_CINVX2 +XINV<3> q_int<3> qn_int<3> VDD VSS / RSC_IHPSG13_CINVX2 +XINV<2> q_int<2> qn_int<2> VDD VSS / RSC_IHPSG13_CINVX2 +XINV<1> q_int<1> qn_int<1> VDD VSS / RSC_IHPSG13_CINVX2 +XINV<0> q_int<0> qn_int<0> VDD VSS / RSC_IHPSG13_CINVX2 +XDRV<4> qn_int<4> ADDR_N_O<4> VDD VSS / RSC_IHPSG13_CINVX8 +XDRV<3> qn_int<3> ADDR_N_O<3> VDD VSS / RSC_IHPSG13_CINVX8 +XDRV<2> qn_int<2> ADDR_N_O<2> VDD VSS / RSC_IHPSG13_CINVX8 +XDRV<1> qn_int<1> ADDR_N_O<1> VDD VSS / RSC_IHPSG13_CINVX8 +XDRV<0> qn_int<0> ADDR_N_O<0> VDD VSS / RSC_IHPSG13_CINVX8 +XDFF<4> BIST_EN_I BIST_ADDR_I<4> ACLK_N_I ADDR_I<4> q_int<4> net2<0> VDD ++ VSS / RSC_IHPSG13_DFNQMX2IX1 +XDFF<3> BIST_EN_I BIST_ADDR_I<3> ACLK_N_I ADDR_I<3> q_int<3> net2<1> VDD ++ VSS / RSC_IHPSG13_DFNQMX2IX1 +XDFF<2> BIST_EN_I BIST_ADDR_I<2> ACLK_N_I ADDR_I<2> q_int<2> net2<2> VDD ++ VSS / RSC_IHPSG13_DFNQMX2IX1 +XDFF<1> BIST_EN_I BIST_ADDR_I<1> ACLK_N_I ADDR_I<1> q_int<1> net2<3> VDD ++ VSS / RSC_IHPSG13_DFNQMX2IX1 +XDFF<0> BIST_EN_I BIST_ADDR_I<0> ACLK_N_I ADDR_I<0> q_int<0> net2<4> VDD ++ VSS / RSC_IHPSG13_DFNQMX2IX1 +XI11<16> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI11<15> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI11<14> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI11<13> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI11<12> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI11<11> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI11<10> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI11<9> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI11<8> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI11<7> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI11<6> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI11<5> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI11<4> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI11<3> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI11<2> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI11<1> VDD VSS / RSC_IHPSG13_FILLCAP8 +.ENDS + + +.SUBCKT RM_IHPSG13_1024x32_c2_1P_COLDEC5 ACLK_N ADDR<4> ADDR<3> ADDR<2> ADDR<1> ADDR<0> ++ ADDR_COL<1> ADDR_COL<0> ADDR_DEC<7> ADDR_DEC<6> ADDR_DEC<5> ADDR_DEC<4> ++ ADDR_DEC<3> ADDR_DEC<2> ADDR_DEC<1> ADDR_DEC<0> BIST_ADDR<4> BIST_ADDR<3> ++ BIST_ADDR<2> BIST_ADDR<1> BIST_ADDR<0> BIST_EN_I VDD VSS +XI17<2> VDD VSS / RSC_IHPSG13_FILLCAP4 +XI17<1> VDD VSS / RSC_IHPSG13_FILLCAP4 +XI13<1> addr_int<1> ADDR_COL<1> VDD VSS / RSC_IHPSG13_CBUFX2 +XI13<0> addr_int<0> ADDR_COL<0> VDD VSS / RSC_IHPSG13_CBUFX2 +XDFF<4> BIST_EN_I BIST_ADDR<4> ACLK_N ADDR<4> addr_int<1> net7<0> VDD ++ VSS / RSC_IHPSG13_DFNQMX2IX1 +XDFF<3> BIST_EN_I BIST_ADDR<3> ACLK_N ADDR<3> addr_int<0> net7<1> VDD ++ VSS / RSC_IHPSG13_DFNQMX2IX1 +XDFF<2> BIST_EN_I BIST_ADDR<2> ACLK_N ADDR<2> padr_int<2> net7<2> VDD ++ VSS / RSC_IHPSG13_DFNQMX2IX1 +XDFF<1> BIST_EN_I BIST_ADDR<1> ACLK_N ADDR<1> padr_int<1> net7<3> VDD ++ VSS / RSC_IHPSG13_DFNQMX2IX1 +XDFF<0> BIST_EN_I BIST_ADDR<0> ACLK_N ADDR<0> padr_int<0> net7<4> VDD ++ VSS / RSC_IHPSG13_DFNQMX2IX1 +XI1<7> PADR<0> PADR<1> PADR<2> addr_n<7> VDD VSS / RSC_IHPSG13_NAND3X2 +XI1<6> NADR<0> PADR<1> PADR<2> addr_n<6> VDD VSS / RSC_IHPSG13_NAND3X2 +XI1<5> PADR<0> NADR<1> PADR<2> addr_n<5> VDD VSS / RSC_IHPSG13_NAND3X2 +XI1<4> NADR<0> NADR<1> PADR<2> addr_n<4> VDD VSS / RSC_IHPSG13_NAND3X2 +XI1<3> PADR<0> PADR<1> NADR<2> addr_n<3> VDD VSS / RSC_IHPSG13_NAND3X2 +XI1<2> NADR<0> PADR<1> NADR<2> addr_n<2> VDD VSS / RSC_IHPSG13_NAND3X2 +XI1<1> PADR<0> NADR<1> NADR<2> addr_n<1> VDD VSS / RSC_IHPSG13_NAND3X2 +XI1<0> NADR<0> NADR<1> NADR<2> addr_n<0> VDD VSS / RSC_IHPSG13_NAND3X2 +XI15<2> NADR<2> PADR<2> VDD VSS / RSC_IHPSG13_INVX2 +XI15<1> NADR<1> PADR<1> VDD VSS / RSC_IHPSG13_INVX2 +XI15<0> NADR<0> PADR<0> VDD VSS / RSC_IHPSG13_INVX2 +XI3<2> padr_int<2> NADR<2> VDD VSS / RSC_IHPSG13_INVX2 +XI3<1> padr_int<1> NADR<1> VDD VSS / RSC_IHPSG13_INVX2 +XI3<0> padr_int<0> NADR<0> VDD VSS / RSC_IHPSG13_INVX2 +XI2<7> addr_n<7> ADDR_DEC<7> VDD VSS / RSC_IHPSG13_INVX2 +XI2<6> addr_n<6> ADDR_DEC<6> VDD VSS / RSC_IHPSG13_INVX2 +XI2<5> addr_n<5> ADDR_DEC<5> VDD VSS / RSC_IHPSG13_INVX2 +XI2<4> addr_n<4> ADDR_DEC<4> VDD VSS / RSC_IHPSG13_INVX2 +XI2<3> addr_n<3> ADDR_DEC<3> VDD VSS / RSC_IHPSG13_INVX2 +XI2<2> addr_n<2> ADDR_DEC<2> VDD VSS / RSC_IHPSG13_INVX2 +XI2<1> addr_n<1> ADDR_DEC<1> VDD VSS / RSC_IHPSG13_INVX2 +XI2<0> addr_n<0> ADDR_DEC<0> VDD VSS / RSC_IHPSG13_INVX2 +.ENDS +.SUBCKT RM_IHPSG13_1024x32_c2_1P_COLCTRL5 A_ADDR_COL<1> A_ADDR_COL<0> A_ADDR_DEC<7> ++ A_ADDR_DEC<6> A_ADDR_DEC<5> A_ADDR_DEC<4> A_ADDR_DEC<3> A_ADDR_DEC<2> ++ A_ADDR_DEC<1> A_ADDR_DEC<0> A_BIST_BM_I A_BIST_DW_I A_BIST_EN_I A_BLC<31> ++ A_BLC<30> A_BLC<29> A_BLC<28> A_BLC<27> A_BLC<26> A_BLC<25> A_BLC<24> ++ A_BLC<23> A_BLC<22> A_BLC<21> A_BLC<20> A_BLC<19> A_BLC<18> A_BLC<17> ++ A_BLC<16> A_BLC<15> A_BLC<14> A_BLC<13> A_BLC<12> A_BLC<11> A_BLC<10> ++ A_BLC<9> A_BLC<8> A_BLC<7> A_BLC<6> A_BLC<5> A_BLC<4> A_BLC<3> A_BLC<2> ++ A_BLC<1> A_BLC<0> A_BLT<31> A_BLT<30> A_BLT<29> A_BLT<28> A_BLT<27> ++ A_BLT<26> A_BLT<25> A_BLT<24> A_BLT<23> A_BLT<22> A_BLT<21> A_BLT<20> ++ A_BLT<19> A_BLT<18> A_BLT<17> A_BLT<16> A_BLT<15> A_BLT<14> A_BLT<13> ++ A_BLT<12> A_BLT<11> A_BLT<10> A_BLT<9> A_BLT<8> A_BLT<7> A_BLT<6> A_BLT<5> ++ A_BLT<4> A_BLT<3> A_BLT<2> A_BLT<1> A_BLT<0> A_BM_I A_DCLK_B_L A_DCLK_B_R ++ A_DCLK_L A_DCLK_R A_DR_O A_DW_I A_RCLK_B_L A_RCLK_B_R A_RCLK_L A_RCLK_R ++ A_TIEH_O A_WCLK_B_L A_WCLK_B_R A_WCLK_L A_WCLK_R VDD VSS +XA_I80<1> A_WCLK_B_L A_RCLK_B_L A_W_nor_R<1> VDD VSS / ++ RSC_IHPSG13_AND2X2 +XA_I80<0> A_WCLK_B_L A_RCLK_B_L A_W_nor_R<0> VDD VSS / ++ RSC_IHPSG13_AND2X2 +XA_I44 A_BM_N A_WCLK_B_L A_DO_WRITE_P VDD VSS / RSC_IHPSG13_NOR2X2 +XI80<29> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI80<28> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI80<27> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI80<26> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI80<25> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI80<24> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI80<23> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI80<22> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI80<21> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI80<20> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI80<19> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI80<18> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI80<17> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI80<16> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI80<15> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI80<14> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI80<13> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI80<12> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI80<11> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI80<10> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI80<9> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI80<8> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI80<7> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI80<6> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI80<5> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI80<4> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI80<3> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI80<2> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI80<1> VDD VSS / RSC_IHPSG13_FILLCAP8 +XA_I74<16> VDD VSS / RSC_IHPSG13_FILLCAP8 +XA_I74<15> VDD VSS / RSC_IHPSG13_FILLCAP8 +XA_I74<14> VDD VSS / RSC_IHPSG13_FILLCAP8 +XA_I74<13> VDD VSS / RSC_IHPSG13_FILLCAP8 +XA_I74<12> VDD VSS / RSC_IHPSG13_FILLCAP8 +XA_I74<11> VDD VSS / RSC_IHPSG13_FILLCAP8 +XA_I74<10> VDD VSS / RSC_IHPSG13_FILLCAP8 +XA_I74<9> VDD VSS / RSC_IHPSG13_FILLCAP8 +XA_I74<8> VDD VSS / RSC_IHPSG13_FILLCAP8 +XA_I74<7> VDD VSS / RSC_IHPSG13_FILLCAP8 +XA_I74<6> VDD VSS / RSC_IHPSG13_FILLCAP8 +XA_I74<5> VDD VSS / RSC_IHPSG13_FILLCAP8 +XA_I74<4> VDD VSS / RSC_IHPSG13_FILLCAP8 +XA_I74<3> VDD VSS / RSC_IHPSG13_FILLCAP8 +XA_I74<2> VDD VSS / RSC_IHPSG13_FILLCAP8 +XA_I74<1> VDD VSS / RSC_IHPSG13_FILLCAP8 +XA_INV<6> A_N1<1> A_P1<1> VDD VSS / RSC_IHPSG13_CINVX4 +XA_INV<5> A_N0<1> A_P0<1> VDD VSS / RSC_IHPSG13_CINVX4 +XA_INV<4> A_N0<0> A_P0<0> VDD VSS / RSC_IHPSG13_CINVX4 +XA_INV<3> A_ADDR_COL<1> A_N1<1> VDD VSS / RSC_IHPSG13_CINVX4 +XA_INV<2> A_ADDR_COL<1> A_N1<0> VDD VSS / RSC_IHPSG13_CINVX4 +XA_INV<1> A_ADDR_COL<0> A_N0<1> VDD VSS / RSC_IHPSG13_CINVX4 +XA_INV<0> A_ADDR_COL<0> A_N0<0> VDD VSS / RSC_IHPSG13_CINVX4 +XA_I81<3> A_W_nor_R<1> A_PRE_N VDD VSS / RSC_IHPSG13_CINVX4_WN +XA_I81<2> A_W_nor_R<1> A_PRE_N VDD VSS / RSC_IHPSG13_CINVX4_WN +XA_I81<1> A_W_nor_R<0> A_PRE_N VDD VSS / RSC_IHPSG13_CINVX4_WN +XA_I81<0> A_W_nor_R<0> A_PRE_N VDD VSS / RSC_IHPSG13_CINVX4_WN +XA_BLTMUX<31> A_BLC<31> A_BLC_SEL A_BLT<31> A_BLT_SEL A_PRE_N A_SEL_P<31> ++ A_WR_ONE A_WR_ZERO VDD VSS / RM_IHPSG13_1024x32_c2_1P_BLDRV +XA_BLTMUX<30> A_BLC<30> A_BLC_SEL A_BLT<30> A_BLT_SEL A_PRE_N A_SEL_P<30> ++ A_WR_ONE A_WR_ZERO VDD VSS / RM_IHPSG13_1024x32_c2_1P_BLDRV +XA_BLTMUX<29> A_BLC<29> A_BLC_SEL A_BLT<29> A_BLT_SEL A_PRE_N A_SEL_P<29> ++ A_WR_ONE A_WR_ZERO VDD VSS / RM_IHPSG13_1024x32_c2_1P_BLDRV +XA_BLTMUX<28> A_BLC<28> A_BLC_SEL A_BLT<28> A_BLT_SEL A_PRE_N A_SEL_P<28> ++ A_WR_ONE A_WR_ZERO VDD VSS / RM_IHPSG13_1024x32_c2_1P_BLDRV +XA_BLTMUX<27> A_BLC<27> A_BLC_SEL A_BLT<27> A_BLT_SEL A_PRE_N A_SEL_P<27> ++ A_WR_ONE A_WR_ZERO VDD VSS / RM_IHPSG13_1024x32_c2_1P_BLDRV +XA_BLTMUX<26> A_BLC<26> A_BLC_SEL A_BLT<26> A_BLT_SEL A_PRE_N A_SEL_P<26> ++ A_WR_ONE A_WR_ZERO VDD VSS / RM_IHPSG13_1024x32_c2_1P_BLDRV +XA_BLTMUX<25> A_BLC<25> A_BLC_SEL A_BLT<25> A_BLT_SEL A_PRE_N A_SEL_P<25> ++ A_WR_ONE A_WR_ZERO VDD VSS / RM_IHPSG13_1024x32_c2_1P_BLDRV +XA_BLTMUX<24> A_BLC<24> A_BLC_SEL A_BLT<24> A_BLT_SEL A_PRE_N A_SEL_P<24> ++ A_WR_ONE A_WR_ZERO VDD VSS / RM_IHPSG13_1024x32_c2_1P_BLDRV +XA_BLTMUX<23> A_BLC<23> A_BLC_SEL A_BLT<23> A_BLT_SEL A_PRE_N A_SEL_P<23> ++ A_WR_ONE A_WR_ZERO VDD VSS / RM_IHPSG13_1024x32_c2_1P_BLDRV +XA_BLTMUX<22> A_BLC<22> A_BLC_SEL A_BLT<22> A_BLT_SEL A_PRE_N A_SEL_P<22> ++ A_WR_ONE A_WR_ZERO VDD VSS / RM_IHPSG13_1024x32_c2_1P_BLDRV +XA_BLTMUX<21> A_BLC<21> A_BLC_SEL A_BLT<21> A_BLT_SEL A_PRE_N A_SEL_P<21> ++ A_WR_ONE A_WR_ZERO VDD VSS / RM_IHPSG13_1024x32_c2_1P_BLDRV +XA_BLTMUX<20> A_BLC<20> A_BLC_SEL A_BLT<20> A_BLT_SEL A_PRE_N A_SEL_P<20> ++ A_WR_ONE A_WR_ZERO VDD VSS / RM_IHPSG13_1024x32_c2_1P_BLDRV +XA_BLTMUX<19> A_BLC<19> A_BLC_SEL A_BLT<19> A_BLT_SEL A_PRE_N A_SEL_P<19> ++ A_WR_ONE A_WR_ZERO VDD VSS / RM_IHPSG13_1024x32_c2_1P_BLDRV +XA_BLTMUX<18> A_BLC<18> A_BLC_SEL A_BLT<18> A_BLT_SEL A_PRE_N A_SEL_P<18> ++ A_WR_ONE A_WR_ZERO VDD VSS / RM_IHPSG13_1024x32_c2_1P_BLDRV +XA_BLTMUX<17> A_BLC<17> A_BLC_SEL A_BLT<17> A_BLT_SEL A_PRE_N A_SEL_P<17> ++ A_WR_ONE A_WR_ZERO VDD VSS / RM_IHPSG13_1024x32_c2_1P_BLDRV +XA_BLTMUX<16> A_BLC<16> A_BLC_SEL A_BLT<16> A_BLT_SEL A_PRE_N A_SEL_P<16> ++ A_WR_ONE A_WR_ZERO VDD VSS / RM_IHPSG13_1024x32_c2_1P_BLDRV +XA_BLTMUX<15> A_BLC<15> A_BLC_SEL A_BLT<15> A_BLT_SEL A_PRE_N A_SEL_P<15> ++ A_WR_ONE A_WR_ZERO VDD VSS / RM_IHPSG13_1024x32_c2_1P_BLDRV +XA_BLTMUX<14> A_BLC<14> A_BLC_SEL A_BLT<14> A_BLT_SEL A_PRE_N A_SEL_P<14> ++ A_WR_ONE A_WR_ZERO VDD VSS / RM_IHPSG13_1024x32_c2_1P_BLDRV +XA_BLTMUX<13> A_BLC<13> A_BLC_SEL A_BLT<13> A_BLT_SEL A_PRE_N A_SEL_P<13> ++ A_WR_ONE A_WR_ZERO VDD VSS / RM_IHPSG13_1024x32_c2_1P_BLDRV +XA_BLTMUX<12> A_BLC<12> A_BLC_SEL A_BLT<12> A_BLT_SEL A_PRE_N A_SEL_P<12> ++ A_WR_ONE A_WR_ZERO VDD VSS / RM_IHPSG13_1024x32_c2_1P_BLDRV +XA_BLTMUX<11> A_BLC<11> A_BLC_SEL A_BLT<11> A_BLT_SEL A_PRE_N A_SEL_P<11> ++ A_WR_ONE A_WR_ZERO VDD VSS / RM_IHPSG13_1024x32_c2_1P_BLDRV +XA_BLTMUX<10> A_BLC<10> A_BLC_SEL A_BLT<10> A_BLT_SEL A_PRE_N A_SEL_P<10> ++ A_WR_ONE A_WR_ZERO VDD VSS / RM_IHPSG13_1024x32_c2_1P_BLDRV +XA_BLTMUX<9> A_BLC<9> A_BLC_SEL A_BLT<9> A_BLT_SEL A_PRE_N A_SEL_P<9> A_WR_ONE ++ A_WR_ZERO VDD VSS / RM_IHPSG13_1024x32_c2_1P_BLDRV +XA_BLTMUX<8> A_BLC<8> A_BLC_SEL A_BLT<8> A_BLT_SEL A_PRE_N A_SEL_P<8> A_WR_ONE ++ A_WR_ZERO VDD VSS / RM_IHPSG13_1024x32_c2_1P_BLDRV +XA_BLTMUX<7> A_BLC<7> A_BLC_SEL A_BLT<7> A_BLT_SEL A_PRE_N A_SEL_P<7> A_WR_ONE ++ A_WR_ZERO VDD VSS / RM_IHPSG13_1024x32_c2_1P_BLDRV +XA_BLTMUX<6> A_BLC<6> A_BLC_SEL A_BLT<6> A_BLT_SEL A_PRE_N A_SEL_P<6> A_WR_ONE ++ A_WR_ZERO VDD VSS / RM_IHPSG13_1024x32_c2_1P_BLDRV +XA_BLTMUX<5> A_BLC<5> A_BLC_SEL A_BLT<5> A_BLT_SEL A_PRE_N A_SEL_P<5> A_WR_ONE ++ A_WR_ZERO VDD VSS / RM_IHPSG13_1024x32_c2_1P_BLDRV +XA_BLTMUX<4> A_BLC<4> A_BLC_SEL A_BLT<4> A_BLT_SEL A_PRE_N A_SEL_P<4> A_WR_ONE ++ A_WR_ZERO VDD VSS / RM_IHPSG13_1024x32_c2_1P_BLDRV +XA_BLTMUX<3> A_BLC<3> A_BLC_SEL A_BLT<3> A_BLT_SEL A_PRE_N A_SEL_P<3> A_WR_ONE ++ A_WR_ZERO VDD VSS / RM_IHPSG13_1024x32_c2_1P_BLDRV +XA_BLTMUX<2> A_BLC<2> A_BLC_SEL A_BLT<2> A_BLT_SEL A_PRE_N A_SEL_P<2> A_WR_ONE ++ A_WR_ZERO VDD VSS / RM_IHPSG13_1024x32_c2_1P_BLDRV +XA_BLTMUX<1> A_BLC<1> A_BLC_SEL A_BLT<1> A_BLT_SEL A_PRE_N A_SEL_P<1> A_WR_ONE ++ A_WR_ZERO VDD VSS / RM_IHPSG13_1024x32_c2_1P_BLDRV +XA_BLTMUX<0> A_BLC<0> A_BLC_SEL A_BLT<0> A_BLT_SEL A_PRE_N A_SEL_P<0> A_WR_ONE ++ A_WR_ZERO VDD VSS / RM_IHPSG13_1024x32_c2_1P_BLDRV +XA_CAPS<17> VDD VSS / RSC_IHPSG13_FILLCAP4 +XA_CAPS<16> VDD VSS / RSC_IHPSG13_FILLCAP4 +XA_CAPS<15> VDD VSS / RSC_IHPSG13_FILLCAP4 +XA_CAPS<14> VDD VSS / RSC_IHPSG13_FILLCAP4 +XA_CAPS<13> VDD VSS / RSC_IHPSG13_FILLCAP4 +XA_CAPS<12> VDD VSS / RSC_IHPSG13_FILLCAP4 +XA_CAPS<11> VDD VSS / RSC_IHPSG13_FILLCAP4 +XA_CAPS<10> VDD VSS / RSC_IHPSG13_FILLCAP4 +XA_CAPS<9> VDD VSS / RSC_IHPSG13_FILLCAP4 +XA_CAPS<8> VDD VSS / RSC_IHPSG13_FILLCAP4 +XA_CAPS<7> VDD VSS / RSC_IHPSG13_FILLCAP4 +XA_CAPS<6> VDD VSS / RSC_IHPSG13_FILLCAP4 +XA_CAPS<5> VDD VSS / RSC_IHPSG13_FILLCAP4 +XA_CAPS<4> VDD VSS / RSC_IHPSG13_FILLCAP4 +XA_CAPS<3> VDD VSS / RSC_IHPSG13_FILLCAP4 +XA_CAPS<2> VDD VSS / RSC_IHPSG13_FILLCAP4 +XA_CAPS<1> VDD VSS / RSC_IHPSG13_FILLCAP4 +XA_I51 net19 A_DR_O VDD VSS / RSC_IHPSG13_INVX4 +XA_I78 A_RCLK_B_L A_SAE VDD VSS / RSC_IHPSG13_CBUFX2 +XA_I69 A_DCLK_L A_DCLK_B_L VDD VSS / RSC_IHPSG13_CINVX8 +XA_I50 A_WCLK_L A_WCLK_B_L VDD VSS / RSC_IHPSG13_CINVX8 +XA_EBUF A_RCLK_L A_RCLK_B_L VDD VSS / RSC_IHPSG13_CINVX8 +XA_I76 A_DI_N A_DO_WRITE_P A_WR_ZERO VDD VSS / RSC_IHPSG13_AND2X6 +XA_I75 A_DI_R A_DO_WRITE_P A_WR_ONE VDD VSS / RSC_IHPSG13_AND2X6 +XA_I83 A_BM_R A_BM_N VDD VSS / RSC_IHPSG13_INVX2 +XA_DEC3INV<31> net23<0> A_SEL_P<31> VDD VSS / RSC_IHPSG13_INVX2 +XA_DEC3INV<30> net23<1> A_SEL_P<30> VDD VSS / RSC_IHPSG13_INVX2 +XA_DEC3INV<29> net23<2> A_SEL_P<29> VDD VSS / RSC_IHPSG13_INVX2 +XA_DEC3INV<28> net23<3> A_SEL_P<28> VDD VSS / RSC_IHPSG13_INVX2 +XA_DEC3INV<27> net23<4> A_SEL_P<27> VDD VSS / RSC_IHPSG13_INVX2 +XA_DEC3INV<26> net23<5> A_SEL_P<26> VDD VSS / RSC_IHPSG13_INVX2 +XA_DEC3INV<25> net23<6> A_SEL_P<25> VDD VSS / RSC_IHPSG13_INVX2 +XA_DEC3INV<24> net23<7> A_SEL_P<24> VDD VSS / RSC_IHPSG13_INVX2 +XA_DEC3INV<23> net23<8> A_SEL_P<23> VDD VSS / RSC_IHPSG13_INVX2 +XA_DEC3INV<22> net23<9> A_SEL_P<22> VDD VSS / RSC_IHPSG13_INVX2 +XA_DEC3INV<21> net23<10> A_SEL_P<21> VDD VSS / RSC_IHPSG13_INVX2 +XA_DEC3INV<20> net23<11> A_SEL_P<20> VDD VSS / RSC_IHPSG13_INVX2 +XA_DEC3INV<19> net23<12> A_SEL_P<19> VDD VSS / RSC_IHPSG13_INVX2 +XA_DEC3INV<18> net23<13> A_SEL_P<18> VDD VSS / RSC_IHPSG13_INVX2 +XA_DEC3INV<17> net23<14> A_SEL_P<17> VDD VSS / RSC_IHPSG13_INVX2 +XA_DEC3INV<16> net23<15> A_SEL_P<16> VDD VSS / RSC_IHPSG13_INVX2 +XA_DEC3INV<15> net23<16> A_SEL_P<15> VDD VSS / RSC_IHPSG13_INVX2 +XA_DEC3INV<14> net23<17> A_SEL_P<14> VDD VSS / RSC_IHPSG13_INVX2 +XA_DEC3INV<13> net23<18> A_SEL_P<13> VDD VSS / RSC_IHPSG13_INVX2 +XA_DEC3INV<12> net23<19> A_SEL_P<12> VDD VSS / RSC_IHPSG13_INVX2 +XA_DEC3INV<11> net23<20> A_SEL_P<11> VDD VSS / RSC_IHPSG13_INVX2 +XA_DEC3INV<10> net23<21> A_SEL_P<10> VDD VSS / RSC_IHPSG13_INVX2 +XA_DEC3INV<9> net23<22> A_SEL_P<9> VDD VSS / RSC_IHPSG13_INVX2 +XA_DEC3INV<8> net23<23> A_SEL_P<8> VDD VSS / RSC_IHPSG13_INVX2 +XA_DEC3INV<7> net23<24> A_SEL_P<7> VDD VSS / RSC_IHPSG13_INVX2 +XA_DEC3INV<6> net23<25> A_SEL_P<6> VDD VSS / RSC_IHPSG13_INVX2 +XA_DEC3INV<5> net23<26> A_SEL_P<5> VDD VSS / RSC_IHPSG13_INVX2 +XA_DEC3INV<4> net23<27> A_SEL_P<4> VDD VSS / RSC_IHPSG13_INVX2 +XA_DEC3INV<3> net23<28> A_SEL_P<3> VDD VSS / RSC_IHPSG13_INVX2 +XA_DEC3INV<2> net23<29> A_SEL_P<2> VDD VSS / RSC_IHPSG13_INVX2 +XA_DEC3INV<1> net23<30> A_SEL_P<1> VDD VSS / RSC_IHPSG13_INVX2 +XA_DEC3INV<0> net23<31> A_SEL_P<0> VDD VSS / RSC_IHPSG13_INVX2 +XA_I49 A_DI_R A_DI_N VDD VSS / RSC_IHPSG13_INVX2 +XA_ISENSE A_SAE A_BLC_SEL A_BLT_SEL net19 net20 VDD VSS / ++ RSC_IHPSG13_DFPQD_MSAFFX2 +XA_DREG A_BIST_EN_I A_BIST_DW_I A_DCLK_B_L A_DW_I A_DI_R net22 VDD VSS ++ / RSC_IHPSG13_DFNQMX2IX1 +XA_BREG A_BIST_EN_I A_BIST_BM_I A_DCLK_B_L A_BM_I A_BM_R net21 VDD VSS ++ / RSC_IHPSG13_DFNQMX2IX1 +XA_DEC3<31> A_P1<1> A_P0<1> A_ADDR_DEC<7> net23<0> VDD VSS / ++ RSC_IHPSG13_NAND3X2 +XA_DEC3<30> A_P1<1> A_P0<1> A_ADDR_DEC<6> net23<1> VDD VSS / ++ RSC_IHPSG13_NAND3X2 +XA_DEC3<29> A_P1<1> A_P0<1> A_ADDR_DEC<5> net23<2> VDD VSS / ++ RSC_IHPSG13_NAND3X2 +XA_DEC3<28> A_P1<1> A_P0<1> A_ADDR_DEC<4> net23<3> VDD VSS / ++ RSC_IHPSG13_NAND3X2 +XA_DEC3<27> A_P1<1> A_P0<1> A_ADDR_DEC<3> net23<4> VDD VSS / ++ RSC_IHPSG13_NAND3X2 +XA_DEC3<26> A_P1<1> A_P0<1> A_ADDR_DEC<2> net23<5> VDD VSS / ++ RSC_IHPSG13_NAND3X2 +XA_DEC3<25> A_P1<1> A_P0<1> A_ADDR_DEC<1> net23<6> VDD VSS / ++ RSC_IHPSG13_NAND3X2 +XA_DEC3<24> A_P1<1> A_P0<1> A_ADDR_DEC<0> net23<7> VDD VSS / ++ RSC_IHPSG13_NAND3X2 +XA_DEC3<23> A_P1<1> A_N0<1> A_ADDR_DEC<7> net23<8> VDD VSS / ++ RSC_IHPSG13_NAND3X2 +XA_DEC3<22> A_P1<1> A_N0<1> A_ADDR_DEC<6> net23<9> VDD VSS / ++ RSC_IHPSG13_NAND3X2 +XA_DEC3<21> A_P1<1> A_N0<1> A_ADDR_DEC<5> net23<10> VDD VSS / ++ RSC_IHPSG13_NAND3X2 +XA_DEC3<20> A_P1<1> A_N0<1> A_ADDR_DEC<4> net23<11> VDD VSS / ++ RSC_IHPSG13_NAND3X2 +XA_DEC3<19> A_P1<1> A_N0<1> A_ADDR_DEC<3> net23<12> VDD VSS / ++ RSC_IHPSG13_NAND3X2 +XA_DEC3<18> A_P1<1> A_N0<1> A_ADDR_DEC<2> net23<13> VDD VSS / ++ RSC_IHPSG13_NAND3X2 +XA_DEC3<17> A_P1<1> A_N0<1> A_ADDR_DEC<1> net23<14> VDD VSS / ++ RSC_IHPSG13_NAND3X2 +XA_DEC3<16> A_P1<1> A_N0<1> A_ADDR_DEC<0> net23<15> VDD VSS / ++ RSC_IHPSG13_NAND3X2 +XA_DEC3<15> A_N1<0> A_P0<0> A_ADDR_DEC<7> net23<16> VDD VSS / ++ RSC_IHPSG13_NAND3X2 +XA_DEC3<14> A_N1<0> A_P0<0> A_ADDR_DEC<6> net23<17> VDD VSS / ++ RSC_IHPSG13_NAND3X2 +XA_DEC3<13> A_N1<0> A_P0<0> A_ADDR_DEC<5> net23<18> VDD VSS / ++ RSC_IHPSG13_NAND3X2 +XA_DEC3<12> A_N1<0> A_P0<0> A_ADDR_DEC<4> net23<19> VDD VSS / ++ RSC_IHPSG13_NAND3X2 +XA_DEC3<11> A_N1<0> A_P0<0> A_ADDR_DEC<3> net23<20> VDD VSS / ++ RSC_IHPSG13_NAND3X2 +XA_DEC3<10> A_N1<0> A_P0<0> A_ADDR_DEC<2> net23<21> VDD VSS / ++ RSC_IHPSG13_NAND3X2 +XA_DEC3<9> A_N1<0> A_P0<0> A_ADDR_DEC<1> net23<22> VDD VSS / ++ RSC_IHPSG13_NAND3X2 +XA_DEC3<8> A_N1<0> A_P0<0> A_ADDR_DEC<0> net23<23> VDD VSS / ++ RSC_IHPSG13_NAND3X2 +XA_DEC3<7> A_N1<0> A_N0<0> A_ADDR_DEC<7> net23<24> VDD VSS / ++ RSC_IHPSG13_NAND3X2 +XA_DEC3<6> A_N1<0> A_N0<0> A_ADDR_DEC<6> net23<25> VDD VSS / ++ RSC_IHPSG13_NAND3X2 +XA_DEC3<5> A_N1<0> A_N0<0> A_ADDR_DEC<5> net23<26> VDD VSS / ++ RSC_IHPSG13_NAND3X2 +XA_DEC3<4> A_N1<0> A_N0<0> A_ADDR_DEC<4> net23<27> VDD VSS / ++ RSC_IHPSG13_NAND3X2 +XA_DEC3<3> A_N1<0> A_N0<0> A_ADDR_DEC<3> net23<28> VDD VSS / ++ RSC_IHPSG13_NAND3X2 +XA_DEC3<2> A_N1<0> A_N0<0> A_ADDR_DEC<2> net23<29> VDD VSS / ++ RSC_IHPSG13_NAND3X2 +XA_DEC3<1> A_N1<0> A_N0<0> A_ADDR_DEC<1> net23<30> VDD VSS / ++ RSC_IHPSG13_NAND3X2 +XA_DEC3<0> A_N1<0> A_N0<0> A_ADDR_DEC<0> net23<31> VDD VSS / ++ RSC_IHPSG13_NAND3X2 +XA_I89 A_DCLK_B_L A_DCLK_B_R / RSC_IHPSG13_MET3RES +XA_I91 A_RCLK_B_L A_RCLK_B_R / RSC_IHPSG13_MET3RES +XA_I90 A_WCLK_B_L A_WCLK_B_R / RSC_IHPSG13_MET3RES +XA_I88 A_DCLK_L A_DCLK_R / RSC_IHPSG13_MET3RES +XA_I87 A_WCLK_L A_WCLK_R / RSC_IHPSG13_MET3RES +XA_R2 A_RCLK_L A_RCLK_R / RSC_IHPSG13_MET3RES +XA_BM_TIEH A_TIEH_O VDD VSS / RSC_IHPSG13_TIEH +.ENDS + +.SUBCKT RM_IHPSG13_1024x32_c2_1P_COLDRV13X12 ADDR_COL_I<1> ADDR_COL_I<0> ADDR_COL_O<1> ++ ADDR_COL_O<0> ADDR_DEC_I<7> ADDR_DEC_I<6> ADDR_DEC_I<5> ADDR_DEC_I<4> ++ ADDR_DEC_I<3> ADDR_DEC_I<2> ADDR_DEC_I<1> ADDR_DEC_I<0> ADDR_DEC_O<7> ++ ADDR_DEC_O<6> ADDR_DEC_O<5> ADDR_DEC_O<4> ADDR_DEC_O<3> ADDR_DEC_O<2> ++ ADDR_DEC_O<1> ADDR_DEC_O<0> DCLK_I DCLK_O RCLK_I RCLK_O WCLK_I WCLK_O ++ VDD VSS +XI1<1> VDD VSS / RSC_IHPSG13_FILLCAP4 +XI1<0> VDD VSS / RSC_IHPSG13_FILLCAP4 +XI0<1> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI0<0> VDD VSS / RSC_IHPSG13_FILLCAP8 +XADDR_COL_DRV<1> ADDR_COL_I<1> ADDR_COL_O<1> VDD VSS / ++ RSC_IHPSG13_CBUFX12 +XADDR_COL_DRV<0> ADDR_COL_I<0> ADDR_COL_O<0> VDD VSS / ++ RSC_IHPSG13_CBUFX12 +XADDR_DEC_DRV<7> ADDR_DEC_I<7> ADDR_DEC_O<7> VDD VSS / ++ RSC_IHPSG13_CBUFX12 +XADDR_DEC_DRV<6> ADDR_DEC_I<6> ADDR_DEC_O<6> VDD VSS / ++ RSC_IHPSG13_CBUFX12 +XADDR_DEC_DRV<5> ADDR_DEC_I<5> ADDR_DEC_O<5> VDD VSS / ++ RSC_IHPSG13_CBUFX12 +XADDR_DEC_DRV<4> ADDR_DEC_I<4> ADDR_DEC_O<4> VDD VSS / ++ RSC_IHPSG13_CBUFX12 +XADDR_DEC_DRV<3> ADDR_DEC_I<3> ADDR_DEC_O<3> VDD VSS / ++ RSC_IHPSG13_CBUFX12 +XADDR_DEC_DRV<2> ADDR_DEC_I<2> ADDR_DEC_O<2> VDD VSS / ++ RSC_IHPSG13_CBUFX12 +XADDR_DEC_DRV<1> ADDR_DEC_I<1> ADDR_DEC_O<1> VDD VSS / ++ RSC_IHPSG13_CBUFX12 +XADDR_DEC_DRV<0> ADDR_DEC_I<0> ADDR_DEC_O<0> VDD VSS / ++ RSC_IHPSG13_CBUFX12 +XDCLK_DRV DCLK_I DCLK_O VDD VSS / RSC_IHPSG13_CBUFX12 +XRCLK_DRV RCLK_I RCLK_O VDD VSS / RSC_IHPSG13_CBUFX12 +XWCLK_DRV WCLK_I WCLK_O VDD VSS / RSC_IHPSG13_CBUFX12 +.ENDS +.SUBCKT RM_IHPSG13_1024x32_c2_1P_WLDRV16X12 A<15> A<14> A<13> A<12> A<11> A<10> A<9> A<8> ++ A<7> A<6> A<5> A<4> A<3> A<2> A<1> A<0> Z<15> Z<14> Z<13> Z<12> Z<11> Z<10> ++ Z<9> Z<8> Z<7> Z<6> Z<5> Z<4> Z<3> Z<2> Z<1> Z<0> VDD VSS +XBUF<15> A<15> Z<15> VDD VSS / RSC_IHPSG13_WLDRVX12 +XBUF<14> A<14> Z<14> VDD VSS / RSC_IHPSG13_WLDRVX12 +XBUF<13> A<13> Z<13> VDD VSS / RSC_IHPSG13_WLDRVX12 +XBUF<12> A<12> Z<12> VDD VSS / RSC_IHPSG13_WLDRVX12 +XBUF<11> A<11> Z<11> VDD VSS / RSC_IHPSG13_WLDRVX12 +XBUF<10> A<10> Z<10> VDD VSS / RSC_IHPSG13_WLDRVX12 +XBUF<9> A<9> Z<9> VDD VSS / RSC_IHPSG13_WLDRVX12 +XBUF<8> A<8> Z<8> VDD VSS / RSC_IHPSG13_WLDRVX12 +XBUF<7> A<7> Z<7> VDD VSS / RSC_IHPSG13_WLDRVX12 +XBUF<6> A<6> Z<6> VDD VSS / RSC_IHPSG13_WLDRVX12 +XBUF<5> A<5> Z<5> VDD VSS / RSC_IHPSG13_WLDRVX12 +XBUF<4> A<4> Z<4> VDD VSS / RSC_IHPSG13_WLDRVX12 +XBUF<3> A<3> Z<3> VDD VSS / RSC_IHPSG13_WLDRVX12 +XBUF<2> A<2> Z<2> VDD VSS / RSC_IHPSG13_WLDRVX12 +XBUF<1> A<1> Z<1> VDD VSS / RSC_IHPSG13_WLDRVX12 +XBUF<0> A<0> Z<0> VDD VSS / RSC_IHPSG13_WLDRVX12 +.ENDS + + + +.SUBCKT RM_IHPSG13_1024x32_c2_2P_COLDRV13X8 ADDR_COL_I<1> ADDR_COL_I<0> ADDR_COL_O<1> ++ ADDR_COL_O<0> ADDR_DEC_I<7> ADDR_DEC_I<6> ADDR_DEC_I<5> ADDR_DEC_I<4> ++ ADDR_DEC_I<3> ADDR_DEC_I<2> ADDR_DEC_I<1> ADDR_DEC_I<0> ADDR_DEC_O<7> ++ ADDR_DEC_O<6> ADDR_DEC_O<5> ADDR_DEC_O<4> ADDR_DEC_O<3> ADDR_DEC_O<2> ++ ADDR_DEC_O<1> ADDR_DEC_O<0> DCLK_I DCLK_O RCLK_I RCLK_O WCLK_I WCLK_O ++ VDD VSS +XI0<5> VDD VSS / RSC_IHPSG13_FILLCAP4 +XI0<4> VDD VSS / RSC_IHPSG13_FILLCAP4 +XI0<3> VDD VSS / RSC_IHPSG13_FILLCAP4 +XI0<2> VDD VSS / RSC_IHPSG13_FILLCAP4 +XI0<1> VDD VSS / RSC_IHPSG13_FILLCAP4 +XWCLK_DRV WCLK_I WCLK_O VDD VSS / RSC_IHPSG13_CBUFX8 +XRCLK_DRV RCLK_I RCLK_O VDD VSS / RSC_IHPSG13_CBUFX8 +XDCLK_DRV DCLK_I DCLK_O VDD VSS / RSC_IHPSG13_CBUFX8 +XADDR_COL_DRV<1> ADDR_COL_I<1> ADDR_COL_O<1> VDD VSS / ++ RSC_IHPSG13_CBUFX8 +XADDR_COL_DRV<0> ADDR_COL_I<0> ADDR_COL_O<0> VDD VSS / ++ RSC_IHPSG13_CBUFX8 +XADDR_DEC_DRV<7> ADDR_DEC_I<7> ADDR_DEC_O<7> VDD VSS / ++ RSC_IHPSG13_CBUFX8 +XADDR_DEC_DRV<6> ADDR_DEC_I<6> ADDR_DEC_O<6> VDD VSS / ++ RSC_IHPSG13_CBUFX8 +XADDR_DEC_DRV<5> ADDR_DEC_I<5> ADDR_DEC_O<5> VDD VSS / ++ RSC_IHPSG13_CBUFX8 +XADDR_DEC_DRV<4> ADDR_DEC_I<4> ADDR_DEC_O<4> VDD VSS / ++ RSC_IHPSG13_CBUFX8 +XADDR_DEC_DRV<3> ADDR_DEC_I<3> ADDR_DEC_O<3> VDD VSS / ++ RSC_IHPSG13_CBUFX8 +XADDR_DEC_DRV<2> ADDR_DEC_I<2> ADDR_DEC_O<2> VDD VSS / ++ RSC_IHPSG13_CBUFX8 +XADDR_DEC_DRV<1> ADDR_DEC_I<1> ADDR_DEC_O<1> VDD VSS / ++ RSC_IHPSG13_CBUFX8 +XADDR_DEC_DRV<0> ADDR_DEC_I<0> ADDR_DEC_O<0> VDD VSS / ++ RSC_IHPSG13_CBUFX8 +XI1<3> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI1<2> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI1<1> VDD VSS / RSC_IHPSG13_FILLCAP8 +.ENDS +.SUBCKT RSC_IHPSG13_WLDRVX8 A Z VDD VSS +MN1 Z net6 VSS VSS sg13_lv_nmos m=1 w=1.41u l=130.00n ng=2 nrd=0 nrs=0 +MN0 net6 A VSS VSS sg13_lv_nmos m=1 w=1.8u l=130.00n ng=2 nrd=0 nrs=0 +MP1 Z net6 VDD VDD sg13_lv_pmos m=1 w=6.48u l=130.00n ng=4 nrd=0 nrs=0 +MP0 net6 A VDD VDD sg13_lv_pmos m=1 w=900.0n l=130.00n ng=1 nrd=0 nrs=0 +.ENDS +.SUBCKT RM_IHPSG13_1024x32_c2_2P_WLDRV16X8 A<15> A<14> A<13> A<12> A<11> A<10> A<9> A<8> ++ A<7> A<6> A<5> A<4> A<3> A<2> A<1> A<0> Z<15> Z<14> Z<13> Z<12> Z<11> Z<10> ++ Z<9> Z<8> Z<7> Z<6> Z<5> Z<4> Z<3> Z<2> Z<1> Z<0> VDD VSS +XBUF<15> A<15> Z<15> VDD VSS / RSC_IHPSG13_WLDRVX8 +XBUF<14> A<14> Z<14> VDD VSS / RSC_IHPSG13_WLDRVX8 +XBUF<13> A<13> Z<13> VDD VSS / RSC_IHPSG13_WLDRVX8 +XBUF<12> A<12> Z<12> VDD VSS / RSC_IHPSG13_WLDRVX8 +XBUF<11> A<11> Z<11> VDD VSS / RSC_IHPSG13_WLDRVX8 +XBUF<10> A<10> Z<10> VDD VSS / RSC_IHPSG13_WLDRVX8 +XBUF<9> A<9> Z<9> VDD VSS / RSC_IHPSG13_WLDRVX8 +XBUF<8> A<8> Z<8> VDD VSS / RSC_IHPSG13_WLDRVX8 +XBUF<7> A<7> Z<7> VDD VSS / RSC_IHPSG13_WLDRVX8 +XBUF<6> A<6> Z<6> VDD VSS / RSC_IHPSG13_WLDRVX8 +XBUF<5> A<5> Z<5> VDD VSS / RSC_IHPSG13_WLDRVX8 +XBUF<4> A<4> Z<4> VDD VSS / RSC_IHPSG13_WLDRVX8 +XBUF<3> A<3> Z<3> VDD VSS / RSC_IHPSG13_WLDRVX8 +XBUF<2> A<2> Z<2> VDD VSS / RSC_IHPSG13_WLDRVX8 +XBUF<1> A<1> Z<1> VDD VSS / RSC_IHPSG13_WLDRVX8 +XBUF<0> A<0> Z<0> VDD VSS / RSC_IHPSG13_WLDRVX8 +.ENDS + + + +.SUBCKT RM_IHPSG13_1024x32_c2_2P_COLDEC2 ACLK_N ADDR<1> ADDR<0> ADDR_COL<1> ADDR_COL<0> ++ ADDR_DEC<7> ADDR_DEC<6> ADDR_DEC<5> ADDR_DEC<4> ADDR_DEC<3> ADDR_DEC<2> ++ ADDR_DEC<1> ADDR_DEC<0> BIST_ADDR<1> BIST_ADDR<0> BIST_EN_I VDD VSS +XI16<17> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI16<16> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI16<15> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI16<14> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI16<13> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI16<12> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI16<11> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI16<10> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI16<9> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI16<8> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI16<7> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI16<6> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI16<5> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI16<4> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI16<3> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI16<2> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI16<1> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI18<24> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI18<23> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI18<22> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI18<21> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI18<20> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI18<19> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI18<18> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI18<17> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI18<16> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI18<15> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI18<14> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI18<13> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI18<12> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI18<11> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI18<10> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI18<9> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI18<8> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI18<7> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI18<6> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI18<5> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI18<4> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI18<3> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI18<2> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI18<1> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI1<3> PADR<0> PADR<1> addr_n<3> VDD VSS / RSC_IHPSG13_NAND2X2 +XI1<2> NADR<0> PADR<1> addr_n<2> VDD VSS / RSC_IHPSG13_NAND2X2 +XI1<1> PADR<0> NADR<1> addr_n<1> VDD VSS / RSC_IHPSG13_NAND2X2 +XI1<0> NADR<0> NADR<1> addr_n<0> VDD VSS / RSC_IHPSG13_NAND2X2 +XI17<1> ADDR_COL<1> VDD VSS / RSC_IHPSG13_TIEL +XI17<0> ADDR_COL<0> VDD VSS / RSC_IHPSG13_TIEL +XI14<3> ADDR_DEC<7> VDD VSS / RSC_IHPSG13_TIEL +XI14<2> ADDR_DEC<6> VDD VSS / RSC_IHPSG13_TIEL +XI14<1> ADDR_DEC<5> VDD VSS / RSC_IHPSG13_TIEL +XI14<0> ADDR_DEC<4> VDD VSS / RSC_IHPSG13_TIEL +XI13<1> NADR<1> PADR<1> VDD VSS / RSC_IHPSG13_INVX2 +XI13<0> NADR<0> PADR<0> VDD VSS / RSC_IHPSG13_INVX2 +XI3<1> padr_int<1> NADR<1> VDD VSS / RSC_IHPSG13_INVX2 +XI3<0> padr_int<0> NADR<0> VDD VSS / RSC_IHPSG13_INVX2 +XI2<3> addr_n<3> ADDR_DEC<3> VDD VSS / RSC_IHPSG13_INVX2 +XI2<2> addr_n<2> ADDR_DEC<2> VDD VSS / RSC_IHPSG13_INVX2 +XI2<1> addr_n<1> ADDR_DEC<1> VDD VSS / RSC_IHPSG13_INVX2 +XI2<0> addr_n<0> ADDR_DEC<0> VDD VSS / RSC_IHPSG13_INVX2 +XDFF<1> BIST_EN_I BIST_ADDR<1> ACLK_N ADDR<1> padr_int<1> net12<0> VDD ++ VSS / RSC_IHPSG13_DFNQMX2IX1 +XDFF<0> BIST_EN_I BIST_ADDR<0> ACLK_N ADDR<0> padr_int<0> net12<1> VDD ++ VSS / RSC_IHPSG13_DFNQMX2IX1 +XI15<5> VDD VSS / RSC_IHPSG13_FILLCAP4 +XI15<4> VDD VSS / RSC_IHPSG13_FILLCAP4 +XI15<3> VDD VSS / RSC_IHPSG13_FILLCAP4 +XI15<2> VDD VSS / RSC_IHPSG13_FILLCAP4 +XI15<1> VDD VSS / RSC_IHPSG13_FILLCAP4 +XI19<4> VDD VSS / RSC_IHPSG13_FILLCAP4 +XI19<3> VDD VSS / RSC_IHPSG13_FILLCAP4 +XI19<2> VDD VSS / RSC_IHPSG13_FILLCAP4 +XI19<1> VDD VSS / RSC_IHPSG13_FILLCAP4 +.ENDS +.SUBCKT RM_IHPSG13_1024x32_c2_2P_COLCTRL2 A_ADDR_DEC<3> A_ADDR_DEC<2> A_ADDR_DEC<1> ++ A_ADDR_DEC<0> A_BIST_BM_I A_BIST_DW_I A_BIST_EN_I A_BLC<3> A_BLC<2> A_BLC<1> ++ A_BLC<0> A_BLT<3> A_BLT<2> A_BLT<1> A_BLT<0> A_BM_I A_DCLK_B_L A_DCLK_B_R ++ A_DCLK_L A_DCLK_R A_DR_O A_DW_I A_RCLK_B_L A_RCLK_B_R A_RCLK_L A_RCLK_R ++ A_TIEH_O A_WCLK_B_L A_WCLK_B_R A_WCLK_L A_WCLK_R B_ADDR_DEC<3> B_ADDR_DEC<2> ++ B_ADDR_DEC<1> B_ADDR_DEC<0> B_BIST_BM_I B_BIST_DW_I B_BIST_EN_I B_BLC<3> ++ B_BLC<2> B_BLC<1> B_BLC<0> B_BLT<3> B_BLT<2> B_BLT<1> B_BLT<0> B_BM_I ++ B_DCLK_B_L B_DCLK_B_R B_DCLK_L B_DCLK_R B_DR_O B_DW_I B_RCLK_B_L B_RCLK_B_R ++ B_RCLK_L B_RCLK_R B_TIEH_O B_WCLK_B_L B_WCLK_B_R B_WCLK_L B_WCLK_R VDD ++ VSS +XB_DREG B_BIST_EN_I B_BIST_DW_I B_DCLK_B_L B_DW_I B_DI_R net046 VDD ++ VSS / RSC_IHPSG13_DFNQMX2IX1 +XB_BREG B_BIST_EN_I B_BIST_BM_I B_DCLK_B_L B_BM_I B_BM_R net045 VDD ++ VSS / RSC_IHPSG13_DFNQMX2IX1 +XA_DREG A_BIST_EN_I A_BIST_DW_I A_DCLK_B_L A_DW_I A_DI_R net22 VDD VSS ++ / RSC_IHPSG13_DFNQMX2IX1 +XA_BREG A_BIST_EN_I A_BIST_BM_I A_DCLK_B_L A_BM_I A_BM_R net23 VDD VSS ++ / RSC_IHPSG13_DFNQMX2IX1 +XB_CAPS VDD VSS / RSC_IHPSG13_FILLCAP4 +XA_CAPS VDD VSS / RSC_IHPSG13_FILLCAP4 +XB_I75 B_DI_R B_DO_WRITE_P B_WR_ONE VDD VSS / RSC_IHPSG13_AND2X2 +XB_I80 B_RCLK_B_L B_WCLK_B_L net041 VDD VSS / RSC_IHPSG13_AND2X2 +XB_I76 B_DI_N B_DO_WRITE_P B_WR_ZERO VDD VSS / RSC_IHPSG13_AND2X2 +XA_I80 A_RCLK_B_L A_WCLK_B_L net21 VDD VSS / RSC_IHPSG13_AND2X2 +XA_I75 A_DI_R A_DO_WRITE_P A_WR_ONE VDD VSS / RSC_IHPSG13_AND2X2 +XA_I76 A_DI_N A_DO_WRITE_P A_WR_ZERO VDD VSS / RSC_IHPSG13_AND2X2 +XB_I44 B_WCLK_B_L B_BM_N B_DO_WRITE_P VDD VSS / RSC_IHPSG13_NOR2X2 +XA_I44 A_WCLK_B_L A_BM_N A_DO_WRITE_P VDD VSS / RSC_IHPSG13_NOR2X2 +XB_I81 net041 B_PRE_N VDD VSS / RSC_IHPSG13_CINVX4_WN +XA_I81 net21 A_PRE_N VDD VSS / RSC_IHPSG13_CINVX4_WN +XB_BM_TIEH B_TIEH_O VDD VSS / RSC_IHPSG13_TIEH +XA_BM_TIEH A_TIEH_O VDD VSS / RSC_IHPSG13_TIEH +XA_I89 A_DCLK_B_L A_DCLK_B_R / RSC_IHPSG13_MET3RES +XA_I88 A_DCLK_L A_DCLK_R / RSC_IHPSG13_MET3RES +XA_I87 A_WCLK_L A_WCLK_R / RSC_IHPSG13_MET3RES +XA_I91 A_RCLK_B_L A_RCLK_B_R / RSC_IHPSG13_MET3RES +XB_I87 B_WCLK_L B_WCLK_R / RSC_IHPSG13_MET3RES +XB_I88 B_DCLK_L B_DCLK_R / RSC_IHPSG13_MET3RES +XB_I89 B_DCLK_B_L B_DCLK_B_R / RSC_IHPSG13_MET3RES +XB_I90 B_WCLK_B_L B_WCLK_B_R / RSC_IHPSG13_MET3RES +XB_R2 B_RCLK_L B_RCLK_R / RSC_IHPSG13_MET3RES +XB_I91 B_RCLK_B_L B_RCLK_B_R / RSC_IHPSG13_MET3RES +XA_R2 A_RCLK_L A_RCLK_R / RSC_IHPSG13_MET3RES +XA_I90 A_WCLK_B_L A_WCLK_B_R / RSC_IHPSG13_MET3RES +XAB_BLMUX A_BLC<3> A_BLC<2> A_BLC<1> A_BLC<0> A_BLC_SEL A_BLT<3> A_BLT<2> ++ A_BLT<1> A_BLT<0> A_BLT_SEL A_PRE_N A_ADDR_DEC<3> A_ADDR_DEC<2> ++ A_ADDR_DEC<1> A_ADDR_DEC<0> A_WR_ONE A_WR_ZERO B_BLC<3> B_BLC<2> B_BLC<1> ++ B_BLC<0> B_BLC_SEL B_BLT<3> B_BLT<2> B_BLT<1> B_BLT<0> B_BLT_SEL B_PRE_N ++ B_ADDR_DEC<3> B_ADDR_DEC<2> B_ADDR_DEC<1> B_ADDR_DEC<0> B_WR_ONE B_WR_ZERO ++ VDD VSS / RM_IHPSG13_1024x32_c2_2P_BLDRV +XB_ISENSE B_SAE B_BLC_SEL B_BLT_SEL net039 net040 VDD VSS / ++ RSC_IHPSG13_DFPQD_MSAFFX2 +XA_ISENSE A_SAE A_BLC_SEL A_BLT_SEL net19 net20 VDD VSS / ++ RSC_IHPSG13_DFPQD_MSAFFX2 +XB_I78 B_RCLK_B_L B_SAE VDD VSS / RSC_IHPSG13_CBUFX2 +XA_I78 A_RCLK_B_L A_SAE VDD VSS / RSC_IHPSG13_CBUFX2 +XB_I83 B_BM_R B_BM_N VDD VSS / RSC_IHPSG13_INVX2 +XB_I49 B_DI_R B_DI_N VDD VSS / RSC_IHPSG13_INVX2 +XA_I83 A_BM_R A_BM_N VDD VSS / RSC_IHPSG13_INVX2 +XA_I49 A_DI_R A_DI_N VDD VSS / RSC_IHPSG13_INVX2 +XB_I51 net039 B_DR_O VDD VSS / RSC_IHPSG13_INVX4 +XA_I51 net19 A_DR_O VDD VSS / RSC_IHPSG13_INVX4 +XA_I69 A_DCLK_L A_DCLK_B_L VDD VSS / RSC_IHPSG13_CINVX2 +XA_I50 A_WCLK_L A_WCLK_B_L VDD VSS / RSC_IHPSG13_CINVX2 +XA_EBUF A_RCLK_L A_RCLK_B_L VDD VSS / RSC_IHPSG13_CINVX2 +XB_EBUF B_RCLK_L B_RCLK_B_L VDD VSS / RSC_IHPSG13_CINVX2 +XB_I50 B_WCLK_L B_WCLK_B_L VDD VSS / RSC_IHPSG13_CINVX2 +XB_I69 B_DCLK_L B_DCLK_B_L VDD VSS / RSC_IHPSG13_CINVX2 +.ENDS +.SUBCKT RM_IHPSG13_1024x32_c2_2P_COLDRV13_FILL4C2 VDD VSS +XI0<2> VDD VSS / RSC_IHPSG13_FILLCAP4 +XI0<1> VDD VSS / RSC_IHPSG13_FILLCAP4 +.ENDS + + +.SUBCKT RM_IHPSG13_1024x32_c2_2P_ROWDEC7 ADDR_N_I<6> ADDR_N_I<5> ADDR_N_I<4> ADDR_N_I<3> ++ ADDR_N_I<2> ADDR_N_I<1> ADDR_N_I<0> CS_I ECLK_I WL_O<127> WL_O<126> ++ WL_O<125> WL_O<124> WL_O<123> WL_O<122> WL_O<121> WL_O<120> WL_O<119> ++ WL_O<118> WL_O<117> WL_O<116> WL_O<115> WL_O<114> WL_O<113> WL_O<112> ++ WL_O<111> WL_O<110> WL_O<109> WL_O<108> WL_O<107> WL_O<106> WL_O<105> ++ WL_O<104> WL_O<103> WL_O<102> WL_O<101> WL_O<100> WL_O<99> WL_O<98> WL_O<97> ++ WL_O<96> WL_O<95> WL_O<94> WL_O<93> WL_O<92> WL_O<91> WL_O<90> WL_O<89> ++ WL_O<88> WL_O<87> WL_O<86> WL_O<85> WL_O<84> WL_O<83> WL_O<82> WL_O<81> ++ WL_O<80> WL_O<79> WL_O<78> WL_O<77> WL_O<76> WL_O<75> WL_O<74> WL_O<73> ++ WL_O<72> WL_O<71> WL_O<70> WL_O<69> WL_O<68> WL_O<67> WL_O<66> WL_O<65> ++ WL_O<64> WL_O<63> WL_O<62> WL_O<61> WL_O<60> WL_O<59> WL_O<58> WL_O<57> ++ WL_O<56> WL_O<55> WL_O<54> WL_O<53> WL_O<52> WL_O<51> WL_O<50> WL_O<49> ++ WL_O<48> WL_O<47> WL_O<46> WL_O<45> WL_O<44> WL_O<43> WL_O<42> WL_O<41> ++ WL_O<40> WL_O<39> WL_O<38> WL_O<37> WL_O<36> WL_O<35> WL_O<34> WL_O<33> ++ WL_O<32> WL_O<31> WL_O<30> WL_O<29> WL_O<28> WL_O<27> WL_O<26> WL_O<25> ++ WL_O<24> WL_O<23> WL_O<22> WL_O<21> WL_O<20> WL_O<19> WL_O<18> WL_O<17> ++ WL_O<16> WL_O<15> WL_O<14> WL_O<13> WL_O<12> WL_O<11> WL_O<10> WL_O<9> ++ WL_O<8> WL_O<7> WL_O<6> WL_O<5> WL_O<4> WL_O<3> WL_O<2> WL_O<1> WL_O<0> ++ VDD VSS +XSEL<7> ADDR_N_I<3> ADDR_N_I<2> ADDR_N_I<1> ADDR_N_I<0> CS00<7> ECLK_H<7> ++ ECLK_H<8> ECLK_B<7> ECLK_B<8> WL_O<127> WL_O<126> WL_O<125> WL_O<124> ++ WL_O<123> WL_O<122> WL_O<121> WL_O<120> WL_O<119> WL_O<118> WL_O<117> ++ WL_O<116> WL_O<115> WL_O<114> WL_O<113> WL_O<112> VDD VSS / ++ RM_IHPSG13_1024x32_c2_2P_DEC04 +XSEL<6> ADDR_N_I<3> ADDR_N_I<2> ADDR_N_I<1> ADDR_N_I<0> CS00<6> ECLK_H<6> ++ ECLK_H<7> ECLK_B<6> ECLK_B<7> WL_O<111> WL_O<110> WL_O<109> WL_O<108> ++ WL_O<107> WL_O<106> WL_O<105> WL_O<104> WL_O<103> WL_O<102> WL_O<101> ++ WL_O<100> WL_O<99> WL_O<98> WL_O<97> WL_O<96> VDD VSS / ++ RM_IHPSG13_1024x32_c2_2P_DEC04 +XSEL<5> ADDR_N_I<3> ADDR_N_I<2> ADDR_N_I<1> ADDR_N_I<0> CS00<5> ECLK_H<5> ++ ECLK_H<6> ECLK_B<5> ECLK_B<6> WL_O<95> WL_O<94> WL_O<93> WL_O<92> WL_O<91> ++ WL_O<90> WL_O<89> WL_O<88> WL_O<87> WL_O<86> WL_O<85> WL_O<84> WL_O<83> ++ WL_O<82> WL_O<81> WL_O<80> VDD VSS / RM_IHPSG13_1024x32_c2_2P_DEC04 +XSEL<4> ADDR_N_I<3> ADDR_N_I<2> ADDR_N_I<1> ADDR_N_I<0> CS00<4> ECLK_H<4> ++ ECLK_H<5> ECLK_B<4> ECLK_B<5> WL_O<79> WL_O<78> WL_O<77> WL_O<76> WL_O<75> ++ WL_O<74> WL_O<73> WL_O<72> WL_O<71> WL_O<70> WL_O<69> WL_O<68> WL_O<67> ++ WL_O<66> WL_O<65> WL_O<64> VDD VSS / RM_IHPSG13_1024x32_c2_2P_DEC04 +XSEL<3> ADDR_N_I<3> ADDR_N_I<2> ADDR_N_I<1> ADDR_N_I<0> CS00<3> ECLK_H<3> ++ ECLK_H<4> ECLK_B<3> ECLK_B<4> WL_O<63> WL_O<62> WL_O<61> WL_O<60> WL_O<59> ++ WL_O<58> WL_O<57> WL_O<56> WL_O<55> WL_O<54> WL_O<53> WL_O<52> WL_O<51> ++ WL_O<50> WL_O<49> WL_O<48> VDD VSS / RM_IHPSG13_1024x32_c2_2P_DEC04 +XSEL<2> ADDR_N_I<3> ADDR_N_I<2> ADDR_N_I<1> ADDR_N_I<0> CS00<2> ECLK_H<2> ++ ECLK_H<3> ECLK_B<2> ECLK_B<3> WL_O<47> WL_O<46> WL_O<45> WL_O<44> WL_O<43> ++ WL_O<42> WL_O<41> WL_O<40> WL_O<39> WL_O<38> WL_O<37> WL_O<36> WL_O<35> ++ WL_O<34> WL_O<33> WL_O<32> VDD VSS / RM_IHPSG13_1024x32_c2_2P_DEC04 +XSEL<1> ADDR_N_I<3> ADDR_N_I<2> ADDR_N_I<1> ADDR_N_I<0> CS00<1> ECLK_H<1> ++ ECLK_H<2> ECLK_B<1> ECLK_B<2> WL_O<31> WL_O<30> WL_O<29> WL_O<28> WL_O<27> ++ WL_O<26> WL_O<25> WL_O<24> WL_O<23> WL_O<22> WL_O<21> WL_O<20> WL_O<19> ++ WL_O<18> WL_O<17> WL_O<16> VDD VSS / RM_IHPSG13_1024x32_c2_2P_DEC04 +XSEL<0> ADDR_N_I<3> ADDR_N_I<2> ADDR_N_I<1> ADDR_N_I<0> CS00<0> ECLK_I ++ ECLK_H<1> ECLK_B<0> ECLK_B<1> WL_O<15> WL_O<14> WL_O<13> WL_O<12> WL_O<11> ++ WL_O<10> WL_O<9> WL_O<8> WL_O<7> WL_O<6> WL_O<5> WL_O<4> WL_O<3> WL_O<2> ++ WL_O<1> WL_O<0> VDD VSS / RM_IHPSG13_1024x32_c2_2P_DEC04 +XDEC11<1> ADDR_N_I<5> ADDR_N_I<4> CS04<1> CS00<7> VDD VSS / ++ RM_IHPSG13_1024x32_c2_2P_DEC03 +XDEC11<0> ADDR_N_I<5> ADDR_N_I<4> CS04<0> CS00<3> VDD VSS / ++ RM_IHPSG13_1024x32_c2_2P_DEC03 +XDEC01<2> ADDR_N_I<7> ADDR_N_I<6> CS_I CS04<1> VDD VSS / ++ RM_IHPSG13_1024x32_c2_2P_DEC01 +XDEC01<1> ADDR_N_I<5> ADDR_N_I<4> CS04<1> CS00<5> VDD VSS / ++ RM_IHPSG13_1024x32_c2_2P_DEC01 +XDEC01<0> ADDR_N_I<5> ADDR_N_I<4> CS04<0> CS00<1> VDD VSS / ++ RM_IHPSG13_1024x32_c2_2P_DEC01 +XL2<66> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<65> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<64> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<63> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<62> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<61> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<60> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<59> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<58> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<57> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<56> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<55> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<54> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<53> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<52> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<51> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<50> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<49> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<48> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<47> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<46> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<45> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<44> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<43> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<42> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<41> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<40> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<39> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<38> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<37> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<36> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<35> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<34> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<33> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<32> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<31> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<30> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<29> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<28> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<27> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<26> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<25> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<24> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<23> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<22> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<21> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<20> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<19> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<18> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<17> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<16> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<15> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<14> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<13> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<12> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<11> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<10> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<9> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<8> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<7> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<6> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<5> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<4> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<3> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<2> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<1> VDD VSS / RSC_IHPSG13_FILLCAP8 +XDEC10<1> ADDR_N_I<5> ADDR_N_I<4> CS04<1> CS00<6> VDD VSS / ++ RM_IHPSG13_1024x32_c2_2P_DEC02 +XDEC10<0> ADDR_N_I<5> ADDR_N_I<4> CS04<0> CS00<2> VDD VSS / ++ RM_IHPSG13_1024x32_c2_2P_DEC02 +XDEC00<2> ADDR_N_I<7> ADDR_N_I<6> CS_I CS04<0> VDD VSS / ++ RM_IHPSG13_1024x32_c2_2P_DEC00 +XDEC00<1> ADDR_N_I<5> ADDR_N_I<4> CS04<1> CS00<4> VDD VSS / ++ RM_IHPSG13_1024x32_c2_2P_DEC00 +XDEC00<0> ADDR_N_I<5> ADDR_N_I<4> CS04<0> CS00<0> VDD VSS / ++ RM_IHPSG13_1024x32_c2_2P_DEC00 +XI0 ADDR_N_I<7> VDD VSS / RSC_IHPSG13_TIEL +.ENDS +.SUBCKT RM_IHPSG13_1024x32_c2_2P_ROWREG7 ACLK_N_I ADDR_I<6> ADDR_I<5> ADDR_I<4> ADDR_I<3> ++ ADDR_I<2> ADDR_I<1> ADDR_I<0> ADDR_N_O<6> ADDR_N_O<5> ADDR_N_O<4> ++ ADDR_N_O<3> ADDR_N_O<2> ADDR_N_O<1> ADDR_N_O<0> BIST_ADDR_I<6> ++ BIST_ADDR_I<5> BIST_ADDR_I<4> BIST_ADDR_I<3> BIST_ADDR_I<2> BIST_ADDR_I<1> ++ BIST_ADDR_I<0> BIST_EN_I VDD VSS +XINV<6> q_int<6> qn_int<6> VDD VSS / RSC_IHPSG13_CINVX2 +XINV<5> q_int<5> qn_int<5> VDD VSS / RSC_IHPSG13_CINVX2 +XINV<4> q_int<4> qn_int<4> VDD VSS / RSC_IHPSG13_CINVX2 +XINV<3> q_int<3> qn_int<3> VDD VSS / RSC_IHPSG13_CINVX2 +XINV<2> q_int<2> qn_int<2> VDD VSS / RSC_IHPSG13_CINVX2 +XINV<1> q_int<1> qn_int<1> VDD VSS / RSC_IHPSG13_CINVX2 +XINV<0> q_int<0> qn_int<0> VDD VSS / RSC_IHPSG13_CINVX2 +XDRV<6> qn_int<6> ADDR_N_O<6> VDD VSS / RSC_IHPSG13_CINVX8 +XDRV<5> qn_int<5> ADDR_N_O<5> VDD VSS / RSC_IHPSG13_CINVX8 +XDRV<4> qn_int<4> ADDR_N_O<4> VDD VSS / RSC_IHPSG13_CINVX8 +XDRV<3> qn_int<3> ADDR_N_O<3> VDD VSS / RSC_IHPSG13_CINVX8 +XDRV<2> qn_int<2> ADDR_N_O<2> VDD VSS / RSC_IHPSG13_CINVX8 +XDRV<1> qn_int<1> ADDR_N_O<1> VDD VSS / RSC_IHPSG13_CINVX8 +XDRV<0> qn_int<0> ADDR_N_O<0> VDD VSS / RSC_IHPSG13_CINVX8 +XDFF<6> BIST_EN_I BIST_ADDR_I<6> ACLK_N_I ADDR_I<6> q_int<6> net2<0> VDD ++ VSS / RSC_IHPSG13_DFNQMX2IX1 +XDFF<5> BIST_EN_I BIST_ADDR_I<5> ACLK_N_I ADDR_I<5> q_int<5> net2<1> VDD ++ VSS / RSC_IHPSG13_DFNQMX2IX1 +XDFF<4> BIST_EN_I BIST_ADDR_I<4> ACLK_N_I ADDR_I<4> q_int<4> net2<2> VDD ++ VSS / RSC_IHPSG13_DFNQMX2IX1 +XDFF<3> BIST_EN_I BIST_ADDR_I<3> ACLK_N_I ADDR_I<3> q_int<3> net2<3> VDD ++ VSS / RSC_IHPSG13_DFNQMX2IX1 +XDFF<2> BIST_EN_I BIST_ADDR_I<2> ACLK_N_I ADDR_I<2> q_int<2> net2<4> VDD ++ VSS / RSC_IHPSG13_DFNQMX2IX1 +XDFF<1> BIST_EN_I BIST_ADDR_I<1> ACLK_N_I ADDR_I<1> q_int<1> net2<5> VDD ++ VSS / RSC_IHPSG13_DFNQMX2IX1 +XDFF<0> BIST_EN_I BIST_ADDR_I<0> ACLK_N_I ADDR_I<0> q_int<0> net2<6> VDD ++ VSS / RSC_IHPSG13_DFNQMX2IX1 +XI11<7> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI11<6> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI11<5> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI11<4> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI11<3> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI11<2> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI11<1> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI11<0> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI12<1> VDD VSS / RSC_IHPSG13_FILLCAP4 +XI12<0> VDD VSS / RSC_IHPSG13_FILLCAP4 +.ENDS + +.SUBCKT RM_IHPSG13_1024x32_c2_2P_ROWDEC4 ADDR_N_I<3> ADDR_N_I<2> ADDR_N_I<1> ADDR_N_I<0> ++ CS_I ECLK_I WL_O<15> WL_O<14> WL_O<13> WL_O<12> WL_O<11> WL_O<10> WL_O<9> ++ WL_O<8> WL_O<7> WL_O<6> WL_O<5> WL_O<4> WL_O<3> WL_O<2> WL_O<1> WL_O<0> ++ VDD VSS +XL2<12> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<11> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<10> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<9> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<8> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<7> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<6> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<5> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<4> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<3> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<2> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<1> VDD VSS / RSC_IHPSG13_FILLCAP8 +XSEL ADDR_N_I<3> ADDR_N_I<2> ADDR_N_I<1> ADDR_N_I<0> CS_I ECLK_I ECLK_H<1> ++ ECLK_B<0> ECLK_B<1> WL_O<15> WL_O<14> WL_O<13> WL_O<12> WL_O<11> WL_O<10> ++ WL_O<9> WL_O<8> WL_O<7> WL_O<6> WL_O<5> WL_O<4> WL_O<3> WL_O<2> WL_O<1> ++ WL_O<0> VDD VSS / RM_IHPSG13_1024x32_c2_2P_DEC04 +.ENDS +.SUBCKT RM_IHPSG13_1024x32_c2_2P_ROWREG4 ACLK_N_I ADDR_I<3> ADDR_I<2> ADDR_I<1> ADDR_I<0> ++ ADDR_N_O<3> ADDR_N_O<2> ADDR_N_O<1> ADDR_N_O<0> BIST_ADDR_I<3> ++ BIST_ADDR_I<2> BIST_ADDR_I<1> BIST_ADDR_I<0> BIST_EN_I VDD VSS +XINV<3> q_int<3> qn_int<3> VDD VSS / RSC_IHPSG13_CINVX2 +XINV<2> q_int<2> qn_int<2> VDD VSS / RSC_IHPSG13_CINVX2 +XINV<1> q_int<1> qn_int<1> VDD VSS / RSC_IHPSG13_CINVX2 +XINV<0> q_int<0> qn_int<0> VDD VSS / RSC_IHPSG13_CINVX2 +XDRV<3> qn_int<3> ADDR_N_O<3> VDD VSS / RSC_IHPSG13_CINVX8 +XDRV<2> qn_int<2> ADDR_N_O<2> VDD VSS / RSC_IHPSG13_CINVX8 +XDRV<1> qn_int<1> ADDR_N_O<1> VDD VSS / RSC_IHPSG13_CINVX8 +XDRV<0> qn_int<0> ADDR_N_O<0> VDD VSS / RSC_IHPSG13_CINVX8 +XDFF<3> BIST_EN_I BIST_ADDR_I<3> ACLK_N_I ADDR_I<3> q_int<3> net7<0> VDD ++ VSS / RSC_IHPSG13_DFNQMX2IX1 +XDFF<2> BIST_EN_I BIST_ADDR_I<2> ACLK_N_I ADDR_I<2> q_int<2> net7<1> VDD ++ VSS / RSC_IHPSG13_DFNQMX2IX1 +XDFF<1> BIST_EN_I BIST_ADDR_I<1> ACLK_N_I ADDR_I<1> q_int<1> net7<2> VDD ++ VSS / RSC_IHPSG13_DFNQMX2IX1 +XDFF<0> BIST_EN_I BIST_ADDR_I<0> ACLK_N_I ADDR_I<0> q_int<0> net7<3> VDD ++ VSS / RSC_IHPSG13_DFNQMX2IX1 +XI11<20> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI11<19> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI11<18> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI11<17> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI11<16> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI11<15> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI11<14> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI11<13> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI11<12> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI11<11> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI11<10> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI11<9> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI11<8> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI11<7> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI11<6> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI11<5> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI11<4> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI11<3> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI11<2> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI11<1> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI12<4> VDD VSS / RSC_IHPSG13_FILLCAP4 +XI12<3> VDD VSS / RSC_IHPSG13_FILLCAP4 +XI12<2> VDD VSS / RSC_IHPSG13_FILLCAP4 +XI12<1> VDD VSS / RSC_IHPSG13_FILLCAP4 +XI12<0> VDD VSS / RSC_IHPSG13_FILLCAP4 +.ENDS + + +.SUBCKT RM_IHPSG13_1024x32_c2_1P_BITKIT_TAP BLC BLT NW PW VDD VSS +.ENDS +.SUBCKT RM_IHPSG13_1024x32_c2_1P_BITKIT_16x2_TAP A_BLC<1> A_BLC<0> A_BLT<1> A_BLT<0> ++ VDD_CORE VSS +XITAP<1> A_BLC<1> A_BLT<1> VDD_CORE VSS VDD_CORE VSS ++ / RM_IHPSG13_1024x32_c2_1P_BITKIT_TAP +XITAP<0> A_BLC<0> A_BLT<0> VDD_CORE VSS VDD_CORE VSS ++ / RM_IHPSG13_1024x32_c2_1P_BITKIT_TAP +XIEDGEBP_COL1<1> BLC<1> BLT<1> VDD_CORE VSS VDD_CORE ++ VSS / RM_IHPSG13_1024x32_c2_1P_BITKIT_EDGE_TB +XIEDGEBP_COL1<0> BLC<1> BLT<1> VDD_CORE VSS VDD_CORE ++ VSS / RM_IHPSG13_1024x32_c2_1P_BITKIT_EDGE_TB +XIEDGEBP_COL2<1> BLC<0> BLT<0> VDD_CORE VSS VDD_CORE ++ VSS / RM_IHPSG13_1024x32_c2_1P_BITKIT_EDGE_TB +XIEDGEBP_COL2<0> BLC<0> BLT<0> VDD_CORE VSS VDD_CORE ++ VSS / RM_IHPSG13_1024x32_c2_1P_BITKIT_EDGE_TB +.ENDS +.SUBCKT RM_IHPSG13_1024x32_c2_1P_BITKIT_16x2_TAP_LR VDD_CORE VSS +XCORNER<1> VDD_CORE VSS VDD_CORE VSS / ++ RM_IHPSG13_1024x32_c2_1P_BITKIT_CORNER +XCORNER<0> VDD_CORE VSS VDD_CORE VSS / ++ RM_IHPSG13_1024x32_c2_1P_BITKIT_CORNER +XTAP_BORDER VDD_CORE VSS VDD_CORE VSS / ++ RM_IHPSG13_1024x32_c2_1P_BITKIT_TAP_LR +.ENDS +.SUBCKT RM_IHPSG13_1024x32_c2_1P_DEC03 ADDR<1> ADDR<0> CS CS_OUT VDD VSS +XDECINV net1 CS_OUT VDD VSS / RSC_IHPSG13_INVX4 +XI0 VDD VSS / RSC_IHPSG13_FILLCAP4 +XDEC ADDR<1> ADDR<0> CS net1 VDD VSS / RSC_IHPSG13_NAND3X2 +.ENDS +.SUBCKT RM_IHPSG13_1024x32_c2_1P_DEC02 ADDR<1> ADDR<0> CS CS_OUT VDD VSS +XDECINV net1 CS_OUT VDD VSS / RSC_IHPSG13_INVX4 +XDEC ADDR<1> NADDR<0> CS net1 VDD VSS / RSC_IHPSG13_NAND3X2 +XI2 VDD VSS / RSC_IHPSG13_FILLCAP4 +XADDRINV ADDR<0> NADDR<0> VDD VSS / RSC_IHPSG13_INVX2 +.ENDS +.SUBCKT RM_IHPSG13_1024x32_c2_1P_ROWDEC8 ADDR_N_I<7> ADDR_N_I<6> ADDR_N_I<5> ADDR_N_I<4> ++ ADDR_N_I<3> ADDR_N_I<2> ADDR_N_I<1> ADDR_N_I<0> CS_I ECLK_I WL_O<255> ++ WL_O<254> WL_O<253> WL_O<252> WL_O<251> WL_O<250> WL_O<249> WL_O<248> ++ WL_O<247> WL_O<246> WL_O<245> WL_O<244> WL_O<243> WL_O<242> WL_O<241> ++ WL_O<240> WL_O<239> WL_O<238> WL_O<237> WL_O<236> WL_O<235> WL_O<234> ++ WL_O<233> WL_O<232> WL_O<231> WL_O<230> WL_O<229> WL_O<228> WL_O<227> ++ WL_O<226> WL_O<225> WL_O<224> WL_O<223> WL_O<222> WL_O<221> WL_O<220> ++ WL_O<219> WL_O<218> WL_O<217> WL_O<216> WL_O<215> WL_O<214> WL_O<213> ++ WL_O<212> WL_O<211> WL_O<210> WL_O<209> WL_O<208> WL_O<207> WL_O<206> ++ WL_O<205> WL_O<204> WL_O<203> WL_O<202> WL_O<201> WL_O<200> WL_O<199> ++ WL_O<198> WL_O<197> WL_O<196> WL_O<195> WL_O<194> WL_O<193> WL_O<192> ++ WL_O<191> WL_O<190> WL_O<189> WL_O<188> WL_O<187> WL_O<186> WL_O<185> ++ WL_O<184> WL_O<183> WL_O<182> WL_O<181> WL_O<180> WL_O<179> WL_O<178> ++ WL_O<177> WL_O<176> WL_O<175> WL_O<174> WL_O<173> WL_O<172> WL_O<171> ++ WL_O<170> WL_O<169> WL_O<168> WL_O<167> WL_O<166> WL_O<165> WL_O<164> ++ WL_O<163> WL_O<162> WL_O<161> WL_O<160> WL_O<159> WL_O<158> WL_O<157> ++ WL_O<156> WL_O<155> WL_O<154> WL_O<153> WL_O<152> WL_O<151> WL_O<150> ++ WL_O<149> WL_O<148> WL_O<147> WL_O<146> WL_O<145> WL_O<144> WL_O<143> ++ WL_O<142> WL_O<141> WL_O<140> WL_O<139> WL_O<138> WL_O<137> WL_O<136> ++ WL_O<135> WL_O<134> WL_O<133> WL_O<132> WL_O<131> WL_O<130> WL_O<129> ++ WL_O<128> WL_O<127> WL_O<126> WL_O<125> WL_O<124> WL_O<123> WL_O<122> ++ WL_O<121> WL_O<120> WL_O<119> WL_O<118> WL_O<117> WL_O<116> WL_O<115> ++ WL_O<114> WL_O<113> WL_O<112> WL_O<111> WL_O<110> WL_O<109> WL_O<108> ++ WL_O<107> WL_O<106> WL_O<105> WL_O<104> WL_O<103> WL_O<102> WL_O<101> ++ WL_O<100> WL_O<99> WL_O<98> WL_O<97> WL_O<96> WL_O<95> WL_O<94> WL_O<93> ++ WL_O<92> WL_O<91> WL_O<90> WL_O<89> WL_O<88> WL_O<87> WL_O<86> WL_O<85> ++ WL_O<84> WL_O<83> WL_O<82> WL_O<81> WL_O<80> WL_O<79> WL_O<78> WL_O<77> ++ WL_O<76> WL_O<75> WL_O<74> WL_O<73> WL_O<72> WL_O<71> WL_O<70> WL_O<69> ++ WL_O<68> WL_O<67> WL_O<66> WL_O<65> WL_O<64> WL_O<63> WL_O<62> WL_O<61> ++ WL_O<60> WL_O<59> WL_O<58> WL_O<57> WL_O<56> WL_O<55> WL_O<54> WL_O<53> ++ WL_O<52> WL_O<51> WL_O<50> WL_O<49> WL_O<48> WL_O<47> WL_O<46> WL_O<45> ++ WL_O<44> WL_O<43> WL_O<42> WL_O<41> WL_O<40> WL_O<39> WL_O<38> WL_O<37> ++ WL_O<36> WL_O<35> WL_O<34> WL_O<33> WL_O<32> WL_O<31> WL_O<30> WL_O<29> ++ WL_O<28> WL_O<27> WL_O<26> WL_O<25> WL_O<24> WL_O<23> WL_O<22> WL_O<21> ++ WL_O<20> WL_O<19> WL_O<18> WL_O<17> WL_O<16> WL_O<15> WL_O<14> WL_O<13> ++ WL_O<12> WL_O<11> WL_O<10> WL_O<9> WL_O<8> WL_O<7> WL_O<6> WL_O<5> WL_O<4> ++ WL_O<3> WL_O<2> WL_O<1> WL_O<0> VDD VSS +XDEC11<4> ADDR_N_I<7> ADDR_N_I<6> CS_I CS04<3> VDD VSS / ++ RM_IHPSG13_1024x32_c2_1P_DEC03 +XDEC11<3> ADDR_N_I<5> ADDR_N_I<4> CS04<3> CS00<15> VDD VSS / ++ RM_IHPSG13_1024x32_c2_1P_DEC03 +XDEC11<2> ADDR_N_I<5> ADDR_N_I<4> CS04<2> CS00<11> VDD VSS / ++ RM_IHPSG13_1024x32_c2_1P_DEC03 +XDEC11<1> ADDR_N_I<5> ADDR_N_I<4> CS04<1> CS00<7> VDD VSS / ++ RM_IHPSG13_1024x32_c2_1P_DEC03 +XDEC11<0> ADDR_N_I<5> ADDR_N_I<4> CS04<0> CS00<3> VDD VSS / ++ RM_IHPSG13_1024x32_c2_1P_DEC03 +XL2<88> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<87> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<86> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<85> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<84> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<83> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<82> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<81> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<80> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<79> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<78> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<77> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<76> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<75> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<74> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<73> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<72> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<71> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<70> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<69> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<68> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<67> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<66> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<65> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<64> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<63> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<62> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<61> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<60> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<59> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<58> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<57> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<56> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<55> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<54> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<53> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<52> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<51> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<50> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<49> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<48> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<47> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<46> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<45> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<44> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<43> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<42> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<41> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<40> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<39> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<38> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<37> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<36> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<35> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<34> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<33> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<32> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<31> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<30> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<29> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<28> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<27> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<26> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<25> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<24> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<23> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<22> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<21> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<20> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<19> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<18> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<17> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<16> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<15> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<14> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<13> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<12> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<11> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<10> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<9> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<8> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<7> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<6> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<5> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<4> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<3> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<2> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<1> VDD VSS / RSC_IHPSG13_FILLCAP8 +XDEC10<4> ADDR_N_I<7> ADDR_N_I<6> CS_I CS04<2> VDD VSS / ++ RM_IHPSG13_1024x32_c2_1P_DEC02 +XDEC10<3> ADDR_N_I<5> ADDR_N_I<4> CS04<3> CS00<14> VDD VSS / ++ RM_IHPSG13_1024x32_c2_1P_DEC02 +XDEC10<2> ADDR_N_I<5> ADDR_N_I<4> CS04<2> CS00<10> VDD VSS / ++ RM_IHPSG13_1024x32_c2_1P_DEC02 +XDEC10<1> ADDR_N_I<5> ADDR_N_I<4> CS04<1> CS00<6> VDD VSS / ++ RM_IHPSG13_1024x32_c2_1P_DEC02 +XDEC10<0> ADDR_N_I<5> ADDR_N_I<4> CS04<0> CS00<2> VDD VSS / ++ RM_IHPSG13_1024x32_c2_1P_DEC02 +XDEC00<4> ADDR_N_I<7> ADDR_N_I<6> CS_I CS04<0> VDD VSS / ++ RM_IHPSG13_1024x32_c2_1P_DEC00 +XDEC00<3> ADDR_N_I<5> ADDR_N_I<4> CS04<3> CS00<12> VDD VSS / ++ RM_IHPSG13_1024x32_c2_1P_DEC00 +XDEC00<2> ADDR_N_I<5> ADDR_N_I<4> CS04<2> CS00<8> VDD VSS / ++ RM_IHPSG13_1024x32_c2_1P_DEC00 +XDEC00<1> ADDR_N_I<5> ADDR_N_I<4> CS04<1> CS00<4> VDD VSS / ++ RM_IHPSG13_1024x32_c2_1P_DEC00 +XDEC00<0> ADDR_N_I<5> ADDR_N_I<4> CS04<0> CS00<0> VDD VSS / ++ RM_IHPSG13_1024x32_c2_1P_DEC00 +XSEL<15> ADDR_N_I<3> ADDR_N_I<2> ADDR_N_I<1> ADDR_N_I<0> CS00<15> ECLK_H<15> ++ ECLK_H<16> ECLK_B<15> ECLK_B<16> WL_O<255> WL_O<254> WL_O<253> WL_O<252> ++ WL_O<251> WL_O<250> WL_O<249> WL_O<248> WL_O<247> WL_O<246> WL_O<245> ++ WL_O<244> WL_O<243> WL_O<242> WL_O<241> WL_O<240> VDD VSS / ++ RM_IHPSG13_1024x32_c2_1P_DEC04 +XSEL<14> ADDR_N_I<3> ADDR_N_I<2> ADDR_N_I<1> ADDR_N_I<0> CS00<14> ECLK_H<14> ++ ECLK_H<15> ECLK_B<14> ECLK_B<15> WL_O<239> WL_O<238> WL_O<237> WL_O<236> ++ WL_O<235> WL_O<234> WL_O<233> WL_O<232> WL_O<231> WL_O<230> WL_O<229> ++ WL_O<228> WL_O<227> WL_O<226> WL_O<225> WL_O<224> VDD VSS / ++ RM_IHPSG13_1024x32_c2_1P_DEC04 +XSEL<13> ADDR_N_I<3> ADDR_N_I<2> ADDR_N_I<1> ADDR_N_I<0> CS00<13> ECLK_H<13> ++ ECLK_H<14> ECLK_B<13> ECLK_B<14> WL_O<223> WL_O<222> WL_O<221> WL_O<220> ++ WL_O<219> WL_O<218> WL_O<217> WL_O<216> WL_O<215> WL_O<214> WL_O<213> ++ WL_O<212> WL_O<211> WL_O<210> WL_O<209> WL_O<208> VDD VSS / ++ RM_IHPSG13_1024x32_c2_1P_DEC04 +XSEL<12> ADDR_N_I<3> ADDR_N_I<2> ADDR_N_I<1> ADDR_N_I<0> CS00<12> ECLK_H<12> ++ ECLK_H<13> ECLK_B<12> ECLK_B<13> WL_O<207> WL_O<206> WL_O<205> WL_O<204> ++ WL_O<203> WL_O<202> WL_O<201> WL_O<200> WL_O<199> WL_O<198> WL_O<197> ++ WL_O<196> WL_O<195> WL_O<194> WL_O<193> WL_O<192> VDD VSS / ++ RM_IHPSG13_1024x32_c2_1P_DEC04 +XSEL<11> ADDR_N_I<3> ADDR_N_I<2> ADDR_N_I<1> ADDR_N_I<0> CS00<11> ECLK_H<11> ++ ECLK_H<12> ECLK_B<11> ECLK_B<12> WL_O<191> WL_O<190> WL_O<189> WL_O<188> ++ WL_O<187> WL_O<186> WL_O<185> WL_O<184> WL_O<183> WL_O<182> WL_O<181> ++ WL_O<180> WL_O<179> WL_O<178> WL_O<177> WL_O<176> VDD VSS / ++ RM_IHPSG13_1024x32_c2_1P_DEC04 +XSEL<10> ADDR_N_I<3> ADDR_N_I<2> ADDR_N_I<1> ADDR_N_I<0> CS00<10> ECLK_H<10> ++ ECLK_H<11> ECLK_B<10> ECLK_B<11> WL_O<175> WL_O<174> WL_O<173> WL_O<172> ++ WL_O<171> WL_O<170> WL_O<169> WL_O<168> WL_O<167> WL_O<166> WL_O<165> ++ WL_O<164> WL_O<163> WL_O<162> WL_O<161> WL_O<160> VDD VSS / ++ RM_IHPSG13_1024x32_c2_1P_DEC04 +XSEL<9> ADDR_N_I<3> ADDR_N_I<2> ADDR_N_I<1> ADDR_N_I<0> CS00<9> ECLK_H<9> ++ ECLK_H<10> ECLK_B<9> ECLK_B<10> WL_O<159> WL_O<158> WL_O<157> WL_O<156> ++ WL_O<155> WL_O<154> WL_O<153> WL_O<152> WL_O<151> WL_O<150> WL_O<149> ++ WL_O<148> WL_O<147> WL_O<146> WL_O<145> WL_O<144> VDD VSS / ++ RM_IHPSG13_1024x32_c2_1P_DEC04 +XSEL<8> ADDR_N_I<3> ADDR_N_I<2> ADDR_N_I<1> ADDR_N_I<0> CS00<8> ECLK_H<8> ++ ECLK_H<9> ECLK_B<8> ECLK_B<9> WL_O<143> WL_O<142> WL_O<141> WL_O<140> ++ WL_O<139> WL_O<138> WL_O<137> WL_O<136> WL_O<135> WL_O<134> WL_O<133> ++ WL_O<132> WL_O<131> WL_O<130> WL_O<129> WL_O<128> VDD VSS / ++ RM_IHPSG13_1024x32_c2_1P_DEC04 +XSEL<7> ADDR_N_I<3> ADDR_N_I<2> ADDR_N_I<1> ADDR_N_I<0> CS00<7> ECLK_H<7> ++ ECLK_H<8> ECLK_B<7> ECLK_B<8> WL_O<127> WL_O<126> WL_O<125> WL_O<124> ++ WL_O<123> WL_O<122> WL_O<121> WL_O<120> WL_O<119> WL_O<118> WL_O<117> ++ WL_O<116> WL_O<115> WL_O<114> WL_O<113> WL_O<112> VDD VSS / ++ RM_IHPSG13_1024x32_c2_1P_DEC04 +XSEL<6> ADDR_N_I<3> ADDR_N_I<2> ADDR_N_I<1> ADDR_N_I<0> CS00<6> ECLK_H<6> ++ ECLK_H<7> ECLK_B<6> ECLK_B<7> WL_O<111> WL_O<110> WL_O<109> WL_O<108> ++ WL_O<107> WL_O<106> WL_O<105> WL_O<104> WL_O<103> WL_O<102> WL_O<101> ++ WL_O<100> WL_O<99> WL_O<98> WL_O<97> WL_O<96> VDD VSS / ++ RM_IHPSG13_1024x32_c2_1P_DEC04 +XSEL<5> ADDR_N_I<3> ADDR_N_I<2> ADDR_N_I<1> ADDR_N_I<0> CS00<5> ECLK_H<5> ++ ECLK_H<6> ECLK_B<5> ECLK_B<6> WL_O<95> WL_O<94> WL_O<93> WL_O<92> WL_O<91> ++ WL_O<90> WL_O<89> WL_O<88> WL_O<87> WL_O<86> WL_O<85> WL_O<84> WL_O<83> ++ WL_O<82> WL_O<81> WL_O<80> VDD VSS / RM_IHPSG13_1024x32_c2_1P_DEC04 +XSEL<4> ADDR_N_I<3> ADDR_N_I<2> ADDR_N_I<1> ADDR_N_I<0> CS00<4> ECLK_H<4> ++ ECLK_H<5> ECLK_B<4> ECLK_B<5> WL_O<79> WL_O<78> WL_O<77> WL_O<76> WL_O<75> ++ WL_O<74> WL_O<73> WL_O<72> WL_O<71> WL_O<70> WL_O<69> WL_O<68> WL_O<67> ++ WL_O<66> WL_O<65> WL_O<64> VDD VSS / RM_IHPSG13_1024x32_c2_1P_DEC04 +XSEL<3> ADDR_N_I<3> ADDR_N_I<2> ADDR_N_I<1> ADDR_N_I<0> CS00<3> ECLK_H<3> ++ ECLK_H<4> ECLK_B<3> ECLK_B<4> WL_O<63> WL_O<62> WL_O<61> WL_O<60> WL_O<59> ++ WL_O<58> WL_O<57> WL_O<56> WL_O<55> WL_O<54> WL_O<53> WL_O<52> WL_O<51> ++ WL_O<50> WL_O<49> WL_O<48> VDD VSS / RM_IHPSG13_1024x32_c2_1P_DEC04 +XSEL<2> ADDR_N_I<3> ADDR_N_I<2> ADDR_N_I<1> ADDR_N_I<0> CS00<2> ECLK_H<2> ++ ECLK_H<3> ECLK_B<2> ECLK_B<3> WL_O<47> WL_O<46> WL_O<45> WL_O<44> WL_O<43> ++ WL_O<42> WL_O<41> WL_O<40> WL_O<39> WL_O<38> WL_O<37> WL_O<36> WL_O<35> ++ WL_O<34> WL_O<33> WL_O<32> VDD VSS / RM_IHPSG13_1024x32_c2_1P_DEC04 +XSEL<1> ADDR_N_I<3> ADDR_N_I<2> ADDR_N_I<1> ADDR_N_I<0> CS00<1> ECLK_H<1> ++ ECLK_H<2> ECLK_B<1> ECLK_B<2> WL_O<31> WL_O<30> WL_O<29> WL_O<28> WL_O<27> ++ WL_O<26> WL_O<25> WL_O<24> WL_O<23> WL_O<22> WL_O<21> WL_O<20> WL_O<19> ++ WL_O<18> WL_O<17> WL_O<16> VDD VSS / RM_IHPSG13_1024x32_c2_1P_DEC04 +XSEL<0> ADDR_N_I<3> ADDR_N_I<2> ADDR_N_I<1> ADDR_N_I<0> CS00<0> ECLK_I ++ ECLK_H<1> ECLK_B<0> ECLK_B<1> WL_O<15> WL_O<14> WL_O<13> WL_O<12> WL_O<11> ++ WL_O<10> WL_O<9> WL_O<8> WL_O<7> WL_O<6> WL_O<5> WL_O<4> WL_O<3> WL_O<2> ++ WL_O<1> WL_O<0> VDD VSS / RM_IHPSG13_1024x32_c2_1P_DEC04 +XDEC01<4> ADDR_N_I<7> ADDR_N_I<6> CS_I CS04<1> VDD VSS / ++ RM_IHPSG13_1024x32_c2_1P_DEC01 +XDEC01<3> ADDR_N_I<5> ADDR_N_I<4> CS04<3> CS00<13> VDD VSS / ++ RM_IHPSG13_1024x32_c2_1P_DEC01 +XDEC01<2> ADDR_N_I<5> ADDR_N_I<4> CS04<2> CS00<9> VDD VSS / ++ RM_IHPSG13_1024x32_c2_1P_DEC01 +XDEC01<1> ADDR_N_I<5> ADDR_N_I<4> CS04<1> CS00<5> VDD VSS / ++ RM_IHPSG13_1024x32_c2_1P_DEC01 +XDEC01<0> ADDR_N_I<5> ADDR_N_I<4> CS04<0> CS00<1> VDD VSS / ++ RM_IHPSG13_1024x32_c2_1P_DEC01 +.ENDS +.SUBCKT RM_IHPSG13_1024x32_c2_1P_ROWREG8 ACLK_N_I ADDR_I<7> ADDR_I<6> ADDR_I<5> ADDR_I<4> ++ ADDR_I<3> ADDR_I<2> ADDR_I<1> ADDR_I<0> ADDR_N_O<7> ADDR_N_O<6> ADDR_N_O<5> ++ ADDR_N_O<4> ADDR_N_O<3> ADDR_N_O<2> ADDR_N_O<1> ADDR_N_O<0> BIST_ADDR_I<7> ++ BIST_ADDR_I<6> BIST_ADDR_I<5> BIST_ADDR_I<4> BIST_ADDR_I<3> BIST_ADDR_I<2> ++ BIST_ADDR_I<1> BIST_ADDR_I<0> BIST_EN_I VDD VSS +XINV<7> q_int<7> qn_int<7> VDD VSS / RSC_IHPSG13_CINVX2 +XINV<6> q_int<6> qn_int<6> VDD VSS / RSC_IHPSG13_CINVX2 +XINV<5> q_int<5> qn_int<5> VDD VSS / RSC_IHPSG13_CINVX2 +XINV<4> q_int<4> qn_int<4> VDD VSS / RSC_IHPSG13_CINVX2 +XINV<3> q_int<3> qn_int<3> VDD VSS / RSC_IHPSG13_CINVX2 +XINV<2> q_int<2> qn_int<2> VDD VSS / RSC_IHPSG13_CINVX2 +XINV<1> q_int<1> qn_int<1> VDD VSS / RSC_IHPSG13_CINVX2 +XINV<0> q_int<0> qn_int<0> VDD VSS / RSC_IHPSG13_CINVX2 +XDRV<7> qn_int<7> ADDR_N_O<7> VDD VSS / RSC_IHPSG13_CINVX8 +XDRV<6> qn_int<6> ADDR_N_O<6> VDD VSS / RSC_IHPSG13_CINVX8 +XDRV<5> qn_int<5> ADDR_N_O<5> VDD VSS / RSC_IHPSG13_CINVX8 +XDRV<4> qn_int<4> ADDR_N_O<4> VDD VSS / RSC_IHPSG13_CINVX8 +XDRV<3> qn_int<3> ADDR_N_O<3> VDD VSS / RSC_IHPSG13_CINVX8 +XDRV<2> qn_int<2> ADDR_N_O<2> VDD VSS / RSC_IHPSG13_CINVX8 +XDRV<1> qn_int<1> ADDR_N_O<1> VDD VSS / RSC_IHPSG13_CINVX8 +XDRV<0> qn_int<0> ADDR_N_O<0> VDD VSS / RSC_IHPSG13_CINVX8 +XDFF<7> BIST_EN_I BIST_ADDR_I<7> ACLK_N_I ADDR_I<7> q_int<7> net2<0> VDD ++ VSS / RSC_IHPSG13_DFNQMX2IX1 +XDFF<6> BIST_EN_I BIST_ADDR_I<6> ACLK_N_I ADDR_I<6> q_int<6> net2<1> VDD ++ VSS / RSC_IHPSG13_DFNQMX2IX1 +XDFF<5> BIST_EN_I BIST_ADDR_I<5> ACLK_N_I ADDR_I<5> q_int<5> net2<2> VDD ++ VSS / RSC_IHPSG13_DFNQMX2IX1 +XDFF<4> BIST_EN_I BIST_ADDR_I<4> ACLK_N_I ADDR_I<4> q_int<4> net2<3> VDD ++ VSS / RSC_IHPSG13_DFNQMX2IX1 +XDFF<3> BIST_EN_I BIST_ADDR_I<3> ACLK_N_I ADDR_I<3> q_int<3> net2<4> VDD ++ VSS / RSC_IHPSG13_DFNQMX2IX1 +XDFF<2> BIST_EN_I BIST_ADDR_I<2> ACLK_N_I ADDR_I<2> q_int<2> net2<5> VDD ++ VSS / RSC_IHPSG13_DFNQMX2IX1 +XDFF<1> BIST_EN_I BIST_ADDR_I<1> ACLK_N_I ADDR_I<1> q_int<1> net2<6> VDD ++ VSS / RSC_IHPSG13_DFNQMX2IX1 +XDFF<0> BIST_EN_I BIST_ADDR_I<0> ACLK_N_I ADDR_I<0> q_int<0> net2<7> VDD ++ VSS / RSC_IHPSG13_DFNQMX2IX1 +XI11<4> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI11<3> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI11<2> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI11<1> VDD VSS / RSC_IHPSG13_FILLCAP8 +.ENDS + +.SUBCKT RM_IHPSG13_1024x32_c2_1P_ROWDEC9 ADDR_N_I<8> ADDR_N_I<7> ADDR_N_I<6> ADDR_N_I<5> ++ ADDR_N_I<4> ADDR_N_I<3> ADDR_N_I<2> ADDR_N_I<1> ADDR_N_I<0> CS_I ECLK_I ++ WL_O<511> WL_O<510> WL_O<509> WL_O<508> WL_O<507> WL_O<506> WL_O<505> ++ WL_O<504> WL_O<503> WL_O<502> WL_O<501> WL_O<500> WL_O<499> WL_O<498> ++ WL_O<497> WL_O<496> WL_O<495> WL_O<494> WL_O<493> WL_O<492> WL_O<491> ++ WL_O<490> WL_O<489> WL_O<488> WL_O<487> WL_O<486> WL_O<485> WL_O<484> ++ WL_O<483> WL_O<482> WL_O<481> WL_O<480> WL_O<479> WL_O<478> WL_O<477> ++ WL_O<476> WL_O<475> WL_O<474> WL_O<473> WL_O<472> WL_O<471> WL_O<470> ++ WL_O<469> WL_O<468> WL_O<467> WL_O<466> WL_O<465> WL_O<464> WL_O<463> ++ WL_O<462> WL_O<461> WL_O<460> WL_O<459> WL_O<458> WL_O<457> WL_O<456> ++ WL_O<455> WL_O<454> WL_O<453> WL_O<452> WL_O<451> WL_O<450> WL_O<449> ++ WL_O<448> WL_O<447> WL_O<446> WL_O<445> WL_O<444> WL_O<443> WL_O<442> ++ WL_O<441> WL_O<440> WL_O<439> WL_O<438> WL_O<437> WL_O<436> WL_O<435> ++ WL_O<434> WL_O<433> WL_O<432> WL_O<431> WL_O<430> WL_O<429> WL_O<428> ++ WL_O<427> WL_O<426> WL_O<425> WL_O<424> WL_O<423> WL_O<422> WL_O<421> ++ WL_O<420> WL_O<419> WL_O<418> WL_O<417> WL_O<416> WL_O<415> WL_O<414> ++ WL_O<413> WL_O<412> WL_O<411> WL_O<410> WL_O<409> WL_O<408> WL_O<407> ++ WL_O<406> WL_O<405> WL_O<404> WL_O<403> WL_O<402> WL_O<401> WL_O<400> ++ WL_O<399> WL_O<398> WL_O<397> WL_O<396> WL_O<395> WL_O<394> WL_O<393> ++ WL_O<392> WL_O<391> WL_O<390> WL_O<389> WL_O<388> WL_O<387> WL_O<386> ++ WL_O<385> WL_O<384> WL_O<383> WL_O<382> WL_O<381> WL_O<380> WL_O<379> ++ WL_O<378> WL_O<377> WL_O<376> WL_O<375> WL_O<374> WL_O<373> WL_O<372> ++ WL_O<371> WL_O<370> WL_O<369> WL_O<368> WL_O<367> WL_O<366> WL_O<365> ++ WL_O<364> WL_O<363> WL_O<362> WL_O<361> WL_O<360> WL_O<359> WL_O<358> ++ WL_O<357> WL_O<356> WL_O<355> WL_O<354> WL_O<353> WL_O<352> WL_O<351> ++ WL_O<350> WL_O<349> WL_O<348> WL_O<347> WL_O<346> WL_O<345> WL_O<344> ++ WL_O<343> WL_O<342> WL_O<341> WL_O<340> WL_O<339> WL_O<338> WL_O<337> ++ WL_O<336> WL_O<335> WL_O<334> WL_O<333> WL_O<332> WL_O<331> WL_O<330> ++ WL_O<329> WL_O<328> WL_O<327> WL_O<326> WL_O<325> WL_O<324> WL_O<323> ++ WL_O<322> WL_O<321> WL_O<320> WL_O<319> WL_O<318> WL_O<317> WL_O<316> ++ WL_O<315> WL_O<314> WL_O<313> WL_O<312> WL_O<311> WL_O<310> WL_O<309> ++ WL_O<308> WL_O<307> WL_O<306> WL_O<305> WL_O<304> WL_O<303> WL_O<302> ++ WL_O<301> WL_O<300> WL_O<299> WL_O<298> WL_O<297> WL_O<296> WL_O<295> ++ WL_O<294> WL_O<293> WL_O<292> WL_O<291> WL_O<290> WL_O<289> WL_O<288> ++ WL_O<287> WL_O<286> WL_O<285> WL_O<284> WL_O<283> WL_O<282> WL_O<281> ++ WL_O<280> WL_O<279> WL_O<278> WL_O<277> WL_O<276> WL_O<275> WL_O<274> ++ WL_O<273> WL_O<272> WL_O<271> WL_O<270> WL_O<269> WL_O<268> WL_O<267> ++ WL_O<266> WL_O<265> WL_O<264> WL_O<263> WL_O<262> WL_O<261> WL_O<260> ++ WL_O<259> WL_O<258> WL_O<257> WL_O<256> WL_O<255> WL_O<254> WL_O<253> ++ WL_O<252> WL_O<251> WL_O<250> WL_O<249> WL_O<248> WL_O<247> WL_O<246> ++ WL_O<245> WL_O<244> WL_O<243> WL_O<242> WL_O<241> WL_O<240> WL_O<239> ++ WL_O<238> WL_O<237> WL_O<236> WL_O<235> WL_O<234> WL_O<233> WL_O<232> ++ WL_O<231> WL_O<230> WL_O<229> WL_O<228> WL_O<227> WL_O<226> WL_O<225> ++ WL_O<224> WL_O<223> WL_O<222> WL_O<221> WL_O<220> WL_O<219> WL_O<218> ++ WL_O<217> WL_O<216> WL_O<215> WL_O<214> WL_O<213> WL_O<212> WL_O<211> ++ WL_O<210> WL_O<209> WL_O<208> WL_O<207> WL_O<206> WL_O<205> WL_O<204> ++ WL_O<203> WL_O<202> WL_O<201> WL_O<200> WL_O<199> WL_O<198> WL_O<197> ++ WL_O<196> WL_O<195> WL_O<194> WL_O<193> WL_O<192> WL_O<191> WL_O<190> ++ WL_O<189> WL_O<188> WL_O<187> WL_O<186> WL_O<185> WL_O<184> WL_O<183> ++ WL_O<182> WL_O<181> WL_O<180> WL_O<179> WL_O<178> WL_O<177> WL_O<176> ++ WL_O<175> WL_O<174> WL_O<173> WL_O<172> WL_O<171> WL_O<170> WL_O<169> ++ WL_O<168> WL_O<167> WL_O<166> WL_O<165> WL_O<164> WL_O<163> WL_O<162> ++ WL_O<161> WL_O<160> WL_O<159> WL_O<158> WL_O<157> WL_O<156> WL_O<155> ++ WL_O<154> WL_O<153> WL_O<152> WL_O<151> WL_O<150> WL_O<149> WL_O<148> ++ WL_O<147> WL_O<146> WL_O<145> WL_O<144> WL_O<143> WL_O<142> WL_O<141> ++ WL_O<140> WL_O<139> WL_O<138> WL_O<137> WL_O<136> WL_O<135> WL_O<134> ++ WL_O<133> WL_O<132> WL_O<131> WL_O<130> WL_O<129> WL_O<128> WL_O<127> ++ WL_O<126> WL_O<125> WL_O<124> WL_O<123> WL_O<122> WL_O<121> WL_O<120> ++ WL_O<119> WL_O<118> WL_O<117> WL_O<116> WL_O<115> WL_O<114> WL_O<113> ++ WL_O<112> WL_O<111> WL_O<110> WL_O<109> WL_O<108> WL_O<107> WL_O<106> ++ WL_O<105> WL_O<104> WL_O<103> WL_O<102> WL_O<101> WL_O<100> WL_O<99> ++ WL_O<98> WL_O<97> WL_O<96> WL_O<95> WL_O<94> WL_O<93> WL_O<92> WL_O<91> ++ WL_O<90> WL_O<89> WL_O<88> WL_O<87> WL_O<86> WL_O<85> WL_O<84> WL_O<83> ++ WL_O<82> WL_O<81> WL_O<80> WL_O<79> WL_O<78> WL_O<77> WL_O<76> WL_O<75> ++ WL_O<74> WL_O<73> WL_O<72> WL_O<71> WL_O<70> WL_O<69> WL_O<68> WL_O<67> ++ WL_O<66> WL_O<65> WL_O<64> WL_O<63> WL_O<62> WL_O<61> WL_O<60> WL_O<59> ++ WL_O<58> WL_O<57> WL_O<56> WL_O<55> WL_O<54> WL_O<53> WL_O<52> WL_O<51> ++ WL_O<50> WL_O<49> WL_O<48> WL_O<47> WL_O<46> WL_O<45> WL_O<44> WL_O<43> ++ WL_O<42> WL_O<41> WL_O<40> WL_O<39> WL_O<38> WL_O<37> WL_O<36> WL_O<35> ++ WL_O<34> WL_O<33> WL_O<32> WL_O<31> WL_O<30> WL_O<29> WL_O<28> WL_O<27> ++ WL_O<26> WL_O<25> WL_O<24> WL_O<23> WL_O<22> WL_O<21> WL_O<20> WL_O<19> ++ WL_O<18> WL_O<17> WL_O<16> WL_O<15> WL_O<14> WL_O<13> WL_O<12> WL_O<11> ++ WL_O<10> WL_O<9> WL_O<8> WL_O<7> WL_O<6> WL_O<5> WL_O<4> WL_O<3> WL_O<2> ++ WL_O<1> WL_O<0> VDD VSS +XL2<172> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<171> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<170> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<169> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<168> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<167> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<166> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<165> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<164> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<163> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<162> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<161> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<160> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<159> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<158> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<157> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<156> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<155> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<154> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<153> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<152> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<151> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<150> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<149> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<148> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<147> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<146> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<145> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<144> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<143> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<142> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<141> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<140> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<139> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<138> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<137> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<136> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<135> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<134> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<133> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<132> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<131> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<130> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<129> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<128> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<127> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<126> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<125> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<124> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<123> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<122> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<121> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<120> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<119> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<118> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<117> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<116> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<115> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<114> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<113> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<112> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<111> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<110> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<109> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<108> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<107> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<106> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<105> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<104> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<103> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<102> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<101> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<100> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<99> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<98> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<97> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<96> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<95> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<94> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<93> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<92> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<91> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<90> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<89> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<88> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<87> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<86> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<85> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<84> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<83> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<82> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<81> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<80> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<79> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<78> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<77> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<76> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<75> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<74> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<73> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<72> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<71> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<70> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<69> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<68> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<67> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<66> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<65> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<64> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<63> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<62> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<61> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<60> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<59> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<58> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<57> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<56> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<55> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<54> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<53> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<52> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<51> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<50> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<49> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<48> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<47> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<46> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<45> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<44> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<43> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<42> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<41> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<40> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<39> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<38> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<37> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<36> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<35> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<34> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<33> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<32> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<31> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<30> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<29> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<28> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<27> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<26> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<25> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<24> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<23> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<22> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<21> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<20> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<19> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<18> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<17> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<16> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<15> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<14> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<13> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<12> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<11> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<10> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<9> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<8> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<7> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<6> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<5> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<4> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<3> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<2> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<1> VDD VSS / RSC_IHPSG13_FILLCAP8 +XDEC11<9> ADDR_N_I<7> ADDR_N_I<6> CS04<1> CS02<7> VDD VSS / ++ RM_IHPSG13_1024x32_c2_1P_DEC03 +XDEC11<8> ADDR_N_I<7> ADDR_N_I<6> CS04<0> CS02<3> VDD VSS / ++ RM_IHPSG13_1024x32_c2_1P_DEC03 +XDEC11<7> ADDR_N_I<5> ADDR_N_I<4> CS02<7> CS00<31> VDD VSS / ++ RM_IHPSG13_1024x32_c2_1P_DEC03 +XDEC11<6> ADDR_N_I<5> ADDR_N_I<4> CS02<6> CS00<27> VDD VSS / ++ RM_IHPSG13_1024x32_c2_1P_DEC03 +XDEC11<5> ADDR_N_I<5> ADDR_N_I<4> CS02<5> CS00<23> VDD VSS / ++ RM_IHPSG13_1024x32_c2_1P_DEC03 +XDEC11<4> ADDR_N_I<5> ADDR_N_I<4> CS02<4> CS00<19> VDD VSS / ++ RM_IHPSG13_1024x32_c2_1P_DEC03 +XDEC11<3> ADDR_N_I<5> ADDR_N_I<4> CS02<3> CS00<15> VDD VSS / ++ RM_IHPSG13_1024x32_c2_1P_DEC03 +XDEC11<2> ADDR_N_I<5> ADDR_N_I<4> CS02<2> CS00<11> VDD VSS / ++ RM_IHPSG13_1024x32_c2_1P_DEC03 +XDEC11<1> ADDR_N_I<5> ADDR_N_I<4> CS02<1> CS00<7> VDD VSS / ++ RM_IHPSG13_1024x32_c2_1P_DEC03 +XDEC11<0> ADDR_N_I<5> ADDR_N_I<4> CS02<0> CS00<3> VDD VSS / ++ RM_IHPSG13_1024x32_c2_1P_DEC03 +XDEC00<10> ADDR_N_I<9> ADDR_N_I<8> CS_I CS04<0> VDD VSS / ++ RM_IHPSG13_1024x32_c2_1P_DEC00 +XDEC00<9> ADDR_N_I<7> ADDR_N_I<6> CS04<1> CS02<4> VDD VSS / ++ RM_IHPSG13_1024x32_c2_1P_DEC00 +XDEC00<8> ADDR_N_I<7> ADDR_N_I<6> CS04<0> CS02<0> VDD VSS / ++ RM_IHPSG13_1024x32_c2_1P_DEC00 +XDEC00<7> ADDR_N_I<5> ADDR_N_I<4> CS02<7> CS00<28> VDD VSS / ++ RM_IHPSG13_1024x32_c2_1P_DEC00 +XDEC00<6> ADDR_N_I<5> ADDR_N_I<4> CS02<6> CS00<24> VDD VSS / ++ RM_IHPSG13_1024x32_c2_1P_DEC00 +XDEC00<5> ADDR_N_I<5> ADDR_N_I<4> CS02<5> CS00<20> VDD VSS / ++ RM_IHPSG13_1024x32_c2_1P_DEC00 +XDEC00<4> ADDR_N_I<5> ADDR_N_I<4> CS02<4> CS00<16> VDD VSS / ++ RM_IHPSG13_1024x32_c2_1P_DEC00 +XDEC00<3> ADDR_N_I<5> ADDR_N_I<4> CS02<3> CS00<12> VDD VSS / ++ RM_IHPSG13_1024x32_c2_1P_DEC00 +XDEC00<2> ADDR_N_I<5> ADDR_N_I<4> CS02<2> CS00<8> VDD VSS / ++ RM_IHPSG13_1024x32_c2_1P_DEC00 +XDEC00<1> ADDR_N_I<5> ADDR_N_I<4> CS02<1> CS00<4> VDD VSS / ++ RM_IHPSG13_1024x32_c2_1P_DEC00 +XDEC00<0> ADDR_N_I<5> ADDR_N_I<4> CS02<0> CS00<0> VDD VSS / ++ RM_IHPSG13_1024x32_c2_1P_DEC00 +XSEL<31> ADDR_N_I<3> ADDR_N_I<2> ADDR_N_I<1> ADDR_N_I<0> CS00<31> ECLK_H<31> ++ ECLK_H<32> ECLK_B<31> ECLK_B<32> WL_O<511> WL_O<510> WL_O<509> WL_O<508> ++ WL_O<507> WL_O<506> WL_O<505> WL_O<504> WL_O<503> WL_O<502> WL_O<501> ++ WL_O<500> WL_O<499> WL_O<498> WL_O<497> WL_O<496> VDD VSS / ++ RM_IHPSG13_1024x32_c2_1P_DEC04 +XSEL<30> ADDR_N_I<3> ADDR_N_I<2> ADDR_N_I<1> ADDR_N_I<0> CS00<30> ECLK_H<30> ++ ECLK_H<31> ECLK_B<30> ECLK_B<31> WL_O<495> WL_O<494> WL_O<493> WL_O<492> ++ WL_O<491> WL_O<490> WL_O<489> WL_O<488> WL_O<487> WL_O<486> WL_O<485> ++ WL_O<484> WL_O<483> WL_O<482> WL_O<481> WL_O<480> VDD VSS / ++ RM_IHPSG13_1024x32_c2_1P_DEC04 +XSEL<29> ADDR_N_I<3> ADDR_N_I<2> ADDR_N_I<1> ADDR_N_I<0> CS00<29> ECLK_H<29> ++ ECLK_H<30> ECLK_B<29> ECLK_B<30> WL_O<479> WL_O<478> WL_O<477> WL_O<476> ++ WL_O<475> WL_O<474> WL_O<473> WL_O<472> WL_O<471> WL_O<470> WL_O<469> ++ WL_O<468> WL_O<467> WL_O<466> WL_O<465> WL_O<464> VDD VSS / ++ RM_IHPSG13_1024x32_c2_1P_DEC04 +XSEL<28> ADDR_N_I<3> ADDR_N_I<2> ADDR_N_I<1> ADDR_N_I<0> CS00<28> ECLK_H<28> ++ ECLK_H<29> ECLK_B<28> ECLK_B<29> WL_O<463> WL_O<462> WL_O<461> WL_O<460> ++ WL_O<459> WL_O<458> WL_O<457> WL_O<456> WL_O<455> WL_O<454> WL_O<453> ++ WL_O<452> WL_O<451> WL_O<450> WL_O<449> WL_O<448> VDD VSS / ++ RM_IHPSG13_1024x32_c2_1P_DEC04 +XSEL<27> ADDR_N_I<3> ADDR_N_I<2> ADDR_N_I<1> ADDR_N_I<0> CS00<27> ECLK_H<27> ++ ECLK_H<28> ECLK_B<27> ECLK_B<28> WL_O<447> WL_O<446> WL_O<445> WL_O<444> ++ WL_O<443> WL_O<442> WL_O<441> WL_O<440> WL_O<439> WL_O<438> WL_O<437> ++ WL_O<436> WL_O<435> WL_O<434> WL_O<433> WL_O<432> VDD VSS / ++ RM_IHPSG13_1024x32_c2_1P_DEC04 +XSEL<26> ADDR_N_I<3> ADDR_N_I<2> ADDR_N_I<1> ADDR_N_I<0> CS00<26> ECLK_H<26> ++ ECLK_H<27> ECLK_B<26> ECLK_B<27> WL_O<431> WL_O<430> WL_O<429> WL_O<428> ++ WL_O<427> WL_O<426> WL_O<425> WL_O<424> WL_O<423> WL_O<422> WL_O<421> ++ WL_O<420> WL_O<419> WL_O<418> WL_O<417> WL_O<416> VDD VSS / ++ RM_IHPSG13_1024x32_c2_1P_DEC04 +XSEL<25> ADDR_N_I<3> ADDR_N_I<2> ADDR_N_I<1> ADDR_N_I<0> CS00<25> ECLK_H<25> ++ ECLK_H<26> ECLK_B<25> ECLK_B<26> WL_O<415> WL_O<414> WL_O<413> WL_O<412> ++ WL_O<411> WL_O<410> WL_O<409> WL_O<408> WL_O<407> WL_O<406> WL_O<405> ++ WL_O<404> WL_O<403> WL_O<402> WL_O<401> WL_O<400> VDD VSS / ++ RM_IHPSG13_1024x32_c2_1P_DEC04 +XSEL<24> ADDR_N_I<3> ADDR_N_I<2> ADDR_N_I<1> ADDR_N_I<0> CS00<24> ECLK_H<24> ++ ECLK_H<25> ECLK_B<24> ECLK_B<25> WL_O<399> WL_O<398> WL_O<397> WL_O<396> ++ WL_O<395> WL_O<394> WL_O<393> WL_O<392> WL_O<391> WL_O<390> WL_O<389> ++ WL_O<388> WL_O<387> WL_O<386> WL_O<385> WL_O<384> VDD VSS / ++ RM_IHPSG13_1024x32_c2_1P_DEC04 +XSEL<23> ADDR_N_I<3> ADDR_N_I<2> ADDR_N_I<1> ADDR_N_I<0> CS00<23> ECLK_H<23> ++ ECLK_H<24> ECLK_B<23> ECLK_B<24> WL_O<383> WL_O<382> WL_O<381> WL_O<380> ++ WL_O<379> WL_O<378> WL_O<377> WL_O<376> WL_O<375> WL_O<374> WL_O<373> ++ WL_O<372> WL_O<371> WL_O<370> WL_O<369> WL_O<368> VDD VSS / ++ RM_IHPSG13_1024x32_c2_1P_DEC04 +XSEL<22> ADDR_N_I<3> ADDR_N_I<2> ADDR_N_I<1> ADDR_N_I<0> CS00<22> ECLK_H<22> ++ ECLK_H<23> ECLK_B<22> ECLK_B<23> WL_O<367> WL_O<366> WL_O<365> WL_O<364> ++ WL_O<363> WL_O<362> WL_O<361> WL_O<360> WL_O<359> WL_O<358> WL_O<357> ++ WL_O<356> WL_O<355> WL_O<354> WL_O<353> WL_O<352> VDD VSS / ++ RM_IHPSG13_1024x32_c2_1P_DEC04 +XSEL<21> ADDR_N_I<3> ADDR_N_I<2> ADDR_N_I<1> ADDR_N_I<0> CS00<21> ECLK_H<21> ++ ECLK_H<22> ECLK_B<21> ECLK_B<22> WL_O<351> WL_O<350> WL_O<349> WL_O<348> ++ WL_O<347> WL_O<346> WL_O<345> WL_O<344> WL_O<343> WL_O<342> WL_O<341> ++ WL_O<340> WL_O<339> WL_O<338> WL_O<337> WL_O<336> VDD VSS / ++ RM_IHPSG13_1024x32_c2_1P_DEC04 +XSEL<20> ADDR_N_I<3> ADDR_N_I<2> ADDR_N_I<1> ADDR_N_I<0> CS00<20> ECLK_H<20> ++ ECLK_H<21> ECLK_B<20> ECLK_B<21> WL_O<335> WL_O<334> WL_O<333> WL_O<332> ++ WL_O<331> WL_O<330> WL_O<329> WL_O<328> WL_O<327> WL_O<326> WL_O<325> ++ WL_O<324> WL_O<323> WL_O<322> WL_O<321> WL_O<320> VDD VSS / ++ RM_IHPSG13_1024x32_c2_1P_DEC04 +XSEL<19> ADDR_N_I<3> ADDR_N_I<2> ADDR_N_I<1> ADDR_N_I<0> CS00<19> ECLK_H<19> ++ ECLK_H<20> ECLK_B<19> ECLK_B<20> WL_O<319> WL_O<318> WL_O<317> WL_O<316> ++ WL_O<315> WL_O<314> WL_O<313> WL_O<312> WL_O<311> WL_O<310> WL_O<309> ++ WL_O<308> WL_O<307> WL_O<306> WL_O<305> WL_O<304> VDD VSS / ++ RM_IHPSG13_1024x32_c2_1P_DEC04 +XSEL<18> ADDR_N_I<3> ADDR_N_I<2> ADDR_N_I<1> ADDR_N_I<0> CS00<18> ECLK_H<18> ++ ECLK_H<19> ECLK_B<18> ECLK_B<19> WL_O<303> WL_O<302> WL_O<301> WL_O<300> ++ WL_O<299> WL_O<298> WL_O<297> WL_O<296> WL_O<295> WL_O<294> WL_O<293> ++ WL_O<292> WL_O<291> WL_O<290> WL_O<289> WL_O<288> VDD VSS / ++ RM_IHPSG13_1024x32_c2_1P_DEC04 +XSEL<17> ADDR_N_I<3> ADDR_N_I<2> ADDR_N_I<1> ADDR_N_I<0> CS00<17> ECLK_H<17> ++ ECLK_H<18> ECLK_B<17> ECLK_B<18> WL_O<287> WL_O<286> WL_O<285> WL_O<284> ++ WL_O<283> WL_O<282> WL_O<281> WL_O<280> WL_O<279> WL_O<278> WL_O<277> ++ WL_O<276> WL_O<275> WL_O<274> WL_O<273> WL_O<272> VDD VSS / ++ RM_IHPSG13_1024x32_c2_1P_DEC04 +XSEL<16> ADDR_N_I<3> ADDR_N_I<2> ADDR_N_I<1> ADDR_N_I<0> CS00<16> ECLK_H<16> ++ ECLK_H<17> ECLK_B<16> ECLK_B<17> WL_O<271> WL_O<270> WL_O<269> WL_O<268> ++ WL_O<267> WL_O<266> WL_O<265> WL_O<264> WL_O<263> WL_O<262> WL_O<261> ++ WL_O<260> WL_O<259> WL_O<258> WL_O<257> WL_O<256> VDD VSS / ++ RM_IHPSG13_1024x32_c2_1P_DEC04 +XSEL<15> ADDR_N_I<3> ADDR_N_I<2> ADDR_N_I<1> ADDR_N_I<0> CS00<15> ECLK_H<15> ++ ECLK_H<16> ECLK_B<15> ECLK_B<16> WL_O<255> WL_O<254> WL_O<253> WL_O<252> ++ WL_O<251> WL_O<250> WL_O<249> WL_O<248> WL_O<247> WL_O<246> WL_O<245> ++ WL_O<244> WL_O<243> WL_O<242> WL_O<241> WL_O<240> VDD VSS / ++ RM_IHPSG13_1024x32_c2_1P_DEC04 +XSEL<14> ADDR_N_I<3> ADDR_N_I<2> ADDR_N_I<1> ADDR_N_I<0> CS00<14> ECLK_H<14> ++ ECLK_H<15> ECLK_B<14> ECLK_B<15> WL_O<239> WL_O<238> WL_O<237> WL_O<236> ++ WL_O<235> WL_O<234> WL_O<233> WL_O<232> WL_O<231> WL_O<230> WL_O<229> ++ WL_O<228> WL_O<227> WL_O<226> WL_O<225> WL_O<224> VDD VSS / ++ RM_IHPSG13_1024x32_c2_1P_DEC04 +XSEL<13> ADDR_N_I<3> ADDR_N_I<2> ADDR_N_I<1> ADDR_N_I<0> CS00<13> ECLK_H<13> ++ ECLK_H<14> ECLK_B<13> ECLK_B<14> WL_O<223> WL_O<222> WL_O<221> WL_O<220> ++ WL_O<219> WL_O<218> WL_O<217> WL_O<216> WL_O<215> WL_O<214> WL_O<213> ++ WL_O<212> WL_O<211> WL_O<210> WL_O<209> WL_O<208> VDD VSS / ++ RM_IHPSG13_1024x32_c2_1P_DEC04 +XSEL<12> ADDR_N_I<3> ADDR_N_I<2> ADDR_N_I<1> ADDR_N_I<0> CS00<12> ECLK_H<12> ++ ECLK_H<13> ECLK_B<12> ECLK_B<13> WL_O<207> WL_O<206> WL_O<205> WL_O<204> ++ WL_O<203> WL_O<202> WL_O<201> WL_O<200> WL_O<199> WL_O<198> WL_O<197> ++ WL_O<196> WL_O<195> WL_O<194> WL_O<193> WL_O<192> VDD VSS / ++ RM_IHPSG13_1024x32_c2_1P_DEC04 +XSEL<11> ADDR_N_I<3> ADDR_N_I<2> ADDR_N_I<1> ADDR_N_I<0> CS00<11> ECLK_H<11> ++ ECLK_H<12> ECLK_B<11> ECLK_B<12> WL_O<191> WL_O<190> WL_O<189> WL_O<188> ++ WL_O<187> WL_O<186> WL_O<185> WL_O<184> WL_O<183> WL_O<182> WL_O<181> ++ WL_O<180> WL_O<179> WL_O<178> WL_O<177> WL_O<176> VDD VSS / ++ RM_IHPSG13_1024x32_c2_1P_DEC04 +XSEL<10> ADDR_N_I<3> ADDR_N_I<2> ADDR_N_I<1> ADDR_N_I<0> CS00<10> ECLK_H<10> ++ ECLK_H<11> ECLK_B<10> ECLK_B<11> WL_O<175> WL_O<174> WL_O<173> WL_O<172> ++ WL_O<171> WL_O<170> WL_O<169> WL_O<168> WL_O<167> WL_O<166> WL_O<165> ++ WL_O<164> WL_O<163> WL_O<162> WL_O<161> WL_O<160> VDD VSS / ++ RM_IHPSG13_1024x32_c2_1P_DEC04 +XSEL<9> ADDR_N_I<3> ADDR_N_I<2> ADDR_N_I<1> ADDR_N_I<0> CS00<9> ECLK_H<9> ++ ECLK_H<10> ECLK_B<9> ECLK_B<10> WL_O<159> WL_O<158> WL_O<157> WL_O<156> ++ WL_O<155> WL_O<154> WL_O<153> WL_O<152> WL_O<151> WL_O<150> WL_O<149> ++ WL_O<148> WL_O<147> WL_O<146> WL_O<145> WL_O<144> VDD VSS / ++ RM_IHPSG13_1024x32_c2_1P_DEC04 +XSEL<8> ADDR_N_I<3> ADDR_N_I<2> ADDR_N_I<1> ADDR_N_I<0> CS00<8> ECLK_H<8> ++ ECLK_H<9> ECLK_B<8> ECLK_B<9> WL_O<143> WL_O<142> WL_O<141> WL_O<140> ++ WL_O<139> WL_O<138> WL_O<137> WL_O<136> WL_O<135> WL_O<134> WL_O<133> ++ WL_O<132> WL_O<131> WL_O<130> WL_O<129> WL_O<128> VDD VSS / ++ RM_IHPSG13_1024x32_c2_1P_DEC04 +XSEL<7> ADDR_N_I<3> ADDR_N_I<2> ADDR_N_I<1> ADDR_N_I<0> CS00<7> ECLK_H<7> ++ ECLK_H<8> ECLK_B<7> ECLK_B<8> WL_O<127> WL_O<126> WL_O<125> WL_O<124> ++ WL_O<123> WL_O<122> WL_O<121> WL_O<120> WL_O<119> WL_O<118> WL_O<117> ++ WL_O<116> WL_O<115> WL_O<114> WL_O<113> WL_O<112> VDD VSS / ++ RM_IHPSG13_1024x32_c2_1P_DEC04 +XSEL<6> ADDR_N_I<3> ADDR_N_I<2> ADDR_N_I<1> ADDR_N_I<0> CS00<6> ECLK_H<6> ++ ECLK_H<7> ECLK_B<6> ECLK_B<7> WL_O<111> WL_O<110> WL_O<109> WL_O<108> ++ WL_O<107> WL_O<106> WL_O<105> WL_O<104> WL_O<103> WL_O<102> WL_O<101> ++ WL_O<100> WL_O<99> WL_O<98> WL_O<97> WL_O<96> VDD VSS / ++ RM_IHPSG13_1024x32_c2_1P_DEC04 +XSEL<5> ADDR_N_I<3> ADDR_N_I<2> ADDR_N_I<1> ADDR_N_I<0> CS00<5> ECLK_H<5> ++ ECLK_H<6> ECLK_B<5> ECLK_B<6> WL_O<95> WL_O<94> WL_O<93> WL_O<92> WL_O<91> ++ WL_O<90> WL_O<89> WL_O<88> WL_O<87> WL_O<86> WL_O<85> WL_O<84> WL_O<83> ++ WL_O<82> WL_O<81> WL_O<80> VDD VSS / RM_IHPSG13_1024x32_c2_1P_DEC04 +XSEL<4> ADDR_N_I<3> ADDR_N_I<2> ADDR_N_I<1> ADDR_N_I<0> CS00<4> ECLK_H<4> ++ ECLK_H<5> ECLK_B<4> ECLK_B<5> WL_O<79> WL_O<78> WL_O<77> WL_O<76> WL_O<75> ++ WL_O<74> WL_O<73> WL_O<72> WL_O<71> WL_O<70> WL_O<69> WL_O<68> WL_O<67> ++ WL_O<66> WL_O<65> WL_O<64> VDD VSS / RM_IHPSG13_1024x32_c2_1P_DEC04 +XSEL<3> ADDR_N_I<3> ADDR_N_I<2> ADDR_N_I<1> ADDR_N_I<0> CS00<3> ECLK_H<3> ++ ECLK_H<4> ECLK_B<3> ECLK_B<4> WL_O<63> WL_O<62> WL_O<61> WL_O<60> WL_O<59> ++ WL_O<58> WL_O<57> WL_O<56> WL_O<55> WL_O<54> WL_O<53> WL_O<52> WL_O<51> ++ WL_O<50> WL_O<49> WL_O<48> VDD VSS / RM_IHPSG13_1024x32_c2_1P_DEC04 +XSEL<2> ADDR_N_I<3> ADDR_N_I<2> ADDR_N_I<1> ADDR_N_I<0> CS00<2> ECLK_H<2> ++ ECLK_H<3> ECLK_B<2> ECLK_B<3> WL_O<47> WL_O<46> WL_O<45> WL_O<44> WL_O<43> ++ WL_O<42> WL_O<41> WL_O<40> WL_O<39> WL_O<38> WL_O<37> WL_O<36> WL_O<35> ++ WL_O<34> WL_O<33> WL_O<32> VDD VSS / RM_IHPSG13_1024x32_c2_1P_DEC04 +XSEL<1> ADDR_N_I<3> ADDR_N_I<2> ADDR_N_I<1> ADDR_N_I<0> CS00<1> ECLK_H<1> ++ ECLK_H<2> ECLK_B<1> ECLK_B<2> WL_O<31> WL_O<30> WL_O<29> WL_O<28> WL_O<27> ++ WL_O<26> WL_O<25> WL_O<24> WL_O<23> WL_O<22> WL_O<21> WL_O<20> WL_O<19> ++ WL_O<18> WL_O<17> WL_O<16> VDD VSS / RM_IHPSG13_1024x32_c2_1P_DEC04 +XSEL<0> ADDR_N_I<3> ADDR_N_I<2> ADDR_N_I<1> ADDR_N_I<0> CS00<0> ECLK_I ++ ECLK_H<1> ECLK_B<0> ECLK_B<1> WL_O<15> WL_O<14> WL_O<13> WL_O<12> WL_O<11> ++ WL_O<10> WL_O<9> WL_O<8> WL_O<7> WL_O<6> WL_O<5> WL_O<4> WL_O<3> WL_O<2> ++ WL_O<1> WL_O<0> VDD VSS / RM_IHPSG13_1024x32_c2_1P_DEC04 +XDEC01<10> ADDR_N_I<9> ADDR_N_I<8> CS_I CS04<1> VDD VSS / ++ RM_IHPSG13_1024x32_c2_1P_DEC01 +XDEC01<9> ADDR_N_I<7> ADDR_N_I<6> CS04<1> CS02<5> VDD VSS / ++ RM_IHPSG13_1024x32_c2_1P_DEC01 +XDEC01<8> ADDR_N_I<7> ADDR_N_I<6> CS04<0> CS02<1> VDD VSS / ++ RM_IHPSG13_1024x32_c2_1P_DEC01 +XDEC01<7> ADDR_N_I<5> ADDR_N_I<4> CS02<7> CS00<29> VDD VSS / ++ RM_IHPSG13_1024x32_c2_1P_DEC01 +XDEC01<6> ADDR_N_I<5> ADDR_N_I<4> CS02<6> CS00<25> VDD VSS / ++ RM_IHPSG13_1024x32_c2_1P_DEC01 +XDEC01<5> ADDR_N_I<5> ADDR_N_I<4> CS02<5> CS00<21> VDD VSS / ++ RM_IHPSG13_1024x32_c2_1P_DEC01 +XDEC01<4> ADDR_N_I<5> ADDR_N_I<4> CS02<4> CS00<17> VDD VSS / ++ RM_IHPSG13_1024x32_c2_1P_DEC01 +XDEC01<3> ADDR_N_I<5> ADDR_N_I<4> CS02<3> CS00<13> VDD VSS / ++ RM_IHPSG13_1024x32_c2_1P_DEC01 +XDEC01<2> ADDR_N_I<5> ADDR_N_I<4> CS02<2> CS00<9> VDD VSS / ++ RM_IHPSG13_1024x32_c2_1P_DEC01 +XDEC01<1> ADDR_N_I<5> ADDR_N_I<4> CS02<1> CS00<5> VDD VSS / ++ RM_IHPSG13_1024x32_c2_1P_DEC01 +XDEC01<0> ADDR_N_I<5> ADDR_N_I<4> CS02<0> CS00<1> VDD VSS / ++ RM_IHPSG13_1024x32_c2_1P_DEC01 +XDEC10<9> ADDR_N_I<7> ADDR_N_I<6> CS04<1> CS02<6> VDD VSS / ++ RM_IHPSG13_1024x32_c2_1P_DEC02 +XDEC10<8> ADDR_N_I<7> ADDR_N_I<6> CS04<0> CS02<2> VDD VSS / ++ RM_IHPSG13_1024x32_c2_1P_DEC02 +XDEC10<7> ADDR_N_I<5> ADDR_N_I<4> CS02<7> CS00<30> VDD VSS / ++ RM_IHPSG13_1024x32_c2_1P_DEC02 +XDEC10<6> ADDR_N_I<5> ADDR_N_I<4> CS02<6> CS00<26> VDD VSS / ++ RM_IHPSG13_1024x32_c2_1P_DEC02 +XDEC10<5> ADDR_N_I<5> ADDR_N_I<4> CS02<5> CS00<22> VDD VSS / ++ RM_IHPSG13_1024x32_c2_1P_DEC02 +XDEC10<4> ADDR_N_I<5> ADDR_N_I<4> CS02<4> CS00<18> VDD VSS / ++ RM_IHPSG13_1024x32_c2_1P_DEC02 +XDEC10<3> ADDR_N_I<5> ADDR_N_I<4> CS02<3> CS00<14> VDD VSS / ++ RM_IHPSG13_1024x32_c2_1P_DEC02 +XDEC10<2> ADDR_N_I<5> ADDR_N_I<4> CS02<2> CS00<10> VDD VSS / ++ RM_IHPSG13_1024x32_c2_1P_DEC02 +XDEC10<1> ADDR_N_I<5> ADDR_N_I<4> CS02<1> CS00<6> VDD VSS / ++ RM_IHPSG13_1024x32_c2_1P_DEC02 +XDEC10<0> ADDR_N_I<5> ADDR_N_I<4> CS02<0> CS00<2> VDD VSS / ++ RM_IHPSG13_1024x32_c2_1P_DEC02 +XI0 ADDR_N_I<9> VDD VSS / RSC_IHPSG13_TIEL +.ENDS +.SUBCKT RM_IHPSG13_1024x32_c2_1P_ROWREG9 ACLK_N_I ADDR_I<8> ADDR_I<7> ADDR_I<6> ADDR_I<5> ++ ADDR_I<4> ADDR_I<3> ADDR_I<2> ADDR_I<1> ADDR_I<0> ADDR_N_O<8> ADDR_N_O<7> ++ ADDR_N_O<6> ADDR_N_O<5> ADDR_N_O<4> ADDR_N_O<3> ADDR_N_O<2> ADDR_N_O<1> ++ ADDR_N_O<0> BIST_ADDR_I<8> BIST_ADDR_I<7> BIST_ADDR_I<6> BIST_ADDR_I<5> ++ BIST_ADDR_I<4> BIST_ADDR_I<3> BIST_ADDR_I<2> BIST_ADDR_I<1> BIST_ADDR_I<0> ++ BIST_EN_I VDD VSS +XINV<8> q_int<8> qn_int<8> VDD VSS / RSC_IHPSG13_CINVX2 +XINV<7> q_int<7> qn_int<7> VDD VSS / RSC_IHPSG13_CINVX2 +XINV<6> q_int<6> qn_int<6> VDD VSS / RSC_IHPSG13_CINVX2 +XINV<5> q_int<5> qn_int<5> VDD VSS / RSC_IHPSG13_CINVX2 +XINV<4> q_int<4> qn_int<4> VDD VSS / RSC_IHPSG13_CINVX2 +XINV<3> q_int<3> qn_int<3> VDD VSS / RSC_IHPSG13_CINVX2 +XINV<2> q_int<2> qn_int<2> VDD VSS / RSC_IHPSG13_CINVX2 +XINV<1> q_int<1> qn_int<1> VDD VSS / RSC_IHPSG13_CINVX2 +XINV<0> q_int<0> qn_int<0> VDD VSS / RSC_IHPSG13_CINVX2 +XDRV<8> qn_int<8> ADDR_N_O<8> VDD VSS / RSC_IHPSG13_CINVX8 +XDRV<7> qn_int<7> ADDR_N_O<7> VDD VSS / RSC_IHPSG13_CINVX8 +XDRV<6> qn_int<6> ADDR_N_O<6> VDD VSS / RSC_IHPSG13_CINVX8 +XDRV<5> qn_int<5> ADDR_N_O<5> VDD VSS / RSC_IHPSG13_CINVX8 +XDRV<4> qn_int<4> ADDR_N_O<4> VDD VSS / RSC_IHPSG13_CINVX8 +XDRV<3> qn_int<3> ADDR_N_O<3> VDD VSS / RSC_IHPSG13_CINVX8 +XDRV<2> qn_int<2> ADDR_N_O<2> VDD VSS / RSC_IHPSG13_CINVX8 +XDRV<1> qn_int<1> ADDR_N_O<1> VDD VSS / RSC_IHPSG13_CINVX8 +XDRV<0> qn_int<0> ADDR_N_O<0> VDD VSS / RSC_IHPSG13_CINVX8 +XDFF<8> BIST_EN_I BIST_ADDR_I<8> ACLK_N_I ADDR_I<8> q_int<8> net04<0> VDD ++ VSS / RSC_IHPSG13_DFNQMX2IX1 +XDFF<7> BIST_EN_I BIST_ADDR_I<7> ACLK_N_I ADDR_I<7> q_int<7> net04<1> VDD ++ VSS / RSC_IHPSG13_DFNQMX2IX1 +XDFF<6> BIST_EN_I BIST_ADDR_I<6> ACLK_N_I ADDR_I<6> q_int<6> net04<2> VDD ++ VSS / RSC_IHPSG13_DFNQMX2IX1 +XDFF<5> BIST_EN_I BIST_ADDR_I<5> ACLK_N_I ADDR_I<5> q_int<5> net04<3> VDD ++ VSS / RSC_IHPSG13_DFNQMX2IX1 +XDFF<4> BIST_EN_I BIST_ADDR_I<4> ACLK_N_I ADDR_I<4> q_int<4> net04<4> VDD ++ VSS / RSC_IHPSG13_DFNQMX2IX1 +XDFF<3> BIST_EN_I BIST_ADDR_I<3> ACLK_N_I ADDR_I<3> q_int<3> net04<5> VDD ++ VSS / RSC_IHPSG13_DFNQMX2IX1 +XDFF<2> BIST_EN_I BIST_ADDR_I<2> ACLK_N_I ADDR_I<2> q_int<2> net04<6> VDD ++ VSS / RSC_IHPSG13_DFNQMX2IX1 +XDFF<1> BIST_EN_I BIST_ADDR_I<1> ACLK_N_I ADDR_I<1> q_int<1> net04<7> VDD ++ VSS / RSC_IHPSG13_DFNQMX2IX1 +XDFF<0> BIST_EN_I BIST_ADDR_I<0> ACLK_N_I ADDR_I<0> q_int<0> net04<8> VDD ++ VSS / RSC_IHPSG13_DFNQMX2IX1 +.ENDS + +.SUBCKT RM_IHPSG13_1024x32_c2_1P_ROWDEC7 ADDR_N_I<6> ADDR_N_I<5> ADDR_N_I<4> ADDR_N_I<3> ++ ADDR_N_I<2> ADDR_N_I<1> ADDR_N_I<0> CS_I ECLK_I WL_O<127> WL_O<126> ++ WL_O<125> WL_O<124> WL_O<123> WL_O<122> WL_O<121> WL_O<120> WL_O<119> ++ WL_O<118> WL_O<117> WL_O<116> WL_O<115> WL_O<114> WL_O<113> WL_O<112> ++ WL_O<111> WL_O<110> WL_O<109> WL_O<108> WL_O<107> WL_O<106> WL_O<105> ++ WL_O<104> WL_O<103> WL_O<102> WL_O<101> WL_O<100> WL_O<99> WL_O<98> WL_O<97> ++ WL_O<96> WL_O<95> WL_O<94> WL_O<93> WL_O<92> WL_O<91> WL_O<90> WL_O<89> ++ WL_O<88> WL_O<87> WL_O<86> WL_O<85> WL_O<84> WL_O<83> WL_O<82> WL_O<81> ++ WL_O<80> WL_O<79> WL_O<78> WL_O<77> WL_O<76> WL_O<75> WL_O<74> WL_O<73> ++ WL_O<72> WL_O<71> WL_O<70> WL_O<69> WL_O<68> WL_O<67> WL_O<66> WL_O<65> ++ WL_O<64> WL_O<63> WL_O<62> WL_O<61> WL_O<60> WL_O<59> WL_O<58> WL_O<57> ++ WL_O<56> WL_O<55> WL_O<54> WL_O<53> WL_O<52> WL_O<51> WL_O<50> WL_O<49> ++ WL_O<48> WL_O<47> WL_O<46> WL_O<45> WL_O<44> WL_O<43> WL_O<42> WL_O<41> ++ WL_O<40> WL_O<39> WL_O<38> WL_O<37> WL_O<36> WL_O<35> WL_O<34> WL_O<33> ++ WL_O<32> WL_O<31> WL_O<30> WL_O<29> WL_O<28> WL_O<27> WL_O<26> WL_O<25> ++ WL_O<24> WL_O<23> WL_O<22> WL_O<21> WL_O<20> WL_O<19> WL_O<18> WL_O<17> ++ WL_O<16> WL_O<15> WL_O<14> WL_O<13> WL_O<12> WL_O<11> WL_O<10> WL_O<9> ++ WL_O<8> WL_O<7> WL_O<6> WL_O<5> WL_O<4> WL_O<3> WL_O<2> WL_O<1> WL_O<0> ++ VDD VSS +XDEC11<1> ADDR_N_I<5> ADDR_N_I<4> CS04<1> CS00<7> VDD VSS / ++ RM_IHPSG13_1024x32_c2_1P_DEC03 +XDEC11<0> ADDR_N_I<5> ADDR_N_I<4> CS04<0> CS00<3> VDD VSS / ++ RM_IHPSG13_1024x32_c2_1P_DEC03 +XDEC10<1> ADDR_N_I<5> ADDR_N_I<4> CS04<1> CS00<6> VDD VSS / ++ RM_IHPSG13_1024x32_c2_1P_DEC02 +XDEC10<0> ADDR_N_I<5> ADDR_N_I<4> CS04<0> CS00<2> VDD VSS / ++ RM_IHPSG13_1024x32_c2_1P_DEC02 +XSEL<7> ADDR_N_I<3> ADDR_N_I<2> ADDR_N_I<1> ADDR_N_I<0> CS00<7> ECLK_H<7> ++ ECLK_H<8> ECLK_B<7> ECLK_B<8> WL_O<127> WL_O<126> WL_O<125> WL_O<124> ++ WL_O<123> WL_O<122> WL_O<121> WL_O<120> WL_O<119> WL_O<118> WL_O<117> ++ WL_O<116> WL_O<115> WL_O<114> WL_O<113> WL_O<112> VDD VSS / ++ RM_IHPSG13_1024x32_c2_1P_DEC04 +XSEL<6> ADDR_N_I<3> ADDR_N_I<2> ADDR_N_I<1> ADDR_N_I<0> CS00<6> ECLK_H<6> ++ ECLK_H<7> ECLK_B<6> ECLK_B<7> WL_O<111> WL_O<110> WL_O<109> WL_O<108> ++ WL_O<107> WL_O<106> WL_O<105> WL_O<104> WL_O<103> WL_O<102> WL_O<101> ++ WL_O<100> WL_O<99> WL_O<98> WL_O<97> WL_O<96> VDD VSS / ++ RM_IHPSG13_1024x32_c2_1P_DEC04 +XSEL<5> ADDR_N_I<3> ADDR_N_I<2> ADDR_N_I<1> ADDR_N_I<0> CS00<5> ECLK_H<5> ++ ECLK_H<6> ECLK_B<5> ECLK_B<6> WL_O<95> WL_O<94> WL_O<93> WL_O<92> WL_O<91> ++ WL_O<90> WL_O<89> WL_O<88> WL_O<87> WL_O<86> WL_O<85> WL_O<84> WL_O<83> ++ WL_O<82> WL_O<81> WL_O<80> VDD VSS / RM_IHPSG13_1024x32_c2_1P_DEC04 +XSEL<4> ADDR_N_I<3> ADDR_N_I<2> ADDR_N_I<1> ADDR_N_I<0> CS00<4> ECLK_H<4> ++ ECLK_H<5> ECLK_B<4> ECLK_B<5> WL_O<79> WL_O<78> WL_O<77> WL_O<76> WL_O<75> ++ WL_O<74> WL_O<73> WL_O<72> WL_O<71> WL_O<70> WL_O<69> WL_O<68> WL_O<67> ++ WL_O<66> WL_O<65> WL_O<64> VDD VSS / RM_IHPSG13_1024x32_c2_1P_DEC04 +XSEL<3> ADDR_N_I<3> ADDR_N_I<2> ADDR_N_I<1> ADDR_N_I<0> CS00<3> ECLK_H<3> ++ ECLK_H<4> ECLK_B<3> ECLK_B<4> WL_O<63> WL_O<62> WL_O<61> WL_O<60> WL_O<59> ++ WL_O<58> WL_O<57> WL_O<56> WL_O<55> WL_O<54> WL_O<53> WL_O<52> WL_O<51> ++ WL_O<50> WL_O<49> WL_O<48> VDD VSS / RM_IHPSG13_1024x32_c2_1P_DEC04 +XSEL<2> ADDR_N_I<3> ADDR_N_I<2> ADDR_N_I<1> ADDR_N_I<0> CS00<2> ECLK_H<2> ++ ECLK_H<3> ECLK_B<2> ECLK_B<3> WL_O<47> WL_O<46> WL_O<45> WL_O<44> WL_O<43> ++ WL_O<42> WL_O<41> WL_O<40> WL_O<39> WL_O<38> WL_O<37> WL_O<36> WL_O<35> ++ WL_O<34> WL_O<33> WL_O<32> VDD VSS / RM_IHPSG13_1024x32_c2_1P_DEC04 +XSEL<1> ADDR_N_I<3> ADDR_N_I<2> ADDR_N_I<1> ADDR_N_I<0> CS00<1> ECLK_H<1> ++ ECLK_H<2> ECLK_B<1> ECLK_B<2> WL_O<31> WL_O<30> WL_O<29> WL_O<28> WL_O<27> ++ WL_O<26> WL_O<25> WL_O<24> WL_O<23> WL_O<22> WL_O<21> WL_O<20> WL_O<19> ++ WL_O<18> WL_O<17> WL_O<16> VDD VSS / RM_IHPSG13_1024x32_c2_1P_DEC04 +XSEL<0> ADDR_N_I<3> ADDR_N_I<2> ADDR_N_I<1> ADDR_N_I<0> CS00<0> ECLK_I ++ ECLK_H<1> ECLK_B<0> ECLK_B<1> WL_O<15> WL_O<14> WL_O<13> WL_O<12> WL_O<11> ++ WL_O<10> WL_O<9> WL_O<8> WL_O<7> WL_O<6> WL_O<5> WL_O<4> WL_O<3> WL_O<2> ++ WL_O<1> WL_O<0> VDD VSS / RM_IHPSG13_1024x32_c2_1P_DEC04 +XDEC00<2> ADDR_N_I<7> ADDR_N_I<6> CS_I CS04<0> VDD VSS / ++ RM_IHPSG13_1024x32_c2_1P_DEC00 +XDEC00<1> ADDR_N_I<5> ADDR_N_I<4> CS04<1> CS00<4> VDD VSS / ++ RM_IHPSG13_1024x32_c2_1P_DEC00 +XDEC00<0> ADDR_N_I<5> ADDR_N_I<4> CS04<0> CS00<0> VDD VSS / ++ RM_IHPSG13_1024x32_c2_1P_DEC00 +XDEC01<2> ADDR_N_I<7> ADDR_N_I<6> CS_I CS04<1> VDD VSS / ++ RM_IHPSG13_1024x32_c2_1P_DEC01 +XDEC01<1> ADDR_N_I<5> ADDR_N_I<4> CS04<1> CS00<5> VDD VSS / ++ RM_IHPSG13_1024x32_c2_1P_DEC01 +XDEC01<0> ADDR_N_I<5> ADDR_N_I<4> CS04<0> CS00<1> VDD VSS / ++ RM_IHPSG13_1024x32_c2_1P_DEC01 +XL2<44> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<43> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<42> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<41> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<40> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<39> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<38> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<37> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<36> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<35> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<34> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<33> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<32> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<31> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<30> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<29> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<28> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<27> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<26> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<25> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<24> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<23> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<22> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<21> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<20> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<19> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<18> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<17> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<16> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<15> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<14> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<13> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<12> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<11> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<10> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<9> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<8> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<7> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<6> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<5> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<4> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<3> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<2> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<1> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI0 ADDR_N_I<7> VDD VSS / RSC_IHPSG13_TIEL +.ENDS +.SUBCKT RM_IHPSG13_1024x32_c2_1P_ROWREG7 ACLK_N_I ADDR_I<6> ADDR_I<5> ADDR_I<4> ADDR_I<3> ++ ADDR_I<2> ADDR_I<1> ADDR_I<0> ADDR_N_O<6> ADDR_N_O<5> ADDR_N_O<4> ++ ADDR_N_O<3> ADDR_N_O<2> ADDR_N_O<1> ADDR_N_O<0> BIST_ADDR_I<6> ++ BIST_ADDR_I<5> BIST_ADDR_I<4> BIST_ADDR_I<3> BIST_ADDR_I<2> BIST_ADDR_I<1> ++ BIST_ADDR_I<0> BIST_EN_I VDD VSS +XINV<6> q_int<6> qn_int<6> VDD VSS / RSC_IHPSG13_CINVX2 +XINV<5> q_int<5> qn_int<5> VDD VSS / RSC_IHPSG13_CINVX2 +XINV<4> q_int<4> qn_int<4> VDD VSS / RSC_IHPSG13_CINVX2 +XINV<3> q_int<3> qn_int<3> VDD VSS / RSC_IHPSG13_CINVX2 +XINV<2> q_int<2> qn_int<2> VDD VSS / RSC_IHPSG13_CINVX2 +XINV<1> q_int<1> qn_int<1> VDD VSS / RSC_IHPSG13_CINVX2 +XINV<0> q_int<0> qn_int<0> VDD VSS / RSC_IHPSG13_CINVX2 +XDRV<6> qn_int<6> ADDR_N_O<6> VDD VSS / RSC_IHPSG13_CINVX8 +XDRV<5> qn_int<5> ADDR_N_O<5> VDD VSS / RSC_IHPSG13_CINVX8 +XDRV<4> qn_int<4> ADDR_N_O<4> VDD VSS / RSC_IHPSG13_CINVX8 +XDRV<3> qn_int<3> ADDR_N_O<3> VDD VSS / RSC_IHPSG13_CINVX8 +XDRV<2> qn_int<2> ADDR_N_O<2> VDD VSS / RSC_IHPSG13_CINVX8 +XDRV<1> qn_int<1> ADDR_N_O<1> VDD VSS / RSC_IHPSG13_CINVX8 +XDRV<0> qn_int<0> ADDR_N_O<0> VDD VSS / RSC_IHPSG13_CINVX8 +XDFF<6> BIST_EN_I BIST_ADDR_I<6> ACLK_N_I ADDR_I<6> q_int<6> net2<0> VDD ++ VSS / RSC_IHPSG13_DFNQMX2IX1 +XDFF<5> BIST_EN_I BIST_ADDR_I<5> ACLK_N_I ADDR_I<5> q_int<5> net2<1> VDD ++ VSS / RSC_IHPSG13_DFNQMX2IX1 +XDFF<4> BIST_EN_I BIST_ADDR_I<4> ACLK_N_I ADDR_I<4> q_int<4> net2<2> VDD ++ VSS / RSC_IHPSG13_DFNQMX2IX1 +XDFF<3> BIST_EN_I BIST_ADDR_I<3> ACLK_N_I ADDR_I<3> q_int<3> net2<3> VDD ++ VSS / RSC_IHPSG13_DFNQMX2IX1 +XDFF<2> BIST_EN_I BIST_ADDR_I<2> ACLK_N_I ADDR_I<2> q_int<2> net2<4> VDD ++ VSS / RSC_IHPSG13_DFNQMX2IX1 +XDFF<1> BIST_EN_I BIST_ADDR_I<1> ACLK_N_I ADDR_I<1> q_int<1> net2<5> VDD ++ VSS / RSC_IHPSG13_DFNQMX2IX1 +XDFF<0> BIST_EN_I BIST_ADDR_I<0> ACLK_N_I ADDR_I<0> q_int<0> net2<6> VDD ++ VSS / RSC_IHPSG13_DFNQMX2IX1 +XI11<8> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI11<7> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI11<6> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI11<5> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI11<4> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI11<3> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI11<2> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI11<1> VDD VSS / RSC_IHPSG13_FILLCAP8 +.ENDS + +.SUBCKT RM_IHPSG13_1024x32_c2_1P_COLDRV13X8 ADDR_COL_I<1> ADDR_COL_I<0> ADDR_COL_O<1> ++ ADDR_COL_O<0> ADDR_DEC_I<7> ADDR_DEC_I<6> ADDR_DEC_I<5> ADDR_DEC_I<4> ++ ADDR_DEC_I<3> ADDR_DEC_I<2> ADDR_DEC_I<1> ADDR_DEC_I<0> ADDR_DEC_O<7> ++ ADDR_DEC_O<6> ADDR_DEC_O<5> ADDR_DEC_O<4> ADDR_DEC_O<3> ADDR_DEC_O<2> ++ ADDR_DEC_O<1> ADDR_DEC_O<0> DCLK_I DCLK_O RCLK_I RCLK_O WCLK_I WCLK_O ++ VDD VSS +XI0<1> VDD VSS / RSC_IHPSG13_FILLCAP4 +XI0<0> VDD VSS / RSC_IHPSG13_FILLCAP4 +XADDR_COL_DRV<1> ADDR_COL_I<1> ADDR_COL_O<1> VDD VSS / ++ RSC_IHPSG13_CBUFX8 +XADDR_COL_DRV<0> ADDR_COL_I<0> ADDR_COL_O<0> VDD VSS / ++ RSC_IHPSG13_CBUFX8 +XADDR_DEC_DRV<7> ADDR_DEC_I<7> ADDR_DEC_O<7> VDD VSS / ++ RSC_IHPSG13_CBUFX8 +XADDR_DEC_DRV<6> ADDR_DEC_I<6> ADDR_DEC_O<6> VDD VSS / ++ RSC_IHPSG13_CBUFX8 +XADDR_DEC_DRV<5> ADDR_DEC_I<5> ADDR_DEC_O<5> VDD VSS / ++ RSC_IHPSG13_CBUFX8 +XADDR_DEC_DRV<4> ADDR_DEC_I<4> ADDR_DEC_O<4> VDD VSS / ++ RSC_IHPSG13_CBUFX8 +XADDR_DEC_DRV<3> ADDR_DEC_I<3> ADDR_DEC_O<3> VDD VSS / ++ RSC_IHPSG13_CBUFX8 +XADDR_DEC_DRV<2> ADDR_DEC_I<2> ADDR_DEC_O<2> VDD VSS / ++ RSC_IHPSG13_CBUFX8 +XADDR_DEC_DRV<1> ADDR_DEC_I<1> ADDR_DEC_O<1> VDD VSS / ++ RSC_IHPSG13_CBUFX8 +XADDR_DEC_DRV<0> ADDR_DEC_I<0> ADDR_DEC_O<0> VDD VSS / ++ RSC_IHPSG13_CBUFX8 +XDCLK_DRV DCLK_I DCLK_O VDD VSS / RSC_IHPSG13_CBUFX8 +XRCLK_DRV RCLK_I RCLK_O VDD VSS / RSC_IHPSG13_CBUFX8 +XWCLK_DRV WCLK_I WCLK_O VDD VSS / RSC_IHPSG13_CBUFX8 +.ENDS +.SUBCKT RM_IHPSG13_1024x32_c2_1P_WLDRV16X8 A<15> A<14> A<13> A<12> A<11> A<10> A<9> A<8> ++ A<7> A<6> A<5> A<4> A<3> A<2> A<1> A<0> Z<15> Z<14> Z<13> Z<12> Z<11> Z<10> ++ Z<9> Z<8> Z<7> Z<6> Z<5> Z<4> Z<3> Z<2> Z<1> Z<0> VDD VSS +XBUF<15> A<15> Z<15> VDD VSS / RSC_IHPSG13_WLDRVX8 +XBUF<14> A<14> Z<14> VDD VSS / RSC_IHPSG13_WLDRVX8 +XBUF<13> A<13> Z<13> VDD VSS / RSC_IHPSG13_WLDRVX8 +XBUF<12> A<12> Z<12> VDD VSS / RSC_IHPSG13_WLDRVX8 +XBUF<11> A<11> Z<11> VDD VSS / RSC_IHPSG13_WLDRVX8 +XBUF<10> A<10> Z<10> VDD VSS / RSC_IHPSG13_WLDRVX8 +XBUF<9> A<9> Z<9> VDD VSS / RSC_IHPSG13_WLDRVX8 +XBUF<8> A<8> Z<8> VDD VSS / RSC_IHPSG13_WLDRVX8 +XBUF<7> A<7> Z<7> VDD VSS / RSC_IHPSG13_WLDRVX8 +XBUF<6> A<6> Z<6> VDD VSS / RSC_IHPSG13_WLDRVX8 +XBUF<5> A<5> Z<5> VDD VSS / RSC_IHPSG13_WLDRVX8 +XBUF<4> A<4> Z<4> VDD VSS / RSC_IHPSG13_WLDRVX8 +XBUF<3> A<3> Z<3> VDD VSS / RSC_IHPSG13_WLDRVX8 +XBUF<2> A<2> Z<2> VDD VSS / RSC_IHPSG13_WLDRVX8 +XBUF<1> A<1> Z<1> VDD VSS / RSC_IHPSG13_WLDRVX8 +XBUF<0> A<0> Z<0> VDD VSS / RSC_IHPSG13_WLDRVX8 +.ENDS + + + +.SUBCKT RM_IHPSG13_1024x32_c2_1P_ROWDEC6 ADDR_N_I<5> ADDR_N_I<4> ADDR_N_I<3> ADDR_N_I<2> ++ ADDR_N_I<1> ADDR_N_I<0> CS_I ECLK_I WL_O<63> WL_O<62> WL_O<61> WL_O<60> ++ WL_O<59> WL_O<58> WL_O<57> WL_O<56> WL_O<55> WL_O<54> WL_O<53> WL_O<52> ++ WL_O<51> WL_O<50> WL_O<49> WL_O<48> WL_O<47> WL_O<46> WL_O<45> WL_O<44> ++ WL_O<43> WL_O<42> WL_O<41> WL_O<40> WL_O<39> WL_O<38> WL_O<37> WL_O<36> ++ WL_O<35> WL_O<34> WL_O<33> WL_O<32> WL_O<31> WL_O<30> WL_O<29> WL_O<28> ++ WL_O<27> WL_O<26> WL_O<25> WL_O<24> WL_O<23> WL_O<22> WL_O<21> WL_O<20> ++ WL_O<19> WL_O<18> WL_O<17> WL_O<16> WL_O<15> WL_O<14> WL_O<13> WL_O<12> ++ WL_O<11> WL_O<10> WL_O<9> WL_O<8> WL_O<7> WL_O<6> WL_O<5> WL_O<4> WL_O<3> ++ WL_O<2> WL_O<1> WL_O<0> VDD VSS +XDEC11 ADDR_N_I<5> ADDR_N_I<4> CS_I CS00<3> VDD VSS / ++ RM_IHPSG13_1024x32_c2_1P_DEC03 +XDEC00 ADDR_N_I<5> ADDR_N_I<4> CS_I CS00<0> VDD VSS / ++ RM_IHPSG13_1024x32_c2_1P_DEC00 +XDEC01 ADDR_N_I<5> ADDR_N_I<4> CS_I CS00<1> VDD VSS / ++ RM_IHPSG13_1024x32_c2_1P_DEC01 +XDEC10 ADDR_N_I<5> ADDR_N_I<4> CS_I CS00<2> VDD VSS / ++ RM_IHPSG13_1024x32_c2_1P_DEC02 +XSEL<3> ADDR_N_I<3> ADDR_N_I<2> ADDR_N_I<1> ADDR_N_I<0> CS00<3> ECLK_H<3> ++ ECLK_H<4> ECLK_B<3> ECLK_B<4> WL_O<63> WL_O<62> WL_O<61> WL_O<60> WL_O<59> ++ WL_O<58> WL_O<57> WL_O<56> WL_O<55> WL_O<54> WL_O<53> WL_O<52> WL_O<51> ++ WL_O<50> WL_O<49> WL_O<48> VDD VSS / RM_IHPSG13_1024x32_c2_1P_DEC04 +XSEL<2> ADDR_N_I<3> ADDR_N_I<2> ADDR_N_I<1> ADDR_N_I<0> CS00<2> ECLK_H<2> ++ ECLK_H<3> ECLK_B<2> ECLK_B<3> WL_O<47> WL_O<46> WL_O<45> WL_O<44> WL_O<43> ++ WL_O<42> WL_O<41> WL_O<40> WL_O<39> WL_O<38> WL_O<37> WL_O<36> WL_O<35> ++ WL_O<34> WL_O<33> WL_O<32> VDD VSS / RM_IHPSG13_1024x32_c2_1P_DEC04 +XSEL<1> ADDR_N_I<3> ADDR_N_I<2> ADDR_N_I<1> ADDR_N_I<0> CS00<1> ECLK_H<1> ++ ECLK_H<2> ECLK_B<1> ECLK_B<2> WL_O<31> WL_O<30> WL_O<29> WL_O<28> WL_O<27> ++ WL_O<26> WL_O<25> WL_O<24> WL_O<23> WL_O<22> WL_O<21> WL_O<20> WL_O<19> ++ WL_O<18> WL_O<17> WL_O<16> VDD VSS / RM_IHPSG13_1024x32_c2_1P_DEC04 +XSEL<0> ADDR_N_I<3> ADDR_N_I<2> ADDR_N_I<1> ADDR_N_I<0> CS00<0> ECLK_I ++ ECLK_H<1> ECLK_B<0> ECLK_B<1> WL_O<15> WL_O<14> WL_O<13> WL_O<12> WL_O<11> ++ WL_O<10> WL_O<9> WL_O<8> WL_O<7> WL_O<6> WL_O<5> WL_O<4> WL_O<3> WL_O<2> ++ WL_O<1> WL_O<0> VDD VSS / RM_IHPSG13_1024x32_c2_1P_DEC04 +XL2<24> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<23> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<22> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<21> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<20> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<19> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<18> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<17> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<16> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<15> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<14> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<13> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<12> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<11> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<10> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<9> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<8> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<7> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<6> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<5> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<4> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<3> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<2> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<1> VDD VSS / RSC_IHPSG13_FILLCAP8 +.ENDS +.SUBCKT RM_IHPSG13_1024x32_c2_1P_ROWREG6 ACLK_N_I ADDR_I<5> ADDR_I<4> ADDR_I<3> ADDR_I<2> ++ ADDR_I<1> ADDR_I<0> ADDR_N_O<5> ADDR_N_O<4> ADDR_N_O<3> ADDR_N_O<2> ++ ADDR_N_O<1> ADDR_N_O<0> BIST_ADDR_I<5> BIST_ADDR_I<4> BIST_ADDR_I<3> ++ BIST_ADDR_I<2> BIST_ADDR_I<1> BIST_ADDR_I<0> BIST_EN_I VDD VSS +XINV<5> q_int<5> qn_int<5> VDD VSS / RSC_IHPSG13_CINVX2 +XINV<4> q_int<4> qn_int<4> VDD VSS / RSC_IHPSG13_CINVX2 +XINV<3> q_int<3> qn_int<3> VDD VSS / RSC_IHPSG13_CINVX2 +XINV<2> q_int<2> qn_int<2> VDD VSS / RSC_IHPSG13_CINVX2 +XINV<1> q_int<1> qn_int<1> VDD VSS / RSC_IHPSG13_CINVX2 +XINV<0> q_int<0> qn_int<0> VDD VSS / RSC_IHPSG13_CINVX2 +XDRV<5> qn_int<5> ADDR_N_O<5> VDD VSS / RSC_IHPSG13_CINVX8 +XDRV<4> qn_int<4> ADDR_N_O<4> VDD VSS / RSC_IHPSG13_CINVX8 +XDRV<3> qn_int<3> ADDR_N_O<3> VDD VSS / RSC_IHPSG13_CINVX8 +XDRV<2> qn_int<2> ADDR_N_O<2> VDD VSS / RSC_IHPSG13_CINVX8 +XDRV<1> qn_int<1> ADDR_N_O<1> VDD VSS / RSC_IHPSG13_CINVX8 +XDRV<0> qn_int<0> ADDR_N_O<0> VDD VSS / RSC_IHPSG13_CINVX8 +XDFF<5> BIST_EN_I BIST_ADDR_I<5> ACLK_N_I ADDR_I<5> q_int<5> net2<0> VDD ++ VSS / RSC_IHPSG13_DFNQMX2IX1 +XDFF<4> BIST_EN_I BIST_ADDR_I<4> ACLK_N_I ADDR_I<4> q_int<4> net2<1> VDD ++ VSS / RSC_IHPSG13_DFNQMX2IX1 +XDFF<3> BIST_EN_I BIST_ADDR_I<3> ACLK_N_I ADDR_I<3> q_int<3> net2<2> VDD ++ VSS / RSC_IHPSG13_DFNQMX2IX1 +XDFF<2> BIST_EN_I BIST_ADDR_I<2> ACLK_N_I ADDR_I<2> q_int<2> net2<3> VDD ++ VSS / RSC_IHPSG13_DFNQMX2IX1 +XDFF<1> BIST_EN_I BIST_ADDR_I<1> ACLK_N_I ADDR_I<1> q_int<1> net2<4> VDD ++ VSS / RSC_IHPSG13_DFNQMX2IX1 +XDFF<0> BIST_EN_I BIST_ADDR_I<0> ACLK_N_I ADDR_I<0> q_int<0> net2<5> VDD ++ VSS / RSC_IHPSG13_DFNQMX2IX1 +XI11<12> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI11<11> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI11<10> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI11<9> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI11<8> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI11<7> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI11<6> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI11<5> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI11<4> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI11<3> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI11<2> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI11<1> VDD VSS / RSC_IHPSG13_FILLCAP8 +.ENDS + + +.SUBCKT RM_IHPSG13_1024x32_c2_1P_COLUMN_pcell_0 A_BLC_BOT<1> A_BLC_BOT<0> A_BLC_TOP<1> A_BLC_TOP<0> A_BLT_BOT<1> A_BLT_BOT<0> A_BLT_TOP<1> A_BLT_TOP<0> A_LWL<255> A_LWL<254> A_LWL<253> A_LWL<252> A_LWL<251> A_LWL<250> A_LWL<249> A_LWL<248> A_LWL<247> A_LWL<246> A_LWL<245> A_LWL<244> A_LWL<243> A_LWL<242> A_LWL<241> A_LWL<240> A_LWL<239> A_LWL<238> A_LWL<237> A_LWL<236> A_LWL<235> A_LWL<234> A_LWL<233> A_LWL<232> A_LWL<231> A_LWL<230> A_LWL<229> A_LWL<228> A_LWL<227> A_LWL<226> A_LWL<225> A_LWL<224> A_LWL<223> A_LWL<222> A_LWL<221> A_LWL<220> A_LWL<219> A_LWL<218> A_LWL<217> A_LWL<216> A_LWL<215> A_LWL<214> A_LWL<213> A_LWL<212> A_LWL<211> A_LWL<210> A_LWL<209> A_LWL<208> A_LWL<207> A_LWL<206> A_LWL<205> A_LWL<204> A_LWL<203> A_LWL<202> A_LWL<201> A_LWL<200> A_LWL<199> A_LWL<198> A_LWL<197> A_LWL<196> A_LWL<195> A_LWL<194> A_LWL<193> A_LWL<192> A_LWL<191> A_LWL<190> A_LWL<189> A_LWL<188> A_LWL<187> A_LWL<186> A_LWL<185> A_LWL<184> A_LWL<183> A_LWL<182> A_LWL<181> A_LWL<180> A_LWL<179> A_LWL<178> A_LWL<177> A_LWL<176> A_LWL<175> A_LWL<174> A_LWL<173> A_LWL<172> A_LWL<171> A_LWL<170> A_LWL<169> A_LWL<168> A_LWL<167> A_LWL<166> A_LWL<165> A_LWL<164> A_LWL<163> A_LWL<162> A_LWL<161> A_LWL<160> A_LWL<159> A_LWL<158> A_LWL<157> A_LWL<156> A_LWL<155> A_LWL<154> A_LWL<153> A_LWL<152> A_LWL<151> A_LWL<150> A_LWL<149> A_LWL<148> A_LWL<147> A_LWL<146> A_LWL<145> A_LWL<144> A_LWL<143> A_LWL<142> A_LWL<141> A_LWL<140> A_LWL<139> A_LWL<138> A_LWL<137> A_LWL<136> A_LWL<135> A_LWL<134> A_LWL<133> A_LWL<132> A_LWL<131> A_LWL<130> A_LWL<129> A_LWL<128> A_LWL<127> A_LWL<126> A_LWL<125> A_LWL<124> A_LWL<123> A_LWL<122> A_LWL<121> A_LWL<120> A_LWL<119> A_LWL<118> A_LWL<117> A_LWL<116> A_LWL<115> A_LWL<114> A_LWL<113> A_LWL<112> A_LWL<111> A_LWL<110> A_LWL<109> A_LWL<108> A_LWL<107> A_LWL<106> A_LWL<105> A_LWL<104> A_LWL<103> A_LWL<102> A_LWL<101> A_LWL<100> A_LWL<99> A_LWL<98> A_LWL<97> A_LWL<96> A_LWL<95> A_LWL<94> A_LWL<93> A_LWL<92> A_LWL<91> A_LWL<90> A_LWL<89> A_LWL<88> A_LWL<87> A_LWL<86> A_LWL<85> A_LWL<84> A_LWL<83> A_LWL<82> A_LWL<81> A_LWL<80> A_LWL<79> A_LWL<78> A_LWL<77> A_LWL<76> A_LWL<75> A_LWL<74> A_LWL<73> A_LWL<72> A_LWL<71> A_LWL<70> A_LWL<69> A_LWL<68> A_LWL<67> A_LWL<66> A_LWL<65> A_LWL<64> A_LWL<63> A_LWL<62> A_LWL<61> A_LWL<60> A_LWL<59> A_LWL<58> A_LWL<57> A_LWL<56> A_LWL<55> A_LWL<54> A_LWL<53> A_LWL<52> A_LWL<51> A_LWL<50> A_LWL<49> A_LWL<48> A_LWL<47> A_LWL<46> A_LWL<45> A_LWL<44> A_LWL<43> A_LWL<42> A_LWL<41> A_LWL<40> A_LWL<39> A_LWL<38> A_LWL<37> A_LWL<36> A_LWL<35> A_LWL<34> A_LWL<33> A_LWL<32> A_LWL<31> A_LWL<30> A_LWL<29> A_LWL<28> A_LWL<27> A_LWL<26> A_LWL<25> A_LWL<24> A_LWL<23> A_LWL<22> A_LWL<21> A_LWL<20> A_LWL<19> A_LWL<18> A_LWL<17> A_LWL<16> A_LWL<15> A_LWL<14> A_LWL<13> A_LWL<12> A_LWL<11> A_LWL<10> A_LWL<9> A_LWL<8> A_LWL<7> A_LWL<6> A_LWL<5> A_LWL<4> A_LWL<3> A_LWL<2> A_LWL<1> A_LWL<0> A_RWL<255> A_RWL<254> A_RWL<253> A_RWL<252> A_RWL<251> A_RWL<250> A_RWL<249> A_RWL<248> A_RWL<247> A_RWL<246> A_RWL<245> A_RWL<244> A_RWL<243> A_RWL<242> A_RWL<241> A_RWL<240> A_RWL<239> A_RWL<238> A_RWL<237> A_RWL<236> A_RWL<235> A_RWL<234> A_RWL<233> A_RWL<232> A_RWL<231> A_RWL<230> A_RWL<229> A_RWL<228> A_RWL<227> A_RWL<226> A_RWL<225> A_RWL<224> A_RWL<223> A_RWL<222> A_RWL<221> A_RWL<220> A_RWL<219> A_RWL<218> A_RWL<217> A_RWL<216> A_RWL<215> A_RWL<214> A_RWL<213> A_RWL<212> A_RWL<211> A_RWL<210> A_RWL<209> A_RWL<208> A_RWL<207> A_RWL<206> A_RWL<205> A_RWL<204> A_RWL<203> A_RWL<202> A_RWL<201> A_RWL<200> A_RWL<199> A_RWL<198> A_RWL<197> A_RWL<196> A_RWL<195> A_RWL<194> A_RWL<193> A_RWL<192> A_RWL<191> A_RWL<190> A_RWL<189> A_RWL<188> A_RWL<187> A_RWL<186> A_RWL<185> A_RWL<184> A_RWL<183> A_RWL<182> A_RWL<181> A_RWL<180> A_RWL<179> A_RWL<178> A_RWL<177> A_RWL<176> A_RWL<175> A_RWL<174> A_RWL<173> A_RWL<172> A_RWL<171> A_RWL<170> A_RWL<169> A_RWL<168> A_RWL<167> A_RWL<166> A_RWL<165> A_RWL<164> A_RWL<163> A_RWL<162> A_RWL<161> A_RWL<160> A_RWL<159> A_RWL<158> A_RWL<157> A_RWL<156> A_RWL<155> A_RWL<154> A_RWL<153> A_RWL<152> A_RWL<151> A_RWL<150> A_RWL<149> A_RWL<148> A_RWL<147> A_RWL<146> A_RWL<145> A_RWL<144> A_RWL<143> A_RWL<142> A_RWL<141> A_RWL<140> A_RWL<139> A_RWL<138> A_RWL<137> A_RWL<136> A_RWL<135> A_RWL<134> A_RWL<133> A_RWL<132> A_RWL<131> A_RWL<130> A_RWL<129> A_RWL<128> A_RWL<127> A_RWL<126> A_RWL<125> A_RWL<124> A_RWL<123> A_RWL<122> A_RWL<121> A_RWL<120> A_RWL<119> A_RWL<118> A_RWL<117> A_RWL<116> A_RWL<115> A_RWL<114> A_RWL<113> A_RWL<112> A_RWL<111> A_RWL<110> A_RWL<109> A_RWL<108> A_RWL<107> A_RWL<106> A_RWL<105> A_RWL<104> A_RWL<103> A_RWL<102> A_RWL<101> A_RWL<100> A_RWL<99> A_RWL<98> A_RWL<97> A_RWL<96> A_RWL<95> A_RWL<94> A_RWL<93> A_RWL<92> A_RWL<91> A_RWL<90> A_RWL<89> A_RWL<88> A_RWL<87> A_RWL<86> A_RWL<85> A_RWL<84> A_RWL<83> A_RWL<82> A_RWL<81> A_RWL<80> A_RWL<79> A_RWL<78> A_RWL<77> A_RWL<76> A_RWL<75> A_RWL<74> A_RWL<73> A_RWL<72> A_RWL<71> A_RWL<70> A_RWL<69> A_RWL<68> A_RWL<67> A_RWL<66> A_RWL<65> A_RWL<64> A_RWL<63> A_RWL<62> A_RWL<61> A_RWL<60> A_RWL<59> A_RWL<58> A_RWL<57> A_RWL<56> A_RWL<55> A_RWL<54> A_RWL<53> A_RWL<52> A_RWL<51> A_RWL<50> A_RWL<49> A_RWL<48> A_RWL<47> A_RWL<46> A_RWL<45> A_RWL<44> A_RWL<43> A_RWL<42> A_RWL<41> A_RWL<40> A_RWL<39> A_RWL<38> A_RWL<37> A_RWL<36> A_RWL<35> A_RWL<34> A_RWL<33> A_RWL<32> A_RWL<31> A_RWL<30> A_RWL<29> A_RWL<28> A_RWL<27> A_RWL<26> A_RWL<25> A_RWL<24> A_RWL<23> A_RWL<22> A_RWL<21> A_RWL<20> A_RWL<19> A_RWL<18> A_RWL<17> A_RWL<16> A_RWL<15> A_RWL<14> A_RWL<13> A_RWL<12> A_RWL<11> A_RWL<10> A_RWL<9> A_RWL<8> A_RWL<7> A_RWL<6> A_RWL<5> A_RWL<4> A_RWL<3> A_RWL<2> A_RWL<1> A_RWL<0> VDD_CORE VSS +XRAM<16> A_BLC<29> A_BLC<28> A_BLC_TOP<1> A_BLC_TOP<0> A_BLT<29> A_BLT<28> A_BLT_TOP<1> A_BLT_TOP<0> A_LWL<255> A_LWL<254> A_LWL<253> A_LWL<252> A_LWL<251> A_LWL<250> A_LWL<249> A_LWL<248> A_LWL<247> A_LWL<246> A_LWL<245> A_LWL<244> A_LWL<243> A_LWL<242> A_LWL<241> A_LWL<240> A_RWL<255> A_RWL<254> A_RWL<253> A_RWL<252> A_RWL<251> A_RWL<250> A_RWL<249> A_RWL<248> A_RWL<247> A_RWL<246> A_RWL<245> A_RWL<244> A_RWL<243> A_RWL<242> A_RWL<241> A_RWL<240> VDD_CORE VSS / RM_IHPSG13_1024x32_c2_1P_BITKIT_16x2_SRAM +XRAM<15> A_BLC<27> A_BLC<26> A_BLC<29> A_BLC<28> A_BLT<27> A_BLT<26> A_BLT<29> A_BLT<28> A_LWL<239> A_LWL<238> A_LWL<237> A_LWL<236> A_LWL<235> A_LWL<234> A_LWL<233> A_LWL<232> A_LWL<231> A_LWL<230> A_LWL<229> A_LWL<228> A_LWL<227> A_LWL<226> A_LWL<225> A_LWL<224> A_RWL<239> A_RWL<238> A_RWL<237> A_RWL<236> A_RWL<235> A_RWL<234> A_RWL<233> A_RWL<232> A_RWL<231> A_RWL<230> A_RWL<229> A_RWL<228> A_RWL<227> A_RWL<226> A_RWL<225> A_RWL<224> VDD_CORE VSS / RM_IHPSG13_1024x32_c2_1P_BITKIT_16x2_SRAM +XRAM<14> A_BLC<25> A_BLC<24> A_BLC<27> A_BLC<26> A_BLT<25> A_BLT<24> A_BLT<27> A_BLT<26> A_LWL<223> A_LWL<222> A_LWL<221> A_LWL<220> A_LWL<219> A_LWL<218> A_LWL<217> A_LWL<216> A_LWL<215> A_LWL<214> A_LWL<213> A_LWL<212> A_LWL<211> A_LWL<210> A_LWL<209> A_LWL<208> A_RWL<223> A_RWL<222> A_RWL<221> A_RWL<220> A_RWL<219> A_RWL<218> A_RWL<217> A_RWL<216> A_RWL<215> A_RWL<214> A_RWL<213> A_RWL<212> A_RWL<211> A_RWL<210> A_RWL<209> A_RWL<208> VDD_CORE VSS / RM_IHPSG13_1024x32_c2_1P_BITKIT_16x2_SRAM +XRAM<13> A_BLC<23> A_BLC<22> A_BLC<25> A_BLC<24> A_BLT<23> A_BLT<22> A_BLT<25> A_BLT<24> A_LWL<207> A_LWL<206> A_LWL<205> A_LWL<204> A_LWL<203> A_LWL<202> A_LWL<201> A_LWL<200> A_LWL<199> A_LWL<198> A_LWL<197> A_LWL<196> A_LWL<195> A_LWL<194> A_LWL<193> A_LWL<192> A_RWL<207> A_RWL<206> A_RWL<205> A_RWL<204> A_RWL<203> A_RWL<202> A_RWL<201> A_RWL<200> A_RWL<199> A_RWL<198> A_RWL<197> A_RWL<196> A_RWL<195> A_RWL<194> A_RWL<193> A_RWL<192> VDD_CORE VSS / RM_IHPSG13_1024x32_c2_1P_BITKIT_16x2_SRAM +XRAM<12> A_BLC<21> A_BLC<20> A_BLC<23> A_BLC<22> A_BLT<21> A_BLT<20> A_BLT<23> A_BLT<22> A_LWL<191> A_LWL<190> A_LWL<189> A_LWL<188> A_LWL<187> A_LWL<186> A_LWL<185> A_LWL<184> A_LWL<183> A_LWL<182> A_LWL<181> A_LWL<180> A_LWL<179> A_LWL<178> A_LWL<177> A_LWL<176> A_RWL<191> A_RWL<190> A_RWL<189> A_RWL<188> A_RWL<187> A_RWL<186> A_RWL<185> A_RWL<184> A_RWL<183> A_RWL<182> A_RWL<181> A_RWL<180> A_RWL<179> A_RWL<178> A_RWL<177> A_RWL<176> VDD_CORE VSS / RM_IHPSG13_1024x32_c2_1P_BITKIT_16x2_SRAM +XRAM<11> A_BLC<19> A_BLC<18> A_BLC<21> A_BLC<20> A_BLT<19> A_BLT<18> A_BLT<21> A_BLT<20> A_LWL<175> A_LWL<174> A_LWL<173> A_LWL<172> A_LWL<171> A_LWL<170> A_LWL<169> A_LWL<168> A_LWL<167> A_LWL<166> A_LWL<165> A_LWL<164> A_LWL<163> A_LWL<162> A_LWL<161> A_LWL<160> A_RWL<175> A_RWL<174> A_RWL<173> A_RWL<172> A_RWL<171> A_RWL<170> A_RWL<169> A_RWL<168> A_RWL<167> A_RWL<166> A_RWL<165> A_RWL<164> A_RWL<163> A_RWL<162> A_RWL<161> A_RWL<160> VDD_CORE VSS / RM_IHPSG13_1024x32_c2_1P_BITKIT_16x2_SRAM +XRAM<10> A_BLC<17> A_BLC<16> A_BLC<19> A_BLC<18> A_BLT<17> A_BLT<16> A_BLT<19> A_BLT<18> A_LWL<159> A_LWL<158> A_LWL<157> A_LWL<156> A_LWL<155> A_LWL<154> A_LWL<153> A_LWL<152> A_LWL<151> A_LWL<150> A_LWL<149> A_LWL<148> A_LWL<147> A_LWL<146> A_LWL<145> A_LWL<144> A_RWL<159> A_RWL<158> A_RWL<157> A_RWL<156> A_RWL<155> A_RWL<154> A_RWL<153> A_RWL<152> A_RWL<151> A_RWL<150> A_RWL<149> A_RWL<148> A_RWL<147> A_RWL<146> A_RWL<145> A_RWL<144> VDD_CORE VSS / RM_IHPSG13_1024x32_c2_1P_BITKIT_16x2_SRAM +XRAM<9> A_BLC<15> A_BLC<14> A_BLC<17> A_BLC<16> A_BLT<15> A_BLT<14> A_BLT<17> A_BLT<16> A_LWL<143> A_LWL<142> A_LWL<141> A_LWL<140> A_LWL<139> A_LWL<138> A_LWL<137> A_LWL<136> A_LWL<135> A_LWL<134> A_LWL<133> A_LWL<132> A_LWL<131> A_LWL<130> A_LWL<129> A_LWL<128> A_RWL<143> A_RWL<142> A_RWL<141> A_RWL<140> A_RWL<139> A_RWL<138> A_RWL<137> A_RWL<136> A_RWL<135> A_RWL<134> A_RWL<133> A_RWL<132> A_RWL<131> A_RWL<130> A_RWL<129> A_RWL<128> VDD_CORE VSS / RM_IHPSG13_1024x32_c2_1P_BITKIT_16x2_SRAM +XRAM<8> A_BLC<13> A_BLC<12> A_BLC<15> A_BLC<14> A_BLT<13> A_BLT<12> A_BLT<15> A_BLT<14> A_LWL<127> A_LWL<126> A_LWL<125> A_LWL<124> A_LWL<123> A_LWL<122> A_LWL<121> A_LWL<120> A_LWL<119> A_LWL<118> A_LWL<117> A_LWL<116> A_LWL<115> A_LWL<114> A_LWL<113> A_LWL<112> A_RWL<127> A_RWL<126> A_RWL<125> A_RWL<124> A_RWL<123> A_RWL<122> A_RWL<121> A_RWL<120> A_RWL<119> A_RWL<118> A_RWL<117> A_RWL<116> A_RWL<115> A_RWL<114> A_RWL<113> A_RWL<112> VDD_CORE VSS / RM_IHPSG13_1024x32_c2_1P_BITKIT_16x2_SRAM +XRAM<7> A_BLC<11> A_BLC<10> A_BLC<13> A_BLC<12> A_BLT<11> A_BLT<10> A_BLT<13> A_BLT<12> A_LWL<111> A_LWL<110> A_LWL<109> A_LWL<108> A_LWL<107> A_LWL<106> A_LWL<105> A_LWL<104> A_LWL<103> A_LWL<102> A_LWL<101> A_LWL<100> A_LWL<99> A_LWL<98> A_LWL<97> A_LWL<96> A_RWL<111> A_RWL<110> A_RWL<109> A_RWL<108> A_RWL<107> A_RWL<106> A_RWL<105> A_RWL<104> A_RWL<103> A_RWL<102> A_RWL<101> A_RWL<100> A_RWL<99> A_RWL<98> A_RWL<97> A_RWL<96> VDD_CORE VSS / RM_IHPSG13_1024x32_c2_1P_BITKIT_16x2_SRAM +XRAM<6> A_BLC<9> A_BLC<8> A_BLC<11> A_BLC<10> A_BLT<9> A_BLT<8> A_BLT<11> A_BLT<10> A_LWL<95> A_LWL<94> A_LWL<93> A_LWL<92> A_LWL<91> A_LWL<90> A_LWL<89> A_LWL<88> A_LWL<87> A_LWL<86> A_LWL<85> A_LWL<84> A_LWL<83> A_LWL<82> A_LWL<81> A_LWL<80> A_RWL<95> A_RWL<94> A_RWL<93> A_RWL<92> A_RWL<91> A_RWL<90> A_RWL<89> A_RWL<88> A_RWL<87> A_RWL<86> A_RWL<85> A_RWL<84> A_RWL<83> A_RWL<82> A_RWL<81> A_RWL<80> VDD_CORE VSS / RM_IHPSG13_1024x32_c2_1P_BITKIT_16x2_SRAM +XRAM<5> A_BLC<7> A_BLC<6> A_BLC<9> A_BLC<8> A_BLT<7> A_BLT<6> A_BLT<9> A_BLT<8> A_LWL<79> A_LWL<78> A_LWL<77> A_LWL<76> A_LWL<75> A_LWL<74> A_LWL<73> A_LWL<72> A_LWL<71> A_LWL<70> A_LWL<69> A_LWL<68> A_LWL<67> A_LWL<66> A_LWL<65> A_LWL<64> A_RWL<79> A_RWL<78> A_RWL<77> A_RWL<76> A_RWL<75> A_RWL<74> A_RWL<73> A_RWL<72> A_RWL<71> A_RWL<70> A_RWL<69> A_RWL<68> A_RWL<67> A_RWL<66> A_RWL<65> A_RWL<64> VDD_CORE VSS / RM_IHPSG13_1024x32_c2_1P_BITKIT_16x2_SRAM +XRAM<4> A_BLC<5> A_BLC<4> A_BLC<7> A_BLC<6> A_BLT<5> A_BLT<4> A_BLT<7> A_BLT<6> A_LWL<63> A_LWL<62> A_LWL<61> A_LWL<60> A_LWL<59> A_LWL<58> A_LWL<57> A_LWL<56> A_LWL<55> A_LWL<54> A_LWL<53> A_LWL<52> A_LWL<51> A_LWL<50> A_LWL<49> A_LWL<48> A_RWL<63> A_RWL<62> A_RWL<61> A_RWL<60> A_RWL<59> A_RWL<58> A_RWL<57> A_RWL<56> A_RWL<55> A_RWL<54> A_RWL<53> A_RWL<52> A_RWL<51> A_RWL<50> A_RWL<49> A_RWL<48> VDD_CORE VSS / RM_IHPSG13_1024x32_c2_1P_BITKIT_16x2_SRAM +XRAM<3> A_BLC<3> A_BLC<2> A_BLC<5> A_BLC<4> A_BLT<3> A_BLT<2> A_BLT<5> A_BLT<4> A_LWL<47> A_LWL<46> A_LWL<45> A_LWL<44> A_LWL<43> A_LWL<42> A_LWL<41> A_LWL<40> A_LWL<39> A_LWL<38> A_LWL<37> A_LWL<36> A_LWL<35> A_LWL<34> A_LWL<33> A_LWL<32> A_RWL<47> A_RWL<46> A_RWL<45> A_RWL<44> A_RWL<43> A_RWL<42> A_RWL<41> A_RWL<40> A_RWL<39> A_RWL<38> A_RWL<37> A_RWL<36> A_RWL<35> A_RWL<34> A_RWL<33> A_RWL<32> VDD_CORE VSS / RM_IHPSG13_1024x32_c2_1P_BITKIT_16x2_SRAM +XRAM<2> A_BLC<1> A_BLC<0> A_BLC<3> A_BLC<2> A_BLT<1> A_BLT<0> A_BLT<3> A_BLT<2> A_LWL<31> A_LWL<30> A_LWL<29> A_LWL<28> A_LWL<27> A_LWL<26> A_LWL<25> A_LWL<24> A_LWL<23> A_LWL<22> A_LWL<21> A_LWL<20> A_LWL<19> A_LWL<18> A_LWL<17> A_LWL<16> A_RWL<31> A_RWL<30> A_RWL<29> A_RWL<28> A_RWL<27> A_RWL<26> A_RWL<25> A_RWL<24> A_RWL<23> A_RWL<22> A_RWL<21> A_RWL<20> A_RWL<19> A_RWL<18> A_RWL<17> A_RWL<16> VDD_CORE VSS / RM_IHPSG13_1024x32_c2_1P_BITKIT_16x2_SRAM +XRAM<1> A_BLC_BOT<1> A_BLC_BOT<0> A_BLC<1> A_BLC<0> A_BLT_BOT<1> A_BLT_BOT<0> A_BLT<1> A_BLT<0> A_LWL<15> A_LWL<14> A_LWL<13> A_LWL<12> A_LWL<11> A_LWL<10> A_LWL<9> A_LWL<8> A_LWL<7> A_LWL<6> A_LWL<5> A_LWL<4> A_LWL<3> A_LWL<2> A_LWL<1> A_LWL<0> A_RWL<15> A_RWL<14> A_RWL<13> A_RWL<12> A_RWL<11> A_RWL<10> A_RWL<9> A_RWL<8> A_RWL<7> A_RWL<6> A_RWL<5> A_RWL<4> A_RWL<3> A_RWL<2> A_RWL<1> A_RWL<0> VDD_CORE VSS / RM_IHPSG13_1024x32_c2_1P_BITKIT_16x2_SRAM +XEDGE<1> A_BLC_TOP<1> A_BLC_TOP<0> A_BLT_TOP<1> A_BLT_TOP<0> VDD_CORE VSS / RM_IHPSG13_1024x32_c2_1P_BITKIT_16x2_EDGE_TB +XEDGE<0> A_BLC_BOT<1> A_BLC_BOT<0> A_BLT_BOT<1> A_BLT_BOT<0> VDD_CORE VSS / RM_IHPSG13_1024x32_c2_1P_BITKIT_16x2_EDGE_TB +.ENDS + + + + +.SUBCKT RM_IHPSG13_1024x32_c2_1P_MATRIX_pcell_1 A_BLC<63> A_BLC<62> A_BLC<61> A_BLC<60> A_BLC<59> A_BLC<58> A_BLC<57> A_BLC<56> A_BLC<55> A_BLC<54> A_BLC<53> A_BLC<52> A_BLC<51> A_BLC<50> A_BLC<49> A_BLC<48> A_BLC<47> A_BLC<46> A_BLC<45> A_BLC<44> A_BLC<43> A_BLC<42> A_BLC<41> A_BLC<40> A_BLC<39> A_BLC<38> A_BLC<37> A_BLC<36> A_BLC<35> A_BLC<34> A_BLC<33> A_BLC<32> A_BLC<31> A_BLC<30> A_BLC<29> A_BLC<28> A_BLC<27> A_BLC<26> A_BLC<25> A_BLC<24> A_BLC<23> A_BLC<22> A_BLC<21> A_BLC<20> A_BLC<19> A_BLC<18> A_BLC<17> A_BLC<16> A_BLC<15> A_BLC<14> A_BLC<13> A_BLC<12> A_BLC<11> A_BLC<10> A_BLC<9> A_BLC<8> A_BLC<7> A_BLC<6> A_BLC<5> A_BLC<4> A_BLC<3> A_BLC<2> A_BLC<1> A_BLC<0> A_BLT<63> A_BLT<62> A_BLT<61> A_BLT<60> A_BLT<59> A_BLT<58> A_BLT<57> A_BLT<56> A_BLT<55> A_BLT<54> A_BLT<53> A_BLT<52> A_BLT<51> A_BLT<50> A_BLT<49> A_BLT<48> A_BLT<47> A_BLT<46> A_BLT<45> A_BLT<44> A_BLT<43> A_BLT<42> A_BLT<41> A_BLT<40> A_BLT<39> A_BLT<38> A_BLT<37> A_BLT<36> A_BLT<35> A_BLT<34> A_BLT<33> A_BLT<32> A_BLT<31> A_BLT<30> A_BLT<29> A_BLT<28> A_BLT<27> A_BLT<26> A_BLT<25> A_BLT<24> A_BLT<23> A_BLT<22> A_BLT<21> A_BLT<20> A_BLT<19> A_BLT<18> A_BLT<17> A_BLT<16> A_BLT<15> A_BLT<14> A_BLT<13> A_BLT<12> A_BLT<11> A_BLT<10> A_BLT<9> A_BLT<8> A_BLT<7> A_BLT<6> A_BLT<5> A_BLT<4> A_BLT<3> A_BLT<2> A_BLT<1> A_BLT<0> A_WL<255> A_WL<254> A_WL<253> A_WL<252> A_WL<251> A_WL<250> A_WL<249> A_WL<248> A_WL<247> A_WL<246> A_WL<245> A_WL<244> A_WL<243> A_WL<242> A_WL<241> A_WL<240> A_WL<239> A_WL<238> A_WL<237> A_WL<236> A_WL<235> A_WL<234> A_WL<233> A_WL<232> A_WL<231> A_WL<230> A_WL<229> A_WL<228> A_WL<227> A_WL<226> A_WL<225> A_WL<224> A_WL<223> A_WL<222> A_WL<221> A_WL<220> A_WL<219> A_WL<218> A_WL<217> A_WL<216> A_WL<215> A_WL<214> A_WL<213> A_WL<212> A_WL<211> A_WL<210> A_WL<209> A_WL<208> A_WL<207> A_WL<206> A_WL<205> A_WL<204> A_WL<203> A_WL<202> A_WL<201> A_WL<200> A_WL<199> A_WL<198> A_WL<197> A_WL<196> A_WL<195> A_WL<194> A_WL<193> A_WL<192> A_WL<191> A_WL<190> A_WL<189> A_WL<188> A_WL<187> A_WL<186> A_WL<185> A_WL<184> A_WL<183> A_WL<182> A_WL<181> A_WL<180> A_WL<179> A_WL<178> A_WL<177> A_WL<176> A_WL<175> A_WL<174> A_WL<173> A_WL<172> A_WL<171> A_WL<170> A_WL<169> A_WL<168> A_WL<167> A_WL<166> A_WL<165> A_WL<164> A_WL<163> A_WL<162> A_WL<161> A_WL<160> A_WL<159> A_WL<158> A_WL<157> A_WL<156> A_WL<155> A_WL<154> A_WL<153> A_WL<152> A_WL<151> A_WL<150> A_WL<149> A_WL<148> A_WL<147> A_WL<146> A_WL<145> A_WL<144> A_WL<143> A_WL<142> A_WL<141> A_WL<140> A_WL<139> A_WL<138> A_WL<137> A_WL<136> A_WL<135> A_WL<134> A_WL<133> A_WL<132> A_WL<131> A_WL<130> A_WL<129> A_WL<128> A_WL<127> A_WL<126> A_WL<125> A_WL<124> A_WL<123> A_WL<122> A_WL<121> A_WL<120> A_WL<119> A_WL<118> A_WL<117> A_WL<116> A_WL<115> A_WL<114> A_WL<113> A_WL<112> A_WL<111> A_WL<110> A_WL<109> A_WL<108> A_WL<107> A_WL<106> A_WL<105> A_WL<104> A_WL<103> A_WL<102> A_WL<101> A_WL<100> A_WL<99> A_WL<98> A_WL<97> A_WL<96> A_WL<95> A_WL<94> A_WL<93> A_WL<92> A_WL<91> A_WL<90> A_WL<89> A_WL<88> A_WL<87> A_WL<86> A_WL<85> A_WL<84> A_WL<83> A_WL<82> A_WL<81> A_WL<80> A_WL<79> A_WL<78> A_WL<77> A_WL<76> A_WL<75> A_WL<74> A_WL<73> A_WL<72> A_WL<71> A_WL<70> A_WL<69> A_WL<68> A_WL<67> A_WL<66> A_WL<65> A_WL<64> A_WL<63> A_WL<62> A_WL<61> A_WL<60> A_WL<59> A_WL<58> A_WL<57> A_WL<56> A_WL<55> A_WL<54> A_WL<53> A_WL<52> A_WL<51> A_WL<50> A_WL<49> A_WL<48> A_WL<47> A_WL<46> A_WL<45> A_WL<44> A_WL<43> A_WL<42> A_WL<41> A_WL<40> A_WL<39> A_WL<38> A_WL<37> A_WL<36> A_WL<35> A_WL<34> A_WL<33> A_WL<32> A_WL<31> A_WL<30> A_WL<29> A_WL<28> A_WL<27> A_WL<26> A_WL<25> A_WL<24> A_WL<23> A_WL<22> A_WL<21> A_WL<20> A_WL<19> A_WL<18> A_WL<17> A_WL<16> A_WL<15> A_WL<14> A_WL<13> A_WL<12> A_WL<11> A_WL<10> A_WL<9> A_WL<8> A_WL<7> A_WL<6> A_WL<5> A_WL<4> A_WL<3> A_WL<2> A_WL<1> A_WL<0> VDD_CORE VSS +XCORNER<3> VDD_CORE VSS / RM_IHPSG13_1024x32_c2_1P_BITKIT_16x2_CORNER +XCORNER<2> VDD_CORE VSS / RM_IHPSG13_1024x32_c2_1P_BITKIT_16x2_CORNER +XCORNER<1> VDD_CORE VSS / RM_IHPSG13_1024x32_c2_1P_BITKIT_16x2_CORNER +XCORNER<0> VDD_CORE VSS / RM_IHPSG13_1024x32_c2_1P_BITKIT_16x2_CORNER +XRAMEDGE_L<15> A_WL<255> A_WL<254> A_WL<253> A_WL<252> A_WL<251> A_WL<250> A_WL<249> A_WL<248> A_WL<247> A_WL<246> A_WL<245> A_WL<244> A_WL<243> A_WL<242> A_WL<241> A_WL<240> VDD_CORE VSS / RM_IHPSG13_1024x32_c2_1P_BITKIT_16x2_EDGE_LR +XRAMEDGE_L<14> A_WL<239> A_WL<238> A_WL<237> A_WL<236> A_WL<235> A_WL<234> A_WL<233> A_WL<232> A_WL<231> A_WL<230> A_WL<229> A_WL<228> A_WL<227> A_WL<226> A_WL<225> A_WL<224> VDD_CORE VSS / RM_IHPSG13_1024x32_c2_1P_BITKIT_16x2_EDGE_LR +XRAMEDGE_L<13> A_WL<223> A_WL<222> A_WL<221> A_WL<220> A_WL<219> A_WL<218> A_WL<217> A_WL<216> A_WL<215> A_WL<214> A_WL<213> A_WL<212> A_WL<211> A_WL<210> A_WL<209> A_WL<208> VDD_CORE VSS / RM_IHPSG13_1024x32_c2_1P_BITKIT_16x2_EDGE_LR +XRAMEDGE_L<12> A_WL<207> A_WL<206> A_WL<205> A_WL<204> A_WL<203> A_WL<202> A_WL<201> A_WL<200> A_WL<199> A_WL<198> A_WL<197> A_WL<196> A_WL<195> A_WL<194> A_WL<193> A_WL<192> VDD_CORE VSS / RM_IHPSG13_1024x32_c2_1P_BITKIT_16x2_EDGE_LR +XRAMEDGE_L<11> A_WL<191> A_WL<190> A_WL<189> A_WL<188> A_WL<187> A_WL<186> A_WL<185> A_WL<184> A_WL<183> A_WL<182> A_WL<181> A_WL<180> A_WL<179> A_WL<178> A_WL<177> A_WL<176> VDD_CORE VSS / RM_IHPSG13_1024x32_c2_1P_BITKIT_16x2_EDGE_LR +XRAMEDGE_L<10> A_WL<175> A_WL<174> A_WL<173> A_WL<172> A_WL<171> A_WL<170> A_WL<169> A_WL<168> A_WL<167> A_WL<166> A_WL<165> A_WL<164> A_WL<163> A_WL<162> A_WL<161> A_WL<160> VDD_CORE VSS / RM_IHPSG13_1024x32_c2_1P_BITKIT_16x2_EDGE_LR +XRAMEDGE_L<9> A_WL<159> A_WL<158> A_WL<157> A_WL<156> A_WL<155> A_WL<154> A_WL<153> A_WL<152> A_WL<151> A_WL<150> A_WL<149> A_WL<148> A_WL<147> A_WL<146> A_WL<145> A_WL<144> VDD_CORE VSS / RM_IHPSG13_1024x32_c2_1P_BITKIT_16x2_EDGE_LR +XRAMEDGE_L<8> A_WL<143> A_WL<142> A_WL<141> A_WL<140> A_WL<139> A_WL<138> A_WL<137> A_WL<136> A_WL<135> A_WL<134> A_WL<133> A_WL<132> A_WL<131> A_WL<130> A_WL<129> A_WL<128> VDD_CORE VSS / RM_IHPSG13_1024x32_c2_1P_BITKIT_16x2_EDGE_LR +XRAMEDGE_L<7> A_WL<127> A_WL<126> A_WL<125> A_WL<124> A_WL<123> A_WL<122> A_WL<121> A_WL<120> A_WL<119> A_WL<118> A_WL<117> A_WL<116> A_WL<115> A_WL<114> A_WL<113> A_WL<112> VDD_CORE VSS / RM_IHPSG13_1024x32_c2_1P_BITKIT_16x2_EDGE_LR +XRAMEDGE_L<6> A_WL<111> A_WL<110> A_WL<109> A_WL<108> A_WL<107> A_WL<106> A_WL<105> A_WL<104> A_WL<103> A_WL<102> A_WL<101> A_WL<100> A_WL<99> A_WL<98> A_WL<97> A_WL<96> VDD_CORE VSS / RM_IHPSG13_1024x32_c2_1P_BITKIT_16x2_EDGE_LR +XRAMEDGE_L<5> A_WL<95> A_WL<94> A_WL<93> A_WL<92> A_WL<91> A_WL<90> A_WL<89> A_WL<88> A_WL<87> A_WL<86> A_WL<85> A_WL<84> A_WL<83> A_WL<82> A_WL<81> A_WL<80> VDD_CORE VSS / RM_IHPSG13_1024x32_c2_1P_BITKIT_16x2_EDGE_LR +XRAMEDGE_L<4> A_WL<79> A_WL<78> A_WL<77> A_WL<76> A_WL<75> A_WL<74> A_WL<73> A_WL<72> A_WL<71> A_WL<70> A_WL<69> A_WL<68> A_WL<67> A_WL<66> A_WL<65> A_WL<64> VDD_CORE VSS / RM_IHPSG13_1024x32_c2_1P_BITKIT_16x2_EDGE_LR +XRAMEDGE_L<3> A_WL<63> A_WL<62> A_WL<61> A_WL<60> A_WL<59> A_WL<58> A_WL<57> A_WL<56> A_WL<55> A_WL<54> A_WL<53> A_WL<52> A_WL<51> A_WL<50> A_WL<49> A_WL<48> VDD_CORE VSS / RM_IHPSG13_1024x32_c2_1P_BITKIT_16x2_EDGE_LR +XRAMEDGE_L<2> A_WL<47> A_WL<46> A_WL<45> A_WL<44> A_WL<43> A_WL<42> A_WL<41> A_WL<40> A_WL<39> A_WL<38> A_WL<37> A_WL<36> A_WL<35> A_WL<34> A_WL<33> A_WL<32> VDD_CORE VSS / RM_IHPSG13_1024x32_c2_1P_BITKIT_16x2_EDGE_LR +XRAMEDGE_L<1> A_WL<31> A_WL<30> A_WL<29> A_WL<28> A_WL<27> A_WL<26> A_WL<25> A_WL<24> A_WL<23> A_WL<22> A_WL<21> A_WL<20> A_WL<19> A_WL<18> A_WL<17> A_WL<16> VDD_CORE VSS / RM_IHPSG13_1024x32_c2_1P_BITKIT_16x2_EDGE_LR +XRAMEDGE_L<0> A_WL<15> A_WL<14> A_WL<13> A_WL<12> A_WL<11> A_WL<10> A_WL<9> A_WL<8> A_WL<7> A_WL<6> A_WL<5> A_WL<4> A_WL<3> A_WL<2> A_WL<1> A_WL<0> VDD_CORE VSS / RM_IHPSG13_1024x32_c2_1P_BITKIT_16x2_EDGE_LR +XRAMEDGE_R<15> A_IWL<8191> A_IWL<8190> A_IWL<8189> A_IWL<8188> A_IWL<8187> A_IWL<8186> A_IWL<8185> A_IWL<8184> A_IWL<8183> A_IWL<8182> A_IWL<8181> A_IWL<8180> A_IWL<8179> A_IWL<8178> A_IWL<8177> A_IWL<8176> VDD_CORE VSS / RM_IHPSG13_1024x32_c2_1P_BITKIT_16x2_EDGE_LR +XRAMEDGE_R<14> A_IWL<8175> A_IWL<8174> A_IWL<8173> A_IWL<8172> A_IWL<8171> A_IWL<8170> A_IWL<8169> A_IWL<8168> A_IWL<8167> A_IWL<8166> A_IWL<8165> A_IWL<8164> A_IWL<8163> A_IWL<8162> A_IWL<8161> A_IWL<8160> VDD_CORE VSS / RM_IHPSG13_1024x32_c2_1P_BITKIT_16x2_EDGE_LR +XRAMEDGE_R<13> A_IWL<8159> A_IWL<8158> A_IWL<8157> A_IWL<8156> A_IWL<8155> A_IWL<8154> A_IWL<8153> A_IWL<8152> A_IWL<8151> A_IWL<8150> A_IWL<8149> A_IWL<8148> A_IWL<8147> A_IWL<8146> A_IWL<8145> A_IWL<8144> VDD_CORE VSS / RM_IHPSG13_1024x32_c2_1P_BITKIT_16x2_EDGE_LR +XRAMEDGE_R<12> A_IWL<8143> A_IWL<8142> A_IWL<8141> A_IWL<8140> A_IWL<8139> A_IWL<8138> A_IWL<8137> A_IWL<8136> A_IWL<8135> A_IWL<8134> A_IWL<8133> A_IWL<8132> A_IWL<8131> A_IWL<8130> A_IWL<8129> A_IWL<8128> VDD_CORE VSS / RM_IHPSG13_1024x32_c2_1P_BITKIT_16x2_EDGE_LR +XRAMEDGE_R<11> A_IWL<8127> A_IWL<8126> A_IWL<8125> A_IWL<8124> A_IWL<8123> A_IWL<8122> A_IWL<8121> A_IWL<8120> A_IWL<8119> A_IWL<8118> A_IWL<8117> A_IWL<8116> A_IWL<8115> A_IWL<8114> A_IWL<8113> A_IWL<8112> VDD_CORE VSS / RM_IHPSG13_1024x32_c2_1P_BITKIT_16x2_EDGE_LR +XRAMEDGE_R<10> A_IWL<8111> A_IWL<8110> A_IWL<8109> A_IWL<8108> A_IWL<8107> A_IWL<8106> A_IWL<8105> A_IWL<8104> A_IWL<8103> A_IWL<8102> A_IWL<8101> A_IWL<8100> A_IWL<8099> A_IWL<8098> A_IWL<8097> A_IWL<8096> VDD_CORE VSS / RM_IHPSG13_1024x32_c2_1P_BITKIT_16x2_EDGE_LR +XRAMEDGE_R<9> A_IWL<8095> A_IWL<8094> A_IWL<8093> A_IWL<8092> A_IWL<8091> A_IWL<8090> A_IWL<8089> A_IWL<8088> A_IWL<8087> A_IWL<8086> A_IWL<8085> A_IWL<8084> A_IWL<8083> A_IWL<8082> A_IWL<8081> A_IWL<8080> VDD_CORE VSS / RM_IHPSG13_1024x32_c2_1P_BITKIT_16x2_EDGE_LR +XRAMEDGE_R<8> A_IWL<8079> A_IWL<8078> A_IWL<8077> A_IWL<8076> A_IWL<8075> A_IWL<8074> A_IWL<8073> A_IWL<8072> A_IWL<8071> A_IWL<8070> A_IWL<8069> A_IWL<8068> A_IWL<8067> A_IWL<8066> A_IWL<8065> A_IWL<8064> VDD_CORE VSS / RM_IHPSG13_1024x32_c2_1P_BITKIT_16x2_EDGE_LR +XRAMEDGE_R<7> A_IWL<8063> A_IWL<8062> A_IWL<8061> A_IWL<8060> A_IWL<8059> A_IWL<8058> A_IWL<8057> A_IWL<8056> A_IWL<8055> A_IWL<8054> A_IWL<8053> A_IWL<8052> A_IWL<8051> A_IWL<8050> A_IWL<8049> A_IWL<8048> VDD_CORE VSS / RM_IHPSG13_1024x32_c2_1P_BITKIT_16x2_EDGE_LR +XRAMEDGE_R<6> A_IWL<8047> A_IWL<8046> A_IWL<8045> A_IWL<8044> A_IWL<8043> A_IWL<8042> A_IWL<8041> A_IWL<8040> A_IWL<8039> A_IWL<8038> A_IWL<8037> A_IWL<8036> A_IWL<8035> A_IWL<8034> A_IWL<8033> A_IWL<8032> VDD_CORE VSS / RM_IHPSG13_1024x32_c2_1P_BITKIT_16x2_EDGE_LR +XRAMEDGE_R<5> A_IWL<8031> A_IWL<8030> A_IWL<8029> A_IWL<8028> A_IWL<8027> A_IWL<8026> A_IWL<8025> A_IWL<8024> A_IWL<8023> A_IWL<8022> A_IWL<8021> A_IWL<8020> A_IWL<8019> A_IWL<8018> A_IWL<8017> A_IWL<8016> VDD_CORE VSS / RM_IHPSG13_1024x32_c2_1P_BITKIT_16x2_EDGE_LR +XRAMEDGE_R<4> A_IWL<8015> A_IWL<8014> A_IWL<8013> A_IWL<8012> A_IWL<8011> A_IWL<8010> A_IWL<8009> A_IWL<8008> A_IWL<8007> A_IWL<8006> A_IWL<8005> A_IWL<8004> A_IWL<8003> A_IWL<8002> A_IWL<8001> A_IWL<8000> VDD_CORE VSS / RM_IHPSG13_1024x32_c2_1P_BITKIT_16x2_EDGE_LR +XRAMEDGE_R<3> A_IWL<7999> A_IWL<7998> A_IWL<7997> A_IWL<7996> A_IWL<7995> A_IWL<7994> A_IWL<7993> A_IWL<7992> A_IWL<7991> A_IWL<7990> A_IWL<7989> A_IWL<7988> A_IWL<7987> A_IWL<7986> A_IWL<7985> A_IWL<7984> VDD_CORE VSS / RM_IHPSG13_1024x32_c2_1P_BITKIT_16x2_EDGE_LR +XRAMEDGE_R<2> A_IWL<7983> A_IWL<7982> A_IWL<7981> A_IWL<7980> A_IWL<7979> A_IWL<7978> A_IWL<7977> A_IWL<7976> A_IWL<7975> A_IWL<7974> A_IWL<7973> A_IWL<7972> A_IWL<7971> A_IWL<7970> A_IWL<7969> A_IWL<7968> VDD_CORE VSS / RM_IHPSG13_1024x32_c2_1P_BITKIT_16x2_EDGE_LR +XRAMEDGE_R<1> A_IWL<7967> A_IWL<7966> A_IWL<7965> A_IWL<7964> A_IWL<7963> A_IWL<7962> A_IWL<7961> A_IWL<7960> A_IWL<7959> A_IWL<7958> A_IWL<7957> A_IWL<7956> A_IWL<7955> A_IWL<7954> A_IWL<7953> A_IWL<7952> VDD_CORE VSS / RM_IHPSG13_1024x32_c2_1P_BITKIT_16x2_EDGE_LR +XRAMEDGE_R<0> A_IWL<7951> A_IWL<7950> A_IWL<7949> A_IWL<7948> A_IWL<7947> A_IWL<7946> A_IWL<7945> A_IWL<7944> A_IWL<7943> A_IWL<7942> A_IWL<7941> A_IWL<7940> A_IWL<7939> A_IWL<7938> A_IWL<7937> A_IWL<7936> VDD_CORE VSS / RM_IHPSG13_1024x32_c2_1P_BITKIT_16x2_EDGE_LR +XCOL<31> A_BLC<63> A_BLC<62> A_BLC_TOP<63> A_BLC_TOP<62> A_BLT<63> A_BLT<62> A_BLT_TOP<63> A_BLT_TOP<62> A_IWL<7935> A_IWL<7934> A_IWL<7933> A_IWL<7932> A_IWL<7931> A_IWL<7930> A_IWL<7929> A_IWL<7928> A_IWL<7927> A_IWL<7926> A_IWL<7925> A_IWL<7924> A_IWL<7923> A_IWL<7922> A_IWL<7921> A_IWL<7920> A_IWL<7919> A_IWL<7918> A_IWL<7917> A_IWL<7916> A_IWL<7915> A_IWL<7914> A_IWL<7913> A_IWL<7912> A_IWL<7911> A_IWL<7910> A_IWL<7909> A_IWL<7908> A_IWL<7907> A_IWL<7906> A_IWL<7905> A_IWL<7904> A_IWL<7903> A_IWL<7902> A_IWL<7901> A_IWL<7900> A_IWL<7899> A_IWL<7898> A_IWL<7897> A_IWL<7896> A_IWL<7895> A_IWL<7894> A_IWL<7893> A_IWL<7892> A_IWL<7891> A_IWL<7890> A_IWL<7889> A_IWL<7888> A_IWL<7887> A_IWL<7886> A_IWL<7885> A_IWL<7884> A_IWL<7883> A_IWL<7882> A_IWL<7881> A_IWL<7880> A_IWL<7879> A_IWL<7878> A_IWL<7877> A_IWL<7876> A_IWL<7875> A_IWL<7874> A_IWL<7873> A_IWL<7872> A_IWL<7871> A_IWL<7870> A_IWL<7869> A_IWL<7868> A_IWL<7867> A_IWL<7866> A_IWL<7865> A_IWL<7864> A_IWL<7863> A_IWL<7862> A_IWL<7861> A_IWL<7860> A_IWL<7859> A_IWL<7858> A_IWL<7857> A_IWL<7856> A_IWL<7855> A_IWL<7854> A_IWL<7853> A_IWL<7852> A_IWL<7851> A_IWL<7850> A_IWL<7849> A_IWL<7848> A_IWL<7847> A_IWL<7846> A_IWL<7845> A_IWL<7844> A_IWL<7843> A_IWL<7842> A_IWL<7841> A_IWL<7840> A_IWL<7839> A_IWL<7838> A_IWL<7837> A_IWL<7836> A_IWL<7835> A_IWL<7834> A_IWL<7833> A_IWL<7832> A_IWL<7831> A_IWL<7830> A_IWL<7829> A_IWL<7828> A_IWL<7827> A_IWL<7826> A_IWL<7825> A_IWL<7824> A_IWL<7823> A_IWL<7822> A_IWL<7821> A_IWL<7820> A_IWL<7819> A_IWL<7818> A_IWL<7817> A_IWL<7816> A_IWL<7815> A_IWL<7814> A_IWL<7813> A_IWL<7812> A_IWL<7811> A_IWL<7810> A_IWL<7809> A_IWL<7808> A_IWL<7807> A_IWL<7806> A_IWL<7805> A_IWL<7804> A_IWL<7803> A_IWL<7802> A_IWL<7801> A_IWL<7800> A_IWL<7799> A_IWL<7798> A_IWL<7797> A_IWL<7796> A_IWL<7795> A_IWL<7794> A_IWL<7793> A_IWL<7792> A_IWL<7791> A_IWL<7790> A_IWL<7789> A_IWL<7788> A_IWL<7787> A_IWL<7786> A_IWL<7785> A_IWL<7784> A_IWL<7783> A_IWL<7782> A_IWL<7781> A_IWL<7780> A_IWL<7779> A_IWL<7778> A_IWL<7777> A_IWL<7776> A_IWL<7775> A_IWL<7774> A_IWL<7773> A_IWL<7772> A_IWL<7771> A_IWL<7770> A_IWL<7769> A_IWL<7768> A_IWL<7767> A_IWL<7766> A_IWL<7765> A_IWL<7764> A_IWL<7763> A_IWL<7762> A_IWL<7761> A_IWL<7760> A_IWL<7759> A_IWL<7758> A_IWL<7757> A_IWL<7756> A_IWL<7755> A_IWL<7754> A_IWL<7753> A_IWL<7752> A_IWL<7751> A_IWL<7750> A_IWL<7749> A_IWL<7748> A_IWL<7747> A_IWL<7746> A_IWL<7745> A_IWL<7744> A_IWL<7743> A_IWL<7742> A_IWL<7741> A_IWL<7740> A_IWL<7739> A_IWL<7738> A_IWL<7737> A_IWL<7736> A_IWL<7735> A_IWL<7734> A_IWL<7733> A_IWL<7732> A_IWL<7731> A_IWL<7730> A_IWL<7729> A_IWL<7728> A_IWL<7727> A_IWL<7726> A_IWL<7725> A_IWL<7724> A_IWL<7723> A_IWL<7722> A_IWL<7721> A_IWL<7720> A_IWL<7719> A_IWL<7718> A_IWL<7717> A_IWL<7716> A_IWL<7715> A_IWL<7714> A_IWL<7713> A_IWL<7712> A_IWL<7711> A_IWL<7710> A_IWL<7709> A_IWL<7708> A_IWL<7707> A_IWL<7706> A_IWL<7705> A_IWL<7704> A_IWL<7703> A_IWL<7702> A_IWL<7701> A_IWL<7700> A_IWL<7699> A_IWL<7698> A_IWL<7697> A_IWL<7696> A_IWL<7695> A_IWL<7694> A_IWL<7693> A_IWL<7692> A_IWL<7691> A_IWL<7690> A_IWL<7689> A_IWL<7688> A_IWL<7687> A_IWL<7686> A_IWL<7685> A_IWL<7684> A_IWL<7683> A_IWL<7682> A_IWL<7681> A_IWL<7680> A_IWL<8191> A_IWL<8190> A_IWL<8189> A_IWL<8188> A_IWL<8187> A_IWL<8186> A_IWL<8185> A_IWL<8184> A_IWL<8183> A_IWL<8182> A_IWL<8181> A_IWL<8180> A_IWL<8179> A_IWL<8178> A_IWL<8177> A_IWL<8176> A_IWL<8175> A_IWL<8174> A_IWL<8173> A_IWL<8172> A_IWL<8171> A_IWL<8170> A_IWL<8169> A_IWL<8168> A_IWL<8167> A_IWL<8166> A_IWL<8165> A_IWL<8164> A_IWL<8163> A_IWL<8162> A_IWL<8161> A_IWL<8160> A_IWL<8159> A_IWL<8158> A_IWL<8157> A_IWL<8156> A_IWL<8155> A_IWL<8154> A_IWL<8153> A_IWL<8152> A_IWL<8151> A_IWL<8150> A_IWL<8149> A_IWL<8148> A_IWL<8147> A_IWL<8146> A_IWL<8145> A_IWL<8144> A_IWL<8143> A_IWL<8142> A_IWL<8141> A_IWL<8140> A_IWL<8139> A_IWL<8138> A_IWL<8137> A_IWL<8136> A_IWL<8135> A_IWL<8134> A_IWL<8133> A_IWL<8132> A_IWL<8131> A_IWL<8130> A_IWL<8129> A_IWL<8128> A_IWL<8127> A_IWL<8126> A_IWL<8125> A_IWL<8124> A_IWL<8123> A_IWL<8122> A_IWL<8121> A_IWL<8120> A_IWL<8119> A_IWL<8118> A_IWL<8117> A_IWL<8116> A_IWL<8115> A_IWL<8114> A_IWL<8113> A_IWL<8112> A_IWL<8111> A_IWL<8110> A_IWL<8109> A_IWL<8108> A_IWL<8107> A_IWL<8106> A_IWL<8105> A_IWL<8104> A_IWL<8103> A_IWL<8102> A_IWL<8101> A_IWL<8100> A_IWL<8099> A_IWL<8098> A_IWL<8097> A_IWL<8096> A_IWL<8095> A_IWL<8094> A_IWL<8093> A_IWL<8092> A_IWL<8091> A_IWL<8090> A_IWL<8089> A_IWL<8088> A_IWL<8087> A_IWL<8086> A_IWL<8085> A_IWL<8084> A_IWL<8083> A_IWL<8082> A_IWL<8081> A_IWL<8080> A_IWL<8079> A_IWL<8078> A_IWL<8077> A_IWL<8076> A_IWL<8075> A_IWL<8074> A_IWL<8073> A_IWL<8072> A_IWL<8071> A_IWL<8070> A_IWL<8069> A_IWL<8068> A_IWL<8067> A_IWL<8066> A_IWL<8065> A_IWL<8064> A_IWL<8063> A_IWL<8062> A_IWL<8061> A_IWL<8060> A_IWL<8059> A_IWL<8058> A_IWL<8057> A_IWL<8056> A_IWL<8055> A_IWL<8054> A_IWL<8053> A_IWL<8052> A_IWL<8051> A_IWL<8050> A_IWL<8049> A_IWL<8048> A_IWL<8047> A_IWL<8046> A_IWL<8045> A_IWL<8044> A_IWL<8043> A_IWL<8042> A_IWL<8041> A_IWL<8040> A_IWL<8039> A_IWL<8038> A_IWL<8037> A_IWL<8036> A_IWL<8035> A_IWL<8034> A_IWL<8033> A_IWL<8032> A_IWL<8031> A_IWL<8030> A_IWL<8029> A_IWL<8028> A_IWL<8027> A_IWL<8026> A_IWL<8025> A_IWL<8024> A_IWL<8023> A_IWL<8022> A_IWL<8021> A_IWL<8020> A_IWL<8019> A_IWL<8018> A_IWL<8017> A_IWL<8016> A_IWL<8015> A_IWL<8014> A_IWL<8013> A_IWL<8012> A_IWL<8011> A_IWL<8010> A_IWL<8009> A_IWL<8008> A_IWL<8007> A_IWL<8006> A_IWL<8005> A_IWL<8004> A_IWL<8003> A_IWL<8002> A_IWL<8001> A_IWL<8000> A_IWL<7999> A_IWL<7998> A_IWL<7997> A_IWL<7996> A_IWL<7995> A_IWL<7994> A_IWL<7993> A_IWL<7992> A_IWL<7991> A_IWL<7990> A_IWL<7989> A_IWL<7988> A_IWL<7987> A_IWL<7986> A_IWL<7985> A_IWL<7984> A_IWL<7983> A_IWL<7982> A_IWL<7981> A_IWL<7980> A_IWL<7979> A_IWL<7978> A_IWL<7977> A_IWL<7976> A_IWL<7975> A_IWL<7974> A_IWL<7973> A_IWL<7972> A_IWL<7971> A_IWL<7970> A_IWL<7969> A_IWL<7968> A_IWL<7967> A_IWL<7966> A_IWL<7965> A_IWL<7964> A_IWL<7963> A_IWL<7962> A_IWL<7961> A_IWL<7960> A_IWL<7959> A_IWL<7958> A_IWL<7957> A_IWL<7956> A_IWL<7955> A_IWL<7954> A_IWL<7953> A_IWL<7952> A_IWL<7951> A_IWL<7950> A_IWL<7949> A_IWL<7948> A_IWL<7947> A_IWL<7946> A_IWL<7945> A_IWL<7944> A_IWL<7943> A_IWL<7942> A_IWL<7941> A_IWL<7940> A_IWL<7939> A_IWL<7938> A_IWL<7937> A_IWL<7936> VDD_CORE VSS / RM_IHPSG13_1024x32_c2_1P_COLUMN_pcell_0 +XCOL<30> A_BLC<61> A_BLC<60> A_BLC_TOP<61> A_BLC_TOP<60> A_BLT<61> A_BLT<60> A_BLT_TOP<61> A_BLT_TOP<60> A_IWL<7679> A_IWL<7678> A_IWL<7677> A_IWL<7676> A_IWL<7675> A_IWL<7674> A_IWL<7673> A_IWL<7672> A_IWL<7671> A_IWL<7670> A_IWL<7669> A_IWL<7668> A_IWL<7667> A_IWL<7666> A_IWL<7665> A_IWL<7664> A_IWL<7663> A_IWL<7662> A_IWL<7661> A_IWL<7660> A_IWL<7659> A_IWL<7658> A_IWL<7657> A_IWL<7656> A_IWL<7655> A_IWL<7654> A_IWL<7653> A_IWL<7652> A_IWL<7651> A_IWL<7650> A_IWL<7649> A_IWL<7648> A_IWL<7647> A_IWL<7646> A_IWL<7645> A_IWL<7644> A_IWL<7643> A_IWL<7642> A_IWL<7641> A_IWL<7640> A_IWL<7639> A_IWL<7638> A_IWL<7637> A_IWL<7636> A_IWL<7635> A_IWL<7634> A_IWL<7633> A_IWL<7632> A_IWL<7631> A_IWL<7630> A_IWL<7629> A_IWL<7628> A_IWL<7627> A_IWL<7626> A_IWL<7625> A_IWL<7624> A_IWL<7623> A_IWL<7622> A_IWL<7621> A_IWL<7620> A_IWL<7619> A_IWL<7618> A_IWL<7617> A_IWL<7616> A_IWL<7615> A_IWL<7614> A_IWL<7613> A_IWL<7612> A_IWL<7611> A_IWL<7610> A_IWL<7609> A_IWL<7608> A_IWL<7607> A_IWL<7606> A_IWL<7605> A_IWL<7604> A_IWL<7603> A_IWL<7602> A_IWL<7601> A_IWL<7600> A_IWL<7599> A_IWL<7598> A_IWL<7597> A_IWL<7596> A_IWL<7595> A_IWL<7594> A_IWL<7593> A_IWL<7592> A_IWL<7591> A_IWL<7590> A_IWL<7589> A_IWL<7588> A_IWL<7587> A_IWL<7586> A_IWL<7585> A_IWL<7584> A_IWL<7583> A_IWL<7582> A_IWL<7581> A_IWL<7580> A_IWL<7579> A_IWL<7578> A_IWL<7577> A_IWL<7576> A_IWL<7575> A_IWL<7574> A_IWL<7573> A_IWL<7572> A_IWL<7571> A_IWL<7570> A_IWL<7569> A_IWL<7568> A_IWL<7567> A_IWL<7566> A_IWL<7565> A_IWL<7564> A_IWL<7563> A_IWL<7562> A_IWL<7561> A_IWL<7560> A_IWL<7559> A_IWL<7558> A_IWL<7557> A_IWL<7556> A_IWL<7555> A_IWL<7554> A_IWL<7553> A_IWL<7552> A_IWL<7551> A_IWL<7550> A_IWL<7549> A_IWL<7548> A_IWL<7547> A_IWL<7546> A_IWL<7545> A_IWL<7544> A_IWL<7543> A_IWL<7542> A_IWL<7541> A_IWL<7540> A_IWL<7539> A_IWL<7538> A_IWL<7537> A_IWL<7536> A_IWL<7535> A_IWL<7534> A_IWL<7533> A_IWL<7532> A_IWL<7531> A_IWL<7530> A_IWL<7529> A_IWL<7528> A_IWL<7527> A_IWL<7526> A_IWL<7525> A_IWL<7524> A_IWL<7523> A_IWL<7522> A_IWL<7521> A_IWL<7520> A_IWL<7519> A_IWL<7518> A_IWL<7517> A_IWL<7516> A_IWL<7515> A_IWL<7514> A_IWL<7513> A_IWL<7512> A_IWL<7511> A_IWL<7510> A_IWL<7509> A_IWL<7508> A_IWL<7507> A_IWL<7506> A_IWL<7505> A_IWL<7504> A_IWL<7503> A_IWL<7502> A_IWL<7501> A_IWL<7500> A_IWL<7499> A_IWL<7498> A_IWL<7497> A_IWL<7496> A_IWL<7495> A_IWL<7494> A_IWL<7493> A_IWL<7492> A_IWL<7491> A_IWL<7490> A_IWL<7489> A_IWL<7488> A_IWL<7487> A_IWL<7486> A_IWL<7485> A_IWL<7484> A_IWL<7483> A_IWL<7482> A_IWL<7481> A_IWL<7480> A_IWL<7479> A_IWL<7478> A_IWL<7477> A_IWL<7476> A_IWL<7475> A_IWL<7474> A_IWL<7473> A_IWL<7472> A_IWL<7471> A_IWL<7470> A_IWL<7469> A_IWL<7468> A_IWL<7467> A_IWL<7466> A_IWL<7465> A_IWL<7464> A_IWL<7463> A_IWL<7462> A_IWL<7461> A_IWL<7460> A_IWL<7459> A_IWL<7458> A_IWL<7457> A_IWL<7456> A_IWL<7455> A_IWL<7454> A_IWL<7453> A_IWL<7452> A_IWL<7451> A_IWL<7450> A_IWL<7449> A_IWL<7448> A_IWL<7447> A_IWL<7446> A_IWL<7445> A_IWL<7444> A_IWL<7443> A_IWL<7442> A_IWL<7441> A_IWL<7440> A_IWL<7439> A_IWL<7438> A_IWL<7437> A_IWL<7436> A_IWL<7435> A_IWL<7434> A_IWL<7433> A_IWL<7432> A_IWL<7431> A_IWL<7430> A_IWL<7429> A_IWL<7428> A_IWL<7427> A_IWL<7426> A_IWL<7425> A_IWL<7424> A_IWL<7935> A_IWL<7934> A_IWL<7933> A_IWL<7932> A_IWL<7931> A_IWL<7930> A_IWL<7929> A_IWL<7928> A_IWL<7927> A_IWL<7926> A_IWL<7925> A_IWL<7924> A_IWL<7923> A_IWL<7922> A_IWL<7921> A_IWL<7920> A_IWL<7919> A_IWL<7918> A_IWL<7917> A_IWL<7916> A_IWL<7915> A_IWL<7914> A_IWL<7913> A_IWL<7912> A_IWL<7911> A_IWL<7910> A_IWL<7909> A_IWL<7908> A_IWL<7907> A_IWL<7906> A_IWL<7905> A_IWL<7904> A_IWL<7903> A_IWL<7902> A_IWL<7901> A_IWL<7900> A_IWL<7899> A_IWL<7898> A_IWL<7897> A_IWL<7896> A_IWL<7895> A_IWL<7894> A_IWL<7893> A_IWL<7892> A_IWL<7891> A_IWL<7890> A_IWL<7889> A_IWL<7888> A_IWL<7887> A_IWL<7886> A_IWL<7885> A_IWL<7884> A_IWL<7883> A_IWL<7882> A_IWL<7881> A_IWL<7880> A_IWL<7879> A_IWL<7878> A_IWL<7877> A_IWL<7876> A_IWL<7875> A_IWL<7874> A_IWL<7873> A_IWL<7872> A_IWL<7871> A_IWL<7870> A_IWL<7869> A_IWL<7868> A_IWL<7867> A_IWL<7866> A_IWL<7865> A_IWL<7864> A_IWL<7863> A_IWL<7862> A_IWL<7861> A_IWL<7860> A_IWL<7859> A_IWL<7858> A_IWL<7857> A_IWL<7856> A_IWL<7855> A_IWL<7854> A_IWL<7853> A_IWL<7852> A_IWL<7851> A_IWL<7850> A_IWL<7849> A_IWL<7848> A_IWL<7847> A_IWL<7846> A_IWL<7845> A_IWL<7844> A_IWL<7843> A_IWL<7842> A_IWL<7841> A_IWL<7840> A_IWL<7839> A_IWL<7838> A_IWL<7837> A_IWL<7836> A_IWL<7835> A_IWL<7834> A_IWL<7833> A_IWL<7832> A_IWL<7831> A_IWL<7830> A_IWL<7829> A_IWL<7828> A_IWL<7827> A_IWL<7826> A_IWL<7825> A_IWL<7824> A_IWL<7823> A_IWL<7822> A_IWL<7821> A_IWL<7820> A_IWL<7819> A_IWL<7818> A_IWL<7817> A_IWL<7816> A_IWL<7815> A_IWL<7814> A_IWL<7813> A_IWL<7812> A_IWL<7811> A_IWL<7810> A_IWL<7809> A_IWL<7808> A_IWL<7807> A_IWL<7806> A_IWL<7805> A_IWL<7804> A_IWL<7803> A_IWL<7802> A_IWL<7801> A_IWL<7800> A_IWL<7799> A_IWL<7798> A_IWL<7797> A_IWL<7796> A_IWL<7795> A_IWL<7794> A_IWL<7793> A_IWL<7792> A_IWL<7791> A_IWL<7790> A_IWL<7789> A_IWL<7788> A_IWL<7787> A_IWL<7786> A_IWL<7785> A_IWL<7784> A_IWL<7783> A_IWL<7782> A_IWL<7781> A_IWL<7780> A_IWL<7779> A_IWL<7778> A_IWL<7777> A_IWL<7776> A_IWL<7775> A_IWL<7774> A_IWL<7773> A_IWL<7772> A_IWL<7771> A_IWL<7770> A_IWL<7769> A_IWL<7768> A_IWL<7767> A_IWL<7766> A_IWL<7765> A_IWL<7764> A_IWL<7763> A_IWL<7762> A_IWL<7761> A_IWL<7760> A_IWL<7759> A_IWL<7758> A_IWL<7757> A_IWL<7756> A_IWL<7755> A_IWL<7754> A_IWL<7753> A_IWL<7752> A_IWL<7751> A_IWL<7750> A_IWL<7749> A_IWL<7748> A_IWL<7747> A_IWL<7746> A_IWL<7745> A_IWL<7744> A_IWL<7743> A_IWL<7742> A_IWL<7741> A_IWL<7740> A_IWL<7739> A_IWL<7738> A_IWL<7737> A_IWL<7736> A_IWL<7735> A_IWL<7734> A_IWL<7733> A_IWL<7732> A_IWL<7731> A_IWL<7730> A_IWL<7729> A_IWL<7728> A_IWL<7727> A_IWL<7726> A_IWL<7725> A_IWL<7724> A_IWL<7723> A_IWL<7722> A_IWL<7721> A_IWL<7720> A_IWL<7719> A_IWL<7718> A_IWL<7717> A_IWL<7716> A_IWL<7715> A_IWL<7714> A_IWL<7713> A_IWL<7712> A_IWL<7711> A_IWL<7710> A_IWL<7709> A_IWL<7708> A_IWL<7707> A_IWL<7706> A_IWL<7705> A_IWL<7704> A_IWL<7703> A_IWL<7702> A_IWL<7701> A_IWL<7700> A_IWL<7699> A_IWL<7698> A_IWL<7697> A_IWL<7696> A_IWL<7695> A_IWL<7694> A_IWL<7693> A_IWL<7692> A_IWL<7691> A_IWL<7690> A_IWL<7689> A_IWL<7688> A_IWL<7687> A_IWL<7686> A_IWL<7685> A_IWL<7684> A_IWL<7683> A_IWL<7682> A_IWL<7681> A_IWL<7680> VDD_CORE VSS / RM_IHPSG13_1024x32_c2_1P_COLUMN_pcell_0 +XCOL<29> A_BLC<59> A_BLC<58> A_BLC_TOP<59> A_BLC_TOP<58> A_BLT<59> A_BLT<58> A_BLT_TOP<59> A_BLT_TOP<58> A_IWL<7423> A_IWL<7422> A_IWL<7421> A_IWL<7420> A_IWL<7419> A_IWL<7418> A_IWL<7417> A_IWL<7416> A_IWL<7415> A_IWL<7414> A_IWL<7413> A_IWL<7412> A_IWL<7411> A_IWL<7410> A_IWL<7409> A_IWL<7408> A_IWL<7407> A_IWL<7406> A_IWL<7405> A_IWL<7404> A_IWL<7403> A_IWL<7402> A_IWL<7401> A_IWL<7400> A_IWL<7399> A_IWL<7398> A_IWL<7397> A_IWL<7396> A_IWL<7395> A_IWL<7394> A_IWL<7393> A_IWL<7392> A_IWL<7391> A_IWL<7390> A_IWL<7389> A_IWL<7388> A_IWL<7387> A_IWL<7386> A_IWL<7385> A_IWL<7384> A_IWL<7383> A_IWL<7382> A_IWL<7381> A_IWL<7380> A_IWL<7379> A_IWL<7378> A_IWL<7377> A_IWL<7376> A_IWL<7375> A_IWL<7374> A_IWL<7373> A_IWL<7372> A_IWL<7371> A_IWL<7370> A_IWL<7369> A_IWL<7368> A_IWL<7367> A_IWL<7366> A_IWL<7365> A_IWL<7364> A_IWL<7363> A_IWL<7362> A_IWL<7361> A_IWL<7360> A_IWL<7359> A_IWL<7358> A_IWL<7357> A_IWL<7356> A_IWL<7355> A_IWL<7354> A_IWL<7353> A_IWL<7352> A_IWL<7351> A_IWL<7350> A_IWL<7349> A_IWL<7348> A_IWL<7347> A_IWL<7346> A_IWL<7345> A_IWL<7344> A_IWL<7343> A_IWL<7342> A_IWL<7341> A_IWL<7340> A_IWL<7339> A_IWL<7338> A_IWL<7337> A_IWL<7336> A_IWL<7335> A_IWL<7334> A_IWL<7333> A_IWL<7332> A_IWL<7331> A_IWL<7330> A_IWL<7329> A_IWL<7328> A_IWL<7327> A_IWL<7326> A_IWL<7325> A_IWL<7324> A_IWL<7323> A_IWL<7322> A_IWL<7321> A_IWL<7320> A_IWL<7319> A_IWL<7318> A_IWL<7317> A_IWL<7316> A_IWL<7315> A_IWL<7314> A_IWL<7313> A_IWL<7312> A_IWL<7311> A_IWL<7310> A_IWL<7309> A_IWL<7308> A_IWL<7307> A_IWL<7306> A_IWL<7305> A_IWL<7304> A_IWL<7303> A_IWL<7302> A_IWL<7301> A_IWL<7300> A_IWL<7299> A_IWL<7298> A_IWL<7297> A_IWL<7296> A_IWL<7295> A_IWL<7294> A_IWL<7293> A_IWL<7292> A_IWL<7291> A_IWL<7290> A_IWL<7289> A_IWL<7288> A_IWL<7287> A_IWL<7286> A_IWL<7285> A_IWL<7284> A_IWL<7283> A_IWL<7282> A_IWL<7281> A_IWL<7280> A_IWL<7279> A_IWL<7278> A_IWL<7277> A_IWL<7276> A_IWL<7275> A_IWL<7274> A_IWL<7273> A_IWL<7272> A_IWL<7271> A_IWL<7270> A_IWL<7269> A_IWL<7268> A_IWL<7267> A_IWL<7266> A_IWL<7265> A_IWL<7264> A_IWL<7263> A_IWL<7262> A_IWL<7261> A_IWL<7260> A_IWL<7259> A_IWL<7258> A_IWL<7257> A_IWL<7256> A_IWL<7255> A_IWL<7254> A_IWL<7253> A_IWL<7252> A_IWL<7251> A_IWL<7250> A_IWL<7249> A_IWL<7248> A_IWL<7247> A_IWL<7246> A_IWL<7245> A_IWL<7244> A_IWL<7243> A_IWL<7242> A_IWL<7241> A_IWL<7240> A_IWL<7239> A_IWL<7238> A_IWL<7237> A_IWL<7236> A_IWL<7235> A_IWL<7234> A_IWL<7233> A_IWL<7232> A_IWL<7231> A_IWL<7230> A_IWL<7229> A_IWL<7228> A_IWL<7227> A_IWL<7226> A_IWL<7225> A_IWL<7224> A_IWL<7223> A_IWL<7222> A_IWL<7221> A_IWL<7220> A_IWL<7219> A_IWL<7218> A_IWL<7217> A_IWL<7216> A_IWL<7215> A_IWL<7214> A_IWL<7213> A_IWL<7212> A_IWL<7211> A_IWL<7210> A_IWL<7209> A_IWL<7208> A_IWL<7207> A_IWL<7206> A_IWL<7205> A_IWL<7204> A_IWL<7203> A_IWL<7202> A_IWL<7201> A_IWL<7200> A_IWL<7199> A_IWL<7198> A_IWL<7197> A_IWL<7196> A_IWL<7195> A_IWL<7194> A_IWL<7193> A_IWL<7192> A_IWL<7191> A_IWL<7190> A_IWL<7189> A_IWL<7188> A_IWL<7187> A_IWL<7186> A_IWL<7185> A_IWL<7184> A_IWL<7183> A_IWL<7182> A_IWL<7181> A_IWL<7180> A_IWL<7179> A_IWL<7178> A_IWL<7177> A_IWL<7176> A_IWL<7175> A_IWL<7174> A_IWL<7173> A_IWL<7172> A_IWL<7171> A_IWL<7170> A_IWL<7169> A_IWL<7168> A_IWL<7679> A_IWL<7678> A_IWL<7677> A_IWL<7676> A_IWL<7675> A_IWL<7674> A_IWL<7673> A_IWL<7672> A_IWL<7671> A_IWL<7670> A_IWL<7669> A_IWL<7668> A_IWL<7667> A_IWL<7666> A_IWL<7665> A_IWL<7664> A_IWL<7663> A_IWL<7662> A_IWL<7661> A_IWL<7660> A_IWL<7659> A_IWL<7658> A_IWL<7657> A_IWL<7656> A_IWL<7655> A_IWL<7654> A_IWL<7653> A_IWL<7652> A_IWL<7651> A_IWL<7650> A_IWL<7649> A_IWL<7648> A_IWL<7647> A_IWL<7646> A_IWL<7645> A_IWL<7644> A_IWL<7643> A_IWL<7642> A_IWL<7641> A_IWL<7640> A_IWL<7639> A_IWL<7638> A_IWL<7637> A_IWL<7636> A_IWL<7635> A_IWL<7634> A_IWL<7633> A_IWL<7632> A_IWL<7631> A_IWL<7630> A_IWL<7629> A_IWL<7628> A_IWL<7627> A_IWL<7626> A_IWL<7625> A_IWL<7624> A_IWL<7623> A_IWL<7622> A_IWL<7621> A_IWL<7620> A_IWL<7619> A_IWL<7618> A_IWL<7617> A_IWL<7616> A_IWL<7615> A_IWL<7614> A_IWL<7613> A_IWL<7612> A_IWL<7611> A_IWL<7610> A_IWL<7609> A_IWL<7608> A_IWL<7607> A_IWL<7606> A_IWL<7605> A_IWL<7604> A_IWL<7603> A_IWL<7602> A_IWL<7601> A_IWL<7600> A_IWL<7599> A_IWL<7598> A_IWL<7597> A_IWL<7596> A_IWL<7595> A_IWL<7594> A_IWL<7593> A_IWL<7592> A_IWL<7591> A_IWL<7590> A_IWL<7589> A_IWL<7588> A_IWL<7587> A_IWL<7586> A_IWL<7585> A_IWL<7584> A_IWL<7583> A_IWL<7582> A_IWL<7581> A_IWL<7580> A_IWL<7579> A_IWL<7578> A_IWL<7577> A_IWL<7576> A_IWL<7575> A_IWL<7574> A_IWL<7573> A_IWL<7572> A_IWL<7571> A_IWL<7570> A_IWL<7569> A_IWL<7568> A_IWL<7567> A_IWL<7566> A_IWL<7565> A_IWL<7564> A_IWL<7563> A_IWL<7562> A_IWL<7561> A_IWL<7560> A_IWL<7559> A_IWL<7558> A_IWL<7557> A_IWL<7556> A_IWL<7555> A_IWL<7554> A_IWL<7553> A_IWL<7552> A_IWL<7551> A_IWL<7550> A_IWL<7549> A_IWL<7548> A_IWL<7547> A_IWL<7546> A_IWL<7545> A_IWL<7544> A_IWL<7543> A_IWL<7542> A_IWL<7541> A_IWL<7540> A_IWL<7539> A_IWL<7538> A_IWL<7537> A_IWL<7536> A_IWL<7535> A_IWL<7534> A_IWL<7533> A_IWL<7532> A_IWL<7531> A_IWL<7530> A_IWL<7529> A_IWL<7528> A_IWL<7527> A_IWL<7526> A_IWL<7525> A_IWL<7524> A_IWL<7523> A_IWL<7522> A_IWL<7521> A_IWL<7520> A_IWL<7519> A_IWL<7518> A_IWL<7517> A_IWL<7516> A_IWL<7515> A_IWL<7514> A_IWL<7513> A_IWL<7512> A_IWL<7511> A_IWL<7510> A_IWL<7509> A_IWL<7508> A_IWL<7507> A_IWL<7506> A_IWL<7505> A_IWL<7504> A_IWL<7503> A_IWL<7502> A_IWL<7501> A_IWL<7500> A_IWL<7499> A_IWL<7498> A_IWL<7497> A_IWL<7496> A_IWL<7495> A_IWL<7494> A_IWL<7493> A_IWL<7492> A_IWL<7491> A_IWL<7490> A_IWL<7489> A_IWL<7488> A_IWL<7487> A_IWL<7486> A_IWL<7485> A_IWL<7484> A_IWL<7483> A_IWL<7482> A_IWL<7481> A_IWL<7480> A_IWL<7479> A_IWL<7478> A_IWL<7477> A_IWL<7476> A_IWL<7475> A_IWL<7474> A_IWL<7473> A_IWL<7472> A_IWL<7471> A_IWL<7470> A_IWL<7469> A_IWL<7468> A_IWL<7467> A_IWL<7466> A_IWL<7465> A_IWL<7464> A_IWL<7463> A_IWL<7462> A_IWL<7461> A_IWL<7460> A_IWL<7459> A_IWL<7458> A_IWL<7457> A_IWL<7456> A_IWL<7455> A_IWL<7454> A_IWL<7453> A_IWL<7452> A_IWL<7451> A_IWL<7450> A_IWL<7449> A_IWL<7448> A_IWL<7447> A_IWL<7446> A_IWL<7445> A_IWL<7444> A_IWL<7443> A_IWL<7442> A_IWL<7441> A_IWL<7440> A_IWL<7439> A_IWL<7438> A_IWL<7437> A_IWL<7436> A_IWL<7435> A_IWL<7434> A_IWL<7433> A_IWL<7432> A_IWL<7431> A_IWL<7430> A_IWL<7429> A_IWL<7428> A_IWL<7427> A_IWL<7426> A_IWL<7425> A_IWL<7424> VDD_CORE VSS / RM_IHPSG13_1024x32_c2_1P_COLUMN_pcell_0 +XCOL<28> A_BLC<57> A_BLC<56> A_BLC_TOP<57> A_BLC_TOP<56> A_BLT<57> A_BLT<56> A_BLT_TOP<57> A_BLT_TOP<56> A_IWL<7167> A_IWL<7166> A_IWL<7165> A_IWL<7164> A_IWL<7163> A_IWL<7162> A_IWL<7161> A_IWL<7160> A_IWL<7159> A_IWL<7158> A_IWL<7157> A_IWL<7156> A_IWL<7155> A_IWL<7154> A_IWL<7153> A_IWL<7152> A_IWL<7151> A_IWL<7150> A_IWL<7149> A_IWL<7148> A_IWL<7147> A_IWL<7146> A_IWL<7145> A_IWL<7144> A_IWL<7143> A_IWL<7142> A_IWL<7141> A_IWL<7140> A_IWL<7139> A_IWL<7138> A_IWL<7137> A_IWL<7136> A_IWL<7135> A_IWL<7134> A_IWL<7133> A_IWL<7132> A_IWL<7131> A_IWL<7130> A_IWL<7129> A_IWL<7128> A_IWL<7127> A_IWL<7126> A_IWL<7125> A_IWL<7124> A_IWL<7123> A_IWL<7122> A_IWL<7121> A_IWL<7120> A_IWL<7119> A_IWL<7118> A_IWL<7117> A_IWL<7116> A_IWL<7115> A_IWL<7114> A_IWL<7113> A_IWL<7112> A_IWL<7111> A_IWL<7110> A_IWL<7109> A_IWL<7108> A_IWL<7107> A_IWL<7106> A_IWL<7105> A_IWL<7104> A_IWL<7103> A_IWL<7102> A_IWL<7101> A_IWL<7100> A_IWL<7099> A_IWL<7098> A_IWL<7097> A_IWL<7096> A_IWL<7095> A_IWL<7094> A_IWL<7093> A_IWL<7092> A_IWL<7091> A_IWL<7090> A_IWL<7089> A_IWL<7088> A_IWL<7087> A_IWL<7086> A_IWL<7085> A_IWL<7084> A_IWL<7083> A_IWL<7082> A_IWL<7081> A_IWL<7080> A_IWL<7079> A_IWL<7078> A_IWL<7077> A_IWL<7076> A_IWL<7075> A_IWL<7074> A_IWL<7073> A_IWL<7072> A_IWL<7071> A_IWL<7070> A_IWL<7069> A_IWL<7068> A_IWL<7067> A_IWL<7066> A_IWL<7065> A_IWL<7064> A_IWL<7063> A_IWL<7062> A_IWL<7061> A_IWL<7060> A_IWL<7059> A_IWL<7058> A_IWL<7057> A_IWL<7056> A_IWL<7055> A_IWL<7054> A_IWL<7053> A_IWL<7052> A_IWL<7051> A_IWL<7050> A_IWL<7049> A_IWL<7048> A_IWL<7047> A_IWL<7046> A_IWL<7045> A_IWL<7044> A_IWL<7043> A_IWL<7042> A_IWL<7041> A_IWL<7040> A_IWL<7039> A_IWL<7038> A_IWL<7037> A_IWL<7036> A_IWL<7035> A_IWL<7034> A_IWL<7033> A_IWL<7032> A_IWL<7031> A_IWL<7030> A_IWL<7029> A_IWL<7028> A_IWL<7027> A_IWL<7026> A_IWL<7025> A_IWL<7024> A_IWL<7023> A_IWL<7022> A_IWL<7021> A_IWL<7020> A_IWL<7019> A_IWL<7018> A_IWL<7017> A_IWL<7016> A_IWL<7015> A_IWL<7014> A_IWL<7013> A_IWL<7012> A_IWL<7011> A_IWL<7010> A_IWL<7009> A_IWL<7008> A_IWL<7007> A_IWL<7006> A_IWL<7005> A_IWL<7004> A_IWL<7003> A_IWL<7002> A_IWL<7001> A_IWL<7000> A_IWL<6999> A_IWL<6998> A_IWL<6997> A_IWL<6996> A_IWL<6995> A_IWL<6994> A_IWL<6993> A_IWL<6992> A_IWL<6991> A_IWL<6990> A_IWL<6989> A_IWL<6988> A_IWL<6987> A_IWL<6986> A_IWL<6985> A_IWL<6984> A_IWL<6983> A_IWL<6982> A_IWL<6981> A_IWL<6980> A_IWL<6979> A_IWL<6978> A_IWL<6977> A_IWL<6976> A_IWL<6975> A_IWL<6974> A_IWL<6973> A_IWL<6972> A_IWL<6971> A_IWL<6970> A_IWL<6969> A_IWL<6968> A_IWL<6967> A_IWL<6966> A_IWL<6965> A_IWL<6964> A_IWL<6963> A_IWL<6962> A_IWL<6961> A_IWL<6960> A_IWL<6959> A_IWL<6958> A_IWL<6957> A_IWL<6956> A_IWL<6955> A_IWL<6954> A_IWL<6953> A_IWL<6952> A_IWL<6951> A_IWL<6950> A_IWL<6949> A_IWL<6948> A_IWL<6947> A_IWL<6946> A_IWL<6945> A_IWL<6944> A_IWL<6943> A_IWL<6942> A_IWL<6941> A_IWL<6940> A_IWL<6939> A_IWL<6938> A_IWL<6937> A_IWL<6936> A_IWL<6935> A_IWL<6934> A_IWL<6933> A_IWL<6932> A_IWL<6931> A_IWL<6930> A_IWL<6929> A_IWL<6928> A_IWL<6927> A_IWL<6926> A_IWL<6925> A_IWL<6924> A_IWL<6923> A_IWL<6922> A_IWL<6921> A_IWL<6920> A_IWL<6919> A_IWL<6918> A_IWL<6917> A_IWL<6916> A_IWL<6915> A_IWL<6914> A_IWL<6913> A_IWL<6912> A_IWL<7423> A_IWL<7422> A_IWL<7421> A_IWL<7420> A_IWL<7419> A_IWL<7418> A_IWL<7417> A_IWL<7416> A_IWL<7415> A_IWL<7414> A_IWL<7413> A_IWL<7412> A_IWL<7411> A_IWL<7410> A_IWL<7409> A_IWL<7408> A_IWL<7407> A_IWL<7406> A_IWL<7405> A_IWL<7404> A_IWL<7403> A_IWL<7402> A_IWL<7401> A_IWL<7400> A_IWL<7399> A_IWL<7398> A_IWL<7397> A_IWL<7396> A_IWL<7395> A_IWL<7394> A_IWL<7393> A_IWL<7392> A_IWL<7391> A_IWL<7390> A_IWL<7389> A_IWL<7388> A_IWL<7387> A_IWL<7386> A_IWL<7385> A_IWL<7384> A_IWL<7383> A_IWL<7382> A_IWL<7381> A_IWL<7380> A_IWL<7379> A_IWL<7378> A_IWL<7377> A_IWL<7376> A_IWL<7375> A_IWL<7374> A_IWL<7373> A_IWL<7372> A_IWL<7371> A_IWL<7370> A_IWL<7369> A_IWL<7368> A_IWL<7367> A_IWL<7366> A_IWL<7365> A_IWL<7364> A_IWL<7363> A_IWL<7362> A_IWL<7361> A_IWL<7360> A_IWL<7359> A_IWL<7358> A_IWL<7357> A_IWL<7356> A_IWL<7355> A_IWL<7354> A_IWL<7353> A_IWL<7352> A_IWL<7351> A_IWL<7350> A_IWL<7349> A_IWL<7348> A_IWL<7347> A_IWL<7346> A_IWL<7345> A_IWL<7344> A_IWL<7343> A_IWL<7342> A_IWL<7341> A_IWL<7340> A_IWL<7339> A_IWL<7338> A_IWL<7337> A_IWL<7336> A_IWL<7335> A_IWL<7334> A_IWL<7333> A_IWL<7332> A_IWL<7331> A_IWL<7330> A_IWL<7329> A_IWL<7328> A_IWL<7327> A_IWL<7326> A_IWL<7325> A_IWL<7324> A_IWL<7323> A_IWL<7322> A_IWL<7321> A_IWL<7320> A_IWL<7319> A_IWL<7318> A_IWL<7317> A_IWL<7316> A_IWL<7315> A_IWL<7314> A_IWL<7313> A_IWL<7312> A_IWL<7311> A_IWL<7310> A_IWL<7309> A_IWL<7308> A_IWL<7307> A_IWL<7306> A_IWL<7305> A_IWL<7304> A_IWL<7303> A_IWL<7302> A_IWL<7301> A_IWL<7300> A_IWL<7299> A_IWL<7298> A_IWL<7297> A_IWL<7296> A_IWL<7295> A_IWL<7294> A_IWL<7293> A_IWL<7292> A_IWL<7291> A_IWL<7290> A_IWL<7289> A_IWL<7288> A_IWL<7287> A_IWL<7286> A_IWL<7285> A_IWL<7284> A_IWL<7283> A_IWL<7282> A_IWL<7281> A_IWL<7280> A_IWL<7279> A_IWL<7278> A_IWL<7277> A_IWL<7276> A_IWL<7275> A_IWL<7274> A_IWL<7273> A_IWL<7272> A_IWL<7271> A_IWL<7270> A_IWL<7269> A_IWL<7268> A_IWL<7267> A_IWL<7266> A_IWL<7265> A_IWL<7264> A_IWL<7263> A_IWL<7262> A_IWL<7261> A_IWL<7260> A_IWL<7259> A_IWL<7258> A_IWL<7257> A_IWL<7256> A_IWL<7255> A_IWL<7254> A_IWL<7253> A_IWL<7252> A_IWL<7251> A_IWL<7250> A_IWL<7249> A_IWL<7248> A_IWL<7247> A_IWL<7246> A_IWL<7245> A_IWL<7244> A_IWL<7243> A_IWL<7242> A_IWL<7241> A_IWL<7240> A_IWL<7239> A_IWL<7238> A_IWL<7237> A_IWL<7236> A_IWL<7235> A_IWL<7234> A_IWL<7233> A_IWL<7232> A_IWL<7231> A_IWL<7230> A_IWL<7229> A_IWL<7228> A_IWL<7227> A_IWL<7226> A_IWL<7225> A_IWL<7224> A_IWL<7223> A_IWL<7222> A_IWL<7221> A_IWL<7220> A_IWL<7219> A_IWL<7218> A_IWL<7217> A_IWL<7216> A_IWL<7215> A_IWL<7214> A_IWL<7213> A_IWL<7212> A_IWL<7211> A_IWL<7210> A_IWL<7209> A_IWL<7208> A_IWL<7207> A_IWL<7206> A_IWL<7205> A_IWL<7204> A_IWL<7203> A_IWL<7202> A_IWL<7201> A_IWL<7200> A_IWL<7199> A_IWL<7198> A_IWL<7197> A_IWL<7196> A_IWL<7195> A_IWL<7194> A_IWL<7193> A_IWL<7192> A_IWL<7191> A_IWL<7190> A_IWL<7189> A_IWL<7188> A_IWL<7187> A_IWL<7186> A_IWL<7185> A_IWL<7184> A_IWL<7183> A_IWL<7182> A_IWL<7181> A_IWL<7180> A_IWL<7179> A_IWL<7178> A_IWL<7177> A_IWL<7176> A_IWL<7175> A_IWL<7174> A_IWL<7173> A_IWL<7172> A_IWL<7171> A_IWL<7170> A_IWL<7169> A_IWL<7168> VDD_CORE VSS / RM_IHPSG13_1024x32_c2_1P_COLUMN_pcell_0 +XCOL<27> A_BLC<55> A_BLC<54> A_BLC_TOP<55> A_BLC_TOP<54> A_BLT<55> A_BLT<54> A_BLT_TOP<55> A_BLT_TOP<54> A_IWL<6911> A_IWL<6910> A_IWL<6909> A_IWL<6908> A_IWL<6907> A_IWL<6906> A_IWL<6905> A_IWL<6904> A_IWL<6903> A_IWL<6902> A_IWL<6901> A_IWL<6900> A_IWL<6899> A_IWL<6898> A_IWL<6897> A_IWL<6896> A_IWL<6895> A_IWL<6894> A_IWL<6893> A_IWL<6892> A_IWL<6891> A_IWL<6890> A_IWL<6889> A_IWL<6888> A_IWL<6887> A_IWL<6886> A_IWL<6885> A_IWL<6884> A_IWL<6883> A_IWL<6882> A_IWL<6881> A_IWL<6880> A_IWL<6879> A_IWL<6878> A_IWL<6877> A_IWL<6876> A_IWL<6875> A_IWL<6874> A_IWL<6873> A_IWL<6872> A_IWL<6871> A_IWL<6870> A_IWL<6869> A_IWL<6868> A_IWL<6867> A_IWL<6866> A_IWL<6865> A_IWL<6864> A_IWL<6863> A_IWL<6862> A_IWL<6861> A_IWL<6860> A_IWL<6859> A_IWL<6858> A_IWL<6857> A_IWL<6856> A_IWL<6855> A_IWL<6854> A_IWL<6853> A_IWL<6852> A_IWL<6851> A_IWL<6850> A_IWL<6849> A_IWL<6848> A_IWL<6847> A_IWL<6846> A_IWL<6845> A_IWL<6844> A_IWL<6843> A_IWL<6842> A_IWL<6841> A_IWL<6840> A_IWL<6839> A_IWL<6838> A_IWL<6837> A_IWL<6836> A_IWL<6835> A_IWL<6834> A_IWL<6833> A_IWL<6832> A_IWL<6831> A_IWL<6830> A_IWL<6829> A_IWL<6828> A_IWL<6827> A_IWL<6826> A_IWL<6825> A_IWL<6824> A_IWL<6823> A_IWL<6822> A_IWL<6821> A_IWL<6820> A_IWL<6819> A_IWL<6818> A_IWL<6817> A_IWL<6816> A_IWL<6815> A_IWL<6814> A_IWL<6813> A_IWL<6812> A_IWL<6811> A_IWL<6810> A_IWL<6809> A_IWL<6808> A_IWL<6807> A_IWL<6806> A_IWL<6805> A_IWL<6804> A_IWL<6803> A_IWL<6802> A_IWL<6801> A_IWL<6800> A_IWL<6799> A_IWL<6798> A_IWL<6797> A_IWL<6796> A_IWL<6795> A_IWL<6794> A_IWL<6793> A_IWL<6792> A_IWL<6791> A_IWL<6790> A_IWL<6789> A_IWL<6788> A_IWL<6787> A_IWL<6786> A_IWL<6785> A_IWL<6784> A_IWL<6783> A_IWL<6782> A_IWL<6781> A_IWL<6780> A_IWL<6779> A_IWL<6778> A_IWL<6777> A_IWL<6776> A_IWL<6775> A_IWL<6774> A_IWL<6773> A_IWL<6772> A_IWL<6771> A_IWL<6770> A_IWL<6769> A_IWL<6768> A_IWL<6767> A_IWL<6766> A_IWL<6765> A_IWL<6764> A_IWL<6763> A_IWL<6762> A_IWL<6761> A_IWL<6760> A_IWL<6759> A_IWL<6758> A_IWL<6757> A_IWL<6756> A_IWL<6755> A_IWL<6754> A_IWL<6753> A_IWL<6752> A_IWL<6751> A_IWL<6750> A_IWL<6749> A_IWL<6748> A_IWL<6747> A_IWL<6746> A_IWL<6745> A_IWL<6744> A_IWL<6743> A_IWL<6742> A_IWL<6741> A_IWL<6740> A_IWL<6739> A_IWL<6738> A_IWL<6737> A_IWL<6736> A_IWL<6735> A_IWL<6734> A_IWL<6733> A_IWL<6732> A_IWL<6731> A_IWL<6730> A_IWL<6729> A_IWL<6728> A_IWL<6727> A_IWL<6726> A_IWL<6725> A_IWL<6724> A_IWL<6723> A_IWL<6722> A_IWL<6721> A_IWL<6720> A_IWL<6719> A_IWL<6718> A_IWL<6717> A_IWL<6716> A_IWL<6715> A_IWL<6714> A_IWL<6713> A_IWL<6712> A_IWL<6711> A_IWL<6710> A_IWL<6709> A_IWL<6708> A_IWL<6707> A_IWL<6706> A_IWL<6705> A_IWL<6704> A_IWL<6703> A_IWL<6702> A_IWL<6701> A_IWL<6700> A_IWL<6699> A_IWL<6698> A_IWL<6697> A_IWL<6696> A_IWL<6695> A_IWL<6694> A_IWL<6693> A_IWL<6692> A_IWL<6691> A_IWL<6690> A_IWL<6689> A_IWL<6688> A_IWL<6687> A_IWL<6686> A_IWL<6685> A_IWL<6684> A_IWL<6683> A_IWL<6682> A_IWL<6681> A_IWL<6680> A_IWL<6679> A_IWL<6678> A_IWL<6677> A_IWL<6676> A_IWL<6675> A_IWL<6674> A_IWL<6673> A_IWL<6672> A_IWL<6671> A_IWL<6670> A_IWL<6669> A_IWL<6668> A_IWL<6667> A_IWL<6666> A_IWL<6665> A_IWL<6664> A_IWL<6663> A_IWL<6662> A_IWL<6661> A_IWL<6660> A_IWL<6659> A_IWL<6658> A_IWL<6657> A_IWL<6656> A_IWL<7167> A_IWL<7166> A_IWL<7165> A_IWL<7164> A_IWL<7163> A_IWL<7162> A_IWL<7161> A_IWL<7160> A_IWL<7159> A_IWL<7158> A_IWL<7157> A_IWL<7156> A_IWL<7155> A_IWL<7154> A_IWL<7153> A_IWL<7152> A_IWL<7151> A_IWL<7150> A_IWL<7149> A_IWL<7148> A_IWL<7147> A_IWL<7146> A_IWL<7145> A_IWL<7144> A_IWL<7143> A_IWL<7142> A_IWL<7141> A_IWL<7140> A_IWL<7139> A_IWL<7138> A_IWL<7137> A_IWL<7136> A_IWL<7135> A_IWL<7134> A_IWL<7133> A_IWL<7132> A_IWL<7131> A_IWL<7130> A_IWL<7129> A_IWL<7128> A_IWL<7127> A_IWL<7126> A_IWL<7125> A_IWL<7124> A_IWL<7123> A_IWL<7122> A_IWL<7121> A_IWL<7120> A_IWL<7119> A_IWL<7118> A_IWL<7117> A_IWL<7116> A_IWL<7115> A_IWL<7114> A_IWL<7113> A_IWL<7112> A_IWL<7111> A_IWL<7110> A_IWL<7109> A_IWL<7108> A_IWL<7107> A_IWL<7106> A_IWL<7105> A_IWL<7104> A_IWL<7103> A_IWL<7102> A_IWL<7101> A_IWL<7100> A_IWL<7099> A_IWL<7098> A_IWL<7097> A_IWL<7096> A_IWL<7095> A_IWL<7094> A_IWL<7093> A_IWL<7092> A_IWL<7091> A_IWL<7090> A_IWL<7089> A_IWL<7088> A_IWL<7087> A_IWL<7086> A_IWL<7085> A_IWL<7084> A_IWL<7083> A_IWL<7082> A_IWL<7081> A_IWL<7080> A_IWL<7079> A_IWL<7078> A_IWL<7077> A_IWL<7076> A_IWL<7075> A_IWL<7074> A_IWL<7073> A_IWL<7072> A_IWL<7071> A_IWL<7070> A_IWL<7069> A_IWL<7068> A_IWL<7067> A_IWL<7066> A_IWL<7065> A_IWL<7064> A_IWL<7063> A_IWL<7062> A_IWL<7061> A_IWL<7060> A_IWL<7059> A_IWL<7058> A_IWL<7057> A_IWL<7056> A_IWL<7055> A_IWL<7054> A_IWL<7053> A_IWL<7052> A_IWL<7051> A_IWL<7050> A_IWL<7049> A_IWL<7048> A_IWL<7047> A_IWL<7046> A_IWL<7045> A_IWL<7044> A_IWL<7043> A_IWL<7042> A_IWL<7041> A_IWL<7040> A_IWL<7039> A_IWL<7038> A_IWL<7037> A_IWL<7036> A_IWL<7035> A_IWL<7034> A_IWL<7033> A_IWL<7032> A_IWL<7031> A_IWL<7030> A_IWL<7029> A_IWL<7028> A_IWL<7027> A_IWL<7026> A_IWL<7025> A_IWL<7024> A_IWL<7023> A_IWL<7022> A_IWL<7021> A_IWL<7020> A_IWL<7019> A_IWL<7018> A_IWL<7017> A_IWL<7016> A_IWL<7015> A_IWL<7014> A_IWL<7013> A_IWL<7012> A_IWL<7011> A_IWL<7010> A_IWL<7009> A_IWL<7008> A_IWL<7007> A_IWL<7006> A_IWL<7005> A_IWL<7004> A_IWL<7003> A_IWL<7002> A_IWL<7001> A_IWL<7000> A_IWL<6999> A_IWL<6998> A_IWL<6997> A_IWL<6996> A_IWL<6995> A_IWL<6994> A_IWL<6993> A_IWL<6992> A_IWL<6991> A_IWL<6990> A_IWL<6989> A_IWL<6988> A_IWL<6987> A_IWL<6986> A_IWL<6985> A_IWL<6984> A_IWL<6983> A_IWL<6982> A_IWL<6981> A_IWL<6980> A_IWL<6979> A_IWL<6978> A_IWL<6977> A_IWL<6976> A_IWL<6975> A_IWL<6974> A_IWL<6973> A_IWL<6972> A_IWL<6971> A_IWL<6970> A_IWL<6969> A_IWL<6968> A_IWL<6967> A_IWL<6966> A_IWL<6965> A_IWL<6964> A_IWL<6963> A_IWL<6962> A_IWL<6961> A_IWL<6960> A_IWL<6959> A_IWL<6958> A_IWL<6957> A_IWL<6956> A_IWL<6955> A_IWL<6954> A_IWL<6953> A_IWL<6952> A_IWL<6951> A_IWL<6950> A_IWL<6949> A_IWL<6948> A_IWL<6947> A_IWL<6946> A_IWL<6945> A_IWL<6944> A_IWL<6943> A_IWL<6942> A_IWL<6941> A_IWL<6940> A_IWL<6939> A_IWL<6938> A_IWL<6937> A_IWL<6936> A_IWL<6935> A_IWL<6934> A_IWL<6933> A_IWL<6932> A_IWL<6931> A_IWL<6930> A_IWL<6929> A_IWL<6928> A_IWL<6927> A_IWL<6926> A_IWL<6925> A_IWL<6924> A_IWL<6923> A_IWL<6922> A_IWL<6921> A_IWL<6920> A_IWL<6919> A_IWL<6918> A_IWL<6917> A_IWL<6916> A_IWL<6915> A_IWL<6914> A_IWL<6913> A_IWL<6912> VDD_CORE VSS / RM_IHPSG13_1024x32_c2_1P_COLUMN_pcell_0 +XCOL<26> A_BLC<53> A_BLC<52> A_BLC_TOP<53> A_BLC_TOP<52> A_BLT<53> A_BLT<52> A_BLT_TOP<53> A_BLT_TOP<52> A_IWL<6655> A_IWL<6654> A_IWL<6653> A_IWL<6652> A_IWL<6651> A_IWL<6650> A_IWL<6649> A_IWL<6648> A_IWL<6647> A_IWL<6646> A_IWL<6645> A_IWL<6644> A_IWL<6643> A_IWL<6642> A_IWL<6641> A_IWL<6640> A_IWL<6639> A_IWL<6638> A_IWL<6637> A_IWL<6636> A_IWL<6635> A_IWL<6634> A_IWL<6633> A_IWL<6632> A_IWL<6631> A_IWL<6630> A_IWL<6629> A_IWL<6628> A_IWL<6627> A_IWL<6626> A_IWL<6625> A_IWL<6624> A_IWL<6623> A_IWL<6622> A_IWL<6621> A_IWL<6620> A_IWL<6619> A_IWL<6618> A_IWL<6617> A_IWL<6616> A_IWL<6615> A_IWL<6614> A_IWL<6613> A_IWL<6612> A_IWL<6611> A_IWL<6610> A_IWL<6609> A_IWL<6608> A_IWL<6607> A_IWL<6606> A_IWL<6605> A_IWL<6604> A_IWL<6603> A_IWL<6602> A_IWL<6601> A_IWL<6600> A_IWL<6599> A_IWL<6598> A_IWL<6597> A_IWL<6596> A_IWL<6595> A_IWL<6594> A_IWL<6593> A_IWL<6592> A_IWL<6591> A_IWL<6590> A_IWL<6589> A_IWL<6588> A_IWL<6587> A_IWL<6586> A_IWL<6585> A_IWL<6584> A_IWL<6583> A_IWL<6582> A_IWL<6581> A_IWL<6580> A_IWL<6579> A_IWL<6578> A_IWL<6577> A_IWL<6576> A_IWL<6575> A_IWL<6574> A_IWL<6573> A_IWL<6572> A_IWL<6571> A_IWL<6570> A_IWL<6569> A_IWL<6568> A_IWL<6567> A_IWL<6566> A_IWL<6565> A_IWL<6564> A_IWL<6563> A_IWL<6562> A_IWL<6561> A_IWL<6560> A_IWL<6559> A_IWL<6558> A_IWL<6557> A_IWL<6556> A_IWL<6555> A_IWL<6554> A_IWL<6553> A_IWL<6552> A_IWL<6551> A_IWL<6550> A_IWL<6549> A_IWL<6548> A_IWL<6547> A_IWL<6546> A_IWL<6545> A_IWL<6544> A_IWL<6543> A_IWL<6542> A_IWL<6541> A_IWL<6540> A_IWL<6539> A_IWL<6538> A_IWL<6537> A_IWL<6536> A_IWL<6535> A_IWL<6534> A_IWL<6533> A_IWL<6532> A_IWL<6531> A_IWL<6530> A_IWL<6529> A_IWL<6528> A_IWL<6527> A_IWL<6526> A_IWL<6525> A_IWL<6524> A_IWL<6523> A_IWL<6522> A_IWL<6521> A_IWL<6520> A_IWL<6519> A_IWL<6518> A_IWL<6517> A_IWL<6516> A_IWL<6515> A_IWL<6514> A_IWL<6513> A_IWL<6512> A_IWL<6511> A_IWL<6510> A_IWL<6509> A_IWL<6508> A_IWL<6507> A_IWL<6506> A_IWL<6505> A_IWL<6504> A_IWL<6503> A_IWL<6502> A_IWL<6501> A_IWL<6500> A_IWL<6499> A_IWL<6498> A_IWL<6497> A_IWL<6496> A_IWL<6495> A_IWL<6494> A_IWL<6493> A_IWL<6492> A_IWL<6491> A_IWL<6490> A_IWL<6489> A_IWL<6488> A_IWL<6487> A_IWL<6486> A_IWL<6485> A_IWL<6484> A_IWL<6483> A_IWL<6482> A_IWL<6481> A_IWL<6480> A_IWL<6479> A_IWL<6478> A_IWL<6477> A_IWL<6476> A_IWL<6475> A_IWL<6474> A_IWL<6473> A_IWL<6472> A_IWL<6471> A_IWL<6470> A_IWL<6469> A_IWL<6468> A_IWL<6467> A_IWL<6466> A_IWL<6465> A_IWL<6464> A_IWL<6463> A_IWL<6462> A_IWL<6461> A_IWL<6460> A_IWL<6459> A_IWL<6458> A_IWL<6457> A_IWL<6456> A_IWL<6455> A_IWL<6454> A_IWL<6453> A_IWL<6452> A_IWL<6451> A_IWL<6450> A_IWL<6449> A_IWL<6448> A_IWL<6447> A_IWL<6446> A_IWL<6445> A_IWL<6444> A_IWL<6443> A_IWL<6442> A_IWL<6441> A_IWL<6440> A_IWL<6439> A_IWL<6438> A_IWL<6437> A_IWL<6436> A_IWL<6435> A_IWL<6434> A_IWL<6433> A_IWL<6432> A_IWL<6431> A_IWL<6430> A_IWL<6429> A_IWL<6428> A_IWL<6427> A_IWL<6426> A_IWL<6425> A_IWL<6424> A_IWL<6423> A_IWL<6422> A_IWL<6421> A_IWL<6420> A_IWL<6419> A_IWL<6418> A_IWL<6417> A_IWL<6416> A_IWL<6415> A_IWL<6414> A_IWL<6413> A_IWL<6412> A_IWL<6411> A_IWL<6410> A_IWL<6409> A_IWL<6408> A_IWL<6407> A_IWL<6406> A_IWL<6405> A_IWL<6404> A_IWL<6403> A_IWL<6402> A_IWL<6401> A_IWL<6400> A_IWL<6911> A_IWL<6910> A_IWL<6909> A_IWL<6908> A_IWL<6907> A_IWL<6906> A_IWL<6905> A_IWL<6904> A_IWL<6903> A_IWL<6902> A_IWL<6901> A_IWL<6900> A_IWL<6899> A_IWL<6898> A_IWL<6897> A_IWL<6896> A_IWL<6895> A_IWL<6894> A_IWL<6893> A_IWL<6892> A_IWL<6891> A_IWL<6890> A_IWL<6889> A_IWL<6888> A_IWL<6887> A_IWL<6886> A_IWL<6885> A_IWL<6884> A_IWL<6883> A_IWL<6882> A_IWL<6881> A_IWL<6880> A_IWL<6879> A_IWL<6878> A_IWL<6877> A_IWL<6876> A_IWL<6875> A_IWL<6874> A_IWL<6873> A_IWL<6872> A_IWL<6871> A_IWL<6870> A_IWL<6869> A_IWL<6868> A_IWL<6867> A_IWL<6866> A_IWL<6865> A_IWL<6864> A_IWL<6863> A_IWL<6862> A_IWL<6861> A_IWL<6860> A_IWL<6859> A_IWL<6858> A_IWL<6857> A_IWL<6856> A_IWL<6855> A_IWL<6854> A_IWL<6853> A_IWL<6852> A_IWL<6851> A_IWL<6850> A_IWL<6849> A_IWL<6848> A_IWL<6847> A_IWL<6846> A_IWL<6845> A_IWL<6844> A_IWL<6843> A_IWL<6842> A_IWL<6841> A_IWL<6840> A_IWL<6839> A_IWL<6838> A_IWL<6837> A_IWL<6836> A_IWL<6835> A_IWL<6834> A_IWL<6833> A_IWL<6832> A_IWL<6831> A_IWL<6830> A_IWL<6829> A_IWL<6828> A_IWL<6827> A_IWL<6826> A_IWL<6825> A_IWL<6824> A_IWL<6823> A_IWL<6822> A_IWL<6821> A_IWL<6820> A_IWL<6819> A_IWL<6818> A_IWL<6817> A_IWL<6816> A_IWL<6815> A_IWL<6814> A_IWL<6813> A_IWL<6812> A_IWL<6811> A_IWL<6810> A_IWL<6809> A_IWL<6808> A_IWL<6807> A_IWL<6806> A_IWL<6805> A_IWL<6804> A_IWL<6803> A_IWL<6802> A_IWL<6801> A_IWL<6800> A_IWL<6799> A_IWL<6798> A_IWL<6797> A_IWL<6796> A_IWL<6795> A_IWL<6794> A_IWL<6793> A_IWL<6792> A_IWL<6791> A_IWL<6790> A_IWL<6789> A_IWL<6788> A_IWL<6787> A_IWL<6786> A_IWL<6785> A_IWL<6784> A_IWL<6783> A_IWL<6782> A_IWL<6781> A_IWL<6780> A_IWL<6779> A_IWL<6778> A_IWL<6777> A_IWL<6776> A_IWL<6775> A_IWL<6774> A_IWL<6773> A_IWL<6772> A_IWL<6771> A_IWL<6770> A_IWL<6769> A_IWL<6768> A_IWL<6767> A_IWL<6766> A_IWL<6765> A_IWL<6764> A_IWL<6763> A_IWL<6762> A_IWL<6761> A_IWL<6760> A_IWL<6759> A_IWL<6758> A_IWL<6757> A_IWL<6756> A_IWL<6755> A_IWL<6754> A_IWL<6753> A_IWL<6752> A_IWL<6751> A_IWL<6750> A_IWL<6749> A_IWL<6748> A_IWL<6747> A_IWL<6746> A_IWL<6745> A_IWL<6744> A_IWL<6743> A_IWL<6742> A_IWL<6741> A_IWL<6740> A_IWL<6739> A_IWL<6738> A_IWL<6737> A_IWL<6736> A_IWL<6735> A_IWL<6734> A_IWL<6733> A_IWL<6732> A_IWL<6731> A_IWL<6730> A_IWL<6729> A_IWL<6728> A_IWL<6727> A_IWL<6726> A_IWL<6725> A_IWL<6724> A_IWL<6723> A_IWL<6722> A_IWL<6721> A_IWL<6720> A_IWL<6719> A_IWL<6718> A_IWL<6717> A_IWL<6716> A_IWL<6715> A_IWL<6714> A_IWL<6713> A_IWL<6712> A_IWL<6711> A_IWL<6710> A_IWL<6709> A_IWL<6708> A_IWL<6707> A_IWL<6706> A_IWL<6705> A_IWL<6704> A_IWL<6703> A_IWL<6702> A_IWL<6701> A_IWL<6700> A_IWL<6699> A_IWL<6698> A_IWL<6697> A_IWL<6696> A_IWL<6695> A_IWL<6694> A_IWL<6693> A_IWL<6692> A_IWL<6691> A_IWL<6690> A_IWL<6689> A_IWL<6688> A_IWL<6687> A_IWL<6686> A_IWL<6685> A_IWL<6684> A_IWL<6683> A_IWL<6682> A_IWL<6681> A_IWL<6680> A_IWL<6679> A_IWL<6678> A_IWL<6677> A_IWL<6676> A_IWL<6675> A_IWL<6674> A_IWL<6673> A_IWL<6672> A_IWL<6671> A_IWL<6670> A_IWL<6669> A_IWL<6668> A_IWL<6667> A_IWL<6666> A_IWL<6665> A_IWL<6664> A_IWL<6663> A_IWL<6662> A_IWL<6661> A_IWL<6660> A_IWL<6659> A_IWL<6658> A_IWL<6657> A_IWL<6656> VDD_CORE VSS / RM_IHPSG13_1024x32_c2_1P_COLUMN_pcell_0 +XCOL<25> A_BLC<51> A_BLC<50> A_BLC_TOP<51> A_BLC_TOP<50> A_BLT<51> A_BLT<50> A_BLT_TOP<51> A_BLT_TOP<50> A_IWL<6399> A_IWL<6398> A_IWL<6397> A_IWL<6396> A_IWL<6395> A_IWL<6394> A_IWL<6393> A_IWL<6392> A_IWL<6391> A_IWL<6390> A_IWL<6389> A_IWL<6388> A_IWL<6387> A_IWL<6386> A_IWL<6385> A_IWL<6384> A_IWL<6383> A_IWL<6382> A_IWL<6381> A_IWL<6380> A_IWL<6379> A_IWL<6378> A_IWL<6377> A_IWL<6376> A_IWL<6375> A_IWL<6374> A_IWL<6373> A_IWL<6372> A_IWL<6371> A_IWL<6370> A_IWL<6369> A_IWL<6368> A_IWL<6367> A_IWL<6366> A_IWL<6365> A_IWL<6364> A_IWL<6363> A_IWL<6362> A_IWL<6361> A_IWL<6360> A_IWL<6359> A_IWL<6358> A_IWL<6357> A_IWL<6356> A_IWL<6355> A_IWL<6354> A_IWL<6353> A_IWL<6352> A_IWL<6351> A_IWL<6350> A_IWL<6349> A_IWL<6348> A_IWL<6347> A_IWL<6346> A_IWL<6345> A_IWL<6344> A_IWL<6343> A_IWL<6342> A_IWL<6341> A_IWL<6340> A_IWL<6339> A_IWL<6338> A_IWL<6337> A_IWL<6336> A_IWL<6335> A_IWL<6334> A_IWL<6333> A_IWL<6332> A_IWL<6331> A_IWL<6330> A_IWL<6329> A_IWL<6328> A_IWL<6327> A_IWL<6326> A_IWL<6325> A_IWL<6324> A_IWL<6323> A_IWL<6322> A_IWL<6321> A_IWL<6320> A_IWL<6319> A_IWL<6318> A_IWL<6317> A_IWL<6316> A_IWL<6315> A_IWL<6314> A_IWL<6313> A_IWL<6312> A_IWL<6311> A_IWL<6310> A_IWL<6309> A_IWL<6308> A_IWL<6307> A_IWL<6306> A_IWL<6305> A_IWL<6304> A_IWL<6303> A_IWL<6302> A_IWL<6301> A_IWL<6300> A_IWL<6299> A_IWL<6298> A_IWL<6297> A_IWL<6296> A_IWL<6295> A_IWL<6294> A_IWL<6293> A_IWL<6292> A_IWL<6291> A_IWL<6290> A_IWL<6289> A_IWL<6288> A_IWL<6287> A_IWL<6286> A_IWL<6285> A_IWL<6284> A_IWL<6283> A_IWL<6282> A_IWL<6281> A_IWL<6280> A_IWL<6279> A_IWL<6278> A_IWL<6277> A_IWL<6276> A_IWL<6275> A_IWL<6274> A_IWL<6273> A_IWL<6272> A_IWL<6271> A_IWL<6270> A_IWL<6269> A_IWL<6268> A_IWL<6267> A_IWL<6266> A_IWL<6265> A_IWL<6264> A_IWL<6263> A_IWL<6262> A_IWL<6261> A_IWL<6260> A_IWL<6259> A_IWL<6258> A_IWL<6257> A_IWL<6256> A_IWL<6255> A_IWL<6254> A_IWL<6253> A_IWL<6252> A_IWL<6251> A_IWL<6250> A_IWL<6249> A_IWL<6248> A_IWL<6247> A_IWL<6246> A_IWL<6245> A_IWL<6244> A_IWL<6243> A_IWL<6242> A_IWL<6241> A_IWL<6240> A_IWL<6239> A_IWL<6238> A_IWL<6237> A_IWL<6236> A_IWL<6235> A_IWL<6234> A_IWL<6233> A_IWL<6232> A_IWL<6231> A_IWL<6230> A_IWL<6229> A_IWL<6228> A_IWL<6227> A_IWL<6226> A_IWL<6225> A_IWL<6224> A_IWL<6223> A_IWL<6222> A_IWL<6221> A_IWL<6220> A_IWL<6219> A_IWL<6218> A_IWL<6217> A_IWL<6216> A_IWL<6215> A_IWL<6214> A_IWL<6213> A_IWL<6212> A_IWL<6211> A_IWL<6210> A_IWL<6209> A_IWL<6208> A_IWL<6207> A_IWL<6206> A_IWL<6205> A_IWL<6204> A_IWL<6203> A_IWL<6202> A_IWL<6201> A_IWL<6200> A_IWL<6199> A_IWL<6198> A_IWL<6197> A_IWL<6196> A_IWL<6195> A_IWL<6194> A_IWL<6193> A_IWL<6192> A_IWL<6191> A_IWL<6190> A_IWL<6189> A_IWL<6188> A_IWL<6187> A_IWL<6186> A_IWL<6185> A_IWL<6184> A_IWL<6183> A_IWL<6182> A_IWL<6181> A_IWL<6180> A_IWL<6179> A_IWL<6178> A_IWL<6177> A_IWL<6176> A_IWL<6175> A_IWL<6174> A_IWL<6173> A_IWL<6172> A_IWL<6171> A_IWL<6170> A_IWL<6169> A_IWL<6168> A_IWL<6167> A_IWL<6166> A_IWL<6165> A_IWL<6164> A_IWL<6163> A_IWL<6162> A_IWL<6161> A_IWL<6160> A_IWL<6159> A_IWL<6158> A_IWL<6157> A_IWL<6156> A_IWL<6155> A_IWL<6154> A_IWL<6153> A_IWL<6152> A_IWL<6151> A_IWL<6150> A_IWL<6149> A_IWL<6148> A_IWL<6147> A_IWL<6146> A_IWL<6145> A_IWL<6144> A_IWL<6655> A_IWL<6654> A_IWL<6653> A_IWL<6652> A_IWL<6651> A_IWL<6650> A_IWL<6649> A_IWL<6648> A_IWL<6647> A_IWL<6646> A_IWL<6645> A_IWL<6644> A_IWL<6643> A_IWL<6642> A_IWL<6641> A_IWL<6640> A_IWL<6639> A_IWL<6638> A_IWL<6637> A_IWL<6636> A_IWL<6635> A_IWL<6634> A_IWL<6633> A_IWL<6632> A_IWL<6631> A_IWL<6630> A_IWL<6629> A_IWL<6628> A_IWL<6627> A_IWL<6626> A_IWL<6625> A_IWL<6624> A_IWL<6623> A_IWL<6622> A_IWL<6621> A_IWL<6620> A_IWL<6619> A_IWL<6618> A_IWL<6617> A_IWL<6616> A_IWL<6615> A_IWL<6614> A_IWL<6613> A_IWL<6612> A_IWL<6611> A_IWL<6610> A_IWL<6609> A_IWL<6608> A_IWL<6607> A_IWL<6606> A_IWL<6605> A_IWL<6604> A_IWL<6603> A_IWL<6602> A_IWL<6601> A_IWL<6600> A_IWL<6599> A_IWL<6598> A_IWL<6597> A_IWL<6596> A_IWL<6595> A_IWL<6594> A_IWL<6593> A_IWL<6592> A_IWL<6591> A_IWL<6590> A_IWL<6589> A_IWL<6588> A_IWL<6587> A_IWL<6586> A_IWL<6585> A_IWL<6584> A_IWL<6583> A_IWL<6582> A_IWL<6581> A_IWL<6580> A_IWL<6579> A_IWL<6578> A_IWL<6577> A_IWL<6576> A_IWL<6575> A_IWL<6574> A_IWL<6573> A_IWL<6572> A_IWL<6571> A_IWL<6570> A_IWL<6569> A_IWL<6568> A_IWL<6567> A_IWL<6566> A_IWL<6565> A_IWL<6564> A_IWL<6563> A_IWL<6562> A_IWL<6561> A_IWL<6560> A_IWL<6559> A_IWL<6558> A_IWL<6557> A_IWL<6556> A_IWL<6555> A_IWL<6554> A_IWL<6553> A_IWL<6552> A_IWL<6551> A_IWL<6550> A_IWL<6549> A_IWL<6548> A_IWL<6547> A_IWL<6546> A_IWL<6545> A_IWL<6544> A_IWL<6543> A_IWL<6542> A_IWL<6541> A_IWL<6540> A_IWL<6539> A_IWL<6538> A_IWL<6537> A_IWL<6536> A_IWL<6535> A_IWL<6534> A_IWL<6533> A_IWL<6532> A_IWL<6531> A_IWL<6530> A_IWL<6529> A_IWL<6528> A_IWL<6527> A_IWL<6526> A_IWL<6525> A_IWL<6524> A_IWL<6523> A_IWL<6522> A_IWL<6521> A_IWL<6520> A_IWL<6519> A_IWL<6518> A_IWL<6517> A_IWL<6516> A_IWL<6515> A_IWL<6514> A_IWL<6513> A_IWL<6512> A_IWL<6511> A_IWL<6510> A_IWL<6509> A_IWL<6508> A_IWL<6507> A_IWL<6506> A_IWL<6505> A_IWL<6504> A_IWL<6503> A_IWL<6502> A_IWL<6501> A_IWL<6500> A_IWL<6499> A_IWL<6498> A_IWL<6497> A_IWL<6496> A_IWL<6495> A_IWL<6494> A_IWL<6493> A_IWL<6492> A_IWL<6491> A_IWL<6490> A_IWL<6489> A_IWL<6488> A_IWL<6487> A_IWL<6486> A_IWL<6485> A_IWL<6484> A_IWL<6483> A_IWL<6482> A_IWL<6481> A_IWL<6480> A_IWL<6479> A_IWL<6478> A_IWL<6477> A_IWL<6476> A_IWL<6475> A_IWL<6474> A_IWL<6473> A_IWL<6472> A_IWL<6471> A_IWL<6470> A_IWL<6469> A_IWL<6468> A_IWL<6467> A_IWL<6466> A_IWL<6465> A_IWL<6464> A_IWL<6463> A_IWL<6462> A_IWL<6461> A_IWL<6460> A_IWL<6459> A_IWL<6458> A_IWL<6457> A_IWL<6456> A_IWL<6455> A_IWL<6454> A_IWL<6453> A_IWL<6452> A_IWL<6451> A_IWL<6450> A_IWL<6449> A_IWL<6448> A_IWL<6447> A_IWL<6446> A_IWL<6445> A_IWL<6444> A_IWL<6443> A_IWL<6442> A_IWL<6441> A_IWL<6440> A_IWL<6439> A_IWL<6438> A_IWL<6437> A_IWL<6436> A_IWL<6435> A_IWL<6434> A_IWL<6433> A_IWL<6432> A_IWL<6431> A_IWL<6430> A_IWL<6429> A_IWL<6428> A_IWL<6427> A_IWL<6426> A_IWL<6425> A_IWL<6424> A_IWL<6423> A_IWL<6422> A_IWL<6421> A_IWL<6420> A_IWL<6419> A_IWL<6418> A_IWL<6417> A_IWL<6416> A_IWL<6415> A_IWL<6414> A_IWL<6413> A_IWL<6412> A_IWL<6411> A_IWL<6410> A_IWL<6409> A_IWL<6408> A_IWL<6407> A_IWL<6406> A_IWL<6405> A_IWL<6404> A_IWL<6403> A_IWL<6402> A_IWL<6401> A_IWL<6400> VDD_CORE VSS / RM_IHPSG13_1024x32_c2_1P_COLUMN_pcell_0 +XCOL<24> A_BLC<49> A_BLC<48> A_BLC_TOP<49> A_BLC_TOP<48> A_BLT<49> A_BLT<48> A_BLT_TOP<49> A_BLT_TOP<48> A_IWL<6143> A_IWL<6142> A_IWL<6141> A_IWL<6140> A_IWL<6139> A_IWL<6138> A_IWL<6137> A_IWL<6136> A_IWL<6135> A_IWL<6134> A_IWL<6133> A_IWL<6132> A_IWL<6131> A_IWL<6130> A_IWL<6129> A_IWL<6128> A_IWL<6127> A_IWL<6126> A_IWL<6125> A_IWL<6124> A_IWL<6123> A_IWL<6122> A_IWL<6121> A_IWL<6120> A_IWL<6119> A_IWL<6118> A_IWL<6117> A_IWL<6116> A_IWL<6115> A_IWL<6114> A_IWL<6113> A_IWL<6112> A_IWL<6111> A_IWL<6110> A_IWL<6109> A_IWL<6108> A_IWL<6107> A_IWL<6106> A_IWL<6105> A_IWL<6104> A_IWL<6103> A_IWL<6102> A_IWL<6101> A_IWL<6100> A_IWL<6099> A_IWL<6098> A_IWL<6097> A_IWL<6096> A_IWL<6095> A_IWL<6094> A_IWL<6093> A_IWL<6092> A_IWL<6091> A_IWL<6090> A_IWL<6089> A_IWL<6088> A_IWL<6087> A_IWL<6086> A_IWL<6085> A_IWL<6084> A_IWL<6083> A_IWL<6082> A_IWL<6081> A_IWL<6080> A_IWL<6079> A_IWL<6078> A_IWL<6077> A_IWL<6076> A_IWL<6075> A_IWL<6074> A_IWL<6073> A_IWL<6072> A_IWL<6071> A_IWL<6070> A_IWL<6069> A_IWL<6068> A_IWL<6067> A_IWL<6066> A_IWL<6065> A_IWL<6064> A_IWL<6063> A_IWL<6062> A_IWL<6061> A_IWL<6060> A_IWL<6059> A_IWL<6058> A_IWL<6057> A_IWL<6056> A_IWL<6055> A_IWL<6054> A_IWL<6053> A_IWL<6052> A_IWL<6051> A_IWL<6050> A_IWL<6049> A_IWL<6048> A_IWL<6047> A_IWL<6046> A_IWL<6045> A_IWL<6044> A_IWL<6043> A_IWL<6042> A_IWL<6041> A_IWL<6040> A_IWL<6039> A_IWL<6038> A_IWL<6037> A_IWL<6036> A_IWL<6035> A_IWL<6034> A_IWL<6033> A_IWL<6032> A_IWL<6031> A_IWL<6030> A_IWL<6029> A_IWL<6028> A_IWL<6027> A_IWL<6026> A_IWL<6025> A_IWL<6024> A_IWL<6023> A_IWL<6022> A_IWL<6021> A_IWL<6020> A_IWL<6019> A_IWL<6018> A_IWL<6017> A_IWL<6016> A_IWL<6015> A_IWL<6014> A_IWL<6013> A_IWL<6012> A_IWL<6011> A_IWL<6010> A_IWL<6009> A_IWL<6008> A_IWL<6007> A_IWL<6006> A_IWL<6005> A_IWL<6004> A_IWL<6003> A_IWL<6002> A_IWL<6001> A_IWL<6000> A_IWL<5999> A_IWL<5998> A_IWL<5997> A_IWL<5996> A_IWL<5995> A_IWL<5994> A_IWL<5993> A_IWL<5992> A_IWL<5991> A_IWL<5990> A_IWL<5989> A_IWL<5988> A_IWL<5987> A_IWL<5986> A_IWL<5985> A_IWL<5984> A_IWL<5983> A_IWL<5982> A_IWL<5981> A_IWL<5980> A_IWL<5979> A_IWL<5978> A_IWL<5977> A_IWL<5976> A_IWL<5975> A_IWL<5974> A_IWL<5973> A_IWL<5972> A_IWL<5971> A_IWL<5970> A_IWL<5969> A_IWL<5968> A_IWL<5967> A_IWL<5966> A_IWL<5965> A_IWL<5964> A_IWL<5963> A_IWL<5962> A_IWL<5961> A_IWL<5960> A_IWL<5959> A_IWL<5958> A_IWL<5957> A_IWL<5956> A_IWL<5955> A_IWL<5954> A_IWL<5953> A_IWL<5952> A_IWL<5951> A_IWL<5950> A_IWL<5949> A_IWL<5948> A_IWL<5947> A_IWL<5946> A_IWL<5945> A_IWL<5944> A_IWL<5943> A_IWL<5942> A_IWL<5941> A_IWL<5940> A_IWL<5939> A_IWL<5938> A_IWL<5937> A_IWL<5936> A_IWL<5935> A_IWL<5934> A_IWL<5933> A_IWL<5932> A_IWL<5931> A_IWL<5930> A_IWL<5929> A_IWL<5928> A_IWL<5927> A_IWL<5926> A_IWL<5925> A_IWL<5924> A_IWL<5923> A_IWL<5922> A_IWL<5921> A_IWL<5920> A_IWL<5919> A_IWL<5918> A_IWL<5917> A_IWL<5916> A_IWL<5915> A_IWL<5914> A_IWL<5913> A_IWL<5912> A_IWL<5911> A_IWL<5910> A_IWL<5909> A_IWL<5908> A_IWL<5907> A_IWL<5906> A_IWL<5905> A_IWL<5904> A_IWL<5903> A_IWL<5902> A_IWL<5901> A_IWL<5900> A_IWL<5899> A_IWL<5898> A_IWL<5897> A_IWL<5896> A_IWL<5895> A_IWL<5894> A_IWL<5893> A_IWL<5892> A_IWL<5891> A_IWL<5890> A_IWL<5889> A_IWL<5888> A_IWL<6399> A_IWL<6398> A_IWL<6397> A_IWL<6396> A_IWL<6395> A_IWL<6394> A_IWL<6393> A_IWL<6392> A_IWL<6391> A_IWL<6390> A_IWL<6389> A_IWL<6388> A_IWL<6387> A_IWL<6386> A_IWL<6385> A_IWL<6384> A_IWL<6383> A_IWL<6382> A_IWL<6381> A_IWL<6380> A_IWL<6379> A_IWL<6378> A_IWL<6377> A_IWL<6376> A_IWL<6375> A_IWL<6374> A_IWL<6373> A_IWL<6372> A_IWL<6371> A_IWL<6370> A_IWL<6369> A_IWL<6368> A_IWL<6367> A_IWL<6366> A_IWL<6365> A_IWL<6364> A_IWL<6363> A_IWL<6362> A_IWL<6361> A_IWL<6360> A_IWL<6359> A_IWL<6358> A_IWL<6357> A_IWL<6356> A_IWL<6355> A_IWL<6354> A_IWL<6353> A_IWL<6352> A_IWL<6351> A_IWL<6350> A_IWL<6349> A_IWL<6348> A_IWL<6347> A_IWL<6346> A_IWL<6345> A_IWL<6344> A_IWL<6343> A_IWL<6342> A_IWL<6341> A_IWL<6340> A_IWL<6339> A_IWL<6338> A_IWL<6337> A_IWL<6336> A_IWL<6335> A_IWL<6334> A_IWL<6333> A_IWL<6332> A_IWL<6331> A_IWL<6330> A_IWL<6329> A_IWL<6328> A_IWL<6327> A_IWL<6326> A_IWL<6325> A_IWL<6324> A_IWL<6323> A_IWL<6322> A_IWL<6321> A_IWL<6320> A_IWL<6319> A_IWL<6318> A_IWL<6317> A_IWL<6316> A_IWL<6315> A_IWL<6314> A_IWL<6313> A_IWL<6312> A_IWL<6311> A_IWL<6310> A_IWL<6309> A_IWL<6308> A_IWL<6307> A_IWL<6306> A_IWL<6305> A_IWL<6304> A_IWL<6303> A_IWL<6302> A_IWL<6301> A_IWL<6300> A_IWL<6299> A_IWL<6298> A_IWL<6297> A_IWL<6296> A_IWL<6295> A_IWL<6294> A_IWL<6293> A_IWL<6292> A_IWL<6291> A_IWL<6290> A_IWL<6289> A_IWL<6288> A_IWL<6287> A_IWL<6286> A_IWL<6285> A_IWL<6284> A_IWL<6283> A_IWL<6282> A_IWL<6281> A_IWL<6280> A_IWL<6279> A_IWL<6278> A_IWL<6277> A_IWL<6276> A_IWL<6275> A_IWL<6274> A_IWL<6273> A_IWL<6272> A_IWL<6271> A_IWL<6270> A_IWL<6269> A_IWL<6268> A_IWL<6267> A_IWL<6266> A_IWL<6265> A_IWL<6264> A_IWL<6263> A_IWL<6262> A_IWL<6261> A_IWL<6260> A_IWL<6259> A_IWL<6258> A_IWL<6257> A_IWL<6256> A_IWL<6255> A_IWL<6254> A_IWL<6253> A_IWL<6252> A_IWL<6251> A_IWL<6250> A_IWL<6249> A_IWL<6248> A_IWL<6247> A_IWL<6246> A_IWL<6245> A_IWL<6244> A_IWL<6243> A_IWL<6242> A_IWL<6241> A_IWL<6240> A_IWL<6239> A_IWL<6238> A_IWL<6237> A_IWL<6236> A_IWL<6235> A_IWL<6234> A_IWL<6233> A_IWL<6232> A_IWL<6231> A_IWL<6230> A_IWL<6229> A_IWL<6228> A_IWL<6227> A_IWL<6226> A_IWL<6225> A_IWL<6224> A_IWL<6223> A_IWL<6222> A_IWL<6221> A_IWL<6220> A_IWL<6219> A_IWL<6218> A_IWL<6217> A_IWL<6216> A_IWL<6215> A_IWL<6214> A_IWL<6213> A_IWL<6212> A_IWL<6211> A_IWL<6210> A_IWL<6209> A_IWL<6208> A_IWL<6207> A_IWL<6206> A_IWL<6205> A_IWL<6204> A_IWL<6203> A_IWL<6202> A_IWL<6201> A_IWL<6200> A_IWL<6199> A_IWL<6198> A_IWL<6197> A_IWL<6196> A_IWL<6195> A_IWL<6194> A_IWL<6193> A_IWL<6192> A_IWL<6191> A_IWL<6190> A_IWL<6189> A_IWL<6188> A_IWL<6187> A_IWL<6186> A_IWL<6185> A_IWL<6184> A_IWL<6183> A_IWL<6182> A_IWL<6181> A_IWL<6180> A_IWL<6179> A_IWL<6178> A_IWL<6177> A_IWL<6176> A_IWL<6175> A_IWL<6174> A_IWL<6173> A_IWL<6172> A_IWL<6171> A_IWL<6170> A_IWL<6169> A_IWL<6168> A_IWL<6167> A_IWL<6166> A_IWL<6165> A_IWL<6164> A_IWL<6163> A_IWL<6162> A_IWL<6161> A_IWL<6160> A_IWL<6159> A_IWL<6158> A_IWL<6157> A_IWL<6156> A_IWL<6155> A_IWL<6154> A_IWL<6153> A_IWL<6152> A_IWL<6151> A_IWL<6150> A_IWL<6149> A_IWL<6148> A_IWL<6147> A_IWL<6146> A_IWL<6145> A_IWL<6144> VDD_CORE VSS / RM_IHPSG13_1024x32_c2_1P_COLUMN_pcell_0 +XCOL<23> A_BLC<47> A_BLC<46> A_BLC_TOP<47> A_BLC_TOP<46> A_BLT<47> A_BLT<46> A_BLT_TOP<47> A_BLT_TOP<46> A_IWL<5887> A_IWL<5886> A_IWL<5885> A_IWL<5884> A_IWL<5883> A_IWL<5882> A_IWL<5881> A_IWL<5880> A_IWL<5879> A_IWL<5878> A_IWL<5877> A_IWL<5876> A_IWL<5875> A_IWL<5874> A_IWL<5873> A_IWL<5872> A_IWL<5871> A_IWL<5870> A_IWL<5869> A_IWL<5868> A_IWL<5867> A_IWL<5866> A_IWL<5865> A_IWL<5864> A_IWL<5863> A_IWL<5862> A_IWL<5861> A_IWL<5860> A_IWL<5859> A_IWL<5858> A_IWL<5857> A_IWL<5856> A_IWL<5855> A_IWL<5854> A_IWL<5853> A_IWL<5852> A_IWL<5851> A_IWL<5850> A_IWL<5849> A_IWL<5848> A_IWL<5847> A_IWL<5846> A_IWL<5845> A_IWL<5844> A_IWL<5843> A_IWL<5842> A_IWL<5841> A_IWL<5840> A_IWL<5839> A_IWL<5838> A_IWL<5837> A_IWL<5836> A_IWL<5835> A_IWL<5834> A_IWL<5833> A_IWL<5832> A_IWL<5831> A_IWL<5830> A_IWL<5829> A_IWL<5828> A_IWL<5827> A_IWL<5826> A_IWL<5825> A_IWL<5824> A_IWL<5823> A_IWL<5822> A_IWL<5821> A_IWL<5820> A_IWL<5819> A_IWL<5818> A_IWL<5817> A_IWL<5816> A_IWL<5815> A_IWL<5814> A_IWL<5813> A_IWL<5812> A_IWL<5811> A_IWL<5810> A_IWL<5809> A_IWL<5808> A_IWL<5807> A_IWL<5806> A_IWL<5805> A_IWL<5804> A_IWL<5803> A_IWL<5802> A_IWL<5801> A_IWL<5800> A_IWL<5799> A_IWL<5798> A_IWL<5797> A_IWL<5796> A_IWL<5795> A_IWL<5794> A_IWL<5793> A_IWL<5792> A_IWL<5791> A_IWL<5790> A_IWL<5789> A_IWL<5788> A_IWL<5787> A_IWL<5786> A_IWL<5785> A_IWL<5784> A_IWL<5783> A_IWL<5782> A_IWL<5781> A_IWL<5780> A_IWL<5779> A_IWL<5778> A_IWL<5777> A_IWL<5776> A_IWL<5775> A_IWL<5774> A_IWL<5773> A_IWL<5772> A_IWL<5771> A_IWL<5770> A_IWL<5769> A_IWL<5768> A_IWL<5767> A_IWL<5766> A_IWL<5765> A_IWL<5764> A_IWL<5763> A_IWL<5762> A_IWL<5761> A_IWL<5760> A_IWL<5759> A_IWL<5758> A_IWL<5757> A_IWL<5756> A_IWL<5755> A_IWL<5754> A_IWL<5753> A_IWL<5752> A_IWL<5751> A_IWL<5750> A_IWL<5749> A_IWL<5748> A_IWL<5747> A_IWL<5746> A_IWL<5745> A_IWL<5744> A_IWL<5743> A_IWL<5742> A_IWL<5741> A_IWL<5740> A_IWL<5739> A_IWL<5738> A_IWL<5737> A_IWL<5736> A_IWL<5735> A_IWL<5734> A_IWL<5733> A_IWL<5732> A_IWL<5731> A_IWL<5730> A_IWL<5729> A_IWL<5728> A_IWL<5727> A_IWL<5726> A_IWL<5725> A_IWL<5724> A_IWL<5723> A_IWL<5722> A_IWL<5721> A_IWL<5720> A_IWL<5719> A_IWL<5718> A_IWL<5717> A_IWL<5716> A_IWL<5715> A_IWL<5714> A_IWL<5713> A_IWL<5712> A_IWL<5711> A_IWL<5710> A_IWL<5709> A_IWL<5708> A_IWL<5707> A_IWL<5706> A_IWL<5705> A_IWL<5704> A_IWL<5703> A_IWL<5702> A_IWL<5701> A_IWL<5700> A_IWL<5699> A_IWL<5698> A_IWL<5697> A_IWL<5696> A_IWL<5695> A_IWL<5694> A_IWL<5693> A_IWL<5692> A_IWL<5691> A_IWL<5690> A_IWL<5689> A_IWL<5688> A_IWL<5687> A_IWL<5686> A_IWL<5685> A_IWL<5684> A_IWL<5683> A_IWL<5682> A_IWL<5681> A_IWL<5680> A_IWL<5679> A_IWL<5678> A_IWL<5677> A_IWL<5676> A_IWL<5675> A_IWL<5674> A_IWL<5673> A_IWL<5672> A_IWL<5671> A_IWL<5670> A_IWL<5669> A_IWL<5668> A_IWL<5667> A_IWL<5666> A_IWL<5665> A_IWL<5664> A_IWL<5663> A_IWL<5662> A_IWL<5661> A_IWL<5660> A_IWL<5659> A_IWL<5658> A_IWL<5657> A_IWL<5656> A_IWL<5655> A_IWL<5654> A_IWL<5653> A_IWL<5652> A_IWL<5651> A_IWL<5650> A_IWL<5649> A_IWL<5648> A_IWL<5647> A_IWL<5646> A_IWL<5645> A_IWL<5644> A_IWL<5643> A_IWL<5642> A_IWL<5641> A_IWL<5640> A_IWL<5639> A_IWL<5638> A_IWL<5637> A_IWL<5636> A_IWL<5635> A_IWL<5634> A_IWL<5633> A_IWL<5632> A_IWL<6143> A_IWL<6142> A_IWL<6141> A_IWL<6140> A_IWL<6139> A_IWL<6138> A_IWL<6137> A_IWL<6136> A_IWL<6135> A_IWL<6134> A_IWL<6133> A_IWL<6132> A_IWL<6131> A_IWL<6130> A_IWL<6129> A_IWL<6128> A_IWL<6127> A_IWL<6126> A_IWL<6125> A_IWL<6124> A_IWL<6123> A_IWL<6122> A_IWL<6121> A_IWL<6120> A_IWL<6119> A_IWL<6118> A_IWL<6117> A_IWL<6116> A_IWL<6115> A_IWL<6114> A_IWL<6113> A_IWL<6112> A_IWL<6111> A_IWL<6110> A_IWL<6109> A_IWL<6108> A_IWL<6107> A_IWL<6106> A_IWL<6105> A_IWL<6104> A_IWL<6103> A_IWL<6102> A_IWL<6101> A_IWL<6100> A_IWL<6099> A_IWL<6098> A_IWL<6097> A_IWL<6096> A_IWL<6095> A_IWL<6094> A_IWL<6093> A_IWL<6092> A_IWL<6091> A_IWL<6090> A_IWL<6089> A_IWL<6088> A_IWL<6087> A_IWL<6086> A_IWL<6085> A_IWL<6084> A_IWL<6083> A_IWL<6082> A_IWL<6081> A_IWL<6080> A_IWL<6079> A_IWL<6078> A_IWL<6077> A_IWL<6076> A_IWL<6075> A_IWL<6074> A_IWL<6073> A_IWL<6072> A_IWL<6071> A_IWL<6070> A_IWL<6069> A_IWL<6068> A_IWL<6067> A_IWL<6066> A_IWL<6065> A_IWL<6064> A_IWL<6063> A_IWL<6062> A_IWL<6061> A_IWL<6060> A_IWL<6059> A_IWL<6058> A_IWL<6057> A_IWL<6056> A_IWL<6055> A_IWL<6054> A_IWL<6053> A_IWL<6052> A_IWL<6051> A_IWL<6050> A_IWL<6049> A_IWL<6048> A_IWL<6047> A_IWL<6046> A_IWL<6045> A_IWL<6044> A_IWL<6043> A_IWL<6042> A_IWL<6041> A_IWL<6040> A_IWL<6039> A_IWL<6038> A_IWL<6037> A_IWL<6036> A_IWL<6035> A_IWL<6034> A_IWL<6033> A_IWL<6032> A_IWL<6031> A_IWL<6030> A_IWL<6029> A_IWL<6028> A_IWL<6027> A_IWL<6026> A_IWL<6025> A_IWL<6024> A_IWL<6023> A_IWL<6022> A_IWL<6021> A_IWL<6020> A_IWL<6019> A_IWL<6018> A_IWL<6017> A_IWL<6016> A_IWL<6015> A_IWL<6014> A_IWL<6013> A_IWL<6012> A_IWL<6011> A_IWL<6010> A_IWL<6009> A_IWL<6008> A_IWL<6007> A_IWL<6006> A_IWL<6005> A_IWL<6004> A_IWL<6003> A_IWL<6002> A_IWL<6001> A_IWL<6000> A_IWL<5999> A_IWL<5998> A_IWL<5997> A_IWL<5996> A_IWL<5995> A_IWL<5994> A_IWL<5993> A_IWL<5992> A_IWL<5991> A_IWL<5990> A_IWL<5989> A_IWL<5988> A_IWL<5987> A_IWL<5986> A_IWL<5985> A_IWL<5984> A_IWL<5983> A_IWL<5982> A_IWL<5981> A_IWL<5980> A_IWL<5979> A_IWL<5978> A_IWL<5977> A_IWL<5976> A_IWL<5975> A_IWL<5974> A_IWL<5973> A_IWL<5972> A_IWL<5971> A_IWL<5970> A_IWL<5969> A_IWL<5968> A_IWL<5967> A_IWL<5966> A_IWL<5965> A_IWL<5964> A_IWL<5963> A_IWL<5962> A_IWL<5961> A_IWL<5960> A_IWL<5959> A_IWL<5958> A_IWL<5957> A_IWL<5956> A_IWL<5955> A_IWL<5954> A_IWL<5953> A_IWL<5952> A_IWL<5951> A_IWL<5950> A_IWL<5949> A_IWL<5948> A_IWL<5947> A_IWL<5946> A_IWL<5945> A_IWL<5944> A_IWL<5943> A_IWL<5942> A_IWL<5941> A_IWL<5940> A_IWL<5939> A_IWL<5938> A_IWL<5937> A_IWL<5936> A_IWL<5935> A_IWL<5934> A_IWL<5933> A_IWL<5932> A_IWL<5931> A_IWL<5930> A_IWL<5929> A_IWL<5928> A_IWL<5927> A_IWL<5926> A_IWL<5925> A_IWL<5924> A_IWL<5923> A_IWL<5922> A_IWL<5921> A_IWL<5920> A_IWL<5919> A_IWL<5918> A_IWL<5917> A_IWL<5916> A_IWL<5915> A_IWL<5914> A_IWL<5913> A_IWL<5912> A_IWL<5911> A_IWL<5910> A_IWL<5909> A_IWL<5908> A_IWL<5907> A_IWL<5906> A_IWL<5905> A_IWL<5904> A_IWL<5903> A_IWL<5902> A_IWL<5901> A_IWL<5900> A_IWL<5899> A_IWL<5898> A_IWL<5897> A_IWL<5896> A_IWL<5895> A_IWL<5894> A_IWL<5893> A_IWL<5892> A_IWL<5891> A_IWL<5890> A_IWL<5889> A_IWL<5888> VDD_CORE VSS / RM_IHPSG13_1024x32_c2_1P_COLUMN_pcell_0 +XCOL<22> A_BLC<45> A_BLC<44> A_BLC_TOP<45> A_BLC_TOP<44> A_BLT<45> A_BLT<44> A_BLT_TOP<45> A_BLT_TOP<44> A_IWL<5631> A_IWL<5630> A_IWL<5629> A_IWL<5628> A_IWL<5627> A_IWL<5626> A_IWL<5625> A_IWL<5624> A_IWL<5623> A_IWL<5622> A_IWL<5621> A_IWL<5620> A_IWL<5619> A_IWL<5618> A_IWL<5617> A_IWL<5616> A_IWL<5615> A_IWL<5614> A_IWL<5613> A_IWL<5612> A_IWL<5611> A_IWL<5610> A_IWL<5609> A_IWL<5608> A_IWL<5607> A_IWL<5606> A_IWL<5605> A_IWL<5604> A_IWL<5603> A_IWL<5602> A_IWL<5601> A_IWL<5600> A_IWL<5599> A_IWL<5598> A_IWL<5597> A_IWL<5596> A_IWL<5595> A_IWL<5594> A_IWL<5593> A_IWL<5592> A_IWL<5591> A_IWL<5590> A_IWL<5589> A_IWL<5588> A_IWL<5587> A_IWL<5586> A_IWL<5585> A_IWL<5584> A_IWL<5583> A_IWL<5582> A_IWL<5581> A_IWL<5580> A_IWL<5579> A_IWL<5578> A_IWL<5577> A_IWL<5576> A_IWL<5575> A_IWL<5574> A_IWL<5573> A_IWL<5572> A_IWL<5571> A_IWL<5570> A_IWL<5569> A_IWL<5568> A_IWL<5567> A_IWL<5566> A_IWL<5565> A_IWL<5564> A_IWL<5563> A_IWL<5562> A_IWL<5561> A_IWL<5560> A_IWL<5559> A_IWL<5558> A_IWL<5557> A_IWL<5556> A_IWL<5555> A_IWL<5554> A_IWL<5553> A_IWL<5552> A_IWL<5551> A_IWL<5550> A_IWL<5549> A_IWL<5548> A_IWL<5547> A_IWL<5546> A_IWL<5545> A_IWL<5544> A_IWL<5543> A_IWL<5542> A_IWL<5541> A_IWL<5540> A_IWL<5539> A_IWL<5538> A_IWL<5537> A_IWL<5536> A_IWL<5535> A_IWL<5534> A_IWL<5533> A_IWL<5532> A_IWL<5531> A_IWL<5530> A_IWL<5529> A_IWL<5528> A_IWL<5527> A_IWL<5526> A_IWL<5525> A_IWL<5524> A_IWL<5523> A_IWL<5522> A_IWL<5521> A_IWL<5520> A_IWL<5519> A_IWL<5518> A_IWL<5517> A_IWL<5516> A_IWL<5515> A_IWL<5514> A_IWL<5513> A_IWL<5512> A_IWL<5511> A_IWL<5510> A_IWL<5509> A_IWL<5508> A_IWL<5507> A_IWL<5506> A_IWL<5505> A_IWL<5504> A_IWL<5503> A_IWL<5502> A_IWL<5501> A_IWL<5500> A_IWL<5499> A_IWL<5498> A_IWL<5497> A_IWL<5496> A_IWL<5495> A_IWL<5494> A_IWL<5493> A_IWL<5492> A_IWL<5491> A_IWL<5490> A_IWL<5489> A_IWL<5488> A_IWL<5487> A_IWL<5486> A_IWL<5485> A_IWL<5484> A_IWL<5483> A_IWL<5482> A_IWL<5481> A_IWL<5480> A_IWL<5479> A_IWL<5478> A_IWL<5477> A_IWL<5476> A_IWL<5475> A_IWL<5474> A_IWL<5473> A_IWL<5472> A_IWL<5471> A_IWL<5470> A_IWL<5469> A_IWL<5468> A_IWL<5467> A_IWL<5466> A_IWL<5465> A_IWL<5464> A_IWL<5463> A_IWL<5462> A_IWL<5461> A_IWL<5460> A_IWL<5459> A_IWL<5458> A_IWL<5457> A_IWL<5456> A_IWL<5455> A_IWL<5454> A_IWL<5453> A_IWL<5452> A_IWL<5451> A_IWL<5450> A_IWL<5449> A_IWL<5448> A_IWL<5447> A_IWL<5446> A_IWL<5445> A_IWL<5444> A_IWL<5443> A_IWL<5442> A_IWL<5441> A_IWL<5440> A_IWL<5439> A_IWL<5438> A_IWL<5437> A_IWL<5436> A_IWL<5435> A_IWL<5434> A_IWL<5433> A_IWL<5432> A_IWL<5431> A_IWL<5430> A_IWL<5429> A_IWL<5428> A_IWL<5427> A_IWL<5426> A_IWL<5425> A_IWL<5424> A_IWL<5423> A_IWL<5422> A_IWL<5421> A_IWL<5420> A_IWL<5419> A_IWL<5418> A_IWL<5417> A_IWL<5416> A_IWL<5415> A_IWL<5414> A_IWL<5413> A_IWL<5412> A_IWL<5411> A_IWL<5410> A_IWL<5409> A_IWL<5408> A_IWL<5407> A_IWL<5406> A_IWL<5405> A_IWL<5404> A_IWL<5403> A_IWL<5402> A_IWL<5401> A_IWL<5400> A_IWL<5399> A_IWL<5398> A_IWL<5397> A_IWL<5396> A_IWL<5395> A_IWL<5394> A_IWL<5393> A_IWL<5392> A_IWL<5391> A_IWL<5390> A_IWL<5389> A_IWL<5388> A_IWL<5387> A_IWL<5386> A_IWL<5385> A_IWL<5384> A_IWL<5383> A_IWL<5382> A_IWL<5381> A_IWL<5380> A_IWL<5379> A_IWL<5378> A_IWL<5377> A_IWL<5376> A_IWL<5887> A_IWL<5886> A_IWL<5885> A_IWL<5884> A_IWL<5883> A_IWL<5882> A_IWL<5881> A_IWL<5880> A_IWL<5879> A_IWL<5878> A_IWL<5877> A_IWL<5876> A_IWL<5875> A_IWL<5874> A_IWL<5873> A_IWL<5872> A_IWL<5871> A_IWL<5870> A_IWL<5869> A_IWL<5868> A_IWL<5867> A_IWL<5866> A_IWL<5865> A_IWL<5864> A_IWL<5863> A_IWL<5862> A_IWL<5861> A_IWL<5860> A_IWL<5859> A_IWL<5858> A_IWL<5857> A_IWL<5856> A_IWL<5855> A_IWL<5854> A_IWL<5853> A_IWL<5852> A_IWL<5851> A_IWL<5850> A_IWL<5849> A_IWL<5848> A_IWL<5847> A_IWL<5846> A_IWL<5845> A_IWL<5844> A_IWL<5843> A_IWL<5842> A_IWL<5841> A_IWL<5840> A_IWL<5839> A_IWL<5838> A_IWL<5837> A_IWL<5836> A_IWL<5835> A_IWL<5834> A_IWL<5833> A_IWL<5832> A_IWL<5831> A_IWL<5830> A_IWL<5829> A_IWL<5828> A_IWL<5827> A_IWL<5826> A_IWL<5825> A_IWL<5824> A_IWL<5823> A_IWL<5822> A_IWL<5821> A_IWL<5820> A_IWL<5819> A_IWL<5818> A_IWL<5817> A_IWL<5816> A_IWL<5815> A_IWL<5814> A_IWL<5813> A_IWL<5812> A_IWL<5811> A_IWL<5810> A_IWL<5809> A_IWL<5808> A_IWL<5807> A_IWL<5806> A_IWL<5805> A_IWL<5804> A_IWL<5803> A_IWL<5802> A_IWL<5801> A_IWL<5800> A_IWL<5799> A_IWL<5798> A_IWL<5797> A_IWL<5796> A_IWL<5795> A_IWL<5794> A_IWL<5793> A_IWL<5792> A_IWL<5791> A_IWL<5790> A_IWL<5789> A_IWL<5788> A_IWL<5787> A_IWL<5786> A_IWL<5785> A_IWL<5784> A_IWL<5783> A_IWL<5782> A_IWL<5781> A_IWL<5780> A_IWL<5779> A_IWL<5778> A_IWL<5777> A_IWL<5776> A_IWL<5775> A_IWL<5774> A_IWL<5773> A_IWL<5772> A_IWL<5771> A_IWL<5770> A_IWL<5769> A_IWL<5768> A_IWL<5767> A_IWL<5766> A_IWL<5765> A_IWL<5764> A_IWL<5763> A_IWL<5762> A_IWL<5761> A_IWL<5760> A_IWL<5759> A_IWL<5758> A_IWL<5757> A_IWL<5756> A_IWL<5755> A_IWL<5754> A_IWL<5753> A_IWL<5752> A_IWL<5751> A_IWL<5750> A_IWL<5749> A_IWL<5748> A_IWL<5747> A_IWL<5746> A_IWL<5745> A_IWL<5744> A_IWL<5743> A_IWL<5742> A_IWL<5741> A_IWL<5740> A_IWL<5739> A_IWL<5738> A_IWL<5737> A_IWL<5736> A_IWL<5735> A_IWL<5734> A_IWL<5733> A_IWL<5732> A_IWL<5731> A_IWL<5730> A_IWL<5729> A_IWL<5728> A_IWL<5727> A_IWL<5726> A_IWL<5725> A_IWL<5724> A_IWL<5723> A_IWL<5722> A_IWL<5721> A_IWL<5720> A_IWL<5719> A_IWL<5718> A_IWL<5717> A_IWL<5716> A_IWL<5715> A_IWL<5714> A_IWL<5713> A_IWL<5712> A_IWL<5711> A_IWL<5710> A_IWL<5709> A_IWL<5708> A_IWL<5707> A_IWL<5706> A_IWL<5705> A_IWL<5704> A_IWL<5703> A_IWL<5702> A_IWL<5701> A_IWL<5700> A_IWL<5699> A_IWL<5698> A_IWL<5697> A_IWL<5696> A_IWL<5695> A_IWL<5694> A_IWL<5693> A_IWL<5692> A_IWL<5691> A_IWL<5690> A_IWL<5689> A_IWL<5688> A_IWL<5687> A_IWL<5686> A_IWL<5685> A_IWL<5684> A_IWL<5683> A_IWL<5682> A_IWL<5681> A_IWL<5680> A_IWL<5679> A_IWL<5678> A_IWL<5677> A_IWL<5676> A_IWL<5675> A_IWL<5674> A_IWL<5673> A_IWL<5672> A_IWL<5671> A_IWL<5670> A_IWL<5669> A_IWL<5668> A_IWL<5667> A_IWL<5666> A_IWL<5665> A_IWL<5664> A_IWL<5663> A_IWL<5662> A_IWL<5661> A_IWL<5660> A_IWL<5659> A_IWL<5658> A_IWL<5657> A_IWL<5656> A_IWL<5655> A_IWL<5654> A_IWL<5653> A_IWL<5652> A_IWL<5651> A_IWL<5650> A_IWL<5649> A_IWL<5648> A_IWL<5647> A_IWL<5646> A_IWL<5645> A_IWL<5644> A_IWL<5643> A_IWL<5642> A_IWL<5641> A_IWL<5640> A_IWL<5639> A_IWL<5638> A_IWL<5637> A_IWL<5636> A_IWL<5635> A_IWL<5634> A_IWL<5633> A_IWL<5632> VDD_CORE VSS / RM_IHPSG13_1024x32_c2_1P_COLUMN_pcell_0 +XCOL<21> A_BLC<43> A_BLC<42> A_BLC_TOP<43> A_BLC_TOP<42> A_BLT<43> A_BLT<42> A_BLT_TOP<43> A_BLT_TOP<42> A_IWL<5375> A_IWL<5374> A_IWL<5373> A_IWL<5372> A_IWL<5371> A_IWL<5370> A_IWL<5369> A_IWL<5368> A_IWL<5367> A_IWL<5366> A_IWL<5365> A_IWL<5364> A_IWL<5363> A_IWL<5362> A_IWL<5361> A_IWL<5360> A_IWL<5359> A_IWL<5358> A_IWL<5357> A_IWL<5356> A_IWL<5355> A_IWL<5354> A_IWL<5353> A_IWL<5352> A_IWL<5351> A_IWL<5350> A_IWL<5349> A_IWL<5348> A_IWL<5347> A_IWL<5346> A_IWL<5345> A_IWL<5344> A_IWL<5343> A_IWL<5342> A_IWL<5341> A_IWL<5340> A_IWL<5339> A_IWL<5338> A_IWL<5337> A_IWL<5336> A_IWL<5335> A_IWL<5334> A_IWL<5333> A_IWL<5332> A_IWL<5331> A_IWL<5330> A_IWL<5329> A_IWL<5328> A_IWL<5327> A_IWL<5326> A_IWL<5325> A_IWL<5324> A_IWL<5323> A_IWL<5322> A_IWL<5321> A_IWL<5320> A_IWL<5319> A_IWL<5318> A_IWL<5317> A_IWL<5316> A_IWL<5315> A_IWL<5314> A_IWL<5313> A_IWL<5312> A_IWL<5311> A_IWL<5310> A_IWL<5309> A_IWL<5308> A_IWL<5307> A_IWL<5306> A_IWL<5305> A_IWL<5304> A_IWL<5303> A_IWL<5302> A_IWL<5301> A_IWL<5300> A_IWL<5299> A_IWL<5298> A_IWL<5297> A_IWL<5296> A_IWL<5295> A_IWL<5294> A_IWL<5293> A_IWL<5292> A_IWL<5291> A_IWL<5290> A_IWL<5289> A_IWL<5288> A_IWL<5287> A_IWL<5286> A_IWL<5285> A_IWL<5284> A_IWL<5283> A_IWL<5282> A_IWL<5281> A_IWL<5280> A_IWL<5279> A_IWL<5278> A_IWL<5277> A_IWL<5276> A_IWL<5275> A_IWL<5274> A_IWL<5273> A_IWL<5272> A_IWL<5271> A_IWL<5270> A_IWL<5269> A_IWL<5268> A_IWL<5267> A_IWL<5266> A_IWL<5265> A_IWL<5264> A_IWL<5263> A_IWL<5262> A_IWL<5261> A_IWL<5260> A_IWL<5259> A_IWL<5258> A_IWL<5257> A_IWL<5256> A_IWL<5255> A_IWL<5254> A_IWL<5253> A_IWL<5252> A_IWL<5251> A_IWL<5250> A_IWL<5249> A_IWL<5248> A_IWL<5247> A_IWL<5246> A_IWL<5245> A_IWL<5244> A_IWL<5243> A_IWL<5242> A_IWL<5241> A_IWL<5240> A_IWL<5239> A_IWL<5238> A_IWL<5237> A_IWL<5236> A_IWL<5235> A_IWL<5234> A_IWL<5233> A_IWL<5232> A_IWL<5231> A_IWL<5230> A_IWL<5229> A_IWL<5228> A_IWL<5227> A_IWL<5226> A_IWL<5225> A_IWL<5224> A_IWL<5223> A_IWL<5222> A_IWL<5221> A_IWL<5220> A_IWL<5219> A_IWL<5218> A_IWL<5217> A_IWL<5216> A_IWL<5215> A_IWL<5214> A_IWL<5213> A_IWL<5212> A_IWL<5211> A_IWL<5210> A_IWL<5209> A_IWL<5208> A_IWL<5207> A_IWL<5206> A_IWL<5205> A_IWL<5204> A_IWL<5203> A_IWL<5202> A_IWL<5201> A_IWL<5200> A_IWL<5199> A_IWL<5198> A_IWL<5197> A_IWL<5196> A_IWL<5195> A_IWL<5194> A_IWL<5193> A_IWL<5192> A_IWL<5191> A_IWL<5190> A_IWL<5189> A_IWL<5188> A_IWL<5187> A_IWL<5186> A_IWL<5185> A_IWL<5184> A_IWL<5183> A_IWL<5182> A_IWL<5181> A_IWL<5180> A_IWL<5179> A_IWL<5178> A_IWL<5177> A_IWL<5176> A_IWL<5175> A_IWL<5174> A_IWL<5173> A_IWL<5172> A_IWL<5171> A_IWL<5170> A_IWL<5169> A_IWL<5168> A_IWL<5167> A_IWL<5166> A_IWL<5165> A_IWL<5164> A_IWL<5163> A_IWL<5162> A_IWL<5161> A_IWL<5160> A_IWL<5159> A_IWL<5158> A_IWL<5157> A_IWL<5156> A_IWL<5155> A_IWL<5154> A_IWL<5153> A_IWL<5152> A_IWL<5151> A_IWL<5150> A_IWL<5149> A_IWL<5148> A_IWL<5147> A_IWL<5146> A_IWL<5145> A_IWL<5144> A_IWL<5143> A_IWL<5142> A_IWL<5141> A_IWL<5140> A_IWL<5139> A_IWL<5138> A_IWL<5137> A_IWL<5136> A_IWL<5135> A_IWL<5134> A_IWL<5133> A_IWL<5132> A_IWL<5131> A_IWL<5130> A_IWL<5129> A_IWL<5128> A_IWL<5127> A_IWL<5126> A_IWL<5125> A_IWL<5124> A_IWL<5123> A_IWL<5122> A_IWL<5121> A_IWL<5120> A_IWL<5631> A_IWL<5630> A_IWL<5629> A_IWL<5628> A_IWL<5627> A_IWL<5626> A_IWL<5625> A_IWL<5624> A_IWL<5623> A_IWL<5622> A_IWL<5621> A_IWL<5620> A_IWL<5619> A_IWL<5618> A_IWL<5617> A_IWL<5616> A_IWL<5615> A_IWL<5614> A_IWL<5613> A_IWL<5612> A_IWL<5611> A_IWL<5610> A_IWL<5609> A_IWL<5608> A_IWL<5607> A_IWL<5606> A_IWL<5605> A_IWL<5604> A_IWL<5603> A_IWL<5602> A_IWL<5601> A_IWL<5600> A_IWL<5599> A_IWL<5598> A_IWL<5597> A_IWL<5596> A_IWL<5595> A_IWL<5594> A_IWL<5593> A_IWL<5592> A_IWL<5591> A_IWL<5590> A_IWL<5589> A_IWL<5588> A_IWL<5587> A_IWL<5586> A_IWL<5585> A_IWL<5584> A_IWL<5583> A_IWL<5582> A_IWL<5581> A_IWL<5580> A_IWL<5579> A_IWL<5578> A_IWL<5577> A_IWL<5576> A_IWL<5575> A_IWL<5574> A_IWL<5573> A_IWL<5572> A_IWL<5571> A_IWL<5570> A_IWL<5569> A_IWL<5568> A_IWL<5567> A_IWL<5566> A_IWL<5565> A_IWL<5564> A_IWL<5563> A_IWL<5562> A_IWL<5561> A_IWL<5560> A_IWL<5559> A_IWL<5558> A_IWL<5557> A_IWL<5556> A_IWL<5555> A_IWL<5554> A_IWL<5553> A_IWL<5552> A_IWL<5551> A_IWL<5550> A_IWL<5549> A_IWL<5548> A_IWL<5547> A_IWL<5546> A_IWL<5545> A_IWL<5544> A_IWL<5543> A_IWL<5542> A_IWL<5541> A_IWL<5540> A_IWL<5539> A_IWL<5538> A_IWL<5537> A_IWL<5536> A_IWL<5535> A_IWL<5534> A_IWL<5533> A_IWL<5532> A_IWL<5531> A_IWL<5530> A_IWL<5529> A_IWL<5528> A_IWL<5527> A_IWL<5526> A_IWL<5525> A_IWL<5524> A_IWL<5523> A_IWL<5522> A_IWL<5521> A_IWL<5520> A_IWL<5519> A_IWL<5518> A_IWL<5517> A_IWL<5516> A_IWL<5515> A_IWL<5514> A_IWL<5513> A_IWL<5512> A_IWL<5511> A_IWL<5510> A_IWL<5509> A_IWL<5508> A_IWL<5507> A_IWL<5506> A_IWL<5505> A_IWL<5504> A_IWL<5503> A_IWL<5502> A_IWL<5501> A_IWL<5500> A_IWL<5499> A_IWL<5498> A_IWL<5497> A_IWL<5496> A_IWL<5495> A_IWL<5494> A_IWL<5493> A_IWL<5492> A_IWL<5491> A_IWL<5490> A_IWL<5489> A_IWL<5488> A_IWL<5487> A_IWL<5486> A_IWL<5485> A_IWL<5484> A_IWL<5483> A_IWL<5482> A_IWL<5481> A_IWL<5480> A_IWL<5479> A_IWL<5478> A_IWL<5477> A_IWL<5476> A_IWL<5475> A_IWL<5474> A_IWL<5473> A_IWL<5472> A_IWL<5471> A_IWL<5470> A_IWL<5469> A_IWL<5468> A_IWL<5467> A_IWL<5466> A_IWL<5465> A_IWL<5464> A_IWL<5463> A_IWL<5462> A_IWL<5461> A_IWL<5460> A_IWL<5459> A_IWL<5458> A_IWL<5457> A_IWL<5456> A_IWL<5455> A_IWL<5454> A_IWL<5453> A_IWL<5452> A_IWL<5451> A_IWL<5450> A_IWL<5449> A_IWL<5448> A_IWL<5447> A_IWL<5446> A_IWL<5445> A_IWL<5444> A_IWL<5443> A_IWL<5442> A_IWL<5441> A_IWL<5440> A_IWL<5439> A_IWL<5438> A_IWL<5437> A_IWL<5436> A_IWL<5435> A_IWL<5434> A_IWL<5433> A_IWL<5432> A_IWL<5431> A_IWL<5430> A_IWL<5429> A_IWL<5428> A_IWL<5427> A_IWL<5426> A_IWL<5425> A_IWL<5424> A_IWL<5423> A_IWL<5422> A_IWL<5421> A_IWL<5420> A_IWL<5419> A_IWL<5418> A_IWL<5417> A_IWL<5416> A_IWL<5415> A_IWL<5414> A_IWL<5413> A_IWL<5412> A_IWL<5411> A_IWL<5410> A_IWL<5409> A_IWL<5408> A_IWL<5407> A_IWL<5406> A_IWL<5405> A_IWL<5404> A_IWL<5403> A_IWL<5402> A_IWL<5401> A_IWL<5400> A_IWL<5399> A_IWL<5398> A_IWL<5397> A_IWL<5396> A_IWL<5395> A_IWL<5394> A_IWL<5393> A_IWL<5392> A_IWL<5391> A_IWL<5390> A_IWL<5389> A_IWL<5388> A_IWL<5387> A_IWL<5386> A_IWL<5385> A_IWL<5384> A_IWL<5383> A_IWL<5382> A_IWL<5381> A_IWL<5380> A_IWL<5379> A_IWL<5378> A_IWL<5377> A_IWL<5376> VDD_CORE VSS / RM_IHPSG13_1024x32_c2_1P_COLUMN_pcell_0 +XCOL<20> A_BLC<41> A_BLC<40> A_BLC_TOP<41> A_BLC_TOP<40> A_BLT<41> A_BLT<40> A_BLT_TOP<41> A_BLT_TOP<40> A_IWL<5119> A_IWL<5118> A_IWL<5117> A_IWL<5116> A_IWL<5115> A_IWL<5114> A_IWL<5113> A_IWL<5112> A_IWL<5111> A_IWL<5110> A_IWL<5109> A_IWL<5108> A_IWL<5107> A_IWL<5106> A_IWL<5105> A_IWL<5104> A_IWL<5103> A_IWL<5102> A_IWL<5101> A_IWL<5100> A_IWL<5099> A_IWL<5098> A_IWL<5097> A_IWL<5096> A_IWL<5095> A_IWL<5094> A_IWL<5093> A_IWL<5092> A_IWL<5091> A_IWL<5090> A_IWL<5089> A_IWL<5088> A_IWL<5087> A_IWL<5086> A_IWL<5085> A_IWL<5084> A_IWL<5083> A_IWL<5082> A_IWL<5081> A_IWL<5080> A_IWL<5079> A_IWL<5078> A_IWL<5077> A_IWL<5076> A_IWL<5075> A_IWL<5074> A_IWL<5073> A_IWL<5072> A_IWL<5071> A_IWL<5070> A_IWL<5069> A_IWL<5068> A_IWL<5067> A_IWL<5066> A_IWL<5065> A_IWL<5064> A_IWL<5063> A_IWL<5062> A_IWL<5061> A_IWL<5060> A_IWL<5059> A_IWL<5058> A_IWL<5057> A_IWL<5056> A_IWL<5055> A_IWL<5054> A_IWL<5053> A_IWL<5052> A_IWL<5051> A_IWL<5050> A_IWL<5049> A_IWL<5048> A_IWL<5047> A_IWL<5046> A_IWL<5045> A_IWL<5044> A_IWL<5043> A_IWL<5042> A_IWL<5041> A_IWL<5040> A_IWL<5039> A_IWL<5038> A_IWL<5037> A_IWL<5036> A_IWL<5035> A_IWL<5034> A_IWL<5033> A_IWL<5032> A_IWL<5031> A_IWL<5030> A_IWL<5029> A_IWL<5028> A_IWL<5027> A_IWL<5026> A_IWL<5025> A_IWL<5024> A_IWL<5023> A_IWL<5022> A_IWL<5021> A_IWL<5020> A_IWL<5019> A_IWL<5018> A_IWL<5017> A_IWL<5016> A_IWL<5015> A_IWL<5014> A_IWL<5013> A_IWL<5012> A_IWL<5011> A_IWL<5010> A_IWL<5009> A_IWL<5008> A_IWL<5007> A_IWL<5006> A_IWL<5005> A_IWL<5004> A_IWL<5003> A_IWL<5002> A_IWL<5001> A_IWL<5000> A_IWL<4999> A_IWL<4998> A_IWL<4997> A_IWL<4996> A_IWL<4995> A_IWL<4994> A_IWL<4993> A_IWL<4992> A_IWL<4991> A_IWL<4990> A_IWL<4989> A_IWL<4988> A_IWL<4987> A_IWL<4986> A_IWL<4985> A_IWL<4984> A_IWL<4983> A_IWL<4982> A_IWL<4981> A_IWL<4980> A_IWL<4979> A_IWL<4978> A_IWL<4977> A_IWL<4976> A_IWL<4975> A_IWL<4974> A_IWL<4973> A_IWL<4972> A_IWL<4971> A_IWL<4970> A_IWL<4969> A_IWL<4968> A_IWL<4967> A_IWL<4966> A_IWL<4965> A_IWL<4964> A_IWL<4963> A_IWL<4962> A_IWL<4961> A_IWL<4960> A_IWL<4959> A_IWL<4958> A_IWL<4957> A_IWL<4956> A_IWL<4955> A_IWL<4954> A_IWL<4953> A_IWL<4952> A_IWL<4951> A_IWL<4950> A_IWL<4949> A_IWL<4948> A_IWL<4947> A_IWL<4946> A_IWL<4945> A_IWL<4944> A_IWL<4943> A_IWL<4942> A_IWL<4941> A_IWL<4940> A_IWL<4939> A_IWL<4938> A_IWL<4937> A_IWL<4936> A_IWL<4935> A_IWL<4934> A_IWL<4933> A_IWL<4932> A_IWL<4931> A_IWL<4930> A_IWL<4929> A_IWL<4928> A_IWL<4927> A_IWL<4926> A_IWL<4925> A_IWL<4924> A_IWL<4923> A_IWL<4922> A_IWL<4921> A_IWL<4920> A_IWL<4919> A_IWL<4918> A_IWL<4917> A_IWL<4916> A_IWL<4915> A_IWL<4914> A_IWL<4913> A_IWL<4912> A_IWL<4911> A_IWL<4910> A_IWL<4909> A_IWL<4908> A_IWL<4907> A_IWL<4906> A_IWL<4905> A_IWL<4904> A_IWL<4903> A_IWL<4902> A_IWL<4901> A_IWL<4900> A_IWL<4899> A_IWL<4898> A_IWL<4897> A_IWL<4896> A_IWL<4895> A_IWL<4894> A_IWL<4893> A_IWL<4892> A_IWL<4891> A_IWL<4890> A_IWL<4889> A_IWL<4888> A_IWL<4887> A_IWL<4886> A_IWL<4885> A_IWL<4884> A_IWL<4883> A_IWL<4882> A_IWL<4881> A_IWL<4880> A_IWL<4879> A_IWL<4878> A_IWL<4877> A_IWL<4876> A_IWL<4875> A_IWL<4874> A_IWL<4873> A_IWL<4872> A_IWL<4871> A_IWL<4870> A_IWL<4869> A_IWL<4868> A_IWL<4867> A_IWL<4866> A_IWL<4865> A_IWL<4864> A_IWL<5375> A_IWL<5374> A_IWL<5373> A_IWL<5372> A_IWL<5371> A_IWL<5370> A_IWL<5369> A_IWL<5368> A_IWL<5367> A_IWL<5366> A_IWL<5365> A_IWL<5364> A_IWL<5363> A_IWL<5362> A_IWL<5361> A_IWL<5360> A_IWL<5359> A_IWL<5358> A_IWL<5357> A_IWL<5356> A_IWL<5355> A_IWL<5354> A_IWL<5353> A_IWL<5352> A_IWL<5351> A_IWL<5350> A_IWL<5349> A_IWL<5348> A_IWL<5347> A_IWL<5346> A_IWL<5345> A_IWL<5344> A_IWL<5343> A_IWL<5342> A_IWL<5341> A_IWL<5340> A_IWL<5339> A_IWL<5338> A_IWL<5337> A_IWL<5336> A_IWL<5335> A_IWL<5334> A_IWL<5333> A_IWL<5332> A_IWL<5331> A_IWL<5330> A_IWL<5329> A_IWL<5328> A_IWL<5327> A_IWL<5326> A_IWL<5325> A_IWL<5324> A_IWL<5323> A_IWL<5322> A_IWL<5321> A_IWL<5320> A_IWL<5319> A_IWL<5318> A_IWL<5317> A_IWL<5316> A_IWL<5315> A_IWL<5314> A_IWL<5313> A_IWL<5312> A_IWL<5311> A_IWL<5310> A_IWL<5309> A_IWL<5308> A_IWL<5307> A_IWL<5306> A_IWL<5305> A_IWL<5304> A_IWL<5303> A_IWL<5302> A_IWL<5301> A_IWL<5300> A_IWL<5299> A_IWL<5298> A_IWL<5297> A_IWL<5296> A_IWL<5295> A_IWL<5294> A_IWL<5293> A_IWL<5292> A_IWL<5291> A_IWL<5290> A_IWL<5289> A_IWL<5288> A_IWL<5287> A_IWL<5286> A_IWL<5285> A_IWL<5284> A_IWL<5283> A_IWL<5282> A_IWL<5281> A_IWL<5280> A_IWL<5279> A_IWL<5278> A_IWL<5277> A_IWL<5276> A_IWL<5275> A_IWL<5274> A_IWL<5273> A_IWL<5272> A_IWL<5271> A_IWL<5270> A_IWL<5269> A_IWL<5268> A_IWL<5267> A_IWL<5266> A_IWL<5265> A_IWL<5264> A_IWL<5263> A_IWL<5262> A_IWL<5261> A_IWL<5260> A_IWL<5259> A_IWL<5258> A_IWL<5257> A_IWL<5256> A_IWL<5255> A_IWL<5254> A_IWL<5253> A_IWL<5252> A_IWL<5251> A_IWL<5250> A_IWL<5249> A_IWL<5248> A_IWL<5247> A_IWL<5246> A_IWL<5245> A_IWL<5244> A_IWL<5243> A_IWL<5242> A_IWL<5241> A_IWL<5240> A_IWL<5239> A_IWL<5238> A_IWL<5237> A_IWL<5236> A_IWL<5235> A_IWL<5234> A_IWL<5233> A_IWL<5232> A_IWL<5231> A_IWL<5230> A_IWL<5229> A_IWL<5228> A_IWL<5227> A_IWL<5226> A_IWL<5225> A_IWL<5224> A_IWL<5223> A_IWL<5222> A_IWL<5221> A_IWL<5220> A_IWL<5219> A_IWL<5218> A_IWL<5217> A_IWL<5216> A_IWL<5215> A_IWL<5214> A_IWL<5213> A_IWL<5212> A_IWL<5211> A_IWL<5210> A_IWL<5209> A_IWL<5208> A_IWL<5207> A_IWL<5206> A_IWL<5205> A_IWL<5204> A_IWL<5203> A_IWL<5202> A_IWL<5201> A_IWL<5200> A_IWL<5199> A_IWL<5198> A_IWL<5197> A_IWL<5196> A_IWL<5195> A_IWL<5194> A_IWL<5193> A_IWL<5192> A_IWL<5191> A_IWL<5190> A_IWL<5189> A_IWL<5188> A_IWL<5187> A_IWL<5186> A_IWL<5185> A_IWL<5184> A_IWL<5183> A_IWL<5182> A_IWL<5181> A_IWL<5180> A_IWL<5179> A_IWL<5178> A_IWL<5177> A_IWL<5176> A_IWL<5175> A_IWL<5174> A_IWL<5173> A_IWL<5172> A_IWL<5171> A_IWL<5170> A_IWL<5169> A_IWL<5168> A_IWL<5167> A_IWL<5166> A_IWL<5165> A_IWL<5164> A_IWL<5163> A_IWL<5162> A_IWL<5161> A_IWL<5160> A_IWL<5159> A_IWL<5158> A_IWL<5157> A_IWL<5156> A_IWL<5155> A_IWL<5154> A_IWL<5153> A_IWL<5152> A_IWL<5151> A_IWL<5150> A_IWL<5149> A_IWL<5148> A_IWL<5147> A_IWL<5146> A_IWL<5145> A_IWL<5144> A_IWL<5143> A_IWL<5142> A_IWL<5141> A_IWL<5140> A_IWL<5139> A_IWL<5138> A_IWL<5137> A_IWL<5136> A_IWL<5135> A_IWL<5134> A_IWL<5133> A_IWL<5132> A_IWL<5131> A_IWL<5130> A_IWL<5129> A_IWL<5128> A_IWL<5127> A_IWL<5126> A_IWL<5125> A_IWL<5124> A_IWL<5123> A_IWL<5122> A_IWL<5121> A_IWL<5120> VDD_CORE VSS / RM_IHPSG13_1024x32_c2_1P_COLUMN_pcell_0 +XCOL<19> A_BLC<39> A_BLC<38> A_BLC_TOP<39> A_BLC_TOP<38> A_BLT<39> A_BLT<38> A_BLT_TOP<39> A_BLT_TOP<38> A_IWL<4863> A_IWL<4862> A_IWL<4861> A_IWL<4860> A_IWL<4859> A_IWL<4858> A_IWL<4857> A_IWL<4856> A_IWL<4855> A_IWL<4854> A_IWL<4853> A_IWL<4852> A_IWL<4851> A_IWL<4850> A_IWL<4849> A_IWL<4848> A_IWL<4847> A_IWL<4846> A_IWL<4845> A_IWL<4844> A_IWL<4843> A_IWL<4842> A_IWL<4841> A_IWL<4840> A_IWL<4839> A_IWL<4838> A_IWL<4837> A_IWL<4836> A_IWL<4835> A_IWL<4834> A_IWL<4833> A_IWL<4832> A_IWL<4831> A_IWL<4830> A_IWL<4829> A_IWL<4828> A_IWL<4827> A_IWL<4826> A_IWL<4825> A_IWL<4824> A_IWL<4823> A_IWL<4822> A_IWL<4821> A_IWL<4820> A_IWL<4819> A_IWL<4818> A_IWL<4817> A_IWL<4816> A_IWL<4815> A_IWL<4814> A_IWL<4813> A_IWL<4812> A_IWL<4811> A_IWL<4810> A_IWL<4809> A_IWL<4808> A_IWL<4807> A_IWL<4806> A_IWL<4805> A_IWL<4804> A_IWL<4803> A_IWL<4802> A_IWL<4801> A_IWL<4800> A_IWL<4799> A_IWL<4798> A_IWL<4797> A_IWL<4796> A_IWL<4795> A_IWL<4794> A_IWL<4793> A_IWL<4792> A_IWL<4791> A_IWL<4790> A_IWL<4789> A_IWL<4788> A_IWL<4787> A_IWL<4786> A_IWL<4785> A_IWL<4784> A_IWL<4783> A_IWL<4782> A_IWL<4781> A_IWL<4780> A_IWL<4779> A_IWL<4778> A_IWL<4777> A_IWL<4776> A_IWL<4775> A_IWL<4774> A_IWL<4773> A_IWL<4772> A_IWL<4771> A_IWL<4770> A_IWL<4769> A_IWL<4768> A_IWL<4767> A_IWL<4766> A_IWL<4765> A_IWL<4764> A_IWL<4763> A_IWL<4762> A_IWL<4761> A_IWL<4760> A_IWL<4759> A_IWL<4758> A_IWL<4757> A_IWL<4756> A_IWL<4755> A_IWL<4754> A_IWL<4753> A_IWL<4752> A_IWL<4751> A_IWL<4750> A_IWL<4749> A_IWL<4748> A_IWL<4747> A_IWL<4746> A_IWL<4745> A_IWL<4744> A_IWL<4743> A_IWL<4742> A_IWL<4741> A_IWL<4740> A_IWL<4739> A_IWL<4738> A_IWL<4737> A_IWL<4736> A_IWL<4735> A_IWL<4734> A_IWL<4733> A_IWL<4732> A_IWL<4731> A_IWL<4730> A_IWL<4729> A_IWL<4728> A_IWL<4727> A_IWL<4726> A_IWL<4725> A_IWL<4724> A_IWL<4723> A_IWL<4722> A_IWL<4721> A_IWL<4720> A_IWL<4719> A_IWL<4718> A_IWL<4717> A_IWL<4716> A_IWL<4715> A_IWL<4714> A_IWL<4713> A_IWL<4712> A_IWL<4711> A_IWL<4710> A_IWL<4709> A_IWL<4708> A_IWL<4707> A_IWL<4706> A_IWL<4705> A_IWL<4704> A_IWL<4703> A_IWL<4702> A_IWL<4701> A_IWL<4700> A_IWL<4699> A_IWL<4698> A_IWL<4697> A_IWL<4696> A_IWL<4695> A_IWL<4694> A_IWL<4693> A_IWL<4692> A_IWL<4691> A_IWL<4690> A_IWL<4689> A_IWL<4688> A_IWL<4687> A_IWL<4686> A_IWL<4685> A_IWL<4684> A_IWL<4683> A_IWL<4682> A_IWL<4681> A_IWL<4680> A_IWL<4679> A_IWL<4678> A_IWL<4677> A_IWL<4676> A_IWL<4675> A_IWL<4674> A_IWL<4673> A_IWL<4672> A_IWL<4671> A_IWL<4670> A_IWL<4669> A_IWL<4668> A_IWL<4667> A_IWL<4666> A_IWL<4665> A_IWL<4664> A_IWL<4663> A_IWL<4662> A_IWL<4661> A_IWL<4660> A_IWL<4659> A_IWL<4658> A_IWL<4657> A_IWL<4656> A_IWL<4655> A_IWL<4654> A_IWL<4653> A_IWL<4652> A_IWL<4651> A_IWL<4650> A_IWL<4649> A_IWL<4648> A_IWL<4647> A_IWL<4646> A_IWL<4645> A_IWL<4644> A_IWL<4643> A_IWL<4642> A_IWL<4641> A_IWL<4640> A_IWL<4639> A_IWL<4638> A_IWL<4637> A_IWL<4636> A_IWL<4635> A_IWL<4634> A_IWL<4633> A_IWL<4632> A_IWL<4631> A_IWL<4630> A_IWL<4629> A_IWL<4628> A_IWL<4627> A_IWL<4626> A_IWL<4625> A_IWL<4624> A_IWL<4623> A_IWL<4622> A_IWL<4621> A_IWL<4620> A_IWL<4619> A_IWL<4618> A_IWL<4617> A_IWL<4616> A_IWL<4615> A_IWL<4614> A_IWL<4613> A_IWL<4612> A_IWL<4611> A_IWL<4610> A_IWL<4609> A_IWL<4608> A_IWL<5119> A_IWL<5118> A_IWL<5117> A_IWL<5116> A_IWL<5115> A_IWL<5114> A_IWL<5113> A_IWL<5112> A_IWL<5111> A_IWL<5110> A_IWL<5109> A_IWL<5108> A_IWL<5107> A_IWL<5106> A_IWL<5105> A_IWL<5104> A_IWL<5103> A_IWL<5102> A_IWL<5101> A_IWL<5100> A_IWL<5099> A_IWL<5098> A_IWL<5097> A_IWL<5096> A_IWL<5095> A_IWL<5094> A_IWL<5093> A_IWL<5092> A_IWL<5091> A_IWL<5090> A_IWL<5089> A_IWL<5088> A_IWL<5087> A_IWL<5086> A_IWL<5085> A_IWL<5084> A_IWL<5083> A_IWL<5082> A_IWL<5081> A_IWL<5080> A_IWL<5079> A_IWL<5078> A_IWL<5077> A_IWL<5076> A_IWL<5075> A_IWL<5074> A_IWL<5073> A_IWL<5072> A_IWL<5071> A_IWL<5070> A_IWL<5069> A_IWL<5068> A_IWL<5067> A_IWL<5066> A_IWL<5065> A_IWL<5064> A_IWL<5063> A_IWL<5062> A_IWL<5061> A_IWL<5060> A_IWL<5059> A_IWL<5058> A_IWL<5057> A_IWL<5056> A_IWL<5055> A_IWL<5054> A_IWL<5053> A_IWL<5052> A_IWL<5051> A_IWL<5050> A_IWL<5049> A_IWL<5048> A_IWL<5047> A_IWL<5046> A_IWL<5045> A_IWL<5044> A_IWL<5043> A_IWL<5042> A_IWL<5041> A_IWL<5040> A_IWL<5039> A_IWL<5038> A_IWL<5037> A_IWL<5036> A_IWL<5035> A_IWL<5034> A_IWL<5033> A_IWL<5032> A_IWL<5031> A_IWL<5030> A_IWL<5029> A_IWL<5028> A_IWL<5027> A_IWL<5026> A_IWL<5025> A_IWL<5024> A_IWL<5023> A_IWL<5022> A_IWL<5021> A_IWL<5020> A_IWL<5019> A_IWL<5018> A_IWL<5017> A_IWL<5016> A_IWL<5015> A_IWL<5014> A_IWL<5013> A_IWL<5012> A_IWL<5011> A_IWL<5010> A_IWL<5009> A_IWL<5008> A_IWL<5007> A_IWL<5006> A_IWL<5005> A_IWL<5004> A_IWL<5003> A_IWL<5002> A_IWL<5001> A_IWL<5000> A_IWL<4999> A_IWL<4998> A_IWL<4997> A_IWL<4996> A_IWL<4995> A_IWL<4994> A_IWL<4993> A_IWL<4992> A_IWL<4991> A_IWL<4990> A_IWL<4989> A_IWL<4988> A_IWL<4987> A_IWL<4986> A_IWL<4985> A_IWL<4984> A_IWL<4983> A_IWL<4982> A_IWL<4981> A_IWL<4980> A_IWL<4979> A_IWL<4978> A_IWL<4977> A_IWL<4976> A_IWL<4975> A_IWL<4974> A_IWL<4973> A_IWL<4972> A_IWL<4971> A_IWL<4970> A_IWL<4969> A_IWL<4968> A_IWL<4967> A_IWL<4966> A_IWL<4965> A_IWL<4964> A_IWL<4963> A_IWL<4962> A_IWL<4961> A_IWL<4960> A_IWL<4959> A_IWL<4958> A_IWL<4957> A_IWL<4956> A_IWL<4955> A_IWL<4954> A_IWL<4953> A_IWL<4952> A_IWL<4951> A_IWL<4950> A_IWL<4949> A_IWL<4948> A_IWL<4947> A_IWL<4946> A_IWL<4945> A_IWL<4944> A_IWL<4943> A_IWL<4942> A_IWL<4941> A_IWL<4940> A_IWL<4939> A_IWL<4938> A_IWL<4937> A_IWL<4936> A_IWL<4935> A_IWL<4934> A_IWL<4933> A_IWL<4932> A_IWL<4931> A_IWL<4930> A_IWL<4929> A_IWL<4928> A_IWL<4927> A_IWL<4926> A_IWL<4925> A_IWL<4924> A_IWL<4923> A_IWL<4922> A_IWL<4921> A_IWL<4920> A_IWL<4919> A_IWL<4918> A_IWL<4917> A_IWL<4916> A_IWL<4915> A_IWL<4914> A_IWL<4913> A_IWL<4912> A_IWL<4911> A_IWL<4910> A_IWL<4909> A_IWL<4908> A_IWL<4907> A_IWL<4906> A_IWL<4905> A_IWL<4904> A_IWL<4903> A_IWL<4902> A_IWL<4901> A_IWL<4900> A_IWL<4899> A_IWL<4898> A_IWL<4897> A_IWL<4896> A_IWL<4895> A_IWL<4894> A_IWL<4893> A_IWL<4892> A_IWL<4891> A_IWL<4890> A_IWL<4889> A_IWL<4888> A_IWL<4887> A_IWL<4886> A_IWL<4885> A_IWL<4884> A_IWL<4883> A_IWL<4882> A_IWL<4881> A_IWL<4880> A_IWL<4879> A_IWL<4878> A_IWL<4877> A_IWL<4876> A_IWL<4875> A_IWL<4874> A_IWL<4873> A_IWL<4872> A_IWL<4871> A_IWL<4870> A_IWL<4869> A_IWL<4868> A_IWL<4867> A_IWL<4866> A_IWL<4865> A_IWL<4864> VDD_CORE VSS / RM_IHPSG13_1024x32_c2_1P_COLUMN_pcell_0 +XCOL<18> A_BLC<37> A_BLC<36> A_BLC_TOP<37> A_BLC_TOP<36> A_BLT<37> A_BLT<36> A_BLT_TOP<37> A_BLT_TOP<36> A_IWL<4607> A_IWL<4606> A_IWL<4605> A_IWL<4604> A_IWL<4603> A_IWL<4602> A_IWL<4601> A_IWL<4600> A_IWL<4599> A_IWL<4598> A_IWL<4597> A_IWL<4596> A_IWL<4595> A_IWL<4594> A_IWL<4593> A_IWL<4592> A_IWL<4591> A_IWL<4590> A_IWL<4589> A_IWL<4588> A_IWL<4587> A_IWL<4586> A_IWL<4585> A_IWL<4584> A_IWL<4583> A_IWL<4582> A_IWL<4581> A_IWL<4580> A_IWL<4579> A_IWL<4578> A_IWL<4577> A_IWL<4576> A_IWL<4575> A_IWL<4574> A_IWL<4573> A_IWL<4572> A_IWL<4571> A_IWL<4570> A_IWL<4569> A_IWL<4568> A_IWL<4567> A_IWL<4566> A_IWL<4565> A_IWL<4564> A_IWL<4563> A_IWL<4562> A_IWL<4561> A_IWL<4560> A_IWL<4559> A_IWL<4558> A_IWL<4557> A_IWL<4556> A_IWL<4555> A_IWL<4554> A_IWL<4553> A_IWL<4552> A_IWL<4551> A_IWL<4550> A_IWL<4549> A_IWL<4548> A_IWL<4547> A_IWL<4546> A_IWL<4545> A_IWL<4544> A_IWL<4543> A_IWL<4542> A_IWL<4541> A_IWL<4540> A_IWL<4539> A_IWL<4538> A_IWL<4537> A_IWL<4536> A_IWL<4535> A_IWL<4534> A_IWL<4533> A_IWL<4532> A_IWL<4531> A_IWL<4530> A_IWL<4529> A_IWL<4528> A_IWL<4527> A_IWL<4526> A_IWL<4525> A_IWL<4524> A_IWL<4523> A_IWL<4522> A_IWL<4521> A_IWL<4520> A_IWL<4519> A_IWL<4518> A_IWL<4517> A_IWL<4516> A_IWL<4515> A_IWL<4514> A_IWL<4513> A_IWL<4512> A_IWL<4511> A_IWL<4510> A_IWL<4509> A_IWL<4508> A_IWL<4507> A_IWL<4506> A_IWL<4505> A_IWL<4504> A_IWL<4503> A_IWL<4502> A_IWL<4501> A_IWL<4500> A_IWL<4499> A_IWL<4498> A_IWL<4497> A_IWL<4496> A_IWL<4495> A_IWL<4494> A_IWL<4493> A_IWL<4492> A_IWL<4491> A_IWL<4490> A_IWL<4489> A_IWL<4488> A_IWL<4487> A_IWL<4486> A_IWL<4485> A_IWL<4484> A_IWL<4483> A_IWL<4482> A_IWL<4481> A_IWL<4480> A_IWL<4479> A_IWL<4478> A_IWL<4477> A_IWL<4476> A_IWL<4475> A_IWL<4474> A_IWL<4473> A_IWL<4472> A_IWL<4471> A_IWL<4470> A_IWL<4469> A_IWL<4468> A_IWL<4467> A_IWL<4466> A_IWL<4465> A_IWL<4464> A_IWL<4463> A_IWL<4462> A_IWL<4461> A_IWL<4460> A_IWL<4459> A_IWL<4458> A_IWL<4457> A_IWL<4456> A_IWL<4455> A_IWL<4454> A_IWL<4453> A_IWL<4452> A_IWL<4451> A_IWL<4450> A_IWL<4449> A_IWL<4448> A_IWL<4447> A_IWL<4446> A_IWL<4445> A_IWL<4444> A_IWL<4443> A_IWL<4442> A_IWL<4441> A_IWL<4440> A_IWL<4439> A_IWL<4438> A_IWL<4437> A_IWL<4436> A_IWL<4435> A_IWL<4434> A_IWL<4433> A_IWL<4432> A_IWL<4431> A_IWL<4430> A_IWL<4429> A_IWL<4428> A_IWL<4427> A_IWL<4426> A_IWL<4425> A_IWL<4424> A_IWL<4423> A_IWL<4422> A_IWL<4421> A_IWL<4420> A_IWL<4419> A_IWL<4418> A_IWL<4417> A_IWL<4416> A_IWL<4415> A_IWL<4414> A_IWL<4413> A_IWL<4412> A_IWL<4411> A_IWL<4410> A_IWL<4409> A_IWL<4408> A_IWL<4407> A_IWL<4406> A_IWL<4405> A_IWL<4404> A_IWL<4403> A_IWL<4402> A_IWL<4401> A_IWL<4400> A_IWL<4399> A_IWL<4398> A_IWL<4397> A_IWL<4396> A_IWL<4395> A_IWL<4394> A_IWL<4393> A_IWL<4392> A_IWL<4391> A_IWL<4390> A_IWL<4389> A_IWL<4388> A_IWL<4387> A_IWL<4386> A_IWL<4385> A_IWL<4384> A_IWL<4383> A_IWL<4382> A_IWL<4381> A_IWL<4380> A_IWL<4379> A_IWL<4378> A_IWL<4377> A_IWL<4376> A_IWL<4375> A_IWL<4374> A_IWL<4373> A_IWL<4372> A_IWL<4371> A_IWL<4370> A_IWL<4369> A_IWL<4368> A_IWL<4367> A_IWL<4366> A_IWL<4365> A_IWL<4364> A_IWL<4363> A_IWL<4362> A_IWL<4361> A_IWL<4360> A_IWL<4359> A_IWL<4358> A_IWL<4357> A_IWL<4356> A_IWL<4355> A_IWL<4354> A_IWL<4353> A_IWL<4352> A_IWL<4863> A_IWL<4862> A_IWL<4861> A_IWL<4860> A_IWL<4859> A_IWL<4858> A_IWL<4857> A_IWL<4856> A_IWL<4855> A_IWL<4854> A_IWL<4853> A_IWL<4852> A_IWL<4851> A_IWL<4850> A_IWL<4849> A_IWL<4848> A_IWL<4847> A_IWL<4846> A_IWL<4845> A_IWL<4844> A_IWL<4843> A_IWL<4842> A_IWL<4841> A_IWL<4840> A_IWL<4839> A_IWL<4838> A_IWL<4837> A_IWL<4836> A_IWL<4835> A_IWL<4834> A_IWL<4833> A_IWL<4832> A_IWL<4831> A_IWL<4830> A_IWL<4829> A_IWL<4828> A_IWL<4827> A_IWL<4826> A_IWL<4825> A_IWL<4824> A_IWL<4823> A_IWL<4822> A_IWL<4821> A_IWL<4820> A_IWL<4819> A_IWL<4818> A_IWL<4817> A_IWL<4816> A_IWL<4815> A_IWL<4814> A_IWL<4813> A_IWL<4812> A_IWL<4811> A_IWL<4810> A_IWL<4809> A_IWL<4808> A_IWL<4807> A_IWL<4806> A_IWL<4805> A_IWL<4804> A_IWL<4803> A_IWL<4802> A_IWL<4801> A_IWL<4800> A_IWL<4799> A_IWL<4798> A_IWL<4797> A_IWL<4796> A_IWL<4795> A_IWL<4794> A_IWL<4793> A_IWL<4792> A_IWL<4791> A_IWL<4790> A_IWL<4789> A_IWL<4788> A_IWL<4787> A_IWL<4786> A_IWL<4785> A_IWL<4784> A_IWL<4783> A_IWL<4782> A_IWL<4781> A_IWL<4780> A_IWL<4779> A_IWL<4778> A_IWL<4777> A_IWL<4776> A_IWL<4775> A_IWL<4774> A_IWL<4773> A_IWL<4772> A_IWL<4771> A_IWL<4770> A_IWL<4769> A_IWL<4768> A_IWL<4767> A_IWL<4766> A_IWL<4765> A_IWL<4764> A_IWL<4763> A_IWL<4762> A_IWL<4761> A_IWL<4760> A_IWL<4759> A_IWL<4758> A_IWL<4757> A_IWL<4756> A_IWL<4755> A_IWL<4754> A_IWL<4753> A_IWL<4752> A_IWL<4751> A_IWL<4750> A_IWL<4749> A_IWL<4748> A_IWL<4747> A_IWL<4746> A_IWL<4745> A_IWL<4744> A_IWL<4743> A_IWL<4742> A_IWL<4741> A_IWL<4740> A_IWL<4739> A_IWL<4738> A_IWL<4737> A_IWL<4736> A_IWL<4735> A_IWL<4734> A_IWL<4733> A_IWL<4732> A_IWL<4731> A_IWL<4730> A_IWL<4729> A_IWL<4728> A_IWL<4727> A_IWL<4726> A_IWL<4725> A_IWL<4724> A_IWL<4723> A_IWL<4722> A_IWL<4721> A_IWL<4720> A_IWL<4719> A_IWL<4718> A_IWL<4717> A_IWL<4716> A_IWL<4715> A_IWL<4714> A_IWL<4713> A_IWL<4712> A_IWL<4711> A_IWL<4710> A_IWL<4709> A_IWL<4708> A_IWL<4707> A_IWL<4706> A_IWL<4705> A_IWL<4704> A_IWL<4703> A_IWL<4702> A_IWL<4701> A_IWL<4700> A_IWL<4699> A_IWL<4698> A_IWL<4697> A_IWL<4696> A_IWL<4695> A_IWL<4694> A_IWL<4693> A_IWL<4692> A_IWL<4691> A_IWL<4690> A_IWL<4689> A_IWL<4688> A_IWL<4687> A_IWL<4686> A_IWL<4685> A_IWL<4684> A_IWL<4683> A_IWL<4682> A_IWL<4681> A_IWL<4680> A_IWL<4679> A_IWL<4678> A_IWL<4677> A_IWL<4676> A_IWL<4675> A_IWL<4674> A_IWL<4673> A_IWL<4672> A_IWL<4671> A_IWL<4670> A_IWL<4669> A_IWL<4668> A_IWL<4667> A_IWL<4666> A_IWL<4665> A_IWL<4664> A_IWL<4663> A_IWL<4662> A_IWL<4661> A_IWL<4660> A_IWL<4659> A_IWL<4658> A_IWL<4657> A_IWL<4656> A_IWL<4655> A_IWL<4654> A_IWL<4653> A_IWL<4652> A_IWL<4651> A_IWL<4650> A_IWL<4649> A_IWL<4648> A_IWL<4647> A_IWL<4646> A_IWL<4645> A_IWL<4644> A_IWL<4643> A_IWL<4642> A_IWL<4641> A_IWL<4640> A_IWL<4639> A_IWL<4638> A_IWL<4637> A_IWL<4636> A_IWL<4635> A_IWL<4634> A_IWL<4633> A_IWL<4632> A_IWL<4631> A_IWL<4630> A_IWL<4629> A_IWL<4628> A_IWL<4627> A_IWL<4626> A_IWL<4625> A_IWL<4624> A_IWL<4623> A_IWL<4622> A_IWL<4621> A_IWL<4620> A_IWL<4619> A_IWL<4618> A_IWL<4617> A_IWL<4616> A_IWL<4615> A_IWL<4614> A_IWL<4613> A_IWL<4612> A_IWL<4611> A_IWL<4610> A_IWL<4609> A_IWL<4608> VDD_CORE VSS / RM_IHPSG13_1024x32_c2_1P_COLUMN_pcell_0 +XCOL<17> A_BLC<35> A_BLC<34> A_BLC_TOP<35> A_BLC_TOP<34> A_BLT<35> A_BLT<34> A_BLT_TOP<35> A_BLT_TOP<34> A_IWL<4351> A_IWL<4350> A_IWL<4349> A_IWL<4348> A_IWL<4347> A_IWL<4346> A_IWL<4345> A_IWL<4344> A_IWL<4343> A_IWL<4342> A_IWL<4341> A_IWL<4340> A_IWL<4339> A_IWL<4338> A_IWL<4337> A_IWL<4336> A_IWL<4335> A_IWL<4334> A_IWL<4333> A_IWL<4332> A_IWL<4331> A_IWL<4330> A_IWL<4329> A_IWL<4328> A_IWL<4327> A_IWL<4326> A_IWL<4325> A_IWL<4324> A_IWL<4323> A_IWL<4322> A_IWL<4321> A_IWL<4320> A_IWL<4319> A_IWL<4318> A_IWL<4317> A_IWL<4316> A_IWL<4315> A_IWL<4314> A_IWL<4313> A_IWL<4312> A_IWL<4311> A_IWL<4310> A_IWL<4309> A_IWL<4308> A_IWL<4307> A_IWL<4306> A_IWL<4305> A_IWL<4304> A_IWL<4303> A_IWL<4302> A_IWL<4301> A_IWL<4300> A_IWL<4299> A_IWL<4298> A_IWL<4297> A_IWL<4296> A_IWL<4295> A_IWL<4294> A_IWL<4293> A_IWL<4292> A_IWL<4291> A_IWL<4290> A_IWL<4289> A_IWL<4288> A_IWL<4287> A_IWL<4286> A_IWL<4285> A_IWL<4284> A_IWL<4283> A_IWL<4282> A_IWL<4281> A_IWL<4280> A_IWL<4279> A_IWL<4278> A_IWL<4277> A_IWL<4276> A_IWL<4275> A_IWL<4274> A_IWL<4273> A_IWL<4272> A_IWL<4271> A_IWL<4270> A_IWL<4269> A_IWL<4268> A_IWL<4267> A_IWL<4266> A_IWL<4265> A_IWL<4264> A_IWL<4263> A_IWL<4262> A_IWL<4261> A_IWL<4260> A_IWL<4259> A_IWL<4258> A_IWL<4257> A_IWL<4256> A_IWL<4255> A_IWL<4254> A_IWL<4253> A_IWL<4252> A_IWL<4251> A_IWL<4250> A_IWL<4249> A_IWL<4248> A_IWL<4247> A_IWL<4246> A_IWL<4245> A_IWL<4244> A_IWL<4243> A_IWL<4242> A_IWL<4241> A_IWL<4240> A_IWL<4239> A_IWL<4238> A_IWL<4237> A_IWL<4236> A_IWL<4235> A_IWL<4234> A_IWL<4233> A_IWL<4232> A_IWL<4231> A_IWL<4230> A_IWL<4229> A_IWL<4228> A_IWL<4227> A_IWL<4226> A_IWL<4225> A_IWL<4224> A_IWL<4223> A_IWL<4222> A_IWL<4221> A_IWL<4220> A_IWL<4219> A_IWL<4218> A_IWL<4217> A_IWL<4216> A_IWL<4215> A_IWL<4214> A_IWL<4213> A_IWL<4212> A_IWL<4211> A_IWL<4210> A_IWL<4209> A_IWL<4208> A_IWL<4207> A_IWL<4206> A_IWL<4205> A_IWL<4204> A_IWL<4203> A_IWL<4202> A_IWL<4201> A_IWL<4200> A_IWL<4199> A_IWL<4198> A_IWL<4197> A_IWL<4196> A_IWL<4195> A_IWL<4194> A_IWL<4193> A_IWL<4192> A_IWL<4191> A_IWL<4190> A_IWL<4189> A_IWL<4188> A_IWL<4187> A_IWL<4186> A_IWL<4185> A_IWL<4184> A_IWL<4183> A_IWL<4182> A_IWL<4181> A_IWL<4180> A_IWL<4179> A_IWL<4178> A_IWL<4177> A_IWL<4176> A_IWL<4175> A_IWL<4174> A_IWL<4173> A_IWL<4172> A_IWL<4171> A_IWL<4170> A_IWL<4169> A_IWL<4168> A_IWL<4167> A_IWL<4166> A_IWL<4165> A_IWL<4164> A_IWL<4163> A_IWL<4162> A_IWL<4161> A_IWL<4160> A_IWL<4159> A_IWL<4158> A_IWL<4157> A_IWL<4156> A_IWL<4155> A_IWL<4154> A_IWL<4153> A_IWL<4152> A_IWL<4151> A_IWL<4150> A_IWL<4149> A_IWL<4148> A_IWL<4147> A_IWL<4146> A_IWL<4145> A_IWL<4144> A_IWL<4143> A_IWL<4142> A_IWL<4141> A_IWL<4140> A_IWL<4139> A_IWL<4138> A_IWL<4137> A_IWL<4136> A_IWL<4135> A_IWL<4134> A_IWL<4133> A_IWL<4132> A_IWL<4131> A_IWL<4130> A_IWL<4129> A_IWL<4128> A_IWL<4127> A_IWL<4126> A_IWL<4125> A_IWL<4124> A_IWL<4123> A_IWL<4122> A_IWL<4121> A_IWL<4120> A_IWL<4119> A_IWL<4118> A_IWL<4117> A_IWL<4116> A_IWL<4115> A_IWL<4114> A_IWL<4113> A_IWL<4112> A_IWL<4111> A_IWL<4110> A_IWL<4109> A_IWL<4108> A_IWL<4107> A_IWL<4106> A_IWL<4105> A_IWL<4104> A_IWL<4103> A_IWL<4102> A_IWL<4101> A_IWL<4100> A_IWL<4099> A_IWL<4098> A_IWL<4097> A_IWL<4096> A_IWL<4607> A_IWL<4606> A_IWL<4605> A_IWL<4604> A_IWL<4603> A_IWL<4602> A_IWL<4601> A_IWL<4600> A_IWL<4599> A_IWL<4598> A_IWL<4597> A_IWL<4596> A_IWL<4595> A_IWL<4594> A_IWL<4593> A_IWL<4592> A_IWL<4591> A_IWL<4590> A_IWL<4589> A_IWL<4588> A_IWL<4587> A_IWL<4586> A_IWL<4585> A_IWL<4584> A_IWL<4583> A_IWL<4582> A_IWL<4581> A_IWL<4580> A_IWL<4579> A_IWL<4578> A_IWL<4577> A_IWL<4576> A_IWL<4575> A_IWL<4574> A_IWL<4573> A_IWL<4572> A_IWL<4571> A_IWL<4570> A_IWL<4569> A_IWL<4568> A_IWL<4567> A_IWL<4566> A_IWL<4565> A_IWL<4564> A_IWL<4563> A_IWL<4562> A_IWL<4561> A_IWL<4560> A_IWL<4559> A_IWL<4558> A_IWL<4557> A_IWL<4556> A_IWL<4555> A_IWL<4554> A_IWL<4553> A_IWL<4552> A_IWL<4551> A_IWL<4550> A_IWL<4549> A_IWL<4548> A_IWL<4547> A_IWL<4546> A_IWL<4545> A_IWL<4544> A_IWL<4543> A_IWL<4542> A_IWL<4541> A_IWL<4540> A_IWL<4539> A_IWL<4538> A_IWL<4537> A_IWL<4536> A_IWL<4535> A_IWL<4534> A_IWL<4533> A_IWL<4532> A_IWL<4531> A_IWL<4530> A_IWL<4529> A_IWL<4528> A_IWL<4527> A_IWL<4526> A_IWL<4525> A_IWL<4524> A_IWL<4523> A_IWL<4522> A_IWL<4521> A_IWL<4520> A_IWL<4519> A_IWL<4518> A_IWL<4517> A_IWL<4516> A_IWL<4515> A_IWL<4514> A_IWL<4513> A_IWL<4512> A_IWL<4511> A_IWL<4510> A_IWL<4509> A_IWL<4508> A_IWL<4507> A_IWL<4506> A_IWL<4505> A_IWL<4504> A_IWL<4503> A_IWL<4502> A_IWL<4501> A_IWL<4500> A_IWL<4499> A_IWL<4498> A_IWL<4497> A_IWL<4496> A_IWL<4495> A_IWL<4494> A_IWL<4493> A_IWL<4492> A_IWL<4491> A_IWL<4490> A_IWL<4489> A_IWL<4488> A_IWL<4487> A_IWL<4486> A_IWL<4485> A_IWL<4484> A_IWL<4483> A_IWL<4482> A_IWL<4481> A_IWL<4480> A_IWL<4479> A_IWL<4478> A_IWL<4477> A_IWL<4476> A_IWL<4475> A_IWL<4474> A_IWL<4473> A_IWL<4472> A_IWL<4471> A_IWL<4470> A_IWL<4469> A_IWL<4468> A_IWL<4467> A_IWL<4466> A_IWL<4465> A_IWL<4464> A_IWL<4463> A_IWL<4462> A_IWL<4461> A_IWL<4460> A_IWL<4459> A_IWL<4458> A_IWL<4457> A_IWL<4456> A_IWL<4455> A_IWL<4454> A_IWL<4453> A_IWL<4452> A_IWL<4451> A_IWL<4450> A_IWL<4449> A_IWL<4448> A_IWL<4447> A_IWL<4446> A_IWL<4445> A_IWL<4444> A_IWL<4443> A_IWL<4442> A_IWL<4441> A_IWL<4440> A_IWL<4439> A_IWL<4438> A_IWL<4437> A_IWL<4436> A_IWL<4435> A_IWL<4434> A_IWL<4433> A_IWL<4432> A_IWL<4431> A_IWL<4430> A_IWL<4429> A_IWL<4428> A_IWL<4427> A_IWL<4426> A_IWL<4425> A_IWL<4424> A_IWL<4423> A_IWL<4422> A_IWL<4421> A_IWL<4420> A_IWL<4419> A_IWL<4418> A_IWL<4417> A_IWL<4416> A_IWL<4415> A_IWL<4414> A_IWL<4413> A_IWL<4412> A_IWL<4411> A_IWL<4410> A_IWL<4409> A_IWL<4408> A_IWL<4407> A_IWL<4406> A_IWL<4405> A_IWL<4404> A_IWL<4403> A_IWL<4402> A_IWL<4401> A_IWL<4400> A_IWL<4399> A_IWL<4398> A_IWL<4397> A_IWL<4396> A_IWL<4395> A_IWL<4394> A_IWL<4393> A_IWL<4392> A_IWL<4391> A_IWL<4390> A_IWL<4389> A_IWL<4388> A_IWL<4387> A_IWL<4386> A_IWL<4385> A_IWL<4384> A_IWL<4383> A_IWL<4382> A_IWL<4381> A_IWL<4380> A_IWL<4379> A_IWL<4378> A_IWL<4377> A_IWL<4376> A_IWL<4375> A_IWL<4374> A_IWL<4373> A_IWL<4372> A_IWL<4371> A_IWL<4370> A_IWL<4369> A_IWL<4368> A_IWL<4367> A_IWL<4366> A_IWL<4365> A_IWL<4364> A_IWL<4363> A_IWL<4362> A_IWL<4361> A_IWL<4360> A_IWL<4359> A_IWL<4358> A_IWL<4357> A_IWL<4356> A_IWL<4355> A_IWL<4354> A_IWL<4353> A_IWL<4352> VDD_CORE VSS / RM_IHPSG13_1024x32_c2_1P_COLUMN_pcell_0 +XCOL<16> A_BLC<33> A_BLC<32> A_BLC_TOP<33> A_BLC_TOP<32> A_BLT<33> A_BLT<32> A_BLT_TOP<33> A_BLT_TOP<32> A_IWL<4095> A_IWL<4094> A_IWL<4093> A_IWL<4092> A_IWL<4091> A_IWL<4090> A_IWL<4089> A_IWL<4088> A_IWL<4087> A_IWL<4086> A_IWL<4085> A_IWL<4084> A_IWL<4083> A_IWL<4082> A_IWL<4081> A_IWL<4080> A_IWL<4079> A_IWL<4078> A_IWL<4077> A_IWL<4076> A_IWL<4075> A_IWL<4074> A_IWL<4073> A_IWL<4072> A_IWL<4071> A_IWL<4070> A_IWL<4069> A_IWL<4068> A_IWL<4067> A_IWL<4066> A_IWL<4065> A_IWL<4064> A_IWL<4063> A_IWL<4062> A_IWL<4061> A_IWL<4060> A_IWL<4059> A_IWL<4058> A_IWL<4057> A_IWL<4056> A_IWL<4055> A_IWL<4054> A_IWL<4053> A_IWL<4052> A_IWL<4051> A_IWL<4050> A_IWL<4049> A_IWL<4048> A_IWL<4047> A_IWL<4046> A_IWL<4045> A_IWL<4044> A_IWL<4043> A_IWL<4042> A_IWL<4041> A_IWL<4040> A_IWL<4039> A_IWL<4038> A_IWL<4037> A_IWL<4036> A_IWL<4035> A_IWL<4034> A_IWL<4033> A_IWL<4032> A_IWL<4031> A_IWL<4030> A_IWL<4029> A_IWL<4028> A_IWL<4027> A_IWL<4026> A_IWL<4025> A_IWL<4024> A_IWL<4023> A_IWL<4022> A_IWL<4021> A_IWL<4020> A_IWL<4019> A_IWL<4018> A_IWL<4017> A_IWL<4016> A_IWL<4015> A_IWL<4014> A_IWL<4013> A_IWL<4012> A_IWL<4011> A_IWL<4010> A_IWL<4009> A_IWL<4008> A_IWL<4007> A_IWL<4006> A_IWL<4005> A_IWL<4004> A_IWL<4003> A_IWL<4002> A_IWL<4001> A_IWL<4000> A_IWL<3999> A_IWL<3998> A_IWL<3997> A_IWL<3996> A_IWL<3995> A_IWL<3994> A_IWL<3993> A_IWL<3992> A_IWL<3991> A_IWL<3990> A_IWL<3989> A_IWL<3988> A_IWL<3987> A_IWL<3986> A_IWL<3985> A_IWL<3984> A_IWL<3983> A_IWL<3982> A_IWL<3981> A_IWL<3980> A_IWL<3979> A_IWL<3978> A_IWL<3977> A_IWL<3976> A_IWL<3975> A_IWL<3974> A_IWL<3973> A_IWL<3972> A_IWL<3971> A_IWL<3970> A_IWL<3969> A_IWL<3968> A_IWL<3967> A_IWL<3966> A_IWL<3965> A_IWL<3964> A_IWL<3963> A_IWL<3962> A_IWL<3961> A_IWL<3960> A_IWL<3959> A_IWL<3958> A_IWL<3957> A_IWL<3956> A_IWL<3955> A_IWL<3954> A_IWL<3953> A_IWL<3952> A_IWL<3951> A_IWL<3950> A_IWL<3949> A_IWL<3948> A_IWL<3947> A_IWL<3946> A_IWL<3945> A_IWL<3944> A_IWL<3943> A_IWL<3942> A_IWL<3941> A_IWL<3940> A_IWL<3939> A_IWL<3938> A_IWL<3937> A_IWL<3936> A_IWL<3935> A_IWL<3934> A_IWL<3933> A_IWL<3932> A_IWL<3931> A_IWL<3930> A_IWL<3929> A_IWL<3928> A_IWL<3927> A_IWL<3926> A_IWL<3925> A_IWL<3924> A_IWL<3923> A_IWL<3922> A_IWL<3921> A_IWL<3920> A_IWL<3919> A_IWL<3918> A_IWL<3917> A_IWL<3916> A_IWL<3915> A_IWL<3914> A_IWL<3913> A_IWL<3912> A_IWL<3911> A_IWL<3910> A_IWL<3909> A_IWL<3908> A_IWL<3907> A_IWL<3906> A_IWL<3905> A_IWL<3904> A_IWL<3903> A_IWL<3902> A_IWL<3901> A_IWL<3900> A_IWL<3899> A_IWL<3898> A_IWL<3897> A_IWL<3896> A_IWL<3895> A_IWL<3894> A_IWL<3893> A_IWL<3892> A_IWL<3891> A_IWL<3890> A_IWL<3889> A_IWL<3888> A_IWL<3887> A_IWL<3886> A_IWL<3885> A_IWL<3884> A_IWL<3883> A_IWL<3882> A_IWL<3881> A_IWL<3880> A_IWL<3879> A_IWL<3878> A_IWL<3877> A_IWL<3876> A_IWL<3875> A_IWL<3874> A_IWL<3873> A_IWL<3872> A_IWL<3871> A_IWL<3870> A_IWL<3869> A_IWL<3868> A_IWL<3867> A_IWL<3866> A_IWL<3865> A_IWL<3864> A_IWL<3863> A_IWL<3862> A_IWL<3861> A_IWL<3860> A_IWL<3859> A_IWL<3858> A_IWL<3857> A_IWL<3856> A_IWL<3855> A_IWL<3854> A_IWL<3853> A_IWL<3852> A_IWL<3851> A_IWL<3850> A_IWL<3849> A_IWL<3848> A_IWL<3847> A_IWL<3846> A_IWL<3845> A_IWL<3844> A_IWL<3843> A_IWL<3842> A_IWL<3841> A_IWL<3840> A_IWL<4351> A_IWL<4350> A_IWL<4349> A_IWL<4348> A_IWL<4347> A_IWL<4346> A_IWL<4345> A_IWL<4344> A_IWL<4343> A_IWL<4342> A_IWL<4341> A_IWL<4340> A_IWL<4339> A_IWL<4338> A_IWL<4337> A_IWL<4336> A_IWL<4335> A_IWL<4334> A_IWL<4333> A_IWL<4332> A_IWL<4331> A_IWL<4330> A_IWL<4329> A_IWL<4328> A_IWL<4327> A_IWL<4326> A_IWL<4325> A_IWL<4324> A_IWL<4323> A_IWL<4322> A_IWL<4321> A_IWL<4320> A_IWL<4319> A_IWL<4318> A_IWL<4317> A_IWL<4316> A_IWL<4315> A_IWL<4314> A_IWL<4313> A_IWL<4312> A_IWL<4311> A_IWL<4310> A_IWL<4309> A_IWL<4308> A_IWL<4307> A_IWL<4306> A_IWL<4305> A_IWL<4304> A_IWL<4303> A_IWL<4302> A_IWL<4301> A_IWL<4300> A_IWL<4299> A_IWL<4298> A_IWL<4297> A_IWL<4296> A_IWL<4295> A_IWL<4294> A_IWL<4293> A_IWL<4292> A_IWL<4291> A_IWL<4290> A_IWL<4289> A_IWL<4288> A_IWL<4287> A_IWL<4286> A_IWL<4285> A_IWL<4284> A_IWL<4283> A_IWL<4282> A_IWL<4281> A_IWL<4280> A_IWL<4279> A_IWL<4278> A_IWL<4277> A_IWL<4276> A_IWL<4275> A_IWL<4274> A_IWL<4273> A_IWL<4272> A_IWL<4271> A_IWL<4270> A_IWL<4269> A_IWL<4268> A_IWL<4267> A_IWL<4266> A_IWL<4265> A_IWL<4264> A_IWL<4263> A_IWL<4262> A_IWL<4261> A_IWL<4260> A_IWL<4259> A_IWL<4258> A_IWL<4257> A_IWL<4256> A_IWL<4255> A_IWL<4254> A_IWL<4253> A_IWL<4252> A_IWL<4251> A_IWL<4250> A_IWL<4249> A_IWL<4248> A_IWL<4247> A_IWL<4246> A_IWL<4245> A_IWL<4244> A_IWL<4243> A_IWL<4242> A_IWL<4241> A_IWL<4240> A_IWL<4239> A_IWL<4238> A_IWL<4237> A_IWL<4236> A_IWL<4235> A_IWL<4234> A_IWL<4233> A_IWL<4232> A_IWL<4231> A_IWL<4230> A_IWL<4229> A_IWL<4228> A_IWL<4227> A_IWL<4226> A_IWL<4225> A_IWL<4224> A_IWL<4223> A_IWL<4222> A_IWL<4221> A_IWL<4220> A_IWL<4219> A_IWL<4218> A_IWL<4217> A_IWL<4216> A_IWL<4215> A_IWL<4214> A_IWL<4213> A_IWL<4212> A_IWL<4211> A_IWL<4210> A_IWL<4209> A_IWL<4208> A_IWL<4207> A_IWL<4206> A_IWL<4205> A_IWL<4204> A_IWL<4203> A_IWL<4202> A_IWL<4201> A_IWL<4200> A_IWL<4199> A_IWL<4198> A_IWL<4197> A_IWL<4196> A_IWL<4195> A_IWL<4194> A_IWL<4193> A_IWL<4192> A_IWL<4191> A_IWL<4190> A_IWL<4189> A_IWL<4188> A_IWL<4187> A_IWL<4186> A_IWL<4185> A_IWL<4184> A_IWL<4183> A_IWL<4182> A_IWL<4181> A_IWL<4180> A_IWL<4179> A_IWL<4178> A_IWL<4177> A_IWL<4176> A_IWL<4175> A_IWL<4174> A_IWL<4173> A_IWL<4172> A_IWL<4171> A_IWL<4170> A_IWL<4169> A_IWL<4168> A_IWL<4167> A_IWL<4166> A_IWL<4165> A_IWL<4164> A_IWL<4163> A_IWL<4162> A_IWL<4161> A_IWL<4160> A_IWL<4159> A_IWL<4158> A_IWL<4157> A_IWL<4156> A_IWL<4155> A_IWL<4154> A_IWL<4153> A_IWL<4152> A_IWL<4151> A_IWL<4150> A_IWL<4149> A_IWL<4148> A_IWL<4147> A_IWL<4146> A_IWL<4145> A_IWL<4144> A_IWL<4143> A_IWL<4142> A_IWL<4141> A_IWL<4140> A_IWL<4139> A_IWL<4138> A_IWL<4137> A_IWL<4136> A_IWL<4135> A_IWL<4134> A_IWL<4133> A_IWL<4132> A_IWL<4131> A_IWL<4130> A_IWL<4129> A_IWL<4128> A_IWL<4127> A_IWL<4126> A_IWL<4125> A_IWL<4124> A_IWL<4123> A_IWL<4122> A_IWL<4121> A_IWL<4120> A_IWL<4119> A_IWL<4118> A_IWL<4117> A_IWL<4116> A_IWL<4115> A_IWL<4114> A_IWL<4113> A_IWL<4112> A_IWL<4111> A_IWL<4110> A_IWL<4109> A_IWL<4108> A_IWL<4107> A_IWL<4106> A_IWL<4105> A_IWL<4104> A_IWL<4103> A_IWL<4102> A_IWL<4101> A_IWL<4100> A_IWL<4099> A_IWL<4098> A_IWL<4097> A_IWL<4096> VDD_CORE VSS / RM_IHPSG13_1024x32_c2_1P_COLUMN_pcell_0 +XCOL<15> A_BLC<31> A_BLC<30> A_BLC_TOP<31> A_BLC_TOP<30> A_BLT<31> A_BLT<30> A_BLT_TOP<31> A_BLT_TOP<30> A_IWL<3839> A_IWL<3838> A_IWL<3837> A_IWL<3836> A_IWL<3835> A_IWL<3834> A_IWL<3833> A_IWL<3832> A_IWL<3831> A_IWL<3830> A_IWL<3829> A_IWL<3828> A_IWL<3827> A_IWL<3826> A_IWL<3825> A_IWL<3824> A_IWL<3823> A_IWL<3822> A_IWL<3821> A_IWL<3820> A_IWL<3819> A_IWL<3818> A_IWL<3817> A_IWL<3816> A_IWL<3815> A_IWL<3814> A_IWL<3813> A_IWL<3812> A_IWL<3811> A_IWL<3810> A_IWL<3809> A_IWL<3808> A_IWL<3807> A_IWL<3806> A_IWL<3805> A_IWL<3804> A_IWL<3803> A_IWL<3802> A_IWL<3801> A_IWL<3800> A_IWL<3799> A_IWL<3798> A_IWL<3797> A_IWL<3796> A_IWL<3795> A_IWL<3794> A_IWL<3793> A_IWL<3792> A_IWL<3791> A_IWL<3790> A_IWL<3789> A_IWL<3788> A_IWL<3787> A_IWL<3786> A_IWL<3785> A_IWL<3784> A_IWL<3783> A_IWL<3782> A_IWL<3781> A_IWL<3780> A_IWL<3779> A_IWL<3778> A_IWL<3777> A_IWL<3776> A_IWL<3775> A_IWL<3774> A_IWL<3773> A_IWL<3772> A_IWL<3771> A_IWL<3770> A_IWL<3769> A_IWL<3768> A_IWL<3767> A_IWL<3766> A_IWL<3765> A_IWL<3764> A_IWL<3763> A_IWL<3762> A_IWL<3761> A_IWL<3760> A_IWL<3759> A_IWL<3758> A_IWL<3757> A_IWL<3756> A_IWL<3755> A_IWL<3754> A_IWL<3753> A_IWL<3752> A_IWL<3751> A_IWL<3750> A_IWL<3749> A_IWL<3748> A_IWL<3747> A_IWL<3746> A_IWL<3745> A_IWL<3744> A_IWL<3743> A_IWL<3742> A_IWL<3741> A_IWL<3740> A_IWL<3739> A_IWL<3738> A_IWL<3737> A_IWL<3736> A_IWL<3735> A_IWL<3734> A_IWL<3733> A_IWL<3732> A_IWL<3731> A_IWL<3730> A_IWL<3729> A_IWL<3728> A_IWL<3727> A_IWL<3726> A_IWL<3725> A_IWL<3724> A_IWL<3723> A_IWL<3722> A_IWL<3721> A_IWL<3720> A_IWL<3719> A_IWL<3718> A_IWL<3717> A_IWL<3716> A_IWL<3715> A_IWL<3714> A_IWL<3713> A_IWL<3712> A_IWL<3711> A_IWL<3710> A_IWL<3709> A_IWL<3708> A_IWL<3707> A_IWL<3706> A_IWL<3705> A_IWL<3704> A_IWL<3703> A_IWL<3702> A_IWL<3701> A_IWL<3700> A_IWL<3699> A_IWL<3698> A_IWL<3697> A_IWL<3696> A_IWL<3695> A_IWL<3694> A_IWL<3693> A_IWL<3692> A_IWL<3691> A_IWL<3690> A_IWL<3689> A_IWL<3688> A_IWL<3687> A_IWL<3686> A_IWL<3685> A_IWL<3684> A_IWL<3683> A_IWL<3682> A_IWL<3681> A_IWL<3680> A_IWL<3679> A_IWL<3678> A_IWL<3677> A_IWL<3676> A_IWL<3675> A_IWL<3674> A_IWL<3673> A_IWL<3672> A_IWL<3671> A_IWL<3670> A_IWL<3669> A_IWL<3668> A_IWL<3667> A_IWL<3666> A_IWL<3665> A_IWL<3664> A_IWL<3663> A_IWL<3662> A_IWL<3661> A_IWL<3660> A_IWL<3659> A_IWL<3658> A_IWL<3657> A_IWL<3656> A_IWL<3655> A_IWL<3654> A_IWL<3653> A_IWL<3652> A_IWL<3651> A_IWL<3650> A_IWL<3649> A_IWL<3648> A_IWL<3647> A_IWL<3646> A_IWL<3645> A_IWL<3644> A_IWL<3643> A_IWL<3642> A_IWL<3641> A_IWL<3640> A_IWL<3639> A_IWL<3638> A_IWL<3637> A_IWL<3636> A_IWL<3635> A_IWL<3634> A_IWL<3633> A_IWL<3632> A_IWL<3631> A_IWL<3630> A_IWL<3629> A_IWL<3628> A_IWL<3627> A_IWL<3626> A_IWL<3625> A_IWL<3624> A_IWL<3623> A_IWL<3622> A_IWL<3621> A_IWL<3620> A_IWL<3619> A_IWL<3618> A_IWL<3617> A_IWL<3616> A_IWL<3615> A_IWL<3614> A_IWL<3613> A_IWL<3612> A_IWL<3611> A_IWL<3610> A_IWL<3609> A_IWL<3608> A_IWL<3607> A_IWL<3606> A_IWL<3605> A_IWL<3604> A_IWL<3603> A_IWL<3602> A_IWL<3601> A_IWL<3600> A_IWL<3599> A_IWL<3598> A_IWL<3597> A_IWL<3596> A_IWL<3595> A_IWL<3594> A_IWL<3593> A_IWL<3592> A_IWL<3591> A_IWL<3590> A_IWL<3589> A_IWL<3588> A_IWL<3587> A_IWL<3586> A_IWL<3585> A_IWL<3584> A_IWL<4095> A_IWL<4094> A_IWL<4093> A_IWL<4092> A_IWL<4091> A_IWL<4090> A_IWL<4089> A_IWL<4088> A_IWL<4087> A_IWL<4086> A_IWL<4085> A_IWL<4084> A_IWL<4083> A_IWL<4082> A_IWL<4081> A_IWL<4080> A_IWL<4079> A_IWL<4078> A_IWL<4077> A_IWL<4076> A_IWL<4075> A_IWL<4074> A_IWL<4073> A_IWL<4072> A_IWL<4071> A_IWL<4070> A_IWL<4069> A_IWL<4068> A_IWL<4067> A_IWL<4066> A_IWL<4065> A_IWL<4064> A_IWL<4063> A_IWL<4062> A_IWL<4061> A_IWL<4060> A_IWL<4059> A_IWL<4058> A_IWL<4057> A_IWL<4056> A_IWL<4055> A_IWL<4054> A_IWL<4053> A_IWL<4052> A_IWL<4051> A_IWL<4050> A_IWL<4049> A_IWL<4048> A_IWL<4047> A_IWL<4046> A_IWL<4045> A_IWL<4044> A_IWL<4043> A_IWL<4042> A_IWL<4041> A_IWL<4040> A_IWL<4039> A_IWL<4038> A_IWL<4037> A_IWL<4036> A_IWL<4035> A_IWL<4034> A_IWL<4033> A_IWL<4032> A_IWL<4031> A_IWL<4030> A_IWL<4029> A_IWL<4028> A_IWL<4027> A_IWL<4026> A_IWL<4025> A_IWL<4024> A_IWL<4023> A_IWL<4022> A_IWL<4021> A_IWL<4020> A_IWL<4019> A_IWL<4018> A_IWL<4017> A_IWL<4016> A_IWL<4015> A_IWL<4014> A_IWL<4013> A_IWL<4012> A_IWL<4011> A_IWL<4010> A_IWL<4009> A_IWL<4008> A_IWL<4007> A_IWL<4006> A_IWL<4005> A_IWL<4004> A_IWL<4003> A_IWL<4002> A_IWL<4001> A_IWL<4000> A_IWL<3999> A_IWL<3998> A_IWL<3997> A_IWL<3996> A_IWL<3995> A_IWL<3994> A_IWL<3993> A_IWL<3992> A_IWL<3991> A_IWL<3990> A_IWL<3989> A_IWL<3988> A_IWL<3987> A_IWL<3986> A_IWL<3985> A_IWL<3984> A_IWL<3983> A_IWL<3982> A_IWL<3981> A_IWL<3980> A_IWL<3979> A_IWL<3978> A_IWL<3977> A_IWL<3976> A_IWL<3975> A_IWL<3974> A_IWL<3973> A_IWL<3972> A_IWL<3971> A_IWL<3970> A_IWL<3969> A_IWL<3968> A_IWL<3967> A_IWL<3966> A_IWL<3965> A_IWL<3964> A_IWL<3963> A_IWL<3962> A_IWL<3961> A_IWL<3960> A_IWL<3959> A_IWL<3958> A_IWL<3957> A_IWL<3956> A_IWL<3955> A_IWL<3954> A_IWL<3953> A_IWL<3952> A_IWL<3951> A_IWL<3950> A_IWL<3949> A_IWL<3948> A_IWL<3947> A_IWL<3946> A_IWL<3945> A_IWL<3944> A_IWL<3943> A_IWL<3942> A_IWL<3941> A_IWL<3940> A_IWL<3939> A_IWL<3938> A_IWL<3937> A_IWL<3936> A_IWL<3935> A_IWL<3934> A_IWL<3933> A_IWL<3932> A_IWL<3931> A_IWL<3930> A_IWL<3929> A_IWL<3928> A_IWL<3927> A_IWL<3926> A_IWL<3925> A_IWL<3924> A_IWL<3923> A_IWL<3922> A_IWL<3921> A_IWL<3920> A_IWL<3919> A_IWL<3918> A_IWL<3917> A_IWL<3916> A_IWL<3915> A_IWL<3914> A_IWL<3913> A_IWL<3912> A_IWL<3911> A_IWL<3910> A_IWL<3909> A_IWL<3908> A_IWL<3907> A_IWL<3906> A_IWL<3905> A_IWL<3904> A_IWL<3903> A_IWL<3902> A_IWL<3901> A_IWL<3900> A_IWL<3899> A_IWL<3898> A_IWL<3897> A_IWL<3896> A_IWL<3895> A_IWL<3894> A_IWL<3893> A_IWL<3892> A_IWL<3891> A_IWL<3890> A_IWL<3889> A_IWL<3888> A_IWL<3887> A_IWL<3886> A_IWL<3885> A_IWL<3884> A_IWL<3883> A_IWL<3882> A_IWL<3881> A_IWL<3880> A_IWL<3879> A_IWL<3878> A_IWL<3877> A_IWL<3876> A_IWL<3875> A_IWL<3874> A_IWL<3873> A_IWL<3872> A_IWL<3871> A_IWL<3870> A_IWL<3869> A_IWL<3868> A_IWL<3867> A_IWL<3866> A_IWL<3865> A_IWL<3864> A_IWL<3863> A_IWL<3862> A_IWL<3861> A_IWL<3860> A_IWL<3859> A_IWL<3858> A_IWL<3857> A_IWL<3856> A_IWL<3855> A_IWL<3854> A_IWL<3853> A_IWL<3852> A_IWL<3851> A_IWL<3850> A_IWL<3849> A_IWL<3848> A_IWL<3847> A_IWL<3846> A_IWL<3845> A_IWL<3844> A_IWL<3843> A_IWL<3842> A_IWL<3841> A_IWL<3840> VDD_CORE VSS / RM_IHPSG13_1024x32_c2_1P_COLUMN_pcell_0 +XCOL<14> A_BLC<29> A_BLC<28> A_BLC_TOP<29> A_BLC_TOP<28> A_BLT<29> A_BLT<28> A_BLT_TOP<29> A_BLT_TOP<28> A_IWL<3583> A_IWL<3582> A_IWL<3581> A_IWL<3580> A_IWL<3579> A_IWL<3578> A_IWL<3577> A_IWL<3576> A_IWL<3575> A_IWL<3574> A_IWL<3573> A_IWL<3572> A_IWL<3571> A_IWL<3570> A_IWL<3569> A_IWL<3568> A_IWL<3567> A_IWL<3566> A_IWL<3565> A_IWL<3564> A_IWL<3563> A_IWL<3562> A_IWL<3561> A_IWL<3560> A_IWL<3559> A_IWL<3558> A_IWL<3557> A_IWL<3556> A_IWL<3555> A_IWL<3554> A_IWL<3553> A_IWL<3552> A_IWL<3551> A_IWL<3550> A_IWL<3549> A_IWL<3548> A_IWL<3547> A_IWL<3546> A_IWL<3545> A_IWL<3544> A_IWL<3543> A_IWL<3542> A_IWL<3541> A_IWL<3540> A_IWL<3539> A_IWL<3538> A_IWL<3537> A_IWL<3536> A_IWL<3535> A_IWL<3534> A_IWL<3533> A_IWL<3532> A_IWL<3531> A_IWL<3530> A_IWL<3529> A_IWL<3528> A_IWL<3527> A_IWL<3526> A_IWL<3525> A_IWL<3524> A_IWL<3523> A_IWL<3522> A_IWL<3521> A_IWL<3520> A_IWL<3519> A_IWL<3518> A_IWL<3517> A_IWL<3516> A_IWL<3515> A_IWL<3514> A_IWL<3513> A_IWL<3512> A_IWL<3511> A_IWL<3510> A_IWL<3509> A_IWL<3508> A_IWL<3507> A_IWL<3506> A_IWL<3505> A_IWL<3504> A_IWL<3503> A_IWL<3502> A_IWL<3501> A_IWL<3500> A_IWL<3499> A_IWL<3498> A_IWL<3497> A_IWL<3496> A_IWL<3495> A_IWL<3494> A_IWL<3493> A_IWL<3492> A_IWL<3491> A_IWL<3490> A_IWL<3489> A_IWL<3488> A_IWL<3487> A_IWL<3486> A_IWL<3485> A_IWL<3484> A_IWL<3483> A_IWL<3482> A_IWL<3481> A_IWL<3480> A_IWL<3479> A_IWL<3478> A_IWL<3477> A_IWL<3476> A_IWL<3475> A_IWL<3474> A_IWL<3473> A_IWL<3472> A_IWL<3471> A_IWL<3470> A_IWL<3469> A_IWL<3468> A_IWL<3467> A_IWL<3466> A_IWL<3465> A_IWL<3464> A_IWL<3463> A_IWL<3462> A_IWL<3461> A_IWL<3460> A_IWL<3459> A_IWL<3458> A_IWL<3457> A_IWL<3456> A_IWL<3455> A_IWL<3454> A_IWL<3453> A_IWL<3452> A_IWL<3451> A_IWL<3450> A_IWL<3449> A_IWL<3448> A_IWL<3447> A_IWL<3446> A_IWL<3445> A_IWL<3444> A_IWL<3443> A_IWL<3442> A_IWL<3441> A_IWL<3440> A_IWL<3439> A_IWL<3438> A_IWL<3437> A_IWL<3436> A_IWL<3435> A_IWL<3434> A_IWL<3433> A_IWL<3432> A_IWL<3431> A_IWL<3430> A_IWL<3429> A_IWL<3428> A_IWL<3427> A_IWL<3426> A_IWL<3425> A_IWL<3424> A_IWL<3423> A_IWL<3422> A_IWL<3421> A_IWL<3420> A_IWL<3419> A_IWL<3418> A_IWL<3417> A_IWL<3416> A_IWL<3415> A_IWL<3414> A_IWL<3413> A_IWL<3412> A_IWL<3411> A_IWL<3410> A_IWL<3409> A_IWL<3408> A_IWL<3407> A_IWL<3406> A_IWL<3405> A_IWL<3404> A_IWL<3403> A_IWL<3402> A_IWL<3401> A_IWL<3400> A_IWL<3399> A_IWL<3398> A_IWL<3397> A_IWL<3396> A_IWL<3395> A_IWL<3394> A_IWL<3393> A_IWL<3392> A_IWL<3391> A_IWL<3390> A_IWL<3389> A_IWL<3388> A_IWL<3387> A_IWL<3386> A_IWL<3385> A_IWL<3384> A_IWL<3383> A_IWL<3382> A_IWL<3381> A_IWL<3380> A_IWL<3379> A_IWL<3378> A_IWL<3377> A_IWL<3376> A_IWL<3375> A_IWL<3374> A_IWL<3373> A_IWL<3372> A_IWL<3371> A_IWL<3370> A_IWL<3369> A_IWL<3368> A_IWL<3367> A_IWL<3366> A_IWL<3365> A_IWL<3364> A_IWL<3363> A_IWL<3362> A_IWL<3361> A_IWL<3360> A_IWL<3359> A_IWL<3358> A_IWL<3357> A_IWL<3356> A_IWL<3355> A_IWL<3354> A_IWL<3353> A_IWL<3352> A_IWL<3351> A_IWL<3350> A_IWL<3349> A_IWL<3348> A_IWL<3347> A_IWL<3346> A_IWL<3345> A_IWL<3344> A_IWL<3343> A_IWL<3342> A_IWL<3341> A_IWL<3340> A_IWL<3339> A_IWL<3338> A_IWL<3337> A_IWL<3336> A_IWL<3335> A_IWL<3334> A_IWL<3333> A_IWL<3332> A_IWL<3331> A_IWL<3330> A_IWL<3329> A_IWL<3328> A_IWL<3839> A_IWL<3838> A_IWL<3837> A_IWL<3836> A_IWL<3835> A_IWL<3834> A_IWL<3833> A_IWL<3832> A_IWL<3831> A_IWL<3830> A_IWL<3829> A_IWL<3828> A_IWL<3827> A_IWL<3826> A_IWL<3825> A_IWL<3824> A_IWL<3823> A_IWL<3822> A_IWL<3821> A_IWL<3820> A_IWL<3819> A_IWL<3818> A_IWL<3817> A_IWL<3816> A_IWL<3815> A_IWL<3814> A_IWL<3813> A_IWL<3812> A_IWL<3811> A_IWL<3810> A_IWL<3809> A_IWL<3808> A_IWL<3807> A_IWL<3806> A_IWL<3805> A_IWL<3804> A_IWL<3803> A_IWL<3802> A_IWL<3801> A_IWL<3800> A_IWL<3799> A_IWL<3798> A_IWL<3797> A_IWL<3796> A_IWL<3795> A_IWL<3794> A_IWL<3793> A_IWL<3792> A_IWL<3791> A_IWL<3790> A_IWL<3789> A_IWL<3788> A_IWL<3787> A_IWL<3786> A_IWL<3785> A_IWL<3784> A_IWL<3783> A_IWL<3782> A_IWL<3781> A_IWL<3780> A_IWL<3779> A_IWL<3778> A_IWL<3777> A_IWL<3776> A_IWL<3775> A_IWL<3774> A_IWL<3773> A_IWL<3772> A_IWL<3771> A_IWL<3770> A_IWL<3769> A_IWL<3768> A_IWL<3767> A_IWL<3766> A_IWL<3765> A_IWL<3764> A_IWL<3763> A_IWL<3762> A_IWL<3761> A_IWL<3760> A_IWL<3759> A_IWL<3758> A_IWL<3757> A_IWL<3756> A_IWL<3755> A_IWL<3754> A_IWL<3753> A_IWL<3752> A_IWL<3751> A_IWL<3750> A_IWL<3749> A_IWL<3748> A_IWL<3747> A_IWL<3746> A_IWL<3745> A_IWL<3744> A_IWL<3743> A_IWL<3742> A_IWL<3741> A_IWL<3740> A_IWL<3739> A_IWL<3738> A_IWL<3737> A_IWL<3736> A_IWL<3735> A_IWL<3734> A_IWL<3733> A_IWL<3732> A_IWL<3731> A_IWL<3730> A_IWL<3729> A_IWL<3728> A_IWL<3727> A_IWL<3726> A_IWL<3725> A_IWL<3724> A_IWL<3723> A_IWL<3722> A_IWL<3721> A_IWL<3720> A_IWL<3719> A_IWL<3718> A_IWL<3717> A_IWL<3716> A_IWL<3715> A_IWL<3714> A_IWL<3713> A_IWL<3712> A_IWL<3711> A_IWL<3710> A_IWL<3709> A_IWL<3708> A_IWL<3707> A_IWL<3706> A_IWL<3705> A_IWL<3704> A_IWL<3703> A_IWL<3702> A_IWL<3701> A_IWL<3700> A_IWL<3699> A_IWL<3698> A_IWL<3697> A_IWL<3696> A_IWL<3695> A_IWL<3694> A_IWL<3693> A_IWL<3692> A_IWL<3691> A_IWL<3690> A_IWL<3689> A_IWL<3688> A_IWL<3687> A_IWL<3686> A_IWL<3685> A_IWL<3684> A_IWL<3683> A_IWL<3682> A_IWL<3681> A_IWL<3680> A_IWL<3679> A_IWL<3678> A_IWL<3677> A_IWL<3676> A_IWL<3675> A_IWL<3674> A_IWL<3673> A_IWL<3672> A_IWL<3671> A_IWL<3670> A_IWL<3669> A_IWL<3668> A_IWL<3667> A_IWL<3666> A_IWL<3665> A_IWL<3664> A_IWL<3663> A_IWL<3662> A_IWL<3661> A_IWL<3660> A_IWL<3659> A_IWL<3658> A_IWL<3657> A_IWL<3656> A_IWL<3655> A_IWL<3654> A_IWL<3653> A_IWL<3652> A_IWL<3651> A_IWL<3650> A_IWL<3649> A_IWL<3648> A_IWL<3647> A_IWL<3646> A_IWL<3645> A_IWL<3644> A_IWL<3643> A_IWL<3642> A_IWL<3641> A_IWL<3640> A_IWL<3639> A_IWL<3638> A_IWL<3637> A_IWL<3636> A_IWL<3635> A_IWL<3634> A_IWL<3633> A_IWL<3632> A_IWL<3631> A_IWL<3630> A_IWL<3629> A_IWL<3628> A_IWL<3627> A_IWL<3626> A_IWL<3625> A_IWL<3624> A_IWL<3623> A_IWL<3622> A_IWL<3621> A_IWL<3620> A_IWL<3619> A_IWL<3618> A_IWL<3617> A_IWL<3616> A_IWL<3615> A_IWL<3614> A_IWL<3613> A_IWL<3612> A_IWL<3611> A_IWL<3610> A_IWL<3609> A_IWL<3608> A_IWL<3607> A_IWL<3606> A_IWL<3605> A_IWL<3604> A_IWL<3603> A_IWL<3602> A_IWL<3601> A_IWL<3600> A_IWL<3599> A_IWL<3598> A_IWL<3597> A_IWL<3596> A_IWL<3595> A_IWL<3594> A_IWL<3593> A_IWL<3592> A_IWL<3591> A_IWL<3590> A_IWL<3589> A_IWL<3588> A_IWL<3587> A_IWL<3586> A_IWL<3585> A_IWL<3584> VDD_CORE VSS / RM_IHPSG13_1024x32_c2_1P_COLUMN_pcell_0 +XCOL<13> A_BLC<27> A_BLC<26> A_BLC_TOP<27> A_BLC_TOP<26> A_BLT<27> A_BLT<26> A_BLT_TOP<27> A_BLT_TOP<26> A_IWL<3327> A_IWL<3326> A_IWL<3325> A_IWL<3324> A_IWL<3323> A_IWL<3322> A_IWL<3321> A_IWL<3320> A_IWL<3319> A_IWL<3318> A_IWL<3317> A_IWL<3316> A_IWL<3315> A_IWL<3314> A_IWL<3313> A_IWL<3312> A_IWL<3311> A_IWL<3310> A_IWL<3309> A_IWL<3308> A_IWL<3307> A_IWL<3306> A_IWL<3305> A_IWL<3304> A_IWL<3303> A_IWL<3302> A_IWL<3301> A_IWL<3300> A_IWL<3299> A_IWL<3298> A_IWL<3297> A_IWL<3296> A_IWL<3295> A_IWL<3294> A_IWL<3293> A_IWL<3292> A_IWL<3291> A_IWL<3290> A_IWL<3289> A_IWL<3288> A_IWL<3287> A_IWL<3286> A_IWL<3285> A_IWL<3284> A_IWL<3283> A_IWL<3282> A_IWL<3281> A_IWL<3280> A_IWL<3279> A_IWL<3278> A_IWL<3277> A_IWL<3276> A_IWL<3275> A_IWL<3274> A_IWL<3273> A_IWL<3272> A_IWL<3271> A_IWL<3270> A_IWL<3269> A_IWL<3268> A_IWL<3267> A_IWL<3266> A_IWL<3265> A_IWL<3264> A_IWL<3263> A_IWL<3262> A_IWL<3261> A_IWL<3260> A_IWL<3259> A_IWL<3258> A_IWL<3257> A_IWL<3256> A_IWL<3255> A_IWL<3254> A_IWL<3253> A_IWL<3252> A_IWL<3251> A_IWL<3250> A_IWL<3249> A_IWL<3248> A_IWL<3247> A_IWL<3246> A_IWL<3245> A_IWL<3244> A_IWL<3243> A_IWL<3242> A_IWL<3241> A_IWL<3240> A_IWL<3239> A_IWL<3238> A_IWL<3237> A_IWL<3236> A_IWL<3235> A_IWL<3234> A_IWL<3233> A_IWL<3232> A_IWL<3231> A_IWL<3230> A_IWL<3229> A_IWL<3228> A_IWL<3227> A_IWL<3226> A_IWL<3225> A_IWL<3224> A_IWL<3223> A_IWL<3222> A_IWL<3221> A_IWL<3220> A_IWL<3219> A_IWL<3218> A_IWL<3217> A_IWL<3216> A_IWL<3215> A_IWL<3214> A_IWL<3213> A_IWL<3212> A_IWL<3211> A_IWL<3210> A_IWL<3209> A_IWL<3208> A_IWL<3207> A_IWL<3206> A_IWL<3205> A_IWL<3204> A_IWL<3203> A_IWL<3202> A_IWL<3201> A_IWL<3200> A_IWL<3199> A_IWL<3198> A_IWL<3197> A_IWL<3196> A_IWL<3195> A_IWL<3194> A_IWL<3193> A_IWL<3192> A_IWL<3191> A_IWL<3190> A_IWL<3189> A_IWL<3188> A_IWL<3187> A_IWL<3186> A_IWL<3185> A_IWL<3184> A_IWL<3183> A_IWL<3182> A_IWL<3181> A_IWL<3180> A_IWL<3179> A_IWL<3178> A_IWL<3177> A_IWL<3176> A_IWL<3175> A_IWL<3174> A_IWL<3173> A_IWL<3172> A_IWL<3171> A_IWL<3170> A_IWL<3169> A_IWL<3168> A_IWL<3167> A_IWL<3166> A_IWL<3165> A_IWL<3164> A_IWL<3163> A_IWL<3162> A_IWL<3161> A_IWL<3160> A_IWL<3159> A_IWL<3158> A_IWL<3157> A_IWL<3156> A_IWL<3155> A_IWL<3154> A_IWL<3153> A_IWL<3152> A_IWL<3151> A_IWL<3150> A_IWL<3149> A_IWL<3148> A_IWL<3147> A_IWL<3146> A_IWL<3145> A_IWL<3144> A_IWL<3143> A_IWL<3142> A_IWL<3141> A_IWL<3140> A_IWL<3139> A_IWL<3138> A_IWL<3137> A_IWL<3136> A_IWL<3135> A_IWL<3134> A_IWL<3133> A_IWL<3132> A_IWL<3131> A_IWL<3130> A_IWL<3129> A_IWL<3128> A_IWL<3127> A_IWL<3126> A_IWL<3125> A_IWL<3124> A_IWL<3123> A_IWL<3122> A_IWL<3121> A_IWL<3120> A_IWL<3119> A_IWL<3118> A_IWL<3117> A_IWL<3116> A_IWL<3115> A_IWL<3114> A_IWL<3113> A_IWL<3112> A_IWL<3111> A_IWL<3110> A_IWL<3109> A_IWL<3108> A_IWL<3107> A_IWL<3106> A_IWL<3105> A_IWL<3104> A_IWL<3103> A_IWL<3102> A_IWL<3101> A_IWL<3100> A_IWL<3099> A_IWL<3098> A_IWL<3097> A_IWL<3096> A_IWL<3095> A_IWL<3094> A_IWL<3093> A_IWL<3092> A_IWL<3091> A_IWL<3090> A_IWL<3089> A_IWL<3088> A_IWL<3087> A_IWL<3086> A_IWL<3085> A_IWL<3084> A_IWL<3083> A_IWL<3082> A_IWL<3081> A_IWL<3080> A_IWL<3079> A_IWL<3078> A_IWL<3077> A_IWL<3076> A_IWL<3075> A_IWL<3074> A_IWL<3073> A_IWL<3072> A_IWL<3583> A_IWL<3582> A_IWL<3581> A_IWL<3580> A_IWL<3579> A_IWL<3578> A_IWL<3577> A_IWL<3576> A_IWL<3575> A_IWL<3574> A_IWL<3573> A_IWL<3572> A_IWL<3571> A_IWL<3570> A_IWL<3569> A_IWL<3568> A_IWL<3567> A_IWL<3566> A_IWL<3565> A_IWL<3564> A_IWL<3563> A_IWL<3562> A_IWL<3561> A_IWL<3560> A_IWL<3559> A_IWL<3558> A_IWL<3557> A_IWL<3556> A_IWL<3555> A_IWL<3554> A_IWL<3553> A_IWL<3552> A_IWL<3551> A_IWL<3550> A_IWL<3549> A_IWL<3548> A_IWL<3547> A_IWL<3546> A_IWL<3545> A_IWL<3544> A_IWL<3543> A_IWL<3542> A_IWL<3541> A_IWL<3540> A_IWL<3539> A_IWL<3538> A_IWL<3537> A_IWL<3536> A_IWL<3535> A_IWL<3534> A_IWL<3533> A_IWL<3532> A_IWL<3531> A_IWL<3530> A_IWL<3529> A_IWL<3528> A_IWL<3527> A_IWL<3526> A_IWL<3525> A_IWL<3524> A_IWL<3523> A_IWL<3522> A_IWL<3521> A_IWL<3520> A_IWL<3519> A_IWL<3518> A_IWL<3517> A_IWL<3516> A_IWL<3515> A_IWL<3514> A_IWL<3513> A_IWL<3512> A_IWL<3511> A_IWL<3510> A_IWL<3509> A_IWL<3508> A_IWL<3507> A_IWL<3506> A_IWL<3505> A_IWL<3504> A_IWL<3503> A_IWL<3502> A_IWL<3501> A_IWL<3500> A_IWL<3499> A_IWL<3498> A_IWL<3497> A_IWL<3496> A_IWL<3495> A_IWL<3494> A_IWL<3493> A_IWL<3492> A_IWL<3491> A_IWL<3490> A_IWL<3489> A_IWL<3488> A_IWL<3487> A_IWL<3486> A_IWL<3485> A_IWL<3484> A_IWL<3483> A_IWL<3482> A_IWL<3481> A_IWL<3480> A_IWL<3479> A_IWL<3478> A_IWL<3477> A_IWL<3476> A_IWL<3475> A_IWL<3474> A_IWL<3473> A_IWL<3472> A_IWL<3471> A_IWL<3470> A_IWL<3469> A_IWL<3468> A_IWL<3467> A_IWL<3466> A_IWL<3465> A_IWL<3464> A_IWL<3463> A_IWL<3462> A_IWL<3461> A_IWL<3460> A_IWL<3459> A_IWL<3458> A_IWL<3457> A_IWL<3456> A_IWL<3455> A_IWL<3454> A_IWL<3453> A_IWL<3452> A_IWL<3451> A_IWL<3450> A_IWL<3449> A_IWL<3448> A_IWL<3447> A_IWL<3446> A_IWL<3445> A_IWL<3444> A_IWL<3443> A_IWL<3442> A_IWL<3441> A_IWL<3440> A_IWL<3439> A_IWL<3438> A_IWL<3437> A_IWL<3436> A_IWL<3435> A_IWL<3434> A_IWL<3433> A_IWL<3432> A_IWL<3431> A_IWL<3430> A_IWL<3429> A_IWL<3428> A_IWL<3427> A_IWL<3426> A_IWL<3425> A_IWL<3424> A_IWL<3423> A_IWL<3422> A_IWL<3421> A_IWL<3420> A_IWL<3419> A_IWL<3418> A_IWL<3417> A_IWL<3416> A_IWL<3415> A_IWL<3414> A_IWL<3413> A_IWL<3412> A_IWL<3411> A_IWL<3410> A_IWL<3409> A_IWL<3408> A_IWL<3407> A_IWL<3406> A_IWL<3405> A_IWL<3404> A_IWL<3403> A_IWL<3402> A_IWL<3401> A_IWL<3400> A_IWL<3399> A_IWL<3398> A_IWL<3397> A_IWL<3396> A_IWL<3395> A_IWL<3394> A_IWL<3393> A_IWL<3392> A_IWL<3391> A_IWL<3390> A_IWL<3389> A_IWL<3388> A_IWL<3387> A_IWL<3386> A_IWL<3385> A_IWL<3384> A_IWL<3383> A_IWL<3382> A_IWL<3381> A_IWL<3380> A_IWL<3379> A_IWL<3378> A_IWL<3377> A_IWL<3376> A_IWL<3375> A_IWL<3374> A_IWL<3373> A_IWL<3372> A_IWL<3371> A_IWL<3370> A_IWL<3369> A_IWL<3368> A_IWL<3367> A_IWL<3366> A_IWL<3365> A_IWL<3364> A_IWL<3363> A_IWL<3362> A_IWL<3361> A_IWL<3360> A_IWL<3359> A_IWL<3358> A_IWL<3357> A_IWL<3356> A_IWL<3355> A_IWL<3354> A_IWL<3353> A_IWL<3352> A_IWL<3351> A_IWL<3350> A_IWL<3349> A_IWL<3348> A_IWL<3347> A_IWL<3346> A_IWL<3345> A_IWL<3344> A_IWL<3343> A_IWL<3342> A_IWL<3341> A_IWL<3340> A_IWL<3339> A_IWL<3338> A_IWL<3337> A_IWL<3336> A_IWL<3335> A_IWL<3334> A_IWL<3333> A_IWL<3332> A_IWL<3331> A_IWL<3330> A_IWL<3329> A_IWL<3328> VDD_CORE VSS / RM_IHPSG13_1024x32_c2_1P_COLUMN_pcell_0 +XCOL<12> A_BLC<25> A_BLC<24> A_BLC_TOP<25> A_BLC_TOP<24> A_BLT<25> A_BLT<24> A_BLT_TOP<25> A_BLT_TOP<24> A_IWL<3071> A_IWL<3070> A_IWL<3069> A_IWL<3068> A_IWL<3067> A_IWL<3066> A_IWL<3065> A_IWL<3064> A_IWL<3063> A_IWL<3062> A_IWL<3061> A_IWL<3060> A_IWL<3059> A_IWL<3058> A_IWL<3057> A_IWL<3056> A_IWL<3055> A_IWL<3054> A_IWL<3053> A_IWL<3052> A_IWL<3051> A_IWL<3050> A_IWL<3049> A_IWL<3048> A_IWL<3047> A_IWL<3046> A_IWL<3045> A_IWL<3044> A_IWL<3043> A_IWL<3042> A_IWL<3041> A_IWL<3040> A_IWL<3039> A_IWL<3038> A_IWL<3037> A_IWL<3036> A_IWL<3035> A_IWL<3034> A_IWL<3033> A_IWL<3032> A_IWL<3031> A_IWL<3030> A_IWL<3029> A_IWL<3028> A_IWL<3027> A_IWL<3026> A_IWL<3025> A_IWL<3024> A_IWL<3023> A_IWL<3022> A_IWL<3021> A_IWL<3020> A_IWL<3019> A_IWL<3018> A_IWL<3017> A_IWL<3016> A_IWL<3015> A_IWL<3014> A_IWL<3013> A_IWL<3012> A_IWL<3011> A_IWL<3010> A_IWL<3009> A_IWL<3008> A_IWL<3007> A_IWL<3006> A_IWL<3005> A_IWL<3004> A_IWL<3003> A_IWL<3002> A_IWL<3001> A_IWL<3000> A_IWL<2999> A_IWL<2998> A_IWL<2997> A_IWL<2996> A_IWL<2995> A_IWL<2994> A_IWL<2993> A_IWL<2992> A_IWL<2991> A_IWL<2990> A_IWL<2989> A_IWL<2988> A_IWL<2987> A_IWL<2986> A_IWL<2985> A_IWL<2984> A_IWL<2983> A_IWL<2982> A_IWL<2981> A_IWL<2980> A_IWL<2979> A_IWL<2978> A_IWL<2977> A_IWL<2976> A_IWL<2975> A_IWL<2974> A_IWL<2973> A_IWL<2972> A_IWL<2971> A_IWL<2970> A_IWL<2969> A_IWL<2968> A_IWL<2967> A_IWL<2966> A_IWL<2965> A_IWL<2964> A_IWL<2963> A_IWL<2962> A_IWL<2961> A_IWL<2960> A_IWL<2959> A_IWL<2958> A_IWL<2957> A_IWL<2956> A_IWL<2955> A_IWL<2954> A_IWL<2953> A_IWL<2952> A_IWL<2951> A_IWL<2950> A_IWL<2949> A_IWL<2948> A_IWL<2947> A_IWL<2946> A_IWL<2945> A_IWL<2944> A_IWL<2943> A_IWL<2942> A_IWL<2941> A_IWL<2940> A_IWL<2939> A_IWL<2938> A_IWL<2937> A_IWL<2936> A_IWL<2935> A_IWL<2934> A_IWL<2933> A_IWL<2932> A_IWL<2931> A_IWL<2930> A_IWL<2929> A_IWL<2928> A_IWL<2927> A_IWL<2926> A_IWL<2925> A_IWL<2924> A_IWL<2923> A_IWL<2922> A_IWL<2921> A_IWL<2920> A_IWL<2919> A_IWL<2918> A_IWL<2917> A_IWL<2916> A_IWL<2915> A_IWL<2914> A_IWL<2913> A_IWL<2912> A_IWL<2911> A_IWL<2910> A_IWL<2909> A_IWL<2908> A_IWL<2907> A_IWL<2906> A_IWL<2905> A_IWL<2904> A_IWL<2903> A_IWL<2902> A_IWL<2901> A_IWL<2900> A_IWL<2899> A_IWL<2898> A_IWL<2897> A_IWL<2896> A_IWL<2895> A_IWL<2894> A_IWL<2893> A_IWL<2892> A_IWL<2891> A_IWL<2890> A_IWL<2889> A_IWL<2888> A_IWL<2887> A_IWL<2886> A_IWL<2885> A_IWL<2884> A_IWL<2883> A_IWL<2882> A_IWL<2881> A_IWL<2880> A_IWL<2879> A_IWL<2878> A_IWL<2877> A_IWL<2876> A_IWL<2875> A_IWL<2874> A_IWL<2873> A_IWL<2872> A_IWL<2871> A_IWL<2870> A_IWL<2869> A_IWL<2868> A_IWL<2867> A_IWL<2866> A_IWL<2865> A_IWL<2864> A_IWL<2863> A_IWL<2862> A_IWL<2861> A_IWL<2860> A_IWL<2859> A_IWL<2858> A_IWL<2857> A_IWL<2856> A_IWL<2855> A_IWL<2854> A_IWL<2853> A_IWL<2852> A_IWL<2851> A_IWL<2850> A_IWL<2849> A_IWL<2848> A_IWL<2847> A_IWL<2846> A_IWL<2845> A_IWL<2844> A_IWL<2843> A_IWL<2842> A_IWL<2841> A_IWL<2840> A_IWL<2839> A_IWL<2838> A_IWL<2837> A_IWL<2836> A_IWL<2835> A_IWL<2834> A_IWL<2833> A_IWL<2832> A_IWL<2831> A_IWL<2830> A_IWL<2829> A_IWL<2828> A_IWL<2827> A_IWL<2826> A_IWL<2825> A_IWL<2824> A_IWL<2823> A_IWL<2822> A_IWL<2821> A_IWL<2820> A_IWL<2819> A_IWL<2818> A_IWL<2817> A_IWL<2816> A_IWL<3327> A_IWL<3326> A_IWL<3325> A_IWL<3324> A_IWL<3323> A_IWL<3322> A_IWL<3321> A_IWL<3320> A_IWL<3319> A_IWL<3318> A_IWL<3317> A_IWL<3316> A_IWL<3315> A_IWL<3314> A_IWL<3313> A_IWL<3312> A_IWL<3311> A_IWL<3310> A_IWL<3309> A_IWL<3308> A_IWL<3307> A_IWL<3306> A_IWL<3305> A_IWL<3304> A_IWL<3303> A_IWL<3302> A_IWL<3301> A_IWL<3300> A_IWL<3299> A_IWL<3298> A_IWL<3297> A_IWL<3296> A_IWL<3295> A_IWL<3294> A_IWL<3293> A_IWL<3292> A_IWL<3291> A_IWL<3290> A_IWL<3289> A_IWL<3288> A_IWL<3287> A_IWL<3286> A_IWL<3285> A_IWL<3284> A_IWL<3283> A_IWL<3282> A_IWL<3281> A_IWL<3280> A_IWL<3279> A_IWL<3278> A_IWL<3277> A_IWL<3276> A_IWL<3275> A_IWL<3274> A_IWL<3273> A_IWL<3272> A_IWL<3271> A_IWL<3270> A_IWL<3269> A_IWL<3268> A_IWL<3267> A_IWL<3266> A_IWL<3265> A_IWL<3264> A_IWL<3263> A_IWL<3262> A_IWL<3261> A_IWL<3260> A_IWL<3259> A_IWL<3258> A_IWL<3257> A_IWL<3256> A_IWL<3255> A_IWL<3254> A_IWL<3253> A_IWL<3252> A_IWL<3251> A_IWL<3250> A_IWL<3249> A_IWL<3248> A_IWL<3247> A_IWL<3246> A_IWL<3245> A_IWL<3244> A_IWL<3243> A_IWL<3242> A_IWL<3241> A_IWL<3240> A_IWL<3239> A_IWL<3238> A_IWL<3237> A_IWL<3236> A_IWL<3235> A_IWL<3234> A_IWL<3233> A_IWL<3232> A_IWL<3231> A_IWL<3230> A_IWL<3229> A_IWL<3228> A_IWL<3227> A_IWL<3226> A_IWL<3225> A_IWL<3224> A_IWL<3223> A_IWL<3222> A_IWL<3221> A_IWL<3220> A_IWL<3219> A_IWL<3218> A_IWL<3217> A_IWL<3216> A_IWL<3215> A_IWL<3214> A_IWL<3213> A_IWL<3212> A_IWL<3211> A_IWL<3210> A_IWL<3209> A_IWL<3208> A_IWL<3207> A_IWL<3206> A_IWL<3205> A_IWL<3204> A_IWL<3203> A_IWL<3202> A_IWL<3201> A_IWL<3200> A_IWL<3199> A_IWL<3198> A_IWL<3197> A_IWL<3196> A_IWL<3195> A_IWL<3194> A_IWL<3193> A_IWL<3192> A_IWL<3191> A_IWL<3190> A_IWL<3189> A_IWL<3188> A_IWL<3187> A_IWL<3186> A_IWL<3185> A_IWL<3184> A_IWL<3183> A_IWL<3182> A_IWL<3181> A_IWL<3180> A_IWL<3179> A_IWL<3178> A_IWL<3177> A_IWL<3176> A_IWL<3175> A_IWL<3174> A_IWL<3173> A_IWL<3172> A_IWL<3171> A_IWL<3170> A_IWL<3169> A_IWL<3168> A_IWL<3167> A_IWL<3166> A_IWL<3165> A_IWL<3164> A_IWL<3163> A_IWL<3162> A_IWL<3161> A_IWL<3160> A_IWL<3159> A_IWL<3158> A_IWL<3157> A_IWL<3156> A_IWL<3155> A_IWL<3154> A_IWL<3153> A_IWL<3152> A_IWL<3151> A_IWL<3150> A_IWL<3149> A_IWL<3148> A_IWL<3147> A_IWL<3146> A_IWL<3145> A_IWL<3144> A_IWL<3143> A_IWL<3142> A_IWL<3141> A_IWL<3140> A_IWL<3139> A_IWL<3138> A_IWL<3137> A_IWL<3136> A_IWL<3135> A_IWL<3134> A_IWL<3133> A_IWL<3132> A_IWL<3131> A_IWL<3130> A_IWL<3129> A_IWL<3128> A_IWL<3127> A_IWL<3126> A_IWL<3125> A_IWL<3124> A_IWL<3123> A_IWL<3122> A_IWL<3121> A_IWL<3120> A_IWL<3119> A_IWL<3118> A_IWL<3117> A_IWL<3116> A_IWL<3115> A_IWL<3114> A_IWL<3113> A_IWL<3112> A_IWL<3111> A_IWL<3110> A_IWL<3109> A_IWL<3108> A_IWL<3107> A_IWL<3106> A_IWL<3105> A_IWL<3104> A_IWL<3103> A_IWL<3102> A_IWL<3101> A_IWL<3100> A_IWL<3099> A_IWL<3098> A_IWL<3097> A_IWL<3096> A_IWL<3095> A_IWL<3094> A_IWL<3093> A_IWL<3092> A_IWL<3091> A_IWL<3090> A_IWL<3089> A_IWL<3088> A_IWL<3087> A_IWL<3086> A_IWL<3085> A_IWL<3084> A_IWL<3083> A_IWL<3082> A_IWL<3081> A_IWL<3080> A_IWL<3079> A_IWL<3078> A_IWL<3077> A_IWL<3076> A_IWL<3075> A_IWL<3074> A_IWL<3073> A_IWL<3072> VDD_CORE VSS / RM_IHPSG13_1024x32_c2_1P_COLUMN_pcell_0 +XCOL<11> A_BLC<23> A_BLC<22> A_BLC_TOP<23> A_BLC_TOP<22> A_BLT<23> A_BLT<22> A_BLT_TOP<23> A_BLT_TOP<22> A_IWL<2815> A_IWL<2814> A_IWL<2813> A_IWL<2812> A_IWL<2811> A_IWL<2810> A_IWL<2809> A_IWL<2808> A_IWL<2807> A_IWL<2806> A_IWL<2805> A_IWL<2804> A_IWL<2803> A_IWL<2802> A_IWL<2801> A_IWL<2800> A_IWL<2799> A_IWL<2798> A_IWL<2797> A_IWL<2796> A_IWL<2795> A_IWL<2794> A_IWL<2793> A_IWL<2792> A_IWL<2791> A_IWL<2790> A_IWL<2789> A_IWL<2788> A_IWL<2787> A_IWL<2786> A_IWL<2785> A_IWL<2784> A_IWL<2783> A_IWL<2782> A_IWL<2781> A_IWL<2780> A_IWL<2779> A_IWL<2778> A_IWL<2777> A_IWL<2776> A_IWL<2775> A_IWL<2774> A_IWL<2773> A_IWL<2772> A_IWL<2771> A_IWL<2770> A_IWL<2769> A_IWL<2768> A_IWL<2767> A_IWL<2766> A_IWL<2765> A_IWL<2764> A_IWL<2763> A_IWL<2762> A_IWL<2761> A_IWL<2760> A_IWL<2759> A_IWL<2758> A_IWL<2757> A_IWL<2756> A_IWL<2755> A_IWL<2754> A_IWL<2753> A_IWL<2752> A_IWL<2751> A_IWL<2750> A_IWL<2749> A_IWL<2748> A_IWL<2747> A_IWL<2746> A_IWL<2745> A_IWL<2744> A_IWL<2743> A_IWL<2742> A_IWL<2741> A_IWL<2740> A_IWL<2739> A_IWL<2738> A_IWL<2737> A_IWL<2736> A_IWL<2735> A_IWL<2734> A_IWL<2733> A_IWL<2732> A_IWL<2731> A_IWL<2730> A_IWL<2729> A_IWL<2728> A_IWL<2727> A_IWL<2726> A_IWL<2725> A_IWL<2724> A_IWL<2723> A_IWL<2722> A_IWL<2721> A_IWL<2720> A_IWL<2719> A_IWL<2718> A_IWL<2717> A_IWL<2716> A_IWL<2715> A_IWL<2714> A_IWL<2713> A_IWL<2712> A_IWL<2711> A_IWL<2710> A_IWL<2709> A_IWL<2708> A_IWL<2707> A_IWL<2706> A_IWL<2705> A_IWL<2704> A_IWL<2703> A_IWL<2702> A_IWL<2701> A_IWL<2700> A_IWL<2699> A_IWL<2698> A_IWL<2697> A_IWL<2696> A_IWL<2695> A_IWL<2694> A_IWL<2693> A_IWL<2692> A_IWL<2691> A_IWL<2690> A_IWL<2689> A_IWL<2688> A_IWL<2687> A_IWL<2686> A_IWL<2685> A_IWL<2684> A_IWL<2683> A_IWL<2682> A_IWL<2681> A_IWL<2680> A_IWL<2679> A_IWL<2678> A_IWL<2677> A_IWL<2676> A_IWL<2675> A_IWL<2674> A_IWL<2673> A_IWL<2672> A_IWL<2671> A_IWL<2670> A_IWL<2669> A_IWL<2668> A_IWL<2667> A_IWL<2666> A_IWL<2665> A_IWL<2664> A_IWL<2663> A_IWL<2662> A_IWL<2661> A_IWL<2660> A_IWL<2659> A_IWL<2658> A_IWL<2657> A_IWL<2656> A_IWL<2655> A_IWL<2654> A_IWL<2653> A_IWL<2652> A_IWL<2651> A_IWL<2650> A_IWL<2649> A_IWL<2648> A_IWL<2647> A_IWL<2646> A_IWL<2645> A_IWL<2644> A_IWL<2643> A_IWL<2642> A_IWL<2641> A_IWL<2640> A_IWL<2639> A_IWL<2638> A_IWL<2637> A_IWL<2636> A_IWL<2635> A_IWL<2634> A_IWL<2633> A_IWL<2632> A_IWL<2631> A_IWL<2630> A_IWL<2629> A_IWL<2628> A_IWL<2627> A_IWL<2626> A_IWL<2625> A_IWL<2624> A_IWL<2623> A_IWL<2622> A_IWL<2621> A_IWL<2620> A_IWL<2619> A_IWL<2618> A_IWL<2617> A_IWL<2616> A_IWL<2615> A_IWL<2614> A_IWL<2613> A_IWL<2612> A_IWL<2611> A_IWL<2610> A_IWL<2609> A_IWL<2608> A_IWL<2607> A_IWL<2606> A_IWL<2605> A_IWL<2604> A_IWL<2603> A_IWL<2602> A_IWL<2601> A_IWL<2600> A_IWL<2599> A_IWL<2598> A_IWL<2597> A_IWL<2596> A_IWL<2595> A_IWL<2594> A_IWL<2593> A_IWL<2592> A_IWL<2591> A_IWL<2590> A_IWL<2589> A_IWL<2588> A_IWL<2587> A_IWL<2586> A_IWL<2585> A_IWL<2584> A_IWL<2583> A_IWL<2582> A_IWL<2581> A_IWL<2580> A_IWL<2579> A_IWL<2578> A_IWL<2577> A_IWL<2576> A_IWL<2575> A_IWL<2574> A_IWL<2573> A_IWL<2572> A_IWL<2571> A_IWL<2570> A_IWL<2569> A_IWL<2568> A_IWL<2567> A_IWL<2566> A_IWL<2565> A_IWL<2564> A_IWL<2563> A_IWL<2562> A_IWL<2561> A_IWL<2560> A_IWL<3071> A_IWL<3070> A_IWL<3069> A_IWL<3068> A_IWL<3067> A_IWL<3066> A_IWL<3065> A_IWL<3064> A_IWL<3063> A_IWL<3062> A_IWL<3061> A_IWL<3060> A_IWL<3059> A_IWL<3058> A_IWL<3057> A_IWL<3056> A_IWL<3055> A_IWL<3054> A_IWL<3053> A_IWL<3052> A_IWL<3051> A_IWL<3050> A_IWL<3049> A_IWL<3048> A_IWL<3047> A_IWL<3046> A_IWL<3045> A_IWL<3044> A_IWL<3043> A_IWL<3042> A_IWL<3041> A_IWL<3040> A_IWL<3039> A_IWL<3038> A_IWL<3037> A_IWL<3036> A_IWL<3035> A_IWL<3034> A_IWL<3033> A_IWL<3032> A_IWL<3031> A_IWL<3030> A_IWL<3029> A_IWL<3028> A_IWL<3027> A_IWL<3026> A_IWL<3025> A_IWL<3024> A_IWL<3023> A_IWL<3022> A_IWL<3021> A_IWL<3020> A_IWL<3019> A_IWL<3018> A_IWL<3017> A_IWL<3016> A_IWL<3015> A_IWL<3014> A_IWL<3013> A_IWL<3012> A_IWL<3011> A_IWL<3010> A_IWL<3009> A_IWL<3008> A_IWL<3007> A_IWL<3006> A_IWL<3005> A_IWL<3004> A_IWL<3003> A_IWL<3002> A_IWL<3001> A_IWL<3000> A_IWL<2999> A_IWL<2998> A_IWL<2997> A_IWL<2996> A_IWL<2995> A_IWL<2994> A_IWL<2993> A_IWL<2992> A_IWL<2991> A_IWL<2990> A_IWL<2989> A_IWL<2988> A_IWL<2987> A_IWL<2986> A_IWL<2985> A_IWL<2984> A_IWL<2983> A_IWL<2982> A_IWL<2981> A_IWL<2980> A_IWL<2979> A_IWL<2978> A_IWL<2977> A_IWL<2976> A_IWL<2975> A_IWL<2974> A_IWL<2973> A_IWL<2972> A_IWL<2971> A_IWL<2970> A_IWL<2969> A_IWL<2968> A_IWL<2967> A_IWL<2966> A_IWL<2965> A_IWL<2964> A_IWL<2963> A_IWL<2962> A_IWL<2961> A_IWL<2960> A_IWL<2959> A_IWL<2958> A_IWL<2957> A_IWL<2956> A_IWL<2955> A_IWL<2954> A_IWL<2953> A_IWL<2952> A_IWL<2951> A_IWL<2950> A_IWL<2949> A_IWL<2948> A_IWL<2947> A_IWL<2946> A_IWL<2945> A_IWL<2944> A_IWL<2943> A_IWL<2942> A_IWL<2941> A_IWL<2940> A_IWL<2939> A_IWL<2938> A_IWL<2937> A_IWL<2936> A_IWL<2935> A_IWL<2934> A_IWL<2933> A_IWL<2932> A_IWL<2931> A_IWL<2930> A_IWL<2929> A_IWL<2928> A_IWL<2927> A_IWL<2926> A_IWL<2925> A_IWL<2924> A_IWL<2923> A_IWL<2922> A_IWL<2921> A_IWL<2920> A_IWL<2919> A_IWL<2918> A_IWL<2917> A_IWL<2916> A_IWL<2915> A_IWL<2914> A_IWL<2913> A_IWL<2912> A_IWL<2911> A_IWL<2910> A_IWL<2909> A_IWL<2908> A_IWL<2907> A_IWL<2906> A_IWL<2905> A_IWL<2904> A_IWL<2903> A_IWL<2902> A_IWL<2901> A_IWL<2900> A_IWL<2899> A_IWL<2898> A_IWL<2897> A_IWL<2896> A_IWL<2895> A_IWL<2894> A_IWL<2893> A_IWL<2892> A_IWL<2891> A_IWL<2890> A_IWL<2889> A_IWL<2888> A_IWL<2887> A_IWL<2886> A_IWL<2885> A_IWL<2884> A_IWL<2883> A_IWL<2882> A_IWL<2881> A_IWL<2880> A_IWL<2879> A_IWL<2878> A_IWL<2877> A_IWL<2876> A_IWL<2875> A_IWL<2874> A_IWL<2873> A_IWL<2872> A_IWL<2871> A_IWL<2870> A_IWL<2869> A_IWL<2868> A_IWL<2867> A_IWL<2866> A_IWL<2865> A_IWL<2864> A_IWL<2863> A_IWL<2862> A_IWL<2861> A_IWL<2860> A_IWL<2859> A_IWL<2858> A_IWL<2857> A_IWL<2856> A_IWL<2855> A_IWL<2854> A_IWL<2853> A_IWL<2852> A_IWL<2851> A_IWL<2850> A_IWL<2849> A_IWL<2848> A_IWL<2847> A_IWL<2846> A_IWL<2845> A_IWL<2844> A_IWL<2843> A_IWL<2842> A_IWL<2841> A_IWL<2840> A_IWL<2839> A_IWL<2838> A_IWL<2837> A_IWL<2836> A_IWL<2835> A_IWL<2834> A_IWL<2833> A_IWL<2832> A_IWL<2831> A_IWL<2830> A_IWL<2829> A_IWL<2828> A_IWL<2827> A_IWL<2826> A_IWL<2825> A_IWL<2824> A_IWL<2823> A_IWL<2822> A_IWL<2821> A_IWL<2820> A_IWL<2819> A_IWL<2818> A_IWL<2817> A_IWL<2816> VDD_CORE VSS / RM_IHPSG13_1024x32_c2_1P_COLUMN_pcell_0 +XCOL<10> A_BLC<21> A_BLC<20> A_BLC_TOP<21> A_BLC_TOP<20> A_BLT<21> A_BLT<20> A_BLT_TOP<21> A_BLT_TOP<20> A_IWL<2559> A_IWL<2558> A_IWL<2557> A_IWL<2556> A_IWL<2555> A_IWL<2554> A_IWL<2553> A_IWL<2552> A_IWL<2551> A_IWL<2550> A_IWL<2549> A_IWL<2548> A_IWL<2547> A_IWL<2546> A_IWL<2545> A_IWL<2544> A_IWL<2543> A_IWL<2542> A_IWL<2541> A_IWL<2540> A_IWL<2539> A_IWL<2538> A_IWL<2537> A_IWL<2536> A_IWL<2535> A_IWL<2534> A_IWL<2533> A_IWL<2532> A_IWL<2531> A_IWL<2530> A_IWL<2529> A_IWL<2528> A_IWL<2527> A_IWL<2526> A_IWL<2525> A_IWL<2524> A_IWL<2523> A_IWL<2522> A_IWL<2521> A_IWL<2520> A_IWL<2519> A_IWL<2518> A_IWL<2517> A_IWL<2516> A_IWL<2515> A_IWL<2514> A_IWL<2513> A_IWL<2512> A_IWL<2511> A_IWL<2510> A_IWL<2509> A_IWL<2508> A_IWL<2507> A_IWL<2506> A_IWL<2505> A_IWL<2504> A_IWL<2503> A_IWL<2502> A_IWL<2501> A_IWL<2500> A_IWL<2499> A_IWL<2498> A_IWL<2497> A_IWL<2496> A_IWL<2495> A_IWL<2494> A_IWL<2493> A_IWL<2492> A_IWL<2491> A_IWL<2490> A_IWL<2489> A_IWL<2488> A_IWL<2487> A_IWL<2486> A_IWL<2485> A_IWL<2484> A_IWL<2483> A_IWL<2482> A_IWL<2481> A_IWL<2480> A_IWL<2479> A_IWL<2478> A_IWL<2477> A_IWL<2476> A_IWL<2475> A_IWL<2474> A_IWL<2473> A_IWL<2472> A_IWL<2471> A_IWL<2470> A_IWL<2469> A_IWL<2468> A_IWL<2467> A_IWL<2466> A_IWL<2465> A_IWL<2464> A_IWL<2463> A_IWL<2462> A_IWL<2461> A_IWL<2460> A_IWL<2459> A_IWL<2458> A_IWL<2457> A_IWL<2456> A_IWL<2455> A_IWL<2454> A_IWL<2453> A_IWL<2452> A_IWL<2451> A_IWL<2450> A_IWL<2449> A_IWL<2448> A_IWL<2447> A_IWL<2446> A_IWL<2445> A_IWL<2444> A_IWL<2443> A_IWL<2442> A_IWL<2441> A_IWL<2440> A_IWL<2439> A_IWL<2438> A_IWL<2437> A_IWL<2436> A_IWL<2435> A_IWL<2434> A_IWL<2433> A_IWL<2432> A_IWL<2431> A_IWL<2430> A_IWL<2429> A_IWL<2428> A_IWL<2427> A_IWL<2426> A_IWL<2425> A_IWL<2424> A_IWL<2423> A_IWL<2422> A_IWL<2421> A_IWL<2420> A_IWL<2419> A_IWL<2418> A_IWL<2417> A_IWL<2416> A_IWL<2415> A_IWL<2414> A_IWL<2413> A_IWL<2412> A_IWL<2411> A_IWL<2410> A_IWL<2409> A_IWL<2408> A_IWL<2407> A_IWL<2406> A_IWL<2405> A_IWL<2404> A_IWL<2403> A_IWL<2402> A_IWL<2401> A_IWL<2400> A_IWL<2399> A_IWL<2398> A_IWL<2397> A_IWL<2396> A_IWL<2395> A_IWL<2394> A_IWL<2393> A_IWL<2392> A_IWL<2391> A_IWL<2390> A_IWL<2389> A_IWL<2388> A_IWL<2387> A_IWL<2386> A_IWL<2385> A_IWL<2384> A_IWL<2383> A_IWL<2382> A_IWL<2381> A_IWL<2380> A_IWL<2379> A_IWL<2378> A_IWL<2377> A_IWL<2376> A_IWL<2375> A_IWL<2374> A_IWL<2373> A_IWL<2372> A_IWL<2371> A_IWL<2370> A_IWL<2369> A_IWL<2368> A_IWL<2367> A_IWL<2366> A_IWL<2365> A_IWL<2364> A_IWL<2363> A_IWL<2362> A_IWL<2361> A_IWL<2360> A_IWL<2359> A_IWL<2358> A_IWL<2357> A_IWL<2356> A_IWL<2355> A_IWL<2354> A_IWL<2353> A_IWL<2352> A_IWL<2351> A_IWL<2350> A_IWL<2349> A_IWL<2348> A_IWL<2347> A_IWL<2346> A_IWL<2345> A_IWL<2344> A_IWL<2343> A_IWL<2342> A_IWL<2341> A_IWL<2340> A_IWL<2339> A_IWL<2338> A_IWL<2337> A_IWL<2336> A_IWL<2335> A_IWL<2334> A_IWL<2333> A_IWL<2332> A_IWL<2331> A_IWL<2330> A_IWL<2329> A_IWL<2328> A_IWL<2327> A_IWL<2326> A_IWL<2325> A_IWL<2324> A_IWL<2323> A_IWL<2322> A_IWL<2321> A_IWL<2320> A_IWL<2319> A_IWL<2318> A_IWL<2317> A_IWL<2316> A_IWL<2315> A_IWL<2314> A_IWL<2313> A_IWL<2312> A_IWL<2311> A_IWL<2310> A_IWL<2309> A_IWL<2308> A_IWL<2307> A_IWL<2306> A_IWL<2305> A_IWL<2304> A_IWL<2815> A_IWL<2814> A_IWL<2813> A_IWL<2812> A_IWL<2811> A_IWL<2810> A_IWL<2809> A_IWL<2808> A_IWL<2807> A_IWL<2806> A_IWL<2805> A_IWL<2804> A_IWL<2803> A_IWL<2802> A_IWL<2801> A_IWL<2800> A_IWL<2799> A_IWL<2798> A_IWL<2797> A_IWL<2796> A_IWL<2795> A_IWL<2794> A_IWL<2793> A_IWL<2792> A_IWL<2791> A_IWL<2790> A_IWL<2789> A_IWL<2788> A_IWL<2787> A_IWL<2786> A_IWL<2785> A_IWL<2784> A_IWL<2783> A_IWL<2782> A_IWL<2781> A_IWL<2780> A_IWL<2779> A_IWL<2778> A_IWL<2777> A_IWL<2776> A_IWL<2775> A_IWL<2774> A_IWL<2773> A_IWL<2772> A_IWL<2771> A_IWL<2770> A_IWL<2769> A_IWL<2768> A_IWL<2767> A_IWL<2766> A_IWL<2765> A_IWL<2764> A_IWL<2763> A_IWL<2762> A_IWL<2761> A_IWL<2760> A_IWL<2759> A_IWL<2758> A_IWL<2757> A_IWL<2756> A_IWL<2755> A_IWL<2754> A_IWL<2753> A_IWL<2752> A_IWL<2751> A_IWL<2750> A_IWL<2749> A_IWL<2748> A_IWL<2747> A_IWL<2746> A_IWL<2745> A_IWL<2744> A_IWL<2743> A_IWL<2742> A_IWL<2741> A_IWL<2740> A_IWL<2739> A_IWL<2738> A_IWL<2737> A_IWL<2736> A_IWL<2735> A_IWL<2734> A_IWL<2733> A_IWL<2732> A_IWL<2731> A_IWL<2730> A_IWL<2729> A_IWL<2728> A_IWL<2727> A_IWL<2726> A_IWL<2725> A_IWL<2724> A_IWL<2723> A_IWL<2722> A_IWL<2721> A_IWL<2720> A_IWL<2719> A_IWL<2718> A_IWL<2717> A_IWL<2716> A_IWL<2715> A_IWL<2714> A_IWL<2713> A_IWL<2712> A_IWL<2711> A_IWL<2710> A_IWL<2709> A_IWL<2708> A_IWL<2707> A_IWL<2706> A_IWL<2705> A_IWL<2704> A_IWL<2703> A_IWL<2702> A_IWL<2701> A_IWL<2700> A_IWL<2699> A_IWL<2698> A_IWL<2697> A_IWL<2696> A_IWL<2695> A_IWL<2694> A_IWL<2693> A_IWL<2692> A_IWL<2691> A_IWL<2690> A_IWL<2689> A_IWL<2688> A_IWL<2687> A_IWL<2686> A_IWL<2685> A_IWL<2684> A_IWL<2683> A_IWL<2682> A_IWL<2681> A_IWL<2680> A_IWL<2679> A_IWL<2678> A_IWL<2677> A_IWL<2676> A_IWL<2675> A_IWL<2674> A_IWL<2673> A_IWL<2672> A_IWL<2671> A_IWL<2670> A_IWL<2669> A_IWL<2668> A_IWL<2667> A_IWL<2666> A_IWL<2665> A_IWL<2664> A_IWL<2663> A_IWL<2662> A_IWL<2661> A_IWL<2660> A_IWL<2659> A_IWL<2658> A_IWL<2657> A_IWL<2656> A_IWL<2655> A_IWL<2654> A_IWL<2653> A_IWL<2652> A_IWL<2651> A_IWL<2650> A_IWL<2649> A_IWL<2648> A_IWL<2647> A_IWL<2646> A_IWL<2645> A_IWL<2644> A_IWL<2643> A_IWL<2642> A_IWL<2641> A_IWL<2640> A_IWL<2639> A_IWL<2638> A_IWL<2637> A_IWL<2636> A_IWL<2635> A_IWL<2634> A_IWL<2633> A_IWL<2632> A_IWL<2631> A_IWL<2630> A_IWL<2629> A_IWL<2628> A_IWL<2627> A_IWL<2626> A_IWL<2625> A_IWL<2624> A_IWL<2623> A_IWL<2622> A_IWL<2621> A_IWL<2620> A_IWL<2619> A_IWL<2618> A_IWL<2617> A_IWL<2616> A_IWL<2615> A_IWL<2614> A_IWL<2613> A_IWL<2612> A_IWL<2611> A_IWL<2610> A_IWL<2609> A_IWL<2608> A_IWL<2607> A_IWL<2606> A_IWL<2605> A_IWL<2604> A_IWL<2603> A_IWL<2602> A_IWL<2601> A_IWL<2600> A_IWL<2599> A_IWL<2598> A_IWL<2597> A_IWL<2596> A_IWL<2595> A_IWL<2594> A_IWL<2593> A_IWL<2592> A_IWL<2591> A_IWL<2590> A_IWL<2589> A_IWL<2588> A_IWL<2587> A_IWL<2586> A_IWL<2585> A_IWL<2584> A_IWL<2583> A_IWL<2582> A_IWL<2581> A_IWL<2580> A_IWL<2579> A_IWL<2578> A_IWL<2577> A_IWL<2576> A_IWL<2575> A_IWL<2574> A_IWL<2573> A_IWL<2572> A_IWL<2571> A_IWL<2570> A_IWL<2569> A_IWL<2568> A_IWL<2567> A_IWL<2566> A_IWL<2565> A_IWL<2564> A_IWL<2563> A_IWL<2562> A_IWL<2561> A_IWL<2560> VDD_CORE VSS / RM_IHPSG13_1024x32_c2_1P_COLUMN_pcell_0 +XCOL<9> A_BLC<19> A_BLC<18> A_BLC_TOP<19> A_BLC_TOP<18> A_BLT<19> A_BLT<18> A_BLT_TOP<19> A_BLT_TOP<18> A_IWL<2303> A_IWL<2302> A_IWL<2301> A_IWL<2300> A_IWL<2299> A_IWL<2298> A_IWL<2297> A_IWL<2296> A_IWL<2295> A_IWL<2294> A_IWL<2293> A_IWL<2292> A_IWL<2291> A_IWL<2290> A_IWL<2289> A_IWL<2288> A_IWL<2287> A_IWL<2286> A_IWL<2285> A_IWL<2284> A_IWL<2283> A_IWL<2282> A_IWL<2281> A_IWL<2280> A_IWL<2279> A_IWL<2278> A_IWL<2277> A_IWL<2276> A_IWL<2275> A_IWL<2274> A_IWL<2273> A_IWL<2272> A_IWL<2271> A_IWL<2270> A_IWL<2269> A_IWL<2268> A_IWL<2267> A_IWL<2266> A_IWL<2265> A_IWL<2264> A_IWL<2263> A_IWL<2262> A_IWL<2261> A_IWL<2260> A_IWL<2259> A_IWL<2258> A_IWL<2257> A_IWL<2256> A_IWL<2255> A_IWL<2254> A_IWL<2253> A_IWL<2252> A_IWL<2251> A_IWL<2250> A_IWL<2249> A_IWL<2248> A_IWL<2247> A_IWL<2246> A_IWL<2245> A_IWL<2244> A_IWL<2243> A_IWL<2242> A_IWL<2241> A_IWL<2240> A_IWL<2239> A_IWL<2238> A_IWL<2237> A_IWL<2236> A_IWL<2235> A_IWL<2234> A_IWL<2233> A_IWL<2232> A_IWL<2231> A_IWL<2230> A_IWL<2229> A_IWL<2228> A_IWL<2227> A_IWL<2226> A_IWL<2225> A_IWL<2224> A_IWL<2223> A_IWL<2222> A_IWL<2221> A_IWL<2220> A_IWL<2219> A_IWL<2218> A_IWL<2217> A_IWL<2216> A_IWL<2215> A_IWL<2214> A_IWL<2213> A_IWL<2212> A_IWL<2211> A_IWL<2210> A_IWL<2209> A_IWL<2208> A_IWL<2207> A_IWL<2206> A_IWL<2205> A_IWL<2204> A_IWL<2203> A_IWL<2202> A_IWL<2201> A_IWL<2200> A_IWL<2199> A_IWL<2198> A_IWL<2197> A_IWL<2196> A_IWL<2195> A_IWL<2194> A_IWL<2193> A_IWL<2192> A_IWL<2191> A_IWL<2190> A_IWL<2189> A_IWL<2188> A_IWL<2187> A_IWL<2186> A_IWL<2185> A_IWL<2184> A_IWL<2183> A_IWL<2182> A_IWL<2181> A_IWL<2180> A_IWL<2179> A_IWL<2178> A_IWL<2177> A_IWL<2176> A_IWL<2175> A_IWL<2174> A_IWL<2173> A_IWL<2172> A_IWL<2171> A_IWL<2170> A_IWL<2169> A_IWL<2168> A_IWL<2167> A_IWL<2166> A_IWL<2165> A_IWL<2164> A_IWL<2163> A_IWL<2162> A_IWL<2161> A_IWL<2160> A_IWL<2159> A_IWL<2158> A_IWL<2157> A_IWL<2156> A_IWL<2155> A_IWL<2154> A_IWL<2153> A_IWL<2152> A_IWL<2151> A_IWL<2150> A_IWL<2149> A_IWL<2148> A_IWL<2147> A_IWL<2146> A_IWL<2145> A_IWL<2144> A_IWL<2143> A_IWL<2142> A_IWL<2141> A_IWL<2140> A_IWL<2139> A_IWL<2138> A_IWL<2137> A_IWL<2136> A_IWL<2135> A_IWL<2134> A_IWL<2133> A_IWL<2132> A_IWL<2131> A_IWL<2130> A_IWL<2129> A_IWL<2128> A_IWL<2127> A_IWL<2126> A_IWL<2125> A_IWL<2124> A_IWL<2123> A_IWL<2122> A_IWL<2121> A_IWL<2120> A_IWL<2119> A_IWL<2118> A_IWL<2117> A_IWL<2116> A_IWL<2115> A_IWL<2114> A_IWL<2113> A_IWL<2112> A_IWL<2111> A_IWL<2110> A_IWL<2109> A_IWL<2108> A_IWL<2107> A_IWL<2106> A_IWL<2105> A_IWL<2104> A_IWL<2103> A_IWL<2102> A_IWL<2101> A_IWL<2100> A_IWL<2099> A_IWL<2098> A_IWL<2097> A_IWL<2096> A_IWL<2095> A_IWL<2094> A_IWL<2093> A_IWL<2092> A_IWL<2091> A_IWL<2090> A_IWL<2089> A_IWL<2088> A_IWL<2087> A_IWL<2086> A_IWL<2085> A_IWL<2084> A_IWL<2083> A_IWL<2082> A_IWL<2081> A_IWL<2080> A_IWL<2079> A_IWL<2078> A_IWL<2077> A_IWL<2076> A_IWL<2075> A_IWL<2074> A_IWL<2073> A_IWL<2072> A_IWL<2071> A_IWL<2070> A_IWL<2069> A_IWL<2068> A_IWL<2067> A_IWL<2066> A_IWL<2065> A_IWL<2064> A_IWL<2063> A_IWL<2062> A_IWL<2061> A_IWL<2060> A_IWL<2059> A_IWL<2058> A_IWL<2057> A_IWL<2056> A_IWL<2055> A_IWL<2054> A_IWL<2053> A_IWL<2052> A_IWL<2051> A_IWL<2050> A_IWL<2049> A_IWL<2048> A_IWL<2559> A_IWL<2558> A_IWL<2557> A_IWL<2556> A_IWL<2555> A_IWL<2554> A_IWL<2553> A_IWL<2552> A_IWL<2551> A_IWL<2550> A_IWL<2549> A_IWL<2548> A_IWL<2547> A_IWL<2546> A_IWL<2545> A_IWL<2544> A_IWL<2543> A_IWL<2542> A_IWL<2541> A_IWL<2540> A_IWL<2539> A_IWL<2538> A_IWL<2537> A_IWL<2536> A_IWL<2535> A_IWL<2534> A_IWL<2533> A_IWL<2532> A_IWL<2531> A_IWL<2530> A_IWL<2529> A_IWL<2528> A_IWL<2527> A_IWL<2526> A_IWL<2525> A_IWL<2524> A_IWL<2523> A_IWL<2522> A_IWL<2521> A_IWL<2520> A_IWL<2519> A_IWL<2518> A_IWL<2517> A_IWL<2516> A_IWL<2515> A_IWL<2514> A_IWL<2513> A_IWL<2512> A_IWL<2511> A_IWL<2510> A_IWL<2509> A_IWL<2508> A_IWL<2507> A_IWL<2506> A_IWL<2505> A_IWL<2504> A_IWL<2503> A_IWL<2502> A_IWL<2501> A_IWL<2500> A_IWL<2499> A_IWL<2498> A_IWL<2497> A_IWL<2496> A_IWL<2495> A_IWL<2494> A_IWL<2493> A_IWL<2492> A_IWL<2491> A_IWL<2490> A_IWL<2489> A_IWL<2488> A_IWL<2487> A_IWL<2486> A_IWL<2485> A_IWL<2484> A_IWL<2483> A_IWL<2482> A_IWL<2481> A_IWL<2480> A_IWL<2479> A_IWL<2478> A_IWL<2477> A_IWL<2476> A_IWL<2475> A_IWL<2474> A_IWL<2473> A_IWL<2472> A_IWL<2471> A_IWL<2470> A_IWL<2469> A_IWL<2468> A_IWL<2467> A_IWL<2466> A_IWL<2465> A_IWL<2464> A_IWL<2463> A_IWL<2462> A_IWL<2461> A_IWL<2460> A_IWL<2459> A_IWL<2458> A_IWL<2457> A_IWL<2456> A_IWL<2455> A_IWL<2454> A_IWL<2453> A_IWL<2452> A_IWL<2451> A_IWL<2450> A_IWL<2449> A_IWL<2448> A_IWL<2447> A_IWL<2446> A_IWL<2445> A_IWL<2444> A_IWL<2443> A_IWL<2442> A_IWL<2441> A_IWL<2440> A_IWL<2439> A_IWL<2438> A_IWL<2437> A_IWL<2436> A_IWL<2435> A_IWL<2434> A_IWL<2433> A_IWL<2432> A_IWL<2431> A_IWL<2430> A_IWL<2429> A_IWL<2428> A_IWL<2427> A_IWL<2426> A_IWL<2425> A_IWL<2424> A_IWL<2423> A_IWL<2422> A_IWL<2421> A_IWL<2420> A_IWL<2419> A_IWL<2418> A_IWL<2417> A_IWL<2416> A_IWL<2415> A_IWL<2414> A_IWL<2413> A_IWL<2412> A_IWL<2411> A_IWL<2410> A_IWL<2409> A_IWL<2408> A_IWL<2407> A_IWL<2406> A_IWL<2405> A_IWL<2404> A_IWL<2403> A_IWL<2402> A_IWL<2401> A_IWL<2400> A_IWL<2399> A_IWL<2398> A_IWL<2397> A_IWL<2396> A_IWL<2395> A_IWL<2394> A_IWL<2393> A_IWL<2392> A_IWL<2391> A_IWL<2390> A_IWL<2389> A_IWL<2388> A_IWL<2387> A_IWL<2386> A_IWL<2385> A_IWL<2384> A_IWL<2383> A_IWL<2382> A_IWL<2381> A_IWL<2380> A_IWL<2379> A_IWL<2378> A_IWL<2377> A_IWL<2376> A_IWL<2375> A_IWL<2374> A_IWL<2373> A_IWL<2372> A_IWL<2371> A_IWL<2370> A_IWL<2369> A_IWL<2368> A_IWL<2367> A_IWL<2366> A_IWL<2365> A_IWL<2364> A_IWL<2363> A_IWL<2362> A_IWL<2361> A_IWL<2360> A_IWL<2359> A_IWL<2358> A_IWL<2357> A_IWL<2356> A_IWL<2355> A_IWL<2354> A_IWL<2353> A_IWL<2352> A_IWL<2351> A_IWL<2350> A_IWL<2349> A_IWL<2348> A_IWL<2347> A_IWL<2346> A_IWL<2345> A_IWL<2344> A_IWL<2343> A_IWL<2342> A_IWL<2341> A_IWL<2340> A_IWL<2339> A_IWL<2338> A_IWL<2337> A_IWL<2336> A_IWL<2335> A_IWL<2334> A_IWL<2333> A_IWL<2332> A_IWL<2331> A_IWL<2330> A_IWL<2329> A_IWL<2328> A_IWL<2327> A_IWL<2326> A_IWL<2325> A_IWL<2324> A_IWL<2323> A_IWL<2322> A_IWL<2321> A_IWL<2320> A_IWL<2319> A_IWL<2318> A_IWL<2317> A_IWL<2316> A_IWL<2315> A_IWL<2314> A_IWL<2313> A_IWL<2312> A_IWL<2311> A_IWL<2310> A_IWL<2309> A_IWL<2308> A_IWL<2307> A_IWL<2306> A_IWL<2305> A_IWL<2304> VDD_CORE VSS / RM_IHPSG13_1024x32_c2_1P_COLUMN_pcell_0 +XCOL<8> A_BLC<17> A_BLC<16> A_BLC_TOP<17> A_BLC_TOP<16> A_BLT<17> A_BLT<16> A_BLT_TOP<17> A_BLT_TOP<16> A_IWL<2047> A_IWL<2046> A_IWL<2045> A_IWL<2044> A_IWL<2043> A_IWL<2042> A_IWL<2041> A_IWL<2040> A_IWL<2039> A_IWL<2038> A_IWL<2037> A_IWL<2036> A_IWL<2035> A_IWL<2034> A_IWL<2033> A_IWL<2032> A_IWL<2031> A_IWL<2030> A_IWL<2029> A_IWL<2028> A_IWL<2027> A_IWL<2026> A_IWL<2025> A_IWL<2024> A_IWL<2023> A_IWL<2022> A_IWL<2021> A_IWL<2020> A_IWL<2019> A_IWL<2018> A_IWL<2017> A_IWL<2016> A_IWL<2015> A_IWL<2014> A_IWL<2013> A_IWL<2012> A_IWL<2011> A_IWL<2010> A_IWL<2009> A_IWL<2008> A_IWL<2007> A_IWL<2006> A_IWL<2005> A_IWL<2004> A_IWL<2003> A_IWL<2002> A_IWL<2001> A_IWL<2000> A_IWL<1999> A_IWL<1998> A_IWL<1997> A_IWL<1996> A_IWL<1995> A_IWL<1994> A_IWL<1993> A_IWL<1992> A_IWL<1991> A_IWL<1990> A_IWL<1989> A_IWL<1988> A_IWL<1987> A_IWL<1986> A_IWL<1985> A_IWL<1984> A_IWL<1983> A_IWL<1982> A_IWL<1981> A_IWL<1980> A_IWL<1979> A_IWL<1978> A_IWL<1977> A_IWL<1976> A_IWL<1975> A_IWL<1974> A_IWL<1973> A_IWL<1972> A_IWL<1971> A_IWL<1970> A_IWL<1969> A_IWL<1968> A_IWL<1967> A_IWL<1966> A_IWL<1965> A_IWL<1964> A_IWL<1963> A_IWL<1962> A_IWL<1961> A_IWL<1960> A_IWL<1959> A_IWL<1958> A_IWL<1957> A_IWL<1956> A_IWL<1955> A_IWL<1954> A_IWL<1953> A_IWL<1952> A_IWL<1951> A_IWL<1950> A_IWL<1949> A_IWL<1948> A_IWL<1947> A_IWL<1946> A_IWL<1945> A_IWL<1944> A_IWL<1943> A_IWL<1942> A_IWL<1941> A_IWL<1940> A_IWL<1939> A_IWL<1938> A_IWL<1937> A_IWL<1936> A_IWL<1935> A_IWL<1934> A_IWL<1933> A_IWL<1932> A_IWL<1931> A_IWL<1930> A_IWL<1929> A_IWL<1928> A_IWL<1927> A_IWL<1926> A_IWL<1925> A_IWL<1924> A_IWL<1923> A_IWL<1922> A_IWL<1921> A_IWL<1920> A_IWL<1919> A_IWL<1918> A_IWL<1917> A_IWL<1916> A_IWL<1915> A_IWL<1914> A_IWL<1913> A_IWL<1912> A_IWL<1911> A_IWL<1910> A_IWL<1909> A_IWL<1908> A_IWL<1907> A_IWL<1906> A_IWL<1905> A_IWL<1904> A_IWL<1903> A_IWL<1902> A_IWL<1901> A_IWL<1900> A_IWL<1899> A_IWL<1898> A_IWL<1897> A_IWL<1896> A_IWL<1895> A_IWL<1894> A_IWL<1893> A_IWL<1892> A_IWL<1891> A_IWL<1890> A_IWL<1889> A_IWL<1888> A_IWL<1887> A_IWL<1886> A_IWL<1885> A_IWL<1884> A_IWL<1883> A_IWL<1882> A_IWL<1881> A_IWL<1880> A_IWL<1879> A_IWL<1878> A_IWL<1877> A_IWL<1876> A_IWL<1875> A_IWL<1874> A_IWL<1873> A_IWL<1872> A_IWL<1871> A_IWL<1870> A_IWL<1869> A_IWL<1868> A_IWL<1867> A_IWL<1866> A_IWL<1865> A_IWL<1864> A_IWL<1863> A_IWL<1862> A_IWL<1861> A_IWL<1860> A_IWL<1859> A_IWL<1858> A_IWL<1857> A_IWL<1856> A_IWL<1855> A_IWL<1854> A_IWL<1853> A_IWL<1852> A_IWL<1851> A_IWL<1850> A_IWL<1849> A_IWL<1848> A_IWL<1847> A_IWL<1846> A_IWL<1845> A_IWL<1844> A_IWL<1843> A_IWL<1842> A_IWL<1841> A_IWL<1840> A_IWL<1839> A_IWL<1838> A_IWL<1837> A_IWL<1836> A_IWL<1835> A_IWL<1834> A_IWL<1833> A_IWL<1832> A_IWL<1831> A_IWL<1830> A_IWL<1829> A_IWL<1828> A_IWL<1827> A_IWL<1826> A_IWL<1825> A_IWL<1824> A_IWL<1823> A_IWL<1822> A_IWL<1821> A_IWL<1820> A_IWL<1819> A_IWL<1818> A_IWL<1817> A_IWL<1816> A_IWL<1815> A_IWL<1814> A_IWL<1813> A_IWL<1812> A_IWL<1811> A_IWL<1810> A_IWL<1809> A_IWL<1808> A_IWL<1807> A_IWL<1806> A_IWL<1805> A_IWL<1804> A_IWL<1803> A_IWL<1802> A_IWL<1801> A_IWL<1800> A_IWL<1799> A_IWL<1798> A_IWL<1797> A_IWL<1796> A_IWL<1795> A_IWL<1794> A_IWL<1793> A_IWL<1792> A_IWL<2303> A_IWL<2302> A_IWL<2301> A_IWL<2300> A_IWL<2299> A_IWL<2298> A_IWL<2297> A_IWL<2296> A_IWL<2295> A_IWL<2294> A_IWL<2293> A_IWL<2292> A_IWL<2291> A_IWL<2290> A_IWL<2289> A_IWL<2288> A_IWL<2287> A_IWL<2286> A_IWL<2285> A_IWL<2284> A_IWL<2283> A_IWL<2282> A_IWL<2281> A_IWL<2280> A_IWL<2279> A_IWL<2278> A_IWL<2277> A_IWL<2276> A_IWL<2275> A_IWL<2274> A_IWL<2273> A_IWL<2272> A_IWL<2271> A_IWL<2270> A_IWL<2269> A_IWL<2268> A_IWL<2267> A_IWL<2266> A_IWL<2265> A_IWL<2264> A_IWL<2263> A_IWL<2262> A_IWL<2261> A_IWL<2260> A_IWL<2259> A_IWL<2258> A_IWL<2257> A_IWL<2256> A_IWL<2255> A_IWL<2254> A_IWL<2253> A_IWL<2252> A_IWL<2251> A_IWL<2250> A_IWL<2249> A_IWL<2248> A_IWL<2247> A_IWL<2246> A_IWL<2245> A_IWL<2244> A_IWL<2243> A_IWL<2242> A_IWL<2241> A_IWL<2240> A_IWL<2239> A_IWL<2238> A_IWL<2237> A_IWL<2236> A_IWL<2235> A_IWL<2234> A_IWL<2233> A_IWL<2232> A_IWL<2231> A_IWL<2230> A_IWL<2229> A_IWL<2228> A_IWL<2227> A_IWL<2226> A_IWL<2225> A_IWL<2224> A_IWL<2223> A_IWL<2222> A_IWL<2221> A_IWL<2220> A_IWL<2219> A_IWL<2218> A_IWL<2217> A_IWL<2216> A_IWL<2215> A_IWL<2214> A_IWL<2213> A_IWL<2212> A_IWL<2211> A_IWL<2210> A_IWL<2209> A_IWL<2208> A_IWL<2207> A_IWL<2206> A_IWL<2205> A_IWL<2204> A_IWL<2203> A_IWL<2202> A_IWL<2201> A_IWL<2200> A_IWL<2199> A_IWL<2198> A_IWL<2197> A_IWL<2196> A_IWL<2195> A_IWL<2194> A_IWL<2193> A_IWL<2192> A_IWL<2191> A_IWL<2190> A_IWL<2189> A_IWL<2188> A_IWL<2187> A_IWL<2186> A_IWL<2185> A_IWL<2184> A_IWL<2183> A_IWL<2182> A_IWL<2181> A_IWL<2180> A_IWL<2179> A_IWL<2178> A_IWL<2177> A_IWL<2176> A_IWL<2175> A_IWL<2174> A_IWL<2173> A_IWL<2172> A_IWL<2171> A_IWL<2170> A_IWL<2169> A_IWL<2168> A_IWL<2167> A_IWL<2166> A_IWL<2165> A_IWL<2164> A_IWL<2163> A_IWL<2162> A_IWL<2161> A_IWL<2160> A_IWL<2159> A_IWL<2158> A_IWL<2157> A_IWL<2156> A_IWL<2155> A_IWL<2154> A_IWL<2153> A_IWL<2152> A_IWL<2151> A_IWL<2150> A_IWL<2149> A_IWL<2148> A_IWL<2147> A_IWL<2146> A_IWL<2145> A_IWL<2144> A_IWL<2143> A_IWL<2142> A_IWL<2141> A_IWL<2140> A_IWL<2139> A_IWL<2138> A_IWL<2137> A_IWL<2136> A_IWL<2135> A_IWL<2134> A_IWL<2133> A_IWL<2132> A_IWL<2131> A_IWL<2130> A_IWL<2129> A_IWL<2128> A_IWL<2127> A_IWL<2126> A_IWL<2125> A_IWL<2124> A_IWL<2123> A_IWL<2122> A_IWL<2121> A_IWL<2120> A_IWL<2119> A_IWL<2118> A_IWL<2117> A_IWL<2116> A_IWL<2115> A_IWL<2114> A_IWL<2113> A_IWL<2112> A_IWL<2111> A_IWL<2110> A_IWL<2109> A_IWL<2108> A_IWL<2107> A_IWL<2106> A_IWL<2105> A_IWL<2104> A_IWL<2103> A_IWL<2102> A_IWL<2101> A_IWL<2100> A_IWL<2099> A_IWL<2098> A_IWL<2097> A_IWL<2096> A_IWL<2095> A_IWL<2094> A_IWL<2093> A_IWL<2092> A_IWL<2091> A_IWL<2090> A_IWL<2089> A_IWL<2088> A_IWL<2087> A_IWL<2086> A_IWL<2085> A_IWL<2084> A_IWL<2083> A_IWL<2082> A_IWL<2081> A_IWL<2080> A_IWL<2079> A_IWL<2078> A_IWL<2077> A_IWL<2076> A_IWL<2075> A_IWL<2074> A_IWL<2073> A_IWL<2072> A_IWL<2071> A_IWL<2070> A_IWL<2069> A_IWL<2068> A_IWL<2067> A_IWL<2066> A_IWL<2065> A_IWL<2064> A_IWL<2063> A_IWL<2062> A_IWL<2061> A_IWL<2060> A_IWL<2059> A_IWL<2058> A_IWL<2057> A_IWL<2056> A_IWL<2055> A_IWL<2054> A_IWL<2053> A_IWL<2052> A_IWL<2051> A_IWL<2050> A_IWL<2049> A_IWL<2048> VDD_CORE VSS / RM_IHPSG13_1024x32_c2_1P_COLUMN_pcell_0 +XCOL<7> A_BLC<15> A_BLC<14> A_BLC_TOP<15> A_BLC_TOP<14> A_BLT<15> A_BLT<14> A_BLT_TOP<15> A_BLT_TOP<14> A_IWL<1791> A_IWL<1790> A_IWL<1789> A_IWL<1788> A_IWL<1787> A_IWL<1786> A_IWL<1785> A_IWL<1784> A_IWL<1783> A_IWL<1782> A_IWL<1781> A_IWL<1780> A_IWL<1779> A_IWL<1778> A_IWL<1777> A_IWL<1776> A_IWL<1775> A_IWL<1774> A_IWL<1773> A_IWL<1772> A_IWL<1771> A_IWL<1770> A_IWL<1769> A_IWL<1768> A_IWL<1767> A_IWL<1766> A_IWL<1765> A_IWL<1764> A_IWL<1763> A_IWL<1762> A_IWL<1761> A_IWL<1760> A_IWL<1759> A_IWL<1758> A_IWL<1757> A_IWL<1756> A_IWL<1755> A_IWL<1754> A_IWL<1753> A_IWL<1752> A_IWL<1751> A_IWL<1750> A_IWL<1749> A_IWL<1748> A_IWL<1747> A_IWL<1746> A_IWL<1745> A_IWL<1744> A_IWL<1743> A_IWL<1742> A_IWL<1741> A_IWL<1740> A_IWL<1739> A_IWL<1738> A_IWL<1737> A_IWL<1736> A_IWL<1735> A_IWL<1734> A_IWL<1733> A_IWL<1732> A_IWL<1731> A_IWL<1730> A_IWL<1729> A_IWL<1728> A_IWL<1727> A_IWL<1726> A_IWL<1725> A_IWL<1724> A_IWL<1723> A_IWL<1722> A_IWL<1721> A_IWL<1720> A_IWL<1719> A_IWL<1718> A_IWL<1717> A_IWL<1716> A_IWL<1715> A_IWL<1714> A_IWL<1713> A_IWL<1712> A_IWL<1711> A_IWL<1710> A_IWL<1709> A_IWL<1708> A_IWL<1707> A_IWL<1706> A_IWL<1705> A_IWL<1704> A_IWL<1703> A_IWL<1702> A_IWL<1701> A_IWL<1700> A_IWL<1699> A_IWL<1698> A_IWL<1697> A_IWL<1696> A_IWL<1695> A_IWL<1694> A_IWL<1693> A_IWL<1692> A_IWL<1691> A_IWL<1690> A_IWL<1689> A_IWL<1688> A_IWL<1687> A_IWL<1686> A_IWL<1685> A_IWL<1684> A_IWL<1683> A_IWL<1682> A_IWL<1681> A_IWL<1680> A_IWL<1679> A_IWL<1678> A_IWL<1677> A_IWL<1676> A_IWL<1675> A_IWL<1674> A_IWL<1673> A_IWL<1672> A_IWL<1671> A_IWL<1670> A_IWL<1669> A_IWL<1668> A_IWL<1667> A_IWL<1666> A_IWL<1665> A_IWL<1664> A_IWL<1663> A_IWL<1662> A_IWL<1661> A_IWL<1660> A_IWL<1659> A_IWL<1658> A_IWL<1657> A_IWL<1656> A_IWL<1655> A_IWL<1654> A_IWL<1653> A_IWL<1652> A_IWL<1651> A_IWL<1650> A_IWL<1649> A_IWL<1648> A_IWL<1647> A_IWL<1646> A_IWL<1645> A_IWL<1644> A_IWL<1643> A_IWL<1642> A_IWL<1641> A_IWL<1640> A_IWL<1639> A_IWL<1638> A_IWL<1637> A_IWL<1636> A_IWL<1635> A_IWL<1634> A_IWL<1633> A_IWL<1632> A_IWL<1631> A_IWL<1630> A_IWL<1629> A_IWL<1628> A_IWL<1627> A_IWL<1626> A_IWL<1625> A_IWL<1624> A_IWL<1623> A_IWL<1622> A_IWL<1621> A_IWL<1620> A_IWL<1619> A_IWL<1618> A_IWL<1617> A_IWL<1616> A_IWL<1615> A_IWL<1614> A_IWL<1613> A_IWL<1612> A_IWL<1611> A_IWL<1610> A_IWL<1609> A_IWL<1608> A_IWL<1607> A_IWL<1606> A_IWL<1605> A_IWL<1604> A_IWL<1603> A_IWL<1602> A_IWL<1601> A_IWL<1600> A_IWL<1599> A_IWL<1598> A_IWL<1597> A_IWL<1596> A_IWL<1595> A_IWL<1594> A_IWL<1593> A_IWL<1592> A_IWL<1591> A_IWL<1590> A_IWL<1589> A_IWL<1588> A_IWL<1587> A_IWL<1586> A_IWL<1585> A_IWL<1584> A_IWL<1583> A_IWL<1582> A_IWL<1581> A_IWL<1580> A_IWL<1579> A_IWL<1578> A_IWL<1577> A_IWL<1576> A_IWL<1575> A_IWL<1574> A_IWL<1573> A_IWL<1572> A_IWL<1571> A_IWL<1570> A_IWL<1569> A_IWL<1568> A_IWL<1567> A_IWL<1566> A_IWL<1565> A_IWL<1564> A_IWL<1563> A_IWL<1562> A_IWL<1561> A_IWL<1560> A_IWL<1559> A_IWL<1558> A_IWL<1557> A_IWL<1556> A_IWL<1555> A_IWL<1554> A_IWL<1553> A_IWL<1552> A_IWL<1551> A_IWL<1550> A_IWL<1549> A_IWL<1548> A_IWL<1547> A_IWL<1546> A_IWL<1545> A_IWL<1544> A_IWL<1543> A_IWL<1542> A_IWL<1541> A_IWL<1540> A_IWL<1539> A_IWL<1538> A_IWL<1537> A_IWL<1536> A_IWL<2047> A_IWL<2046> A_IWL<2045> A_IWL<2044> A_IWL<2043> A_IWL<2042> A_IWL<2041> A_IWL<2040> A_IWL<2039> A_IWL<2038> A_IWL<2037> A_IWL<2036> A_IWL<2035> A_IWL<2034> A_IWL<2033> A_IWL<2032> A_IWL<2031> A_IWL<2030> A_IWL<2029> A_IWL<2028> A_IWL<2027> A_IWL<2026> A_IWL<2025> A_IWL<2024> A_IWL<2023> A_IWL<2022> A_IWL<2021> A_IWL<2020> A_IWL<2019> A_IWL<2018> A_IWL<2017> A_IWL<2016> A_IWL<2015> A_IWL<2014> A_IWL<2013> A_IWL<2012> A_IWL<2011> A_IWL<2010> A_IWL<2009> A_IWL<2008> A_IWL<2007> A_IWL<2006> A_IWL<2005> A_IWL<2004> A_IWL<2003> A_IWL<2002> A_IWL<2001> A_IWL<2000> A_IWL<1999> A_IWL<1998> A_IWL<1997> A_IWL<1996> A_IWL<1995> A_IWL<1994> A_IWL<1993> A_IWL<1992> A_IWL<1991> A_IWL<1990> A_IWL<1989> A_IWL<1988> A_IWL<1987> A_IWL<1986> A_IWL<1985> A_IWL<1984> A_IWL<1983> A_IWL<1982> A_IWL<1981> A_IWL<1980> A_IWL<1979> A_IWL<1978> A_IWL<1977> A_IWL<1976> A_IWL<1975> A_IWL<1974> A_IWL<1973> A_IWL<1972> A_IWL<1971> A_IWL<1970> A_IWL<1969> A_IWL<1968> A_IWL<1967> A_IWL<1966> A_IWL<1965> A_IWL<1964> A_IWL<1963> A_IWL<1962> A_IWL<1961> A_IWL<1960> A_IWL<1959> A_IWL<1958> A_IWL<1957> A_IWL<1956> A_IWL<1955> A_IWL<1954> A_IWL<1953> A_IWL<1952> A_IWL<1951> A_IWL<1950> A_IWL<1949> A_IWL<1948> A_IWL<1947> A_IWL<1946> A_IWL<1945> A_IWL<1944> A_IWL<1943> A_IWL<1942> A_IWL<1941> A_IWL<1940> A_IWL<1939> A_IWL<1938> A_IWL<1937> A_IWL<1936> A_IWL<1935> A_IWL<1934> A_IWL<1933> A_IWL<1932> A_IWL<1931> A_IWL<1930> A_IWL<1929> A_IWL<1928> A_IWL<1927> A_IWL<1926> A_IWL<1925> A_IWL<1924> A_IWL<1923> A_IWL<1922> A_IWL<1921> A_IWL<1920> A_IWL<1919> A_IWL<1918> A_IWL<1917> A_IWL<1916> A_IWL<1915> A_IWL<1914> A_IWL<1913> A_IWL<1912> A_IWL<1911> A_IWL<1910> A_IWL<1909> A_IWL<1908> A_IWL<1907> A_IWL<1906> A_IWL<1905> A_IWL<1904> A_IWL<1903> A_IWL<1902> A_IWL<1901> A_IWL<1900> A_IWL<1899> A_IWL<1898> A_IWL<1897> A_IWL<1896> A_IWL<1895> A_IWL<1894> A_IWL<1893> A_IWL<1892> A_IWL<1891> A_IWL<1890> A_IWL<1889> A_IWL<1888> A_IWL<1887> A_IWL<1886> A_IWL<1885> A_IWL<1884> A_IWL<1883> A_IWL<1882> A_IWL<1881> A_IWL<1880> A_IWL<1879> A_IWL<1878> A_IWL<1877> A_IWL<1876> A_IWL<1875> A_IWL<1874> A_IWL<1873> A_IWL<1872> A_IWL<1871> A_IWL<1870> A_IWL<1869> A_IWL<1868> A_IWL<1867> A_IWL<1866> A_IWL<1865> A_IWL<1864> A_IWL<1863> A_IWL<1862> A_IWL<1861> A_IWL<1860> A_IWL<1859> A_IWL<1858> A_IWL<1857> A_IWL<1856> A_IWL<1855> A_IWL<1854> A_IWL<1853> A_IWL<1852> A_IWL<1851> A_IWL<1850> A_IWL<1849> A_IWL<1848> A_IWL<1847> A_IWL<1846> A_IWL<1845> A_IWL<1844> A_IWL<1843> A_IWL<1842> A_IWL<1841> A_IWL<1840> A_IWL<1839> A_IWL<1838> A_IWL<1837> A_IWL<1836> A_IWL<1835> A_IWL<1834> A_IWL<1833> A_IWL<1832> A_IWL<1831> A_IWL<1830> A_IWL<1829> A_IWL<1828> A_IWL<1827> A_IWL<1826> A_IWL<1825> A_IWL<1824> A_IWL<1823> A_IWL<1822> A_IWL<1821> A_IWL<1820> A_IWL<1819> A_IWL<1818> A_IWL<1817> A_IWL<1816> A_IWL<1815> A_IWL<1814> A_IWL<1813> A_IWL<1812> A_IWL<1811> A_IWL<1810> A_IWL<1809> A_IWL<1808> A_IWL<1807> A_IWL<1806> A_IWL<1805> A_IWL<1804> A_IWL<1803> A_IWL<1802> A_IWL<1801> A_IWL<1800> A_IWL<1799> A_IWL<1798> A_IWL<1797> A_IWL<1796> A_IWL<1795> A_IWL<1794> A_IWL<1793> A_IWL<1792> VDD_CORE VSS / RM_IHPSG13_1024x32_c2_1P_COLUMN_pcell_0 +XCOL<6> A_BLC<13> A_BLC<12> A_BLC_TOP<13> A_BLC_TOP<12> A_BLT<13> A_BLT<12> A_BLT_TOP<13> A_BLT_TOP<12> A_IWL<1535> A_IWL<1534> A_IWL<1533> A_IWL<1532> A_IWL<1531> A_IWL<1530> A_IWL<1529> A_IWL<1528> A_IWL<1527> A_IWL<1526> A_IWL<1525> A_IWL<1524> A_IWL<1523> A_IWL<1522> A_IWL<1521> A_IWL<1520> A_IWL<1519> A_IWL<1518> A_IWL<1517> A_IWL<1516> A_IWL<1515> A_IWL<1514> A_IWL<1513> A_IWL<1512> A_IWL<1511> A_IWL<1510> A_IWL<1509> A_IWL<1508> A_IWL<1507> A_IWL<1506> A_IWL<1505> A_IWL<1504> A_IWL<1503> A_IWL<1502> A_IWL<1501> A_IWL<1500> A_IWL<1499> A_IWL<1498> A_IWL<1497> A_IWL<1496> A_IWL<1495> A_IWL<1494> A_IWL<1493> A_IWL<1492> A_IWL<1491> A_IWL<1490> A_IWL<1489> A_IWL<1488> A_IWL<1487> A_IWL<1486> A_IWL<1485> A_IWL<1484> A_IWL<1483> A_IWL<1482> A_IWL<1481> A_IWL<1480> A_IWL<1479> A_IWL<1478> A_IWL<1477> A_IWL<1476> A_IWL<1475> A_IWL<1474> A_IWL<1473> A_IWL<1472> A_IWL<1471> A_IWL<1470> A_IWL<1469> A_IWL<1468> A_IWL<1467> A_IWL<1466> A_IWL<1465> A_IWL<1464> A_IWL<1463> A_IWL<1462> A_IWL<1461> A_IWL<1460> A_IWL<1459> A_IWL<1458> A_IWL<1457> A_IWL<1456> A_IWL<1455> A_IWL<1454> A_IWL<1453> A_IWL<1452> A_IWL<1451> A_IWL<1450> A_IWL<1449> A_IWL<1448> A_IWL<1447> A_IWL<1446> A_IWL<1445> A_IWL<1444> A_IWL<1443> A_IWL<1442> A_IWL<1441> A_IWL<1440> A_IWL<1439> A_IWL<1438> A_IWL<1437> A_IWL<1436> A_IWL<1435> A_IWL<1434> A_IWL<1433> A_IWL<1432> A_IWL<1431> A_IWL<1430> A_IWL<1429> A_IWL<1428> A_IWL<1427> A_IWL<1426> A_IWL<1425> A_IWL<1424> A_IWL<1423> A_IWL<1422> A_IWL<1421> A_IWL<1420> A_IWL<1419> A_IWL<1418> A_IWL<1417> A_IWL<1416> A_IWL<1415> A_IWL<1414> A_IWL<1413> A_IWL<1412> A_IWL<1411> A_IWL<1410> A_IWL<1409> A_IWL<1408> A_IWL<1407> A_IWL<1406> A_IWL<1405> A_IWL<1404> A_IWL<1403> A_IWL<1402> A_IWL<1401> A_IWL<1400> A_IWL<1399> A_IWL<1398> A_IWL<1397> A_IWL<1396> A_IWL<1395> A_IWL<1394> A_IWL<1393> A_IWL<1392> A_IWL<1391> A_IWL<1390> A_IWL<1389> A_IWL<1388> A_IWL<1387> A_IWL<1386> A_IWL<1385> A_IWL<1384> A_IWL<1383> A_IWL<1382> A_IWL<1381> A_IWL<1380> A_IWL<1379> A_IWL<1378> A_IWL<1377> A_IWL<1376> A_IWL<1375> A_IWL<1374> A_IWL<1373> A_IWL<1372> A_IWL<1371> A_IWL<1370> A_IWL<1369> A_IWL<1368> A_IWL<1367> A_IWL<1366> A_IWL<1365> A_IWL<1364> A_IWL<1363> A_IWL<1362> A_IWL<1361> A_IWL<1360> A_IWL<1359> A_IWL<1358> A_IWL<1357> A_IWL<1356> A_IWL<1355> A_IWL<1354> A_IWL<1353> A_IWL<1352> A_IWL<1351> A_IWL<1350> A_IWL<1349> A_IWL<1348> A_IWL<1347> A_IWL<1346> A_IWL<1345> A_IWL<1344> A_IWL<1343> A_IWL<1342> A_IWL<1341> A_IWL<1340> A_IWL<1339> A_IWL<1338> A_IWL<1337> A_IWL<1336> A_IWL<1335> A_IWL<1334> A_IWL<1333> A_IWL<1332> A_IWL<1331> A_IWL<1330> A_IWL<1329> A_IWL<1328> A_IWL<1327> A_IWL<1326> A_IWL<1325> A_IWL<1324> A_IWL<1323> A_IWL<1322> A_IWL<1321> A_IWL<1320> A_IWL<1319> A_IWL<1318> A_IWL<1317> A_IWL<1316> A_IWL<1315> A_IWL<1314> A_IWL<1313> A_IWL<1312> A_IWL<1311> A_IWL<1310> A_IWL<1309> A_IWL<1308> A_IWL<1307> A_IWL<1306> A_IWL<1305> A_IWL<1304> A_IWL<1303> A_IWL<1302> A_IWL<1301> A_IWL<1300> A_IWL<1299> A_IWL<1298> A_IWL<1297> A_IWL<1296> A_IWL<1295> A_IWL<1294> A_IWL<1293> A_IWL<1292> A_IWL<1291> A_IWL<1290> A_IWL<1289> A_IWL<1288> A_IWL<1287> A_IWL<1286> A_IWL<1285> A_IWL<1284> A_IWL<1283> A_IWL<1282> A_IWL<1281> A_IWL<1280> A_IWL<1791> A_IWL<1790> A_IWL<1789> A_IWL<1788> A_IWL<1787> A_IWL<1786> A_IWL<1785> A_IWL<1784> A_IWL<1783> A_IWL<1782> A_IWL<1781> A_IWL<1780> A_IWL<1779> A_IWL<1778> A_IWL<1777> A_IWL<1776> A_IWL<1775> A_IWL<1774> A_IWL<1773> A_IWL<1772> A_IWL<1771> A_IWL<1770> A_IWL<1769> A_IWL<1768> A_IWL<1767> A_IWL<1766> A_IWL<1765> A_IWL<1764> A_IWL<1763> A_IWL<1762> A_IWL<1761> A_IWL<1760> A_IWL<1759> A_IWL<1758> A_IWL<1757> A_IWL<1756> A_IWL<1755> A_IWL<1754> A_IWL<1753> A_IWL<1752> A_IWL<1751> A_IWL<1750> A_IWL<1749> A_IWL<1748> A_IWL<1747> A_IWL<1746> A_IWL<1745> A_IWL<1744> A_IWL<1743> A_IWL<1742> A_IWL<1741> A_IWL<1740> A_IWL<1739> A_IWL<1738> A_IWL<1737> A_IWL<1736> A_IWL<1735> A_IWL<1734> A_IWL<1733> A_IWL<1732> A_IWL<1731> A_IWL<1730> A_IWL<1729> A_IWL<1728> A_IWL<1727> A_IWL<1726> A_IWL<1725> A_IWL<1724> A_IWL<1723> A_IWL<1722> A_IWL<1721> A_IWL<1720> A_IWL<1719> A_IWL<1718> A_IWL<1717> A_IWL<1716> A_IWL<1715> A_IWL<1714> A_IWL<1713> A_IWL<1712> A_IWL<1711> A_IWL<1710> A_IWL<1709> A_IWL<1708> A_IWL<1707> A_IWL<1706> A_IWL<1705> A_IWL<1704> A_IWL<1703> A_IWL<1702> A_IWL<1701> A_IWL<1700> A_IWL<1699> A_IWL<1698> A_IWL<1697> A_IWL<1696> A_IWL<1695> A_IWL<1694> A_IWL<1693> A_IWL<1692> A_IWL<1691> A_IWL<1690> A_IWL<1689> A_IWL<1688> A_IWL<1687> A_IWL<1686> A_IWL<1685> A_IWL<1684> A_IWL<1683> A_IWL<1682> A_IWL<1681> A_IWL<1680> A_IWL<1679> A_IWL<1678> A_IWL<1677> A_IWL<1676> A_IWL<1675> A_IWL<1674> A_IWL<1673> A_IWL<1672> A_IWL<1671> A_IWL<1670> A_IWL<1669> A_IWL<1668> A_IWL<1667> A_IWL<1666> A_IWL<1665> A_IWL<1664> A_IWL<1663> A_IWL<1662> A_IWL<1661> A_IWL<1660> A_IWL<1659> A_IWL<1658> A_IWL<1657> A_IWL<1656> A_IWL<1655> A_IWL<1654> A_IWL<1653> A_IWL<1652> A_IWL<1651> A_IWL<1650> A_IWL<1649> A_IWL<1648> A_IWL<1647> A_IWL<1646> A_IWL<1645> A_IWL<1644> A_IWL<1643> A_IWL<1642> A_IWL<1641> A_IWL<1640> A_IWL<1639> A_IWL<1638> A_IWL<1637> A_IWL<1636> A_IWL<1635> A_IWL<1634> A_IWL<1633> A_IWL<1632> A_IWL<1631> A_IWL<1630> A_IWL<1629> A_IWL<1628> A_IWL<1627> A_IWL<1626> A_IWL<1625> A_IWL<1624> A_IWL<1623> A_IWL<1622> A_IWL<1621> A_IWL<1620> A_IWL<1619> A_IWL<1618> A_IWL<1617> A_IWL<1616> A_IWL<1615> A_IWL<1614> A_IWL<1613> A_IWL<1612> A_IWL<1611> A_IWL<1610> A_IWL<1609> A_IWL<1608> A_IWL<1607> A_IWL<1606> A_IWL<1605> A_IWL<1604> A_IWL<1603> A_IWL<1602> A_IWL<1601> A_IWL<1600> A_IWL<1599> A_IWL<1598> A_IWL<1597> A_IWL<1596> A_IWL<1595> A_IWL<1594> A_IWL<1593> A_IWL<1592> A_IWL<1591> A_IWL<1590> A_IWL<1589> A_IWL<1588> A_IWL<1587> A_IWL<1586> A_IWL<1585> A_IWL<1584> A_IWL<1583> A_IWL<1582> A_IWL<1581> A_IWL<1580> A_IWL<1579> A_IWL<1578> A_IWL<1577> A_IWL<1576> A_IWL<1575> A_IWL<1574> A_IWL<1573> A_IWL<1572> A_IWL<1571> A_IWL<1570> A_IWL<1569> A_IWL<1568> A_IWL<1567> A_IWL<1566> A_IWL<1565> A_IWL<1564> A_IWL<1563> A_IWL<1562> A_IWL<1561> A_IWL<1560> A_IWL<1559> A_IWL<1558> A_IWL<1557> A_IWL<1556> A_IWL<1555> A_IWL<1554> A_IWL<1553> A_IWL<1552> A_IWL<1551> A_IWL<1550> A_IWL<1549> A_IWL<1548> A_IWL<1547> A_IWL<1546> A_IWL<1545> A_IWL<1544> A_IWL<1543> A_IWL<1542> A_IWL<1541> A_IWL<1540> A_IWL<1539> A_IWL<1538> A_IWL<1537> A_IWL<1536> VDD_CORE VSS / RM_IHPSG13_1024x32_c2_1P_COLUMN_pcell_0 +XCOL<5> A_BLC<11> A_BLC<10> A_BLC_TOP<11> A_BLC_TOP<10> A_BLT<11> A_BLT<10> A_BLT_TOP<11> A_BLT_TOP<10> A_IWL<1279> A_IWL<1278> A_IWL<1277> A_IWL<1276> A_IWL<1275> A_IWL<1274> A_IWL<1273> A_IWL<1272> A_IWL<1271> A_IWL<1270> A_IWL<1269> A_IWL<1268> A_IWL<1267> A_IWL<1266> A_IWL<1265> A_IWL<1264> A_IWL<1263> A_IWL<1262> A_IWL<1261> A_IWL<1260> A_IWL<1259> A_IWL<1258> A_IWL<1257> A_IWL<1256> A_IWL<1255> A_IWL<1254> A_IWL<1253> A_IWL<1252> A_IWL<1251> A_IWL<1250> A_IWL<1249> A_IWL<1248> A_IWL<1247> A_IWL<1246> A_IWL<1245> A_IWL<1244> A_IWL<1243> A_IWL<1242> A_IWL<1241> A_IWL<1240> A_IWL<1239> A_IWL<1238> A_IWL<1237> A_IWL<1236> A_IWL<1235> A_IWL<1234> A_IWL<1233> A_IWL<1232> A_IWL<1231> A_IWL<1230> A_IWL<1229> A_IWL<1228> A_IWL<1227> A_IWL<1226> A_IWL<1225> A_IWL<1224> A_IWL<1223> A_IWL<1222> A_IWL<1221> A_IWL<1220> A_IWL<1219> A_IWL<1218> A_IWL<1217> A_IWL<1216> A_IWL<1215> A_IWL<1214> A_IWL<1213> A_IWL<1212> A_IWL<1211> A_IWL<1210> A_IWL<1209> A_IWL<1208> A_IWL<1207> A_IWL<1206> A_IWL<1205> A_IWL<1204> A_IWL<1203> A_IWL<1202> A_IWL<1201> A_IWL<1200> A_IWL<1199> A_IWL<1198> A_IWL<1197> A_IWL<1196> A_IWL<1195> A_IWL<1194> A_IWL<1193> A_IWL<1192> A_IWL<1191> A_IWL<1190> A_IWL<1189> A_IWL<1188> A_IWL<1187> A_IWL<1186> A_IWL<1185> A_IWL<1184> A_IWL<1183> A_IWL<1182> A_IWL<1181> A_IWL<1180> A_IWL<1179> A_IWL<1178> A_IWL<1177> A_IWL<1176> A_IWL<1175> A_IWL<1174> A_IWL<1173> A_IWL<1172> A_IWL<1171> A_IWL<1170> A_IWL<1169> A_IWL<1168> A_IWL<1167> A_IWL<1166> A_IWL<1165> A_IWL<1164> A_IWL<1163> A_IWL<1162> A_IWL<1161> A_IWL<1160> A_IWL<1159> A_IWL<1158> A_IWL<1157> A_IWL<1156> A_IWL<1155> A_IWL<1154> A_IWL<1153> A_IWL<1152> A_IWL<1151> A_IWL<1150> A_IWL<1149> A_IWL<1148> A_IWL<1147> A_IWL<1146> A_IWL<1145> A_IWL<1144> A_IWL<1143> A_IWL<1142> A_IWL<1141> A_IWL<1140> A_IWL<1139> A_IWL<1138> A_IWL<1137> A_IWL<1136> A_IWL<1135> A_IWL<1134> A_IWL<1133> A_IWL<1132> A_IWL<1131> A_IWL<1130> A_IWL<1129> A_IWL<1128> A_IWL<1127> A_IWL<1126> A_IWL<1125> A_IWL<1124> A_IWL<1123> A_IWL<1122> A_IWL<1121> A_IWL<1120> A_IWL<1119> A_IWL<1118> A_IWL<1117> A_IWL<1116> A_IWL<1115> A_IWL<1114> A_IWL<1113> A_IWL<1112> A_IWL<1111> A_IWL<1110> A_IWL<1109> A_IWL<1108> A_IWL<1107> A_IWL<1106> A_IWL<1105> A_IWL<1104> A_IWL<1103> A_IWL<1102> A_IWL<1101> A_IWL<1100> A_IWL<1099> A_IWL<1098> A_IWL<1097> A_IWL<1096> A_IWL<1095> A_IWL<1094> A_IWL<1093> A_IWL<1092> A_IWL<1091> A_IWL<1090> A_IWL<1089> A_IWL<1088> A_IWL<1087> A_IWL<1086> A_IWL<1085> A_IWL<1084> A_IWL<1083> A_IWL<1082> A_IWL<1081> A_IWL<1080> A_IWL<1079> A_IWL<1078> A_IWL<1077> A_IWL<1076> A_IWL<1075> A_IWL<1074> A_IWL<1073> A_IWL<1072> A_IWL<1071> A_IWL<1070> A_IWL<1069> A_IWL<1068> A_IWL<1067> A_IWL<1066> A_IWL<1065> A_IWL<1064> A_IWL<1063> A_IWL<1062> A_IWL<1061> A_IWL<1060> A_IWL<1059> A_IWL<1058> A_IWL<1057> A_IWL<1056> A_IWL<1055> A_IWL<1054> A_IWL<1053> A_IWL<1052> A_IWL<1051> A_IWL<1050> A_IWL<1049> A_IWL<1048> A_IWL<1047> A_IWL<1046> A_IWL<1045> A_IWL<1044> A_IWL<1043> A_IWL<1042> A_IWL<1041> A_IWL<1040> A_IWL<1039> A_IWL<1038> A_IWL<1037> A_IWL<1036> A_IWL<1035> A_IWL<1034> A_IWL<1033> A_IWL<1032> A_IWL<1031> A_IWL<1030> A_IWL<1029> A_IWL<1028> A_IWL<1027> A_IWL<1026> A_IWL<1025> A_IWL<1024> A_IWL<1535> A_IWL<1534> A_IWL<1533> A_IWL<1532> A_IWL<1531> A_IWL<1530> A_IWL<1529> A_IWL<1528> A_IWL<1527> A_IWL<1526> A_IWL<1525> A_IWL<1524> A_IWL<1523> A_IWL<1522> A_IWL<1521> A_IWL<1520> A_IWL<1519> A_IWL<1518> A_IWL<1517> A_IWL<1516> A_IWL<1515> A_IWL<1514> A_IWL<1513> A_IWL<1512> A_IWL<1511> A_IWL<1510> A_IWL<1509> A_IWL<1508> A_IWL<1507> A_IWL<1506> A_IWL<1505> A_IWL<1504> A_IWL<1503> A_IWL<1502> A_IWL<1501> A_IWL<1500> A_IWL<1499> A_IWL<1498> A_IWL<1497> A_IWL<1496> A_IWL<1495> A_IWL<1494> A_IWL<1493> A_IWL<1492> A_IWL<1491> A_IWL<1490> A_IWL<1489> A_IWL<1488> A_IWL<1487> A_IWL<1486> A_IWL<1485> A_IWL<1484> A_IWL<1483> A_IWL<1482> A_IWL<1481> A_IWL<1480> A_IWL<1479> A_IWL<1478> A_IWL<1477> A_IWL<1476> A_IWL<1475> A_IWL<1474> A_IWL<1473> A_IWL<1472> A_IWL<1471> A_IWL<1470> A_IWL<1469> A_IWL<1468> A_IWL<1467> A_IWL<1466> A_IWL<1465> A_IWL<1464> A_IWL<1463> A_IWL<1462> A_IWL<1461> A_IWL<1460> A_IWL<1459> A_IWL<1458> A_IWL<1457> A_IWL<1456> A_IWL<1455> A_IWL<1454> A_IWL<1453> A_IWL<1452> A_IWL<1451> A_IWL<1450> A_IWL<1449> A_IWL<1448> A_IWL<1447> A_IWL<1446> A_IWL<1445> A_IWL<1444> A_IWL<1443> A_IWL<1442> A_IWL<1441> A_IWL<1440> A_IWL<1439> A_IWL<1438> A_IWL<1437> A_IWL<1436> A_IWL<1435> A_IWL<1434> A_IWL<1433> A_IWL<1432> A_IWL<1431> A_IWL<1430> A_IWL<1429> A_IWL<1428> A_IWL<1427> A_IWL<1426> A_IWL<1425> A_IWL<1424> A_IWL<1423> A_IWL<1422> A_IWL<1421> A_IWL<1420> A_IWL<1419> A_IWL<1418> A_IWL<1417> A_IWL<1416> A_IWL<1415> A_IWL<1414> A_IWL<1413> A_IWL<1412> A_IWL<1411> A_IWL<1410> A_IWL<1409> A_IWL<1408> A_IWL<1407> A_IWL<1406> A_IWL<1405> A_IWL<1404> A_IWL<1403> A_IWL<1402> A_IWL<1401> A_IWL<1400> A_IWL<1399> A_IWL<1398> A_IWL<1397> A_IWL<1396> A_IWL<1395> A_IWL<1394> A_IWL<1393> A_IWL<1392> A_IWL<1391> A_IWL<1390> A_IWL<1389> A_IWL<1388> A_IWL<1387> A_IWL<1386> A_IWL<1385> A_IWL<1384> A_IWL<1383> A_IWL<1382> A_IWL<1381> A_IWL<1380> A_IWL<1379> A_IWL<1378> A_IWL<1377> A_IWL<1376> A_IWL<1375> A_IWL<1374> A_IWL<1373> A_IWL<1372> A_IWL<1371> A_IWL<1370> A_IWL<1369> A_IWL<1368> A_IWL<1367> A_IWL<1366> A_IWL<1365> A_IWL<1364> A_IWL<1363> A_IWL<1362> A_IWL<1361> A_IWL<1360> A_IWL<1359> A_IWL<1358> A_IWL<1357> A_IWL<1356> A_IWL<1355> A_IWL<1354> A_IWL<1353> A_IWL<1352> A_IWL<1351> A_IWL<1350> A_IWL<1349> A_IWL<1348> A_IWL<1347> A_IWL<1346> A_IWL<1345> A_IWL<1344> A_IWL<1343> A_IWL<1342> A_IWL<1341> A_IWL<1340> A_IWL<1339> A_IWL<1338> A_IWL<1337> A_IWL<1336> A_IWL<1335> A_IWL<1334> A_IWL<1333> A_IWL<1332> A_IWL<1331> A_IWL<1330> A_IWL<1329> A_IWL<1328> A_IWL<1327> A_IWL<1326> A_IWL<1325> A_IWL<1324> A_IWL<1323> A_IWL<1322> A_IWL<1321> A_IWL<1320> A_IWL<1319> A_IWL<1318> A_IWL<1317> A_IWL<1316> A_IWL<1315> A_IWL<1314> A_IWL<1313> A_IWL<1312> A_IWL<1311> A_IWL<1310> A_IWL<1309> A_IWL<1308> A_IWL<1307> A_IWL<1306> A_IWL<1305> A_IWL<1304> A_IWL<1303> A_IWL<1302> A_IWL<1301> A_IWL<1300> A_IWL<1299> A_IWL<1298> A_IWL<1297> A_IWL<1296> A_IWL<1295> A_IWL<1294> A_IWL<1293> A_IWL<1292> A_IWL<1291> A_IWL<1290> A_IWL<1289> A_IWL<1288> A_IWL<1287> A_IWL<1286> A_IWL<1285> A_IWL<1284> A_IWL<1283> A_IWL<1282> A_IWL<1281> A_IWL<1280> VDD_CORE VSS / RM_IHPSG13_1024x32_c2_1P_COLUMN_pcell_0 +XCOL<4> A_BLC<9> A_BLC<8> A_BLC_TOP<9> A_BLC_TOP<8> A_BLT<9> A_BLT<8> A_BLT_TOP<9> A_BLT_TOP<8> A_IWL<1023> A_IWL<1022> A_IWL<1021> A_IWL<1020> A_IWL<1019> A_IWL<1018> A_IWL<1017> A_IWL<1016> A_IWL<1015> A_IWL<1014> A_IWL<1013> A_IWL<1012> A_IWL<1011> A_IWL<1010> A_IWL<1009> A_IWL<1008> A_IWL<1007> A_IWL<1006> A_IWL<1005> A_IWL<1004> A_IWL<1003> A_IWL<1002> A_IWL<1001> A_IWL<1000> A_IWL<999> A_IWL<998> A_IWL<997> A_IWL<996> A_IWL<995> A_IWL<994> A_IWL<993> A_IWL<992> A_IWL<991> A_IWL<990> A_IWL<989> A_IWL<988> A_IWL<987> A_IWL<986> A_IWL<985> A_IWL<984> A_IWL<983> A_IWL<982> A_IWL<981> A_IWL<980> A_IWL<979> A_IWL<978> A_IWL<977> A_IWL<976> A_IWL<975> A_IWL<974> A_IWL<973> A_IWL<972> A_IWL<971> A_IWL<970> A_IWL<969> A_IWL<968> A_IWL<967> A_IWL<966> A_IWL<965> A_IWL<964> A_IWL<963> A_IWL<962> A_IWL<961> A_IWL<960> A_IWL<959> A_IWL<958> A_IWL<957> A_IWL<956> A_IWL<955> A_IWL<954> A_IWL<953> A_IWL<952> A_IWL<951> A_IWL<950> A_IWL<949> A_IWL<948> A_IWL<947> A_IWL<946> A_IWL<945> A_IWL<944> A_IWL<943> A_IWL<942> A_IWL<941> A_IWL<940> A_IWL<939> A_IWL<938> A_IWL<937> A_IWL<936> A_IWL<935> A_IWL<934> A_IWL<933> A_IWL<932> A_IWL<931> A_IWL<930> A_IWL<929> A_IWL<928> A_IWL<927> A_IWL<926> A_IWL<925> A_IWL<924> A_IWL<923> A_IWL<922> A_IWL<921> A_IWL<920> A_IWL<919> A_IWL<918> A_IWL<917> A_IWL<916> A_IWL<915> A_IWL<914> A_IWL<913> A_IWL<912> A_IWL<911> A_IWL<910> A_IWL<909> A_IWL<908> A_IWL<907> A_IWL<906> A_IWL<905> A_IWL<904> A_IWL<903> A_IWL<902> A_IWL<901> A_IWL<900> A_IWL<899> A_IWL<898> A_IWL<897> A_IWL<896> A_IWL<895> A_IWL<894> A_IWL<893> A_IWL<892> A_IWL<891> A_IWL<890> A_IWL<889> A_IWL<888> A_IWL<887> A_IWL<886> A_IWL<885> A_IWL<884> A_IWL<883> A_IWL<882> A_IWL<881> A_IWL<880> A_IWL<879> A_IWL<878> A_IWL<877> A_IWL<876> A_IWL<875> A_IWL<874> A_IWL<873> A_IWL<872> A_IWL<871> A_IWL<870> A_IWL<869> A_IWL<868> A_IWL<867> A_IWL<866> A_IWL<865> A_IWL<864> A_IWL<863> A_IWL<862> A_IWL<861> A_IWL<860> A_IWL<859> A_IWL<858> A_IWL<857> A_IWL<856> A_IWL<855> A_IWL<854> A_IWL<853> A_IWL<852> A_IWL<851> A_IWL<850> A_IWL<849> A_IWL<848> A_IWL<847> A_IWL<846> A_IWL<845> A_IWL<844> A_IWL<843> A_IWL<842> A_IWL<841> A_IWL<840> A_IWL<839> A_IWL<838> A_IWL<837> A_IWL<836> A_IWL<835> A_IWL<834> A_IWL<833> A_IWL<832> A_IWL<831> A_IWL<830> A_IWL<829> A_IWL<828> A_IWL<827> A_IWL<826> A_IWL<825> A_IWL<824> A_IWL<823> A_IWL<822> A_IWL<821> A_IWL<820> A_IWL<819> A_IWL<818> A_IWL<817> A_IWL<816> A_IWL<815> A_IWL<814> A_IWL<813> A_IWL<812> A_IWL<811> A_IWL<810> A_IWL<809> A_IWL<808> A_IWL<807> A_IWL<806> A_IWL<805> A_IWL<804> A_IWL<803> A_IWL<802> A_IWL<801> A_IWL<800> A_IWL<799> A_IWL<798> A_IWL<797> A_IWL<796> A_IWL<795> A_IWL<794> A_IWL<793> A_IWL<792> A_IWL<791> A_IWL<790> A_IWL<789> A_IWL<788> A_IWL<787> A_IWL<786> A_IWL<785> A_IWL<784> A_IWL<783> A_IWL<782> A_IWL<781> A_IWL<780> A_IWL<779> A_IWL<778> A_IWL<777> A_IWL<776> A_IWL<775> A_IWL<774> A_IWL<773> A_IWL<772> A_IWL<771> A_IWL<770> A_IWL<769> A_IWL<768> A_IWL<1279> A_IWL<1278> A_IWL<1277> A_IWL<1276> A_IWL<1275> A_IWL<1274> A_IWL<1273> A_IWL<1272> A_IWL<1271> A_IWL<1270> A_IWL<1269> A_IWL<1268> A_IWL<1267> A_IWL<1266> A_IWL<1265> A_IWL<1264> A_IWL<1263> A_IWL<1262> A_IWL<1261> A_IWL<1260> A_IWL<1259> A_IWL<1258> A_IWL<1257> A_IWL<1256> A_IWL<1255> A_IWL<1254> A_IWL<1253> A_IWL<1252> A_IWL<1251> A_IWL<1250> A_IWL<1249> A_IWL<1248> A_IWL<1247> A_IWL<1246> A_IWL<1245> A_IWL<1244> A_IWL<1243> A_IWL<1242> A_IWL<1241> A_IWL<1240> A_IWL<1239> A_IWL<1238> A_IWL<1237> A_IWL<1236> A_IWL<1235> A_IWL<1234> A_IWL<1233> A_IWL<1232> A_IWL<1231> A_IWL<1230> A_IWL<1229> A_IWL<1228> A_IWL<1227> A_IWL<1226> A_IWL<1225> A_IWL<1224> A_IWL<1223> A_IWL<1222> A_IWL<1221> A_IWL<1220> A_IWL<1219> A_IWL<1218> A_IWL<1217> A_IWL<1216> A_IWL<1215> A_IWL<1214> A_IWL<1213> A_IWL<1212> A_IWL<1211> A_IWL<1210> A_IWL<1209> A_IWL<1208> A_IWL<1207> A_IWL<1206> A_IWL<1205> A_IWL<1204> A_IWL<1203> A_IWL<1202> A_IWL<1201> A_IWL<1200> A_IWL<1199> A_IWL<1198> A_IWL<1197> A_IWL<1196> A_IWL<1195> A_IWL<1194> A_IWL<1193> A_IWL<1192> A_IWL<1191> A_IWL<1190> A_IWL<1189> A_IWL<1188> A_IWL<1187> A_IWL<1186> A_IWL<1185> A_IWL<1184> A_IWL<1183> A_IWL<1182> A_IWL<1181> A_IWL<1180> A_IWL<1179> A_IWL<1178> A_IWL<1177> A_IWL<1176> A_IWL<1175> A_IWL<1174> A_IWL<1173> A_IWL<1172> A_IWL<1171> A_IWL<1170> A_IWL<1169> A_IWL<1168> A_IWL<1167> A_IWL<1166> A_IWL<1165> A_IWL<1164> A_IWL<1163> A_IWL<1162> A_IWL<1161> A_IWL<1160> A_IWL<1159> A_IWL<1158> A_IWL<1157> A_IWL<1156> A_IWL<1155> A_IWL<1154> A_IWL<1153> A_IWL<1152> A_IWL<1151> A_IWL<1150> A_IWL<1149> A_IWL<1148> A_IWL<1147> A_IWL<1146> A_IWL<1145> A_IWL<1144> A_IWL<1143> A_IWL<1142> A_IWL<1141> A_IWL<1140> A_IWL<1139> A_IWL<1138> A_IWL<1137> A_IWL<1136> A_IWL<1135> A_IWL<1134> A_IWL<1133> A_IWL<1132> A_IWL<1131> A_IWL<1130> A_IWL<1129> A_IWL<1128> A_IWL<1127> A_IWL<1126> A_IWL<1125> A_IWL<1124> A_IWL<1123> A_IWL<1122> A_IWL<1121> A_IWL<1120> A_IWL<1119> A_IWL<1118> A_IWL<1117> A_IWL<1116> A_IWL<1115> A_IWL<1114> A_IWL<1113> A_IWL<1112> A_IWL<1111> A_IWL<1110> A_IWL<1109> A_IWL<1108> A_IWL<1107> A_IWL<1106> A_IWL<1105> A_IWL<1104> A_IWL<1103> A_IWL<1102> A_IWL<1101> A_IWL<1100> A_IWL<1099> A_IWL<1098> A_IWL<1097> A_IWL<1096> A_IWL<1095> A_IWL<1094> A_IWL<1093> A_IWL<1092> A_IWL<1091> A_IWL<1090> A_IWL<1089> A_IWL<1088> A_IWL<1087> A_IWL<1086> A_IWL<1085> A_IWL<1084> A_IWL<1083> A_IWL<1082> A_IWL<1081> A_IWL<1080> A_IWL<1079> A_IWL<1078> A_IWL<1077> A_IWL<1076> A_IWL<1075> A_IWL<1074> A_IWL<1073> A_IWL<1072> A_IWL<1071> A_IWL<1070> A_IWL<1069> A_IWL<1068> A_IWL<1067> A_IWL<1066> A_IWL<1065> A_IWL<1064> A_IWL<1063> A_IWL<1062> A_IWL<1061> A_IWL<1060> A_IWL<1059> A_IWL<1058> A_IWL<1057> A_IWL<1056> A_IWL<1055> A_IWL<1054> A_IWL<1053> A_IWL<1052> A_IWL<1051> A_IWL<1050> A_IWL<1049> A_IWL<1048> A_IWL<1047> A_IWL<1046> A_IWL<1045> A_IWL<1044> A_IWL<1043> A_IWL<1042> A_IWL<1041> A_IWL<1040> A_IWL<1039> A_IWL<1038> A_IWL<1037> A_IWL<1036> A_IWL<1035> A_IWL<1034> A_IWL<1033> A_IWL<1032> A_IWL<1031> A_IWL<1030> A_IWL<1029> A_IWL<1028> A_IWL<1027> A_IWL<1026> A_IWL<1025> A_IWL<1024> VDD_CORE VSS / RM_IHPSG13_1024x32_c2_1P_COLUMN_pcell_0 +XCOL<3> A_BLC<7> A_BLC<6> A_BLC_TOP<7> A_BLC_TOP<6> A_BLT<7> A_BLT<6> A_BLT_TOP<7> A_BLT_TOP<6> A_IWL<767> A_IWL<766> A_IWL<765> A_IWL<764> A_IWL<763> A_IWL<762> A_IWL<761> A_IWL<760> A_IWL<759> A_IWL<758> A_IWL<757> A_IWL<756> A_IWL<755> A_IWL<754> A_IWL<753> A_IWL<752> A_IWL<751> A_IWL<750> A_IWL<749> A_IWL<748> A_IWL<747> A_IWL<746> A_IWL<745> A_IWL<744> A_IWL<743> A_IWL<742> A_IWL<741> A_IWL<740> A_IWL<739> A_IWL<738> A_IWL<737> A_IWL<736> A_IWL<735> A_IWL<734> A_IWL<733> A_IWL<732> A_IWL<731> A_IWL<730> A_IWL<729> A_IWL<728> A_IWL<727> A_IWL<726> A_IWL<725> A_IWL<724> A_IWL<723> A_IWL<722> A_IWL<721> A_IWL<720> A_IWL<719> A_IWL<718> A_IWL<717> A_IWL<716> A_IWL<715> A_IWL<714> A_IWL<713> A_IWL<712> A_IWL<711> A_IWL<710> A_IWL<709> A_IWL<708> A_IWL<707> A_IWL<706> A_IWL<705> A_IWL<704> A_IWL<703> A_IWL<702> A_IWL<701> A_IWL<700> A_IWL<699> A_IWL<698> A_IWL<697> A_IWL<696> A_IWL<695> A_IWL<694> A_IWL<693> A_IWL<692> A_IWL<691> A_IWL<690> A_IWL<689> A_IWL<688> A_IWL<687> A_IWL<686> A_IWL<685> A_IWL<684> A_IWL<683> A_IWL<682> A_IWL<681> A_IWL<680> A_IWL<679> A_IWL<678> A_IWL<677> A_IWL<676> A_IWL<675> A_IWL<674> A_IWL<673> A_IWL<672> A_IWL<671> A_IWL<670> A_IWL<669> A_IWL<668> A_IWL<667> A_IWL<666> A_IWL<665> A_IWL<664> A_IWL<663> A_IWL<662> A_IWL<661> A_IWL<660> A_IWL<659> A_IWL<658> A_IWL<657> A_IWL<656> A_IWL<655> A_IWL<654> A_IWL<653> A_IWL<652> A_IWL<651> A_IWL<650> A_IWL<649> A_IWL<648> A_IWL<647> A_IWL<646> A_IWL<645> A_IWL<644> A_IWL<643> A_IWL<642> A_IWL<641> A_IWL<640> A_IWL<639> A_IWL<638> A_IWL<637> A_IWL<636> A_IWL<635> A_IWL<634> A_IWL<633> A_IWL<632> A_IWL<631> A_IWL<630> A_IWL<629> A_IWL<628> A_IWL<627> A_IWL<626> A_IWL<625> A_IWL<624> A_IWL<623> A_IWL<622> A_IWL<621> A_IWL<620> A_IWL<619> A_IWL<618> A_IWL<617> A_IWL<616> A_IWL<615> A_IWL<614> A_IWL<613> A_IWL<612> A_IWL<611> A_IWL<610> A_IWL<609> A_IWL<608> A_IWL<607> A_IWL<606> A_IWL<605> A_IWL<604> A_IWL<603> A_IWL<602> A_IWL<601> A_IWL<600> A_IWL<599> A_IWL<598> A_IWL<597> A_IWL<596> A_IWL<595> A_IWL<594> A_IWL<593> A_IWL<592> A_IWL<591> A_IWL<590> A_IWL<589> A_IWL<588> A_IWL<587> A_IWL<586> A_IWL<585> A_IWL<584> A_IWL<583> A_IWL<582> A_IWL<581> A_IWL<580> A_IWL<579> A_IWL<578> A_IWL<577> A_IWL<576> A_IWL<575> A_IWL<574> A_IWL<573> A_IWL<572> A_IWL<571> A_IWL<570> A_IWL<569> A_IWL<568> A_IWL<567> A_IWL<566> A_IWL<565> A_IWL<564> A_IWL<563> A_IWL<562> A_IWL<561> A_IWL<560> A_IWL<559> A_IWL<558> A_IWL<557> A_IWL<556> A_IWL<555> A_IWL<554> A_IWL<553> A_IWL<552> A_IWL<551> A_IWL<550> A_IWL<549> A_IWL<548> A_IWL<547> A_IWL<546> A_IWL<545> A_IWL<544> A_IWL<543> A_IWL<542> A_IWL<541> A_IWL<540> A_IWL<539> A_IWL<538> A_IWL<537> A_IWL<536> A_IWL<535> A_IWL<534> A_IWL<533> A_IWL<532> A_IWL<531> A_IWL<530> A_IWL<529> A_IWL<528> A_IWL<527> A_IWL<526> A_IWL<525> A_IWL<524> A_IWL<523> A_IWL<522> A_IWL<521> A_IWL<520> A_IWL<519> A_IWL<518> A_IWL<517> A_IWL<516> A_IWL<515> A_IWL<514> A_IWL<513> A_IWL<512> A_IWL<1023> A_IWL<1022> A_IWL<1021> A_IWL<1020> A_IWL<1019> A_IWL<1018> A_IWL<1017> A_IWL<1016> A_IWL<1015> A_IWL<1014> A_IWL<1013> A_IWL<1012> A_IWL<1011> A_IWL<1010> A_IWL<1009> A_IWL<1008> A_IWL<1007> A_IWL<1006> A_IWL<1005> A_IWL<1004> A_IWL<1003> A_IWL<1002> A_IWL<1001> A_IWL<1000> A_IWL<999> A_IWL<998> A_IWL<997> A_IWL<996> A_IWL<995> A_IWL<994> A_IWL<993> A_IWL<992> A_IWL<991> A_IWL<990> A_IWL<989> A_IWL<988> A_IWL<987> A_IWL<986> A_IWL<985> A_IWL<984> A_IWL<983> A_IWL<982> A_IWL<981> A_IWL<980> A_IWL<979> A_IWL<978> A_IWL<977> A_IWL<976> A_IWL<975> A_IWL<974> A_IWL<973> A_IWL<972> A_IWL<971> A_IWL<970> A_IWL<969> A_IWL<968> A_IWL<967> A_IWL<966> A_IWL<965> A_IWL<964> A_IWL<963> A_IWL<962> A_IWL<961> A_IWL<960> A_IWL<959> A_IWL<958> A_IWL<957> A_IWL<956> A_IWL<955> A_IWL<954> A_IWL<953> A_IWL<952> A_IWL<951> A_IWL<950> A_IWL<949> A_IWL<948> A_IWL<947> A_IWL<946> A_IWL<945> A_IWL<944> A_IWL<943> A_IWL<942> A_IWL<941> A_IWL<940> A_IWL<939> A_IWL<938> A_IWL<937> A_IWL<936> A_IWL<935> A_IWL<934> A_IWL<933> A_IWL<932> A_IWL<931> A_IWL<930> A_IWL<929> A_IWL<928> A_IWL<927> A_IWL<926> A_IWL<925> A_IWL<924> A_IWL<923> A_IWL<922> A_IWL<921> A_IWL<920> A_IWL<919> A_IWL<918> A_IWL<917> A_IWL<916> A_IWL<915> A_IWL<914> A_IWL<913> A_IWL<912> A_IWL<911> A_IWL<910> A_IWL<909> A_IWL<908> A_IWL<907> A_IWL<906> A_IWL<905> A_IWL<904> A_IWL<903> A_IWL<902> A_IWL<901> A_IWL<900> A_IWL<899> A_IWL<898> A_IWL<897> A_IWL<896> A_IWL<895> A_IWL<894> A_IWL<893> A_IWL<892> A_IWL<891> A_IWL<890> A_IWL<889> A_IWL<888> A_IWL<887> A_IWL<886> A_IWL<885> A_IWL<884> A_IWL<883> A_IWL<882> A_IWL<881> A_IWL<880> A_IWL<879> A_IWL<878> A_IWL<877> A_IWL<876> A_IWL<875> A_IWL<874> A_IWL<873> A_IWL<872> A_IWL<871> A_IWL<870> A_IWL<869> A_IWL<868> A_IWL<867> A_IWL<866> A_IWL<865> A_IWL<864> A_IWL<863> A_IWL<862> A_IWL<861> A_IWL<860> A_IWL<859> A_IWL<858> A_IWL<857> A_IWL<856> A_IWL<855> A_IWL<854> A_IWL<853> A_IWL<852> A_IWL<851> A_IWL<850> A_IWL<849> A_IWL<848> A_IWL<847> A_IWL<846> A_IWL<845> A_IWL<844> A_IWL<843> A_IWL<842> A_IWL<841> A_IWL<840> A_IWL<839> A_IWL<838> A_IWL<837> A_IWL<836> A_IWL<835> A_IWL<834> A_IWL<833> A_IWL<832> A_IWL<831> A_IWL<830> A_IWL<829> A_IWL<828> A_IWL<827> A_IWL<826> A_IWL<825> A_IWL<824> A_IWL<823> A_IWL<822> A_IWL<821> A_IWL<820> A_IWL<819> A_IWL<818> A_IWL<817> A_IWL<816> A_IWL<815> A_IWL<814> A_IWL<813> A_IWL<812> A_IWL<811> A_IWL<810> A_IWL<809> A_IWL<808> A_IWL<807> A_IWL<806> A_IWL<805> A_IWL<804> A_IWL<803> A_IWL<802> A_IWL<801> A_IWL<800> A_IWL<799> A_IWL<798> A_IWL<797> A_IWL<796> A_IWL<795> A_IWL<794> A_IWL<793> A_IWL<792> A_IWL<791> A_IWL<790> A_IWL<789> A_IWL<788> A_IWL<787> A_IWL<786> A_IWL<785> A_IWL<784> A_IWL<783> A_IWL<782> A_IWL<781> A_IWL<780> A_IWL<779> A_IWL<778> A_IWL<777> A_IWL<776> A_IWL<775> A_IWL<774> A_IWL<773> A_IWL<772> A_IWL<771> A_IWL<770> A_IWL<769> A_IWL<768> VDD_CORE VSS / RM_IHPSG13_1024x32_c2_1P_COLUMN_pcell_0 +XCOL<2> A_BLC<5> A_BLC<4> A_BLC_TOP<5> A_BLC_TOP<4> A_BLT<5> A_BLT<4> A_BLT_TOP<5> A_BLT_TOP<4> A_IWL<511> A_IWL<510> A_IWL<509> A_IWL<508> A_IWL<507> A_IWL<506> A_IWL<505> A_IWL<504> A_IWL<503> A_IWL<502> A_IWL<501> A_IWL<500> A_IWL<499> A_IWL<498> A_IWL<497> A_IWL<496> A_IWL<495> A_IWL<494> A_IWL<493> A_IWL<492> A_IWL<491> A_IWL<490> A_IWL<489> A_IWL<488> A_IWL<487> A_IWL<486> A_IWL<485> A_IWL<484> A_IWL<483> A_IWL<482> A_IWL<481> A_IWL<480> A_IWL<479> A_IWL<478> A_IWL<477> A_IWL<476> A_IWL<475> A_IWL<474> A_IWL<473> A_IWL<472> A_IWL<471> A_IWL<470> A_IWL<469> A_IWL<468> A_IWL<467> A_IWL<466> A_IWL<465> A_IWL<464> A_IWL<463> A_IWL<462> A_IWL<461> A_IWL<460> A_IWL<459> A_IWL<458> A_IWL<457> A_IWL<456> A_IWL<455> A_IWL<454> A_IWL<453> A_IWL<452> A_IWL<451> A_IWL<450> A_IWL<449> A_IWL<448> A_IWL<447> A_IWL<446> A_IWL<445> A_IWL<444> A_IWL<443> A_IWL<442> A_IWL<441> A_IWL<440> A_IWL<439> A_IWL<438> A_IWL<437> A_IWL<436> A_IWL<435> A_IWL<434> A_IWL<433> A_IWL<432> A_IWL<431> A_IWL<430> A_IWL<429> A_IWL<428> A_IWL<427> A_IWL<426> A_IWL<425> A_IWL<424> A_IWL<423> A_IWL<422> A_IWL<421> A_IWL<420> A_IWL<419> A_IWL<418> A_IWL<417> A_IWL<416> A_IWL<415> A_IWL<414> A_IWL<413> A_IWL<412> A_IWL<411> A_IWL<410> A_IWL<409> A_IWL<408> A_IWL<407> A_IWL<406> A_IWL<405> A_IWL<404> A_IWL<403> A_IWL<402> A_IWL<401> A_IWL<400> A_IWL<399> A_IWL<398> A_IWL<397> A_IWL<396> A_IWL<395> A_IWL<394> A_IWL<393> A_IWL<392> A_IWL<391> A_IWL<390> A_IWL<389> A_IWL<388> A_IWL<387> A_IWL<386> A_IWL<385> A_IWL<384> A_IWL<383> A_IWL<382> A_IWL<381> A_IWL<380> A_IWL<379> A_IWL<378> A_IWL<377> A_IWL<376> A_IWL<375> A_IWL<374> A_IWL<373> A_IWL<372> A_IWL<371> A_IWL<370> A_IWL<369> A_IWL<368> A_IWL<367> A_IWL<366> A_IWL<365> A_IWL<364> A_IWL<363> A_IWL<362> A_IWL<361> A_IWL<360> A_IWL<359> A_IWL<358> A_IWL<357> A_IWL<356> A_IWL<355> A_IWL<354> A_IWL<353> A_IWL<352> A_IWL<351> A_IWL<350> A_IWL<349> A_IWL<348> A_IWL<347> A_IWL<346> A_IWL<345> A_IWL<344> A_IWL<343> A_IWL<342> A_IWL<341> A_IWL<340> A_IWL<339> A_IWL<338> A_IWL<337> A_IWL<336> A_IWL<335> A_IWL<334> A_IWL<333> A_IWL<332> A_IWL<331> A_IWL<330> A_IWL<329> A_IWL<328> A_IWL<327> A_IWL<326> A_IWL<325> A_IWL<324> A_IWL<323> A_IWL<322> A_IWL<321> A_IWL<320> A_IWL<319> A_IWL<318> A_IWL<317> A_IWL<316> A_IWL<315> A_IWL<314> A_IWL<313> A_IWL<312> A_IWL<311> A_IWL<310> A_IWL<309> A_IWL<308> A_IWL<307> A_IWL<306> A_IWL<305> A_IWL<304> A_IWL<303> A_IWL<302> A_IWL<301> A_IWL<300> A_IWL<299> A_IWL<298> A_IWL<297> A_IWL<296> A_IWL<295> A_IWL<294> A_IWL<293> A_IWL<292> A_IWL<291> A_IWL<290> A_IWL<289> A_IWL<288> A_IWL<287> A_IWL<286> A_IWL<285> A_IWL<284> A_IWL<283> A_IWL<282> A_IWL<281> A_IWL<280> A_IWL<279> A_IWL<278> A_IWL<277> A_IWL<276> A_IWL<275> A_IWL<274> A_IWL<273> A_IWL<272> A_IWL<271> A_IWL<270> A_IWL<269> A_IWL<268> A_IWL<267> A_IWL<266> A_IWL<265> A_IWL<264> A_IWL<263> A_IWL<262> A_IWL<261> A_IWL<260> A_IWL<259> A_IWL<258> A_IWL<257> A_IWL<256> A_IWL<767> A_IWL<766> A_IWL<765> A_IWL<764> A_IWL<763> A_IWL<762> A_IWL<761> A_IWL<760> A_IWL<759> A_IWL<758> A_IWL<757> A_IWL<756> A_IWL<755> A_IWL<754> A_IWL<753> A_IWL<752> A_IWL<751> A_IWL<750> A_IWL<749> A_IWL<748> A_IWL<747> A_IWL<746> A_IWL<745> A_IWL<744> A_IWL<743> A_IWL<742> A_IWL<741> A_IWL<740> A_IWL<739> A_IWL<738> A_IWL<737> A_IWL<736> A_IWL<735> A_IWL<734> A_IWL<733> A_IWL<732> A_IWL<731> A_IWL<730> A_IWL<729> A_IWL<728> A_IWL<727> A_IWL<726> A_IWL<725> A_IWL<724> A_IWL<723> A_IWL<722> A_IWL<721> A_IWL<720> A_IWL<719> A_IWL<718> A_IWL<717> A_IWL<716> A_IWL<715> A_IWL<714> A_IWL<713> A_IWL<712> A_IWL<711> A_IWL<710> A_IWL<709> A_IWL<708> A_IWL<707> A_IWL<706> A_IWL<705> A_IWL<704> A_IWL<703> A_IWL<702> A_IWL<701> A_IWL<700> A_IWL<699> A_IWL<698> A_IWL<697> A_IWL<696> A_IWL<695> A_IWL<694> A_IWL<693> A_IWL<692> A_IWL<691> A_IWL<690> A_IWL<689> A_IWL<688> A_IWL<687> A_IWL<686> A_IWL<685> A_IWL<684> A_IWL<683> A_IWL<682> A_IWL<681> A_IWL<680> A_IWL<679> A_IWL<678> A_IWL<677> A_IWL<676> A_IWL<675> A_IWL<674> A_IWL<673> A_IWL<672> A_IWL<671> A_IWL<670> A_IWL<669> A_IWL<668> A_IWL<667> A_IWL<666> A_IWL<665> A_IWL<664> A_IWL<663> A_IWL<662> A_IWL<661> A_IWL<660> A_IWL<659> A_IWL<658> A_IWL<657> A_IWL<656> A_IWL<655> A_IWL<654> A_IWL<653> A_IWL<652> A_IWL<651> A_IWL<650> A_IWL<649> A_IWL<648> A_IWL<647> A_IWL<646> A_IWL<645> A_IWL<644> A_IWL<643> A_IWL<642> A_IWL<641> A_IWL<640> A_IWL<639> A_IWL<638> A_IWL<637> A_IWL<636> A_IWL<635> A_IWL<634> A_IWL<633> A_IWL<632> A_IWL<631> A_IWL<630> A_IWL<629> A_IWL<628> A_IWL<627> A_IWL<626> A_IWL<625> A_IWL<624> A_IWL<623> A_IWL<622> A_IWL<621> A_IWL<620> A_IWL<619> A_IWL<618> A_IWL<617> A_IWL<616> A_IWL<615> A_IWL<614> A_IWL<613> A_IWL<612> A_IWL<611> A_IWL<610> A_IWL<609> A_IWL<608> A_IWL<607> A_IWL<606> A_IWL<605> A_IWL<604> A_IWL<603> A_IWL<602> A_IWL<601> A_IWL<600> A_IWL<599> A_IWL<598> A_IWL<597> A_IWL<596> A_IWL<595> A_IWL<594> A_IWL<593> A_IWL<592> A_IWL<591> A_IWL<590> A_IWL<589> A_IWL<588> A_IWL<587> A_IWL<586> A_IWL<585> A_IWL<584> A_IWL<583> A_IWL<582> A_IWL<581> A_IWL<580> A_IWL<579> A_IWL<578> A_IWL<577> A_IWL<576> A_IWL<575> A_IWL<574> A_IWL<573> A_IWL<572> A_IWL<571> A_IWL<570> A_IWL<569> A_IWL<568> A_IWL<567> A_IWL<566> A_IWL<565> A_IWL<564> A_IWL<563> A_IWL<562> A_IWL<561> A_IWL<560> A_IWL<559> A_IWL<558> A_IWL<557> A_IWL<556> A_IWL<555> A_IWL<554> A_IWL<553> A_IWL<552> A_IWL<551> A_IWL<550> A_IWL<549> A_IWL<548> A_IWL<547> A_IWL<546> A_IWL<545> A_IWL<544> A_IWL<543> A_IWL<542> A_IWL<541> A_IWL<540> A_IWL<539> A_IWL<538> A_IWL<537> A_IWL<536> A_IWL<535> A_IWL<534> A_IWL<533> A_IWL<532> A_IWL<531> A_IWL<530> A_IWL<529> A_IWL<528> A_IWL<527> A_IWL<526> A_IWL<525> A_IWL<524> A_IWL<523> A_IWL<522> A_IWL<521> A_IWL<520> A_IWL<519> A_IWL<518> A_IWL<517> A_IWL<516> A_IWL<515> A_IWL<514> A_IWL<513> A_IWL<512> VDD_CORE VSS / RM_IHPSG13_1024x32_c2_1P_COLUMN_pcell_0 +XCOL<1> A_BLC<3> A_BLC<2> A_BLC_TOP<3> A_BLC_TOP<2> A_BLT<3> A_BLT<2> A_BLT_TOP<3> A_BLT_TOP<2> A_IWL<255> A_IWL<254> A_IWL<253> A_IWL<252> A_IWL<251> A_IWL<250> A_IWL<249> A_IWL<248> A_IWL<247> A_IWL<246> A_IWL<245> A_IWL<244> A_IWL<243> A_IWL<242> A_IWL<241> A_IWL<240> A_IWL<239> A_IWL<238> A_IWL<237> A_IWL<236> A_IWL<235> A_IWL<234> A_IWL<233> A_IWL<232> A_IWL<231> A_IWL<230> A_IWL<229> A_IWL<228> A_IWL<227> A_IWL<226> A_IWL<225> A_IWL<224> A_IWL<223> A_IWL<222> A_IWL<221> A_IWL<220> A_IWL<219> A_IWL<218> A_IWL<217> A_IWL<216> A_IWL<215> A_IWL<214> A_IWL<213> A_IWL<212> A_IWL<211> A_IWL<210> A_IWL<209> A_IWL<208> A_IWL<207> A_IWL<206> A_IWL<205> A_IWL<204> A_IWL<203> A_IWL<202> A_IWL<201> A_IWL<200> A_IWL<199> A_IWL<198> A_IWL<197> A_IWL<196> A_IWL<195> A_IWL<194> A_IWL<193> A_IWL<192> A_IWL<191> A_IWL<190> A_IWL<189> A_IWL<188> A_IWL<187> A_IWL<186> A_IWL<185> A_IWL<184> A_IWL<183> A_IWL<182> A_IWL<181> A_IWL<180> A_IWL<179> A_IWL<178> A_IWL<177> A_IWL<176> A_IWL<175> A_IWL<174> A_IWL<173> A_IWL<172> A_IWL<171> A_IWL<170> A_IWL<169> A_IWL<168> A_IWL<167> A_IWL<166> A_IWL<165> A_IWL<164> A_IWL<163> A_IWL<162> A_IWL<161> A_IWL<160> A_IWL<159> A_IWL<158> A_IWL<157> A_IWL<156> A_IWL<155> A_IWL<154> A_IWL<153> A_IWL<152> A_IWL<151> A_IWL<150> A_IWL<149> A_IWL<148> A_IWL<147> A_IWL<146> A_IWL<145> A_IWL<144> A_IWL<143> A_IWL<142> A_IWL<141> A_IWL<140> A_IWL<139> A_IWL<138> A_IWL<137> A_IWL<136> A_IWL<135> A_IWL<134> A_IWL<133> A_IWL<132> A_IWL<131> A_IWL<130> A_IWL<129> A_IWL<128> A_IWL<127> A_IWL<126> A_IWL<125> A_IWL<124> A_IWL<123> A_IWL<122> A_IWL<121> A_IWL<120> A_IWL<119> A_IWL<118> A_IWL<117> A_IWL<116> A_IWL<115> A_IWL<114> A_IWL<113> A_IWL<112> A_IWL<111> A_IWL<110> A_IWL<109> A_IWL<108> A_IWL<107> A_IWL<106> A_IWL<105> A_IWL<104> A_IWL<103> A_IWL<102> A_IWL<101> A_IWL<100> A_IWL<99> A_IWL<98> A_IWL<97> A_IWL<96> A_IWL<95> A_IWL<94> A_IWL<93> A_IWL<92> A_IWL<91> A_IWL<90> A_IWL<89> A_IWL<88> A_IWL<87> A_IWL<86> A_IWL<85> A_IWL<84> A_IWL<83> A_IWL<82> A_IWL<81> A_IWL<80> A_IWL<79> A_IWL<78> A_IWL<77> A_IWL<76> A_IWL<75> A_IWL<74> A_IWL<73> A_IWL<72> A_IWL<71> A_IWL<70> A_IWL<69> A_IWL<68> A_IWL<67> A_IWL<66> A_IWL<65> A_IWL<64> A_IWL<63> A_IWL<62> A_IWL<61> A_IWL<60> A_IWL<59> A_IWL<58> A_IWL<57> A_IWL<56> A_IWL<55> A_IWL<54> A_IWL<53> A_IWL<52> A_IWL<51> A_IWL<50> A_IWL<49> A_IWL<48> A_IWL<47> A_IWL<46> A_IWL<45> A_IWL<44> A_IWL<43> A_IWL<42> A_IWL<41> A_IWL<40> A_IWL<39> A_IWL<38> A_IWL<37> A_IWL<36> A_IWL<35> A_IWL<34> A_IWL<33> A_IWL<32> A_IWL<31> A_IWL<30> A_IWL<29> A_IWL<28> A_IWL<27> A_IWL<26> A_IWL<25> A_IWL<24> A_IWL<23> A_IWL<22> A_IWL<21> A_IWL<20> A_IWL<19> A_IWL<18> A_IWL<17> A_IWL<16> A_IWL<15> A_IWL<14> A_IWL<13> A_IWL<12> A_IWL<11> A_IWL<10> A_IWL<9> A_IWL<8> A_IWL<7> A_IWL<6> A_IWL<5> A_IWL<4> A_IWL<3> A_IWL<2> A_IWL<1> A_IWL<0> A_IWL<511> A_IWL<510> A_IWL<509> A_IWL<508> A_IWL<507> A_IWL<506> A_IWL<505> A_IWL<504> A_IWL<503> A_IWL<502> A_IWL<501> A_IWL<500> A_IWL<499> A_IWL<498> A_IWL<497> A_IWL<496> A_IWL<495> A_IWL<494> A_IWL<493> A_IWL<492> A_IWL<491> A_IWL<490> A_IWL<489> A_IWL<488> A_IWL<487> A_IWL<486> A_IWL<485> A_IWL<484> A_IWL<483> A_IWL<482> A_IWL<481> A_IWL<480> A_IWL<479> A_IWL<478> A_IWL<477> A_IWL<476> A_IWL<475> A_IWL<474> A_IWL<473> A_IWL<472> A_IWL<471> A_IWL<470> A_IWL<469> A_IWL<468> A_IWL<467> A_IWL<466> A_IWL<465> A_IWL<464> A_IWL<463> A_IWL<462> A_IWL<461> A_IWL<460> A_IWL<459> A_IWL<458> A_IWL<457> A_IWL<456> A_IWL<455> A_IWL<454> A_IWL<453> A_IWL<452> A_IWL<451> A_IWL<450> A_IWL<449> A_IWL<448> A_IWL<447> A_IWL<446> A_IWL<445> A_IWL<444> A_IWL<443> A_IWL<442> A_IWL<441> A_IWL<440> A_IWL<439> A_IWL<438> A_IWL<437> A_IWL<436> A_IWL<435> A_IWL<434> A_IWL<433> A_IWL<432> A_IWL<431> A_IWL<430> A_IWL<429> A_IWL<428> A_IWL<427> A_IWL<426> A_IWL<425> A_IWL<424> A_IWL<423> A_IWL<422> A_IWL<421> A_IWL<420> A_IWL<419> A_IWL<418> A_IWL<417> A_IWL<416> A_IWL<415> A_IWL<414> A_IWL<413> A_IWL<412> A_IWL<411> A_IWL<410> A_IWL<409> A_IWL<408> A_IWL<407> A_IWL<406> A_IWL<405> A_IWL<404> A_IWL<403> A_IWL<402> A_IWL<401> A_IWL<400> A_IWL<399> A_IWL<398> A_IWL<397> A_IWL<396> A_IWL<395> A_IWL<394> A_IWL<393> A_IWL<392> A_IWL<391> A_IWL<390> A_IWL<389> A_IWL<388> A_IWL<387> A_IWL<386> A_IWL<385> A_IWL<384> A_IWL<383> A_IWL<382> A_IWL<381> A_IWL<380> A_IWL<379> A_IWL<378> A_IWL<377> A_IWL<376> A_IWL<375> A_IWL<374> A_IWL<373> A_IWL<372> A_IWL<371> A_IWL<370> A_IWL<369> A_IWL<368> A_IWL<367> A_IWL<366> A_IWL<365> A_IWL<364> A_IWL<363> A_IWL<362> A_IWL<361> A_IWL<360> A_IWL<359> A_IWL<358> A_IWL<357> A_IWL<356> A_IWL<355> A_IWL<354> A_IWL<353> A_IWL<352> A_IWL<351> A_IWL<350> A_IWL<349> A_IWL<348> A_IWL<347> A_IWL<346> A_IWL<345> A_IWL<344> A_IWL<343> A_IWL<342> A_IWL<341> A_IWL<340> A_IWL<339> A_IWL<338> A_IWL<337> A_IWL<336> A_IWL<335> A_IWL<334> A_IWL<333> A_IWL<332> A_IWL<331> A_IWL<330> A_IWL<329> A_IWL<328> A_IWL<327> A_IWL<326> A_IWL<325> A_IWL<324> A_IWL<323> A_IWL<322> A_IWL<321> A_IWL<320> A_IWL<319> A_IWL<318> A_IWL<317> A_IWL<316> A_IWL<315> A_IWL<314> A_IWL<313> A_IWL<312> A_IWL<311> A_IWL<310> A_IWL<309> A_IWL<308> A_IWL<307> A_IWL<306> A_IWL<305> A_IWL<304> A_IWL<303> A_IWL<302> A_IWL<301> A_IWL<300> A_IWL<299> A_IWL<298> A_IWL<297> A_IWL<296> A_IWL<295> A_IWL<294> A_IWL<293> A_IWL<292> A_IWL<291> A_IWL<290> A_IWL<289> A_IWL<288> A_IWL<287> A_IWL<286> A_IWL<285> A_IWL<284> A_IWL<283> A_IWL<282> A_IWL<281> A_IWL<280> A_IWL<279> A_IWL<278> A_IWL<277> A_IWL<276> A_IWL<275> A_IWL<274> A_IWL<273> A_IWL<272> A_IWL<271> A_IWL<270> A_IWL<269> A_IWL<268> A_IWL<267> A_IWL<266> A_IWL<265> A_IWL<264> A_IWL<263> A_IWL<262> A_IWL<261> A_IWL<260> A_IWL<259> A_IWL<258> A_IWL<257> A_IWL<256> VDD_CORE VSS / RM_IHPSG13_1024x32_c2_1P_COLUMN_pcell_0 +XCOL<0> A_BLC<1> A_BLC<0> A_BLC_TOP<1> A_BLC_TOP<0> A_BLT<1> A_BLT<0> A_BLT_TOP<1> A_BLT_TOP<0> A_WL<255> A_WL<254> A_WL<253> A_WL<252> A_WL<251> A_WL<250> A_WL<249> A_WL<248> A_WL<247> A_WL<246> A_WL<245> A_WL<244> A_WL<243> A_WL<242> A_WL<241> A_WL<240> A_WL<239> A_WL<238> A_WL<237> A_WL<236> A_WL<235> A_WL<234> A_WL<233> A_WL<232> A_WL<231> A_WL<230> A_WL<229> A_WL<228> A_WL<227> A_WL<226> A_WL<225> A_WL<224> A_WL<223> A_WL<222> A_WL<221> A_WL<220> A_WL<219> A_WL<218> A_WL<217> A_WL<216> A_WL<215> A_WL<214> A_WL<213> A_WL<212> A_WL<211> A_WL<210> A_WL<209> A_WL<208> A_WL<207> A_WL<206> A_WL<205> A_WL<204> A_WL<203> A_WL<202> A_WL<201> A_WL<200> A_WL<199> A_WL<198> A_WL<197> A_WL<196> A_WL<195> A_WL<194> A_WL<193> A_WL<192> A_WL<191> A_WL<190> A_WL<189> A_WL<188> A_WL<187> A_WL<186> A_WL<185> A_WL<184> A_WL<183> A_WL<182> A_WL<181> A_WL<180> A_WL<179> A_WL<178> A_WL<177> A_WL<176> A_WL<175> A_WL<174> A_WL<173> A_WL<172> A_WL<171> A_WL<170> A_WL<169> A_WL<168> A_WL<167> A_WL<166> A_WL<165> A_WL<164> A_WL<163> A_WL<162> A_WL<161> A_WL<160> A_WL<159> A_WL<158> A_WL<157> A_WL<156> A_WL<155> A_WL<154> A_WL<153> A_WL<152> A_WL<151> A_WL<150> A_WL<149> A_WL<148> A_WL<147> A_WL<146> A_WL<145> A_WL<144> A_WL<143> A_WL<142> A_WL<141> A_WL<140> A_WL<139> A_WL<138> A_WL<137> A_WL<136> A_WL<135> A_WL<134> A_WL<133> A_WL<132> A_WL<131> A_WL<130> A_WL<129> A_WL<128> A_WL<127> A_WL<126> A_WL<125> A_WL<124> A_WL<123> A_WL<122> A_WL<121> A_WL<120> A_WL<119> A_WL<118> A_WL<117> A_WL<116> A_WL<115> A_WL<114> A_WL<113> A_WL<112> A_WL<111> A_WL<110> A_WL<109> A_WL<108> A_WL<107> A_WL<106> A_WL<105> A_WL<104> A_WL<103> A_WL<102> A_WL<101> A_WL<100> A_WL<99> A_WL<98> A_WL<97> A_WL<96> A_WL<95> A_WL<94> A_WL<93> A_WL<92> A_WL<91> A_WL<90> A_WL<89> A_WL<88> A_WL<87> A_WL<86> A_WL<85> A_WL<84> A_WL<83> A_WL<82> A_WL<81> A_WL<80> A_WL<79> A_WL<78> A_WL<77> A_WL<76> A_WL<75> A_WL<74> A_WL<73> A_WL<72> A_WL<71> A_WL<70> A_WL<69> A_WL<68> A_WL<67> A_WL<66> A_WL<65> A_WL<64> A_WL<63> A_WL<62> A_WL<61> A_WL<60> A_WL<59> A_WL<58> A_WL<57> A_WL<56> A_WL<55> A_WL<54> A_WL<53> A_WL<52> A_WL<51> A_WL<50> A_WL<49> A_WL<48> A_WL<47> A_WL<46> A_WL<45> A_WL<44> A_WL<43> A_WL<42> A_WL<41> A_WL<40> A_WL<39> A_WL<38> A_WL<37> A_WL<36> A_WL<35> A_WL<34> A_WL<33> A_WL<32> A_WL<31> A_WL<30> A_WL<29> A_WL<28> A_WL<27> A_WL<26> A_WL<25> A_WL<24> A_WL<23> A_WL<22> A_WL<21> A_WL<20> A_WL<19> A_WL<18> A_WL<17> A_WL<16> A_WL<15> A_WL<14> A_WL<13> A_WL<12> A_WL<11> A_WL<10> A_WL<9> A_WL<8> A_WL<7> A_WL<6> A_WL<5> A_WL<4> A_WL<3> A_WL<2> A_WL<1> A_WL<0> A_IWL<255> A_IWL<254> A_IWL<253> A_IWL<252> A_IWL<251> A_IWL<250> A_IWL<249> A_IWL<248> A_IWL<247> A_IWL<246> A_IWL<245> A_IWL<244> A_IWL<243> A_IWL<242> A_IWL<241> A_IWL<240> A_IWL<239> A_IWL<238> A_IWL<237> A_IWL<236> A_IWL<235> A_IWL<234> A_IWL<233> A_IWL<232> A_IWL<231> A_IWL<230> A_IWL<229> A_IWL<228> A_IWL<227> A_IWL<226> A_IWL<225> A_IWL<224> A_IWL<223> A_IWL<222> A_IWL<221> A_IWL<220> A_IWL<219> A_IWL<218> A_IWL<217> A_IWL<216> A_IWL<215> A_IWL<214> A_IWL<213> A_IWL<212> A_IWL<211> A_IWL<210> A_IWL<209> A_IWL<208> A_IWL<207> A_IWL<206> A_IWL<205> A_IWL<204> A_IWL<203> A_IWL<202> A_IWL<201> A_IWL<200> A_IWL<199> A_IWL<198> A_IWL<197> A_IWL<196> A_IWL<195> A_IWL<194> A_IWL<193> A_IWL<192> A_IWL<191> A_IWL<190> A_IWL<189> A_IWL<188> A_IWL<187> A_IWL<186> A_IWL<185> A_IWL<184> A_IWL<183> A_IWL<182> A_IWL<181> A_IWL<180> A_IWL<179> A_IWL<178> A_IWL<177> A_IWL<176> A_IWL<175> A_IWL<174> A_IWL<173> A_IWL<172> A_IWL<171> A_IWL<170> A_IWL<169> A_IWL<168> A_IWL<167> A_IWL<166> A_IWL<165> A_IWL<164> A_IWL<163> A_IWL<162> A_IWL<161> A_IWL<160> A_IWL<159> A_IWL<158> A_IWL<157> A_IWL<156> A_IWL<155> A_IWL<154> A_IWL<153> A_IWL<152> A_IWL<151> A_IWL<150> A_IWL<149> A_IWL<148> A_IWL<147> A_IWL<146> A_IWL<145> A_IWL<144> A_IWL<143> A_IWL<142> A_IWL<141> A_IWL<140> A_IWL<139> A_IWL<138> A_IWL<137> A_IWL<136> A_IWL<135> A_IWL<134> A_IWL<133> A_IWL<132> A_IWL<131> A_IWL<130> A_IWL<129> A_IWL<128> A_IWL<127> A_IWL<126> A_IWL<125> A_IWL<124> A_IWL<123> A_IWL<122> A_IWL<121> A_IWL<120> A_IWL<119> A_IWL<118> A_IWL<117> A_IWL<116> A_IWL<115> A_IWL<114> A_IWL<113> A_IWL<112> A_IWL<111> A_IWL<110> A_IWL<109> A_IWL<108> A_IWL<107> A_IWL<106> A_IWL<105> A_IWL<104> A_IWL<103> A_IWL<102> A_IWL<101> A_IWL<100> A_IWL<99> A_IWL<98> A_IWL<97> A_IWL<96> A_IWL<95> A_IWL<94> A_IWL<93> A_IWL<92> A_IWL<91> A_IWL<90> A_IWL<89> A_IWL<88> A_IWL<87> A_IWL<86> A_IWL<85> A_IWL<84> A_IWL<83> A_IWL<82> A_IWL<81> A_IWL<80> A_IWL<79> A_IWL<78> A_IWL<77> A_IWL<76> A_IWL<75> A_IWL<74> A_IWL<73> A_IWL<72> A_IWL<71> A_IWL<70> A_IWL<69> A_IWL<68> A_IWL<67> A_IWL<66> A_IWL<65> A_IWL<64> A_IWL<63> A_IWL<62> A_IWL<61> A_IWL<60> A_IWL<59> A_IWL<58> A_IWL<57> A_IWL<56> A_IWL<55> A_IWL<54> A_IWL<53> A_IWL<52> A_IWL<51> A_IWL<50> A_IWL<49> A_IWL<48> A_IWL<47> A_IWL<46> A_IWL<45> A_IWL<44> A_IWL<43> A_IWL<42> A_IWL<41> A_IWL<40> A_IWL<39> A_IWL<38> A_IWL<37> A_IWL<36> A_IWL<35> A_IWL<34> A_IWL<33> A_IWL<32> A_IWL<31> A_IWL<30> A_IWL<29> A_IWL<28> A_IWL<27> A_IWL<26> A_IWL<25> A_IWL<24> A_IWL<23> A_IWL<22> A_IWL<21> A_IWL<20> A_IWL<19> A_IWL<18> A_IWL<17> A_IWL<16> A_IWL<15> A_IWL<14> A_IWL<13> A_IWL<12> A_IWL<11> A_IWL<10> A_IWL<9> A_IWL<8> A_IWL<7> A_IWL<6> A_IWL<5> A_IWL<4> A_IWL<3> A_IWL<2> A_IWL<1> A_IWL<0> VDD_CORE VSS / RM_IHPSG13_1024x32_c2_1P_COLUMN_pcell_0 +.ENDS + + + + +.SUBCKT RM_IHPSG13_1024x32_c2_1P_DLY_pcell_2 A Z VDD VSS + XIDL<2> D<7> Z VDD VSS / RSC_IHPSG13_CDLYX1 + XIDL<1> D<6> D<7> VDD VSS / RSC_IHPSG13_CDLYX1 + XIDM<6> D<5> D<6> VDD VSS / RSC_IHPSG13_CDLYX1_DUMMY + XIDM<5> D<4> D<5> VDD VSS / RSC_IHPSG13_CDLYX1_DUMMY + XIDM<4> D<3> D<4> VDD VSS / RSC_IHPSG13_CDLYX1_DUMMY + XIDM<3> D<2> D<3> VDD VSS / RSC_IHPSG13_CDLYX1_DUMMY + XIDM<2> D<1> D<2> VDD VSS / RSC_IHPSG13_CDLYX1_DUMMY + XIDM<1> A D<1> VDD VSS / RSC_IHPSG13_CDLYX1_DUMMY +.ENDS + + +.SUBCKT RM_IHPSG13_1024x32_c2_1P_DLY_pcell_3 A Z VDD VSS + XIDL<4> D<7> Z VDD VSS / RSC_IHPSG13_CDLYX1 + XIDL<3> D<6> D<7> VDD VSS / RSC_IHPSG13_CDLYX1 + XIDL<2> D<5> D<6> VDD VSS / RSC_IHPSG13_CDLYX1 + XIDL<1> D<4> D<5> VDD VSS / RSC_IHPSG13_CDLYX1 + XIDM<4> D<3> D<4> VDD VSS / RSC_IHPSG13_CDLYX1_DUMMY + XIDM<3> D<2> D<3> VDD VSS / RSC_IHPSG13_CDLYX1_DUMMY + XIDM<2> D<1> D<2> VDD VSS / RSC_IHPSG13_CDLYX1_DUMMY + XIDM<1> A D<1> VDD VSS / RSC_IHPSG13_CDLYX1_DUMMY +.ENDS + + + +.SUBCKT RM_IHPSG13_1P_1024x32_c2_bm_bist A_ADDR<9> A_ADDR<8> A_ADDR<7> A_ADDR<6> A_ADDR<5> A_ADDR<4> A_ADDR<3> A_ADDR<2> A_ADDR<1> A_ADDR<0> A_BIST_ADDR<9> A_BIST_ADDR<8> A_BIST_ADDR<7> A_BIST_ADDR<6> A_BIST_ADDR<5> A_BIST_ADDR<4> A_BIST_ADDR<3> A_BIST_ADDR<2> A_BIST_ADDR<1> A_BIST_ADDR<0> A_BIST_BM<31> A_BIST_BM<30> A_BIST_BM<29> A_BIST_BM<28> A_BIST_BM<27> A_BIST_BM<26> A_BIST_BM<25> A_BIST_BM<24> A_BIST_BM<23> A_BIST_BM<22> A_BIST_BM<21> A_BIST_BM<20> A_BIST_BM<19> A_BIST_BM<18> A_BIST_BM<17> A_BIST_BM<16> A_BIST_BM<15> A_BIST_BM<14> A_BIST_BM<13> A_BIST_BM<12> A_BIST_BM<11> A_BIST_BM<10> A_BIST_BM<9> A_BIST_BM<8> A_BIST_BM<7> A_BIST_BM<6> A_BIST_BM<5> A_BIST_BM<4> A_BIST_BM<3> A_BIST_BM<2> A_BIST_BM<1> A_BIST_BM<0> A_BIST_CLK A_BIST_DIN<31> A_BIST_DIN<30> A_BIST_DIN<29> A_BIST_DIN<28> A_BIST_DIN<27> A_BIST_DIN<26> A_BIST_DIN<25> A_BIST_DIN<24> A_BIST_DIN<23> A_BIST_DIN<22> A_BIST_DIN<21> A_BIST_DIN<20> A_BIST_DIN<19> A_BIST_DIN<18> A_BIST_DIN<17> A_BIST_DIN<16> A_BIST_DIN<15> A_BIST_DIN<14> A_BIST_DIN<13> A_BIST_DIN<12> A_BIST_DIN<11> A_BIST_DIN<10> A_BIST_DIN<9> A_BIST_DIN<8> A_BIST_DIN<7> A_BIST_DIN<6> A_BIST_DIN<5> A_BIST_DIN<4> A_BIST_DIN<3> A_BIST_DIN<2> A_BIST_DIN<1> A_BIST_DIN<0> A_BIST_EN A_BIST_MEN A_BIST_REN A_BIST_WEN A_BM<31> A_BM<30> A_BM<29> A_BM<28> A_BM<27> A_BM<26> A_BM<25> A_BM<24> A_BM<23> A_BM<22> A_BM<21> A_BM<20> A_BM<19> A_BM<18> A_BM<17> A_BM<16> A_BM<15> A_BM<14> A_BM<13> A_BM<12> A_BM<11> A_BM<10> A_BM<9> A_BM<8> A_BM<7> A_BM<6> A_BM<5> A_BM<4> A_BM<3> A_BM<2> A_BM<1> A_BM<0> A_CLK A_DIN<31> A_DIN<30> A_DIN<29> A_DIN<28> A_DIN<27> A_DIN<26> A_DIN<25> A_DIN<24> A_DIN<23> A_DIN<22> A_DIN<21> A_DIN<20> A_DIN<19> A_DIN<18> A_DIN<17> A_DIN<16> A_DIN<15> A_DIN<14> A_DIN<13> A_DIN<12> A_DIN<11> A_DIN<10> A_DIN<9> A_DIN<8> A_DIN<7> A_DIN<6> A_DIN<5> A_DIN<4> A_DIN<3> A_DIN<2> A_DIN<1> A_DIN<0> A_DLY A_DOUT<31> A_DOUT<30> A_DOUT<29> A_DOUT<28> A_DOUT<27> A_DOUT<26> A_DOUT<25> A_DOUT<24> A_DOUT<23> A_DOUT<22> A_DOUT<21> A_DOUT<20> A_DOUT<19> A_DOUT<18> A_DOUT<17> A_DOUT<16> A_DOUT<15> A_DOUT<14> A_DOUT<13> A_DOUT<12> A_DOUT<11> A_DOUT<10> A_DOUT<9> A_DOUT<8> A_DOUT<7> A_DOUT<6> A_DOUT<5> A_DOUT<4> A_DOUT<3> A_DOUT<2> A_DOUT<1> A_DOUT<0> A_MEN A_REN A_WEN VDD! VDDARRAY! VSS! + + +XRAM<1> a_blc_r<63> a_blc_r<62> a_blc_r<61> a_blc_r<60> a_blc_r<59> a_blc_r<58> a_blc_r<57> a_blc_r<56> a_blc_r<55> a_blc_r<54> a_blc_r<53> a_blc_r<52> a_blc_r<51> a_blc_r<50> a_blc_r<49> a_blc_r<48> a_blc_r<47> a_blc_r<46> a_blc_r<45> a_blc_r<44> a_blc_r<43> a_blc_r<42> a_blc_r<41> a_blc_r<40> a_blc_r<39> a_blc_r<38> a_blc_r<37> a_blc_r<36> a_blc_r<35> a_blc_r<34> a_blc_r<33> a_blc_r<32> a_blc_r<31> a_blc_r<30> a_blc_r<29> a_blc_r<28> a_blc_r<27> a_blc_r<26> a_blc_r<25> a_blc_r<24> a_blc_r<23> a_blc_r<22> a_blc_r<21> a_blc_r<20> a_blc_r<19> a_blc_r<18> a_blc_r<17> a_blc_r<16> a_blc_r<15> a_blc_r<14> a_blc_r<13> a_blc_r<12> a_blc_r<11> a_blc_r<10> a_blc_r<9> a_blc_r<8> a_blc_r<7> a_blc_r<6> a_blc_r<5> a_blc_r<4> a_blc_r<3> a_blc_r<2> a_blc_r<1> a_blc_r<0> a_blt_r<63> a_blt_r<62> a_blt_r<61> a_blt_r<60> a_blt_r<59> a_blt_r<58> a_blt_r<57> a_blt_r<56> a_blt_r<55> a_blt_r<54> a_blt_r<53> a_blt_r<52> a_blt_r<51> a_blt_r<50> a_blt_r<49> a_blt_r<48> a_blt_r<47> a_blt_r<46> a_blt_r<45> a_blt_r<44> a_blt_r<43> a_blt_r<42> a_blt_r<41> a_blt_r<40> a_blt_r<39> a_blt_r<38> a_blt_r<37> a_blt_r<36> a_blt_r<35> a_blt_r<34> a_blt_r<33> a_blt_r<32> a_blt_r<31> a_blt_r<30> a_blt_r<29> a_blt_r<28> a_blt_r<27> a_blt_r<26> a_blt_r<25> a_blt_r<24> a_blt_r<23> a_blt_r<22> a_blt_r<21> a_blt_r<20> a_blt_r<19> a_blt_r<18> a_blt_r<17> a_blt_r<16> a_blt_r<15> a_blt_r<14> a_blt_r<13> a_blt_r<12> a_blt_r<11> a_blt_r<10> a_blt_r<9> a_blt_r<8> a_blt_r<7> a_blt_r<6> a_blt_r<5> a_blt_r<4> a_blt_r<3> a_blt_r<2> a_blt_r<1> a_blt_r<0> a_wl_r<255> a_wl_r<254> a_wl_r<253> a_wl_r<252> a_wl_r<251> a_wl_r<250> a_wl_r<249> a_wl_r<248> a_wl_r<247> a_wl_r<246> a_wl_r<245> a_wl_r<244> a_wl_r<243> a_wl_r<242> a_wl_r<241> a_wl_r<240> a_wl_r<239> a_wl_r<238> a_wl_r<237> a_wl_r<236> a_wl_r<235> a_wl_r<234> a_wl_r<233> a_wl_r<232> a_wl_r<231> a_wl_r<230> a_wl_r<229> a_wl_r<228> a_wl_r<227> a_wl_r<226> a_wl_r<225> a_wl_r<224> a_wl_r<223> a_wl_r<222> a_wl_r<221> a_wl_r<220> a_wl_r<219> a_wl_r<218> a_wl_r<217> a_wl_r<216> a_wl_r<215> a_wl_r<214> a_wl_r<213> a_wl_r<212> a_wl_r<211> a_wl_r<210> a_wl_r<209> a_wl_r<208> a_wl_r<207> a_wl_r<206> a_wl_r<205> a_wl_r<204> a_wl_r<203> a_wl_r<202> a_wl_r<201> a_wl_r<200> a_wl_r<199> a_wl_r<198> a_wl_r<197> a_wl_r<196> a_wl_r<195> a_wl_r<194> a_wl_r<193> a_wl_r<192> a_wl_r<191> a_wl_r<190> a_wl_r<189> a_wl_r<188> a_wl_r<187> a_wl_r<186> a_wl_r<185> a_wl_r<184> a_wl_r<183> a_wl_r<182> a_wl_r<181> a_wl_r<180> a_wl_r<179> a_wl_r<178> a_wl_r<177> a_wl_r<176> a_wl_r<175> a_wl_r<174> a_wl_r<173> a_wl_r<172> a_wl_r<171> a_wl_r<170> a_wl_r<169> a_wl_r<168> a_wl_r<167> a_wl_r<166> a_wl_r<165> a_wl_r<164> a_wl_r<163> a_wl_r<162> a_wl_r<161> a_wl_r<160> a_wl_r<159> a_wl_r<158> a_wl_r<157> a_wl_r<156> a_wl_r<155> a_wl_r<154> a_wl_r<153> a_wl_r<152> a_wl_r<151> a_wl_r<150> a_wl_r<149> a_wl_r<148> a_wl_r<147> a_wl_r<146> a_wl_r<145> a_wl_r<144> a_wl_r<143> a_wl_r<142> a_wl_r<141> a_wl_r<140> a_wl_r<139> a_wl_r<138> a_wl_r<137> a_wl_r<136> a_wl_r<135> a_wl_r<134> a_wl_r<133> a_wl_r<132> a_wl_r<131> a_wl_r<130> a_wl_r<129> a_wl_r<128> a_wl_r<127> a_wl_r<126> a_wl_r<125> a_wl_r<124> a_wl_r<123> a_wl_r<122> a_wl_r<121> a_wl_r<120> a_wl_r<119> a_wl_r<118> a_wl_r<117> a_wl_r<116> a_wl_r<115> a_wl_r<114> a_wl_r<113> a_wl_r<112> a_wl_r<111> a_wl_r<110> a_wl_r<109> a_wl_r<108> a_wl_r<107> a_wl_r<106> a_wl_r<105> a_wl_r<104> a_wl_r<103> a_wl_r<102> a_wl_r<101> a_wl_r<100> a_wl_r<99> a_wl_r<98> a_wl_r<97> a_wl_r<96> a_wl_r<95> a_wl_r<94> a_wl_r<93> a_wl_r<92> a_wl_r<91> a_wl_r<90> a_wl_r<89> a_wl_r<88> a_wl_r<87> a_wl_r<86> a_wl_r<85> a_wl_r<84> a_wl_r<83> a_wl_r<82> a_wl_r<81> a_wl_r<80> a_wl_r<79> a_wl_r<78> a_wl_r<77> a_wl_r<76> a_wl_r<75> a_wl_r<74> a_wl_r<73> a_wl_r<72> a_wl_r<71> a_wl_r<70> a_wl_r<69> a_wl_r<68> a_wl_r<67> a_wl_r<66> a_wl_r<65> a_wl_r<64> a_wl_r<63> a_wl_r<62> a_wl_r<61> a_wl_r<60> a_wl_r<59> a_wl_r<58> a_wl_r<57> a_wl_r<56> a_wl_r<55> a_wl_r<54> a_wl_r<53> a_wl_r<52> a_wl_r<51> a_wl_r<50> a_wl_r<49> a_wl_r<48> a_wl_r<47> a_wl_r<46> a_wl_r<45> a_wl_r<44> a_wl_r<43> a_wl_r<42> a_wl_r<41> a_wl_r<40> a_wl_r<39> a_wl_r<38> a_wl_r<37> a_wl_r<36> a_wl_r<35> a_wl_r<34> a_wl_r<33> a_wl_r<32> a_wl_r<31> a_wl_r<30> a_wl_r<29> a_wl_r<28> a_wl_r<27> a_wl_r<26> a_wl_r<25> a_wl_r<24> a_wl_r<23> a_wl_r<22> a_wl_r<21> a_wl_r<20> a_wl_r<19> a_wl_r<18> a_wl_r<17> a_wl_r<16> a_wl_r<15> a_wl_r<14> a_wl_r<13> a_wl_r<12> a_wl_r<11> a_wl_r<10> a_wl_r<9> a_wl_r<8> a_wl_r<7> a_wl_r<6> a_wl_r<5> a_wl_r<4> a_wl_r<3> a_wl_r<2> a_wl_r<1> a_wl_r<0> VDDARRAY! VSS! / RM_IHPSG13_1024x32_c2_1P_MATRIX_pcell_1 +XRAM<0> a_blc_l<63> a_blc_l<62> a_blc_l<61> a_blc_l<60> a_blc_l<59> a_blc_l<58> a_blc_l<57> a_blc_l<56> a_blc_l<55> a_blc_l<54> a_blc_l<53> a_blc_l<52> a_blc_l<51> a_blc_l<50> a_blc_l<49> a_blc_l<48> a_blc_l<47> a_blc_l<46> a_blc_l<45> a_blc_l<44> a_blc_l<43> a_blc_l<42> a_blc_l<41> a_blc_l<40> a_blc_l<39> a_blc_l<38> a_blc_l<37> a_blc_l<36> a_blc_l<35> a_blc_l<34> a_blc_l<33> a_blc_l<32> a_blc_l<31> a_blc_l<30> a_blc_l<29> a_blc_l<28> a_blc_l<27> a_blc_l<26> a_blc_l<25> a_blc_l<24> a_blc_l<23> a_blc_l<22> a_blc_l<21> a_blc_l<20> a_blc_l<19> a_blc_l<18> a_blc_l<17> a_blc_l<16> a_blc_l<15> a_blc_l<14> a_blc_l<13> a_blc_l<12> a_blc_l<11> a_blc_l<10> a_blc_l<9> a_blc_l<8> a_blc_l<7> a_blc_l<6> a_blc_l<5> a_blc_l<4> a_blc_l<3> a_blc_l<2> a_blc_l<1> a_blc_l<0> a_blt_l<63> a_blt_l<62> a_blt_l<61> a_blt_l<60> a_blt_l<59> a_blt_l<58> a_blt_l<57> a_blt_l<56> a_blt_l<55> a_blt_l<54> a_blt_l<53> a_blt_l<52> a_blt_l<51> a_blt_l<50> a_blt_l<49> a_blt_l<48> a_blt_l<47> a_blt_l<46> a_blt_l<45> a_blt_l<44> a_blt_l<43> a_blt_l<42> a_blt_l<41> a_blt_l<40> a_blt_l<39> a_blt_l<38> a_blt_l<37> a_blt_l<36> a_blt_l<35> a_blt_l<34> a_blt_l<33> a_blt_l<32> a_blt_l<31> a_blt_l<30> a_blt_l<29> a_blt_l<28> a_blt_l<27> a_blt_l<26> a_blt_l<25> a_blt_l<24> a_blt_l<23> a_blt_l<22> a_blt_l<21> a_blt_l<20> a_blt_l<19> a_blt_l<18> a_blt_l<17> a_blt_l<16> a_blt_l<15> a_blt_l<14> a_blt_l<13> a_blt_l<12> a_blt_l<11> a_blt_l<10> a_blt_l<9> a_blt_l<8> a_blt_l<7> a_blt_l<6> a_blt_l<5> a_blt_l<4> a_blt_l<3> a_blt_l<2> a_blt_l<1> a_blt_l<0> a_wl_l<255> a_wl_l<254> a_wl_l<253> a_wl_l<252> a_wl_l<251> a_wl_l<250> a_wl_l<249> a_wl_l<248> a_wl_l<247> a_wl_l<246> a_wl_l<245> a_wl_l<244> a_wl_l<243> a_wl_l<242> a_wl_l<241> a_wl_l<240> a_wl_l<239> a_wl_l<238> a_wl_l<237> a_wl_l<236> a_wl_l<235> a_wl_l<234> a_wl_l<233> a_wl_l<232> a_wl_l<231> a_wl_l<230> a_wl_l<229> a_wl_l<228> a_wl_l<227> a_wl_l<226> a_wl_l<225> a_wl_l<224> a_wl_l<223> a_wl_l<222> a_wl_l<221> a_wl_l<220> a_wl_l<219> a_wl_l<218> a_wl_l<217> a_wl_l<216> a_wl_l<215> a_wl_l<214> a_wl_l<213> a_wl_l<212> a_wl_l<211> a_wl_l<210> a_wl_l<209> a_wl_l<208> a_wl_l<207> a_wl_l<206> a_wl_l<205> a_wl_l<204> a_wl_l<203> a_wl_l<202> a_wl_l<201> a_wl_l<200> a_wl_l<199> a_wl_l<198> a_wl_l<197> a_wl_l<196> a_wl_l<195> a_wl_l<194> a_wl_l<193> a_wl_l<192> a_wl_l<191> a_wl_l<190> a_wl_l<189> a_wl_l<188> a_wl_l<187> a_wl_l<186> a_wl_l<185> a_wl_l<184> a_wl_l<183> a_wl_l<182> a_wl_l<181> a_wl_l<180> a_wl_l<179> a_wl_l<178> a_wl_l<177> a_wl_l<176> a_wl_l<175> a_wl_l<174> a_wl_l<173> a_wl_l<172> a_wl_l<171> a_wl_l<170> a_wl_l<169> a_wl_l<168> a_wl_l<167> a_wl_l<166> a_wl_l<165> a_wl_l<164> a_wl_l<163> a_wl_l<162> a_wl_l<161> a_wl_l<160> a_wl_l<159> a_wl_l<158> a_wl_l<157> a_wl_l<156> a_wl_l<155> a_wl_l<154> a_wl_l<153> a_wl_l<152> a_wl_l<151> a_wl_l<150> a_wl_l<149> a_wl_l<148> a_wl_l<147> a_wl_l<146> a_wl_l<145> a_wl_l<144> a_wl_l<143> a_wl_l<142> a_wl_l<141> a_wl_l<140> a_wl_l<139> a_wl_l<138> a_wl_l<137> a_wl_l<136> a_wl_l<135> a_wl_l<134> a_wl_l<133> a_wl_l<132> a_wl_l<131> a_wl_l<130> a_wl_l<129> a_wl_l<128> a_wl_l<127> a_wl_l<126> a_wl_l<125> a_wl_l<124> a_wl_l<123> a_wl_l<122> a_wl_l<121> a_wl_l<120> a_wl_l<119> a_wl_l<118> a_wl_l<117> a_wl_l<116> a_wl_l<115> a_wl_l<114> a_wl_l<113> a_wl_l<112> a_wl_l<111> a_wl_l<110> a_wl_l<109> a_wl_l<108> a_wl_l<107> a_wl_l<106> a_wl_l<105> a_wl_l<104> a_wl_l<103> a_wl_l<102> a_wl_l<101> a_wl_l<100> a_wl_l<99> a_wl_l<98> a_wl_l<97> a_wl_l<96> a_wl_l<95> a_wl_l<94> a_wl_l<93> a_wl_l<92> a_wl_l<91> a_wl_l<90> a_wl_l<89> a_wl_l<88> a_wl_l<87> a_wl_l<86> a_wl_l<85> a_wl_l<84> a_wl_l<83> a_wl_l<82> a_wl_l<81> a_wl_l<80> a_wl_l<79> a_wl_l<78> a_wl_l<77> a_wl_l<76> a_wl_l<75> a_wl_l<74> a_wl_l<73> a_wl_l<72> a_wl_l<71> a_wl_l<70> a_wl_l<69> a_wl_l<68> a_wl_l<67> a_wl_l<66> a_wl_l<65> a_wl_l<64> a_wl_l<63> a_wl_l<62> a_wl_l<61> a_wl_l<60> a_wl_l<59> a_wl_l<58> a_wl_l<57> a_wl_l<56> a_wl_l<55> a_wl_l<54> a_wl_l<53> a_wl_l<52> a_wl_l<51> a_wl_l<50> a_wl_l<49> a_wl_l<48> a_wl_l<47> a_wl_l<46> a_wl_l<45> a_wl_l<44> a_wl_l<43> a_wl_l<42> a_wl_l<41> a_wl_l<40> a_wl_l<39> a_wl_l<38> a_wl_l<37> a_wl_l<36> a_wl_l<35> a_wl_l<34> a_wl_l<33> a_wl_l<32> a_wl_l<31> a_wl_l<30> a_wl_l<29> a_wl_l<28> a_wl_l<27> a_wl_l<26> a_wl_l<25> a_wl_l<24> a_wl_l<23> a_wl_l<22> a_wl_l<21> a_wl_l<20> a_wl_l<19> a_wl_l<18> a_wl_l<17> a_wl_l<16> a_wl_l<15> a_wl_l<14> a_wl_l<13> a_wl_l<12> a_wl_l<11> a_wl_l<10> a_wl_l<9> a_wl_l<8> a_wl_l<7> a_wl_l<6> a_wl_l<5> a_wl_l<4> a_wl_l<3> a_wl_l<2> a_wl_l<1> a_wl_l<0> VDDARRAY! VSS! / RM_IHPSG13_1024x32_c2_1P_MATRIX_pcell_1 + + +XA_COLDRV<1> a_addr_col<1> a_addr_col<0> a_addr_col_r<1> a_addr_col_r<0> a_addr_dec<7> a_addr_dec<6> a_addr_dec<5> a_addr_dec<4> a_addr_dec<3> a_addr_dec<2> a_addr_dec<1> a_addr_dec<0> a_addr_dec_r<7> a_addr_dec_r<6> a_addr_dec_r<5> a_addr_dec_r<4> a_addr_dec_r<3> a_addr_dec_r<2> a_addr_dec_r<1> a_addr_dec_r<0> a_dclk a_dclk_p_r<0> a_rclk a_rclk_p_r<0> a_wclk a_wclk_p_r<0> VDD! VSS! / RM_IHPSG13_1024x32_c2_1P_COLDRV13X4 +XA_COLDRV<0> a_addr_col<1> a_addr_col<0> a_addr_col_l<1> a_addr_col_l<0> a_addr_dec<7> a_addr_dec<6> a_addr_dec<5> a_addr_dec<4> a_addr_dec<3> a_addr_dec<2> a_addr_dec<1> a_addr_dec<0> a_addr_dec_l<7> a_addr_dec_l<6> a_addr_dec_l<5> a_addr_dec_l<4> a_addr_dec_l<3> a_addr_dec_l<2> a_addr_dec_l<1> a_addr_dec_l<0> a_dclk a_dclk_p_l<0> a_rclk a_rclk_p_l<0> a_wclk a_wclk_p_l<0> VDD! VSS! / RM_IHPSG13_1024x32_c2_1P_COLDRV13X4 + + +XA_WLDRV<31> a_wi<255> a_wi<254> a_wi<253> a_wi<252> a_wi<251> a_wi<250> a_wi<249> a_wi<248> a_wi<247> a_wi<246> a_wi<245> a_wi<244> a_wi<243> a_wi<242> a_wi<241> a_wi<240> a_wl_r<255> a_wl_r<254> a_wl_r<253> a_wl_r<252> a_wl_r<251> a_wl_r<250> a_wl_r<249> a_wl_r<248> a_wl_r<247> a_wl_r<246> a_wl_r<245> a_wl_r<244> a_wl_r<243> a_wl_r<242> a_wl_r<241> a_wl_r<240> VDD! VSS! / RM_IHPSG13_1024x32_c2_1P_WLDRV16X4 +XA_WLDRV<30> a_wi<239> a_wi<238> a_wi<237> a_wi<236> a_wi<235> a_wi<234> a_wi<233> a_wi<232> a_wi<231> a_wi<230> a_wi<229> a_wi<228> a_wi<227> a_wi<226> a_wi<225> a_wi<224> a_wl_r<239> a_wl_r<238> a_wl_r<237> a_wl_r<236> a_wl_r<235> a_wl_r<234> a_wl_r<233> a_wl_r<232> a_wl_r<231> a_wl_r<230> a_wl_r<229> a_wl_r<228> a_wl_r<227> a_wl_r<226> a_wl_r<225> a_wl_r<224> VDD! VSS! / RM_IHPSG13_1024x32_c2_1P_WLDRV16X4 +XA_WLDRV<29> a_wi<223> a_wi<222> a_wi<221> a_wi<220> a_wi<219> a_wi<218> a_wi<217> a_wi<216> a_wi<215> a_wi<214> a_wi<213> a_wi<212> a_wi<211> a_wi<210> a_wi<209> a_wi<208> a_wl_r<223> a_wl_r<222> a_wl_r<221> a_wl_r<220> a_wl_r<219> a_wl_r<218> a_wl_r<217> a_wl_r<216> a_wl_r<215> a_wl_r<214> a_wl_r<213> a_wl_r<212> a_wl_r<211> a_wl_r<210> a_wl_r<209> a_wl_r<208> VDD! VSS! / RM_IHPSG13_1024x32_c2_1P_WLDRV16X4 +XA_WLDRV<28> a_wi<207> a_wi<206> a_wi<205> a_wi<204> a_wi<203> a_wi<202> a_wi<201> a_wi<200> a_wi<199> a_wi<198> a_wi<197> a_wi<196> a_wi<195> a_wi<194> a_wi<193> a_wi<192> a_wl_r<207> a_wl_r<206> a_wl_r<205> a_wl_r<204> a_wl_r<203> a_wl_r<202> a_wl_r<201> a_wl_r<200> a_wl_r<199> a_wl_r<198> a_wl_r<197> a_wl_r<196> a_wl_r<195> a_wl_r<194> a_wl_r<193> a_wl_r<192> VDD! VSS! / RM_IHPSG13_1024x32_c2_1P_WLDRV16X4 +XA_WLDRV<27> a_wi<191> a_wi<190> a_wi<189> a_wi<188> a_wi<187> a_wi<186> a_wi<185> a_wi<184> a_wi<183> a_wi<182> a_wi<181> a_wi<180> a_wi<179> a_wi<178> a_wi<177> a_wi<176> a_wl_r<191> a_wl_r<190> a_wl_r<189> a_wl_r<188> a_wl_r<187> a_wl_r<186> a_wl_r<185> a_wl_r<184> a_wl_r<183> a_wl_r<182> a_wl_r<181> a_wl_r<180> a_wl_r<179> a_wl_r<178> a_wl_r<177> a_wl_r<176> VDD! VSS! / RM_IHPSG13_1024x32_c2_1P_WLDRV16X4 +XA_WLDRV<26> a_wi<175> a_wi<174> a_wi<173> a_wi<172> a_wi<171> a_wi<170> a_wi<169> a_wi<168> a_wi<167> a_wi<166> a_wi<165> a_wi<164> a_wi<163> a_wi<162> a_wi<161> a_wi<160> a_wl_r<175> a_wl_r<174> a_wl_r<173> a_wl_r<172> a_wl_r<171> a_wl_r<170> a_wl_r<169> a_wl_r<168> a_wl_r<167> a_wl_r<166> a_wl_r<165> a_wl_r<164> a_wl_r<163> a_wl_r<162> a_wl_r<161> a_wl_r<160> VDD! VSS! / RM_IHPSG13_1024x32_c2_1P_WLDRV16X4 +XA_WLDRV<25> a_wi<159> a_wi<158> a_wi<157> a_wi<156> a_wi<155> a_wi<154> a_wi<153> a_wi<152> a_wi<151> a_wi<150> a_wi<149> a_wi<148> a_wi<147> a_wi<146> a_wi<145> a_wi<144> a_wl_r<159> a_wl_r<158> a_wl_r<157> a_wl_r<156> a_wl_r<155> a_wl_r<154> a_wl_r<153> a_wl_r<152> a_wl_r<151> a_wl_r<150> a_wl_r<149> a_wl_r<148> a_wl_r<147> a_wl_r<146> a_wl_r<145> a_wl_r<144> VDD! VSS! / RM_IHPSG13_1024x32_c2_1P_WLDRV16X4 +XA_WLDRV<24> a_wi<143> a_wi<142> a_wi<141> a_wi<140> a_wi<139> a_wi<138> a_wi<137> a_wi<136> a_wi<135> a_wi<134> a_wi<133> a_wi<132> a_wi<131> a_wi<130> a_wi<129> a_wi<128> a_wl_r<143> a_wl_r<142> a_wl_r<141> a_wl_r<140> a_wl_r<139> a_wl_r<138> a_wl_r<137> a_wl_r<136> a_wl_r<135> a_wl_r<134> a_wl_r<133> a_wl_r<132> a_wl_r<131> a_wl_r<130> a_wl_r<129> a_wl_r<128> VDD! VSS! / RM_IHPSG13_1024x32_c2_1P_WLDRV16X4 +XA_WLDRV<23> a_wi<127> a_wi<126> a_wi<125> a_wi<124> a_wi<123> a_wi<122> a_wi<121> a_wi<120> a_wi<119> a_wi<118> a_wi<117> a_wi<116> a_wi<115> a_wi<114> a_wi<113> a_wi<112> a_wl_r<127> a_wl_r<126> a_wl_r<125> a_wl_r<124> a_wl_r<123> a_wl_r<122> a_wl_r<121> a_wl_r<120> a_wl_r<119> a_wl_r<118> a_wl_r<117> a_wl_r<116> a_wl_r<115> a_wl_r<114> a_wl_r<113> a_wl_r<112> VDD! VSS! / RM_IHPSG13_1024x32_c2_1P_WLDRV16X4 +XA_WLDRV<22> a_wi<111> a_wi<110> a_wi<109> a_wi<108> a_wi<107> a_wi<106> a_wi<105> a_wi<104> a_wi<103> a_wi<102> a_wi<101> a_wi<100> a_wi<99> a_wi<98> a_wi<97> a_wi<96> a_wl_r<111> a_wl_r<110> a_wl_r<109> a_wl_r<108> a_wl_r<107> a_wl_r<106> a_wl_r<105> a_wl_r<104> a_wl_r<103> a_wl_r<102> a_wl_r<101> a_wl_r<100> a_wl_r<99> a_wl_r<98> a_wl_r<97> a_wl_r<96> VDD! VSS! / RM_IHPSG13_1024x32_c2_1P_WLDRV16X4 +XA_WLDRV<21> a_wi<95> a_wi<94> a_wi<93> a_wi<92> a_wi<91> a_wi<90> a_wi<89> a_wi<88> a_wi<87> a_wi<86> a_wi<85> a_wi<84> a_wi<83> a_wi<82> a_wi<81> a_wi<80> a_wl_r<95> a_wl_r<94> a_wl_r<93> a_wl_r<92> a_wl_r<91> a_wl_r<90> a_wl_r<89> a_wl_r<88> a_wl_r<87> a_wl_r<86> a_wl_r<85> a_wl_r<84> a_wl_r<83> a_wl_r<82> a_wl_r<81> a_wl_r<80> VDD! VSS! / RM_IHPSG13_1024x32_c2_1P_WLDRV16X4 +XA_WLDRV<20> a_wi<79> a_wi<78> a_wi<77> a_wi<76> a_wi<75> a_wi<74> a_wi<73> a_wi<72> a_wi<71> a_wi<70> a_wi<69> a_wi<68> a_wi<67> a_wi<66> a_wi<65> a_wi<64> a_wl_r<79> a_wl_r<78> a_wl_r<77> a_wl_r<76> a_wl_r<75> a_wl_r<74> a_wl_r<73> a_wl_r<72> a_wl_r<71> a_wl_r<70> a_wl_r<69> a_wl_r<68> a_wl_r<67> a_wl_r<66> a_wl_r<65> a_wl_r<64> VDD! VSS! / RM_IHPSG13_1024x32_c2_1P_WLDRV16X4 +XA_WLDRV<19> a_wi<63> a_wi<62> a_wi<61> a_wi<60> a_wi<59> a_wi<58> a_wi<57> a_wi<56> a_wi<55> a_wi<54> a_wi<53> a_wi<52> a_wi<51> a_wi<50> a_wi<49> a_wi<48> a_wl_r<63> a_wl_r<62> a_wl_r<61> a_wl_r<60> a_wl_r<59> a_wl_r<58> a_wl_r<57> a_wl_r<56> a_wl_r<55> a_wl_r<54> a_wl_r<53> a_wl_r<52> a_wl_r<51> a_wl_r<50> a_wl_r<49> a_wl_r<48> VDD! VSS! / RM_IHPSG13_1024x32_c2_1P_WLDRV16X4 +XA_WLDRV<18> a_wi<47> a_wi<46> a_wi<45> a_wi<44> a_wi<43> a_wi<42> a_wi<41> a_wi<40> a_wi<39> a_wi<38> a_wi<37> a_wi<36> a_wi<35> a_wi<34> a_wi<33> a_wi<32> a_wl_r<47> a_wl_r<46> a_wl_r<45> a_wl_r<44> a_wl_r<43> a_wl_r<42> a_wl_r<41> a_wl_r<40> a_wl_r<39> a_wl_r<38> a_wl_r<37> a_wl_r<36> a_wl_r<35> a_wl_r<34> a_wl_r<33> a_wl_r<32> VDD! VSS! / RM_IHPSG13_1024x32_c2_1P_WLDRV16X4 +XA_WLDRV<17> a_wi<31> a_wi<30> a_wi<29> a_wi<28> a_wi<27> a_wi<26> a_wi<25> a_wi<24> a_wi<23> a_wi<22> a_wi<21> a_wi<20> a_wi<19> a_wi<18> a_wi<17> a_wi<16> a_wl_r<31> a_wl_r<30> a_wl_r<29> a_wl_r<28> a_wl_r<27> a_wl_r<26> a_wl_r<25> a_wl_r<24> a_wl_r<23> a_wl_r<22> a_wl_r<21> a_wl_r<20> a_wl_r<19> a_wl_r<18> a_wl_r<17> a_wl_r<16> VDD! VSS! / RM_IHPSG13_1024x32_c2_1P_WLDRV16X4 +XA_WLDRV<16> a_wi<15> a_wi<14> a_wi<13> a_wi<12> a_wi<11> a_wi<10> a_wi<9> a_wi<8> a_wi<7> a_wi<6> a_wi<5> a_wi<4> a_wi<3> a_wi<2> a_wi<1> a_wi<0> a_wl_r<15> a_wl_r<14> a_wl_r<13> a_wl_r<12> a_wl_r<11> a_wl_r<10> a_wl_r<9> a_wl_r<8> a_wl_r<7> a_wl_r<6> a_wl_r<5> a_wl_r<4> a_wl_r<3> a_wl_r<2> a_wl_r<1> a_wl_r<0> VDD! VSS! / RM_IHPSG13_1024x32_c2_1P_WLDRV16X4 +XA_WLDRV<15> a_wi<255> a_wi<254> a_wi<253> a_wi<252> a_wi<251> a_wi<250> a_wi<249> a_wi<248> a_wi<247> a_wi<246> a_wi<245> a_wi<244> a_wi<243> a_wi<242> a_wi<241> a_wi<240> a_wl_l<255> a_wl_l<254> a_wl_l<253> a_wl_l<252> a_wl_l<251> a_wl_l<250> a_wl_l<249> a_wl_l<248> a_wl_l<247> a_wl_l<246> a_wl_l<245> a_wl_l<244> a_wl_l<243> a_wl_l<242> a_wl_l<241> a_wl_l<240> VDD! VSS! / RM_IHPSG13_1024x32_c2_1P_WLDRV16X4 +XA_WLDRV<14> a_wi<239> a_wi<238> a_wi<237> a_wi<236> a_wi<235> a_wi<234> a_wi<233> a_wi<232> a_wi<231> a_wi<230> a_wi<229> a_wi<228> a_wi<227> a_wi<226> a_wi<225> a_wi<224> a_wl_l<239> a_wl_l<238> a_wl_l<237> a_wl_l<236> a_wl_l<235> a_wl_l<234> a_wl_l<233> a_wl_l<232> a_wl_l<231> a_wl_l<230> a_wl_l<229> a_wl_l<228> a_wl_l<227> a_wl_l<226> a_wl_l<225> a_wl_l<224> VDD! VSS! / RM_IHPSG13_1024x32_c2_1P_WLDRV16X4 +XA_WLDRV<13> a_wi<223> a_wi<222> a_wi<221> a_wi<220> a_wi<219> a_wi<218> a_wi<217> a_wi<216> a_wi<215> a_wi<214> a_wi<213> a_wi<212> a_wi<211> a_wi<210> a_wi<209> a_wi<208> a_wl_l<223> a_wl_l<222> a_wl_l<221> a_wl_l<220> a_wl_l<219> a_wl_l<218> a_wl_l<217> a_wl_l<216> a_wl_l<215> a_wl_l<214> a_wl_l<213> a_wl_l<212> a_wl_l<211> a_wl_l<210> a_wl_l<209> a_wl_l<208> VDD! VSS! / RM_IHPSG13_1024x32_c2_1P_WLDRV16X4 +XA_WLDRV<12> a_wi<207> a_wi<206> a_wi<205> a_wi<204> a_wi<203> a_wi<202> a_wi<201> a_wi<200> a_wi<199> a_wi<198> a_wi<197> a_wi<196> a_wi<195> a_wi<194> a_wi<193> a_wi<192> a_wl_l<207> a_wl_l<206> a_wl_l<205> a_wl_l<204> a_wl_l<203> a_wl_l<202> a_wl_l<201> a_wl_l<200> a_wl_l<199> a_wl_l<198> a_wl_l<197> a_wl_l<196> a_wl_l<195> a_wl_l<194> a_wl_l<193> a_wl_l<192> VDD! VSS! / RM_IHPSG13_1024x32_c2_1P_WLDRV16X4 +XA_WLDRV<11> a_wi<191> a_wi<190> a_wi<189> a_wi<188> a_wi<187> a_wi<186> a_wi<185> a_wi<184> a_wi<183> a_wi<182> a_wi<181> a_wi<180> a_wi<179> a_wi<178> a_wi<177> a_wi<176> a_wl_l<191> a_wl_l<190> a_wl_l<189> a_wl_l<188> a_wl_l<187> a_wl_l<186> a_wl_l<185> a_wl_l<184> a_wl_l<183> a_wl_l<182> a_wl_l<181> a_wl_l<180> a_wl_l<179> a_wl_l<178> a_wl_l<177> a_wl_l<176> VDD! VSS! / RM_IHPSG13_1024x32_c2_1P_WLDRV16X4 +XA_WLDRV<10> a_wi<175> a_wi<174> a_wi<173> a_wi<172> a_wi<171> a_wi<170> a_wi<169> a_wi<168> a_wi<167> a_wi<166> a_wi<165> a_wi<164> a_wi<163> a_wi<162> a_wi<161> a_wi<160> a_wl_l<175> a_wl_l<174> a_wl_l<173> a_wl_l<172> a_wl_l<171> a_wl_l<170> a_wl_l<169> a_wl_l<168> a_wl_l<167> a_wl_l<166> a_wl_l<165> a_wl_l<164> a_wl_l<163> a_wl_l<162> a_wl_l<161> a_wl_l<160> VDD! VSS! / RM_IHPSG13_1024x32_c2_1P_WLDRV16X4 +XA_WLDRV<9> a_wi<159> a_wi<158> a_wi<157> a_wi<156> a_wi<155> a_wi<154> a_wi<153> a_wi<152> a_wi<151> a_wi<150> a_wi<149> a_wi<148> a_wi<147> a_wi<146> a_wi<145> a_wi<144> a_wl_l<159> a_wl_l<158> a_wl_l<157> a_wl_l<156> a_wl_l<155> a_wl_l<154> a_wl_l<153> a_wl_l<152> a_wl_l<151> a_wl_l<150> a_wl_l<149> a_wl_l<148> a_wl_l<147> a_wl_l<146> a_wl_l<145> a_wl_l<144> VDD! VSS! / RM_IHPSG13_1024x32_c2_1P_WLDRV16X4 +XA_WLDRV<8> a_wi<143> a_wi<142> a_wi<141> a_wi<140> a_wi<139> a_wi<138> a_wi<137> a_wi<136> a_wi<135> a_wi<134> a_wi<133> a_wi<132> a_wi<131> a_wi<130> a_wi<129> a_wi<128> a_wl_l<143> a_wl_l<142> a_wl_l<141> a_wl_l<140> a_wl_l<139> a_wl_l<138> a_wl_l<137> a_wl_l<136> a_wl_l<135> a_wl_l<134> a_wl_l<133> a_wl_l<132> a_wl_l<131> a_wl_l<130> a_wl_l<129> a_wl_l<128> VDD! VSS! / RM_IHPSG13_1024x32_c2_1P_WLDRV16X4 +XA_WLDRV<7> a_wi<127> a_wi<126> a_wi<125> a_wi<124> a_wi<123> a_wi<122> a_wi<121> a_wi<120> a_wi<119> a_wi<118> a_wi<117> a_wi<116> a_wi<115> a_wi<114> a_wi<113> a_wi<112> a_wl_l<127> a_wl_l<126> a_wl_l<125> a_wl_l<124> a_wl_l<123> a_wl_l<122> a_wl_l<121> a_wl_l<120> a_wl_l<119> a_wl_l<118> a_wl_l<117> a_wl_l<116> a_wl_l<115> a_wl_l<114> a_wl_l<113> a_wl_l<112> VDD! VSS! / RM_IHPSG13_1024x32_c2_1P_WLDRV16X4 +XA_WLDRV<6> a_wi<111> a_wi<110> a_wi<109> a_wi<108> a_wi<107> a_wi<106> a_wi<105> a_wi<104> a_wi<103> a_wi<102> a_wi<101> a_wi<100> a_wi<99> a_wi<98> a_wi<97> a_wi<96> a_wl_l<111> a_wl_l<110> a_wl_l<109> a_wl_l<108> a_wl_l<107> a_wl_l<106> a_wl_l<105> a_wl_l<104> a_wl_l<103> a_wl_l<102> a_wl_l<101> a_wl_l<100> a_wl_l<99> a_wl_l<98> a_wl_l<97> a_wl_l<96> VDD! VSS! / RM_IHPSG13_1024x32_c2_1P_WLDRV16X4 +XA_WLDRV<5> a_wi<95> a_wi<94> a_wi<93> a_wi<92> a_wi<91> a_wi<90> a_wi<89> a_wi<88> a_wi<87> a_wi<86> a_wi<85> a_wi<84> a_wi<83> a_wi<82> a_wi<81> a_wi<80> a_wl_l<95> a_wl_l<94> a_wl_l<93> a_wl_l<92> a_wl_l<91> a_wl_l<90> a_wl_l<89> a_wl_l<88> a_wl_l<87> a_wl_l<86> a_wl_l<85> a_wl_l<84> a_wl_l<83> a_wl_l<82> a_wl_l<81> a_wl_l<80> VDD! VSS! / RM_IHPSG13_1024x32_c2_1P_WLDRV16X4 +XA_WLDRV<4> a_wi<79> a_wi<78> a_wi<77> a_wi<76> a_wi<75> a_wi<74> a_wi<73> a_wi<72> a_wi<71> a_wi<70> a_wi<69> a_wi<68> a_wi<67> a_wi<66> a_wi<65> a_wi<64> a_wl_l<79> a_wl_l<78> a_wl_l<77> a_wl_l<76> a_wl_l<75> a_wl_l<74> a_wl_l<73> a_wl_l<72> a_wl_l<71> a_wl_l<70> a_wl_l<69> a_wl_l<68> a_wl_l<67> a_wl_l<66> a_wl_l<65> a_wl_l<64> VDD! VSS! / RM_IHPSG13_1024x32_c2_1P_WLDRV16X4 +XA_WLDRV<3> a_wi<63> a_wi<62> a_wi<61> a_wi<60> a_wi<59> a_wi<58> a_wi<57> a_wi<56> a_wi<55> a_wi<54> a_wi<53> a_wi<52> a_wi<51> a_wi<50> a_wi<49> a_wi<48> a_wl_l<63> a_wl_l<62> a_wl_l<61> a_wl_l<60> a_wl_l<59> a_wl_l<58> a_wl_l<57> a_wl_l<56> a_wl_l<55> a_wl_l<54> a_wl_l<53> a_wl_l<52> a_wl_l<51> a_wl_l<50> a_wl_l<49> a_wl_l<48> VDD! VSS! / RM_IHPSG13_1024x32_c2_1P_WLDRV16X4 +XA_WLDRV<2> a_wi<47> a_wi<46> a_wi<45> a_wi<44> a_wi<43> a_wi<42> a_wi<41> a_wi<40> a_wi<39> a_wi<38> a_wi<37> a_wi<36> a_wi<35> a_wi<34> a_wi<33> a_wi<32> a_wl_l<47> a_wl_l<46> a_wl_l<45> a_wl_l<44> a_wl_l<43> a_wl_l<42> a_wl_l<41> a_wl_l<40> a_wl_l<39> a_wl_l<38> a_wl_l<37> a_wl_l<36> a_wl_l<35> a_wl_l<34> a_wl_l<33> a_wl_l<32> VDD! VSS! / RM_IHPSG13_1024x32_c2_1P_WLDRV16X4 +XA_WLDRV<1> a_wi<31> a_wi<30> a_wi<29> a_wi<28> a_wi<27> a_wi<26> a_wi<25> a_wi<24> a_wi<23> a_wi<22> a_wi<21> a_wi<20> a_wi<19> a_wi<18> a_wi<17> a_wi<16> a_wl_l<31> a_wl_l<30> a_wl_l<29> a_wl_l<28> a_wl_l<27> a_wl_l<26> a_wl_l<25> a_wl_l<24> a_wl_l<23> a_wl_l<22> a_wl_l<21> a_wl_l<20> a_wl_l<19> a_wl_l<18> a_wl_l<17> a_wl_l<16> VDD! VSS! / RM_IHPSG13_1024x32_c2_1P_WLDRV16X4 +XA_WLDRV<0> a_wi<15> a_wi<14> a_wi<13> a_wi<12> a_wi<11> a_wi<10> a_wi<9> a_wi<8> a_wi<7> a_wi<6> a_wi<5> a_wi<4> a_wi<3> a_wi<2> a_wi<1> a_wi<0> a_wl_l<15> a_wl_l<14> a_wl_l<13> a_wl_l<12> a_wl_l<11> a_wl_l<10> a_wl_l<9> a_wl_l<8> a_wl_l<7> a_wl_l<6> a_wl_l<5> a_wl_l<4> a_wl_l<3> a_wl_l<2> a_wl_l<1> a_wl_l<0> VDD! VSS! / RM_IHPSG13_1024x32_c2_1P_WLDRV16X4 + + +XA_CTRL a_aclk_n A_BIST_CLK A_BIST_MEN A_BIST_EN A_BIST_REN A_BIST_WEN a_tiel A_CLK A_MEN a_dclk a_eclk a_pulse_h a_pulse_l a_pulse a_rclk A_REN a_cs a_wclk A_WEN VDD! VSS! / RM_IHPSG13_1024x32_c2_1P_CTRL + + +XA_ROWDEC a_addr_row<7> a_addr_row<6> a_addr_row<5> a_addr_row<4> a_addr_row<3> a_addr_row<2> a_addr_row<1> a_addr_row<0> a_cs a_eclk a_wi<255> a_wi<254> a_wi<253> a_wi<252> a_wi<251> a_wi<250> a_wi<249> a_wi<248> a_wi<247> a_wi<246> a_wi<245> a_wi<244> a_wi<243> a_wi<242> a_wi<241> a_wi<240> a_wi<239> a_wi<238> a_wi<237> a_wi<236> a_wi<235> a_wi<234> a_wi<233> a_wi<232> a_wi<231> a_wi<230> a_wi<229> a_wi<228> a_wi<227> a_wi<226> a_wi<225> a_wi<224> a_wi<223> a_wi<222> a_wi<221> a_wi<220> a_wi<219> a_wi<218> a_wi<217> a_wi<216> a_wi<215> a_wi<214> a_wi<213> a_wi<212> a_wi<211> a_wi<210> a_wi<209> a_wi<208> a_wi<207> a_wi<206> a_wi<205> a_wi<204> a_wi<203> a_wi<202> a_wi<201> a_wi<200> a_wi<199> a_wi<198> a_wi<197> a_wi<196> a_wi<195> a_wi<194> a_wi<193> a_wi<192> a_wi<191> a_wi<190> a_wi<189> a_wi<188> a_wi<187> a_wi<186> a_wi<185> a_wi<184> a_wi<183> a_wi<182> a_wi<181> a_wi<180> a_wi<179> a_wi<178> a_wi<177> a_wi<176> a_wi<175> a_wi<174> a_wi<173> a_wi<172> a_wi<171> a_wi<170> a_wi<169> a_wi<168> a_wi<167> a_wi<166> a_wi<165> a_wi<164> a_wi<163> a_wi<162> a_wi<161> a_wi<160> a_wi<159> a_wi<158> a_wi<157> a_wi<156> a_wi<155> a_wi<154> a_wi<153> a_wi<152> a_wi<151> a_wi<150> a_wi<149> a_wi<148> a_wi<147> a_wi<146> a_wi<145> a_wi<144> a_wi<143> a_wi<142> a_wi<141> a_wi<140> a_wi<139> a_wi<138> a_wi<137> a_wi<136> a_wi<135> a_wi<134> a_wi<133> a_wi<132> a_wi<131> a_wi<130> a_wi<129> a_wi<128> a_wi<127> a_wi<126> a_wi<125> a_wi<124> a_wi<123> a_wi<122> a_wi<121> a_wi<120> a_wi<119> a_wi<118> a_wi<117> a_wi<116> a_wi<115> a_wi<114> a_wi<113> a_wi<112> a_wi<111> a_wi<110> a_wi<109> a_wi<108> a_wi<107> a_wi<106> a_wi<105> a_wi<104> a_wi<103> a_wi<102> a_wi<101> a_wi<100> a_wi<99> a_wi<98> a_wi<97> a_wi<96> a_wi<95> a_wi<94> a_wi<93> a_wi<92> a_wi<91> a_wi<90> a_wi<89> a_wi<88> a_wi<87> a_wi<86> a_wi<85> a_wi<84> a_wi<83> a_wi<82> a_wi<81> a_wi<80> a_wi<79> a_wi<78> a_wi<77> a_wi<76> a_wi<75> a_wi<74> a_wi<73> a_wi<72> a_wi<71> a_wi<70> a_wi<69> a_wi<68> a_wi<67> a_wi<66> a_wi<65> a_wi<64> a_wi<63> a_wi<62> a_wi<61> a_wi<60> a_wi<59> a_wi<58> a_wi<57> a_wi<56> a_wi<55> a_wi<54> a_wi<53> a_wi<52> a_wi<51> a_wi<50> a_wi<49> a_wi<48> a_wi<47> a_wi<46> a_wi<45> a_wi<44> a_wi<43> a_wi<42> a_wi<41> a_wi<40> a_wi<39> a_wi<38> a_wi<37> a_wi<36> a_wi<35> a_wi<34> a_wi<33> a_wi<32> a_wi<31> a_wi<30> a_wi<29> a_wi<28> a_wi<27> a_wi<26> a_wi<25> a_wi<24> a_wi<23> a_wi<22> a_wi<21> a_wi<20> a_wi<19> a_wi<18> a_wi<17> a_wi<16> a_wi<15> a_wi<14> a_wi<13> a_wi<12> a_wi<11> a_wi<10> a_wi<9> a_wi<8> a_wi<7> a_wi<6> a_wi<5> a_wi<4> a_wi<3> a_wi<2> a_wi<1> a_wi<0> VDD! VSS! / RM_IHPSG13_1024x32_c2_1P_ROWDEC8 +XA_ROWREG a_aclk_n A_ADDR<9> A_ADDR<8> A_ADDR<7> A_ADDR<6> A_ADDR<5> A_ADDR<4> A_ADDR<3> A_ADDR<2> a_addr_row<7> a_addr_row<6> a_addr_row<5> a_addr_row<4> a_addr_row<3> a_addr_row<2> a_addr_row<1> a_addr_row<0> A_BIST_ADDR<9> A_BIST_ADDR<8> A_BIST_ADDR<7> A_BIST_ADDR<6> A_BIST_ADDR<5> A_BIST_ADDR<4> A_BIST_ADDR<3> A_BIST_ADDR<2> A_BIST_EN VDD! VSS! / RM_IHPSG13_1024x32_c2_1P_ROWREG8 +XA_COLDEC a_aclk_n A_ADDR<1> A_ADDR<0> a_addr_col<1> a_addr_col<0> a_addr_dec<7> a_addr_dec<6> a_addr_dec<5> a_addr_dec<4> a_addr_dec<3> a_addr_dec<2> a_addr_dec<1> a_addr_dec<0> A_BIST_ADDR<1> A_BIST_ADDR<0> A_BIST_EN VDD! VSS! / RM_IHPSG13_1024x32_c2_1P_COLDEC2 + + +XA_DLYH a_pulse a_pulse_h VDD! VSS! / RM_IHPSG13_1024x32_c2_1P_DLY_pcell_2 +XA_DLYL a_pulse_x a_pulse_l VDD! VSS! / RM_IHPSG13_1024x32_c2_1P_DLY_pcell_3 +XA_DLYMUX a_pulse_h A_DLY a_pulse_x VDD! VSS! / RM_IHPSG13_1024x32_c2_1P_DLY_MUX + +XCOLCTRL<31> a_addr_dec_r<3> a_addr_dec_r<2> a_addr_dec_r<1> a_addr_dec_r<0> A_BIST_BM<31> A_BIST_DIN<31> A_BIST_EN a_blc_r<63> a_blc_r<62> a_blc_r<61> a_blc_r<60> a_blt_r<63> a_blt_r<62> a_blt_r<61> a_blt_r<60> A_BM<31> a_dclk_n_r<15> a_dclk_n_r<16> a_dclk_p_r<15> a_dclk_p_r<16> A_DOUT<31> A_DIN<31> a_rclk_n_r<15> a_rclk_n_r<16> a_rclk_p_r<15> a_rclk_p_r<16> a_tieh<31> a_wclk_n_r<15> a_wclk_n_r<16> a_wclk_p_r<15> a_wclk_p_r<16> VDD! VSS! / RM_IHPSG13_1024x32_c2_1P_COLCTRL2 +XCOLCTRL<30> a_addr_dec_r<3> a_addr_dec_r<2> a_addr_dec_r<1> a_addr_dec_r<0> A_BIST_BM<30> A_BIST_DIN<30> A_BIST_EN a_blc_r<59> a_blc_r<58> a_blc_r<57> a_blc_r<56> a_blt_r<59> a_blt_r<58> a_blt_r<57> a_blt_r<56> A_BM<30> a_dclk_n_r<14> a_dclk_n_r<15> a_dclk_p_r<14> a_dclk_p_r<15> A_DOUT<30> A_DIN<30> a_rclk_n_r<14> a_rclk_n_r<15> a_rclk_p_r<14> a_rclk_p_r<15> a_tieh<30> a_wclk_n_r<14> a_wclk_n_r<15> a_wclk_p_r<14> a_wclk_p_r<15> VDD! VSS! / RM_IHPSG13_1024x32_c2_1P_COLCTRL2 +XCOLCTRL<29> a_addr_dec_r<3> a_addr_dec_r<2> a_addr_dec_r<1> a_addr_dec_r<0> A_BIST_BM<29> A_BIST_DIN<29> A_BIST_EN a_blc_r<55> a_blc_r<54> a_blc_r<53> a_blc_r<52> a_blt_r<55> a_blt_r<54> a_blt_r<53> a_blt_r<52> A_BM<29> a_dclk_n_r<13> a_dclk_n_r<14> a_dclk_p_r<13> a_dclk_p_r<14> A_DOUT<29> A_DIN<29> a_rclk_n_r<13> a_rclk_n_r<14> a_rclk_p_r<13> a_rclk_p_r<14> a_tieh<29> a_wclk_n_r<13> a_wclk_n_r<14> a_wclk_p_r<13> a_wclk_p_r<14> VDD! VSS! / RM_IHPSG13_1024x32_c2_1P_COLCTRL2 +XCOLCTRL<28> a_addr_dec_r<3> a_addr_dec_r<2> a_addr_dec_r<1> a_addr_dec_r<0> A_BIST_BM<28> A_BIST_DIN<28> A_BIST_EN a_blc_r<51> a_blc_r<50> a_blc_r<49> a_blc_r<48> a_blt_r<51> a_blt_r<50> a_blt_r<49> a_blt_r<48> A_BM<28> a_dclk_n_r<12> a_dclk_n_r<13> a_dclk_p_r<12> a_dclk_p_r<13> A_DOUT<28> A_DIN<28> a_rclk_n_r<12> a_rclk_n_r<13> a_rclk_p_r<12> a_rclk_p_r<13> a_tieh<28> a_wclk_n_r<12> a_wclk_n_r<13> a_wclk_p_r<12> a_wclk_p_r<13> VDD! VSS! / RM_IHPSG13_1024x32_c2_1P_COLCTRL2 +XCOLCTRL<27> a_addr_dec_r<3> a_addr_dec_r<2> a_addr_dec_r<1> a_addr_dec_r<0> A_BIST_BM<27> A_BIST_DIN<27> A_BIST_EN a_blc_r<47> a_blc_r<46> a_blc_r<45> a_blc_r<44> a_blt_r<47> a_blt_r<46> a_blt_r<45> a_blt_r<44> A_BM<27> a_dclk_n_r<11> a_dclk_n_r<12> a_dclk_p_r<11> a_dclk_p_r<12> A_DOUT<27> A_DIN<27> a_rclk_n_r<11> a_rclk_n_r<12> a_rclk_p_r<11> a_rclk_p_r<12> a_tieh<27> a_wclk_n_r<11> a_wclk_n_r<12> a_wclk_p_r<11> a_wclk_p_r<12> VDD! VSS! / RM_IHPSG13_1024x32_c2_1P_COLCTRL2 +XCOLCTRL<26> a_addr_dec_r<3> a_addr_dec_r<2> a_addr_dec_r<1> a_addr_dec_r<0> A_BIST_BM<26> A_BIST_DIN<26> A_BIST_EN a_blc_r<43> a_blc_r<42> a_blc_r<41> a_blc_r<40> a_blt_r<43> a_blt_r<42> a_blt_r<41> a_blt_r<40> A_BM<26> a_dclk_n_r<10> a_dclk_n_r<11> a_dclk_p_r<10> a_dclk_p_r<11> A_DOUT<26> A_DIN<26> a_rclk_n_r<10> a_rclk_n_r<11> a_rclk_p_r<10> a_rclk_p_r<11> a_tieh<26> a_wclk_n_r<10> a_wclk_n_r<11> a_wclk_p_r<10> a_wclk_p_r<11> VDD! VSS! / RM_IHPSG13_1024x32_c2_1P_COLCTRL2 +XCOLCTRL<25> a_addr_dec_r<3> a_addr_dec_r<2> a_addr_dec_r<1> a_addr_dec_r<0> A_BIST_BM<25> A_BIST_DIN<25> A_BIST_EN a_blc_r<39> a_blc_r<38> a_blc_r<37> a_blc_r<36> a_blt_r<39> a_blt_r<38> a_blt_r<37> a_blt_r<36> A_BM<25> a_dclk_n_r<9> a_dclk_n_r<10> a_dclk_p_r<9> a_dclk_p_r<10> A_DOUT<25> A_DIN<25> a_rclk_n_r<9> a_rclk_n_r<10> a_rclk_p_r<9> a_rclk_p_r<10> a_tieh<25> a_wclk_n_r<9> a_wclk_n_r<10> a_wclk_p_r<9> a_wclk_p_r<10> VDD! VSS! / RM_IHPSG13_1024x32_c2_1P_COLCTRL2 +XCOLCTRL<24> a_addr_dec_r<3> a_addr_dec_r<2> a_addr_dec_r<1> a_addr_dec_r<0> A_BIST_BM<24> A_BIST_DIN<24> A_BIST_EN a_blc_r<35> a_blc_r<34> a_blc_r<33> a_blc_r<32> a_blt_r<35> a_blt_r<34> a_blt_r<33> a_blt_r<32> A_BM<24> a_dclk_n_r<8> a_dclk_n_r<9> a_dclk_p_r<8> a_dclk_p_r<9> A_DOUT<24> A_DIN<24> a_rclk_n_r<8> a_rclk_n_r<9> a_rclk_p_r<8> a_rclk_p_r<9> a_tieh<24> a_wclk_n_r<8> a_wclk_n_r<9> a_wclk_p_r<8> a_wclk_p_r<9> VDD! VSS! / RM_IHPSG13_1024x32_c2_1P_COLCTRL2 +XCOLCTRL<23> a_addr_dec_r<3> a_addr_dec_r<2> a_addr_dec_r<1> a_addr_dec_r<0> A_BIST_BM<23> A_BIST_DIN<23> A_BIST_EN a_blc_r<31> a_blc_r<30> a_blc_r<29> a_blc_r<28> a_blt_r<31> a_blt_r<30> a_blt_r<29> a_blt_r<28> A_BM<23> a_dclk_n_r<7> a_dclk_n_r<8> a_dclk_p_r<7> a_dclk_p_r<8> A_DOUT<23> A_DIN<23> a_rclk_n_r<7> a_rclk_n_r<8> a_rclk_p_r<7> a_rclk_p_r<8> a_tieh<23> a_wclk_n_r<7> a_wclk_n_r<8> a_wclk_p_r<7> a_wclk_p_r<8> VDD! VSS! / RM_IHPSG13_1024x32_c2_1P_COLCTRL2 +XCOLCTRL<22> a_addr_dec_r<3> a_addr_dec_r<2> a_addr_dec_r<1> a_addr_dec_r<0> A_BIST_BM<22> A_BIST_DIN<22> A_BIST_EN a_blc_r<27> a_blc_r<26> a_blc_r<25> a_blc_r<24> a_blt_r<27> a_blt_r<26> a_blt_r<25> a_blt_r<24> A_BM<22> a_dclk_n_r<6> a_dclk_n_r<7> a_dclk_p_r<6> a_dclk_p_r<7> A_DOUT<22> A_DIN<22> a_rclk_n_r<6> a_rclk_n_r<7> a_rclk_p_r<6> a_rclk_p_r<7> a_tieh<22> a_wclk_n_r<6> a_wclk_n_r<7> a_wclk_p_r<6> a_wclk_p_r<7> VDD! VSS! / RM_IHPSG13_1024x32_c2_1P_COLCTRL2 +XCOLCTRL<21> a_addr_dec_r<3> a_addr_dec_r<2> a_addr_dec_r<1> a_addr_dec_r<0> A_BIST_BM<21> A_BIST_DIN<21> A_BIST_EN a_blc_r<23> a_blc_r<22> a_blc_r<21> a_blc_r<20> a_blt_r<23> a_blt_r<22> a_blt_r<21> a_blt_r<20> A_BM<21> a_dclk_n_r<5> a_dclk_n_r<6> a_dclk_p_r<5> a_dclk_p_r<6> A_DOUT<21> A_DIN<21> a_rclk_n_r<5> a_rclk_n_r<6> a_rclk_p_r<5> a_rclk_p_r<6> a_tieh<21> a_wclk_n_r<5> a_wclk_n_r<6> a_wclk_p_r<5> a_wclk_p_r<6> VDD! VSS! / RM_IHPSG13_1024x32_c2_1P_COLCTRL2 +XCOLCTRL<20> a_addr_dec_r<3> a_addr_dec_r<2> a_addr_dec_r<1> a_addr_dec_r<0> A_BIST_BM<20> A_BIST_DIN<20> A_BIST_EN a_blc_r<19> a_blc_r<18> a_blc_r<17> a_blc_r<16> a_blt_r<19> a_blt_r<18> a_blt_r<17> a_blt_r<16> A_BM<20> a_dclk_n_r<4> a_dclk_n_r<5> a_dclk_p_r<4> a_dclk_p_r<5> A_DOUT<20> A_DIN<20> a_rclk_n_r<4> a_rclk_n_r<5> a_rclk_p_r<4> a_rclk_p_r<5> a_tieh<20> a_wclk_n_r<4> a_wclk_n_r<5> a_wclk_p_r<4> a_wclk_p_r<5> VDD! VSS! / RM_IHPSG13_1024x32_c2_1P_COLCTRL2 +XCOLCTRL<19> a_addr_dec_r<3> a_addr_dec_r<2> a_addr_dec_r<1> a_addr_dec_r<0> A_BIST_BM<19> A_BIST_DIN<19> A_BIST_EN a_blc_r<15> a_blc_r<14> a_blc_r<13> a_blc_r<12> a_blt_r<15> a_blt_r<14> a_blt_r<13> a_blt_r<12> A_BM<19> a_dclk_n_r<3> a_dclk_n_r<4> a_dclk_p_r<3> a_dclk_p_r<4> A_DOUT<19> A_DIN<19> a_rclk_n_r<3> a_rclk_n_r<4> a_rclk_p_r<3> a_rclk_p_r<4> a_tieh<19> a_wclk_n_r<3> a_wclk_n_r<4> a_wclk_p_r<3> a_wclk_p_r<4> VDD! VSS! / RM_IHPSG13_1024x32_c2_1P_COLCTRL2 +XCOLCTRL<18> a_addr_dec_r<3> a_addr_dec_r<2> a_addr_dec_r<1> a_addr_dec_r<0> A_BIST_BM<18> A_BIST_DIN<18> A_BIST_EN a_blc_r<11> a_blc_r<10> a_blc_r<9> a_blc_r<8> a_blt_r<11> a_blt_r<10> a_blt_r<9> a_blt_r<8> A_BM<18> a_dclk_n_r<2> a_dclk_n_r<3> a_dclk_p_r<2> a_dclk_p_r<3> A_DOUT<18> A_DIN<18> a_rclk_n_r<2> a_rclk_n_r<3> a_rclk_p_r<2> a_rclk_p_r<3> a_tieh<18> a_wclk_n_r<2> a_wclk_n_r<3> a_wclk_p_r<2> a_wclk_p_r<3> VDD! VSS! / RM_IHPSG13_1024x32_c2_1P_COLCTRL2 +XCOLCTRL<17> a_addr_dec_r<3> a_addr_dec_r<2> a_addr_dec_r<1> a_addr_dec_r<0> A_BIST_BM<17> A_BIST_DIN<17> A_BIST_EN a_blc_r<7> a_blc_r<6> a_blc_r<5> a_blc_r<4> a_blt_r<7> a_blt_r<6> a_blt_r<5> a_blt_r<4> A_BM<17> a_dclk_n_r<1> a_dclk_n_r<2> a_dclk_p_r<1> a_dclk_p_r<2> A_DOUT<17> A_DIN<17> a_rclk_n_r<1> a_rclk_n_r<2> a_rclk_p_r<1> a_rclk_p_r<2> a_tieh<17> a_wclk_n_r<1> a_wclk_n_r<2> a_wclk_p_r<1> a_wclk_p_r<2> VDD! VSS! / RM_IHPSG13_1024x32_c2_1P_COLCTRL2 +XCOLCTRL<16> a_addr_dec_r<3> a_addr_dec_r<2> a_addr_dec_r<1> a_addr_dec_r<0> A_BIST_BM<16> A_BIST_DIN<16> A_BIST_EN a_blc_r<3> a_blc_r<2> a_blc_r<1> a_blc_r<0> a_blt_r<3> a_blt_r<2> a_blt_r<1> a_blt_r<0> A_BM<16> a_dclk_n_r<0> a_dclk_n_r<1> a_dclk_p_r<0> a_dclk_p_r<1> A_DOUT<16> A_DIN<16> a_rclk_n_r<0> a_rclk_n_r<1> a_rclk_p_r<0> a_rclk_p_r<1> a_tieh<16> a_wclk_n_r<0> a_wclk_n_r<1> a_wclk_p_r<0> a_wclk_p_r<1> VDD! VSS! / RM_IHPSG13_1024x32_c2_1P_COLCTRL2 +XCOLCTRL<15> a_addr_dec_l<3> a_addr_dec_l<2> a_addr_dec_l<1> a_addr_dec_l<0> A_BIST_BM<0> A_BIST_DIN<0> A_BIST_EN a_blc_l<63> a_blc_l<62> a_blc_l<61> a_blc_l<60> a_blt_l<63> a_blt_l<62> a_blt_l<61> a_blt_l<60> A_BM<0> a_dclk_n_l<15> a_dclk_n_l<16> a_dclk_p_l<15> a_dclk_p_l<16> A_DOUT<0> A_DIN<0> a_rclk_n_l<15> a_rclk_n_l<16> a_rclk_p_l<15> a_rclk_p_l<16> a_tieh<0> a_wclk_n_l<15> a_wclk_n_l<16> a_wclk_p_l<15> a_wclk_p_l<16> VDD! VSS! / RM_IHPSG13_1024x32_c2_1P_COLCTRL2 +XCOLCTRL<14> a_addr_dec_l<3> a_addr_dec_l<2> a_addr_dec_l<1> a_addr_dec_l<0> A_BIST_BM<1> A_BIST_DIN<1> A_BIST_EN a_blc_l<59> a_blc_l<58> a_blc_l<57> a_blc_l<56> a_blt_l<59> a_blt_l<58> a_blt_l<57> a_blt_l<56> A_BM<1> a_dclk_n_l<14> a_dclk_n_l<15> a_dclk_p_l<14> a_dclk_p_l<15> A_DOUT<1> A_DIN<1> a_rclk_n_l<14> a_rclk_n_l<15> a_rclk_p_l<14> a_rclk_p_l<15> a_tieh<1> a_wclk_n_l<14> a_wclk_n_l<15> a_wclk_p_l<14> a_wclk_p_l<15> VDD! VSS! / RM_IHPSG13_1024x32_c2_1P_COLCTRL2 +XCOLCTRL<13> a_addr_dec_l<3> a_addr_dec_l<2> a_addr_dec_l<1> a_addr_dec_l<0> A_BIST_BM<2> A_BIST_DIN<2> A_BIST_EN a_blc_l<55> a_blc_l<54> a_blc_l<53> a_blc_l<52> a_blt_l<55> a_blt_l<54> a_blt_l<53> a_blt_l<52> A_BM<2> a_dclk_n_l<13> a_dclk_n_l<14> a_dclk_p_l<13> a_dclk_p_l<14> A_DOUT<2> A_DIN<2> a_rclk_n_l<13> a_rclk_n_l<14> a_rclk_p_l<13> a_rclk_p_l<14> a_tieh<2> a_wclk_n_l<13> a_wclk_n_l<14> a_wclk_p_l<13> a_wclk_p_l<14> VDD! VSS! / RM_IHPSG13_1024x32_c2_1P_COLCTRL2 +XCOLCTRL<12> a_addr_dec_l<3> a_addr_dec_l<2> a_addr_dec_l<1> a_addr_dec_l<0> A_BIST_BM<3> A_BIST_DIN<3> A_BIST_EN a_blc_l<51> a_blc_l<50> a_blc_l<49> a_blc_l<48> a_blt_l<51> a_blt_l<50> a_blt_l<49> a_blt_l<48> A_BM<3> a_dclk_n_l<12> a_dclk_n_l<13> a_dclk_p_l<12> a_dclk_p_l<13> A_DOUT<3> A_DIN<3> a_rclk_n_l<12> a_rclk_n_l<13> a_rclk_p_l<12> a_rclk_p_l<13> a_tieh<3> a_wclk_n_l<12> a_wclk_n_l<13> a_wclk_p_l<12> a_wclk_p_l<13> VDD! VSS! / RM_IHPSG13_1024x32_c2_1P_COLCTRL2 +XCOLCTRL<11> a_addr_dec_l<3> a_addr_dec_l<2> a_addr_dec_l<1> a_addr_dec_l<0> A_BIST_BM<4> A_BIST_DIN<4> A_BIST_EN a_blc_l<47> a_blc_l<46> a_blc_l<45> a_blc_l<44> a_blt_l<47> a_blt_l<46> a_blt_l<45> a_blt_l<44> A_BM<4> a_dclk_n_l<11> a_dclk_n_l<12> a_dclk_p_l<11> a_dclk_p_l<12> A_DOUT<4> A_DIN<4> a_rclk_n_l<11> a_rclk_n_l<12> a_rclk_p_l<11> a_rclk_p_l<12> a_tieh<4> a_wclk_n_l<11> a_wclk_n_l<12> a_wclk_p_l<11> a_wclk_p_l<12> VDD! VSS! / RM_IHPSG13_1024x32_c2_1P_COLCTRL2 +XCOLCTRL<10> a_addr_dec_l<3> a_addr_dec_l<2> a_addr_dec_l<1> a_addr_dec_l<0> A_BIST_BM<5> A_BIST_DIN<5> A_BIST_EN a_blc_l<43> a_blc_l<42> a_blc_l<41> a_blc_l<40> a_blt_l<43> a_blt_l<42> a_blt_l<41> a_blt_l<40> A_BM<5> a_dclk_n_l<10> a_dclk_n_l<11> a_dclk_p_l<10> a_dclk_p_l<11> A_DOUT<5> A_DIN<5> a_rclk_n_l<10> a_rclk_n_l<11> a_rclk_p_l<10> a_rclk_p_l<11> a_tieh<5> a_wclk_n_l<10> a_wclk_n_l<11> a_wclk_p_l<10> a_wclk_p_l<11> VDD! VSS! / RM_IHPSG13_1024x32_c2_1P_COLCTRL2 +XCOLCTRL<9> a_addr_dec_l<3> a_addr_dec_l<2> a_addr_dec_l<1> a_addr_dec_l<0> A_BIST_BM<6> A_BIST_DIN<6> A_BIST_EN a_blc_l<39> a_blc_l<38> a_blc_l<37> a_blc_l<36> a_blt_l<39> a_blt_l<38> a_blt_l<37> a_blt_l<36> A_BM<6> a_dclk_n_l<9> a_dclk_n_l<10> a_dclk_p_l<9> a_dclk_p_l<10> A_DOUT<6> A_DIN<6> a_rclk_n_l<9> a_rclk_n_l<10> a_rclk_p_l<9> a_rclk_p_l<10> a_tieh<6> a_wclk_n_l<9> a_wclk_n_l<10> a_wclk_p_l<9> a_wclk_p_l<10> VDD! VSS! / RM_IHPSG13_1024x32_c2_1P_COLCTRL2 +XCOLCTRL<8> a_addr_dec_l<3> a_addr_dec_l<2> a_addr_dec_l<1> a_addr_dec_l<0> A_BIST_BM<7> A_BIST_DIN<7> A_BIST_EN a_blc_l<35> a_blc_l<34> a_blc_l<33> a_blc_l<32> a_blt_l<35> a_blt_l<34> a_blt_l<33> a_blt_l<32> A_BM<7> a_dclk_n_l<8> a_dclk_n_l<9> a_dclk_p_l<8> a_dclk_p_l<9> A_DOUT<7> A_DIN<7> a_rclk_n_l<8> a_rclk_n_l<9> a_rclk_p_l<8> a_rclk_p_l<9> a_tieh<7> a_wclk_n_l<8> a_wclk_n_l<9> a_wclk_p_l<8> a_wclk_p_l<9> VDD! VSS! / RM_IHPSG13_1024x32_c2_1P_COLCTRL2 +XCOLCTRL<7> a_addr_dec_l<3> a_addr_dec_l<2> a_addr_dec_l<1> a_addr_dec_l<0> A_BIST_BM<8> A_BIST_DIN<8> A_BIST_EN a_blc_l<31> a_blc_l<30> a_blc_l<29> a_blc_l<28> a_blt_l<31> a_blt_l<30> a_blt_l<29> a_blt_l<28> A_BM<8> a_dclk_n_l<7> a_dclk_n_l<8> a_dclk_p_l<7> a_dclk_p_l<8> A_DOUT<8> A_DIN<8> a_rclk_n_l<7> a_rclk_n_l<8> a_rclk_p_l<7> a_rclk_p_l<8> a_tieh<8> a_wclk_n_l<7> a_wclk_n_l<8> a_wclk_p_l<7> a_wclk_p_l<8> VDD! VSS! / RM_IHPSG13_1024x32_c2_1P_COLCTRL2 +XCOLCTRL<6> a_addr_dec_l<3> a_addr_dec_l<2> a_addr_dec_l<1> a_addr_dec_l<0> A_BIST_BM<9> A_BIST_DIN<9> A_BIST_EN a_blc_l<27> a_blc_l<26> a_blc_l<25> a_blc_l<24> a_blt_l<27> a_blt_l<26> a_blt_l<25> a_blt_l<24> A_BM<9> a_dclk_n_l<6> a_dclk_n_l<7> a_dclk_p_l<6> a_dclk_p_l<7> A_DOUT<9> A_DIN<9> a_rclk_n_l<6> a_rclk_n_l<7> a_rclk_p_l<6> a_rclk_p_l<7> a_tieh<9> a_wclk_n_l<6> a_wclk_n_l<7> a_wclk_p_l<6> a_wclk_p_l<7> VDD! VSS! / RM_IHPSG13_1024x32_c2_1P_COLCTRL2 +XCOLCTRL<5> a_addr_dec_l<3> a_addr_dec_l<2> a_addr_dec_l<1> a_addr_dec_l<0> A_BIST_BM<10> A_BIST_DIN<10> A_BIST_EN a_blc_l<23> a_blc_l<22> a_blc_l<21> a_blc_l<20> a_blt_l<23> a_blt_l<22> a_blt_l<21> a_blt_l<20> A_BM<10> a_dclk_n_l<5> a_dclk_n_l<6> a_dclk_p_l<5> a_dclk_p_l<6> A_DOUT<10> A_DIN<10> a_rclk_n_l<5> a_rclk_n_l<6> a_rclk_p_l<5> a_rclk_p_l<6> a_tieh<10> a_wclk_n_l<5> a_wclk_n_l<6> a_wclk_p_l<5> a_wclk_p_l<6> VDD! VSS! / RM_IHPSG13_1024x32_c2_1P_COLCTRL2 +XCOLCTRL<4> a_addr_dec_l<3> a_addr_dec_l<2> a_addr_dec_l<1> a_addr_dec_l<0> A_BIST_BM<11> A_BIST_DIN<11> A_BIST_EN a_blc_l<19> a_blc_l<18> a_blc_l<17> a_blc_l<16> a_blt_l<19> a_blt_l<18> a_blt_l<17> a_blt_l<16> A_BM<11> a_dclk_n_l<4> a_dclk_n_l<5> a_dclk_p_l<4> a_dclk_p_l<5> A_DOUT<11> A_DIN<11> a_rclk_n_l<4> a_rclk_n_l<5> a_rclk_p_l<4> a_rclk_p_l<5> a_tieh<11> a_wclk_n_l<4> a_wclk_n_l<5> a_wclk_p_l<4> a_wclk_p_l<5> VDD! VSS! / RM_IHPSG13_1024x32_c2_1P_COLCTRL2 +XCOLCTRL<3> a_addr_dec_l<3> a_addr_dec_l<2> a_addr_dec_l<1> a_addr_dec_l<0> A_BIST_BM<12> A_BIST_DIN<12> A_BIST_EN a_blc_l<15> a_blc_l<14> a_blc_l<13> a_blc_l<12> a_blt_l<15> a_blt_l<14> a_blt_l<13> a_blt_l<12> A_BM<12> a_dclk_n_l<3> a_dclk_n_l<4> a_dclk_p_l<3> a_dclk_p_l<4> A_DOUT<12> A_DIN<12> a_rclk_n_l<3> a_rclk_n_l<4> a_rclk_p_l<3> a_rclk_p_l<4> a_tieh<12> a_wclk_n_l<3> a_wclk_n_l<4> a_wclk_p_l<3> a_wclk_p_l<4> VDD! VSS! / RM_IHPSG13_1024x32_c2_1P_COLCTRL2 +XCOLCTRL<2> a_addr_dec_l<3> a_addr_dec_l<2> a_addr_dec_l<1> a_addr_dec_l<0> A_BIST_BM<13> A_BIST_DIN<13> A_BIST_EN a_blc_l<11> a_blc_l<10> a_blc_l<9> a_blc_l<8> a_blt_l<11> a_blt_l<10> a_blt_l<9> a_blt_l<8> A_BM<13> a_dclk_n_l<2> a_dclk_n_l<3> a_dclk_p_l<2> a_dclk_p_l<3> A_DOUT<13> A_DIN<13> a_rclk_n_l<2> a_rclk_n_l<3> a_rclk_p_l<2> a_rclk_p_l<3> a_tieh<13> a_wclk_n_l<2> a_wclk_n_l<3> a_wclk_p_l<2> a_wclk_p_l<3> VDD! VSS! / RM_IHPSG13_1024x32_c2_1P_COLCTRL2 +XCOLCTRL<1> a_addr_dec_l<3> a_addr_dec_l<2> a_addr_dec_l<1> a_addr_dec_l<0> A_BIST_BM<14> A_BIST_DIN<14> A_BIST_EN a_blc_l<7> a_blc_l<6> a_blc_l<5> a_blc_l<4> a_blt_l<7> a_blt_l<6> a_blt_l<5> a_blt_l<4> A_BM<14> a_dclk_n_l<1> a_dclk_n_l<2> a_dclk_p_l<1> a_dclk_p_l<2> A_DOUT<14> A_DIN<14> a_rclk_n_l<1> a_rclk_n_l<2> a_rclk_p_l<1> a_rclk_p_l<2> a_tieh<14> a_wclk_n_l<1> a_wclk_n_l<2> a_wclk_p_l<1> a_wclk_p_l<2> VDD! VSS! / RM_IHPSG13_1024x32_c2_1P_COLCTRL2 +XCOLCTRL<0> a_addr_dec_l<3> a_addr_dec_l<2> a_addr_dec_l<1> a_addr_dec_l<0> A_BIST_BM<15> A_BIST_DIN<15> A_BIST_EN a_blc_l<3> a_blc_l<2> a_blc_l<1> a_blc_l<0> a_blt_l<3> a_blt_l<2> a_blt_l<1> a_blt_l<0> A_BM<15> a_dclk_n_l<0> a_dclk_n_l<1> a_dclk_p_l<0> a_dclk_p_l<1> A_DOUT<15> A_DIN<15> a_rclk_n_l<0> a_rclk_n_l<1> a_rclk_p_l<0> a_rclk_p_l<1> a_tieh<15> a_wclk_n_l<0> a_wclk_n_l<1> a_wclk_p_l<0> a_wclk_p_l<1> VDD! VSS! / RM_IHPSG13_1024x32_c2_1P_COLCTRL2 + + +XDRVFILL4<1> VDD! VSS! / RM_IHPSG13_1024x32_c2_1P_COLDRV13_FILL4 +XDRVFILL4<2> VDD! VSS! / RM_IHPSG13_1024x32_c2_1P_COLDRV13_FILL4 +XCOLFILL4<1> VDD! VSS! / RM_IHPSG13_1024x32_c2_1P_COLDRV13_FILL4C2 +XCOLFILL4<2> VDD! VSS! / RM_IHPSG13_1024x32_c2_1P_COLDRV13_FILL4C2 +XCOLFILL4<3> VDD! VSS! / RM_IHPSG13_1024x32_c2_1P_COLDRV13_FILL4C2 +XCOLFILL4<4> VDD! VSS! / RM_IHPSG13_1024x32_c2_1P_COLDRV13_FILL4C2 +XCOLFILL4<5> VDD! VSS! / RM_IHPSG13_1024x32_c2_1P_COLDRV13_FILL4C2 +XCOLFILL4<6> VDD! VSS! / RM_IHPSG13_1024x32_c2_1P_COLDRV13_FILL4C2 +.ENDS diff --git a/flow/platforms/ihp-sg13g2/cdl/RM_IHPSG13_1P_256x16_c2_bm_bist.cdl b/flow/platforms/ihp-sg13g2/cdl/RM_IHPSG13_1P_256x16_c2_bm_bist.cdl new file mode 100644 index 0000000000..f2c1907df5 --- /dev/null +++ b/flow/platforms/ihp-sg13g2/cdl/RM_IHPSG13_1P_256x16_c2_bm_bist.cdl @@ -0,0 +1,6331 @@ +* ------------------------------------------------------ +* +* Copyright 2025 IHP PDK Authors +* +* Licensed under the Apache License, Version 2.0 (the "License"); +* you may not use this file except in compliance with the License. +* You may obtain a copy of the License at +* +* https://www.apache.org/licenses/LICENSE-2.0 +* +* Unless required by applicable law or agreed to in writing, software +* distributed under the License is distributed on an "AS IS" BASIS, +* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +* See the License for the specific language governing permissions and +* limitations under the License. +* +* Generated on Wed Aug 27 12:14:51 2025 +* +* ------------------------------------------------------ + +.SUBCKT RM_IHPSG13_256x16_c2_1P_BITKIT_CORNER NW PW VDD VSS +.ENDS +.SUBCKT RM_IHPSG13_256x16_c2_1P_BITKIT_16x2_CORNER VDD_CORE VSS +XI16 VDD_CORE VSS VDD_CORE VSS / ++ RM_IHPSG13_256x16_c2_1P_BITKIT_CORNER +.ENDS +.SUBCKT RM_IHPSG13_256x16_c2_1P_BITKIT_EDGE_LR LWL NW PW VDD VSS +MN1 VSS LWL VSS VSS sg13_lv_nmos m=1 w=300.0n l=130.00n ng=1 nrd=0 nrs=0 +MN0 VSS net9 VSS VSS sg13_lv_nmos m=1 w=300.0n l=130.00n ng=1 nrd=0 nrs=0 +.ENDS +.SUBCKT RM_IHPSG13_256x16_c2_1P_BITKIT_16x2_EDGE_LR A_WL<15> A_WL<14> A_WL<13> A_WL<12> ++ A_WL<11> A_WL<10> A_WL<9> A_WL<8> A_WL<7> A_WL<6> A_WL<5> A_WL<4> A_WL<3> ++ A_WL<2> A_WL<1> A_WL<0> VDD_CORE VSS +XI0<15> A_WL<15> VDD_CORE VSS VDD_CORE VSS / ++ RM_IHPSG13_256x16_c2_1P_BITKIT_EDGE_LR +XI0<14> A_WL<14> VDD_CORE VSS VDD_CORE VSS / ++ RM_IHPSG13_256x16_c2_1P_BITKIT_EDGE_LR +XI0<13> A_WL<13> VDD_CORE VSS VDD_CORE VSS / ++ RM_IHPSG13_256x16_c2_1P_BITKIT_EDGE_LR +XI0<12> A_WL<12> VDD_CORE VSS VDD_CORE VSS / ++ RM_IHPSG13_256x16_c2_1P_BITKIT_EDGE_LR +XI0<11> A_WL<11> VDD_CORE VSS VDD_CORE VSS / ++ RM_IHPSG13_256x16_c2_1P_BITKIT_EDGE_LR +XI0<10> A_WL<10> VDD_CORE VSS VDD_CORE VSS / ++ RM_IHPSG13_256x16_c2_1P_BITKIT_EDGE_LR +XI0<9> A_WL<9> VDD_CORE VSS VDD_CORE VSS / ++ RM_IHPSG13_256x16_c2_1P_BITKIT_EDGE_LR +XI0<8> A_WL<8> VDD_CORE VSS VDD_CORE VSS / ++ RM_IHPSG13_256x16_c2_1P_BITKIT_EDGE_LR +XI0<7> A_WL<7> VDD_CORE VSS VDD_CORE VSS / ++ RM_IHPSG13_256x16_c2_1P_BITKIT_EDGE_LR +XI0<6> A_WL<6> VDD_CORE VSS VDD_CORE VSS / ++ RM_IHPSG13_256x16_c2_1P_BITKIT_EDGE_LR +XI0<5> A_WL<5> VDD_CORE VSS VDD_CORE VSS / ++ RM_IHPSG13_256x16_c2_1P_BITKIT_EDGE_LR +XI0<4> A_WL<4> VDD_CORE VSS VDD_CORE VSS / ++ RM_IHPSG13_256x16_c2_1P_BITKIT_EDGE_LR +XI0<3> A_WL<3> VDD_CORE VSS VDD_CORE VSS / ++ RM_IHPSG13_256x16_c2_1P_BITKIT_EDGE_LR +XI0<2> A_WL<2> VDD_CORE VSS VDD_CORE VSS / ++ RM_IHPSG13_256x16_c2_1P_BITKIT_EDGE_LR +XI0<1> A_WL<1> VDD_CORE VSS VDD_CORE VSS / ++ RM_IHPSG13_256x16_c2_1P_BITKIT_EDGE_LR +XI0<0> A_WL<0> VDD_CORE VSS VDD_CORE VSS / ++ RM_IHPSG13_256x16_c2_1P_BITKIT_EDGE_LR +.ENDS +.SUBCKT RM_IHPSG13_256x16_c2_1P_BITKIT_CELL BLC_BOT BLC_TOP BLT_BOT BLT_TOP LWL NW PW ++ RWL VDD VSS +MN0 NC NT VSS PW sg13_lv_nmos m=1 w=300.0n l=130.00n ng=1 nrd=0 nrs=0 +MN1 NT NC VSS PW sg13_lv_nmos m=1 w=300.0n l=130.00n ng=1 nrd=0 nrs=0 +MN3 NC RWL BLC_TOP PW sg13_lv_nmos m=1 w=300.0n l=130.00n ng=1 nrd=0 nrs=0 +MN2 BLT_BOT LWL NT PW sg13_lv_nmos m=1 w=300.0n l=130.00n ng=1 nrd=0 nrs=0 +MP1 NT NC VDD NW sg13_lv_pmos m=1 w=150.00n l=130.00n ng=1 nrd=0 nrs=0 +MP0 NC NT VDD NW sg13_lv_pmos m=1 w=150.00n l=130.00n ng=1 nrd=0 nrs=0 +R1 BLC_BOT BLC_TOP lvsres w=2.6e-07 l=6e-07 +R0 BLT_BOT BLT_TOP lvsres w=2.6e-07 l=6e-07 +R2 RWL LWL lvsres w=2.6e-07 l=6e-07 +.ENDS +.SUBCKT RM_IHPSG13_256x16_c2_1P_BITKIT_16x2_SRAM A_BLC_BOT<1> A_BLC_BOT<0> A_BLC_TOP<1> ++ A_BLC_TOP<0> A_BLT_BOT<1> A_BLT_BOT<0> A_BLT_TOP<1> A_BLT_TOP<0> A_LWL<15> ++ A_LWL<14> A_LWL<13> A_LWL<12> A_LWL<11> A_LWL<10> A_LWL<9> A_LWL<8> A_LWL<7> ++ A_LWL<6> A_LWL<5> A_LWL<4> A_LWL<3> A_LWL<2> A_LWL<1> A_LWL<0> A_RWL<15> ++ A_RWL<14> A_RWL<13> A_RWL<12> A_RWL<11> A_RWL<10> A_RWL<9> A_RWL<8> A_RWL<7> ++ A_RWL<6> A_RWL<5> A_RWL<4> A_RWL<3> A_RWL<2> A_RWL<1> A_RWL<0> VDD_CORE ++ VSS +XCELL<31> A_BLC_TOP<1> A_RBLC<15> A_BLT_TOP<1> A_RBLT<15> A_RWL<15> ++ VDD_CORE VSS A_XWL<15> VDD_CORE VSS / ++ RM_IHPSG13_256x16_c2_1P_BITKIT_CELL +XCELL<30> A_RBLC<14> A_RBLC<15> A_RBLT<14> A_RBLT<15> A_RWL<14> VDD_CORE ++ VSS A_XWL<14> VDD_CORE VSS / RM_IHPSG13_256x16_c2_1P_BITKIT_CELL +XCELL<29> A_RBLC<14> A_RBLC<13> A_RBLT<14> A_RBLT<13> A_RWL<13> VDD_CORE ++ VSS A_XWL<13> VDD_CORE VSS / RM_IHPSG13_256x16_c2_1P_BITKIT_CELL +XCELL<28> A_RBLC<12> A_RBLC<13> A_RBLT<12> A_RBLT<13> A_RWL<12> VDD_CORE ++ VSS A_XWL<12> VDD_CORE VSS / RM_IHPSG13_256x16_c2_1P_BITKIT_CELL +XCELL<27> A_RBLC<12> A_RBLC<11> A_RBLT<12> A_RBLT<11> A_RWL<11> VDD_CORE ++ VSS A_XWL<11> VDD_CORE VSS / RM_IHPSG13_256x16_c2_1P_BITKIT_CELL +XCELL<26> A_RBLC<10> A_RBLC<11> A_RBLT<10> A_RBLT<11> A_RWL<10> VDD_CORE ++ VSS A_XWL<10> VDD_CORE VSS / RM_IHPSG13_256x16_c2_1P_BITKIT_CELL +XCELL<25> A_RBLC<10> A_RBLC<9> A_RBLT<10> A_RBLT<9> A_RWL<9> VDD_CORE ++ VSS A_XWL<9> VDD_CORE VSS / RM_IHPSG13_256x16_c2_1P_BITKIT_CELL +XCELL<24> A_RBLC<8> A_RBLC<9> A_RBLT<8> A_RBLT<9> A_RWL<8> VDD_CORE ++ VSS A_XWL<8> VDD_CORE VSS / RM_IHPSG13_256x16_c2_1P_BITKIT_CELL +XCELL<23> A_RBLC<8> A_RBLC<7> A_RBLT<8> A_RBLT<7> A_RWL<7> VDD_CORE ++ VSS A_XWL<7> VDD_CORE VSS / RM_IHPSG13_256x16_c2_1P_BITKIT_CELL +XCELL<22> A_RBLC<6> A_RBLC<7> A_RBLT<6> A_RBLT<7> A_RWL<6> VDD_CORE ++ VSS A_XWL<6> VDD_CORE VSS / RM_IHPSG13_256x16_c2_1P_BITKIT_CELL +XCELL<21> A_RBLC<6> A_RBLC<5> A_RBLT<6> A_RBLT<5> A_RWL<5> VDD_CORE ++ VSS A_XWL<5> VDD_CORE VSS / RM_IHPSG13_256x16_c2_1P_BITKIT_CELL +XCELL<20> A_RBLC<4> A_RBLC<5> A_RBLT<4> A_RBLT<5> A_RWL<4> VDD_CORE ++ VSS A_XWL<4> VDD_CORE VSS / RM_IHPSG13_256x16_c2_1P_BITKIT_CELL +XCELL<19> A_RBLC<4> A_RBLC<3> A_RBLT<4> A_RBLT<3> A_RWL<3> VDD_CORE ++ VSS A_XWL<3> VDD_CORE VSS / RM_IHPSG13_256x16_c2_1P_BITKIT_CELL +XCELL<18> A_RBLC<2> A_RBLC<3> A_RBLT<2> A_RBLT<3> A_RWL<2> VDD_CORE ++ VSS A_XWL<2> VDD_CORE VSS / RM_IHPSG13_256x16_c2_1P_BITKIT_CELL +XCELL<17> A_RBLC<2> A_RBLC<1> A_RBLT<2> A_RBLT<1> A_RWL<1> VDD_CORE ++ VSS A_XWL<1> VDD_CORE VSS / RM_IHPSG13_256x16_c2_1P_BITKIT_CELL +XCELL<16> A_BLC_BOT<1> A_RBLC<1> A_BLT_BOT<1> A_RBLT<1> A_RWL<0> VDD_CORE ++ VSS A_XWL<0> VDD_CORE VSS / RM_IHPSG13_256x16_c2_1P_BITKIT_CELL +XCELL<15> A_BLC_TOP<0> A_LBLC<15> A_BLT_TOP<0> A_LBLT<15> A_LWL<15> ++ VDD_CORE VSS A_XWL<15> VDD_CORE VSS / ++ RM_IHPSG13_256x16_c2_1P_BITKIT_CELL +XCELL<14> A_LBLC<14> A_LBLC<15> A_LBLT<14> A_LBLT<15> A_LWL<14> VDD_CORE ++ VSS A_XWL<14> VDD_CORE VSS / RM_IHPSG13_256x16_c2_1P_BITKIT_CELL +XCELL<13> A_LBLC<14> A_LBLC<13> A_LBLT<14> A_LBLT<13> A_LWL<13> VDD_CORE ++ VSS A_XWL<13> VDD_CORE VSS / RM_IHPSG13_256x16_c2_1P_BITKIT_CELL +XCELL<12> A_LBLC<12> A_LBLC<13> A_LBLT<12> A_LBLT<13> A_LWL<12> VDD_CORE ++ VSS A_XWL<12> VDD_CORE VSS / RM_IHPSG13_256x16_c2_1P_BITKIT_CELL +XCELL<11> A_LBLC<12> A_LBLC<11> A_LBLT<12> A_LBLT<11> A_LWL<11> VDD_CORE ++ VSS A_XWL<11> VDD_CORE VSS / RM_IHPSG13_256x16_c2_1P_BITKIT_CELL +XCELL<10> A_LBLC<10> A_LBLC<11> A_LBLT<10> A_LBLT<11> A_LWL<10> VDD_CORE ++ VSS A_XWL<10> VDD_CORE VSS / RM_IHPSG13_256x16_c2_1P_BITKIT_CELL +XCELL<9> A_LBLC<10> A_LBLC<9> A_LBLT<10> A_LBLT<9> A_LWL<9> VDD_CORE ++ VSS A_XWL<9> VDD_CORE VSS / RM_IHPSG13_256x16_c2_1P_BITKIT_CELL +XCELL<8> A_LBLC<8> A_LBLC<9> A_LBLT<8> A_LBLT<9> A_LWL<8> VDD_CORE ++ VSS A_XWL<8> VDD_CORE VSS / RM_IHPSG13_256x16_c2_1P_BITKIT_CELL +XCELL<7> A_LBLC<8> A_LBLC<7> A_LBLT<8> A_LBLT<7> A_LWL<7> VDD_CORE ++ VSS A_XWL<7> VDD_CORE VSS / RM_IHPSG13_256x16_c2_1P_BITKIT_CELL +XCELL<6> A_LBLC<6> A_LBLC<7> A_LBLT<6> A_LBLT<7> A_LWL<6> VDD_CORE ++ VSS A_XWL<6> VDD_CORE VSS / RM_IHPSG13_256x16_c2_1P_BITKIT_CELL +XCELL<5> A_LBLC<6> A_LBLC<5> A_LBLT<6> A_LBLT<5> A_LWL<5> VDD_CORE ++ VSS A_XWL<5> VDD_CORE VSS / RM_IHPSG13_256x16_c2_1P_BITKIT_CELL +XCELL<4> A_LBLC<4> A_LBLC<5> A_LBLT<4> A_LBLT<5> A_LWL<4> VDD_CORE ++ VSS A_XWL<4> VDD_CORE VSS / RM_IHPSG13_256x16_c2_1P_BITKIT_CELL +XCELL<3> A_LBLC<4> A_LBLC<3> A_LBLT<4> A_LBLT<3> A_LWL<3> VDD_CORE ++ VSS A_XWL<3> VDD_CORE VSS / RM_IHPSG13_256x16_c2_1P_BITKIT_CELL +XCELL<2> A_LBLC<2> A_LBLC<3> A_LBLT<2> A_LBLT<3> A_LWL<2> VDD_CORE ++ VSS A_XWL<2> VDD_CORE VSS / RM_IHPSG13_256x16_c2_1P_BITKIT_CELL +XCELL<1> A_LBLC<2> A_LBLC<1> A_LBLT<2> A_LBLT<1> A_LWL<1> VDD_CORE ++ VSS A_XWL<1> VDD_CORE VSS / RM_IHPSG13_256x16_c2_1P_BITKIT_CELL +XCELL<0> A_BLC_BOT<0> A_LBLC<1> A_BLT_BOT<0> A_LBLT<1> A_LWL<0> VDD_CORE ++ VSS A_XWL<0> VDD_CORE VSS / RM_IHPSG13_256x16_c2_1P_BITKIT_CELL +.ENDS +.SUBCKT RM_IHPSG13_256x16_c2_1P_BITKIT_EDGE_TB BLC BLT NW PW VDD VSS +.ENDS +.SUBCKT RM_IHPSG13_256x16_c2_1P_BITKIT_16x2_EDGE_TB A_BLC<1> A_BLC<0> A_BLT<1> A_BLT<0> ++ VDD_CORE VSS +XEDGE<1> A_BLC<1> A_BLT<1> VDD_CORE VSS VDD_CORE VSS ++ / RM_IHPSG13_256x16_c2_1P_BITKIT_EDGE_TB +XEDGE<0> A_BLC<0> A_BLT<0> VDD_CORE VSS VDD_CORE VSS ++ / RM_IHPSG13_256x16_c2_1P_BITKIT_EDGE_TB +.ENDS + +.SUBCKT RSC_IHPSG13_CBUFX4 A Z VDD VSS +MN0 net9 A VSS VSS sg13_lv_nmos m=1 w=705.000n l=130.00n ng=1 nrd=0 ++ nrs=0 +MN1 Z net9 VSS VSS sg13_lv_nmos m=1 w=1.41u l=130.00n ng=2 nrd=0 nrs=0 +MP0 net9 A VDD VDD sg13_lv_pmos m=1 w=1.62u l=130.00n ng=1 nrd=0 nrs=0 +MP1 Z net9 VDD VDD sg13_lv_pmos m=1 w=3.24u l=130.00n ng=2 nrd=0 nrs=0 +.ENDS +.SUBCKT RM_IHPSG13_256x16_c2_1P_COLDRV13X4 ADDR_COL_I<1> ADDR_COL_I<0> ADDR_COL_O<1> ++ ADDR_COL_O<0> ADDR_DEC_I<7> ADDR_DEC_I<6> ADDR_DEC_I<5> ADDR_DEC_I<4> ++ ADDR_DEC_I<3> ADDR_DEC_I<2> ADDR_DEC_I<1> ADDR_DEC_I<0> ADDR_DEC_O<7> ++ ADDR_DEC_O<6> ADDR_DEC_O<5> ADDR_DEC_O<4> ADDR_DEC_O<3> ADDR_DEC_O<2> ++ ADDR_DEC_O<1> ADDR_DEC_O<0> DCLK_I DCLK_O RCLK_I RCLK_O WCLK_I WCLK_O ++ VDD VSS +XADDR_COL_DRV<1> ADDR_COL_I<1> ADDR_COL_O<1> VDD VSS / ++ RSC_IHPSG13_CBUFX4 +XADDR_COL_DRV<0> ADDR_COL_I<0> ADDR_COL_O<0> VDD VSS / ++ RSC_IHPSG13_CBUFX4 +XADDR_DEC_DRV<7> ADDR_DEC_I<7> ADDR_DEC_O<7> VDD VSS / ++ RSC_IHPSG13_CBUFX4 +XADDR_DEC_DRV<6> ADDR_DEC_I<6> ADDR_DEC_O<6> VDD VSS / ++ RSC_IHPSG13_CBUFX4 +XADDR_DEC_DRV<5> ADDR_DEC_I<5> ADDR_DEC_O<5> VDD VSS / ++ RSC_IHPSG13_CBUFX4 +XADDR_DEC_DRV<4> ADDR_DEC_I<4> ADDR_DEC_O<4> VDD VSS / ++ RSC_IHPSG13_CBUFX4 +XADDR_DEC_DRV<3> ADDR_DEC_I<3> ADDR_DEC_O<3> VDD VSS / ++ RSC_IHPSG13_CBUFX4 +XADDR_DEC_DRV<2> ADDR_DEC_I<2> ADDR_DEC_O<2> VDD VSS / ++ RSC_IHPSG13_CBUFX4 +XADDR_DEC_DRV<1> ADDR_DEC_I<1> ADDR_DEC_O<1> VDD VSS / ++ RSC_IHPSG13_CBUFX4 +XADDR_DEC_DRV<0> ADDR_DEC_I<0> ADDR_DEC_O<0> VDD VSS / ++ RSC_IHPSG13_CBUFX4 +XDCLK_DRV DCLK_I DCLK_O VDD VSS / RSC_IHPSG13_CBUFX4 +XRCLK_DRV RCLK_I RCLK_O VDD VSS / RSC_IHPSG13_CBUFX4 +XWCLK_DRV WCLK_I WCLK_O VDD VSS / RSC_IHPSG13_CBUFX4 +.ENDS +.SUBCKT RSC_IHPSG13_WLDRVX4 A Z VDD VSS +MN1 Z net6 VSS VSS sg13_lv_nmos m=1 w=705.000n l=130.00n ng=1 nrd=0 ++ nrs=0 +MN0 net6 A VSS VSS sg13_lv_nmos m=1 w=900.0n l=130.00n ng=1 nrd=0 nrs=0 +MP1 Z net6 VDD VDD sg13_lv_pmos m=1 w=3.24u l=130.00n ng=2 nrd=0 nrs=0 +MP0 net6 A VDD VDD sg13_lv_pmos m=1 w=900.0n l=130.00n ng=1 nrd=0 nrs=0 +.ENDS +.SUBCKT RM_IHPSG13_256x16_c2_1P_WLDRV16X4 A<15> A<14> A<13> A<12> A<11> A<10> A<9> A<8> ++ A<7> A<6> A<5> A<4> A<3> A<2> A<1> A<0> Z<15> Z<14> Z<13> Z<12> Z<11> Z<10> ++ Z<9> Z<8> Z<7> Z<6> Z<5> Z<4> Z<3> Z<2> Z<1> Z<0> VDD VSS +XBUF<15> A<15> Z<15> VDD VSS / RSC_IHPSG13_WLDRVX4 +XBUF<14> A<14> Z<14> VDD VSS / RSC_IHPSG13_WLDRVX4 +XBUF<13> A<13> Z<13> VDD VSS / RSC_IHPSG13_WLDRVX4 +XBUF<12> A<12> Z<12> VDD VSS / RSC_IHPSG13_WLDRVX4 +XBUF<11> A<11> Z<11> VDD VSS / RSC_IHPSG13_WLDRVX4 +XBUF<10> A<10> Z<10> VDD VSS / RSC_IHPSG13_WLDRVX4 +XBUF<9> A<9> Z<9> VDD VSS / RSC_IHPSG13_WLDRVX4 +XBUF<8> A<8> Z<8> VDD VSS / RSC_IHPSG13_WLDRVX4 +XBUF<7> A<7> Z<7> VDD VSS / RSC_IHPSG13_WLDRVX4 +XBUF<6> A<6> Z<6> VDD VSS / RSC_IHPSG13_WLDRVX4 +XBUF<5> A<5> Z<5> VDD VSS / RSC_IHPSG13_WLDRVX4 +XBUF<4> A<4> Z<4> VDD VSS / RSC_IHPSG13_WLDRVX4 +XBUF<3> A<3> Z<3> VDD VSS / RSC_IHPSG13_WLDRVX4 +XBUF<2> A<2> Z<2> VDD VSS / RSC_IHPSG13_WLDRVX4 +XBUF<1> A<1> Z<1> VDD VSS / RSC_IHPSG13_WLDRVX4 +XBUF<0> A<0> Z<0> VDD VSS / RSC_IHPSG13_WLDRVX4 +.ENDS +.SUBCKT RSC_IHPSG13_FILLCAP8 VDD VSS +MN0 vss_r vdd_r VSS VSS sg13_lv_nmos m=1 w=4.98u l=130.00n ng=6 nrd=0 ++ nrs=0 +MP0 vdd_r vss_r VDD VDD sg13_lv_pmos m=1 w=6.48u l=385.000n ng=4 nrd=0 ++ nrs=0 +.ENDS +.SUBCKT RSC_IHPSG13_LHPQX2 CP D Q VDD VSS +MN3 QIN CPN net14 VSS sg13_lv_nmos m=1 w=480.00n l=130.00n ng=1 nrd=0 nrs=0 +MN2 net14 net10 VSS VSS sg13_lv_nmos m=1 w=480.00n l=130.00n ng=1 ++ nrd=0 nrs=0 +MN5 net21 D VSS VSS sg13_lv_nmos m=1 w=870.00n l=130.00n ng=1 nrd=0 ++ nrs=0 +MN6 QIN CP net21 VSS sg13_lv_nmos m=1 w=870.00n l=130.00n ng=1 nrd=0 nrs=0 +MN1 net10 QIN VSS VSS sg13_lv_nmos m=1 w=480.00n l=130.00n ng=1 nrd=0 ++ nrs=0 +MN0 CPN CP VSS VSS sg13_lv_nmos m=1 w=480.00n l=130.00n ng=1 nrd=0 ++ nrs=0 +MN4 Q QIN VSS VSS sg13_lv_nmos m=1 w=980.00n l=130.00n ng=1 nrd=0 nrs=0 +MP2 QIN CP net16 VDD sg13_lv_pmos m=1 w=480.00n l=130.00n ng=1 nrd=0 nrs=0 +MP0 CPN CP VDD VDD sg13_lv_pmos m=1 w=480.00n l=130.00n ng=1 nrd=0 ++ nrs=0 +MP4 Q QIN VDD VDD sg13_lv_pmos m=1 w=1.62u l=130.00n ng=1 nrd=0 nrs=0 +MP3 net10 QIN VDD VDD sg13_lv_pmos m=1 w=480.00n l=130.00n ng=1 nrd=0 ++ nrs=0 +MP1 net16 net10 VDD VDD sg13_lv_pmos m=1 w=480.00n l=130.00n ng=1 ++ nrd=0 nrs=0 +MP6 QIN CPN net20 VDD sg13_lv_pmos m=1 w=975.000n l=130.00n ng=1 nrd=0 ++ nrs=0 +MP5 net20 D VDD VDD sg13_lv_pmos m=1 w=975.000n l=130.00n ng=1 nrd=0 ++ nrs=0 +.ENDS +.SUBCKT RSC_IHPSG13_NAND2X2 A B Z VDD VSS +MP1 Z B VDD VDD sg13_lv_pmos m=1 w=1.62u l=130.00n ng=1 nrd=0 nrs=0 +MP0 Z A VDD VDD sg13_lv_pmos m=1 w=1.62u l=130.00n ng=1 nrd=0 nrs=0 +MN0 Z B net7 VSS sg13_lv_nmos m=1 w=980.00n l=130.00n ng=1 nrd=0 nrs=0 +MN1 net7 A VSS VSS sg13_lv_nmos m=1 w=980.00n l=130.00n ng=1 nrd=0 ++ nrs=0 +.ENDS +.SUBCKT RSC_IHPSG13_CINVX4 A Z VDD VSS +MN0 Z A VSS VSS sg13_lv_nmos m=1 w=1.41u l=130.00n ng=2 nrd=0 nrs=0 +MP0 Z A VDD VDD sg13_lv_pmos m=1 w=3.24u l=130.00n ng=2 nrd=0 nrs=0 +.ENDS +.SUBCKT RSC_IHPSG13_CINVX2 A Z VDD VSS +MN0 Z A VSS VSS sg13_lv_nmos m=1 w=705.000n l=130.00n ng=1 nrd=0 nrs=0 +MP0 Z A VDD VDD sg13_lv_pmos m=1 w=1.62u l=130.00n ng=1 nrd=0 nrs=0 +.ENDS +.SUBCKT RSC_IHPSG13_INVX2 A Z VDD VSS +MN0 Z A VSS VSS sg13_lv_nmos m=1 w=980.00n l=130.00n ng=1 nrd=0 nrs=0 +MP0 Z A VDD VDD sg13_lv_pmos m=1 w=1.62u l=130.00n ng=1 nrd=0 nrs=0 +.ENDS +.SUBCKT RSC_IHPSG13_NAND3X2 A B C Z VDD VSS +MP2 Z A VDD VDD sg13_lv_pmos m=1 w=1.62u l=130.00n ng=1 nrd=0 nrs=0 +MP1 Z B VDD VDD sg13_lv_pmos m=1 w=1.62u l=130.00n ng=1 nrd=0 nrs=0 +MP0 Z C VDD VDD sg13_lv_pmos m=1 w=1.62u l=130.00n ng=1 nrd=0 nrs=0 +MN1 net12 B net16 VSS sg13_lv_nmos m=1 w=980.00n l=130.00n ng=1 nrd=0 nrs=0 +MN0 Z C net12 VSS sg13_lv_nmos m=1 w=980.00n l=130.00n ng=1 nrd=0 nrs=0 +MN2 net16 A VSS VSS sg13_lv_nmos m=1 w=980.00n l=130.00n ng=1 nrd=0 ++ nrs=0 +.ENDS +.SUBCKT RSC_IHPSG13_NOR3X2 A B C Z VDD VSS +MP0 net13 A VDD VDD sg13_lv_pmos m=1 w=1.62u l=130.00n ng=1 nrd=0 nrs=0 +MP2 Z C net10 VDD sg13_lv_pmos m=1 w=1.62u l=130.00n ng=1 nrd=0 nrs=0 +MP1 net10 B net13 VDD sg13_lv_pmos m=1 w=1.62u l=130.00n ng=1 nrd=0 nrs=0 +MN1 Z B VSS VSS sg13_lv_nmos m=1 w=875.000n l=130.00n ng=1 nrd=0 nrs=0 +MN0 Z C VSS VSS sg13_lv_nmos m=1 w=875.000n l=130.00n ng=1 nrd=0 nrs=0 +MN2 Z A VSS VSS sg13_lv_nmos m=1 w=875.000n l=130.00n ng=1 nrd=0 nrs=0 +.ENDS +.SUBCKT RSC_IHPSG13_FILLCAP4 VDD VSS +MN0 vss_r vdd_r VSS VSS sg13_lv_nmos m=1 w=2.49u l=130.00n ng=3 nrd=0 ++ nrs=0 +MP0 vdd_r vss_r VDD VDD sg13_lv_pmos m=1 w=3.24u l=385.000n ng=2 nrd=0 ++ nrs=0 +.ENDS +.SUBCKT RSC_IHPSG13_MET2RES A B +R0 B A lvsres w=2.6e-07 l=6e-07 +.ENDS +.SUBCKT RM_IHPSG13_256x16_c2_1P_DEC04 ADDR<3> ADDR<2> ADDR<1> ADDR<0> CS ECLK_H_BOT ++ ECLK_H_TOP ECLK_L_BOT ECLK_L_TOP WL<15> WL<14> WL<13> WL<12> WL<11> WL<10> ++ WL<9> WL<8> WL<7> WL<6> WL<5> WL<4> WL<3> WL<2> WL<1> WL<0> VDD VSS +XLATCH<3> CS ADDR<3> PADR<3> VDD VSS / RSC_IHPSG13_LHPQX2 +XLATCH<2> CS ADDR<2> PADR<2> VDD VSS / RSC_IHPSG13_LHPQX2 +XLATCH<1> CS ADDR<1> PADR<1> VDD VSS / RSC_IHPSG13_LHPQX2 +XLATCH<0> CS ADDR<0> PADR<0> VDD VSS / RSC_IHPSG13_LHPQX2 +XI0<3> PADR<1> PADR<0> sel01<3> VDD VSS / RSC_IHPSG13_NAND2X2 +XI0<2> PADR<1> NADR<0> sel01<2> VDD VSS / RSC_IHPSG13_NAND2X2 +XI0<1> NADR<1> PADR<0> sel01<1> VDD VSS / RSC_IHPSG13_NAND2X2 +XI0<0> NADR<1> NADR<0> sel01<0> VDD VSS / RSC_IHPSG13_NAND2X2 +XI4 ECLK_L_BOT EN VDD VSS / RSC_IHPSG13_CINVX4 +XI5 ECLK_H_BOT ECLK_L_BOT VDD VSS / RSC_IHPSG13_CINVX2 +XI3<3> PADR<3> NADR<3> VDD VSS / RSC_IHPSG13_INVX2 +XI3<2> PADR<2> NADR<2> VDD VSS / RSC_IHPSG13_INVX2 +XI3<1> PADR<1> NADR<1> VDD VSS / RSC_IHPSG13_INVX2 +XI3<0> PADR<0> NADR<0> VDD VSS / RSC_IHPSG13_INVX2 +XI1<3> PADR<2> PADR<3> CS sel23<3> VDD VSS / RSC_IHPSG13_NAND3X2 +XI1<2> NADR<2> PADR<3> CS sel23<2> VDD VSS / RSC_IHPSG13_NAND3X2 +XI1<1> PADR<2> NADR<3> CS sel23<1> VDD VSS / RSC_IHPSG13_NAND3X2 +XI1<0> NADR<2> NADR<3> CS sel23<0> VDD VSS / RSC_IHPSG13_NAND3X2 +XI2<15> sel23<3> sel01<3> EN WL<15> VDD VSS / RSC_IHPSG13_NOR3X2 +XI2<14> sel23<3> sel01<2> EN WL<14> VDD VSS / RSC_IHPSG13_NOR3X2 +XI2<13> sel23<3> sel01<1> EN WL<13> VDD VSS / RSC_IHPSG13_NOR3X2 +XI2<12> sel23<3> sel01<0> EN WL<12> VDD VSS / RSC_IHPSG13_NOR3X2 +XI2<11> sel23<2> sel01<3> EN WL<11> VDD VSS / RSC_IHPSG13_NOR3X2 +XI2<10> sel23<2> sel01<2> EN WL<10> VDD VSS / RSC_IHPSG13_NOR3X2 +XI2<9> sel23<2> sel01<1> EN WL<9> VDD VSS / RSC_IHPSG13_NOR3X2 +XI2<8> sel23<2> sel01<0> EN WL<8> VDD VSS / RSC_IHPSG13_NOR3X2 +XI2<7> sel23<1> sel01<3> EN WL<7> VDD VSS / RSC_IHPSG13_NOR3X2 +XI2<6> sel23<1> sel01<2> EN WL<6> VDD VSS / RSC_IHPSG13_NOR3X2 +XI2<5> sel23<1> sel01<1> EN WL<5> VDD VSS / RSC_IHPSG13_NOR3X2 +XI2<4> sel23<1> sel01<0> EN WL<4> VDD VSS / RSC_IHPSG13_NOR3X2 +XI2<3> sel23<0> sel01<3> EN WL<3> VDD VSS / RSC_IHPSG13_NOR3X2 +XI2<2> sel23<0> sel01<2> EN WL<2> VDD VSS / RSC_IHPSG13_NOR3X2 +XI2<1> sel23<0> sel01<1> EN WL<1> VDD VSS / RSC_IHPSG13_NOR3X2 +XI2<0> sel23<0> sel01<0> EN WL<0> VDD VSS / RSC_IHPSG13_NOR3X2 +XCAPS4 VDD VSS / RSC_IHPSG13_FILLCAP4 +XI11 ECLK_L_BOT ECLK_L_TOP / RSC_IHPSG13_MET2RES +XR0 ECLK_H_BOT ECLK_H_TOP / RSC_IHPSG13_MET2RES +.ENDS +.SUBCKT RM_IHPSG13_256x16_c2_1P_ROWDEC4 ADDR_N_I<3> ADDR_N_I<2> ADDR_N_I<1> ADDR_N_I<0> ++ CS_I ECLK_I WL_O<15> WL_O<14> WL_O<13> WL_O<12> WL_O<11> WL_O<10> WL_O<9> ++ WL_O<8> WL_O<7> WL_O<6> WL_O<5> WL_O<4> WL_O<3> WL_O<2> WL_O<1> WL_O<0> ++ VDD VSS +XL2<8> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<7> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<6> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<5> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<4> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<3> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<2> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<1> VDD VSS / RSC_IHPSG13_FILLCAP8 +XSEL ADDR_N_I<3> ADDR_N_I<2> ADDR_N_I<1> ADDR_N_I<0> CS_I ECLK_I ECLK_H<1> ++ ECLK_B<0> ECLK_B<1> WL_O<15> WL_O<14> WL_O<13> WL_O<12> WL_O<11> WL_O<10> ++ WL_O<9> WL_O<8> WL_O<7> WL_O<6> WL_O<5> WL_O<4> WL_O<3> WL_O<2> WL_O<1> ++ WL_O<0> VDD VSS / RM_IHPSG13_256x16_c2_1P_DEC04 +.ENDS +.SUBCKT RSC_IHPSG13_CINVX8 A Z VDD VSS +MN0 Z A VSS VSS sg13_lv_nmos m=1 w=2.82u l=130.00n ng=4 nrd=0 nrs=0 +MP0 Z A VDD VDD sg13_lv_pmos m=1 w=6.48u l=130.00n ng=4 nrd=0 nrs=0 +.ENDS +.SUBCKT RSC_IHPSG13_DFNQMX2IX1 BE BI CN D QI QIN VDD VSS +MN15 net026 BI VSS VSS sg13_lv_nmos m=1 w=560.00n l=130.00n ng=1 nrd=0 ++ nrs=0 +MN14 MXI_OUT BE net026 VSS sg13_lv_nmos m=1 w=560.00n l=130.00n ng=1 nrd=0 ++ nrs=0 +MN1 net025 D VSS VSS sg13_lv_nmos m=1 w=560.00n l=130.00n ng=1 nrd=0 ++ nrs=0 +MN0 MXI_OUT BEN net025 VSS sg13_lv_nmos m=1 w=560.00n l=130.00n ng=1 nrd=0 ++ nrs=0 +MN10 QI CNN net21 VSS sg13_lv_nmos m=1 w=850.00n l=130.00n ng=1 nrd=0 nrs=0 +MN11 net21 QI_MS VSS VSS sg13_lv_nmos m=1 w=850.00n l=130.00n ng=1 ++ nrd=0 nrs=0 +MN7 net30 QI_MS VSS VSS sg13_lv_nmos m=1 w=480.00n l=130.00n ng=1 ++ nrd=0 nrs=0 +MN6 QIN_MS CNN net30 VSS sg13_lv_nmos m=1 w=480.00n l=130.00n ng=1 nrd=0 ++ nrs=0 +MN3 QI_MS QIN_MS VSS VSS sg13_lv_nmos m=1 w=480.00n l=130.00n ng=1 ++ nrd=0 nrs=0 +MN12 CNN CN VSS VSS sg13_lv_nmos m=1 w=495.000n l=130.00n ng=1 nrd=0 ++ nrs=0 +MN9 net37 MXI_OUT VSS VSS sg13_lv_nmos m=1 w=870.00n l=130.00n ng=1 ++ nrd=0 nrs=0 +MN8 QIN_MS CN net37 VSS sg13_lv_nmos m=1 w=870.00n l=130.00n ng=1 nrd=0 ++ nrs=0 +MN5 QI CN net25 VSS sg13_lv_nmos m=1 w=480.00n l=130.00n ng=1 nrd=0 nrs=0 +MN4 net25 QIN VSS VSS sg13_lv_nmos m=1 w=480.00n l=130.00n ng=1 nrd=0 ++ nrs=0 +MN2 QIN QI VSS VSS sg13_lv_nmos m=1 w=480.00n l=130.00n ng=1 nrd=0 ++ nrs=0 +MN13 BEN BE VSS VSS sg13_lv_nmos m=1 w=560.00n l=130.00n ng=1 nrd=0 ++ nrs=0 +MP15 MXI_OUT BEN net027 VDD sg13_lv_pmos m=1 w=985.000n l=130.00n ng=1 ++ nrd=0 nrs=0 +MP14 net027 BI VDD VDD sg13_lv_pmos m=1 w=985.000n l=130.00n ng=1 ++ nrd=0 nrs=0 +MP1 MXI_OUT BE net024 VDD sg13_lv_pmos m=1 w=985.000n l=130.00n ng=1 nrd=0 ++ nrs=0 +MP0 net024 D VDD VDD sg13_lv_pmos m=1 w=985.000n l=130.00n ng=1 nrd=0 ++ nrs=0 +MP13 BEN BE VDD VDD sg13_lv_pmos m=1 w=645.000n l=130.00n ng=1 nrd=0 ++ nrs=0 +MP6 QI_MS QIN_MS VDD VDD sg13_lv_pmos m=1 w=480.00n l=130.00n ng=1 ++ nrd=0 nrs=0 +MP3 QI CNN net27 VDD sg13_lv_pmos m=1 w=480.00n l=130.00n ng=1 nrd=0 nrs=0 +MP2 net27 QIN VDD VDD sg13_lv_pmos m=1 w=480.00n l=130.00n ng=1 nrd=0 ++ nrs=0 +MP10 net36 MXI_OUT VDD VDD sg13_lv_pmos m=1 w=975.000n l=130.00n ng=1 ++ nrd=0 nrs=0 +MP11 QIN_MS CNN net36 VDD sg13_lv_pmos m=1 w=975.000n l=130.00n ng=1 nrd=0 ++ nrs=0 +MP4 net32 QI_MS VDD VDD sg13_lv_pmos m=1 w=480.00n l=130.00n ng=1 ++ nrd=0 nrs=0 +MP5 QIN_MS CN net32 VDD sg13_lv_pmos m=1 w=480.00n l=130.00n ng=1 nrd=0 ++ nrs=0 +MP7 QIN QI VDD VDD sg13_lv_pmos m=1 w=480.00n l=130.00n ng=1 nrd=0 ++ nrs=0 +MP12 CNN CN VDD VDD sg13_lv_pmos m=1 w=480.00n l=130.00n ng=1 nrd=0 ++ nrs=0 +MP9 QI CN net19 VDD sg13_lv_pmos m=1 w=990.00n l=130.00n ng=1 nrd=0 nrs=0 +MP8 net19 QI_MS VDD VDD sg13_lv_pmos m=1 w=990.00n l=130.00n ng=1 ++ nrd=0 nrs=0 +.ENDS +.SUBCKT RM_IHPSG13_256x16_c2_1P_ROWREG4 ACLK_N_I ADDR_I<3> ADDR_I<2> ADDR_I<1> ADDR_I<0> ++ ADDR_N_O<3> ADDR_N_O<2> ADDR_N_O<1> ADDR_N_O<0> BIST_ADDR_I<3> ++ BIST_ADDR_I<2> BIST_ADDR_I<1> BIST_ADDR_I<0> BIST_EN_I VDD VSS +XINV<3> q_int<3> qn_int<3> VDD VSS / RSC_IHPSG13_CINVX2 +XINV<2> q_int<2> qn_int<2> VDD VSS / RSC_IHPSG13_CINVX2 +XINV<1> q_int<1> qn_int<1> VDD VSS / RSC_IHPSG13_CINVX2 +XINV<0> q_int<0> qn_int<0> VDD VSS / RSC_IHPSG13_CINVX2 +XDRV<3> qn_int<3> ADDR_N_O<3> VDD VSS / RSC_IHPSG13_CINVX8 +XDRV<2> qn_int<2> ADDR_N_O<2> VDD VSS / RSC_IHPSG13_CINVX8 +XDRV<1> qn_int<1> ADDR_N_O<1> VDD VSS / RSC_IHPSG13_CINVX8 +XDRV<0> qn_int<0> ADDR_N_O<0> VDD VSS / RSC_IHPSG13_CINVX8 +XDFF<3> BIST_EN_I BIST_ADDR_I<3> ACLK_N_I ADDR_I<3> q_int<3> net2<0> VDD ++ VSS / RSC_IHPSG13_DFNQMX2IX1 +XDFF<2> BIST_EN_I BIST_ADDR_I<2> ACLK_N_I ADDR_I<2> q_int<2> net2<1> VDD ++ VSS / RSC_IHPSG13_DFNQMX2IX1 +XDFF<1> BIST_EN_I BIST_ADDR_I<1> ACLK_N_I ADDR_I<1> q_int<1> net2<2> VDD ++ VSS / RSC_IHPSG13_DFNQMX2IX1 +XDFF<0> BIST_EN_I BIST_ADDR_I<0> ACLK_N_I ADDR_I<0> q_int<0> net2<3> VDD ++ VSS / RSC_IHPSG13_DFNQMX2IX1 +XI11<20> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI11<19> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI11<18> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI11<17> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI11<16> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI11<15> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI11<14> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI11<13> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI11<12> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI11<11> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI11<10> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI11<9> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI11<8> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI11<7> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI11<6> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI11<5> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI11<4> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI11<3> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI11<2> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI11<1> VDD VSS / RSC_IHPSG13_FILLCAP8 +.ENDS +.SUBCKT RSC_IHPSG13_CDLYX1 A Z VDD VSS +MN1 net010 net032 VSS VSS sg13_lv_nmos m=1 w=300.0n l=160.00n ng=1 ++ nrd=0 nrs=0 +MN2 net032 A net014 VSS sg13_lv_nmos m=1 w=300.0n l=160.00n ng=1 nrd=0 ++ nrs=0 +MN0 Z net032 net010 VSS sg13_lv_nmos m=1 w=300.0n l=160.00n ng=1 nrd=0 ++ nrs=0 +MN3 net014 A VSS VSS sg13_lv_nmos m=1 w=300.0n l=160.00n ng=1 nrd=0 ++ nrs=0 +MP1 Z net032 net07 VDD sg13_lv_pmos m=1 w=720.00n l=160.00n ng=1 nrd=0 ++ nrs=0 +MP3 net011 A VDD VDD sg13_lv_pmos m=1 w=720.00n l=160.00n ng=1 nrd=0 ++ nrs=0 +MP0 net07 net032 VDD VDD sg13_lv_pmos m=1 w=720.00n l=160.00n ng=1 ++ nrd=0 nrs=0 +MP2 net032 A net011 VDD sg13_lv_pmos m=1 w=720.00n l=160.00n ng=1 nrd=0 ++ nrs=0 +.ENDS +.SUBCKT RSC_IHPSG13_CDLYX1_DUMMY A Z VDD VSS +MN0 vss_r vdd_r VSS VSS sg13_lv_nmos m=1 w=2.49u l=300.0n ng=3 nrd=0 ++ nrs=0 +MP0 vdd_r vss_r VDD VDD sg13_lv_pmos m=1 w=3.24u l=640.00n ng=2 nrd=0 ++ nrs=0 +R0 Z A lvsres w=2.6e-07 l=6e-07 +.ENDS + +.SUBCKT RSC_IHPSG13_MX2IX1 A0 A1 S ZN VDD VSS +MP4 SN S VDD VDD sg13_lv_pmos m=1 w=645.000n l=130.00n ng=1 nrd=0 nrs=0 +MP3 ZN SN net12 VDD sg13_lv_pmos m=1 w=985.000n l=130.00n ng=1 nrd=0 nrs=0 +MP2 net12 A1 VDD VDD sg13_lv_pmos m=1 w=985.000n l=130.00n ng=1 nrd=0 ++ nrs=0 +MP1 ZN S net17 VDD sg13_lv_pmos m=1 w=985.000n l=130.00n ng=1 nrd=0 nrs=0 +MP0 net17 A0 VDD VDD sg13_lv_pmos m=1 w=985.000n l=130.00n ng=1 nrd=0 ++ nrs=0 +MN5 SN S VSS VSS sg13_lv_nmos m=1 w=480.00n l=130.00n ng=1 nrd=0 nrs=0 +MN3 net13 A1 VSS VSS sg13_lv_nmos m=1 w=480.00n l=130.00n ng=1 nrd=0 ++ nrs=0 +MN2 ZN S net13 VSS sg13_lv_nmos m=1 w=480.00n l=130.00n ng=1 nrd=0 nrs=0 +MN1 net15 A0 VSS VSS sg13_lv_nmos m=1 w=480.00n l=130.00n ng=1 nrd=0 ++ nrs=0 +MN0 ZN SN net15 VSS sg13_lv_nmos m=1 w=480.00n l=130.00n ng=1 nrd=0 nrs=0 +.ENDS +.SUBCKT RM_IHPSG13_256x16_c2_1P_DLY_MUX A SEL Z VDD VSS +XI11 net4 Z VDD VSS / RSC_IHPSG13_CINVX2 +XI8 A D<3> SEL net4 VDD VSS / RSC_IHPSG13_MX2IX1 +XI20<3> D<2> D<3> VDD VSS / RSC_IHPSG13_CDLYX1 +XI20<2> D<1> D<2> VDD VSS / RSC_IHPSG13_CDLYX1 +XI20<1> A D<1> VDD VSS / RSC_IHPSG13_CDLYX1 +.ENDS +.SUBCKT RSC_IHPSG13_DFNQX2 CN D Q VDD VSS +MN0 Q QIN_SL VSS VSS sg13_lv_nmos m=1 w=980.00n l=130.00n ng=1 nrd=0 ++ nrs=0 +MN10 QIN_SL CNN net21 VSS sg13_lv_nmos m=1 w=850.00n l=130.00n ng=1 nrd=0 ++ nrs=0 +MN11 net21 QI_MS VSS VSS sg13_lv_nmos m=1 w=850.00n l=130.00n ng=1 ++ nrd=0 nrs=0 +MN7 net30 QI_MS VSS VSS sg13_lv_nmos m=1 w=480.00n l=130.00n ng=1 ++ nrd=0 nrs=0 +MN6 QIN_MS CNN net30 VSS sg13_lv_nmos m=1 w=480.00n l=130.00n ng=1 nrd=0 ++ nrs=0 +MN3 QI_MS QIN_MS VSS VSS sg13_lv_nmos m=1 w=480.00n l=130.00n ng=1 ++ nrd=0 nrs=0 +MN12 CNN CN VSS VSS sg13_lv_nmos m=1 w=495.000n l=130.00n ng=1 nrd=0 ++ nrs=0 +MN9 net37 D VSS VSS sg13_lv_nmos m=1 w=870.00n l=130.00n ng=1 nrd=0 ++ nrs=0 +MN8 QIN_MS CN net37 VSS sg13_lv_nmos m=1 w=870.00n l=130.00n ng=1 nrd=0 ++ nrs=0 +MN5 QIN_SL CN net25 VSS sg13_lv_nmos m=1 w=480.00n l=130.00n ng=1 nrd=0 ++ nrs=0 +MN4 net25 QI_SL VSS VSS sg13_lv_nmos m=1 w=480.00n l=130.00n ng=1 ++ nrd=0 nrs=0 +MN2 QI_SL QIN_SL VSS VSS sg13_lv_nmos m=1 w=480.00n l=130.00n ng=1 ++ nrd=0 nrs=0 +MP0 Q QIN_SL VDD VDD sg13_lv_pmos m=1 w=1.62u l=130.00n ng=1 nrd=0 ++ nrs=0 +MP6 QI_MS QIN_MS VDD VDD sg13_lv_pmos m=1 w=480.00n l=130.00n ng=1 ++ nrd=0 nrs=0 +MP3 QIN_SL CNN net27 VDD sg13_lv_pmos m=1 w=480.00n l=130.00n ng=1 nrd=0 ++ nrs=0 +MP2 net27 QI_SL VDD VDD sg13_lv_pmos m=1 w=480.00n l=130.00n ng=1 ++ nrd=0 nrs=0 +MP10 net36 D VDD VDD sg13_lv_pmos m=1 w=975.000n l=130.00n ng=1 nrd=0 ++ nrs=0 +MP11 QIN_MS CNN net36 VDD sg13_lv_pmos m=1 w=975.000n l=130.00n ng=1 nrd=0 ++ nrs=0 +MP4 net32 QI_MS VDD VDD sg13_lv_pmos m=1 w=480.00n l=130.00n ng=1 ++ nrd=0 nrs=0 +MP5 QIN_MS CN net32 VDD sg13_lv_pmos m=1 w=480.00n l=130.00n ng=1 nrd=0 ++ nrs=0 +MP7 QI_SL QIN_SL VDD VDD sg13_lv_pmos m=1 w=480.00n l=130.00n ng=1 ++ nrd=0 nrs=0 +MP12 CNN CN VDD VDD sg13_lv_pmos m=1 w=480.00n l=130.00n ng=1 nrd=0 ++ nrs=0 +MP9 QIN_SL CN net19 VDD sg13_lv_pmos m=1 w=990.00n l=130.00n ng=1 nrd=0 ++ nrs=0 +MP8 net19 QI_MS VDD VDD sg13_lv_pmos m=1 w=990.00n l=130.00n ng=1 ++ nrd=0 nrs=0 +.ENDS +.SUBCKT RSC_IHPSG13_CNAND2X2 A B Z VDD VSS +MN0 Z B net6 VSS sg13_lv_nmos m=1 w=980.00n l=130.00n ng=1 nrd=0 nrs=0 +MN1 net6 A VSS VSS sg13_lv_nmos m=1 w=980.00n l=130.00n ng=1 nrd=0 ++ nrs=0 +MP1 Z B VDD VDD sg13_lv_pmos m=1 w=1.62u l=130.00n ng=1 nrd=0 nrs=0 +MP0 Z A VDD VDD sg13_lv_pmos m=1 w=1.62u l=130.00n ng=1 nrd=0 nrs=0 +.ENDS +.SUBCKT RSC_IHPSG13_CGATEPX4 CP E Q VDD VSS +MN1 net08 QIN VSS VSS sg13_lv_nmos m=1 w=480.00n l=130.00n ng=1 nrd=0 ++ nrs=0 +MN2 net019 net08 VSS VSS sg13_lv_nmos m=1 w=480.00n l=130.00n ng=1 ++ nrd=0 nrs=0 +MN3 QIN CP net019 VSS sg13_lv_nmos m=1 w=480.00n l=130.00n ng=1 nrd=0 nrs=0 +MN6 Q net015 VSS VSS sg13_lv_nmos m=1 w=1.41u l=130.00n ng=2 nrd=0 ++ nrs=0 +MN5 net015 net08 net018 VSS sg13_lv_nmos m=1 w=980.00n l=130.00n ng=1 ++ nrd=0 nrs=0 +MN8 QIN CPN net023 VSS sg13_lv_nmos m=1 w=870.00n l=130.00n ng=1 nrd=0 ++ nrs=0 +MN7 net023 E VSS VSS sg13_lv_nmos m=1 w=870.00n l=130.00n ng=1 nrd=0 ++ nrs=0 +MN4 net018 CP VSS VSS sg13_lv_nmos m=1 w=980.00n l=130.00n ng=1 nrd=0 ++ nrs=0 +MN0 CPN CP VSS VSS sg13_lv_nmos m=1 w=500.0n l=130.00n ng=1 nrd=0 nrs=0 +MP3 net08 QIN VDD VDD sg13_lv_pmos m=1 w=480.00n l=130.00n ng=1 nrd=0 ++ nrs=0 +MP2 QIN CPN net017 VDD sg13_lv_pmos m=1 w=480.00n l=130.00n ng=1 nrd=0 ++ nrs=0 +MP1 net017 net08 VDD VDD sg13_lv_pmos m=1 w=480.00n l=130.00n ng=1 ++ nrd=0 nrs=0 +MP0 CPN CP VDD VDD sg13_lv_pmos m=1 w=500.0n l=130.00n ng=1 nrd=0 nrs=0 +MP8 QIN CP net024 VDD sg13_lv_pmos m=1 w=975.000n l=130.00n ng=1 nrd=0 ++ nrs=0 +MP7 net024 E VDD VDD sg13_lv_pmos m=1 w=975.000n l=130.00n ng=1 nrd=0 ++ nrs=0 +MP4 net015 CP VDD VDD sg13_lv_pmos m=1 w=1.27u l=130.00n ng=1 nrd=0 ++ nrs=0 +MP6 Q net015 VDD VDD sg13_lv_pmos m=1 w=3.24u l=130.00n ng=2 nrd=0 ++ nrs=0 +MP5 net015 net08 VDD VDD sg13_lv_pmos m=1 w=1.27u l=130.00n ng=1 nrd=0 ++ nrs=0 +.ENDS +.SUBCKT RSC_IHPSG13_CBUFX8 A Z VDD VSS +MP0 net4 A VDD VDD sg13_lv_pmos m=1 w=3.24u l=130.00n ng=2 nrd=0 nrs=0 +MP1 Z net4 VDD VDD sg13_lv_pmos m=1 w=6.48u l=130.00n ng=4 nrd=0 nrs=0 +MN1 Z net4 VSS VSS sg13_lv_nmos m=1 w=2.82u l=130.00n ng=4 nrd=0 nrs=0 +MN0 net4 A VSS VSS sg13_lv_nmos m=1 w=1.41u l=130.00n ng=2 nrd=0 nrs=0 +.ENDS +.SUBCKT RSC_IHPSG13_CDLYX2 A Z VDD VSS +MN2 net4 A net9 VSS sg13_lv_nmos m=1 w=320.00n l=200.0n ng=1 nrd=0 nrs=0 +MN0 Z net4 VSS VSS sg13_lv_nmos m=1 w=705.000n l=130.00n ng=1 nrd=0 ++ nrs=0 +MN1 net9 A VSS VSS sg13_lv_nmos m=1 w=320.00n l=200.0n ng=1 nrd=0 nrs=0 +MP2 net4 A net10 VDD sg13_lv_pmos m=1 w=1.2u l=200.0n ng=1 nrd=0 nrs=0 +MP1 net10 A VDD VDD sg13_lv_pmos m=1 w=1.2u l=200.0n ng=1 nrd=0 nrs=0 +MP0 Z net4 VDD VDD sg13_lv_pmos m=1 w=1.62u l=130.00n ng=1 nrd=0 nrs=0 +.ENDS +.SUBCKT RSC_IHPSG13_MX2X2 A0 A1 S Z VDD VSS +MP6 Z net010 VDD VDD sg13_lv_pmos m=1 w=1.62u l=130.00n ng=1 nrd=0 ++ nrs=0 +MP4 SN S VDD VDD sg13_lv_pmos m=1 w=645.000n l=130.00n ng=1 nrd=0 nrs=0 +MP3 net010 SN net12 VDD sg13_lv_pmos m=1 w=985.000n l=130.00n ng=1 nrd=0 ++ nrs=0 +MP2 net12 A1 VDD VDD sg13_lv_pmos m=1 w=985.000n l=130.00n ng=1 nrd=0 ++ nrs=0 +MP1 net010 S net17 VDD sg13_lv_pmos m=1 w=985.000n l=130.00n ng=1 nrd=0 ++ nrs=0 +MP0 net17 A0 VDD VDD sg13_lv_pmos m=1 w=985.000n l=130.00n ng=1 nrd=0 ++ nrs=0 +MN6 Z net010 VSS VSS sg13_lv_nmos m=1 w=705.000n l=130.00n ng=1 nrd=0 ++ nrs=0 +MN5 SN S VSS VSS sg13_lv_nmos m=1 w=560.00n l=130.00n ng=1 nrd=0 nrs=0 +MN3 net13 A1 VSS VSS sg13_lv_nmos m=1 w=560.00n l=130.00n ng=1 nrd=0 ++ nrs=0 +MN2 net010 S net13 VSS sg13_lv_nmos m=1 w=560.00n l=130.00n ng=1 nrd=0 ++ nrs=0 +MN1 net15 A0 VSS VSS sg13_lv_nmos m=1 w=560.00n l=130.00n ng=1 nrd=0 ++ nrs=0 +MN0 net010 SN net15 VSS sg13_lv_nmos m=1 w=560.00n l=130.00n ng=1 nrd=0 ++ nrs=0 +.ENDS +.SUBCKT RSC_IHPSG13_AND2X2 A B Z VDD VSS +MN3 Z net6 VSS VSS sg13_lv_nmos m=1 w=980.00n l=130.00n ng=1 nrd=0 ++ nrs=0 +MN4 net9 B VSS VSS sg13_lv_nmos m=1 w=500.0n l=130.00n ng=1 nrd=0 nrs=0 +MN6 net6 A net9 VSS sg13_lv_nmos m=1 w=500.0n l=130.00n ng=1 nrd=0 nrs=0 +MP2 Z net6 VDD VDD sg13_lv_pmos m=1 w=1.62u l=130.00n ng=1 nrd=0 nrs=0 +MP0 net6 B VDD VDD sg13_lv_pmos m=1 w=860.00n l=130.00n ng=1 nrd=0 ++ nrs=0 +MP1 net6 A VDD VDD sg13_lv_pmos m=1 w=860.00n l=130.00n ng=1 nrd=0 ++ nrs=0 +.ENDS +.SUBCKT RSC_IHPSG13_TIEL Z VDD VSS +MN0 Z net2 VSS VSS sg13_lv_nmos m=1 w=480.00n l=130.00n ng=1 nrd=0 ++ nrs=0 +MP0 net2 net2 VDD VDD sg13_lv_pmos m=1 w=480.00n l=130.00n ng=1 nrd=0 ++ nrs=0 +.ENDS +.SUBCKT RSC_IHPSG13_XOR2X2 A B Z VDD VSS +MP8 net012 B net7 VDD sg13_lv_pmos m=1 w=825.000n l=130.00n ng=1 nrd=0 ++ nrs=0 +MP7 net011 net3 net012 VDD sg13_lv_pmos m=1 w=825.000n l=130.00n ng=1 ++ nrd=0 nrs=0 +MP6 Z net012 VDD VDD sg13_lv_pmos m=1 w=1.535u l=130.00n ng=1 nrd=0 ++ nrs=0 +MP2 net7 A VDD VDD sg13_lv_pmos m=1 w=825.000n l=130.00n ng=1 nrd=0 ++ nrs=0 +MP4 net011 net7 VDD VDD sg13_lv_pmos m=1 w=825.000n l=130.00n ng=1 ++ nrd=0 nrs=0 +MP5 net3 B VDD VDD sg13_lv_pmos m=1 w=580.00n l=130.00n ng=1 nrd=0 ++ nrs=0 +MN7 net012 B net011 VSS sg13_lv_nmos m=1 w=555.000n l=130.00n ng=1 nrd=0 ++ nrs=0 +MN6 net7 net3 net012 VSS sg13_lv_nmos m=1 w=555.000n l=130.00n ng=1 nrd=0 ++ nrs=0 +MN5 Z net012 VSS VSS sg13_lv_nmos m=1 w=775.000n l=130.00n ng=1 nrd=0 ++ nrs=0 +MN2 net7 A VSS VSS sg13_lv_nmos m=1 w=555.000n l=130.00n ng=1 nrd=0 ++ nrs=0 +MN4 net3 B VSS VSS sg13_lv_nmos m=1 w=480.00n l=130.00n ng=1 nrd=0 ++ nrs=0 +MN3 net011 net7 VSS VSS sg13_lv_nmos m=1 w=555.000n l=130.00n ng=1 ++ nrd=0 nrs=0 +.ENDS +.SUBCKT RSC_IHPSG13_OA12X1 A B C Z VDD VSS +MN2 net7 C VSS VSS sg13_lv_nmos m=1 w=980.00n l=130.00n ng=1 nrd=0 ++ nrs=0 +MN3 Z net17 VSS VSS sg13_lv_nmos m=1 w=500.0n l=130.00n ng=1 nrd=0 ++ nrs=0 +MN1 net17 B net7 VSS sg13_lv_nmos m=1 w=980.00n l=130.00n ng=1 nrd=0 nrs=0 +MN0 net17 A net7 VSS sg13_lv_nmos m=1 w=980.00n l=130.00n ng=1 nrd=0 nrs=0 +MP0 net24 A VDD VDD sg13_lv_pmos m=1 w=1.62u l=130.00n ng=1 nrd=0 nrs=0 +MP3 Z net17 VDD VDD sg13_lv_pmos m=1 w=905.000n l=130.00n ng=1 nrd=0 ++ nrs=0 +MP1 net17 B net24 VDD sg13_lv_pmos m=1 w=1.62u l=130.00n ng=1 nrd=0 nrs=0 +MP2 net17 C VDD VDD sg13_lv_pmos m=1 w=905.000n l=130.00n ng=1 nrd=0 ++ nrs=0 +.ENDS +.SUBCKT RM_IHPSG13_256x16_c2_1P_CTRL ACLK_N BIST_CK_I BIST_CS_I BIST_EN BIST_RE_I ++ BIST_WE_I B_TIEL_O CK_I CS_I DCLK ECLK PULSE_H PULSE_L PULSE_O RCLK RE_I ++ ROW_CS WCLK WE_I VDD VSS +XI17 ck_regs we col_we VDD VSS / RSC_IHPSG13_DFNQX2 +XI16 ck_regs re col_re VDD VSS / RSC_IHPSG13_DFNQX2 +XI18 ck_regs cs net7 VDD VSS / RSC_IHPSG13_DFNQX2 +XI71 ACLK_N net012 PULSE_O VDD VSS / RSC_IHPSG13_DFNQX2 +XI77 col_we net9 net016 VDD VSS / RSC_IHPSG13_CNAND2X2 +XI76 col_re net9 net018 VDD VSS / RSC_IHPSG13_CNAND2X2 +XI15 ck_dly WEorREandCS aclk VDD VSS / RSC_IHPSG13_CGATEPX4 +XI14 ck WEandCS DCLK VDD VSS / RSC_IHPSG13_CGATEPX4 +XI60 net7 ROW_CS VDD VSS / RSC_IHPSG13_CBUFX8 +XI73 PULSE_O net012 VDD VSS / RSC_IHPSG13_CINVX2 +XI8 net9 net8 VDD VSS / RSC_IHPSG13_CINVX2 +XI64 ck ck_dly VDD VSS / RSC_IHPSG13_CDLYX2 +XI86 CS_I BIST_CS_I BIST_EN cs VDD VSS / RSC_IHPSG13_MX2X2 +XI87 CK_I BIST_CK_I BIST_EN ck VDD VSS / RSC_IHPSG13_MX2X2 +XI85 WE_I BIST_WE_I BIST_EN we VDD VSS / RSC_IHPSG13_MX2X2 +XI84 RE_I BIST_RE_I BIST_EN re VDD VSS / RSC_IHPSG13_MX2X2 +XI22 we cs WEandCS VDD VSS / RSC_IHPSG13_AND2X2 +XBM_TIEL B_TIEL_O VDD VSS / RSC_IHPSG13_TIEL +XI48 ck_dly ck_regs VDD VSS / RSC_IHPSG13_CINVX4 +XI81 net016 WCLK VDD VSS / RSC_IHPSG13_CINVX4 +XI80 net018 RCLK VDD VSS / RSC_IHPSG13_CINVX4 +XI78 net8 net020 VDD VSS / RSC_IHPSG13_CINVX4 +XI6 PULSE_L PULSE_H net9 VDD VSS / RSC_IHPSG13_XOR2X2 +XI79 net020 ECLK VDD VSS / RSC_IHPSG13_CINVX8 +XI63 aclk ACLK_N VDD VSS / RSC_IHPSG13_CINVX8 +XI21 re we cs WEorREandCS VDD VSS / RSC_IHPSG13_OA12X1 +.ENDS +.SUBCKT RM_IHPSG13_256x16_c2_1P_COLDEC2 ACLK_N ADDR<1> ADDR<0> ADDR_COL<1> ADDR_COL<0> ++ ADDR_DEC<7> ADDR_DEC<6> ADDR_DEC<5> ADDR_DEC<4> ADDR_DEC<3> ADDR_DEC<2> ++ ADDR_DEC<1> ADDR_DEC<0> BIST_ADDR<1> BIST_ADDR<0> BIST_EN_I VDD VSS +XI14<5> VDD VSS / RSC_IHPSG13_FILLCAP4 +XI14<4> VDD VSS / RSC_IHPSG13_FILLCAP4 +XI14<3> VDD VSS / RSC_IHPSG13_FILLCAP4 +XI14<2> VDD VSS / RSC_IHPSG13_FILLCAP4 +XI14<1> VDD VSS / RSC_IHPSG13_FILLCAP4 +XDFF<1> BIST_EN_I BIST_ADDR<1> ACLK_N ADDR<1> padr_int<1> net6<0> VDD ++ VSS / RSC_IHPSG13_DFNQMX2IX1 +XDFF<0> BIST_EN_I BIST_ADDR<0> ACLK_N ADDR<0> padr_int<0> net6<1> VDD ++ VSS / RSC_IHPSG13_DFNQMX2IX1 +XI1<3> PADR<1> PADR<0> addr_n<3> VDD VSS / RSC_IHPSG13_NAND2X2 +XI1<2> PADR<1> NADR<0> addr_n<2> VDD VSS / RSC_IHPSG13_NAND2X2 +XI1<1> NADR<1> PADR<0> addr_n<1> VDD VSS / RSC_IHPSG13_NAND2X2 +XI1<0> NADR<1> NADR<0> addr_n<0> VDD VSS / RSC_IHPSG13_NAND2X2 +XI16<37> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI16<36> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI16<35> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI16<34> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI16<33> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI16<32> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI16<31> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI16<30> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI16<29> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI16<28> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI16<27> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI16<26> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI16<25> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI16<24> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI16<23> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI16<22> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI16<21> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI16<20> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI16<19> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI16<18> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI16<17> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI16<16> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI16<15> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI16<14> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI16<13> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI16<12> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI16<11> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI16<10> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI16<9> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI16<8> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI16<7> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI16<6> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI16<5> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI16<4> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI16<3> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI16<2> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI16<1> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI3<1> padr_int<1> NADR<1> VDD VSS / RSC_IHPSG13_INVX2 +XI3<0> padr_int<0> NADR<0> VDD VSS / RSC_IHPSG13_INVX2 +XI13<1> NADR<1> PADR<1> VDD VSS / RSC_IHPSG13_INVX2 +XI13<0> NADR<0> PADR<0> VDD VSS / RSC_IHPSG13_INVX2 +XI2<3> addr_n<3> ADDR_DEC<3> VDD VSS / RSC_IHPSG13_INVX2 +XI2<2> addr_n<2> ADDR_DEC<2> VDD VSS / RSC_IHPSG13_INVX2 +XI2<1> addr_n<1> ADDR_DEC<1> VDD VSS / RSC_IHPSG13_INVX2 +XI2<0> addr_n<0> ADDR_DEC<0> VDD VSS / RSC_IHPSG13_INVX2 +XI15<1> ADDR_COL<1> VDD VSS / RSC_IHPSG13_TIEL +XI15<0> ADDR_COL<0> VDD VSS / RSC_IHPSG13_TIEL +XI17<3> ADDR_DEC<7> VDD VSS / RSC_IHPSG13_TIEL +XI17<2> ADDR_DEC<6> VDD VSS / RSC_IHPSG13_TIEL +XI17<1> ADDR_DEC<5> VDD VSS / RSC_IHPSG13_TIEL +XI17<0> ADDR_DEC<4> VDD VSS / RSC_IHPSG13_TIEL +.ENDS +.SUBCKT RSC_IHPSG13_NOR2X2 A B Z VDD VSS +MP1 Z B net9 VDD sg13_lv_pmos m=1 w=1.62u l=130.00n ng=1 nrd=0 nrs=0 +MP0 net9 A VDD VDD sg13_lv_pmos m=1 w=1.62u l=130.00n ng=1 nrd=0 nrs=0 +MN0 Z B VSS VSS sg13_lv_nmos m=1 w=980.00n l=130.00n ng=1 nrd=0 nrs=0 +MN1 Z A VSS VSS sg13_lv_nmos m=1 w=980.00n l=130.00n ng=1 nrd=0 nrs=0 +.ENDS +.SUBCKT RSC_IHPSG13_CINVX4_WN A Z VDD VSS +MN0 Z A VSS VSS sg13_lv_nmos m=1 w=705.000n l=130.00n ng=1 nrd=0 nrs=0 +MP0 Z A VDD VDD sg13_lv_pmos m=1 w=3.24u l=130.00n ng=2 nrd=0 nrs=0 +.ENDS +.SUBCKT RM_IHPSG13_256x16_c2_1P_BLDRV BLC BLC_SEL BLT BLT_SEL PRE_N SEL_P WR_ONE WR_ZERO ++ VDD VSS +XCDEC SEL_P WR_ZERO BLC_PMOS_DRIVE VDD VSS / RSC_IHPSG13_NAND2X2 +XTDEC SEL_P WR_ONE BLT_PMOS_DRIVE VDD VSS / RSC_IHPSG13_NAND2X2 +MTWN BLT BLT_NMOS_DRIVE VSS VSS sg13_lv_nmos m=1 w=4.82u l=130.00n ++ ng=2 nrd=0 nrs=0 +MCWN BLC BLC_NMOS_DRIVE VSS VSS sg13_lv_nmos m=1 w=4.82u l=130.00n ++ ng=2 nrd=0 nrs=0 +MCWP BLC BLC_PMOS_DRIVE VDD VDD sg13_lv_pmos m=1 w=1.5u l=130.00n ng=1 ++ nrd=0 nrs=0 +MTWP BLT BLT_PMOS_DRIVE VDD VDD sg13_lv_pmos m=1 w=1.5u l=130.00n ng=1 ++ nrd=0 nrs=0 +MTSP BLT_SEL SEL_N BLT VDD sg13_lv_pmos m=1 w=1.5u l=130.00n ng=1 nrd=0 ++ nrs=0 +MTPR BLT PRE_N VDD VDD sg13_lv_pmos m=1 w=3.000u l=130.00n ng=2 nrd=0 ++ nrs=0 +MCSP BLC_SEL SEL_N BLC VDD sg13_lv_pmos m=1 w=1.5u l=130.00n ng=1 nrd=0 ++ nrs=0 +MCPR BLC PRE_N VDD VDD sg13_lv_pmos m=1 w=3.000u l=130.00n ng=2 nrd=0 ++ nrs=0 +XI86 SEL_P SEL_N VDD VSS / RSC_IHPSG13_INVX2 +XTINV BLC_PMOS_DRIVE BLT_NMOS_DRIVE VDD VSS / RSC_IHPSG13_INVX2 +XCINV BLT_PMOS_DRIVE BLC_NMOS_DRIVE VDD VSS / RSC_IHPSG13_INVX2 +.ENDS +.SUBCKT RSC_IHPSG13_TIEH Z VDD VSS +MN0 net2 net2 VSS VSS sg13_lv_nmos m=1 w=480.00n l=130.00n ng=1 nrd=0 ++ nrs=0 +MP0 Z net2 VDD VDD sg13_lv_pmos m=1 w=480.00n l=130.00n ng=1 nrd=0 ++ nrs=0 +.ENDS +.SUBCKT RSC_IHPSG13_MET3RES A B +R0 B A lvsres w=2.6e-07 l=6e-07 +.ENDS +.SUBCKT RSC_IHPSG13_DFPQD_MSAFFX2 CP DN DP QN QP VDD VSS +MN12 SN RN DIFFP VSS sg13_lv_nmos m=1 w=2.4u l=200.0n ng=2 nrd=0 nrs=0 +MN13 TAIL CP VSS VSS sg13_lv_nmos m=1 w=2.4u l=130.00n ng=2 nrd=0 nrs=0 +MN9 DIFFP DP TAIL VSS sg13_lv_nmos m=1 w=2.4u l=200.0n ng=2 nrd=0 nrs=0 +MN10 DIFFN DN TAIL VSS sg13_lv_nmos m=1 w=2.4u l=200.0n ng=2 nrd=0 nrs=0 +MN11 RN SN DIFFN VSS sg13_lv_nmos m=1 w=2.4u l=200.0n ng=2 nrd=0 nrs=0 +MN19 net33 SN VSS VSS sg13_lv_nmos m=1 w=980.00n l=130.00n ng=1 nrd=0 ++ nrs=0 +MN20 QN QP net37 VSS sg13_lv_nmos m=1 w=980.00n l=130.00n ng=1 nrd=0 nrs=0 +MN18 net37 RN VSS VSS sg13_lv_nmos m=1 w=980.00n l=130.00n ng=1 nrd=0 ++ nrs=0 +MN17 QP QN net33 VSS sg13_lv_nmos m=1 w=980.00n l=130.00n ng=1 nrd=0 nrs=0 +MP15 SN RN VDD VDD sg13_lv_pmos m=1 w=800.0n l=130.00n ng=1 nrd=0 nrs=0 +MP16 RN CP VDD VDD sg13_lv_pmos m=1 w=800.0n l=130.00n ng=1 nrd=0 nrs=0 +MP14 DIFFP CP VDD VDD sg13_lv_pmos m=1 w=800.0n l=130.00n ng=1 nrd=0 ++ nrs=0 +MP12 RN SN VDD VDD sg13_lv_pmos m=1 w=800.0n l=130.00n ng=1 nrd=0 nrs=0 +MP13 DIFFN CP VDD VDD sg13_lv_pmos m=1 w=800.0n l=130.00n ng=1 nrd=0 ++ nrs=0 +MP11 SN CP VDD VDD sg13_lv_pmos m=1 w=800.0n l=130.00n ng=1 nrd=0 nrs=0 +MP19 QN QP VDD VDD sg13_lv_pmos m=1 w=900.0n l=130.00n ng=1 nrd=0 nrs=0 +MP20 QP SN VDD VDD sg13_lv_pmos m=1 w=1.8u l=130.00n ng=2 nrd=0 nrs=0 +MP18 QN RN VDD VDD sg13_lv_pmos m=1 w=1.8u l=130.00n ng=2 nrd=0 nrs=0 +MP17 QP QN VDD VDD sg13_lv_pmos m=1 w=900.0n l=130.00n ng=1 nrd=0 nrs=0 +.ENDS +.SUBCKT RSC_IHPSG13_CBUFX2 A Z VDD VSS +MN1 Z net4 VSS VSS sg13_lv_nmos m=1 w=705.000n l=130.00n ng=1 nrd=0 ++ nrs=0 +MN0 net4 A VSS VSS sg13_lv_nmos m=1 w=540.00n l=130.00n ng=1 nrd=0 ++ nrs=0 +MP1 Z net4 VDD VDD sg13_lv_pmos m=1 w=1.62u l=130.00n ng=1 nrd=0 nrs=0 +MP0 net4 A VDD VDD sg13_lv_pmos m=1 w=1.1u l=130.00n ng=1 nrd=0 nrs=0 +.ENDS +.SUBCKT RSC_IHPSG13_INVX4 A Z VDD VSS +MN0 Z A VSS VSS sg13_lv_nmos m=1 w=1.96u l=130.00n ng=2 nrd=0 nrs=0 +MP0 Z A VDD VDD sg13_lv_pmos m=1 w=3.24u l=130.00n ng=2 nrd=0 nrs=0 +.ENDS +.SUBCKT RM_IHPSG13_256x16_c2_1P_COLCTRL2 A_ADDR_DEC<3> A_ADDR_DEC<2> A_ADDR_DEC<1> ++ A_ADDR_DEC<0> A_BIST_BM_I A_BIST_DW_I A_BIST_EN_I A_BLC<3> A_BLC<2> A_BLC<1> ++ A_BLC<0> A_BLT<3> A_BLT<2> A_BLT<1> A_BLT<0> A_BM_I A_DCLK_B_L A_DCLK_B_R ++ A_DCLK_L A_DCLK_R A_DR_O A_DW_I A_RCLK_B_L A_RCLK_B_R A_RCLK_L A_RCLK_R ++ A_TIEH_O A_WCLK_B_L A_WCLK_B_R A_WCLK_L A_WCLK_R VDD VSS +XA_DREG A_BIST_EN_I A_BIST_DW_I A_DCLK_B_L A_DW_I A_DI_R net22 VDD VSS ++ / RSC_IHPSG13_DFNQMX2IX1 +XA_BREG A_BIST_EN_I A_BIST_BM_I A_DCLK_B_L A_BM_I A_BM_R net23 VDD VSS ++ / RSC_IHPSG13_DFNQMX2IX1 +XA_CAPS<5> VDD VSS / RSC_IHPSG13_FILLCAP4 +XA_CAPS<4> VDD VSS / RSC_IHPSG13_FILLCAP4 +XA_CAPS<3> VDD VSS / RSC_IHPSG13_FILLCAP4 +XA_CAPS<2> VDD VSS / RSC_IHPSG13_FILLCAP4 +XA_CAPS<1> VDD VSS / RSC_IHPSG13_FILLCAP4 +XA_I80 A_WCLK_B_R A_RCLK_B_R net21 VDD VSS / RSC_IHPSG13_AND2X2 +XA_I75 A_DI_R A_DO_WRITE_P A_WR_ONE VDD VSS / RSC_IHPSG13_AND2X2 +XA_I76 A_DI_N A_DO_WRITE_P A_WR_ZERO VDD VSS / RSC_IHPSG13_AND2X2 +XA_I44 A_WCLK_B_R A_BM_N A_DO_WRITE_P VDD VSS / RSC_IHPSG13_NOR2X2 +XA_I81 net21 A_PRE_N VDD VSS / RSC_IHPSG13_CINVX4_WN +XA_BLTMUX<3> A_BLC<3> A_BLC_SEL A_BLT<3> A_BLT_SEL A_PRE_N A_ADDR_DEC<3> ++ A_WR_ONE A_WR_ZERO VDD VSS / RM_IHPSG13_256x16_c2_1P_BLDRV +XA_BLTMUX<2> A_BLC<2> A_BLC_SEL A_BLT<2> A_BLT_SEL A_PRE_N A_ADDR_DEC<2> ++ A_WR_ONE A_WR_ZERO VDD VSS / RM_IHPSG13_256x16_c2_1P_BLDRV +XA_BLTMUX<1> A_BLC<1> A_BLC_SEL A_BLT<1> A_BLT_SEL A_PRE_N A_ADDR_DEC<1> ++ A_WR_ONE A_WR_ZERO VDD VSS / RM_IHPSG13_256x16_c2_1P_BLDRV +XA_BLTMUX<0> A_BLC<0> A_BLC_SEL A_BLT<0> A_BLT_SEL A_PRE_N A_ADDR_DEC<0> ++ A_WR_ONE A_WR_ZERO VDD VSS / RM_IHPSG13_256x16_c2_1P_BLDRV +XA_BM_TIEH A_TIEH_O VDD VSS / RSC_IHPSG13_TIEH +XA_I89 A_DCLK_B_L A_DCLK_B_R / RSC_IHPSG13_MET3RES +XA_I88 A_DCLK_L A_DCLK_R / RSC_IHPSG13_MET3RES +XA_I87 A_WCLK_L A_WCLK_R / RSC_IHPSG13_MET3RES +XA_I91 A_RCLK_B_R A_RCLK_B_L / RSC_IHPSG13_MET3RES +XA_R2 A_RCLK_R A_RCLK_L / RSC_IHPSG13_MET3RES +XA_I90 A_WCLK_B_R A_WCLK_B_L / RSC_IHPSG13_MET3RES +XA_ISENSE A_SAE A_BLC_SEL A_BLT_SEL net19 net20 VDD VSS / ++ RSC_IHPSG13_DFPQD_MSAFFX2 +XA_I78 A_RCLK_B_R A_SAE VDD VSS / RSC_IHPSG13_CBUFX2 +XA_I83 A_BM_R A_BM_N VDD VSS / RSC_IHPSG13_INVX2 +XA_I49 A_DI_R A_DI_N VDD VSS / RSC_IHPSG13_INVX2 +XA_I51 net19 A_DR_O VDD VSS / RSC_IHPSG13_INVX4 +XA_I69 A_DCLK_L A_DCLK_B_L VDD VSS / RSC_IHPSG13_CINVX2 +XA_I50 A_WCLK_L A_WCLK_B_R VDD VSS / RSC_IHPSG13_CINVX2 +XA_EBUF A_RCLK_R A_RCLK_B_R VDD VSS / RSC_IHPSG13_CINVX2 +.ENDS +.SUBCKT RM_IHPSG13_256x16_c2_1P_COLDRV13_FILL4 VDD VSS +XI0<9> VDD VSS / RSC_IHPSG13_FILLCAP4 +XI0<8> VDD VSS / RSC_IHPSG13_FILLCAP4 +XI0<7> VDD VSS / RSC_IHPSG13_FILLCAP4 +XI0<6> VDD VSS / RSC_IHPSG13_FILLCAP4 +XI0<5> VDD VSS / RSC_IHPSG13_FILLCAP4 +XI0<4> VDD VSS / RSC_IHPSG13_FILLCAP4 +XI0<3> VDD VSS / RSC_IHPSG13_FILLCAP4 +XI0<2> VDD VSS / RSC_IHPSG13_FILLCAP4 +XI0<1> VDD VSS / RSC_IHPSG13_FILLCAP4 +.ENDS +.SUBCKT RM_IHPSG13_256x16_c2_1P_COLDRV13_FILL4C2 VDD VSS +XI0<2> VDD VSS / RSC_IHPSG13_FILLCAP4 +XI0<1> VDD VSS / RSC_IHPSG13_FILLCAP4 +.ENDS + + +.SUBCKT RM_IHPSG13_256x16_c2_1P_COLDEC4 ACLK_N ADDR<3> ADDR<2> ADDR<1> ADDR<0> ++ ADDR_COL<1> ADDR_COL<0> ADDR_DEC<7> ADDR_DEC<6> ADDR_DEC<5> ADDR_DEC<4> ++ ADDR_DEC<3> ADDR_DEC<2> ADDR_DEC<1> ADDR_DEC<0> BIST_ADDR<3> BIST_ADDR<2> ++ BIST_ADDR<1> BIST_ADDR<0> BIST_EN_I VDD VSS +XI15 ADDR_COL<1> VDD VSS / RSC_IHPSG13_TIEL +XI14 addr_int ADDR_COL<0> VDD VSS / RSC_IHPSG13_CBUFX2 +XDFF<3> BIST_EN_I BIST_ADDR<3> ACLK_N ADDR<3> addr_int net7<0> VDD VSS ++ / RSC_IHPSG13_DFNQMX2IX1 +XDFF<2> BIST_EN_I BIST_ADDR<2> ACLK_N ADDR<2> padr_int<2> net7<1> VDD ++ VSS / RSC_IHPSG13_DFNQMX2IX1 +XDFF<1> BIST_EN_I BIST_ADDR<1> ACLK_N ADDR<1> padr_int<1> net7<2> VDD ++ VSS / RSC_IHPSG13_DFNQMX2IX1 +XDFF<0> BIST_EN_I BIST_ADDR<0> ACLK_N ADDR<0> padr_int<0> net7<3> VDD ++ VSS / RSC_IHPSG13_DFNQMX2IX1 +XI1<7> PADR<0> PADR<1> PADR<2> addr_n<7> VDD VSS / RSC_IHPSG13_NAND3X2 +XI1<6> NADR<0> PADR<1> PADR<2> addr_n<6> VDD VSS / RSC_IHPSG13_NAND3X2 +XI1<5> PADR<0> NADR<1> PADR<2> addr_n<5> VDD VSS / RSC_IHPSG13_NAND3X2 +XI1<4> NADR<0> NADR<1> PADR<2> addr_n<4> VDD VSS / RSC_IHPSG13_NAND3X2 +XI1<3> PADR<0> PADR<1> NADR<2> addr_n<3> VDD VSS / RSC_IHPSG13_NAND3X2 +XI1<2> NADR<0> PADR<1> NADR<2> addr_n<2> VDD VSS / RSC_IHPSG13_NAND3X2 +XI1<1> PADR<0> NADR<1> NADR<2> addr_n<1> VDD VSS / RSC_IHPSG13_NAND3X2 +XI1<0> NADR<0> NADR<1> NADR<2> addr_n<0> VDD VSS / RSC_IHPSG13_NAND3X2 +XI13<2> NADR<2> PADR<2> VDD VSS / RSC_IHPSG13_INVX2 +XI13<1> NADR<1> PADR<1> VDD VSS / RSC_IHPSG13_INVX2 +XI13<0> NADR<0> PADR<0> VDD VSS / RSC_IHPSG13_INVX2 +XI3<2> padr_int<2> NADR<2> VDD VSS / RSC_IHPSG13_INVX2 +XI3<1> padr_int<1> NADR<1> VDD VSS / RSC_IHPSG13_INVX2 +XI3<0> padr_int<0> NADR<0> VDD VSS / RSC_IHPSG13_INVX2 +XI2<7> addr_n<7> ADDR_DEC<7> VDD VSS / RSC_IHPSG13_INVX2 +XI2<6> addr_n<6> ADDR_DEC<6> VDD VSS / RSC_IHPSG13_INVX2 +XI2<5> addr_n<5> ADDR_DEC<5> VDD VSS / RSC_IHPSG13_INVX2 +XI2<4> addr_n<4> ADDR_DEC<4> VDD VSS / RSC_IHPSG13_INVX2 +XI2<3> addr_n<3> ADDR_DEC<3> VDD VSS / RSC_IHPSG13_INVX2 +XI2<2> addr_n<2> ADDR_DEC<2> VDD VSS / RSC_IHPSG13_INVX2 +XI2<1> addr_n<1> ADDR_DEC<1> VDD VSS / RSC_IHPSG13_INVX2 +XI2<0> addr_n<0> ADDR_DEC<0> VDD VSS / RSC_IHPSG13_INVX2 +XI16<3> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI16<2> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI16<1> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI17<2> VDD VSS / RSC_IHPSG13_FILLCAP4 +XI17<1> VDD VSS / RSC_IHPSG13_FILLCAP4 +.ENDS +.SUBCKT RSC_IHPSG13_AND2X4 A B Z VDD VSS +MN3 Z net6 VSS VSS sg13_lv_nmos m=1 w=1.96u l=130.00n ng=2 nrd=0 nrs=0 +MN4 net9 B VSS VSS sg13_lv_nmos m=1 w=500.0n l=130.00n ng=1 nrd=0 nrs=0 +MN6 net6 A net9 VSS sg13_lv_nmos m=1 w=500.0n l=130.00n ng=1 nrd=0 nrs=0 +MP2 Z net6 VDD VDD sg13_lv_pmos m=1 w=3.24u l=130.00n ng=2 nrd=0 nrs=0 +MP0 net6 B VDD VDD sg13_lv_pmos m=1 w=860.00n l=130.00n ng=1 nrd=0 ++ nrs=0 +MP1 net6 A VDD VDD sg13_lv_pmos m=1 w=860.00n l=130.00n ng=1 nrd=0 ++ nrs=0 +.ENDS +.SUBCKT RM_IHPSG13_256x16_c2_1P_COLCTRL4 A_ADDR_COL A_ADDR_DEC<7> A_ADDR_DEC<6> ++ A_ADDR_DEC<5> A_ADDR_DEC<4> A_ADDR_DEC<3> A_ADDR_DEC<2> A_ADDR_DEC<1> ++ A_ADDR_DEC<0> A_BIST_BM_I A_BIST_DW_I A_BIST_EN_I A_BLC<15> A_BLC<14> ++ A_BLC<13> A_BLC<12> A_BLC<11> A_BLC<10> A_BLC<9> A_BLC<8> A_BLC<7> A_BLC<6> ++ A_BLC<5> A_BLC<4> A_BLC<3> A_BLC<2> A_BLC<1> A_BLC<0> A_BLT<15> A_BLT<14> ++ A_BLT<13> A_BLT<12> A_BLT<11> A_BLT<10> A_BLT<9> A_BLT<8> A_BLT<7> A_BLT<6> ++ A_BLT<5> A_BLT<4> A_BLT<3> A_BLT<2> A_BLT<1> A_BLT<0> A_BM_I A_DCLK_B_L ++ A_DCLK_B_R A_DCLK_L A_DCLK_R A_DR_O A_DW_I A_RCLK_B_L A_RCLK_B_R A_RCLK_L ++ A_RCLK_R A_TIEH_O A_WCLK_B_L A_WCLK_B_R A_WCLK_L A_WCLK_R VDD VSS +XA_I80 A_WCLK_B_L A_RCLK_B_L net21 VDD VSS / RSC_IHPSG13_AND2X2 +XA_I76 A_DO_WRITE_P A_DI_N A_WR_ZERO VDD VSS / RSC_IHPSG13_AND2X4 +XA_I75 A_DI_R A_DO_WRITE_P A_WR_ONE VDD VSS / RSC_IHPSG13_AND2X4 +XA_CAPS<8> VDD VSS / RSC_IHPSG13_FILLCAP4 +XA_CAPS<7> VDD VSS / RSC_IHPSG13_FILLCAP4 +XA_CAPS<6> VDD VSS / RSC_IHPSG13_FILLCAP4 +XA_CAPS<5> VDD VSS / RSC_IHPSG13_FILLCAP4 +XA_CAPS<4> VDD VSS / RSC_IHPSG13_FILLCAP4 +XA_CAPS<3> VDD VSS / RSC_IHPSG13_FILLCAP4 +XA_CAPS<2> VDD VSS / RSC_IHPSG13_FILLCAP4 +XA_CAPS<1> VDD VSS / RSC_IHPSG13_FILLCAP4 +XA_I69 A_DCLK_L A_DCLK_B_L VDD VSS / RSC_IHPSG13_CINVX4 +XA_I50 A_WCLK_L A_WCLK_B_L VDD VSS / RSC_IHPSG13_CINVX4 +XA_EBUF A_RCLK_L A_RCLK_B_L VDD VSS / RSC_IHPSG13_CINVX4 +XA_INV<1> A_N0 A_P0 VDD VSS / RSC_IHPSG13_CINVX4 +XA_INV<0> A_ADDR_COL A_N0 VDD VSS / RSC_IHPSG13_CINVX4 +XA_I81<1> net21 A_PRE_N VDD VSS / RSC_IHPSG13_CINVX4_WN +XA_I81<0> net21 A_PRE_N VDD VSS / RSC_IHPSG13_CINVX4_WN +XA_BLTMUX<15> A_BLC<15> A_BLC_SEL A_BLT<15> A_BLT_SEL A_PRE_N A_SEL_P<15> ++ A_WR_ONE A_WR_ZERO VDD VSS / RM_IHPSG13_256x16_c2_1P_BLDRV +XA_BLTMUX<14> A_BLC<14> A_BLC_SEL A_BLT<14> A_BLT_SEL A_PRE_N A_SEL_P<14> ++ A_WR_ONE A_WR_ZERO VDD VSS / RM_IHPSG13_256x16_c2_1P_BLDRV +XA_BLTMUX<13> A_BLC<13> A_BLC_SEL A_BLT<13> A_BLT_SEL A_PRE_N A_SEL_P<13> ++ A_WR_ONE A_WR_ZERO VDD VSS / RM_IHPSG13_256x16_c2_1P_BLDRV +XA_BLTMUX<12> A_BLC<12> A_BLC_SEL A_BLT<12> A_BLT_SEL A_PRE_N A_SEL_P<12> ++ A_WR_ONE A_WR_ZERO VDD VSS / RM_IHPSG13_256x16_c2_1P_BLDRV +XA_BLTMUX<11> A_BLC<11> A_BLC_SEL A_BLT<11> A_BLT_SEL A_PRE_N A_SEL_P<11> ++ A_WR_ONE A_WR_ZERO VDD VSS / RM_IHPSG13_256x16_c2_1P_BLDRV +XA_BLTMUX<10> A_BLC<10> A_BLC_SEL A_BLT<10> A_BLT_SEL A_PRE_N A_SEL_P<10> ++ A_WR_ONE A_WR_ZERO VDD VSS / RM_IHPSG13_256x16_c2_1P_BLDRV +XA_BLTMUX<9> A_BLC<9> A_BLC_SEL A_BLT<9> A_BLT_SEL A_PRE_N A_SEL_P<9> A_WR_ONE ++ A_WR_ZERO VDD VSS / RM_IHPSG13_256x16_c2_1P_BLDRV +XA_BLTMUX<8> A_BLC<8> A_BLC_SEL A_BLT<8> A_BLT_SEL A_PRE_N A_SEL_P<8> A_WR_ONE ++ A_WR_ZERO VDD VSS / RM_IHPSG13_256x16_c2_1P_BLDRV +XA_BLTMUX<7> A_BLC<7> A_BLC_SEL A_BLT<7> A_BLT_SEL A_PRE_N A_SEL_P<7> A_WR_ONE ++ A_WR_ZERO VDD VSS / RM_IHPSG13_256x16_c2_1P_BLDRV +XA_BLTMUX<6> A_BLC<6> A_BLC_SEL A_BLT<6> A_BLT_SEL A_PRE_N A_SEL_P<6> A_WR_ONE ++ A_WR_ZERO VDD VSS / RM_IHPSG13_256x16_c2_1P_BLDRV +XA_BLTMUX<5> A_BLC<5> A_BLC_SEL A_BLT<5> A_BLT_SEL A_PRE_N A_SEL_P<5> A_WR_ONE ++ A_WR_ZERO VDD VSS / RM_IHPSG13_256x16_c2_1P_BLDRV +XA_BLTMUX<4> A_BLC<4> A_BLC_SEL A_BLT<4> A_BLT_SEL A_PRE_N A_SEL_P<4> A_WR_ONE ++ A_WR_ZERO VDD VSS / RM_IHPSG13_256x16_c2_1P_BLDRV +XA_BLTMUX<3> A_BLC<3> A_BLC_SEL A_BLT<3> A_BLT_SEL A_PRE_N A_SEL_P<3> A_WR_ONE ++ A_WR_ZERO VDD VSS / RM_IHPSG13_256x16_c2_1P_BLDRV +XA_BLTMUX<2> A_BLC<2> A_BLC_SEL A_BLT<2> A_BLT_SEL A_PRE_N A_SEL_P<2> A_WR_ONE ++ A_WR_ZERO VDD VSS / RM_IHPSG13_256x16_c2_1P_BLDRV +XA_BLTMUX<1> A_BLC<1> A_BLC_SEL A_BLT<1> A_BLT_SEL A_PRE_N A_SEL_P<1> A_WR_ONE ++ A_WR_ZERO VDD VSS / RM_IHPSG13_256x16_c2_1P_BLDRV +XA_BLTMUX<0> A_BLC<0> A_BLC_SEL A_BLT<0> A_BLT_SEL A_PRE_N A_SEL_P<0> A_WR_ONE ++ A_WR_ZERO VDD VSS / RM_IHPSG13_256x16_c2_1P_BLDRV +XA_R2 A_RCLK_L A_RCLK_R / RSC_IHPSG13_MET3RES +XA_I87 A_WCLK_L A_WCLK_R / RSC_IHPSG13_MET3RES +XA_I88 A_DCLK_L A_DCLK_R / RSC_IHPSG13_MET3RES +XA_I89 A_DCLK_B_L A_DCLK_B_R / RSC_IHPSG13_MET3RES +XA_I90 A_WCLK_B_L A_WCLK_B_R / RSC_IHPSG13_MET3RES +XA_I91 A_RCLK_B_L A_RCLK_B_R / RSC_IHPSG13_MET3RES +XA_ISENSE A_SAE A_BLC_SEL A_BLT_SEL net19 net20 VDD VSS / ++ RSC_IHPSG13_DFPQD_MSAFFX2 +XA_I51 net19 A_DR_O VDD VSS / RSC_IHPSG13_INVX4 +XA_I78 A_RCLK_B_L A_SAE VDD VSS / RSC_IHPSG13_CBUFX2 +XA_DREG A_BIST_EN_I A_BIST_DW_I A_DCLK_B_L A_DW_I A_DI_R net22 VDD VSS ++ / RSC_IHPSG13_DFNQMX2IX1 +XA_BREG A_BIST_EN_I A_BIST_BM_I A_DCLK_B_L A_BM_I A_BM_R net24 VDD VSS ++ / RSC_IHPSG13_DFNQMX2IX1 +XA_DEC3INV<15> net23<0> A_SEL_P<15> VDD VSS / RSC_IHPSG13_INVX2 +XA_DEC3INV<14> net23<1> A_SEL_P<14> VDD VSS / RSC_IHPSG13_INVX2 +XA_DEC3INV<13> net23<2> A_SEL_P<13> VDD VSS / RSC_IHPSG13_INVX2 +XA_DEC3INV<12> net23<3> A_SEL_P<12> VDD VSS / RSC_IHPSG13_INVX2 +XA_DEC3INV<11> net23<4> A_SEL_P<11> VDD VSS / RSC_IHPSG13_INVX2 +XA_DEC3INV<10> net23<5> A_SEL_P<10> VDD VSS / RSC_IHPSG13_INVX2 +XA_DEC3INV<9> net23<6> A_SEL_P<9> VDD VSS / RSC_IHPSG13_INVX2 +XA_DEC3INV<8> net23<7> A_SEL_P<8> VDD VSS / RSC_IHPSG13_INVX2 +XA_DEC3INV<7> net23<8> A_SEL_P<7> VDD VSS / RSC_IHPSG13_INVX2 +XA_DEC3INV<6> net23<9> A_SEL_P<6> VDD VSS / RSC_IHPSG13_INVX2 +XA_DEC3INV<5> net23<10> A_SEL_P<5> VDD VSS / RSC_IHPSG13_INVX2 +XA_DEC3INV<4> net23<11> A_SEL_P<4> VDD VSS / RSC_IHPSG13_INVX2 +XA_DEC3INV<3> net23<12> A_SEL_P<3> VDD VSS / RSC_IHPSG13_INVX2 +XA_DEC3INV<2> net23<13> A_SEL_P<2> VDD VSS / RSC_IHPSG13_INVX2 +XA_DEC3INV<1> net23<14> A_SEL_P<1> VDD VSS / RSC_IHPSG13_INVX2 +XA_DEC3INV<0> net23<15> A_SEL_P<0> VDD VSS / RSC_IHPSG13_INVX2 +XA_I83 A_BM_R A_BM_N VDD VSS / RSC_IHPSG13_INVX2 +XA_I49 A_DI_R A_DI_N VDD VSS / RSC_IHPSG13_INVX2 +XA_I70<4> VDD VSS / RSC_IHPSG13_FILLCAP8 +XA_I70<3> VDD VSS / RSC_IHPSG13_FILLCAP8 +XA_I70<2> VDD VSS / RSC_IHPSG13_FILLCAP8 +XA_I70<1> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI73<14> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI73<13> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI73<12> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI73<11> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI73<10> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI73<9> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI73<8> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI73<7> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI73<6> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI73<5> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI73<4> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI73<3> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI73<2> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI73<1> VDD VSS / RSC_IHPSG13_FILLCAP8 +XA_I44 A_BM_N A_WCLK_B_L A_DO_WRITE_P VDD VSS / RSC_IHPSG13_NOR2X2 +XA_DEC3<15> A_P0 A_ADDR_DEC<7> net23<0> VDD VSS / RSC_IHPSG13_NAND2X2 +XA_DEC3<14> A_P0 A_ADDR_DEC<6> net23<1> VDD VSS / RSC_IHPSG13_NAND2X2 +XA_DEC3<13> A_P0 A_ADDR_DEC<5> net23<2> VDD VSS / RSC_IHPSG13_NAND2X2 +XA_DEC3<12> A_P0 A_ADDR_DEC<4> net23<3> VDD VSS / RSC_IHPSG13_NAND2X2 +XA_DEC3<11> A_P0 A_ADDR_DEC<3> net23<4> VDD VSS / RSC_IHPSG13_NAND2X2 +XA_DEC3<10> A_P0 A_ADDR_DEC<2> net23<5> VDD VSS / RSC_IHPSG13_NAND2X2 +XA_DEC3<9> A_P0 A_ADDR_DEC<1> net23<6> VDD VSS / RSC_IHPSG13_NAND2X2 +XA_DEC3<8> A_P0 A_ADDR_DEC<0> net23<7> VDD VSS / RSC_IHPSG13_NAND2X2 +XA_DEC3<7> A_N0 A_ADDR_DEC<7> net23<8> VDD VSS / RSC_IHPSG13_NAND2X2 +XA_DEC3<6> A_N0 A_ADDR_DEC<6> net23<9> VDD VSS / RSC_IHPSG13_NAND2X2 +XA_DEC3<5> A_N0 A_ADDR_DEC<5> net23<10> VDD VSS / RSC_IHPSG13_NAND2X2 +XA_DEC3<4> A_N0 A_ADDR_DEC<4> net23<11> VDD VSS / RSC_IHPSG13_NAND2X2 +XA_DEC3<3> A_N0 A_ADDR_DEC<3> net23<12> VDD VSS / RSC_IHPSG13_NAND2X2 +XA_DEC3<2> A_N0 A_ADDR_DEC<2> net23<13> VDD VSS / RSC_IHPSG13_NAND2X2 +XA_DEC3<1> A_N0 A_ADDR_DEC<1> net23<14> VDD VSS / RSC_IHPSG13_NAND2X2 +XA_DEC3<0> A_N0 A_ADDR_DEC<0> net23<15> VDD VSS / RSC_IHPSG13_NAND2X2 +XA_BM_TIEH A_TIEH_O VDD VSS / RSC_IHPSG13_TIEH +.ENDS + + +.SUBCKT RM_IHPSG13_256x16_c2_1P_COLDEC3 ACLK_N ADDR<2> ADDR<1> ADDR<0> ADDR_COL<1> ++ ADDR_COL<0> ADDR_DEC<7> ADDR_DEC<6> ADDR_DEC<5> ADDR_DEC<4> ADDR_DEC<3> ++ ADDR_DEC<2> ADDR_DEC<1> ADDR_DEC<0> BIST_ADDR<2> BIST_ADDR<1> BIST_ADDR<0> ++ BIST_EN_I VDD VSS +XI15<1> ADDR_COL<1> VDD VSS / RSC_IHPSG13_TIEL +XI15<0> ADDR_COL<0> VDD VSS / RSC_IHPSG13_TIEL +XI1<7> PADR<0> PADR<1> PADR<2> addr_n<7> VDD VSS / RSC_IHPSG13_NAND3X2 +XI1<6> NADR<0> PADR<1> PADR<2> addr_n<6> VDD VSS / RSC_IHPSG13_NAND3X2 +XI1<5> PADR<0> NADR<1> PADR<2> addr_n<5> VDD VSS / RSC_IHPSG13_NAND3X2 +XI1<4> NADR<0> NADR<1> PADR<2> addr_n<4> VDD VSS / RSC_IHPSG13_NAND3X2 +XI1<3> PADR<0> PADR<1> NADR<2> addr_n<3> VDD VSS / RSC_IHPSG13_NAND3X2 +XI1<2> NADR<0> PADR<1> NADR<2> addr_n<2> VDD VSS / RSC_IHPSG13_NAND3X2 +XI1<1> PADR<0> NADR<1> NADR<2> addr_n<1> VDD VSS / RSC_IHPSG13_NAND3X2 +XI1<0> NADR<0> NADR<1> NADR<2> addr_n<0> VDD VSS / RSC_IHPSG13_NAND3X2 +XDFF<2> BIST_EN_I BIST_ADDR<2> ACLK_N ADDR<2> padr_int<2> net6<0> VDD ++ VSS / RSC_IHPSG13_DFNQMX2IX1 +XDFF<1> BIST_EN_I BIST_ADDR<1> ACLK_N ADDR<1> padr_int<1> net6<1> VDD ++ VSS / RSC_IHPSG13_DFNQMX2IX1 +XDFF<0> BIST_EN_I BIST_ADDR<0> ACLK_N ADDR<0> padr_int<0> net6<2> VDD ++ VSS / RSC_IHPSG13_DFNQMX2IX1 +XI17<2> VDD VSS / RSC_IHPSG13_FILLCAP4 +XI17<1> VDD VSS / RSC_IHPSG13_FILLCAP4 +XI13<2> NADR<2> PADR<2> VDD VSS / RSC_IHPSG13_INVX2 +XI13<1> NADR<1> PADR<1> VDD VSS / RSC_IHPSG13_INVX2 +XI13<0> NADR<0> PADR<0> VDD VSS / RSC_IHPSG13_INVX2 +XI3<2> padr_int<2> NADR<2> VDD VSS / RSC_IHPSG13_INVX2 +XI3<1> padr_int<1> NADR<1> VDD VSS / RSC_IHPSG13_INVX2 +XI3<0> padr_int<0> NADR<0> VDD VSS / RSC_IHPSG13_INVX2 +XI2<7> addr_n<7> ADDR_DEC<7> VDD VSS / RSC_IHPSG13_INVX2 +XI2<6> addr_n<6> ADDR_DEC<6> VDD VSS / RSC_IHPSG13_INVX2 +XI2<5> addr_n<5> ADDR_DEC<5> VDD VSS / RSC_IHPSG13_INVX2 +XI2<4> addr_n<4> ADDR_DEC<4> VDD VSS / RSC_IHPSG13_INVX2 +XI2<3> addr_n<3> ADDR_DEC<3> VDD VSS / RSC_IHPSG13_INVX2 +XI2<2> addr_n<2> ADDR_DEC<2> VDD VSS / RSC_IHPSG13_INVX2 +XI2<1> addr_n<1> ADDR_DEC<1> VDD VSS / RSC_IHPSG13_INVX2 +XI2<0> addr_n<0> ADDR_DEC<0> VDD VSS / RSC_IHPSG13_INVX2 +XI16<6> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI16<5> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI16<4> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI16<3> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI16<2> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI16<1> VDD VSS / RSC_IHPSG13_FILLCAP8 +.ENDS +.SUBCKT RM_IHPSG13_256x16_c2_1P_COLCTRL3 A_ADDR_DEC<7> A_ADDR_DEC<6> A_ADDR_DEC<5> ++ A_ADDR_DEC<4> A_ADDR_DEC<3> A_ADDR_DEC<2> A_ADDR_DEC<1> A_ADDR_DEC<0> ++ A_BIST_BM_I A_BIST_DW_I A_BIST_EN_I A_BLC<7> A_BLC<6> A_BLC<5> A_BLC<4> ++ A_BLC<3> A_BLC<2> A_BLC<1> A_BLC<0> A_BLT<7> A_BLT<6> A_BLT<5> A_BLT<4> ++ A_BLT<3> A_BLT<2> A_BLT<1> A_BLT<0> A_BM_I A_DCLK_B_L A_DCLK_B_R A_DCLK_L ++ A_DCLK_R A_DR_O A_DW_I A_RCLK_B_L A_RCLK_B_R A_RCLK_L A_RCLK_R A_TIEH_O ++ A_WCLK_B_L A_WCLK_B_R A_WCLK_L A_WCLK_R VDD VSS +XA_DREG A_BIST_EN_I A_BIST_DW_I A_DCLK_B_L A_DW_I A_DI_R net22 VDD VSS ++ / RSC_IHPSG13_DFNQMX2IX1 +XA_BREG A_BIST_EN_I A_BIST_BM_I A_DCLK_B_R A_BM_I A_BM_R net23 VDD VSS ++ / RSC_IHPSG13_DFNQMX2IX1 +XA_I70<8> VDD VSS / RSC_IHPSG13_FILLCAP8 +XA_I70<7> VDD VSS / RSC_IHPSG13_FILLCAP8 +XA_I70<6> VDD VSS / RSC_IHPSG13_FILLCAP8 +XA_I70<5> VDD VSS / RSC_IHPSG13_FILLCAP8 +XA_I70<4> VDD VSS / RSC_IHPSG13_FILLCAP8 +XA_I70<3> VDD VSS / RSC_IHPSG13_FILLCAP8 +XA_I70<2> VDD VSS / RSC_IHPSG13_FILLCAP8 +XA_I70<1> VDD VSS / RSC_IHPSG13_FILLCAP8 +XA_I51 net19 A_DR_O VDD VSS / RSC_IHPSG13_INVX4 +XA_I44 A_BM_N A_WCLK_B_R A_DO_WRITE_P VDD VSS / RSC_IHPSG13_NOR2X2 +XA_BM_TIEH A_TIEH_O VDD VSS / RSC_IHPSG13_TIEH +XA_BLTMUX<7> A_BLC<7> A_BLC_SEL A_BLT<7> A_BLT_SEL A_PRE_N A_ADDR_DEC<7> ++ A_WR_ONE A_WR_ZERO VDD VSS / RM_IHPSG13_256x16_c2_1P_BLDRV +XA_BLTMUX<6> A_BLC<6> A_BLC_SEL A_BLT<6> A_BLT_SEL A_PRE_N A_ADDR_DEC<6> ++ A_WR_ONE A_WR_ZERO VDD VSS / RM_IHPSG13_256x16_c2_1P_BLDRV +XA_BLTMUX<5> A_BLC<5> A_BLC_SEL A_BLT<5> A_BLT_SEL A_PRE_N A_ADDR_DEC<5> ++ A_WR_ONE A_WR_ZERO VDD VSS / RM_IHPSG13_256x16_c2_1P_BLDRV +XA_BLTMUX<4> A_BLC<4> A_BLC_SEL A_BLT<4> A_BLT_SEL A_PRE_N A_ADDR_DEC<4> ++ A_WR_ONE A_WR_ZERO VDD VSS / RM_IHPSG13_256x16_c2_1P_BLDRV +XA_BLTMUX<3> A_BLC<3> A_BLC_SEL A_BLT<3> A_BLT_SEL A_PRE_N A_ADDR_DEC<3> ++ A_WR_ONE A_WR_ZERO VDD VSS / RM_IHPSG13_256x16_c2_1P_BLDRV +XA_BLTMUX<2> A_BLC<2> A_BLC_SEL A_BLT<2> A_BLT_SEL A_PRE_N A_ADDR_DEC<2> ++ A_WR_ONE A_WR_ZERO VDD VSS / RM_IHPSG13_256x16_c2_1P_BLDRV +XA_BLTMUX<1> A_BLC<1> A_BLC_SEL A_BLT<1> A_BLT_SEL A_PRE_N A_ADDR_DEC<1> ++ A_WR_ONE A_WR_ZERO VDD VSS / RM_IHPSG13_256x16_c2_1P_BLDRV +XA_BLTMUX<0> A_BLC<0> A_BLC_SEL A_BLT<0> A_BLT_SEL A_PRE_N A_ADDR_DEC<0> ++ A_WR_ONE A_WR_ZERO VDD VSS / RM_IHPSG13_256x16_c2_1P_BLDRV +XA_I49 A_DI_R A_DI_N VDD VSS / RSC_IHPSG13_INVX2 +XA_I83 A_BM_R A_BM_N VDD VSS / RSC_IHPSG13_INVX2 +XA_I69 A_DCLK_L A_DCLK_B_L VDD VSS / RSC_IHPSG13_CINVX2 +XA_I50 A_WCLK_L A_WCLK_B_L VDD VSS / RSC_IHPSG13_CINVX2 +XA_EBUF A_RCLK_L A_RCLK_B_L VDD VSS / RSC_IHPSG13_CINVX2 +XA_I78 A_RCLK_B_L A_SAE VDD VSS / RSC_IHPSG13_CBUFX2 +XA_I88 A_DCLK_L A_DCLK_R / RSC_IHPSG13_MET3RES +XA_I87 A_WCLK_L A_WCLK_R / RSC_IHPSG13_MET3RES +XA_R2 A_RCLK_L A_RCLK_R / RSC_IHPSG13_MET3RES +XA_I91 A_RCLK_B_L A_RCLK_B_R / RSC_IHPSG13_MET3RES +XA_I90 A_WCLK_B_L A_WCLK_B_R / RSC_IHPSG13_MET3RES +XA_I89 A_DCLK_B_L A_DCLK_B_R / RSC_IHPSG13_MET3RES +XA_I80 A_WCLK_B_R A_RCLK_B_R net21 VDD VSS / RSC_IHPSG13_AND2X2 +XA_I76 A_DI_N A_DO_WRITE_P A_WR_ZERO VDD VSS / RSC_IHPSG13_AND2X2 +XA_I75 A_DI_R A_DO_WRITE_P A_WR_ONE VDD VSS / RSC_IHPSG13_AND2X2 +XA_ISENSE A_SAE A_BLC_SEL A_BLT_SEL net19 net20 VDD VSS / ++ RSC_IHPSG13_DFPQD_MSAFFX2 +XA_I81 net21 A_PRE_N VDD VSS / RSC_IHPSG13_CINVX4_WN +XA_CAPS<5> VDD VSS / RSC_IHPSG13_FILLCAP4 +XA_CAPS<4> VDD VSS / RSC_IHPSG13_FILLCAP4 +XA_CAPS<3> VDD VSS / RSC_IHPSG13_FILLCAP4 +XA_CAPS<2> VDD VSS / RSC_IHPSG13_FILLCAP4 +XA_CAPS<1> VDD VSS / RSC_IHPSG13_FILLCAP4 +.ENDS + +.SUBCKT RM_IHPSG13_256x16_c2_2P_BITKIT_16x2_CORNER VDD_CORE VSS +XI16 VDD_CORE VSS VDD_CORE VSS / ++ RM_IHPSG13_256x16_c2_1P_BITKIT_CORNER +.ENDS +.SUBCKT RM_IHPSG13_256x16_c2_2P_BITKIT_EDGE_LR A_WL B_WL NW PW VDD VSS +MN1 VSS A_WL VSS VSS sg13_lv_nmos m=1 w=300.0n l=130.00n ng=1 nrd=0 nrs=0 +MN0 VSS B_WL VSS VSS sg13_lv_nmos m=1 w=300.0n l=130.00n ng=1 nrd=0 nrs=0 +.ENDS +.SUBCKT RM_IHPSG13_256x16_c2_2P_BITKIT_16x2_EDGE_LR A_WL<15> A_WL<14> A_WL<13> A_WL<12> ++ A_WL<11> A_WL<10> A_WL<9> A_WL<8> A_WL<7> A_WL<6> A_WL<5> A_WL<4> A_WL<3> ++ A_WL<2> A_WL<1> A_WL<0> B_WL<15> B_WL<14> B_WL<13> B_WL<12> B_WL<11> ++ B_WL<10> B_WL<9> B_WL<8> B_WL<7> B_WL<6> B_WL<5> B_WL<4> B_WL<3> B_WL<2> ++ B_WL<1> B_WL<0> VDD_CORE VSS +XI0<15> A_WL<15> B_WL<15> VDD_CORE VSS VDD_CORE VSS ++ / RM_IHPSG13_256x16_c2_2P_BITKIT_EDGE_LR +XI0<14> A_WL<14> B_WL<14> VDD_CORE VSS VDD_CORE VSS ++ / RM_IHPSG13_256x16_c2_2P_BITKIT_EDGE_LR +XI0<13> A_WL<13> B_WL<13> VDD_CORE VSS VDD_CORE VSS ++ / RM_IHPSG13_256x16_c2_2P_BITKIT_EDGE_LR +XI0<12> A_WL<12> B_WL<12> VDD_CORE VSS VDD_CORE VSS ++ / RM_IHPSG13_256x16_c2_2P_BITKIT_EDGE_LR +XI0<11> A_WL<11> B_WL<11> VDD_CORE VSS VDD_CORE VSS ++ / RM_IHPSG13_256x16_c2_2P_BITKIT_EDGE_LR +XI0<10> A_WL<10> B_WL<10> VDD_CORE VSS VDD_CORE VSS ++ / RM_IHPSG13_256x16_c2_2P_BITKIT_EDGE_LR +XI0<9> A_WL<9> B_WL<9> VDD_CORE VSS VDD_CORE VSS / ++ RM_IHPSG13_256x16_c2_2P_BITKIT_EDGE_LR +XI0<8> A_WL<8> B_WL<8> VDD_CORE VSS VDD_CORE VSS / ++ RM_IHPSG13_256x16_c2_2P_BITKIT_EDGE_LR +XI0<7> A_WL<7> B_WL<7> VDD_CORE VSS VDD_CORE VSS / ++ RM_IHPSG13_256x16_c2_2P_BITKIT_EDGE_LR +XI0<6> A_WL<6> B_WL<6> VDD_CORE VSS VDD_CORE VSS / ++ RM_IHPSG13_256x16_c2_2P_BITKIT_EDGE_LR +XI0<5> A_WL<5> B_WL<5> VDD_CORE VSS VDD_CORE VSS / ++ RM_IHPSG13_256x16_c2_2P_BITKIT_EDGE_LR +XI0<4> A_WL<4> B_WL<4> VDD_CORE VSS VDD_CORE VSS / ++ RM_IHPSG13_256x16_c2_2P_BITKIT_EDGE_LR +XI0<3> A_WL<3> B_WL<3> VDD_CORE VSS VDD_CORE VSS / ++ RM_IHPSG13_256x16_c2_2P_BITKIT_EDGE_LR +XI0<2> A_WL<2> B_WL<2> VDD_CORE VSS VDD_CORE VSS / ++ RM_IHPSG13_256x16_c2_2P_BITKIT_EDGE_LR +XI0<1> A_WL<1> B_WL<1> VDD_CORE VSS VDD_CORE VSS / ++ RM_IHPSG13_256x16_c2_2P_BITKIT_EDGE_LR +XI0<0> A_WL<0> B_WL<0> VDD_CORE VSS VDD_CORE VSS / ++ RM_IHPSG13_256x16_c2_2P_BITKIT_EDGE_LR +.ENDS +.SUBCKT RM_IHPSG13_256x16_c2_2P_BITKIT_CELL A_BLC_BOT A_BLC_TOP A_BLT_BOT A_BLT_TOP ++ A_LWL A_RWL B_BLC_BOT B_BLC_TOP B_BLT_BOT B_BLT_TOP B_LWL B_RWL NW PW VDD VSS +MN5 NC B_RWL B_BLC_BOT PW sg13_lv_nmos m=1 w=300.0n l=130.00n ng=1 nrd=0 nrs=0 +MN4 B_BLT_BOT B_LWL NT PW sg13_lv_nmos m=1 w=300.0n l=130.00n ng=1 nrd=0 nrs=0 +MN0 NC NT VSS PW sg13_lv_nmos m=1 w=600.0n l=130.00n ng=2 nrd=0 nrs=0 +MN1 NT NC VSS PW sg13_lv_nmos m=1 w=600.0n l=130.00n ng=2 nrd=0 nrs=0 +MN3 NC A_RWL A_BLC_TOP PW sg13_lv_nmos m=1 w=300.0n l=130.00n ng=1 nrd=0 nrs=0 +MN2 A_BLT_TOP A_LWL NT PW sg13_lv_nmos m=1 w=300.0n l=130.00n ng=1 nrd=0 nrs=0 +MP1 NT NC VDD NW sg13_lv_pmos m=1 w=150.00n l=130.00n ng=1 nrd=0 nrs=0 +MP0 NC NT VDD NW sg13_lv_pmos m=1 w=150.00n l=130.00n ng=1 nrd=0 nrs=0 +R5 B_RWL B_LWL lvsres w=2.6e-07 l=6e-07 +R4 B_BLC_BOT B_BLC_TOP lvsres w=2.6e-07 l=6e-07 +R3 B_BLT_BOT B_BLT_TOP lvsres w=2.6e-07 l=6e-07 +R1 A_BLC_BOT A_BLC_TOP lvsres w=2.6e-07 l=6e-07 +R0 A_BLT_BOT A_BLT_TOP lvsres w=2.6e-07 l=6e-07 +R2 A_RWL A_LWL lvsres w=2.6e-07 l=6e-07 +.ENDS +.SUBCKT RM_IHPSG13_256x16_c2_2P_BITKIT_16x2_SRAM A_BLC_BOT<1> A_BLC_BOT<0> A_BLC_TOP<1> ++ A_BLC_TOP<0> A_BLT_BOT<1> A_BLT_BOT<0> A_BLT_TOP<1> A_BLT_TOP<0> A_LWL<15> ++ A_LWL<14> A_LWL<13> A_LWL<12> A_LWL<11> A_LWL<10> A_LWL<9> A_LWL<8> A_LWL<7> ++ A_LWL<6> A_LWL<5> A_LWL<4> A_LWL<3> A_LWL<2> A_LWL<1> A_LWL<0> A_RWL<15> ++ A_RWL<14> A_RWL<13> A_RWL<12> A_RWL<11> A_RWL<10> A_RWL<9> A_RWL<8> A_RWL<7> ++ A_RWL<6> A_RWL<5> A_RWL<4> A_RWL<3> A_RWL<2> A_RWL<1> A_RWL<0> B_BLC_BOT<1> ++ B_BLC_BOT<0> B_BLC_TOP<1> B_BLC_TOP<0> B_BLT_BOT<1> B_BLT_BOT<0> ++ B_BLT_TOP<1> B_BLT_TOP<0> B_LWL<15> B_LWL<14> B_LWL<13> B_LWL<12> B_LWL<11> ++ B_LWL<10> B_LWL<9> B_LWL<8> B_LWL<7> B_LWL<6> B_LWL<5> B_LWL<4> B_LWL<3> ++ B_LWL<2> B_LWL<1> B_LWL<0> B_RWL<15> B_RWL<14> B_RWL<13> B_RWL<12> B_RWL<11> ++ B_RWL<10> B_RWL<9> B_RWL<8> B_RWL<7> B_RWL<6> B_RWL<5> B_RWL<4> B_RWL<3> ++ B_RWL<2> B_RWL<1> B_RWL<0> VDD_CORE VSS +XCELL<31> A_BLC_TOP<1> A_RBLC<15> A_BLT_TOP<1> A_RBLT<15> A_XWL<15> A_RWL<15> ++ B_BLC_TOP<1> B_RBLC<15> B_BLT_TOP<1> B_RBLT<15> B_XWL<15> B_RWL<15> ++ VDD_CORE VSS VDD_CORE VSS / ++ RM_IHPSG13_256x16_c2_2P_BITKIT_CELL +XCELL<30> A_RBLC<14> A_RBLC<15> A_RBLT<14> A_RBLT<15> A_XWL<14> A_RWL<14> ++ B_RBLC<14> B_RBLC<15> B_RBLT<14> B_RBLT<15> B_XWL<14> B_RWL<14> VDD_CORE ++ VSS VDD_CORE VSS / RM_IHPSG13_256x16_c2_2P_BITKIT_CELL +XCELL<29> A_RBLC<14> A_RBLC<13> A_RBLT<14> A_RBLT<13> A_XWL<13> A_RWL<13> ++ B_RBLC<14> B_RBLC<13> B_RBLT<14> B_RBLT<13> B_XWL<13> B_RWL<13> VDD_CORE ++ VSS VDD_CORE VSS / RM_IHPSG13_256x16_c2_2P_BITKIT_CELL +XCELL<28> A_RBLC<12> A_RBLC<13> A_RBLT<12> A_RBLT<13> A_XWL<12> A_RWL<12> ++ B_RBLC<12> B_RBLC<13> B_RBLT<12> B_RBLT<13> B_XWL<12> B_RWL<12> VDD_CORE ++ VSS VDD_CORE VSS / RM_IHPSG13_256x16_c2_2P_BITKIT_CELL +XCELL<27> A_RBLC<12> A_RBLC<11> A_RBLT<12> A_RBLT<11> A_XWL<11> A_RWL<11> ++ B_RBLC<12> B_RBLC<11> B_RBLT<12> B_RBLT<11> B_XWL<11> B_RWL<11> VDD_CORE ++ VSS VDD_CORE VSS / RM_IHPSG13_256x16_c2_2P_BITKIT_CELL +XCELL<26> A_RBLC<10> A_RBLC<11> A_RBLT<10> A_RBLT<11> A_XWL<10> A_RWL<10> ++ B_RBLC<10> B_RBLC<11> B_RBLT<10> B_RBLT<11> B_XWL<10> B_RWL<10> VDD_CORE ++ VSS VDD_CORE VSS / RM_IHPSG13_256x16_c2_2P_BITKIT_CELL +XCELL<25> A_RBLC<10> A_RBLC<9> A_RBLT<10> A_RBLT<9> A_XWL<9> A_RWL<9> ++ B_RBLC<10> B_RBLC<9> B_RBLT<10> B_RBLT<9> B_XWL<9> B_RWL<9> VDD_CORE ++ VSS VDD_CORE VSS / RM_IHPSG13_256x16_c2_2P_BITKIT_CELL +XCELL<24> A_RBLC<8> A_RBLC<9> A_RBLT<8> A_RBLT<9> A_XWL<8> A_RWL<8> B_RBLC<8> ++ B_RBLC<9> B_RBLT<8> B_RBLT<9> B_XWL<8> B_RWL<8> VDD_CORE VSS ++ VDD_CORE VSS / RM_IHPSG13_256x16_c2_2P_BITKIT_CELL +XCELL<23> A_RBLC<8> A_RBLC<7> A_RBLT<8> A_RBLT<7> A_XWL<7> A_RWL<7> B_RBLC<8> ++ B_RBLC<7> B_RBLT<8> B_RBLT<7> B_XWL<7> B_RWL<7> VDD_CORE VSS ++ VDD_CORE VSS / RM_IHPSG13_256x16_c2_2P_BITKIT_CELL +XCELL<22> A_RBLC<6> A_RBLC<7> A_RBLT<6> A_RBLT<7> A_XWL<6> A_RWL<6> B_RBLC<6> ++ B_RBLC<7> B_RBLT<6> B_RBLT<7> B_XWL<6> B_RWL<6> VDD_CORE VSS ++ VDD_CORE VSS / RM_IHPSG13_256x16_c2_2P_BITKIT_CELL +XCELL<21> A_RBLC<6> A_RBLC<5> A_RBLT<6> A_RBLT<5> A_XWL<5> A_RWL<5> B_RBLC<6> ++ B_RBLC<5> B_RBLT<6> B_RBLT<5> B_XWL<5> B_RWL<5> VDD_CORE VSS ++ VDD_CORE VSS / RM_IHPSG13_256x16_c2_2P_BITKIT_CELL +XCELL<20> A_RBLC<4> A_RBLC<5> A_RBLT<4> A_RBLT<5> A_XWL<4> A_RWL<4> B_RBLC<4> ++ B_RBLC<5> B_RBLT<4> B_RBLT<5> B_XWL<4> B_RWL<4> VDD_CORE VSS ++ VDD_CORE VSS / RM_IHPSG13_256x16_c2_2P_BITKIT_CELL +XCELL<19> A_RBLC<4> A_RBLC<3> A_RBLT<4> A_RBLT<3> A_XWL<3> A_RWL<3> B_RBLC<4> ++ B_RBLC<3> B_RBLT<4> B_RBLT<3> B_XWL<3> B_RWL<3> VDD_CORE VSS ++ VDD_CORE VSS / RM_IHPSG13_256x16_c2_2P_BITKIT_CELL +XCELL<18> A_RBLC<2> A_RBLC<3> A_RBLT<2> A_RBLT<3> A_XWL<2> A_RWL<2> B_RBLC<2> ++ B_RBLC<3> B_RBLT<2> B_RBLT<3> B_XWL<2> B_RWL<2> VDD_CORE VSS ++ VDD_CORE VSS / RM_IHPSG13_256x16_c2_2P_BITKIT_CELL +XCELL<17> A_RBLC<2> A_RBLC<1> A_RBLT<2> A_RBLT<1> A_XWL<1> A_RWL<1> B_RBLC<2> ++ B_RBLC<1> B_RBLT<2> B_RBLT<1> B_XWL<1> B_RWL<1> VDD_CORE VSS ++ VDD_CORE VSS / RM_IHPSG13_256x16_c2_2P_BITKIT_CELL +XCELL<16> A_BLC_BOT<1> A_RBLC<1> A_BLT_BOT<1> A_RBLT<1> A_XWL<0> A_RWL<0> ++ B_BLC_BOT<1> B_RBLC<1> B_BLT_BOT<1> B_RBLT<1> B_XWL<0> B_RWL<0> VDD_CORE ++ VSS VDD_CORE VSS / RM_IHPSG13_256x16_c2_2P_BITKIT_CELL +XCELL<15> A_BLC_TOP<0> A_LBLC<15> A_BLT_TOP<0> A_LBLT<15> A_LWL<15> A_XWL<15> ++ B_BLC_TOP<0> B_LBLC<15> B_BLT_TOP<0> B_LBLT<15> B_LWL<15> B_XWL<15> ++ VDD_CORE VSS VDD_CORE VSS / ++ RM_IHPSG13_256x16_c2_2P_BITKIT_CELL +XCELL<14> A_LBLC<14> A_LBLC<15> A_LBLT<14> A_LBLT<15> A_LWL<14> A_XWL<14> ++ B_LBLC<14> B_LBLC<15> B_LBLT<14> B_LBLT<15> B_LWL<14> B_XWL<14> VDD_CORE ++ VSS VDD_CORE VSS / RM_IHPSG13_256x16_c2_2P_BITKIT_CELL +XCELL<13> A_LBLC<14> A_LBLC<13> A_LBLT<14> A_LBLT<13> A_LWL<13> A_XWL<13> ++ B_LBLC<14> B_LBLC<13> B_LBLT<14> B_LBLT<13> B_LWL<13> B_XWL<13> VDD_CORE ++ VSS VDD_CORE VSS / RM_IHPSG13_256x16_c2_2P_BITKIT_CELL +XCELL<12> A_LBLC<12> A_LBLC<13> A_LBLT<12> A_LBLT<13> A_LWL<12> A_XWL<12> ++ B_LBLC<12> B_LBLC<13> B_LBLT<12> B_LBLT<13> B_LWL<12> B_XWL<12> VDD_CORE ++ VSS VDD_CORE VSS / RM_IHPSG13_256x16_c2_2P_BITKIT_CELL +XCELL<11> A_LBLC<12> A_LBLC<11> A_LBLT<12> A_LBLT<11> A_LWL<11> A_XWL<11> ++ B_LBLC<12> B_LBLC<11> B_LBLT<12> B_LBLT<11> B_LWL<11> B_XWL<11> VDD_CORE ++ VSS VDD_CORE VSS / RM_IHPSG13_256x16_c2_2P_BITKIT_CELL +XCELL<10> A_LBLC<10> A_LBLC<11> A_LBLT<10> A_LBLT<11> A_LWL<10> A_XWL<10> ++ B_LBLC<10> B_LBLC<11> B_LBLT<10> B_LBLT<11> B_LWL<10> B_XWL<10> VDD_CORE ++ VSS VDD_CORE VSS / RM_IHPSG13_256x16_c2_2P_BITKIT_CELL +XCELL<9> A_LBLC<10> A_LBLC<9> A_LBLT<10> A_LBLT<9> A_LWL<9> A_XWL<9> ++ B_LBLC<10> B_LBLC<9> B_LBLT<10> B_LBLT<9> B_LWL<9> B_XWL<9> VDD_CORE ++ VSS VDD_CORE VSS / RM_IHPSG13_256x16_c2_2P_BITKIT_CELL +XCELL<8> A_LBLC<8> A_LBLC<9> A_LBLT<8> A_LBLT<9> A_LWL<8> A_XWL<8> B_LBLC<8> ++ B_LBLC<9> B_LBLT<8> B_LBLT<9> B_LWL<8> B_XWL<8> VDD_CORE VSS ++ VDD_CORE VSS / RM_IHPSG13_256x16_c2_2P_BITKIT_CELL +XCELL<7> A_LBLC<8> A_LBLC<7> A_LBLT<8> A_LBLT<7> A_LWL<7> A_XWL<7> B_LBLC<8> ++ B_LBLC<7> B_LBLT<8> B_LBLT<7> B_LWL<7> B_XWL<7> VDD_CORE VSS ++ VDD_CORE VSS / RM_IHPSG13_256x16_c2_2P_BITKIT_CELL +XCELL<6> A_LBLC<6> A_LBLC<7> A_LBLT<6> A_LBLT<7> A_LWL<6> A_XWL<6> B_LBLC<6> ++ B_LBLC<7> B_LBLT<6> B_LBLT<7> B_LWL<6> B_XWL<6> VDD_CORE VSS ++ VDD_CORE VSS / RM_IHPSG13_256x16_c2_2P_BITKIT_CELL +XCELL<5> A_LBLC<6> A_LBLC<5> A_LBLT<6> A_LBLT<5> A_LWL<5> A_XWL<5> B_LBLC<6> ++ B_LBLC<5> B_LBLT<6> B_LBLT<5> B_LWL<5> B_XWL<5> VDD_CORE VSS ++ VDD_CORE VSS / RM_IHPSG13_256x16_c2_2P_BITKIT_CELL +XCELL<4> A_LBLC<4> A_LBLC<5> A_LBLT<4> A_LBLT<5> A_LWL<4> A_XWL<4> B_LBLC<4> ++ B_LBLC<5> B_LBLT<4> B_LBLT<5> B_LWL<4> B_XWL<4> VDD_CORE VSS ++ VDD_CORE VSS / RM_IHPSG13_256x16_c2_2P_BITKIT_CELL +XCELL<3> A_LBLC<4> A_LBLC<3> A_LBLT<4> A_LBLT<3> A_LWL<3> A_XWL<3> B_LBLC<4> ++ B_LBLC<3> B_LBLT<4> B_LBLT<3> B_LWL<3> B_XWL<3> VDD_CORE VSS ++ VDD_CORE VSS / RM_IHPSG13_256x16_c2_2P_BITKIT_CELL +XCELL<2> A_LBLC<2> A_LBLC<3> A_LBLT<2> A_LBLT<3> A_LWL<2> A_XWL<2> B_LBLC<2> ++ B_LBLC<3> B_LBLT<2> B_LBLT<3> B_LWL<2> B_XWL<2> VDD_CORE VSS ++ VDD_CORE VSS / RM_IHPSG13_256x16_c2_2P_BITKIT_CELL +XCELL<1> A_LBLC<2> A_LBLC<1> A_LBLT<2> A_LBLT<1> A_LWL<1> A_XWL<1> B_LBLC<2> ++ B_LBLC<1> B_LBLT<2> B_LBLT<1> B_LWL<1> B_XWL<1> VDD_CORE VSS ++ VDD_CORE VSS / RM_IHPSG13_256x16_c2_2P_BITKIT_CELL +XCELL<0> A_BLC_BOT<0> A_LBLC<1> A_BLT_BOT<0> A_LBLT<1> A_LWL<0> A_XWL<0> ++ B_BLC_BOT<0> B_LBLC<1> B_BLT_BOT<0> B_LBLT<1> B_LWL<0> B_XWL<0> VDD_CORE ++ VSS VDD_CORE VSS / RM_IHPSG13_256x16_c2_2P_BITKIT_CELL +.ENDS +.SUBCKT RM_IHPSG13_256x16_c2_2P_BITKIT_EDGE_TB A_BLC A_BLT B_BLC B_BLT NW PW VDD VSS +.ENDS +.SUBCKT RM_IHPSG13_256x16_c2_2P_BITKIT_16x2_EDGE_TB A_BLC<1> A_BLC<0> A_BLT<1> A_BLT<0> ++ B_BLC<1> B_BLC<0> B_BLT<1> B_BLT<0> VDD_CORE VSS +XEDGE<1> A_BLC<1> A_BLT<1> B_BLC<1> B_BLT<1> VDD_CORE VSS ++ VDD_CORE VSS / RM_IHPSG13_256x16_c2_2P_BITKIT_EDGE_TB +XEDGE<0> A_BLC<0> A_BLT<0> B_BLC<0> B_BLT<0> VDD_CORE VSS ++ VDD_CORE VSS / RM_IHPSG13_256x16_c2_2P_BITKIT_EDGE_TB +.ENDS +.SUBCKT RM_IHPSG13_256x16_c2_2P_BITKIT_TAP A_BLC A_BLT B_BLC B_BLT NW PW VDD VSS +.ENDS +.SUBCKT RM_IHPSG13_256x16_c2_2P_BITKIT_16x2_TAP A_BLC<1> A_BLC<0> A_BLT<1> A_BLT<0> ++ B_BLC<1> B_BLC<0> B_BLT<1> B_BLT<0> VDD_CORE VSS +XIEDGEBP_COL1<1> A_BLC<1> A_BLT<1> B_BLC<1> B_BLT<1> VDD_CORE VSS ++ VDD_CORE VSS / RM_IHPSG13_256x16_c2_2P_BITKIT_EDGE_TB +XIEDGEBP_COL1<0> A_BLC<1> A_BLT<1> B_BLC<1> B_BLT<1> VDD_CORE VSS ++ VDD_CORE VSS / RM_IHPSG13_256x16_c2_2P_BITKIT_EDGE_TB +XIEDGEBP_COL2<1> A_BLC<0> A_BLT<0> B_BLC<0> B_BLT<0> VDD_CORE VSS ++ VDD_CORE VSS / RM_IHPSG13_256x16_c2_2P_BITKIT_EDGE_TB +XIEDGEBP_COL2<0> A_BLC<0> A_BLT<0> B_BLC<0> B_BLT<0> VDD_CORE VSS ++ VDD_CORE VSS / RM_IHPSG13_256x16_c2_2P_BITKIT_EDGE_TB +XITAP<1> A_BLC<1> A_BLT<1> B_BLC<1> B_BLT<1> VDD_CORE VSS ++ VDD_CORE VSS / RM_IHPSG13_256x16_c2_2P_BITKIT_TAP +XITAP<0> A_BLC<0> A_BLT<0> B_BLC<0> B_BLT<0> VDD_CORE VSS ++ VDD_CORE VSS / RM_IHPSG13_256x16_c2_2P_BITKIT_TAP +.ENDS + + +.SUBCKT RM_IHPSG13_256x16_c2_1P_BITKIT_TAP_LR NW PW VDD VSS +.ENDS +.SUBCKT RM_IHPSG13_256x16_c2_2P_BITKIT_16x2_TAP_LR VDD_CORE VSS +XCORNER<1> VDD_CORE VSS VDD_CORE VSS / ++ RM_IHPSG13_256x16_c2_1P_BITKIT_CORNER +XCORNER<0> VDD_CORE VSS VDD_CORE VSS / ++ RM_IHPSG13_256x16_c2_1P_BITKIT_CORNER +XTAP_BORDER VDD_CORE VSS VDD_CORE VSS / ++ RM_IHPSG13_256x16_c2_1P_BITKIT_TAP_LR +.ENDS + +.SUBCKT RSC_IHPSG13_CBUFX12 A Z VDD VSS +MN1 Z net6 VSS VSS sg13_lv_nmos m=1 w=4.23u l=130.00n ng=6 nrd=0 nrs=0 +MN0 net6 A VSS VSS sg13_lv_nmos m=1 w=1.41u l=130.00n ng=2 nrd=0 nrs=0 +MP1 Z net6 VDD VDD sg13_lv_pmos m=1 w=9.72u l=130.00n ng=6 nrd=0 nrs=0 +MP0 net6 A VDD VDD sg13_lv_pmos m=1 w=3.24u l=130.00n ng=2 nrd=0 nrs=0 +.ENDS +.SUBCKT RM_IHPSG13_256x16_c2_2P_COLDRV13X12 ADDR_COL_I<1> ADDR_COL_I<0> ADDR_COL_O<1> ++ ADDR_COL_O<0> ADDR_DEC_I<7> ADDR_DEC_I<6> ADDR_DEC_I<5> ADDR_DEC_I<4> ++ ADDR_DEC_I<3> ADDR_DEC_I<2> ADDR_DEC_I<1> ADDR_DEC_I<0> ADDR_DEC_O<7> ++ ADDR_DEC_O<6> ADDR_DEC_O<5> ADDR_DEC_O<4> ADDR_DEC_O<3> ADDR_DEC_O<2> ++ ADDR_DEC_O<1> ADDR_DEC_O<0> DCLK_I DCLK_O RCLK_I RCLK_O WCLK_I WCLK_O ++ VDD VSS +XI1<3> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI1<2> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI1<1> VDD VSS / RSC_IHPSG13_FILLCAP8 +XWCLK_DRV WCLK_I WCLK_O VDD VSS / RSC_IHPSG13_CBUFX12 +XRCLK_DRV RCLK_I RCLK_O VDD VSS / RSC_IHPSG13_CBUFX12 +XDCLK_DRV DCLK_I DCLK_O VDD VSS / RSC_IHPSG13_CBUFX12 +XADDR_COL_DRV<1> ADDR_COL_I<1> ADDR_COL_O<1> VDD VSS / ++ RSC_IHPSG13_CBUFX12 +XADDR_COL_DRV<0> ADDR_COL_I<0> ADDR_COL_O<0> VDD VSS / ++ RSC_IHPSG13_CBUFX12 +XADDR_DEC_DRV<7> ADDR_DEC_I<7> ADDR_DEC_O<7> VDD VSS / ++ RSC_IHPSG13_CBUFX12 +XADDR_DEC_DRV<6> ADDR_DEC_I<6> ADDR_DEC_O<6> VDD VSS / ++ RSC_IHPSG13_CBUFX12 +XADDR_DEC_DRV<5> ADDR_DEC_I<5> ADDR_DEC_O<5> VDD VSS / ++ RSC_IHPSG13_CBUFX12 +XADDR_DEC_DRV<4> ADDR_DEC_I<4> ADDR_DEC_O<4> VDD VSS / ++ RSC_IHPSG13_CBUFX12 +XADDR_DEC_DRV<3> ADDR_DEC_I<3> ADDR_DEC_O<3> VDD VSS / ++ RSC_IHPSG13_CBUFX12 +XADDR_DEC_DRV<2> ADDR_DEC_I<2> ADDR_DEC_O<2> VDD VSS / ++ RSC_IHPSG13_CBUFX12 +XADDR_DEC_DRV<1> ADDR_DEC_I<1> ADDR_DEC_O<1> VDD VSS / ++ RSC_IHPSG13_CBUFX12 +XADDR_DEC_DRV<0> ADDR_DEC_I<0> ADDR_DEC_O<0> VDD VSS / ++ RSC_IHPSG13_CBUFX12 +XI0<6> VDD VSS / RSC_IHPSG13_FILLCAP4 +XI0<5> VDD VSS / RSC_IHPSG13_FILLCAP4 +XI0<4> VDD VSS / RSC_IHPSG13_FILLCAP4 +XI0<3> VDD VSS / RSC_IHPSG13_FILLCAP4 +XI0<2> VDD VSS / RSC_IHPSG13_FILLCAP4 +XI0<1> VDD VSS / RSC_IHPSG13_FILLCAP4 +.ENDS +.SUBCKT RSC_IHPSG13_WLDRVX12 A Z VDD VSS +MN1 Z net6 VSS VSS sg13_lv_nmos m=1 w=1.41u l=130.00n ng=2 nrd=0 nrs=0 +MN0 net6 A VSS VSS sg13_lv_nmos m=1 w=1.8u l=130.00n ng=2 nrd=0 nrs=0 +MP1 Z net6 VDD VDD sg13_lv_pmos m=1 w=9.72u l=130.00n ng=6 nrd=0 nrs=0 +MP0 net6 A VDD VDD sg13_lv_pmos m=1 w=900.0n l=130.00n ng=1 nrd=0 nrs=0 +.ENDS +.SUBCKT RM_IHPSG13_256x16_c2_2P_WLDRV16X12 A<15> A<14> A<13> A<12> A<11> A<10> A<9> A<8> ++ A<7> A<6> A<5> A<4> A<3> A<2> A<1> A<0> Z<15> Z<14> Z<13> Z<12> Z<11> Z<10> ++ Z<9> Z<8> Z<7> Z<6> Z<5> Z<4> Z<3> Z<2> Z<1> Z<0> VDD VSS +XBUF<15> A<15> Z<15> VDD VSS / RSC_IHPSG13_WLDRVX12 +XBUF<14> A<14> Z<14> VDD VSS / RSC_IHPSG13_WLDRVX12 +XBUF<13> A<13> Z<13> VDD VSS / RSC_IHPSG13_WLDRVX12 +XBUF<12> A<12> Z<12> VDD VSS / RSC_IHPSG13_WLDRVX12 +XBUF<11> A<11> Z<11> VDD VSS / RSC_IHPSG13_WLDRVX12 +XBUF<10> A<10> Z<10> VDD VSS / RSC_IHPSG13_WLDRVX12 +XBUF<9> A<9> Z<9> VDD VSS / RSC_IHPSG13_WLDRVX12 +XBUF<8> A<8> Z<8> VDD VSS / RSC_IHPSG13_WLDRVX12 +XBUF<7> A<7> Z<7> VDD VSS / RSC_IHPSG13_WLDRVX12 +XBUF<6> A<6> Z<6> VDD VSS / RSC_IHPSG13_WLDRVX12 +XBUF<5> A<5> Z<5> VDD VSS / RSC_IHPSG13_WLDRVX12 +XBUF<4> A<4> Z<4> VDD VSS / RSC_IHPSG13_WLDRVX12 +XBUF<3> A<3> Z<3> VDD VSS / RSC_IHPSG13_WLDRVX12 +XBUF<2> A<2> Z<2> VDD VSS / RSC_IHPSG13_WLDRVX12 +XBUF<1> A<1> Z<1> VDD VSS / RSC_IHPSG13_WLDRVX12 +XBUF<0> A<0> Z<0> VDD VSS / RSC_IHPSG13_WLDRVX12 +.ENDS +.SUBCKT RM_IHPSG13_256x16_c2_2P_DEC04 ADDR<3> ADDR<2> ADDR<1> ADDR<0> CS ECLK_H_BOT ++ ECLK_H_TOP ECLK_L_BOT ECLK_L_TOP WL<15> WL<14> WL<13> WL<12> WL<11> WL<10> ++ WL<9> WL<8> WL<7> WL<6> WL<5> WL<4> WL<3> WL<2> WL<1> WL<0> VDD VSS +XI0<3> PADR<1> PADR<0> sel01<3> VDD VSS / RSC_IHPSG13_NAND2X2 +XI0<2> PADR<1> NADR<0> sel01<2> VDD VSS / RSC_IHPSG13_NAND2X2 +XI0<1> NADR<1> PADR<0> sel01<1> VDD VSS / RSC_IHPSG13_NAND2X2 +XI0<0> NADR<1> NADR<0> sel01<0> VDD VSS / RSC_IHPSG13_NAND2X2 +XI4 ECLK_L_BOT EN VDD VSS / RSC_IHPSG13_CINVX4 +XI5 ECLK_H_BOT ECLK_L_BOT VDD VSS / RSC_IHPSG13_CINVX2 +XI3<3> PADR<3> NADR<3> VDD VSS / RSC_IHPSG13_INVX2 +XI3<2> PADR<2> NADR<2> VDD VSS / RSC_IHPSG13_INVX2 +XI3<1> PADR<1> NADR<1> VDD VSS / RSC_IHPSG13_INVX2 +XI3<0> PADR<0> NADR<0> VDD VSS / RSC_IHPSG13_INVX2 +XR0 ECLK_H_BOT ECLK_H_TOP / RSC_IHPSG13_MET2RES +XI11 ECLK_L_BOT ECLK_L_TOP / RSC_IHPSG13_MET2RES +XI1<3> PADR<2> PADR<3> CS sel23<3> VDD VSS / RSC_IHPSG13_NAND3X2 +XI1<2> NADR<2> PADR<3> CS sel23<2> VDD VSS / RSC_IHPSG13_NAND3X2 +XI1<1> PADR<2> NADR<3> CS sel23<1> VDD VSS / RSC_IHPSG13_NAND3X2 +XI1<0> NADR<2> NADR<3> CS sel23<0> VDD VSS / RSC_IHPSG13_NAND3X2 +XI2<15> sel23<3> sel01<3> EN WL<15> VDD VSS / RSC_IHPSG13_NOR3X2 +XI2<14> sel23<3> sel01<2> EN WL<14> VDD VSS / RSC_IHPSG13_NOR3X2 +XI2<13> sel23<3> sel01<1> EN WL<13> VDD VSS / RSC_IHPSG13_NOR3X2 +XI2<12> sel23<3> sel01<0> EN WL<12> VDD VSS / RSC_IHPSG13_NOR3X2 +XI2<11> sel23<2> sel01<3> EN WL<11> VDD VSS / RSC_IHPSG13_NOR3X2 +XI2<10> sel23<2> sel01<2> EN WL<10> VDD VSS / RSC_IHPSG13_NOR3X2 +XI2<9> sel23<2> sel01<1> EN WL<9> VDD VSS / RSC_IHPSG13_NOR3X2 +XI2<8> sel23<2> sel01<0> EN WL<8> VDD VSS / RSC_IHPSG13_NOR3X2 +XI2<7> sel23<1> sel01<3> EN WL<7> VDD VSS / RSC_IHPSG13_NOR3X2 +XI2<6> sel23<1> sel01<2> EN WL<6> VDD VSS / RSC_IHPSG13_NOR3X2 +XI2<5> sel23<1> sel01<1> EN WL<5> VDD VSS / RSC_IHPSG13_NOR3X2 +XI2<4> sel23<1> sel01<0> EN WL<4> VDD VSS / RSC_IHPSG13_NOR3X2 +XI2<3> sel23<0> sel01<3> EN WL<3> VDD VSS / RSC_IHPSG13_NOR3X2 +XI2<2> sel23<0> sel01<2> EN WL<2> VDD VSS / RSC_IHPSG13_NOR3X2 +XI2<1> sel23<0> sel01<1> EN WL<1> VDD VSS / RSC_IHPSG13_NOR3X2 +XI2<0> sel23<0> sel01<0> EN WL<0> VDD VSS / RSC_IHPSG13_NOR3X2 +XCAPS4 VDD VSS / RSC_IHPSG13_FILLCAP4 +XLATCH<3> CS ADDR<3> PADR<3> VDD VSS / RSC_IHPSG13_LHPQX2 +XLATCH<2> CS ADDR<2> PADR<2> VDD VSS / RSC_IHPSG13_LHPQX2 +XLATCH<1> CS ADDR<1> PADR<1> VDD VSS / RSC_IHPSG13_LHPQX2 +XLATCH<0> CS ADDR<0> PADR<0> VDD VSS / RSC_IHPSG13_LHPQX2 +.ENDS +.SUBCKT RM_IHPSG13_256x16_c2_2P_DEC02 ADDR<1> ADDR<0> CS CS_OUT VDD VSS +XDEC ADDR<1> NADDR<0> CS net1 VDD VSS / RSC_IHPSG13_NAND3X2 +XADDRINV ADDR<0> NADDR<0> VDD VSS / RSC_IHPSG13_INVX2 +XDECINV net1 CS_OUT VDD VSS / RSC_IHPSG13_INVX4 +XI2<1> VDD VSS / RSC_IHPSG13_FILLCAP4 +XI2<0> VDD VSS / RSC_IHPSG13_FILLCAP4 +.ENDS +.SUBCKT RM_IHPSG13_256x16_c2_2P_DEC01 ADDR<1> ADDR<0> CS CS_OUT VDD VSS +XDEC NADDR<1> ADDR<0> CS net1 VDD VSS / RSC_IHPSG13_NAND3X2 +XADDRINV ADDR<1> NADDR<1> VDD VSS / RSC_IHPSG13_INVX2 +XDECINV net1 CS_OUT VDD VSS / RSC_IHPSG13_INVX4 +XI2<1> VDD VSS / RSC_IHPSG13_FILLCAP4 +XI2<0> VDD VSS / RSC_IHPSG13_FILLCAP4 +.ENDS +.SUBCKT RM_IHPSG13_256x16_c2_2P_DEC00 ADDR<1> ADDR<0> CS CS_OUT VDD VSS +XDEC NADDR<1> NADDR<0> CS net1 VDD VSS / RSC_IHPSG13_NAND3X2 +XADDRINV<1> ADDR<1> NADDR<1> VDD VSS / RSC_IHPSG13_INVX2 +XADDRINV<0> ADDR<0> NADDR<0> VDD VSS / RSC_IHPSG13_INVX2 +XI1<1> VDD VSS / RSC_IHPSG13_FILLCAP4 +XI1<0> VDD VSS / RSC_IHPSG13_FILLCAP4 +XDECINV net1 CS_OUT VDD VSS / RSC_IHPSG13_INVX4 +.ENDS +.SUBCKT RM_IHPSG13_256x16_c2_2P_DEC03 ADDR<1> ADDR<0> CS CS_OUT VDD VSS +XDEC ADDR<1> ADDR<0> CS net1 VDD VSS / RSC_IHPSG13_NAND3X2 +XDECINV net1 CS_OUT VDD VSS / RSC_IHPSG13_INVX4 +XI0<1> VDD VSS / RSC_IHPSG13_FILLCAP4 +XI0<0> VDD VSS / RSC_IHPSG13_FILLCAP4 +.ENDS +.SUBCKT RM_IHPSG13_256x16_c2_2P_ROWDEC9 ADDR_N_I<8> ADDR_N_I<7> ADDR_N_I<6> ADDR_N_I<5> ++ ADDR_N_I<4> ADDR_N_I<3> ADDR_N_I<2> ADDR_N_I<1> ADDR_N_I<0> CS_I ECLK_I ++ WL_O<511> WL_O<510> WL_O<509> WL_O<508> WL_O<507> WL_O<506> WL_O<505> ++ WL_O<504> WL_O<503> WL_O<502> WL_O<501> WL_O<500> WL_O<499> WL_O<498> ++ WL_O<497> WL_O<496> WL_O<495> WL_O<494> WL_O<493> WL_O<492> WL_O<491> ++ WL_O<490> WL_O<489> WL_O<488> WL_O<487> WL_O<486> WL_O<485> WL_O<484> ++ WL_O<483> WL_O<482> WL_O<481> WL_O<480> WL_O<479> WL_O<478> WL_O<477> ++ WL_O<476> WL_O<475> WL_O<474> WL_O<473> WL_O<472> WL_O<471> WL_O<470> ++ WL_O<469> WL_O<468> WL_O<467> WL_O<466> WL_O<465> WL_O<464> WL_O<463> ++ WL_O<462> WL_O<461> WL_O<460> WL_O<459> WL_O<458> WL_O<457> WL_O<456> ++ WL_O<455> WL_O<454> WL_O<453> WL_O<452> WL_O<451> WL_O<450> WL_O<449> ++ WL_O<448> WL_O<447> WL_O<446> WL_O<445> WL_O<444> WL_O<443> WL_O<442> ++ WL_O<441> WL_O<440> WL_O<439> WL_O<438> WL_O<437> WL_O<436> WL_O<435> ++ WL_O<434> WL_O<433> WL_O<432> WL_O<431> WL_O<430> WL_O<429> WL_O<428> ++ WL_O<427> WL_O<426> WL_O<425> WL_O<424> WL_O<423> WL_O<422> WL_O<421> ++ WL_O<420> WL_O<419> WL_O<418> WL_O<417> WL_O<416> WL_O<415> WL_O<414> ++ WL_O<413> WL_O<412> WL_O<411> WL_O<410> WL_O<409> WL_O<408> WL_O<407> ++ WL_O<406> WL_O<405> WL_O<404> WL_O<403> WL_O<402> WL_O<401> WL_O<400> ++ WL_O<399> WL_O<398> WL_O<397> WL_O<396> WL_O<395> WL_O<394> WL_O<393> ++ WL_O<392> WL_O<391> WL_O<390> WL_O<389> WL_O<388> WL_O<387> WL_O<386> ++ WL_O<385> WL_O<384> WL_O<383> WL_O<382> WL_O<381> WL_O<380> WL_O<379> ++ WL_O<378> WL_O<377> WL_O<376> WL_O<375> WL_O<374> WL_O<373> WL_O<372> ++ WL_O<371> WL_O<370> WL_O<369> WL_O<368> WL_O<367> WL_O<366> WL_O<365> ++ WL_O<364> WL_O<363> WL_O<362> WL_O<361> WL_O<360> WL_O<359> WL_O<358> ++ WL_O<357> WL_O<356> WL_O<355> WL_O<354> WL_O<353> WL_O<352> WL_O<351> ++ WL_O<350> WL_O<349> WL_O<348> WL_O<347> WL_O<346> WL_O<345> WL_O<344> ++ WL_O<343> WL_O<342> WL_O<341> WL_O<340> WL_O<339> WL_O<338> WL_O<337> ++ WL_O<336> WL_O<335> WL_O<334> WL_O<333> WL_O<332> WL_O<331> WL_O<330> ++ WL_O<329> WL_O<328> WL_O<327> WL_O<326> WL_O<325> WL_O<324> WL_O<323> ++ WL_O<322> WL_O<321> WL_O<320> WL_O<319> WL_O<318> WL_O<317> WL_O<316> ++ WL_O<315> WL_O<314> WL_O<313> WL_O<312> WL_O<311> WL_O<310> WL_O<309> ++ WL_O<308> WL_O<307> WL_O<306> WL_O<305> WL_O<304> WL_O<303> WL_O<302> ++ WL_O<301> WL_O<300> WL_O<299> WL_O<298> WL_O<297> WL_O<296> WL_O<295> ++ WL_O<294> WL_O<293> WL_O<292> WL_O<291> WL_O<290> WL_O<289> WL_O<288> ++ WL_O<287> WL_O<286> WL_O<285> WL_O<284> WL_O<283> WL_O<282> WL_O<281> ++ WL_O<280> WL_O<279> WL_O<278> WL_O<277> WL_O<276> WL_O<275> WL_O<274> ++ WL_O<273> WL_O<272> WL_O<271> WL_O<270> WL_O<269> WL_O<268> WL_O<267> ++ WL_O<266> WL_O<265> WL_O<264> WL_O<263> WL_O<262> WL_O<261> WL_O<260> ++ WL_O<259> WL_O<258> WL_O<257> WL_O<256> WL_O<255> WL_O<254> WL_O<253> ++ WL_O<252> WL_O<251> WL_O<250> WL_O<249> WL_O<248> WL_O<247> WL_O<246> ++ WL_O<245> WL_O<244> WL_O<243> WL_O<242> WL_O<241> WL_O<240> WL_O<239> ++ WL_O<238> WL_O<237> WL_O<236> WL_O<235> WL_O<234> WL_O<233> WL_O<232> ++ WL_O<231> WL_O<230> WL_O<229> WL_O<228> WL_O<227> WL_O<226> WL_O<225> ++ WL_O<224> WL_O<223> WL_O<222> WL_O<221> WL_O<220> WL_O<219> WL_O<218> ++ WL_O<217> WL_O<216> WL_O<215> WL_O<214> WL_O<213> WL_O<212> WL_O<211> ++ WL_O<210> WL_O<209> WL_O<208> WL_O<207> WL_O<206> WL_O<205> WL_O<204> ++ WL_O<203> WL_O<202> WL_O<201> WL_O<200> WL_O<199> WL_O<198> WL_O<197> ++ WL_O<196> WL_O<195> WL_O<194> WL_O<193> WL_O<192> WL_O<191> WL_O<190> ++ WL_O<189> WL_O<188> WL_O<187> WL_O<186> WL_O<185> WL_O<184> WL_O<183> ++ WL_O<182> WL_O<181> WL_O<180> WL_O<179> WL_O<178> WL_O<177> WL_O<176> ++ WL_O<175> WL_O<174> WL_O<173> WL_O<172> WL_O<171> WL_O<170> WL_O<169> ++ WL_O<168> WL_O<167> WL_O<166> WL_O<165> WL_O<164> WL_O<163> WL_O<162> ++ WL_O<161> WL_O<160> WL_O<159> WL_O<158> WL_O<157> WL_O<156> WL_O<155> ++ WL_O<154> WL_O<153> WL_O<152> WL_O<151> WL_O<150> WL_O<149> WL_O<148> ++ WL_O<147> WL_O<146> WL_O<145> WL_O<144> WL_O<143> WL_O<142> WL_O<141> ++ WL_O<140> WL_O<139> WL_O<138> WL_O<137> WL_O<136> WL_O<135> WL_O<134> ++ WL_O<133> WL_O<132> WL_O<131> WL_O<130> WL_O<129> WL_O<128> WL_O<127> ++ WL_O<126> WL_O<125> WL_O<124> WL_O<123> WL_O<122> WL_O<121> WL_O<120> ++ WL_O<119> WL_O<118> WL_O<117> WL_O<116> WL_O<115> WL_O<114> WL_O<113> ++ WL_O<112> WL_O<111> WL_O<110> WL_O<109> WL_O<108> WL_O<107> WL_O<106> ++ WL_O<105> WL_O<104> WL_O<103> WL_O<102> WL_O<101> WL_O<100> WL_O<99> ++ WL_O<98> WL_O<97> WL_O<96> WL_O<95> WL_O<94> WL_O<93> WL_O<92> WL_O<91> ++ WL_O<90> WL_O<89> WL_O<88> WL_O<87> WL_O<86> WL_O<85> WL_O<84> WL_O<83> ++ WL_O<82> WL_O<81> WL_O<80> WL_O<79> WL_O<78> WL_O<77> WL_O<76> WL_O<75> ++ WL_O<74> WL_O<73> WL_O<72> WL_O<71> WL_O<70> WL_O<69> WL_O<68> WL_O<67> ++ WL_O<66> WL_O<65> WL_O<64> WL_O<63> WL_O<62> WL_O<61> WL_O<60> WL_O<59> ++ WL_O<58> WL_O<57> WL_O<56> WL_O<55> WL_O<54> WL_O<53> WL_O<52> WL_O<51> ++ WL_O<50> WL_O<49> WL_O<48> WL_O<47> WL_O<46> WL_O<45> WL_O<44> WL_O<43> ++ WL_O<42> WL_O<41> WL_O<40> WL_O<39> WL_O<38> WL_O<37> WL_O<36> WL_O<35> ++ WL_O<34> WL_O<33> WL_O<32> WL_O<31> WL_O<30> WL_O<29> WL_O<28> WL_O<27> ++ WL_O<26> WL_O<25> WL_O<24> WL_O<23> WL_O<22> WL_O<21> WL_O<20> WL_O<19> ++ WL_O<18> WL_O<17> WL_O<16> WL_O<15> WL_O<14> WL_O<13> WL_O<12> WL_O<11> ++ WL_O<10> WL_O<9> WL_O<8> WL_O<7> WL_O<6> WL_O<5> WL_O<4> WL_O<3> WL_O<2> ++ WL_O<1> WL_O<0> VDD VSS +XSEL<31> ADDR_N_I<3> ADDR_N_I<2> ADDR_N_I<1> ADDR_N_I<0> CS00<31> ECLK_H<31> ++ ECLK_H<32> ECLK_B<31> ECLK_B<32> WL_O<511> WL_O<510> WL_O<509> WL_O<508> ++ WL_O<507> WL_O<506> WL_O<505> WL_O<504> WL_O<503> WL_O<502> WL_O<501> ++ WL_O<500> WL_O<499> WL_O<498> WL_O<497> WL_O<496> VDD VSS / ++ RM_IHPSG13_256x16_c2_2P_DEC04 +XSEL<30> ADDR_N_I<3> ADDR_N_I<2> ADDR_N_I<1> ADDR_N_I<0> CS00<30> ECLK_H<30> ++ ECLK_H<31> ECLK_B<30> ECLK_B<31> WL_O<495> WL_O<494> WL_O<493> WL_O<492> ++ WL_O<491> WL_O<490> WL_O<489> WL_O<488> WL_O<487> WL_O<486> WL_O<485> ++ WL_O<484> WL_O<483> WL_O<482> WL_O<481> WL_O<480> VDD VSS / ++ RM_IHPSG13_256x16_c2_2P_DEC04 +XSEL<29> ADDR_N_I<3> ADDR_N_I<2> ADDR_N_I<1> ADDR_N_I<0> CS00<29> ECLK_H<29> ++ ECLK_H<30> ECLK_B<29> ECLK_B<30> WL_O<479> WL_O<478> WL_O<477> WL_O<476> ++ WL_O<475> WL_O<474> WL_O<473> WL_O<472> WL_O<471> WL_O<470> WL_O<469> ++ WL_O<468> WL_O<467> WL_O<466> WL_O<465> WL_O<464> VDD VSS / ++ RM_IHPSG13_256x16_c2_2P_DEC04 +XSEL<28> ADDR_N_I<3> ADDR_N_I<2> ADDR_N_I<1> ADDR_N_I<0> CS00<28> ECLK_H<28> ++ ECLK_H<29> ECLK_B<28> ECLK_B<29> WL_O<463> WL_O<462> WL_O<461> WL_O<460> ++ WL_O<459> WL_O<458> WL_O<457> WL_O<456> WL_O<455> WL_O<454> WL_O<453> ++ WL_O<452> WL_O<451> WL_O<450> WL_O<449> WL_O<448> VDD VSS / ++ RM_IHPSG13_256x16_c2_2P_DEC04 +XSEL<27> ADDR_N_I<3> ADDR_N_I<2> ADDR_N_I<1> ADDR_N_I<0> CS00<27> ECLK_H<27> ++ ECLK_H<28> ECLK_B<27> ECLK_B<28> WL_O<447> WL_O<446> WL_O<445> WL_O<444> ++ WL_O<443> WL_O<442> WL_O<441> WL_O<440> WL_O<439> WL_O<438> WL_O<437> ++ WL_O<436> WL_O<435> WL_O<434> WL_O<433> WL_O<432> VDD VSS / ++ RM_IHPSG13_256x16_c2_2P_DEC04 +XSEL<26> ADDR_N_I<3> ADDR_N_I<2> ADDR_N_I<1> ADDR_N_I<0> CS00<26> ECLK_H<26> ++ ECLK_H<27> ECLK_B<26> ECLK_B<27> WL_O<431> WL_O<430> WL_O<429> WL_O<428> ++ WL_O<427> WL_O<426> WL_O<425> WL_O<424> WL_O<423> WL_O<422> WL_O<421> ++ WL_O<420> WL_O<419> WL_O<418> WL_O<417> WL_O<416> VDD VSS / ++ RM_IHPSG13_256x16_c2_2P_DEC04 +XSEL<25> ADDR_N_I<3> ADDR_N_I<2> ADDR_N_I<1> ADDR_N_I<0> CS00<25> ECLK_H<25> ++ ECLK_H<26> ECLK_B<25> ECLK_B<26> WL_O<415> WL_O<414> WL_O<413> WL_O<412> ++ WL_O<411> WL_O<410> WL_O<409> WL_O<408> WL_O<407> WL_O<406> WL_O<405> ++ WL_O<404> WL_O<403> WL_O<402> WL_O<401> WL_O<400> VDD VSS / ++ RM_IHPSG13_256x16_c2_2P_DEC04 +XSEL<24> ADDR_N_I<3> ADDR_N_I<2> ADDR_N_I<1> ADDR_N_I<0> CS00<24> ECLK_H<24> ++ ECLK_H<25> ECLK_B<24> ECLK_B<25> WL_O<399> WL_O<398> WL_O<397> WL_O<396> ++ WL_O<395> WL_O<394> WL_O<393> WL_O<392> WL_O<391> WL_O<390> WL_O<389> ++ WL_O<388> WL_O<387> WL_O<386> WL_O<385> WL_O<384> VDD VSS / ++ RM_IHPSG13_256x16_c2_2P_DEC04 +XSEL<23> ADDR_N_I<3> ADDR_N_I<2> ADDR_N_I<1> ADDR_N_I<0> CS00<23> ECLK_H<23> ++ ECLK_H<24> ECLK_B<23> ECLK_B<24> WL_O<383> WL_O<382> WL_O<381> WL_O<380> ++ WL_O<379> WL_O<378> WL_O<377> WL_O<376> WL_O<375> WL_O<374> WL_O<373> ++ WL_O<372> WL_O<371> WL_O<370> WL_O<369> WL_O<368> VDD VSS / ++ RM_IHPSG13_256x16_c2_2P_DEC04 +XSEL<22> ADDR_N_I<3> ADDR_N_I<2> ADDR_N_I<1> ADDR_N_I<0> CS00<22> ECLK_H<22> ++ ECLK_H<23> ECLK_B<22> ECLK_B<23> WL_O<367> WL_O<366> WL_O<365> WL_O<364> ++ WL_O<363> WL_O<362> WL_O<361> WL_O<360> WL_O<359> WL_O<358> WL_O<357> ++ WL_O<356> WL_O<355> WL_O<354> WL_O<353> WL_O<352> VDD VSS / ++ RM_IHPSG13_256x16_c2_2P_DEC04 +XSEL<21> ADDR_N_I<3> ADDR_N_I<2> ADDR_N_I<1> ADDR_N_I<0> CS00<21> ECLK_H<21> ++ ECLK_H<22> ECLK_B<21> ECLK_B<22> WL_O<351> WL_O<350> WL_O<349> WL_O<348> ++ WL_O<347> WL_O<346> WL_O<345> WL_O<344> WL_O<343> WL_O<342> WL_O<341> ++ WL_O<340> WL_O<339> WL_O<338> WL_O<337> WL_O<336> VDD VSS / ++ RM_IHPSG13_256x16_c2_2P_DEC04 +XSEL<20> ADDR_N_I<3> ADDR_N_I<2> ADDR_N_I<1> ADDR_N_I<0> CS00<20> ECLK_H<20> ++ ECLK_H<21> ECLK_B<20> ECLK_B<21> WL_O<335> WL_O<334> WL_O<333> WL_O<332> ++ WL_O<331> WL_O<330> WL_O<329> WL_O<328> WL_O<327> WL_O<326> WL_O<325> ++ WL_O<324> WL_O<323> WL_O<322> WL_O<321> WL_O<320> VDD VSS / ++ RM_IHPSG13_256x16_c2_2P_DEC04 +XSEL<19> ADDR_N_I<3> ADDR_N_I<2> ADDR_N_I<1> ADDR_N_I<0> CS00<19> ECLK_H<19> ++ ECLK_H<20> ECLK_B<19> ECLK_B<20> WL_O<319> WL_O<318> WL_O<317> WL_O<316> ++ WL_O<315> WL_O<314> WL_O<313> WL_O<312> WL_O<311> WL_O<310> WL_O<309> ++ WL_O<308> WL_O<307> WL_O<306> WL_O<305> WL_O<304> VDD VSS / ++ RM_IHPSG13_256x16_c2_2P_DEC04 +XSEL<18> ADDR_N_I<3> ADDR_N_I<2> ADDR_N_I<1> ADDR_N_I<0> CS00<18> ECLK_H<18> ++ ECLK_H<19> ECLK_B<18> ECLK_B<19> WL_O<303> WL_O<302> WL_O<301> WL_O<300> ++ WL_O<299> WL_O<298> WL_O<297> WL_O<296> WL_O<295> WL_O<294> WL_O<293> ++ WL_O<292> WL_O<291> WL_O<290> WL_O<289> WL_O<288> VDD VSS / ++ RM_IHPSG13_256x16_c2_2P_DEC04 +XSEL<17> ADDR_N_I<3> ADDR_N_I<2> ADDR_N_I<1> ADDR_N_I<0> CS00<17> ECLK_H<17> ++ ECLK_H<18> ECLK_B<17> ECLK_B<18> WL_O<287> WL_O<286> WL_O<285> WL_O<284> ++ WL_O<283> WL_O<282> WL_O<281> WL_O<280> WL_O<279> WL_O<278> WL_O<277> ++ WL_O<276> WL_O<275> WL_O<274> WL_O<273> WL_O<272> VDD VSS / ++ RM_IHPSG13_256x16_c2_2P_DEC04 +XSEL<16> ADDR_N_I<3> ADDR_N_I<2> ADDR_N_I<1> ADDR_N_I<0> CS00<16> ECLK_H<16> ++ ECLK_H<17> ECLK_B<16> ECLK_B<17> WL_O<271> WL_O<270> WL_O<269> WL_O<268> ++ WL_O<267> WL_O<266> WL_O<265> WL_O<264> WL_O<263> WL_O<262> WL_O<261> ++ WL_O<260> WL_O<259> WL_O<258> WL_O<257> WL_O<256> VDD VSS / ++ RM_IHPSG13_256x16_c2_2P_DEC04 +XSEL<15> ADDR_N_I<3> ADDR_N_I<2> ADDR_N_I<1> ADDR_N_I<0> CS00<15> ECLK_H<15> ++ ECLK_H<16> ECLK_B<15> ECLK_B<16> WL_O<255> WL_O<254> WL_O<253> WL_O<252> ++ WL_O<251> WL_O<250> WL_O<249> WL_O<248> WL_O<247> WL_O<246> WL_O<245> ++ WL_O<244> WL_O<243> WL_O<242> WL_O<241> WL_O<240> VDD VSS / ++ RM_IHPSG13_256x16_c2_2P_DEC04 +XSEL<14> ADDR_N_I<3> ADDR_N_I<2> ADDR_N_I<1> ADDR_N_I<0> CS00<14> ECLK_H<14> ++ ECLK_H<15> ECLK_B<14> ECLK_B<15> WL_O<239> WL_O<238> WL_O<237> WL_O<236> ++ WL_O<235> WL_O<234> WL_O<233> WL_O<232> WL_O<231> WL_O<230> WL_O<229> ++ WL_O<228> WL_O<227> WL_O<226> WL_O<225> WL_O<224> VDD VSS / ++ RM_IHPSG13_256x16_c2_2P_DEC04 +XSEL<13> ADDR_N_I<3> ADDR_N_I<2> ADDR_N_I<1> ADDR_N_I<0> CS00<13> ECLK_H<13> ++ ECLK_H<14> ECLK_B<13> ECLK_B<14> WL_O<223> WL_O<222> WL_O<221> WL_O<220> ++ WL_O<219> WL_O<218> WL_O<217> WL_O<216> WL_O<215> WL_O<214> WL_O<213> ++ WL_O<212> WL_O<211> WL_O<210> WL_O<209> WL_O<208> VDD VSS / ++ RM_IHPSG13_256x16_c2_2P_DEC04 +XSEL<12> ADDR_N_I<3> ADDR_N_I<2> ADDR_N_I<1> ADDR_N_I<0> CS00<12> ECLK_H<12> ++ ECLK_H<13> ECLK_B<12> ECLK_B<13> WL_O<207> WL_O<206> WL_O<205> WL_O<204> ++ WL_O<203> WL_O<202> WL_O<201> WL_O<200> WL_O<199> WL_O<198> WL_O<197> ++ WL_O<196> WL_O<195> WL_O<194> WL_O<193> WL_O<192> VDD VSS / ++ RM_IHPSG13_256x16_c2_2P_DEC04 +XSEL<11> ADDR_N_I<3> ADDR_N_I<2> ADDR_N_I<1> ADDR_N_I<0> CS00<11> ECLK_H<11> ++ ECLK_H<12> ECLK_B<11> ECLK_B<12> WL_O<191> WL_O<190> WL_O<189> WL_O<188> ++ WL_O<187> WL_O<186> WL_O<185> WL_O<184> WL_O<183> WL_O<182> WL_O<181> ++ WL_O<180> WL_O<179> WL_O<178> WL_O<177> WL_O<176> VDD VSS / ++ RM_IHPSG13_256x16_c2_2P_DEC04 +XSEL<10> ADDR_N_I<3> ADDR_N_I<2> ADDR_N_I<1> ADDR_N_I<0> CS00<10> ECLK_H<10> ++ ECLK_H<11> ECLK_B<10> ECLK_B<11> WL_O<175> WL_O<174> WL_O<173> WL_O<172> ++ WL_O<171> WL_O<170> WL_O<169> WL_O<168> WL_O<167> WL_O<166> WL_O<165> ++ WL_O<164> WL_O<163> WL_O<162> WL_O<161> WL_O<160> VDD VSS / ++ RM_IHPSG13_256x16_c2_2P_DEC04 +XSEL<9> ADDR_N_I<3> ADDR_N_I<2> ADDR_N_I<1> ADDR_N_I<0> CS00<9> ECLK_H<9> ++ ECLK_H<10> ECLK_B<9> ECLK_B<10> WL_O<159> WL_O<158> WL_O<157> WL_O<156> ++ WL_O<155> WL_O<154> WL_O<153> WL_O<152> WL_O<151> WL_O<150> WL_O<149> ++ WL_O<148> WL_O<147> WL_O<146> WL_O<145> WL_O<144> VDD VSS / ++ RM_IHPSG13_256x16_c2_2P_DEC04 +XSEL<8> ADDR_N_I<3> ADDR_N_I<2> ADDR_N_I<1> ADDR_N_I<0> CS00<8> ECLK_H<8> ++ ECLK_H<9> ECLK_B<8> ECLK_B<9> WL_O<143> WL_O<142> WL_O<141> WL_O<140> ++ WL_O<139> WL_O<138> WL_O<137> WL_O<136> WL_O<135> WL_O<134> WL_O<133> ++ WL_O<132> WL_O<131> WL_O<130> WL_O<129> WL_O<128> VDD VSS / ++ RM_IHPSG13_256x16_c2_2P_DEC04 +XSEL<7> ADDR_N_I<3> ADDR_N_I<2> ADDR_N_I<1> ADDR_N_I<0> CS00<7> ECLK_H<7> ++ ECLK_H<8> ECLK_B<7> ECLK_B<8> WL_O<127> WL_O<126> WL_O<125> WL_O<124> ++ WL_O<123> WL_O<122> WL_O<121> WL_O<120> WL_O<119> WL_O<118> WL_O<117> ++ WL_O<116> WL_O<115> WL_O<114> WL_O<113> WL_O<112> VDD VSS / ++ RM_IHPSG13_256x16_c2_2P_DEC04 +XSEL<6> ADDR_N_I<3> ADDR_N_I<2> ADDR_N_I<1> ADDR_N_I<0> CS00<6> ECLK_H<6> ++ ECLK_H<7> ECLK_B<6> ECLK_B<7> WL_O<111> WL_O<110> WL_O<109> WL_O<108> ++ WL_O<107> WL_O<106> WL_O<105> WL_O<104> WL_O<103> WL_O<102> WL_O<101> ++ WL_O<100> WL_O<99> WL_O<98> WL_O<97> WL_O<96> VDD VSS / ++ RM_IHPSG13_256x16_c2_2P_DEC04 +XSEL<5> ADDR_N_I<3> ADDR_N_I<2> ADDR_N_I<1> ADDR_N_I<0> CS00<5> ECLK_H<5> ++ ECLK_H<6> ECLK_B<5> ECLK_B<6> WL_O<95> WL_O<94> WL_O<93> WL_O<92> WL_O<91> ++ WL_O<90> WL_O<89> WL_O<88> WL_O<87> WL_O<86> WL_O<85> WL_O<84> WL_O<83> ++ WL_O<82> WL_O<81> WL_O<80> VDD VSS / RM_IHPSG13_256x16_c2_2P_DEC04 +XSEL<4> ADDR_N_I<3> ADDR_N_I<2> ADDR_N_I<1> ADDR_N_I<0> CS00<4> ECLK_H<4> ++ ECLK_H<5> ECLK_B<4> ECLK_B<5> WL_O<79> WL_O<78> WL_O<77> WL_O<76> WL_O<75> ++ WL_O<74> WL_O<73> WL_O<72> WL_O<71> WL_O<70> WL_O<69> WL_O<68> WL_O<67> ++ WL_O<66> WL_O<65> WL_O<64> VDD VSS / RM_IHPSG13_256x16_c2_2P_DEC04 +XSEL<3> ADDR_N_I<3> ADDR_N_I<2> ADDR_N_I<1> ADDR_N_I<0> CS00<3> ECLK_H<3> ++ ECLK_H<4> ECLK_B<3> ECLK_B<4> WL_O<63> WL_O<62> WL_O<61> WL_O<60> WL_O<59> ++ WL_O<58> WL_O<57> WL_O<56> WL_O<55> WL_O<54> WL_O<53> WL_O<52> WL_O<51> ++ WL_O<50> WL_O<49> WL_O<48> VDD VSS / RM_IHPSG13_256x16_c2_2P_DEC04 +XSEL<2> ADDR_N_I<3> ADDR_N_I<2> ADDR_N_I<1> ADDR_N_I<0> CS00<2> ECLK_H<2> ++ ECLK_H<3> ECLK_B<2> ECLK_B<3> WL_O<47> WL_O<46> WL_O<45> WL_O<44> WL_O<43> ++ WL_O<42> WL_O<41> WL_O<40> WL_O<39> WL_O<38> WL_O<37> WL_O<36> WL_O<35> ++ WL_O<34> WL_O<33> WL_O<32> VDD VSS / RM_IHPSG13_256x16_c2_2P_DEC04 +XSEL<1> ADDR_N_I<3> ADDR_N_I<2> ADDR_N_I<1> ADDR_N_I<0> CS00<1> ECLK_H<1> ++ ECLK_H<2> ECLK_B<1> ECLK_B<2> WL_O<31> WL_O<30> WL_O<29> WL_O<28> WL_O<27> ++ WL_O<26> WL_O<25> WL_O<24> WL_O<23> WL_O<22> WL_O<21> WL_O<20> WL_O<19> ++ WL_O<18> WL_O<17> WL_O<16> VDD VSS / RM_IHPSG13_256x16_c2_2P_DEC04 +XSEL<0> ADDR_N_I<3> ADDR_N_I<2> ADDR_N_I<1> ADDR_N_I<0> CS00<0> ECLK_I ++ ECLK_H<1> ECLK_B<0> ECLK_B<1> WL_O<15> WL_O<14> WL_O<13> WL_O<12> WL_O<11> ++ WL_O<10> WL_O<9> WL_O<8> WL_O<7> WL_O<6> WL_O<5> WL_O<4> WL_O<3> WL_O<2> ++ WL_O<1> WL_O<0> VDD VSS / RM_IHPSG13_256x16_c2_2P_DEC04 +XDEC10<9> ADDR_N_I<7> ADDR_N_I<6> CS04<1> CS02<6> VDD VSS / ++ RM_IHPSG13_256x16_c2_2P_DEC02 +XDEC10<8> ADDR_N_I<7> ADDR_N_I<6> CS04<0> CS02<2> VDD VSS / ++ RM_IHPSG13_256x16_c2_2P_DEC02 +XDEC10<7> ADDR_N_I<5> ADDR_N_I<4> CS02<7> CS00<30> VDD VSS / ++ RM_IHPSG13_256x16_c2_2P_DEC02 +XDEC10<6> ADDR_N_I<5> ADDR_N_I<4> CS02<6> CS00<26> VDD VSS / ++ RM_IHPSG13_256x16_c2_2P_DEC02 +XDEC10<5> ADDR_N_I<5> ADDR_N_I<4> CS02<5> CS00<22> VDD VSS / ++ RM_IHPSG13_256x16_c2_2P_DEC02 +XDEC10<4> ADDR_N_I<5> ADDR_N_I<4> CS02<4> CS00<18> VDD VSS / ++ RM_IHPSG13_256x16_c2_2P_DEC02 +XDEC10<3> ADDR_N_I<5> ADDR_N_I<4> CS02<3> CS00<14> VDD VSS / ++ RM_IHPSG13_256x16_c2_2P_DEC02 +XDEC10<2> ADDR_N_I<5> ADDR_N_I<4> CS02<2> CS00<10> VDD VSS / ++ RM_IHPSG13_256x16_c2_2P_DEC02 +XDEC10<1> ADDR_N_I<5> ADDR_N_I<4> CS02<1> CS00<6> VDD VSS / ++ RM_IHPSG13_256x16_c2_2P_DEC02 +XDEC10<0> ADDR_N_I<5> ADDR_N_I<4> CS02<0> CS00<2> VDD VSS / ++ RM_IHPSG13_256x16_c2_2P_DEC02 +XDEC01<10> ADDR_N_I<9> ADDR_N_I<8> CS_I CS04<1> VDD VSS / ++ RM_IHPSG13_256x16_c2_2P_DEC01 +XDEC01<9> ADDR_N_I<7> ADDR_N_I<6> CS04<1> CS02<5> VDD VSS / ++ RM_IHPSG13_256x16_c2_2P_DEC01 +XDEC01<8> ADDR_N_I<7> ADDR_N_I<6> CS04<0> CS02<1> VDD VSS / ++ RM_IHPSG13_256x16_c2_2P_DEC01 +XDEC01<7> ADDR_N_I<5> ADDR_N_I<4> CS02<7> CS00<29> VDD VSS / ++ RM_IHPSG13_256x16_c2_2P_DEC01 +XDEC01<6> ADDR_N_I<5> ADDR_N_I<4> CS02<6> CS00<25> VDD VSS / ++ RM_IHPSG13_256x16_c2_2P_DEC01 +XDEC01<5> ADDR_N_I<5> ADDR_N_I<4> CS02<5> CS00<21> VDD VSS / ++ RM_IHPSG13_256x16_c2_2P_DEC01 +XDEC01<4> ADDR_N_I<5> ADDR_N_I<4> CS02<4> CS00<17> VDD VSS / ++ RM_IHPSG13_256x16_c2_2P_DEC01 +XDEC01<3> ADDR_N_I<5> ADDR_N_I<4> CS02<3> CS00<13> VDD VSS / ++ RM_IHPSG13_256x16_c2_2P_DEC01 +XDEC01<2> ADDR_N_I<5> ADDR_N_I<4> CS02<2> CS00<9> VDD VSS / ++ RM_IHPSG13_256x16_c2_2P_DEC01 +XDEC01<1> ADDR_N_I<5> ADDR_N_I<4> CS02<1> CS00<5> VDD VSS / ++ RM_IHPSG13_256x16_c2_2P_DEC01 +XDEC01<0> ADDR_N_I<5> ADDR_N_I<4> CS02<0> CS00<1> VDD VSS / ++ RM_IHPSG13_256x16_c2_2P_DEC01 +XL2<258> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<257> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<256> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<255> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<254> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<253> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<252> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<251> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<250> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<249> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<248> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<247> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<246> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<245> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<244> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<243> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<242> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<241> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<240> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<239> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<238> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<237> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<236> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<235> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<234> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<233> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<232> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<231> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<230> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<229> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<228> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<227> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<226> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<225> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<224> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<223> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<222> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<221> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<220> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<219> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<218> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<217> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<216> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<215> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<214> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<213> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<212> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<211> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<210> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<209> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<208> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<207> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<206> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<205> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<204> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<203> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<202> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<201> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<200> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<199> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<198> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<197> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<196> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<195> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<194> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<193> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<192> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<191> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<190> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<189> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<188> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<187> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<186> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<185> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<184> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<183> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<182> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<181> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<180> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<179> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<178> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<177> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<176> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<175> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<174> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<173> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<172> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<171> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<170> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<169> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<168> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<167> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<166> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<165> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<164> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<163> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<162> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<161> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<160> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<159> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<158> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<157> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<156> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<155> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<154> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<153> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<152> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<151> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<150> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<149> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<148> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<147> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<146> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<145> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<144> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<143> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<142> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<141> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<140> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<139> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<138> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<137> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<136> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<135> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<134> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<133> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<132> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<131> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<130> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<129> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<128> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<127> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<126> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<125> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<124> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<123> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<122> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<121> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<120> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<119> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<118> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<117> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<116> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<115> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<114> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<113> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<112> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<111> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<110> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<109> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<108> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<107> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<106> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<105> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<104> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<103> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<102> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<101> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<100> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<99> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<98> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<97> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<96> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<95> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<94> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<93> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<92> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<91> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<90> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<89> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<88> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<87> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<86> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<85> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<84> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<83> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<82> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<81> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<80> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<79> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<78> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<77> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<76> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<75> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<74> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<73> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<72> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<71> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<70> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<69> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<68> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<67> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<66> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<65> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<64> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<63> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<62> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<61> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<60> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<59> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<58> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<57> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<56> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<55> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<54> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<53> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<52> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<51> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<50> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<49> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<48> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<47> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<46> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<45> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<44> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<43> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<42> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<41> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<40> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<39> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<38> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<37> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<36> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<35> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<34> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<33> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<32> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<31> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<30> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<29> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<28> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<27> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<26> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<25> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<24> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<23> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<22> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<21> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<20> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<19> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<18> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<17> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<16> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<15> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<14> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<13> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<12> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<11> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<10> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<9> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<8> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<7> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<6> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<5> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<4> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<3> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<2> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<1> VDD VSS / RSC_IHPSG13_FILLCAP8 +XDEC00<10> ADDR_N_I<9> ADDR_N_I<8> CS_I CS04<0> VDD VSS / ++ RM_IHPSG13_256x16_c2_2P_DEC00 +XDEC00<9> ADDR_N_I<7> ADDR_N_I<6> CS04<1> CS02<4> VDD VSS / ++ RM_IHPSG13_256x16_c2_2P_DEC00 +XDEC00<8> ADDR_N_I<7> ADDR_N_I<6> CS04<0> CS02<0> VDD VSS / ++ RM_IHPSG13_256x16_c2_2P_DEC00 +XDEC00<7> ADDR_N_I<5> ADDR_N_I<4> CS02<7> CS00<28> VDD VSS / ++ RM_IHPSG13_256x16_c2_2P_DEC00 +XDEC00<6> ADDR_N_I<5> ADDR_N_I<4> CS02<6> CS00<24> VDD VSS / ++ RM_IHPSG13_256x16_c2_2P_DEC00 +XDEC00<5> ADDR_N_I<5> ADDR_N_I<4> CS02<5> CS00<20> VDD VSS / ++ RM_IHPSG13_256x16_c2_2P_DEC00 +XDEC00<4> ADDR_N_I<5> ADDR_N_I<4> CS02<4> CS00<16> VDD VSS / ++ RM_IHPSG13_256x16_c2_2P_DEC00 +XDEC00<3> ADDR_N_I<5> ADDR_N_I<4> CS02<3> CS00<12> VDD VSS / ++ RM_IHPSG13_256x16_c2_2P_DEC00 +XDEC00<2> ADDR_N_I<5> ADDR_N_I<4> CS02<2> CS00<8> VDD VSS / ++ RM_IHPSG13_256x16_c2_2P_DEC00 +XDEC00<1> ADDR_N_I<5> ADDR_N_I<4> CS02<1> CS00<4> VDD VSS / ++ RM_IHPSG13_256x16_c2_2P_DEC00 +XDEC00<0> ADDR_N_I<5> ADDR_N_I<4> CS02<0> CS00<0> VDD VSS / ++ RM_IHPSG13_256x16_c2_2P_DEC00 +XDEC11<9> ADDR_N_I<7> ADDR_N_I<6> CS04<1> CS02<7> VDD VSS / ++ RM_IHPSG13_256x16_c2_2P_DEC03 +XDEC11<8> ADDR_N_I<7> ADDR_N_I<6> CS04<0> CS02<3> VDD VSS / ++ RM_IHPSG13_256x16_c2_2P_DEC03 +XDEC11<7> ADDR_N_I<5> ADDR_N_I<4> CS02<7> CS00<31> VDD VSS / ++ RM_IHPSG13_256x16_c2_2P_DEC03 +XDEC11<6> ADDR_N_I<5> ADDR_N_I<4> CS02<6> CS00<27> VDD VSS / ++ RM_IHPSG13_256x16_c2_2P_DEC03 +XDEC11<5> ADDR_N_I<5> ADDR_N_I<4> CS02<5> CS00<23> VDD VSS / ++ RM_IHPSG13_256x16_c2_2P_DEC03 +XDEC11<4> ADDR_N_I<5> ADDR_N_I<4> CS02<4> CS00<19> VDD VSS / ++ RM_IHPSG13_256x16_c2_2P_DEC03 +XDEC11<3> ADDR_N_I<5> ADDR_N_I<4> CS02<3> CS00<15> VDD VSS / ++ RM_IHPSG13_256x16_c2_2P_DEC03 +XDEC11<2> ADDR_N_I<5> ADDR_N_I<4> CS02<2> CS00<11> VDD VSS / ++ RM_IHPSG13_256x16_c2_2P_DEC03 +XDEC11<1> ADDR_N_I<5> ADDR_N_I<4> CS02<1> CS00<7> VDD VSS / ++ RM_IHPSG13_256x16_c2_2P_DEC03 +XDEC11<0> ADDR_N_I<5> ADDR_N_I<4> CS02<0> CS00<3> VDD VSS / ++ RM_IHPSG13_256x16_c2_2P_DEC03 +XI0 ADDR_N_I<9> VDD VSS / RSC_IHPSG13_TIEL +.ENDS +.SUBCKT RM_IHPSG13_256x16_c2_2P_ROWREG9 ACLK_N_I ADDR_I<8> ADDR_I<7> ADDR_I<6> ADDR_I<5> ++ ADDR_I<4> ADDR_I<3> ADDR_I<2> ADDR_I<1> ADDR_I<0> ADDR_N_O<8> ADDR_N_O<7> ++ ADDR_N_O<6> ADDR_N_O<5> ADDR_N_O<4> ADDR_N_O<3> ADDR_N_O<2> ADDR_N_O<1> ++ ADDR_N_O<0> BIST_ADDR_I<8> BIST_ADDR_I<7> BIST_ADDR_I<6> BIST_ADDR_I<5> ++ BIST_ADDR_I<4> BIST_ADDR_I<3> BIST_ADDR_I<2> BIST_ADDR_I<1> BIST_ADDR_I<0> ++ BIST_EN_I VDD VSS +XDFF<8> BIST_EN_I BIST_ADDR_I<8> ACLK_N_I ADDR_I<8> q_int<8> net04<0> VDD ++ VSS / RSC_IHPSG13_DFNQMX2IX1 +XDFF<7> BIST_EN_I BIST_ADDR_I<7> ACLK_N_I ADDR_I<7> q_int<7> net04<1> VDD ++ VSS / RSC_IHPSG13_DFNQMX2IX1 +XDFF<6> BIST_EN_I BIST_ADDR_I<6> ACLK_N_I ADDR_I<6> q_int<6> net04<2> VDD ++ VSS / RSC_IHPSG13_DFNQMX2IX1 +XDFF<5> BIST_EN_I BIST_ADDR_I<5> ACLK_N_I ADDR_I<5> q_int<5> net04<3> VDD ++ VSS / RSC_IHPSG13_DFNQMX2IX1 +XDFF<4> BIST_EN_I BIST_ADDR_I<4> ACLK_N_I ADDR_I<4> q_int<4> net04<4> VDD ++ VSS / RSC_IHPSG13_DFNQMX2IX1 +XDFF<3> BIST_EN_I BIST_ADDR_I<3> ACLK_N_I ADDR_I<3> q_int<3> net04<5> VDD ++ VSS / RSC_IHPSG13_DFNQMX2IX1 +XDFF<2> BIST_EN_I BIST_ADDR_I<2> ACLK_N_I ADDR_I<2> q_int<2> net04<6> VDD ++ VSS / RSC_IHPSG13_DFNQMX2IX1 +XDFF<1> BIST_EN_I BIST_ADDR_I<1> ACLK_N_I ADDR_I<1> q_int<1> net04<7> VDD ++ VSS / RSC_IHPSG13_DFNQMX2IX1 +XDFF<0> BIST_EN_I BIST_ADDR_I<0> ACLK_N_I ADDR_I<0> q_int<0> net04<8> VDD ++ VSS / RSC_IHPSG13_DFNQMX2IX1 +XDRV<8> qn_int<8> ADDR_N_O<8> VDD VSS / RSC_IHPSG13_CINVX8 +XDRV<7> qn_int<7> ADDR_N_O<7> VDD VSS / RSC_IHPSG13_CINVX8 +XDRV<6> qn_int<6> ADDR_N_O<6> VDD VSS / RSC_IHPSG13_CINVX8 +XDRV<5> qn_int<5> ADDR_N_O<5> VDD VSS / RSC_IHPSG13_CINVX8 +XDRV<4> qn_int<4> ADDR_N_O<4> VDD VSS / RSC_IHPSG13_CINVX8 +XDRV<3> qn_int<3> ADDR_N_O<3> VDD VSS / RSC_IHPSG13_CINVX8 +XDRV<2> qn_int<2> ADDR_N_O<2> VDD VSS / RSC_IHPSG13_CINVX8 +XDRV<1> qn_int<1> ADDR_N_O<1> VDD VSS / RSC_IHPSG13_CINVX8 +XDRV<0> qn_int<0> ADDR_N_O<0> VDD VSS / RSC_IHPSG13_CINVX8 +XINV<8> q_int<8> qn_int<8> VDD VSS / RSC_IHPSG13_CINVX2 +XINV<7> q_int<7> qn_int<7> VDD VSS / RSC_IHPSG13_CINVX2 +XINV<6> q_int<6> qn_int<6> VDD VSS / RSC_IHPSG13_CINVX2 +XINV<5> q_int<5> qn_int<5> VDD VSS / RSC_IHPSG13_CINVX2 +XINV<4> q_int<4> qn_int<4> VDD VSS / RSC_IHPSG13_CINVX2 +XINV<3> q_int<3> qn_int<3> VDD VSS / RSC_IHPSG13_CINVX2 +XINV<2> q_int<2> qn_int<2> VDD VSS / RSC_IHPSG13_CINVX2 +XINV<1> q_int<1> qn_int<1> VDD VSS / RSC_IHPSG13_CINVX2 +XINV<0> q_int<0> qn_int<0> VDD VSS / RSC_IHPSG13_CINVX2 +.ENDS + +.SUBCKT RM_IHPSG13_256x16_c2_2P_DLY_MUX A SEL Z VDD VSS +XI11 net4 Z VDD VSS / RSC_IHPSG13_CINVX2 +XI8 A D<3> SEL net4 VDD VSS / RSC_IHPSG13_MX2IX1 +XI20<3> D<2> D<3> VDD VSS / RSC_IHPSG13_CDLYX1 +XI20<2> D<1> D<2> VDD VSS / RSC_IHPSG13_CDLYX1 +XI20<1> A D<1> VDD VSS / RSC_IHPSG13_CDLYX1 +.ENDS +.SUBCKT RM_IHPSG13_256x16_c2_2P_CTRL ACLK_N BIST_CK_I BIST_CS_I BIST_EN BIST_RE_I ++ BIST_WE_I B_TIEL_O CK_I CS_I DCLK ECLK PULSE_H PULSE_L PULSE_O RCLK RE_I ++ ROW_CS WCLK WE_I VDD VSS +XI17 ck_regs we col_we VDD VSS / RSC_IHPSG13_DFNQX2 +XI16 ck_regs re col_re VDD VSS / RSC_IHPSG13_DFNQX2 +XI18 ck_regs cs net7 VDD VSS / RSC_IHPSG13_DFNQX2 +XI71 ACLK_N net012 PULSE_O VDD VSS / RSC_IHPSG13_DFNQX2 +XI77 col_we net017 net016 VDD VSS / RSC_IHPSG13_CNAND2X2 +XI76 col_re net017 net018 VDD VSS / RSC_IHPSG13_CNAND2X2 +XI15 ck_dly WEorREandCS aclk VDD VSS / RSC_IHPSG13_CGATEPX4 +XI14 ck WEandCS DCLK VDD VSS / RSC_IHPSG13_CGATEPX4 +XI60 net7 ROW_CS VDD VSS / RSC_IHPSG13_CBUFX8 +XI73 PULSE_O net012 VDD VSS / RSC_IHPSG13_CINVX2 +XI8 net017 net8 VDD VSS / RSC_IHPSG13_CINVX2 +XCAPS4<7> VDD VSS / RSC_IHPSG13_FILLCAP4 +XCAPS4<6> VDD VSS / RSC_IHPSG13_FILLCAP4 +XCAPS4<5> VDD VSS / RSC_IHPSG13_FILLCAP4 +XCAPS4<4> VDD VSS / RSC_IHPSG13_FILLCAP4 +XCAPS4<3> VDD VSS / RSC_IHPSG13_FILLCAP4 +XCAPS4<2> VDD VSS / RSC_IHPSG13_FILLCAP4 +XCAPS4<1> VDD VSS / RSC_IHPSG13_FILLCAP4 +XBM_TIEL B_TIEL_O VDD VSS / RSC_IHPSG13_TIEL +XI64 ck ck_dly VDD VSS / RSC_IHPSG13_CDLYX2 +XI86 CS_I BIST_CS_I BIST_EN cs VDD VSS / RSC_IHPSG13_MX2X2 +XI87 CK_I BIST_CK_I BIST_EN ck VDD VSS / RSC_IHPSG13_MX2X2 +XI85 WE_I BIST_WE_I BIST_EN we VDD VSS / RSC_IHPSG13_MX2X2 +XI84 RE_I BIST_RE_I BIST_EN re VDD VSS / RSC_IHPSG13_MX2X2 +XI48 ck_dly ck_regs VDD VSS / RSC_IHPSG13_CINVX4 +XI81 net016 WCLK VDD VSS / RSC_IHPSG13_CINVX4 +XI80 net018 RCLK VDD VSS / RSC_IHPSG13_CINVX4 +XI78 net8 net020 VDD VSS / RSC_IHPSG13_CINVX4 +XCAPS8<7> VDD VSS / RSC_IHPSG13_FILLCAP8 +XCAPS8<6> VDD VSS / RSC_IHPSG13_FILLCAP8 +XCAPS8<5> VDD VSS / RSC_IHPSG13_FILLCAP8 +XCAPS8<4> VDD VSS / RSC_IHPSG13_FILLCAP8 +XCAPS8<3> VDD VSS / RSC_IHPSG13_FILLCAP8 +XCAPS8<2> VDD VSS / RSC_IHPSG13_FILLCAP8 +XCAPS8<1> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI6 PULSE_L PULSE_H net017 VDD VSS / RSC_IHPSG13_XOR2X2 +XI22 we cs WEandCS VDD VSS / RSC_IHPSG13_AND2X2 +XI79 net020 ECLK VDD VSS / RSC_IHPSG13_CINVX8 +XI63 aclk ACLK_N VDD VSS / RSC_IHPSG13_CINVX8 +XI21 re we cs WEorREandCS VDD VSS / RSC_IHPSG13_OA12X1 +.ENDS +.SUBCKT RM_IHPSG13_256x16_c2_2P_COLDEC5 ACLK_N ADDR<4> ADDR<3> ADDR<2> ADDR<1> ADDR<0> ++ ADDR_COL<1> ADDR_COL<0> ADDR_DEC<7> ADDR_DEC<6> ADDR_DEC<5> ADDR_DEC<4> ++ ADDR_DEC<3> ADDR_DEC<2> ADDR_DEC<1> ADDR_DEC<0> BIST_ADDR<4> BIST_ADDR<3> ++ BIST_ADDR<2> BIST_ADDR<1> BIST_ADDR<0> BIST_EN_I VDD VSS +XI17<4> VDD VSS / RSC_IHPSG13_FILLCAP4 +XI17<3> VDD VSS / RSC_IHPSG13_FILLCAP4 +XI17<2> VDD VSS / RSC_IHPSG13_FILLCAP4 +XI17<1> VDD VSS / RSC_IHPSG13_FILLCAP4 +XI1<7> PADR<0> PADR<1> PADR<2> addr_n<7> VDD VSS / RSC_IHPSG13_NAND3X2 +XI1<6> NADR<0> PADR<1> PADR<2> addr_n<6> VDD VSS / RSC_IHPSG13_NAND3X2 +XI1<5> PADR<0> NADR<1> PADR<2> addr_n<5> VDD VSS / RSC_IHPSG13_NAND3X2 +XI1<4> NADR<0> NADR<1> PADR<2> addr_n<4> VDD VSS / RSC_IHPSG13_NAND3X2 +XI1<3> PADR<0> PADR<1> NADR<2> addr_n<3> VDD VSS / RSC_IHPSG13_NAND3X2 +XI1<2> NADR<0> PADR<1> NADR<2> addr_n<2> VDD VSS / RSC_IHPSG13_NAND3X2 +XI1<1> PADR<0> NADR<1> NADR<2> addr_n<1> VDD VSS / RSC_IHPSG13_NAND3X2 +XI1<0> NADR<0> NADR<1> NADR<2> addr_n<0> VDD VSS / RSC_IHPSG13_NAND3X2 +XDFF<4> BIST_EN_I BIST_ADDR<4> ACLK_N ADDR<4> addr_int<1> net13<0> VDD ++ VSS / RSC_IHPSG13_DFNQMX2IX1 +XDFF<3> BIST_EN_I BIST_ADDR<3> ACLK_N ADDR<3> addr_int<0> net13<1> VDD ++ VSS / RSC_IHPSG13_DFNQMX2IX1 +XDFF<2> BIST_EN_I BIST_ADDR<2> ACLK_N ADDR<2> padr_int<2> net13<2> VDD ++ VSS / RSC_IHPSG13_DFNQMX2IX1 +XDFF<1> BIST_EN_I BIST_ADDR<1> ACLK_N ADDR<1> padr_int<1> net13<3> VDD ++ VSS / RSC_IHPSG13_DFNQMX2IX1 +XDFF<0> BIST_EN_I BIST_ADDR<0> ACLK_N ADDR<0> padr_int<0> net13<4> VDD ++ VSS / RSC_IHPSG13_DFNQMX2IX1 +XI3<2> padr_int<2> NADR<2> VDD VSS / RSC_IHPSG13_INVX2 +XI3<1> padr_int<1> NADR<1> VDD VSS / RSC_IHPSG13_INVX2 +XI3<0> padr_int<0> NADR<0> VDD VSS / RSC_IHPSG13_INVX2 +XI2<7> addr_n<7> ADDR_DEC<7> VDD VSS / RSC_IHPSG13_INVX2 +XI2<6> addr_n<6> ADDR_DEC<6> VDD VSS / RSC_IHPSG13_INVX2 +XI2<5> addr_n<5> ADDR_DEC<5> VDD VSS / RSC_IHPSG13_INVX2 +XI2<4> addr_n<4> ADDR_DEC<4> VDD VSS / RSC_IHPSG13_INVX2 +XI2<3> addr_n<3> ADDR_DEC<3> VDD VSS / RSC_IHPSG13_INVX2 +XI2<2> addr_n<2> ADDR_DEC<2> VDD VSS / RSC_IHPSG13_INVX2 +XI2<1> addr_n<1> ADDR_DEC<1> VDD VSS / RSC_IHPSG13_INVX2 +XI2<0> addr_n<0> ADDR_DEC<0> VDD VSS / RSC_IHPSG13_INVX2 +XI15<2> NADR<2> PADR<2> VDD VSS / RSC_IHPSG13_INVX2 +XI15<1> NADR<1> PADR<1> VDD VSS / RSC_IHPSG13_INVX2 +XI15<0> NADR<0> PADR<0> VDD VSS / RSC_IHPSG13_INVX2 +XI13<1> addr_int<1> ADDR_COL<1> VDD VSS / RSC_IHPSG13_CBUFX2 +XI13<0> addr_int<0> ADDR_COL<0> VDD VSS / RSC_IHPSG13_CBUFX2 +XI14<5> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI14<4> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI14<3> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI14<2> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI14<1> VDD VSS / RSC_IHPSG13_FILLCAP8 +.ENDS +.SUBCKT RM_IHPSG13_256x16_c2_2P_BLDRV A_BLC<3> A_BLC<2> A_BLC<1> A_BLC<0> A_BLC_SEL ++ A_BLT<3> A_BLT<2> A_BLT<1> A_BLT<0> A_BLT_SEL A_PRE_N A_SEL_P<3> A_SEL_P<2> ++ A_SEL_P<1> A_SEL_P<0> A_WR_ONE A_WR_ZERO B_BLC<3> B_BLC<2> B_BLC<1> B_BLC<0> ++ B_BLC_SEL B_BLT<3> B_BLT<2> B_BLT<1> B_BLT<0> B_BLT_SEL B_PRE_N B_SEL_P<3> ++ B_SEL_P<2> B_SEL_P<1> B_SEL_P<0> B_WR_ONE B_WR_ZERO VDD VSS +MA_CWN<3> A_BLC<3> A_BLC_NMOS_DRIVE<3> VSS VSS sg13_lv_nmos m=1 ++ w=4.82u l=130.00n ng=2 nrd=0 nrs=0 +MA_CWN<2> A_BLC<2> A_BLC_NMOS_DRIVE<2> VSS VSS sg13_lv_nmos m=1 ++ w=4.82u l=130.00n ng=2 nrd=0 nrs=0 +MA_CWN<1> A_BLC<1> A_BLC_NMOS_DRIVE<1> VSS VSS sg13_lv_nmos m=1 ++ w=4.82u l=130.00n ng=2 nrd=0 nrs=0 +MA_CWN<0> A_BLC<0> A_BLC_NMOS_DRIVE<0> VSS VSS sg13_lv_nmos m=1 ++ w=4.82u l=130.00n ng=2 nrd=0 nrs=0 +MA_TWN<3> A_BLT<3> A_BLT_NMOS_DRIVE<3> VSS VSS sg13_lv_nmos m=1 ++ w=4.82u l=130.00n ng=2 nrd=0 nrs=0 +MA_TWN<2> A_BLT<2> A_BLT_NMOS_DRIVE<2> VSS VSS sg13_lv_nmos m=1 ++ w=4.82u l=130.00n ng=2 nrd=0 nrs=0 +MA_TWN<1> A_BLT<1> A_BLT_NMOS_DRIVE<1> VSS VSS sg13_lv_nmos m=1 ++ w=4.82u l=130.00n ng=2 nrd=0 nrs=0 +MA_TWN<0> A_BLT<0> A_BLT_NMOS_DRIVE<0> VSS VSS sg13_lv_nmos m=1 ++ w=4.82u l=130.00n ng=2 nrd=0 nrs=0 +MB_TWN<3> B_BLT<3> B_BLT_NMOS_DRIVE<3> VSS VSS sg13_lv_nmos m=1 ++ w=4.82u l=130.00n ng=2 nrd=0 nrs=0 +MB_TWN<2> B_BLT<2> B_BLT_NMOS_DRIVE<2> VSS VSS sg13_lv_nmos m=1 ++ w=4.82u l=130.00n ng=2 nrd=0 nrs=0 +MB_TWN<1> B_BLT<1> B_BLT_NMOS_DRIVE<1> VSS VSS sg13_lv_nmos m=1 ++ w=4.82u l=130.00n ng=2 nrd=0 nrs=0 +MB_TWN<0> B_BLT<0> B_BLT_NMOS_DRIVE<0> VSS VSS sg13_lv_nmos m=1 ++ w=4.82u l=130.00n ng=2 nrd=0 nrs=0 +MB_CWN<3> B_BLC<3> B_BLC_NMOS_DRIVE<3> VSS VSS sg13_lv_nmos m=1 ++ w=4.82u l=130.00n ng=2 nrd=0 nrs=0 +MB_CWN<2> B_BLC<2> B_BLC_NMOS_DRIVE<2> VSS VSS sg13_lv_nmos m=1 ++ w=4.82u l=130.00n ng=2 nrd=0 nrs=0 +MB_CWN<1> B_BLC<1> B_BLC_NMOS_DRIVE<1> VSS VSS sg13_lv_nmos m=1 ++ w=4.82u l=130.00n ng=2 nrd=0 nrs=0 +MB_CWN<0> B_BLC<0> B_BLC_NMOS_DRIVE<0> VSS VSS sg13_lv_nmos m=1 ++ w=4.82u l=130.00n ng=2 nrd=0 nrs=0 +MA_CPR<3> A_BLC<3> A_PRE_N VDD VDD sg13_lv_pmos m=1 w=3.000u l=130.00n ++ ng=2 nrd=0 nrs=0 +MA_CPR<2> A_BLC<2> A_PRE_N VDD VDD sg13_lv_pmos m=1 w=3.000u l=130.00n ++ ng=2 nrd=0 nrs=0 +MA_CPR<1> A_BLC<1> A_PRE_N VDD VDD sg13_lv_pmos m=1 w=3.000u l=130.00n ++ ng=2 nrd=0 nrs=0 +MA_CPR<0> A_BLC<0> A_PRE_N VDD VDD sg13_lv_pmos m=1 w=3.000u l=130.00n ++ ng=2 nrd=0 nrs=0 +MA_TWP<3> A_BLT<3> A_BLT_PMOS_DRIVE<3> VDD VDD sg13_lv_pmos m=1 w=1.5u ++ l=130.00n ng=1 nrd=0 nrs=0 +MA_TWP<2> A_BLT<2> A_BLT_PMOS_DRIVE<2> VDD VDD sg13_lv_pmos m=1 w=1.5u ++ l=130.00n ng=1 nrd=0 nrs=0 +MA_TWP<1> A_BLT<1> A_BLT_PMOS_DRIVE<1> VDD VDD sg13_lv_pmos m=1 w=1.5u ++ l=130.00n ng=1 nrd=0 nrs=0 +MA_TWP<0> A_BLT<0> A_BLT_PMOS_DRIVE<0> VDD VDD sg13_lv_pmos m=1 w=1.5u ++ l=130.00n ng=1 nrd=0 nrs=0 +MA_CWP<3> A_BLC<3> A_BLC_PMOS_DRIVE<3> VDD VDD sg13_lv_pmos m=1 w=1.5u ++ l=130.00n ng=1 nrd=0 nrs=0 +MA_CWP<2> A_BLC<2> A_BLC_PMOS_DRIVE<2> VDD VDD sg13_lv_pmos m=1 w=1.5u ++ l=130.00n ng=1 nrd=0 nrs=0 +MA_CWP<1> A_BLC<1> A_BLC_PMOS_DRIVE<1> VDD VDD sg13_lv_pmos m=1 w=1.5u ++ l=130.00n ng=1 nrd=0 nrs=0 +MA_CWP<0> A_BLC<0> A_BLC_PMOS_DRIVE<0> VDD VDD sg13_lv_pmos m=1 w=1.5u ++ l=130.00n ng=1 nrd=0 nrs=0 +MA_TPR<3> A_BLT<3> A_PRE_N VDD VDD sg13_lv_pmos m=1 w=3.000u l=130.00n ++ ng=2 nrd=0 nrs=0 +MA_TPR<2> A_BLT<2> A_PRE_N VDD VDD sg13_lv_pmos m=1 w=3.000u l=130.00n ++ ng=2 nrd=0 nrs=0 +MA_TPR<1> A_BLT<1> A_PRE_N VDD VDD sg13_lv_pmos m=1 w=3.000u l=130.00n ++ ng=2 nrd=0 nrs=0 +MA_TPR<0> A_BLT<0> A_PRE_N VDD VDD sg13_lv_pmos m=1 w=3.000u l=130.00n ++ ng=2 nrd=0 nrs=0 +MA_TSP<3> A_BLT_SEL A_SEL_N<3> A_BLT<3> VDD sg13_lv_pmos m=1 w=1.5u ++ l=130.00n ng=1 nrd=0 nrs=0 +MA_TSP<2> A_BLT_SEL A_SEL_N<2> A_BLT<2> VDD sg13_lv_pmos m=1 w=1.5u ++ l=130.00n ng=1 nrd=0 nrs=0 +MA_TSP<1> A_BLT_SEL A_SEL_N<1> A_BLT<1> VDD sg13_lv_pmos m=1 w=1.5u ++ l=130.00n ng=1 nrd=0 nrs=0 +MA_TSP<0> A_BLT_SEL A_SEL_N<0> A_BLT<0> VDD sg13_lv_pmos m=1 w=1.5u ++ l=130.00n ng=1 nrd=0 nrs=0 +MA_CSP<3> A_BLC_SEL A_SEL_N<3> A_BLC<3> VDD sg13_lv_pmos m=1 w=1.5u ++ l=130.00n ng=1 nrd=0 nrs=0 +MA_CSP<2> A_BLC_SEL A_SEL_N<2> A_BLC<2> VDD sg13_lv_pmos m=1 w=1.5u ++ l=130.00n ng=1 nrd=0 nrs=0 +MA_CSP<1> A_BLC_SEL A_SEL_N<1> A_BLC<1> VDD sg13_lv_pmos m=1 w=1.5u ++ l=130.00n ng=1 nrd=0 nrs=0 +MA_CSP<0> A_BLC_SEL A_SEL_N<0> A_BLC<0> VDD sg13_lv_pmos m=1 w=1.5u ++ l=130.00n ng=1 nrd=0 nrs=0 +MB_CWP<3> B_BLC<3> B_BLC_PMOS_DRIVE<3> VDD VDD sg13_lv_pmos m=1 w=1.5u ++ l=130.00n ng=1 nrd=0 nrs=0 +MB_CWP<2> B_BLC<2> B_BLC_PMOS_DRIVE<2> VDD VDD sg13_lv_pmos m=1 w=1.5u ++ l=130.00n ng=1 nrd=0 nrs=0 +MB_CWP<1> B_BLC<1> B_BLC_PMOS_DRIVE<1> VDD VDD sg13_lv_pmos m=1 w=1.5u ++ l=130.00n ng=1 nrd=0 nrs=0 +MB_CWP<0> B_BLC<0> B_BLC_PMOS_DRIVE<0> VDD VDD sg13_lv_pmos m=1 w=1.5u ++ l=130.00n ng=1 nrd=0 nrs=0 +MB_TWP<3> B_BLT<3> B_BLT_PMOS_DRIVE<3> VDD VDD sg13_lv_pmos m=1 w=1.5u ++ l=130.00n ng=1 nrd=0 nrs=0 +MB_TWP<2> B_BLT<2> B_BLT_PMOS_DRIVE<2> VDD VDD sg13_lv_pmos m=1 w=1.5u ++ l=130.00n ng=1 nrd=0 nrs=0 +MB_TWP<1> B_BLT<1> B_BLT_PMOS_DRIVE<1> VDD VDD sg13_lv_pmos m=1 w=1.5u ++ l=130.00n ng=1 nrd=0 nrs=0 +MB_TWP<0> B_BLT<0> B_BLT_PMOS_DRIVE<0> VDD VDD sg13_lv_pmos m=1 w=1.5u ++ l=130.00n ng=1 nrd=0 nrs=0 +MB_TSP<3> B_BLT_SEL B_SEL_N<3> B_BLT<3> VDD sg13_lv_pmos m=1 w=1.5u ++ l=130.00n ng=1 nrd=0 nrs=0 +MB_TSP<2> B_BLT_SEL B_SEL_N<2> B_BLT<2> VDD sg13_lv_pmos m=1 w=1.5u ++ l=130.00n ng=1 nrd=0 nrs=0 +MB_TSP<1> B_BLT_SEL B_SEL_N<1> B_BLT<1> VDD sg13_lv_pmos m=1 w=1.5u ++ l=130.00n ng=1 nrd=0 nrs=0 +MB_TSP<0> B_BLT_SEL B_SEL_N<0> B_BLT<0> VDD sg13_lv_pmos m=1 w=1.5u ++ l=130.00n ng=1 nrd=0 nrs=0 +MB_TPR<3> B_BLT<3> B_PRE_N VDD VDD sg13_lv_pmos m=1 w=3.000u l=130.00n ++ ng=2 nrd=0 nrs=0 +MB_TPR<2> B_BLT<2> B_PRE_N VDD VDD sg13_lv_pmos m=1 w=3.000u l=130.00n ++ ng=2 nrd=0 nrs=0 +MB_TPR<1> B_BLT<1> B_PRE_N VDD VDD sg13_lv_pmos m=1 w=3.000u l=130.00n ++ ng=2 nrd=0 nrs=0 +MB_TPR<0> B_BLT<0> B_PRE_N VDD VDD sg13_lv_pmos m=1 w=3.000u l=130.00n ++ ng=2 nrd=0 nrs=0 +MB_CSP<3> B_BLC_SEL B_SEL_N<3> B_BLC<3> VDD sg13_lv_pmos m=1 w=1.5u ++ l=130.00n ng=1 nrd=0 nrs=0 +MB_CSP<2> B_BLC_SEL B_SEL_N<2> B_BLC<2> VDD sg13_lv_pmos m=1 w=1.5u ++ l=130.00n ng=1 nrd=0 nrs=0 +MB_CSP<1> B_BLC_SEL B_SEL_N<1> B_BLC<1> VDD sg13_lv_pmos m=1 w=1.5u ++ l=130.00n ng=1 nrd=0 nrs=0 +MB_CSP<0> B_BLC_SEL B_SEL_N<0> B_BLC<0> VDD sg13_lv_pmos m=1 w=1.5u ++ l=130.00n ng=1 nrd=0 nrs=0 +MB_CPR<3> B_BLC<3> B_PRE_N VDD VDD sg13_lv_pmos m=1 w=3.000u l=130.00n ++ ng=2 nrd=0 nrs=0 +MB_CPR<2> B_BLC<2> B_PRE_N VDD VDD sg13_lv_pmos m=1 w=3.000u l=130.00n ++ ng=2 nrd=0 nrs=0 +MB_CPR<1> B_BLC<1> B_PRE_N VDD VDD sg13_lv_pmos m=1 w=3.000u l=130.00n ++ ng=2 nrd=0 nrs=0 +MB_CPR<0> B_BLC<0> B_PRE_N VDD VDD sg13_lv_pmos m=1 w=3.000u l=130.00n ++ ng=2 nrd=0 nrs=0 +XA_SEL<3> A_SEL_P<3> A_SEL_N<3> VDD VSS / RSC_IHPSG13_INVX2 +XA_SEL<2> A_SEL_P<2> A_SEL_N<2> VDD VSS / RSC_IHPSG13_INVX2 +XA_SEL<1> A_SEL_P<1> A_SEL_N<1> VDD VSS / RSC_IHPSG13_INVX2 +XA_SEL<0> A_SEL_P<0> A_SEL_N<0> VDD VSS / RSC_IHPSG13_INVX2 +XA_CINV<3> A_BLT_PMOS_DRIVE<3> A_BLC_NMOS_DRIVE<3> VDD VSS / ++ RSC_IHPSG13_INVX2 +XA_CINV<2> A_BLT_PMOS_DRIVE<2> A_BLC_NMOS_DRIVE<2> VDD VSS / ++ RSC_IHPSG13_INVX2 +XA_CINV<1> A_BLT_PMOS_DRIVE<1> A_BLC_NMOS_DRIVE<1> VDD VSS / ++ RSC_IHPSG13_INVX2 +XA_CINV<0> A_BLT_PMOS_DRIVE<0> A_BLC_NMOS_DRIVE<0> VDD VSS / ++ RSC_IHPSG13_INVX2 +XA_TINV<3> A_BLC_PMOS_DRIVE<3> A_BLT_NMOS_DRIVE<3> VDD VSS / ++ RSC_IHPSG13_INVX2 +XA_TINV<2> A_BLC_PMOS_DRIVE<2> A_BLT_NMOS_DRIVE<2> VDD VSS / ++ RSC_IHPSG13_INVX2 +XA_TINV<1> A_BLC_PMOS_DRIVE<1> A_BLT_NMOS_DRIVE<1> VDD VSS / ++ RSC_IHPSG13_INVX2 +XA_TINV<0> A_BLC_PMOS_DRIVE<0> A_BLT_NMOS_DRIVE<0> VDD VSS / ++ RSC_IHPSG13_INVX2 +XB_SEL<3> B_SEL_P<3> B_SEL_N<3> VDD VSS / RSC_IHPSG13_INVX2 +XB_SEL<2> B_SEL_P<2> B_SEL_N<2> VDD VSS / RSC_IHPSG13_INVX2 +XB_SEL<1> B_SEL_P<1> B_SEL_N<1> VDD VSS / RSC_IHPSG13_INVX2 +XB_SEL<0> B_SEL_P<0> B_SEL_N<0> VDD VSS / RSC_IHPSG13_INVX2 +XB_TINV<3> B_BLC_PMOS_DRIVE<3> B_BLT_NMOS_DRIVE<3> VDD VSS / ++ RSC_IHPSG13_INVX2 +XB_TINV<2> B_BLC_PMOS_DRIVE<2> B_BLT_NMOS_DRIVE<2> VDD VSS / ++ RSC_IHPSG13_INVX2 +XB_TINV<1> B_BLC_PMOS_DRIVE<1> B_BLT_NMOS_DRIVE<1> VDD VSS / ++ RSC_IHPSG13_INVX2 +XB_TINV<0> B_BLC_PMOS_DRIVE<0> B_BLT_NMOS_DRIVE<0> VDD VSS / ++ RSC_IHPSG13_INVX2 +XB_CINV<3> B_BLT_PMOS_DRIVE<3> B_BLC_NMOS_DRIVE<3> VDD VSS / ++ RSC_IHPSG13_INVX2 +XB_CINV<2> B_BLT_PMOS_DRIVE<2> B_BLC_NMOS_DRIVE<2> VDD VSS / ++ RSC_IHPSG13_INVX2 +XB_CINV<1> B_BLT_PMOS_DRIVE<1> B_BLC_NMOS_DRIVE<1> VDD VSS / ++ RSC_IHPSG13_INVX2 +XB_CINV<0> B_BLT_PMOS_DRIVE<0> B_BLC_NMOS_DRIVE<0> VDD VSS / ++ RSC_IHPSG13_INVX2 +XA_TDEC<3> A_SEL_P<3> A_WR_ONE A_BLT_PMOS_DRIVE<3> VDD VSS / ++ RSC_IHPSG13_NAND2X2 +XA_TDEC<2> A_SEL_P<2> A_WR_ONE A_BLT_PMOS_DRIVE<2> VDD VSS / ++ RSC_IHPSG13_NAND2X2 +XA_TDEC<1> A_SEL_P<1> A_WR_ONE A_BLT_PMOS_DRIVE<1> VDD VSS / ++ RSC_IHPSG13_NAND2X2 +XA_TDEC<0> A_SEL_P<0> A_WR_ONE A_BLT_PMOS_DRIVE<0> VDD VSS / ++ RSC_IHPSG13_NAND2X2 +XA_CDEC<3> A_SEL_P<3> A_WR_ZERO A_BLC_PMOS_DRIVE<3> VDD VSS / ++ RSC_IHPSG13_NAND2X2 +XA_CDEC<2> A_SEL_P<2> A_WR_ZERO A_BLC_PMOS_DRIVE<2> VDD VSS / ++ RSC_IHPSG13_NAND2X2 +XA_CDEC<1> A_SEL_P<1> A_WR_ZERO A_BLC_PMOS_DRIVE<1> VDD VSS / ++ RSC_IHPSG13_NAND2X2 +XA_CDEC<0> A_SEL_P<0> A_WR_ZERO A_BLC_PMOS_DRIVE<0> VDD VSS / ++ RSC_IHPSG13_NAND2X2 +XB_CDEC<3> B_SEL_P<3> B_WR_ZERO B_BLC_PMOS_DRIVE<3> VDD VSS / ++ RSC_IHPSG13_NAND2X2 +XB_CDEC<2> B_SEL_P<2> B_WR_ZERO B_BLC_PMOS_DRIVE<2> VDD VSS / ++ RSC_IHPSG13_NAND2X2 +XB_CDEC<1> B_SEL_P<1> B_WR_ZERO B_BLC_PMOS_DRIVE<1> VDD VSS / ++ RSC_IHPSG13_NAND2X2 +XB_CDEC<0> B_SEL_P<0> B_WR_ZERO B_BLC_PMOS_DRIVE<0> VDD VSS / ++ RSC_IHPSG13_NAND2X2 +XB_TDEC<3> B_SEL_P<3> B_WR_ONE B_BLT_PMOS_DRIVE<3> VDD VSS / ++ RSC_IHPSG13_NAND2X2 +XB_TDEC<2> B_SEL_P<2> B_WR_ONE B_BLT_PMOS_DRIVE<2> VDD VSS / ++ RSC_IHPSG13_NAND2X2 +XB_TDEC<1> B_SEL_P<1> B_WR_ONE B_BLT_PMOS_DRIVE<1> VDD VSS / ++ RSC_IHPSG13_NAND2X2 +XB_TDEC<0> B_SEL_P<0> B_WR_ONE B_BLT_PMOS_DRIVE<0> VDD VSS / ++ RSC_IHPSG13_NAND2X2 +.ENDS +.SUBCKT RSC_IHPSG13_AND2X6 A B Z VDD VSS +MN3 Z net6 VSS VSS sg13_lv_nmos m=1 w=2.94u l=130.00n ng=3 nrd=0 nrs=0 +MN4 net9 B VSS VSS sg13_lv_nmos m=1 w=500.0n l=130.00n ng=1 nrd=0 nrs=0 +MN6 net6 A net9 VSS sg13_lv_nmos m=1 w=500.0n l=130.00n ng=1 nrd=0 nrs=0 +MP2 Z net6 VDD VDD sg13_lv_pmos m=1 w=4.86u l=130.00n ng=3 nrd=0 nrs=0 +MP0 net6 B VDD VDD sg13_lv_pmos m=1 w=860.00n l=130.00n ng=1 nrd=0 ++ nrs=0 +MP1 net6 A VDD VDD sg13_lv_pmos m=1 w=860.00n l=130.00n ng=1 nrd=0 ++ nrs=0 +.ENDS +.SUBCKT RM_IHPSG13_256x16_c2_2P_COLCTRL5 A_ADDR_COL<1> A_ADDR_COL<0> A_ADDR_DEC<7> ++ A_ADDR_DEC<6> A_ADDR_DEC<5> A_ADDR_DEC<4> A_ADDR_DEC<3> A_ADDR_DEC<2> ++ A_ADDR_DEC<1> A_ADDR_DEC<0> A_BIST_BM_I A_BIST_DW_I A_BIST_EN_I A_BLC<31> ++ A_BLC<30> A_BLC<29> A_BLC<28> A_BLC<27> A_BLC<26> A_BLC<25> A_BLC<24> ++ A_BLC<23> A_BLC<22> A_BLC<21> A_BLC<20> A_BLC<19> A_BLC<18> A_BLC<17> ++ A_BLC<16> A_BLC<15> A_BLC<14> A_BLC<13> A_BLC<12> A_BLC<11> A_BLC<10> ++ A_BLC<9> A_BLC<8> A_BLC<7> A_BLC<6> A_BLC<5> A_BLC<4> A_BLC<3> A_BLC<2> ++ A_BLC<1> A_BLC<0> A_BLT<31> A_BLT<30> A_BLT<29> A_BLT<28> A_BLT<27> ++ A_BLT<26> A_BLT<25> A_BLT<24> A_BLT<23> A_BLT<22> A_BLT<21> A_BLT<20> ++ A_BLT<19> A_BLT<18> A_BLT<17> A_BLT<16> A_BLT<15> A_BLT<14> A_BLT<13> ++ A_BLT<12> A_BLT<11> A_BLT<10> A_BLT<9> A_BLT<8> A_BLT<7> A_BLT<6> A_BLT<5> ++ A_BLT<4> A_BLT<3> A_BLT<2> A_BLT<1> A_BLT<0> A_BM_I A_DCLK_B_L A_DCLK_B_R ++ A_DCLK_L A_DCLK_R A_DR_O A_DW_I A_RCLK_B_L A_RCLK_B_R A_RCLK_L A_RCLK_R ++ A_TIEH_O A_WCLK_B_L A_WCLK_B_R A_WCLK_L A_WCLK_R B_ADDR_COL<1> B_ADDR_COL<0> ++ B_ADDR_DEC<7> B_ADDR_DEC<6> B_ADDR_DEC<5> B_ADDR_DEC<4> B_ADDR_DEC<3> ++ B_ADDR_DEC<2> B_ADDR_DEC<1> B_ADDR_DEC<0> B_BIST_BM_I B_BIST_DW_I ++ B_BIST_EN_I B_BLC<31> B_BLC<30> B_BLC<29> B_BLC<28> B_BLC<27> B_BLC<26> ++ B_BLC<25> B_BLC<24> B_BLC<23> B_BLC<22> B_BLC<21> B_BLC<20> B_BLC<19> ++ B_BLC<18> B_BLC<17> B_BLC<16> B_BLC<15> B_BLC<14> B_BLC<13> B_BLC<12> ++ B_BLC<11> B_BLC<10> B_BLC<9> B_BLC<8> B_BLC<7> B_BLC<6> B_BLC<5> B_BLC<4> ++ B_BLC<3> B_BLC<2> B_BLC<1> B_BLC<0> B_BLT<31> B_BLT<30> B_BLT<29> B_BLT<28> ++ B_BLT<27> B_BLT<26> B_BLT<25> B_BLT<24> B_BLT<23> B_BLT<22> B_BLT<21> ++ B_BLT<20> B_BLT<19> B_BLT<18> B_BLT<17> B_BLT<16> B_BLT<15> B_BLT<14> ++ B_BLT<13> B_BLT<12> B_BLT<11> B_BLT<10> B_BLT<9> B_BLT<8> B_BLT<7> B_BLT<6> ++ B_BLT<5> B_BLT<4> B_BLT<3> B_BLT<2> B_BLT<1> B_BLT<0> B_BM_I B_DCLK_B_L ++ B_DCLK_B_R B_DCLK_L B_DCLK_R B_DR_O B_DW_I B_RCLK_B_L B_RCLK_B_R B_RCLK_L ++ B_RCLK_R B_TIEH_O B_WCLK_B_L B_WCLK_B_R B_WCLK_L B_WCLK_R VDD VSS +XB_I80<1> B_WCLK_B_L B_RCLK_B_L B_W_nor_R<1> VDD VSS / ++ RSC_IHPSG13_AND2X2 +XB_I80<0> B_WCLK_B_L B_RCLK_B_L B_W_nor_R<0> VDD VSS / ++ RSC_IHPSG13_AND2X2 +XA_I80<1> A_WCLK_B_L A_RCLK_B_L A_W_nor_R<1> VDD VSS / ++ RSC_IHPSG13_AND2X2 +XA_I80<0> A_WCLK_B_L A_RCLK_B_L A_W_nor_R<0> VDD VSS / ++ RSC_IHPSG13_AND2X2 +XB_I44 B_BM_N B_WCLK_B_L B_DO_WRITE_P VDD VSS / RSC_IHPSG13_NOR2X2 +XA_I44 A_BM_N A_WCLK_B_L A_DO_WRITE_P VDD VSS / RSC_IHPSG13_NOR2X2 +XI_FILL4<16> VDD VSS / RSC_IHPSG13_FILLCAP4 +XI_FILL4<15> VDD VSS / RSC_IHPSG13_FILLCAP4 +XI_FILL4<14> VDD VSS / RSC_IHPSG13_FILLCAP4 +XI_FILL4<13> VDD VSS / RSC_IHPSG13_FILLCAP4 +XI_FILL4<12> VDD VSS / RSC_IHPSG13_FILLCAP4 +XI_FILL4<11> VDD VSS / RSC_IHPSG13_FILLCAP4 +XI_FILL4<10> VDD VSS / RSC_IHPSG13_FILLCAP4 +XI_FILL4<9> VDD VSS / RSC_IHPSG13_FILLCAP4 +XI_FILL4<8> VDD VSS / RSC_IHPSG13_FILLCAP4 +XI_FILL4<7> VDD VSS / RSC_IHPSG13_FILLCAP4 +XI_FILL4<6> VDD VSS / RSC_IHPSG13_FILLCAP4 +XI_FILL4<5> VDD VSS / RSC_IHPSG13_FILLCAP4 +XI_FILL4<4> VDD VSS / RSC_IHPSG13_FILLCAP4 +XI_FILL4<3> VDD VSS / RSC_IHPSG13_FILLCAP4 +XI_FILL4<2> VDD VSS / RSC_IHPSG13_FILLCAP4 +XI_FILL4<1> VDD VSS / RSC_IHPSG13_FILLCAP4 +XB_INV<6> B_N1<1> B_P1<1> VDD VSS / RSC_IHPSG13_CINVX4 +XB_INV<5> B_N0<1> B_P0<1> VDD VSS / RSC_IHPSG13_CINVX4 +XB_INV<4> B_N0<0> B_P0<0> VDD VSS / RSC_IHPSG13_CINVX4 +XB_INV<3> B_ADDR_COL<1> B_N1<1> VDD VSS / RSC_IHPSG13_CINVX4 +XB_INV<2> B_ADDR_COL<1> B_N1<0> VDD VSS / RSC_IHPSG13_CINVX4 +XB_INV<1> B_ADDR_COL<0> B_N0<1> VDD VSS / RSC_IHPSG13_CINVX4 +XB_INV<0> B_ADDR_COL<0> B_N0<0> VDD VSS / RSC_IHPSG13_CINVX4 +XA_INV<6> A_N1<1> A_P1<1> VDD VSS / RSC_IHPSG13_CINVX4 +XA_INV<5> A_N0<1> A_P0<1> VDD VSS / RSC_IHPSG13_CINVX4 +XA_INV<4> A_N0<0> A_P0<0> VDD VSS / RSC_IHPSG13_CINVX4 +XA_INV<3> A_ADDR_COL<1> A_N1<1> VDD VSS / RSC_IHPSG13_CINVX4 +XA_INV<2> A_ADDR_COL<1> A_N1<0> VDD VSS / RSC_IHPSG13_CINVX4 +XA_INV<1> A_ADDR_COL<0> A_N0<1> VDD VSS / RSC_IHPSG13_CINVX4 +XA_INV<0> A_ADDR_COL<0> A_N0<0> VDD VSS / RSC_IHPSG13_CINVX4 +XB_I81<3> B_W_nor_R<1> B_PRE_N VDD VSS / RSC_IHPSG13_CINVX4_WN +XB_I81<2> B_W_nor_R<1> B_PRE_N VDD VSS / RSC_IHPSG13_CINVX4_WN +XB_I81<1> B_W_nor_R<0> B_PRE_N VDD VSS / RSC_IHPSG13_CINVX4_WN +XB_I81<0> B_W_nor_R<0> B_PRE_N VDD VSS / RSC_IHPSG13_CINVX4_WN +XA_I81<3> A_W_nor_R<1> A_PRE_N VDD VSS / RSC_IHPSG13_CINVX4_WN +XA_I81<2> A_W_nor_R<1> A_PRE_N VDD VSS / RSC_IHPSG13_CINVX4_WN +XA_I81<1> A_W_nor_R<0> A_PRE_N VDD VSS / RSC_IHPSG13_CINVX4_WN +XA_I81<0> A_W_nor_R<0> A_PRE_N VDD VSS / RSC_IHPSG13_CINVX4_WN +XI_FILL8<78> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI_FILL8<77> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI_FILL8<76> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI_FILL8<75> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI_FILL8<74> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI_FILL8<73> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI_FILL8<72> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI_FILL8<71> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI_FILL8<70> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI_FILL8<69> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI_FILL8<68> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI_FILL8<67> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI_FILL8<66> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI_FILL8<65> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI_FILL8<64> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI_FILL8<63> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI_FILL8<62> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI_FILL8<61> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI_FILL8<60> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI_FILL8<59> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI_FILL8<58> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI_FILL8<57> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI_FILL8<56> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI_FILL8<55> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI_FILL8<54> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI_FILL8<53> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI_FILL8<52> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI_FILL8<51> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI_FILL8<50> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI_FILL8<49> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI_FILL8<48> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI_FILL8<47> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI_FILL8<46> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI_FILL8<45> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI_FILL8<44> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI_FILL8<43> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI_FILL8<42> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI_FILL8<41> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI_FILL8<40> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI_FILL8<39> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI_FILL8<38> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI_FILL8<37> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI_FILL8<36> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI_FILL8<35> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI_FILL8<34> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI_FILL8<33> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI_FILL8<32> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI_FILL8<31> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI_FILL8<30> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI_FILL8<29> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI_FILL8<28> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI_FILL8<27> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI_FILL8<26> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI_FILL8<25> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI_FILL8<24> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI_FILL8<23> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI_FILL8<22> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI_FILL8<21> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI_FILL8<20> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI_FILL8<19> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI_FILL8<18> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI_FILL8<17> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI_FILL8<16> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI_FILL8<15> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI_FILL8<14> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI_FILL8<13> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI_FILL8<12> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI_FILL8<11> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI_FILL8<10> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI_FILL8<9> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI_FILL8<8> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI_FILL8<7> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI_FILL8<6> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI_FILL8<5> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI_FILL8<4> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI_FILL8<3> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI_FILL8<2> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI_FILL8<1> VDD VSS / RSC_IHPSG13_FILLCAP8 +XAB_BLMUX<7> A_BLC<31> A_BLC<30> A_BLC<29> A_BLC<28> A_BLC_SEL A_BLT<31> ++ A_BLT<30> A_BLT<29> A_BLT<28> A_BLT_SEL A_PRE_N A_SEL_P<31> A_SEL_P<30> ++ A_SEL_P<29> A_SEL_P<28> A_WR_ONE A_WR_ZERO B_BLC<31> B_BLC<30> B_BLC<29> ++ B_BLC<28> B_BLC_SEL B_BLT<31> B_BLT<30> B_BLT<29> B_BLT<28> B_BLT_SEL ++ B_PRE_N B_SEL_P<31> B_SEL_P<30> B_SEL_P<29> B_SEL_P<28> B_WR_ONE B_WR_ZERO ++ VDD VSS / RM_IHPSG13_256x16_c2_2P_BLDRV +XAB_BLMUX<6> A_BLC<27> A_BLC<26> A_BLC<25> A_BLC<24> A_BLC_SEL A_BLT<27> ++ A_BLT<26> A_BLT<25> A_BLT<24> A_BLT_SEL A_PRE_N A_SEL_P<27> A_SEL_P<26> ++ A_SEL_P<25> A_SEL_P<24> A_WR_ONE A_WR_ZERO B_BLC<27> B_BLC<26> B_BLC<25> ++ B_BLC<24> B_BLC_SEL B_BLT<27> B_BLT<26> B_BLT<25> B_BLT<24> B_BLT_SEL ++ B_PRE_N B_SEL_P<27> B_SEL_P<26> B_SEL_P<25> B_SEL_P<24> B_WR_ONE B_WR_ZERO ++ VDD VSS / RM_IHPSG13_256x16_c2_2P_BLDRV +XAB_BLMUX<5> A_BLC<23> A_BLC<22> A_BLC<21> A_BLC<20> A_BLC_SEL A_BLT<23> ++ A_BLT<22> A_BLT<21> A_BLT<20> A_BLT_SEL A_PRE_N A_SEL_P<23> A_SEL_P<22> ++ A_SEL_P<21> A_SEL_P<20> A_WR_ONE A_WR_ZERO B_BLC<23> B_BLC<22> B_BLC<21> ++ B_BLC<20> B_BLC_SEL B_BLT<23> B_BLT<22> B_BLT<21> B_BLT<20> B_BLT_SEL ++ B_PRE_N B_SEL_P<23> B_SEL_P<22> B_SEL_P<21> B_SEL_P<20> B_WR_ONE B_WR_ZERO ++ VDD VSS / RM_IHPSG13_256x16_c2_2P_BLDRV +XAB_BLMUX<4> A_BLC<19> A_BLC<18> A_BLC<17> A_BLC<16> A_BLC_SEL A_BLT<19> ++ A_BLT<18> A_BLT<17> A_BLT<16> A_BLT_SEL A_PRE_N A_SEL_P<19> A_SEL_P<18> ++ A_SEL_P<17> A_SEL_P<16> A_WR_ONE A_WR_ZERO B_BLC<19> B_BLC<18> B_BLC<17> ++ B_BLC<16> B_BLC_SEL B_BLT<19> B_BLT<18> B_BLT<17> B_BLT<16> B_BLT_SEL ++ B_PRE_N B_SEL_P<19> B_SEL_P<18> B_SEL_P<17> B_SEL_P<16> B_WR_ONE B_WR_ZERO ++ VDD VSS / RM_IHPSG13_256x16_c2_2P_BLDRV +XAB_BLMUX<3> A_BLC<15> A_BLC<14> A_BLC<13> A_BLC<12> A_BLC_SEL A_BLT<15> ++ A_BLT<14> A_BLT<13> A_BLT<12> A_BLT_SEL A_PRE_N A_SEL_P<15> A_SEL_P<14> ++ A_SEL_P<13> A_SEL_P<12> A_WR_ONE A_WR_ZERO B_BLC<15> B_BLC<14> B_BLC<13> ++ B_BLC<12> B_BLC_SEL B_BLT<15> B_BLT<14> B_BLT<13> B_BLT<12> B_BLT_SEL ++ B_PRE_N B_SEL_P<15> B_SEL_P<14> B_SEL_P<13> B_SEL_P<12> B_WR_ONE B_WR_ZERO ++ VDD VSS / RM_IHPSG13_256x16_c2_2P_BLDRV +XAB_BLMUX<2> A_BLC<11> A_BLC<10> A_BLC<9> A_BLC<8> A_BLC_SEL A_BLT<11> ++ A_BLT<10> A_BLT<9> A_BLT<8> A_BLT_SEL A_PRE_N A_SEL_P<11> A_SEL_P<10> ++ A_SEL_P<9> A_SEL_P<8> A_WR_ONE A_WR_ZERO B_BLC<11> B_BLC<10> B_BLC<9> ++ B_BLC<8> B_BLC_SEL B_BLT<11> B_BLT<10> B_BLT<9> B_BLT<8> B_BLT_SEL B_PRE_N ++ B_SEL_P<11> B_SEL_P<10> B_SEL_P<9> B_SEL_P<8> B_WR_ONE B_WR_ZERO VDD ++ VSS / RM_IHPSG13_256x16_c2_2P_BLDRV +XAB_BLMUX<1> A_BLC<7> A_BLC<6> A_BLC<5> A_BLC<4> A_BLC_SEL A_BLT<7> A_BLT<6> ++ A_BLT<5> A_BLT<4> A_BLT_SEL A_PRE_N A_SEL_P<7> A_SEL_P<6> A_SEL_P<5> ++ A_SEL_P<4> A_WR_ONE A_WR_ZERO B_BLC<7> B_BLC<6> B_BLC<5> B_BLC<4> B_BLC_SEL ++ B_BLT<7> B_BLT<6> B_BLT<5> B_BLT<4> B_BLT_SEL B_PRE_N B_SEL_P<7> B_SEL_P<6> ++ B_SEL_P<5> B_SEL_P<4> B_WR_ONE B_WR_ZERO VDD VSS / ++ RM_IHPSG13_256x16_c2_2P_BLDRV +XAB_BLMUX<0> A_BLC<3> A_BLC<2> A_BLC<1> A_BLC<0> A_BLC_SEL A_BLT<3> A_BLT<2> ++ A_BLT<1> A_BLT<0> A_BLT_SEL A_PRE_N A_SEL_P<3> A_SEL_P<2> A_SEL_P<1> ++ A_SEL_P<0> A_WR_ONE A_WR_ZERO B_BLC<3> B_BLC<2> B_BLC<1> B_BLC<0> B_BLC_SEL ++ B_BLT<3> B_BLT<2> B_BLT<1> B_BLT<0> B_BLT_SEL B_PRE_N B_SEL_P<3> B_SEL_P<2> ++ B_SEL_P<1> B_SEL_P<0> B_WR_ONE B_WR_ZERO VDD VSS / ++ RM_IHPSG13_256x16_c2_2P_BLDRV +XB_I51 net037 B_DR_O VDD VSS / RSC_IHPSG13_INVX4 +XA_I51 net19 A_DR_O VDD VSS / RSC_IHPSG13_INVX4 +XB_I78 B_RCLK_B_L B_SAE VDD VSS / RSC_IHPSG13_CBUFX2 +XA_I78 A_RCLK_B_L A_SAE VDD VSS / RSC_IHPSG13_CBUFX2 +XB_I69 B_DCLK_L B_DCLK_B_L VDD VSS / RSC_IHPSG13_CINVX8 +XB_I50 B_WCLK_L B_WCLK_B_L VDD VSS / RSC_IHPSG13_CINVX8 +XB_EBUF B_RCLK_L B_RCLK_B_L VDD VSS / RSC_IHPSG13_CINVX8 +XA_I69 A_DCLK_L A_DCLK_B_L VDD VSS / RSC_IHPSG13_CINVX8 +XA_I50 A_WCLK_L A_WCLK_B_L VDD VSS / RSC_IHPSG13_CINVX8 +XA_EBUF A_RCLK_L A_RCLK_B_L VDD VSS / RSC_IHPSG13_CINVX8 +XB_I76 B_DI_N B_DO_WRITE_P B_WR_ZERO VDD VSS / RSC_IHPSG13_AND2X6 +XB_I75 B_DI_R B_DO_WRITE_P B_WR_ONE VDD VSS / RSC_IHPSG13_AND2X6 +XA_I76 A_DI_N A_DO_WRITE_P A_WR_ZERO VDD VSS / RSC_IHPSG13_AND2X6 +XA_I75 A_DI_R A_DO_WRITE_P A_WR_ONE VDD VSS / RSC_IHPSG13_AND2X6 +XB_I83 B_BM_R B_BM_N VDD VSS / RSC_IHPSG13_INVX2 +XB_DEC3INV<31> net041<0> B_SEL_P<31> VDD VSS / RSC_IHPSG13_INVX2 +XB_DEC3INV<30> net041<1> B_SEL_P<30> VDD VSS / RSC_IHPSG13_INVX2 +XB_DEC3INV<29> net041<2> B_SEL_P<29> VDD VSS / RSC_IHPSG13_INVX2 +XB_DEC3INV<28> net041<3> B_SEL_P<28> VDD VSS / RSC_IHPSG13_INVX2 +XB_DEC3INV<27> net041<4> B_SEL_P<27> VDD VSS / RSC_IHPSG13_INVX2 +XB_DEC3INV<26> net041<5> B_SEL_P<26> VDD VSS / RSC_IHPSG13_INVX2 +XB_DEC3INV<25> net041<6> B_SEL_P<25> VDD VSS / RSC_IHPSG13_INVX2 +XB_DEC3INV<24> net041<7> B_SEL_P<24> VDD VSS / RSC_IHPSG13_INVX2 +XB_DEC3INV<23> net041<8> B_SEL_P<23> VDD VSS / RSC_IHPSG13_INVX2 +XB_DEC3INV<22> net041<9> B_SEL_P<22> VDD VSS / RSC_IHPSG13_INVX2 +XB_DEC3INV<21> net041<10> B_SEL_P<21> VDD VSS / RSC_IHPSG13_INVX2 +XB_DEC3INV<20> net041<11> B_SEL_P<20> VDD VSS / RSC_IHPSG13_INVX2 +XB_DEC3INV<19> net041<12> B_SEL_P<19> VDD VSS / RSC_IHPSG13_INVX2 +XB_DEC3INV<18> net041<13> B_SEL_P<18> VDD VSS / RSC_IHPSG13_INVX2 +XB_DEC3INV<17> net041<14> B_SEL_P<17> VDD VSS / RSC_IHPSG13_INVX2 +XB_DEC3INV<16> net041<15> B_SEL_P<16> VDD VSS / RSC_IHPSG13_INVX2 +XB_DEC3INV<15> net041<16> B_SEL_P<15> VDD VSS / RSC_IHPSG13_INVX2 +XB_DEC3INV<14> net041<17> B_SEL_P<14> VDD VSS / RSC_IHPSG13_INVX2 +XB_DEC3INV<13> net041<18> B_SEL_P<13> VDD VSS / RSC_IHPSG13_INVX2 +XB_DEC3INV<12> net041<19> B_SEL_P<12> VDD VSS / RSC_IHPSG13_INVX2 +XB_DEC3INV<11> net041<20> B_SEL_P<11> VDD VSS / RSC_IHPSG13_INVX2 +XB_DEC3INV<10> net041<21> B_SEL_P<10> VDD VSS / RSC_IHPSG13_INVX2 +XB_DEC3INV<9> net041<22> B_SEL_P<9> VDD VSS / RSC_IHPSG13_INVX2 +XB_DEC3INV<8> net041<23> B_SEL_P<8> VDD VSS / RSC_IHPSG13_INVX2 +XB_DEC3INV<7> net041<24> B_SEL_P<7> VDD VSS / RSC_IHPSG13_INVX2 +XB_DEC3INV<6> net041<25> B_SEL_P<6> VDD VSS / RSC_IHPSG13_INVX2 +XB_DEC3INV<5> net041<26> B_SEL_P<5> VDD VSS / RSC_IHPSG13_INVX2 +XB_DEC3INV<4> net041<27> B_SEL_P<4> VDD VSS / RSC_IHPSG13_INVX2 +XB_DEC3INV<3> net041<28> B_SEL_P<3> VDD VSS / RSC_IHPSG13_INVX2 +XB_DEC3INV<2> net041<29> B_SEL_P<2> VDD VSS / RSC_IHPSG13_INVX2 +XB_DEC3INV<1> net041<30> B_SEL_P<1> VDD VSS / RSC_IHPSG13_INVX2 +XB_DEC3INV<0> net041<31> B_SEL_P<0> VDD VSS / RSC_IHPSG13_INVX2 +XB_I49 B_DI_R B_DI_N VDD VSS / RSC_IHPSG13_INVX2 +XA_I83 A_BM_R A_BM_N VDD VSS / RSC_IHPSG13_INVX2 +XA_DEC3INV<31> net23<0> A_SEL_P<31> VDD VSS / RSC_IHPSG13_INVX2 +XA_DEC3INV<30> net23<1> A_SEL_P<30> VDD VSS / RSC_IHPSG13_INVX2 +XA_DEC3INV<29> net23<2> A_SEL_P<29> VDD VSS / RSC_IHPSG13_INVX2 +XA_DEC3INV<28> net23<3> A_SEL_P<28> VDD VSS / RSC_IHPSG13_INVX2 +XA_DEC3INV<27> net23<4> A_SEL_P<27> VDD VSS / RSC_IHPSG13_INVX2 +XA_DEC3INV<26> net23<5> A_SEL_P<26> VDD VSS / RSC_IHPSG13_INVX2 +XA_DEC3INV<25> net23<6> A_SEL_P<25> VDD VSS / RSC_IHPSG13_INVX2 +XA_DEC3INV<24> net23<7> A_SEL_P<24> VDD VSS / RSC_IHPSG13_INVX2 +XA_DEC3INV<23> net23<8> A_SEL_P<23> VDD VSS / RSC_IHPSG13_INVX2 +XA_DEC3INV<22> net23<9> A_SEL_P<22> VDD VSS / RSC_IHPSG13_INVX2 +XA_DEC3INV<21> net23<10> A_SEL_P<21> VDD VSS / RSC_IHPSG13_INVX2 +XA_DEC3INV<20> net23<11> A_SEL_P<20> VDD VSS / RSC_IHPSG13_INVX2 +XA_DEC3INV<19> net23<12> A_SEL_P<19> VDD VSS / RSC_IHPSG13_INVX2 +XA_DEC3INV<18> net23<13> A_SEL_P<18> VDD VSS / RSC_IHPSG13_INVX2 +XA_DEC3INV<17> net23<14> A_SEL_P<17> VDD VSS / RSC_IHPSG13_INVX2 +XA_DEC3INV<16> net23<15> A_SEL_P<16> VDD VSS / RSC_IHPSG13_INVX2 +XA_DEC3INV<15> net23<16> A_SEL_P<15> VDD VSS / RSC_IHPSG13_INVX2 +XA_DEC3INV<14> net23<17> A_SEL_P<14> VDD VSS / RSC_IHPSG13_INVX2 +XA_DEC3INV<13> net23<18> A_SEL_P<13> VDD VSS / RSC_IHPSG13_INVX2 +XA_DEC3INV<12> net23<19> A_SEL_P<12> VDD VSS / RSC_IHPSG13_INVX2 +XA_DEC3INV<11> net23<20> A_SEL_P<11> VDD VSS / RSC_IHPSG13_INVX2 +XA_DEC3INV<10> net23<21> A_SEL_P<10> VDD VSS / RSC_IHPSG13_INVX2 +XA_DEC3INV<9> net23<22> A_SEL_P<9> VDD VSS / RSC_IHPSG13_INVX2 +XA_DEC3INV<8> net23<23> A_SEL_P<8> VDD VSS / RSC_IHPSG13_INVX2 +XA_DEC3INV<7> net23<24> A_SEL_P<7> VDD VSS / RSC_IHPSG13_INVX2 +XA_DEC3INV<6> net23<25> A_SEL_P<6> VDD VSS / RSC_IHPSG13_INVX2 +XA_DEC3INV<5> net23<26> A_SEL_P<5> VDD VSS / RSC_IHPSG13_INVX2 +XA_DEC3INV<4> net23<27> A_SEL_P<4> VDD VSS / RSC_IHPSG13_INVX2 +XA_DEC3INV<3> net23<28> A_SEL_P<3> VDD VSS / RSC_IHPSG13_INVX2 +XA_DEC3INV<2> net23<29> A_SEL_P<2> VDD VSS / RSC_IHPSG13_INVX2 +XA_DEC3INV<1> net23<30> A_SEL_P<1> VDD VSS / RSC_IHPSG13_INVX2 +XA_DEC3INV<0> net23<31> A_SEL_P<0> VDD VSS / RSC_IHPSG13_INVX2 +XA_I49 A_DI_R A_DI_N VDD VSS / RSC_IHPSG13_INVX2 +XB_ISENSE B_SAE B_BLC_SEL B_BLT_SEL net037 net038 VDD VSS / ++ RSC_IHPSG13_DFPQD_MSAFFX2 +XA_ISENSE A_SAE A_BLC_SEL A_BLT_SEL net19 net20 VDD VSS / ++ RSC_IHPSG13_DFPQD_MSAFFX2 +XB_DREG B_BIST_EN_I B_BIST_DW_I B_DCLK_B_L B_DW_I B_DI_R net042 VDD ++ VSS / RSC_IHPSG13_DFNQMX2IX1 +XB_BREG B_BIST_EN_I B_BIST_BM_I B_DCLK_B_L B_BM_I B_BM_R net043 VDD ++ VSS / RSC_IHPSG13_DFNQMX2IX1 +XA_DREG A_BIST_EN_I A_BIST_DW_I A_DCLK_B_L A_DW_I A_DI_R net22 VDD VSS ++ / RSC_IHPSG13_DFNQMX2IX1 +XA_BREG A_BIST_EN_I A_BIST_BM_I A_DCLK_B_L A_BM_I A_BM_R net21 VDD VSS ++ / RSC_IHPSG13_DFNQMX2IX1 +XB_DEC3<31> B_P1<1> B_P0<1> B_ADDR_DEC<7> net041<0> VDD VSS / ++ RSC_IHPSG13_NAND3X2 +XB_DEC3<30> B_P1<1> B_P0<1> B_ADDR_DEC<6> net041<1> VDD VSS / ++ RSC_IHPSG13_NAND3X2 +XB_DEC3<29> B_P1<1> B_P0<1> B_ADDR_DEC<5> net041<2> VDD VSS / ++ RSC_IHPSG13_NAND3X2 +XB_DEC3<28> B_P1<1> B_P0<1> B_ADDR_DEC<4> net041<3> VDD VSS / ++ RSC_IHPSG13_NAND3X2 +XB_DEC3<27> B_P1<1> B_P0<1> B_ADDR_DEC<3> net041<4> VDD VSS / ++ RSC_IHPSG13_NAND3X2 +XB_DEC3<26> B_P1<1> B_P0<1> B_ADDR_DEC<2> net041<5> VDD VSS / ++ RSC_IHPSG13_NAND3X2 +XB_DEC3<25> B_P1<1> B_P0<1> B_ADDR_DEC<1> net041<6> VDD VSS / ++ RSC_IHPSG13_NAND3X2 +XB_DEC3<24> B_P1<1> B_P0<1> B_ADDR_DEC<0> net041<7> VDD VSS / ++ RSC_IHPSG13_NAND3X2 +XB_DEC3<23> B_P1<1> B_N0<1> B_ADDR_DEC<7> net041<8> VDD VSS / ++ RSC_IHPSG13_NAND3X2 +XB_DEC3<22> B_P1<1> B_N0<1> B_ADDR_DEC<6> net041<9> VDD VSS / ++ RSC_IHPSG13_NAND3X2 +XB_DEC3<21> B_P1<1> B_N0<1> B_ADDR_DEC<5> net041<10> VDD VSS / ++ RSC_IHPSG13_NAND3X2 +XB_DEC3<20> B_P1<1> B_N0<1> B_ADDR_DEC<4> net041<11> VDD VSS / ++ RSC_IHPSG13_NAND3X2 +XB_DEC3<19> B_P1<1> B_N0<1> B_ADDR_DEC<3> net041<12> VDD VSS / ++ RSC_IHPSG13_NAND3X2 +XB_DEC3<18> B_P1<1> B_N0<1> B_ADDR_DEC<2> net041<13> VDD VSS / ++ RSC_IHPSG13_NAND3X2 +XB_DEC3<17> B_P1<1> B_N0<1> B_ADDR_DEC<1> net041<14> VDD VSS / ++ RSC_IHPSG13_NAND3X2 +XB_DEC3<16> B_P1<1> B_N0<1> B_ADDR_DEC<0> net041<15> VDD VSS / ++ RSC_IHPSG13_NAND3X2 +XB_DEC3<15> B_N1<0> B_P0<0> B_ADDR_DEC<7> net041<16> VDD VSS / ++ RSC_IHPSG13_NAND3X2 +XB_DEC3<14> B_N1<0> B_P0<0> B_ADDR_DEC<6> net041<17> VDD VSS / ++ RSC_IHPSG13_NAND3X2 +XB_DEC3<13> B_N1<0> B_P0<0> B_ADDR_DEC<5> net041<18> VDD VSS / ++ RSC_IHPSG13_NAND3X2 +XB_DEC3<12> B_N1<0> B_P0<0> B_ADDR_DEC<4> net041<19> VDD VSS / ++ RSC_IHPSG13_NAND3X2 +XB_DEC3<11> B_N1<0> B_P0<0> B_ADDR_DEC<3> net041<20> VDD VSS / ++ RSC_IHPSG13_NAND3X2 +XB_DEC3<10> B_N1<0> B_P0<0> B_ADDR_DEC<2> net041<21> VDD VSS / ++ RSC_IHPSG13_NAND3X2 +XB_DEC3<9> B_N1<0> B_P0<0> B_ADDR_DEC<1> net041<22> VDD VSS / ++ RSC_IHPSG13_NAND3X2 +XB_DEC3<8> B_N1<0> B_P0<0> B_ADDR_DEC<0> net041<23> VDD VSS / ++ RSC_IHPSG13_NAND3X2 +XB_DEC3<7> B_N1<0> B_N0<0> B_ADDR_DEC<7> net041<24> VDD VSS / ++ RSC_IHPSG13_NAND3X2 +XB_DEC3<6> B_N1<0> B_N0<0> B_ADDR_DEC<6> net041<25> VDD VSS / ++ RSC_IHPSG13_NAND3X2 +XB_DEC3<5> B_N1<0> B_N0<0> B_ADDR_DEC<5> net041<26> VDD VSS / ++ RSC_IHPSG13_NAND3X2 +XB_DEC3<4> B_N1<0> B_N0<0> B_ADDR_DEC<4> net041<27> VDD VSS / ++ RSC_IHPSG13_NAND3X2 +XB_DEC3<3> B_N1<0> B_N0<0> B_ADDR_DEC<3> net041<28> VDD VSS / ++ RSC_IHPSG13_NAND3X2 +XB_DEC3<2> B_N1<0> B_N0<0> B_ADDR_DEC<2> net041<29> VDD VSS / ++ RSC_IHPSG13_NAND3X2 +XB_DEC3<1> B_N1<0> B_N0<0> B_ADDR_DEC<1> net041<30> VDD VSS / ++ RSC_IHPSG13_NAND3X2 +XB_DEC3<0> B_N1<0> B_N0<0> B_ADDR_DEC<0> net041<31> VDD VSS / ++ RSC_IHPSG13_NAND3X2 +XA_DEC3<31> A_P1<1> A_P0<1> A_ADDR_DEC<7> net23<0> VDD VSS / ++ RSC_IHPSG13_NAND3X2 +XA_DEC3<30> A_P1<1> A_P0<1> A_ADDR_DEC<6> net23<1> VDD VSS / ++ RSC_IHPSG13_NAND3X2 +XA_DEC3<29> A_P1<1> A_P0<1> A_ADDR_DEC<5> net23<2> VDD VSS / ++ RSC_IHPSG13_NAND3X2 +XA_DEC3<28> A_P1<1> A_P0<1> A_ADDR_DEC<4> net23<3> VDD VSS / ++ RSC_IHPSG13_NAND3X2 +XA_DEC3<27> A_P1<1> A_P0<1> A_ADDR_DEC<3> net23<4> VDD VSS / ++ RSC_IHPSG13_NAND3X2 +XA_DEC3<26> A_P1<1> A_P0<1> A_ADDR_DEC<2> net23<5> VDD VSS / ++ RSC_IHPSG13_NAND3X2 +XA_DEC3<25> A_P1<1> A_P0<1> A_ADDR_DEC<1> net23<6> VDD VSS / ++ RSC_IHPSG13_NAND3X2 +XA_DEC3<24> A_P1<1> A_P0<1> A_ADDR_DEC<0> net23<7> VDD VSS / ++ RSC_IHPSG13_NAND3X2 +XA_DEC3<23> A_P1<1> A_N0<1> A_ADDR_DEC<7> net23<8> VDD VSS / ++ RSC_IHPSG13_NAND3X2 +XA_DEC3<22> A_P1<1> A_N0<1> A_ADDR_DEC<6> net23<9> VDD VSS / ++ RSC_IHPSG13_NAND3X2 +XA_DEC3<21> A_P1<1> A_N0<1> A_ADDR_DEC<5> net23<10> VDD VSS / ++ RSC_IHPSG13_NAND3X2 +XA_DEC3<20> A_P1<1> A_N0<1> A_ADDR_DEC<4> net23<11> VDD VSS / ++ RSC_IHPSG13_NAND3X2 +XA_DEC3<19> A_P1<1> A_N0<1> A_ADDR_DEC<3> net23<12> VDD VSS / ++ RSC_IHPSG13_NAND3X2 +XA_DEC3<18> A_P1<1> A_N0<1> A_ADDR_DEC<2> net23<13> VDD VSS / ++ RSC_IHPSG13_NAND3X2 +XA_DEC3<17> A_P1<1> A_N0<1> A_ADDR_DEC<1> net23<14> VDD VSS / ++ RSC_IHPSG13_NAND3X2 +XA_DEC3<16> A_P1<1> A_N0<1> A_ADDR_DEC<0> net23<15> VDD VSS / ++ RSC_IHPSG13_NAND3X2 +XA_DEC3<15> A_N1<0> A_P0<0> A_ADDR_DEC<7> net23<16> VDD VSS / ++ RSC_IHPSG13_NAND3X2 +XA_DEC3<14> A_N1<0> A_P0<0> A_ADDR_DEC<6> net23<17> VDD VSS / ++ RSC_IHPSG13_NAND3X2 +XA_DEC3<13> A_N1<0> A_P0<0> A_ADDR_DEC<5> net23<18> VDD VSS / ++ RSC_IHPSG13_NAND3X2 +XA_DEC3<12> A_N1<0> A_P0<0> A_ADDR_DEC<4> net23<19> VDD VSS / ++ RSC_IHPSG13_NAND3X2 +XA_DEC3<11> A_N1<0> A_P0<0> A_ADDR_DEC<3> net23<20> VDD VSS / ++ RSC_IHPSG13_NAND3X2 +XA_DEC3<10> A_N1<0> A_P0<0> A_ADDR_DEC<2> net23<21> VDD VSS / ++ RSC_IHPSG13_NAND3X2 +XA_DEC3<9> A_N1<0> A_P0<0> A_ADDR_DEC<1> net23<22> VDD VSS / ++ RSC_IHPSG13_NAND3X2 +XA_DEC3<8> A_N1<0> A_P0<0> A_ADDR_DEC<0> net23<23> VDD VSS / ++ RSC_IHPSG13_NAND3X2 +XA_DEC3<7> A_N1<0> A_N0<0> A_ADDR_DEC<7> net23<24> VDD VSS / ++ RSC_IHPSG13_NAND3X2 +XA_DEC3<6> A_N1<0> A_N0<0> A_ADDR_DEC<6> net23<25> VDD VSS / ++ RSC_IHPSG13_NAND3X2 +XA_DEC3<5> A_N1<0> A_N0<0> A_ADDR_DEC<5> net23<26> VDD VSS / ++ RSC_IHPSG13_NAND3X2 +XA_DEC3<4> A_N1<0> A_N0<0> A_ADDR_DEC<4> net23<27> VDD VSS / ++ RSC_IHPSG13_NAND3X2 +XA_DEC3<3> A_N1<0> A_N0<0> A_ADDR_DEC<3> net23<28> VDD VSS / ++ RSC_IHPSG13_NAND3X2 +XA_DEC3<2> A_N1<0> A_N0<0> A_ADDR_DEC<2> net23<29> VDD VSS / ++ RSC_IHPSG13_NAND3X2 +XA_DEC3<1> A_N1<0> A_N0<0> A_ADDR_DEC<1> net23<30> VDD VSS / ++ RSC_IHPSG13_NAND3X2 +XA_DEC3<0> A_N1<0> A_N0<0> A_ADDR_DEC<0> net23<31> VDD VSS / ++ RSC_IHPSG13_NAND3X2 +XB_I89 B_DCLK_B_L B_DCLK_B_R / RSC_IHPSG13_MET3RES +XB_I91 B_RCLK_B_L B_RCLK_B_R / RSC_IHPSG13_MET3RES +XB_I90 B_WCLK_B_L B_WCLK_B_R / RSC_IHPSG13_MET3RES +XB_I88 B_DCLK_L B_DCLK_R / RSC_IHPSG13_MET3RES +XB_I87 B_WCLK_L B_WCLK_R / RSC_IHPSG13_MET3RES +XB_R2 B_RCLK_L B_RCLK_R / RSC_IHPSG13_MET3RES +XA_I89 A_DCLK_B_L A_DCLK_B_R / RSC_IHPSG13_MET3RES +XA_I91 A_RCLK_B_L A_RCLK_B_R / RSC_IHPSG13_MET3RES +XA_I90 A_WCLK_B_L A_WCLK_B_R / RSC_IHPSG13_MET3RES +XA_I88 A_DCLK_L A_DCLK_R / RSC_IHPSG13_MET3RES +XA_I87 A_WCLK_L A_WCLK_R / RSC_IHPSG13_MET3RES +XA_R2 A_RCLK_L A_RCLK_R / RSC_IHPSG13_MET3RES +XB_BM_TIEH B_TIEH_O VDD VSS / RSC_IHPSG13_TIEH +XA_BM_TIEH A_TIEH_O VDD VSS / RSC_IHPSG13_TIEH +.ENDS +.SUBCKT RM_IHPSG13_256x16_c2_2P_COLDRV13_FILL4 VDD VSS +XI0<11> VDD VSS / RSC_IHPSG13_FILLCAP4 +XI0<10> VDD VSS / RSC_IHPSG13_FILLCAP4 +XI0<9> VDD VSS / RSC_IHPSG13_FILLCAP4 +XI0<8> VDD VSS / RSC_IHPSG13_FILLCAP4 +XI0<7> VDD VSS / RSC_IHPSG13_FILLCAP4 +XI0<6> VDD VSS / RSC_IHPSG13_FILLCAP4 +XI0<5> VDD VSS / RSC_IHPSG13_FILLCAP4 +XI0<4> VDD VSS / RSC_IHPSG13_FILLCAP4 +XI0<3> VDD VSS / RSC_IHPSG13_FILLCAP4 +XI0<2> VDD VSS / RSC_IHPSG13_FILLCAP4 +XI0<1> VDD VSS / RSC_IHPSG13_FILLCAP4 +.ENDS + + +.SUBCKT RSC_IHPSG13_CBUFX16 A Z VDD VSS +MN0 net4 A VSS VSS sg13_lv_nmos m=1 w=2.115u l=130.00n ng=3 nrd=0 nrs=0 +MN1 Z net4 VSS VSS sg13_lv_nmos m=1 w=5.64u l=130.00n ng=8 nrd=0 nrs=0 +MP1 Z net4 VDD VDD sg13_lv_pmos m=1 w=13.000u l=130.00n ng=8 nrd=0 ++ nrs=0 +MP0 net4 A VDD VDD sg13_lv_pmos m=1 w=4.89u l=130.00n ng=3 nrd=0 nrs=0 +.ENDS +.SUBCKT RM_IHPSG13_256x16_c2_1P_COLDRV13X16 ADDR_COL_I<1> ADDR_COL_I<0> ADDR_COL_O<1> ++ ADDR_COL_O<0> ADDR_DEC_I<7> ADDR_DEC_I<6> ADDR_DEC_I<5> ADDR_DEC_I<4> ++ ADDR_DEC_I<3> ADDR_DEC_I<2> ADDR_DEC_I<1> ADDR_DEC_I<0> ADDR_DEC_O<7> ++ ADDR_DEC_O<6> ADDR_DEC_O<5> ADDR_DEC_O<4> ADDR_DEC_O<3> ADDR_DEC_O<2> ++ ADDR_DEC_O<1> ADDR_DEC_O<0> DCLK_I DCLK_O RCLK_I RCLK_O WCLK_I WCLK_O ++ VDD VSS +XI1<1> VDD VSS / RSC_IHPSG13_FILLCAP4 +XI1<0> VDD VSS / RSC_IHPSG13_FILLCAP4 +XI0<3> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI0<2> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI0<1> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI0<0> VDD VSS / RSC_IHPSG13_FILLCAP8 +XADDR_COL_DRV<1> ADDR_COL_I<1> ADDR_COL_O<1> VDD VSS / ++ RSC_IHPSG13_CBUFX16 +XADDR_COL_DRV<0> ADDR_COL_I<0> ADDR_COL_O<0> VDD VSS / ++ RSC_IHPSG13_CBUFX16 +XADDR_DEC_DRV<7> ADDR_DEC_I<7> ADDR_DEC_O<7> VDD VSS / ++ RSC_IHPSG13_CBUFX16 +XADDR_DEC_DRV<6> ADDR_DEC_I<6> ADDR_DEC_O<6> VDD VSS / ++ RSC_IHPSG13_CBUFX16 +XADDR_DEC_DRV<5> ADDR_DEC_I<5> ADDR_DEC_O<5> VDD VSS / ++ RSC_IHPSG13_CBUFX16 +XADDR_DEC_DRV<4> ADDR_DEC_I<4> ADDR_DEC_O<4> VDD VSS / ++ RSC_IHPSG13_CBUFX16 +XADDR_DEC_DRV<3> ADDR_DEC_I<3> ADDR_DEC_O<3> VDD VSS / ++ RSC_IHPSG13_CBUFX16 +XADDR_DEC_DRV<2> ADDR_DEC_I<2> ADDR_DEC_O<2> VDD VSS / ++ RSC_IHPSG13_CBUFX16 +XADDR_DEC_DRV<1> ADDR_DEC_I<1> ADDR_DEC_O<1> VDD VSS / ++ RSC_IHPSG13_CBUFX16 +XADDR_DEC_DRV<0> ADDR_DEC_I<0> ADDR_DEC_O<0> VDD VSS / ++ RSC_IHPSG13_CBUFX16 +XDCLK_DRV DCLK_I DCLK_O VDD VSS / RSC_IHPSG13_CBUFX16 +XRCLK_DRV RCLK_I RCLK_O VDD VSS / RSC_IHPSG13_CBUFX16 +XWCLK_DRV WCLK_I WCLK_O VDD VSS / RSC_IHPSG13_CBUFX16 +.ENDS +.SUBCKT RSC_IHPSG13_WLDRVX16 A Z VDD VSS +MN1 Z net6 VSS VSS sg13_lv_nmos m=1 w=1.41u l=130.00n ng=2 nrd=0 nrs=0 +MN0 net6 A VSS VSS sg13_lv_nmos m=1 w=1.8u l=130.00n ng=2 nrd=0 nrs=0 +MP1 Z net6 VDD VDD sg13_lv_pmos m=1 w=12.96u l=130.00n ng=8 nrd=0 nrs=0 +MP0 net6 A VDD VDD sg13_lv_pmos m=1 w=900.0n l=130.00n ng=1 nrd=0 nrs=0 +.ENDS +.SUBCKT RM_IHPSG13_256x16_c2_1P_WLDRV16X16 A<15> A<14> A<13> A<12> A<11> A<10> A<9> A<8> ++ A<7> A<6> A<5> A<4> A<3> A<2> A<1> A<0> Z<15> Z<14> Z<13> Z<12> Z<11> Z<10> ++ Z<9> Z<8> Z<7> Z<6> Z<5> Z<4> Z<3> Z<2> Z<1> Z<0> VDD VSS +XBUF<15> A<15> Z<15> VDD VSS / RSC_IHPSG13_WLDRVX16 +XBUF<14> A<14> Z<14> VDD VSS / RSC_IHPSG13_WLDRVX16 +XBUF<13> A<13> Z<13> VDD VSS / RSC_IHPSG13_WLDRVX16 +XBUF<12> A<12> Z<12> VDD VSS / RSC_IHPSG13_WLDRVX16 +XBUF<11> A<11> Z<11> VDD VSS / RSC_IHPSG13_WLDRVX16 +XBUF<10> A<10> Z<10> VDD VSS / RSC_IHPSG13_WLDRVX16 +XBUF<9> A<9> Z<9> VDD VSS / RSC_IHPSG13_WLDRVX16 +XBUF<8> A<8> Z<8> VDD VSS / RSC_IHPSG13_WLDRVX16 +XBUF<7> A<7> Z<7> VDD VSS / RSC_IHPSG13_WLDRVX16 +XBUF<6> A<6> Z<6> VDD VSS / RSC_IHPSG13_WLDRVX16 +XBUF<5> A<5> Z<5> VDD VSS / RSC_IHPSG13_WLDRVX16 +XBUF<4> A<4> Z<4> VDD VSS / RSC_IHPSG13_WLDRVX16 +XBUF<3> A<3> Z<3> VDD VSS / RSC_IHPSG13_WLDRVX16 +XBUF<2> A<2> Z<2> VDD VSS / RSC_IHPSG13_WLDRVX16 +XBUF<1> A<1> Z<1> VDD VSS / RSC_IHPSG13_WLDRVX16 +XBUF<0> A<0> Z<0> VDD VSS / RSC_IHPSG13_WLDRVX16 +.ENDS + + +.SUBCKT RM_IHPSG13_256x16_c2_2P_COLDRV13X4 ADDR_COL_I<1> ADDR_COL_I<0> ADDR_COL_O<1> ++ ADDR_COL_O<0> ADDR_DEC_I<7> ADDR_DEC_I<6> ADDR_DEC_I<5> ADDR_DEC_I<4> ++ ADDR_DEC_I<3> ADDR_DEC_I<2> ADDR_DEC_I<1> ADDR_DEC_I<0> ADDR_DEC_O<7> ++ ADDR_DEC_O<6> ADDR_DEC_O<5> ADDR_DEC_O<4> ADDR_DEC_O<3> ADDR_DEC_O<2> ++ ADDR_DEC_O<1> ADDR_DEC_O<0> DCLK_I DCLK_O RCLK_I RCLK_O WCLK_I WCLK_O ++ VDD VSS +XWCLK_DRV WCLK_I WCLK_O VDD VSS / RSC_IHPSG13_CBUFX4 +XRCLK_DRV RCLK_I RCLK_O VDD VSS / RSC_IHPSG13_CBUFX4 +XDCLK_DRV DCLK_I DCLK_O VDD VSS / RSC_IHPSG13_CBUFX4 +XADDR_COL_DRV<1> ADDR_COL_I<1> ADDR_COL_O<1> VDD VSS / ++ RSC_IHPSG13_CBUFX4 +XADDR_COL_DRV<0> ADDR_COL_I<0> ADDR_COL_O<0> VDD VSS / ++ RSC_IHPSG13_CBUFX4 +XADDR_DEC_DRV<7> ADDR_DEC_I<7> ADDR_DEC_O<7> VDD VSS / ++ RSC_IHPSG13_CBUFX4 +XADDR_DEC_DRV<6> ADDR_DEC_I<6> ADDR_DEC_O<6> VDD VSS / ++ RSC_IHPSG13_CBUFX4 +XADDR_DEC_DRV<5> ADDR_DEC_I<5> ADDR_DEC_O<5> VDD VSS / ++ RSC_IHPSG13_CBUFX4 +XADDR_DEC_DRV<4> ADDR_DEC_I<4> ADDR_DEC_O<4> VDD VSS / ++ RSC_IHPSG13_CBUFX4 +XADDR_DEC_DRV<3> ADDR_DEC_I<3> ADDR_DEC_O<3> VDD VSS / ++ RSC_IHPSG13_CBUFX4 +XADDR_DEC_DRV<2> ADDR_DEC_I<2> ADDR_DEC_O<2> VDD VSS / ++ RSC_IHPSG13_CBUFX4 +XADDR_DEC_DRV<1> ADDR_DEC_I<1> ADDR_DEC_O<1> VDD VSS / ++ RSC_IHPSG13_CBUFX4 +XADDR_DEC_DRV<0> ADDR_DEC_I<0> ADDR_DEC_O<0> VDD VSS / ++ RSC_IHPSG13_CBUFX4 +XI0<6> VDD VSS / RSC_IHPSG13_FILLCAP4 +XI0<5> VDD VSS / RSC_IHPSG13_FILLCAP4 +XI0<4> VDD VSS / RSC_IHPSG13_FILLCAP4 +XI0<3> VDD VSS / RSC_IHPSG13_FILLCAP4 +XI0<2> VDD VSS / RSC_IHPSG13_FILLCAP4 +XI0<1> VDD VSS / RSC_IHPSG13_FILLCAP4 +XI1 VDD VSS / RSC_IHPSG13_FILLCAP8 +.ENDS +.SUBCKT RM_IHPSG13_256x16_c2_2P_WLDRV16X4 A<15> A<14> A<13> A<12> A<11> A<10> A<9> A<8> ++ A<7> A<6> A<5> A<4> A<3> A<2> A<1> A<0> Z<15> Z<14> Z<13> Z<12> Z<11> Z<10> ++ Z<9> Z<8> Z<7> Z<6> Z<5> Z<4> Z<3> Z<2> Z<1> Z<0> VDD VSS +XBUF<15> A<15> Z<15> VDD VSS / RSC_IHPSG13_WLDRVX4 +XBUF<14> A<14> Z<14> VDD VSS / RSC_IHPSG13_WLDRVX4 +XBUF<13> A<13> Z<13> VDD VSS / RSC_IHPSG13_WLDRVX4 +XBUF<12> A<12> Z<12> VDD VSS / RSC_IHPSG13_WLDRVX4 +XBUF<11> A<11> Z<11> VDD VSS / RSC_IHPSG13_WLDRVX4 +XBUF<10> A<10> Z<10> VDD VSS / RSC_IHPSG13_WLDRVX4 +XBUF<9> A<9> Z<9> VDD VSS / RSC_IHPSG13_WLDRVX4 +XBUF<8> A<8> Z<8> VDD VSS / RSC_IHPSG13_WLDRVX4 +XBUF<7> A<7> Z<7> VDD VSS / RSC_IHPSG13_WLDRVX4 +XBUF<6> A<6> Z<6> VDD VSS / RSC_IHPSG13_WLDRVX4 +XBUF<5> A<5> Z<5> VDD VSS / RSC_IHPSG13_WLDRVX4 +XBUF<4> A<4> Z<4> VDD VSS / RSC_IHPSG13_WLDRVX4 +XBUF<3> A<3> Z<3> VDD VSS / RSC_IHPSG13_WLDRVX4 +XBUF<2> A<2> Z<2> VDD VSS / RSC_IHPSG13_WLDRVX4 +XBUF<1> A<1> Z<1> VDD VSS / RSC_IHPSG13_WLDRVX4 +XBUF<0> A<0> Z<0> VDD VSS / RSC_IHPSG13_WLDRVX4 +.ENDS +.SUBCKT RM_IHPSG13_256x16_c2_2P_ROWDEC8 ADDR_N_I<7> ADDR_N_I<6> ADDR_N_I<5> ADDR_N_I<4> ++ ADDR_N_I<3> ADDR_N_I<2> ADDR_N_I<1> ADDR_N_I<0> CS_I ECLK_I WL_O<255> ++ WL_O<254> WL_O<253> WL_O<252> WL_O<251> WL_O<250> WL_O<249> WL_O<248> ++ WL_O<247> WL_O<246> WL_O<245> WL_O<244> WL_O<243> WL_O<242> WL_O<241> ++ WL_O<240> WL_O<239> WL_O<238> WL_O<237> WL_O<236> WL_O<235> WL_O<234> ++ WL_O<233> WL_O<232> WL_O<231> WL_O<230> WL_O<229> WL_O<228> WL_O<227> ++ WL_O<226> WL_O<225> WL_O<224> WL_O<223> WL_O<222> WL_O<221> WL_O<220> ++ WL_O<219> WL_O<218> WL_O<217> WL_O<216> WL_O<215> WL_O<214> WL_O<213> ++ WL_O<212> WL_O<211> WL_O<210> WL_O<209> WL_O<208> WL_O<207> WL_O<206> ++ WL_O<205> WL_O<204> WL_O<203> WL_O<202> WL_O<201> WL_O<200> WL_O<199> ++ WL_O<198> WL_O<197> WL_O<196> WL_O<195> WL_O<194> WL_O<193> WL_O<192> ++ WL_O<191> WL_O<190> WL_O<189> WL_O<188> WL_O<187> WL_O<186> WL_O<185> ++ WL_O<184> WL_O<183> WL_O<182> WL_O<181> WL_O<180> WL_O<179> WL_O<178> ++ WL_O<177> WL_O<176> WL_O<175> WL_O<174> WL_O<173> WL_O<172> WL_O<171> ++ WL_O<170> WL_O<169> WL_O<168> WL_O<167> WL_O<166> WL_O<165> WL_O<164> ++ WL_O<163> WL_O<162> WL_O<161> WL_O<160> WL_O<159> WL_O<158> WL_O<157> ++ WL_O<156> WL_O<155> WL_O<154> WL_O<153> WL_O<152> WL_O<151> WL_O<150> ++ WL_O<149> WL_O<148> WL_O<147> WL_O<146> WL_O<145> WL_O<144> WL_O<143> ++ WL_O<142> WL_O<141> WL_O<140> WL_O<139> WL_O<138> WL_O<137> WL_O<136> ++ WL_O<135> WL_O<134> WL_O<133> WL_O<132> WL_O<131> WL_O<130> WL_O<129> ++ WL_O<128> WL_O<127> WL_O<126> WL_O<125> WL_O<124> WL_O<123> WL_O<122> ++ WL_O<121> WL_O<120> WL_O<119> WL_O<118> WL_O<117> WL_O<116> WL_O<115> ++ WL_O<114> WL_O<113> WL_O<112> WL_O<111> WL_O<110> WL_O<109> WL_O<108> ++ WL_O<107> WL_O<106> WL_O<105> WL_O<104> WL_O<103> WL_O<102> WL_O<101> ++ WL_O<100> WL_O<99> WL_O<98> WL_O<97> WL_O<96> WL_O<95> WL_O<94> WL_O<93> ++ WL_O<92> WL_O<91> WL_O<90> WL_O<89> WL_O<88> WL_O<87> WL_O<86> WL_O<85> ++ WL_O<84> WL_O<83> WL_O<82> WL_O<81> WL_O<80> WL_O<79> WL_O<78> WL_O<77> ++ WL_O<76> WL_O<75> WL_O<74> WL_O<73> WL_O<72> WL_O<71> WL_O<70> WL_O<69> ++ WL_O<68> WL_O<67> WL_O<66> WL_O<65> WL_O<64> WL_O<63> WL_O<62> WL_O<61> ++ WL_O<60> WL_O<59> WL_O<58> WL_O<57> WL_O<56> WL_O<55> WL_O<54> WL_O<53> ++ WL_O<52> WL_O<51> WL_O<50> WL_O<49> WL_O<48> WL_O<47> WL_O<46> WL_O<45> ++ WL_O<44> WL_O<43> WL_O<42> WL_O<41> WL_O<40> WL_O<39> WL_O<38> WL_O<37> ++ WL_O<36> WL_O<35> WL_O<34> WL_O<33> WL_O<32> WL_O<31> WL_O<30> WL_O<29> ++ WL_O<28> WL_O<27> WL_O<26> WL_O<25> WL_O<24> WL_O<23> WL_O<22> WL_O<21> ++ WL_O<20> WL_O<19> WL_O<18> WL_O<17> WL_O<16> WL_O<15> WL_O<14> WL_O<13> ++ WL_O<12> WL_O<11> WL_O<10> WL_O<9> WL_O<8> WL_O<7> WL_O<6> WL_O<5> WL_O<4> ++ WL_O<3> WL_O<2> WL_O<1> WL_O<0> VDD VSS +XDEC11<4> ADDR_N_I<7> ADDR_N_I<6> CS_I CS04<3> VDD VSS / ++ RM_IHPSG13_256x16_c2_2P_DEC03 +XDEC11<3> ADDR_N_I<5> ADDR_N_I<4> CS04<3> CS00<15> VDD VSS / ++ RM_IHPSG13_256x16_c2_2P_DEC03 +XDEC11<2> ADDR_N_I<5> ADDR_N_I<4> CS04<2> CS00<11> VDD VSS / ++ RM_IHPSG13_256x16_c2_2P_DEC03 +XDEC11<1> ADDR_N_I<5> ADDR_N_I<4> CS04<1> CS00<7> VDD VSS / ++ RM_IHPSG13_256x16_c2_2P_DEC03 +XDEC11<0> ADDR_N_I<5> ADDR_N_I<4> CS04<0> CS00<3> VDD VSS / ++ RM_IHPSG13_256x16_c2_2P_DEC03 +XSEL<15> ADDR_N_I<3> ADDR_N_I<2> ADDR_N_I<1> ADDR_N_I<0> CS00<15> ECLK_H<15> ++ ECLK_H<16> ECLK_B<15> ECLK_B<16> WL_O<255> WL_O<254> WL_O<253> WL_O<252> ++ WL_O<251> WL_O<250> WL_O<249> WL_O<248> WL_O<247> WL_O<246> WL_O<245> ++ WL_O<244> WL_O<243> WL_O<242> WL_O<241> WL_O<240> VDD VSS / ++ RM_IHPSG13_256x16_c2_2P_DEC04 +XSEL<14> ADDR_N_I<3> ADDR_N_I<2> ADDR_N_I<1> ADDR_N_I<0> CS00<14> ECLK_H<14> ++ ECLK_H<15> ECLK_B<14> ECLK_B<15> WL_O<239> WL_O<238> WL_O<237> WL_O<236> ++ WL_O<235> WL_O<234> WL_O<233> WL_O<232> WL_O<231> WL_O<230> WL_O<229> ++ WL_O<228> WL_O<227> WL_O<226> WL_O<225> WL_O<224> VDD VSS / ++ RM_IHPSG13_256x16_c2_2P_DEC04 +XSEL<13> ADDR_N_I<3> ADDR_N_I<2> ADDR_N_I<1> ADDR_N_I<0> CS00<13> ECLK_H<13> ++ ECLK_H<14> ECLK_B<13> ECLK_B<14> WL_O<223> WL_O<222> WL_O<221> WL_O<220> ++ WL_O<219> WL_O<218> WL_O<217> WL_O<216> WL_O<215> WL_O<214> WL_O<213> ++ WL_O<212> WL_O<211> WL_O<210> WL_O<209> WL_O<208> VDD VSS / ++ RM_IHPSG13_256x16_c2_2P_DEC04 +XSEL<12> ADDR_N_I<3> ADDR_N_I<2> ADDR_N_I<1> ADDR_N_I<0> CS00<12> ECLK_H<12> ++ ECLK_H<13> ECLK_B<12> ECLK_B<13> WL_O<207> WL_O<206> WL_O<205> WL_O<204> ++ WL_O<203> WL_O<202> WL_O<201> WL_O<200> WL_O<199> WL_O<198> WL_O<197> ++ WL_O<196> WL_O<195> WL_O<194> WL_O<193> WL_O<192> VDD VSS / ++ RM_IHPSG13_256x16_c2_2P_DEC04 +XSEL<11> ADDR_N_I<3> ADDR_N_I<2> ADDR_N_I<1> ADDR_N_I<0> CS00<11> ECLK_H<11> ++ ECLK_H<12> ECLK_B<11> ECLK_B<12> WL_O<191> WL_O<190> WL_O<189> WL_O<188> ++ WL_O<187> WL_O<186> WL_O<185> WL_O<184> WL_O<183> WL_O<182> WL_O<181> ++ WL_O<180> WL_O<179> WL_O<178> WL_O<177> WL_O<176> VDD VSS / ++ RM_IHPSG13_256x16_c2_2P_DEC04 +XSEL<10> ADDR_N_I<3> ADDR_N_I<2> ADDR_N_I<1> ADDR_N_I<0> CS00<10> ECLK_H<10> ++ ECLK_H<11> ECLK_B<10> ECLK_B<11> WL_O<175> WL_O<174> WL_O<173> WL_O<172> ++ WL_O<171> WL_O<170> WL_O<169> WL_O<168> WL_O<167> WL_O<166> WL_O<165> ++ WL_O<164> WL_O<163> WL_O<162> WL_O<161> WL_O<160> VDD VSS / ++ RM_IHPSG13_256x16_c2_2P_DEC04 +XSEL<9> ADDR_N_I<3> ADDR_N_I<2> ADDR_N_I<1> ADDR_N_I<0> CS00<9> ECLK_H<9> ++ ECLK_H<10> ECLK_B<9> ECLK_B<10> WL_O<159> WL_O<158> WL_O<157> WL_O<156> ++ WL_O<155> WL_O<154> WL_O<153> WL_O<152> WL_O<151> WL_O<150> WL_O<149> ++ WL_O<148> WL_O<147> WL_O<146> WL_O<145> WL_O<144> VDD VSS / ++ RM_IHPSG13_256x16_c2_2P_DEC04 +XSEL<8> ADDR_N_I<3> ADDR_N_I<2> ADDR_N_I<1> ADDR_N_I<0> CS00<8> ECLK_H<8> ++ ECLK_H<9> ECLK_B<8> ECLK_B<9> WL_O<143> WL_O<142> WL_O<141> WL_O<140> ++ WL_O<139> WL_O<138> WL_O<137> WL_O<136> WL_O<135> WL_O<134> WL_O<133> ++ WL_O<132> WL_O<131> WL_O<130> WL_O<129> WL_O<128> VDD VSS / ++ RM_IHPSG13_256x16_c2_2P_DEC04 +XSEL<7> ADDR_N_I<3> ADDR_N_I<2> ADDR_N_I<1> ADDR_N_I<0> CS00<7> ECLK_H<7> ++ ECLK_H<8> ECLK_B<7> ECLK_B<8> WL_O<127> WL_O<126> WL_O<125> WL_O<124> ++ WL_O<123> WL_O<122> WL_O<121> WL_O<120> WL_O<119> WL_O<118> WL_O<117> ++ WL_O<116> WL_O<115> WL_O<114> WL_O<113> WL_O<112> VDD VSS / ++ RM_IHPSG13_256x16_c2_2P_DEC04 +XSEL<6> ADDR_N_I<3> ADDR_N_I<2> ADDR_N_I<1> ADDR_N_I<0> CS00<6> ECLK_H<6> ++ ECLK_H<7> ECLK_B<6> ECLK_B<7> WL_O<111> WL_O<110> WL_O<109> WL_O<108> ++ WL_O<107> WL_O<106> WL_O<105> WL_O<104> WL_O<103> WL_O<102> WL_O<101> ++ WL_O<100> WL_O<99> WL_O<98> WL_O<97> WL_O<96> VDD VSS / ++ RM_IHPSG13_256x16_c2_2P_DEC04 +XSEL<5> ADDR_N_I<3> ADDR_N_I<2> ADDR_N_I<1> ADDR_N_I<0> CS00<5> ECLK_H<5> ++ ECLK_H<6> ECLK_B<5> ECLK_B<6> WL_O<95> WL_O<94> WL_O<93> WL_O<92> WL_O<91> ++ WL_O<90> WL_O<89> WL_O<88> WL_O<87> WL_O<86> WL_O<85> WL_O<84> WL_O<83> ++ WL_O<82> WL_O<81> WL_O<80> VDD VSS / RM_IHPSG13_256x16_c2_2P_DEC04 +XSEL<4> ADDR_N_I<3> ADDR_N_I<2> ADDR_N_I<1> ADDR_N_I<0> CS00<4> ECLK_H<4> ++ ECLK_H<5> ECLK_B<4> ECLK_B<5> WL_O<79> WL_O<78> WL_O<77> WL_O<76> WL_O<75> ++ WL_O<74> WL_O<73> WL_O<72> WL_O<71> WL_O<70> WL_O<69> WL_O<68> WL_O<67> ++ WL_O<66> WL_O<65> WL_O<64> VDD VSS / RM_IHPSG13_256x16_c2_2P_DEC04 +XSEL<3> ADDR_N_I<3> ADDR_N_I<2> ADDR_N_I<1> ADDR_N_I<0> CS00<3> ECLK_H<3> ++ ECLK_H<4> ECLK_B<3> ECLK_B<4> WL_O<63> WL_O<62> WL_O<61> WL_O<60> WL_O<59> ++ WL_O<58> WL_O<57> WL_O<56> WL_O<55> WL_O<54> WL_O<53> WL_O<52> WL_O<51> ++ WL_O<50> WL_O<49> WL_O<48> VDD VSS / RM_IHPSG13_256x16_c2_2P_DEC04 +XSEL<2> ADDR_N_I<3> ADDR_N_I<2> ADDR_N_I<1> ADDR_N_I<0> CS00<2> ECLK_H<2> ++ ECLK_H<3> ECLK_B<2> ECLK_B<3> WL_O<47> WL_O<46> WL_O<45> WL_O<44> WL_O<43> ++ WL_O<42> WL_O<41> WL_O<40> WL_O<39> WL_O<38> WL_O<37> WL_O<36> WL_O<35> ++ WL_O<34> WL_O<33> WL_O<32> VDD VSS / RM_IHPSG13_256x16_c2_2P_DEC04 +XSEL<1> ADDR_N_I<3> ADDR_N_I<2> ADDR_N_I<1> ADDR_N_I<0> CS00<1> ECLK_H<1> ++ ECLK_H<2> ECLK_B<1> ECLK_B<2> WL_O<31> WL_O<30> WL_O<29> WL_O<28> WL_O<27> ++ WL_O<26> WL_O<25> WL_O<24> WL_O<23> WL_O<22> WL_O<21> WL_O<20> WL_O<19> ++ WL_O<18> WL_O<17> WL_O<16> VDD VSS / RM_IHPSG13_256x16_c2_2P_DEC04 +XSEL<0> ADDR_N_I<3> ADDR_N_I<2> ADDR_N_I<1> ADDR_N_I<0> CS00<0> ECLK_I ++ ECLK_H<1> ECLK_B<0> ECLK_B<1> WL_O<15> WL_O<14> WL_O<13> WL_O<12> WL_O<11> ++ WL_O<10> WL_O<9> WL_O<8> WL_O<7> WL_O<6> WL_O<5> WL_O<4> WL_O<3> WL_O<2> ++ WL_O<1> WL_O<0> VDD VSS / RM_IHPSG13_256x16_c2_2P_DEC04 +XDEC10<4> ADDR_N_I<7> ADDR_N_I<6> CS_I CS04<2> VDD VSS / ++ RM_IHPSG13_256x16_c2_2P_DEC02 +XDEC10<3> ADDR_N_I<5> ADDR_N_I<4> CS04<3> CS00<14> VDD VSS / ++ RM_IHPSG13_256x16_c2_2P_DEC02 +XDEC10<2> ADDR_N_I<5> ADDR_N_I<4> CS04<2> CS00<10> VDD VSS / ++ RM_IHPSG13_256x16_c2_2P_DEC02 +XDEC10<1> ADDR_N_I<5> ADDR_N_I<4> CS04<1> CS00<6> VDD VSS / ++ RM_IHPSG13_256x16_c2_2P_DEC02 +XDEC10<0> ADDR_N_I<5> ADDR_N_I<4> CS04<0> CS00<2> VDD VSS / ++ RM_IHPSG13_256x16_c2_2P_DEC02 +XL2<132> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<131> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<130> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<129> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<128> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<127> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<126> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<125> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<124> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<123> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<122> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<121> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<120> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<119> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<118> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<117> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<116> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<115> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<114> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<113> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<112> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<111> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<110> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<109> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<108> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<107> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<106> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<105> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<104> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<103> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<102> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<101> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<100> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<99> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<98> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<97> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<96> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<95> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<94> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<93> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<92> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<91> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<90> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<89> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<88> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<87> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<86> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<85> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<84> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<83> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<82> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<81> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<80> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<79> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<78> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<77> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<76> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<75> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<74> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<73> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<72> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<71> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<70> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<69> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<68> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<67> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<66> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<65> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<64> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<63> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<62> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<61> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<60> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<59> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<58> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<57> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<56> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<55> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<54> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<53> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<52> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<51> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<50> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<49> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<48> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<47> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<46> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<45> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<44> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<43> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<42> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<41> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<40> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<39> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<38> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<37> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<36> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<35> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<34> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<33> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<32> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<31> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<30> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<29> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<28> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<27> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<26> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<25> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<24> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<23> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<22> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<21> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<20> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<19> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<18> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<17> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<16> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<15> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<14> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<13> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<12> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<11> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<10> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<9> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<8> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<7> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<6> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<5> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<4> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<3> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<2> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<1> VDD VSS / RSC_IHPSG13_FILLCAP8 +XDEC00<4> ADDR_N_I<7> ADDR_N_I<6> CS_I CS04<0> VDD VSS / ++ RM_IHPSG13_256x16_c2_2P_DEC00 +XDEC00<3> ADDR_N_I<5> ADDR_N_I<4> CS04<3> CS00<12> VDD VSS / ++ RM_IHPSG13_256x16_c2_2P_DEC00 +XDEC00<2> ADDR_N_I<5> ADDR_N_I<4> CS04<2> CS00<8> VDD VSS / ++ RM_IHPSG13_256x16_c2_2P_DEC00 +XDEC00<1> ADDR_N_I<5> ADDR_N_I<4> CS04<1> CS00<4> VDD VSS / ++ RM_IHPSG13_256x16_c2_2P_DEC00 +XDEC00<0> ADDR_N_I<5> ADDR_N_I<4> CS04<0> CS00<0> VDD VSS / ++ RM_IHPSG13_256x16_c2_2P_DEC00 +XDEC01<4> ADDR_N_I<7> ADDR_N_I<6> CS_I CS04<1> VDD VSS / ++ RM_IHPSG13_256x16_c2_2P_DEC01 +XDEC01<3> ADDR_N_I<5> ADDR_N_I<4> CS04<3> CS00<13> VDD VSS / ++ RM_IHPSG13_256x16_c2_2P_DEC01 +XDEC01<2> ADDR_N_I<5> ADDR_N_I<4> CS04<2> CS00<9> VDD VSS / ++ RM_IHPSG13_256x16_c2_2P_DEC01 +XDEC01<1> ADDR_N_I<5> ADDR_N_I<4> CS04<1> CS00<5> VDD VSS / ++ RM_IHPSG13_256x16_c2_2P_DEC01 +XDEC01<0> ADDR_N_I<5> ADDR_N_I<4> CS04<0> CS00<1> VDD VSS / ++ RM_IHPSG13_256x16_c2_2P_DEC01 +.ENDS +.SUBCKT RM_IHPSG13_256x16_c2_2P_ROWREG8 ACLK_N_I ADDR_I<7> ADDR_I<6> ADDR_I<5> ADDR_I<4> ++ ADDR_I<3> ADDR_I<2> ADDR_I<1> ADDR_I<0> ADDR_N_O<7> ADDR_N_O<6> ADDR_N_O<5> ++ ADDR_N_O<4> ADDR_N_O<3> ADDR_N_O<2> ADDR_N_O<1> ADDR_N_O<0> BIST_ADDR_I<7> ++ BIST_ADDR_I<6> BIST_ADDR_I<5> BIST_ADDR_I<4> BIST_ADDR_I<3> BIST_ADDR_I<2> ++ BIST_ADDR_I<1> BIST_ADDR_I<0> BIST_EN_I VDD VSS +XINV<7> q_int<7> qn_int<7> VDD VSS / RSC_IHPSG13_CINVX2 +XINV<6> q_int<6> qn_int<6> VDD VSS / RSC_IHPSG13_CINVX2 +XINV<5> q_int<5> qn_int<5> VDD VSS / RSC_IHPSG13_CINVX2 +XINV<4> q_int<4> qn_int<4> VDD VSS / RSC_IHPSG13_CINVX2 +XINV<3> q_int<3> qn_int<3> VDD VSS / RSC_IHPSG13_CINVX2 +XINV<2> q_int<2> qn_int<2> VDD VSS / RSC_IHPSG13_CINVX2 +XINV<1> q_int<1> qn_int<1> VDD VSS / RSC_IHPSG13_CINVX2 +XINV<0> q_int<0> qn_int<0> VDD VSS / RSC_IHPSG13_CINVX2 +XDRV<7> qn_int<7> ADDR_N_O<7> VDD VSS / RSC_IHPSG13_CINVX8 +XDRV<6> qn_int<6> ADDR_N_O<6> VDD VSS / RSC_IHPSG13_CINVX8 +XDRV<5> qn_int<5> ADDR_N_O<5> VDD VSS / RSC_IHPSG13_CINVX8 +XDRV<4> qn_int<4> ADDR_N_O<4> VDD VSS / RSC_IHPSG13_CINVX8 +XDRV<3> qn_int<3> ADDR_N_O<3> VDD VSS / RSC_IHPSG13_CINVX8 +XDRV<2> qn_int<2> ADDR_N_O<2> VDD VSS / RSC_IHPSG13_CINVX8 +XDRV<1> qn_int<1> ADDR_N_O<1> VDD VSS / RSC_IHPSG13_CINVX8 +XDRV<0> qn_int<0> ADDR_N_O<0> VDD VSS / RSC_IHPSG13_CINVX8 +XDFF<7> BIST_EN_I BIST_ADDR_I<7> ACLK_N_I ADDR_I<7> q_int<7> net2<0> VDD ++ VSS / RSC_IHPSG13_DFNQMX2IX1 +XDFF<6> BIST_EN_I BIST_ADDR_I<6> ACLK_N_I ADDR_I<6> q_int<6> net2<1> VDD ++ VSS / RSC_IHPSG13_DFNQMX2IX1 +XDFF<5> BIST_EN_I BIST_ADDR_I<5> ACLK_N_I ADDR_I<5> q_int<5> net2<2> VDD ++ VSS / RSC_IHPSG13_DFNQMX2IX1 +XDFF<4> BIST_EN_I BIST_ADDR_I<4> ACLK_N_I ADDR_I<4> q_int<4> net2<3> VDD ++ VSS / RSC_IHPSG13_DFNQMX2IX1 +XDFF<3> BIST_EN_I BIST_ADDR_I<3> ACLK_N_I ADDR_I<3> q_int<3> net2<4> VDD ++ VSS / RSC_IHPSG13_DFNQMX2IX1 +XDFF<2> BIST_EN_I BIST_ADDR_I<2> ACLK_N_I ADDR_I<2> q_int<2> net2<5> VDD ++ VSS / RSC_IHPSG13_DFNQMX2IX1 +XDFF<1> BIST_EN_I BIST_ADDR_I<1> ACLK_N_I ADDR_I<1> q_int<1> net2<6> VDD ++ VSS / RSC_IHPSG13_DFNQMX2IX1 +XDFF<0> BIST_EN_I BIST_ADDR_I<0> ACLK_N_I ADDR_I<0> q_int<0> net2<7> VDD ++ VSS / RSC_IHPSG13_DFNQMX2IX1 +XI11<4> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI11<3> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI11<2> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI11<1> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI10 VDD VSS / RSC_IHPSG13_FILLCAP4 +.ENDS +.SUBCKT RM_IHPSG13_256x16_c2_2P_COLDEC4 ACLK_N ADDR<3> ADDR<2> ADDR<1> ADDR<0> ++ ADDR_COL<1> ADDR_COL<0> ADDR_DEC<7> ADDR_DEC<6> ADDR_DEC<5> ADDR_DEC<4> ++ ADDR_DEC<3> ADDR_DEC<2> ADDR_DEC<1> ADDR_DEC<0> BIST_ADDR<3> BIST_ADDR<2> ++ BIST_ADDR<1> BIST_ADDR<0> BIST_EN_I VDD VSS +XI1<7> PADR<0> PADR<1> PADR<2> addr_n<7> VDD VSS / RSC_IHPSG13_NAND3X2 +XI1<6> NADR<0> PADR<1> PADR<2> addr_n<6> VDD VSS / RSC_IHPSG13_NAND3X2 +XI1<5> PADR<0> NADR<1> PADR<2> addr_n<5> VDD VSS / RSC_IHPSG13_NAND3X2 +XI1<4> NADR<0> NADR<1> PADR<2> addr_n<4> VDD VSS / RSC_IHPSG13_NAND3X2 +XI1<3> PADR<0> PADR<1> NADR<2> addr_n<3> VDD VSS / RSC_IHPSG13_NAND3X2 +XI1<2> NADR<0> PADR<1> NADR<2> addr_n<2> VDD VSS / RSC_IHPSG13_NAND3X2 +XI1<1> PADR<0> NADR<1> NADR<2> addr_n<1> VDD VSS / RSC_IHPSG13_NAND3X2 +XI1<0> NADR<0> NADR<1> NADR<2> addr_n<0> VDD VSS / RSC_IHPSG13_NAND3X2 +XDFF<3> BIST_EN_I BIST_ADDR<3> ACLK_N ADDR<3> addr_int net12<0> VDD ++ VSS / RSC_IHPSG13_DFNQMX2IX1 +XDFF<2> BIST_EN_I BIST_ADDR<2> ACLK_N ADDR<2> padr_int<2> net12<1> VDD ++ VSS / RSC_IHPSG13_DFNQMX2IX1 +XDFF<1> BIST_EN_I BIST_ADDR<1> ACLK_N ADDR<1> padr_int<1> net12<2> VDD ++ VSS / RSC_IHPSG13_DFNQMX2IX1 +XDFF<0> BIST_EN_I BIST_ADDR<0> ACLK_N ADDR<0> padr_int<0> net12<3> VDD ++ VSS / RSC_IHPSG13_DFNQMX2IX1 +XI17<4> VDD VSS / RSC_IHPSG13_FILLCAP4 +XI17<3> VDD VSS / RSC_IHPSG13_FILLCAP4 +XI17<2> VDD VSS / RSC_IHPSG13_FILLCAP4 +XI17<1> VDD VSS / RSC_IHPSG13_FILLCAP4 +XI13<2> NADR<2> PADR<2> VDD VSS / RSC_IHPSG13_INVX2 +XI13<1> NADR<1> PADR<1> VDD VSS / RSC_IHPSG13_INVX2 +XI13<0> NADR<0> PADR<0> VDD VSS / RSC_IHPSG13_INVX2 +XI2<7> addr_n<7> ADDR_DEC<7> VDD VSS / RSC_IHPSG13_INVX2 +XI2<6> addr_n<6> ADDR_DEC<6> VDD VSS / RSC_IHPSG13_INVX2 +XI2<5> addr_n<5> ADDR_DEC<5> VDD VSS / RSC_IHPSG13_INVX2 +XI2<4> addr_n<4> ADDR_DEC<4> VDD VSS / RSC_IHPSG13_INVX2 +XI2<3> addr_n<3> ADDR_DEC<3> VDD VSS / RSC_IHPSG13_INVX2 +XI2<2> addr_n<2> ADDR_DEC<2> VDD VSS / RSC_IHPSG13_INVX2 +XI2<1> addr_n<1> ADDR_DEC<1> VDD VSS / RSC_IHPSG13_INVX2 +XI2<0> addr_n<0> ADDR_DEC<0> VDD VSS / RSC_IHPSG13_INVX2 +XI3<2> padr_int<2> NADR<2> VDD VSS / RSC_IHPSG13_INVX2 +XI3<1> padr_int<1> NADR<1> VDD VSS / RSC_IHPSG13_INVX2 +XI3<0> padr_int<0> NADR<0> VDD VSS / RSC_IHPSG13_INVX2 +XI14 addr_int ADDR_COL<0> VDD VSS / RSC_IHPSG13_CBUFX2 +XI16<8> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI16<7> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI16<6> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI16<5> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI16<4> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI16<3> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI16<2> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI16<1> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI15 ADDR_COL<1> VDD VSS / RSC_IHPSG13_TIEL +.ENDS +.SUBCKT RM_IHPSG13_256x16_c2_2P_COLCTRL4 A_ADDR_COL A_ADDR_DEC<7> A_ADDR_DEC<6> ++ A_ADDR_DEC<5> A_ADDR_DEC<4> A_ADDR_DEC<3> A_ADDR_DEC<2> A_ADDR_DEC<1> ++ A_ADDR_DEC<0> A_BIST_BM_I A_BIST_DW_I A_BIST_EN_I A_BLC<15> A_BLC<14> ++ A_BLC<13> A_BLC<12> A_BLC<11> A_BLC<10> A_BLC<9> A_BLC<8> A_BLC<7> A_BLC<6> ++ A_BLC<5> A_BLC<4> A_BLC<3> A_BLC<2> A_BLC<1> A_BLC<0> A_BLT<15> A_BLT<14> ++ A_BLT<13> A_BLT<12> A_BLT<11> A_BLT<10> A_BLT<9> A_BLT<8> A_BLT<7> A_BLT<6> ++ A_BLT<5> A_BLT<4> A_BLT<3> A_BLT<2> A_BLT<1> A_BLT<0> A_BM_I A_DCLK_B_L ++ A_DCLK_B_R A_DCLK_L A_DCLK_R A_DR_O A_DW_I A_RCLK_B_L A_RCLK_B_R A_RCLK_L ++ A_RCLK_R A_TIEH_O A_WCLK_B_L A_WCLK_B_R A_WCLK_L A_WCLK_R B_ADDR_COL ++ B_ADDR_DEC<7> B_ADDR_DEC<6> B_ADDR_DEC<5> B_ADDR_DEC<4> B_ADDR_DEC<3> ++ B_ADDR_DEC<2> B_ADDR_DEC<1> B_ADDR_DEC<0> B_BIST_BM_I B_BIST_DW_I ++ B_BIST_EN_I B_BLC<15> B_BLC<14> B_BLC<13> B_BLC<12> B_BLC<11> B_BLC<10> ++ B_BLC<9> B_BLC<8> B_BLC<7> B_BLC<6> B_BLC<5> B_BLC<4> B_BLC<3> B_BLC<2> ++ B_BLC<1> B_BLC<0> B_BLT<15> B_BLT<14> B_BLT<13> B_BLT<12> B_BLT<11> ++ B_BLT<10> B_BLT<9> B_BLT<8> B_BLT<7> B_BLT<6> B_BLT<5> B_BLT<4> B_BLT<3> ++ B_BLT<2> B_BLT<1> B_BLT<0> B_BM_I B_DCLK_B_L B_DCLK_B_R B_DCLK_L B_DCLK_R ++ B_DR_O B_DW_I B_RCLK_B_L B_RCLK_B_R B_RCLK_L B_RCLK_R B_TIEH_O B_WCLK_B_L ++ B_WCLK_B_R B_WCLK_L B_WCLK_R VDD VSS +XB_I80 B_RCLK_B_L B_WCLK_B_L net041 VDD VSS / RSC_IHPSG13_AND2X2 +XA_I80 A_RCLK_B_L A_WCLK_B_L net21 VDD VSS / RSC_IHPSG13_AND2X2 +XB_I76 B_DI_N B_DO_WRITE_P B_WR_ZERO VDD VSS / RSC_IHPSG13_AND2X4 +XB_I75 B_DI_R B_DO_WRITE_P B_WR_ONE VDD VSS / RSC_IHPSG13_AND2X4 +XA_I76 A_DI_N A_DO_WRITE_P A_WR_ZERO VDD VSS / RSC_IHPSG13_AND2X4 +XA_I75 A_DI_R A_DO_WRITE_P A_WR_ONE VDD VSS / RSC_IHPSG13_AND2X4 +XI_FILL4<26> VDD VSS / RSC_IHPSG13_FILLCAP4 +XI_FILL4<25> VDD VSS / RSC_IHPSG13_FILLCAP4 +XI_FILL4<24> VDD VSS / RSC_IHPSG13_FILLCAP4 +XI_FILL4<23> VDD VSS / RSC_IHPSG13_FILLCAP4 +XI_FILL4<22> VDD VSS / RSC_IHPSG13_FILLCAP4 +XI_FILL4<21> VDD VSS / RSC_IHPSG13_FILLCAP4 +XI_FILL4<20> VDD VSS / RSC_IHPSG13_FILLCAP4 +XI_FILL4<19> VDD VSS / RSC_IHPSG13_FILLCAP4 +XI_FILL4<18> VDD VSS / RSC_IHPSG13_FILLCAP4 +XI_FILL4<17> VDD VSS / RSC_IHPSG13_FILLCAP4 +XI_FILL4<16> VDD VSS / RSC_IHPSG13_FILLCAP4 +XI_FILL4<15> VDD VSS / RSC_IHPSG13_FILLCAP4 +XI_FILL4<14> VDD VSS / RSC_IHPSG13_FILLCAP4 +XI_FILL4<13> VDD VSS / RSC_IHPSG13_FILLCAP4 +XI_FILL4<12> VDD VSS / RSC_IHPSG13_FILLCAP4 +XI_FILL4<11> VDD VSS / RSC_IHPSG13_FILLCAP4 +XI_FILL4<10> VDD VSS / RSC_IHPSG13_FILLCAP4 +XI_FILL4<9> VDD VSS / RSC_IHPSG13_FILLCAP4 +XI_FILL4<8> VDD VSS / RSC_IHPSG13_FILLCAP4 +XI_FILL4<7> VDD VSS / RSC_IHPSG13_FILLCAP4 +XI_FILL4<6> VDD VSS / RSC_IHPSG13_FILLCAP4 +XI_FILL4<5> VDD VSS / RSC_IHPSG13_FILLCAP4 +XI_FILL4<4> VDD VSS / RSC_IHPSG13_FILLCAP4 +XI_FILL4<3> VDD VSS / RSC_IHPSG13_FILLCAP4 +XI_FILL4<2> VDD VSS / RSC_IHPSG13_FILLCAP4 +XI_FILL4<1> VDD VSS / RSC_IHPSG13_FILLCAP4 +XB_I69 B_DCLK_L B_DCLK_B_L VDD VSS / RSC_IHPSG13_CINVX4 +XB_I50 B_WCLK_L B_WCLK_B_L VDD VSS / RSC_IHPSG13_CINVX4 +XB_EBUF B_RCLK_L B_RCLK_B_L VDD VSS / RSC_IHPSG13_CINVX4 +XB_INV<1> B_N0 B_P0 VDD VSS / RSC_IHPSG13_CINVX4 +XB_INV<0> B_ADDR_COL B_N0 VDD VSS / RSC_IHPSG13_CINVX4 +XA_I69 A_DCLK_L A_DCLK_B_L VDD VSS / RSC_IHPSG13_CINVX4 +XA_I50 A_WCLK_L A_WCLK_B_L VDD VSS / RSC_IHPSG13_CINVX4 +XA_EBUF A_RCLK_L A_RCLK_B_L VDD VSS / RSC_IHPSG13_CINVX4 +XA_INV<1> A_N0 A_P0 VDD VSS / RSC_IHPSG13_CINVX4 +XA_INV<0> A_ADDR_COL A_N0 VDD VSS / RSC_IHPSG13_CINVX4 +XB_I81<1> net041 B_PRE_N VDD VSS / RSC_IHPSG13_CINVX4_WN +XB_I81<0> net041 B_PRE_N VDD VSS / RSC_IHPSG13_CINVX4_WN +XA_I81<1> net21 A_PRE_N VDD VSS / RSC_IHPSG13_CINVX4_WN +XA_I81<0> net21 A_PRE_N VDD VSS / RSC_IHPSG13_CINVX4_WN +XA_R2 A_RCLK_L A_RCLK_R / RSC_IHPSG13_MET3RES +XA_I87 A_WCLK_L A_WCLK_R / RSC_IHPSG13_MET3RES +XA_I88 A_DCLK_L A_DCLK_R / RSC_IHPSG13_MET3RES +XA_I89 A_DCLK_B_L A_DCLK_B_R / RSC_IHPSG13_MET3RES +XA_I90 A_WCLK_B_L A_WCLK_B_R / RSC_IHPSG13_MET3RES +XA_I91 A_RCLK_B_L A_RCLK_B_R / RSC_IHPSG13_MET3RES +XB_R2 B_RCLK_L B_RCLK_R / RSC_IHPSG13_MET3RES +XB_I87 B_WCLK_L B_WCLK_R / RSC_IHPSG13_MET3RES +XB_I88 B_DCLK_L B_DCLK_R / RSC_IHPSG13_MET3RES +XB_I89 B_DCLK_B_L B_DCLK_B_R / RSC_IHPSG13_MET3RES +XB_I90 B_WCLK_B_L B_WCLK_B_R / RSC_IHPSG13_MET3RES +XB_I91 B_RCLK_B_L B_RCLK_B_R / RSC_IHPSG13_MET3RES +XA_ISENSE A_SAE A_BLC_SEL A_BLT_SEL net19 net20 VDD VSS / ++ RSC_IHPSG13_DFPQD_MSAFFX2 +XB_ISENSE B_SAE B_BLC_SEL B_BLT_SEL net037 net038 VDD VSS / ++ RSC_IHPSG13_DFPQD_MSAFFX2 +XAB_BLMUX<3> A_BLC<15> A_BLC<14> A_BLC<13> A_BLC<12> A_BLC_SEL A_BLT<15> ++ A_BLT<14> A_BLT<13> A_BLT<12> A_BLT_SEL A_PRE_N A_SEL_P<15> A_SEL_P<14> ++ A_SEL_P<13> A_SEL_P<12> A_WR_ONE A_WR_ZERO B_BLC<15> B_BLC<14> B_BLC<13> ++ B_BLC<12> B_BLC_SEL B_BLT<15> B_BLT<14> B_BLT<13> B_BLT<12> B_BLT_SEL ++ B_PRE_N B_SEL_P<15> B_SEL_P<14> B_SEL_P<13> B_SEL_P<12> B_WR_ONE B_WR_ZERO ++ VDD VSS / RM_IHPSG13_256x16_c2_2P_BLDRV +XAB_BLMUX<2> A_BLC<11> A_BLC<10> A_BLC<9> A_BLC<8> A_BLC_SEL A_BLT<11> ++ A_BLT<10> A_BLT<9> A_BLT<8> A_BLT_SEL A_PRE_N A_SEL_P<11> A_SEL_P<10> ++ A_SEL_P<9> A_SEL_P<8> A_WR_ONE A_WR_ZERO B_BLC<11> B_BLC<10> B_BLC<9> ++ B_BLC<8> B_BLC_SEL B_BLT<11> B_BLT<10> B_BLT<9> B_BLT<8> B_BLT_SEL B_PRE_N ++ B_SEL_P<11> B_SEL_P<10> B_SEL_P<9> B_SEL_P<8> B_WR_ONE B_WR_ZERO VDD ++ VSS / RM_IHPSG13_256x16_c2_2P_BLDRV +XAB_BLMUX<1> A_BLC<7> A_BLC<6> A_BLC<5> A_BLC<4> A_BLC_SEL A_BLT<7> A_BLT<6> ++ A_BLT<5> A_BLT<4> A_BLT_SEL A_PRE_N A_SEL_P<7> A_SEL_P<6> A_SEL_P<5> ++ A_SEL_P<4> A_WR_ONE A_WR_ZERO B_BLC<7> B_BLC<6> B_BLC<5> B_BLC<4> B_BLC_SEL ++ B_BLT<7> B_BLT<6> B_BLT<5> B_BLT<4> B_BLT_SEL B_PRE_N B_SEL_P<7> B_SEL_P<6> ++ B_SEL_P<5> B_SEL_P<4> B_WR_ONE B_WR_ZERO VDD VSS / ++ RM_IHPSG13_256x16_c2_2P_BLDRV +XAB_BLMUX<0> A_BLC<3> A_BLC<2> A_BLC<1> A_BLC<0> A_BLC_SEL A_BLT<3> A_BLT<2> ++ A_BLT<1> A_BLT<0> A_BLT_SEL A_PRE_N A_SEL_P<3> A_SEL_P<2> A_SEL_P<1> ++ A_SEL_P<0> A_WR_ONE A_WR_ZERO B_BLC<3> B_BLC<2> B_BLC<1> B_BLC<0> B_BLC_SEL ++ B_BLT<3> B_BLT<2> B_BLT<1> B_BLT<0> B_BLT_SEL B_PRE_N B_SEL_P<3> B_SEL_P<2> ++ B_SEL_P<1> B_SEL_P<0> B_WR_ONE B_WR_ZERO VDD VSS / ++ RM_IHPSG13_256x16_c2_2P_BLDRV +XA_I51 net19 A_DR_O VDD VSS / RSC_IHPSG13_INVX4 +XB_I51 net037 B_DR_O VDD VSS / RSC_IHPSG13_INVX4 +XA_I78 A_RCLK_B_L A_SAE VDD VSS / RSC_IHPSG13_CBUFX2 +XB_I78 B_RCLK_B_L B_SAE VDD VSS / RSC_IHPSG13_CBUFX2 +XA_DREG A_BIST_EN_I A_BIST_DW_I A_DCLK_B_L A_DW_I A_DI_R net22 VDD VSS ++ / RSC_IHPSG13_DFNQMX2IX1 +XB_DREG B_BIST_EN_I B_BIST_DW_I B_DCLK_B_L B_DW_I B_DI_R net046 VDD ++ VSS / RSC_IHPSG13_DFNQMX2IX1 +XB_BREG B_BIST_EN_I B_BIST_BM_I B_DCLK_B_L B_BM_I B_BM_R net045 VDD ++ VSS / RSC_IHPSG13_DFNQMX2IX1 +XA_BREG A_BIST_EN_I A_BIST_BM_I A_DCLK_B_L A_BM_I A_BM_R net24 VDD VSS ++ / RSC_IHPSG13_DFNQMX2IX1 +XA_DEC3INV<15> net23<0> A_SEL_P<15> VDD VSS / RSC_IHPSG13_INVX2 +XA_DEC3INV<14> net23<1> A_SEL_P<14> VDD VSS / RSC_IHPSG13_INVX2 +XA_DEC3INV<13> net23<2> A_SEL_P<13> VDD VSS / RSC_IHPSG13_INVX2 +XA_DEC3INV<12> net23<3> A_SEL_P<12> VDD VSS / RSC_IHPSG13_INVX2 +XA_DEC3INV<11> net23<4> A_SEL_P<11> VDD VSS / RSC_IHPSG13_INVX2 +XA_DEC3INV<10> net23<5> A_SEL_P<10> VDD VSS / RSC_IHPSG13_INVX2 +XA_DEC3INV<9> net23<6> A_SEL_P<9> VDD VSS / RSC_IHPSG13_INVX2 +XA_DEC3INV<8> net23<7> A_SEL_P<8> VDD VSS / RSC_IHPSG13_INVX2 +XA_DEC3INV<7> net23<8> A_SEL_P<7> VDD VSS / RSC_IHPSG13_INVX2 +XA_DEC3INV<6> net23<9> A_SEL_P<6> VDD VSS / RSC_IHPSG13_INVX2 +XA_DEC3INV<5> net23<10> A_SEL_P<5> VDD VSS / RSC_IHPSG13_INVX2 +XA_DEC3INV<4> net23<11> A_SEL_P<4> VDD VSS / RSC_IHPSG13_INVX2 +XA_DEC3INV<3> net23<12> A_SEL_P<3> VDD VSS / RSC_IHPSG13_INVX2 +XA_DEC3INV<2> net23<13> A_SEL_P<2> VDD VSS / RSC_IHPSG13_INVX2 +XA_DEC3INV<1> net23<14> A_SEL_P<1> VDD VSS / RSC_IHPSG13_INVX2 +XA_DEC3INV<0> net23<15> A_SEL_P<0> VDD VSS / RSC_IHPSG13_INVX2 +XA_I83 A_BM_R A_BM_N VDD VSS / RSC_IHPSG13_INVX2 +XA_I49 A_DI_R A_DI_N VDD VSS / RSC_IHPSG13_INVX2 +XB_DEC3INV<15> net044<0> B_SEL_P<15> VDD VSS / RSC_IHPSG13_INVX2 +XB_DEC3INV<14> net044<1> B_SEL_P<14> VDD VSS / RSC_IHPSG13_INVX2 +XB_DEC3INV<13> net044<2> B_SEL_P<13> VDD VSS / RSC_IHPSG13_INVX2 +XB_DEC3INV<12> net044<3> B_SEL_P<12> VDD VSS / RSC_IHPSG13_INVX2 +XB_DEC3INV<11> net044<4> B_SEL_P<11> VDD VSS / RSC_IHPSG13_INVX2 +XB_DEC3INV<10> net044<5> B_SEL_P<10> VDD VSS / RSC_IHPSG13_INVX2 +XB_DEC3INV<9> net044<6> B_SEL_P<9> VDD VSS / RSC_IHPSG13_INVX2 +XB_DEC3INV<8> net044<7> B_SEL_P<8> VDD VSS / RSC_IHPSG13_INVX2 +XB_DEC3INV<7> net044<8> B_SEL_P<7> VDD VSS / RSC_IHPSG13_INVX2 +XB_DEC3INV<6> net044<9> B_SEL_P<6> VDD VSS / RSC_IHPSG13_INVX2 +XB_DEC3INV<5> net044<10> B_SEL_P<5> VDD VSS / RSC_IHPSG13_INVX2 +XB_DEC3INV<4> net044<11> B_SEL_P<4> VDD VSS / RSC_IHPSG13_INVX2 +XB_DEC3INV<3> net044<12> B_SEL_P<3> VDD VSS / RSC_IHPSG13_INVX2 +XB_DEC3INV<2> net044<13> B_SEL_P<2> VDD VSS / RSC_IHPSG13_INVX2 +XB_DEC3INV<1> net044<14> B_SEL_P<1> VDD VSS / RSC_IHPSG13_INVX2 +XB_DEC3INV<0> net044<15> B_SEL_P<0> VDD VSS / RSC_IHPSG13_INVX2 +XB_I83 B_BM_R B_BM_N VDD VSS / RSC_IHPSG13_INVX2 +XB_I49 B_DI_R B_DI_N VDD VSS / RSC_IHPSG13_INVX2 +XI_FILL8<20> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI_FILL8<19> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI_FILL8<18> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI_FILL8<17> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI_FILL8<16> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI_FILL8<15> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI_FILL8<14> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI_FILL8<13> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI_FILL8<12> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI_FILL8<11> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI_FILL8<10> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI_FILL8<9> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI_FILL8<8> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI_FILL8<7> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI_FILL8<6> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI_FILL8<5> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI_FILL8<4> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI_FILL8<3> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI_FILL8<2> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI_FILL8<1> VDD VSS / RSC_IHPSG13_FILLCAP8 +XA_I44 A_BM_N A_WCLK_B_L A_DO_WRITE_P VDD VSS / RSC_IHPSG13_NOR2X2 +XB_I44 B_BM_N B_WCLK_B_L B_DO_WRITE_P VDD VSS / RSC_IHPSG13_NOR2X2 +XA_DEC3<15> A_P0 A_ADDR_DEC<7> net23<0> VDD VSS / RSC_IHPSG13_NAND2X2 +XA_DEC3<14> A_P0 A_ADDR_DEC<6> net23<1> VDD VSS / RSC_IHPSG13_NAND2X2 +XA_DEC3<13> A_P0 A_ADDR_DEC<5> net23<2> VDD VSS / RSC_IHPSG13_NAND2X2 +XA_DEC3<12> A_P0 A_ADDR_DEC<4> net23<3> VDD VSS / RSC_IHPSG13_NAND2X2 +XA_DEC3<11> A_P0 A_ADDR_DEC<3> net23<4> VDD VSS / RSC_IHPSG13_NAND2X2 +XA_DEC3<10> A_P0 A_ADDR_DEC<2> net23<5> VDD VSS / RSC_IHPSG13_NAND2X2 +XA_DEC3<9> A_P0 A_ADDR_DEC<1> net23<6> VDD VSS / RSC_IHPSG13_NAND2X2 +XA_DEC3<8> A_P0 A_ADDR_DEC<0> net23<7> VDD VSS / RSC_IHPSG13_NAND2X2 +XA_DEC3<7> A_N0 A_ADDR_DEC<7> net23<8> VDD VSS / RSC_IHPSG13_NAND2X2 +XA_DEC3<6> A_N0 A_ADDR_DEC<6> net23<9> VDD VSS / RSC_IHPSG13_NAND2X2 +XA_DEC3<5> A_N0 A_ADDR_DEC<5> net23<10> VDD VSS / RSC_IHPSG13_NAND2X2 +XA_DEC3<4> A_N0 A_ADDR_DEC<4> net23<11> VDD VSS / RSC_IHPSG13_NAND2X2 +XA_DEC3<3> A_N0 A_ADDR_DEC<3> net23<12> VDD VSS / RSC_IHPSG13_NAND2X2 +XA_DEC3<2> A_N0 A_ADDR_DEC<2> net23<13> VDD VSS / RSC_IHPSG13_NAND2X2 +XA_DEC3<1> A_N0 A_ADDR_DEC<1> net23<14> VDD VSS / RSC_IHPSG13_NAND2X2 +XA_DEC3<0> A_N0 A_ADDR_DEC<0> net23<15> VDD VSS / RSC_IHPSG13_NAND2X2 +XB_DEC3<15> B_P0 B_ADDR_DEC<7> net044<0> VDD VSS / RSC_IHPSG13_NAND2X2 +XB_DEC3<14> B_P0 B_ADDR_DEC<6> net044<1> VDD VSS / RSC_IHPSG13_NAND2X2 +XB_DEC3<13> B_P0 B_ADDR_DEC<5> net044<2> VDD VSS / RSC_IHPSG13_NAND2X2 +XB_DEC3<12> B_P0 B_ADDR_DEC<4> net044<3> VDD VSS / RSC_IHPSG13_NAND2X2 +XB_DEC3<11> B_P0 B_ADDR_DEC<3> net044<4> VDD VSS / RSC_IHPSG13_NAND2X2 +XB_DEC3<10> B_P0 B_ADDR_DEC<2> net044<5> VDD VSS / RSC_IHPSG13_NAND2X2 +XB_DEC3<9> B_P0 B_ADDR_DEC<1> net044<6> VDD VSS / RSC_IHPSG13_NAND2X2 +XB_DEC3<8> B_P0 B_ADDR_DEC<0> net044<7> VDD VSS / RSC_IHPSG13_NAND2X2 +XB_DEC3<7> B_N0 B_ADDR_DEC<7> net044<8> VDD VSS / RSC_IHPSG13_NAND2X2 +XB_DEC3<6> B_N0 B_ADDR_DEC<6> net044<9> VDD VSS / RSC_IHPSG13_NAND2X2 +XB_DEC3<5> B_N0 B_ADDR_DEC<5> net044<10> VDD VSS / RSC_IHPSG13_NAND2X2 +XB_DEC3<4> B_N0 B_ADDR_DEC<4> net044<11> VDD VSS / RSC_IHPSG13_NAND2X2 +XB_DEC3<3> B_N0 B_ADDR_DEC<3> net044<12> VDD VSS / RSC_IHPSG13_NAND2X2 +XB_DEC3<2> B_N0 B_ADDR_DEC<2> net044<13> VDD VSS / RSC_IHPSG13_NAND2X2 +XB_DEC3<1> B_N0 B_ADDR_DEC<1> net044<14> VDD VSS / RSC_IHPSG13_NAND2X2 +XB_DEC3<0> B_N0 B_ADDR_DEC<0> net044<15> VDD VSS / RSC_IHPSG13_NAND2X2 +XB_BM_TIEH B_TIEH_O VDD VSS / RSC_IHPSG13_TIEH +XA_BM_TIEH A_TIEH_O VDD VSS / RSC_IHPSG13_TIEH +.ENDS + + +.SUBCKT RM_IHPSG13_256x16_c2_2P_ROWDEC5 ADDR_N_I<4> ADDR_N_I<3> ADDR_N_I<2> ADDR_N_I<1> ++ ADDR_N_I<0> CS_I ECLK_I WL_O<31> WL_O<30> WL_O<29> WL_O<28> WL_O<27> ++ WL_O<26> WL_O<25> WL_O<24> WL_O<23> WL_O<22> WL_O<21> WL_O<20> WL_O<19> ++ WL_O<18> WL_O<17> WL_O<16> WL_O<15> WL_O<14> WL_O<13> WL_O<12> WL_O<11> ++ WL_O<10> WL_O<9> WL_O<8> WL_O<7> WL_O<6> WL_O<5> WL_O<4> WL_O<3> WL_O<2> ++ WL_O<1> WL_O<0> VDD VSS +XDEC00 ADDR_N_I<5> ADDR_N_I<4> CS_I CS00<0> VDD VSS / ++ RM_IHPSG13_256x16_c2_2P_DEC00 +XSEL<1> ADDR_N_I<3> ADDR_N_I<2> ADDR_N_I<1> ADDR_N_I<0> CS00<1> ECLK_H<1> ++ ECLK_H<2> ECLK_B<1> ECLK_B<2> WL_O<31> WL_O<30> WL_O<29> WL_O<28> WL_O<27> ++ WL_O<26> WL_O<25> WL_O<24> WL_O<23> WL_O<22> WL_O<21> WL_O<20> WL_O<19> ++ WL_O<18> WL_O<17> WL_O<16> VDD VSS / RM_IHPSG13_256x16_c2_2P_DEC04 +XSEL<0> ADDR_N_I<3> ADDR_N_I<2> ADDR_N_I<1> ADDR_N_I<0> CS00<0> ECLK_I ++ ECLK_H<1> ECLK_B<0> ECLK_B<1> WL_O<15> WL_O<14> WL_O<13> WL_O<12> WL_O<11> ++ WL_O<10> WL_O<9> WL_O<8> WL_O<7> WL_O<6> WL_O<5> WL_O<4> WL_O<3> WL_O<2> ++ WL_O<1> WL_O<0> VDD VSS / RM_IHPSG13_256x16_c2_2P_DEC04 +XDEC01 ADDR_N_I<5> ADDR_N_I<4> CS_I CS00<1> VDD VSS / ++ RM_IHPSG13_256x16_c2_2P_DEC01 +XL2<18> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<17> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<16> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<15> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<14> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<13> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<12> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<11> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<10> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<9> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<8> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<7> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<6> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<5> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<4> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<3> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<2> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<1> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI0 ADDR_N_I<5> VDD VSS / RSC_IHPSG13_TIEL +.ENDS +.SUBCKT RM_IHPSG13_256x16_c2_2P_ROWREG5 ACLK_N_I ADDR_I<4> ADDR_I<3> ADDR_I<2> ADDR_I<1> ++ ADDR_I<0> ADDR_N_O<4> ADDR_N_O<3> ADDR_N_O<2> ADDR_N_O<1> ADDR_N_O<0> ++ BIST_ADDR_I<4> BIST_ADDR_I<3> BIST_ADDR_I<2> BIST_ADDR_I<1> BIST_ADDR_I<0> ++ BIST_EN_I VDD VSS +XINV<4> q_int<4> qn_int<4> VDD VSS / RSC_IHPSG13_CINVX2 +XINV<3> q_int<3> qn_int<3> VDD VSS / RSC_IHPSG13_CINVX2 +XINV<2> q_int<2> qn_int<2> VDD VSS / RSC_IHPSG13_CINVX2 +XINV<1> q_int<1> qn_int<1> VDD VSS / RSC_IHPSG13_CINVX2 +XINV<0> q_int<0> qn_int<0> VDD VSS / RSC_IHPSG13_CINVX2 +XDRV<4> qn_int<4> ADDR_N_O<4> VDD VSS / RSC_IHPSG13_CINVX8 +XDRV<3> qn_int<3> ADDR_N_O<3> VDD VSS / RSC_IHPSG13_CINVX8 +XDRV<2> qn_int<2> ADDR_N_O<2> VDD VSS / RSC_IHPSG13_CINVX8 +XDRV<1> qn_int<1> ADDR_N_O<1> VDD VSS / RSC_IHPSG13_CINVX8 +XDRV<0> qn_int<0> ADDR_N_O<0> VDD VSS / RSC_IHPSG13_CINVX8 +XDFF<4> BIST_EN_I BIST_ADDR_I<4> ACLK_N_I ADDR_I<4> q_int<4> net2<0> VDD ++ VSS / RSC_IHPSG13_DFNQMX2IX1 +XDFF<3> BIST_EN_I BIST_ADDR_I<3> ACLK_N_I ADDR_I<3> q_int<3> net2<1> VDD ++ VSS / RSC_IHPSG13_DFNQMX2IX1 +XDFF<2> BIST_EN_I BIST_ADDR_I<2> ACLK_N_I ADDR_I<2> q_int<2> net2<2> VDD ++ VSS / RSC_IHPSG13_DFNQMX2IX1 +XDFF<1> BIST_EN_I BIST_ADDR_I<1> ACLK_N_I ADDR_I<1> q_int<1> net2<3> VDD ++ VSS / RSC_IHPSG13_DFNQMX2IX1 +XDFF<0> BIST_EN_I BIST_ADDR_I<0> ACLK_N_I ADDR_I<0> q_int<0> net2<4> VDD ++ VSS / RSC_IHPSG13_DFNQMX2IX1 +XI11<16> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI11<15> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI11<14> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI11<13> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI11<12> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI11<11> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI11<10> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI11<9> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI11<8> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI11<7> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI11<6> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI11<5> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI11<4> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI11<3> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI11<2> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI11<1> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI12<3> VDD VSS / RSC_IHPSG13_FILLCAP4 +XI12<2> VDD VSS / RSC_IHPSG13_FILLCAP4 +XI12<1> VDD VSS / RSC_IHPSG13_FILLCAP4 +XI12<0> VDD VSS / RSC_IHPSG13_FILLCAP4 +.ENDS + + +.SUBCKT RM_IHPSG13_256x16_c2_2P_COLDEC3 ACLK_N ADDR<2> ADDR<1> ADDR<0> ADDR_COL<1> ++ ADDR_COL<0> ADDR_DEC<7> ADDR_DEC<6> ADDR_DEC<5> ADDR_DEC<4> ADDR_DEC<3> ++ ADDR_DEC<2> ADDR_DEC<1> ADDR_DEC<0> BIST_ADDR<2> BIST_ADDR<1> BIST_ADDR<0> ++ BIST_EN_I VDD VSS +XI1<7> PADR<0> PADR<1> PADR<2> addr_n<7> VDD VSS / RSC_IHPSG13_NAND3X2 +XI1<6> NADR<0> PADR<1> PADR<2> addr_n<6> VDD VSS / RSC_IHPSG13_NAND3X2 +XI1<5> PADR<0> NADR<1> PADR<2> addr_n<5> VDD VSS / RSC_IHPSG13_NAND3X2 +XI1<4> NADR<0> NADR<1> PADR<2> addr_n<4> VDD VSS / RSC_IHPSG13_NAND3X2 +XI1<3> PADR<0> PADR<1> NADR<2> addr_n<3> VDD VSS / RSC_IHPSG13_NAND3X2 +XI1<2> NADR<0> PADR<1> NADR<2> addr_n<2> VDD VSS / RSC_IHPSG13_NAND3X2 +XI1<1> PADR<0> NADR<1> NADR<2> addr_n<1> VDD VSS / RSC_IHPSG13_NAND3X2 +XI1<0> NADR<0> NADR<1> NADR<2> addr_n<0> VDD VSS / RSC_IHPSG13_NAND3X2 +XDFF<2> BIST_EN_I BIST_ADDR<2> ACLK_N ADDR<2> padr_int<2> net13<0> VDD ++ VSS / RSC_IHPSG13_DFNQMX2IX1 +XDFF<1> BIST_EN_I BIST_ADDR<1> ACLK_N ADDR<1> padr_int<1> net13<1> VDD ++ VSS / RSC_IHPSG13_DFNQMX2IX1 +XDFF<0> BIST_EN_I BIST_ADDR<0> ACLK_N ADDR<0> padr_int<0> net13<2> VDD ++ VSS / RSC_IHPSG13_DFNQMX2IX1 +XI15<1> ADDR_COL<1> VDD VSS / RSC_IHPSG13_TIEL +XI15<0> ADDR_COL<0> VDD VSS / RSC_IHPSG13_TIEL +XI13<2> NADR<2> PADR<2> VDD VSS / RSC_IHPSG13_INVX2 +XI13<1> NADR<1> PADR<1> VDD VSS / RSC_IHPSG13_INVX2 +XI13<0> NADR<0> PADR<0> VDD VSS / RSC_IHPSG13_INVX2 +XI3<2> padr_int<2> NADR<2> VDD VSS / RSC_IHPSG13_INVX2 +XI3<1> padr_int<1> NADR<1> VDD VSS / RSC_IHPSG13_INVX2 +XI3<0> padr_int<0> NADR<0> VDD VSS / RSC_IHPSG13_INVX2 +XI2<7> addr_n<7> ADDR_DEC<7> VDD VSS / RSC_IHPSG13_INVX2 +XI2<6> addr_n<6> ADDR_DEC<6> VDD VSS / RSC_IHPSG13_INVX2 +XI2<5> addr_n<5> ADDR_DEC<5> VDD VSS / RSC_IHPSG13_INVX2 +XI2<4> addr_n<4> ADDR_DEC<4> VDD VSS / RSC_IHPSG13_INVX2 +XI2<3> addr_n<3> ADDR_DEC<3> VDD VSS / RSC_IHPSG13_INVX2 +XI2<2> addr_n<2> ADDR_DEC<2> VDD VSS / RSC_IHPSG13_INVX2 +XI2<1> addr_n<1> ADDR_DEC<1> VDD VSS / RSC_IHPSG13_INVX2 +XI2<0> addr_n<0> ADDR_DEC<0> VDD VSS / RSC_IHPSG13_INVX2 +XI17<4> VDD VSS / RSC_IHPSG13_FILLCAP4 +XI17<3> VDD VSS / RSC_IHPSG13_FILLCAP4 +XI17<2> VDD VSS / RSC_IHPSG13_FILLCAP4 +XI17<1> VDD VSS / RSC_IHPSG13_FILLCAP4 +XI16<11> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI16<10> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI16<9> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI16<8> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI16<7> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI16<6> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI16<5> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI16<4> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI16<3> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI16<2> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI16<1> VDD VSS / RSC_IHPSG13_FILLCAP8 +.ENDS +.SUBCKT RSC_IHPSG13_DFPQD_MSAFFX2P CP DN DP QN QP VDD VSS +XI_AMP CP DN DP QN QP VDD VSS / RSC_IHPSG13_DFPQD_MSAFFX2 +.ENDS +.SUBCKT RM_IHPSG13_256x16_c2_2P_COLCTRL3 A_ADDR_DEC<7> A_ADDR_DEC<6> A_ADDR_DEC<5> ++ A_ADDR_DEC<4> A_ADDR_DEC<3> A_ADDR_DEC<2> A_ADDR_DEC<1> A_ADDR_DEC<0> ++ A_BIST_BM_I A_BIST_DW_I A_BIST_EN_I A_BLC<7> A_BLC<6> A_BLC<5> A_BLC<4> ++ A_BLC<3> A_BLC<2> A_BLC<1> A_BLC<0> A_BLT<7> A_BLT<6> A_BLT<5> A_BLT<4> ++ A_BLT<3> A_BLT<2> A_BLT<1> A_BLT<0> A_BM_I A_DCLK_B_L A_DCLK_B_R A_DCLK_L ++ A_DCLK_R A_DR_O A_DW_I A_RCLK_B_L A_RCLK_B_R A_RCLK_L A_RCLK_R A_TIEH_O ++ A_WCLK_B_L A_WCLK_B_R A_WCLK_L A_WCLK_R B_ADDR_DEC<7> B_ADDR_DEC<6> ++ B_ADDR_DEC<5> B_ADDR_DEC<4> B_ADDR_DEC<3> B_ADDR_DEC<2> B_ADDR_DEC<1> ++ B_ADDR_DEC<0> B_BIST_BM_I B_BIST_DW_I B_BIST_EN_I B_BLC<7> B_BLC<6> B_BLC<5> ++ B_BLC<4> B_BLC<3> B_BLC<2> B_BLC<1> B_BLC<0> B_BLT<7> B_BLT<6> B_BLT<5> ++ B_BLT<4> B_BLT<3> B_BLT<2> B_BLT<1> B_BLT<0> B_BM_I B_DCLK_B_L B_DCLK_B_R ++ B_DCLK_L B_DCLK_R B_DR_O B_DW_I B_RCLK_B_L B_RCLK_B_R B_RCLK_L B_RCLK_R ++ B_TIEH_O B_WCLK_B_L B_WCLK_B_R B_WCLK_L B_WCLK_R VDD VSS +XB_DREG B_BIST_EN_I B_BIST_DW_I B_DCLK_B_L B_DW_I B_DI_R net044 VDD ++ VSS / RSC_IHPSG13_DFNQMX2IX1 +XB_BREG B_BIST_EN_I B_BIST_BM_I B_DCLK_B_L B_BM_I B_BM_R net043 VDD ++ VSS / RSC_IHPSG13_DFNQMX2IX1 +XA_DREG A_BIST_EN_I A_BIST_DW_I A_DCLK_B_L A_DW_I A_DI_R net22 VDD VSS ++ / RSC_IHPSG13_DFNQMX2IX1 +XA_BREG A_BIST_EN_I A_BIST_BM_I A_DCLK_B_L A_BM_I A_BM_R net23 VDD VSS ++ / RSC_IHPSG13_DFNQMX2IX1 +XI_FILL8<11> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI_FILL8<10> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI_FILL8<9> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI_FILL8<8> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI_FILL8<7> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI_FILL8<6> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI_FILL8<5> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI_FILL8<4> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI_FILL8<3> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI_FILL8<2> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI_FILL8<1> VDD VSS / RSC_IHPSG13_FILLCAP8 +XB_I51 net037 B_DR_O VDD VSS / RSC_IHPSG13_INVX4 +XA_I51 net19 A_DR_O VDD VSS / RSC_IHPSG13_INVX4 +XB_I44 B_BM_N B_WCLK_B_L B_DO_WRITE_P VDD VSS / RSC_IHPSG13_NOR2X2 +XA_I44 A_BM_N A_WCLK_B_L A_DO_WRITE_P VDD VSS / RSC_IHPSG13_NOR2X2 +XB_BM_TIEH B_TIEH_O VDD VSS / RSC_IHPSG13_TIEH +XA_BM_TIEH A_TIEH_O VDD VSS / RSC_IHPSG13_TIEH +XB_ISENSE B_SAE B_BLC_SEL B_BLT_SEL net037 net038 VDD VSS / ++ RSC_IHPSG13_DFPQD_MSAFFX2P +XA_ISENSE A_SAE A_BLC_SEL A_BLT_SEL net19 net20 VDD VSS / ++ RSC_IHPSG13_DFPQD_MSAFFX2P +XB_I49 B_DI_R B_DI_N VDD VSS / RSC_IHPSG13_INVX2 +XB_I83 B_BM_R B_BM_N VDD VSS / RSC_IHPSG13_INVX2 +XA_I49 A_DI_R A_DI_N VDD VSS / RSC_IHPSG13_INVX2 +XA_I83 A_BM_R A_BM_N VDD VSS / RSC_IHPSG13_INVX2 +XB_I69 B_DCLK_L B_DCLK_B_L VDD VSS / RSC_IHPSG13_CINVX2 +XB_I50 B_WCLK_L B_WCLK_B_L VDD VSS / RSC_IHPSG13_CINVX2 +XB_EBUF B_RCLK_L B_RCLK_B_L VDD VSS / RSC_IHPSG13_CINVX2 +XA_I69 A_DCLK_L A_DCLK_B_L VDD VSS / RSC_IHPSG13_CINVX2 +XA_I50 A_WCLK_L A_WCLK_B_L VDD VSS / RSC_IHPSG13_CINVX2 +XA_EBUF A_RCLK_L A_RCLK_B_L VDD VSS / RSC_IHPSG13_CINVX2 +XAB_BLMUX<1> A_BLC<7> A_BLC<6> A_BLC<5> A_BLC<4> A_BLC_SEL A_BLT<7> A_BLT<6> ++ A_BLT<5> A_BLT<4> A_BLT_SEL A_PRE_N A_ADDR_DEC<7> A_ADDR_DEC<6> ++ A_ADDR_DEC<5> A_ADDR_DEC<4> A_WR_ONE A_WR_ZERO B_BLC<7> B_BLC<6> B_BLC<5> ++ B_BLC<4> B_BLC_SEL B_BLT<7> B_BLT<6> B_BLT<5> B_BLT<4> B_BLT_SEL B_PRE_N ++ B_ADDR_DEC<7> B_ADDR_DEC<6> B_ADDR_DEC<5> B_ADDR_DEC<4> B_WR_ONE B_WR_ZERO ++ VDD VSS / RM_IHPSG13_256x16_c2_2P_BLDRV +XAB_BLMUX<0> A_BLC<3> A_BLC<2> A_BLC<1> A_BLC<0> A_BLC_SEL A_BLT<3> A_BLT<2> ++ A_BLT<1> A_BLT<0> A_BLT_SEL A_PRE_N A_ADDR_DEC<3> A_ADDR_DEC<2> ++ A_ADDR_DEC<1> A_ADDR_DEC<0> A_WR_ONE A_WR_ZERO B_BLC<3> B_BLC<2> B_BLC<1> ++ B_BLC<0> B_BLC_SEL B_BLT<3> B_BLT<2> B_BLT<1> B_BLT<0> B_BLT_SEL B_PRE_N ++ B_ADDR_DEC<3> B_ADDR_DEC<2> B_ADDR_DEC<1> B_ADDR_DEC<0> B_WR_ONE B_WR_ZERO ++ VDD VSS / RM_IHPSG13_256x16_c2_2P_BLDRV +XB_I78 B_RCLK_B_L B_SAE VDD VSS / RSC_IHPSG13_CBUFX2 +XA_I78 A_RCLK_B_L A_SAE VDD VSS / RSC_IHPSG13_CBUFX2 +XB_I88 B_DCLK_L B_DCLK_R / RSC_IHPSG13_MET3RES +XB_I87 B_WCLK_L B_WCLK_R / RSC_IHPSG13_MET3RES +XB_R2 B_RCLK_L B_RCLK_R / RSC_IHPSG13_MET3RES +XB_I91 B_RCLK_B_L B_RCLK_B_R / RSC_IHPSG13_MET3RES +XB_I90 B_WCLK_B_L B_WCLK_B_R / RSC_IHPSG13_MET3RES +XB_I89 B_DCLK_B_L B_DCLK_B_R / RSC_IHPSG13_MET3RES +XA_I88 A_DCLK_L A_DCLK_R / RSC_IHPSG13_MET3RES +XA_I87 A_WCLK_L A_WCLK_R / RSC_IHPSG13_MET3RES +XA_R2 A_RCLK_L A_RCLK_R / RSC_IHPSG13_MET3RES +XA_I91 A_RCLK_B_L A_RCLK_B_R / RSC_IHPSG13_MET3RES +XA_I90 A_WCLK_B_L A_WCLK_B_R / RSC_IHPSG13_MET3RES +XA_I89 A_DCLK_B_L A_DCLK_B_R / RSC_IHPSG13_MET3RES +XB_I80 B_WCLK_B_L B_RCLK_B_L net041 VDD VSS / RSC_IHPSG13_AND2X2 +XB_I76 B_DO_WRITE_P B_DI_N B_WR_ZERO VDD VSS / RSC_IHPSG13_AND2X2 +XB_I75 B_DO_WRITE_P B_DI_R B_WR_ONE VDD VSS / RSC_IHPSG13_AND2X2 +XA_I80 A_WCLK_B_L A_RCLK_B_L net21 VDD VSS / RSC_IHPSG13_AND2X2 +XA_I76 A_DI_N A_DO_WRITE_P A_WR_ZERO VDD VSS / RSC_IHPSG13_AND2X2 +XA_I75 A_DI_R A_DO_WRITE_P A_WR_ONE VDD VSS / RSC_IHPSG13_AND2X2 +XB_I81 net041 B_PRE_N VDD VSS / RSC_IHPSG13_CINVX4_WN +XA_I81 net21 A_PRE_N VDD VSS / RSC_IHPSG13_CINVX4_WN +XI_FILL4<10> VDD VSS / RSC_IHPSG13_FILLCAP4 +XI_FILL4<9> VDD VSS / RSC_IHPSG13_FILLCAP4 +XI_FILL4<8> VDD VSS / RSC_IHPSG13_FILLCAP4 +XI_FILL4<7> VDD VSS / RSC_IHPSG13_FILLCAP4 +XI_FILL4<6> VDD VSS / RSC_IHPSG13_FILLCAP4 +XI_FILL4<5> VDD VSS / RSC_IHPSG13_FILLCAP4 +XI_FILL4<4> VDD VSS / RSC_IHPSG13_FILLCAP4 +XI_FILL4<3> VDD VSS / RSC_IHPSG13_FILLCAP4 +XI_FILL4<2> VDD VSS / RSC_IHPSG13_FILLCAP4 +XI_FILL4<1> VDD VSS / RSC_IHPSG13_FILLCAP4 +.ENDS + +.SUBCKT RM_IHPSG13_256x16_c2_2P_ROWDEC6 ADDR_N_I<5> ADDR_N_I<4> ADDR_N_I<3> ADDR_N_I<2> ++ ADDR_N_I<1> ADDR_N_I<0> CS_I ECLK_I WL_O<63> WL_O<62> WL_O<61> WL_O<60> ++ WL_O<59> WL_O<58> WL_O<57> WL_O<56> WL_O<55> WL_O<54> WL_O<53> WL_O<52> ++ WL_O<51> WL_O<50> WL_O<49> WL_O<48> WL_O<47> WL_O<46> WL_O<45> WL_O<44> ++ WL_O<43> WL_O<42> WL_O<41> WL_O<40> WL_O<39> WL_O<38> WL_O<37> WL_O<36> ++ WL_O<35> WL_O<34> WL_O<33> WL_O<32> WL_O<31> WL_O<30> WL_O<29> WL_O<28> ++ WL_O<27> WL_O<26> WL_O<25> WL_O<24> WL_O<23> WL_O<22> WL_O<21> WL_O<20> ++ WL_O<19> WL_O<18> WL_O<17> WL_O<16> WL_O<15> WL_O<14> WL_O<13> WL_O<12> ++ WL_O<11> WL_O<10> WL_O<9> WL_O<8> WL_O<7> WL_O<6> WL_O<5> WL_O<4> WL_O<3> ++ WL_O<2> WL_O<1> WL_O<0> VDD VSS +XDEC10 ADDR_N_I<5> ADDR_N_I<4> CS_I CS00<2> VDD VSS / ++ RM_IHPSG13_256x16_c2_2P_DEC02 +XDEC00 ADDR_N_I<5> ADDR_N_I<4> CS_I CS00<0> VDD VSS / ++ RM_IHPSG13_256x16_c2_2P_DEC00 +XSEL<3> ADDR_N_I<3> ADDR_N_I<2> ADDR_N_I<1> ADDR_N_I<0> CS00<3> ECLK_H<3> ++ ECLK_H<4> ECLK_B<3> ECLK_B<4> WL_O<63> WL_O<62> WL_O<61> WL_O<60> WL_O<59> ++ WL_O<58> WL_O<57> WL_O<56> WL_O<55> WL_O<54> WL_O<53> WL_O<52> WL_O<51> ++ WL_O<50> WL_O<49> WL_O<48> VDD VSS / RM_IHPSG13_256x16_c2_2P_DEC04 +XSEL<2> ADDR_N_I<3> ADDR_N_I<2> ADDR_N_I<1> ADDR_N_I<0> CS00<2> ECLK_H<2> ++ ECLK_H<3> ECLK_B<2> ECLK_B<3> WL_O<47> WL_O<46> WL_O<45> WL_O<44> WL_O<43> ++ WL_O<42> WL_O<41> WL_O<40> WL_O<39> WL_O<38> WL_O<37> WL_O<36> WL_O<35> ++ WL_O<34> WL_O<33> WL_O<32> VDD VSS / RM_IHPSG13_256x16_c2_2P_DEC04 +XSEL<1> ADDR_N_I<3> ADDR_N_I<2> ADDR_N_I<1> ADDR_N_I<0> CS00<1> ECLK_H<1> ++ ECLK_H<2> ECLK_B<1> ECLK_B<2> WL_O<31> WL_O<30> WL_O<29> WL_O<28> WL_O<27> ++ WL_O<26> WL_O<25> WL_O<24> WL_O<23> WL_O<22> WL_O<21> WL_O<20> WL_O<19> ++ WL_O<18> WL_O<17> WL_O<16> VDD VSS / RM_IHPSG13_256x16_c2_2P_DEC04 +XSEL<0> ADDR_N_I<3> ADDR_N_I<2> ADDR_N_I<1> ADDR_N_I<0> CS00<0> ECLK_I ++ ECLK_H<1> ECLK_B<0> ECLK_B<1> WL_O<15> WL_O<14> WL_O<13> WL_O<12> WL_O<11> ++ WL_O<10> WL_O<9> WL_O<8> WL_O<7> WL_O<6> WL_O<5> WL_O<4> WL_O<3> WL_O<2> ++ WL_O<1> WL_O<0> VDD VSS / RM_IHPSG13_256x16_c2_2P_DEC04 +XDEC11 ADDR_N_I<5> ADDR_N_I<4> CS_I CS00<3> VDD VSS / ++ RM_IHPSG13_256x16_c2_2P_DEC03 +XL2<36> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<35> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<34> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<33> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<32> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<31> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<30> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<29> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<28> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<27> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<26> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<25> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<24> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<23> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<22> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<21> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<20> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<19> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<18> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<17> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<16> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<15> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<14> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<13> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<12> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<11> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<10> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<9> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<8> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<7> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<6> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<5> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<4> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<3> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<2> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<1> VDD VSS / RSC_IHPSG13_FILLCAP8 +XDEC01 ADDR_N_I<5> ADDR_N_I<4> CS_I CS00<1> VDD VSS / ++ RM_IHPSG13_256x16_c2_2P_DEC01 +.ENDS +.SUBCKT RM_IHPSG13_256x16_c2_2P_ROWREG6 ACLK_N_I ADDR_I<5> ADDR_I<4> ADDR_I<3> ADDR_I<2> ++ ADDR_I<1> ADDR_I<0> ADDR_N_O<5> ADDR_N_O<4> ADDR_N_O<3> ADDR_N_O<2> ++ ADDR_N_O<1> ADDR_N_O<0> BIST_ADDR_I<5> BIST_ADDR_I<4> BIST_ADDR_I<3> ++ BIST_ADDR_I<2> BIST_ADDR_I<1> BIST_ADDR_I<0> BIST_EN_I VDD VSS +XINV<5> q_int<5> qn_int<5> VDD VSS / RSC_IHPSG13_CINVX2 +XINV<4> q_int<4> qn_int<4> VDD VSS / RSC_IHPSG13_CINVX2 +XINV<3> q_int<3> qn_int<3> VDD VSS / RSC_IHPSG13_CINVX2 +XINV<2> q_int<2> qn_int<2> VDD VSS / RSC_IHPSG13_CINVX2 +XINV<1> q_int<1> qn_int<1> VDD VSS / RSC_IHPSG13_CINVX2 +XINV<0> q_int<0> qn_int<0> VDD VSS / RSC_IHPSG13_CINVX2 +XDRV<5> qn_int<5> ADDR_N_O<5> VDD VSS / RSC_IHPSG13_CINVX8 +XDRV<4> qn_int<4> ADDR_N_O<4> VDD VSS / RSC_IHPSG13_CINVX8 +XDRV<3> qn_int<3> ADDR_N_O<3> VDD VSS / RSC_IHPSG13_CINVX8 +XDRV<2> qn_int<2> ADDR_N_O<2> VDD VSS / RSC_IHPSG13_CINVX8 +XDRV<1> qn_int<1> ADDR_N_O<1> VDD VSS / RSC_IHPSG13_CINVX8 +XDRV<0> qn_int<0> ADDR_N_O<0> VDD VSS / RSC_IHPSG13_CINVX8 +XDFF<5> BIST_EN_I BIST_ADDR_I<5> ACLK_N_I ADDR_I<5> q_int<5> net2<0> VDD ++ VSS / RSC_IHPSG13_DFNQMX2IX1 +XDFF<4> BIST_EN_I BIST_ADDR_I<4> ACLK_N_I ADDR_I<4> q_int<4> net2<1> VDD ++ VSS / RSC_IHPSG13_DFNQMX2IX1 +XDFF<3> BIST_EN_I BIST_ADDR_I<3> ACLK_N_I ADDR_I<3> q_int<3> net2<2> VDD ++ VSS / RSC_IHPSG13_DFNQMX2IX1 +XDFF<2> BIST_EN_I BIST_ADDR_I<2> ACLK_N_I ADDR_I<2> q_int<2> net2<3> VDD ++ VSS / RSC_IHPSG13_DFNQMX2IX1 +XDFF<1> BIST_EN_I BIST_ADDR_I<1> ACLK_N_I ADDR_I<1> q_int<1> net2<4> VDD ++ VSS / RSC_IHPSG13_DFNQMX2IX1 +XDFF<0> BIST_EN_I BIST_ADDR_I<0> ACLK_N_I ADDR_I<0> q_int<0> net2<5> VDD ++ VSS / RSC_IHPSG13_DFNQMX2IX1 +XI11<12> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI11<11> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI11<10> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI11<9> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI11<8> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI11<7> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI11<6> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI11<5> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI11<4> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI11<3> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI11<2> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI11<1> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI12<2> VDD VSS / RSC_IHPSG13_FILLCAP4 +XI12<1> VDD VSS / RSC_IHPSG13_FILLCAP4 +XI12<0> VDD VSS / RSC_IHPSG13_FILLCAP4 +.ENDS + +.SUBCKT RM_IHPSG13_256x16_c2_2P_COLDRV13X16 ADDR_COL_I<1> ADDR_COL_I<0> ADDR_COL_O<1> ++ ADDR_COL_O<0> ADDR_DEC_I<7> ADDR_DEC_I<6> ADDR_DEC_I<5> ADDR_DEC_I<4> ++ ADDR_DEC_I<3> ADDR_DEC_I<2> ADDR_DEC_I<1> ADDR_DEC_I<0> ADDR_DEC_O<7> ++ ADDR_DEC_O<6> ADDR_DEC_O<5> ADDR_DEC_O<4> ADDR_DEC_O<3> ADDR_DEC_O<2> ++ ADDR_DEC_O<1> ADDR_DEC_O<0> DCLK_I DCLK_O RCLK_I RCLK_O WCLK_I WCLK_O ++ VDD VSS +XI0<7> VDD VSS / RSC_IHPSG13_FILLCAP4 +XI0<6> VDD VSS / RSC_IHPSG13_FILLCAP4 +XI0<5> VDD VSS / RSC_IHPSG13_FILLCAP4 +XI0<4> VDD VSS / RSC_IHPSG13_FILLCAP4 +XI0<3> VDD VSS / RSC_IHPSG13_FILLCAP4 +XI0<2> VDD VSS / RSC_IHPSG13_FILLCAP4 +XI0<1> VDD VSS / RSC_IHPSG13_FILLCAP4 +XWCLK_DRV WCLK_I WCLK_O VDD VSS / RSC_IHPSG13_CBUFX16 +XRCLK_DRV RCLK_I RCLK_O VDD VSS / RSC_IHPSG13_CBUFX16 +XDCLK_DRV DCLK_I DCLK_O VDD VSS / RSC_IHPSG13_CBUFX16 +XADDR_COL_DRV<1> ADDR_COL_I<1> ADDR_COL_O<1> VDD VSS / ++ RSC_IHPSG13_CBUFX16 +XADDR_COL_DRV<0> ADDR_COL_I<0> ADDR_COL_O<0> VDD VSS / ++ RSC_IHPSG13_CBUFX16 +XADDR_DEC_DRV<7> ADDR_DEC_I<7> ADDR_DEC_O<7> VDD VSS / ++ RSC_IHPSG13_CBUFX16 +XADDR_DEC_DRV<6> ADDR_DEC_I<6> ADDR_DEC_O<6> VDD VSS / ++ RSC_IHPSG13_CBUFX16 +XADDR_DEC_DRV<5> ADDR_DEC_I<5> ADDR_DEC_O<5> VDD VSS / ++ RSC_IHPSG13_CBUFX16 +XADDR_DEC_DRV<4> ADDR_DEC_I<4> ADDR_DEC_O<4> VDD VSS / ++ RSC_IHPSG13_CBUFX16 +XADDR_DEC_DRV<3> ADDR_DEC_I<3> ADDR_DEC_O<3> VDD VSS / ++ RSC_IHPSG13_CBUFX16 +XADDR_DEC_DRV<2> ADDR_DEC_I<2> ADDR_DEC_O<2> VDD VSS / ++ RSC_IHPSG13_CBUFX16 +XADDR_DEC_DRV<1> ADDR_DEC_I<1> ADDR_DEC_O<1> VDD VSS / ++ RSC_IHPSG13_CBUFX16 +XADDR_DEC_DRV<0> ADDR_DEC_I<0> ADDR_DEC_O<0> VDD VSS / ++ RSC_IHPSG13_CBUFX16 +XI1<5> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI1<4> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI1<3> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI1<2> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI1<1> VDD VSS / RSC_IHPSG13_FILLCAP8 +.ENDS +.SUBCKT RM_IHPSG13_256x16_c2_2P_WLDRV16X16 A<15> A<14> A<13> A<12> A<11> A<10> A<9> A<8> ++ A<7> A<6> A<5> A<4> A<3> A<2> A<1> A<0> Z<15> Z<14> Z<13> Z<12> Z<11> Z<10> ++ Z<9> Z<8> Z<7> Z<6> Z<5> Z<4> Z<3> Z<2> Z<1> Z<0> VDD VSS +XBUF<15> A<15> Z<15> VDD VSS / RSC_IHPSG13_WLDRVX16 +XBUF<14> A<14> Z<14> VDD VSS / RSC_IHPSG13_WLDRVX16 +XBUF<13> A<13> Z<13> VDD VSS / RSC_IHPSG13_WLDRVX16 +XBUF<12> A<12> Z<12> VDD VSS / RSC_IHPSG13_WLDRVX16 +XBUF<11> A<11> Z<11> VDD VSS / RSC_IHPSG13_WLDRVX16 +XBUF<10> A<10> Z<10> VDD VSS / RSC_IHPSG13_WLDRVX16 +XBUF<9> A<9> Z<9> VDD VSS / RSC_IHPSG13_WLDRVX16 +XBUF<8> A<8> Z<8> VDD VSS / RSC_IHPSG13_WLDRVX16 +XBUF<7> A<7> Z<7> VDD VSS / RSC_IHPSG13_WLDRVX16 +XBUF<6> A<6> Z<6> VDD VSS / RSC_IHPSG13_WLDRVX16 +XBUF<5> A<5> Z<5> VDD VSS / RSC_IHPSG13_WLDRVX16 +XBUF<4> A<4> Z<4> VDD VSS / RSC_IHPSG13_WLDRVX16 +XBUF<3> A<3> Z<3> VDD VSS / RSC_IHPSG13_WLDRVX16 +XBUF<2> A<2> Z<2> VDD VSS / RSC_IHPSG13_WLDRVX16 +XBUF<1> A<1> Z<1> VDD VSS / RSC_IHPSG13_WLDRVX16 +XBUF<0> A<0> Z<0> VDD VSS / RSC_IHPSG13_WLDRVX16 +.ENDS + + +.SUBCKT RM_IHPSG13_256x16_c2_1P_DEC01 ADDR<1> ADDR<0> CS CS_OUT VDD VSS +XDECINV net1 CS_OUT VDD VSS / RSC_IHPSG13_INVX4 +XDEC NADDR<1> ADDR<0> CS net1 VDD VSS / RSC_IHPSG13_NAND3X2 +XI2 VDD VSS / RSC_IHPSG13_FILLCAP4 +XADDRINV ADDR<1> NADDR<1> VDD VSS / RSC_IHPSG13_INVX2 +.ENDS +.SUBCKT RM_IHPSG13_256x16_c2_1P_DEC00 ADDR<1> ADDR<0> CS CS_OUT VDD VSS +XDECINV net1 CS_OUT VDD VSS / RSC_IHPSG13_INVX4 +XDEC NADDR<1> NADDR<0> CS net1 VDD VSS / RSC_IHPSG13_NAND3X2 +XADDRINV<1> ADDR<1> NADDR<1> VDD VSS / RSC_IHPSG13_INVX2 +XADDRINV<0> ADDR<0> NADDR<0> VDD VSS / RSC_IHPSG13_INVX2 +XI1 VDD VSS / RSC_IHPSG13_FILLCAP4 +.ENDS +.SUBCKT RM_IHPSG13_256x16_c2_1P_ROWDEC5 ADDR_N_I<4> ADDR_N_I<3> ADDR_N_I<2> ADDR_N_I<1> ++ ADDR_N_I<0> CS_I ECLK_I WL_O<31> WL_O<30> WL_O<29> WL_O<28> WL_O<27> ++ WL_O<26> WL_O<25> WL_O<24> WL_O<23> WL_O<22> WL_O<21> WL_O<20> WL_O<19> ++ WL_O<18> WL_O<17> WL_O<16> WL_O<15> WL_O<14> WL_O<13> WL_O<12> WL_O<11> ++ WL_O<10> WL_O<9> WL_O<8> WL_O<7> WL_O<6> WL_O<5> WL_O<4> WL_O<3> WL_O<2> ++ WL_O<1> WL_O<0> VDD VSS +XL2<12> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<11> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<10> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<9> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<8> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<7> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<6> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<5> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<4> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<3> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<2> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<1> VDD VSS / RSC_IHPSG13_FILLCAP8 +XDEC01 ADDR_N_I<5> ADDR_N_I<4> CS_I CS00<1> VDD VSS / ++ RM_IHPSG13_256x16_c2_1P_DEC01 +XDEC00 ADDR_N_I<5> ADDR_N_I<4> CS_I CS00<0> VDD VSS / ++ RM_IHPSG13_256x16_c2_1P_DEC00 +XSEL<1> ADDR_N_I<3> ADDR_N_I<2> ADDR_N_I<1> ADDR_N_I<0> CS00<1> ECLK_H<1> ++ ECLK_H<2> ECLK_B<1> ECLK_B<2> WL_O<31> WL_O<30> WL_O<29> WL_O<28> WL_O<27> ++ WL_O<26> WL_O<25> WL_O<24> WL_O<23> WL_O<22> WL_O<21> WL_O<20> WL_O<19> ++ WL_O<18> WL_O<17> WL_O<16> VDD VSS / RM_IHPSG13_256x16_c2_1P_DEC04 +XSEL<0> ADDR_N_I<3> ADDR_N_I<2> ADDR_N_I<1> ADDR_N_I<0> CS00<0> ECLK_I ++ ECLK_H<1> ECLK_B<0> ECLK_B<1> WL_O<15> WL_O<14> WL_O<13> WL_O<12> WL_O<11> ++ WL_O<10> WL_O<9> WL_O<8> WL_O<7> WL_O<6> WL_O<5> WL_O<4> WL_O<3> WL_O<2> ++ WL_O<1> WL_O<0> VDD VSS / RM_IHPSG13_256x16_c2_1P_DEC04 +XI0 ADDR_N_I<5> VDD VSS / RSC_IHPSG13_TIEL +.ENDS +.SUBCKT RM_IHPSG13_256x16_c2_1P_ROWREG5 ACLK_N_I ADDR_I<4> ADDR_I<3> ADDR_I<2> ADDR_I<1> ++ ADDR_I<0> ADDR_N_O<4> ADDR_N_O<3> ADDR_N_O<2> ADDR_N_O<1> ADDR_N_O<0> ++ BIST_ADDR_I<4> BIST_ADDR_I<3> BIST_ADDR_I<2> BIST_ADDR_I<1> BIST_ADDR_I<0> ++ BIST_EN_I VDD VSS +XINV<4> q_int<4> qn_int<4> VDD VSS / RSC_IHPSG13_CINVX2 +XINV<3> q_int<3> qn_int<3> VDD VSS / RSC_IHPSG13_CINVX2 +XINV<2> q_int<2> qn_int<2> VDD VSS / RSC_IHPSG13_CINVX2 +XINV<1> q_int<1> qn_int<1> VDD VSS / RSC_IHPSG13_CINVX2 +XINV<0> q_int<0> qn_int<0> VDD VSS / RSC_IHPSG13_CINVX2 +XDRV<4> qn_int<4> ADDR_N_O<4> VDD VSS / RSC_IHPSG13_CINVX8 +XDRV<3> qn_int<3> ADDR_N_O<3> VDD VSS / RSC_IHPSG13_CINVX8 +XDRV<2> qn_int<2> ADDR_N_O<2> VDD VSS / RSC_IHPSG13_CINVX8 +XDRV<1> qn_int<1> ADDR_N_O<1> VDD VSS / RSC_IHPSG13_CINVX8 +XDRV<0> qn_int<0> ADDR_N_O<0> VDD VSS / RSC_IHPSG13_CINVX8 +XDFF<4> BIST_EN_I BIST_ADDR_I<4> ACLK_N_I ADDR_I<4> q_int<4> net2<0> VDD ++ VSS / RSC_IHPSG13_DFNQMX2IX1 +XDFF<3> BIST_EN_I BIST_ADDR_I<3> ACLK_N_I ADDR_I<3> q_int<3> net2<1> VDD ++ VSS / RSC_IHPSG13_DFNQMX2IX1 +XDFF<2> BIST_EN_I BIST_ADDR_I<2> ACLK_N_I ADDR_I<2> q_int<2> net2<2> VDD ++ VSS / RSC_IHPSG13_DFNQMX2IX1 +XDFF<1> BIST_EN_I BIST_ADDR_I<1> ACLK_N_I ADDR_I<1> q_int<1> net2<3> VDD ++ VSS / RSC_IHPSG13_DFNQMX2IX1 +XDFF<0> BIST_EN_I BIST_ADDR_I<0> ACLK_N_I ADDR_I<0> q_int<0> net2<4> VDD ++ VSS / RSC_IHPSG13_DFNQMX2IX1 +XI11<16> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI11<15> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI11<14> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI11<13> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI11<12> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI11<11> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI11<10> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI11<9> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI11<8> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI11<7> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI11<6> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI11<5> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI11<4> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI11<3> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI11<2> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI11<1> VDD VSS / RSC_IHPSG13_FILLCAP8 +.ENDS + + +.SUBCKT RM_IHPSG13_256x16_c2_1P_COLDEC5 ACLK_N ADDR<4> ADDR<3> ADDR<2> ADDR<1> ADDR<0> ++ ADDR_COL<1> ADDR_COL<0> ADDR_DEC<7> ADDR_DEC<6> ADDR_DEC<5> ADDR_DEC<4> ++ ADDR_DEC<3> ADDR_DEC<2> ADDR_DEC<1> ADDR_DEC<0> BIST_ADDR<4> BIST_ADDR<3> ++ BIST_ADDR<2> BIST_ADDR<1> BIST_ADDR<0> BIST_EN_I VDD VSS +XI17<2> VDD VSS / RSC_IHPSG13_FILLCAP4 +XI17<1> VDD VSS / RSC_IHPSG13_FILLCAP4 +XI13<1> addr_int<1> ADDR_COL<1> VDD VSS / RSC_IHPSG13_CBUFX2 +XI13<0> addr_int<0> ADDR_COL<0> VDD VSS / RSC_IHPSG13_CBUFX2 +XDFF<4> BIST_EN_I BIST_ADDR<4> ACLK_N ADDR<4> addr_int<1> net7<0> VDD ++ VSS / RSC_IHPSG13_DFNQMX2IX1 +XDFF<3> BIST_EN_I BIST_ADDR<3> ACLK_N ADDR<3> addr_int<0> net7<1> VDD ++ VSS / RSC_IHPSG13_DFNQMX2IX1 +XDFF<2> BIST_EN_I BIST_ADDR<2> ACLK_N ADDR<2> padr_int<2> net7<2> VDD ++ VSS / RSC_IHPSG13_DFNQMX2IX1 +XDFF<1> BIST_EN_I BIST_ADDR<1> ACLK_N ADDR<1> padr_int<1> net7<3> VDD ++ VSS / RSC_IHPSG13_DFNQMX2IX1 +XDFF<0> BIST_EN_I BIST_ADDR<0> ACLK_N ADDR<0> padr_int<0> net7<4> VDD ++ VSS / RSC_IHPSG13_DFNQMX2IX1 +XI1<7> PADR<0> PADR<1> PADR<2> addr_n<7> VDD VSS / RSC_IHPSG13_NAND3X2 +XI1<6> NADR<0> PADR<1> PADR<2> addr_n<6> VDD VSS / RSC_IHPSG13_NAND3X2 +XI1<5> PADR<0> NADR<1> PADR<2> addr_n<5> VDD VSS / RSC_IHPSG13_NAND3X2 +XI1<4> NADR<0> NADR<1> PADR<2> addr_n<4> VDD VSS / RSC_IHPSG13_NAND3X2 +XI1<3> PADR<0> PADR<1> NADR<2> addr_n<3> VDD VSS / RSC_IHPSG13_NAND3X2 +XI1<2> NADR<0> PADR<1> NADR<2> addr_n<2> VDD VSS / RSC_IHPSG13_NAND3X2 +XI1<1> PADR<0> NADR<1> NADR<2> addr_n<1> VDD VSS / RSC_IHPSG13_NAND3X2 +XI1<0> NADR<0> NADR<1> NADR<2> addr_n<0> VDD VSS / RSC_IHPSG13_NAND3X2 +XI15<2> NADR<2> PADR<2> VDD VSS / RSC_IHPSG13_INVX2 +XI15<1> NADR<1> PADR<1> VDD VSS / RSC_IHPSG13_INVX2 +XI15<0> NADR<0> PADR<0> VDD VSS / RSC_IHPSG13_INVX2 +XI3<2> padr_int<2> NADR<2> VDD VSS / RSC_IHPSG13_INVX2 +XI3<1> padr_int<1> NADR<1> VDD VSS / RSC_IHPSG13_INVX2 +XI3<0> padr_int<0> NADR<0> VDD VSS / RSC_IHPSG13_INVX2 +XI2<7> addr_n<7> ADDR_DEC<7> VDD VSS / RSC_IHPSG13_INVX2 +XI2<6> addr_n<6> ADDR_DEC<6> VDD VSS / RSC_IHPSG13_INVX2 +XI2<5> addr_n<5> ADDR_DEC<5> VDD VSS / RSC_IHPSG13_INVX2 +XI2<4> addr_n<4> ADDR_DEC<4> VDD VSS / RSC_IHPSG13_INVX2 +XI2<3> addr_n<3> ADDR_DEC<3> VDD VSS / RSC_IHPSG13_INVX2 +XI2<2> addr_n<2> ADDR_DEC<2> VDD VSS / RSC_IHPSG13_INVX2 +XI2<1> addr_n<1> ADDR_DEC<1> VDD VSS / RSC_IHPSG13_INVX2 +XI2<0> addr_n<0> ADDR_DEC<0> VDD VSS / RSC_IHPSG13_INVX2 +.ENDS +.SUBCKT RM_IHPSG13_256x16_c2_1P_COLCTRL5 A_ADDR_COL<1> A_ADDR_COL<0> A_ADDR_DEC<7> ++ A_ADDR_DEC<6> A_ADDR_DEC<5> A_ADDR_DEC<4> A_ADDR_DEC<3> A_ADDR_DEC<2> ++ A_ADDR_DEC<1> A_ADDR_DEC<0> A_BIST_BM_I A_BIST_DW_I A_BIST_EN_I A_BLC<31> ++ A_BLC<30> A_BLC<29> A_BLC<28> A_BLC<27> A_BLC<26> A_BLC<25> A_BLC<24> ++ A_BLC<23> A_BLC<22> A_BLC<21> A_BLC<20> A_BLC<19> A_BLC<18> A_BLC<17> ++ A_BLC<16> A_BLC<15> A_BLC<14> A_BLC<13> A_BLC<12> A_BLC<11> A_BLC<10> ++ A_BLC<9> A_BLC<8> A_BLC<7> A_BLC<6> A_BLC<5> A_BLC<4> A_BLC<3> A_BLC<2> ++ A_BLC<1> A_BLC<0> A_BLT<31> A_BLT<30> A_BLT<29> A_BLT<28> A_BLT<27> ++ A_BLT<26> A_BLT<25> A_BLT<24> A_BLT<23> A_BLT<22> A_BLT<21> A_BLT<20> ++ A_BLT<19> A_BLT<18> A_BLT<17> A_BLT<16> A_BLT<15> A_BLT<14> A_BLT<13> ++ A_BLT<12> A_BLT<11> A_BLT<10> A_BLT<9> A_BLT<8> A_BLT<7> A_BLT<6> A_BLT<5> ++ A_BLT<4> A_BLT<3> A_BLT<2> A_BLT<1> A_BLT<0> A_BM_I A_DCLK_B_L A_DCLK_B_R ++ A_DCLK_L A_DCLK_R A_DR_O A_DW_I A_RCLK_B_L A_RCLK_B_R A_RCLK_L A_RCLK_R ++ A_TIEH_O A_WCLK_B_L A_WCLK_B_R A_WCLK_L A_WCLK_R VDD VSS +XA_I80<1> A_WCLK_B_L A_RCLK_B_L A_W_nor_R<1> VDD VSS / ++ RSC_IHPSG13_AND2X2 +XA_I80<0> A_WCLK_B_L A_RCLK_B_L A_W_nor_R<0> VDD VSS / ++ RSC_IHPSG13_AND2X2 +XA_I44 A_BM_N A_WCLK_B_L A_DO_WRITE_P VDD VSS / RSC_IHPSG13_NOR2X2 +XI80<29> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI80<28> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI80<27> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI80<26> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI80<25> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI80<24> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI80<23> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI80<22> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI80<21> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI80<20> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI80<19> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI80<18> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI80<17> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI80<16> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI80<15> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI80<14> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI80<13> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI80<12> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI80<11> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI80<10> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI80<9> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI80<8> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI80<7> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI80<6> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI80<5> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI80<4> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI80<3> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI80<2> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI80<1> VDD VSS / RSC_IHPSG13_FILLCAP8 +XA_I74<16> VDD VSS / RSC_IHPSG13_FILLCAP8 +XA_I74<15> VDD VSS / RSC_IHPSG13_FILLCAP8 +XA_I74<14> VDD VSS / RSC_IHPSG13_FILLCAP8 +XA_I74<13> VDD VSS / RSC_IHPSG13_FILLCAP8 +XA_I74<12> VDD VSS / RSC_IHPSG13_FILLCAP8 +XA_I74<11> VDD VSS / RSC_IHPSG13_FILLCAP8 +XA_I74<10> VDD VSS / RSC_IHPSG13_FILLCAP8 +XA_I74<9> VDD VSS / RSC_IHPSG13_FILLCAP8 +XA_I74<8> VDD VSS / RSC_IHPSG13_FILLCAP8 +XA_I74<7> VDD VSS / RSC_IHPSG13_FILLCAP8 +XA_I74<6> VDD VSS / RSC_IHPSG13_FILLCAP8 +XA_I74<5> VDD VSS / RSC_IHPSG13_FILLCAP8 +XA_I74<4> VDD VSS / RSC_IHPSG13_FILLCAP8 +XA_I74<3> VDD VSS / RSC_IHPSG13_FILLCAP8 +XA_I74<2> VDD VSS / RSC_IHPSG13_FILLCAP8 +XA_I74<1> VDD VSS / RSC_IHPSG13_FILLCAP8 +XA_INV<6> A_N1<1> A_P1<1> VDD VSS / RSC_IHPSG13_CINVX4 +XA_INV<5> A_N0<1> A_P0<1> VDD VSS / RSC_IHPSG13_CINVX4 +XA_INV<4> A_N0<0> A_P0<0> VDD VSS / RSC_IHPSG13_CINVX4 +XA_INV<3> A_ADDR_COL<1> A_N1<1> VDD VSS / RSC_IHPSG13_CINVX4 +XA_INV<2> A_ADDR_COL<1> A_N1<0> VDD VSS / RSC_IHPSG13_CINVX4 +XA_INV<1> A_ADDR_COL<0> A_N0<1> VDD VSS / RSC_IHPSG13_CINVX4 +XA_INV<0> A_ADDR_COL<0> A_N0<0> VDD VSS / RSC_IHPSG13_CINVX4 +XA_I81<3> A_W_nor_R<1> A_PRE_N VDD VSS / RSC_IHPSG13_CINVX4_WN +XA_I81<2> A_W_nor_R<1> A_PRE_N VDD VSS / RSC_IHPSG13_CINVX4_WN +XA_I81<1> A_W_nor_R<0> A_PRE_N VDD VSS / RSC_IHPSG13_CINVX4_WN +XA_I81<0> A_W_nor_R<0> A_PRE_N VDD VSS / RSC_IHPSG13_CINVX4_WN +XA_BLTMUX<31> A_BLC<31> A_BLC_SEL A_BLT<31> A_BLT_SEL A_PRE_N A_SEL_P<31> ++ A_WR_ONE A_WR_ZERO VDD VSS / RM_IHPSG13_256x16_c2_1P_BLDRV +XA_BLTMUX<30> A_BLC<30> A_BLC_SEL A_BLT<30> A_BLT_SEL A_PRE_N A_SEL_P<30> ++ A_WR_ONE A_WR_ZERO VDD VSS / RM_IHPSG13_256x16_c2_1P_BLDRV +XA_BLTMUX<29> A_BLC<29> A_BLC_SEL A_BLT<29> A_BLT_SEL A_PRE_N A_SEL_P<29> ++ A_WR_ONE A_WR_ZERO VDD VSS / RM_IHPSG13_256x16_c2_1P_BLDRV +XA_BLTMUX<28> A_BLC<28> A_BLC_SEL A_BLT<28> A_BLT_SEL A_PRE_N A_SEL_P<28> ++ A_WR_ONE A_WR_ZERO VDD VSS / RM_IHPSG13_256x16_c2_1P_BLDRV +XA_BLTMUX<27> A_BLC<27> A_BLC_SEL A_BLT<27> A_BLT_SEL A_PRE_N A_SEL_P<27> ++ A_WR_ONE A_WR_ZERO VDD VSS / RM_IHPSG13_256x16_c2_1P_BLDRV +XA_BLTMUX<26> A_BLC<26> A_BLC_SEL A_BLT<26> A_BLT_SEL A_PRE_N A_SEL_P<26> ++ A_WR_ONE A_WR_ZERO VDD VSS / RM_IHPSG13_256x16_c2_1P_BLDRV +XA_BLTMUX<25> A_BLC<25> A_BLC_SEL A_BLT<25> A_BLT_SEL A_PRE_N A_SEL_P<25> ++ A_WR_ONE A_WR_ZERO VDD VSS / RM_IHPSG13_256x16_c2_1P_BLDRV +XA_BLTMUX<24> A_BLC<24> A_BLC_SEL A_BLT<24> A_BLT_SEL A_PRE_N A_SEL_P<24> ++ A_WR_ONE A_WR_ZERO VDD VSS / RM_IHPSG13_256x16_c2_1P_BLDRV +XA_BLTMUX<23> A_BLC<23> A_BLC_SEL A_BLT<23> A_BLT_SEL A_PRE_N A_SEL_P<23> ++ A_WR_ONE A_WR_ZERO VDD VSS / RM_IHPSG13_256x16_c2_1P_BLDRV +XA_BLTMUX<22> A_BLC<22> A_BLC_SEL A_BLT<22> A_BLT_SEL A_PRE_N A_SEL_P<22> ++ A_WR_ONE A_WR_ZERO VDD VSS / RM_IHPSG13_256x16_c2_1P_BLDRV +XA_BLTMUX<21> A_BLC<21> A_BLC_SEL A_BLT<21> A_BLT_SEL A_PRE_N A_SEL_P<21> ++ A_WR_ONE A_WR_ZERO VDD VSS / RM_IHPSG13_256x16_c2_1P_BLDRV +XA_BLTMUX<20> A_BLC<20> A_BLC_SEL A_BLT<20> A_BLT_SEL A_PRE_N A_SEL_P<20> ++ A_WR_ONE A_WR_ZERO VDD VSS / RM_IHPSG13_256x16_c2_1P_BLDRV +XA_BLTMUX<19> A_BLC<19> A_BLC_SEL A_BLT<19> A_BLT_SEL A_PRE_N A_SEL_P<19> ++ A_WR_ONE A_WR_ZERO VDD VSS / RM_IHPSG13_256x16_c2_1P_BLDRV +XA_BLTMUX<18> A_BLC<18> A_BLC_SEL A_BLT<18> A_BLT_SEL A_PRE_N A_SEL_P<18> ++ A_WR_ONE A_WR_ZERO VDD VSS / RM_IHPSG13_256x16_c2_1P_BLDRV +XA_BLTMUX<17> A_BLC<17> A_BLC_SEL A_BLT<17> A_BLT_SEL A_PRE_N A_SEL_P<17> ++ A_WR_ONE A_WR_ZERO VDD VSS / RM_IHPSG13_256x16_c2_1P_BLDRV +XA_BLTMUX<16> A_BLC<16> A_BLC_SEL A_BLT<16> A_BLT_SEL A_PRE_N A_SEL_P<16> ++ A_WR_ONE A_WR_ZERO VDD VSS / RM_IHPSG13_256x16_c2_1P_BLDRV +XA_BLTMUX<15> A_BLC<15> A_BLC_SEL A_BLT<15> A_BLT_SEL A_PRE_N A_SEL_P<15> ++ A_WR_ONE A_WR_ZERO VDD VSS / RM_IHPSG13_256x16_c2_1P_BLDRV +XA_BLTMUX<14> A_BLC<14> A_BLC_SEL A_BLT<14> A_BLT_SEL A_PRE_N A_SEL_P<14> ++ A_WR_ONE A_WR_ZERO VDD VSS / RM_IHPSG13_256x16_c2_1P_BLDRV +XA_BLTMUX<13> A_BLC<13> A_BLC_SEL A_BLT<13> A_BLT_SEL A_PRE_N A_SEL_P<13> ++ A_WR_ONE A_WR_ZERO VDD VSS / RM_IHPSG13_256x16_c2_1P_BLDRV +XA_BLTMUX<12> A_BLC<12> A_BLC_SEL A_BLT<12> A_BLT_SEL A_PRE_N A_SEL_P<12> ++ A_WR_ONE A_WR_ZERO VDD VSS / RM_IHPSG13_256x16_c2_1P_BLDRV +XA_BLTMUX<11> A_BLC<11> A_BLC_SEL A_BLT<11> A_BLT_SEL A_PRE_N A_SEL_P<11> ++ A_WR_ONE A_WR_ZERO VDD VSS / RM_IHPSG13_256x16_c2_1P_BLDRV +XA_BLTMUX<10> A_BLC<10> A_BLC_SEL A_BLT<10> A_BLT_SEL A_PRE_N A_SEL_P<10> ++ A_WR_ONE A_WR_ZERO VDD VSS / RM_IHPSG13_256x16_c2_1P_BLDRV +XA_BLTMUX<9> A_BLC<9> A_BLC_SEL A_BLT<9> A_BLT_SEL A_PRE_N A_SEL_P<9> A_WR_ONE ++ A_WR_ZERO VDD VSS / RM_IHPSG13_256x16_c2_1P_BLDRV +XA_BLTMUX<8> A_BLC<8> A_BLC_SEL A_BLT<8> A_BLT_SEL A_PRE_N A_SEL_P<8> A_WR_ONE ++ A_WR_ZERO VDD VSS / RM_IHPSG13_256x16_c2_1P_BLDRV +XA_BLTMUX<7> A_BLC<7> A_BLC_SEL A_BLT<7> A_BLT_SEL A_PRE_N A_SEL_P<7> A_WR_ONE ++ A_WR_ZERO VDD VSS / RM_IHPSG13_256x16_c2_1P_BLDRV +XA_BLTMUX<6> A_BLC<6> A_BLC_SEL A_BLT<6> A_BLT_SEL A_PRE_N A_SEL_P<6> A_WR_ONE ++ A_WR_ZERO VDD VSS / RM_IHPSG13_256x16_c2_1P_BLDRV +XA_BLTMUX<5> A_BLC<5> A_BLC_SEL A_BLT<5> A_BLT_SEL A_PRE_N A_SEL_P<5> A_WR_ONE ++ A_WR_ZERO VDD VSS / RM_IHPSG13_256x16_c2_1P_BLDRV +XA_BLTMUX<4> A_BLC<4> A_BLC_SEL A_BLT<4> A_BLT_SEL A_PRE_N A_SEL_P<4> A_WR_ONE ++ A_WR_ZERO VDD VSS / RM_IHPSG13_256x16_c2_1P_BLDRV +XA_BLTMUX<3> A_BLC<3> A_BLC_SEL A_BLT<3> A_BLT_SEL A_PRE_N A_SEL_P<3> A_WR_ONE ++ A_WR_ZERO VDD VSS / RM_IHPSG13_256x16_c2_1P_BLDRV +XA_BLTMUX<2> A_BLC<2> A_BLC_SEL A_BLT<2> A_BLT_SEL A_PRE_N A_SEL_P<2> A_WR_ONE ++ A_WR_ZERO VDD VSS / RM_IHPSG13_256x16_c2_1P_BLDRV +XA_BLTMUX<1> A_BLC<1> A_BLC_SEL A_BLT<1> A_BLT_SEL A_PRE_N A_SEL_P<1> A_WR_ONE ++ A_WR_ZERO VDD VSS / RM_IHPSG13_256x16_c2_1P_BLDRV +XA_BLTMUX<0> A_BLC<0> A_BLC_SEL A_BLT<0> A_BLT_SEL A_PRE_N A_SEL_P<0> A_WR_ONE ++ A_WR_ZERO VDD VSS / RM_IHPSG13_256x16_c2_1P_BLDRV +XA_CAPS<17> VDD VSS / RSC_IHPSG13_FILLCAP4 +XA_CAPS<16> VDD VSS / RSC_IHPSG13_FILLCAP4 +XA_CAPS<15> VDD VSS / RSC_IHPSG13_FILLCAP4 +XA_CAPS<14> VDD VSS / RSC_IHPSG13_FILLCAP4 +XA_CAPS<13> VDD VSS / RSC_IHPSG13_FILLCAP4 +XA_CAPS<12> VDD VSS / RSC_IHPSG13_FILLCAP4 +XA_CAPS<11> VDD VSS / RSC_IHPSG13_FILLCAP4 +XA_CAPS<10> VDD VSS / RSC_IHPSG13_FILLCAP4 +XA_CAPS<9> VDD VSS / RSC_IHPSG13_FILLCAP4 +XA_CAPS<8> VDD VSS / RSC_IHPSG13_FILLCAP4 +XA_CAPS<7> VDD VSS / RSC_IHPSG13_FILLCAP4 +XA_CAPS<6> VDD VSS / RSC_IHPSG13_FILLCAP4 +XA_CAPS<5> VDD VSS / RSC_IHPSG13_FILLCAP4 +XA_CAPS<4> VDD VSS / RSC_IHPSG13_FILLCAP4 +XA_CAPS<3> VDD VSS / RSC_IHPSG13_FILLCAP4 +XA_CAPS<2> VDD VSS / RSC_IHPSG13_FILLCAP4 +XA_CAPS<1> VDD VSS / RSC_IHPSG13_FILLCAP4 +XA_I51 net19 A_DR_O VDD VSS / RSC_IHPSG13_INVX4 +XA_I78 A_RCLK_B_L A_SAE VDD VSS / RSC_IHPSG13_CBUFX2 +XA_I69 A_DCLK_L A_DCLK_B_L VDD VSS / RSC_IHPSG13_CINVX8 +XA_I50 A_WCLK_L A_WCLK_B_L VDD VSS / RSC_IHPSG13_CINVX8 +XA_EBUF A_RCLK_L A_RCLK_B_L VDD VSS / RSC_IHPSG13_CINVX8 +XA_I76 A_DI_N A_DO_WRITE_P A_WR_ZERO VDD VSS / RSC_IHPSG13_AND2X6 +XA_I75 A_DI_R A_DO_WRITE_P A_WR_ONE VDD VSS / RSC_IHPSG13_AND2X6 +XA_I83 A_BM_R A_BM_N VDD VSS / RSC_IHPSG13_INVX2 +XA_DEC3INV<31> net23<0> A_SEL_P<31> VDD VSS / RSC_IHPSG13_INVX2 +XA_DEC3INV<30> net23<1> A_SEL_P<30> VDD VSS / RSC_IHPSG13_INVX2 +XA_DEC3INV<29> net23<2> A_SEL_P<29> VDD VSS / RSC_IHPSG13_INVX2 +XA_DEC3INV<28> net23<3> A_SEL_P<28> VDD VSS / RSC_IHPSG13_INVX2 +XA_DEC3INV<27> net23<4> A_SEL_P<27> VDD VSS / RSC_IHPSG13_INVX2 +XA_DEC3INV<26> net23<5> A_SEL_P<26> VDD VSS / RSC_IHPSG13_INVX2 +XA_DEC3INV<25> net23<6> A_SEL_P<25> VDD VSS / RSC_IHPSG13_INVX2 +XA_DEC3INV<24> net23<7> A_SEL_P<24> VDD VSS / RSC_IHPSG13_INVX2 +XA_DEC3INV<23> net23<8> A_SEL_P<23> VDD VSS / RSC_IHPSG13_INVX2 +XA_DEC3INV<22> net23<9> A_SEL_P<22> VDD VSS / RSC_IHPSG13_INVX2 +XA_DEC3INV<21> net23<10> A_SEL_P<21> VDD VSS / RSC_IHPSG13_INVX2 +XA_DEC3INV<20> net23<11> A_SEL_P<20> VDD VSS / RSC_IHPSG13_INVX2 +XA_DEC3INV<19> net23<12> A_SEL_P<19> VDD VSS / RSC_IHPSG13_INVX2 +XA_DEC3INV<18> net23<13> A_SEL_P<18> VDD VSS / RSC_IHPSG13_INVX2 +XA_DEC3INV<17> net23<14> A_SEL_P<17> VDD VSS / RSC_IHPSG13_INVX2 +XA_DEC3INV<16> net23<15> A_SEL_P<16> VDD VSS / RSC_IHPSG13_INVX2 +XA_DEC3INV<15> net23<16> A_SEL_P<15> VDD VSS / RSC_IHPSG13_INVX2 +XA_DEC3INV<14> net23<17> A_SEL_P<14> VDD VSS / RSC_IHPSG13_INVX2 +XA_DEC3INV<13> net23<18> A_SEL_P<13> VDD VSS / RSC_IHPSG13_INVX2 +XA_DEC3INV<12> net23<19> A_SEL_P<12> VDD VSS / RSC_IHPSG13_INVX2 +XA_DEC3INV<11> net23<20> A_SEL_P<11> VDD VSS / RSC_IHPSG13_INVX2 +XA_DEC3INV<10> net23<21> A_SEL_P<10> VDD VSS / RSC_IHPSG13_INVX2 +XA_DEC3INV<9> net23<22> A_SEL_P<9> VDD VSS / RSC_IHPSG13_INVX2 +XA_DEC3INV<8> net23<23> A_SEL_P<8> VDD VSS / RSC_IHPSG13_INVX2 +XA_DEC3INV<7> net23<24> A_SEL_P<7> VDD VSS / RSC_IHPSG13_INVX2 +XA_DEC3INV<6> net23<25> A_SEL_P<6> VDD VSS / RSC_IHPSG13_INVX2 +XA_DEC3INV<5> net23<26> A_SEL_P<5> VDD VSS / RSC_IHPSG13_INVX2 +XA_DEC3INV<4> net23<27> A_SEL_P<4> VDD VSS / RSC_IHPSG13_INVX2 +XA_DEC3INV<3> net23<28> A_SEL_P<3> VDD VSS / RSC_IHPSG13_INVX2 +XA_DEC3INV<2> net23<29> A_SEL_P<2> VDD VSS / RSC_IHPSG13_INVX2 +XA_DEC3INV<1> net23<30> A_SEL_P<1> VDD VSS / RSC_IHPSG13_INVX2 +XA_DEC3INV<0> net23<31> A_SEL_P<0> VDD VSS / RSC_IHPSG13_INVX2 +XA_I49 A_DI_R A_DI_N VDD VSS / RSC_IHPSG13_INVX2 +XA_ISENSE A_SAE A_BLC_SEL A_BLT_SEL net19 net20 VDD VSS / ++ RSC_IHPSG13_DFPQD_MSAFFX2 +XA_DREG A_BIST_EN_I A_BIST_DW_I A_DCLK_B_L A_DW_I A_DI_R net22 VDD VSS ++ / RSC_IHPSG13_DFNQMX2IX1 +XA_BREG A_BIST_EN_I A_BIST_BM_I A_DCLK_B_L A_BM_I A_BM_R net21 VDD VSS ++ / RSC_IHPSG13_DFNQMX2IX1 +XA_DEC3<31> A_P1<1> A_P0<1> A_ADDR_DEC<7> net23<0> VDD VSS / ++ RSC_IHPSG13_NAND3X2 +XA_DEC3<30> A_P1<1> A_P0<1> A_ADDR_DEC<6> net23<1> VDD VSS / ++ RSC_IHPSG13_NAND3X2 +XA_DEC3<29> A_P1<1> A_P0<1> A_ADDR_DEC<5> net23<2> VDD VSS / ++ RSC_IHPSG13_NAND3X2 +XA_DEC3<28> A_P1<1> A_P0<1> A_ADDR_DEC<4> net23<3> VDD VSS / ++ RSC_IHPSG13_NAND3X2 +XA_DEC3<27> A_P1<1> A_P0<1> A_ADDR_DEC<3> net23<4> VDD VSS / ++ RSC_IHPSG13_NAND3X2 +XA_DEC3<26> A_P1<1> A_P0<1> A_ADDR_DEC<2> net23<5> VDD VSS / ++ RSC_IHPSG13_NAND3X2 +XA_DEC3<25> A_P1<1> A_P0<1> A_ADDR_DEC<1> net23<6> VDD VSS / ++ RSC_IHPSG13_NAND3X2 +XA_DEC3<24> A_P1<1> A_P0<1> A_ADDR_DEC<0> net23<7> VDD VSS / ++ RSC_IHPSG13_NAND3X2 +XA_DEC3<23> A_P1<1> A_N0<1> A_ADDR_DEC<7> net23<8> VDD VSS / ++ RSC_IHPSG13_NAND3X2 +XA_DEC3<22> A_P1<1> A_N0<1> A_ADDR_DEC<6> net23<9> VDD VSS / ++ RSC_IHPSG13_NAND3X2 +XA_DEC3<21> A_P1<1> A_N0<1> A_ADDR_DEC<5> net23<10> VDD VSS / ++ RSC_IHPSG13_NAND3X2 +XA_DEC3<20> A_P1<1> A_N0<1> A_ADDR_DEC<4> net23<11> VDD VSS / ++ RSC_IHPSG13_NAND3X2 +XA_DEC3<19> A_P1<1> A_N0<1> A_ADDR_DEC<3> net23<12> VDD VSS / ++ RSC_IHPSG13_NAND3X2 +XA_DEC3<18> A_P1<1> A_N0<1> A_ADDR_DEC<2> net23<13> VDD VSS / ++ RSC_IHPSG13_NAND3X2 +XA_DEC3<17> A_P1<1> A_N0<1> A_ADDR_DEC<1> net23<14> VDD VSS / ++ RSC_IHPSG13_NAND3X2 +XA_DEC3<16> A_P1<1> A_N0<1> A_ADDR_DEC<0> net23<15> VDD VSS / ++ RSC_IHPSG13_NAND3X2 +XA_DEC3<15> A_N1<0> A_P0<0> A_ADDR_DEC<7> net23<16> VDD VSS / ++ RSC_IHPSG13_NAND3X2 +XA_DEC3<14> A_N1<0> A_P0<0> A_ADDR_DEC<6> net23<17> VDD VSS / ++ RSC_IHPSG13_NAND3X2 +XA_DEC3<13> A_N1<0> A_P0<0> A_ADDR_DEC<5> net23<18> VDD VSS / ++ RSC_IHPSG13_NAND3X2 +XA_DEC3<12> A_N1<0> A_P0<0> A_ADDR_DEC<4> net23<19> VDD VSS / ++ RSC_IHPSG13_NAND3X2 +XA_DEC3<11> A_N1<0> A_P0<0> A_ADDR_DEC<3> net23<20> VDD VSS / ++ RSC_IHPSG13_NAND3X2 +XA_DEC3<10> A_N1<0> A_P0<0> A_ADDR_DEC<2> net23<21> VDD VSS / ++ RSC_IHPSG13_NAND3X2 +XA_DEC3<9> A_N1<0> A_P0<0> A_ADDR_DEC<1> net23<22> VDD VSS / ++ RSC_IHPSG13_NAND3X2 +XA_DEC3<8> A_N1<0> A_P0<0> A_ADDR_DEC<0> net23<23> VDD VSS / ++ RSC_IHPSG13_NAND3X2 +XA_DEC3<7> A_N1<0> A_N0<0> A_ADDR_DEC<7> net23<24> VDD VSS / ++ RSC_IHPSG13_NAND3X2 +XA_DEC3<6> A_N1<0> A_N0<0> A_ADDR_DEC<6> net23<25> VDD VSS / ++ RSC_IHPSG13_NAND3X2 +XA_DEC3<5> A_N1<0> A_N0<0> A_ADDR_DEC<5> net23<26> VDD VSS / ++ RSC_IHPSG13_NAND3X2 +XA_DEC3<4> A_N1<0> A_N0<0> A_ADDR_DEC<4> net23<27> VDD VSS / ++ RSC_IHPSG13_NAND3X2 +XA_DEC3<3> A_N1<0> A_N0<0> A_ADDR_DEC<3> net23<28> VDD VSS / ++ RSC_IHPSG13_NAND3X2 +XA_DEC3<2> A_N1<0> A_N0<0> A_ADDR_DEC<2> net23<29> VDD VSS / ++ RSC_IHPSG13_NAND3X2 +XA_DEC3<1> A_N1<0> A_N0<0> A_ADDR_DEC<1> net23<30> VDD VSS / ++ RSC_IHPSG13_NAND3X2 +XA_DEC3<0> A_N1<0> A_N0<0> A_ADDR_DEC<0> net23<31> VDD VSS / ++ RSC_IHPSG13_NAND3X2 +XA_I89 A_DCLK_B_L A_DCLK_B_R / RSC_IHPSG13_MET3RES +XA_I91 A_RCLK_B_L A_RCLK_B_R / RSC_IHPSG13_MET3RES +XA_I90 A_WCLK_B_L A_WCLK_B_R / RSC_IHPSG13_MET3RES +XA_I88 A_DCLK_L A_DCLK_R / RSC_IHPSG13_MET3RES +XA_I87 A_WCLK_L A_WCLK_R / RSC_IHPSG13_MET3RES +XA_R2 A_RCLK_L A_RCLK_R / RSC_IHPSG13_MET3RES +XA_BM_TIEH A_TIEH_O VDD VSS / RSC_IHPSG13_TIEH +.ENDS + +.SUBCKT RM_IHPSG13_256x16_c2_1P_COLDRV13X12 ADDR_COL_I<1> ADDR_COL_I<0> ADDR_COL_O<1> ++ ADDR_COL_O<0> ADDR_DEC_I<7> ADDR_DEC_I<6> ADDR_DEC_I<5> ADDR_DEC_I<4> ++ ADDR_DEC_I<3> ADDR_DEC_I<2> ADDR_DEC_I<1> ADDR_DEC_I<0> ADDR_DEC_O<7> ++ ADDR_DEC_O<6> ADDR_DEC_O<5> ADDR_DEC_O<4> ADDR_DEC_O<3> ADDR_DEC_O<2> ++ ADDR_DEC_O<1> ADDR_DEC_O<0> DCLK_I DCLK_O RCLK_I RCLK_O WCLK_I WCLK_O ++ VDD VSS +XI1<1> VDD VSS / RSC_IHPSG13_FILLCAP4 +XI1<0> VDD VSS / RSC_IHPSG13_FILLCAP4 +XI0<1> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI0<0> VDD VSS / RSC_IHPSG13_FILLCAP8 +XADDR_COL_DRV<1> ADDR_COL_I<1> ADDR_COL_O<1> VDD VSS / ++ RSC_IHPSG13_CBUFX12 +XADDR_COL_DRV<0> ADDR_COL_I<0> ADDR_COL_O<0> VDD VSS / ++ RSC_IHPSG13_CBUFX12 +XADDR_DEC_DRV<7> ADDR_DEC_I<7> ADDR_DEC_O<7> VDD VSS / ++ RSC_IHPSG13_CBUFX12 +XADDR_DEC_DRV<6> ADDR_DEC_I<6> ADDR_DEC_O<6> VDD VSS / ++ RSC_IHPSG13_CBUFX12 +XADDR_DEC_DRV<5> ADDR_DEC_I<5> ADDR_DEC_O<5> VDD VSS / ++ RSC_IHPSG13_CBUFX12 +XADDR_DEC_DRV<4> ADDR_DEC_I<4> ADDR_DEC_O<4> VDD VSS / ++ RSC_IHPSG13_CBUFX12 +XADDR_DEC_DRV<3> ADDR_DEC_I<3> ADDR_DEC_O<3> VDD VSS / ++ RSC_IHPSG13_CBUFX12 +XADDR_DEC_DRV<2> ADDR_DEC_I<2> ADDR_DEC_O<2> VDD VSS / ++ RSC_IHPSG13_CBUFX12 +XADDR_DEC_DRV<1> ADDR_DEC_I<1> ADDR_DEC_O<1> VDD VSS / ++ RSC_IHPSG13_CBUFX12 +XADDR_DEC_DRV<0> ADDR_DEC_I<0> ADDR_DEC_O<0> VDD VSS / ++ RSC_IHPSG13_CBUFX12 +XDCLK_DRV DCLK_I DCLK_O VDD VSS / RSC_IHPSG13_CBUFX12 +XRCLK_DRV RCLK_I RCLK_O VDD VSS / RSC_IHPSG13_CBUFX12 +XWCLK_DRV WCLK_I WCLK_O VDD VSS / RSC_IHPSG13_CBUFX12 +.ENDS +.SUBCKT RM_IHPSG13_256x16_c2_1P_WLDRV16X12 A<15> A<14> A<13> A<12> A<11> A<10> A<9> A<8> ++ A<7> A<6> A<5> A<4> A<3> A<2> A<1> A<0> Z<15> Z<14> Z<13> Z<12> Z<11> Z<10> ++ Z<9> Z<8> Z<7> Z<6> Z<5> Z<4> Z<3> Z<2> Z<1> Z<0> VDD VSS +XBUF<15> A<15> Z<15> VDD VSS / RSC_IHPSG13_WLDRVX12 +XBUF<14> A<14> Z<14> VDD VSS / RSC_IHPSG13_WLDRVX12 +XBUF<13> A<13> Z<13> VDD VSS / RSC_IHPSG13_WLDRVX12 +XBUF<12> A<12> Z<12> VDD VSS / RSC_IHPSG13_WLDRVX12 +XBUF<11> A<11> Z<11> VDD VSS / RSC_IHPSG13_WLDRVX12 +XBUF<10> A<10> Z<10> VDD VSS / RSC_IHPSG13_WLDRVX12 +XBUF<9> A<9> Z<9> VDD VSS / RSC_IHPSG13_WLDRVX12 +XBUF<8> A<8> Z<8> VDD VSS / RSC_IHPSG13_WLDRVX12 +XBUF<7> A<7> Z<7> VDD VSS / RSC_IHPSG13_WLDRVX12 +XBUF<6> A<6> Z<6> VDD VSS / RSC_IHPSG13_WLDRVX12 +XBUF<5> A<5> Z<5> VDD VSS / RSC_IHPSG13_WLDRVX12 +XBUF<4> A<4> Z<4> VDD VSS / RSC_IHPSG13_WLDRVX12 +XBUF<3> A<3> Z<3> VDD VSS / RSC_IHPSG13_WLDRVX12 +XBUF<2> A<2> Z<2> VDD VSS / RSC_IHPSG13_WLDRVX12 +XBUF<1> A<1> Z<1> VDD VSS / RSC_IHPSG13_WLDRVX12 +XBUF<0> A<0> Z<0> VDD VSS / RSC_IHPSG13_WLDRVX12 +.ENDS + + + +.SUBCKT RM_IHPSG13_256x16_c2_2P_COLDRV13X8 ADDR_COL_I<1> ADDR_COL_I<0> ADDR_COL_O<1> ++ ADDR_COL_O<0> ADDR_DEC_I<7> ADDR_DEC_I<6> ADDR_DEC_I<5> ADDR_DEC_I<4> ++ ADDR_DEC_I<3> ADDR_DEC_I<2> ADDR_DEC_I<1> ADDR_DEC_I<0> ADDR_DEC_O<7> ++ ADDR_DEC_O<6> ADDR_DEC_O<5> ADDR_DEC_O<4> ADDR_DEC_O<3> ADDR_DEC_O<2> ++ ADDR_DEC_O<1> ADDR_DEC_O<0> DCLK_I DCLK_O RCLK_I RCLK_O WCLK_I WCLK_O ++ VDD VSS +XI0<5> VDD VSS / RSC_IHPSG13_FILLCAP4 +XI0<4> VDD VSS / RSC_IHPSG13_FILLCAP4 +XI0<3> VDD VSS / RSC_IHPSG13_FILLCAP4 +XI0<2> VDD VSS / RSC_IHPSG13_FILLCAP4 +XI0<1> VDD VSS / RSC_IHPSG13_FILLCAP4 +XWCLK_DRV WCLK_I WCLK_O VDD VSS / RSC_IHPSG13_CBUFX8 +XRCLK_DRV RCLK_I RCLK_O VDD VSS / RSC_IHPSG13_CBUFX8 +XDCLK_DRV DCLK_I DCLK_O VDD VSS / RSC_IHPSG13_CBUFX8 +XADDR_COL_DRV<1> ADDR_COL_I<1> ADDR_COL_O<1> VDD VSS / ++ RSC_IHPSG13_CBUFX8 +XADDR_COL_DRV<0> ADDR_COL_I<0> ADDR_COL_O<0> VDD VSS / ++ RSC_IHPSG13_CBUFX8 +XADDR_DEC_DRV<7> ADDR_DEC_I<7> ADDR_DEC_O<7> VDD VSS / ++ RSC_IHPSG13_CBUFX8 +XADDR_DEC_DRV<6> ADDR_DEC_I<6> ADDR_DEC_O<6> VDD VSS / ++ RSC_IHPSG13_CBUFX8 +XADDR_DEC_DRV<5> ADDR_DEC_I<5> ADDR_DEC_O<5> VDD VSS / ++ RSC_IHPSG13_CBUFX8 +XADDR_DEC_DRV<4> ADDR_DEC_I<4> ADDR_DEC_O<4> VDD VSS / ++ RSC_IHPSG13_CBUFX8 +XADDR_DEC_DRV<3> ADDR_DEC_I<3> ADDR_DEC_O<3> VDD VSS / ++ RSC_IHPSG13_CBUFX8 +XADDR_DEC_DRV<2> ADDR_DEC_I<2> ADDR_DEC_O<2> VDD VSS / ++ RSC_IHPSG13_CBUFX8 +XADDR_DEC_DRV<1> ADDR_DEC_I<1> ADDR_DEC_O<1> VDD VSS / ++ RSC_IHPSG13_CBUFX8 +XADDR_DEC_DRV<0> ADDR_DEC_I<0> ADDR_DEC_O<0> VDD VSS / ++ RSC_IHPSG13_CBUFX8 +XI1<3> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI1<2> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI1<1> VDD VSS / RSC_IHPSG13_FILLCAP8 +.ENDS +.SUBCKT RSC_IHPSG13_WLDRVX8 A Z VDD VSS +MN1 Z net6 VSS VSS sg13_lv_nmos m=1 w=1.41u l=130.00n ng=2 nrd=0 nrs=0 +MN0 net6 A VSS VSS sg13_lv_nmos m=1 w=1.8u l=130.00n ng=2 nrd=0 nrs=0 +MP1 Z net6 VDD VDD sg13_lv_pmos m=1 w=6.48u l=130.00n ng=4 nrd=0 nrs=0 +MP0 net6 A VDD VDD sg13_lv_pmos m=1 w=900.0n l=130.00n ng=1 nrd=0 nrs=0 +.ENDS +.SUBCKT RM_IHPSG13_256x16_c2_2P_WLDRV16X8 A<15> A<14> A<13> A<12> A<11> A<10> A<9> A<8> ++ A<7> A<6> A<5> A<4> A<3> A<2> A<1> A<0> Z<15> Z<14> Z<13> Z<12> Z<11> Z<10> ++ Z<9> Z<8> Z<7> Z<6> Z<5> Z<4> Z<3> Z<2> Z<1> Z<0> VDD VSS +XBUF<15> A<15> Z<15> VDD VSS / RSC_IHPSG13_WLDRVX8 +XBUF<14> A<14> Z<14> VDD VSS / RSC_IHPSG13_WLDRVX8 +XBUF<13> A<13> Z<13> VDD VSS / RSC_IHPSG13_WLDRVX8 +XBUF<12> A<12> Z<12> VDD VSS / RSC_IHPSG13_WLDRVX8 +XBUF<11> A<11> Z<11> VDD VSS / RSC_IHPSG13_WLDRVX8 +XBUF<10> A<10> Z<10> VDD VSS / RSC_IHPSG13_WLDRVX8 +XBUF<9> A<9> Z<9> VDD VSS / RSC_IHPSG13_WLDRVX8 +XBUF<8> A<8> Z<8> VDD VSS / RSC_IHPSG13_WLDRVX8 +XBUF<7> A<7> Z<7> VDD VSS / RSC_IHPSG13_WLDRVX8 +XBUF<6> A<6> Z<6> VDD VSS / RSC_IHPSG13_WLDRVX8 +XBUF<5> A<5> Z<5> VDD VSS / RSC_IHPSG13_WLDRVX8 +XBUF<4> A<4> Z<4> VDD VSS / RSC_IHPSG13_WLDRVX8 +XBUF<3> A<3> Z<3> VDD VSS / RSC_IHPSG13_WLDRVX8 +XBUF<2> A<2> Z<2> VDD VSS / RSC_IHPSG13_WLDRVX8 +XBUF<1> A<1> Z<1> VDD VSS / RSC_IHPSG13_WLDRVX8 +XBUF<0> A<0> Z<0> VDD VSS / RSC_IHPSG13_WLDRVX8 +.ENDS + + + +.SUBCKT RM_IHPSG13_256x16_c2_2P_COLDEC2 ACLK_N ADDR<1> ADDR<0> ADDR_COL<1> ADDR_COL<0> ++ ADDR_DEC<7> ADDR_DEC<6> ADDR_DEC<5> ADDR_DEC<4> ADDR_DEC<3> ADDR_DEC<2> ++ ADDR_DEC<1> ADDR_DEC<0> BIST_ADDR<1> BIST_ADDR<0> BIST_EN_I VDD VSS +XI16<17> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI16<16> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI16<15> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI16<14> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI16<13> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI16<12> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI16<11> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI16<10> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI16<9> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI16<8> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI16<7> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI16<6> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI16<5> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI16<4> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI16<3> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI16<2> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI16<1> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI18<24> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI18<23> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI18<22> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI18<21> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI18<20> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI18<19> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI18<18> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI18<17> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI18<16> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI18<15> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI18<14> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI18<13> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI18<12> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI18<11> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI18<10> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI18<9> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI18<8> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI18<7> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI18<6> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI18<5> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI18<4> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI18<3> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI18<2> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI18<1> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI1<3> PADR<0> PADR<1> addr_n<3> VDD VSS / RSC_IHPSG13_NAND2X2 +XI1<2> NADR<0> PADR<1> addr_n<2> VDD VSS / RSC_IHPSG13_NAND2X2 +XI1<1> PADR<0> NADR<1> addr_n<1> VDD VSS / RSC_IHPSG13_NAND2X2 +XI1<0> NADR<0> NADR<1> addr_n<0> VDD VSS / RSC_IHPSG13_NAND2X2 +XI17<1> ADDR_COL<1> VDD VSS / RSC_IHPSG13_TIEL +XI17<0> ADDR_COL<0> VDD VSS / RSC_IHPSG13_TIEL +XI14<3> ADDR_DEC<7> VDD VSS / RSC_IHPSG13_TIEL +XI14<2> ADDR_DEC<6> VDD VSS / RSC_IHPSG13_TIEL +XI14<1> ADDR_DEC<5> VDD VSS / RSC_IHPSG13_TIEL +XI14<0> ADDR_DEC<4> VDD VSS / RSC_IHPSG13_TIEL +XI13<1> NADR<1> PADR<1> VDD VSS / RSC_IHPSG13_INVX2 +XI13<0> NADR<0> PADR<0> VDD VSS / RSC_IHPSG13_INVX2 +XI3<1> padr_int<1> NADR<1> VDD VSS / RSC_IHPSG13_INVX2 +XI3<0> padr_int<0> NADR<0> VDD VSS / RSC_IHPSG13_INVX2 +XI2<3> addr_n<3> ADDR_DEC<3> VDD VSS / RSC_IHPSG13_INVX2 +XI2<2> addr_n<2> ADDR_DEC<2> VDD VSS / RSC_IHPSG13_INVX2 +XI2<1> addr_n<1> ADDR_DEC<1> VDD VSS / RSC_IHPSG13_INVX2 +XI2<0> addr_n<0> ADDR_DEC<0> VDD VSS / RSC_IHPSG13_INVX2 +XDFF<1> BIST_EN_I BIST_ADDR<1> ACLK_N ADDR<1> padr_int<1> net12<0> VDD ++ VSS / RSC_IHPSG13_DFNQMX2IX1 +XDFF<0> BIST_EN_I BIST_ADDR<0> ACLK_N ADDR<0> padr_int<0> net12<1> VDD ++ VSS / RSC_IHPSG13_DFNQMX2IX1 +XI15<5> VDD VSS / RSC_IHPSG13_FILLCAP4 +XI15<4> VDD VSS / RSC_IHPSG13_FILLCAP4 +XI15<3> VDD VSS / RSC_IHPSG13_FILLCAP4 +XI15<2> VDD VSS / RSC_IHPSG13_FILLCAP4 +XI15<1> VDD VSS / RSC_IHPSG13_FILLCAP4 +XI19<4> VDD VSS / RSC_IHPSG13_FILLCAP4 +XI19<3> VDD VSS / RSC_IHPSG13_FILLCAP4 +XI19<2> VDD VSS / RSC_IHPSG13_FILLCAP4 +XI19<1> VDD VSS / RSC_IHPSG13_FILLCAP4 +.ENDS +.SUBCKT RM_IHPSG13_256x16_c2_2P_COLCTRL2 A_ADDR_DEC<3> A_ADDR_DEC<2> A_ADDR_DEC<1> ++ A_ADDR_DEC<0> A_BIST_BM_I A_BIST_DW_I A_BIST_EN_I A_BLC<3> A_BLC<2> A_BLC<1> ++ A_BLC<0> A_BLT<3> A_BLT<2> A_BLT<1> A_BLT<0> A_BM_I A_DCLK_B_L A_DCLK_B_R ++ A_DCLK_L A_DCLK_R A_DR_O A_DW_I A_RCLK_B_L A_RCLK_B_R A_RCLK_L A_RCLK_R ++ A_TIEH_O A_WCLK_B_L A_WCLK_B_R A_WCLK_L A_WCLK_R B_ADDR_DEC<3> B_ADDR_DEC<2> ++ B_ADDR_DEC<1> B_ADDR_DEC<0> B_BIST_BM_I B_BIST_DW_I B_BIST_EN_I B_BLC<3> ++ B_BLC<2> B_BLC<1> B_BLC<0> B_BLT<3> B_BLT<2> B_BLT<1> B_BLT<0> B_BM_I ++ B_DCLK_B_L B_DCLK_B_R B_DCLK_L B_DCLK_R B_DR_O B_DW_I B_RCLK_B_L B_RCLK_B_R ++ B_RCLK_L B_RCLK_R B_TIEH_O B_WCLK_B_L B_WCLK_B_R B_WCLK_L B_WCLK_R VDD ++ VSS +XB_DREG B_BIST_EN_I B_BIST_DW_I B_DCLK_B_L B_DW_I B_DI_R net046 VDD ++ VSS / RSC_IHPSG13_DFNQMX2IX1 +XB_BREG B_BIST_EN_I B_BIST_BM_I B_DCLK_B_L B_BM_I B_BM_R net045 VDD ++ VSS / RSC_IHPSG13_DFNQMX2IX1 +XA_DREG A_BIST_EN_I A_BIST_DW_I A_DCLK_B_L A_DW_I A_DI_R net22 VDD VSS ++ / RSC_IHPSG13_DFNQMX2IX1 +XA_BREG A_BIST_EN_I A_BIST_BM_I A_DCLK_B_L A_BM_I A_BM_R net23 VDD VSS ++ / RSC_IHPSG13_DFNQMX2IX1 +XB_CAPS VDD VSS / RSC_IHPSG13_FILLCAP4 +XA_CAPS VDD VSS / RSC_IHPSG13_FILLCAP4 +XB_I75 B_DI_R B_DO_WRITE_P B_WR_ONE VDD VSS / RSC_IHPSG13_AND2X2 +XB_I80 B_RCLK_B_L B_WCLK_B_L net041 VDD VSS / RSC_IHPSG13_AND2X2 +XB_I76 B_DI_N B_DO_WRITE_P B_WR_ZERO VDD VSS / RSC_IHPSG13_AND2X2 +XA_I80 A_RCLK_B_L A_WCLK_B_L net21 VDD VSS / RSC_IHPSG13_AND2X2 +XA_I75 A_DI_R A_DO_WRITE_P A_WR_ONE VDD VSS / RSC_IHPSG13_AND2X2 +XA_I76 A_DI_N A_DO_WRITE_P A_WR_ZERO VDD VSS / RSC_IHPSG13_AND2X2 +XB_I44 B_WCLK_B_L B_BM_N B_DO_WRITE_P VDD VSS / RSC_IHPSG13_NOR2X2 +XA_I44 A_WCLK_B_L A_BM_N A_DO_WRITE_P VDD VSS / RSC_IHPSG13_NOR2X2 +XB_I81 net041 B_PRE_N VDD VSS / RSC_IHPSG13_CINVX4_WN +XA_I81 net21 A_PRE_N VDD VSS / RSC_IHPSG13_CINVX4_WN +XB_BM_TIEH B_TIEH_O VDD VSS / RSC_IHPSG13_TIEH +XA_BM_TIEH A_TIEH_O VDD VSS / RSC_IHPSG13_TIEH +XA_I89 A_DCLK_B_L A_DCLK_B_R / RSC_IHPSG13_MET3RES +XA_I88 A_DCLK_L A_DCLK_R / RSC_IHPSG13_MET3RES +XA_I87 A_WCLK_L A_WCLK_R / RSC_IHPSG13_MET3RES +XA_I91 A_RCLK_B_L A_RCLK_B_R / RSC_IHPSG13_MET3RES +XB_I87 B_WCLK_L B_WCLK_R / RSC_IHPSG13_MET3RES +XB_I88 B_DCLK_L B_DCLK_R / RSC_IHPSG13_MET3RES +XB_I89 B_DCLK_B_L B_DCLK_B_R / RSC_IHPSG13_MET3RES +XB_I90 B_WCLK_B_L B_WCLK_B_R / RSC_IHPSG13_MET3RES +XB_R2 B_RCLK_L B_RCLK_R / RSC_IHPSG13_MET3RES +XB_I91 B_RCLK_B_L B_RCLK_B_R / RSC_IHPSG13_MET3RES +XA_R2 A_RCLK_L A_RCLK_R / RSC_IHPSG13_MET3RES +XA_I90 A_WCLK_B_L A_WCLK_B_R / RSC_IHPSG13_MET3RES +XAB_BLMUX A_BLC<3> A_BLC<2> A_BLC<1> A_BLC<0> A_BLC_SEL A_BLT<3> A_BLT<2> ++ A_BLT<1> A_BLT<0> A_BLT_SEL A_PRE_N A_ADDR_DEC<3> A_ADDR_DEC<2> ++ A_ADDR_DEC<1> A_ADDR_DEC<0> A_WR_ONE A_WR_ZERO B_BLC<3> B_BLC<2> B_BLC<1> ++ B_BLC<0> B_BLC_SEL B_BLT<3> B_BLT<2> B_BLT<1> B_BLT<0> B_BLT_SEL B_PRE_N ++ B_ADDR_DEC<3> B_ADDR_DEC<2> B_ADDR_DEC<1> B_ADDR_DEC<0> B_WR_ONE B_WR_ZERO ++ VDD VSS / RM_IHPSG13_256x16_c2_2P_BLDRV +XB_ISENSE B_SAE B_BLC_SEL B_BLT_SEL net039 net040 VDD VSS / ++ RSC_IHPSG13_DFPQD_MSAFFX2 +XA_ISENSE A_SAE A_BLC_SEL A_BLT_SEL net19 net20 VDD VSS / ++ RSC_IHPSG13_DFPQD_MSAFFX2 +XB_I78 B_RCLK_B_L B_SAE VDD VSS / RSC_IHPSG13_CBUFX2 +XA_I78 A_RCLK_B_L A_SAE VDD VSS / RSC_IHPSG13_CBUFX2 +XB_I83 B_BM_R B_BM_N VDD VSS / RSC_IHPSG13_INVX2 +XB_I49 B_DI_R B_DI_N VDD VSS / RSC_IHPSG13_INVX2 +XA_I83 A_BM_R A_BM_N VDD VSS / RSC_IHPSG13_INVX2 +XA_I49 A_DI_R A_DI_N VDD VSS / RSC_IHPSG13_INVX2 +XB_I51 net039 B_DR_O VDD VSS / RSC_IHPSG13_INVX4 +XA_I51 net19 A_DR_O VDD VSS / RSC_IHPSG13_INVX4 +XA_I69 A_DCLK_L A_DCLK_B_L VDD VSS / RSC_IHPSG13_CINVX2 +XA_I50 A_WCLK_L A_WCLK_B_L VDD VSS / RSC_IHPSG13_CINVX2 +XA_EBUF A_RCLK_L A_RCLK_B_L VDD VSS / RSC_IHPSG13_CINVX2 +XB_EBUF B_RCLK_L B_RCLK_B_L VDD VSS / RSC_IHPSG13_CINVX2 +XB_I50 B_WCLK_L B_WCLK_B_L VDD VSS / RSC_IHPSG13_CINVX2 +XB_I69 B_DCLK_L B_DCLK_B_L VDD VSS / RSC_IHPSG13_CINVX2 +.ENDS +.SUBCKT RM_IHPSG13_256x16_c2_2P_COLDRV13_FILL4C2 VDD VSS +XI0<2> VDD VSS / RSC_IHPSG13_FILLCAP4 +XI0<1> VDD VSS / RSC_IHPSG13_FILLCAP4 +.ENDS + + +.SUBCKT RM_IHPSG13_256x16_c2_2P_ROWDEC7 ADDR_N_I<6> ADDR_N_I<5> ADDR_N_I<4> ADDR_N_I<3> ++ ADDR_N_I<2> ADDR_N_I<1> ADDR_N_I<0> CS_I ECLK_I WL_O<127> WL_O<126> ++ WL_O<125> WL_O<124> WL_O<123> WL_O<122> WL_O<121> WL_O<120> WL_O<119> ++ WL_O<118> WL_O<117> WL_O<116> WL_O<115> WL_O<114> WL_O<113> WL_O<112> ++ WL_O<111> WL_O<110> WL_O<109> WL_O<108> WL_O<107> WL_O<106> WL_O<105> ++ WL_O<104> WL_O<103> WL_O<102> WL_O<101> WL_O<100> WL_O<99> WL_O<98> WL_O<97> ++ WL_O<96> WL_O<95> WL_O<94> WL_O<93> WL_O<92> WL_O<91> WL_O<90> WL_O<89> ++ WL_O<88> WL_O<87> WL_O<86> WL_O<85> WL_O<84> WL_O<83> WL_O<82> WL_O<81> ++ WL_O<80> WL_O<79> WL_O<78> WL_O<77> WL_O<76> WL_O<75> WL_O<74> WL_O<73> ++ WL_O<72> WL_O<71> WL_O<70> WL_O<69> WL_O<68> WL_O<67> WL_O<66> WL_O<65> ++ WL_O<64> WL_O<63> WL_O<62> WL_O<61> WL_O<60> WL_O<59> WL_O<58> WL_O<57> ++ WL_O<56> WL_O<55> WL_O<54> WL_O<53> WL_O<52> WL_O<51> WL_O<50> WL_O<49> ++ WL_O<48> WL_O<47> WL_O<46> WL_O<45> WL_O<44> WL_O<43> WL_O<42> WL_O<41> ++ WL_O<40> WL_O<39> WL_O<38> WL_O<37> WL_O<36> WL_O<35> WL_O<34> WL_O<33> ++ WL_O<32> WL_O<31> WL_O<30> WL_O<29> WL_O<28> WL_O<27> WL_O<26> WL_O<25> ++ WL_O<24> WL_O<23> WL_O<22> WL_O<21> WL_O<20> WL_O<19> WL_O<18> WL_O<17> ++ WL_O<16> WL_O<15> WL_O<14> WL_O<13> WL_O<12> WL_O<11> WL_O<10> WL_O<9> ++ WL_O<8> WL_O<7> WL_O<6> WL_O<5> WL_O<4> WL_O<3> WL_O<2> WL_O<1> WL_O<0> ++ VDD VSS +XSEL<7> ADDR_N_I<3> ADDR_N_I<2> ADDR_N_I<1> ADDR_N_I<0> CS00<7> ECLK_H<7> ++ ECLK_H<8> ECLK_B<7> ECLK_B<8> WL_O<127> WL_O<126> WL_O<125> WL_O<124> ++ WL_O<123> WL_O<122> WL_O<121> WL_O<120> WL_O<119> WL_O<118> WL_O<117> ++ WL_O<116> WL_O<115> WL_O<114> WL_O<113> WL_O<112> VDD VSS / ++ RM_IHPSG13_256x16_c2_2P_DEC04 +XSEL<6> ADDR_N_I<3> ADDR_N_I<2> ADDR_N_I<1> ADDR_N_I<0> CS00<6> ECLK_H<6> ++ ECLK_H<7> ECLK_B<6> ECLK_B<7> WL_O<111> WL_O<110> WL_O<109> WL_O<108> ++ WL_O<107> WL_O<106> WL_O<105> WL_O<104> WL_O<103> WL_O<102> WL_O<101> ++ WL_O<100> WL_O<99> WL_O<98> WL_O<97> WL_O<96> VDD VSS / ++ RM_IHPSG13_256x16_c2_2P_DEC04 +XSEL<5> ADDR_N_I<3> ADDR_N_I<2> ADDR_N_I<1> ADDR_N_I<0> CS00<5> ECLK_H<5> ++ ECLK_H<6> ECLK_B<5> ECLK_B<6> WL_O<95> WL_O<94> WL_O<93> WL_O<92> WL_O<91> ++ WL_O<90> WL_O<89> WL_O<88> WL_O<87> WL_O<86> WL_O<85> WL_O<84> WL_O<83> ++ WL_O<82> WL_O<81> WL_O<80> VDD VSS / RM_IHPSG13_256x16_c2_2P_DEC04 +XSEL<4> ADDR_N_I<3> ADDR_N_I<2> ADDR_N_I<1> ADDR_N_I<0> CS00<4> ECLK_H<4> ++ ECLK_H<5> ECLK_B<4> ECLK_B<5> WL_O<79> WL_O<78> WL_O<77> WL_O<76> WL_O<75> ++ WL_O<74> WL_O<73> WL_O<72> WL_O<71> WL_O<70> WL_O<69> WL_O<68> WL_O<67> ++ WL_O<66> WL_O<65> WL_O<64> VDD VSS / RM_IHPSG13_256x16_c2_2P_DEC04 +XSEL<3> ADDR_N_I<3> ADDR_N_I<2> ADDR_N_I<1> ADDR_N_I<0> CS00<3> ECLK_H<3> ++ ECLK_H<4> ECLK_B<3> ECLK_B<4> WL_O<63> WL_O<62> WL_O<61> WL_O<60> WL_O<59> ++ WL_O<58> WL_O<57> WL_O<56> WL_O<55> WL_O<54> WL_O<53> WL_O<52> WL_O<51> ++ WL_O<50> WL_O<49> WL_O<48> VDD VSS / RM_IHPSG13_256x16_c2_2P_DEC04 +XSEL<2> ADDR_N_I<3> ADDR_N_I<2> ADDR_N_I<1> ADDR_N_I<0> CS00<2> ECLK_H<2> ++ ECLK_H<3> ECLK_B<2> ECLK_B<3> WL_O<47> WL_O<46> WL_O<45> WL_O<44> WL_O<43> ++ WL_O<42> WL_O<41> WL_O<40> WL_O<39> WL_O<38> WL_O<37> WL_O<36> WL_O<35> ++ WL_O<34> WL_O<33> WL_O<32> VDD VSS / RM_IHPSG13_256x16_c2_2P_DEC04 +XSEL<1> ADDR_N_I<3> ADDR_N_I<2> ADDR_N_I<1> ADDR_N_I<0> CS00<1> ECLK_H<1> ++ ECLK_H<2> ECLK_B<1> ECLK_B<2> WL_O<31> WL_O<30> WL_O<29> WL_O<28> WL_O<27> ++ WL_O<26> WL_O<25> WL_O<24> WL_O<23> WL_O<22> WL_O<21> WL_O<20> WL_O<19> ++ WL_O<18> WL_O<17> WL_O<16> VDD VSS / RM_IHPSG13_256x16_c2_2P_DEC04 +XSEL<0> ADDR_N_I<3> ADDR_N_I<2> ADDR_N_I<1> ADDR_N_I<0> CS00<0> ECLK_I ++ ECLK_H<1> ECLK_B<0> ECLK_B<1> WL_O<15> WL_O<14> WL_O<13> WL_O<12> WL_O<11> ++ WL_O<10> WL_O<9> WL_O<8> WL_O<7> WL_O<6> WL_O<5> WL_O<4> WL_O<3> WL_O<2> ++ WL_O<1> WL_O<0> VDD VSS / RM_IHPSG13_256x16_c2_2P_DEC04 +XDEC11<1> ADDR_N_I<5> ADDR_N_I<4> CS04<1> CS00<7> VDD VSS / ++ RM_IHPSG13_256x16_c2_2P_DEC03 +XDEC11<0> ADDR_N_I<5> ADDR_N_I<4> CS04<0> CS00<3> VDD VSS / ++ RM_IHPSG13_256x16_c2_2P_DEC03 +XDEC01<2> ADDR_N_I<7> ADDR_N_I<6> CS_I CS04<1> VDD VSS / ++ RM_IHPSG13_256x16_c2_2P_DEC01 +XDEC01<1> ADDR_N_I<5> ADDR_N_I<4> CS04<1> CS00<5> VDD VSS / ++ RM_IHPSG13_256x16_c2_2P_DEC01 +XDEC01<0> ADDR_N_I<5> ADDR_N_I<4> CS04<0> CS00<1> VDD VSS / ++ RM_IHPSG13_256x16_c2_2P_DEC01 +XL2<66> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<65> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<64> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<63> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<62> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<61> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<60> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<59> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<58> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<57> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<56> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<55> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<54> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<53> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<52> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<51> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<50> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<49> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<48> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<47> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<46> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<45> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<44> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<43> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<42> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<41> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<40> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<39> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<38> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<37> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<36> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<35> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<34> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<33> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<32> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<31> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<30> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<29> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<28> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<27> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<26> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<25> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<24> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<23> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<22> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<21> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<20> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<19> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<18> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<17> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<16> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<15> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<14> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<13> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<12> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<11> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<10> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<9> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<8> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<7> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<6> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<5> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<4> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<3> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<2> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<1> VDD VSS / RSC_IHPSG13_FILLCAP8 +XDEC10<1> ADDR_N_I<5> ADDR_N_I<4> CS04<1> CS00<6> VDD VSS / ++ RM_IHPSG13_256x16_c2_2P_DEC02 +XDEC10<0> ADDR_N_I<5> ADDR_N_I<4> CS04<0> CS00<2> VDD VSS / ++ RM_IHPSG13_256x16_c2_2P_DEC02 +XDEC00<2> ADDR_N_I<7> ADDR_N_I<6> CS_I CS04<0> VDD VSS / ++ RM_IHPSG13_256x16_c2_2P_DEC00 +XDEC00<1> ADDR_N_I<5> ADDR_N_I<4> CS04<1> CS00<4> VDD VSS / ++ RM_IHPSG13_256x16_c2_2P_DEC00 +XDEC00<0> ADDR_N_I<5> ADDR_N_I<4> CS04<0> CS00<0> VDD VSS / ++ RM_IHPSG13_256x16_c2_2P_DEC00 +XI0 ADDR_N_I<7> VDD VSS / RSC_IHPSG13_TIEL +.ENDS +.SUBCKT RM_IHPSG13_256x16_c2_2P_ROWREG7 ACLK_N_I ADDR_I<6> ADDR_I<5> ADDR_I<4> ADDR_I<3> ++ ADDR_I<2> ADDR_I<1> ADDR_I<0> ADDR_N_O<6> ADDR_N_O<5> ADDR_N_O<4> ++ ADDR_N_O<3> ADDR_N_O<2> ADDR_N_O<1> ADDR_N_O<0> BIST_ADDR_I<6> ++ BIST_ADDR_I<5> BIST_ADDR_I<4> BIST_ADDR_I<3> BIST_ADDR_I<2> BIST_ADDR_I<1> ++ BIST_ADDR_I<0> BIST_EN_I VDD VSS +XINV<6> q_int<6> qn_int<6> VDD VSS / RSC_IHPSG13_CINVX2 +XINV<5> q_int<5> qn_int<5> VDD VSS / RSC_IHPSG13_CINVX2 +XINV<4> q_int<4> qn_int<4> VDD VSS / RSC_IHPSG13_CINVX2 +XINV<3> q_int<3> qn_int<3> VDD VSS / RSC_IHPSG13_CINVX2 +XINV<2> q_int<2> qn_int<2> VDD VSS / RSC_IHPSG13_CINVX2 +XINV<1> q_int<1> qn_int<1> VDD VSS / RSC_IHPSG13_CINVX2 +XINV<0> q_int<0> qn_int<0> VDD VSS / RSC_IHPSG13_CINVX2 +XDRV<6> qn_int<6> ADDR_N_O<6> VDD VSS / RSC_IHPSG13_CINVX8 +XDRV<5> qn_int<5> ADDR_N_O<5> VDD VSS / RSC_IHPSG13_CINVX8 +XDRV<4> qn_int<4> ADDR_N_O<4> VDD VSS / RSC_IHPSG13_CINVX8 +XDRV<3> qn_int<3> ADDR_N_O<3> VDD VSS / RSC_IHPSG13_CINVX8 +XDRV<2> qn_int<2> ADDR_N_O<2> VDD VSS / RSC_IHPSG13_CINVX8 +XDRV<1> qn_int<1> ADDR_N_O<1> VDD VSS / RSC_IHPSG13_CINVX8 +XDRV<0> qn_int<0> ADDR_N_O<0> VDD VSS / RSC_IHPSG13_CINVX8 +XDFF<6> BIST_EN_I BIST_ADDR_I<6> ACLK_N_I ADDR_I<6> q_int<6> net2<0> VDD ++ VSS / RSC_IHPSG13_DFNQMX2IX1 +XDFF<5> BIST_EN_I BIST_ADDR_I<5> ACLK_N_I ADDR_I<5> q_int<5> net2<1> VDD ++ VSS / RSC_IHPSG13_DFNQMX2IX1 +XDFF<4> BIST_EN_I BIST_ADDR_I<4> ACLK_N_I ADDR_I<4> q_int<4> net2<2> VDD ++ VSS / RSC_IHPSG13_DFNQMX2IX1 +XDFF<3> BIST_EN_I BIST_ADDR_I<3> ACLK_N_I ADDR_I<3> q_int<3> net2<3> VDD ++ VSS / RSC_IHPSG13_DFNQMX2IX1 +XDFF<2> BIST_EN_I BIST_ADDR_I<2> ACLK_N_I ADDR_I<2> q_int<2> net2<4> VDD ++ VSS / RSC_IHPSG13_DFNQMX2IX1 +XDFF<1> BIST_EN_I BIST_ADDR_I<1> ACLK_N_I ADDR_I<1> q_int<1> net2<5> VDD ++ VSS / RSC_IHPSG13_DFNQMX2IX1 +XDFF<0> BIST_EN_I BIST_ADDR_I<0> ACLK_N_I ADDR_I<0> q_int<0> net2<6> VDD ++ VSS / RSC_IHPSG13_DFNQMX2IX1 +XI11<7> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI11<6> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI11<5> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI11<4> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI11<3> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI11<2> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI11<1> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI11<0> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI12<1> VDD VSS / RSC_IHPSG13_FILLCAP4 +XI12<0> VDD VSS / RSC_IHPSG13_FILLCAP4 +.ENDS + +.SUBCKT RM_IHPSG13_256x16_c2_2P_ROWDEC4 ADDR_N_I<3> ADDR_N_I<2> ADDR_N_I<1> ADDR_N_I<0> ++ CS_I ECLK_I WL_O<15> WL_O<14> WL_O<13> WL_O<12> WL_O<11> WL_O<10> WL_O<9> ++ WL_O<8> WL_O<7> WL_O<6> WL_O<5> WL_O<4> WL_O<3> WL_O<2> WL_O<1> WL_O<0> ++ VDD VSS +XL2<12> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<11> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<10> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<9> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<8> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<7> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<6> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<5> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<4> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<3> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<2> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<1> VDD VSS / RSC_IHPSG13_FILLCAP8 +XSEL ADDR_N_I<3> ADDR_N_I<2> ADDR_N_I<1> ADDR_N_I<0> CS_I ECLK_I ECLK_H<1> ++ ECLK_B<0> ECLK_B<1> WL_O<15> WL_O<14> WL_O<13> WL_O<12> WL_O<11> WL_O<10> ++ WL_O<9> WL_O<8> WL_O<7> WL_O<6> WL_O<5> WL_O<4> WL_O<3> WL_O<2> WL_O<1> ++ WL_O<0> VDD VSS / RM_IHPSG13_256x16_c2_2P_DEC04 +.ENDS +.SUBCKT RM_IHPSG13_256x16_c2_2P_ROWREG4 ACLK_N_I ADDR_I<3> ADDR_I<2> ADDR_I<1> ADDR_I<0> ++ ADDR_N_O<3> ADDR_N_O<2> ADDR_N_O<1> ADDR_N_O<0> BIST_ADDR_I<3> ++ BIST_ADDR_I<2> BIST_ADDR_I<1> BIST_ADDR_I<0> BIST_EN_I VDD VSS +XINV<3> q_int<3> qn_int<3> VDD VSS / RSC_IHPSG13_CINVX2 +XINV<2> q_int<2> qn_int<2> VDD VSS / RSC_IHPSG13_CINVX2 +XINV<1> q_int<1> qn_int<1> VDD VSS / RSC_IHPSG13_CINVX2 +XINV<0> q_int<0> qn_int<0> VDD VSS / RSC_IHPSG13_CINVX2 +XDRV<3> qn_int<3> ADDR_N_O<3> VDD VSS / RSC_IHPSG13_CINVX8 +XDRV<2> qn_int<2> ADDR_N_O<2> VDD VSS / RSC_IHPSG13_CINVX8 +XDRV<1> qn_int<1> ADDR_N_O<1> VDD VSS / RSC_IHPSG13_CINVX8 +XDRV<0> qn_int<0> ADDR_N_O<0> VDD VSS / RSC_IHPSG13_CINVX8 +XDFF<3> BIST_EN_I BIST_ADDR_I<3> ACLK_N_I ADDR_I<3> q_int<3> net7<0> VDD ++ VSS / RSC_IHPSG13_DFNQMX2IX1 +XDFF<2> BIST_EN_I BIST_ADDR_I<2> ACLK_N_I ADDR_I<2> q_int<2> net7<1> VDD ++ VSS / RSC_IHPSG13_DFNQMX2IX1 +XDFF<1> BIST_EN_I BIST_ADDR_I<1> ACLK_N_I ADDR_I<1> q_int<1> net7<2> VDD ++ VSS / RSC_IHPSG13_DFNQMX2IX1 +XDFF<0> BIST_EN_I BIST_ADDR_I<0> ACLK_N_I ADDR_I<0> q_int<0> net7<3> VDD ++ VSS / RSC_IHPSG13_DFNQMX2IX1 +XI11<20> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI11<19> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI11<18> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI11<17> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI11<16> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI11<15> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI11<14> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI11<13> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI11<12> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI11<11> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI11<10> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI11<9> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI11<8> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI11<7> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI11<6> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI11<5> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI11<4> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI11<3> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI11<2> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI11<1> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI12<4> VDD VSS / RSC_IHPSG13_FILLCAP4 +XI12<3> VDD VSS / RSC_IHPSG13_FILLCAP4 +XI12<2> VDD VSS / RSC_IHPSG13_FILLCAP4 +XI12<1> VDD VSS / RSC_IHPSG13_FILLCAP4 +XI12<0> VDD VSS / RSC_IHPSG13_FILLCAP4 +.ENDS + + +.SUBCKT RM_IHPSG13_256x16_c2_1P_BITKIT_TAP BLC BLT NW PW VDD VSS +.ENDS +.SUBCKT RM_IHPSG13_256x16_c2_1P_BITKIT_16x2_TAP A_BLC<1> A_BLC<0> A_BLT<1> A_BLT<0> ++ VDD_CORE VSS +XITAP<1> A_BLC<1> A_BLT<1> VDD_CORE VSS VDD_CORE VSS ++ / RM_IHPSG13_256x16_c2_1P_BITKIT_TAP +XITAP<0> A_BLC<0> A_BLT<0> VDD_CORE VSS VDD_CORE VSS ++ / RM_IHPSG13_256x16_c2_1P_BITKIT_TAP +XIEDGEBP_COL1<1> BLC<1> BLT<1> VDD_CORE VSS VDD_CORE ++ VSS / RM_IHPSG13_256x16_c2_1P_BITKIT_EDGE_TB +XIEDGEBP_COL1<0> BLC<1> BLT<1> VDD_CORE VSS VDD_CORE ++ VSS / RM_IHPSG13_256x16_c2_1P_BITKIT_EDGE_TB +XIEDGEBP_COL2<1> BLC<0> BLT<0> VDD_CORE VSS VDD_CORE ++ VSS / RM_IHPSG13_256x16_c2_1P_BITKIT_EDGE_TB +XIEDGEBP_COL2<0> BLC<0> BLT<0> VDD_CORE VSS VDD_CORE ++ VSS / RM_IHPSG13_256x16_c2_1P_BITKIT_EDGE_TB +.ENDS +.SUBCKT RM_IHPSG13_256x16_c2_1P_BITKIT_16x2_TAP_LR VDD_CORE VSS +XCORNER<1> VDD_CORE VSS VDD_CORE VSS / ++ RM_IHPSG13_256x16_c2_1P_BITKIT_CORNER +XCORNER<0> VDD_CORE VSS VDD_CORE VSS / ++ RM_IHPSG13_256x16_c2_1P_BITKIT_CORNER +XTAP_BORDER VDD_CORE VSS VDD_CORE VSS / ++ RM_IHPSG13_256x16_c2_1P_BITKIT_TAP_LR +.ENDS +.SUBCKT RM_IHPSG13_256x16_c2_1P_DEC03 ADDR<1> ADDR<0> CS CS_OUT VDD VSS +XDECINV net1 CS_OUT VDD VSS / RSC_IHPSG13_INVX4 +XI0 VDD VSS / RSC_IHPSG13_FILLCAP4 +XDEC ADDR<1> ADDR<0> CS net1 VDD VSS / RSC_IHPSG13_NAND3X2 +.ENDS +.SUBCKT RM_IHPSG13_256x16_c2_1P_DEC02 ADDR<1> ADDR<0> CS CS_OUT VDD VSS +XDECINV net1 CS_OUT VDD VSS / RSC_IHPSG13_INVX4 +XDEC ADDR<1> NADDR<0> CS net1 VDD VSS / RSC_IHPSG13_NAND3X2 +XI2 VDD VSS / RSC_IHPSG13_FILLCAP4 +XADDRINV ADDR<0> NADDR<0> VDD VSS / RSC_IHPSG13_INVX2 +.ENDS +.SUBCKT RM_IHPSG13_256x16_c2_1P_ROWDEC8 ADDR_N_I<7> ADDR_N_I<6> ADDR_N_I<5> ADDR_N_I<4> ++ ADDR_N_I<3> ADDR_N_I<2> ADDR_N_I<1> ADDR_N_I<0> CS_I ECLK_I WL_O<255> ++ WL_O<254> WL_O<253> WL_O<252> WL_O<251> WL_O<250> WL_O<249> WL_O<248> ++ WL_O<247> WL_O<246> WL_O<245> WL_O<244> WL_O<243> WL_O<242> WL_O<241> ++ WL_O<240> WL_O<239> WL_O<238> WL_O<237> WL_O<236> WL_O<235> WL_O<234> ++ WL_O<233> WL_O<232> WL_O<231> WL_O<230> WL_O<229> WL_O<228> WL_O<227> ++ WL_O<226> WL_O<225> WL_O<224> WL_O<223> WL_O<222> WL_O<221> WL_O<220> ++ WL_O<219> WL_O<218> WL_O<217> WL_O<216> WL_O<215> WL_O<214> WL_O<213> ++ WL_O<212> WL_O<211> WL_O<210> WL_O<209> WL_O<208> WL_O<207> WL_O<206> ++ WL_O<205> WL_O<204> WL_O<203> WL_O<202> WL_O<201> WL_O<200> WL_O<199> ++ WL_O<198> WL_O<197> WL_O<196> WL_O<195> WL_O<194> WL_O<193> WL_O<192> ++ WL_O<191> WL_O<190> WL_O<189> WL_O<188> WL_O<187> WL_O<186> WL_O<185> ++ WL_O<184> WL_O<183> WL_O<182> WL_O<181> WL_O<180> WL_O<179> WL_O<178> ++ WL_O<177> WL_O<176> WL_O<175> WL_O<174> WL_O<173> WL_O<172> WL_O<171> ++ WL_O<170> WL_O<169> WL_O<168> WL_O<167> WL_O<166> WL_O<165> WL_O<164> ++ WL_O<163> WL_O<162> WL_O<161> WL_O<160> WL_O<159> WL_O<158> WL_O<157> ++ WL_O<156> WL_O<155> WL_O<154> WL_O<153> WL_O<152> WL_O<151> WL_O<150> ++ WL_O<149> WL_O<148> WL_O<147> WL_O<146> WL_O<145> WL_O<144> WL_O<143> ++ WL_O<142> WL_O<141> WL_O<140> WL_O<139> WL_O<138> WL_O<137> WL_O<136> ++ WL_O<135> WL_O<134> WL_O<133> WL_O<132> WL_O<131> WL_O<130> WL_O<129> ++ WL_O<128> WL_O<127> WL_O<126> WL_O<125> WL_O<124> WL_O<123> WL_O<122> ++ WL_O<121> WL_O<120> WL_O<119> WL_O<118> WL_O<117> WL_O<116> WL_O<115> ++ WL_O<114> WL_O<113> WL_O<112> WL_O<111> WL_O<110> WL_O<109> WL_O<108> ++ WL_O<107> WL_O<106> WL_O<105> WL_O<104> WL_O<103> WL_O<102> WL_O<101> ++ WL_O<100> WL_O<99> WL_O<98> WL_O<97> WL_O<96> WL_O<95> WL_O<94> WL_O<93> ++ WL_O<92> WL_O<91> WL_O<90> WL_O<89> WL_O<88> WL_O<87> WL_O<86> WL_O<85> ++ WL_O<84> WL_O<83> WL_O<82> WL_O<81> WL_O<80> WL_O<79> WL_O<78> WL_O<77> ++ WL_O<76> WL_O<75> WL_O<74> WL_O<73> WL_O<72> WL_O<71> WL_O<70> WL_O<69> ++ WL_O<68> WL_O<67> WL_O<66> WL_O<65> WL_O<64> WL_O<63> WL_O<62> WL_O<61> ++ WL_O<60> WL_O<59> WL_O<58> WL_O<57> WL_O<56> WL_O<55> WL_O<54> WL_O<53> ++ WL_O<52> WL_O<51> WL_O<50> WL_O<49> WL_O<48> WL_O<47> WL_O<46> WL_O<45> ++ WL_O<44> WL_O<43> WL_O<42> WL_O<41> WL_O<40> WL_O<39> WL_O<38> WL_O<37> ++ WL_O<36> WL_O<35> WL_O<34> WL_O<33> WL_O<32> WL_O<31> WL_O<30> WL_O<29> ++ WL_O<28> WL_O<27> WL_O<26> WL_O<25> WL_O<24> WL_O<23> WL_O<22> WL_O<21> ++ WL_O<20> WL_O<19> WL_O<18> WL_O<17> WL_O<16> WL_O<15> WL_O<14> WL_O<13> ++ WL_O<12> WL_O<11> WL_O<10> WL_O<9> WL_O<8> WL_O<7> WL_O<6> WL_O<5> WL_O<4> ++ WL_O<3> WL_O<2> WL_O<1> WL_O<0> VDD VSS +XDEC11<4> ADDR_N_I<7> ADDR_N_I<6> CS_I CS04<3> VDD VSS / ++ RM_IHPSG13_256x16_c2_1P_DEC03 +XDEC11<3> ADDR_N_I<5> ADDR_N_I<4> CS04<3> CS00<15> VDD VSS / ++ RM_IHPSG13_256x16_c2_1P_DEC03 +XDEC11<2> ADDR_N_I<5> ADDR_N_I<4> CS04<2> CS00<11> VDD VSS / ++ RM_IHPSG13_256x16_c2_1P_DEC03 +XDEC11<1> ADDR_N_I<5> ADDR_N_I<4> CS04<1> CS00<7> VDD VSS / ++ RM_IHPSG13_256x16_c2_1P_DEC03 +XDEC11<0> ADDR_N_I<5> ADDR_N_I<4> CS04<0> CS00<3> VDD VSS / ++ RM_IHPSG13_256x16_c2_1P_DEC03 +XL2<88> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<87> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<86> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<85> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<84> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<83> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<82> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<81> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<80> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<79> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<78> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<77> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<76> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<75> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<74> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<73> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<72> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<71> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<70> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<69> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<68> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<67> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<66> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<65> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<64> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<63> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<62> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<61> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<60> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<59> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<58> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<57> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<56> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<55> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<54> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<53> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<52> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<51> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<50> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<49> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<48> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<47> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<46> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<45> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<44> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<43> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<42> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<41> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<40> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<39> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<38> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<37> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<36> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<35> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<34> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<33> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<32> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<31> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<30> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<29> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<28> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<27> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<26> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<25> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<24> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<23> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<22> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<21> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<20> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<19> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<18> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<17> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<16> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<15> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<14> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<13> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<12> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<11> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<10> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<9> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<8> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<7> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<6> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<5> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<4> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<3> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<2> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<1> VDD VSS / RSC_IHPSG13_FILLCAP8 +XDEC10<4> ADDR_N_I<7> ADDR_N_I<6> CS_I CS04<2> VDD VSS / ++ RM_IHPSG13_256x16_c2_1P_DEC02 +XDEC10<3> ADDR_N_I<5> ADDR_N_I<4> CS04<3> CS00<14> VDD VSS / ++ RM_IHPSG13_256x16_c2_1P_DEC02 +XDEC10<2> ADDR_N_I<5> ADDR_N_I<4> CS04<2> CS00<10> VDD VSS / ++ RM_IHPSG13_256x16_c2_1P_DEC02 +XDEC10<1> ADDR_N_I<5> ADDR_N_I<4> CS04<1> CS00<6> VDD VSS / ++ RM_IHPSG13_256x16_c2_1P_DEC02 +XDEC10<0> ADDR_N_I<5> ADDR_N_I<4> CS04<0> CS00<2> VDD VSS / ++ RM_IHPSG13_256x16_c2_1P_DEC02 +XDEC00<4> ADDR_N_I<7> ADDR_N_I<6> CS_I CS04<0> VDD VSS / ++ RM_IHPSG13_256x16_c2_1P_DEC00 +XDEC00<3> ADDR_N_I<5> ADDR_N_I<4> CS04<3> CS00<12> VDD VSS / ++ RM_IHPSG13_256x16_c2_1P_DEC00 +XDEC00<2> ADDR_N_I<5> ADDR_N_I<4> CS04<2> CS00<8> VDD VSS / ++ RM_IHPSG13_256x16_c2_1P_DEC00 +XDEC00<1> ADDR_N_I<5> ADDR_N_I<4> CS04<1> CS00<4> VDD VSS / ++ RM_IHPSG13_256x16_c2_1P_DEC00 +XDEC00<0> ADDR_N_I<5> ADDR_N_I<4> CS04<0> CS00<0> VDD VSS / ++ RM_IHPSG13_256x16_c2_1P_DEC00 +XSEL<15> ADDR_N_I<3> ADDR_N_I<2> ADDR_N_I<1> ADDR_N_I<0> CS00<15> ECLK_H<15> ++ ECLK_H<16> ECLK_B<15> ECLK_B<16> WL_O<255> WL_O<254> WL_O<253> WL_O<252> ++ WL_O<251> WL_O<250> WL_O<249> WL_O<248> WL_O<247> WL_O<246> WL_O<245> ++ WL_O<244> WL_O<243> WL_O<242> WL_O<241> WL_O<240> VDD VSS / ++ RM_IHPSG13_256x16_c2_1P_DEC04 +XSEL<14> ADDR_N_I<3> ADDR_N_I<2> ADDR_N_I<1> ADDR_N_I<0> CS00<14> ECLK_H<14> ++ ECLK_H<15> ECLK_B<14> ECLK_B<15> WL_O<239> WL_O<238> WL_O<237> WL_O<236> ++ WL_O<235> WL_O<234> WL_O<233> WL_O<232> WL_O<231> WL_O<230> WL_O<229> ++ WL_O<228> WL_O<227> WL_O<226> WL_O<225> WL_O<224> VDD VSS / ++ RM_IHPSG13_256x16_c2_1P_DEC04 +XSEL<13> ADDR_N_I<3> ADDR_N_I<2> ADDR_N_I<1> ADDR_N_I<0> CS00<13> ECLK_H<13> ++ ECLK_H<14> ECLK_B<13> ECLK_B<14> WL_O<223> WL_O<222> WL_O<221> WL_O<220> ++ WL_O<219> WL_O<218> WL_O<217> WL_O<216> WL_O<215> WL_O<214> WL_O<213> ++ WL_O<212> WL_O<211> WL_O<210> WL_O<209> WL_O<208> VDD VSS / ++ RM_IHPSG13_256x16_c2_1P_DEC04 +XSEL<12> ADDR_N_I<3> ADDR_N_I<2> ADDR_N_I<1> ADDR_N_I<0> CS00<12> ECLK_H<12> ++ ECLK_H<13> ECLK_B<12> ECLK_B<13> WL_O<207> WL_O<206> WL_O<205> WL_O<204> ++ WL_O<203> WL_O<202> WL_O<201> WL_O<200> WL_O<199> WL_O<198> WL_O<197> ++ WL_O<196> WL_O<195> WL_O<194> WL_O<193> WL_O<192> VDD VSS / ++ RM_IHPSG13_256x16_c2_1P_DEC04 +XSEL<11> ADDR_N_I<3> ADDR_N_I<2> ADDR_N_I<1> ADDR_N_I<0> CS00<11> ECLK_H<11> ++ ECLK_H<12> ECLK_B<11> ECLK_B<12> WL_O<191> WL_O<190> WL_O<189> WL_O<188> ++ WL_O<187> WL_O<186> WL_O<185> WL_O<184> WL_O<183> WL_O<182> WL_O<181> ++ WL_O<180> WL_O<179> WL_O<178> WL_O<177> WL_O<176> VDD VSS / ++ RM_IHPSG13_256x16_c2_1P_DEC04 +XSEL<10> ADDR_N_I<3> ADDR_N_I<2> ADDR_N_I<1> ADDR_N_I<0> CS00<10> ECLK_H<10> ++ ECLK_H<11> ECLK_B<10> ECLK_B<11> WL_O<175> WL_O<174> WL_O<173> WL_O<172> ++ WL_O<171> WL_O<170> WL_O<169> WL_O<168> WL_O<167> WL_O<166> WL_O<165> ++ WL_O<164> WL_O<163> WL_O<162> WL_O<161> WL_O<160> VDD VSS / ++ RM_IHPSG13_256x16_c2_1P_DEC04 +XSEL<9> ADDR_N_I<3> ADDR_N_I<2> ADDR_N_I<1> ADDR_N_I<0> CS00<9> ECLK_H<9> ++ ECLK_H<10> ECLK_B<9> ECLK_B<10> WL_O<159> WL_O<158> WL_O<157> WL_O<156> ++ WL_O<155> WL_O<154> WL_O<153> WL_O<152> WL_O<151> WL_O<150> WL_O<149> ++ WL_O<148> WL_O<147> WL_O<146> WL_O<145> WL_O<144> VDD VSS / ++ RM_IHPSG13_256x16_c2_1P_DEC04 +XSEL<8> ADDR_N_I<3> ADDR_N_I<2> ADDR_N_I<1> ADDR_N_I<0> CS00<8> ECLK_H<8> ++ ECLK_H<9> ECLK_B<8> ECLK_B<9> WL_O<143> WL_O<142> WL_O<141> WL_O<140> ++ WL_O<139> WL_O<138> WL_O<137> WL_O<136> WL_O<135> WL_O<134> WL_O<133> ++ WL_O<132> WL_O<131> WL_O<130> WL_O<129> WL_O<128> VDD VSS / ++ RM_IHPSG13_256x16_c2_1P_DEC04 +XSEL<7> ADDR_N_I<3> ADDR_N_I<2> ADDR_N_I<1> ADDR_N_I<0> CS00<7> ECLK_H<7> ++ ECLK_H<8> ECLK_B<7> ECLK_B<8> WL_O<127> WL_O<126> WL_O<125> WL_O<124> ++ WL_O<123> WL_O<122> WL_O<121> WL_O<120> WL_O<119> WL_O<118> WL_O<117> ++ WL_O<116> WL_O<115> WL_O<114> WL_O<113> WL_O<112> VDD VSS / ++ RM_IHPSG13_256x16_c2_1P_DEC04 +XSEL<6> ADDR_N_I<3> ADDR_N_I<2> ADDR_N_I<1> ADDR_N_I<0> CS00<6> ECLK_H<6> ++ ECLK_H<7> ECLK_B<6> ECLK_B<7> WL_O<111> WL_O<110> WL_O<109> WL_O<108> ++ WL_O<107> WL_O<106> WL_O<105> WL_O<104> WL_O<103> WL_O<102> WL_O<101> ++ WL_O<100> WL_O<99> WL_O<98> WL_O<97> WL_O<96> VDD VSS / ++ RM_IHPSG13_256x16_c2_1P_DEC04 +XSEL<5> ADDR_N_I<3> ADDR_N_I<2> ADDR_N_I<1> ADDR_N_I<0> CS00<5> ECLK_H<5> ++ ECLK_H<6> ECLK_B<5> ECLK_B<6> WL_O<95> WL_O<94> WL_O<93> WL_O<92> WL_O<91> ++ WL_O<90> WL_O<89> WL_O<88> WL_O<87> WL_O<86> WL_O<85> WL_O<84> WL_O<83> ++ WL_O<82> WL_O<81> WL_O<80> VDD VSS / RM_IHPSG13_256x16_c2_1P_DEC04 +XSEL<4> ADDR_N_I<3> ADDR_N_I<2> ADDR_N_I<1> ADDR_N_I<0> CS00<4> ECLK_H<4> ++ ECLK_H<5> ECLK_B<4> ECLK_B<5> WL_O<79> WL_O<78> WL_O<77> WL_O<76> WL_O<75> ++ WL_O<74> WL_O<73> WL_O<72> WL_O<71> WL_O<70> WL_O<69> WL_O<68> WL_O<67> ++ WL_O<66> WL_O<65> WL_O<64> VDD VSS / RM_IHPSG13_256x16_c2_1P_DEC04 +XSEL<3> ADDR_N_I<3> ADDR_N_I<2> ADDR_N_I<1> ADDR_N_I<0> CS00<3> ECLK_H<3> ++ ECLK_H<4> ECLK_B<3> ECLK_B<4> WL_O<63> WL_O<62> WL_O<61> WL_O<60> WL_O<59> ++ WL_O<58> WL_O<57> WL_O<56> WL_O<55> WL_O<54> WL_O<53> WL_O<52> WL_O<51> ++ WL_O<50> WL_O<49> WL_O<48> VDD VSS / RM_IHPSG13_256x16_c2_1P_DEC04 +XSEL<2> ADDR_N_I<3> ADDR_N_I<2> ADDR_N_I<1> ADDR_N_I<0> CS00<2> ECLK_H<2> ++ ECLK_H<3> ECLK_B<2> ECLK_B<3> WL_O<47> WL_O<46> WL_O<45> WL_O<44> WL_O<43> ++ WL_O<42> WL_O<41> WL_O<40> WL_O<39> WL_O<38> WL_O<37> WL_O<36> WL_O<35> ++ WL_O<34> WL_O<33> WL_O<32> VDD VSS / RM_IHPSG13_256x16_c2_1P_DEC04 +XSEL<1> ADDR_N_I<3> ADDR_N_I<2> ADDR_N_I<1> ADDR_N_I<0> CS00<1> ECLK_H<1> ++ ECLK_H<2> ECLK_B<1> ECLK_B<2> WL_O<31> WL_O<30> WL_O<29> WL_O<28> WL_O<27> ++ WL_O<26> WL_O<25> WL_O<24> WL_O<23> WL_O<22> WL_O<21> WL_O<20> WL_O<19> ++ WL_O<18> WL_O<17> WL_O<16> VDD VSS / RM_IHPSG13_256x16_c2_1P_DEC04 +XSEL<0> ADDR_N_I<3> ADDR_N_I<2> ADDR_N_I<1> ADDR_N_I<0> CS00<0> ECLK_I ++ ECLK_H<1> ECLK_B<0> ECLK_B<1> WL_O<15> WL_O<14> WL_O<13> WL_O<12> WL_O<11> ++ WL_O<10> WL_O<9> WL_O<8> WL_O<7> WL_O<6> WL_O<5> WL_O<4> WL_O<3> WL_O<2> ++ WL_O<1> WL_O<0> VDD VSS / RM_IHPSG13_256x16_c2_1P_DEC04 +XDEC01<4> ADDR_N_I<7> ADDR_N_I<6> CS_I CS04<1> VDD VSS / ++ RM_IHPSG13_256x16_c2_1P_DEC01 +XDEC01<3> ADDR_N_I<5> ADDR_N_I<4> CS04<3> CS00<13> VDD VSS / ++ RM_IHPSG13_256x16_c2_1P_DEC01 +XDEC01<2> ADDR_N_I<5> ADDR_N_I<4> CS04<2> CS00<9> VDD VSS / ++ RM_IHPSG13_256x16_c2_1P_DEC01 +XDEC01<1> ADDR_N_I<5> ADDR_N_I<4> CS04<1> CS00<5> VDD VSS / ++ RM_IHPSG13_256x16_c2_1P_DEC01 +XDEC01<0> ADDR_N_I<5> ADDR_N_I<4> CS04<0> CS00<1> VDD VSS / ++ RM_IHPSG13_256x16_c2_1P_DEC01 +.ENDS +.SUBCKT RM_IHPSG13_256x16_c2_1P_ROWREG8 ACLK_N_I ADDR_I<7> ADDR_I<6> ADDR_I<5> ADDR_I<4> ++ ADDR_I<3> ADDR_I<2> ADDR_I<1> ADDR_I<0> ADDR_N_O<7> ADDR_N_O<6> ADDR_N_O<5> ++ ADDR_N_O<4> ADDR_N_O<3> ADDR_N_O<2> ADDR_N_O<1> ADDR_N_O<0> BIST_ADDR_I<7> ++ BIST_ADDR_I<6> BIST_ADDR_I<5> BIST_ADDR_I<4> BIST_ADDR_I<3> BIST_ADDR_I<2> ++ BIST_ADDR_I<1> BIST_ADDR_I<0> BIST_EN_I VDD VSS +XINV<7> q_int<7> qn_int<7> VDD VSS / RSC_IHPSG13_CINVX2 +XINV<6> q_int<6> qn_int<6> VDD VSS / RSC_IHPSG13_CINVX2 +XINV<5> q_int<5> qn_int<5> VDD VSS / RSC_IHPSG13_CINVX2 +XINV<4> q_int<4> qn_int<4> VDD VSS / RSC_IHPSG13_CINVX2 +XINV<3> q_int<3> qn_int<3> VDD VSS / RSC_IHPSG13_CINVX2 +XINV<2> q_int<2> qn_int<2> VDD VSS / RSC_IHPSG13_CINVX2 +XINV<1> q_int<1> qn_int<1> VDD VSS / RSC_IHPSG13_CINVX2 +XINV<0> q_int<0> qn_int<0> VDD VSS / RSC_IHPSG13_CINVX2 +XDRV<7> qn_int<7> ADDR_N_O<7> VDD VSS / RSC_IHPSG13_CINVX8 +XDRV<6> qn_int<6> ADDR_N_O<6> VDD VSS / RSC_IHPSG13_CINVX8 +XDRV<5> qn_int<5> ADDR_N_O<5> VDD VSS / RSC_IHPSG13_CINVX8 +XDRV<4> qn_int<4> ADDR_N_O<4> VDD VSS / RSC_IHPSG13_CINVX8 +XDRV<3> qn_int<3> ADDR_N_O<3> VDD VSS / RSC_IHPSG13_CINVX8 +XDRV<2> qn_int<2> ADDR_N_O<2> VDD VSS / RSC_IHPSG13_CINVX8 +XDRV<1> qn_int<1> ADDR_N_O<1> VDD VSS / RSC_IHPSG13_CINVX8 +XDRV<0> qn_int<0> ADDR_N_O<0> VDD VSS / RSC_IHPSG13_CINVX8 +XDFF<7> BIST_EN_I BIST_ADDR_I<7> ACLK_N_I ADDR_I<7> q_int<7> net2<0> VDD ++ VSS / RSC_IHPSG13_DFNQMX2IX1 +XDFF<6> BIST_EN_I BIST_ADDR_I<6> ACLK_N_I ADDR_I<6> q_int<6> net2<1> VDD ++ VSS / RSC_IHPSG13_DFNQMX2IX1 +XDFF<5> BIST_EN_I BIST_ADDR_I<5> ACLK_N_I ADDR_I<5> q_int<5> net2<2> VDD ++ VSS / RSC_IHPSG13_DFNQMX2IX1 +XDFF<4> BIST_EN_I BIST_ADDR_I<4> ACLK_N_I ADDR_I<4> q_int<4> net2<3> VDD ++ VSS / RSC_IHPSG13_DFNQMX2IX1 +XDFF<3> BIST_EN_I BIST_ADDR_I<3> ACLK_N_I ADDR_I<3> q_int<3> net2<4> VDD ++ VSS / RSC_IHPSG13_DFNQMX2IX1 +XDFF<2> BIST_EN_I BIST_ADDR_I<2> ACLK_N_I ADDR_I<2> q_int<2> net2<5> VDD ++ VSS / RSC_IHPSG13_DFNQMX2IX1 +XDFF<1> BIST_EN_I BIST_ADDR_I<1> ACLK_N_I ADDR_I<1> q_int<1> net2<6> VDD ++ VSS / RSC_IHPSG13_DFNQMX2IX1 +XDFF<0> BIST_EN_I BIST_ADDR_I<0> ACLK_N_I ADDR_I<0> q_int<0> net2<7> VDD ++ VSS / RSC_IHPSG13_DFNQMX2IX1 +XI11<4> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI11<3> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI11<2> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI11<1> VDD VSS / RSC_IHPSG13_FILLCAP8 +.ENDS + +.SUBCKT RM_IHPSG13_256x16_c2_1P_ROWDEC9 ADDR_N_I<8> ADDR_N_I<7> ADDR_N_I<6> ADDR_N_I<5> ++ ADDR_N_I<4> ADDR_N_I<3> ADDR_N_I<2> ADDR_N_I<1> ADDR_N_I<0> CS_I ECLK_I ++ WL_O<511> WL_O<510> WL_O<509> WL_O<508> WL_O<507> WL_O<506> WL_O<505> ++ WL_O<504> WL_O<503> WL_O<502> WL_O<501> WL_O<500> WL_O<499> WL_O<498> ++ WL_O<497> WL_O<496> WL_O<495> WL_O<494> WL_O<493> WL_O<492> WL_O<491> ++ WL_O<490> WL_O<489> WL_O<488> WL_O<487> WL_O<486> WL_O<485> WL_O<484> ++ WL_O<483> WL_O<482> WL_O<481> WL_O<480> WL_O<479> WL_O<478> WL_O<477> ++ WL_O<476> WL_O<475> WL_O<474> WL_O<473> WL_O<472> WL_O<471> WL_O<470> ++ WL_O<469> WL_O<468> WL_O<467> WL_O<466> WL_O<465> WL_O<464> WL_O<463> ++ WL_O<462> WL_O<461> WL_O<460> WL_O<459> WL_O<458> WL_O<457> WL_O<456> ++ WL_O<455> WL_O<454> WL_O<453> WL_O<452> WL_O<451> WL_O<450> WL_O<449> ++ WL_O<448> WL_O<447> WL_O<446> WL_O<445> WL_O<444> WL_O<443> WL_O<442> ++ WL_O<441> WL_O<440> WL_O<439> WL_O<438> WL_O<437> WL_O<436> WL_O<435> ++ WL_O<434> WL_O<433> WL_O<432> WL_O<431> WL_O<430> WL_O<429> WL_O<428> ++ WL_O<427> WL_O<426> WL_O<425> WL_O<424> WL_O<423> WL_O<422> WL_O<421> ++ WL_O<420> WL_O<419> WL_O<418> WL_O<417> WL_O<416> WL_O<415> WL_O<414> ++ WL_O<413> WL_O<412> WL_O<411> WL_O<410> WL_O<409> WL_O<408> WL_O<407> ++ WL_O<406> WL_O<405> WL_O<404> WL_O<403> WL_O<402> WL_O<401> WL_O<400> ++ WL_O<399> WL_O<398> WL_O<397> WL_O<396> WL_O<395> WL_O<394> WL_O<393> ++ WL_O<392> WL_O<391> WL_O<390> WL_O<389> WL_O<388> WL_O<387> WL_O<386> ++ WL_O<385> WL_O<384> WL_O<383> WL_O<382> WL_O<381> WL_O<380> WL_O<379> ++ WL_O<378> WL_O<377> WL_O<376> WL_O<375> WL_O<374> WL_O<373> WL_O<372> ++ WL_O<371> WL_O<370> WL_O<369> WL_O<368> WL_O<367> WL_O<366> WL_O<365> ++ WL_O<364> WL_O<363> WL_O<362> WL_O<361> WL_O<360> WL_O<359> WL_O<358> ++ WL_O<357> WL_O<356> WL_O<355> WL_O<354> WL_O<353> WL_O<352> WL_O<351> ++ WL_O<350> WL_O<349> WL_O<348> WL_O<347> WL_O<346> WL_O<345> WL_O<344> ++ WL_O<343> WL_O<342> WL_O<341> WL_O<340> WL_O<339> WL_O<338> WL_O<337> ++ WL_O<336> WL_O<335> WL_O<334> WL_O<333> WL_O<332> WL_O<331> WL_O<330> ++ WL_O<329> WL_O<328> WL_O<327> WL_O<326> WL_O<325> WL_O<324> WL_O<323> ++ WL_O<322> WL_O<321> WL_O<320> WL_O<319> WL_O<318> WL_O<317> WL_O<316> ++ WL_O<315> WL_O<314> WL_O<313> WL_O<312> WL_O<311> WL_O<310> WL_O<309> ++ WL_O<308> WL_O<307> WL_O<306> WL_O<305> WL_O<304> WL_O<303> WL_O<302> ++ WL_O<301> WL_O<300> WL_O<299> WL_O<298> WL_O<297> WL_O<296> WL_O<295> ++ WL_O<294> WL_O<293> WL_O<292> WL_O<291> WL_O<290> WL_O<289> WL_O<288> ++ WL_O<287> WL_O<286> WL_O<285> WL_O<284> WL_O<283> WL_O<282> WL_O<281> ++ WL_O<280> WL_O<279> WL_O<278> WL_O<277> WL_O<276> WL_O<275> WL_O<274> ++ WL_O<273> WL_O<272> WL_O<271> WL_O<270> WL_O<269> WL_O<268> WL_O<267> ++ WL_O<266> WL_O<265> WL_O<264> WL_O<263> WL_O<262> WL_O<261> WL_O<260> ++ WL_O<259> WL_O<258> WL_O<257> WL_O<256> WL_O<255> WL_O<254> WL_O<253> ++ WL_O<252> WL_O<251> WL_O<250> WL_O<249> WL_O<248> WL_O<247> WL_O<246> ++ WL_O<245> WL_O<244> WL_O<243> WL_O<242> WL_O<241> WL_O<240> WL_O<239> ++ WL_O<238> WL_O<237> WL_O<236> WL_O<235> WL_O<234> WL_O<233> WL_O<232> ++ WL_O<231> WL_O<230> WL_O<229> WL_O<228> WL_O<227> WL_O<226> WL_O<225> ++ WL_O<224> WL_O<223> WL_O<222> WL_O<221> WL_O<220> WL_O<219> WL_O<218> ++ WL_O<217> WL_O<216> WL_O<215> WL_O<214> WL_O<213> WL_O<212> WL_O<211> ++ WL_O<210> WL_O<209> WL_O<208> WL_O<207> WL_O<206> WL_O<205> WL_O<204> ++ WL_O<203> WL_O<202> WL_O<201> WL_O<200> WL_O<199> WL_O<198> WL_O<197> ++ WL_O<196> WL_O<195> WL_O<194> WL_O<193> WL_O<192> WL_O<191> WL_O<190> ++ WL_O<189> WL_O<188> WL_O<187> WL_O<186> WL_O<185> WL_O<184> WL_O<183> ++ WL_O<182> WL_O<181> WL_O<180> WL_O<179> WL_O<178> WL_O<177> WL_O<176> ++ WL_O<175> WL_O<174> WL_O<173> WL_O<172> WL_O<171> WL_O<170> WL_O<169> ++ WL_O<168> WL_O<167> WL_O<166> WL_O<165> WL_O<164> WL_O<163> WL_O<162> ++ WL_O<161> WL_O<160> WL_O<159> WL_O<158> WL_O<157> WL_O<156> WL_O<155> ++ WL_O<154> WL_O<153> WL_O<152> WL_O<151> WL_O<150> WL_O<149> WL_O<148> ++ WL_O<147> WL_O<146> WL_O<145> WL_O<144> WL_O<143> WL_O<142> WL_O<141> ++ WL_O<140> WL_O<139> WL_O<138> WL_O<137> WL_O<136> WL_O<135> WL_O<134> ++ WL_O<133> WL_O<132> WL_O<131> WL_O<130> WL_O<129> WL_O<128> WL_O<127> ++ WL_O<126> WL_O<125> WL_O<124> WL_O<123> WL_O<122> WL_O<121> WL_O<120> ++ WL_O<119> WL_O<118> WL_O<117> WL_O<116> WL_O<115> WL_O<114> WL_O<113> ++ WL_O<112> WL_O<111> WL_O<110> WL_O<109> WL_O<108> WL_O<107> WL_O<106> ++ WL_O<105> WL_O<104> WL_O<103> WL_O<102> WL_O<101> WL_O<100> WL_O<99> ++ WL_O<98> WL_O<97> WL_O<96> WL_O<95> WL_O<94> WL_O<93> WL_O<92> WL_O<91> ++ WL_O<90> WL_O<89> WL_O<88> WL_O<87> WL_O<86> WL_O<85> WL_O<84> WL_O<83> ++ WL_O<82> WL_O<81> WL_O<80> WL_O<79> WL_O<78> WL_O<77> WL_O<76> WL_O<75> ++ WL_O<74> WL_O<73> WL_O<72> WL_O<71> WL_O<70> WL_O<69> WL_O<68> WL_O<67> ++ WL_O<66> WL_O<65> WL_O<64> WL_O<63> WL_O<62> WL_O<61> WL_O<60> WL_O<59> ++ WL_O<58> WL_O<57> WL_O<56> WL_O<55> WL_O<54> WL_O<53> WL_O<52> WL_O<51> ++ WL_O<50> WL_O<49> WL_O<48> WL_O<47> WL_O<46> WL_O<45> WL_O<44> WL_O<43> ++ WL_O<42> WL_O<41> WL_O<40> WL_O<39> WL_O<38> WL_O<37> WL_O<36> WL_O<35> ++ WL_O<34> WL_O<33> WL_O<32> WL_O<31> WL_O<30> WL_O<29> WL_O<28> WL_O<27> ++ WL_O<26> WL_O<25> WL_O<24> WL_O<23> WL_O<22> WL_O<21> WL_O<20> WL_O<19> ++ WL_O<18> WL_O<17> WL_O<16> WL_O<15> WL_O<14> WL_O<13> WL_O<12> WL_O<11> ++ WL_O<10> WL_O<9> WL_O<8> WL_O<7> WL_O<6> WL_O<5> WL_O<4> WL_O<3> WL_O<2> ++ WL_O<1> WL_O<0> VDD VSS +XL2<172> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<171> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<170> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<169> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<168> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<167> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<166> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<165> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<164> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<163> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<162> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<161> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<160> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<159> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<158> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<157> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<156> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<155> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<154> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<153> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<152> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<151> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<150> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<149> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<148> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<147> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<146> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<145> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<144> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<143> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<142> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<141> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<140> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<139> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<138> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<137> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<136> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<135> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<134> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<133> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<132> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<131> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<130> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<129> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<128> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<127> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<126> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<125> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<124> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<123> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<122> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<121> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<120> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<119> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<118> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<117> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<116> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<115> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<114> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<113> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<112> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<111> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<110> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<109> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<108> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<107> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<106> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<105> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<104> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<103> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<102> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<101> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<100> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<99> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<98> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<97> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<96> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<95> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<94> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<93> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<92> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<91> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<90> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<89> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<88> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<87> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<86> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<85> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<84> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<83> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<82> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<81> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<80> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<79> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<78> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<77> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<76> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<75> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<74> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<73> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<72> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<71> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<70> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<69> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<68> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<67> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<66> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<65> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<64> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<63> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<62> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<61> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<60> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<59> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<58> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<57> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<56> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<55> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<54> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<53> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<52> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<51> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<50> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<49> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<48> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<47> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<46> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<45> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<44> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<43> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<42> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<41> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<40> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<39> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<38> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<37> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<36> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<35> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<34> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<33> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<32> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<31> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<30> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<29> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<28> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<27> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<26> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<25> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<24> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<23> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<22> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<21> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<20> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<19> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<18> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<17> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<16> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<15> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<14> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<13> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<12> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<11> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<10> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<9> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<8> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<7> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<6> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<5> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<4> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<3> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<2> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<1> VDD VSS / RSC_IHPSG13_FILLCAP8 +XDEC11<9> ADDR_N_I<7> ADDR_N_I<6> CS04<1> CS02<7> VDD VSS / ++ RM_IHPSG13_256x16_c2_1P_DEC03 +XDEC11<8> ADDR_N_I<7> ADDR_N_I<6> CS04<0> CS02<3> VDD VSS / ++ RM_IHPSG13_256x16_c2_1P_DEC03 +XDEC11<7> ADDR_N_I<5> ADDR_N_I<4> CS02<7> CS00<31> VDD VSS / ++ RM_IHPSG13_256x16_c2_1P_DEC03 +XDEC11<6> ADDR_N_I<5> ADDR_N_I<4> CS02<6> CS00<27> VDD VSS / ++ RM_IHPSG13_256x16_c2_1P_DEC03 +XDEC11<5> ADDR_N_I<5> ADDR_N_I<4> CS02<5> CS00<23> VDD VSS / ++ RM_IHPSG13_256x16_c2_1P_DEC03 +XDEC11<4> ADDR_N_I<5> ADDR_N_I<4> CS02<4> CS00<19> VDD VSS / ++ RM_IHPSG13_256x16_c2_1P_DEC03 +XDEC11<3> ADDR_N_I<5> ADDR_N_I<4> CS02<3> CS00<15> VDD VSS / ++ RM_IHPSG13_256x16_c2_1P_DEC03 +XDEC11<2> ADDR_N_I<5> ADDR_N_I<4> CS02<2> CS00<11> VDD VSS / ++ RM_IHPSG13_256x16_c2_1P_DEC03 +XDEC11<1> ADDR_N_I<5> ADDR_N_I<4> CS02<1> CS00<7> VDD VSS / ++ RM_IHPSG13_256x16_c2_1P_DEC03 +XDEC11<0> ADDR_N_I<5> ADDR_N_I<4> CS02<0> CS00<3> VDD VSS / ++ RM_IHPSG13_256x16_c2_1P_DEC03 +XDEC00<10> ADDR_N_I<9> ADDR_N_I<8> CS_I CS04<0> VDD VSS / ++ RM_IHPSG13_256x16_c2_1P_DEC00 +XDEC00<9> ADDR_N_I<7> ADDR_N_I<6> CS04<1> CS02<4> VDD VSS / ++ RM_IHPSG13_256x16_c2_1P_DEC00 +XDEC00<8> ADDR_N_I<7> ADDR_N_I<6> CS04<0> CS02<0> VDD VSS / ++ RM_IHPSG13_256x16_c2_1P_DEC00 +XDEC00<7> ADDR_N_I<5> ADDR_N_I<4> CS02<7> CS00<28> VDD VSS / ++ RM_IHPSG13_256x16_c2_1P_DEC00 +XDEC00<6> ADDR_N_I<5> ADDR_N_I<4> CS02<6> CS00<24> VDD VSS / ++ RM_IHPSG13_256x16_c2_1P_DEC00 +XDEC00<5> ADDR_N_I<5> ADDR_N_I<4> CS02<5> CS00<20> VDD VSS / ++ RM_IHPSG13_256x16_c2_1P_DEC00 +XDEC00<4> ADDR_N_I<5> ADDR_N_I<4> CS02<4> CS00<16> VDD VSS / ++ RM_IHPSG13_256x16_c2_1P_DEC00 +XDEC00<3> ADDR_N_I<5> ADDR_N_I<4> CS02<3> CS00<12> VDD VSS / ++ RM_IHPSG13_256x16_c2_1P_DEC00 +XDEC00<2> ADDR_N_I<5> ADDR_N_I<4> CS02<2> CS00<8> VDD VSS / ++ RM_IHPSG13_256x16_c2_1P_DEC00 +XDEC00<1> ADDR_N_I<5> ADDR_N_I<4> CS02<1> CS00<4> VDD VSS / ++ RM_IHPSG13_256x16_c2_1P_DEC00 +XDEC00<0> ADDR_N_I<5> ADDR_N_I<4> CS02<0> CS00<0> VDD VSS / ++ RM_IHPSG13_256x16_c2_1P_DEC00 +XSEL<31> ADDR_N_I<3> ADDR_N_I<2> ADDR_N_I<1> ADDR_N_I<0> CS00<31> ECLK_H<31> ++ ECLK_H<32> ECLK_B<31> ECLK_B<32> WL_O<511> WL_O<510> WL_O<509> WL_O<508> ++ WL_O<507> WL_O<506> WL_O<505> WL_O<504> WL_O<503> WL_O<502> WL_O<501> ++ WL_O<500> WL_O<499> WL_O<498> WL_O<497> WL_O<496> VDD VSS / ++ RM_IHPSG13_256x16_c2_1P_DEC04 +XSEL<30> ADDR_N_I<3> ADDR_N_I<2> ADDR_N_I<1> ADDR_N_I<0> CS00<30> ECLK_H<30> ++ ECLK_H<31> ECLK_B<30> ECLK_B<31> WL_O<495> WL_O<494> WL_O<493> WL_O<492> ++ WL_O<491> WL_O<490> WL_O<489> WL_O<488> WL_O<487> WL_O<486> WL_O<485> ++ WL_O<484> WL_O<483> WL_O<482> WL_O<481> WL_O<480> VDD VSS / ++ RM_IHPSG13_256x16_c2_1P_DEC04 +XSEL<29> ADDR_N_I<3> ADDR_N_I<2> ADDR_N_I<1> ADDR_N_I<0> CS00<29> ECLK_H<29> ++ ECLK_H<30> ECLK_B<29> ECLK_B<30> WL_O<479> WL_O<478> WL_O<477> WL_O<476> ++ WL_O<475> WL_O<474> WL_O<473> WL_O<472> WL_O<471> WL_O<470> WL_O<469> ++ WL_O<468> WL_O<467> WL_O<466> WL_O<465> WL_O<464> VDD VSS / ++ RM_IHPSG13_256x16_c2_1P_DEC04 +XSEL<28> ADDR_N_I<3> ADDR_N_I<2> ADDR_N_I<1> ADDR_N_I<0> CS00<28> ECLK_H<28> ++ ECLK_H<29> ECLK_B<28> ECLK_B<29> WL_O<463> WL_O<462> WL_O<461> WL_O<460> ++ WL_O<459> WL_O<458> WL_O<457> WL_O<456> WL_O<455> WL_O<454> WL_O<453> ++ WL_O<452> WL_O<451> WL_O<450> WL_O<449> WL_O<448> VDD VSS / ++ RM_IHPSG13_256x16_c2_1P_DEC04 +XSEL<27> ADDR_N_I<3> ADDR_N_I<2> ADDR_N_I<1> ADDR_N_I<0> CS00<27> ECLK_H<27> ++ ECLK_H<28> ECLK_B<27> ECLK_B<28> WL_O<447> WL_O<446> WL_O<445> WL_O<444> ++ WL_O<443> WL_O<442> WL_O<441> WL_O<440> WL_O<439> WL_O<438> WL_O<437> ++ WL_O<436> WL_O<435> WL_O<434> WL_O<433> WL_O<432> VDD VSS / ++ RM_IHPSG13_256x16_c2_1P_DEC04 +XSEL<26> ADDR_N_I<3> ADDR_N_I<2> ADDR_N_I<1> ADDR_N_I<0> CS00<26> ECLK_H<26> ++ ECLK_H<27> ECLK_B<26> ECLK_B<27> WL_O<431> WL_O<430> WL_O<429> WL_O<428> ++ WL_O<427> WL_O<426> WL_O<425> WL_O<424> WL_O<423> WL_O<422> WL_O<421> ++ WL_O<420> WL_O<419> WL_O<418> WL_O<417> WL_O<416> VDD VSS / ++ RM_IHPSG13_256x16_c2_1P_DEC04 +XSEL<25> ADDR_N_I<3> ADDR_N_I<2> ADDR_N_I<1> ADDR_N_I<0> CS00<25> ECLK_H<25> ++ ECLK_H<26> ECLK_B<25> ECLK_B<26> WL_O<415> WL_O<414> WL_O<413> WL_O<412> ++ WL_O<411> WL_O<410> WL_O<409> WL_O<408> WL_O<407> WL_O<406> WL_O<405> ++ WL_O<404> WL_O<403> WL_O<402> WL_O<401> WL_O<400> VDD VSS / ++ RM_IHPSG13_256x16_c2_1P_DEC04 +XSEL<24> ADDR_N_I<3> ADDR_N_I<2> ADDR_N_I<1> ADDR_N_I<0> CS00<24> ECLK_H<24> ++ ECLK_H<25> ECLK_B<24> ECLK_B<25> WL_O<399> WL_O<398> WL_O<397> WL_O<396> ++ WL_O<395> WL_O<394> WL_O<393> WL_O<392> WL_O<391> WL_O<390> WL_O<389> ++ WL_O<388> WL_O<387> WL_O<386> WL_O<385> WL_O<384> VDD VSS / ++ RM_IHPSG13_256x16_c2_1P_DEC04 +XSEL<23> ADDR_N_I<3> ADDR_N_I<2> ADDR_N_I<1> ADDR_N_I<0> CS00<23> ECLK_H<23> ++ ECLK_H<24> ECLK_B<23> ECLK_B<24> WL_O<383> WL_O<382> WL_O<381> WL_O<380> ++ WL_O<379> WL_O<378> WL_O<377> WL_O<376> WL_O<375> WL_O<374> WL_O<373> ++ WL_O<372> WL_O<371> WL_O<370> WL_O<369> WL_O<368> VDD VSS / ++ RM_IHPSG13_256x16_c2_1P_DEC04 +XSEL<22> ADDR_N_I<3> ADDR_N_I<2> ADDR_N_I<1> ADDR_N_I<0> CS00<22> ECLK_H<22> ++ ECLK_H<23> ECLK_B<22> ECLK_B<23> WL_O<367> WL_O<366> WL_O<365> WL_O<364> ++ WL_O<363> WL_O<362> WL_O<361> WL_O<360> WL_O<359> WL_O<358> WL_O<357> ++ WL_O<356> WL_O<355> WL_O<354> WL_O<353> WL_O<352> VDD VSS / ++ RM_IHPSG13_256x16_c2_1P_DEC04 +XSEL<21> ADDR_N_I<3> ADDR_N_I<2> ADDR_N_I<1> ADDR_N_I<0> CS00<21> ECLK_H<21> ++ ECLK_H<22> ECLK_B<21> ECLK_B<22> WL_O<351> WL_O<350> WL_O<349> WL_O<348> ++ WL_O<347> WL_O<346> WL_O<345> WL_O<344> WL_O<343> WL_O<342> WL_O<341> ++ WL_O<340> WL_O<339> WL_O<338> WL_O<337> WL_O<336> VDD VSS / ++ RM_IHPSG13_256x16_c2_1P_DEC04 +XSEL<20> ADDR_N_I<3> ADDR_N_I<2> ADDR_N_I<1> ADDR_N_I<0> CS00<20> ECLK_H<20> ++ ECLK_H<21> ECLK_B<20> ECLK_B<21> WL_O<335> WL_O<334> WL_O<333> WL_O<332> ++ WL_O<331> WL_O<330> WL_O<329> WL_O<328> WL_O<327> WL_O<326> WL_O<325> ++ WL_O<324> WL_O<323> WL_O<322> WL_O<321> WL_O<320> VDD VSS / ++ RM_IHPSG13_256x16_c2_1P_DEC04 +XSEL<19> ADDR_N_I<3> ADDR_N_I<2> ADDR_N_I<1> ADDR_N_I<0> CS00<19> ECLK_H<19> ++ ECLK_H<20> ECLK_B<19> ECLK_B<20> WL_O<319> WL_O<318> WL_O<317> WL_O<316> ++ WL_O<315> WL_O<314> WL_O<313> WL_O<312> WL_O<311> WL_O<310> WL_O<309> ++ WL_O<308> WL_O<307> WL_O<306> WL_O<305> WL_O<304> VDD VSS / ++ RM_IHPSG13_256x16_c2_1P_DEC04 +XSEL<18> ADDR_N_I<3> ADDR_N_I<2> ADDR_N_I<1> ADDR_N_I<0> CS00<18> ECLK_H<18> ++ ECLK_H<19> ECLK_B<18> ECLK_B<19> WL_O<303> WL_O<302> WL_O<301> WL_O<300> ++ WL_O<299> WL_O<298> WL_O<297> WL_O<296> WL_O<295> WL_O<294> WL_O<293> ++ WL_O<292> WL_O<291> WL_O<290> WL_O<289> WL_O<288> VDD VSS / ++ RM_IHPSG13_256x16_c2_1P_DEC04 +XSEL<17> ADDR_N_I<3> ADDR_N_I<2> ADDR_N_I<1> ADDR_N_I<0> CS00<17> ECLK_H<17> ++ ECLK_H<18> ECLK_B<17> ECLK_B<18> WL_O<287> WL_O<286> WL_O<285> WL_O<284> ++ WL_O<283> WL_O<282> WL_O<281> WL_O<280> WL_O<279> WL_O<278> WL_O<277> ++ WL_O<276> WL_O<275> WL_O<274> WL_O<273> WL_O<272> VDD VSS / ++ RM_IHPSG13_256x16_c2_1P_DEC04 +XSEL<16> ADDR_N_I<3> ADDR_N_I<2> ADDR_N_I<1> ADDR_N_I<0> CS00<16> ECLK_H<16> ++ ECLK_H<17> ECLK_B<16> ECLK_B<17> WL_O<271> WL_O<270> WL_O<269> WL_O<268> ++ WL_O<267> WL_O<266> WL_O<265> WL_O<264> WL_O<263> WL_O<262> WL_O<261> ++ WL_O<260> WL_O<259> WL_O<258> WL_O<257> WL_O<256> VDD VSS / ++ RM_IHPSG13_256x16_c2_1P_DEC04 +XSEL<15> ADDR_N_I<3> ADDR_N_I<2> ADDR_N_I<1> ADDR_N_I<0> CS00<15> ECLK_H<15> ++ ECLK_H<16> ECLK_B<15> ECLK_B<16> WL_O<255> WL_O<254> WL_O<253> WL_O<252> ++ WL_O<251> WL_O<250> WL_O<249> WL_O<248> WL_O<247> WL_O<246> WL_O<245> ++ WL_O<244> WL_O<243> WL_O<242> WL_O<241> WL_O<240> VDD VSS / ++ RM_IHPSG13_256x16_c2_1P_DEC04 +XSEL<14> ADDR_N_I<3> ADDR_N_I<2> ADDR_N_I<1> ADDR_N_I<0> CS00<14> ECLK_H<14> ++ ECLK_H<15> ECLK_B<14> ECLK_B<15> WL_O<239> WL_O<238> WL_O<237> WL_O<236> ++ WL_O<235> WL_O<234> WL_O<233> WL_O<232> WL_O<231> WL_O<230> WL_O<229> ++ WL_O<228> WL_O<227> WL_O<226> WL_O<225> WL_O<224> VDD VSS / ++ RM_IHPSG13_256x16_c2_1P_DEC04 +XSEL<13> ADDR_N_I<3> ADDR_N_I<2> ADDR_N_I<1> ADDR_N_I<0> CS00<13> ECLK_H<13> ++ ECLK_H<14> ECLK_B<13> ECLK_B<14> WL_O<223> WL_O<222> WL_O<221> WL_O<220> ++ WL_O<219> WL_O<218> WL_O<217> WL_O<216> WL_O<215> WL_O<214> WL_O<213> ++ WL_O<212> WL_O<211> WL_O<210> WL_O<209> WL_O<208> VDD VSS / ++ RM_IHPSG13_256x16_c2_1P_DEC04 +XSEL<12> ADDR_N_I<3> ADDR_N_I<2> ADDR_N_I<1> ADDR_N_I<0> CS00<12> ECLK_H<12> ++ ECLK_H<13> ECLK_B<12> ECLK_B<13> WL_O<207> WL_O<206> WL_O<205> WL_O<204> ++ WL_O<203> WL_O<202> WL_O<201> WL_O<200> WL_O<199> WL_O<198> WL_O<197> ++ WL_O<196> WL_O<195> WL_O<194> WL_O<193> WL_O<192> VDD VSS / ++ RM_IHPSG13_256x16_c2_1P_DEC04 +XSEL<11> ADDR_N_I<3> ADDR_N_I<2> ADDR_N_I<1> ADDR_N_I<0> CS00<11> ECLK_H<11> ++ ECLK_H<12> ECLK_B<11> ECLK_B<12> WL_O<191> WL_O<190> WL_O<189> WL_O<188> ++ WL_O<187> WL_O<186> WL_O<185> WL_O<184> WL_O<183> WL_O<182> WL_O<181> ++ WL_O<180> WL_O<179> WL_O<178> WL_O<177> WL_O<176> VDD VSS / ++ RM_IHPSG13_256x16_c2_1P_DEC04 +XSEL<10> ADDR_N_I<3> ADDR_N_I<2> ADDR_N_I<1> ADDR_N_I<0> CS00<10> ECLK_H<10> ++ ECLK_H<11> ECLK_B<10> ECLK_B<11> WL_O<175> WL_O<174> WL_O<173> WL_O<172> ++ WL_O<171> WL_O<170> WL_O<169> WL_O<168> WL_O<167> WL_O<166> WL_O<165> ++ WL_O<164> WL_O<163> WL_O<162> WL_O<161> WL_O<160> VDD VSS / ++ RM_IHPSG13_256x16_c2_1P_DEC04 +XSEL<9> ADDR_N_I<3> ADDR_N_I<2> ADDR_N_I<1> ADDR_N_I<0> CS00<9> ECLK_H<9> ++ ECLK_H<10> ECLK_B<9> ECLK_B<10> WL_O<159> WL_O<158> WL_O<157> WL_O<156> ++ WL_O<155> WL_O<154> WL_O<153> WL_O<152> WL_O<151> WL_O<150> WL_O<149> ++ WL_O<148> WL_O<147> WL_O<146> WL_O<145> WL_O<144> VDD VSS / ++ RM_IHPSG13_256x16_c2_1P_DEC04 +XSEL<8> ADDR_N_I<3> ADDR_N_I<2> ADDR_N_I<1> ADDR_N_I<0> CS00<8> ECLK_H<8> ++ ECLK_H<9> ECLK_B<8> ECLK_B<9> WL_O<143> WL_O<142> WL_O<141> WL_O<140> ++ WL_O<139> WL_O<138> WL_O<137> WL_O<136> WL_O<135> WL_O<134> WL_O<133> ++ WL_O<132> WL_O<131> WL_O<130> WL_O<129> WL_O<128> VDD VSS / ++ RM_IHPSG13_256x16_c2_1P_DEC04 +XSEL<7> ADDR_N_I<3> ADDR_N_I<2> ADDR_N_I<1> ADDR_N_I<0> CS00<7> ECLK_H<7> ++ ECLK_H<8> ECLK_B<7> ECLK_B<8> WL_O<127> WL_O<126> WL_O<125> WL_O<124> ++ WL_O<123> WL_O<122> WL_O<121> WL_O<120> WL_O<119> WL_O<118> WL_O<117> ++ WL_O<116> WL_O<115> WL_O<114> WL_O<113> WL_O<112> VDD VSS / ++ RM_IHPSG13_256x16_c2_1P_DEC04 +XSEL<6> ADDR_N_I<3> ADDR_N_I<2> ADDR_N_I<1> ADDR_N_I<0> CS00<6> ECLK_H<6> ++ ECLK_H<7> ECLK_B<6> ECLK_B<7> WL_O<111> WL_O<110> WL_O<109> WL_O<108> ++ WL_O<107> WL_O<106> WL_O<105> WL_O<104> WL_O<103> WL_O<102> WL_O<101> ++ WL_O<100> WL_O<99> WL_O<98> WL_O<97> WL_O<96> VDD VSS / ++ RM_IHPSG13_256x16_c2_1P_DEC04 +XSEL<5> ADDR_N_I<3> ADDR_N_I<2> ADDR_N_I<1> ADDR_N_I<0> CS00<5> ECLK_H<5> ++ ECLK_H<6> ECLK_B<5> ECLK_B<6> WL_O<95> WL_O<94> WL_O<93> WL_O<92> WL_O<91> ++ WL_O<90> WL_O<89> WL_O<88> WL_O<87> WL_O<86> WL_O<85> WL_O<84> WL_O<83> ++ WL_O<82> WL_O<81> WL_O<80> VDD VSS / RM_IHPSG13_256x16_c2_1P_DEC04 +XSEL<4> ADDR_N_I<3> ADDR_N_I<2> ADDR_N_I<1> ADDR_N_I<0> CS00<4> ECLK_H<4> ++ ECLK_H<5> ECLK_B<4> ECLK_B<5> WL_O<79> WL_O<78> WL_O<77> WL_O<76> WL_O<75> ++ WL_O<74> WL_O<73> WL_O<72> WL_O<71> WL_O<70> WL_O<69> WL_O<68> WL_O<67> ++ WL_O<66> WL_O<65> WL_O<64> VDD VSS / RM_IHPSG13_256x16_c2_1P_DEC04 +XSEL<3> ADDR_N_I<3> ADDR_N_I<2> ADDR_N_I<1> ADDR_N_I<0> CS00<3> ECLK_H<3> ++ ECLK_H<4> ECLK_B<3> ECLK_B<4> WL_O<63> WL_O<62> WL_O<61> WL_O<60> WL_O<59> ++ WL_O<58> WL_O<57> WL_O<56> WL_O<55> WL_O<54> WL_O<53> WL_O<52> WL_O<51> ++ WL_O<50> WL_O<49> WL_O<48> VDD VSS / RM_IHPSG13_256x16_c2_1P_DEC04 +XSEL<2> ADDR_N_I<3> ADDR_N_I<2> ADDR_N_I<1> ADDR_N_I<0> CS00<2> ECLK_H<2> ++ ECLK_H<3> ECLK_B<2> ECLK_B<3> WL_O<47> WL_O<46> WL_O<45> WL_O<44> WL_O<43> ++ WL_O<42> WL_O<41> WL_O<40> WL_O<39> WL_O<38> WL_O<37> WL_O<36> WL_O<35> ++ WL_O<34> WL_O<33> WL_O<32> VDD VSS / RM_IHPSG13_256x16_c2_1P_DEC04 +XSEL<1> ADDR_N_I<3> ADDR_N_I<2> ADDR_N_I<1> ADDR_N_I<0> CS00<1> ECLK_H<1> ++ ECLK_H<2> ECLK_B<1> ECLK_B<2> WL_O<31> WL_O<30> WL_O<29> WL_O<28> WL_O<27> ++ WL_O<26> WL_O<25> WL_O<24> WL_O<23> WL_O<22> WL_O<21> WL_O<20> WL_O<19> ++ WL_O<18> WL_O<17> WL_O<16> VDD VSS / RM_IHPSG13_256x16_c2_1P_DEC04 +XSEL<0> ADDR_N_I<3> ADDR_N_I<2> ADDR_N_I<1> ADDR_N_I<0> CS00<0> ECLK_I ++ ECLK_H<1> ECLK_B<0> ECLK_B<1> WL_O<15> WL_O<14> WL_O<13> WL_O<12> WL_O<11> ++ WL_O<10> WL_O<9> WL_O<8> WL_O<7> WL_O<6> WL_O<5> WL_O<4> WL_O<3> WL_O<2> ++ WL_O<1> WL_O<0> VDD VSS / RM_IHPSG13_256x16_c2_1P_DEC04 +XDEC01<10> ADDR_N_I<9> ADDR_N_I<8> CS_I CS04<1> VDD VSS / ++ RM_IHPSG13_256x16_c2_1P_DEC01 +XDEC01<9> ADDR_N_I<7> ADDR_N_I<6> CS04<1> CS02<5> VDD VSS / ++ RM_IHPSG13_256x16_c2_1P_DEC01 +XDEC01<8> ADDR_N_I<7> ADDR_N_I<6> CS04<0> CS02<1> VDD VSS / ++ RM_IHPSG13_256x16_c2_1P_DEC01 +XDEC01<7> ADDR_N_I<5> ADDR_N_I<4> CS02<7> CS00<29> VDD VSS / ++ RM_IHPSG13_256x16_c2_1P_DEC01 +XDEC01<6> ADDR_N_I<5> ADDR_N_I<4> CS02<6> CS00<25> VDD VSS / ++ RM_IHPSG13_256x16_c2_1P_DEC01 +XDEC01<5> ADDR_N_I<5> ADDR_N_I<4> CS02<5> CS00<21> VDD VSS / ++ RM_IHPSG13_256x16_c2_1P_DEC01 +XDEC01<4> ADDR_N_I<5> ADDR_N_I<4> CS02<4> CS00<17> VDD VSS / ++ RM_IHPSG13_256x16_c2_1P_DEC01 +XDEC01<3> ADDR_N_I<5> ADDR_N_I<4> CS02<3> CS00<13> VDD VSS / ++ RM_IHPSG13_256x16_c2_1P_DEC01 +XDEC01<2> ADDR_N_I<5> ADDR_N_I<4> CS02<2> CS00<9> VDD VSS / ++ RM_IHPSG13_256x16_c2_1P_DEC01 +XDEC01<1> ADDR_N_I<5> ADDR_N_I<4> CS02<1> CS00<5> VDD VSS / ++ RM_IHPSG13_256x16_c2_1P_DEC01 +XDEC01<0> ADDR_N_I<5> ADDR_N_I<4> CS02<0> CS00<1> VDD VSS / ++ RM_IHPSG13_256x16_c2_1P_DEC01 +XDEC10<9> ADDR_N_I<7> ADDR_N_I<6> CS04<1> CS02<6> VDD VSS / ++ RM_IHPSG13_256x16_c2_1P_DEC02 +XDEC10<8> ADDR_N_I<7> ADDR_N_I<6> CS04<0> CS02<2> VDD VSS / ++ RM_IHPSG13_256x16_c2_1P_DEC02 +XDEC10<7> ADDR_N_I<5> ADDR_N_I<4> CS02<7> CS00<30> VDD VSS / ++ RM_IHPSG13_256x16_c2_1P_DEC02 +XDEC10<6> ADDR_N_I<5> ADDR_N_I<4> CS02<6> CS00<26> VDD VSS / ++ RM_IHPSG13_256x16_c2_1P_DEC02 +XDEC10<5> ADDR_N_I<5> ADDR_N_I<4> CS02<5> CS00<22> VDD VSS / ++ RM_IHPSG13_256x16_c2_1P_DEC02 +XDEC10<4> ADDR_N_I<5> ADDR_N_I<4> CS02<4> CS00<18> VDD VSS / ++ RM_IHPSG13_256x16_c2_1P_DEC02 +XDEC10<3> ADDR_N_I<5> ADDR_N_I<4> CS02<3> CS00<14> VDD VSS / ++ RM_IHPSG13_256x16_c2_1P_DEC02 +XDEC10<2> ADDR_N_I<5> ADDR_N_I<4> CS02<2> CS00<10> VDD VSS / ++ RM_IHPSG13_256x16_c2_1P_DEC02 +XDEC10<1> ADDR_N_I<5> ADDR_N_I<4> CS02<1> CS00<6> VDD VSS / ++ RM_IHPSG13_256x16_c2_1P_DEC02 +XDEC10<0> ADDR_N_I<5> ADDR_N_I<4> CS02<0> CS00<2> VDD VSS / ++ RM_IHPSG13_256x16_c2_1P_DEC02 +XI0 ADDR_N_I<9> VDD VSS / RSC_IHPSG13_TIEL +.ENDS +.SUBCKT RM_IHPSG13_256x16_c2_1P_ROWREG9 ACLK_N_I ADDR_I<8> ADDR_I<7> ADDR_I<6> ADDR_I<5> ++ ADDR_I<4> ADDR_I<3> ADDR_I<2> ADDR_I<1> ADDR_I<0> ADDR_N_O<8> ADDR_N_O<7> ++ ADDR_N_O<6> ADDR_N_O<5> ADDR_N_O<4> ADDR_N_O<3> ADDR_N_O<2> ADDR_N_O<1> ++ ADDR_N_O<0> BIST_ADDR_I<8> BIST_ADDR_I<7> BIST_ADDR_I<6> BIST_ADDR_I<5> ++ BIST_ADDR_I<4> BIST_ADDR_I<3> BIST_ADDR_I<2> BIST_ADDR_I<1> BIST_ADDR_I<0> ++ BIST_EN_I VDD VSS +XINV<8> q_int<8> qn_int<8> VDD VSS / RSC_IHPSG13_CINVX2 +XINV<7> q_int<7> qn_int<7> VDD VSS / RSC_IHPSG13_CINVX2 +XINV<6> q_int<6> qn_int<6> VDD VSS / RSC_IHPSG13_CINVX2 +XINV<5> q_int<5> qn_int<5> VDD VSS / RSC_IHPSG13_CINVX2 +XINV<4> q_int<4> qn_int<4> VDD VSS / RSC_IHPSG13_CINVX2 +XINV<3> q_int<3> qn_int<3> VDD VSS / RSC_IHPSG13_CINVX2 +XINV<2> q_int<2> qn_int<2> VDD VSS / RSC_IHPSG13_CINVX2 +XINV<1> q_int<1> qn_int<1> VDD VSS / RSC_IHPSG13_CINVX2 +XINV<0> q_int<0> qn_int<0> VDD VSS / RSC_IHPSG13_CINVX2 +XDRV<8> qn_int<8> ADDR_N_O<8> VDD VSS / RSC_IHPSG13_CINVX8 +XDRV<7> qn_int<7> ADDR_N_O<7> VDD VSS / RSC_IHPSG13_CINVX8 +XDRV<6> qn_int<6> ADDR_N_O<6> VDD VSS / RSC_IHPSG13_CINVX8 +XDRV<5> qn_int<5> ADDR_N_O<5> VDD VSS / RSC_IHPSG13_CINVX8 +XDRV<4> qn_int<4> ADDR_N_O<4> VDD VSS / RSC_IHPSG13_CINVX8 +XDRV<3> qn_int<3> ADDR_N_O<3> VDD VSS / RSC_IHPSG13_CINVX8 +XDRV<2> qn_int<2> ADDR_N_O<2> VDD VSS / RSC_IHPSG13_CINVX8 +XDRV<1> qn_int<1> ADDR_N_O<1> VDD VSS / RSC_IHPSG13_CINVX8 +XDRV<0> qn_int<0> ADDR_N_O<0> VDD VSS / RSC_IHPSG13_CINVX8 +XDFF<8> BIST_EN_I BIST_ADDR_I<8> ACLK_N_I ADDR_I<8> q_int<8> net04<0> VDD ++ VSS / RSC_IHPSG13_DFNQMX2IX1 +XDFF<7> BIST_EN_I BIST_ADDR_I<7> ACLK_N_I ADDR_I<7> q_int<7> net04<1> VDD ++ VSS / RSC_IHPSG13_DFNQMX2IX1 +XDFF<6> BIST_EN_I BIST_ADDR_I<6> ACLK_N_I ADDR_I<6> q_int<6> net04<2> VDD ++ VSS / RSC_IHPSG13_DFNQMX2IX1 +XDFF<5> BIST_EN_I BIST_ADDR_I<5> ACLK_N_I ADDR_I<5> q_int<5> net04<3> VDD ++ VSS / RSC_IHPSG13_DFNQMX2IX1 +XDFF<4> BIST_EN_I BIST_ADDR_I<4> ACLK_N_I ADDR_I<4> q_int<4> net04<4> VDD ++ VSS / RSC_IHPSG13_DFNQMX2IX1 +XDFF<3> BIST_EN_I BIST_ADDR_I<3> ACLK_N_I ADDR_I<3> q_int<3> net04<5> VDD ++ VSS / RSC_IHPSG13_DFNQMX2IX1 +XDFF<2> BIST_EN_I BIST_ADDR_I<2> ACLK_N_I ADDR_I<2> q_int<2> net04<6> VDD ++ VSS / RSC_IHPSG13_DFNQMX2IX1 +XDFF<1> BIST_EN_I BIST_ADDR_I<1> ACLK_N_I ADDR_I<1> q_int<1> net04<7> VDD ++ VSS / RSC_IHPSG13_DFNQMX2IX1 +XDFF<0> BIST_EN_I BIST_ADDR_I<0> ACLK_N_I ADDR_I<0> q_int<0> net04<8> VDD ++ VSS / RSC_IHPSG13_DFNQMX2IX1 +.ENDS + +.SUBCKT RM_IHPSG13_256x16_c2_1P_ROWDEC7 ADDR_N_I<6> ADDR_N_I<5> ADDR_N_I<4> ADDR_N_I<3> ++ ADDR_N_I<2> ADDR_N_I<1> ADDR_N_I<0> CS_I ECLK_I WL_O<127> WL_O<126> ++ WL_O<125> WL_O<124> WL_O<123> WL_O<122> WL_O<121> WL_O<120> WL_O<119> ++ WL_O<118> WL_O<117> WL_O<116> WL_O<115> WL_O<114> WL_O<113> WL_O<112> ++ WL_O<111> WL_O<110> WL_O<109> WL_O<108> WL_O<107> WL_O<106> WL_O<105> ++ WL_O<104> WL_O<103> WL_O<102> WL_O<101> WL_O<100> WL_O<99> WL_O<98> WL_O<97> ++ WL_O<96> WL_O<95> WL_O<94> WL_O<93> WL_O<92> WL_O<91> WL_O<90> WL_O<89> ++ WL_O<88> WL_O<87> WL_O<86> WL_O<85> WL_O<84> WL_O<83> WL_O<82> WL_O<81> ++ WL_O<80> WL_O<79> WL_O<78> WL_O<77> WL_O<76> WL_O<75> WL_O<74> WL_O<73> ++ WL_O<72> WL_O<71> WL_O<70> WL_O<69> WL_O<68> WL_O<67> WL_O<66> WL_O<65> ++ WL_O<64> WL_O<63> WL_O<62> WL_O<61> WL_O<60> WL_O<59> WL_O<58> WL_O<57> ++ WL_O<56> WL_O<55> WL_O<54> WL_O<53> WL_O<52> WL_O<51> WL_O<50> WL_O<49> ++ WL_O<48> WL_O<47> WL_O<46> WL_O<45> WL_O<44> WL_O<43> WL_O<42> WL_O<41> ++ WL_O<40> WL_O<39> WL_O<38> WL_O<37> WL_O<36> WL_O<35> WL_O<34> WL_O<33> ++ WL_O<32> WL_O<31> WL_O<30> WL_O<29> WL_O<28> WL_O<27> WL_O<26> WL_O<25> ++ WL_O<24> WL_O<23> WL_O<22> WL_O<21> WL_O<20> WL_O<19> WL_O<18> WL_O<17> ++ WL_O<16> WL_O<15> WL_O<14> WL_O<13> WL_O<12> WL_O<11> WL_O<10> WL_O<9> ++ WL_O<8> WL_O<7> WL_O<6> WL_O<5> WL_O<4> WL_O<3> WL_O<2> WL_O<1> WL_O<0> ++ VDD VSS +XDEC11<1> ADDR_N_I<5> ADDR_N_I<4> CS04<1> CS00<7> VDD VSS / ++ RM_IHPSG13_256x16_c2_1P_DEC03 +XDEC11<0> ADDR_N_I<5> ADDR_N_I<4> CS04<0> CS00<3> VDD VSS / ++ RM_IHPSG13_256x16_c2_1P_DEC03 +XDEC10<1> ADDR_N_I<5> ADDR_N_I<4> CS04<1> CS00<6> VDD VSS / ++ RM_IHPSG13_256x16_c2_1P_DEC02 +XDEC10<0> ADDR_N_I<5> ADDR_N_I<4> CS04<0> CS00<2> VDD VSS / ++ RM_IHPSG13_256x16_c2_1P_DEC02 +XSEL<7> ADDR_N_I<3> ADDR_N_I<2> ADDR_N_I<1> ADDR_N_I<0> CS00<7> ECLK_H<7> ++ ECLK_H<8> ECLK_B<7> ECLK_B<8> WL_O<127> WL_O<126> WL_O<125> WL_O<124> ++ WL_O<123> WL_O<122> WL_O<121> WL_O<120> WL_O<119> WL_O<118> WL_O<117> ++ WL_O<116> WL_O<115> WL_O<114> WL_O<113> WL_O<112> VDD VSS / ++ RM_IHPSG13_256x16_c2_1P_DEC04 +XSEL<6> ADDR_N_I<3> ADDR_N_I<2> ADDR_N_I<1> ADDR_N_I<0> CS00<6> ECLK_H<6> ++ ECLK_H<7> ECLK_B<6> ECLK_B<7> WL_O<111> WL_O<110> WL_O<109> WL_O<108> ++ WL_O<107> WL_O<106> WL_O<105> WL_O<104> WL_O<103> WL_O<102> WL_O<101> ++ WL_O<100> WL_O<99> WL_O<98> WL_O<97> WL_O<96> VDD VSS / ++ RM_IHPSG13_256x16_c2_1P_DEC04 +XSEL<5> ADDR_N_I<3> ADDR_N_I<2> ADDR_N_I<1> ADDR_N_I<0> CS00<5> ECLK_H<5> ++ ECLK_H<6> ECLK_B<5> ECLK_B<6> WL_O<95> WL_O<94> WL_O<93> WL_O<92> WL_O<91> ++ WL_O<90> WL_O<89> WL_O<88> WL_O<87> WL_O<86> WL_O<85> WL_O<84> WL_O<83> ++ WL_O<82> WL_O<81> WL_O<80> VDD VSS / RM_IHPSG13_256x16_c2_1P_DEC04 +XSEL<4> ADDR_N_I<3> ADDR_N_I<2> ADDR_N_I<1> ADDR_N_I<0> CS00<4> ECLK_H<4> ++ ECLK_H<5> ECLK_B<4> ECLK_B<5> WL_O<79> WL_O<78> WL_O<77> WL_O<76> WL_O<75> ++ WL_O<74> WL_O<73> WL_O<72> WL_O<71> WL_O<70> WL_O<69> WL_O<68> WL_O<67> ++ WL_O<66> WL_O<65> WL_O<64> VDD VSS / RM_IHPSG13_256x16_c2_1P_DEC04 +XSEL<3> ADDR_N_I<3> ADDR_N_I<2> ADDR_N_I<1> ADDR_N_I<0> CS00<3> ECLK_H<3> ++ ECLK_H<4> ECLK_B<3> ECLK_B<4> WL_O<63> WL_O<62> WL_O<61> WL_O<60> WL_O<59> ++ WL_O<58> WL_O<57> WL_O<56> WL_O<55> WL_O<54> WL_O<53> WL_O<52> WL_O<51> ++ WL_O<50> WL_O<49> WL_O<48> VDD VSS / RM_IHPSG13_256x16_c2_1P_DEC04 +XSEL<2> ADDR_N_I<3> ADDR_N_I<2> ADDR_N_I<1> ADDR_N_I<0> CS00<2> ECLK_H<2> ++ ECLK_H<3> ECLK_B<2> ECLK_B<3> WL_O<47> WL_O<46> WL_O<45> WL_O<44> WL_O<43> ++ WL_O<42> WL_O<41> WL_O<40> WL_O<39> WL_O<38> WL_O<37> WL_O<36> WL_O<35> ++ WL_O<34> WL_O<33> WL_O<32> VDD VSS / RM_IHPSG13_256x16_c2_1P_DEC04 +XSEL<1> ADDR_N_I<3> ADDR_N_I<2> ADDR_N_I<1> ADDR_N_I<0> CS00<1> ECLK_H<1> ++ ECLK_H<2> ECLK_B<1> ECLK_B<2> WL_O<31> WL_O<30> WL_O<29> WL_O<28> WL_O<27> ++ WL_O<26> WL_O<25> WL_O<24> WL_O<23> WL_O<22> WL_O<21> WL_O<20> WL_O<19> ++ WL_O<18> WL_O<17> WL_O<16> VDD VSS / RM_IHPSG13_256x16_c2_1P_DEC04 +XSEL<0> ADDR_N_I<3> ADDR_N_I<2> ADDR_N_I<1> ADDR_N_I<0> CS00<0> ECLK_I ++ ECLK_H<1> ECLK_B<0> ECLK_B<1> WL_O<15> WL_O<14> WL_O<13> WL_O<12> WL_O<11> ++ WL_O<10> WL_O<9> WL_O<8> WL_O<7> WL_O<6> WL_O<5> WL_O<4> WL_O<3> WL_O<2> ++ WL_O<1> WL_O<0> VDD VSS / RM_IHPSG13_256x16_c2_1P_DEC04 +XDEC00<2> ADDR_N_I<7> ADDR_N_I<6> CS_I CS04<0> VDD VSS / ++ RM_IHPSG13_256x16_c2_1P_DEC00 +XDEC00<1> ADDR_N_I<5> ADDR_N_I<4> CS04<1> CS00<4> VDD VSS / ++ RM_IHPSG13_256x16_c2_1P_DEC00 +XDEC00<0> ADDR_N_I<5> ADDR_N_I<4> CS04<0> CS00<0> VDD VSS / ++ RM_IHPSG13_256x16_c2_1P_DEC00 +XDEC01<2> ADDR_N_I<7> ADDR_N_I<6> CS_I CS04<1> VDD VSS / ++ RM_IHPSG13_256x16_c2_1P_DEC01 +XDEC01<1> ADDR_N_I<5> ADDR_N_I<4> CS04<1> CS00<5> VDD VSS / ++ RM_IHPSG13_256x16_c2_1P_DEC01 +XDEC01<0> ADDR_N_I<5> ADDR_N_I<4> CS04<0> CS00<1> VDD VSS / ++ RM_IHPSG13_256x16_c2_1P_DEC01 +XL2<44> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<43> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<42> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<41> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<40> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<39> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<38> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<37> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<36> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<35> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<34> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<33> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<32> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<31> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<30> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<29> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<28> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<27> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<26> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<25> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<24> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<23> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<22> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<21> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<20> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<19> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<18> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<17> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<16> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<15> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<14> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<13> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<12> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<11> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<10> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<9> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<8> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<7> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<6> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<5> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<4> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<3> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<2> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<1> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI0 ADDR_N_I<7> VDD VSS / RSC_IHPSG13_TIEL +.ENDS +.SUBCKT RM_IHPSG13_256x16_c2_1P_ROWREG7 ACLK_N_I ADDR_I<6> ADDR_I<5> ADDR_I<4> ADDR_I<3> ++ ADDR_I<2> ADDR_I<1> ADDR_I<0> ADDR_N_O<6> ADDR_N_O<5> ADDR_N_O<4> ++ ADDR_N_O<3> ADDR_N_O<2> ADDR_N_O<1> ADDR_N_O<0> BIST_ADDR_I<6> ++ BIST_ADDR_I<5> BIST_ADDR_I<4> BIST_ADDR_I<3> BIST_ADDR_I<2> BIST_ADDR_I<1> ++ BIST_ADDR_I<0> BIST_EN_I VDD VSS +XINV<6> q_int<6> qn_int<6> VDD VSS / RSC_IHPSG13_CINVX2 +XINV<5> q_int<5> qn_int<5> VDD VSS / RSC_IHPSG13_CINVX2 +XINV<4> q_int<4> qn_int<4> VDD VSS / RSC_IHPSG13_CINVX2 +XINV<3> q_int<3> qn_int<3> VDD VSS / RSC_IHPSG13_CINVX2 +XINV<2> q_int<2> qn_int<2> VDD VSS / RSC_IHPSG13_CINVX2 +XINV<1> q_int<1> qn_int<1> VDD VSS / RSC_IHPSG13_CINVX2 +XINV<0> q_int<0> qn_int<0> VDD VSS / RSC_IHPSG13_CINVX2 +XDRV<6> qn_int<6> ADDR_N_O<6> VDD VSS / RSC_IHPSG13_CINVX8 +XDRV<5> qn_int<5> ADDR_N_O<5> VDD VSS / RSC_IHPSG13_CINVX8 +XDRV<4> qn_int<4> ADDR_N_O<4> VDD VSS / RSC_IHPSG13_CINVX8 +XDRV<3> qn_int<3> ADDR_N_O<3> VDD VSS / RSC_IHPSG13_CINVX8 +XDRV<2> qn_int<2> ADDR_N_O<2> VDD VSS / RSC_IHPSG13_CINVX8 +XDRV<1> qn_int<1> ADDR_N_O<1> VDD VSS / RSC_IHPSG13_CINVX8 +XDRV<0> qn_int<0> ADDR_N_O<0> VDD VSS / RSC_IHPSG13_CINVX8 +XDFF<6> BIST_EN_I BIST_ADDR_I<6> ACLK_N_I ADDR_I<6> q_int<6> net2<0> VDD ++ VSS / RSC_IHPSG13_DFNQMX2IX1 +XDFF<5> BIST_EN_I BIST_ADDR_I<5> ACLK_N_I ADDR_I<5> q_int<5> net2<1> VDD ++ VSS / RSC_IHPSG13_DFNQMX2IX1 +XDFF<4> BIST_EN_I BIST_ADDR_I<4> ACLK_N_I ADDR_I<4> q_int<4> net2<2> VDD ++ VSS / RSC_IHPSG13_DFNQMX2IX1 +XDFF<3> BIST_EN_I BIST_ADDR_I<3> ACLK_N_I ADDR_I<3> q_int<3> net2<3> VDD ++ VSS / RSC_IHPSG13_DFNQMX2IX1 +XDFF<2> BIST_EN_I BIST_ADDR_I<2> ACLK_N_I ADDR_I<2> q_int<2> net2<4> VDD ++ VSS / RSC_IHPSG13_DFNQMX2IX1 +XDFF<1> BIST_EN_I BIST_ADDR_I<1> ACLK_N_I ADDR_I<1> q_int<1> net2<5> VDD ++ VSS / RSC_IHPSG13_DFNQMX2IX1 +XDFF<0> BIST_EN_I BIST_ADDR_I<0> ACLK_N_I ADDR_I<0> q_int<0> net2<6> VDD ++ VSS / RSC_IHPSG13_DFNQMX2IX1 +XI11<8> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI11<7> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI11<6> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI11<5> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI11<4> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI11<3> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI11<2> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI11<1> VDD VSS / RSC_IHPSG13_FILLCAP8 +.ENDS + +.SUBCKT RM_IHPSG13_256x16_c2_1P_COLDRV13X8 ADDR_COL_I<1> ADDR_COL_I<0> ADDR_COL_O<1> ++ ADDR_COL_O<0> ADDR_DEC_I<7> ADDR_DEC_I<6> ADDR_DEC_I<5> ADDR_DEC_I<4> ++ ADDR_DEC_I<3> ADDR_DEC_I<2> ADDR_DEC_I<1> ADDR_DEC_I<0> ADDR_DEC_O<7> ++ ADDR_DEC_O<6> ADDR_DEC_O<5> ADDR_DEC_O<4> ADDR_DEC_O<3> ADDR_DEC_O<2> ++ ADDR_DEC_O<1> ADDR_DEC_O<0> DCLK_I DCLK_O RCLK_I RCLK_O WCLK_I WCLK_O ++ VDD VSS +XI0<1> VDD VSS / RSC_IHPSG13_FILLCAP4 +XI0<0> VDD VSS / RSC_IHPSG13_FILLCAP4 +XADDR_COL_DRV<1> ADDR_COL_I<1> ADDR_COL_O<1> VDD VSS / ++ RSC_IHPSG13_CBUFX8 +XADDR_COL_DRV<0> ADDR_COL_I<0> ADDR_COL_O<0> VDD VSS / ++ RSC_IHPSG13_CBUFX8 +XADDR_DEC_DRV<7> ADDR_DEC_I<7> ADDR_DEC_O<7> VDD VSS / ++ RSC_IHPSG13_CBUFX8 +XADDR_DEC_DRV<6> ADDR_DEC_I<6> ADDR_DEC_O<6> VDD VSS / ++ RSC_IHPSG13_CBUFX8 +XADDR_DEC_DRV<5> ADDR_DEC_I<5> ADDR_DEC_O<5> VDD VSS / ++ RSC_IHPSG13_CBUFX8 +XADDR_DEC_DRV<4> ADDR_DEC_I<4> ADDR_DEC_O<4> VDD VSS / ++ RSC_IHPSG13_CBUFX8 +XADDR_DEC_DRV<3> ADDR_DEC_I<3> ADDR_DEC_O<3> VDD VSS / ++ RSC_IHPSG13_CBUFX8 +XADDR_DEC_DRV<2> ADDR_DEC_I<2> ADDR_DEC_O<2> VDD VSS / ++ RSC_IHPSG13_CBUFX8 +XADDR_DEC_DRV<1> ADDR_DEC_I<1> ADDR_DEC_O<1> VDD VSS / ++ RSC_IHPSG13_CBUFX8 +XADDR_DEC_DRV<0> ADDR_DEC_I<0> ADDR_DEC_O<0> VDD VSS / ++ RSC_IHPSG13_CBUFX8 +XDCLK_DRV DCLK_I DCLK_O VDD VSS / RSC_IHPSG13_CBUFX8 +XRCLK_DRV RCLK_I RCLK_O VDD VSS / RSC_IHPSG13_CBUFX8 +XWCLK_DRV WCLK_I WCLK_O VDD VSS / RSC_IHPSG13_CBUFX8 +.ENDS +.SUBCKT RM_IHPSG13_256x16_c2_1P_WLDRV16X8 A<15> A<14> A<13> A<12> A<11> A<10> A<9> A<8> ++ A<7> A<6> A<5> A<4> A<3> A<2> A<1> A<0> Z<15> Z<14> Z<13> Z<12> Z<11> Z<10> ++ Z<9> Z<8> Z<7> Z<6> Z<5> Z<4> Z<3> Z<2> Z<1> Z<0> VDD VSS +XBUF<15> A<15> Z<15> VDD VSS / RSC_IHPSG13_WLDRVX8 +XBUF<14> A<14> Z<14> VDD VSS / RSC_IHPSG13_WLDRVX8 +XBUF<13> A<13> Z<13> VDD VSS / RSC_IHPSG13_WLDRVX8 +XBUF<12> A<12> Z<12> VDD VSS / RSC_IHPSG13_WLDRVX8 +XBUF<11> A<11> Z<11> VDD VSS / RSC_IHPSG13_WLDRVX8 +XBUF<10> A<10> Z<10> VDD VSS / RSC_IHPSG13_WLDRVX8 +XBUF<9> A<9> Z<9> VDD VSS / RSC_IHPSG13_WLDRVX8 +XBUF<8> A<8> Z<8> VDD VSS / RSC_IHPSG13_WLDRVX8 +XBUF<7> A<7> Z<7> VDD VSS / RSC_IHPSG13_WLDRVX8 +XBUF<6> A<6> Z<6> VDD VSS / RSC_IHPSG13_WLDRVX8 +XBUF<5> A<5> Z<5> VDD VSS / RSC_IHPSG13_WLDRVX8 +XBUF<4> A<4> Z<4> VDD VSS / RSC_IHPSG13_WLDRVX8 +XBUF<3> A<3> Z<3> VDD VSS / RSC_IHPSG13_WLDRVX8 +XBUF<2> A<2> Z<2> VDD VSS / RSC_IHPSG13_WLDRVX8 +XBUF<1> A<1> Z<1> VDD VSS / RSC_IHPSG13_WLDRVX8 +XBUF<0> A<0> Z<0> VDD VSS / RSC_IHPSG13_WLDRVX8 +.ENDS + + + +.SUBCKT RM_IHPSG13_256x16_c2_1P_ROWDEC6 ADDR_N_I<5> ADDR_N_I<4> ADDR_N_I<3> ADDR_N_I<2> ++ ADDR_N_I<1> ADDR_N_I<0> CS_I ECLK_I WL_O<63> WL_O<62> WL_O<61> WL_O<60> ++ WL_O<59> WL_O<58> WL_O<57> WL_O<56> WL_O<55> WL_O<54> WL_O<53> WL_O<52> ++ WL_O<51> WL_O<50> WL_O<49> WL_O<48> WL_O<47> WL_O<46> WL_O<45> WL_O<44> ++ WL_O<43> WL_O<42> WL_O<41> WL_O<40> WL_O<39> WL_O<38> WL_O<37> WL_O<36> ++ WL_O<35> WL_O<34> WL_O<33> WL_O<32> WL_O<31> WL_O<30> WL_O<29> WL_O<28> ++ WL_O<27> WL_O<26> WL_O<25> WL_O<24> WL_O<23> WL_O<22> WL_O<21> WL_O<20> ++ WL_O<19> WL_O<18> WL_O<17> WL_O<16> WL_O<15> WL_O<14> WL_O<13> WL_O<12> ++ WL_O<11> WL_O<10> WL_O<9> WL_O<8> WL_O<7> WL_O<6> WL_O<5> WL_O<4> WL_O<3> ++ WL_O<2> WL_O<1> WL_O<0> VDD VSS +XDEC11 ADDR_N_I<5> ADDR_N_I<4> CS_I CS00<3> VDD VSS / ++ RM_IHPSG13_256x16_c2_1P_DEC03 +XDEC00 ADDR_N_I<5> ADDR_N_I<4> CS_I CS00<0> VDD VSS / ++ RM_IHPSG13_256x16_c2_1P_DEC00 +XDEC01 ADDR_N_I<5> ADDR_N_I<4> CS_I CS00<1> VDD VSS / ++ RM_IHPSG13_256x16_c2_1P_DEC01 +XDEC10 ADDR_N_I<5> ADDR_N_I<4> CS_I CS00<2> VDD VSS / ++ RM_IHPSG13_256x16_c2_1P_DEC02 +XSEL<3> ADDR_N_I<3> ADDR_N_I<2> ADDR_N_I<1> ADDR_N_I<0> CS00<3> ECLK_H<3> ++ ECLK_H<4> ECLK_B<3> ECLK_B<4> WL_O<63> WL_O<62> WL_O<61> WL_O<60> WL_O<59> ++ WL_O<58> WL_O<57> WL_O<56> WL_O<55> WL_O<54> WL_O<53> WL_O<52> WL_O<51> ++ WL_O<50> WL_O<49> WL_O<48> VDD VSS / RM_IHPSG13_256x16_c2_1P_DEC04 +XSEL<2> ADDR_N_I<3> ADDR_N_I<2> ADDR_N_I<1> ADDR_N_I<0> CS00<2> ECLK_H<2> ++ ECLK_H<3> ECLK_B<2> ECLK_B<3> WL_O<47> WL_O<46> WL_O<45> WL_O<44> WL_O<43> ++ WL_O<42> WL_O<41> WL_O<40> WL_O<39> WL_O<38> WL_O<37> WL_O<36> WL_O<35> ++ WL_O<34> WL_O<33> WL_O<32> VDD VSS / RM_IHPSG13_256x16_c2_1P_DEC04 +XSEL<1> ADDR_N_I<3> ADDR_N_I<2> ADDR_N_I<1> ADDR_N_I<0> CS00<1> ECLK_H<1> ++ ECLK_H<2> ECLK_B<1> ECLK_B<2> WL_O<31> WL_O<30> WL_O<29> WL_O<28> WL_O<27> ++ WL_O<26> WL_O<25> WL_O<24> WL_O<23> WL_O<22> WL_O<21> WL_O<20> WL_O<19> ++ WL_O<18> WL_O<17> WL_O<16> VDD VSS / RM_IHPSG13_256x16_c2_1P_DEC04 +XSEL<0> ADDR_N_I<3> ADDR_N_I<2> ADDR_N_I<1> ADDR_N_I<0> CS00<0> ECLK_I ++ ECLK_H<1> ECLK_B<0> ECLK_B<1> WL_O<15> WL_O<14> WL_O<13> WL_O<12> WL_O<11> ++ WL_O<10> WL_O<9> WL_O<8> WL_O<7> WL_O<6> WL_O<5> WL_O<4> WL_O<3> WL_O<2> ++ WL_O<1> WL_O<0> VDD VSS / RM_IHPSG13_256x16_c2_1P_DEC04 +XL2<24> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<23> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<22> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<21> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<20> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<19> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<18> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<17> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<16> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<15> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<14> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<13> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<12> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<11> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<10> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<9> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<8> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<7> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<6> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<5> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<4> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<3> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<2> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<1> VDD VSS / RSC_IHPSG13_FILLCAP8 +.ENDS +.SUBCKT RM_IHPSG13_256x16_c2_1P_ROWREG6 ACLK_N_I ADDR_I<5> ADDR_I<4> ADDR_I<3> ADDR_I<2> ++ ADDR_I<1> ADDR_I<0> ADDR_N_O<5> ADDR_N_O<4> ADDR_N_O<3> ADDR_N_O<2> ++ ADDR_N_O<1> ADDR_N_O<0> BIST_ADDR_I<5> BIST_ADDR_I<4> BIST_ADDR_I<3> ++ BIST_ADDR_I<2> BIST_ADDR_I<1> BIST_ADDR_I<0> BIST_EN_I VDD VSS +XINV<5> q_int<5> qn_int<5> VDD VSS / RSC_IHPSG13_CINVX2 +XINV<4> q_int<4> qn_int<4> VDD VSS / RSC_IHPSG13_CINVX2 +XINV<3> q_int<3> qn_int<3> VDD VSS / RSC_IHPSG13_CINVX2 +XINV<2> q_int<2> qn_int<2> VDD VSS / RSC_IHPSG13_CINVX2 +XINV<1> q_int<1> qn_int<1> VDD VSS / RSC_IHPSG13_CINVX2 +XINV<0> q_int<0> qn_int<0> VDD VSS / RSC_IHPSG13_CINVX2 +XDRV<5> qn_int<5> ADDR_N_O<5> VDD VSS / RSC_IHPSG13_CINVX8 +XDRV<4> qn_int<4> ADDR_N_O<4> VDD VSS / RSC_IHPSG13_CINVX8 +XDRV<3> qn_int<3> ADDR_N_O<3> VDD VSS / RSC_IHPSG13_CINVX8 +XDRV<2> qn_int<2> ADDR_N_O<2> VDD VSS / RSC_IHPSG13_CINVX8 +XDRV<1> qn_int<1> ADDR_N_O<1> VDD VSS / RSC_IHPSG13_CINVX8 +XDRV<0> qn_int<0> ADDR_N_O<0> VDD VSS / RSC_IHPSG13_CINVX8 +XDFF<5> BIST_EN_I BIST_ADDR_I<5> ACLK_N_I ADDR_I<5> q_int<5> net2<0> VDD ++ VSS / RSC_IHPSG13_DFNQMX2IX1 +XDFF<4> BIST_EN_I BIST_ADDR_I<4> ACLK_N_I ADDR_I<4> q_int<4> net2<1> VDD ++ VSS / RSC_IHPSG13_DFNQMX2IX1 +XDFF<3> BIST_EN_I BIST_ADDR_I<3> ACLK_N_I ADDR_I<3> q_int<3> net2<2> VDD ++ VSS / RSC_IHPSG13_DFNQMX2IX1 +XDFF<2> BIST_EN_I BIST_ADDR_I<2> ACLK_N_I ADDR_I<2> q_int<2> net2<3> VDD ++ VSS / RSC_IHPSG13_DFNQMX2IX1 +XDFF<1> BIST_EN_I BIST_ADDR_I<1> ACLK_N_I ADDR_I<1> q_int<1> net2<4> VDD ++ VSS / RSC_IHPSG13_DFNQMX2IX1 +XDFF<0> BIST_EN_I BIST_ADDR_I<0> ACLK_N_I ADDR_I<0> q_int<0> net2<5> VDD ++ VSS / RSC_IHPSG13_DFNQMX2IX1 +XI11<12> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI11<11> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI11<10> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI11<9> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI11<8> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI11<7> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI11<6> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI11<5> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI11<4> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI11<3> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI11<2> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI11<1> VDD VSS / RSC_IHPSG13_FILLCAP8 +.ENDS + + +.SUBCKT RM_IHPSG13_256x16_c2_1P_COLUMN_pcell_0 A_BLC_BOT<1> A_BLC_BOT<0> A_BLC_TOP<1> A_BLC_TOP<0> A_BLT_BOT<1> A_BLT_BOT<0> A_BLT_TOP<1> A_BLT_TOP<0> A_LWL<63> A_LWL<62> A_LWL<61> A_LWL<60> A_LWL<59> A_LWL<58> A_LWL<57> A_LWL<56> A_LWL<55> A_LWL<54> A_LWL<53> A_LWL<52> A_LWL<51> A_LWL<50> A_LWL<49> A_LWL<48> A_LWL<47> A_LWL<46> A_LWL<45> A_LWL<44> A_LWL<43> A_LWL<42> A_LWL<41> A_LWL<40> A_LWL<39> A_LWL<38> A_LWL<37> A_LWL<36> A_LWL<35> A_LWL<34> A_LWL<33> A_LWL<32> A_LWL<31> A_LWL<30> A_LWL<29> A_LWL<28> A_LWL<27> A_LWL<26> A_LWL<25> A_LWL<24> A_LWL<23> A_LWL<22> A_LWL<21> A_LWL<20> A_LWL<19> A_LWL<18> A_LWL<17> A_LWL<16> A_LWL<15> A_LWL<14> A_LWL<13> A_LWL<12> A_LWL<11> A_LWL<10> A_LWL<9> A_LWL<8> A_LWL<7> A_LWL<6> A_LWL<5> A_LWL<4> A_LWL<3> A_LWL<2> A_LWL<1> A_LWL<0> A_RWL<63> A_RWL<62> A_RWL<61> A_RWL<60> A_RWL<59> A_RWL<58> A_RWL<57> A_RWL<56> A_RWL<55> A_RWL<54> A_RWL<53> A_RWL<52> A_RWL<51> A_RWL<50> A_RWL<49> A_RWL<48> A_RWL<47> A_RWL<46> A_RWL<45> A_RWL<44> A_RWL<43> A_RWL<42> A_RWL<41> A_RWL<40> A_RWL<39> A_RWL<38> A_RWL<37> A_RWL<36> A_RWL<35> A_RWL<34> A_RWL<33> A_RWL<32> A_RWL<31> A_RWL<30> A_RWL<29> A_RWL<28> A_RWL<27> A_RWL<26> A_RWL<25> A_RWL<24> A_RWL<23> A_RWL<22> A_RWL<21> A_RWL<20> A_RWL<19> A_RWL<18> A_RWL<17> A_RWL<16> A_RWL<15> A_RWL<14> A_RWL<13> A_RWL<12> A_RWL<11> A_RWL<10> A_RWL<9> A_RWL<8> A_RWL<7> A_RWL<6> A_RWL<5> A_RWL<4> A_RWL<3> A_RWL<2> A_RWL<1> A_RWL<0> VDD_CORE VSS +XRAM<4> A_BLC<5> A_BLC<4> A_BLC_TOP<1> A_BLC_TOP<0> A_BLT<5> A_BLT<4> A_BLT_TOP<1> A_BLT_TOP<0> A_LWL<63> A_LWL<62> A_LWL<61> A_LWL<60> A_LWL<59> A_LWL<58> A_LWL<57> A_LWL<56> A_LWL<55> A_LWL<54> A_LWL<53> A_LWL<52> A_LWL<51> A_LWL<50> A_LWL<49> A_LWL<48> A_RWL<63> A_RWL<62> A_RWL<61> A_RWL<60> A_RWL<59> A_RWL<58> A_RWL<57> A_RWL<56> A_RWL<55> A_RWL<54> A_RWL<53> A_RWL<52> A_RWL<51> A_RWL<50> A_RWL<49> A_RWL<48> VDD_CORE VSS / RM_IHPSG13_256x16_c2_1P_BITKIT_16x2_SRAM +XRAM<3> A_BLC<3> A_BLC<2> A_BLC<5> A_BLC<4> A_BLT<3> A_BLT<2> A_BLT<5> A_BLT<4> A_LWL<47> A_LWL<46> A_LWL<45> A_LWL<44> A_LWL<43> A_LWL<42> A_LWL<41> A_LWL<40> A_LWL<39> A_LWL<38> A_LWL<37> A_LWL<36> A_LWL<35> A_LWL<34> A_LWL<33> A_LWL<32> A_RWL<47> A_RWL<46> A_RWL<45> A_RWL<44> A_RWL<43> A_RWL<42> A_RWL<41> A_RWL<40> A_RWL<39> A_RWL<38> A_RWL<37> A_RWL<36> A_RWL<35> A_RWL<34> A_RWL<33> A_RWL<32> VDD_CORE VSS / RM_IHPSG13_256x16_c2_1P_BITKIT_16x2_SRAM +XRAM<2> A_BLC<1> A_BLC<0> A_BLC<3> A_BLC<2> A_BLT<1> A_BLT<0> A_BLT<3> A_BLT<2> A_LWL<31> A_LWL<30> A_LWL<29> A_LWL<28> A_LWL<27> A_LWL<26> A_LWL<25> A_LWL<24> A_LWL<23> A_LWL<22> A_LWL<21> A_LWL<20> A_LWL<19> A_LWL<18> A_LWL<17> A_LWL<16> A_RWL<31> A_RWL<30> A_RWL<29> A_RWL<28> A_RWL<27> A_RWL<26> A_RWL<25> A_RWL<24> A_RWL<23> A_RWL<22> A_RWL<21> A_RWL<20> A_RWL<19> A_RWL<18> A_RWL<17> A_RWL<16> VDD_CORE VSS / RM_IHPSG13_256x16_c2_1P_BITKIT_16x2_SRAM +XRAM<1> A_BLC_BOT<1> A_BLC_BOT<0> A_BLC<1> A_BLC<0> A_BLT_BOT<1> A_BLT_BOT<0> A_BLT<1> A_BLT<0> A_LWL<15> A_LWL<14> A_LWL<13> A_LWL<12> A_LWL<11> A_LWL<10> A_LWL<9> A_LWL<8> A_LWL<7> A_LWL<6> A_LWL<5> A_LWL<4> A_LWL<3> A_LWL<2> A_LWL<1> A_LWL<0> A_RWL<15> A_RWL<14> A_RWL<13> A_RWL<12> A_RWL<11> A_RWL<10> A_RWL<9> A_RWL<8> A_RWL<7> A_RWL<6> A_RWL<5> A_RWL<4> A_RWL<3> A_RWL<2> A_RWL<1> A_RWL<0> VDD_CORE VSS / RM_IHPSG13_256x16_c2_1P_BITKIT_16x2_SRAM +XEDGE<1> A_BLC_TOP<1> A_BLC_TOP<0> A_BLT_TOP<1> A_BLT_TOP<0> VDD_CORE VSS / RM_IHPSG13_256x16_c2_1P_BITKIT_16x2_EDGE_TB +XEDGE<0> A_BLC_BOT<1> A_BLC_BOT<0> A_BLT_BOT<1> A_BLT_BOT<0> VDD_CORE VSS / RM_IHPSG13_256x16_c2_1P_BITKIT_16x2_EDGE_TB +.ENDS + + + + +.SUBCKT RM_IHPSG13_256x16_c2_1P_MATRIX_pcell_1 A_BLC<31> A_BLC<30> A_BLC<29> A_BLC<28> A_BLC<27> A_BLC<26> A_BLC<25> A_BLC<24> A_BLC<23> A_BLC<22> A_BLC<21> A_BLC<20> A_BLC<19> A_BLC<18> A_BLC<17> A_BLC<16> A_BLC<15> A_BLC<14> A_BLC<13> A_BLC<12> A_BLC<11> A_BLC<10> A_BLC<9> A_BLC<8> A_BLC<7> A_BLC<6> A_BLC<5> A_BLC<4> A_BLC<3> A_BLC<2> A_BLC<1> A_BLC<0> A_BLT<31> A_BLT<30> A_BLT<29> A_BLT<28> A_BLT<27> A_BLT<26> A_BLT<25> A_BLT<24> A_BLT<23> A_BLT<22> A_BLT<21> A_BLT<20> A_BLT<19> A_BLT<18> A_BLT<17> A_BLT<16> A_BLT<15> A_BLT<14> A_BLT<13> A_BLT<12> A_BLT<11> A_BLT<10> A_BLT<9> A_BLT<8> A_BLT<7> A_BLT<6> A_BLT<5> A_BLT<4> A_BLT<3> A_BLT<2> A_BLT<1> A_BLT<0> A_WL<63> A_WL<62> A_WL<61> A_WL<60> A_WL<59> A_WL<58> A_WL<57> A_WL<56> A_WL<55> A_WL<54> A_WL<53> A_WL<52> A_WL<51> A_WL<50> A_WL<49> A_WL<48> A_WL<47> A_WL<46> A_WL<45> A_WL<44> A_WL<43> A_WL<42> A_WL<41> A_WL<40> A_WL<39> A_WL<38> A_WL<37> A_WL<36> A_WL<35> A_WL<34> A_WL<33> A_WL<32> A_WL<31> A_WL<30> A_WL<29> A_WL<28> A_WL<27> A_WL<26> A_WL<25> A_WL<24> A_WL<23> A_WL<22> A_WL<21> A_WL<20> A_WL<19> A_WL<18> A_WL<17> A_WL<16> A_WL<15> A_WL<14> A_WL<13> A_WL<12> A_WL<11> A_WL<10> A_WL<9> A_WL<8> A_WL<7> A_WL<6> A_WL<5> A_WL<4> A_WL<3> A_WL<2> A_WL<1> A_WL<0> VDD_CORE VSS +XCORNER<3> VDD_CORE VSS / RM_IHPSG13_256x16_c2_1P_BITKIT_16x2_CORNER +XCORNER<2> VDD_CORE VSS / RM_IHPSG13_256x16_c2_1P_BITKIT_16x2_CORNER +XCORNER<1> VDD_CORE VSS / RM_IHPSG13_256x16_c2_1P_BITKIT_16x2_CORNER +XCORNER<0> VDD_CORE VSS / RM_IHPSG13_256x16_c2_1P_BITKIT_16x2_CORNER +XRAMEDGE_L<3> A_WL<63> A_WL<62> A_WL<61> A_WL<60> A_WL<59> A_WL<58> A_WL<57> A_WL<56> A_WL<55> A_WL<54> A_WL<53> A_WL<52> A_WL<51> A_WL<50> A_WL<49> A_WL<48> VDD_CORE VSS / RM_IHPSG13_256x16_c2_1P_BITKIT_16x2_EDGE_LR +XRAMEDGE_L<2> A_WL<47> A_WL<46> A_WL<45> A_WL<44> A_WL<43> A_WL<42> A_WL<41> A_WL<40> A_WL<39> A_WL<38> A_WL<37> A_WL<36> A_WL<35> A_WL<34> A_WL<33> A_WL<32> VDD_CORE VSS / RM_IHPSG13_256x16_c2_1P_BITKIT_16x2_EDGE_LR +XRAMEDGE_L<1> A_WL<31> A_WL<30> A_WL<29> A_WL<28> A_WL<27> A_WL<26> A_WL<25> A_WL<24> A_WL<23> A_WL<22> A_WL<21> A_WL<20> A_WL<19> A_WL<18> A_WL<17> A_WL<16> VDD_CORE VSS / RM_IHPSG13_256x16_c2_1P_BITKIT_16x2_EDGE_LR +XRAMEDGE_L<0> A_WL<15> A_WL<14> A_WL<13> A_WL<12> A_WL<11> A_WL<10> A_WL<9> A_WL<8> A_WL<7> A_WL<6> A_WL<5> A_WL<4> A_WL<3> A_WL<2> A_WL<1> A_WL<0> VDD_CORE VSS / RM_IHPSG13_256x16_c2_1P_BITKIT_16x2_EDGE_LR +XRAMEDGE_R<3> A_IWL<1023> A_IWL<1022> A_IWL<1021> A_IWL<1020> A_IWL<1019> A_IWL<1018> A_IWL<1017> A_IWL<1016> A_IWL<1015> A_IWL<1014> A_IWL<1013> A_IWL<1012> A_IWL<1011> A_IWL<1010> A_IWL<1009> A_IWL<1008> VDD_CORE VSS / RM_IHPSG13_256x16_c2_1P_BITKIT_16x2_EDGE_LR +XRAMEDGE_R<2> A_IWL<1007> A_IWL<1006> A_IWL<1005> A_IWL<1004> A_IWL<1003> A_IWL<1002> A_IWL<1001> A_IWL<1000> A_IWL<999> A_IWL<998> A_IWL<997> A_IWL<996> A_IWL<995> A_IWL<994> A_IWL<993> A_IWL<992> VDD_CORE VSS / RM_IHPSG13_256x16_c2_1P_BITKIT_16x2_EDGE_LR +XRAMEDGE_R<1> A_IWL<991> A_IWL<990> A_IWL<989> A_IWL<988> A_IWL<987> A_IWL<986> A_IWL<985> A_IWL<984> A_IWL<983> A_IWL<982> A_IWL<981> A_IWL<980> A_IWL<979> A_IWL<978> A_IWL<977> A_IWL<976> VDD_CORE VSS / RM_IHPSG13_256x16_c2_1P_BITKIT_16x2_EDGE_LR +XRAMEDGE_R<0> A_IWL<975> A_IWL<974> A_IWL<973> A_IWL<972> A_IWL<971> A_IWL<970> A_IWL<969> A_IWL<968> A_IWL<967> A_IWL<966> A_IWL<965> A_IWL<964> A_IWL<963> A_IWL<962> A_IWL<961> A_IWL<960> VDD_CORE VSS / RM_IHPSG13_256x16_c2_1P_BITKIT_16x2_EDGE_LR +XCOL<15> A_BLC<31> A_BLC<30> A_BLC_TOP<31> A_BLC_TOP<30> A_BLT<31> A_BLT<30> A_BLT_TOP<31> A_BLT_TOP<30> A_IWL<959> A_IWL<958> A_IWL<957> A_IWL<956> A_IWL<955> A_IWL<954> A_IWL<953> A_IWL<952> A_IWL<951> A_IWL<950> A_IWL<949> A_IWL<948> A_IWL<947> A_IWL<946> A_IWL<945> A_IWL<944> A_IWL<943> A_IWL<942> A_IWL<941> A_IWL<940> A_IWL<939> A_IWL<938> A_IWL<937> A_IWL<936> A_IWL<935> A_IWL<934> A_IWL<933> A_IWL<932> A_IWL<931> A_IWL<930> A_IWL<929> A_IWL<928> A_IWL<927> A_IWL<926> A_IWL<925> A_IWL<924> A_IWL<923> A_IWL<922> A_IWL<921> A_IWL<920> A_IWL<919> A_IWL<918> A_IWL<917> A_IWL<916> A_IWL<915> A_IWL<914> A_IWL<913> A_IWL<912> A_IWL<911> A_IWL<910> A_IWL<909> A_IWL<908> A_IWL<907> A_IWL<906> A_IWL<905> A_IWL<904> A_IWL<903> A_IWL<902> A_IWL<901> A_IWL<900> A_IWL<899> A_IWL<898> A_IWL<897> A_IWL<896> A_IWL<1023> A_IWL<1022> A_IWL<1021> A_IWL<1020> A_IWL<1019> A_IWL<1018> A_IWL<1017> A_IWL<1016> A_IWL<1015> A_IWL<1014> A_IWL<1013> A_IWL<1012> A_IWL<1011> A_IWL<1010> A_IWL<1009> A_IWL<1008> A_IWL<1007> A_IWL<1006> A_IWL<1005> A_IWL<1004> A_IWL<1003> A_IWL<1002> A_IWL<1001> A_IWL<1000> A_IWL<999> A_IWL<998> A_IWL<997> A_IWL<996> A_IWL<995> A_IWL<994> A_IWL<993> A_IWL<992> A_IWL<991> A_IWL<990> A_IWL<989> A_IWL<988> A_IWL<987> A_IWL<986> A_IWL<985> A_IWL<984> A_IWL<983> A_IWL<982> A_IWL<981> A_IWL<980> A_IWL<979> A_IWL<978> A_IWL<977> A_IWL<976> A_IWL<975> A_IWL<974> A_IWL<973> A_IWL<972> A_IWL<971> A_IWL<970> A_IWL<969> A_IWL<968> A_IWL<967> A_IWL<966> A_IWL<965> A_IWL<964> A_IWL<963> A_IWL<962> A_IWL<961> A_IWL<960> VDD_CORE VSS / RM_IHPSG13_256x16_c2_1P_COLUMN_pcell_0 +XCOL<14> A_BLC<29> A_BLC<28> A_BLC_TOP<29> A_BLC_TOP<28> A_BLT<29> A_BLT<28> A_BLT_TOP<29> A_BLT_TOP<28> A_IWL<895> A_IWL<894> A_IWL<893> A_IWL<892> A_IWL<891> A_IWL<890> A_IWL<889> A_IWL<888> A_IWL<887> A_IWL<886> A_IWL<885> A_IWL<884> A_IWL<883> A_IWL<882> A_IWL<881> A_IWL<880> A_IWL<879> A_IWL<878> A_IWL<877> A_IWL<876> A_IWL<875> A_IWL<874> A_IWL<873> A_IWL<872> A_IWL<871> A_IWL<870> A_IWL<869> A_IWL<868> A_IWL<867> A_IWL<866> A_IWL<865> A_IWL<864> A_IWL<863> A_IWL<862> A_IWL<861> A_IWL<860> A_IWL<859> A_IWL<858> A_IWL<857> A_IWL<856> A_IWL<855> A_IWL<854> A_IWL<853> A_IWL<852> A_IWL<851> A_IWL<850> A_IWL<849> A_IWL<848> A_IWL<847> A_IWL<846> A_IWL<845> A_IWL<844> A_IWL<843> A_IWL<842> A_IWL<841> A_IWL<840> A_IWL<839> A_IWL<838> A_IWL<837> A_IWL<836> A_IWL<835> A_IWL<834> A_IWL<833> A_IWL<832> A_IWL<959> A_IWL<958> A_IWL<957> A_IWL<956> A_IWL<955> A_IWL<954> A_IWL<953> A_IWL<952> A_IWL<951> A_IWL<950> A_IWL<949> A_IWL<948> A_IWL<947> A_IWL<946> A_IWL<945> A_IWL<944> A_IWL<943> A_IWL<942> A_IWL<941> A_IWL<940> A_IWL<939> A_IWL<938> A_IWL<937> A_IWL<936> A_IWL<935> A_IWL<934> A_IWL<933> A_IWL<932> A_IWL<931> A_IWL<930> A_IWL<929> A_IWL<928> A_IWL<927> A_IWL<926> A_IWL<925> A_IWL<924> A_IWL<923> A_IWL<922> A_IWL<921> A_IWL<920> A_IWL<919> A_IWL<918> A_IWL<917> A_IWL<916> A_IWL<915> A_IWL<914> A_IWL<913> A_IWL<912> A_IWL<911> A_IWL<910> A_IWL<909> A_IWL<908> A_IWL<907> A_IWL<906> A_IWL<905> A_IWL<904> A_IWL<903> A_IWL<902> A_IWL<901> A_IWL<900> A_IWL<899> A_IWL<898> A_IWL<897> A_IWL<896> VDD_CORE VSS / RM_IHPSG13_256x16_c2_1P_COLUMN_pcell_0 +XCOL<13> A_BLC<27> A_BLC<26> A_BLC_TOP<27> A_BLC_TOP<26> A_BLT<27> A_BLT<26> A_BLT_TOP<27> A_BLT_TOP<26> A_IWL<831> A_IWL<830> A_IWL<829> A_IWL<828> A_IWL<827> A_IWL<826> A_IWL<825> A_IWL<824> A_IWL<823> A_IWL<822> A_IWL<821> A_IWL<820> A_IWL<819> A_IWL<818> A_IWL<817> A_IWL<816> A_IWL<815> A_IWL<814> A_IWL<813> A_IWL<812> A_IWL<811> A_IWL<810> A_IWL<809> A_IWL<808> A_IWL<807> A_IWL<806> A_IWL<805> A_IWL<804> A_IWL<803> A_IWL<802> A_IWL<801> A_IWL<800> A_IWL<799> A_IWL<798> A_IWL<797> A_IWL<796> A_IWL<795> A_IWL<794> A_IWL<793> A_IWL<792> A_IWL<791> A_IWL<790> A_IWL<789> A_IWL<788> A_IWL<787> A_IWL<786> A_IWL<785> A_IWL<784> A_IWL<783> A_IWL<782> A_IWL<781> A_IWL<780> A_IWL<779> A_IWL<778> A_IWL<777> A_IWL<776> A_IWL<775> A_IWL<774> A_IWL<773> A_IWL<772> A_IWL<771> A_IWL<770> A_IWL<769> A_IWL<768> A_IWL<895> A_IWL<894> A_IWL<893> A_IWL<892> A_IWL<891> A_IWL<890> A_IWL<889> A_IWL<888> A_IWL<887> A_IWL<886> A_IWL<885> A_IWL<884> A_IWL<883> A_IWL<882> A_IWL<881> A_IWL<880> A_IWL<879> A_IWL<878> A_IWL<877> A_IWL<876> A_IWL<875> A_IWL<874> A_IWL<873> A_IWL<872> A_IWL<871> A_IWL<870> A_IWL<869> A_IWL<868> A_IWL<867> A_IWL<866> A_IWL<865> A_IWL<864> A_IWL<863> A_IWL<862> A_IWL<861> A_IWL<860> A_IWL<859> A_IWL<858> A_IWL<857> A_IWL<856> A_IWL<855> A_IWL<854> A_IWL<853> A_IWL<852> A_IWL<851> A_IWL<850> A_IWL<849> A_IWL<848> A_IWL<847> A_IWL<846> A_IWL<845> A_IWL<844> A_IWL<843> A_IWL<842> A_IWL<841> A_IWL<840> A_IWL<839> A_IWL<838> A_IWL<837> A_IWL<836> A_IWL<835> A_IWL<834> A_IWL<833> A_IWL<832> VDD_CORE VSS / RM_IHPSG13_256x16_c2_1P_COLUMN_pcell_0 +XCOL<12> A_BLC<25> A_BLC<24> A_BLC_TOP<25> A_BLC_TOP<24> A_BLT<25> A_BLT<24> A_BLT_TOP<25> A_BLT_TOP<24> A_IWL<767> A_IWL<766> A_IWL<765> A_IWL<764> A_IWL<763> A_IWL<762> A_IWL<761> A_IWL<760> A_IWL<759> A_IWL<758> A_IWL<757> A_IWL<756> A_IWL<755> A_IWL<754> A_IWL<753> A_IWL<752> A_IWL<751> A_IWL<750> A_IWL<749> A_IWL<748> A_IWL<747> A_IWL<746> A_IWL<745> A_IWL<744> A_IWL<743> A_IWL<742> A_IWL<741> A_IWL<740> A_IWL<739> A_IWL<738> A_IWL<737> A_IWL<736> A_IWL<735> A_IWL<734> A_IWL<733> A_IWL<732> A_IWL<731> A_IWL<730> A_IWL<729> A_IWL<728> A_IWL<727> A_IWL<726> A_IWL<725> A_IWL<724> A_IWL<723> A_IWL<722> A_IWL<721> A_IWL<720> A_IWL<719> A_IWL<718> A_IWL<717> A_IWL<716> A_IWL<715> A_IWL<714> A_IWL<713> A_IWL<712> A_IWL<711> A_IWL<710> A_IWL<709> A_IWL<708> A_IWL<707> A_IWL<706> A_IWL<705> A_IWL<704> A_IWL<831> A_IWL<830> A_IWL<829> A_IWL<828> A_IWL<827> A_IWL<826> A_IWL<825> A_IWL<824> A_IWL<823> A_IWL<822> A_IWL<821> A_IWL<820> A_IWL<819> A_IWL<818> A_IWL<817> A_IWL<816> A_IWL<815> A_IWL<814> A_IWL<813> A_IWL<812> A_IWL<811> A_IWL<810> A_IWL<809> A_IWL<808> A_IWL<807> A_IWL<806> A_IWL<805> A_IWL<804> A_IWL<803> A_IWL<802> A_IWL<801> A_IWL<800> A_IWL<799> A_IWL<798> A_IWL<797> A_IWL<796> A_IWL<795> A_IWL<794> A_IWL<793> A_IWL<792> A_IWL<791> A_IWL<790> A_IWL<789> A_IWL<788> A_IWL<787> A_IWL<786> A_IWL<785> A_IWL<784> A_IWL<783> A_IWL<782> A_IWL<781> A_IWL<780> A_IWL<779> A_IWL<778> A_IWL<777> A_IWL<776> A_IWL<775> A_IWL<774> A_IWL<773> A_IWL<772> A_IWL<771> A_IWL<770> A_IWL<769> A_IWL<768> VDD_CORE VSS / RM_IHPSG13_256x16_c2_1P_COLUMN_pcell_0 +XCOL<11> A_BLC<23> A_BLC<22> A_BLC_TOP<23> A_BLC_TOP<22> A_BLT<23> A_BLT<22> A_BLT_TOP<23> A_BLT_TOP<22> A_IWL<703> A_IWL<702> A_IWL<701> A_IWL<700> A_IWL<699> A_IWL<698> A_IWL<697> A_IWL<696> A_IWL<695> A_IWL<694> A_IWL<693> A_IWL<692> A_IWL<691> A_IWL<690> A_IWL<689> A_IWL<688> A_IWL<687> A_IWL<686> A_IWL<685> A_IWL<684> A_IWL<683> A_IWL<682> A_IWL<681> A_IWL<680> A_IWL<679> A_IWL<678> A_IWL<677> A_IWL<676> A_IWL<675> A_IWL<674> A_IWL<673> A_IWL<672> A_IWL<671> A_IWL<670> A_IWL<669> A_IWL<668> A_IWL<667> A_IWL<666> A_IWL<665> A_IWL<664> A_IWL<663> A_IWL<662> A_IWL<661> A_IWL<660> A_IWL<659> A_IWL<658> A_IWL<657> A_IWL<656> A_IWL<655> A_IWL<654> A_IWL<653> A_IWL<652> A_IWL<651> A_IWL<650> A_IWL<649> A_IWL<648> A_IWL<647> A_IWL<646> A_IWL<645> A_IWL<644> A_IWL<643> A_IWL<642> A_IWL<641> A_IWL<640> A_IWL<767> A_IWL<766> A_IWL<765> A_IWL<764> A_IWL<763> A_IWL<762> A_IWL<761> A_IWL<760> A_IWL<759> A_IWL<758> A_IWL<757> A_IWL<756> A_IWL<755> A_IWL<754> A_IWL<753> A_IWL<752> A_IWL<751> A_IWL<750> A_IWL<749> A_IWL<748> A_IWL<747> A_IWL<746> A_IWL<745> A_IWL<744> A_IWL<743> A_IWL<742> A_IWL<741> A_IWL<740> A_IWL<739> A_IWL<738> A_IWL<737> A_IWL<736> A_IWL<735> A_IWL<734> A_IWL<733> A_IWL<732> A_IWL<731> A_IWL<730> A_IWL<729> A_IWL<728> A_IWL<727> A_IWL<726> A_IWL<725> A_IWL<724> A_IWL<723> A_IWL<722> A_IWL<721> A_IWL<720> A_IWL<719> A_IWL<718> A_IWL<717> A_IWL<716> A_IWL<715> A_IWL<714> A_IWL<713> A_IWL<712> A_IWL<711> A_IWL<710> A_IWL<709> A_IWL<708> A_IWL<707> A_IWL<706> A_IWL<705> A_IWL<704> VDD_CORE VSS / RM_IHPSG13_256x16_c2_1P_COLUMN_pcell_0 +XCOL<10> A_BLC<21> A_BLC<20> A_BLC_TOP<21> A_BLC_TOP<20> A_BLT<21> A_BLT<20> A_BLT_TOP<21> A_BLT_TOP<20> A_IWL<639> A_IWL<638> A_IWL<637> A_IWL<636> A_IWL<635> A_IWL<634> A_IWL<633> A_IWL<632> A_IWL<631> A_IWL<630> A_IWL<629> A_IWL<628> A_IWL<627> A_IWL<626> A_IWL<625> A_IWL<624> A_IWL<623> A_IWL<622> A_IWL<621> A_IWL<620> A_IWL<619> A_IWL<618> A_IWL<617> A_IWL<616> A_IWL<615> A_IWL<614> A_IWL<613> A_IWL<612> A_IWL<611> A_IWL<610> A_IWL<609> A_IWL<608> A_IWL<607> A_IWL<606> A_IWL<605> A_IWL<604> A_IWL<603> A_IWL<602> A_IWL<601> A_IWL<600> A_IWL<599> A_IWL<598> A_IWL<597> A_IWL<596> A_IWL<595> A_IWL<594> A_IWL<593> A_IWL<592> A_IWL<591> A_IWL<590> A_IWL<589> A_IWL<588> A_IWL<587> A_IWL<586> A_IWL<585> A_IWL<584> A_IWL<583> A_IWL<582> A_IWL<581> A_IWL<580> A_IWL<579> A_IWL<578> A_IWL<577> A_IWL<576> A_IWL<703> A_IWL<702> A_IWL<701> A_IWL<700> A_IWL<699> A_IWL<698> A_IWL<697> A_IWL<696> A_IWL<695> A_IWL<694> A_IWL<693> A_IWL<692> A_IWL<691> A_IWL<690> A_IWL<689> A_IWL<688> A_IWL<687> A_IWL<686> A_IWL<685> A_IWL<684> A_IWL<683> A_IWL<682> A_IWL<681> A_IWL<680> A_IWL<679> A_IWL<678> A_IWL<677> A_IWL<676> A_IWL<675> A_IWL<674> A_IWL<673> A_IWL<672> A_IWL<671> A_IWL<670> A_IWL<669> A_IWL<668> A_IWL<667> A_IWL<666> A_IWL<665> A_IWL<664> A_IWL<663> A_IWL<662> A_IWL<661> A_IWL<660> A_IWL<659> A_IWL<658> A_IWL<657> A_IWL<656> A_IWL<655> A_IWL<654> A_IWL<653> A_IWL<652> A_IWL<651> A_IWL<650> A_IWL<649> A_IWL<648> A_IWL<647> A_IWL<646> A_IWL<645> A_IWL<644> A_IWL<643> A_IWL<642> A_IWL<641> A_IWL<640> VDD_CORE VSS / RM_IHPSG13_256x16_c2_1P_COLUMN_pcell_0 +XCOL<9> A_BLC<19> A_BLC<18> A_BLC_TOP<19> A_BLC_TOP<18> A_BLT<19> A_BLT<18> A_BLT_TOP<19> A_BLT_TOP<18> A_IWL<575> A_IWL<574> A_IWL<573> A_IWL<572> A_IWL<571> A_IWL<570> A_IWL<569> A_IWL<568> A_IWL<567> A_IWL<566> A_IWL<565> A_IWL<564> A_IWL<563> A_IWL<562> A_IWL<561> A_IWL<560> A_IWL<559> A_IWL<558> A_IWL<557> A_IWL<556> A_IWL<555> A_IWL<554> A_IWL<553> A_IWL<552> A_IWL<551> A_IWL<550> A_IWL<549> A_IWL<548> A_IWL<547> A_IWL<546> A_IWL<545> A_IWL<544> A_IWL<543> A_IWL<542> A_IWL<541> A_IWL<540> A_IWL<539> A_IWL<538> A_IWL<537> A_IWL<536> A_IWL<535> A_IWL<534> A_IWL<533> A_IWL<532> A_IWL<531> A_IWL<530> A_IWL<529> A_IWL<528> A_IWL<527> A_IWL<526> A_IWL<525> A_IWL<524> A_IWL<523> A_IWL<522> A_IWL<521> A_IWL<520> A_IWL<519> A_IWL<518> A_IWL<517> A_IWL<516> A_IWL<515> A_IWL<514> A_IWL<513> A_IWL<512> A_IWL<639> A_IWL<638> A_IWL<637> A_IWL<636> A_IWL<635> A_IWL<634> A_IWL<633> A_IWL<632> A_IWL<631> A_IWL<630> A_IWL<629> A_IWL<628> A_IWL<627> A_IWL<626> A_IWL<625> A_IWL<624> A_IWL<623> A_IWL<622> A_IWL<621> A_IWL<620> A_IWL<619> A_IWL<618> A_IWL<617> A_IWL<616> A_IWL<615> A_IWL<614> A_IWL<613> A_IWL<612> A_IWL<611> A_IWL<610> A_IWL<609> A_IWL<608> A_IWL<607> A_IWL<606> A_IWL<605> A_IWL<604> A_IWL<603> A_IWL<602> A_IWL<601> A_IWL<600> A_IWL<599> A_IWL<598> A_IWL<597> A_IWL<596> A_IWL<595> A_IWL<594> A_IWL<593> A_IWL<592> A_IWL<591> A_IWL<590> A_IWL<589> A_IWL<588> A_IWL<587> A_IWL<586> A_IWL<585> A_IWL<584> A_IWL<583> A_IWL<582> A_IWL<581> A_IWL<580> A_IWL<579> A_IWL<578> A_IWL<577> A_IWL<576> VDD_CORE VSS / RM_IHPSG13_256x16_c2_1P_COLUMN_pcell_0 +XCOL<8> A_BLC<17> A_BLC<16> A_BLC_TOP<17> A_BLC_TOP<16> A_BLT<17> A_BLT<16> A_BLT_TOP<17> A_BLT_TOP<16> A_IWL<511> A_IWL<510> A_IWL<509> A_IWL<508> A_IWL<507> A_IWL<506> A_IWL<505> A_IWL<504> A_IWL<503> A_IWL<502> A_IWL<501> A_IWL<500> A_IWL<499> A_IWL<498> A_IWL<497> A_IWL<496> A_IWL<495> A_IWL<494> A_IWL<493> A_IWL<492> A_IWL<491> A_IWL<490> A_IWL<489> A_IWL<488> A_IWL<487> A_IWL<486> A_IWL<485> A_IWL<484> A_IWL<483> A_IWL<482> A_IWL<481> A_IWL<480> A_IWL<479> A_IWL<478> A_IWL<477> A_IWL<476> A_IWL<475> A_IWL<474> A_IWL<473> A_IWL<472> A_IWL<471> A_IWL<470> A_IWL<469> A_IWL<468> A_IWL<467> A_IWL<466> A_IWL<465> A_IWL<464> A_IWL<463> A_IWL<462> A_IWL<461> A_IWL<460> A_IWL<459> A_IWL<458> A_IWL<457> A_IWL<456> A_IWL<455> A_IWL<454> A_IWL<453> A_IWL<452> A_IWL<451> A_IWL<450> A_IWL<449> A_IWL<448> A_IWL<575> A_IWL<574> A_IWL<573> A_IWL<572> A_IWL<571> A_IWL<570> A_IWL<569> A_IWL<568> A_IWL<567> A_IWL<566> A_IWL<565> A_IWL<564> A_IWL<563> A_IWL<562> A_IWL<561> A_IWL<560> A_IWL<559> A_IWL<558> A_IWL<557> A_IWL<556> A_IWL<555> A_IWL<554> A_IWL<553> A_IWL<552> A_IWL<551> A_IWL<550> A_IWL<549> A_IWL<548> A_IWL<547> A_IWL<546> A_IWL<545> A_IWL<544> A_IWL<543> A_IWL<542> A_IWL<541> A_IWL<540> A_IWL<539> A_IWL<538> A_IWL<537> A_IWL<536> A_IWL<535> A_IWL<534> A_IWL<533> A_IWL<532> A_IWL<531> A_IWL<530> A_IWL<529> A_IWL<528> A_IWL<527> A_IWL<526> A_IWL<525> A_IWL<524> A_IWL<523> A_IWL<522> A_IWL<521> A_IWL<520> A_IWL<519> A_IWL<518> A_IWL<517> A_IWL<516> A_IWL<515> A_IWL<514> A_IWL<513> A_IWL<512> VDD_CORE VSS / RM_IHPSG13_256x16_c2_1P_COLUMN_pcell_0 +XCOL<7> A_BLC<15> A_BLC<14> A_BLC_TOP<15> A_BLC_TOP<14> A_BLT<15> A_BLT<14> A_BLT_TOP<15> A_BLT_TOP<14> A_IWL<447> A_IWL<446> A_IWL<445> A_IWL<444> A_IWL<443> A_IWL<442> A_IWL<441> A_IWL<440> A_IWL<439> A_IWL<438> A_IWL<437> A_IWL<436> A_IWL<435> A_IWL<434> A_IWL<433> A_IWL<432> A_IWL<431> A_IWL<430> A_IWL<429> A_IWL<428> A_IWL<427> A_IWL<426> A_IWL<425> A_IWL<424> A_IWL<423> A_IWL<422> A_IWL<421> A_IWL<420> A_IWL<419> A_IWL<418> A_IWL<417> A_IWL<416> A_IWL<415> A_IWL<414> A_IWL<413> A_IWL<412> A_IWL<411> A_IWL<410> A_IWL<409> A_IWL<408> A_IWL<407> A_IWL<406> A_IWL<405> A_IWL<404> A_IWL<403> A_IWL<402> A_IWL<401> A_IWL<400> A_IWL<399> A_IWL<398> A_IWL<397> A_IWL<396> A_IWL<395> A_IWL<394> A_IWL<393> A_IWL<392> A_IWL<391> A_IWL<390> A_IWL<389> A_IWL<388> A_IWL<387> A_IWL<386> A_IWL<385> A_IWL<384> A_IWL<511> A_IWL<510> A_IWL<509> A_IWL<508> A_IWL<507> A_IWL<506> A_IWL<505> A_IWL<504> A_IWL<503> A_IWL<502> A_IWL<501> A_IWL<500> A_IWL<499> A_IWL<498> A_IWL<497> A_IWL<496> A_IWL<495> A_IWL<494> A_IWL<493> A_IWL<492> A_IWL<491> A_IWL<490> A_IWL<489> A_IWL<488> A_IWL<487> A_IWL<486> A_IWL<485> A_IWL<484> A_IWL<483> A_IWL<482> A_IWL<481> A_IWL<480> A_IWL<479> A_IWL<478> A_IWL<477> A_IWL<476> A_IWL<475> A_IWL<474> A_IWL<473> A_IWL<472> A_IWL<471> A_IWL<470> A_IWL<469> A_IWL<468> A_IWL<467> A_IWL<466> A_IWL<465> A_IWL<464> A_IWL<463> A_IWL<462> A_IWL<461> A_IWL<460> A_IWL<459> A_IWL<458> A_IWL<457> A_IWL<456> A_IWL<455> A_IWL<454> A_IWL<453> A_IWL<452> A_IWL<451> A_IWL<450> A_IWL<449> A_IWL<448> VDD_CORE VSS / RM_IHPSG13_256x16_c2_1P_COLUMN_pcell_0 +XCOL<6> A_BLC<13> A_BLC<12> A_BLC_TOP<13> A_BLC_TOP<12> A_BLT<13> A_BLT<12> A_BLT_TOP<13> A_BLT_TOP<12> A_IWL<383> A_IWL<382> A_IWL<381> A_IWL<380> A_IWL<379> A_IWL<378> A_IWL<377> A_IWL<376> A_IWL<375> A_IWL<374> A_IWL<373> A_IWL<372> A_IWL<371> A_IWL<370> A_IWL<369> A_IWL<368> A_IWL<367> A_IWL<366> A_IWL<365> A_IWL<364> A_IWL<363> A_IWL<362> A_IWL<361> A_IWL<360> A_IWL<359> A_IWL<358> A_IWL<357> A_IWL<356> A_IWL<355> A_IWL<354> A_IWL<353> A_IWL<352> A_IWL<351> A_IWL<350> A_IWL<349> A_IWL<348> A_IWL<347> A_IWL<346> A_IWL<345> A_IWL<344> A_IWL<343> A_IWL<342> A_IWL<341> A_IWL<340> A_IWL<339> A_IWL<338> A_IWL<337> A_IWL<336> A_IWL<335> A_IWL<334> A_IWL<333> A_IWL<332> A_IWL<331> A_IWL<330> A_IWL<329> A_IWL<328> A_IWL<327> A_IWL<326> A_IWL<325> A_IWL<324> A_IWL<323> A_IWL<322> A_IWL<321> A_IWL<320> A_IWL<447> A_IWL<446> A_IWL<445> A_IWL<444> A_IWL<443> A_IWL<442> A_IWL<441> A_IWL<440> A_IWL<439> A_IWL<438> A_IWL<437> A_IWL<436> A_IWL<435> A_IWL<434> A_IWL<433> A_IWL<432> A_IWL<431> A_IWL<430> A_IWL<429> A_IWL<428> A_IWL<427> A_IWL<426> A_IWL<425> A_IWL<424> A_IWL<423> A_IWL<422> A_IWL<421> A_IWL<420> A_IWL<419> A_IWL<418> A_IWL<417> A_IWL<416> A_IWL<415> A_IWL<414> A_IWL<413> A_IWL<412> A_IWL<411> A_IWL<410> A_IWL<409> A_IWL<408> A_IWL<407> A_IWL<406> A_IWL<405> A_IWL<404> A_IWL<403> A_IWL<402> A_IWL<401> A_IWL<400> A_IWL<399> A_IWL<398> A_IWL<397> A_IWL<396> A_IWL<395> A_IWL<394> A_IWL<393> A_IWL<392> A_IWL<391> A_IWL<390> A_IWL<389> A_IWL<388> A_IWL<387> A_IWL<386> A_IWL<385> A_IWL<384> VDD_CORE VSS / RM_IHPSG13_256x16_c2_1P_COLUMN_pcell_0 +XCOL<5> A_BLC<11> A_BLC<10> A_BLC_TOP<11> A_BLC_TOP<10> A_BLT<11> A_BLT<10> A_BLT_TOP<11> A_BLT_TOP<10> A_IWL<319> A_IWL<318> A_IWL<317> A_IWL<316> A_IWL<315> A_IWL<314> A_IWL<313> A_IWL<312> A_IWL<311> A_IWL<310> A_IWL<309> A_IWL<308> A_IWL<307> A_IWL<306> A_IWL<305> A_IWL<304> A_IWL<303> A_IWL<302> A_IWL<301> A_IWL<300> A_IWL<299> A_IWL<298> A_IWL<297> A_IWL<296> A_IWL<295> A_IWL<294> A_IWL<293> A_IWL<292> A_IWL<291> A_IWL<290> A_IWL<289> A_IWL<288> A_IWL<287> A_IWL<286> A_IWL<285> A_IWL<284> A_IWL<283> A_IWL<282> A_IWL<281> A_IWL<280> A_IWL<279> A_IWL<278> A_IWL<277> A_IWL<276> A_IWL<275> A_IWL<274> A_IWL<273> A_IWL<272> A_IWL<271> A_IWL<270> A_IWL<269> A_IWL<268> A_IWL<267> A_IWL<266> A_IWL<265> A_IWL<264> A_IWL<263> A_IWL<262> A_IWL<261> A_IWL<260> A_IWL<259> A_IWL<258> A_IWL<257> A_IWL<256> A_IWL<383> A_IWL<382> A_IWL<381> A_IWL<380> A_IWL<379> A_IWL<378> A_IWL<377> A_IWL<376> A_IWL<375> A_IWL<374> A_IWL<373> A_IWL<372> A_IWL<371> A_IWL<370> A_IWL<369> A_IWL<368> A_IWL<367> A_IWL<366> A_IWL<365> A_IWL<364> A_IWL<363> A_IWL<362> A_IWL<361> A_IWL<360> A_IWL<359> A_IWL<358> A_IWL<357> A_IWL<356> A_IWL<355> A_IWL<354> A_IWL<353> A_IWL<352> A_IWL<351> A_IWL<350> A_IWL<349> A_IWL<348> A_IWL<347> A_IWL<346> A_IWL<345> A_IWL<344> A_IWL<343> A_IWL<342> A_IWL<341> A_IWL<340> A_IWL<339> A_IWL<338> A_IWL<337> A_IWL<336> A_IWL<335> A_IWL<334> A_IWL<333> A_IWL<332> A_IWL<331> A_IWL<330> A_IWL<329> A_IWL<328> A_IWL<327> A_IWL<326> A_IWL<325> A_IWL<324> A_IWL<323> A_IWL<322> A_IWL<321> A_IWL<320> VDD_CORE VSS / RM_IHPSG13_256x16_c2_1P_COLUMN_pcell_0 +XCOL<4> A_BLC<9> A_BLC<8> A_BLC_TOP<9> A_BLC_TOP<8> A_BLT<9> A_BLT<8> A_BLT_TOP<9> A_BLT_TOP<8> A_IWL<255> A_IWL<254> A_IWL<253> A_IWL<252> A_IWL<251> A_IWL<250> A_IWL<249> A_IWL<248> A_IWL<247> A_IWL<246> A_IWL<245> A_IWL<244> A_IWL<243> A_IWL<242> A_IWL<241> A_IWL<240> A_IWL<239> A_IWL<238> A_IWL<237> A_IWL<236> A_IWL<235> A_IWL<234> A_IWL<233> A_IWL<232> A_IWL<231> A_IWL<230> A_IWL<229> A_IWL<228> A_IWL<227> A_IWL<226> A_IWL<225> A_IWL<224> A_IWL<223> A_IWL<222> A_IWL<221> A_IWL<220> A_IWL<219> A_IWL<218> A_IWL<217> A_IWL<216> A_IWL<215> A_IWL<214> A_IWL<213> A_IWL<212> A_IWL<211> A_IWL<210> A_IWL<209> A_IWL<208> A_IWL<207> A_IWL<206> A_IWL<205> A_IWL<204> A_IWL<203> A_IWL<202> A_IWL<201> A_IWL<200> A_IWL<199> A_IWL<198> A_IWL<197> A_IWL<196> A_IWL<195> A_IWL<194> A_IWL<193> A_IWL<192> A_IWL<319> A_IWL<318> A_IWL<317> A_IWL<316> A_IWL<315> A_IWL<314> A_IWL<313> A_IWL<312> A_IWL<311> A_IWL<310> A_IWL<309> A_IWL<308> A_IWL<307> A_IWL<306> A_IWL<305> A_IWL<304> A_IWL<303> A_IWL<302> A_IWL<301> A_IWL<300> A_IWL<299> A_IWL<298> A_IWL<297> A_IWL<296> A_IWL<295> A_IWL<294> A_IWL<293> A_IWL<292> A_IWL<291> A_IWL<290> A_IWL<289> A_IWL<288> A_IWL<287> A_IWL<286> A_IWL<285> A_IWL<284> A_IWL<283> A_IWL<282> A_IWL<281> A_IWL<280> A_IWL<279> A_IWL<278> A_IWL<277> A_IWL<276> A_IWL<275> A_IWL<274> A_IWL<273> A_IWL<272> A_IWL<271> A_IWL<270> A_IWL<269> A_IWL<268> A_IWL<267> A_IWL<266> A_IWL<265> A_IWL<264> A_IWL<263> A_IWL<262> A_IWL<261> A_IWL<260> A_IWL<259> A_IWL<258> A_IWL<257> A_IWL<256> VDD_CORE VSS / RM_IHPSG13_256x16_c2_1P_COLUMN_pcell_0 +XCOL<3> A_BLC<7> A_BLC<6> A_BLC_TOP<7> A_BLC_TOP<6> A_BLT<7> A_BLT<6> A_BLT_TOP<7> A_BLT_TOP<6> A_IWL<191> A_IWL<190> A_IWL<189> A_IWL<188> A_IWL<187> A_IWL<186> A_IWL<185> A_IWL<184> A_IWL<183> A_IWL<182> A_IWL<181> A_IWL<180> A_IWL<179> A_IWL<178> A_IWL<177> A_IWL<176> A_IWL<175> A_IWL<174> A_IWL<173> A_IWL<172> A_IWL<171> A_IWL<170> A_IWL<169> A_IWL<168> A_IWL<167> A_IWL<166> A_IWL<165> A_IWL<164> A_IWL<163> A_IWL<162> A_IWL<161> A_IWL<160> A_IWL<159> A_IWL<158> A_IWL<157> A_IWL<156> A_IWL<155> A_IWL<154> A_IWL<153> A_IWL<152> A_IWL<151> A_IWL<150> A_IWL<149> A_IWL<148> A_IWL<147> A_IWL<146> A_IWL<145> A_IWL<144> A_IWL<143> A_IWL<142> A_IWL<141> A_IWL<140> A_IWL<139> A_IWL<138> A_IWL<137> A_IWL<136> A_IWL<135> A_IWL<134> A_IWL<133> A_IWL<132> A_IWL<131> A_IWL<130> A_IWL<129> A_IWL<128> A_IWL<255> A_IWL<254> A_IWL<253> A_IWL<252> A_IWL<251> A_IWL<250> A_IWL<249> A_IWL<248> A_IWL<247> A_IWL<246> A_IWL<245> A_IWL<244> A_IWL<243> A_IWL<242> A_IWL<241> A_IWL<240> A_IWL<239> A_IWL<238> A_IWL<237> A_IWL<236> A_IWL<235> A_IWL<234> A_IWL<233> A_IWL<232> A_IWL<231> A_IWL<230> A_IWL<229> A_IWL<228> A_IWL<227> A_IWL<226> A_IWL<225> A_IWL<224> A_IWL<223> A_IWL<222> A_IWL<221> A_IWL<220> A_IWL<219> A_IWL<218> A_IWL<217> A_IWL<216> A_IWL<215> A_IWL<214> A_IWL<213> A_IWL<212> A_IWL<211> A_IWL<210> A_IWL<209> A_IWL<208> A_IWL<207> A_IWL<206> A_IWL<205> A_IWL<204> A_IWL<203> A_IWL<202> A_IWL<201> A_IWL<200> A_IWL<199> A_IWL<198> A_IWL<197> A_IWL<196> A_IWL<195> A_IWL<194> A_IWL<193> A_IWL<192> VDD_CORE VSS / RM_IHPSG13_256x16_c2_1P_COLUMN_pcell_0 +XCOL<2> A_BLC<5> A_BLC<4> A_BLC_TOP<5> A_BLC_TOP<4> A_BLT<5> A_BLT<4> A_BLT_TOP<5> A_BLT_TOP<4> A_IWL<127> A_IWL<126> A_IWL<125> A_IWL<124> A_IWL<123> A_IWL<122> A_IWL<121> A_IWL<120> A_IWL<119> A_IWL<118> A_IWL<117> A_IWL<116> A_IWL<115> A_IWL<114> A_IWL<113> A_IWL<112> A_IWL<111> A_IWL<110> A_IWL<109> A_IWL<108> A_IWL<107> A_IWL<106> A_IWL<105> A_IWL<104> A_IWL<103> A_IWL<102> A_IWL<101> A_IWL<100> A_IWL<99> A_IWL<98> A_IWL<97> A_IWL<96> A_IWL<95> A_IWL<94> A_IWL<93> A_IWL<92> A_IWL<91> A_IWL<90> A_IWL<89> A_IWL<88> A_IWL<87> A_IWL<86> A_IWL<85> A_IWL<84> A_IWL<83> A_IWL<82> A_IWL<81> A_IWL<80> A_IWL<79> A_IWL<78> A_IWL<77> A_IWL<76> A_IWL<75> A_IWL<74> A_IWL<73> A_IWL<72> A_IWL<71> A_IWL<70> A_IWL<69> A_IWL<68> A_IWL<67> A_IWL<66> A_IWL<65> A_IWL<64> A_IWL<191> A_IWL<190> A_IWL<189> A_IWL<188> A_IWL<187> A_IWL<186> A_IWL<185> A_IWL<184> A_IWL<183> A_IWL<182> A_IWL<181> A_IWL<180> A_IWL<179> A_IWL<178> A_IWL<177> A_IWL<176> A_IWL<175> A_IWL<174> A_IWL<173> A_IWL<172> A_IWL<171> A_IWL<170> A_IWL<169> A_IWL<168> A_IWL<167> A_IWL<166> A_IWL<165> A_IWL<164> A_IWL<163> A_IWL<162> A_IWL<161> A_IWL<160> A_IWL<159> A_IWL<158> A_IWL<157> A_IWL<156> A_IWL<155> A_IWL<154> A_IWL<153> A_IWL<152> A_IWL<151> A_IWL<150> A_IWL<149> A_IWL<148> A_IWL<147> A_IWL<146> A_IWL<145> A_IWL<144> A_IWL<143> A_IWL<142> A_IWL<141> A_IWL<140> A_IWL<139> A_IWL<138> A_IWL<137> A_IWL<136> A_IWL<135> A_IWL<134> A_IWL<133> A_IWL<132> A_IWL<131> A_IWL<130> A_IWL<129> A_IWL<128> VDD_CORE VSS / RM_IHPSG13_256x16_c2_1P_COLUMN_pcell_0 +XCOL<1> A_BLC<3> A_BLC<2> A_BLC_TOP<3> A_BLC_TOP<2> A_BLT<3> A_BLT<2> A_BLT_TOP<3> A_BLT_TOP<2> A_IWL<63> A_IWL<62> A_IWL<61> A_IWL<60> A_IWL<59> A_IWL<58> A_IWL<57> A_IWL<56> A_IWL<55> A_IWL<54> A_IWL<53> A_IWL<52> A_IWL<51> A_IWL<50> A_IWL<49> A_IWL<48> A_IWL<47> A_IWL<46> A_IWL<45> A_IWL<44> A_IWL<43> A_IWL<42> A_IWL<41> A_IWL<40> A_IWL<39> A_IWL<38> A_IWL<37> A_IWL<36> A_IWL<35> A_IWL<34> A_IWL<33> A_IWL<32> A_IWL<31> A_IWL<30> A_IWL<29> A_IWL<28> A_IWL<27> A_IWL<26> A_IWL<25> A_IWL<24> A_IWL<23> A_IWL<22> A_IWL<21> A_IWL<20> A_IWL<19> A_IWL<18> A_IWL<17> A_IWL<16> A_IWL<15> A_IWL<14> A_IWL<13> A_IWL<12> A_IWL<11> A_IWL<10> A_IWL<9> A_IWL<8> A_IWL<7> A_IWL<6> A_IWL<5> A_IWL<4> A_IWL<3> A_IWL<2> A_IWL<1> A_IWL<0> A_IWL<127> A_IWL<126> A_IWL<125> A_IWL<124> A_IWL<123> A_IWL<122> A_IWL<121> A_IWL<120> A_IWL<119> A_IWL<118> A_IWL<117> A_IWL<116> A_IWL<115> A_IWL<114> A_IWL<113> A_IWL<112> A_IWL<111> A_IWL<110> A_IWL<109> A_IWL<108> A_IWL<107> A_IWL<106> A_IWL<105> A_IWL<104> A_IWL<103> A_IWL<102> A_IWL<101> A_IWL<100> A_IWL<99> A_IWL<98> A_IWL<97> A_IWL<96> A_IWL<95> A_IWL<94> A_IWL<93> A_IWL<92> A_IWL<91> A_IWL<90> A_IWL<89> A_IWL<88> A_IWL<87> A_IWL<86> A_IWL<85> A_IWL<84> A_IWL<83> A_IWL<82> A_IWL<81> A_IWL<80> A_IWL<79> A_IWL<78> A_IWL<77> A_IWL<76> A_IWL<75> A_IWL<74> A_IWL<73> A_IWL<72> A_IWL<71> A_IWL<70> A_IWL<69> A_IWL<68> A_IWL<67> A_IWL<66> A_IWL<65> A_IWL<64> VDD_CORE VSS / RM_IHPSG13_256x16_c2_1P_COLUMN_pcell_0 +XCOL<0> A_BLC<1> A_BLC<0> A_BLC_TOP<1> A_BLC_TOP<0> A_BLT<1> A_BLT<0> A_BLT_TOP<1> A_BLT_TOP<0> A_WL<63> A_WL<62> A_WL<61> A_WL<60> A_WL<59> A_WL<58> A_WL<57> A_WL<56> A_WL<55> A_WL<54> A_WL<53> A_WL<52> A_WL<51> A_WL<50> A_WL<49> A_WL<48> A_WL<47> A_WL<46> A_WL<45> A_WL<44> A_WL<43> A_WL<42> A_WL<41> A_WL<40> A_WL<39> A_WL<38> A_WL<37> A_WL<36> A_WL<35> A_WL<34> A_WL<33> A_WL<32> A_WL<31> A_WL<30> A_WL<29> A_WL<28> A_WL<27> A_WL<26> A_WL<25> A_WL<24> A_WL<23> A_WL<22> A_WL<21> A_WL<20> A_WL<19> A_WL<18> A_WL<17> A_WL<16> A_WL<15> A_WL<14> A_WL<13> A_WL<12> A_WL<11> A_WL<10> A_WL<9> A_WL<8> A_WL<7> A_WL<6> A_WL<5> A_WL<4> A_WL<3> A_WL<2> A_WL<1> A_WL<0> A_IWL<63> A_IWL<62> A_IWL<61> A_IWL<60> A_IWL<59> A_IWL<58> A_IWL<57> A_IWL<56> A_IWL<55> A_IWL<54> A_IWL<53> A_IWL<52> A_IWL<51> A_IWL<50> A_IWL<49> A_IWL<48> A_IWL<47> A_IWL<46> A_IWL<45> A_IWL<44> A_IWL<43> A_IWL<42> A_IWL<41> A_IWL<40> A_IWL<39> A_IWL<38> A_IWL<37> A_IWL<36> A_IWL<35> A_IWL<34> A_IWL<33> A_IWL<32> A_IWL<31> A_IWL<30> A_IWL<29> A_IWL<28> A_IWL<27> A_IWL<26> A_IWL<25> A_IWL<24> A_IWL<23> A_IWL<22> A_IWL<21> A_IWL<20> A_IWL<19> A_IWL<18> A_IWL<17> A_IWL<16> A_IWL<15> A_IWL<14> A_IWL<13> A_IWL<12> A_IWL<11> A_IWL<10> A_IWL<9> A_IWL<8> A_IWL<7> A_IWL<6> A_IWL<5> A_IWL<4> A_IWL<3> A_IWL<2> A_IWL<1> A_IWL<0> VDD_CORE VSS / RM_IHPSG13_256x16_c2_1P_COLUMN_pcell_0 +.ENDS + + + + +.SUBCKT RM_IHPSG13_256x16_c2_1P_DLY_pcell_2 A Z VDD VSS + XIDL D<7> Z VDD VSS / RSC_IHPSG13_CDLYX1 + XIDM<7> D<6> D<7> VDD VSS / RSC_IHPSG13_CDLYX1_DUMMY + XIDM<6> D<5> D<6> VDD VSS / RSC_IHPSG13_CDLYX1_DUMMY + XIDM<5> D<4> D<5> VDD VSS / RSC_IHPSG13_CDLYX1_DUMMY + XIDM<4> D<3> D<4> VDD VSS / RSC_IHPSG13_CDLYX1_DUMMY + XIDM<3> D<2> D<3> VDD VSS / RSC_IHPSG13_CDLYX1_DUMMY + XIDM<2> D<1> D<2> VDD VSS / RSC_IHPSG13_CDLYX1_DUMMY + XIDM<1> A D<1> VDD VSS / RSC_IHPSG13_CDLYX1_DUMMY +.ENDS + + +.SUBCKT RM_IHPSG13_256x16_c2_1P_DLY_pcell_3 A Z VDD VSS + XIDM<8> D<7> Z VDD VSS / RSC_IHPSG13_CDLYX1_DUMMY + XIDM<7> D<6> D<7> VDD VSS / RSC_IHPSG13_CDLYX1_DUMMY + XIDM<6> D<5> D<6> VDD VSS / RSC_IHPSG13_CDLYX1_DUMMY + XIDM<5> D<4> D<5> VDD VSS / RSC_IHPSG13_CDLYX1_DUMMY + XIDM<4> D<3> D<4> VDD VSS / RSC_IHPSG13_CDLYX1_DUMMY + XIDM<3> D<2> D<3> VDD VSS / RSC_IHPSG13_CDLYX1_DUMMY + XIDM<2> D<1> D<2> VDD VSS / RSC_IHPSG13_CDLYX1_DUMMY + XIDM<1> A D<1> VDD VSS / RSC_IHPSG13_CDLYX1_DUMMY +.ENDS + + + +.SUBCKT RM_IHPSG13_1P_256x16_c2_bm_bist A_ADDR<7> A_ADDR<6> A_ADDR<5> A_ADDR<4> A_ADDR<3> A_ADDR<2> A_ADDR<1> A_ADDR<0> A_BIST_ADDR<7> A_BIST_ADDR<6> A_BIST_ADDR<5> A_BIST_ADDR<4> A_BIST_ADDR<3> A_BIST_ADDR<2> A_BIST_ADDR<1> A_BIST_ADDR<0> A_BIST_BM<15> A_BIST_BM<14> A_BIST_BM<13> A_BIST_BM<12> A_BIST_BM<11> A_BIST_BM<10> A_BIST_BM<9> A_BIST_BM<8> A_BIST_BM<7> A_BIST_BM<6> A_BIST_BM<5> A_BIST_BM<4> A_BIST_BM<3> A_BIST_BM<2> A_BIST_BM<1> A_BIST_BM<0> A_BIST_CLK A_BIST_DIN<15> A_BIST_DIN<14> A_BIST_DIN<13> A_BIST_DIN<12> A_BIST_DIN<11> A_BIST_DIN<10> A_BIST_DIN<9> A_BIST_DIN<8> A_BIST_DIN<7> A_BIST_DIN<6> A_BIST_DIN<5> A_BIST_DIN<4> A_BIST_DIN<3> A_BIST_DIN<2> A_BIST_DIN<1> A_BIST_DIN<0> A_BIST_EN A_BIST_MEN A_BIST_REN A_BIST_WEN A_BM<15> A_BM<14> A_BM<13> A_BM<12> A_BM<11> A_BM<10> A_BM<9> A_BM<8> A_BM<7> A_BM<6> A_BM<5> A_BM<4> A_BM<3> A_BM<2> A_BM<1> A_BM<0> A_CLK A_DIN<15> A_DIN<14> A_DIN<13> A_DIN<12> A_DIN<11> A_DIN<10> A_DIN<9> A_DIN<8> A_DIN<7> A_DIN<6> A_DIN<5> A_DIN<4> A_DIN<3> A_DIN<2> A_DIN<1> A_DIN<0> A_DLY A_DOUT<15> A_DOUT<14> A_DOUT<13> A_DOUT<12> A_DOUT<11> A_DOUT<10> A_DOUT<9> A_DOUT<8> A_DOUT<7> A_DOUT<6> A_DOUT<5> A_DOUT<4> A_DOUT<3> A_DOUT<2> A_DOUT<1> A_DOUT<0> A_MEN A_REN A_WEN VDD! VDDARRAY! VSS! + + +XRAM<1> a_blc_r<31> a_blc_r<30> a_blc_r<29> a_blc_r<28> a_blc_r<27> a_blc_r<26> a_blc_r<25> a_blc_r<24> a_blc_r<23> a_blc_r<22> a_blc_r<21> a_blc_r<20> a_blc_r<19> a_blc_r<18> a_blc_r<17> a_blc_r<16> a_blc_r<15> a_blc_r<14> a_blc_r<13> a_blc_r<12> a_blc_r<11> a_blc_r<10> a_blc_r<9> a_blc_r<8> a_blc_r<7> a_blc_r<6> a_blc_r<5> a_blc_r<4> a_blc_r<3> a_blc_r<2> a_blc_r<1> a_blc_r<0> a_blt_r<31> a_blt_r<30> a_blt_r<29> a_blt_r<28> a_blt_r<27> a_blt_r<26> a_blt_r<25> a_blt_r<24> a_blt_r<23> a_blt_r<22> a_blt_r<21> a_blt_r<20> a_blt_r<19> a_blt_r<18> a_blt_r<17> a_blt_r<16> a_blt_r<15> a_blt_r<14> a_blt_r<13> a_blt_r<12> a_blt_r<11> a_blt_r<10> a_blt_r<9> a_blt_r<8> a_blt_r<7> a_blt_r<6> a_blt_r<5> a_blt_r<4> a_blt_r<3> a_blt_r<2> a_blt_r<1> a_blt_r<0> a_wl_r<63> a_wl_r<62> a_wl_r<61> a_wl_r<60> a_wl_r<59> a_wl_r<58> a_wl_r<57> a_wl_r<56> a_wl_r<55> a_wl_r<54> a_wl_r<53> a_wl_r<52> a_wl_r<51> a_wl_r<50> a_wl_r<49> a_wl_r<48> a_wl_r<47> a_wl_r<46> a_wl_r<45> a_wl_r<44> a_wl_r<43> a_wl_r<42> a_wl_r<41> a_wl_r<40> a_wl_r<39> a_wl_r<38> a_wl_r<37> a_wl_r<36> a_wl_r<35> a_wl_r<34> a_wl_r<33> a_wl_r<32> a_wl_r<31> a_wl_r<30> a_wl_r<29> a_wl_r<28> a_wl_r<27> a_wl_r<26> a_wl_r<25> a_wl_r<24> a_wl_r<23> a_wl_r<22> a_wl_r<21> a_wl_r<20> a_wl_r<19> a_wl_r<18> a_wl_r<17> a_wl_r<16> a_wl_r<15> a_wl_r<14> a_wl_r<13> a_wl_r<12> a_wl_r<11> a_wl_r<10> a_wl_r<9> a_wl_r<8> a_wl_r<7> a_wl_r<6> a_wl_r<5> a_wl_r<4> a_wl_r<3> a_wl_r<2> a_wl_r<1> a_wl_r<0> VDDARRAY! VSS! / RM_IHPSG13_256x16_c2_1P_MATRIX_pcell_1 +XRAM<0> a_blc_l<31> a_blc_l<30> a_blc_l<29> a_blc_l<28> a_blc_l<27> a_blc_l<26> a_blc_l<25> a_blc_l<24> a_blc_l<23> a_blc_l<22> a_blc_l<21> a_blc_l<20> a_blc_l<19> a_blc_l<18> a_blc_l<17> a_blc_l<16> a_blc_l<15> a_blc_l<14> a_blc_l<13> a_blc_l<12> a_blc_l<11> a_blc_l<10> a_blc_l<9> a_blc_l<8> a_blc_l<7> a_blc_l<6> a_blc_l<5> a_blc_l<4> a_blc_l<3> a_blc_l<2> a_blc_l<1> a_blc_l<0> a_blt_l<31> a_blt_l<30> a_blt_l<29> a_blt_l<28> a_blt_l<27> a_blt_l<26> a_blt_l<25> a_blt_l<24> a_blt_l<23> a_blt_l<22> a_blt_l<21> a_blt_l<20> a_blt_l<19> a_blt_l<18> a_blt_l<17> a_blt_l<16> a_blt_l<15> a_blt_l<14> a_blt_l<13> a_blt_l<12> a_blt_l<11> a_blt_l<10> a_blt_l<9> a_blt_l<8> a_blt_l<7> a_blt_l<6> a_blt_l<5> a_blt_l<4> a_blt_l<3> a_blt_l<2> a_blt_l<1> a_blt_l<0> a_wl_l<63> a_wl_l<62> a_wl_l<61> a_wl_l<60> a_wl_l<59> a_wl_l<58> a_wl_l<57> a_wl_l<56> a_wl_l<55> a_wl_l<54> a_wl_l<53> a_wl_l<52> a_wl_l<51> a_wl_l<50> a_wl_l<49> a_wl_l<48> a_wl_l<47> a_wl_l<46> a_wl_l<45> a_wl_l<44> a_wl_l<43> a_wl_l<42> a_wl_l<41> a_wl_l<40> a_wl_l<39> a_wl_l<38> a_wl_l<37> a_wl_l<36> a_wl_l<35> a_wl_l<34> a_wl_l<33> a_wl_l<32> a_wl_l<31> a_wl_l<30> a_wl_l<29> a_wl_l<28> a_wl_l<27> a_wl_l<26> a_wl_l<25> a_wl_l<24> a_wl_l<23> a_wl_l<22> a_wl_l<21> a_wl_l<20> a_wl_l<19> a_wl_l<18> a_wl_l<17> a_wl_l<16> a_wl_l<15> a_wl_l<14> a_wl_l<13> a_wl_l<12> a_wl_l<11> a_wl_l<10> a_wl_l<9> a_wl_l<8> a_wl_l<7> a_wl_l<6> a_wl_l<5> a_wl_l<4> a_wl_l<3> a_wl_l<2> a_wl_l<1> a_wl_l<0> VDDARRAY! VSS! / RM_IHPSG13_256x16_c2_1P_MATRIX_pcell_1 + + +XA_COLDRV<1> a_addr_col<1> a_addr_col<0> a_addr_col_r<1> a_addr_col_r<0> a_addr_dec<7> a_addr_dec<6> a_addr_dec<5> a_addr_dec<4> a_addr_dec<3> a_addr_dec<2> a_addr_dec<1> a_addr_dec<0> a_addr_dec_r<7> a_addr_dec_r<6> a_addr_dec_r<5> a_addr_dec_r<4> a_addr_dec_r<3> a_addr_dec_r<2> a_addr_dec_r<1> a_addr_dec_r<0> a_dclk a_dclk_p_r<0> a_rclk a_rclk_p_r<0> a_wclk a_wclk_p_r<0> VDD! VSS! / RM_IHPSG13_256x16_c2_1P_COLDRV13X4 +XA_COLDRV<0> a_addr_col<1> a_addr_col<0> a_addr_col_l<1> a_addr_col_l<0> a_addr_dec<7> a_addr_dec<6> a_addr_dec<5> a_addr_dec<4> a_addr_dec<3> a_addr_dec<2> a_addr_dec<1> a_addr_dec<0> a_addr_dec_l<7> a_addr_dec_l<6> a_addr_dec_l<5> a_addr_dec_l<4> a_addr_dec_l<3> a_addr_dec_l<2> a_addr_dec_l<1> a_addr_dec_l<0> a_dclk a_dclk_p_l<0> a_rclk a_rclk_p_l<0> a_wclk a_wclk_p_l<0> VDD! VSS! / RM_IHPSG13_256x16_c2_1P_COLDRV13X4 + + +XA_WLDRV<7> a_wi<63> a_wi<62> a_wi<61> a_wi<60> a_wi<59> a_wi<58> a_wi<57> a_wi<56> a_wi<55> a_wi<54> a_wi<53> a_wi<52> a_wi<51> a_wi<50> a_wi<49> a_wi<48> a_wl_r<63> a_wl_r<62> a_wl_r<61> a_wl_r<60> a_wl_r<59> a_wl_r<58> a_wl_r<57> a_wl_r<56> a_wl_r<55> a_wl_r<54> a_wl_r<53> a_wl_r<52> a_wl_r<51> a_wl_r<50> a_wl_r<49> a_wl_r<48> VDD! VSS! / RM_IHPSG13_256x16_c2_1P_WLDRV16X4 +XA_WLDRV<6> a_wi<47> a_wi<46> a_wi<45> a_wi<44> a_wi<43> a_wi<42> a_wi<41> a_wi<40> a_wi<39> a_wi<38> a_wi<37> a_wi<36> a_wi<35> a_wi<34> a_wi<33> a_wi<32> a_wl_r<47> a_wl_r<46> a_wl_r<45> a_wl_r<44> a_wl_r<43> a_wl_r<42> a_wl_r<41> a_wl_r<40> a_wl_r<39> a_wl_r<38> a_wl_r<37> a_wl_r<36> a_wl_r<35> a_wl_r<34> a_wl_r<33> a_wl_r<32> VDD! VSS! / RM_IHPSG13_256x16_c2_1P_WLDRV16X4 +XA_WLDRV<5> a_wi<31> a_wi<30> a_wi<29> a_wi<28> a_wi<27> a_wi<26> a_wi<25> a_wi<24> a_wi<23> a_wi<22> a_wi<21> a_wi<20> a_wi<19> a_wi<18> a_wi<17> a_wi<16> a_wl_r<31> a_wl_r<30> a_wl_r<29> a_wl_r<28> a_wl_r<27> a_wl_r<26> a_wl_r<25> a_wl_r<24> a_wl_r<23> a_wl_r<22> a_wl_r<21> a_wl_r<20> a_wl_r<19> a_wl_r<18> a_wl_r<17> a_wl_r<16> VDD! VSS! / RM_IHPSG13_256x16_c2_1P_WLDRV16X4 +XA_WLDRV<4> a_wi<15> a_wi<14> a_wi<13> a_wi<12> a_wi<11> a_wi<10> a_wi<9> a_wi<8> a_wi<7> a_wi<6> a_wi<5> a_wi<4> a_wi<3> a_wi<2> a_wi<1> a_wi<0> a_wl_r<15> a_wl_r<14> a_wl_r<13> a_wl_r<12> a_wl_r<11> a_wl_r<10> a_wl_r<9> a_wl_r<8> a_wl_r<7> a_wl_r<6> a_wl_r<5> a_wl_r<4> a_wl_r<3> a_wl_r<2> a_wl_r<1> a_wl_r<0> VDD! VSS! / RM_IHPSG13_256x16_c2_1P_WLDRV16X4 +XA_WLDRV<3> a_wi<63> a_wi<62> a_wi<61> a_wi<60> a_wi<59> a_wi<58> a_wi<57> a_wi<56> a_wi<55> a_wi<54> a_wi<53> a_wi<52> a_wi<51> a_wi<50> a_wi<49> a_wi<48> a_wl_l<63> a_wl_l<62> a_wl_l<61> a_wl_l<60> a_wl_l<59> a_wl_l<58> a_wl_l<57> a_wl_l<56> a_wl_l<55> a_wl_l<54> a_wl_l<53> a_wl_l<52> a_wl_l<51> a_wl_l<50> a_wl_l<49> a_wl_l<48> VDD! VSS! / RM_IHPSG13_256x16_c2_1P_WLDRV16X4 +XA_WLDRV<2> a_wi<47> a_wi<46> a_wi<45> a_wi<44> a_wi<43> a_wi<42> a_wi<41> a_wi<40> a_wi<39> a_wi<38> a_wi<37> a_wi<36> a_wi<35> a_wi<34> a_wi<33> a_wi<32> a_wl_l<47> a_wl_l<46> a_wl_l<45> a_wl_l<44> a_wl_l<43> a_wl_l<42> a_wl_l<41> a_wl_l<40> a_wl_l<39> a_wl_l<38> a_wl_l<37> a_wl_l<36> a_wl_l<35> a_wl_l<34> a_wl_l<33> a_wl_l<32> VDD! VSS! / RM_IHPSG13_256x16_c2_1P_WLDRV16X4 +XA_WLDRV<1> a_wi<31> a_wi<30> a_wi<29> a_wi<28> a_wi<27> a_wi<26> a_wi<25> a_wi<24> a_wi<23> a_wi<22> a_wi<21> a_wi<20> a_wi<19> a_wi<18> a_wi<17> a_wi<16> a_wl_l<31> a_wl_l<30> a_wl_l<29> a_wl_l<28> a_wl_l<27> a_wl_l<26> a_wl_l<25> a_wl_l<24> a_wl_l<23> a_wl_l<22> a_wl_l<21> a_wl_l<20> a_wl_l<19> a_wl_l<18> a_wl_l<17> a_wl_l<16> VDD! VSS! / RM_IHPSG13_256x16_c2_1P_WLDRV16X4 +XA_WLDRV<0> a_wi<15> a_wi<14> a_wi<13> a_wi<12> a_wi<11> a_wi<10> a_wi<9> a_wi<8> a_wi<7> a_wi<6> a_wi<5> a_wi<4> a_wi<3> a_wi<2> a_wi<1> a_wi<0> a_wl_l<15> a_wl_l<14> a_wl_l<13> a_wl_l<12> a_wl_l<11> a_wl_l<10> a_wl_l<9> a_wl_l<8> a_wl_l<7> a_wl_l<6> a_wl_l<5> a_wl_l<4> a_wl_l<3> a_wl_l<2> a_wl_l<1> a_wl_l<0> VDD! VSS! / RM_IHPSG13_256x16_c2_1P_WLDRV16X4 + + +XA_CTRL a_aclk_n A_BIST_CLK A_BIST_MEN A_BIST_EN A_BIST_REN A_BIST_WEN a_tiel A_CLK A_MEN a_dclk a_eclk a_pulse_h a_pulse_l a_pulse a_rclk A_REN a_cs a_wclk A_WEN VDD! VSS! / RM_IHPSG13_256x16_c2_1P_CTRL + + +XA_ROWDEC a_addr_row<5> a_addr_row<4> a_addr_row<3> a_addr_row<2> a_addr_row<1> a_addr_row<0> a_cs a_eclk a_wi<63> a_wi<62> a_wi<61> a_wi<60> a_wi<59> a_wi<58> a_wi<57> a_wi<56> a_wi<55> a_wi<54> a_wi<53> a_wi<52> a_wi<51> a_wi<50> a_wi<49> a_wi<48> a_wi<47> a_wi<46> a_wi<45> a_wi<44> a_wi<43> a_wi<42> a_wi<41> a_wi<40> a_wi<39> a_wi<38> a_wi<37> a_wi<36> a_wi<35> a_wi<34> a_wi<33> a_wi<32> a_wi<31> a_wi<30> a_wi<29> a_wi<28> a_wi<27> a_wi<26> a_wi<25> a_wi<24> a_wi<23> a_wi<22> a_wi<21> a_wi<20> a_wi<19> a_wi<18> a_wi<17> a_wi<16> a_wi<15> a_wi<14> a_wi<13> a_wi<12> a_wi<11> a_wi<10> a_wi<9> a_wi<8> a_wi<7> a_wi<6> a_wi<5> a_wi<4> a_wi<3> a_wi<2> a_wi<1> a_wi<0> VDD! VSS! / RM_IHPSG13_256x16_c2_1P_ROWDEC6 +XA_ROWREG a_aclk_n A_ADDR<7> A_ADDR<6> A_ADDR<5> A_ADDR<4> A_ADDR<3> A_ADDR<2> a_addr_row<5> a_addr_row<4> a_addr_row<3> a_addr_row<2> a_addr_row<1> a_addr_row<0> A_BIST_ADDR<7> A_BIST_ADDR<6> A_BIST_ADDR<5> A_BIST_ADDR<4> A_BIST_ADDR<3> A_BIST_ADDR<2> A_BIST_EN VDD! VSS! / RM_IHPSG13_256x16_c2_1P_ROWREG6 +XA_COLDEC a_aclk_n A_ADDR<1> A_ADDR<0> a_addr_col<1> a_addr_col<0> a_addr_dec<7> a_addr_dec<6> a_addr_dec<5> a_addr_dec<4> a_addr_dec<3> a_addr_dec<2> a_addr_dec<1> a_addr_dec<0> A_BIST_ADDR<1> A_BIST_ADDR<0> A_BIST_EN VDD! VSS! / RM_IHPSG13_256x16_c2_1P_COLDEC2 + + +XA_DLYH a_pulse a_pulse_h VDD! VSS! / RM_IHPSG13_256x16_c2_1P_DLY_pcell_2 +XA_DLYL a_pulse_x a_pulse_l VDD! VSS! / RM_IHPSG13_256x16_c2_1P_DLY_pcell_3 +XA_DLYMUX a_pulse_h A_DLY a_pulse_x VDD! VSS! / RM_IHPSG13_256x16_c2_1P_DLY_MUX + +XCOLCTRL<15> a_addr_dec_r<3> a_addr_dec_r<2> a_addr_dec_r<1> a_addr_dec_r<0> A_BIST_BM<15> A_BIST_DIN<15> A_BIST_EN a_blc_r<31> a_blc_r<30> a_blc_r<29> a_blc_r<28> a_blt_r<31> a_blt_r<30> a_blt_r<29> a_blt_r<28> A_BM<15> a_dclk_n_r<7> a_dclk_n_r<8> a_dclk_p_r<7> a_dclk_p_r<8> A_DOUT<15> A_DIN<15> a_rclk_n_r<7> a_rclk_n_r<8> a_rclk_p_r<7> a_rclk_p_r<8> a_tieh<15> a_wclk_n_r<7> a_wclk_n_r<8> a_wclk_p_r<7> a_wclk_p_r<8> VDD! VSS! / RM_IHPSG13_256x16_c2_1P_COLCTRL2 +XCOLCTRL<14> a_addr_dec_r<3> a_addr_dec_r<2> a_addr_dec_r<1> a_addr_dec_r<0> A_BIST_BM<14> A_BIST_DIN<14> A_BIST_EN a_blc_r<27> a_blc_r<26> a_blc_r<25> a_blc_r<24> a_blt_r<27> a_blt_r<26> a_blt_r<25> a_blt_r<24> A_BM<14> a_dclk_n_r<6> a_dclk_n_r<7> a_dclk_p_r<6> a_dclk_p_r<7> A_DOUT<14> A_DIN<14> a_rclk_n_r<6> a_rclk_n_r<7> a_rclk_p_r<6> a_rclk_p_r<7> a_tieh<14> a_wclk_n_r<6> a_wclk_n_r<7> a_wclk_p_r<6> a_wclk_p_r<7> VDD! VSS! / RM_IHPSG13_256x16_c2_1P_COLCTRL2 +XCOLCTRL<13> a_addr_dec_r<3> a_addr_dec_r<2> a_addr_dec_r<1> a_addr_dec_r<0> A_BIST_BM<13> A_BIST_DIN<13> A_BIST_EN a_blc_r<23> a_blc_r<22> a_blc_r<21> a_blc_r<20> a_blt_r<23> a_blt_r<22> a_blt_r<21> a_blt_r<20> A_BM<13> a_dclk_n_r<5> a_dclk_n_r<6> a_dclk_p_r<5> a_dclk_p_r<6> A_DOUT<13> A_DIN<13> a_rclk_n_r<5> a_rclk_n_r<6> a_rclk_p_r<5> a_rclk_p_r<6> a_tieh<13> a_wclk_n_r<5> a_wclk_n_r<6> a_wclk_p_r<5> a_wclk_p_r<6> VDD! VSS! / RM_IHPSG13_256x16_c2_1P_COLCTRL2 +XCOLCTRL<12> a_addr_dec_r<3> a_addr_dec_r<2> a_addr_dec_r<1> a_addr_dec_r<0> A_BIST_BM<12> A_BIST_DIN<12> A_BIST_EN a_blc_r<19> a_blc_r<18> a_blc_r<17> a_blc_r<16> a_blt_r<19> a_blt_r<18> a_blt_r<17> a_blt_r<16> A_BM<12> a_dclk_n_r<4> a_dclk_n_r<5> a_dclk_p_r<4> a_dclk_p_r<5> A_DOUT<12> A_DIN<12> a_rclk_n_r<4> a_rclk_n_r<5> a_rclk_p_r<4> a_rclk_p_r<5> a_tieh<12> a_wclk_n_r<4> a_wclk_n_r<5> a_wclk_p_r<4> a_wclk_p_r<5> VDD! VSS! / RM_IHPSG13_256x16_c2_1P_COLCTRL2 +XCOLCTRL<11> a_addr_dec_r<3> a_addr_dec_r<2> a_addr_dec_r<1> a_addr_dec_r<0> A_BIST_BM<11> A_BIST_DIN<11> A_BIST_EN a_blc_r<15> a_blc_r<14> a_blc_r<13> a_blc_r<12> a_blt_r<15> a_blt_r<14> a_blt_r<13> a_blt_r<12> A_BM<11> a_dclk_n_r<3> a_dclk_n_r<4> a_dclk_p_r<3> a_dclk_p_r<4> A_DOUT<11> A_DIN<11> a_rclk_n_r<3> a_rclk_n_r<4> a_rclk_p_r<3> a_rclk_p_r<4> a_tieh<11> a_wclk_n_r<3> a_wclk_n_r<4> a_wclk_p_r<3> a_wclk_p_r<4> VDD! VSS! / RM_IHPSG13_256x16_c2_1P_COLCTRL2 +XCOLCTRL<10> a_addr_dec_r<3> a_addr_dec_r<2> a_addr_dec_r<1> a_addr_dec_r<0> A_BIST_BM<10> A_BIST_DIN<10> A_BIST_EN a_blc_r<11> a_blc_r<10> a_blc_r<9> a_blc_r<8> a_blt_r<11> a_blt_r<10> a_blt_r<9> a_blt_r<8> A_BM<10> a_dclk_n_r<2> a_dclk_n_r<3> a_dclk_p_r<2> a_dclk_p_r<3> A_DOUT<10> A_DIN<10> a_rclk_n_r<2> a_rclk_n_r<3> a_rclk_p_r<2> a_rclk_p_r<3> a_tieh<10> a_wclk_n_r<2> a_wclk_n_r<3> a_wclk_p_r<2> a_wclk_p_r<3> VDD! VSS! / RM_IHPSG13_256x16_c2_1P_COLCTRL2 +XCOLCTRL<9> a_addr_dec_r<3> a_addr_dec_r<2> a_addr_dec_r<1> a_addr_dec_r<0> A_BIST_BM<9> A_BIST_DIN<9> A_BIST_EN a_blc_r<7> a_blc_r<6> a_blc_r<5> a_blc_r<4> a_blt_r<7> a_blt_r<6> a_blt_r<5> a_blt_r<4> A_BM<9> a_dclk_n_r<1> a_dclk_n_r<2> a_dclk_p_r<1> a_dclk_p_r<2> A_DOUT<9> A_DIN<9> a_rclk_n_r<1> a_rclk_n_r<2> a_rclk_p_r<1> a_rclk_p_r<2> a_tieh<9> a_wclk_n_r<1> a_wclk_n_r<2> a_wclk_p_r<1> a_wclk_p_r<2> VDD! VSS! / RM_IHPSG13_256x16_c2_1P_COLCTRL2 +XCOLCTRL<8> a_addr_dec_r<3> a_addr_dec_r<2> a_addr_dec_r<1> a_addr_dec_r<0> A_BIST_BM<8> A_BIST_DIN<8> A_BIST_EN a_blc_r<3> a_blc_r<2> a_blc_r<1> a_blc_r<0> a_blt_r<3> a_blt_r<2> a_blt_r<1> a_blt_r<0> A_BM<8> a_dclk_n_r<0> a_dclk_n_r<1> a_dclk_p_r<0> a_dclk_p_r<1> A_DOUT<8> A_DIN<8> a_rclk_n_r<0> a_rclk_n_r<1> a_rclk_p_r<0> a_rclk_p_r<1> a_tieh<8> a_wclk_n_r<0> a_wclk_n_r<1> a_wclk_p_r<0> a_wclk_p_r<1> VDD! VSS! / RM_IHPSG13_256x16_c2_1P_COLCTRL2 +XCOLCTRL<7> a_addr_dec_l<3> a_addr_dec_l<2> a_addr_dec_l<1> a_addr_dec_l<0> A_BIST_BM<0> A_BIST_DIN<0> A_BIST_EN a_blc_l<31> a_blc_l<30> a_blc_l<29> a_blc_l<28> a_blt_l<31> a_blt_l<30> a_blt_l<29> a_blt_l<28> A_BM<0> a_dclk_n_l<7> a_dclk_n_l<8> a_dclk_p_l<7> a_dclk_p_l<8> A_DOUT<0> A_DIN<0> a_rclk_n_l<7> a_rclk_n_l<8> a_rclk_p_l<7> a_rclk_p_l<8> a_tieh<0> a_wclk_n_l<7> a_wclk_n_l<8> a_wclk_p_l<7> a_wclk_p_l<8> VDD! VSS! / RM_IHPSG13_256x16_c2_1P_COLCTRL2 +XCOLCTRL<6> a_addr_dec_l<3> a_addr_dec_l<2> a_addr_dec_l<1> a_addr_dec_l<0> A_BIST_BM<1> A_BIST_DIN<1> A_BIST_EN a_blc_l<27> a_blc_l<26> a_blc_l<25> a_blc_l<24> a_blt_l<27> a_blt_l<26> a_blt_l<25> a_blt_l<24> A_BM<1> a_dclk_n_l<6> a_dclk_n_l<7> a_dclk_p_l<6> a_dclk_p_l<7> A_DOUT<1> A_DIN<1> a_rclk_n_l<6> a_rclk_n_l<7> a_rclk_p_l<6> a_rclk_p_l<7> a_tieh<1> a_wclk_n_l<6> a_wclk_n_l<7> a_wclk_p_l<6> a_wclk_p_l<7> VDD! VSS! / RM_IHPSG13_256x16_c2_1P_COLCTRL2 +XCOLCTRL<5> a_addr_dec_l<3> a_addr_dec_l<2> a_addr_dec_l<1> a_addr_dec_l<0> A_BIST_BM<2> A_BIST_DIN<2> A_BIST_EN a_blc_l<23> a_blc_l<22> a_blc_l<21> a_blc_l<20> a_blt_l<23> a_blt_l<22> a_blt_l<21> a_blt_l<20> A_BM<2> a_dclk_n_l<5> a_dclk_n_l<6> a_dclk_p_l<5> a_dclk_p_l<6> A_DOUT<2> A_DIN<2> a_rclk_n_l<5> a_rclk_n_l<6> a_rclk_p_l<5> a_rclk_p_l<6> a_tieh<2> a_wclk_n_l<5> a_wclk_n_l<6> a_wclk_p_l<5> a_wclk_p_l<6> VDD! VSS! / RM_IHPSG13_256x16_c2_1P_COLCTRL2 +XCOLCTRL<4> a_addr_dec_l<3> a_addr_dec_l<2> a_addr_dec_l<1> a_addr_dec_l<0> A_BIST_BM<3> A_BIST_DIN<3> A_BIST_EN a_blc_l<19> a_blc_l<18> a_blc_l<17> a_blc_l<16> a_blt_l<19> a_blt_l<18> a_blt_l<17> a_blt_l<16> A_BM<3> a_dclk_n_l<4> a_dclk_n_l<5> a_dclk_p_l<4> a_dclk_p_l<5> A_DOUT<3> A_DIN<3> a_rclk_n_l<4> a_rclk_n_l<5> a_rclk_p_l<4> a_rclk_p_l<5> a_tieh<3> a_wclk_n_l<4> a_wclk_n_l<5> a_wclk_p_l<4> a_wclk_p_l<5> VDD! VSS! / RM_IHPSG13_256x16_c2_1P_COLCTRL2 +XCOLCTRL<3> a_addr_dec_l<3> a_addr_dec_l<2> a_addr_dec_l<1> a_addr_dec_l<0> A_BIST_BM<4> A_BIST_DIN<4> A_BIST_EN a_blc_l<15> a_blc_l<14> a_blc_l<13> a_blc_l<12> a_blt_l<15> a_blt_l<14> a_blt_l<13> a_blt_l<12> A_BM<4> a_dclk_n_l<3> a_dclk_n_l<4> a_dclk_p_l<3> a_dclk_p_l<4> A_DOUT<4> A_DIN<4> a_rclk_n_l<3> a_rclk_n_l<4> a_rclk_p_l<3> a_rclk_p_l<4> a_tieh<4> a_wclk_n_l<3> a_wclk_n_l<4> a_wclk_p_l<3> a_wclk_p_l<4> VDD! VSS! / RM_IHPSG13_256x16_c2_1P_COLCTRL2 +XCOLCTRL<2> a_addr_dec_l<3> a_addr_dec_l<2> a_addr_dec_l<1> a_addr_dec_l<0> A_BIST_BM<5> A_BIST_DIN<5> A_BIST_EN a_blc_l<11> a_blc_l<10> a_blc_l<9> a_blc_l<8> a_blt_l<11> a_blt_l<10> a_blt_l<9> a_blt_l<8> A_BM<5> a_dclk_n_l<2> a_dclk_n_l<3> a_dclk_p_l<2> a_dclk_p_l<3> A_DOUT<5> A_DIN<5> a_rclk_n_l<2> a_rclk_n_l<3> a_rclk_p_l<2> a_rclk_p_l<3> a_tieh<5> a_wclk_n_l<2> a_wclk_n_l<3> a_wclk_p_l<2> a_wclk_p_l<3> VDD! VSS! / RM_IHPSG13_256x16_c2_1P_COLCTRL2 +XCOLCTRL<1> a_addr_dec_l<3> a_addr_dec_l<2> a_addr_dec_l<1> a_addr_dec_l<0> A_BIST_BM<6> A_BIST_DIN<6> A_BIST_EN a_blc_l<7> a_blc_l<6> a_blc_l<5> a_blc_l<4> a_blt_l<7> a_blt_l<6> a_blt_l<5> a_blt_l<4> A_BM<6> a_dclk_n_l<1> a_dclk_n_l<2> a_dclk_p_l<1> a_dclk_p_l<2> A_DOUT<6> A_DIN<6> a_rclk_n_l<1> a_rclk_n_l<2> a_rclk_p_l<1> a_rclk_p_l<2> a_tieh<6> a_wclk_n_l<1> a_wclk_n_l<2> a_wclk_p_l<1> a_wclk_p_l<2> VDD! VSS! / RM_IHPSG13_256x16_c2_1P_COLCTRL2 +XCOLCTRL<0> a_addr_dec_l<3> a_addr_dec_l<2> a_addr_dec_l<1> a_addr_dec_l<0> A_BIST_BM<7> A_BIST_DIN<7> A_BIST_EN a_blc_l<3> a_blc_l<2> a_blc_l<1> a_blc_l<0> a_blt_l<3> a_blt_l<2> a_blt_l<1> a_blt_l<0> A_BM<7> a_dclk_n_l<0> a_dclk_n_l<1> a_dclk_p_l<0> a_dclk_p_l<1> A_DOUT<7> A_DIN<7> a_rclk_n_l<0> a_rclk_n_l<1> a_rclk_p_l<0> a_rclk_p_l<1> a_tieh<7> a_wclk_n_l<0> a_wclk_n_l<1> a_wclk_p_l<0> a_wclk_p_l<1> VDD! VSS! / RM_IHPSG13_256x16_c2_1P_COLCTRL2 + + +XDRVFILL4<1> VDD! VSS! / RM_IHPSG13_256x16_c2_1P_COLDRV13_FILL4 +XDRVFILL4<2> VDD! VSS! / RM_IHPSG13_256x16_c2_1P_COLDRV13_FILL4 +XCOLFILL4<1> VDD! VSS! / RM_IHPSG13_256x16_c2_1P_COLDRV13_FILL4C2 +XCOLFILL4<2> VDD! VSS! / RM_IHPSG13_256x16_c2_1P_COLDRV13_FILL4C2 +XCOLFILL4<3> VDD! VSS! / RM_IHPSG13_256x16_c2_1P_COLDRV13_FILL4C2 +XCOLFILL4<4> VDD! VSS! / RM_IHPSG13_256x16_c2_1P_COLDRV13_FILL4C2 +XCOLFILL4<5> VDD! VSS! / RM_IHPSG13_256x16_c2_1P_COLDRV13_FILL4C2 +XCOLFILL4<6> VDD! VSS! / RM_IHPSG13_256x16_c2_1P_COLDRV13_FILL4C2 +.ENDS diff --git a/flow/platforms/ihp-sg13g2/cdl/RM_IHPSG13_1P_256x32_c2_bm_bist.cdl b/flow/platforms/ihp-sg13g2/cdl/RM_IHPSG13_1P_256x32_c2_bm_bist.cdl new file mode 100644 index 0000000000..aedfca6219 --- /dev/null +++ b/flow/platforms/ihp-sg13g2/cdl/RM_IHPSG13_1P_256x32_c2_bm_bist.cdl @@ -0,0 +1,6363 @@ +* ------------------------------------------------------ +* +* Copyright 2025 IHP PDK Authors +* +* Licensed under the Apache License, Version 2.0 (the "License"); +* you may not use this file except in compliance with the License. +* You may obtain a copy of the License at +* +* https://www.apache.org/licenses/LICENSE-2.0 +* +* Unless required by applicable law or agreed to in writing, software +* distributed under the License is distributed on an "AS IS" BASIS, +* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +* See the License for the specific language governing permissions and +* limitations under the License. +* +* Generated on Thu Aug 21 20:49:12 2025 +* +* ------------------------------------------------------ + +.SUBCKT RM_IHPSG13_256x32_c2_1P_BITKIT_CORNER NW PW VDD VSS +.ENDS +.SUBCKT RM_IHPSG13_256x32_c2_1P_BITKIT_16x2_CORNER VDD_CORE VSS +XI16 VDD_CORE VSS VDD_CORE VSS / ++ RM_IHPSG13_256x32_c2_1P_BITKIT_CORNER +.ENDS +.SUBCKT RM_IHPSG13_256x32_c2_1P_BITKIT_EDGE_LR LWL NW PW VDD VSS +MN1 VSS LWL VSS VSS sg13_lv_nmos m=1 w=300.0n l=130.00n ng=1 nrd=0 nrs=0 +MN0 VSS net9 VSS VSS sg13_lv_nmos m=1 w=300.0n l=130.00n ng=1 nrd=0 nrs=0 +.ENDS +.SUBCKT RM_IHPSG13_256x32_c2_1P_BITKIT_16x2_EDGE_LR A_WL<15> A_WL<14> A_WL<13> A_WL<12> ++ A_WL<11> A_WL<10> A_WL<9> A_WL<8> A_WL<7> A_WL<6> A_WL<5> A_WL<4> A_WL<3> ++ A_WL<2> A_WL<1> A_WL<0> VDD_CORE VSS +XI0<15> A_WL<15> VDD_CORE VSS VDD_CORE VSS / ++ RM_IHPSG13_256x32_c2_1P_BITKIT_EDGE_LR +XI0<14> A_WL<14> VDD_CORE VSS VDD_CORE VSS / ++ RM_IHPSG13_256x32_c2_1P_BITKIT_EDGE_LR +XI0<13> A_WL<13> VDD_CORE VSS VDD_CORE VSS / ++ RM_IHPSG13_256x32_c2_1P_BITKIT_EDGE_LR +XI0<12> A_WL<12> VDD_CORE VSS VDD_CORE VSS / ++ RM_IHPSG13_256x32_c2_1P_BITKIT_EDGE_LR +XI0<11> A_WL<11> VDD_CORE VSS VDD_CORE VSS / ++ RM_IHPSG13_256x32_c2_1P_BITKIT_EDGE_LR +XI0<10> A_WL<10> VDD_CORE VSS VDD_CORE VSS / ++ RM_IHPSG13_256x32_c2_1P_BITKIT_EDGE_LR +XI0<9> A_WL<9> VDD_CORE VSS VDD_CORE VSS / ++ RM_IHPSG13_256x32_c2_1P_BITKIT_EDGE_LR +XI0<8> A_WL<8> VDD_CORE VSS VDD_CORE VSS / ++ RM_IHPSG13_256x32_c2_1P_BITKIT_EDGE_LR +XI0<7> A_WL<7> VDD_CORE VSS VDD_CORE VSS / ++ RM_IHPSG13_256x32_c2_1P_BITKIT_EDGE_LR +XI0<6> A_WL<6> VDD_CORE VSS VDD_CORE VSS / ++ RM_IHPSG13_256x32_c2_1P_BITKIT_EDGE_LR +XI0<5> A_WL<5> VDD_CORE VSS VDD_CORE VSS / ++ RM_IHPSG13_256x32_c2_1P_BITKIT_EDGE_LR +XI0<4> A_WL<4> VDD_CORE VSS VDD_CORE VSS / ++ RM_IHPSG13_256x32_c2_1P_BITKIT_EDGE_LR +XI0<3> A_WL<3> VDD_CORE VSS VDD_CORE VSS / ++ RM_IHPSG13_256x32_c2_1P_BITKIT_EDGE_LR +XI0<2> A_WL<2> VDD_CORE VSS VDD_CORE VSS / ++ RM_IHPSG13_256x32_c2_1P_BITKIT_EDGE_LR +XI0<1> A_WL<1> VDD_CORE VSS VDD_CORE VSS / ++ RM_IHPSG13_256x32_c2_1P_BITKIT_EDGE_LR +XI0<0> A_WL<0> VDD_CORE VSS VDD_CORE VSS / ++ RM_IHPSG13_256x32_c2_1P_BITKIT_EDGE_LR +.ENDS +.SUBCKT RM_IHPSG13_256x32_c2_1P_BITKIT_CELL BLC_BOT BLC_TOP BLT_BOT BLT_TOP LWL NW PW ++ RWL VDD VSS +MN0 NC NT VSS PW sg13_lv_nmos m=1 w=300.0n l=130.00n ng=1 nrd=0 nrs=0 +MN1 NT NC VSS PW sg13_lv_nmos m=1 w=300.0n l=130.00n ng=1 nrd=0 nrs=0 +MN3 NC RWL BLC_TOP PW sg13_lv_nmos m=1 w=300.0n l=130.00n ng=1 nrd=0 nrs=0 +MN2 BLT_BOT LWL NT PW sg13_lv_nmos m=1 w=300.0n l=130.00n ng=1 nrd=0 nrs=0 +MP1 NT NC VDD NW sg13_lv_pmos m=1 w=150.00n l=130.00n ng=1 nrd=0 nrs=0 +MP0 NC NT VDD NW sg13_lv_pmos m=1 w=150.00n l=130.00n ng=1 nrd=0 nrs=0 +R1 BLC_BOT BLC_TOP lvsres w=2.6e-07 l=6e-07 +R0 BLT_BOT BLT_TOP lvsres w=2.6e-07 l=6e-07 +R2 RWL LWL lvsres w=2.6e-07 l=6e-07 +.ENDS +.SUBCKT RM_IHPSG13_256x32_c2_1P_BITKIT_16x2_SRAM A_BLC_BOT<1> A_BLC_BOT<0> A_BLC_TOP<1> ++ A_BLC_TOP<0> A_BLT_BOT<1> A_BLT_BOT<0> A_BLT_TOP<1> A_BLT_TOP<0> A_LWL<15> ++ A_LWL<14> A_LWL<13> A_LWL<12> A_LWL<11> A_LWL<10> A_LWL<9> A_LWL<8> A_LWL<7> ++ A_LWL<6> A_LWL<5> A_LWL<4> A_LWL<3> A_LWL<2> A_LWL<1> A_LWL<0> A_RWL<15> ++ A_RWL<14> A_RWL<13> A_RWL<12> A_RWL<11> A_RWL<10> A_RWL<9> A_RWL<8> A_RWL<7> ++ A_RWL<6> A_RWL<5> A_RWL<4> A_RWL<3> A_RWL<2> A_RWL<1> A_RWL<0> VDD_CORE ++ VSS +XCELL<31> A_BLC_TOP<1> A_RBLC<15> A_BLT_TOP<1> A_RBLT<15> A_RWL<15> ++ VDD_CORE VSS A_XWL<15> VDD_CORE VSS / ++ RM_IHPSG13_256x32_c2_1P_BITKIT_CELL +XCELL<30> A_RBLC<14> A_RBLC<15> A_RBLT<14> A_RBLT<15> A_RWL<14> VDD_CORE ++ VSS A_XWL<14> VDD_CORE VSS / RM_IHPSG13_256x32_c2_1P_BITKIT_CELL +XCELL<29> A_RBLC<14> A_RBLC<13> A_RBLT<14> A_RBLT<13> A_RWL<13> VDD_CORE ++ VSS A_XWL<13> VDD_CORE VSS / RM_IHPSG13_256x32_c2_1P_BITKIT_CELL +XCELL<28> A_RBLC<12> A_RBLC<13> A_RBLT<12> A_RBLT<13> A_RWL<12> VDD_CORE ++ VSS A_XWL<12> VDD_CORE VSS / RM_IHPSG13_256x32_c2_1P_BITKIT_CELL +XCELL<27> A_RBLC<12> A_RBLC<11> A_RBLT<12> A_RBLT<11> A_RWL<11> VDD_CORE ++ VSS A_XWL<11> VDD_CORE VSS / RM_IHPSG13_256x32_c2_1P_BITKIT_CELL +XCELL<26> A_RBLC<10> A_RBLC<11> A_RBLT<10> A_RBLT<11> A_RWL<10> VDD_CORE ++ VSS A_XWL<10> VDD_CORE VSS / RM_IHPSG13_256x32_c2_1P_BITKIT_CELL +XCELL<25> A_RBLC<10> A_RBLC<9> A_RBLT<10> A_RBLT<9> A_RWL<9> VDD_CORE ++ VSS A_XWL<9> VDD_CORE VSS / RM_IHPSG13_256x32_c2_1P_BITKIT_CELL +XCELL<24> A_RBLC<8> A_RBLC<9> A_RBLT<8> A_RBLT<9> A_RWL<8> VDD_CORE ++ VSS A_XWL<8> VDD_CORE VSS / RM_IHPSG13_256x32_c2_1P_BITKIT_CELL +XCELL<23> A_RBLC<8> A_RBLC<7> A_RBLT<8> A_RBLT<7> A_RWL<7> VDD_CORE ++ VSS A_XWL<7> VDD_CORE VSS / RM_IHPSG13_256x32_c2_1P_BITKIT_CELL +XCELL<22> A_RBLC<6> A_RBLC<7> A_RBLT<6> A_RBLT<7> A_RWL<6> VDD_CORE ++ VSS A_XWL<6> VDD_CORE VSS / RM_IHPSG13_256x32_c2_1P_BITKIT_CELL +XCELL<21> A_RBLC<6> A_RBLC<5> A_RBLT<6> A_RBLT<5> A_RWL<5> VDD_CORE ++ VSS A_XWL<5> VDD_CORE VSS / RM_IHPSG13_256x32_c2_1P_BITKIT_CELL +XCELL<20> A_RBLC<4> A_RBLC<5> A_RBLT<4> A_RBLT<5> A_RWL<4> VDD_CORE ++ VSS A_XWL<4> VDD_CORE VSS / RM_IHPSG13_256x32_c2_1P_BITKIT_CELL +XCELL<19> A_RBLC<4> A_RBLC<3> A_RBLT<4> A_RBLT<3> A_RWL<3> VDD_CORE ++ VSS A_XWL<3> VDD_CORE VSS / RM_IHPSG13_256x32_c2_1P_BITKIT_CELL +XCELL<18> A_RBLC<2> A_RBLC<3> A_RBLT<2> A_RBLT<3> A_RWL<2> VDD_CORE ++ VSS A_XWL<2> VDD_CORE VSS / RM_IHPSG13_256x32_c2_1P_BITKIT_CELL +XCELL<17> A_RBLC<2> A_RBLC<1> A_RBLT<2> A_RBLT<1> A_RWL<1> VDD_CORE ++ VSS A_XWL<1> VDD_CORE VSS / RM_IHPSG13_256x32_c2_1P_BITKIT_CELL +XCELL<16> A_BLC_BOT<1> A_RBLC<1> A_BLT_BOT<1> A_RBLT<1> A_RWL<0> VDD_CORE ++ VSS A_XWL<0> VDD_CORE VSS / RM_IHPSG13_256x32_c2_1P_BITKIT_CELL +XCELL<15> A_BLC_TOP<0> A_LBLC<15> A_BLT_TOP<0> A_LBLT<15> A_LWL<15> ++ VDD_CORE VSS A_XWL<15> VDD_CORE VSS / ++ RM_IHPSG13_256x32_c2_1P_BITKIT_CELL +XCELL<14> A_LBLC<14> A_LBLC<15> A_LBLT<14> A_LBLT<15> A_LWL<14> VDD_CORE ++ VSS A_XWL<14> VDD_CORE VSS / RM_IHPSG13_256x32_c2_1P_BITKIT_CELL +XCELL<13> A_LBLC<14> A_LBLC<13> A_LBLT<14> A_LBLT<13> A_LWL<13> VDD_CORE ++ VSS A_XWL<13> VDD_CORE VSS / RM_IHPSG13_256x32_c2_1P_BITKIT_CELL +XCELL<12> A_LBLC<12> A_LBLC<13> A_LBLT<12> A_LBLT<13> A_LWL<12> VDD_CORE ++ VSS A_XWL<12> VDD_CORE VSS / RM_IHPSG13_256x32_c2_1P_BITKIT_CELL +XCELL<11> A_LBLC<12> A_LBLC<11> A_LBLT<12> A_LBLT<11> A_LWL<11> VDD_CORE ++ VSS A_XWL<11> VDD_CORE VSS / RM_IHPSG13_256x32_c2_1P_BITKIT_CELL +XCELL<10> A_LBLC<10> A_LBLC<11> A_LBLT<10> A_LBLT<11> A_LWL<10> VDD_CORE ++ VSS A_XWL<10> VDD_CORE VSS / RM_IHPSG13_256x32_c2_1P_BITKIT_CELL +XCELL<9> A_LBLC<10> A_LBLC<9> A_LBLT<10> A_LBLT<9> A_LWL<9> VDD_CORE ++ VSS A_XWL<9> VDD_CORE VSS / RM_IHPSG13_256x32_c2_1P_BITKIT_CELL +XCELL<8> A_LBLC<8> A_LBLC<9> A_LBLT<8> A_LBLT<9> A_LWL<8> VDD_CORE ++ VSS A_XWL<8> VDD_CORE VSS / RM_IHPSG13_256x32_c2_1P_BITKIT_CELL +XCELL<7> A_LBLC<8> A_LBLC<7> A_LBLT<8> A_LBLT<7> A_LWL<7> VDD_CORE ++ VSS A_XWL<7> VDD_CORE VSS / RM_IHPSG13_256x32_c2_1P_BITKIT_CELL +XCELL<6> A_LBLC<6> A_LBLC<7> A_LBLT<6> A_LBLT<7> A_LWL<6> VDD_CORE ++ VSS A_XWL<6> VDD_CORE VSS / RM_IHPSG13_256x32_c2_1P_BITKIT_CELL +XCELL<5> A_LBLC<6> A_LBLC<5> A_LBLT<6> A_LBLT<5> A_LWL<5> VDD_CORE ++ VSS A_XWL<5> VDD_CORE VSS / RM_IHPSG13_256x32_c2_1P_BITKIT_CELL +XCELL<4> A_LBLC<4> A_LBLC<5> A_LBLT<4> A_LBLT<5> A_LWL<4> VDD_CORE ++ VSS A_XWL<4> VDD_CORE VSS / RM_IHPSG13_256x32_c2_1P_BITKIT_CELL +XCELL<3> A_LBLC<4> A_LBLC<3> A_LBLT<4> A_LBLT<3> A_LWL<3> VDD_CORE ++ VSS A_XWL<3> VDD_CORE VSS / RM_IHPSG13_256x32_c2_1P_BITKIT_CELL +XCELL<2> A_LBLC<2> A_LBLC<3> A_LBLT<2> A_LBLT<3> A_LWL<2> VDD_CORE ++ VSS A_XWL<2> VDD_CORE VSS / RM_IHPSG13_256x32_c2_1P_BITKIT_CELL +XCELL<1> A_LBLC<2> A_LBLC<1> A_LBLT<2> A_LBLT<1> A_LWL<1> VDD_CORE ++ VSS A_XWL<1> VDD_CORE VSS / RM_IHPSG13_256x32_c2_1P_BITKIT_CELL +XCELL<0> A_BLC_BOT<0> A_LBLC<1> A_BLT_BOT<0> A_LBLT<1> A_LWL<0> VDD_CORE ++ VSS A_XWL<0> VDD_CORE VSS / RM_IHPSG13_256x32_c2_1P_BITKIT_CELL +.ENDS +.SUBCKT RM_IHPSG13_256x32_c2_1P_BITKIT_EDGE_TB BLC BLT NW PW VDD VSS +.ENDS +.SUBCKT RM_IHPSG13_256x32_c2_1P_BITKIT_16x2_EDGE_TB A_BLC<1> A_BLC<0> A_BLT<1> A_BLT<0> ++ VDD_CORE VSS +XEDGE<1> A_BLC<1> A_BLT<1> VDD_CORE VSS VDD_CORE VSS ++ / RM_IHPSG13_256x32_c2_1P_BITKIT_EDGE_TB +XEDGE<0> A_BLC<0> A_BLT<0> VDD_CORE VSS VDD_CORE VSS ++ / RM_IHPSG13_256x32_c2_1P_BITKIT_EDGE_TB +.ENDS + +.SUBCKT RSC_IHPSG13_CBUFX4 A Z VDD VSS +MN0 net9 A VSS VSS sg13_lv_nmos m=1 w=705.000n l=130.00n ng=1 nrd=0 ++ nrs=0 +MN1 Z net9 VSS VSS sg13_lv_nmos m=1 w=1.41u l=130.00n ng=2 nrd=0 nrs=0 +MP0 net9 A VDD VDD sg13_lv_pmos m=1 w=1.62u l=130.00n ng=1 nrd=0 nrs=0 +MP1 Z net9 VDD VDD sg13_lv_pmos m=1 w=3.24u l=130.00n ng=2 nrd=0 nrs=0 +.ENDS +.SUBCKT RM_IHPSG13_256x32_c2_1P_COLDRV13X4 ADDR_COL_I<1> ADDR_COL_I<0> ADDR_COL_O<1> ++ ADDR_COL_O<0> ADDR_DEC_I<7> ADDR_DEC_I<6> ADDR_DEC_I<5> ADDR_DEC_I<4> ++ ADDR_DEC_I<3> ADDR_DEC_I<2> ADDR_DEC_I<1> ADDR_DEC_I<0> ADDR_DEC_O<7> ++ ADDR_DEC_O<6> ADDR_DEC_O<5> ADDR_DEC_O<4> ADDR_DEC_O<3> ADDR_DEC_O<2> ++ ADDR_DEC_O<1> ADDR_DEC_O<0> DCLK_I DCLK_O RCLK_I RCLK_O WCLK_I WCLK_O ++ VDD VSS +XADDR_COL_DRV<1> ADDR_COL_I<1> ADDR_COL_O<1> VDD VSS / ++ RSC_IHPSG13_CBUFX4 +XADDR_COL_DRV<0> ADDR_COL_I<0> ADDR_COL_O<0> VDD VSS / ++ RSC_IHPSG13_CBUFX4 +XADDR_DEC_DRV<7> ADDR_DEC_I<7> ADDR_DEC_O<7> VDD VSS / ++ RSC_IHPSG13_CBUFX4 +XADDR_DEC_DRV<6> ADDR_DEC_I<6> ADDR_DEC_O<6> VDD VSS / ++ RSC_IHPSG13_CBUFX4 +XADDR_DEC_DRV<5> ADDR_DEC_I<5> ADDR_DEC_O<5> VDD VSS / ++ RSC_IHPSG13_CBUFX4 +XADDR_DEC_DRV<4> ADDR_DEC_I<4> ADDR_DEC_O<4> VDD VSS / ++ RSC_IHPSG13_CBUFX4 +XADDR_DEC_DRV<3> ADDR_DEC_I<3> ADDR_DEC_O<3> VDD VSS / ++ RSC_IHPSG13_CBUFX4 +XADDR_DEC_DRV<2> ADDR_DEC_I<2> ADDR_DEC_O<2> VDD VSS / ++ RSC_IHPSG13_CBUFX4 +XADDR_DEC_DRV<1> ADDR_DEC_I<1> ADDR_DEC_O<1> VDD VSS / ++ RSC_IHPSG13_CBUFX4 +XADDR_DEC_DRV<0> ADDR_DEC_I<0> ADDR_DEC_O<0> VDD VSS / ++ RSC_IHPSG13_CBUFX4 +XDCLK_DRV DCLK_I DCLK_O VDD VSS / RSC_IHPSG13_CBUFX4 +XRCLK_DRV RCLK_I RCLK_O VDD VSS / RSC_IHPSG13_CBUFX4 +XWCLK_DRV WCLK_I WCLK_O VDD VSS / RSC_IHPSG13_CBUFX4 +.ENDS +.SUBCKT RSC_IHPSG13_WLDRVX4 A Z VDD VSS +MN1 Z net6 VSS VSS sg13_lv_nmos m=1 w=705.000n l=130.00n ng=1 nrd=0 ++ nrs=0 +MN0 net6 A VSS VSS sg13_lv_nmos m=1 w=900.0n l=130.00n ng=1 nrd=0 nrs=0 +MP1 Z net6 VDD VDD sg13_lv_pmos m=1 w=3.24u l=130.00n ng=2 nrd=0 nrs=0 +MP0 net6 A VDD VDD sg13_lv_pmos m=1 w=900.0n l=130.00n ng=1 nrd=0 nrs=0 +.ENDS +.SUBCKT RM_IHPSG13_256x32_c2_1P_WLDRV16X4 A<15> A<14> A<13> A<12> A<11> A<10> A<9> A<8> ++ A<7> A<6> A<5> A<4> A<3> A<2> A<1> A<0> Z<15> Z<14> Z<13> Z<12> Z<11> Z<10> ++ Z<9> Z<8> Z<7> Z<6> Z<5> Z<4> Z<3> Z<2> Z<1> Z<0> VDD VSS +XBUF<15> A<15> Z<15> VDD VSS / RSC_IHPSG13_WLDRVX4 +XBUF<14> A<14> Z<14> VDD VSS / RSC_IHPSG13_WLDRVX4 +XBUF<13> A<13> Z<13> VDD VSS / RSC_IHPSG13_WLDRVX4 +XBUF<12> A<12> Z<12> VDD VSS / RSC_IHPSG13_WLDRVX4 +XBUF<11> A<11> Z<11> VDD VSS / RSC_IHPSG13_WLDRVX4 +XBUF<10> A<10> Z<10> VDD VSS / RSC_IHPSG13_WLDRVX4 +XBUF<9> A<9> Z<9> VDD VSS / RSC_IHPSG13_WLDRVX4 +XBUF<8> A<8> Z<8> VDD VSS / RSC_IHPSG13_WLDRVX4 +XBUF<7> A<7> Z<7> VDD VSS / RSC_IHPSG13_WLDRVX4 +XBUF<6> A<6> Z<6> VDD VSS / RSC_IHPSG13_WLDRVX4 +XBUF<5> A<5> Z<5> VDD VSS / RSC_IHPSG13_WLDRVX4 +XBUF<4> A<4> Z<4> VDD VSS / RSC_IHPSG13_WLDRVX4 +XBUF<3> A<3> Z<3> VDD VSS / RSC_IHPSG13_WLDRVX4 +XBUF<2> A<2> Z<2> VDD VSS / RSC_IHPSG13_WLDRVX4 +XBUF<1> A<1> Z<1> VDD VSS / RSC_IHPSG13_WLDRVX4 +XBUF<0> A<0> Z<0> VDD VSS / RSC_IHPSG13_WLDRVX4 +.ENDS +.SUBCKT RSC_IHPSG13_FILLCAP8 VDD VSS +MN0 vss_r vdd_r VSS VSS sg13_lv_nmos m=1 w=4.98u l=130.00n ng=6 nrd=0 ++ nrs=0 +MP0 vdd_r vss_r VDD VDD sg13_lv_pmos m=1 w=6.48u l=385.000n ng=4 nrd=0 ++ nrs=0 +.ENDS +.SUBCKT RSC_IHPSG13_LHPQX2 CP D Q VDD VSS +MN3 QIN CPN net14 VSS sg13_lv_nmos m=1 w=480.00n l=130.00n ng=1 nrd=0 nrs=0 +MN2 net14 net10 VSS VSS sg13_lv_nmos m=1 w=480.00n l=130.00n ng=1 ++ nrd=0 nrs=0 +MN5 net21 D VSS VSS sg13_lv_nmos m=1 w=870.00n l=130.00n ng=1 nrd=0 ++ nrs=0 +MN6 QIN CP net21 VSS sg13_lv_nmos m=1 w=870.00n l=130.00n ng=1 nrd=0 nrs=0 +MN1 net10 QIN VSS VSS sg13_lv_nmos m=1 w=480.00n l=130.00n ng=1 nrd=0 ++ nrs=0 +MN0 CPN CP VSS VSS sg13_lv_nmos m=1 w=480.00n l=130.00n ng=1 nrd=0 ++ nrs=0 +MN4 Q QIN VSS VSS sg13_lv_nmos m=1 w=980.00n l=130.00n ng=1 nrd=0 nrs=0 +MP2 QIN CP net16 VDD sg13_lv_pmos m=1 w=480.00n l=130.00n ng=1 nrd=0 nrs=0 +MP0 CPN CP VDD VDD sg13_lv_pmos m=1 w=480.00n l=130.00n ng=1 nrd=0 ++ nrs=0 +MP4 Q QIN VDD VDD sg13_lv_pmos m=1 w=1.62u l=130.00n ng=1 nrd=0 nrs=0 +MP3 net10 QIN VDD VDD sg13_lv_pmos m=1 w=480.00n l=130.00n ng=1 nrd=0 ++ nrs=0 +MP1 net16 net10 VDD VDD sg13_lv_pmos m=1 w=480.00n l=130.00n ng=1 ++ nrd=0 nrs=0 +MP6 QIN CPN net20 VDD sg13_lv_pmos m=1 w=975.000n l=130.00n ng=1 nrd=0 ++ nrs=0 +MP5 net20 D VDD VDD sg13_lv_pmos m=1 w=975.000n l=130.00n ng=1 nrd=0 ++ nrs=0 +.ENDS +.SUBCKT RSC_IHPSG13_NAND2X2 A B Z VDD VSS +MP1 Z B VDD VDD sg13_lv_pmos m=1 w=1.62u l=130.00n ng=1 nrd=0 nrs=0 +MP0 Z A VDD VDD sg13_lv_pmos m=1 w=1.62u l=130.00n ng=1 nrd=0 nrs=0 +MN0 Z B net7 VSS sg13_lv_nmos m=1 w=980.00n l=130.00n ng=1 nrd=0 nrs=0 +MN1 net7 A VSS VSS sg13_lv_nmos m=1 w=980.00n l=130.00n ng=1 nrd=0 ++ nrs=0 +.ENDS +.SUBCKT RSC_IHPSG13_CINVX4 A Z VDD VSS +MN0 Z A VSS VSS sg13_lv_nmos m=1 w=1.41u l=130.00n ng=2 nrd=0 nrs=0 +MP0 Z A VDD VDD sg13_lv_pmos m=1 w=3.24u l=130.00n ng=2 nrd=0 nrs=0 +.ENDS +.SUBCKT RSC_IHPSG13_CINVX2 A Z VDD VSS +MN0 Z A VSS VSS sg13_lv_nmos m=1 w=705.000n l=130.00n ng=1 nrd=0 nrs=0 +MP0 Z A VDD VDD sg13_lv_pmos m=1 w=1.62u l=130.00n ng=1 nrd=0 nrs=0 +.ENDS +.SUBCKT RSC_IHPSG13_INVX2 A Z VDD VSS +MN0 Z A VSS VSS sg13_lv_nmos m=1 w=980.00n l=130.00n ng=1 nrd=0 nrs=0 +MP0 Z A VDD VDD sg13_lv_pmos m=1 w=1.62u l=130.00n ng=1 nrd=0 nrs=0 +.ENDS +.SUBCKT RSC_IHPSG13_NAND3X2 A B C Z VDD VSS +MP2 Z A VDD VDD sg13_lv_pmos m=1 w=1.62u l=130.00n ng=1 nrd=0 nrs=0 +MP1 Z B VDD VDD sg13_lv_pmos m=1 w=1.62u l=130.00n ng=1 nrd=0 nrs=0 +MP0 Z C VDD VDD sg13_lv_pmos m=1 w=1.62u l=130.00n ng=1 nrd=0 nrs=0 +MN1 net12 B net16 VSS sg13_lv_nmos m=1 w=980.00n l=130.00n ng=1 nrd=0 nrs=0 +MN0 Z C net12 VSS sg13_lv_nmos m=1 w=980.00n l=130.00n ng=1 nrd=0 nrs=0 +MN2 net16 A VSS VSS sg13_lv_nmos m=1 w=980.00n l=130.00n ng=1 nrd=0 ++ nrs=0 +.ENDS +.SUBCKT RSC_IHPSG13_NOR3X2 A B C Z VDD VSS +MP0 net13 A VDD VDD sg13_lv_pmos m=1 w=1.62u l=130.00n ng=1 nrd=0 nrs=0 +MP2 Z C net10 VDD sg13_lv_pmos m=1 w=1.62u l=130.00n ng=1 nrd=0 nrs=0 +MP1 net10 B net13 VDD sg13_lv_pmos m=1 w=1.62u l=130.00n ng=1 nrd=0 nrs=0 +MN1 Z B VSS VSS sg13_lv_nmos m=1 w=875.000n l=130.00n ng=1 nrd=0 nrs=0 +MN0 Z C VSS VSS sg13_lv_nmos m=1 w=875.000n l=130.00n ng=1 nrd=0 nrs=0 +MN2 Z A VSS VSS sg13_lv_nmos m=1 w=875.000n l=130.00n ng=1 nrd=0 nrs=0 +.ENDS +.SUBCKT RSC_IHPSG13_FILLCAP4 VDD VSS +MN0 vss_r vdd_r VSS VSS sg13_lv_nmos m=1 w=2.49u l=130.00n ng=3 nrd=0 ++ nrs=0 +MP0 vdd_r vss_r VDD VDD sg13_lv_pmos m=1 w=3.24u l=385.000n ng=2 nrd=0 ++ nrs=0 +.ENDS +.SUBCKT RSC_IHPSG13_MET2RES A B +R0 B A lvsres w=2.6e-07 l=6e-07 +.ENDS +.SUBCKT RM_IHPSG13_256x32_c2_1P_DEC04 ADDR<3> ADDR<2> ADDR<1> ADDR<0> CS ECLK_H_BOT ++ ECLK_H_TOP ECLK_L_BOT ECLK_L_TOP WL<15> WL<14> WL<13> WL<12> WL<11> WL<10> ++ WL<9> WL<8> WL<7> WL<6> WL<5> WL<4> WL<3> WL<2> WL<1> WL<0> VDD VSS +XLATCH<3> CS ADDR<3> PADR<3> VDD VSS / RSC_IHPSG13_LHPQX2 +XLATCH<2> CS ADDR<2> PADR<2> VDD VSS / RSC_IHPSG13_LHPQX2 +XLATCH<1> CS ADDR<1> PADR<1> VDD VSS / RSC_IHPSG13_LHPQX2 +XLATCH<0> CS ADDR<0> PADR<0> VDD VSS / RSC_IHPSG13_LHPQX2 +XI0<3> PADR<1> PADR<0> sel01<3> VDD VSS / RSC_IHPSG13_NAND2X2 +XI0<2> PADR<1> NADR<0> sel01<2> VDD VSS / RSC_IHPSG13_NAND2X2 +XI0<1> NADR<1> PADR<0> sel01<1> VDD VSS / RSC_IHPSG13_NAND2X2 +XI0<0> NADR<1> NADR<0> sel01<0> VDD VSS / RSC_IHPSG13_NAND2X2 +XI4 ECLK_L_BOT EN VDD VSS / RSC_IHPSG13_CINVX4 +XI5 ECLK_H_BOT ECLK_L_BOT VDD VSS / RSC_IHPSG13_CINVX2 +XI3<3> PADR<3> NADR<3> VDD VSS / RSC_IHPSG13_INVX2 +XI3<2> PADR<2> NADR<2> VDD VSS / RSC_IHPSG13_INVX2 +XI3<1> PADR<1> NADR<1> VDD VSS / RSC_IHPSG13_INVX2 +XI3<0> PADR<0> NADR<0> VDD VSS / RSC_IHPSG13_INVX2 +XI1<3> PADR<2> PADR<3> CS sel23<3> VDD VSS / RSC_IHPSG13_NAND3X2 +XI1<2> NADR<2> PADR<3> CS sel23<2> VDD VSS / RSC_IHPSG13_NAND3X2 +XI1<1> PADR<2> NADR<3> CS sel23<1> VDD VSS / RSC_IHPSG13_NAND3X2 +XI1<0> NADR<2> NADR<3> CS sel23<0> VDD VSS / RSC_IHPSG13_NAND3X2 +XI2<15> sel23<3> sel01<3> EN WL<15> VDD VSS / RSC_IHPSG13_NOR3X2 +XI2<14> sel23<3> sel01<2> EN WL<14> VDD VSS / RSC_IHPSG13_NOR3X2 +XI2<13> sel23<3> sel01<1> EN WL<13> VDD VSS / RSC_IHPSG13_NOR3X2 +XI2<12> sel23<3> sel01<0> EN WL<12> VDD VSS / RSC_IHPSG13_NOR3X2 +XI2<11> sel23<2> sel01<3> EN WL<11> VDD VSS / RSC_IHPSG13_NOR3X2 +XI2<10> sel23<2> sel01<2> EN WL<10> VDD VSS / RSC_IHPSG13_NOR3X2 +XI2<9> sel23<2> sel01<1> EN WL<9> VDD VSS / RSC_IHPSG13_NOR3X2 +XI2<8> sel23<2> sel01<0> EN WL<8> VDD VSS / RSC_IHPSG13_NOR3X2 +XI2<7> sel23<1> sel01<3> EN WL<7> VDD VSS / RSC_IHPSG13_NOR3X2 +XI2<6> sel23<1> sel01<2> EN WL<6> VDD VSS / RSC_IHPSG13_NOR3X2 +XI2<5> sel23<1> sel01<1> EN WL<5> VDD VSS / RSC_IHPSG13_NOR3X2 +XI2<4> sel23<1> sel01<0> EN WL<4> VDD VSS / RSC_IHPSG13_NOR3X2 +XI2<3> sel23<0> sel01<3> EN WL<3> VDD VSS / RSC_IHPSG13_NOR3X2 +XI2<2> sel23<0> sel01<2> EN WL<2> VDD VSS / RSC_IHPSG13_NOR3X2 +XI2<1> sel23<0> sel01<1> EN WL<1> VDD VSS / RSC_IHPSG13_NOR3X2 +XI2<0> sel23<0> sel01<0> EN WL<0> VDD VSS / RSC_IHPSG13_NOR3X2 +XCAPS4 VDD VSS / RSC_IHPSG13_FILLCAP4 +XI11 ECLK_L_BOT ECLK_L_TOP / RSC_IHPSG13_MET2RES +XR0 ECLK_H_BOT ECLK_H_TOP / RSC_IHPSG13_MET2RES +.ENDS +.SUBCKT RM_IHPSG13_256x32_c2_1P_ROWDEC4 ADDR_N_I<3> ADDR_N_I<2> ADDR_N_I<1> ADDR_N_I<0> ++ CS_I ECLK_I WL_O<15> WL_O<14> WL_O<13> WL_O<12> WL_O<11> WL_O<10> WL_O<9> ++ WL_O<8> WL_O<7> WL_O<6> WL_O<5> WL_O<4> WL_O<3> WL_O<2> WL_O<1> WL_O<0> ++ VDD VSS +XL2<8> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<7> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<6> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<5> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<4> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<3> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<2> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<1> VDD VSS / RSC_IHPSG13_FILLCAP8 +XSEL ADDR_N_I<3> ADDR_N_I<2> ADDR_N_I<1> ADDR_N_I<0> CS_I ECLK_I ECLK_H<1> ++ ECLK_B<0> ECLK_B<1> WL_O<15> WL_O<14> WL_O<13> WL_O<12> WL_O<11> WL_O<10> ++ WL_O<9> WL_O<8> WL_O<7> WL_O<6> WL_O<5> WL_O<4> WL_O<3> WL_O<2> WL_O<1> ++ WL_O<0> VDD VSS / RM_IHPSG13_256x32_c2_1P_DEC04 +.ENDS +.SUBCKT RSC_IHPSG13_CINVX8 A Z VDD VSS +MN0 Z A VSS VSS sg13_lv_nmos m=1 w=2.82u l=130.00n ng=4 nrd=0 nrs=0 +MP0 Z A VDD VDD sg13_lv_pmos m=1 w=6.48u l=130.00n ng=4 nrd=0 nrs=0 +.ENDS +.SUBCKT RSC_IHPSG13_DFNQMX2IX1 BE BI CN D QI QIN VDD VSS +MN15 net026 BI VSS VSS sg13_lv_nmos m=1 w=560.00n l=130.00n ng=1 nrd=0 ++ nrs=0 +MN14 MXI_OUT BE net026 VSS sg13_lv_nmos m=1 w=560.00n l=130.00n ng=1 nrd=0 ++ nrs=0 +MN1 net025 D VSS VSS sg13_lv_nmos m=1 w=560.00n l=130.00n ng=1 nrd=0 ++ nrs=0 +MN0 MXI_OUT BEN net025 VSS sg13_lv_nmos m=1 w=560.00n l=130.00n ng=1 nrd=0 ++ nrs=0 +MN10 QI CNN net21 VSS sg13_lv_nmos m=1 w=850.00n l=130.00n ng=1 nrd=0 nrs=0 +MN11 net21 QI_MS VSS VSS sg13_lv_nmos m=1 w=850.00n l=130.00n ng=1 ++ nrd=0 nrs=0 +MN7 net30 QI_MS VSS VSS sg13_lv_nmos m=1 w=480.00n l=130.00n ng=1 ++ nrd=0 nrs=0 +MN6 QIN_MS CNN net30 VSS sg13_lv_nmos m=1 w=480.00n l=130.00n ng=1 nrd=0 ++ nrs=0 +MN3 QI_MS QIN_MS VSS VSS sg13_lv_nmos m=1 w=480.00n l=130.00n ng=1 ++ nrd=0 nrs=0 +MN12 CNN CN VSS VSS sg13_lv_nmos m=1 w=495.000n l=130.00n ng=1 nrd=0 ++ nrs=0 +MN9 net37 MXI_OUT VSS VSS sg13_lv_nmos m=1 w=870.00n l=130.00n ng=1 ++ nrd=0 nrs=0 +MN8 QIN_MS CN net37 VSS sg13_lv_nmos m=1 w=870.00n l=130.00n ng=1 nrd=0 ++ nrs=0 +MN5 QI CN net25 VSS sg13_lv_nmos m=1 w=480.00n l=130.00n ng=1 nrd=0 nrs=0 +MN4 net25 QIN VSS VSS sg13_lv_nmos m=1 w=480.00n l=130.00n ng=1 nrd=0 ++ nrs=0 +MN2 QIN QI VSS VSS sg13_lv_nmos m=1 w=480.00n l=130.00n ng=1 nrd=0 ++ nrs=0 +MN13 BEN BE VSS VSS sg13_lv_nmos m=1 w=560.00n l=130.00n ng=1 nrd=0 ++ nrs=0 +MP15 MXI_OUT BEN net027 VDD sg13_lv_pmos m=1 w=985.000n l=130.00n ng=1 ++ nrd=0 nrs=0 +MP14 net027 BI VDD VDD sg13_lv_pmos m=1 w=985.000n l=130.00n ng=1 ++ nrd=0 nrs=0 +MP1 MXI_OUT BE net024 VDD sg13_lv_pmos m=1 w=985.000n l=130.00n ng=1 nrd=0 ++ nrs=0 +MP0 net024 D VDD VDD sg13_lv_pmos m=1 w=985.000n l=130.00n ng=1 nrd=0 ++ nrs=0 +MP13 BEN BE VDD VDD sg13_lv_pmos m=1 w=645.000n l=130.00n ng=1 nrd=0 ++ nrs=0 +MP6 QI_MS QIN_MS VDD VDD sg13_lv_pmos m=1 w=480.00n l=130.00n ng=1 ++ nrd=0 nrs=0 +MP3 QI CNN net27 VDD sg13_lv_pmos m=1 w=480.00n l=130.00n ng=1 nrd=0 nrs=0 +MP2 net27 QIN VDD VDD sg13_lv_pmos m=1 w=480.00n l=130.00n ng=1 nrd=0 ++ nrs=0 +MP10 net36 MXI_OUT VDD VDD sg13_lv_pmos m=1 w=975.000n l=130.00n ng=1 ++ nrd=0 nrs=0 +MP11 QIN_MS CNN net36 VDD sg13_lv_pmos m=1 w=975.000n l=130.00n ng=1 nrd=0 ++ nrs=0 +MP4 net32 QI_MS VDD VDD sg13_lv_pmos m=1 w=480.00n l=130.00n ng=1 ++ nrd=0 nrs=0 +MP5 QIN_MS CN net32 VDD sg13_lv_pmos m=1 w=480.00n l=130.00n ng=1 nrd=0 ++ nrs=0 +MP7 QIN QI VDD VDD sg13_lv_pmos m=1 w=480.00n l=130.00n ng=1 nrd=0 ++ nrs=0 +MP12 CNN CN VDD VDD sg13_lv_pmos m=1 w=480.00n l=130.00n ng=1 nrd=0 ++ nrs=0 +MP9 QI CN net19 VDD sg13_lv_pmos m=1 w=990.00n l=130.00n ng=1 nrd=0 nrs=0 +MP8 net19 QI_MS VDD VDD sg13_lv_pmos m=1 w=990.00n l=130.00n ng=1 ++ nrd=0 nrs=0 +.ENDS +.SUBCKT RM_IHPSG13_256x32_c2_1P_ROWREG4 ACLK_N_I ADDR_I<3> ADDR_I<2> ADDR_I<1> ADDR_I<0> ++ ADDR_N_O<3> ADDR_N_O<2> ADDR_N_O<1> ADDR_N_O<0> BIST_ADDR_I<3> ++ BIST_ADDR_I<2> BIST_ADDR_I<1> BIST_ADDR_I<0> BIST_EN_I VDD VSS +XINV<3> q_int<3> qn_int<3> VDD VSS / RSC_IHPSG13_CINVX2 +XINV<2> q_int<2> qn_int<2> VDD VSS / RSC_IHPSG13_CINVX2 +XINV<1> q_int<1> qn_int<1> VDD VSS / RSC_IHPSG13_CINVX2 +XINV<0> q_int<0> qn_int<0> VDD VSS / RSC_IHPSG13_CINVX2 +XDRV<3> qn_int<3> ADDR_N_O<3> VDD VSS / RSC_IHPSG13_CINVX8 +XDRV<2> qn_int<2> ADDR_N_O<2> VDD VSS / RSC_IHPSG13_CINVX8 +XDRV<1> qn_int<1> ADDR_N_O<1> VDD VSS / RSC_IHPSG13_CINVX8 +XDRV<0> qn_int<0> ADDR_N_O<0> VDD VSS / RSC_IHPSG13_CINVX8 +XDFF<3> BIST_EN_I BIST_ADDR_I<3> ACLK_N_I ADDR_I<3> q_int<3> net2<0> VDD ++ VSS / RSC_IHPSG13_DFNQMX2IX1 +XDFF<2> BIST_EN_I BIST_ADDR_I<2> ACLK_N_I ADDR_I<2> q_int<2> net2<1> VDD ++ VSS / RSC_IHPSG13_DFNQMX2IX1 +XDFF<1> BIST_EN_I BIST_ADDR_I<1> ACLK_N_I ADDR_I<1> q_int<1> net2<2> VDD ++ VSS / RSC_IHPSG13_DFNQMX2IX1 +XDFF<0> BIST_EN_I BIST_ADDR_I<0> ACLK_N_I ADDR_I<0> q_int<0> net2<3> VDD ++ VSS / RSC_IHPSG13_DFNQMX2IX1 +XI11<20> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI11<19> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI11<18> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI11<17> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI11<16> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI11<15> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI11<14> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI11<13> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI11<12> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI11<11> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI11<10> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI11<9> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI11<8> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI11<7> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI11<6> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI11<5> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI11<4> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI11<3> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI11<2> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI11<1> VDD VSS / RSC_IHPSG13_FILLCAP8 +.ENDS +.SUBCKT RSC_IHPSG13_CDLYX1 A Z VDD VSS +MN1 net010 net032 VSS VSS sg13_lv_nmos m=1 w=300.0n l=160.00n ng=1 ++ nrd=0 nrs=0 +MN2 net032 A net014 VSS sg13_lv_nmos m=1 w=300.0n l=160.00n ng=1 nrd=0 ++ nrs=0 +MN0 Z net032 net010 VSS sg13_lv_nmos m=1 w=300.0n l=160.00n ng=1 nrd=0 ++ nrs=0 +MN3 net014 A VSS VSS sg13_lv_nmos m=1 w=300.0n l=160.00n ng=1 nrd=0 ++ nrs=0 +MP1 Z net032 net07 VDD sg13_lv_pmos m=1 w=720.00n l=160.00n ng=1 nrd=0 ++ nrs=0 +MP3 net011 A VDD VDD sg13_lv_pmos m=1 w=720.00n l=160.00n ng=1 nrd=0 ++ nrs=0 +MP0 net07 net032 VDD VDD sg13_lv_pmos m=1 w=720.00n l=160.00n ng=1 ++ nrd=0 nrs=0 +MP2 net032 A net011 VDD sg13_lv_pmos m=1 w=720.00n l=160.00n ng=1 nrd=0 ++ nrs=0 +.ENDS +.SUBCKT RSC_IHPSG13_CDLYX1_DUMMY A Z VDD VSS +MN0 vss_r vdd_r VSS VSS sg13_lv_nmos m=1 w=2.49u l=300.0n ng=3 nrd=0 ++ nrs=0 +MP0 vdd_r vss_r VDD VDD sg13_lv_pmos m=1 w=3.24u l=640.00n ng=2 nrd=0 ++ nrs=0 +R0 Z A lvsres w=2.6e-07 l=6e-07 +.ENDS + +.SUBCKT RSC_IHPSG13_MX2IX1 A0 A1 S ZN VDD VSS +MP4 SN S VDD VDD sg13_lv_pmos m=1 w=645.000n l=130.00n ng=1 nrd=0 nrs=0 +MP3 ZN SN net12 VDD sg13_lv_pmos m=1 w=985.000n l=130.00n ng=1 nrd=0 nrs=0 +MP2 net12 A1 VDD VDD sg13_lv_pmos m=1 w=985.000n l=130.00n ng=1 nrd=0 ++ nrs=0 +MP1 ZN S net17 VDD sg13_lv_pmos m=1 w=985.000n l=130.00n ng=1 nrd=0 nrs=0 +MP0 net17 A0 VDD VDD sg13_lv_pmos m=1 w=985.000n l=130.00n ng=1 nrd=0 ++ nrs=0 +MN5 SN S VSS VSS sg13_lv_nmos m=1 w=480.00n l=130.00n ng=1 nrd=0 nrs=0 +MN3 net13 A1 VSS VSS sg13_lv_nmos m=1 w=480.00n l=130.00n ng=1 nrd=0 ++ nrs=0 +MN2 ZN S net13 VSS sg13_lv_nmos m=1 w=480.00n l=130.00n ng=1 nrd=0 nrs=0 +MN1 net15 A0 VSS VSS sg13_lv_nmos m=1 w=480.00n l=130.00n ng=1 nrd=0 ++ nrs=0 +MN0 ZN SN net15 VSS sg13_lv_nmos m=1 w=480.00n l=130.00n ng=1 nrd=0 nrs=0 +.ENDS +.SUBCKT RM_IHPSG13_256x32_c2_1P_DLY_MUX A SEL Z VDD VSS +XI11 net4 Z VDD VSS / RSC_IHPSG13_CINVX2 +XI8 A D<3> SEL net4 VDD VSS / RSC_IHPSG13_MX2IX1 +XI20<3> D<2> D<3> VDD VSS / RSC_IHPSG13_CDLYX1 +XI20<2> D<1> D<2> VDD VSS / RSC_IHPSG13_CDLYX1 +XI20<1> A D<1> VDD VSS / RSC_IHPSG13_CDLYX1 +.ENDS +.SUBCKT RSC_IHPSG13_DFNQX2 CN D Q VDD VSS +MN0 Q QIN_SL VSS VSS sg13_lv_nmos m=1 w=980.00n l=130.00n ng=1 nrd=0 ++ nrs=0 +MN10 QIN_SL CNN net21 VSS sg13_lv_nmos m=1 w=850.00n l=130.00n ng=1 nrd=0 ++ nrs=0 +MN11 net21 QI_MS VSS VSS sg13_lv_nmos m=1 w=850.00n l=130.00n ng=1 ++ nrd=0 nrs=0 +MN7 net30 QI_MS VSS VSS sg13_lv_nmos m=1 w=480.00n l=130.00n ng=1 ++ nrd=0 nrs=0 +MN6 QIN_MS CNN net30 VSS sg13_lv_nmos m=1 w=480.00n l=130.00n ng=1 nrd=0 ++ nrs=0 +MN3 QI_MS QIN_MS VSS VSS sg13_lv_nmos m=1 w=480.00n l=130.00n ng=1 ++ nrd=0 nrs=0 +MN12 CNN CN VSS VSS sg13_lv_nmos m=1 w=495.000n l=130.00n ng=1 nrd=0 ++ nrs=0 +MN9 net37 D VSS VSS sg13_lv_nmos m=1 w=870.00n l=130.00n ng=1 nrd=0 ++ nrs=0 +MN8 QIN_MS CN net37 VSS sg13_lv_nmos m=1 w=870.00n l=130.00n ng=1 nrd=0 ++ nrs=0 +MN5 QIN_SL CN net25 VSS sg13_lv_nmos m=1 w=480.00n l=130.00n ng=1 nrd=0 ++ nrs=0 +MN4 net25 QI_SL VSS VSS sg13_lv_nmos m=1 w=480.00n l=130.00n ng=1 ++ nrd=0 nrs=0 +MN2 QI_SL QIN_SL VSS VSS sg13_lv_nmos m=1 w=480.00n l=130.00n ng=1 ++ nrd=0 nrs=0 +MP0 Q QIN_SL VDD VDD sg13_lv_pmos m=1 w=1.62u l=130.00n ng=1 nrd=0 ++ nrs=0 +MP6 QI_MS QIN_MS VDD VDD sg13_lv_pmos m=1 w=480.00n l=130.00n ng=1 ++ nrd=0 nrs=0 +MP3 QIN_SL CNN net27 VDD sg13_lv_pmos m=1 w=480.00n l=130.00n ng=1 nrd=0 ++ nrs=0 +MP2 net27 QI_SL VDD VDD sg13_lv_pmos m=1 w=480.00n l=130.00n ng=1 ++ nrd=0 nrs=0 +MP10 net36 D VDD VDD sg13_lv_pmos m=1 w=975.000n l=130.00n ng=1 nrd=0 ++ nrs=0 +MP11 QIN_MS CNN net36 VDD sg13_lv_pmos m=1 w=975.000n l=130.00n ng=1 nrd=0 ++ nrs=0 +MP4 net32 QI_MS VDD VDD sg13_lv_pmos m=1 w=480.00n l=130.00n ng=1 ++ nrd=0 nrs=0 +MP5 QIN_MS CN net32 VDD sg13_lv_pmos m=1 w=480.00n l=130.00n ng=1 nrd=0 ++ nrs=0 +MP7 QI_SL QIN_SL VDD VDD sg13_lv_pmos m=1 w=480.00n l=130.00n ng=1 ++ nrd=0 nrs=0 +MP12 CNN CN VDD VDD sg13_lv_pmos m=1 w=480.00n l=130.00n ng=1 nrd=0 ++ nrs=0 +MP9 QIN_SL CN net19 VDD sg13_lv_pmos m=1 w=990.00n l=130.00n ng=1 nrd=0 ++ nrs=0 +MP8 net19 QI_MS VDD VDD sg13_lv_pmos m=1 w=990.00n l=130.00n ng=1 ++ nrd=0 nrs=0 +.ENDS +.SUBCKT RSC_IHPSG13_CNAND2X2 A B Z VDD VSS +MN0 Z B net6 VSS sg13_lv_nmos m=1 w=980.00n l=130.00n ng=1 nrd=0 nrs=0 +MN1 net6 A VSS VSS sg13_lv_nmos m=1 w=980.00n l=130.00n ng=1 nrd=0 ++ nrs=0 +MP1 Z B VDD VDD sg13_lv_pmos m=1 w=1.62u l=130.00n ng=1 nrd=0 nrs=0 +MP0 Z A VDD VDD sg13_lv_pmos m=1 w=1.62u l=130.00n ng=1 nrd=0 nrs=0 +.ENDS +.SUBCKT RSC_IHPSG13_CGATEPX4 CP E Q VDD VSS +MN1 net08 QIN VSS VSS sg13_lv_nmos m=1 w=480.00n l=130.00n ng=1 nrd=0 ++ nrs=0 +MN2 net019 net08 VSS VSS sg13_lv_nmos m=1 w=480.00n l=130.00n ng=1 ++ nrd=0 nrs=0 +MN3 QIN CP net019 VSS sg13_lv_nmos m=1 w=480.00n l=130.00n ng=1 nrd=0 nrs=0 +MN6 Q net015 VSS VSS sg13_lv_nmos m=1 w=1.41u l=130.00n ng=2 nrd=0 ++ nrs=0 +MN5 net015 net08 net018 VSS sg13_lv_nmos m=1 w=980.00n l=130.00n ng=1 ++ nrd=0 nrs=0 +MN8 QIN CPN net023 VSS sg13_lv_nmos m=1 w=870.00n l=130.00n ng=1 nrd=0 ++ nrs=0 +MN7 net023 E VSS VSS sg13_lv_nmos m=1 w=870.00n l=130.00n ng=1 nrd=0 ++ nrs=0 +MN4 net018 CP VSS VSS sg13_lv_nmos m=1 w=980.00n l=130.00n ng=1 nrd=0 ++ nrs=0 +MN0 CPN CP VSS VSS sg13_lv_nmos m=1 w=500.0n l=130.00n ng=1 nrd=0 nrs=0 +MP3 net08 QIN VDD VDD sg13_lv_pmos m=1 w=480.00n l=130.00n ng=1 nrd=0 ++ nrs=0 +MP2 QIN CPN net017 VDD sg13_lv_pmos m=1 w=480.00n l=130.00n ng=1 nrd=0 ++ nrs=0 +MP1 net017 net08 VDD VDD sg13_lv_pmos m=1 w=480.00n l=130.00n ng=1 ++ nrd=0 nrs=0 +MP0 CPN CP VDD VDD sg13_lv_pmos m=1 w=500.0n l=130.00n ng=1 nrd=0 nrs=0 +MP8 QIN CP net024 VDD sg13_lv_pmos m=1 w=975.000n l=130.00n ng=1 nrd=0 ++ nrs=0 +MP7 net024 E VDD VDD sg13_lv_pmos m=1 w=975.000n l=130.00n ng=1 nrd=0 ++ nrs=0 +MP4 net015 CP VDD VDD sg13_lv_pmos m=1 w=1.27u l=130.00n ng=1 nrd=0 ++ nrs=0 +MP6 Q net015 VDD VDD sg13_lv_pmos m=1 w=3.24u l=130.00n ng=2 nrd=0 ++ nrs=0 +MP5 net015 net08 VDD VDD sg13_lv_pmos m=1 w=1.27u l=130.00n ng=1 nrd=0 ++ nrs=0 +.ENDS +.SUBCKT RSC_IHPSG13_CBUFX8 A Z VDD VSS +MP0 net4 A VDD VDD sg13_lv_pmos m=1 w=3.24u l=130.00n ng=2 nrd=0 nrs=0 +MP1 Z net4 VDD VDD sg13_lv_pmos m=1 w=6.48u l=130.00n ng=4 nrd=0 nrs=0 +MN1 Z net4 VSS VSS sg13_lv_nmos m=1 w=2.82u l=130.00n ng=4 nrd=0 nrs=0 +MN0 net4 A VSS VSS sg13_lv_nmos m=1 w=1.41u l=130.00n ng=2 nrd=0 nrs=0 +.ENDS +.SUBCKT RSC_IHPSG13_CDLYX2 A Z VDD VSS +MN2 net4 A net9 VSS sg13_lv_nmos m=1 w=320.00n l=200.0n ng=1 nrd=0 nrs=0 +MN0 Z net4 VSS VSS sg13_lv_nmos m=1 w=705.000n l=130.00n ng=1 nrd=0 ++ nrs=0 +MN1 net9 A VSS VSS sg13_lv_nmos m=1 w=320.00n l=200.0n ng=1 nrd=0 nrs=0 +MP2 net4 A net10 VDD sg13_lv_pmos m=1 w=1.2u l=200.0n ng=1 nrd=0 nrs=0 +MP1 net10 A VDD VDD sg13_lv_pmos m=1 w=1.2u l=200.0n ng=1 nrd=0 nrs=0 +MP0 Z net4 VDD VDD sg13_lv_pmos m=1 w=1.62u l=130.00n ng=1 nrd=0 nrs=0 +.ENDS +.SUBCKT RSC_IHPSG13_MX2X2 A0 A1 S Z VDD VSS +MP6 Z net010 VDD VDD sg13_lv_pmos m=1 w=1.62u l=130.00n ng=1 nrd=0 ++ nrs=0 +MP4 SN S VDD VDD sg13_lv_pmos m=1 w=645.000n l=130.00n ng=1 nrd=0 nrs=0 +MP3 net010 SN net12 VDD sg13_lv_pmos m=1 w=985.000n l=130.00n ng=1 nrd=0 ++ nrs=0 +MP2 net12 A1 VDD VDD sg13_lv_pmos m=1 w=985.000n l=130.00n ng=1 nrd=0 ++ nrs=0 +MP1 net010 S net17 VDD sg13_lv_pmos m=1 w=985.000n l=130.00n ng=1 nrd=0 ++ nrs=0 +MP0 net17 A0 VDD VDD sg13_lv_pmos m=1 w=985.000n l=130.00n ng=1 nrd=0 ++ nrs=0 +MN6 Z net010 VSS VSS sg13_lv_nmos m=1 w=705.000n l=130.00n ng=1 nrd=0 ++ nrs=0 +MN5 SN S VSS VSS sg13_lv_nmos m=1 w=560.00n l=130.00n ng=1 nrd=0 nrs=0 +MN3 net13 A1 VSS VSS sg13_lv_nmos m=1 w=560.00n l=130.00n ng=1 nrd=0 ++ nrs=0 +MN2 net010 S net13 VSS sg13_lv_nmos m=1 w=560.00n l=130.00n ng=1 nrd=0 ++ nrs=0 +MN1 net15 A0 VSS VSS sg13_lv_nmos m=1 w=560.00n l=130.00n ng=1 nrd=0 ++ nrs=0 +MN0 net010 SN net15 VSS sg13_lv_nmos m=1 w=560.00n l=130.00n ng=1 nrd=0 ++ nrs=0 +.ENDS +.SUBCKT RSC_IHPSG13_AND2X2 A B Z VDD VSS +MN3 Z net6 VSS VSS sg13_lv_nmos m=1 w=980.00n l=130.00n ng=1 nrd=0 ++ nrs=0 +MN4 net9 B VSS VSS sg13_lv_nmos m=1 w=500.0n l=130.00n ng=1 nrd=0 nrs=0 +MN6 net6 A net9 VSS sg13_lv_nmos m=1 w=500.0n l=130.00n ng=1 nrd=0 nrs=0 +MP2 Z net6 VDD VDD sg13_lv_pmos m=1 w=1.62u l=130.00n ng=1 nrd=0 nrs=0 +MP0 net6 B VDD VDD sg13_lv_pmos m=1 w=860.00n l=130.00n ng=1 nrd=0 ++ nrs=0 +MP1 net6 A VDD VDD sg13_lv_pmos m=1 w=860.00n l=130.00n ng=1 nrd=0 ++ nrs=0 +.ENDS +.SUBCKT RSC_IHPSG13_TIEL Z VDD VSS +MN0 Z net2 VSS VSS sg13_lv_nmos m=1 w=480.00n l=130.00n ng=1 nrd=0 ++ nrs=0 +MP0 net2 net2 VDD VDD sg13_lv_pmos m=1 w=480.00n l=130.00n ng=1 nrd=0 ++ nrs=0 +.ENDS +.SUBCKT RSC_IHPSG13_XOR2X2 A B Z VDD VSS +MP8 net012 B net7 VDD sg13_lv_pmos m=1 w=825.000n l=130.00n ng=1 nrd=0 ++ nrs=0 +MP7 net011 net3 net012 VDD sg13_lv_pmos m=1 w=825.000n l=130.00n ng=1 ++ nrd=0 nrs=0 +MP6 Z net012 VDD VDD sg13_lv_pmos m=1 w=1.535u l=130.00n ng=1 nrd=0 ++ nrs=0 +MP2 net7 A VDD VDD sg13_lv_pmos m=1 w=825.000n l=130.00n ng=1 nrd=0 ++ nrs=0 +MP4 net011 net7 VDD VDD sg13_lv_pmos m=1 w=825.000n l=130.00n ng=1 ++ nrd=0 nrs=0 +MP5 net3 B VDD VDD sg13_lv_pmos m=1 w=580.00n l=130.00n ng=1 nrd=0 ++ nrs=0 +MN7 net012 B net011 VSS sg13_lv_nmos m=1 w=555.000n l=130.00n ng=1 nrd=0 ++ nrs=0 +MN6 net7 net3 net012 VSS sg13_lv_nmos m=1 w=555.000n l=130.00n ng=1 nrd=0 ++ nrs=0 +MN5 Z net012 VSS VSS sg13_lv_nmos m=1 w=775.000n l=130.00n ng=1 nrd=0 ++ nrs=0 +MN2 net7 A VSS VSS sg13_lv_nmos m=1 w=555.000n l=130.00n ng=1 nrd=0 ++ nrs=0 +MN4 net3 B VSS VSS sg13_lv_nmos m=1 w=480.00n l=130.00n ng=1 nrd=0 ++ nrs=0 +MN3 net011 net7 VSS VSS sg13_lv_nmos m=1 w=555.000n l=130.00n ng=1 ++ nrd=0 nrs=0 +.ENDS +.SUBCKT RSC_IHPSG13_OA12X1 A B C Z VDD VSS +MN2 net7 C VSS VSS sg13_lv_nmos m=1 w=980.00n l=130.00n ng=1 nrd=0 ++ nrs=0 +MN3 Z net17 VSS VSS sg13_lv_nmos m=1 w=500.0n l=130.00n ng=1 nrd=0 ++ nrs=0 +MN1 net17 B net7 VSS sg13_lv_nmos m=1 w=980.00n l=130.00n ng=1 nrd=0 nrs=0 +MN0 net17 A net7 VSS sg13_lv_nmos m=1 w=980.00n l=130.00n ng=1 nrd=0 nrs=0 +MP0 net24 A VDD VDD sg13_lv_pmos m=1 w=1.62u l=130.00n ng=1 nrd=0 nrs=0 +MP3 Z net17 VDD VDD sg13_lv_pmos m=1 w=905.000n l=130.00n ng=1 nrd=0 ++ nrs=0 +MP1 net17 B net24 VDD sg13_lv_pmos m=1 w=1.62u l=130.00n ng=1 nrd=0 nrs=0 +MP2 net17 C VDD VDD sg13_lv_pmos m=1 w=905.000n l=130.00n ng=1 nrd=0 ++ nrs=0 +.ENDS +.SUBCKT RM_IHPSG13_256x32_c2_1P_CTRL ACLK_N BIST_CK_I BIST_CS_I BIST_EN BIST_RE_I ++ BIST_WE_I B_TIEL_O CK_I CS_I DCLK ECLK PULSE_H PULSE_L PULSE_O RCLK RE_I ++ ROW_CS WCLK WE_I VDD VSS +XI17 ck_regs we col_we VDD VSS / RSC_IHPSG13_DFNQX2 +XI16 ck_regs re col_re VDD VSS / RSC_IHPSG13_DFNQX2 +XI18 ck_regs cs net7 VDD VSS / RSC_IHPSG13_DFNQX2 +XI71 ACLK_N net012 PULSE_O VDD VSS / RSC_IHPSG13_DFNQX2 +XI77 col_we net9 net016 VDD VSS / RSC_IHPSG13_CNAND2X2 +XI76 col_re net9 net018 VDD VSS / RSC_IHPSG13_CNAND2X2 +XI15 ck_dly WEorREandCS aclk VDD VSS / RSC_IHPSG13_CGATEPX4 +XI14 ck WEandCS DCLK VDD VSS / RSC_IHPSG13_CGATEPX4 +XI60 net7 ROW_CS VDD VSS / RSC_IHPSG13_CBUFX8 +XI73 PULSE_O net012 VDD VSS / RSC_IHPSG13_CINVX2 +XI8 net9 net8 VDD VSS / RSC_IHPSG13_CINVX2 +XI64 ck ck_dly VDD VSS / RSC_IHPSG13_CDLYX2 +XI86 CS_I BIST_CS_I BIST_EN cs VDD VSS / RSC_IHPSG13_MX2X2 +XI87 CK_I BIST_CK_I BIST_EN ck VDD VSS / RSC_IHPSG13_MX2X2 +XI85 WE_I BIST_WE_I BIST_EN we VDD VSS / RSC_IHPSG13_MX2X2 +XI84 RE_I BIST_RE_I BIST_EN re VDD VSS / RSC_IHPSG13_MX2X2 +XI22 we cs WEandCS VDD VSS / RSC_IHPSG13_AND2X2 +XBM_TIEL B_TIEL_O VDD VSS / RSC_IHPSG13_TIEL +XI48 ck_dly ck_regs VDD VSS / RSC_IHPSG13_CINVX4 +XI81 net016 WCLK VDD VSS / RSC_IHPSG13_CINVX4 +XI80 net018 RCLK VDD VSS / RSC_IHPSG13_CINVX4 +XI78 net8 net020 VDD VSS / RSC_IHPSG13_CINVX4 +XI6 PULSE_L PULSE_H net9 VDD VSS / RSC_IHPSG13_XOR2X2 +XI79 net020 ECLK VDD VSS / RSC_IHPSG13_CINVX8 +XI63 aclk ACLK_N VDD VSS / RSC_IHPSG13_CINVX8 +XI21 re we cs WEorREandCS VDD VSS / RSC_IHPSG13_OA12X1 +.ENDS +.SUBCKT RM_IHPSG13_256x32_c2_1P_COLDEC2 ACLK_N ADDR<1> ADDR<0> ADDR_COL<1> ADDR_COL<0> ++ ADDR_DEC<7> ADDR_DEC<6> ADDR_DEC<5> ADDR_DEC<4> ADDR_DEC<3> ADDR_DEC<2> ++ ADDR_DEC<1> ADDR_DEC<0> BIST_ADDR<1> BIST_ADDR<0> BIST_EN_I VDD VSS +XI14<5> VDD VSS / RSC_IHPSG13_FILLCAP4 +XI14<4> VDD VSS / RSC_IHPSG13_FILLCAP4 +XI14<3> VDD VSS / RSC_IHPSG13_FILLCAP4 +XI14<2> VDD VSS / RSC_IHPSG13_FILLCAP4 +XI14<1> VDD VSS / RSC_IHPSG13_FILLCAP4 +XDFF<1> BIST_EN_I BIST_ADDR<1> ACLK_N ADDR<1> padr_int<1> net6<0> VDD ++ VSS / RSC_IHPSG13_DFNQMX2IX1 +XDFF<0> BIST_EN_I BIST_ADDR<0> ACLK_N ADDR<0> padr_int<0> net6<1> VDD ++ VSS / RSC_IHPSG13_DFNQMX2IX1 +XI1<3> PADR<1> PADR<0> addr_n<3> VDD VSS / RSC_IHPSG13_NAND2X2 +XI1<2> PADR<1> NADR<0> addr_n<2> VDD VSS / RSC_IHPSG13_NAND2X2 +XI1<1> NADR<1> PADR<0> addr_n<1> VDD VSS / RSC_IHPSG13_NAND2X2 +XI1<0> NADR<1> NADR<0> addr_n<0> VDD VSS / RSC_IHPSG13_NAND2X2 +XI16<37> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI16<36> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI16<35> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI16<34> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI16<33> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI16<32> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI16<31> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI16<30> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI16<29> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI16<28> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI16<27> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI16<26> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI16<25> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI16<24> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI16<23> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI16<22> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI16<21> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI16<20> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI16<19> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI16<18> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI16<17> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI16<16> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI16<15> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI16<14> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI16<13> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI16<12> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI16<11> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI16<10> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI16<9> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI16<8> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI16<7> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI16<6> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI16<5> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI16<4> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI16<3> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI16<2> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI16<1> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI3<1> padr_int<1> NADR<1> VDD VSS / RSC_IHPSG13_INVX2 +XI3<0> padr_int<0> NADR<0> VDD VSS / RSC_IHPSG13_INVX2 +XI13<1> NADR<1> PADR<1> VDD VSS / RSC_IHPSG13_INVX2 +XI13<0> NADR<0> PADR<0> VDD VSS / RSC_IHPSG13_INVX2 +XI2<3> addr_n<3> ADDR_DEC<3> VDD VSS / RSC_IHPSG13_INVX2 +XI2<2> addr_n<2> ADDR_DEC<2> VDD VSS / RSC_IHPSG13_INVX2 +XI2<1> addr_n<1> ADDR_DEC<1> VDD VSS / RSC_IHPSG13_INVX2 +XI2<0> addr_n<0> ADDR_DEC<0> VDD VSS / RSC_IHPSG13_INVX2 +XI15<1> ADDR_COL<1> VDD VSS / RSC_IHPSG13_TIEL +XI15<0> ADDR_COL<0> VDD VSS / RSC_IHPSG13_TIEL +XI17<3> ADDR_DEC<7> VDD VSS / RSC_IHPSG13_TIEL +XI17<2> ADDR_DEC<6> VDD VSS / RSC_IHPSG13_TIEL +XI17<1> ADDR_DEC<5> VDD VSS / RSC_IHPSG13_TIEL +XI17<0> ADDR_DEC<4> VDD VSS / RSC_IHPSG13_TIEL +.ENDS +.SUBCKT RSC_IHPSG13_NOR2X2 A B Z VDD VSS +MP1 Z B net9 VDD sg13_lv_pmos m=1 w=1.62u l=130.00n ng=1 nrd=0 nrs=0 +MP0 net9 A VDD VDD sg13_lv_pmos m=1 w=1.62u l=130.00n ng=1 nrd=0 nrs=0 +MN0 Z B VSS VSS sg13_lv_nmos m=1 w=980.00n l=130.00n ng=1 nrd=0 nrs=0 +MN1 Z A VSS VSS sg13_lv_nmos m=1 w=980.00n l=130.00n ng=1 nrd=0 nrs=0 +.ENDS +.SUBCKT RSC_IHPSG13_CINVX4_WN A Z VDD VSS +MN0 Z A VSS VSS sg13_lv_nmos m=1 w=705.000n l=130.00n ng=1 nrd=0 nrs=0 +MP0 Z A VDD VDD sg13_lv_pmos m=1 w=3.24u l=130.00n ng=2 nrd=0 nrs=0 +.ENDS +.SUBCKT RM_IHPSG13_256x32_c2_1P_BLDRV BLC BLC_SEL BLT BLT_SEL PRE_N SEL_P WR_ONE WR_ZERO ++ VDD VSS +XCDEC SEL_P WR_ZERO BLC_PMOS_DRIVE VDD VSS / RSC_IHPSG13_NAND2X2 +XTDEC SEL_P WR_ONE BLT_PMOS_DRIVE VDD VSS / RSC_IHPSG13_NAND2X2 +MTWN BLT BLT_NMOS_DRIVE VSS VSS sg13_lv_nmos m=1 w=4.82u l=130.00n ++ ng=2 nrd=0 nrs=0 +MCWN BLC BLC_NMOS_DRIVE VSS VSS sg13_lv_nmos m=1 w=4.82u l=130.00n ++ ng=2 nrd=0 nrs=0 +MCWP BLC BLC_PMOS_DRIVE VDD VDD sg13_lv_pmos m=1 w=1.5u l=130.00n ng=1 ++ nrd=0 nrs=0 +MTWP BLT BLT_PMOS_DRIVE VDD VDD sg13_lv_pmos m=1 w=1.5u l=130.00n ng=1 ++ nrd=0 nrs=0 +MTSP BLT_SEL SEL_N BLT VDD sg13_lv_pmos m=1 w=1.5u l=130.00n ng=1 nrd=0 ++ nrs=0 +MTPR BLT PRE_N VDD VDD sg13_lv_pmos m=1 w=3.000u l=130.00n ng=2 nrd=0 ++ nrs=0 +MCSP BLC_SEL SEL_N BLC VDD sg13_lv_pmos m=1 w=1.5u l=130.00n ng=1 nrd=0 ++ nrs=0 +MCPR BLC PRE_N VDD VDD sg13_lv_pmos m=1 w=3.000u l=130.00n ng=2 nrd=0 ++ nrs=0 +XI86 SEL_P SEL_N VDD VSS / RSC_IHPSG13_INVX2 +XTINV BLC_PMOS_DRIVE BLT_NMOS_DRIVE VDD VSS / RSC_IHPSG13_INVX2 +XCINV BLT_PMOS_DRIVE BLC_NMOS_DRIVE VDD VSS / RSC_IHPSG13_INVX2 +.ENDS +.SUBCKT RSC_IHPSG13_TIEH Z VDD VSS +MN0 net2 net2 VSS VSS sg13_lv_nmos m=1 w=480.00n l=130.00n ng=1 nrd=0 ++ nrs=0 +MP0 Z net2 VDD VDD sg13_lv_pmos m=1 w=480.00n l=130.00n ng=1 nrd=0 ++ nrs=0 +.ENDS +.SUBCKT RSC_IHPSG13_MET3RES A B +R0 B A lvsres w=2.6e-07 l=6e-07 +.ENDS +.SUBCKT RSC_IHPSG13_DFPQD_MSAFFX2 CP DN DP QN QP VDD VSS +MN12 SN RN DIFFP VSS sg13_lv_nmos m=1 w=2.4u l=200.0n ng=2 nrd=0 nrs=0 +MN13 TAIL CP VSS VSS sg13_lv_nmos m=1 w=2.4u l=130.00n ng=2 nrd=0 nrs=0 +MN9 DIFFP DP TAIL VSS sg13_lv_nmos m=1 w=2.4u l=200.0n ng=2 nrd=0 nrs=0 +MN10 DIFFN DN TAIL VSS sg13_lv_nmos m=1 w=2.4u l=200.0n ng=2 nrd=0 nrs=0 +MN11 RN SN DIFFN VSS sg13_lv_nmos m=1 w=2.4u l=200.0n ng=2 nrd=0 nrs=0 +MN19 net33 SN VSS VSS sg13_lv_nmos m=1 w=980.00n l=130.00n ng=1 nrd=0 ++ nrs=0 +MN20 QN QP net37 VSS sg13_lv_nmos m=1 w=980.00n l=130.00n ng=1 nrd=0 nrs=0 +MN18 net37 RN VSS VSS sg13_lv_nmos m=1 w=980.00n l=130.00n ng=1 nrd=0 ++ nrs=0 +MN17 QP QN net33 VSS sg13_lv_nmos m=1 w=980.00n l=130.00n ng=1 nrd=0 nrs=0 +MP15 SN RN VDD VDD sg13_lv_pmos m=1 w=800.0n l=130.00n ng=1 nrd=0 nrs=0 +MP16 RN CP VDD VDD sg13_lv_pmos m=1 w=800.0n l=130.00n ng=1 nrd=0 nrs=0 +MP14 DIFFP CP VDD VDD sg13_lv_pmos m=1 w=800.0n l=130.00n ng=1 nrd=0 ++ nrs=0 +MP12 RN SN VDD VDD sg13_lv_pmos m=1 w=800.0n l=130.00n ng=1 nrd=0 nrs=0 +MP13 DIFFN CP VDD VDD sg13_lv_pmos m=1 w=800.0n l=130.00n ng=1 nrd=0 ++ nrs=0 +MP11 SN CP VDD VDD sg13_lv_pmos m=1 w=800.0n l=130.00n ng=1 nrd=0 nrs=0 +MP19 QN QP VDD VDD sg13_lv_pmos m=1 w=900.0n l=130.00n ng=1 nrd=0 nrs=0 +MP20 QP SN VDD VDD sg13_lv_pmos m=1 w=1.8u l=130.00n ng=2 nrd=0 nrs=0 +MP18 QN RN VDD VDD sg13_lv_pmos m=1 w=1.8u l=130.00n ng=2 nrd=0 nrs=0 +MP17 QP QN VDD VDD sg13_lv_pmos m=1 w=900.0n l=130.00n ng=1 nrd=0 nrs=0 +.ENDS +.SUBCKT RSC_IHPSG13_CBUFX2 A Z VDD VSS +MN1 Z net4 VSS VSS sg13_lv_nmos m=1 w=705.000n l=130.00n ng=1 nrd=0 ++ nrs=0 +MN0 net4 A VSS VSS sg13_lv_nmos m=1 w=540.00n l=130.00n ng=1 nrd=0 ++ nrs=0 +MP1 Z net4 VDD VDD sg13_lv_pmos m=1 w=1.62u l=130.00n ng=1 nrd=0 nrs=0 +MP0 net4 A VDD VDD sg13_lv_pmos m=1 w=1.1u l=130.00n ng=1 nrd=0 nrs=0 +.ENDS +.SUBCKT RSC_IHPSG13_INVX4 A Z VDD VSS +MN0 Z A VSS VSS sg13_lv_nmos m=1 w=1.96u l=130.00n ng=2 nrd=0 nrs=0 +MP0 Z A VDD VDD sg13_lv_pmos m=1 w=3.24u l=130.00n ng=2 nrd=0 nrs=0 +.ENDS +.SUBCKT RM_IHPSG13_256x32_c2_1P_COLCTRL2 A_ADDR_DEC<3> A_ADDR_DEC<2> A_ADDR_DEC<1> ++ A_ADDR_DEC<0> A_BIST_BM_I A_BIST_DW_I A_BIST_EN_I A_BLC<3> A_BLC<2> A_BLC<1> ++ A_BLC<0> A_BLT<3> A_BLT<2> A_BLT<1> A_BLT<0> A_BM_I A_DCLK_B_L A_DCLK_B_R ++ A_DCLK_L A_DCLK_R A_DR_O A_DW_I A_RCLK_B_L A_RCLK_B_R A_RCLK_L A_RCLK_R ++ A_TIEH_O A_WCLK_B_L A_WCLK_B_R A_WCLK_L A_WCLK_R VDD VSS +XA_DREG A_BIST_EN_I A_BIST_DW_I A_DCLK_B_L A_DW_I A_DI_R net22 VDD VSS ++ / RSC_IHPSG13_DFNQMX2IX1 +XA_BREG A_BIST_EN_I A_BIST_BM_I A_DCLK_B_L A_BM_I A_BM_R net23 VDD VSS ++ / RSC_IHPSG13_DFNQMX2IX1 +XA_CAPS<5> VDD VSS / RSC_IHPSG13_FILLCAP4 +XA_CAPS<4> VDD VSS / RSC_IHPSG13_FILLCAP4 +XA_CAPS<3> VDD VSS / RSC_IHPSG13_FILLCAP4 +XA_CAPS<2> VDD VSS / RSC_IHPSG13_FILLCAP4 +XA_CAPS<1> VDD VSS / RSC_IHPSG13_FILLCAP4 +XA_I80 A_WCLK_B_R A_RCLK_B_R net21 VDD VSS / RSC_IHPSG13_AND2X2 +XA_I75 A_DI_R A_DO_WRITE_P A_WR_ONE VDD VSS / RSC_IHPSG13_AND2X2 +XA_I76 A_DI_N A_DO_WRITE_P A_WR_ZERO VDD VSS / RSC_IHPSG13_AND2X2 +XA_I44 A_WCLK_B_R A_BM_N A_DO_WRITE_P VDD VSS / RSC_IHPSG13_NOR2X2 +XA_I81 net21 A_PRE_N VDD VSS / RSC_IHPSG13_CINVX4_WN +XA_BLTMUX<3> A_BLC<3> A_BLC_SEL A_BLT<3> A_BLT_SEL A_PRE_N A_ADDR_DEC<3> ++ A_WR_ONE A_WR_ZERO VDD VSS / RM_IHPSG13_256x32_c2_1P_BLDRV +XA_BLTMUX<2> A_BLC<2> A_BLC_SEL A_BLT<2> A_BLT_SEL A_PRE_N A_ADDR_DEC<2> ++ A_WR_ONE A_WR_ZERO VDD VSS / RM_IHPSG13_256x32_c2_1P_BLDRV +XA_BLTMUX<1> A_BLC<1> A_BLC_SEL A_BLT<1> A_BLT_SEL A_PRE_N A_ADDR_DEC<1> ++ A_WR_ONE A_WR_ZERO VDD VSS / RM_IHPSG13_256x32_c2_1P_BLDRV +XA_BLTMUX<0> A_BLC<0> A_BLC_SEL A_BLT<0> A_BLT_SEL A_PRE_N A_ADDR_DEC<0> ++ A_WR_ONE A_WR_ZERO VDD VSS / RM_IHPSG13_256x32_c2_1P_BLDRV +XA_BM_TIEH A_TIEH_O VDD VSS / RSC_IHPSG13_TIEH +XA_I89 A_DCLK_B_L A_DCLK_B_R / RSC_IHPSG13_MET3RES +XA_I88 A_DCLK_L A_DCLK_R / RSC_IHPSG13_MET3RES +XA_I87 A_WCLK_L A_WCLK_R / RSC_IHPSG13_MET3RES +XA_I91 A_RCLK_B_R A_RCLK_B_L / RSC_IHPSG13_MET3RES +XA_R2 A_RCLK_R A_RCLK_L / RSC_IHPSG13_MET3RES +XA_I90 A_WCLK_B_R A_WCLK_B_L / RSC_IHPSG13_MET3RES +XA_ISENSE A_SAE A_BLC_SEL A_BLT_SEL net19 net20 VDD VSS / ++ RSC_IHPSG13_DFPQD_MSAFFX2 +XA_I78 A_RCLK_B_R A_SAE VDD VSS / RSC_IHPSG13_CBUFX2 +XA_I83 A_BM_R A_BM_N VDD VSS / RSC_IHPSG13_INVX2 +XA_I49 A_DI_R A_DI_N VDD VSS / RSC_IHPSG13_INVX2 +XA_I51 net19 A_DR_O VDD VSS / RSC_IHPSG13_INVX4 +XA_I69 A_DCLK_L A_DCLK_B_L VDD VSS / RSC_IHPSG13_CINVX2 +XA_I50 A_WCLK_L A_WCLK_B_R VDD VSS / RSC_IHPSG13_CINVX2 +XA_EBUF A_RCLK_R A_RCLK_B_R VDD VSS / RSC_IHPSG13_CINVX2 +.ENDS +.SUBCKT RM_IHPSG13_256x32_c2_1P_COLDRV13_FILL4 VDD VSS +XI0<9> VDD VSS / RSC_IHPSG13_FILLCAP4 +XI0<8> VDD VSS / RSC_IHPSG13_FILLCAP4 +XI0<7> VDD VSS / RSC_IHPSG13_FILLCAP4 +XI0<6> VDD VSS / RSC_IHPSG13_FILLCAP4 +XI0<5> VDD VSS / RSC_IHPSG13_FILLCAP4 +XI0<4> VDD VSS / RSC_IHPSG13_FILLCAP4 +XI0<3> VDD VSS / RSC_IHPSG13_FILLCAP4 +XI0<2> VDD VSS / RSC_IHPSG13_FILLCAP4 +XI0<1> VDD VSS / RSC_IHPSG13_FILLCAP4 +.ENDS +.SUBCKT RM_IHPSG13_256x32_c2_1P_COLDRV13_FILL4C2 VDD VSS +XI0<2> VDD VSS / RSC_IHPSG13_FILLCAP4 +XI0<1> VDD VSS / RSC_IHPSG13_FILLCAP4 +.ENDS + + +.SUBCKT RM_IHPSG13_256x32_c2_1P_COLDEC4 ACLK_N ADDR<3> ADDR<2> ADDR<1> ADDR<0> ++ ADDR_COL<1> ADDR_COL<0> ADDR_DEC<7> ADDR_DEC<6> ADDR_DEC<5> ADDR_DEC<4> ++ ADDR_DEC<3> ADDR_DEC<2> ADDR_DEC<1> ADDR_DEC<0> BIST_ADDR<3> BIST_ADDR<2> ++ BIST_ADDR<1> BIST_ADDR<0> BIST_EN_I VDD VSS +XI15 ADDR_COL<1> VDD VSS / RSC_IHPSG13_TIEL +XI14 addr_int ADDR_COL<0> VDD VSS / RSC_IHPSG13_CBUFX2 +XDFF<3> BIST_EN_I BIST_ADDR<3> ACLK_N ADDR<3> addr_int net7<0> VDD VSS ++ / RSC_IHPSG13_DFNQMX2IX1 +XDFF<2> BIST_EN_I BIST_ADDR<2> ACLK_N ADDR<2> padr_int<2> net7<1> VDD ++ VSS / RSC_IHPSG13_DFNQMX2IX1 +XDFF<1> BIST_EN_I BIST_ADDR<1> ACLK_N ADDR<1> padr_int<1> net7<2> VDD ++ VSS / RSC_IHPSG13_DFNQMX2IX1 +XDFF<0> BIST_EN_I BIST_ADDR<0> ACLK_N ADDR<0> padr_int<0> net7<3> VDD ++ VSS / RSC_IHPSG13_DFNQMX2IX1 +XI1<7> PADR<0> PADR<1> PADR<2> addr_n<7> VDD VSS / RSC_IHPSG13_NAND3X2 +XI1<6> NADR<0> PADR<1> PADR<2> addr_n<6> VDD VSS / RSC_IHPSG13_NAND3X2 +XI1<5> PADR<0> NADR<1> PADR<2> addr_n<5> VDD VSS / RSC_IHPSG13_NAND3X2 +XI1<4> NADR<0> NADR<1> PADR<2> addr_n<4> VDD VSS / RSC_IHPSG13_NAND3X2 +XI1<3> PADR<0> PADR<1> NADR<2> addr_n<3> VDD VSS / RSC_IHPSG13_NAND3X2 +XI1<2> NADR<0> PADR<1> NADR<2> addr_n<2> VDD VSS / RSC_IHPSG13_NAND3X2 +XI1<1> PADR<0> NADR<1> NADR<2> addr_n<1> VDD VSS / RSC_IHPSG13_NAND3X2 +XI1<0> NADR<0> NADR<1> NADR<2> addr_n<0> VDD VSS / RSC_IHPSG13_NAND3X2 +XI13<2> NADR<2> PADR<2> VDD VSS / RSC_IHPSG13_INVX2 +XI13<1> NADR<1> PADR<1> VDD VSS / RSC_IHPSG13_INVX2 +XI13<0> NADR<0> PADR<0> VDD VSS / RSC_IHPSG13_INVX2 +XI3<2> padr_int<2> NADR<2> VDD VSS / RSC_IHPSG13_INVX2 +XI3<1> padr_int<1> NADR<1> VDD VSS / RSC_IHPSG13_INVX2 +XI3<0> padr_int<0> NADR<0> VDD VSS / RSC_IHPSG13_INVX2 +XI2<7> addr_n<7> ADDR_DEC<7> VDD VSS / RSC_IHPSG13_INVX2 +XI2<6> addr_n<6> ADDR_DEC<6> VDD VSS / RSC_IHPSG13_INVX2 +XI2<5> addr_n<5> ADDR_DEC<5> VDD VSS / RSC_IHPSG13_INVX2 +XI2<4> addr_n<4> ADDR_DEC<4> VDD VSS / RSC_IHPSG13_INVX2 +XI2<3> addr_n<3> ADDR_DEC<3> VDD VSS / RSC_IHPSG13_INVX2 +XI2<2> addr_n<2> ADDR_DEC<2> VDD VSS / RSC_IHPSG13_INVX2 +XI2<1> addr_n<1> ADDR_DEC<1> VDD VSS / RSC_IHPSG13_INVX2 +XI2<0> addr_n<0> ADDR_DEC<0> VDD VSS / RSC_IHPSG13_INVX2 +XI16<3> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI16<2> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI16<1> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI17<2> VDD VSS / RSC_IHPSG13_FILLCAP4 +XI17<1> VDD VSS / RSC_IHPSG13_FILLCAP4 +.ENDS +.SUBCKT RSC_IHPSG13_AND2X4 A B Z VDD VSS +MN3 Z net6 VSS VSS sg13_lv_nmos m=1 w=1.96u l=130.00n ng=2 nrd=0 nrs=0 +MN4 net9 B VSS VSS sg13_lv_nmos m=1 w=500.0n l=130.00n ng=1 nrd=0 nrs=0 +MN6 net6 A net9 VSS sg13_lv_nmos m=1 w=500.0n l=130.00n ng=1 nrd=0 nrs=0 +MP2 Z net6 VDD VDD sg13_lv_pmos m=1 w=3.24u l=130.00n ng=2 nrd=0 nrs=0 +MP0 net6 B VDD VDD sg13_lv_pmos m=1 w=860.00n l=130.00n ng=1 nrd=0 ++ nrs=0 +MP1 net6 A VDD VDD sg13_lv_pmos m=1 w=860.00n l=130.00n ng=1 nrd=0 ++ nrs=0 +.ENDS +.SUBCKT RM_IHPSG13_256x32_c2_1P_COLCTRL4 A_ADDR_COL A_ADDR_DEC<7> A_ADDR_DEC<6> ++ A_ADDR_DEC<5> A_ADDR_DEC<4> A_ADDR_DEC<3> A_ADDR_DEC<2> A_ADDR_DEC<1> ++ A_ADDR_DEC<0> A_BIST_BM_I A_BIST_DW_I A_BIST_EN_I A_BLC<15> A_BLC<14> ++ A_BLC<13> A_BLC<12> A_BLC<11> A_BLC<10> A_BLC<9> A_BLC<8> A_BLC<7> A_BLC<6> ++ A_BLC<5> A_BLC<4> A_BLC<3> A_BLC<2> A_BLC<1> A_BLC<0> A_BLT<15> A_BLT<14> ++ A_BLT<13> A_BLT<12> A_BLT<11> A_BLT<10> A_BLT<9> A_BLT<8> A_BLT<7> A_BLT<6> ++ A_BLT<5> A_BLT<4> A_BLT<3> A_BLT<2> A_BLT<1> A_BLT<0> A_BM_I A_DCLK_B_L ++ A_DCLK_B_R A_DCLK_L A_DCLK_R A_DR_O A_DW_I A_RCLK_B_L A_RCLK_B_R A_RCLK_L ++ A_RCLK_R A_TIEH_O A_WCLK_B_L A_WCLK_B_R A_WCLK_L A_WCLK_R VDD VSS +XA_I80 A_WCLK_B_L A_RCLK_B_L net21 VDD VSS / RSC_IHPSG13_AND2X2 +XA_I76 A_DO_WRITE_P A_DI_N A_WR_ZERO VDD VSS / RSC_IHPSG13_AND2X4 +XA_I75 A_DI_R A_DO_WRITE_P A_WR_ONE VDD VSS / RSC_IHPSG13_AND2X4 +XA_CAPS<8> VDD VSS / RSC_IHPSG13_FILLCAP4 +XA_CAPS<7> VDD VSS / RSC_IHPSG13_FILLCAP4 +XA_CAPS<6> VDD VSS / RSC_IHPSG13_FILLCAP4 +XA_CAPS<5> VDD VSS / RSC_IHPSG13_FILLCAP4 +XA_CAPS<4> VDD VSS / RSC_IHPSG13_FILLCAP4 +XA_CAPS<3> VDD VSS / RSC_IHPSG13_FILLCAP4 +XA_CAPS<2> VDD VSS / RSC_IHPSG13_FILLCAP4 +XA_CAPS<1> VDD VSS / RSC_IHPSG13_FILLCAP4 +XA_I69 A_DCLK_L A_DCLK_B_L VDD VSS / RSC_IHPSG13_CINVX4 +XA_I50 A_WCLK_L A_WCLK_B_L VDD VSS / RSC_IHPSG13_CINVX4 +XA_EBUF A_RCLK_L A_RCLK_B_L VDD VSS / RSC_IHPSG13_CINVX4 +XA_INV<1> A_N0 A_P0 VDD VSS / RSC_IHPSG13_CINVX4 +XA_INV<0> A_ADDR_COL A_N0 VDD VSS / RSC_IHPSG13_CINVX4 +XA_I81<1> net21 A_PRE_N VDD VSS / RSC_IHPSG13_CINVX4_WN +XA_I81<0> net21 A_PRE_N VDD VSS / RSC_IHPSG13_CINVX4_WN +XA_BLTMUX<15> A_BLC<15> A_BLC_SEL A_BLT<15> A_BLT_SEL A_PRE_N A_SEL_P<15> ++ A_WR_ONE A_WR_ZERO VDD VSS / RM_IHPSG13_256x32_c2_1P_BLDRV +XA_BLTMUX<14> A_BLC<14> A_BLC_SEL A_BLT<14> A_BLT_SEL A_PRE_N A_SEL_P<14> ++ A_WR_ONE A_WR_ZERO VDD VSS / RM_IHPSG13_256x32_c2_1P_BLDRV +XA_BLTMUX<13> A_BLC<13> A_BLC_SEL A_BLT<13> A_BLT_SEL A_PRE_N A_SEL_P<13> ++ A_WR_ONE A_WR_ZERO VDD VSS / RM_IHPSG13_256x32_c2_1P_BLDRV +XA_BLTMUX<12> A_BLC<12> A_BLC_SEL A_BLT<12> A_BLT_SEL A_PRE_N A_SEL_P<12> ++ A_WR_ONE A_WR_ZERO VDD VSS / RM_IHPSG13_256x32_c2_1P_BLDRV +XA_BLTMUX<11> A_BLC<11> A_BLC_SEL A_BLT<11> A_BLT_SEL A_PRE_N A_SEL_P<11> ++ A_WR_ONE A_WR_ZERO VDD VSS / RM_IHPSG13_256x32_c2_1P_BLDRV +XA_BLTMUX<10> A_BLC<10> A_BLC_SEL A_BLT<10> A_BLT_SEL A_PRE_N A_SEL_P<10> ++ A_WR_ONE A_WR_ZERO VDD VSS / RM_IHPSG13_256x32_c2_1P_BLDRV +XA_BLTMUX<9> A_BLC<9> A_BLC_SEL A_BLT<9> A_BLT_SEL A_PRE_N A_SEL_P<9> A_WR_ONE ++ A_WR_ZERO VDD VSS / RM_IHPSG13_256x32_c2_1P_BLDRV +XA_BLTMUX<8> A_BLC<8> A_BLC_SEL A_BLT<8> A_BLT_SEL A_PRE_N A_SEL_P<8> A_WR_ONE ++ A_WR_ZERO VDD VSS / RM_IHPSG13_256x32_c2_1P_BLDRV +XA_BLTMUX<7> A_BLC<7> A_BLC_SEL A_BLT<7> A_BLT_SEL A_PRE_N A_SEL_P<7> A_WR_ONE ++ A_WR_ZERO VDD VSS / RM_IHPSG13_256x32_c2_1P_BLDRV +XA_BLTMUX<6> A_BLC<6> A_BLC_SEL A_BLT<6> A_BLT_SEL A_PRE_N A_SEL_P<6> A_WR_ONE ++ A_WR_ZERO VDD VSS / RM_IHPSG13_256x32_c2_1P_BLDRV +XA_BLTMUX<5> A_BLC<5> A_BLC_SEL A_BLT<5> A_BLT_SEL A_PRE_N A_SEL_P<5> A_WR_ONE ++ A_WR_ZERO VDD VSS / RM_IHPSG13_256x32_c2_1P_BLDRV +XA_BLTMUX<4> A_BLC<4> A_BLC_SEL A_BLT<4> A_BLT_SEL A_PRE_N A_SEL_P<4> A_WR_ONE ++ A_WR_ZERO VDD VSS / RM_IHPSG13_256x32_c2_1P_BLDRV +XA_BLTMUX<3> A_BLC<3> A_BLC_SEL A_BLT<3> A_BLT_SEL A_PRE_N A_SEL_P<3> A_WR_ONE ++ A_WR_ZERO VDD VSS / RM_IHPSG13_256x32_c2_1P_BLDRV +XA_BLTMUX<2> A_BLC<2> A_BLC_SEL A_BLT<2> A_BLT_SEL A_PRE_N A_SEL_P<2> A_WR_ONE ++ A_WR_ZERO VDD VSS / RM_IHPSG13_256x32_c2_1P_BLDRV +XA_BLTMUX<1> A_BLC<1> A_BLC_SEL A_BLT<1> A_BLT_SEL A_PRE_N A_SEL_P<1> A_WR_ONE ++ A_WR_ZERO VDD VSS / RM_IHPSG13_256x32_c2_1P_BLDRV +XA_BLTMUX<0> A_BLC<0> A_BLC_SEL A_BLT<0> A_BLT_SEL A_PRE_N A_SEL_P<0> A_WR_ONE ++ A_WR_ZERO VDD VSS / RM_IHPSG13_256x32_c2_1P_BLDRV +XA_R2 A_RCLK_L A_RCLK_R / RSC_IHPSG13_MET3RES +XA_I87 A_WCLK_L A_WCLK_R / RSC_IHPSG13_MET3RES +XA_I88 A_DCLK_L A_DCLK_R / RSC_IHPSG13_MET3RES +XA_I89 A_DCLK_B_L A_DCLK_B_R / RSC_IHPSG13_MET3RES +XA_I90 A_WCLK_B_L A_WCLK_B_R / RSC_IHPSG13_MET3RES +XA_I91 A_RCLK_B_L A_RCLK_B_R / RSC_IHPSG13_MET3RES +XA_ISENSE A_SAE A_BLC_SEL A_BLT_SEL net19 net20 VDD VSS / ++ RSC_IHPSG13_DFPQD_MSAFFX2 +XA_I51 net19 A_DR_O VDD VSS / RSC_IHPSG13_INVX4 +XA_I78 A_RCLK_B_L A_SAE VDD VSS / RSC_IHPSG13_CBUFX2 +XA_DREG A_BIST_EN_I A_BIST_DW_I A_DCLK_B_L A_DW_I A_DI_R net22 VDD VSS ++ / RSC_IHPSG13_DFNQMX2IX1 +XA_BREG A_BIST_EN_I A_BIST_BM_I A_DCLK_B_L A_BM_I A_BM_R net24 VDD VSS ++ / RSC_IHPSG13_DFNQMX2IX1 +XA_DEC3INV<15> net23<0> A_SEL_P<15> VDD VSS / RSC_IHPSG13_INVX2 +XA_DEC3INV<14> net23<1> A_SEL_P<14> VDD VSS / RSC_IHPSG13_INVX2 +XA_DEC3INV<13> net23<2> A_SEL_P<13> VDD VSS / RSC_IHPSG13_INVX2 +XA_DEC3INV<12> net23<3> A_SEL_P<12> VDD VSS / RSC_IHPSG13_INVX2 +XA_DEC3INV<11> net23<4> A_SEL_P<11> VDD VSS / RSC_IHPSG13_INVX2 +XA_DEC3INV<10> net23<5> A_SEL_P<10> VDD VSS / RSC_IHPSG13_INVX2 +XA_DEC3INV<9> net23<6> A_SEL_P<9> VDD VSS / RSC_IHPSG13_INVX2 +XA_DEC3INV<8> net23<7> A_SEL_P<8> VDD VSS / RSC_IHPSG13_INVX2 +XA_DEC3INV<7> net23<8> A_SEL_P<7> VDD VSS / RSC_IHPSG13_INVX2 +XA_DEC3INV<6> net23<9> A_SEL_P<6> VDD VSS / RSC_IHPSG13_INVX2 +XA_DEC3INV<5> net23<10> A_SEL_P<5> VDD VSS / RSC_IHPSG13_INVX2 +XA_DEC3INV<4> net23<11> A_SEL_P<4> VDD VSS / RSC_IHPSG13_INVX2 +XA_DEC3INV<3> net23<12> A_SEL_P<3> VDD VSS / RSC_IHPSG13_INVX2 +XA_DEC3INV<2> net23<13> A_SEL_P<2> VDD VSS / RSC_IHPSG13_INVX2 +XA_DEC3INV<1> net23<14> A_SEL_P<1> VDD VSS / RSC_IHPSG13_INVX2 +XA_DEC3INV<0> net23<15> A_SEL_P<0> VDD VSS / RSC_IHPSG13_INVX2 +XA_I83 A_BM_R A_BM_N VDD VSS / RSC_IHPSG13_INVX2 +XA_I49 A_DI_R A_DI_N VDD VSS / RSC_IHPSG13_INVX2 +XA_I70<4> VDD VSS / RSC_IHPSG13_FILLCAP8 +XA_I70<3> VDD VSS / RSC_IHPSG13_FILLCAP8 +XA_I70<2> VDD VSS / RSC_IHPSG13_FILLCAP8 +XA_I70<1> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI73<14> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI73<13> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI73<12> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI73<11> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI73<10> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI73<9> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI73<8> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI73<7> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI73<6> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI73<5> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI73<4> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI73<3> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI73<2> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI73<1> VDD VSS / RSC_IHPSG13_FILLCAP8 +XA_I44 A_BM_N A_WCLK_B_L A_DO_WRITE_P VDD VSS / RSC_IHPSG13_NOR2X2 +XA_DEC3<15> A_P0 A_ADDR_DEC<7> net23<0> VDD VSS / RSC_IHPSG13_NAND2X2 +XA_DEC3<14> A_P0 A_ADDR_DEC<6> net23<1> VDD VSS / RSC_IHPSG13_NAND2X2 +XA_DEC3<13> A_P0 A_ADDR_DEC<5> net23<2> VDD VSS / RSC_IHPSG13_NAND2X2 +XA_DEC3<12> A_P0 A_ADDR_DEC<4> net23<3> VDD VSS / RSC_IHPSG13_NAND2X2 +XA_DEC3<11> A_P0 A_ADDR_DEC<3> net23<4> VDD VSS / RSC_IHPSG13_NAND2X2 +XA_DEC3<10> A_P0 A_ADDR_DEC<2> net23<5> VDD VSS / RSC_IHPSG13_NAND2X2 +XA_DEC3<9> A_P0 A_ADDR_DEC<1> net23<6> VDD VSS / RSC_IHPSG13_NAND2X2 +XA_DEC3<8> A_P0 A_ADDR_DEC<0> net23<7> VDD VSS / RSC_IHPSG13_NAND2X2 +XA_DEC3<7> A_N0 A_ADDR_DEC<7> net23<8> VDD VSS / RSC_IHPSG13_NAND2X2 +XA_DEC3<6> A_N0 A_ADDR_DEC<6> net23<9> VDD VSS / RSC_IHPSG13_NAND2X2 +XA_DEC3<5> A_N0 A_ADDR_DEC<5> net23<10> VDD VSS / RSC_IHPSG13_NAND2X2 +XA_DEC3<4> A_N0 A_ADDR_DEC<4> net23<11> VDD VSS / RSC_IHPSG13_NAND2X2 +XA_DEC3<3> A_N0 A_ADDR_DEC<3> net23<12> VDD VSS / RSC_IHPSG13_NAND2X2 +XA_DEC3<2> A_N0 A_ADDR_DEC<2> net23<13> VDD VSS / RSC_IHPSG13_NAND2X2 +XA_DEC3<1> A_N0 A_ADDR_DEC<1> net23<14> VDD VSS / RSC_IHPSG13_NAND2X2 +XA_DEC3<0> A_N0 A_ADDR_DEC<0> net23<15> VDD VSS / RSC_IHPSG13_NAND2X2 +XA_BM_TIEH A_TIEH_O VDD VSS / RSC_IHPSG13_TIEH +.ENDS + + +.SUBCKT RM_IHPSG13_256x32_c2_1P_COLDEC3 ACLK_N ADDR<2> ADDR<1> ADDR<0> ADDR_COL<1> ++ ADDR_COL<0> ADDR_DEC<7> ADDR_DEC<6> ADDR_DEC<5> ADDR_DEC<4> ADDR_DEC<3> ++ ADDR_DEC<2> ADDR_DEC<1> ADDR_DEC<0> BIST_ADDR<2> BIST_ADDR<1> BIST_ADDR<0> ++ BIST_EN_I VDD VSS +XI15<1> ADDR_COL<1> VDD VSS / RSC_IHPSG13_TIEL +XI15<0> ADDR_COL<0> VDD VSS / RSC_IHPSG13_TIEL +XI1<7> PADR<0> PADR<1> PADR<2> addr_n<7> VDD VSS / RSC_IHPSG13_NAND3X2 +XI1<6> NADR<0> PADR<1> PADR<2> addr_n<6> VDD VSS / RSC_IHPSG13_NAND3X2 +XI1<5> PADR<0> NADR<1> PADR<2> addr_n<5> VDD VSS / RSC_IHPSG13_NAND3X2 +XI1<4> NADR<0> NADR<1> PADR<2> addr_n<4> VDD VSS / RSC_IHPSG13_NAND3X2 +XI1<3> PADR<0> PADR<1> NADR<2> addr_n<3> VDD VSS / RSC_IHPSG13_NAND3X2 +XI1<2> NADR<0> PADR<1> NADR<2> addr_n<2> VDD VSS / RSC_IHPSG13_NAND3X2 +XI1<1> PADR<0> NADR<1> NADR<2> addr_n<1> VDD VSS / RSC_IHPSG13_NAND3X2 +XI1<0> NADR<0> NADR<1> NADR<2> addr_n<0> VDD VSS / RSC_IHPSG13_NAND3X2 +XDFF<2> BIST_EN_I BIST_ADDR<2> ACLK_N ADDR<2> padr_int<2> net6<0> VDD ++ VSS / RSC_IHPSG13_DFNQMX2IX1 +XDFF<1> BIST_EN_I BIST_ADDR<1> ACLK_N ADDR<1> padr_int<1> net6<1> VDD ++ VSS / RSC_IHPSG13_DFNQMX2IX1 +XDFF<0> BIST_EN_I BIST_ADDR<0> ACLK_N ADDR<0> padr_int<0> net6<2> VDD ++ VSS / RSC_IHPSG13_DFNQMX2IX1 +XI17<2> VDD VSS / RSC_IHPSG13_FILLCAP4 +XI17<1> VDD VSS / RSC_IHPSG13_FILLCAP4 +XI13<2> NADR<2> PADR<2> VDD VSS / RSC_IHPSG13_INVX2 +XI13<1> NADR<1> PADR<1> VDD VSS / RSC_IHPSG13_INVX2 +XI13<0> NADR<0> PADR<0> VDD VSS / RSC_IHPSG13_INVX2 +XI3<2> padr_int<2> NADR<2> VDD VSS / RSC_IHPSG13_INVX2 +XI3<1> padr_int<1> NADR<1> VDD VSS / RSC_IHPSG13_INVX2 +XI3<0> padr_int<0> NADR<0> VDD VSS / RSC_IHPSG13_INVX2 +XI2<7> addr_n<7> ADDR_DEC<7> VDD VSS / RSC_IHPSG13_INVX2 +XI2<6> addr_n<6> ADDR_DEC<6> VDD VSS / RSC_IHPSG13_INVX2 +XI2<5> addr_n<5> ADDR_DEC<5> VDD VSS / RSC_IHPSG13_INVX2 +XI2<4> addr_n<4> ADDR_DEC<4> VDD VSS / RSC_IHPSG13_INVX2 +XI2<3> addr_n<3> ADDR_DEC<3> VDD VSS / RSC_IHPSG13_INVX2 +XI2<2> addr_n<2> ADDR_DEC<2> VDD VSS / RSC_IHPSG13_INVX2 +XI2<1> addr_n<1> ADDR_DEC<1> VDD VSS / RSC_IHPSG13_INVX2 +XI2<0> addr_n<0> ADDR_DEC<0> VDD VSS / RSC_IHPSG13_INVX2 +XI16<6> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI16<5> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI16<4> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI16<3> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI16<2> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI16<1> VDD VSS / RSC_IHPSG13_FILLCAP8 +.ENDS +.SUBCKT RM_IHPSG13_256x32_c2_1P_COLCTRL3 A_ADDR_DEC<7> A_ADDR_DEC<6> A_ADDR_DEC<5> ++ A_ADDR_DEC<4> A_ADDR_DEC<3> A_ADDR_DEC<2> A_ADDR_DEC<1> A_ADDR_DEC<0> ++ A_BIST_BM_I A_BIST_DW_I A_BIST_EN_I A_BLC<7> A_BLC<6> A_BLC<5> A_BLC<4> ++ A_BLC<3> A_BLC<2> A_BLC<1> A_BLC<0> A_BLT<7> A_BLT<6> A_BLT<5> A_BLT<4> ++ A_BLT<3> A_BLT<2> A_BLT<1> A_BLT<0> A_BM_I A_DCLK_B_L A_DCLK_B_R A_DCLK_L ++ A_DCLK_R A_DR_O A_DW_I A_RCLK_B_L A_RCLK_B_R A_RCLK_L A_RCLK_R A_TIEH_O ++ A_WCLK_B_L A_WCLK_B_R A_WCLK_L A_WCLK_R VDD VSS +XA_DREG A_BIST_EN_I A_BIST_DW_I A_DCLK_B_L A_DW_I A_DI_R net22 VDD VSS ++ / RSC_IHPSG13_DFNQMX2IX1 +XA_BREG A_BIST_EN_I A_BIST_BM_I A_DCLK_B_R A_BM_I A_BM_R net23 VDD VSS ++ / RSC_IHPSG13_DFNQMX2IX1 +XA_I70<8> VDD VSS / RSC_IHPSG13_FILLCAP8 +XA_I70<7> VDD VSS / RSC_IHPSG13_FILLCAP8 +XA_I70<6> VDD VSS / RSC_IHPSG13_FILLCAP8 +XA_I70<5> VDD VSS / RSC_IHPSG13_FILLCAP8 +XA_I70<4> VDD VSS / RSC_IHPSG13_FILLCAP8 +XA_I70<3> VDD VSS / RSC_IHPSG13_FILLCAP8 +XA_I70<2> VDD VSS / RSC_IHPSG13_FILLCAP8 +XA_I70<1> VDD VSS / RSC_IHPSG13_FILLCAP8 +XA_I51 net19 A_DR_O VDD VSS / RSC_IHPSG13_INVX4 +XA_I44 A_BM_N A_WCLK_B_R A_DO_WRITE_P VDD VSS / RSC_IHPSG13_NOR2X2 +XA_BM_TIEH A_TIEH_O VDD VSS / RSC_IHPSG13_TIEH +XA_BLTMUX<7> A_BLC<7> A_BLC_SEL A_BLT<7> A_BLT_SEL A_PRE_N A_ADDR_DEC<7> ++ A_WR_ONE A_WR_ZERO VDD VSS / RM_IHPSG13_256x32_c2_1P_BLDRV +XA_BLTMUX<6> A_BLC<6> A_BLC_SEL A_BLT<6> A_BLT_SEL A_PRE_N A_ADDR_DEC<6> ++ A_WR_ONE A_WR_ZERO VDD VSS / RM_IHPSG13_256x32_c2_1P_BLDRV +XA_BLTMUX<5> A_BLC<5> A_BLC_SEL A_BLT<5> A_BLT_SEL A_PRE_N A_ADDR_DEC<5> ++ A_WR_ONE A_WR_ZERO VDD VSS / RM_IHPSG13_256x32_c2_1P_BLDRV +XA_BLTMUX<4> A_BLC<4> A_BLC_SEL A_BLT<4> A_BLT_SEL A_PRE_N A_ADDR_DEC<4> ++ A_WR_ONE A_WR_ZERO VDD VSS / RM_IHPSG13_256x32_c2_1P_BLDRV +XA_BLTMUX<3> A_BLC<3> A_BLC_SEL A_BLT<3> A_BLT_SEL A_PRE_N A_ADDR_DEC<3> ++ A_WR_ONE A_WR_ZERO VDD VSS / RM_IHPSG13_256x32_c2_1P_BLDRV +XA_BLTMUX<2> A_BLC<2> A_BLC_SEL A_BLT<2> A_BLT_SEL A_PRE_N A_ADDR_DEC<2> ++ A_WR_ONE A_WR_ZERO VDD VSS / RM_IHPSG13_256x32_c2_1P_BLDRV +XA_BLTMUX<1> A_BLC<1> A_BLC_SEL A_BLT<1> A_BLT_SEL A_PRE_N A_ADDR_DEC<1> ++ A_WR_ONE A_WR_ZERO VDD VSS / RM_IHPSG13_256x32_c2_1P_BLDRV +XA_BLTMUX<0> A_BLC<0> A_BLC_SEL A_BLT<0> A_BLT_SEL A_PRE_N A_ADDR_DEC<0> ++ A_WR_ONE A_WR_ZERO VDD VSS / RM_IHPSG13_256x32_c2_1P_BLDRV +XA_I49 A_DI_R A_DI_N VDD VSS / RSC_IHPSG13_INVX2 +XA_I83 A_BM_R A_BM_N VDD VSS / RSC_IHPSG13_INVX2 +XA_I69 A_DCLK_L A_DCLK_B_L VDD VSS / RSC_IHPSG13_CINVX2 +XA_I50 A_WCLK_L A_WCLK_B_L VDD VSS / RSC_IHPSG13_CINVX2 +XA_EBUF A_RCLK_L A_RCLK_B_L VDD VSS / RSC_IHPSG13_CINVX2 +XA_I78 A_RCLK_B_L A_SAE VDD VSS / RSC_IHPSG13_CBUFX2 +XA_I88 A_DCLK_L A_DCLK_R / RSC_IHPSG13_MET3RES +XA_I87 A_WCLK_L A_WCLK_R / RSC_IHPSG13_MET3RES +XA_R2 A_RCLK_L A_RCLK_R / RSC_IHPSG13_MET3RES +XA_I91 A_RCLK_B_L A_RCLK_B_R / RSC_IHPSG13_MET3RES +XA_I90 A_WCLK_B_L A_WCLK_B_R / RSC_IHPSG13_MET3RES +XA_I89 A_DCLK_B_L A_DCLK_B_R / RSC_IHPSG13_MET3RES +XA_I80 A_WCLK_B_R A_RCLK_B_R net21 VDD VSS / RSC_IHPSG13_AND2X2 +XA_I76 A_DI_N A_DO_WRITE_P A_WR_ZERO VDD VSS / RSC_IHPSG13_AND2X2 +XA_I75 A_DI_R A_DO_WRITE_P A_WR_ONE VDD VSS / RSC_IHPSG13_AND2X2 +XA_ISENSE A_SAE A_BLC_SEL A_BLT_SEL net19 net20 VDD VSS / ++ RSC_IHPSG13_DFPQD_MSAFFX2 +XA_I81 net21 A_PRE_N VDD VSS / RSC_IHPSG13_CINVX4_WN +XA_CAPS<5> VDD VSS / RSC_IHPSG13_FILLCAP4 +XA_CAPS<4> VDD VSS / RSC_IHPSG13_FILLCAP4 +XA_CAPS<3> VDD VSS / RSC_IHPSG13_FILLCAP4 +XA_CAPS<2> VDD VSS / RSC_IHPSG13_FILLCAP4 +XA_CAPS<1> VDD VSS / RSC_IHPSG13_FILLCAP4 +.ENDS + +.SUBCKT RM_IHPSG13_256x32_c2_2P_BITKIT_16x2_CORNER VDD_CORE VSS +XI16 VDD_CORE VSS VDD_CORE VSS / ++ RM_IHPSG13_256x32_c2_1P_BITKIT_CORNER +.ENDS +.SUBCKT RM_IHPSG13_256x32_c2_2P_BITKIT_EDGE_LR A_WL B_WL NW PW VDD VSS +MN1 VSS A_WL VSS VSS sg13_lv_nmos m=1 w=300.0n l=130.00n ng=1 nrd=0 nrs=0 +MN0 VSS B_WL VSS VSS sg13_lv_nmos m=1 w=300.0n l=130.00n ng=1 nrd=0 nrs=0 +.ENDS +.SUBCKT RM_IHPSG13_256x32_c2_2P_BITKIT_16x2_EDGE_LR A_WL<15> A_WL<14> A_WL<13> A_WL<12> ++ A_WL<11> A_WL<10> A_WL<9> A_WL<8> A_WL<7> A_WL<6> A_WL<5> A_WL<4> A_WL<3> ++ A_WL<2> A_WL<1> A_WL<0> B_WL<15> B_WL<14> B_WL<13> B_WL<12> B_WL<11> ++ B_WL<10> B_WL<9> B_WL<8> B_WL<7> B_WL<6> B_WL<5> B_WL<4> B_WL<3> B_WL<2> ++ B_WL<1> B_WL<0> VDD_CORE VSS +XI0<15> A_WL<15> B_WL<15> VDD_CORE VSS VDD_CORE VSS ++ / RM_IHPSG13_256x32_c2_2P_BITKIT_EDGE_LR +XI0<14> A_WL<14> B_WL<14> VDD_CORE VSS VDD_CORE VSS ++ / RM_IHPSG13_256x32_c2_2P_BITKIT_EDGE_LR +XI0<13> A_WL<13> B_WL<13> VDD_CORE VSS VDD_CORE VSS ++ / RM_IHPSG13_256x32_c2_2P_BITKIT_EDGE_LR +XI0<12> A_WL<12> B_WL<12> VDD_CORE VSS VDD_CORE VSS ++ / RM_IHPSG13_256x32_c2_2P_BITKIT_EDGE_LR +XI0<11> A_WL<11> B_WL<11> VDD_CORE VSS VDD_CORE VSS ++ / RM_IHPSG13_256x32_c2_2P_BITKIT_EDGE_LR +XI0<10> A_WL<10> B_WL<10> VDD_CORE VSS VDD_CORE VSS ++ / RM_IHPSG13_256x32_c2_2P_BITKIT_EDGE_LR +XI0<9> A_WL<9> B_WL<9> VDD_CORE VSS VDD_CORE VSS / ++ RM_IHPSG13_256x32_c2_2P_BITKIT_EDGE_LR +XI0<8> A_WL<8> B_WL<8> VDD_CORE VSS VDD_CORE VSS / ++ RM_IHPSG13_256x32_c2_2P_BITKIT_EDGE_LR +XI0<7> A_WL<7> B_WL<7> VDD_CORE VSS VDD_CORE VSS / ++ RM_IHPSG13_256x32_c2_2P_BITKIT_EDGE_LR +XI0<6> A_WL<6> B_WL<6> VDD_CORE VSS VDD_CORE VSS / ++ RM_IHPSG13_256x32_c2_2P_BITKIT_EDGE_LR +XI0<5> A_WL<5> B_WL<5> VDD_CORE VSS VDD_CORE VSS / ++ RM_IHPSG13_256x32_c2_2P_BITKIT_EDGE_LR +XI0<4> A_WL<4> B_WL<4> VDD_CORE VSS VDD_CORE VSS / ++ RM_IHPSG13_256x32_c2_2P_BITKIT_EDGE_LR +XI0<3> A_WL<3> B_WL<3> VDD_CORE VSS VDD_CORE VSS / ++ RM_IHPSG13_256x32_c2_2P_BITKIT_EDGE_LR +XI0<2> A_WL<2> B_WL<2> VDD_CORE VSS VDD_CORE VSS / ++ RM_IHPSG13_256x32_c2_2P_BITKIT_EDGE_LR +XI0<1> A_WL<1> B_WL<1> VDD_CORE VSS VDD_CORE VSS / ++ RM_IHPSG13_256x32_c2_2P_BITKIT_EDGE_LR +XI0<0> A_WL<0> B_WL<0> VDD_CORE VSS VDD_CORE VSS / ++ RM_IHPSG13_256x32_c2_2P_BITKIT_EDGE_LR +.ENDS +.SUBCKT RM_IHPSG13_256x32_c2_2P_BITKIT_CELL A_BLC_BOT A_BLC_TOP A_BLT_BOT A_BLT_TOP ++ A_LWL A_RWL B_BLC_BOT B_BLC_TOP B_BLT_BOT B_BLT_TOP B_LWL B_RWL NW PW VDD VSS +MN5 NC B_RWL B_BLC_BOT PW sg13_lv_nmos m=1 w=300.0n l=130.00n ng=1 nrd=0 nrs=0 +MN4 B_BLT_BOT B_LWL NT PW sg13_lv_nmos m=1 w=300.0n l=130.00n ng=1 nrd=0 nrs=0 +MN0 NC NT VSS PW sg13_lv_nmos m=1 w=600.0n l=130.00n ng=2 nrd=0 nrs=0 +MN1 NT NC VSS PW sg13_lv_nmos m=1 w=600.0n l=130.00n ng=2 nrd=0 nrs=0 +MN3 NC A_RWL A_BLC_TOP PW sg13_lv_nmos m=1 w=300.0n l=130.00n ng=1 nrd=0 nrs=0 +MN2 A_BLT_TOP A_LWL NT PW sg13_lv_nmos m=1 w=300.0n l=130.00n ng=1 nrd=0 nrs=0 +MP1 NT NC VDD NW sg13_lv_pmos m=1 w=150.00n l=130.00n ng=1 nrd=0 nrs=0 +MP0 NC NT VDD NW sg13_lv_pmos m=1 w=150.00n l=130.00n ng=1 nrd=0 nrs=0 +R5 B_RWL B_LWL lvsres w=2.6e-07 l=6e-07 +R4 B_BLC_BOT B_BLC_TOP lvsres w=2.6e-07 l=6e-07 +R3 B_BLT_BOT B_BLT_TOP lvsres w=2.6e-07 l=6e-07 +R1 A_BLC_BOT A_BLC_TOP lvsres w=2.6e-07 l=6e-07 +R0 A_BLT_BOT A_BLT_TOP lvsres w=2.6e-07 l=6e-07 +R2 A_RWL A_LWL lvsres w=2.6e-07 l=6e-07 +.ENDS +.SUBCKT RM_IHPSG13_256x32_c2_2P_BITKIT_16x2_SRAM A_BLC_BOT<1> A_BLC_BOT<0> A_BLC_TOP<1> ++ A_BLC_TOP<0> A_BLT_BOT<1> A_BLT_BOT<0> A_BLT_TOP<1> A_BLT_TOP<0> A_LWL<15> ++ A_LWL<14> A_LWL<13> A_LWL<12> A_LWL<11> A_LWL<10> A_LWL<9> A_LWL<8> A_LWL<7> ++ A_LWL<6> A_LWL<5> A_LWL<4> A_LWL<3> A_LWL<2> A_LWL<1> A_LWL<0> A_RWL<15> ++ A_RWL<14> A_RWL<13> A_RWL<12> A_RWL<11> A_RWL<10> A_RWL<9> A_RWL<8> A_RWL<7> ++ A_RWL<6> A_RWL<5> A_RWL<4> A_RWL<3> A_RWL<2> A_RWL<1> A_RWL<0> B_BLC_BOT<1> ++ B_BLC_BOT<0> B_BLC_TOP<1> B_BLC_TOP<0> B_BLT_BOT<1> B_BLT_BOT<0> ++ B_BLT_TOP<1> B_BLT_TOP<0> B_LWL<15> B_LWL<14> B_LWL<13> B_LWL<12> B_LWL<11> ++ B_LWL<10> B_LWL<9> B_LWL<8> B_LWL<7> B_LWL<6> B_LWL<5> B_LWL<4> B_LWL<3> ++ B_LWL<2> B_LWL<1> B_LWL<0> B_RWL<15> B_RWL<14> B_RWL<13> B_RWL<12> B_RWL<11> ++ B_RWL<10> B_RWL<9> B_RWL<8> B_RWL<7> B_RWL<6> B_RWL<5> B_RWL<4> B_RWL<3> ++ B_RWL<2> B_RWL<1> B_RWL<0> VDD_CORE VSS +XCELL<31> A_BLC_TOP<1> A_RBLC<15> A_BLT_TOP<1> A_RBLT<15> A_XWL<15> A_RWL<15> ++ B_BLC_TOP<1> B_RBLC<15> B_BLT_TOP<1> B_RBLT<15> B_XWL<15> B_RWL<15> ++ VDD_CORE VSS VDD_CORE VSS / ++ RM_IHPSG13_256x32_c2_2P_BITKIT_CELL +XCELL<30> A_RBLC<14> A_RBLC<15> A_RBLT<14> A_RBLT<15> A_XWL<14> A_RWL<14> ++ B_RBLC<14> B_RBLC<15> B_RBLT<14> B_RBLT<15> B_XWL<14> B_RWL<14> VDD_CORE ++ VSS VDD_CORE VSS / RM_IHPSG13_256x32_c2_2P_BITKIT_CELL +XCELL<29> A_RBLC<14> A_RBLC<13> A_RBLT<14> A_RBLT<13> A_XWL<13> A_RWL<13> ++ B_RBLC<14> B_RBLC<13> B_RBLT<14> B_RBLT<13> B_XWL<13> B_RWL<13> VDD_CORE ++ VSS VDD_CORE VSS / RM_IHPSG13_256x32_c2_2P_BITKIT_CELL +XCELL<28> A_RBLC<12> A_RBLC<13> A_RBLT<12> A_RBLT<13> A_XWL<12> A_RWL<12> ++ B_RBLC<12> B_RBLC<13> B_RBLT<12> B_RBLT<13> B_XWL<12> B_RWL<12> VDD_CORE ++ VSS VDD_CORE VSS / RM_IHPSG13_256x32_c2_2P_BITKIT_CELL +XCELL<27> A_RBLC<12> A_RBLC<11> A_RBLT<12> A_RBLT<11> A_XWL<11> A_RWL<11> ++ B_RBLC<12> B_RBLC<11> B_RBLT<12> B_RBLT<11> B_XWL<11> B_RWL<11> VDD_CORE ++ VSS VDD_CORE VSS / RM_IHPSG13_256x32_c2_2P_BITKIT_CELL +XCELL<26> A_RBLC<10> A_RBLC<11> A_RBLT<10> A_RBLT<11> A_XWL<10> A_RWL<10> ++ B_RBLC<10> B_RBLC<11> B_RBLT<10> B_RBLT<11> B_XWL<10> B_RWL<10> VDD_CORE ++ VSS VDD_CORE VSS / RM_IHPSG13_256x32_c2_2P_BITKIT_CELL +XCELL<25> A_RBLC<10> A_RBLC<9> A_RBLT<10> A_RBLT<9> A_XWL<9> A_RWL<9> ++ B_RBLC<10> B_RBLC<9> B_RBLT<10> B_RBLT<9> B_XWL<9> B_RWL<9> VDD_CORE ++ VSS VDD_CORE VSS / RM_IHPSG13_256x32_c2_2P_BITKIT_CELL +XCELL<24> A_RBLC<8> A_RBLC<9> A_RBLT<8> A_RBLT<9> A_XWL<8> A_RWL<8> B_RBLC<8> ++ B_RBLC<9> B_RBLT<8> B_RBLT<9> B_XWL<8> B_RWL<8> VDD_CORE VSS ++ VDD_CORE VSS / RM_IHPSG13_256x32_c2_2P_BITKIT_CELL +XCELL<23> A_RBLC<8> A_RBLC<7> A_RBLT<8> A_RBLT<7> A_XWL<7> A_RWL<7> B_RBLC<8> ++ B_RBLC<7> B_RBLT<8> B_RBLT<7> B_XWL<7> B_RWL<7> VDD_CORE VSS ++ VDD_CORE VSS / RM_IHPSG13_256x32_c2_2P_BITKIT_CELL +XCELL<22> A_RBLC<6> A_RBLC<7> A_RBLT<6> A_RBLT<7> A_XWL<6> A_RWL<6> B_RBLC<6> ++ B_RBLC<7> B_RBLT<6> B_RBLT<7> B_XWL<6> B_RWL<6> VDD_CORE VSS ++ VDD_CORE VSS / RM_IHPSG13_256x32_c2_2P_BITKIT_CELL +XCELL<21> A_RBLC<6> A_RBLC<5> A_RBLT<6> A_RBLT<5> A_XWL<5> A_RWL<5> B_RBLC<6> ++ B_RBLC<5> B_RBLT<6> B_RBLT<5> B_XWL<5> B_RWL<5> VDD_CORE VSS ++ VDD_CORE VSS / RM_IHPSG13_256x32_c2_2P_BITKIT_CELL +XCELL<20> A_RBLC<4> A_RBLC<5> A_RBLT<4> A_RBLT<5> A_XWL<4> A_RWL<4> B_RBLC<4> ++ B_RBLC<5> B_RBLT<4> B_RBLT<5> B_XWL<4> B_RWL<4> VDD_CORE VSS ++ VDD_CORE VSS / RM_IHPSG13_256x32_c2_2P_BITKIT_CELL +XCELL<19> A_RBLC<4> A_RBLC<3> A_RBLT<4> A_RBLT<3> A_XWL<3> A_RWL<3> B_RBLC<4> ++ B_RBLC<3> B_RBLT<4> B_RBLT<3> B_XWL<3> B_RWL<3> VDD_CORE VSS ++ VDD_CORE VSS / RM_IHPSG13_256x32_c2_2P_BITKIT_CELL +XCELL<18> A_RBLC<2> A_RBLC<3> A_RBLT<2> A_RBLT<3> A_XWL<2> A_RWL<2> B_RBLC<2> ++ B_RBLC<3> B_RBLT<2> B_RBLT<3> B_XWL<2> B_RWL<2> VDD_CORE VSS ++ VDD_CORE VSS / RM_IHPSG13_256x32_c2_2P_BITKIT_CELL +XCELL<17> A_RBLC<2> A_RBLC<1> A_RBLT<2> A_RBLT<1> A_XWL<1> A_RWL<1> B_RBLC<2> ++ B_RBLC<1> B_RBLT<2> B_RBLT<1> B_XWL<1> B_RWL<1> VDD_CORE VSS ++ VDD_CORE VSS / RM_IHPSG13_256x32_c2_2P_BITKIT_CELL +XCELL<16> A_BLC_BOT<1> A_RBLC<1> A_BLT_BOT<1> A_RBLT<1> A_XWL<0> A_RWL<0> ++ B_BLC_BOT<1> B_RBLC<1> B_BLT_BOT<1> B_RBLT<1> B_XWL<0> B_RWL<0> VDD_CORE ++ VSS VDD_CORE VSS / RM_IHPSG13_256x32_c2_2P_BITKIT_CELL +XCELL<15> A_BLC_TOP<0> A_LBLC<15> A_BLT_TOP<0> A_LBLT<15> A_LWL<15> A_XWL<15> ++ B_BLC_TOP<0> B_LBLC<15> B_BLT_TOP<0> B_LBLT<15> B_LWL<15> B_XWL<15> ++ VDD_CORE VSS VDD_CORE VSS / ++ RM_IHPSG13_256x32_c2_2P_BITKIT_CELL +XCELL<14> A_LBLC<14> A_LBLC<15> A_LBLT<14> A_LBLT<15> A_LWL<14> A_XWL<14> ++ B_LBLC<14> B_LBLC<15> B_LBLT<14> B_LBLT<15> B_LWL<14> B_XWL<14> VDD_CORE ++ VSS VDD_CORE VSS / RM_IHPSG13_256x32_c2_2P_BITKIT_CELL +XCELL<13> A_LBLC<14> A_LBLC<13> A_LBLT<14> A_LBLT<13> A_LWL<13> A_XWL<13> ++ B_LBLC<14> B_LBLC<13> B_LBLT<14> B_LBLT<13> B_LWL<13> B_XWL<13> VDD_CORE ++ VSS VDD_CORE VSS / RM_IHPSG13_256x32_c2_2P_BITKIT_CELL +XCELL<12> A_LBLC<12> A_LBLC<13> A_LBLT<12> A_LBLT<13> A_LWL<12> A_XWL<12> ++ B_LBLC<12> B_LBLC<13> B_LBLT<12> B_LBLT<13> B_LWL<12> B_XWL<12> VDD_CORE ++ VSS VDD_CORE VSS / RM_IHPSG13_256x32_c2_2P_BITKIT_CELL +XCELL<11> A_LBLC<12> A_LBLC<11> A_LBLT<12> A_LBLT<11> A_LWL<11> A_XWL<11> ++ B_LBLC<12> B_LBLC<11> B_LBLT<12> B_LBLT<11> B_LWL<11> B_XWL<11> VDD_CORE ++ VSS VDD_CORE VSS / RM_IHPSG13_256x32_c2_2P_BITKIT_CELL +XCELL<10> A_LBLC<10> A_LBLC<11> A_LBLT<10> A_LBLT<11> A_LWL<10> A_XWL<10> ++ B_LBLC<10> B_LBLC<11> B_LBLT<10> B_LBLT<11> B_LWL<10> B_XWL<10> VDD_CORE ++ VSS VDD_CORE VSS / RM_IHPSG13_256x32_c2_2P_BITKIT_CELL +XCELL<9> A_LBLC<10> A_LBLC<9> A_LBLT<10> A_LBLT<9> A_LWL<9> A_XWL<9> ++ B_LBLC<10> B_LBLC<9> B_LBLT<10> B_LBLT<9> B_LWL<9> B_XWL<9> VDD_CORE ++ VSS VDD_CORE VSS / RM_IHPSG13_256x32_c2_2P_BITKIT_CELL +XCELL<8> A_LBLC<8> A_LBLC<9> A_LBLT<8> A_LBLT<9> A_LWL<8> A_XWL<8> B_LBLC<8> ++ B_LBLC<9> B_LBLT<8> B_LBLT<9> B_LWL<8> B_XWL<8> VDD_CORE VSS ++ VDD_CORE VSS / RM_IHPSG13_256x32_c2_2P_BITKIT_CELL +XCELL<7> A_LBLC<8> A_LBLC<7> A_LBLT<8> A_LBLT<7> A_LWL<7> A_XWL<7> B_LBLC<8> ++ B_LBLC<7> B_LBLT<8> B_LBLT<7> B_LWL<7> B_XWL<7> VDD_CORE VSS ++ VDD_CORE VSS / RM_IHPSG13_256x32_c2_2P_BITKIT_CELL +XCELL<6> A_LBLC<6> A_LBLC<7> A_LBLT<6> A_LBLT<7> A_LWL<6> A_XWL<6> B_LBLC<6> ++ B_LBLC<7> B_LBLT<6> B_LBLT<7> B_LWL<6> B_XWL<6> VDD_CORE VSS ++ VDD_CORE VSS / RM_IHPSG13_256x32_c2_2P_BITKIT_CELL +XCELL<5> A_LBLC<6> A_LBLC<5> A_LBLT<6> A_LBLT<5> A_LWL<5> A_XWL<5> B_LBLC<6> ++ B_LBLC<5> B_LBLT<6> B_LBLT<5> B_LWL<5> B_XWL<5> VDD_CORE VSS ++ VDD_CORE VSS / RM_IHPSG13_256x32_c2_2P_BITKIT_CELL +XCELL<4> A_LBLC<4> A_LBLC<5> A_LBLT<4> A_LBLT<5> A_LWL<4> A_XWL<4> B_LBLC<4> ++ B_LBLC<5> B_LBLT<4> B_LBLT<5> B_LWL<4> B_XWL<4> VDD_CORE VSS ++ VDD_CORE VSS / RM_IHPSG13_256x32_c2_2P_BITKIT_CELL +XCELL<3> A_LBLC<4> A_LBLC<3> A_LBLT<4> A_LBLT<3> A_LWL<3> A_XWL<3> B_LBLC<4> ++ B_LBLC<3> B_LBLT<4> B_LBLT<3> B_LWL<3> B_XWL<3> VDD_CORE VSS ++ VDD_CORE VSS / RM_IHPSG13_256x32_c2_2P_BITKIT_CELL +XCELL<2> A_LBLC<2> A_LBLC<3> A_LBLT<2> A_LBLT<3> A_LWL<2> A_XWL<2> B_LBLC<2> ++ B_LBLC<3> B_LBLT<2> B_LBLT<3> B_LWL<2> B_XWL<2> VDD_CORE VSS ++ VDD_CORE VSS / RM_IHPSG13_256x32_c2_2P_BITKIT_CELL +XCELL<1> A_LBLC<2> A_LBLC<1> A_LBLT<2> A_LBLT<1> A_LWL<1> A_XWL<1> B_LBLC<2> ++ B_LBLC<1> B_LBLT<2> B_LBLT<1> B_LWL<1> B_XWL<1> VDD_CORE VSS ++ VDD_CORE VSS / RM_IHPSG13_256x32_c2_2P_BITKIT_CELL +XCELL<0> A_BLC_BOT<0> A_LBLC<1> A_BLT_BOT<0> A_LBLT<1> A_LWL<0> A_XWL<0> ++ B_BLC_BOT<0> B_LBLC<1> B_BLT_BOT<0> B_LBLT<1> B_LWL<0> B_XWL<0> VDD_CORE ++ VSS VDD_CORE VSS / RM_IHPSG13_256x32_c2_2P_BITKIT_CELL +.ENDS +.SUBCKT RM_IHPSG13_256x32_c2_2P_BITKIT_EDGE_TB A_BLC A_BLT B_BLC B_BLT NW PW VDD VSS +.ENDS +.SUBCKT RM_IHPSG13_256x32_c2_2P_BITKIT_16x2_EDGE_TB A_BLC<1> A_BLC<0> A_BLT<1> A_BLT<0> ++ B_BLC<1> B_BLC<0> B_BLT<1> B_BLT<0> VDD_CORE VSS +XEDGE<1> A_BLC<1> A_BLT<1> B_BLC<1> B_BLT<1> VDD_CORE VSS ++ VDD_CORE VSS / RM_IHPSG13_256x32_c2_2P_BITKIT_EDGE_TB +XEDGE<0> A_BLC<0> A_BLT<0> B_BLC<0> B_BLT<0> VDD_CORE VSS ++ VDD_CORE VSS / RM_IHPSG13_256x32_c2_2P_BITKIT_EDGE_TB +.ENDS +.SUBCKT RM_IHPSG13_256x32_c2_2P_BITKIT_TAP A_BLC A_BLT B_BLC B_BLT NW PW VDD VSS +.ENDS +.SUBCKT RM_IHPSG13_256x32_c2_2P_BITKIT_16x2_TAP A_BLC<1> A_BLC<0> A_BLT<1> A_BLT<0> ++ B_BLC<1> B_BLC<0> B_BLT<1> B_BLT<0> VDD_CORE VSS +XIEDGEBP_COL1<1> A_BLC<1> A_BLT<1> B_BLC<1> B_BLT<1> VDD_CORE VSS ++ VDD_CORE VSS / RM_IHPSG13_256x32_c2_2P_BITKIT_EDGE_TB +XIEDGEBP_COL1<0> A_BLC<1> A_BLT<1> B_BLC<1> B_BLT<1> VDD_CORE VSS ++ VDD_CORE VSS / RM_IHPSG13_256x32_c2_2P_BITKIT_EDGE_TB +XIEDGEBP_COL2<1> A_BLC<0> A_BLT<0> B_BLC<0> B_BLT<0> VDD_CORE VSS ++ VDD_CORE VSS / RM_IHPSG13_256x32_c2_2P_BITKIT_EDGE_TB +XIEDGEBP_COL2<0> A_BLC<0> A_BLT<0> B_BLC<0> B_BLT<0> VDD_CORE VSS ++ VDD_CORE VSS / RM_IHPSG13_256x32_c2_2P_BITKIT_EDGE_TB +XITAP<1> A_BLC<1> A_BLT<1> B_BLC<1> B_BLT<1> VDD_CORE VSS ++ VDD_CORE VSS / RM_IHPSG13_256x32_c2_2P_BITKIT_TAP +XITAP<0> A_BLC<0> A_BLT<0> B_BLC<0> B_BLT<0> VDD_CORE VSS ++ VDD_CORE VSS / RM_IHPSG13_256x32_c2_2P_BITKIT_TAP +.ENDS + + +.SUBCKT RM_IHPSG13_256x32_c2_1P_BITKIT_TAP_LR NW PW VDD VSS +.ENDS +.SUBCKT RM_IHPSG13_256x32_c2_2P_BITKIT_16x2_TAP_LR VDD_CORE VSS +XCORNER<1> VDD_CORE VSS VDD_CORE VSS / ++ RM_IHPSG13_256x32_c2_1P_BITKIT_CORNER +XCORNER<0> VDD_CORE VSS VDD_CORE VSS / ++ RM_IHPSG13_256x32_c2_1P_BITKIT_CORNER +XTAP_BORDER VDD_CORE VSS VDD_CORE VSS / ++ RM_IHPSG13_256x32_c2_1P_BITKIT_TAP_LR +.ENDS + +.SUBCKT RSC_IHPSG13_CBUFX12 A Z VDD VSS +MN1 Z net6 VSS VSS sg13_lv_nmos m=1 w=4.23u l=130.00n ng=6 nrd=0 nrs=0 +MN0 net6 A VSS VSS sg13_lv_nmos m=1 w=1.41u l=130.00n ng=2 nrd=0 nrs=0 +MP1 Z net6 VDD VDD sg13_lv_pmos m=1 w=9.72u l=130.00n ng=6 nrd=0 nrs=0 +MP0 net6 A VDD VDD sg13_lv_pmos m=1 w=3.24u l=130.00n ng=2 nrd=0 nrs=0 +.ENDS +.SUBCKT RM_IHPSG13_256x32_c2_2P_COLDRV13X12 ADDR_COL_I<1> ADDR_COL_I<0> ADDR_COL_O<1> ++ ADDR_COL_O<0> ADDR_DEC_I<7> ADDR_DEC_I<6> ADDR_DEC_I<5> ADDR_DEC_I<4> ++ ADDR_DEC_I<3> ADDR_DEC_I<2> ADDR_DEC_I<1> ADDR_DEC_I<0> ADDR_DEC_O<7> ++ ADDR_DEC_O<6> ADDR_DEC_O<5> ADDR_DEC_O<4> ADDR_DEC_O<3> ADDR_DEC_O<2> ++ ADDR_DEC_O<1> ADDR_DEC_O<0> DCLK_I DCLK_O RCLK_I RCLK_O WCLK_I WCLK_O ++ VDD VSS +XI1<3> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI1<2> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI1<1> VDD VSS / RSC_IHPSG13_FILLCAP8 +XWCLK_DRV WCLK_I WCLK_O VDD VSS / RSC_IHPSG13_CBUFX12 +XRCLK_DRV RCLK_I RCLK_O VDD VSS / RSC_IHPSG13_CBUFX12 +XDCLK_DRV DCLK_I DCLK_O VDD VSS / RSC_IHPSG13_CBUFX12 +XADDR_COL_DRV<1> ADDR_COL_I<1> ADDR_COL_O<1> VDD VSS / ++ RSC_IHPSG13_CBUFX12 +XADDR_COL_DRV<0> ADDR_COL_I<0> ADDR_COL_O<0> VDD VSS / ++ RSC_IHPSG13_CBUFX12 +XADDR_DEC_DRV<7> ADDR_DEC_I<7> ADDR_DEC_O<7> VDD VSS / ++ RSC_IHPSG13_CBUFX12 +XADDR_DEC_DRV<6> ADDR_DEC_I<6> ADDR_DEC_O<6> VDD VSS / ++ RSC_IHPSG13_CBUFX12 +XADDR_DEC_DRV<5> ADDR_DEC_I<5> ADDR_DEC_O<5> VDD VSS / ++ RSC_IHPSG13_CBUFX12 +XADDR_DEC_DRV<4> ADDR_DEC_I<4> ADDR_DEC_O<4> VDD VSS / ++ RSC_IHPSG13_CBUFX12 +XADDR_DEC_DRV<3> ADDR_DEC_I<3> ADDR_DEC_O<3> VDD VSS / ++ RSC_IHPSG13_CBUFX12 +XADDR_DEC_DRV<2> ADDR_DEC_I<2> ADDR_DEC_O<2> VDD VSS / ++ RSC_IHPSG13_CBUFX12 +XADDR_DEC_DRV<1> ADDR_DEC_I<1> ADDR_DEC_O<1> VDD VSS / ++ RSC_IHPSG13_CBUFX12 +XADDR_DEC_DRV<0> ADDR_DEC_I<0> ADDR_DEC_O<0> VDD VSS / ++ RSC_IHPSG13_CBUFX12 +XI0<6> VDD VSS / RSC_IHPSG13_FILLCAP4 +XI0<5> VDD VSS / RSC_IHPSG13_FILLCAP4 +XI0<4> VDD VSS / RSC_IHPSG13_FILLCAP4 +XI0<3> VDD VSS / RSC_IHPSG13_FILLCAP4 +XI0<2> VDD VSS / RSC_IHPSG13_FILLCAP4 +XI0<1> VDD VSS / RSC_IHPSG13_FILLCAP4 +.ENDS +.SUBCKT RSC_IHPSG13_WLDRVX12 A Z VDD VSS +MN1 Z net6 VSS VSS sg13_lv_nmos m=1 w=1.41u l=130.00n ng=2 nrd=0 nrs=0 +MN0 net6 A VSS VSS sg13_lv_nmos m=1 w=1.8u l=130.00n ng=2 nrd=0 nrs=0 +MP1 Z net6 VDD VDD sg13_lv_pmos m=1 w=9.72u l=130.00n ng=6 nrd=0 nrs=0 +MP0 net6 A VDD VDD sg13_lv_pmos m=1 w=900.0n l=130.00n ng=1 nrd=0 nrs=0 +.ENDS +.SUBCKT RM_IHPSG13_256x32_c2_2P_WLDRV16X12 A<15> A<14> A<13> A<12> A<11> A<10> A<9> A<8> ++ A<7> A<6> A<5> A<4> A<3> A<2> A<1> A<0> Z<15> Z<14> Z<13> Z<12> Z<11> Z<10> ++ Z<9> Z<8> Z<7> Z<6> Z<5> Z<4> Z<3> Z<2> Z<1> Z<0> VDD VSS +XBUF<15> A<15> Z<15> VDD VSS / RSC_IHPSG13_WLDRVX12 +XBUF<14> A<14> Z<14> VDD VSS / RSC_IHPSG13_WLDRVX12 +XBUF<13> A<13> Z<13> VDD VSS / RSC_IHPSG13_WLDRVX12 +XBUF<12> A<12> Z<12> VDD VSS / RSC_IHPSG13_WLDRVX12 +XBUF<11> A<11> Z<11> VDD VSS / RSC_IHPSG13_WLDRVX12 +XBUF<10> A<10> Z<10> VDD VSS / RSC_IHPSG13_WLDRVX12 +XBUF<9> A<9> Z<9> VDD VSS / RSC_IHPSG13_WLDRVX12 +XBUF<8> A<8> Z<8> VDD VSS / RSC_IHPSG13_WLDRVX12 +XBUF<7> A<7> Z<7> VDD VSS / RSC_IHPSG13_WLDRVX12 +XBUF<6> A<6> Z<6> VDD VSS / RSC_IHPSG13_WLDRVX12 +XBUF<5> A<5> Z<5> VDD VSS / RSC_IHPSG13_WLDRVX12 +XBUF<4> A<4> Z<4> VDD VSS / RSC_IHPSG13_WLDRVX12 +XBUF<3> A<3> Z<3> VDD VSS / RSC_IHPSG13_WLDRVX12 +XBUF<2> A<2> Z<2> VDD VSS / RSC_IHPSG13_WLDRVX12 +XBUF<1> A<1> Z<1> VDD VSS / RSC_IHPSG13_WLDRVX12 +XBUF<0> A<0> Z<0> VDD VSS / RSC_IHPSG13_WLDRVX12 +.ENDS +.SUBCKT RM_IHPSG13_256x32_c2_2P_DEC04 ADDR<3> ADDR<2> ADDR<1> ADDR<0> CS ECLK_H_BOT ++ ECLK_H_TOP ECLK_L_BOT ECLK_L_TOP WL<15> WL<14> WL<13> WL<12> WL<11> WL<10> ++ WL<9> WL<8> WL<7> WL<6> WL<5> WL<4> WL<3> WL<2> WL<1> WL<0> VDD VSS +XI0<3> PADR<1> PADR<0> sel01<3> VDD VSS / RSC_IHPSG13_NAND2X2 +XI0<2> PADR<1> NADR<0> sel01<2> VDD VSS / RSC_IHPSG13_NAND2X2 +XI0<1> NADR<1> PADR<0> sel01<1> VDD VSS / RSC_IHPSG13_NAND2X2 +XI0<0> NADR<1> NADR<0> sel01<0> VDD VSS / RSC_IHPSG13_NAND2X2 +XI4 ECLK_L_BOT EN VDD VSS / RSC_IHPSG13_CINVX4 +XI5 ECLK_H_BOT ECLK_L_BOT VDD VSS / RSC_IHPSG13_CINVX2 +XI3<3> PADR<3> NADR<3> VDD VSS / RSC_IHPSG13_INVX2 +XI3<2> PADR<2> NADR<2> VDD VSS / RSC_IHPSG13_INVX2 +XI3<1> PADR<1> NADR<1> VDD VSS / RSC_IHPSG13_INVX2 +XI3<0> PADR<0> NADR<0> VDD VSS / RSC_IHPSG13_INVX2 +XR0 ECLK_H_BOT ECLK_H_TOP / RSC_IHPSG13_MET2RES +XI11 ECLK_L_BOT ECLK_L_TOP / RSC_IHPSG13_MET2RES +XI1<3> PADR<2> PADR<3> CS sel23<3> VDD VSS / RSC_IHPSG13_NAND3X2 +XI1<2> NADR<2> PADR<3> CS sel23<2> VDD VSS / RSC_IHPSG13_NAND3X2 +XI1<1> PADR<2> NADR<3> CS sel23<1> VDD VSS / RSC_IHPSG13_NAND3X2 +XI1<0> NADR<2> NADR<3> CS sel23<0> VDD VSS / RSC_IHPSG13_NAND3X2 +XI2<15> sel23<3> sel01<3> EN WL<15> VDD VSS / RSC_IHPSG13_NOR3X2 +XI2<14> sel23<3> sel01<2> EN WL<14> VDD VSS / RSC_IHPSG13_NOR3X2 +XI2<13> sel23<3> sel01<1> EN WL<13> VDD VSS / RSC_IHPSG13_NOR3X2 +XI2<12> sel23<3> sel01<0> EN WL<12> VDD VSS / RSC_IHPSG13_NOR3X2 +XI2<11> sel23<2> sel01<3> EN WL<11> VDD VSS / RSC_IHPSG13_NOR3X2 +XI2<10> sel23<2> sel01<2> EN WL<10> VDD VSS / RSC_IHPSG13_NOR3X2 +XI2<9> sel23<2> sel01<1> EN WL<9> VDD VSS / RSC_IHPSG13_NOR3X2 +XI2<8> sel23<2> sel01<0> EN WL<8> VDD VSS / RSC_IHPSG13_NOR3X2 +XI2<7> sel23<1> sel01<3> EN WL<7> VDD VSS / RSC_IHPSG13_NOR3X2 +XI2<6> sel23<1> sel01<2> EN WL<6> VDD VSS / RSC_IHPSG13_NOR3X2 +XI2<5> sel23<1> sel01<1> EN WL<5> VDD VSS / RSC_IHPSG13_NOR3X2 +XI2<4> sel23<1> sel01<0> EN WL<4> VDD VSS / RSC_IHPSG13_NOR3X2 +XI2<3> sel23<0> sel01<3> EN WL<3> VDD VSS / RSC_IHPSG13_NOR3X2 +XI2<2> sel23<0> sel01<2> EN WL<2> VDD VSS / RSC_IHPSG13_NOR3X2 +XI2<1> sel23<0> sel01<1> EN WL<1> VDD VSS / RSC_IHPSG13_NOR3X2 +XI2<0> sel23<0> sel01<0> EN WL<0> VDD VSS / RSC_IHPSG13_NOR3X2 +XCAPS4 VDD VSS / RSC_IHPSG13_FILLCAP4 +XLATCH<3> CS ADDR<3> PADR<3> VDD VSS / RSC_IHPSG13_LHPQX2 +XLATCH<2> CS ADDR<2> PADR<2> VDD VSS / RSC_IHPSG13_LHPQX2 +XLATCH<1> CS ADDR<1> PADR<1> VDD VSS / RSC_IHPSG13_LHPQX2 +XLATCH<0> CS ADDR<0> PADR<0> VDD VSS / RSC_IHPSG13_LHPQX2 +.ENDS +.SUBCKT RM_IHPSG13_256x32_c2_2P_DEC02 ADDR<1> ADDR<0> CS CS_OUT VDD VSS +XDEC ADDR<1> NADDR<0> CS net1 VDD VSS / RSC_IHPSG13_NAND3X2 +XADDRINV ADDR<0> NADDR<0> VDD VSS / RSC_IHPSG13_INVX2 +XDECINV net1 CS_OUT VDD VSS / RSC_IHPSG13_INVX4 +XI2<1> VDD VSS / RSC_IHPSG13_FILLCAP4 +XI2<0> VDD VSS / RSC_IHPSG13_FILLCAP4 +.ENDS +.SUBCKT RM_IHPSG13_256x32_c2_2P_DEC01 ADDR<1> ADDR<0> CS CS_OUT VDD VSS +XDEC NADDR<1> ADDR<0> CS net1 VDD VSS / RSC_IHPSG13_NAND3X2 +XADDRINV ADDR<1> NADDR<1> VDD VSS / RSC_IHPSG13_INVX2 +XDECINV net1 CS_OUT VDD VSS / RSC_IHPSG13_INVX4 +XI2<1> VDD VSS / RSC_IHPSG13_FILLCAP4 +XI2<0> VDD VSS / RSC_IHPSG13_FILLCAP4 +.ENDS +.SUBCKT RM_IHPSG13_256x32_c2_2P_DEC00 ADDR<1> ADDR<0> CS CS_OUT VDD VSS +XDEC NADDR<1> NADDR<0> CS net1 VDD VSS / RSC_IHPSG13_NAND3X2 +XADDRINV<1> ADDR<1> NADDR<1> VDD VSS / RSC_IHPSG13_INVX2 +XADDRINV<0> ADDR<0> NADDR<0> VDD VSS / RSC_IHPSG13_INVX2 +XI1<1> VDD VSS / RSC_IHPSG13_FILLCAP4 +XI1<0> VDD VSS / RSC_IHPSG13_FILLCAP4 +XDECINV net1 CS_OUT VDD VSS / RSC_IHPSG13_INVX4 +.ENDS +.SUBCKT RM_IHPSG13_256x32_c2_2P_DEC03 ADDR<1> ADDR<0> CS CS_OUT VDD VSS +XDEC ADDR<1> ADDR<0> CS net1 VDD VSS / RSC_IHPSG13_NAND3X2 +XDECINV net1 CS_OUT VDD VSS / RSC_IHPSG13_INVX4 +XI0<1> VDD VSS / RSC_IHPSG13_FILLCAP4 +XI0<0> VDD VSS / RSC_IHPSG13_FILLCAP4 +.ENDS +.SUBCKT RM_IHPSG13_256x32_c2_2P_ROWDEC9 ADDR_N_I<8> ADDR_N_I<7> ADDR_N_I<6> ADDR_N_I<5> ++ ADDR_N_I<4> ADDR_N_I<3> ADDR_N_I<2> ADDR_N_I<1> ADDR_N_I<0> CS_I ECLK_I ++ WL_O<511> WL_O<510> WL_O<509> WL_O<508> WL_O<507> WL_O<506> WL_O<505> ++ WL_O<504> WL_O<503> WL_O<502> WL_O<501> WL_O<500> WL_O<499> WL_O<498> ++ WL_O<497> WL_O<496> WL_O<495> WL_O<494> WL_O<493> WL_O<492> WL_O<491> ++ WL_O<490> WL_O<489> WL_O<488> WL_O<487> WL_O<486> WL_O<485> WL_O<484> ++ WL_O<483> WL_O<482> WL_O<481> WL_O<480> WL_O<479> WL_O<478> WL_O<477> ++ WL_O<476> WL_O<475> WL_O<474> WL_O<473> WL_O<472> WL_O<471> WL_O<470> ++ WL_O<469> WL_O<468> WL_O<467> WL_O<466> WL_O<465> WL_O<464> WL_O<463> ++ WL_O<462> WL_O<461> WL_O<460> WL_O<459> WL_O<458> WL_O<457> WL_O<456> ++ WL_O<455> WL_O<454> WL_O<453> WL_O<452> WL_O<451> WL_O<450> WL_O<449> ++ WL_O<448> WL_O<447> WL_O<446> WL_O<445> WL_O<444> WL_O<443> WL_O<442> ++ WL_O<441> WL_O<440> WL_O<439> WL_O<438> WL_O<437> WL_O<436> WL_O<435> ++ WL_O<434> WL_O<433> WL_O<432> WL_O<431> WL_O<430> WL_O<429> WL_O<428> ++ WL_O<427> WL_O<426> WL_O<425> WL_O<424> WL_O<423> WL_O<422> WL_O<421> ++ WL_O<420> WL_O<419> WL_O<418> WL_O<417> WL_O<416> WL_O<415> WL_O<414> ++ WL_O<413> WL_O<412> WL_O<411> WL_O<410> WL_O<409> WL_O<408> WL_O<407> ++ WL_O<406> WL_O<405> WL_O<404> WL_O<403> WL_O<402> WL_O<401> WL_O<400> ++ WL_O<399> WL_O<398> WL_O<397> WL_O<396> WL_O<395> WL_O<394> WL_O<393> ++ WL_O<392> WL_O<391> WL_O<390> WL_O<389> WL_O<388> WL_O<387> WL_O<386> ++ WL_O<385> WL_O<384> WL_O<383> WL_O<382> WL_O<381> WL_O<380> WL_O<379> ++ WL_O<378> WL_O<377> WL_O<376> WL_O<375> WL_O<374> WL_O<373> WL_O<372> ++ WL_O<371> WL_O<370> WL_O<369> WL_O<368> WL_O<367> WL_O<366> WL_O<365> ++ WL_O<364> WL_O<363> WL_O<362> WL_O<361> WL_O<360> WL_O<359> WL_O<358> ++ WL_O<357> WL_O<356> WL_O<355> WL_O<354> WL_O<353> WL_O<352> WL_O<351> ++ WL_O<350> WL_O<349> WL_O<348> WL_O<347> WL_O<346> WL_O<345> WL_O<344> ++ WL_O<343> WL_O<342> WL_O<341> WL_O<340> WL_O<339> WL_O<338> WL_O<337> ++ WL_O<336> WL_O<335> WL_O<334> WL_O<333> WL_O<332> WL_O<331> WL_O<330> ++ WL_O<329> WL_O<328> WL_O<327> WL_O<326> WL_O<325> WL_O<324> WL_O<323> ++ WL_O<322> WL_O<321> WL_O<320> WL_O<319> WL_O<318> WL_O<317> WL_O<316> ++ WL_O<315> WL_O<314> WL_O<313> WL_O<312> WL_O<311> WL_O<310> WL_O<309> ++ WL_O<308> WL_O<307> WL_O<306> WL_O<305> WL_O<304> WL_O<303> WL_O<302> ++ WL_O<301> WL_O<300> WL_O<299> WL_O<298> WL_O<297> WL_O<296> WL_O<295> ++ WL_O<294> WL_O<293> WL_O<292> WL_O<291> WL_O<290> WL_O<289> WL_O<288> ++ WL_O<287> WL_O<286> WL_O<285> WL_O<284> WL_O<283> WL_O<282> WL_O<281> ++ WL_O<280> WL_O<279> WL_O<278> WL_O<277> WL_O<276> WL_O<275> WL_O<274> ++ WL_O<273> WL_O<272> WL_O<271> WL_O<270> WL_O<269> WL_O<268> WL_O<267> ++ WL_O<266> WL_O<265> WL_O<264> WL_O<263> WL_O<262> WL_O<261> WL_O<260> ++ WL_O<259> WL_O<258> WL_O<257> WL_O<256> WL_O<255> WL_O<254> WL_O<253> ++ WL_O<252> WL_O<251> WL_O<250> WL_O<249> WL_O<248> WL_O<247> WL_O<246> ++ WL_O<245> WL_O<244> WL_O<243> WL_O<242> WL_O<241> WL_O<240> WL_O<239> ++ WL_O<238> WL_O<237> WL_O<236> WL_O<235> WL_O<234> WL_O<233> WL_O<232> ++ WL_O<231> WL_O<230> WL_O<229> WL_O<228> WL_O<227> WL_O<226> WL_O<225> ++ WL_O<224> WL_O<223> WL_O<222> WL_O<221> WL_O<220> WL_O<219> WL_O<218> ++ WL_O<217> WL_O<216> WL_O<215> WL_O<214> WL_O<213> WL_O<212> WL_O<211> ++ WL_O<210> WL_O<209> WL_O<208> WL_O<207> WL_O<206> WL_O<205> WL_O<204> ++ WL_O<203> WL_O<202> WL_O<201> WL_O<200> WL_O<199> WL_O<198> WL_O<197> ++ WL_O<196> WL_O<195> WL_O<194> WL_O<193> WL_O<192> WL_O<191> WL_O<190> ++ WL_O<189> WL_O<188> WL_O<187> WL_O<186> WL_O<185> WL_O<184> WL_O<183> ++ WL_O<182> WL_O<181> WL_O<180> WL_O<179> WL_O<178> WL_O<177> WL_O<176> ++ WL_O<175> WL_O<174> WL_O<173> WL_O<172> WL_O<171> WL_O<170> WL_O<169> ++ WL_O<168> WL_O<167> WL_O<166> WL_O<165> WL_O<164> WL_O<163> WL_O<162> ++ WL_O<161> WL_O<160> WL_O<159> WL_O<158> WL_O<157> WL_O<156> WL_O<155> ++ WL_O<154> WL_O<153> WL_O<152> WL_O<151> WL_O<150> WL_O<149> WL_O<148> ++ WL_O<147> WL_O<146> WL_O<145> WL_O<144> WL_O<143> WL_O<142> WL_O<141> ++ WL_O<140> WL_O<139> WL_O<138> WL_O<137> WL_O<136> WL_O<135> WL_O<134> ++ WL_O<133> WL_O<132> WL_O<131> WL_O<130> WL_O<129> WL_O<128> WL_O<127> ++ WL_O<126> WL_O<125> WL_O<124> WL_O<123> WL_O<122> WL_O<121> WL_O<120> ++ WL_O<119> WL_O<118> WL_O<117> WL_O<116> WL_O<115> WL_O<114> WL_O<113> ++ WL_O<112> WL_O<111> WL_O<110> WL_O<109> WL_O<108> WL_O<107> WL_O<106> ++ WL_O<105> WL_O<104> WL_O<103> WL_O<102> WL_O<101> WL_O<100> WL_O<99> ++ WL_O<98> WL_O<97> WL_O<96> WL_O<95> WL_O<94> WL_O<93> WL_O<92> WL_O<91> ++ WL_O<90> WL_O<89> WL_O<88> WL_O<87> WL_O<86> WL_O<85> WL_O<84> WL_O<83> ++ WL_O<82> WL_O<81> WL_O<80> WL_O<79> WL_O<78> WL_O<77> WL_O<76> WL_O<75> ++ WL_O<74> WL_O<73> WL_O<72> WL_O<71> WL_O<70> WL_O<69> WL_O<68> WL_O<67> ++ WL_O<66> WL_O<65> WL_O<64> WL_O<63> WL_O<62> WL_O<61> WL_O<60> WL_O<59> ++ WL_O<58> WL_O<57> WL_O<56> WL_O<55> WL_O<54> WL_O<53> WL_O<52> WL_O<51> ++ WL_O<50> WL_O<49> WL_O<48> WL_O<47> WL_O<46> WL_O<45> WL_O<44> WL_O<43> ++ WL_O<42> WL_O<41> WL_O<40> WL_O<39> WL_O<38> WL_O<37> WL_O<36> WL_O<35> ++ WL_O<34> WL_O<33> WL_O<32> WL_O<31> WL_O<30> WL_O<29> WL_O<28> WL_O<27> ++ WL_O<26> WL_O<25> WL_O<24> WL_O<23> WL_O<22> WL_O<21> WL_O<20> WL_O<19> ++ WL_O<18> WL_O<17> WL_O<16> WL_O<15> WL_O<14> WL_O<13> WL_O<12> WL_O<11> ++ WL_O<10> WL_O<9> WL_O<8> WL_O<7> WL_O<6> WL_O<5> WL_O<4> WL_O<3> WL_O<2> ++ WL_O<1> WL_O<0> VDD VSS +XSEL<31> ADDR_N_I<3> ADDR_N_I<2> ADDR_N_I<1> ADDR_N_I<0> CS00<31> ECLK_H<31> ++ ECLK_H<32> ECLK_B<31> ECLK_B<32> WL_O<511> WL_O<510> WL_O<509> WL_O<508> ++ WL_O<507> WL_O<506> WL_O<505> WL_O<504> WL_O<503> WL_O<502> WL_O<501> ++ WL_O<500> WL_O<499> WL_O<498> WL_O<497> WL_O<496> VDD VSS / ++ RM_IHPSG13_256x32_c2_2P_DEC04 +XSEL<30> ADDR_N_I<3> ADDR_N_I<2> ADDR_N_I<1> ADDR_N_I<0> CS00<30> ECLK_H<30> ++ ECLK_H<31> ECLK_B<30> ECLK_B<31> WL_O<495> WL_O<494> WL_O<493> WL_O<492> ++ WL_O<491> WL_O<490> WL_O<489> WL_O<488> WL_O<487> WL_O<486> WL_O<485> ++ WL_O<484> WL_O<483> WL_O<482> WL_O<481> WL_O<480> VDD VSS / ++ RM_IHPSG13_256x32_c2_2P_DEC04 +XSEL<29> ADDR_N_I<3> ADDR_N_I<2> ADDR_N_I<1> ADDR_N_I<0> CS00<29> ECLK_H<29> ++ ECLK_H<30> ECLK_B<29> ECLK_B<30> WL_O<479> WL_O<478> WL_O<477> WL_O<476> ++ WL_O<475> WL_O<474> WL_O<473> WL_O<472> WL_O<471> WL_O<470> WL_O<469> ++ WL_O<468> WL_O<467> WL_O<466> WL_O<465> WL_O<464> VDD VSS / ++ RM_IHPSG13_256x32_c2_2P_DEC04 +XSEL<28> ADDR_N_I<3> ADDR_N_I<2> ADDR_N_I<1> ADDR_N_I<0> CS00<28> ECLK_H<28> ++ ECLK_H<29> ECLK_B<28> ECLK_B<29> WL_O<463> WL_O<462> WL_O<461> WL_O<460> ++ WL_O<459> WL_O<458> WL_O<457> WL_O<456> WL_O<455> WL_O<454> WL_O<453> ++ WL_O<452> WL_O<451> WL_O<450> WL_O<449> WL_O<448> VDD VSS / ++ RM_IHPSG13_256x32_c2_2P_DEC04 +XSEL<27> ADDR_N_I<3> ADDR_N_I<2> ADDR_N_I<1> ADDR_N_I<0> CS00<27> ECLK_H<27> ++ ECLK_H<28> ECLK_B<27> ECLK_B<28> WL_O<447> WL_O<446> WL_O<445> WL_O<444> ++ WL_O<443> WL_O<442> WL_O<441> WL_O<440> WL_O<439> WL_O<438> WL_O<437> ++ WL_O<436> WL_O<435> WL_O<434> WL_O<433> WL_O<432> VDD VSS / ++ RM_IHPSG13_256x32_c2_2P_DEC04 +XSEL<26> ADDR_N_I<3> ADDR_N_I<2> ADDR_N_I<1> ADDR_N_I<0> CS00<26> ECLK_H<26> ++ ECLK_H<27> ECLK_B<26> ECLK_B<27> WL_O<431> WL_O<430> WL_O<429> WL_O<428> ++ WL_O<427> WL_O<426> WL_O<425> WL_O<424> WL_O<423> WL_O<422> WL_O<421> ++ WL_O<420> WL_O<419> WL_O<418> WL_O<417> WL_O<416> VDD VSS / ++ RM_IHPSG13_256x32_c2_2P_DEC04 +XSEL<25> ADDR_N_I<3> ADDR_N_I<2> ADDR_N_I<1> ADDR_N_I<0> CS00<25> ECLK_H<25> ++ ECLK_H<26> ECLK_B<25> ECLK_B<26> WL_O<415> WL_O<414> WL_O<413> WL_O<412> ++ WL_O<411> WL_O<410> WL_O<409> WL_O<408> WL_O<407> WL_O<406> WL_O<405> ++ WL_O<404> WL_O<403> WL_O<402> WL_O<401> WL_O<400> VDD VSS / ++ RM_IHPSG13_256x32_c2_2P_DEC04 +XSEL<24> ADDR_N_I<3> ADDR_N_I<2> ADDR_N_I<1> ADDR_N_I<0> CS00<24> ECLK_H<24> ++ ECLK_H<25> ECLK_B<24> ECLK_B<25> WL_O<399> WL_O<398> WL_O<397> WL_O<396> ++ WL_O<395> WL_O<394> WL_O<393> WL_O<392> WL_O<391> WL_O<390> WL_O<389> ++ WL_O<388> WL_O<387> WL_O<386> WL_O<385> WL_O<384> VDD VSS / ++ RM_IHPSG13_256x32_c2_2P_DEC04 +XSEL<23> ADDR_N_I<3> ADDR_N_I<2> ADDR_N_I<1> ADDR_N_I<0> CS00<23> ECLK_H<23> ++ ECLK_H<24> ECLK_B<23> ECLK_B<24> WL_O<383> WL_O<382> WL_O<381> WL_O<380> ++ WL_O<379> WL_O<378> WL_O<377> WL_O<376> WL_O<375> WL_O<374> WL_O<373> ++ WL_O<372> WL_O<371> WL_O<370> WL_O<369> WL_O<368> VDD VSS / ++ RM_IHPSG13_256x32_c2_2P_DEC04 +XSEL<22> ADDR_N_I<3> ADDR_N_I<2> ADDR_N_I<1> ADDR_N_I<0> CS00<22> ECLK_H<22> ++ ECLK_H<23> ECLK_B<22> ECLK_B<23> WL_O<367> WL_O<366> WL_O<365> WL_O<364> ++ WL_O<363> WL_O<362> WL_O<361> WL_O<360> WL_O<359> WL_O<358> WL_O<357> ++ WL_O<356> WL_O<355> WL_O<354> WL_O<353> WL_O<352> VDD VSS / ++ RM_IHPSG13_256x32_c2_2P_DEC04 +XSEL<21> ADDR_N_I<3> ADDR_N_I<2> ADDR_N_I<1> ADDR_N_I<0> CS00<21> ECLK_H<21> ++ ECLK_H<22> ECLK_B<21> ECLK_B<22> WL_O<351> WL_O<350> WL_O<349> WL_O<348> ++ WL_O<347> WL_O<346> WL_O<345> WL_O<344> WL_O<343> WL_O<342> WL_O<341> ++ WL_O<340> WL_O<339> WL_O<338> WL_O<337> WL_O<336> VDD VSS / ++ RM_IHPSG13_256x32_c2_2P_DEC04 +XSEL<20> ADDR_N_I<3> ADDR_N_I<2> ADDR_N_I<1> ADDR_N_I<0> CS00<20> ECLK_H<20> ++ ECLK_H<21> ECLK_B<20> ECLK_B<21> WL_O<335> WL_O<334> WL_O<333> WL_O<332> ++ WL_O<331> WL_O<330> WL_O<329> WL_O<328> WL_O<327> WL_O<326> WL_O<325> ++ WL_O<324> WL_O<323> WL_O<322> WL_O<321> WL_O<320> VDD VSS / ++ RM_IHPSG13_256x32_c2_2P_DEC04 +XSEL<19> ADDR_N_I<3> ADDR_N_I<2> ADDR_N_I<1> ADDR_N_I<0> CS00<19> ECLK_H<19> ++ ECLK_H<20> ECLK_B<19> ECLK_B<20> WL_O<319> WL_O<318> WL_O<317> WL_O<316> ++ WL_O<315> WL_O<314> WL_O<313> WL_O<312> WL_O<311> WL_O<310> WL_O<309> ++ WL_O<308> WL_O<307> WL_O<306> WL_O<305> WL_O<304> VDD VSS / ++ RM_IHPSG13_256x32_c2_2P_DEC04 +XSEL<18> ADDR_N_I<3> ADDR_N_I<2> ADDR_N_I<1> ADDR_N_I<0> CS00<18> ECLK_H<18> ++ ECLK_H<19> ECLK_B<18> ECLK_B<19> WL_O<303> WL_O<302> WL_O<301> WL_O<300> ++ WL_O<299> WL_O<298> WL_O<297> WL_O<296> WL_O<295> WL_O<294> WL_O<293> ++ WL_O<292> WL_O<291> WL_O<290> WL_O<289> WL_O<288> VDD VSS / ++ RM_IHPSG13_256x32_c2_2P_DEC04 +XSEL<17> ADDR_N_I<3> ADDR_N_I<2> ADDR_N_I<1> ADDR_N_I<0> CS00<17> ECLK_H<17> ++ ECLK_H<18> ECLK_B<17> ECLK_B<18> WL_O<287> WL_O<286> WL_O<285> WL_O<284> ++ WL_O<283> WL_O<282> WL_O<281> WL_O<280> WL_O<279> WL_O<278> WL_O<277> ++ WL_O<276> WL_O<275> WL_O<274> WL_O<273> WL_O<272> VDD VSS / ++ RM_IHPSG13_256x32_c2_2P_DEC04 +XSEL<16> ADDR_N_I<3> ADDR_N_I<2> ADDR_N_I<1> ADDR_N_I<0> CS00<16> ECLK_H<16> ++ ECLK_H<17> ECLK_B<16> ECLK_B<17> WL_O<271> WL_O<270> WL_O<269> WL_O<268> ++ WL_O<267> WL_O<266> WL_O<265> WL_O<264> WL_O<263> WL_O<262> WL_O<261> ++ WL_O<260> WL_O<259> WL_O<258> WL_O<257> WL_O<256> VDD VSS / ++ RM_IHPSG13_256x32_c2_2P_DEC04 +XSEL<15> ADDR_N_I<3> ADDR_N_I<2> ADDR_N_I<1> ADDR_N_I<0> CS00<15> ECLK_H<15> ++ ECLK_H<16> ECLK_B<15> ECLK_B<16> WL_O<255> WL_O<254> WL_O<253> WL_O<252> ++ WL_O<251> WL_O<250> WL_O<249> WL_O<248> WL_O<247> WL_O<246> WL_O<245> ++ WL_O<244> WL_O<243> WL_O<242> WL_O<241> WL_O<240> VDD VSS / ++ RM_IHPSG13_256x32_c2_2P_DEC04 +XSEL<14> ADDR_N_I<3> ADDR_N_I<2> ADDR_N_I<1> ADDR_N_I<0> CS00<14> ECLK_H<14> ++ ECLK_H<15> ECLK_B<14> ECLK_B<15> WL_O<239> WL_O<238> WL_O<237> WL_O<236> ++ WL_O<235> WL_O<234> WL_O<233> WL_O<232> WL_O<231> WL_O<230> WL_O<229> ++ WL_O<228> WL_O<227> WL_O<226> WL_O<225> WL_O<224> VDD VSS / ++ RM_IHPSG13_256x32_c2_2P_DEC04 +XSEL<13> ADDR_N_I<3> ADDR_N_I<2> ADDR_N_I<1> ADDR_N_I<0> CS00<13> ECLK_H<13> ++ ECLK_H<14> ECLK_B<13> ECLK_B<14> WL_O<223> WL_O<222> WL_O<221> WL_O<220> ++ WL_O<219> WL_O<218> WL_O<217> WL_O<216> WL_O<215> WL_O<214> WL_O<213> ++ WL_O<212> WL_O<211> WL_O<210> WL_O<209> WL_O<208> VDD VSS / ++ RM_IHPSG13_256x32_c2_2P_DEC04 +XSEL<12> ADDR_N_I<3> ADDR_N_I<2> ADDR_N_I<1> ADDR_N_I<0> CS00<12> ECLK_H<12> ++ ECLK_H<13> ECLK_B<12> ECLK_B<13> WL_O<207> WL_O<206> WL_O<205> WL_O<204> ++ WL_O<203> WL_O<202> WL_O<201> WL_O<200> WL_O<199> WL_O<198> WL_O<197> ++ WL_O<196> WL_O<195> WL_O<194> WL_O<193> WL_O<192> VDD VSS / ++ RM_IHPSG13_256x32_c2_2P_DEC04 +XSEL<11> ADDR_N_I<3> ADDR_N_I<2> ADDR_N_I<1> ADDR_N_I<0> CS00<11> ECLK_H<11> ++ ECLK_H<12> ECLK_B<11> ECLK_B<12> WL_O<191> WL_O<190> WL_O<189> WL_O<188> ++ WL_O<187> WL_O<186> WL_O<185> WL_O<184> WL_O<183> WL_O<182> WL_O<181> ++ WL_O<180> WL_O<179> WL_O<178> WL_O<177> WL_O<176> VDD VSS / ++ RM_IHPSG13_256x32_c2_2P_DEC04 +XSEL<10> ADDR_N_I<3> ADDR_N_I<2> ADDR_N_I<1> ADDR_N_I<0> CS00<10> ECLK_H<10> ++ ECLK_H<11> ECLK_B<10> ECLK_B<11> WL_O<175> WL_O<174> WL_O<173> WL_O<172> ++ WL_O<171> WL_O<170> WL_O<169> WL_O<168> WL_O<167> WL_O<166> WL_O<165> ++ WL_O<164> WL_O<163> WL_O<162> WL_O<161> WL_O<160> VDD VSS / ++ RM_IHPSG13_256x32_c2_2P_DEC04 +XSEL<9> ADDR_N_I<3> ADDR_N_I<2> ADDR_N_I<1> ADDR_N_I<0> CS00<9> ECLK_H<9> ++ ECLK_H<10> ECLK_B<9> ECLK_B<10> WL_O<159> WL_O<158> WL_O<157> WL_O<156> ++ WL_O<155> WL_O<154> WL_O<153> WL_O<152> WL_O<151> WL_O<150> WL_O<149> ++ WL_O<148> WL_O<147> WL_O<146> WL_O<145> WL_O<144> VDD VSS / ++ RM_IHPSG13_256x32_c2_2P_DEC04 +XSEL<8> ADDR_N_I<3> ADDR_N_I<2> ADDR_N_I<1> ADDR_N_I<0> CS00<8> ECLK_H<8> ++ ECLK_H<9> ECLK_B<8> ECLK_B<9> WL_O<143> WL_O<142> WL_O<141> WL_O<140> ++ WL_O<139> WL_O<138> WL_O<137> WL_O<136> WL_O<135> WL_O<134> WL_O<133> ++ WL_O<132> WL_O<131> WL_O<130> WL_O<129> WL_O<128> VDD VSS / ++ RM_IHPSG13_256x32_c2_2P_DEC04 +XSEL<7> ADDR_N_I<3> ADDR_N_I<2> ADDR_N_I<1> ADDR_N_I<0> CS00<7> ECLK_H<7> ++ ECLK_H<8> ECLK_B<7> ECLK_B<8> WL_O<127> WL_O<126> WL_O<125> WL_O<124> ++ WL_O<123> WL_O<122> WL_O<121> WL_O<120> WL_O<119> WL_O<118> WL_O<117> ++ WL_O<116> WL_O<115> WL_O<114> WL_O<113> WL_O<112> VDD VSS / ++ RM_IHPSG13_256x32_c2_2P_DEC04 +XSEL<6> ADDR_N_I<3> ADDR_N_I<2> ADDR_N_I<1> ADDR_N_I<0> CS00<6> ECLK_H<6> ++ ECLK_H<7> ECLK_B<6> ECLK_B<7> WL_O<111> WL_O<110> WL_O<109> WL_O<108> ++ WL_O<107> WL_O<106> WL_O<105> WL_O<104> WL_O<103> WL_O<102> WL_O<101> ++ WL_O<100> WL_O<99> WL_O<98> WL_O<97> WL_O<96> VDD VSS / ++ RM_IHPSG13_256x32_c2_2P_DEC04 +XSEL<5> ADDR_N_I<3> ADDR_N_I<2> ADDR_N_I<1> ADDR_N_I<0> CS00<5> ECLK_H<5> ++ ECLK_H<6> ECLK_B<5> ECLK_B<6> WL_O<95> WL_O<94> WL_O<93> WL_O<92> WL_O<91> ++ WL_O<90> WL_O<89> WL_O<88> WL_O<87> WL_O<86> WL_O<85> WL_O<84> WL_O<83> ++ WL_O<82> WL_O<81> WL_O<80> VDD VSS / RM_IHPSG13_256x32_c2_2P_DEC04 +XSEL<4> ADDR_N_I<3> ADDR_N_I<2> ADDR_N_I<1> ADDR_N_I<0> CS00<4> ECLK_H<4> ++ ECLK_H<5> ECLK_B<4> ECLK_B<5> WL_O<79> WL_O<78> WL_O<77> WL_O<76> WL_O<75> ++ WL_O<74> WL_O<73> WL_O<72> WL_O<71> WL_O<70> WL_O<69> WL_O<68> WL_O<67> ++ WL_O<66> WL_O<65> WL_O<64> VDD VSS / RM_IHPSG13_256x32_c2_2P_DEC04 +XSEL<3> ADDR_N_I<3> ADDR_N_I<2> ADDR_N_I<1> ADDR_N_I<0> CS00<3> ECLK_H<3> ++ ECLK_H<4> ECLK_B<3> ECLK_B<4> WL_O<63> WL_O<62> WL_O<61> WL_O<60> WL_O<59> ++ WL_O<58> WL_O<57> WL_O<56> WL_O<55> WL_O<54> WL_O<53> WL_O<52> WL_O<51> ++ WL_O<50> WL_O<49> WL_O<48> VDD VSS / RM_IHPSG13_256x32_c2_2P_DEC04 +XSEL<2> ADDR_N_I<3> ADDR_N_I<2> ADDR_N_I<1> ADDR_N_I<0> CS00<2> ECLK_H<2> ++ ECLK_H<3> ECLK_B<2> ECLK_B<3> WL_O<47> WL_O<46> WL_O<45> WL_O<44> WL_O<43> ++ WL_O<42> WL_O<41> WL_O<40> WL_O<39> WL_O<38> WL_O<37> WL_O<36> WL_O<35> ++ WL_O<34> WL_O<33> WL_O<32> VDD VSS / RM_IHPSG13_256x32_c2_2P_DEC04 +XSEL<1> ADDR_N_I<3> ADDR_N_I<2> ADDR_N_I<1> ADDR_N_I<0> CS00<1> ECLK_H<1> ++ ECLK_H<2> ECLK_B<1> ECLK_B<2> WL_O<31> WL_O<30> WL_O<29> WL_O<28> WL_O<27> ++ WL_O<26> WL_O<25> WL_O<24> WL_O<23> WL_O<22> WL_O<21> WL_O<20> WL_O<19> ++ WL_O<18> WL_O<17> WL_O<16> VDD VSS / RM_IHPSG13_256x32_c2_2P_DEC04 +XSEL<0> ADDR_N_I<3> ADDR_N_I<2> ADDR_N_I<1> ADDR_N_I<0> CS00<0> ECLK_I ++ ECLK_H<1> ECLK_B<0> ECLK_B<1> WL_O<15> WL_O<14> WL_O<13> WL_O<12> WL_O<11> ++ WL_O<10> WL_O<9> WL_O<8> WL_O<7> WL_O<6> WL_O<5> WL_O<4> WL_O<3> WL_O<2> ++ WL_O<1> WL_O<0> VDD VSS / RM_IHPSG13_256x32_c2_2P_DEC04 +XDEC10<9> ADDR_N_I<7> ADDR_N_I<6> CS04<1> CS02<6> VDD VSS / ++ RM_IHPSG13_256x32_c2_2P_DEC02 +XDEC10<8> ADDR_N_I<7> ADDR_N_I<6> CS04<0> CS02<2> VDD VSS / ++ RM_IHPSG13_256x32_c2_2P_DEC02 +XDEC10<7> ADDR_N_I<5> ADDR_N_I<4> CS02<7> CS00<30> VDD VSS / ++ RM_IHPSG13_256x32_c2_2P_DEC02 +XDEC10<6> ADDR_N_I<5> ADDR_N_I<4> CS02<6> CS00<26> VDD VSS / ++ RM_IHPSG13_256x32_c2_2P_DEC02 +XDEC10<5> ADDR_N_I<5> ADDR_N_I<4> CS02<5> CS00<22> VDD VSS / ++ RM_IHPSG13_256x32_c2_2P_DEC02 +XDEC10<4> ADDR_N_I<5> ADDR_N_I<4> CS02<4> CS00<18> VDD VSS / ++ RM_IHPSG13_256x32_c2_2P_DEC02 +XDEC10<3> ADDR_N_I<5> ADDR_N_I<4> CS02<3> CS00<14> VDD VSS / ++ RM_IHPSG13_256x32_c2_2P_DEC02 +XDEC10<2> ADDR_N_I<5> ADDR_N_I<4> CS02<2> CS00<10> VDD VSS / ++ RM_IHPSG13_256x32_c2_2P_DEC02 +XDEC10<1> ADDR_N_I<5> ADDR_N_I<4> CS02<1> CS00<6> VDD VSS / ++ RM_IHPSG13_256x32_c2_2P_DEC02 +XDEC10<0> ADDR_N_I<5> ADDR_N_I<4> CS02<0> CS00<2> VDD VSS / ++ RM_IHPSG13_256x32_c2_2P_DEC02 +XDEC01<10> ADDR_N_I<9> ADDR_N_I<8> CS_I CS04<1> VDD VSS / ++ RM_IHPSG13_256x32_c2_2P_DEC01 +XDEC01<9> ADDR_N_I<7> ADDR_N_I<6> CS04<1> CS02<5> VDD VSS / ++ RM_IHPSG13_256x32_c2_2P_DEC01 +XDEC01<8> ADDR_N_I<7> ADDR_N_I<6> CS04<0> CS02<1> VDD VSS / ++ RM_IHPSG13_256x32_c2_2P_DEC01 +XDEC01<7> ADDR_N_I<5> ADDR_N_I<4> CS02<7> CS00<29> VDD VSS / ++ RM_IHPSG13_256x32_c2_2P_DEC01 +XDEC01<6> ADDR_N_I<5> ADDR_N_I<4> CS02<6> CS00<25> VDD VSS / ++ RM_IHPSG13_256x32_c2_2P_DEC01 +XDEC01<5> ADDR_N_I<5> ADDR_N_I<4> CS02<5> CS00<21> VDD VSS / ++ RM_IHPSG13_256x32_c2_2P_DEC01 +XDEC01<4> ADDR_N_I<5> ADDR_N_I<4> CS02<4> CS00<17> VDD VSS / ++ RM_IHPSG13_256x32_c2_2P_DEC01 +XDEC01<3> ADDR_N_I<5> ADDR_N_I<4> CS02<3> CS00<13> VDD VSS / ++ RM_IHPSG13_256x32_c2_2P_DEC01 +XDEC01<2> ADDR_N_I<5> ADDR_N_I<4> CS02<2> CS00<9> VDD VSS / ++ RM_IHPSG13_256x32_c2_2P_DEC01 +XDEC01<1> ADDR_N_I<5> ADDR_N_I<4> CS02<1> CS00<5> VDD VSS / ++ RM_IHPSG13_256x32_c2_2P_DEC01 +XDEC01<0> ADDR_N_I<5> ADDR_N_I<4> CS02<0> CS00<1> VDD VSS / ++ RM_IHPSG13_256x32_c2_2P_DEC01 +XL2<258> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<257> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<256> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<255> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<254> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<253> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<252> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<251> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<250> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<249> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<248> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<247> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<246> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<245> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<244> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<243> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<242> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<241> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<240> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<239> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<238> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<237> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<236> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<235> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<234> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<233> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<232> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<231> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<230> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<229> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<228> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<227> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<226> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<225> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<224> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<223> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<222> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<221> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<220> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<219> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<218> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<217> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<216> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<215> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<214> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<213> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<212> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<211> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<210> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<209> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<208> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<207> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<206> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<205> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<204> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<203> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<202> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<201> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<200> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<199> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<198> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<197> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<196> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<195> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<194> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<193> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<192> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<191> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<190> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<189> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<188> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<187> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<186> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<185> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<184> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<183> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<182> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<181> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<180> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<179> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<178> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<177> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<176> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<175> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<174> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<173> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<172> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<171> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<170> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<169> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<168> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<167> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<166> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<165> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<164> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<163> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<162> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<161> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<160> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<159> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<158> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<157> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<156> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<155> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<154> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<153> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<152> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<151> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<150> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<149> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<148> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<147> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<146> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<145> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<144> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<143> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<142> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<141> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<140> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<139> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<138> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<137> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<136> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<135> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<134> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<133> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<132> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<131> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<130> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<129> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<128> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<127> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<126> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<125> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<124> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<123> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<122> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<121> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<120> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<119> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<118> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<117> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<116> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<115> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<114> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<113> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<112> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<111> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<110> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<109> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<108> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<107> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<106> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<105> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<104> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<103> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<102> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<101> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<100> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<99> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<98> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<97> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<96> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<95> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<94> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<93> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<92> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<91> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<90> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<89> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<88> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<87> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<86> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<85> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<84> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<83> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<82> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<81> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<80> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<79> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<78> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<77> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<76> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<75> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<74> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<73> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<72> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<71> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<70> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<69> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<68> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<67> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<66> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<65> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<64> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<63> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<62> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<61> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<60> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<59> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<58> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<57> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<56> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<55> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<54> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<53> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<52> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<51> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<50> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<49> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<48> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<47> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<46> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<45> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<44> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<43> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<42> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<41> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<40> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<39> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<38> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<37> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<36> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<35> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<34> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<33> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<32> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<31> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<30> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<29> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<28> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<27> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<26> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<25> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<24> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<23> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<22> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<21> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<20> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<19> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<18> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<17> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<16> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<15> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<14> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<13> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<12> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<11> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<10> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<9> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<8> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<7> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<6> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<5> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<4> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<3> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<2> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<1> VDD VSS / RSC_IHPSG13_FILLCAP8 +XDEC00<10> ADDR_N_I<9> ADDR_N_I<8> CS_I CS04<0> VDD VSS / ++ RM_IHPSG13_256x32_c2_2P_DEC00 +XDEC00<9> ADDR_N_I<7> ADDR_N_I<6> CS04<1> CS02<4> VDD VSS / ++ RM_IHPSG13_256x32_c2_2P_DEC00 +XDEC00<8> ADDR_N_I<7> ADDR_N_I<6> CS04<0> CS02<0> VDD VSS / ++ RM_IHPSG13_256x32_c2_2P_DEC00 +XDEC00<7> ADDR_N_I<5> ADDR_N_I<4> CS02<7> CS00<28> VDD VSS / ++ RM_IHPSG13_256x32_c2_2P_DEC00 +XDEC00<6> ADDR_N_I<5> ADDR_N_I<4> CS02<6> CS00<24> VDD VSS / ++ RM_IHPSG13_256x32_c2_2P_DEC00 +XDEC00<5> ADDR_N_I<5> ADDR_N_I<4> CS02<5> CS00<20> VDD VSS / ++ RM_IHPSG13_256x32_c2_2P_DEC00 +XDEC00<4> ADDR_N_I<5> ADDR_N_I<4> CS02<4> CS00<16> VDD VSS / ++ RM_IHPSG13_256x32_c2_2P_DEC00 +XDEC00<3> ADDR_N_I<5> ADDR_N_I<4> CS02<3> CS00<12> VDD VSS / ++ RM_IHPSG13_256x32_c2_2P_DEC00 +XDEC00<2> ADDR_N_I<5> ADDR_N_I<4> CS02<2> CS00<8> VDD VSS / ++ RM_IHPSG13_256x32_c2_2P_DEC00 +XDEC00<1> ADDR_N_I<5> ADDR_N_I<4> CS02<1> CS00<4> VDD VSS / ++ RM_IHPSG13_256x32_c2_2P_DEC00 +XDEC00<0> ADDR_N_I<5> ADDR_N_I<4> CS02<0> CS00<0> VDD VSS / ++ RM_IHPSG13_256x32_c2_2P_DEC00 +XDEC11<9> ADDR_N_I<7> ADDR_N_I<6> CS04<1> CS02<7> VDD VSS / ++ RM_IHPSG13_256x32_c2_2P_DEC03 +XDEC11<8> ADDR_N_I<7> ADDR_N_I<6> CS04<0> CS02<3> VDD VSS / ++ RM_IHPSG13_256x32_c2_2P_DEC03 +XDEC11<7> ADDR_N_I<5> ADDR_N_I<4> CS02<7> CS00<31> VDD VSS / ++ RM_IHPSG13_256x32_c2_2P_DEC03 +XDEC11<6> ADDR_N_I<5> ADDR_N_I<4> CS02<6> CS00<27> VDD VSS / ++ RM_IHPSG13_256x32_c2_2P_DEC03 +XDEC11<5> ADDR_N_I<5> ADDR_N_I<4> CS02<5> CS00<23> VDD VSS / ++ RM_IHPSG13_256x32_c2_2P_DEC03 +XDEC11<4> ADDR_N_I<5> ADDR_N_I<4> CS02<4> CS00<19> VDD VSS / ++ RM_IHPSG13_256x32_c2_2P_DEC03 +XDEC11<3> ADDR_N_I<5> ADDR_N_I<4> CS02<3> CS00<15> VDD VSS / ++ RM_IHPSG13_256x32_c2_2P_DEC03 +XDEC11<2> ADDR_N_I<5> ADDR_N_I<4> CS02<2> CS00<11> VDD VSS / ++ RM_IHPSG13_256x32_c2_2P_DEC03 +XDEC11<1> ADDR_N_I<5> ADDR_N_I<4> CS02<1> CS00<7> VDD VSS / ++ RM_IHPSG13_256x32_c2_2P_DEC03 +XDEC11<0> ADDR_N_I<5> ADDR_N_I<4> CS02<0> CS00<3> VDD VSS / ++ RM_IHPSG13_256x32_c2_2P_DEC03 +XI0 ADDR_N_I<9> VDD VSS / RSC_IHPSG13_TIEL +.ENDS +.SUBCKT RM_IHPSG13_256x32_c2_2P_ROWREG9 ACLK_N_I ADDR_I<8> ADDR_I<7> ADDR_I<6> ADDR_I<5> ++ ADDR_I<4> ADDR_I<3> ADDR_I<2> ADDR_I<1> ADDR_I<0> ADDR_N_O<8> ADDR_N_O<7> ++ ADDR_N_O<6> ADDR_N_O<5> ADDR_N_O<4> ADDR_N_O<3> ADDR_N_O<2> ADDR_N_O<1> ++ ADDR_N_O<0> BIST_ADDR_I<8> BIST_ADDR_I<7> BIST_ADDR_I<6> BIST_ADDR_I<5> ++ BIST_ADDR_I<4> BIST_ADDR_I<3> BIST_ADDR_I<2> BIST_ADDR_I<1> BIST_ADDR_I<0> ++ BIST_EN_I VDD VSS +XDFF<8> BIST_EN_I BIST_ADDR_I<8> ACLK_N_I ADDR_I<8> q_int<8> net04<0> VDD ++ VSS / RSC_IHPSG13_DFNQMX2IX1 +XDFF<7> BIST_EN_I BIST_ADDR_I<7> ACLK_N_I ADDR_I<7> q_int<7> net04<1> VDD ++ VSS / RSC_IHPSG13_DFNQMX2IX1 +XDFF<6> BIST_EN_I BIST_ADDR_I<6> ACLK_N_I ADDR_I<6> q_int<6> net04<2> VDD ++ VSS / RSC_IHPSG13_DFNQMX2IX1 +XDFF<5> BIST_EN_I BIST_ADDR_I<5> ACLK_N_I ADDR_I<5> q_int<5> net04<3> VDD ++ VSS / RSC_IHPSG13_DFNQMX2IX1 +XDFF<4> BIST_EN_I BIST_ADDR_I<4> ACLK_N_I ADDR_I<4> q_int<4> net04<4> VDD ++ VSS / RSC_IHPSG13_DFNQMX2IX1 +XDFF<3> BIST_EN_I BIST_ADDR_I<3> ACLK_N_I ADDR_I<3> q_int<3> net04<5> VDD ++ VSS / RSC_IHPSG13_DFNQMX2IX1 +XDFF<2> BIST_EN_I BIST_ADDR_I<2> ACLK_N_I ADDR_I<2> q_int<2> net04<6> VDD ++ VSS / RSC_IHPSG13_DFNQMX2IX1 +XDFF<1> BIST_EN_I BIST_ADDR_I<1> ACLK_N_I ADDR_I<1> q_int<1> net04<7> VDD ++ VSS / RSC_IHPSG13_DFNQMX2IX1 +XDFF<0> BIST_EN_I BIST_ADDR_I<0> ACLK_N_I ADDR_I<0> q_int<0> net04<8> VDD ++ VSS / RSC_IHPSG13_DFNQMX2IX1 +XDRV<8> qn_int<8> ADDR_N_O<8> VDD VSS / RSC_IHPSG13_CINVX8 +XDRV<7> qn_int<7> ADDR_N_O<7> VDD VSS / RSC_IHPSG13_CINVX8 +XDRV<6> qn_int<6> ADDR_N_O<6> VDD VSS / RSC_IHPSG13_CINVX8 +XDRV<5> qn_int<5> ADDR_N_O<5> VDD VSS / RSC_IHPSG13_CINVX8 +XDRV<4> qn_int<4> ADDR_N_O<4> VDD VSS / RSC_IHPSG13_CINVX8 +XDRV<3> qn_int<3> ADDR_N_O<3> VDD VSS / RSC_IHPSG13_CINVX8 +XDRV<2> qn_int<2> ADDR_N_O<2> VDD VSS / RSC_IHPSG13_CINVX8 +XDRV<1> qn_int<1> ADDR_N_O<1> VDD VSS / RSC_IHPSG13_CINVX8 +XDRV<0> qn_int<0> ADDR_N_O<0> VDD VSS / RSC_IHPSG13_CINVX8 +XINV<8> q_int<8> qn_int<8> VDD VSS / RSC_IHPSG13_CINVX2 +XINV<7> q_int<7> qn_int<7> VDD VSS / RSC_IHPSG13_CINVX2 +XINV<6> q_int<6> qn_int<6> VDD VSS / RSC_IHPSG13_CINVX2 +XINV<5> q_int<5> qn_int<5> VDD VSS / RSC_IHPSG13_CINVX2 +XINV<4> q_int<4> qn_int<4> VDD VSS / RSC_IHPSG13_CINVX2 +XINV<3> q_int<3> qn_int<3> VDD VSS / RSC_IHPSG13_CINVX2 +XINV<2> q_int<2> qn_int<2> VDD VSS / RSC_IHPSG13_CINVX2 +XINV<1> q_int<1> qn_int<1> VDD VSS / RSC_IHPSG13_CINVX2 +XINV<0> q_int<0> qn_int<0> VDD VSS / RSC_IHPSG13_CINVX2 +.ENDS + +.SUBCKT RM_IHPSG13_256x32_c2_2P_DLY_MUX A SEL Z VDD VSS +XI11 net4 Z VDD VSS / RSC_IHPSG13_CINVX2 +XI8 A D<3> SEL net4 VDD VSS / RSC_IHPSG13_MX2IX1 +XI20<3> D<2> D<3> VDD VSS / RSC_IHPSG13_CDLYX1 +XI20<2> D<1> D<2> VDD VSS / RSC_IHPSG13_CDLYX1 +XI20<1> A D<1> VDD VSS / RSC_IHPSG13_CDLYX1 +.ENDS +.SUBCKT RM_IHPSG13_256x32_c2_2P_CTRL ACLK_N BIST_CK_I BIST_CS_I BIST_EN BIST_RE_I ++ BIST_WE_I B_TIEL_O CK_I CS_I DCLK ECLK PULSE_H PULSE_L PULSE_O RCLK RE_I ++ ROW_CS WCLK WE_I VDD VSS +XI17 ck_regs we col_we VDD VSS / RSC_IHPSG13_DFNQX2 +XI16 ck_regs re col_re VDD VSS / RSC_IHPSG13_DFNQX2 +XI18 ck_regs cs net7 VDD VSS / RSC_IHPSG13_DFNQX2 +XI71 ACLK_N net012 PULSE_O VDD VSS / RSC_IHPSG13_DFNQX2 +XI77 col_we net017 net016 VDD VSS / RSC_IHPSG13_CNAND2X2 +XI76 col_re net017 net018 VDD VSS / RSC_IHPSG13_CNAND2X2 +XI15 ck_dly WEorREandCS aclk VDD VSS / RSC_IHPSG13_CGATEPX4 +XI14 ck WEandCS DCLK VDD VSS / RSC_IHPSG13_CGATEPX4 +XI60 net7 ROW_CS VDD VSS / RSC_IHPSG13_CBUFX8 +XI73 PULSE_O net012 VDD VSS / RSC_IHPSG13_CINVX2 +XI8 net017 net8 VDD VSS / RSC_IHPSG13_CINVX2 +XCAPS4<7> VDD VSS / RSC_IHPSG13_FILLCAP4 +XCAPS4<6> VDD VSS / RSC_IHPSG13_FILLCAP4 +XCAPS4<5> VDD VSS / RSC_IHPSG13_FILLCAP4 +XCAPS4<4> VDD VSS / RSC_IHPSG13_FILLCAP4 +XCAPS4<3> VDD VSS / RSC_IHPSG13_FILLCAP4 +XCAPS4<2> VDD VSS / RSC_IHPSG13_FILLCAP4 +XCAPS4<1> VDD VSS / RSC_IHPSG13_FILLCAP4 +XBM_TIEL B_TIEL_O VDD VSS / RSC_IHPSG13_TIEL +XI64 ck ck_dly VDD VSS / RSC_IHPSG13_CDLYX2 +XI86 CS_I BIST_CS_I BIST_EN cs VDD VSS / RSC_IHPSG13_MX2X2 +XI87 CK_I BIST_CK_I BIST_EN ck VDD VSS / RSC_IHPSG13_MX2X2 +XI85 WE_I BIST_WE_I BIST_EN we VDD VSS / RSC_IHPSG13_MX2X2 +XI84 RE_I BIST_RE_I BIST_EN re VDD VSS / RSC_IHPSG13_MX2X2 +XI48 ck_dly ck_regs VDD VSS / RSC_IHPSG13_CINVX4 +XI81 net016 WCLK VDD VSS / RSC_IHPSG13_CINVX4 +XI80 net018 RCLK VDD VSS / RSC_IHPSG13_CINVX4 +XI78 net8 net020 VDD VSS / RSC_IHPSG13_CINVX4 +XCAPS8<7> VDD VSS / RSC_IHPSG13_FILLCAP8 +XCAPS8<6> VDD VSS / RSC_IHPSG13_FILLCAP8 +XCAPS8<5> VDD VSS / RSC_IHPSG13_FILLCAP8 +XCAPS8<4> VDD VSS / RSC_IHPSG13_FILLCAP8 +XCAPS8<3> VDD VSS / RSC_IHPSG13_FILLCAP8 +XCAPS8<2> VDD VSS / RSC_IHPSG13_FILLCAP8 +XCAPS8<1> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI6 PULSE_L PULSE_H net017 VDD VSS / RSC_IHPSG13_XOR2X2 +XI22 we cs WEandCS VDD VSS / RSC_IHPSG13_AND2X2 +XI79 net020 ECLK VDD VSS / RSC_IHPSG13_CINVX8 +XI63 aclk ACLK_N VDD VSS / RSC_IHPSG13_CINVX8 +XI21 re we cs WEorREandCS VDD VSS / RSC_IHPSG13_OA12X1 +.ENDS +.SUBCKT RM_IHPSG13_256x32_c2_2P_COLDEC5 ACLK_N ADDR<4> ADDR<3> ADDR<2> ADDR<1> ADDR<0> ++ ADDR_COL<1> ADDR_COL<0> ADDR_DEC<7> ADDR_DEC<6> ADDR_DEC<5> ADDR_DEC<4> ++ ADDR_DEC<3> ADDR_DEC<2> ADDR_DEC<1> ADDR_DEC<0> BIST_ADDR<4> BIST_ADDR<3> ++ BIST_ADDR<2> BIST_ADDR<1> BIST_ADDR<0> BIST_EN_I VDD VSS +XI17<4> VDD VSS / RSC_IHPSG13_FILLCAP4 +XI17<3> VDD VSS / RSC_IHPSG13_FILLCAP4 +XI17<2> VDD VSS / RSC_IHPSG13_FILLCAP4 +XI17<1> VDD VSS / RSC_IHPSG13_FILLCAP4 +XI1<7> PADR<0> PADR<1> PADR<2> addr_n<7> VDD VSS / RSC_IHPSG13_NAND3X2 +XI1<6> NADR<0> PADR<1> PADR<2> addr_n<6> VDD VSS / RSC_IHPSG13_NAND3X2 +XI1<5> PADR<0> NADR<1> PADR<2> addr_n<5> VDD VSS / RSC_IHPSG13_NAND3X2 +XI1<4> NADR<0> NADR<1> PADR<2> addr_n<4> VDD VSS / RSC_IHPSG13_NAND3X2 +XI1<3> PADR<0> PADR<1> NADR<2> addr_n<3> VDD VSS / RSC_IHPSG13_NAND3X2 +XI1<2> NADR<0> PADR<1> NADR<2> addr_n<2> VDD VSS / RSC_IHPSG13_NAND3X2 +XI1<1> PADR<0> NADR<1> NADR<2> addr_n<1> VDD VSS / RSC_IHPSG13_NAND3X2 +XI1<0> NADR<0> NADR<1> NADR<2> addr_n<0> VDD VSS / RSC_IHPSG13_NAND3X2 +XDFF<4> BIST_EN_I BIST_ADDR<4> ACLK_N ADDR<4> addr_int<1> net13<0> VDD ++ VSS / RSC_IHPSG13_DFNQMX2IX1 +XDFF<3> BIST_EN_I BIST_ADDR<3> ACLK_N ADDR<3> addr_int<0> net13<1> VDD ++ VSS / RSC_IHPSG13_DFNQMX2IX1 +XDFF<2> BIST_EN_I BIST_ADDR<2> ACLK_N ADDR<2> padr_int<2> net13<2> VDD ++ VSS / RSC_IHPSG13_DFNQMX2IX1 +XDFF<1> BIST_EN_I BIST_ADDR<1> ACLK_N ADDR<1> padr_int<1> net13<3> VDD ++ VSS / RSC_IHPSG13_DFNQMX2IX1 +XDFF<0> BIST_EN_I BIST_ADDR<0> ACLK_N ADDR<0> padr_int<0> net13<4> VDD ++ VSS / RSC_IHPSG13_DFNQMX2IX1 +XI3<2> padr_int<2> NADR<2> VDD VSS / RSC_IHPSG13_INVX2 +XI3<1> padr_int<1> NADR<1> VDD VSS / RSC_IHPSG13_INVX2 +XI3<0> padr_int<0> NADR<0> VDD VSS / RSC_IHPSG13_INVX2 +XI2<7> addr_n<7> ADDR_DEC<7> VDD VSS / RSC_IHPSG13_INVX2 +XI2<6> addr_n<6> ADDR_DEC<6> VDD VSS / RSC_IHPSG13_INVX2 +XI2<5> addr_n<5> ADDR_DEC<5> VDD VSS / RSC_IHPSG13_INVX2 +XI2<4> addr_n<4> ADDR_DEC<4> VDD VSS / RSC_IHPSG13_INVX2 +XI2<3> addr_n<3> ADDR_DEC<3> VDD VSS / RSC_IHPSG13_INVX2 +XI2<2> addr_n<2> ADDR_DEC<2> VDD VSS / RSC_IHPSG13_INVX2 +XI2<1> addr_n<1> ADDR_DEC<1> VDD VSS / RSC_IHPSG13_INVX2 +XI2<0> addr_n<0> ADDR_DEC<0> VDD VSS / RSC_IHPSG13_INVX2 +XI15<2> NADR<2> PADR<2> VDD VSS / RSC_IHPSG13_INVX2 +XI15<1> NADR<1> PADR<1> VDD VSS / RSC_IHPSG13_INVX2 +XI15<0> NADR<0> PADR<0> VDD VSS / RSC_IHPSG13_INVX2 +XI13<1> addr_int<1> ADDR_COL<1> VDD VSS / RSC_IHPSG13_CBUFX2 +XI13<0> addr_int<0> ADDR_COL<0> VDD VSS / RSC_IHPSG13_CBUFX2 +XI14<5> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI14<4> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI14<3> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI14<2> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI14<1> VDD VSS / RSC_IHPSG13_FILLCAP8 +.ENDS +.SUBCKT RM_IHPSG13_256x32_c2_2P_BLDRV A_BLC<3> A_BLC<2> A_BLC<1> A_BLC<0> A_BLC_SEL ++ A_BLT<3> A_BLT<2> A_BLT<1> A_BLT<0> A_BLT_SEL A_PRE_N A_SEL_P<3> A_SEL_P<2> ++ A_SEL_P<1> A_SEL_P<0> A_WR_ONE A_WR_ZERO B_BLC<3> B_BLC<2> B_BLC<1> B_BLC<0> ++ B_BLC_SEL B_BLT<3> B_BLT<2> B_BLT<1> B_BLT<0> B_BLT_SEL B_PRE_N B_SEL_P<3> ++ B_SEL_P<2> B_SEL_P<1> B_SEL_P<0> B_WR_ONE B_WR_ZERO VDD VSS +MA_CWN<3> A_BLC<3> A_BLC_NMOS_DRIVE<3> VSS VSS sg13_lv_nmos m=1 ++ w=4.82u l=130.00n ng=2 nrd=0 nrs=0 +MA_CWN<2> A_BLC<2> A_BLC_NMOS_DRIVE<2> VSS VSS sg13_lv_nmos m=1 ++ w=4.82u l=130.00n ng=2 nrd=0 nrs=0 +MA_CWN<1> A_BLC<1> A_BLC_NMOS_DRIVE<1> VSS VSS sg13_lv_nmos m=1 ++ w=4.82u l=130.00n ng=2 nrd=0 nrs=0 +MA_CWN<0> A_BLC<0> A_BLC_NMOS_DRIVE<0> VSS VSS sg13_lv_nmos m=1 ++ w=4.82u l=130.00n ng=2 nrd=0 nrs=0 +MA_TWN<3> A_BLT<3> A_BLT_NMOS_DRIVE<3> VSS VSS sg13_lv_nmos m=1 ++ w=4.82u l=130.00n ng=2 nrd=0 nrs=0 +MA_TWN<2> A_BLT<2> A_BLT_NMOS_DRIVE<2> VSS VSS sg13_lv_nmos m=1 ++ w=4.82u l=130.00n ng=2 nrd=0 nrs=0 +MA_TWN<1> A_BLT<1> A_BLT_NMOS_DRIVE<1> VSS VSS sg13_lv_nmos m=1 ++ w=4.82u l=130.00n ng=2 nrd=0 nrs=0 +MA_TWN<0> A_BLT<0> A_BLT_NMOS_DRIVE<0> VSS VSS sg13_lv_nmos m=1 ++ w=4.82u l=130.00n ng=2 nrd=0 nrs=0 +MB_TWN<3> B_BLT<3> B_BLT_NMOS_DRIVE<3> VSS VSS sg13_lv_nmos m=1 ++ w=4.82u l=130.00n ng=2 nrd=0 nrs=0 +MB_TWN<2> B_BLT<2> B_BLT_NMOS_DRIVE<2> VSS VSS sg13_lv_nmos m=1 ++ w=4.82u l=130.00n ng=2 nrd=0 nrs=0 +MB_TWN<1> B_BLT<1> B_BLT_NMOS_DRIVE<1> VSS VSS sg13_lv_nmos m=1 ++ w=4.82u l=130.00n ng=2 nrd=0 nrs=0 +MB_TWN<0> B_BLT<0> B_BLT_NMOS_DRIVE<0> VSS VSS sg13_lv_nmos m=1 ++ w=4.82u l=130.00n ng=2 nrd=0 nrs=0 +MB_CWN<3> B_BLC<3> B_BLC_NMOS_DRIVE<3> VSS VSS sg13_lv_nmos m=1 ++ w=4.82u l=130.00n ng=2 nrd=0 nrs=0 +MB_CWN<2> B_BLC<2> B_BLC_NMOS_DRIVE<2> VSS VSS sg13_lv_nmos m=1 ++ w=4.82u l=130.00n ng=2 nrd=0 nrs=0 +MB_CWN<1> B_BLC<1> B_BLC_NMOS_DRIVE<1> VSS VSS sg13_lv_nmos m=1 ++ w=4.82u l=130.00n ng=2 nrd=0 nrs=0 +MB_CWN<0> B_BLC<0> B_BLC_NMOS_DRIVE<0> VSS VSS sg13_lv_nmos m=1 ++ w=4.82u l=130.00n ng=2 nrd=0 nrs=0 +MA_CPR<3> A_BLC<3> A_PRE_N VDD VDD sg13_lv_pmos m=1 w=3.000u l=130.00n ++ ng=2 nrd=0 nrs=0 +MA_CPR<2> A_BLC<2> A_PRE_N VDD VDD sg13_lv_pmos m=1 w=3.000u l=130.00n ++ ng=2 nrd=0 nrs=0 +MA_CPR<1> A_BLC<1> A_PRE_N VDD VDD sg13_lv_pmos m=1 w=3.000u l=130.00n ++ ng=2 nrd=0 nrs=0 +MA_CPR<0> A_BLC<0> A_PRE_N VDD VDD sg13_lv_pmos m=1 w=3.000u l=130.00n ++ ng=2 nrd=0 nrs=0 +MA_TWP<3> A_BLT<3> A_BLT_PMOS_DRIVE<3> VDD VDD sg13_lv_pmos m=1 w=1.5u ++ l=130.00n ng=1 nrd=0 nrs=0 +MA_TWP<2> A_BLT<2> A_BLT_PMOS_DRIVE<2> VDD VDD sg13_lv_pmos m=1 w=1.5u ++ l=130.00n ng=1 nrd=0 nrs=0 +MA_TWP<1> A_BLT<1> A_BLT_PMOS_DRIVE<1> VDD VDD sg13_lv_pmos m=1 w=1.5u ++ l=130.00n ng=1 nrd=0 nrs=0 +MA_TWP<0> A_BLT<0> A_BLT_PMOS_DRIVE<0> VDD VDD sg13_lv_pmos m=1 w=1.5u ++ l=130.00n ng=1 nrd=0 nrs=0 +MA_CWP<3> A_BLC<3> A_BLC_PMOS_DRIVE<3> VDD VDD sg13_lv_pmos m=1 w=1.5u ++ l=130.00n ng=1 nrd=0 nrs=0 +MA_CWP<2> A_BLC<2> A_BLC_PMOS_DRIVE<2> VDD VDD sg13_lv_pmos m=1 w=1.5u ++ l=130.00n ng=1 nrd=0 nrs=0 +MA_CWP<1> A_BLC<1> A_BLC_PMOS_DRIVE<1> VDD VDD sg13_lv_pmos m=1 w=1.5u ++ l=130.00n ng=1 nrd=0 nrs=0 +MA_CWP<0> A_BLC<0> A_BLC_PMOS_DRIVE<0> VDD VDD sg13_lv_pmos m=1 w=1.5u ++ l=130.00n ng=1 nrd=0 nrs=0 +MA_TPR<3> A_BLT<3> A_PRE_N VDD VDD sg13_lv_pmos m=1 w=3.000u l=130.00n ++ ng=2 nrd=0 nrs=0 +MA_TPR<2> A_BLT<2> A_PRE_N VDD VDD sg13_lv_pmos m=1 w=3.000u l=130.00n ++ ng=2 nrd=0 nrs=0 +MA_TPR<1> A_BLT<1> A_PRE_N VDD VDD sg13_lv_pmos m=1 w=3.000u l=130.00n ++ ng=2 nrd=0 nrs=0 +MA_TPR<0> A_BLT<0> A_PRE_N VDD VDD sg13_lv_pmos m=1 w=3.000u l=130.00n ++ ng=2 nrd=0 nrs=0 +MA_TSP<3> A_BLT_SEL A_SEL_N<3> A_BLT<3> VDD sg13_lv_pmos m=1 w=1.5u ++ l=130.00n ng=1 nrd=0 nrs=0 +MA_TSP<2> A_BLT_SEL A_SEL_N<2> A_BLT<2> VDD sg13_lv_pmos m=1 w=1.5u ++ l=130.00n ng=1 nrd=0 nrs=0 +MA_TSP<1> A_BLT_SEL A_SEL_N<1> A_BLT<1> VDD sg13_lv_pmos m=1 w=1.5u ++ l=130.00n ng=1 nrd=0 nrs=0 +MA_TSP<0> A_BLT_SEL A_SEL_N<0> A_BLT<0> VDD sg13_lv_pmos m=1 w=1.5u ++ l=130.00n ng=1 nrd=0 nrs=0 +MA_CSP<3> A_BLC_SEL A_SEL_N<3> A_BLC<3> VDD sg13_lv_pmos m=1 w=1.5u ++ l=130.00n ng=1 nrd=0 nrs=0 +MA_CSP<2> A_BLC_SEL A_SEL_N<2> A_BLC<2> VDD sg13_lv_pmos m=1 w=1.5u ++ l=130.00n ng=1 nrd=0 nrs=0 +MA_CSP<1> A_BLC_SEL A_SEL_N<1> A_BLC<1> VDD sg13_lv_pmos m=1 w=1.5u ++ l=130.00n ng=1 nrd=0 nrs=0 +MA_CSP<0> A_BLC_SEL A_SEL_N<0> A_BLC<0> VDD sg13_lv_pmos m=1 w=1.5u ++ l=130.00n ng=1 nrd=0 nrs=0 +MB_CWP<3> B_BLC<3> B_BLC_PMOS_DRIVE<3> VDD VDD sg13_lv_pmos m=1 w=1.5u ++ l=130.00n ng=1 nrd=0 nrs=0 +MB_CWP<2> B_BLC<2> B_BLC_PMOS_DRIVE<2> VDD VDD sg13_lv_pmos m=1 w=1.5u ++ l=130.00n ng=1 nrd=0 nrs=0 +MB_CWP<1> B_BLC<1> B_BLC_PMOS_DRIVE<1> VDD VDD sg13_lv_pmos m=1 w=1.5u ++ l=130.00n ng=1 nrd=0 nrs=0 +MB_CWP<0> B_BLC<0> B_BLC_PMOS_DRIVE<0> VDD VDD sg13_lv_pmos m=1 w=1.5u ++ l=130.00n ng=1 nrd=0 nrs=0 +MB_TWP<3> B_BLT<3> B_BLT_PMOS_DRIVE<3> VDD VDD sg13_lv_pmos m=1 w=1.5u ++ l=130.00n ng=1 nrd=0 nrs=0 +MB_TWP<2> B_BLT<2> B_BLT_PMOS_DRIVE<2> VDD VDD sg13_lv_pmos m=1 w=1.5u ++ l=130.00n ng=1 nrd=0 nrs=0 +MB_TWP<1> B_BLT<1> B_BLT_PMOS_DRIVE<1> VDD VDD sg13_lv_pmos m=1 w=1.5u ++ l=130.00n ng=1 nrd=0 nrs=0 +MB_TWP<0> B_BLT<0> B_BLT_PMOS_DRIVE<0> VDD VDD sg13_lv_pmos m=1 w=1.5u ++ l=130.00n ng=1 nrd=0 nrs=0 +MB_TSP<3> B_BLT_SEL B_SEL_N<3> B_BLT<3> VDD sg13_lv_pmos m=1 w=1.5u ++ l=130.00n ng=1 nrd=0 nrs=0 +MB_TSP<2> B_BLT_SEL B_SEL_N<2> B_BLT<2> VDD sg13_lv_pmos m=1 w=1.5u ++ l=130.00n ng=1 nrd=0 nrs=0 +MB_TSP<1> B_BLT_SEL B_SEL_N<1> B_BLT<1> VDD sg13_lv_pmos m=1 w=1.5u ++ l=130.00n ng=1 nrd=0 nrs=0 +MB_TSP<0> B_BLT_SEL B_SEL_N<0> B_BLT<0> VDD sg13_lv_pmos m=1 w=1.5u ++ l=130.00n ng=1 nrd=0 nrs=0 +MB_TPR<3> B_BLT<3> B_PRE_N VDD VDD sg13_lv_pmos m=1 w=3.000u l=130.00n ++ ng=2 nrd=0 nrs=0 +MB_TPR<2> B_BLT<2> B_PRE_N VDD VDD sg13_lv_pmos m=1 w=3.000u l=130.00n ++ ng=2 nrd=0 nrs=0 +MB_TPR<1> B_BLT<1> B_PRE_N VDD VDD sg13_lv_pmos m=1 w=3.000u l=130.00n ++ ng=2 nrd=0 nrs=0 +MB_TPR<0> B_BLT<0> B_PRE_N VDD VDD sg13_lv_pmos m=1 w=3.000u l=130.00n ++ ng=2 nrd=0 nrs=0 +MB_CSP<3> B_BLC_SEL B_SEL_N<3> B_BLC<3> VDD sg13_lv_pmos m=1 w=1.5u ++ l=130.00n ng=1 nrd=0 nrs=0 +MB_CSP<2> B_BLC_SEL B_SEL_N<2> B_BLC<2> VDD sg13_lv_pmos m=1 w=1.5u ++ l=130.00n ng=1 nrd=0 nrs=0 +MB_CSP<1> B_BLC_SEL B_SEL_N<1> B_BLC<1> VDD sg13_lv_pmos m=1 w=1.5u ++ l=130.00n ng=1 nrd=0 nrs=0 +MB_CSP<0> B_BLC_SEL B_SEL_N<0> B_BLC<0> VDD sg13_lv_pmos m=1 w=1.5u ++ l=130.00n ng=1 nrd=0 nrs=0 +MB_CPR<3> B_BLC<3> B_PRE_N VDD VDD sg13_lv_pmos m=1 w=3.000u l=130.00n ++ ng=2 nrd=0 nrs=0 +MB_CPR<2> B_BLC<2> B_PRE_N VDD VDD sg13_lv_pmos m=1 w=3.000u l=130.00n ++ ng=2 nrd=0 nrs=0 +MB_CPR<1> B_BLC<1> B_PRE_N VDD VDD sg13_lv_pmos m=1 w=3.000u l=130.00n ++ ng=2 nrd=0 nrs=0 +MB_CPR<0> B_BLC<0> B_PRE_N VDD VDD sg13_lv_pmos m=1 w=3.000u l=130.00n ++ ng=2 nrd=0 nrs=0 +XA_SEL<3> A_SEL_P<3> A_SEL_N<3> VDD VSS / RSC_IHPSG13_INVX2 +XA_SEL<2> A_SEL_P<2> A_SEL_N<2> VDD VSS / RSC_IHPSG13_INVX2 +XA_SEL<1> A_SEL_P<1> A_SEL_N<1> VDD VSS / RSC_IHPSG13_INVX2 +XA_SEL<0> A_SEL_P<0> A_SEL_N<0> VDD VSS / RSC_IHPSG13_INVX2 +XA_CINV<3> A_BLT_PMOS_DRIVE<3> A_BLC_NMOS_DRIVE<3> VDD VSS / ++ RSC_IHPSG13_INVX2 +XA_CINV<2> A_BLT_PMOS_DRIVE<2> A_BLC_NMOS_DRIVE<2> VDD VSS / ++ RSC_IHPSG13_INVX2 +XA_CINV<1> A_BLT_PMOS_DRIVE<1> A_BLC_NMOS_DRIVE<1> VDD VSS / ++ RSC_IHPSG13_INVX2 +XA_CINV<0> A_BLT_PMOS_DRIVE<0> A_BLC_NMOS_DRIVE<0> VDD VSS / ++ RSC_IHPSG13_INVX2 +XA_TINV<3> A_BLC_PMOS_DRIVE<3> A_BLT_NMOS_DRIVE<3> VDD VSS / ++ RSC_IHPSG13_INVX2 +XA_TINV<2> A_BLC_PMOS_DRIVE<2> A_BLT_NMOS_DRIVE<2> VDD VSS / ++ RSC_IHPSG13_INVX2 +XA_TINV<1> A_BLC_PMOS_DRIVE<1> A_BLT_NMOS_DRIVE<1> VDD VSS / ++ RSC_IHPSG13_INVX2 +XA_TINV<0> A_BLC_PMOS_DRIVE<0> A_BLT_NMOS_DRIVE<0> VDD VSS / ++ RSC_IHPSG13_INVX2 +XB_SEL<3> B_SEL_P<3> B_SEL_N<3> VDD VSS / RSC_IHPSG13_INVX2 +XB_SEL<2> B_SEL_P<2> B_SEL_N<2> VDD VSS / RSC_IHPSG13_INVX2 +XB_SEL<1> B_SEL_P<1> B_SEL_N<1> VDD VSS / RSC_IHPSG13_INVX2 +XB_SEL<0> B_SEL_P<0> B_SEL_N<0> VDD VSS / RSC_IHPSG13_INVX2 +XB_TINV<3> B_BLC_PMOS_DRIVE<3> B_BLT_NMOS_DRIVE<3> VDD VSS / ++ RSC_IHPSG13_INVX2 +XB_TINV<2> B_BLC_PMOS_DRIVE<2> B_BLT_NMOS_DRIVE<2> VDD VSS / ++ RSC_IHPSG13_INVX2 +XB_TINV<1> B_BLC_PMOS_DRIVE<1> B_BLT_NMOS_DRIVE<1> VDD VSS / ++ RSC_IHPSG13_INVX2 +XB_TINV<0> B_BLC_PMOS_DRIVE<0> B_BLT_NMOS_DRIVE<0> VDD VSS / ++ RSC_IHPSG13_INVX2 +XB_CINV<3> B_BLT_PMOS_DRIVE<3> B_BLC_NMOS_DRIVE<3> VDD VSS / ++ RSC_IHPSG13_INVX2 +XB_CINV<2> B_BLT_PMOS_DRIVE<2> B_BLC_NMOS_DRIVE<2> VDD VSS / ++ RSC_IHPSG13_INVX2 +XB_CINV<1> B_BLT_PMOS_DRIVE<1> B_BLC_NMOS_DRIVE<1> VDD VSS / ++ RSC_IHPSG13_INVX2 +XB_CINV<0> B_BLT_PMOS_DRIVE<0> B_BLC_NMOS_DRIVE<0> VDD VSS / ++ RSC_IHPSG13_INVX2 +XA_TDEC<3> A_SEL_P<3> A_WR_ONE A_BLT_PMOS_DRIVE<3> VDD VSS / ++ RSC_IHPSG13_NAND2X2 +XA_TDEC<2> A_SEL_P<2> A_WR_ONE A_BLT_PMOS_DRIVE<2> VDD VSS / ++ RSC_IHPSG13_NAND2X2 +XA_TDEC<1> A_SEL_P<1> A_WR_ONE A_BLT_PMOS_DRIVE<1> VDD VSS / ++ RSC_IHPSG13_NAND2X2 +XA_TDEC<0> A_SEL_P<0> A_WR_ONE A_BLT_PMOS_DRIVE<0> VDD VSS / ++ RSC_IHPSG13_NAND2X2 +XA_CDEC<3> A_SEL_P<3> A_WR_ZERO A_BLC_PMOS_DRIVE<3> VDD VSS / ++ RSC_IHPSG13_NAND2X2 +XA_CDEC<2> A_SEL_P<2> A_WR_ZERO A_BLC_PMOS_DRIVE<2> VDD VSS / ++ RSC_IHPSG13_NAND2X2 +XA_CDEC<1> A_SEL_P<1> A_WR_ZERO A_BLC_PMOS_DRIVE<1> VDD VSS / ++ RSC_IHPSG13_NAND2X2 +XA_CDEC<0> A_SEL_P<0> A_WR_ZERO A_BLC_PMOS_DRIVE<0> VDD VSS / ++ RSC_IHPSG13_NAND2X2 +XB_CDEC<3> B_SEL_P<3> B_WR_ZERO B_BLC_PMOS_DRIVE<3> VDD VSS / ++ RSC_IHPSG13_NAND2X2 +XB_CDEC<2> B_SEL_P<2> B_WR_ZERO B_BLC_PMOS_DRIVE<2> VDD VSS / ++ RSC_IHPSG13_NAND2X2 +XB_CDEC<1> B_SEL_P<1> B_WR_ZERO B_BLC_PMOS_DRIVE<1> VDD VSS / ++ RSC_IHPSG13_NAND2X2 +XB_CDEC<0> B_SEL_P<0> B_WR_ZERO B_BLC_PMOS_DRIVE<0> VDD VSS / ++ RSC_IHPSG13_NAND2X2 +XB_TDEC<3> B_SEL_P<3> B_WR_ONE B_BLT_PMOS_DRIVE<3> VDD VSS / ++ RSC_IHPSG13_NAND2X2 +XB_TDEC<2> B_SEL_P<2> B_WR_ONE B_BLT_PMOS_DRIVE<2> VDD VSS / ++ RSC_IHPSG13_NAND2X2 +XB_TDEC<1> B_SEL_P<1> B_WR_ONE B_BLT_PMOS_DRIVE<1> VDD VSS / ++ RSC_IHPSG13_NAND2X2 +XB_TDEC<0> B_SEL_P<0> B_WR_ONE B_BLT_PMOS_DRIVE<0> VDD VSS / ++ RSC_IHPSG13_NAND2X2 +.ENDS +.SUBCKT RSC_IHPSG13_AND2X6 A B Z VDD VSS +MN3 Z net6 VSS VSS sg13_lv_nmos m=1 w=2.94u l=130.00n ng=3 nrd=0 nrs=0 +MN4 net9 B VSS VSS sg13_lv_nmos m=1 w=500.0n l=130.00n ng=1 nrd=0 nrs=0 +MN6 net6 A net9 VSS sg13_lv_nmos m=1 w=500.0n l=130.00n ng=1 nrd=0 nrs=0 +MP2 Z net6 VDD VDD sg13_lv_pmos m=1 w=4.86u l=130.00n ng=3 nrd=0 nrs=0 +MP0 net6 B VDD VDD sg13_lv_pmos m=1 w=860.00n l=130.00n ng=1 nrd=0 ++ nrs=0 +MP1 net6 A VDD VDD sg13_lv_pmos m=1 w=860.00n l=130.00n ng=1 nrd=0 ++ nrs=0 +.ENDS +.SUBCKT RM_IHPSG13_256x32_c2_2P_COLCTRL5 A_ADDR_COL<1> A_ADDR_COL<0> A_ADDR_DEC<7> ++ A_ADDR_DEC<6> A_ADDR_DEC<5> A_ADDR_DEC<4> A_ADDR_DEC<3> A_ADDR_DEC<2> ++ A_ADDR_DEC<1> A_ADDR_DEC<0> A_BIST_BM_I A_BIST_DW_I A_BIST_EN_I A_BLC<31> ++ A_BLC<30> A_BLC<29> A_BLC<28> A_BLC<27> A_BLC<26> A_BLC<25> A_BLC<24> ++ A_BLC<23> A_BLC<22> A_BLC<21> A_BLC<20> A_BLC<19> A_BLC<18> A_BLC<17> ++ A_BLC<16> A_BLC<15> A_BLC<14> A_BLC<13> A_BLC<12> A_BLC<11> A_BLC<10> ++ A_BLC<9> A_BLC<8> A_BLC<7> A_BLC<6> A_BLC<5> A_BLC<4> A_BLC<3> A_BLC<2> ++ A_BLC<1> A_BLC<0> A_BLT<31> A_BLT<30> A_BLT<29> A_BLT<28> A_BLT<27> ++ A_BLT<26> A_BLT<25> A_BLT<24> A_BLT<23> A_BLT<22> A_BLT<21> A_BLT<20> ++ A_BLT<19> A_BLT<18> A_BLT<17> A_BLT<16> A_BLT<15> A_BLT<14> A_BLT<13> ++ A_BLT<12> A_BLT<11> A_BLT<10> A_BLT<9> A_BLT<8> A_BLT<7> A_BLT<6> A_BLT<5> ++ A_BLT<4> A_BLT<3> A_BLT<2> A_BLT<1> A_BLT<0> A_BM_I A_DCLK_B_L A_DCLK_B_R ++ A_DCLK_L A_DCLK_R A_DR_O A_DW_I A_RCLK_B_L A_RCLK_B_R A_RCLK_L A_RCLK_R ++ A_TIEH_O A_WCLK_B_L A_WCLK_B_R A_WCLK_L A_WCLK_R B_ADDR_COL<1> B_ADDR_COL<0> ++ B_ADDR_DEC<7> B_ADDR_DEC<6> B_ADDR_DEC<5> B_ADDR_DEC<4> B_ADDR_DEC<3> ++ B_ADDR_DEC<2> B_ADDR_DEC<1> B_ADDR_DEC<0> B_BIST_BM_I B_BIST_DW_I ++ B_BIST_EN_I B_BLC<31> B_BLC<30> B_BLC<29> B_BLC<28> B_BLC<27> B_BLC<26> ++ B_BLC<25> B_BLC<24> B_BLC<23> B_BLC<22> B_BLC<21> B_BLC<20> B_BLC<19> ++ B_BLC<18> B_BLC<17> B_BLC<16> B_BLC<15> B_BLC<14> B_BLC<13> B_BLC<12> ++ B_BLC<11> B_BLC<10> B_BLC<9> B_BLC<8> B_BLC<7> B_BLC<6> B_BLC<5> B_BLC<4> ++ B_BLC<3> B_BLC<2> B_BLC<1> B_BLC<0> B_BLT<31> B_BLT<30> B_BLT<29> B_BLT<28> ++ B_BLT<27> B_BLT<26> B_BLT<25> B_BLT<24> B_BLT<23> B_BLT<22> B_BLT<21> ++ B_BLT<20> B_BLT<19> B_BLT<18> B_BLT<17> B_BLT<16> B_BLT<15> B_BLT<14> ++ B_BLT<13> B_BLT<12> B_BLT<11> B_BLT<10> B_BLT<9> B_BLT<8> B_BLT<7> B_BLT<6> ++ B_BLT<5> B_BLT<4> B_BLT<3> B_BLT<2> B_BLT<1> B_BLT<0> B_BM_I B_DCLK_B_L ++ B_DCLK_B_R B_DCLK_L B_DCLK_R B_DR_O B_DW_I B_RCLK_B_L B_RCLK_B_R B_RCLK_L ++ B_RCLK_R B_TIEH_O B_WCLK_B_L B_WCLK_B_R B_WCLK_L B_WCLK_R VDD VSS +XB_I80<1> B_WCLK_B_L B_RCLK_B_L B_W_nor_R<1> VDD VSS / ++ RSC_IHPSG13_AND2X2 +XB_I80<0> B_WCLK_B_L B_RCLK_B_L B_W_nor_R<0> VDD VSS / ++ RSC_IHPSG13_AND2X2 +XA_I80<1> A_WCLK_B_L A_RCLK_B_L A_W_nor_R<1> VDD VSS / ++ RSC_IHPSG13_AND2X2 +XA_I80<0> A_WCLK_B_L A_RCLK_B_L A_W_nor_R<0> VDD VSS / ++ RSC_IHPSG13_AND2X2 +XB_I44 B_BM_N B_WCLK_B_L B_DO_WRITE_P VDD VSS / RSC_IHPSG13_NOR2X2 +XA_I44 A_BM_N A_WCLK_B_L A_DO_WRITE_P VDD VSS / RSC_IHPSG13_NOR2X2 +XI_FILL4<16> VDD VSS / RSC_IHPSG13_FILLCAP4 +XI_FILL4<15> VDD VSS / RSC_IHPSG13_FILLCAP4 +XI_FILL4<14> VDD VSS / RSC_IHPSG13_FILLCAP4 +XI_FILL4<13> VDD VSS / RSC_IHPSG13_FILLCAP4 +XI_FILL4<12> VDD VSS / RSC_IHPSG13_FILLCAP4 +XI_FILL4<11> VDD VSS / RSC_IHPSG13_FILLCAP4 +XI_FILL4<10> VDD VSS / RSC_IHPSG13_FILLCAP4 +XI_FILL4<9> VDD VSS / RSC_IHPSG13_FILLCAP4 +XI_FILL4<8> VDD VSS / RSC_IHPSG13_FILLCAP4 +XI_FILL4<7> VDD VSS / RSC_IHPSG13_FILLCAP4 +XI_FILL4<6> VDD VSS / RSC_IHPSG13_FILLCAP4 +XI_FILL4<5> VDD VSS / RSC_IHPSG13_FILLCAP4 +XI_FILL4<4> VDD VSS / RSC_IHPSG13_FILLCAP4 +XI_FILL4<3> VDD VSS / RSC_IHPSG13_FILLCAP4 +XI_FILL4<2> VDD VSS / RSC_IHPSG13_FILLCAP4 +XI_FILL4<1> VDD VSS / RSC_IHPSG13_FILLCAP4 +XB_INV<6> B_N1<1> B_P1<1> VDD VSS / RSC_IHPSG13_CINVX4 +XB_INV<5> B_N0<1> B_P0<1> VDD VSS / RSC_IHPSG13_CINVX4 +XB_INV<4> B_N0<0> B_P0<0> VDD VSS / RSC_IHPSG13_CINVX4 +XB_INV<3> B_ADDR_COL<1> B_N1<1> VDD VSS / RSC_IHPSG13_CINVX4 +XB_INV<2> B_ADDR_COL<1> B_N1<0> VDD VSS / RSC_IHPSG13_CINVX4 +XB_INV<1> B_ADDR_COL<0> B_N0<1> VDD VSS / RSC_IHPSG13_CINVX4 +XB_INV<0> B_ADDR_COL<0> B_N0<0> VDD VSS / RSC_IHPSG13_CINVX4 +XA_INV<6> A_N1<1> A_P1<1> VDD VSS / RSC_IHPSG13_CINVX4 +XA_INV<5> A_N0<1> A_P0<1> VDD VSS / RSC_IHPSG13_CINVX4 +XA_INV<4> A_N0<0> A_P0<0> VDD VSS / RSC_IHPSG13_CINVX4 +XA_INV<3> A_ADDR_COL<1> A_N1<1> VDD VSS / RSC_IHPSG13_CINVX4 +XA_INV<2> A_ADDR_COL<1> A_N1<0> VDD VSS / RSC_IHPSG13_CINVX4 +XA_INV<1> A_ADDR_COL<0> A_N0<1> VDD VSS / RSC_IHPSG13_CINVX4 +XA_INV<0> A_ADDR_COL<0> A_N0<0> VDD VSS / RSC_IHPSG13_CINVX4 +XB_I81<3> B_W_nor_R<1> B_PRE_N VDD VSS / RSC_IHPSG13_CINVX4_WN +XB_I81<2> B_W_nor_R<1> B_PRE_N VDD VSS / RSC_IHPSG13_CINVX4_WN +XB_I81<1> B_W_nor_R<0> B_PRE_N VDD VSS / RSC_IHPSG13_CINVX4_WN +XB_I81<0> B_W_nor_R<0> B_PRE_N VDD VSS / RSC_IHPSG13_CINVX4_WN +XA_I81<3> A_W_nor_R<1> A_PRE_N VDD VSS / RSC_IHPSG13_CINVX4_WN +XA_I81<2> A_W_nor_R<1> A_PRE_N VDD VSS / RSC_IHPSG13_CINVX4_WN +XA_I81<1> A_W_nor_R<0> A_PRE_N VDD VSS / RSC_IHPSG13_CINVX4_WN +XA_I81<0> A_W_nor_R<0> A_PRE_N VDD VSS / RSC_IHPSG13_CINVX4_WN +XI_FILL8<78> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI_FILL8<77> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI_FILL8<76> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI_FILL8<75> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI_FILL8<74> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI_FILL8<73> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI_FILL8<72> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI_FILL8<71> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI_FILL8<70> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI_FILL8<69> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI_FILL8<68> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI_FILL8<67> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI_FILL8<66> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI_FILL8<65> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI_FILL8<64> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI_FILL8<63> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI_FILL8<62> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI_FILL8<61> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI_FILL8<60> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI_FILL8<59> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI_FILL8<58> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI_FILL8<57> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI_FILL8<56> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI_FILL8<55> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI_FILL8<54> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI_FILL8<53> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI_FILL8<52> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI_FILL8<51> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI_FILL8<50> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI_FILL8<49> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI_FILL8<48> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI_FILL8<47> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI_FILL8<46> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI_FILL8<45> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI_FILL8<44> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI_FILL8<43> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI_FILL8<42> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI_FILL8<41> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI_FILL8<40> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI_FILL8<39> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI_FILL8<38> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI_FILL8<37> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI_FILL8<36> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI_FILL8<35> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI_FILL8<34> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI_FILL8<33> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI_FILL8<32> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI_FILL8<31> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI_FILL8<30> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI_FILL8<29> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI_FILL8<28> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI_FILL8<27> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI_FILL8<26> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI_FILL8<25> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI_FILL8<24> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI_FILL8<23> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI_FILL8<22> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI_FILL8<21> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI_FILL8<20> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI_FILL8<19> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI_FILL8<18> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI_FILL8<17> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI_FILL8<16> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI_FILL8<15> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI_FILL8<14> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI_FILL8<13> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI_FILL8<12> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI_FILL8<11> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI_FILL8<10> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI_FILL8<9> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI_FILL8<8> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI_FILL8<7> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI_FILL8<6> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI_FILL8<5> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI_FILL8<4> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI_FILL8<3> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI_FILL8<2> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI_FILL8<1> VDD VSS / RSC_IHPSG13_FILLCAP8 +XAB_BLMUX<7> A_BLC<31> A_BLC<30> A_BLC<29> A_BLC<28> A_BLC_SEL A_BLT<31> ++ A_BLT<30> A_BLT<29> A_BLT<28> A_BLT_SEL A_PRE_N A_SEL_P<31> A_SEL_P<30> ++ A_SEL_P<29> A_SEL_P<28> A_WR_ONE A_WR_ZERO B_BLC<31> B_BLC<30> B_BLC<29> ++ B_BLC<28> B_BLC_SEL B_BLT<31> B_BLT<30> B_BLT<29> B_BLT<28> B_BLT_SEL ++ B_PRE_N B_SEL_P<31> B_SEL_P<30> B_SEL_P<29> B_SEL_P<28> B_WR_ONE B_WR_ZERO ++ VDD VSS / RM_IHPSG13_256x32_c2_2P_BLDRV +XAB_BLMUX<6> A_BLC<27> A_BLC<26> A_BLC<25> A_BLC<24> A_BLC_SEL A_BLT<27> ++ A_BLT<26> A_BLT<25> A_BLT<24> A_BLT_SEL A_PRE_N A_SEL_P<27> A_SEL_P<26> ++ A_SEL_P<25> A_SEL_P<24> A_WR_ONE A_WR_ZERO B_BLC<27> B_BLC<26> B_BLC<25> ++ B_BLC<24> B_BLC_SEL B_BLT<27> B_BLT<26> B_BLT<25> B_BLT<24> B_BLT_SEL ++ B_PRE_N B_SEL_P<27> B_SEL_P<26> B_SEL_P<25> B_SEL_P<24> B_WR_ONE B_WR_ZERO ++ VDD VSS / RM_IHPSG13_256x32_c2_2P_BLDRV +XAB_BLMUX<5> A_BLC<23> A_BLC<22> A_BLC<21> A_BLC<20> A_BLC_SEL A_BLT<23> ++ A_BLT<22> A_BLT<21> A_BLT<20> A_BLT_SEL A_PRE_N A_SEL_P<23> A_SEL_P<22> ++ A_SEL_P<21> A_SEL_P<20> A_WR_ONE A_WR_ZERO B_BLC<23> B_BLC<22> B_BLC<21> ++ B_BLC<20> B_BLC_SEL B_BLT<23> B_BLT<22> B_BLT<21> B_BLT<20> B_BLT_SEL ++ B_PRE_N B_SEL_P<23> B_SEL_P<22> B_SEL_P<21> B_SEL_P<20> B_WR_ONE B_WR_ZERO ++ VDD VSS / RM_IHPSG13_256x32_c2_2P_BLDRV +XAB_BLMUX<4> A_BLC<19> A_BLC<18> A_BLC<17> A_BLC<16> A_BLC_SEL A_BLT<19> ++ A_BLT<18> A_BLT<17> A_BLT<16> A_BLT_SEL A_PRE_N A_SEL_P<19> A_SEL_P<18> ++ A_SEL_P<17> A_SEL_P<16> A_WR_ONE A_WR_ZERO B_BLC<19> B_BLC<18> B_BLC<17> ++ B_BLC<16> B_BLC_SEL B_BLT<19> B_BLT<18> B_BLT<17> B_BLT<16> B_BLT_SEL ++ B_PRE_N B_SEL_P<19> B_SEL_P<18> B_SEL_P<17> B_SEL_P<16> B_WR_ONE B_WR_ZERO ++ VDD VSS / RM_IHPSG13_256x32_c2_2P_BLDRV +XAB_BLMUX<3> A_BLC<15> A_BLC<14> A_BLC<13> A_BLC<12> A_BLC_SEL A_BLT<15> ++ A_BLT<14> A_BLT<13> A_BLT<12> A_BLT_SEL A_PRE_N A_SEL_P<15> A_SEL_P<14> ++ A_SEL_P<13> A_SEL_P<12> A_WR_ONE A_WR_ZERO B_BLC<15> B_BLC<14> B_BLC<13> ++ B_BLC<12> B_BLC_SEL B_BLT<15> B_BLT<14> B_BLT<13> B_BLT<12> B_BLT_SEL ++ B_PRE_N B_SEL_P<15> B_SEL_P<14> B_SEL_P<13> B_SEL_P<12> B_WR_ONE B_WR_ZERO ++ VDD VSS / RM_IHPSG13_256x32_c2_2P_BLDRV +XAB_BLMUX<2> A_BLC<11> A_BLC<10> A_BLC<9> A_BLC<8> A_BLC_SEL A_BLT<11> ++ A_BLT<10> A_BLT<9> A_BLT<8> A_BLT_SEL A_PRE_N A_SEL_P<11> A_SEL_P<10> ++ A_SEL_P<9> A_SEL_P<8> A_WR_ONE A_WR_ZERO B_BLC<11> B_BLC<10> B_BLC<9> ++ B_BLC<8> B_BLC_SEL B_BLT<11> B_BLT<10> B_BLT<9> B_BLT<8> B_BLT_SEL B_PRE_N ++ B_SEL_P<11> B_SEL_P<10> B_SEL_P<9> B_SEL_P<8> B_WR_ONE B_WR_ZERO VDD ++ VSS / RM_IHPSG13_256x32_c2_2P_BLDRV +XAB_BLMUX<1> A_BLC<7> A_BLC<6> A_BLC<5> A_BLC<4> A_BLC_SEL A_BLT<7> A_BLT<6> ++ A_BLT<5> A_BLT<4> A_BLT_SEL A_PRE_N A_SEL_P<7> A_SEL_P<6> A_SEL_P<5> ++ A_SEL_P<4> A_WR_ONE A_WR_ZERO B_BLC<7> B_BLC<6> B_BLC<5> B_BLC<4> B_BLC_SEL ++ B_BLT<7> B_BLT<6> B_BLT<5> B_BLT<4> B_BLT_SEL B_PRE_N B_SEL_P<7> B_SEL_P<6> ++ B_SEL_P<5> B_SEL_P<4> B_WR_ONE B_WR_ZERO VDD VSS / ++ RM_IHPSG13_256x32_c2_2P_BLDRV +XAB_BLMUX<0> A_BLC<3> A_BLC<2> A_BLC<1> A_BLC<0> A_BLC_SEL A_BLT<3> A_BLT<2> ++ A_BLT<1> A_BLT<0> A_BLT_SEL A_PRE_N A_SEL_P<3> A_SEL_P<2> A_SEL_P<1> ++ A_SEL_P<0> A_WR_ONE A_WR_ZERO B_BLC<3> B_BLC<2> B_BLC<1> B_BLC<0> B_BLC_SEL ++ B_BLT<3> B_BLT<2> B_BLT<1> B_BLT<0> B_BLT_SEL B_PRE_N B_SEL_P<3> B_SEL_P<2> ++ B_SEL_P<1> B_SEL_P<0> B_WR_ONE B_WR_ZERO VDD VSS / ++ RM_IHPSG13_256x32_c2_2P_BLDRV +XB_I51 net037 B_DR_O VDD VSS / RSC_IHPSG13_INVX4 +XA_I51 net19 A_DR_O VDD VSS / RSC_IHPSG13_INVX4 +XB_I78 B_RCLK_B_L B_SAE VDD VSS / RSC_IHPSG13_CBUFX2 +XA_I78 A_RCLK_B_L A_SAE VDD VSS / RSC_IHPSG13_CBUFX2 +XB_I69 B_DCLK_L B_DCLK_B_L VDD VSS / RSC_IHPSG13_CINVX8 +XB_I50 B_WCLK_L B_WCLK_B_L VDD VSS / RSC_IHPSG13_CINVX8 +XB_EBUF B_RCLK_L B_RCLK_B_L VDD VSS / RSC_IHPSG13_CINVX8 +XA_I69 A_DCLK_L A_DCLK_B_L VDD VSS / RSC_IHPSG13_CINVX8 +XA_I50 A_WCLK_L A_WCLK_B_L VDD VSS / RSC_IHPSG13_CINVX8 +XA_EBUF A_RCLK_L A_RCLK_B_L VDD VSS / RSC_IHPSG13_CINVX8 +XB_I76 B_DI_N B_DO_WRITE_P B_WR_ZERO VDD VSS / RSC_IHPSG13_AND2X6 +XB_I75 B_DI_R B_DO_WRITE_P B_WR_ONE VDD VSS / RSC_IHPSG13_AND2X6 +XA_I76 A_DI_N A_DO_WRITE_P A_WR_ZERO VDD VSS / RSC_IHPSG13_AND2X6 +XA_I75 A_DI_R A_DO_WRITE_P A_WR_ONE VDD VSS / RSC_IHPSG13_AND2X6 +XB_I83 B_BM_R B_BM_N VDD VSS / RSC_IHPSG13_INVX2 +XB_DEC3INV<31> net041<0> B_SEL_P<31> VDD VSS / RSC_IHPSG13_INVX2 +XB_DEC3INV<30> net041<1> B_SEL_P<30> VDD VSS / RSC_IHPSG13_INVX2 +XB_DEC3INV<29> net041<2> B_SEL_P<29> VDD VSS / RSC_IHPSG13_INVX2 +XB_DEC3INV<28> net041<3> B_SEL_P<28> VDD VSS / RSC_IHPSG13_INVX2 +XB_DEC3INV<27> net041<4> B_SEL_P<27> VDD VSS / RSC_IHPSG13_INVX2 +XB_DEC3INV<26> net041<5> B_SEL_P<26> VDD VSS / RSC_IHPSG13_INVX2 +XB_DEC3INV<25> net041<6> B_SEL_P<25> VDD VSS / RSC_IHPSG13_INVX2 +XB_DEC3INV<24> net041<7> B_SEL_P<24> VDD VSS / RSC_IHPSG13_INVX2 +XB_DEC3INV<23> net041<8> B_SEL_P<23> VDD VSS / RSC_IHPSG13_INVX2 +XB_DEC3INV<22> net041<9> B_SEL_P<22> VDD VSS / RSC_IHPSG13_INVX2 +XB_DEC3INV<21> net041<10> B_SEL_P<21> VDD VSS / RSC_IHPSG13_INVX2 +XB_DEC3INV<20> net041<11> B_SEL_P<20> VDD VSS / RSC_IHPSG13_INVX2 +XB_DEC3INV<19> net041<12> B_SEL_P<19> VDD VSS / RSC_IHPSG13_INVX2 +XB_DEC3INV<18> net041<13> B_SEL_P<18> VDD VSS / RSC_IHPSG13_INVX2 +XB_DEC3INV<17> net041<14> B_SEL_P<17> VDD VSS / RSC_IHPSG13_INVX2 +XB_DEC3INV<16> net041<15> B_SEL_P<16> VDD VSS / RSC_IHPSG13_INVX2 +XB_DEC3INV<15> net041<16> B_SEL_P<15> VDD VSS / RSC_IHPSG13_INVX2 +XB_DEC3INV<14> net041<17> B_SEL_P<14> VDD VSS / RSC_IHPSG13_INVX2 +XB_DEC3INV<13> net041<18> B_SEL_P<13> VDD VSS / RSC_IHPSG13_INVX2 +XB_DEC3INV<12> net041<19> B_SEL_P<12> VDD VSS / RSC_IHPSG13_INVX2 +XB_DEC3INV<11> net041<20> B_SEL_P<11> VDD VSS / RSC_IHPSG13_INVX2 +XB_DEC3INV<10> net041<21> B_SEL_P<10> VDD VSS / RSC_IHPSG13_INVX2 +XB_DEC3INV<9> net041<22> B_SEL_P<9> VDD VSS / RSC_IHPSG13_INVX2 +XB_DEC3INV<8> net041<23> B_SEL_P<8> VDD VSS / RSC_IHPSG13_INVX2 +XB_DEC3INV<7> net041<24> B_SEL_P<7> VDD VSS / RSC_IHPSG13_INVX2 +XB_DEC3INV<6> net041<25> B_SEL_P<6> VDD VSS / RSC_IHPSG13_INVX2 +XB_DEC3INV<5> net041<26> B_SEL_P<5> VDD VSS / RSC_IHPSG13_INVX2 +XB_DEC3INV<4> net041<27> B_SEL_P<4> VDD VSS / RSC_IHPSG13_INVX2 +XB_DEC3INV<3> net041<28> B_SEL_P<3> VDD VSS / RSC_IHPSG13_INVX2 +XB_DEC3INV<2> net041<29> B_SEL_P<2> VDD VSS / RSC_IHPSG13_INVX2 +XB_DEC3INV<1> net041<30> B_SEL_P<1> VDD VSS / RSC_IHPSG13_INVX2 +XB_DEC3INV<0> net041<31> B_SEL_P<0> VDD VSS / RSC_IHPSG13_INVX2 +XB_I49 B_DI_R B_DI_N VDD VSS / RSC_IHPSG13_INVX2 +XA_I83 A_BM_R A_BM_N VDD VSS / RSC_IHPSG13_INVX2 +XA_DEC3INV<31> net23<0> A_SEL_P<31> VDD VSS / RSC_IHPSG13_INVX2 +XA_DEC3INV<30> net23<1> A_SEL_P<30> VDD VSS / RSC_IHPSG13_INVX2 +XA_DEC3INV<29> net23<2> A_SEL_P<29> VDD VSS / RSC_IHPSG13_INVX2 +XA_DEC3INV<28> net23<3> A_SEL_P<28> VDD VSS / RSC_IHPSG13_INVX2 +XA_DEC3INV<27> net23<4> A_SEL_P<27> VDD VSS / RSC_IHPSG13_INVX2 +XA_DEC3INV<26> net23<5> A_SEL_P<26> VDD VSS / RSC_IHPSG13_INVX2 +XA_DEC3INV<25> net23<6> A_SEL_P<25> VDD VSS / RSC_IHPSG13_INVX2 +XA_DEC3INV<24> net23<7> A_SEL_P<24> VDD VSS / RSC_IHPSG13_INVX2 +XA_DEC3INV<23> net23<8> A_SEL_P<23> VDD VSS / RSC_IHPSG13_INVX2 +XA_DEC3INV<22> net23<9> A_SEL_P<22> VDD VSS / RSC_IHPSG13_INVX2 +XA_DEC3INV<21> net23<10> A_SEL_P<21> VDD VSS / RSC_IHPSG13_INVX2 +XA_DEC3INV<20> net23<11> A_SEL_P<20> VDD VSS / RSC_IHPSG13_INVX2 +XA_DEC3INV<19> net23<12> A_SEL_P<19> VDD VSS / RSC_IHPSG13_INVX2 +XA_DEC3INV<18> net23<13> A_SEL_P<18> VDD VSS / RSC_IHPSG13_INVX2 +XA_DEC3INV<17> net23<14> A_SEL_P<17> VDD VSS / RSC_IHPSG13_INVX2 +XA_DEC3INV<16> net23<15> A_SEL_P<16> VDD VSS / RSC_IHPSG13_INVX2 +XA_DEC3INV<15> net23<16> A_SEL_P<15> VDD VSS / RSC_IHPSG13_INVX2 +XA_DEC3INV<14> net23<17> A_SEL_P<14> VDD VSS / RSC_IHPSG13_INVX2 +XA_DEC3INV<13> net23<18> A_SEL_P<13> VDD VSS / RSC_IHPSG13_INVX2 +XA_DEC3INV<12> net23<19> A_SEL_P<12> VDD VSS / RSC_IHPSG13_INVX2 +XA_DEC3INV<11> net23<20> A_SEL_P<11> VDD VSS / RSC_IHPSG13_INVX2 +XA_DEC3INV<10> net23<21> A_SEL_P<10> VDD VSS / RSC_IHPSG13_INVX2 +XA_DEC3INV<9> net23<22> A_SEL_P<9> VDD VSS / RSC_IHPSG13_INVX2 +XA_DEC3INV<8> net23<23> A_SEL_P<8> VDD VSS / RSC_IHPSG13_INVX2 +XA_DEC3INV<7> net23<24> A_SEL_P<7> VDD VSS / RSC_IHPSG13_INVX2 +XA_DEC3INV<6> net23<25> A_SEL_P<6> VDD VSS / RSC_IHPSG13_INVX2 +XA_DEC3INV<5> net23<26> A_SEL_P<5> VDD VSS / RSC_IHPSG13_INVX2 +XA_DEC3INV<4> net23<27> A_SEL_P<4> VDD VSS / RSC_IHPSG13_INVX2 +XA_DEC3INV<3> net23<28> A_SEL_P<3> VDD VSS / RSC_IHPSG13_INVX2 +XA_DEC3INV<2> net23<29> A_SEL_P<2> VDD VSS / RSC_IHPSG13_INVX2 +XA_DEC3INV<1> net23<30> A_SEL_P<1> VDD VSS / RSC_IHPSG13_INVX2 +XA_DEC3INV<0> net23<31> A_SEL_P<0> VDD VSS / RSC_IHPSG13_INVX2 +XA_I49 A_DI_R A_DI_N VDD VSS / RSC_IHPSG13_INVX2 +XB_ISENSE B_SAE B_BLC_SEL B_BLT_SEL net037 net038 VDD VSS / ++ RSC_IHPSG13_DFPQD_MSAFFX2 +XA_ISENSE A_SAE A_BLC_SEL A_BLT_SEL net19 net20 VDD VSS / ++ RSC_IHPSG13_DFPQD_MSAFFX2 +XB_DREG B_BIST_EN_I B_BIST_DW_I B_DCLK_B_L B_DW_I B_DI_R net042 VDD ++ VSS / RSC_IHPSG13_DFNQMX2IX1 +XB_BREG B_BIST_EN_I B_BIST_BM_I B_DCLK_B_L B_BM_I B_BM_R net043 VDD ++ VSS / RSC_IHPSG13_DFNQMX2IX1 +XA_DREG A_BIST_EN_I A_BIST_DW_I A_DCLK_B_L A_DW_I A_DI_R net22 VDD VSS ++ / RSC_IHPSG13_DFNQMX2IX1 +XA_BREG A_BIST_EN_I A_BIST_BM_I A_DCLK_B_L A_BM_I A_BM_R net21 VDD VSS ++ / RSC_IHPSG13_DFNQMX2IX1 +XB_DEC3<31> B_P1<1> B_P0<1> B_ADDR_DEC<7> net041<0> VDD VSS / ++ RSC_IHPSG13_NAND3X2 +XB_DEC3<30> B_P1<1> B_P0<1> B_ADDR_DEC<6> net041<1> VDD VSS / ++ RSC_IHPSG13_NAND3X2 +XB_DEC3<29> B_P1<1> B_P0<1> B_ADDR_DEC<5> net041<2> VDD VSS / ++ RSC_IHPSG13_NAND3X2 +XB_DEC3<28> B_P1<1> B_P0<1> B_ADDR_DEC<4> net041<3> VDD VSS / ++ RSC_IHPSG13_NAND3X2 +XB_DEC3<27> B_P1<1> B_P0<1> B_ADDR_DEC<3> net041<4> VDD VSS / ++ RSC_IHPSG13_NAND3X2 +XB_DEC3<26> B_P1<1> B_P0<1> B_ADDR_DEC<2> net041<5> VDD VSS / ++ RSC_IHPSG13_NAND3X2 +XB_DEC3<25> B_P1<1> B_P0<1> B_ADDR_DEC<1> net041<6> VDD VSS / ++ RSC_IHPSG13_NAND3X2 +XB_DEC3<24> B_P1<1> B_P0<1> B_ADDR_DEC<0> net041<7> VDD VSS / ++ RSC_IHPSG13_NAND3X2 +XB_DEC3<23> B_P1<1> B_N0<1> B_ADDR_DEC<7> net041<8> VDD VSS / ++ RSC_IHPSG13_NAND3X2 +XB_DEC3<22> B_P1<1> B_N0<1> B_ADDR_DEC<6> net041<9> VDD VSS / ++ RSC_IHPSG13_NAND3X2 +XB_DEC3<21> B_P1<1> B_N0<1> B_ADDR_DEC<5> net041<10> VDD VSS / ++ RSC_IHPSG13_NAND3X2 +XB_DEC3<20> B_P1<1> B_N0<1> B_ADDR_DEC<4> net041<11> VDD VSS / ++ RSC_IHPSG13_NAND3X2 +XB_DEC3<19> B_P1<1> B_N0<1> B_ADDR_DEC<3> net041<12> VDD VSS / ++ RSC_IHPSG13_NAND3X2 +XB_DEC3<18> B_P1<1> B_N0<1> B_ADDR_DEC<2> net041<13> VDD VSS / ++ RSC_IHPSG13_NAND3X2 +XB_DEC3<17> B_P1<1> B_N0<1> B_ADDR_DEC<1> net041<14> VDD VSS / ++ RSC_IHPSG13_NAND3X2 +XB_DEC3<16> B_P1<1> B_N0<1> B_ADDR_DEC<0> net041<15> VDD VSS / ++ RSC_IHPSG13_NAND3X2 +XB_DEC3<15> B_N1<0> B_P0<0> B_ADDR_DEC<7> net041<16> VDD VSS / ++ RSC_IHPSG13_NAND3X2 +XB_DEC3<14> B_N1<0> B_P0<0> B_ADDR_DEC<6> net041<17> VDD VSS / ++ RSC_IHPSG13_NAND3X2 +XB_DEC3<13> B_N1<0> B_P0<0> B_ADDR_DEC<5> net041<18> VDD VSS / ++ RSC_IHPSG13_NAND3X2 +XB_DEC3<12> B_N1<0> B_P0<0> B_ADDR_DEC<4> net041<19> VDD VSS / ++ RSC_IHPSG13_NAND3X2 +XB_DEC3<11> B_N1<0> B_P0<0> B_ADDR_DEC<3> net041<20> VDD VSS / ++ RSC_IHPSG13_NAND3X2 +XB_DEC3<10> B_N1<0> B_P0<0> B_ADDR_DEC<2> net041<21> VDD VSS / ++ RSC_IHPSG13_NAND3X2 +XB_DEC3<9> B_N1<0> B_P0<0> B_ADDR_DEC<1> net041<22> VDD VSS / ++ RSC_IHPSG13_NAND3X2 +XB_DEC3<8> B_N1<0> B_P0<0> B_ADDR_DEC<0> net041<23> VDD VSS / ++ RSC_IHPSG13_NAND3X2 +XB_DEC3<7> B_N1<0> B_N0<0> B_ADDR_DEC<7> net041<24> VDD VSS / ++ RSC_IHPSG13_NAND3X2 +XB_DEC3<6> B_N1<0> B_N0<0> B_ADDR_DEC<6> net041<25> VDD VSS / ++ RSC_IHPSG13_NAND3X2 +XB_DEC3<5> B_N1<0> B_N0<0> B_ADDR_DEC<5> net041<26> VDD VSS / ++ RSC_IHPSG13_NAND3X2 +XB_DEC3<4> B_N1<0> B_N0<0> B_ADDR_DEC<4> net041<27> VDD VSS / ++ RSC_IHPSG13_NAND3X2 +XB_DEC3<3> B_N1<0> B_N0<0> B_ADDR_DEC<3> net041<28> VDD VSS / ++ RSC_IHPSG13_NAND3X2 +XB_DEC3<2> B_N1<0> B_N0<0> B_ADDR_DEC<2> net041<29> VDD VSS / ++ RSC_IHPSG13_NAND3X2 +XB_DEC3<1> B_N1<0> B_N0<0> B_ADDR_DEC<1> net041<30> VDD VSS / ++ RSC_IHPSG13_NAND3X2 +XB_DEC3<0> B_N1<0> B_N0<0> B_ADDR_DEC<0> net041<31> VDD VSS / ++ RSC_IHPSG13_NAND3X2 +XA_DEC3<31> A_P1<1> A_P0<1> A_ADDR_DEC<7> net23<0> VDD VSS / ++ RSC_IHPSG13_NAND3X2 +XA_DEC3<30> A_P1<1> A_P0<1> A_ADDR_DEC<6> net23<1> VDD VSS / ++ RSC_IHPSG13_NAND3X2 +XA_DEC3<29> A_P1<1> A_P0<1> A_ADDR_DEC<5> net23<2> VDD VSS / ++ RSC_IHPSG13_NAND3X2 +XA_DEC3<28> A_P1<1> A_P0<1> A_ADDR_DEC<4> net23<3> VDD VSS / ++ RSC_IHPSG13_NAND3X2 +XA_DEC3<27> A_P1<1> A_P0<1> A_ADDR_DEC<3> net23<4> VDD VSS / ++ RSC_IHPSG13_NAND3X2 +XA_DEC3<26> A_P1<1> A_P0<1> A_ADDR_DEC<2> net23<5> VDD VSS / ++ RSC_IHPSG13_NAND3X2 +XA_DEC3<25> A_P1<1> A_P0<1> A_ADDR_DEC<1> net23<6> VDD VSS / ++ RSC_IHPSG13_NAND3X2 +XA_DEC3<24> A_P1<1> A_P0<1> A_ADDR_DEC<0> net23<7> VDD VSS / ++ RSC_IHPSG13_NAND3X2 +XA_DEC3<23> A_P1<1> A_N0<1> A_ADDR_DEC<7> net23<8> VDD VSS / ++ RSC_IHPSG13_NAND3X2 +XA_DEC3<22> A_P1<1> A_N0<1> A_ADDR_DEC<6> net23<9> VDD VSS / ++ RSC_IHPSG13_NAND3X2 +XA_DEC3<21> A_P1<1> A_N0<1> A_ADDR_DEC<5> net23<10> VDD VSS / ++ RSC_IHPSG13_NAND3X2 +XA_DEC3<20> A_P1<1> A_N0<1> A_ADDR_DEC<4> net23<11> VDD VSS / ++ RSC_IHPSG13_NAND3X2 +XA_DEC3<19> A_P1<1> A_N0<1> A_ADDR_DEC<3> net23<12> VDD VSS / ++ RSC_IHPSG13_NAND3X2 +XA_DEC3<18> A_P1<1> A_N0<1> A_ADDR_DEC<2> net23<13> VDD VSS / ++ RSC_IHPSG13_NAND3X2 +XA_DEC3<17> A_P1<1> A_N0<1> A_ADDR_DEC<1> net23<14> VDD VSS / ++ RSC_IHPSG13_NAND3X2 +XA_DEC3<16> A_P1<1> A_N0<1> A_ADDR_DEC<0> net23<15> VDD VSS / ++ RSC_IHPSG13_NAND3X2 +XA_DEC3<15> A_N1<0> A_P0<0> A_ADDR_DEC<7> net23<16> VDD VSS / ++ RSC_IHPSG13_NAND3X2 +XA_DEC3<14> A_N1<0> A_P0<0> A_ADDR_DEC<6> net23<17> VDD VSS / ++ RSC_IHPSG13_NAND3X2 +XA_DEC3<13> A_N1<0> A_P0<0> A_ADDR_DEC<5> net23<18> VDD VSS / ++ RSC_IHPSG13_NAND3X2 +XA_DEC3<12> A_N1<0> A_P0<0> A_ADDR_DEC<4> net23<19> VDD VSS / ++ RSC_IHPSG13_NAND3X2 +XA_DEC3<11> A_N1<0> A_P0<0> A_ADDR_DEC<3> net23<20> VDD VSS / ++ RSC_IHPSG13_NAND3X2 +XA_DEC3<10> A_N1<0> A_P0<0> A_ADDR_DEC<2> net23<21> VDD VSS / ++ RSC_IHPSG13_NAND3X2 +XA_DEC3<9> A_N1<0> A_P0<0> A_ADDR_DEC<1> net23<22> VDD VSS / ++ RSC_IHPSG13_NAND3X2 +XA_DEC3<8> A_N1<0> A_P0<0> A_ADDR_DEC<0> net23<23> VDD VSS / ++ RSC_IHPSG13_NAND3X2 +XA_DEC3<7> A_N1<0> A_N0<0> A_ADDR_DEC<7> net23<24> VDD VSS / ++ RSC_IHPSG13_NAND3X2 +XA_DEC3<6> A_N1<0> A_N0<0> A_ADDR_DEC<6> net23<25> VDD VSS / ++ RSC_IHPSG13_NAND3X2 +XA_DEC3<5> A_N1<0> A_N0<0> A_ADDR_DEC<5> net23<26> VDD VSS / ++ RSC_IHPSG13_NAND3X2 +XA_DEC3<4> A_N1<0> A_N0<0> A_ADDR_DEC<4> net23<27> VDD VSS / ++ RSC_IHPSG13_NAND3X2 +XA_DEC3<3> A_N1<0> A_N0<0> A_ADDR_DEC<3> net23<28> VDD VSS / ++ RSC_IHPSG13_NAND3X2 +XA_DEC3<2> A_N1<0> A_N0<0> A_ADDR_DEC<2> net23<29> VDD VSS / ++ RSC_IHPSG13_NAND3X2 +XA_DEC3<1> A_N1<0> A_N0<0> A_ADDR_DEC<1> net23<30> VDD VSS / ++ RSC_IHPSG13_NAND3X2 +XA_DEC3<0> A_N1<0> A_N0<0> A_ADDR_DEC<0> net23<31> VDD VSS / ++ RSC_IHPSG13_NAND3X2 +XB_I89 B_DCLK_B_L B_DCLK_B_R / RSC_IHPSG13_MET3RES +XB_I91 B_RCLK_B_L B_RCLK_B_R / RSC_IHPSG13_MET3RES +XB_I90 B_WCLK_B_L B_WCLK_B_R / RSC_IHPSG13_MET3RES +XB_I88 B_DCLK_L B_DCLK_R / RSC_IHPSG13_MET3RES +XB_I87 B_WCLK_L B_WCLK_R / RSC_IHPSG13_MET3RES +XB_R2 B_RCLK_L B_RCLK_R / RSC_IHPSG13_MET3RES +XA_I89 A_DCLK_B_L A_DCLK_B_R / RSC_IHPSG13_MET3RES +XA_I91 A_RCLK_B_L A_RCLK_B_R / RSC_IHPSG13_MET3RES +XA_I90 A_WCLK_B_L A_WCLK_B_R / RSC_IHPSG13_MET3RES +XA_I88 A_DCLK_L A_DCLK_R / RSC_IHPSG13_MET3RES +XA_I87 A_WCLK_L A_WCLK_R / RSC_IHPSG13_MET3RES +XA_R2 A_RCLK_L A_RCLK_R / RSC_IHPSG13_MET3RES +XB_BM_TIEH B_TIEH_O VDD VSS / RSC_IHPSG13_TIEH +XA_BM_TIEH A_TIEH_O VDD VSS / RSC_IHPSG13_TIEH +.ENDS +.SUBCKT RM_IHPSG13_256x32_c2_2P_COLDRV13_FILL4 VDD VSS +XI0<11> VDD VSS / RSC_IHPSG13_FILLCAP4 +XI0<10> VDD VSS / RSC_IHPSG13_FILLCAP4 +XI0<9> VDD VSS / RSC_IHPSG13_FILLCAP4 +XI0<8> VDD VSS / RSC_IHPSG13_FILLCAP4 +XI0<7> VDD VSS / RSC_IHPSG13_FILLCAP4 +XI0<6> VDD VSS / RSC_IHPSG13_FILLCAP4 +XI0<5> VDD VSS / RSC_IHPSG13_FILLCAP4 +XI0<4> VDD VSS / RSC_IHPSG13_FILLCAP4 +XI0<3> VDD VSS / RSC_IHPSG13_FILLCAP4 +XI0<2> VDD VSS / RSC_IHPSG13_FILLCAP4 +XI0<1> VDD VSS / RSC_IHPSG13_FILLCAP4 +.ENDS + + +.SUBCKT RSC_IHPSG13_CBUFX16 A Z VDD VSS +MN0 net4 A VSS VSS sg13_lv_nmos m=1 w=2.115u l=130.00n ng=3 nrd=0 nrs=0 +MN1 Z net4 VSS VSS sg13_lv_nmos m=1 w=5.64u l=130.00n ng=8 nrd=0 nrs=0 +MP1 Z net4 VDD VDD sg13_lv_pmos m=1 w=13.000u l=130.00n ng=8 nrd=0 ++ nrs=0 +MP0 net4 A VDD VDD sg13_lv_pmos m=1 w=4.89u l=130.00n ng=3 nrd=0 nrs=0 +.ENDS +.SUBCKT RM_IHPSG13_256x32_c2_1P_COLDRV13X16 ADDR_COL_I<1> ADDR_COL_I<0> ADDR_COL_O<1> ++ ADDR_COL_O<0> ADDR_DEC_I<7> ADDR_DEC_I<6> ADDR_DEC_I<5> ADDR_DEC_I<4> ++ ADDR_DEC_I<3> ADDR_DEC_I<2> ADDR_DEC_I<1> ADDR_DEC_I<0> ADDR_DEC_O<7> ++ ADDR_DEC_O<6> ADDR_DEC_O<5> ADDR_DEC_O<4> ADDR_DEC_O<3> ADDR_DEC_O<2> ++ ADDR_DEC_O<1> ADDR_DEC_O<0> DCLK_I DCLK_O RCLK_I RCLK_O WCLK_I WCLK_O ++ VDD VSS +XI1<1> VDD VSS / RSC_IHPSG13_FILLCAP4 +XI1<0> VDD VSS / RSC_IHPSG13_FILLCAP4 +XI0<3> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI0<2> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI0<1> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI0<0> VDD VSS / RSC_IHPSG13_FILLCAP8 +XADDR_COL_DRV<1> ADDR_COL_I<1> ADDR_COL_O<1> VDD VSS / ++ RSC_IHPSG13_CBUFX16 +XADDR_COL_DRV<0> ADDR_COL_I<0> ADDR_COL_O<0> VDD VSS / ++ RSC_IHPSG13_CBUFX16 +XADDR_DEC_DRV<7> ADDR_DEC_I<7> ADDR_DEC_O<7> VDD VSS / ++ RSC_IHPSG13_CBUFX16 +XADDR_DEC_DRV<6> ADDR_DEC_I<6> ADDR_DEC_O<6> VDD VSS / ++ RSC_IHPSG13_CBUFX16 +XADDR_DEC_DRV<5> ADDR_DEC_I<5> ADDR_DEC_O<5> VDD VSS / ++ RSC_IHPSG13_CBUFX16 +XADDR_DEC_DRV<4> ADDR_DEC_I<4> ADDR_DEC_O<4> VDD VSS / ++ RSC_IHPSG13_CBUFX16 +XADDR_DEC_DRV<3> ADDR_DEC_I<3> ADDR_DEC_O<3> VDD VSS / ++ RSC_IHPSG13_CBUFX16 +XADDR_DEC_DRV<2> ADDR_DEC_I<2> ADDR_DEC_O<2> VDD VSS / ++ RSC_IHPSG13_CBUFX16 +XADDR_DEC_DRV<1> ADDR_DEC_I<1> ADDR_DEC_O<1> VDD VSS / ++ RSC_IHPSG13_CBUFX16 +XADDR_DEC_DRV<0> ADDR_DEC_I<0> ADDR_DEC_O<0> VDD VSS / ++ RSC_IHPSG13_CBUFX16 +XDCLK_DRV DCLK_I DCLK_O VDD VSS / RSC_IHPSG13_CBUFX16 +XRCLK_DRV RCLK_I RCLK_O VDD VSS / RSC_IHPSG13_CBUFX16 +XWCLK_DRV WCLK_I WCLK_O VDD VSS / RSC_IHPSG13_CBUFX16 +.ENDS +.SUBCKT RSC_IHPSG13_WLDRVX16 A Z VDD VSS +MN1 Z net6 VSS VSS sg13_lv_nmos m=1 w=1.41u l=130.00n ng=2 nrd=0 nrs=0 +MN0 net6 A VSS VSS sg13_lv_nmos m=1 w=1.8u l=130.00n ng=2 nrd=0 nrs=0 +MP1 Z net6 VDD VDD sg13_lv_pmos m=1 w=12.96u l=130.00n ng=8 nrd=0 nrs=0 +MP0 net6 A VDD VDD sg13_lv_pmos m=1 w=900.0n l=130.00n ng=1 nrd=0 nrs=0 +.ENDS +.SUBCKT RM_IHPSG13_256x32_c2_1P_WLDRV16X16 A<15> A<14> A<13> A<12> A<11> A<10> A<9> A<8> ++ A<7> A<6> A<5> A<4> A<3> A<2> A<1> A<0> Z<15> Z<14> Z<13> Z<12> Z<11> Z<10> ++ Z<9> Z<8> Z<7> Z<6> Z<5> Z<4> Z<3> Z<2> Z<1> Z<0> VDD VSS +XBUF<15> A<15> Z<15> VDD VSS / RSC_IHPSG13_WLDRVX16 +XBUF<14> A<14> Z<14> VDD VSS / RSC_IHPSG13_WLDRVX16 +XBUF<13> A<13> Z<13> VDD VSS / RSC_IHPSG13_WLDRVX16 +XBUF<12> A<12> Z<12> VDD VSS / RSC_IHPSG13_WLDRVX16 +XBUF<11> A<11> Z<11> VDD VSS / RSC_IHPSG13_WLDRVX16 +XBUF<10> A<10> Z<10> VDD VSS / RSC_IHPSG13_WLDRVX16 +XBUF<9> A<9> Z<9> VDD VSS / RSC_IHPSG13_WLDRVX16 +XBUF<8> A<8> Z<8> VDD VSS / RSC_IHPSG13_WLDRVX16 +XBUF<7> A<7> Z<7> VDD VSS / RSC_IHPSG13_WLDRVX16 +XBUF<6> A<6> Z<6> VDD VSS / RSC_IHPSG13_WLDRVX16 +XBUF<5> A<5> Z<5> VDD VSS / RSC_IHPSG13_WLDRVX16 +XBUF<4> A<4> Z<4> VDD VSS / RSC_IHPSG13_WLDRVX16 +XBUF<3> A<3> Z<3> VDD VSS / RSC_IHPSG13_WLDRVX16 +XBUF<2> A<2> Z<2> VDD VSS / RSC_IHPSG13_WLDRVX16 +XBUF<1> A<1> Z<1> VDD VSS / RSC_IHPSG13_WLDRVX16 +XBUF<0> A<0> Z<0> VDD VSS / RSC_IHPSG13_WLDRVX16 +.ENDS + + +.SUBCKT RM_IHPSG13_256x32_c2_2P_COLDRV13X4 ADDR_COL_I<1> ADDR_COL_I<0> ADDR_COL_O<1> ++ ADDR_COL_O<0> ADDR_DEC_I<7> ADDR_DEC_I<6> ADDR_DEC_I<5> ADDR_DEC_I<4> ++ ADDR_DEC_I<3> ADDR_DEC_I<2> ADDR_DEC_I<1> ADDR_DEC_I<0> ADDR_DEC_O<7> ++ ADDR_DEC_O<6> ADDR_DEC_O<5> ADDR_DEC_O<4> ADDR_DEC_O<3> ADDR_DEC_O<2> ++ ADDR_DEC_O<1> ADDR_DEC_O<0> DCLK_I DCLK_O RCLK_I RCLK_O WCLK_I WCLK_O ++ VDD VSS +XWCLK_DRV WCLK_I WCLK_O VDD VSS / RSC_IHPSG13_CBUFX4 +XRCLK_DRV RCLK_I RCLK_O VDD VSS / RSC_IHPSG13_CBUFX4 +XDCLK_DRV DCLK_I DCLK_O VDD VSS / RSC_IHPSG13_CBUFX4 +XADDR_COL_DRV<1> ADDR_COL_I<1> ADDR_COL_O<1> VDD VSS / ++ RSC_IHPSG13_CBUFX4 +XADDR_COL_DRV<0> ADDR_COL_I<0> ADDR_COL_O<0> VDD VSS / ++ RSC_IHPSG13_CBUFX4 +XADDR_DEC_DRV<7> ADDR_DEC_I<7> ADDR_DEC_O<7> VDD VSS / ++ RSC_IHPSG13_CBUFX4 +XADDR_DEC_DRV<6> ADDR_DEC_I<6> ADDR_DEC_O<6> VDD VSS / ++ RSC_IHPSG13_CBUFX4 +XADDR_DEC_DRV<5> ADDR_DEC_I<5> ADDR_DEC_O<5> VDD VSS / ++ RSC_IHPSG13_CBUFX4 +XADDR_DEC_DRV<4> ADDR_DEC_I<4> ADDR_DEC_O<4> VDD VSS / ++ RSC_IHPSG13_CBUFX4 +XADDR_DEC_DRV<3> ADDR_DEC_I<3> ADDR_DEC_O<3> VDD VSS / ++ RSC_IHPSG13_CBUFX4 +XADDR_DEC_DRV<2> ADDR_DEC_I<2> ADDR_DEC_O<2> VDD VSS / ++ RSC_IHPSG13_CBUFX4 +XADDR_DEC_DRV<1> ADDR_DEC_I<1> ADDR_DEC_O<1> VDD VSS / ++ RSC_IHPSG13_CBUFX4 +XADDR_DEC_DRV<0> ADDR_DEC_I<0> ADDR_DEC_O<0> VDD VSS / ++ RSC_IHPSG13_CBUFX4 +XI0<6> VDD VSS / RSC_IHPSG13_FILLCAP4 +XI0<5> VDD VSS / RSC_IHPSG13_FILLCAP4 +XI0<4> VDD VSS / RSC_IHPSG13_FILLCAP4 +XI0<3> VDD VSS / RSC_IHPSG13_FILLCAP4 +XI0<2> VDD VSS / RSC_IHPSG13_FILLCAP4 +XI0<1> VDD VSS / RSC_IHPSG13_FILLCAP4 +XI1 VDD VSS / RSC_IHPSG13_FILLCAP8 +.ENDS +.SUBCKT RM_IHPSG13_256x32_c2_2P_WLDRV16X4 A<15> A<14> A<13> A<12> A<11> A<10> A<9> A<8> ++ A<7> A<6> A<5> A<4> A<3> A<2> A<1> A<0> Z<15> Z<14> Z<13> Z<12> Z<11> Z<10> ++ Z<9> Z<8> Z<7> Z<6> Z<5> Z<4> Z<3> Z<2> Z<1> Z<0> VDD VSS +XBUF<15> A<15> Z<15> VDD VSS / RSC_IHPSG13_WLDRVX4 +XBUF<14> A<14> Z<14> VDD VSS / RSC_IHPSG13_WLDRVX4 +XBUF<13> A<13> Z<13> VDD VSS / RSC_IHPSG13_WLDRVX4 +XBUF<12> A<12> Z<12> VDD VSS / RSC_IHPSG13_WLDRVX4 +XBUF<11> A<11> Z<11> VDD VSS / RSC_IHPSG13_WLDRVX4 +XBUF<10> A<10> Z<10> VDD VSS / RSC_IHPSG13_WLDRVX4 +XBUF<9> A<9> Z<9> VDD VSS / RSC_IHPSG13_WLDRVX4 +XBUF<8> A<8> Z<8> VDD VSS / RSC_IHPSG13_WLDRVX4 +XBUF<7> A<7> Z<7> VDD VSS / RSC_IHPSG13_WLDRVX4 +XBUF<6> A<6> Z<6> VDD VSS / RSC_IHPSG13_WLDRVX4 +XBUF<5> A<5> Z<5> VDD VSS / RSC_IHPSG13_WLDRVX4 +XBUF<4> A<4> Z<4> VDD VSS / RSC_IHPSG13_WLDRVX4 +XBUF<3> A<3> Z<3> VDD VSS / RSC_IHPSG13_WLDRVX4 +XBUF<2> A<2> Z<2> VDD VSS / RSC_IHPSG13_WLDRVX4 +XBUF<1> A<1> Z<1> VDD VSS / RSC_IHPSG13_WLDRVX4 +XBUF<0> A<0> Z<0> VDD VSS / RSC_IHPSG13_WLDRVX4 +.ENDS +.SUBCKT RM_IHPSG13_256x32_c2_2P_ROWDEC8 ADDR_N_I<7> ADDR_N_I<6> ADDR_N_I<5> ADDR_N_I<4> ++ ADDR_N_I<3> ADDR_N_I<2> ADDR_N_I<1> ADDR_N_I<0> CS_I ECLK_I WL_O<255> ++ WL_O<254> WL_O<253> WL_O<252> WL_O<251> WL_O<250> WL_O<249> WL_O<248> ++ WL_O<247> WL_O<246> WL_O<245> WL_O<244> WL_O<243> WL_O<242> WL_O<241> ++ WL_O<240> WL_O<239> WL_O<238> WL_O<237> WL_O<236> WL_O<235> WL_O<234> ++ WL_O<233> WL_O<232> WL_O<231> WL_O<230> WL_O<229> WL_O<228> WL_O<227> ++ WL_O<226> WL_O<225> WL_O<224> WL_O<223> WL_O<222> WL_O<221> WL_O<220> ++ WL_O<219> WL_O<218> WL_O<217> WL_O<216> WL_O<215> WL_O<214> WL_O<213> ++ WL_O<212> WL_O<211> WL_O<210> WL_O<209> WL_O<208> WL_O<207> WL_O<206> ++ WL_O<205> WL_O<204> WL_O<203> WL_O<202> WL_O<201> WL_O<200> WL_O<199> ++ WL_O<198> WL_O<197> WL_O<196> WL_O<195> WL_O<194> WL_O<193> WL_O<192> ++ WL_O<191> WL_O<190> WL_O<189> WL_O<188> WL_O<187> WL_O<186> WL_O<185> ++ WL_O<184> WL_O<183> WL_O<182> WL_O<181> WL_O<180> WL_O<179> WL_O<178> ++ WL_O<177> WL_O<176> WL_O<175> WL_O<174> WL_O<173> WL_O<172> WL_O<171> ++ WL_O<170> WL_O<169> WL_O<168> WL_O<167> WL_O<166> WL_O<165> WL_O<164> ++ WL_O<163> WL_O<162> WL_O<161> WL_O<160> WL_O<159> WL_O<158> WL_O<157> ++ WL_O<156> WL_O<155> WL_O<154> WL_O<153> WL_O<152> WL_O<151> WL_O<150> ++ WL_O<149> WL_O<148> WL_O<147> WL_O<146> WL_O<145> WL_O<144> WL_O<143> ++ WL_O<142> WL_O<141> WL_O<140> WL_O<139> WL_O<138> WL_O<137> WL_O<136> ++ WL_O<135> WL_O<134> WL_O<133> WL_O<132> WL_O<131> WL_O<130> WL_O<129> ++ WL_O<128> WL_O<127> WL_O<126> WL_O<125> WL_O<124> WL_O<123> WL_O<122> ++ WL_O<121> WL_O<120> WL_O<119> WL_O<118> WL_O<117> WL_O<116> WL_O<115> ++ WL_O<114> WL_O<113> WL_O<112> WL_O<111> WL_O<110> WL_O<109> WL_O<108> ++ WL_O<107> WL_O<106> WL_O<105> WL_O<104> WL_O<103> WL_O<102> WL_O<101> ++ WL_O<100> WL_O<99> WL_O<98> WL_O<97> WL_O<96> WL_O<95> WL_O<94> WL_O<93> ++ WL_O<92> WL_O<91> WL_O<90> WL_O<89> WL_O<88> WL_O<87> WL_O<86> WL_O<85> ++ WL_O<84> WL_O<83> WL_O<82> WL_O<81> WL_O<80> WL_O<79> WL_O<78> WL_O<77> ++ WL_O<76> WL_O<75> WL_O<74> WL_O<73> WL_O<72> WL_O<71> WL_O<70> WL_O<69> ++ WL_O<68> WL_O<67> WL_O<66> WL_O<65> WL_O<64> WL_O<63> WL_O<62> WL_O<61> ++ WL_O<60> WL_O<59> WL_O<58> WL_O<57> WL_O<56> WL_O<55> WL_O<54> WL_O<53> ++ WL_O<52> WL_O<51> WL_O<50> WL_O<49> WL_O<48> WL_O<47> WL_O<46> WL_O<45> ++ WL_O<44> WL_O<43> WL_O<42> WL_O<41> WL_O<40> WL_O<39> WL_O<38> WL_O<37> ++ WL_O<36> WL_O<35> WL_O<34> WL_O<33> WL_O<32> WL_O<31> WL_O<30> WL_O<29> ++ WL_O<28> WL_O<27> WL_O<26> WL_O<25> WL_O<24> WL_O<23> WL_O<22> WL_O<21> ++ WL_O<20> WL_O<19> WL_O<18> WL_O<17> WL_O<16> WL_O<15> WL_O<14> WL_O<13> ++ WL_O<12> WL_O<11> WL_O<10> WL_O<9> WL_O<8> WL_O<7> WL_O<6> WL_O<5> WL_O<4> ++ WL_O<3> WL_O<2> WL_O<1> WL_O<0> VDD VSS +XDEC11<4> ADDR_N_I<7> ADDR_N_I<6> CS_I CS04<3> VDD VSS / ++ RM_IHPSG13_256x32_c2_2P_DEC03 +XDEC11<3> ADDR_N_I<5> ADDR_N_I<4> CS04<3> CS00<15> VDD VSS / ++ RM_IHPSG13_256x32_c2_2P_DEC03 +XDEC11<2> ADDR_N_I<5> ADDR_N_I<4> CS04<2> CS00<11> VDD VSS / ++ RM_IHPSG13_256x32_c2_2P_DEC03 +XDEC11<1> ADDR_N_I<5> ADDR_N_I<4> CS04<1> CS00<7> VDD VSS / ++ RM_IHPSG13_256x32_c2_2P_DEC03 +XDEC11<0> ADDR_N_I<5> ADDR_N_I<4> CS04<0> CS00<3> VDD VSS / ++ RM_IHPSG13_256x32_c2_2P_DEC03 +XSEL<15> ADDR_N_I<3> ADDR_N_I<2> ADDR_N_I<1> ADDR_N_I<0> CS00<15> ECLK_H<15> ++ ECLK_H<16> ECLK_B<15> ECLK_B<16> WL_O<255> WL_O<254> WL_O<253> WL_O<252> ++ WL_O<251> WL_O<250> WL_O<249> WL_O<248> WL_O<247> WL_O<246> WL_O<245> ++ WL_O<244> WL_O<243> WL_O<242> WL_O<241> WL_O<240> VDD VSS / ++ RM_IHPSG13_256x32_c2_2P_DEC04 +XSEL<14> ADDR_N_I<3> ADDR_N_I<2> ADDR_N_I<1> ADDR_N_I<0> CS00<14> ECLK_H<14> ++ ECLK_H<15> ECLK_B<14> ECLK_B<15> WL_O<239> WL_O<238> WL_O<237> WL_O<236> ++ WL_O<235> WL_O<234> WL_O<233> WL_O<232> WL_O<231> WL_O<230> WL_O<229> ++ WL_O<228> WL_O<227> WL_O<226> WL_O<225> WL_O<224> VDD VSS / ++ RM_IHPSG13_256x32_c2_2P_DEC04 +XSEL<13> ADDR_N_I<3> ADDR_N_I<2> ADDR_N_I<1> ADDR_N_I<0> CS00<13> ECLK_H<13> ++ ECLK_H<14> ECLK_B<13> ECLK_B<14> WL_O<223> WL_O<222> WL_O<221> WL_O<220> ++ WL_O<219> WL_O<218> WL_O<217> WL_O<216> WL_O<215> WL_O<214> WL_O<213> ++ WL_O<212> WL_O<211> WL_O<210> WL_O<209> WL_O<208> VDD VSS / ++ RM_IHPSG13_256x32_c2_2P_DEC04 +XSEL<12> ADDR_N_I<3> ADDR_N_I<2> ADDR_N_I<1> ADDR_N_I<0> CS00<12> ECLK_H<12> ++ ECLK_H<13> ECLK_B<12> ECLK_B<13> WL_O<207> WL_O<206> WL_O<205> WL_O<204> ++ WL_O<203> WL_O<202> WL_O<201> WL_O<200> WL_O<199> WL_O<198> WL_O<197> ++ WL_O<196> WL_O<195> WL_O<194> WL_O<193> WL_O<192> VDD VSS / ++ RM_IHPSG13_256x32_c2_2P_DEC04 +XSEL<11> ADDR_N_I<3> ADDR_N_I<2> ADDR_N_I<1> ADDR_N_I<0> CS00<11> ECLK_H<11> ++ ECLK_H<12> ECLK_B<11> ECLK_B<12> WL_O<191> WL_O<190> WL_O<189> WL_O<188> ++ WL_O<187> WL_O<186> WL_O<185> WL_O<184> WL_O<183> WL_O<182> WL_O<181> ++ WL_O<180> WL_O<179> WL_O<178> WL_O<177> WL_O<176> VDD VSS / ++ RM_IHPSG13_256x32_c2_2P_DEC04 +XSEL<10> ADDR_N_I<3> ADDR_N_I<2> ADDR_N_I<1> ADDR_N_I<0> CS00<10> ECLK_H<10> ++ ECLK_H<11> ECLK_B<10> ECLK_B<11> WL_O<175> WL_O<174> WL_O<173> WL_O<172> ++ WL_O<171> WL_O<170> WL_O<169> WL_O<168> WL_O<167> WL_O<166> WL_O<165> ++ WL_O<164> WL_O<163> WL_O<162> WL_O<161> WL_O<160> VDD VSS / ++ RM_IHPSG13_256x32_c2_2P_DEC04 +XSEL<9> ADDR_N_I<3> ADDR_N_I<2> ADDR_N_I<1> ADDR_N_I<0> CS00<9> ECLK_H<9> ++ ECLK_H<10> ECLK_B<9> ECLK_B<10> WL_O<159> WL_O<158> WL_O<157> WL_O<156> ++ WL_O<155> WL_O<154> WL_O<153> WL_O<152> WL_O<151> WL_O<150> WL_O<149> ++ WL_O<148> WL_O<147> WL_O<146> WL_O<145> WL_O<144> VDD VSS / ++ RM_IHPSG13_256x32_c2_2P_DEC04 +XSEL<8> ADDR_N_I<3> ADDR_N_I<2> ADDR_N_I<1> ADDR_N_I<0> CS00<8> ECLK_H<8> ++ ECLK_H<9> ECLK_B<8> ECLK_B<9> WL_O<143> WL_O<142> WL_O<141> WL_O<140> ++ WL_O<139> WL_O<138> WL_O<137> WL_O<136> WL_O<135> WL_O<134> WL_O<133> ++ WL_O<132> WL_O<131> WL_O<130> WL_O<129> WL_O<128> VDD VSS / ++ RM_IHPSG13_256x32_c2_2P_DEC04 +XSEL<7> ADDR_N_I<3> ADDR_N_I<2> ADDR_N_I<1> ADDR_N_I<0> CS00<7> ECLK_H<7> ++ ECLK_H<8> ECLK_B<7> ECLK_B<8> WL_O<127> WL_O<126> WL_O<125> WL_O<124> ++ WL_O<123> WL_O<122> WL_O<121> WL_O<120> WL_O<119> WL_O<118> WL_O<117> ++ WL_O<116> WL_O<115> WL_O<114> WL_O<113> WL_O<112> VDD VSS / ++ RM_IHPSG13_256x32_c2_2P_DEC04 +XSEL<6> ADDR_N_I<3> ADDR_N_I<2> ADDR_N_I<1> ADDR_N_I<0> CS00<6> ECLK_H<6> ++ ECLK_H<7> ECLK_B<6> ECLK_B<7> WL_O<111> WL_O<110> WL_O<109> WL_O<108> ++ WL_O<107> WL_O<106> WL_O<105> WL_O<104> WL_O<103> WL_O<102> WL_O<101> ++ WL_O<100> WL_O<99> WL_O<98> WL_O<97> WL_O<96> VDD VSS / ++ RM_IHPSG13_256x32_c2_2P_DEC04 +XSEL<5> ADDR_N_I<3> ADDR_N_I<2> ADDR_N_I<1> ADDR_N_I<0> CS00<5> ECLK_H<5> ++ ECLK_H<6> ECLK_B<5> ECLK_B<6> WL_O<95> WL_O<94> WL_O<93> WL_O<92> WL_O<91> ++ WL_O<90> WL_O<89> WL_O<88> WL_O<87> WL_O<86> WL_O<85> WL_O<84> WL_O<83> ++ WL_O<82> WL_O<81> WL_O<80> VDD VSS / RM_IHPSG13_256x32_c2_2P_DEC04 +XSEL<4> ADDR_N_I<3> ADDR_N_I<2> ADDR_N_I<1> ADDR_N_I<0> CS00<4> ECLK_H<4> ++ ECLK_H<5> ECLK_B<4> ECLK_B<5> WL_O<79> WL_O<78> WL_O<77> WL_O<76> WL_O<75> ++ WL_O<74> WL_O<73> WL_O<72> WL_O<71> WL_O<70> WL_O<69> WL_O<68> WL_O<67> ++ WL_O<66> WL_O<65> WL_O<64> VDD VSS / RM_IHPSG13_256x32_c2_2P_DEC04 +XSEL<3> ADDR_N_I<3> ADDR_N_I<2> ADDR_N_I<1> ADDR_N_I<0> CS00<3> ECLK_H<3> ++ ECLK_H<4> ECLK_B<3> ECLK_B<4> WL_O<63> WL_O<62> WL_O<61> WL_O<60> WL_O<59> ++ WL_O<58> WL_O<57> WL_O<56> WL_O<55> WL_O<54> WL_O<53> WL_O<52> WL_O<51> ++ WL_O<50> WL_O<49> WL_O<48> VDD VSS / RM_IHPSG13_256x32_c2_2P_DEC04 +XSEL<2> ADDR_N_I<3> ADDR_N_I<2> ADDR_N_I<1> ADDR_N_I<0> CS00<2> ECLK_H<2> ++ ECLK_H<3> ECLK_B<2> ECLK_B<3> WL_O<47> WL_O<46> WL_O<45> WL_O<44> WL_O<43> ++ WL_O<42> WL_O<41> WL_O<40> WL_O<39> WL_O<38> WL_O<37> WL_O<36> WL_O<35> ++ WL_O<34> WL_O<33> WL_O<32> VDD VSS / RM_IHPSG13_256x32_c2_2P_DEC04 +XSEL<1> ADDR_N_I<3> ADDR_N_I<2> ADDR_N_I<1> ADDR_N_I<0> CS00<1> ECLK_H<1> ++ ECLK_H<2> ECLK_B<1> ECLK_B<2> WL_O<31> WL_O<30> WL_O<29> WL_O<28> WL_O<27> ++ WL_O<26> WL_O<25> WL_O<24> WL_O<23> WL_O<22> WL_O<21> WL_O<20> WL_O<19> ++ WL_O<18> WL_O<17> WL_O<16> VDD VSS / RM_IHPSG13_256x32_c2_2P_DEC04 +XSEL<0> ADDR_N_I<3> ADDR_N_I<2> ADDR_N_I<1> ADDR_N_I<0> CS00<0> ECLK_I ++ ECLK_H<1> ECLK_B<0> ECLK_B<1> WL_O<15> WL_O<14> WL_O<13> WL_O<12> WL_O<11> ++ WL_O<10> WL_O<9> WL_O<8> WL_O<7> WL_O<6> WL_O<5> WL_O<4> WL_O<3> WL_O<2> ++ WL_O<1> WL_O<0> VDD VSS / RM_IHPSG13_256x32_c2_2P_DEC04 +XDEC10<4> ADDR_N_I<7> ADDR_N_I<6> CS_I CS04<2> VDD VSS / ++ RM_IHPSG13_256x32_c2_2P_DEC02 +XDEC10<3> ADDR_N_I<5> ADDR_N_I<4> CS04<3> CS00<14> VDD VSS / ++ RM_IHPSG13_256x32_c2_2P_DEC02 +XDEC10<2> ADDR_N_I<5> ADDR_N_I<4> CS04<2> CS00<10> VDD VSS / ++ RM_IHPSG13_256x32_c2_2P_DEC02 +XDEC10<1> ADDR_N_I<5> ADDR_N_I<4> CS04<1> CS00<6> VDD VSS / ++ RM_IHPSG13_256x32_c2_2P_DEC02 +XDEC10<0> ADDR_N_I<5> ADDR_N_I<4> CS04<0> CS00<2> VDD VSS / ++ RM_IHPSG13_256x32_c2_2P_DEC02 +XL2<132> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<131> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<130> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<129> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<128> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<127> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<126> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<125> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<124> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<123> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<122> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<121> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<120> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<119> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<118> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<117> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<116> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<115> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<114> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<113> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<112> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<111> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<110> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<109> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<108> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<107> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<106> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<105> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<104> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<103> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<102> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<101> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<100> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<99> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<98> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<97> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<96> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<95> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<94> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<93> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<92> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<91> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<90> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<89> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<88> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<87> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<86> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<85> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<84> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<83> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<82> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<81> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<80> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<79> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<78> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<77> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<76> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<75> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<74> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<73> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<72> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<71> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<70> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<69> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<68> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<67> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<66> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<65> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<64> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<63> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<62> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<61> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<60> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<59> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<58> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<57> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<56> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<55> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<54> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<53> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<52> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<51> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<50> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<49> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<48> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<47> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<46> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<45> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<44> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<43> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<42> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<41> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<40> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<39> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<38> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<37> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<36> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<35> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<34> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<33> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<32> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<31> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<30> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<29> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<28> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<27> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<26> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<25> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<24> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<23> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<22> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<21> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<20> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<19> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<18> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<17> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<16> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<15> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<14> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<13> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<12> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<11> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<10> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<9> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<8> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<7> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<6> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<5> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<4> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<3> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<2> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<1> VDD VSS / RSC_IHPSG13_FILLCAP8 +XDEC00<4> ADDR_N_I<7> ADDR_N_I<6> CS_I CS04<0> VDD VSS / ++ RM_IHPSG13_256x32_c2_2P_DEC00 +XDEC00<3> ADDR_N_I<5> ADDR_N_I<4> CS04<3> CS00<12> VDD VSS / ++ RM_IHPSG13_256x32_c2_2P_DEC00 +XDEC00<2> ADDR_N_I<5> ADDR_N_I<4> CS04<2> CS00<8> VDD VSS / ++ RM_IHPSG13_256x32_c2_2P_DEC00 +XDEC00<1> ADDR_N_I<5> ADDR_N_I<4> CS04<1> CS00<4> VDD VSS / ++ RM_IHPSG13_256x32_c2_2P_DEC00 +XDEC00<0> ADDR_N_I<5> ADDR_N_I<4> CS04<0> CS00<0> VDD VSS / ++ RM_IHPSG13_256x32_c2_2P_DEC00 +XDEC01<4> ADDR_N_I<7> ADDR_N_I<6> CS_I CS04<1> VDD VSS / ++ RM_IHPSG13_256x32_c2_2P_DEC01 +XDEC01<3> ADDR_N_I<5> ADDR_N_I<4> CS04<3> CS00<13> VDD VSS / ++ RM_IHPSG13_256x32_c2_2P_DEC01 +XDEC01<2> ADDR_N_I<5> ADDR_N_I<4> CS04<2> CS00<9> VDD VSS / ++ RM_IHPSG13_256x32_c2_2P_DEC01 +XDEC01<1> ADDR_N_I<5> ADDR_N_I<4> CS04<1> CS00<5> VDD VSS / ++ RM_IHPSG13_256x32_c2_2P_DEC01 +XDEC01<0> ADDR_N_I<5> ADDR_N_I<4> CS04<0> CS00<1> VDD VSS / ++ RM_IHPSG13_256x32_c2_2P_DEC01 +.ENDS +.SUBCKT RM_IHPSG13_256x32_c2_2P_ROWREG8 ACLK_N_I ADDR_I<7> ADDR_I<6> ADDR_I<5> ADDR_I<4> ++ ADDR_I<3> ADDR_I<2> ADDR_I<1> ADDR_I<0> ADDR_N_O<7> ADDR_N_O<6> ADDR_N_O<5> ++ ADDR_N_O<4> ADDR_N_O<3> ADDR_N_O<2> ADDR_N_O<1> ADDR_N_O<0> BIST_ADDR_I<7> ++ BIST_ADDR_I<6> BIST_ADDR_I<5> BIST_ADDR_I<4> BIST_ADDR_I<3> BIST_ADDR_I<2> ++ BIST_ADDR_I<1> BIST_ADDR_I<0> BIST_EN_I VDD VSS +XINV<7> q_int<7> qn_int<7> VDD VSS / RSC_IHPSG13_CINVX2 +XINV<6> q_int<6> qn_int<6> VDD VSS / RSC_IHPSG13_CINVX2 +XINV<5> q_int<5> qn_int<5> VDD VSS / RSC_IHPSG13_CINVX2 +XINV<4> q_int<4> qn_int<4> VDD VSS / RSC_IHPSG13_CINVX2 +XINV<3> q_int<3> qn_int<3> VDD VSS / RSC_IHPSG13_CINVX2 +XINV<2> q_int<2> qn_int<2> VDD VSS / RSC_IHPSG13_CINVX2 +XINV<1> q_int<1> qn_int<1> VDD VSS / RSC_IHPSG13_CINVX2 +XINV<0> q_int<0> qn_int<0> VDD VSS / RSC_IHPSG13_CINVX2 +XDRV<7> qn_int<7> ADDR_N_O<7> VDD VSS / RSC_IHPSG13_CINVX8 +XDRV<6> qn_int<6> ADDR_N_O<6> VDD VSS / RSC_IHPSG13_CINVX8 +XDRV<5> qn_int<5> ADDR_N_O<5> VDD VSS / RSC_IHPSG13_CINVX8 +XDRV<4> qn_int<4> ADDR_N_O<4> VDD VSS / RSC_IHPSG13_CINVX8 +XDRV<3> qn_int<3> ADDR_N_O<3> VDD VSS / RSC_IHPSG13_CINVX8 +XDRV<2> qn_int<2> ADDR_N_O<2> VDD VSS / RSC_IHPSG13_CINVX8 +XDRV<1> qn_int<1> ADDR_N_O<1> VDD VSS / RSC_IHPSG13_CINVX8 +XDRV<0> qn_int<0> ADDR_N_O<0> VDD VSS / RSC_IHPSG13_CINVX8 +XDFF<7> BIST_EN_I BIST_ADDR_I<7> ACLK_N_I ADDR_I<7> q_int<7> net2<0> VDD ++ VSS / RSC_IHPSG13_DFNQMX2IX1 +XDFF<6> BIST_EN_I BIST_ADDR_I<6> ACLK_N_I ADDR_I<6> q_int<6> net2<1> VDD ++ VSS / RSC_IHPSG13_DFNQMX2IX1 +XDFF<5> BIST_EN_I BIST_ADDR_I<5> ACLK_N_I ADDR_I<5> q_int<5> net2<2> VDD ++ VSS / RSC_IHPSG13_DFNQMX2IX1 +XDFF<4> BIST_EN_I BIST_ADDR_I<4> ACLK_N_I ADDR_I<4> q_int<4> net2<3> VDD ++ VSS / RSC_IHPSG13_DFNQMX2IX1 +XDFF<3> BIST_EN_I BIST_ADDR_I<3> ACLK_N_I ADDR_I<3> q_int<3> net2<4> VDD ++ VSS / RSC_IHPSG13_DFNQMX2IX1 +XDFF<2> BIST_EN_I BIST_ADDR_I<2> ACLK_N_I ADDR_I<2> q_int<2> net2<5> VDD ++ VSS / RSC_IHPSG13_DFNQMX2IX1 +XDFF<1> BIST_EN_I BIST_ADDR_I<1> ACLK_N_I ADDR_I<1> q_int<1> net2<6> VDD ++ VSS / RSC_IHPSG13_DFNQMX2IX1 +XDFF<0> BIST_EN_I BIST_ADDR_I<0> ACLK_N_I ADDR_I<0> q_int<0> net2<7> VDD ++ VSS / RSC_IHPSG13_DFNQMX2IX1 +XI11<4> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI11<3> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI11<2> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI11<1> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI10 VDD VSS / RSC_IHPSG13_FILLCAP4 +.ENDS +.SUBCKT RM_IHPSG13_256x32_c2_2P_COLDEC4 ACLK_N ADDR<3> ADDR<2> ADDR<1> ADDR<0> ++ ADDR_COL<1> ADDR_COL<0> ADDR_DEC<7> ADDR_DEC<6> ADDR_DEC<5> ADDR_DEC<4> ++ ADDR_DEC<3> ADDR_DEC<2> ADDR_DEC<1> ADDR_DEC<0> BIST_ADDR<3> BIST_ADDR<2> ++ BIST_ADDR<1> BIST_ADDR<0> BIST_EN_I VDD VSS +XI1<7> PADR<0> PADR<1> PADR<2> addr_n<7> VDD VSS / RSC_IHPSG13_NAND3X2 +XI1<6> NADR<0> PADR<1> PADR<2> addr_n<6> VDD VSS / RSC_IHPSG13_NAND3X2 +XI1<5> PADR<0> NADR<1> PADR<2> addr_n<5> VDD VSS / RSC_IHPSG13_NAND3X2 +XI1<4> NADR<0> NADR<1> PADR<2> addr_n<4> VDD VSS / RSC_IHPSG13_NAND3X2 +XI1<3> PADR<0> PADR<1> NADR<2> addr_n<3> VDD VSS / RSC_IHPSG13_NAND3X2 +XI1<2> NADR<0> PADR<1> NADR<2> addr_n<2> VDD VSS / RSC_IHPSG13_NAND3X2 +XI1<1> PADR<0> NADR<1> NADR<2> addr_n<1> VDD VSS / RSC_IHPSG13_NAND3X2 +XI1<0> NADR<0> NADR<1> NADR<2> addr_n<0> VDD VSS / RSC_IHPSG13_NAND3X2 +XDFF<3> BIST_EN_I BIST_ADDR<3> ACLK_N ADDR<3> addr_int net12<0> VDD ++ VSS / RSC_IHPSG13_DFNQMX2IX1 +XDFF<2> BIST_EN_I BIST_ADDR<2> ACLK_N ADDR<2> padr_int<2> net12<1> VDD ++ VSS / RSC_IHPSG13_DFNQMX2IX1 +XDFF<1> BIST_EN_I BIST_ADDR<1> ACLK_N ADDR<1> padr_int<1> net12<2> VDD ++ VSS / RSC_IHPSG13_DFNQMX2IX1 +XDFF<0> BIST_EN_I BIST_ADDR<0> ACLK_N ADDR<0> padr_int<0> net12<3> VDD ++ VSS / RSC_IHPSG13_DFNQMX2IX1 +XI17<4> VDD VSS / RSC_IHPSG13_FILLCAP4 +XI17<3> VDD VSS / RSC_IHPSG13_FILLCAP4 +XI17<2> VDD VSS / RSC_IHPSG13_FILLCAP4 +XI17<1> VDD VSS / RSC_IHPSG13_FILLCAP4 +XI13<2> NADR<2> PADR<2> VDD VSS / RSC_IHPSG13_INVX2 +XI13<1> NADR<1> PADR<1> VDD VSS / RSC_IHPSG13_INVX2 +XI13<0> NADR<0> PADR<0> VDD VSS / RSC_IHPSG13_INVX2 +XI2<7> addr_n<7> ADDR_DEC<7> VDD VSS / RSC_IHPSG13_INVX2 +XI2<6> addr_n<6> ADDR_DEC<6> VDD VSS / RSC_IHPSG13_INVX2 +XI2<5> addr_n<5> ADDR_DEC<5> VDD VSS / RSC_IHPSG13_INVX2 +XI2<4> addr_n<4> ADDR_DEC<4> VDD VSS / RSC_IHPSG13_INVX2 +XI2<3> addr_n<3> ADDR_DEC<3> VDD VSS / RSC_IHPSG13_INVX2 +XI2<2> addr_n<2> ADDR_DEC<2> VDD VSS / RSC_IHPSG13_INVX2 +XI2<1> addr_n<1> ADDR_DEC<1> VDD VSS / RSC_IHPSG13_INVX2 +XI2<0> addr_n<0> ADDR_DEC<0> VDD VSS / RSC_IHPSG13_INVX2 +XI3<2> padr_int<2> NADR<2> VDD VSS / RSC_IHPSG13_INVX2 +XI3<1> padr_int<1> NADR<1> VDD VSS / RSC_IHPSG13_INVX2 +XI3<0> padr_int<0> NADR<0> VDD VSS / RSC_IHPSG13_INVX2 +XI14 addr_int ADDR_COL<0> VDD VSS / RSC_IHPSG13_CBUFX2 +XI16<8> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI16<7> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI16<6> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI16<5> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI16<4> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI16<3> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI16<2> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI16<1> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI15 ADDR_COL<1> VDD VSS / RSC_IHPSG13_TIEL +.ENDS +.SUBCKT RM_IHPSG13_256x32_c2_2P_COLCTRL4 A_ADDR_COL A_ADDR_DEC<7> A_ADDR_DEC<6> ++ A_ADDR_DEC<5> A_ADDR_DEC<4> A_ADDR_DEC<3> A_ADDR_DEC<2> A_ADDR_DEC<1> ++ A_ADDR_DEC<0> A_BIST_BM_I A_BIST_DW_I A_BIST_EN_I A_BLC<15> A_BLC<14> ++ A_BLC<13> A_BLC<12> A_BLC<11> A_BLC<10> A_BLC<9> A_BLC<8> A_BLC<7> A_BLC<6> ++ A_BLC<5> A_BLC<4> A_BLC<3> A_BLC<2> A_BLC<1> A_BLC<0> A_BLT<15> A_BLT<14> ++ A_BLT<13> A_BLT<12> A_BLT<11> A_BLT<10> A_BLT<9> A_BLT<8> A_BLT<7> A_BLT<6> ++ A_BLT<5> A_BLT<4> A_BLT<3> A_BLT<2> A_BLT<1> A_BLT<0> A_BM_I A_DCLK_B_L ++ A_DCLK_B_R A_DCLK_L A_DCLK_R A_DR_O A_DW_I A_RCLK_B_L A_RCLK_B_R A_RCLK_L ++ A_RCLK_R A_TIEH_O A_WCLK_B_L A_WCLK_B_R A_WCLK_L A_WCLK_R B_ADDR_COL ++ B_ADDR_DEC<7> B_ADDR_DEC<6> B_ADDR_DEC<5> B_ADDR_DEC<4> B_ADDR_DEC<3> ++ B_ADDR_DEC<2> B_ADDR_DEC<1> B_ADDR_DEC<0> B_BIST_BM_I B_BIST_DW_I ++ B_BIST_EN_I B_BLC<15> B_BLC<14> B_BLC<13> B_BLC<12> B_BLC<11> B_BLC<10> ++ B_BLC<9> B_BLC<8> B_BLC<7> B_BLC<6> B_BLC<5> B_BLC<4> B_BLC<3> B_BLC<2> ++ B_BLC<1> B_BLC<0> B_BLT<15> B_BLT<14> B_BLT<13> B_BLT<12> B_BLT<11> ++ B_BLT<10> B_BLT<9> B_BLT<8> B_BLT<7> B_BLT<6> B_BLT<5> B_BLT<4> B_BLT<3> ++ B_BLT<2> B_BLT<1> B_BLT<0> B_BM_I B_DCLK_B_L B_DCLK_B_R B_DCLK_L B_DCLK_R ++ B_DR_O B_DW_I B_RCLK_B_L B_RCLK_B_R B_RCLK_L B_RCLK_R B_TIEH_O B_WCLK_B_L ++ B_WCLK_B_R B_WCLK_L B_WCLK_R VDD VSS +XB_I80 B_RCLK_B_L B_WCLK_B_L net041 VDD VSS / RSC_IHPSG13_AND2X2 +XA_I80 A_RCLK_B_L A_WCLK_B_L net21 VDD VSS / RSC_IHPSG13_AND2X2 +XB_I76 B_DI_N B_DO_WRITE_P B_WR_ZERO VDD VSS / RSC_IHPSG13_AND2X4 +XB_I75 B_DI_R B_DO_WRITE_P B_WR_ONE VDD VSS / RSC_IHPSG13_AND2X4 +XA_I76 A_DI_N A_DO_WRITE_P A_WR_ZERO VDD VSS / RSC_IHPSG13_AND2X4 +XA_I75 A_DI_R A_DO_WRITE_P A_WR_ONE VDD VSS / RSC_IHPSG13_AND2X4 +XI_FILL4<26> VDD VSS / RSC_IHPSG13_FILLCAP4 +XI_FILL4<25> VDD VSS / RSC_IHPSG13_FILLCAP4 +XI_FILL4<24> VDD VSS / RSC_IHPSG13_FILLCAP4 +XI_FILL4<23> VDD VSS / RSC_IHPSG13_FILLCAP4 +XI_FILL4<22> VDD VSS / RSC_IHPSG13_FILLCAP4 +XI_FILL4<21> VDD VSS / RSC_IHPSG13_FILLCAP4 +XI_FILL4<20> VDD VSS / RSC_IHPSG13_FILLCAP4 +XI_FILL4<19> VDD VSS / RSC_IHPSG13_FILLCAP4 +XI_FILL4<18> VDD VSS / RSC_IHPSG13_FILLCAP4 +XI_FILL4<17> VDD VSS / RSC_IHPSG13_FILLCAP4 +XI_FILL4<16> VDD VSS / RSC_IHPSG13_FILLCAP4 +XI_FILL4<15> VDD VSS / RSC_IHPSG13_FILLCAP4 +XI_FILL4<14> VDD VSS / RSC_IHPSG13_FILLCAP4 +XI_FILL4<13> VDD VSS / RSC_IHPSG13_FILLCAP4 +XI_FILL4<12> VDD VSS / RSC_IHPSG13_FILLCAP4 +XI_FILL4<11> VDD VSS / RSC_IHPSG13_FILLCAP4 +XI_FILL4<10> VDD VSS / RSC_IHPSG13_FILLCAP4 +XI_FILL4<9> VDD VSS / RSC_IHPSG13_FILLCAP4 +XI_FILL4<8> VDD VSS / RSC_IHPSG13_FILLCAP4 +XI_FILL4<7> VDD VSS / RSC_IHPSG13_FILLCAP4 +XI_FILL4<6> VDD VSS / RSC_IHPSG13_FILLCAP4 +XI_FILL4<5> VDD VSS / RSC_IHPSG13_FILLCAP4 +XI_FILL4<4> VDD VSS / RSC_IHPSG13_FILLCAP4 +XI_FILL4<3> VDD VSS / RSC_IHPSG13_FILLCAP4 +XI_FILL4<2> VDD VSS / RSC_IHPSG13_FILLCAP4 +XI_FILL4<1> VDD VSS / RSC_IHPSG13_FILLCAP4 +XB_I69 B_DCLK_L B_DCLK_B_L VDD VSS / RSC_IHPSG13_CINVX4 +XB_I50 B_WCLK_L B_WCLK_B_L VDD VSS / RSC_IHPSG13_CINVX4 +XB_EBUF B_RCLK_L B_RCLK_B_L VDD VSS / RSC_IHPSG13_CINVX4 +XB_INV<1> B_N0 B_P0 VDD VSS / RSC_IHPSG13_CINVX4 +XB_INV<0> B_ADDR_COL B_N0 VDD VSS / RSC_IHPSG13_CINVX4 +XA_I69 A_DCLK_L A_DCLK_B_L VDD VSS / RSC_IHPSG13_CINVX4 +XA_I50 A_WCLK_L A_WCLK_B_L VDD VSS / RSC_IHPSG13_CINVX4 +XA_EBUF A_RCLK_L A_RCLK_B_L VDD VSS / RSC_IHPSG13_CINVX4 +XA_INV<1> A_N0 A_P0 VDD VSS / RSC_IHPSG13_CINVX4 +XA_INV<0> A_ADDR_COL A_N0 VDD VSS / RSC_IHPSG13_CINVX4 +XB_I81<1> net041 B_PRE_N VDD VSS / RSC_IHPSG13_CINVX4_WN +XB_I81<0> net041 B_PRE_N VDD VSS / RSC_IHPSG13_CINVX4_WN +XA_I81<1> net21 A_PRE_N VDD VSS / RSC_IHPSG13_CINVX4_WN +XA_I81<0> net21 A_PRE_N VDD VSS / RSC_IHPSG13_CINVX4_WN +XA_R2 A_RCLK_L A_RCLK_R / RSC_IHPSG13_MET3RES +XA_I87 A_WCLK_L A_WCLK_R / RSC_IHPSG13_MET3RES +XA_I88 A_DCLK_L A_DCLK_R / RSC_IHPSG13_MET3RES +XA_I89 A_DCLK_B_L A_DCLK_B_R / RSC_IHPSG13_MET3RES +XA_I90 A_WCLK_B_L A_WCLK_B_R / RSC_IHPSG13_MET3RES +XA_I91 A_RCLK_B_L A_RCLK_B_R / RSC_IHPSG13_MET3RES +XB_R2 B_RCLK_L B_RCLK_R / RSC_IHPSG13_MET3RES +XB_I87 B_WCLK_L B_WCLK_R / RSC_IHPSG13_MET3RES +XB_I88 B_DCLK_L B_DCLK_R / RSC_IHPSG13_MET3RES +XB_I89 B_DCLK_B_L B_DCLK_B_R / RSC_IHPSG13_MET3RES +XB_I90 B_WCLK_B_L B_WCLK_B_R / RSC_IHPSG13_MET3RES +XB_I91 B_RCLK_B_L B_RCLK_B_R / RSC_IHPSG13_MET3RES +XA_ISENSE A_SAE A_BLC_SEL A_BLT_SEL net19 net20 VDD VSS / ++ RSC_IHPSG13_DFPQD_MSAFFX2 +XB_ISENSE B_SAE B_BLC_SEL B_BLT_SEL net037 net038 VDD VSS / ++ RSC_IHPSG13_DFPQD_MSAFFX2 +XAB_BLMUX<3> A_BLC<15> A_BLC<14> A_BLC<13> A_BLC<12> A_BLC_SEL A_BLT<15> ++ A_BLT<14> A_BLT<13> A_BLT<12> A_BLT_SEL A_PRE_N A_SEL_P<15> A_SEL_P<14> ++ A_SEL_P<13> A_SEL_P<12> A_WR_ONE A_WR_ZERO B_BLC<15> B_BLC<14> B_BLC<13> ++ B_BLC<12> B_BLC_SEL B_BLT<15> B_BLT<14> B_BLT<13> B_BLT<12> B_BLT_SEL ++ B_PRE_N B_SEL_P<15> B_SEL_P<14> B_SEL_P<13> B_SEL_P<12> B_WR_ONE B_WR_ZERO ++ VDD VSS / RM_IHPSG13_256x32_c2_2P_BLDRV +XAB_BLMUX<2> A_BLC<11> A_BLC<10> A_BLC<9> A_BLC<8> A_BLC_SEL A_BLT<11> ++ A_BLT<10> A_BLT<9> A_BLT<8> A_BLT_SEL A_PRE_N A_SEL_P<11> A_SEL_P<10> ++ A_SEL_P<9> A_SEL_P<8> A_WR_ONE A_WR_ZERO B_BLC<11> B_BLC<10> B_BLC<9> ++ B_BLC<8> B_BLC_SEL B_BLT<11> B_BLT<10> B_BLT<9> B_BLT<8> B_BLT_SEL B_PRE_N ++ B_SEL_P<11> B_SEL_P<10> B_SEL_P<9> B_SEL_P<8> B_WR_ONE B_WR_ZERO VDD ++ VSS / RM_IHPSG13_256x32_c2_2P_BLDRV +XAB_BLMUX<1> A_BLC<7> A_BLC<6> A_BLC<5> A_BLC<4> A_BLC_SEL A_BLT<7> A_BLT<6> ++ A_BLT<5> A_BLT<4> A_BLT_SEL A_PRE_N A_SEL_P<7> A_SEL_P<6> A_SEL_P<5> ++ A_SEL_P<4> A_WR_ONE A_WR_ZERO B_BLC<7> B_BLC<6> B_BLC<5> B_BLC<4> B_BLC_SEL ++ B_BLT<7> B_BLT<6> B_BLT<5> B_BLT<4> B_BLT_SEL B_PRE_N B_SEL_P<7> B_SEL_P<6> ++ B_SEL_P<5> B_SEL_P<4> B_WR_ONE B_WR_ZERO VDD VSS / ++ RM_IHPSG13_256x32_c2_2P_BLDRV +XAB_BLMUX<0> A_BLC<3> A_BLC<2> A_BLC<1> A_BLC<0> A_BLC_SEL A_BLT<3> A_BLT<2> ++ A_BLT<1> A_BLT<0> A_BLT_SEL A_PRE_N A_SEL_P<3> A_SEL_P<2> A_SEL_P<1> ++ A_SEL_P<0> A_WR_ONE A_WR_ZERO B_BLC<3> B_BLC<2> B_BLC<1> B_BLC<0> B_BLC_SEL ++ B_BLT<3> B_BLT<2> B_BLT<1> B_BLT<0> B_BLT_SEL B_PRE_N B_SEL_P<3> B_SEL_P<2> ++ B_SEL_P<1> B_SEL_P<0> B_WR_ONE B_WR_ZERO VDD VSS / ++ RM_IHPSG13_256x32_c2_2P_BLDRV +XA_I51 net19 A_DR_O VDD VSS / RSC_IHPSG13_INVX4 +XB_I51 net037 B_DR_O VDD VSS / RSC_IHPSG13_INVX4 +XA_I78 A_RCLK_B_L A_SAE VDD VSS / RSC_IHPSG13_CBUFX2 +XB_I78 B_RCLK_B_L B_SAE VDD VSS / RSC_IHPSG13_CBUFX2 +XA_DREG A_BIST_EN_I A_BIST_DW_I A_DCLK_B_L A_DW_I A_DI_R net22 VDD VSS ++ / RSC_IHPSG13_DFNQMX2IX1 +XB_DREG B_BIST_EN_I B_BIST_DW_I B_DCLK_B_L B_DW_I B_DI_R net046 VDD ++ VSS / RSC_IHPSG13_DFNQMX2IX1 +XB_BREG B_BIST_EN_I B_BIST_BM_I B_DCLK_B_L B_BM_I B_BM_R net045 VDD ++ VSS / RSC_IHPSG13_DFNQMX2IX1 +XA_BREG A_BIST_EN_I A_BIST_BM_I A_DCLK_B_L A_BM_I A_BM_R net24 VDD VSS ++ / RSC_IHPSG13_DFNQMX2IX1 +XA_DEC3INV<15> net23<0> A_SEL_P<15> VDD VSS / RSC_IHPSG13_INVX2 +XA_DEC3INV<14> net23<1> A_SEL_P<14> VDD VSS / RSC_IHPSG13_INVX2 +XA_DEC3INV<13> net23<2> A_SEL_P<13> VDD VSS / RSC_IHPSG13_INVX2 +XA_DEC3INV<12> net23<3> A_SEL_P<12> VDD VSS / RSC_IHPSG13_INVX2 +XA_DEC3INV<11> net23<4> A_SEL_P<11> VDD VSS / RSC_IHPSG13_INVX2 +XA_DEC3INV<10> net23<5> A_SEL_P<10> VDD VSS / RSC_IHPSG13_INVX2 +XA_DEC3INV<9> net23<6> A_SEL_P<9> VDD VSS / RSC_IHPSG13_INVX2 +XA_DEC3INV<8> net23<7> A_SEL_P<8> VDD VSS / RSC_IHPSG13_INVX2 +XA_DEC3INV<7> net23<8> A_SEL_P<7> VDD VSS / RSC_IHPSG13_INVX2 +XA_DEC3INV<6> net23<9> A_SEL_P<6> VDD VSS / RSC_IHPSG13_INVX2 +XA_DEC3INV<5> net23<10> A_SEL_P<5> VDD VSS / RSC_IHPSG13_INVX2 +XA_DEC3INV<4> net23<11> A_SEL_P<4> VDD VSS / RSC_IHPSG13_INVX2 +XA_DEC3INV<3> net23<12> A_SEL_P<3> VDD VSS / RSC_IHPSG13_INVX2 +XA_DEC3INV<2> net23<13> A_SEL_P<2> VDD VSS / RSC_IHPSG13_INVX2 +XA_DEC3INV<1> net23<14> A_SEL_P<1> VDD VSS / RSC_IHPSG13_INVX2 +XA_DEC3INV<0> net23<15> A_SEL_P<0> VDD VSS / RSC_IHPSG13_INVX2 +XA_I83 A_BM_R A_BM_N VDD VSS / RSC_IHPSG13_INVX2 +XA_I49 A_DI_R A_DI_N VDD VSS / RSC_IHPSG13_INVX2 +XB_DEC3INV<15> net044<0> B_SEL_P<15> VDD VSS / RSC_IHPSG13_INVX2 +XB_DEC3INV<14> net044<1> B_SEL_P<14> VDD VSS / RSC_IHPSG13_INVX2 +XB_DEC3INV<13> net044<2> B_SEL_P<13> VDD VSS / RSC_IHPSG13_INVX2 +XB_DEC3INV<12> net044<3> B_SEL_P<12> VDD VSS / RSC_IHPSG13_INVX2 +XB_DEC3INV<11> net044<4> B_SEL_P<11> VDD VSS / RSC_IHPSG13_INVX2 +XB_DEC3INV<10> net044<5> B_SEL_P<10> VDD VSS / RSC_IHPSG13_INVX2 +XB_DEC3INV<9> net044<6> B_SEL_P<9> VDD VSS / RSC_IHPSG13_INVX2 +XB_DEC3INV<8> net044<7> B_SEL_P<8> VDD VSS / RSC_IHPSG13_INVX2 +XB_DEC3INV<7> net044<8> B_SEL_P<7> VDD VSS / RSC_IHPSG13_INVX2 +XB_DEC3INV<6> net044<9> B_SEL_P<6> VDD VSS / RSC_IHPSG13_INVX2 +XB_DEC3INV<5> net044<10> B_SEL_P<5> VDD VSS / RSC_IHPSG13_INVX2 +XB_DEC3INV<4> net044<11> B_SEL_P<4> VDD VSS / RSC_IHPSG13_INVX2 +XB_DEC3INV<3> net044<12> B_SEL_P<3> VDD VSS / RSC_IHPSG13_INVX2 +XB_DEC3INV<2> net044<13> B_SEL_P<2> VDD VSS / RSC_IHPSG13_INVX2 +XB_DEC3INV<1> net044<14> B_SEL_P<1> VDD VSS / RSC_IHPSG13_INVX2 +XB_DEC3INV<0> net044<15> B_SEL_P<0> VDD VSS / RSC_IHPSG13_INVX2 +XB_I83 B_BM_R B_BM_N VDD VSS / RSC_IHPSG13_INVX2 +XB_I49 B_DI_R B_DI_N VDD VSS / RSC_IHPSG13_INVX2 +XI_FILL8<20> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI_FILL8<19> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI_FILL8<18> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI_FILL8<17> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI_FILL8<16> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI_FILL8<15> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI_FILL8<14> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI_FILL8<13> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI_FILL8<12> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI_FILL8<11> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI_FILL8<10> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI_FILL8<9> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI_FILL8<8> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI_FILL8<7> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI_FILL8<6> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI_FILL8<5> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI_FILL8<4> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI_FILL8<3> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI_FILL8<2> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI_FILL8<1> VDD VSS / RSC_IHPSG13_FILLCAP8 +XA_I44 A_BM_N A_WCLK_B_L A_DO_WRITE_P VDD VSS / RSC_IHPSG13_NOR2X2 +XB_I44 B_BM_N B_WCLK_B_L B_DO_WRITE_P VDD VSS / RSC_IHPSG13_NOR2X2 +XA_DEC3<15> A_P0 A_ADDR_DEC<7> net23<0> VDD VSS / RSC_IHPSG13_NAND2X2 +XA_DEC3<14> A_P0 A_ADDR_DEC<6> net23<1> VDD VSS / RSC_IHPSG13_NAND2X2 +XA_DEC3<13> A_P0 A_ADDR_DEC<5> net23<2> VDD VSS / RSC_IHPSG13_NAND2X2 +XA_DEC3<12> A_P0 A_ADDR_DEC<4> net23<3> VDD VSS / RSC_IHPSG13_NAND2X2 +XA_DEC3<11> A_P0 A_ADDR_DEC<3> net23<4> VDD VSS / RSC_IHPSG13_NAND2X2 +XA_DEC3<10> A_P0 A_ADDR_DEC<2> net23<5> VDD VSS / RSC_IHPSG13_NAND2X2 +XA_DEC3<9> A_P0 A_ADDR_DEC<1> net23<6> VDD VSS / RSC_IHPSG13_NAND2X2 +XA_DEC3<8> A_P0 A_ADDR_DEC<0> net23<7> VDD VSS / RSC_IHPSG13_NAND2X2 +XA_DEC3<7> A_N0 A_ADDR_DEC<7> net23<8> VDD VSS / RSC_IHPSG13_NAND2X2 +XA_DEC3<6> A_N0 A_ADDR_DEC<6> net23<9> VDD VSS / RSC_IHPSG13_NAND2X2 +XA_DEC3<5> A_N0 A_ADDR_DEC<5> net23<10> VDD VSS / RSC_IHPSG13_NAND2X2 +XA_DEC3<4> A_N0 A_ADDR_DEC<4> net23<11> VDD VSS / RSC_IHPSG13_NAND2X2 +XA_DEC3<3> A_N0 A_ADDR_DEC<3> net23<12> VDD VSS / RSC_IHPSG13_NAND2X2 +XA_DEC3<2> A_N0 A_ADDR_DEC<2> net23<13> VDD VSS / RSC_IHPSG13_NAND2X2 +XA_DEC3<1> A_N0 A_ADDR_DEC<1> net23<14> VDD VSS / RSC_IHPSG13_NAND2X2 +XA_DEC3<0> A_N0 A_ADDR_DEC<0> net23<15> VDD VSS / RSC_IHPSG13_NAND2X2 +XB_DEC3<15> B_P0 B_ADDR_DEC<7> net044<0> VDD VSS / RSC_IHPSG13_NAND2X2 +XB_DEC3<14> B_P0 B_ADDR_DEC<6> net044<1> VDD VSS / RSC_IHPSG13_NAND2X2 +XB_DEC3<13> B_P0 B_ADDR_DEC<5> net044<2> VDD VSS / RSC_IHPSG13_NAND2X2 +XB_DEC3<12> B_P0 B_ADDR_DEC<4> net044<3> VDD VSS / RSC_IHPSG13_NAND2X2 +XB_DEC3<11> B_P0 B_ADDR_DEC<3> net044<4> VDD VSS / RSC_IHPSG13_NAND2X2 +XB_DEC3<10> B_P0 B_ADDR_DEC<2> net044<5> VDD VSS / RSC_IHPSG13_NAND2X2 +XB_DEC3<9> B_P0 B_ADDR_DEC<1> net044<6> VDD VSS / RSC_IHPSG13_NAND2X2 +XB_DEC3<8> B_P0 B_ADDR_DEC<0> net044<7> VDD VSS / RSC_IHPSG13_NAND2X2 +XB_DEC3<7> B_N0 B_ADDR_DEC<7> net044<8> VDD VSS / RSC_IHPSG13_NAND2X2 +XB_DEC3<6> B_N0 B_ADDR_DEC<6> net044<9> VDD VSS / RSC_IHPSG13_NAND2X2 +XB_DEC3<5> B_N0 B_ADDR_DEC<5> net044<10> VDD VSS / RSC_IHPSG13_NAND2X2 +XB_DEC3<4> B_N0 B_ADDR_DEC<4> net044<11> VDD VSS / RSC_IHPSG13_NAND2X2 +XB_DEC3<3> B_N0 B_ADDR_DEC<3> net044<12> VDD VSS / RSC_IHPSG13_NAND2X2 +XB_DEC3<2> B_N0 B_ADDR_DEC<2> net044<13> VDD VSS / RSC_IHPSG13_NAND2X2 +XB_DEC3<1> B_N0 B_ADDR_DEC<1> net044<14> VDD VSS / RSC_IHPSG13_NAND2X2 +XB_DEC3<0> B_N0 B_ADDR_DEC<0> net044<15> VDD VSS / RSC_IHPSG13_NAND2X2 +XB_BM_TIEH B_TIEH_O VDD VSS / RSC_IHPSG13_TIEH +XA_BM_TIEH A_TIEH_O VDD VSS / RSC_IHPSG13_TIEH +.ENDS + + +.SUBCKT RM_IHPSG13_256x32_c2_2P_ROWDEC5 ADDR_N_I<4> ADDR_N_I<3> ADDR_N_I<2> ADDR_N_I<1> ++ ADDR_N_I<0> CS_I ECLK_I WL_O<31> WL_O<30> WL_O<29> WL_O<28> WL_O<27> ++ WL_O<26> WL_O<25> WL_O<24> WL_O<23> WL_O<22> WL_O<21> WL_O<20> WL_O<19> ++ WL_O<18> WL_O<17> WL_O<16> WL_O<15> WL_O<14> WL_O<13> WL_O<12> WL_O<11> ++ WL_O<10> WL_O<9> WL_O<8> WL_O<7> WL_O<6> WL_O<5> WL_O<4> WL_O<3> WL_O<2> ++ WL_O<1> WL_O<0> VDD VSS +XDEC00 ADDR_N_I<5> ADDR_N_I<4> CS_I CS00<0> VDD VSS / ++ RM_IHPSG13_256x32_c2_2P_DEC00 +XSEL<1> ADDR_N_I<3> ADDR_N_I<2> ADDR_N_I<1> ADDR_N_I<0> CS00<1> ECLK_H<1> ++ ECLK_H<2> ECLK_B<1> ECLK_B<2> WL_O<31> WL_O<30> WL_O<29> WL_O<28> WL_O<27> ++ WL_O<26> WL_O<25> WL_O<24> WL_O<23> WL_O<22> WL_O<21> WL_O<20> WL_O<19> ++ WL_O<18> WL_O<17> WL_O<16> VDD VSS / RM_IHPSG13_256x32_c2_2P_DEC04 +XSEL<0> ADDR_N_I<3> ADDR_N_I<2> ADDR_N_I<1> ADDR_N_I<0> CS00<0> ECLK_I ++ ECLK_H<1> ECLK_B<0> ECLK_B<1> WL_O<15> WL_O<14> WL_O<13> WL_O<12> WL_O<11> ++ WL_O<10> WL_O<9> WL_O<8> WL_O<7> WL_O<6> WL_O<5> WL_O<4> WL_O<3> WL_O<2> ++ WL_O<1> WL_O<0> VDD VSS / RM_IHPSG13_256x32_c2_2P_DEC04 +XDEC01 ADDR_N_I<5> ADDR_N_I<4> CS_I CS00<1> VDD VSS / ++ RM_IHPSG13_256x32_c2_2P_DEC01 +XL2<18> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<17> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<16> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<15> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<14> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<13> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<12> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<11> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<10> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<9> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<8> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<7> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<6> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<5> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<4> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<3> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<2> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<1> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI0 ADDR_N_I<5> VDD VSS / RSC_IHPSG13_TIEL +.ENDS +.SUBCKT RM_IHPSG13_256x32_c2_2P_ROWREG5 ACLK_N_I ADDR_I<4> ADDR_I<3> ADDR_I<2> ADDR_I<1> ++ ADDR_I<0> ADDR_N_O<4> ADDR_N_O<3> ADDR_N_O<2> ADDR_N_O<1> ADDR_N_O<0> ++ BIST_ADDR_I<4> BIST_ADDR_I<3> BIST_ADDR_I<2> BIST_ADDR_I<1> BIST_ADDR_I<0> ++ BIST_EN_I VDD VSS +XINV<4> q_int<4> qn_int<4> VDD VSS / RSC_IHPSG13_CINVX2 +XINV<3> q_int<3> qn_int<3> VDD VSS / RSC_IHPSG13_CINVX2 +XINV<2> q_int<2> qn_int<2> VDD VSS / RSC_IHPSG13_CINVX2 +XINV<1> q_int<1> qn_int<1> VDD VSS / RSC_IHPSG13_CINVX2 +XINV<0> q_int<0> qn_int<0> VDD VSS / RSC_IHPSG13_CINVX2 +XDRV<4> qn_int<4> ADDR_N_O<4> VDD VSS / RSC_IHPSG13_CINVX8 +XDRV<3> qn_int<3> ADDR_N_O<3> VDD VSS / RSC_IHPSG13_CINVX8 +XDRV<2> qn_int<2> ADDR_N_O<2> VDD VSS / RSC_IHPSG13_CINVX8 +XDRV<1> qn_int<1> ADDR_N_O<1> VDD VSS / RSC_IHPSG13_CINVX8 +XDRV<0> qn_int<0> ADDR_N_O<0> VDD VSS / RSC_IHPSG13_CINVX8 +XDFF<4> BIST_EN_I BIST_ADDR_I<4> ACLK_N_I ADDR_I<4> q_int<4> net2<0> VDD ++ VSS / RSC_IHPSG13_DFNQMX2IX1 +XDFF<3> BIST_EN_I BIST_ADDR_I<3> ACLK_N_I ADDR_I<3> q_int<3> net2<1> VDD ++ VSS / RSC_IHPSG13_DFNQMX2IX1 +XDFF<2> BIST_EN_I BIST_ADDR_I<2> ACLK_N_I ADDR_I<2> q_int<2> net2<2> VDD ++ VSS / RSC_IHPSG13_DFNQMX2IX1 +XDFF<1> BIST_EN_I BIST_ADDR_I<1> ACLK_N_I ADDR_I<1> q_int<1> net2<3> VDD ++ VSS / RSC_IHPSG13_DFNQMX2IX1 +XDFF<0> BIST_EN_I BIST_ADDR_I<0> ACLK_N_I ADDR_I<0> q_int<0> net2<4> VDD ++ VSS / RSC_IHPSG13_DFNQMX2IX1 +XI11<16> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI11<15> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI11<14> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI11<13> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI11<12> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI11<11> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI11<10> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI11<9> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI11<8> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI11<7> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI11<6> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI11<5> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI11<4> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI11<3> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI11<2> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI11<1> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI12<3> VDD VSS / RSC_IHPSG13_FILLCAP4 +XI12<2> VDD VSS / RSC_IHPSG13_FILLCAP4 +XI12<1> VDD VSS / RSC_IHPSG13_FILLCAP4 +XI12<0> VDD VSS / RSC_IHPSG13_FILLCAP4 +.ENDS + + +.SUBCKT RM_IHPSG13_256x32_c2_2P_COLDEC3 ACLK_N ADDR<2> ADDR<1> ADDR<0> ADDR_COL<1> ++ ADDR_COL<0> ADDR_DEC<7> ADDR_DEC<6> ADDR_DEC<5> ADDR_DEC<4> ADDR_DEC<3> ++ ADDR_DEC<2> ADDR_DEC<1> ADDR_DEC<0> BIST_ADDR<2> BIST_ADDR<1> BIST_ADDR<0> ++ BIST_EN_I VDD VSS +XI1<7> PADR<0> PADR<1> PADR<2> addr_n<7> VDD VSS / RSC_IHPSG13_NAND3X2 +XI1<6> NADR<0> PADR<1> PADR<2> addr_n<6> VDD VSS / RSC_IHPSG13_NAND3X2 +XI1<5> PADR<0> NADR<1> PADR<2> addr_n<5> VDD VSS / RSC_IHPSG13_NAND3X2 +XI1<4> NADR<0> NADR<1> PADR<2> addr_n<4> VDD VSS / RSC_IHPSG13_NAND3X2 +XI1<3> PADR<0> PADR<1> NADR<2> addr_n<3> VDD VSS / RSC_IHPSG13_NAND3X2 +XI1<2> NADR<0> PADR<1> NADR<2> addr_n<2> VDD VSS / RSC_IHPSG13_NAND3X2 +XI1<1> PADR<0> NADR<1> NADR<2> addr_n<1> VDD VSS / RSC_IHPSG13_NAND3X2 +XI1<0> NADR<0> NADR<1> NADR<2> addr_n<0> VDD VSS / RSC_IHPSG13_NAND3X2 +XDFF<2> BIST_EN_I BIST_ADDR<2> ACLK_N ADDR<2> padr_int<2> net13<0> VDD ++ VSS / RSC_IHPSG13_DFNQMX2IX1 +XDFF<1> BIST_EN_I BIST_ADDR<1> ACLK_N ADDR<1> padr_int<1> net13<1> VDD ++ VSS / RSC_IHPSG13_DFNQMX2IX1 +XDFF<0> BIST_EN_I BIST_ADDR<0> ACLK_N ADDR<0> padr_int<0> net13<2> VDD ++ VSS / RSC_IHPSG13_DFNQMX2IX1 +XI15<1> ADDR_COL<1> VDD VSS / RSC_IHPSG13_TIEL +XI15<0> ADDR_COL<0> VDD VSS / RSC_IHPSG13_TIEL +XI13<2> NADR<2> PADR<2> VDD VSS / RSC_IHPSG13_INVX2 +XI13<1> NADR<1> PADR<1> VDD VSS / RSC_IHPSG13_INVX2 +XI13<0> NADR<0> PADR<0> VDD VSS / RSC_IHPSG13_INVX2 +XI3<2> padr_int<2> NADR<2> VDD VSS / RSC_IHPSG13_INVX2 +XI3<1> padr_int<1> NADR<1> VDD VSS / RSC_IHPSG13_INVX2 +XI3<0> padr_int<0> NADR<0> VDD VSS / RSC_IHPSG13_INVX2 +XI2<7> addr_n<7> ADDR_DEC<7> VDD VSS / RSC_IHPSG13_INVX2 +XI2<6> addr_n<6> ADDR_DEC<6> VDD VSS / RSC_IHPSG13_INVX2 +XI2<5> addr_n<5> ADDR_DEC<5> VDD VSS / RSC_IHPSG13_INVX2 +XI2<4> addr_n<4> ADDR_DEC<4> VDD VSS / RSC_IHPSG13_INVX2 +XI2<3> addr_n<3> ADDR_DEC<3> VDD VSS / RSC_IHPSG13_INVX2 +XI2<2> addr_n<2> ADDR_DEC<2> VDD VSS / RSC_IHPSG13_INVX2 +XI2<1> addr_n<1> ADDR_DEC<1> VDD VSS / RSC_IHPSG13_INVX2 +XI2<0> addr_n<0> ADDR_DEC<0> VDD VSS / RSC_IHPSG13_INVX2 +XI17<4> VDD VSS / RSC_IHPSG13_FILLCAP4 +XI17<3> VDD VSS / RSC_IHPSG13_FILLCAP4 +XI17<2> VDD VSS / RSC_IHPSG13_FILLCAP4 +XI17<1> VDD VSS / RSC_IHPSG13_FILLCAP4 +XI16<11> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI16<10> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI16<9> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI16<8> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI16<7> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI16<6> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI16<5> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI16<4> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI16<3> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI16<2> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI16<1> VDD VSS / RSC_IHPSG13_FILLCAP8 +.ENDS +.SUBCKT RSC_IHPSG13_DFPQD_MSAFFX2P CP DN DP QN QP VDD VSS +XI_AMP CP DN DP QN QP VDD VSS / RSC_IHPSG13_DFPQD_MSAFFX2 +.ENDS +.SUBCKT RM_IHPSG13_256x32_c2_2P_COLCTRL3 A_ADDR_DEC<7> A_ADDR_DEC<6> A_ADDR_DEC<5> ++ A_ADDR_DEC<4> A_ADDR_DEC<3> A_ADDR_DEC<2> A_ADDR_DEC<1> A_ADDR_DEC<0> ++ A_BIST_BM_I A_BIST_DW_I A_BIST_EN_I A_BLC<7> A_BLC<6> A_BLC<5> A_BLC<4> ++ A_BLC<3> A_BLC<2> A_BLC<1> A_BLC<0> A_BLT<7> A_BLT<6> A_BLT<5> A_BLT<4> ++ A_BLT<3> A_BLT<2> A_BLT<1> A_BLT<0> A_BM_I A_DCLK_B_L A_DCLK_B_R A_DCLK_L ++ A_DCLK_R A_DR_O A_DW_I A_RCLK_B_L A_RCLK_B_R A_RCLK_L A_RCLK_R A_TIEH_O ++ A_WCLK_B_L A_WCLK_B_R A_WCLK_L A_WCLK_R B_ADDR_DEC<7> B_ADDR_DEC<6> ++ B_ADDR_DEC<5> B_ADDR_DEC<4> B_ADDR_DEC<3> B_ADDR_DEC<2> B_ADDR_DEC<1> ++ B_ADDR_DEC<0> B_BIST_BM_I B_BIST_DW_I B_BIST_EN_I B_BLC<7> B_BLC<6> B_BLC<5> ++ B_BLC<4> B_BLC<3> B_BLC<2> B_BLC<1> B_BLC<0> B_BLT<7> B_BLT<6> B_BLT<5> ++ B_BLT<4> B_BLT<3> B_BLT<2> B_BLT<1> B_BLT<0> B_BM_I B_DCLK_B_L B_DCLK_B_R ++ B_DCLK_L B_DCLK_R B_DR_O B_DW_I B_RCLK_B_L B_RCLK_B_R B_RCLK_L B_RCLK_R ++ B_TIEH_O B_WCLK_B_L B_WCLK_B_R B_WCLK_L B_WCLK_R VDD VSS +XB_DREG B_BIST_EN_I B_BIST_DW_I B_DCLK_B_L B_DW_I B_DI_R net044 VDD ++ VSS / RSC_IHPSG13_DFNQMX2IX1 +XB_BREG B_BIST_EN_I B_BIST_BM_I B_DCLK_B_L B_BM_I B_BM_R net043 VDD ++ VSS / RSC_IHPSG13_DFNQMX2IX1 +XA_DREG A_BIST_EN_I A_BIST_DW_I A_DCLK_B_L A_DW_I A_DI_R net22 VDD VSS ++ / RSC_IHPSG13_DFNQMX2IX1 +XA_BREG A_BIST_EN_I A_BIST_BM_I A_DCLK_B_L A_BM_I A_BM_R net23 VDD VSS ++ / RSC_IHPSG13_DFNQMX2IX1 +XI_FILL8<11> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI_FILL8<10> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI_FILL8<9> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI_FILL8<8> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI_FILL8<7> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI_FILL8<6> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI_FILL8<5> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI_FILL8<4> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI_FILL8<3> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI_FILL8<2> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI_FILL8<1> VDD VSS / RSC_IHPSG13_FILLCAP8 +XB_I51 net037 B_DR_O VDD VSS / RSC_IHPSG13_INVX4 +XA_I51 net19 A_DR_O VDD VSS / RSC_IHPSG13_INVX4 +XB_I44 B_BM_N B_WCLK_B_L B_DO_WRITE_P VDD VSS / RSC_IHPSG13_NOR2X2 +XA_I44 A_BM_N A_WCLK_B_L A_DO_WRITE_P VDD VSS / RSC_IHPSG13_NOR2X2 +XB_BM_TIEH B_TIEH_O VDD VSS / RSC_IHPSG13_TIEH +XA_BM_TIEH A_TIEH_O VDD VSS / RSC_IHPSG13_TIEH +XB_ISENSE B_SAE B_BLC_SEL B_BLT_SEL net037 net038 VDD VSS / ++ RSC_IHPSG13_DFPQD_MSAFFX2P +XA_ISENSE A_SAE A_BLC_SEL A_BLT_SEL net19 net20 VDD VSS / ++ RSC_IHPSG13_DFPQD_MSAFFX2P +XB_I49 B_DI_R B_DI_N VDD VSS / RSC_IHPSG13_INVX2 +XB_I83 B_BM_R B_BM_N VDD VSS / RSC_IHPSG13_INVX2 +XA_I49 A_DI_R A_DI_N VDD VSS / RSC_IHPSG13_INVX2 +XA_I83 A_BM_R A_BM_N VDD VSS / RSC_IHPSG13_INVX2 +XB_I69 B_DCLK_L B_DCLK_B_L VDD VSS / RSC_IHPSG13_CINVX2 +XB_I50 B_WCLK_L B_WCLK_B_L VDD VSS / RSC_IHPSG13_CINVX2 +XB_EBUF B_RCLK_L B_RCLK_B_L VDD VSS / RSC_IHPSG13_CINVX2 +XA_I69 A_DCLK_L A_DCLK_B_L VDD VSS / RSC_IHPSG13_CINVX2 +XA_I50 A_WCLK_L A_WCLK_B_L VDD VSS / RSC_IHPSG13_CINVX2 +XA_EBUF A_RCLK_L A_RCLK_B_L VDD VSS / RSC_IHPSG13_CINVX2 +XAB_BLMUX<1> A_BLC<7> A_BLC<6> A_BLC<5> A_BLC<4> A_BLC_SEL A_BLT<7> A_BLT<6> ++ A_BLT<5> A_BLT<4> A_BLT_SEL A_PRE_N A_ADDR_DEC<7> A_ADDR_DEC<6> ++ A_ADDR_DEC<5> A_ADDR_DEC<4> A_WR_ONE A_WR_ZERO B_BLC<7> B_BLC<6> B_BLC<5> ++ B_BLC<4> B_BLC_SEL B_BLT<7> B_BLT<6> B_BLT<5> B_BLT<4> B_BLT_SEL B_PRE_N ++ B_ADDR_DEC<7> B_ADDR_DEC<6> B_ADDR_DEC<5> B_ADDR_DEC<4> B_WR_ONE B_WR_ZERO ++ VDD VSS / RM_IHPSG13_256x32_c2_2P_BLDRV +XAB_BLMUX<0> A_BLC<3> A_BLC<2> A_BLC<1> A_BLC<0> A_BLC_SEL A_BLT<3> A_BLT<2> ++ A_BLT<1> A_BLT<0> A_BLT_SEL A_PRE_N A_ADDR_DEC<3> A_ADDR_DEC<2> ++ A_ADDR_DEC<1> A_ADDR_DEC<0> A_WR_ONE A_WR_ZERO B_BLC<3> B_BLC<2> B_BLC<1> ++ B_BLC<0> B_BLC_SEL B_BLT<3> B_BLT<2> B_BLT<1> B_BLT<0> B_BLT_SEL B_PRE_N ++ B_ADDR_DEC<3> B_ADDR_DEC<2> B_ADDR_DEC<1> B_ADDR_DEC<0> B_WR_ONE B_WR_ZERO ++ VDD VSS / RM_IHPSG13_256x32_c2_2P_BLDRV +XB_I78 B_RCLK_B_L B_SAE VDD VSS / RSC_IHPSG13_CBUFX2 +XA_I78 A_RCLK_B_L A_SAE VDD VSS / RSC_IHPSG13_CBUFX2 +XB_I88 B_DCLK_L B_DCLK_R / RSC_IHPSG13_MET3RES +XB_I87 B_WCLK_L B_WCLK_R / RSC_IHPSG13_MET3RES +XB_R2 B_RCLK_L B_RCLK_R / RSC_IHPSG13_MET3RES +XB_I91 B_RCLK_B_L B_RCLK_B_R / RSC_IHPSG13_MET3RES +XB_I90 B_WCLK_B_L B_WCLK_B_R / RSC_IHPSG13_MET3RES +XB_I89 B_DCLK_B_L B_DCLK_B_R / RSC_IHPSG13_MET3RES +XA_I88 A_DCLK_L A_DCLK_R / RSC_IHPSG13_MET3RES +XA_I87 A_WCLK_L A_WCLK_R / RSC_IHPSG13_MET3RES +XA_R2 A_RCLK_L A_RCLK_R / RSC_IHPSG13_MET3RES +XA_I91 A_RCLK_B_L A_RCLK_B_R / RSC_IHPSG13_MET3RES +XA_I90 A_WCLK_B_L A_WCLK_B_R / RSC_IHPSG13_MET3RES +XA_I89 A_DCLK_B_L A_DCLK_B_R / RSC_IHPSG13_MET3RES +XB_I80 B_WCLK_B_L B_RCLK_B_L net041 VDD VSS / RSC_IHPSG13_AND2X2 +XB_I76 B_DO_WRITE_P B_DI_N B_WR_ZERO VDD VSS / RSC_IHPSG13_AND2X2 +XB_I75 B_DO_WRITE_P B_DI_R B_WR_ONE VDD VSS / RSC_IHPSG13_AND2X2 +XA_I80 A_WCLK_B_L A_RCLK_B_L net21 VDD VSS / RSC_IHPSG13_AND2X2 +XA_I76 A_DI_N A_DO_WRITE_P A_WR_ZERO VDD VSS / RSC_IHPSG13_AND2X2 +XA_I75 A_DI_R A_DO_WRITE_P A_WR_ONE VDD VSS / RSC_IHPSG13_AND2X2 +XB_I81 net041 B_PRE_N VDD VSS / RSC_IHPSG13_CINVX4_WN +XA_I81 net21 A_PRE_N VDD VSS / RSC_IHPSG13_CINVX4_WN +XI_FILL4<10> VDD VSS / RSC_IHPSG13_FILLCAP4 +XI_FILL4<9> VDD VSS / RSC_IHPSG13_FILLCAP4 +XI_FILL4<8> VDD VSS / RSC_IHPSG13_FILLCAP4 +XI_FILL4<7> VDD VSS / RSC_IHPSG13_FILLCAP4 +XI_FILL4<6> VDD VSS / RSC_IHPSG13_FILLCAP4 +XI_FILL4<5> VDD VSS / RSC_IHPSG13_FILLCAP4 +XI_FILL4<4> VDD VSS / RSC_IHPSG13_FILLCAP4 +XI_FILL4<3> VDD VSS / RSC_IHPSG13_FILLCAP4 +XI_FILL4<2> VDD VSS / RSC_IHPSG13_FILLCAP4 +XI_FILL4<1> VDD VSS / RSC_IHPSG13_FILLCAP4 +.ENDS + +.SUBCKT RM_IHPSG13_256x32_c2_2P_ROWDEC6 ADDR_N_I<5> ADDR_N_I<4> ADDR_N_I<3> ADDR_N_I<2> ++ ADDR_N_I<1> ADDR_N_I<0> CS_I ECLK_I WL_O<63> WL_O<62> WL_O<61> WL_O<60> ++ WL_O<59> WL_O<58> WL_O<57> WL_O<56> WL_O<55> WL_O<54> WL_O<53> WL_O<52> ++ WL_O<51> WL_O<50> WL_O<49> WL_O<48> WL_O<47> WL_O<46> WL_O<45> WL_O<44> ++ WL_O<43> WL_O<42> WL_O<41> WL_O<40> WL_O<39> WL_O<38> WL_O<37> WL_O<36> ++ WL_O<35> WL_O<34> WL_O<33> WL_O<32> WL_O<31> WL_O<30> WL_O<29> WL_O<28> ++ WL_O<27> WL_O<26> WL_O<25> WL_O<24> WL_O<23> WL_O<22> WL_O<21> WL_O<20> ++ WL_O<19> WL_O<18> WL_O<17> WL_O<16> WL_O<15> WL_O<14> WL_O<13> WL_O<12> ++ WL_O<11> WL_O<10> WL_O<9> WL_O<8> WL_O<7> WL_O<6> WL_O<5> WL_O<4> WL_O<3> ++ WL_O<2> WL_O<1> WL_O<0> VDD VSS +XDEC10 ADDR_N_I<5> ADDR_N_I<4> CS_I CS00<2> VDD VSS / ++ RM_IHPSG13_256x32_c2_2P_DEC02 +XDEC00 ADDR_N_I<5> ADDR_N_I<4> CS_I CS00<0> VDD VSS / ++ RM_IHPSG13_256x32_c2_2P_DEC00 +XSEL<3> ADDR_N_I<3> ADDR_N_I<2> ADDR_N_I<1> ADDR_N_I<0> CS00<3> ECLK_H<3> ++ ECLK_H<4> ECLK_B<3> ECLK_B<4> WL_O<63> WL_O<62> WL_O<61> WL_O<60> WL_O<59> ++ WL_O<58> WL_O<57> WL_O<56> WL_O<55> WL_O<54> WL_O<53> WL_O<52> WL_O<51> ++ WL_O<50> WL_O<49> WL_O<48> VDD VSS / RM_IHPSG13_256x32_c2_2P_DEC04 +XSEL<2> ADDR_N_I<3> ADDR_N_I<2> ADDR_N_I<1> ADDR_N_I<0> CS00<2> ECLK_H<2> ++ ECLK_H<3> ECLK_B<2> ECLK_B<3> WL_O<47> WL_O<46> WL_O<45> WL_O<44> WL_O<43> ++ WL_O<42> WL_O<41> WL_O<40> WL_O<39> WL_O<38> WL_O<37> WL_O<36> WL_O<35> ++ WL_O<34> WL_O<33> WL_O<32> VDD VSS / RM_IHPSG13_256x32_c2_2P_DEC04 +XSEL<1> ADDR_N_I<3> ADDR_N_I<2> ADDR_N_I<1> ADDR_N_I<0> CS00<1> ECLK_H<1> ++ ECLK_H<2> ECLK_B<1> ECLK_B<2> WL_O<31> WL_O<30> WL_O<29> WL_O<28> WL_O<27> ++ WL_O<26> WL_O<25> WL_O<24> WL_O<23> WL_O<22> WL_O<21> WL_O<20> WL_O<19> ++ WL_O<18> WL_O<17> WL_O<16> VDD VSS / RM_IHPSG13_256x32_c2_2P_DEC04 +XSEL<0> ADDR_N_I<3> ADDR_N_I<2> ADDR_N_I<1> ADDR_N_I<0> CS00<0> ECLK_I ++ ECLK_H<1> ECLK_B<0> ECLK_B<1> WL_O<15> WL_O<14> WL_O<13> WL_O<12> WL_O<11> ++ WL_O<10> WL_O<9> WL_O<8> WL_O<7> WL_O<6> WL_O<5> WL_O<4> WL_O<3> WL_O<2> ++ WL_O<1> WL_O<0> VDD VSS / RM_IHPSG13_256x32_c2_2P_DEC04 +XDEC11 ADDR_N_I<5> ADDR_N_I<4> CS_I CS00<3> VDD VSS / ++ RM_IHPSG13_256x32_c2_2P_DEC03 +XL2<36> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<35> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<34> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<33> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<32> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<31> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<30> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<29> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<28> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<27> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<26> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<25> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<24> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<23> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<22> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<21> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<20> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<19> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<18> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<17> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<16> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<15> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<14> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<13> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<12> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<11> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<10> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<9> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<8> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<7> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<6> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<5> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<4> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<3> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<2> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<1> VDD VSS / RSC_IHPSG13_FILLCAP8 +XDEC01 ADDR_N_I<5> ADDR_N_I<4> CS_I CS00<1> VDD VSS / ++ RM_IHPSG13_256x32_c2_2P_DEC01 +.ENDS +.SUBCKT RM_IHPSG13_256x32_c2_2P_ROWREG6 ACLK_N_I ADDR_I<5> ADDR_I<4> ADDR_I<3> ADDR_I<2> ++ ADDR_I<1> ADDR_I<0> ADDR_N_O<5> ADDR_N_O<4> ADDR_N_O<3> ADDR_N_O<2> ++ ADDR_N_O<1> ADDR_N_O<0> BIST_ADDR_I<5> BIST_ADDR_I<4> BIST_ADDR_I<3> ++ BIST_ADDR_I<2> BIST_ADDR_I<1> BIST_ADDR_I<0> BIST_EN_I VDD VSS +XINV<5> q_int<5> qn_int<5> VDD VSS / RSC_IHPSG13_CINVX2 +XINV<4> q_int<4> qn_int<4> VDD VSS / RSC_IHPSG13_CINVX2 +XINV<3> q_int<3> qn_int<3> VDD VSS / RSC_IHPSG13_CINVX2 +XINV<2> q_int<2> qn_int<2> VDD VSS / RSC_IHPSG13_CINVX2 +XINV<1> q_int<1> qn_int<1> VDD VSS / RSC_IHPSG13_CINVX2 +XINV<0> q_int<0> qn_int<0> VDD VSS / RSC_IHPSG13_CINVX2 +XDRV<5> qn_int<5> ADDR_N_O<5> VDD VSS / RSC_IHPSG13_CINVX8 +XDRV<4> qn_int<4> ADDR_N_O<4> VDD VSS / RSC_IHPSG13_CINVX8 +XDRV<3> qn_int<3> ADDR_N_O<3> VDD VSS / RSC_IHPSG13_CINVX8 +XDRV<2> qn_int<2> ADDR_N_O<2> VDD VSS / RSC_IHPSG13_CINVX8 +XDRV<1> qn_int<1> ADDR_N_O<1> VDD VSS / RSC_IHPSG13_CINVX8 +XDRV<0> qn_int<0> ADDR_N_O<0> VDD VSS / RSC_IHPSG13_CINVX8 +XDFF<5> BIST_EN_I BIST_ADDR_I<5> ACLK_N_I ADDR_I<5> q_int<5> net2<0> VDD ++ VSS / RSC_IHPSG13_DFNQMX2IX1 +XDFF<4> BIST_EN_I BIST_ADDR_I<4> ACLK_N_I ADDR_I<4> q_int<4> net2<1> VDD ++ VSS / RSC_IHPSG13_DFNQMX2IX1 +XDFF<3> BIST_EN_I BIST_ADDR_I<3> ACLK_N_I ADDR_I<3> q_int<3> net2<2> VDD ++ VSS / RSC_IHPSG13_DFNQMX2IX1 +XDFF<2> BIST_EN_I BIST_ADDR_I<2> ACLK_N_I ADDR_I<2> q_int<2> net2<3> VDD ++ VSS / RSC_IHPSG13_DFNQMX2IX1 +XDFF<1> BIST_EN_I BIST_ADDR_I<1> ACLK_N_I ADDR_I<1> q_int<1> net2<4> VDD ++ VSS / RSC_IHPSG13_DFNQMX2IX1 +XDFF<0> BIST_EN_I BIST_ADDR_I<0> ACLK_N_I ADDR_I<0> q_int<0> net2<5> VDD ++ VSS / RSC_IHPSG13_DFNQMX2IX1 +XI11<12> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI11<11> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI11<10> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI11<9> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI11<8> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI11<7> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI11<6> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI11<5> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI11<4> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI11<3> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI11<2> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI11<1> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI12<2> VDD VSS / RSC_IHPSG13_FILLCAP4 +XI12<1> VDD VSS / RSC_IHPSG13_FILLCAP4 +XI12<0> VDD VSS / RSC_IHPSG13_FILLCAP4 +.ENDS + +.SUBCKT RM_IHPSG13_256x32_c2_2P_COLDRV13X16 ADDR_COL_I<1> ADDR_COL_I<0> ADDR_COL_O<1> ++ ADDR_COL_O<0> ADDR_DEC_I<7> ADDR_DEC_I<6> ADDR_DEC_I<5> ADDR_DEC_I<4> ++ ADDR_DEC_I<3> ADDR_DEC_I<2> ADDR_DEC_I<1> ADDR_DEC_I<0> ADDR_DEC_O<7> ++ ADDR_DEC_O<6> ADDR_DEC_O<5> ADDR_DEC_O<4> ADDR_DEC_O<3> ADDR_DEC_O<2> ++ ADDR_DEC_O<1> ADDR_DEC_O<0> DCLK_I DCLK_O RCLK_I RCLK_O WCLK_I WCLK_O ++ VDD VSS +XI0<7> VDD VSS / RSC_IHPSG13_FILLCAP4 +XI0<6> VDD VSS / RSC_IHPSG13_FILLCAP4 +XI0<5> VDD VSS / RSC_IHPSG13_FILLCAP4 +XI0<4> VDD VSS / RSC_IHPSG13_FILLCAP4 +XI0<3> VDD VSS / RSC_IHPSG13_FILLCAP4 +XI0<2> VDD VSS / RSC_IHPSG13_FILLCAP4 +XI0<1> VDD VSS / RSC_IHPSG13_FILLCAP4 +XWCLK_DRV WCLK_I WCLK_O VDD VSS / RSC_IHPSG13_CBUFX16 +XRCLK_DRV RCLK_I RCLK_O VDD VSS / RSC_IHPSG13_CBUFX16 +XDCLK_DRV DCLK_I DCLK_O VDD VSS / RSC_IHPSG13_CBUFX16 +XADDR_COL_DRV<1> ADDR_COL_I<1> ADDR_COL_O<1> VDD VSS / ++ RSC_IHPSG13_CBUFX16 +XADDR_COL_DRV<0> ADDR_COL_I<0> ADDR_COL_O<0> VDD VSS / ++ RSC_IHPSG13_CBUFX16 +XADDR_DEC_DRV<7> ADDR_DEC_I<7> ADDR_DEC_O<7> VDD VSS / ++ RSC_IHPSG13_CBUFX16 +XADDR_DEC_DRV<6> ADDR_DEC_I<6> ADDR_DEC_O<6> VDD VSS / ++ RSC_IHPSG13_CBUFX16 +XADDR_DEC_DRV<5> ADDR_DEC_I<5> ADDR_DEC_O<5> VDD VSS / ++ RSC_IHPSG13_CBUFX16 +XADDR_DEC_DRV<4> ADDR_DEC_I<4> ADDR_DEC_O<4> VDD VSS / ++ RSC_IHPSG13_CBUFX16 +XADDR_DEC_DRV<3> ADDR_DEC_I<3> ADDR_DEC_O<3> VDD VSS / ++ RSC_IHPSG13_CBUFX16 +XADDR_DEC_DRV<2> ADDR_DEC_I<2> ADDR_DEC_O<2> VDD VSS / ++ RSC_IHPSG13_CBUFX16 +XADDR_DEC_DRV<1> ADDR_DEC_I<1> ADDR_DEC_O<1> VDD VSS / ++ RSC_IHPSG13_CBUFX16 +XADDR_DEC_DRV<0> ADDR_DEC_I<0> ADDR_DEC_O<0> VDD VSS / ++ RSC_IHPSG13_CBUFX16 +XI1<5> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI1<4> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI1<3> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI1<2> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI1<1> VDD VSS / RSC_IHPSG13_FILLCAP8 +.ENDS +.SUBCKT RM_IHPSG13_256x32_c2_2P_WLDRV16X16 A<15> A<14> A<13> A<12> A<11> A<10> A<9> A<8> ++ A<7> A<6> A<5> A<4> A<3> A<2> A<1> A<0> Z<15> Z<14> Z<13> Z<12> Z<11> Z<10> ++ Z<9> Z<8> Z<7> Z<6> Z<5> Z<4> Z<3> Z<2> Z<1> Z<0> VDD VSS +XBUF<15> A<15> Z<15> VDD VSS / RSC_IHPSG13_WLDRVX16 +XBUF<14> A<14> Z<14> VDD VSS / RSC_IHPSG13_WLDRVX16 +XBUF<13> A<13> Z<13> VDD VSS / RSC_IHPSG13_WLDRVX16 +XBUF<12> A<12> Z<12> VDD VSS / RSC_IHPSG13_WLDRVX16 +XBUF<11> A<11> Z<11> VDD VSS / RSC_IHPSG13_WLDRVX16 +XBUF<10> A<10> Z<10> VDD VSS / RSC_IHPSG13_WLDRVX16 +XBUF<9> A<9> Z<9> VDD VSS / RSC_IHPSG13_WLDRVX16 +XBUF<8> A<8> Z<8> VDD VSS / RSC_IHPSG13_WLDRVX16 +XBUF<7> A<7> Z<7> VDD VSS / RSC_IHPSG13_WLDRVX16 +XBUF<6> A<6> Z<6> VDD VSS / RSC_IHPSG13_WLDRVX16 +XBUF<5> A<5> Z<5> VDD VSS / RSC_IHPSG13_WLDRVX16 +XBUF<4> A<4> Z<4> VDD VSS / RSC_IHPSG13_WLDRVX16 +XBUF<3> A<3> Z<3> VDD VSS / RSC_IHPSG13_WLDRVX16 +XBUF<2> A<2> Z<2> VDD VSS / RSC_IHPSG13_WLDRVX16 +XBUF<1> A<1> Z<1> VDD VSS / RSC_IHPSG13_WLDRVX16 +XBUF<0> A<0> Z<0> VDD VSS / RSC_IHPSG13_WLDRVX16 +.ENDS + + +.SUBCKT RM_IHPSG13_256x32_c2_1P_DEC01 ADDR<1> ADDR<0> CS CS_OUT VDD VSS +XDECINV net1 CS_OUT VDD VSS / RSC_IHPSG13_INVX4 +XDEC NADDR<1> ADDR<0> CS net1 VDD VSS / RSC_IHPSG13_NAND3X2 +XI2 VDD VSS / RSC_IHPSG13_FILLCAP4 +XADDRINV ADDR<1> NADDR<1> VDD VSS / RSC_IHPSG13_INVX2 +.ENDS +.SUBCKT RM_IHPSG13_256x32_c2_1P_DEC00 ADDR<1> ADDR<0> CS CS_OUT VDD VSS +XDECINV net1 CS_OUT VDD VSS / RSC_IHPSG13_INVX4 +XDEC NADDR<1> NADDR<0> CS net1 VDD VSS / RSC_IHPSG13_NAND3X2 +XADDRINV<1> ADDR<1> NADDR<1> VDD VSS / RSC_IHPSG13_INVX2 +XADDRINV<0> ADDR<0> NADDR<0> VDD VSS / RSC_IHPSG13_INVX2 +XI1 VDD VSS / RSC_IHPSG13_FILLCAP4 +.ENDS +.SUBCKT RM_IHPSG13_256x32_c2_1P_ROWDEC5 ADDR_N_I<4> ADDR_N_I<3> ADDR_N_I<2> ADDR_N_I<1> ++ ADDR_N_I<0> CS_I ECLK_I WL_O<31> WL_O<30> WL_O<29> WL_O<28> WL_O<27> ++ WL_O<26> WL_O<25> WL_O<24> WL_O<23> WL_O<22> WL_O<21> WL_O<20> WL_O<19> ++ WL_O<18> WL_O<17> WL_O<16> WL_O<15> WL_O<14> WL_O<13> WL_O<12> WL_O<11> ++ WL_O<10> WL_O<9> WL_O<8> WL_O<7> WL_O<6> WL_O<5> WL_O<4> WL_O<3> WL_O<2> ++ WL_O<1> WL_O<0> VDD VSS +XL2<12> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<11> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<10> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<9> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<8> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<7> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<6> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<5> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<4> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<3> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<2> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<1> VDD VSS / RSC_IHPSG13_FILLCAP8 +XDEC01 ADDR_N_I<5> ADDR_N_I<4> CS_I CS00<1> VDD VSS / ++ RM_IHPSG13_256x32_c2_1P_DEC01 +XDEC00 ADDR_N_I<5> ADDR_N_I<4> CS_I CS00<0> VDD VSS / ++ RM_IHPSG13_256x32_c2_1P_DEC00 +XSEL<1> ADDR_N_I<3> ADDR_N_I<2> ADDR_N_I<1> ADDR_N_I<0> CS00<1> ECLK_H<1> ++ ECLK_H<2> ECLK_B<1> ECLK_B<2> WL_O<31> WL_O<30> WL_O<29> WL_O<28> WL_O<27> ++ WL_O<26> WL_O<25> WL_O<24> WL_O<23> WL_O<22> WL_O<21> WL_O<20> WL_O<19> ++ WL_O<18> WL_O<17> WL_O<16> VDD VSS / RM_IHPSG13_256x32_c2_1P_DEC04 +XSEL<0> ADDR_N_I<3> ADDR_N_I<2> ADDR_N_I<1> ADDR_N_I<0> CS00<0> ECLK_I ++ ECLK_H<1> ECLK_B<0> ECLK_B<1> WL_O<15> WL_O<14> WL_O<13> WL_O<12> WL_O<11> ++ WL_O<10> WL_O<9> WL_O<8> WL_O<7> WL_O<6> WL_O<5> WL_O<4> WL_O<3> WL_O<2> ++ WL_O<1> WL_O<0> VDD VSS / RM_IHPSG13_256x32_c2_1P_DEC04 +XI0 ADDR_N_I<5> VDD VSS / RSC_IHPSG13_TIEL +.ENDS +.SUBCKT RM_IHPSG13_256x32_c2_1P_ROWREG5 ACLK_N_I ADDR_I<4> ADDR_I<3> ADDR_I<2> ADDR_I<1> ++ ADDR_I<0> ADDR_N_O<4> ADDR_N_O<3> ADDR_N_O<2> ADDR_N_O<1> ADDR_N_O<0> ++ BIST_ADDR_I<4> BIST_ADDR_I<3> BIST_ADDR_I<2> BIST_ADDR_I<1> BIST_ADDR_I<0> ++ BIST_EN_I VDD VSS +XINV<4> q_int<4> qn_int<4> VDD VSS / RSC_IHPSG13_CINVX2 +XINV<3> q_int<3> qn_int<3> VDD VSS / RSC_IHPSG13_CINVX2 +XINV<2> q_int<2> qn_int<2> VDD VSS / RSC_IHPSG13_CINVX2 +XINV<1> q_int<1> qn_int<1> VDD VSS / RSC_IHPSG13_CINVX2 +XINV<0> q_int<0> qn_int<0> VDD VSS / RSC_IHPSG13_CINVX2 +XDRV<4> qn_int<4> ADDR_N_O<4> VDD VSS / RSC_IHPSG13_CINVX8 +XDRV<3> qn_int<3> ADDR_N_O<3> VDD VSS / RSC_IHPSG13_CINVX8 +XDRV<2> qn_int<2> ADDR_N_O<2> VDD VSS / RSC_IHPSG13_CINVX8 +XDRV<1> qn_int<1> ADDR_N_O<1> VDD VSS / RSC_IHPSG13_CINVX8 +XDRV<0> qn_int<0> ADDR_N_O<0> VDD VSS / RSC_IHPSG13_CINVX8 +XDFF<4> BIST_EN_I BIST_ADDR_I<4> ACLK_N_I ADDR_I<4> q_int<4> net2<0> VDD ++ VSS / RSC_IHPSG13_DFNQMX2IX1 +XDFF<3> BIST_EN_I BIST_ADDR_I<3> ACLK_N_I ADDR_I<3> q_int<3> net2<1> VDD ++ VSS / RSC_IHPSG13_DFNQMX2IX1 +XDFF<2> BIST_EN_I BIST_ADDR_I<2> ACLK_N_I ADDR_I<2> q_int<2> net2<2> VDD ++ VSS / RSC_IHPSG13_DFNQMX2IX1 +XDFF<1> BIST_EN_I BIST_ADDR_I<1> ACLK_N_I ADDR_I<1> q_int<1> net2<3> VDD ++ VSS / RSC_IHPSG13_DFNQMX2IX1 +XDFF<0> BIST_EN_I BIST_ADDR_I<0> ACLK_N_I ADDR_I<0> q_int<0> net2<4> VDD ++ VSS / RSC_IHPSG13_DFNQMX2IX1 +XI11<16> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI11<15> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI11<14> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI11<13> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI11<12> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI11<11> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI11<10> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI11<9> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI11<8> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI11<7> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI11<6> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI11<5> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI11<4> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI11<3> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI11<2> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI11<1> VDD VSS / RSC_IHPSG13_FILLCAP8 +.ENDS + + +.SUBCKT RM_IHPSG13_256x32_c2_1P_COLDEC5 ACLK_N ADDR<4> ADDR<3> ADDR<2> ADDR<1> ADDR<0> ++ ADDR_COL<1> ADDR_COL<0> ADDR_DEC<7> ADDR_DEC<6> ADDR_DEC<5> ADDR_DEC<4> ++ ADDR_DEC<3> ADDR_DEC<2> ADDR_DEC<1> ADDR_DEC<0> BIST_ADDR<4> BIST_ADDR<3> ++ BIST_ADDR<2> BIST_ADDR<1> BIST_ADDR<0> BIST_EN_I VDD VSS +XI17<2> VDD VSS / RSC_IHPSG13_FILLCAP4 +XI17<1> VDD VSS / RSC_IHPSG13_FILLCAP4 +XI13<1> addr_int<1> ADDR_COL<1> VDD VSS / RSC_IHPSG13_CBUFX2 +XI13<0> addr_int<0> ADDR_COL<0> VDD VSS / RSC_IHPSG13_CBUFX2 +XDFF<4> BIST_EN_I BIST_ADDR<4> ACLK_N ADDR<4> addr_int<1> net7<0> VDD ++ VSS / RSC_IHPSG13_DFNQMX2IX1 +XDFF<3> BIST_EN_I BIST_ADDR<3> ACLK_N ADDR<3> addr_int<0> net7<1> VDD ++ VSS / RSC_IHPSG13_DFNQMX2IX1 +XDFF<2> BIST_EN_I BIST_ADDR<2> ACLK_N ADDR<2> padr_int<2> net7<2> VDD ++ VSS / RSC_IHPSG13_DFNQMX2IX1 +XDFF<1> BIST_EN_I BIST_ADDR<1> ACLK_N ADDR<1> padr_int<1> net7<3> VDD ++ VSS / RSC_IHPSG13_DFNQMX2IX1 +XDFF<0> BIST_EN_I BIST_ADDR<0> ACLK_N ADDR<0> padr_int<0> net7<4> VDD ++ VSS / RSC_IHPSG13_DFNQMX2IX1 +XI1<7> PADR<0> PADR<1> PADR<2> addr_n<7> VDD VSS / RSC_IHPSG13_NAND3X2 +XI1<6> NADR<0> PADR<1> PADR<2> addr_n<6> VDD VSS / RSC_IHPSG13_NAND3X2 +XI1<5> PADR<0> NADR<1> PADR<2> addr_n<5> VDD VSS / RSC_IHPSG13_NAND3X2 +XI1<4> NADR<0> NADR<1> PADR<2> addr_n<4> VDD VSS / RSC_IHPSG13_NAND3X2 +XI1<3> PADR<0> PADR<1> NADR<2> addr_n<3> VDD VSS / RSC_IHPSG13_NAND3X2 +XI1<2> NADR<0> PADR<1> NADR<2> addr_n<2> VDD VSS / RSC_IHPSG13_NAND3X2 +XI1<1> PADR<0> NADR<1> NADR<2> addr_n<1> VDD VSS / RSC_IHPSG13_NAND3X2 +XI1<0> NADR<0> NADR<1> NADR<2> addr_n<0> VDD VSS / RSC_IHPSG13_NAND3X2 +XI15<2> NADR<2> PADR<2> VDD VSS / RSC_IHPSG13_INVX2 +XI15<1> NADR<1> PADR<1> VDD VSS / RSC_IHPSG13_INVX2 +XI15<0> NADR<0> PADR<0> VDD VSS / RSC_IHPSG13_INVX2 +XI3<2> padr_int<2> NADR<2> VDD VSS / RSC_IHPSG13_INVX2 +XI3<1> padr_int<1> NADR<1> VDD VSS / RSC_IHPSG13_INVX2 +XI3<0> padr_int<0> NADR<0> VDD VSS / RSC_IHPSG13_INVX2 +XI2<7> addr_n<7> ADDR_DEC<7> VDD VSS / RSC_IHPSG13_INVX2 +XI2<6> addr_n<6> ADDR_DEC<6> VDD VSS / RSC_IHPSG13_INVX2 +XI2<5> addr_n<5> ADDR_DEC<5> VDD VSS / RSC_IHPSG13_INVX2 +XI2<4> addr_n<4> ADDR_DEC<4> VDD VSS / RSC_IHPSG13_INVX2 +XI2<3> addr_n<3> ADDR_DEC<3> VDD VSS / RSC_IHPSG13_INVX2 +XI2<2> addr_n<2> ADDR_DEC<2> VDD VSS / RSC_IHPSG13_INVX2 +XI2<1> addr_n<1> ADDR_DEC<1> VDD VSS / RSC_IHPSG13_INVX2 +XI2<0> addr_n<0> ADDR_DEC<0> VDD VSS / RSC_IHPSG13_INVX2 +.ENDS +.SUBCKT RM_IHPSG13_256x32_c2_1P_COLCTRL5 A_ADDR_COL<1> A_ADDR_COL<0> A_ADDR_DEC<7> ++ A_ADDR_DEC<6> A_ADDR_DEC<5> A_ADDR_DEC<4> A_ADDR_DEC<3> A_ADDR_DEC<2> ++ A_ADDR_DEC<1> A_ADDR_DEC<0> A_BIST_BM_I A_BIST_DW_I A_BIST_EN_I A_BLC<31> ++ A_BLC<30> A_BLC<29> A_BLC<28> A_BLC<27> A_BLC<26> A_BLC<25> A_BLC<24> ++ A_BLC<23> A_BLC<22> A_BLC<21> A_BLC<20> A_BLC<19> A_BLC<18> A_BLC<17> ++ A_BLC<16> A_BLC<15> A_BLC<14> A_BLC<13> A_BLC<12> A_BLC<11> A_BLC<10> ++ A_BLC<9> A_BLC<8> A_BLC<7> A_BLC<6> A_BLC<5> A_BLC<4> A_BLC<3> A_BLC<2> ++ A_BLC<1> A_BLC<0> A_BLT<31> A_BLT<30> A_BLT<29> A_BLT<28> A_BLT<27> ++ A_BLT<26> A_BLT<25> A_BLT<24> A_BLT<23> A_BLT<22> A_BLT<21> A_BLT<20> ++ A_BLT<19> A_BLT<18> A_BLT<17> A_BLT<16> A_BLT<15> A_BLT<14> A_BLT<13> ++ A_BLT<12> A_BLT<11> A_BLT<10> A_BLT<9> A_BLT<8> A_BLT<7> A_BLT<6> A_BLT<5> ++ A_BLT<4> A_BLT<3> A_BLT<2> A_BLT<1> A_BLT<0> A_BM_I A_DCLK_B_L A_DCLK_B_R ++ A_DCLK_L A_DCLK_R A_DR_O A_DW_I A_RCLK_B_L A_RCLK_B_R A_RCLK_L A_RCLK_R ++ A_TIEH_O A_WCLK_B_L A_WCLK_B_R A_WCLK_L A_WCLK_R VDD VSS +XA_I80<1> A_WCLK_B_L A_RCLK_B_L A_W_nor_R<1> VDD VSS / ++ RSC_IHPSG13_AND2X2 +XA_I80<0> A_WCLK_B_L A_RCLK_B_L A_W_nor_R<0> VDD VSS / ++ RSC_IHPSG13_AND2X2 +XA_I44 A_BM_N A_WCLK_B_L A_DO_WRITE_P VDD VSS / RSC_IHPSG13_NOR2X2 +XI80<29> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI80<28> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI80<27> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI80<26> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI80<25> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI80<24> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI80<23> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI80<22> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI80<21> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI80<20> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI80<19> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI80<18> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI80<17> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI80<16> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI80<15> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI80<14> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI80<13> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI80<12> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI80<11> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI80<10> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI80<9> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI80<8> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI80<7> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI80<6> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI80<5> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI80<4> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI80<3> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI80<2> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI80<1> VDD VSS / RSC_IHPSG13_FILLCAP8 +XA_I74<16> VDD VSS / RSC_IHPSG13_FILLCAP8 +XA_I74<15> VDD VSS / RSC_IHPSG13_FILLCAP8 +XA_I74<14> VDD VSS / RSC_IHPSG13_FILLCAP8 +XA_I74<13> VDD VSS / RSC_IHPSG13_FILLCAP8 +XA_I74<12> VDD VSS / RSC_IHPSG13_FILLCAP8 +XA_I74<11> VDD VSS / RSC_IHPSG13_FILLCAP8 +XA_I74<10> VDD VSS / RSC_IHPSG13_FILLCAP8 +XA_I74<9> VDD VSS / RSC_IHPSG13_FILLCAP8 +XA_I74<8> VDD VSS / RSC_IHPSG13_FILLCAP8 +XA_I74<7> VDD VSS / RSC_IHPSG13_FILLCAP8 +XA_I74<6> VDD VSS / RSC_IHPSG13_FILLCAP8 +XA_I74<5> VDD VSS / RSC_IHPSG13_FILLCAP8 +XA_I74<4> VDD VSS / RSC_IHPSG13_FILLCAP8 +XA_I74<3> VDD VSS / RSC_IHPSG13_FILLCAP8 +XA_I74<2> VDD VSS / RSC_IHPSG13_FILLCAP8 +XA_I74<1> VDD VSS / RSC_IHPSG13_FILLCAP8 +XA_INV<6> A_N1<1> A_P1<1> VDD VSS / RSC_IHPSG13_CINVX4 +XA_INV<5> A_N0<1> A_P0<1> VDD VSS / RSC_IHPSG13_CINVX4 +XA_INV<4> A_N0<0> A_P0<0> VDD VSS / RSC_IHPSG13_CINVX4 +XA_INV<3> A_ADDR_COL<1> A_N1<1> VDD VSS / RSC_IHPSG13_CINVX4 +XA_INV<2> A_ADDR_COL<1> A_N1<0> VDD VSS / RSC_IHPSG13_CINVX4 +XA_INV<1> A_ADDR_COL<0> A_N0<1> VDD VSS / RSC_IHPSG13_CINVX4 +XA_INV<0> A_ADDR_COL<0> A_N0<0> VDD VSS / RSC_IHPSG13_CINVX4 +XA_I81<3> A_W_nor_R<1> A_PRE_N VDD VSS / RSC_IHPSG13_CINVX4_WN +XA_I81<2> A_W_nor_R<1> A_PRE_N VDD VSS / RSC_IHPSG13_CINVX4_WN +XA_I81<1> A_W_nor_R<0> A_PRE_N VDD VSS / RSC_IHPSG13_CINVX4_WN +XA_I81<0> A_W_nor_R<0> A_PRE_N VDD VSS / RSC_IHPSG13_CINVX4_WN +XA_BLTMUX<31> A_BLC<31> A_BLC_SEL A_BLT<31> A_BLT_SEL A_PRE_N A_SEL_P<31> ++ A_WR_ONE A_WR_ZERO VDD VSS / RM_IHPSG13_256x32_c2_1P_BLDRV +XA_BLTMUX<30> A_BLC<30> A_BLC_SEL A_BLT<30> A_BLT_SEL A_PRE_N A_SEL_P<30> ++ A_WR_ONE A_WR_ZERO VDD VSS / RM_IHPSG13_256x32_c2_1P_BLDRV +XA_BLTMUX<29> A_BLC<29> A_BLC_SEL A_BLT<29> A_BLT_SEL A_PRE_N A_SEL_P<29> ++ A_WR_ONE A_WR_ZERO VDD VSS / RM_IHPSG13_256x32_c2_1P_BLDRV +XA_BLTMUX<28> A_BLC<28> A_BLC_SEL A_BLT<28> A_BLT_SEL A_PRE_N A_SEL_P<28> ++ A_WR_ONE A_WR_ZERO VDD VSS / RM_IHPSG13_256x32_c2_1P_BLDRV +XA_BLTMUX<27> A_BLC<27> A_BLC_SEL A_BLT<27> A_BLT_SEL A_PRE_N A_SEL_P<27> ++ A_WR_ONE A_WR_ZERO VDD VSS / RM_IHPSG13_256x32_c2_1P_BLDRV +XA_BLTMUX<26> A_BLC<26> A_BLC_SEL A_BLT<26> A_BLT_SEL A_PRE_N A_SEL_P<26> ++ A_WR_ONE A_WR_ZERO VDD VSS / RM_IHPSG13_256x32_c2_1P_BLDRV +XA_BLTMUX<25> A_BLC<25> A_BLC_SEL A_BLT<25> A_BLT_SEL A_PRE_N A_SEL_P<25> ++ A_WR_ONE A_WR_ZERO VDD VSS / RM_IHPSG13_256x32_c2_1P_BLDRV +XA_BLTMUX<24> A_BLC<24> A_BLC_SEL A_BLT<24> A_BLT_SEL A_PRE_N A_SEL_P<24> ++ A_WR_ONE A_WR_ZERO VDD VSS / RM_IHPSG13_256x32_c2_1P_BLDRV +XA_BLTMUX<23> A_BLC<23> A_BLC_SEL A_BLT<23> A_BLT_SEL A_PRE_N A_SEL_P<23> ++ A_WR_ONE A_WR_ZERO VDD VSS / RM_IHPSG13_256x32_c2_1P_BLDRV +XA_BLTMUX<22> A_BLC<22> A_BLC_SEL A_BLT<22> A_BLT_SEL A_PRE_N A_SEL_P<22> ++ A_WR_ONE A_WR_ZERO VDD VSS / RM_IHPSG13_256x32_c2_1P_BLDRV +XA_BLTMUX<21> A_BLC<21> A_BLC_SEL A_BLT<21> A_BLT_SEL A_PRE_N A_SEL_P<21> ++ A_WR_ONE A_WR_ZERO VDD VSS / RM_IHPSG13_256x32_c2_1P_BLDRV +XA_BLTMUX<20> A_BLC<20> A_BLC_SEL A_BLT<20> A_BLT_SEL A_PRE_N A_SEL_P<20> ++ A_WR_ONE A_WR_ZERO VDD VSS / RM_IHPSG13_256x32_c2_1P_BLDRV +XA_BLTMUX<19> A_BLC<19> A_BLC_SEL A_BLT<19> A_BLT_SEL A_PRE_N A_SEL_P<19> ++ A_WR_ONE A_WR_ZERO VDD VSS / RM_IHPSG13_256x32_c2_1P_BLDRV +XA_BLTMUX<18> A_BLC<18> A_BLC_SEL A_BLT<18> A_BLT_SEL A_PRE_N A_SEL_P<18> ++ A_WR_ONE A_WR_ZERO VDD VSS / RM_IHPSG13_256x32_c2_1P_BLDRV +XA_BLTMUX<17> A_BLC<17> A_BLC_SEL A_BLT<17> A_BLT_SEL A_PRE_N A_SEL_P<17> ++ A_WR_ONE A_WR_ZERO VDD VSS / RM_IHPSG13_256x32_c2_1P_BLDRV +XA_BLTMUX<16> A_BLC<16> A_BLC_SEL A_BLT<16> A_BLT_SEL A_PRE_N A_SEL_P<16> ++ A_WR_ONE A_WR_ZERO VDD VSS / RM_IHPSG13_256x32_c2_1P_BLDRV +XA_BLTMUX<15> A_BLC<15> A_BLC_SEL A_BLT<15> A_BLT_SEL A_PRE_N A_SEL_P<15> ++ A_WR_ONE A_WR_ZERO VDD VSS / RM_IHPSG13_256x32_c2_1P_BLDRV +XA_BLTMUX<14> A_BLC<14> A_BLC_SEL A_BLT<14> A_BLT_SEL A_PRE_N A_SEL_P<14> ++ A_WR_ONE A_WR_ZERO VDD VSS / RM_IHPSG13_256x32_c2_1P_BLDRV +XA_BLTMUX<13> A_BLC<13> A_BLC_SEL A_BLT<13> A_BLT_SEL A_PRE_N A_SEL_P<13> ++ A_WR_ONE A_WR_ZERO VDD VSS / RM_IHPSG13_256x32_c2_1P_BLDRV +XA_BLTMUX<12> A_BLC<12> A_BLC_SEL A_BLT<12> A_BLT_SEL A_PRE_N A_SEL_P<12> ++ A_WR_ONE A_WR_ZERO VDD VSS / RM_IHPSG13_256x32_c2_1P_BLDRV +XA_BLTMUX<11> A_BLC<11> A_BLC_SEL A_BLT<11> A_BLT_SEL A_PRE_N A_SEL_P<11> ++ A_WR_ONE A_WR_ZERO VDD VSS / RM_IHPSG13_256x32_c2_1P_BLDRV +XA_BLTMUX<10> A_BLC<10> A_BLC_SEL A_BLT<10> A_BLT_SEL A_PRE_N A_SEL_P<10> ++ A_WR_ONE A_WR_ZERO VDD VSS / RM_IHPSG13_256x32_c2_1P_BLDRV +XA_BLTMUX<9> A_BLC<9> A_BLC_SEL A_BLT<9> A_BLT_SEL A_PRE_N A_SEL_P<9> A_WR_ONE ++ A_WR_ZERO VDD VSS / RM_IHPSG13_256x32_c2_1P_BLDRV +XA_BLTMUX<8> A_BLC<8> A_BLC_SEL A_BLT<8> A_BLT_SEL A_PRE_N A_SEL_P<8> A_WR_ONE ++ A_WR_ZERO VDD VSS / RM_IHPSG13_256x32_c2_1P_BLDRV +XA_BLTMUX<7> A_BLC<7> A_BLC_SEL A_BLT<7> A_BLT_SEL A_PRE_N A_SEL_P<7> A_WR_ONE ++ A_WR_ZERO VDD VSS / RM_IHPSG13_256x32_c2_1P_BLDRV +XA_BLTMUX<6> A_BLC<6> A_BLC_SEL A_BLT<6> A_BLT_SEL A_PRE_N A_SEL_P<6> A_WR_ONE ++ A_WR_ZERO VDD VSS / RM_IHPSG13_256x32_c2_1P_BLDRV +XA_BLTMUX<5> A_BLC<5> A_BLC_SEL A_BLT<5> A_BLT_SEL A_PRE_N A_SEL_P<5> A_WR_ONE ++ A_WR_ZERO VDD VSS / RM_IHPSG13_256x32_c2_1P_BLDRV +XA_BLTMUX<4> A_BLC<4> A_BLC_SEL A_BLT<4> A_BLT_SEL A_PRE_N A_SEL_P<4> A_WR_ONE ++ A_WR_ZERO VDD VSS / RM_IHPSG13_256x32_c2_1P_BLDRV +XA_BLTMUX<3> A_BLC<3> A_BLC_SEL A_BLT<3> A_BLT_SEL A_PRE_N A_SEL_P<3> A_WR_ONE ++ A_WR_ZERO VDD VSS / RM_IHPSG13_256x32_c2_1P_BLDRV +XA_BLTMUX<2> A_BLC<2> A_BLC_SEL A_BLT<2> A_BLT_SEL A_PRE_N A_SEL_P<2> A_WR_ONE ++ A_WR_ZERO VDD VSS / RM_IHPSG13_256x32_c2_1P_BLDRV +XA_BLTMUX<1> A_BLC<1> A_BLC_SEL A_BLT<1> A_BLT_SEL A_PRE_N A_SEL_P<1> A_WR_ONE ++ A_WR_ZERO VDD VSS / RM_IHPSG13_256x32_c2_1P_BLDRV +XA_BLTMUX<0> A_BLC<0> A_BLC_SEL A_BLT<0> A_BLT_SEL A_PRE_N A_SEL_P<0> A_WR_ONE ++ A_WR_ZERO VDD VSS / RM_IHPSG13_256x32_c2_1P_BLDRV +XA_CAPS<17> VDD VSS / RSC_IHPSG13_FILLCAP4 +XA_CAPS<16> VDD VSS / RSC_IHPSG13_FILLCAP4 +XA_CAPS<15> VDD VSS / RSC_IHPSG13_FILLCAP4 +XA_CAPS<14> VDD VSS / RSC_IHPSG13_FILLCAP4 +XA_CAPS<13> VDD VSS / RSC_IHPSG13_FILLCAP4 +XA_CAPS<12> VDD VSS / RSC_IHPSG13_FILLCAP4 +XA_CAPS<11> VDD VSS / RSC_IHPSG13_FILLCAP4 +XA_CAPS<10> VDD VSS / RSC_IHPSG13_FILLCAP4 +XA_CAPS<9> VDD VSS / RSC_IHPSG13_FILLCAP4 +XA_CAPS<8> VDD VSS / RSC_IHPSG13_FILLCAP4 +XA_CAPS<7> VDD VSS / RSC_IHPSG13_FILLCAP4 +XA_CAPS<6> VDD VSS / RSC_IHPSG13_FILLCAP4 +XA_CAPS<5> VDD VSS / RSC_IHPSG13_FILLCAP4 +XA_CAPS<4> VDD VSS / RSC_IHPSG13_FILLCAP4 +XA_CAPS<3> VDD VSS / RSC_IHPSG13_FILLCAP4 +XA_CAPS<2> VDD VSS / RSC_IHPSG13_FILLCAP4 +XA_CAPS<1> VDD VSS / RSC_IHPSG13_FILLCAP4 +XA_I51 net19 A_DR_O VDD VSS / RSC_IHPSG13_INVX4 +XA_I78 A_RCLK_B_L A_SAE VDD VSS / RSC_IHPSG13_CBUFX2 +XA_I69 A_DCLK_L A_DCLK_B_L VDD VSS / RSC_IHPSG13_CINVX8 +XA_I50 A_WCLK_L A_WCLK_B_L VDD VSS / RSC_IHPSG13_CINVX8 +XA_EBUF A_RCLK_L A_RCLK_B_L VDD VSS / RSC_IHPSG13_CINVX8 +XA_I76 A_DI_N A_DO_WRITE_P A_WR_ZERO VDD VSS / RSC_IHPSG13_AND2X6 +XA_I75 A_DI_R A_DO_WRITE_P A_WR_ONE VDD VSS / RSC_IHPSG13_AND2X6 +XA_I83 A_BM_R A_BM_N VDD VSS / RSC_IHPSG13_INVX2 +XA_DEC3INV<31> net23<0> A_SEL_P<31> VDD VSS / RSC_IHPSG13_INVX2 +XA_DEC3INV<30> net23<1> A_SEL_P<30> VDD VSS / RSC_IHPSG13_INVX2 +XA_DEC3INV<29> net23<2> A_SEL_P<29> VDD VSS / RSC_IHPSG13_INVX2 +XA_DEC3INV<28> net23<3> A_SEL_P<28> VDD VSS / RSC_IHPSG13_INVX2 +XA_DEC3INV<27> net23<4> A_SEL_P<27> VDD VSS / RSC_IHPSG13_INVX2 +XA_DEC3INV<26> net23<5> A_SEL_P<26> VDD VSS / RSC_IHPSG13_INVX2 +XA_DEC3INV<25> net23<6> A_SEL_P<25> VDD VSS / RSC_IHPSG13_INVX2 +XA_DEC3INV<24> net23<7> A_SEL_P<24> VDD VSS / RSC_IHPSG13_INVX2 +XA_DEC3INV<23> net23<8> A_SEL_P<23> VDD VSS / RSC_IHPSG13_INVX2 +XA_DEC3INV<22> net23<9> A_SEL_P<22> VDD VSS / RSC_IHPSG13_INVX2 +XA_DEC3INV<21> net23<10> A_SEL_P<21> VDD VSS / RSC_IHPSG13_INVX2 +XA_DEC3INV<20> net23<11> A_SEL_P<20> VDD VSS / RSC_IHPSG13_INVX2 +XA_DEC3INV<19> net23<12> A_SEL_P<19> VDD VSS / RSC_IHPSG13_INVX2 +XA_DEC3INV<18> net23<13> A_SEL_P<18> VDD VSS / RSC_IHPSG13_INVX2 +XA_DEC3INV<17> net23<14> A_SEL_P<17> VDD VSS / RSC_IHPSG13_INVX2 +XA_DEC3INV<16> net23<15> A_SEL_P<16> VDD VSS / RSC_IHPSG13_INVX2 +XA_DEC3INV<15> net23<16> A_SEL_P<15> VDD VSS / RSC_IHPSG13_INVX2 +XA_DEC3INV<14> net23<17> A_SEL_P<14> VDD VSS / RSC_IHPSG13_INVX2 +XA_DEC3INV<13> net23<18> A_SEL_P<13> VDD VSS / RSC_IHPSG13_INVX2 +XA_DEC3INV<12> net23<19> A_SEL_P<12> VDD VSS / RSC_IHPSG13_INVX2 +XA_DEC3INV<11> net23<20> A_SEL_P<11> VDD VSS / RSC_IHPSG13_INVX2 +XA_DEC3INV<10> net23<21> A_SEL_P<10> VDD VSS / RSC_IHPSG13_INVX2 +XA_DEC3INV<9> net23<22> A_SEL_P<9> VDD VSS / RSC_IHPSG13_INVX2 +XA_DEC3INV<8> net23<23> A_SEL_P<8> VDD VSS / RSC_IHPSG13_INVX2 +XA_DEC3INV<7> net23<24> A_SEL_P<7> VDD VSS / RSC_IHPSG13_INVX2 +XA_DEC3INV<6> net23<25> A_SEL_P<6> VDD VSS / RSC_IHPSG13_INVX2 +XA_DEC3INV<5> net23<26> A_SEL_P<5> VDD VSS / RSC_IHPSG13_INVX2 +XA_DEC3INV<4> net23<27> A_SEL_P<4> VDD VSS / RSC_IHPSG13_INVX2 +XA_DEC3INV<3> net23<28> A_SEL_P<3> VDD VSS / RSC_IHPSG13_INVX2 +XA_DEC3INV<2> net23<29> A_SEL_P<2> VDD VSS / RSC_IHPSG13_INVX2 +XA_DEC3INV<1> net23<30> A_SEL_P<1> VDD VSS / RSC_IHPSG13_INVX2 +XA_DEC3INV<0> net23<31> A_SEL_P<0> VDD VSS / RSC_IHPSG13_INVX2 +XA_I49 A_DI_R A_DI_N VDD VSS / RSC_IHPSG13_INVX2 +XA_ISENSE A_SAE A_BLC_SEL A_BLT_SEL net19 net20 VDD VSS / ++ RSC_IHPSG13_DFPQD_MSAFFX2 +XA_DREG A_BIST_EN_I A_BIST_DW_I A_DCLK_B_L A_DW_I A_DI_R net22 VDD VSS ++ / RSC_IHPSG13_DFNQMX2IX1 +XA_BREG A_BIST_EN_I A_BIST_BM_I A_DCLK_B_L A_BM_I A_BM_R net21 VDD VSS ++ / RSC_IHPSG13_DFNQMX2IX1 +XA_DEC3<31> A_P1<1> A_P0<1> A_ADDR_DEC<7> net23<0> VDD VSS / ++ RSC_IHPSG13_NAND3X2 +XA_DEC3<30> A_P1<1> A_P0<1> A_ADDR_DEC<6> net23<1> VDD VSS / ++ RSC_IHPSG13_NAND3X2 +XA_DEC3<29> A_P1<1> A_P0<1> A_ADDR_DEC<5> net23<2> VDD VSS / ++ RSC_IHPSG13_NAND3X2 +XA_DEC3<28> A_P1<1> A_P0<1> A_ADDR_DEC<4> net23<3> VDD VSS / ++ RSC_IHPSG13_NAND3X2 +XA_DEC3<27> A_P1<1> A_P0<1> A_ADDR_DEC<3> net23<4> VDD VSS / ++ RSC_IHPSG13_NAND3X2 +XA_DEC3<26> A_P1<1> A_P0<1> A_ADDR_DEC<2> net23<5> VDD VSS / ++ RSC_IHPSG13_NAND3X2 +XA_DEC3<25> A_P1<1> A_P0<1> A_ADDR_DEC<1> net23<6> VDD VSS / ++ RSC_IHPSG13_NAND3X2 +XA_DEC3<24> A_P1<1> A_P0<1> A_ADDR_DEC<0> net23<7> VDD VSS / ++ RSC_IHPSG13_NAND3X2 +XA_DEC3<23> A_P1<1> A_N0<1> A_ADDR_DEC<7> net23<8> VDD VSS / ++ RSC_IHPSG13_NAND3X2 +XA_DEC3<22> A_P1<1> A_N0<1> A_ADDR_DEC<6> net23<9> VDD VSS / ++ RSC_IHPSG13_NAND3X2 +XA_DEC3<21> A_P1<1> A_N0<1> A_ADDR_DEC<5> net23<10> VDD VSS / ++ RSC_IHPSG13_NAND3X2 +XA_DEC3<20> A_P1<1> A_N0<1> A_ADDR_DEC<4> net23<11> VDD VSS / ++ RSC_IHPSG13_NAND3X2 +XA_DEC3<19> A_P1<1> A_N0<1> A_ADDR_DEC<3> net23<12> VDD VSS / ++ RSC_IHPSG13_NAND3X2 +XA_DEC3<18> A_P1<1> A_N0<1> A_ADDR_DEC<2> net23<13> VDD VSS / ++ RSC_IHPSG13_NAND3X2 +XA_DEC3<17> A_P1<1> A_N0<1> A_ADDR_DEC<1> net23<14> VDD VSS / ++ RSC_IHPSG13_NAND3X2 +XA_DEC3<16> A_P1<1> A_N0<1> A_ADDR_DEC<0> net23<15> VDD VSS / ++ RSC_IHPSG13_NAND3X2 +XA_DEC3<15> A_N1<0> A_P0<0> A_ADDR_DEC<7> net23<16> VDD VSS / ++ RSC_IHPSG13_NAND3X2 +XA_DEC3<14> A_N1<0> A_P0<0> A_ADDR_DEC<6> net23<17> VDD VSS / ++ RSC_IHPSG13_NAND3X2 +XA_DEC3<13> A_N1<0> A_P0<0> A_ADDR_DEC<5> net23<18> VDD VSS / ++ RSC_IHPSG13_NAND3X2 +XA_DEC3<12> A_N1<0> A_P0<0> A_ADDR_DEC<4> net23<19> VDD VSS / ++ RSC_IHPSG13_NAND3X2 +XA_DEC3<11> A_N1<0> A_P0<0> A_ADDR_DEC<3> net23<20> VDD VSS / ++ RSC_IHPSG13_NAND3X2 +XA_DEC3<10> A_N1<0> A_P0<0> A_ADDR_DEC<2> net23<21> VDD VSS / ++ RSC_IHPSG13_NAND3X2 +XA_DEC3<9> A_N1<0> A_P0<0> A_ADDR_DEC<1> net23<22> VDD VSS / ++ RSC_IHPSG13_NAND3X2 +XA_DEC3<8> A_N1<0> A_P0<0> A_ADDR_DEC<0> net23<23> VDD VSS / ++ RSC_IHPSG13_NAND3X2 +XA_DEC3<7> A_N1<0> A_N0<0> A_ADDR_DEC<7> net23<24> VDD VSS / ++ RSC_IHPSG13_NAND3X2 +XA_DEC3<6> A_N1<0> A_N0<0> A_ADDR_DEC<6> net23<25> VDD VSS / ++ RSC_IHPSG13_NAND3X2 +XA_DEC3<5> A_N1<0> A_N0<0> A_ADDR_DEC<5> net23<26> VDD VSS / ++ RSC_IHPSG13_NAND3X2 +XA_DEC3<4> A_N1<0> A_N0<0> A_ADDR_DEC<4> net23<27> VDD VSS / ++ RSC_IHPSG13_NAND3X2 +XA_DEC3<3> A_N1<0> A_N0<0> A_ADDR_DEC<3> net23<28> VDD VSS / ++ RSC_IHPSG13_NAND3X2 +XA_DEC3<2> A_N1<0> A_N0<0> A_ADDR_DEC<2> net23<29> VDD VSS / ++ RSC_IHPSG13_NAND3X2 +XA_DEC3<1> A_N1<0> A_N0<0> A_ADDR_DEC<1> net23<30> VDD VSS / ++ RSC_IHPSG13_NAND3X2 +XA_DEC3<0> A_N1<0> A_N0<0> A_ADDR_DEC<0> net23<31> VDD VSS / ++ RSC_IHPSG13_NAND3X2 +XA_I89 A_DCLK_B_L A_DCLK_B_R / RSC_IHPSG13_MET3RES +XA_I91 A_RCLK_B_L A_RCLK_B_R / RSC_IHPSG13_MET3RES +XA_I90 A_WCLK_B_L A_WCLK_B_R / RSC_IHPSG13_MET3RES +XA_I88 A_DCLK_L A_DCLK_R / RSC_IHPSG13_MET3RES +XA_I87 A_WCLK_L A_WCLK_R / RSC_IHPSG13_MET3RES +XA_R2 A_RCLK_L A_RCLK_R / RSC_IHPSG13_MET3RES +XA_BM_TIEH A_TIEH_O VDD VSS / RSC_IHPSG13_TIEH +.ENDS + +.SUBCKT RM_IHPSG13_256x32_c2_1P_COLDRV13X12 ADDR_COL_I<1> ADDR_COL_I<0> ADDR_COL_O<1> ++ ADDR_COL_O<0> ADDR_DEC_I<7> ADDR_DEC_I<6> ADDR_DEC_I<5> ADDR_DEC_I<4> ++ ADDR_DEC_I<3> ADDR_DEC_I<2> ADDR_DEC_I<1> ADDR_DEC_I<0> ADDR_DEC_O<7> ++ ADDR_DEC_O<6> ADDR_DEC_O<5> ADDR_DEC_O<4> ADDR_DEC_O<3> ADDR_DEC_O<2> ++ ADDR_DEC_O<1> ADDR_DEC_O<0> DCLK_I DCLK_O RCLK_I RCLK_O WCLK_I WCLK_O ++ VDD VSS +XI1<1> VDD VSS / RSC_IHPSG13_FILLCAP4 +XI1<0> VDD VSS / RSC_IHPSG13_FILLCAP4 +XI0<1> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI0<0> VDD VSS / RSC_IHPSG13_FILLCAP8 +XADDR_COL_DRV<1> ADDR_COL_I<1> ADDR_COL_O<1> VDD VSS / ++ RSC_IHPSG13_CBUFX12 +XADDR_COL_DRV<0> ADDR_COL_I<0> ADDR_COL_O<0> VDD VSS / ++ RSC_IHPSG13_CBUFX12 +XADDR_DEC_DRV<7> ADDR_DEC_I<7> ADDR_DEC_O<7> VDD VSS / ++ RSC_IHPSG13_CBUFX12 +XADDR_DEC_DRV<6> ADDR_DEC_I<6> ADDR_DEC_O<6> VDD VSS / ++ RSC_IHPSG13_CBUFX12 +XADDR_DEC_DRV<5> ADDR_DEC_I<5> ADDR_DEC_O<5> VDD VSS / ++ RSC_IHPSG13_CBUFX12 +XADDR_DEC_DRV<4> ADDR_DEC_I<4> ADDR_DEC_O<4> VDD VSS / ++ RSC_IHPSG13_CBUFX12 +XADDR_DEC_DRV<3> ADDR_DEC_I<3> ADDR_DEC_O<3> VDD VSS / ++ RSC_IHPSG13_CBUFX12 +XADDR_DEC_DRV<2> ADDR_DEC_I<2> ADDR_DEC_O<2> VDD VSS / ++ RSC_IHPSG13_CBUFX12 +XADDR_DEC_DRV<1> ADDR_DEC_I<1> ADDR_DEC_O<1> VDD VSS / ++ RSC_IHPSG13_CBUFX12 +XADDR_DEC_DRV<0> ADDR_DEC_I<0> ADDR_DEC_O<0> VDD VSS / ++ RSC_IHPSG13_CBUFX12 +XDCLK_DRV DCLK_I DCLK_O VDD VSS / RSC_IHPSG13_CBUFX12 +XRCLK_DRV RCLK_I RCLK_O VDD VSS / RSC_IHPSG13_CBUFX12 +XWCLK_DRV WCLK_I WCLK_O VDD VSS / RSC_IHPSG13_CBUFX12 +.ENDS +.SUBCKT RM_IHPSG13_256x32_c2_1P_WLDRV16X12 A<15> A<14> A<13> A<12> A<11> A<10> A<9> A<8> ++ A<7> A<6> A<5> A<4> A<3> A<2> A<1> A<0> Z<15> Z<14> Z<13> Z<12> Z<11> Z<10> ++ Z<9> Z<8> Z<7> Z<6> Z<5> Z<4> Z<3> Z<2> Z<1> Z<0> VDD VSS +XBUF<15> A<15> Z<15> VDD VSS / RSC_IHPSG13_WLDRVX12 +XBUF<14> A<14> Z<14> VDD VSS / RSC_IHPSG13_WLDRVX12 +XBUF<13> A<13> Z<13> VDD VSS / RSC_IHPSG13_WLDRVX12 +XBUF<12> A<12> Z<12> VDD VSS / RSC_IHPSG13_WLDRVX12 +XBUF<11> A<11> Z<11> VDD VSS / RSC_IHPSG13_WLDRVX12 +XBUF<10> A<10> Z<10> VDD VSS / RSC_IHPSG13_WLDRVX12 +XBUF<9> A<9> Z<9> VDD VSS / RSC_IHPSG13_WLDRVX12 +XBUF<8> A<8> Z<8> VDD VSS / RSC_IHPSG13_WLDRVX12 +XBUF<7> A<7> Z<7> VDD VSS / RSC_IHPSG13_WLDRVX12 +XBUF<6> A<6> Z<6> VDD VSS / RSC_IHPSG13_WLDRVX12 +XBUF<5> A<5> Z<5> VDD VSS / RSC_IHPSG13_WLDRVX12 +XBUF<4> A<4> Z<4> VDD VSS / RSC_IHPSG13_WLDRVX12 +XBUF<3> A<3> Z<3> VDD VSS / RSC_IHPSG13_WLDRVX12 +XBUF<2> A<2> Z<2> VDD VSS / RSC_IHPSG13_WLDRVX12 +XBUF<1> A<1> Z<1> VDD VSS / RSC_IHPSG13_WLDRVX12 +XBUF<0> A<0> Z<0> VDD VSS / RSC_IHPSG13_WLDRVX12 +.ENDS + + + +.SUBCKT RM_IHPSG13_256x32_c2_2P_COLDRV13X8 ADDR_COL_I<1> ADDR_COL_I<0> ADDR_COL_O<1> ++ ADDR_COL_O<0> ADDR_DEC_I<7> ADDR_DEC_I<6> ADDR_DEC_I<5> ADDR_DEC_I<4> ++ ADDR_DEC_I<3> ADDR_DEC_I<2> ADDR_DEC_I<1> ADDR_DEC_I<0> ADDR_DEC_O<7> ++ ADDR_DEC_O<6> ADDR_DEC_O<5> ADDR_DEC_O<4> ADDR_DEC_O<3> ADDR_DEC_O<2> ++ ADDR_DEC_O<1> ADDR_DEC_O<0> DCLK_I DCLK_O RCLK_I RCLK_O WCLK_I WCLK_O ++ VDD VSS +XI0<5> VDD VSS / RSC_IHPSG13_FILLCAP4 +XI0<4> VDD VSS / RSC_IHPSG13_FILLCAP4 +XI0<3> VDD VSS / RSC_IHPSG13_FILLCAP4 +XI0<2> VDD VSS / RSC_IHPSG13_FILLCAP4 +XI0<1> VDD VSS / RSC_IHPSG13_FILLCAP4 +XWCLK_DRV WCLK_I WCLK_O VDD VSS / RSC_IHPSG13_CBUFX8 +XRCLK_DRV RCLK_I RCLK_O VDD VSS / RSC_IHPSG13_CBUFX8 +XDCLK_DRV DCLK_I DCLK_O VDD VSS / RSC_IHPSG13_CBUFX8 +XADDR_COL_DRV<1> ADDR_COL_I<1> ADDR_COL_O<1> VDD VSS / ++ RSC_IHPSG13_CBUFX8 +XADDR_COL_DRV<0> ADDR_COL_I<0> ADDR_COL_O<0> VDD VSS / ++ RSC_IHPSG13_CBUFX8 +XADDR_DEC_DRV<7> ADDR_DEC_I<7> ADDR_DEC_O<7> VDD VSS / ++ RSC_IHPSG13_CBUFX8 +XADDR_DEC_DRV<6> ADDR_DEC_I<6> ADDR_DEC_O<6> VDD VSS / ++ RSC_IHPSG13_CBUFX8 +XADDR_DEC_DRV<5> ADDR_DEC_I<5> ADDR_DEC_O<5> VDD VSS / ++ RSC_IHPSG13_CBUFX8 +XADDR_DEC_DRV<4> ADDR_DEC_I<4> ADDR_DEC_O<4> VDD VSS / ++ RSC_IHPSG13_CBUFX8 +XADDR_DEC_DRV<3> ADDR_DEC_I<3> ADDR_DEC_O<3> VDD VSS / ++ RSC_IHPSG13_CBUFX8 +XADDR_DEC_DRV<2> ADDR_DEC_I<2> ADDR_DEC_O<2> VDD VSS / ++ RSC_IHPSG13_CBUFX8 +XADDR_DEC_DRV<1> ADDR_DEC_I<1> ADDR_DEC_O<1> VDD VSS / ++ RSC_IHPSG13_CBUFX8 +XADDR_DEC_DRV<0> ADDR_DEC_I<0> ADDR_DEC_O<0> VDD VSS / ++ RSC_IHPSG13_CBUFX8 +XI1<3> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI1<2> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI1<1> VDD VSS / RSC_IHPSG13_FILLCAP8 +.ENDS +.SUBCKT RSC_IHPSG13_WLDRVX8 A Z VDD VSS +MN1 Z net6 VSS VSS sg13_lv_nmos m=1 w=1.41u l=130.00n ng=2 nrd=0 nrs=0 +MN0 net6 A VSS VSS sg13_lv_nmos m=1 w=1.8u l=130.00n ng=2 nrd=0 nrs=0 +MP1 Z net6 VDD VDD sg13_lv_pmos m=1 w=6.48u l=130.00n ng=4 nrd=0 nrs=0 +MP0 net6 A VDD VDD sg13_lv_pmos m=1 w=900.0n l=130.00n ng=1 nrd=0 nrs=0 +.ENDS +.SUBCKT RM_IHPSG13_256x32_c2_2P_WLDRV16X8 A<15> A<14> A<13> A<12> A<11> A<10> A<9> A<8> ++ A<7> A<6> A<5> A<4> A<3> A<2> A<1> A<0> Z<15> Z<14> Z<13> Z<12> Z<11> Z<10> ++ Z<9> Z<8> Z<7> Z<6> Z<5> Z<4> Z<3> Z<2> Z<1> Z<0> VDD VSS +XBUF<15> A<15> Z<15> VDD VSS / RSC_IHPSG13_WLDRVX8 +XBUF<14> A<14> Z<14> VDD VSS / RSC_IHPSG13_WLDRVX8 +XBUF<13> A<13> Z<13> VDD VSS / RSC_IHPSG13_WLDRVX8 +XBUF<12> A<12> Z<12> VDD VSS / RSC_IHPSG13_WLDRVX8 +XBUF<11> A<11> Z<11> VDD VSS / RSC_IHPSG13_WLDRVX8 +XBUF<10> A<10> Z<10> VDD VSS / RSC_IHPSG13_WLDRVX8 +XBUF<9> A<9> Z<9> VDD VSS / RSC_IHPSG13_WLDRVX8 +XBUF<8> A<8> Z<8> VDD VSS / RSC_IHPSG13_WLDRVX8 +XBUF<7> A<7> Z<7> VDD VSS / RSC_IHPSG13_WLDRVX8 +XBUF<6> A<6> Z<6> VDD VSS / RSC_IHPSG13_WLDRVX8 +XBUF<5> A<5> Z<5> VDD VSS / RSC_IHPSG13_WLDRVX8 +XBUF<4> A<4> Z<4> VDD VSS / RSC_IHPSG13_WLDRVX8 +XBUF<3> A<3> Z<3> VDD VSS / RSC_IHPSG13_WLDRVX8 +XBUF<2> A<2> Z<2> VDD VSS / RSC_IHPSG13_WLDRVX8 +XBUF<1> A<1> Z<1> VDD VSS / RSC_IHPSG13_WLDRVX8 +XBUF<0> A<0> Z<0> VDD VSS / RSC_IHPSG13_WLDRVX8 +.ENDS + + + +.SUBCKT RM_IHPSG13_256x32_c2_2P_COLDEC2 ACLK_N ADDR<1> ADDR<0> ADDR_COL<1> ADDR_COL<0> ++ ADDR_DEC<7> ADDR_DEC<6> ADDR_DEC<5> ADDR_DEC<4> ADDR_DEC<3> ADDR_DEC<2> ++ ADDR_DEC<1> ADDR_DEC<0> BIST_ADDR<1> BIST_ADDR<0> BIST_EN_I VDD VSS +XI16<17> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI16<16> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI16<15> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI16<14> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI16<13> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI16<12> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI16<11> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI16<10> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI16<9> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI16<8> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI16<7> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI16<6> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI16<5> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI16<4> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI16<3> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI16<2> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI16<1> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI18<24> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI18<23> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI18<22> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI18<21> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI18<20> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI18<19> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI18<18> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI18<17> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI18<16> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI18<15> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI18<14> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI18<13> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI18<12> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI18<11> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI18<10> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI18<9> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI18<8> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI18<7> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI18<6> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI18<5> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI18<4> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI18<3> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI18<2> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI18<1> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI1<3> PADR<0> PADR<1> addr_n<3> VDD VSS / RSC_IHPSG13_NAND2X2 +XI1<2> NADR<0> PADR<1> addr_n<2> VDD VSS / RSC_IHPSG13_NAND2X2 +XI1<1> PADR<0> NADR<1> addr_n<1> VDD VSS / RSC_IHPSG13_NAND2X2 +XI1<0> NADR<0> NADR<1> addr_n<0> VDD VSS / RSC_IHPSG13_NAND2X2 +XI17<1> ADDR_COL<1> VDD VSS / RSC_IHPSG13_TIEL +XI17<0> ADDR_COL<0> VDD VSS / RSC_IHPSG13_TIEL +XI14<3> ADDR_DEC<7> VDD VSS / RSC_IHPSG13_TIEL +XI14<2> ADDR_DEC<6> VDD VSS / RSC_IHPSG13_TIEL +XI14<1> ADDR_DEC<5> VDD VSS / RSC_IHPSG13_TIEL +XI14<0> ADDR_DEC<4> VDD VSS / RSC_IHPSG13_TIEL +XI13<1> NADR<1> PADR<1> VDD VSS / RSC_IHPSG13_INVX2 +XI13<0> NADR<0> PADR<0> VDD VSS / RSC_IHPSG13_INVX2 +XI3<1> padr_int<1> NADR<1> VDD VSS / RSC_IHPSG13_INVX2 +XI3<0> padr_int<0> NADR<0> VDD VSS / RSC_IHPSG13_INVX2 +XI2<3> addr_n<3> ADDR_DEC<3> VDD VSS / RSC_IHPSG13_INVX2 +XI2<2> addr_n<2> ADDR_DEC<2> VDD VSS / RSC_IHPSG13_INVX2 +XI2<1> addr_n<1> ADDR_DEC<1> VDD VSS / RSC_IHPSG13_INVX2 +XI2<0> addr_n<0> ADDR_DEC<0> VDD VSS / RSC_IHPSG13_INVX2 +XDFF<1> BIST_EN_I BIST_ADDR<1> ACLK_N ADDR<1> padr_int<1> net12<0> VDD ++ VSS / RSC_IHPSG13_DFNQMX2IX1 +XDFF<0> BIST_EN_I BIST_ADDR<0> ACLK_N ADDR<0> padr_int<0> net12<1> VDD ++ VSS / RSC_IHPSG13_DFNQMX2IX1 +XI15<5> VDD VSS / RSC_IHPSG13_FILLCAP4 +XI15<4> VDD VSS / RSC_IHPSG13_FILLCAP4 +XI15<3> VDD VSS / RSC_IHPSG13_FILLCAP4 +XI15<2> VDD VSS / RSC_IHPSG13_FILLCAP4 +XI15<1> VDD VSS / RSC_IHPSG13_FILLCAP4 +XI19<4> VDD VSS / RSC_IHPSG13_FILLCAP4 +XI19<3> VDD VSS / RSC_IHPSG13_FILLCAP4 +XI19<2> VDD VSS / RSC_IHPSG13_FILLCAP4 +XI19<1> VDD VSS / RSC_IHPSG13_FILLCAP4 +.ENDS +.SUBCKT RM_IHPSG13_256x32_c2_2P_COLCTRL2 A_ADDR_DEC<3> A_ADDR_DEC<2> A_ADDR_DEC<1> ++ A_ADDR_DEC<0> A_BIST_BM_I A_BIST_DW_I A_BIST_EN_I A_BLC<3> A_BLC<2> A_BLC<1> ++ A_BLC<0> A_BLT<3> A_BLT<2> A_BLT<1> A_BLT<0> A_BM_I A_DCLK_B_L A_DCLK_B_R ++ A_DCLK_L A_DCLK_R A_DR_O A_DW_I A_RCLK_B_L A_RCLK_B_R A_RCLK_L A_RCLK_R ++ A_TIEH_O A_WCLK_B_L A_WCLK_B_R A_WCLK_L A_WCLK_R B_ADDR_DEC<3> B_ADDR_DEC<2> ++ B_ADDR_DEC<1> B_ADDR_DEC<0> B_BIST_BM_I B_BIST_DW_I B_BIST_EN_I B_BLC<3> ++ B_BLC<2> B_BLC<1> B_BLC<0> B_BLT<3> B_BLT<2> B_BLT<1> B_BLT<0> B_BM_I ++ B_DCLK_B_L B_DCLK_B_R B_DCLK_L B_DCLK_R B_DR_O B_DW_I B_RCLK_B_L B_RCLK_B_R ++ B_RCLK_L B_RCLK_R B_TIEH_O B_WCLK_B_L B_WCLK_B_R B_WCLK_L B_WCLK_R VDD ++ VSS +XB_DREG B_BIST_EN_I B_BIST_DW_I B_DCLK_B_L B_DW_I B_DI_R net046 VDD ++ VSS / RSC_IHPSG13_DFNQMX2IX1 +XB_BREG B_BIST_EN_I B_BIST_BM_I B_DCLK_B_L B_BM_I B_BM_R net045 VDD ++ VSS / RSC_IHPSG13_DFNQMX2IX1 +XA_DREG A_BIST_EN_I A_BIST_DW_I A_DCLK_B_L A_DW_I A_DI_R net22 VDD VSS ++ / RSC_IHPSG13_DFNQMX2IX1 +XA_BREG A_BIST_EN_I A_BIST_BM_I A_DCLK_B_L A_BM_I A_BM_R net23 VDD VSS ++ / RSC_IHPSG13_DFNQMX2IX1 +XB_CAPS VDD VSS / RSC_IHPSG13_FILLCAP4 +XA_CAPS VDD VSS / RSC_IHPSG13_FILLCAP4 +XB_I75 B_DI_R B_DO_WRITE_P B_WR_ONE VDD VSS / RSC_IHPSG13_AND2X2 +XB_I80 B_RCLK_B_L B_WCLK_B_L net041 VDD VSS / RSC_IHPSG13_AND2X2 +XB_I76 B_DI_N B_DO_WRITE_P B_WR_ZERO VDD VSS / RSC_IHPSG13_AND2X2 +XA_I80 A_RCLK_B_L A_WCLK_B_L net21 VDD VSS / RSC_IHPSG13_AND2X2 +XA_I75 A_DI_R A_DO_WRITE_P A_WR_ONE VDD VSS / RSC_IHPSG13_AND2X2 +XA_I76 A_DI_N A_DO_WRITE_P A_WR_ZERO VDD VSS / RSC_IHPSG13_AND2X2 +XB_I44 B_WCLK_B_L B_BM_N B_DO_WRITE_P VDD VSS / RSC_IHPSG13_NOR2X2 +XA_I44 A_WCLK_B_L A_BM_N A_DO_WRITE_P VDD VSS / RSC_IHPSG13_NOR2X2 +XB_I81 net041 B_PRE_N VDD VSS / RSC_IHPSG13_CINVX4_WN +XA_I81 net21 A_PRE_N VDD VSS / RSC_IHPSG13_CINVX4_WN +XB_BM_TIEH B_TIEH_O VDD VSS / RSC_IHPSG13_TIEH +XA_BM_TIEH A_TIEH_O VDD VSS / RSC_IHPSG13_TIEH +XA_I89 A_DCLK_B_L A_DCLK_B_R / RSC_IHPSG13_MET3RES +XA_I88 A_DCLK_L A_DCLK_R / RSC_IHPSG13_MET3RES +XA_I87 A_WCLK_L A_WCLK_R / RSC_IHPSG13_MET3RES +XA_I91 A_RCLK_B_L A_RCLK_B_R / RSC_IHPSG13_MET3RES +XB_I87 B_WCLK_L B_WCLK_R / RSC_IHPSG13_MET3RES +XB_I88 B_DCLK_L B_DCLK_R / RSC_IHPSG13_MET3RES +XB_I89 B_DCLK_B_L B_DCLK_B_R / RSC_IHPSG13_MET3RES +XB_I90 B_WCLK_B_L B_WCLK_B_R / RSC_IHPSG13_MET3RES +XB_R2 B_RCLK_L B_RCLK_R / RSC_IHPSG13_MET3RES +XB_I91 B_RCLK_B_L B_RCLK_B_R / RSC_IHPSG13_MET3RES +XA_R2 A_RCLK_L A_RCLK_R / RSC_IHPSG13_MET3RES +XA_I90 A_WCLK_B_L A_WCLK_B_R / RSC_IHPSG13_MET3RES +XAB_BLMUX A_BLC<3> A_BLC<2> A_BLC<1> A_BLC<0> A_BLC_SEL A_BLT<3> A_BLT<2> ++ A_BLT<1> A_BLT<0> A_BLT_SEL A_PRE_N A_ADDR_DEC<3> A_ADDR_DEC<2> ++ A_ADDR_DEC<1> A_ADDR_DEC<0> A_WR_ONE A_WR_ZERO B_BLC<3> B_BLC<2> B_BLC<1> ++ B_BLC<0> B_BLC_SEL B_BLT<3> B_BLT<2> B_BLT<1> B_BLT<0> B_BLT_SEL B_PRE_N ++ B_ADDR_DEC<3> B_ADDR_DEC<2> B_ADDR_DEC<1> B_ADDR_DEC<0> B_WR_ONE B_WR_ZERO ++ VDD VSS / RM_IHPSG13_256x32_c2_2P_BLDRV +XB_ISENSE B_SAE B_BLC_SEL B_BLT_SEL net039 net040 VDD VSS / ++ RSC_IHPSG13_DFPQD_MSAFFX2 +XA_ISENSE A_SAE A_BLC_SEL A_BLT_SEL net19 net20 VDD VSS / ++ RSC_IHPSG13_DFPQD_MSAFFX2 +XB_I78 B_RCLK_B_L B_SAE VDD VSS / RSC_IHPSG13_CBUFX2 +XA_I78 A_RCLK_B_L A_SAE VDD VSS / RSC_IHPSG13_CBUFX2 +XB_I83 B_BM_R B_BM_N VDD VSS / RSC_IHPSG13_INVX2 +XB_I49 B_DI_R B_DI_N VDD VSS / RSC_IHPSG13_INVX2 +XA_I83 A_BM_R A_BM_N VDD VSS / RSC_IHPSG13_INVX2 +XA_I49 A_DI_R A_DI_N VDD VSS / RSC_IHPSG13_INVX2 +XB_I51 net039 B_DR_O VDD VSS / RSC_IHPSG13_INVX4 +XA_I51 net19 A_DR_O VDD VSS / RSC_IHPSG13_INVX4 +XA_I69 A_DCLK_L A_DCLK_B_L VDD VSS / RSC_IHPSG13_CINVX2 +XA_I50 A_WCLK_L A_WCLK_B_L VDD VSS / RSC_IHPSG13_CINVX2 +XA_EBUF A_RCLK_L A_RCLK_B_L VDD VSS / RSC_IHPSG13_CINVX2 +XB_EBUF B_RCLK_L B_RCLK_B_L VDD VSS / RSC_IHPSG13_CINVX2 +XB_I50 B_WCLK_L B_WCLK_B_L VDD VSS / RSC_IHPSG13_CINVX2 +XB_I69 B_DCLK_L B_DCLK_B_L VDD VSS / RSC_IHPSG13_CINVX2 +.ENDS +.SUBCKT RM_IHPSG13_256x32_c2_2P_COLDRV13_FILL4C2 VDD VSS +XI0<2> VDD VSS / RSC_IHPSG13_FILLCAP4 +XI0<1> VDD VSS / RSC_IHPSG13_FILLCAP4 +.ENDS + + +.SUBCKT RM_IHPSG13_256x32_c2_2P_ROWDEC7 ADDR_N_I<6> ADDR_N_I<5> ADDR_N_I<4> ADDR_N_I<3> ++ ADDR_N_I<2> ADDR_N_I<1> ADDR_N_I<0> CS_I ECLK_I WL_O<127> WL_O<126> ++ WL_O<125> WL_O<124> WL_O<123> WL_O<122> WL_O<121> WL_O<120> WL_O<119> ++ WL_O<118> WL_O<117> WL_O<116> WL_O<115> WL_O<114> WL_O<113> WL_O<112> ++ WL_O<111> WL_O<110> WL_O<109> WL_O<108> WL_O<107> WL_O<106> WL_O<105> ++ WL_O<104> WL_O<103> WL_O<102> WL_O<101> WL_O<100> WL_O<99> WL_O<98> WL_O<97> ++ WL_O<96> WL_O<95> WL_O<94> WL_O<93> WL_O<92> WL_O<91> WL_O<90> WL_O<89> ++ WL_O<88> WL_O<87> WL_O<86> WL_O<85> WL_O<84> WL_O<83> WL_O<82> WL_O<81> ++ WL_O<80> WL_O<79> WL_O<78> WL_O<77> WL_O<76> WL_O<75> WL_O<74> WL_O<73> ++ WL_O<72> WL_O<71> WL_O<70> WL_O<69> WL_O<68> WL_O<67> WL_O<66> WL_O<65> ++ WL_O<64> WL_O<63> WL_O<62> WL_O<61> WL_O<60> WL_O<59> WL_O<58> WL_O<57> ++ WL_O<56> WL_O<55> WL_O<54> WL_O<53> WL_O<52> WL_O<51> WL_O<50> WL_O<49> ++ WL_O<48> WL_O<47> WL_O<46> WL_O<45> WL_O<44> WL_O<43> WL_O<42> WL_O<41> ++ WL_O<40> WL_O<39> WL_O<38> WL_O<37> WL_O<36> WL_O<35> WL_O<34> WL_O<33> ++ WL_O<32> WL_O<31> WL_O<30> WL_O<29> WL_O<28> WL_O<27> WL_O<26> WL_O<25> ++ WL_O<24> WL_O<23> WL_O<22> WL_O<21> WL_O<20> WL_O<19> WL_O<18> WL_O<17> ++ WL_O<16> WL_O<15> WL_O<14> WL_O<13> WL_O<12> WL_O<11> WL_O<10> WL_O<9> ++ WL_O<8> WL_O<7> WL_O<6> WL_O<5> WL_O<4> WL_O<3> WL_O<2> WL_O<1> WL_O<0> ++ VDD VSS +XSEL<7> ADDR_N_I<3> ADDR_N_I<2> ADDR_N_I<1> ADDR_N_I<0> CS00<7> ECLK_H<7> ++ ECLK_H<8> ECLK_B<7> ECLK_B<8> WL_O<127> WL_O<126> WL_O<125> WL_O<124> ++ WL_O<123> WL_O<122> WL_O<121> WL_O<120> WL_O<119> WL_O<118> WL_O<117> ++ WL_O<116> WL_O<115> WL_O<114> WL_O<113> WL_O<112> VDD VSS / ++ RM_IHPSG13_256x32_c2_2P_DEC04 +XSEL<6> ADDR_N_I<3> ADDR_N_I<2> ADDR_N_I<1> ADDR_N_I<0> CS00<6> ECLK_H<6> ++ ECLK_H<7> ECLK_B<6> ECLK_B<7> WL_O<111> WL_O<110> WL_O<109> WL_O<108> ++ WL_O<107> WL_O<106> WL_O<105> WL_O<104> WL_O<103> WL_O<102> WL_O<101> ++ WL_O<100> WL_O<99> WL_O<98> WL_O<97> WL_O<96> VDD VSS / ++ RM_IHPSG13_256x32_c2_2P_DEC04 +XSEL<5> ADDR_N_I<3> ADDR_N_I<2> ADDR_N_I<1> ADDR_N_I<0> CS00<5> ECLK_H<5> ++ ECLK_H<6> ECLK_B<5> ECLK_B<6> WL_O<95> WL_O<94> WL_O<93> WL_O<92> WL_O<91> ++ WL_O<90> WL_O<89> WL_O<88> WL_O<87> WL_O<86> WL_O<85> WL_O<84> WL_O<83> ++ WL_O<82> WL_O<81> WL_O<80> VDD VSS / RM_IHPSG13_256x32_c2_2P_DEC04 +XSEL<4> ADDR_N_I<3> ADDR_N_I<2> ADDR_N_I<1> ADDR_N_I<0> CS00<4> ECLK_H<4> ++ ECLK_H<5> ECLK_B<4> ECLK_B<5> WL_O<79> WL_O<78> WL_O<77> WL_O<76> WL_O<75> ++ WL_O<74> WL_O<73> WL_O<72> WL_O<71> WL_O<70> WL_O<69> WL_O<68> WL_O<67> ++ WL_O<66> WL_O<65> WL_O<64> VDD VSS / RM_IHPSG13_256x32_c2_2P_DEC04 +XSEL<3> ADDR_N_I<3> ADDR_N_I<2> ADDR_N_I<1> ADDR_N_I<0> CS00<3> ECLK_H<3> ++ ECLK_H<4> ECLK_B<3> ECLK_B<4> WL_O<63> WL_O<62> WL_O<61> WL_O<60> WL_O<59> ++ WL_O<58> WL_O<57> WL_O<56> WL_O<55> WL_O<54> WL_O<53> WL_O<52> WL_O<51> ++ WL_O<50> WL_O<49> WL_O<48> VDD VSS / RM_IHPSG13_256x32_c2_2P_DEC04 +XSEL<2> ADDR_N_I<3> ADDR_N_I<2> ADDR_N_I<1> ADDR_N_I<0> CS00<2> ECLK_H<2> ++ ECLK_H<3> ECLK_B<2> ECLK_B<3> WL_O<47> WL_O<46> WL_O<45> WL_O<44> WL_O<43> ++ WL_O<42> WL_O<41> WL_O<40> WL_O<39> WL_O<38> WL_O<37> WL_O<36> WL_O<35> ++ WL_O<34> WL_O<33> WL_O<32> VDD VSS / RM_IHPSG13_256x32_c2_2P_DEC04 +XSEL<1> ADDR_N_I<3> ADDR_N_I<2> ADDR_N_I<1> ADDR_N_I<0> CS00<1> ECLK_H<1> ++ ECLK_H<2> ECLK_B<1> ECLK_B<2> WL_O<31> WL_O<30> WL_O<29> WL_O<28> WL_O<27> ++ WL_O<26> WL_O<25> WL_O<24> WL_O<23> WL_O<22> WL_O<21> WL_O<20> WL_O<19> ++ WL_O<18> WL_O<17> WL_O<16> VDD VSS / RM_IHPSG13_256x32_c2_2P_DEC04 +XSEL<0> ADDR_N_I<3> ADDR_N_I<2> ADDR_N_I<1> ADDR_N_I<0> CS00<0> ECLK_I ++ ECLK_H<1> ECLK_B<0> ECLK_B<1> WL_O<15> WL_O<14> WL_O<13> WL_O<12> WL_O<11> ++ WL_O<10> WL_O<9> WL_O<8> WL_O<7> WL_O<6> WL_O<5> WL_O<4> WL_O<3> WL_O<2> ++ WL_O<1> WL_O<0> VDD VSS / RM_IHPSG13_256x32_c2_2P_DEC04 +XDEC11<1> ADDR_N_I<5> ADDR_N_I<4> CS04<1> CS00<7> VDD VSS / ++ RM_IHPSG13_256x32_c2_2P_DEC03 +XDEC11<0> ADDR_N_I<5> ADDR_N_I<4> CS04<0> CS00<3> VDD VSS / ++ RM_IHPSG13_256x32_c2_2P_DEC03 +XDEC01<2> ADDR_N_I<7> ADDR_N_I<6> CS_I CS04<1> VDD VSS / ++ RM_IHPSG13_256x32_c2_2P_DEC01 +XDEC01<1> ADDR_N_I<5> ADDR_N_I<4> CS04<1> CS00<5> VDD VSS / ++ RM_IHPSG13_256x32_c2_2P_DEC01 +XDEC01<0> ADDR_N_I<5> ADDR_N_I<4> CS04<0> CS00<1> VDD VSS / ++ RM_IHPSG13_256x32_c2_2P_DEC01 +XL2<66> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<65> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<64> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<63> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<62> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<61> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<60> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<59> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<58> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<57> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<56> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<55> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<54> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<53> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<52> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<51> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<50> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<49> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<48> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<47> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<46> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<45> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<44> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<43> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<42> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<41> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<40> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<39> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<38> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<37> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<36> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<35> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<34> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<33> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<32> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<31> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<30> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<29> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<28> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<27> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<26> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<25> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<24> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<23> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<22> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<21> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<20> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<19> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<18> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<17> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<16> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<15> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<14> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<13> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<12> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<11> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<10> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<9> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<8> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<7> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<6> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<5> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<4> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<3> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<2> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<1> VDD VSS / RSC_IHPSG13_FILLCAP8 +XDEC10<1> ADDR_N_I<5> ADDR_N_I<4> CS04<1> CS00<6> VDD VSS / ++ RM_IHPSG13_256x32_c2_2P_DEC02 +XDEC10<0> ADDR_N_I<5> ADDR_N_I<4> CS04<0> CS00<2> VDD VSS / ++ RM_IHPSG13_256x32_c2_2P_DEC02 +XDEC00<2> ADDR_N_I<7> ADDR_N_I<6> CS_I CS04<0> VDD VSS / ++ RM_IHPSG13_256x32_c2_2P_DEC00 +XDEC00<1> ADDR_N_I<5> ADDR_N_I<4> CS04<1> CS00<4> VDD VSS / ++ RM_IHPSG13_256x32_c2_2P_DEC00 +XDEC00<0> ADDR_N_I<5> ADDR_N_I<4> CS04<0> CS00<0> VDD VSS / ++ RM_IHPSG13_256x32_c2_2P_DEC00 +XI0 ADDR_N_I<7> VDD VSS / RSC_IHPSG13_TIEL +.ENDS +.SUBCKT RM_IHPSG13_256x32_c2_2P_ROWREG7 ACLK_N_I ADDR_I<6> ADDR_I<5> ADDR_I<4> ADDR_I<3> ++ ADDR_I<2> ADDR_I<1> ADDR_I<0> ADDR_N_O<6> ADDR_N_O<5> ADDR_N_O<4> ++ ADDR_N_O<3> ADDR_N_O<2> ADDR_N_O<1> ADDR_N_O<0> BIST_ADDR_I<6> ++ BIST_ADDR_I<5> BIST_ADDR_I<4> BIST_ADDR_I<3> BIST_ADDR_I<2> BIST_ADDR_I<1> ++ BIST_ADDR_I<0> BIST_EN_I VDD VSS +XINV<6> q_int<6> qn_int<6> VDD VSS / RSC_IHPSG13_CINVX2 +XINV<5> q_int<5> qn_int<5> VDD VSS / RSC_IHPSG13_CINVX2 +XINV<4> q_int<4> qn_int<4> VDD VSS / RSC_IHPSG13_CINVX2 +XINV<3> q_int<3> qn_int<3> VDD VSS / RSC_IHPSG13_CINVX2 +XINV<2> q_int<2> qn_int<2> VDD VSS / RSC_IHPSG13_CINVX2 +XINV<1> q_int<1> qn_int<1> VDD VSS / RSC_IHPSG13_CINVX2 +XINV<0> q_int<0> qn_int<0> VDD VSS / RSC_IHPSG13_CINVX2 +XDRV<6> qn_int<6> ADDR_N_O<6> VDD VSS / RSC_IHPSG13_CINVX8 +XDRV<5> qn_int<5> ADDR_N_O<5> VDD VSS / RSC_IHPSG13_CINVX8 +XDRV<4> qn_int<4> ADDR_N_O<4> VDD VSS / RSC_IHPSG13_CINVX8 +XDRV<3> qn_int<3> ADDR_N_O<3> VDD VSS / RSC_IHPSG13_CINVX8 +XDRV<2> qn_int<2> ADDR_N_O<2> VDD VSS / RSC_IHPSG13_CINVX8 +XDRV<1> qn_int<1> ADDR_N_O<1> VDD VSS / RSC_IHPSG13_CINVX8 +XDRV<0> qn_int<0> ADDR_N_O<0> VDD VSS / RSC_IHPSG13_CINVX8 +XDFF<6> BIST_EN_I BIST_ADDR_I<6> ACLK_N_I ADDR_I<6> q_int<6> net2<0> VDD ++ VSS / RSC_IHPSG13_DFNQMX2IX1 +XDFF<5> BIST_EN_I BIST_ADDR_I<5> ACLK_N_I ADDR_I<5> q_int<5> net2<1> VDD ++ VSS / RSC_IHPSG13_DFNQMX2IX1 +XDFF<4> BIST_EN_I BIST_ADDR_I<4> ACLK_N_I ADDR_I<4> q_int<4> net2<2> VDD ++ VSS / RSC_IHPSG13_DFNQMX2IX1 +XDFF<3> BIST_EN_I BIST_ADDR_I<3> ACLK_N_I ADDR_I<3> q_int<3> net2<3> VDD ++ VSS / RSC_IHPSG13_DFNQMX2IX1 +XDFF<2> BIST_EN_I BIST_ADDR_I<2> ACLK_N_I ADDR_I<2> q_int<2> net2<4> VDD ++ VSS / RSC_IHPSG13_DFNQMX2IX1 +XDFF<1> BIST_EN_I BIST_ADDR_I<1> ACLK_N_I ADDR_I<1> q_int<1> net2<5> VDD ++ VSS / RSC_IHPSG13_DFNQMX2IX1 +XDFF<0> BIST_EN_I BIST_ADDR_I<0> ACLK_N_I ADDR_I<0> q_int<0> net2<6> VDD ++ VSS / RSC_IHPSG13_DFNQMX2IX1 +XI11<7> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI11<6> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI11<5> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI11<4> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI11<3> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI11<2> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI11<1> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI11<0> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI12<1> VDD VSS / RSC_IHPSG13_FILLCAP4 +XI12<0> VDD VSS / RSC_IHPSG13_FILLCAP4 +.ENDS + +.SUBCKT RM_IHPSG13_256x32_c2_2P_ROWDEC4 ADDR_N_I<3> ADDR_N_I<2> ADDR_N_I<1> ADDR_N_I<0> ++ CS_I ECLK_I WL_O<15> WL_O<14> WL_O<13> WL_O<12> WL_O<11> WL_O<10> WL_O<9> ++ WL_O<8> WL_O<7> WL_O<6> WL_O<5> WL_O<4> WL_O<3> WL_O<2> WL_O<1> WL_O<0> ++ VDD VSS +XL2<12> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<11> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<10> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<9> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<8> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<7> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<6> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<5> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<4> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<3> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<2> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<1> VDD VSS / RSC_IHPSG13_FILLCAP8 +XSEL ADDR_N_I<3> ADDR_N_I<2> ADDR_N_I<1> ADDR_N_I<0> CS_I ECLK_I ECLK_H<1> ++ ECLK_B<0> ECLK_B<1> WL_O<15> WL_O<14> WL_O<13> WL_O<12> WL_O<11> WL_O<10> ++ WL_O<9> WL_O<8> WL_O<7> WL_O<6> WL_O<5> WL_O<4> WL_O<3> WL_O<2> WL_O<1> ++ WL_O<0> VDD VSS / RM_IHPSG13_256x32_c2_2P_DEC04 +.ENDS +.SUBCKT RM_IHPSG13_256x32_c2_2P_ROWREG4 ACLK_N_I ADDR_I<3> ADDR_I<2> ADDR_I<1> ADDR_I<0> ++ ADDR_N_O<3> ADDR_N_O<2> ADDR_N_O<1> ADDR_N_O<0> BIST_ADDR_I<3> ++ BIST_ADDR_I<2> BIST_ADDR_I<1> BIST_ADDR_I<0> BIST_EN_I VDD VSS +XINV<3> q_int<3> qn_int<3> VDD VSS / RSC_IHPSG13_CINVX2 +XINV<2> q_int<2> qn_int<2> VDD VSS / RSC_IHPSG13_CINVX2 +XINV<1> q_int<1> qn_int<1> VDD VSS / RSC_IHPSG13_CINVX2 +XINV<0> q_int<0> qn_int<0> VDD VSS / RSC_IHPSG13_CINVX2 +XDRV<3> qn_int<3> ADDR_N_O<3> VDD VSS / RSC_IHPSG13_CINVX8 +XDRV<2> qn_int<2> ADDR_N_O<2> VDD VSS / RSC_IHPSG13_CINVX8 +XDRV<1> qn_int<1> ADDR_N_O<1> VDD VSS / RSC_IHPSG13_CINVX8 +XDRV<0> qn_int<0> ADDR_N_O<0> VDD VSS / RSC_IHPSG13_CINVX8 +XDFF<3> BIST_EN_I BIST_ADDR_I<3> ACLK_N_I ADDR_I<3> q_int<3> net7<0> VDD ++ VSS / RSC_IHPSG13_DFNQMX2IX1 +XDFF<2> BIST_EN_I BIST_ADDR_I<2> ACLK_N_I ADDR_I<2> q_int<2> net7<1> VDD ++ VSS / RSC_IHPSG13_DFNQMX2IX1 +XDFF<1> BIST_EN_I BIST_ADDR_I<1> ACLK_N_I ADDR_I<1> q_int<1> net7<2> VDD ++ VSS / RSC_IHPSG13_DFNQMX2IX1 +XDFF<0> BIST_EN_I BIST_ADDR_I<0> ACLK_N_I ADDR_I<0> q_int<0> net7<3> VDD ++ VSS / RSC_IHPSG13_DFNQMX2IX1 +XI11<20> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI11<19> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI11<18> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI11<17> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI11<16> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI11<15> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI11<14> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI11<13> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI11<12> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI11<11> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI11<10> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI11<9> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI11<8> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI11<7> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI11<6> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI11<5> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI11<4> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI11<3> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI11<2> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI11<1> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI12<4> VDD VSS / RSC_IHPSG13_FILLCAP4 +XI12<3> VDD VSS / RSC_IHPSG13_FILLCAP4 +XI12<2> VDD VSS / RSC_IHPSG13_FILLCAP4 +XI12<1> VDD VSS / RSC_IHPSG13_FILLCAP4 +XI12<0> VDD VSS / RSC_IHPSG13_FILLCAP4 +.ENDS + + +.SUBCKT RM_IHPSG13_256x32_c2_1P_BITKIT_TAP BLC BLT NW PW VDD VSS +.ENDS +.SUBCKT RM_IHPSG13_256x32_c2_1P_BITKIT_16x2_TAP A_BLC<1> A_BLC<0> A_BLT<1> A_BLT<0> ++ VDD_CORE VSS +XITAP<1> A_BLC<1> A_BLT<1> VDD_CORE VSS VDD_CORE VSS ++ / RM_IHPSG13_256x32_c2_1P_BITKIT_TAP +XITAP<0> A_BLC<0> A_BLT<0> VDD_CORE VSS VDD_CORE VSS ++ / RM_IHPSG13_256x32_c2_1P_BITKIT_TAP +XIEDGEBP_COL1<1> BLC<1> BLT<1> VDD_CORE VSS VDD_CORE ++ VSS / RM_IHPSG13_256x32_c2_1P_BITKIT_EDGE_TB +XIEDGEBP_COL1<0> BLC<1> BLT<1> VDD_CORE VSS VDD_CORE ++ VSS / RM_IHPSG13_256x32_c2_1P_BITKIT_EDGE_TB +XIEDGEBP_COL2<1> BLC<0> BLT<0> VDD_CORE VSS VDD_CORE ++ VSS / RM_IHPSG13_256x32_c2_1P_BITKIT_EDGE_TB +XIEDGEBP_COL2<0> BLC<0> BLT<0> VDD_CORE VSS VDD_CORE ++ VSS / RM_IHPSG13_256x32_c2_1P_BITKIT_EDGE_TB +.ENDS +.SUBCKT RM_IHPSG13_256x32_c2_1P_BITKIT_16x2_TAP_LR VDD_CORE VSS +XCORNER<1> VDD_CORE VSS VDD_CORE VSS / ++ RM_IHPSG13_256x32_c2_1P_BITKIT_CORNER +XCORNER<0> VDD_CORE VSS VDD_CORE VSS / ++ RM_IHPSG13_256x32_c2_1P_BITKIT_CORNER +XTAP_BORDER VDD_CORE VSS VDD_CORE VSS / ++ RM_IHPSG13_256x32_c2_1P_BITKIT_TAP_LR +.ENDS +.SUBCKT RM_IHPSG13_256x32_c2_1P_DEC03 ADDR<1> ADDR<0> CS CS_OUT VDD VSS +XDECINV net1 CS_OUT VDD VSS / RSC_IHPSG13_INVX4 +XI0 VDD VSS / RSC_IHPSG13_FILLCAP4 +XDEC ADDR<1> ADDR<0> CS net1 VDD VSS / RSC_IHPSG13_NAND3X2 +.ENDS +.SUBCKT RM_IHPSG13_256x32_c2_1P_DEC02 ADDR<1> ADDR<0> CS CS_OUT VDD VSS +XDECINV net1 CS_OUT VDD VSS / RSC_IHPSG13_INVX4 +XDEC ADDR<1> NADDR<0> CS net1 VDD VSS / RSC_IHPSG13_NAND3X2 +XI2 VDD VSS / RSC_IHPSG13_FILLCAP4 +XADDRINV ADDR<0> NADDR<0> VDD VSS / RSC_IHPSG13_INVX2 +.ENDS +.SUBCKT RM_IHPSG13_256x32_c2_1P_ROWDEC8 ADDR_N_I<7> ADDR_N_I<6> ADDR_N_I<5> ADDR_N_I<4> ++ ADDR_N_I<3> ADDR_N_I<2> ADDR_N_I<1> ADDR_N_I<0> CS_I ECLK_I WL_O<255> ++ WL_O<254> WL_O<253> WL_O<252> WL_O<251> WL_O<250> WL_O<249> WL_O<248> ++ WL_O<247> WL_O<246> WL_O<245> WL_O<244> WL_O<243> WL_O<242> WL_O<241> ++ WL_O<240> WL_O<239> WL_O<238> WL_O<237> WL_O<236> WL_O<235> WL_O<234> ++ WL_O<233> WL_O<232> WL_O<231> WL_O<230> WL_O<229> WL_O<228> WL_O<227> ++ WL_O<226> WL_O<225> WL_O<224> WL_O<223> WL_O<222> WL_O<221> WL_O<220> ++ WL_O<219> WL_O<218> WL_O<217> WL_O<216> WL_O<215> WL_O<214> WL_O<213> ++ WL_O<212> WL_O<211> WL_O<210> WL_O<209> WL_O<208> WL_O<207> WL_O<206> ++ WL_O<205> WL_O<204> WL_O<203> WL_O<202> WL_O<201> WL_O<200> WL_O<199> ++ WL_O<198> WL_O<197> WL_O<196> WL_O<195> WL_O<194> WL_O<193> WL_O<192> ++ WL_O<191> WL_O<190> WL_O<189> WL_O<188> WL_O<187> WL_O<186> WL_O<185> ++ WL_O<184> WL_O<183> WL_O<182> WL_O<181> WL_O<180> WL_O<179> WL_O<178> ++ WL_O<177> WL_O<176> WL_O<175> WL_O<174> WL_O<173> WL_O<172> WL_O<171> ++ WL_O<170> WL_O<169> WL_O<168> WL_O<167> WL_O<166> WL_O<165> WL_O<164> ++ WL_O<163> WL_O<162> WL_O<161> WL_O<160> WL_O<159> WL_O<158> WL_O<157> ++ WL_O<156> WL_O<155> WL_O<154> WL_O<153> WL_O<152> WL_O<151> WL_O<150> ++ WL_O<149> WL_O<148> WL_O<147> WL_O<146> WL_O<145> WL_O<144> WL_O<143> ++ WL_O<142> WL_O<141> WL_O<140> WL_O<139> WL_O<138> WL_O<137> WL_O<136> ++ WL_O<135> WL_O<134> WL_O<133> WL_O<132> WL_O<131> WL_O<130> WL_O<129> ++ WL_O<128> WL_O<127> WL_O<126> WL_O<125> WL_O<124> WL_O<123> WL_O<122> ++ WL_O<121> WL_O<120> WL_O<119> WL_O<118> WL_O<117> WL_O<116> WL_O<115> ++ WL_O<114> WL_O<113> WL_O<112> WL_O<111> WL_O<110> WL_O<109> WL_O<108> ++ WL_O<107> WL_O<106> WL_O<105> WL_O<104> WL_O<103> WL_O<102> WL_O<101> ++ WL_O<100> WL_O<99> WL_O<98> WL_O<97> WL_O<96> WL_O<95> WL_O<94> WL_O<93> ++ WL_O<92> WL_O<91> WL_O<90> WL_O<89> WL_O<88> WL_O<87> WL_O<86> WL_O<85> ++ WL_O<84> WL_O<83> WL_O<82> WL_O<81> WL_O<80> WL_O<79> WL_O<78> WL_O<77> ++ WL_O<76> WL_O<75> WL_O<74> WL_O<73> WL_O<72> WL_O<71> WL_O<70> WL_O<69> ++ WL_O<68> WL_O<67> WL_O<66> WL_O<65> WL_O<64> WL_O<63> WL_O<62> WL_O<61> ++ WL_O<60> WL_O<59> WL_O<58> WL_O<57> WL_O<56> WL_O<55> WL_O<54> WL_O<53> ++ WL_O<52> WL_O<51> WL_O<50> WL_O<49> WL_O<48> WL_O<47> WL_O<46> WL_O<45> ++ WL_O<44> WL_O<43> WL_O<42> WL_O<41> WL_O<40> WL_O<39> WL_O<38> WL_O<37> ++ WL_O<36> WL_O<35> WL_O<34> WL_O<33> WL_O<32> WL_O<31> WL_O<30> WL_O<29> ++ WL_O<28> WL_O<27> WL_O<26> WL_O<25> WL_O<24> WL_O<23> WL_O<22> WL_O<21> ++ WL_O<20> WL_O<19> WL_O<18> WL_O<17> WL_O<16> WL_O<15> WL_O<14> WL_O<13> ++ WL_O<12> WL_O<11> WL_O<10> WL_O<9> WL_O<8> WL_O<7> WL_O<6> WL_O<5> WL_O<4> ++ WL_O<3> WL_O<2> WL_O<1> WL_O<0> VDD VSS +XDEC11<4> ADDR_N_I<7> ADDR_N_I<6> CS_I CS04<3> VDD VSS / ++ RM_IHPSG13_256x32_c2_1P_DEC03 +XDEC11<3> ADDR_N_I<5> ADDR_N_I<4> CS04<3> CS00<15> VDD VSS / ++ RM_IHPSG13_256x32_c2_1P_DEC03 +XDEC11<2> ADDR_N_I<5> ADDR_N_I<4> CS04<2> CS00<11> VDD VSS / ++ RM_IHPSG13_256x32_c2_1P_DEC03 +XDEC11<1> ADDR_N_I<5> ADDR_N_I<4> CS04<1> CS00<7> VDD VSS / ++ RM_IHPSG13_256x32_c2_1P_DEC03 +XDEC11<0> ADDR_N_I<5> ADDR_N_I<4> CS04<0> CS00<3> VDD VSS / ++ RM_IHPSG13_256x32_c2_1P_DEC03 +XL2<88> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<87> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<86> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<85> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<84> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<83> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<82> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<81> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<80> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<79> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<78> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<77> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<76> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<75> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<74> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<73> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<72> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<71> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<70> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<69> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<68> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<67> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<66> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<65> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<64> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<63> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<62> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<61> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<60> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<59> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<58> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<57> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<56> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<55> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<54> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<53> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<52> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<51> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<50> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<49> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<48> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<47> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<46> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<45> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<44> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<43> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<42> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<41> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<40> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<39> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<38> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<37> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<36> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<35> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<34> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<33> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<32> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<31> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<30> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<29> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<28> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<27> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<26> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<25> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<24> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<23> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<22> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<21> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<20> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<19> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<18> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<17> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<16> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<15> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<14> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<13> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<12> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<11> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<10> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<9> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<8> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<7> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<6> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<5> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<4> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<3> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<2> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<1> VDD VSS / RSC_IHPSG13_FILLCAP8 +XDEC10<4> ADDR_N_I<7> ADDR_N_I<6> CS_I CS04<2> VDD VSS / ++ RM_IHPSG13_256x32_c2_1P_DEC02 +XDEC10<3> ADDR_N_I<5> ADDR_N_I<4> CS04<3> CS00<14> VDD VSS / ++ RM_IHPSG13_256x32_c2_1P_DEC02 +XDEC10<2> ADDR_N_I<5> ADDR_N_I<4> CS04<2> CS00<10> VDD VSS / ++ RM_IHPSG13_256x32_c2_1P_DEC02 +XDEC10<1> ADDR_N_I<5> ADDR_N_I<4> CS04<1> CS00<6> VDD VSS / ++ RM_IHPSG13_256x32_c2_1P_DEC02 +XDEC10<0> ADDR_N_I<5> ADDR_N_I<4> CS04<0> CS00<2> VDD VSS / ++ RM_IHPSG13_256x32_c2_1P_DEC02 +XDEC00<4> ADDR_N_I<7> ADDR_N_I<6> CS_I CS04<0> VDD VSS / ++ RM_IHPSG13_256x32_c2_1P_DEC00 +XDEC00<3> ADDR_N_I<5> ADDR_N_I<4> CS04<3> CS00<12> VDD VSS / ++ RM_IHPSG13_256x32_c2_1P_DEC00 +XDEC00<2> ADDR_N_I<5> ADDR_N_I<4> CS04<2> CS00<8> VDD VSS / ++ RM_IHPSG13_256x32_c2_1P_DEC00 +XDEC00<1> ADDR_N_I<5> ADDR_N_I<4> CS04<1> CS00<4> VDD VSS / ++ RM_IHPSG13_256x32_c2_1P_DEC00 +XDEC00<0> ADDR_N_I<5> ADDR_N_I<4> CS04<0> CS00<0> VDD VSS / ++ RM_IHPSG13_256x32_c2_1P_DEC00 +XSEL<15> ADDR_N_I<3> ADDR_N_I<2> ADDR_N_I<1> ADDR_N_I<0> CS00<15> ECLK_H<15> ++ ECLK_H<16> ECLK_B<15> ECLK_B<16> WL_O<255> WL_O<254> WL_O<253> WL_O<252> ++ WL_O<251> WL_O<250> WL_O<249> WL_O<248> WL_O<247> WL_O<246> WL_O<245> ++ WL_O<244> WL_O<243> WL_O<242> WL_O<241> WL_O<240> VDD VSS / ++ RM_IHPSG13_256x32_c2_1P_DEC04 +XSEL<14> ADDR_N_I<3> ADDR_N_I<2> ADDR_N_I<1> ADDR_N_I<0> CS00<14> ECLK_H<14> ++ ECLK_H<15> ECLK_B<14> ECLK_B<15> WL_O<239> WL_O<238> WL_O<237> WL_O<236> ++ WL_O<235> WL_O<234> WL_O<233> WL_O<232> WL_O<231> WL_O<230> WL_O<229> ++ WL_O<228> WL_O<227> WL_O<226> WL_O<225> WL_O<224> VDD VSS / ++ RM_IHPSG13_256x32_c2_1P_DEC04 +XSEL<13> ADDR_N_I<3> ADDR_N_I<2> ADDR_N_I<1> ADDR_N_I<0> CS00<13> ECLK_H<13> ++ ECLK_H<14> ECLK_B<13> ECLK_B<14> WL_O<223> WL_O<222> WL_O<221> WL_O<220> ++ WL_O<219> WL_O<218> WL_O<217> WL_O<216> WL_O<215> WL_O<214> WL_O<213> ++ WL_O<212> WL_O<211> WL_O<210> WL_O<209> WL_O<208> VDD VSS / ++ RM_IHPSG13_256x32_c2_1P_DEC04 +XSEL<12> ADDR_N_I<3> ADDR_N_I<2> ADDR_N_I<1> ADDR_N_I<0> CS00<12> ECLK_H<12> ++ ECLK_H<13> ECLK_B<12> ECLK_B<13> WL_O<207> WL_O<206> WL_O<205> WL_O<204> ++ WL_O<203> WL_O<202> WL_O<201> WL_O<200> WL_O<199> WL_O<198> WL_O<197> ++ WL_O<196> WL_O<195> WL_O<194> WL_O<193> WL_O<192> VDD VSS / ++ RM_IHPSG13_256x32_c2_1P_DEC04 +XSEL<11> ADDR_N_I<3> ADDR_N_I<2> ADDR_N_I<1> ADDR_N_I<0> CS00<11> ECLK_H<11> ++ ECLK_H<12> ECLK_B<11> ECLK_B<12> WL_O<191> WL_O<190> WL_O<189> WL_O<188> ++ WL_O<187> WL_O<186> WL_O<185> WL_O<184> WL_O<183> WL_O<182> WL_O<181> ++ WL_O<180> WL_O<179> WL_O<178> WL_O<177> WL_O<176> VDD VSS / ++ RM_IHPSG13_256x32_c2_1P_DEC04 +XSEL<10> ADDR_N_I<3> ADDR_N_I<2> ADDR_N_I<1> ADDR_N_I<0> CS00<10> ECLK_H<10> ++ ECLK_H<11> ECLK_B<10> ECLK_B<11> WL_O<175> WL_O<174> WL_O<173> WL_O<172> ++ WL_O<171> WL_O<170> WL_O<169> WL_O<168> WL_O<167> WL_O<166> WL_O<165> ++ WL_O<164> WL_O<163> WL_O<162> WL_O<161> WL_O<160> VDD VSS / ++ RM_IHPSG13_256x32_c2_1P_DEC04 +XSEL<9> ADDR_N_I<3> ADDR_N_I<2> ADDR_N_I<1> ADDR_N_I<0> CS00<9> ECLK_H<9> ++ ECLK_H<10> ECLK_B<9> ECLK_B<10> WL_O<159> WL_O<158> WL_O<157> WL_O<156> ++ WL_O<155> WL_O<154> WL_O<153> WL_O<152> WL_O<151> WL_O<150> WL_O<149> ++ WL_O<148> WL_O<147> WL_O<146> WL_O<145> WL_O<144> VDD VSS / ++ RM_IHPSG13_256x32_c2_1P_DEC04 +XSEL<8> ADDR_N_I<3> ADDR_N_I<2> ADDR_N_I<1> ADDR_N_I<0> CS00<8> ECLK_H<8> ++ ECLK_H<9> ECLK_B<8> ECLK_B<9> WL_O<143> WL_O<142> WL_O<141> WL_O<140> ++ WL_O<139> WL_O<138> WL_O<137> WL_O<136> WL_O<135> WL_O<134> WL_O<133> ++ WL_O<132> WL_O<131> WL_O<130> WL_O<129> WL_O<128> VDD VSS / ++ RM_IHPSG13_256x32_c2_1P_DEC04 +XSEL<7> ADDR_N_I<3> ADDR_N_I<2> ADDR_N_I<1> ADDR_N_I<0> CS00<7> ECLK_H<7> ++ ECLK_H<8> ECLK_B<7> ECLK_B<8> WL_O<127> WL_O<126> WL_O<125> WL_O<124> ++ WL_O<123> WL_O<122> WL_O<121> WL_O<120> WL_O<119> WL_O<118> WL_O<117> ++ WL_O<116> WL_O<115> WL_O<114> WL_O<113> WL_O<112> VDD VSS / ++ RM_IHPSG13_256x32_c2_1P_DEC04 +XSEL<6> ADDR_N_I<3> ADDR_N_I<2> ADDR_N_I<1> ADDR_N_I<0> CS00<6> ECLK_H<6> ++ ECLK_H<7> ECLK_B<6> ECLK_B<7> WL_O<111> WL_O<110> WL_O<109> WL_O<108> ++ WL_O<107> WL_O<106> WL_O<105> WL_O<104> WL_O<103> WL_O<102> WL_O<101> ++ WL_O<100> WL_O<99> WL_O<98> WL_O<97> WL_O<96> VDD VSS / ++ RM_IHPSG13_256x32_c2_1P_DEC04 +XSEL<5> ADDR_N_I<3> ADDR_N_I<2> ADDR_N_I<1> ADDR_N_I<0> CS00<5> ECLK_H<5> ++ ECLK_H<6> ECLK_B<5> ECLK_B<6> WL_O<95> WL_O<94> WL_O<93> WL_O<92> WL_O<91> ++ WL_O<90> WL_O<89> WL_O<88> WL_O<87> WL_O<86> WL_O<85> WL_O<84> WL_O<83> ++ WL_O<82> WL_O<81> WL_O<80> VDD VSS / RM_IHPSG13_256x32_c2_1P_DEC04 +XSEL<4> ADDR_N_I<3> ADDR_N_I<2> ADDR_N_I<1> ADDR_N_I<0> CS00<4> ECLK_H<4> ++ ECLK_H<5> ECLK_B<4> ECLK_B<5> WL_O<79> WL_O<78> WL_O<77> WL_O<76> WL_O<75> ++ WL_O<74> WL_O<73> WL_O<72> WL_O<71> WL_O<70> WL_O<69> WL_O<68> WL_O<67> ++ WL_O<66> WL_O<65> WL_O<64> VDD VSS / RM_IHPSG13_256x32_c2_1P_DEC04 +XSEL<3> ADDR_N_I<3> ADDR_N_I<2> ADDR_N_I<1> ADDR_N_I<0> CS00<3> ECLK_H<3> ++ ECLK_H<4> ECLK_B<3> ECLK_B<4> WL_O<63> WL_O<62> WL_O<61> WL_O<60> WL_O<59> ++ WL_O<58> WL_O<57> WL_O<56> WL_O<55> WL_O<54> WL_O<53> WL_O<52> WL_O<51> ++ WL_O<50> WL_O<49> WL_O<48> VDD VSS / RM_IHPSG13_256x32_c2_1P_DEC04 +XSEL<2> ADDR_N_I<3> ADDR_N_I<2> ADDR_N_I<1> ADDR_N_I<0> CS00<2> ECLK_H<2> ++ ECLK_H<3> ECLK_B<2> ECLK_B<3> WL_O<47> WL_O<46> WL_O<45> WL_O<44> WL_O<43> ++ WL_O<42> WL_O<41> WL_O<40> WL_O<39> WL_O<38> WL_O<37> WL_O<36> WL_O<35> ++ WL_O<34> WL_O<33> WL_O<32> VDD VSS / RM_IHPSG13_256x32_c2_1P_DEC04 +XSEL<1> ADDR_N_I<3> ADDR_N_I<2> ADDR_N_I<1> ADDR_N_I<0> CS00<1> ECLK_H<1> ++ ECLK_H<2> ECLK_B<1> ECLK_B<2> WL_O<31> WL_O<30> WL_O<29> WL_O<28> WL_O<27> ++ WL_O<26> WL_O<25> WL_O<24> WL_O<23> WL_O<22> WL_O<21> WL_O<20> WL_O<19> ++ WL_O<18> WL_O<17> WL_O<16> VDD VSS / RM_IHPSG13_256x32_c2_1P_DEC04 +XSEL<0> ADDR_N_I<3> ADDR_N_I<2> ADDR_N_I<1> ADDR_N_I<0> CS00<0> ECLK_I ++ ECLK_H<1> ECLK_B<0> ECLK_B<1> WL_O<15> WL_O<14> WL_O<13> WL_O<12> WL_O<11> ++ WL_O<10> WL_O<9> WL_O<8> WL_O<7> WL_O<6> WL_O<5> WL_O<4> WL_O<3> WL_O<2> ++ WL_O<1> WL_O<0> VDD VSS / RM_IHPSG13_256x32_c2_1P_DEC04 +XDEC01<4> ADDR_N_I<7> ADDR_N_I<6> CS_I CS04<1> VDD VSS / ++ RM_IHPSG13_256x32_c2_1P_DEC01 +XDEC01<3> ADDR_N_I<5> ADDR_N_I<4> CS04<3> CS00<13> VDD VSS / ++ RM_IHPSG13_256x32_c2_1P_DEC01 +XDEC01<2> ADDR_N_I<5> ADDR_N_I<4> CS04<2> CS00<9> VDD VSS / ++ RM_IHPSG13_256x32_c2_1P_DEC01 +XDEC01<1> ADDR_N_I<5> ADDR_N_I<4> CS04<1> CS00<5> VDD VSS / ++ RM_IHPSG13_256x32_c2_1P_DEC01 +XDEC01<0> ADDR_N_I<5> ADDR_N_I<4> CS04<0> CS00<1> VDD VSS / ++ RM_IHPSG13_256x32_c2_1P_DEC01 +.ENDS +.SUBCKT RM_IHPSG13_256x32_c2_1P_ROWREG8 ACLK_N_I ADDR_I<7> ADDR_I<6> ADDR_I<5> ADDR_I<4> ++ ADDR_I<3> ADDR_I<2> ADDR_I<1> ADDR_I<0> ADDR_N_O<7> ADDR_N_O<6> ADDR_N_O<5> ++ ADDR_N_O<4> ADDR_N_O<3> ADDR_N_O<2> ADDR_N_O<1> ADDR_N_O<0> BIST_ADDR_I<7> ++ BIST_ADDR_I<6> BIST_ADDR_I<5> BIST_ADDR_I<4> BIST_ADDR_I<3> BIST_ADDR_I<2> ++ BIST_ADDR_I<1> BIST_ADDR_I<0> BIST_EN_I VDD VSS +XINV<7> q_int<7> qn_int<7> VDD VSS / RSC_IHPSG13_CINVX2 +XINV<6> q_int<6> qn_int<6> VDD VSS / RSC_IHPSG13_CINVX2 +XINV<5> q_int<5> qn_int<5> VDD VSS / RSC_IHPSG13_CINVX2 +XINV<4> q_int<4> qn_int<4> VDD VSS / RSC_IHPSG13_CINVX2 +XINV<3> q_int<3> qn_int<3> VDD VSS / RSC_IHPSG13_CINVX2 +XINV<2> q_int<2> qn_int<2> VDD VSS / RSC_IHPSG13_CINVX2 +XINV<1> q_int<1> qn_int<1> VDD VSS / RSC_IHPSG13_CINVX2 +XINV<0> q_int<0> qn_int<0> VDD VSS / RSC_IHPSG13_CINVX2 +XDRV<7> qn_int<7> ADDR_N_O<7> VDD VSS / RSC_IHPSG13_CINVX8 +XDRV<6> qn_int<6> ADDR_N_O<6> VDD VSS / RSC_IHPSG13_CINVX8 +XDRV<5> qn_int<5> ADDR_N_O<5> VDD VSS / RSC_IHPSG13_CINVX8 +XDRV<4> qn_int<4> ADDR_N_O<4> VDD VSS / RSC_IHPSG13_CINVX8 +XDRV<3> qn_int<3> ADDR_N_O<3> VDD VSS / RSC_IHPSG13_CINVX8 +XDRV<2> qn_int<2> ADDR_N_O<2> VDD VSS / RSC_IHPSG13_CINVX8 +XDRV<1> qn_int<1> ADDR_N_O<1> VDD VSS / RSC_IHPSG13_CINVX8 +XDRV<0> qn_int<0> ADDR_N_O<0> VDD VSS / RSC_IHPSG13_CINVX8 +XDFF<7> BIST_EN_I BIST_ADDR_I<7> ACLK_N_I ADDR_I<7> q_int<7> net2<0> VDD ++ VSS / RSC_IHPSG13_DFNQMX2IX1 +XDFF<6> BIST_EN_I BIST_ADDR_I<6> ACLK_N_I ADDR_I<6> q_int<6> net2<1> VDD ++ VSS / RSC_IHPSG13_DFNQMX2IX1 +XDFF<5> BIST_EN_I BIST_ADDR_I<5> ACLK_N_I ADDR_I<5> q_int<5> net2<2> VDD ++ VSS / RSC_IHPSG13_DFNQMX2IX1 +XDFF<4> BIST_EN_I BIST_ADDR_I<4> ACLK_N_I ADDR_I<4> q_int<4> net2<3> VDD ++ VSS / RSC_IHPSG13_DFNQMX2IX1 +XDFF<3> BIST_EN_I BIST_ADDR_I<3> ACLK_N_I ADDR_I<3> q_int<3> net2<4> VDD ++ VSS / RSC_IHPSG13_DFNQMX2IX1 +XDFF<2> BIST_EN_I BIST_ADDR_I<2> ACLK_N_I ADDR_I<2> q_int<2> net2<5> VDD ++ VSS / RSC_IHPSG13_DFNQMX2IX1 +XDFF<1> BIST_EN_I BIST_ADDR_I<1> ACLK_N_I ADDR_I<1> q_int<1> net2<6> VDD ++ VSS / RSC_IHPSG13_DFNQMX2IX1 +XDFF<0> BIST_EN_I BIST_ADDR_I<0> ACLK_N_I ADDR_I<0> q_int<0> net2<7> VDD ++ VSS / RSC_IHPSG13_DFNQMX2IX1 +XI11<4> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI11<3> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI11<2> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI11<1> VDD VSS / RSC_IHPSG13_FILLCAP8 +.ENDS + +.SUBCKT RM_IHPSG13_256x32_c2_1P_ROWDEC9 ADDR_N_I<8> ADDR_N_I<7> ADDR_N_I<6> ADDR_N_I<5> ++ ADDR_N_I<4> ADDR_N_I<3> ADDR_N_I<2> ADDR_N_I<1> ADDR_N_I<0> CS_I ECLK_I ++ WL_O<511> WL_O<510> WL_O<509> WL_O<508> WL_O<507> WL_O<506> WL_O<505> ++ WL_O<504> WL_O<503> WL_O<502> WL_O<501> WL_O<500> WL_O<499> WL_O<498> ++ WL_O<497> WL_O<496> WL_O<495> WL_O<494> WL_O<493> WL_O<492> WL_O<491> ++ WL_O<490> WL_O<489> WL_O<488> WL_O<487> WL_O<486> WL_O<485> WL_O<484> ++ WL_O<483> WL_O<482> WL_O<481> WL_O<480> WL_O<479> WL_O<478> WL_O<477> ++ WL_O<476> WL_O<475> WL_O<474> WL_O<473> WL_O<472> WL_O<471> WL_O<470> ++ WL_O<469> WL_O<468> WL_O<467> WL_O<466> WL_O<465> WL_O<464> WL_O<463> ++ WL_O<462> WL_O<461> WL_O<460> WL_O<459> WL_O<458> WL_O<457> WL_O<456> ++ WL_O<455> WL_O<454> WL_O<453> WL_O<452> WL_O<451> WL_O<450> WL_O<449> ++ WL_O<448> WL_O<447> WL_O<446> WL_O<445> WL_O<444> WL_O<443> WL_O<442> ++ WL_O<441> WL_O<440> WL_O<439> WL_O<438> WL_O<437> WL_O<436> WL_O<435> ++ WL_O<434> WL_O<433> WL_O<432> WL_O<431> WL_O<430> WL_O<429> WL_O<428> ++ WL_O<427> WL_O<426> WL_O<425> WL_O<424> WL_O<423> WL_O<422> WL_O<421> ++ WL_O<420> WL_O<419> WL_O<418> WL_O<417> WL_O<416> WL_O<415> WL_O<414> ++ WL_O<413> WL_O<412> WL_O<411> WL_O<410> WL_O<409> WL_O<408> WL_O<407> ++ WL_O<406> WL_O<405> WL_O<404> WL_O<403> WL_O<402> WL_O<401> WL_O<400> ++ WL_O<399> WL_O<398> WL_O<397> WL_O<396> WL_O<395> WL_O<394> WL_O<393> ++ WL_O<392> WL_O<391> WL_O<390> WL_O<389> WL_O<388> WL_O<387> WL_O<386> ++ WL_O<385> WL_O<384> WL_O<383> WL_O<382> WL_O<381> WL_O<380> WL_O<379> ++ WL_O<378> WL_O<377> WL_O<376> WL_O<375> WL_O<374> WL_O<373> WL_O<372> ++ WL_O<371> WL_O<370> WL_O<369> WL_O<368> WL_O<367> WL_O<366> WL_O<365> ++ WL_O<364> WL_O<363> WL_O<362> WL_O<361> WL_O<360> WL_O<359> WL_O<358> ++ WL_O<357> WL_O<356> WL_O<355> WL_O<354> WL_O<353> WL_O<352> WL_O<351> ++ WL_O<350> WL_O<349> WL_O<348> WL_O<347> WL_O<346> WL_O<345> WL_O<344> ++ WL_O<343> WL_O<342> WL_O<341> WL_O<340> WL_O<339> WL_O<338> WL_O<337> ++ WL_O<336> WL_O<335> WL_O<334> WL_O<333> WL_O<332> WL_O<331> WL_O<330> ++ WL_O<329> WL_O<328> WL_O<327> WL_O<326> WL_O<325> WL_O<324> WL_O<323> ++ WL_O<322> WL_O<321> WL_O<320> WL_O<319> WL_O<318> WL_O<317> WL_O<316> ++ WL_O<315> WL_O<314> WL_O<313> WL_O<312> WL_O<311> WL_O<310> WL_O<309> ++ WL_O<308> WL_O<307> WL_O<306> WL_O<305> WL_O<304> WL_O<303> WL_O<302> ++ WL_O<301> WL_O<300> WL_O<299> WL_O<298> WL_O<297> WL_O<296> WL_O<295> ++ WL_O<294> WL_O<293> WL_O<292> WL_O<291> WL_O<290> WL_O<289> WL_O<288> ++ WL_O<287> WL_O<286> WL_O<285> WL_O<284> WL_O<283> WL_O<282> WL_O<281> ++ WL_O<280> WL_O<279> WL_O<278> WL_O<277> WL_O<276> WL_O<275> WL_O<274> ++ WL_O<273> WL_O<272> WL_O<271> WL_O<270> WL_O<269> WL_O<268> WL_O<267> ++ WL_O<266> WL_O<265> WL_O<264> WL_O<263> WL_O<262> WL_O<261> WL_O<260> ++ WL_O<259> WL_O<258> WL_O<257> WL_O<256> WL_O<255> WL_O<254> WL_O<253> ++ WL_O<252> WL_O<251> WL_O<250> WL_O<249> WL_O<248> WL_O<247> WL_O<246> ++ WL_O<245> WL_O<244> WL_O<243> WL_O<242> WL_O<241> WL_O<240> WL_O<239> ++ WL_O<238> WL_O<237> WL_O<236> WL_O<235> WL_O<234> WL_O<233> WL_O<232> ++ WL_O<231> WL_O<230> WL_O<229> WL_O<228> WL_O<227> WL_O<226> WL_O<225> ++ WL_O<224> WL_O<223> WL_O<222> WL_O<221> WL_O<220> WL_O<219> WL_O<218> ++ WL_O<217> WL_O<216> WL_O<215> WL_O<214> WL_O<213> WL_O<212> WL_O<211> ++ WL_O<210> WL_O<209> WL_O<208> WL_O<207> WL_O<206> WL_O<205> WL_O<204> ++ WL_O<203> WL_O<202> WL_O<201> WL_O<200> WL_O<199> WL_O<198> WL_O<197> ++ WL_O<196> WL_O<195> WL_O<194> WL_O<193> WL_O<192> WL_O<191> WL_O<190> ++ WL_O<189> WL_O<188> WL_O<187> WL_O<186> WL_O<185> WL_O<184> WL_O<183> ++ WL_O<182> WL_O<181> WL_O<180> WL_O<179> WL_O<178> WL_O<177> WL_O<176> ++ WL_O<175> WL_O<174> WL_O<173> WL_O<172> WL_O<171> WL_O<170> WL_O<169> ++ WL_O<168> WL_O<167> WL_O<166> WL_O<165> WL_O<164> WL_O<163> WL_O<162> ++ WL_O<161> WL_O<160> WL_O<159> WL_O<158> WL_O<157> WL_O<156> WL_O<155> ++ WL_O<154> WL_O<153> WL_O<152> WL_O<151> WL_O<150> WL_O<149> WL_O<148> ++ WL_O<147> WL_O<146> WL_O<145> WL_O<144> WL_O<143> WL_O<142> WL_O<141> ++ WL_O<140> WL_O<139> WL_O<138> WL_O<137> WL_O<136> WL_O<135> WL_O<134> ++ WL_O<133> WL_O<132> WL_O<131> WL_O<130> WL_O<129> WL_O<128> WL_O<127> ++ WL_O<126> WL_O<125> WL_O<124> WL_O<123> WL_O<122> WL_O<121> WL_O<120> ++ WL_O<119> WL_O<118> WL_O<117> WL_O<116> WL_O<115> WL_O<114> WL_O<113> ++ WL_O<112> WL_O<111> WL_O<110> WL_O<109> WL_O<108> WL_O<107> WL_O<106> ++ WL_O<105> WL_O<104> WL_O<103> WL_O<102> WL_O<101> WL_O<100> WL_O<99> ++ WL_O<98> WL_O<97> WL_O<96> WL_O<95> WL_O<94> WL_O<93> WL_O<92> WL_O<91> ++ WL_O<90> WL_O<89> WL_O<88> WL_O<87> WL_O<86> WL_O<85> WL_O<84> WL_O<83> ++ WL_O<82> WL_O<81> WL_O<80> WL_O<79> WL_O<78> WL_O<77> WL_O<76> WL_O<75> ++ WL_O<74> WL_O<73> WL_O<72> WL_O<71> WL_O<70> WL_O<69> WL_O<68> WL_O<67> ++ WL_O<66> WL_O<65> WL_O<64> WL_O<63> WL_O<62> WL_O<61> WL_O<60> WL_O<59> ++ WL_O<58> WL_O<57> WL_O<56> WL_O<55> WL_O<54> WL_O<53> WL_O<52> WL_O<51> ++ WL_O<50> WL_O<49> WL_O<48> WL_O<47> WL_O<46> WL_O<45> WL_O<44> WL_O<43> ++ WL_O<42> WL_O<41> WL_O<40> WL_O<39> WL_O<38> WL_O<37> WL_O<36> WL_O<35> ++ WL_O<34> WL_O<33> WL_O<32> WL_O<31> WL_O<30> WL_O<29> WL_O<28> WL_O<27> ++ WL_O<26> WL_O<25> WL_O<24> WL_O<23> WL_O<22> WL_O<21> WL_O<20> WL_O<19> ++ WL_O<18> WL_O<17> WL_O<16> WL_O<15> WL_O<14> WL_O<13> WL_O<12> WL_O<11> ++ WL_O<10> WL_O<9> WL_O<8> WL_O<7> WL_O<6> WL_O<5> WL_O<4> WL_O<3> WL_O<2> ++ WL_O<1> WL_O<0> VDD VSS +XL2<172> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<171> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<170> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<169> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<168> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<167> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<166> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<165> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<164> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<163> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<162> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<161> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<160> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<159> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<158> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<157> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<156> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<155> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<154> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<153> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<152> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<151> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<150> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<149> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<148> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<147> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<146> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<145> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<144> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<143> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<142> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<141> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<140> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<139> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<138> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<137> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<136> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<135> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<134> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<133> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<132> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<131> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<130> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<129> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<128> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<127> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<126> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<125> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<124> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<123> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<122> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<121> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<120> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<119> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<118> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<117> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<116> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<115> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<114> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<113> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<112> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<111> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<110> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<109> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<108> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<107> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<106> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<105> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<104> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<103> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<102> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<101> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<100> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<99> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<98> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<97> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<96> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<95> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<94> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<93> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<92> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<91> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<90> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<89> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<88> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<87> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<86> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<85> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<84> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<83> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<82> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<81> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<80> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<79> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<78> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<77> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<76> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<75> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<74> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<73> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<72> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<71> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<70> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<69> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<68> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<67> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<66> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<65> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<64> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<63> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<62> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<61> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<60> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<59> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<58> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<57> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<56> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<55> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<54> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<53> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<52> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<51> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<50> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<49> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<48> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<47> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<46> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<45> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<44> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<43> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<42> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<41> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<40> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<39> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<38> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<37> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<36> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<35> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<34> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<33> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<32> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<31> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<30> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<29> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<28> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<27> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<26> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<25> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<24> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<23> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<22> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<21> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<20> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<19> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<18> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<17> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<16> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<15> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<14> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<13> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<12> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<11> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<10> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<9> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<8> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<7> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<6> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<5> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<4> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<3> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<2> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<1> VDD VSS / RSC_IHPSG13_FILLCAP8 +XDEC11<9> ADDR_N_I<7> ADDR_N_I<6> CS04<1> CS02<7> VDD VSS / ++ RM_IHPSG13_256x32_c2_1P_DEC03 +XDEC11<8> ADDR_N_I<7> ADDR_N_I<6> CS04<0> CS02<3> VDD VSS / ++ RM_IHPSG13_256x32_c2_1P_DEC03 +XDEC11<7> ADDR_N_I<5> ADDR_N_I<4> CS02<7> CS00<31> VDD VSS / ++ RM_IHPSG13_256x32_c2_1P_DEC03 +XDEC11<6> ADDR_N_I<5> ADDR_N_I<4> CS02<6> CS00<27> VDD VSS / ++ RM_IHPSG13_256x32_c2_1P_DEC03 +XDEC11<5> ADDR_N_I<5> ADDR_N_I<4> CS02<5> CS00<23> VDD VSS / ++ RM_IHPSG13_256x32_c2_1P_DEC03 +XDEC11<4> ADDR_N_I<5> ADDR_N_I<4> CS02<4> CS00<19> VDD VSS / ++ RM_IHPSG13_256x32_c2_1P_DEC03 +XDEC11<3> ADDR_N_I<5> ADDR_N_I<4> CS02<3> CS00<15> VDD VSS / ++ RM_IHPSG13_256x32_c2_1P_DEC03 +XDEC11<2> ADDR_N_I<5> ADDR_N_I<4> CS02<2> CS00<11> VDD VSS / ++ RM_IHPSG13_256x32_c2_1P_DEC03 +XDEC11<1> ADDR_N_I<5> ADDR_N_I<4> CS02<1> CS00<7> VDD VSS / ++ RM_IHPSG13_256x32_c2_1P_DEC03 +XDEC11<0> ADDR_N_I<5> ADDR_N_I<4> CS02<0> CS00<3> VDD VSS / ++ RM_IHPSG13_256x32_c2_1P_DEC03 +XDEC00<10> ADDR_N_I<9> ADDR_N_I<8> CS_I CS04<0> VDD VSS / ++ RM_IHPSG13_256x32_c2_1P_DEC00 +XDEC00<9> ADDR_N_I<7> ADDR_N_I<6> CS04<1> CS02<4> VDD VSS / ++ RM_IHPSG13_256x32_c2_1P_DEC00 +XDEC00<8> ADDR_N_I<7> ADDR_N_I<6> CS04<0> CS02<0> VDD VSS / ++ RM_IHPSG13_256x32_c2_1P_DEC00 +XDEC00<7> ADDR_N_I<5> ADDR_N_I<4> CS02<7> CS00<28> VDD VSS / ++ RM_IHPSG13_256x32_c2_1P_DEC00 +XDEC00<6> ADDR_N_I<5> ADDR_N_I<4> CS02<6> CS00<24> VDD VSS / ++ RM_IHPSG13_256x32_c2_1P_DEC00 +XDEC00<5> ADDR_N_I<5> ADDR_N_I<4> CS02<5> CS00<20> VDD VSS / ++ RM_IHPSG13_256x32_c2_1P_DEC00 +XDEC00<4> ADDR_N_I<5> ADDR_N_I<4> CS02<4> CS00<16> VDD VSS / ++ RM_IHPSG13_256x32_c2_1P_DEC00 +XDEC00<3> ADDR_N_I<5> ADDR_N_I<4> CS02<3> CS00<12> VDD VSS / ++ RM_IHPSG13_256x32_c2_1P_DEC00 +XDEC00<2> ADDR_N_I<5> ADDR_N_I<4> CS02<2> CS00<8> VDD VSS / ++ RM_IHPSG13_256x32_c2_1P_DEC00 +XDEC00<1> ADDR_N_I<5> ADDR_N_I<4> CS02<1> CS00<4> VDD VSS / ++ RM_IHPSG13_256x32_c2_1P_DEC00 +XDEC00<0> ADDR_N_I<5> ADDR_N_I<4> CS02<0> CS00<0> VDD VSS / ++ RM_IHPSG13_256x32_c2_1P_DEC00 +XSEL<31> ADDR_N_I<3> ADDR_N_I<2> ADDR_N_I<1> ADDR_N_I<0> CS00<31> ECLK_H<31> ++ ECLK_H<32> ECLK_B<31> ECLK_B<32> WL_O<511> WL_O<510> WL_O<509> WL_O<508> ++ WL_O<507> WL_O<506> WL_O<505> WL_O<504> WL_O<503> WL_O<502> WL_O<501> ++ WL_O<500> WL_O<499> WL_O<498> WL_O<497> WL_O<496> VDD VSS / ++ RM_IHPSG13_256x32_c2_1P_DEC04 +XSEL<30> ADDR_N_I<3> ADDR_N_I<2> ADDR_N_I<1> ADDR_N_I<0> CS00<30> ECLK_H<30> ++ ECLK_H<31> ECLK_B<30> ECLK_B<31> WL_O<495> WL_O<494> WL_O<493> WL_O<492> ++ WL_O<491> WL_O<490> WL_O<489> WL_O<488> WL_O<487> WL_O<486> WL_O<485> ++ WL_O<484> WL_O<483> WL_O<482> WL_O<481> WL_O<480> VDD VSS / ++ RM_IHPSG13_256x32_c2_1P_DEC04 +XSEL<29> ADDR_N_I<3> ADDR_N_I<2> ADDR_N_I<1> ADDR_N_I<0> CS00<29> ECLK_H<29> ++ ECLK_H<30> ECLK_B<29> ECLK_B<30> WL_O<479> WL_O<478> WL_O<477> WL_O<476> ++ WL_O<475> WL_O<474> WL_O<473> WL_O<472> WL_O<471> WL_O<470> WL_O<469> ++ WL_O<468> WL_O<467> WL_O<466> WL_O<465> WL_O<464> VDD VSS / ++ RM_IHPSG13_256x32_c2_1P_DEC04 +XSEL<28> ADDR_N_I<3> ADDR_N_I<2> ADDR_N_I<1> ADDR_N_I<0> CS00<28> ECLK_H<28> ++ ECLK_H<29> ECLK_B<28> ECLK_B<29> WL_O<463> WL_O<462> WL_O<461> WL_O<460> ++ WL_O<459> WL_O<458> WL_O<457> WL_O<456> WL_O<455> WL_O<454> WL_O<453> ++ WL_O<452> WL_O<451> WL_O<450> WL_O<449> WL_O<448> VDD VSS / ++ RM_IHPSG13_256x32_c2_1P_DEC04 +XSEL<27> ADDR_N_I<3> ADDR_N_I<2> ADDR_N_I<1> ADDR_N_I<0> CS00<27> ECLK_H<27> ++ ECLK_H<28> ECLK_B<27> ECLK_B<28> WL_O<447> WL_O<446> WL_O<445> WL_O<444> ++ WL_O<443> WL_O<442> WL_O<441> WL_O<440> WL_O<439> WL_O<438> WL_O<437> ++ WL_O<436> WL_O<435> WL_O<434> WL_O<433> WL_O<432> VDD VSS / ++ RM_IHPSG13_256x32_c2_1P_DEC04 +XSEL<26> ADDR_N_I<3> ADDR_N_I<2> ADDR_N_I<1> ADDR_N_I<0> CS00<26> ECLK_H<26> ++ ECLK_H<27> ECLK_B<26> ECLK_B<27> WL_O<431> WL_O<430> WL_O<429> WL_O<428> ++ WL_O<427> WL_O<426> WL_O<425> WL_O<424> WL_O<423> WL_O<422> WL_O<421> ++ WL_O<420> WL_O<419> WL_O<418> WL_O<417> WL_O<416> VDD VSS / ++ RM_IHPSG13_256x32_c2_1P_DEC04 +XSEL<25> ADDR_N_I<3> ADDR_N_I<2> ADDR_N_I<1> ADDR_N_I<0> CS00<25> ECLK_H<25> ++ ECLK_H<26> ECLK_B<25> ECLK_B<26> WL_O<415> WL_O<414> WL_O<413> WL_O<412> ++ WL_O<411> WL_O<410> WL_O<409> WL_O<408> WL_O<407> WL_O<406> WL_O<405> ++ WL_O<404> WL_O<403> WL_O<402> WL_O<401> WL_O<400> VDD VSS / ++ RM_IHPSG13_256x32_c2_1P_DEC04 +XSEL<24> ADDR_N_I<3> ADDR_N_I<2> ADDR_N_I<1> ADDR_N_I<0> CS00<24> ECLK_H<24> ++ ECLK_H<25> ECLK_B<24> ECLK_B<25> WL_O<399> WL_O<398> WL_O<397> WL_O<396> ++ WL_O<395> WL_O<394> WL_O<393> WL_O<392> WL_O<391> WL_O<390> WL_O<389> ++ WL_O<388> WL_O<387> WL_O<386> WL_O<385> WL_O<384> VDD VSS / ++ RM_IHPSG13_256x32_c2_1P_DEC04 +XSEL<23> ADDR_N_I<3> ADDR_N_I<2> ADDR_N_I<1> ADDR_N_I<0> CS00<23> ECLK_H<23> ++ ECLK_H<24> ECLK_B<23> ECLK_B<24> WL_O<383> WL_O<382> WL_O<381> WL_O<380> ++ WL_O<379> WL_O<378> WL_O<377> WL_O<376> WL_O<375> WL_O<374> WL_O<373> ++ WL_O<372> WL_O<371> WL_O<370> WL_O<369> WL_O<368> VDD VSS / ++ RM_IHPSG13_256x32_c2_1P_DEC04 +XSEL<22> ADDR_N_I<3> ADDR_N_I<2> ADDR_N_I<1> ADDR_N_I<0> CS00<22> ECLK_H<22> ++ ECLK_H<23> ECLK_B<22> ECLK_B<23> WL_O<367> WL_O<366> WL_O<365> WL_O<364> ++ WL_O<363> WL_O<362> WL_O<361> WL_O<360> WL_O<359> WL_O<358> WL_O<357> ++ WL_O<356> WL_O<355> WL_O<354> WL_O<353> WL_O<352> VDD VSS / ++ RM_IHPSG13_256x32_c2_1P_DEC04 +XSEL<21> ADDR_N_I<3> ADDR_N_I<2> ADDR_N_I<1> ADDR_N_I<0> CS00<21> ECLK_H<21> ++ ECLK_H<22> ECLK_B<21> ECLK_B<22> WL_O<351> WL_O<350> WL_O<349> WL_O<348> ++ WL_O<347> WL_O<346> WL_O<345> WL_O<344> WL_O<343> WL_O<342> WL_O<341> ++ WL_O<340> WL_O<339> WL_O<338> WL_O<337> WL_O<336> VDD VSS / ++ RM_IHPSG13_256x32_c2_1P_DEC04 +XSEL<20> ADDR_N_I<3> ADDR_N_I<2> ADDR_N_I<1> ADDR_N_I<0> CS00<20> ECLK_H<20> ++ ECLK_H<21> ECLK_B<20> ECLK_B<21> WL_O<335> WL_O<334> WL_O<333> WL_O<332> ++ WL_O<331> WL_O<330> WL_O<329> WL_O<328> WL_O<327> WL_O<326> WL_O<325> ++ WL_O<324> WL_O<323> WL_O<322> WL_O<321> WL_O<320> VDD VSS / ++ RM_IHPSG13_256x32_c2_1P_DEC04 +XSEL<19> ADDR_N_I<3> ADDR_N_I<2> ADDR_N_I<1> ADDR_N_I<0> CS00<19> ECLK_H<19> ++ ECLK_H<20> ECLK_B<19> ECLK_B<20> WL_O<319> WL_O<318> WL_O<317> WL_O<316> ++ WL_O<315> WL_O<314> WL_O<313> WL_O<312> WL_O<311> WL_O<310> WL_O<309> ++ WL_O<308> WL_O<307> WL_O<306> WL_O<305> WL_O<304> VDD VSS / ++ RM_IHPSG13_256x32_c2_1P_DEC04 +XSEL<18> ADDR_N_I<3> ADDR_N_I<2> ADDR_N_I<1> ADDR_N_I<0> CS00<18> ECLK_H<18> ++ ECLK_H<19> ECLK_B<18> ECLK_B<19> WL_O<303> WL_O<302> WL_O<301> WL_O<300> ++ WL_O<299> WL_O<298> WL_O<297> WL_O<296> WL_O<295> WL_O<294> WL_O<293> ++ WL_O<292> WL_O<291> WL_O<290> WL_O<289> WL_O<288> VDD VSS / ++ RM_IHPSG13_256x32_c2_1P_DEC04 +XSEL<17> ADDR_N_I<3> ADDR_N_I<2> ADDR_N_I<1> ADDR_N_I<0> CS00<17> ECLK_H<17> ++ ECLK_H<18> ECLK_B<17> ECLK_B<18> WL_O<287> WL_O<286> WL_O<285> WL_O<284> ++ WL_O<283> WL_O<282> WL_O<281> WL_O<280> WL_O<279> WL_O<278> WL_O<277> ++ WL_O<276> WL_O<275> WL_O<274> WL_O<273> WL_O<272> VDD VSS / ++ RM_IHPSG13_256x32_c2_1P_DEC04 +XSEL<16> ADDR_N_I<3> ADDR_N_I<2> ADDR_N_I<1> ADDR_N_I<0> CS00<16> ECLK_H<16> ++ ECLK_H<17> ECLK_B<16> ECLK_B<17> WL_O<271> WL_O<270> WL_O<269> WL_O<268> ++ WL_O<267> WL_O<266> WL_O<265> WL_O<264> WL_O<263> WL_O<262> WL_O<261> ++ WL_O<260> WL_O<259> WL_O<258> WL_O<257> WL_O<256> VDD VSS / ++ RM_IHPSG13_256x32_c2_1P_DEC04 +XSEL<15> ADDR_N_I<3> ADDR_N_I<2> ADDR_N_I<1> ADDR_N_I<0> CS00<15> ECLK_H<15> ++ ECLK_H<16> ECLK_B<15> ECLK_B<16> WL_O<255> WL_O<254> WL_O<253> WL_O<252> ++ WL_O<251> WL_O<250> WL_O<249> WL_O<248> WL_O<247> WL_O<246> WL_O<245> ++ WL_O<244> WL_O<243> WL_O<242> WL_O<241> WL_O<240> VDD VSS / ++ RM_IHPSG13_256x32_c2_1P_DEC04 +XSEL<14> ADDR_N_I<3> ADDR_N_I<2> ADDR_N_I<1> ADDR_N_I<0> CS00<14> ECLK_H<14> ++ ECLK_H<15> ECLK_B<14> ECLK_B<15> WL_O<239> WL_O<238> WL_O<237> WL_O<236> ++ WL_O<235> WL_O<234> WL_O<233> WL_O<232> WL_O<231> WL_O<230> WL_O<229> ++ WL_O<228> WL_O<227> WL_O<226> WL_O<225> WL_O<224> VDD VSS / ++ RM_IHPSG13_256x32_c2_1P_DEC04 +XSEL<13> ADDR_N_I<3> ADDR_N_I<2> ADDR_N_I<1> ADDR_N_I<0> CS00<13> ECLK_H<13> ++ ECLK_H<14> ECLK_B<13> ECLK_B<14> WL_O<223> WL_O<222> WL_O<221> WL_O<220> ++ WL_O<219> WL_O<218> WL_O<217> WL_O<216> WL_O<215> WL_O<214> WL_O<213> ++ WL_O<212> WL_O<211> WL_O<210> WL_O<209> WL_O<208> VDD VSS / ++ RM_IHPSG13_256x32_c2_1P_DEC04 +XSEL<12> ADDR_N_I<3> ADDR_N_I<2> ADDR_N_I<1> ADDR_N_I<0> CS00<12> ECLK_H<12> ++ ECLK_H<13> ECLK_B<12> ECLK_B<13> WL_O<207> WL_O<206> WL_O<205> WL_O<204> ++ WL_O<203> WL_O<202> WL_O<201> WL_O<200> WL_O<199> WL_O<198> WL_O<197> ++ WL_O<196> WL_O<195> WL_O<194> WL_O<193> WL_O<192> VDD VSS / ++ RM_IHPSG13_256x32_c2_1P_DEC04 +XSEL<11> ADDR_N_I<3> ADDR_N_I<2> ADDR_N_I<1> ADDR_N_I<0> CS00<11> ECLK_H<11> ++ ECLK_H<12> ECLK_B<11> ECLK_B<12> WL_O<191> WL_O<190> WL_O<189> WL_O<188> ++ WL_O<187> WL_O<186> WL_O<185> WL_O<184> WL_O<183> WL_O<182> WL_O<181> ++ WL_O<180> WL_O<179> WL_O<178> WL_O<177> WL_O<176> VDD VSS / ++ RM_IHPSG13_256x32_c2_1P_DEC04 +XSEL<10> ADDR_N_I<3> ADDR_N_I<2> ADDR_N_I<1> ADDR_N_I<0> CS00<10> ECLK_H<10> ++ ECLK_H<11> ECLK_B<10> ECLK_B<11> WL_O<175> WL_O<174> WL_O<173> WL_O<172> ++ WL_O<171> WL_O<170> WL_O<169> WL_O<168> WL_O<167> WL_O<166> WL_O<165> ++ WL_O<164> WL_O<163> WL_O<162> WL_O<161> WL_O<160> VDD VSS / ++ RM_IHPSG13_256x32_c2_1P_DEC04 +XSEL<9> ADDR_N_I<3> ADDR_N_I<2> ADDR_N_I<1> ADDR_N_I<0> CS00<9> ECLK_H<9> ++ ECLK_H<10> ECLK_B<9> ECLK_B<10> WL_O<159> WL_O<158> WL_O<157> WL_O<156> ++ WL_O<155> WL_O<154> WL_O<153> WL_O<152> WL_O<151> WL_O<150> WL_O<149> ++ WL_O<148> WL_O<147> WL_O<146> WL_O<145> WL_O<144> VDD VSS / ++ RM_IHPSG13_256x32_c2_1P_DEC04 +XSEL<8> ADDR_N_I<3> ADDR_N_I<2> ADDR_N_I<1> ADDR_N_I<0> CS00<8> ECLK_H<8> ++ ECLK_H<9> ECLK_B<8> ECLK_B<9> WL_O<143> WL_O<142> WL_O<141> WL_O<140> ++ WL_O<139> WL_O<138> WL_O<137> WL_O<136> WL_O<135> WL_O<134> WL_O<133> ++ WL_O<132> WL_O<131> WL_O<130> WL_O<129> WL_O<128> VDD VSS / ++ RM_IHPSG13_256x32_c2_1P_DEC04 +XSEL<7> ADDR_N_I<3> ADDR_N_I<2> ADDR_N_I<1> ADDR_N_I<0> CS00<7> ECLK_H<7> ++ ECLK_H<8> ECLK_B<7> ECLK_B<8> WL_O<127> WL_O<126> WL_O<125> WL_O<124> ++ WL_O<123> WL_O<122> WL_O<121> WL_O<120> WL_O<119> WL_O<118> WL_O<117> ++ WL_O<116> WL_O<115> WL_O<114> WL_O<113> WL_O<112> VDD VSS / ++ RM_IHPSG13_256x32_c2_1P_DEC04 +XSEL<6> ADDR_N_I<3> ADDR_N_I<2> ADDR_N_I<1> ADDR_N_I<0> CS00<6> ECLK_H<6> ++ ECLK_H<7> ECLK_B<6> ECLK_B<7> WL_O<111> WL_O<110> WL_O<109> WL_O<108> ++ WL_O<107> WL_O<106> WL_O<105> WL_O<104> WL_O<103> WL_O<102> WL_O<101> ++ WL_O<100> WL_O<99> WL_O<98> WL_O<97> WL_O<96> VDD VSS / ++ RM_IHPSG13_256x32_c2_1P_DEC04 +XSEL<5> ADDR_N_I<3> ADDR_N_I<2> ADDR_N_I<1> ADDR_N_I<0> CS00<5> ECLK_H<5> ++ ECLK_H<6> ECLK_B<5> ECLK_B<6> WL_O<95> WL_O<94> WL_O<93> WL_O<92> WL_O<91> ++ WL_O<90> WL_O<89> WL_O<88> WL_O<87> WL_O<86> WL_O<85> WL_O<84> WL_O<83> ++ WL_O<82> WL_O<81> WL_O<80> VDD VSS / RM_IHPSG13_256x32_c2_1P_DEC04 +XSEL<4> ADDR_N_I<3> ADDR_N_I<2> ADDR_N_I<1> ADDR_N_I<0> CS00<4> ECLK_H<4> ++ ECLK_H<5> ECLK_B<4> ECLK_B<5> WL_O<79> WL_O<78> WL_O<77> WL_O<76> WL_O<75> ++ WL_O<74> WL_O<73> WL_O<72> WL_O<71> WL_O<70> WL_O<69> WL_O<68> WL_O<67> ++ WL_O<66> WL_O<65> WL_O<64> VDD VSS / RM_IHPSG13_256x32_c2_1P_DEC04 +XSEL<3> ADDR_N_I<3> ADDR_N_I<2> ADDR_N_I<1> ADDR_N_I<0> CS00<3> ECLK_H<3> ++ ECLK_H<4> ECLK_B<3> ECLK_B<4> WL_O<63> WL_O<62> WL_O<61> WL_O<60> WL_O<59> ++ WL_O<58> WL_O<57> WL_O<56> WL_O<55> WL_O<54> WL_O<53> WL_O<52> WL_O<51> ++ WL_O<50> WL_O<49> WL_O<48> VDD VSS / RM_IHPSG13_256x32_c2_1P_DEC04 +XSEL<2> ADDR_N_I<3> ADDR_N_I<2> ADDR_N_I<1> ADDR_N_I<0> CS00<2> ECLK_H<2> ++ ECLK_H<3> ECLK_B<2> ECLK_B<3> WL_O<47> WL_O<46> WL_O<45> WL_O<44> WL_O<43> ++ WL_O<42> WL_O<41> WL_O<40> WL_O<39> WL_O<38> WL_O<37> WL_O<36> WL_O<35> ++ WL_O<34> WL_O<33> WL_O<32> VDD VSS / RM_IHPSG13_256x32_c2_1P_DEC04 +XSEL<1> ADDR_N_I<3> ADDR_N_I<2> ADDR_N_I<1> ADDR_N_I<0> CS00<1> ECLK_H<1> ++ ECLK_H<2> ECLK_B<1> ECLK_B<2> WL_O<31> WL_O<30> WL_O<29> WL_O<28> WL_O<27> ++ WL_O<26> WL_O<25> WL_O<24> WL_O<23> WL_O<22> WL_O<21> WL_O<20> WL_O<19> ++ WL_O<18> WL_O<17> WL_O<16> VDD VSS / RM_IHPSG13_256x32_c2_1P_DEC04 +XSEL<0> ADDR_N_I<3> ADDR_N_I<2> ADDR_N_I<1> ADDR_N_I<0> CS00<0> ECLK_I ++ ECLK_H<1> ECLK_B<0> ECLK_B<1> WL_O<15> WL_O<14> WL_O<13> WL_O<12> WL_O<11> ++ WL_O<10> WL_O<9> WL_O<8> WL_O<7> WL_O<6> WL_O<5> WL_O<4> WL_O<3> WL_O<2> ++ WL_O<1> WL_O<0> VDD VSS / RM_IHPSG13_256x32_c2_1P_DEC04 +XDEC01<10> ADDR_N_I<9> ADDR_N_I<8> CS_I CS04<1> VDD VSS / ++ RM_IHPSG13_256x32_c2_1P_DEC01 +XDEC01<9> ADDR_N_I<7> ADDR_N_I<6> CS04<1> CS02<5> VDD VSS / ++ RM_IHPSG13_256x32_c2_1P_DEC01 +XDEC01<8> ADDR_N_I<7> ADDR_N_I<6> CS04<0> CS02<1> VDD VSS / ++ RM_IHPSG13_256x32_c2_1P_DEC01 +XDEC01<7> ADDR_N_I<5> ADDR_N_I<4> CS02<7> CS00<29> VDD VSS / ++ RM_IHPSG13_256x32_c2_1P_DEC01 +XDEC01<6> ADDR_N_I<5> ADDR_N_I<4> CS02<6> CS00<25> VDD VSS / ++ RM_IHPSG13_256x32_c2_1P_DEC01 +XDEC01<5> ADDR_N_I<5> ADDR_N_I<4> CS02<5> CS00<21> VDD VSS / ++ RM_IHPSG13_256x32_c2_1P_DEC01 +XDEC01<4> ADDR_N_I<5> ADDR_N_I<4> CS02<4> CS00<17> VDD VSS / ++ RM_IHPSG13_256x32_c2_1P_DEC01 +XDEC01<3> ADDR_N_I<5> ADDR_N_I<4> CS02<3> CS00<13> VDD VSS / ++ RM_IHPSG13_256x32_c2_1P_DEC01 +XDEC01<2> ADDR_N_I<5> ADDR_N_I<4> CS02<2> CS00<9> VDD VSS / ++ RM_IHPSG13_256x32_c2_1P_DEC01 +XDEC01<1> ADDR_N_I<5> ADDR_N_I<4> CS02<1> CS00<5> VDD VSS / ++ RM_IHPSG13_256x32_c2_1P_DEC01 +XDEC01<0> ADDR_N_I<5> ADDR_N_I<4> CS02<0> CS00<1> VDD VSS / ++ RM_IHPSG13_256x32_c2_1P_DEC01 +XDEC10<9> ADDR_N_I<7> ADDR_N_I<6> CS04<1> CS02<6> VDD VSS / ++ RM_IHPSG13_256x32_c2_1P_DEC02 +XDEC10<8> ADDR_N_I<7> ADDR_N_I<6> CS04<0> CS02<2> VDD VSS / ++ RM_IHPSG13_256x32_c2_1P_DEC02 +XDEC10<7> ADDR_N_I<5> ADDR_N_I<4> CS02<7> CS00<30> VDD VSS / ++ RM_IHPSG13_256x32_c2_1P_DEC02 +XDEC10<6> ADDR_N_I<5> ADDR_N_I<4> CS02<6> CS00<26> VDD VSS / ++ RM_IHPSG13_256x32_c2_1P_DEC02 +XDEC10<5> ADDR_N_I<5> ADDR_N_I<4> CS02<5> CS00<22> VDD VSS / ++ RM_IHPSG13_256x32_c2_1P_DEC02 +XDEC10<4> ADDR_N_I<5> ADDR_N_I<4> CS02<4> CS00<18> VDD VSS / ++ RM_IHPSG13_256x32_c2_1P_DEC02 +XDEC10<3> ADDR_N_I<5> ADDR_N_I<4> CS02<3> CS00<14> VDD VSS / ++ RM_IHPSG13_256x32_c2_1P_DEC02 +XDEC10<2> ADDR_N_I<5> ADDR_N_I<4> CS02<2> CS00<10> VDD VSS / ++ RM_IHPSG13_256x32_c2_1P_DEC02 +XDEC10<1> ADDR_N_I<5> ADDR_N_I<4> CS02<1> CS00<6> VDD VSS / ++ RM_IHPSG13_256x32_c2_1P_DEC02 +XDEC10<0> ADDR_N_I<5> ADDR_N_I<4> CS02<0> CS00<2> VDD VSS / ++ RM_IHPSG13_256x32_c2_1P_DEC02 +XI0 ADDR_N_I<9> VDD VSS / RSC_IHPSG13_TIEL +.ENDS +.SUBCKT RM_IHPSG13_256x32_c2_1P_ROWREG9 ACLK_N_I ADDR_I<8> ADDR_I<7> ADDR_I<6> ADDR_I<5> ++ ADDR_I<4> ADDR_I<3> ADDR_I<2> ADDR_I<1> ADDR_I<0> ADDR_N_O<8> ADDR_N_O<7> ++ ADDR_N_O<6> ADDR_N_O<5> ADDR_N_O<4> ADDR_N_O<3> ADDR_N_O<2> ADDR_N_O<1> ++ ADDR_N_O<0> BIST_ADDR_I<8> BIST_ADDR_I<7> BIST_ADDR_I<6> BIST_ADDR_I<5> ++ BIST_ADDR_I<4> BIST_ADDR_I<3> BIST_ADDR_I<2> BIST_ADDR_I<1> BIST_ADDR_I<0> ++ BIST_EN_I VDD VSS +XINV<8> q_int<8> qn_int<8> VDD VSS / RSC_IHPSG13_CINVX2 +XINV<7> q_int<7> qn_int<7> VDD VSS / RSC_IHPSG13_CINVX2 +XINV<6> q_int<6> qn_int<6> VDD VSS / RSC_IHPSG13_CINVX2 +XINV<5> q_int<5> qn_int<5> VDD VSS / RSC_IHPSG13_CINVX2 +XINV<4> q_int<4> qn_int<4> VDD VSS / RSC_IHPSG13_CINVX2 +XINV<3> q_int<3> qn_int<3> VDD VSS / RSC_IHPSG13_CINVX2 +XINV<2> q_int<2> qn_int<2> VDD VSS / RSC_IHPSG13_CINVX2 +XINV<1> q_int<1> qn_int<1> VDD VSS / RSC_IHPSG13_CINVX2 +XINV<0> q_int<0> qn_int<0> VDD VSS / RSC_IHPSG13_CINVX2 +XDRV<8> qn_int<8> ADDR_N_O<8> VDD VSS / RSC_IHPSG13_CINVX8 +XDRV<7> qn_int<7> ADDR_N_O<7> VDD VSS / RSC_IHPSG13_CINVX8 +XDRV<6> qn_int<6> ADDR_N_O<6> VDD VSS / RSC_IHPSG13_CINVX8 +XDRV<5> qn_int<5> ADDR_N_O<5> VDD VSS / RSC_IHPSG13_CINVX8 +XDRV<4> qn_int<4> ADDR_N_O<4> VDD VSS / RSC_IHPSG13_CINVX8 +XDRV<3> qn_int<3> ADDR_N_O<3> VDD VSS / RSC_IHPSG13_CINVX8 +XDRV<2> qn_int<2> ADDR_N_O<2> VDD VSS / RSC_IHPSG13_CINVX8 +XDRV<1> qn_int<1> ADDR_N_O<1> VDD VSS / RSC_IHPSG13_CINVX8 +XDRV<0> qn_int<0> ADDR_N_O<0> VDD VSS / RSC_IHPSG13_CINVX8 +XDFF<8> BIST_EN_I BIST_ADDR_I<8> ACLK_N_I ADDR_I<8> q_int<8> net04<0> VDD ++ VSS / RSC_IHPSG13_DFNQMX2IX1 +XDFF<7> BIST_EN_I BIST_ADDR_I<7> ACLK_N_I ADDR_I<7> q_int<7> net04<1> VDD ++ VSS / RSC_IHPSG13_DFNQMX2IX1 +XDFF<6> BIST_EN_I BIST_ADDR_I<6> ACLK_N_I ADDR_I<6> q_int<6> net04<2> VDD ++ VSS / RSC_IHPSG13_DFNQMX2IX1 +XDFF<5> BIST_EN_I BIST_ADDR_I<5> ACLK_N_I ADDR_I<5> q_int<5> net04<3> VDD ++ VSS / RSC_IHPSG13_DFNQMX2IX1 +XDFF<4> BIST_EN_I BIST_ADDR_I<4> ACLK_N_I ADDR_I<4> q_int<4> net04<4> VDD ++ VSS / RSC_IHPSG13_DFNQMX2IX1 +XDFF<3> BIST_EN_I BIST_ADDR_I<3> ACLK_N_I ADDR_I<3> q_int<3> net04<5> VDD ++ VSS / RSC_IHPSG13_DFNQMX2IX1 +XDFF<2> BIST_EN_I BIST_ADDR_I<2> ACLK_N_I ADDR_I<2> q_int<2> net04<6> VDD ++ VSS / RSC_IHPSG13_DFNQMX2IX1 +XDFF<1> BIST_EN_I BIST_ADDR_I<1> ACLK_N_I ADDR_I<1> q_int<1> net04<7> VDD ++ VSS / RSC_IHPSG13_DFNQMX2IX1 +XDFF<0> BIST_EN_I BIST_ADDR_I<0> ACLK_N_I ADDR_I<0> q_int<0> net04<8> VDD ++ VSS / RSC_IHPSG13_DFNQMX2IX1 +.ENDS + +.SUBCKT RM_IHPSG13_256x32_c2_1P_ROWDEC7 ADDR_N_I<6> ADDR_N_I<5> ADDR_N_I<4> ADDR_N_I<3> ++ ADDR_N_I<2> ADDR_N_I<1> ADDR_N_I<0> CS_I ECLK_I WL_O<127> WL_O<126> ++ WL_O<125> WL_O<124> WL_O<123> WL_O<122> WL_O<121> WL_O<120> WL_O<119> ++ WL_O<118> WL_O<117> WL_O<116> WL_O<115> WL_O<114> WL_O<113> WL_O<112> ++ WL_O<111> WL_O<110> WL_O<109> WL_O<108> WL_O<107> WL_O<106> WL_O<105> ++ WL_O<104> WL_O<103> WL_O<102> WL_O<101> WL_O<100> WL_O<99> WL_O<98> WL_O<97> ++ WL_O<96> WL_O<95> WL_O<94> WL_O<93> WL_O<92> WL_O<91> WL_O<90> WL_O<89> ++ WL_O<88> WL_O<87> WL_O<86> WL_O<85> WL_O<84> WL_O<83> WL_O<82> WL_O<81> ++ WL_O<80> WL_O<79> WL_O<78> WL_O<77> WL_O<76> WL_O<75> WL_O<74> WL_O<73> ++ WL_O<72> WL_O<71> WL_O<70> WL_O<69> WL_O<68> WL_O<67> WL_O<66> WL_O<65> ++ WL_O<64> WL_O<63> WL_O<62> WL_O<61> WL_O<60> WL_O<59> WL_O<58> WL_O<57> ++ WL_O<56> WL_O<55> WL_O<54> WL_O<53> WL_O<52> WL_O<51> WL_O<50> WL_O<49> ++ WL_O<48> WL_O<47> WL_O<46> WL_O<45> WL_O<44> WL_O<43> WL_O<42> WL_O<41> ++ WL_O<40> WL_O<39> WL_O<38> WL_O<37> WL_O<36> WL_O<35> WL_O<34> WL_O<33> ++ WL_O<32> WL_O<31> WL_O<30> WL_O<29> WL_O<28> WL_O<27> WL_O<26> WL_O<25> ++ WL_O<24> WL_O<23> WL_O<22> WL_O<21> WL_O<20> WL_O<19> WL_O<18> WL_O<17> ++ WL_O<16> WL_O<15> WL_O<14> WL_O<13> WL_O<12> WL_O<11> WL_O<10> WL_O<9> ++ WL_O<8> WL_O<7> WL_O<6> WL_O<5> WL_O<4> WL_O<3> WL_O<2> WL_O<1> WL_O<0> ++ VDD VSS +XDEC11<1> ADDR_N_I<5> ADDR_N_I<4> CS04<1> CS00<7> VDD VSS / ++ RM_IHPSG13_256x32_c2_1P_DEC03 +XDEC11<0> ADDR_N_I<5> ADDR_N_I<4> CS04<0> CS00<3> VDD VSS / ++ RM_IHPSG13_256x32_c2_1P_DEC03 +XDEC10<1> ADDR_N_I<5> ADDR_N_I<4> CS04<1> CS00<6> VDD VSS / ++ RM_IHPSG13_256x32_c2_1P_DEC02 +XDEC10<0> ADDR_N_I<5> ADDR_N_I<4> CS04<0> CS00<2> VDD VSS / ++ RM_IHPSG13_256x32_c2_1P_DEC02 +XSEL<7> ADDR_N_I<3> ADDR_N_I<2> ADDR_N_I<1> ADDR_N_I<0> CS00<7> ECLK_H<7> ++ ECLK_H<8> ECLK_B<7> ECLK_B<8> WL_O<127> WL_O<126> WL_O<125> WL_O<124> ++ WL_O<123> WL_O<122> WL_O<121> WL_O<120> WL_O<119> WL_O<118> WL_O<117> ++ WL_O<116> WL_O<115> WL_O<114> WL_O<113> WL_O<112> VDD VSS / ++ RM_IHPSG13_256x32_c2_1P_DEC04 +XSEL<6> ADDR_N_I<3> ADDR_N_I<2> ADDR_N_I<1> ADDR_N_I<0> CS00<6> ECLK_H<6> ++ ECLK_H<7> ECLK_B<6> ECLK_B<7> WL_O<111> WL_O<110> WL_O<109> WL_O<108> ++ WL_O<107> WL_O<106> WL_O<105> WL_O<104> WL_O<103> WL_O<102> WL_O<101> ++ WL_O<100> WL_O<99> WL_O<98> WL_O<97> WL_O<96> VDD VSS / ++ RM_IHPSG13_256x32_c2_1P_DEC04 +XSEL<5> ADDR_N_I<3> ADDR_N_I<2> ADDR_N_I<1> ADDR_N_I<0> CS00<5> ECLK_H<5> ++ ECLK_H<6> ECLK_B<5> ECLK_B<6> WL_O<95> WL_O<94> WL_O<93> WL_O<92> WL_O<91> ++ WL_O<90> WL_O<89> WL_O<88> WL_O<87> WL_O<86> WL_O<85> WL_O<84> WL_O<83> ++ WL_O<82> WL_O<81> WL_O<80> VDD VSS / RM_IHPSG13_256x32_c2_1P_DEC04 +XSEL<4> ADDR_N_I<3> ADDR_N_I<2> ADDR_N_I<1> ADDR_N_I<0> CS00<4> ECLK_H<4> ++ ECLK_H<5> ECLK_B<4> ECLK_B<5> WL_O<79> WL_O<78> WL_O<77> WL_O<76> WL_O<75> ++ WL_O<74> WL_O<73> WL_O<72> WL_O<71> WL_O<70> WL_O<69> WL_O<68> WL_O<67> ++ WL_O<66> WL_O<65> WL_O<64> VDD VSS / RM_IHPSG13_256x32_c2_1P_DEC04 +XSEL<3> ADDR_N_I<3> ADDR_N_I<2> ADDR_N_I<1> ADDR_N_I<0> CS00<3> ECLK_H<3> ++ ECLK_H<4> ECLK_B<3> ECLK_B<4> WL_O<63> WL_O<62> WL_O<61> WL_O<60> WL_O<59> ++ WL_O<58> WL_O<57> WL_O<56> WL_O<55> WL_O<54> WL_O<53> WL_O<52> WL_O<51> ++ WL_O<50> WL_O<49> WL_O<48> VDD VSS / RM_IHPSG13_256x32_c2_1P_DEC04 +XSEL<2> ADDR_N_I<3> ADDR_N_I<2> ADDR_N_I<1> ADDR_N_I<0> CS00<2> ECLK_H<2> ++ ECLK_H<3> ECLK_B<2> ECLK_B<3> WL_O<47> WL_O<46> WL_O<45> WL_O<44> WL_O<43> ++ WL_O<42> WL_O<41> WL_O<40> WL_O<39> WL_O<38> WL_O<37> WL_O<36> WL_O<35> ++ WL_O<34> WL_O<33> WL_O<32> VDD VSS / RM_IHPSG13_256x32_c2_1P_DEC04 +XSEL<1> ADDR_N_I<3> ADDR_N_I<2> ADDR_N_I<1> ADDR_N_I<0> CS00<1> ECLK_H<1> ++ ECLK_H<2> ECLK_B<1> ECLK_B<2> WL_O<31> WL_O<30> WL_O<29> WL_O<28> WL_O<27> ++ WL_O<26> WL_O<25> WL_O<24> WL_O<23> WL_O<22> WL_O<21> WL_O<20> WL_O<19> ++ WL_O<18> WL_O<17> WL_O<16> VDD VSS / RM_IHPSG13_256x32_c2_1P_DEC04 +XSEL<0> ADDR_N_I<3> ADDR_N_I<2> ADDR_N_I<1> ADDR_N_I<0> CS00<0> ECLK_I ++ ECLK_H<1> ECLK_B<0> ECLK_B<1> WL_O<15> WL_O<14> WL_O<13> WL_O<12> WL_O<11> ++ WL_O<10> WL_O<9> WL_O<8> WL_O<7> WL_O<6> WL_O<5> WL_O<4> WL_O<3> WL_O<2> ++ WL_O<1> WL_O<0> VDD VSS / RM_IHPSG13_256x32_c2_1P_DEC04 +XDEC00<2> ADDR_N_I<7> ADDR_N_I<6> CS_I CS04<0> VDD VSS / ++ RM_IHPSG13_256x32_c2_1P_DEC00 +XDEC00<1> ADDR_N_I<5> ADDR_N_I<4> CS04<1> CS00<4> VDD VSS / ++ RM_IHPSG13_256x32_c2_1P_DEC00 +XDEC00<0> ADDR_N_I<5> ADDR_N_I<4> CS04<0> CS00<0> VDD VSS / ++ RM_IHPSG13_256x32_c2_1P_DEC00 +XDEC01<2> ADDR_N_I<7> ADDR_N_I<6> CS_I CS04<1> VDD VSS / ++ RM_IHPSG13_256x32_c2_1P_DEC01 +XDEC01<1> ADDR_N_I<5> ADDR_N_I<4> CS04<1> CS00<5> VDD VSS / ++ RM_IHPSG13_256x32_c2_1P_DEC01 +XDEC01<0> ADDR_N_I<5> ADDR_N_I<4> CS04<0> CS00<1> VDD VSS / ++ RM_IHPSG13_256x32_c2_1P_DEC01 +XL2<44> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<43> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<42> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<41> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<40> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<39> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<38> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<37> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<36> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<35> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<34> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<33> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<32> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<31> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<30> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<29> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<28> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<27> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<26> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<25> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<24> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<23> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<22> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<21> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<20> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<19> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<18> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<17> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<16> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<15> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<14> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<13> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<12> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<11> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<10> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<9> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<8> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<7> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<6> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<5> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<4> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<3> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<2> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<1> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI0 ADDR_N_I<7> VDD VSS / RSC_IHPSG13_TIEL +.ENDS +.SUBCKT RM_IHPSG13_256x32_c2_1P_ROWREG7 ACLK_N_I ADDR_I<6> ADDR_I<5> ADDR_I<4> ADDR_I<3> ++ ADDR_I<2> ADDR_I<1> ADDR_I<0> ADDR_N_O<6> ADDR_N_O<5> ADDR_N_O<4> ++ ADDR_N_O<3> ADDR_N_O<2> ADDR_N_O<1> ADDR_N_O<0> BIST_ADDR_I<6> ++ BIST_ADDR_I<5> BIST_ADDR_I<4> BIST_ADDR_I<3> BIST_ADDR_I<2> BIST_ADDR_I<1> ++ BIST_ADDR_I<0> BIST_EN_I VDD VSS +XINV<6> q_int<6> qn_int<6> VDD VSS / RSC_IHPSG13_CINVX2 +XINV<5> q_int<5> qn_int<5> VDD VSS / RSC_IHPSG13_CINVX2 +XINV<4> q_int<4> qn_int<4> VDD VSS / RSC_IHPSG13_CINVX2 +XINV<3> q_int<3> qn_int<3> VDD VSS / RSC_IHPSG13_CINVX2 +XINV<2> q_int<2> qn_int<2> VDD VSS / RSC_IHPSG13_CINVX2 +XINV<1> q_int<1> qn_int<1> VDD VSS / RSC_IHPSG13_CINVX2 +XINV<0> q_int<0> qn_int<0> VDD VSS / RSC_IHPSG13_CINVX2 +XDRV<6> qn_int<6> ADDR_N_O<6> VDD VSS / RSC_IHPSG13_CINVX8 +XDRV<5> qn_int<5> ADDR_N_O<5> VDD VSS / RSC_IHPSG13_CINVX8 +XDRV<4> qn_int<4> ADDR_N_O<4> VDD VSS / RSC_IHPSG13_CINVX8 +XDRV<3> qn_int<3> ADDR_N_O<3> VDD VSS / RSC_IHPSG13_CINVX8 +XDRV<2> qn_int<2> ADDR_N_O<2> VDD VSS / RSC_IHPSG13_CINVX8 +XDRV<1> qn_int<1> ADDR_N_O<1> VDD VSS / RSC_IHPSG13_CINVX8 +XDRV<0> qn_int<0> ADDR_N_O<0> VDD VSS / RSC_IHPSG13_CINVX8 +XDFF<6> BIST_EN_I BIST_ADDR_I<6> ACLK_N_I ADDR_I<6> q_int<6> net2<0> VDD ++ VSS / RSC_IHPSG13_DFNQMX2IX1 +XDFF<5> BIST_EN_I BIST_ADDR_I<5> ACLK_N_I ADDR_I<5> q_int<5> net2<1> VDD ++ VSS / RSC_IHPSG13_DFNQMX2IX1 +XDFF<4> BIST_EN_I BIST_ADDR_I<4> ACLK_N_I ADDR_I<4> q_int<4> net2<2> VDD ++ VSS / RSC_IHPSG13_DFNQMX2IX1 +XDFF<3> BIST_EN_I BIST_ADDR_I<3> ACLK_N_I ADDR_I<3> q_int<3> net2<3> VDD ++ VSS / RSC_IHPSG13_DFNQMX2IX1 +XDFF<2> BIST_EN_I BIST_ADDR_I<2> ACLK_N_I ADDR_I<2> q_int<2> net2<4> VDD ++ VSS / RSC_IHPSG13_DFNQMX2IX1 +XDFF<1> BIST_EN_I BIST_ADDR_I<1> ACLK_N_I ADDR_I<1> q_int<1> net2<5> VDD ++ VSS / RSC_IHPSG13_DFNQMX2IX1 +XDFF<0> BIST_EN_I BIST_ADDR_I<0> ACLK_N_I ADDR_I<0> q_int<0> net2<6> VDD ++ VSS / RSC_IHPSG13_DFNQMX2IX1 +XI11<8> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI11<7> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI11<6> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI11<5> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI11<4> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI11<3> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI11<2> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI11<1> VDD VSS / RSC_IHPSG13_FILLCAP8 +.ENDS + +.SUBCKT RM_IHPSG13_256x32_c2_1P_COLDRV13X8 ADDR_COL_I<1> ADDR_COL_I<0> ADDR_COL_O<1> ++ ADDR_COL_O<0> ADDR_DEC_I<7> ADDR_DEC_I<6> ADDR_DEC_I<5> ADDR_DEC_I<4> ++ ADDR_DEC_I<3> ADDR_DEC_I<2> ADDR_DEC_I<1> ADDR_DEC_I<0> ADDR_DEC_O<7> ++ ADDR_DEC_O<6> ADDR_DEC_O<5> ADDR_DEC_O<4> ADDR_DEC_O<3> ADDR_DEC_O<2> ++ ADDR_DEC_O<1> ADDR_DEC_O<0> DCLK_I DCLK_O RCLK_I RCLK_O WCLK_I WCLK_O ++ VDD VSS +XI0<1> VDD VSS / RSC_IHPSG13_FILLCAP4 +XI0<0> VDD VSS / RSC_IHPSG13_FILLCAP4 +XADDR_COL_DRV<1> ADDR_COL_I<1> ADDR_COL_O<1> VDD VSS / ++ RSC_IHPSG13_CBUFX8 +XADDR_COL_DRV<0> ADDR_COL_I<0> ADDR_COL_O<0> VDD VSS / ++ RSC_IHPSG13_CBUFX8 +XADDR_DEC_DRV<7> ADDR_DEC_I<7> ADDR_DEC_O<7> VDD VSS / ++ RSC_IHPSG13_CBUFX8 +XADDR_DEC_DRV<6> ADDR_DEC_I<6> ADDR_DEC_O<6> VDD VSS / ++ RSC_IHPSG13_CBUFX8 +XADDR_DEC_DRV<5> ADDR_DEC_I<5> ADDR_DEC_O<5> VDD VSS / ++ RSC_IHPSG13_CBUFX8 +XADDR_DEC_DRV<4> ADDR_DEC_I<4> ADDR_DEC_O<4> VDD VSS / ++ RSC_IHPSG13_CBUFX8 +XADDR_DEC_DRV<3> ADDR_DEC_I<3> ADDR_DEC_O<3> VDD VSS / ++ RSC_IHPSG13_CBUFX8 +XADDR_DEC_DRV<2> ADDR_DEC_I<2> ADDR_DEC_O<2> VDD VSS / ++ RSC_IHPSG13_CBUFX8 +XADDR_DEC_DRV<1> ADDR_DEC_I<1> ADDR_DEC_O<1> VDD VSS / ++ RSC_IHPSG13_CBUFX8 +XADDR_DEC_DRV<0> ADDR_DEC_I<0> ADDR_DEC_O<0> VDD VSS / ++ RSC_IHPSG13_CBUFX8 +XDCLK_DRV DCLK_I DCLK_O VDD VSS / RSC_IHPSG13_CBUFX8 +XRCLK_DRV RCLK_I RCLK_O VDD VSS / RSC_IHPSG13_CBUFX8 +XWCLK_DRV WCLK_I WCLK_O VDD VSS / RSC_IHPSG13_CBUFX8 +.ENDS +.SUBCKT RM_IHPSG13_256x32_c2_1P_WLDRV16X8 A<15> A<14> A<13> A<12> A<11> A<10> A<9> A<8> ++ A<7> A<6> A<5> A<4> A<3> A<2> A<1> A<0> Z<15> Z<14> Z<13> Z<12> Z<11> Z<10> ++ Z<9> Z<8> Z<7> Z<6> Z<5> Z<4> Z<3> Z<2> Z<1> Z<0> VDD VSS +XBUF<15> A<15> Z<15> VDD VSS / RSC_IHPSG13_WLDRVX8 +XBUF<14> A<14> Z<14> VDD VSS / RSC_IHPSG13_WLDRVX8 +XBUF<13> A<13> Z<13> VDD VSS / RSC_IHPSG13_WLDRVX8 +XBUF<12> A<12> Z<12> VDD VSS / RSC_IHPSG13_WLDRVX8 +XBUF<11> A<11> Z<11> VDD VSS / RSC_IHPSG13_WLDRVX8 +XBUF<10> A<10> Z<10> VDD VSS / RSC_IHPSG13_WLDRVX8 +XBUF<9> A<9> Z<9> VDD VSS / RSC_IHPSG13_WLDRVX8 +XBUF<8> A<8> Z<8> VDD VSS / RSC_IHPSG13_WLDRVX8 +XBUF<7> A<7> Z<7> VDD VSS / RSC_IHPSG13_WLDRVX8 +XBUF<6> A<6> Z<6> VDD VSS / RSC_IHPSG13_WLDRVX8 +XBUF<5> A<5> Z<5> VDD VSS / RSC_IHPSG13_WLDRVX8 +XBUF<4> A<4> Z<4> VDD VSS / RSC_IHPSG13_WLDRVX8 +XBUF<3> A<3> Z<3> VDD VSS / RSC_IHPSG13_WLDRVX8 +XBUF<2> A<2> Z<2> VDD VSS / RSC_IHPSG13_WLDRVX8 +XBUF<1> A<1> Z<1> VDD VSS / RSC_IHPSG13_WLDRVX8 +XBUF<0> A<0> Z<0> VDD VSS / RSC_IHPSG13_WLDRVX8 +.ENDS + + + +.SUBCKT RM_IHPSG13_256x32_c2_1P_ROWDEC6 ADDR_N_I<5> ADDR_N_I<4> ADDR_N_I<3> ADDR_N_I<2> ++ ADDR_N_I<1> ADDR_N_I<0> CS_I ECLK_I WL_O<63> WL_O<62> WL_O<61> WL_O<60> ++ WL_O<59> WL_O<58> WL_O<57> WL_O<56> WL_O<55> WL_O<54> WL_O<53> WL_O<52> ++ WL_O<51> WL_O<50> WL_O<49> WL_O<48> WL_O<47> WL_O<46> WL_O<45> WL_O<44> ++ WL_O<43> WL_O<42> WL_O<41> WL_O<40> WL_O<39> WL_O<38> WL_O<37> WL_O<36> ++ WL_O<35> WL_O<34> WL_O<33> WL_O<32> WL_O<31> WL_O<30> WL_O<29> WL_O<28> ++ WL_O<27> WL_O<26> WL_O<25> WL_O<24> WL_O<23> WL_O<22> WL_O<21> WL_O<20> ++ WL_O<19> WL_O<18> WL_O<17> WL_O<16> WL_O<15> WL_O<14> WL_O<13> WL_O<12> ++ WL_O<11> WL_O<10> WL_O<9> WL_O<8> WL_O<7> WL_O<6> WL_O<5> WL_O<4> WL_O<3> ++ WL_O<2> WL_O<1> WL_O<0> VDD VSS +XDEC11 ADDR_N_I<5> ADDR_N_I<4> CS_I CS00<3> VDD VSS / ++ RM_IHPSG13_256x32_c2_1P_DEC03 +XDEC00 ADDR_N_I<5> ADDR_N_I<4> CS_I CS00<0> VDD VSS / ++ RM_IHPSG13_256x32_c2_1P_DEC00 +XDEC01 ADDR_N_I<5> ADDR_N_I<4> CS_I CS00<1> VDD VSS / ++ RM_IHPSG13_256x32_c2_1P_DEC01 +XDEC10 ADDR_N_I<5> ADDR_N_I<4> CS_I CS00<2> VDD VSS / ++ RM_IHPSG13_256x32_c2_1P_DEC02 +XSEL<3> ADDR_N_I<3> ADDR_N_I<2> ADDR_N_I<1> ADDR_N_I<0> CS00<3> ECLK_H<3> ++ ECLK_H<4> ECLK_B<3> ECLK_B<4> WL_O<63> WL_O<62> WL_O<61> WL_O<60> WL_O<59> ++ WL_O<58> WL_O<57> WL_O<56> WL_O<55> WL_O<54> WL_O<53> WL_O<52> WL_O<51> ++ WL_O<50> WL_O<49> WL_O<48> VDD VSS / RM_IHPSG13_256x32_c2_1P_DEC04 +XSEL<2> ADDR_N_I<3> ADDR_N_I<2> ADDR_N_I<1> ADDR_N_I<0> CS00<2> ECLK_H<2> ++ ECLK_H<3> ECLK_B<2> ECLK_B<3> WL_O<47> WL_O<46> WL_O<45> WL_O<44> WL_O<43> ++ WL_O<42> WL_O<41> WL_O<40> WL_O<39> WL_O<38> WL_O<37> WL_O<36> WL_O<35> ++ WL_O<34> WL_O<33> WL_O<32> VDD VSS / RM_IHPSG13_256x32_c2_1P_DEC04 +XSEL<1> ADDR_N_I<3> ADDR_N_I<2> ADDR_N_I<1> ADDR_N_I<0> CS00<1> ECLK_H<1> ++ ECLK_H<2> ECLK_B<1> ECLK_B<2> WL_O<31> WL_O<30> WL_O<29> WL_O<28> WL_O<27> ++ WL_O<26> WL_O<25> WL_O<24> WL_O<23> WL_O<22> WL_O<21> WL_O<20> WL_O<19> ++ WL_O<18> WL_O<17> WL_O<16> VDD VSS / RM_IHPSG13_256x32_c2_1P_DEC04 +XSEL<0> ADDR_N_I<3> ADDR_N_I<2> ADDR_N_I<1> ADDR_N_I<0> CS00<0> ECLK_I ++ ECLK_H<1> ECLK_B<0> ECLK_B<1> WL_O<15> WL_O<14> WL_O<13> WL_O<12> WL_O<11> ++ WL_O<10> WL_O<9> WL_O<8> WL_O<7> WL_O<6> WL_O<5> WL_O<4> WL_O<3> WL_O<2> ++ WL_O<1> WL_O<0> VDD VSS / RM_IHPSG13_256x32_c2_1P_DEC04 +XL2<24> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<23> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<22> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<21> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<20> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<19> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<18> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<17> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<16> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<15> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<14> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<13> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<12> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<11> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<10> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<9> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<8> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<7> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<6> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<5> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<4> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<3> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<2> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<1> VDD VSS / RSC_IHPSG13_FILLCAP8 +.ENDS +.SUBCKT RM_IHPSG13_256x32_c2_1P_ROWREG6 ACLK_N_I ADDR_I<5> ADDR_I<4> ADDR_I<3> ADDR_I<2> ++ ADDR_I<1> ADDR_I<0> ADDR_N_O<5> ADDR_N_O<4> ADDR_N_O<3> ADDR_N_O<2> ++ ADDR_N_O<1> ADDR_N_O<0> BIST_ADDR_I<5> BIST_ADDR_I<4> BIST_ADDR_I<3> ++ BIST_ADDR_I<2> BIST_ADDR_I<1> BIST_ADDR_I<0> BIST_EN_I VDD VSS +XINV<5> q_int<5> qn_int<5> VDD VSS / RSC_IHPSG13_CINVX2 +XINV<4> q_int<4> qn_int<4> VDD VSS / RSC_IHPSG13_CINVX2 +XINV<3> q_int<3> qn_int<3> VDD VSS / RSC_IHPSG13_CINVX2 +XINV<2> q_int<2> qn_int<2> VDD VSS / RSC_IHPSG13_CINVX2 +XINV<1> q_int<1> qn_int<1> VDD VSS / RSC_IHPSG13_CINVX2 +XINV<0> q_int<0> qn_int<0> VDD VSS / RSC_IHPSG13_CINVX2 +XDRV<5> qn_int<5> ADDR_N_O<5> VDD VSS / RSC_IHPSG13_CINVX8 +XDRV<4> qn_int<4> ADDR_N_O<4> VDD VSS / RSC_IHPSG13_CINVX8 +XDRV<3> qn_int<3> ADDR_N_O<3> VDD VSS / RSC_IHPSG13_CINVX8 +XDRV<2> qn_int<2> ADDR_N_O<2> VDD VSS / RSC_IHPSG13_CINVX8 +XDRV<1> qn_int<1> ADDR_N_O<1> VDD VSS / RSC_IHPSG13_CINVX8 +XDRV<0> qn_int<0> ADDR_N_O<0> VDD VSS / RSC_IHPSG13_CINVX8 +XDFF<5> BIST_EN_I BIST_ADDR_I<5> ACLK_N_I ADDR_I<5> q_int<5> net2<0> VDD ++ VSS / RSC_IHPSG13_DFNQMX2IX1 +XDFF<4> BIST_EN_I BIST_ADDR_I<4> ACLK_N_I ADDR_I<4> q_int<4> net2<1> VDD ++ VSS / RSC_IHPSG13_DFNQMX2IX1 +XDFF<3> BIST_EN_I BIST_ADDR_I<3> ACLK_N_I ADDR_I<3> q_int<3> net2<2> VDD ++ VSS / RSC_IHPSG13_DFNQMX2IX1 +XDFF<2> BIST_EN_I BIST_ADDR_I<2> ACLK_N_I ADDR_I<2> q_int<2> net2<3> VDD ++ VSS / RSC_IHPSG13_DFNQMX2IX1 +XDFF<1> BIST_EN_I BIST_ADDR_I<1> ACLK_N_I ADDR_I<1> q_int<1> net2<4> VDD ++ VSS / RSC_IHPSG13_DFNQMX2IX1 +XDFF<0> BIST_EN_I BIST_ADDR_I<0> ACLK_N_I ADDR_I<0> q_int<0> net2<5> VDD ++ VSS / RSC_IHPSG13_DFNQMX2IX1 +XI11<12> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI11<11> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI11<10> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI11<9> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI11<8> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI11<7> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI11<6> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI11<5> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI11<4> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI11<3> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI11<2> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI11<1> VDD VSS / RSC_IHPSG13_FILLCAP8 +.ENDS + + +.SUBCKT RM_IHPSG13_256x32_c2_1P_COLUMN_pcell_0 A_BLC_BOT<1> A_BLC_BOT<0> A_BLC_TOP<1> A_BLC_TOP<0> A_BLT_BOT<1> A_BLT_BOT<0> A_BLT_TOP<1> A_BLT_TOP<0> A_LWL<63> A_LWL<62> A_LWL<61> A_LWL<60> A_LWL<59> A_LWL<58> A_LWL<57> A_LWL<56> A_LWL<55> A_LWL<54> A_LWL<53> A_LWL<52> A_LWL<51> A_LWL<50> A_LWL<49> A_LWL<48> A_LWL<47> A_LWL<46> A_LWL<45> A_LWL<44> A_LWL<43> A_LWL<42> A_LWL<41> A_LWL<40> A_LWL<39> A_LWL<38> A_LWL<37> A_LWL<36> A_LWL<35> A_LWL<34> A_LWL<33> A_LWL<32> A_LWL<31> A_LWL<30> A_LWL<29> A_LWL<28> A_LWL<27> A_LWL<26> A_LWL<25> A_LWL<24> A_LWL<23> A_LWL<22> A_LWL<21> A_LWL<20> A_LWL<19> A_LWL<18> A_LWL<17> A_LWL<16> A_LWL<15> A_LWL<14> A_LWL<13> A_LWL<12> A_LWL<11> A_LWL<10> A_LWL<9> A_LWL<8> A_LWL<7> A_LWL<6> A_LWL<5> A_LWL<4> A_LWL<3> A_LWL<2> A_LWL<1> A_LWL<0> A_RWL<63> A_RWL<62> A_RWL<61> A_RWL<60> A_RWL<59> A_RWL<58> A_RWL<57> A_RWL<56> A_RWL<55> A_RWL<54> A_RWL<53> A_RWL<52> A_RWL<51> A_RWL<50> A_RWL<49> A_RWL<48> A_RWL<47> A_RWL<46> A_RWL<45> A_RWL<44> A_RWL<43> A_RWL<42> A_RWL<41> A_RWL<40> A_RWL<39> A_RWL<38> A_RWL<37> A_RWL<36> A_RWL<35> A_RWL<34> A_RWL<33> A_RWL<32> A_RWL<31> A_RWL<30> A_RWL<29> A_RWL<28> A_RWL<27> A_RWL<26> A_RWL<25> A_RWL<24> A_RWL<23> A_RWL<22> A_RWL<21> A_RWL<20> A_RWL<19> A_RWL<18> A_RWL<17> A_RWL<16> A_RWL<15> A_RWL<14> A_RWL<13> A_RWL<12> A_RWL<11> A_RWL<10> A_RWL<9> A_RWL<8> A_RWL<7> A_RWL<6> A_RWL<5> A_RWL<4> A_RWL<3> A_RWL<2> A_RWL<1> A_RWL<0> VDD_CORE VSS +XRAM<4> A_BLC<5> A_BLC<4> A_BLC_TOP<1> A_BLC_TOP<0> A_BLT<5> A_BLT<4> A_BLT_TOP<1> A_BLT_TOP<0> A_LWL<63> A_LWL<62> A_LWL<61> A_LWL<60> A_LWL<59> A_LWL<58> A_LWL<57> A_LWL<56> A_LWL<55> A_LWL<54> A_LWL<53> A_LWL<52> A_LWL<51> A_LWL<50> A_LWL<49> A_LWL<48> A_RWL<63> A_RWL<62> A_RWL<61> A_RWL<60> A_RWL<59> A_RWL<58> A_RWL<57> A_RWL<56> A_RWL<55> A_RWL<54> A_RWL<53> A_RWL<52> A_RWL<51> A_RWL<50> A_RWL<49> A_RWL<48> VDD_CORE VSS / RM_IHPSG13_256x32_c2_1P_BITKIT_16x2_SRAM +XRAM<3> A_BLC<3> A_BLC<2> A_BLC<5> A_BLC<4> A_BLT<3> A_BLT<2> A_BLT<5> A_BLT<4> A_LWL<47> A_LWL<46> A_LWL<45> A_LWL<44> A_LWL<43> A_LWL<42> A_LWL<41> A_LWL<40> A_LWL<39> A_LWL<38> A_LWL<37> A_LWL<36> A_LWL<35> A_LWL<34> A_LWL<33> A_LWL<32> A_RWL<47> A_RWL<46> A_RWL<45> A_RWL<44> A_RWL<43> A_RWL<42> A_RWL<41> A_RWL<40> A_RWL<39> A_RWL<38> A_RWL<37> A_RWL<36> A_RWL<35> A_RWL<34> A_RWL<33> A_RWL<32> VDD_CORE VSS / RM_IHPSG13_256x32_c2_1P_BITKIT_16x2_SRAM +XRAM<2> A_BLC<1> A_BLC<0> A_BLC<3> A_BLC<2> A_BLT<1> A_BLT<0> A_BLT<3> A_BLT<2> A_LWL<31> A_LWL<30> A_LWL<29> A_LWL<28> A_LWL<27> A_LWL<26> A_LWL<25> A_LWL<24> A_LWL<23> A_LWL<22> A_LWL<21> A_LWL<20> A_LWL<19> A_LWL<18> A_LWL<17> A_LWL<16> A_RWL<31> A_RWL<30> A_RWL<29> A_RWL<28> A_RWL<27> A_RWL<26> A_RWL<25> A_RWL<24> A_RWL<23> A_RWL<22> A_RWL<21> A_RWL<20> A_RWL<19> A_RWL<18> A_RWL<17> A_RWL<16> VDD_CORE VSS / RM_IHPSG13_256x32_c2_1P_BITKIT_16x2_SRAM +XRAM<1> A_BLC_BOT<1> A_BLC_BOT<0> A_BLC<1> A_BLC<0> A_BLT_BOT<1> A_BLT_BOT<0> A_BLT<1> A_BLT<0> A_LWL<15> A_LWL<14> A_LWL<13> A_LWL<12> A_LWL<11> A_LWL<10> A_LWL<9> A_LWL<8> A_LWL<7> A_LWL<6> A_LWL<5> A_LWL<4> A_LWL<3> A_LWL<2> A_LWL<1> A_LWL<0> A_RWL<15> A_RWL<14> A_RWL<13> A_RWL<12> A_RWL<11> A_RWL<10> A_RWL<9> A_RWL<8> A_RWL<7> A_RWL<6> A_RWL<5> A_RWL<4> A_RWL<3> A_RWL<2> A_RWL<1> A_RWL<0> VDD_CORE VSS / RM_IHPSG13_256x32_c2_1P_BITKIT_16x2_SRAM +XEDGE<1> A_BLC_TOP<1> A_BLC_TOP<0> A_BLT_TOP<1> A_BLT_TOP<0> VDD_CORE VSS / RM_IHPSG13_256x32_c2_1P_BITKIT_16x2_EDGE_TB +XEDGE<0> A_BLC_BOT<1> A_BLC_BOT<0> A_BLT_BOT<1> A_BLT_BOT<0> VDD_CORE VSS / RM_IHPSG13_256x32_c2_1P_BITKIT_16x2_EDGE_TB +.ENDS + + + + +.SUBCKT RM_IHPSG13_256x32_c2_1P_MATRIX_pcell_1 A_BLC<63> A_BLC<62> A_BLC<61> A_BLC<60> A_BLC<59> A_BLC<58> A_BLC<57> A_BLC<56> A_BLC<55> A_BLC<54> A_BLC<53> A_BLC<52> A_BLC<51> A_BLC<50> A_BLC<49> A_BLC<48> A_BLC<47> A_BLC<46> A_BLC<45> A_BLC<44> A_BLC<43> A_BLC<42> A_BLC<41> A_BLC<40> A_BLC<39> A_BLC<38> A_BLC<37> A_BLC<36> A_BLC<35> A_BLC<34> A_BLC<33> A_BLC<32> A_BLC<31> A_BLC<30> A_BLC<29> A_BLC<28> A_BLC<27> A_BLC<26> A_BLC<25> A_BLC<24> A_BLC<23> A_BLC<22> A_BLC<21> A_BLC<20> A_BLC<19> A_BLC<18> A_BLC<17> A_BLC<16> A_BLC<15> A_BLC<14> A_BLC<13> A_BLC<12> A_BLC<11> A_BLC<10> A_BLC<9> A_BLC<8> A_BLC<7> A_BLC<6> A_BLC<5> A_BLC<4> A_BLC<3> A_BLC<2> A_BLC<1> A_BLC<0> A_BLT<63> A_BLT<62> A_BLT<61> A_BLT<60> A_BLT<59> A_BLT<58> A_BLT<57> A_BLT<56> A_BLT<55> A_BLT<54> A_BLT<53> A_BLT<52> A_BLT<51> A_BLT<50> A_BLT<49> A_BLT<48> A_BLT<47> A_BLT<46> A_BLT<45> A_BLT<44> A_BLT<43> A_BLT<42> A_BLT<41> A_BLT<40> A_BLT<39> A_BLT<38> A_BLT<37> A_BLT<36> A_BLT<35> A_BLT<34> A_BLT<33> A_BLT<32> A_BLT<31> A_BLT<30> A_BLT<29> A_BLT<28> A_BLT<27> A_BLT<26> A_BLT<25> A_BLT<24> A_BLT<23> A_BLT<22> A_BLT<21> A_BLT<20> A_BLT<19> A_BLT<18> A_BLT<17> A_BLT<16> A_BLT<15> A_BLT<14> A_BLT<13> A_BLT<12> A_BLT<11> A_BLT<10> A_BLT<9> A_BLT<8> A_BLT<7> A_BLT<6> A_BLT<5> A_BLT<4> A_BLT<3> A_BLT<2> A_BLT<1> A_BLT<0> A_WL<63> A_WL<62> A_WL<61> A_WL<60> A_WL<59> A_WL<58> A_WL<57> A_WL<56> A_WL<55> A_WL<54> A_WL<53> A_WL<52> A_WL<51> A_WL<50> A_WL<49> A_WL<48> A_WL<47> A_WL<46> A_WL<45> A_WL<44> A_WL<43> A_WL<42> A_WL<41> A_WL<40> A_WL<39> A_WL<38> A_WL<37> A_WL<36> A_WL<35> A_WL<34> A_WL<33> A_WL<32> A_WL<31> A_WL<30> A_WL<29> A_WL<28> A_WL<27> A_WL<26> A_WL<25> A_WL<24> A_WL<23> A_WL<22> A_WL<21> A_WL<20> A_WL<19> A_WL<18> A_WL<17> A_WL<16> A_WL<15> A_WL<14> A_WL<13> A_WL<12> A_WL<11> A_WL<10> A_WL<9> A_WL<8> A_WL<7> A_WL<6> A_WL<5> A_WL<4> A_WL<3> A_WL<2> A_WL<1> A_WL<0> VDD_CORE VSS +XCORNER<3> VDD_CORE VSS / RM_IHPSG13_256x32_c2_1P_BITKIT_16x2_CORNER +XCORNER<2> VDD_CORE VSS / RM_IHPSG13_256x32_c2_1P_BITKIT_16x2_CORNER +XCORNER<1> VDD_CORE VSS / RM_IHPSG13_256x32_c2_1P_BITKIT_16x2_CORNER +XCORNER<0> VDD_CORE VSS / RM_IHPSG13_256x32_c2_1P_BITKIT_16x2_CORNER +XRAMEDGE_L<3> A_WL<63> A_WL<62> A_WL<61> A_WL<60> A_WL<59> A_WL<58> A_WL<57> A_WL<56> A_WL<55> A_WL<54> A_WL<53> A_WL<52> A_WL<51> A_WL<50> A_WL<49> A_WL<48> VDD_CORE VSS / RM_IHPSG13_256x32_c2_1P_BITKIT_16x2_EDGE_LR +XRAMEDGE_L<2> A_WL<47> A_WL<46> A_WL<45> A_WL<44> A_WL<43> A_WL<42> A_WL<41> A_WL<40> A_WL<39> A_WL<38> A_WL<37> A_WL<36> A_WL<35> A_WL<34> A_WL<33> A_WL<32> VDD_CORE VSS / RM_IHPSG13_256x32_c2_1P_BITKIT_16x2_EDGE_LR +XRAMEDGE_L<1> A_WL<31> A_WL<30> A_WL<29> A_WL<28> A_WL<27> A_WL<26> A_WL<25> A_WL<24> A_WL<23> A_WL<22> A_WL<21> A_WL<20> A_WL<19> A_WL<18> A_WL<17> A_WL<16> VDD_CORE VSS / RM_IHPSG13_256x32_c2_1P_BITKIT_16x2_EDGE_LR +XRAMEDGE_L<0> A_WL<15> A_WL<14> A_WL<13> A_WL<12> A_WL<11> A_WL<10> A_WL<9> A_WL<8> A_WL<7> A_WL<6> A_WL<5> A_WL<4> A_WL<3> A_WL<2> A_WL<1> A_WL<0> VDD_CORE VSS / RM_IHPSG13_256x32_c2_1P_BITKIT_16x2_EDGE_LR +XRAMEDGE_R<3> A_IWL<2047> A_IWL<2046> A_IWL<2045> A_IWL<2044> A_IWL<2043> A_IWL<2042> A_IWL<2041> A_IWL<2040> A_IWL<2039> A_IWL<2038> A_IWL<2037> A_IWL<2036> A_IWL<2035> A_IWL<2034> A_IWL<2033> A_IWL<2032> VDD_CORE VSS / RM_IHPSG13_256x32_c2_1P_BITKIT_16x2_EDGE_LR +XRAMEDGE_R<2> A_IWL<2031> A_IWL<2030> A_IWL<2029> A_IWL<2028> A_IWL<2027> A_IWL<2026> A_IWL<2025> A_IWL<2024> A_IWL<2023> A_IWL<2022> A_IWL<2021> A_IWL<2020> A_IWL<2019> A_IWL<2018> A_IWL<2017> A_IWL<2016> VDD_CORE VSS / RM_IHPSG13_256x32_c2_1P_BITKIT_16x2_EDGE_LR +XRAMEDGE_R<1> A_IWL<2015> A_IWL<2014> A_IWL<2013> A_IWL<2012> A_IWL<2011> A_IWL<2010> A_IWL<2009> A_IWL<2008> A_IWL<2007> A_IWL<2006> A_IWL<2005> A_IWL<2004> A_IWL<2003> A_IWL<2002> A_IWL<2001> A_IWL<2000> VDD_CORE VSS / RM_IHPSG13_256x32_c2_1P_BITKIT_16x2_EDGE_LR +XRAMEDGE_R<0> A_IWL<1999> A_IWL<1998> A_IWL<1997> A_IWL<1996> A_IWL<1995> A_IWL<1994> A_IWL<1993> A_IWL<1992> A_IWL<1991> A_IWL<1990> A_IWL<1989> A_IWL<1988> A_IWL<1987> A_IWL<1986> A_IWL<1985> A_IWL<1984> VDD_CORE VSS / RM_IHPSG13_256x32_c2_1P_BITKIT_16x2_EDGE_LR +XCOL<31> A_BLC<63> A_BLC<62> A_BLC_TOP<63> A_BLC_TOP<62> A_BLT<63> A_BLT<62> A_BLT_TOP<63> A_BLT_TOP<62> A_IWL<1983> A_IWL<1982> A_IWL<1981> A_IWL<1980> A_IWL<1979> A_IWL<1978> A_IWL<1977> A_IWL<1976> A_IWL<1975> A_IWL<1974> A_IWL<1973> A_IWL<1972> A_IWL<1971> A_IWL<1970> A_IWL<1969> A_IWL<1968> A_IWL<1967> A_IWL<1966> A_IWL<1965> A_IWL<1964> A_IWL<1963> A_IWL<1962> A_IWL<1961> A_IWL<1960> A_IWL<1959> A_IWL<1958> A_IWL<1957> A_IWL<1956> A_IWL<1955> A_IWL<1954> A_IWL<1953> A_IWL<1952> A_IWL<1951> A_IWL<1950> A_IWL<1949> A_IWL<1948> A_IWL<1947> A_IWL<1946> A_IWL<1945> A_IWL<1944> A_IWL<1943> A_IWL<1942> A_IWL<1941> A_IWL<1940> A_IWL<1939> A_IWL<1938> A_IWL<1937> A_IWL<1936> A_IWL<1935> A_IWL<1934> A_IWL<1933> A_IWL<1932> A_IWL<1931> A_IWL<1930> A_IWL<1929> A_IWL<1928> A_IWL<1927> A_IWL<1926> A_IWL<1925> A_IWL<1924> A_IWL<1923> A_IWL<1922> A_IWL<1921> A_IWL<1920> A_IWL<2047> A_IWL<2046> A_IWL<2045> A_IWL<2044> A_IWL<2043> A_IWL<2042> A_IWL<2041> A_IWL<2040> A_IWL<2039> A_IWL<2038> A_IWL<2037> A_IWL<2036> A_IWL<2035> A_IWL<2034> A_IWL<2033> A_IWL<2032> A_IWL<2031> A_IWL<2030> A_IWL<2029> A_IWL<2028> A_IWL<2027> A_IWL<2026> A_IWL<2025> A_IWL<2024> A_IWL<2023> A_IWL<2022> A_IWL<2021> A_IWL<2020> A_IWL<2019> A_IWL<2018> A_IWL<2017> A_IWL<2016> A_IWL<2015> A_IWL<2014> A_IWL<2013> A_IWL<2012> A_IWL<2011> A_IWL<2010> A_IWL<2009> A_IWL<2008> A_IWL<2007> A_IWL<2006> A_IWL<2005> A_IWL<2004> A_IWL<2003> A_IWL<2002> A_IWL<2001> A_IWL<2000> A_IWL<1999> A_IWL<1998> A_IWL<1997> A_IWL<1996> A_IWL<1995> A_IWL<1994> A_IWL<1993> A_IWL<1992> A_IWL<1991> A_IWL<1990> A_IWL<1989> A_IWL<1988> A_IWL<1987> A_IWL<1986> A_IWL<1985> A_IWL<1984> VDD_CORE VSS / RM_IHPSG13_256x32_c2_1P_COLUMN_pcell_0 +XCOL<30> A_BLC<61> A_BLC<60> A_BLC_TOP<61> A_BLC_TOP<60> A_BLT<61> A_BLT<60> A_BLT_TOP<61> A_BLT_TOP<60> A_IWL<1919> A_IWL<1918> A_IWL<1917> A_IWL<1916> A_IWL<1915> A_IWL<1914> A_IWL<1913> A_IWL<1912> A_IWL<1911> A_IWL<1910> A_IWL<1909> A_IWL<1908> A_IWL<1907> A_IWL<1906> A_IWL<1905> A_IWL<1904> A_IWL<1903> A_IWL<1902> A_IWL<1901> A_IWL<1900> A_IWL<1899> A_IWL<1898> A_IWL<1897> A_IWL<1896> A_IWL<1895> A_IWL<1894> A_IWL<1893> A_IWL<1892> A_IWL<1891> A_IWL<1890> A_IWL<1889> A_IWL<1888> A_IWL<1887> A_IWL<1886> A_IWL<1885> A_IWL<1884> A_IWL<1883> A_IWL<1882> A_IWL<1881> A_IWL<1880> A_IWL<1879> A_IWL<1878> A_IWL<1877> A_IWL<1876> A_IWL<1875> A_IWL<1874> A_IWL<1873> A_IWL<1872> A_IWL<1871> A_IWL<1870> A_IWL<1869> A_IWL<1868> A_IWL<1867> A_IWL<1866> A_IWL<1865> A_IWL<1864> A_IWL<1863> A_IWL<1862> A_IWL<1861> A_IWL<1860> A_IWL<1859> A_IWL<1858> A_IWL<1857> A_IWL<1856> A_IWL<1983> A_IWL<1982> A_IWL<1981> A_IWL<1980> A_IWL<1979> A_IWL<1978> A_IWL<1977> A_IWL<1976> A_IWL<1975> A_IWL<1974> A_IWL<1973> A_IWL<1972> A_IWL<1971> A_IWL<1970> A_IWL<1969> A_IWL<1968> A_IWL<1967> A_IWL<1966> A_IWL<1965> A_IWL<1964> A_IWL<1963> A_IWL<1962> A_IWL<1961> A_IWL<1960> A_IWL<1959> A_IWL<1958> A_IWL<1957> A_IWL<1956> A_IWL<1955> A_IWL<1954> A_IWL<1953> A_IWL<1952> A_IWL<1951> A_IWL<1950> A_IWL<1949> A_IWL<1948> A_IWL<1947> A_IWL<1946> A_IWL<1945> A_IWL<1944> A_IWL<1943> A_IWL<1942> A_IWL<1941> A_IWL<1940> A_IWL<1939> A_IWL<1938> A_IWL<1937> A_IWL<1936> A_IWL<1935> A_IWL<1934> A_IWL<1933> A_IWL<1932> A_IWL<1931> A_IWL<1930> A_IWL<1929> A_IWL<1928> A_IWL<1927> A_IWL<1926> A_IWL<1925> A_IWL<1924> A_IWL<1923> A_IWL<1922> A_IWL<1921> A_IWL<1920> VDD_CORE VSS / RM_IHPSG13_256x32_c2_1P_COLUMN_pcell_0 +XCOL<29> A_BLC<59> A_BLC<58> A_BLC_TOP<59> A_BLC_TOP<58> A_BLT<59> A_BLT<58> A_BLT_TOP<59> A_BLT_TOP<58> A_IWL<1855> A_IWL<1854> A_IWL<1853> A_IWL<1852> A_IWL<1851> A_IWL<1850> A_IWL<1849> A_IWL<1848> A_IWL<1847> A_IWL<1846> A_IWL<1845> A_IWL<1844> A_IWL<1843> A_IWL<1842> A_IWL<1841> A_IWL<1840> A_IWL<1839> A_IWL<1838> A_IWL<1837> A_IWL<1836> A_IWL<1835> A_IWL<1834> A_IWL<1833> A_IWL<1832> A_IWL<1831> A_IWL<1830> A_IWL<1829> A_IWL<1828> A_IWL<1827> A_IWL<1826> A_IWL<1825> A_IWL<1824> A_IWL<1823> A_IWL<1822> A_IWL<1821> A_IWL<1820> A_IWL<1819> A_IWL<1818> A_IWL<1817> A_IWL<1816> A_IWL<1815> A_IWL<1814> A_IWL<1813> A_IWL<1812> A_IWL<1811> A_IWL<1810> A_IWL<1809> A_IWL<1808> A_IWL<1807> A_IWL<1806> A_IWL<1805> A_IWL<1804> A_IWL<1803> A_IWL<1802> A_IWL<1801> A_IWL<1800> A_IWL<1799> A_IWL<1798> A_IWL<1797> A_IWL<1796> A_IWL<1795> A_IWL<1794> A_IWL<1793> A_IWL<1792> A_IWL<1919> A_IWL<1918> A_IWL<1917> A_IWL<1916> A_IWL<1915> A_IWL<1914> A_IWL<1913> A_IWL<1912> A_IWL<1911> A_IWL<1910> A_IWL<1909> A_IWL<1908> A_IWL<1907> A_IWL<1906> A_IWL<1905> A_IWL<1904> A_IWL<1903> A_IWL<1902> A_IWL<1901> A_IWL<1900> A_IWL<1899> A_IWL<1898> A_IWL<1897> A_IWL<1896> A_IWL<1895> A_IWL<1894> A_IWL<1893> A_IWL<1892> A_IWL<1891> A_IWL<1890> A_IWL<1889> A_IWL<1888> A_IWL<1887> A_IWL<1886> A_IWL<1885> A_IWL<1884> A_IWL<1883> A_IWL<1882> A_IWL<1881> A_IWL<1880> A_IWL<1879> A_IWL<1878> A_IWL<1877> A_IWL<1876> A_IWL<1875> A_IWL<1874> A_IWL<1873> A_IWL<1872> A_IWL<1871> A_IWL<1870> A_IWL<1869> A_IWL<1868> A_IWL<1867> A_IWL<1866> A_IWL<1865> A_IWL<1864> A_IWL<1863> A_IWL<1862> A_IWL<1861> A_IWL<1860> A_IWL<1859> A_IWL<1858> A_IWL<1857> A_IWL<1856> VDD_CORE VSS / RM_IHPSG13_256x32_c2_1P_COLUMN_pcell_0 +XCOL<28> A_BLC<57> A_BLC<56> A_BLC_TOP<57> A_BLC_TOP<56> A_BLT<57> A_BLT<56> A_BLT_TOP<57> A_BLT_TOP<56> A_IWL<1791> A_IWL<1790> A_IWL<1789> A_IWL<1788> A_IWL<1787> A_IWL<1786> A_IWL<1785> A_IWL<1784> A_IWL<1783> A_IWL<1782> A_IWL<1781> A_IWL<1780> A_IWL<1779> A_IWL<1778> A_IWL<1777> A_IWL<1776> A_IWL<1775> A_IWL<1774> A_IWL<1773> A_IWL<1772> A_IWL<1771> A_IWL<1770> A_IWL<1769> A_IWL<1768> A_IWL<1767> A_IWL<1766> A_IWL<1765> A_IWL<1764> A_IWL<1763> A_IWL<1762> A_IWL<1761> A_IWL<1760> A_IWL<1759> A_IWL<1758> A_IWL<1757> A_IWL<1756> A_IWL<1755> A_IWL<1754> A_IWL<1753> A_IWL<1752> A_IWL<1751> A_IWL<1750> A_IWL<1749> A_IWL<1748> A_IWL<1747> A_IWL<1746> A_IWL<1745> A_IWL<1744> A_IWL<1743> A_IWL<1742> A_IWL<1741> A_IWL<1740> A_IWL<1739> A_IWL<1738> A_IWL<1737> A_IWL<1736> A_IWL<1735> A_IWL<1734> A_IWL<1733> A_IWL<1732> A_IWL<1731> A_IWL<1730> A_IWL<1729> A_IWL<1728> A_IWL<1855> A_IWL<1854> A_IWL<1853> A_IWL<1852> A_IWL<1851> A_IWL<1850> A_IWL<1849> A_IWL<1848> A_IWL<1847> A_IWL<1846> A_IWL<1845> A_IWL<1844> A_IWL<1843> A_IWL<1842> A_IWL<1841> A_IWL<1840> A_IWL<1839> A_IWL<1838> A_IWL<1837> A_IWL<1836> A_IWL<1835> A_IWL<1834> A_IWL<1833> A_IWL<1832> A_IWL<1831> A_IWL<1830> A_IWL<1829> A_IWL<1828> A_IWL<1827> A_IWL<1826> A_IWL<1825> A_IWL<1824> A_IWL<1823> A_IWL<1822> A_IWL<1821> A_IWL<1820> A_IWL<1819> A_IWL<1818> A_IWL<1817> A_IWL<1816> A_IWL<1815> A_IWL<1814> A_IWL<1813> A_IWL<1812> A_IWL<1811> A_IWL<1810> A_IWL<1809> A_IWL<1808> A_IWL<1807> A_IWL<1806> A_IWL<1805> A_IWL<1804> A_IWL<1803> A_IWL<1802> A_IWL<1801> A_IWL<1800> A_IWL<1799> A_IWL<1798> A_IWL<1797> A_IWL<1796> A_IWL<1795> A_IWL<1794> A_IWL<1793> A_IWL<1792> VDD_CORE VSS / RM_IHPSG13_256x32_c2_1P_COLUMN_pcell_0 +XCOL<27> A_BLC<55> A_BLC<54> A_BLC_TOP<55> A_BLC_TOP<54> A_BLT<55> A_BLT<54> A_BLT_TOP<55> A_BLT_TOP<54> A_IWL<1727> A_IWL<1726> A_IWL<1725> A_IWL<1724> A_IWL<1723> A_IWL<1722> A_IWL<1721> A_IWL<1720> A_IWL<1719> A_IWL<1718> A_IWL<1717> A_IWL<1716> A_IWL<1715> A_IWL<1714> A_IWL<1713> A_IWL<1712> A_IWL<1711> A_IWL<1710> A_IWL<1709> A_IWL<1708> A_IWL<1707> A_IWL<1706> A_IWL<1705> A_IWL<1704> A_IWL<1703> A_IWL<1702> A_IWL<1701> A_IWL<1700> A_IWL<1699> A_IWL<1698> A_IWL<1697> A_IWL<1696> A_IWL<1695> A_IWL<1694> A_IWL<1693> A_IWL<1692> A_IWL<1691> A_IWL<1690> A_IWL<1689> A_IWL<1688> A_IWL<1687> A_IWL<1686> A_IWL<1685> A_IWL<1684> A_IWL<1683> A_IWL<1682> A_IWL<1681> A_IWL<1680> A_IWL<1679> A_IWL<1678> A_IWL<1677> A_IWL<1676> A_IWL<1675> A_IWL<1674> A_IWL<1673> A_IWL<1672> A_IWL<1671> A_IWL<1670> A_IWL<1669> A_IWL<1668> A_IWL<1667> A_IWL<1666> A_IWL<1665> A_IWL<1664> A_IWL<1791> A_IWL<1790> A_IWL<1789> A_IWL<1788> A_IWL<1787> A_IWL<1786> A_IWL<1785> A_IWL<1784> A_IWL<1783> A_IWL<1782> A_IWL<1781> A_IWL<1780> A_IWL<1779> A_IWL<1778> A_IWL<1777> A_IWL<1776> A_IWL<1775> A_IWL<1774> A_IWL<1773> A_IWL<1772> A_IWL<1771> A_IWL<1770> A_IWL<1769> A_IWL<1768> A_IWL<1767> A_IWL<1766> A_IWL<1765> A_IWL<1764> A_IWL<1763> A_IWL<1762> A_IWL<1761> A_IWL<1760> A_IWL<1759> A_IWL<1758> A_IWL<1757> A_IWL<1756> A_IWL<1755> A_IWL<1754> A_IWL<1753> A_IWL<1752> A_IWL<1751> A_IWL<1750> A_IWL<1749> A_IWL<1748> A_IWL<1747> A_IWL<1746> A_IWL<1745> A_IWL<1744> A_IWL<1743> A_IWL<1742> A_IWL<1741> A_IWL<1740> A_IWL<1739> A_IWL<1738> A_IWL<1737> A_IWL<1736> A_IWL<1735> A_IWL<1734> A_IWL<1733> A_IWL<1732> A_IWL<1731> A_IWL<1730> A_IWL<1729> A_IWL<1728> VDD_CORE VSS / RM_IHPSG13_256x32_c2_1P_COLUMN_pcell_0 +XCOL<26> A_BLC<53> A_BLC<52> A_BLC_TOP<53> A_BLC_TOP<52> A_BLT<53> A_BLT<52> A_BLT_TOP<53> A_BLT_TOP<52> A_IWL<1663> A_IWL<1662> A_IWL<1661> A_IWL<1660> A_IWL<1659> A_IWL<1658> A_IWL<1657> A_IWL<1656> A_IWL<1655> A_IWL<1654> A_IWL<1653> A_IWL<1652> A_IWL<1651> A_IWL<1650> A_IWL<1649> A_IWL<1648> A_IWL<1647> A_IWL<1646> A_IWL<1645> A_IWL<1644> A_IWL<1643> A_IWL<1642> A_IWL<1641> A_IWL<1640> A_IWL<1639> A_IWL<1638> A_IWL<1637> A_IWL<1636> A_IWL<1635> A_IWL<1634> A_IWL<1633> A_IWL<1632> A_IWL<1631> A_IWL<1630> A_IWL<1629> A_IWL<1628> A_IWL<1627> A_IWL<1626> A_IWL<1625> A_IWL<1624> A_IWL<1623> A_IWL<1622> A_IWL<1621> A_IWL<1620> A_IWL<1619> A_IWL<1618> A_IWL<1617> A_IWL<1616> A_IWL<1615> A_IWL<1614> A_IWL<1613> A_IWL<1612> A_IWL<1611> A_IWL<1610> A_IWL<1609> A_IWL<1608> A_IWL<1607> A_IWL<1606> A_IWL<1605> A_IWL<1604> A_IWL<1603> A_IWL<1602> A_IWL<1601> A_IWL<1600> A_IWL<1727> A_IWL<1726> A_IWL<1725> A_IWL<1724> A_IWL<1723> A_IWL<1722> A_IWL<1721> A_IWL<1720> A_IWL<1719> A_IWL<1718> A_IWL<1717> A_IWL<1716> A_IWL<1715> A_IWL<1714> A_IWL<1713> A_IWL<1712> A_IWL<1711> A_IWL<1710> A_IWL<1709> A_IWL<1708> A_IWL<1707> A_IWL<1706> A_IWL<1705> A_IWL<1704> A_IWL<1703> A_IWL<1702> A_IWL<1701> A_IWL<1700> A_IWL<1699> A_IWL<1698> A_IWL<1697> A_IWL<1696> A_IWL<1695> A_IWL<1694> A_IWL<1693> A_IWL<1692> A_IWL<1691> A_IWL<1690> A_IWL<1689> A_IWL<1688> A_IWL<1687> A_IWL<1686> A_IWL<1685> A_IWL<1684> A_IWL<1683> A_IWL<1682> A_IWL<1681> A_IWL<1680> A_IWL<1679> A_IWL<1678> A_IWL<1677> A_IWL<1676> A_IWL<1675> A_IWL<1674> A_IWL<1673> A_IWL<1672> A_IWL<1671> A_IWL<1670> A_IWL<1669> A_IWL<1668> A_IWL<1667> A_IWL<1666> A_IWL<1665> A_IWL<1664> VDD_CORE VSS / RM_IHPSG13_256x32_c2_1P_COLUMN_pcell_0 +XCOL<25> A_BLC<51> A_BLC<50> A_BLC_TOP<51> A_BLC_TOP<50> A_BLT<51> A_BLT<50> A_BLT_TOP<51> A_BLT_TOP<50> A_IWL<1599> A_IWL<1598> A_IWL<1597> A_IWL<1596> A_IWL<1595> A_IWL<1594> A_IWL<1593> A_IWL<1592> A_IWL<1591> A_IWL<1590> A_IWL<1589> A_IWL<1588> A_IWL<1587> A_IWL<1586> A_IWL<1585> A_IWL<1584> A_IWL<1583> A_IWL<1582> A_IWL<1581> A_IWL<1580> A_IWL<1579> A_IWL<1578> A_IWL<1577> A_IWL<1576> A_IWL<1575> A_IWL<1574> A_IWL<1573> A_IWL<1572> A_IWL<1571> A_IWL<1570> A_IWL<1569> A_IWL<1568> A_IWL<1567> A_IWL<1566> A_IWL<1565> A_IWL<1564> A_IWL<1563> A_IWL<1562> A_IWL<1561> A_IWL<1560> A_IWL<1559> A_IWL<1558> A_IWL<1557> A_IWL<1556> A_IWL<1555> A_IWL<1554> A_IWL<1553> A_IWL<1552> A_IWL<1551> A_IWL<1550> A_IWL<1549> A_IWL<1548> A_IWL<1547> A_IWL<1546> A_IWL<1545> A_IWL<1544> A_IWL<1543> A_IWL<1542> A_IWL<1541> A_IWL<1540> A_IWL<1539> A_IWL<1538> A_IWL<1537> A_IWL<1536> A_IWL<1663> A_IWL<1662> A_IWL<1661> A_IWL<1660> A_IWL<1659> A_IWL<1658> A_IWL<1657> A_IWL<1656> A_IWL<1655> A_IWL<1654> A_IWL<1653> A_IWL<1652> A_IWL<1651> A_IWL<1650> A_IWL<1649> A_IWL<1648> A_IWL<1647> A_IWL<1646> A_IWL<1645> A_IWL<1644> A_IWL<1643> A_IWL<1642> A_IWL<1641> A_IWL<1640> A_IWL<1639> A_IWL<1638> A_IWL<1637> A_IWL<1636> A_IWL<1635> A_IWL<1634> A_IWL<1633> A_IWL<1632> A_IWL<1631> A_IWL<1630> A_IWL<1629> A_IWL<1628> A_IWL<1627> A_IWL<1626> A_IWL<1625> A_IWL<1624> A_IWL<1623> A_IWL<1622> A_IWL<1621> A_IWL<1620> A_IWL<1619> A_IWL<1618> A_IWL<1617> A_IWL<1616> A_IWL<1615> A_IWL<1614> A_IWL<1613> A_IWL<1612> A_IWL<1611> A_IWL<1610> A_IWL<1609> A_IWL<1608> A_IWL<1607> A_IWL<1606> A_IWL<1605> A_IWL<1604> A_IWL<1603> A_IWL<1602> A_IWL<1601> A_IWL<1600> VDD_CORE VSS / RM_IHPSG13_256x32_c2_1P_COLUMN_pcell_0 +XCOL<24> A_BLC<49> A_BLC<48> A_BLC_TOP<49> A_BLC_TOP<48> A_BLT<49> A_BLT<48> A_BLT_TOP<49> A_BLT_TOP<48> A_IWL<1535> A_IWL<1534> A_IWL<1533> A_IWL<1532> A_IWL<1531> A_IWL<1530> A_IWL<1529> A_IWL<1528> A_IWL<1527> A_IWL<1526> A_IWL<1525> A_IWL<1524> A_IWL<1523> A_IWL<1522> A_IWL<1521> A_IWL<1520> A_IWL<1519> A_IWL<1518> A_IWL<1517> A_IWL<1516> A_IWL<1515> A_IWL<1514> A_IWL<1513> A_IWL<1512> A_IWL<1511> A_IWL<1510> A_IWL<1509> A_IWL<1508> A_IWL<1507> A_IWL<1506> A_IWL<1505> A_IWL<1504> A_IWL<1503> A_IWL<1502> A_IWL<1501> A_IWL<1500> A_IWL<1499> A_IWL<1498> A_IWL<1497> A_IWL<1496> A_IWL<1495> A_IWL<1494> A_IWL<1493> A_IWL<1492> A_IWL<1491> A_IWL<1490> A_IWL<1489> A_IWL<1488> A_IWL<1487> A_IWL<1486> A_IWL<1485> A_IWL<1484> A_IWL<1483> A_IWL<1482> A_IWL<1481> A_IWL<1480> A_IWL<1479> A_IWL<1478> A_IWL<1477> A_IWL<1476> A_IWL<1475> A_IWL<1474> A_IWL<1473> A_IWL<1472> A_IWL<1599> A_IWL<1598> A_IWL<1597> A_IWL<1596> A_IWL<1595> A_IWL<1594> A_IWL<1593> A_IWL<1592> A_IWL<1591> A_IWL<1590> A_IWL<1589> A_IWL<1588> A_IWL<1587> A_IWL<1586> A_IWL<1585> A_IWL<1584> A_IWL<1583> A_IWL<1582> A_IWL<1581> A_IWL<1580> A_IWL<1579> A_IWL<1578> A_IWL<1577> A_IWL<1576> A_IWL<1575> A_IWL<1574> A_IWL<1573> A_IWL<1572> A_IWL<1571> A_IWL<1570> A_IWL<1569> A_IWL<1568> A_IWL<1567> A_IWL<1566> A_IWL<1565> A_IWL<1564> A_IWL<1563> A_IWL<1562> A_IWL<1561> A_IWL<1560> A_IWL<1559> A_IWL<1558> A_IWL<1557> A_IWL<1556> A_IWL<1555> A_IWL<1554> A_IWL<1553> A_IWL<1552> A_IWL<1551> A_IWL<1550> A_IWL<1549> A_IWL<1548> A_IWL<1547> A_IWL<1546> A_IWL<1545> A_IWL<1544> A_IWL<1543> A_IWL<1542> A_IWL<1541> A_IWL<1540> A_IWL<1539> A_IWL<1538> A_IWL<1537> A_IWL<1536> VDD_CORE VSS / RM_IHPSG13_256x32_c2_1P_COLUMN_pcell_0 +XCOL<23> A_BLC<47> A_BLC<46> A_BLC_TOP<47> A_BLC_TOP<46> A_BLT<47> A_BLT<46> A_BLT_TOP<47> A_BLT_TOP<46> A_IWL<1471> A_IWL<1470> A_IWL<1469> A_IWL<1468> A_IWL<1467> A_IWL<1466> A_IWL<1465> A_IWL<1464> A_IWL<1463> A_IWL<1462> A_IWL<1461> A_IWL<1460> A_IWL<1459> A_IWL<1458> A_IWL<1457> A_IWL<1456> A_IWL<1455> A_IWL<1454> A_IWL<1453> A_IWL<1452> A_IWL<1451> A_IWL<1450> A_IWL<1449> A_IWL<1448> A_IWL<1447> A_IWL<1446> A_IWL<1445> A_IWL<1444> A_IWL<1443> A_IWL<1442> A_IWL<1441> A_IWL<1440> A_IWL<1439> A_IWL<1438> A_IWL<1437> A_IWL<1436> A_IWL<1435> A_IWL<1434> A_IWL<1433> A_IWL<1432> A_IWL<1431> A_IWL<1430> A_IWL<1429> A_IWL<1428> A_IWL<1427> A_IWL<1426> A_IWL<1425> A_IWL<1424> A_IWL<1423> A_IWL<1422> A_IWL<1421> A_IWL<1420> A_IWL<1419> A_IWL<1418> A_IWL<1417> A_IWL<1416> A_IWL<1415> A_IWL<1414> A_IWL<1413> A_IWL<1412> A_IWL<1411> A_IWL<1410> A_IWL<1409> A_IWL<1408> A_IWL<1535> A_IWL<1534> A_IWL<1533> A_IWL<1532> A_IWL<1531> A_IWL<1530> A_IWL<1529> A_IWL<1528> A_IWL<1527> A_IWL<1526> A_IWL<1525> A_IWL<1524> A_IWL<1523> A_IWL<1522> A_IWL<1521> A_IWL<1520> A_IWL<1519> A_IWL<1518> A_IWL<1517> A_IWL<1516> A_IWL<1515> A_IWL<1514> A_IWL<1513> A_IWL<1512> A_IWL<1511> A_IWL<1510> A_IWL<1509> A_IWL<1508> A_IWL<1507> A_IWL<1506> A_IWL<1505> A_IWL<1504> A_IWL<1503> A_IWL<1502> A_IWL<1501> A_IWL<1500> A_IWL<1499> A_IWL<1498> A_IWL<1497> A_IWL<1496> A_IWL<1495> A_IWL<1494> A_IWL<1493> A_IWL<1492> A_IWL<1491> A_IWL<1490> A_IWL<1489> A_IWL<1488> A_IWL<1487> A_IWL<1486> A_IWL<1485> A_IWL<1484> A_IWL<1483> A_IWL<1482> A_IWL<1481> A_IWL<1480> A_IWL<1479> A_IWL<1478> A_IWL<1477> A_IWL<1476> A_IWL<1475> A_IWL<1474> A_IWL<1473> A_IWL<1472> VDD_CORE VSS / RM_IHPSG13_256x32_c2_1P_COLUMN_pcell_0 +XCOL<22> A_BLC<45> A_BLC<44> A_BLC_TOP<45> A_BLC_TOP<44> A_BLT<45> A_BLT<44> A_BLT_TOP<45> A_BLT_TOP<44> A_IWL<1407> A_IWL<1406> A_IWL<1405> A_IWL<1404> A_IWL<1403> A_IWL<1402> A_IWL<1401> A_IWL<1400> A_IWL<1399> A_IWL<1398> A_IWL<1397> A_IWL<1396> A_IWL<1395> A_IWL<1394> A_IWL<1393> A_IWL<1392> A_IWL<1391> A_IWL<1390> A_IWL<1389> A_IWL<1388> A_IWL<1387> A_IWL<1386> A_IWL<1385> A_IWL<1384> A_IWL<1383> A_IWL<1382> A_IWL<1381> A_IWL<1380> A_IWL<1379> A_IWL<1378> A_IWL<1377> A_IWL<1376> A_IWL<1375> A_IWL<1374> A_IWL<1373> A_IWL<1372> A_IWL<1371> A_IWL<1370> A_IWL<1369> A_IWL<1368> A_IWL<1367> A_IWL<1366> A_IWL<1365> A_IWL<1364> A_IWL<1363> A_IWL<1362> A_IWL<1361> A_IWL<1360> A_IWL<1359> A_IWL<1358> A_IWL<1357> A_IWL<1356> A_IWL<1355> A_IWL<1354> A_IWL<1353> A_IWL<1352> A_IWL<1351> A_IWL<1350> A_IWL<1349> A_IWL<1348> A_IWL<1347> A_IWL<1346> A_IWL<1345> A_IWL<1344> A_IWL<1471> A_IWL<1470> A_IWL<1469> A_IWL<1468> A_IWL<1467> A_IWL<1466> A_IWL<1465> A_IWL<1464> A_IWL<1463> A_IWL<1462> A_IWL<1461> A_IWL<1460> A_IWL<1459> A_IWL<1458> A_IWL<1457> A_IWL<1456> A_IWL<1455> A_IWL<1454> A_IWL<1453> A_IWL<1452> A_IWL<1451> A_IWL<1450> A_IWL<1449> A_IWL<1448> A_IWL<1447> A_IWL<1446> A_IWL<1445> A_IWL<1444> A_IWL<1443> A_IWL<1442> A_IWL<1441> A_IWL<1440> A_IWL<1439> A_IWL<1438> A_IWL<1437> A_IWL<1436> A_IWL<1435> A_IWL<1434> A_IWL<1433> A_IWL<1432> A_IWL<1431> A_IWL<1430> A_IWL<1429> A_IWL<1428> A_IWL<1427> A_IWL<1426> A_IWL<1425> A_IWL<1424> A_IWL<1423> A_IWL<1422> A_IWL<1421> A_IWL<1420> A_IWL<1419> A_IWL<1418> A_IWL<1417> A_IWL<1416> A_IWL<1415> A_IWL<1414> A_IWL<1413> A_IWL<1412> A_IWL<1411> A_IWL<1410> A_IWL<1409> A_IWL<1408> VDD_CORE VSS / RM_IHPSG13_256x32_c2_1P_COLUMN_pcell_0 +XCOL<21> A_BLC<43> A_BLC<42> A_BLC_TOP<43> A_BLC_TOP<42> A_BLT<43> A_BLT<42> A_BLT_TOP<43> A_BLT_TOP<42> A_IWL<1343> A_IWL<1342> A_IWL<1341> A_IWL<1340> A_IWL<1339> A_IWL<1338> A_IWL<1337> A_IWL<1336> A_IWL<1335> A_IWL<1334> A_IWL<1333> A_IWL<1332> A_IWL<1331> A_IWL<1330> A_IWL<1329> A_IWL<1328> A_IWL<1327> A_IWL<1326> A_IWL<1325> A_IWL<1324> A_IWL<1323> A_IWL<1322> A_IWL<1321> A_IWL<1320> A_IWL<1319> A_IWL<1318> A_IWL<1317> A_IWL<1316> A_IWL<1315> A_IWL<1314> A_IWL<1313> A_IWL<1312> A_IWL<1311> A_IWL<1310> A_IWL<1309> A_IWL<1308> A_IWL<1307> A_IWL<1306> A_IWL<1305> A_IWL<1304> A_IWL<1303> A_IWL<1302> A_IWL<1301> A_IWL<1300> A_IWL<1299> A_IWL<1298> A_IWL<1297> A_IWL<1296> A_IWL<1295> A_IWL<1294> A_IWL<1293> A_IWL<1292> A_IWL<1291> A_IWL<1290> A_IWL<1289> A_IWL<1288> A_IWL<1287> A_IWL<1286> A_IWL<1285> A_IWL<1284> A_IWL<1283> A_IWL<1282> A_IWL<1281> A_IWL<1280> A_IWL<1407> A_IWL<1406> A_IWL<1405> A_IWL<1404> A_IWL<1403> A_IWL<1402> A_IWL<1401> A_IWL<1400> A_IWL<1399> A_IWL<1398> A_IWL<1397> A_IWL<1396> A_IWL<1395> A_IWL<1394> A_IWL<1393> A_IWL<1392> A_IWL<1391> A_IWL<1390> A_IWL<1389> A_IWL<1388> A_IWL<1387> A_IWL<1386> A_IWL<1385> A_IWL<1384> A_IWL<1383> A_IWL<1382> A_IWL<1381> A_IWL<1380> A_IWL<1379> A_IWL<1378> A_IWL<1377> A_IWL<1376> A_IWL<1375> A_IWL<1374> A_IWL<1373> A_IWL<1372> A_IWL<1371> A_IWL<1370> A_IWL<1369> A_IWL<1368> A_IWL<1367> A_IWL<1366> A_IWL<1365> A_IWL<1364> A_IWL<1363> A_IWL<1362> A_IWL<1361> A_IWL<1360> A_IWL<1359> A_IWL<1358> A_IWL<1357> A_IWL<1356> A_IWL<1355> A_IWL<1354> A_IWL<1353> A_IWL<1352> A_IWL<1351> A_IWL<1350> A_IWL<1349> A_IWL<1348> A_IWL<1347> A_IWL<1346> A_IWL<1345> A_IWL<1344> VDD_CORE VSS / RM_IHPSG13_256x32_c2_1P_COLUMN_pcell_0 +XCOL<20> A_BLC<41> A_BLC<40> A_BLC_TOP<41> A_BLC_TOP<40> A_BLT<41> A_BLT<40> A_BLT_TOP<41> A_BLT_TOP<40> A_IWL<1279> A_IWL<1278> A_IWL<1277> A_IWL<1276> A_IWL<1275> A_IWL<1274> A_IWL<1273> A_IWL<1272> A_IWL<1271> A_IWL<1270> A_IWL<1269> A_IWL<1268> A_IWL<1267> A_IWL<1266> A_IWL<1265> A_IWL<1264> A_IWL<1263> A_IWL<1262> A_IWL<1261> A_IWL<1260> A_IWL<1259> A_IWL<1258> A_IWL<1257> A_IWL<1256> A_IWL<1255> A_IWL<1254> A_IWL<1253> A_IWL<1252> A_IWL<1251> A_IWL<1250> A_IWL<1249> A_IWL<1248> A_IWL<1247> A_IWL<1246> A_IWL<1245> A_IWL<1244> A_IWL<1243> A_IWL<1242> A_IWL<1241> A_IWL<1240> A_IWL<1239> A_IWL<1238> A_IWL<1237> A_IWL<1236> A_IWL<1235> A_IWL<1234> A_IWL<1233> A_IWL<1232> A_IWL<1231> A_IWL<1230> A_IWL<1229> A_IWL<1228> A_IWL<1227> A_IWL<1226> A_IWL<1225> A_IWL<1224> A_IWL<1223> A_IWL<1222> A_IWL<1221> A_IWL<1220> A_IWL<1219> A_IWL<1218> A_IWL<1217> A_IWL<1216> A_IWL<1343> A_IWL<1342> A_IWL<1341> A_IWL<1340> A_IWL<1339> A_IWL<1338> A_IWL<1337> A_IWL<1336> A_IWL<1335> A_IWL<1334> A_IWL<1333> A_IWL<1332> A_IWL<1331> A_IWL<1330> A_IWL<1329> A_IWL<1328> A_IWL<1327> A_IWL<1326> A_IWL<1325> A_IWL<1324> A_IWL<1323> A_IWL<1322> A_IWL<1321> A_IWL<1320> A_IWL<1319> A_IWL<1318> A_IWL<1317> A_IWL<1316> A_IWL<1315> A_IWL<1314> A_IWL<1313> A_IWL<1312> A_IWL<1311> A_IWL<1310> A_IWL<1309> A_IWL<1308> A_IWL<1307> A_IWL<1306> A_IWL<1305> A_IWL<1304> A_IWL<1303> A_IWL<1302> A_IWL<1301> A_IWL<1300> A_IWL<1299> A_IWL<1298> A_IWL<1297> A_IWL<1296> A_IWL<1295> A_IWL<1294> A_IWL<1293> A_IWL<1292> A_IWL<1291> A_IWL<1290> A_IWL<1289> A_IWL<1288> A_IWL<1287> A_IWL<1286> A_IWL<1285> A_IWL<1284> A_IWL<1283> A_IWL<1282> A_IWL<1281> A_IWL<1280> VDD_CORE VSS / RM_IHPSG13_256x32_c2_1P_COLUMN_pcell_0 +XCOL<19> A_BLC<39> A_BLC<38> A_BLC_TOP<39> A_BLC_TOP<38> A_BLT<39> A_BLT<38> A_BLT_TOP<39> A_BLT_TOP<38> A_IWL<1215> A_IWL<1214> A_IWL<1213> A_IWL<1212> A_IWL<1211> A_IWL<1210> A_IWL<1209> A_IWL<1208> A_IWL<1207> A_IWL<1206> A_IWL<1205> A_IWL<1204> A_IWL<1203> A_IWL<1202> A_IWL<1201> A_IWL<1200> A_IWL<1199> A_IWL<1198> A_IWL<1197> A_IWL<1196> A_IWL<1195> A_IWL<1194> A_IWL<1193> A_IWL<1192> A_IWL<1191> A_IWL<1190> A_IWL<1189> A_IWL<1188> A_IWL<1187> A_IWL<1186> A_IWL<1185> A_IWL<1184> A_IWL<1183> A_IWL<1182> A_IWL<1181> A_IWL<1180> A_IWL<1179> A_IWL<1178> A_IWL<1177> A_IWL<1176> A_IWL<1175> A_IWL<1174> A_IWL<1173> A_IWL<1172> A_IWL<1171> A_IWL<1170> A_IWL<1169> A_IWL<1168> A_IWL<1167> A_IWL<1166> A_IWL<1165> A_IWL<1164> A_IWL<1163> A_IWL<1162> A_IWL<1161> A_IWL<1160> A_IWL<1159> A_IWL<1158> A_IWL<1157> A_IWL<1156> A_IWL<1155> A_IWL<1154> A_IWL<1153> A_IWL<1152> A_IWL<1279> A_IWL<1278> A_IWL<1277> A_IWL<1276> A_IWL<1275> A_IWL<1274> A_IWL<1273> A_IWL<1272> A_IWL<1271> A_IWL<1270> A_IWL<1269> A_IWL<1268> A_IWL<1267> A_IWL<1266> A_IWL<1265> A_IWL<1264> A_IWL<1263> A_IWL<1262> A_IWL<1261> A_IWL<1260> A_IWL<1259> A_IWL<1258> A_IWL<1257> A_IWL<1256> A_IWL<1255> A_IWL<1254> A_IWL<1253> A_IWL<1252> A_IWL<1251> A_IWL<1250> A_IWL<1249> A_IWL<1248> A_IWL<1247> A_IWL<1246> A_IWL<1245> A_IWL<1244> A_IWL<1243> A_IWL<1242> A_IWL<1241> A_IWL<1240> A_IWL<1239> A_IWL<1238> A_IWL<1237> A_IWL<1236> A_IWL<1235> A_IWL<1234> A_IWL<1233> A_IWL<1232> A_IWL<1231> A_IWL<1230> A_IWL<1229> A_IWL<1228> A_IWL<1227> A_IWL<1226> A_IWL<1225> A_IWL<1224> A_IWL<1223> A_IWL<1222> A_IWL<1221> A_IWL<1220> A_IWL<1219> A_IWL<1218> A_IWL<1217> A_IWL<1216> VDD_CORE VSS / RM_IHPSG13_256x32_c2_1P_COLUMN_pcell_0 +XCOL<18> A_BLC<37> A_BLC<36> A_BLC_TOP<37> A_BLC_TOP<36> A_BLT<37> A_BLT<36> A_BLT_TOP<37> A_BLT_TOP<36> A_IWL<1151> A_IWL<1150> A_IWL<1149> A_IWL<1148> A_IWL<1147> A_IWL<1146> A_IWL<1145> A_IWL<1144> A_IWL<1143> A_IWL<1142> A_IWL<1141> A_IWL<1140> A_IWL<1139> A_IWL<1138> A_IWL<1137> A_IWL<1136> A_IWL<1135> A_IWL<1134> A_IWL<1133> A_IWL<1132> A_IWL<1131> A_IWL<1130> A_IWL<1129> A_IWL<1128> A_IWL<1127> A_IWL<1126> A_IWL<1125> A_IWL<1124> A_IWL<1123> A_IWL<1122> A_IWL<1121> A_IWL<1120> A_IWL<1119> A_IWL<1118> A_IWL<1117> A_IWL<1116> A_IWL<1115> A_IWL<1114> A_IWL<1113> A_IWL<1112> A_IWL<1111> A_IWL<1110> A_IWL<1109> A_IWL<1108> A_IWL<1107> A_IWL<1106> A_IWL<1105> A_IWL<1104> A_IWL<1103> A_IWL<1102> A_IWL<1101> A_IWL<1100> A_IWL<1099> A_IWL<1098> A_IWL<1097> A_IWL<1096> A_IWL<1095> A_IWL<1094> A_IWL<1093> A_IWL<1092> A_IWL<1091> A_IWL<1090> A_IWL<1089> A_IWL<1088> A_IWL<1215> A_IWL<1214> A_IWL<1213> A_IWL<1212> A_IWL<1211> A_IWL<1210> A_IWL<1209> A_IWL<1208> A_IWL<1207> A_IWL<1206> A_IWL<1205> A_IWL<1204> A_IWL<1203> A_IWL<1202> A_IWL<1201> A_IWL<1200> A_IWL<1199> A_IWL<1198> A_IWL<1197> A_IWL<1196> A_IWL<1195> A_IWL<1194> A_IWL<1193> A_IWL<1192> A_IWL<1191> A_IWL<1190> A_IWL<1189> A_IWL<1188> A_IWL<1187> A_IWL<1186> A_IWL<1185> A_IWL<1184> A_IWL<1183> A_IWL<1182> A_IWL<1181> A_IWL<1180> A_IWL<1179> A_IWL<1178> A_IWL<1177> A_IWL<1176> A_IWL<1175> A_IWL<1174> A_IWL<1173> A_IWL<1172> A_IWL<1171> A_IWL<1170> A_IWL<1169> A_IWL<1168> A_IWL<1167> A_IWL<1166> A_IWL<1165> A_IWL<1164> A_IWL<1163> A_IWL<1162> A_IWL<1161> A_IWL<1160> A_IWL<1159> A_IWL<1158> A_IWL<1157> A_IWL<1156> A_IWL<1155> A_IWL<1154> A_IWL<1153> A_IWL<1152> VDD_CORE VSS / RM_IHPSG13_256x32_c2_1P_COLUMN_pcell_0 +XCOL<17> A_BLC<35> A_BLC<34> A_BLC_TOP<35> A_BLC_TOP<34> A_BLT<35> A_BLT<34> A_BLT_TOP<35> A_BLT_TOP<34> A_IWL<1087> A_IWL<1086> A_IWL<1085> A_IWL<1084> A_IWL<1083> A_IWL<1082> A_IWL<1081> A_IWL<1080> A_IWL<1079> A_IWL<1078> A_IWL<1077> A_IWL<1076> A_IWL<1075> A_IWL<1074> A_IWL<1073> A_IWL<1072> A_IWL<1071> A_IWL<1070> A_IWL<1069> A_IWL<1068> A_IWL<1067> A_IWL<1066> A_IWL<1065> A_IWL<1064> A_IWL<1063> A_IWL<1062> A_IWL<1061> A_IWL<1060> A_IWL<1059> A_IWL<1058> A_IWL<1057> A_IWL<1056> A_IWL<1055> A_IWL<1054> A_IWL<1053> A_IWL<1052> A_IWL<1051> A_IWL<1050> A_IWL<1049> A_IWL<1048> A_IWL<1047> A_IWL<1046> A_IWL<1045> A_IWL<1044> A_IWL<1043> A_IWL<1042> A_IWL<1041> A_IWL<1040> A_IWL<1039> A_IWL<1038> A_IWL<1037> A_IWL<1036> A_IWL<1035> A_IWL<1034> A_IWL<1033> A_IWL<1032> A_IWL<1031> A_IWL<1030> A_IWL<1029> A_IWL<1028> A_IWL<1027> A_IWL<1026> A_IWL<1025> A_IWL<1024> A_IWL<1151> A_IWL<1150> A_IWL<1149> A_IWL<1148> A_IWL<1147> A_IWL<1146> A_IWL<1145> A_IWL<1144> A_IWL<1143> A_IWL<1142> A_IWL<1141> A_IWL<1140> A_IWL<1139> A_IWL<1138> A_IWL<1137> A_IWL<1136> A_IWL<1135> A_IWL<1134> A_IWL<1133> A_IWL<1132> A_IWL<1131> A_IWL<1130> A_IWL<1129> A_IWL<1128> A_IWL<1127> A_IWL<1126> A_IWL<1125> A_IWL<1124> A_IWL<1123> A_IWL<1122> A_IWL<1121> A_IWL<1120> A_IWL<1119> A_IWL<1118> A_IWL<1117> A_IWL<1116> A_IWL<1115> A_IWL<1114> A_IWL<1113> A_IWL<1112> A_IWL<1111> A_IWL<1110> A_IWL<1109> A_IWL<1108> A_IWL<1107> A_IWL<1106> A_IWL<1105> A_IWL<1104> A_IWL<1103> A_IWL<1102> A_IWL<1101> A_IWL<1100> A_IWL<1099> A_IWL<1098> A_IWL<1097> A_IWL<1096> A_IWL<1095> A_IWL<1094> A_IWL<1093> A_IWL<1092> A_IWL<1091> A_IWL<1090> A_IWL<1089> A_IWL<1088> VDD_CORE VSS / RM_IHPSG13_256x32_c2_1P_COLUMN_pcell_0 +XCOL<16> A_BLC<33> A_BLC<32> A_BLC_TOP<33> A_BLC_TOP<32> A_BLT<33> A_BLT<32> A_BLT_TOP<33> A_BLT_TOP<32> A_IWL<1023> A_IWL<1022> A_IWL<1021> A_IWL<1020> A_IWL<1019> A_IWL<1018> A_IWL<1017> A_IWL<1016> A_IWL<1015> A_IWL<1014> A_IWL<1013> A_IWL<1012> A_IWL<1011> A_IWL<1010> A_IWL<1009> A_IWL<1008> A_IWL<1007> A_IWL<1006> A_IWL<1005> A_IWL<1004> A_IWL<1003> A_IWL<1002> A_IWL<1001> A_IWL<1000> A_IWL<999> A_IWL<998> A_IWL<997> A_IWL<996> A_IWL<995> A_IWL<994> A_IWL<993> A_IWL<992> A_IWL<991> A_IWL<990> A_IWL<989> A_IWL<988> A_IWL<987> A_IWL<986> A_IWL<985> A_IWL<984> A_IWL<983> A_IWL<982> A_IWL<981> A_IWL<980> A_IWL<979> A_IWL<978> A_IWL<977> A_IWL<976> A_IWL<975> A_IWL<974> A_IWL<973> A_IWL<972> A_IWL<971> A_IWL<970> A_IWL<969> A_IWL<968> A_IWL<967> A_IWL<966> A_IWL<965> A_IWL<964> A_IWL<963> A_IWL<962> A_IWL<961> A_IWL<960> A_IWL<1087> A_IWL<1086> A_IWL<1085> A_IWL<1084> A_IWL<1083> A_IWL<1082> A_IWL<1081> A_IWL<1080> A_IWL<1079> A_IWL<1078> A_IWL<1077> A_IWL<1076> A_IWL<1075> A_IWL<1074> A_IWL<1073> A_IWL<1072> A_IWL<1071> A_IWL<1070> A_IWL<1069> A_IWL<1068> A_IWL<1067> A_IWL<1066> A_IWL<1065> A_IWL<1064> A_IWL<1063> A_IWL<1062> A_IWL<1061> A_IWL<1060> A_IWL<1059> A_IWL<1058> A_IWL<1057> A_IWL<1056> A_IWL<1055> A_IWL<1054> A_IWL<1053> A_IWL<1052> A_IWL<1051> A_IWL<1050> A_IWL<1049> A_IWL<1048> A_IWL<1047> A_IWL<1046> A_IWL<1045> A_IWL<1044> A_IWL<1043> A_IWL<1042> A_IWL<1041> A_IWL<1040> A_IWL<1039> A_IWL<1038> A_IWL<1037> A_IWL<1036> A_IWL<1035> A_IWL<1034> A_IWL<1033> A_IWL<1032> A_IWL<1031> A_IWL<1030> A_IWL<1029> A_IWL<1028> A_IWL<1027> A_IWL<1026> A_IWL<1025> A_IWL<1024> VDD_CORE VSS / RM_IHPSG13_256x32_c2_1P_COLUMN_pcell_0 +XCOL<15> A_BLC<31> A_BLC<30> A_BLC_TOP<31> A_BLC_TOP<30> A_BLT<31> A_BLT<30> A_BLT_TOP<31> A_BLT_TOP<30> A_IWL<959> A_IWL<958> A_IWL<957> A_IWL<956> A_IWL<955> A_IWL<954> A_IWL<953> A_IWL<952> A_IWL<951> A_IWL<950> A_IWL<949> A_IWL<948> A_IWL<947> A_IWL<946> A_IWL<945> A_IWL<944> A_IWL<943> A_IWL<942> A_IWL<941> A_IWL<940> A_IWL<939> A_IWL<938> A_IWL<937> A_IWL<936> A_IWL<935> A_IWL<934> A_IWL<933> A_IWL<932> A_IWL<931> A_IWL<930> A_IWL<929> A_IWL<928> A_IWL<927> A_IWL<926> A_IWL<925> A_IWL<924> A_IWL<923> A_IWL<922> A_IWL<921> A_IWL<920> A_IWL<919> A_IWL<918> A_IWL<917> A_IWL<916> A_IWL<915> A_IWL<914> A_IWL<913> A_IWL<912> A_IWL<911> A_IWL<910> A_IWL<909> A_IWL<908> A_IWL<907> A_IWL<906> A_IWL<905> A_IWL<904> A_IWL<903> A_IWL<902> A_IWL<901> A_IWL<900> A_IWL<899> A_IWL<898> A_IWL<897> A_IWL<896> A_IWL<1023> A_IWL<1022> A_IWL<1021> A_IWL<1020> A_IWL<1019> A_IWL<1018> A_IWL<1017> A_IWL<1016> A_IWL<1015> A_IWL<1014> A_IWL<1013> A_IWL<1012> A_IWL<1011> A_IWL<1010> A_IWL<1009> A_IWL<1008> A_IWL<1007> A_IWL<1006> A_IWL<1005> A_IWL<1004> A_IWL<1003> A_IWL<1002> A_IWL<1001> A_IWL<1000> A_IWL<999> A_IWL<998> A_IWL<997> A_IWL<996> A_IWL<995> A_IWL<994> A_IWL<993> A_IWL<992> A_IWL<991> A_IWL<990> A_IWL<989> A_IWL<988> A_IWL<987> A_IWL<986> A_IWL<985> A_IWL<984> A_IWL<983> A_IWL<982> A_IWL<981> A_IWL<980> A_IWL<979> A_IWL<978> A_IWL<977> A_IWL<976> A_IWL<975> A_IWL<974> A_IWL<973> A_IWL<972> A_IWL<971> A_IWL<970> A_IWL<969> A_IWL<968> A_IWL<967> A_IWL<966> A_IWL<965> A_IWL<964> A_IWL<963> A_IWL<962> A_IWL<961> A_IWL<960> VDD_CORE VSS / RM_IHPSG13_256x32_c2_1P_COLUMN_pcell_0 +XCOL<14> A_BLC<29> A_BLC<28> A_BLC_TOP<29> A_BLC_TOP<28> A_BLT<29> A_BLT<28> A_BLT_TOP<29> A_BLT_TOP<28> A_IWL<895> A_IWL<894> A_IWL<893> A_IWL<892> A_IWL<891> A_IWL<890> A_IWL<889> A_IWL<888> A_IWL<887> A_IWL<886> A_IWL<885> A_IWL<884> A_IWL<883> A_IWL<882> A_IWL<881> A_IWL<880> A_IWL<879> A_IWL<878> A_IWL<877> A_IWL<876> A_IWL<875> A_IWL<874> A_IWL<873> A_IWL<872> A_IWL<871> A_IWL<870> A_IWL<869> A_IWL<868> A_IWL<867> A_IWL<866> A_IWL<865> A_IWL<864> A_IWL<863> A_IWL<862> A_IWL<861> A_IWL<860> A_IWL<859> A_IWL<858> A_IWL<857> A_IWL<856> A_IWL<855> A_IWL<854> A_IWL<853> A_IWL<852> A_IWL<851> A_IWL<850> A_IWL<849> A_IWL<848> A_IWL<847> A_IWL<846> A_IWL<845> A_IWL<844> A_IWL<843> A_IWL<842> A_IWL<841> A_IWL<840> A_IWL<839> A_IWL<838> A_IWL<837> A_IWL<836> A_IWL<835> A_IWL<834> A_IWL<833> A_IWL<832> A_IWL<959> A_IWL<958> A_IWL<957> A_IWL<956> A_IWL<955> A_IWL<954> A_IWL<953> A_IWL<952> A_IWL<951> A_IWL<950> A_IWL<949> A_IWL<948> A_IWL<947> A_IWL<946> A_IWL<945> A_IWL<944> A_IWL<943> A_IWL<942> A_IWL<941> A_IWL<940> A_IWL<939> A_IWL<938> A_IWL<937> A_IWL<936> A_IWL<935> A_IWL<934> A_IWL<933> A_IWL<932> A_IWL<931> A_IWL<930> A_IWL<929> A_IWL<928> A_IWL<927> A_IWL<926> A_IWL<925> A_IWL<924> A_IWL<923> A_IWL<922> A_IWL<921> A_IWL<920> A_IWL<919> A_IWL<918> A_IWL<917> A_IWL<916> A_IWL<915> A_IWL<914> A_IWL<913> A_IWL<912> A_IWL<911> A_IWL<910> A_IWL<909> A_IWL<908> A_IWL<907> A_IWL<906> A_IWL<905> A_IWL<904> A_IWL<903> A_IWL<902> A_IWL<901> A_IWL<900> A_IWL<899> A_IWL<898> A_IWL<897> A_IWL<896> VDD_CORE VSS / RM_IHPSG13_256x32_c2_1P_COLUMN_pcell_0 +XCOL<13> A_BLC<27> A_BLC<26> A_BLC_TOP<27> A_BLC_TOP<26> A_BLT<27> A_BLT<26> A_BLT_TOP<27> A_BLT_TOP<26> A_IWL<831> A_IWL<830> A_IWL<829> A_IWL<828> A_IWL<827> A_IWL<826> A_IWL<825> A_IWL<824> A_IWL<823> A_IWL<822> A_IWL<821> A_IWL<820> A_IWL<819> A_IWL<818> A_IWL<817> A_IWL<816> A_IWL<815> A_IWL<814> A_IWL<813> A_IWL<812> A_IWL<811> A_IWL<810> A_IWL<809> A_IWL<808> A_IWL<807> A_IWL<806> A_IWL<805> A_IWL<804> A_IWL<803> A_IWL<802> A_IWL<801> A_IWL<800> A_IWL<799> A_IWL<798> A_IWL<797> A_IWL<796> A_IWL<795> A_IWL<794> A_IWL<793> A_IWL<792> A_IWL<791> A_IWL<790> A_IWL<789> A_IWL<788> A_IWL<787> A_IWL<786> A_IWL<785> A_IWL<784> A_IWL<783> A_IWL<782> A_IWL<781> A_IWL<780> A_IWL<779> A_IWL<778> A_IWL<777> A_IWL<776> A_IWL<775> A_IWL<774> A_IWL<773> A_IWL<772> A_IWL<771> A_IWL<770> A_IWL<769> A_IWL<768> A_IWL<895> A_IWL<894> A_IWL<893> A_IWL<892> A_IWL<891> A_IWL<890> A_IWL<889> A_IWL<888> A_IWL<887> A_IWL<886> A_IWL<885> A_IWL<884> A_IWL<883> A_IWL<882> A_IWL<881> A_IWL<880> A_IWL<879> A_IWL<878> A_IWL<877> A_IWL<876> A_IWL<875> A_IWL<874> A_IWL<873> A_IWL<872> A_IWL<871> A_IWL<870> A_IWL<869> A_IWL<868> A_IWL<867> A_IWL<866> A_IWL<865> A_IWL<864> A_IWL<863> A_IWL<862> A_IWL<861> A_IWL<860> A_IWL<859> A_IWL<858> A_IWL<857> A_IWL<856> A_IWL<855> A_IWL<854> A_IWL<853> A_IWL<852> A_IWL<851> A_IWL<850> A_IWL<849> A_IWL<848> A_IWL<847> A_IWL<846> A_IWL<845> A_IWL<844> A_IWL<843> A_IWL<842> A_IWL<841> A_IWL<840> A_IWL<839> A_IWL<838> A_IWL<837> A_IWL<836> A_IWL<835> A_IWL<834> A_IWL<833> A_IWL<832> VDD_CORE VSS / RM_IHPSG13_256x32_c2_1P_COLUMN_pcell_0 +XCOL<12> A_BLC<25> A_BLC<24> A_BLC_TOP<25> A_BLC_TOP<24> A_BLT<25> A_BLT<24> A_BLT_TOP<25> A_BLT_TOP<24> A_IWL<767> A_IWL<766> A_IWL<765> A_IWL<764> A_IWL<763> A_IWL<762> A_IWL<761> A_IWL<760> A_IWL<759> A_IWL<758> A_IWL<757> A_IWL<756> A_IWL<755> A_IWL<754> A_IWL<753> A_IWL<752> A_IWL<751> A_IWL<750> A_IWL<749> A_IWL<748> A_IWL<747> A_IWL<746> A_IWL<745> A_IWL<744> A_IWL<743> A_IWL<742> A_IWL<741> A_IWL<740> A_IWL<739> A_IWL<738> A_IWL<737> A_IWL<736> A_IWL<735> A_IWL<734> A_IWL<733> A_IWL<732> A_IWL<731> A_IWL<730> A_IWL<729> A_IWL<728> A_IWL<727> A_IWL<726> A_IWL<725> A_IWL<724> A_IWL<723> A_IWL<722> A_IWL<721> A_IWL<720> A_IWL<719> A_IWL<718> A_IWL<717> A_IWL<716> A_IWL<715> A_IWL<714> A_IWL<713> A_IWL<712> A_IWL<711> A_IWL<710> A_IWL<709> A_IWL<708> A_IWL<707> A_IWL<706> A_IWL<705> A_IWL<704> A_IWL<831> A_IWL<830> A_IWL<829> A_IWL<828> A_IWL<827> A_IWL<826> A_IWL<825> A_IWL<824> A_IWL<823> A_IWL<822> A_IWL<821> A_IWL<820> A_IWL<819> A_IWL<818> A_IWL<817> A_IWL<816> A_IWL<815> A_IWL<814> A_IWL<813> A_IWL<812> A_IWL<811> A_IWL<810> A_IWL<809> A_IWL<808> A_IWL<807> A_IWL<806> A_IWL<805> A_IWL<804> A_IWL<803> A_IWL<802> A_IWL<801> A_IWL<800> A_IWL<799> A_IWL<798> A_IWL<797> A_IWL<796> A_IWL<795> A_IWL<794> A_IWL<793> A_IWL<792> A_IWL<791> A_IWL<790> A_IWL<789> A_IWL<788> A_IWL<787> A_IWL<786> A_IWL<785> A_IWL<784> A_IWL<783> A_IWL<782> A_IWL<781> A_IWL<780> A_IWL<779> A_IWL<778> A_IWL<777> A_IWL<776> A_IWL<775> A_IWL<774> A_IWL<773> A_IWL<772> A_IWL<771> A_IWL<770> A_IWL<769> A_IWL<768> VDD_CORE VSS / RM_IHPSG13_256x32_c2_1P_COLUMN_pcell_0 +XCOL<11> A_BLC<23> A_BLC<22> A_BLC_TOP<23> A_BLC_TOP<22> A_BLT<23> A_BLT<22> A_BLT_TOP<23> A_BLT_TOP<22> A_IWL<703> A_IWL<702> A_IWL<701> A_IWL<700> A_IWL<699> A_IWL<698> A_IWL<697> A_IWL<696> A_IWL<695> A_IWL<694> A_IWL<693> A_IWL<692> A_IWL<691> A_IWL<690> A_IWL<689> A_IWL<688> A_IWL<687> A_IWL<686> A_IWL<685> A_IWL<684> A_IWL<683> A_IWL<682> A_IWL<681> A_IWL<680> A_IWL<679> A_IWL<678> A_IWL<677> A_IWL<676> A_IWL<675> A_IWL<674> A_IWL<673> A_IWL<672> A_IWL<671> A_IWL<670> A_IWL<669> A_IWL<668> A_IWL<667> A_IWL<666> A_IWL<665> A_IWL<664> A_IWL<663> A_IWL<662> A_IWL<661> A_IWL<660> A_IWL<659> A_IWL<658> A_IWL<657> A_IWL<656> A_IWL<655> A_IWL<654> A_IWL<653> A_IWL<652> A_IWL<651> A_IWL<650> A_IWL<649> A_IWL<648> A_IWL<647> A_IWL<646> A_IWL<645> A_IWL<644> A_IWL<643> A_IWL<642> A_IWL<641> A_IWL<640> A_IWL<767> A_IWL<766> A_IWL<765> A_IWL<764> A_IWL<763> A_IWL<762> A_IWL<761> A_IWL<760> A_IWL<759> A_IWL<758> A_IWL<757> A_IWL<756> A_IWL<755> A_IWL<754> A_IWL<753> A_IWL<752> A_IWL<751> A_IWL<750> A_IWL<749> A_IWL<748> A_IWL<747> A_IWL<746> A_IWL<745> A_IWL<744> A_IWL<743> A_IWL<742> A_IWL<741> A_IWL<740> A_IWL<739> A_IWL<738> A_IWL<737> A_IWL<736> A_IWL<735> A_IWL<734> A_IWL<733> A_IWL<732> A_IWL<731> A_IWL<730> A_IWL<729> A_IWL<728> A_IWL<727> A_IWL<726> A_IWL<725> A_IWL<724> A_IWL<723> A_IWL<722> A_IWL<721> A_IWL<720> A_IWL<719> A_IWL<718> A_IWL<717> A_IWL<716> A_IWL<715> A_IWL<714> A_IWL<713> A_IWL<712> A_IWL<711> A_IWL<710> A_IWL<709> A_IWL<708> A_IWL<707> A_IWL<706> A_IWL<705> A_IWL<704> VDD_CORE VSS / RM_IHPSG13_256x32_c2_1P_COLUMN_pcell_0 +XCOL<10> A_BLC<21> A_BLC<20> A_BLC_TOP<21> A_BLC_TOP<20> A_BLT<21> A_BLT<20> A_BLT_TOP<21> A_BLT_TOP<20> A_IWL<639> A_IWL<638> A_IWL<637> A_IWL<636> A_IWL<635> A_IWL<634> A_IWL<633> A_IWL<632> A_IWL<631> A_IWL<630> A_IWL<629> A_IWL<628> A_IWL<627> A_IWL<626> A_IWL<625> A_IWL<624> A_IWL<623> A_IWL<622> A_IWL<621> A_IWL<620> A_IWL<619> A_IWL<618> A_IWL<617> A_IWL<616> A_IWL<615> A_IWL<614> A_IWL<613> A_IWL<612> A_IWL<611> A_IWL<610> A_IWL<609> A_IWL<608> A_IWL<607> A_IWL<606> A_IWL<605> A_IWL<604> A_IWL<603> A_IWL<602> A_IWL<601> A_IWL<600> A_IWL<599> A_IWL<598> A_IWL<597> A_IWL<596> A_IWL<595> A_IWL<594> A_IWL<593> A_IWL<592> A_IWL<591> A_IWL<590> A_IWL<589> A_IWL<588> A_IWL<587> A_IWL<586> A_IWL<585> A_IWL<584> A_IWL<583> A_IWL<582> A_IWL<581> A_IWL<580> A_IWL<579> A_IWL<578> A_IWL<577> A_IWL<576> A_IWL<703> A_IWL<702> A_IWL<701> A_IWL<700> A_IWL<699> A_IWL<698> A_IWL<697> A_IWL<696> A_IWL<695> A_IWL<694> A_IWL<693> A_IWL<692> A_IWL<691> A_IWL<690> A_IWL<689> A_IWL<688> A_IWL<687> A_IWL<686> A_IWL<685> A_IWL<684> A_IWL<683> A_IWL<682> A_IWL<681> A_IWL<680> A_IWL<679> A_IWL<678> A_IWL<677> A_IWL<676> A_IWL<675> A_IWL<674> A_IWL<673> A_IWL<672> A_IWL<671> A_IWL<670> A_IWL<669> A_IWL<668> A_IWL<667> A_IWL<666> A_IWL<665> A_IWL<664> A_IWL<663> A_IWL<662> A_IWL<661> A_IWL<660> A_IWL<659> A_IWL<658> A_IWL<657> A_IWL<656> A_IWL<655> A_IWL<654> A_IWL<653> A_IWL<652> A_IWL<651> A_IWL<650> A_IWL<649> A_IWL<648> A_IWL<647> A_IWL<646> A_IWL<645> A_IWL<644> A_IWL<643> A_IWL<642> A_IWL<641> A_IWL<640> VDD_CORE VSS / RM_IHPSG13_256x32_c2_1P_COLUMN_pcell_0 +XCOL<9> A_BLC<19> A_BLC<18> A_BLC_TOP<19> A_BLC_TOP<18> A_BLT<19> A_BLT<18> A_BLT_TOP<19> A_BLT_TOP<18> A_IWL<575> A_IWL<574> A_IWL<573> A_IWL<572> A_IWL<571> A_IWL<570> A_IWL<569> A_IWL<568> A_IWL<567> A_IWL<566> A_IWL<565> A_IWL<564> A_IWL<563> A_IWL<562> A_IWL<561> A_IWL<560> A_IWL<559> A_IWL<558> A_IWL<557> A_IWL<556> A_IWL<555> A_IWL<554> A_IWL<553> A_IWL<552> A_IWL<551> A_IWL<550> A_IWL<549> A_IWL<548> A_IWL<547> A_IWL<546> A_IWL<545> A_IWL<544> A_IWL<543> A_IWL<542> A_IWL<541> A_IWL<540> A_IWL<539> A_IWL<538> A_IWL<537> A_IWL<536> A_IWL<535> A_IWL<534> A_IWL<533> A_IWL<532> A_IWL<531> A_IWL<530> A_IWL<529> A_IWL<528> A_IWL<527> A_IWL<526> A_IWL<525> A_IWL<524> A_IWL<523> A_IWL<522> A_IWL<521> A_IWL<520> A_IWL<519> A_IWL<518> A_IWL<517> A_IWL<516> A_IWL<515> A_IWL<514> A_IWL<513> A_IWL<512> A_IWL<639> A_IWL<638> A_IWL<637> A_IWL<636> A_IWL<635> A_IWL<634> A_IWL<633> A_IWL<632> A_IWL<631> A_IWL<630> A_IWL<629> A_IWL<628> A_IWL<627> A_IWL<626> A_IWL<625> A_IWL<624> A_IWL<623> A_IWL<622> A_IWL<621> A_IWL<620> A_IWL<619> A_IWL<618> A_IWL<617> A_IWL<616> A_IWL<615> A_IWL<614> A_IWL<613> A_IWL<612> A_IWL<611> A_IWL<610> A_IWL<609> A_IWL<608> A_IWL<607> A_IWL<606> A_IWL<605> A_IWL<604> A_IWL<603> A_IWL<602> A_IWL<601> A_IWL<600> A_IWL<599> A_IWL<598> A_IWL<597> A_IWL<596> A_IWL<595> A_IWL<594> A_IWL<593> A_IWL<592> A_IWL<591> A_IWL<590> A_IWL<589> A_IWL<588> A_IWL<587> A_IWL<586> A_IWL<585> A_IWL<584> A_IWL<583> A_IWL<582> A_IWL<581> A_IWL<580> A_IWL<579> A_IWL<578> A_IWL<577> A_IWL<576> VDD_CORE VSS / RM_IHPSG13_256x32_c2_1P_COLUMN_pcell_0 +XCOL<8> A_BLC<17> A_BLC<16> A_BLC_TOP<17> A_BLC_TOP<16> A_BLT<17> A_BLT<16> A_BLT_TOP<17> A_BLT_TOP<16> A_IWL<511> A_IWL<510> A_IWL<509> A_IWL<508> A_IWL<507> A_IWL<506> A_IWL<505> A_IWL<504> A_IWL<503> A_IWL<502> A_IWL<501> A_IWL<500> A_IWL<499> A_IWL<498> A_IWL<497> A_IWL<496> A_IWL<495> A_IWL<494> A_IWL<493> A_IWL<492> A_IWL<491> A_IWL<490> A_IWL<489> A_IWL<488> A_IWL<487> A_IWL<486> A_IWL<485> A_IWL<484> A_IWL<483> A_IWL<482> A_IWL<481> A_IWL<480> A_IWL<479> A_IWL<478> A_IWL<477> A_IWL<476> A_IWL<475> A_IWL<474> A_IWL<473> A_IWL<472> A_IWL<471> A_IWL<470> A_IWL<469> A_IWL<468> A_IWL<467> A_IWL<466> A_IWL<465> A_IWL<464> A_IWL<463> A_IWL<462> A_IWL<461> A_IWL<460> A_IWL<459> A_IWL<458> A_IWL<457> A_IWL<456> A_IWL<455> A_IWL<454> A_IWL<453> A_IWL<452> A_IWL<451> A_IWL<450> A_IWL<449> A_IWL<448> A_IWL<575> A_IWL<574> A_IWL<573> A_IWL<572> A_IWL<571> A_IWL<570> A_IWL<569> A_IWL<568> A_IWL<567> A_IWL<566> A_IWL<565> A_IWL<564> A_IWL<563> A_IWL<562> A_IWL<561> A_IWL<560> A_IWL<559> A_IWL<558> A_IWL<557> A_IWL<556> A_IWL<555> A_IWL<554> A_IWL<553> A_IWL<552> A_IWL<551> A_IWL<550> A_IWL<549> A_IWL<548> A_IWL<547> A_IWL<546> A_IWL<545> A_IWL<544> A_IWL<543> A_IWL<542> A_IWL<541> A_IWL<540> A_IWL<539> A_IWL<538> A_IWL<537> A_IWL<536> A_IWL<535> A_IWL<534> A_IWL<533> A_IWL<532> A_IWL<531> A_IWL<530> A_IWL<529> A_IWL<528> A_IWL<527> A_IWL<526> A_IWL<525> A_IWL<524> A_IWL<523> A_IWL<522> A_IWL<521> A_IWL<520> A_IWL<519> A_IWL<518> A_IWL<517> A_IWL<516> A_IWL<515> A_IWL<514> A_IWL<513> A_IWL<512> VDD_CORE VSS / RM_IHPSG13_256x32_c2_1P_COLUMN_pcell_0 +XCOL<7> A_BLC<15> A_BLC<14> A_BLC_TOP<15> A_BLC_TOP<14> A_BLT<15> A_BLT<14> A_BLT_TOP<15> A_BLT_TOP<14> A_IWL<447> A_IWL<446> A_IWL<445> A_IWL<444> A_IWL<443> A_IWL<442> A_IWL<441> A_IWL<440> A_IWL<439> A_IWL<438> A_IWL<437> A_IWL<436> A_IWL<435> A_IWL<434> A_IWL<433> A_IWL<432> A_IWL<431> A_IWL<430> A_IWL<429> A_IWL<428> A_IWL<427> A_IWL<426> A_IWL<425> A_IWL<424> A_IWL<423> A_IWL<422> A_IWL<421> A_IWL<420> A_IWL<419> A_IWL<418> A_IWL<417> A_IWL<416> A_IWL<415> A_IWL<414> A_IWL<413> A_IWL<412> A_IWL<411> A_IWL<410> A_IWL<409> A_IWL<408> A_IWL<407> A_IWL<406> A_IWL<405> A_IWL<404> A_IWL<403> A_IWL<402> A_IWL<401> A_IWL<400> A_IWL<399> A_IWL<398> A_IWL<397> A_IWL<396> A_IWL<395> A_IWL<394> A_IWL<393> A_IWL<392> A_IWL<391> A_IWL<390> A_IWL<389> A_IWL<388> A_IWL<387> A_IWL<386> A_IWL<385> A_IWL<384> A_IWL<511> A_IWL<510> A_IWL<509> A_IWL<508> A_IWL<507> A_IWL<506> A_IWL<505> A_IWL<504> A_IWL<503> A_IWL<502> A_IWL<501> A_IWL<500> A_IWL<499> A_IWL<498> A_IWL<497> A_IWL<496> A_IWL<495> A_IWL<494> A_IWL<493> A_IWL<492> A_IWL<491> A_IWL<490> A_IWL<489> A_IWL<488> A_IWL<487> A_IWL<486> A_IWL<485> A_IWL<484> A_IWL<483> A_IWL<482> A_IWL<481> A_IWL<480> A_IWL<479> A_IWL<478> A_IWL<477> A_IWL<476> A_IWL<475> A_IWL<474> A_IWL<473> A_IWL<472> A_IWL<471> A_IWL<470> A_IWL<469> A_IWL<468> A_IWL<467> A_IWL<466> A_IWL<465> A_IWL<464> A_IWL<463> A_IWL<462> A_IWL<461> A_IWL<460> A_IWL<459> A_IWL<458> A_IWL<457> A_IWL<456> A_IWL<455> A_IWL<454> A_IWL<453> A_IWL<452> A_IWL<451> A_IWL<450> A_IWL<449> A_IWL<448> VDD_CORE VSS / RM_IHPSG13_256x32_c2_1P_COLUMN_pcell_0 +XCOL<6> A_BLC<13> A_BLC<12> A_BLC_TOP<13> A_BLC_TOP<12> A_BLT<13> A_BLT<12> A_BLT_TOP<13> A_BLT_TOP<12> A_IWL<383> A_IWL<382> A_IWL<381> A_IWL<380> A_IWL<379> A_IWL<378> A_IWL<377> A_IWL<376> A_IWL<375> A_IWL<374> A_IWL<373> A_IWL<372> A_IWL<371> A_IWL<370> A_IWL<369> A_IWL<368> A_IWL<367> A_IWL<366> A_IWL<365> A_IWL<364> A_IWL<363> A_IWL<362> A_IWL<361> A_IWL<360> A_IWL<359> A_IWL<358> A_IWL<357> A_IWL<356> A_IWL<355> A_IWL<354> A_IWL<353> A_IWL<352> A_IWL<351> A_IWL<350> A_IWL<349> A_IWL<348> A_IWL<347> A_IWL<346> A_IWL<345> A_IWL<344> A_IWL<343> A_IWL<342> A_IWL<341> A_IWL<340> A_IWL<339> A_IWL<338> A_IWL<337> A_IWL<336> A_IWL<335> A_IWL<334> A_IWL<333> A_IWL<332> A_IWL<331> A_IWL<330> A_IWL<329> A_IWL<328> A_IWL<327> A_IWL<326> A_IWL<325> A_IWL<324> A_IWL<323> A_IWL<322> A_IWL<321> A_IWL<320> A_IWL<447> A_IWL<446> A_IWL<445> A_IWL<444> A_IWL<443> A_IWL<442> A_IWL<441> A_IWL<440> A_IWL<439> A_IWL<438> A_IWL<437> A_IWL<436> A_IWL<435> A_IWL<434> A_IWL<433> A_IWL<432> A_IWL<431> A_IWL<430> A_IWL<429> A_IWL<428> A_IWL<427> A_IWL<426> A_IWL<425> A_IWL<424> A_IWL<423> A_IWL<422> A_IWL<421> A_IWL<420> A_IWL<419> A_IWL<418> A_IWL<417> A_IWL<416> A_IWL<415> A_IWL<414> A_IWL<413> A_IWL<412> A_IWL<411> A_IWL<410> A_IWL<409> A_IWL<408> A_IWL<407> A_IWL<406> A_IWL<405> A_IWL<404> A_IWL<403> A_IWL<402> A_IWL<401> A_IWL<400> A_IWL<399> A_IWL<398> A_IWL<397> A_IWL<396> A_IWL<395> A_IWL<394> A_IWL<393> A_IWL<392> A_IWL<391> A_IWL<390> A_IWL<389> A_IWL<388> A_IWL<387> A_IWL<386> A_IWL<385> A_IWL<384> VDD_CORE VSS / RM_IHPSG13_256x32_c2_1P_COLUMN_pcell_0 +XCOL<5> A_BLC<11> A_BLC<10> A_BLC_TOP<11> A_BLC_TOP<10> A_BLT<11> A_BLT<10> A_BLT_TOP<11> A_BLT_TOP<10> A_IWL<319> A_IWL<318> A_IWL<317> A_IWL<316> A_IWL<315> A_IWL<314> A_IWL<313> A_IWL<312> A_IWL<311> A_IWL<310> A_IWL<309> A_IWL<308> A_IWL<307> A_IWL<306> A_IWL<305> A_IWL<304> A_IWL<303> A_IWL<302> A_IWL<301> A_IWL<300> A_IWL<299> A_IWL<298> A_IWL<297> A_IWL<296> A_IWL<295> A_IWL<294> A_IWL<293> A_IWL<292> A_IWL<291> A_IWL<290> A_IWL<289> A_IWL<288> A_IWL<287> A_IWL<286> A_IWL<285> A_IWL<284> A_IWL<283> A_IWL<282> A_IWL<281> A_IWL<280> A_IWL<279> A_IWL<278> A_IWL<277> A_IWL<276> A_IWL<275> A_IWL<274> A_IWL<273> A_IWL<272> A_IWL<271> A_IWL<270> A_IWL<269> A_IWL<268> A_IWL<267> A_IWL<266> A_IWL<265> A_IWL<264> A_IWL<263> A_IWL<262> A_IWL<261> A_IWL<260> A_IWL<259> A_IWL<258> A_IWL<257> A_IWL<256> A_IWL<383> A_IWL<382> A_IWL<381> A_IWL<380> A_IWL<379> A_IWL<378> A_IWL<377> A_IWL<376> A_IWL<375> A_IWL<374> A_IWL<373> A_IWL<372> A_IWL<371> A_IWL<370> A_IWL<369> A_IWL<368> A_IWL<367> A_IWL<366> A_IWL<365> A_IWL<364> A_IWL<363> A_IWL<362> A_IWL<361> A_IWL<360> A_IWL<359> A_IWL<358> A_IWL<357> A_IWL<356> A_IWL<355> A_IWL<354> A_IWL<353> A_IWL<352> A_IWL<351> A_IWL<350> A_IWL<349> A_IWL<348> A_IWL<347> A_IWL<346> A_IWL<345> A_IWL<344> A_IWL<343> A_IWL<342> A_IWL<341> A_IWL<340> A_IWL<339> A_IWL<338> A_IWL<337> A_IWL<336> A_IWL<335> A_IWL<334> A_IWL<333> A_IWL<332> A_IWL<331> A_IWL<330> A_IWL<329> A_IWL<328> A_IWL<327> A_IWL<326> A_IWL<325> A_IWL<324> A_IWL<323> A_IWL<322> A_IWL<321> A_IWL<320> VDD_CORE VSS / RM_IHPSG13_256x32_c2_1P_COLUMN_pcell_0 +XCOL<4> A_BLC<9> A_BLC<8> A_BLC_TOP<9> A_BLC_TOP<8> A_BLT<9> A_BLT<8> A_BLT_TOP<9> A_BLT_TOP<8> A_IWL<255> A_IWL<254> A_IWL<253> A_IWL<252> A_IWL<251> A_IWL<250> A_IWL<249> A_IWL<248> A_IWL<247> A_IWL<246> A_IWL<245> A_IWL<244> A_IWL<243> A_IWL<242> A_IWL<241> A_IWL<240> A_IWL<239> A_IWL<238> A_IWL<237> A_IWL<236> A_IWL<235> A_IWL<234> A_IWL<233> A_IWL<232> A_IWL<231> A_IWL<230> A_IWL<229> A_IWL<228> A_IWL<227> A_IWL<226> A_IWL<225> A_IWL<224> A_IWL<223> A_IWL<222> A_IWL<221> A_IWL<220> A_IWL<219> A_IWL<218> A_IWL<217> A_IWL<216> A_IWL<215> A_IWL<214> A_IWL<213> A_IWL<212> A_IWL<211> A_IWL<210> A_IWL<209> A_IWL<208> A_IWL<207> A_IWL<206> A_IWL<205> A_IWL<204> A_IWL<203> A_IWL<202> A_IWL<201> A_IWL<200> A_IWL<199> A_IWL<198> A_IWL<197> A_IWL<196> A_IWL<195> A_IWL<194> A_IWL<193> A_IWL<192> A_IWL<319> A_IWL<318> A_IWL<317> A_IWL<316> A_IWL<315> A_IWL<314> A_IWL<313> A_IWL<312> A_IWL<311> A_IWL<310> A_IWL<309> A_IWL<308> A_IWL<307> A_IWL<306> A_IWL<305> A_IWL<304> A_IWL<303> A_IWL<302> A_IWL<301> A_IWL<300> A_IWL<299> A_IWL<298> A_IWL<297> A_IWL<296> A_IWL<295> A_IWL<294> A_IWL<293> A_IWL<292> A_IWL<291> A_IWL<290> A_IWL<289> A_IWL<288> A_IWL<287> A_IWL<286> A_IWL<285> A_IWL<284> A_IWL<283> A_IWL<282> A_IWL<281> A_IWL<280> A_IWL<279> A_IWL<278> A_IWL<277> A_IWL<276> A_IWL<275> A_IWL<274> A_IWL<273> A_IWL<272> A_IWL<271> A_IWL<270> A_IWL<269> A_IWL<268> A_IWL<267> A_IWL<266> A_IWL<265> A_IWL<264> A_IWL<263> A_IWL<262> A_IWL<261> A_IWL<260> A_IWL<259> A_IWL<258> A_IWL<257> A_IWL<256> VDD_CORE VSS / RM_IHPSG13_256x32_c2_1P_COLUMN_pcell_0 +XCOL<3> A_BLC<7> A_BLC<6> A_BLC_TOP<7> A_BLC_TOP<6> A_BLT<7> A_BLT<6> A_BLT_TOP<7> A_BLT_TOP<6> A_IWL<191> A_IWL<190> A_IWL<189> A_IWL<188> A_IWL<187> A_IWL<186> A_IWL<185> A_IWL<184> A_IWL<183> A_IWL<182> A_IWL<181> A_IWL<180> A_IWL<179> A_IWL<178> A_IWL<177> A_IWL<176> A_IWL<175> A_IWL<174> A_IWL<173> A_IWL<172> A_IWL<171> A_IWL<170> A_IWL<169> A_IWL<168> A_IWL<167> A_IWL<166> A_IWL<165> A_IWL<164> A_IWL<163> A_IWL<162> A_IWL<161> A_IWL<160> A_IWL<159> A_IWL<158> A_IWL<157> A_IWL<156> A_IWL<155> A_IWL<154> A_IWL<153> A_IWL<152> A_IWL<151> A_IWL<150> A_IWL<149> A_IWL<148> A_IWL<147> A_IWL<146> A_IWL<145> A_IWL<144> A_IWL<143> A_IWL<142> A_IWL<141> A_IWL<140> A_IWL<139> A_IWL<138> A_IWL<137> A_IWL<136> A_IWL<135> A_IWL<134> A_IWL<133> A_IWL<132> A_IWL<131> A_IWL<130> A_IWL<129> A_IWL<128> A_IWL<255> A_IWL<254> A_IWL<253> A_IWL<252> A_IWL<251> A_IWL<250> A_IWL<249> A_IWL<248> A_IWL<247> A_IWL<246> A_IWL<245> A_IWL<244> A_IWL<243> A_IWL<242> A_IWL<241> A_IWL<240> A_IWL<239> A_IWL<238> A_IWL<237> A_IWL<236> A_IWL<235> A_IWL<234> A_IWL<233> A_IWL<232> A_IWL<231> A_IWL<230> A_IWL<229> A_IWL<228> A_IWL<227> A_IWL<226> A_IWL<225> A_IWL<224> A_IWL<223> A_IWL<222> A_IWL<221> A_IWL<220> A_IWL<219> A_IWL<218> A_IWL<217> A_IWL<216> A_IWL<215> A_IWL<214> A_IWL<213> A_IWL<212> A_IWL<211> A_IWL<210> A_IWL<209> A_IWL<208> A_IWL<207> A_IWL<206> A_IWL<205> A_IWL<204> A_IWL<203> A_IWL<202> A_IWL<201> A_IWL<200> A_IWL<199> A_IWL<198> A_IWL<197> A_IWL<196> A_IWL<195> A_IWL<194> A_IWL<193> A_IWL<192> VDD_CORE VSS / RM_IHPSG13_256x32_c2_1P_COLUMN_pcell_0 +XCOL<2> A_BLC<5> A_BLC<4> A_BLC_TOP<5> A_BLC_TOP<4> A_BLT<5> A_BLT<4> A_BLT_TOP<5> A_BLT_TOP<4> A_IWL<127> A_IWL<126> A_IWL<125> A_IWL<124> A_IWL<123> A_IWL<122> A_IWL<121> A_IWL<120> A_IWL<119> A_IWL<118> A_IWL<117> A_IWL<116> A_IWL<115> A_IWL<114> A_IWL<113> A_IWL<112> A_IWL<111> A_IWL<110> A_IWL<109> A_IWL<108> A_IWL<107> A_IWL<106> A_IWL<105> A_IWL<104> A_IWL<103> A_IWL<102> A_IWL<101> A_IWL<100> A_IWL<99> A_IWL<98> A_IWL<97> A_IWL<96> A_IWL<95> A_IWL<94> A_IWL<93> A_IWL<92> A_IWL<91> A_IWL<90> A_IWL<89> A_IWL<88> A_IWL<87> A_IWL<86> A_IWL<85> A_IWL<84> A_IWL<83> A_IWL<82> A_IWL<81> A_IWL<80> A_IWL<79> A_IWL<78> A_IWL<77> A_IWL<76> A_IWL<75> A_IWL<74> A_IWL<73> A_IWL<72> A_IWL<71> A_IWL<70> A_IWL<69> A_IWL<68> A_IWL<67> A_IWL<66> A_IWL<65> A_IWL<64> A_IWL<191> A_IWL<190> A_IWL<189> A_IWL<188> A_IWL<187> A_IWL<186> A_IWL<185> A_IWL<184> A_IWL<183> A_IWL<182> A_IWL<181> A_IWL<180> A_IWL<179> A_IWL<178> A_IWL<177> A_IWL<176> A_IWL<175> A_IWL<174> A_IWL<173> A_IWL<172> A_IWL<171> A_IWL<170> A_IWL<169> A_IWL<168> A_IWL<167> A_IWL<166> A_IWL<165> A_IWL<164> A_IWL<163> A_IWL<162> A_IWL<161> A_IWL<160> A_IWL<159> A_IWL<158> A_IWL<157> A_IWL<156> A_IWL<155> A_IWL<154> A_IWL<153> A_IWL<152> A_IWL<151> A_IWL<150> A_IWL<149> A_IWL<148> A_IWL<147> A_IWL<146> A_IWL<145> A_IWL<144> A_IWL<143> A_IWL<142> A_IWL<141> A_IWL<140> A_IWL<139> A_IWL<138> A_IWL<137> A_IWL<136> A_IWL<135> A_IWL<134> A_IWL<133> A_IWL<132> A_IWL<131> A_IWL<130> A_IWL<129> A_IWL<128> VDD_CORE VSS / RM_IHPSG13_256x32_c2_1P_COLUMN_pcell_0 +XCOL<1> A_BLC<3> A_BLC<2> A_BLC_TOP<3> A_BLC_TOP<2> A_BLT<3> A_BLT<2> A_BLT_TOP<3> A_BLT_TOP<2> A_IWL<63> A_IWL<62> A_IWL<61> A_IWL<60> A_IWL<59> A_IWL<58> A_IWL<57> A_IWL<56> A_IWL<55> A_IWL<54> A_IWL<53> A_IWL<52> A_IWL<51> A_IWL<50> A_IWL<49> A_IWL<48> A_IWL<47> A_IWL<46> A_IWL<45> A_IWL<44> A_IWL<43> A_IWL<42> A_IWL<41> A_IWL<40> A_IWL<39> A_IWL<38> A_IWL<37> A_IWL<36> A_IWL<35> A_IWL<34> A_IWL<33> A_IWL<32> A_IWL<31> A_IWL<30> A_IWL<29> A_IWL<28> A_IWL<27> A_IWL<26> A_IWL<25> A_IWL<24> A_IWL<23> A_IWL<22> A_IWL<21> A_IWL<20> A_IWL<19> A_IWL<18> A_IWL<17> A_IWL<16> A_IWL<15> A_IWL<14> A_IWL<13> A_IWL<12> A_IWL<11> A_IWL<10> A_IWL<9> A_IWL<8> A_IWL<7> A_IWL<6> A_IWL<5> A_IWL<4> A_IWL<3> A_IWL<2> A_IWL<1> A_IWL<0> A_IWL<127> A_IWL<126> A_IWL<125> A_IWL<124> A_IWL<123> A_IWL<122> A_IWL<121> A_IWL<120> A_IWL<119> A_IWL<118> A_IWL<117> A_IWL<116> A_IWL<115> A_IWL<114> A_IWL<113> A_IWL<112> A_IWL<111> A_IWL<110> A_IWL<109> A_IWL<108> A_IWL<107> A_IWL<106> A_IWL<105> A_IWL<104> A_IWL<103> A_IWL<102> A_IWL<101> A_IWL<100> A_IWL<99> A_IWL<98> A_IWL<97> A_IWL<96> A_IWL<95> A_IWL<94> A_IWL<93> A_IWL<92> A_IWL<91> A_IWL<90> A_IWL<89> A_IWL<88> A_IWL<87> A_IWL<86> A_IWL<85> A_IWL<84> A_IWL<83> A_IWL<82> A_IWL<81> A_IWL<80> A_IWL<79> A_IWL<78> A_IWL<77> A_IWL<76> A_IWL<75> A_IWL<74> A_IWL<73> A_IWL<72> A_IWL<71> A_IWL<70> A_IWL<69> A_IWL<68> A_IWL<67> A_IWL<66> A_IWL<65> A_IWL<64> VDD_CORE VSS / RM_IHPSG13_256x32_c2_1P_COLUMN_pcell_0 +XCOL<0> A_BLC<1> A_BLC<0> A_BLC_TOP<1> A_BLC_TOP<0> A_BLT<1> A_BLT<0> A_BLT_TOP<1> A_BLT_TOP<0> A_WL<63> A_WL<62> A_WL<61> A_WL<60> A_WL<59> A_WL<58> A_WL<57> A_WL<56> A_WL<55> A_WL<54> A_WL<53> A_WL<52> A_WL<51> A_WL<50> A_WL<49> A_WL<48> A_WL<47> A_WL<46> A_WL<45> A_WL<44> A_WL<43> A_WL<42> A_WL<41> A_WL<40> A_WL<39> A_WL<38> A_WL<37> A_WL<36> A_WL<35> A_WL<34> A_WL<33> A_WL<32> A_WL<31> A_WL<30> A_WL<29> A_WL<28> A_WL<27> A_WL<26> A_WL<25> A_WL<24> A_WL<23> A_WL<22> A_WL<21> A_WL<20> A_WL<19> A_WL<18> A_WL<17> A_WL<16> A_WL<15> A_WL<14> A_WL<13> A_WL<12> A_WL<11> A_WL<10> A_WL<9> A_WL<8> A_WL<7> A_WL<6> A_WL<5> A_WL<4> A_WL<3> A_WL<2> A_WL<1> A_WL<0> A_IWL<63> A_IWL<62> A_IWL<61> A_IWL<60> A_IWL<59> A_IWL<58> A_IWL<57> A_IWL<56> A_IWL<55> A_IWL<54> A_IWL<53> A_IWL<52> A_IWL<51> A_IWL<50> A_IWL<49> A_IWL<48> A_IWL<47> A_IWL<46> A_IWL<45> A_IWL<44> A_IWL<43> A_IWL<42> A_IWL<41> A_IWL<40> A_IWL<39> A_IWL<38> A_IWL<37> A_IWL<36> A_IWL<35> A_IWL<34> A_IWL<33> A_IWL<32> A_IWL<31> A_IWL<30> A_IWL<29> A_IWL<28> A_IWL<27> A_IWL<26> A_IWL<25> A_IWL<24> A_IWL<23> A_IWL<22> A_IWL<21> A_IWL<20> A_IWL<19> A_IWL<18> A_IWL<17> A_IWL<16> A_IWL<15> A_IWL<14> A_IWL<13> A_IWL<12> A_IWL<11> A_IWL<10> A_IWL<9> A_IWL<8> A_IWL<7> A_IWL<6> A_IWL<5> A_IWL<4> A_IWL<3> A_IWL<2> A_IWL<1> A_IWL<0> VDD_CORE VSS / RM_IHPSG13_256x32_c2_1P_COLUMN_pcell_0 +.ENDS + + + + +.SUBCKT RM_IHPSG13_256x32_c2_1P_DLY_pcell_2 A Z VDD VSS + XIDL D<7> Z VDD VSS / RSC_IHPSG13_CDLYX1 + XIDM<7> D<6> D<7> VDD VSS / RSC_IHPSG13_CDLYX1_DUMMY + XIDM<6> D<5> D<6> VDD VSS / RSC_IHPSG13_CDLYX1_DUMMY + XIDM<5> D<4> D<5> VDD VSS / RSC_IHPSG13_CDLYX1_DUMMY + XIDM<4> D<3> D<4> VDD VSS / RSC_IHPSG13_CDLYX1_DUMMY + XIDM<3> D<2> D<3> VDD VSS / RSC_IHPSG13_CDLYX1_DUMMY + XIDM<2> D<1> D<2> VDD VSS / RSC_IHPSG13_CDLYX1_DUMMY + XIDM<1> A D<1> VDD VSS / RSC_IHPSG13_CDLYX1_DUMMY +.ENDS + + +.SUBCKT RM_IHPSG13_256x32_c2_1P_DLY_pcell_3 A Z VDD VSS + XIDM<8> D<7> Z VDD VSS / RSC_IHPSG13_CDLYX1_DUMMY + XIDM<7> D<6> D<7> VDD VSS / RSC_IHPSG13_CDLYX1_DUMMY + XIDM<6> D<5> D<6> VDD VSS / RSC_IHPSG13_CDLYX1_DUMMY + XIDM<5> D<4> D<5> VDD VSS / RSC_IHPSG13_CDLYX1_DUMMY + XIDM<4> D<3> D<4> VDD VSS / RSC_IHPSG13_CDLYX1_DUMMY + XIDM<3> D<2> D<3> VDD VSS / RSC_IHPSG13_CDLYX1_DUMMY + XIDM<2> D<1> D<2> VDD VSS / RSC_IHPSG13_CDLYX1_DUMMY + XIDM<1> A D<1> VDD VSS / RSC_IHPSG13_CDLYX1_DUMMY +.ENDS + + + +.SUBCKT RM_IHPSG13_1P_256x32_c2_bm_bist A_ADDR<7> A_ADDR<6> A_ADDR<5> A_ADDR<4> A_ADDR<3> A_ADDR<2> A_ADDR<1> A_ADDR<0> A_BIST_ADDR<7> A_BIST_ADDR<6> A_BIST_ADDR<5> A_BIST_ADDR<4> A_BIST_ADDR<3> A_BIST_ADDR<2> A_BIST_ADDR<1> A_BIST_ADDR<0> A_BIST_BM<31> A_BIST_BM<30> A_BIST_BM<29> A_BIST_BM<28> A_BIST_BM<27> A_BIST_BM<26> A_BIST_BM<25> A_BIST_BM<24> A_BIST_BM<23> A_BIST_BM<22> A_BIST_BM<21> A_BIST_BM<20> A_BIST_BM<19> A_BIST_BM<18> A_BIST_BM<17> A_BIST_BM<16> A_BIST_BM<15> A_BIST_BM<14> A_BIST_BM<13> A_BIST_BM<12> A_BIST_BM<11> A_BIST_BM<10> A_BIST_BM<9> A_BIST_BM<8> A_BIST_BM<7> A_BIST_BM<6> A_BIST_BM<5> A_BIST_BM<4> A_BIST_BM<3> A_BIST_BM<2> A_BIST_BM<1> A_BIST_BM<0> A_BIST_CLK A_BIST_DIN<31> A_BIST_DIN<30> A_BIST_DIN<29> A_BIST_DIN<28> A_BIST_DIN<27> A_BIST_DIN<26> A_BIST_DIN<25> A_BIST_DIN<24> A_BIST_DIN<23> A_BIST_DIN<22> A_BIST_DIN<21> A_BIST_DIN<20> A_BIST_DIN<19> A_BIST_DIN<18> A_BIST_DIN<17> A_BIST_DIN<16> A_BIST_DIN<15> A_BIST_DIN<14> A_BIST_DIN<13> A_BIST_DIN<12> A_BIST_DIN<11> A_BIST_DIN<10> A_BIST_DIN<9> A_BIST_DIN<8> A_BIST_DIN<7> A_BIST_DIN<6> A_BIST_DIN<5> A_BIST_DIN<4> A_BIST_DIN<3> A_BIST_DIN<2> A_BIST_DIN<1> A_BIST_DIN<0> A_BIST_EN A_BIST_MEN A_BIST_REN A_BIST_WEN A_BM<31> A_BM<30> A_BM<29> A_BM<28> A_BM<27> A_BM<26> A_BM<25> A_BM<24> A_BM<23> A_BM<22> A_BM<21> A_BM<20> A_BM<19> A_BM<18> A_BM<17> A_BM<16> A_BM<15> A_BM<14> A_BM<13> A_BM<12> A_BM<11> A_BM<10> A_BM<9> A_BM<8> A_BM<7> A_BM<6> A_BM<5> A_BM<4> A_BM<3> A_BM<2> A_BM<1> A_BM<0> A_CLK A_DIN<31> A_DIN<30> A_DIN<29> A_DIN<28> A_DIN<27> A_DIN<26> A_DIN<25> A_DIN<24> A_DIN<23> A_DIN<22> A_DIN<21> A_DIN<20> A_DIN<19> A_DIN<18> A_DIN<17> A_DIN<16> A_DIN<15> A_DIN<14> A_DIN<13> A_DIN<12> A_DIN<11> A_DIN<10> A_DIN<9> A_DIN<8> A_DIN<7> A_DIN<6> A_DIN<5> A_DIN<4> A_DIN<3> A_DIN<2> A_DIN<1> A_DIN<0> A_DLY A_DOUT<31> A_DOUT<30> A_DOUT<29> A_DOUT<28> A_DOUT<27> A_DOUT<26> A_DOUT<25> A_DOUT<24> A_DOUT<23> A_DOUT<22> A_DOUT<21> A_DOUT<20> A_DOUT<19> A_DOUT<18> A_DOUT<17> A_DOUT<16> A_DOUT<15> A_DOUT<14> A_DOUT<13> A_DOUT<12> A_DOUT<11> A_DOUT<10> A_DOUT<9> A_DOUT<8> A_DOUT<7> A_DOUT<6> A_DOUT<5> A_DOUT<4> A_DOUT<3> A_DOUT<2> A_DOUT<1> A_DOUT<0> A_MEN A_REN A_WEN VDD! VDDARRAY! VSS! + + +XRAM<1> a_blc_r<63> a_blc_r<62> a_blc_r<61> a_blc_r<60> a_blc_r<59> a_blc_r<58> a_blc_r<57> a_blc_r<56> a_blc_r<55> a_blc_r<54> a_blc_r<53> a_blc_r<52> a_blc_r<51> a_blc_r<50> a_blc_r<49> a_blc_r<48> a_blc_r<47> a_blc_r<46> a_blc_r<45> a_blc_r<44> a_blc_r<43> a_blc_r<42> a_blc_r<41> a_blc_r<40> a_blc_r<39> a_blc_r<38> a_blc_r<37> a_blc_r<36> a_blc_r<35> a_blc_r<34> a_blc_r<33> a_blc_r<32> a_blc_r<31> a_blc_r<30> a_blc_r<29> a_blc_r<28> a_blc_r<27> a_blc_r<26> a_blc_r<25> a_blc_r<24> a_blc_r<23> a_blc_r<22> a_blc_r<21> a_blc_r<20> a_blc_r<19> a_blc_r<18> a_blc_r<17> a_blc_r<16> a_blc_r<15> a_blc_r<14> a_blc_r<13> a_blc_r<12> a_blc_r<11> a_blc_r<10> a_blc_r<9> a_blc_r<8> a_blc_r<7> a_blc_r<6> a_blc_r<5> a_blc_r<4> a_blc_r<3> a_blc_r<2> a_blc_r<1> a_blc_r<0> a_blt_r<63> a_blt_r<62> a_blt_r<61> a_blt_r<60> a_blt_r<59> a_blt_r<58> a_blt_r<57> a_blt_r<56> a_blt_r<55> a_blt_r<54> a_blt_r<53> a_blt_r<52> a_blt_r<51> a_blt_r<50> a_blt_r<49> a_blt_r<48> a_blt_r<47> a_blt_r<46> a_blt_r<45> a_blt_r<44> a_blt_r<43> a_blt_r<42> a_blt_r<41> a_blt_r<40> a_blt_r<39> a_blt_r<38> a_blt_r<37> a_blt_r<36> a_blt_r<35> a_blt_r<34> a_blt_r<33> a_blt_r<32> a_blt_r<31> a_blt_r<30> a_blt_r<29> a_blt_r<28> a_blt_r<27> a_blt_r<26> a_blt_r<25> a_blt_r<24> a_blt_r<23> a_blt_r<22> a_blt_r<21> a_blt_r<20> a_blt_r<19> a_blt_r<18> a_blt_r<17> a_blt_r<16> a_blt_r<15> a_blt_r<14> a_blt_r<13> a_blt_r<12> a_blt_r<11> a_blt_r<10> a_blt_r<9> a_blt_r<8> a_blt_r<7> a_blt_r<6> a_blt_r<5> a_blt_r<4> a_blt_r<3> a_blt_r<2> a_blt_r<1> a_blt_r<0> a_wl_r<63> a_wl_r<62> a_wl_r<61> a_wl_r<60> a_wl_r<59> a_wl_r<58> a_wl_r<57> a_wl_r<56> a_wl_r<55> a_wl_r<54> a_wl_r<53> a_wl_r<52> a_wl_r<51> a_wl_r<50> a_wl_r<49> a_wl_r<48> a_wl_r<47> a_wl_r<46> a_wl_r<45> a_wl_r<44> a_wl_r<43> a_wl_r<42> a_wl_r<41> a_wl_r<40> a_wl_r<39> a_wl_r<38> a_wl_r<37> a_wl_r<36> a_wl_r<35> a_wl_r<34> a_wl_r<33> a_wl_r<32> a_wl_r<31> a_wl_r<30> a_wl_r<29> a_wl_r<28> a_wl_r<27> a_wl_r<26> a_wl_r<25> a_wl_r<24> a_wl_r<23> a_wl_r<22> a_wl_r<21> a_wl_r<20> a_wl_r<19> a_wl_r<18> a_wl_r<17> a_wl_r<16> a_wl_r<15> a_wl_r<14> a_wl_r<13> a_wl_r<12> a_wl_r<11> a_wl_r<10> a_wl_r<9> a_wl_r<8> a_wl_r<7> a_wl_r<6> a_wl_r<5> a_wl_r<4> a_wl_r<3> a_wl_r<2> a_wl_r<1> a_wl_r<0> VDDARRAY! VSS! / RM_IHPSG13_256x32_c2_1P_MATRIX_pcell_1 +XRAM<0> a_blc_l<63> a_blc_l<62> a_blc_l<61> a_blc_l<60> a_blc_l<59> a_blc_l<58> a_blc_l<57> a_blc_l<56> a_blc_l<55> a_blc_l<54> a_blc_l<53> a_blc_l<52> a_blc_l<51> a_blc_l<50> a_blc_l<49> a_blc_l<48> a_blc_l<47> a_blc_l<46> a_blc_l<45> a_blc_l<44> a_blc_l<43> a_blc_l<42> a_blc_l<41> a_blc_l<40> a_blc_l<39> a_blc_l<38> a_blc_l<37> a_blc_l<36> a_blc_l<35> a_blc_l<34> a_blc_l<33> a_blc_l<32> a_blc_l<31> a_blc_l<30> a_blc_l<29> a_blc_l<28> a_blc_l<27> a_blc_l<26> a_blc_l<25> a_blc_l<24> a_blc_l<23> a_blc_l<22> a_blc_l<21> a_blc_l<20> a_blc_l<19> a_blc_l<18> a_blc_l<17> a_blc_l<16> a_blc_l<15> a_blc_l<14> a_blc_l<13> a_blc_l<12> a_blc_l<11> a_blc_l<10> a_blc_l<9> a_blc_l<8> a_blc_l<7> a_blc_l<6> a_blc_l<5> a_blc_l<4> a_blc_l<3> a_blc_l<2> a_blc_l<1> a_blc_l<0> a_blt_l<63> a_blt_l<62> a_blt_l<61> a_blt_l<60> a_blt_l<59> a_blt_l<58> a_blt_l<57> a_blt_l<56> a_blt_l<55> a_blt_l<54> a_blt_l<53> a_blt_l<52> a_blt_l<51> a_blt_l<50> a_blt_l<49> a_blt_l<48> a_blt_l<47> a_blt_l<46> a_blt_l<45> a_blt_l<44> a_blt_l<43> a_blt_l<42> a_blt_l<41> a_blt_l<40> a_blt_l<39> a_blt_l<38> a_blt_l<37> a_blt_l<36> a_blt_l<35> a_blt_l<34> a_blt_l<33> a_blt_l<32> a_blt_l<31> a_blt_l<30> a_blt_l<29> a_blt_l<28> a_blt_l<27> a_blt_l<26> a_blt_l<25> a_blt_l<24> a_blt_l<23> a_blt_l<22> a_blt_l<21> a_blt_l<20> a_blt_l<19> a_blt_l<18> a_blt_l<17> a_blt_l<16> a_blt_l<15> a_blt_l<14> a_blt_l<13> a_blt_l<12> a_blt_l<11> a_blt_l<10> a_blt_l<9> a_blt_l<8> a_blt_l<7> a_blt_l<6> a_blt_l<5> a_blt_l<4> a_blt_l<3> a_blt_l<2> a_blt_l<1> a_blt_l<0> a_wl_l<63> a_wl_l<62> a_wl_l<61> a_wl_l<60> a_wl_l<59> a_wl_l<58> a_wl_l<57> a_wl_l<56> a_wl_l<55> a_wl_l<54> a_wl_l<53> a_wl_l<52> a_wl_l<51> a_wl_l<50> a_wl_l<49> a_wl_l<48> a_wl_l<47> a_wl_l<46> a_wl_l<45> a_wl_l<44> a_wl_l<43> a_wl_l<42> a_wl_l<41> a_wl_l<40> a_wl_l<39> a_wl_l<38> a_wl_l<37> a_wl_l<36> a_wl_l<35> a_wl_l<34> a_wl_l<33> a_wl_l<32> a_wl_l<31> a_wl_l<30> a_wl_l<29> a_wl_l<28> a_wl_l<27> a_wl_l<26> a_wl_l<25> a_wl_l<24> a_wl_l<23> a_wl_l<22> a_wl_l<21> a_wl_l<20> a_wl_l<19> a_wl_l<18> a_wl_l<17> a_wl_l<16> a_wl_l<15> a_wl_l<14> a_wl_l<13> a_wl_l<12> a_wl_l<11> a_wl_l<10> a_wl_l<9> a_wl_l<8> a_wl_l<7> a_wl_l<6> a_wl_l<5> a_wl_l<4> a_wl_l<3> a_wl_l<2> a_wl_l<1> a_wl_l<0> VDDARRAY! VSS! / RM_IHPSG13_256x32_c2_1P_MATRIX_pcell_1 + + +XA_COLDRV<1> a_addr_col<1> a_addr_col<0> a_addr_col_r<1> a_addr_col_r<0> a_addr_dec<7> a_addr_dec<6> a_addr_dec<5> a_addr_dec<4> a_addr_dec<3> a_addr_dec<2> a_addr_dec<1> a_addr_dec<0> a_addr_dec_r<7> a_addr_dec_r<6> a_addr_dec_r<5> a_addr_dec_r<4> a_addr_dec_r<3> a_addr_dec_r<2> a_addr_dec_r<1> a_addr_dec_r<0> a_dclk a_dclk_p_r<0> a_rclk a_rclk_p_r<0> a_wclk a_wclk_p_r<0> VDD! VSS! / RM_IHPSG13_256x32_c2_1P_COLDRV13X4 +XA_COLDRV<0> a_addr_col<1> a_addr_col<0> a_addr_col_l<1> a_addr_col_l<0> a_addr_dec<7> a_addr_dec<6> a_addr_dec<5> a_addr_dec<4> a_addr_dec<3> a_addr_dec<2> a_addr_dec<1> a_addr_dec<0> a_addr_dec_l<7> a_addr_dec_l<6> a_addr_dec_l<5> a_addr_dec_l<4> a_addr_dec_l<3> a_addr_dec_l<2> a_addr_dec_l<1> a_addr_dec_l<0> a_dclk a_dclk_p_l<0> a_rclk a_rclk_p_l<0> a_wclk a_wclk_p_l<0> VDD! VSS! / RM_IHPSG13_256x32_c2_1P_COLDRV13X4 + + +XA_WLDRV<7> a_wi<63> a_wi<62> a_wi<61> a_wi<60> a_wi<59> a_wi<58> a_wi<57> a_wi<56> a_wi<55> a_wi<54> a_wi<53> a_wi<52> a_wi<51> a_wi<50> a_wi<49> a_wi<48> a_wl_r<63> a_wl_r<62> a_wl_r<61> a_wl_r<60> a_wl_r<59> a_wl_r<58> a_wl_r<57> a_wl_r<56> a_wl_r<55> a_wl_r<54> a_wl_r<53> a_wl_r<52> a_wl_r<51> a_wl_r<50> a_wl_r<49> a_wl_r<48> VDD! VSS! / RM_IHPSG13_256x32_c2_1P_WLDRV16X4 +XA_WLDRV<6> a_wi<47> a_wi<46> a_wi<45> a_wi<44> a_wi<43> a_wi<42> a_wi<41> a_wi<40> a_wi<39> a_wi<38> a_wi<37> a_wi<36> a_wi<35> a_wi<34> a_wi<33> a_wi<32> a_wl_r<47> a_wl_r<46> a_wl_r<45> a_wl_r<44> a_wl_r<43> a_wl_r<42> a_wl_r<41> a_wl_r<40> a_wl_r<39> a_wl_r<38> a_wl_r<37> a_wl_r<36> a_wl_r<35> a_wl_r<34> a_wl_r<33> a_wl_r<32> VDD! VSS! / RM_IHPSG13_256x32_c2_1P_WLDRV16X4 +XA_WLDRV<5> a_wi<31> a_wi<30> a_wi<29> a_wi<28> a_wi<27> a_wi<26> a_wi<25> a_wi<24> a_wi<23> a_wi<22> a_wi<21> a_wi<20> a_wi<19> a_wi<18> a_wi<17> a_wi<16> a_wl_r<31> a_wl_r<30> a_wl_r<29> a_wl_r<28> a_wl_r<27> a_wl_r<26> a_wl_r<25> a_wl_r<24> a_wl_r<23> a_wl_r<22> a_wl_r<21> a_wl_r<20> a_wl_r<19> a_wl_r<18> a_wl_r<17> a_wl_r<16> VDD! VSS! / RM_IHPSG13_256x32_c2_1P_WLDRV16X4 +XA_WLDRV<4> a_wi<15> a_wi<14> a_wi<13> a_wi<12> a_wi<11> a_wi<10> a_wi<9> a_wi<8> a_wi<7> a_wi<6> a_wi<5> a_wi<4> a_wi<3> a_wi<2> a_wi<1> a_wi<0> a_wl_r<15> a_wl_r<14> a_wl_r<13> a_wl_r<12> a_wl_r<11> a_wl_r<10> a_wl_r<9> a_wl_r<8> a_wl_r<7> a_wl_r<6> a_wl_r<5> a_wl_r<4> a_wl_r<3> a_wl_r<2> a_wl_r<1> a_wl_r<0> VDD! VSS! / RM_IHPSG13_256x32_c2_1P_WLDRV16X4 +XA_WLDRV<3> a_wi<63> a_wi<62> a_wi<61> a_wi<60> a_wi<59> a_wi<58> a_wi<57> a_wi<56> a_wi<55> a_wi<54> a_wi<53> a_wi<52> a_wi<51> a_wi<50> a_wi<49> a_wi<48> a_wl_l<63> a_wl_l<62> a_wl_l<61> a_wl_l<60> a_wl_l<59> a_wl_l<58> a_wl_l<57> a_wl_l<56> a_wl_l<55> a_wl_l<54> a_wl_l<53> a_wl_l<52> a_wl_l<51> a_wl_l<50> a_wl_l<49> a_wl_l<48> VDD! VSS! / RM_IHPSG13_256x32_c2_1P_WLDRV16X4 +XA_WLDRV<2> a_wi<47> a_wi<46> a_wi<45> a_wi<44> a_wi<43> a_wi<42> a_wi<41> a_wi<40> a_wi<39> a_wi<38> a_wi<37> a_wi<36> a_wi<35> a_wi<34> a_wi<33> a_wi<32> a_wl_l<47> a_wl_l<46> a_wl_l<45> a_wl_l<44> a_wl_l<43> a_wl_l<42> a_wl_l<41> a_wl_l<40> a_wl_l<39> a_wl_l<38> a_wl_l<37> a_wl_l<36> a_wl_l<35> a_wl_l<34> a_wl_l<33> a_wl_l<32> VDD! VSS! / RM_IHPSG13_256x32_c2_1P_WLDRV16X4 +XA_WLDRV<1> a_wi<31> a_wi<30> a_wi<29> a_wi<28> a_wi<27> a_wi<26> a_wi<25> a_wi<24> a_wi<23> a_wi<22> a_wi<21> a_wi<20> a_wi<19> a_wi<18> a_wi<17> a_wi<16> a_wl_l<31> a_wl_l<30> a_wl_l<29> a_wl_l<28> a_wl_l<27> a_wl_l<26> a_wl_l<25> a_wl_l<24> a_wl_l<23> a_wl_l<22> a_wl_l<21> a_wl_l<20> a_wl_l<19> a_wl_l<18> a_wl_l<17> a_wl_l<16> VDD! VSS! / RM_IHPSG13_256x32_c2_1P_WLDRV16X4 +XA_WLDRV<0> a_wi<15> a_wi<14> a_wi<13> a_wi<12> a_wi<11> a_wi<10> a_wi<9> a_wi<8> a_wi<7> a_wi<6> a_wi<5> a_wi<4> a_wi<3> a_wi<2> a_wi<1> a_wi<0> a_wl_l<15> a_wl_l<14> a_wl_l<13> a_wl_l<12> a_wl_l<11> a_wl_l<10> a_wl_l<9> a_wl_l<8> a_wl_l<7> a_wl_l<6> a_wl_l<5> a_wl_l<4> a_wl_l<3> a_wl_l<2> a_wl_l<1> a_wl_l<0> VDD! VSS! / RM_IHPSG13_256x32_c2_1P_WLDRV16X4 + + +XA_CTRL a_aclk_n A_BIST_CLK A_BIST_MEN A_BIST_EN A_BIST_REN A_BIST_WEN a_tiel A_CLK A_MEN a_dclk a_eclk a_pulse_h a_pulse_l a_pulse a_rclk A_REN a_cs a_wclk A_WEN VDD! VSS! / RM_IHPSG13_256x32_c2_1P_CTRL + + +XA_ROWDEC a_addr_row<5> a_addr_row<4> a_addr_row<3> a_addr_row<2> a_addr_row<1> a_addr_row<0> a_cs a_eclk a_wi<63> a_wi<62> a_wi<61> a_wi<60> a_wi<59> a_wi<58> a_wi<57> a_wi<56> a_wi<55> a_wi<54> a_wi<53> a_wi<52> a_wi<51> a_wi<50> a_wi<49> a_wi<48> a_wi<47> a_wi<46> a_wi<45> a_wi<44> a_wi<43> a_wi<42> a_wi<41> a_wi<40> a_wi<39> a_wi<38> a_wi<37> a_wi<36> a_wi<35> a_wi<34> a_wi<33> a_wi<32> a_wi<31> a_wi<30> a_wi<29> a_wi<28> a_wi<27> a_wi<26> a_wi<25> a_wi<24> a_wi<23> a_wi<22> a_wi<21> a_wi<20> a_wi<19> a_wi<18> a_wi<17> a_wi<16> a_wi<15> a_wi<14> a_wi<13> a_wi<12> a_wi<11> a_wi<10> a_wi<9> a_wi<8> a_wi<7> a_wi<6> a_wi<5> a_wi<4> a_wi<3> a_wi<2> a_wi<1> a_wi<0> VDD! VSS! / RM_IHPSG13_256x32_c2_1P_ROWDEC6 +XA_ROWREG a_aclk_n A_ADDR<7> A_ADDR<6> A_ADDR<5> A_ADDR<4> A_ADDR<3> A_ADDR<2> a_addr_row<5> a_addr_row<4> a_addr_row<3> a_addr_row<2> a_addr_row<1> a_addr_row<0> A_BIST_ADDR<7> A_BIST_ADDR<6> A_BIST_ADDR<5> A_BIST_ADDR<4> A_BIST_ADDR<3> A_BIST_ADDR<2> A_BIST_EN VDD! VSS! / RM_IHPSG13_256x32_c2_1P_ROWREG6 +XA_COLDEC a_aclk_n A_ADDR<1> A_ADDR<0> a_addr_col<1> a_addr_col<0> a_addr_dec<7> a_addr_dec<6> a_addr_dec<5> a_addr_dec<4> a_addr_dec<3> a_addr_dec<2> a_addr_dec<1> a_addr_dec<0> A_BIST_ADDR<1> A_BIST_ADDR<0> A_BIST_EN VDD! VSS! / RM_IHPSG13_256x32_c2_1P_COLDEC2 + + +XA_DLYH a_pulse a_pulse_h VDD! VSS! / RM_IHPSG13_256x32_c2_1P_DLY_pcell_2 +XA_DLYL a_pulse_x a_pulse_l VDD! VSS! / RM_IHPSG13_256x32_c2_1P_DLY_pcell_3 +XA_DLYMUX a_pulse_h A_DLY a_pulse_x VDD! VSS! / RM_IHPSG13_256x32_c2_1P_DLY_MUX + +XCOLCTRL<31> a_addr_dec_r<3> a_addr_dec_r<2> a_addr_dec_r<1> a_addr_dec_r<0> A_BIST_BM<31> A_BIST_DIN<31> A_BIST_EN a_blc_r<63> a_blc_r<62> a_blc_r<61> a_blc_r<60> a_blt_r<63> a_blt_r<62> a_blt_r<61> a_blt_r<60> A_BM<31> a_dclk_n_r<15> a_dclk_n_r<16> a_dclk_p_r<15> a_dclk_p_r<16> A_DOUT<31> A_DIN<31> a_rclk_n_r<15> a_rclk_n_r<16> a_rclk_p_r<15> a_rclk_p_r<16> a_tieh<31> a_wclk_n_r<15> a_wclk_n_r<16> a_wclk_p_r<15> a_wclk_p_r<16> VDD! VSS! / RM_IHPSG13_256x32_c2_1P_COLCTRL2 +XCOLCTRL<30> a_addr_dec_r<3> a_addr_dec_r<2> a_addr_dec_r<1> a_addr_dec_r<0> A_BIST_BM<30> A_BIST_DIN<30> A_BIST_EN a_blc_r<59> a_blc_r<58> a_blc_r<57> a_blc_r<56> a_blt_r<59> a_blt_r<58> a_blt_r<57> a_blt_r<56> A_BM<30> a_dclk_n_r<14> a_dclk_n_r<15> a_dclk_p_r<14> a_dclk_p_r<15> A_DOUT<30> A_DIN<30> a_rclk_n_r<14> a_rclk_n_r<15> a_rclk_p_r<14> a_rclk_p_r<15> a_tieh<30> a_wclk_n_r<14> a_wclk_n_r<15> a_wclk_p_r<14> a_wclk_p_r<15> VDD! VSS! / RM_IHPSG13_256x32_c2_1P_COLCTRL2 +XCOLCTRL<29> a_addr_dec_r<3> a_addr_dec_r<2> a_addr_dec_r<1> a_addr_dec_r<0> A_BIST_BM<29> A_BIST_DIN<29> A_BIST_EN a_blc_r<55> a_blc_r<54> a_blc_r<53> a_blc_r<52> a_blt_r<55> a_blt_r<54> a_blt_r<53> a_blt_r<52> A_BM<29> a_dclk_n_r<13> a_dclk_n_r<14> a_dclk_p_r<13> a_dclk_p_r<14> A_DOUT<29> A_DIN<29> a_rclk_n_r<13> a_rclk_n_r<14> a_rclk_p_r<13> a_rclk_p_r<14> a_tieh<29> a_wclk_n_r<13> a_wclk_n_r<14> a_wclk_p_r<13> a_wclk_p_r<14> VDD! VSS! / RM_IHPSG13_256x32_c2_1P_COLCTRL2 +XCOLCTRL<28> a_addr_dec_r<3> a_addr_dec_r<2> a_addr_dec_r<1> a_addr_dec_r<0> A_BIST_BM<28> A_BIST_DIN<28> A_BIST_EN a_blc_r<51> a_blc_r<50> a_blc_r<49> a_blc_r<48> a_blt_r<51> a_blt_r<50> a_blt_r<49> a_blt_r<48> A_BM<28> a_dclk_n_r<12> a_dclk_n_r<13> a_dclk_p_r<12> a_dclk_p_r<13> A_DOUT<28> A_DIN<28> a_rclk_n_r<12> a_rclk_n_r<13> a_rclk_p_r<12> a_rclk_p_r<13> a_tieh<28> a_wclk_n_r<12> a_wclk_n_r<13> a_wclk_p_r<12> a_wclk_p_r<13> VDD! VSS! / RM_IHPSG13_256x32_c2_1P_COLCTRL2 +XCOLCTRL<27> a_addr_dec_r<3> a_addr_dec_r<2> a_addr_dec_r<1> a_addr_dec_r<0> A_BIST_BM<27> A_BIST_DIN<27> A_BIST_EN a_blc_r<47> a_blc_r<46> a_blc_r<45> a_blc_r<44> a_blt_r<47> a_blt_r<46> a_blt_r<45> a_blt_r<44> A_BM<27> a_dclk_n_r<11> a_dclk_n_r<12> a_dclk_p_r<11> a_dclk_p_r<12> A_DOUT<27> A_DIN<27> a_rclk_n_r<11> a_rclk_n_r<12> a_rclk_p_r<11> a_rclk_p_r<12> a_tieh<27> a_wclk_n_r<11> a_wclk_n_r<12> a_wclk_p_r<11> a_wclk_p_r<12> VDD! VSS! / RM_IHPSG13_256x32_c2_1P_COLCTRL2 +XCOLCTRL<26> a_addr_dec_r<3> a_addr_dec_r<2> a_addr_dec_r<1> a_addr_dec_r<0> A_BIST_BM<26> A_BIST_DIN<26> A_BIST_EN a_blc_r<43> a_blc_r<42> a_blc_r<41> a_blc_r<40> a_blt_r<43> a_blt_r<42> a_blt_r<41> a_blt_r<40> A_BM<26> a_dclk_n_r<10> a_dclk_n_r<11> a_dclk_p_r<10> a_dclk_p_r<11> A_DOUT<26> A_DIN<26> a_rclk_n_r<10> a_rclk_n_r<11> a_rclk_p_r<10> a_rclk_p_r<11> a_tieh<26> a_wclk_n_r<10> a_wclk_n_r<11> a_wclk_p_r<10> a_wclk_p_r<11> VDD! VSS! / RM_IHPSG13_256x32_c2_1P_COLCTRL2 +XCOLCTRL<25> a_addr_dec_r<3> a_addr_dec_r<2> a_addr_dec_r<1> a_addr_dec_r<0> A_BIST_BM<25> A_BIST_DIN<25> A_BIST_EN a_blc_r<39> a_blc_r<38> a_blc_r<37> a_blc_r<36> a_blt_r<39> a_blt_r<38> a_blt_r<37> a_blt_r<36> A_BM<25> a_dclk_n_r<9> a_dclk_n_r<10> a_dclk_p_r<9> a_dclk_p_r<10> A_DOUT<25> A_DIN<25> a_rclk_n_r<9> a_rclk_n_r<10> a_rclk_p_r<9> a_rclk_p_r<10> a_tieh<25> a_wclk_n_r<9> a_wclk_n_r<10> a_wclk_p_r<9> a_wclk_p_r<10> VDD! VSS! / RM_IHPSG13_256x32_c2_1P_COLCTRL2 +XCOLCTRL<24> a_addr_dec_r<3> a_addr_dec_r<2> a_addr_dec_r<1> a_addr_dec_r<0> A_BIST_BM<24> A_BIST_DIN<24> A_BIST_EN a_blc_r<35> a_blc_r<34> a_blc_r<33> a_blc_r<32> a_blt_r<35> a_blt_r<34> a_blt_r<33> a_blt_r<32> A_BM<24> a_dclk_n_r<8> a_dclk_n_r<9> a_dclk_p_r<8> a_dclk_p_r<9> A_DOUT<24> A_DIN<24> a_rclk_n_r<8> a_rclk_n_r<9> a_rclk_p_r<8> a_rclk_p_r<9> a_tieh<24> a_wclk_n_r<8> a_wclk_n_r<9> a_wclk_p_r<8> a_wclk_p_r<9> VDD! VSS! / RM_IHPSG13_256x32_c2_1P_COLCTRL2 +XCOLCTRL<23> a_addr_dec_r<3> a_addr_dec_r<2> a_addr_dec_r<1> a_addr_dec_r<0> A_BIST_BM<23> A_BIST_DIN<23> A_BIST_EN a_blc_r<31> a_blc_r<30> a_blc_r<29> a_blc_r<28> a_blt_r<31> a_blt_r<30> a_blt_r<29> a_blt_r<28> A_BM<23> a_dclk_n_r<7> a_dclk_n_r<8> a_dclk_p_r<7> a_dclk_p_r<8> A_DOUT<23> A_DIN<23> a_rclk_n_r<7> a_rclk_n_r<8> a_rclk_p_r<7> a_rclk_p_r<8> a_tieh<23> a_wclk_n_r<7> a_wclk_n_r<8> a_wclk_p_r<7> a_wclk_p_r<8> VDD! VSS! / RM_IHPSG13_256x32_c2_1P_COLCTRL2 +XCOLCTRL<22> a_addr_dec_r<3> a_addr_dec_r<2> a_addr_dec_r<1> a_addr_dec_r<0> A_BIST_BM<22> A_BIST_DIN<22> A_BIST_EN a_blc_r<27> a_blc_r<26> a_blc_r<25> a_blc_r<24> a_blt_r<27> a_blt_r<26> a_blt_r<25> a_blt_r<24> A_BM<22> a_dclk_n_r<6> a_dclk_n_r<7> a_dclk_p_r<6> a_dclk_p_r<7> A_DOUT<22> A_DIN<22> a_rclk_n_r<6> a_rclk_n_r<7> a_rclk_p_r<6> a_rclk_p_r<7> a_tieh<22> a_wclk_n_r<6> a_wclk_n_r<7> a_wclk_p_r<6> a_wclk_p_r<7> VDD! VSS! / RM_IHPSG13_256x32_c2_1P_COLCTRL2 +XCOLCTRL<21> a_addr_dec_r<3> a_addr_dec_r<2> a_addr_dec_r<1> a_addr_dec_r<0> A_BIST_BM<21> A_BIST_DIN<21> A_BIST_EN a_blc_r<23> a_blc_r<22> a_blc_r<21> a_blc_r<20> a_blt_r<23> a_blt_r<22> a_blt_r<21> a_blt_r<20> A_BM<21> a_dclk_n_r<5> a_dclk_n_r<6> a_dclk_p_r<5> a_dclk_p_r<6> A_DOUT<21> A_DIN<21> a_rclk_n_r<5> a_rclk_n_r<6> a_rclk_p_r<5> a_rclk_p_r<6> a_tieh<21> a_wclk_n_r<5> a_wclk_n_r<6> a_wclk_p_r<5> a_wclk_p_r<6> VDD! VSS! / RM_IHPSG13_256x32_c2_1P_COLCTRL2 +XCOLCTRL<20> a_addr_dec_r<3> a_addr_dec_r<2> a_addr_dec_r<1> a_addr_dec_r<0> A_BIST_BM<20> A_BIST_DIN<20> A_BIST_EN a_blc_r<19> a_blc_r<18> a_blc_r<17> a_blc_r<16> a_blt_r<19> a_blt_r<18> a_blt_r<17> a_blt_r<16> A_BM<20> a_dclk_n_r<4> a_dclk_n_r<5> a_dclk_p_r<4> a_dclk_p_r<5> A_DOUT<20> A_DIN<20> a_rclk_n_r<4> a_rclk_n_r<5> a_rclk_p_r<4> a_rclk_p_r<5> a_tieh<20> a_wclk_n_r<4> a_wclk_n_r<5> a_wclk_p_r<4> a_wclk_p_r<5> VDD! VSS! / RM_IHPSG13_256x32_c2_1P_COLCTRL2 +XCOLCTRL<19> a_addr_dec_r<3> a_addr_dec_r<2> a_addr_dec_r<1> a_addr_dec_r<0> A_BIST_BM<19> A_BIST_DIN<19> A_BIST_EN a_blc_r<15> a_blc_r<14> a_blc_r<13> a_blc_r<12> a_blt_r<15> a_blt_r<14> a_blt_r<13> a_blt_r<12> A_BM<19> a_dclk_n_r<3> a_dclk_n_r<4> a_dclk_p_r<3> a_dclk_p_r<4> A_DOUT<19> A_DIN<19> a_rclk_n_r<3> a_rclk_n_r<4> a_rclk_p_r<3> a_rclk_p_r<4> a_tieh<19> a_wclk_n_r<3> a_wclk_n_r<4> a_wclk_p_r<3> a_wclk_p_r<4> VDD! VSS! / RM_IHPSG13_256x32_c2_1P_COLCTRL2 +XCOLCTRL<18> a_addr_dec_r<3> a_addr_dec_r<2> a_addr_dec_r<1> a_addr_dec_r<0> A_BIST_BM<18> A_BIST_DIN<18> A_BIST_EN a_blc_r<11> a_blc_r<10> a_blc_r<9> a_blc_r<8> a_blt_r<11> a_blt_r<10> a_blt_r<9> a_blt_r<8> A_BM<18> a_dclk_n_r<2> a_dclk_n_r<3> a_dclk_p_r<2> a_dclk_p_r<3> A_DOUT<18> A_DIN<18> a_rclk_n_r<2> a_rclk_n_r<3> a_rclk_p_r<2> a_rclk_p_r<3> a_tieh<18> a_wclk_n_r<2> a_wclk_n_r<3> a_wclk_p_r<2> a_wclk_p_r<3> VDD! VSS! / RM_IHPSG13_256x32_c2_1P_COLCTRL2 +XCOLCTRL<17> a_addr_dec_r<3> a_addr_dec_r<2> a_addr_dec_r<1> a_addr_dec_r<0> A_BIST_BM<17> A_BIST_DIN<17> A_BIST_EN a_blc_r<7> a_blc_r<6> a_blc_r<5> a_blc_r<4> a_blt_r<7> a_blt_r<6> a_blt_r<5> a_blt_r<4> A_BM<17> a_dclk_n_r<1> a_dclk_n_r<2> a_dclk_p_r<1> a_dclk_p_r<2> A_DOUT<17> A_DIN<17> a_rclk_n_r<1> a_rclk_n_r<2> a_rclk_p_r<1> a_rclk_p_r<2> a_tieh<17> a_wclk_n_r<1> a_wclk_n_r<2> a_wclk_p_r<1> a_wclk_p_r<2> VDD! VSS! / RM_IHPSG13_256x32_c2_1P_COLCTRL2 +XCOLCTRL<16> a_addr_dec_r<3> a_addr_dec_r<2> a_addr_dec_r<1> a_addr_dec_r<0> A_BIST_BM<16> A_BIST_DIN<16> A_BIST_EN a_blc_r<3> a_blc_r<2> a_blc_r<1> a_blc_r<0> a_blt_r<3> a_blt_r<2> a_blt_r<1> a_blt_r<0> A_BM<16> a_dclk_n_r<0> a_dclk_n_r<1> a_dclk_p_r<0> a_dclk_p_r<1> A_DOUT<16> A_DIN<16> a_rclk_n_r<0> a_rclk_n_r<1> a_rclk_p_r<0> a_rclk_p_r<1> a_tieh<16> a_wclk_n_r<0> a_wclk_n_r<1> a_wclk_p_r<0> a_wclk_p_r<1> VDD! VSS! / RM_IHPSG13_256x32_c2_1P_COLCTRL2 +XCOLCTRL<15> a_addr_dec_l<3> a_addr_dec_l<2> a_addr_dec_l<1> a_addr_dec_l<0> A_BIST_BM<0> A_BIST_DIN<0> A_BIST_EN a_blc_l<63> a_blc_l<62> a_blc_l<61> a_blc_l<60> a_blt_l<63> a_blt_l<62> a_blt_l<61> a_blt_l<60> A_BM<0> a_dclk_n_l<15> a_dclk_n_l<16> a_dclk_p_l<15> a_dclk_p_l<16> A_DOUT<0> A_DIN<0> a_rclk_n_l<15> a_rclk_n_l<16> a_rclk_p_l<15> a_rclk_p_l<16> a_tieh<0> a_wclk_n_l<15> a_wclk_n_l<16> a_wclk_p_l<15> a_wclk_p_l<16> VDD! VSS! / RM_IHPSG13_256x32_c2_1P_COLCTRL2 +XCOLCTRL<14> a_addr_dec_l<3> a_addr_dec_l<2> a_addr_dec_l<1> a_addr_dec_l<0> A_BIST_BM<1> A_BIST_DIN<1> A_BIST_EN a_blc_l<59> a_blc_l<58> a_blc_l<57> a_blc_l<56> a_blt_l<59> a_blt_l<58> a_blt_l<57> a_blt_l<56> A_BM<1> a_dclk_n_l<14> a_dclk_n_l<15> a_dclk_p_l<14> a_dclk_p_l<15> A_DOUT<1> A_DIN<1> a_rclk_n_l<14> a_rclk_n_l<15> a_rclk_p_l<14> a_rclk_p_l<15> a_tieh<1> a_wclk_n_l<14> a_wclk_n_l<15> a_wclk_p_l<14> a_wclk_p_l<15> VDD! VSS! / RM_IHPSG13_256x32_c2_1P_COLCTRL2 +XCOLCTRL<13> a_addr_dec_l<3> a_addr_dec_l<2> a_addr_dec_l<1> a_addr_dec_l<0> A_BIST_BM<2> A_BIST_DIN<2> A_BIST_EN a_blc_l<55> a_blc_l<54> a_blc_l<53> a_blc_l<52> a_blt_l<55> a_blt_l<54> a_blt_l<53> a_blt_l<52> A_BM<2> a_dclk_n_l<13> a_dclk_n_l<14> a_dclk_p_l<13> a_dclk_p_l<14> A_DOUT<2> A_DIN<2> a_rclk_n_l<13> a_rclk_n_l<14> a_rclk_p_l<13> a_rclk_p_l<14> a_tieh<2> a_wclk_n_l<13> a_wclk_n_l<14> a_wclk_p_l<13> a_wclk_p_l<14> VDD! VSS! / RM_IHPSG13_256x32_c2_1P_COLCTRL2 +XCOLCTRL<12> a_addr_dec_l<3> a_addr_dec_l<2> a_addr_dec_l<1> a_addr_dec_l<0> A_BIST_BM<3> A_BIST_DIN<3> A_BIST_EN a_blc_l<51> a_blc_l<50> a_blc_l<49> a_blc_l<48> a_blt_l<51> a_blt_l<50> a_blt_l<49> a_blt_l<48> A_BM<3> a_dclk_n_l<12> a_dclk_n_l<13> a_dclk_p_l<12> a_dclk_p_l<13> A_DOUT<3> A_DIN<3> a_rclk_n_l<12> a_rclk_n_l<13> a_rclk_p_l<12> a_rclk_p_l<13> a_tieh<3> a_wclk_n_l<12> a_wclk_n_l<13> a_wclk_p_l<12> a_wclk_p_l<13> VDD! VSS! / RM_IHPSG13_256x32_c2_1P_COLCTRL2 +XCOLCTRL<11> a_addr_dec_l<3> a_addr_dec_l<2> a_addr_dec_l<1> a_addr_dec_l<0> A_BIST_BM<4> A_BIST_DIN<4> A_BIST_EN a_blc_l<47> a_blc_l<46> a_blc_l<45> a_blc_l<44> a_blt_l<47> a_blt_l<46> a_blt_l<45> a_blt_l<44> A_BM<4> a_dclk_n_l<11> a_dclk_n_l<12> a_dclk_p_l<11> a_dclk_p_l<12> A_DOUT<4> A_DIN<4> a_rclk_n_l<11> a_rclk_n_l<12> a_rclk_p_l<11> a_rclk_p_l<12> a_tieh<4> a_wclk_n_l<11> a_wclk_n_l<12> a_wclk_p_l<11> a_wclk_p_l<12> VDD! VSS! / RM_IHPSG13_256x32_c2_1P_COLCTRL2 +XCOLCTRL<10> a_addr_dec_l<3> a_addr_dec_l<2> a_addr_dec_l<1> a_addr_dec_l<0> A_BIST_BM<5> A_BIST_DIN<5> A_BIST_EN a_blc_l<43> a_blc_l<42> a_blc_l<41> a_blc_l<40> a_blt_l<43> a_blt_l<42> a_blt_l<41> a_blt_l<40> A_BM<5> a_dclk_n_l<10> a_dclk_n_l<11> a_dclk_p_l<10> a_dclk_p_l<11> A_DOUT<5> A_DIN<5> a_rclk_n_l<10> a_rclk_n_l<11> a_rclk_p_l<10> a_rclk_p_l<11> a_tieh<5> a_wclk_n_l<10> a_wclk_n_l<11> a_wclk_p_l<10> a_wclk_p_l<11> VDD! VSS! / RM_IHPSG13_256x32_c2_1P_COLCTRL2 +XCOLCTRL<9> a_addr_dec_l<3> a_addr_dec_l<2> a_addr_dec_l<1> a_addr_dec_l<0> A_BIST_BM<6> A_BIST_DIN<6> A_BIST_EN a_blc_l<39> a_blc_l<38> a_blc_l<37> a_blc_l<36> a_blt_l<39> a_blt_l<38> a_blt_l<37> a_blt_l<36> A_BM<6> a_dclk_n_l<9> a_dclk_n_l<10> a_dclk_p_l<9> a_dclk_p_l<10> A_DOUT<6> A_DIN<6> a_rclk_n_l<9> a_rclk_n_l<10> a_rclk_p_l<9> a_rclk_p_l<10> a_tieh<6> a_wclk_n_l<9> a_wclk_n_l<10> a_wclk_p_l<9> a_wclk_p_l<10> VDD! VSS! / RM_IHPSG13_256x32_c2_1P_COLCTRL2 +XCOLCTRL<8> a_addr_dec_l<3> a_addr_dec_l<2> a_addr_dec_l<1> a_addr_dec_l<0> A_BIST_BM<7> A_BIST_DIN<7> A_BIST_EN a_blc_l<35> a_blc_l<34> a_blc_l<33> a_blc_l<32> a_blt_l<35> a_blt_l<34> a_blt_l<33> a_blt_l<32> A_BM<7> a_dclk_n_l<8> a_dclk_n_l<9> a_dclk_p_l<8> a_dclk_p_l<9> A_DOUT<7> A_DIN<7> a_rclk_n_l<8> a_rclk_n_l<9> a_rclk_p_l<8> a_rclk_p_l<9> a_tieh<7> a_wclk_n_l<8> a_wclk_n_l<9> a_wclk_p_l<8> a_wclk_p_l<9> VDD! VSS! / RM_IHPSG13_256x32_c2_1P_COLCTRL2 +XCOLCTRL<7> a_addr_dec_l<3> a_addr_dec_l<2> a_addr_dec_l<1> a_addr_dec_l<0> A_BIST_BM<8> A_BIST_DIN<8> A_BIST_EN a_blc_l<31> a_blc_l<30> a_blc_l<29> a_blc_l<28> a_blt_l<31> a_blt_l<30> a_blt_l<29> a_blt_l<28> A_BM<8> a_dclk_n_l<7> a_dclk_n_l<8> a_dclk_p_l<7> a_dclk_p_l<8> A_DOUT<8> A_DIN<8> a_rclk_n_l<7> a_rclk_n_l<8> a_rclk_p_l<7> a_rclk_p_l<8> a_tieh<8> a_wclk_n_l<7> a_wclk_n_l<8> a_wclk_p_l<7> a_wclk_p_l<8> VDD! VSS! / RM_IHPSG13_256x32_c2_1P_COLCTRL2 +XCOLCTRL<6> a_addr_dec_l<3> a_addr_dec_l<2> a_addr_dec_l<1> a_addr_dec_l<0> A_BIST_BM<9> A_BIST_DIN<9> A_BIST_EN a_blc_l<27> a_blc_l<26> a_blc_l<25> a_blc_l<24> a_blt_l<27> a_blt_l<26> a_blt_l<25> a_blt_l<24> A_BM<9> a_dclk_n_l<6> a_dclk_n_l<7> a_dclk_p_l<6> a_dclk_p_l<7> A_DOUT<9> A_DIN<9> a_rclk_n_l<6> a_rclk_n_l<7> a_rclk_p_l<6> a_rclk_p_l<7> a_tieh<9> a_wclk_n_l<6> a_wclk_n_l<7> a_wclk_p_l<6> a_wclk_p_l<7> VDD! VSS! / RM_IHPSG13_256x32_c2_1P_COLCTRL2 +XCOLCTRL<5> a_addr_dec_l<3> a_addr_dec_l<2> a_addr_dec_l<1> a_addr_dec_l<0> A_BIST_BM<10> A_BIST_DIN<10> A_BIST_EN a_blc_l<23> a_blc_l<22> a_blc_l<21> a_blc_l<20> a_blt_l<23> a_blt_l<22> a_blt_l<21> a_blt_l<20> A_BM<10> a_dclk_n_l<5> a_dclk_n_l<6> a_dclk_p_l<5> a_dclk_p_l<6> A_DOUT<10> A_DIN<10> a_rclk_n_l<5> a_rclk_n_l<6> a_rclk_p_l<5> a_rclk_p_l<6> a_tieh<10> a_wclk_n_l<5> a_wclk_n_l<6> a_wclk_p_l<5> a_wclk_p_l<6> VDD! VSS! / RM_IHPSG13_256x32_c2_1P_COLCTRL2 +XCOLCTRL<4> a_addr_dec_l<3> a_addr_dec_l<2> a_addr_dec_l<1> a_addr_dec_l<0> A_BIST_BM<11> A_BIST_DIN<11> A_BIST_EN a_blc_l<19> a_blc_l<18> a_blc_l<17> a_blc_l<16> a_blt_l<19> a_blt_l<18> a_blt_l<17> a_blt_l<16> A_BM<11> a_dclk_n_l<4> a_dclk_n_l<5> a_dclk_p_l<4> a_dclk_p_l<5> A_DOUT<11> A_DIN<11> a_rclk_n_l<4> a_rclk_n_l<5> a_rclk_p_l<4> a_rclk_p_l<5> a_tieh<11> a_wclk_n_l<4> a_wclk_n_l<5> a_wclk_p_l<4> a_wclk_p_l<5> VDD! VSS! / RM_IHPSG13_256x32_c2_1P_COLCTRL2 +XCOLCTRL<3> a_addr_dec_l<3> a_addr_dec_l<2> a_addr_dec_l<1> a_addr_dec_l<0> A_BIST_BM<12> A_BIST_DIN<12> A_BIST_EN a_blc_l<15> a_blc_l<14> a_blc_l<13> a_blc_l<12> a_blt_l<15> a_blt_l<14> a_blt_l<13> a_blt_l<12> A_BM<12> a_dclk_n_l<3> a_dclk_n_l<4> a_dclk_p_l<3> a_dclk_p_l<4> A_DOUT<12> A_DIN<12> a_rclk_n_l<3> a_rclk_n_l<4> a_rclk_p_l<3> a_rclk_p_l<4> a_tieh<12> a_wclk_n_l<3> a_wclk_n_l<4> a_wclk_p_l<3> a_wclk_p_l<4> VDD! VSS! / RM_IHPSG13_256x32_c2_1P_COLCTRL2 +XCOLCTRL<2> a_addr_dec_l<3> a_addr_dec_l<2> a_addr_dec_l<1> a_addr_dec_l<0> A_BIST_BM<13> A_BIST_DIN<13> A_BIST_EN a_blc_l<11> a_blc_l<10> a_blc_l<9> a_blc_l<8> a_blt_l<11> a_blt_l<10> a_blt_l<9> a_blt_l<8> A_BM<13> a_dclk_n_l<2> a_dclk_n_l<3> a_dclk_p_l<2> a_dclk_p_l<3> A_DOUT<13> A_DIN<13> a_rclk_n_l<2> a_rclk_n_l<3> a_rclk_p_l<2> a_rclk_p_l<3> a_tieh<13> a_wclk_n_l<2> a_wclk_n_l<3> a_wclk_p_l<2> a_wclk_p_l<3> VDD! VSS! / RM_IHPSG13_256x32_c2_1P_COLCTRL2 +XCOLCTRL<1> a_addr_dec_l<3> a_addr_dec_l<2> a_addr_dec_l<1> a_addr_dec_l<0> A_BIST_BM<14> A_BIST_DIN<14> A_BIST_EN a_blc_l<7> a_blc_l<6> a_blc_l<5> a_blc_l<4> a_blt_l<7> a_blt_l<6> a_blt_l<5> a_blt_l<4> A_BM<14> a_dclk_n_l<1> a_dclk_n_l<2> a_dclk_p_l<1> a_dclk_p_l<2> A_DOUT<14> A_DIN<14> a_rclk_n_l<1> a_rclk_n_l<2> a_rclk_p_l<1> a_rclk_p_l<2> a_tieh<14> a_wclk_n_l<1> a_wclk_n_l<2> a_wclk_p_l<1> a_wclk_p_l<2> VDD! VSS! / RM_IHPSG13_256x32_c2_1P_COLCTRL2 +XCOLCTRL<0> a_addr_dec_l<3> a_addr_dec_l<2> a_addr_dec_l<1> a_addr_dec_l<0> A_BIST_BM<15> A_BIST_DIN<15> A_BIST_EN a_blc_l<3> a_blc_l<2> a_blc_l<1> a_blc_l<0> a_blt_l<3> a_blt_l<2> a_blt_l<1> a_blt_l<0> A_BM<15> a_dclk_n_l<0> a_dclk_n_l<1> a_dclk_p_l<0> a_dclk_p_l<1> A_DOUT<15> A_DIN<15> a_rclk_n_l<0> a_rclk_n_l<1> a_rclk_p_l<0> a_rclk_p_l<1> a_tieh<15> a_wclk_n_l<0> a_wclk_n_l<1> a_wclk_p_l<0> a_wclk_p_l<1> VDD! VSS! / RM_IHPSG13_256x32_c2_1P_COLCTRL2 + + +XDRVFILL4<1> VDD! VSS! / RM_IHPSG13_256x32_c2_1P_COLDRV13_FILL4 +XDRVFILL4<2> VDD! VSS! / RM_IHPSG13_256x32_c2_1P_COLDRV13_FILL4 +XCOLFILL4<1> VDD! VSS! / RM_IHPSG13_256x32_c2_1P_COLDRV13_FILL4C2 +XCOLFILL4<2> VDD! VSS! / RM_IHPSG13_256x32_c2_1P_COLDRV13_FILL4C2 +XCOLFILL4<3> VDD! VSS! / RM_IHPSG13_256x32_c2_1P_COLDRV13_FILL4C2 +XCOLFILL4<4> VDD! VSS! / RM_IHPSG13_256x32_c2_1P_COLDRV13_FILL4C2 +XCOLFILL4<5> VDD! VSS! / RM_IHPSG13_256x32_c2_1P_COLDRV13_FILL4C2 +XCOLFILL4<6> VDD! VSS! / RM_IHPSG13_256x32_c2_1P_COLDRV13_FILL4C2 +.ENDS diff --git a/flow/platforms/ihp-sg13g2/cdl/RM_IHPSG13_1P_256x8_c3_bm_bist.cdl b/flow/platforms/ihp-sg13g2/cdl/RM_IHPSG13_1P_256x8_c3_bm_bist.cdl new file mode 100644 index 0000000000..ff357d9a04 --- /dev/null +++ b/flow/platforms/ihp-sg13g2/cdl/RM_IHPSG13_1P_256x8_c3_bm_bist.cdl @@ -0,0 +1,6307 @@ +* ------------------------------------------------------ +* +* Copyright 2025 IHP PDK Authors +* +* Licensed under the Apache License, Version 2.0 (the "License"); +* you may not use this file except in compliance with the License. +* You may obtain a copy of the License at +* +* https://www.apache.org/licenses/LICENSE-2.0 +* +* Unless required by applicable law or agreed to in writing, software +* distributed under the License is distributed on an "AS IS" BASIS, +* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +* See the License for the specific language governing permissions and +* limitations under the License. +* +* Generated on Wed Aug 27 16:22:45 2025 +* +* ------------------------------------------------------ + +.SUBCKT RM_IHPSG13_256x8_c3_1P_BITKIT_CORNER NW PW VDD VSS +.ENDS +.SUBCKT RM_IHPSG13_256x8_c3_1P_BITKIT_16x2_CORNER VDD_CORE VSS +XI16 VDD_CORE VSS VDD_CORE VSS / ++ RM_IHPSG13_256x8_c3_1P_BITKIT_CORNER +.ENDS +.SUBCKT RM_IHPSG13_256x8_c3_1P_BITKIT_EDGE_LR LWL NW PW VDD VSS +MN1 VSS LWL VSS VSS sg13_lv_nmos m=1 w=300.0n l=130.00n ng=1 nrd=0 nrs=0 +MN0 VSS net9 VSS VSS sg13_lv_nmos m=1 w=300.0n l=130.00n ng=1 nrd=0 nrs=0 +.ENDS +.SUBCKT RM_IHPSG13_256x8_c3_1P_BITKIT_16x2_EDGE_LR A_WL<15> A_WL<14> A_WL<13> A_WL<12> ++ A_WL<11> A_WL<10> A_WL<9> A_WL<8> A_WL<7> A_WL<6> A_WL<5> A_WL<4> A_WL<3> ++ A_WL<2> A_WL<1> A_WL<0> VDD_CORE VSS +XI0<15> A_WL<15> VDD_CORE VSS VDD_CORE VSS / ++ RM_IHPSG13_256x8_c3_1P_BITKIT_EDGE_LR +XI0<14> A_WL<14> VDD_CORE VSS VDD_CORE VSS / ++ RM_IHPSG13_256x8_c3_1P_BITKIT_EDGE_LR +XI0<13> A_WL<13> VDD_CORE VSS VDD_CORE VSS / ++ RM_IHPSG13_256x8_c3_1P_BITKIT_EDGE_LR +XI0<12> A_WL<12> VDD_CORE VSS VDD_CORE VSS / ++ RM_IHPSG13_256x8_c3_1P_BITKIT_EDGE_LR +XI0<11> A_WL<11> VDD_CORE VSS VDD_CORE VSS / ++ RM_IHPSG13_256x8_c3_1P_BITKIT_EDGE_LR +XI0<10> A_WL<10> VDD_CORE VSS VDD_CORE VSS / ++ RM_IHPSG13_256x8_c3_1P_BITKIT_EDGE_LR +XI0<9> A_WL<9> VDD_CORE VSS VDD_CORE VSS / ++ RM_IHPSG13_256x8_c3_1P_BITKIT_EDGE_LR +XI0<8> A_WL<8> VDD_CORE VSS VDD_CORE VSS / ++ RM_IHPSG13_256x8_c3_1P_BITKIT_EDGE_LR +XI0<7> A_WL<7> VDD_CORE VSS VDD_CORE VSS / ++ RM_IHPSG13_256x8_c3_1P_BITKIT_EDGE_LR +XI0<6> A_WL<6> VDD_CORE VSS VDD_CORE VSS / ++ RM_IHPSG13_256x8_c3_1P_BITKIT_EDGE_LR +XI0<5> A_WL<5> VDD_CORE VSS VDD_CORE VSS / ++ RM_IHPSG13_256x8_c3_1P_BITKIT_EDGE_LR +XI0<4> A_WL<4> VDD_CORE VSS VDD_CORE VSS / ++ RM_IHPSG13_256x8_c3_1P_BITKIT_EDGE_LR +XI0<3> A_WL<3> VDD_CORE VSS VDD_CORE VSS / ++ RM_IHPSG13_256x8_c3_1P_BITKIT_EDGE_LR +XI0<2> A_WL<2> VDD_CORE VSS VDD_CORE VSS / ++ RM_IHPSG13_256x8_c3_1P_BITKIT_EDGE_LR +XI0<1> A_WL<1> VDD_CORE VSS VDD_CORE VSS / ++ RM_IHPSG13_256x8_c3_1P_BITKIT_EDGE_LR +XI0<0> A_WL<0> VDD_CORE VSS VDD_CORE VSS / ++ RM_IHPSG13_256x8_c3_1P_BITKIT_EDGE_LR +.ENDS +.SUBCKT RM_IHPSG13_256x8_c3_1P_BITKIT_CELL BLC_BOT BLC_TOP BLT_BOT BLT_TOP LWL NW PW ++ RWL VDD VSS +MN0 NC NT VSS PW sg13_lv_nmos m=1 w=300.0n l=130.00n ng=1 nrd=0 nrs=0 +MN1 NT NC VSS PW sg13_lv_nmos m=1 w=300.0n l=130.00n ng=1 nrd=0 nrs=0 +MN3 NC RWL BLC_TOP PW sg13_lv_nmos m=1 w=300.0n l=130.00n ng=1 nrd=0 nrs=0 +MN2 BLT_BOT LWL NT PW sg13_lv_nmos m=1 w=300.0n l=130.00n ng=1 nrd=0 nrs=0 +MP1 NT NC VDD NW sg13_lv_pmos m=1 w=150.00n l=130.00n ng=1 nrd=0 nrs=0 +MP0 NC NT VDD NW sg13_lv_pmos m=1 w=150.00n l=130.00n ng=1 nrd=0 nrs=0 +R1 BLC_BOT BLC_TOP lvsres w=2.6e-07 l=6e-07 +R0 BLT_BOT BLT_TOP lvsres w=2.6e-07 l=6e-07 +R2 RWL LWL lvsres w=2.6e-07 l=6e-07 +.ENDS +.SUBCKT RM_IHPSG13_256x8_c3_1P_BITKIT_16x2_SRAM A_BLC_BOT<1> A_BLC_BOT<0> A_BLC_TOP<1> ++ A_BLC_TOP<0> A_BLT_BOT<1> A_BLT_BOT<0> A_BLT_TOP<1> A_BLT_TOP<0> A_LWL<15> ++ A_LWL<14> A_LWL<13> A_LWL<12> A_LWL<11> A_LWL<10> A_LWL<9> A_LWL<8> A_LWL<7> ++ A_LWL<6> A_LWL<5> A_LWL<4> A_LWL<3> A_LWL<2> A_LWL<1> A_LWL<0> A_RWL<15> ++ A_RWL<14> A_RWL<13> A_RWL<12> A_RWL<11> A_RWL<10> A_RWL<9> A_RWL<8> A_RWL<7> ++ A_RWL<6> A_RWL<5> A_RWL<4> A_RWL<3> A_RWL<2> A_RWL<1> A_RWL<0> VDD_CORE ++ VSS +XCELL<31> A_BLC_TOP<1> A_RBLC<15> A_BLT_TOP<1> A_RBLT<15> A_RWL<15> ++ VDD_CORE VSS A_XWL<15> VDD_CORE VSS / ++ RM_IHPSG13_256x8_c3_1P_BITKIT_CELL +XCELL<30> A_RBLC<14> A_RBLC<15> A_RBLT<14> A_RBLT<15> A_RWL<14> VDD_CORE ++ VSS A_XWL<14> VDD_CORE VSS / RM_IHPSG13_256x8_c3_1P_BITKIT_CELL +XCELL<29> A_RBLC<14> A_RBLC<13> A_RBLT<14> A_RBLT<13> A_RWL<13> VDD_CORE ++ VSS A_XWL<13> VDD_CORE VSS / RM_IHPSG13_256x8_c3_1P_BITKIT_CELL +XCELL<28> A_RBLC<12> A_RBLC<13> A_RBLT<12> A_RBLT<13> A_RWL<12> VDD_CORE ++ VSS A_XWL<12> VDD_CORE VSS / RM_IHPSG13_256x8_c3_1P_BITKIT_CELL +XCELL<27> A_RBLC<12> A_RBLC<11> A_RBLT<12> A_RBLT<11> A_RWL<11> VDD_CORE ++ VSS A_XWL<11> VDD_CORE VSS / RM_IHPSG13_256x8_c3_1P_BITKIT_CELL +XCELL<26> A_RBLC<10> A_RBLC<11> A_RBLT<10> A_RBLT<11> A_RWL<10> VDD_CORE ++ VSS A_XWL<10> VDD_CORE VSS / RM_IHPSG13_256x8_c3_1P_BITKIT_CELL +XCELL<25> A_RBLC<10> A_RBLC<9> A_RBLT<10> A_RBLT<9> A_RWL<9> VDD_CORE ++ VSS A_XWL<9> VDD_CORE VSS / RM_IHPSG13_256x8_c3_1P_BITKIT_CELL +XCELL<24> A_RBLC<8> A_RBLC<9> A_RBLT<8> A_RBLT<9> A_RWL<8> VDD_CORE ++ VSS A_XWL<8> VDD_CORE VSS / RM_IHPSG13_256x8_c3_1P_BITKIT_CELL +XCELL<23> A_RBLC<8> A_RBLC<7> A_RBLT<8> A_RBLT<7> A_RWL<7> VDD_CORE ++ VSS A_XWL<7> VDD_CORE VSS / RM_IHPSG13_256x8_c3_1P_BITKIT_CELL +XCELL<22> A_RBLC<6> A_RBLC<7> A_RBLT<6> A_RBLT<7> A_RWL<6> VDD_CORE ++ VSS A_XWL<6> VDD_CORE VSS / RM_IHPSG13_256x8_c3_1P_BITKIT_CELL +XCELL<21> A_RBLC<6> A_RBLC<5> A_RBLT<6> A_RBLT<5> A_RWL<5> VDD_CORE ++ VSS A_XWL<5> VDD_CORE VSS / RM_IHPSG13_256x8_c3_1P_BITKIT_CELL +XCELL<20> A_RBLC<4> A_RBLC<5> A_RBLT<4> A_RBLT<5> A_RWL<4> VDD_CORE ++ VSS A_XWL<4> VDD_CORE VSS / RM_IHPSG13_256x8_c3_1P_BITKIT_CELL +XCELL<19> A_RBLC<4> A_RBLC<3> A_RBLT<4> A_RBLT<3> A_RWL<3> VDD_CORE ++ VSS A_XWL<3> VDD_CORE VSS / RM_IHPSG13_256x8_c3_1P_BITKIT_CELL +XCELL<18> A_RBLC<2> A_RBLC<3> A_RBLT<2> A_RBLT<3> A_RWL<2> VDD_CORE ++ VSS A_XWL<2> VDD_CORE VSS / RM_IHPSG13_256x8_c3_1P_BITKIT_CELL +XCELL<17> A_RBLC<2> A_RBLC<1> A_RBLT<2> A_RBLT<1> A_RWL<1> VDD_CORE ++ VSS A_XWL<1> VDD_CORE VSS / RM_IHPSG13_256x8_c3_1P_BITKIT_CELL +XCELL<16> A_BLC_BOT<1> A_RBLC<1> A_BLT_BOT<1> A_RBLT<1> A_RWL<0> VDD_CORE ++ VSS A_XWL<0> VDD_CORE VSS / RM_IHPSG13_256x8_c3_1P_BITKIT_CELL +XCELL<15> A_BLC_TOP<0> A_LBLC<15> A_BLT_TOP<0> A_LBLT<15> A_LWL<15> ++ VDD_CORE VSS A_XWL<15> VDD_CORE VSS / ++ RM_IHPSG13_256x8_c3_1P_BITKIT_CELL +XCELL<14> A_LBLC<14> A_LBLC<15> A_LBLT<14> A_LBLT<15> A_LWL<14> VDD_CORE ++ VSS A_XWL<14> VDD_CORE VSS / RM_IHPSG13_256x8_c3_1P_BITKIT_CELL +XCELL<13> A_LBLC<14> A_LBLC<13> A_LBLT<14> A_LBLT<13> A_LWL<13> VDD_CORE ++ VSS A_XWL<13> VDD_CORE VSS / RM_IHPSG13_256x8_c3_1P_BITKIT_CELL +XCELL<12> A_LBLC<12> A_LBLC<13> A_LBLT<12> A_LBLT<13> A_LWL<12> VDD_CORE ++ VSS A_XWL<12> VDD_CORE VSS / RM_IHPSG13_256x8_c3_1P_BITKIT_CELL +XCELL<11> A_LBLC<12> A_LBLC<11> A_LBLT<12> A_LBLT<11> A_LWL<11> VDD_CORE ++ VSS A_XWL<11> VDD_CORE VSS / RM_IHPSG13_256x8_c3_1P_BITKIT_CELL +XCELL<10> A_LBLC<10> A_LBLC<11> A_LBLT<10> A_LBLT<11> A_LWL<10> VDD_CORE ++ VSS A_XWL<10> VDD_CORE VSS / RM_IHPSG13_256x8_c3_1P_BITKIT_CELL +XCELL<9> A_LBLC<10> A_LBLC<9> A_LBLT<10> A_LBLT<9> A_LWL<9> VDD_CORE ++ VSS A_XWL<9> VDD_CORE VSS / RM_IHPSG13_256x8_c3_1P_BITKIT_CELL +XCELL<8> A_LBLC<8> A_LBLC<9> A_LBLT<8> A_LBLT<9> A_LWL<8> VDD_CORE ++ VSS A_XWL<8> VDD_CORE VSS / RM_IHPSG13_256x8_c3_1P_BITKIT_CELL +XCELL<7> A_LBLC<8> A_LBLC<7> A_LBLT<8> A_LBLT<7> A_LWL<7> VDD_CORE ++ VSS A_XWL<7> VDD_CORE VSS / RM_IHPSG13_256x8_c3_1P_BITKIT_CELL +XCELL<6> A_LBLC<6> A_LBLC<7> A_LBLT<6> A_LBLT<7> A_LWL<6> VDD_CORE ++ VSS A_XWL<6> VDD_CORE VSS / RM_IHPSG13_256x8_c3_1P_BITKIT_CELL +XCELL<5> A_LBLC<6> A_LBLC<5> A_LBLT<6> A_LBLT<5> A_LWL<5> VDD_CORE ++ VSS A_XWL<5> VDD_CORE VSS / RM_IHPSG13_256x8_c3_1P_BITKIT_CELL +XCELL<4> A_LBLC<4> A_LBLC<5> A_LBLT<4> A_LBLT<5> A_LWL<4> VDD_CORE ++ VSS A_XWL<4> VDD_CORE VSS / RM_IHPSG13_256x8_c3_1P_BITKIT_CELL +XCELL<3> A_LBLC<4> A_LBLC<3> A_LBLT<4> A_LBLT<3> A_LWL<3> VDD_CORE ++ VSS A_XWL<3> VDD_CORE VSS / RM_IHPSG13_256x8_c3_1P_BITKIT_CELL +XCELL<2> A_LBLC<2> A_LBLC<3> A_LBLT<2> A_LBLT<3> A_LWL<2> VDD_CORE ++ VSS A_XWL<2> VDD_CORE VSS / RM_IHPSG13_256x8_c3_1P_BITKIT_CELL +XCELL<1> A_LBLC<2> A_LBLC<1> A_LBLT<2> A_LBLT<1> A_LWL<1> VDD_CORE ++ VSS A_XWL<1> VDD_CORE VSS / RM_IHPSG13_256x8_c3_1P_BITKIT_CELL +XCELL<0> A_BLC_BOT<0> A_LBLC<1> A_BLT_BOT<0> A_LBLT<1> A_LWL<0> VDD_CORE ++ VSS A_XWL<0> VDD_CORE VSS / RM_IHPSG13_256x8_c3_1P_BITKIT_CELL +.ENDS +.SUBCKT RM_IHPSG13_256x8_c3_1P_BITKIT_EDGE_TB BLC BLT NW PW VDD VSS +.ENDS +.SUBCKT RM_IHPSG13_256x8_c3_1P_BITKIT_16x2_EDGE_TB A_BLC<1> A_BLC<0> A_BLT<1> A_BLT<0> ++ VDD_CORE VSS +XEDGE<1> A_BLC<1> A_BLT<1> VDD_CORE VSS VDD_CORE VSS ++ / RM_IHPSG13_256x8_c3_1P_BITKIT_EDGE_TB +XEDGE<0> A_BLC<0> A_BLT<0> VDD_CORE VSS VDD_CORE VSS ++ / RM_IHPSG13_256x8_c3_1P_BITKIT_EDGE_TB +.ENDS + +.SUBCKT RSC_IHPSG13_CBUFX4 A Z VDD VSS +MN0 net9 A VSS VSS sg13_lv_nmos m=1 w=705.000n l=130.00n ng=1 nrd=0 ++ nrs=0 +MN1 Z net9 VSS VSS sg13_lv_nmos m=1 w=1.41u l=130.00n ng=2 nrd=0 nrs=0 +MP0 net9 A VDD VDD sg13_lv_pmos m=1 w=1.62u l=130.00n ng=1 nrd=0 nrs=0 +MP1 Z net9 VDD VDD sg13_lv_pmos m=1 w=3.24u l=130.00n ng=2 nrd=0 nrs=0 +.ENDS +.SUBCKT RM_IHPSG13_256x8_c3_1P_COLDRV13X4 ADDR_COL_I<1> ADDR_COL_I<0> ADDR_COL_O<1> ++ ADDR_COL_O<0> ADDR_DEC_I<7> ADDR_DEC_I<6> ADDR_DEC_I<5> ADDR_DEC_I<4> ++ ADDR_DEC_I<3> ADDR_DEC_I<2> ADDR_DEC_I<1> ADDR_DEC_I<0> ADDR_DEC_O<7> ++ ADDR_DEC_O<6> ADDR_DEC_O<5> ADDR_DEC_O<4> ADDR_DEC_O<3> ADDR_DEC_O<2> ++ ADDR_DEC_O<1> ADDR_DEC_O<0> DCLK_I DCLK_O RCLK_I RCLK_O WCLK_I WCLK_O ++ VDD VSS +XADDR_COL_DRV<1> ADDR_COL_I<1> ADDR_COL_O<1> VDD VSS / ++ RSC_IHPSG13_CBUFX4 +XADDR_COL_DRV<0> ADDR_COL_I<0> ADDR_COL_O<0> VDD VSS / ++ RSC_IHPSG13_CBUFX4 +XADDR_DEC_DRV<7> ADDR_DEC_I<7> ADDR_DEC_O<7> VDD VSS / ++ RSC_IHPSG13_CBUFX4 +XADDR_DEC_DRV<6> ADDR_DEC_I<6> ADDR_DEC_O<6> VDD VSS / ++ RSC_IHPSG13_CBUFX4 +XADDR_DEC_DRV<5> ADDR_DEC_I<5> ADDR_DEC_O<5> VDD VSS / ++ RSC_IHPSG13_CBUFX4 +XADDR_DEC_DRV<4> ADDR_DEC_I<4> ADDR_DEC_O<4> VDD VSS / ++ RSC_IHPSG13_CBUFX4 +XADDR_DEC_DRV<3> ADDR_DEC_I<3> ADDR_DEC_O<3> VDD VSS / ++ RSC_IHPSG13_CBUFX4 +XADDR_DEC_DRV<2> ADDR_DEC_I<2> ADDR_DEC_O<2> VDD VSS / ++ RSC_IHPSG13_CBUFX4 +XADDR_DEC_DRV<1> ADDR_DEC_I<1> ADDR_DEC_O<1> VDD VSS / ++ RSC_IHPSG13_CBUFX4 +XADDR_DEC_DRV<0> ADDR_DEC_I<0> ADDR_DEC_O<0> VDD VSS / ++ RSC_IHPSG13_CBUFX4 +XDCLK_DRV DCLK_I DCLK_O VDD VSS / RSC_IHPSG13_CBUFX4 +XRCLK_DRV RCLK_I RCLK_O VDD VSS / RSC_IHPSG13_CBUFX4 +XWCLK_DRV WCLK_I WCLK_O VDD VSS / RSC_IHPSG13_CBUFX4 +.ENDS +.SUBCKT RSC_IHPSG13_WLDRVX4 A Z VDD VSS +MN1 Z net6 VSS VSS sg13_lv_nmos m=1 w=705.000n l=130.00n ng=1 nrd=0 ++ nrs=0 +MN0 net6 A VSS VSS sg13_lv_nmos m=1 w=900.0n l=130.00n ng=1 nrd=0 nrs=0 +MP1 Z net6 VDD VDD sg13_lv_pmos m=1 w=3.24u l=130.00n ng=2 nrd=0 nrs=0 +MP0 net6 A VDD VDD sg13_lv_pmos m=1 w=900.0n l=130.00n ng=1 nrd=0 nrs=0 +.ENDS +.SUBCKT RM_IHPSG13_256x8_c3_1P_WLDRV16X4 A<15> A<14> A<13> A<12> A<11> A<10> A<9> A<8> ++ A<7> A<6> A<5> A<4> A<3> A<2> A<1> A<0> Z<15> Z<14> Z<13> Z<12> Z<11> Z<10> ++ Z<9> Z<8> Z<7> Z<6> Z<5> Z<4> Z<3> Z<2> Z<1> Z<0> VDD VSS +XBUF<15> A<15> Z<15> VDD VSS / RSC_IHPSG13_WLDRVX4 +XBUF<14> A<14> Z<14> VDD VSS / RSC_IHPSG13_WLDRVX4 +XBUF<13> A<13> Z<13> VDD VSS / RSC_IHPSG13_WLDRVX4 +XBUF<12> A<12> Z<12> VDD VSS / RSC_IHPSG13_WLDRVX4 +XBUF<11> A<11> Z<11> VDD VSS / RSC_IHPSG13_WLDRVX4 +XBUF<10> A<10> Z<10> VDD VSS / RSC_IHPSG13_WLDRVX4 +XBUF<9> A<9> Z<9> VDD VSS / RSC_IHPSG13_WLDRVX4 +XBUF<8> A<8> Z<8> VDD VSS / RSC_IHPSG13_WLDRVX4 +XBUF<7> A<7> Z<7> VDD VSS / RSC_IHPSG13_WLDRVX4 +XBUF<6> A<6> Z<6> VDD VSS / RSC_IHPSG13_WLDRVX4 +XBUF<5> A<5> Z<5> VDD VSS / RSC_IHPSG13_WLDRVX4 +XBUF<4> A<4> Z<4> VDD VSS / RSC_IHPSG13_WLDRVX4 +XBUF<3> A<3> Z<3> VDD VSS / RSC_IHPSG13_WLDRVX4 +XBUF<2> A<2> Z<2> VDD VSS / RSC_IHPSG13_WLDRVX4 +XBUF<1> A<1> Z<1> VDD VSS / RSC_IHPSG13_WLDRVX4 +XBUF<0> A<0> Z<0> VDD VSS / RSC_IHPSG13_WLDRVX4 +.ENDS +.SUBCKT RSC_IHPSG13_FILLCAP8 VDD VSS +MN0 vss_r vdd_r VSS VSS sg13_lv_nmos m=1 w=4.98u l=130.00n ng=6 nrd=0 ++ nrs=0 +MP0 vdd_r vss_r VDD VDD sg13_lv_pmos m=1 w=6.48u l=385.000n ng=4 nrd=0 ++ nrs=0 +.ENDS +.SUBCKT RSC_IHPSG13_LHPQX2 CP D Q VDD VSS +MN3 QIN CPN net14 VSS sg13_lv_nmos m=1 w=480.00n l=130.00n ng=1 nrd=0 nrs=0 +MN2 net14 net10 VSS VSS sg13_lv_nmos m=1 w=480.00n l=130.00n ng=1 ++ nrd=0 nrs=0 +MN5 net21 D VSS VSS sg13_lv_nmos m=1 w=870.00n l=130.00n ng=1 nrd=0 ++ nrs=0 +MN6 QIN CP net21 VSS sg13_lv_nmos m=1 w=870.00n l=130.00n ng=1 nrd=0 nrs=0 +MN1 net10 QIN VSS VSS sg13_lv_nmos m=1 w=480.00n l=130.00n ng=1 nrd=0 ++ nrs=0 +MN0 CPN CP VSS VSS sg13_lv_nmos m=1 w=480.00n l=130.00n ng=1 nrd=0 ++ nrs=0 +MN4 Q QIN VSS VSS sg13_lv_nmos m=1 w=980.00n l=130.00n ng=1 nrd=0 nrs=0 +MP2 QIN CP net16 VDD sg13_lv_pmos m=1 w=480.00n l=130.00n ng=1 nrd=0 nrs=0 +MP0 CPN CP VDD VDD sg13_lv_pmos m=1 w=480.00n l=130.00n ng=1 nrd=0 ++ nrs=0 +MP4 Q QIN VDD VDD sg13_lv_pmos m=1 w=1.62u l=130.00n ng=1 nrd=0 nrs=0 +MP3 net10 QIN VDD VDD sg13_lv_pmos m=1 w=480.00n l=130.00n ng=1 nrd=0 ++ nrs=0 +MP1 net16 net10 VDD VDD sg13_lv_pmos m=1 w=480.00n l=130.00n ng=1 ++ nrd=0 nrs=0 +MP6 QIN CPN net20 VDD sg13_lv_pmos m=1 w=975.000n l=130.00n ng=1 nrd=0 ++ nrs=0 +MP5 net20 D VDD VDD sg13_lv_pmos m=1 w=975.000n l=130.00n ng=1 nrd=0 ++ nrs=0 +.ENDS +.SUBCKT RSC_IHPSG13_NAND2X2 A B Z VDD VSS +MP1 Z B VDD VDD sg13_lv_pmos m=1 w=1.62u l=130.00n ng=1 nrd=0 nrs=0 +MP0 Z A VDD VDD sg13_lv_pmos m=1 w=1.62u l=130.00n ng=1 nrd=0 nrs=0 +MN0 Z B net7 VSS sg13_lv_nmos m=1 w=980.00n l=130.00n ng=1 nrd=0 nrs=0 +MN1 net7 A VSS VSS sg13_lv_nmos m=1 w=980.00n l=130.00n ng=1 nrd=0 ++ nrs=0 +.ENDS +.SUBCKT RSC_IHPSG13_CINVX4 A Z VDD VSS +MN0 Z A VSS VSS sg13_lv_nmos m=1 w=1.41u l=130.00n ng=2 nrd=0 nrs=0 +MP0 Z A VDD VDD sg13_lv_pmos m=1 w=3.24u l=130.00n ng=2 nrd=0 nrs=0 +.ENDS +.SUBCKT RSC_IHPSG13_CINVX2 A Z VDD VSS +MN0 Z A VSS VSS sg13_lv_nmos m=1 w=705.000n l=130.00n ng=1 nrd=0 nrs=0 +MP0 Z A VDD VDD sg13_lv_pmos m=1 w=1.62u l=130.00n ng=1 nrd=0 nrs=0 +.ENDS +.SUBCKT RSC_IHPSG13_INVX2 A Z VDD VSS +MN0 Z A VSS VSS sg13_lv_nmos m=1 w=980.00n l=130.00n ng=1 nrd=0 nrs=0 +MP0 Z A VDD VDD sg13_lv_pmos m=1 w=1.62u l=130.00n ng=1 nrd=0 nrs=0 +.ENDS +.SUBCKT RSC_IHPSG13_NAND3X2 A B C Z VDD VSS +MP2 Z A VDD VDD sg13_lv_pmos m=1 w=1.62u l=130.00n ng=1 nrd=0 nrs=0 +MP1 Z B VDD VDD sg13_lv_pmos m=1 w=1.62u l=130.00n ng=1 nrd=0 nrs=0 +MP0 Z C VDD VDD sg13_lv_pmos m=1 w=1.62u l=130.00n ng=1 nrd=0 nrs=0 +MN1 net12 B net16 VSS sg13_lv_nmos m=1 w=980.00n l=130.00n ng=1 nrd=0 nrs=0 +MN0 Z C net12 VSS sg13_lv_nmos m=1 w=980.00n l=130.00n ng=1 nrd=0 nrs=0 +MN2 net16 A VSS VSS sg13_lv_nmos m=1 w=980.00n l=130.00n ng=1 nrd=0 ++ nrs=0 +.ENDS +.SUBCKT RSC_IHPSG13_NOR3X2 A B C Z VDD VSS +MP0 net13 A VDD VDD sg13_lv_pmos m=1 w=1.62u l=130.00n ng=1 nrd=0 nrs=0 +MP2 Z C net10 VDD sg13_lv_pmos m=1 w=1.62u l=130.00n ng=1 nrd=0 nrs=0 +MP1 net10 B net13 VDD sg13_lv_pmos m=1 w=1.62u l=130.00n ng=1 nrd=0 nrs=0 +MN1 Z B VSS VSS sg13_lv_nmos m=1 w=875.000n l=130.00n ng=1 nrd=0 nrs=0 +MN0 Z C VSS VSS sg13_lv_nmos m=1 w=875.000n l=130.00n ng=1 nrd=0 nrs=0 +MN2 Z A VSS VSS sg13_lv_nmos m=1 w=875.000n l=130.00n ng=1 nrd=0 nrs=0 +.ENDS +.SUBCKT RSC_IHPSG13_FILLCAP4 VDD VSS +MN0 vss_r vdd_r VSS VSS sg13_lv_nmos m=1 w=2.49u l=130.00n ng=3 nrd=0 ++ nrs=0 +MP0 vdd_r vss_r VDD VDD sg13_lv_pmos m=1 w=3.24u l=385.000n ng=2 nrd=0 ++ nrs=0 +.ENDS +.SUBCKT RSC_IHPSG13_MET2RES A B +R0 B A lvsres w=2.6e-07 l=6e-07 +.ENDS +.SUBCKT RM_IHPSG13_256x8_c3_1P_DEC04 ADDR<3> ADDR<2> ADDR<1> ADDR<0> CS ECLK_H_BOT ++ ECLK_H_TOP ECLK_L_BOT ECLK_L_TOP WL<15> WL<14> WL<13> WL<12> WL<11> WL<10> ++ WL<9> WL<8> WL<7> WL<6> WL<5> WL<4> WL<3> WL<2> WL<1> WL<0> VDD VSS +XLATCH<3> CS ADDR<3> PADR<3> VDD VSS / RSC_IHPSG13_LHPQX2 +XLATCH<2> CS ADDR<2> PADR<2> VDD VSS / RSC_IHPSG13_LHPQX2 +XLATCH<1> CS ADDR<1> PADR<1> VDD VSS / RSC_IHPSG13_LHPQX2 +XLATCH<0> CS ADDR<0> PADR<0> VDD VSS / RSC_IHPSG13_LHPQX2 +XI0<3> PADR<1> PADR<0> sel01<3> VDD VSS / RSC_IHPSG13_NAND2X2 +XI0<2> PADR<1> NADR<0> sel01<2> VDD VSS / RSC_IHPSG13_NAND2X2 +XI0<1> NADR<1> PADR<0> sel01<1> VDD VSS / RSC_IHPSG13_NAND2X2 +XI0<0> NADR<1> NADR<0> sel01<0> VDD VSS / RSC_IHPSG13_NAND2X2 +XI4 ECLK_L_BOT EN VDD VSS / RSC_IHPSG13_CINVX4 +XI5 ECLK_H_BOT ECLK_L_BOT VDD VSS / RSC_IHPSG13_CINVX2 +XI3<3> PADR<3> NADR<3> VDD VSS / RSC_IHPSG13_INVX2 +XI3<2> PADR<2> NADR<2> VDD VSS / RSC_IHPSG13_INVX2 +XI3<1> PADR<1> NADR<1> VDD VSS / RSC_IHPSG13_INVX2 +XI3<0> PADR<0> NADR<0> VDD VSS / RSC_IHPSG13_INVX2 +XI1<3> PADR<2> PADR<3> CS sel23<3> VDD VSS / RSC_IHPSG13_NAND3X2 +XI1<2> NADR<2> PADR<3> CS sel23<2> VDD VSS / RSC_IHPSG13_NAND3X2 +XI1<1> PADR<2> NADR<3> CS sel23<1> VDD VSS / RSC_IHPSG13_NAND3X2 +XI1<0> NADR<2> NADR<3> CS sel23<0> VDD VSS / RSC_IHPSG13_NAND3X2 +XI2<15> sel23<3> sel01<3> EN WL<15> VDD VSS / RSC_IHPSG13_NOR3X2 +XI2<14> sel23<3> sel01<2> EN WL<14> VDD VSS / RSC_IHPSG13_NOR3X2 +XI2<13> sel23<3> sel01<1> EN WL<13> VDD VSS / RSC_IHPSG13_NOR3X2 +XI2<12> sel23<3> sel01<0> EN WL<12> VDD VSS / RSC_IHPSG13_NOR3X2 +XI2<11> sel23<2> sel01<3> EN WL<11> VDD VSS / RSC_IHPSG13_NOR3X2 +XI2<10> sel23<2> sel01<2> EN WL<10> VDD VSS / RSC_IHPSG13_NOR3X2 +XI2<9> sel23<2> sel01<1> EN WL<9> VDD VSS / RSC_IHPSG13_NOR3X2 +XI2<8> sel23<2> sel01<0> EN WL<8> VDD VSS / RSC_IHPSG13_NOR3X2 +XI2<7> sel23<1> sel01<3> EN WL<7> VDD VSS / RSC_IHPSG13_NOR3X2 +XI2<6> sel23<1> sel01<2> EN WL<6> VDD VSS / RSC_IHPSG13_NOR3X2 +XI2<5> sel23<1> sel01<1> EN WL<5> VDD VSS / RSC_IHPSG13_NOR3X2 +XI2<4> sel23<1> sel01<0> EN WL<4> VDD VSS / RSC_IHPSG13_NOR3X2 +XI2<3> sel23<0> sel01<3> EN WL<3> VDD VSS / RSC_IHPSG13_NOR3X2 +XI2<2> sel23<0> sel01<2> EN WL<2> VDD VSS / RSC_IHPSG13_NOR3X2 +XI2<1> sel23<0> sel01<1> EN WL<1> VDD VSS / RSC_IHPSG13_NOR3X2 +XI2<0> sel23<0> sel01<0> EN WL<0> VDD VSS / RSC_IHPSG13_NOR3X2 +XCAPS4 VDD VSS / RSC_IHPSG13_FILLCAP4 +XI11 ECLK_L_BOT ECLK_L_TOP / RSC_IHPSG13_MET2RES +XR0 ECLK_H_BOT ECLK_H_TOP / RSC_IHPSG13_MET2RES +.ENDS +.SUBCKT RM_IHPSG13_256x8_c3_1P_ROWDEC4 ADDR_N_I<3> ADDR_N_I<2> ADDR_N_I<1> ADDR_N_I<0> ++ CS_I ECLK_I WL_O<15> WL_O<14> WL_O<13> WL_O<12> WL_O<11> WL_O<10> WL_O<9> ++ WL_O<8> WL_O<7> WL_O<6> WL_O<5> WL_O<4> WL_O<3> WL_O<2> WL_O<1> WL_O<0> ++ VDD VSS +XL2<8> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<7> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<6> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<5> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<4> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<3> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<2> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<1> VDD VSS / RSC_IHPSG13_FILLCAP8 +XSEL ADDR_N_I<3> ADDR_N_I<2> ADDR_N_I<1> ADDR_N_I<0> CS_I ECLK_I ECLK_H<1> ++ ECLK_B<0> ECLK_B<1> WL_O<15> WL_O<14> WL_O<13> WL_O<12> WL_O<11> WL_O<10> ++ WL_O<9> WL_O<8> WL_O<7> WL_O<6> WL_O<5> WL_O<4> WL_O<3> WL_O<2> WL_O<1> ++ WL_O<0> VDD VSS / RM_IHPSG13_256x8_c3_1P_DEC04 +.ENDS +.SUBCKT RSC_IHPSG13_CINVX8 A Z VDD VSS +MN0 Z A VSS VSS sg13_lv_nmos m=1 w=2.82u l=130.00n ng=4 nrd=0 nrs=0 +MP0 Z A VDD VDD sg13_lv_pmos m=1 w=6.48u l=130.00n ng=4 nrd=0 nrs=0 +.ENDS +.SUBCKT RSC_IHPSG13_DFNQMX2IX1 BE BI CN D QI QIN VDD VSS +MN15 net026 BI VSS VSS sg13_lv_nmos m=1 w=560.00n l=130.00n ng=1 nrd=0 ++ nrs=0 +MN14 MXI_OUT BE net026 VSS sg13_lv_nmos m=1 w=560.00n l=130.00n ng=1 nrd=0 ++ nrs=0 +MN1 net025 D VSS VSS sg13_lv_nmos m=1 w=560.00n l=130.00n ng=1 nrd=0 ++ nrs=0 +MN0 MXI_OUT BEN net025 VSS sg13_lv_nmos m=1 w=560.00n l=130.00n ng=1 nrd=0 ++ nrs=0 +MN10 QI CNN net21 VSS sg13_lv_nmos m=1 w=850.00n l=130.00n ng=1 nrd=0 nrs=0 +MN11 net21 QI_MS VSS VSS sg13_lv_nmos m=1 w=850.00n l=130.00n ng=1 ++ nrd=0 nrs=0 +MN7 net30 QI_MS VSS VSS sg13_lv_nmos m=1 w=480.00n l=130.00n ng=1 ++ nrd=0 nrs=0 +MN6 QIN_MS CNN net30 VSS sg13_lv_nmos m=1 w=480.00n l=130.00n ng=1 nrd=0 ++ nrs=0 +MN3 QI_MS QIN_MS VSS VSS sg13_lv_nmos m=1 w=480.00n l=130.00n ng=1 ++ nrd=0 nrs=0 +MN12 CNN CN VSS VSS sg13_lv_nmos m=1 w=495.000n l=130.00n ng=1 nrd=0 ++ nrs=0 +MN9 net37 MXI_OUT VSS VSS sg13_lv_nmos m=1 w=870.00n l=130.00n ng=1 ++ nrd=0 nrs=0 +MN8 QIN_MS CN net37 VSS sg13_lv_nmos m=1 w=870.00n l=130.00n ng=1 nrd=0 ++ nrs=0 +MN5 QI CN net25 VSS sg13_lv_nmos m=1 w=480.00n l=130.00n ng=1 nrd=0 nrs=0 +MN4 net25 QIN VSS VSS sg13_lv_nmos m=1 w=480.00n l=130.00n ng=1 nrd=0 ++ nrs=0 +MN2 QIN QI VSS VSS sg13_lv_nmos m=1 w=480.00n l=130.00n ng=1 nrd=0 ++ nrs=0 +MN13 BEN BE VSS VSS sg13_lv_nmos m=1 w=560.00n l=130.00n ng=1 nrd=0 ++ nrs=0 +MP15 MXI_OUT BEN net027 VDD sg13_lv_pmos m=1 w=985.000n l=130.00n ng=1 ++ nrd=0 nrs=0 +MP14 net027 BI VDD VDD sg13_lv_pmos m=1 w=985.000n l=130.00n ng=1 ++ nrd=0 nrs=0 +MP1 MXI_OUT BE net024 VDD sg13_lv_pmos m=1 w=985.000n l=130.00n ng=1 nrd=0 ++ nrs=0 +MP0 net024 D VDD VDD sg13_lv_pmos m=1 w=985.000n l=130.00n ng=1 nrd=0 ++ nrs=0 +MP13 BEN BE VDD VDD sg13_lv_pmos m=1 w=645.000n l=130.00n ng=1 nrd=0 ++ nrs=0 +MP6 QI_MS QIN_MS VDD VDD sg13_lv_pmos m=1 w=480.00n l=130.00n ng=1 ++ nrd=0 nrs=0 +MP3 QI CNN net27 VDD sg13_lv_pmos m=1 w=480.00n l=130.00n ng=1 nrd=0 nrs=0 +MP2 net27 QIN VDD VDD sg13_lv_pmos m=1 w=480.00n l=130.00n ng=1 nrd=0 ++ nrs=0 +MP10 net36 MXI_OUT VDD VDD sg13_lv_pmos m=1 w=975.000n l=130.00n ng=1 ++ nrd=0 nrs=0 +MP11 QIN_MS CNN net36 VDD sg13_lv_pmos m=1 w=975.000n l=130.00n ng=1 nrd=0 ++ nrs=0 +MP4 net32 QI_MS VDD VDD sg13_lv_pmos m=1 w=480.00n l=130.00n ng=1 ++ nrd=0 nrs=0 +MP5 QIN_MS CN net32 VDD sg13_lv_pmos m=1 w=480.00n l=130.00n ng=1 nrd=0 ++ nrs=0 +MP7 QIN QI VDD VDD sg13_lv_pmos m=1 w=480.00n l=130.00n ng=1 nrd=0 ++ nrs=0 +MP12 CNN CN VDD VDD sg13_lv_pmos m=1 w=480.00n l=130.00n ng=1 nrd=0 ++ nrs=0 +MP9 QI CN net19 VDD sg13_lv_pmos m=1 w=990.00n l=130.00n ng=1 nrd=0 nrs=0 +MP8 net19 QI_MS VDD VDD sg13_lv_pmos m=1 w=990.00n l=130.00n ng=1 ++ nrd=0 nrs=0 +.ENDS +.SUBCKT RM_IHPSG13_256x8_c3_1P_ROWREG4 ACLK_N_I ADDR_I<3> ADDR_I<2> ADDR_I<1> ADDR_I<0> ++ ADDR_N_O<3> ADDR_N_O<2> ADDR_N_O<1> ADDR_N_O<0> BIST_ADDR_I<3> ++ BIST_ADDR_I<2> BIST_ADDR_I<1> BIST_ADDR_I<0> BIST_EN_I VDD VSS +XINV<3> q_int<3> qn_int<3> VDD VSS / RSC_IHPSG13_CINVX2 +XINV<2> q_int<2> qn_int<2> VDD VSS / RSC_IHPSG13_CINVX2 +XINV<1> q_int<1> qn_int<1> VDD VSS / RSC_IHPSG13_CINVX2 +XINV<0> q_int<0> qn_int<0> VDD VSS / RSC_IHPSG13_CINVX2 +XDRV<3> qn_int<3> ADDR_N_O<3> VDD VSS / RSC_IHPSG13_CINVX8 +XDRV<2> qn_int<2> ADDR_N_O<2> VDD VSS / RSC_IHPSG13_CINVX8 +XDRV<1> qn_int<1> ADDR_N_O<1> VDD VSS / RSC_IHPSG13_CINVX8 +XDRV<0> qn_int<0> ADDR_N_O<0> VDD VSS / RSC_IHPSG13_CINVX8 +XDFF<3> BIST_EN_I BIST_ADDR_I<3> ACLK_N_I ADDR_I<3> q_int<3> net2<0> VDD ++ VSS / RSC_IHPSG13_DFNQMX2IX1 +XDFF<2> BIST_EN_I BIST_ADDR_I<2> ACLK_N_I ADDR_I<2> q_int<2> net2<1> VDD ++ VSS / RSC_IHPSG13_DFNQMX2IX1 +XDFF<1> BIST_EN_I BIST_ADDR_I<1> ACLK_N_I ADDR_I<1> q_int<1> net2<2> VDD ++ VSS / RSC_IHPSG13_DFNQMX2IX1 +XDFF<0> BIST_EN_I BIST_ADDR_I<0> ACLK_N_I ADDR_I<0> q_int<0> net2<3> VDD ++ VSS / RSC_IHPSG13_DFNQMX2IX1 +XI11<20> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI11<19> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI11<18> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI11<17> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI11<16> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI11<15> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI11<14> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI11<13> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI11<12> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI11<11> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI11<10> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI11<9> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI11<8> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI11<7> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI11<6> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI11<5> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI11<4> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI11<3> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI11<2> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI11<1> VDD VSS / RSC_IHPSG13_FILLCAP8 +.ENDS +.SUBCKT RSC_IHPSG13_CDLYX1 A Z VDD VSS +MN1 net010 net032 VSS VSS sg13_lv_nmos m=1 w=300.0n l=160.00n ng=1 ++ nrd=0 nrs=0 +MN2 net032 A net014 VSS sg13_lv_nmos m=1 w=300.0n l=160.00n ng=1 nrd=0 ++ nrs=0 +MN0 Z net032 net010 VSS sg13_lv_nmos m=1 w=300.0n l=160.00n ng=1 nrd=0 ++ nrs=0 +MN3 net014 A VSS VSS sg13_lv_nmos m=1 w=300.0n l=160.00n ng=1 nrd=0 ++ nrs=0 +MP1 Z net032 net07 VDD sg13_lv_pmos m=1 w=720.00n l=160.00n ng=1 nrd=0 ++ nrs=0 +MP3 net011 A VDD VDD sg13_lv_pmos m=1 w=720.00n l=160.00n ng=1 nrd=0 ++ nrs=0 +MP0 net07 net032 VDD VDD sg13_lv_pmos m=1 w=720.00n l=160.00n ng=1 ++ nrd=0 nrs=0 +MP2 net032 A net011 VDD sg13_lv_pmos m=1 w=720.00n l=160.00n ng=1 nrd=0 ++ nrs=0 +.ENDS +.SUBCKT RSC_IHPSG13_CDLYX1_DUMMY A Z VDD VSS +MN0 vss_r vdd_r VSS VSS sg13_lv_nmos m=1 w=2.49u l=300.0n ng=3 nrd=0 ++ nrs=0 +MP0 vdd_r vss_r VDD VDD sg13_lv_pmos m=1 w=3.24u l=640.00n ng=2 nrd=0 ++ nrs=0 +R0 Z A lvsres w=2.6e-07 l=6e-07 +.ENDS + +.SUBCKT RSC_IHPSG13_MX2IX1 A0 A1 S ZN VDD VSS +MP4 SN S VDD VDD sg13_lv_pmos m=1 w=645.000n l=130.00n ng=1 nrd=0 nrs=0 +MP3 ZN SN net12 VDD sg13_lv_pmos m=1 w=985.000n l=130.00n ng=1 nrd=0 nrs=0 +MP2 net12 A1 VDD VDD sg13_lv_pmos m=1 w=985.000n l=130.00n ng=1 nrd=0 ++ nrs=0 +MP1 ZN S net17 VDD sg13_lv_pmos m=1 w=985.000n l=130.00n ng=1 nrd=0 nrs=0 +MP0 net17 A0 VDD VDD sg13_lv_pmos m=1 w=985.000n l=130.00n ng=1 nrd=0 ++ nrs=0 +MN5 SN S VSS VSS sg13_lv_nmos m=1 w=480.00n l=130.00n ng=1 nrd=0 nrs=0 +MN3 net13 A1 VSS VSS sg13_lv_nmos m=1 w=480.00n l=130.00n ng=1 nrd=0 ++ nrs=0 +MN2 ZN S net13 VSS sg13_lv_nmos m=1 w=480.00n l=130.00n ng=1 nrd=0 nrs=0 +MN1 net15 A0 VSS VSS sg13_lv_nmos m=1 w=480.00n l=130.00n ng=1 nrd=0 ++ nrs=0 +MN0 ZN SN net15 VSS sg13_lv_nmos m=1 w=480.00n l=130.00n ng=1 nrd=0 nrs=0 +.ENDS +.SUBCKT RM_IHPSG13_256x8_c3_1P_DLY_MUX A SEL Z VDD VSS +XI11 net4 Z VDD VSS / RSC_IHPSG13_CINVX2 +XI8 A D<3> SEL net4 VDD VSS / RSC_IHPSG13_MX2IX1 +XI20<3> D<2> D<3> VDD VSS / RSC_IHPSG13_CDLYX1 +XI20<2> D<1> D<2> VDD VSS / RSC_IHPSG13_CDLYX1 +XI20<1> A D<1> VDD VSS / RSC_IHPSG13_CDLYX1 +.ENDS +.SUBCKT RSC_IHPSG13_DFNQX2 CN D Q VDD VSS +MN0 Q QIN_SL VSS VSS sg13_lv_nmos m=1 w=980.00n l=130.00n ng=1 nrd=0 ++ nrs=0 +MN10 QIN_SL CNN net21 VSS sg13_lv_nmos m=1 w=850.00n l=130.00n ng=1 nrd=0 ++ nrs=0 +MN11 net21 QI_MS VSS VSS sg13_lv_nmos m=1 w=850.00n l=130.00n ng=1 ++ nrd=0 nrs=0 +MN7 net30 QI_MS VSS VSS sg13_lv_nmos m=1 w=480.00n l=130.00n ng=1 ++ nrd=0 nrs=0 +MN6 QIN_MS CNN net30 VSS sg13_lv_nmos m=1 w=480.00n l=130.00n ng=1 nrd=0 ++ nrs=0 +MN3 QI_MS QIN_MS VSS VSS sg13_lv_nmos m=1 w=480.00n l=130.00n ng=1 ++ nrd=0 nrs=0 +MN12 CNN CN VSS VSS sg13_lv_nmos m=1 w=495.000n l=130.00n ng=1 nrd=0 ++ nrs=0 +MN9 net37 D VSS VSS sg13_lv_nmos m=1 w=870.00n l=130.00n ng=1 nrd=0 ++ nrs=0 +MN8 QIN_MS CN net37 VSS sg13_lv_nmos m=1 w=870.00n l=130.00n ng=1 nrd=0 ++ nrs=0 +MN5 QIN_SL CN net25 VSS sg13_lv_nmos m=1 w=480.00n l=130.00n ng=1 nrd=0 ++ nrs=0 +MN4 net25 QI_SL VSS VSS sg13_lv_nmos m=1 w=480.00n l=130.00n ng=1 ++ nrd=0 nrs=0 +MN2 QI_SL QIN_SL VSS VSS sg13_lv_nmos m=1 w=480.00n l=130.00n ng=1 ++ nrd=0 nrs=0 +MP0 Q QIN_SL VDD VDD sg13_lv_pmos m=1 w=1.62u l=130.00n ng=1 nrd=0 ++ nrs=0 +MP6 QI_MS QIN_MS VDD VDD sg13_lv_pmos m=1 w=480.00n l=130.00n ng=1 ++ nrd=0 nrs=0 +MP3 QIN_SL CNN net27 VDD sg13_lv_pmos m=1 w=480.00n l=130.00n ng=1 nrd=0 ++ nrs=0 +MP2 net27 QI_SL VDD VDD sg13_lv_pmos m=1 w=480.00n l=130.00n ng=1 ++ nrd=0 nrs=0 +MP10 net36 D VDD VDD sg13_lv_pmos m=1 w=975.000n l=130.00n ng=1 nrd=0 ++ nrs=0 +MP11 QIN_MS CNN net36 VDD sg13_lv_pmos m=1 w=975.000n l=130.00n ng=1 nrd=0 ++ nrs=0 +MP4 net32 QI_MS VDD VDD sg13_lv_pmos m=1 w=480.00n l=130.00n ng=1 ++ nrd=0 nrs=0 +MP5 QIN_MS CN net32 VDD sg13_lv_pmos m=1 w=480.00n l=130.00n ng=1 nrd=0 ++ nrs=0 +MP7 QI_SL QIN_SL VDD VDD sg13_lv_pmos m=1 w=480.00n l=130.00n ng=1 ++ nrd=0 nrs=0 +MP12 CNN CN VDD VDD sg13_lv_pmos m=1 w=480.00n l=130.00n ng=1 nrd=0 ++ nrs=0 +MP9 QIN_SL CN net19 VDD sg13_lv_pmos m=1 w=990.00n l=130.00n ng=1 nrd=0 ++ nrs=0 +MP8 net19 QI_MS VDD VDD sg13_lv_pmos m=1 w=990.00n l=130.00n ng=1 ++ nrd=0 nrs=0 +.ENDS +.SUBCKT RSC_IHPSG13_CNAND2X2 A B Z VDD VSS +MN0 Z B net6 VSS sg13_lv_nmos m=1 w=980.00n l=130.00n ng=1 nrd=0 nrs=0 +MN1 net6 A VSS VSS sg13_lv_nmos m=1 w=980.00n l=130.00n ng=1 nrd=0 ++ nrs=0 +MP1 Z B VDD VDD sg13_lv_pmos m=1 w=1.62u l=130.00n ng=1 nrd=0 nrs=0 +MP0 Z A VDD VDD sg13_lv_pmos m=1 w=1.62u l=130.00n ng=1 nrd=0 nrs=0 +.ENDS +.SUBCKT RSC_IHPSG13_CGATEPX4 CP E Q VDD VSS +MN1 net08 QIN VSS VSS sg13_lv_nmos m=1 w=480.00n l=130.00n ng=1 nrd=0 ++ nrs=0 +MN2 net019 net08 VSS VSS sg13_lv_nmos m=1 w=480.00n l=130.00n ng=1 ++ nrd=0 nrs=0 +MN3 QIN CP net019 VSS sg13_lv_nmos m=1 w=480.00n l=130.00n ng=1 nrd=0 nrs=0 +MN6 Q net015 VSS VSS sg13_lv_nmos m=1 w=1.41u l=130.00n ng=2 nrd=0 ++ nrs=0 +MN5 net015 net08 net018 VSS sg13_lv_nmos m=1 w=980.00n l=130.00n ng=1 ++ nrd=0 nrs=0 +MN8 QIN CPN net023 VSS sg13_lv_nmos m=1 w=870.00n l=130.00n ng=1 nrd=0 ++ nrs=0 +MN7 net023 E VSS VSS sg13_lv_nmos m=1 w=870.00n l=130.00n ng=1 nrd=0 ++ nrs=0 +MN4 net018 CP VSS VSS sg13_lv_nmos m=1 w=980.00n l=130.00n ng=1 nrd=0 ++ nrs=0 +MN0 CPN CP VSS VSS sg13_lv_nmos m=1 w=500.0n l=130.00n ng=1 nrd=0 nrs=0 +MP3 net08 QIN VDD VDD sg13_lv_pmos m=1 w=480.00n l=130.00n ng=1 nrd=0 ++ nrs=0 +MP2 QIN CPN net017 VDD sg13_lv_pmos m=1 w=480.00n l=130.00n ng=1 nrd=0 ++ nrs=0 +MP1 net017 net08 VDD VDD sg13_lv_pmos m=1 w=480.00n l=130.00n ng=1 ++ nrd=0 nrs=0 +MP0 CPN CP VDD VDD sg13_lv_pmos m=1 w=500.0n l=130.00n ng=1 nrd=0 nrs=0 +MP8 QIN CP net024 VDD sg13_lv_pmos m=1 w=975.000n l=130.00n ng=1 nrd=0 ++ nrs=0 +MP7 net024 E VDD VDD sg13_lv_pmos m=1 w=975.000n l=130.00n ng=1 nrd=0 ++ nrs=0 +MP4 net015 CP VDD VDD sg13_lv_pmos m=1 w=1.27u l=130.00n ng=1 nrd=0 ++ nrs=0 +MP6 Q net015 VDD VDD sg13_lv_pmos m=1 w=3.24u l=130.00n ng=2 nrd=0 ++ nrs=0 +MP5 net015 net08 VDD VDD sg13_lv_pmos m=1 w=1.27u l=130.00n ng=1 nrd=0 ++ nrs=0 +.ENDS +.SUBCKT RSC_IHPSG13_CBUFX8 A Z VDD VSS +MP0 net4 A VDD VDD sg13_lv_pmos m=1 w=3.24u l=130.00n ng=2 nrd=0 nrs=0 +MP1 Z net4 VDD VDD sg13_lv_pmos m=1 w=6.48u l=130.00n ng=4 nrd=0 nrs=0 +MN1 Z net4 VSS VSS sg13_lv_nmos m=1 w=2.82u l=130.00n ng=4 nrd=0 nrs=0 +MN0 net4 A VSS VSS sg13_lv_nmos m=1 w=1.41u l=130.00n ng=2 nrd=0 nrs=0 +.ENDS +.SUBCKT RSC_IHPSG13_CDLYX2 A Z VDD VSS +MN2 net4 A net9 VSS sg13_lv_nmos m=1 w=320.00n l=200.0n ng=1 nrd=0 nrs=0 +MN0 Z net4 VSS VSS sg13_lv_nmos m=1 w=705.000n l=130.00n ng=1 nrd=0 ++ nrs=0 +MN1 net9 A VSS VSS sg13_lv_nmos m=1 w=320.00n l=200.0n ng=1 nrd=0 nrs=0 +MP2 net4 A net10 VDD sg13_lv_pmos m=1 w=1.2u l=200.0n ng=1 nrd=0 nrs=0 +MP1 net10 A VDD VDD sg13_lv_pmos m=1 w=1.2u l=200.0n ng=1 nrd=0 nrs=0 +MP0 Z net4 VDD VDD sg13_lv_pmos m=1 w=1.62u l=130.00n ng=1 nrd=0 nrs=0 +.ENDS +.SUBCKT RSC_IHPSG13_MX2X2 A0 A1 S Z VDD VSS +MP6 Z net010 VDD VDD sg13_lv_pmos m=1 w=1.62u l=130.00n ng=1 nrd=0 ++ nrs=0 +MP4 SN S VDD VDD sg13_lv_pmos m=1 w=645.000n l=130.00n ng=1 nrd=0 nrs=0 +MP3 net010 SN net12 VDD sg13_lv_pmos m=1 w=985.000n l=130.00n ng=1 nrd=0 ++ nrs=0 +MP2 net12 A1 VDD VDD sg13_lv_pmos m=1 w=985.000n l=130.00n ng=1 nrd=0 ++ nrs=0 +MP1 net010 S net17 VDD sg13_lv_pmos m=1 w=985.000n l=130.00n ng=1 nrd=0 ++ nrs=0 +MP0 net17 A0 VDD VDD sg13_lv_pmos m=1 w=985.000n l=130.00n ng=1 nrd=0 ++ nrs=0 +MN6 Z net010 VSS VSS sg13_lv_nmos m=1 w=705.000n l=130.00n ng=1 nrd=0 ++ nrs=0 +MN5 SN S VSS VSS sg13_lv_nmos m=1 w=560.00n l=130.00n ng=1 nrd=0 nrs=0 +MN3 net13 A1 VSS VSS sg13_lv_nmos m=1 w=560.00n l=130.00n ng=1 nrd=0 ++ nrs=0 +MN2 net010 S net13 VSS sg13_lv_nmos m=1 w=560.00n l=130.00n ng=1 nrd=0 ++ nrs=0 +MN1 net15 A0 VSS VSS sg13_lv_nmos m=1 w=560.00n l=130.00n ng=1 nrd=0 ++ nrs=0 +MN0 net010 SN net15 VSS sg13_lv_nmos m=1 w=560.00n l=130.00n ng=1 nrd=0 ++ nrs=0 +.ENDS +.SUBCKT RSC_IHPSG13_AND2X2 A B Z VDD VSS +MN3 Z net6 VSS VSS sg13_lv_nmos m=1 w=980.00n l=130.00n ng=1 nrd=0 ++ nrs=0 +MN4 net9 B VSS VSS sg13_lv_nmos m=1 w=500.0n l=130.00n ng=1 nrd=0 nrs=0 +MN6 net6 A net9 VSS sg13_lv_nmos m=1 w=500.0n l=130.00n ng=1 nrd=0 nrs=0 +MP2 Z net6 VDD VDD sg13_lv_pmos m=1 w=1.62u l=130.00n ng=1 nrd=0 nrs=0 +MP0 net6 B VDD VDD sg13_lv_pmos m=1 w=860.00n l=130.00n ng=1 nrd=0 ++ nrs=0 +MP1 net6 A VDD VDD sg13_lv_pmos m=1 w=860.00n l=130.00n ng=1 nrd=0 ++ nrs=0 +.ENDS +.SUBCKT RSC_IHPSG13_TIEL Z VDD VSS +MN0 Z net2 VSS VSS sg13_lv_nmos m=1 w=480.00n l=130.00n ng=1 nrd=0 ++ nrs=0 +MP0 net2 net2 VDD VDD sg13_lv_pmos m=1 w=480.00n l=130.00n ng=1 nrd=0 ++ nrs=0 +.ENDS +.SUBCKT RSC_IHPSG13_XOR2X2 A B Z VDD VSS +MP8 net012 B net7 VDD sg13_lv_pmos m=1 w=825.000n l=130.00n ng=1 nrd=0 ++ nrs=0 +MP7 net011 net3 net012 VDD sg13_lv_pmos m=1 w=825.000n l=130.00n ng=1 ++ nrd=0 nrs=0 +MP6 Z net012 VDD VDD sg13_lv_pmos m=1 w=1.535u l=130.00n ng=1 nrd=0 ++ nrs=0 +MP2 net7 A VDD VDD sg13_lv_pmos m=1 w=825.000n l=130.00n ng=1 nrd=0 ++ nrs=0 +MP4 net011 net7 VDD VDD sg13_lv_pmos m=1 w=825.000n l=130.00n ng=1 ++ nrd=0 nrs=0 +MP5 net3 B VDD VDD sg13_lv_pmos m=1 w=580.00n l=130.00n ng=1 nrd=0 ++ nrs=0 +MN7 net012 B net011 VSS sg13_lv_nmos m=1 w=555.000n l=130.00n ng=1 nrd=0 ++ nrs=0 +MN6 net7 net3 net012 VSS sg13_lv_nmos m=1 w=555.000n l=130.00n ng=1 nrd=0 ++ nrs=0 +MN5 Z net012 VSS VSS sg13_lv_nmos m=1 w=775.000n l=130.00n ng=1 nrd=0 ++ nrs=0 +MN2 net7 A VSS VSS sg13_lv_nmos m=1 w=555.000n l=130.00n ng=1 nrd=0 ++ nrs=0 +MN4 net3 B VSS VSS sg13_lv_nmos m=1 w=480.00n l=130.00n ng=1 nrd=0 ++ nrs=0 +MN3 net011 net7 VSS VSS sg13_lv_nmos m=1 w=555.000n l=130.00n ng=1 ++ nrd=0 nrs=0 +.ENDS +.SUBCKT RSC_IHPSG13_OA12X1 A B C Z VDD VSS +MN2 net7 C VSS VSS sg13_lv_nmos m=1 w=980.00n l=130.00n ng=1 nrd=0 ++ nrs=0 +MN3 Z net17 VSS VSS sg13_lv_nmos m=1 w=500.0n l=130.00n ng=1 nrd=0 ++ nrs=0 +MN1 net17 B net7 VSS sg13_lv_nmos m=1 w=980.00n l=130.00n ng=1 nrd=0 nrs=0 +MN0 net17 A net7 VSS sg13_lv_nmos m=1 w=980.00n l=130.00n ng=1 nrd=0 nrs=0 +MP0 net24 A VDD VDD sg13_lv_pmos m=1 w=1.62u l=130.00n ng=1 nrd=0 nrs=0 +MP3 Z net17 VDD VDD sg13_lv_pmos m=1 w=905.000n l=130.00n ng=1 nrd=0 ++ nrs=0 +MP1 net17 B net24 VDD sg13_lv_pmos m=1 w=1.62u l=130.00n ng=1 nrd=0 nrs=0 +MP2 net17 C VDD VDD sg13_lv_pmos m=1 w=905.000n l=130.00n ng=1 nrd=0 ++ nrs=0 +.ENDS +.SUBCKT RM_IHPSG13_256x8_c3_1P_CTRL ACLK_N BIST_CK_I BIST_CS_I BIST_EN BIST_RE_I ++ BIST_WE_I B_TIEL_O CK_I CS_I DCLK ECLK PULSE_H PULSE_L PULSE_O RCLK RE_I ++ ROW_CS WCLK WE_I VDD VSS +XI17 ck_regs we col_we VDD VSS / RSC_IHPSG13_DFNQX2 +XI16 ck_regs re col_re VDD VSS / RSC_IHPSG13_DFNQX2 +XI18 ck_regs cs net7 VDD VSS / RSC_IHPSG13_DFNQX2 +XI71 ACLK_N net012 PULSE_O VDD VSS / RSC_IHPSG13_DFNQX2 +XI77 col_we net9 net016 VDD VSS / RSC_IHPSG13_CNAND2X2 +XI76 col_re net9 net018 VDD VSS / RSC_IHPSG13_CNAND2X2 +XI15 ck_dly WEorREandCS aclk VDD VSS / RSC_IHPSG13_CGATEPX4 +XI14 ck WEandCS DCLK VDD VSS / RSC_IHPSG13_CGATEPX4 +XI60 net7 ROW_CS VDD VSS / RSC_IHPSG13_CBUFX8 +XI73 PULSE_O net012 VDD VSS / RSC_IHPSG13_CINVX2 +XI8 net9 net8 VDD VSS / RSC_IHPSG13_CINVX2 +XI64 ck ck_dly VDD VSS / RSC_IHPSG13_CDLYX2 +XI86 CS_I BIST_CS_I BIST_EN cs VDD VSS / RSC_IHPSG13_MX2X2 +XI87 CK_I BIST_CK_I BIST_EN ck VDD VSS / RSC_IHPSG13_MX2X2 +XI85 WE_I BIST_WE_I BIST_EN we VDD VSS / RSC_IHPSG13_MX2X2 +XI84 RE_I BIST_RE_I BIST_EN re VDD VSS / RSC_IHPSG13_MX2X2 +XI22 we cs WEandCS VDD VSS / RSC_IHPSG13_AND2X2 +XBM_TIEL B_TIEL_O VDD VSS / RSC_IHPSG13_TIEL +XI48 ck_dly ck_regs VDD VSS / RSC_IHPSG13_CINVX4 +XI81 net016 WCLK VDD VSS / RSC_IHPSG13_CINVX4 +XI80 net018 RCLK VDD VSS / RSC_IHPSG13_CINVX4 +XI78 net8 net020 VDD VSS / RSC_IHPSG13_CINVX4 +XI6 PULSE_L PULSE_H net9 VDD VSS / RSC_IHPSG13_XOR2X2 +XI79 net020 ECLK VDD VSS / RSC_IHPSG13_CINVX8 +XI63 aclk ACLK_N VDD VSS / RSC_IHPSG13_CINVX8 +XI21 re we cs WEorREandCS VDD VSS / RSC_IHPSG13_OA12X1 +.ENDS +.SUBCKT RM_IHPSG13_256x8_c3_1P_COLDEC2 ACLK_N ADDR<1> ADDR<0> ADDR_COL<1> ADDR_COL<0> ++ ADDR_DEC<7> ADDR_DEC<6> ADDR_DEC<5> ADDR_DEC<4> ADDR_DEC<3> ADDR_DEC<2> ++ ADDR_DEC<1> ADDR_DEC<0> BIST_ADDR<1> BIST_ADDR<0> BIST_EN_I VDD VSS +XI14<5> VDD VSS / RSC_IHPSG13_FILLCAP4 +XI14<4> VDD VSS / RSC_IHPSG13_FILLCAP4 +XI14<3> VDD VSS / RSC_IHPSG13_FILLCAP4 +XI14<2> VDD VSS / RSC_IHPSG13_FILLCAP4 +XI14<1> VDD VSS / RSC_IHPSG13_FILLCAP4 +XDFF<1> BIST_EN_I BIST_ADDR<1> ACLK_N ADDR<1> padr_int<1> net6<0> VDD ++ VSS / RSC_IHPSG13_DFNQMX2IX1 +XDFF<0> BIST_EN_I BIST_ADDR<0> ACLK_N ADDR<0> padr_int<0> net6<1> VDD ++ VSS / RSC_IHPSG13_DFNQMX2IX1 +XI1<3> PADR<1> PADR<0> addr_n<3> VDD VSS / RSC_IHPSG13_NAND2X2 +XI1<2> PADR<1> NADR<0> addr_n<2> VDD VSS / RSC_IHPSG13_NAND2X2 +XI1<1> NADR<1> PADR<0> addr_n<1> VDD VSS / RSC_IHPSG13_NAND2X2 +XI1<0> NADR<1> NADR<0> addr_n<0> VDD VSS / RSC_IHPSG13_NAND2X2 +XI16<37> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI16<36> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI16<35> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI16<34> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI16<33> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI16<32> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI16<31> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI16<30> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI16<29> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI16<28> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI16<27> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI16<26> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI16<25> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI16<24> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI16<23> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI16<22> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI16<21> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI16<20> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI16<19> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI16<18> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI16<17> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI16<16> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI16<15> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI16<14> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI16<13> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI16<12> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI16<11> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI16<10> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI16<9> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI16<8> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI16<7> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI16<6> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI16<5> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI16<4> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI16<3> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI16<2> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI16<1> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI3<1> padr_int<1> NADR<1> VDD VSS / RSC_IHPSG13_INVX2 +XI3<0> padr_int<0> NADR<0> VDD VSS / RSC_IHPSG13_INVX2 +XI13<1> NADR<1> PADR<1> VDD VSS / RSC_IHPSG13_INVX2 +XI13<0> NADR<0> PADR<0> VDD VSS / RSC_IHPSG13_INVX2 +XI2<3> addr_n<3> ADDR_DEC<3> VDD VSS / RSC_IHPSG13_INVX2 +XI2<2> addr_n<2> ADDR_DEC<2> VDD VSS / RSC_IHPSG13_INVX2 +XI2<1> addr_n<1> ADDR_DEC<1> VDD VSS / RSC_IHPSG13_INVX2 +XI2<0> addr_n<0> ADDR_DEC<0> VDD VSS / RSC_IHPSG13_INVX2 +XI15<1> ADDR_COL<1> VDD VSS / RSC_IHPSG13_TIEL +XI15<0> ADDR_COL<0> VDD VSS / RSC_IHPSG13_TIEL +XI17<3> ADDR_DEC<7> VDD VSS / RSC_IHPSG13_TIEL +XI17<2> ADDR_DEC<6> VDD VSS / RSC_IHPSG13_TIEL +XI17<1> ADDR_DEC<5> VDD VSS / RSC_IHPSG13_TIEL +XI17<0> ADDR_DEC<4> VDD VSS / RSC_IHPSG13_TIEL +.ENDS +.SUBCKT RSC_IHPSG13_NOR2X2 A B Z VDD VSS +MP1 Z B net9 VDD sg13_lv_pmos m=1 w=1.62u l=130.00n ng=1 nrd=0 nrs=0 +MP0 net9 A VDD VDD sg13_lv_pmos m=1 w=1.62u l=130.00n ng=1 nrd=0 nrs=0 +MN0 Z B VSS VSS sg13_lv_nmos m=1 w=980.00n l=130.00n ng=1 nrd=0 nrs=0 +MN1 Z A VSS VSS sg13_lv_nmos m=1 w=980.00n l=130.00n ng=1 nrd=0 nrs=0 +.ENDS +.SUBCKT RSC_IHPSG13_CINVX4_WN A Z VDD VSS +MN0 Z A VSS VSS sg13_lv_nmos m=1 w=705.000n l=130.00n ng=1 nrd=0 nrs=0 +MP0 Z A VDD VDD sg13_lv_pmos m=1 w=3.24u l=130.00n ng=2 nrd=0 nrs=0 +.ENDS +.SUBCKT RM_IHPSG13_256x8_c3_1P_BLDRV BLC BLC_SEL BLT BLT_SEL PRE_N SEL_P WR_ONE WR_ZERO ++ VDD VSS +XCDEC SEL_P WR_ZERO BLC_PMOS_DRIVE VDD VSS / RSC_IHPSG13_NAND2X2 +XTDEC SEL_P WR_ONE BLT_PMOS_DRIVE VDD VSS / RSC_IHPSG13_NAND2X2 +MTWN BLT BLT_NMOS_DRIVE VSS VSS sg13_lv_nmos m=1 w=4.82u l=130.00n ++ ng=2 nrd=0 nrs=0 +MCWN BLC BLC_NMOS_DRIVE VSS VSS sg13_lv_nmos m=1 w=4.82u l=130.00n ++ ng=2 nrd=0 nrs=0 +MCWP BLC BLC_PMOS_DRIVE VDD VDD sg13_lv_pmos m=1 w=1.5u l=130.00n ng=1 ++ nrd=0 nrs=0 +MTWP BLT BLT_PMOS_DRIVE VDD VDD sg13_lv_pmos m=1 w=1.5u l=130.00n ng=1 ++ nrd=0 nrs=0 +MTSP BLT_SEL SEL_N BLT VDD sg13_lv_pmos m=1 w=1.5u l=130.00n ng=1 nrd=0 ++ nrs=0 +MTPR BLT PRE_N VDD VDD sg13_lv_pmos m=1 w=3.000u l=130.00n ng=2 nrd=0 ++ nrs=0 +MCSP BLC_SEL SEL_N BLC VDD sg13_lv_pmos m=1 w=1.5u l=130.00n ng=1 nrd=0 ++ nrs=0 +MCPR BLC PRE_N VDD VDD sg13_lv_pmos m=1 w=3.000u l=130.00n ng=2 nrd=0 ++ nrs=0 +XI86 SEL_P SEL_N VDD VSS / RSC_IHPSG13_INVX2 +XTINV BLC_PMOS_DRIVE BLT_NMOS_DRIVE VDD VSS / RSC_IHPSG13_INVX2 +XCINV BLT_PMOS_DRIVE BLC_NMOS_DRIVE VDD VSS / RSC_IHPSG13_INVX2 +.ENDS +.SUBCKT RSC_IHPSG13_TIEH Z VDD VSS +MN0 net2 net2 VSS VSS sg13_lv_nmos m=1 w=480.00n l=130.00n ng=1 nrd=0 ++ nrs=0 +MP0 Z net2 VDD VDD sg13_lv_pmos m=1 w=480.00n l=130.00n ng=1 nrd=0 ++ nrs=0 +.ENDS +.SUBCKT RSC_IHPSG13_MET3RES A B +R0 B A lvsres w=2.6e-07 l=6e-07 +.ENDS +.SUBCKT RSC_IHPSG13_DFPQD_MSAFFX2 CP DN DP QN QP VDD VSS +MN12 SN RN DIFFP VSS sg13_lv_nmos m=1 w=2.4u l=200.0n ng=2 nrd=0 nrs=0 +MN13 TAIL CP VSS VSS sg13_lv_nmos m=1 w=2.4u l=130.00n ng=2 nrd=0 nrs=0 +MN9 DIFFP DP TAIL VSS sg13_lv_nmos m=1 w=2.4u l=200.0n ng=2 nrd=0 nrs=0 +MN10 DIFFN DN TAIL VSS sg13_lv_nmos m=1 w=2.4u l=200.0n ng=2 nrd=0 nrs=0 +MN11 RN SN DIFFN VSS sg13_lv_nmos m=1 w=2.4u l=200.0n ng=2 nrd=0 nrs=0 +MN19 net33 SN VSS VSS sg13_lv_nmos m=1 w=980.00n l=130.00n ng=1 nrd=0 ++ nrs=0 +MN20 QN QP net37 VSS sg13_lv_nmos m=1 w=980.00n l=130.00n ng=1 nrd=0 nrs=0 +MN18 net37 RN VSS VSS sg13_lv_nmos m=1 w=980.00n l=130.00n ng=1 nrd=0 ++ nrs=0 +MN17 QP QN net33 VSS sg13_lv_nmos m=1 w=980.00n l=130.00n ng=1 nrd=0 nrs=0 +MP15 SN RN VDD VDD sg13_lv_pmos m=1 w=800.0n l=130.00n ng=1 nrd=0 nrs=0 +MP16 RN CP VDD VDD sg13_lv_pmos m=1 w=800.0n l=130.00n ng=1 nrd=0 nrs=0 +MP14 DIFFP CP VDD VDD sg13_lv_pmos m=1 w=800.0n l=130.00n ng=1 nrd=0 ++ nrs=0 +MP12 RN SN VDD VDD sg13_lv_pmos m=1 w=800.0n l=130.00n ng=1 nrd=0 nrs=0 +MP13 DIFFN CP VDD VDD sg13_lv_pmos m=1 w=800.0n l=130.00n ng=1 nrd=0 ++ nrs=0 +MP11 SN CP VDD VDD sg13_lv_pmos m=1 w=800.0n l=130.00n ng=1 nrd=0 nrs=0 +MP19 QN QP VDD VDD sg13_lv_pmos m=1 w=900.0n l=130.00n ng=1 nrd=0 nrs=0 +MP20 QP SN VDD VDD sg13_lv_pmos m=1 w=1.8u l=130.00n ng=2 nrd=0 nrs=0 +MP18 QN RN VDD VDD sg13_lv_pmos m=1 w=1.8u l=130.00n ng=2 nrd=0 nrs=0 +MP17 QP QN VDD VDD sg13_lv_pmos m=1 w=900.0n l=130.00n ng=1 nrd=0 nrs=0 +.ENDS +.SUBCKT RSC_IHPSG13_CBUFX2 A Z VDD VSS +MN1 Z net4 VSS VSS sg13_lv_nmos m=1 w=705.000n l=130.00n ng=1 nrd=0 ++ nrs=0 +MN0 net4 A VSS VSS sg13_lv_nmos m=1 w=540.00n l=130.00n ng=1 nrd=0 ++ nrs=0 +MP1 Z net4 VDD VDD sg13_lv_pmos m=1 w=1.62u l=130.00n ng=1 nrd=0 nrs=0 +MP0 net4 A VDD VDD sg13_lv_pmos m=1 w=1.1u l=130.00n ng=1 nrd=0 nrs=0 +.ENDS +.SUBCKT RSC_IHPSG13_INVX4 A Z VDD VSS +MN0 Z A VSS VSS sg13_lv_nmos m=1 w=1.96u l=130.00n ng=2 nrd=0 nrs=0 +MP0 Z A VDD VDD sg13_lv_pmos m=1 w=3.24u l=130.00n ng=2 nrd=0 nrs=0 +.ENDS +.SUBCKT RM_IHPSG13_256x8_c3_1P_COLCTRL2 A_ADDR_DEC<3> A_ADDR_DEC<2> A_ADDR_DEC<1> ++ A_ADDR_DEC<0> A_BIST_BM_I A_BIST_DW_I A_BIST_EN_I A_BLC<3> A_BLC<2> A_BLC<1> ++ A_BLC<0> A_BLT<3> A_BLT<2> A_BLT<1> A_BLT<0> A_BM_I A_DCLK_B_L A_DCLK_B_R ++ A_DCLK_L A_DCLK_R A_DR_O A_DW_I A_RCLK_B_L A_RCLK_B_R A_RCLK_L A_RCLK_R ++ A_TIEH_O A_WCLK_B_L A_WCLK_B_R A_WCLK_L A_WCLK_R VDD VSS +XA_DREG A_BIST_EN_I A_BIST_DW_I A_DCLK_B_L A_DW_I A_DI_R net22 VDD VSS ++ / RSC_IHPSG13_DFNQMX2IX1 +XA_BREG A_BIST_EN_I A_BIST_BM_I A_DCLK_B_L A_BM_I A_BM_R net23 VDD VSS ++ / RSC_IHPSG13_DFNQMX2IX1 +XA_CAPS<5> VDD VSS / RSC_IHPSG13_FILLCAP4 +XA_CAPS<4> VDD VSS / RSC_IHPSG13_FILLCAP4 +XA_CAPS<3> VDD VSS / RSC_IHPSG13_FILLCAP4 +XA_CAPS<2> VDD VSS / RSC_IHPSG13_FILLCAP4 +XA_CAPS<1> VDD VSS / RSC_IHPSG13_FILLCAP4 +XA_I80 A_WCLK_B_R A_RCLK_B_R net21 VDD VSS / RSC_IHPSG13_AND2X2 +XA_I75 A_DI_R A_DO_WRITE_P A_WR_ONE VDD VSS / RSC_IHPSG13_AND2X2 +XA_I76 A_DI_N A_DO_WRITE_P A_WR_ZERO VDD VSS / RSC_IHPSG13_AND2X2 +XA_I44 A_WCLK_B_R A_BM_N A_DO_WRITE_P VDD VSS / RSC_IHPSG13_NOR2X2 +XA_I81 net21 A_PRE_N VDD VSS / RSC_IHPSG13_CINVX4_WN +XA_BLTMUX<3> A_BLC<3> A_BLC_SEL A_BLT<3> A_BLT_SEL A_PRE_N A_ADDR_DEC<3> ++ A_WR_ONE A_WR_ZERO VDD VSS / RM_IHPSG13_256x8_c3_1P_BLDRV +XA_BLTMUX<2> A_BLC<2> A_BLC_SEL A_BLT<2> A_BLT_SEL A_PRE_N A_ADDR_DEC<2> ++ A_WR_ONE A_WR_ZERO VDD VSS / RM_IHPSG13_256x8_c3_1P_BLDRV +XA_BLTMUX<1> A_BLC<1> A_BLC_SEL A_BLT<1> A_BLT_SEL A_PRE_N A_ADDR_DEC<1> ++ A_WR_ONE A_WR_ZERO VDD VSS / RM_IHPSG13_256x8_c3_1P_BLDRV +XA_BLTMUX<0> A_BLC<0> A_BLC_SEL A_BLT<0> A_BLT_SEL A_PRE_N A_ADDR_DEC<0> ++ A_WR_ONE A_WR_ZERO VDD VSS / RM_IHPSG13_256x8_c3_1P_BLDRV +XA_BM_TIEH A_TIEH_O VDD VSS / RSC_IHPSG13_TIEH +XA_I89 A_DCLK_B_L A_DCLK_B_R / RSC_IHPSG13_MET3RES +XA_I88 A_DCLK_L A_DCLK_R / RSC_IHPSG13_MET3RES +XA_I87 A_WCLK_L A_WCLK_R / RSC_IHPSG13_MET3RES +XA_I91 A_RCLK_B_R A_RCLK_B_L / RSC_IHPSG13_MET3RES +XA_R2 A_RCLK_R A_RCLK_L / RSC_IHPSG13_MET3RES +XA_I90 A_WCLK_B_R A_WCLK_B_L / RSC_IHPSG13_MET3RES +XA_ISENSE A_SAE A_BLC_SEL A_BLT_SEL net19 net20 VDD VSS / ++ RSC_IHPSG13_DFPQD_MSAFFX2 +XA_I78 A_RCLK_B_R A_SAE VDD VSS / RSC_IHPSG13_CBUFX2 +XA_I83 A_BM_R A_BM_N VDD VSS / RSC_IHPSG13_INVX2 +XA_I49 A_DI_R A_DI_N VDD VSS / RSC_IHPSG13_INVX2 +XA_I51 net19 A_DR_O VDD VSS / RSC_IHPSG13_INVX4 +XA_I69 A_DCLK_L A_DCLK_B_L VDD VSS / RSC_IHPSG13_CINVX2 +XA_I50 A_WCLK_L A_WCLK_B_R VDD VSS / RSC_IHPSG13_CINVX2 +XA_EBUF A_RCLK_R A_RCLK_B_R VDD VSS / RSC_IHPSG13_CINVX2 +.ENDS +.SUBCKT RM_IHPSG13_256x8_c3_1P_COLDRV13_FILL4 VDD VSS +XI0<9> VDD VSS / RSC_IHPSG13_FILLCAP4 +XI0<8> VDD VSS / RSC_IHPSG13_FILLCAP4 +XI0<7> VDD VSS / RSC_IHPSG13_FILLCAP4 +XI0<6> VDD VSS / RSC_IHPSG13_FILLCAP4 +XI0<5> VDD VSS / RSC_IHPSG13_FILLCAP4 +XI0<4> VDD VSS / RSC_IHPSG13_FILLCAP4 +XI0<3> VDD VSS / RSC_IHPSG13_FILLCAP4 +XI0<2> VDD VSS / RSC_IHPSG13_FILLCAP4 +XI0<1> VDD VSS / RSC_IHPSG13_FILLCAP4 +.ENDS +.SUBCKT RM_IHPSG13_256x8_c3_1P_COLDRV13_FILL4C2 VDD VSS +XI0<2> VDD VSS / RSC_IHPSG13_FILLCAP4 +XI0<1> VDD VSS / RSC_IHPSG13_FILLCAP4 +.ENDS + + +.SUBCKT RM_IHPSG13_256x8_c3_1P_COLDEC4 ACLK_N ADDR<3> ADDR<2> ADDR<1> ADDR<0> ++ ADDR_COL<1> ADDR_COL<0> ADDR_DEC<7> ADDR_DEC<6> ADDR_DEC<5> ADDR_DEC<4> ++ ADDR_DEC<3> ADDR_DEC<2> ADDR_DEC<1> ADDR_DEC<0> BIST_ADDR<3> BIST_ADDR<2> ++ BIST_ADDR<1> BIST_ADDR<0> BIST_EN_I VDD VSS +XI15 ADDR_COL<1> VDD VSS / RSC_IHPSG13_TIEL +XI14 addr_int ADDR_COL<0> VDD VSS / RSC_IHPSG13_CBUFX2 +XDFF<3> BIST_EN_I BIST_ADDR<3> ACLK_N ADDR<3> addr_int net7<0> VDD VSS ++ / RSC_IHPSG13_DFNQMX2IX1 +XDFF<2> BIST_EN_I BIST_ADDR<2> ACLK_N ADDR<2> padr_int<2> net7<1> VDD ++ VSS / RSC_IHPSG13_DFNQMX2IX1 +XDFF<1> BIST_EN_I BIST_ADDR<1> ACLK_N ADDR<1> padr_int<1> net7<2> VDD ++ VSS / RSC_IHPSG13_DFNQMX2IX1 +XDFF<0> BIST_EN_I BIST_ADDR<0> ACLK_N ADDR<0> padr_int<0> net7<3> VDD ++ VSS / RSC_IHPSG13_DFNQMX2IX1 +XI1<7> PADR<0> PADR<1> PADR<2> addr_n<7> VDD VSS / RSC_IHPSG13_NAND3X2 +XI1<6> NADR<0> PADR<1> PADR<2> addr_n<6> VDD VSS / RSC_IHPSG13_NAND3X2 +XI1<5> PADR<0> NADR<1> PADR<2> addr_n<5> VDD VSS / RSC_IHPSG13_NAND3X2 +XI1<4> NADR<0> NADR<1> PADR<2> addr_n<4> VDD VSS / RSC_IHPSG13_NAND3X2 +XI1<3> PADR<0> PADR<1> NADR<2> addr_n<3> VDD VSS / RSC_IHPSG13_NAND3X2 +XI1<2> NADR<0> PADR<1> NADR<2> addr_n<2> VDD VSS / RSC_IHPSG13_NAND3X2 +XI1<1> PADR<0> NADR<1> NADR<2> addr_n<1> VDD VSS / RSC_IHPSG13_NAND3X2 +XI1<0> NADR<0> NADR<1> NADR<2> addr_n<0> VDD VSS / RSC_IHPSG13_NAND3X2 +XI13<2> NADR<2> PADR<2> VDD VSS / RSC_IHPSG13_INVX2 +XI13<1> NADR<1> PADR<1> VDD VSS / RSC_IHPSG13_INVX2 +XI13<0> NADR<0> PADR<0> VDD VSS / RSC_IHPSG13_INVX2 +XI3<2> padr_int<2> NADR<2> VDD VSS / RSC_IHPSG13_INVX2 +XI3<1> padr_int<1> NADR<1> VDD VSS / RSC_IHPSG13_INVX2 +XI3<0> padr_int<0> NADR<0> VDD VSS / RSC_IHPSG13_INVX2 +XI2<7> addr_n<7> ADDR_DEC<7> VDD VSS / RSC_IHPSG13_INVX2 +XI2<6> addr_n<6> ADDR_DEC<6> VDD VSS / RSC_IHPSG13_INVX2 +XI2<5> addr_n<5> ADDR_DEC<5> VDD VSS / RSC_IHPSG13_INVX2 +XI2<4> addr_n<4> ADDR_DEC<4> VDD VSS / RSC_IHPSG13_INVX2 +XI2<3> addr_n<3> ADDR_DEC<3> VDD VSS / RSC_IHPSG13_INVX2 +XI2<2> addr_n<2> ADDR_DEC<2> VDD VSS / RSC_IHPSG13_INVX2 +XI2<1> addr_n<1> ADDR_DEC<1> VDD VSS / RSC_IHPSG13_INVX2 +XI2<0> addr_n<0> ADDR_DEC<0> VDD VSS / RSC_IHPSG13_INVX2 +XI16<3> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI16<2> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI16<1> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI17<2> VDD VSS / RSC_IHPSG13_FILLCAP4 +XI17<1> VDD VSS / RSC_IHPSG13_FILLCAP4 +.ENDS +.SUBCKT RSC_IHPSG13_AND2X4 A B Z VDD VSS +MN3 Z net6 VSS VSS sg13_lv_nmos m=1 w=1.96u l=130.00n ng=2 nrd=0 nrs=0 +MN4 net9 B VSS VSS sg13_lv_nmos m=1 w=500.0n l=130.00n ng=1 nrd=0 nrs=0 +MN6 net6 A net9 VSS sg13_lv_nmos m=1 w=500.0n l=130.00n ng=1 nrd=0 nrs=0 +MP2 Z net6 VDD VDD sg13_lv_pmos m=1 w=3.24u l=130.00n ng=2 nrd=0 nrs=0 +MP0 net6 B VDD VDD sg13_lv_pmos m=1 w=860.00n l=130.00n ng=1 nrd=0 ++ nrs=0 +MP1 net6 A VDD VDD sg13_lv_pmos m=1 w=860.00n l=130.00n ng=1 nrd=0 ++ nrs=0 +.ENDS +.SUBCKT RM_IHPSG13_256x8_c3_1P_COLCTRL4 A_ADDR_COL A_ADDR_DEC<7> A_ADDR_DEC<6> ++ A_ADDR_DEC<5> A_ADDR_DEC<4> A_ADDR_DEC<3> A_ADDR_DEC<2> A_ADDR_DEC<1> ++ A_ADDR_DEC<0> A_BIST_BM_I A_BIST_DW_I A_BIST_EN_I A_BLC<15> A_BLC<14> ++ A_BLC<13> A_BLC<12> A_BLC<11> A_BLC<10> A_BLC<9> A_BLC<8> A_BLC<7> A_BLC<6> ++ A_BLC<5> A_BLC<4> A_BLC<3> A_BLC<2> A_BLC<1> A_BLC<0> A_BLT<15> A_BLT<14> ++ A_BLT<13> A_BLT<12> A_BLT<11> A_BLT<10> A_BLT<9> A_BLT<8> A_BLT<7> A_BLT<6> ++ A_BLT<5> A_BLT<4> A_BLT<3> A_BLT<2> A_BLT<1> A_BLT<0> A_BM_I A_DCLK_B_L ++ A_DCLK_B_R A_DCLK_L A_DCLK_R A_DR_O A_DW_I A_RCLK_B_L A_RCLK_B_R A_RCLK_L ++ A_RCLK_R A_TIEH_O A_WCLK_B_L A_WCLK_B_R A_WCLK_L A_WCLK_R VDD VSS +XA_I80 A_WCLK_B_L A_RCLK_B_L net21 VDD VSS / RSC_IHPSG13_AND2X2 +XA_I76 A_DO_WRITE_P A_DI_N A_WR_ZERO VDD VSS / RSC_IHPSG13_AND2X4 +XA_I75 A_DI_R A_DO_WRITE_P A_WR_ONE VDD VSS / RSC_IHPSG13_AND2X4 +XA_CAPS<8> VDD VSS / RSC_IHPSG13_FILLCAP4 +XA_CAPS<7> VDD VSS / RSC_IHPSG13_FILLCAP4 +XA_CAPS<6> VDD VSS / RSC_IHPSG13_FILLCAP4 +XA_CAPS<5> VDD VSS / RSC_IHPSG13_FILLCAP4 +XA_CAPS<4> VDD VSS / RSC_IHPSG13_FILLCAP4 +XA_CAPS<3> VDD VSS / RSC_IHPSG13_FILLCAP4 +XA_CAPS<2> VDD VSS / RSC_IHPSG13_FILLCAP4 +XA_CAPS<1> VDD VSS / RSC_IHPSG13_FILLCAP4 +XA_I69 A_DCLK_L A_DCLK_B_L VDD VSS / RSC_IHPSG13_CINVX4 +XA_I50 A_WCLK_L A_WCLK_B_L VDD VSS / RSC_IHPSG13_CINVX4 +XA_EBUF A_RCLK_L A_RCLK_B_L VDD VSS / RSC_IHPSG13_CINVX4 +XA_INV<1> A_N0 A_P0 VDD VSS / RSC_IHPSG13_CINVX4 +XA_INV<0> A_ADDR_COL A_N0 VDD VSS / RSC_IHPSG13_CINVX4 +XA_I81<1> net21 A_PRE_N VDD VSS / RSC_IHPSG13_CINVX4_WN +XA_I81<0> net21 A_PRE_N VDD VSS / RSC_IHPSG13_CINVX4_WN +XA_BLTMUX<15> A_BLC<15> A_BLC_SEL A_BLT<15> A_BLT_SEL A_PRE_N A_SEL_P<15> ++ A_WR_ONE A_WR_ZERO VDD VSS / RM_IHPSG13_256x8_c3_1P_BLDRV +XA_BLTMUX<14> A_BLC<14> A_BLC_SEL A_BLT<14> A_BLT_SEL A_PRE_N A_SEL_P<14> ++ A_WR_ONE A_WR_ZERO VDD VSS / RM_IHPSG13_256x8_c3_1P_BLDRV +XA_BLTMUX<13> A_BLC<13> A_BLC_SEL A_BLT<13> A_BLT_SEL A_PRE_N A_SEL_P<13> ++ A_WR_ONE A_WR_ZERO VDD VSS / RM_IHPSG13_256x8_c3_1P_BLDRV +XA_BLTMUX<12> A_BLC<12> A_BLC_SEL A_BLT<12> A_BLT_SEL A_PRE_N A_SEL_P<12> ++ A_WR_ONE A_WR_ZERO VDD VSS / RM_IHPSG13_256x8_c3_1P_BLDRV +XA_BLTMUX<11> A_BLC<11> A_BLC_SEL A_BLT<11> A_BLT_SEL A_PRE_N A_SEL_P<11> ++ A_WR_ONE A_WR_ZERO VDD VSS / RM_IHPSG13_256x8_c3_1P_BLDRV +XA_BLTMUX<10> A_BLC<10> A_BLC_SEL A_BLT<10> A_BLT_SEL A_PRE_N A_SEL_P<10> ++ A_WR_ONE A_WR_ZERO VDD VSS / RM_IHPSG13_256x8_c3_1P_BLDRV +XA_BLTMUX<9> A_BLC<9> A_BLC_SEL A_BLT<9> A_BLT_SEL A_PRE_N A_SEL_P<9> A_WR_ONE ++ A_WR_ZERO VDD VSS / RM_IHPSG13_256x8_c3_1P_BLDRV +XA_BLTMUX<8> A_BLC<8> A_BLC_SEL A_BLT<8> A_BLT_SEL A_PRE_N A_SEL_P<8> A_WR_ONE ++ A_WR_ZERO VDD VSS / RM_IHPSG13_256x8_c3_1P_BLDRV +XA_BLTMUX<7> A_BLC<7> A_BLC_SEL A_BLT<7> A_BLT_SEL A_PRE_N A_SEL_P<7> A_WR_ONE ++ A_WR_ZERO VDD VSS / RM_IHPSG13_256x8_c3_1P_BLDRV +XA_BLTMUX<6> A_BLC<6> A_BLC_SEL A_BLT<6> A_BLT_SEL A_PRE_N A_SEL_P<6> A_WR_ONE ++ A_WR_ZERO VDD VSS / RM_IHPSG13_256x8_c3_1P_BLDRV +XA_BLTMUX<5> A_BLC<5> A_BLC_SEL A_BLT<5> A_BLT_SEL A_PRE_N A_SEL_P<5> A_WR_ONE ++ A_WR_ZERO VDD VSS / RM_IHPSG13_256x8_c3_1P_BLDRV +XA_BLTMUX<4> A_BLC<4> A_BLC_SEL A_BLT<4> A_BLT_SEL A_PRE_N A_SEL_P<4> A_WR_ONE ++ A_WR_ZERO VDD VSS / RM_IHPSG13_256x8_c3_1P_BLDRV +XA_BLTMUX<3> A_BLC<3> A_BLC_SEL A_BLT<3> A_BLT_SEL A_PRE_N A_SEL_P<3> A_WR_ONE ++ A_WR_ZERO VDD VSS / RM_IHPSG13_256x8_c3_1P_BLDRV +XA_BLTMUX<2> A_BLC<2> A_BLC_SEL A_BLT<2> A_BLT_SEL A_PRE_N A_SEL_P<2> A_WR_ONE ++ A_WR_ZERO VDD VSS / RM_IHPSG13_256x8_c3_1P_BLDRV +XA_BLTMUX<1> A_BLC<1> A_BLC_SEL A_BLT<1> A_BLT_SEL A_PRE_N A_SEL_P<1> A_WR_ONE ++ A_WR_ZERO VDD VSS / RM_IHPSG13_256x8_c3_1P_BLDRV +XA_BLTMUX<0> A_BLC<0> A_BLC_SEL A_BLT<0> A_BLT_SEL A_PRE_N A_SEL_P<0> A_WR_ONE ++ A_WR_ZERO VDD VSS / RM_IHPSG13_256x8_c3_1P_BLDRV +XA_R2 A_RCLK_L A_RCLK_R / RSC_IHPSG13_MET3RES +XA_I87 A_WCLK_L A_WCLK_R / RSC_IHPSG13_MET3RES +XA_I88 A_DCLK_L A_DCLK_R / RSC_IHPSG13_MET3RES +XA_I89 A_DCLK_B_L A_DCLK_B_R / RSC_IHPSG13_MET3RES +XA_I90 A_WCLK_B_L A_WCLK_B_R / RSC_IHPSG13_MET3RES +XA_I91 A_RCLK_B_L A_RCLK_B_R / RSC_IHPSG13_MET3RES +XA_ISENSE A_SAE A_BLC_SEL A_BLT_SEL net19 net20 VDD VSS / ++ RSC_IHPSG13_DFPQD_MSAFFX2 +XA_I51 net19 A_DR_O VDD VSS / RSC_IHPSG13_INVX4 +XA_I78 A_RCLK_B_L A_SAE VDD VSS / RSC_IHPSG13_CBUFX2 +XA_DREG A_BIST_EN_I A_BIST_DW_I A_DCLK_B_L A_DW_I A_DI_R net22 VDD VSS ++ / RSC_IHPSG13_DFNQMX2IX1 +XA_BREG A_BIST_EN_I A_BIST_BM_I A_DCLK_B_L A_BM_I A_BM_R net24 VDD VSS ++ / RSC_IHPSG13_DFNQMX2IX1 +XA_DEC3INV<15> net23<0> A_SEL_P<15> VDD VSS / RSC_IHPSG13_INVX2 +XA_DEC3INV<14> net23<1> A_SEL_P<14> VDD VSS / RSC_IHPSG13_INVX2 +XA_DEC3INV<13> net23<2> A_SEL_P<13> VDD VSS / RSC_IHPSG13_INVX2 +XA_DEC3INV<12> net23<3> A_SEL_P<12> VDD VSS / RSC_IHPSG13_INVX2 +XA_DEC3INV<11> net23<4> A_SEL_P<11> VDD VSS / RSC_IHPSG13_INVX2 +XA_DEC3INV<10> net23<5> A_SEL_P<10> VDD VSS / RSC_IHPSG13_INVX2 +XA_DEC3INV<9> net23<6> A_SEL_P<9> VDD VSS / RSC_IHPSG13_INVX2 +XA_DEC3INV<8> net23<7> A_SEL_P<8> VDD VSS / RSC_IHPSG13_INVX2 +XA_DEC3INV<7> net23<8> A_SEL_P<7> VDD VSS / RSC_IHPSG13_INVX2 +XA_DEC3INV<6> net23<9> A_SEL_P<6> VDD VSS / RSC_IHPSG13_INVX2 +XA_DEC3INV<5> net23<10> A_SEL_P<5> VDD VSS / RSC_IHPSG13_INVX2 +XA_DEC3INV<4> net23<11> A_SEL_P<4> VDD VSS / RSC_IHPSG13_INVX2 +XA_DEC3INV<3> net23<12> A_SEL_P<3> VDD VSS / RSC_IHPSG13_INVX2 +XA_DEC3INV<2> net23<13> A_SEL_P<2> VDD VSS / RSC_IHPSG13_INVX2 +XA_DEC3INV<1> net23<14> A_SEL_P<1> VDD VSS / RSC_IHPSG13_INVX2 +XA_DEC3INV<0> net23<15> A_SEL_P<0> VDD VSS / RSC_IHPSG13_INVX2 +XA_I83 A_BM_R A_BM_N VDD VSS / RSC_IHPSG13_INVX2 +XA_I49 A_DI_R A_DI_N VDD VSS / RSC_IHPSG13_INVX2 +XA_I70<4> VDD VSS / RSC_IHPSG13_FILLCAP8 +XA_I70<3> VDD VSS / RSC_IHPSG13_FILLCAP8 +XA_I70<2> VDD VSS / RSC_IHPSG13_FILLCAP8 +XA_I70<1> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI73<14> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI73<13> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI73<12> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI73<11> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI73<10> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI73<9> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI73<8> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI73<7> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI73<6> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI73<5> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI73<4> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI73<3> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI73<2> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI73<1> VDD VSS / RSC_IHPSG13_FILLCAP8 +XA_I44 A_BM_N A_WCLK_B_L A_DO_WRITE_P VDD VSS / RSC_IHPSG13_NOR2X2 +XA_DEC3<15> A_P0 A_ADDR_DEC<7> net23<0> VDD VSS / RSC_IHPSG13_NAND2X2 +XA_DEC3<14> A_P0 A_ADDR_DEC<6> net23<1> VDD VSS / RSC_IHPSG13_NAND2X2 +XA_DEC3<13> A_P0 A_ADDR_DEC<5> net23<2> VDD VSS / RSC_IHPSG13_NAND2X2 +XA_DEC3<12> A_P0 A_ADDR_DEC<4> net23<3> VDD VSS / RSC_IHPSG13_NAND2X2 +XA_DEC3<11> A_P0 A_ADDR_DEC<3> net23<4> VDD VSS / RSC_IHPSG13_NAND2X2 +XA_DEC3<10> A_P0 A_ADDR_DEC<2> net23<5> VDD VSS / RSC_IHPSG13_NAND2X2 +XA_DEC3<9> A_P0 A_ADDR_DEC<1> net23<6> VDD VSS / RSC_IHPSG13_NAND2X2 +XA_DEC3<8> A_P0 A_ADDR_DEC<0> net23<7> VDD VSS / RSC_IHPSG13_NAND2X2 +XA_DEC3<7> A_N0 A_ADDR_DEC<7> net23<8> VDD VSS / RSC_IHPSG13_NAND2X2 +XA_DEC3<6> A_N0 A_ADDR_DEC<6> net23<9> VDD VSS / RSC_IHPSG13_NAND2X2 +XA_DEC3<5> A_N0 A_ADDR_DEC<5> net23<10> VDD VSS / RSC_IHPSG13_NAND2X2 +XA_DEC3<4> A_N0 A_ADDR_DEC<4> net23<11> VDD VSS / RSC_IHPSG13_NAND2X2 +XA_DEC3<3> A_N0 A_ADDR_DEC<3> net23<12> VDD VSS / RSC_IHPSG13_NAND2X2 +XA_DEC3<2> A_N0 A_ADDR_DEC<2> net23<13> VDD VSS / RSC_IHPSG13_NAND2X2 +XA_DEC3<1> A_N0 A_ADDR_DEC<1> net23<14> VDD VSS / RSC_IHPSG13_NAND2X2 +XA_DEC3<0> A_N0 A_ADDR_DEC<0> net23<15> VDD VSS / RSC_IHPSG13_NAND2X2 +XA_BM_TIEH A_TIEH_O VDD VSS / RSC_IHPSG13_TIEH +.ENDS + + +.SUBCKT RM_IHPSG13_256x8_c3_1P_COLDEC3 ACLK_N ADDR<2> ADDR<1> ADDR<0> ADDR_COL<1> ++ ADDR_COL<0> ADDR_DEC<7> ADDR_DEC<6> ADDR_DEC<5> ADDR_DEC<4> ADDR_DEC<3> ++ ADDR_DEC<2> ADDR_DEC<1> ADDR_DEC<0> BIST_ADDR<2> BIST_ADDR<1> BIST_ADDR<0> ++ BIST_EN_I VDD VSS +XI15<1> ADDR_COL<1> VDD VSS / RSC_IHPSG13_TIEL +XI15<0> ADDR_COL<0> VDD VSS / RSC_IHPSG13_TIEL +XI1<7> PADR<0> PADR<1> PADR<2> addr_n<7> VDD VSS / RSC_IHPSG13_NAND3X2 +XI1<6> NADR<0> PADR<1> PADR<2> addr_n<6> VDD VSS / RSC_IHPSG13_NAND3X2 +XI1<5> PADR<0> NADR<1> PADR<2> addr_n<5> VDD VSS / RSC_IHPSG13_NAND3X2 +XI1<4> NADR<0> NADR<1> PADR<2> addr_n<4> VDD VSS / RSC_IHPSG13_NAND3X2 +XI1<3> PADR<0> PADR<1> NADR<2> addr_n<3> VDD VSS / RSC_IHPSG13_NAND3X2 +XI1<2> NADR<0> PADR<1> NADR<2> addr_n<2> VDD VSS / RSC_IHPSG13_NAND3X2 +XI1<1> PADR<0> NADR<1> NADR<2> addr_n<1> VDD VSS / RSC_IHPSG13_NAND3X2 +XI1<0> NADR<0> NADR<1> NADR<2> addr_n<0> VDD VSS / RSC_IHPSG13_NAND3X2 +XDFF<2> BIST_EN_I BIST_ADDR<2> ACLK_N ADDR<2> padr_int<2> net6<0> VDD ++ VSS / RSC_IHPSG13_DFNQMX2IX1 +XDFF<1> BIST_EN_I BIST_ADDR<1> ACLK_N ADDR<1> padr_int<1> net6<1> VDD ++ VSS / RSC_IHPSG13_DFNQMX2IX1 +XDFF<0> BIST_EN_I BIST_ADDR<0> ACLK_N ADDR<0> padr_int<0> net6<2> VDD ++ VSS / RSC_IHPSG13_DFNQMX2IX1 +XI17<2> VDD VSS / RSC_IHPSG13_FILLCAP4 +XI17<1> VDD VSS / RSC_IHPSG13_FILLCAP4 +XI13<2> NADR<2> PADR<2> VDD VSS / RSC_IHPSG13_INVX2 +XI13<1> NADR<1> PADR<1> VDD VSS / RSC_IHPSG13_INVX2 +XI13<0> NADR<0> PADR<0> VDD VSS / RSC_IHPSG13_INVX2 +XI3<2> padr_int<2> NADR<2> VDD VSS / RSC_IHPSG13_INVX2 +XI3<1> padr_int<1> NADR<1> VDD VSS / RSC_IHPSG13_INVX2 +XI3<0> padr_int<0> NADR<0> VDD VSS / RSC_IHPSG13_INVX2 +XI2<7> addr_n<7> ADDR_DEC<7> VDD VSS / RSC_IHPSG13_INVX2 +XI2<6> addr_n<6> ADDR_DEC<6> VDD VSS / RSC_IHPSG13_INVX2 +XI2<5> addr_n<5> ADDR_DEC<5> VDD VSS / RSC_IHPSG13_INVX2 +XI2<4> addr_n<4> ADDR_DEC<4> VDD VSS / RSC_IHPSG13_INVX2 +XI2<3> addr_n<3> ADDR_DEC<3> VDD VSS / RSC_IHPSG13_INVX2 +XI2<2> addr_n<2> ADDR_DEC<2> VDD VSS / RSC_IHPSG13_INVX2 +XI2<1> addr_n<1> ADDR_DEC<1> VDD VSS / RSC_IHPSG13_INVX2 +XI2<0> addr_n<0> ADDR_DEC<0> VDD VSS / RSC_IHPSG13_INVX2 +XI16<6> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI16<5> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI16<4> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI16<3> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI16<2> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI16<1> VDD VSS / RSC_IHPSG13_FILLCAP8 +.ENDS +.SUBCKT RM_IHPSG13_256x8_c3_1P_COLCTRL3 A_ADDR_DEC<7> A_ADDR_DEC<6> A_ADDR_DEC<5> ++ A_ADDR_DEC<4> A_ADDR_DEC<3> A_ADDR_DEC<2> A_ADDR_DEC<1> A_ADDR_DEC<0> ++ A_BIST_BM_I A_BIST_DW_I A_BIST_EN_I A_BLC<7> A_BLC<6> A_BLC<5> A_BLC<4> ++ A_BLC<3> A_BLC<2> A_BLC<1> A_BLC<0> A_BLT<7> A_BLT<6> A_BLT<5> A_BLT<4> ++ A_BLT<3> A_BLT<2> A_BLT<1> A_BLT<0> A_BM_I A_DCLK_B_L A_DCLK_B_R A_DCLK_L ++ A_DCLK_R A_DR_O A_DW_I A_RCLK_B_L A_RCLK_B_R A_RCLK_L A_RCLK_R A_TIEH_O ++ A_WCLK_B_L A_WCLK_B_R A_WCLK_L A_WCLK_R VDD VSS +XA_DREG A_BIST_EN_I A_BIST_DW_I A_DCLK_B_L A_DW_I A_DI_R net22 VDD VSS ++ / RSC_IHPSG13_DFNQMX2IX1 +XA_BREG A_BIST_EN_I A_BIST_BM_I A_DCLK_B_R A_BM_I A_BM_R net23 VDD VSS ++ / RSC_IHPSG13_DFNQMX2IX1 +XA_I70<8> VDD VSS / RSC_IHPSG13_FILLCAP8 +XA_I70<7> VDD VSS / RSC_IHPSG13_FILLCAP8 +XA_I70<6> VDD VSS / RSC_IHPSG13_FILLCAP8 +XA_I70<5> VDD VSS / RSC_IHPSG13_FILLCAP8 +XA_I70<4> VDD VSS / RSC_IHPSG13_FILLCAP8 +XA_I70<3> VDD VSS / RSC_IHPSG13_FILLCAP8 +XA_I70<2> VDD VSS / RSC_IHPSG13_FILLCAP8 +XA_I70<1> VDD VSS / RSC_IHPSG13_FILLCAP8 +XA_I51 net19 A_DR_O VDD VSS / RSC_IHPSG13_INVX4 +XA_I44 A_BM_N A_WCLK_B_R A_DO_WRITE_P VDD VSS / RSC_IHPSG13_NOR2X2 +XA_BM_TIEH A_TIEH_O VDD VSS / RSC_IHPSG13_TIEH +XA_BLTMUX<7> A_BLC<7> A_BLC_SEL A_BLT<7> A_BLT_SEL A_PRE_N A_ADDR_DEC<7> ++ A_WR_ONE A_WR_ZERO VDD VSS / RM_IHPSG13_256x8_c3_1P_BLDRV +XA_BLTMUX<6> A_BLC<6> A_BLC_SEL A_BLT<6> A_BLT_SEL A_PRE_N A_ADDR_DEC<6> ++ A_WR_ONE A_WR_ZERO VDD VSS / RM_IHPSG13_256x8_c3_1P_BLDRV +XA_BLTMUX<5> A_BLC<5> A_BLC_SEL A_BLT<5> A_BLT_SEL A_PRE_N A_ADDR_DEC<5> ++ A_WR_ONE A_WR_ZERO VDD VSS / RM_IHPSG13_256x8_c3_1P_BLDRV +XA_BLTMUX<4> A_BLC<4> A_BLC_SEL A_BLT<4> A_BLT_SEL A_PRE_N A_ADDR_DEC<4> ++ A_WR_ONE A_WR_ZERO VDD VSS / RM_IHPSG13_256x8_c3_1P_BLDRV +XA_BLTMUX<3> A_BLC<3> A_BLC_SEL A_BLT<3> A_BLT_SEL A_PRE_N A_ADDR_DEC<3> ++ A_WR_ONE A_WR_ZERO VDD VSS / RM_IHPSG13_256x8_c3_1P_BLDRV +XA_BLTMUX<2> A_BLC<2> A_BLC_SEL A_BLT<2> A_BLT_SEL A_PRE_N A_ADDR_DEC<2> ++ A_WR_ONE A_WR_ZERO VDD VSS / RM_IHPSG13_256x8_c3_1P_BLDRV +XA_BLTMUX<1> A_BLC<1> A_BLC_SEL A_BLT<1> A_BLT_SEL A_PRE_N A_ADDR_DEC<1> ++ A_WR_ONE A_WR_ZERO VDD VSS / RM_IHPSG13_256x8_c3_1P_BLDRV +XA_BLTMUX<0> A_BLC<0> A_BLC_SEL A_BLT<0> A_BLT_SEL A_PRE_N A_ADDR_DEC<0> ++ A_WR_ONE A_WR_ZERO VDD VSS / RM_IHPSG13_256x8_c3_1P_BLDRV +XA_I49 A_DI_R A_DI_N VDD VSS / RSC_IHPSG13_INVX2 +XA_I83 A_BM_R A_BM_N VDD VSS / RSC_IHPSG13_INVX2 +XA_I69 A_DCLK_L A_DCLK_B_L VDD VSS / RSC_IHPSG13_CINVX2 +XA_I50 A_WCLK_L A_WCLK_B_L VDD VSS / RSC_IHPSG13_CINVX2 +XA_EBUF A_RCLK_L A_RCLK_B_L VDD VSS / RSC_IHPSG13_CINVX2 +XA_I78 A_RCLK_B_L A_SAE VDD VSS / RSC_IHPSG13_CBUFX2 +XA_I88 A_DCLK_L A_DCLK_R / RSC_IHPSG13_MET3RES +XA_I87 A_WCLK_L A_WCLK_R / RSC_IHPSG13_MET3RES +XA_R2 A_RCLK_L A_RCLK_R / RSC_IHPSG13_MET3RES +XA_I91 A_RCLK_B_L A_RCLK_B_R / RSC_IHPSG13_MET3RES +XA_I90 A_WCLK_B_L A_WCLK_B_R / RSC_IHPSG13_MET3RES +XA_I89 A_DCLK_B_L A_DCLK_B_R / RSC_IHPSG13_MET3RES +XA_I80 A_WCLK_B_R A_RCLK_B_R net21 VDD VSS / RSC_IHPSG13_AND2X2 +XA_I76 A_DI_N A_DO_WRITE_P A_WR_ZERO VDD VSS / RSC_IHPSG13_AND2X2 +XA_I75 A_DI_R A_DO_WRITE_P A_WR_ONE VDD VSS / RSC_IHPSG13_AND2X2 +XA_ISENSE A_SAE A_BLC_SEL A_BLT_SEL net19 net20 VDD VSS / ++ RSC_IHPSG13_DFPQD_MSAFFX2 +XA_I81 net21 A_PRE_N VDD VSS / RSC_IHPSG13_CINVX4_WN +XA_CAPS<5> VDD VSS / RSC_IHPSG13_FILLCAP4 +XA_CAPS<4> VDD VSS / RSC_IHPSG13_FILLCAP4 +XA_CAPS<3> VDD VSS / RSC_IHPSG13_FILLCAP4 +XA_CAPS<2> VDD VSS / RSC_IHPSG13_FILLCAP4 +XA_CAPS<1> VDD VSS / RSC_IHPSG13_FILLCAP4 +.ENDS + +.SUBCKT RM_IHPSG13_256x8_c3_2P_BITKIT_16x2_CORNER VDD_CORE VSS +XI16 VDD_CORE VSS VDD_CORE VSS / ++ RM_IHPSG13_256x8_c3_1P_BITKIT_CORNER +.ENDS +.SUBCKT RM_IHPSG13_256x8_c3_2P_BITKIT_EDGE_LR A_WL B_WL NW PW VDD VSS +MN1 VSS A_WL VSS VSS sg13_lv_nmos m=1 w=300.0n l=130.00n ng=1 nrd=0 nrs=0 +MN0 VSS B_WL VSS VSS sg13_lv_nmos m=1 w=300.0n l=130.00n ng=1 nrd=0 nrs=0 +.ENDS +.SUBCKT RM_IHPSG13_256x8_c3_2P_BITKIT_16x2_EDGE_LR A_WL<15> A_WL<14> A_WL<13> A_WL<12> ++ A_WL<11> A_WL<10> A_WL<9> A_WL<8> A_WL<7> A_WL<6> A_WL<5> A_WL<4> A_WL<3> ++ A_WL<2> A_WL<1> A_WL<0> B_WL<15> B_WL<14> B_WL<13> B_WL<12> B_WL<11> ++ B_WL<10> B_WL<9> B_WL<8> B_WL<7> B_WL<6> B_WL<5> B_WL<4> B_WL<3> B_WL<2> ++ B_WL<1> B_WL<0> VDD_CORE VSS +XI0<15> A_WL<15> B_WL<15> VDD_CORE VSS VDD_CORE VSS ++ / RM_IHPSG13_256x8_c3_2P_BITKIT_EDGE_LR +XI0<14> A_WL<14> B_WL<14> VDD_CORE VSS VDD_CORE VSS ++ / RM_IHPSG13_256x8_c3_2P_BITKIT_EDGE_LR +XI0<13> A_WL<13> B_WL<13> VDD_CORE VSS VDD_CORE VSS ++ / RM_IHPSG13_256x8_c3_2P_BITKIT_EDGE_LR +XI0<12> A_WL<12> B_WL<12> VDD_CORE VSS VDD_CORE VSS ++ / RM_IHPSG13_256x8_c3_2P_BITKIT_EDGE_LR +XI0<11> A_WL<11> B_WL<11> VDD_CORE VSS VDD_CORE VSS ++ / RM_IHPSG13_256x8_c3_2P_BITKIT_EDGE_LR +XI0<10> A_WL<10> B_WL<10> VDD_CORE VSS VDD_CORE VSS ++ / RM_IHPSG13_256x8_c3_2P_BITKIT_EDGE_LR +XI0<9> A_WL<9> B_WL<9> VDD_CORE VSS VDD_CORE VSS / ++ RM_IHPSG13_256x8_c3_2P_BITKIT_EDGE_LR +XI0<8> A_WL<8> B_WL<8> VDD_CORE VSS VDD_CORE VSS / ++ RM_IHPSG13_256x8_c3_2P_BITKIT_EDGE_LR +XI0<7> A_WL<7> B_WL<7> VDD_CORE VSS VDD_CORE VSS / ++ RM_IHPSG13_256x8_c3_2P_BITKIT_EDGE_LR +XI0<6> A_WL<6> B_WL<6> VDD_CORE VSS VDD_CORE VSS / ++ RM_IHPSG13_256x8_c3_2P_BITKIT_EDGE_LR +XI0<5> A_WL<5> B_WL<5> VDD_CORE VSS VDD_CORE VSS / ++ RM_IHPSG13_256x8_c3_2P_BITKIT_EDGE_LR +XI0<4> A_WL<4> B_WL<4> VDD_CORE VSS VDD_CORE VSS / ++ RM_IHPSG13_256x8_c3_2P_BITKIT_EDGE_LR +XI0<3> A_WL<3> B_WL<3> VDD_CORE VSS VDD_CORE VSS / ++ RM_IHPSG13_256x8_c3_2P_BITKIT_EDGE_LR +XI0<2> A_WL<2> B_WL<2> VDD_CORE VSS VDD_CORE VSS / ++ RM_IHPSG13_256x8_c3_2P_BITKIT_EDGE_LR +XI0<1> A_WL<1> B_WL<1> VDD_CORE VSS VDD_CORE VSS / ++ RM_IHPSG13_256x8_c3_2P_BITKIT_EDGE_LR +XI0<0> A_WL<0> B_WL<0> VDD_CORE VSS VDD_CORE VSS / ++ RM_IHPSG13_256x8_c3_2P_BITKIT_EDGE_LR +.ENDS +.SUBCKT RM_IHPSG13_256x8_c3_2P_BITKIT_CELL A_BLC_BOT A_BLC_TOP A_BLT_BOT A_BLT_TOP ++ A_LWL A_RWL B_BLC_BOT B_BLC_TOP B_BLT_BOT B_BLT_TOP B_LWL B_RWL NW PW VDD VSS +MN5 NC B_RWL B_BLC_BOT PW sg13_lv_nmos m=1 w=300.0n l=130.00n ng=1 nrd=0 nrs=0 +MN4 B_BLT_BOT B_LWL NT PW sg13_lv_nmos m=1 w=300.0n l=130.00n ng=1 nrd=0 nrs=0 +MN0 NC NT VSS PW sg13_lv_nmos m=1 w=600.0n l=130.00n ng=2 nrd=0 nrs=0 +MN1 NT NC VSS PW sg13_lv_nmos m=1 w=600.0n l=130.00n ng=2 nrd=0 nrs=0 +MN3 NC A_RWL A_BLC_TOP PW sg13_lv_nmos m=1 w=300.0n l=130.00n ng=1 nrd=0 nrs=0 +MN2 A_BLT_TOP A_LWL NT PW sg13_lv_nmos m=1 w=300.0n l=130.00n ng=1 nrd=0 nrs=0 +MP1 NT NC VDD NW sg13_lv_pmos m=1 w=150.00n l=130.00n ng=1 nrd=0 nrs=0 +MP0 NC NT VDD NW sg13_lv_pmos m=1 w=150.00n l=130.00n ng=1 nrd=0 nrs=0 +R5 B_RWL B_LWL lvsres w=2.6e-07 l=6e-07 +R4 B_BLC_BOT B_BLC_TOP lvsres w=2.6e-07 l=6e-07 +R3 B_BLT_BOT B_BLT_TOP lvsres w=2.6e-07 l=6e-07 +R1 A_BLC_BOT A_BLC_TOP lvsres w=2.6e-07 l=6e-07 +R0 A_BLT_BOT A_BLT_TOP lvsres w=2.6e-07 l=6e-07 +R2 A_RWL A_LWL lvsres w=2.6e-07 l=6e-07 +.ENDS +.SUBCKT RM_IHPSG13_256x8_c3_2P_BITKIT_16x2_SRAM A_BLC_BOT<1> A_BLC_BOT<0> A_BLC_TOP<1> ++ A_BLC_TOP<0> A_BLT_BOT<1> A_BLT_BOT<0> A_BLT_TOP<1> A_BLT_TOP<0> A_LWL<15> ++ A_LWL<14> A_LWL<13> A_LWL<12> A_LWL<11> A_LWL<10> A_LWL<9> A_LWL<8> A_LWL<7> ++ A_LWL<6> A_LWL<5> A_LWL<4> A_LWL<3> A_LWL<2> A_LWL<1> A_LWL<0> A_RWL<15> ++ A_RWL<14> A_RWL<13> A_RWL<12> A_RWL<11> A_RWL<10> A_RWL<9> A_RWL<8> A_RWL<7> ++ A_RWL<6> A_RWL<5> A_RWL<4> A_RWL<3> A_RWL<2> A_RWL<1> A_RWL<0> B_BLC_BOT<1> ++ B_BLC_BOT<0> B_BLC_TOP<1> B_BLC_TOP<0> B_BLT_BOT<1> B_BLT_BOT<0> ++ B_BLT_TOP<1> B_BLT_TOP<0> B_LWL<15> B_LWL<14> B_LWL<13> B_LWL<12> B_LWL<11> ++ B_LWL<10> B_LWL<9> B_LWL<8> B_LWL<7> B_LWL<6> B_LWL<5> B_LWL<4> B_LWL<3> ++ B_LWL<2> B_LWL<1> B_LWL<0> B_RWL<15> B_RWL<14> B_RWL<13> B_RWL<12> B_RWL<11> ++ B_RWL<10> B_RWL<9> B_RWL<8> B_RWL<7> B_RWL<6> B_RWL<5> B_RWL<4> B_RWL<3> ++ B_RWL<2> B_RWL<1> B_RWL<0> VDD_CORE VSS +XCELL<31> A_BLC_TOP<1> A_RBLC<15> A_BLT_TOP<1> A_RBLT<15> A_XWL<15> A_RWL<15> ++ B_BLC_TOP<1> B_RBLC<15> B_BLT_TOP<1> B_RBLT<15> B_XWL<15> B_RWL<15> ++ VDD_CORE VSS VDD_CORE VSS / ++ RM_IHPSG13_256x8_c3_2P_BITKIT_CELL +XCELL<30> A_RBLC<14> A_RBLC<15> A_RBLT<14> A_RBLT<15> A_XWL<14> A_RWL<14> ++ B_RBLC<14> B_RBLC<15> B_RBLT<14> B_RBLT<15> B_XWL<14> B_RWL<14> VDD_CORE ++ VSS VDD_CORE VSS / RM_IHPSG13_256x8_c3_2P_BITKIT_CELL +XCELL<29> A_RBLC<14> A_RBLC<13> A_RBLT<14> A_RBLT<13> A_XWL<13> A_RWL<13> ++ B_RBLC<14> B_RBLC<13> B_RBLT<14> B_RBLT<13> B_XWL<13> B_RWL<13> VDD_CORE ++ VSS VDD_CORE VSS / RM_IHPSG13_256x8_c3_2P_BITKIT_CELL +XCELL<28> A_RBLC<12> A_RBLC<13> A_RBLT<12> A_RBLT<13> A_XWL<12> A_RWL<12> ++ B_RBLC<12> B_RBLC<13> B_RBLT<12> B_RBLT<13> B_XWL<12> B_RWL<12> VDD_CORE ++ VSS VDD_CORE VSS / RM_IHPSG13_256x8_c3_2P_BITKIT_CELL +XCELL<27> A_RBLC<12> A_RBLC<11> A_RBLT<12> A_RBLT<11> A_XWL<11> A_RWL<11> ++ B_RBLC<12> B_RBLC<11> B_RBLT<12> B_RBLT<11> B_XWL<11> B_RWL<11> VDD_CORE ++ VSS VDD_CORE VSS / RM_IHPSG13_256x8_c3_2P_BITKIT_CELL +XCELL<26> A_RBLC<10> A_RBLC<11> A_RBLT<10> A_RBLT<11> A_XWL<10> A_RWL<10> ++ B_RBLC<10> B_RBLC<11> B_RBLT<10> B_RBLT<11> B_XWL<10> B_RWL<10> VDD_CORE ++ VSS VDD_CORE VSS / RM_IHPSG13_256x8_c3_2P_BITKIT_CELL +XCELL<25> A_RBLC<10> A_RBLC<9> A_RBLT<10> A_RBLT<9> A_XWL<9> A_RWL<9> ++ B_RBLC<10> B_RBLC<9> B_RBLT<10> B_RBLT<9> B_XWL<9> B_RWL<9> VDD_CORE ++ VSS VDD_CORE VSS / RM_IHPSG13_256x8_c3_2P_BITKIT_CELL +XCELL<24> A_RBLC<8> A_RBLC<9> A_RBLT<8> A_RBLT<9> A_XWL<8> A_RWL<8> B_RBLC<8> ++ B_RBLC<9> B_RBLT<8> B_RBLT<9> B_XWL<8> B_RWL<8> VDD_CORE VSS ++ VDD_CORE VSS / RM_IHPSG13_256x8_c3_2P_BITKIT_CELL +XCELL<23> A_RBLC<8> A_RBLC<7> A_RBLT<8> A_RBLT<7> A_XWL<7> A_RWL<7> B_RBLC<8> ++ B_RBLC<7> B_RBLT<8> B_RBLT<7> B_XWL<7> B_RWL<7> VDD_CORE VSS ++ VDD_CORE VSS / RM_IHPSG13_256x8_c3_2P_BITKIT_CELL +XCELL<22> A_RBLC<6> A_RBLC<7> A_RBLT<6> A_RBLT<7> A_XWL<6> A_RWL<6> B_RBLC<6> ++ B_RBLC<7> B_RBLT<6> B_RBLT<7> B_XWL<6> B_RWL<6> VDD_CORE VSS ++ VDD_CORE VSS / RM_IHPSG13_256x8_c3_2P_BITKIT_CELL +XCELL<21> A_RBLC<6> A_RBLC<5> A_RBLT<6> A_RBLT<5> A_XWL<5> A_RWL<5> B_RBLC<6> ++ B_RBLC<5> B_RBLT<6> B_RBLT<5> B_XWL<5> B_RWL<5> VDD_CORE VSS ++ VDD_CORE VSS / RM_IHPSG13_256x8_c3_2P_BITKIT_CELL +XCELL<20> A_RBLC<4> A_RBLC<5> A_RBLT<4> A_RBLT<5> A_XWL<4> A_RWL<4> B_RBLC<4> ++ B_RBLC<5> B_RBLT<4> B_RBLT<5> B_XWL<4> B_RWL<4> VDD_CORE VSS ++ VDD_CORE VSS / RM_IHPSG13_256x8_c3_2P_BITKIT_CELL +XCELL<19> A_RBLC<4> A_RBLC<3> A_RBLT<4> A_RBLT<3> A_XWL<3> A_RWL<3> B_RBLC<4> ++ B_RBLC<3> B_RBLT<4> B_RBLT<3> B_XWL<3> B_RWL<3> VDD_CORE VSS ++ VDD_CORE VSS / RM_IHPSG13_256x8_c3_2P_BITKIT_CELL +XCELL<18> A_RBLC<2> A_RBLC<3> A_RBLT<2> A_RBLT<3> A_XWL<2> A_RWL<2> B_RBLC<2> ++ B_RBLC<3> B_RBLT<2> B_RBLT<3> B_XWL<2> B_RWL<2> VDD_CORE VSS ++ VDD_CORE VSS / RM_IHPSG13_256x8_c3_2P_BITKIT_CELL +XCELL<17> A_RBLC<2> A_RBLC<1> A_RBLT<2> A_RBLT<1> A_XWL<1> A_RWL<1> B_RBLC<2> ++ B_RBLC<1> B_RBLT<2> B_RBLT<1> B_XWL<1> B_RWL<1> VDD_CORE VSS ++ VDD_CORE VSS / RM_IHPSG13_256x8_c3_2P_BITKIT_CELL +XCELL<16> A_BLC_BOT<1> A_RBLC<1> A_BLT_BOT<1> A_RBLT<1> A_XWL<0> A_RWL<0> ++ B_BLC_BOT<1> B_RBLC<1> B_BLT_BOT<1> B_RBLT<1> B_XWL<0> B_RWL<0> VDD_CORE ++ VSS VDD_CORE VSS / RM_IHPSG13_256x8_c3_2P_BITKIT_CELL +XCELL<15> A_BLC_TOP<0> A_LBLC<15> A_BLT_TOP<0> A_LBLT<15> A_LWL<15> A_XWL<15> ++ B_BLC_TOP<0> B_LBLC<15> B_BLT_TOP<0> B_LBLT<15> B_LWL<15> B_XWL<15> ++ VDD_CORE VSS VDD_CORE VSS / ++ RM_IHPSG13_256x8_c3_2P_BITKIT_CELL +XCELL<14> A_LBLC<14> A_LBLC<15> A_LBLT<14> A_LBLT<15> A_LWL<14> A_XWL<14> ++ B_LBLC<14> B_LBLC<15> B_LBLT<14> B_LBLT<15> B_LWL<14> B_XWL<14> VDD_CORE ++ VSS VDD_CORE VSS / RM_IHPSG13_256x8_c3_2P_BITKIT_CELL +XCELL<13> A_LBLC<14> A_LBLC<13> A_LBLT<14> A_LBLT<13> A_LWL<13> A_XWL<13> ++ B_LBLC<14> B_LBLC<13> B_LBLT<14> B_LBLT<13> B_LWL<13> B_XWL<13> VDD_CORE ++ VSS VDD_CORE VSS / RM_IHPSG13_256x8_c3_2P_BITKIT_CELL +XCELL<12> A_LBLC<12> A_LBLC<13> A_LBLT<12> A_LBLT<13> A_LWL<12> A_XWL<12> ++ B_LBLC<12> B_LBLC<13> B_LBLT<12> B_LBLT<13> B_LWL<12> B_XWL<12> VDD_CORE ++ VSS VDD_CORE VSS / RM_IHPSG13_256x8_c3_2P_BITKIT_CELL +XCELL<11> A_LBLC<12> A_LBLC<11> A_LBLT<12> A_LBLT<11> A_LWL<11> A_XWL<11> ++ B_LBLC<12> B_LBLC<11> B_LBLT<12> B_LBLT<11> B_LWL<11> B_XWL<11> VDD_CORE ++ VSS VDD_CORE VSS / RM_IHPSG13_256x8_c3_2P_BITKIT_CELL +XCELL<10> A_LBLC<10> A_LBLC<11> A_LBLT<10> A_LBLT<11> A_LWL<10> A_XWL<10> ++ B_LBLC<10> B_LBLC<11> B_LBLT<10> B_LBLT<11> B_LWL<10> B_XWL<10> VDD_CORE ++ VSS VDD_CORE VSS / RM_IHPSG13_256x8_c3_2P_BITKIT_CELL +XCELL<9> A_LBLC<10> A_LBLC<9> A_LBLT<10> A_LBLT<9> A_LWL<9> A_XWL<9> ++ B_LBLC<10> B_LBLC<9> B_LBLT<10> B_LBLT<9> B_LWL<9> B_XWL<9> VDD_CORE ++ VSS VDD_CORE VSS / RM_IHPSG13_256x8_c3_2P_BITKIT_CELL +XCELL<8> A_LBLC<8> A_LBLC<9> A_LBLT<8> A_LBLT<9> A_LWL<8> A_XWL<8> B_LBLC<8> ++ B_LBLC<9> B_LBLT<8> B_LBLT<9> B_LWL<8> B_XWL<8> VDD_CORE VSS ++ VDD_CORE VSS / RM_IHPSG13_256x8_c3_2P_BITKIT_CELL +XCELL<7> A_LBLC<8> A_LBLC<7> A_LBLT<8> A_LBLT<7> A_LWL<7> A_XWL<7> B_LBLC<8> ++ B_LBLC<7> B_LBLT<8> B_LBLT<7> B_LWL<7> B_XWL<7> VDD_CORE VSS ++ VDD_CORE VSS / RM_IHPSG13_256x8_c3_2P_BITKIT_CELL +XCELL<6> A_LBLC<6> A_LBLC<7> A_LBLT<6> A_LBLT<7> A_LWL<6> A_XWL<6> B_LBLC<6> ++ B_LBLC<7> B_LBLT<6> B_LBLT<7> B_LWL<6> B_XWL<6> VDD_CORE VSS ++ VDD_CORE VSS / RM_IHPSG13_256x8_c3_2P_BITKIT_CELL +XCELL<5> A_LBLC<6> A_LBLC<5> A_LBLT<6> A_LBLT<5> A_LWL<5> A_XWL<5> B_LBLC<6> ++ B_LBLC<5> B_LBLT<6> B_LBLT<5> B_LWL<5> B_XWL<5> VDD_CORE VSS ++ VDD_CORE VSS / RM_IHPSG13_256x8_c3_2P_BITKIT_CELL +XCELL<4> A_LBLC<4> A_LBLC<5> A_LBLT<4> A_LBLT<5> A_LWL<4> A_XWL<4> B_LBLC<4> ++ B_LBLC<5> B_LBLT<4> B_LBLT<5> B_LWL<4> B_XWL<4> VDD_CORE VSS ++ VDD_CORE VSS / RM_IHPSG13_256x8_c3_2P_BITKIT_CELL +XCELL<3> A_LBLC<4> A_LBLC<3> A_LBLT<4> A_LBLT<3> A_LWL<3> A_XWL<3> B_LBLC<4> ++ B_LBLC<3> B_LBLT<4> B_LBLT<3> B_LWL<3> B_XWL<3> VDD_CORE VSS ++ VDD_CORE VSS / RM_IHPSG13_256x8_c3_2P_BITKIT_CELL +XCELL<2> A_LBLC<2> A_LBLC<3> A_LBLT<2> A_LBLT<3> A_LWL<2> A_XWL<2> B_LBLC<2> ++ B_LBLC<3> B_LBLT<2> B_LBLT<3> B_LWL<2> B_XWL<2> VDD_CORE VSS ++ VDD_CORE VSS / RM_IHPSG13_256x8_c3_2P_BITKIT_CELL +XCELL<1> A_LBLC<2> A_LBLC<1> A_LBLT<2> A_LBLT<1> A_LWL<1> A_XWL<1> B_LBLC<2> ++ B_LBLC<1> B_LBLT<2> B_LBLT<1> B_LWL<1> B_XWL<1> VDD_CORE VSS ++ VDD_CORE VSS / RM_IHPSG13_256x8_c3_2P_BITKIT_CELL +XCELL<0> A_BLC_BOT<0> A_LBLC<1> A_BLT_BOT<0> A_LBLT<1> A_LWL<0> A_XWL<0> ++ B_BLC_BOT<0> B_LBLC<1> B_BLT_BOT<0> B_LBLT<1> B_LWL<0> B_XWL<0> VDD_CORE ++ VSS VDD_CORE VSS / RM_IHPSG13_256x8_c3_2P_BITKIT_CELL +.ENDS +.SUBCKT RM_IHPSG13_256x8_c3_2P_BITKIT_EDGE_TB A_BLC A_BLT B_BLC B_BLT NW PW VDD VSS +.ENDS +.SUBCKT RM_IHPSG13_256x8_c3_2P_BITKIT_16x2_EDGE_TB A_BLC<1> A_BLC<0> A_BLT<1> A_BLT<0> ++ B_BLC<1> B_BLC<0> B_BLT<1> B_BLT<0> VDD_CORE VSS +XEDGE<1> A_BLC<1> A_BLT<1> B_BLC<1> B_BLT<1> VDD_CORE VSS ++ VDD_CORE VSS / RM_IHPSG13_256x8_c3_2P_BITKIT_EDGE_TB +XEDGE<0> A_BLC<0> A_BLT<0> B_BLC<0> B_BLT<0> VDD_CORE VSS ++ VDD_CORE VSS / RM_IHPSG13_256x8_c3_2P_BITKIT_EDGE_TB +.ENDS +.SUBCKT RM_IHPSG13_256x8_c3_2P_BITKIT_TAP A_BLC A_BLT B_BLC B_BLT NW PW VDD VSS +.ENDS +.SUBCKT RM_IHPSG13_256x8_c3_2P_BITKIT_16x2_TAP A_BLC<1> A_BLC<0> A_BLT<1> A_BLT<0> ++ B_BLC<1> B_BLC<0> B_BLT<1> B_BLT<0> VDD_CORE VSS +XIEDGEBP_COL1<1> A_BLC<1> A_BLT<1> B_BLC<1> B_BLT<1> VDD_CORE VSS ++ VDD_CORE VSS / RM_IHPSG13_256x8_c3_2P_BITKIT_EDGE_TB +XIEDGEBP_COL1<0> A_BLC<1> A_BLT<1> B_BLC<1> B_BLT<1> VDD_CORE VSS ++ VDD_CORE VSS / RM_IHPSG13_256x8_c3_2P_BITKIT_EDGE_TB +XIEDGEBP_COL2<1> A_BLC<0> A_BLT<0> B_BLC<0> B_BLT<0> VDD_CORE VSS ++ VDD_CORE VSS / RM_IHPSG13_256x8_c3_2P_BITKIT_EDGE_TB +XIEDGEBP_COL2<0> A_BLC<0> A_BLT<0> B_BLC<0> B_BLT<0> VDD_CORE VSS ++ VDD_CORE VSS / RM_IHPSG13_256x8_c3_2P_BITKIT_EDGE_TB +XITAP<1> A_BLC<1> A_BLT<1> B_BLC<1> B_BLT<1> VDD_CORE VSS ++ VDD_CORE VSS / RM_IHPSG13_256x8_c3_2P_BITKIT_TAP +XITAP<0> A_BLC<0> A_BLT<0> B_BLC<0> B_BLT<0> VDD_CORE VSS ++ VDD_CORE VSS / RM_IHPSG13_256x8_c3_2P_BITKIT_TAP +.ENDS + + +.SUBCKT RM_IHPSG13_256x8_c3_1P_BITKIT_TAP_LR NW PW VDD VSS +.ENDS +.SUBCKT RM_IHPSG13_256x8_c3_2P_BITKIT_16x2_TAP_LR VDD_CORE VSS +XCORNER<1> VDD_CORE VSS VDD_CORE VSS / ++ RM_IHPSG13_256x8_c3_1P_BITKIT_CORNER +XCORNER<0> VDD_CORE VSS VDD_CORE VSS / ++ RM_IHPSG13_256x8_c3_1P_BITKIT_CORNER +XTAP_BORDER VDD_CORE VSS VDD_CORE VSS / ++ RM_IHPSG13_256x8_c3_1P_BITKIT_TAP_LR +.ENDS + +.SUBCKT RSC_IHPSG13_CBUFX12 A Z VDD VSS +MN1 Z net6 VSS VSS sg13_lv_nmos m=1 w=4.23u l=130.00n ng=6 nrd=0 nrs=0 +MN0 net6 A VSS VSS sg13_lv_nmos m=1 w=1.41u l=130.00n ng=2 nrd=0 nrs=0 +MP1 Z net6 VDD VDD sg13_lv_pmos m=1 w=9.72u l=130.00n ng=6 nrd=0 nrs=0 +MP0 net6 A VDD VDD sg13_lv_pmos m=1 w=3.24u l=130.00n ng=2 nrd=0 nrs=0 +.ENDS +.SUBCKT RM_IHPSG13_256x8_c3_2P_COLDRV13X12 ADDR_COL_I<1> ADDR_COL_I<0> ADDR_COL_O<1> ++ ADDR_COL_O<0> ADDR_DEC_I<7> ADDR_DEC_I<6> ADDR_DEC_I<5> ADDR_DEC_I<4> ++ ADDR_DEC_I<3> ADDR_DEC_I<2> ADDR_DEC_I<1> ADDR_DEC_I<0> ADDR_DEC_O<7> ++ ADDR_DEC_O<6> ADDR_DEC_O<5> ADDR_DEC_O<4> ADDR_DEC_O<3> ADDR_DEC_O<2> ++ ADDR_DEC_O<1> ADDR_DEC_O<0> DCLK_I DCLK_O RCLK_I RCLK_O WCLK_I WCLK_O ++ VDD VSS +XI1<3> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI1<2> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI1<1> VDD VSS / RSC_IHPSG13_FILLCAP8 +XWCLK_DRV WCLK_I WCLK_O VDD VSS / RSC_IHPSG13_CBUFX12 +XRCLK_DRV RCLK_I RCLK_O VDD VSS / RSC_IHPSG13_CBUFX12 +XDCLK_DRV DCLK_I DCLK_O VDD VSS / RSC_IHPSG13_CBUFX12 +XADDR_COL_DRV<1> ADDR_COL_I<1> ADDR_COL_O<1> VDD VSS / ++ RSC_IHPSG13_CBUFX12 +XADDR_COL_DRV<0> ADDR_COL_I<0> ADDR_COL_O<0> VDD VSS / ++ RSC_IHPSG13_CBUFX12 +XADDR_DEC_DRV<7> ADDR_DEC_I<7> ADDR_DEC_O<7> VDD VSS / ++ RSC_IHPSG13_CBUFX12 +XADDR_DEC_DRV<6> ADDR_DEC_I<6> ADDR_DEC_O<6> VDD VSS / ++ RSC_IHPSG13_CBUFX12 +XADDR_DEC_DRV<5> ADDR_DEC_I<5> ADDR_DEC_O<5> VDD VSS / ++ RSC_IHPSG13_CBUFX12 +XADDR_DEC_DRV<4> ADDR_DEC_I<4> ADDR_DEC_O<4> VDD VSS / ++ RSC_IHPSG13_CBUFX12 +XADDR_DEC_DRV<3> ADDR_DEC_I<3> ADDR_DEC_O<3> VDD VSS / ++ RSC_IHPSG13_CBUFX12 +XADDR_DEC_DRV<2> ADDR_DEC_I<2> ADDR_DEC_O<2> VDD VSS / ++ RSC_IHPSG13_CBUFX12 +XADDR_DEC_DRV<1> ADDR_DEC_I<1> ADDR_DEC_O<1> VDD VSS / ++ RSC_IHPSG13_CBUFX12 +XADDR_DEC_DRV<0> ADDR_DEC_I<0> ADDR_DEC_O<0> VDD VSS / ++ RSC_IHPSG13_CBUFX12 +XI0<6> VDD VSS / RSC_IHPSG13_FILLCAP4 +XI0<5> VDD VSS / RSC_IHPSG13_FILLCAP4 +XI0<4> VDD VSS / RSC_IHPSG13_FILLCAP4 +XI0<3> VDD VSS / RSC_IHPSG13_FILLCAP4 +XI0<2> VDD VSS / RSC_IHPSG13_FILLCAP4 +XI0<1> VDD VSS / RSC_IHPSG13_FILLCAP4 +.ENDS +.SUBCKT RSC_IHPSG13_WLDRVX12 A Z VDD VSS +MN1 Z net6 VSS VSS sg13_lv_nmos m=1 w=1.41u l=130.00n ng=2 nrd=0 nrs=0 +MN0 net6 A VSS VSS sg13_lv_nmos m=1 w=1.8u l=130.00n ng=2 nrd=0 nrs=0 +MP1 Z net6 VDD VDD sg13_lv_pmos m=1 w=9.72u l=130.00n ng=6 nrd=0 nrs=0 +MP0 net6 A VDD VDD sg13_lv_pmos m=1 w=900.0n l=130.00n ng=1 nrd=0 nrs=0 +.ENDS +.SUBCKT RM_IHPSG13_256x8_c3_2P_WLDRV16X12 A<15> A<14> A<13> A<12> A<11> A<10> A<9> A<8> ++ A<7> A<6> A<5> A<4> A<3> A<2> A<1> A<0> Z<15> Z<14> Z<13> Z<12> Z<11> Z<10> ++ Z<9> Z<8> Z<7> Z<6> Z<5> Z<4> Z<3> Z<2> Z<1> Z<0> VDD VSS +XBUF<15> A<15> Z<15> VDD VSS / RSC_IHPSG13_WLDRVX12 +XBUF<14> A<14> Z<14> VDD VSS / RSC_IHPSG13_WLDRVX12 +XBUF<13> A<13> Z<13> VDD VSS / RSC_IHPSG13_WLDRVX12 +XBUF<12> A<12> Z<12> VDD VSS / RSC_IHPSG13_WLDRVX12 +XBUF<11> A<11> Z<11> VDD VSS / RSC_IHPSG13_WLDRVX12 +XBUF<10> A<10> Z<10> VDD VSS / RSC_IHPSG13_WLDRVX12 +XBUF<9> A<9> Z<9> VDD VSS / RSC_IHPSG13_WLDRVX12 +XBUF<8> A<8> Z<8> VDD VSS / RSC_IHPSG13_WLDRVX12 +XBUF<7> A<7> Z<7> VDD VSS / RSC_IHPSG13_WLDRVX12 +XBUF<6> A<6> Z<6> VDD VSS / RSC_IHPSG13_WLDRVX12 +XBUF<5> A<5> Z<5> VDD VSS / RSC_IHPSG13_WLDRVX12 +XBUF<4> A<4> Z<4> VDD VSS / RSC_IHPSG13_WLDRVX12 +XBUF<3> A<3> Z<3> VDD VSS / RSC_IHPSG13_WLDRVX12 +XBUF<2> A<2> Z<2> VDD VSS / RSC_IHPSG13_WLDRVX12 +XBUF<1> A<1> Z<1> VDD VSS / RSC_IHPSG13_WLDRVX12 +XBUF<0> A<0> Z<0> VDD VSS / RSC_IHPSG13_WLDRVX12 +.ENDS +.SUBCKT RM_IHPSG13_256x8_c3_2P_DEC04 ADDR<3> ADDR<2> ADDR<1> ADDR<0> CS ECLK_H_BOT ++ ECLK_H_TOP ECLK_L_BOT ECLK_L_TOP WL<15> WL<14> WL<13> WL<12> WL<11> WL<10> ++ WL<9> WL<8> WL<7> WL<6> WL<5> WL<4> WL<3> WL<2> WL<1> WL<0> VDD VSS +XI0<3> PADR<1> PADR<0> sel01<3> VDD VSS / RSC_IHPSG13_NAND2X2 +XI0<2> PADR<1> NADR<0> sel01<2> VDD VSS / RSC_IHPSG13_NAND2X2 +XI0<1> NADR<1> PADR<0> sel01<1> VDD VSS / RSC_IHPSG13_NAND2X2 +XI0<0> NADR<1> NADR<0> sel01<0> VDD VSS / RSC_IHPSG13_NAND2X2 +XI4 ECLK_L_BOT EN VDD VSS / RSC_IHPSG13_CINVX4 +XI5 ECLK_H_BOT ECLK_L_BOT VDD VSS / RSC_IHPSG13_CINVX2 +XI3<3> PADR<3> NADR<3> VDD VSS / RSC_IHPSG13_INVX2 +XI3<2> PADR<2> NADR<2> VDD VSS / RSC_IHPSG13_INVX2 +XI3<1> PADR<1> NADR<1> VDD VSS / RSC_IHPSG13_INVX2 +XI3<0> PADR<0> NADR<0> VDD VSS / RSC_IHPSG13_INVX2 +XR0 ECLK_H_BOT ECLK_H_TOP / RSC_IHPSG13_MET2RES +XI11 ECLK_L_BOT ECLK_L_TOP / RSC_IHPSG13_MET2RES +XI1<3> PADR<2> PADR<3> CS sel23<3> VDD VSS / RSC_IHPSG13_NAND3X2 +XI1<2> NADR<2> PADR<3> CS sel23<2> VDD VSS / RSC_IHPSG13_NAND3X2 +XI1<1> PADR<2> NADR<3> CS sel23<1> VDD VSS / RSC_IHPSG13_NAND3X2 +XI1<0> NADR<2> NADR<3> CS sel23<0> VDD VSS / RSC_IHPSG13_NAND3X2 +XI2<15> sel23<3> sel01<3> EN WL<15> VDD VSS / RSC_IHPSG13_NOR3X2 +XI2<14> sel23<3> sel01<2> EN WL<14> VDD VSS / RSC_IHPSG13_NOR3X2 +XI2<13> sel23<3> sel01<1> EN WL<13> VDD VSS / RSC_IHPSG13_NOR3X2 +XI2<12> sel23<3> sel01<0> EN WL<12> VDD VSS / RSC_IHPSG13_NOR3X2 +XI2<11> sel23<2> sel01<3> EN WL<11> VDD VSS / RSC_IHPSG13_NOR3X2 +XI2<10> sel23<2> sel01<2> EN WL<10> VDD VSS / RSC_IHPSG13_NOR3X2 +XI2<9> sel23<2> sel01<1> EN WL<9> VDD VSS / RSC_IHPSG13_NOR3X2 +XI2<8> sel23<2> sel01<0> EN WL<8> VDD VSS / RSC_IHPSG13_NOR3X2 +XI2<7> sel23<1> sel01<3> EN WL<7> VDD VSS / RSC_IHPSG13_NOR3X2 +XI2<6> sel23<1> sel01<2> EN WL<6> VDD VSS / RSC_IHPSG13_NOR3X2 +XI2<5> sel23<1> sel01<1> EN WL<5> VDD VSS / RSC_IHPSG13_NOR3X2 +XI2<4> sel23<1> sel01<0> EN WL<4> VDD VSS / RSC_IHPSG13_NOR3X2 +XI2<3> sel23<0> sel01<3> EN WL<3> VDD VSS / RSC_IHPSG13_NOR3X2 +XI2<2> sel23<0> sel01<2> EN WL<2> VDD VSS / RSC_IHPSG13_NOR3X2 +XI2<1> sel23<0> sel01<1> EN WL<1> VDD VSS / RSC_IHPSG13_NOR3X2 +XI2<0> sel23<0> sel01<0> EN WL<0> VDD VSS / RSC_IHPSG13_NOR3X2 +XCAPS4 VDD VSS / RSC_IHPSG13_FILLCAP4 +XLATCH<3> CS ADDR<3> PADR<3> VDD VSS / RSC_IHPSG13_LHPQX2 +XLATCH<2> CS ADDR<2> PADR<2> VDD VSS / RSC_IHPSG13_LHPQX2 +XLATCH<1> CS ADDR<1> PADR<1> VDD VSS / RSC_IHPSG13_LHPQX2 +XLATCH<0> CS ADDR<0> PADR<0> VDD VSS / RSC_IHPSG13_LHPQX2 +.ENDS +.SUBCKT RM_IHPSG13_256x8_c3_2P_DEC02 ADDR<1> ADDR<0> CS CS_OUT VDD VSS +XDEC ADDR<1> NADDR<0> CS net1 VDD VSS / RSC_IHPSG13_NAND3X2 +XADDRINV ADDR<0> NADDR<0> VDD VSS / RSC_IHPSG13_INVX2 +XDECINV net1 CS_OUT VDD VSS / RSC_IHPSG13_INVX4 +XI2<1> VDD VSS / RSC_IHPSG13_FILLCAP4 +XI2<0> VDD VSS / RSC_IHPSG13_FILLCAP4 +.ENDS +.SUBCKT RM_IHPSG13_256x8_c3_2P_DEC01 ADDR<1> ADDR<0> CS CS_OUT VDD VSS +XDEC NADDR<1> ADDR<0> CS net1 VDD VSS / RSC_IHPSG13_NAND3X2 +XADDRINV ADDR<1> NADDR<1> VDD VSS / RSC_IHPSG13_INVX2 +XDECINV net1 CS_OUT VDD VSS / RSC_IHPSG13_INVX4 +XI2<1> VDD VSS / RSC_IHPSG13_FILLCAP4 +XI2<0> VDD VSS / RSC_IHPSG13_FILLCAP4 +.ENDS +.SUBCKT RM_IHPSG13_256x8_c3_2P_DEC00 ADDR<1> ADDR<0> CS CS_OUT VDD VSS +XDEC NADDR<1> NADDR<0> CS net1 VDD VSS / RSC_IHPSG13_NAND3X2 +XADDRINV<1> ADDR<1> NADDR<1> VDD VSS / RSC_IHPSG13_INVX2 +XADDRINV<0> ADDR<0> NADDR<0> VDD VSS / RSC_IHPSG13_INVX2 +XI1<1> VDD VSS / RSC_IHPSG13_FILLCAP4 +XI1<0> VDD VSS / RSC_IHPSG13_FILLCAP4 +XDECINV net1 CS_OUT VDD VSS / RSC_IHPSG13_INVX4 +.ENDS +.SUBCKT RM_IHPSG13_256x8_c3_2P_DEC03 ADDR<1> ADDR<0> CS CS_OUT VDD VSS +XDEC ADDR<1> ADDR<0> CS net1 VDD VSS / RSC_IHPSG13_NAND3X2 +XDECINV net1 CS_OUT VDD VSS / RSC_IHPSG13_INVX4 +XI0<1> VDD VSS / RSC_IHPSG13_FILLCAP4 +XI0<0> VDD VSS / RSC_IHPSG13_FILLCAP4 +.ENDS +.SUBCKT RM_IHPSG13_256x8_c3_2P_ROWDEC9 ADDR_N_I<8> ADDR_N_I<7> ADDR_N_I<6> ADDR_N_I<5> ++ ADDR_N_I<4> ADDR_N_I<3> ADDR_N_I<2> ADDR_N_I<1> ADDR_N_I<0> CS_I ECLK_I ++ WL_O<511> WL_O<510> WL_O<509> WL_O<508> WL_O<507> WL_O<506> WL_O<505> ++ WL_O<504> WL_O<503> WL_O<502> WL_O<501> WL_O<500> WL_O<499> WL_O<498> ++ WL_O<497> WL_O<496> WL_O<495> WL_O<494> WL_O<493> WL_O<492> WL_O<491> ++ WL_O<490> WL_O<489> WL_O<488> WL_O<487> WL_O<486> WL_O<485> WL_O<484> ++ WL_O<483> WL_O<482> WL_O<481> WL_O<480> WL_O<479> WL_O<478> WL_O<477> ++ WL_O<476> WL_O<475> WL_O<474> WL_O<473> WL_O<472> WL_O<471> WL_O<470> ++ WL_O<469> WL_O<468> WL_O<467> WL_O<466> WL_O<465> WL_O<464> WL_O<463> ++ WL_O<462> WL_O<461> WL_O<460> WL_O<459> WL_O<458> WL_O<457> WL_O<456> ++ WL_O<455> WL_O<454> WL_O<453> WL_O<452> WL_O<451> WL_O<450> WL_O<449> ++ WL_O<448> WL_O<447> WL_O<446> WL_O<445> WL_O<444> WL_O<443> WL_O<442> ++ WL_O<441> WL_O<440> WL_O<439> WL_O<438> WL_O<437> WL_O<436> WL_O<435> ++ WL_O<434> WL_O<433> WL_O<432> WL_O<431> WL_O<430> WL_O<429> WL_O<428> ++ WL_O<427> WL_O<426> WL_O<425> WL_O<424> WL_O<423> WL_O<422> WL_O<421> ++ WL_O<420> WL_O<419> WL_O<418> WL_O<417> WL_O<416> WL_O<415> WL_O<414> ++ WL_O<413> WL_O<412> WL_O<411> WL_O<410> WL_O<409> WL_O<408> WL_O<407> ++ WL_O<406> WL_O<405> WL_O<404> WL_O<403> WL_O<402> WL_O<401> WL_O<400> ++ WL_O<399> WL_O<398> WL_O<397> WL_O<396> WL_O<395> WL_O<394> WL_O<393> ++ WL_O<392> WL_O<391> WL_O<390> WL_O<389> WL_O<388> WL_O<387> WL_O<386> ++ WL_O<385> WL_O<384> WL_O<383> WL_O<382> WL_O<381> WL_O<380> WL_O<379> ++ WL_O<378> WL_O<377> WL_O<376> WL_O<375> WL_O<374> WL_O<373> WL_O<372> ++ WL_O<371> WL_O<370> WL_O<369> WL_O<368> WL_O<367> WL_O<366> WL_O<365> ++ WL_O<364> WL_O<363> WL_O<362> WL_O<361> WL_O<360> WL_O<359> WL_O<358> ++ WL_O<357> WL_O<356> WL_O<355> WL_O<354> WL_O<353> WL_O<352> WL_O<351> ++ WL_O<350> WL_O<349> WL_O<348> WL_O<347> WL_O<346> WL_O<345> WL_O<344> ++ WL_O<343> WL_O<342> WL_O<341> WL_O<340> WL_O<339> WL_O<338> WL_O<337> ++ WL_O<336> WL_O<335> WL_O<334> WL_O<333> WL_O<332> WL_O<331> WL_O<330> ++ WL_O<329> WL_O<328> WL_O<327> WL_O<326> WL_O<325> WL_O<324> WL_O<323> ++ WL_O<322> WL_O<321> WL_O<320> WL_O<319> WL_O<318> WL_O<317> WL_O<316> ++ WL_O<315> WL_O<314> WL_O<313> WL_O<312> WL_O<311> WL_O<310> WL_O<309> ++ WL_O<308> WL_O<307> WL_O<306> WL_O<305> WL_O<304> WL_O<303> WL_O<302> ++ WL_O<301> WL_O<300> WL_O<299> WL_O<298> WL_O<297> WL_O<296> WL_O<295> ++ WL_O<294> WL_O<293> WL_O<292> WL_O<291> WL_O<290> WL_O<289> WL_O<288> ++ WL_O<287> WL_O<286> WL_O<285> WL_O<284> WL_O<283> WL_O<282> WL_O<281> ++ WL_O<280> WL_O<279> WL_O<278> WL_O<277> WL_O<276> WL_O<275> WL_O<274> ++ WL_O<273> WL_O<272> WL_O<271> WL_O<270> WL_O<269> WL_O<268> WL_O<267> ++ WL_O<266> WL_O<265> WL_O<264> WL_O<263> WL_O<262> WL_O<261> WL_O<260> ++ WL_O<259> WL_O<258> WL_O<257> WL_O<256> WL_O<255> WL_O<254> WL_O<253> ++ WL_O<252> WL_O<251> WL_O<250> WL_O<249> WL_O<248> WL_O<247> WL_O<246> ++ WL_O<245> WL_O<244> WL_O<243> WL_O<242> WL_O<241> WL_O<240> WL_O<239> ++ WL_O<238> WL_O<237> WL_O<236> WL_O<235> WL_O<234> WL_O<233> WL_O<232> ++ WL_O<231> WL_O<230> WL_O<229> WL_O<228> WL_O<227> WL_O<226> WL_O<225> ++ WL_O<224> WL_O<223> WL_O<222> WL_O<221> WL_O<220> WL_O<219> WL_O<218> ++ WL_O<217> WL_O<216> WL_O<215> WL_O<214> WL_O<213> WL_O<212> WL_O<211> ++ WL_O<210> WL_O<209> WL_O<208> WL_O<207> WL_O<206> WL_O<205> WL_O<204> ++ WL_O<203> WL_O<202> WL_O<201> WL_O<200> WL_O<199> WL_O<198> WL_O<197> ++ WL_O<196> WL_O<195> WL_O<194> WL_O<193> WL_O<192> WL_O<191> WL_O<190> ++ WL_O<189> WL_O<188> WL_O<187> WL_O<186> WL_O<185> WL_O<184> WL_O<183> ++ WL_O<182> WL_O<181> WL_O<180> WL_O<179> WL_O<178> WL_O<177> WL_O<176> ++ WL_O<175> WL_O<174> WL_O<173> WL_O<172> WL_O<171> WL_O<170> WL_O<169> ++ WL_O<168> WL_O<167> WL_O<166> WL_O<165> WL_O<164> WL_O<163> WL_O<162> ++ WL_O<161> WL_O<160> WL_O<159> WL_O<158> WL_O<157> WL_O<156> WL_O<155> ++ WL_O<154> WL_O<153> WL_O<152> WL_O<151> WL_O<150> WL_O<149> WL_O<148> ++ WL_O<147> WL_O<146> WL_O<145> WL_O<144> WL_O<143> WL_O<142> WL_O<141> ++ WL_O<140> WL_O<139> WL_O<138> WL_O<137> WL_O<136> WL_O<135> WL_O<134> ++ WL_O<133> WL_O<132> WL_O<131> WL_O<130> WL_O<129> WL_O<128> WL_O<127> ++ WL_O<126> WL_O<125> WL_O<124> WL_O<123> WL_O<122> WL_O<121> WL_O<120> ++ WL_O<119> WL_O<118> WL_O<117> WL_O<116> WL_O<115> WL_O<114> WL_O<113> ++ WL_O<112> WL_O<111> WL_O<110> WL_O<109> WL_O<108> WL_O<107> WL_O<106> ++ WL_O<105> WL_O<104> WL_O<103> WL_O<102> WL_O<101> WL_O<100> WL_O<99> ++ WL_O<98> WL_O<97> WL_O<96> WL_O<95> WL_O<94> WL_O<93> WL_O<92> WL_O<91> ++ WL_O<90> WL_O<89> WL_O<88> WL_O<87> WL_O<86> WL_O<85> WL_O<84> WL_O<83> ++ WL_O<82> WL_O<81> WL_O<80> WL_O<79> WL_O<78> WL_O<77> WL_O<76> WL_O<75> ++ WL_O<74> WL_O<73> WL_O<72> WL_O<71> WL_O<70> WL_O<69> WL_O<68> WL_O<67> ++ WL_O<66> WL_O<65> WL_O<64> WL_O<63> WL_O<62> WL_O<61> WL_O<60> WL_O<59> ++ WL_O<58> WL_O<57> WL_O<56> WL_O<55> WL_O<54> WL_O<53> WL_O<52> WL_O<51> ++ WL_O<50> WL_O<49> WL_O<48> WL_O<47> WL_O<46> WL_O<45> WL_O<44> WL_O<43> ++ WL_O<42> WL_O<41> WL_O<40> WL_O<39> WL_O<38> WL_O<37> WL_O<36> WL_O<35> ++ WL_O<34> WL_O<33> WL_O<32> WL_O<31> WL_O<30> WL_O<29> WL_O<28> WL_O<27> ++ WL_O<26> WL_O<25> WL_O<24> WL_O<23> WL_O<22> WL_O<21> WL_O<20> WL_O<19> ++ WL_O<18> WL_O<17> WL_O<16> WL_O<15> WL_O<14> WL_O<13> WL_O<12> WL_O<11> ++ WL_O<10> WL_O<9> WL_O<8> WL_O<7> WL_O<6> WL_O<5> WL_O<4> WL_O<3> WL_O<2> ++ WL_O<1> WL_O<0> VDD VSS +XSEL<31> ADDR_N_I<3> ADDR_N_I<2> ADDR_N_I<1> ADDR_N_I<0> CS00<31> ECLK_H<31> ++ ECLK_H<32> ECLK_B<31> ECLK_B<32> WL_O<511> WL_O<510> WL_O<509> WL_O<508> ++ WL_O<507> WL_O<506> WL_O<505> WL_O<504> WL_O<503> WL_O<502> WL_O<501> ++ WL_O<500> WL_O<499> WL_O<498> WL_O<497> WL_O<496> VDD VSS / ++ RM_IHPSG13_256x8_c3_2P_DEC04 +XSEL<30> ADDR_N_I<3> ADDR_N_I<2> ADDR_N_I<1> ADDR_N_I<0> CS00<30> ECLK_H<30> ++ ECLK_H<31> ECLK_B<30> ECLK_B<31> WL_O<495> WL_O<494> WL_O<493> WL_O<492> ++ WL_O<491> WL_O<490> WL_O<489> WL_O<488> WL_O<487> WL_O<486> WL_O<485> ++ WL_O<484> WL_O<483> WL_O<482> WL_O<481> WL_O<480> VDD VSS / ++ RM_IHPSG13_256x8_c3_2P_DEC04 +XSEL<29> ADDR_N_I<3> ADDR_N_I<2> ADDR_N_I<1> ADDR_N_I<0> CS00<29> ECLK_H<29> ++ ECLK_H<30> ECLK_B<29> ECLK_B<30> WL_O<479> WL_O<478> WL_O<477> WL_O<476> ++ WL_O<475> WL_O<474> WL_O<473> WL_O<472> WL_O<471> WL_O<470> WL_O<469> ++ WL_O<468> WL_O<467> WL_O<466> WL_O<465> WL_O<464> VDD VSS / ++ RM_IHPSG13_256x8_c3_2P_DEC04 +XSEL<28> ADDR_N_I<3> ADDR_N_I<2> ADDR_N_I<1> ADDR_N_I<0> CS00<28> ECLK_H<28> ++ ECLK_H<29> ECLK_B<28> ECLK_B<29> WL_O<463> WL_O<462> WL_O<461> WL_O<460> ++ WL_O<459> WL_O<458> WL_O<457> WL_O<456> WL_O<455> WL_O<454> WL_O<453> ++ WL_O<452> WL_O<451> WL_O<450> WL_O<449> WL_O<448> VDD VSS / ++ RM_IHPSG13_256x8_c3_2P_DEC04 +XSEL<27> ADDR_N_I<3> ADDR_N_I<2> ADDR_N_I<1> ADDR_N_I<0> CS00<27> ECLK_H<27> ++ ECLK_H<28> ECLK_B<27> ECLK_B<28> WL_O<447> WL_O<446> WL_O<445> WL_O<444> ++ WL_O<443> WL_O<442> WL_O<441> WL_O<440> WL_O<439> WL_O<438> WL_O<437> ++ WL_O<436> WL_O<435> WL_O<434> WL_O<433> WL_O<432> VDD VSS / ++ RM_IHPSG13_256x8_c3_2P_DEC04 +XSEL<26> ADDR_N_I<3> ADDR_N_I<2> ADDR_N_I<1> ADDR_N_I<0> CS00<26> ECLK_H<26> ++ ECLK_H<27> ECLK_B<26> ECLK_B<27> WL_O<431> WL_O<430> WL_O<429> WL_O<428> ++ WL_O<427> WL_O<426> WL_O<425> WL_O<424> WL_O<423> WL_O<422> WL_O<421> ++ WL_O<420> WL_O<419> WL_O<418> WL_O<417> WL_O<416> VDD VSS / ++ RM_IHPSG13_256x8_c3_2P_DEC04 +XSEL<25> ADDR_N_I<3> ADDR_N_I<2> ADDR_N_I<1> ADDR_N_I<0> CS00<25> ECLK_H<25> ++ ECLK_H<26> ECLK_B<25> ECLK_B<26> WL_O<415> WL_O<414> WL_O<413> WL_O<412> ++ WL_O<411> WL_O<410> WL_O<409> WL_O<408> WL_O<407> WL_O<406> WL_O<405> ++ WL_O<404> WL_O<403> WL_O<402> WL_O<401> WL_O<400> VDD VSS / ++ RM_IHPSG13_256x8_c3_2P_DEC04 +XSEL<24> ADDR_N_I<3> ADDR_N_I<2> ADDR_N_I<1> ADDR_N_I<0> CS00<24> ECLK_H<24> ++ ECLK_H<25> ECLK_B<24> ECLK_B<25> WL_O<399> WL_O<398> WL_O<397> WL_O<396> ++ WL_O<395> WL_O<394> WL_O<393> WL_O<392> WL_O<391> WL_O<390> WL_O<389> ++ WL_O<388> WL_O<387> WL_O<386> WL_O<385> WL_O<384> VDD VSS / ++ RM_IHPSG13_256x8_c3_2P_DEC04 +XSEL<23> ADDR_N_I<3> ADDR_N_I<2> ADDR_N_I<1> ADDR_N_I<0> CS00<23> ECLK_H<23> ++ ECLK_H<24> ECLK_B<23> ECLK_B<24> WL_O<383> WL_O<382> WL_O<381> WL_O<380> ++ WL_O<379> WL_O<378> WL_O<377> WL_O<376> WL_O<375> WL_O<374> WL_O<373> ++ WL_O<372> WL_O<371> WL_O<370> WL_O<369> WL_O<368> VDD VSS / ++ RM_IHPSG13_256x8_c3_2P_DEC04 +XSEL<22> ADDR_N_I<3> ADDR_N_I<2> ADDR_N_I<1> ADDR_N_I<0> CS00<22> ECLK_H<22> ++ ECLK_H<23> ECLK_B<22> ECLK_B<23> WL_O<367> WL_O<366> WL_O<365> WL_O<364> ++ WL_O<363> WL_O<362> WL_O<361> WL_O<360> WL_O<359> WL_O<358> WL_O<357> ++ WL_O<356> WL_O<355> WL_O<354> WL_O<353> WL_O<352> VDD VSS / ++ RM_IHPSG13_256x8_c3_2P_DEC04 +XSEL<21> ADDR_N_I<3> ADDR_N_I<2> ADDR_N_I<1> ADDR_N_I<0> CS00<21> ECLK_H<21> ++ ECLK_H<22> ECLK_B<21> ECLK_B<22> WL_O<351> WL_O<350> WL_O<349> WL_O<348> ++ WL_O<347> WL_O<346> WL_O<345> WL_O<344> WL_O<343> WL_O<342> WL_O<341> ++ WL_O<340> WL_O<339> WL_O<338> WL_O<337> WL_O<336> VDD VSS / ++ RM_IHPSG13_256x8_c3_2P_DEC04 +XSEL<20> ADDR_N_I<3> ADDR_N_I<2> ADDR_N_I<1> ADDR_N_I<0> CS00<20> ECLK_H<20> ++ ECLK_H<21> ECLK_B<20> ECLK_B<21> WL_O<335> WL_O<334> WL_O<333> WL_O<332> ++ WL_O<331> WL_O<330> WL_O<329> WL_O<328> WL_O<327> WL_O<326> WL_O<325> ++ WL_O<324> WL_O<323> WL_O<322> WL_O<321> WL_O<320> VDD VSS / ++ RM_IHPSG13_256x8_c3_2P_DEC04 +XSEL<19> ADDR_N_I<3> ADDR_N_I<2> ADDR_N_I<1> ADDR_N_I<0> CS00<19> ECLK_H<19> ++ ECLK_H<20> ECLK_B<19> ECLK_B<20> WL_O<319> WL_O<318> WL_O<317> WL_O<316> ++ WL_O<315> WL_O<314> WL_O<313> WL_O<312> WL_O<311> WL_O<310> WL_O<309> ++ WL_O<308> WL_O<307> WL_O<306> WL_O<305> WL_O<304> VDD VSS / ++ RM_IHPSG13_256x8_c3_2P_DEC04 +XSEL<18> ADDR_N_I<3> ADDR_N_I<2> ADDR_N_I<1> ADDR_N_I<0> CS00<18> ECLK_H<18> ++ ECLK_H<19> ECLK_B<18> ECLK_B<19> WL_O<303> WL_O<302> WL_O<301> WL_O<300> ++ WL_O<299> WL_O<298> WL_O<297> WL_O<296> WL_O<295> WL_O<294> WL_O<293> ++ WL_O<292> WL_O<291> WL_O<290> WL_O<289> WL_O<288> VDD VSS / ++ RM_IHPSG13_256x8_c3_2P_DEC04 +XSEL<17> ADDR_N_I<3> ADDR_N_I<2> ADDR_N_I<1> ADDR_N_I<0> CS00<17> ECLK_H<17> ++ ECLK_H<18> ECLK_B<17> ECLK_B<18> WL_O<287> WL_O<286> WL_O<285> WL_O<284> ++ WL_O<283> WL_O<282> WL_O<281> WL_O<280> WL_O<279> WL_O<278> WL_O<277> ++ WL_O<276> WL_O<275> WL_O<274> WL_O<273> WL_O<272> VDD VSS / ++ RM_IHPSG13_256x8_c3_2P_DEC04 +XSEL<16> ADDR_N_I<3> ADDR_N_I<2> ADDR_N_I<1> ADDR_N_I<0> CS00<16> ECLK_H<16> ++ ECLK_H<17> ECLK_B<16> ECLK_B<17> WL_O<271> WL_O<270> WL_O<269> WL_O<268> ++ WL_O<267> WL_O<266> WL_O<265> WL_O<264> WL_O<263> WL_O<262> WL_O<261> ++ WL_O<260> WL_O<259> WL_O<258> WL_O<257> WL_O<256> VDD VSS / ++ RM_IHPSG13_256x8_c3_2P_DEC04 +XSEL<15> ADDR_N_I<3> ADDR_N_I<2> ADDR_N_I<1> ADDR_N_I<0> CS00<15> ECLK_H<15> ++ ECLK_H<16> ECLK_B<15> ECLK_B<16> WL_O<255> WL_O<254> WL_O<253> WL_O<252> ++ WL_O<251> WL_O<250> WL_O<249> WL_O<248> WL_O<247> WL_O<246> WL_O<245> ++ WL_O<244> WL_O<243> WL_O<242> WL_O<241> WL_O<240> VDD VSS / ++ RM_IHPSG13_256x8_c3_2P_DEC04 +XSEL<14> ADDR_N_I<3> ADDR_N_I<2> ADDR_N_I<1> ADDR_N_I<0> CS00<14> ECLK_H<14> ++ ECLK_H<15> ECLK_B<14> ECLK_B<15> WL_O<239> WL_O<238> WL_O<237> WL_O<236> ++ WL_O<235> WL_O<234> WL_O<233> WL_O<232> WL_O<231> WL_O<230> WL_O<229> ++ WL_O<228> WL_O<227> WL_O<226> WL_O<225> WL_O<224> VDD VSS / ++ RM_IHPSG13_256x8_c3_2P_DEC04 +XSEL<13> ADDR_N_I<3> ADDR_N_I<2> ADDR_N_I<1> ADDR_N_I<0> CS00<13> ECLK_H<13> ++ ECLK_H<14> ECLK_B<13> ECLK_B<14> WL_O<223> WL_O<222> WL_O<221> WL_O<220> ++ WL_O<219> WL_O<218> WL_O<217> WL_O<216> WL_O<215> WL_O<214> WL_O<213> ++ WL_O<212> WL_O<211> WL_O<210> WL_O<209> WL_O<208> VDD VSS / ++ RM_IHPSG13_256x8_c3_2P_DEC04 +XSEL<12> ADDR_N_I<3> ADDR_N_I<2> ADDR_N_I<1> ADDR_N_I<0> CS00<12> ECLK_H<12> ++ ECLK_H<13> ECLK_B<12> ECLK_B<13> WL_O<207> WL_O<206> WL_O<205> WL_O<204> ++ WL_O<203> WL_O<202> WL_O<201> WL_O<200> WL_O<199> WL_O<198> WL_O<197> ++ WL_O<196> WL_O<195> WL_O<194> WL_O<193> WL_O<192> VDD VSS / ++ RM_IHPSG13_256x8_c3_2P_DEC04 +XSEL<11> ADDR_N_I<3> ADDR_N_I<2> ADDR_N_I<1> ADDR_N_I<0> CS00<11> ECLK_H<11> ++ ECLK_H<12> ECLK_B<11> ECLK_B<12> WL_O<191> WL_O<190> WL_O<189> WL_O<188> ++ WL_O<187> WL_O<186> WL_O<185> WL_O<184> WL_O<183> WL_O<182> WL_O<181> ++ WL_O<180> WL_O<179> WL_O<178> WL_O<177> WL_O<176> VDD VSS / ++ RM_IHPSG13_256x8_c3_2P_DEC04 +XSEL<10> ADDR_N_I<3> ADDR_N_I<2> ADDR_N_I<1> ADDR_N_I<0> CS00<10> ECLK_H<10> ++ ECLK_H<11> ECLK_B<10> ECLK_B<11> WL_O<175> WL_O<174> WL_O<173> WL_O<172> ++ WL_O<171> WL_O<170> WL_O<169> WL_O<168> WL_O<167> WL_O<166> WL_O<165> ++ WL_O<164> WL_O<163> WL_O<162> WL_O<161> WL_O<160> VDD VSS / ++ RM_IHPSG13_256x8_c3_2P_DEC04 +XSEL<9> ADDR_N_I<3> ADDR_N_I<2> ADDR_N_I<1> ADDR_N_I<0> CS00<9> ECLK_H<9> ++ ECLK_H<10> ECLK_B<9> ECLK_B<10> WL_O<159> WL_O<158> WL_O<157> WL_O<156> ++ WL_O<155> WL_O<154> WL_O<153> WL_O<152> WL_O<151> WL_O<150> WL_O<149> ++ WL_O<148> WL_O<147> WL_O<146> WL_O<145> WL_O<144> VDD VSS / ++ RM_IHPSG13_256x8_c3_2P_DEC04 +XSEL<8> ADDR_N_I<3> ADDR_N_I<2> ADDR_N_I<1> ADDR_N_I<0> CS00<8> ECLK_H<8> ++ ECLK_H<9> ECLK_B<8> ECLK_B<9> WL_O<143> WL_O<142> WL_O<141> WL_O<140> ++ WL_O<139> WL_O<138> WL_O<137> WL_O<136> WL_O<135> WL_O<134> WL_O<133> ++ WL_O<132> WL_O<131> WL_O<130> WL_O<129> WL_O<128> VDD VSS / ++ RM_IHPSG13_256x8_c3_2P_DEC04 +XSEL<7> ADDR_N_I<3> ADDR_N_I<2> ADDR_N_I<1> ADDR_N_I<0> CS00<7> ECLK_H<7> ++ ECLK_H<8> ECLK_B<7> ECLK_B<8> WL_O<127> WL_O<126> WL_O<125> WL_O<124> ++ WL_O<123> WL_O<122> WL_O<121> WL_O<120> WL_O<119> WL_O<118> WL_O<117> ++ WL_O<116> WL_O<115> WL_O<114> WL_O<113> WL_O<112> VDD VSS / ++ RM_IHPSG13_256x8_c3_2P_DEC04 +XSEL<6> ADDR_N_I<3> ADDR_N_I<2> ADDR_N_I<1> ADDR_N_I<0> CS00<6> ECLK_H<6> ++ ECLK_H<7> ECLK_B<6> ECLK_B<7> WL_O<111> WL_O<110> WL_O<109> WL_O<108> ++ WL_O<107> WL_O<106> WL_O<105> WL_O<104> WL_O<103> WL_O<102> WL_O<101> ++ WL_O<100> WL_O<99> WL_O<98> WL_O<97> WL_O<96> VDD VSS / ++ RM_IHPSG13_256x8_c3_2P_DEC04 +XSEL<5> ADDR_N_I<3> ADDR_N_I<2> ADDR_N_I<1> ADDR_N_I<0> CS00<5> ECLK_H<5> ++ ECLK_H<6> ECLK_B<5> ECLK_B<6> WL_O<95> WL_O<94> WL_O<93> WL_O<92> WL_O<91> ++ WL_O<90> WL_O<89> WL_O<88> WL_O<87> WL_O<86> WL_O<85> WL_O<84> WL_O<83> ++ WL_O<82> WL_O<81> WL_O<80> VDD VSS / RM_IHPSG13_256x8_c3_2P_DEC04 +XSEL<4> ADDR_N_I<3> ADDR_N_I<2> ADDR_N_I<1> ADDR_N_I<0> CS00<4> ECLK_H<4> ++ ECLK_H<5> ECLK_B<4> ECLK_B<5> WL_O<79> WL_O<78> WL_O<77> WL_O<76> WL_O<75> ++ WL_O<74> WL_O<73> WL_O<72> WL_O<71> WL_O<70> WL_O<69> WL_O<68> WL_O<67> ++ WL_O<66> WL_O<65> WL_O<64> VDD VSS / RM_IHPSG13_256x8_c3_2P_DEC04 +XSEL<3> ADDR_N_I<3> ADDR_N_I<2> ADDR_N_I<1> ADDR_N_I<0> CS00<3> ECLK_H<3> ++ ECLK_H<4> ECLK_B<3> ECLK_B<4> WL_O<63> WL_O<62> WL_O<61> WL_O<60> WL_O<59> ++ WL_O<58> WL_O<57> WL_O<56> WL_O<55> WL_O<54> WL_O<53> WL_O<52> WL_O<51> ++ WL_O<50> WL_O<49> WL_O<48> VDD VSS / RM_IHPSG13_256x8_c3_2P_DEC04 +XSEL<2> ADDR_N_I<3> ADDR_N_I<2> ADDR_N_I<1> ADDR_N_I<0> CS00<2> ECLK_H<2> ++ ECLK_H<3> ECLK_B<2> ECLK_B<3> WL_O<47> WL_O<46> WL_O<45> WL_O<44> WL_O<43> ++ WL_O<42> WL_O<41> WL_O<40> WL_O<39> WL_O<38> WL_O<37> WL_O<36> WL_O<35> ++ WL_O<34> WL_O<33> WL_O<32> VDD VSS / RM_IHPSG13_256x8_c3_2P_DEC04 +XSEL<1> ADDR_N_I<3> ADDR_N_I<2> ADDR_N_I<1> ADDR_N_I<0> CS00<1> ECLK_H<1> ++ ECLK_H<2> ECLK_B<1> ECLK_B<2> WL_O<31> WL_O<30> WL_O<29> WL_O<28> WL_O<27> ++ WL_O<26> WL_O<25> WL_O<24> WL_O<23> WL_O<22> WL_O<21> WL_O<20> WL_O<19> ++ WL_O<18> WL_O<17> WL_O<16> VDD VSS / RM_IHPSG13_256x8_c3_2P_DEC04 +XSEL<0> ADDR_N_I<3> ADDR_N_I<2> ADDR_N_I<1> ADDR_N_I<0> CS00<0> ECLK_I ++ ECLK_H<1> ECLK_B<0> ECLK_B<1> WL_O<15> WL_O<14> WL_O<13> WL_O<12> WL_O<11> ++ WL_O<10> WL_O<9> WL_O<8> WL_O<7> WL_O<6> WL_O<5> WL_O<4> WL_O<3> WL_O<2> ++ WL_O<1> WL_O<0> VDD VSS / RM_IHPSG13_256x8_c3_2P_DEC04 +XDEC10<9> ADDR_N_I<7> ADDR_N_I<6> CS04<1> CS02<6> VDD VSS / ++ RM_IHPSG13_256x8_c3_2P_DEC02 +XDEC10<8> ADDR_N_I<7> ADDR_N_I<6> CS04<0> CS02<2> VDD VSS / ++ RM_IHPSG13_256x8_c3_2P_DEC02 +XDEC10<7> ADDR_N_I<5> ADDR_N_I<4> CS02<7> CS00<30> VDD VSS / ++ RM_IHPSG13_256x8_c3_2P_DEC02 +XDEC10<6> ADDR_N_I<5> ADDR_N_I<4> CS02<6> CS00<26> VDD VSS / ++ RM_IHPSG13_256x8_c3_2P_DEC02 +XDEC10<5> ADDR_N_I<5> ADDR_N_I<4> CS02<5> CS00<22> VDD VSS / ++ RM_IHPSG13_256x8_c3_2P_DEC02 +XDEC10<4> ADDR_N_I<5> ADDR_N_I<4> CS02<4> CS00<18> VDD VSS / ++ RM_IHPSG13_256x8_c3_2P_DEC02 +XDEC10<3> ADDR_N_I<5> ADDR_N_I<4> CS02<3> CS00<14> VDD VSS / ++ RM_IHPSG13_256x8_c3_2P_DEC02 +XDEC10<2> ADDR_N_I<5> ADDR_N_I<4> CS02<2> CS00<10> VDD VSS / ++ RM_IHPSG13_256x8_c3_2P_DEC02 +XDEC10<1> ADDR_N_I<5> ADDR_N_I<4> CS02<1> CS00<6> VDD VSS / ++ RM_IHPSG13_256x8_c3_2P_DEC02 +XDEC10<0> ADDR_N_I<5> ADDR_N_I<4> CS02<0> CS00<2> VDD VSS / ++ RM_IHPSG13_256x8_c3_2P_DEC02 +XDEC01<10> ADDR_N_I<9> ADDR_N_I<8> CS_I CS04<1> VDD VSS / ++ RM_IHPSG13_256x8_c3_2P_DEC01 +XDEC01<9> ADDR_N_I<7> ADDR_N_I<6> CS04<1> CS02<5> VDD VSS / ++ RM_IHPSG13_256x8_c3_2P_DEC01 +XDEC01<8> ADDR_N_I<7> ADDR_N_I<6> CS04<0> CS02<1> VDD VSS / ++ RM_IHPSG13_256x8_c3_2P_DEC01 +XDEC01<7> ADDR_N_I<5> ADDR_N_I<4> CS02<7> CS00<29> VDD VSS / ++ RM_IHPSG13_256x8_c3_2P_DEC01 +XDEC01<6> ADDR_N_I<5> ADDR_N_I<4> CS02<6> CS00<25> VDD VSS / ++ RM_IHPSG13_256x8_c3_2P_DEC01 +XDEC01<5> ADDR_N_I<5> ADDR_N_I<4> CS02<5> CS00<21> VDD VSS / ++ RM_IHPSG13_256x8_c3_2P_DEC01 +XDEC01<4> ADDR_N_I<5> ADDR_N_I<4> CS02<4> CS00<17> VDD VSS / ++ RM_IHPSG13_256x8_c3_2P_DEC01 +XDEC01<3> ADDR_N_I<5> ADDR_N_I<4> CS02<3> CS00<13> VDD VSS / ++ RM_IHPSG13_256x8_c3_2P_DEC01 +XDEC01<2> ADDR_N_I<5> ADDR_N_I<4> CS02<2> CS00<9> VDD VSS / ++ RM_IHPSG13_256x8_c3_2P_DEC01 +XDEC01<1> ADDR_N_I<5> ADDR_N_I<4> CS02<1> CS00<5> VDD VSS / ++ RM_IHPSG13_256x8_c3_2P_DEC01 +XDEC01<0> ADDR_N_I<5> ADDR_N_I<4> CS02<0> CS00<1> VDD VSS / ++ RM_IHPSG13_256x8_c3_2P_DEC01 +XL2<258> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<257> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<256> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<255> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<254> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<253> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<252> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<251> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<250> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<249> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<248> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<247> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<246> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<245> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<244> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<243> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<242> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<241> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<240> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<239> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<238> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<237> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<236> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<235> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<234> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<233> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<232> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<231> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<230> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<229> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<228> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<227> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<226> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<225> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<224> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<223> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<222> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<221> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<220> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<219> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<218> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<217> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<216> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<215> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<214> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<213> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<212> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<211> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<210> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<209> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<208> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<207> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<206> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<205> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<204> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<203> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<202> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<201> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<200> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<199> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<198> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<197> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<196> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<195> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<194> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<193> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<192> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<191> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<190> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<189> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<188> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<187> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<186> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<185> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<184> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<183> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<182> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<181> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<180> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<179> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<178> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<177> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<176> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<175> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<174> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<173> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<172> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<171> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<170> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<169> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<168> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<167> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<166> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<165> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<164> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<163> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<162> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<161> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<160> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<159> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<158> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<157> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<156> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<155> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<154> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<153> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<152> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<151> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<150> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<149> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<148> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<147> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<146> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<145> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<144> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<143> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<142> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<141> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<140> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<139> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<138> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<137> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<136> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<135> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<134> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<133> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<132> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<131> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<130> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<129> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<128> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<127> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<126> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<125> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<124> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<123> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<122> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<121> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<120> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<119> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<118> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<117> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<116> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<115> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<114> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<113> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<112> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<111> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<110> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<109> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<108> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<107> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<106> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<105> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<104> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<103> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<102> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<101> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<100> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<99> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<98> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<97> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<96> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<95> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<94> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<93> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<92> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<91> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<90> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<89> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<88> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<87> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<86> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<85> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<84> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<83> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<82> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<81> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<80> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<79> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<78> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<77> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<76> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<75> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<74> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<73> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<72> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<71> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<70> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<69> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<68> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<67> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<66> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<65> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<64> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<63> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<62> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<61> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<60> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<59> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<58> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<57> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<56> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<55> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<54> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<53> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<52> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<51> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<50> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<49> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<48> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<47> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<46> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<45> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<44> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<43> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<42> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<41> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<40> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<39> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<38> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<37> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<36> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<35> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<34> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<33> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<32> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<31> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<30> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<29> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<28> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<27> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<26> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<25> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<24> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<23> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<22> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<21> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<20> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<19> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<18> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<17> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<16> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<15> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<14> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<13> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<12> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<11> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<10> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<9> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<8> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<7> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<6> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<5> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<4> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<3> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<2> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<1> VDD VSS / RSC_IHPSG13_FILLCAP8 +XDEC00<10> ADDR_N_I<9> ADDR_N_I<8> CS_I CS04<0> VDD VSS / ++ RM_IHPSG13_256x8_c3_2P_DEC00 +XDEC00<9> ADDR_N_I<7> ADDR_N_I<6> CS04<1> CS02<4> VDD VSS / ++ RM_IHPSG13_256x8_c3_2P_DEC00 +XDEC00<8> ADDR_N_I<7> ADDR_N_I<6> CS04<0> CS02<0> VDD VSS / ++ RM_IHPSG13_256x8_c3_2P_DEC00 +XDEC00<7> ADDR_N_I<5> ADDR_N_I<4> CS02<7> CS00<28> VDD VSS / ++ RM_IHPSG13_256x8_c3_2P_DEC00 +XDEC00<6> ADDR_N_I<5> ADDR_N_I<4> CS02<6> CS00<24> VDD VSS / ++ RM_IHPSG13_256x8_c3_2P_DEC00 +XDEC00<5> ADDR_N_I<5> ADDR_N_I<4> CS02<5> CS00<20> VDD VSS / ++ RM_IHPSG13_256x8_c3_2P_DEC00 +XDEC00<4> ADDR_N_I<5> ADDR_N_I<4> CS02<4> CS00<16> VDD VSS / ++ RM_IHPSG13_256x8_c3_2P_DEC00 +XDEC00<3> ADDR_N_I<5> ADDR_N_I<4> CS02<3> CS00<12> VDD VSS / ++ RM_IHPSG13_256x8_c3_2P_DEC00 +XDEC00<2> ADDR_N_I<5> ADDR_N_I<4> CS02<2> CS00<8> VDD VSS / ++ RM_IHPSG13_256x8_c3_2P_DEC00 +XDEC00<1> ADDR_N_I<5> ADDR_N_I<4> CS02<1> CS00<4> VDD VSS / ++ RM_IHPSG13_256x8_c3_2P_DEC00 +XDEC00<0> ADDR_N_I<5> ADDR_N_I<4> CS02<0> CS00<0> VDD VSS / ++ RM_IHPSG13_256x8_c3_2P_DEC00 +XDEC11<9> ADDR_N_I<7> ADDR_N_I<6> CS04<1> CS02<7> VDD VSS / ++ RM_IHPSG13_256x8_c3_2P_DEC03 +XDEC11<8> ADDR_N_I<7> ADDR_N_I<6> CS04<0> CS02<3> VDD VSS / ++ RM_IHPSG13_256x8_c3_2P_DEC03 +XDEC11<7> ADDR_N_I<5> ADDR_N_I<4> CS02<7> CS00<31> VDD VSS / ++ RM_IHPSG13_256x8_c3_2P_DEC03 +XDEC11<6> ADDR_N_I<5> ADDR_N_I<4> CS02<6> CS00<27> VDD VSS / ++ RM_IHPSG13_256x8_c3_2P_DEC03 +XDEC11<5> ADDR_N_I<5> ADDR_N_I<4> CS02<5> CS00<23> VDD VSS / ++ RM_IHPSG13_256x8_c3_2P_DEC03 +XDEC11<4> ADDR_N_I<5> ADDR_N_I<4> CS02<4> CS00<19> VDD VSS / ++ RM_IHPSG13_256x8_c3_2P_DEC03 +XDEC11<3> ADDR_N_I<5> ADDR_N_I<4> CS02<3> CS00<15> VDD VSS / ++ RM_IHPSG13_256x8_c3_2P_DEC03 +XDEC11<2> ADDR_N_I<5> ADDR_N_I<4> CS02<2> CS00<11> VDD VSS / ++ RM_IHPSG13_256x8_c3_2P_DEC03 +XDEC11<1> ADDR_N_I<5> ADDR_N_I<4> CS02<1> CS00<7> VDD VSS / ++ RM_IHPSG13_256x8_c3_2P_DEC03 +XDEC11<0> ADDR_N_I<5> ADDR_N_I<4> CS02<0> CS00<3> VDD VSS / ++ RM_IHPSG13_256x8_c3_2P_DEC03 +XI0 ADDR_N_I<9> VDD VSS / RSC_IHPSG13_TIEL +.ENDS +.SUBCKT RM_IHPSG13_256x8_c3_2P_ROWREG9 ACLK_N_I ADDR_I<8> ADDR_I<7> ADDR_I<6> ADDR_I<5> ++ ADDR_I<4> ADDR_I<3> ADDR_I<2> ADDR_I<1> ADDR_I<0> ADDR_N_O<8> ADDR_N_O<7> ++ ADDR_N_O<6> ADDR_N_O<5> ADDR_N_O<4> ADDR_N_O<3> ADDR_N_O<2> ADDR_N_O<1> ++ ADDR_N_O<0> BIST_ADDR_I<8> BIST_ADDR_I<7> BIST_ADDR_I<6> BIST_ADDR_I<5> ++ BIST_ADDR_I<4> BIST_ADDR_I<3> BIST_ADDR_I<2> BIST_ADDR_I<1> BIST_ADDR_I<0> ++ BIST_EN_I VDD VSS +XDFF<8> BIST_EN_I BIST_ADDR_I<8> ACLK_N_I ADDR_I<8> q_int<8> net04<0> VDD ++ VSS / RSC_IHPSG13_DFNQMX2IX1 +XDFF<7> BIST_EN_I BIST_ADDR_I<7> ACLK_N_I ADDR_I<7> q_int<7> net04<1> VDD ++ VSS / RSC_IHPSG13_DFNQMX2IX1 +XDFF<6> BIST_EN_I BIST_ADDR_I<6> ACLK_N_I ADDR_I<6> q_int<6> net04<2> VDD ++ VSS / RSC_IHPSG13_DFNQMX2IX1 +XDFF<5> BIST_EN_I BIST_ADDR_I<5> ACLK_N_I ADDR_I<5> q_int<5> net04<3> VDD ++ VSS / RSC_IHPSG13_DFNQMX2IX1 +XDFF<4> BIST_EN_I BIST_ADDR_I<4> ACLK_N_I ADDR_I<4> q_int<4> net04<4> VDD ++ VSS / RSC_IHPSG13_DFNQMX2IX1 +XDFF<3> BIST_EN_I BIST_ADDR_I<3> ACLK_N_I ADDR_I<3> q_int<3> net04<5> VDD ++ VSS / RSC_IHPSG13_DFNQMX2IX1 +XDFF<2> BIST_EN_I BIST_ADDR_I<2> ACLK_N_I ADDR_I<2> q_int<2> net04<6> VDD ++ VSS / RSC_IHPSG13_DFNQMX2IX1 +XDFF<1> BIST_EN_I BIST_ADDR_I<1> ACLK_N_I ADDR_I<1> q_int<1> net04<7> VDD ++ VSS / RSC_IHPSG13_DFNQMX2IX1 +XDFF<0> BIST_EN_I BIST_ADDR_I<0> ACLK_N_I ADDR_I<0> q_int<0> net04<8> VDD ++ VSS / RSC_IHPSG13_DFNQMX2IX1 +XDRV<8> qn_int<8> ADDR_N_O<8> VDD VSS / RSC_IHPSG13_CINVX8 +XDRV<7> qn_int<7> ADDR_N_O<7> VDD VSS / RSC_IHPSG13_CINVX8 +XDRV<6> qn_int<6> ADDR_N_O<6> VDD VSS / RSC_IHPSG13_CINVX8 +XDRV<5> qn_int<5> ADDR_N_O<5> VDD VSS / RSC_IHPSG13_CINVX8 +XDRV<4> qn_int<4> ADDR_N_O<4> VDD VSS / RSC_IHPSG13_CINVX8 +XDRV<3> qn_int<3> ADDR_N_O<3> VDD VSS / RSC_IHPSG13_CINVX8 +XDRV<2> qn_int<2> ADDR_N_O<2> VDD VSS / RSC_IHPSG13_CINVX8 +XDRV<1> qn_int<1> ADDR_N_O<1> VDD VSS / RSC_IHPSG13_CINVX8 +XDRV<0> qn_int<0> ADDR_N_O<0> VDD VSS / RSC_IHPSG13_CINVX8 +XINV<8> q_int<8> qn_int<8> VDD VSS / RSC_IHPSG13_CINVX2 +XINV<7> q_int<7> qn_int<7> VDD VSS / RSC_IHPSG13_CINVX2 +XINV<6> q_int<6> qn_int<6> VDD VSS / RSC_IHPSG13_CINVX2 +XINV<5> q_int<5> qn_int<5> VDD VSS / RSC_IHPSG13_CINVX2 +XINV<4> q_int<4> qn_int<4> VDD VSS / RSC_IHPSG13_CINVX2 +XINV<3> q_int<3> qn_int<3> VDD VSS / RSC_IHPSG13_CINVX2 +XINV<2> q_int<2> qn_int<2> VDD VSS / RSC_IHPSG13_CINVX2 +XINV<1> q_int<1> qn_int<1> VDD VSS / RSC_IHPSG13_CINVX2 +XINV<0> q_int<0> qn_int<0> VDD VSS / RSC_IHPSG13_CINVX2 +.ENDS + +.SUBCKT RM_IHPSG13_256x8_c3_2P_DLY_MUX A SEL Z VDD VSS +XI11 net4 Z VDD VSS / RSC_IHPSG13_CINVX2 +XI8 A D<3> SEL net4 VDD VSS / RSC_IHPSG13_MX2IX1 +XI20<3> D<2> D<3> VDD VSS / RSC_IHPSG13_CDLYX1 +XI20<2> D<1> D<2> VDD VSS / RSC_IHPSG13_CDLYX1 +XI20<1> A D<1> VDD VSS / RSC_IHPSG13_CDLYX1 +.ENDS +.SUBCKT RM_IHPSG13_256x8_c3_2P_CTRL ACLK_N BIST_CK_I BIST_CS_I BIST_EN BIST_RE_I ++ BIST_WE_I B_TIEL_O CK_I CS_I DCLK ECLK PULSE_H PULSE_L PULSE_O RCLK RE_I ++ ROW_CS WCLK WE_I VDD VSS +XI17 ck_regs we col_we VDD VSS / RSC_IHPSG13_DFNQX2 +XI16 ck_regs re col_re VDD VSS / RSC_IHPSG13_DFNQX2 +XI18 ck_regs cs net7 VDD VSS / RSC_IHPSG13_DFNQX2 +XI71 ACLK_N net012 PULSE_O VDD VSS / RSC_IHPSG13_DFNQX2 +XI77 col_we net017 net016 VDD VSS / RSC_IHPSG13_CNAND2X2 +XI76 col_re net017 net018 VDD VSS / RSC_IHPSG13_CNAND2X2 +XI15 ck_dly WEorREandCS aclk VDD VSS / RSC_IHPSG13_CGATEPX4 +XI14 ck WEandCS DCLK VDD VSS / RSC_IHPSG13_CGATEPX4 +XI60 net7 ROW_CS VDD VSS / RSC_IHPSG13_CBUFX8 +XI73 PULSE_O net012 VDD VSS / RSC_IHPSG13_CINVX2 +XI8 net017 net8 VDD VSS / RSC_IHPSG13_CINVX2 +XCAPS4<7> VDD VSS / RSC_IHPSG13_FILLCAP4 +XCAPS4<6> VDD VSS / RSC_IHPSG13_FILLCAP4 +XCAPS4<5> VDD VSS / RSC_IHPSG13_FILLCAP4 +XCAPS4<4> VDD VSS / RSC_IHPSG13_FILLCAP4 +XCAPS4<3> VDD VSS / RSC_IHPSG13_FILLCAP4 +XCAPS4<2> VDD VSS / RSC_IHPSG13_FILLCAP4 +XCAPS4<1> VDD VSS / RSC_IHPSG13_FILLCAP4 +XBM_TIEL B_TIEL_O VDD VSS / RSC_IHPSG13_TIEL +XI64 ck ck_dly VDD VSS / RSC_IHPSG13_CDLYX2 +XI86 CS_I BIST_CS_I BIST_EN cs VDD VSS / RSC_IHPSG13_MX2X2 +XI87 CK_I BIST_CK_I BIST_EN ck VDD VSS / RSC_IHPSG13_MX2X2 +XI85 WE_I BIST_WE_I BIST_EN we VDD VSS / RSC_IHPSG13_MX2X2 +XI84 RE_I BIST_RE_I BIST_EN re VDD VSS / RSC_IHPSG13_MX2X2 +XI48 ck_dly ck_regs VDD VSS / RSC_IHPSG13_CINVX4 +XI81 net016 WCLK VDD VSS / RSC_IHPSG13_CINVX4 +XI80 net018 RCLK VDD VSS / RSC_IHPSG13_CINVX4 +XI78 net8 net020 VDD VSS / RSC_IHPSG13_CINVX4 +XCAPS8<7> VDD VSS / RSC_IHPSG13_FILLCAP8 +XCAPS8<6> VDD VSS / RSC_IHPSG13_FILLCAP8 +XCAPS8<5> VDD VSS / RSC_IHPSG13_FILLCAP8 +XCAPS8<4> VDD VSS / RSC_IHPSG13_FILLCAP8 +XCAPS8<3> VDD VSS / RSC_IHPSG13_FILLCAP8 +XCAPS8<2> VDD VSS / RSC_IHPSG13_FILLCAP8 +XCAPS8<1> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI6 PULSE_L PULSE_H net017 VDD VSS / RSC_IHPSG13_XOR2X2 +XI22 we cs WEandCS VDD VSS / RSC_IHPSG13_AND2X2 +XI79 net020 ECLK VDD VSS / RSC_IHPSG13_CINVX8 +XI63 aclk ACLK_N VDD VSS / RSC_IHPSG13_CINVX8 +XI21 re we cs WEorREandCS VDD VSS / RSC_IHPSG13_OA12X1 +.ENDS +.SUBCKT RM_IHPSG13_256x8_c3_2P_COLDEC5 ACLK_N ADDR<4> ADDR<3> ADDR<2> ADDR<1> ADDR<0> ++ ADDR_COL<1> ADDR_COL<0> ADDR_DEC<7> ADDR_DEC<6> ADDR_DEC<5> ADDR_DEC<4> ++ ADDR_DEC<3> ADDR_DEC<2> ADDR_DEC<1> ADDR_DEC<0> BIST_ADDR<4> BIST_ADDR<3> ++ BIST_ADDR<2> BIST_ADDR<1> BIST_ADDR<0> BIST_EN_I VDD VSS +XI17<4> VDD VSS / RSC_IHPSG13_FILLCAP4 +XI17<3> VDD VSS / RSC_IHPSG13_FILLCAP4 +XI17<2> VDD VSS / RSC_IHPSG13_FILLCAP4 +XI17<1> VDD VSS / RSC_IHPSG13_FILLCAP4 +XI1<7> PADR<0> PADR<1> PADR<2> addr_n<7> VDD VSS / RSC_IHPSG13_NAND3X2 +XI1<6> NADR<0> PADR<1> PADR<2> addr_n<6> VDD VSS / RSC_IHPSG13_NAND3X2 +XI1<5> PADR<0> NADR<1> PADR<2> addr_n<5> VDD VSS / RSC_IHPSG13_NAND3X2 +XI1<4> NADR<0> NADR<1> PADR<2> addr_n<4> VDD VSS / RSC_IHPSG13_NAND3X2 +XI1<3> PADR<0> PADR<1> NADR<2> addr_n<3> VDD VSS / RSC_IHPSG13_NAND3X2 +XI1<2> NADR<0> PADR<1> NADR<2> addr_n<2> VDD VSS / RSC_IHPSG13_NAND3X2 +XI1<1> PADR<0> NADR<1> NADR<2> addr_n<1> VDD VSS / RSC_IHPSG13_NAND3X2 +XI1<0> NADR<0> NADR<1> NADR<2> addr_n<0> VDD VSS / RSC_IHPSG13_NAND3X2 +XDFF<4> BIST_EN_I BIST_ADDR<4> ACLK_N ADDR<4> addr_int<1> net13<0> VDD ++ VSS / RSC_IHPSG13_DFNQMX2IX1 +XDFF<3> BIST_EN_I BIST_ADDR<3> ACLK_N ADDR<3> addr_int<0> net13<1> VDD ++ VSS / RSC_IHPSG13_DFNQMX2IX1 +XDFF<2> BIST_EN_I BIST_ADDR<2> ACLK_N ADDR<2> padr_int<2> net13<2> VDD ++ VSS / RSC_IHPSG13_DFNQMX2IX1 +XDFF<1> BIST_EN_I BIST_ADDR<1> ACLK_N ADDR<1> padr_int<1> net13<3> VDD ++ VSS / RSC_IHPSG13_DFNQMX2IX1 +XDFF<0> BIST_EN_I BIST_ADDR<0> ACLK_N ADDR<0> padr_int<0> net13<4> VDD ++ VSS / RSC_IHPSG13_DFNQMX2IX1 +XI3<2> padr_int<2> NADR<2> VDD VSS / RSC_IHPSG13_INVX2 +XI3<1> padr_int<1> NADR<1> VDD VSS / RSC_IHPSG13_INVX2 +XI3<0> padr_int<0> NADR<0> VDD VSS / RSC_IHPSG13_INVX2 +XI2<7> addr_n<7> ADDR_DEC<7> VDD VSS / RSC_IHPSG13_INVX2 +XI2<6> addr_n<6> ADDR_DEC<6> VDD VSS / RSC_IHPSG13_INVX2 +XI2<5> addr_n<5> ADDR_DEC<5> VDD VSS / RSC_IHPSG13_INVX2 +XI2<4> addr_n<4> ADDR_DEC<4> VDD VSS / RSC_IHPSG13_INVX2 +XI2<3> addr_n<3> ADDR_DEC<3> VDD VSS / RSC_IHPSG13_INVX2 +XI2<2> addr_n<2> ADDR_DEC<2> VDD VSS / RSC_IHPSG13_INVX2 +XI2<1> addr_n<1> ADDR_DEC<1> VDD VSS / RSC_IHPSG13_INVX2 +XI2<0> addr_n<0> ADDR_DEC<0> VDD VSS / RSC_IHPSG13_INVX2 +XI15<2> NADR<2> PADR<2> VDD VSS / RSC_IHPSG13_INVX2 +XI15<1> NADR<1> PADR<1> VDD VSS / RSC_IHPSG13_INVX2 +XI15<0> NADR<0> PADR<0> VDD VSS / RSC_IHPSG13_INVX2 +XI13<1> addr_int<1> ADDR_COL<1> VDD VSS / RSC_IHPSG13_CBUFX2 +XI13<0> addr_int<0> ADDR_COL<0> VDD VSS / RSC_IHPSG13_CBUFX2 +XI14<5> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI14<4> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI14<3> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI14<2> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI14<1> VDD VSS / RSC_IHPSG13_FILLCAP8 +.ENDS +.SUBCKT RM_IHPSG13_256x8_c3_2P_BLDRV A_BLC<3> A_BLC<2> A_BLC<1> A_BLC<0> A_BLC_SEL ++ A_BLT<3> A_BLT<2> A_BLT<1> A_BLT<0> A_BLT_SEL A_PRE_N A_SEL_P<3> A_SEL_P<2> ++ A_SEL_P<1> A_SEL_P<0> A_WR_ONE A_WR_ZERO B_BLC<3> B_BLC<2> B_BLC<1> B_BLC<0> ++ B_BLC_SEL B_BLT<3> B_BLT<2> B_BLT<1> B_BLT<0> B_BLT_SEL B_PRE_N B_SEL_P<3> ++ B_SEL_P<2> B_SEL_P<1> B_SEL_P<0> B_WR_ONE B_WR_ZERO VDD VSS +MA_CWN<3> A_BLC<3> A_BLC_NMOS_DRIVE<3> VSS VSS sg13_lv_nmos m=1 ++ w=4.82u l=130.00n ng=2 nrd=0 nrs=0 +MA_CWN<2> A_BLC<2> A_BLC_NMOS_DRIVE<2> VSS VSS sg13_lv_nmos m=1 ++ w=4.82u l=130.00n ng=2 nrd=0 nrs=0 +MA_CWN<1> A_BLC<1> A_BLC_NMOS_DRIVE<1> VSS VSS sg13_lv_nmos m=1 ++ w=4.82u l=130.00n ng=2 nrd=0 nrs=0 +MA_CWN<0> A_BLC<0> A_BLC_NMOS_DRIVE<0> VSS VSS sg13_lv_nmos m=1 ++ w=4.82u l=130.00n ng=2 nrd=0 nrs=0 +MA_TWN<3> A_BLT<3> A_BLT_NMOS_DRIVE<3> VSS VSS sg13_lv_nmos m=1 ++ w=4.82u l=130.00n ng=2 nrd=0 nrs=0 +MA_TWN<2> A_BLT<2> A_BLT_NMOS_DRIVE<2> VSS VSS sg13_lv_nmos m=1 ++ w=4.82u l=130.00n ng=2 nrd=0 nrs=0 +MA_TWN<1> A_BLT<1> A_BLT_NMOS_DRIVE<1> VSS VSS sg13_lv_nmos m=1 ++ w=4.82u l=130.00n ng=2 nrd=0 nrs=0 +MA_TWN<0> A_BLT<0> A_BLT_NMOS_DRIVE<0> VSS VSS sg13_lv_nmos m=1 ++ w=4.82u l=130.00n ng=2 nrd=0 nrs=0 +MB_TWN<3> B_BLT<3> B_BLT_NMOS_DRIVE<3> VSS VSS sg13_lv_nmos m=1 ++ w=4.82u l=130.00n ng=2 nrd=0 nrs=0 +MB_TWN<2> B_BLT<2> B_BLT_NMOS_DRIVE<2> VSS VSS sg13_lv_nmos m=1 ++ w=4.82u l=130.00n ng=2 nrd=0 nrs=0 +MB_TWN<1> B_BLT<1> B_BLT_NMOS_DRIVE<1> VSS VSS sg13_lv_nmos m=1 ++ w=4.82u l=130.00n ng=2 nrd=0 nrs=0 +MB_TWN<0> B_BLT<0> B_BLT_NMOS_DRIVE<0> VSS VSS sg13_lv_nmos m=1 ++ w=4.82u l=130.00n ng=2 nrd=0 nrs=0 +MB_CWN<3> B_BLC<3> B_BLC_NMOS_DRIVE<3> VSS VSS sg13_lv_nmos m=1 ++ w=4.82u l=130.00n ng=2 nrd=0 nrs=0 +MB_CWN<2> B_BLC<2> B_BLC_NMOS_DRIVE<2> VSS VSS sg13_lv_nmos m=1 ++ w=4.82u l=130.00n ng=2 nrd=0 nrs=0 +MB_CWN<1> B_BLC<1> B_BLC_NMOS_DRIVE<1> VSS VSS sg13_lv_nmos m=1 ++ w=4.82u l=130.00n ng=2 nrd=0 nrs=0 +MB_CWN<0> B_BLC<0> B_BLC_NMOS_DRIVE<0> VSS VSS sg13_lv_nmos m=1 ++ w=4.82u l=130.00n ng=2 nrd=0 nrs=0 +MA_CPR<3> A_BLC<3> A_PRE_N VDD VDD sg13_lv_pmos m=1 w=3.000u l=130.00n ++ ng=2 nrd=0 nrs=0 +MA_CPR<2> A_BLC<2> A_PRE_N VDD VDD sg13_lv_pmos m=1 w=3.000u l=130.00n ++ ng=2 nrd=0 nrs=0 +MA_CPR<1> A_BLC<1> A_PRE_N VDD VDD sg13_lv_pmos m=1 w=3.000u l=130.00n ++ ng=2 nrd=0 nrs=0 +MA_CPR<0> A_BLC<0> A_PRE_N VDD VDD sg13_lv_pmos m=1 w=3.000u l=130.00n ++ ng=2 nrd=0 nrs=0 +MA_TWP<3> A_BLT<3> A_BLT_PMOS_DRIVE<3> VDD VDD sg13_lv_pmos m=1 w=1.5u ++ l=130.00n ng=1 nrd=0 nrs=0 +MA_TWP<2> A_BLT<2> A_BLT_PMOS_DRIVE<2> VDD VDD sg13_lv_pmos m=1 w=1.5u ++ l=130.00n ng=1 nrd=0 nrs=0 +MA_TWP<1> A_BLT<1> A_BLT_PMOS_DRIVE<1> VDD VDD sg13_lv_pmos m=1 w=1.5u ++ l=130.00n ng=1 nrd=0 nrs=0 +MA_TWP<0> A_BLT<0> A_BLT_PMOS_DRIVE<0> VDD VDD sg13_lv_pmos m=1 w=1.5u ++ l=130.00n ng=1 nrd=0 nrs=0 +MA_CWP<3> A_BLC<3> A_BLC_PMOS_DRIVE<3> VDD VDD sg13_lv_pmos m=1 w=1.5u ++ l=130.00n ng=1 nrd=0 nrs=0 +MA_CWP<2> A_BLC<2> A_BLC_PMOS_DRIVE<2> VDD VDD sg13_lv_pmos m=1 w=1.5u ++ l=130.00n ng=1 nrd=0 nrs=0 +MA_CWP<1> A_BLC<1> A_BLC_PMOS_DRIVE<1> VDD VDD sg13_lv_pmos m=1 w=1.5u ++ l=130.00n ng=1 nrd=0 nrs=0 +MA_CWP<0> A_BLC<0> A_BLC_PMOS_DRIVE<0> VDD VDD sg13_lv_pmos m=1 w=1.5u ++ l=130.00n ng=1 nrd=0 nrs=0 +MA_TPR<3> A_BLT<3> A_PRE_N VDD VDD sg13_lv_pmos m=1 w=3.000u l=130.00n ++ ng=2 nrd=0 nrs=0 +MA_TPR<2> A_BLT<2> A_PRE_N VDD VDD sg13_lv_pmos m=1 w=3.000u l=130.00n ++ ng=2 nrd=0 nrs=0 +MA_TPR<1> A_BLT<1> A_PRE_N VDD VDD sg13_lv_pmos m=1 w=3.000u l=130.00n ++ ng=2 nrd=0 nrs=0 +MA_TPR<0> A_BLT<0> A_PRE_N VDD VDD sg13_lv_pmos m=1 w=3.000u l=130.00n ++ ng=2 nrd=0 nrs=0 +MA_TSP<3> A_BLT_SEL A_SEL_N<3> A_BLT<3> VDD sg13_lv_pmos m=1 w=1.5u ++ l=130.00n ng=1 nrd=0 nrs=0 +MA_TSP<2> A_BLT_SEL A_SEL_N<2> A_BLT<2> VDD sg13_lv_pmos m=1 w=1.5u ++ l=130.00n ng=1 nrd=0 nrs=0 +MA_TSP<1> A_BLT_SEL A_SEL_N<1> A_BLT<1> VDD sg13_lv_pmos m=1 w=1.5u ++ l=130.00n ng=1 nrd=0 nrs=0 +MA_TSP<0> A_BLT_SEL A_SEL_N<0> A_BLT<0> VDD sg13_lv_pmos m=1 w=1.5u ++ l=130.00n ng=1 nrd=0 nrs=0 +MA_CSP<3> A_BLC_SEL A_SEL_N<3> A_BLC<3> VDD sg13_lv_pmos m=1 w=1.5u ++ l=130.00n ng=1 nrd=0 nrs=0 +MA_CSP<2> A_BLC_SEL A_SEL_N<2> A_BLC<2> VDD sg13_lv_pmos m=1 w=1.5u ++ l=130.00n ng=1 nrd=0 nrs=0 +MA_CSP<1> A_BLC_SEL A_SEL_N<1> A_BLC<1> VDD sg13_lv_pmos m=1 w=1.5u ++ l=130.00n ng=1 nrd=0 nrs=0 +MA_CSP<0> A_BLC_SEL A_SEL_N<0> A_BLC<0> VDD sg13_lv_pmos m=1 w=1.5u ++ l=130.00n ng=1 nrd=0 nrs=0 +MB_CWP<3> B_BLC<3> B_BLC_PMOS_DRIVE<3> VDD VDD sg13_lv_pmos m=1 w=1.5u ++ l=130.00n ng=1 nrd=0 nrs=0 +MB_CWP<2> B_BLC<2> B_BLC_PMOS_DRIVE<2> VDD VDD sg13_lv_pmos m=1 w=1.5u ++ l=130.00n ng=1 nrd=0 nrs=0 +MB_CWP<1> B_BLC<1> B_BLC_PMOS_DRIVE<1> VDD VDD sg13_lv_pmos m=1 w=1.5u ++ l=130.00n ng=1 nrd=0 nrs=0 +MB_CWP<0> B_BLC<0> B_BLC_PMOS_DRIVE<0> VDD VDD sg13_lv_pmos m=1 w=1.5u ++ l=130.00n ng=1 nrd=0 nrs=0 +MB_TWP<3> B_BLT<3> B_BLT_PMOS_DRIVE<3> VDD VDD sg13_lv_pmos m=1 w=1.5u ++ l=130.00n ng=1 nrd=0 nrs=0 +MB_TWP<2> B_BLT<2> B_BLT_PMOS_DRIVE<2> VDD VDD sg13_lv_pmos m=1 w=1.5u ++ l=130.00n ng=1 nrd=0 nrs=0 +MB_TWP<1> B_BLT<1> B_BLT_PMOS_DRIVE<1> VDD VDD sg13_lv_pmos m=1 w=1.5u ++ l=130.00n ng=1 nrd=0 nrs=0 +MB_TWP<0> B_BLT<0> B_BLT_PMOS_DRIVE<0> VDD VDD sg13_lv_pmos m=1 w=1.5u ++ l=130.00n ng=1 nrd=0 nrs=0 +MB_TSP<3> B_BLT_SEL B_SEL_N<3> B_BLT<3> VDD sg13_lv_pmos m=1 w=1.5u ++ l=130.00n ng=1 nrd=0 nrs=0 +MB_TSP<2> B_BLT_SEL B_SEL_N<2> B_BLT<2> VDD sg13_lv_pmos m=1 w=1.5u ++ l=130.00n ng=1 nrd=0 nrs=0 +MB_TSP<1> B_BLT_SEL B_SEL_N<1> B_BLT<1> VDD sg13_lv_pmos m=1 w=1.5u ++ l=130.00n ng=1 nrd=0 nrs=0 +MB_TSP<0> B_BLT_SEL B_SEL_N<0> B_BLT<0> VDD sg13_lv_pmos m=1 w=1.5u ++ l=130.00n ng=1 nrd=0 nrs=0 +MB_TPR<3> B_BLT<3> B_PRE_N VDD VDD sg13_lv_pmos m=1 w=3.000u l=130.00n ++ ng=2 nrd=0 nrs=0 +MB_TPR<2> B_BLT<2> B_PRE_N VDD VDD sg13_lv_pmos m=1 w=3.000u l=130.00n ++ ng=2 nrd=0 nrs=0 +MB_TPR<1> B_BLT<1> B_PRE_N VDD VDD sg13_lv_pmos m=1 w=3.000u l=130.00n ++ ng=2 nrd=0 nrs=0 +MB_TPR<0> B_BLT<0> B_PRE_N VDD VDD sg13_lv_pmos m=1 w=3.000u l=130.00n ++ ng=2 nrd=0 nrs=0 +MB_CSP<3> B_BLC_SEL B_SEL_N<3> B_BLC<3> VDD sg13_lv_pmos m=1 w=1.5u ++ l=130.00n ng=1 nrd=0 nrs=0 +MB_CSP<2> B_BLC_SEL B_SEL_N<2> B_BLC<2> VDD sg13_lv_pmos m=1 w=1.5u ++ l=130.00n ng=1 nrd=0 nrs=0 +MB_CSP<1> B_BLC_SEL B_SEL_N<1> B_BLC<1> VDD sg13_lv_pmos m=1 w=1.5u ++ l=130.00n ng=1 nrd=0 nrs=0 +MB_CSP<0> B_BLC_SEL B_SEL_N<0> B_BLC<0> VDD sg13_lv_pmos m=1 w=1.5u ++ l=130.00n ng=1 nrd=0 nrs=0 +MB_CPR<3> B_BLC<3> B_PRE_N VDD VDD sg13_lv_pmos m=1 w=3.000u l=130.00n ++ ng=2 nrd=0 nrs=0 +MB_CPR<2> B_BLC<2> B_PRE_N VDD VDD sg13_lv_pmos m=1 w=3.000u l=130.00n ++ ng=2 nrd=0 nrs=0 +MB_CPR<1> B_BLC<1> B_PRE_N VDD VDD sg13_lv_pmos m=1 w=3.000u l=130.00n ++ ng=2 nrd=0 nrs=0 +MB_CPR<0> B_BLC<0> B_PRE_N VDD VDD sg13_lv_pmos m=1 w=3.000u l=130.00n ++ ng=2 nrd=0 nrs=0 +XA_SEL<3> A_SEL_P<3> A_SEL_N<3> VDD VSS / RSC_IHPSG13_INVX2 +XA_SEL<2> A_SEL_P<2> A_SEL_N<2> VDD VSS / RSC_IHPSG13_INVX2 +XA_SEL<1> A_SEL_P<1> A_SEL_N<1> VDD VSS / RSC_IHPSG13_INVX2 +XA_SEL<0> A_SEL_P<0> A_SEL_N<0> VDD VSS / RSC_IHPSG13_INVX2 +XA_CINV<3> A_BLT_PMOS_DRIVE<3> A_BLC_NMOS_DRIVE<3> VDD VSS / ++ RSC_IHPSG13_INVX2 +XA_CINV<2> A_BLT_PMOS_DRIVE<2> A_BLC_NMOS_DRIVE<2> VDD VSS / ++ RSC_IHPSG13_INVX2 +XA_CINV<1> A_BLT_PMOS_DRIVE<1> A_BLC_NMOS_DRIVE<1> VDD VSS / ++ RSC_IHPSG13_INVX2 +XA_CINV<0> A_BLT_PMOS_DRIVE<0> A_BLC_NMOS_DRIVE<0> VDD VSS / ++ RSC_IHPSG13_INVX2 +XA_TINV<3> A_BLC_PMOS_DRIVE<3> A_BLT_NMOS_DRIVE<3> VDD VSS / ++ RSC_IHPSG13_INVX2 +XA_TINV<2> A_BLC_PMOS_DRIVE<2> A_BLT_NMOS_DRIVE<2> VDD VSS / ++ RSC_IHPSG13_INVX2 +XA_TINV<1> A_BLC_PMOS_DRIVE<1> A_BLT_NMOS_DRIVE<1> VDD VSS / ++ RSC_IHPSG13_INVX2 +XA_TINV<0> A_BLC_PMOS_DRIVE<0> A_BLT_NMOS_DRIVE<0> VDD VSS / ++ RSC_IHPSG13_INVX2 +XB_SEL<3> B_SEL_P<3> B_SEL_N<3> VDD VSS / RSC_IHPSG13_INVX2 +XB_SEL<2> B_SEL_P<2> B_SEL_N<2> VDD VSS / RSC_IHPSG13_INVX2 +XB_SEL<1> B_SEL_P<1> B_SEL_N<1> VDD VSS / RSC_IHPSG13_INVX2 +XB_SEL<0> B_SEL_P<0> B_SEL_N<0> VDD VSS / RSC_IHPSG13_INVX2 +XB_TINV<3> B_BLC_PMOS_DRIVE<3> B_BLT_NMOS_DRIVE<3> VDD VSS / ++ RSC_IHPSG13_INVX2 +XB_TINV<2> B_BLC_PMOS_DRIVE<2> B_BLT_NMOS_DRIVE<2> VDD VSS / ++ RSC_IHPSG13_INVX2 +XB_TINV<1> B_BLC_PMOS_DRIVE<1> B_BLT_NMOS_DRIVE<1> VDD VSS / ++ RSC_IHPSG13_INVX2 +XB_TINV<0> B_BLC_PMOS_DRIVE<0> B_BLT_NMOS_DRIVE<0> VDD VSS / ++ RSC_IHPSG13_INVX2 +XB_CINV<3> B_BLT_PMOS_DRIVE<3> B_BLC_NMOS_DRIVE<3> VDD VSS / ++ RSC_IHPSG13_INVX2 +XB_CINV<2> B_BLT_PMOS_DRIVE<2> B_BLC_NMOS_DRIVE<2> VDD VSS / ++ RSC_IHPSG13_INVX2 +XB_CINV<1> B_BLT_PMOS_DRIVE<1> B_BLC_NMOS_DRIVE<1> VDD VSS / ++ RSC_IHPSG13_INVX2 +XB_CINV<0> B_BLT_PMOS_DRIVE<0> B_BLC_NMOS_DRIVE<0> VDD VSS / ++ RSC_IHPSG13_INVX2 +XA_TDEC<3> A_SEL_P<3> A_WR_ONE A_BLT_PMOS_DRIVE<3> VDD VSS / ++ RSC_IHPSG13_NAND2X2 +XA_TDEC<2> A_SEL_P<2> A_WR_ONE A_BLT_PMOS_DRIVE<2> VDD VSS / ++ RSC_IHPSG13_NAND2X2 +XA_TDEC<1> A_SEL_P<1> A_WR_ONE A_BLT_PMOS_DRIVE<1> VDD VSS / ++ RSC_IHPSG13_NAND2X2 +XA_TDEC<0> A_SEL_P<0> A_WR_ONE A_BLT_PMOS_DRIVE<0> VDD VSS / ++ RSC_IHPSG13_NAND2X2 +XA_CDEC<3> A_SEL_P<3> A_WR_ZERO A_BLC_PMOS_DRIVE<3> VDD VSS / ++ RSC_IHPSG13_NAND2X2 +XA_CDEC<2> A_SEL_P<2> A_WR_ZERO A_BLC_PMOS_DRIVE<2> VDD VSS / ++ RSC_IHPSG13_NAND2X2 +XA_CDEC<1> A_SEL_P<1> A_WR_ZERO A_BLC_PMOS_DRIVE<1> VDD VSS / ++ RSC_IHPSG13_NAND2X2 +XA_CDEC<0> A_SEL_P<0> A_WR_ZERO A_BLC_PMOS_DRIVE<0> VDD VSS / ++ RSC_IHPSG13_NAND2X2 +XB_CDEC<3> B_SEL_P<3> B_WR_ZERO B_BLC_PMOS_DRIVE<3> VDD VSS / ++ RSC_IHPSG13_NAND2X2 +XB_CDEC<2> B_SEL_P<2> B_WR_ZERO B_BLC_PMOS_DRIVE<2> VDD VSS / ++ RSC_IHPSG13_NAND2X2 +XB_CDEC<1> B_SEL_P<1> B_WR_ZERO B_BLC_PMOS_DRIVE<1> VDD VSS / ++ RSC_IHPSG13_NAND2X2 +XB_CDEC<0> B_SEL_P<0> B_WR_ZERO B_BLC_PMOS_DRIVE<0> VDD VSS / ++ RSC_IHPSG13_NAND2X2 +XB_TDEC<3> B_SEL_P<3> B_WR_ONE B_BLT_PMOS_DRIVE<3> VDD VSS / ++ RSC_IHPSG13_NAND2X2 +XB_TDEC<2> B_SEL_P<2> B_WR_ONE B_BLT_PMOS_DRIVE<2> VDD VSS / ++ RSC_IHPSG13_NAND2X2 +XB_TDEC<1> B_SEL_P<1> B_WR_ONE B_BLT_PMOS_DRIVE<1> VDD VSS / ++ RSC_IHPSG13_NAND2X2 +XB_TDEC<0> B_SEL_P<0> B_WR_ONE B_BLT_PMOS_DRIVE<0> VDD VSS / ++ RSC_IHPSG13_NAND2X2 +.ENDS +.SUBCKT RSC_IHPSG13_AND2X6 A B Z VDD VSS +MN3 Z net6 VSS VSS sg13_lv_nmos m=1 w=2.94u l=130.00n ng=3 nrd=0 nrs=0 +MN4 net9 B VSS VSS sg13_lv_nmos m=1 w=500.0n l=130.00n ng=1 nrd=0 nrs=0 +MN6 net6 A net9 VSS sg13_lv_nmos m=1 w=500.0n l=130.00n ng=1 nrd=0 nrs=0 +MP2 Z net6 VDD VDD sg13_lv_pmos m=1 w=4.86u l=130.00n ng=3 nrd=0 nrs=0 +MP0 net6 B VDD VDD sg13_lv_pmos m=1 w=860.00n l=130.00n ng=1 nrd=0 ++ nrs=0 +MP1 net6 A VDD VDD sg13_lv_pmos m=1 w=860.00n l=130.00n ng=1 nrd=0 ++ nrs=0 +.ENDS +.SUBCKT RM_IHPSG13_256x8_c3_2P_COLCTRL5 A_ADDR_COL<1> A_ADDR_COL<0> A_ADDR_DEC<7> ++ A_ADDR_DEC<6> A_ADDR_DEC<5> A_ADDR_DEC<4> A_ADDR_DEC<3> A_ADDR_DEC<2> ++ A_ADDR_DEC<1> A_ADDR_DEC<0> A_BIST_BM_I A_BIST_DW_I A_BIST_EN_I A_BLC<31> ++ A_BLC<30> A_BLC<29> A_BLC<28> A_BLC<27> A_BLC<26> A_BLC<25> A_BLC<24> ++ A_BLC<23> A_BLC<22> A_BLC<21> A_BLC<20> A_BLC<19> A_BLC<18> A_BLC<17> ++ A_BLC<16> A_BLC<15> A_BLC<14> A_BLC<13> A_BLC<12> A_BLC<11> A_BLC<10> ++ A_BLC<9> A_BLC<8> A_BLC<7> A_BLC<6> A_BLC<5> A_BLC<4> A_BLC<3> A_BLC<2> ++ A_BLC<1> A_BLC<0> A_BLT<31> A_BLT<30> A_BLT<29> A_BLT<28> A_BLT<27> ++ A_BLT<26> A_BLT<25> A_BLT<24> A_BLT<23> A_BLT<22> A_BLT<21> A_BLT<20> ++ A_BLT<19> A_BLT<18> A_BLT<17> A_BLT<16> A_BLT<15> A_BLT<14> A_BLT<13> ++ A_BLT<12> A_BLT<11> A_BLT<10> A_BLT<9> A_BLT<8> A_BLT<7> A_BLT<6> A_BLT<5> ++ A_BLT<4> A_BLT<3> A_BLT<2> A_BLT<1> A_BLT<0> A_BM_I A_DCLK_B_L A_DCLK_B_R ++ A_DCLK_L A_DCLK_R A_DR_O A_DW_I A_RCLK_B_L A_RCLK_B_R A_RCLK_L A_RCLK_R ++ A_TIEH_O A_WCLK_B_L A_WCLK_B_R A_WCLK_L A_WCLK_R B_ADDR_COL<1> B_ADDR_COL<0> ++ B_ADDR_DEC<7> B_ADDR_DEC<6> B_ADDR_DEC<5> B_ADDR_DEC<4> B_ADDR_DEC<3> ++ B_ADDR_DEC<2> B_ADDR_DEC<1> B_ADDR_DEC<0> B_BIST_BM_I B_BIST_DW_I ++ B_BIST_EN_I B_BLC<31> B_BLC<30> B_BLC<29> B_BLC<28> B_BLC<27> B_BLC<26> ++ B_BLC<25> B_BLC<24> B_BLC<23> B_BLC<22> B_BLC<21> B_BLC<20> B_BLC<19> ++ B_BLC<18> B_BLC<17> B_BLC<16> B_BLC<15> B_BLC<14> B_BLC<13> B_BLC<12> ++ B_BLC<11> B_BLC<10> B_BLC<9> B_BLC<8> B_BLC<7> B_BLC<6> B_BLC<5> B_BLC<4> ++ B_BLC<3> B_BLC<2> B_BLC<1> B_BLC<0> B_BLT<31> B_BLT<30> B_BLT<29> B_BLT<28> ++ B_BLT<27> B_BLT<26> B_BLT<25> B_BLT<24> B_BLT<23> B_BLT<22> B_BLT<21> ++ B_BLT<20> B_BLT<19> B_BLT<18> B_BLT<17> B_BLT<16> B_BLT<15> B_BLT<14> ++ B_BLT<13> B_BLT<12> B_BLT<11> B_BLT<10> B_BLT<9> B_BLT<8> B_BLT<7> B_BLT<6> ++ B_BLT<5> B_BLT<4> B_BLT<3> B_BLT<2> B_BLT<1> B_BLT<0> B_BM_I B_DCLK_B_L ++ B_DCLK_B_R B_DCLK_L B_DCLK_R B_DR_O B_DW_I B_RCLK_B_L B_RCLK_B_R B_RCLK_L ++ B_RCLK_R B_TIEH_O B_WCLK_B_L B_WCLK_B_R B_WCLK_L B_WCLK_R VDD VSS +XB_I80<1> B_WCLK_B_L B_RCLK_B_L B_W_nor_R<1> VDD VSS / ++ RSC_IHPSG13_AND2X2 +XB_I80<0> B_WCLK_B_L B_RCLK_B_L B_W_nor_R<0> VDD VSS / ++ RSC_IHPSG13_AND2X2 +XA_I80<1> A_WCLK_B_L A_RCLK_B_L A_W_nor_R<1> VDD VSS / ++ RSC_IHPSG13_AND2X2 +XA_I80<0> A_WCLK_B_L A_RCLK_B_L A_W_nor_R<0> VDD VSS / ++ RSC_IHPSG13_AND2X2 +XB_I44 B_BM_N B_WCLK_B_L B_DO_WRITE_P VDD VSS / RSC_IHPSG13_NOR2X2 +XA_I44 A_BM_N A_WCLK_B_L A_DO_WRITE_P VDD VSS / RSC_IHPSG13_NOR2X2 +XI_FILL4<16> VDD VSS / RSC_IHPSG13_FILLCAP4 +XI_FILL4<15> VDD VSS / RSC_IHPSG13_FILLCAP4 +XI_FILL4<14> VDD VSS / RSC_IHPSG13_FILLCAP4 +XI_FILL4<13> VDD VSS / RSC_IHPSG13_FILLCAP4 +XI_FILL4<12> VDD VSS / RSC_IHPSG13_FILLCAP4 +XI_FILL4<11> VDD VSS / RSC_IHPSG13_FILLCAP4 +XI_FILL4<10> VDD VSS / RSC_IHPSG13_FILLCAP4 +XI_FILL4<9> VDD VSS / RSC_IHPSG13_FILLCAP4 +XI_FILL4<8> VDD VSS / RSC_IHPSG13_FILLCAP4 +XI_FILL4<7> VDD VSS / RSC_IHPSG13_FILLCAP4 +XI_FILL4<6> VDD VSS / RSC_IHPSG13_FILLCAP4 +XI_FILL4<5> VDD VSS / RSC_IHPSG13_FILLCAP4 +XI_FILL4<4> VDD VSS / RSC_IHPSG13_FILLCAP4 +XI_FILL4<3> VDD VSS / RSC_IHPSG13_FILLCAP4 +XI_FILL4<2> VDD VSS / RSC_IHPSG13_FILLCAP4 +XI_FILL4<1> VDD VSS / RSC_IHPSG13_FILLCAP4 +XB_INV<6> B_N1<1> B_P1<1> VDD VSS / RSC_IHPSG13_CINVX4 +XB_INV<5> B_N0<1> B_P0<1> VDD VSS / RSC_IHPSG13_CINVX4 +XB_INV<4> B_N0<0> B_P0<0> VDD VSS / RSC_IHPSG13_CINVX4 +XB_INV<3> B_ADDR_COL<1> B_N1<1> VDD VSS / RSC_IHPSG13_CINVX4 +XB_INV<2> B_ADDR_COL<1> B_N1<0> VDD VSS / RSC_IHPSG13_CINVX4 +XB_INV<1> B_ADDR_COL<0> B_N0<1> VDD VSS / RSC_IHPSG13_CINVX4 +XB_INV<0> B_ADDR_COL<0> B_N0<0> VDD VSS / RSC_IHPSG13_CINVX4 +XA_INV<6> A_N1<1> A_P1<1> VDD VSS / RSC_IHPSG13_CINVX4 +XA_INV<5> A_N0<1> A_P0<1> VDD VSS / RSC_IHPSG13_CINVX4 +XA_INV<4> A_N0<0> A_P0<0> VDD VSS / RSC_IHPSG13_CINVX4 +XA_INV<3> A_ADDR_COL<1> A_N1<1> VDD VSS / RSC_IHPSG13_CINVX4 +XA_INV<2> A_ADDR_COL<1> A_N1<0> VDD VSS / RSC_IHPSG13_CINVX4 +XA_INV<1> A_ADDR_COL<0> A_N0<1> VDD VSS / RSC_IHPSG13_CINVX4 +XA_INV<0> A_ADDR_COL<0> A_N0<0> VDD VSS / RSC_IHPSG13_CINVX4 +XB_I81<3> B_W_nor_R<1> B_PRE_N VDD VSS / RSC_IHPSG13_CINVX4_WN +XB_I81<2> B_W_nor_R<1> B_PRE_N VDD VSS / RSC_IHPSG13_CINVX4_WN +XB_I81<1> B_W_nor_R<0> B_PRE_N VDD VSS / RSC_IHPSG13_CINVX4_WN +XB_I81<0> B_W_nor_R<0> B_PRE_N VDD VSS / RSC_IHPSG13_CINVX4_WN +XA_I81<3> A_W_nor_R<1> A_PRE_N VDD VSS / RSC_IHPSG13_CINVX4_WN +XA_I81<2> A_W_nor_R<1> A_PRE_N VDD VSS / RSC_IHPSG13_CINVX4_WN +XA_I81<1> A_W_nor_R<0> A_PRE_N VDD VSS / RSC_IHPSG13_CINVX4_WN +XA_I81<0> A_W_nor_R<0> A_PRE_N VDD VSS / RSC_IHPSG13_CINVX4_WN +XI_FILL8<78> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI_FILL8<77> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI_FILL8<76> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI_FILL8<75> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI_FILL8<74> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI_FILL8<73> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI_FILL8<72> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI_FILL8<71> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI_FILL8<70> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI_FILL8<69> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI_FILL8<68> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI_FILL8<67> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI_FILL8<66> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI_FILL8<65> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI_FILL8<64> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI_FILL8<63> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI_FILL8<62> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI_FILL8<61> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI_FILL8<60> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI_FILL8<59> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI_FILL8<58> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI_FILL8<57> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI_FILL8<56> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI_FILL8<55> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI_FILL8<54> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI_FILL8<53> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI_FILL8<52> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI_FILL8<51> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI_FILL8<50> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI_FILL8<49> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI_FILL8<48> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI_FILL8<47> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI_FILL8<46> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI_FILL8<45> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI_FILL8<44> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI_FILL8<43> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI_FILL8<42> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI_FILL8<41> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI_FILL8<40> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI_FILL8<39> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI_FILL8<38> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI_FILL8<37> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI_FILL8<36> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI_FILL8<35> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI_FILL8<34> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI_FILL8<33> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI_FILL8<32> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI_FILL8<31> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI_FILL8<30> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI_FILL8<29> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI_FILL8<28> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI_FILL8<27> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI_FILL8<26> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI_FILL8<25> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI_FILL8<24> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI_FILL8<23> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI_FILL8<22> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI_FILL8<21> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI_FILL8<20> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI_FILL8<19> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI_FILL8<18> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI_FILL8<17> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI_FILL8<16> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI_FILL8<15> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI_FILL8<14> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI_FILL8<13> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI_FILL8<12> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI_FILL8<11> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI_FILL8<10> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI_FILL8<9> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI_FILL8<8> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI_FILL8<7> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI_FILL8<6> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI_FILL8<5> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI_FILL8<4> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI_FILL8<3> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI_FILL8<2> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI_FILL8<1> VDD VSS / RSC_IHPSG13_FILLCAP8 +XAB_BLMUX<7> A_BLC<31> A_BLC<30> A_BLC<29> A_BLC<28> A_BLC_SEL A_BLT<31> ++ A_BLT<30> A_BLT<29> A_BLT<28> A_BLT_SEL A_PRE_N A_SEL_P<31> A_SEL_P<30> ++ A_SEL_P<29> A_SEL_P<28> A_WR_ONE A_WR_ZERO B_BLC<31> B_BLC<30> B_BLC<29> ++ B_BLC<28> B_BLC_SEL B_BLT<31> B_BLT<30> B_BLT<29> B_BLT<28> B_BLT_SEL ++ B_PRE_N B_SEL_P<31> B_SEL_P<30> B_SEL_P<29> B_SEL_P<28> B_WR_ONE B_WR_ZERO ++ VDD VSS / RM_IHPSG13_256x8_c3_2P_BLDRV +XAB_BLMUX<6> A_BLC<27> A_BLC<26> A_BLC<25> A_BLC<24> A_BLC_SEL A_BLT<27> ++ A_BLT<26> A_BLT<25> A_BLT<24> A_BLT_SEL A_PRE_N A_SEL_P<27> A_SEL_P<26> ++ A_SEL_P<25> A_SEL_P<24> A_WR_ONE A_WR_ZERO B_BLC<27> B_BLC<26> B_BLC<25> ++ B_BLC<24> B_BLC_SEL B_BLT<27> B_BLT<26> B_BLT<25> B_BLT<24> B_BLT_SEL ++ B_PRE_N B_SEL_P<27> B_SEL_P<26> B_SEL_P<25> B_SEL_P<24> B_WR_ONE B_WR_ZERO ++ VDD VSS / RM_IHPSG13_256x8_c3_2P_BLDRV +XAB_BLMUX<5> A_BLC<23> A_BLC<22> A_BLC<21> A_BLC<20> A_BLC_SEL A_BLT<23> ++ A_BLT<22> A_BLT<21> A_BLT<20> A_BLT_SEL A_PRE_N A_SEL_P<23> A_SEL_P<22> ++ A_SEL_P<21> A_SEL_P<20> A_WR_ONE A_WR_ZERO B_BLC<23> B_BLC<22> B_BLC<21> ++ B_BLC<20> B_BLC_SEL B_BLT<23> B_BLT<22> B_BLT<21> B_BLT<20> B_BLT_SEL ++ B_PRE_N B_SEL_P<23> B_SEL_P<22> B_SEL_P<21> B_SEL_P<20> B_WR_ONE B_WR_ZERO ++ VDD VSS / RM_IHPSG13_256x8_c3_2P_BLDRV +XAB_BLMUX<4> A_BLC<19> A_BLC<18> A_BLC<17> A_BLC<16> A_BLC_SEL A_BLT<19> ++ A_BLT<18> A_BLT<17> A_BLT<16> A_BLT_SEL A_PRE_N A_SEL_P<19> A_SEL_P<18> ++ A_SEL_P<17> A_SEL_P<16> A_WR_ONE A_WR_ZERO B_BLC<19> B_BLC<18> B_BLC<17> ++ B_BLC<16> B_BLC_SEL B_BLT<19> B_BLT<18> B_BLT<17> B_BLT<16> B_BLT_SEL ++ B_PRE_N B_SEL_P<19> B_SEL_P<18> B_SEL_P<17> B_SEL_P<16> B_WR_ONE B_WR_ZERO ++ VDD VSS / RM_IHPSG13_256x8_c3_2P_BLDRV +XAB_BLMUX<3> A_BLC<15> A_BLC<14> A_BLC<13> A_BLC<12> A_BLC_SEL A_BLT<15> ++ A_BLT<14> A_BLT<13> A_BLT<12> A_BLT_SEL A_PRE_N A_SEL_P<15> A_SEL_P<14> ++ A_SEL_P<13> A_SEL_P<12> A_WR_ONE A_WR_ZERO B_BLC<15> B_BLC<14> B_BLC<13> ++ B_BLC<12> B_BLC_SEL B_BLT<15> B_BLT<14> B_BLT<13> B_BLT<12> B_BLT_SEL ++ B_PRE_N B_SEL_P<15> B_SEL_P<14> B_SEL_P<13> B_SEL_P<12> B_WR_ONE B_WR_ZERO ++ VDD VSS / RM_IHPSG13_256x8_c3_2P_BLDRV +XAB_BLMUX<2> A_BLC<11> A_BLC<10> A_BLC<9> A_BLC<8> A_BLC_SEL A_BLT<11> ++ A_BLT<10> A_BLT<9> A_BLT<8> A_BLT_SEL A_PRE_N A_SEL_P<11> A_SEL_P<10> ++ A_SEL_P<9> A_SEL_P<8> A_WR_ONE A_WR_ZERO B_BLC<11> B_BLC<10> B_BLC<9> ++ B_BLC<8> B_BLC_SEL B_BLT<11> B_BLT<10> B_BLT<9> B_BLT<8> B_BLT_SEL B_PRE_N ++ B_SEL_P<11> B_SEL_P<10> B_SEL_P<9> B_SEL_P<8> B_WR_ONE B_WR_ZERO VDD ++ VSS / RM_IHPSG13_256x8_c3_2P_BLDRV +XAB_BLMUX<1> A_BLC<7> A_BLC<6> A_BLC<5> A_BLC<4> A_BLC_SEL A_BLT<7> A_BLT<6> ++ A_BLT<5> A_BLT<4> A_BLT_SEL A_PRE_N A_SEL_P<7> A_SEL_P<6> A_SEL_P<5> ++ A_SEL_P<4> A_WR_ONE A_WR_ZERO B_BLC<7> B_BLC<6> B_BLC<5> B_BLC<4> B_BLC_SEL ++ B_BLT<7> B_BLT<6> B_BLT<5> B_BLT<4> B_BLT_SEL B_PRE_N B_SEL_P<7> B_SEL_P<6> ++ B_SEL_P<5> B_SEL_P<4> B_WR_ONE B_WR_ZERO VDD VSS / ++ RM_IHPSG13_256x8_c3_2P_BLDRV +XAB_BLMUX<0> A_BLC<3> A_BLC<2> A_BLC<1> A_BLC<0> A_BLC_SEL A_BLT<3> A_BLT<2> ++ A_BLT<1> A_BLT<0> A_BLT_SEL A_PRE_N A_SEL_P<3> A_SEL_P<2> A_SEL_P<1> ++ A_SEL_P<0> A_WR_ONE A_WR_ZERO B_BLC<3> B_BLC<2> B_BLC<1> B_BLC<0> B_BLC_SEL ++ B_BLT<3> B_BLT<2> B_BLT<1> B_BLT<0> B_BLT_SEL B_PRE_N B_SEL_P<3> B_SEL_P<2> ++ B_SEL_P<1> B_SEL_P<0> B_WR_ONE B_WR_ZERO VDD VSS / ++ RM_IHPSG13_256x8_c3_2P_BLDRV +XB_I51 net037 B_DR_O VDD VSS / RSC_IHPSG13_INVX4 +XA_I51 net19 A_DR_O VDD VSS / RSC_IHPSG13_INVX4 +XB_I78 B_RCLK_B_L B_SAE VDD VSS / RSC_IHPSG13_CBUFX2 +XA_I78 A_RCLK_B_L A_SAE VDD VSS / RSC_IHPSG13_CBUFX2 +XB_I69 B_DCLK_L B_DCLK_B_L VDD VSS / RSC_IHPSG13_CINVX8 +XB_I50 B_WCLK_L B_WCLK_B_L VDD VSS / RSC_IHPSG13_CINVX8 +XB_EBUF B_RCLK_L B_RCLK_B_L VDD VSS / RSC_IHPSG13_CINVX8 +XA_I69 A_DCLK_L A_DCLK_B_L VDD VSS / RSC_IHPSG13_CINVX8 +XA_I50 A_WCLK_L A_WCLK_B_L VDD VSS / RSC_IHPSG13_CINVX8 +XA_EBUF A_RCLK_L A_RCLK_B_L VDD VSS / RSC_IHPSG13_CINVX8 +XB_I76 B_DI_N B_DO_WRITE_P B_WR_ZERO VDD VSS / RSC_IHPSG13_AND2X6 +XB_I75 B_DI_R B_DO_WRITE_P B_WR_ONE VDD VSS / RSC_IHPSG13_AND2X6 +XA_I76 A_DI_N A_DO_WRITE_P A_WR_ZERO VDD VSS / RSC_IHPSG13_AND2X6 +XA_I75 A_DI_R A_DO_WRITE_P A_WR_ONE VDD VSS / RSC_IHPSG13_AND2X6 +XB_I83 B_BM_R B_BM_N VDD VSS / RSC_IHPSG13_INVX2 +XB_DEC3INV<31> net041<0> B_SEL_P<31> VDD VSS / RSC_IHPSG13_INVX2 +XB_DEC3INV<30> net041<1> B_SEL_P<30> VDD VSS / RSC_IHPSG13_INVX2 +XB_DEC3INV<29> net041<2> B_SEL_P<29> VDD VSS / RSC_IHPSG13_INVX2 +XB_DEC3INV<28> net041<3> B_SEL_P<28> VDD VSS / RSC_IHPSG13_INVX2 +XB_DEC3INV<27> net041<4> B_SEL_P<27> VDD VSS / RSC_IHPSG13_INVX2 +XB_DEC3INV<26> net041<5> B_SEL_P<26> VDD VSS / RSC_IHPSG13_INVX2 +XB_DEC3INV<25> net041<6> B_SEL_P<25> VDD VSS / RSC_IHPSG13_INVX2 +XB_DEC3INV<24> net041<7> B_SEL_P<24> VDD VSS / RSC_IHPSG13_INVX2 +XB_DEC3INV<23> net041<8> B_SEL_P<23> VDD VSS / RSC_IHPSG13_INVX2 +XB_DEC3INV<22> net041<9> B_SEL_P<22> VDD VSS / RSC_IHPSG13_INVX2 +XB_DEC3INV<21> net041<10> B_SEL_P<21> VDD VSS / RSC_IHPSG13_INVX2 +XB_DEC3INV<20> net041<11> B_SEL_P<20> VDD VSS / RSC_IHPSG13_INVX2 +XB_DEC3INV<19> net041<12> B_SEL_P<19> VDD VSS / RSC_IHPSG13_INVX2 +XB_DEC3INV<18> net041<13> B_SEL_P<18> VDD VSS / RSC_IHPSG13_INVX2 +XB_DEC3INV<17> net041<14> B_SEL_P<17> VDD VSS / RSC_IHPSG13_INVX2 +XB_DEC3INV<16> net041<15> B_SEL_P<16> VDD VSS / RSC_IHPSG13_INVX2 +XB_DEC3INV<15> net041<16> B_SEL_P<15> VDD VSS / RSC_IHPSG13_INVX2 +XB_DEC3INV<14> net041<17> B_SEL_P<14> VDD VSS / RSC_IHPSG13_INVX2 +XB_DEC3INV<13> net041<18> B_SEL_P<13> VDD VSS / RSC_IHPSG13_INVX2 +XB_DEC3INV<12> net041<19> B_SEL_P<12> VDD VSS / RSC_IHPSG13_INVX2 +XB_DEC3INV<11> net041<20> B_SEL_P<11> VDD VSS / RSC_IHPSG13_INVX2 +XB_DEC3INV<10> net041<21> B_SEL_P<10> VDD VSS / RSC_IHPSG13_INVX2 +XB_DEC3INV<9> net041<22> B_SEL_P<9> VDD VSS / RSC_IHPSG13_INVX2 +XB_DEC3INV<8> net041<23> B_SEL_P<8> VDD VSS / RSC_IHPSG13_INVX2 +XB_DEC3INV<7> net041<24> B_SEL_P<7> VDD VSS / RSC_IHPSG13_INVX2 +XB_DEC3INV<6> net041<25> B_SEL_P<6> VDD VSS / RSC_IHPSG13_INVX2 +XB_DEC3INV<5> net041<26> B_SEL_P<5> VDD VSS / RSC_IHPSG13_INVX2 +XB_DEC3INV<4> net041<27> B_SEL_P<4> VDD VSS / RSC_IHPSG13_INVX2 +XB_DEC3INV<3> net041<28> B_SEL_P<3> VDD VSS / RSC_IHPSG13_INVX2 +XB_DEC3INV<2> net041<29> B_SEL_P<2> VDD VSS / RSC_IHPSG13_INVX2 +XB_DEC3INV<1> net041<30> B_SEL_P<1> VDD VSS / RSC_IHPSG13_INVX2 +XB_DEC3INV<0> net041<31> B_SEL_P<0> VDD VSS / RSC_IHPSG13_INVX2 +XB_I49 B_DI_R B_DI_N VDD VSS / RSC_IHPSG13_INVX2 +XA_I83 A_BM_R A_BM_N VDD VSS / RSC_IHPSG13_INVX2 +XA_DEC3INV<31> net23<0> A_SEL_P<31> VDD VSS / RSC_IHPSG13_INVX2 +XA_DEC3INV<30> net23<1> A_SEL_P<30> VDD VSS / RSC_IHPSG13_INVX2 +XA_DEC3INV<29> net23<2> A_SEL_P<29> VDD VSS / RSC_IHPSG13_INVX2 +XA_DEC3INV<28> net23<3> A_SEL_P<28> VDD VSS / RSC_IHPSG13_INVX2 +XA_DEC3INV<27> net23<4> A_SEL_P<27> VDD VSS / RSC_IHPSG13_INVX2 +XA_DEC3INV<26> net23<5> A_SEL_P<26> VDD VSS / RSC_IHPSG13_INVX2 +XA_DEC3INV<25> net23<6> A_SEL_P<25> VDD VSS / RSC_IHPSG13_INVX2 +XA_DEC3INV<24> net23<7> A_SEL_P<24> VDD VSS / RSC_IHPSG13_INVX2 +XA_DEC3INV<23> net23<8> A_SEL_P<23> VDD VSS / RSC_IHPSG13_INVX2 +XA_DEC3INV<22> net23<9> A_SEL_P<22> VDD VSS / RSC_IHPSG13_INVX2 +XA_DEC3INV<21> net23<10> A_SEL_P<21> VDD VSS / RSC_IHPSG13_INVX2 +XA_DEC3INV<20> net23<11> A_SEL_P<20> VDD VSS / RSC_IHPSG13_INVX2 +XA_DEC3INV<19> net23<12> A_SEL_P<19> VDD VSS / RSC_IHPSG13_INVX2 +XA_DEC3INV<18> net23<13> A_SEL_P<18> VDD VSS / RSC_IHPSG13_INVX2 +XA_DEC3INV<17> net23<14> A_SEL_P<17> VDD VSS / RSC_IHPSG13_INVX2 +XA_DEC3INV<16> net23<15> A_SEL_P<16> VDD VSS / RSC_IHPSG13_INVX2 +XA_DEC3INV<15> net23<16> A_SEL_P<15> VDD VSS / RSC_IHPSG13_INVX2 +XA_DEC3INV<14> net23<17> A_SEL_P<14> VDD VSS / RSC_IHPSG13_INVX2 +XA_DEC3INV<13> net23<18> A_SEL_P<13> VDD VSS / RSC_IHPSG13_INVX2 +XA_DEC3INV<12> net23<19> A_SEL_P<12> VDD VSS / RSC_IHPSG13_INVX2 +XA_DEC3INV<11> net23<20> A_SEL_P<11> VDD VSS / RSC_IHPSG13_INVX2 +XA_DEC3INV<10> net23<21> A_SEL_P<10> VDD VSS / RSC_IHPSG13_INVX2 +XA_DEC3INV<9> net23<22> A_SEL_P<9> VDD VSS / RSC_IHPSG13_INVX2 +XA_DEC3INV<8> net23<23> A_SEL_P<8> VDD VSS / RSC_IHPSG13_INVX2 +XA_DEC3INV<7> net23<24> A_SEL_P<7> VDD VSS / RSC_IHPSG13_INVX2 +XA_DEC3INV<6> net23<25> A_SEL_P<6> VDD VSS / RSC_IHPSG13_INVX2 +XA_DEC3INV<5> net23<26> A_SEL_P<5> VDD VSS / RSC_IHPSG13_INVX2 +XA_DEC3INV<4> net23<27> A_SEL_P<4> VDD VSS / RSC_IHPSG13_INVX2 +XA_DEC3INV<3> net23<28> A_SEL_P<3> VDD VSS / RSC_IHPSG13_INVX2 +XA_DEC3INV<2> net23<29> A_SEL_P<2> VDD VSS / RSC_IHPSG13_INVX2 +XA_DEC3INV<1> net23<30> A_SEL_P<1> VDD VSS / RSC_IHPSG13_INVX2 +XA_DEC3INV<0> net23<31> A_SEL_P<0> VDD VSS / RSC_IHPSG13_INVX2 +XA_I49 A_DI_R A_DI_N VDD VSS / RSC_IHPSG13_INVX2 +XB_ISENSE B_SAE B_BLC_SEL B_BLT_SEL net037 net038 VDD VSS / ++ RSC_IHPSG13_DFPQD_MSAFFX2 +XA_ISENSE A_SAE A_BLC_SEL A_BLT_SEL net19 net20 VDD VSS / ++ RSC_IHPSG13_DFPQD_MSAFFX2 +XB_DREG B_BIST_EN_I B_BIST_DW_I B_DCLK_B_L B_DW_I B_DI_R net042 VDD ++ VSS / RSC_IHPSG13_DFNQMX2IX1 +XB_BREG B_BIST_EN_I B_BIST_BM_I B_DCLK_B_L B_BM_I B_BM_R net043 VDD ++ VSS / RSC_IHPSG13_DFNQMX2IX1 +XA_DREG A_BIST_EN_I A_BIST_DW_I A_DCLK_B_L A_DW_I A_DI_R net22 VDD VSS ++ / RSC_IHPSG13_DFNQMX2IX1 +XA_BREG A_BIST_EN_I A_BIST_BM_I A_DCLK_B_L A_BM_I A_BM_R net21 VDD VSS ++ / RSC_IHPSG13_DFNQMX2IX1 +XB_DEC3<31> B_P1<1> B_P0<1> B_ADDR_DEC<7> net041<0> VDD VSS / ++ RSC_IHPSG13_NAND3X2 +XB_DEC3<30> B_P1<1> B_P0<1> B_ADDR_DEC<6> net041<1> VDD VSS / ++ RSC_IHPSG13_NAND3X2 +XB_DEC3<29> B_P1<1> B_P0<1> B_ADDR_DEC<5> net041<2> VDD VSS / ++ RSC_IHPSG13_NAND3X2 +XB_DEC3<28> B_P1<1> B_P0<1> B_ADDR_DEC<4> net041<3> VDD VSS / ++ RSC_IHPSG13_NAND3X2 +XB_DEC3<27> B_P1<1> B_P0<1> B_ADDR_DEC<3> net041<4> VDD VSS / ++ RSC_IHPSG13_NAND3X2 +XB_DEC3<26> B_P1<1> B_P0<1> B_ADDR_DEC<2> net041<5> VDD VSS / ++ RSC_IHPSG13_NAND3X2 +XB_DEC3<25> B_P1<1> B_P0<1> B_ADDR_DEC<1> net041<6> VDD VSS / ++ RSC_IHPSG13_NAND3X2 +XB_DEC3<24> B_P1<1> B_P0<1> B_ADDR_DEC<0> net041<7> VDD VSS / ++ RSC_IHPSG13_NAND3X2 +XB_DEC3<23> B_P1<1> B_N0<1> B_ADDR_DEC<7> net041<8> VDD VSS / ++ RSC_IHPSG13_NAND3X2 +XB_DEC3<22> B_P1<1> B_N0<1> B_ADDR_DEC<6> net041<9> VDD VSS / ++ RSC_IHPSG13_NAND3X2 +XB_DEC3<21> B_P1<1> B_N0<1> B_ADDR_DEC<5> net041<10> VDD VSS / ++ RSC_IHPSG13_NAND3X2 +XB_DEC3<20> B_P1<1> B_N0<1> B_ADDR_DEC<4> net041<11> VDD VSS / ++ RSC_IHPSG13_NAND3X2 +XB_DEC3<19> B_P1<1> B_N0<1> B_ADDR_DEC<3> net041<12> VDD VSS / ++ RSC_IHPSG13_NAND3X2 +XB_DEC3<18> B_P1<1> B_N0<1> B_ADDR_DEC<2> net041<13> VDD VSS / ++ RSC_IHPSG13_NAND3X2 +XB_DEC3<17> B_P1<1> B_N0<1> B_ADDR_DEC<1> net041<14> VDD VSS / ++ RSC_IHPSG13_NAND3X2 +XB_DEC3<16> B_P1<1> B_N0<1> B_ADDR_DEC<0> net041<15> VDD VSS / ++ RSC_IHPSG13_NAND3X2 +XB_DEC3<15> B_N1<0> B_P0<0> B_ADDR_DEC<7> net041<16> VDD VSS / ++ RSC_IHPSG13_NAND3X2 +XB_DEC3<14> B_N1<0> B_P0<0> B_ADDR_DEC<6> net041<17> VDD VSS / ++ RSC_IHPSG13_NAND3X2 +XB_DEC3<13> B_N1<0> B_P0<0> B_ADDR_DEC<5> net041<18> VDD VSS / ++ RSC_IHPSG13_NAND3X2 +XB_DEC3<12> B_N1<0> B_P0<0> B_ADDR_DEC<4> net041<19> VDD VSS / ++ RSC_IHPSG13_NAND3X2 +XB_DEC3<11> B_N1<0> B_P0<0> B_ADDR_DEC<3> net041<20> VDD VSS / ++ RSC_IHPSG13_NAND3X2 +XB_DEC3<10> B_N1<0> B_P0<0> B_ADDR_DEC<2> net041<21> VDD VSS / ++ RSC_IHPSG13_NAND3X2 +XB_DEC3<9> B_N1<0> B_P0<0> B_ADDR_DEC<1> net041<22> VDD VSS / ++ RSC_IHPSG13_NAND3X2 +XB_DEC3<8> B_N1<0> B_P0<0> B_ADDR_DEC<0> net041<23> VDD VSS / ++ RSC_IHPSG13_NAND3X2 +XB_DEC3<7> B_N1<0> B_N0<0> B_ADDR_DEC<7> net041<24> VDD VSS / ++ RSC_IHPSG13_NAND3X2 +XB_DEC3<6> B_N1<0> B_N0<0> B_ADDR_DEC<6> net041<25> VDD VSS / ++ RSC_IHPSG13_NAND3X2 +XB_DEC3<5> B_N1<0> B_N0<0> B_ADDR_DEC<5> net041<26> VDD VSS / ++ RSC_IHPSG13_NAND3X2 +XB_DEC3<4> B_N1<0> B_N0<0> B_ADDR_DEC<4> net041<27> VDD VSS / ++ RSC_IHPSG13_NAND3X2 +XB_DEC3<3> B_N1<0> B_N0<0> B_ADDR_DEC<3> net041<28> VDD VSS / ++ RSC_IHPSG13_NAND3X2 +XB_DEC3<2> B_N1<0> B_N0<0> B_ADDR_DEC<2> net041<29> VDD VSS / ++ RSC_IHPSG13_NAND3X2 +XB_DEC3<1> B_N1<0> B_N0<0> B_ADDR_DEC<1> net041<30> VDD VSS / ++ RSC_IHPSG13_NAND3X2 +XB_DEC3<0> B_N1<0> B_N0<0> B_ADDR_DEC<0> net041<31> VDD VSS / ++ RSC_IHPSG13_NAND3X2 +XA_DEC3<31> A_P1<1> A_P0<1> A_ADDR_DEC<7> net23<0> VDD VSS / ++ RSC_IHPSG13_NAND3X2 +XA_DEC3<30> A_P1<1> A_P0<1> A_ADDR_DEC<6> net23<1> VDD VSS / ++ RSC_IHPSG13_NAND3X2 +XA_DEC3<29> A_P1<1> A_P0<1> A_ADDR_DEC<5> net23<2> VDD VSS / ++ RSC_IHPSG13_NAND3X2 +XA_DEC3<28> A_P1<1> A_P0<1> A_ADDR_DEC<4> net23<3> VDD VSS / ++ RSC_IHPSG13_NAND3X2 +XA_DEC3<27> A_P1<1> A_P0<1> A_ADDR_DEC<3> net23<4> VDD VSS / ++ RSC_IHPSG13_NAND3X2 +XA_DEC3<26> A_P1<1> A_P0<1> A_ADDR_DEC<2> net23<5> VDD VSS / ++ RSC_IHPSG13_NAND3X2 +XA_DEC3<25> A_P1<1> A_P0<1> A_ADDR_DEC<1> net23<6> VDD VSS / ++ RSC_IHPSG13_NAND3X2 +XA_DEC3<24> A_P1<1> A_P0<1> A_ADDR_DEC<0> net23<7> VDD VSS / ++ RSC_IHPSG13_NAND3X2 +XA_DEC3<23> A_P1<1> A_N0<1> A_ADDR_DEC<7> net23<8> VDD VSS / ++ RSC_IHPSG13_NAND3X2 +XA_DEC3<22> A_P1<1> A_N0<1> A_ADDR_DEC<6> net23<9> VDD VSS / ++ RSC_IHPSG13_NAND3X2 +XA_DEC3<21> A_P1<1> A_N0<1> A_ADDR_DEC<5> net23<10> VDD VSS / ++ RSC_IHPSG13_NAND3X2 +XA_DEC3<20> A_P1<1> A_N0<1> A_ADDR_DEC<4> net23<11> VDD VSS / ++ RSC_IHPSG13_NAND3X2 +XA_DEC3<19> A_P1<1> A_N0<1> A_ADDR_DEC<3> net23<12> VDD VSS / ++ RSC_IHPSG13_NAND3X2 +XA_DEC3<18> A_P1<1> A_N0<1> A_ADDR_DEC<2> net23<13> VDD VSS / ++ RSC_IHPSG13_NAND3X2 +XA_DEC3<17> A_P1<1> A_N0<1> A_ADDR_DEC<1> net23<14> VDD VSS / ++ RSC_IHPSG13_NAND3X2 +XA_DEC3<16> A_P1<1> A_N0<1> A_ADDR_DEC<0> net23<15> VDD VSS / ++ RSC_IHPSG13_NAND3X2 +XA_DEC3<15> A_N1<0> A_P0<0> A_ADDR_DEC<7> net23<16> VDD VSS / ++ RSC_IHPSG13_NAND3X2 +XA_DEC3<14> A_N1<0> A_P0<0> A_ADDR_DEC<6> net23<17> VDD VSS / ++ RSC_IHPSG13_NAND3X2 +XA_DEC3<13> A_N1<0> A_P0<0> A_ADDR_DEC<5> net23<18> VDD VSS / ++ RSC_IHPSG13_NAND3X2 +XA_DEC3<12> A_N1<0> A_P0<0> A_ADDR_DEC<4> net23<19> VDD VSS / ++ RSC_IHPSG13_NAND3X2 +XA_DEC3<11> A_N1<0> A_P0<0> A_ADDR_DEC<3> net23<20> VDD VSS / ++ RSC_IHPSG13_NAND3X2 +XA_DEC3<10> A_N1<0> A_P0<0> A_ADDR_DEC<2> net23<21> VDD VSS / ++ RSC_IHPSG13_NAND3X2 +XA_DEC3<9> A_N1<0> A_P0<0> A_ADDR_DEC<1> net23<22> VDD VSS / ++ RSC_IHPSG13_NAND3X2 +XA_DEC3<8> A_N1<0> A_P0<0> A_ADDR_DEC<0> net23<23> VDD VSS / ++ RSC_IHPSG13_NAND3X2 +XA_DEC3<7> A_N1<0> A_N0<0> A_ADDR_DEC<7> net23<24> VDD VSS / ++ RSC_IHPSG13_NAND3X2 +XA_DEC3<6> A_N1<0> A_N0<0> A_ADDR_DEC<6> net23<25> VDD VSS / ++ RSC_IHPSG13_NAND3X2 +XA_DEC3<5> A_N1<0> A_N0<0> A_ADDR_DEC<5> net23<26> VDD VSS / ++ RSC_IHPSG13_NAND3X2 +XA_DEC3<4> A_N1<0> A_N0<0> A_ADDR_DEC<4> net23<27> VDD VSS / ++ RSC_IHPSG13_NAND3X2 +XA_DEC3<3> A_N1<0> A_N0<0> A_ADDR_DEC<3> net23<28> VDD VSS / ++ RSC_IHPSG13_NAND3X2 +XA_DEC3<2> A_N1<0> A_N0<0> A_ADDR_DEC<2> net23<29> VDD VSS / ++ RSC_IHPSG13_NAND3X2 +XA_DEC3<1> A_N1<0> A_N0<0> A_ADDR_DEC<1> net23<30> VDD VSS / ++ RSC_IHPSG13_NAND3X2 +XA_DEC3<0> A_N1<0> A_N0<0> A_ADDR_DEC<0> net23<31> VDD VSS / ++ RSC_IHPSG13_NAND3X2 +XB_I89 B_DCLK_B_L B_DCLK_B_R / RSC_IHPSG13_MET3RES +XB_I91 B_RCLK_B_L B_RCLK_B_R / RSC_IHPSG13_MET3RES +XB_I90 B_WCLK_B_L B_WCLK_B_R / RSC_IHPSG13_MET3RES +XB_I88 B_DCLK_L B_DCLK_R / RSC_IHPSG13_MET3RES +XB_I87 B_WCLK_L B_WCLK_R / RSC_IHPSG13_MET3RES +XB_R2 B_RCLK_L B_RCLK_R / RSC_IHPSG13_MET3RES +XA_I89 A_DCLK_B_L A_DCLK_B_R / RSC_IHPSG13_MET3RES +XA_I91 A_RCLK_B_L A_RCLK_B_R / RSC_IHPSG13_MET3RES +XA_I90 A_WCLK_B_L A_WCLK_B_R / RSC_IHPSG13_MET3RES +XA_I88 A_DCLK_L A_DCLK_R / RSC_IHPSG13_MET3RES +XA_I87 A_WCLK_L A_WCLK_R / RSC_IHPSG13_MET3RES +XA_R2 A_RCLK_L A_RCLK_R / RSC_IHPSG13_MET3RES +XB_BM_TIEH B_TIEH_O VDD VSS / RSC_IHPSG13_TIEH +XA_BM_TIEH A_TIEH_O VDD VSS / RSC_IHPSG13_TIEH +.ENDS +.SUBCKT RM_IHPSG13_256x8_c3_2P_COLDRV13_FILL4 VDD VSS +XI0<11> VDD VSS / RSC_IHPSG13_FILLCAP4 +XI0<10> VDD VSS / RSC_IHPSG13_FILLCAP4 +XI0<9> VDD VSS / RSC_IHPSG13_FILLCAP4 +XI0<8> VDD VSS / RSC_IHPSG13_FILLCAP4 +XI0<7> VDD VSS / RSC_IHPSG13_FILLCAP4 +XI0<6> VDD VSS / RSC_IHPSG13_FILLCAP4 +XI0<5> VDD VSS / RSC_IHPSG13_FILLCAP4 +XI0<4> VDD VSS / RSC_IHPSG13_FILLCAP4 +XI0<3> VDD VSS / RSC_IHPSG13_FILLCAP4 +XI0<2> VDD VSS / RSC_IHPSG13_FILLCAP4 +XI0<1> VDD VSS / RSC_IHPSG13_FILLCAP4 +.ENDS + + +.SUBCKT RSC_IHPSG13_CBUFX16 A Z VDD VSS +MN0 net4 A VSS VSS sg13_lv_nmos m=1 w=2.115u l=130.00n ng=3 nrd=0 nrs=0 +MN1 Z net4 VSS VSS sg13_lv_nmos m=1 w=5.64u l=130.00n ng=8 nrd=0 nrs=0 +MP1 Z net4 VDD VDD sg13_lv_pmos m=1 w=13.000u l=130.00n ng=8 nrd=0 ++ nrs=0 +MP0 net4 A VDD VDD sg13_lv_pmos m=1 w=4.89u l=130.00n ng=3 nrd=0 nrs=0 +.ENDS +.SUBCKT RM_IHPSG13_256x8_c3_1P_COLDRV13X16 ADDR_COL_I<1> ADDR_COL_I<0> ADDR_COL_O<1> ++ ADDR_COL_O<0> ADDR_DEC_I<7> ADDR_DEC_I<6> ADDR_DEC_I<5> ADDR_DEC_I<4> ++ ADDR_DEC_I<3> ADDR_DEC_I<2> ADDR_DEC_I<1> ADDR_DEC_I<0> ADDR_DEC_O<7> ++ ADDR_DEC_O<6> ADDR_DEC_O<5> ADDR_DEC_O<4> ADDR_DEC_O<3> ADDR_DEC_O<2> ++ ADDR_DEC_O<1> ADDR_DEC_O<0> DCLK_I DCLK_O RCLK_I RCLK_O WCLK_I WCLK_O ++ VDD VSS +XI1<1> VDD VSS / RSC_IHPSG13_FILLCAP4 +XI1<0> VDD VSS / RSC_IHPSG13_FILLCAP4 +XI0<3> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI0<2> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI0<1> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI0<0> VDD VSS / RSC_IHPSG13_FILLCAP8 +XADDR_COL_DRV<1> ADDR_COL_I<1> ADDR_COL_O<1> VDD VSS / ++ RSC_IHPSG13_CBUFX16 +XADDR_COL_DRV<0> ADDR_COL_I<0> ADDR_COL_O<0> VDD VSS / ++ RSC_IHPSG13_CBUFX16 +XADDR_DEC_DRV<7> ADDR_DEC_I<7> ADDR_DEC_O<7> VDD VSS / ++ RSC_IHPSG13_CBUFX16 +XADDR_DEC_DRV<6> ADDR_DEC_I<6> ADDR_DEC_O<6> VDD VSS / ++ RSC_IHPSG13_CBUFX16 +XADDR_DEC_DRV<5> ADDR_DEC_I<5> ADDR_DEC_O<5> VDD VSS / ++ RSC_IHPSG13_CBUFX16 +XADDR_DEC_DRV<4> ADDR_DEC_I<4> ADDR_DEC_O<4> VDD VSS / ++ RSC_IHPSG13_CBUFX16 +XADDR_DEC_DRV<3> ADDR_DEC_I<3> ADDR_DEC_O<3> VDD VSS / ++ RSC_IHPSG13_CBUFX16 +XADDR_DEC_DRV<2> ADDR_DEC_I<2> ADDR_DEC_O<2> VDD VSS / ++ RSC_IHPSG13_CBUFX16 +XADDR_DEC_DRV<1> ADDR_DEC_I<1> ADDR_DEC_O<1> VDD VSS / ++ RSC_IHPSG13_CBUFX16 +XADDR_DEC_DRV<0> ADDR_DEC_I<0> ADDR_DEC_O<0> VDD VSS / ++ RSC_IHPSG13_CBUFX16 +XDCLK_DRV DCLK_I DCLK_O VDD VSS / RSC_IHPSG13_CBUFX16 +XRCLK_DRV RCLK_I RCLK_O VDD VSS / RSC_IHPSG13_CBUFX16 +XWCLK_DRV WCLK_I WCLK_O VDD VSS / RSC_IHPSG13_CBUFX16 +.ENDS +.SUBCKT RSC_IHPSG13_WLDRVX16 A Z VDD VSS +MN1 Z net6 VSS VSS sg13_lv_nmos m=1 w=1.41u l=130.00n ng=2 nrd=0 nrs=0 +MN0 net6 A VSS VSS sg13_lv_nmos m=1 w=1.8u l=130.00n ng=2 nrd=0 nrs=0 +MP1 Z net6 VDD VDD sg13_lv_pmos m=1 w=12.96u l=130.00n ng=8 nrd=0 nrs=0 +MP0 net6 A VDD VDD sg13_lv_pmos m=1 w=900.0n l=130.00n ng=1 nrd=0 nrs=0 +.ENDS +.SUBCKT RM_IHPSG13_256x8_c3_1P_WLDRV16X16 A<15> A<14> A<13> A<12> A<11> A<10> A<9> A<8> ++ A<7> A<6> A<5> A<4> A<3> A<2> A<1> A<0> Z<15> Z<14> Z<13> Z<12> Z<11> Z<10> ++ Z<9> Z<8> Z<7> Z<6> Z<5> Z<4> Z<3> Z<2> Z<1> Z<0> VDD VSS +XBUF<15> A<15> Z<15> VDD VSS / RSC_IHPSG13_WLDRVX16 +XBUF<14> A<14> Z<14> VDD VSS / RSC_IHPSG13_WLDRVX16 +XBUF<13> A<13> Z<13> VDD VSS / RSC_IHPSG13_WLDRVX16 +XBUF<12> A<12> Z<12> VDD VSS / RSC_IHPSG13_WLDRVX16 +XBUF<11> A<11> Z<11> VDD VSS / RSC_IHPSG13_WLDRVX16 +XBUF<10> A<10> Z<10> VDD VSS / RSC_IHPSG13_WLDRVX16 +XBUF<9> A<9> Z<9> VDD VSS / RSC_IHPSG13_WLDRVX16 +XBUF<8> A<8> Z<8> VDD VSS / RSC_IHPSG13_WLDRVX16 +XBUF<7> A<7> Z<7> VDD VSS / RSC_IHPSG13_WLDRVX16 +XBUF<6> A<6> Z<6> VDD VSS / RSC_IHPSG13_WLDRVX16 +XBUF<5> A<5> Z<5> VDD VSS / RSC_IHPSG13_WLDRVX16 +XBUF<4> A<4> Z<4> VDD VSS / RSC_IHPSG13_WLDRVX16 +XBUF<3> A<3> Z<3> VDD VSS / RSC_IHPSG13_WLDRVX16 +XBUF<2> A<2> Z<2> VDD VSS / RSC_IHPSG13_WLDRVX16 +XBUF<1> A<1> Z<1> VDD VSS / RSC_IHPSG13_WLDRVX16 +XBUF<0> A<0> Z<0> VDD VSS / RSC_IHPSG13_WLDRVX16 +.ENDS + + +.SUBCKT RM_IHPSG13_256x8_c3_2P_COLDRV13X4 ADDR_COL_I<1> ADDR_COL_I<0> ADDR_COL_O<1> ++ ADDR_COL_O<0> ADDR_DEC_I<7> ADDR_DEC_I<6> ADDR_DEC_I<5> ADDR_DEC_I<4> ++ ADDR_DEC_I<3> ADDR_DEC_I<2> ADDR_DEC_I<1> ADDR_DEC_I<0> ADDR_DEC_O<7> ++ ADDR_DEC_O<6> ADDR_DEC_O<5> ADDR_DEC_O<4> ADDR_DEC_O<3> ADDR_DEC_O<2> ++ ADDR_DEC_O<1> ADDR_DEC_O<0> DCLK_I DCLK_O RCLK_I RCLK_O WCLK_I WCLK_O ++ VDD VSS +XWCLK_DRV WCLK_I WCLK_O VDD VSS / RSC_IHPSG13_CBUFX4 +XRCLK_DRV RCLK_I RCLK_O VDD VSS / RSC_IHPSG13_CBUFX4 +XDCLK_DRV DCLK_I DCLK_O VDD VSS / RSC_IHPSG13_CBUFX4 +XADDR_COL_DRV<1> ADDR_COL_I<1> ADDR_COL_O<1> VDD VSS / ++ RSC_IHPSG13_CBUFX4 +XADDR_COL_DRV<0> ADDR_COL_I<0> ADDR_COL_O<0> VDD VSS / ++ RSC_IHPSG13_CBUFX4 +XADDR_DEC_DRV<7> ADDR_DEC_I<7> ADDR_DEC_O<7> VDD VSS / ++ RSC_IHPSG13_CBUFX4 +XADDR_DEC_DRV<6> ADDR_DEC_I<6> ADDR_DEC_O<6> VDD VSS / ++ RSC_IHPSG13_CBUFX4 +XADDR_DEC_DRV<5> ADDR_DEC_I<5> ADDR_DEC_O<5> VDD VSS / ++ RSC_IHPSG13_CBUFX4 +XADDR_DEC_DRV<4> ADDR_DEC_I<4> ADDR_DEC_O<4> VDD VSS / ++ RSC_IHPSG13_CBUFX4 +XADDR_DEC_DRV<3> ADDR_DEC_I<3> ADDR_DEC_O<3> VDD VSS / ++ RSC_IHPSG13_CBUFX4 +XADDR_DEC_DRV<2> ADDR_DEC_I<2> ADDR_DEC_O<2> VDD VSS / ++ RSC_IHPSG13_CBUFX4 +XADDR_DEC_DRV<1> ADDR_DEC_I<1> ADDR_DEC_O<1> VDD VSS / ++ RSC_IHPSG13_CBUFX4 +XADDR_DEC_DRV<0> ADDR_DEC_I<0> ADDR_DEC_O<0> VDD VSS / ++ RSC_IHPSG13_CBUFX4 +XI0<6> VDD VSS / RSC_IHPSG13_FILLCAP4 +XI0<5> VDD VSS / RSC_IHPSG13_FILLCAP4 +XI0<4> VDD VSS / RSC_IHPSG13_FILLCAP4 +XI0<3> VDD VSS / RSC_IHPSG13_FILLCAP4 +XI0<2> VDD VSS / RSC_IHPSG13_FILLCAP4 +XI0<1> VDD VSS / RSC_IHPSG13_FILLCAP4 +XI1 VDD VSS / RSC_IHPSG13_FILLCAP8 +.ENDS +.SUBCKT RM_IHPSG13_256x8_c3_2P_WLDRV16X4 A<15> A<14> A<13> A<12> A<11> A<10> A<9> A<8> ++ A<7> A<6> A<5> A<4> A<3> A<2> A<1> A<0> Z<15> Z<14> Z<13> Z<12> Z<11> Z<10> ++ Z<9> Z<8> Z<7> Z<6> Z<5> Z<4> Z<3> Z<2> Z<1> Z<0> VDD VSS +XBUF<15> A<15> Z<15> VDD VSS / RSC_IHPSG13_WLDRVX4 +XBUF<14> A<14> Z<14> VDD VSS / RSC_IHPSG13_WLDRVX4 +XBUF<13> A<13> Z<13> VDD VSS / RSC_IHPSG13_WLDRVX4 +XBUF<12> A<12> Z<12> VDD VSS / RSC_IHPSG13_WLDRVX4 +XBUF<11> A<11> Z<11> VDD VSS / RSC_IHPSG13_WLDRVX4 +XBUF<10> A<10> Z<10> VDD VSS / RSC_IHPSG13_WLDRVX4 +XBUF<9> A<9> Z<9> VDD VSS / RSC_IHPSG13_WLDRVX4 +XBUF<8> A<8> Z<8> VDD VSS / RSC_IHPSG13_WLDRVX4 +XBUF<7> A<7> Z<7> VDD VSS / RSC_IHPSG13_WLDRVX4 +XBUF<6> A<6> Z<6> VDD VSS / RSC_IHPSG13_WLDRVX4 +XBUF<5> A<5> Z<5> VDD VSS / RSC_IHPSG13_WLDRVX4 +XBUF<4> A<4> Z<4> VDD VSS / RSC_IHPSG13_WLDRVX4 +XBUF<3> A<3> Z<3> VDD VSS / RSC_IHPSG13_WLDRVX4 +XBUF<2> A<2> Z<2> VDD VSS / RSC_IHPSG13_WLDRVX4 +XBUF<1> A<1> Z<1> VDD VSS / RSC_IHPSG13_WLDRVX4 +XBUF<0> A<0> Z<0> VDD VSS / RSC_IHPSG13_WLDRVX4 +.ENDS +.SUBCKT RM_IHPSG13_256x8_c3_2P_ROWDEC8 ADDR_N_I<7> ADDR_N_I<6> ADDR_N_I<5> ADDR_N_I<4> ++ ADDR_N_I<3> ADDR_N_I<2> ADDR_N_I<1> ADDR_N_I<0> CS_I ECLK_I WL_O<255> ++ WL_O<254> WL_O<253> WL_O<252> WL_O<251> WL_O<250> WL_O<249> WL_O<248> ++ WL_O<247> WL_O<246> WL_O<245> WL_O<244> WL_O<243> WL_O<242> WL_O<241> ++ WL_O<240> WL_O<239> WL_O<238> WL_O<237> WL_O<236> WL_O<235> WL_O<234> ++ WL_O<233> WL_O<232> WL_O<231> WL_O<230> WL_O<229> WL_O<228> WL_O<227> ++ WL_O<226> WL_O<225> WL_O<224> WL_O<223> WL_O<222> WL_O<221> WL_O<220> ++ WL_O<219> WL_O<218> WL_O<217> WL_O<216> WL_O<215> WL_O<214> WL_O<213> ++ WL_O<212> WL_O<211> WL_O<210> WL_O<209> WL_O<208> WL_O<207> WL_O<206> ++ WL_O<205> WL_O<204> WL_O<203> WL_O<202> WL_O<201> WL_O<200> WL_O<199> ++ WL_O<198> WL_O<197> WL_O<196> WL_O<195> WL_O<194> WL_O<193> WL_O<192> ++ WL_O<191> WL_O<190> WL_O<189> WL_O<188> WL_O<187> WL_O<186> WL_O<185> ++ WL_O<184> WL_O<183> WL_O<182> WL_O<181> WL_O<180> WL_O<179> WL_O<178> ++ WL_O<177> WL_O<176> WL_O<175> WL_O<174> WL_O<173> WL_O<172> WL_O<171> ++ WL_O<170> WL_O<169> WL_O<168> WL_O<167> WL_O<166> WL_O<165> WL_O<164> ++ WL_O<163> WL_O<162> WL_O<161> WL_O<160> WL_O<159> WL_O<158> WL_O<157> ++ WL_O<156> WL_O<155> WL_O<154> WL_O<153> WL_O<152> WL_O<151> WL_O<150> ++ WL_O<149> WL_O<148> WL_O<147> WL_O<146> WL_O<145> WL_O<144> WL_O<143> ++ WL_O<142> WL_O<141> WL_O<140> WL_O<139> WL_O<138> WL_O<137> WL_O<136> ++ WL_O<135> WL_O<134> WL_O<133> WL_O<132> WL_O<131> WL_O<130> WL_O<129> ++ WL_O<128> WL_O<127> WL_O<126> WL_O<125> WL_O<124> WL_O<123> WL_O<122> ++ WL_O<121> WL_O<120> WL_O<119> WL_O<118> WL_O<117> WL_O<116> WL_O<115> ++ WL_O<114> WL_O<113> WL_O<112> WL_O<111> WL_O<110> WL_O<109> WL_O<108> ++ WL_O<107> WL_O<106> WL_O<105> WL_O<104> WL_O<103> WL_O<102> WL_O<101> ++ WL_O<100> WL_O<99> WL_O<98> WL_O<97> WL_O<96> WL_O<95> WL_O<94> WL_O<93> ++ WL_O<92> WL_O<91> WL_O<90> WL_O<89> WL_O<88> WL_O<87> WL_O<86> WL_O<85> ++ WL_O<84> WL_O<83> WL_O<82> WL_O<81> WL_O<80> WL_O<79> WL_O<78> WL_O<77> ++ WL_O<76> WL_O<75> WL_O<74> WL_O<73> WL_O<72> WL_O<71> WL_O<70> WL_O<69> ++ WL_O<68> WL_O<67> WL_O<66> WL_O<65> WL_O<64> WL_O<63> WL_O<62> WL_O<61> ++ WL_O<60> WL_O<59> WL_O<58> WL_O<57> WL_O<56> WL_O<55> WL_O<54> WL_O<53> ++ WL_O<52> WL_O<51> WL_O<50> WL_O<49> WL_O<48> WL_O<47> WL_O<46> WL_O<45> ++ WL_O<44> WL_O<43> WL_O<42> WL_O<41> WL_O<40> WL_O<39> WL_O<38> WL_O<37> ++ WL_O<36> WL_O<35> WL_O<34> WL_O<33> WL_O<32> WL_O<31> WL_O<30> WL_O<29> ++ WL_O<28> WL_O<27> WL_O<26> WL_O<25> WL_O<24> WL_O<23> WL_O<22> WL_O<21> ++ WL_O<20> WL_O<19> WL_O<18> WL_O<17> WL_O<16> WL_O<15> WL_O<14> WL_O<13> ++ WL_O<12> WL_O<11> WL_O<10> WL_O<9> WL_O<8> WL_O<7> WL_O<6> WL_O<5> WL_O<4> ++ WL_O<3> WL_O<2> WL_O<1> WL_O<0> VDD VSS +XDEC11<4> ADDR_N_I<7> ADDR_N_I<6> CS_I CS04<3> VDD VSS / ++ RM_IHPSG13_256x8_c3_2P_DEC03 +XDEC11<3> ADDR_N_I<5> ADDR_N_I<4> CS04<3> CS00<15> VDD VSS / ++ RM_IHPSG13_256x8_c3_2P_DEC03 +XDEC11<2> ADDR_N_I<5> ADDR_N_I<4> CS04<2> CS00<11> VDD VSS / ++ RM_IHPSG13_256x8_c3_2P_DEC03 +XDEC11<1> ADDR_N_I<5> ADDR_N_I<4> CS04<1> CS00<7> VDD VSS / ++ RM_IHPSG13_256x8_c3_2P_DEC03 +XDEC11<0> ADDR_N_I<5> ADDR_N_I<4> CS04<0> CS00<3> VDD VSS / ++ RM_IHPSG13_256x8_c3_2P_DEC03 +XSEL<15> ADDR_N_I<3> ADDR_N_I<2> ADDR_N_I<1> ADDR_N_I<0> CS00<15> ECLK_H<15> ++ ECLK_H<16> ECLK_B<15> ECLK_B<16> WL_O<255> WL_O<254> WL_O<253> WL_O<252> ++ WL_O<251> WL_O<250> WL_O<249> WL_O<248> WL_O<247> WL_O<246> WL_O<245> ++ WL_O<244> WL_O<243> WL_O<242> WL_O<241> WL_O<240> VDD VSS / ++ RM_IHPSG13_256x8_c3_2P_DEC04 +XSEL<14> ADDR_N_I<3> ADDR_N_I<2> ADDR_N_I<1> ADDR_N_I<0> CS00<14> ECLK_H<14> ++ ECLK_H<15> ECLK_B<14> ECLK_B<15> WL_O<239> WL_O<238> WL_O<237> WL_O<236> ++ WL_O<235> WL_O<234> WL_O<233> WL_O<232> WL_O<231> WL_O<230> WL_O<229> ++ WL_O<228> WL_O<227> WL_O<226> WL_O<225> WL_O<224> VDD VSS / ++ RM_IHPSG13_256x8_c3_2P_DEC04 +XSEL<13> ADDR_N_I<3> ADDR_N_I<2> ADDR_N_I<1> ADDR_N_I<0> CS00<13> ECLK_H<13> ++ ECLK_H<14> ECLK_B<13> ECLK_B<14> WL_O<223> WL_O<222> WL_O<221> WL_O<220> ++ WL_O<219> WL_O<218> WL_O<217> WL_O<216> WL_O<215> WL_O<214> WL_O<213> ++ WL_O<212> WL_O<211> WL_O<210> WL_O<209> WL_O<208> VDD VSS / ++ RM_IHPSG13_256x8_c3_2P_DEC04 +XSEL<12> ADDR_N_I<3> ADDR_N_I<2> ADDR_N_I<1> ADDR_N_I<0> CS00<12> ECLK_H<12> ++ ECLK_H<13> ECLK_B<12> ECLK_B<13> WL_O<207> WL_O<206> WL_O<205> WL_O<204> ++ WL_O<203> WL_O<202> WL_O<201> WL_O<200> WL_O<199> WL_O<198> WL_O<197> ++ WL_O<196> WL_O<195> WL_O<194> WL_O<193> WL_O<192> VDD VSS / ++ RM_IHPSG13_256x8_c3_2P_DEC04 +XSEL<11> ADDR_N_I<3> ADDR_N_I<2> ADDR_N_I<1> ADDR_N_I<0> CS00<11> ECLK_H<11> ++ ECLK_H<12> ECLK_B<11> ECLK_B<12> WL_O<191> WL_O<190> WL_O<189> WL_O<188> ++ WL_O<187> WL_O<186> WL_O<185> WL_O<184> WL_O<183> WL_O<182> WL_O<181> ++ WL_O<180> WL_O<179> WL_O<178> WL_O<177> WL_O<176> VDD VSS / ++ RM_IHPSG13_256x8_c3_2P_DEC04 +XSEL<10> ADDR_N_I<3> ADDR_N_I<2> ADDR_N_I<1> ADDR_N_I<0> CS00<10> ECLK_H<10> ++ ECLK_H<11> ECLK_B<10> ECLK_B<11> WL_O<175> WL_O<174> WL_O<173> WL_O<172> ++ WL_O<171> WL_O<170> WL_O<169> WL_O<168> WL_O<167> WL_O<166> WL_O<165> ++ WL_O<164> WL_O<163> WL_O<162> WL_O<161> WL_O<160> VDD VSS / ++ RM_IHPSG13_256x8_c3_2P_DEC04 +XSEL<9> ADDR_N_I<3> ADDR_N_I<2> ADDR_N_I<1> ADDR_N_I<0> CS00<9> ECLK_H<9> ++ ECLK_H<10> ECLK_B<9> ECLK_B<10> WL_O<159> WL_O<158> WL_O<157> WL_O<156> ++ WL_O<155> WL_O<154> WL_O<153> WL_O<152> WL_O<151> WL_O<150> WL_O<149> ++ WL_O<148> WL_O<147> WL_O<146> WL_O<145> WL_O<144> VDD VSS / ++ RM_IHPSG13_256x8_c3_2P_DEC04 +XSEL<8> ADDR_N_I<3> ADDR_N_I<2> ADDR_N_I<1> ADDR_N_I<0> CS00<8> ECLK_H<8> ++ ECLK_H<9> ECLK_B<8> ECLK_B<9> WL_O<143> WL_O<142> WL_O<141> WL_O<140> ++ WL_O<139> WL_O<138> WL_O<137> WL_O<136> WL_O<135> WL_O<134> WL_O<133> ++ WL_O<132> WL_O<131> WL_O<130> WL_O<129> WL_O<128> VDD VSS / ++ RM_IHPSG13_256x8_c3_2P_DEC04 +XSEL<7> ADDR_N_I<3> ADDR_N_I<2> ADDR_N_I<1> ADDR_N_I<0> CS00<7> ECLK_H<7> ++ ECLK_H<8> ECLK_B<7> ECLK_B<8> WL_O<127> WL_O<126> WL_O<125> WL_O<124> ++ WL_O<123> WL_O<122> WL_O<121> WL_O<120> WL_O<119> WL_O<118> WL_O<117> ++ WL_O<116> WL_O<115> WL_O<114> WL_O<113> WL_O<112> VDD VSS / ++ RM_IHPSG13_256x8_c3_2P_DEC04 +XSEL<6> ADDR_N_I<3> ADDR_N_I<2> ADDR_N_I<1> ADDR_N_I<0> CS00<6> ECLK_H<6> ++ ECLK_H<7> ECLK_B<6> ECLK_B<7> WL_O<111> WL_O<110> WL_O<109> WL_O<108> ++ WL_O<107> WL_O<106> WL_O<105> WL_O<104> WL_O<103> WL_O<102> WL_O<101> ++ WL_O<100> WL_O<99> WL_O<98> WL_O<97> WL_O<96> VDD VSS / ++ RM_IHPSG13_256x8_c3_2P_DEC04 +XSEL<5> ADDR_N_I<3> ADDR_N_I<2> ADDR_N_I<1> ADDR_N_I<0> CS00<5> ECLK_H<5> ++ ECLK_H<6> ECLK_B<5> ECLK_B<6> WL_O<95> WL_O<94> WL_O<93> WL_O<92> WL_O<91> ++ WL_O<90> WL_O<89> WL_O<88> WL_O<87> WL_O<86> WL_O<85> WL_O<84> WL_O<83> ++ WL_O<82> WL_O<81> WL_O<80> VDD VSS / RM_IHPSG13_256x8_c3_2P_DEC04 +XSEL<4> ADDR_N_I<3> ADDR_N_I<2> ADDR_N_I<1> ADDR_N_I<0> CS00<4> ECLK_H<4> ++ ECLK_H<5> ECLK_B<4> ECLK_B<5> WL_O<79> WL_O<78> WL_O<77> WL_O<76> WL_O<75> ++ WL_O<74> WL_O<73> WL_O<72> WL_O<71> WL_O<70> WL_O<69> WL_O<68> WL_O<67> ++ WL_O<66> WL_O<65> WL_O<64> VDD VSS / RM_IHPSG13_256x8_c3_2P_DEC04 +XSEL<3> ADDR_N_I<3> ADDR_N_I<2> ADDR_N_I<1> ADDR_N_I<0> CS00<3> ECLK_H<3> ++ ECLK_H<4> ECLK_B<3> ECLK_B<4> WL_O<63> WL_O<62> WL_O<61> WL_O<60> WL_O<59> ++ WL_O<58> WL_O<57> WL_O<56> WL_O<55> WL_O<54> WL_O<53> WL_O<52> WL_O<51> ++ WL_O<50> WL_O<49> WL_O<48> VDD VSS / RM_IHPSG13_256x8_c3_2P_DEC04 +XSEL<2> ADDR_N_I<3> ADDR_N_I<2> ADDR_N_I<1> ADDR_N_I<0> CS00<2> ECLK_H<2> ++ ECLK_H<3> ECLK_B<2> ECLK_B<3> WL_O<47> WL_O<46> WL_O<45> WL_O<44> WL_O<43> ++ WL_O<42> WL_O<41> WL_O<40> WL_O<39> WL_O<38> WL_O<37> WL_O<36> WL_O<35> ++ WL_O<34> WL_O<33> WL_O<32> VDD VSS / RM_IHPSG13_256x8_c3_2P_DEC04 +XSEL<1> ADDR_N_I<3> ADDR_N_I<2> ADDR_N_I<1> ADDR_N_I<0> CS00<1> ECLK_H<1> ++ ECLK_H<2> ECLK_B<1> ECLK_B<2> WL_O<31> WL_O<30> WL_O<29> WL_O<28> WL_O<27> ++ WL_O<26> WL_O<25> WL_O<24> WL_O<23> WL_O<22> WL_O<21> WL_O<20> WL_O<19> ++ WL_O<18> WL_O<17> WL_O<16> VDD VSS / RM_IHPSG13_256x8_c3_2P_DEC04 +XSEL<0> ADDR_N_I<3> ADDR_N_I<2> ADDR_N_I<1> ADDR_N_I<0> CS00<0> ECLK_I ++ ECLK_H<1> ECLK_B<0> ECLK_B<1> WL_O<15> WL_O<14> WL_O<13> WL_O<12> WL_O<11> ++ WL_O<10> WL_O<9> WL_O<8> WL_O<7> WL_O<6> WL_O<5> WL_O<4> WL_O<3> WL_O<2> ++ WL_O<1> WL_O<0> VDD VSS / RM_IHPSG13_256x8_c3_2P_DEC04 +XDEC10<4> ADDR_N_I<7> ADDR_N_I<6> CS_I CS04<2> VDD VSS / ++ RM_IHPSG13_256x8_c3_2P_DEC02 +XDEC10<3> ADDR_N_I<5> ADDR_N_I<4> CS04<3> CS00<14> VDD VSS / ++ RM_IHPSG13_256x8_c3_2P_DEC02 +XDEC10<2> ADDR_N_I<5> ADDR_N_I<4> CS04<2> CS00<10> VDD VSS / ++ RM_IHPSG13_256x8_c3_2P_DEC02 +XDEC10<1> ADDR_N_I<5> ADDR_N_I<4> CS04<1> CS00<6> VDD VSS / ++ RM_IHPSG13_256x8_c3_2P_DEC02 +XDEC10<0> ADDR_N_I<5> ADDR_N_I<4> CS04<0> CS00<2> VDD VSS / ++ RM_IHPSG13_256x8_c3_2P_DEC02 +XL2<132> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<131> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<130> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<129> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<128> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<127> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<126> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<125> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<124> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<123> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<122> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<121> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<120> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<119> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<118> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<117> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<116> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<115> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<114> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<113> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<112> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<111> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<110> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<109> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<108> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<107> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<106> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<105> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<104> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<103> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<102> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<101> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<100> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<99> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<98> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<97> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<96> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<95> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<94> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<93> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<92> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<91> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<90> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<89> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<88> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<87> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<86> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<85> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<84> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<83> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<82> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<81> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<80> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<79> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<78> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<77> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<76> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<75> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<74> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<73> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<72> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<71> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<70> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<69> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<68> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<67> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<66> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<65> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<64> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<63> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<62> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<61> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<60> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<59> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<58> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<57> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<56> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<55> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<54> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<53> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<52> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<51> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<50> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<49> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<48> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<47> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<46> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<45> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<44> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<43> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<42> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<41> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<40> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<39> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<38> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<37> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<36> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<35> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<34> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<33> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<32> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<31> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<30> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<29> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<28> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<27> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<26> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<25> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<24> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<23> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<22> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<21> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<20> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<19> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<18> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<17> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<16> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<15> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<14> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<13> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<12> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<11> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<10> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<9> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<8> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<7> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<6> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<5> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<4> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<3> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<2> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<1> VDD VSS / RSC_IHPSG13_FILLCAP8 +XDEC00<4> ADDR_N_I<7> ADDR_N_I<6> CS_I CS04<0> VDD VSS / ++ RM_IHPSG13_256x8_c3_2P_DEC00 +XDEC00<3> ADDR_N_I<5> ADDR_N_I<4> CS04<3> CS00<12> VDD VSS / ++ RM_IHPSG13_256x8_c3_2P_DEC00 +XDEC00<2> ADDR_N_I<5> ADDR_N_I<4> CS04<2> CS00<8> VDD VSS / ++ RM_IHPSG13_256x8_c3_2P_DEC00 +XDEC00<1> ADDR_N_I<5> ADDR_N_I<4> CS04<1> CS00<4> VDD VSS / ++ RM_IHPSG13_256x8_c3_2P_DEC00 +XDEC00<0> ADDR_N_I<5> ADDR_N_I<4> CS04<0> CS00<0> VDD VSS / ++ RM_IHPSG13_256x8_c3_2P_DEC00 +XDEC01<4> ADDR_N_I<7> ADDR_N_I<6> CS_I CS04<1> VDD VSS / ++ RM_IHPSG13_256x8_c3_2P_DEC01 +XDEC01<3> ADDR_N_I<5> ADDR_N_I<4> CS04<3> CS00<13> VDD VSS / ++ RM_IHPSG13_256x8_c3_2P_DEC01 +XDEC01<2> ADDR_N_I<5> ADDR_N_I<4> CS04<2> CS00<9> VDD VSS / ++ RM_IHPSG13_256x8_c3_2P_DEC01 +XDEC01<1> ADDR_N_I<5> ADDR_N_I<4> CS04<1> CS00<5> VDD VSS / ++ RM_IHPSG13_256x8_c3_2P_DEC01 +XDEC01<0> ADDR_N_I<5> ADDR_N_I<4> CS04<0> CS00<1> VDD VSS / ++ RM_IHPSG13_256x8_c3_2P_DEC01 +.ENDS +.SUBCKT RM_IHPSG13_256x8_c3_2P_ROWREG8 ACLK_N_I ADDR_I<7> ADDR_I<6> ADDR_I<5> ADDR_I<4> ++ ADDR_I<3> ADDR_I<2> ADDR_I<1> ADDR_I<0> ADDR_N_O<7> ADDR_N_O<6> ADDR_N_O<5> ++ ADDR_N_O<4> ADDR_N_O<3> ADDR_N_O<2> ADDR_N_O<1> ADDR_N_O<0> BIST_ADDR_I<7> ++ BIST_ADDR_I<6> BIST_ADDR_I<5> BIST_ADDR_I<4> BIST_ADDR_I<3> BIST_ADDR_I<2> ++ BIST_ADDR_I<1> BIST_ADDR_I<0> BIST_EN_I VDD VSS +XINV<7> q_int<7> qn_int<7> VDD VSS / RSC_IHPSG13_CINVX2 +XINV<6> q_int<6> qn_int<6> VDD VSS / RSC_IHPSG13_CINVX2 +XINV<5> q_int<5> qn_int<5> VDD VSS / RSC_IHPSG13_CINVX2 +XINV<4> q_int<4> qn_int<4> VDD VSS / RSC_IHPSG13_CINVX2 +XINV<3> q_int<3> qn_int<3> VDD VSS / RSC_IHPSG13_CINVX2 +XINV<2> q_int<2> qn_int<2> VDD VSS / RSC_IHPSG13_CINVX2 +XINV<1> q_int<1> qn_int<1> VDD VSS / RSC_IHPSG13_CINVX2 +XINV<0> q_int<0> qn_int<0> VDD VSS / RSC_IHPSG13_CINVX2 +XDRV<7> qn_int<7> ADDR_N_O<7> VDD VSS / RSC_IHPSG13_CINVX8 +XDRV<6> qn_int<6> ADDR_N_O<6> VDD VSS / RSC_IHPSG13_CINVX8 +XDRV<5> qn_int<5> ADDR_N_O<5> VDD VSS / RSC_IHPSG13_CINVX8 +XDRV<4> qn_int<4> ADDR_N_O<4> VDD VSS / RSC_IHPSG13_CINVX8 +XDRV<3> qn_int<3> ADDR_N_O<3> VDD VSS / RSC_IHPSG13_CINVX8 +XDRV<2> qn_int<2> ADDR_N_O<2> VDD VSS / RSC_IHPSG13_CINVX8 +XDRV<1> qn_int<1> ADDR_N_O<1> VDD VSS / RSC_IHPSG13_CINVX8 +XDRV<0> qn_int<0> ADDR_N_O<0> VDD VSS / RSC_IHPSG13_CINVX8 +XDFF<7> BIST_EN_I BIST_ADDR_I<7> ACLK_N_I ADDR_I<7> q_int<7> net2<0> VDD ++ VSS / RSC_IHPSG13_DFNQMX2IX1 +XDFF<6> BIST_EN_I BIST_ADDR_I<6> ACLK_N_I ADDR_I<6> q_int<6> net2<1> VDD ++ VSS / RSC_IHPSG13_DFNQMX2IX1 +XDFF<5> BIST_EN_I BIST_ADDR_I<5> ACLK_N_I ADDR_I<5> q_int<5> net2<2> VDD ++ VSS / RSC_IHPSG13_DFNQMX2IX1 +XDFF<4> BIST_EN_I BIST_ADDR_I<4> ACLK_N_I ADDR_I<4> q_int<4> net2<3> VDD ++ VSS / RSC_IHPSG13_DFNQMX2IX1 +XDFF<3> BIST_EN_I BIST_ADDR_I<3> ACLK_N_I ADDR_I<3> q_int<3> net2<4> VDD ++ VSS / RSC_IHPSG13_DFNQMX2IX1 +XDFF<2> BIST_EN_I BIST_ADDR_I<2> ACLK_N_I ADDR_I<2> q_int<2> net2<5> VDD ++ VSS / RSC_IHPSG13_DFNQMX2IX1 +XDFF<1> BIST_EN_I BIST_ADDR_I<1> ACLK_N_I ADDR_I<1> q_int<1> net2<6> VDD ++ VSS / RSC_IHPSG13_DFNQMX2IX1 +XDFF<0> BIST_EN_I BIST_ADDR_I<0> ACLK_N_I ADDR_I<0> q_int<0> net2<7> VDD ++ VSS / RSC_IHPSG13_DFNQMX2IX1 +XI11<4> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI11<3> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI11<2> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI11<1> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI10 VDD VSS / RSC_IHPSG13_FILLCAP4 +.ENDS +.SUBCKT RM_IHPSG13_256x8_c3_2P_COLDEC4 ACLK_N ADDR<3> ADDR<2> ADDR<1> ADDR<0> ++ ADDR_COL<1> ADDR_COL<0> ADDR_DEC<7> ADDR_DEC<6> ADDR_DEC<5> ADDR_DEC<4> ++ ADDR_DEC<3> ADDR_DEC<2> ADDR_DEC<1> ADDR_DEC<0> BIST_ADDR<3> BIST_ADDR<2> ++ BIST_ADDR<1> BIST_ADDR<0> BIST_EN_I VDD VSS +XI1<7> PADR<0> PADR<1> PADR<2> addr_n<7> VDD VSS / RSC_IHPSG13_NAND3X2 +XI1<6> NADR<0> PADR<1> PADR<2> addr_n<6> VDD VSS / RSC_IHPSG13_NAND3X2 +XI1<5> PADR<0> NADR<1> PADR<2> addr_n<5> VDD VSS / RSC_IHPSG13_NAND3X2 +XI1<4> NADR<0> NADR<1> PADR<2> addr_n<4> VDD VSS / RSC_IHPSG13_NAND3X2 +XI1<3> PADR<0> PADR<1> NADR<2> addr_n<3> VDD VSS / RSC_IHPSG13_NAND3X2 +XI1<2> NADR<0> PADR<1> NADR<2> addr_n<2> VDD VSS / RSC_IHPSG13_NAND3X2 +XI1<1> PADR<0> NADR<1> NADR<2> addr_n<1> VDD VSS / RSC_IHPSG13_NAND3X2 +XI1<0> NADR<0> NADR<1> NADR<2> addr_n<0> VDD VSS / RSC_IHPSG13_NAND3X2 +XDFF<3> BIST_EN_I BIST_ADDR<3> ACLK_N ADDR<3> addr_int net12<0> VDD ++ VSS / RSC_IHPSG13_DFNQMX2IX1 +XDFF<2> BIST_EN_I BIST_ADDR<2> ACLK_N ADDR<2> padr_int<2> net12<1> VDD ++ VSS / RSC_IHPSG13_DFNQMX2IX1 +XDFF<1> BIST_EN_I BIST_ADDR<1> ACLK_N ADDR<1> padr_int<1> net12<2> VDD ++ VSS / RSC_IHPSG13_DFNQMX2IX1 +XDFF<0> BIST_EN_I BIST_ADDR<0> ACLK_N ADDR<0> padr_int<0> net12<3> VDD ++ VSS / RSC_IHPSG13_DFNQMX2IX1 +XI17<4> VDD VSS / RSC_IHPSG13_FILLCAP4 +XI17<3> VDD VSS / RSC_IHPSG13_FILLCAP4 +XI17<2> VDD VSS / RSC_IHPSG13_FILLCAP4 +XI17<1> VDD VSS / RSC_IHPSG13_FILLCAP4 +XI13<2> NADR<2> PADR<2> VDD VSS / RSC_IHPSG13_INVX2 +XI13<1> NADR<1> PADR<1> VDD VSS / RSC_IHPSG13_INVX2 +XI13<0> NADR<0> PADR<0> VDD VSS / RSC_IHPSG13_INVX2 +XI2<7> addr_n<7> ADDR_DEC<7> VDD VSS / RSC_IHPSG13_INVX2 +XI2<6> addr_n<6> ADDR_DEC<6> VDD VSS / RSC_IHPSG13_INVX2 +XI2<5> addr_n<5> ADDR_DEC<5> VDD VSS / RSC_IHPSG13_INVX2 +XI2<4> addr_n<4> ADDR_DEC<4> VDD VSS / RSC_IHPSG13_INVX2 +XI2<3> addr_n<3> ADDR_DEC<3> VDD VSS / RSC_IHPSG13_INVX2 +XI2<2> addr_n<2> ADDR_DEC<2> VDD VSS / RSC_IHPSG13_INVX2 +XI2<1> addr_n<1> ADDR_DEC<1> VDD VSS / RSC_IHPSG13_INVX2 +XI2<0> addr_n<0> ADDR_DEC<0> VDD VSS / RSC_IHPSG13_INVX2 +XI3<2> padr_int<2> NADR<2> VDD VSS / RSC_IHPSG13_INVX2 +XI3<1> padr_int<1> NADR<1> VDD VSS / RSC_IHPSG13_INVX2 +XI3<0> padr_int<0> NADR<0> VDD VSS / RSC_IHPSG13_INVX2 +XI14 addr_int ADDR_COL<0> VDD VSS / RSC_IHPSG13_CBUFX2 +XI16<8> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI16<7> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI16<6> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI16<5> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI16<4> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI16<3> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI16<2> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI16<1> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI15 ADDR_COL<1> VDD VSS / RSC_IHPSG13_TIEL +.ENDS +.SUBCKT RM_IHPSG13_256x8_c3_2P_COLCTRL4 A_ADDR_COL A_ADDR_DEC<7> A_ADDR_DEC<6> ++ A_ADDR_DEC<5> A_ADDR_DEC<4> A_ADDR_DEC<3> A_ADDR_DEC<2> A_ADDR_DEC<1> ++ A_ADDR_DEC<0> A_BIST_BM_I A_BIST_DW_I A_BIST_EN_I A_BLC<15> A_BLC<14> ++ A_BLC<13> A_BLC<12> A_BLC<11> A_BLC<10> A_BLC<9> A_BLC<8> A_BLC<7> A_BLC<6> ++ A_BLC<5> A_BLC<4> A_BLC<3> A_BLC<2> A_BLC<1> A_BLC<0> A_BLT<15> A_BLT<14> ++ A_BLT<13> A_BLT<12> A_BLT<11> A_BLT<10> A_BLT<9> A_BLT<8> A_BLT<7> A_BLT<6> ++ A_BLT<5> A_BLT<4> A_BLT<3> A_BLT<2> A_BLT<1> A_BLT<0> A_BM_I A_DCLK_B_L ++ A_DCLK_B_R A_DCLK_L A_DCLK_R A_DR_O A_DW_I A_RCLK_B_L A_RCLK_B_R A_RCLK_L ++ A_RCLK_R A_TIEH_O A_WCLK_B_L A_WCLK_B_R A_WCLK_L A_WCLK_R B_ADDR_COL ++ B_ADDR_DEC<7> B_ADDR_DEC<6> B_ADDR_DEC<5> B_ADDR_DEC<4> B_ADDR_DEC<3> ++ B_ADDR_DEC<2> B_ADDR_DEC<1> B_ADDR_DEC<0> B_BIST_BM_I B_BIST_DW_I ++ B_BIST_EN_I B_BLC<15> B_BLC<14> B_BLC<13> B_BLC<12> B_BLC<11> B_BLC<10> ++ B_BLC<9> B_BLC<8> B_BLC<7> B_BLC<6> B_BLC<5> B_BLC<4> B_BLC<3> B_BLC<2> ++ B_BLC<1> B_BLC<0> B_BLT<15> B_BLT<14> B_BLT<13> B_BLT<12> B_BLT<11> ++ B_BLT<10> B_BLT<9> B_BLT<8> B_BLT<7> B_BLT<6> B_BLT<5> B_BLT<4> B_BLT<3> ++ B_BLT<2> B_BLT<1> B_BLT<0> B_BM_I B_DCLK_B_L B_DCLK_B_R B_DCLK_L B_DCLK_R ++ B_DR_O B_DW_I B_RCLK_B_L B_RCLK_B_R B_RCLK_L B_RCLK_R B_TIEH_O B_WCLK_B_L ++ B_WCLK_B_R B_WCLK_L B_WCLK_R VDD VSS +XB_I80 B_RCLK_B_L B_WCLK_B_L net041 VDD VSS / RSC_IHPSG13_AND2X2 +XA_I80 A_RCLK_B_L A_WCLK_B_L net21 VDD VSS / RSC_IHPSG13_AND2X2 +XB_I76 B_DI_N B_DO_WRITE_P B_WR_ZERO VDD VSS / RSC_IHPSG13_AND2X4 +XB_I75 B_DI_R B_DO_WRITE_P B_WR_ONE VDD VSS / RSC_IHPSG13_AND2X4 +XA_I76 A_DI_N A_DO_WRITE_P A_WR_ZERO VDD VSS / RSC_IHPSG13_AND2X4 +XA_I75 A_DI_R A_DO_WRITE_P A_WR_ONE VDD VSS / RSC_IHPSG13_AND2X4 +XI_FILL4<26> VDD VSS / RSC_IHPSG13_FILLCAP4 +XI_FILL4<25> VDD VSS / RSC_IHPSG13_FILLCAP4 +XI_FILL4<24> VDD VSS / RSC_IHPSG13_FILLCAP4 +XI_FILL4<23> VDD VSS / RSC_IHPSG13_FILLCAP4 +XI_FILL4<22> VDD VSS / RSC_IHPSG13_FILLCAP4 +XI_FILL4<21> VDD VSS / RSC_IHPSG13_FILLCAP4 +XI_FILL4<20> VDD VSS / RSC_IHPSG13_FILLCAP4 +XI_FILL4<19> VDD VSS / RSC_IHPSG13_FILLCAP4 +XI_FILL4<18> VDD VSS / RSC_IHPSG13_FILLCAP4 +XI_FILL4<17> VDD VSS / RSC_IHPSG13_FILLCAP4 +XI_FILL4<16> VDD VSS / RSC_IHPSG13_FILLCAP4 +XI_FILL4<15> VDD VSS / RSC_IHPSG13_FILLCAP4 +XI_FILL4<14> VDD VSS / RSC_IHPSG13_FILLCAP4 +XI_FILL4<13> VDD VSS / RSC_IHPSG13_FILLCAP4 +XI_FILL4<12> VDD VSS / RSC_IHPSG13_FILLCAP4 +XI_FILL4<11> VDD VSS / RSC_IHPSG13_FILLCAP4 +XI_FILL4<10> VDD VSS / RSC_IHPSG13_FILLCAP4 +XI_FILL4<9> VDD VSS / RSC_IHPSG13_FILLCAP4 +XI_FILL4<8> VDD VSS / RSC_IHPSG13_FILLCAP4 +XI_FILL4<7> VDD VSS / RSC_IHPSG13_FILLCAP4 +XI_FILL4<6> VDD VSS / RSC_IHPSG13_FILLCAP4 +XI_FILL4<5> VDD VSS / RSC_IHPSG13_FILLCAP4 +XI_FILL4<4> VDD VSS / RSC_IHPSG13_FILLCAP4 +XI_FILL4<3> VDD VSS / RSC_IHPSG13_FILLCAP4 +XI_FILL4<2> VDD VSS / RSC_IHPSG13_FILLCAP4 +XI_FILL4<1> VDD VSS / RSC_IHPSG13_FILLCAP4 +XB_I69 B_DCLK_L B_DCLK_B_L VDD VSS / RSC_IHPSG13_CINVX4 +XB_I50 B_WCLK_L B_WCLK_B_L VDD VSS / RSC_IHPSG13_CINVX4 +XB_EBUF B_RCLK_L B_RCLK_B_L VDD VSS / RSC_IHPSG13_CINVX4 +XB_INV<1> B_N0 B_P0 VDD VSS / RSC_IHPSG13_CINVX4 +XB_INV<0> B_ADDR_COL B_N0 VDD VSS / RSC_IHPSG13_CINVX4 +XA_I69 A_DCLK_L A_DCLK_B_L VDD VSS / RSC_IHPSG13_CINVX4 +XA_I50 A_WCLK_L A_WCLK_B_L VDD VSS / RSC_IHPSG13_CINVX4 +XA_EBUF A_RCLK_L A_RCLK_B_L VDD VSS / RSC_IHPSG13_CINVX4 +XA_INV<1> A_N0 A_P0 VDD VSS / RSC_IHPSG13_CINVX4 +XA_INV<0> A_ADDR_COL A_N0 VDD VSS / RSC_IHPSG13_CINVX4 +XB_I81<1> net041 B_PRE_N VDD VSS / RSC_IHPSG13_CINVX4_WN +XB_I81<0> net041 B_PRE_N VDD VSS / RSC_IHPSG13_CINVX4_WN +XA_I81<1> net21 A_PRE_N VDD VSS / RSC_IHPSG13_CINVX4_WN +XA_I81<0> net21 A_PRE_N VDD VSS / RSC_IHPSG13_CINVX4_WN +XA_R2 A_RCLK_L A_RCLK_R / RSC_IHPSG13_MET3RES +XA_I87 A_WCLK_L A_WCLK_R / RSC_IHPSG13_MET3RES +XA_I88 A_DCLK_L A_DCLK_R / RSC_IHPSG13_MET3RES +XA_I89 A_DCLK_B_L A_DCLK_B_R / RSC_IHPSG13_MET3RES +XA_I90 A_WCLK_B_L A_WCLK_B_R / RSC_IHPSG13_MET3RES +XA_I91 A_RCLK_B_L A_RCLK_B_R / RSC_IHPSG13_MET3RES +XB_R2 B_RCLK_L B_RCLK_R / RSC_IHPSG13_MET3RES +XB_I87 B_WCLK_L B_WCLK_R / RSC_IHPSG13_MET3RES +XB_I88 B_DCLK_L B_DCLK_R / RSC_IHPSG13_MET3RES +XB_I89 B_DCLK_B_L B_DCLK_B_R / RSC_IHPSG13_MET3RES +XB_I90 B_WCLK_B_L B_WCLK_B_R / RSC_IHPSG13_MET3RES +XB_I91 B_RCLK_B_L B_RCLK_B_R / RSC_IHPSG13_MET3RES +XA_ISENSE A_SAE A_BLC_SEL A_BLT_SEL net19 net20 VDD VSS / ++ RSC_IHPSG13_DFPQD_MSAFFX2 +XB_ISENSE B_SAE B_BLC_SEL B_BLT_SEL net037 net038 VDD VSS / ++ RSC_IHPSG13_DFPQD_MSAFFX2 +XAB_BLMUX<3> A_BLC<15> A_BLC<14> A_BLC<13> A_BLC<12> A_BLC_SEL A_BLT<15> ++ A_BLT<14> A_BLT<13> A_BLT<12> A_BLT_SEL A_PRE_N A_SEL_P<15> A_SEL_P<14> ++ A_SEL_P<13> A_SEL_P<12> A_WR_ONE A_WR_ZERO B_BLC<15> B_BLC<14> B_BLC<13> ++ B_BLC<12> B_BLC_SEL B_BLT<15> B_BLT<14> B_BLT<13> B_BLT<12> B_BLT_SEL ++ B_PRE_N B_SEL_P<15> B_SEL_P<14> B_SEL_P<13> B_SEL_P<12> B_WR_ONE B_WR_ZERO ++ VDD VSS / RM_IHPSG13_256x8_c3_2P_BLDRV +XAB_BLMUX<2> A_BLC<11> A_BLC<10> A_BLC<9> A_BLC<8> A_BLC_SEL A_BLT<11> ++ A_BLT<10> A_BLT<9> A_BLT<8> A_BLT_SEL A_PRE_N A_SEL_P<11> A_SEL_P<10> ++ A_SEL_P<9> A_SEL_P<8> A_WR_ONE A_WR_ZERO B_BLC<11> B_BLC<10> B_BLC<9> ++ B_BLC<8> B_BLC_SEL B_BLT<11> B_BLT<10> B_BLT<9> B_BLT<8> B_BLT_SEL B_PRE_N ++ B_SEL_P<11> B_SEL_P<10> B_SEL_P<9> B_SEL_P<8> B_WR_ONE B_WR_ZERO VDD ++ VSS / RM_IHPSG13_256x8_c3_2P_BLDRV +XAB_BLMUX<1> A_BLC<7> A_BLC<6> A_BLC<5> A_BLC<4> A_BLC_SEL A_BLT<7> A_BLT<6> ++ A_BLT<5> A_BLT<4> A_BLT_SEL A_PRE_N A_SEL_P<7> A_SEL_P<6> A_SEL_P<5> ++ A_SEL_P<4> A_WR_ONE A_WR_ZERO B_BLC<7> B_BLC<6> B_BLC<5> B_BLC<4> B_BLC_SEL ++ B_BLT<7> B_BLT<6> B_BLT<5> B_BLT<4> B_BLT_SEL B_PRE_N B_SEL_P<7> B_SEL_P<6> ++ B_SEL_P<5> B_SEL_P<4> B_WR_ONE B_WR_ZERO VDD VSS / ++ RM_IHPSG13_256x8_c3_2P_BLDRV +XAB_BLMUX<0> A_BLC<3> A_BLC<2> A_BLC<1> A_BLC<0> A_BLC_SEL A_BLT<3> A_BLT<2> ++ A_BLT<1> A_BLT<0> A_BLT_SEL A_PRE_N A_SEL_P<3> A_SEL_P<2> A_SEL_P<1> ++ A_SEL_P<0> A_WR_ONE A_WR_ZERO B_BLC<3> B_BLC<2> B_BLC<1> B_BLC<0> B_BLC_SEL ++ B_BLT<3> B_BLT<2> B_BLT<1> B_BLT<0> B_BLT_SEL B_PRE_N B_SEL_P<3> B_SEL_P<2> ++ B_SEL_P<1> B_SEL_P<0> B_WR_ONE B_WR_ZERO VDD VSS / ++ RM_IHPSG13_256x8_c3_2P_BLDRV +XA_I51 net19 A_DR_O VDD VSS / RSC_IHPSG13_INVX4 +XB_I51 net037 B_DR_O VDD VSS / RSC_IHPSG13_INVX4 +XA_I78 A_RCLK_B_L A_SAE VDD VSS / RSC_IHPSG13_CBUFX2 +XB_I78 B_RCLK_B_L B_SAE VDD VSS / RSC_IHPSG13_CBUFX2 +XA_DREG A_BIST_EN_I A_BIST_DW_I A_DCLK_B_L A_DW_I A_DI_R net22 VDD VSS ++ / RSC_IHPSG13_DFNQMX2IX1 +XB_DREG B_BIST_EN_I B_BIST_DW_I B_DCLK_B_L B_DW_I B_DI_R net046 VDD ++ VSS / RSC_IHPSG13_DFNQMX2IX1 +XB_BREG B_BIST_EN_I B_BIST_BM_I B_DCLK_B_L B_BM_I B_BM_R net045 VDD ++ VSS / RSC_IHPSG13_DFNQMX2IX1 +XA_BREG A_BIST_EN_I A_BIST_BM_I A_DCLK_B_L A_BM_I A_BM_R net24 VDD VSS ++ / RSC_IHPSG13_DFNQMX2IX1 +XA_DEC3INV<15> net23<0> A_SEL_P<15> VDD VSS / RSC_IHPSG13_INVX2 +XA_DEC3INV<14> net23<1> A_SEL_P<14> VDD VSS / RSC_IHPSG13_INVX2 +XA_DEC3INV<13> net23<2> A_SEL_P<13> VDD VSS / RSC_IHPSG13_INVX2 +XA_DEC3INV<12> net23<3> A_SEL_P<12> VDD VSS / RSC_IHPSG13_INVX2 +XA_DEC3INV<11> net23<4> A_SEL_P<11> VDD VSS / RSC_IHPSG13_INVX2 +XA_DEC3INV<10> net23<5> A_SEL_P<10> VDD VSS / RSC_IHPSG13_INVX2 +XA_DEC3INV<9> net23<6> A_SEL_P<9> VDD VSS / RSC_IHPSG13_INVX2 +XA_DEC3INV<8> net23<7> A_SEL_P<8> VDD VSS / RSC_IHPSG13_INVX2 +XA_DEC3INV<7> net23<8> A_SEL_P<7> VDD VSS / RSC_IHPSG13_INVX2 +XA_DEC3INV<6> net23<9> A_SEL_P<6> VDD VSS / RSC_IHPSG13_INVX2 +XA_DEC3INV<5> net23<10> A_SEL_P<5> VDD VSS / RSC_IHPSG13_INVX2 +XA_DEC3INV<4> net23<11> A_SEL_P<4> VDD VSS / RSC_IHPSG13_INVX2 +XA_DEC3INV<3> net23<12> A_SEL_P<3> VDD VSS / RSC_IHPSG13_INVX2 +XA_DEC3INV<2> net23<13> A_SEL_P<2> VDD VSS / RSC_IHPSG13_INVX2 +XA_DEC3INV<1> net23<14> A_SEL_P<1> VDD VSS / RSC_IHPSG13_INVX2 +XA_DEC3INV<0> net23<15> A_SEL_P<0> VDD VSS / RSC_IHPSG13_INVX2 +XA_I83 A_BM_R A_BM_N VDD VSS / RSC_IHPSG13_INVX2 +XA_I49 A_DI_R A_DI_N VDD VSS / RSC_IHPSG13_INVX2 +XB_DEC3INV<15> net044<0> B_SEL_P<15> VDD VSS / RSC_IHPSG13_INVX2 +XB_DEC3INV<14> net044<1> B_SEL_P<14> VDD VSS / RSC_IHPSG13_INVX2 +XB_DEC3INV<13> net044<2> B_SEL_P<13> VDD VSS / RSC_IHPSG13_INVX2 +XB_DEC3INV<12> net044<3> B_SEL_P<12> VDD VSS / RSC_IHPSG13_INVX2 +XB_DEC3INV<11> net044<4> B_SEL_P<11> VDD VSS / RSC_IHPSG13_INVX2 +XB_DEC3INV<10> net044<5> B_SEL_P<10> VDD VSS / RSC_IHPSG13_INVX2 +XB_DEC3INV<9> net044<6> B_SEL_P<9> VDD VSS / RSC_IHPSG13_INVX2 +XB_DEC3INV<8> net044<7> B_SEL_P<8> VDD VSS / RSC_IHPSG13_INVX2 +XB_DEC3INV<7> net044<8> B_SEL_P<7> VDD VSS / RSC_IHPSG13_INVX2 +XB_DEC3INV<6> net044<9> B_SEL_P<6> VDD VSS / RSC_IHPSG13_INVX2 +XB_DEC3INV<5> net044<10> B_SEL_P<5> VDD VSS / RSC_IHPSG13_INVX2 +XB_DEC3INV<4> net044<11> B_SEL_P<4> VDD VSS / RSC_IHPSG13_INVX2 +XB_DEC3INV<3> net044<12> B_SEL_P<3> VDD VSS / RSC_IHPSG13_INVX2 +XB_DEC3INV<2> net044<13> B_SEL_P<2> VDD VSS / RSC_IHPSG13_INVX2 +XB_DEC3INV<1> net044<14> B_SEL_P<1> VDD VSS / RSC_IHPSG13_INVX2 +XB_DEC3INV<0> net044<15> B_SEL_P<0> VDD VSS / RSC_IHPSG13_INVX2 +XB_I83 B_BM_R B_BM_N VDD VSS / RSC_IHPSG13_INVX2 +XB_I49 B_DI_R B_DI_N VDD VSS / RSC_IHPSG13_INVX2 +XI_FILL8<20> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI_FILL8<19> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI_FILL8<18> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI_FILL8<17> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI_FILL8<16> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI_FILL8<15> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI_FILL8<14> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI_FILL8<13> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI_FILL8<12> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI_FILL8<11> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI_FILL8<10> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI_FILL8<9> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI_FILL8<8> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI_FILL8<7> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI_FILL8<6> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI_FILL8<5> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI_FILL8<4> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI_FILL8<3> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI_FILL8<2> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI_FILL8<1> VDD VSS / RSC_IHPSG13_FILLCAP8 +XA_I44 A_BM_N A_WCLK_B_L A_DO_WRITE_P VDD VSS / RSC_IHPSG13_NOR2X2 +XB_I44 B_BM_N B_WCLK_B_L B_DO_WRITE_P VDD VSS / RSC_IHPSG13_NOR2X2 +XA_DEC3<15> A_P0 A_ADDR_DEC<7> net23<0> VDD VSS / RSC_IHPSG13_NAND2X2 +XA_DEC3<14> A_P0 A_ADDR_DEC<6> net23<1> VDD VSS / RSC_IHPSG13_NAND2X2 +XA_DEC3<13> A_P0 A_ADDR_DEC<5> net23<2> VDD VSS / RSC_IHPSG13_NAND2X2 +XA_DEC3<12> A_P0 A_ADDR_DEC<4> net23<3> VDD VSS / RSC_IHPSG13_NAND2X2 +XA_DEC3<11> A_P0 A_ADDR_DEC<3> net23<4> VDD VSS / RSC_IHPSG13_NAND2X2 +XA_DEC3<10> A_P0 A_ADDR_DEC<2> net23<5> VDD VSS / RSC_IHPSG13_NAND2X2 +XA_DEC3<9> A_P0 A_ADDR_DEC<1> net23<6> VDD VSS / RSC_IHPSG13_NAND2X2 +XA_DEC3<8> A_P0 A_ADDR_DEC<0> net23<7> VDD VSS / RSC_IHPSG13_NAND2X2 +XA_DEC3<7> A_N0 A_ADDR_DEC<7> net23<8> VDD VSS / RSC_IHPSG13_NAND2X2 +XA_DEC3<6> A_N0 A_ADDR_DEC<6> net23<9> VDD VSS / RSC_IHPSG13_NAND2X2 +XA_DEC3<5> A_N0 A_ADDR_DEC<5> net23<10> VDD VSS / RSC_IHPSG13_NAND2X2 +XA_DEC3<4> A_N0 A_ADDR_DEC<4> net23<11> VDD VSS / RSC_IHPSG13_NAND2X2 +XA_DEC3<3> A_N0 A_ADDR_DEC<3> net23<12> VDD VSS / RSC_IHPSG13_NAND2X2 +XA_DEC3<2> A_N0 A_ADDR_DEC<2> net23<13> VDD VSS / RSC_IHPSG13_NAND2X2 +XA_DEC3<1> A_N0 A_ADDR_DEC<1> net23<14> VDD VSS / RSC_IHPSG13_NAND2X2 +XA_DEC3<0> A_N0 A_ADDR_DEC<0> net23<15> VDD VSS / RSC_IHPSG13_NAND2X2 +XB_DEC3<15> B_P0 B_ADDR_DEC<7> net044<0> VDD VSS / RSC_IHPSG13_NAND2X2 +XB_DEC3<14> B_P0 B_ADDR_DEC<6> net044<1> VDD VSS / RSC_IHPSG13_NAND2X2 +XB_DEC3<13> B_P0 B_ADDR_DEC<5> net044<2> VDD VSS / RSC_IHPSG13_NAND2X2 +XB_DEC3<12> B_P0 B_ADDR_DEC<4> net044<3> VDD VSS / RSC_IHPSG13_NAND2X2 +XB_DEC3<11> B_P0 B_ADDR_DEC<3> net044<4> VDD VSS / RSC_IHPSG13_NAND2X2 +XB_DEC3<10> B_P0 B_ADDR_DEC<2> net044<5> VDD VSS / RSC_IHPSG13_NAND2X2 +XB_DEC3<9> B_P0 B_ADDR_DEC<1> net044<6> VDD VSS / RSC_IHPSG13_NAND2X2 +XB_DEC3<8> B_P0 B_ADDR_DEC<0> net044<7> VDD VSS / RSC_IHPSG13_NAND2X2 +XB_DEC3<7> B_N0 B_ADDR_DEC<7> net044<8> VDD VSS / RSC_IHPSG13_NAND2X2 +XB_DEC3<6> B_N0 B_ADDR_DEC<6> net044<9> VDD VSS / RSC_IHPSG13_NAND2X2 +XB_DEC3<5> B_N0 B_ADDR_DEC<5> net044<10> VDD VSS / RSC_IHPSG13_NAND2X2 +XB_DEC3<4> B_N0 B_ADDR_DEC<4> net044<11> VDD VSS / RSC_IHPSG13_NAND2X2 +XB_DEC3<3> B_N0 B_ADDR_DEC<3> net044<12> VDD VSS / RSC_IHPSG13_NAND2X2 +XB_DEC3<2> B_N0 B_ADDR_DEC<2> net044<13> VDD VSS / RSC_IHPSG13_NAND2X2 +XB_DEC3<1> B_N0 B_ADDR_DEC<1> net044<14> VDD VSS / RSC_IHPSG13_NAND2X2 +XB_DEC3<0> B_N0 B_ADDR_DEC<0> net044<15> VDD VSS / RSC_IHPSG13_NAND2X2 +XB_BM_TIEH B_TIEH_O VDD VSS / RSC_IHPSG13_TIEH +XA_BM_TIEH A_TIEH_O VDD VSS / RSC_IHPSG13_TIEH +.ENDS + + +.SUBCKT RM_IHPSG13_256x8_c3_2P_ROWDEC5 ADDR_N_I<4> ADDR_N_I<3> ADDR_N_I<2> ADDR_N_I<1> ++ ADDR_N_I<0> CS_I ECLK_I WL_O<31> WL_O<30> WL_O<29> WL_O<28> WL_O<27> ++ WL_O<26> WL_O<25> WL_O<24> WL_O<23> WL_O<22> WL_O<21> WL_O<20> WL_O<19> ++ WL_O<18> WL_O<17> WL_O<16> WL_O<15> WL_O<14> WL_O<13> WL_O<12> WL_O<11> ++ WL_O<10> WL_O<9> WL_O<8> WL_O<7> WL_O<6> WL_O<5> WL_O<4> WL_O<3> WL_O<2> ++ WL_O<1> WL_O<0> VDD VSS +XDEC00 ADDR_N_I<5> ADDR_N_I<4> CS_I CS00<0> VDD VSS / ++ RM_IHPSG13_256x8_c3_2P_DEC00 +XSEL<1> ADDR_N_I<3> ADDR_N_I<2> ADDR_N_I<1> ADDR_N_I<0> CS00<1> ECLK_H<1> ++ ECLK_H<2> ECLK_B<1> ECLK_B<2> WL_O<31> WL_O<30> WL_O<29> WL_O<28> WL_O<27> ++ WL_O<26> WL_O<25> WL_O<24> WL_O<23> WL_O<22> WL_O<21> WL_O<20> WL_O<19> ++ WL_O<18> WL_O<17> WL_O<16> VDD VSS / RM_IHPSG13_256x8_c3_2P_DEC04 +XSEL<0> ADDR_N_I<3> ADDR_N_I<2> ADDR_N_I<1> ADDR_N_I<0> CS00<0> ECLK_I ++ ECLK_H<1> ECLK_B<0> ECLK_B<1> WL_O<15> WL_O<14> WL_O<13> WL_O<12> WL_O<11> ++ WL_O<10> WL_O<9> WL_O<8> WL_O<7> WL_O<6> WL_O<5> WL_O<4> WL_O<3> WL_O<2> ++ WL_O<1> WL_O<0> VDD VSS / RM_IHPSG13_256x8_c3_2P_DEC04 +XDEC01 ADDR_N_I<5> ADDR_N_I<4> CS_I CS00<1> VDD VSS / ++ RM_IHPSG13_256x8_c3_2P_DEC01 +XL2<18> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<17> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<16> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<15> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<14> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<13> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<12> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<11> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<10> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<9> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<8> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<7> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<6> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<5> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<4> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<3> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<2> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<1> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI0 ADDR_N_I<5> VDD VSS / RSC_IHPSG13_TIEL +.ENDS +.SUBCKT RM_IHPSG13_256x8_c3_2P_ROWREG5 ACLK_N_I ADDR_I<4> ADDR_I<3> ADDR_I<2> ADDR_I<1> ++ ADDR_I<0> ADDR_N_O<4> ADDR_N_O<3> ADDR_N_O<2> ADDR_N_O<1> ADDR_N_O<0> ++ BIST_ADDR_I<4> BIST_ADDR_I<3> BIST_ADDR_I<2> BIST_ADDR_I<1> BIST_ADDR_I<0> ++ BIST_EN_I VDD VSS +XINV<4> q_int<4> qn_int<4> VDD VSS / RSC_IHPSG13_CINVX2 +XINV<3> q_int<3> qn_int<3> VDD VSS / RSC_IHPSG13_CINVX2 +XINV<2> q_int<2> qn_int<2> VDD VSS / RSC_IHPSG13_CINVX2 +XINV<1> q_int<1> qn_int<1> VDD VSS / RSC_IHPSG13_CINVX2 +XINV<0> q_int<0> qn_int<0> VDD VSS / RSC_IHPSG13_CINVX2 +XDRV<4> qn_int<4> ADDR_N_O<4> VDD VSS / RSC_IHPSG13_CINVX8 +XDRV<3> qn_int<3> ADDR_N_O<3> VDD VSS / RSC_IHPSG13_CINVX8 +XDRV<2> qn_int<2> ADDR_N_O<2> VDD VSS / RSC_IHPSG13_CINVX8 +XDRV<1> qn_int<1> ADDR_N_O<1> VDD VSS / RSC_IHPSG13_CINVX8 +XDRV<0> qn_int<0> ADDR_N_O<0> VDD VSS / RSC_IHPSG13_CINVX8 +XDFF<4> BIST_EN_I BIST_ADDR_I<4> ACLK_N_I ADDR_I<4> q_int<4> net2<0> VDD ++ VSS / RSC_IHPSG13_DFNQMX2IX1 +XDFF<3> BIST_EN_I BIST_ADDR_I<3> ACLK_N_I ADDR_I<3> q_int<3> net2<1> VDD ++ VSS / RSC_IHPSG13_DFNQMX2IX1 +XDFF<2> BIST_EN_I BIST_ADDR_I<2> ACLK_N_I ADDR_I<2> q_int<2> net2<2> VDD ++ VSS / RSC_IHPSG13_DFNQMX2IX1 +XDFF<1> BIST_EN_I BIST_ADDR_I<1> ACLK_N_I ADDR_I<1> q_int<1> net2<3> VDD ++ VSS / RSC_IHPSG13_DFNQMX2IX1 +XDFF<0> BIST_EN_I BIST_ADDR_I<0> ACLK_N_I ADDR_I<0> q_int<0> net2<4> VDD ++ VSS / RSC_IHPSG13_DFNQMX2IX1 +XI11<16> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI11<15> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI11<14> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI11<13> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI11<12> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI11<11> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI11<10> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI11<9> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI11<8> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI11<7> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI11<6> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI11<5> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI11<4> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI11<3> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI11<2> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI11<1> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI12<3> VDD VSS / RSC_IHPSG13_FILLCAP4 +XI12<2> VDD VSS / RSC_IHPSG13_FILLCAP4 +XI12<1> VDD VSS / RSC_IHPSG13_FILLCAP4 +XI12<0> VDD VSS / RSC_IHPSG13_FILLCAP4 +.ENDS + + +.SUBCKT RM_IHPSG13_256x8_c3_2P_COLDEC3 ACLK_N ADDR<2> ADDR<1> ADDR<0> ADDR_COL<1> ++ ADDR_COL<0> ADDR_DEC<7> ADDR_DEC<6> ADDR_DEC<5> ADDR_DEC<4> ADDR_DEC<3> ++ ADDR_DEC<2> ADDR_DEC<1> ADDR_DEC<0> BIST_ADDR<2> BIST_ADDR<1> BIST_ADDR<0> ++ BIST_EN_I VDD VSS +XI1<7> PADR<0> PADR<1> PADR<2> addr_n<7> VDD VSS / RSC_IHPSG13_NAND3X2 +XI1<6> NADR<0> PADR<1> PADR<2> addr_n<6> VDD VSS / RSC_IHPSG13_NAND3X2 +XI1<5> PADR<0> NADR<1> PADR<2> addr_n<5> VDD VSS / RSC_IHPSG13_NAND3X2 +XI1<4> NADR<0> NADR<1> PADR<2> addr_n<4> VDD VSS / RSC_IHPSG13_NAND3X2 +XI1<3> PADR<0> PADR<1> NADR<2> addr_n<3> VDD VSS / RSC_IHPSG13_NAND3X2 +XI1<2> NADR<0> PADR<1> NADR<2> addr_n<2> VDD VSS / RSC_IHPSG13_NAND3X2 +XI1<1> PADR<0> NADR<1> NADR<2> addr_n<1> VDD VSS / RSC_IHPSG13_NAND3X2 +XI1<0> NADR<0> NADR<1> NADR<2> addr_n<0> VDD VSS / RSC_IHPSG13_NAND3X2 +XDFF<2> BIST_EN_I BIST_ADDR<2> ACLK_N ADDR<2> padr_int<2> net13<0> VDD ++ VSS / RSC_IHPSG13_DFNQMX2IX1 +XDFF<1> BIST_EN_I BIST_ADDR<1> ACLK_N ADDR<1> padr_int<1> net13<1> VDD ++ VSS / RSC_IHPSG13_DFNQMX2IX1 +XDFF<0> BIST_EN_I BIST_ADDR<0> ACLK_N ADDR<0> padr_int<0> net13<2> VDD ++ VSS / RSC_IHPSG13_DFNQMX2IX1 +XI15<1> ADDR_COL<1> VDD VSS / RSC_IHPSG13_TIEL +XI15<0> ADDR_COL<0> VDD VSS / RSC_IHPSG13_TIEL +XI13<2> NADR<2> PADR<2> VDD VSS / RSC_IHPSG13_INVX2 +XI13<1> NADR<1> PADR<1> VDD VSS / RSC_IHPSG13_INVX2 +XI13<0> NADR<0> PADR<0> VDD VSS / RSC_IHPSG13_INVX2 +XI3<2> padr_int<2> NADR<2> VDD VSS / RSC_IHPSG13_INVX2 +XI3<1> padr_int<1> NADR<1> VDD VSS / RSC_IHPSG13_INVX2 +XI3<0> padr_int<0> NADR<0> VDD VSS / RSC_IHPSG13_INVX2 +XI2<7> addr_n<7> ADDR_DEC<7> VDD VSS / RSC_IHPSG13_INVX2 +XI2<6> addr_n<6> ADDR_DEC<6> VDD VSS / RSC_IHPSG13_INVX2 +XI2<5> addr_n<5> ADDR_DEC<5> VDD VSS / RSC_IHPSG13_INVX2 +XI2<4> addr_n<4> ADDR_DEC<4> VDD VSS / RSC_IHPSG13_INVX2 +XI2<3> addr_n<3> ADDR_DEC<3> VDD VSS / RSC_IHPSG13_INVX2 +XI2<2> addr_n<2> ADDR_DEC<2> VDD VSS / RSC_IHPSG13_INVX2 +XI2<1> addr_n<1> ADDR_DEC<1> VDD VSS / RSC_IHPSG13_INVX2 +XI2<0> addr_n<0> ADDR_DEC<0> VDD VSS / RSC_IHPSG13_INVX2 +XI17<4> VDD VSS / RSC_IHPSG13_FILLCAP4 +XI17<3> VDD VSS / RSC_IHPSG13_FILLCAP4 +XI17<2> VDD VSS / RSC_IHPSG13_FILLCAP4 +XI17<1> VDD VSS / RSC_IHPSG13_FILLCAP4 +XI16<11> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI16<10> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI16<9> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI16<8> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI16<7> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI16<6> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI16<5> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI16<4> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI16<3> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI16<2> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI16<1> VDD VSS / RSC_IHPSG13_FILLCAP8 +.ENDS +.SUBCKT RSC_IHPSG13_DFPQD_MSAFFX2P CP DN DP QN QP VDD VSS +XI_AMP CP DN DP QN QP VDD VSS / RSC_IHPSG13_DFPQD_MSAFFX2 +.ENDS +.SUBCKT RM_IHPSG13_256x8_c3_2P_COLCTRL3 A_ADDR_DEC<7> A_ADDR_DEC<6> A_ADDR_DEC<5> ++ A_ADDR_DEC<4> A_ADDR_DEC<3> A_ADDR_DEC<2> A_ADDR_DEC<1> A_ADDR_DEC<0> ++ A_BIST_BM_I A_BIST_DW_I A_BIST_EN_I A_BLC<7> A_BLC<6> A_BLC<5> A_BLC<4> ++ A_BLC<3> A_BLC<2> A_BLC<1> A_BLC<0> A_BLT<7> A_BLT<6> A_BLT<5> A_BLT<4> ++ A_BLT<3> A_BLT<2> A_BLT<1> A_BLT<0> A_BM_I A_DCLK_B_L A_DCLK_B_R A_DCLK_L ++ A_DCLK_R A_DR_O A_DW_I A_RCLK_B_L A_RCLK_B_R A_RCLK_L A_RCLK_R A_TIEH_O ++ A_WCLK_B_L A_WCLK_B_R A_WCLK_L A_WCLK_R B_ADDR_DEC<7> B_ADDR_DEC<6> ++ B_ADDR_DEC<5> B_ADDR_DEC<4> B_ADDR_DEC<3> B_ADDR_DEC<2> B_ADDR_DEC<1> ++ B_ADDR_DEC<0> B_BIST_BM_I B_BIST_DW_I B_BIST_EN_I B_BLC<7> B_BLC<6> B_BLC<5> ++ B_BLC<4> B_BLC<3> B_BLC<2> B_BLC<1> B_BLC<0> B_BLT<7> B_BLT<6> B_BLT<5> ++ B_BLT<4> B_BLT<3> B_BLT<2> B_BLT<1> B_BLT<0> B_BM_I B_DCLK_B_L B_DCLK_B_R ++ B_DCLK_L B_DCLK_R B_DR_O B_DW_I B_RCLK_B_L B_RCLK_B_R B_RCLK_L B_RCLK_R ++ B_TIEH_O B_WCLK_B_L B_WCLK_B_R B_WCLK_L B_WCLK_R VDD VSS +XB_DREG B_BIST_EN_I B_BIST_DW_I B_DCLK_B_L B_DW_I B_DI_R net044 VDD ++ VSS / RSC_IHPSG13_DFNQMX2IX1 +XB_BREG B_BIST_EN_I B_BIST_BM_I B_DCLK_B_L B_BM_I B_BM_R net043 VDD ++ VSS / RSC_IHPSG13_DFNQMX2IX1 +XA_DREG A_BIST_EN_I A_BIST_DW_I A_DCLK_B_L A_DW_I A_DI_R net22 VDD VSS ++ / RSC_IHPSG13_DFNQMX2IX1 +XA_BREG A_BIST_EN_I A_BIST_BM_I A_DCLK_B_L A_BM_I A_BM_R net23 VDD VSS ++ / RSC_IHPSG13_DFNQMX2IX1 +XI_FILL8<11> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI_FILL8<10> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI_FILL8<9> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI_FILL8<8> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI_FILL8<7> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI_FILL8<6> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI_FILL8<5> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI_FILL8<4> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI_FILL8<3> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI_FILL8<2> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI_FILL8<1> VDD VSS / RSC_IHPSG13_FILLCAP8 +XB_I51 net037 B_DR_O VDD VSS / RSC_IHPSG13_INVX4 +XA_I51 net19 A_DR_O VDD VSS / RSC_IHPSG13_INVX4 +XB_I44 B_BM_N B_WCLK_B_L B_DO_WRITE_P VDD VSS / RSC_IHPSG13_NOR2X2 +XA_I44 A_BM_N A_WCLK_B_L A_DO_WRITE_P VDD VSS / RSC_IHPSG13_NOR2X2 +XB_BM_TIEH B_TIEH_O VDD VSS / RSC_IHPSG13_TIEH +XA_BM_TIEH A_TIEH_O VDD VSS / RSC_IHPSG13_TIEH +XB_ISENSE B_SAE B_BLC_SEL B_BLT_SEL net037 net038 VDD VSS / ++ RSC_IHPSG13_DFPQD_MSAFFX2P +XA_ISENSE A_SAE A_BLC_SEL A_BLT_SEL net19 net20 VDD VSS / ++ RSC_IHPSG13_DFPQD_MSAFFX2P +XB_I49 B_DI_R B_DI_N VDD VSS / RSC_IHPSG13_INVX2 +XB_I83 B_BM_R B_BM_N VDD VSS / RSC_IHPSG13_INVX2 +XA_I49 A_DI_R A_DI_N VDD VSS / RSC_IHPSG13_INVX2 +XA_I83 A_BM_R A_BM_N VDD VSS / RSC_IHPSG13_INVX2 +XB_I69 B_DCLK_L B_DCLK_B_L VDD VSS / RSC_IHPSG13_CINVX2 +XB_I50 B_WCLK_L B_WCLK_B_L VDD VSS / RSC_IHPSG13_CINVX2 +XB_EBUF B_RCLK_L B_RCLK_B_L VDD VSS / RSC_IHPSG13_CINVX2 +XA_I69 A_DCLK_L A_DCLK_B_L VDD VSS / RSC_IHPSG13_CINVX2 +XA_I50 A_WCLK_L A_WCLK_B_L VDD VSS / RSC_IHPSG13_CINVX2 +XA_EBUF A_RCLK_L A_RCLK_B_L VDD VSS / RSC_IHPSG13_CINVX2 +XAB_BLMUX<1> A_BLC<7> A_BLC<6> A_BLC<5> A_BLC<4> A_BLC_SEL A_BLT<7> A_BLT<6> ++ A_BLT<5> A_BLT<4> A_BLT_SEL A_PRE_N A_ADDR_DEC<7> A_ADDR_DEC<6> ++ A_ADDR_DEC<5> A_ADDR_DEC<4> A_WR_ONE A_WR_ZERO B_BLC<7> B_BLC<6> B_BLC<5> ++ B_BLC<4> B_BLC_SEL B_BLT<7> B_BLT<6> B_BLT<5> B_BLT<4> B_BLT_SEL B_PRE_N ++ B_ADDR_DEC<7> B_ADDR_DEC<6> B_ADDR_DEC<5> B_ADDR_DEC<4> B_WR_ONE B_WR_ZERO ++ VDD VSS / RM_IHPSG13_256x8_c3_2P_BLDRV +XAB_BLMUX<0> A_BLC<3> A_BLC<2> A_BLC<1> A_BLC<0> A_BLC_SEL A_BLT<3> A_BLT<2> ++ A_BLT<1> A_BLT<0> A_BLT_SEL A_PRE_N A_ADDR_DEC<3> A_ADDR_DEC<2> ++ A_ADDR_DEC<1> A_ADDR_DEC<0> A_WR_ONE A_WR_ZERO B_BLC<3> B_BLC<2> B_BLC<1> ++ B_BLC<0> B_BLC_SEL B_BLT<3> B_BLT<2> B_BLT<1> B_BLT<0> B_BLT_SEL B_PRE_N ++ B_ADDR_DEC<3> B_ADDR_DEC<2> B_ADDR_DEC<1> B_ADDR_DEC<0> B_WR_ONE B_WR_ZERO ++ VDD VSS / RM_IHPSG13_256x8_c3_2P_BLDRV +XB_I78 B_RCLK_B_L B_SAE VDD VSS / RSC_IHPSG13_CBUFX2 +XA_I78 A_RCLK_B_L A_SAE VDD VSS / RSC_IHPSG13_CBUFX2 +XB_I88 B_DCLK_L B_DCLK_R / RSC_IHPSG13_MET3RES +XB_I87 B_WCLK_L B_WCLK_R / RSC_IHPSG13_MET3RES +XB_R2 B_RCLK_L B_RCLK_R / RSC_IHPSG13_MET3RES +XB_I91 B_RCLK_B_L B_RCLK_B_R / RSC_IHPSG13_MET3RES +XB_I90 B_WCLK_B_L B_WCLK_B_R / RSC_IHPSG13_MET3RES +XB_I89 B_DCLK_B_L B_DCLK_B_R / RSC_IHPSG13_MET3RES +XA_I88 A_DCLK_L A_DCLK_R / RSC_IHPSG13_MET3RES +XA_I87 A_WCLK_L A_WCLK_R / RSC_IHPSG13_MET3RES +XA_R2 A_RCLK_L A_RCLK_R / RSC_IHPSG13_MET3RES +XA_I91 A_RCLK_B_L A_RCLK_B_R / RSC_IHPSG13_MET3RES +XA_I90 A_WCLK_B_L A_WCLK_B_R / RSC_IHPSG13_MET3RES +XA_I89 A_DCLK_B_L A_DCLK_B_R / RSC_IHPSG13_MET3RES +XB_I80 B_WCLK_B_L B_RCLK_B_L net041 VDD VSS / RSC_IHPSG13_AND2X2 +XB_I76 B_DO_WRITE_P B_DI_N B_WR_ZERO VDD VSS / RSC_IHPSG13_AND2X2 +XB_I75 B_DO_WRITE_P B_DI_R B_WR_ONE VDD VSS / RSC_IHPSG13_AND2X2 +XA_I80 A_WCLK_B_L A_RCLK_B_L net21 VDD VSS / RSC_IHPSG13_AND2X2 +XA_I76 A_DI_N A_DO_WRITE_P A_WR_ZERO VDD VSS / RSC_IHPSG13_AND2X2 +XA_I75 A_DI_R A_DO_WRITE_P A_WR_ONE VDD VSS / RSC_IHPSG13_AND2X2 +XB_I81 net041 B_PRE_N VDD VSS / RSC_IHPSG13_CINVX4_WN +XA_I81 net21 A_PRE_N VDD VSS / RSC_IHPSG13_CINVX4_WN +XI_FILL4<10> VDD VSS / RSC_IHPSG13_FILLCAP4 +XI_FILL4<9> VDD VSS / RSC_IHPSG13_FILLCAP4 +XI_FILL4<8> VDD VSS / RSC_IHPSG13_FILLCAP4 +XI_FILL4<7> VDD VSS / RSC_IHPSG13_FILLCAP4 +XI_FILL4<6> VDD VSS / RSC_IHPSG13_FILLCAP4 +XI_FILL4<5> VDD VSS / RSC_IHPSG13_FILLCAP4 +XI_FILL4<4> VDD VSS / RSC_IHPSG13_FILLCAP4 +XI_FILL4<3> VDD VSS / RSC_IHPSG13_FILLCAP4 +XI_FILL4<2> VDD VSS / RSC_IHPSG13_FILLCAP4 +XI_FILL4<1> VDD VSS / RSC_IHPSG13_FILLCAP4 +.ENDS + +.SUBCKT RM_IHPSG13_256x8_c3_2P_ROWDEC6 ADDR_N_I<5> ADDR_N_I<4> ADDR_N_I<3> ADDR_N_I<2> ++ ADDR_N_I<1> ADDR_N_I<0> CS_I ECLK_I WL_O<63> WL_O<62> WL_O<61> WL_O<60> ++ WL_O<59> WL_O<58> WL_O<57> WL_O<56> WL_O<55> WL_O<54> WL_O<53> WL_O<52> ++ WL_O<51> WL_O<50> WL_O<49> WL_O<48> WL_O<47> WL_O<46> WL_O<45> WL_O<44> ++ WL_O<43> WL_O<42> WL_O<41> WL_O<40> WL_O<39> WL_O<38> WL_O<37> WL_O<36> ++ WL_O<35> WL_O<34> WL_O<33> WL_O<32> WL_O<31> WL_O<30> WL_O<29> WL_O<28> ++ WL_O<27> WL_O<26> WL_O<25> WL_O<24> WL_O<23> WL_O<22> WL_O<21> WL_O<20> ++ WL_O<19> WL_O<18> WL_O<17> WL_O<16> WL_O<15> WL_O<14> WL_O<13> WL_O<12> ++ WL_O<11> WL_O<10> WL_O<9> WL_O<8> WL_O<7> WL_O<6> WL_O<5> WL_O<4> WL_O<3> ++ WL_O<2> WL_O<1> WL_O<0> VDD VSS +XDEC10 ADDR_N_I<5> ADDR_N_I<4> CS_I CS00<2> VDD VSS / ++ RM_IHPSG13_256x8_c3_2P_DEC02 +XDEC00 ADDR_N_I<5> ADDR_N_I<4> CS_I CS00<0> VDD VSS / ++ RM_IHPSG13_256x8_c3_2P_DEC00 +XSEL<3> ADDR_N_I<3> ADDR_N_I<2> ADDR_N_I<1> ADDR_N_I<0> CS00<3> ECLK_H<3> ++ ECLK_H<4> ECLK_B<3> ECLK_B<4> WL_O<63> WL_O<62> WL_O<61> WL_O<60> WL_O<59> ++ WL_O<58> WL_O<57> WL_O<56> WL_O<55> WL_O<54> WL_O<53> WL_O<52> WL_O<51> ++ WL_O<50> WL_O<49> WL_O<48> VDD VSS / RM_IHPSG13_256x8_c3_2P_DEC04 +XSEL<2> ADDR_N_I<3> ADDR_N_I<2> ADDR_N_I<1> ADDR_N_I<0> CS00<2> ECLK_H<2> ++ ECLK_H<3> ECLK_B<2> ECLK_B<3> WL_O<47> WL_O<46> WL_O<45> WL_O<44> WL_O<43> ++ WL_O<42> WL_O<41> WL_O<40> WL_O<39> WL_O<38> WL_O<37> WL_O<36> WL_O<35> ++ WL_O<34> WL_O<33> WL_O<32> VDD VSS / RM_IHPSG13_256x8_c3_2P_DEC04 +XSEL<1> ADDR_N_I<3> ADDR_N_I<2> ADDR_N_I<1> ADDR_N_I<0> CS00<1> ECLK_H<1> ++ ECLK_H<2> ECLK_B<1> ECLK_B<2> WL_O<31> WL_O<30> WL_O<29> WL_O<28> WL_O<27> ++ WL_O<26> WL_O<25> WL_O<24> WL_O<23> WL_O<22> WL_O<21> WL_O<20> WL_O<19> ++ WL_O<18> WL_O<17> WL_O<16> VDD VSS / RM_IHPSG13_256x8_c3_2P_DEC04 +XSEL<0> ADDR_N_I<3> ADDR_N_I<2> ADDR_N_I<1> ADDR_N_I<0> CS00<0> ECLK_I ++ ECLK_H<1> ECLK_B<0> ECLK_B<1> WL_O<15> WL_O<14> WL_O<13> WL_O<12> WL_O<11> ++ WL_O<10> WL_O<9> WL_O<8> WL_O<7> WL_O<6> WL_O<5> WL_O<4> WL_O<3> WL_O<2> ++ WL_O<1> WL_O<0> VDD VSS / RM_IHPSG13_256x8_c3_2P_DEC04 +XDEC11 ADDR_N_I<5> ADDR_N_I<4> CS_I CS00<3> VDD VSS / ++ RM_IHPSG13_256x8_c3_2P_DEC03 +XL2<36> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<35> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<34> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<33> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<32> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<31> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<30> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<29> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<28> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<27> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<26> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<25> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<24> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<23> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<22> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<21> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<20> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<19> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<18> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<17> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<16> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<15> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<14> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<13> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<12> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<11> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<10> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<9> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<8> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<7> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<6> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<5> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<4> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<3> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<2> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<1> VDD VSS / RSC_IHPSG13_FILLCAP8 +XDEC01 ADDR_N_I<5> ADDR_N_I<4> CS_I CS00<1> VDD VSS / ++ RM_IHPSG13_256x8_c3_2P_DEC01 +.ENDS +.SUBCKT RM_IHPSG13_256x8_c3_2P_ROWREG6 ACLK_N_I ADDR_I<5> ADDR_I<4> ADDR_I<3> ADDR_I<2> ++ ADDR_I<1> ADDR_I<0> ADDR_N_O<5> ADDR_N_O<4> ADDR_N_O<3> ADDR_N_O<2> ++ ADDR_N_O<1> ADDR_N_O<0> BIST_ADDR_I<5> BIST_ADDR_I<4> BIST_ADDR_I<3> ++ BIST_ADDR_I<2> BIST_ADDR_I<1> BIST_ADDR_I<0> BIST_EN_I VDD VSS +XINV<5> q_int<5> qn_int<5> VDD VSS / RSC_IHPSG13_CINVX2 +XINV<4> q_int<4> qn_int<4> VDD VSS / RSC_IHPSG13_CINVX2 +XINV<3> q_int<3> qn_int<3> VDD VSS / RSC_IHPSG13_CINVX2 +XINV<2> q_int<2> qn_int<2> VDD VSS / RSC_IHPSG13_CINVX2 +XINV<1> q_int<1> qn_int<1> VDD VSS / RSC_IHPSG13_CINVX2 +XINV<0> q_int<0> qn_int<0> VDD VSS / RSC_IHPSG13_CINVX2 +XDRV<5> qn_int<5> ADDR_N_O<5> VDD VSS / RSC_IHPSG13_CINVX8 +XDRV<4> qn_int<4> ADDR_N_O<4> VDD VSS / RSC_IHPSG13_CINVX8 +XDRV<3> qn_int<3> ADDR_N_O<3> VDD VSS / RSC_IHPSG13_CINVX8 +XDRV<2> qn_int<2> ADDR_N_O<2> VDD VSS / RSC_IHPSG13_CINVX8 +XDRV<1> qn_int<1> ADDR_N_O<1> VDD VSS / RSC_IHPSG13_CINVX8 +XDRV<0> qn_int<0> ADDR_N_O<0> VDD VSS / RSC_IHPSG13_CINVX8 +XDFF<5> BIST_EN_I BIST_ADDR_I<5> ACLK_N_I ADDR_I<5> q_int<5> net2<0> VDD ++ VSS / RSC_IHPSG13_DFNQMX2IX1 +XDFF<4> BIST_EN_I BIST_ADDR_I<4> ACLK_N_I ADDR_I<4> q_int<4> net2<1> VDD ++ VSS / RSC_IHPSG13_DFNQMX2IX1 +XDFF<3> BIST_EN_I BIST_ADDR_I<3> ACLK_N_I ADDR_I<3> q_int<3> net2<2> VDD ++ VSS / RSC_IHPSG13_DFNQMX2IX1 +XDFF<2> BIST_EN_I BIST_ADDR_I<2> ACLK_N_I ADDR_I<2> q_int<2> net2<3> VDD ++ VSS / RSC_IHPSG13_DFNQMX2IX1 +XDFF<1> BIST_EN_I BIST_ADDR_I<1> ACLK_N_I ADDR_I<1> q_int<1> net2<4> VDD ++ VSS / RSC_IHPSG13_DFNQMX2IX1 +XDFF<0> BIST_EN_I BIST_ADDR_I<0> ACLK_N_I ADDR_I<0> q_int<0> net2<5> VDD ++ VSS / RSC_IHPSG13_DFNQMX2IX1 +XI11<12> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI11<11> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI11<10> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI11<9> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI11<8> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI11<7> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI11<6> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI11<5> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI11<4> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI11<3> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI11<2> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI11<1> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI12<2> VDD VSS / RSC_IHPSG13_FILLCAP4 +XI12<1> VDD VSS / RSC_IHPSG13_FILLCAP4 +XI12<0> VDD VSS / RSC_IHPSG13_FILLCAP4 +.ENDS + +.SUBCKT RM_IHPSG13_256x8_c3_2P_COLDRV13X16 ADDR_COL_I<1> ADDR_COL_I<0> ADDR_COL_O<1> ++ ADDR_COL_O<0> ADDR_DEC_I<7> ADDR_DEC_I<6> ADDR_DEC_I<5> ADDR_DEC_I<4> ++ ADDR_DEC_I<3> ADDR_DEC_I<2> ADDR_DEC_I<1> ADDR_DEC_I<0> ADDR_DEC_O<7> ++ ADDR_DEC_O<6> ADDR_DEC_O<5> ADDR_DEC_O<4> ADDR_DEC_O<3> ADDR_DEC_O<2> ++ ADDR_DEC_O<1> ADDR_DEC_O<0> DCLK_I DCLK_O RCLK_I RCLK_O WCLK_I WCLK_O ++ VDD VSS +XI0<7> VDD VSS / RSC_IHPSG13_FILLCAP4 +XI0<6> VDD VSS / RSC_IHPSG13_FILLCAP4 +XI0<5> VDD VSS / RSC_IHPSG13_FILLCAP4 +XI0<4> VDD VSS / RSC_IHPSG13_FILLCAP4 +XI0<3> VDD VSS / RSC_IHPSG13_FILLCAP4 +XI0<2> VDD VSS / RSC_IHPSG13_FILLCAP4 +XI0<1> VDD VSS / RSC_IHPSG13_FILLCAP4 +XWCLK_DRV WCLK_I WCLK_O VDD VSS / RSC_IHPSG13_CBUFX16 +XRCLK_DRV RCLK_I RCLK_O VDD VSS / RSC_IHPSG13_CBUFX16 +XDCLK_DRV DCLK_I DCLK_O VDD VSS / RSC_IHPSG13_CBUFX16 +XADDR_COL_DRV<1> ADDR_COL_I<1> ADDR_COL_O<1> VDD VSS / ++ RSC_IHPSG13_CBUFX16 +XADDR_COL_DRV<0> ADDR_COL_I<0> ADDR_COL_O<0> VDD VSS / ++ RSC_IHPSG13_CBUFX16 +XADDR_DEC_DRV<7> ADDR_DEC_I<7> ADDR_DEC_O<7> VDD VSS / ++ RSC_IHPSG13_CBUFX16 +XADDR_DEC_DRV<6> ADDR_DEC_I<6> ADDR_DEC_O<6> VDD VSS / ++ RSC_IHPSG13_CBUFX16 +XADDR_DEC_DRV<5> ADDR_DEC_I<5> ADDR_DEC_O<5> VDD VSS / ++ RSC_IHPSG13_CBUFX16 +XADDR_DEC_DRV<4> ADDR_DEC_I<4> ADDR_DEC_O<4> VDD VSS / ++ RSC_IHPSG13_CBUFX16 +XADDR_DEC_DRV<3> ADDR_DEC_I<3> ADDR_DEC_O<3> VDD VSS / ++ RSC_IHPSG13_CBUFX16 +XADDR_DEC_DRV<2> ADDR_DEC_I<2> ADDR_DEC_O<2> VDD VSS / ++ RSC_IHPSG13_CBUFX16 +XADDR_DEC_DRV<1> ADDR_DEC_I<1> ADDR_DEC_O<1> VDD VSS / ++ RSC_IHPSG13_CBUFX16 +XADDR_DEC_DRV<0> ADDR_DEC_I<0> ADDR_DEC_O<0> VDD VSS / ++ RSC_IHPSG13_CBUFX16 +XI1<5> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI1<4> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI1<3> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI1<2> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI1<1> VDD VSS / RSC_IHPSG13_FILLCAP8 +.ENDS +.SUBCKT RM_IHPSG13_256x8_c3_2P_WLDRV16X16 A<15> A<14> A<13> A<12> A<11> A<10> A<9> A<8> ++ A<7> A<6> A<5> A<4> A<3> A<2> A<1> A<0> Z<15> Z<14> Z<13> Z<12> Z<11> Z<10> ++ Z<9> Z<8> Z<7> Z<6> Z<5> Z<4> Z<3> Z<2> Z<1> Z<0> VDD VSS +XBUF<15> A<15> Z<15> VDD VSS / RSC_IHPSG13_WLDRVX16 +XBUF<14> A<14> Z<14> VDD VSS / RSC_IHPSG13_WLDRVX16 +XBUF<13> A<13> Z<13> VDD VSS / RSC_IHPSG13_WLDRVX16 +XBUF<12> A<12> Z<12> VDD VSS / RSC_IHPSG13_WLDRVX16 +XBUF<11> A<11> Z<11> VDD VSS / RSC_IHPSG13_WLDRVX16 +XBUF<10> A<10> Z<10> VDD VSS / RSC_IHPSG13_WLDRVX16 +XBUF<9> A<9> Z<9> VDD VSS / RSC_IHPSG13_WLDRVX16 +XBUF<8> A<8> Z<8> VDD VSS / RSC_IHPSG13_WLDRVX16 +XBUF<7> A<7> Z<7> VDD VSS / RSC_IHPSG13_WLDRVX16 +XBUF<6> A<6> Z<6> VDD VSS / RSC_IHPSG13_WLDRVX16 +XBUF<5> A<5> Z<5> VDD VSS / RSC_IHPSG13_WLDRVX16 +XBUF<4> A<4> Z<4> VDD VSS / RSC_IHPSG13_WLDRVX16 +XBUF<3> A<3> Z<3> VDD VSS / RSC_IHPSG13_WLDRVX16 +XBUF<2> A<2> Z<2> VDD VSS / RSC_IHPSG13_WLDRVX16 +XBUF<1> A<1> Z<1> VDD VSS / RSC_IHPSG13_WLDRVX16 +XBUF<0> A<0> Z<0> VDD VSS / RSC_IHPSG13_WLDRVX16 +.ENDS + + +.SUBCKT RM_IHPSG13_256x8_c3_1P_DEC01 ADDR<1> ADDR<0> CS CS_OUT VDD VSS +XDECINV net1 CS_OUT VDD VSS / RSC_IHPSG13_INVX4 +XDEC NADDR<1> ADDR<0> CS net1 VDD VSS / RSC_IHPSG13_NAND3X2 +XI2 VDD VSS / RSC_IHPSG13_FILLCAP4 +XADDRINV ADDR<1> NADDR<1> VDD VSS / RSC_IHPSG13_INVX2 +.ENDS +.SUBCKT RM_IHPSG13_256x8_c3_1P_DEC00 ADDR<1> ADDR<0> CS CS_OUT VDD VSS +XDECINV net1 CS_OUT VDD VSS / RSC_IHPSG13_INVX4 +XDEC NADDR<1> NADDR<0> CS net1 VDD VSS / RSC_IHPSG13_NAND3X2 +XADDRINV<1> ADDR<1> NADDR<1> VDD VSS / RSC_IHPSG13_INVX2 +XADDRINV<0> ADDR<0> NADDR<0> VDD VSS / RSC_IHPSG13_INVX2 +XI1 VDD VSS / RSC_IHPSG13_FILLCAP4 +.ENDS +.SUBCKT RM_IHPSG13_256x8_c3_1P_ROWDEC5 ADDR_N_I<4> ADDR_N_I<3> ADDR_N_I<2> ADDR_N_I<1> ++ ADDR_N_I<0> CS_I ECLK_I WL_O<31> WL_O<30> WL_O<29> WL_O<28> WL_O<27> ++ WL_O<26> WL_O<25> WL_O<24> WL_O<23> WL_O<22> WL_O<21> WL_O<20> WL_O<19> ++ WL_O<18> WL_O<17> WL_O<16> WL_O<15> WL_O<14> WL_O<13> WL_O<12> WL_O<11> ++ WL_O<10> WL_O<9> WL_O<8> WL_O<7> WL_O<6> WL_O<5> WL_O<4> WL_O<3> WL_O<2> ++ WL_O<1> WL_O<0> VDD VSS +XL2<12> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<11> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<10> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<9> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<8> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<7> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<6> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<5> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<4> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<3> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<2> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<1> VDD VSS / RSC_IHPSG13_FILLCAP8 +XDEC01 ADDR_N_I<5> ADDR_N_I<4> CS_I CS00<1> VDD VSS / ++ RM_IHPSG13_256x8_c3_1P_DEC01 +XDEC00 ADDR_N_I<5> ADDR_N_I<4> CS_I CS00<0> VDD VSS / ++ RM_IHPSG13_256x8_c3_1P_DEC00 +XSEL<1> ADDR_N_I<3> ADDR_N_I<2> ADDR_N_I<1> ADDR_N_I<0> CS00<1> ECLK_H<1> ++ ECLK_H<2> ECLK_B<1> ECLK_B<2> WL_O<31> WL_O<30> WL_O<29> WL_O<28> WL_O<27> ++ WL_O<26> WL_O<25> WL_O<24> WL_O<23> WL_O<22> WL_O<21> WL_O<20> WL_O<19> ++ WL_O<18> WL_O<17> WL_O<16> VDD VSS / RM_IHPSG13_256x8_c3_1P_DEC04 +XSEL<0> ADDR_N_I<3> ADDR_N_I<2> ADDR_N_I<1> ADDR_N_I<0> CS00<0> ECLK_I ++ ECLK_H<1> ECLK_B<0> ECLK_B<1> WL_O<15> WL_O<14> WL_O<13> WL_O<12> WL_O<11> ++ WL_O<10> WL_O<9> WL_O<8> WL_O<7> WL_O<6> WL_O<5> WL_O<4> WL_O<3> WL_O<2> ++ WL_O<1> WL_O<0> VDD VSS / RM_IHPSG13_256x8_c3_1P_DEC04 +XI0 ADDR_N_I<5> VDD VSS / RSC_IHPSG13_TIEL +.ENDS +.SUBCKT RM_IHPSG13_256x8_c3_1P_ROWREG5 ACLK_N_I ADDR_I<4> ADDR_I<3> ADDR_I<2> ADDR_I<1> ++ ADDR_I<0> ADDR_N_O<4> ADDR_N_O<3> ADDR_N_O<2> ADDR_N_O<1> ADDR_N_O<0> ++ BIST_ADDR_I<4> BIST_ADDR_I<3> BIST_ADDR_I<2> BIST_ADDR_I<1> BIST_ADDR_I<0> ++ BIST_EN_I VDD VSS +XINV<4> q_int<4> qn_int<4> VDD VSS / RSC_IHPSG13_CINVX2 +XINV<3> q_int<3> qn_int<3> VDD VSS / RSC_IHPSG13_CINVX2 +XINV<2> q_int<2> qn_int<2> VDD VSS / RSC_IHPSG13_CINVX2 +XINV<1> q_int<1> qn_int<1> VDD VSS / RSC_IHPSG13_CINVX2 +XINV<0> q_int<0> qn_int<0> VDD VSS / RSC_IHPSG13_CINVX2 +XDRV<4> qn_int<4> ADDR_N_O<4> VDD VSS / RSC_IHPSG13_CINVX8 +XDRV<3> qn_int<3> ADDR_N_O<3> VDD VSS / RSC_IHPSG13_CINVX8 +XDRV<2> qn_int<2> ADDR_N_O<2> VDD VSS / RSC_IHPSG13_CINVX8 +XDRV<1> qn_int<1> ADDR_N_O<1> VDD VSS / RSC_IHPSG13_CINVX8 +XDRV<0> qn_int<0> ADDR_N_O<0> VDD VSS / RSC_IHPSG13_CINVX8 +XDFF<4> BIST_EN_I BIST_ADDR_I<4> ACLK_N_I ADDR_I<4> q_int<4> net2<0> VDD ++ VSS / RSC_IHPSG13_DFNQMX2IX1 +XDFF<3> BIST_EN_I BIST_ADDR_I<3> ACLK_N_I ADDR_I<3> q_int<3> net2<1> VDD ++ VSS / RSC_IHPSG13_DFNQMX2IX1 +XDFF<2> BIST_EN_I BIST_ADDR_I<2> ACLK_N_I ADDR_I<2> q_int<2> net2<2> VDD ++ VSS / RSC_IHPSG13_DFNQMX2IX1 +XDFF<1> BIST_EN_I BIST_ADDR_I<1> ACLK_N_I ADDR_I<1> q_int<1> net2<3> VDD ++ VSS / RSC_IHPSG13_DFNQMX2IX1 +XDFF<0> BIST_EN_I BIST_ADDR_I<0> ACLK_N_I ADDR_I<0> q_int<0> net2<4> VDD ++ VSS / RSC_IHPSG13_DFNQMX2IX1 +XI11<16> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI11<15> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI11<14> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI11<13> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI11<12> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI11<11> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI11<10> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI11<9> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI11<8> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI11<7> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI11<6> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI11<5> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI11<4> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI11<3> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI11<2> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI11<1> VDD VSS / RSC_IHPSG13_FILLCAP8 +.ENDS + + +.SUBCKT RM_IHPSG13_256x8_c3_1P_COLDEC5 ACLK_N ADDR<4> ADDR<3> ADDR<2> ADDR<1> ADDR<0> ++ ADDR_COL<1> ADDR_COL<0> ADDR_DEC<7> ADDR_DEC<6> ADDR_DEC<5> ADDR_DEC<4> ++ ADDR_DEC<3> ADDR_DEC<2> ADDR_DEC<1> ADDR_DEC<0> BIST_ADDR<4> BIST_ADDR<3> ++ BIST_ADDR<2> BIST_ADDR<1> BIST_ADDR<0> BIST_EN_I VDD VSS +XI17<2> VDD VSS / RSC_IHPSG13_FILLCAP4 +XI17<1> VDD VSS / RSC_IHPSG13_FILLCAP4 +XI13<1> addr_int<1> ADDR_COL<1> VDD VSS / RSC_IHPSG13_CBUFX2 +XI13<0> addr_int<0> ADDR_COL<0> VDD VSS / RSC_IHPSG13_CBUFX2 +XDFF<4> BIST_EN_I BIST_ADDR<4> ACLK_N ADDR<4> addr_int<1> net7<0> VDD ++ VSS / RSC_IHPSG13_DFNQMX2IX1 +XDFF<3> BIST_EN_I BIST_ADDR<3> ACLK_N ADDR<3> addr_int<0> net7<1> VDD ++ VSS / RSC_IHPSG13_DFNQMX2IX1 +XDFF<2> BIST_EN_I BIST_ADDR<2> ACLK_N ADDR<2> padr_int<2> net7<2> VDD ++ VSS / RSC_IHPSG13_DFNQMX2IX1 +XDFF<1> BIST_EN_I BIST_ADDR<1> ACLK_N ADDR<1> padr_int<1> net7<3> VDD ++ VSS / RSC_IHPSG13_DFNQMX2IX1 +XDFF<0> BIST_EN_I BIST_ADDR<0> ACLK_N ADDR<0> padr_int<0> net7<4> VDD ++ VSS / RSC_IHPSG13_DFNQMX2IX1 +XI1<7> PADR<0> PADR<1> PADR<2> addr_n<7> VDD VSS / RSC_IHPSG13_NAND3X2 +XI1<6> NADR<0> PADR<1> PADR<2> addr_n<6> VDD VSS / RSC_IHPSG13_NAND3X2 +XI1<5> PADR<0> NADR<1> PADR<2> addr_n<5> VDD VSS / RSC_IHPSG13_NAND3X2 +XI1<4> NADR<0> NADR<1> PADR<2> addr_n<4> VDD VSS / RSC_IHPSG13_NAND3X2 +XI1<3> PADR<0> PADR<1> NADR<2> addr_n<3> VDD VSS / RSC_IHPSG13_NAND3X2 +XI1<2> NADR<0> PADR<1> NADR<2> addr_n<2> VDD VSS / RSC_IHPSG13_NAND3X2 +XI1<1> PADR<0> NADR<1> NADR<2> addr_n<1> VDD VSS / RSC_IHPSG13_NAND3X2 +XI1<0> NADR<0> NADR<1> NADR<2> addr_n<0> VDD VSS / RSC_IHPSG13_NAND3X2 +XI15<2> NADR<2> PADR<2> VDD VSS / RSC_IHPSG13_INVX2 +XI15<1> NADR<1> PADR<1> VDD VSS / RSC_IHPSG13_INVX2 +XI15<0> NADR<0> PADR<0> VDD VSS / RSC_IHPSG13_INVX2 +XI3<2> padr_int<2> NADR<2> VDD VSS / RSC_IHPSG13_INVX2 +XI3<1> padr_int<1> NADR<1> VDD VSS / RSC_IHPSG13_INVX2 +XI3<0> padr_int<0> NADR<0> VDD VSS / RSC_IHPSG13_INVX2 +XI2<7> addr_n<7> ADDR_DEC<7> VDD VSS / RSC_IHPSG13_INVX2 +XI2<6> addr_n<6> ADDR_DEC<6> VDD VSS / RSC_IHPSG13_INVX2 +XI2<5> addr_n<5> ADDR_DEC<5> VDD VSS / RSC_IHPSG13_INVX2 +XI2<4> addr_n<4> ADDR_DEC<4> VDD VSS / RSC_IHPSG13_INVX2 +XI2<3> addr_n<3> ADDR_DEC<3> VDD VSS / RSC_IHPSG13_INVX2 +XI2<2> addr_n<2> ADDR_DEC<2> VDD VSS / RSC_IHPSG13_INVX2 +XI2<1> addr_n<1> ADDR_DEC<1> VDD VSS / RSC_IHPSG13_INVX2 +XI2<0> addr_n<0> ADDR_DEC<0> VDD VSS / RSC_IHPSG13_INVX2 +.ENDS +.SUBCKT RM_IHPSG13_256x8_c3_1P_COLCTRL5 A_ADDR_COL<1> A_ADDR_COL<0> A_ADDR_DEC<7> ++ A_ADDR_DEC<6> A_ADDR_DEC<5> A_ADDR_DEC<4> A_ADDR_DEC<3> A_ADDR_DEC<2> ++ A_ADDR_DEC<1> A_ADDR_DEC<0> A_BIST_BM_I A_BIST_DW_I A_BIST_EN_I A_BLC<31> ++ A_BLC<30> A_BLC<29> A_BLC<28> A_BLC<27> A_BLC<26> A_BLC<25> A_BLC<24> ++ A_BLC<23> A_BLC<22> A_BLC<21> A_BLC<20> A_BLC<19> A_BLC<18> A_BLC<17> ++ A_BLC<16> A_BLC<15> A_BLC<14> A_BLC<13> A_BLC<12> A_BLC<11> A_BLC<10> ++ A_BLC<9> A_BLC<8> A_BLC<7> A_BLC<6> A_BLC<5> A_BLC<4> A_BLC<3> A_BLC<2> ++ A_BLC<1> A_BLC<0> A_BLT<31> A_BLT<30> A_BLT<29> A_BLT<28> A_BLT<27> ++ A_BLT<26> A_BLT<25> A_BLT<24> A_BLT<23> A_BLT<22> A_BLT<21> A_BLT<20> ++ A_BLT<19> A_BLT<18> A_BLT<17> A_BLT<16> A_BLT<15> A_BLT<14> A_BLT<13> ++ A_BLT<12> A_BLT<11> A_BLT<10> A_BLT<9> A_BLT<8> A_BLT<7> A_BLT<6> A_BLT<5> ++ A_BLT<4> A_BLT<3> A_BLT<2> A_BLT<1> A_BLT<0> A_BM_I A_DCLK_B_L A_DCLK_B_R ++ A_DCLK_L A_DCLK_R A_DR_O A_DW_I A_RCLK_B_L A_RCLK_B_R A_RCLK_L A_RCLK_R ++ A_TIEH_O A_WCLK_B_L A_WCLK_B_R A_WCLK_L A_WCLK_R VDD VSS +XA_I80<1> A_WCLK_B_L A_RCLK_B_L A_W_nor_R<1> VDD VSS / ++ RSC_IHPSG13_AND2X2 +XA_I80<0> A_WCLK_B_L A_RCLK_B_L A_W_nor_R<0> VDD VSS / ++ RSC_IHPSG13_AND2X2 +XA_I44 A_BM_N A_WCLK_B_L A_DO_WRITE_P VDD VSS / RSC_IHPSG13_NOR2X2 +XI80<29> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI80<28> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI80<27> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI80<26> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI80<25> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI80<24> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI80<23> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI80<22> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI80<21> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI80<20> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI80<19> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI80<18> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI80<17> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI80<16> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI80<15> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI80<14> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI80<13> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI80<12> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI80<11> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI80<10> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI80<9> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI80<8> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI80<7> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI80<6> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI80<5> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI80<4> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI80<3> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI80<2> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI80<1> VDD VSS / RSC_IHPSG13_FILLCAP8 +XA_I74<16> VDD VSS / RSC_IHPSG13_FILLCAP8 +XA_I74<15> VDD VSS / RSC_IHPSG13_FILLCAP8 +XA_I74<14> VDD VSS / RSC_IHPSG13_FILLCAP8 +XA_I74<13> VDD VSS / RSC_IHPSG13_FILLCAP8 +XA_I74<12> VDD VSS / RSC_IHPSG13_FILLCAP8 +XA_I74<11> VDD VSS / RSC_IHPSG13_FILLCAP8 +XA_I74<10> VDD VSS / RSC_IHPSG13_FILLCAP8 +XA_I74<9> VDD VSS / RSC_IHPSG13_FILLCAP8 +XA_I74<8> VDD VSS / RSC_IHPSG13_FILLCAP8 +XA_I74<7> VDD VSS / RSC_IHPSG13_FILLCAP8 +XA_I74<6> VDD VSS / RSC_IHPSG13_FILLCAP8 +XA_I74<5> VDD VSS / RSC_IHPSG13_FILLCAP8 +XA_I74<4> VDD VSS / RSC_IHPSG13_FILLCAP8 +XA_I74<3> VDD VSS / RSC_IHPSG13_FILLCAP8 +XA_I74<2> VDD VSS / RSC_IHPSG13_FILLCAP8 +XA_I74<1> VDD VSS / RSC_IHPSG13_FILLCAP8 +XA_INV<6> A_N1<1> A_P1<1> VDD VSS / RSC_IHPSG13_CINVX4 +XA_INV<5> A_N0<1> A_P0<1> VDD VSS / RSC_IHPSG13_CINVX4 +XA_INV<4> A_N0<0> A_P0<0> VDD VSS / RSC_IHPSG13_CINVX4 +XA_INV<3> A_ADDR_COL<1> A_N1<1> VDD VSS / RSC_IHPSG13_CINVX4 +XA_INV<2> A_ADDR_COL<1> A_N1<0> VDD VSS / RSC_IHPSG13_CINVX4 +XA_INV<1> A_ADDR_COL<0> A_N0<1> VDD VSS / RSC_IHPSG13_CINVX4 +XA_INV<0> A_ADDR_COL<0> A_N0<0> VDD VSS / RSC_IHPSG13_CINVX4 +XA_I81<3> A_W_nor_R<1> A_PRE_N VDD VSS / RSC_IHPSG13_CINVX4_WN +XA_I81<2> A_W_nor_R<1> A_PRE_N VDD VSS / RSC_IHPSG13_CINVX4_WN +XA_I81<1> A_W_nor_R<0> A_PRE_N VDD VSS / RSC_IHPSG13_CINVX4_WN +XA_I81<0> A_W_nor_R<0> A_PRE_N VDD VSS / RSC_IHPSG13_CINVX4_WN +XA_BLTMUX<31> A_BLC<31> A_BLC_SEL A_BLT<31> A_BLT_SEL A_PRE_N A_SEL_P<31> ++ A_WR_ONE A_WR_ZERO VDD VSS / RM_IHPSG13_256x8_c3_1P_BLDRV +XA_BLTMUX<30> A_BLC<30> A_BLC_SEL A_BLT<30> A_BLT_SEL A_PRE_N A_SEL_P<30> ++ A_WR_ONE A_WR_ZERO VDD VSS / RM_IHPSG13_256x8_c3_1P_BLDRV +XA_BLTMUX<29> A_BLC<29> A_BLC_SEL A_BLT<29> A_BLT_SEL A_PRE_N A_SEL_P<29> ++ A_WR_ONE A_WR_ZERO VDD VSS / RM_IHPSG13_256x8_c3_1P_BLDRV +XA_BLTMUX<28> A_BLC<28> A_BLC_SEL A_BLT<28> A_BLT_SEL A_PRE_N A_SEL_P<28> ++ A_WR_ONE A_WR_ZERO VDD VSS / RM_IHPSG13_256x8_c3_1P_BLDRV +XA_BLTMUX<27> A_BLC<27> A_BLC_SEL A_BLT<27> A_BLT_SEL A_PRE_N A_SEL_P<27> ++ A_WR_ONE A_WR_ZERO VDD VSS / RM_IHPSG13_256x8_c3_1P_BLDRV +XA_BLTMUX<26> A_BLC<26> A_BLC_SEL A_BLT<26> A_BLT_SEL A_PRE_N A_SEL_P<26> ++ A_WR_ONE A_WR_ZERO VDD VSS / RM_IHPSG13_256x8_c3_1P_BLDRV +XA_BLTMUX<25> A_BLC<25> A_BLC_SEL A_BLT<25> A_BLT_SEL A_PRE_N A_SEL_P<25> ++ A_WR_ONE A_WR_ZERO VDD VSS / RM_IHPSG13_256x8_c3_1P_BLDRV +XA_BLTMUX<24> A_BLC<24> A_BLC_SEL A_BLT<24> A_BLT_SEL A_PRE_N A_SEL_P<24> ++ A_WR_ONE A_WR_ZERO VDD VSS / RM_IHPSG13_256x8_c3_1P_BLDRV +XA_BLTMUX<23> A_BLC<23> A_BLC_SEL A_BLT<23> A_BLT_SEL A_PRE_N A_SEL_P<23> ++ A_WR_ONE A_WR_ZERO VDD VSS / RM_IHPSG13_256x8_c3_1P_BLDRV +XA_BLTMUX<22> A_BLC<22> A_BLC_SEL A_BLT<22> A_BLT_SEL A_PRE_N A_SEL_P<22> ++ A_WR_ONE A_WR_ZERO VDD VSS / RM_IHPSG13_256x8_c3_1P_BLDRV +XA_BLTMUX<21> A_BLC<21> A_BLC_SEL A_BLT<21> A_BLT_SEL A_PRE_N A_SEL_P<21> ++ A_WR_ONE A_WR_ZERO VDD VSS / RM_IHPSG13_256x8_c3_1P_BLDRV +XA_BLTMUX<20> A_BLC<20> A_BLC_SEL A_BLT<20> A_BLT_SEL A_PRE_N A_SEL_P<20> ++ A_WR_ONE A_WR_ZERO VDD VSS / RM_IHPSG13_256x8_c3_1P_BLDRV +XA_BLTMUX<19> A_BLC<19> A_BLC_SEL A_BLT<19> A_BLT_SEL A_PRE_N A_SEL_P<19> ++ A_WR_ONE A_WR_ZERO VDD VSS / RM_IHPSG13_256x8_c3_1P_BLDRV +XA_BLTMUX<18> A_BLC<18> A_BLC_SEL A_BLT<18> A_BLT_SEL A_PRE_N A_SEL_P<18> ++ A_WR_ONE A_WR_ZERO VDD VSS / RM_IHPSG13_256x8_c3_1P_BLDRV +XA_BLTMUX<17> A_BLC<17> A_BLC_SEL A_BLT<17> A_BLT_SEL A_PRE_N A_SEL_P<17> ++ A_WR_ONE A_WR_ZERO VDD VSS / RM_IHPSG13_256x8_c3_1P_BLDRV +XA_BLTMUX<16> A_BLC<16> A_BLC_SEL A_BLT<16> A_BLT_SEL A_PRE_N A_SEL_P<16> ++ A_WR_ONE A_WR_ZERO VDD VSS / RM_IHPSG13_256x8_c3_1P_BLDRV +XA_BLTMUX<15> A_BLC<15> A_BLC_SEL A_BLT<15> A_BLT_SEL A_PRE_N A_SEL_P<15> ++ A_WR_ONE A_WR_ZERO VDD VSS / RM_IHPSG13_256x8_c3_1P_BLDRV +XA_BLTMUX<14> A_BLC<14> A_BLC_SEL A_BLT<14> A_BLT_SEL A_PRE_N A_SEL_P<14> ++ A_WR_ONE A_WR_ZERO VDD VSS / RM_IHPSG13_256x8_c3_1P_BLDRV +XA_BLTMUX<13> A_BLC<13> A_BLC_SEL A_BLT<13> A_BLT_SEL A_PRE_N A_SEL_P<13> ++ A_WR_ONE A_WR_ZERO VDD VSS / RM_IHPSG13_256x8_c3_1P_BLDRV +XA_BLTMUX<12> A_BLC<12> A_BLC_SEL A_BLT<12> A_BLT_SEL A_PRE_N A_SEL_P<12> ++ A_WR_ONE A_WR_ZERO VDD VSS / RM_IHPSG13_256x8_c3_1P_BLDRV +XA_BLTMUX<11> A_BLC<11> A_BLC_SEL A_BLT<11> A_BLT_SEL A_PRE_N A_SEL_P<11> ++ A_WR_ONE A_WR_ZERO VDD VSS / RM_IHPSG13_256x8_c3_1P_BLDRV +XA_BLTMUX<10> A_BLC<10> A_BLC_SEL A_BLT<10> A_BLT_SEL A_PRE_N A_SEL_P<10> ++ A_WR_ONE A_WR_ZERO VDD VSS / RM_IHPSG13_256x8_c3_1P_BLDRV +XA_BLTMUX<9> A_BLC<9> A_BLC_SEL A_BLT<9> A_BLT_SEL A_PRE_N A_SEL_P<9> A_WR_ONE ++ A_WR_ZERO VDD VSS / RM_IHPSG13_256x8_c3_1P_BLDRV +XA_BLTMUX<8> A_BLC<8> A_BLC_SEL A_BLT<8> A_BLT_SEL A_PRE_N A_SEL_P<8> A_WR_ONE ++ A_WR_ZERO VDD VSS / RM_IHPSG13_256x8_c3_1P_BLDRV +XA_BLTMUX<7> A_BLC<7> A_BLC_SEL A_BLT<7> A_BLT_SEL A_PRE_N A_SEL_P<7> A_WR_ONE ++ A_WR_ZERO VDD VSS / RM_IHPSG13_256x8_c3_1P_BLDRV +XA_BLTMUX<6> A_BLC<6> A_BLC_SEL A_BLT<6> A_BLT_SEL A_PRE_N A_SEL_P<6> A_WR_ONE ++ A_WR_ZERO VDD VSS / RM_IHPSG13_256x8_c3_1P_BLDRV +XA_BLTMUX<5> A_BLC<5> A_BLC_SEL A_BLT<5> A_BLT_SEL A_PRE_N A_SEL_P<5> A_WR_ONE ++ A_WR_ZERO VDD VSS / RM_IHPSG13_256x8_c3_1P_BLDRV +XA_BLTMUX<4> A_BLC<4> A_BLC_SEL A_BLT<4> A_BLT_SEL A_PRE_N A_SEL_P<4> A_WR_ONE ++ A_WR_ZERO VDD VSS / RM_IHPSG13_256x8_c3_1P_BLDRV +XA_BLTMUX<3> A_BLC<3> A_BLC_SEL A_BLT<3> A_BLT_SEL A_PRE_N A_SEL_P<3> A_WR_ONE ++ A_WR_ZERO VDD VSS / RM_IHPSG13_256x8_c3_1P_BLDRV +XA_BLTMUX<2> A_BLC<2> A_BLC_SEL A_BLT<2> A_BLT_SEL A_PRE_N A_SEL_P<2> A_WR_ONE ++ A_WR_ZERO VDD VSS / RM_IHPSG13_256x8_c3_1P_BLDRV +XA_BLTMUX<1> A_BLC<1> A_BLC_SEL A_BLT<1> A_BLT_SEL A_PRE_N A_SEL_P<1> A_WR_ONE ++ A_WR_ZERO VDD VSS / RM_IHPSG13_256x8_c3_1P_BLDRV +XA_BLTMUX<0> A_BLC<0> A_BLC_SEL A_BLT<0> A_BLT_SEL A_PRE_N A_SEL_P<0> A_WR_ONE ++ A_WR_ZERO VDD VSS / RM_IHPSG13_256x8_c3_1P_BLDRV +XA_CAPS<17> VDD VSS / RSC_IHPSG13_FILLCAP4 +XA_CAPS<16> VDD VSS / RSC_IHPSG13_FILLCAP4 +XA_CAPS<15> VDD VSS / RSC_IHPSG13_FILLCAP4 +XA_CAPS<14> VDD VSS / RSC_IHPSG13_FILLCAP4 +XA_CAPS<13> VDD VSS / RSC_IHPSG13_FILLCAP4 +XA_CAPS<12> VDD VSS / RSC_IHPSG13_FILLCAP4 +XA_CAPS<11> VDD VSS / RSC_IHPSG13_FILLCAP4 +XA_CAPS<10> VDD VSS / RSC_IHPSG13_FILLCAP4 +XA_CAPS<9> VDD VSS / RSC_IHPSG13_FILLCAP4 +XA_CAPS<8> VDD VSS / RSC_IHPSG13_FILLCAP4 +XA_CAPS<7> VDD VSS / RSC_IHPSG13_FILLCAP4 +XA_CAPS<6> VDD VSS / RSC_IHPSG13_FILLCAP4 +XA_CAPS<5> VDD VSS / RSC_IHPSG13_FILLCAP4 +XA_CAPS<4> VDD VSS / RSC_IHPSG13_FILLCAP4 +XA_CAPS<3> VDD VSS / RSC_IHPSG13_FILLCAP4 +XA_CAPS<2> VDD VSS / RSC_IHPSG13_FILLCAP4 +XA_CAPS<1> VDD VSS / RSC_IHPSG13_FILLCAP4 +XA_I51 net19 A_DR_O VDD VSS / RSC_IHPSG13_INVX4 +XA_I78 A_RCLK_B_L A_SAE VDD VSS / RSC_IHPSG13_CBUFX2 +XA_I69 A_DCLK_L A_DCLK_B_L VDD VSS / RSC_IHPSG13_CINVX8 +XA_I50 A_WCLK_L A_WCLK_B_L VDD VSS / RSC_IHPSG13_CINVX8 +XA_EBUF A_RCLK_L A_RCLK_B_L VDD VSS / RSC_IHPSG13_CINVX8 +XA_I76 A_DI_N A_DO_WRITE_P A_WR_ZERO VDD VSS / RSC_IHPSG13_AND2X6 +XA_I75 A_DI_R A_DO_WRITE_P A_WR_ONE VDD VSS / RSC_IHPSG13_AND2X6 +XA_I83 A_BM_R A_BM_N VDD VSS / RSC_IHPSG13_INVX2 +XA_DEC3INV<31> net23<0> A_SEL_P<31> VDD VSS / RSC_IHPSG13_INVX2 +XA_DEC3INV<30> net23<1> A_SEL_P<30> VDD VSS / RSC_IHPSG13_INVX2 +XA_DEC3INV<29> net23<2> A_SEL_P<29> VDD VSS / RSC_IHPSG13_INVX2 +XA_DEC3INV<28> net23<3> A_SEL_P<28> VDD VSS / RSC_IHPSG13_INVX2 +XA_DEC3INV<27> net23<4> A_SEL_P<27> VDD VSS / RSC_IHPSG13_INVX2 +XA_DEC3INV<26> net23<5> A_SEL_P<26> VDD VSS / RSC_IHPSG13_INVX2 +XA_DEC3INV<25> net23<6> A_SEL_P<25> VDD VSS / RSC_IHPSG13_INVX2 +XA_DEC3INV<24> net23<7> A_SEL_P<24> VDD VSS / RSC_IHPSG13_INVX2 +XA_DEC3INV<23> net23<8> A_SEL_P<23> VDD VSS / RSC_IHPSG13_INVX2 +XA_DEC3INV<22> net23<9> A_SEL_P<22> VDD VSS / RSC_IHPSG13_INVX2 +XA_DEC3INV<21> net23<10> A_SEL_P<21> VDD VSS / RSC_IHPSG13_INVX2 +XA_DEC3INV<20> net23<11> A_SEL_P<20> VDD VSS / RSC_IHPSG13_INVX2 +XA_DEC3INV<19> net23<12> A_SEL_P<19> VDD VSS / RSC_IHPSG13_INVX2 +XA_DEC3INV<18> net23<13> A_SEL_P<18> VDD VSS / RSC_IHPSG13_INVX2 +XA_DEC3INV<17> net23<14> A_SEL_P<17> VDD VSS / RSC_IHPSG13_INVX2 +XA_DEC3INV<16> net23<15> A_SEL_P<16> VDD VSS / RSC_IHPSG13_INVX2 +XA_DEC3INV<15> net23<16> A_SEL_P<15> VDD VSS / RSC_IHPSG13_INVX2 +XA_DEC3INV<14> net23<17> A_SEL_P<14> VDD VSS / RSC_IHPSG13_INVX2 +XA_DEC3INV<13> net23<18> A_SEL_P<13> VDD VSS / RSC_IHPSG13_INVX2 +XA_DEC3INV<12> net23<19> A_SEL_P<12> VDD VSS / RSC_IHPSG13_INVX2 +XA_DEC3INV<11> net23<20> A_SEL_P<11> VDD VSS / RSC_IHPSG13_INVX2 +XA_DEC3INV<10> net23<21> A_SEL_P<10> VDD VSS / RSC_IHPSG13_INVX2 +XA_DEC3INV<9> net23<22> A_SEL_P<9> VDD VSS / RSC_IHPSG13_INVX2 +XA_DEC3INV<8> net23<23> A_SEL_P<8> VDD VSS / RSC_IHPSG13_INVX2 +XA_DEC3INV<7> net23<24> A_SEL_P<7> VDD VSS / RSC_IHPSG13_INVX2 +XA_DEC3INV<6> net23<25> A_SEL_P<6> VDD VSS / RSC_IHPSG13_INVX2 +XA_DEC3INV<5> net23<26> A_SEL_P<5> VDD VSS / RSC_IHPSG13_INVX2 +XA_DEC3INV<4> net23<27> A_SEL_P<4> VDD VSS / RSC_IHPSG13_INVX2 +XA_DEC3INV<3> net23<28> A_SEL_P<3> VDD VSS / RSC_IHPSG13_INVX2 +XA_DEC3INV<2> net23<29> A_SEL_P<2> VDD VSS / RSC_IHPSG13_INVX2 +XA_DEC3INV<1> net23<30> A_SEL_P<1> VDD VSS / RSC_IHPSG13_INVX2 +XA_DEC3INV<0> net23<31> A_SEL_P<0> VDD VSS / RSC_IHPSG13_INVX2 +XA_I49 A_DI_R A_DI_N VDD VSS / RSC_IHPSG13_INVX2 +XA_ISENSE A_SAE A_BLC_SEL A_BLT_SEL net19 net20 VDD VSS / ++ RSC_IHPSG13_DFPQD_MSAFFX2 +XA_DREG A_BIST_EN_I A_BIST_DW_I A_DCLK_B_L A_DW_I A_DI_R net22 VDD VSS ++ / RSC_IHPSG13_DFNQMX2IX1 +XA_BREG A_BIST_EN_I A_BIST_BM_I A_DCLK_B_L A_BM_I A_BM_R net21 VDD VSS ++ / RSC_IHPSG13_DFNQMX2IX1 +XA_DEC3<31> A_P1<1> A_P0<1> A_ADDR_DEC<7> net23<0> VDD VSS / ++ RSC_IHPSG13_NAND3X2 +XA_DEC3<30> A_P1<1> A_P0<1> A_ADDR_DEC<6> net23<1> VDD VSS / ++ RSC_IHPSG13_NAND3X2 +XA_DEC3<29> A_P1<1> A_P0<1> A_ADDR_DEC<5> net23<2> VDD VSS / ++ RSC_IHPSG13_NAND3X2 +XA_DEC3<28> A_P1<1> A_P0<1> A_ADDR_DEC<4> net23<3> VDD VSS / ++ RSC_IHPSG13_NAND3X2 +XA_DEC3<27> A_P1<1> A_P0<1> A_ADDR_DEC<3> net23<4> VDD VSS / ++ RSC_IHPSG13_NAND3X2 +XA_DEC3<26> A_P1<1> A_P0<1> A_ADDR_DEC<2> net23<5> VDD VSS / ++ RSC_IHPSG13_NAND3X2 +XA_DEC3<25> A_P1<1> A_P0<1> A_ADDR_DEC<1> net23<6> VDD VSS / ++ RSC_IHPSG13_NAND3X2 +XA_DEC3<24> A_P1<1> A_P0<1> A_ADDR_DEC<0> net23<7> VDD VSS / ++ RSC_IHPSG13_NAND3X2 +XA_DEC3<23> A_P1<1> A_N0<1> A_ADDR_DEC<7> net23<8> VDD VSS / ++ RSC_IHPSG13_NAND3X2 +XA_DEC3<22> A_P1<1> A_N0<1> A_ADDR_DEC<6> net23<9> VDD VSS / ++ RSC_IHPSG13_NAND3X2 +XA_DEC3<21> A_P1<1> A_N0<1> A_ADDR_DEC<5> net23<10> VDD VSS / ++ RSC_IHPSG13_NAND3X2 +XA_DEC3<20> A_P1<1> A_N0<1> A_ADDR_DEC<4> net23<11> VDD VSS / ++ RSC_IHPSG13_NAND3X2 +XA_DEC3<19> A_P1<1> A_N0<1> A_ADDR_DEC<3> net23<12> VDD VSS / ++ RSC_IHPSG13_NAND3X2 +XA_DEC3<18> A_P1<1> A_N0<1> A_ADDR_DEC<2> net23<13> VDD VSS / ++ RSC_IHPSG13_NAND3X2 +XA_DEC3<17> A_P1<1> A_N0<1> A_ADDR_DEC<1> net23<14> VDD VSS / ++ RSC_IHPSG13_NAND3X2 +XA_DEC3<16> A_P1<1> A_N0<1> A_ADDR_DEC<0> net23<15> VDD VSS / ++ RSC_IHPSG13_NAND3X2 +XA_DEC3<15> A_N1<0> A_P0<0> A_ADDR_DEC<7> net23<16> VDD VSS / ++ RSC_IHPSG13_NAND3X2 +XA_DEC3<14> A_N1<0> A_P0<0> A_ADDR_DEC<6> net23<17> VDD VSS / ++ RSC_IHPSG13_NAND3X2 +XA_DEC3<13> A_N1<0> A_P0<0> A_ADDR_DEC<5> net23<18> VDD VSS / ++ RSC_IHPSG13_NAND3X2 +XA_DEC3<12> A_N1<0> A_P0<0> A_ADDR_DEC<4> net23<19> VDD VSS / ++ RSC_IHPSG13_NAND3X2 +XA_DEC3<11> A_N1<0> A_P0<0> A_ADDR_DEC<3> net23<20> VDD VSS / ++ RSC_IHPSG13_NAND3X2 +XA_DEC3<10> A_N1<0> A_P0<0> A_ADDR_DEC<2> net23<21> VDD VSS / ++ RSC_IHPSG13_NAND3X2 +XA_DEC3<9> A_N1<0> A_P0<0> A_ADDR_DEC<1> net23<22> VDD VSS / ++ RSC_IHPSG13_NAND3X2 +XA_DEC3<8> A_N1<0> A_P0<0> A_ADDR_DEC<0> net23<23> VDD VSS / ++ RSC_IHPSG13_NAND3X2 +XA_DEC3<7> A_N1<0> A_N0<0> A_ADDR_DEC<7> net23<24> VDD VSS / ++ RSC_IHPSG13_NAND3X2 +XA_DEC3<6> A_N1<0> A_N0<0> A_ADDR_DEC<6> net23<25> VDD VSS / ++ RSC_IHPSG13_NAND3X2 +XA_DEC3<5> A_N1<0> A_N0<0> A_ADDR_DEC<5> net23<26> VDD VSS / ++ RSC_IHPSG13_NAND3X2 +XA_DEC3<4> A_N1<0> A_N0<0> A_ADDR_DEC<4> net23<27> VDD VSS / ++ RSC_IHPSG13_NAND3X2 +XA_DEC3<3> A_N1<0> A_N0<0> A_ADDR_DEC<3> net23<28> VDD VSS / ++ RSC_IHPSG13_NAND3X2 +XA_DEC3<2> A_N1<0> A_N0<0> A_ADDR_DEC<2> net23<29> VDD VSS / ++ RSC_IHPSG13_NAND3X2 +XA_DEC3<1> A_N1<0> A_N0<0> A_ADDR_DEC<1> net23<30> VDD VSS / ++ RSC_IHPSG13_NAND3X2 +XA_DEC3<0> A_N1<0> A_N0<0> A_ADDR_DEC<0> net23<31> VDD VSS / ++ RSC_IHPSG13_NAND3X2 +XA_I89 A_DCLK_B_L A_DCLK_B_R / RSC_IHPSG13_MET3RES +XA_I91 A_RCLK_B_L A_RCLK_B_R / RSC_IHPSG13_MET3RES +XA_I90 A_WCLK_B_L A_WCLK_B_R / RSC_IHPSG13_MET3RES +XA_I88 A_DCLK_L A_DCLK_R / RSC_IHPSG13_MET3RES +XA_I87 A_WCLK_L A_WCLK_R / RSC_IHPSG13_MET3RES +XA_R2 A_RCLK_L A_RCLK_R / RSC_IHPSG13_MET3RES +XA_BM_TIEH A_TIEH_O VDD VSS / RSC_IHPSG13_TIEH +.ENDS + +.SUBCKT RM_IHPSG13_256x8_c3_1P_COLDRV13X12 ADDR_COL_I<1> ADDR_COL_I<0> ADDR_COL_O<1> ++ ADDR_COL_O<0> ADDR_DEC_I<7> ADDR_DEC_I<6> ADDR_DEC_I<5> ADDR_DEC_I<4> ++ ADDR_DEC_I<3> ADDR_DEC_I<2> ADDR_DEC_I<1> ADDR_DEC_I<0> ADDR_DEC_O<7> ++ ADDR_DEC_O<6> ADDR_DEC_O<5> ADDR_DEC_O<4> ADDR_DEC_O<3> ADDR_DEC_O<2> ++ ADDR_DEC_O<1> ADDR_DEC_O<0> DCLK_I DCLK_O RCLK_I RCLK_O WCLK_I WCLK_O ++ VDD VSS +XI1<1> VDD VSS / RSC_IHPSG13_FILLCAP4 +XI1<0> VDD VSS / RSC_IHPSG13_FILLCAP4 +XI0<1> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI0<0> VDD VSS / RSC_IHPSG13_FILLCAP8 +XADDR_COL_DRV<1> ADDR_COL_I<1> ADDR_COL_O<1> VDD VSS / ++ RSC_IHPSG13_CBUFX12 +XADDR_COL_DRV<0> ADDR_COL_I<0> ADDR_COL_O<0> VDD VSS / ++ RSC_IHPSG13_CBUFX12 +XADDR_DEC_DRV<7> ADDR_DEC_I<7> ADDR_DEC_O<7> VDD VSS / ++ RSC_IHPSG13_CBUFX12 +XADDR_DEC_DRV<6> ADDR_DEC_I<6> ADDR_DEC_O<6> VDD VSS / ++ RSC_IHPSG13_CBUFX12 +XADDR_DEC_DRV<5> ADDR_DEC_I<5> ADDR_DEC_O<5> VDD VSS / ++ RSC_IHPSG13_CBUFX12 +XADDR_DEC_DRV<4> ADDR_DEC_I<4> ADDR_DEC_O<4> VDD VSS / ++ RSC_IHPSG13_CBUFX12 +XADDR_DEC_DRV<3> ADDR_DEC_I<3> ADDR_DEC_O<3> VDD VSS / ++ RSC_IHPSG13_CBUFX12 +XADDR_DEC_DRV<2> ADDR_DEC_I<2> ADDR_DEC_O<2> VDD VSS / ++ RSC_IHPSG13_CBUFX12 +XADDR_DEC_DRV<1> ADDR_DEC_I<1> ADDR_DEC_O<1> VDD VSS / ++ RSC_IHPSG13_CBUFX12 +XADDR_DEC_DRV<0> ADDR_DEC_I<0> ADDR_DEC_O<0> VDD VSS / ++ RSC_IHPSG13_CBUFX12 +XDCLK_DRV DCLK_I DCLK_O VDD VSS / RSC_IHPSG13_CBUFX12 +XRCLK_DRV RCLK_I RCLK_O VDD VSS / RSC_IHPSG13_CBUFX12 +XWCLK_DRV WCLK_I WCLK_O VDD VSS / RSC_IHPSG13_CBUFX12 +.ENDS +.SUBCKT RM_IHPSG13_256x8_c3_1P_WLDRV16X12 A<15> A<14> A<13> A<12> A<11> A<10> A<9> A<8> ++ A<7> A<6> A<5> A<4> A<3> A<2> A<1> A<0> Z<15> Z<14> Z<13> Z<12> Z<11> Z<10> ++ Z<9> Z<8> Z<7> Z<6> Z<5> Z<4> Z<3> Z<2> Z<1> Z<0> VDD VSS +XBUF<15> A<15> Z<15> VDD VSS / RSC_IHPSG13_WLDRVX12 +XBUF<14> A<14> Z<14> VDD VSS / RSC_IHPSG13_WLDRVX12 +XBUF<13> A<13> Z<13> VDD VSS / RSC_IHPSG13_WLDRVX12 +XBUF<12> A<12> Z<12> VDD VSS / RSC_IHPSG13_WLDRVX12 +XBUF<11> A<11> Z<11> VDD VSS / RSC_IHPSG13_WLDRVX12 +XBUF<10> A<10> Z<10> VDD VSS / RSC_IHPSG13_WLDRVX12 +XBUF<9> A<9> Z<9> VDD VSS / RSC_IHPSG13_WLDRVX12 +XBUF<8> A<8> Z<8> VDD VSS / RSC_IHPSG13_WLDRVX12 +XBUF<7> A<7> Z<7> VDD VSS / RSC_IHPSG13_WLDRVX12 +XBUF<6> A<6> Z<6> VDD VSS / RSC_IHPSG13_WLDRVX12 +XBUF<5> A<5> Z<5> VDD VSS / RSC_IHPSG13_WLDRVX12 +XBUF<4> A<4> Z<4> VDD VSS / RSC_IHPSG13_WLDRVX12 +XBUF<3> A<3> Z<3> VDD VSS / RSC_IHPSG13_WLDRVX12 +XBUF<2> A<2> Z<2> VDD VSS / RSC_IHPSG13_WLDRVX12 +XBUF<1> A<1> Z<1> VDD VSS / RSC_IHPSG13_WLDRVX12 +XBUF<0> A<0> Z<0> VDD VSS / RSC_IHPSG13_WLDRVX12 +.ENDS + + + +.SUBCKT RM_IHPSG13_256x8_c3_2P_COLDRV13X8 ADDR_COL_I<1> ADDR_COL_I<0> ADDR_COL_O<1> ++ ADDR_COL_O<0> ADDR_DEC_I<7> ADDR_DEC_I<6> ADDR_DEC_I<5> ADDR_DEC_I<4> ++ ADDR_DEC_I<3> ADDR_DEC_I<2> ADDR_DEC_I<1> ADDR_DEC_I<0> ADDR_DEC_O<7> ++ ADDR_DEC_O<6> ADDR_DEC_O<5> ADDR_DEC_O<4> ADDR_DEC_O<3> ADDR_DEC_O<2> ++ ADDR_DEC_O<1> ADDR_DEC_O<0> DCLK_I DCLK_O RCLK_I RCLK_O WCLK_I WCLK_O ++ VDD VSS +XI0<5> VDD VSS / RSC_IHPSG13_FILLCAP4 +XI0<4> VDD VSS / RSC_IHPSG13_FILLCAP4 +XI0<3> VDD VSS / RSC_IHPSG13_FILLCAP4 +XI0<2> VDD VSS / RSC_IHPSG13_FILLCAP4 +XI0<1> VDD VSS / RSC_IHPSG13_FILLCAP4 +XWCLK_DRV WCLK_I WCLK_O VDD VSS / RSC_IHPSG13_CBUFX8 +XRCLK_DRV RCLK_I RCLK_O VDD VSS / RSC_IHPSG13_CBUFX8 +XDCLK_DRV DCLK_I DCLK_O VDD VSS / RSC_IHPSG13_CBUFX8 +XADDR_COL_DRV<1> ADDR_COL_I<1> ADDR_COL_O<1> VDD VSS / ++ RSC_IHPSG13_CBUFX8 +XADDR_COL_DRV<0> ADDR_COL_I<0> ADDR_COL_O<0> VDD VSS / ++ RSC_IHPSG13_CBUFX8 +XADDR_DEC_DRV<7> ADDR_DEC_I<7> ADDR_DEC_O<7> VDD VSS / ++ RSC_IHPSG13_CBUFX8 +XADDR_DEC_DRV<6> ADDR_DEC_I<6> ADDR_DEC_O<6> VDD VSS / ++ RSC_IHPSG13_CBUFX8 +XADDR_DEC_DRV<5> ADDR_DEC_I<5> ADDR_DEC_O<5> VDD VSS / ++ RSC_IHPSG13_CBUFX8 +XADDR_DEC_DRV<4> ADDR_DEC_I<4> ADDR_DEC_O<4> VDD VSS / ++ RSC_IHPSG13_CBUFX8 +XADDR_DEC_DRV<3> ADDR_DEC_I<3> ADDR_DEC_O<3> VDD VSS / ++ RSC_IHPSG13_CBUFX8 +XADDR_DEC_DRV<2> ADDR_DEC_I<2> ADDR_DEC_O<2> VDD VSS / ++ RSC_IHPSG13_CBUFX8 +XADDR_DEC_DRV<1> ADDR_DEC_I<1> ADDR_DEC_O<1> VDD VSS / ++ RSC_IHPSG13_CBUFX8 +XADDR_DEC_DRV<0> ADDR_DEC_I<0> ADDR_DEC_O<0> VDD VSS / ++ RSC_IHPSG13_CBUFX8 +XI1<3> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI1<2> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI1<1> VDD VSS / RSC_IHPSG13_FILLCAP8 +.ENDS +.SUBCKT RSC_IHPSG13_WLDRVX8 A Z VDD VSS +MN1 Z net6 VSS VSS sg13_lv_nmos m=1 w=1.41u l=130.00n ng=2 nrd=0 nrs=0 +MN0 net6 A VSS VSS sg13_lv_nmos m=1 w=1.8u l=130.00n ng=2 nrd=0 nrs=0 +MP1 Z net6 VDD VDD sg13_lv_pmos m=1 w=6.48u l=130.00n ng=4 nrd=0 nrs=0 +MP0 net6 A VDD VDD sg13_lv_pmos m=1 w=900.0n l=130.00n ng=1 nrd=0 nrs=0 +.ENDS +.SUBCKT RM_IHPSG13_256x8_c3_2P_WLDRV16X8 A<15> A<14> A<13> A<12> A<11> A<10> A<9> A<8> ++ A<7> A<6> A<5> A<4> A<3> A<2> A<1> A<0> Z<15> Z<14> Z<13> Z<12> Z<11> Z<10> ++ Z<9> Z<8> Z<7> Z<6> Z<5> Z<4> Z<3> Z<2> Z<1> Z<0> VDD VSS +XBUF<15> A<15> Z<15> VDD VSS / RSC_IHPSG13_WLDRVX8 +XBUF<14> A<14> Z<14> VDD VSS / RSC_IHPSG13_WLDRVX8 +XBUF<13> A<13> Z<13> VDD VSS / RSC_IHPSG13_WLDRVX8 +XBUF<12> A<12> Z<12> VDD VSS / RSC_IHPSG13_WLDRVX8 +XBUF<11> A<11> Z<11> VDD VSS / RSC_IHPSG13_WLDRVX8 +XBUF<10> A<10> Z<10> VDD VSS / RSC_IHPSG13_WLDRVX8 +XBUF<9> A<9> Z<9> VDD VSS / RSC_IHPSG13_WLDRVX8 +XBUF<8> A<8> Z<8> VDD VSS / RSC_IHPSG13_WLDRVX8 +XBUF<7> A<7> Z<7> VDD VSS / RSC_IHPSG13_WLDRVX8 +XBUF<6> A<6> Z<6> VDD VSS / RSC_IHPSG13_WLDRVX8 +XBUF<5> A<5> Z<5> VDD VSS / RSC_IHPSG13_WLDRVX8 +XBUF<4> A<4> Z<4> VDD VSS / RSC_IHPSG13_WLDRVX8 +XBUF<3> A<3> Z<3> VDD VSS / RSC_IHPSG13_WLDRVX8 +XBUF<2> A<2> Z<2> VDD VSS / RSC_IHPSG13_WLDRVX8 +XBUF<1> A<1> Z<1> VDD VSS / RSC_IHPSG13_WLDRVX8 +XBUF<0> A<0> Z<0> VDD VSS / RSC_IHPSG13_WLDRVX8 +.ENDS + + + +.SUBCKT RM_IHPSG13_256x8_c3_2P_COLDEC2 ACLK_N ADDR<1> ADDR<0> ADDR_COL<1> ADDR_COL<0> ++ ADDR_DEC<7> ADDR_DEC<6> ADDR_DEC<5> ADDR_DEC<4> ADDR_DEC<3> ADDR_DEC<2> ++ ADDR_DEC<1> ADDR_DEC<0> BIST_ADDR<1> BIST_ADDR<0> BIST_EN_I VDD VSS +XI16<17> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI16<16> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI16<15> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI16<14> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI16<13> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI16<12> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI16<11> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI16<10> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI16<9> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI16<8> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI16<7> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI16<6> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI16<5> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI16<4> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI16<3> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI16<2> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI16<1> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI18<24> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI18<23> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI18<22> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI18<21> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI18<20> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI18<19> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI18<18> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI18<17> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI18<16> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI18<15> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI18<14> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI18<13> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI18<12> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI18<11> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI18<10> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI18<9> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI18<8> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI18<7> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI18<6> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI18<5> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI18<4> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI18<3> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI18<2> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI18<1> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI1<3> PADR<0> PADR<1> addr_n<3> VDD VSS / RSC_IHPSG13_NAND2X2 +XI1<2> NADR<0> PADR<1> addr_n<2> VDD VSS / RSC_IHPSG13_NAND2X2 +XI1<1> PADR<0> NADR<1> addr_n<1> VDD VSS / RSC_IHPSG13_NAND2X2 +XI1<0> NADR<0> NADR<1> addr_n<0> VDD VSS / RSC_IHPSG13_NAND2X2 +XI17<1> ADDR_COL<1> VDD VSS / RSC_IHPSG13_TIEL +XI17<0> ADDR_COL<0> VDD VSS / RSC_IHPSG13_TIEL +XI14<3> ADDR_DEC<7> VDD VSS / RSC_IHPSG13_TIEL +XI14<2> ADDR_DEC<6> VDD VSS / RSC_IHPSG13_TIEL +XI14<1> ADDR_DEC<5> VDD VSS / RSC_IHPSG13_TIEL +XI14<0> ADDR_DEC<4> VDD VSS / RSC_IHPSG13_TIEL +XI13<1> NADR<1> PADR<1> VDD VSS / RSC_IHPSG13_INVX2 +XI13<0> NADR<0> PADR<0> VDD VSS / RSC_IHPSG13_INVX2 +XI3<1> padr_int<1> NADR<1> VDD VSS / RSC_IHPSG13_INVX2 +XI3<0> padr_int<0> NADR<0> VDD VSS / RSC_IHPSG13_INVX2 +XI2<3> addr_n<3> ADDR_DEC<3> VDD VSS / RSC_IHPSG13_INVX2 +XI2<2> addr_n<2> ADDR_DEC<2> VDD VSS / RSC_IHPSG13_INVX2 +XI2<1> addr_n<1> ADDR_DEC<1> VDD VSS / RSC_IHPSG13_INVX2 +XI2<0> addr_n<0> ADDR_DEC<0> VDD VSS / RSC_IHPSG13_INVX2 +XDFF<1> BIST_EN_I BIST_ADDR<1> ACLK_N ADDR<1> padr_int<1> net12<0> VDD ++ VSS / RSC_IHPSG13_DFNQMX2IX1 +XDFF<0> BIST_EN_I BIST_ADDR<0> ACLK_N ADDR<0> padr_int<0> net12<1> VDD ++ VSS / RSC_IHPSG13_DFNQMX2IX1 +XI15<5> VDD VSS / RSC_IHPSG13_FILLCAP4 +XI15<4> VDD VSS / RSC_IHPSG13_FILLCAP4 +XI15<3> VDD VSS / RSC_IHPSG13_FILLCAP4 +XI15<2> VDD VSS / RSC_IHPSG13_FILLCAP4 +XI15<1> VDD VSS / RSC_IHPSG13_FILLCAP4 +XI19<4> VDD VSS / RSC_IHPSG13_FILLCAP4 +XI19<3> VDD VSS / RSC_IHPSG13_FILLCAP4 +XI19<2> VDD VSS / RSC_IHPSG13_FILLCAP4 +XI19<1> VDD VSS / RSC_IHPSG13_FILLCAP4 +.ENDS +.SUBCKT RM_IHPSG13_256x8_c3_2P_COLCTRL2 A_ADDR_DEC<3> A_ADDR_DEC<2> A_ADDR_DEC<1> ++ A_ADDR_DEC<0> A_BIST_BM_I A_BIST_DW_I A_BIST_EN_I A_BLC<3> A_BLC<2> A_BLC<1> ++ A_BLC<0> A_BLT<3> A_BLT<2> A_BLT<1> A_BLT<0> A_BM_I A_DCLK_B_L A_DCLK_B_R ++ A_DCLK_L A_DCLK_R A_DR_O A_DW_I A_RCLK_B_L A_RCLK_B_R A_RCLK_L A_RCLK_R ++ A_TIEH_O A_WCLK_B_L A_WCLK_B_R A_WCLK_L A_WCLK_R B_ADDR_DEC<3> B_ADDR_DEC<2> ++ B_ADDR_DEC<1> B_ADDR_DEC<0> B_BIST_BM_I B_BIST_DW_I B_BIST_EN_I B_BLC<3> ++ B_BLC<2> B_BLC<1> B_BLC<0> B_BLT<3> B_BLT<2> B_BLT<1> B_BLT<0> B_BM_I ++ B_DCLK_B_L B_DCLK_B_R B_DCLK_L B_DCLK_R B_DR_O B_DW_I B_RCLK_B_L B_RCLK_B_R ++ B_RCLK_L B_RCLK_R B_TIEH_O B_WCLK_B_L B_WCLK_B_R B_WCLK_L B_WCLK_R VDD ++ VSS +XB_DREG B_BIST_EN_I B_BIST_DW_I B_DCLK_B_L B_DW_I B_DI_R net046 VDD ++ VSS / RSC_IHPSG13_DFNQMX2IX1 +XB_BREG B_BIST_EN_I B_BIST_BM_I B_DCLK_B_L B_BM_I B_BM_R net045 VDD ++ VSS / RSC_IHPSG13_DFNQMX2IX1 +XA_DREG A_BIST_EN_I A_BIST_DW_I A_DCLK_B_L A_DW_I A_DI_R net22 VDD VSS ++ / RSC_IHPSG13_DFNQMX2IX1 +XA_BREG A_BIST_EN_I A_BIST_BM_I A_DCLK_B_L A_BM_I A_BM_R net23 VDD VSS ++ / RSC_IHPSG13_DFNQMX2IX1 +XB_CAPS VDD VSS / RSC_IHPSG13_FILLCAP4 +XA_CAPS VDD VSS / RSC_IHPSG13_FILLCAP4 +XB_I75 B_DI_R B_DO_WRITE_P B_WR_ONE VDD VSS / RSC_IHPSG13_AND2X2 +XB_I80 B_RCLK_B_L B_WCLK_B_L net041 VDD VSS / RSC_IHPSG13_AND2X2 +XB_I76 B_DI_N B_DO_WRITE_P B_WR_ZERO VDD VSS / RSC_IHPSG13_AND2X2 +XA_I80 A_RCLK_B_L A_WCLK_B_L net21 VDD VSS / RSC_IHPSG13_AND2X2 +XA_I75 A_DI_R A_DO_WRITE_P A_WR_ONE VDD VSS / RSC_IHPSG13_AND2X2 +XA_I76 A_DI_N A_DO_WRITE_P A_WR_ZERO VDD VSS / RSC_IHPSG13_AND2X2 +XB_I44 B_WCLK_B_L B_BM_N B_DO_WRITE_P VDD VSS / RSC_IHPSG13_NOR2X2 +XA_I44 A_WCLK_B_L A_BM_N A_DO_WRITE_P VDD VSS / RSC_IHPSG13_NOR2X2 +XB_I81 net041 B_PRE_N VDD VSS / RSC_IHPSG13_CINVX4_WN +XA_I81 net21 A_PRE_N VDD VSS / RSC_IHPSG13_CINVX4_WN +XB_BM_TIEH B_TIEH_O VDD VSS / RSC_IHPSG13_TIEH +XA_BM_TIEH A_TIEH_O VDD VSS / RSC_IHPSG13_TIEH +XA_I89 A_DCLK_B_L A_DCLK_B_R / RSC_IHPSG13_MET3RES +XA_I88 A_DCLK_L A_DCLK_R / RSC_IHPSG13_MET3RES +XA_I87 A_WCLK_L A_WCLK_R / RSC_IHPSG13_MET3RES +XA_I91 A_RCLK_B_L A_RCLK_B_R / RSC_IHPSG13_MET3RES +XB_I87 B_WCLK_L B_WCLK_R / RSC_IHPSG13_MET3RES +XB_I88 B_DCLK_L B_DCLK_R / RSC_IHPSG13_MET3RES +XB_I89 B_DCLK_B_L B_DCLK_B_R / RSC_IHPSG13_MET3RES +XB_I90 B_WCLK_B_L B_WCLK_B_R / RSC_IHPSG13_MET3RES +XB_R2 B_RCLK_L B_RCLK_R / RSC_IHPSG13_MET3RES +XB_I91 B_RCLK_B_L B_RCLK_B_R / RSC_IHPSG13_MET3RES +XA_R2 A_RCLK_L A_RCLK_R / RSC_IHPSG13_MET3RES +XA_I90 A_WCLK_B_L A_WCLK_B_R / RSC_IHPSG13_MET3RES +XAB_BLMUX A_BLC<3> A_BLC<2> A_BLC<1> A_BLC<0> A_BLC_SEL A_BLT<3> A_BLT<2> ++ A_BLT<1> A_BLT<0> A_BLT_SEL A_PRE_N A_ADDR_DEC<3> A_ADDR_DEC<2> ++ A_ADDR_DEC<1> A_ADDR_DEC<0> A_WR_ONE A_WR_ZERO B_BLC<3> B_BLC<2> B_BLC<1> ++ B_BLC<0> B_BLC_SEL B_BLT<3> B_BLT<2> B_BLT<1> B_BLT<0> B_BLT_SEL B_PRE_N ++ B_ADDR_DEC<3> B_ADDR_DEC<2> B_ADDR_DEC<1> B_ADDR_DEC<0> B_WR_ONE B_WR_ZERO ++ VDD VSS / RM_IHPSG13_256x8_c3_2P_BLDRV +XB_ISENSE B_SAE B_BLC_SEL B_BLT_SEL net039 net040 VDD VSS / ++ RSC_IHPSG13_DFPQD_MSAFFX2 +XA_ISENSE A_SAE A_BLC_SEL A_BLT_SEL net19 net20 VDD VSS / ++ RSC_IHPSG13_DFPQD_MSAFFX2 +XB_I78 B_RCLK_B_L B_SAE VDD VSS / RSC_IHPSG13_CBUFX2 +XA_I78 A_RCLK_B_L A_SAE VDD VSS / RSC_IHPSG13_CBUFX2 +XB_I83 B_BM_R B_BM_N VDD VSS / RSC_IHPSG13_INVX2 +XB_I49 B_DI_R B_DI_N VDD VSS / RSC_IHPSG13_INVX2 +XA_I83 A_BM_R A_BM_N VDD VSS / RSC_IHPSG13_INVX2 +XA_I49 A_DI_R A_DI_N VDD VSS / RSC_IHPSG13_INVX2 +XB_I51 net039 B_DR_O VDD VSS / RSC_IHPSG13_INVX4 +XA_I51 net19 A_DR_O VDD VSS / RSC_IHPSG13_INVX4 +XA_I69 A_DCLK_L A_DCLK_B_L VDD VSS / RSC_IHPSG13_CINVX2 +XA_I50 A_WCLK_L A_WCLK_B_L VDD VSS / RSC_IHPSG13_CINVX2 +XA_EBUF A_RCLK_L A_RCLK_B_L VDD VSS / RSC_IHPSG13_CINVX2 +XB_EBUF B_RCLK_L B_RCLK_B_L VDD VSS / RSC_IHPSG13_CINVX2 +XB_I50 B_WCLK_L B_WCLK_B_L VDD VSS / RSC_IHPSG13_CINVX2 +XB_I69 B_DCLK_L B_DCLK_B_L VDD VSS / RSC_IHPSG13_CINVX2 +.ENDS +.SUBCKT RM_IHPSG13_256x8_c3_2P_COLDRV13_FILL4C2 VDD VSS +XI0<2> VDD VSS / RSC_IHPSG13_FILLCAP4 +XI0<1> VDD VSS / RSC_IHPSG13_FILLCAP4 +.ENDS + + +.SUBCKT RM_IHPSG13_256x8_c3_2P_ROWDEC7 ADDR_N_I<6> ADDR_N_I<5> ADDR_N_I<4> ADDR_N_I<3> ++ ADDR_N_I<2> ADDR_N_I<1> ADDR_N_I<0> CS_I ECLK_I WL_O<127> WL_O<126> ++ WL_O<125> WL_O<124> WL_O<123> WL_O<122> WL_O<121> WL_O<120> WL_O<119> ++ WL_O<118> WL_O<117> WL_O<116> WL_O<115> WL_O<114> WL_O<113> WL_O<112> ++ WL_O<111> WL_O<110> WL_O<109> WL_O<108> WL_O<107> WL_O<106> WL_O<105> ++ WL_O<104> WL_O<103> WL_O<102> WL_O<101> WL_O<100> WL_O<99> WL_O<98> WL_O<97> ++ WL_O<96> WL_O<95> WL_O<94> WL_O<93> WL_O<92> WL_O<91> WL_O<90> WL_O<89> ++ WL_O<88> WL_O<87> WL_O<86> WL_O<85> WL_O<84> WL_O<83> WL_O<82> WL_O<81> ++ WL_O<80> WL_O<79> WL_O<78> WL_O<77> WL_O<76> WL_O<75> WL_O<74> WL_O<73> ++ WL_O<72> WL_O<71> WL_O<70> WL_O<69> WL_O<68> WL_O<67> WL_O<66> WL_O<65> ++ WL_O<64> WL_O<63> WL_O<62> WL_O<61> WL_O<60> WL_O<59> WL_O<58> WL_O<57> ++ WL_O<56> WL_O<55> WL_O<54> WL_O<53> WL_O<52> WL_O<51> WL_O<50> WL_O<49> ++ WL_O<48> WL_O<47> WL_O<46> WL_O<45> WL_O<44> WL_O<43> WL_O<42> WL_O<41> ++ WL_O<40> WL_O<39> WL_O<38> WL_O<37> WL_O<36> WL_O<35> WL_O<34> WL_O<33> ++ WL_O<32> WL_O<31> WL_O<30> WL_O<29> WL_O<28> WL_O<27> WL_O<26> WL_O<25> ++ WL_O<24> WL_O<23> WL_O<22> WL_O<21> WL_O<20> WL_O<19> WL_O<18> WL_O<17> ++ WL_O<16> WL_O<15> WL_O<14> WL_O<13> WL_O<12> WL_O<11> WL_O<10> WL_O<9> ++ WL_O<8> WL_O<7> WL_O<6> WL_O<5> WL_O<4> WL_O<3> WL_O<2> WL_O<1> WL_O<0> ++ VDD VSS +XSEL<7> ADDR_N_I<3> ADDR_N_I<2> ADDR_N_I<1> ADDR_N_I<0> CS00<7> ECLK_H<7> ++ ECLK_H<8> ECLK_B<7> ECLK_B<8> WL_O<127> WL_O<126> WL_O<125> WL_O<124> ++ WL_O<123> WL_O<122> WL_O<121> WL_O<120> WL_O<119> WL_O<118> WL_O<117> ++ WL_O<116> WL_O<115> WL_O<114> WL_O<113> WL_O<112> VDD VSS / ++ RM_IHPSG13_256x8_c3_2P_DEC04 +XSEL<6> ADDR_N_I<3> ADDR_N_I<2> ADDR_N_I<1> ADDR_N_I<0> CS00<6> ECLK_H<6> ++ ECLK_H<7> ECLK_B<6> ECLK_B<7> WL_O<111> WL_O<110> WL_O<109> WL_O<108> ++ WL_O<107> WL_O<106> WL_O<105> WL_O<104> WL_O<103> WL_O<102> WL_O<101> ++ WL_O<100> WL_O<99> WL_O<98> WL_O<97> WL_O<96> VDD VSS / ++ RM_IHPSG13_256x8_c3_2P_DEC04 +XSEL<5> ADDR_N_I<3> ADDR_N_I<2> ADDR_N_I<1> ADDR_N_I<0> CS00<5> ECLK_H<5> ++ ECLK_H<6> ECLK_B<5> ECLK_B<6> WL_O<95> WL_O<94> WL_O<93> WL_O<92> WL_O<91> ++ WL_O<90> WL_O<89> WL_O<88> WL_O<87> WL_O<86> WL_O<85> WL_O<84> WL_O<83> ++ WL_O<82> WL_O<81> WL_O<80> VDD VSS / RM_IHPSG13_256x8_c3_2P_DEC04 +XSEL<4> ADDR_N_I<3> ADDR_N_I<2> ADDR_N_I<1> ADDR_N_I<0> CS00<4> ECLK_H<4> ++ ECLK_H<5> ECLK_B<4> ECLK_B<5> WL_O<79> WL_O<78> WL_O<77> WL_O<76> WL_O<75> ++ WL_O<74> WL_O<73> WL_O<72> WL_O<71> WL_O<70> WL_O<69> WL_O<68> WL_O<67> ++ WL_O<66> WL_O<65> WL_O<64> VDD VSS / RM_IHPSG13_256x8_c3_2P_DEC04 +XSEL<3> ADDR_N_I<3> ADDR_N_I<2> ADDR_N_I<1> ADDR_N_I<0> CS00<3> ECLK_H<3> ++ ECLK_H<4> ECLK_B<3> ECLK_B<4> WL_O<63> WL_O<62> WL_O<61> WL_O<60> WL_O<59> ++ WL_O<58> WL_O<57> WL_O<56> WL_O<55> WL_O<54> WL_O<53> WL_O<52> WL_O<51> ++ WL_O<50> WL_O<49> WL_O<48> VDD VSS / RM_IHPSG13_256x8_c3_2P_DEC04 +XSEL<2> ADDR_N_I<3> ADDR_N_I<2> ADDR_N_I<1> ADDR_N_I<0> CS00<2> ECLK_H<2> ++ ECLK_H<3> ECLK_B<2> ECLK_B<3> WL_O<47> WL_O<46> WL_O<45> WL_O<44> WL_O<43> ++ WL_O<42> WL_O<41> WL_O<40> WL_O<39> WL_O<38> WL_O<37> WL_O<36> WL_O<35> ++ WL_O<34> WL_O<33> WL_O<32> VDD VSS / RM_IHPSG13_256x8_c3_2P_DEC04 +XSEL<1> ADDR_N_I<3> ADDR_N_I<2> ADDR_N_I<1> ADDR_N_I<0> CS00<1> ECLK_H<1> ++ ECLK_H<2> ECLK_B<1> ECLK_B<2> WL_O<31> WL_O<30> WL_O<29> WL_O<28> WL_O<27> ++ WL_O<26> WL_O<25> WL_O<24> WL_O<23> WL_O<22> WL_O<21> WL_O<20> WL_O<19> ++ WL_O<18> WL_O<17> WL_O<16> VDD VSS / RM_IHPSG13_256x8_c3_2P_DEC04 +XSEL<0> ADDR_N_I<3> ADDR_N_I<2> ADDR_N_I<1> ADDR_N_I<0> CS00<0> ECLK_I ++ ECLK_H<1> ECLK_B<0> ECLK_B<1> WL_O<15> WL_O<14> WL_O<13> WL_O<12> WL_O<11> ++ WL_O<10> WL_O<9> WL_O<8> WL_O<7> WL_O<6> WL_O<5> WL_O<4> WL_O<3> WL_O<2> ++ WL_O<1> WL_O<0> VDD VSS / RM_IHPSG13_256x8_c3_2P_DEC04 +XDEC11<1> ADDR_N_I<5> ADDR_N_I<4> CS04<1> CS00<7> VDD VSS / ++ RM_IHPSG13_256x8_c3_2P_DEC03 +XDEC11<0> ADDR_N_I<5> ADDR_N_I<4> CS04<0> CS00<3> VDD VSS / ++ RM_IHPSG13_256x8_c3_2P_DEC03 +XDEC01<2> ADDR_N_I<7> ADDR_N_I<6> CS_I CS04<1> VDD VSS / ++ RM_IHPSG13_256x8_c3_2P_DEC01 +XDEC01<1> ADDR_N_I<5> ADDR_N_I<4> CS04<1> CS00<5> VDD VSS / ++ RM_IHPSG13_256x8_c3_2P_DEC01 +XDEC01<0> ADDR_N_I<5> ADDR_N_I<4> CS04<0> CS00<1> VDD VSS / ++ RM_IHPSG13_256x8_c3_2P_DEC01 +XL2<66> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<65> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<64> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<63> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<62> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<61> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<60> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<59> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<58> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<57> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<56> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<55> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<54> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<53> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<52> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<51> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<50> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<49> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<48> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<47> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<46> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<45> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<44> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<43> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<42> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<41> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<40> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<39> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<38> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<37> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<36> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<35> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<34> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<33> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<32> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<31> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<30> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<29> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<28> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<27> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<26> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<25> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<24> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<23> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<22> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<21> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<20> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<19> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<18> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<17> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<16> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<15> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<14> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<13> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<12> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<11> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<10> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<9> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<8> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<7> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<6> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<5> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<4> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<3> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<2> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<1> VDD VSS / RSC_IHPSG13_FILLCAP8 +XDEC10<1> ADDR_N_I<5> ADDR_N_I<4> CS04<1> CS00<6> VDD VSS / ++ RM_IHPSG13_256x8_c3_2P_DEC02 +XDEC10<0> ADDR_N_I<5> ADDR_N_I<4> CS04<0> CS00<2> VDD VSS / ++ RM_IHPSG13_256x8_c3_2P_DEC02 +XDEC00<2> ADDR_N_I<7> ADDR_N_I<6> CS_I CS04<0> VDD VSS / ++ RM_IHPSG13_256x8_c3_2P_DEC00 +XDEC00<1> ADDR_N_I<5> ADDR_N_I<4> CS04<1> CS00<4> VDD VSS / ++ RM_IHPSG13_256x8_c3_2P_DEC00 +XDEC00<0> ADDR_N_I<5> ADDR_N_I<4> CS04<0> CS00<0> VDD VSS / ++ RM_IHPSG13_256x8_c3_2P_DEC00 +XI0 ADDR_N_I<7> VDD VSS / RSC_IHPSG13_TIEL +.ENDS +.SUBCKT RM_IHPSG13_256x8_c3_2P_ROWREG7 ACLK_N_I ADDR_I<6> ADDR_I<5> ADDR_I<4> ADDR_I<3> ++ ADDR_I<2> ADDR_I<1> ADDR_I<0> ADDR_N_O<6> ADDR_N_O<5> ADDR_N_O<4> ++ ADDR_N_O<3> ADDR_N_O<2> ADDR_N_O<1> ADDR_N_O<0> BIST_ADDR_I<6> ++ BIST_ADDR_I<5> BIST_ADDR_I<4> BIST_ADDR_I<3> BIST_ADDR_I<2> BIST_ADDR_I<1> ++ BIST_ADDR_I<0> BIST_EN_I VDD VSS +XINV<6> q_int<6> qn_int<6> VDD VSS / RSC_IHPSG13_CINVX2 +XINV<5> q_int<5> qn_int<5> VDD VSS / RSC_IHPSG13_CINVX2 +XINV<4> q_int<4> qn_int<4> VDD VSS / RSC_IHPSG13_CINVX2 +XINV<3> q_int<3> qn_int<3> VDD VSS / RSC_IHPSG13_CINVX2 +XINV<2> q_int<2> qn_int<2> VDD VSS / RSC_IHPSG13_CINVX2 +XINV<1> q_int<1> qn_int<1> VDD VSS / RSC_IHPSG13_CINVX2 +XINV<0> q_int<0> qn_int<0> VDD VSS / RSC_IHPSG13_CINVX2 +XDRV<6> qn_int<6> ADDR_N_O<6> VDD VSS / RSC_IHPSG13_CINVX8 +XDRV<5> qn_int<5> ADDR_N_O<5> VDD VSS / RSC_IHPSG13_CINVX8 +XDRV<4> qn_int<4> ADDR_N_O<4> VDD VSS / RSC_IHPSG13_CINVX8 +XDRV<3> qn_int<3> ADDR_N_O<3> VDD VSS / RSC_IHPSG13_CINVX8 +XDRV<2> qn_int<2> ADDR_N_O<2> VDD VSS / RSC_IHPSG13_CINVX8 +XDRV<1> qn_int<1> ADDR_N_O<1> VDD VSS / RSC_IHPSG13_CINVX8 +XDRV<0> qn_int<0> ADDR_N_O<0> VDD VSS / RSC_IHPSG13_CINVX8 +XDFF<6> BIST_EN_I BIST_ADDR_I<6> ACLK_N_I ADDR_I<6> q_int<6> net2<0> VDD ++ VSS / RSC_IHPSG13_DFNQMX2IX1 +XDFF<5> BIST_EN_I BIST_ADDR_I<5> ACLK_N_I ADDR_I<5> q_int<5> net2<1> VDD ++ VSS / RSC_IHPSG13_DFNQMX2IX1 +XDFF<4> BIST_EN_I BIST_ADDR_I<4> ACLK_N_I ADDR_I<4> q_int<4> net2<2> VDD ++ VSS / RSC_IHPSG13_DFNQMX2IX1 +XDFF<3> BIST_EN_I BIST_ADDR_I<3> ACLK_N_I ADDR_I<3> q_int<3> net2<3> VDD ++ VSS / RSC_IHPSG13_DFNQMX2IX1 +XDFF<2> BIST_EN_I BIST_ADDR_I<2> ACLK_N_I ADDR_I<2> q_int<2> net2<4> VDD ++ VSS / RSC_IHPSG13_DFNQMX2IX1 +XDFF<1> BIST_EN_I BIST_ADDR_I<1> ACLK_N_I ADDR_I<1> q_int<1> net2<5> VDD ++ VSS / RSC_IHPSG13_DFNQMX2IX1 +XDFF<0> BIST_EN_I BIST_ADDR_I<0> ACLK_N_I ADDR_I<0> q_int<0> net2<6> VDD ++ VSS / RSC_IHPSG13_DFNQMX2IX1 +XI11<7> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI11<6> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI11<5> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI11<4> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI11<3> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI11<2> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI11<1> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI11<0> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI12<1> VDD VSS / RSC_IHPSG13_FILLCAP4 +XI12<0> VDD VSS / RSC_IHPSG13_FILLCAP4 +.ENDS + +.SUBCKT RM_IHPSG13_256x8_c3_2P_ROWDEC4 ADDR_N_I<3> ADDR_N_I<2> ADDR_N_I<1> ADDR_N_I<0> ++ CS_I ECLK_I WL_O<15> WL_O<14> WL_O<13> WL_O<12> WL_O<11> WL_O<10> WL_O<9> ++ WL_O<8> WL_O<7> WL_O<6> WL_O<5> WL_O<4> WL_O<3> WL_O<2> WL_O<1> WL_O<0> ++ VDD VSS +XL2<12> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<11> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<10> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<9> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<8> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<7> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<6> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<5> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<4> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<3> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<2> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<1> VDD VSS / RSC_IHPSG13_FILLCAP8 +XSEL ADDR_N_I<3> ADDR_N_I<2> ADDR_N_I<1> ADDR_N_I<0> CS_I ECLK_I ECLK_H<1> ++ ECLK_B<0> ECLK_B<1> WL_O<15> WL_O<14> WL_O<13> WL_O<12> WL_O<11> WL_O<10> ++ WL_O<9> WL_O<8> WL_O<7> WL_O<6> WL_O<5> WL_O<4> WL_O<3> WL_O<2> WL_O<1> ++ WL_O<0> VDD VSS / RM_IHPSG13_256x8_c3_2P_DEC04 +.ENDS +.SUBCKT RM_IHPSG13_256x8_c3_2P_ROWREG4 ACLK_N_I ADDR_I<3> ADDR_I<2> ADDR_I<1> ADDR_I<0> ++ ADDR_N_O<3> ADDR_N_O<2> ADDR_N_O<1> ADDR_N_O<0> BIST_ADDR_I<3> ++ BIST_ADDR_I<2> BIST_ADDR_I<1> BIST_ADDR_I<0> BIST_EN_I VDD VSS +XINV<3> q_int<3> qn_int<3> VDD VSS / RSC_IHPSG13_CINVX2 +XINV<2> q_int<2> qn_int<2> VDD VSS / RSC_IHPSG13_CINVX2 +XINV<1> q_int<1> qn_int<1> VDD VSS / RSC_IHPSG13_CINVX2 +XINV<0> q_int<0> qn_int<0> VDD VSS / RSC_IHPSG13_CINVX2 +XDRV<3> qn_int<3> ADDR_N_O<3> VDD VSS / RSC_IHPSG13_CINVX8 +XDRV<2> qn_int<2> ADDR_N_O<2> VDD VSS / RSC_IHPSG13_CINVX8 +XDRV<1> qn_int<1> ADDR_N_O<1> VDD VSS / RSC_IHPSG13_CINVX8 +XDRV<0> qn_int<0> ADDR_N_O<0> VDD VSS / RSC_IHPSG13_CINVX8 +XDFF<3> BIST_EN_I BIST_ADDR_I<3> ACLK_N_I ADDR_I<3> q_int<3> net7<0> VDD ++ VSS / RSC_IHPSG13_DFNQMX2IX1 +XDFF<2> BIST_EN_I BIST_ADDR_I<2> ACLK_N_I ADDR_I<2> q_int<2> net7<1> VDD ++ VSS / RSC_IHPSG13_DFNQMX2IX1 +XDFF<1> BIST_EN_I BIST_ADDR_I<1> ACLK_N_I ADDR_I<1> q_int<1> net7<2> VDD ++ VSS / RSC_IHPSG13_DFNQMX2IX1 +XDFF<0> BIST_EN_I BIST_ADDR_I<0> ACLK_N_I ADDR_I<0> q_int<0> net7<3> VDD ++ VSS / RSC_IHPSG13_DFNQMX2IX1 +XI11<20> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI11<19> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI11<18> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI11<17> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI11<16> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI11<15> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI11<14> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI11<13> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI11<12> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI11<11> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI11<10> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI11<9> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI11<8> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI11<7> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI11<6> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI11<5> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI11<4> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI11<3> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI11<2> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI11<1> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI12<4> VDD VSS / RSC_IHPSG13_FILLCAP4 +XI12<3> VDD VSS / RSC_IHPSG13_FILLCAP4 +XI12<2> VDD VSS / RSC_IHPSG13_FILLCAP4 +XI12<1> VDD VSS / RSC_IHPSG13_FILLCAP4 +XI12<0> VDD VSS / RSC_IHPSG13_FILLCAP4 +.ENDS + + +.SUBCKT RM_IHPSG13_256x8_c3_1P_BITKIT_TAP BLC BLT NW PW VDD VSS +.ENDS +.SUBCKT RM_IHPSG13_256x8_c3_1P_BITKIT_16x2_TAP A_BLC<1> A_BLC<0> A_BLT<1> A_BLT<0> ++ VDD_CORE VSS +XITAP<1> A_BLC<1> A_BLT<1> VDD_CORE VSS VDD_CORE VSS ++ / RM_IHPSG13_256x8_c3_1P_BITKIT_TAP +XITAP<0> A_BLC<0> A_BLT<0> VDD_CORE VSS VDD_CORE VSS ++ / RM_IHPSG13_256x8_c3_1P_BITKIT_TAP +XIEDGEBP_COL1<1> BLC<1> BLT<1> VDD_CORE VSS VDD_CORE ++ VSS / RM_IHPSG13_256x8_c3_1P_BITKIT_EDGE_TB +XIEDGEBP_COL1<0> BLC<1> BLT<1> VDD_CORE VSS VDD_CORE ++ VSS / RM_IHPSG13_256x8_c3_1P_BITKIT_EDGE_TB +XIEDGEBP_COL2<1> BLC<0> BLT<0> VDD_CORE VSS VDD_CORE ++ VSS / RM_IHPSG13_256x8_c3_1P_BITKIT_EDGE_TB +XIEDGEBP_COL2<0> BLC<0> BLT<0> VDD_CORE VSS VDD_CORE ++ VSS / RM_IHPSG13_256x8_c3_1P_BITKIT_EDGE_TB +.ENDS +.SUBCKT RM_IHPSG13_256x8_c3_1P_BITKIT_16x2_TAP_LR VDD_CORE VSS +XCORNER<1> VDD_CORE VSS VDD_CORE VSS / ++ RM_IHPSG13_256x8_c3_1P_BITKIT_CORNER +XCORNER<0> VDD_CORE VSS VDD_CORE VSS / ++ RM_IHPSG13_256x8_c3_1P_BITKIT_CORNER +XTAP_BORDER VDD_CORE VSS VDD_CORE VSS / ++ RM_IHPSG13_256x8_c3_1P_BITKIT_TAP_LR +.ENDS +.SUBCKT RM_IHPSG13_256x8_c3_1P_DEC03 ADDR<1> ADDR<0> CS CS_OUT VDD VSS +XDECINV net1 CS_OUT VDD VSS / RSC_IHPSG13_INVX4 +XI0 VDD VSS / RSC_IHPSG13_FILLCAP4 +XDEC ADDR<1> ADDR<0> CS net1 VDD VSS / RSC_IHPSG13_NAND3X2 +.ENDS +.SUBCKT RM_IHPSG13_256x8_c3_1P_DEC02 ADDR<1> ADDR<0> CS CS_OUT VDD VSS +XDECINV net1 CS_OUT VDD VSS / RSC_IHPSG13_INVX4 +XDEC ADDR<1> NADDR<0> CS net1 VDD VSS / RSC_IHPSG13_NAND3X2 +XI2 VDD VSS / RSC_IHPSG13_FILLCAP4 +XADDRINV ADDR<0> NADDR<0> VDD VSS / RSC_IHPSG13_INVX2 +.ENDS +.SUBCKT RM_IHPSG13_256x8_c3_1P_ROWDEC8 ADDR_N_I<7> ADDR_N_I<6> ADDR_N_I<5> ADDR_N_I<4> ++ ADDR_N_I<3> ADDR_N_I<2> ADDR_N_I<1> ADDR_N_I<0> CS_I ECLK_I WL_O<255> ++ WL_O<254> WL_O<253> WL_O<252> WL_O<251> WL_O<250> WL_O<249> WL_O<248> ++ WL_O<247> WL_O<246> WL_O<245> WL_O<244> WL_O<243> WL_O<242> WL_O<241> ++ WL_O<240> WL_O<239> WL_O<238> WL_O<237> WL_O<236> WL_O<235> WL_O<234> ++ WL_O<233> WL_O<232> WL_O<231> WL_O<230> WL_O<229> WL_O<228> WL_O<227> ++ WL_O<226> WL_O<225> WL_O<224> WL_O<223> WL_O<222> WL_O<221> WL_O<220> ++ WL_O<219> WL_O<218> WL_O<217> WL_O<216> WL_O<215> WL_O<214> WL_O<213> ++ WL_O<212> WL_O<211> WL_O<210> WL_O<209> WL_O<208> WL_O<207> WL_O<206> ++ WL_O<205> WL_O<204> WL_O<203> WL_O<202> WL_O<201> WL_O<200> WL_O<199> ++ WL_O<198> WL_O<197> WL_O<196> WL_O<195> WL_O<194> WL_O<193> WL_O<192> ++ WL_O<191> WL_O<190> WL_O<189> WL_O<188> WL_O<187> WL_O<186> WL_O<185> ++ WL_O<184> WL_O<183> WL_O<182> WL_O<181> WL_O<180> WL_O<179> WL_O<178> ++ WL_O<177> WL_O<176> WL_O<175> WL_O<174> WL_O<173> WL_O<172> WL_O<171> ++ WL_O<170> WL_O<169> WL_O<168> WL_O<167> WL_O<166> WL_O<165> WL_O<164> ++ WL_O<163> WL_O<162> WL_O<161> WL_O<160> WL_O<159> WL_O<158> WL_O<157> ++ WL_O<156> WL_O<155> WL_O<154> WL_O<153> WL_O<152> WL_O<151> WL_O<150> ++ WL_O<149> WL_O<148> WL_O<147> WL_O<146> WL_O<145> WL_O<144> WL_O<143> ++ WL_O<142> WL_O<141> WL_O<140> WL_O<139> WL_O<138> WL_O<137> WL_O<136> ++ WL_O<135> WL_O<134> WL_O<133> WL_O<132> WL_O<131> WL_O<130> WL_O<129> ++ WL_O<128> WL_O<127> WL_O<126> WL_O<125> WL_O<124> WL_O<123> WL_O<122> ++ WL_O<121> WL_O<120> WL_O<119> WL_O<118> WL_O<117> WL_O<116> WL_O<115> ++ WL_O<114> WL_O<113> WL_O<112> WL_O<111> WL_O<110> WL_O<109> WL_O<108> ++ WL_O<107> WL_O<106> WL_O<105> WL_O<104> WL_O<103> WL_O<102> WL_O<101> ++ WL_O<100> WL_O<99> WL_O<98> WL_O<97> WL_O<96> WL_O<95> WL_O<94> WL_O<93> ++ WL_O<92> WL_O<91> WL_O<90> WL_O<89> WL_O<88> WL_O<87> WL_O<86> WL_O<85> ++ WL_O<84> WL_O<83> WL_O<82> WL_O<81> WL_O<80> WL_O<79> WL_O<78> WL_O<77> ++ WL_O<76> WL_O<75> WL_O<74> WL_O<73> WL_O<72> WL_O<71> WL_O<70> WL_O<69> ++ WL_O<68> WL_O<67> WL_O<66> WL_O<65> WL_O<64> WL_O<63> WL_O<62> WL_O<61> ++ WL_O<60> WL_O<59> WL_O<58> WL_O<57> WL_O<56> WL_O<55> WL_O<54> WL_O<53> ++ WL_O<52> WL_O<51> WL_O<50> WL_O<49> WL_O<48> WL_O<47> WL_O<46> WL_O<45> ++ WL_O<44> WL_O<43> WL_O<42> WL_O<41> WL_O<40> WL_O<39> WL_O<38> WL_O<37> ++ WL_O<36> WL_O<35> WL_O<34> WL_O<33> WL_O<32> WL_O<31> WL_O<30> WL_O<29> ++ WL_O<28> WL_O<27> WL_O<26> WL_O<25> WL_O<24> WL_O<23> WL_O<22> WL_O<21> ++ WL_O<20> WL_O<19> WL_O<18> WL_O<17> WL_O<16> WL_O<15> WL_O<14> WL_O<13> ++ WL_O<12> WL_O<11> WL_O<10> WL_O<9> WL_O<8> WL_O<7> WL_O<6> WL_O<5> WL_O<4> ++ WL_O<3> WL_O<2> WL_O<1> WL_O<0> VDD VSS +XDEC11<4> ADDR_N_I<7> ADDR_N_I<6> CS_I CS04<3> VDD VSS / ++ RM_IHPSG13_256x8_c3_1P_DEC03 +XDEC11<3> ADDR_N_I<5> ADDR_N_I<4> CS04<3> CS00<15> VDD VSS / ++ RM_IHPSG13_256x8_c3_1P_DEC03 +XDEC11<2> ADDR_N_I<5> ADDR_N_I<4> CS04<2> CS00<11> VDD VSS / ++ RM_IHPSG13_256x8_c3_1P_DEC03 +XDEC11<1> ADDR_N_I<5> ADDR_N_I<4> CS04<1> CS00<7> VDD VSS / ++ RM_IHPSG13_256x8_c3_1P_DEC03 +XDEC11<0> ADDR_N_I<5> ADDR_N_I<4> CS04<0> CS00<3> VDD VSS / ++ RM_IHPSG13_256x8_c3_1P_DEC03 +XL2<88> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<87> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<86> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<85> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<84> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<83> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<82> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<81> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<80> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<79> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<78> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<77> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<76> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<75> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<74> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<73> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<72> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<71> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<70> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<69> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<68> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<67> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<66> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<65> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<64> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<63> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<62> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<61> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<60> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<59> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<58> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<57> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<56> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<55> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<54> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<53> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<52> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<51> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<50> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<49> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<48> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<47> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<46> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<45> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<44> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<43> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<42> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<41> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<40> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<39> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<38> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<37> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<36> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<35> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<34> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<33> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<32> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<31> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<30> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<29> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<28> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<27> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<26> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<25> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<24> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<23> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<22> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<21> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<20> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<19> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<18> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<17> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<16> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<15> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<14> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<13> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<12> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<11> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<10> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<9> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<8> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<7> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<6> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<5> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<4> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<3> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<2> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<1> VDD VSS / RSC_IHPSG13_FILLCAP8 +XDEC10<4> ADDR_N_I<7> ADDR_N_I<6> CS_I CS04<2> VDD VSS / ++ RM_IHPSG13_256x8_c3_1P_DEC02 +XDEC10<3> ADDR_N_I<5> ADDR_N_I<4> CS04<3> CS00<14> VDD VSS / ++ RM_IHPSG13_256x8_c3_1P_DEC02 +XDEC10<2> ADDR_N_I<5> ADDR_N_I<4> CS04<2> CS00<10> VDD VSS / ++ RM_IHPSG13_256x8_c3_1P_DEC02 +XDEC10<1> ADDR_N_I<5> ADDR_N_I<4> CS04<1> CS00<6> VDD VSS / ++ RM_IHPSG13_256x8_c3_1P_DEC02 +XDEC10<0> ADDR_N_I<5> ADDR_N_I<4> CS04<0> CS00<2> VDD VSS / ++ RM_IHPSG13_256x8_c3_1P_DEC02 +XDEC00<4> ADDR_N_I<7> ADDR_N_I<6> CS_I CS04<0> VDD VSS / ++ RM_IHPSG13_256x8_c3_1P_DEC00 +XDEC00<3> ADDR_N_I<5> ADDR_N_I<4> CS04<3> CS00<12> VDD VSS / ++ RM_IHPSG13_256x8_c3_1P_DEC00 +XDEC00<2> ADDR_N_I<5> ADDR_N_I<4> CS04<2> CS00<8> VDD VSS / ++ RM_IHPSG13_256x8_c3_1P_DEC00 +XDEC00<1> ADDR_N_I<5> ADDR_N_I<4> CS04<1> CS00<4> VDD VSS / ++ RM_IHPSG13_256x8_c3_1P_DEC00 +XDEC00<0> ADDR_N_I<5> ADDR_N_I<4> CS04<0> CS00<0> VDD VSS / ++ RM_IHPSG13_256x8_c3_1P_DEC00 +XSEL<15> ADDR_N_I<3> ADDR_N_I<2> ADDR_N_I<1> ADDR_N_I<0> CS00<15> ECLK_H<15> ++ ECLK_H<16> ECLK_B<15> ECLK_B<16> WL_O<255> WL_O<254> WL_O<253> WL_O<252> ++ WL_O<251> WL_O<250> WL_O<249> WL_O<248> WL_O<247> WL_O<246> WL_O<245> ++ WL_O<244> WL_O<243> WL_O<242> WL_O<241> WL_O<240> VDD VSS / ++ RM_IHPSG13_256x8_c3_1P_DEC04 +XSEL<14> ADDR_N_I<3> ADDR_N_I<2> ADDR_N_I<1> ADDR_N_I<0> CS00<14> ECLK_H<14> ++ ECLK_H<15> ECLK_B<14> ECLK_B<15> WL_O<239> WL_O<238> WL_O<237> WL_O<236> ++ WL_O<235> WL_O<234> WL_O<233> WL_O<232> WL_O<231> WL_O<230> WL_O<229> ++ WL_O<228> WL_O<227> WL_O<226> WL_O<225> WL_O<224> VDD VSS / ++ RM_IHPSG13_256x8_c3_1P_DEC04 +XSEL<13> ADDR_N_I<3> ADDR_N_I<2> ADDR_N_I<1> ADDR_N_I<0> CS00<13> ECLK_H<13> ++ ECLK_H<14> ECLK_B<13> ECLK_B<14> WL_O<223> WL_O<222> WL_O<221> WL_O<220> ++ WL_O<219> WL_O<218> WL_O<217> WL_O<216> WL_O<215> WL_O<214> WL_O<213> ++ WL_O<212> WL_O<211> WL_O<210> WL_O<209> WL_O<208> VDD VSS / ++ RM_IHPSG13_256x8_c3_1P_DEC04 +XSEL<12> ADDR_N_I<3> ADDR_N_I<2> ADDR_N_I<1> ADDR_N_I<0> CS00<12> ECLK_H<12> ++ ECLK_H<13> ECLK_B<12> ECLK_B<13> WL_O<207> WL_O<206> WL_O<205> WL_O<204> ++ WL_O<203> WL_O<202> WL_O<201> WL_O<200> WL_O<199> WL_O<198> WL_O<197> ++ WL_O<196> WL_O<195> WL_O<194> WL_O<193> WL_O<192> VDD VSS / ++ RM_IHPSG13_256x8_c3_1P_DEC04 +XSEL<11> ADDR_N_I<3> ADDR_N_I<2> ADDR_N_I<1> ADDR_N_I<0> CS00<11> ECLK_H<11> ++ ECLK_H<12> ECLK_B<11> ECLK_B<12> WL_O<191> WL_O<190> WL_O<189> WL_O<188> ++ WL_O<187> WL_O<186> WL_O<185> WL_O<184> WL_O<183> WL_O<182> WL_O<181> ++ WL_O<180> WL_O<179> WL_O<178> WL_O<177> WL_O<176> VDD VSS / ++ RM_IHPSG13_256x8_c3_1P_DEC04 +XSEL<10> ADDR_N_I<3> ADDR_N_I<2> ADDR_N_I<1> ADDR_N_I<0> CS00<10> ECLK_H<10> ++ ECLK_H<11> ECLK_B<10> ECLK_B<11> WL_O<175> WL_O<174> WL_O<173> WL_O<172> ++ WL_O<171> WL_O<170> WL_O<169> WL_O<168> WL_O<167> WL_O<166> WL_O<165> ++ WL_O<164> WL_O<163> WL_O<162> WL_O<161> WL_O<160> VDD VSS / ++ RM_IHPSG13_256x8_c3_1P_DEC04 +XSEL<9> ADDR_N_I<3> ADDR_N_I<2> ADDR_N_I<1> ADDR_N_I<0> CS00<9> ECLK_H<9> ++ ECLK_H<10> ECLK_B<9> ECLK_B<10> WL_O<159> WL_O<158> WL_O<157> WL_O<156> ++ WL_O<155> WL_O<154> WL_O<153> WL_O<152> WL_O<151> WL_O<150> WL_O<149> ++ WL_O<148> WL_O<147> WL_O<146> WL_O<145> WL_O<144> VDD VSS / ++ RM_IHPSG13_256x8_c3_1P_DEC04 +XSEL<8> ADDR_N_I<3> ADDR_N_I<2> ADDR_N_I<1> ADDR_N_I<0> CS00<8> ECLK_H<8> ++ ECLK_H<9> ECLK_B<8> ECLK_B<9> WL_O<143> WL_O<142> WL_O<141> WL_O<140> ++ WL_O<139> WL_O<138> WL_O<137> WL_O<136> WL_O<135> WL_O<134> WL_O<133> ++ WL_O<132> WL_O<131> WL_O<130> WL_O<129> WL_O<128> VDD VSS / ++ RM_IHPSG13_256x8_c3_1P_DEC04 +XSEL<7> ADDR_N_I<3> ADDR_N_I<2> ADDR_N_I<1> ADDR_N_I<0> CS00<7> ECLK_H<7> ++ ECLK_H<8> ECLK_B<7> ECLK_B<8> WL_O<127> WL_O<126> WL_O<125> WL_O<124> ++ WL_O<123> WL_O<122> WL_O<121> WL_O<120> WL_O<119> WL_O<118> WL_O<117> ++ WL_O<116> WL_O<115> WL_O<114> WL_O<113> WL_O<112> VDD VSS / ++ RM_IHPSG13_256x8_c3_1P_DEC04 +XSEL<6> ADDR_N_I<3> ADDR_N_I<2> ADDR_N_I<1> ADDR_N_I<0> CS00<6> ECLK_H<6> ++ ECLK_H<7> ECLK_B<6> ECLK_B<7> WL_O<111> WL_O<110> WL_O<109> WL_O<108> ++ WL_O<107> WL_O<106> WL_O<105> WL_O<104> WL_O<103> WL_O<102> WL_O<101> ++ WL_O<100> WL_O<99> WL_O<98> WL_O<97> WL_O<96> VDD VSS / ++ RM_IHPSG13_256x8_c3_1P_DEC04 +XSEL<5> ADDR_N_I<3> ADDR_N_I<2> ADDR_N_I<1> ADDR_N_I<0> CS00<5> ECLK_H<5> ++ ECLK_H<6> ECLK_B<5> ECLK_B<6> WL_O<95> WL_O<94> WL_O<93> WL_O<92> WL_O<91> ++ WL_O<90> WL_O<89> WL_O<88> WL_O<87> WL_O<86> WL_O<85> WL_O<84> WL_O<83> ++ WL_O<82> WL_O<81> WL_O<80> VDD VSS / RM_IHPSG13_256x8_c3_1P_DEC04 +XSEL<4> ADDR_N_I<3> ADDR_N_I<2> ADDR_N_I<1> ADDR_N_I<0> CS00<4> ECLK_H<4> ++ ECLK_H<5> ECLK_B<4> ECLK_B<5> WL_O<79> WL_O<78> WL_O<77> WL_O<76> WL_O<75> ++ WL_O<74> WL_O<73> WL_O<72> WL_O<71> WL_O<70> WL_O<69> WL_O<68> WL_O<67> ++ WL_O<66> WL_O<65> WL_O<64> VDD VSS / RM_IHPSG13_256x8_c3_1P_DEC04 +XSEL<3> ADDR_N_I<3> ADDR_N_I<2> ADDR_N_I<1> ADDR_N_I<0> CS00<3> ECLK_H<3> ++ ECLK_H<4> ECLK_B<3> ECLK_B<4> WL_O<63> WL_O<62> WL_O<61> WL_O<60> WL_O<59> ++ WL_O<58> WL_O<57> WL_O<56> WL_O<55> WL_O<54> WL_O<53> WL_O<52> WL_O<51> ++ WL_O<50> WL_O<49> WL_O<48> VDD VSS / RM_IHPSG13_256x8_c3_1P_DEC04 +XSEL<2> ADDR_N_I<3> ADDR_N_I<2> ADDR_N_I<1> ADDR_N_I<0> CS00<2> ECLK_H<2> ++ ECLK_H<3> ECLK_B<2> ECLK_B<3> WL_O<47> WL_O<46> WL_O<45> WL_O<44> WL_O<43> ++ WL_O<42> WL_O<41> WL_O<40> WL_O<39> WL_O<38> WL_O<37> WL_O<36> WL_O<35> ++ WL_O<34> WL_O<33> WL_O<32> VDD VSS / RM_IHPSG13_256x8_c3_1P_DEC04 +XSEL<1> ADDR_N_I<3> ADDR_N_I<2> ADDR_N_I<1> ADDR_N_I<0> CS00<1> ECLK_H<1> ++ ECLK_H<2> ECLK_B<1> ECLK_B<2> WL_O<31> WL_O<30> WL_O<29> WL_O<28> WL_O<27> ++ WL_O<26> WL_O<25> WL_O<24> WL_O<23> WL_O<22> WL_O<21> WL_O<20> WL_O<19> ++ WL_O<18> WL_O<17> WL_O<16> VDD VSS / RM_IHPSG13_256x8_c3_1P_DEC04 +XSEL<0> ADDR_N_I<3> ADDR_N_I<2> ADDR_N_I<1> ADDR_N_I<0> CS00<0> ECLK_I ++ ECLK_H<1> ECLK_B<0> ECLK_B<1> WL_O<15> WL_O<14> WL_O<13> WL_O<12> WL_O<11> ++ WL_O<10> WL_O<9> WL_O<8> WL_O<7> WL_O<6> WL_O<5> WL_O<4> WL_O<3> WL_O<2> ++ WL_O<1> WL_O<0> VDD VSS / RM_IHPSG13_256x8_c3_1P_DEC04 +XDEC01<4> ADDR_N_I<7> ADDR_N_I<6> CS_I CS04<1> VDD VSS / ++ RM_IHPSG13_256x8_c3_1P_DEC01 +XDEC01<3> ADDR_N_I<5> ADDR_N_I<4> CS04<3> CS00<13> VDD VSS / ++ RM_IHPSG13_256x8_c3_1P_DEC01 +XDEC01<2> ADDR_N_I<5> ADDR_N_I<4> CS04<2> CS00<9> VDD VSS / ++ RM_IHPSG13_256x8_c3_1P_DEC01 +XDEC01<1> ADDR_N_I<5> ADDR_N_I<4> CS04<1> CS00<5> VDD VSS / ++ RM_IHPSG13_256x8_c3_1P_DEC01 +XDEC01<0> ADDR_N_I<5> ADDR_N_I<4> CS04<0> CS00<1> VDD VSS / ++ RM_IHPSG13_256x8_c3_1P_DEC01 +.ENDS +.SUBCKT RM_IHPSG13_256x8_c3_1P_ROWREG8 ACLK_N_I ADDR_I<7> ADDR_I<6> ADDR_I<5> ADDR_I<4> ++ ADDR_I<3> ADDR_I<2> ADDR_I<1> ADDR_I<0> ADDR_N_O<7> ADDR_N_O<6> ADDR_N_O<5> ++ ADDR_N_O<4> ADDR_N_O<3> ADDR_N_O<2> ADDR_N_O<1> ADDR_N_O<0> BIST_ADDR_I<7> ++ BIST_ADDR_I<6> BIST_ADDR_I<5> BIST_ADDR_I<4> BIST_ADDR_I<3> BIST_ADDR_I<2> ++ BIST_ADDR_I<1> BIST_ADDR_I<0> BIST_EN_I VDD VSS +XINV<7> q_int<7> qn_int<7> VDD VSS / RSC_IHPSG13_CINVX2 +XINV<6> q_int<6> qn_int<6> VDD VSS / RSC_IHPSG13_CINVX2 +XINV<5> q_int<5> qn_int<5> VDD VSS / RSC_IHPSG13_CINVX2 +XINV<4> q_int<4> qn_int<4> VDD VSS / RSC_IHPSG13_CINVX2 +XINV<3> q_int<3> qn_int<3> VDD VSS / RSC_IHPSG13_CINVX2 +XINV<2> q_int<2> qn_int<2> VDD VSS / RSC_IHPSG13_CINVX2 +XINV<1> q_int<1> qn_int<1> VDD VSS / RSC_IHPSG13_CINVX2 +XINV<0> q_int<0> qn_int<0> VDD VSS / RSC_IHPSG13_CINVX2 +XDRV<7> qn_int<7> ADDR_N_O<7> VDD VSS / RSC_IHPSG13_CINVX8 +XDRV<6> qn_int<6> ADDR_N_O<6> VDD VSS / RSC_IHPSG13_CINVX8 +XDRV<5> qn_int<5> ADDR_N_O<5> VDD VSS / RSC_IHPSG13_CINVX8 +XDRV<4> qn_int<4> ADDR_N_O<4> VDD VSS / RSC_IHPSG13_CINVX8 +XDRV<3> qn_int<3> ADDR_N_O<3> VDD VSS / RSC_IHPSG13_CINVX8 +XDRV<2> qn_int<2> ADDR_N_O<2> VDD VSS / RSC_IHPSG13_CINVX8 +XDRV<1> qn_int<1> ADDR_N_O<1> VDD VSS / RSC_IHPSG13_CINVX8 +XDRV<0> qn_int<0> ADDR_N_O<0> VDD VSS / RSC_IHPSG13_CINVX8 +XDFF<7> BIST_EN_I BIST_ADDR_I<7> ACLK_N_I ADDR_I<7> q_int<7> net2<0> VDD ++ VSS / RSC_IHPSG13_DFNQMX2IX1 +XDFF<6> BIST_EN_I BIST_ADDR_I<6> ACLK_N_I ADDR_I<6> q_int<6> net2<1> VDD ++ VSS / RSC_IHPSG13_DFNQMX2IX1 +XDFF<5> BIST_EN_I BIST_ADDR_I<5> ACLK_N_I ADDR_I<5> q_int<5> net2<2> VDD ++ VSS / RSC_IHPSG13_DFNQMX2IX1 +XDFF<4> BIST_EN_I BIST_ADDR_I<4> ACLK_N_I ADDR_I<4> q_int<4> net2<3> VDD ++ VSS / RSC_IHPSG13_DFNQMX2IX1 +XDFF<3> BIST_EN_I BIST_ADDR_I<3> ACLK_N_I ADDR_I<3> q_int<3> net2<4> VDD ++ VSS / RSC_IHPSG13_DFNQMX2IX1 +XDFF<2> BIST_EN_I BIST_ADDR_I<2> ACLK_N_I ADDR_I<2> q_int<2> net2<5> VDD ++ VSS / RSC_IHPSG13_DFNQMX2IX1 +XDFF<1> BIST_EN_I BIST_ADDR_I<1> ACLK_N_I ADDR_I<1> q_int<1> net2<6> VDD ++ VSS / RSC_IHPSG13_DFNQMX2IX1 +XDFF<0> BIST_EN_I BIST_ADDR_I<0> ACLK_N_I ADDR_I<0> q_int<0> net2<7> VDD ++ VSS / RSC_IHPSG13_DFNQMX2IX1 +XI11<4> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI11<3> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI11<2> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI11<1> VDD VSS / RSC_IHPSG13_FILLCAP8 +.ENDS + +.SUBCKT RM_IHPSG13_256x8_c3_1P_ROWDEC9 ADDR_N_I<8> ADDR_N_I<7> ADDR_N_I<6> ADDR_N_I<5> ++ ADDR_N_I<4> ADDR_N_I<3> ADDR_N_I<2> ADDR_N_I<1> ADDR_N_I<0> CS_I ECLK_I ++ WL_O<511> WL_O<510> WL_O<509> WL_O<508> WL_O<507> WL_O<506> WL_O<505> ++ WL_O<504> WL_O<503> WL_O<502> WL_O<501> WL_O<500> WL_O<499> WL_O<498> ++ WL_O<497> WL_O<496> WL_O<495> WL_O<494> WL_O<493> WL_O<492> WL_O<491> ++ WL_O<490> WL_O<489> WL_O<488> WL_O<487> WL_O<486> WL_O<485> WL_O<484> ++ WL_O<483> WL_O<482> WL_O<481> WL_O<480> WL_O<479> WL_O<478> WL_O<477> ++ WL_O<476> WL_O<475> WL_O<474> WL_O<473> WL_O<472> WL_O<471> WL_O<470> ++ WL_O<469> WL_O<468> WL_O<467> WL_O<466> WL_O<465> WL_O<464> WL_O<463> ++ WL_O<462> WL_O<461> WL_O<460> WL_O<459> WL_O<458> WL_O<457> WL_O<456> ++ WL_O<455> WL_O<454> WL_O<453> WL_O<452> WL_O<451> WL_O<450> WL_O<449> ++ WL_O<448> WL_O<447> WL_O<446> WL_O<445> WL_O<444> WL_O<443> WL_O<442> ++ WL_O<441> WL_O<440> WL_O<439> WL_O<438> WL_O<437> WL_O<436> WL_O<435> ++ WL_O<434> WL_O<433> WL_O<432> WL_O<431> WL_O<430> WL_O<429> WL_O<428> ++ WL_O<427> WL_O<426> WL_O<425> WL_O<424> WL_O<423> WL_O<422> WL_O<421> ++ WL_O<420> WL_O<419> WL_O<418> WL_O<417> WL_O<416> WL_O<415> WL_O<414> ++ WL_O<413> WL_O<412> WL_O<411> WL_O<410> WL_O<409> WL_O<408> WL_O<407> ++ WL_O<406> WL_O<405> WL_O<404> WL_O<403> WL_O<402> WL_O<401> WL_O<400> ++ WL_O<399> WL_O<398> WL_O<397> WL_O<396> WL_O<395> WL_O<394> WL_O<393> ++ WL_O<392> WL_O<391> WL_O<390> WL_O<389> WL_O<388> WL_O<387> WL_O<386> ++ WL_O<385> WL_O<384> WL_O<383> WL_O<382> WL_O<381> WL_O<380> WL_O<379> ++ WL_O<378> WL_O<377> WL_O<376> WL_O<375> WL_O<374> WL_O<373> WL_O<372> ++ WL_O<371> WL_O<370> WL_O<369> WL_O<368> WL_O<367> WL_O<366> WL_O<365> ++ WL_O<364> WL_O<363> WL_O<362> WL_O<361> WL_O<360> WL_O<359> WL_O<358> ++ WL_O<357> WL_O<356> WL_O<355> WL_O<354> WL_O<353> WL_O<352> WL_O<351> ++ WL_O<350> WL_O<349> WL_O<348> WL_O<347> WL_O<346> WL_O<345> WL_O<344> ++ WL_O<343> WL_O<342> WL_O<341> WL_O<340> WL_O<339> WL_O<338> WL_O<337> ++ WL_O<336> WL_O<335> WL_O<334> WL_O<333> WL_O<332> WL_O<331> WL_O<330> ++ WL_O<329> WL_O<328> WL_O<327> WL_O<326> WL_O<325> WL_O<324> WL_O<323> ++ WL_O<322> WL_O<321> WL_O<320> WL_O<319> WL_O<318> WL_O<317> WL_O<316> ++ WL_O<315> WL_O<314> WL_O<313> WL_O<312> WL_O<311> WL_O<310> WL_O<309> ++ WL_O<308> WL_O<307> WL_O<306> WL_O<305> WL_O<304> WL_O<303> WL_O<302> ++ WL_O<301> WL_O<300> WL_O<299> WL_O<298> WL_O<297> WL_O<296> WL_O<295> ++ WL_O<294> WL_O<293> WL_O<292> WL_O<291> WL_O<290> WL_O<289> WL_O<288> ++ WL_O<287> WL_O<286> WL_O<285> WL_O<284> WL_O<283> WL_O<282> WL_O<281> ++ WL_O<280> WL_O<279> WL_O<278> WL_O<277> WL_O<276> WL_O<275> WL_O<274> ++ WL_O<273> WL_O<272> WL_O<271> WL_O<270> WL_O<269> WL_O<268> WL_O<267> ++ WL_O<266> WL_O<265> WL_O<264> WL_O<263> WL_O<262> WL_O<261> WL_O<260> ++ WL_O<259> WL_O<258> WL_O<257> WL_O<256> WL_O<255> WL_O<254> WL_O<253> ++ WL_O<252> WL_O<251> WL_O<250> WL_O<249> WL_O<248> WL_O<247> WL_O<246> ++ WL_O<245> WL_O<244> WL_O<243> WL_O<242> WL_O<241> WL_O<240> WL_O<239> ++ WL_O<238> WL_O<237> WL_O<236> WL_O<235> WL_O<234> WL_O<233> WL_O<232> ++ WL_O<231> WL_O<230> WL_O<229> WL_O<228> WL_O<227> WL_O<226> WL_O<225> ++ WL_O<224> WL_O<223> WL_O<222> WL_O<221> WL_O<220> WL_O<219> WL_O<218> ++ WL_O<217> WL_O<216> WL_O<215> WL_O<214> WL_O<213> WL_O<212> WL_O<211> ++ WL_O<210> WL_O<209> WL_O<208> WL_O<207> WL_O<206> WL_O<205> WL_O<204> ++ WL_O<203> WL_O<202> WL_O<201> WL_O<200> WL_O<199> WL_O<198> WL_O<197> ++ WL_O<196> WL_O<195> WL_O<194> WL_O<193> WL_O<192> WL_O<191> WL_O<190> ++ WL_O<189> WL_O<188> WL_O<187> WL_O<186> WL_O<185> WL_O<184> WL_O<183> ++ WL_O<182> WL_O<181> WL_O<180> WL_O<179> WL_O<178> WL_O<177> WL_O<176> ++ WL_O<175> WL_O<174> WL_O<173> WL_O<172> WL_O<171> WL_O<170> WL_O<169> ++ WL_O<168> WL_O<167> WL_O<166> WL_O<165> WL_O<164> WL_O<163> WL_O<162> ++ WL_O<161> WL_O<160> WL_O<159> WL_O<158> WL_O<157> WL_O<156> WL_O<155> ++ WL_O<154> WL_O<153> WL_O<152> WL_O<151> WL_O<150> WL_O<149> WL_O<148> ++ WL_O<147> WL_O<146> WL_O<145> WL_O<144> WL_O<143> WL_O<142> WL_O<141> ++ WL_O<140> WL_O<139> WL_O<138> WL_O<137> WL_O<136> WL_O<135> WL_O<134> ++ WL_O<133> WL_O<132> WL_O<131> WL_O<130> WL_O<129> WL_O<128> WL_O<127> ++ WL_O<126> WL_O<125> WL_O<124> WL_O<123> WL_O<122> WL_O<121> WL_O<120> ++ WL_O<119> WL_O<118> WL_O<117> WL_O<116> WL_O<115> WL_O<114> WL_O<113> ++ WL_O<112> WL_O<111> WL_O<110> WL_O<109> WL_O<108> WL_O<107> WL_O<106> ++ WL_O<105> WL_O<104> WL_O<103> WL_O<102> WL_O<101> WL_O<100> WL_O<99> ++ WL_O<98> WL_O<97> WL_O<96> WL_O<95> WL_O<94> WL_O<93> WL_O<92> WL_O<91> ++ WL_O<90> WL_O<89> WL_O<88> WL_O<87> WL_O<86> WL_O<85> WL_O<84> WL_O<83> ++ WL_O<82> WL_O<81> WL_O<80> WL_O<79> WL_O<78> WL_O<77> WL_O<76> WL_O<75> ++ WL_O<74> WL_O<73> WL_O<72> WL_O<71> WL_O<70> WL_O<69> WL_O<68> WL_O<67> ++ WL_O<66> WL_O<65> WL_O<64> WL_O<63> WL_O<62> WL_O<61> WL_O<60> WL_O<59> ++ WL_O<58> WL_O<57> WL_O<56> WL_O<55> WL_O<54> WL_O<53> WL_O<52> WL_O<51> ++ WL_O<50> WL_O<49> WL_O<48> WL_O<47> WL_O<46> WL_O<45> WL_O<44> WL_O<43> ++ WL_O<42> WL_O<41> WL_O<40> WL_O<39> WL_O<38> WL_O<37> WL_O<36> WL_O<35> ++ WL_O<34> WL_O<33> WL_O<32> WL_O<31> WL_O<30> WL_O<29> WL_O<28> WL_O<27> ++ WL_O<26> WL_O<25> WL_O<24> WL_O<23> WL_O<22> WL_O<21> WL_O<20> WL_O<19> ++ WL_O<18> WL_O<17> WL_O<16> WL_O<15> WL_O<14> WL_O<13> WL_O<12> WL_O<11> ++ WL_O<10> WL_O<9> WL_O<8> WL_O<7> WL_O<6> WL_O<5> WL_O<4> WL_O<3> WL_O<2> ++ WL_O<1> WL_O<0> VDD VSS +XL2<172> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<171> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<170> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<169> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<168> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<167> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<166> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<165> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<164> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<163> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<162> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<161> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<160> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<159> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<158> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<157> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<156> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<155> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<154> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<153> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<152> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<151> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<150> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<149> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<148> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<147> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<146> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<145> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<144> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<143> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<142> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<141> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<140> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<139> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<138> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<137> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<136> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<135> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<134> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<133> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<132> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<131> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<130> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<129> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<128> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<127> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<126> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<125> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<124> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<123> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<122> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<121> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<120> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<119> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<118> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<117> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<116> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<115> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<114> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<113> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<112> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<111> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<110> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<109> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<108> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<107> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<106> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<105> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<104> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<103> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<102> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<101> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<100> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<99> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<98> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<97> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<96> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<95> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<94> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<93> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<92> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<91> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<90> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<89> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<88> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<87> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<86> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<85> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<84> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<83> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<82> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<81> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<80> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<79> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<78> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<77> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<76> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<75> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<74> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<73> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<72> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<71> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<70> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<69> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<68> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<67> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<66> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<65> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<64> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<63> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<62> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<61> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<60> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<59> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<58> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<57> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<56> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<55> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<54> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<53> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<52> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<51> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<50> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<49> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<48> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<47> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<46> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<45> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<44> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<43> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<42> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<41> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<40> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<39> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<38> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<37> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<36> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<35> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<34> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<33> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<32> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<31> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<30> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<29> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<28> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<27> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<26> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<25> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<24> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<23> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<22> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<21> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<20> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<19> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<18> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<17> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<16> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<15> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<14> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<13> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<12> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<11> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<10> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<9> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<8> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<7> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<6> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<5> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<4> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<3> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<2> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<1> VDD VSS / RSC_IHPSG13_FILLCAP8 +XDEC11<9> ADDR_N_I<7> ADDR_N_I<6> CS04<1> CS02<7> VDD VSS / ++ RM_IHPSG13_256x8_c3_1P_DEC03 +XDEC11<8> ADDR_N_I<7> ADDR_N_I<6> CS04<0> CS02<3> VDD VSS / ++ RM_IHPSG13_256x8_c3_1P_DEC03 +XDEC11<7> ADDR_N_I<5> ADDR_N_I<4> CS02<7> CS00<31> VDD VSS / ++ RM_IHPSG13_256x8_c3_1P_DEC03 +XDEC11<6> ADDR_N_I<5> ADDR_N_I<4> CS02<6> CS00<27> VDD VSS / ++ RM_IHPSG13_256x8_c3_1P_DEC03 +XDEC11<5> ADDR_N_I<5> ADDR_N_I<4> CS02<5> CS00<23> VDD VSS / ++ RM_IHPSG13_256x8_c3_1P_DEC03 +XDEC11<4> ADDR_N_I<5> ADDR_N_I<4> CS02<4> CS00<19> VDD VSS / ++ RM_IHPSG13_256x8_c3_1P_DEC03 +XDEC11<3> ADDR_N_I<5> ADDR_N_I<4> CS02<3> CS00<15> VDD VSS / ++ RM_IHPSG13_256x8_c3_1P_DEC03 +XDEC11<2> ADDR_N_I<5> ADDR_N_I<4> CS02<2> CS00<11> VDD VSS / ++ RM_IHPSG13_256x8_c3_1P_DEC03 +XDEC11<1> ADDR_N_I<5> ADDR_N_I<4> CS02<1> CS00<7> VDD VSS / ++ RM_IHPSG13_256x8_c3_1P_DEC03 +XDEC11<0> ADDR_N_I<5> ADDR_N_I<4> CS02<0> CS00<3> VDD VSS / ++ RM_IHPSG13_256x8_c3_1P_DEC03 +XDEC00<10> ADDR_N_I<9> ADDR_N_I<8> CS_I CS04<0> VDD VSS / ++ RM_IHPSG13_256x8_c3_1P_DEC00 +XDEC00<9> ADDR_N_I<7> ADDR_N_I<6> CS04<1> CS02<4> VDD VSS / ++ RM_IHPSG13_256x8_c3_1P_DEC00 +XDEC00<8> ADDR_N_I<7> ADDR_N_I<6> CS04<0> CS02<0> VDD VSS / ++ RM_IHPSG13_256x8_c3_1P_DEC00 +XDEC00<7> ADDR_N_I<5> ADDR_N_I<4> CS02<7> CS00<28> VDD VSS / ++ RM_IHPSG13_256x8_c3_1P_DEC00 +XDEC00<6> ADDR_N_I<5> ADDR_N_I<4> CS02<6> CS00<24> VDD VSS / ++ RM_IHPSG13_256x8_c3_1P_DEC00 +XDEC00<5> ADDR_N_I<5> ADDR_N_I<4> CS02<5> CS00<20> VDD VSS / ++ RM_IHPSG13_256x8_c3_1P_DEC00 +XDEC00<4> ADDR_N_I<5> ADDR_N_I<4> CS02<4> CS00<16> VDD VSS / ++ RM_IHPSG13_256x8_c3_1P_DEC00 +XDEC00<3> ADDR_N_I<5> ADDR_N_I<4> CS02<3> CS00<12> VDD VSS / ++ RM_IHPSG13_256x8_c3_1P_DEC00 +XDEC00<2> ADDR_N_I<5> ADDR_N_I<4> CS02<2> CS00<8> VDD VSS / ++ RM_IHPSG13_256x8_c3_1P_DEC00 +XDEC00<1> ADDR_N_I<5> ADDR_N_I<4> CS02<1> CS00<4> VDD VSS / ++ RM_IHPSG13_256x8_c3_1P_DEC00 +XDEC00<0> ADDR_N_I<5> ADDR_N_I<4> CS02<0> CS00<0> VDD VSS / ++ RM_IHPSG13_256x8_c3_1P_DEC00 +XSEL<31> ADDR_N_I<3> ADDR_N_I<2> ADDR_N_I<1> ADDR_N_I<0> CS00<31> ECLK_H<31> ++ ECLK_H<32> ECLK_B<31> ECLK_B<32> WL_O<511> WL_O<510> WL_O<509> WL_O<508> ++ WL_O<507> WL_O<506> WL_O<505> WL_O<504> WL_O<503> WL_O<502> WL_O<501> ++ WL_O<500> WL_O<499> WL_O<498> WL_O<497> WL_O<496> VDD VSS / ++ RM_IHPSG13_256x8_c3_1P_DEC04 +XSEL<30> ADDR_N_I<3> ADDR_N_I<2> ADDR_N_I<1> ADDR_N_I<0> CS00<30> ECLK_H<30> ++ ECLK_H<31> ECLK_B<30> ECLK_B<31> WL_O<495> WL_O<494> WL_O<493> WL_O<492> ++ WL_O<491> WL_O<490> WL_O<489> WL_O<488> WL_O<487> WL_O<486> WL_O<485> ++ WL_O<484> WL_O<483> WL_O<482> WL_O<481> WL_O<480> VDD VSS / ++ RM_IHPSG13_256x8_c3_1P_DEC04 +XSEL<29> ADDR_N_I<3> ADDR_N_I<2> ADDR_N_I<1> ADDR_N_I<0> CS00<29> ECLK_H<29> ++ ECLK_H<30> ECLK_B<29> ECLK_B<30> WL_O<479> WL_O<478> WL_O<477> WL_O<476> ++ WL_O<475> WL_O<474> WL_O<473> WL_O<472> WL_O<471> WL_O<470> WL_O<469> ++ WL_O<468> WL_O<467> WL_O<466> WL_O<465> WL_O<464> VDD VSS / ++ RM_IHPSG13_256x8_c3_1P_DEC04 +XSEL<28> ADDR_N_I<3> ADDR_N_I<2> ADDR_N_I<1> ADDR_N_I<0> CS00<28> ECLK_H<28> ++ ECLK_H<29> ECLK_B<28> ECLK_B<29> WL_O<463> WL_O<462> WL_O<461> WL_O<460> ++ WL_O<459> WL_O<458> WL_O<457> WL_O<456> WL_O<455> WL_O<454> WL_O<453> ++ WL_O<452> WL_O<451> WL_O<450> WL_O<449> WL_O<448> VDD VSS / ++ RM_IHPSG13_256x8_c3_1P_DEC04 +XSEL<27> ADDR_N_I<3> ADDR_N_I<2> ADDR_N_I<1> ADDR_N_I<0> CS00<27> ECLK_H<27> ++ ECLK_H<28> ECLK_B<27> ECLK_B<28> WL_O<447> WL_O<446> WL_O<445> WL_O<444> ++ WL_O<443> WL_O<442> WL_O<441> WL_O<440> WL_O<439> WL_O<438> WL_O<437> ++ WL_O<436> WL_O<435> WL_O<434> WL_O<433> WL_O<432> VDD VSS / ++ RM_IHPSG13_256x8_c3_1P_DEC04 +XSEL<26> ADDR_N_I<3> ADDR_N_I<2> ADDR_N_I<1> ADDR_N_I<0> CS00<26> ECLK_H<26> ++ ECLK_H<27> ECLK_B<26> ECLK_B<27> WL_O<431> WL_O<430> WL_O<429> WL_O<428> ++ WL_O<427> WL_O<426> WL_O<425> WL_O<424> WL_O<423> WL_O<422> WL_O<421> ++ WL_O<420> WL_O<419> WL_O<418> WL_O<417> WL_O<416> VDD VSS / ++ RM_IHPSG13_256x8_c3_1P_DEC04 +XSEL<25> ADDR_N_I<3> ADDR_N_I<2> ADDR_N_I<1> ADDR_N_I<0> CS00<25> ECLK_H<25> ++ ECLK_H<26> ECLK_B<25> ECLK_B<26> WL_O<415> WL_O<414> WL_O<413> WL_O<412> ++ WL_O<411> WL_O<410> WL_O<409> WL_O<408> WL_O<407> WL_O<406> WL_O<405> ++ WL_O<404> WL_O<403> WL_O<402> WL_O<401> WL_O<400> VDD VSS / ++ RM_IHPSG13_256x8_c3_1P_DEC04 +XSEL<24> ADDR_N_I<3> ADDR_N_I<2> ADDR_N_I<1> ADDR_N_I<0> CS00<24> ECLK_H<24> ++ ECLK_H<25> ECLK_B<24> ECLK_B<25> WL_O<399> WL_O<398> WL_O<397> WL_O<396> ++ WL_O<395> WL_O<394> WL_O<393> WL_O<392> WL_O<391> WL_O<390> WL_O<389> ++ WL_O<388> WL_O<387> WL_O<386> WL_O<385> WL_O<384> VDD VSS / ++ RM_IHPSG13_256x8_c3_1P_DEC04 +XSEL<23> ADDR_N_I<3> ADDR_N_I<2> ADDR_N_I<1> ADDR_N_I<0> CS00<23> ECLK_H<23> ++ ECLK_H<24> ECLK_B<23> ECLK_B<24> WL_O<383> WL_O<382> WL_O<381> WL_O<380> ++ WL_O<379> WL_O<378> WL_O<377> WL_O<376> WL_O<375> WL_O<374> WL_O<373> ++ WL_O<372> WL_O<371> WL_O<370> WL_O<369> WL_O<368> VDD VSS / ++ RM_IHPSG13_256x8_c3_1P_DEC04 +XSEL<22> ADDR_N_I<3> ADDR_N_I<2> ADDR_N_I<1> ADDR_N_I<0> CS00<22> ECLK_H<22> ++ ECLK_H<23> ECLK_B<22> ECLK_B<23> WL_O<367> WL_O<366> WL_O<365> WL_O<364> ++ WL_O<363> WL_O<362> WL_O<361> WL_O<360> WL_O<359> WL_O<358> WL_O<357> ++ WL_O<356> WL_O<355> WL_O<354> WL_O<353> WL_O<352> VDD VSS / ++ RM_IHPSG13_256x8_c3_1P_DEC04 +XSEL<21> ADDR_N_I<3> ADDR_N_I<2> ADDR_N_I<1> ADDR_N_I<0> CS00<21> ECLK_H<21> ++ ECLK_H<22> ECLK_B<21> ECLK_B<22> WL_O<351> WL_O<350> WL_O<349> WL_O<348> ++ WL_O<347> WL_O<346> WL_O<345> WL_O<344> WL_O<343> WL_O<342> WL_O<341> ++ WL_O<340> WL_O<339> WL_O<338> WL_O<337> WL_O<336> VDD VSS / ++ RM_IHPSG13_256x8_c3_1P_DEC04 +XSEL<20> ADDR_N_I<3> ADDR_N_I<2> ADDR_N_I<1> ADDR_N_I<0> CS00<20> ECLK_H<20> ++ ECLK_H<21> ECLK_B<20> ECLK_B<21> WL_O<335> WL_O<334> WL_O<333> WL_O<332> ++ WL_O<331> WL_O<330> WL_O<329> WL_O<328> WL_O<327> WL_O<326> WL_O<325> ++ WL_O<324> WL_O<323> WL_O<322> WL_O<321> WL_O<320> VDD VSS / ++ RM_IHPSG13_256x8_c3_1P_DEC04 +XSEL<19> ADDR_N_I<3> ADDR_N_I<2> ADDR_N_I<1> ADDR_N_I<0> CS00<19> ECLK_H<19> ++ ECLK_H<20> ECLK_B<19> ECLK_B<20> WL_O<319> WL_O<318> WL_O<317> WL_O<316> ++ WL_O<315> WL_O<314> WL_O<313> WL_O<312> WL_O<311> WL_O<310> WL_O<309> ++ WL_O<308> WL_O<307> WL_O<306> WL_O<305> WL_O<304> VDD VSS / ++ RM_IHPSG13_256x8_c3_1P_DEC04 +XSEL<18> ADDR_N_I<3> ADDR_N_I<2> ADDR_N_I<1> ADDR_N_I<0> CS00<18> ECLK_H<18> ++ ECLK_H<19> ECLK_B<18> ECLK_B<19> WL_O<303> WL_O<302> WL_O<301> WL_O<300> ++ WL_O<299> WL_O<298> WL_O<297> WL_O<296> WL_O<295> WL_O<294> WL_O<293> ++ WL_O<292> WL_O<291> WL_O<290> WL_O<289> WL_O<288> VDD VSS / ++ RM_IHPSG13_256x8_c3_1P_DEC04 +XSEL<17> ADDR_N_I<3> ADDR_N_I<2> ADDR_N_I<1> ADDR_N_I<0> CS00<17> ECLK_H<17> ++ ECLK_H<18> ECLK_B<17> ECLK_B<18> WL_O<287> WL_O<286> WL_O<285> WL_O<284> ++ WL_O<283> WL_O<282> WL_O<281> WL_O<280> WL_O<279> WL_O<278> WL_O<277> ++ WL_O<276> WL_O<275> WL_O<274> WL_O<273> WL_O<272> VDD VSS / ++ RM_IHPSG13_256x8_c3_1P_DEC04 +XSEL<16> ADDR_N_I<3> ADDR_N_I<2> ADDR_N_I<1> ADDR_N_I<0> CS00<16> ECLK_H<16> ++ ECLK_H<17> ECLK_B<16> ECLK_B<17> WL_O<271> WL_O<270> WL_O<269> WL_O<268> ++ WL_O<267> WL_O<266> WL_O<265> WL_O<264> WL_O<263> WL_O<262> WL_O<261> ++ WL_O<260> WL_O<259> WL_O<258> WL_O<257> WL_O<256> VDD VSS / ++ RM_IHPSG13_256x8_c3_1P_DEC04 +XSEL<15> ADDR_N_I<3> ADDR_N_I<2> ADDR_N_I<1> ADDR_N_I<0> CS00<15> ECLK_H<15> ++ ECLK_H<16> ECLK_B<15> ECLK_B<16> WL_O<255> WL_O<254> WL_O<253> WL_O<252> ++ WL_O<251> WL_O<250> WL_O<249> WL_O<248> WL_O<247> WL_O<246> WL_O<245> ++ WL_O<244> WL_O<243> WL_O<242> WL_O<241> WL_O<240> VDD VSS / ++ RM_IHPSG13_256x8_c3_1P_DEC04 +XSEL<14> ADDR_N_I<3> ADDR_N_I<2> ADDR_N_I<1> ADDR_N_I<0> CS00<14> ECLK_H<14> ++ ECLK_H<15> ECLK_B<14> ECLK_B<15> WL_O<239> WL_O<238> WL_O<237> WL_O<236> ++ WL_O<235> WL_O<234> WL_O<233> WL_O<232> WL_O<231> WL_O<230> WL_O<229> ++ WL_O<228> WL_O<227> WL_O<226> WL_O<225> WL_O<224> VDD VSS / ++ RM_IHPSG13_256x8_c3_1P_DEC04 +XSEL<13> ADDR_N_I<3> ADDR_N_I<2> ADDR_N_I<1> ADDR_N_I<0> CS00<13> ECLK_H<13> ++ ECLK_H<14> ECLK_B<13> ECLK_B<14> WL_O<223> WL_O<222> WL_O<221> WL_O<220> ++ WL_O<219> WL_O<218> WL_O<217> WL_O<216> WL_O<215> WL_O<214> WL_O<213> ++ WL_O<212> WL_O<211> WL_O<210> WL_O<209> WL_O<208> VDD VSS / ++ RM_IHPSG13_256x8_c3_1P_DEC04 +XSEL<12> ADDR_N_I<3> ADDR_N_I<2> ADDR_N_I<1> ADDR_N_I<0> CS00<12> ECLK_H<12> ++ ECLK_H<13> ECLK_B<12> ECLK_B<13> WL_O<207> WL_O<206> WL_O<205> WL_O<204> ++ WL_O<203> WL_O<202> WL_O<201> WL_O<200> WL_O<199> WL_O<198> WL_O<197> ++ WL_O<196> WL_O<195> WL_O<194> WL_O<193> WL_O<192> VDD VSS / ++ RM_IHPSG13_256x8_c3_1P_DEC04 +XSEL<11> ADDR_N_I<3> ADDR_N_I<2> ADDR_N_I<1> ADDR_N_I<0> CS00<11> ECLK_H<11> ++ ECLK_H<12> ECLK_B<11> ECLK_B<12> WL_O<191> WL_O<190> WL_O<189> WL_O<188> ++ WL_O<187> WL_O<186> WL_O<185> WL_O<184> WL_O<183> WL_O<182> WL_O<181> ++ WL_O<180> WL_O<179> WL_O<178> WL_O<177> WL_O<176> VDD VSS / ++ RM_IHPSG13_256x8_c3_1P_DEC04 +XSEL<10> ADDR_N_I<3> ADDR_N_I<2> ADDR_N_I<1> ADDR_N_I<0> CS00<10> ECLK_H<10> ++ ECLK_H<11> ECLK_B<10> ECLK_B<11> WL_O<175> WL_O<174> WL_O<173> WL_O<172> ++ WL_O<171> WL_O<170> WL_O<169> WL_O<168> WL_O<167> WL_O<166> WL_O<165> ++ WL_O<164> WL_O<163> WL_O<162> WL_O<161> WL_O<160> VDD VSS / ++ RM_IHPSG13_256x8_c3_1P_DEC04 +XSEL<9> ADDR_N_I<3> ADDR_N_I<2> ADDR_N_I<1> ADDR_N_I<0> CS00<9> ECLK_H<9> ++ ECLK_H<10> ECLK_B<9> ECLK_B<10> WL_O<159> WL_O<158> WL_O<157> WL_O<156> ++ WL_O<155> WL_O<154> WL_O<153> WL_O<152> WL_O<151> WL_O<150> WL_O<149> ++ WL_O<148> WL_O<147> WL_O<146> WL_O<145> WL_O<144> VDD VSS / ++ RM_IHPSG13_256x8_c3_1P_DEC04 +XSEL<8> ADDR_N_I<3> ADDR_N_I<2> ADDR_N_I<1> ADDR_N_I<0> CS00<8> ECLK_H<8> ++ ECLK_H<9> ECLK_B<8> ECLK_B<9> WL_O<143> WL_O<142> WL_O<141> WL_O<140> ++ WL_O<139> WL_O<138> WL_O<137> WL_O<136> WL_O<135> WL_O<134> WL_O<133> ++ WL_O<132> WL_O<131> WL_O<130> WL_O<129> WL_O<128> VDD VSS / ++ RM_IHPSG13_256x8_c3_1P_DEC04 +XSEL<7> ADDR_N_I<3> ADDR_N_I<2> ADDR_N_I<1> ADDR_N_I<0> CS00<7> ECLK_H<7> ++ ECLK_H<8> ECLK_B<7> ECLK_B<8> WL_O<127> WL_O<126> WL_O<125> WL_O<124> ++ WL_O<123> WL_O<122> WL_O<121> WL_O<120> WL_O<119> WL_O<118> WL_O<117> ++ WL_O<116> WL_O<115> WL_O<114> WL_O<113> WL_O<112> VDD VSS / ++ RM_IHPSG13_256x8_c3_1P_DEC04 +XSEL<6> ADDR_N_I<3> ADDR_N_I<2> ADDR_N_I<1> ADDR_N_I<0> CS00<6> ECLK_H<6> ++ ECLK_H<7> ECLK_B<6> ECLK_B<7> WL_O<111> WL_O<110> WL_O<109> WL_O<108> ++ WL_O<107> WL_O<106> WL_O<105> WL_O<104> WL_O<103> WL_O<102> WL_O<101> ++ WL_O<100> WL_O<99> WL_O<98> WL_O<97> WL_O<96> VDD VSS / ++ RM_IHPSG13_256x8_c3_1P_DEC04 +XSEL<5> ADDR_N_I<3> ADDR_N_I<2> ADDR_N_I<1> ADDR_N_I<0> CS00<5> ECLK_H<5> ++ ECLK_H<6> ECLK_B<5> ECLK_B<6> WL_O<95> WL_O<94> WL_O<93> WL_O<92> WL_O<91> ++ WL_O<90> WL_O<89> WL_O<88> WL_O<87> WL_O<86> WL_O<85> WL_O<84> WL_O<83> ++ WL_O<82> WL_O<81> WL_O<80> VDD VSS / RM_IHPSG13_256x8_c3_1P_DEC04 +XSEL<4> ADDR_N_I<3> ADDR_N_I<2> ADDR_N_I<1> ADDR_N_I<0> CS00<4> ECLK_H<4> ++ ECLK_H<5> ECLK_B<4> ECLK_B<5> WL_O<79> WL_O<78> WL_O<77> WL_O<76> WL_O<75> ++ WL_O<74> WL_O<73> WL_O<72> WL_O<71> WL_O<70> WL_O<69> WL_O<68> WL_O<67> ++ WL_O<66> WL_O<65> WL_O<64> VDD VSS / RM_IHPSG13_256x8_c3_1P_DEC04 +XSEL<3> ADDR_N_I<3> ADDR_N_I<2> ADDR_N_I<1> ADDR_N_I<0> CS00<3> ECLK_H<3> ++ ECLK_H<4> ECLK_B<3> ECLK_B<4> WL_O<63> WL_O<62> WL_O<61> WL_O<60> WL_O<59> ++ WL_O<58> WL_O<57> WL_O<56> WL_O<55> WL_O<54> WL_O<53> WL_O<52> WL_O<51> ++ WL_O<50> WL_O<49> WL_O<48> VDD VSS / RM_IHPSG13_256x8_c3_1P_DEC04 +XSEL<2> ADDR_N_I<3> ADDR_N_I<2> ADDR_N_I<1> ADDR_N_I<0> CS00<2> ECLK_H<2> ++ ECLK_H<3> ECLK_B<2> ECLK_B<3> WL_O<47> WL_O<46> WL_O<45> WL_O<44> WL_O<43> ++ WL_O<42> WL_O<41> WL_O<40> WL_O<39> WL_O<38> WL_O<37> WL_O<36> WL_O<35> ++ WL_O<34> WL_O<33> WL_O<32> VDD VSS / RM_IHPSG13_256x8_c3_1P_DEC04 +XSEL<1> ADDR_N_I<3> ADDR_N_I<2> ADDR_N_I<1> ADDR_N_I<0> CS00<1> ECLK_H<1> ++ ECLK_H<2> ECLK_B<1> ECLK_B<2> WL_O<31> WL_O<30> WL_O<29> WL_O<28> WL_O<27> ++ WL_O<26> WL_O<25> WL_O<24> WL_O<23> WL_O<22> WL_O<21> WL_O<20> WL_O<19> ++ WL_O<18> WL_O<17> WL_O<16> VDD VSS / RM_IHPSG13_256x8_c3_1P_DEC04 +XSEL<0> ADDR_N_I<3> ADDR_N_I<2> ADDR_N_I<1> ADDR_N_I<0> CS00<0> ECLK_I ++ ECLK_H<1> ECLK_B<0> ECLK_B<1> WL_O<15> WL_O<14> WL_O<13> WL_O<12> WL_O<11> ++ WL_O<10> WL_O<9> WL_O<8> WL_O<7> WL_O<6> WL_O<5> WL_O<4> WL_O<3> WL_O<2> ++ WL_O<1> WL_O<0> VDD VSS / RM_IHPSG13_256x8_c3_1P_DEC04 +XDEC01<10> ADDR_N_I<9> ADDR_N_I<8> CS_I CS04<1> VDD VSS / ++ RM_IHPSG13_256x8_c3_1P_DEC01 +XDEC01<9> ADDR_N_I<7> ADDR_N_I<6> CS04<1> CS02<5> VDD VSS / ++ RM_IHPSG13_256x8_c3_1P_DEC01 +XDEC01<8> ADDR_N_I<7> ADDR_N_I<6> CS04<0> CS02<1> VDD VSS / ++ RM_IHPSG13_256x8_c3_1P_DEC01 +XDEC01<7> ADDR_N_I<5> ADDR_N_I<4> CS02<7> CS00<29> VDD VSS / ++ RM_IHPSG13_256x8_c3_1P_DEC01 +XDEC01<6> ADDR_N_I<5> ADDR_N_I<4> CS02<6> CS00<25> VDD VSS / ++ RM_IHPSG13_256x8_c3_1P_DEC01 +XDEC01<5> ADDR_N_I<5> ADDR_N_I<4> CS02<5> CS00<21> VDD VSS / ++ RM_IHPSG13_256x8_c3_1P_DEC01 +XDEC01<4> ADDR_N_I<5> ADDR_N_I<4> CS02<4> CS00<17> VDD VSS / ++ RM_IHPSG13_256x8_c3_1P_DEC01 +XDEC01<3> ADDR_N_I<5> ADDR_N_I<4> CS02<3> CS00<13> VDD VSS / ++ RM_IHPSG13_256x8_c3_1P_DEC01 +XDEC01<2> ADDR_N_I<5> ADDR_N_I<4> CS02<2> CS00<9> VDD VSS / ++ RM_IHPSG13_256x8_c3_1P_DEC01 +XDEC01<1> ADDR_N_I<5> ADDR_N_I<4> CS02<1> CS00<5> VDD VSS / ++ RM_IHPSG13_256x8_c3_1P_DEC01 +XDEC01<0> ADDR_N_I<5> ADDR_N_I<4> CS02<0> CS00<1> VDD VSS / ++ RM_IHPSG13_256x8_c3_1P_DEC01 +XDEC10<9> ADDR_N_I<7> ADDR_N_I<6> CS04<1> CS02<6> VDD VSS / ++ RM_IHPSG13_256x8_c3_1P_DEC02 +XDEC10<8> ADDR_N_I<7> ADDR_N_I<6> CS04<0> CS02<2> VDD VSS / ++ RM_IHPSG13_256x8_c3_1P_DEC02 +XDEC10<7> ADDR_N_I<5> ADDR_N_I<4> CS02<7> CS00<30> VDD VSS / ++ RM_IHPSG13_256x8_c3_1P_DEC02 +XDEC10<6> ADDR_N_I<5> ADDR_N_I<4> CS02<6> CS00<26> VDD VSS / ++ RM_IHPSG13_256x8_c3_1P_DEC02 +XDEC10<5> ADDR_N_I<5> ADDR_N_I<4> CS02<5> CS00<22> VDD VSS / ++ RM_IHPSG13_256x8_c3_1P_DEC02 +XDEC10<4> ADDR_N_I<5> ADDR_N_I<4> CS02<4> CS00<18> VDD VSS / ++ RM_IHPSG13_256x8_c3_1P_DEC02 +XDEC10<3> ADDR_N_I<5> ADDR_N_I<4> CS02<3> CS00<14> VDD VSS / ++ RM_IHPSG13_256x8_c3_1P_DEC02 +XDEC10<2> ADDR_N_I<5> ADDR_N_I<4> CS02<2> CS00<10> VDD VSS / ++ RM_IHPSG13_256x8_c3_1P_DEC02 +XDEC10<1> ADDR_N_I<5> ADDR_N_I<4> CS02<1> CS00<6> VDD VSS / ++ RM_IHPSG13_256x8_c3_1P_DEC02 +XDEC10<0> ADDR_N_I<5> ADDR_N_I<4> CS02<0> CS00<2> VDD VSS / ++ RM_IHPSG13_256x8_c3_1P_DEC02 +XI0 ADDR_N_I<9> VDD VSS / RSC_IHPSG13_TIEL +.ENDS +.SUBCKT RM_IHPSG13_256x8_c3_1P_ROWREG9 ACLK_N_I ADDR_I<8> ADDR_I<7> ADDR_I<6> ADDR_I<5> ++ ADDR_I<4> ADDR_I<3> ADDR_I<2> ADDR_I<1> ADDR_I<0> ADDR_N_O<8> ADDR_N_O<7> ++ ADDR_N_O<6> ADDR_N_O<5> ADDR_N_O<4> ADDR_N_O<3> ADDR_N_O<2> ADDR_N_O<1> ++ ADDR_N_O<0> BIST_ADDR_I<8> BIST_ADDR_I<7> BIST_ADDR_I<6> BIST_ADDR_I<5> ++ BIST_ADDR_I<4> BIST_ADDR_I<3> BIST_ADDR_I<2> BIST_ADDR_I<1> BIST_ADDR_I<0> ++ BIST_EN_I VDD VSS +XINV<8> q_int<8> qn_int<8> VDD VSS / RSC_IHPSG13_CINVX2 +XINV<7> q_int<7> qn_int<7> VDD VSS / RSC_IHPSG13_CINVX2 +XINV<6> q_int<6> qn_int<6> VDD VSS / RSC_IHPSG13_CINVX2 +XINV<5> q_int<5> qn_int<5> VDD VSS / RSC_IHPSG13_CINVX2 +XINV<4> q_int<4> qn_int<4> VDD VSS / RSC_IHPSG13_CINVX2 +XINV<3> q_int<3> qn_int<3> VDD VSS / RSC_IHPSG13_CINVX2 +XINV<2> q_int<2> qn_int<2> VDD VSS / RSC_IHPSG13_CINVX2 +XINV<1> q_int<1> qn_int<1> VDD VSS / RSC_IHPSG13_CINVX2 +XINV<0> q_int<0> qn_int<0> VDD VSS / RSC_IHPSG13_CINVX2 +XDRV<8> qn_int<8> ADDR_N_O<8> VDD VSS / RSC_IHPSG13_CINVX8 +XDRV<7> qn_int<7> ADDR_N_O<7> VDD VSS / RSC_IHPSG13_CINVX8 +XDRV<6> qn_int<6> ADDR_N_O<6> VDD VSS / RSC_IHPSG13_CINVX8 +XDRV<5> qn_int<5> ADDR_N_O<5> VDD VSS / RSC_IHPSG13_CINVX8 +XDRV<4> qn_int<4> ADDR_N_O<4> VDD VSS / RSC_IHPSG13_CINVX8 +XDRV<3> qn_int<3> ADDR_N_O<3> VDD VSS / RSC_IHPSG13_CINVX8 +XDRV<2> qn_int<2> ADDR_N_O<2> VDD VSS / RSC_IHPSG13_CINVX8 +XDRV<1> qn_int<1> ADDR_N_O<1> VDD VSS / RSC_IHPSG13_CINVX8 +XDRV<0> qn_int<0> ADDR_N_O<0> VDD VSS / RSC_IHPSG13_CINVX8 +XDFF<8> BIST_EN_I BIST_ADDR_I<8> ACLK_N_I ADDR_I<8> q_int<8> net04<0> VDD ++ VSS / RSC_IHPSG13_DFNQMX2IX1 +XDFF<7> BIST_EN_I BIST_ADDR_I<7> ACLK_N_I ADDR_I<7> q_int<7> net04<1> VDD ++ VSS / RSC_IHPSG13_DFNQMX2IX1 +XDFF<6> BIST_EN_I BIST_ADDR_I<6> ACLK_N_I ADDR_I<6> q_int<6> net04<2> VDD ++ VSS / RSC_IHPSG13_DFNQMX2IX1 +XDFF<5> BIST_EN_I BIST_ADDR_I<5> ACLK_N_I ADDR_I<5> q_int<5> net04<3> VDD ++ VSS / RSC_IHPSG13_DFNQMX2IX1 +XDFF<4> BIST_EN_I BIST_ADDR_I<4> ACLK_N_I ADDR_I<4> q_int<4> net04<4> VDD ++ VSS / RSC_IHPSG13_DFNQMX2IX1 +XDFF<3> BIST_EN_I BIST_ADDR_I<3> ACLK_N_I ADDR_I<3> q_int<3> net04<5> VDD ++ VSS / RSC_IHPSG13_DFNQMX2IX1 +XDFF<2> BIST_EN_I BIST_ADDR_I<2> ACLK_N_I ADDR_I<2> q_int<2> net04<6> VDD ++ VSS / RSC_IHPSG13_DFNQMX2IX1 +XDFF<1> BIST_EN_I BIST_ADDR_I<1> ACLK_N_I ADDR_I<1> q_int<1> net04<7> VDD ++ VSS / RSC_IHPSG13_DFNQMX2IX1 +XDFF<0> BIST_EN_I BIST_ADDR_I<0> ACLK_N_I ADDR_I<0> q_int<0> net04<8> VDD ++ VSS / RSC_IHPSG13_DFNQMX2IX1 +.ENDS + +.SUBCKT RM_IHPSG13_256x8_c3_1P_ROWDEC7 ADDR_N_I<6> ADDR_N_I<5> ADDR_N_I<4> ADDR_N_I<3> ++ ADDR_N_I<2> ADDR_N_I<1> ADDR_N_I<0> CS_I ECLK_I WL_O<127> WL_O<126> ++ WL_O<125> WL_O<124> WL_O<123> WL_O<122> WL_O<121> WL_O<120> WL_O<119> ++ WL_O<118> WL_O<117> WL_O<116> WL_O<115> WL_O<114> WL_O<113> WL_O<112> ++ WL_O<111> WL_O<110> WL_O<109> WL_O<108> WL_O<107> WL_O<106> WL_O<105> ++ WL_O<104> WL_O<103> WL_O<102> WL_O<101> WL_O<100> WL_O<99> WL_O<98> WL_O<97> ++ WL_O<96> WL_O<95> WL_O<94> WL_O<93> WL_O<92> WL_O<91> WL_O<90> WL_O<89> ++ WL_O<88> WL_O<87> WL_O<86> WL_O<85> WL_O<84> WL_O<83> WL_O<82> WL_O<81> ++ WL_O<80> WL_O<79> WL_O<78> WL_O<77> WL_O<76> WL_O<75> WL_O<74> WL_O<73> ++ WL_O<72> WL_O<71> WL_O<70> WL_O<69> WL_O<68> WL_O<67> WL_O<66> WL_O<65> ++ WL_O<64> WL_O<63> WL_O<62> WL_O<61> WL_O<60> WL_O<59> WL_O<58> WL_O<57> ++ WL_O<56> WL_O<55> WL_O<54> WL_O<53> WL_O<52> WL_O<51> WL_O<50> WL_O<49> ++ WL_O<48> WL_O<47> WL_O<46> WL_O<45> WL_O<44> WL_O<43> WL_O<42> WL_O<41> ++ WL_O<40> WL_O<39> WL_O<38> WL_O<37> WL_O<36> WL_O<35> WL_O<34> WL_O<33> ++ WL_O<32> WL_O<31> WL_O<30> WL_O<29> WL_O<28> WL_O<27> WL_O<26> WL_O<25> ++ WL_O<24> WL_O<23> WL_O<22> WL_O<21> WL_O<20> WL_O<19> WL_O<18> WL_O<17> ++ WL_O<16> WL_O<15> WL_O<14> WL_O<13> WL_O<12> WL_O<11> WL_O<10> WL_O<9> ++ WL_O<8> WL_O<7> WL_O<6> WL_O<5> WL_O<4> WL_O<3> WL_O<2> WL_O<1> WL_O<0> ++ VDD VSS +XDEC11<1> ADDR_N_I<5> ADDR_N_I<4> CS04<1> CS00<7> VDD VSS / ++ RM_IHPSG13_256x8_c3_1P_DEC03 +XDEC11<0> ADDR_N_I<5> ADDR_N_I<4> CS04<0> CS00<3> VDD VSS / ++ RM_IHPSG13_256x8_c3_1P_DEC03 +XDEC10<1> ADDR_N_I<5> ADDR_N_I<4> CS04<1> CS00<6> VDD VSS / ++ RM_IHPSG13_256x8_c3_1P_DEC02 +XDEC10<0> ADDR_N_I<5> ADDR_N_I<4> CS04<0> CS00<2> VDD VSS / ++ RM_IHPSG13_256x8_c3_1P_DEC02 +XSEL<7> ADDR_N_I<3> ADDR_N_I<2> ADDR_N_I<1> ADDR_N_I<0> CS00<7> ECLK_H<7> ++ ECLK_H<8> ECLK_B<7> ECLK_B<8> WL_O<127> WL_O<126> WL_O<125> WL_O<124> ++ WL_O<123> WL_O<122> WL_O<121> WL_O<120> WL_O<119> WL_O<118> WL_O<117> ++ WL_O<116> WL_O<115> WL_O<114> WL_O<113> WL_O<112> VDD VSS / ++ RM_IHPSG13_256x8_c3_1P_DEC04 +XSEL<6> ADDR_N_I<3> ADDR_N_I<2> ADDR_N_I<1> ADDR_N_I<0> CS00<6> ECLK_H<6> ++ ECLK_H<7> ECLK_B<6> ECLK_B<7> WL_O<111> WL_O<110> WL_O<109> WL_O<108> ++ WL_O<107> WL_O<106> WL_O<105> WL_O<104> WL_O<103> WL_O<102> WL_O<101> ++ WL_O<100> WL_O<99> WL_O<98> WL_O<97> WL_O<96> VDD VSS / ++ RM_IHPSG13_256x8_c3_1P_DEC04 +XSEL<5> ADDR_N_I<3> ADDR_N_I<2> ADDR_N_I<1> ADDR_N_I<0> CS00<5> ECLK_H<5> ++ ECLK_H<6> ECLK_B<5> ECLK_B<6> WL_O<95> WL_O<94> WL_O<93> WL_O<92> WL_O<91> ++ WL_O<90> WL_O<89> WL_O<88> WL_O<87> WL_O<86> WL_O<85> WL_O<84> WL_O<83> ++ WL_O<82> WL_O<81> WL_O<80> VDD VSS / RM_IHPSG13_256x8_c3_1P_DEC04 +XSEL<4> ADDR_N_I<3> ADDR_N_I<2> ADDR_N_I<1> ADDR_N_I<0> CS00<4> ECLK_H<4> ++ ECLK_H<5> ECLK_B<4> ECLK_B<5> WL_O<79> WL_O<78> WL_O<77> WL_O<76> WL_O<75> ++ WL_O<74> WL_O<73> WL_O<72> WL_O<71> WL_O<70> WL_O<69> WL_O<68> WL_O<67> ++ WL_O<66> WL_O<65> WL_O<64> VDD VSS / RM_IHPSG13_256x8_c3_1P_DEC04 +XSEL<3> ADDR_N_I<3> ADDR_N_I<2> ADDR_N_I<1> ADDR_N_I<0> CS00<3> ECLK_H<3> ++ ECLK_H<4> ECLK_B<3> ECLK_B<4> WL_O<63> WL_O<62> WL_O<61> WL_O<60> WL_O<59> ++ WL_O<58> WL_O<57> WL_O<56> WL_O<55> WL_O<54> WL_O<53> WL_O<52> WL_O<51> ++ WL_O<50> WL_O<49> WL_O<48> VDD VSS / RM_IHPSG13_256x8_c3_1P_DEC04 +XSEL<2> ADDR_N_I<3> ADDR_N_I<2> ADDR_N_I<1> ADDR_N_I<0> CS00<2> ECLK_H<2> ++ ECLK_H<3> ECLK_B<2> ECLK_B<3> WL_O<47> WL_O<46> WL_O<45> WL_O<44> WL_O<43> ++ WL_O<42> WL_O<41> WL_O<40> WL_O<39> WL_O<38> WL_O<37> WL_O<36> WL_O<35> ++ WL_O<34> WL_O<33> WL_O<32> VDD VSS / RM_IHPSG13_256x8_c3_1P_DEC04 +XSEL<1> ADDR_N_I<3> ADDR_N_I<2> ADDR_N_I<1> ADDR_N_I<0> CS00<1> ECLK_H<1> ++ ECLK_H<2> ECLK_B<1> ECLK_B<2> WL_O<31> WL_O<30> WL_O<29> WL_O<28> WL_O<27> ++ WL_O<26> WL_O<25> WL_O<24> WL_O<23> WL_O<22> WL_O<21> WL_O<20> WL_O<19> ++ WL_O<18> WL_O<17> WL_O<16> VDD VSS / RM_IHPSG13_256x8_c3_1P_DEC04 +XSEL<0> ADDR_N_I<3> ADDR_N_I<2> ADDR_N_I<1> ADDR_N_I<0> CS00<0> ECLK_I ++ ECLK_H<1> ECLK_B<0> ECLK_B<1> WL_O<15> WL_O<14> WL_O<13> WL_O<12> WL_O<11> ++ WL_O<10> WL_O<9> WL_O<8> WL_O<7> WL_O<6> WL_O<5> WL_O<4> WL_O<3> WL_O<2> ++ WL_O<1> WL_O<0> VDD VSS / RM_IHPSG13_256x8_c3_1P_DEC04 +XDEC00<2> ADDR_N_I<7> ADDR_N_I<6> CS_I CS04<0> VDD VSS / ++ RM_IHPSG13_256x8_c3_1P_DEC00 +XDEC00<1> ADDR_N_I<5> ADDR_N_I<4> CS04<1> CS00<4> VDD VSS / ++ RM_IHPSG13_256x8_c3_1P_DEC00 +XDEC00<0> ADDR_N_I<5> ADDR_N_I<4> CS04<0> CS00<0> VDD VSS / ++ RM_IHPSG13_256x8_c3_1P_DEC00 +XDEC01<2> ADDR_N_I<7> ADDR_N_I<6> CS_I CS04<1> VDD VSS / ++ RM_IHPSG13_256x8_c3_1P_DEC01 +XDEC01<1> ADDR_N_I<5> ADDR_N_I<4> CS04<1> CS00<5> VDD VSS / ++ RM_IHPSG13_256x8_c3_1P_DEC01 +XDEC01<0> ADDR_N_I<5> ADDR_N_I<4> CS04<0> CS00<1> VDD VSS / ++ RM_IHPSG13_256x8_c3_1P_DEC01 +XL2<44> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<43> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<42> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<41> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<40> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<39> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<38> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<37> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<36> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<35> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<34> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<33> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<32> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<31> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<30> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<29> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<28> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<27> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<26> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<25> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<24> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<23> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<22> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<21> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<20> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<19> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<18> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<17> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<16> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<15> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<14> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<13> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<12> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<11> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<10> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<9> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<8> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<7> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<6> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<5> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<4> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<3> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<2> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<1> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI0 ADDR_N_I<7> VDD VSS / RSC_IHPSG13_TIEL +.ENDS +.SUBCKT RM_IHPSG13_256x8_c3_1P_ROWREG7 ACLK_N_I ADDR_I<6> ADDR_I<5> ADDR_I<4> ADDR_I<3> ++ ADDR_I<2> ADDR_I<1> ADDR_I<0> ADDR_N_O<6> ADDR_N_O<5> ADDR_N_O<4> ++ ADDR_N_O<3> ADDR_N_O<2> ADDR_N_O<1> ADDR_N_O<0> BIST_ADDR_I<6> ++ BIST_ADDR_I<5> BIST_ADDR_I<4> BIST_ADDR_I<3> BIST_ADDR_I<2> BIST_ADDR_I<1> ++ BIST_ADDR_I<0> BIST_EN_I VDD VSS +XINV<6> q_int<6> qn_int<6> VDD VSS / RSC_IHPSG13_CINVX2 +XINV<5> q_int<5> qn_int<5> VDD VSS / RSC_IHPSG13_CINVX2 +XINV<4> q_int<4> qn_int<4> VDD VSS / RSC_IHPSG13_CINVX2 +XINV<3> q_int<3> qn_int<3> VDD VSS / RSC_IHPSG13_CINVX2 +XINV<2> q_int<2> qn_int<2> VDD VSS / RSC_IHPSG13_CINVX2 +XINV<1> q_int<1> qn_int<1> VDD VSS / RSC_IHPSG13_CINVX2 +XINV<0> q_int<0> qn_int<0> VDD VSS / RSC_IHPSG13_CINVX2 +XDRV<6> qn_int<6> ADDR_N_O<6> VDD VSS / RSC_IHPSG13_CINVX8 +XDRV<5> qn_int<5> ADDR_N_O<5> VDD VSS / RSC_IHPSG13_CINVX8 +XDRV<4> qn_int<4> ADDR_N_O<4> VDD VSS / RSC_IHPSG13_CINVX8 +XDRV<3> qn_int<3> ADDR_N_O<3> VDD VSS / RSC_IHPSG13_CINVX8 +XDRV<2> qn_int<2> ADDR_N_O<2> VDD VSS / RSC_IHPSG13_CINVX8 +XDRV<1> qn_int<1> ADDR_N_O<1> VDD VSS / RSC_IHPSG13_CINVX8 +XDRV<0> qn_int<0> ADDR_N_O<0> VDD VSS / RSC_IHPSG13_CINVX8 +XDFF<6> BIST_EN_I BIST_ADDR_I<6> ACLK_N_I ADDR_I<6> q_int<6> net2<0> VDD ++ VSS / RSC_IHPSG13_DFNQMX2IX1 +XDFF<5> BIST_EN_I BIST_ADDR_I<5> ACLK_N_I ADDR_I<5> q_int<5> net2<1> VDD ++ VSS / RSC_IHPSG13_DFNQMX2IX1 +XDFF<4> BIST_EN_I BIST_ADDR_I<4> ACLK_N_I ADDR_I<4> q_int<4> net2<2> VDD ++ VSS / RSC_IHPSG13_DFNQMX2IX1 +XDFF<3> BIST_EN_I BIST_ADDR_I<3> ACLK_N_I ADDR_I<3> q_int<3> net2<3> VDD ++ VSS / RSC_IHPSG13_DFNQMX2IX1 +XDFF<2> BIST_EN_I BIST_ADDR_I<2> ACLK_N_I ADDR_I<2> q_int<2> net2<4> VDD ++ VSS / RSC_IHPSG13_DFNQMX2IX1 +XDFF<1> BIST_EN_I BIST_ADDR_I<1> ACLK_N_I ADDR_I<1> q_int<1> net2<5> VDD ++ VSS / RSC_IHPSG13_DFNQMX2IX1 +XDFF<0> BIST_EN_I BIST_ADDR_I<0> ACLK_N_I ADDR_I<0> q_int<0> net2<6> VDD ++ VSS / RSC_IHPSG13_DFNQMX2IX1 +XI11<8> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI11<7> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI11<6> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI11<5> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI11<4> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI11<3> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI11<2> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI11<1> VDD VSS / RSC_IHPSG13_FILLCAP8 +.ENDS + +.SUBCKT RM_IHPSG13_256x8_c3_1P_COLDRV13X8 ADDR_COL_I<1> ADDR_COL_I<0> ADDR_COL_O<1> ++ ADDR_COL_O<0> ADDR_DEC_I<7> ADDR_DEC_I<6> ADDR_DEC_I<5> ADDR_DEC_I<4> ++ ADDR_DEC_I<3> ADDR_DEC_I<2> ADDR_DEC_I<1> ADDR_DEC_I<0> ADDR_DEC_O<7> ++ ADDR_DEC_O<6> ADDR_DEC_O<5> ADDR_DEC_O<4> ADDR_DEC_O<3> ADDR_DEC_O<2> ++ ADDR_DEC_O<1> ADDR_DEC_O<0> DCLK_I DCLK_O RCLK_I RCLK_O WCLK_I WCLK_O ++ VDD VSS +XI0<1> VDD VSS / RSC_IHPSG13_FILLCAP4 +XI0<0> VDD VSS / RSC_IHPSG13_FILLCAP4 +XADDR_COL_DRV<1> ADDR_COL_I<1> ADDR_COL_O<1> VDD VSS / ++ RSC_IHPSG13_CBUFX8 +XADDR_COL_DRV<0> ADDR_COL_I<0> ADDR_COL_O<0> VDD VSS / ++ RSC_IHPSG13_CBUFX8 +XADDR_DEC_DRV<7> ADDR_DEC_I<7> ADDR_DEC_O<7> VDD VSS / ++ RSC_IHPSG13_CBUFX8 +XADDR_DEC_DRV<6> ADDR_DEC_I<6> ADDR_DEC_O<6> VDD VSS / ++ RSC_IHPSG13_CBUFX8 +XADDR_DEC_DRV<5> ADDR_DEC_I<5> ADDR_DEC_O<5> VDD VSS / ++ RSC_IHPSG13_CBUFX8 +XADDR_DEC_DRV<4> ADDR_DEC_I<4> ADDR_DEC_O<4> VDD VSS / ++ RSC_IHPSG13_CBUFX8 +XADDR_DEC_DRV<3> ADDR_DEC_I<3> ADDR_DEC_O<3> VDD VSS / ++ RSC_IHPSG13_CBUFX8 +XADDR_DEC_DRV<2> ADDR_DEC_I<2> ADDR_DEC_O<2> VDD VSS / ++ RSC_IHPSG13_CBUFX8 +XADDR_DEC_DRV<1> ADDR_DEC_I<1> ADDR_DEC_O<1> VDD VSS / ++ RSC_IHPSG13_CBUFX8 +XADDR_DEC_DRV<0> ADDR_DEC_I<0> ADDR_DEC_O<0> VDD VSS / ++ RSC_IHPSG13_CBUFX8 +XDCLK_DRV DCLK_I DCLK_O VDD VSS / RSC_IHPSG13_CBUFX8 +XRCLK_DRV RCLK_I RCLK_O VDD VSS / RSC_IHPSG13_CBUFX8 +XWCLK_DRV WCLK_I WCLK_O VDD VSS / RSC_IHPSG13_CBUFX8 +.ENDS +.SUBCKT RM_IHPSG13_256x8_c3_1P_WLDRV16X8 A<15> A<14> A<13> A<12> A<11> A<10> A<9> A<8> ++ A<7> A<6> A<5> A<4> A<3> A<2> A<1> A<0> Z<15> Z<14> Z<13> Z<12> Z<11> Z<10> ++ Z<9> Z<8> Z<7> Z<6> Z<5> Z<4> Z<3> Z<2> Z<1> Z<0> VDD VSS +XBUF<15> A<15> Z<15> VDD VSS / RSC_IHPSG13_WLDRVX8 +XBUF<14> A<14> Z<14> VDD VSS / RSC_IHPSG13_WLDRVX8 +XBUF<13> A<13> Z<13> VDD VSS / RSC_IHPSG13_WLDRVX8 +XBUF<12> A<12> Z<12> VDD VSS / RSC_IHPSG13_WLDRVX8 +XBUF<11> A<11> Z<11> VDD VSS / RSC_IHPSG13_WLDRVX8 +XBUF<10> A<10> Z<10> VDD VSS / RSC_IHPSG13_WLDRVX8 +XBUF<9> A<9> Z<9> VDD VSS / RSC_IHPSG13_WLDRVX8 +XBUF<8> A<8> Z<8> VDD VSS / RSC_IHPSG13_WLDRVX8 +XBUF<7> A<7> Z<7> VDD VSS / RSC_IHPSG13_WLDRVX8 +XBUF<6> A<6> Z<6> VDD VSS / RSC_IHPSG13_WLDRVX8 +XBUF<5> A<5> Z<5> VDD VSS / RSC_IHPSG13_WLDRVX8 +XBUF<4> A<4> Z<4> VDD VSS / RSC_IHPSG13_WLDRVX8 +XBUF<3> A<3> Z<3> VDD VSS / RSC_IHPSG13_WLDRVX8 +XBUF<2> A<2> Z<2> VDD VSS / RSC_IHPSG13_WLDRVX8 +XBUF<1> A<1> Z<1> VDD VSS / RSC_IHPSG13_WLDRVX8 +XBUF<0> A<0> Z<0> VDD VSS / RSC_IHPSG13_WLDRVX8 +.ENDS + + + +.SUBCKT RM_IHPSG13_256x8_c3_1P_ROWDEC6 ADDR_N_I<5> ADDR_N_I<4> ADDR_N_I<3> ADDR_N_I<2> ++ ADDR_N_I<1> ADDR_N_I<0> CS_I ECLK_I WL_O<63> WL_O<62> WL_O<61> WL_O<60> ++ WL_O<59> WL_O<58> WL_O<57> WL_O<56> WL_O<55> WL_O<54> WL_O<53> WL_O<52> ++ WL_O<51> WL_O<50> WL_O<49> WL_O<48> WL_O<47> WL_O<46> WL_O<45> WL_O<44> ++ WL_O<43> WL_O<42> WL_O<41> WL_O<40> WL_O<39> WL_O<38> WL_O<37> WL_O<36> ++ WL_O<35> WL_O<34> WL_O<33> WL_O<32> WL_O<31> WL_O<30> WL_O<29> WL_O<28> ++ WL_O<27> WL_O<26> WL_O<25> WL_O<24> WL_O<23> WL_O<22> WL_O<21> WL_O<20> ++ WL_O<19> WL_O<18> WL_O<17> WL_O<16> WL_O<15> WL_O<14> WL_O<13> WL_O<12> ++ WL_O<11> WL_O<10> WL_O<9> WL_O<8> WL_O<7> WL_O<6> WL_O<5> WL_O<4> WL_O<3> ++ WL_O<2> WL_O<1> WL_O<0> VDD VSS +XDEC11 ADDR_N_I<5> ADDR_N_I<4> CS_I CS00<3> VDD VSS / ++ RM_IHPSG13_256x8_c3_1P_DEC03 +XDEC00 ADDR_N_I<5> ADDR_N_I<4> CS_I CS00<0> VDD VSS / ++ RM_IHPSG13_256x8_c3_1P_DEC00 +XDEC01 ADDR_N_I<5> ADDR_N_I<4> CS_I CS00<1> VDD VSS / ++ RM_IHPSG13_256x8_c3_1P_DEC01 +XDEC10 ADDR_N_I<5> ADDR_N_I<4> CS_I CS00<2> VDD VSS / ++ RM_IHPSG13_256x8_c3_1P_DEC02 +XSEL<3> ADDR_N_I<3> ADDR_N_I<2> ADDR_N_I<1> ADDR_N_I<0> CS00<3> ECLK_H<3> ++ ECLK_H<4> ECLK_B<3> ECLK_B<4> WL_O<63> WL_O<62> WL_O<61> WL_O<60> WL_O<59> ++ WL_O<58> WL_O<57> WL_O<56> WL_O<55> WL_O<54> WL_O<53> WL_O<52> WL_O<51> ++ WL_O<50> WL_O<49> WL_O<48> VDD VSS / RM_IHPSG13_256x8_c3_1P_DEC04 +XSEL<2> ADDR_N_I<3> ADDR_N_I<2> ADDR_N_I<1> ADDR_N_I<0> CS00<2> ECLK_H<2> ++ ECLK_H<3> ECLK_B<2> ECLK_B<3> WL_O<47> WL_O<46> WL_O<45> WL_O<44> WL_O<43> ++ WL_O<42> WL_O<41> WL_O<40> WL_O<39> WL_O<38> WL_O<37> WL_O<36> WL_O<35> ++ WL_O<34> WL_O<33> WL_O<32> VDD VSS / RM_IHPSG13_256x8_c3_1P_DEC04 +XSEL<1> ADDR_N_I<3> ADDR_N_I<2> ADDR_N_I<1> ADDR_N_I<0> CS00<1> ECLK_H<1> ++ ECLK_H<2> ECLK_B<1> ECLK_B<2> WL_O<31> WL_O<30> WL_O<29> WL_O<28> WL_O<27> ++ WL_O<26> WL_O<25> WL_O<24> WL_O<23> WL_O<22> WL_O<21> WL_O<20> WL_O<19> ++ WL_O<18> WL_O<17> WL_O<16> VDD VSS / RM_IHPSG13_256x8_c3_1P_DEC04 +XSEL<0> ADDR_N_I<3> ADDR_N_I<2> ADDR_N_I<1> ADDR_N_I<0> CS00<0> ECLK_I ++ ECLK_H<1> ECLK_B<0> ECLK_B<1> WL_O<15> WL_O<14> WL_O<13> WL_O<12> WL_O<11> ++ WL_O<10> WL_O<9> WL_O<8> WL_O<7> WL_O<6> WL_O<5> WL_O<4> WL_O<3> WL_O<2> ++ WL_O<1> WL_O<0> VDD VSS / RM_IHPSG13_256x8_c3_1P_DEC04 +XL2<24> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<23> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<22> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<21> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<20> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<19> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<18> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<17> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<16> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<15> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<14> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<13> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<12> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<11> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<10> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<9> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<8> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<7> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<6> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<5> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<4> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<3> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<2> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<1> VDD VSS / RSC_IHPSG13_FILLCAP8 +.ENDS +.SUBCKT RM_IHPSG13_256x8_c3_1P_ROWREG6 ACLK_N_I ADDR_I<5> ADDR_I<4> ADDR_I<3> ADDR_I<2> ++ ADDR_I<1> ADDR_I<0> ADDR_N_O<5> ADDR_N_O<4> ADDR_N_O<3> ADDR_N_O<2> ++ ADDR_N_O<1> ADDR_N_O<0> BIST_ADDR_I<5> BIST_ADDR_I<4> BIST_ADDR_I<3> ++ BIST_ADDR_I<2> BIST_ADDR_I<1> BIST_ADDR_I<0> BIST_EN_I VDD VSS +XINV<5> q_int<5> qn_int<5> VDD VSS / RSC_IHPSG13_CINVX2 +XINV<4> q_int<4> qn_int<4> VDD VSS / RSC_IHPSG13_CINVX2 +XINV<3> q_int<3> qn_int<3> VDD VSS / RSC_IHPSG13_CINVX2 +XINV<2> q_int<2> qn_int<2> VDD VSS / RSC_IHPSG13_CINVX2 +XINV<1> q_int<1> qn_int<1> VDD VSS / RSC_IHPSG13_CINVX2 +XINV<0> q_int<0> qn_int<0> VDD VSS / RSC_IHPSG13_CINVX2 +XDRV<5> qn_int<5> ADDR_N_O<5> VDD VSS / RSC_IHPSG13_CINVX8 +XDRV<4> qn_int<4> ADDR_N_O<4> VDD VSS / RSC_IHPSG13_CINVX8 +XDRV<3> qn_int<3> ADDR_N_O<3> VDD VSS / RSC_IHPSG13_CINVX8 +XDRV<2> qn_int<2> ADDR_N_O<2> VDD VSS / RSC_IHPSG13_CINVX8 +XDRV<1> qn_int<1> ADDR_N_O<1> VDD VSS / RSC_IHPSG13_CINVX8 +XDRV<0> qn_int<0> ADDR_N_O<0> VDD VSS / RSC_IHPSG13_CINVX8 +XDFF<5> BIST_EN_I BIST_ADDR_I<5> ACLK_N_I ADDR_I<5> q_int<5> net2<0> VDD ++ VSS / RSC_IHPSG13_DFNQMX2IX1 +XDFF<4> BIST_EN_I BIST_ADDR_I<4> ACLK_N_I ADDR_I<4> q_int<4> net2<1> VDD ++ VSS / RSC_IHPSG13_DFNQMX2IX1 +XDFF<3> BIST_EN_I BIST_ADDR_I<3> ACLK_N_I ADDR_I<3> q_int<3> net2<2> VDD ++ VSS / RSC_IHPSG13_DFNQMX2IX1 +XDFF<2> BIST_EN_I BIST_ADDR_I<2> ACLK_N_I ADDR_I<2> q_int<2> net2<3> VDD ++ VSS / RSC_IHPSG13_DFNQMX2IX1 +XDFF<1> BIST_EN_I BIST_ADDR_I<1> ACLK_N_I ADDR_I<1> q_int<1> net2<4> VDD ++ VSS / RSC_IHPSG13_DFNQMX2IX1 +XDFF<0> BIST_EN_I BIST_ADDR_I<0> ACLK_N_I ADDR_I<0> q_int<0> net2<5> VDD ++ VSS / RSC_IHPSG13_DFNQMX2IX1 +XI11<12> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI11<11> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI11<10> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI11<9> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI11<8> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI11<7> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI11<6> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI11<5> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI11<4> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI11<3> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI11<2> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI11<1> VDD VSS / RSC_IHPSG13_FILLCAP8 +.ENDS + + +.SUBCKT RM_IHPSG13_256x8_c3_1P_COLUMN_pcell_0 A_BLC_BOT<1> A_BLC_BOT<0> A_BLC_TOP<1> A_BLC_TOP<0> A_BLT_BOT<1> A_BLT_BOT<0> A_BLT_TOP<1> A_BLT_TOP<0> A_LWL<31> A_LWL<30> A_LWL<29> A_LWL<28> A_LWL<27> A_LWL<26> A_LWL<25> A_LWL<24> A_LWL<23> A_LWL<22> A_LWL<21> A_LWL<20> A_LWL<19> A_LWL<18> A_LWL<17> A_LWL<16> A_LWL<15> A_LWL<14> A_LWL<13> A_LWL<12> A_LWL<11> A_LWL<10> A_LWL<9> A_LWL<8> A_LWL<7> A_LWL<6> A_LWL<5> A_LWL<4> A_LWL<3> A_LWL<2> A_LWL<1> A_LWL<0> A_RWL<31> A_RWL<30> A_RWL<29> A_RWL<28> A_RWL<27> A_RWL<26> A_RWL<25> A_RWL<24> A_RWL<23> A_RWL<22> A_RWL<21> A_RWL<20> A_RWL<19> A_RWL<18> A_RWL<17> A_RWL<16> A_RWL<15> A_RWL<14> A_RWL<13> A_RWL<12> A_RWL<11> A_RWL<10> A_RWL<9> A_RWL<8> A_RWL<7> A_RWL<6> A_RWL<5> A_RWL<4> A_RWL<3> A_RWL<2> A_RWL<1> A_RWL<0> VDD_CORE VSS +XRAM<2> A_BLC<1> A_BLC<0> A_BLC_TOP<1> A_BLC_TOP<0> A_BLT<1> A_BLT<0> A_BLT_TOP<1> A_BLT_TOP<0> A_LWL<31> A_LWL<30> A_LWL<29> A_LWL<28> A_LWL<27> A_LWL<26> A_LWL<25> A_LWL<24> A_LWL<23> A_LWL<22> A_LWL<21> A_LWL<20> A_LWL<19> A_LWL<18> A_LWL<17> A_LWL<16> A_RWL<31> A_RWL<30> A_RWL<29> A_RWL<28> A_RWL<27> A_RWL<26> A_RWL<25> A_RWL<24> A_RWL<23> A_RWL<22> A_RWL<21> A_RWL<20> A_RWL<19> A_RWL<18> A_RWL<17> A_RWL<16> VDD_CORE VSS / RM_IHPSG13_256x8_c3_1P_BITKIT_16x2_SRAM +XRAM<1> A_BLC_BOT<1> A_BLC_BOT<0> A_BLC<1> A_BLC<0> A_BLT_BOT<1> A_BLT_BOT<0> A_BLT<1> A_BLT<0> A_LWL<15> A_LWL<14> A_LWL<13> A_LWL<12> A_LWL<11> A_LWL<10> A_LWL<9> A_LWL<8> A_LWL<7> A_LWL<6> A_LWL<5> A_LWL<4> A_LWL<3> A_LWL<2> A_LWL<1> A_LWL<0> A_RWL<15> A_RWL<14> A_RWL<13> A_RWL<12> A_RWL<11> A_RWL<10> A_RWL<9> A_RWL<8> A_RWL<7> A_RWL<6> A_RWL<5> A_RWL<4> A_RWL<3> A_RWL<2> A_RWL<1> A_RWL<0> VDD_CORE VSS / RM_IHPSG13_256x8_c3_1P_BITKIT_16x2_SRAM +XEDGE<1> A_BLC_TOP<1> A_BLC_TOP<0> A_BLT_TOP<1> A_BLT_TOP<0> VDD_CORE VSS / RM_IHPSG13_256x8_c3_1P_BITKIT_16x2_EDGE_TB +XEDGE<0> A_BLC_BOT<1> A_BLC_BOT<0> A_BLT_BOT<1> A_BLT_BOT<0> VDD_CORE VSS / RM_IHPSG13_256x8_c3_1P_BITKIT_16x2_EDGE_TB +.ENDS + + + + +.SUBCKT RM_IHPSG13_256x8_c3_1P_MATRIX_pcell_1 A_BLC<31> A_BLC<30> A_BLC<29> A_BLC<28> A_BLC<27> A_BLC<26> A_BLC<25> A_BLC<24> A_BLC<23> A_BLC<22> A_BLC<21> A_BLC<20> A_BLC<19> A_BLC<18> A_BLC<17> A_BLC<16> A_BLC<15> A_BLC<14> A_BLC<13> A_BLC<12> A_BLC<11> A_BLC<10> A_BLC<9> A_BLC<8> A_BLC<7> A_BLC<6> A_BLC<5> A_BLC<4> A_BLC<3> A_BLC<2> A_BLC<1> A_BLC<0> A_BLT<31> A_BLT<30> A_BLT<29> A_BLT<28> A_BLT<27> A_BLT<26> A_BLT<25> A_BLT<24> A_BLT<23> A_BLT<22> A_BLT<21> A_BLT<20> A_BLT<19> A_BLT<18> A_BLT<17> A_BLT<16> A_BLT<15> A_BLT<14> A_BLT<13> A_BLT<12> A_BLT<11> A_BLT<10> A_BLT<9> A_BLT<8> A_BLT<7> A_BLT<6> A_BLT<5> A_BLT<4> A_BLT<3> A_BLT<2> A_BLT<1> A_BLT<0> A_WL<31> A_WL<30> A_WL<29> A_WL<28> A_WL<27> A_WL<26> A_WL<25> A_WL<24> A_WL<23> A_WL<22> A_WL<21> A_WL<20> A_WL<19> A_WL<18> A_WL<17> A_WL<16> A_WL<15> A_WL<14> A_WL<13> A_WL<12> A_WL<11> A_WL<10> A_WL<9> A_WL<8> A_WL<7> A_WL<6> A_WL<5> A_WL<4> A_WL<3> A_WL<2> A_WL<1> A_WL<0> VDD_CORE VSS +XCORNER<3> VDD_CORE VSS / RM_IHPSG13_256x8_c3_1P_BITKIT_16x2_CORNER +XCORNER<2> VDD_CORE VSS / RM_IHPSG13_256x8_c3_1P_BITKIT_16x2_CORNER +XCORNER<1> VDD_CORE VSS / RM_IHPSG13_256x8_c3_1P_BITKIT_16x2_CORNER +XCORNER<0> VDD_CORE VSS / RM_IHPSG13_256x8_c3_1P_BITKIT_16x2_CORNER +XRAMEDGE_L<1> A_WL<31> A_WL<30> A_WL<29> A_WL<28> A_WL<27> A_WL<26> A_WL<25> A_WL<24> A_WL<23> A_WL<22> A_WL<21> A_WL<20> A_WL<19> A_WL<18> A_WL<17> A_WL<16> VDD_CORE VSS / RM_IHPSG13_256x8_c3_1P_BITKIT_16x2_EDGE_LR +XRAMEDGE_L<0> A_WL<15> A_WL<14> A_WL<13> A_WL<12> A_WL<11> A_WL<10> A_WL<9> A_WL<8> A_WL<7> A_WL<6> A_WL<5> A_WL<4> A_WL<3> A_WL<2> A_WL<1> A_WL<0> VDD_CORE VSS / RM_IHPSG13_256x8_c3_1P_BITKIT_16x2_EDGE_LR +XRAMEDGE_R<1> A_IWL<511> A_IWL<510> A_IWL<509> A_IWL<508> A_IWL<507> A_IWL<506> A_IWL<505> A_IWL<504> A_IWL<503> A_IWL<502> A_IWL<501> A_IWL<500> A_IWL<499> A_IWL<498> A_IWL<497> A_IWL<496> VDD_CORE VSS / RM_IHPSG13_256x8_c3_1P_BITKIT_16x2_EDGE_LR +XRAMEDGE_R<0> A_IWL<495> A_IWL<494> A_IWL<493> A_IWL<492> A_IWL<491> A_IWL<490> A_IWL<489> A_IWL<488> A_IWL<487> A_IWL<486> A_IWL<485> A_IWL<484> A_IWL<483> A_IWL<482> A_IWL<481> A_IWL<480> VDD_CORE VSS / RM_IHPSG13_256x8_c3_1P_BITKIT_16x2_EDGE_LR +XCOL<15> A_BLC<31> A_BLC<30> A_BLC_TOP<31> A_BLC_TOP<30> A_BLT<31> A_BLT<30> A_BLT_TOP<31> A_BLT_TOP<30> A_IWL<479> A_IWL<478> A_IWL<477> A_IWL<476> A_IWL<475> A_IWL<474> A_IWL<473> A_IWL<472> A_IWL<471> A_IWL<470> A_IWL<469> A_IWL<468> A_IWL<467> A_IWL<466> A_IWL<465> A_IWL<464> A_IWL<463> A_IWL<462> A_IWL<461> A_IWL<460> A_IWL<459> A_IWL<458> A_IWL<457> A_IWL<456> A_IWL<455> A_IWL<454> A_IWL<453> A_IWL<452> A_IWL<451> A_IWL<450> A_IWL<449> A_IWL<448> A_IWL<511> A_IWL<510> A_IWL<509> A_IWL<508> A_IWL<507> A_IWL<506> A_IWL<505> A_IWL<504> A_IWL<503> A_IWL<502> A_IWL<501> A_IWL<500> A_IWL<499> A_IWL<498> A_IWL<497> A_IWL<496> A_IWL<495> A_IWL<494> A_IWL<493> A_IWL<492> A_IWL<491> A_IWL<490> A_IWL<489> A_IWL<488> A_IWL<487> A_IWL<486> A_IWL<485> A_IWL<484> A_IWL<483> A_IWL<482> A_IWL<481> A_IWL<480> VDD_CORE VSS / RM_IHPSG13_256x8_c3_1P_COLUMN_pcell_0 +XCOL<14> A_BLC<29> A_BLC<28> A_BLC_TOP<29> A_BLC_TOP<28> A_BLT<29> A_BLT<28> A_BLT_TOP<29> A_BLT_TOP<28> A_IWL<447> A_IWL<446> A_IWL<445> A_IWL<444> A_IWL<443> A_IWL<442> A_IWL<441> A_IWL<440> A_IWL<439> A_IWL<438> A_IWL<437> A_IWL<436> A_IWL<435> A_IWL<434> A_IWL<433> A_IWL<432> A_IWL<431> A_IWL<430> A_IWL<429> A_IWL<428> A_IWL<427> A_IWL<426> A_IWL<425> A_IWL<424> A_IWL<423> A_IWL<422> A_IWL<421> A_IWL<420> A_IWL<419> A_IWL<418> A_IWL<417> A_IWL<416> A_IWL<479> A_IWL<478> A_IWL<477> A_IWL<476> A_IWL<475> A_IWL<474> A_IWL<473> A_IWL<472> A_IWL<471> A_IWL<470> A_IWL<469> A_IWL<468> A_IWL<467> A_IWL<466> A_IWL<465> A_IWL<464> A_IWL<463> A_IWL<462> A_IWL<461> A_IWL<460> A_IWL<459> A_IWL<458> A_IWL<457> A_IWL<456> A_IWL<455> A_IWL<454> A_IWL<453> A_IWL<452> A_IWL<451> A_IWL<450> A_IWL<449> A_IWL<448> VDD_CORE VSS / RM_IHPSG13_256x8_c3_1P_COLUMN_pcell_0 +XCOL<13> A_BLC<27> A_BLC<26> A_BLC_TOP<27> A_BLC_TOP<26> A_BLT<27> A_BLT<26> A_BLT_TOP<27> A_BLT_TOP<26> A_IWL<415> A_IWL<414> A_IWL<413> A_IWL<412> A_IWL<411> A_IWL<410> A_IWL<409> A_IWL<408> A_IWL<407> A_IWL<406> A_IWL<405> A_IWL<404> A_IWL<403> A_IWL<402> A_IWL<401> A_IWL<400> A_IWL<399> A_IWL<398> A_IWL<397> A_IWL<396> A_IWL<395> A_IWL<394> A_IWL<393> A_IWL<392> A_IWL<391> A_IWL<390> A_IWL<389> A_IWL<388> A_IWL<387> A_IWL<386> A_IWL<385> A_IWL<384> A_IWL<447> A_IWL<446> A_IWL<445> A_IWL<444> A_IWL<443> A_IWL<442> A_IWL<441> A_IWL<440> A_IWL<439> A_IWL<438> A_IWL<437> A_IWL<436> A_IWL<435> A_IWL<434> A_IWL<433> A_IWL<432> A_IWL<431> A_IWL<430> A_IWL<429> A_IWL<428> A_IWL<427> A_IWL<426> A_IWL<425> A_IWL<424> A_IWL<423> A_IWL<422> A_IWL<421> A_IWL<420> A_IWL<419> A_IWL<418> A_IWL<417> A_IWL<416> VDD_CORE VSS / RM_IHPSG13_256x8_c3_1P_COLUMN_pcell_0 +XCOL<12> A_BLC<25> A_BLC<24> A_BLC_TOP<25> A_BLC_TOP<24> A_BLT<25> A_BLT<24> A_BLT_TOP<25> A_BLT_TOP<24> A_IWL<383> A_IWL<382> A_IWL<381> A_IWL<380> A_IWL<379> A_IWL<378> A_IWL<377> A_IWL<376> A_IWL<375> A_IWL<374> A_IWL<373> A_IWL<372> A_IWL<371> A_IWL<370> A_IWL<369> A_IWL<368> A_IWL<367> A_IWL<366> A_IWL<365> A_IWL<364> A_IWL<363> A_IWL<362> A_IWL<361> A_IWL<360> A_IWL<359> A_IWL<358> A_IWL<357> A_IWL<356> A_IWL<355> A_IWL<354> A_IWL<353> A_IWL<352> A_IWL<415> A_IWL<414> A_IWL<413> A_IWL<412> A_IWL<411> A_IWL<410> A_IWL<409> A_IWL<408> A_IWL<407> A_IWL<406> A_IWL<405> A_IWL<404> A_IWL<403> A_IWL<402> A_IWL<401> A_IWL<400> A_IWL<399> A_IWL<398> A_IWL<397> A_IWL<396> A_IWL<395> A_IWL<394> A_IWL<393> A_IWL<392> A_IWL<391> A_IWL<390> A_IWL<389> A_IWL<388> A_IWL<387> A_IWL<386> A_IWL<385> A_IWL<384> VDD_CORE VSS / RM_IHPSG13_256x8_c3_1P_COLUMN_pcell_0 +XCOL<11> A_BLC<23> A_BLC<22> A_BLC_TOP<23> A_BLC_TOP<22> A_BLT<23> A_BLT<22> A_BLT_TOP<23> A_BLT_TOP<22> A_IWL<351> A_IWL<350> A_IWL<349> A_IWL<348> A_IWL<347> A_IWL<346> A_IWL<345> A_IWL<344> A_IWL<343> A_IWL<342> A_IWL<341> A_IWL<340> A_IWL<339> A_IWL<338> A_IWL<337> A_IWL<336> A_IWL<335> A_IWL<334> A_IWL<333> A_IWL<332> A_IWL<331> A_IWL<330> A_IWL<329> A_IWL<328> A_IWL<327> A_IWL<326> A_IWL<325> A_IWL<324> A_IWL<323> A_IWL<322> A_IWL<321> A_IWL<320> A_IWL<383> A_IWL<382> A_IWL<381> A_IWL<380> A_IWL<379> A_IWL<378> A_IWL<377> A_IWL<376> A_IWL<375> A_IWL<374> A_IWL<373> A_IWL<372> A_IWL<371> A_IWL<370> A_IWL<369> A_IWL<368> A_IWL<367> A_IWL<366> A_IWL<365> A_IWL<364> A_IWL<363> A_IWL<362> A_IWL<361> A_IWL<360> A_IWL<359> A_IWL<358> A_IWL<357> A_IWL<356> A_IWL<355> A_IWL<354> A_IWL<353> A_IWL<352> VDD_CORE VSS / RM_IHPSG13_256x8_c3_1P_COLUMN_pcell_0 +XCOL<10> A_BLC<21> A_BLC<20> A_BLC_TOP<21> A_BLC_TOP<20> A_BLT<21> A_BLT<20> A_BLT_TOP<21> A_BLT_TOP<20> A_IWL<319> A_IWL<318> A_IWL<317> A_IWL<316> A_IWL<315> A_IWL<314> A_IWL<313> A_IWL<312> A_IWL<311> A_IWL<310> A_IWL<309> A_IWL<308> A_IWL<307> A_IWL<306> A_IWL<305> A_IWL<304> A_IWL<303> A_IWL<302> A_IWL<301> A_IWL<300> A_IWL<299> A_IWL<298> A_IWL<297> A_IWL<296> A_IWL<295> A_IWL<294> A_IWL<293> A_IWL<292> A_IWL<291> A_IWL<290> A_IWL<289> A_IWL<288> A_IWL<351> A_IWL<350> A_IWL<349> A_IWL<348> A_IWL<347> A_IWL<346> A_IWL<345> A_IWL<344> A_IWL<343> A_IWL<342> A_IWL<341> A_IWL<340> A_IWL<339> A_IWL<338> A_IWL<337> A_IWL<336> A_IWL<335> A_IWL<334> A_IWL<333> A_IWL<332> A_IWL<331> A_IWL<330> A_IWL<329> A_IWL<328> A_IWL<327> A_IWL<326> A_IWL<325> A_IWL<324> A_IWL<323> A_IWL<322> A_IWL<321> A_IWL<320> VDD_CORE VSS / RM_IHPSG13_256x8_c3_1P_COLUMN_pcell_0 +XCOL<9> A_BLC<19> A_BLC<18> A_BLC_TOP<19> A_BLC_TOP<18> A_BLT<19> A_BLT<18> A_BLT_TOP<19> A_BLT_TOP<18> A_IWL<287> A_IWL<286> A_IWL<285> A_IWL<284> A_IWL<283> A_IWL<282> A_IWL<281> A_IWL<280> A_IWL<279> A_IWL<278> A_IWL<277> A_IWL<276> A_IWL<275> A_IWL<274> A_IWL<273> A_IWL<272> A_IWL<271> A_IWL<270> A_IWL<269> A_IWL<268> A_IWL<267> A_IWL<266> A_IWL<265> A_IWL<264> A_IWL<263> A_IWL<262> A_IWL<261> A_IWL<260> A_IWL<259> A_IWL<258> A_IWL<257> A_IWL<256> A_IWL<319> A_IWL<318> A_IWL<317> A_IWL<316> A_IWL<315> A_IWL<314> A_IWL<313> A_IWL<312> A_IWL<311> A_IWL<310> A_IWL<309> A_IWL<308> A_IWL<307> A_IWL<306> A_IWL<305> A_IWL<304> A_IWL<303> A_IWL<302> A_IWL<301> A_IWL<300> A_IWL<299> A_IWL<298> A_IWL<297> A_IWL<296> A_IWL<295> A_IWL<294> A_IWL<293> A_IWL<292> A_IWL<291> A_IWL<290> A_IWL<289> A_IWL<288> VDD_CORE VSS / RM_IHPSG13_256x8_c3_1P_COLUMN_pcell_0 +XCOL<8> A_BLC<17> A_BLC<16> A_BLC_TOP<17> A_BLC_TOP<16> A_BLT<17> A_BLT<16> A_BLT_TOP<17> A_BLT_TOP<16> A_IWL<255> A_IWL<254> A_IWL<253> A_IWL<252> A_IWL<251> A_IWL<250> A_IWL<249> A_IWL<248> A_IWL<247> A_IWL<246> A_IWL<245> A_IWL<244> A_IWL<243> A_IWL<242> A_IWL<241> A_IWL<240> A_IWL<239> A_IWL<238> A_IWL<237> A_IWL<236> A_IWL<235> A_IWL<234> A_IWL<233> A_IWL<232> A_IWL<231> A_IWL<230> A_IWL<229> A_IWL<228> A_IWL<227> A_IWL<226> A_IWL<225> A_IWL<224> A_IWL<287> A_IWL<286> A_IWL<285> A_IWL<284> A_IWL<283> A_IWL<282> A_IWL<281> A_IWL<280> A_IWL<279> A_IWL<278> A_IWL<277> A_IWL<276> A_IWL<275> A_IWL<274> A_IWL<273> A_IWL<272> A_IWL<271> A_IWL<270> A_IWL<269> A_IWL<268> A_IWL<267> A_IWL<266> A_IWL<265> A_IWL<264> A_IWL<263> A_IWL<262> A_IWL<261> A_IWL<260> A_IWL<259> A_IWL<258> A_IWL<257> A_IWL<256> VDD_CORE VSS / RM_IHPSG13_256x8_c3_1P_COLUMN_pcell_0 +XCOL<7> A_BLC<15> A_BLC<14> A_BLC_TOP<15> A_BLC_TOP<14> A_BLT<15> A_BLT<14> A_BLT_TOP<15> A_BLT_TOP<14> A_IWL<223> A_IWL<222> A_IWL<221> A_IWL<220> A_IWL<219> A_IWL<218> A_IWL<217> A_IWL<216> A_IWL<215> A_IWL<214> A_IWL<213> A_IWL<212> A_IWL<211> A_IWL<210> A_IWL<209> A_IWL<208> A_IWL<207> A_IWL<206> A_IWL<205> A_IWL<204> A_IWL<203> A_IWL<202> A_IWL<201> A_IWL<200> A_IWL<199> A_IWL<198> A_IWL<197> A_IWL<196> A_IWL<195> A_IWL<194> A_IWL<193> A_IWL<192> A_IWL<255> A_IWL<254> A_IWL<253> A_IWL<252> A_IWL<251> A_IWL<250> A_IWL<249> A_IWL<248> A_IWL<247> A_IWL<246> A_IWL<245> A_IWL<244> A_IWL<243> A_IWL<242> A_IWL<241> A_IWL<240> A_IWL<239> A_IWL<238> A_IWL<237> A_IWL<236> A_IWL<235> A_IWL<234> A_IWL<233> A_IWL<232> A_IWL<231> A_IWL<230> A_IWL<229> A_IWL<228> A_IWL<227> A_IWL<226> A_IWL<225> A_IWL<224> VDD_CORE VSS / RM_IHPSG13_256x8_c3_1P_COLUMN_pcell_0 +XCOL<6> A_BLC<13> A_BLC<12> A_BLC_TOP<13> A_BLC_TOP<12> A_BLT<13> A_BLT<12> A_BLT_TOP<13> A_BLT_TOP<12> A_IWL<191> A_IWL<190> A_IWL<189> A_IWL<188> A_IWL<187> A_IWL<186> A_IWL<185> A_IWL<184> A_IWL<183> A_IWL<182> A_IWL<181> A_IWL<180> A_IWL<179> A_IWL<178> A_IWL<177> A_IWL<176> A_IWL<175> A_IWL<174> A_IWL<173> A_IWL<172> A_IWL<171> A_IWL<170> A_IWL<169> A_IWL<168> A_IWL<167> A_IWL<166> A_IWL<165> A_IWL<164> A_IWL<163> A_IWL<162> A_IWL<161> A_IWL<160> A_IWL<223> A_IWL<222> A_IWL<221> A_IWL<220> A_IWL<219> A_IWL<218> A_IWL<217> A_IWL<216> A_IWL<215> A_IWL<214> A_IWL<213> A_IWL<212> A_IWL<211> A_IWL<210> A_IWL<209> A_IWL<208> A_IWL<207> A_IWL<206> A_IWL<205> A_IWL<204> A_IWL<203> A_IWL<202> A_IWL<201> A_IWL<200> A_IWL<199> A_IWL<198> A_IWL<197> A_IWL<196> A_IWL<195> A_IWL<194> A_IWL<193> A_IWL<192> VDD_CORE VSS / RM_IHPSG13_256x8_c3_1P_COLUMN_pcell_0 +XCOL<5> A_BLC<11> A_BLC<10> A_BLC_TOP<11> A_BLC_TOP<10> A_BLT<11> A_BLT<10> A_BLT_TOP<11> A_BLT_TOP<10> A_IWL<159> A_IWL<158> A_IWL<157> A_IWL<156> A_IWL<155> A_IWL<154> A_IWL<153> A_IWL<152> A_IWL<151> A_IWL<150> A_IWL<149> A_IWL<148> A_IWL<147> A_IWL<146> A_IWL<145> A_IWL<144> A_IWL<143> A_IWL<142> A_IWL<141> A_IWL<140> A_IWL<139> A_IWL<138> A_IWL<137> A_IWL<136> A_IWL<135> A_IWL<134> A_IWL<133> A_IWL<132> A_IWL<131> A_IWL<130> A_IWL<129> A_IWL<128> A_IWL<191> A_IWL<190> A_IWL<189> A_IWL<188> A_IWL<187> A_IWL<186> A_IWL<185> A_IWL<184> A_IWL<183> A_IWL<182> A_IWL<181> A_IWL<180> A_IWL<179> A_IWL<178> A_IWL<177> A_IWL<176> A_IWL<175> A_IWL<174> A_IWL<173> A_IWL<172> A_IWL<171> A_IWL<170> A_IWL<169> A_IWL<168> A_IWL<167> A_IWL<166> A_IWL<165> A_IWL<164> A_IWL<163> A_IWL<162> A_IWL<161> A_IWL<160> VDD_CORE VSS / RM_IHPSG13_256x8_c3_1P_COLUMN_pcell_0 +XCOL<4> A_BLC<9> A_BLC<8> A_BLC_TOP<9> A_BLC_TOP<8> A_BLT<9> A_BLT<8> A_BLT_TOP<9> A_BLT_TOP<8> A_IWL<127> A_IWL<126> A_IWL<125> A_IWL<124> A_IWL<123> A_IWL<122> A_IWL<121> A_IWL<120> A_IWL<119> A_IWL<118> A_IWL<117> A_IWL<116> A_IWL<115> A_IWL<114> A_IWL<113> A_IWL<112> A_IWL<111> A_IWL<110> A_IWL<109> A_IWL<108> A_IWL<107> A_IWL<106> A_IWL<105> A_IWL<104> A_IWL<103> A_IWL<102> A_IWL<101> A_IWL<100> A_IWL<99> A_IWL<98> A_IWL<97> A_IWL<96> A_IWL<159> A_IWL<158> A_IWL<157> A_IWL<156> A_IWL<155> A_IWL<154> A_IWL<153> A_IWL<152> A_IWL<151> A_IWL<150> A_IWL<149> A_IWL<148> A_IWL<147> A_IWL<146> A_IWL<145> A_IWL<144> A_IWL<143> A_IWL<142> A_IWL<141> A_IWL<140> A_IWL<139> A_IWL<138> A_IWL<137> A_IWL<136> A_IWL<135> A_IWL<134> A_IWL<133> A_IWL<132> A_IWL<131> A_IWL<130> A_IWL<129> A_IWL<128> VDD_CORE VSS / RM_IHPSG13_256x8_c3_1P_COLUMN_pcell_0 +XCOL<3> A_BLC<7> A_BLC<6> A_BLC_TOP<7> A_BLC_TOP<6> A_BLT<7> A_BLT<6> A_BLT_TOP<7> A_BLT_TOP<6> A_IWL<95> A_IWL<94> A_IWL<93> A_IWL<92> A_IWL<91> A_IWL<90> A_IWL<89> A_IWL<88> A_IWL<87> A_IWL<86> A_IWL<85> A_IWL<84> A_IWL<83> A_IWL<82> A_IWL<81> A_IWL<80> A_IWL<79> A_IWL<78> A_IWL<77> A_IWL<76> A_IWL<75> A_IWL<74> A_IWL<73> A_IWL<72> A_IWL<71> A_IWL<70> A_IWL<69> A_IWL<68> A_IWL<67> A_IWL<66> A_IWL<65> A_IWL<64> A_IWL<127> A_IWL<126> A_IWL<125> A_IWL<124> A_IWL<123> A_IWL<122> A_IWL<121> A_IWL<120> A_IWL<119> A_IWL<118> A_IWL<117> A_IWL<116> A_IWL<115> A_IWL<114> A_IWL<113> A_IWL<112> A_IWL<111> A_IWL<110> A_IWL<109> A_IWL<108> A_IWL<107> A_IWL<106> A_IWL<105> A_IWL<104> A_IWL<103> A_IWL<102> A_IWL<101> A_IWL<100> A_IWL<99> A_IWL<98> A_IWL<97> A_IWL<96> VDD_CORE VSS / RM_IHPSG13_256x8_c3_1P_COLUMN_pcell_0 +XCOL<2> A_BLC<5> A_BLC<4> A_BLC_TOP<5> A_BLC_TOP<4> A_BLT<5> A_BLT<4> A_BLT_TOP<5> A_BLT_TOP<4> A_IWL<63> A_IWL<62> A_IWL<61> A_IWL<60> A_IWL<59> A_IWL<58> A_IWL<57> A_IWL<56> A_IWL<55> A_IWL<54> A_IWL<53> A_IWL<52> A_IWL<51> A_IWL<50> A_IWL<49> A_IWL<48> A_IWL<47> A_IWL<46> A_IWL<45> A_IWL<44> A_IWL<43> A_IWL<42> A_IWL<41> A_IWL<40> A_IWL<39> A_IWL<38> A_IWL<37> A_IWL<36> A_IWL<35> A_IWL<34> A_IWL<33> A_IWL<32> A_IWL<95> A_IWL<94> A_IWL<93> A_IWL<92> A_IWL<91> A_IWL<90> A_IWL<89> A_IWL<88> A_IWL<87> A_IWL<86> A_IWL<85> A_IWL<84> A_IWL<83> A_IWL<82> A_IWL<81> A_IWL<80> A_IWL<79> A_IWL<78> A_IWL<77> A_IWL<76> A_IWL<75> A_IWL<74> A_IWL<73> A_IWL<72> A_IWL<71> A_IWL<70> A_IWL<69> A_IWL<68> A_IWL<67> A_IWL<66> A_IWL<65> A_IWL<64> VDD_CORE VSS / RM_IHPSG13_256x8_c3_1P_COLUMN_pcell_0 +XCOL<1> A_BLC<3> A_BLC<2> A_BLC_TOP<3> A_BLC_TOP<2> A_BLT<3> A_BLT<2> A_BLT_TOP<3> A_BLT_TOP<2> A_IWL<31> A_IWL<30> A_IWL<29> A_IWL<28> A_IWL<27> A_IWL<26> A_IWL<25> A_IWL<24> A_IWL<23> A_IWL<22> A_IWL<21> A_IWL<20> A_IWL<19> A_IWL<18> A_IWL<17> A_IWL<16> A_IWL<15> A_IWL<14> A_IWL<13> A_IWL<12> A_IWL<11> A_IWL<10> A_IWL<9> A_IWL<8> A_IWL<7> A_IWL<6> A_IWL<5> A_IWL<4> A_IWL<3> A_IWL<2> A_IWL<1> A_IWL<0> A_IWL<63> A_IWL<62> A_IWL<61> A_IWL<60> A_IWL<59> A_IWL<58> A_IWL<57> A_IWL<56> A_IWL<55> A_IWL<54> A_IWL<53> A_IWL<52> A_IWL<51> A_IWL<50> A_IWL<49> A_IWL<48> A_IWL<47> A_IWL<46> A_IWL<45> A_IWL<44> A_IWL<43> A_IWL<42> A_IWL<41> A_IWL<40> A_IWL<39> A_IWL<38> A_IWL<37> A_IWL<36> A_IWL<35> A_IWL<34> A_IWL<33> A_IWL<32> VDD_CORE VSS / RM_IHPSG13_256x8_c3_1P_COLUMN_pcell_0 +XCOL<0> A_BLC<1> A_BLC<0> A_BLC_TOP<1> A_BLC_TOP<0> A_BLT<1> A_BLT<0> A_BLT_TOP<1> A_BLT_TOP<0> A_WL<31> A_WL<30> A_WL<29> A_WL<28> A_WL<27> A_WL<26> A_WL<25> A_WL<24> A_WL<23> A_WL<22> A_WL<21> A_WL<20> A_WL<19> A_WL<18> A_WL<17> A_WL<16> A_WL<15> A_WL<14> A_WL<13> A_WL<12> A_WL<11> A_WL<10> A_WL<9> A_WL<8> A_WL<7> A_WL<6> A_WL<5> A_WL<4> A_WL<3> A_WL<2> A_WL<1> A_WL<0> A_IWL<31> A_IWL<30> A_IWL<29> A_IWL<28> A_IWL<27> A_IWL<26> A_IWL<25> A_IWL<24> A_IWL<23> A_IWL<22> A_IWL<21> A_IWL<20> A_IWL<19> A_IWL<18> A_IWL<17> A_IWL<16> A_IWL<15> A_IWL<14> A_IWL<13> A_IWL<12> A_IWL<11> A_IWL<10> A_IWL<9> A_IWL<8> A_IWL<7> A_IWL<6> A_IWL<5> A_IWL<4> A_IWL<3> A_IWL<2> A_IWL<1> A_IWL<0> VDD_CORE VSS / RM_IHPSG13_256x8_c3_1P_COLUMN_pcell_0 +.ENDS + + + + +.SUBCKT RM_IHPSG13_256x8_c3_1P_DLY_pcell_2 A Z VDD VSS + XIDL D<7> Z VDD VSS / RSC_IHPSG13_CDLYX1 + XIDM<7> D<6> D<7> VDD VSS / RSC_IHPSG13_CDLYX1_DUMMY + XIDM<6> D<5> D<6> VDD VSS / RSC_IHPSG13_CDLYX1_DUMMY + XIDM<5> D<4> D<5> VDD VSS / RSC_IHPSG13_CDLYX1_DUMMY + XIDM<4> D<3> D<4> VDD VSS / RSC_IHPSG13_CDLYX1_DUMMY + XIDM<3> D<2> D<3> VDD VSS / RSC_IHPSG13_CDLYX1_DUMMY + XIDM<2> D<1> D<2> VDD VSS / RSC_IHPSG13_CDLYX1_DUMMY + XIDM<1> A D<1> VDD VSS / RSC_IHPSG13_CDLYX1_DUMMY +.ENDS + + +.SUBCKT RM_IHPSG13_256x8_c3_1P_DLY_pcell_3 A Z VDD VSS + XIDM<8> D<7> Z VDD VSS / RSC_IHPSG13_CDLYX1_DUMMY + XIDM<7> D<6> D<7> VDD VSS / RSC_IHPSG13_CDLYX1_DUMMY + XIDM<6> D<5> D<6> VDD VSS / RSC_IHPSG13_CDLYX1_DUMMY + XIDM<5> D<4> D<5> VDD VSS / RSC_IHPSG13_CDLYX1_DUMMY + XIDM<4> D<3> D<4> VDD VSS / RSC_IHPSG13_CDLYX1_DUMMY + XIDM<3> D<2> D<3> VDD VSS / RSC_IHPSG13_CDLYX1_DUMMY + XIDM<2> D<1> D<2> VDD VSS / RSC_IHPSG13_CDLYX1_DUMMY + XIDM<1> A D<1> VDD VSS / RSC_IHPSG13_CDLYX1_DUMMY +.ENDS + + + +.SUBCKT RM_IHPSG13_1P_256x8_c3_bm_bist A_ADDR<7> A_ADDR<6> A_ADDR<5> A_ADDR<4> A_ADDR<3> A_ADDR<2> A_ADDR<1> A_ADDR<0> A_BIST_ADDR<7> A_BIST_ADDR<6> A_BIST_ADDR<5> A_BIST_ADDR<4> A_BIST_ADDR<3> A_BIST_ADDR<2> A_BIST_ADDR<1> A_BIST_ADDR<0> A_BIST_BM<7> A_BIST_BM<6> A_BIST_BM<5> A_BIST_BM<4> A_BIST_BM<3> A_BIST_BM<2> A_BIST_BM<1> A_BIST_BM<0> A_BIST_CLK A_BIST_DIN<7> A_BIST_DIN<6> A_BIST_DIN<5> A_BIST_DIN<4> A_BIST_DIN<3> A_BIST_DIN<2> A_BIST_DIN<1> A_BIST_DIN<0> A_BIST_EN A_BIST_MEN A_BIST_REN A_BIST_WEN A_BM<7> A_BM<6> A_BM<5> A_BM<4> A_BM<3> A_BM<2> A_BM<1> A_BM<0> A_CLK A_DIN<7> A_DIN<6> A_DIN<5> A_DIN<4> A_DIN<3> A_DIN<2> A_DIN<1> A_DIN<0> A_DLY A_DOUT<7> A_DOUT<6> A_DOUT<5> A_DOUT<4> A_DOUT<3> A_DOUT<2> A_DOUT<1> A_DOUT<0> A_MEN A_REN A_WEN VDD! VDDARRAY! VSS! + + +XRAM<1> a_blc_r<31> a_blc_r<30> a_blc_r<29> a_blc_r<28> a_blc_r<27> a_blc_r<26> a_blc_r<25> a_blc_r<24> a_blc_r<23> a_blc_r<22> a_blc_r<21> a_blc_r<20> a_blc_r<19> a_blc_r<18> a_blc_r<17> a_blc_r<16> a_blc_r<15> a_blc_r<14> a_blc_r<13> a_blc_r<12> a_blc_r<11> a_blc_r<10> a_blc_r<9> a_blc_r<8> a_blc_r<7> a_blc_r<6> a_blc_r<5> a_blc_r<4> a_blc_r<3> a_blc_r<2> a_blc_r<1> a_blc_r<0> a_blt_r<31> a_blt_r<30> a_blt_r<29> a_blt_r<28> a_blt_r<27> a_blt_r<26> a_blt_r<25> a_blt_r<24> a_blt_r<23> a_blt_r<22> a_blt_r<21> a_blt_r<20> a_blt_r<19> a_blt_r<18> a_blt_r<17> a_blt_r<16> a_blt_r<15> a_blt_r<14> a_blt_r<13> a_blt_r<12> a_blt_r<11> a_blt_r<10> a_blt_r<9> a_blt_r<8> a_blt_r<7> a_blt_r<6> a_blt_r<5> a_blt_r<4> a_blt_r<3> a_blt_r<2> a_blt_r<1> a_blt_r<0> a_wl_r<31> a_wl_r<30> a_wl_r<29> a_wl_r<28> a_wl_r<27> a_wl_r<26> a_wl_r<25> a_wl_r<24> a_wl_r<23> a_wl_r<22> a_wl_r<21> a_wl_r<20> a_wl_r<19> a_wl_r<18> a_wl_r<17> a_wl_r<16> a_wl_r<15> a_wl_r<14> a_wl_r<13> a_wl_r<12> a_wl_r<11> a_wl_r<10> a_wl_r<9> a_wl_r<8> a_wl_r<7> a_wl_r<6> a_wl_r<5> a_wl_r<4> a_wl_r<3> a_wl_r<2> a_wl_r<1> a_wl_r<0> VDDARRAY! VSS! / RM_IHPSG13_256x8_c3_1P_MATRIX_pcell_1 +XRAM<0> a_blc_l<31> a_blc_l<30> a_blc_l<29> a_blc_l<28> a_blc_l<27> a_blc_l<26> a_blc_l<25> a_blc_l<24> a_blc_l<23> a_blc_l<22> a_blc_l<21> a_blc_l<20> a_blc_l<19> a_blc_l<18> a_blc_l<17> a_blc_l<16> a_blc_l<15> a_blc_l<14> a_blc_l<13> a_blc_l<12> a_blc_l<11> a_blc_l<10> a_blc_l<9> a_blc_l<8> a_blc_l<7> a_blc_l<6> a_blc_l<5> a_blc_l<4> a_blc_l<3> a_blc_l<2> a_blc_l<1> a_blc_l<0> a_blt_l<31> a_blt_l<30> a_blt_l<29> a_blt_l<28> a_blt_l<27> a_blt_l<26> a_blt_l<25> a_blt_l<24> a_blt_l<23> a_blt_l<22> a_blt_l<21> a_blt_l<20> a_blt_l<19> a_blt_l<18> a_blt_l<17> a_blt_l<16> a_blt_l<15> a_blt_l<14> a_blt_l<13> a_blt_l<12> a_blt_l<11> a_blt_l<10> a_blt_l<9> a_blt_l<8> a_blt_l<7> a_blt_l<6> a_blt_l<5> a_blt_l<4> a_blt_l<3> a_blt_l<2> a_blt_l<1> a_blt_l<0> a_wl_l<31> a_wl_l<30> a_wl_l<29> a_wl_l<28> a_wl_l<27> a_wl_l<26> a_wl_l<25> a_wl_l<24> a_wl_l<23> a_wl_l<22> a_wl_l<21> a_wl_l<20> a_wl_l<19> a_wl_l<18> a_wl_l<17> a_wl_l<16> a_wl_l<15> a_wl_l<14> a_wl_l<13> a_wl_l<12> a_wl_l<11> a_wl_l<10> a_wl_l<9> a_wl_l<8> a_wl_l<7> a_wl_l<6> a_wl_l<5> a_wl_l<4> a_wl_l<3> a_wl_l<2> a_wl_l<1> a_wl_l<0> VDDARRAY! VSS! / RM_IHPSG13_256x8_c3_1P_MATRIX_pcell_1 + + +XA_COLDRV<1> a_addr_col<1> a_addr_col<0> a_addr_col_r<1> a_addr_col_r<0> a_addr_dec<7> a_addr_dec<6> a_addr_dec<5> a_addr_dec<4> a_addr_dec<3> a_addr_dec<2> a_addr_dec<1> a_addr_dec<0> a_addr_dec_r<7> a_addr_dec_r<6> a_addr_dec_r<5> a_addr_dec_r<4> a_addr_dec_r<3> a_addr_dec_r<2> a_addr_dec_r<1> a_addr_dec_r<0> a_dclk a_dclk_p_r<0> a_rclk a_rclk_p_r<0> a_wclk a_wclk_p_r<0> VDD! VSS! / RM_IHPSG13_256x8_c3_1P_COLDRV13X4 +XA_COLDRV<0> a_addr_col<1> a_addr_col<0> a_addr_col_l<1> a_addr_col_l<0> a_addr_dec<7> a_addr_dec<6> a_addr_dec<5> a_addr_dec<4> a_addr_dec<3> a_addr_dec<2> a_addr_dec<1> a_addr_dec<0> a_addr_dec_l<7> a_addr_dec_l<6> a_addr_dec_l<5> a_addr_dec_l<4> a_addr_dec_l<3> a_addr_dec_l<2> a_addr_dec_l<1> a_addr_dec_l<0> a_dclk a_dclk_p_l<0> a_rclk a_rclk_p_l<0> a_wclk a_wclk_p_l<0> VDD! VSS! / RM_IHPSG13_256x8_c3_1P_COLDRV13X4 + + +XA_WLDRV<3> a_wi<31> a_wi<30> a_wi<29> a_wi<28> a_wi<27> a_wi<26> a_wi<25> a_wi<24> a_wi<23> a_wi<22> a_wi<21> a_wi<20> a_wi<19> a_wi<18> a_wi<17> a_wi<16> a_wl_r<31> a_wl_r<30> a_wl_r<29> a_wl_r<28> a_wl_r<27> a_wl_r<26> a_wl_r<25> a_wl_r<24> a_wl_r<23> a_wl_r<22> a_wl_r<21> a_wl_r<20> a_wl_r<19> a_wl_r<18> a_wl_r<17> a_wl_r<16> VDD! VSS! / RM_IHPSG13_256x8_c3_1P_WLDRV16X4 +XA_WLDRV<2> a_wi<15> a_wi<14> a_wi<13> a_wi<12> a_wi<11> a_wi<10> a_wi<9> a_wi<8> a_wi<7> a_wi<6> a_wi<5> a_wi<4> a_wi<3> a_wi<2> a_wi<1> a_wi<0> a_wl_r<15> a_wl_r<14> a_wl_r<13> a_wl_r<12> a_wl_r<11> a_wl_r<10> a_wl_r<9> a_wl_r<8> a_wl_r<7> a_wl_r<6> a_wl_r<5> a_wl_r<4> a_wl_r<3> a_wl_r<2> a_wl_r<1> a_wl_r<0> VDD! VSS! / RM_IHPSG13_256x8_c3_1P_WLDRV16X4 +XA_WLDRV<1> a_wi<31> a_wi<30> a_wi<29> a_wi<28> a_wi<27> a_wi<26> a_wi<25> a_wi<24> a_wi<23> a_wi<22> a_wi<21> a_wi<20> a_wi<19> a_wi<18> a_wi<17> a_wi<16> a_wl_l<31> a_wl_l<30> a_wl_l<29> a_wl_l<28> a_wl_l<27> a_wl_l<26> a_wl_l<25> a_wl_l<24> a_wl_l<23> a_wl_l<22> a_wl_l<21> a_wl_l<20> a_wl_l<19> a_wl_l<18> a_wl_l<17> a_wl_l<16> VDD! VSS! / RM_IHPSG13_256x8_c3_1P_WLDRV16X4 +XA_WLDRV<0> a_wi<15> a_wi<14> a_wi<13> a_wi<12> a_wi<11> a_wi<10> a_wi<9> a_wi<8> a_wi<7> a_wi<6> a_wi<5> a_wi<4> a_wi<3> a_wi<2> a_wi<1> a_wi<0> a_wl_l<15> a_wl_l<14> a_wl_l<13> a_wl_l<12> a_wl_l<11> a_wl_l<10> a_wl_l<9> a_wl_l<8> a_wl_l<7> a_wl_l<6> a_wl_l<5> a_wl_l<4> a_wl_l<3> a_wl_l<2> a_wl_l<1> a_wl_l<0> VDD! VSS! / RM_IHPSG13_256x8_c3_1P_WLDRV16X4 + + +XA_CTRL a_aclk_n A_BIST_CLK A_BIST_MEN A_BIST_EN A_BIST_REN A_BIST_WEN a_tiel A_CLK A_MEN a_dclk a_eclk a_pulse_h a_pulse_l a_pulse a_rclk A_REN a_cs a_wclk A_WEN VDD! VSS! / RM_IHPSG13_256x8_c3_1P_CTRL + + +XA_ROWDEC a_addr_row<4> a_addr_row<3> a_addr_row<2> a_addr_row<1> a_addr_row<0> a_cs a_eclk a_wi<31> a_wi<30> a_wi<29> a_wi<28> a_wi<27> a_wi<26> a_wi<25> a_wi<24> a_wi<23> a_wi<22> a_wi<21> a_wi<20> a_wi<19> a_wi<18> a_wi<17> a_wi<16> a_wi<15> a_wi<14> a_wi<13> a_wi<12> a_wi<11> a_wi<10> a_wi<9> a_wi<8> a_wi<7> a_wi<6> a_wi<5> a_wi<4> a_wi<3> a_wi<2> a_wi<1> a_wi<0> VDD! VSS! / RM_IHPSG13_256x8_c3_1P_ROWDEC5 +XA_ROWREG a_aclk_n A_ADDR<7> A_ADDR<6> A_ADDR<5> A_ADDR<4> A_ADDR<3> a_addr_row<4> a_addr_row<3> a_addr_row<2> a_addr_row<1> a_addr_row<0> A_BIST_ADDR<7> A_BIST_ADDR<6> A_BIST_ADDR<5> A_BIST_ADDR<4> A_BIST_ADDR<3> A_BIST_EN VDD! VSS! / RM_IHPSG13_256x8_c3_1P_ROWREG5 +XA_COLDEC a_aclk_n A_ADDR<2> A_ADDR<1> A_ADDR<0> a_addr_col<1> a_addr_col<0> a_addr_dec<7> a_addr_dec<6> a_addr_dec<5> a_addr_dec<4> a_addr_dec<3> a_addr_dec<2> a_addr_dec<1> a_addr_dec<0> A_BIST_ADDR<2> A_BIST_ADDR<1> A_BIST_ADDR<0> A_BIST_EN VDD! VSS! / RM_IHPSG13_256x8_c3_1P_COLDEC3 + + +XA_DLYH a_pulse a_pulse_h VDD! VSS! / RM_IHPSG13_256x8_c3_1P_DLY_pcell_2 +XA_DLYL a_pulse_x a_pulse_l VDD! VSS! / RM_IHPSG13_256x8_c3_1P_DLY_pcell_3 +XA_DLYMUX a_pulse_h A_DLY a_pulse_x VDD! VSS! / RM_IHPSG13_256x8_c3_1P_DLY_MUX + +XCOLCTRL<7> a_addr_dec_r<7> a_addr_dec_r<6> a_addr_dec_r<5> a_addr_dec_r<4> a_addr_dec_r<3> a_addr_dec_r<2> a_addr_dec_r<1> a_addr_dec_r<0> A_BIST_BM<7> A_BIST_DIN<7> A_BIST_EN a_blc_r<31> a_blc_r<30> a_blc_r<29> a_blc_r<28> a_blc_r<27> a_blc_r<26> a_blc_r<25> a_blc_r<24> a_blt_r<31> a_blt_r<30> a_blt_r<29> a_blt_r<28> a_blt_r<27> a_blt_r<26> a_blt_r<25> a_blt_r<24> A_BM<7> a_dclk_n_r<3> a_dclk_n_r<4> a_dclk_p_r<3> a_dclk_p_r<4> A_DOUT<7> A_DIN<7> a_rclk_n_r<3> a_rclk_n_r<4> a_rclk_p_r<3> a_rclk_p_r<4> a_tieh<7> a_wclk_n_r<3> a_wclk_n_r<4> a_wclk_p_r<3> a_wclk_p_r<4> VDD! VSS! / RM_IHPSG13_256x8_c3_1P_COLCTRL3 +XCOLCTRL<6> a_addr_dec_r<7> a_addr_dec_r<6> a_addr_dec_r<5> a_addr_dec_r<4> a_addr_dec_r<3> a_addr_dec_r<2> a_addr_dec_r<1> a_addr_dec_r<0> A_BIST_BM<6> A_BIST_DIN<6> A_BIST_EN a_blc_r<23> a_blc_r<22> a_blc_r<21> a_blc_r<20> a_blc_r<19> a_blc_r<18> a_blc_r<17> a_blc_r<16> a_blt_r<23> a_blt_r<22> a_blt_r<21> a_blt_r<20> a_blt_r<19> a_blt_r<18> a_blt_r<17> a_blt_r<16> A_BM<6> a_dclk_n_r<2> a_dclk_n_r<3> a_dclk_p_r<2> a_dclk_p_r<3> A_DOUT<6> A_DIN<6> a_rclk_n_r<2> a_rclk_n_r<3> a_rclk_p_r<2> a_rclk_p_r<3> a_tieh<6> a_wclk_n_r<2> a_wclk_n_r<3> a_wclk_p_r<2> a_wclk_p_r<3> VDD! VSS! / RM_IHPSG13_256x8_c3_1P_COLCTRL3 +XCOLCTRL<5> a_addr_dec_r<7> a_addr_dec_r<6> a_addr_dec_r<5> a_addr_dec_r<4> a_addr_dec_r<3> a_addr_dec_r<2> a_addr_dec_r<1> a_addr_dec_r<0> A_BIST_BM<5> A_BIST_DIN<5> A_BIST_EN a_blc_r<15> a_blc_r<14> a_blc_r<13> a_blc_r<12> a_blc_r<11> a_blc_r<10> a_blc_r<9> a_blc_r<8> a_blt_r<15> a_blt_r<14> a_blt_r<13> a_blt_r<12> a_blt_r<11> a_blt_r<10> a_blt_r<9> a_blt_r<8> A_BM<5> a_dclk_n_r<1> a_dclk_n_r<2> a_dclk_p_r<1> a_dclk_p_r<2> A_DOUT<5> A_DIN<5> a_rclk_n_r<1> a_rclk_n_r<2> a_rclk_p_r<1> a_rclk_p_r<2> a_tieh<5> a_wclk_n_r<1> a_wclk_n_r<2> a_wclk_p_r<1> a_wclk_p_r<2> VDD! VSS! / RM_IHPSG13_256x8_c3_1P_COLCTRL3 +XCOLCTRL<4> a_addr_dec_r<7> a_addr_dec_r<6> a_addr_dec_r<5> a_addr_dec_r<4> a_addr_dec_r<3> a_addr_dec_r<2> a_addr_dec_r<1> a_addr_dec_r<0> A_BIST_BM<4> A_BIST_DIN<4> A_BIST_EN a_blc_r<7> a_blc_r<6> a_blc_r<5> a_blc_r<4> a_blc_r<3> a_blc_r<2> a_blc_r<1> a_blc_r<0> a_blt_r<7> a_blt_r<6> a_blt_r<5> a_blt_r<4> a_blt_r<3> a_blt_r<2> a_blt_r<1> a_blt_r<0> A_BM<4> a_dclk_n_r<0> a_dclk_n_r<1> a_dclk_p_r<0> a_dclk_p_r<1> A_DOUT<4> A_DIN<4> a_rclk_n_r<0> a_rclk_n_r<1> a_rclk_p_r<0> a_rclk_p_r<1> a_tieh<4> a_wclk_n_r<0> a_wclk_n_r<1> a_wclk_p_r<0> a_wclk_p_r<1> VDD! VSS! / RM_IHPSG13_256x8_c3_1P_COLCTRL3 +XCOLCTRL<3> a_addr_dec_l<7> a_addr_dec_l<6> a_addr_dec_l<5> a_addr_dec_l<4> a_addr_dec_l<3> a_addr_dec_l<2> a_addr_dec_l<1> a_addr_dec_l<0> A_BIST_BM<0> A_BIST_DIN<0> A_BIST_EN a_blc_l<31> a_blc_l<30> a_blc_l<29> a_blc_l<28> a_blc_l<27> a_blc_l<26> a_blc_l<25> a_blc_l<24> a_blt_l<31> a_blt_l<30> a_blt_l<29> a_blt_l<28> a_blt_l<27> a_blt_l<26> a_blt_l<25> a_blt_l<24> A_BM<0> a_dclk_n_l<3> a_dclk_n_l<4> a_dclk_p_l<3> a_dclk_p_l<4> A_DOUT<0> A_DIN<0> a_rclk_n_l<3> a_rclk_n_l<4> a_rclk_p_l<3> a_rclk_p_l<4> a_tieh<0> a_wclk_n_l<3> a_wclk_n_l<4> a_wclk_p_l<3> a_wclk_p_l<4> VDD! VSS! / RM_IHPSG13_256x8_c3_1P_COLCTRL3 +XCOLCTRL<2> a_addr_dec_l<7> a_addr_dec_l<6> a_addr_dec_l<5> a_addr_dec_l<4> a_addr_dec_l<3> a_addr_dec_l<2> a_addr_dec_l<1> a_addr_dec_l<0> A_BIST_BM<1> A_BIST_DIN<1> A_BIST_EN a_blc_l<23> a_blc_l<22> a_blc_l<21> a_blc_l<20> a_blc_l<19> a_blc_l<18> a_blc_l<17> a_blc_l<16> a_blt_l<23> a_blt_l<22> a_blt_l<21> a_blt_l<20> a_blt_l<19> a_blt_l<18> a_blt_l<17> a_blt_l<16> A_BM<1> a_dclk_n_l<2> a_dclk_n_l<3> a_dclk_p_l<2> a_dclk_p_l<3> A_DOUT<1> A_DIN<1> a_rclk_n_l<2> a_rclk_n_l<3> a_rclk_p_l<2> a_rclk_p_l<3> a_tieh<1> a_wclk_n_l<2> a_wclk_n_l<3> a_wclk_p_l<2> a_wclk_p_l<3> VDD! VSS! / RM_IHPSG13_256x8_c3_1P_COLCTRL3 +XCOLCTRL<1> a_addr_dec_l<7> a_addr_dec_l<6> a_addr_dec_l<5> a_addr_dec_l<4> a_addr_dec_l<3> a_addr_dec_l<2> a_addr_dec_l<1> a_addr_dec_l<0> A_BIST_BM<2> A_BIST_DIN<2> A_BIST_EN a_blc_l<15> a_blc_l<14> a_blc_l<13> a_blc_l<12> a_blc_l<11> a_blc_l<10> a_blc_l<9> a_blc_l<8> a_blt_l<15> a_blt_l<14> a_blt_l<13> a_blt_l<12> a_blt_l<11> a_blt_l<10> a_blt_l<9> a_blt_l<8> A_BM<2> a_dclk_n_l<1> a_dclk_n_l<2> a_dclk_p_l<1> a_dclk_p_l<2> A_DOUT<2> A_DIN<2> a_rclk_n_l<1> a_rclk_n_l<2> a_rclk_p_l<1> a_rclk_p_l<2> a_tieh<2> a_wclk_n_l<1> a_wclk_n_l<2> a_wclk_p_l<1> a_wclk_p_l<2> VDD! VSS! / RM_IHPSG13_256x8_c3_1P_COLCTRL3 +XCOLCTRL<0> a_addr_dec_l<7> a_addr_dec_l<6> a_addr_dec_l<5> a_addr_dec_l<4> a_addr_dec_l<3> a_addr_dec_l<2> a_addr_dec_l<1> a_addr_dec_l<0> A_BIST_BM<3> A_BIST_DIN<3> A_BIST_EN a_blc_l<7> a_blc_l<6> a_blc_l<5> a_blc_l<4> a_blc_l<3> a_blc_l<2> a_blc_l<1> a_blc_l<0> a_blt_l<7> a_blt_l<6> a_blt_l<5> a_blt_l<4> a_blt_l<3> a_blt_l<2> a_blt_l<1> a_blt_l<0> A_BM<3> a_dclk_n_l<0> a_dclk_n_l<1> a_dclk_p_l<0> a_dclk_p_l<1> A_DOUT<3> A_DIN<3> a_rclk_n_l<0> a_rclk_n_l<1> a_rclk_p_l<0> a_rclk_p_l<1> a_tieh<3> a_wclk_n_l<0> a_wclk_n_l<1> a_wclk_p_l<0> a_wclk_p_l<1> VDD! VSS! / RM_IHPSG13_256x8_c3_1P_COLCTRL3 + + +XDRVFILL4<1> VDD! VSS! / RM_IHPSG13_256x8_c3_1P_COLDRV13_FILL4 +XDRVFILL4<2> VDD! VSS! / RM_IHPSG13_256x8_c3_1P_COLDRV13_FILL4 +.ENDS diff --git a/flow/platforms/ihp-sg13g2/cdl/RM_IHPSG13_1P_512x16_c2_bm_bist.cdl b/flow/platforms/ihp-sg13g2/cdl/RM_IHPSG13_1P_512x16_c2_bm_bist.cdl new file mode 100644 index 0000000000..8caa25b7e1 --- /dev/null +++ b/flow/platforms/ihp-sg13g2/cdl/RM_IHPSG13_1P_512x16_c2_bm_bist.cdl @@ -0,0 +1,6351 @@ +* ------------------------------------------------------ +* +* Copyright 2025 IHP PDK Authors +* +* Licensed under the Apache License, Version 2.0 (the "License"); +* you may not use this file except in compliance with the License. +* You may obtain a copy of the License at +* +* https://www.apache.org/licenses/LICENSE-2.0 +* +* Unless required by applicable law or agreed to in writing, software +* distributed under the License is distributed on an "AS IS" BASIS, +* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +* See the License for the specific language governing permissions and +* limitations under the License. +* +* Generated on Wed Aug 27 12:16:38 2025 +* +* ------------------------------------------------------ + +.SUBCKT RM_IHPSG13_512x16_c2_1P_BITKIT_CORNER NW PW VDD VSS +.ENDS +.SUBCKT RM_IHPSG13_512x16_c2_1P_BITKIT_16x2_CORNER VDD_CORE VSS +XI16 VDD_CORE VSS VDD_CORE VSS / ++ RM_IHPSG13_512x16_c2_1P_BITKIT_CORNER +.ENDS +.SUBCKT RM_IHPSG13_512x16_c2_1P_BITKIT_EDGE_LR LWL NW PW VDD VSS +MN1 VSS LWL VSS VSS sg13_lv_nmos m=1 w=300.0n l=130.00n ng=1 nrd=0 nrs=0 +MN0 VSS net9 VSS VSS sg13_lv_nmos m=1 w=300.0n l=130.00n ng=1 nrd=0 nrs=0 +.ENDS +.SUBCKT RM_IHPSG13_512x16_c2_1P_BITKIT_16x2_EDGE_LR A_WL<15> A_WL<14> A_WL<13> A_WL<12> ++ A_WL<11> A_WL<10> A_WL<9> A_WL<8> A_WL<7> A_WL<6> A_WL<5> A_WL<4> A_WL<3> ++ A_WL<2> A_WL<1> A_WL<0> VDD_CORE VSS +XI0<15> A_WL<15> VDD_CORE VSS VDD_CORE VSS / ++ RM_IHPSG13_512x16_c2_1P_BITKIT_EDGE_LR +XI0<14> A_WL<14> VDD_CORE VSS VDD_CORE VSS / ++ RM_IHPSG13_512x16_c2_1P_BITKIT_EDGE_LR +XI0<13> A_WL<13> VDD_CORE VSS VDD_CORE VSS / ++ RM_IHPSG13_512x16_c2_1P_BITKIT_EDGE_LR +XI0<12> A_WL<12> VDD_CORE VSS VDD_CORE VSS / ++ RM_IHPSG13_512x16_c2_1P_BITKIT_EDGE_LR +XI0<11> A_WL<11> VDD_CORE VSS VDD_CORE VSS / ++ RM_IHPSG13_512x16_c2_1P_BITKIT_EDGE_LR +XI0<10> A_WL<10> VDD_CORE VSS VDD_CORE VSS / ++ RM_IHPSG13_512x16_c2_1P_BITKIT_EDGE_LR +XI0<9> A_WL<9> VDD_CORE VSS VDD_CORE VSS / ++ RM_IHPSG13_512x16_c2_1P_BITKIT_EDGE_LR +XI0<8> A_WL<8> VDD_CORE VSS VDD_CORE VSS / ++ RM_IHPSG13_512x16_c2_1P_BITKIT_EDGE_LR +XI0<7> A_WL<7> VDD_CORE VSS VDD_CORE VSS / ++ RM_IHPSG13_512x16_c2_1P_BITKIT_EDGE_LR +XI0<6> A_WL<6> VDD_CORE VSS VDD_CORE VSS / ++ RM_IHPSG13_512x16_c2_1P_BITKIT_EDGE_LR +XI0<5> A_WL<5> VDD_CORE VSS VDD_CORE VSS / ++ RM_IHPSG13_512x16_c2_1P_BITKIT_EDGE_LR +XI0<4> A_WL<4> VDD_CORE VSS VDD_CORE VSS / ++ RM_IHPSG13_512x16_c2_1P_BITKIT_EDGE_LR +XI0<3> A_WL<3> VDD_CORE VSS VDD_CORE VSS / ++ RM_IHPSG13_512x16_c2_1P_BITKIT_EDGE_LR +XI0<2> A_WL<2> VDD_CORE VSS VDD_CORE VSS / ++ RM_IHPSG13_512x16_c2_1P_BITKIT_EDGE_LR +XI0<1> A_WL<1> VDD_CORE VSS VDD_CORE VSS / ++ RM_IHPSG13_512x16_c2_1P_BITKIT_EDGE_LR +XI0<0> A_WL<0> VDD_CORE VSS VDD_CORE VSS / ++ RM_IHPSG13_512x16_c2_1P_BITKIT_EDGE_LR +.ENDS +.SUBCKT RM_IHPSG13_512x16_c2_1P_BITKIT_CELL BLC_BOT BLC_TOP BLT_BOT BLT_TOP LWL NW PW ++ RWL VDD VSS +MN0 NC NT VSS PW sg13_lv_nmos m=1 w=300.0n l=130.00n ng=1 nrd=0 nrs=0 +MN1 NT NC VSS PW sg13_lv_nmos m=1 w=300.0n l=130.00n ng=1 nrd=0 nrs=0 +MN3 NC RWL BLC_TOP PW sg13_lv_nmos m=1 w=300.0n l=130.00n ng=1 nrd=0 nrs=0 +MN2 BLT_BOT LWL NT PW sg13_lv_nmos m=1 w=300.0n l=130.00n ng=1 nrd=0 nrs=0 +MP1 NT NC VDD NW sg13_lv_pmos m=1 w=150.00n l=130.00n ng=1 nrd=0 nrs=0 +MP0 NC NT VDD NW sg13_lv_pmos m=1 w=150.00n l=130.00n ng=1 nrd=0 nrs=0 +R1 BLC_BOT BLC_TOP lvsres w=2.6e-07 l=6e-07 +R0 BLT_BOT BLT_TOP lvsres w=2.6e-07 l=6e-07 +R2 RWL LWL lvsres w=2.6e-07 l=6e-07 +.ENDS +.SUBCKT RM_IHPSG13_512x16_c2_1P_BITKIT_16x2_SRAM A_BLC_BOT<1> A_BLC_BOT<0> A_BLC_TOP<1> ++ A_BLC_TOP<0> A_BLT_BOT<1> A_BLT_BOT<0> A_BLT_TOP<1> A_BLT_TOP<0> A_LWL<15> ++ A_LWL<14> A_LWL<13> A_LWL<12> A_LWL<11> A_LWL<10> A_LWL<9> A_LWL<8> A_LWL<7> ++ A_LWL<6> A_LWL<5> A_LWL<4> A_LWL<3> A_LWL<2> A_LWL<1> A_LWL<0> A_RWL<15> ++ A_RWL<14> A_RWL<13> A_RWL<12> A_RWL<11> A_RWL<10> A_RWL<9> A_RWL<8> A_RWL<7> ++ A_RWL<6> A_RWL<5> A_RWL<4> A_RWL<3> A_RWL<2> A_RWL<1> A_RWL<0> VDD_CORE ++ VSS +XCELL<31> A_BLC_TOP<1> A_RBLC<15> A_BLT_TOP<1> A_RBLT<15> A_RWL<15> ++ VDD_CORE VSS A_XWL<15> VDD_CORE VSS / ++ RM_IHPSG13_512x16_c2_1P_BITKIT_CELL +XCELL<30> A_RBLC<14> A_RBLC<15> A_RBLT<14> A_RBLT<15> A_RWL<14> VDD_CORE ++ VSS A_XWL<14> VDD_CORE VSS / RM_IHPSG13_512x16_c2_1P_BITKIT_CELL +XCELL<29> A_RBLC<14> A_RBLC<13> A_RBLT<14> A_RBLT<13> A_RWL<13> VDD_CORE ++ VSS A_XWL<13> VDD_CORE VSS / RM_IHPSG13_512x16_c2_1P_BITKIT_CELL +XCELL<28> A_RBLC<12> A_RBLC<13> A_RBLT<12> A_RBLT<13> A_RWL<12> VDD_CORE ++ VSS A_XWL<12> VDD_CORE VSS / RM_IHPSG13_512x16_c2_1P_BITKIT_CELL +XCELL<27> A_RBLC<12> A_RBLC<11> A_RBLT<12> A_RBLT<11> A_RWL<11> VDD_CORE ++ VSS A_XWL<11> VDD_CORE VSS / RM_IHPSG13_512x16_c2_1P_BITKIT_CELL +XCELL<26> A_RBLC<10> A_RBLC<11> A_RBLT<10> A_RBLT<11> A_RWL<10> VDD_CORE ++ VSS A_XWL<10> VDD_CORE VSS / RM_IHPSG13_512x16_c2_1P_BITKIT_CELL +XCELL<25> A_RBLC<10> A_RBLC<9> A_RBLT<10> A_RBLT<9> A_RWL<9> VDD_CORE ++ VSS A_XWL<9> VDD_CORE VSS / RM_IHPSG13_512x16_c2_1P_BITKIT_CELL +XCELL<24> A_RBLC<8> A_RBLC<9> A_RBLT<8> A_RBLT<9> A_RWL<8> VDD_CORE ++ VSS A_XWL<8> VDD_CORE VSS / RM_IHPSG13_512x16_c2_1P_BITKIT_CELL +XCELL<23> A_RBLC<8> A_RBLC<7> A_RBLT<8> A_RBLT<7> A_RWL<7> VDD_CORE ++ VSS A_XWL<7> VDD_CORE VSS / RM_IHPSG13_512x16_c2_1P_BITKIT_CELL +XCELL<22> A_RBLC<6> A_RBLC<7> A_RBLT<6> A_RBLT<7> A_RWL<6> VDD_CORE ++ VSS A_XWL<6> VDD_CORE VSS / RM_IHPSG13_512x16_c2_1P_BITKIT_CELL +XCELL<21> A_RBLC<6> A_RBLC<5> A_RBLT<6> A_RBLT<5> A_RWL<5> VDD_CORE ++ VSS A_XWL<5> VDD_CORE VSS / RM_IHPSG13_512x16_c2_1P_BITKIT_CELL +XCELL<20> A_RBLC<4> A_RBLC<5> A_RBLT<4> A_RBLT<5> A_RWL<4> VDD_CORE ++ VSS A_XWL<4> VDD_CORE VSS / RM_IHPSG13_512x16_c2_1P_BITKIT_CELL +XCELL<19> A_RBLC<4> A_RBLC<3> A_RBLT<4> A_RBLT<3> A_RWL<3> VDD_CORE ++ VSS A_XWL<3> VDD_CORE VSS / RM_IHPSG13_512x16_c2_1P_BITKIT_CELL +XCELL<18> A_RBLC<2> A_RBLC<3> A_RBLT<2> A_RBLT<3> A_RWL<2> VDD_CORE ++ VSS A_XWL<2> VDD_CORE VSS / RM_IHPSG13_512x16_c2_1P_BITKIT_CELL +XCELL<17> A_RBLC<2> A_RBLC<1> A_RBLT<2> A_RBLT<1> A_RWL<1> VDD_CORE ++ VSS A_XWL<1> VDD_CORE VSS / RM_IHPSG13_512x16_c2_1P_BITKIT_CELL +XCELL<16> A_BLC_BOT<1> A_RBLC<1> A_BLT_BOT<1> A_RBLT<1> A_RWL<0> VDD_CORE ++ VSS A_XWL<0> VDD_CORE VSS / RM_IHPSG13_512x16_c2_1P_BITKIT_CELL +XCELL<15> A_BLC_TOP<0> A_LBLC<15> A_BLT_TOP<0> A_LBLT<15> A_LWL<15> ++ VDD_CORE VSS A_XWL<15> VDD_CORE VSS / ++ RM_IHPSG13_512x16_c2_1P_BITKIT_CELL +XCELL<14> A_LBLC<14> A_LBLC<15> A_LBLT<14> A_LBLT<15> A_LWL<14> VDD_CORE ++ VSS A_XWL<14> VDD_CORE VSS / RM_IHPSG13_512x16_c2_1P_BITKIT_CELL +XCELL<13> A_LBLC<14> A_LBLC<13> A_LBLT<14> A_LBLT<13> A_LWL<13> VDD_CORE ++ VSS A_XWL<13> VDD_CORE VSS / RM_IHPSG13_512x16_c2_1P_BITKIT_CELL +XCELL<12> A_LBLC<12> A_LBLC<13> A_LBLT<12> A_LBLT<13> A_LWL<12> VDD_CORE ++ VSS A_XWL<12> VDD_CORE VSS / RM_IHPSG13_512x16_c2_1P_BITKIT_CELL +XCELL<11> A_LBLC<12> A_LBLC<11> A_LBLT<12> A_LBLT<11> A_LWL<11> VDD_CORE ++ VSS A_XWL<11> VDD_CORE VSS / RM_IHPSG13_512x16_c2_1P_BITKIT_CELL +XCELL<10> A_LBLC<10> A_LBLC<11> A_LBLT<10> A_LBLT<11> A_LWL<10> VDD_CORE ++ VSS A_XWL<10> VDD_CORE VSS / RM_IHPSG13_512x16_c2_1P_BITKIT_CELL +XCELL<9> A_LBLC<10> A_LBLC<9> A_LBLT<10> A_LBLT<9> A_LWL<9> VDD_CORE ++ VSS A_XWL<9> VDD_CORE VSS / RM_IHPSG13_512x16_c2_1P_BITKIT_CELL +XCELL<8> A_LBLC<8> A_LBLC<9> A_LBLT<8> A_LBLT<9> A_LWL<8> VDD_CORE ++ VSS A_XWL<8> VDD_CORE VSS / RM_IHPSG13_512x16_c2_1P_BITKIT_CELL +XCELL<7> A_LBLC<8> A_LBLC<7> A_LBLT<8> A_LBLT<7> A_LWL<7> VDD_CORE ++ VSS A_XWL<7> VDD_CORE VSS / RM_IHPSG13_512x16_c2_1P_BITKIT_CELL +XCELL<6> A_LBLC<6> A_LBLC<7> A_LBLT<6> A_LBLT<7> A_LWL<6> VDD_CORE ++ VSS A_XWL<6> VDD_CORE VSS / RM_IHPSG13_512x16_c2_1P_BITKIT_CELL +XCELL<5> A_LBLC<6> A_LBLC<5> A_LBLT<6> A_LBLT<5> A_LWL<5> VDD_CORE ++ VSS A_XWL<5> VDD_CORE VSS / RM_IHPSG13_512x16_c2_1P_BITKIT_CELL +XCELL<4> A_LBLC<4> A_LBLC<5> A_LBLT<4> A_LBLT<5> A_LWL<4> VDD_CORE ++ VSS A_XWL<4> VDD_CORE VSS / RM_IHPSG13_512x16_c2_1P_BITKIT_CELL +XCELL<3> A_LBLC<4> A_LBLC<3> A_LBLT<4> A_LBLT<3> A_LWL<3> VDD_CORE ++ VSS A_XWL<3> VDD_CORE VSS / RM_IHPSG13_512x16_c2_1P_BITKIT_CELL +XCELL<2> A_LBLC<2> A_LBLC<3> A_LBLT<2> A_LBLT<3> A_LWL<2> VDD_CORE ++ VSS A_XWL<2> VDD_CORE VSS / RM_IHPSG13_512x16_c2_1P_BITKIT_CELL +XCELL<1> A_LBLC<2> A_LBLC<1> A_LBLT<2> A_LBLT<1> A_LWL<1> VDD_CORE ++ VSS A_XWL<1> VDD_CORE VSS / RM_IHPSG13_512x16_c2_1P_BITKIT_CELL +XCELL<0> A_BLC_BOT<0> A_LBLC<1> A_BLT_BOT<0> A_LBLT<1> A_LWL<0> VDD_CORE ++ VSS A_XWL<0> VDD_CORE VSS / RM_IHPSG13_512x16_c2_1P_BITKIT_CELL +.ENDS +.SUBCKT RM_IHPSG13_512x16_c2_1P_BITKIT_EDGE_TB BLC BLT NW PW VDD VSS +.ENDS +.SUBCKT RM_IHPSG13_512x16_c2_1P_BITKIT_16x2_EDGE_TB A_BLC<1> A_BLC<0> A_BLT<1> A_BLT<0> ++ VDD_CORE VSS +XEDGE<1> A_BLC<1> A_BLT<1> VDD_CORE VSS VDD_CORE VSS ++ / RM_IHPSG13_512x16_c2_1P_BITKIT_EDGE_TB +XEDGE<0> A_BLC<0> A_BLT<0> VDD_CORE VSS VDD_CORE VSS ++ / RM_IHPSG13_512x16_c2_1P_BITKIT_EDGE_TB +.ENDS + +.SUBCKT RSC_IHPSG13_CBUFX4 A Z VDD VSS +MN0 net9 A VSS VSS sg13_lv_nmos m=1 w=705.000n l=130.00n ng=1 nrd=0 ++ nrs=0 +MN1 Z net9 VSS VSS sg13_lv_nmos m=1 w=1.41u l=130.00n ng=2 nrd=0 nrs=0 +MP0 net9 A VDD VDD sg13_lv_pmos m=1 w=1.62u l=130.00n ng=1 nrd=0 nrs=0 +MP1 Z net9 VDD VDD sg13_lv_pmos m=1 w=3.24u l=130.00n ng=2 nrd=0 nrs=0 +.ENDS +.SUBCKT RM_IHPSG13_512x16_c2_1P_COLDRV13X4 ADDR_COL_I<1> ADDR_COL_I<0> ADDR_COL_O<1> ++ ADDR_COL_O<0> ADDR_DEC_I<7> ADDR_DEC_I<6> ADDR_DEC_I<5> ADDR_DEC_I<4> ++ ADDR_DEC_I<3> ADDR_DEC_I<2> ADDR_DEC_I<1> ADDR_DEC_I<0> ADDR_DEC_O<7> ++ ADDR_DEC_O<6> ADDR_DEC_O<5> ADDR_DEC_O<4> ADDR_DEC_O<3> ADDR_DEC_O<2> ++ ADDR_DEC_O<1> ADDR_DEC_O<0> DCLK_I DCLK_O RCLK_I RCLK_O WCLK_I WCLK_O ++ VDD VSS +XADDR_COL_DRV<1> ADDR_COL_I<1> ADDR_COL_O<1> VDD VSS / ++ RSC_IHPSG13_CBUFX4 +XADDR_COL_DRV<0> ADDR_COL_I<0> ADDR_COL_O<0> VDD VSS / ++ RSC_IHPSG13_CBUFX4 +XADDR_DEC_DRV<7> ADDR_DEC_I<7> ADDR_DEC_O<7> VDD VSS / ++ RSC_IHPSG13_CBUFX4 +XADDR_DEC_DRV<6> ADDR_DEC_I<6> ADDR_DEC_O<6> VDD VSS / ++ RSC_IHPSG13_CBUFX4 +XADDR_DEC_DRV<5> ADDR_DEC_I<5> ADDR_DEC_O<5> VDD VSS / ++ RSC_IHPSG13_CBUFX4 +XADDR_DEC_DRV<4> ADDR_DEC_I<4> ADDR_DEC_O<4> VDD VSS / ++ RSC_IHPSG13_CBUFX4 +XADDR_DEC_DRV<3> ADDR_DEC_I<3> ADDR_DEC_O<3> VDD VSS / ++ RSC_IHPSG13_CBUFX4 +XADDR_DEC_DRV<2> ADDR_DEC_I<2> ADDR_DEC_O<2> VDD VSS / ++ RSC_IHPSG13_CBUFX4 +XADDR_DEC_DRV<1> ADDR_DEC_I<1> ADDR_DEC_O<1> VDD VSS / ++ RSC_IHPSG13_CBUFX4 +XADDR_DEC_DRV<0> ADDR_DEC_I<0> ADDR_DEC_O<0> VDD VSS / ++ RSC_IHPSG13_CBUFX4 +XDCLK_DRV DCLK_I DCLK_O VDD VSS / RSC_IHPSG13_CBUFX4 +XRCLK_DRV RCLK_I RCLK_O VDD VSS / RSC_IHPSG13_CBUFX4 +XWCLK_DRV WCLK_I WCLK_O VDD VSS / RSC_IHPSG13_CBUFX4 +.ENDS +.SUBCKT RSC_IHPSG13_WLDRVX4 A Z VDD VSS +MN1 Z net6 VSS VSS sg13_lv_nmos m=1 w=705.000n l=130.00n ng=1 nrd=0 ++ nrs=0 +MN0 net6 A VSS VSS sg13_lv_nmos m=1 w=900.0n l=130.00n ng=1 nrd=0 nrs=0 +MP1 Z net6 VDD VDD sg13_lv_pmos m=1 w=3.24u l=130.00n ng=2 nrd=0 nrs=0 +MP0 net6 A VDD VDD sg13_lv_pmos m=1 w=900.0n l=130.00n ng=1 nrd=0 nrs=0 +.ENDS +.SUBCKT RM_IHPSG13_512x16_c2_1P_WLDRV16X4 A<15> A<14> A<13> A<12> A<11> A<10> A<9> A<8> ++ A<7> A<6> A<5> A<4> A<3> A<2> A<1> A<0> Z<15> Z<14> Z<13> Z<12> Z<11> Z<10> ++ Z<9> Z<8> Z<7> Z<6> Z<5> Z<4> Z<3> Z<2> Z<1> Z<0> VDD VSS +XBUF<15> A<15> Z<15> VDD VSS / RSC_IHPSG13_WLDRVX4 +XBUF<14> A<14> Z<14> VDD VSS / RSC_IHPSG13_WLDRVX4 +XBUF<13> A<13> Z<13> VDD VSS / RSC_IHPSG13_WLDRVX4 +XBUF<12> A<12> Z<12> VDD VSS / RSC_IHPSG13_WLDRVX4 +XBUF<11> A<11> Z<11> VDD VSS / RSC_IHPSG13_WLDRVX4 +XBUF<10> A<10> Z<10> VDD VSS / RSC_IHPSG13_WLDRVX4 +XBUF<9> A<9> Z<9> VDD VSS / RSC_IHPSG13_WLDRVX4 +XBUF<8> A<8> Z<8> VDD VSS / RSC_IHPSG13_WLDRVX4 +XBUF<7> A<7> Z<7> VDD VSS / RSC_IHPSG13_WLDRVX4 +XBUF<6> A<6> Z<6> VDD VSS / RSC_IHPSG13_WLDRVX4 +XBUF<5> A<5> Z<5> VDD VSS / RSC_IHPSG13_WLDRVX4 +XBUF<4> A<4> Z<4> VDD VSS / RSC_IHPSG13_WLDRVX4 +XBUF<3> A<3> Z<3> VDD VSS / RSC_IHPSG13_WLDRVX4 +XBUF<2> A<2> Z<2> VDD VSS / RSC_IHPSG13_WLDRVX4 +XBUF<1> A<1> Z<1> VDD VSS / RSC_IHPSG13_WLDRVX4 +XBUF<0> A<0> Z<0> VDD VSS / RSC_IHPSG13_WLDRVX4 +.ENDS +.SUBCKT RSC_IHPSG13_FILLCAP8 VDD VSS +MN0 vss_r vdd_r VSS VSS sg13_lv_nmos m=1 w=4.98u l=130.00n ng=6 nrd=0 ++ nrs=0 +MP0 vdd_r vss_r VDD VDD sg13_lv_pmos m=1 w=6.48u l=385.000n ng=4 nrd=0 ++ nrs=0 +.ENDS +.SUBCKT RSC_IHPSG13_LHPQX2 CP D Q VDD VSS +MN3 QIN CPN net14 VSS sg13_lv_nmos m=1 w=480.00n l=130.00n ng=1 nrd=0 nrs=0 +MN2 net14 net10 VSS VSS sg13_lv_nmos m=1 w=480.00n l=130.00n ng=1 ++ nrd=0 nrs=0 +MN5 net21 D VSS VSS sg13_lv_nmos m=1 w=870.00n l=130.00n ng=1 nrd=0 ++ nrs=0 +MN6 QIN CP net21 VSS sg13_lv_nmos m=1 w=870.00n l=130.00n ng=1 nrd=0 nrs=0 +MN1 net10 QIN VSS VSS sg13_lv_nmos m=1 w=480.00n l=130.00n ng=1 nrd=0 ++ nrs=0 +MN0 CPN CP VSS VSS sg13_lv_nmos m=1 w=480.00n l=130.00n ng=1 nrd=0 ++ nrs=0 +MN4 Q QIN VSS VSS sg13_lv_nmos m=1 w=980.00n l=130.00n ng=1 nrd=0 nrs=0 +MP2 QIN CP net16 VDD sg13_lv_pmos m=1 w=480.00n l=130.00n ng=1 nrd=0 nrs=0 +MP0 CPN CP VDD VDD sg13_lv_pmos m=1 w=480.00n l=130.00n ng=1 nrd=0 ++ nrs=0 +MP4 Q QIN VDD VDD sg13_lv_pmos m=1 w=1.62u l=130.00n ng=1 nrd=0 nrs=0 +MP3 net10 QIN VDD VDD sg13_lv_pmos m=1 w=480.00n l=130.00n ng=1 nrd=0 ++ nrs=0 +MP1 net16 net10 VDD VDD sg13_lv_pmos m=1 w=480.00n l=130.00n ng=1 ++ nrd=0 nrs=0 +MP6 QIN CPN net20 VDD sg13_lv_pmos m=1 w=975.000n l=130.00n ng=1 nrd=0 ++ nrs=0 +MP5 net20 D VDD VDD sg13_lv_pmos m=1 w=975.000n l=130.00n ng=1 nrd=0 ++ nrs=0 +.ENDS +.SUBCKT RSC_IHPSG13_NAND2X2 A B Z VDD VSS +MP1 Z B VDD VDD sg13_lv_pmos m=1 w=1.62u l=130.00n ng=1 nrd=0 nrs=0 +MP0 Z A VDD VDD sg13_lv_pmos m=1 w=1.62u l=130.00n ng=1 nrd=0 nrs=0 +MN0 Z B net7 VSS sg13_lv_nmos m=1 w=980.00n l=130.00n ng=1 nrd=0 nrs=0 +MN1 net7 A VSS VSS sg13_lv_nmos m=1 w=980.00n l=130.00n ng=1 nrd=0 ++ nrs=0 +.ENDS +.SUBCKT RSC_IHPSG13_CINVX4 A Z VDD VSS +MN0 Z A VSS VSS sg13_lv_nmos m=1 w=1.41u l=130.00n ng=2 nrd=0 nrs=0 +MP0 Z A VDD VDD sg13_lv_pmos m=1 w=3.24u l=130.00n ng=2 nrd=0 nrs=0 +.ENDS +.SUBCKT RSC_IHPSG13_CINVX2 A Z VDD VSS +MN0 Z A VSS VSS sg13_lv_nmos m=1 w=705.000n l=130.00n ng=1 nrd=0 nrs=0 +MP0 Z A VDD VDD sg13_lv_pmos m=1 w=1.62u l=130.00n ng=1 nrd=0 nrs=0 +.ENDS +.SUBCKT RSC_IHPSG13_INVX2 A Z VDD VSS +MN0 Z A VSS VSS sg13_lv_nmos m=1 w=980.00n l=130.00n ng=1 nrd=0 nrs=0 +MP0 Z A VDD VDD sg13_lv_pmos m=1 w=1.62u l=130.00n ng=1 nrd=0 nrs=0 +.ENDS +.SUBCKT RSC_IHPSG13_NAND3X2 A B C Z VDD VSS +MP2 Z A VDD VDD sg13_lv_pmos m=1 w=1.62u l=130.00n ng=1 nrd=0 nrs=0 +MP1 Z B VDD VDD sg13_lv_pmos m=1 w=1.62u l=130.00n ng=1 nrd=0 nrs=0 +MP0 Z C VDD VDD sg13_lv_pmos m=1 w=1.62u l=130.00n ng=1 nrd=0 nrs=0 +MN1 net12 B net16 VSS sg13_lv_nmos m=1 w=980.00n l=130.00n ng=1 nrd=0 nrs=0 +MN0 Z C net12 VSS sg13_lv_nmos m=1 w=980.00n l=130.00n ng=1 nrd=0 nrs=0 +MN2 net16 A VSS VSS sg13_lv_nmos m=1 w=980.00n l=130.00n ng=1 nrd=0 ++ nrs=0 +.ENDS +.SUBCKT RSC_IHPSG13_NOR3X2 A B C Z VDD VSS +MP0 net13 A VDD VDD sg13_lv_pmos m=1 w=1.62u l=130.00n ng=1 nrd=0 nrs=0 +MP2 Z C net10 VDD sg13_lv_pmos m=1 w=1.62u l=130.00n ng=1 nrd=0 nrs=0 +MP1 net10 B net13 VDD sg13_lv_pmos m=1 w=1.62u l=130.00n ng=1 nrd=0 nrs=0 +MN1 Z B VSS VSS sg13_lv_nmos m=1 w=875.000n l=130.00n ng=1 nrd=0 nrs=0 +MN0 Z C VSS VSS sg13_lv_nmos m=1 w=875.000n l=130.00n ng=1 nrd=0 nrs=0 +MN2 Z A VSS VSS sg13_lv_nmos m=1 w=875.000n l=130.00n ng=1 nrd=0 nrs=0 +.ENDS +.SUBCKT RSC_IHPSG13_FILLCAP4 VDD VSS +MN0 vss_r vdd_r VSS VSS sg13_lv_nmos m=1 w=2.49u l=130.00n ng=3 nrd=0 ++ nrs=0 +MP0 vdd_r vss_r VDD VDD sg13_lv_pmos m=1 w=3.24u l=385.000n ng=2 nrd=0 ++ nrs=0 +.ENDS +.SUBCKT RSC_IHPSG13_MET2RES A B +R0 B A lvsres w=2.6e-07 l=6e-07 +.ENDS +.SUBCKT RM_IHPSG13_512x16_c2_1P_DEC04 ADDR<3> ADDR<2> ADDR<1> ADDR<0> CS ECLK_H_BOT ++ ECLK_H_TOP ECLK_L_BOT ECLK_L_TOP WL<15> WL<14> WL<13> WL<12> WL<11> WL<10> ++ WL<9> WL<8> WL<7> WL<6> WL<5> WL<4> WL<3> WL<2> WL<1> WL<0> VDD VSS +XLATCH<3> CS ADDR<3> PADR<3> VDD VSS / RSC_IHPSG13_LHPQX2 +XLATCH<2> CS ADDR<2> PADR<2> VDD VSS / RSC_IHPSG13_LHPQX2 +XLATCH<1> CS ADDR<1> PADR<1> VDD VSS / RSC_IHPSG13_LHPQX2 +XLATCH<0> CS ADDR<0> PADR<0> VDD VSS / RSC_IHPSG13_LHPQX2 +XI0<3> PADR<1> PADR<0> sel01<3> VDD VSS / RSC_IHPSG13_NAND2X2 +XI0<2> PADR<1> NADR<0> sel01<2> VDD VSS / RSC_IHPSG13_NAND2X2 +XI0<1> NADR<1> PADR<0> sel01<1> VDD VSS / RSC_IHPSG13_NAND2X2 +XI0<0> NADR<1> NADR<0> sel01<0> VDD VSS / RSC_IHPSG13_NAND2X2 +XI4 ECLK_L_BOT EN VDD VSS / RSC_IHPSG13_CINVX4 +XI5 ECLK_H_BOT ECLK_L_BOT VDD VSS / RSC_IHPSG13_CINVX2 +XI3<3> PADR<3> NADR<3> VDD VSS / RSC_IHPSG13_INVX2 +XI3<2> PADR<2> NADR<2> VDD VSS / RSC_IHPSG13_INVX2 +XI3<1> PADR<1> NADR<1> VDD VSS / RSC_IHPSG13_INVX2 +XI3<0> PADR<0> NADR<0> VDD VSS / RSC_IHPSG13_INVX2 +XI1<3> PADR<2> PADR<3> CS sel23<3> VDD VSS / RSC_IHPSG13_NAND3X2 +XI1<2> NADR<2> PADR<3> CS sel23<2> VDD VSS / RSC_IHPSG13_NAND3X2 +XI1<1> PADR<2> NADR<3> CS sel23<1> VDD VSS / RSC_IHPSG13_NAND3X2 +XI1<0> NADR<2> NADR<3> CS sel23<0> VDD VSS / RSC_IHPSG13_NAND3X2 +XI2<15> sel23<3> sel01<3> EN WL<15> VDD VSS / RSC_IHPSG13_NOR3X2 +XI2<14> sel23<3> sel01<2> EN WL<14> VDD VSS / RSC_IHPSG13_NOR3X2 +XI2<13> sel23<3> sel01<1> EN WL<13> VDD VSS / RSC_IHPSG13_NOR3X2 +XI2<12> sel23<3> sel01<0> EN WL<12> VDD VSS / RSC_IHPSG13_NOR3X2 +XI2<11> sel23<2> sel01<3> EN WL<11> VDD VSS / RSC_IHPSG13_NOR3X2 +XI2<10> sel23<2> sel01<2> EN WL<10> VDD VSS / RSC_IHPSG13_NOR3X2 +XI2<9> sel23<2> sel01<1> EN WL<9> VDD VSS / RSC_IHPSG13_NOR3X2 +XI2<8> sel23<2> sel01<0> EN WL<8> VDD VSS / RSC_IHPSG13_NOR3X2 +XI2<7> sel23<1> sel01<3> EN WL<7> VDD VSS / RSC_IHPSG13_NOR3X2 +XI2<6> sel23<1> sel01<2> EN WL<6> VDD VSS / RSC_IHPSG13_NOR3X2 +XI2<5> sel23<1> sel01<1> EN WL<5> VDD VSS / RSC_IHPSG13_NOR3X2 +XI2<4> sel23<1> sel01<0> EN WL<4> VDD VSS / RSC_IHPSG13_NOR3X2 +XI2<3> sel23<0> sel01<3> EN WL<3> VDD VSS / RSC_IHPSG13_NOR3X2 +XI2<2> sel23<0> sel01<2> EN WL<2> VDD VSS / RSC_IHPSG13_NOR3X2 +XI2<1> sel23<0> sel01<1> EN WL<1> VDD VSS / RSC_IHPSG13_NOR3X2 +XI2<0> sel23<0> sel01<0> EN WL<0> VDD VSS / RSC_IHPSG13_NOR3X2 +XCAPS4 VDD VSS / RSC_IHPSG13_FILLCAP4 +XI11 ECLK_L_BOT ECLK_L_TOP / RSC_IHPSG13_MET2RES +XR0 ECLK_H_BOT ECLK_H_TOP / RSC_IHPSG13_MET2RES +.ENDS +.SUBCKT RM_IHPSG13_512x16_c2_1P_ROWDEC4 ADDR_N_I<3> ADDR_N_I<2> ADDR_N_I<1> ADDR_N_I<0> ++ CS_I ECLK_I WL_O<15> WL_O<14> WL_O<13> WL_O<12> WL_O<11> WL_O<10> WL_O<9> ++ WL_O<8> WL_O<7> WL_O<6> WL_O<5> WL_O<4> WL_O<3> WL_O<2> WL_O<1> WL_O<0> ++ VDD VSS +XL2<8> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<7> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<6> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<5> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<4> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<3> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<2> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<1> VDD VSS / RSC_IHPSG13_FILLCAP8 +XSEL ADDR_N_I<3> ADDR_N_I<2> ADDR_N_I<1> ADDR_N_I<0> CS_I ECLK_I ECLK_H<1> ++ ECLK_B<0> ECLK_B<1> WL_O<15> WL_O<14> WL_O<13> WL_O<12> WL_O<11> WL_O<10> ++ WL_O<9> WL_O<8> WL_O<7> WL_O<6> WL_O<5> WL_O<4> WL_O<3> WL_O<2> WL_O<1> ++ WL_O<0> VDD VSS / RM_IHPSG13_512x16_c2_1P_DEC04 +.ENDS +.SUBCKT RSC_IHPSG13_CINVX8 A Z VDD VSS +MN0 Z A VSS VSS sg13_lv_nmos m=1 w=2.82u l=130.00n ng=4 nrd=0 nrs=0 +MP0 Z A VDD VDD sg13_lv_pmos m=1 w=6.48u l=130.00n ng=4 nrd=0 nrs=0 +.ENDS +.SUBCKT RSC_IHPSG13_DFNQMX2IX1 BE BI CN D QI QIN VDD VSS +MN15 net026 BI VSS VSS sg13_lv_nmos m=1 w=560.00n l=130.00n ng=1 nrd=0 ++ nrs=0 +MN14 MXI_OUT BE net026 VSS sg13_lv_nmos m=1 w=560.00n l=130.00n ng=1 nrd=0 ++ nrs=0 +MN1 net025 D VSS VSS sg13_lv_nmos m=1 w=560.00n l=130.00n ng=1 nrd=0 ++ nrs=0 +MN0 MXI_OUT BEN net025 VSS sg13_lv_nmos m=1 w=560.00n l=130.00n ng=1 nrd=0 ++ nrs=0 +MN10 QI CNN net21 VSS sg13_lv_nmos m=1 w=850.00n l=130.00n ng=1 nrd=0 nrs=0 +MN11 net21 QI_MS VSS VSS sg13_lv_nmos m=1 w=850.00n l=130.00n ng=1 ++ nrd=0 nrs=0 +MN7 net30 QI_MS VSS VSS sg13_lv_nmos m=1 w=480.00n l=130.00n ng=1 ++ nrd=0 nrs=0 +MN6 QIN_MS CNN net30 VSS sg13_lv_nmos m=1 w=480.00n l=130.00n ng=1 nrd=0 ++ nrs=0 +MN3 QI_MS QIN_MS VSS VSS sg13_lv_nmos m=1 w=480.00n l=130.00n ng=1 ++ nrd=0 nrs=0 +MN12 CNN CN VSS VSS sg13_lv_nmos m=1 w=495.000n l=130.00n ng=1 nrd=0 ++ nrs=0 +MN9 net37 MXI_OUT VSS VSS sg13_lv_nmos m=1 w=870.00n l=130.00n ng=1 ++ nrd=0 nrs=0 +MN8 QIN_MS CN net37 VSS sg13_lv_nmos m=1 w=870.00n l=130.00n ng=1 nrd=0 ++ nrs=0 +MN5 QI CN net25 VSS sg13_lv_nmos m=1 w=480.00n l=130.00n ng=1 nrd=0 nrs=0 +MN4 net25 QIN VSS VSS sg13_lv_nmos m=1 w=480.00n l=130.00n ng=1 nrd=0 ++ nrs=0 +MN2 QIN QI VSS VSS sg13_lv_nmos m=1 w=480.00n l=130.00n ng=1 nrd=0 ++ nrs=0 +MN13 BEN BE VSS VSS sg13_lv_nmos m=1 w=560.00n l=130.00n ng=1 nrd=0 ++ nrs=0 +MP15 MXI_OUT BEN net027 VDD sg13_lv_pmos m=1 w=985.000n l=130.00n ng=1 ++ nrd=0 nrs=0 +MP14 net027 BI VDD VDD sg13_lv_pmos m=1 w=985.000n l=130.00n ng=1 ++ nrd=0 nrs=0 +MP1 MXI_OUT BE net024 VDD sg13_lv_pmos m=1 w=985.000n l=130.00n ng=1 nrd=0 ++ nrs=0 +MP0 net024 D VDD VDD sg13_lv_pmos m=1 w=985.000n l=130.00n ng=1 nrd=0 ++ nrs=0 +MP13 BEN BE VDD VDD sg13_lv_pmos m=1 w=645.000n l=130.00n ng=1 nrd=0 ++ nrs=0 +MP6 QI_MS QIN_MS VDD VDD sg13_lv_pmos m=1 w=480.00n l=130.00n ng=1 ++ nrd=0 nrs=0 +MP3 QI CNN net27 VDD sg13_lv_pmos m=1 w=480.00n l=130.00n ng=1 nrd=0 nrs=0 +MP2 net27 QIN VDD VDD sg13_lv_pmos m=1 w=480.00n l=130.00n ng=1 nrd=0 ++ nrs=0 +MP10 net36 MXI_OUT VDD VDD sg13_lv_pmos m=1 w=975.000n l=130.00n ng=1 ++ nrd=0 nrs=0 +MP11 QIN_MS CNN net36 VDD sg13_lv_pmos m=1 w=975.000n l=130.00n ng=1 nrd=0 ++ nrs=0 +MP4 net32 QI_MS VDD VDD sg13_lv_pmos m=1 w=480.00n l=130.00n ng=1 ++ nrd=0 nrs=0 +MP5 QIN_MS CN net32 VDD sg13_lv_pmos m=1 w=480.00n l=130.00n ng=1 nrd=0 ++ nrs=0 +MP7 QIN QI VDD VDD sg13_lv_pmos m=1 w=480.00n l=130.00n ng=1 nrd=0 ++ nrs=0 +MP12 CNN CN VDD VDD sg13_lv_pmos m=1 w=480.00n l=130.00n ng=1 nrd=0 ++ nrs=0 +MP9 QI CN net19 VDD sg13_lv_pmos m=1 w=990.00n l=130.00n ng=1 nrd=0 nrs=0 +MP8 net19 QI_MS VDD VDD sg13_lv_pmos m=1 w=990.00n l=130.00n ng=1 ++ nrd=0 nrs=0 +.ENDS +.SUBCKT RM_IHPSG13_512x16_c2_1P_ROWREG4 ACLK_N_I ADDR_I<3> ADDR_I<2> ADDR_I<1> ADDR_I<0> ++ ADDR_N_O<3> ADDR_N_O<2> ADDR_N_O<1> ADDR_N_O<0> BIST_ADDR_I<3> ++ BIST_ADDR_I<2> BIST_ADDR_I<1> BIST_ADDR_I<0> BIST_EN_I VDD VSS +XINV<3> q_int<3> qn_int<3> VDD VSS / RSC_IHPSG13_CINVX2 +XINV<2> q_int<2> qn_int<2> VDD VSS / RSC_IHPSG13_CINVX2 +XINV<1> q_int<1> qn_int<1> VDD VSS / RSC_IHPSG13_CINVX2 +XINV<0> q_int<0> qn_int<0> VDD VSS / RSC_IHPSG13_CINVX2 +XDRV<3> qn_int<3> ADDR_N_O<3> VDD VSS / RSC_IHPSG13_CINVX8 +XDRV<2> qn_int<2> ADDR_N_O<2> VDD VSS / RSC_IHPSG13_CINVX8 +XDRV<1> qn_int<1> ADDR_N_O<1> VDD VSS / RSC_IHPSG13_CINVX8 +XDRV<0> qn_int<0> ADDR_N_O<0> VDD VSS / RSC_IHPSG13_CINVX8 +XDFF<3> BIST_EN_I BIST_ADDR_I<3> ACLK_N_I ADDR_I<3> q_int<3> net2<0> VDD ++ VSS / RSC_IHPSG13_DFNQMX2IX1 +XDFF<2> BIST_EN_I BIST_ADDR_I<2> ACLK_N_I ADDR_I<2> q_int<2> net2<1> VDD ++ VSS / RSC_IHPSG13_DFNQMX2IX1 +XDFF<1> BIST_EN_I BIST_ADDR_I<1> ACLK_N_I ADDR_I<1> q_int<1> net2<2> VDD ++ VSS / RSC_IHPSG13_DFNQMX2IX1 +XDFF<0> BIST_EN_I BIST_ADDR_I<0> ACLK_N_I ADDR_I<0> q_int<0> net2<3> VDD ++ VSS / RSC_IHPSG13_DFNQMX2IX1 +XI11<20> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI11<19> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI11<18> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI11<17> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI11<16> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI11<15> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI11<14> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI11<13> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI11<12> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI11<11> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI11<10> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI11<9> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI11<8> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI11<7> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI11<6> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI11<5> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI11<4> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI11<3> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI11<2> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI11<1> VDD VSS / RSC_IHPSG13_FILLCAP8 +.ENDS +.SUBCKT RSC_IHPSG13_CDLYX1 A Z VDD VSS +MN1 net010 net032 VSS VSS sg13_lv_nmos m=1 w=300.0n l=160.00n ng=1 ++ nrd=0 nrs=0 +MN2 net032 A net014 VSS sg13_lv_nmos m=1 w=300.0n l=160.00n ng=1 nrd=0 ++ nrs=0 +MN0 Z net032 net010 VSS sg13_lv_nmos m=1 w=300.0n l=160.00n ng=1 nrd=0 ++ nrs=0 +MN3 net014 A VSS VSS sg13_lv_nmos m=1 w=300.0n l=160.00n ng=1 nrd=0 ++ nrs=0 +MP1 Z net032 net07 VDD sg13_lv_pmos m=1 w=720.00n l=160.00n ng=1 nrd=0 ++ nrs=0 +MP3 net011 A VDD VDD sg13_lv_pmos m=1 w=720.00n l=160.00n ng=1 nrd=0 ++ nrs=0 +MP0 net07 net032 VDD VDD sg13_lv_pmos m=1 w=720.00n l=160.00n ng=1 ++ nrd=0 nrs=0 +MP2 net032 A net011 VDD sg13_lv_pmos m=1 w=720.00n l=160.00n ng=1 nrd=0 ++ nrs=0 +.ENDS +.SUBCKT RSC_IHPSG13_CDLYX1_DUMMY A Z VDD VSS +MN0 vss_r vdd_r VSS VSS sg13_lv_nmos m=1 w=2.49u l=300.0n ng=3 nrd=0 ++ nrs=0 +MP0 vdd_r vss_r VDD VDD sg13_lv_pmos m=1 w=3.24u l=640.00n ng=2 nrd=0 ++ nrs=0 +R0 Z A lvsres w=2.6e-07 l=6e-07 +.ENDS + +.SUBCKT RSC_IHPSG13_MX2IX1 A0 A1 S ZN VDD VSS +MP4 SN S VDD VDD sg13_lv_pmos m=1 w=645.000n l=130.00n ng=1 nrd=0 nrs=0 +MP3 ZN SN net12 VDD sg13_lv_pmos m=1 w=985.000n l=130.00n ng=1 nrd=0 nrs=0 +MP2 net12 A1 VDD VDD sg13_lv_pmos m=1 w=985.000n l=130.00n ng=1 nrd=0 ++ nrs=0 +MP1 ZN S net17 VDD sg13_lv_pmos m=1 w=985.000n l=130.00n ng=1 nrd=0 nrs=0 +MP0 net17 A0 VDD VDD sg13_lv_pmos m=1 w=985.000n l=130.00n ng=1 nrd=0 ++ nrs=0 +MN5 SN S VSS VSS sg13_lv_nmos m=1 w=480.00n l=130.00n ng=1 nrd=0 nrs=0 +MN3 net13 A1 VSS VSS sg13_lv_nmos m=1 w=480.00n l=130.00n ng=1 nrd=0 ++ nrs=0 +MN2 ZN S net13 VSS sg13_lv_nmos m=1 w=480.00n l=130.00n ng=1 nrd=0 nrs=0 +MN1 net15 A0 VSS VSS sg13_lv_nmos m=1 w=480.00n l=130.00n ng=1 nrd=0 ++ nrs=0 +MN0 ZN SN net15 VSS sg13_lv_nmos m=1 w=480.00n l=130.00n ng=1 nrd=0 nrs=0 +.ENDS +.SUBCKT RM_IHPSG13_512x16_c2_1P_DLY_MUX A SEL Z VDD VSS +XI11 net4 Z VDD VSS / RSC_IHPSG13_CINVX2 +XI8 A D<3> SEL net4 VDD VSS / RSC_IHPSG13_MX2IX1 +XI20<3> D<2> D<3> VDD VSS / RSC_IHPSG13_CDLYX1 +XI20<2> D<1> D<2> VDD VSS / RSC_IHPSG13_CDLYX1 +XI20<1> A D<1> VDD VSS / RSC_IHPSG13_CDLYX1 +.ENDS +.SUBCKT RSC_IHPSG13_DFNQX2 CN D Q VDD VSS +MN0 Q QIN_SL VSS VSS sg13_lv_nmos m=1 w=980.00n l=130.00n ng=1 nrd=0 ++ nrs=0 +MN10 QIN_SL CNN net21 VSS sg13_lv_nmos m=1 w=850.00n l=130.00n ng=1 nrd=0 ++ nrs=0 +MN11 net21 QI_MS VSS VSS sg13_lv_nmos m=1 w=850.00n l=130.00n ng=1 ++ nrd=0 nrs=0 +MN7 net30 QI_MS VSS VSS sg13_lv_nmos m=1 w=480.00n l=130.00n ng=1 ++ nrd=0 nrs=0 +MN6 QIN_MS CNN net30 VSS sg13_lv_nmos m=1 w=480.00n l=130.00n ng=1 nrd=0 ++ nrs=0 +MN3 QI_MS QIN_MS VSS VSS sg13_lv_nmos m=1 w=480.00n l=130.00n ng=1 ++ nrd=0 nrs=0 +MN12 CNN CN VSS VSS sg13_lv_nmos m=1 w=495.000n l=130.00n ng=1 nrd=0 ++ nrs=0 +MN9 net37 D VSS VSS sg13_lv_nmos m=1 w=870.00n l=130.00n ng=1 nrd=0 ++ nrs=0 +MN8 QIN_MS CN net37 VSS sg13_lv_nmos m=1 w=870.00n l=130.00n ng=1 nrd=0 ++ nrs=0 +MN5 QIN_SL CN net25 VSS sg13_lv_nmos m=1 w=480.00n l=130.00n ng=1 nrd=0 ++ nrs=0 +MN4 net25 QI_SL VSS VSS sg13_lv_nmos m=1 w=480.00n l=130.00n ng=1 ++ nrd=0 nrs=0 +MN2 QI_SL QIN_SL VSS VSS sg13_lv_nmos m=1 w=480.00n l=130.00n ng=1 ++ nrd=0 nrs=0 +MP0 Q QIN_SL VDD VDD sg13_lv_pmos m=1 w=1.62u l=130.00n ng=1 nrd=0 ++ nrs=0 +MP6 QI_MS QIN_MS VDD VDD sg13_lv_pmos m=1 w=480.00n l=130.00n ng=1 ++ nrd=0 nrs=0 +MP3 QIN_SL CNN net27 VDD sg13_lv_pmos m=1 w=480.00n l=130.00n ng=1 nrd=0 ++ nrs=0 +MP2 net27 QI_SL VDD VDD sg13_lv_pmos m=1 w=480.00n l=130.00n ng=1 ++ nrd=0 nrs=0 +MP10 net36 D VDD VDD sg13_lv_pmos m=1 w=975.000n l=130.00n ng=1 nrd=0 ++ nrs=0 +MP11 QIN_MS CNN net36 VDD sg13_lv_pmos m=1 w=975.000n l=130.00n ng=1 nrd=0 ++ nrs=0 +MP4 net32 QI_MS VDD VDD sg13_lv_pmos m=1 w=480.00n l=130.00n ng=1 ++ nrd=0 nrs=0 +MP5 QIN_MS CN net32 VDD sg13_lv_pmos m=1 w=480.00n l=130.00n ng=1 nrd=0 ++ nrs=0 +MP7 QI_SL QIN_SL VDD VDD sg13_lv_pmos m=1 w=480.00n l=130.00n ng=1 ++ nrd=0 nrs=0 +MP12 CNN CN VDD VDD sg13_lv_pmos m=1 w=480.00n l=130.00n ng=1 nrd=0 ++ nrs=0 +MP9 QIN_SL CN net19 VDD sg13_lv_pmos m=1 w=990.00n l=130.00n ng=1 nrd=0 ++ nrs=0 +MP8 net19 QI_MS VDD VDD sg13_lv_pmos m=1 w=990.00n l=130.00n ng=1 ++ nrd=0 nrs=0 +.ENDS +.SUBCKT RSC_IHPSG13_CNAND2X2 A B Z VDD VSS +MN0 Z B net6 VSS sg13_lv_nmos m=1 w=980.00n l=130.00n ng=1 nrd=0 nrs=0 +MN1 net6 A VSS VSS sg13_lv_nmos m=1 w=980.00n l=130.00n ng=1 nrd=0 ++ nrs=0 +MP1 Z B VDD VDD sg13_lv_pmos m=1 w=1.62u l=130.00n ng=1 nrd=0 nrs=0 +MP0 Z A VDD VDD sg13_lv_pmos m=1 w=1.62u l=130.00n ng=1 nrd=0 nrs=0 +.ENDS +.SUBCKT RSC_IHPSG13_CGATEPX4 CP E Q VDD VSS +MN1 net08 QIN VSS VSS sg13_lv_nmos m=1 w=480.00n l=130.00n ng=1 nrd=0 ++ nrs=0 +MN2 net019 net08 VSS VSS sg13_lv_nmos m=1 w=480.00n l=130.00n ng=1 ++ nrd=0 nrs=0 +MN3 QIN CP net019 VSS sg13_lv_nmos m=1 w=480.00n l=130.00n ng=1 nrd=0 nrs=0 +MN6 Q net015 VSS VSS sg13_lv_nmos m=1 w=1.41u l=130.00n ng=2 nrd=0 ++ nrs=0 +MN5 net015 net08 net018 VSS sg13_lv_nmos m=1 w=980.00n l=130.00n ng=1 ++ nrd=0 nrs=0 +MN8 QIN CPN net023 VSS sg13_lv_nmos m=1 w=870.00n l=130.00n ng=1 nrd=0 ++ nrs=0 +MN7 net023 E VSS VSS sg13_lv_nmos m=1 w=870.00n l=130.00n ng=1 nrd=0 ++ nrs=0 +MN4 net018 CP VSS VSS sg13_lv_nmos m=1 w=980.00n l=130.00n ng=1 nrd=0 ++ nrs=0 +MN0 CPN CP VSS VSS sg13_lv_nmos m=1 w=500.0n l=130.00n ng=1 nrd=0 nrs=0 +MP3 net08 QIN VDD VDD sg13_lv_pmos m=1 w=480.00n l=130.00n ng=1 nrd=0 ++ nrs=0 +MP2 QIN CPN net017 VDD sg13_lv_pmos m=1 w=480.00n l=130.00n ng=1 nrd=0 ++ nrs=0 +MP1 net017 net08 VDD VDD sg13_lv_pmos m=1 w=480.00n l=130.00n ng=1 ++ nrd=0 nrs=0 +MP0 CPN CP VDD VDD sg13_lv_pmos m=1 w=500.0n l=130.00n ng=1 nrd=0 nrs=0 +MP8 QIN CP net024 VDD sg13_lv_pmos m=1 w=975.000n l=130.00n ng=1 nrd=0 ++ nrs=0 +MP7 net024 E VDD VDD sg13_lv_pmos m=1 w=975.000n l=130.00n ng=1 nrd=0 ++ nrs=0 +MP4 net015 CP VDD VDD sg13_lv_pmos m=1 w=1.27u l=130.00n ng=1 nrd=0 ++ nrs=0 +MP6 Q net015 VDD VDD sg13_lv_pmos m=1 w=3.24u l=130.00n ng=2 nrd=0 ++ nrs=0 +MP5 net015 net08 VDD VDD sg13_lv_pmos m=1 w=1.27u l=130.00n ng=1 nrd=0 ++ nrs=0 +.ENDS +.SUBCKT RSC_IHPSG13_CBUFX8 A Z VDD VSS +MP0 net4 A VDD VDD sg13_lv_pmos m=1 w=3.24u l=130.00n ng=2 nrd=0 nrs=0 +MP1 Z net4 VDD VDD sg13_lv_pmos m=1 w=6.48u l=130.00n ng=4 nrd=0 nrs=0 +MN1 Z net4 VSS VSS sg13_lv_nmos m=1 w=2.82u l=130.00n ng=4 nrd=0 nrs=0 +MN0 net4 A VSS VSS sg13_lv_nmos m=1 w=1.41u l=130.00n ng=2 nrd=0 nrs=0 +.ENDS +.SUBCKT RSC_IHPSG13_CDLYX2 A Z VDD VSS +MN2 net4 A net9 VSS sg13_lv_nmos m=1 w=320.00n l=200.0n ng=1 nrd=0 nrs=0 +MN0 Z net4 VSS VSS sg13_lv_nmos m=1 w=705.000n l=130.00n ng=1 nrd=0 ++ nrs=0 +MN1 net9 A VSS VSS sg13_lv_nmos m=1 w=320.00n l=200.0n ng=1 nrd=0 nrs=0 +MP2 net4 A net10 VDD sg13_lv_pmos m=1 w=1.2u l=200.0n ng=1 nrd=0 nrs=0 +MP1 net10 A VDD VDD sg13_lv_pmos m=1 w=1.2u l=200.0n ng=1 nrd=0 nrs=0 +MP0 Z net4 VDD VDD sg13_lv_pmos m=1 w=1.62u l=130.00n ng=1 nrd=0 nrs=0 +.ENDS +.SUBCKT RSC_IHPSG13_MX2X2 A0 A1 S Z VDD VSS +MP6 Z net010 VDD VDD sg13_lv_pmos m=1 w=1.62u l=130.00n ng=1 nrd=0 ++ nrs=0 +MP4 SN S VDD VDD sg13_lv_pmos m=1 w=645.000n l=130.00n ng=1 nrd=0 nrs=0 +MP3 net010 SN net12 VDD sg13_lv_pmos m=1 w=985.000n l=130.00n ng=1 nrd=0 ++ nrs=0 +MP2 net12 A1 VDD VDD sg13_lv_pmos m=1 w=985.000n l=130.00n ng=1 nrd=0 ++ nrs=0 +MP1 net010 S net17 VDD sg13_lv_pmos m=1 w=985.000n l=130.00n ng=1 nrd=0 ++ nrs=0 +MP0 net17 A0 VDD VDD sg13_lv_pmos m=1 w=985.000n l=130.00n ng=1 nrd=0 ++ nrs=0 +MN6 Z net010 VSS VSS sg13_lv_nmos m=1 w=705.000n l=130.00n ng=1 nrd=0 ++ nrs=0 +MN5 SN S VSS VSS sg13_lv_nmos m=1 w=560.00n l=130.00n ng=1 nrd=0 nrs=0 +MN3 net13 A1 VSS VSS sg13_lv_nmos m=1 w=560.00n l=130.00n ng=1 nrd=0 ++ nrs=0 +MN2 net010 S net13 VSS sg13_lv_nmos m=1 w=560.00n l=130.00n ng=1 nrd=0 ++ nrs=0 +MN1 net15 A0 VSS VSS sg13_lv_nmos m=1 w=560.00n l=130.00n ng=1 nrd=0 ++ nrs=0 +MN0 net010 SN net15 VSS sg13_lv_nmos m=1 w=560.00n l=130.00n ng=1 nrd=0 ++ nrs=0 +.ENDS +.SUBCKT RSC_IHPSG13_AND2X2 A B Z VDD VSS +MN3 Z net6 VSS VSS sg13_lv_nmos m=1 w=980.00n l=130.00n ng=1 nrd=0 ++ nrs=0 +MN4 net9 B VSS VSS sg13_lv_nmos m=1 w=500.0n l=130.00n ng=1 nrd=0 nrs=0 +MN6 net6 A net9 VSS sg13_lv_nmos m=1 w=500.0n l=130.00n ng=1 nrd=0 nrs=0 +MP2 Z net6 VDD VDD sg13_lv_pmos m=1 w=1.62u l=130.00n ng=1 nrd=0 nrs=0 +MP0 net6 B VDD VDD sg13_lv_pmos m=1 w=860.00n l=130.00n ng=1 nrd=0 ++ nrs=0 +MP1 net6 A VDD VDD sg13_lv_pmos m=1 w=860.00n l=130.00n ng=1 nrd=0 ++ nrs=0 +.ENDS +.SUBCKT RSC_IHPSG13_TIEL Z VDD VSS +MN0 Z net2 VSS VSS sg13_lv_nmos m=1 w=480.00n l=130.00n ng=1 nrd=0 ++ nrs=0 +MP0 net2 net2 VDD VDD sg13_lv_pmos m=1 w=480.00n l=130.00n ng=1 nrd=0 ++ nrs=0 +.ENDS +.SUBCKT RSC_IHPSG13_XOR2X2 A B Z VDD VSS +MP8 net012 B net7 VDD sg13_lv_pmos m=1 w=825.000n l=130.00n ng=1 nrd=0 ++ nrs=0 +MP7 net011 net3 net012 VDD sg13_lv_pmos m=1 w=825.000n l=130.00n ng=1 ++ nrd=0 nrs=0 +MP6 Z net012 VDD VDD sg13_lv_pmos m=1 w=1.535u l=130.00n ng=1 nrd=0 ++ nrs=0 +MP2 net7 A VDD VDD sg13_lv_pmos m=1 w=825.000n l=130.00n ng=1 nrd=0 ++ nrs=0 +MP4 net011 net7 VDD VDD sg13_lv_pmos m=1 w=825.000n l=130.00n ng=1 ++ nrd=0 nrs=0 +MP5 net3 B VDD VDD sg13_lv_pmos m=1 w=580.00n l=130.00n ng=1 nrd=0 ++ nrs=0 +MN7 net012 B net011 VSS sg13_lv_nmos m=1 w=555.000n l=130.00n ng=1 nrd=0 ++ nrs=0 +MN6 net7 net3 net012 VSS sg13_lv_nmos m=1 w=555.000n l=130.00n ng=1 nrd=0 ++ nrs=0 +MN5 Z net012 VSS VSS sg13_lv_nmos m=1 w=775.000n l=130.00n ng=1 nrd=0 ++ nrs=0 +MN2 net7 A VSS VSS sg13_lv_nmos m=1 w=555.000n l=130.00n ng=1 nrd=0 ++ nrs=0 +MN4 net3 B VSS VSS sg13_lv_nmos m=1 w=480.00n l=130.00n ng=1 nrd=0 ++ nrs=0 +MN3 net011 net7 VSS VSS sg13_lv_nmos m=1 w=555.000n l=130.00n ng=1 ++ nrd=0 nrs=0 +.ENDS +.SUBCKT RSC_IHPSG13_OA12X1 A B C Z VDD VSS +MN2 net7 C VSS VSS sg13_lv_nmos m=1 w=980.00n l=130.00n ng=1 nrd=0 ++ nrs=0 +MN3 Z net17 VSS VSS sg13_lv_nmos m=1 w=500.0n l=130.00n ng=1 nrd=0 ++ nrs=0 +MN1 net17 B net7 VSS sg13_lv_nmos m=1 w=980.00n l=130.00n ng=1 nrd=0 nrs=0 +MN0 net17 A net7 VSS sg13_lv_nmos m=1 w=980.00n l=130.00n ng=1 nrd=0 nrs=0 +MP0 net24 A VDD VDD sg13_lv_pmos m=1 w=1.62u l=130.00n ng=1 nrd=0 nrs=0 +MP3 Z net17 VDD VDD sg13_lv_pmos m=1 w=905.000n l=130.00n ng=1 nrd=0 ++ nrs=0 +MP1 net17 B net24 VDD sg13_lv_pmos m=1 w=1.62u l=130.00n ng=1 nrd=0 nrs=0 +MP2 net17 C VDD VDD sg13_lv_pmos m=1 w=905.000n l=130.00n ng=1 nrd=0 ++ nrs=0 +.ENDS +.SUBCKT RM_IHPSG13_512x16_c2_1P_CTRL ACLK_N BIST_CK_I BIST_CS_I BIST_EN BIST_RE_I ++ BIST_WE_I B_TIEL_O CK_I CS_I DCLK ECLK PULSE_H PULSE_L PULSE_O RCLK RE_I ++ ROW_CS WCLK WE_I VDD VSS +XI17 ck_regs we col_we VDD VSS / RSC_IHPSG13_DFNQX2 +XI16 ck_regs re col_re VDD VSS / RSC_IHPSG13_DFNQX2 +XI18 ck_regs cs net7 VDD VSS / RSC_IHPSG13_DFNQX2 +XI71 ACLK_N net012 PULSE_O VDD VSS / RSC_IHPSG13_DFNQX2 +XI77 col_we net9 net016 VDD VSS / RSC_IHPSG13_CNAND2X2 +XI76 col_re net9 net018 VDD VSS / RSC_IHPSG13_CNAND2X2 +XI15 ck_dly WEorREandCS aclk VDD VSS / RSC_IHPSG13_CGATEPX4 +XI14 ck WEandCS DCLK VDD VSS / RSC_IHPSG13_CGATEPX4 +XI60 net7 ROW_CS VDD VSS / RSC_IHPSG13_CBUFX8 +XI73 PULSE_O net012 VDD VSS / RSC_IHPSG13_CINVX2 +XI8 net9 net8 VDD VSS / RSC_IHPSG13_CINVX2 +XI64 ck ck_dly VDD VSS / RSC_IHPSG13_CDLYX2 +XI86 CS_I BIST_CS_I BIST_EN cs VDD VSS / RSC_IHPSG13_MX2X2 +XI87 CK_I BIST_CK_I BIST_EN ck VDD VSS / RSC_IHPSG13_MX2X2 +XI85 WE_I BIST_WE_I BIST_EN we VDD VSS / RSC_IHPSG13_MX2X2 +XI84 RE_I BIST_RE_I BIST_EN re VDD VSS / RSC_IHPSG13_MX2X2 +XI22 we cs WEandCS VDD VSS / RSC_IHPSG13_AND2X2 +XBM_TIEL B_TIEL_O VDD VSS / RSC_IHPSG13_TIEL +XI48 ck_dly ck_regs VDD VSS / RSC_IHPSG13_CINVX4 +XI81 net016 WCLK VDD VSS / RSC_IHPSG13_CINVX4 +XI80 net018 RCLK VDD VSS / RSC_IHPSG13_CINVX4 +XI78 net8 net020 VDD VSS / RSC_IHPSG13_CINVX4 +XI6 PULSE_L PULSE_H net9 VDD VSS / RSC_IHPSG13_XOR2X2 +XI79 net020 ECLK VDD VSS / RSC_IHPSG13_CINVX8 +XI63 aclk ACLK_N VDD VSS / RSC_IHPSG13_CINVX8 +XI21 re we cs WEorREandCS VDD VSS / RSC_IHPSG13_OA12X1 +.ENDS +.SUBCKT RM_IHPSG13_512x16_c2_1P_COLDEC2 ACLK_N ADDR<1> ADDR<0> ADDR_COL<1> ADDR_COL<0> ++ ADDR_DEC<7> ADDR_DEC<6> ADDR_DEC<5> ADDR_DEC<4> ADDR_DEC<3> ADDR_DEC<2> ++ ADDR_DEC<1> ADDR_DEC<0> BIST_ADDR<1> BIST_ADDR<0> BIST_EN_I VDD VSS +XI14<5> VDD VSS / RSC_IHPSG13_FILLCAP4 +XI14<4> VDD VSS / RSC_IHPSG13_FILLCAP4 +XI14<3> VDD VSS / RSC_IHPSG13_FILLCAP4 +XI14<2> VDD VSS / RSC_IHPSG13_FILLCAP4 +XI14<1> VDD VSS / RSC_IHPSG13_FILLCAP4 +XDFF<1> BIST_EN_I BIST_ADDR<1> ACLK_N ADDR<1> padr_int<1> net6<0> VDD ++ VSS / RSC_IHPSG13_DFNQMX2IX1 +XDFF<0> BIST_EN_I BIST_ADDR<0> ACLK_N ADDR<0> padr_int<0> net6<1> VDD ++ VSS / RSC_IHPSG13_DFNQMX2IX1 +XI1<3> PADR<1> PADR<0> addr_n<3> VDD VSS / RSC_IHPSG13_NAND2X2 +XI1<2> PADR<1> NADR<0> addr_n<2> VDD VSS / RSC_IHPSG13_NAND2X2 +XI1<1> NADR<1> PADR<0> addr_n<1> VDD VSS / RSC_IHPSG13_NAND2X2 +XI1<0> NADR<1> NADR<0> addr_n<0> VDD VSS / RSC_IHPSG13_NAND2X2 +XI16<37> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI16<36> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI16<35> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI16<34> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI16<33> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI16<32> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI16<31> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI16<30> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI16<29> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI16<28> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI16<27> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI16<26> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI16<25> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI16<24> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI16<23> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI16<22> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI16<21> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI16<20> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI16<19> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI16<18> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI16<17> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI16<16> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI16<15> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI16<14> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI16<13> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI16<12> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI16<11> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI16<10> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI16<9> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI16<8> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI16<7> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI16<6> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI16<5> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI16<4> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI16<3> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI16<2> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI16<1> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI3<1> padr_int<1> NADR<1> VDD VSS / RSC_IHPSG13_INVX2 +XI3<0> padr_int<0> NADR<0> VDD VSS / RSC_IHPSG13_INVX2 +XI13<1> NADR<1> PADR<1> VDD VSS / RSC_IHPSG13_INVX2 +XI13<0> NADR<0> PADR<0> VDD VSS / RSC_IHPSG13_INVX2 +XI2<3> addr_n<3> ADDR_DEC<3> VDD VSS / RSC_IHPSG13_INVX2 +XI2<2> addr_n<2> ADDR_DEC<2> VDD VSS / RSC_IHPSG13_INVX2 +XI2<1> addr_n<1> ADDR_DEC<1> VDD VSS / RSC_IHPSG13_INVX2 +XI2<0> addr_n<0> ADDR_DEC<0> VDD VSS / RSC_IHPSG13_INVX2 +XI15<1> ADDR_COL<1> VDD VSS / RSC_IHPSG13_TIEL +XI15<0> ADDR_COL<0> VDD VSS / RSC_IHPSG13_TIEL +XI17<3> ADDR_DEC<7> VDD VSS / RSC_IHPSG13_TIEL +XI17<2> ADDR_DEC<6> VDD VSS / RSC_IHPSG13_TIEL +XI17<1> ADDR_DEC<5> VDD VSS / RSC_IHPSG13_TIEL +XI17<0> ADDR_DEC<4> VDD VSS / RSC_IHPSG13_TIEL +.ENDS +.SUBCKT RSC_IHPSG13_NOR2X2 A B Z VDD VSS +MP1 Z B net9 VDD sg13_lv_pmos m=1 w=1.62u l=130.00n ng=1 nrd=0 nrs=0 +MP0 net9 A VDD VDD sg13_lv_pmos m=1 w=1.62u l=130.00n ng=1 nrd=0 nrs=0 +MN0 Z B VSS VSS sg13_lv_nmos m=1 w=980.00n l=130.00n ng=1 nrd=0 nrs=0 +MN1 Z A VSS VSS sg13_lv_nmos m=1 w=980.00n l=130.00n ng=1 nrd=0 nrs=0 +.ENDS +.SUBCKT RSC_IHPSG13_CINVX4_WN A Z VDD VSS +MN0 Z A VSS VSS sg13_lv_nmos m=1 w=705.000n l=130.00n ng=1 nrd=0 nrs=0 +MP0 Z A VDD VDD sg13_lv_pmos m=1 w=3.24u l=130.00n ng=2 nrd=0 nrs=0 +.ENDS +.SUBCKT RM_IHPSG13_512x16_c2_1P_BLDRV BLC BLC_SEL BLT BLT_SEL PRE_N SEL_P WR_ONE WR_ZERO ++ VDD VSS +XCDEC SEL_P WR_ZERO BLC_PMOS_DRIVE VDD VSS / RSC_IHPSG13_NAND2X2 +XTDEC SEL_P WR_ONE BLT_PMOS_DRIVE VDD VSS / RSC_IHPSG13_NAND2X2 +MTWN BLT BLT_NMOS_DRIVE VSS VSS sg13_lv_nmos m=1 w=4.82u l=130.00n ++ ng=2 nrd=0 nrs=0 +MCWN BLC BLC_NMOS_DRIVE VSS VSS sg13_lv_nmos m=1 w=4.82u l=130.00n ++ ng=2 nrd=0 nrs=0 +MCWP BLC BLC_PMOS_DRIVE VDD VDD sg13_lv_pmos m=1 w=1.5u l=130.00n ng=1 ++ nrd=0 nrs=0 +MTWP BLT BLT_PMOS_DRIVE VDD VDD sg13_lv_pmos m=1 w=1.5u l=130.00n ng=1 ++ nrd=0 nrs=0 +MTSP BLT_SEL SEL_N BLT VDD sg13_lv_pmos m=1 w=1.5u l=130.00n ng=1 nrd=0 ++ nrs=0 +MTPR BLT PRE_N VDD VDD sg13_lv_pmos m=1 w=3.000u l=130.00n ng=2 nrd=0 ++ nrs=0 +MCSP BLC_SEL SEL_N BLC VDD sg13_lv_pmos m=1 w=1.5u l=130.00n ng=1 nrd=0 ++ nrs=0 +MCPR BLC PRE_N VDD VDD sg13_lv_pmos m=1 w=3.000u l=130.00n ng=2 nrd=0 ++ nrs=0 +XI86 SEL_P SEL_N VDD VSS / RSC_IHPSG13_INVX2 +XTINV BLC_PMOS_DRIVE BLT_NMOS_DRIVE VDD VSS / RSC_IHPSG13_INVX2 +XCINV BLT_PMOS_DRIVE BLC_NMOS_DRIVE VDD VSS / RSC_IHPSG13_INVX2 +.ENDS +.SUBCKT RSC_IHPSG13_TIEH Z VDD VSS +MN0 net2 net2 VSS VSS sg13_lv_nmos m=1 w=480.00n l=130.00n ng=1 nrd=0 ++ nrs=0 +MP0 Z net2 VDD VDD sg13_lv_pmos m=1 w=480.00n l=130.00n ng=1 nrd=0 ++ nrs=0 +.ENDS +.SUBCKT RSC_IHPSG13_MET3RES A B +R0 B A lvsres w=2.6e-07 l=6e-07 +.ENDS +.SUBCKT RSC_IHPSG13_DFPQD_MSAFFX2 CP DN DP QN QP VDD VSS +MN12 SN RN DIFFP VSS sg13_lv_nmos m=1 w=2.4u l=200.0n ng=2 nrd=0 nrs=0 +MN13 TAIL CP VSS VSS sg13_lv_nmos m=1 w=2.4u l=130.00n ng=2 nrd=0 nrs=0 +MN9 DIFFP DP TAIL VSS sg13_lv_nmos m=1 w=2.4u l=200.0n ng=2 nrd=0 nrs=0 +MN10 DIFFN DN TAIL VSS sg13_lv_nmos m=1 w=2.4u l=200.0n ng=2 nrd=0 nrs=0 +MN11 RN SN DIFFN VSS sg13_lv_nmos m=1 w=2.4u l=200.0n ng=2 nrd=0 nrs=0 +MN19 net33 SN VSS VSS sg13_lv_nmos m=1 w=980.00n l=130.00n ng=1 nrd=0 ++ nrs=0 +MN20 QN QP net37 VSS sg13_lv_nmos m=1 w=980.00n l=130.00n ng=1 nrd=0 nrs=0 +MN18 net37 RN VSS VSS sg13_lv_nmos m=1 w=980.00n l=130.00n ng=1 nrd=0 ++ nrs=0 +MN17 QP QN net33 VSS sg13_lv_nmos m=1 w=980.00n l=130.00n ng=1 nrd=0 nrs=0 +MP15 SN RN VDD VDD sg13_lv_pmos m=1 w=800.0n l=130.00n ng=1 nrd=0 nrs=0 +MP16 RN CP VDD VDD sg13_lv_pmos m=1 w=800.0n l=130.00n ng=1 nrd=0 nrs=0 +MP14 DIFFP CP VDD VDD sg13_lv_pmos m=1 w=800.0n l=130.00n ng=1 nrd=0 ++ nrs=0 +MP12 RN SN VDD VDD sg13_lv_pmos m=1 w=800.0n l=130.00n ng=1 nrd=0 nrs=0 +MP13 DIFFN CP VDD VDD sg13_lv_pmos m=1 w=800.0n l=130.00n ng=1 nrd=0 ++ nrs=0 +MP11 SN CP VDD VDD sg13_lv_pmos m=1 w=800.0n l=130.00n ng=1 nrd=0 nrs=0 +MP19 QN QP VDD VDD sg13_lv_pmos m=1 w=900.0n l=130.00n ng=1 nrd=0 nrs=0 +MP20 QP SN VDD VDD sg13_lv_pmos m=1 w=1.8u l=130.00n ng=2 nrd=0 nrs=0 +MP18 QN RN VDD VDD sg13_lv_pmos m=1 w=1.8u l=130.00n ng=2 nrd=0 nrs=0 +MP17 QP QN VDD VDD sg13_lv_pmos m=1 w=900.0n l=130.00n ng=1 nrd=0 nrs=0 +.ENDS +.SUBCKT RSC_IHPSG13_CBUFX2 A Z VDD VSS +MN1 Z net4 VSS VSS sg13_lv_nmos m=1 w=705.000n l=130.00n ng=1 nrd=0 ++ nrs=0 +MN0 net4 A VSS VSS sg13_lv_nmos m=1 w=540.00n l=130.00n ng=1 nrd=0 ++ nrs=0 +MP1 Z net4 VDD VDD sg13_lv_pmos m=1 w=1.62u l=130.00n ng=1 nrd=0 nrs=0 +MP0 net4 A VDD VDD sg13_lv_pmos m=1 w=1.1u l=130.00n ng=1 nrd=0 nrs=0 +.ENDS +.SUBCKT RSC_IHPSG13_INVX4 A Z VDD VSS +MN0 Z A VSS VSS sg13_lv_nmos m=1 w=1.96u l=130.00n ng=2 nrd=0 nrs=0 +MP0 Z A VDD VDD sg13_lv_pmos m=1 w=3.24u l=130.00n ng=2 nrd=0 nrs=0 +.ENDS +.SUBCKT RM_IHPSG13_512x16_c2_1P_COLCTRL2 A_ADDR_DEC<3> A_ADDR_DEC<2> A_ADDR_DEC<1> ++ A_ADDR_DEC<0> A_BIST_BM_I A_BIST_DW_I A_BIST_EN_I A_BLC<3> A_BLC<2> A_BLC<1> ++ A_BLC<0> A_BLT<3> A_BLT<2> A_BLT<1> A_BLT<0> A_BM_I A_DCLK_B_L A_DCLK_B_R ++ A_DCLK_L A_DCLK_R A_DR_O A_DW_I A_RCLK_B_L A_RCLK_B_R A_RCLK_L A_RCLK_R ++ A_TIEH_O A_WCLK_B_L A_WCLK_B_R A_WCLK_L A_WCLK_R VDD VSS +XA_DREG A_BIST_EN_I A_BIST_DW_I A_DCLK_B_L A_DW_I A_DI_R net22 VDD VSS ++ / RSC_IHPSG13_DFNQMX2IX1 +XA_BREG A_BIST_EN_I A_BIST_BM_I A_DCLK_B_L A_BM_I A_BM_R net23 VDD VSS ++ / RSC_IHPSG13_DFNQMX2IX1 +XA_CAPS<5> VDD VSS / RSC_IHPSG13_FILLCAP4 +XA_CAPS<4> VDD VSS / RSC_IHPSG13_FILLCAP4 +XA_CAPS<3> VDD VSS / RSC_IHPSG13_FILLCAP4 +XA_CAPS<2> VDD VSS / RSC_IHPSG13_FILLCAP4 +XA_CAPS<1> VDD VSS / RSC_IHPSG13_FILLCAP4 +XA_I80 A_WCLK_B_R A_RCLK_B_R net21 VDD VSS / RSC_IHPSG13_AND2X2 +XA_I75 A_DI_R A_DO_WRITE_P A_WR_ONE VDD VSS / RSC_IHPSG13_AND2X2 +XA_I76 A_DI_N A_DO_WRITE_P A_WR_ZERO VDD VSS / RSC_IHPSG13_AND2X2 +XA_I44 A_WCLK_B_R A_BM_N A_DO_WRITE_P VDD VSS / RSC_IHPSG13_NOR2X2 +XA_I81 net21 A_PRE_N VDD VSS / RSC_IHPSG13_CINVX4_WN +XA_BLTMUX<3> A_BLC<3> A_BLC_SEL A_BLT<3> A_BLT_SEL A_PRE_N A_ADDR_DEC<3> ++ A_WR_ONE A_WR_ZERO VDD VSS / RM_IHPSG13_512x16_c2_1P_BLDRV +XA_BLTMUX<2> A_BLC<2> A_BLC_SEL A_BLT<2> A_BLT_SEL A_PRE_N A_ADDR_DEC<2> ++ A_WR_ONE A_WR_ZERO VDD VSS / RM_IHPSG13_512x16_c2_1P_BLDRV +XA_BLTMUX<1> A_BLC<1> A_BLC_SEL A_BLT<1> A_BLT_SEL A_PRE_N A_ADDR_DEC<1> ++ A_WR_ONE A_WR_ZERO VDD VSS / RM_IHPSG13_512x16_c2_1P_BLDRV +XA_BLTMUX<0> A_BLC<0> A_BLC_SEL A_BLT<0> A_BLT_SEL A_PRE_N A_ADDR_DEC<0> ++ A_WR_ONE A_WR_ZERO VDD VSS / RM_IHPSG13_512x16_c2_1P_BLDRV +XA_BM_TIEH A_TIEH_O VDD VSS / RSC_IHPSG13_TIEH +XA_I89 A_DCLK_B_L A_DCLK_B_R / RSC_IHPSG13_MET3RES +XA_I88 A_DCLK_L A_DCLK_R / RSC_IHPSG13_MET3RES +XA_I87 A_WCLK_L A_WCLK_R / RSC_IHPSG13_MET3RES +XA_I91 A_RCLK_B_R A_RCLK_B_L / RSC_IHPSG13_MET3RES +XA_R2 A_RCLK_R A_RCLK_L / RSC_IHPSG13_MET3RES +XA_I90 A_WCLK_B_R A_WCLK_B_L / RSC_IHPSG13_MET3RES +XA_ISENSE A_SAE A_BLC_SEL A_BLT_SEL net19 net20 VDD VSS / ++ RSC_IHPSG13_DFPQD_MSAFFX2 +XA_I78 A_RCLK_B_R A_SAE VDD VSS / RSC_IHPSG13_CBUFX2 +XA_I83 A_BM_R A_BM_N VDD VSS / RSC_IHPSG13_INVX2 +XA_I49 A_DI_R A_DI_N VDD VSS / RSC_IHPSG13_INVX2 +XA_I51 net19 A_DR_O VDD VSS / RSC_IHPSG13_INVX4 +XA_I69 A_DCLK_L A_DCLK_B_L VDD VSS / RSC_IHPSG13_CINVX2 +XA_I50 A_WCLK_L A_WCLK_B_R VDD VSS / RSC_IHPSG13_CINVX2 +XA_EBUF A_RCLK_R A_RCLK_B_R VDD VSS / RSC_IHPSG13_CINVX2 +.ENDS +.SUBCKT RM_IHPSG13_512x16_c2_1P_COLDRV13_FILL4 VDD VSS +XI0<9> VDD VSS / RSC_IHPSG13_FILLCAP4 +XI0<8> VDD VSS / RSC_IHPSG13_FILLCAP4 +XI0<7> VDD VSS / RSC_IHPSG13_FILLCAP4 +XI0<6> VDD VSS / RSC_IHPSG13_FILLCAP4 +XI0<5> VDD VSS / RSC_IHPSG13_FILLCAP4 +XI0<4> VDD VSS / RSC_IHPSG13_FILLCAP4 +XI0<3> VDD VSS / RSC_IHPSG13_FILLCAP4 +XI0<2> VDD VSS / RSC_IHPSG13_FILLCAP4 +XI0<1> VDD VSS / RSC_IHPSG13_FILLCAP4 +.ENDS +.SUBCKT RM_IHPSG13_512x16_c2_1P_COLDRV13_FILL4C2 VDD VSS +XI0<2> VDD VSS / RSC_IHPSG13_FILLCAP4 +XI0<1> VDD VSS / RSC_IHPSG13_FILLCAP4 +.ENDS + + +.SUBCKT RM_IHPSG13_512x16_c2_1P_COLDEC4 ACLK_N ADDR<3> ADDR<2> ADDR<1> ADDR<0> ++ ADDR_COL<1> ADDR_COL<0> ADDR_DEC<7> ADDR_DEC<6> ADDR_DEC<5> ADDR_DEC<4> ++ ADDR_DEC<3> ADDR_DEC<2> ADDR_DEC<1> ADDR_DEC<0> BIST_ADDR<3> BIST_ADDR<2> ++ BIST_ADDR<1> BIST_ADDR<0> BIST_EN_I VDD VSS +XI15 ADDR_COL<1> VDD VSS / RSC_IHPSG13_TIEL +XI14 addr_int ADDR_COL<0> VDD VSS / RSC_IHPSG13_CBUFX2 +XDFF<3> BIST_EN_I BIST_ADDR<3> ACLK_N ADDR<3> addr_int net7<0> VDD VSS ++ / RSC_IHPSG13_DFNQMX2IX1 +XDFF<2> BIST_EN_I BIST_ADDR<2> ACLK_N ADDR<2> padr_int<2> net7<1> VDD ++ VSS / RSC_IHPSG13_DFNQMX2IX1 +XDFF<1> BIST_EN_I BIST_ADDR<1> ACLK_N ADDR<1> padr_int<1> net7<2> VDD ++ VSS / RSC_IHPSG13_DFNQMX2IX1 +XDFF<0> BIST_EN_I BIST_ADDR<0> ACLK_N ADDR<0> padr_int<0> net7<3> VDD ++ VSS / RSC_IHPSG13_DFNQMX2IX1 +XI1<7> PADR<0> PADR<1> PADR<2> addr_n<7> VDD VSS / RSC_IHPSG13_NAND3X2 +XI1<6> NADR<0> PADR<1> PADR<2> addr_n<6> VDD VSS / RSC_IHPSG13_NAND3X2 +XI1<5> PADR<0> NADR<1> PADR<2> addr_n<5> VDD VSS / RSC_IHPSG13_NAND3X2 +XI1<4> NADR<0> NADR<1> PADR<2> addr_n<4> VDD VSS / RSC_IHPSG13_NAND3X2 +XI1<3> PADR<0> PADR<1> NADR<2> addr_n<3> VDD VSS / RSC_IHPSG13_NAND3X2 +XI1<2> NADR<0> PADR<1> NADR<2> addr_n<2> VDD VSS / RSC_IHPSG13_NAND3X2 +XI1<1> PADR<0> NADR<1> NADR<2> addr_n<1> VDD VSS / RSC_IHPSG13_NAND3X2 +XI1<0> NADR<0> NADR<1> NADR<2> addr_n<0> VDD VSS / RSC_IHPSG13_NAND3X2 +XI13<2> NADR<2> PADR<2> VDD VSS / RSC_IHPSG13_INVX2 +XI13<1> NADR<1> PADR<1> VDD VSS / RSC_IHPSG13_INVX2 +XI13<0> NADR<0> PADR<0> VDD VSS / RSC_IHPSG13_INVX2 +XI3<2> padr_int<2> NADR<2> VDD VSS / RSC_IHPSG13_INVX2 +XI3<1> padr_int<1> NADR<1> VDD VSS / RSC_IHPSG13_INVX2 +XI3<0> padr_int<0> NADR<0> VDD VSS / RSC_IHPSG13_INVX2 +XI2<7> addr_n<7> ADDR_DEC<7> VDD VSS / RSC_IHPSG13_INVX2 +XI2<6> addr_n<6> ADDR_DEC<6> VDD VSS / RSC_IHPSG13_INVX2 +XI2<5> addr_n<5> ADDR_DEC<5> VDD VSS / RSC_IHPSG13_INVX2 +XI2<4> addr_n<4> ADDR_DEC<4> VDD VSS / RSC_IHPSG13_INVX2 +XI2<3> addr_n<3> ADDR_DEC<3> VDD VSS / RSC_IHPSG13_INVX2 +XI2<2> addr_n<2> ADDR_DEC<2> VDD VSS / RSC_IHPSG13_INVX2 +XI2<1> addr_n<1> ADDR_DEC<1> VDD VSS / RSC_IHPSG13_INVX2 +XI2<0> addr_n<0> ADDR_DEC<0> VDD VSS / RSC_IHPSG13_INVX2 +XI16<3> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI16<2> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI16<1> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI17<2> VDD VSS / RSC_IHPSG13_FILLCAP4 +XI17<1> VDD VSS / RSC_IHPSG13_FILLCAP4 +.ENDS +.SUBCKT RSC_IHPSG13_AND2X4 A B Z VDD VSS +MN3 Z net6 VSS VSS sg13_lv_nmos m=1 w=1.96u l=130.00n ng=2 nrd=0 nrs=0 +MN4 net9 B VSS VSS sg13_lv_nmos m=1 w=500.0n l=130.00n ng=1 nrd=0 nrs=0 +MN6 net6 A net9 VSS sg13_lv_nmos m=1 w=500.0n l=130.00n ng=1 nrd=0 nrs=0 +MP2 Z net6 VDD VDD sg13_lv_pmos m=1 w=3.24u l=130.00n ng=2 nrd=0 nrs=0 +MP0 net6 B VDD VDD sg13_lv_pmos m=1 w=860.00n l=130.00n ng=1 nrd=0 ++ nrs=0 +MP1 net6 A VDD VDD sg13_lv_pmos m=1 w=860.00n l=130.00n ng=1 nrd=0 ++ nrs=0 +.ENDS +.SUBCKT RM_IHPSG13_512x16_c2_1P_COLCTRL4 A_ADDR_COL A_ADDR_DEC<7> A_ADDR_DEC<6> ++ A_ADDR_DEC<5> A_ADDR_DEC<4> A_ADDR_DEC<3> A_ADDR_DEC<2> A_ADDR_DEC<1> ++ A_ADDR_DEC<0> A_BIST_BM_I A_BIST_DW_I A_BIST_EN_I A_BLC<15> A_BLC<14> ++ A_BLC<13> A_BLC<12> A_BLC<11> A_BLC<10> A_BLC<9> A_BLC<8> A_BLC<7> A_BLC<6> ++ A_BLC<5> A_BLC<4> A_BLC<3> A_BLC<2> A_BLC<1> A_BLC<0> A_BLT<15> A_BLT<14> ++ A_BLT<13> A_BLT<12> A_BLT<11> A_BLT<10> A_BLT<9> A_BLT<8> A_BLT<7> A_BLT<6> ++ A_BLT<5> A_BLT<4> A_BLT<3> A_BLT<2> A_BLT<1> A_BLT<0> A_BM_I A_DCLK_B_L ++ A_DCLK_B_R A_DCLK_L A_DCLK_R A_DR_O A_DW_I A_RCLK_B_L A_RCLK_B_R A_RCLK_L ++ A_RCLK_R A_TIEH_O A_WCLK_B_L A_WCLK_B_R A_WCLK_L A_WCLK_R VDD VSS +XA_I80 A_WCLK_B_L A_RCLK_B_L net21 VDD VSS / RSC_IHPSG13_AND2X2 +XA_I76 A_DO_WRITE_P A_DI_N A_WR_ZERO VDD VSS / RSC_IHPSG13_AND2X4 +XA_I75 A_DI_R A_DO_WRITE_P A_WR_ONE VDD VSS / RSC_IHPSG13_AND2X4 +XA_CAPS<8> VDD VSS / RSC_IHPSG13_FILLCAP4 +XA_CAPS<7> VDD VSS / RSC_IHPSG13_FILLCAP4 +XA_CAPS<6> VDD VSS / RSC_IHPSG13_FILLCAP4 +XA_CAPS<5> VDD VSS / RSC_IHPSG13_FILLCAP4 +XA_CAPS<4> VDD VSS / RSC_IHPSG13_FILLCAP4 +XA_CAPS<3> VDD VSS / RSC_IHPSG13_FILLCAP4 +XA_CAPS<2> VDD VSS / RSC_IHPSG13_FILLCAP4 +XA_CAPS<1> VDD VSS / RSC_IHPSG13_FILLCAP4 +XA_I69 A_DCLK_L A_DCLK_B_L VDD VSS / RSC_IHPSG13_CINVX4 +XA_I50 A_WCLK_L A_WCLK_B_L VDD VSS / RSC_IHPSG13_CINVX4 +XA_EBUF A_RCLK_L A_RCLK_B_L VDD VSS / RSC_IHPSG13_CINVX4 +XA_INV<1> A_N0 A_P0 VDD VSS / RSC_IHPSG13_CINVX4 +XA_INV<0> A_ADDR_COL A_N0 VDD VSS / RSC_IHPSG13_CINVX4 +XA_I81<1> net21 A_PRE_N VDD VSS / RSC_IHPSG13_CINVX4_WN +XA_I81<0> net21 A_PRE_N VDD VSS / RSC_IHPSG13_CINVX4_WN +XA_BLTMUX<15> A_BLC<15> A_BLC_SEL A_BLT<15> A_BLT_SEL A_PRE_N A_SEL_P<15> ++ A_WR_ONE A_WR_ZERO VDD VSS / RM_IHPSG13_512x16_c2_1P_BLDRV +XA_BLTMUX<14> A_BLC<14> A_BLC_SEL A_BLT<14> A_BLT_SEL A_PRE_N A_SEL_P<14> ++ A_WR_ONE A_WR_ZERO VDD VSS / RM_IHPSG13_512x16_c2_1P_BLDRV +XA_BLTMUX<13> A_BLC<13> A_BLC_SEL A_BLT<13> A_BLT_SEL A_PRE_N A_SEL_P<13> ++ A_WR_ONE A_WR_ZERO VDD VSS / RM_IHPSG13_512x16_c2_1P_BLDRV +XA_BLTMUX<12> A_BLC<12> A_BLC_SEL A_BLT<12> A_BLT_SEL A_PRE_N A_SEL_P<12> ++ A_WR_ONE A_WR_ZERO VDD VSS / RM_IHPSG13_512x16_c2_1P_BLDRV +XA_BLTMUX<11> A_BLC<11> A_BLC_SEL A_BLT<11> A_BLT_SEL A_PRE_N A_SEL_P<11> ++ A_WR_ONE A_WR_ZERO VDD VSS / RM_IHPSG13_512x16_c2_1P_BLDRV +XA_BLTMUX<10> A_BLC<10> A_BLC_SEL A_BLT<10> A_BLT_SEL A_PRE_N A_SEL_P<10> ++ A_WR_ONE A_WR_ZERO VDD VSS / RM_IHPSG13_512x16_c2_1P_BLDRV +XA_BLTMUX<9> A_BLC<9> A_BLC_SEL A_BLT<9> A_BLT_SEL A_PRE_N A_SEL_P<9> A_WR_ONE ++ A_WR_ZERO VDD VSS / RM_IHPSG13_512x16_c2_1P_BLDRV +XA_BLTMUX<8> A_BLC<8> A_BLC_SEL A_BLT<8> A_BLT_SEL A_PRE_N A_SEL_P<8> A_WR_ONE ++ A_WR_ZERO VDD VSS / RM_IHPSG13_512x16_c2_1P_BLDRV +XA_BLTMUX<7> A_BLC<7> A_BLC_SEL A_BLT<7> A_BLT_SEL A_PRE_N A_SEL_P<7> A_WR_ONE ++ A_WR_ZERO VDD VSS / RM_IHPSG13_512x16_c2_1P_BLDRV +XA_BLTMUX<6> A_BLC<6> A_BLC_SEL A_BLT<6> A_BLT_SEL A_PRE_N A_SEL_P<6> A_WR_ONE ++ A_WR_ZERO VDD VSS / RM_IHPSG13_512x16_c2_1P_BLDRV +XA_BLTMUX<5> A_BLC<5> A_BLC_SEL A_BLT<5> A_BLT_SEL A_PRE_N A_SEL_P<5> A_WR_ONE ++ A_WR_ZERO VDD VSS / RM_IHPSG13_512x16_c2_1P_BLDRV +XA_BLTMUX<4> A_BLC<4> A_BLC_SEL A_BLT<4> A_BLT_SEL A_PRE_N A_SEL_P<4> A_WR_ONE ++ A_WR_ZERO VDD VSS / RM_IHPSG13_512x16_c2_1P_BLDRV +XA_BLTMUX<3> A_BLC<3> A_BLC_SEL A_BLT<3> A_BLT_SEL A_PRE_N A_SEL_P<3> A_WR_ONE ++ A_WR_ZERO VDD VSS / RM_IHPSG13_512x16_c2_1P_BLDRV +XA_BLTMUX<2> A_BLC<2> A_BLC_SEL A_BLT<2> A_BLT_SEL A_PRE_N A_SEL_P<2> A_WR_ONE ++ A_WR_ZERO VDD VSS / RM_IHPSG13_512x16_c2_1P_BLDRV +XA_BLTMUX<1> A_BLC<1> A_BLC_SEL A_BLT<1> A_BLT_SEL A_PRE_N A_SEL_P<1> A_WR_ONE ++ A_WR_ZERO VDD VSS / RM_IHPSG13_512x16_c2_1P_BLDRV +XA_BLTMUX<0> A_BLC<0> A_BLC_SEL A_BLT<0> A_BLT_SEL A_PRE_N A_SEL_P<0> A_WR_ONE ++ A_WR_ZERO VDD VSS / RM_IHPSG13_512x16_c2_1P_BLDRV +XA_R2 A_RCLK_L A_RCLK_R / RSC_IHPSG13_MET3RES +XA_I87 A_WCLK_L A_WCLK_R / RSC_IHPSG13_MET3RES +XA_I88 A_DCLK_L A_DCLK_R / RSC_IHPSG13_MET3RES +XA_I89 A_DCLK_B_L A_DCLK_B_R / RSC_IHPSG13_MET3RES +XA_I90 A_WCLK_B_L A_WCLK_B_R / RSC_IHPSG13_MET3RES +XA_I91 A_RCLK_B_L A_RCLK_B_R / RSC_IHPSG13_MET3RES +XA_ISENSE A_SAE A_BLC_SEL A_BLT_SEL net19 net20 VDD VSS / ++ RSC_IHPSG13_DFPQD_MSAFFX2 +XA_I51 net19 A_DR_O VDD VSS / RSC_IHPSG13_INVX4 +XA_I78 A_RCLK_B_L A_SAE VDD VSS / RSC_IHPSG13_CBUFX2 +XA_DREG A_BIST_EN_I A_BIST_DW_I A_DCLK_B_L A_DW_I A_DI_R net22 VDD VSS ++ / RSC_IHPSG13_DFNQMX2IX1 +XA_BREG A_BIST_EN_I A_BIST_BM_I A_DCLK_B_L A_BM_I A_BM_R net24 VDD VSS ++ / RSC_IHPSG13_DFNQMX2IX1 +XA_DEC3INV<15> net23<0> A_SEL_P<15> VDD VSS / RSC_IHPSG13_INVX2 +XA_DEC3INV<14> net23<1> A_SEL_P<14> VDD VSS / RSC_IHPSG13_INVX2 +XA_DEC3INV<13> net23<2> A_SEL_P<13> VDD VSS / RSC_IHPSG13_INVX2 +XA_DEC3INV<12> net23<3> A_SEL_P<12> VDD VSS / RSC_IHPSG13_INVX2 +XA_DEC3INV<11> net23<4> A_SEL_P<11> VDD VSS / RSC_IHPSG13_INVX2 +XA_DEC3INV<10> net23<5> A_SEL_P<10> VDD VSS / RSC_IHPSG13_INVX2 +XA_DEC3INV<9> net23<6> A_SEL_P<9> VDD VSS / RSC_IHPSG13_INVX2 +XA_DEC3INV<8> net23<7> A_SEL_P<8> VDD VSS / RSC_IHPSG13_INVX2 +XA_DEC3INV<7> net23<8> A_SEL_P<7> VDD VSS / RSC_IHPSG13_INVX2 +XA_DEC3INV<6> net23<9> A_SEL_P<6> VDD VSS / RSC_IHPSG13_INVX2 +XA_DEC3INV<5> net23<10> A_SEL_P<5> VDD VSS / RSC_IHPSG13_INVX2 +XA_DEC3INV<4> net23<11> A_SEL_P<4> VDD VSS / RSC_IHPSG13_INVX2 +XA_DEC3INV<3> net23<12> A_SEL_P<3> VDD VSS / RSC_IHPSG13_INVX2 +XA_DEC3INV<2> net23<13> A_SEL_P<2> VDD VSS / RSC_IHPSG13_INVX2 +XA_DEC3INV<1> net23<14> A_SEL_P<1> VDD VSS / RSC_IHPSG13_INVX2 +XA_DEC3INV<0> net23<15> A_SEL_P<0> VDD VSS / RSC_IHPSG13_INVX2 +XA_I83 A_BM_R A_BM_N VDD VSS / RSC_IHPSG13_INVX2 +XA_I49 A_DI_R A_DI_N VDD VSS / RSC_IHPSG13_INVX2 +XA_I70<4> VDD VSS / RSC_IHPSG13_FILLCAP8 +XA_I70<3> VDD VSS / RSC_IHPSG13_FILLCAP8 +XA_I70<2> VDD VSS / RSC_IHPSG13_FILLCAP8 +XA_I70<1> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI73<14> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI73<13> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI73<12> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI73<11> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI73<10> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI73<9> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI73<8> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI73<7> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI73<6> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI73<5> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI73<4> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI73<3> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI73<2> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI73<1> VDD VSS / RSC_IHPSG13_FILLCAP8 +XA_I44 A_BM_N A_WCLK_B_L A_DO_WRITE_P VDD VSS / RSC_IHPSG13_NOR2X2 +XA_DEC3<15> A_P0 A_ADDR_DEC<7> net23<0> VDD VSS / RSC_IHPSG13_NAND2X2 +XA_DEC3<14> A_P0 A_ADDR_DEC<6> net23<1> VDD VSS / RSC_IHPSG13_NAND2X2 +XA_DEC3<13> A_P0 A_ADDR_DEC<5> net23<2> VDD VSS / RSC_IHPSG13_NAND2X2 +XA_DEC3<12> A_P0 A_ADDR_DEC<4> net23<3> VDD VSS / RSC_IHPSG13_NAND2X2 +XA_DEC3<11> A_P0 A_ADDR_DEC<3> net23<4> VDD VSS / RSC_IHPSG13_NAND2X2 +XA_DEC3<10> A_P0 A_ADDR_DEC<2> net23<5> VDD VSS / RSC_IHPSG13_NAND2X2 +XA_DEC3<9> A_P0 A_ADDR_DEC<1> net23<6> VDD VSS / RSC_IHPSG13_NAND2X2 +XA_DEC3<8> A_P0 A_ADDR_DEC<0> net23<7> VDD VSS / RSC_IHPSG13_NAND2X2 +XA_DEC3<7> A_N0 A_ADDR_DEC<7> net23<8> VDD VSS / RSC_IHPSG13_NAND2X2 +XA_DEC3<6> A_N0 A_ADDR_DEC<6> net23<9> VDD VSS / RSC_IHPSG13_NAND2X2 +XA_DEC3<5> A_N0 A_ADDR_DEC<5> net23<10> VDD VSS / RSC_IHPSG13_NAND2X2 +XA_DEC3<4> A_N0 A_ADDR_DEC<4> net23<11> VDD VSS / RSC_IHPSG13_NAND2X2 +XA_DEC3<3> A_N0 A_ADDR_DEC<3> net23<12> VDD VSS / RSC_IHPSG13_NAND2X2 +XA_DEC3<2> A_N0 A_ADDR_DEC<2> net23<13> VDD VSS / RSC_IHPSG13_NAND2X2 +XA_DEC3<1> A_N0 A_ADDR_DEC<1> net23<14> VDD VSS / RSC_IHPSG13_NAND2X2 +XA_DEC3<0> A_N0 A_ADDR_DEC<0> net23<15> VDD VSS / RSC_IHPSG13_NAND2X2 +XA_BM_TIEH A_TIEH_O VDD VSS / RSC_IHPSG13_TIEH +.ENDS + + +.SUBCKT RM_IHPSG13_512x16_c2_1P_COLDEC3 ACLK_N ADDR<2> ADDR<1> ADDR<0> ADDR_COL<1> ++ ADDR_COL<0> ADDR_DEC<7> ADDR_DEC<6> ADDR_DEC<5> ADDR_DEC<4> ADDR_DEC<3> ++ ADDR_DEC<2> ADDR_DEC<1> ADDR_DEC<0> BIST_ADDR<2> BIST_ADDR<1> BIST_ADDR<0> ++ BIST_EN_I VDD VSS +XI15<1> ADDR_COL<1> VDD VSS / RSC_IHPSG13_TIEL +XI15<0> ADDR_COL<0> VDD VSS / RSC_IHPSG13_TIEL +XI1<7> PADR<0> PADR<1> PADR<2> addr_n<7> VDD VSS / RSC_IHPSG13_NAND3X2 +XI1<6> NADR<0> PADR<1> PADR<2> addr_n<6> VDD VSS / RSC_IHPSG13_NAND3X2 +XI1<5> PADR<0> NADR<1> PADR<2> addr_n<5> VDD VSS / RSC_IHPSG13_NAND3X2 +XI1<4> NADR<0> NADR<1> PADR<2> addr_n<4> VDD VSS / RSC_IHPSG13_NAND3X2 +XI1<3> PADR<0> PADR<1> NADR<2> addr_n<3> VDD VSS / RSC_IHPSG13_NAND3X2 +XI1<2> NADR<0> PADR<1> NADR<2> addr_n<2> VDD VSS / RSC_IHPSG13_NAND3X2 +XI1<1> PADR<0> NADR<1> NADR<2> addr_n<1> VDD VSS / RSC_IHPSG13_NAND3X2 +XI1<0> NADR<0> NADR<1> NADR<2> addr_n<0> VDD VSS / RSC_IHPSG13_NAND3X2 +XDFF<2> BIST_EN_I BIST_ADDR<2> ACLK_N ADDR<2> padr_int<2> net6<0> VDD ++ VSS / RSC_IHPSG13_DFNQMX2IX1 +XDFF<1> BIST_EN_I BIST_ADDR<1> ACLK_N ADDR<1> padr_int<1> net6<1> VDD ++ VSS / RSC_IHPSG13_DFNQMX2IX1 +XDFF<0> BIST_EN_I BIST_ADDR<0> ACLK_N ADDR<0> padr_int<0> net6<2> VDD ++ VSS / RSC_IHPSG13_DFNQMX2IX1 +XI17<2> VDD VSS / RSC_IHPSG13_FILLCAP4 +XI17<1> VDD VSS / RSC_IHPSG13_FILLCAP4 +XI13<2> NADR<2> PADR<2> VDD VSS / RSC_IHPSG13_INVX2 +XI13<1> NADR<1> PADR<1> VDD VSS / RSC_IHPSG13_INVX2 +XI13<0> NADR<0> PADR<0> VDD VSS / RSC_IHPSG13_INVX2 +XI3<2> padr_int<2> NADR<2> VDD VSS / RSC_IHPSG13_INVX2 +XI3<1> padr_int<1> NADR<1> VDD VSS / RSC_IHPSG13_INVX2 +XI3<0> padr_int<0> NADR<0> VDD VSS / RSC_IHPSG13_INVX2 +XI2<7> addr_n<7> ADDR_DEC<7> VDD VSS / RSC_IHPSG13_INVX2 +XI2<6> addr_n<6> ADDR_DEC<6> VDD VSS / RSC_IHPSG13_INVX2 +XI2<5> addr_n<5> ADDR_DEC<5> VDD VSS / RSC_IHPSG13_INVX2 +XI2<4> addr_n<4> ADDR_DEC<4> VDD VSS / RSC_IHPSG13_INVX2 +XI2<3> addr_n<3> ADDR_DEC<3> VDD VSS / RSC_IHPSG13_INVX2 +XI2<2> addr_n<2> ADDR_DEC<2> VDD VSS / RSC_IHPSG13_INVX2 +XI2<1> addr_n<1> ADDR_DEC<1> VDD VSS / RSC_IHPSG13_INVX2 +XI2<0> addr_n<0> ADDR_DEC<0> VDD VSS / RSC_IHPSG13_INVX2 +XI16<6> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI16<5> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI16<4> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI16<3> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI16<2> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI16<1> VDD VSS / RSC_IHPSG13_FILLCAP8 +.ENDS +.SUBCKT RM_IHPSG13_512x16_c2_1P_COLCTRL3 A_ADDR_DEC<7> A_ADDR_DEC<6> A_ADDR_DEC<5> ++ A_ADDR_DEC<4> A_ADDR_DEC<3> A_ADDR_DEC<2> A_ADDR_DEC<1> A_ADDR_DEC<0> ++ A_BIST_BM_I A_BIST_DW_I A_BIST_EN_I A_BLC<7> A_BLC<6> A_BLC<5> A_BLC<4> ++ A_BLC<3> A_BLC<2> A_BLC<1> A_BLC<0> A_BLT<7> A_BLT<6> A_BLT<5> A_BLT<4> ++ A_BLT<3> A_BLT<2> A_BLT<1> A_BLT<0> A_BM_I A_DCLK_B_L A_DCLK_B_R A_DCLK_L ++ A_DCLK_R A_DR_O A_DW_I A_RCLK_B_L A_RCLK_B_R A_RCLK_L A_RCLK_R A_TIEH_O ++ A_WCLK_B_L A_WCLK_B_R A_WCLK_L A_WCLK_R VDD VSS +XA_DREG A_BIST_EN_I A_BIST_DW_I A_DCLK_B_L A_DW_I A_DI_R net22 VDD VSS ++ / RSC_IHPSG13_DFNQMX2IX1 +XA_BREG A_BIST_EN_I A_BIST_BM_I A_DCLK_B_R A_BM_I A_BM_R net23 VDD VSS ++ / RSC_IHPSG13_DFNQMX2IX1 +XA_I70<8> VDD VSS / RSC_IHPSG13_FILLCAP8 +XA_I70<7> VDD VSS / RSC_IHPSG13_FILLCAP8 +XA_I70<6> VDD VSS / RSC_IHPSG13_FILLCAP8 +XA_I70<5> VDD VSS / RSC_IHPSG13_FILLCAP8 +XA_I70<4> VDD VSS / RSC_IHPSG13_FILLCAP8 +XA_I70<3> VDD VSS / RSC_IHPSG13_FILLCAP8 +XA_I70<2> VDD VSS / RSC_IHPSG13_FILLCAP8 +XA_I70<1> VDD VSS / RSC_IHPSG13_FILLCAP8 +XA_I51 net19 A_DR_O VDD VSS / RSC_IHPSG13_INVX4 +XA_I44 A_BM_N A_WCLK_B_R A_DO_WRITE_P VDD VSS / RSC_IHPSG13_NOR2X2 +XA_BM_TIEH A_TIEH_O VDD VSS / RSC_IHPSG13_TIEH +XA_BLTMUX<7> A_BLC<7> A_BLC_SEL A_BLT<7> A_BLT_SEL A_PRE_N A_ADDR_DEC<7> ++ A_WR_ONE A_WR_ZERO VDD VSS / RM_IHPSG13_512x16_c2_1P_BLDRV +XA_BLTMUX<6> A_BLC<6> A_BLC_SEL A_BLT<6> A_BLT_SEL A_PRE_N A_ADDR_DEC<6> ++ A_WR_ONE A_WR_ZERO VDD VSS / RM_IHPSG13_512x16_c2_1P_BLDRV +XA_BLTMUX<5> A_BLC<5> A_BLC_SEL A_BLT<5> A_BLT_SEL A_PRE_N A_ADDR_DEC<5> ++ A_WR_ONE A_WR_ZERO VDD VSS / RM_IHPSG13_512x16_c2_1P_BLDRV +XA_BLTMUX<4> A_BLC<4> A_BLC_SEL A_BLT<4> A_BLT_SEL A_PRE_N A_ADDR_DEC<4> ++ A_WR_ONE A_WR_ZERO VDD VSS / RM_IHPSG13_512x16_c2_1P_BLDRV +XA_BLTMUX<3> A_BLC<3> A_BLC_SEL A_BLT<3> A_BLT_SEL A_PRE_N A_ADDR_DEC<3> ++ A_WR_ONE A_WR_ZERO VDD VSS / RM_IHPSG13_512x16_c2_1P_BLDRV +XA_BLTMUX<2> A_BLC<2> A_BLC_SEL A_BLT<2> A_BLT_SEL A_PRE_N A_ADDR_DEC<2> ++ A_WR_ONE A_WR_ZERO VDD VSS / RM_IHPSG13_512x16_c2_1P_BLDRV +XA_BLTMUX<1> A_BLC<1> A_BLC_SEL A_BLT<1> A_BLT_SEL A_PRE_N A_ADDR_DEC<1> ++ A_WR_ONE A_WR_ZERO VDD VSS / RM_IHPSG13_512x16_c2_1P_BLDRV +XA_BLTMUX<0> A_BLC<0> A_BLC_SEL A_BLT<0> A_BLT_SEL A_PRE_N A_ADDR_DEC<0> ++ A_WR_ONE A_WR_ZERO VDD VSS / RM_IHPSG13_512x16_c2_1P_BLDRV +XA_I49 A_DI_R A_DI_N VDD VSS / RSC_IHPSG13_INVX2 +XA_I83 A_BM_R A_BM_N VDD VSS / RSC_IHPSG13_INVX2 +XA_I69 A_DCLK_L A_DCLK_B_L VDD VSS / RSC_IHPSG13_CINVX2 +XA_I50 A_WCLK_L A_WCLK_B_L VDD VSS / RSC_IHPSG13_CINVX2 +XA_EBUF A_RCLK_L A_RCLK_B_L VDD VSS / RSC_IHPSG13_CINVX2 +XA_I78 A_RCLK_B_L A_SAE VDD VSS / RSC_IHPSG13_CBUFX2 +XA_I88 A_DCLK_L A_DCLK_R / RSC_IHPSG13_MET3RES +XA_I87 A_WCLK_L A_WCLK_R / RSC_IHPSG13_MET3RES +XA_R2 A_RCLK_L A_RCLK_R / RSC_IHPSG13_MET3RES +XA_I91 A_RCLK_B_L A_RCLK_B_R / RSC_IHPSG13_MET3RES +XA_I90 A_WCLK_B_L A_WCLK_B_R / RSC_IHPSG13_MET3RES +XA_I89 A_DCLK_B_L A_DCLK_B_R / RSC_IHPSG13_MET3RES +XA_I80 A_WCLK_B_R A_RCLK_B_R net21 VDD VSS / RSC_IHPSG13_AND2X2 +XA_I76 A_DI_N A_DO_WRITE_P A_WR_ZERO VDD VSS / RSC_IHPSG13_AND2X2 +XA_I75 A_DI_R A_DO_WRITE_P A_WR_ONE VDD VSS / RSC_IHPSG13_AND2X2 +XA_ISENSE A_SAE A_BLC_SEL A_BLT_SEL net19 net20 VDD VSS / ++ RSC_IHPSG13_DFPQD_MSAFFX2 +XA_I81 net21 A_PRE_N VDD VSS / RSC_IHPSG13_CINVX4_WN +XA_CAPS<5> VDD VSS / RSC_IHPSG13_FILLCAP4 +XA_CAPS<4> VDD VSS / RSC_IHPSG13_FILLCAP4 +XA_CAPS<3> VDD VSS / RSC_IHPSG13_FILLCAP4 +XA_CAPS<2> VDD VSS / RSC_IHPSG13_FILLCAP4 +XA_CAPS<1> VDD VSS / RSC_IHPSG13_FILLCAP4 +.ENDS + +.SUBCKT RM_IHPSG13_512x16_c2_2P_BITKIT_16x2_CORNER VDD_CORE VSS +XI16 VDD_CORE VSS VDD_CORE VSS / ++ RM_IHPSG13_512x16_c2_1P_BITKIT_CORNER +.ENDS +.SUBCKT RM_IHPSG13_512x16_c2_2P_BITKIT_EDGE_LR A_WL B_WL NW PW VDD VSS +MN1 VSS A_WL VSS VSS sg13_lv_nmos m=1 w=300.0n l=130.00n ng=1 nrd=0 nrs=0 +MN0 VSS B_WL VSS VSS sg13_lv_nmos m=1 w=300.0n l=130.00n ng=1 nrd=0 nrs=0 +.ENDS +.SUBCKT RM_IHPSG13_512x16_c2_2P_BITKIT_16x2_EDGE_LR A_WL<15> A_WL<14> A_WL<13> A_WL<12> ++ A_WL<11> A_WL<10> A_WL<9> A_WL<8> A_WL<7> A_WL<6> A_WL<5> A_WL<4> A_WL<3> ++ A_WL<2> A_WL<1> A_WL<0> B_WL<15> B_WL<14> B_WL<13> B_WL<12> B_WL<11> ++ B_WL<10> B_WL<9> B_WL<8> B_WL<7> B_WL<6> B_WL<5> B_WL<4> B_WL<3> B_WL<2> ++ B_WL<1> B_WL<0> VDD_CORE VSS +XI0<15> A_WL<15> B_WL<15> VDD_CORE VSS VDD_CORE VSS ++ / RM_IHPSG13_512x16_c2_2P_BITKIT_EDGE_LR +XI0<14> A_WL<14> B_WL<14> VDD_CORE VSS VDD_CORE VSS ++ / RM_IHPSG13_512x16_c2_2P_BITKIT_EDGE_LR +XI0<13> A_WL<13> B_WL<13> VDD_CORE VSS VDD_CORE VSS ++ / RM_IHPSG13_512x16_c2_2P_BITKIT_EDGE_LR +XI0<12> A_WL<12> B_WL<12> VDD_CORE VSS VDD_CORE VSS ++ / RM_IHPSG13_512x16_c2_2P_BITKIT_EDGE_LR +XI0<11> A_WL<11> B_WL<11> VDD_CORE VSS VDD_CORE VSS ++ / RM_IHPSG13_512x16_c2_2P_BITKIT_EDGE_LR +XI0<10> A_WL<10> B_WL<10> VDD_CORE VSS VDD_CORE VSS ++ / RM_IHPSG13_512x16_c2_2P_BITKIT_EDGE_LR +XI0<9> A_WL<9> B_WL<9> VDD_CORE VSS VDD_CORE VSS / ++ RM_IHPSG13_512x16_c2_2P_BITKIT_EDGE_LR +XI0<8> A_WL<8> B_WL<8> VDD_CORE VSS VDD_CORE VSS / ++ RM_IHPSG13_512x16_c2_2P_BITKIT_EDGE_LR +XI0<7> A_WL<7> B_WL<7> VDD_CORE VSS VDD_CORE VSS / ++ RM_IHPSG13_512x16_c2_2P_BITKIT_EDGE_LR +XI0<6> A_WL<6> B_WL<6> VDD_CORE VSS VDD_CORE VSS / ++ RM_IHPSG13_512x16_c2_2P_BITKIT_EDGE_LR +XI0<5> A_WL<5> B_WL<5> VDD_CORE VSS VDD_CORE VSS / ++ RM_IHPSG13_512x16_c2_2P_BITKIT_EDGE_LR +XI0<4> A_WL<4> B_WL<4> VDD_CORE VSS VDD_CORE VSS / ++ RM_IHPSG13_512x16_c2_2P_BITKIT_EDGE_LR +XI0<3> A_WL<3> B_WL<3> VDD_CORE VSS VDD_CORE VSS / ++ RM_IHPSG13_512x16_c2_2P_BITKIT_EDGE_LR +XI0<2> A_WL<2> B_WL<2> VDD_CORE VSS VDD_CORE VSS / ++ RM_IHPSG13_512x16_c2_2P_BITKIT_EDGE_LR +XI0<1> A_WL<1> B_WL<1> VDD_CORE VSS VDD_CORE VSS / ++ RM_IHPSG13_512x16_c2_2P_BITKIT_EDGE_LR +XI0<0> A_WL<0> B_WL<0> VDD_CORE VSS VDD_CORE VSS / ++ RM_IHPSG13_512x16_c2_2P_BITKIT_EDGE_LR +.ENDS +.SUBCKT RM_IHPSG13_512x16_c2_2P_BITKIT_CELL A_BLC_BOT A_BLC_TOP A_BLT_BOT A_BLT_TOP ++ A_LWL A_RWL B_BLC_BOT B_BLC_TOP B_BLT_BOT B_BLT_TOP B_LWL B_RWL NW PW VDD VSS +MN5 NC B_RWL B_BLC_BOT PW sg13_lv_nmos m=1 w=300.0n l=130.00n ng=1 nrd=0 nrs=0 +MN4 B_BLT_BOT B_LWL NT PW sg13_lv_nmos m=1 w=300.0n l=130.00n ng=1 nrd=0 nrs=0 +MN0 NC NT VSS PW sg13_lv_nmos m=1 w=600.0n l=130.00n ng=2 nrd=0 nrs=0 +MN1 NT NC VSS PW sg13_lv_nmos m=1 w=600.0n l=130.00n ng=2 nrd=0 nrs=0 +MN3 NC A_RWL A_BLC_TOP PW sg13_lv_nmos m=1 w=300.0n l=130.00n ng=1 nrd=0 nrs=0 +MN2 A_BLT_TOP A_LWL NT PW sg13_lv_nmos m=1 w=300.0n l=130.00n ng=1 nrd=0 nrs=0 +MP1 NT NC VDD NW sg13_lv_pmos m=1 w=150.00n l=130.00n ng=1 nrd=0 nrs=0 +MP0 NC NT VDD NW sg13_lv_pmos m=1 w=150.00n l=130.00n ng=1 nrd=0 nrs=0 +R5 B_RWL B_LWL lvsres w=2.6e-07 l=6e-07 +R4 B_BLC_BOT B_BLC_TOP lvsres w=2.6e-07 l=6e-07 +R3 B_BLT_BOT B_BLT_TOP lvsres w=2.6e-07 l=6e-07 +R1 A_BLC_BOT A_BLC_TOP lvsres w=2.6e-07 l=6e-07 +R0 A_BLT_BOT A_BLT_TOP lvsres w=2.6e-07 l=6e-07 +R2 A_RWL A_LWL lvsres w=2.6e-07 l=6e-07 +.ENDS +.SUBCKT RM_IHPSG13_512x16_c2_2P_BITKIT_16x2_SRAM A_BLC_BOT<1> A_BLC_BOT<0> A_BLC_TOP<1> ++ A_BLC_TOP<0> A_BLT_BOT<1> A_BLT_BOT<0> A_BLT_TOP<1> A_BLT_TOP<0> A_LWL<15> ++ A_LWL<14> A_LWL<13> A_LWL<12> A_LWL<11> A_LWL<10> A_LWL<9> A_LWL<8> A_LWL<7> ++ A_LWL<6> A_LWL<5> A_LWL<4> A_LWL<3> A_LWL<2> A_LWL<1> A_LWL<0> A_RWL<15> ++ A_RWL<14> A_RWL<13> A_RWL<12> A_RWL<11> A_RWL<10> A_RWL<9> A_RWL<8> A_RWL<7> ++ A_RWL<6> A_RWL<5> A_RWL<4> A_RWL<3> A_RWL<2> A_RWL<1> A_RWL<0> B_BLC_BOT<1> ++ B_BLC_BOT<0> B_BLC_TOP<1> B_BLC_TOP<0> B_BLT_BOT<1> B_BLT_BOT<0> ++ B_BLT_TOP<1> B_BLT_TOP<0> B_LWL<15> B_LWL<14> B_LWL<13> B_LWL<12> B_LWL<11> ++ B_LWL<10> B_LWL<9> B_LWL<8> B_LWL<7> B_LWL<6> B_LWL<5> B_LWL<4> B_LWL<3> ++ B_LWL<2> B_LWL<1> B_LWL<0> B_RWL<15> B_RWL<14> B_RWL<13> B_RWL<12> B_RWL<11> ++ B_RWL<10> B_RWL<9> B_RWL<8> B_RWL<7> B_RWL<6> B_RWL<5> B_RWL<4> B_RWL<3> ++ B_RWL<2> B_RWL<1> B_RWL<0> VDD_CORE VSS +XCELL<31> A_BLC_TOP<1> A_RBLC<15> A_BLT_TOP<1> A_RBLT<15> A_XWL<15> A_RWL<15> ++ B_BLC_TOP<1> B_RBLC<15> B_BLT_TOP<1> B_RBLT<15> B_XWL<15> B_RWL<15> ++ VDD_CORE VSS VDD_CORE VSS / ++ RM_IHPSG13_512x16_c2_2P_BITKIT_CELL +XCELL<30> A_RBLC<14> A_RBLC<15> A_RBLT<14> A_RBLT<15> A_XWL<14> A_RWL<14> ++ B_RBLC<14> B_RBLC<15> B_RBLT<14> B_RBLT<15> B_XWL<14> B_RWL<14> VDD_CORE ++ VSS VDD_CORE VSS / RM_IHPSG13_512x16_c2_2P_BITKIT_CELL +XCELL<29> A_RBLC<14> A_RBLC<13> A_RBLT<14> A_RBLT<13> A_XWL<13> A_RWL<13> ++ B_RBLC<14> B_RBLC<13> B_RBLT<14> B_RBLT<13> B_XWL<13> B_RWL<13> VDD_CORE ++ VSS VDD_CORE VSS / RM_IHPSG13_512x16_c2_2P_BITKIT_CELL +XCELL<28> A_RBLC<12> A_RBLC<13> A_RBLT<12> A_RBLT<13> A_XWL<12> A_RWL<12> ++ B_RBLC<12> B_RBLC<13> B_RBLT<12> B_RBLT<13> B_XWL<12> B_RWL<12> VDD_CORE ++ VSS VDD_CORE VSS / RM_IHPSG13_512x16_c2_2P_BITKIT_CELL +XCELL<27> A_RBLC<12> A_RBLC<11> A_RBLT<12> A_RBLT<11> A_XWL<11> A_RWL<11> ++ B_RBLC<12> B_RBLC<11> B_RBLT<12> B_RBLT<11> B_XWL<11> B_RWL<11> VDD_CORE ++ VSS VDD_CORE VSS / RM_IHPSG13_512x16_c2_2P_BITKIT_CELL +XCELL<26> A_RBLC<10> A_RBLC<11> A_RBLT<10> A_RBLT<11> A_XWL<10> A_RWL<10> ++ B_RBLC<10> B_RBLC<11> B_RBLT<10> B_RBLT<11> B_XWL<10> B_RWL<10> VDD_CORE ++ VSS VDD_CORE VSS / RM_IHPSG13_512x16_c2_2P_BITKIT_CELL +XCELL<25> A_RBLC<10> A_RBLC<9> A_RBLT<10> A_RBLT<9> A_XWL<9> A_RWL<9> ++ B_RBLC<10> B_RBLC<9> B_RBLT<10> B_RBLT<9> B_XWL<9> B_RWL<9> VDD_CORE ++ VSS VDD_CORE VSS / RM_IHPSG13_512x16_c2_2P_BITKIT_CELL +XCELL<24> A_RBLC<8> A_RBLC<9> A_RBLT<8> A_RBLT<9> A_XWL<8> A_RWL<8> B_RBLC<8> ++ B_RBLC<9> B_RBLT<8> B_RBLT<9> B_XWL<8> B_RWL<8> VDD_CORE VSS ++ VDD_CORE VSS / RM_IHPSG13_512x16_c2_2P_BITKIT_CELL +XCELL<23> A_RBLC<8> A_RBLC<7> A_RBLT<8> A_RBLT<7> A_XWL<7> A_RWL<7> B_RBLC<8> ++ B_RBLC<7> B_RBLT<8> B_RBLT<7> B_XWL<7> B_RWL<7> VDD_CORE VSS ++ VDD_CORE VSS / RM_IHPSG13_512x16_c2_2P_BITKIT_CELL +XCELL<22> A_RBLC<6> A_RBLC<7> A_RBLT<6> A_RBLT<7> A_XWL<6> A_RWL<6> B_RBLC<6> ++ B_RBLC<7> B_RBLT<6> B_RBLT<7> B_XWL<6> B_RWL<6> VDD_CORE VSS ++ VDD_CORE VSS / RM_IHPSG13_512x16_c2_2P_BITKIT_CELL +XCELL<21> A_RBLC<6> A_RBLC<5> A_RBLT<6> A_RBLT<5> A_XWL<5> A_RWL<5> B_RBLC<6> ++ B_RBLC<5> B_RBLT<6> B_RBLT<5> B_XWL<5> B_RWL<5> VDD_CORE VSS ++ VDD_CORE VSS / RM_IHPSG13_512x16_c2_2P_BITKIT_CELL +XCELL<20> A_RBLC<4> A_RBLC<5> A_RBLT<4> A_RBLT<5> A_XWL<4> A_RWL<4> B_RBLC<4> ++ B_RBLC<5> B_RBLT<4> B_RBLT<5> B_XWL<4> B_RWL<4> VDD_CORE VSS ++ VDD_CORE VSS / RM_IHPSG13_512x16_c2_2P_BITKIT_CELL +XCELL<19> A_RBLC<4> A_RBLC<3> A_RBLT<4> A_RBLT<3> A_XWL<3> A_RWL<3> B_RBLC<4> ++ B_RBLC<3> B_RBLT<4> B_RBLT<3> B_XWL<3> B_RWL<3> VDD_CORE VSS ++ VDD_CORE VSS / RM_IHPSG13_512x16_c2_2P_BITKIT_CELL +XCELL<18> A_RBLC<2> A_RBLC<3> A_RBLT<2> A_RBLT<3> A_XWL<2> A_RWL<2> B_RBLC<2> ++ B_RBLC<3> B_RBLT<2> B_RBLT<3> B_XWL<2> B_RWL<2> VDD_CORE VSS ++ VDD_CORE VSS / RM_IHPSG13_512x16_c2_2P_BITKIT_CELL +XCELL<17> A_RBLC<2> A_RBLC<1> A_RBLT<2> A_RBLT<1> A_XWL<1> A_RWL<1> B_RBLC<2> ++ B_RBLC<1> B_RBLT<2> B_RBLT<1> B_XWL<1> B_RWL<1> VDD_CORE VSS ++ VDD_CORE VSS / RM_IHPSG13_512x16_c2_2P_BITKIT_CELL +XCELL<16> A_BLC_BOT<1> A_RBLC<1> A_BLT_BOT<1> A_RBLT<1> A_XWL<0> A_RWL<0> ++ B_BLC_BOT<1> B_RBLC<1> B_BLT_BOT<1> B_RBLT<1> B_XWL<0> B_RWL<0> VDD_CORE ++ VSS VDD_CORE VSS / RM_IHPSG13_512x16_c2_2P_BITKIT_CELL +XCELL<15> A_BLC_TOP<0> A_LBLC<15> A_BLT_TOP<0> A_LBLT<15> A_LWL<15> A_XWL<15> ++ B_BLC_TOP<0> B_LBLC<15> B_BLT_TOP<0> B_LBLT<15> B_LWL<15> B_XWL<15> ++ VDD_CORE VSS VDD_CORE VSS / ++ RM_IHPSG13_512x16_c2_2P_BITKIT_CELL +XCELL<14> A_LBLC<14> A_LBLC<15> A_LBLT<14> A_LBLT<15> A_LWL<14> A_XWL<14> ++ B_LBLC<14> B_LBLC<15> B_LBLT<14> B_LBLT<15> B_LWL<14> B_XWL<14> VDD_CORE ++ VSS VDD_CORE VSS / RM_IHPSG13_512x16_c2_2P_BITKIT_CELL +XCELL<13> A_LBLC<14> A_LBLC<13> A_LBLT<14> A_LBLT<13> A_LWL<13> A_XWL<13> ++ B_LBLC<14> B_LBLC<13> B_LBLT<14> B_LBLT<13> B_LWL<13> B_XWL<13> VDD_CORE ++ VSS VDD_CORE VSS / RM_IHPSG13_512x16_c2_2P_BITKIT_CELL +XCELL<12> A_LBLC<12> A_LBLC<13> A_LBLT<12> A_LBLT<13> A_LWL<12> A_XWL<12> ++ B_LBLC<12> B_LBLC<13> B_LBLT<12> B_LBLT<13> B_LWL<12> B_XWL<12> VDD_CORE ++ VSS VDD_CORE VSS / RM_IHPSG13_512x16_c2_2P_BITKIT_CELL +XCELL<11> A_LBLC<12> A_LBLC<11> A_LBLT<12> A_LBLT<11> A_LWL<11> A_XWL<11> ++ B_LBLC<12> B_LBLC<11> B_LBLT<12> B_LBLT<11> B_LWL<11> B_XWL<11> VDD_CORE ++ VSS VDD_CORE VSS / RM_IHPSG13_512x16_c2_2P_BITKIT_CELL +XCELL<10> A_LBLC<10> A_LBLC<11> A_LBLT<10> A_LBLT<11> A_LWL<10> A_XWL<10> ++ B_LBLC<10> B_LBLC<11> B_LBLT<10> B_LBLT<11> B_LWL<10> B_XWL<10> VDD_CORE ++ VSS VDD_CORE VSS / RM_IHPSG13_512x16_c2_2P_BITKIT_CELL +XCELL<9> A_LBLC<10> A_LBLC<9> A_LBLT<10> A_LBLT<9> A_LWL<9> A_XWL<9> ++ B_LBLC<10> B_LBLC<9> B_LBLT<10> B_LBLT<9> B_LWL<9> B_XWL<9> VDD_CORE ++ VSS VDD_CORE VSS / RM_IHPSG13_512x16_c2_2P_BITKIT_CELL +XCELL<8> A_LBLC<8> A_LBLC<9> A_LBLT<8> A_LBLT<9> A_LWL<8> A_XWL<8> B_LBLC<8> ++ B_LBLC<9> B_LBLT<8> B_LBLT<9> B_LWL<8> B_XWL<8> VDD_CORE VSS ++ VDD_CORE VSS / RM_IHPSG13_512x16_c2_2P_BITKIT_CELL +XCELL<7> A_LBLC<8> A_LBLC<7> A_LBLT<8> A_LBLT<7> A_LWL<7> A_XWL<7> B_LBLC<8> ++ B_LBLC<7> B_LBLT<8> B_LBLT<7> B_LWL<7> B_XWL<7> VDD_CORE VSS ++ VDD_CORE VSS / RM_IHPSG13_512x16_c2_2P_BITKIT_CELL +XCELL<6> A_LBLC<6> A_LBLC<7> A_LBLT<6> A_LBLT<7> A_LWL<6> A_XWL<6> B_LBLC<6> ++ B_LBLC<7> B_LBLT<6> B_LBLT<7> B_LWL<6> B_XWL<6> VDD_CORE VSS ++ VDD_CORE VSS / RM_IHPSG13_512x16_c2_2P_BITKIT_CELL +XCELL<5> A_LBLC<6> A_LBLC<5> A_LBLT<6> A_LBLT<5> A_LWL<5> A_XWL<5> B_LBLC<6> ++ B_LBLC<5> B_LBLT<6> B_LBLT<5> B_LWL<5> B_XWL<5> VDD_CORE VSS ++ VDD_CORE VSS / RM_IHPSG13_512x16_c2_2P_BITKIT_CELL +XCELL<4> A_LBLC<4> A_LBLC<5> A_LBLT<4> A_LBLT<5> A_LWL<4> A_XWL<4> B_LBLC<4> ++ B_LBLC<5> B_LBLT<4> B_LBLT<5> B_LWL<4> B_XWL<4> VDD_CORE VSS ++ VDD_CORE VSS / RM_IHPSG13_512x16_c2_2P_BITKIT_CELL +XCELL<3> A_LBLC<4> A_LBLC<3> A_LBLT<4> A_LBLT<3> A_LWL<3> A_XWL<3> B_LBLC<4> ++ B_LBLC<3> B_LBLT<4> B_LBLT<3> B_LWL<3> B_XWL<3> VDD_CORE VSS ++ VDD_CORE VSS / RM_IHPSG13_512x16_c2_2P_BITKIT_CELL +XCELL<2> A_LBLC<2> A_LBLC<3> A_LBLT<2> A_LBLT<3> A_LWL<2> A_XWL<2> B_LBLC<2> ++ B_LBLC<3> B_LBLT<2> B_LBLT<3> B_LWL<2> B_XWL<2> VDD_CORE VSS ++ VDD_CORE VSS / RM_IHPSG13_512x16_c2_2P_BITKIT_CELL +XCELL<1> A_LBLC<2> A_LBLC<1> A_LBLT<2> A_LBLT<1> A_LWL<1> A_XWL<1> B_LBLC<2> ++ B_LBLC<1> B_LBLT<2> B_LBLT<1> B_LWL<1> B_XWL<1> VDD_CORE VSS ++ VDD_CORE VSS / RM_IHPSG13_512x16_c2_2P_BITKIT_CELL +XCELL<0> A_BLC_BOT<0> A_LBLC<1> A_BLT_BOT<0> A_LBLT<1> A_LWL<0> A_XWL<0> ++ B_BLC_BOT<0> B_LBLC<1> B_BLT_BOT<0> B_LBLT<1> B_LWL<0> B_XWL<0> VDD_CORE ++ VSS VDD_CORE VSS / RM_IHPSG13_512x16_c2_2P_BITKIT_CELL +.ENDS +.SUBCKT RM_IHPSG13_512x16_c2_2P_BITKIT_EDGE_TB A_BLC A_BLT B_BLC B_BLT NW PW VDD VSS +.ENDS +.SUBCKT RM_IHPSG13_512x16_c2_2P_BITKIT_16x2_EDGE_TB A_BLC<1> A_BLC<0> A_BLT<1> A_BLT<0> ++ B_BLC<1> B_BLC<0> B_BLT<1> B_BLT<0> VDD_CORE VSS +XEDGE<1> A_BLC<1> A_BLT<1> B_BLC<1> B_BLT<1> VDD_CORE VSS ++ VDD_CORE VSS / RM_IHPSG13_512x16_c2_2P_BITKIT_EDGE_TB +XEDGE<0> A_BLC<0> A_BLT<0> B_BLC<0> B_BLT<0> VDD_CORE VSS ++ VDD_CORE VSS / RM_IHPSG13_512x16_c2_2P_BITKIT_EDGE_TB +.ENDS +.SUBCKT RM_IHPSG13_512x16_c2_2P_BITKIT_TAP A_BLC A_BLT B_BLC B_BLT NW PW VDD VSS +.ENDS +.SUBCKT RM_IHPSG13_512x16_c2_2P_BITKIT_16x2_TAP A_BLC<1> A_BLC<0> A_BLT<1> A_BLT<0> ++ B_BLC<1> B_BLC<0> B_BLT<1> B_BLT<0> VDD_CORE VSS +XIEDGEBP_COL1<1> A_BLC<1> A_BLT<1> B_BLC<1> B_BLT<1> VDD_CORE VSS ++ VDD_CORE VSS / RM_IHPSG13_512x16_c2_2P_BITKIT_EDGE_TB +XIEDGEBP_COL1<0> A_BLC<1> A_BLT<1> B_BLC<1> B_BLT<1> VDD_CORE VSS ++ VDD_CORE VSS / RM_IHPSG13_512x16_c2_2P_BITKIT_EDGE_TB +XIEDGEBP_COL2<1> A_BLC<0> A_BLT<0> B_BLC<0> B_BLT<0> VDD_CORE VSS ++ VDD_CORE VSS / RM_IHPSG13_512x16_c2_2P_BITKIT_EDGE_TB +XIEDGEBP_COL2<0> A_BLC<0> A_BLT<0> B_BLC<0> B_BLT<0> VDD_CORE VSS ++ VDD_CORE VSS / RM_IHPSG13_512x16_c2_2P_BITKIT_EDGE_TB +XITAP<1> A_BLC<1> A_BLT<1> B_BLC<1> B_BLT<1> VDD_CORE VSS ++ VDD_CORE VSS / RM_IHPSG13_512x16_c2_2P_BITKIT_TAP +XITAP<0> A_BLC<0> A_BLT<0> B_BLC<0> B_BLT<0> VDD_CORE VSS ++ VDD_CORE VSS / RM_IHPSG13_512x16_c2_2P_BITKIT_TAP +.ENDS + + +.SUBCKT RM_IHPSG13_512x16_c2_1P_BITKIT_TAP_LR NW PW VDD VSS +.ENDS +.SUBCKT RM_IHPSG13_512x16_c2_2P_BITKIT_16x2_TAP_LR VDD_CORE VSS +XCORNER<1> VDD_CORE VSS VDD_CORE VSS / ++ RM_IHPSG13_512x16_c2_1P_BITKIT_CORNER +XCORNER<0> VDD_CORE VSS VDD_CORE VSS / ++ RM_IHPSG13_512x16_c2_1P_BITKIT_CORNER +XTAP_BORDER VDD_CORE VSS VDD_CORE VSS / ++ RM_IHPSG13_512x16_c2_1P_BITKIT_TAP_LR +.ENDS + +.SUBCKT RSC_IHPSG13_CBUFX12 A Z VDD VSS +MN1 Z net6 VSS VSS sg13_lv_nmos m=1 w=4.23u l=130.00n ng=6 nrd=0 nrs=0 +MN0 net6 A VSS VSS sg13_lv_nmos m=1 w=1.41u l=130.00n ng=2 nrd=0 nrs=0 +MP1 Z net6 VDD VDD sg13_lv_pmos m=1 w=9.72u l=130.00n ng=6 nrd=0 nrs=0 +MP0 net6 A VDD VDD sg13_lv_pmos m=1 w=3.24u l=130.00n ng=2 nrd=0 nrs=0 +.ENDS +.SUBCKT RM_IHPSG13_512x16_c2_2P_COLDRV13X12 ADDR_COL_I<1> ADDR_COL_I<0> ADDR_COL_O<1> ++ ADDR_COL_O<0> ADDR_DEC_I<7> ADDR_DEC_I<6> ADDR_DEC_I<5> ADDR_DEC_I<4> ++ ADDR_DEC_I<3> ADDR_DEC_I<2> ADDR_DEC_I<1> ADDR_DEC_I<0> ADDR_DEC_O<7> ++ ADDR_DEC_O<6> ADDR_DEC_O<5> ADDR_DEC_O<4> ADDR_DEC_O<3> ADDR_DEC_O<2> ++ ADDR_DEC_O<1> ADDR_DEC_O<0> DCLK_I DCLK_O RCLK_I RCLK_O WCLK_I WCLK_O ++ VDD VSS +XI1<3> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI1<2> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI1<1> VDD VSS / RSC_IHPSG13_FILLCAP8 +XWCLK_DRV WCLK_I WCLK_O VDD VSS / RSC_IHPSG13_CBUFX12 +XRCLK_DRV RCLK_I RCLK_O VDD VSS / RSC_IHPSG13_CBUFX12 +XDCLK_DRV DCLK_I DCLK_O VDD VSS / RSC_IHPSG13_CBUFX12 +XADDR_COL_DRV<1> ADDR_COL_I<1> ADDR_COL_O<1> VDD VSS / ++ RSC_IHPSG13_CBUFX12 +XADDR_COL_DRV<0> ADDR_COL_I<0> ADDR_COL_O<0> VDD VSS / ++ RSC_IHPSG13_CBUFX12 +XADDR_DEC_DRV<7> ADDR_DEC_I<7> ADDR_DEC_O<7> VDD VSS / ++ RSC_IHPSG13_CBUFX12 +XADDR_DEC_DRV<6> ADDR_DEC_I<6> ADDR_DEC_O<6> VDD VSS / ++ RSC_IHPSG13_CBUFX12 +XADDR_DEC_DRV<5> ADDR_DEC_I<5> ADDR_DEC_O<5> VDD VSS / ++ RSC_IHPSG13_CBUFX12 +XADDR_DEC_DRV<4> ADDR_DEC_I<4> ADDR_DEC_O<4> VDD VSS / ++ RSC_IHPSG13_CBUFX12 +XADDR_DEC_DRV<3> ADDR_DEC_I<3> ADDR_DEC_O<3> VDD VSS / ++ RSC_IHPSG13_CBUFX12 +XADDR_DEC_DRV<2> ADDR_DEC_I<2> ADDR_DEC_O<2> VDD VSS / ++ RSC_IHPSG13_CBUFX12 +XADDR_DEC_DRV<1> ADDR_DEC_I<1> ADDR_DEC_O<1> VDD VSS / ++ RSC_IHPSG13_CBUFX12 +XADDR_DEC_DRV<0> ADDR_DEC_I<0> ADDR_DEC_O<0> VDD VSS / ++ RSC_IHPSG13_CBUFX12 +XI0<6> VDD VSS / RSC_IHPSG13_FILLCAP4 +XI0<5> VDD VSS / RSC_IHPSG13_FILLCAP4 +XI0<4> VDD VSS / RSC_IHPSG13_FILLCAP4 +XI0<3> VDD VSS / RSC_IHPSG13_FILLCAP4 +XI0<2> VDD VSS / RSC_IHPSG13_FILLCAP4 +XI0<1> VDD VSS / RSC_IHPSG13_FILLCAP4 +.ENDS +.SUBCKT RSC_IHPSG13_WLDRVX12 A Z VDD VSS +MN1 Z net6 VSS VSS sg13_lv_nmos m=1 w=1.41u l=130.00n ng=2 nrd=0 nrs=0 +MN0 net6 A VSS VSS sg13_lv_nmos m=1 w=1.8u l=130.00n ng=2 nrd=0 nrs=0 +MP1 Z net6 VDD VDD sg13_lv_pmos m=1 w=9.72u l=130.00n ng=6 nrd=0 nrs=0 +MP0 net6 A VDD VDD sg13_lv_pmos m=1 w=900.0n l=130.00n ng=1 nrd=0 nrs=0 +.ENDS +.SUBCKT RM_IHPSG13_512x16_c2_2P_WLDRV16X12 A<15> A<14> A<13> A<12> A<11> A<10> A<9> A<8> ++ A<7> A<6> A<5> A<4> A<3> A<2> A<1> A<0> Z<15> Z<14> Z<13> Z<12> Z<11> Z<10> ++ Z<9> Z<8> Z<7> Z<6> Z<5> Z<4> Z<3> Z<2> Z<1> Z<0> VDD VSS +XBUF<15> A<15> Z<15> VDD VSS / RSC_IHPSG13_WLDRVX12 +XBUF<14> A<14> Z<14> VDD VSS / RSC_IHPSG13_WLDRVX12 +XBUF<13> A<13> Z<13> VDD VSS / RSC_IHPSG13_WLDRVX12 +XBUF<12> A<12> Z<12> VDD VSS / RSC_IHPSG13_WLDRVX12 +XBUF<11> A<11> Z<11> VDD VSS / RSC_IHPSG13_WLDRVX12 +XBUF<10> A<10> Z<10> VDD VSS / RSC_IHPSG13_WLDRVX12 +XBUF<9> A<9> Z<9> VDD VSS / RSC_IHPSG13_WLDRVX12 +XBUF<8> A<8> Z<8> VDD VSS / RSC_IHPSG13_WLDRVX12 +XBUF<7> A<7> Z<7> VDD VSS / RSC_IHPSG13_WLDRVX12 +XBUF<6> A<6> Z<6> VDD VSS / RSC_IHPSG13_WLDRVX12 +XBUF<5> A<5> Z<5> VDD VSS / RSC_IHPSG13_WLDRVX12 +XBUF<4> A<4> Z<4> VDD VSS / RSC_IHPSG13_WLDRVX12 +XBUF<3> A<3> Z<3> VDD VSS / RSC_IHPSG13_WLDRVX12 +XBUF<2> A<2> Z<2> VDD VSS / RSC_IHPSG13_WLDRVX12 +XBUF<1> A<1> Z<1> VDD VSS / RSC_IHPSG13_WLDRVX12 +XBUF<0> A<0> Z<0> VDD VSS / RSC_IHPSG13_WLDRVX12 +.ENDS +.SUBCKT RM_IHPSG13_512x16_c2_2P_DEC04 ADDR<3> ADDR<2> ADDR<1> ADDR<0> CS ECLK_H_BOT ++ ECLK_H_TOP ECLK_L_BOT ECLK_L_TOP WL<15> WL<14> WL<13> WL<12> WL<11> WL<10> ++ WL<9> WL<8> WL<7> WL<6> WL<5> WL<4> WL<3> WL<2> WL<1> WL<0> VDD VSS +XI0<3> PADR<1> PADR<0> sel01<3> VDD VSS / RSC_IHPSG13_NAND2X2 +XI0<2> PADR<1> NADR<0> sel01<2> VDD VSS / RSC_IHPSG13_NAND2X2 +XI0<1> NADR<1> PADR<0> sel01<1> VDD VSS / RSC_IHPSG13_NAND2X2 +XI0<0> NADR<1> NADR<0> sel01<0> VDD VSS / RSC_IHPSG13_NAND2X2 +XI4 ECLK_L_BOT EN VDD VSS / RSC_IHPSG13_CINVX4 +XI5 ECLK_H_BOT ECLK_L_BOT VDD VSS / RSC_IHPSG13_CINVX2 +XI3<3> PADR<3> NADR<3> VDD VSS / RSC_IHPSG13_INVX2 +XI3<2> PADR<2> NADR<2> VDD VSS / RSC_IHPSG13_INVX2 +XI3<1> PADR<1> NADR<1> VDD VSS / RSC_IHPSG13_INVX2 +XI3<0> PADR<0> NADR<0> VDD VSS / RSC_IHPSG13_INVX2 +XR0 ECLK_H_BOT ECLK_H_TOP / RSC_IHPSG13_MET2RES +XI11 ECLK_L_BOT ECLK_L_TOP / RSC_IHPSG13_MET2RES +XI1<3> PADR<2> PADR<3> CS sel23<3> VDD VSS / RSC_IHPSG13_NAND3X2 +XI1<2> NADR<2> PADR<3> CS sel23<2> VDD VSS / RSC_IHPSG13_NAND3X2 +XI1<1> PADR<2> NADR<3> CS sel23<1> VDD VSS / RSC_IHPSG13_NAND3X2 +XI1<0> NADR<2> NADR<3> CS sel23<0> VDD VSS / RSC_IHPSG13_NAND3X2 +XI2<15> sel23<3> sel01<3> EN WL<15> VDD VSS / RSC_IHPSG13_NOR3X2 +XI2<14> sel23<3> sel01<2> EN WL<14> VDD VSS / RSC_IHPSG13_NOR3X2 +XI2<13> sel23<3> sel01<1> EN WL<13> VDD VSS / RSC_IHPSG13_NOR3X2 +XI2<12> sel23<3> sel01<0> EN WL<12> VDD VSS / RSC_IHPSG13_NOR3X2 +XI2<11> sel23<2> sel01<3> EN WL<11> VDD VSS / RSC_IHPSG13_NOR3X2 +XI2<10> sel23<2> sel01<2> EN WL<10> VDD VSS / RSC_IHPSG13_NOR3X2 +XI2<9> sel23<2> sel01<1> EN WL<9> VDD VSS / RSC_IHPSG13_NOR3X2 +XI2<8> sel23<2> sel01<0> EN WL<8> VDD VSS / RSC_IHPSG13_NOR3X2 +XI2<7> sel23<1> sel01<3> EN WL<7> VDD VSS / RSC_IHPSG13_NOR3X2 +XI2<6> sel23<1> sel01<2> EN WL<6> VDD VSS / RSC_IHPSG13_NOR3X2 +XI2<5> sel23<1> sel01<1> EN WL<5> VDD VSS / RSC_IHPSG13_NOR3X2 +XI2<4> sel23<1> sel01<0> EN WL<4> VDD VSS / RSC_IHPSG13_NOR3X2 +XI2<3> sel23<0> sel01<3> EN WL<3> VDD VSS / RSC_IHPSG13_NOR3X2 +XI2<2> sel23<0> sel01<2> EN WL<2> VDD VSS / RSC_IHPSG13_NOR3X2 +XI2<1> sel23<0> sel01<1> EN WL<1> VDD VSS / RSC_IHPSG13_NOR3X2 +XI2<0> sel23<0> sel01<0> EN WL<0> VDD VSS / RSC_IHPSG13_NOR3X2 +XCAPS4 VDD VSS / RSC_IHPSG13_FILLCAP4 +XLATCH<3> CS ADDR<3> PADR<3> VDD VSS / RSC_IHPSG13_LHPQX2 +XLATCH<2> CS ADDR<2> PADR<2> VDD VSS / RSC_IHPSG13_LHPQX2 +XLATCH<1> CS ADDR<1> PADR<1> VDD VSS / RSC_IHPSG13_LHPQX2 +XLATCH<0> CS ADDR<0> PADR<0> VDD VSS / RSC_IHPSG13_LHPQX2 +.ENDS +.SUBCKT RM_IHPSG13_512x16_c2_2P_DEC02 ADDR<1> ADDR<0> CS CS_OUT VDD VSS +XDEC ADDR<1> NADDR<0> CS net1 VDD VSS / RSC_IHPSG13_NAND3X2 +XADDRINV ADDR<0> NADDR<0> VDD VSS / RSC_IHPSG13_INVX2 +XDECINV net1 CS_OUT VDD VSS / RSC_IHPSG13_INVX4 +XI2<1> VDD VSS / RSC_IHPSG13_FILLCAP4 +XI2<0> VDD VSS / RSC_IHPSG13_FILLCAP4 +.ENDS +.SUBCKT RM_IHPSG13_512x16_c2_2P_DEC01 ADDR<1> ADDR<0> CS CS_OUT VDD VSS +XDEC NADDR<1> ADDR<0> CS net1 VDD VSS / RSC_IHPSG13_NAND3X2 +XADDRINV ADDR<1> NADDR<1> VDD VSS / RSC_IHPSG13_INVX2 +XDECINV net1 CS_OUT VDD VSS / RSC_IHPSG13_INVX4 +XI2<1> VDD VSS / RSC_IHPSG13_FILLCAP4 +XI2<0> VDD VSS / RSC_IHPSG13_FILLCAP4 +.ENDS +.SUBCKT RM_IHPSG13_512x16_c2_2P_DEC00 ADDR<1> ADDR<0> CS CS_OUT VDD VSS +XDEC NADDR<1> NADDR<0> CS net1 VDD VSS / RSC_IHPSG13_NAND3X2 +XADDRINV<1> ADDR<1> NADDR<1> VDD VSS / RSC_IHPSG13_INVX2 +XADDRINV<0> ADDR<0> NADDR<0> VDD VSS / RSC_IHPSG13_INVX2 +XI1<1> VDD VSS / RSC_IHPSG13_FILLCAP4 +XI1<0> VDD VSS / RSC_IHPSG13_FILLCAP4 +XDECINV net1 CS_OUT VDD VSS / RSC_IHPSG13_INVX4 +.ENDS +.SUBCKT RM_IHPSG13_512x16_c2_2P_DEC03 ADDR<1> ADDR<0> CS CS_OUT VDD VSS +XDEC ADDR<1> ADDR<0> CS net1 VDD VSS / RSC_IHPSG13_NAND3X2 +XDECINV net1 CS_OUT VDD VSS / RSC_IHPSG13_INVX4 +XI0<1> VDD VSS / RSC_IHPSG13_FILLCAP4 +XI0<0> VDD VSS / RSC_IHPSG13_FILLCAP4 +.ENDS +.SUBCKT RM_IHPSG13_512x16_c2_2P_ROWDEC9 ADDR_N_I<8> ADDR_N_I<7> ADDR_N_I<6> ADDR_N_I<5> ++ ADDR_N_I<4> ADDR_N_I<3> ADDR_N_I<2> ADDR_N_I<1> ADDR_N_I<0> CS_I ECLK_I ++ WL_O<511> WL_O<510> WL_O<509> WL_O<508> WL_O<507> WL_O<506> WL_O<505> ++ WL_O<504> WL_O<503> WL_O<502> WL_O<501> WL_O<500> WL_O<499> WL_O<498> ++ WL_O<497> WL_O<496> WL_O<495> WL_O<494> WL_O<493> WL_O<492> WL_O<491> ++ WL_O<490> WL_O<489> WL_O<488> WL_O<487> WL_O<486> WL_O<485> WL_O<484> ++ WL_O<483> WL_O<482> WL_O<481> WL_O<480> WL_O<479> WL_O<478> WL_O<477> ++ WL_O<476> WL_O<475> WL_O<474> WL_O<473> WL_O<472> WL_O<471> WL_O<470> ++ WL_O<469> WL_O<468> WL_O<467> WL_O<466> WL_O<465> WL_O<464> WL_O<463> ++ WL_O<462> WL_O<461> WL_O<460> WL_O<459> WL_O<458> WL_O<457> WL_O<456> ++ WL_O<455> WL_O<454> WL_O<453> WL_O<452> WL_O<451> WL_O<450> WL_O<449> ++ WL_O<448> WL_O<447> WL_O<446> WL_O<445> WL_O<444> WL_O<443> WL_O<442> ++ WL_O<441> WL_O<440> WL_O<439> WL_O<438> WL_O<437> WL_O<436> WL_O<435> ++ WL_O<434> WL_O<433> WL_O<432> WL_O<431> WL_O<430> WL_O<429> WL_O<428> ++ WL_O<427> WL_O<426> WL_O<425> WL_O<424> WL_O<423> WL_O<422> WL_O<421> ++ WL_O<420> WL_O<419> WL_O<418> WL_O<417> WL_O<416> WL_O<415> WL_O<414> ++ WL_O<413> WL_O<412> WL_O<411> WL_O<410> WL_O<409> WL_O<408> WL_O<407> ++ WL_O<406> WL_O<405> WL_O<404> WL_O<403> WL_O<402> WL_O<401> WL_O<400> ++ WL_O<399> WL_O<398> WL_O<397> WL_O<396> WL_O<395> WL_O<394> WL_O<393> ++ WL_O<392> WL_O<391> WL_O<390> WL_O<389> WL_O<388> WL_O<387> WL_O<386> ++ WL_O<385> WL_O<384> WL_O<383> WL_O<382> WL_O<381> WL_O<380> WL_O<379> ++ WL_O<378> WL_O<377> WL_O<376> WL_O<375> WL_O<374> WL_O<373> WL_O<372> ++ WL_O<371> WL_O<370> WL_O<369> WL_O<368> WL_O<367> WL_O<366> WL_O<365> ++ WL_O<364> WL_O<363> WL_O<362> WL_O<361> WL_O<360> WL_O<359> WL_O<358> ++ WL_O<357> WL_O<356> WL_O<355> WL_O<354> WL_O<353> WL_O<352> WL_O<351> ++ WL_O<350> WL_O<349> WL_O<348> WL_O<347> WL_O<346> WL_O<345> WL_O<344> ++ WL_O<343> WL_O<342> WL_O<341> WL_O<340> WL_O<339> WL_O<338> WL_O<337> ++ WL_O<336> WL_O<335> WL_O<334> WL_O<333> WL_O<332> WL_O<331> WL_O<330> ++ WL_O<329> WL_O<328> WL_O<327> WL_O<326> WL_O<325> WL_O<324> WL_O<323> ++ WL_O<322> WL_O<321> WL_O<320> WL_O<319> WL_O<318> WL_O<317> WL_O<316> ++ WL_O<315> WL_O<314> WL_O<313> WL_O<312> WL_O<311> WL_O<310> WL_O<309> ++ WL_O<308> WL_O<307> WL_O<306> WL_O<305> WL_O<304> WL_O<303> WL_O<302> ++ WL_O<301> WL_O<300> WL_O<299> WL_O<298> WL_O<297> WL_O<296> WL_O<295> ++ WL_O<294> WL_O<293> WL_O<292> WL_O<291> WL_O<290> WL_O<289> WL_O<288> ++ WL_O<287> WL_O<286> WL_O<285> WL_O<284> WL_O<283> WL_O<282> WL_O<281> ++ WL_O<280> WL_O<279> WL_O<278> WL_O<277> WL_O<276> WL_O<275> WL_O<274> ++ WL_O<273> WL_O<272> WL_O<271> WL_O<270> WL_O<269> WL_O<268> WL_O<267> ++ WL_O<266> WL_O<265> WL_O<264> WL_O<263> WL_O<262> WL_O<261> WL_O<260> ++ WL_O<259> WL_O<258> WL_O<257> WL_O<256> WL_O<255> WL_O<254> WL_O<253> ++ WL_O<252> WL_O<251> WL_O<250> WL_O<249> WL_O<248> WL_O<247> WL_O<246> ++ WL_O<245> WL_O<244> WL_O<243> WL_O<242> WL_O<241> WL_O<240> WL_O<239> ++ WL_O<238> WL_O<237> WL_O<236> WL_O<235> WL_O<234> WL_O<233> WL_O<232> ++ WL_O<231> WL_O<230> WL_O<229> WL_O<228> WL_O<227> WL_O<226> WL_O<225> ++ WL_O<224> WL_O<223> WL_O<222> WL_O<221> WL_O<220> WL_O<219> WL_O<218> ++ WL_O<217> WL_O<216> WL_O<215> WL_O<214> WL_O<213> WL_O<212> WL_O<211> ++ WL_O<210> WL_O<209> WL_O<208> WL_O<207> WL_O<206> WL_O<205> WL_O<204> ++ WL_O<203> WL_O<202> WL_O<201> WL_O<200> WL_O<199> WL_O<198> WL_O<197> ++ WL_O<196> WL_O<195> WL_O<194> WL_O<193> WL_O<192> WL_O<191> WL_O<190> ++ WL_O<189> WL_O<188> WL_O<187> WL_O<186> WL_O<185> WL_O<184> WL_O<183> ++ WL_O<182> WL_O<181> WL_O<180> WL_O<179> WL_O<178> WL_O<177> WL_O<176> ++ WL_O<175> WL_O<174> WL_O<173> WL_O<172> WL_O<171> WL_O<170> WL_O<169> ++ WL_O<168> WL_O<167> WL_O<166> WL_O<165> WL_O<164> WL_O<163> WL_O<162> ++ WL_O<161> WL_O<160> WL_O<159> WL_O<158> WL_O<157> WL_O<156> WL_O<155> ++ WL_O<154> WL_O<153> WL_O<152> WL_O<151> WL_O<150> WL_O<149> WL_O<148> ++ WL_O<147> WL_O<146> WL_O<145> WL_O<144> WL_O<143> WL_O<142> WL_O<141> ++ WL_O<140> WL_O<139> WL_O<138> WL_O<137> WL_O<136> WL_O<135> WL_O<134> ++ WL_O<133> WL_O<132> WL_O<131> WL_O<130> WL_O<129> WL_O<128> WL_O<127> ++ WL_O<126> WL_O<125> WL_O<124> WL_O<123> WL_O<122> WL_O<121> WL_O<120> ++ WL_O<119> WL_O<118> WL_O<117> WL_O<116> WL_O<115> WL_O<114> WL_O<113> ++ WL_O<112> WL_O<111> WL_O<110> WL_O<109> WL_O<108> WL_O<107> WL_O<106> ++ WL_O<105> WL_O<104> WL_O<103> WL_O<102> WL_O<101> WL_O<100> WL_O<99> ++ WL_O<98> WL_O<97> WL_O<96> WL_O<95> WL_O<94> WL_O<93> WL_O<92> WL_O<91> ++ WL_O<90> WL_O<89> WL_O<88> WL_O<87> WL_O<86> WL_O<85> WL_O<84> WL_O<83> ++ WL_O<82> WL_O<81> WL_O<80> WL_O<79> WL_O<78> WL_O<77> WL_O<76> WL_O<75> ++ WL_O<74> WL_O<73> WL_O<72> WL_O<71> WL_O<70> WL_O<69> WL_O<68> WL_O<67> ++ WL_O<66> WL_O<65> WL_O<64> WL_O<63> WL_O<62> WL_O<61> WL_O<60> WL_O<59> ++ WL_O<58> WL_O<57> WL_O<56> WL_O<55> WL_O<54> WL_O<53> WL_O<52> WL_O<51> ++ WL_O<50> WL_O<49> WL_O<48> WL_O<47> WL_O<46> WL_O<45> WL_O<44> WL_O<43> ++ WL_O<42> WL_O<41> WL_O<40> WL_O<39> WL_O<38> WL_O<37> WL_O<36> WL_O<35> ++ WL_O<34> WL_O<33> WL_O<32> WL_O<31> WL_O<30> WL_O<29> WL_O<28> WL_O<27> ++ WL_O<26> WL_O<25> WL_O<24> WL_O<23> WL_O<22> WL_O<21> WL_O<20> WL_O<19> ++ WL_O<18> WL_O<17> WL_O<16> WL_O<15> WL_O<14> WL_O<13> WL_O<12> WL_O<11> ++ WL_O<10> WL_O<9> WL_O<8> WL_O<7> WL_O<6> WL_O<5> WL_O<4> WL_O<3> WL_O<2> ++ WL_O<1> WL_O<0> VDD VSS +XSEL<31> ADDR_N_I<3> ADDR_N_I<2> ADDR_N_I<1> ADDR_N_I<0> CS00<31> ECLK_H<31> ++ ECLK_H<32> ECLK_B<31> ECLK_B<32> WL_O<511> WL_O<510> WL_O<509> WL_O<508> ++ WL_O<507> WL_O<506> WL_O<505> WL_O<504> WL_O<503> WL_O<502> WL_O<501> ++ WL_O<500> WL_O<499> WL_O<498> WL_O<497> WL_O<496> VDD VSS / ++ RM_IHPSG13_512x16_c2_2P_DEC04 +XSEL<30> ADDR_N_I<3> ADDR_N_I<2> ADDR_N_I<1> ADDR_N_I<0> CS00<30> ECLK_H<30> ++ ECLK_H<31> ECLK_B<30> ECLK_B<31> WL_O<495> WL_O<494> WL_O<493> WL_O<492> ++ WL_O<491> WL_O<490> WL_O<489> WL_O<488> WL_O<487> WL_O<486> WL_O<485> ++ WL_O<484> WL_O<483> WL_O<482> WL_O<481> WL_O<480> VDD VSS / ++ RM_IHPSG13_512x16_c2_2P_DEC04 +XSEL<29> ADDR_N_I<3> ADDR_N_I<2> ADDR_N_I<1> ADDR_N_I<0> CS00<29> ECLK_H<29> ++ ECLK_H<30> ECLK_B<29> ECLK_B<30> WL_O<479> WL_O<478> WL_O<477> WL_O<476> ++ WL_O<475> WL_O<474> WL_O<473> WL_O<472> WL_O<471> WL_O<470> WL_O<469> ++ WL_O<468> WL_O<467> WL_O<466> WL_O<465> WL_O<464> VDD VSS / ++ RM_IHPSG13_512x16_c2_2P_DEC04 +XSEL<28> ADDR_N_I<3> ADDR_N_I<2> ADDR_N_I<1> ADDR_N_I<0> CS00<28> ECLK_H<28> ++ ECLK_H<29> ECLK_B<28> ECLK_B<29> WL_O<463> WL_O<462> WL_O<461> WL_O<460> ++ WL_O<459> WL_O<458> WL_O<457> WL_O<456> WL_O<455> WL_O<454> WL_O<453> ++ WL_O<452> WL_O<451> WL_O<450> WL_O<449> WL_O<448> VDD VSS / ++ RM_IHPSG13_512x16_c2_2P_DEC04 +XSEL<27> ADDR_N_I<3> ADDR_N_I<2> ADDR_N_I<1> ADDR_N_I<0> CS00<27> ECLK_H<27> ++ ECLK_H<28> ECLK_B<27> ECLK_B<28> WL_O<447> WL_O<446> WL_O<445> WL_O<444> ++ WL_O<443> WL_O<442> WL_O<441> WL_O<440> WL_O<439> WL_O<438> WL_O<437> ++ WL_O<436> WL_O<435> WL_O<434> WL_O<433> WL_O<432> VDD VSS / ++ RM_IHPSG13_512x16_c2_2P_DEC04 +XSEL<26> ADDR_N_I<3> ADDR_N_I<2> ADDR_N_I<1> ADDR_N_I<0> CS00<26> ECLK_H<26> ++ ECLK_H<27> ECLK_B<26> ECLK_B<27> WL_O<431> WL_O<430> WL_O<429> WL_O<428> ++ WL_O<427> WL_O<426> WL_O<425> WL_O<424> WL_O<423> WL_O<422> WL_O<421> ++ WL_O<420> WL_O<419> WL_O<418> WL_O<417> WL_O<416> VDD VSS / ++ RM_IHPSG13_512x16_c2_2P_DEC04 +XSEL<25> ADDR_N_I<3> ADDR_N_I<2> ADDR_N_I<1> ADDR_N_I<0> CS00<25> ECLK_H<25> ++ ECLK_H<26> ECLK_B<25> ECLK_B<26> WL_O<415> WL_O<414> WL_O<413> WL_O<412> ++ WL_O<411> WL_O<410> WL_O<409> WL_O<408> WL_O<407> WL_O<406> WL_O<405> ++ WL_O<404> WL_O<403> WL_O<402> WL_O<401> WL_O<400> VDD VSS / ++ RM_IHPSG13_512x16_c2_2P_DEC04 +XSEL<24> ADDR_N_I<3> ADDR_N_I<2> ADDR_N_I<1> ADDR_N_I<0> CS00<24> ECLK_H<24> ++ ECLK_H<25> ECLK_B<24> ECLK_B<25> WL_O<399> WL_O<398> WL_O<397> WL_O<396> ++ WL_O<395> WL_O<394> WL_O<393> WL_O<392> WL_O<391> WL_O<390> WL_O<389> ++ WL_O<388> WL_O<387> WL_O<386> WL_O<385> WL_O<384> VDD VSS / ++ RM_IHPSG13_512x16_c2_2P_DEC04 +XSEL<23> ADDR_N_I<3> ADDR_N_I<2> ADDR_N_I<1> ADDR_N_I<0> CS00<23> ECLK_H<23> ++ ECLK_H<24> ECLK_B<23> ECLK_B<24> WL_O<383> WL_O<382> WL_O<381> WL_O<380> ++ WL_O<379> WL_O<378> WL_O<377> WL_O<376> WL_O<375> WL_O<374> WL_O<373> ++ WL_O<372> WL_O<371> WL_O<370> WL_O<369> WL_O<368> VDD VSS / ++ RM_IHPSG13_512x16_c2_2P_DEC04 +XSEL<22> ADDR_N_I<3> ADDR_N_I<2> ADDR_N_I<1> ADDR_N_I<0> CS00<22> ECLK_H<22> ++ ECLK_H<23> ECLK_B<22> ECLK_B<23> WL_O<367> WL_O<366> WL_O<365> WL_O<364> ++ WL_O<363> WL_O<362> WL_O<361> WL_O<360> WL_O<359> WL_O<358> WL_O<357> ++ WL_O<356> WL_O<355> WL_O<354> WL_O<353> WL_O<352> VDD VSS / ++ RM_IHPSG13_512x16_c2_2P_DEC04 +XSEL<21> ADDR_N_I<3> ADDR_N_I<2> ADDR_N_I<1> ADDR_N_I<0> CS00<21> ECLK_H<21> ++ ECLK_H<22> ECLK_B<21> ECLK_B<22> WL_O<351> WL_O<350> WL_O<349> WL_O<348> ++ WL_O<347> WL_O<346> WL_O<345> WL_O<344> WL_O<343> WL_O<342> WL_O<341> ++ WL_O<340> WL_O<339> WL_O<338> WL_O<337> WL_O<336> VDD VSS / ++ RM_IHPSG13_512x16_c2_2P_DEC04 +XSEL<20> ADDR_N_I<3> ADDR_N_I<2> ADDR_N_I<1> ADDR_N_I<0> CS00<20> ECLK_H<20> ++ ECLK_H<21> ECLK_B<20> ECLK_B<21> WL_O<335> WL_O<334> WL_O<333> WL_O<332> ++ WL_O<331> WL_O<330> WL_O<329> WL_O<328> WL_O<327> WL_O<326> WL_O<325> ++ WL_O<324> WL_O<323> WL_O<322> WL_O<321> WL_O<320> VDD VSS / ++ RM_IHPSG13_512x16_c2_2P_DEC04 +XSEL<19> ADDR_N_I<3> ADDR_N_I<2> ADDR_N_I<1> ADDR_N_I<0> CS00<19> ECLK_H<19> ++ ECLK_H<20> ECLK_B<19> ECLK_B<20> WL_O<319> WL_O<318> WL_O<317> WL_O<316> ++ WL_O<315> WL_O<314> WL_O<313> WL_O<312> WL_O<311> WL_O<310> WL_O<309> ++ WL_O<308> WL_O<307> WL_O<306> WL_O<305> WL_O<304> VDD VSS / ++ RM_IHPSG13_512x16_c2_2P_DEC04 +XSEL<18> ADDR_N_I<3> ADDR_N_I<2> ADDR_N_I<1> ADDR_N_I<0> CS00<18> ECLK_H<18> ++ ECLK_H<19> ECLK_B<18> ECLK_B<19> WL_O<303> WL_O<302> WL_O<301> WL_O<300> ++ WL_O<299> WL_O<298> WL_O<297> WL_O<296> WL_O<295> WL_O<294> WL_O<293> ++ WL_O<292> WL_O<291> WL_O<290> WL_O<289> WL_O<288> VDD VSS / ++ RM_IHPSG13_512x16_c2_2P_DEC04 +XSEL<17> ADDR_N_I<3> ADDR_N_I<2> ADDR_N_I<1> ADDR_N_I<0> CS00<17> ECLK_H<17> ++ ECLK_H<18> ECLK_B<17> ECLK_B<18> WL_O<287> WL_O<286> WL_O<285> WL_O<284> ++ WL_O<283> WL_O<282> WL_O<281> WL_O<280> WL_O<279> WL_O<278> WL_O<277> ++ WL_O<276> WL_O<275> WL_O<274> WL_O<273> WL_O<272> VDD VSS / ++ RM_IHPSG13_512x16_c2_2P_DEC04 +XSEL<16> ADDR_N_I<3> ADDR_N_I<2> ADDR_N_I<1> ADDR_N_I<0> CS00<16> ECLK_H<16> ++ ECLK_H<17> ECLK_B<16> ECLK_B<17> WL_O<271> WL_O<270> WL_O<269> WL_O<268> ++ WL_O<267> WL_O<266> WL_O<265> WL_O<264> WL_O<263> WL_O<262> WL_O<261> ++ WL_O<260> WL_O<259> WL_O<258> WL_O<257> WL_O<256> VDD VSS / ++ RM_IHPSG13_512x16_c2_2P_DEC04 +XSEL<15> ADDR_N_I<3> ADDR_N_I<2> ADDR_N_I<1> ADDR_N_I<0> CS00<15> ECLK_H<15> ++ ECLK_H<16> ECLK_B<15> ECLK_B<16> WL_O<255> WL_O<254> WL_O<253> WL_O<252> ++ WL_O<251> WL_O<250> WL_O<249> WL_O<248> WL_O<247> WL_O<246> WL_O<245> ++ WL_O<244> WL_O<243> WL_O<242> WL_O<241> WL_O<240> VDD VSS / ++ RM_IHPSG13_512x16_c2_2P_DEC04 +XSEL<14> ADDR_N_I<3> ADDR_N_I<2> ADDR_N_I<1> ADDR_N_I<0> CS00<14> ECLK_H<14> ++ ECLK_H<15> ECLK_B<14> ECLK_B<15> WL_O<239> WL_O<238> WL_O<237> WL_O<236> ++ WL_O<235> WL_O<234> WL_O<233> WL_O<232> WL_O<231> WL_O<230> WL_O<229> ++ WL_O<228> WL_O<227> WL_O<226> WL_O<225> WL_O<224> VDD VSS / ++ RM_IHPSG13_512x16_c2_2P_DEC04 +XSEL<13> ADDR_N_I<3> ADDR_N_I<2> ADDR_N_I<1> ADDR_N_I<0> CS00<13> ECLK_H<13> ++ ECLK_H<14> ECLK_B<13> ECLK_B<14> WL_O<223> WL_O<222> WL_O<221> WL_O<220> ++ WL_O<219> WL_O<218> WL_O<217> WL_O<216> WL_O<215> WL_O<214> WL_O<213> ++ WL_O<212> WL_O<211> WL_O<210> WL_O<209> WL_O<208> VDD VSS / ++ RM_IHPSG13_512x16_c2_2P_DEC04 +XSEL<12> ADDR_N_I<3> ADDR_N_I<2> ADDR_N_I<1> ADDR_N_I<0> CS00<12> ECLK_H<12> ++ ECLK_H<13> ECLK_B<12> ECLK_B<13> WL_O<207> WL_O<206> WL_O<205> WL_O<204> ++ WL_O<203> WL_O<202> WL_O<201> WL_O<200> WL_O<199> WL_O<198> WL_O<197> ++ WL_O<196> WL_O<195> WL_O<194> WL_O<193> WL_O<192> VDD VSS / ++ RM_IHPSG13_512x16_c2_2P_DEC04 +XSEL<11> ADDR_N_I<3> ADDR_N_I<2> ADDR_N_I<1> ADDR_N_I<0> CS00<11> ECLK_H<11> ++ ECLK_H<12> ECLK_B<11> ECLK_B<12> WL_O<191> WL_O<190> WL_O<189> WL_O<188> ++ WL_O<187> WL_O<186> WL_O<185> WL_O<184> WL_O<183> WL_O<182> WL_O<181> ++ WL_O<180> WL_O<179> WL_O<178> WL_O<177> WL_O<176> VDD VSS / ++ RM_IHPSG13_512x16_c2_2P_DEC04 +XSEL<10> ADDR_N_I<3> ADDR_N_I<2> ADDR_N_I<1> ADDR_N_I<0> CS00<10> ECLK_H<10> ++ ECLK_H<11> ECLK_B<10> ECLK_B<11> WL_O<175> WL_O<174> WL_O<173> WL_O<172> ++ WL_O<171> WL_O<170> WL_O<169> WL_O<168> WL_O<167> WL_O<166> WL_O<165> ++ WL_O<164> WL_O<163> WL_O<162> WL_O<161> WL_O<160> VDD VSS / ++ RM_IHPSG13_512x16_c2_2P_DEC04 +XSEL<9> ADDR_N_I<3> ADDR_N_I<2> ADDR_N_I<1> ADDR_N_I<0> CS00<9> ECLK_H<9> ++ ECLK_H<10> ECLK_B<9> ECLK_B<10> WL_O<159> WL_O<158> WL_O<157> WL_O<156> ++ WL_O<155> WL_O<154> WL_O<153> WL_O<152> WL_O<151> WL_O<150> WL_O<149> ++ WL_O<148> WL_O<147> WL_O<146> WL_O<145> WL_O<144> VDD VSS / ++ RM_IHPSG13_512x16_c2_2P_DEC04 +XSEL<8> ADDR_N_I<3> ADDR_N_I<2> ADDR_N_I<1> ADDR_N_I<0> CS00<8> ECLK_H<8> ++ ECLK_H<9> ECLK_B<8> ECLK_B<9> WL_O<143> WL_O<142> WL_O<141> WL_O<140> ++ WL_O<139> WL_O<138> WL_O<137> WL_O<136> WL_O<135> WL_O<134> WL_O<133> ++ WL_O<132> WL_O<131> WL_O<130> WL_O<129> WL_O<128> VDD VSS / ++ RM_IHPSG13_512x16_c2_2P_DEC04 +XSEL<7> ADDR_N_I<3> ADDR_N_I<2> ADDR_N_I<1> ADDR_N_I<0> CS00<7> ECLK_H<7> ++ ECLK_H<8> ECLK_B<7> ECLK_B<8> WL_O<127> WL_O<126> WL_O<125> WL_O<124> ++ WL_O<123> WL_O<122> WL_O<121> WL_O<120> WL_O<119> WL_O<118> WL_O<117> ++ WL_O<116> WL_O<115> WL_O<114> WL_O<113> WL_O<112> VDD VSS / ++ RM_IHPSG13_512x16_c2_2P_DEC04 +XSEL<6> ADDR_N_I<3> ADDR_N_I<2> ADDR_N_I<1> ADDR_N_I<0> CS00<6> ECLK_H<6> ++ ECLK_H<7> ECLK_B<6> ECLK_B<7> WL_O<111> WL_O<110> WL_O<109> WL_O<108> ++ WL_O<107> WL_O<106> WL_O<105> WL_O<104> WL_O<103> WL_O<102> WL_O<101> ++ WL_O<100> WL_O<99> WL_O<98> WL_O<97> WL_O<96> VDD VSS / ++ RM_IHPSG13_512x16_c2_2P_DEC04 +XSEL<5> ADDR_N_I<3> ADDR_N_I<2> ADDR_N_I<1> ADDR_N_I<0> CS00<5> ECLK_H<5> ++ ECLK_H<6> ECLK_B<5> ECLK_B<6> WL_O<95> WL_O<94> WL_O<93> WL_O<92> WL_O<91> ++ WL_O<90> WL_O<89> WL_O<88> WL_O<87> WL_O<86> WL_O<85> WL_O<84> WL_O<83> ++ WL_O<82> WL_O<81> WL_O<80> VDD VSS / RM_IHPSG13_512x16_c2_2P_DEC04 +XSEL<4> ADDR_N_I<3> ADDR_N_I<2> ADDR_N_I<1> ADDR_N_I<0> CS00<4> ECLK_H<4> ++ ECLK_H<5> ECLK_B<4> ECLK_B<5> WL_O<79> WL_O<78> WL_O<77> WL_O<76> WL_O<75> ++ WL_O<74> WL_O<73> WL_O<72> WL_O<71> WL_O<70> WL_O<69> WL_O<68> WL_O<67> ++ WL_O<66> WL_O<65> WL_O<64> VDD VSS / RM_IHPSG13_512x16_c2_2P_DEC04 +XSEL<3> ADDR_N_I<3> ADDR_N_I<2> ADDR_N_I<1> ADDR_N_I<0> CS00<3> ECLK_H<3> ++ ECLK_H<4> ECLK_B<3> ECLK_B<4> WL_O<63> WL_O<62> WL_O<61> WL_O<60> WL_O<59> ++ WL_O<58> WL_O<57> WL_O<56> WL_O<55> WL_O<54> WL_O<53> WL_O<52> WL_O<51> ++ WL_O<50> WL_O<49> WL_O<48> VDD VSS / RM_IHPSG13_512x16_c2_2P_DEC04 +XSEL<2> ADDR_N_I<3> ADDR_N_I<2> ADDR_N_I<1> ADDR_N_I<0> CS00<2> ECLK_H<2> ++ ECLK_H<3> ECLK_B<2> ECLK_B<3> WL_O<47> WL_O<46> WL_O<45> WL_O<44> WL_O<43> ++ WL_O<42> WL_O<41> WL_O<40> WL_O<39> WL_O<38> WL_O<37> WL_O<36> WL_O<35> ++ WL_O<34> WL_O<33> WL_O<32> VDD VSS / RM_IHPSG13_512x16_c2_2P_DEC04 +XSEL<1> ADDR_N_I<3> ADDR_N_I<2> ADDR_N_I<1> ADDR_N_I<0> CS00<1> ECLK_H<1> ++ ECLK_H<2> ECLK_B<1> ECLK_B<2> WL_O<31> WL_O<30> WL_O<29> WL_O<28> WL_O<27> ++ WL_O<26> WL_O<25> WL_O<24> WL_O<23> WL_O<22> WL_O<21> WL_O<20> WL_O<19> ++ WL_O<18> WL_O<17> WL_O<16> VDD VSS / RM_IHPSG13_512x16_c2_2P_DEC04 +XSEL<0> ADDR_N_I<3> ADDR_N_I<2> ADDR_N_I<1> ADDR_N_I<0> CS00<0> ECLK_I ++ ECLK_H<1> ECLK_B<0> ECLK_B<1> WL_O<15> WL_O<14> WL_O<13> WL_O<12> WL_O<11> ++ WL_O<10> WL_O<9> WL_O<8> WL_O<7> WL_O<6> WL_O<5> WL_O<4> WL_O<3> WL_O<2> ++ WL_O<1> WL_O<0> VDD VSS / RM_IHPSG13_512x16_c2_2P_DEC04 +XDEC10<9> ADDR_N_I<7> ADDR_N_I<6> CS04<1> CS02<6> VDD VSS / ++ RM_IHPSG13_512x16_c2_2P_DEC02 +XDEC10<8> ADDR_N_I<7> ADDR_N_I<6> CS04<0> CS02<2> VDD VSS / ++ RM_IHPSG13_512x16_c2_2P_DEC02 +XDEC10<7> ADDR_N_I<5> ADDR_N_I<4> CS02<7> CS00<30> VDD VSS / ++ RM_IHPSG13_512x16_c2_2P_DEC02 +XDEC10<6> ADDR_N_I<5> ADDR_N_I<4> CS02<6> CS00<26> VDD VSS / ++ RM_IHPSG13_512x16_c2_2P_DEC02 +XDEC10<5> ADDR_N_I<5> ADDR_N_I<4> CS02<5> CS00<22> VDD VSS / ++ RM_IHPSG13_512x16_c2_2P_DEC02 +XDEC10<4> ADDR_N_I<5> ADDR_N_I<4> CS02<4> CS00<18> VDD VSS / ++ RM_IHPSG13_512x16_c2_2P_DEC02 +XDEC10<3> ADDR_N_I<5> ADDR_N_I<4> CS02<3> CS00<14> VDD VSS / ++ RM_IHPSG13_512x16_c2_2P_DEC02 +XDEC10<2> ADDR_N_I<5> ADDR_N_I<4> CS02<2> CS00<10> VDD VSS / ++ RM_IHPSG13_512x16_c2_2P_DEC02 +XDEC10<1> ADDR_N_I<5> ADDR_N_I<4> CS02<1> CS00<6> VDD VSS / ++ RM_IHPSG13_512x16_c2_2P_DEC02 +XDEC10<0> ADDR_N_I<5> ADDR_N_I<4> CS02<0> CS00<2> VDD VSS / ++ RM_IHPSG13_512x16_c2_2P_DEC02 +XDEC01<10> ADDR_N_I<9> ADDR_N_I<8> CS_I CS04<1> VDD VSS / ++ RM_IHPSG13_512x16_c2_2P_DEC01 +XDEC01<9> ADDR_N_I<7> ADDR_N_I<6> CS04<1> CS02<5> VDD VSS / ++ RM_IHPSG13_512x16_c2_2P_DEC01 +XDEC01<8> ADDR_N_I<7> ADDR_N_I<6> CS04<0> CS02<1> VDD VSS / ++ RM_IHPSG13_512x16_c2_2P_DEC01 +XDEC01<7> ADDR_N_I<5> ADDR_N_I<4> CS02<7> CS00<29> VDD VSS / ++ RM_IHPSG13_512x16_c2_2P_DEC01 +XDEC01<6> ADDR_N_I<5> ADDR_N_I<4> CS02<6> CS00<25> VDD VSS / ++ RM_IHPSG13_512x16_c2_2P_DEC01 +XDEC01<5> ADDR_N_I<5> ADDR_N_I<4> CS02<5> CS00<21> VDD VSS / ++ RM_IHPSG13_512x16_c2_2P_DEC01 +XDEC01<4> ADDR_N_I<5> ADDR_N_I<4> CS02<4> CS00<17> VDD VSS / ++ RM_IHPSG13_512x16_c2_2P_DEC01 +XDEC01<3> ADDR_N_I<5> ADDR_N_I<4> CS02<3> CS00<13> VDD VSS / ++ RM_IHPSG13_512x16_c2_2P_DEC01 +XDEC01<2> ADDR_N_I<5> ADDR_N_I<4> CS02<2> CS00<9> VDD VSS / ++ RM_IHPSG13_512x16_c2_2P_DEC01 +XDEC01<1> ADDR_N_I<5> ADDR_N_I<4> CS02<1> CS00<5> VDD VSS / ++ RM_IHPSG13_512x16_c2_2P_DEC01 +XDEC01<0> ADDR_N_I<5> ADDR_N_I<4> CS02<0> CS00<1> VDD VSS / ++ RM_IHPSG13_512x16_c2_2P_DEC01 +XL2<258> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<257> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<256> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<255> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<254> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<253> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<252> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<251> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<250> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<249> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<248> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<247> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<246> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<245> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<244> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<243> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<242> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<241> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<240> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<239> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<238> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<237> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<236> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<235> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<234> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<233> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<232> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<231> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<230> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<229> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<228> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<227> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<226> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<225> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<224> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<223> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<222> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<221> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<220> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<219> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<218> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<217> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<216> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<215> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<214> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<213> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<212> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<211> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<210> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<209> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<208> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<207> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<206> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<205> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<204> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<203> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<202> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<201> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<200> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<199> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<198> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<197> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<196> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<195> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<194> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<193> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<192> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<191> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<190> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<189> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<188> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<187> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<186> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<185> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<184> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<183> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<182> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<181> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<180> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<179> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<178> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<177> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<176> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<175> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<174> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<173> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<172> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<171> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<170> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<169> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<168> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<167> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<166> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<165> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<164> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<163> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<162> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<161> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<160> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<159> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<158> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<157> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<156> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<155> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<154> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<153> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<152> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<151> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<150> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<149> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<148> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<147> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<146> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<145> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<144> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<143> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<142> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<141> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<140> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<139> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<138> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<137> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<136> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<135> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<134> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<133> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<132> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<131> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<130> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<129> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<128> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<127> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<126> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<125> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<124> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<123> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<122> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<121> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<120> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<119> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<118> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<117> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<116> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<115> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<114> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<113> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<112> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<111> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<110> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<109> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<108> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<107> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<106> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<105> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<104> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<103> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<102> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<101> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<100> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<99> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<98> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<97> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<96> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<95> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<94> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<93> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<92> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<91> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<90> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<89> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<88> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<87> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<86> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<85> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<84> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<83> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<82> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<81> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<80> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<79> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<78> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<77> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<76> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<75> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<74> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<73> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<72> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<71> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<70> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<69> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<68> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<67> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<66> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<65> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<64> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<63> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<62> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<61> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<60> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<59> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<58> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<57> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<56> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<55> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<54> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<53> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<52> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<51> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<50> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<49> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<48> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<47> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<46> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<45> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<44> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<43> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<42> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<41> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<40> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<39> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<38> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<37> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<36> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<35> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<34> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<33> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<32> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<31> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<30> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<29> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<28> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<27> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<26> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<25> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<24> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<23> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<22> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<21> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<20> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<19> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<18> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<17> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<16> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<15> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<14> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<13> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<12> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<11> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<10> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<9> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<8> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<7> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<6> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<5> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<4> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<3> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<2> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<1> VDD VSS / RSC_IHPSG13_FILLCAP8 +XDEC00<10> ADDR_N_I<9> ADDR_N_I<8> CS_I CS04<0> VDD VSS / ++ RM_IHPSG13_512x16_c2_2P_DEC00 +XDEC00<9> ADDR_N_I<7> ADDR_N_I<6> CS04<1> CS02<4> VDD VSS / ++ RM_IHPSG13_512x16_c2_2P_DEC00 +XDEC00<8> ADDR_N_I<7> ADDR_N_I<6> CS04<0> CS02<0> VDD VSS / ++ RM_IHPSG13_512x16_c2_2P_DEC00 +XDEC00<7> ADDR_N_I<5> ADDR_N_I<4> CS02<7> CS00<28> VDD VSS / ++ RM_IHPSG13_512x16_c2_2P_DEC00 +XDEC00<6> ADDR_N_I<5> ADDR_N_I<4> CS02<6> CS00<24> VDD VSS / ++ RM_IHPSG13_512x16_c2_2P_DEC00 +XDEC00<5> ADDR_N_I<5> ADDR_N_I<4> CS02<5> CS00<20> VDD VSS / ++ RM_IHPSG13_512x16_c2_2P_DEC00 +XDEC00<4> ADDR_N_I<5> ADDR_N_I<4> CS02<4> CS00<16> VDD VSS / ++ RM_IHPSG13_512x16_c2_2P_DEC00 +XDEC00<3> ADDR_N_I<5> ADDR_N_I<4> CS02<3> CS00<12> VDD VSS / ++ RM_IHPSG13_512x16_c2_2P_DEC00 +XDEC00<2> ADDR_N_I<5> ADDR_N_I<4> CS02<2> CS00<8> VDD VSS / ++ RM_IHPSG13_512x16_c2_2P_DEC00 +XDEC00<1> ADDR_N_I<5> ADDR_N_I<4> CS02<1> CS00<4> VDD VSS / ++ RM_IHPSG13_512x16_c2_2P_DEC00 +XDEC00<0> ADDR_N_I<5> ADDR_N_I<4> CS02<0> CS00<0> VDD VSS / ++ RM_IHPSG13_512x16_c2_2P_DEC00 +XDEC11<9> ADDR_N_I<7> ADDR_N_I<6> CS04<1> CS02<7> VDD VSS / ++ RM_IHPSG13_512x16_c2_2P_DEC03 +XDEC11<8> ADDR_N_I<7> ADDR_N_I<6> CS04<0> CS02<3> VDD VSS / ++ RM_IHPSG13_512x16_c2_2P_DEC03 +XDEC11<7> ADDR_N_I<5> ADDR_N_I<4> CS02<7> CS00<31> VDD VSS / ++ RM_IHPSG13_512x16_c2_2P_DEC03 +XDEC11<6> ADDR_N_I<5> ADDR_N_I<4> CS02<6> CS00<27> VDD VSS / ++ RM_IHPSG13_512x16_c2_2P_DEC03 +XDEC11<5> ADDR_N_I<5> ADDR_N_I<4> CS02<5> CS00<23> VDD VSS / ++ RM_IHPSG13_512x16_c2_2P_DEC03 +XDEC11<4> ADDR_N_I<5> ADDR_N_I<4> CS02<4> CS00<19> VDD VSS / ++ RM_IHPSG13_512x16_c2_2P_DEC03 +XDEC11<3> ADDR_N_I<5> ADDR_N_I<4> CS02<3> CS00<15> VDD VSS / ++ RM_IHPSG13_512x16_c2_2P_DEC03 +XDEC11<2> ADDR_N_I<5> ADDR_N_I<4> CS02<2> CS00<11> VDD VSS / ++ RM_IHPSG13_512x16_c2_2P_DEC03 +XDEC11<1> ADDR_N_I<5> ADDR_N_I<4> CS02<1> CS00<7> VDD VSS / ++ RM_IHPSG13_512x16_c2_2P_DEC03 +XDEC11<0> ADDR_N_I<5> ADDR_N_I<4> CS02<0> CS00<3> VDD VSS / ++ RM_IHPSG13_512x16_c2_2P_DEC03 +XI0 ADDR_N_I<9> VDD VSS / RSC_IHPSG13_TIEL +.ENDS +.SUBCKT RM_IHPSG13_512x16_c2_2P_ROWREG9 ACLK_N_I ADDR_I<8> ADDR_I<7> ADDR_I<6> ADDR_I<5> ++ ADDR_I<4> ADDR_I<3> ADDR_I<2> ADDR_I<1> ADDR_I<0> ADDR_N_O<8> ADDR_N_O<7> ++ ADDR_N_O<6> ADDR_N_O<5> ADDR_N_O<4> ADDR_N_O<3> ADDR_N_O<2> ADDR_N_O<1> ++ ADDR_N_O<0> BIST_ADDR_I<8> BIST_ADDR_I<7> BIST_ADDR_I<6> BIST_ADDR_I<5> ++ BIST_ADDR_I<4> BIST_ADDR_I<3> BIST_ADDR_I<2> BIST_ADDR_I<1> BIST_ADDR_I<0> ++ BIST_EN_I VDD VSS +XDFF<8> BIST_EN_I BIST_ADDR_I<8> ACLK_N_I ADDR_I<8> q_int<8> net04<0> VDD ++ VSS / RSC_IHPSG13_DFNQMX2IX1 +XDFF<7> BIST_EN_I BIST_ADDR_I<7> ACLK_N_I ADDR_I<7> q_int<7> net04<1> VDD ++ VSS / RSC_IHPSG13_DFNQMX2IX1 +XDFF<6> BIST_EN_I BIST_ADDR_I<6> ACLK_N_I ADDR_I<6> q_int<6> net04<2> VDD ++ VSS / RSC_IHPSG13_DFNQMX2IX1 +XDFF<5> BIST_EN_I BIST_ADDR_I<5> ACLK_N_I ADDR_I<5> q_int<5> net04<3> VDD ++ VSS / RSC_IHPSG13_DFNQMX2IX1 +XDFF<4> BIST_EN_I BIST_ADDR_I<4> ACLK_N_I ADDR_I<4> q_int<4> net04<4> VDD ++ VSS / RSC_IHPSG13_DFNQMX2IX1 +XDFF<3> BIST_EN_I BIST_ADDR_I<3> ACLK_N_I ADDR_I<3> q_int<3> net04<5> VDD ++ VSS / RSC_IHPSG13_DFNQMX2IX1 +XDFF<2> BIST_EN_I BIST_ADDR_I<2> ACLK_N_I ADDR_I<2> q_int<2> net04<6> VDD ++ VSS / RSC_IHPSG13_DFNQMX2IX1 +XDFF<1> BIST_EN_I BIST_ADDR_I<1> ACLK_N_I ADDR_I<1> q_int<1> net04<7> VDD ++ VSS / RSC_IHPSG13_DFNQMX2IX1 +XDFF<0> BIST_EN_I BIST_ADDR_I<0> ACLK_N_I ADDR_I<0> q_int<0> net04<8> VDD ++ VSS / RSC_IHPSG13_DFNQMX2IX1 +XDRV<8> qn_int<8> ADDR_N_O<8> VDD VSS / RSC_IHPSG13_CINVX8 +XDRV<7> qn_int<7> ADDR_N_O<7> VDD VSS / RSC_IHPSG13_CINVX8 +XDRV<6> qn_int<6> ADDR_N_O<6> VDD VSS / RSC_IHPSG13_CINVX8 +XDRV<5> qn_int<5> ADDR_N_O<5> VDD VSS / RSC_IHPSG13_CINVX8 +XDRV<4> qn_int<4> ADDR_N_O<4> VDD VSS / RSC_IHPSG13_CINVX8 +XDRV<3> qn_int<3> ADDR_N_O<3> VDD VSS / RSC_IHPSG13_CINVX8 +XDRV<2> qn_int<2> ADDR_N_O<2> VDD VSS / RSC_IHPSG13_CINVX8 +XDRV<1> qn_int<1> ADDR_N_O<1> VDD VSS / RSC_IHPSG13_CINVX8 +XDRV<0> qn_int<0> ADDR_N_O<0> VDD VSS / RSC_IHPSG13_CINVX8 +XINV<8> q_int<8> qn_int<8> VDD VSS / RSC_IHPSG13_CINVX2 +XINV<7> q_int<7> qn_int<7> VDD VSS / RSC_IHPSG13_CINVX2 +XINV<6> q_int<6> qn_int<6> VDD VSS / RSC_IHPSG13_CINVX2 +XINV<5> q_int<5> qn_int<5> VDD VSS / RSC_IHPSG13_CINVX2 +XINV<4> q_int<4> qn_int<4> VDD VSS / RSC_IHPSG13_CINVX2 +XINV<3> q_int<3> qn_int<3> VDD VSS / RSC_IHPSG13_CINVX2 +XINV<2> q_int<2> qn_int<2> VDD VSS / RSC_IHPSG13_CINVX2 +XINV<1> q_int<1> qn_int<1> VDD VSS / RSC_IHPSG13_CINVX2 +XINV<0> q_int<0> qn_int<0> VDD VSS / RSC_IHPSG13_CINVX2 +.ENDS + +.SUBCKT RM_IHPSG13_512x16_c2_2P_DLY_MUX A SEL Z VDD VSS +XI11 net4 Z VDD VSS / RSC_IHPSG13_CINVX2 +XI8 A D<3> SEL net4 VDD VSS / RSC_IHPSG13_MX2IX1 +XI20<3> D<2> D<3> VDD VSS / RSC_IHPSG13_CDLYX1 +XI20<2> D<1> D<2> VDD VSS / RSC_IHPSG13_CDLYX1 +XI20<1> A D<1> VDD VSS / RSC_IHPSG13_CDLYX1 +.ENDS +.SUBCKT RM_IHPSG13_512x16_c2_2P_CTRL ACLK_N BIST_CK_I BIST_CS_I BIST_EN BIST_RE_I ++ BIST_WE_I B_TIEL_O CK_I CS_I DCLK ECLK PULSE_H PULSE_L PULSE_O RCLK RE_I ++ ROW_CS WCLK WE_I VDD VSS +XI17 ck_regs we col_we VDD VSS / RSC_IHPSG13_DFNQX2 +XI16 ck_regs re col_re VDD VSS / RSC_IHPSG13_DFNQX2 +XI18 ck_regs cs net7 VDD VSS / RSC_IHPSG13_DFNQX2 +XI71 ACLK_N net012 PULSE_O VDD VSS / RSC_IHPSG13_DFNQX2 +XI77 col_we net017 net016 VDD VSS / RSC_IHPSG13_CNAND2X2 +XI76 col_re net017 net018 VDD VSS / RSC_IHPSG13_CNAND2X2 +XI15 ck_dly WEorREandCS aclk VDD VSS / RSC_IHPSG13_CGATEPX4 +XI14 ck WEandCS DCLK VDD VSS / RSC_IHPSG13_CGATEPX4 +XI60 net7 ROW_CS VDD VSS / RSC_IHPSG13_CBUFX8 +XI73 PULSE_O net012 VDD VSS / RSC_IHPSG13_CINVX2 +XI8 net017 net8 VDD VSS / RSC_IHPSG13_CINVX2 +XCAPS4<7> VDD VSS / RSC_IHPSG13_FILLCAP4 +XCAPS4<6> VDD VSS / RSC_IHPSG13_FILLCAP4 +XCAPS4<5> VDD VSS / RSC_IHPSG13_FILLCAP4 +XCAPS4<4> VDD VSS / RSC_IHPSG13_FILLCAP4 +XCAPS4<3> VDD VSS / RSC_IHPSG13_FILLCAP4 +XCAPS4<2> VDD VSS / RSC_IHPSG13_FILLCAP4 +XCAPS4<1> VDD VSS / RSC_IHPSG13_FILLCAP4 +XBM_TIEL B_TIEL_O VDD VSS / RSC_IHPSG13_TIEL +XI64 ck ck_dly VDD VSS / RSC_IHPSG13_CDLYX2 +XI86 CS_I BIST_CS_I BIST_EN cs VDD VSS / RSC_IHPSG13_MX2X2 +XI87 CK_I BIST_CK_I BIST_EN ck VDD VSS / RSC_IHPSG13_MX2X2 +XI85 WE_I BIST_WE_I BIST_EN we VDD VSS / RSC_IHPSG13_MX2X2 +XI84 RE_I BIST_RE_I BIST_EN re VDD VSS / RSC_IHPSG13_MX2X2 +XI48 ck_dly ck_regs VDD VSS / RSC_IHPSG13_CINVX4 +XI81 net016 WCLK VDD VSS / RSC_IHPSG13_CINVX4 +XI80 net018 RCLK VDD VSS / RSC_IHPSG13_CINVX4 +XI78 net8 net020 VDD VSS / RSC_IHPSG13_CINVX4 +XCAPS8<7> VDD VSS / RSC_IHPSG13_FILLCAP8 +XCAPS8<6> VDD VSS / RSC_IHPSG13_FILLCAP8 +XCAPS8<5> VDD VSS / RSC_IHPSG13_FILLCAP8 +XCAPS8<4> VDD VSS / RSC_IHPSG13_FILLCAP8 +XCAPS8<3> VDD VSS / RSC_IHPSG13_FILLCAP8 +XCAPS8<2> VDD VSS / RSC_IHPSG13_FILLCAP8 +XCAPS8<1> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI6 PULSE_L PULSE_H net017 VDD VSS / RSC_IHPSG13_XOR2X2 +XI22 we cs WEandCS VDD VSS / RSC_IHPSG13_AND2X2 +XI79 net020 ECLK VDD VSS / RSC_IHPSG13_CINVX8 +XI63 aclk ACLK_N VDD VSS / RSC_IHPSG13_CINVX8 +XI21 re we cs WEorREandCS VDD VSS / RSC_IHPSG13_OA12X1 +.ENDS +.SUBCKT RM_IHPSG13_512x16_c2_2P_COLDEC5 ACLK_N ADDR<4> ADDR<3> ADDR<2> ADDR<1> ADDR<0> ++ ADDR_COL<1> ADDR_COL<0> ADDR_DEC<7> ADDR_DEC<6> ADDR_DEC<5> ADDR_DEC<4> ++ ADDR_DEC<3> ADDR_DEC<2> ADDR_DEC<1> ADDR_DEC<0> BIST_ADDR<4> BIST_ADDR<3> ++ BIST_ADDR<2> BIST_ADDR<1> BIST_ADDR<0> BIST_EN_I VDD VSS +XI17<4> VDD VSS / RSC_IHPSG13_FILLCAP4 +XI17<3> VDD VSS / RSC_IHPSG13_FILLCAP4 +XI17<2> VDD VSS / RSC_IHPSG13_FILLCAP4 +XI17<1> VDD VSS / RSC_IHPSG13_FILLCAP4 +XI1<7> PADR<0> PADR<1> PADR<2> addr_n<7> VDD VSS / RSC_IHPSG13_NAND3X2 +XI1<6> NADR<0> PADR<1> PADR<2> addr_n<6> VDD VSS / RSC_IHPSG13_NAND3X2 +XI1<5> PADR<0> NADR<1> PADR<2> addr_n<5> VDD VSS / RSC_IHPSG13_NAND3X2 +XI1<4> NADR<0> NADR<1> PADR<2> addr_n<4> VDD VSS / RSC_IHPSG13_NAND3X2 +XI1<3> PADR<0> PADR<1> NADR<2> addr_n<3> VDD VSS / RSC_IHPSG13_NAND3X2 +XI1<2> NADR<0> PADR<1> NADR<2> addr_n<2> VDD VSS / RSC_IHPSG13_NAND3X2 +XI1<1> PADR<0> NADR<1> NADR<2> addr_n<1> VDD VSS / RSC_IHPSG13_NAND3X2 +XI1<0> NADR<0> NADR<1> NADR<2> addr_n<0> VDD VSS / RSC_IHPSG13_NAND3X2 +XDFF<4> BIST_EN_I BIST_ADDR<4> ACLK_N ADDR<4> addr_int<1> net13<0> VDD ++ VSS / RSC_IHPSG13_DFNQMX2IX1 +XDFF<3> BIST_EN_I BIST_ADDR<3> ACLK_N ADDR<3> addr_int<0> net13<1> VDD ++ VSS / RSC_IHPSG13_DFNQMX2IX1 +XDFF<2> BIST_EN_I BIST_ADDR<2> ACLK_N ADDR<2> padr_int<2> net13<2> VDD ++ VSS / RSC_IHPSG13_DFNQMX2IX1 +XDFF<1> BIST_EN_I BIST_ADDR<1> ACLK_N ADDR<1> padr_int<1> net13<3> VDD ++ VSS / RSC_IHPSG13_DFNQMX2IX1 +XDFF<0> BIST_EN_I BIST_ADDR<0> ACLK_N ADDR<0> padr_int<0> net13<4> VDD ++ VSS / RSC_IHPSG13_DFNQMX2IX1 +XI3<2> padr_int<2> NADR<2> VDD VSS / RSC_IHPSG13_INVX2 +XI3<1> padr_int<1> NADR<1> VDD VSS / RSC_IHPSG13_INVX2 +XI3<0> padr_int<0> NADR<0> VDD VSS / RSC_IHPSG13_INVX2 +XI2<7> addr_n<7> ADDR_DEC<7> VDD VSS / RSC_IHPSG13_INVX2 +XI2<6> addr_n<6> ADDR_DEC<6> VDD VSS / RSC_IHPSG13_INVX2 +XI2<5> addr_n<5> ADDR_DEC<5> VDD VSS / RSC_IHPSG13_INVX2 +XI2<4> addr_n<4> ADDR_DEC<4> VDD VSS / RSC_IHPSG13_INVX2 +XI2<3> addr_n<3> ADDR_DEC<3> VDD VSS / RSC_IHPSG13_INVX2 +XI2<2> addr_n<2> ADDR_DEC<2> VDD VSS / RSC_IHPSG13_INVX2 +XI2<1> addr_n<1> ADDR_DEC<1> VDD VSS / RSC_IHPSG13_INVX2 +XI2<0> addr_n<0> ADDR_DEC<0> VDD VSS / RSC_IHPSG13_INVX2 +XI15<2> NADR<2> PADR<2> VDD VSS / RSC_IHPSG13_INVX2 +XI15<1> NADR<1> PADR<1> VDD VSS / RSC_IHPSG13_INVX2 +XI15<0> NADR<0> PADR<0> VDD VSS / RSC_IHPSG13_INVX2 +XI13<1> addr_int<1> ADDR_COL<1> VDD VSS / RSC_IHPSG13_CBUFX2 +XI13<0> addr_int<0> ADDR_COL<0> VDD VSS / RSC_IHPSG13_CBUFX2 +XI14<5> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI14<4> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI14<3> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI14<2> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI14<1> VDD VSS / RSC_IHPSG13_FILLCAP8 +.ENDS +.SUBCKT RM_IHPSG13_512x16_c2_2P_BLDRV A_BLC<3> A_BLC<2> A_BLC<1> A_BLC<0> A_BLC_SEL ++ A_BLT<3> A_BLT<2> A_BLT<1> A_BLT<0> A_BLT_SEL A_PRE_N A_SEL_P<3> A_SEL_P<2> ++ A_SEL_P<1> A_SEL_P<0> A_WR_ONE A_WR_ZERO B_BLC<3> B_BLC<2> B_BLC<1> B_BLC<0> ++ B_BLC_SEL B_BLT<3> B_BLT<2> B_BLT<1> B_BLT<0> B_BLT_SEL B_PRE_N B_SEL_P<3> ++ B_SEL_P<2> B_SEL_P<1> B_SEL_P<0> B_WR_ONE B_WR_ZERO VDD VSS +MA_CWN<3> A_BLC<3> A_BLC_NMOS_DRIVE<3> VSS VSS sg13_lv_nmos m=1 ++ w=4.82u l=130.00n ng=2 nrd=0 nrs=0 +MA_CWN<2> A_BLC<2> A_BLC_NMOS_DRIVE<2> VSS VSS sg13_lv_nmos m=1 ++ w=4.82u l=130.00n ng=2 nrd=0 nrs=0 +MA_CWN<1> A_BLC<1> A_BLC_NMOS_DRIVE<1> VSS VSS sg13_lv_nmos m=1 ++ w=4.82u l=130.00n ng=2 nrd=0 nrs=0 +MA_CWN<0> A_BLC<0> A_BLC_NMOS_DRIVE<0> VSS VSS sg13_lv_nmos m=1 ++ w=4.82u l=130.00n ng=2 nrd=0 nrs=0 +MA_TWN<3> A_BLT<3> A_BLT_NMOS_DRIVE<3> VSS VSS sg13_lv_nmos m=1 ++ w=4.82u l=130.00n ng=2 nrd=0 nrs=0 +MA_TWN<2> A_BLT<2> A_BLT_NMOS_DRIVE<2> VSS VSS sg13_lv_nmos m=1 ++ w=4.82u l=130.00n ng=2 nrd=0 nrs=0 +MA_TWN<1> A_BLT<1> A_BLT_NMOS_DRIVE<1> VSS VSS sg13_lv_nmos m=1 ++ w=4.82u l=130.00n ng=2 nrd=0 nrs=0 +MA_TWN<0> A_BLT<0> A_BLT_NMOS_DRIVE<0> VSS VSS sg13_lv_nmos m=1 ++ w=4.82u l=130.00n ng=2 nrd=0 nrs=0 +MB_TWN<3> B_BLT<3> B_BLT_NMOS_DRIVE<3> VSS VSS sg13_lv_nmos m=1 ++ w=4.82u l=130.00n ng=2 nrd=0 nrs=0 +MB_TWN<2> B_BLT<2> B_BLT_NMOS_DRIVE<2> VSS VSS sg13_lv_nmos m=1 ++ w=4.82u l=130.00n ng=2 nrd=0 nrs=0 +MB_TWN<1> B_BLT<1> B_BLT_NMOS_DRIVE<1> VSS VSS sg13_lv_nmos m=1 ++ w=4.82u l=130.00n ng=2 nrd=0 nrs=0 +MB_TWN<0> B_BLT<0> B_BLT_NMOS_DRIVE<0> VSS VSS sg13_lv_nmos m=1 ++ w=4.82u l=130.00n ng=2 nrd=0 nrs=0 +MB_CWN<3> B_BLC<3> B_BLC_NMOS_DRIVE<3> VSS VSS sg13_lv_nmos m=1 ++ w=4.82u l=130.00n ng=2 nrd=0 nrs=0 +MB_CWN<2> B_BLC<2> B_BLC_NMOS_DRIVE<2> VSS VSS sg13_lv_nmos m=1 ++ w=4.82u l=130.00n ng=2 nrd=0 nrs=0 +MB_CWN<1> B_BLC<1> B_BLC_NMOS_DRIVE<1> VSS VSS sg13_lv_nmos m=1 ++ w=4.82u l=130.00n ng=2 nrd=0 nrs=0 +MB_CWN<0> B_BLC<0> B_BLC_NMOS_DRIVE<0> VSS VSS sg13_lv_nmos m=1 ++ w=4.82u l=130.00n ng=2 nrd=0 nrs=0 +MA_CPR<3> A_BLC<3> A_PRE_N VDD VDD sg13_lv_pmos m=1 w=3.000u l=130.00n ++ ng=2 nrd=0 nrs=0 +MA_CPR<2> A_BLC<2> A_PRE_N VDD VDD sg13_lv_pmos m=1 w=3.000u l=130.00n ++ ng=2 nrd=0 nrs=0 +MA_CPR<1> A_BLC<1> A_PRE_N VDD VDD sg13_lv_pmos m=1 w=3.000u l=130.00n ++ ng=2 nrd=0 nrs=0 +MA_CPR<0> A_BLC<0> A_PRE_N VDD VDD sg13_lv_pmos m=1 w=3.000u l=130.00n ++ ng=2 nrd=0 nrs=0 +MA_TWP<3> A_BLT<3> A_BLT_PMOS_DRIVE<3> VDD VDD sg13_lv_pmos m=1 w=1.5u ++ l=130.00n ng=1 nrd=0 nrs=0 +MA_TWP<2> A_BLT<2> A_BLT_PMOS_DRIVE<2> VDD VDD sg13_lv_pmos m=1 w=1.5u ++ l=130.00n ng=1 nrd=0 nrs=0 +MA_TWP<1> A_BLT<1> A_BLT_PMOS_DRIVE<1> VDD VDD sg13_lv_pmos m=1 w=1.5u ++ l=130.00n ng=1 nrd=0 nrs=0 +MA_TWP<0> A_BLT<0> A_BLT_PMOS_DRIVE<0> VDD VDD sg13_lv_pmos m=1 w=1.5u ++ l=130.00n ng=1 nrd=0 nrs=0 +MA_CWP<3> A_BLC<3> A_BLC_PMOS_DRIVE<3> VDD VDD sg13_lv_pmos m=1 w=1.5u ++ l=130.00n ng=1 nrd=0 nrs=0 +MA_CWP<2> A_BLC<2> A_BLC_PMOS_DRIVE<2> VDD VDD sg13_lv_pmos m=1 w=1.5u ++ l=130.00n ng=1 nrd=0 nrs=0 +MA_CWP<1> A_BLC<1> A_BLC_PMOS_DRIVE<1> VDD VDD sg13_lv_pmos m=1 w=1.5u ++ l=130.00n ng=1 nrd=0 nrs=0 +MA_CWP<0> A_BLC<0> A_BLC_PMOS_DRIVE<0> VDD VDD sg13_lv_pmos m=1 w=1.5u ++ l=130.00n ng=1 nrd=0 nrs=0 +MA_TPR<3> A_BLT<3> A_PRE_N VDD VDD sg13_lv_pmos m=1 w=3.000u l=130.00n ++ ng=2 nrd=0 nrs=0 +MA_TPR<2> A_BLT<2> A_PRE_N VDD VDD sg13_lv_pmos m=1 w=3.000u l=130.00n ++ ng=2 nrd=0 nrs=0 +MA_TPR<1> A_BLT<1> A_PRE_N VDD VDD sg13_lv_pmos m=1 w=3.000u l=130.00n ++ ng=2 nrd=0 nrs=0 +MA_TPR<0> A_BLT<0> A_PRE_N VDD VDD sg13_lv_pmos m=1 w=3.000u l=130.00n ++ ng=2 nrd=0 nrs=0 +MA_TSP<3> A_BLT_SEL A_SEL_N<3> A_BLT<3> VDD sg13_lv_pmos m=1 w=1.5u ++ l=130.00n ng=1 nrd=0 nrs=0 +MA_TSP<2> A_BLT_SEL A_SEL_N<2> A_BLT<2> VDD sg13_lv_pmos m=1 w=1.5u ++ l=130.00n ng=1 nrd=0 nrs=0 +MA_TSP<1> A_BLT_SEL A_SEL_N<1> A_BLT<1> VDD sg13_lv_pmos m=1 w=1.5u ++ l=130.00n ng=1 nrd=0 nrs=0 +MA_TSP<0> A_BLT_SEL A_SEL_N<0> A_BLT<0> VDD sg13_lv_pmos m=1 w=1.5u ++ l=130.00n ng=1 nrd=0 nrs=0 +MA_CSP<3> A_BLC_SEL A_SEL_N<3> A_BLC<3> VDD sg13_lv_pmos m=1 w=1.5u ++ l=130.00n ng=1 nrd=0 nrs=0 +MA_CSP<2> A_BLC_SEL A_SEL_N<2> A_BLC<2> VDD sg13_lv_pmos m=1 w=1.5u ++ l=130.00n ng=1 nrd=0 nrs=0 +MA_CSP<1> A_BLC_SEL A_SEL_N<1> A_BLC<1> VDD sg13_lv_pmos m=1 w=1.5u ++ l=130.00n ng=1 nrd=0 nrs=0 +MA_CSP<0> A_BLC_SEL A_SEL_N<0> A_BLC<0> VDD sg13_lv_pmos m=1 w=1.5u ++ l=130.00n ng=1 nrd=0 nrs=0 +MB_CWP<3> B_BLC<3> B_BLC_PMOS_DRIVE<3> VDD VDD sg13_lv_pmos m=1 w=1.5u ++ l=130.00n ng=1 nrd=0 nrs=0 +MB_CWP<2> B_BLC<2> B_BLC_PMOS_DRIVE<2> VDD VDD sg13_lv_pmos m=1 w=1.5u ++ l=130.00n ng=1 nrd=0 nrs=0 +MB_CWP<1> B_BLC<1> B_BLC_PMOS_DRIVE<1> VDD VDD sg13_lv_pmos m=1 w=1.5u ++ l=130.00n ng=1 nrd=0 nrs=0 +MB_CWP<0> B_BLC<0> B_BLC_PMOS_DRIVE<0> VDD VDD sg13_lv_pmos m=1 w=1.5u ++ l=130.00n ng=1 nrd=0 nrs=0 +MB_TWP<3> B_BLT<3> B_BLT_PMOS_DRIVE<3> VDD VDD sg13_lv_pmos m=1 w=1.5u ++ l=130.00n ng=1 nrd=0 nrs=0 +MB_TWP<2> B_BLT<2> B_BLT_PMOS_DRIVE<2> VDD VDD sg13_lv_pmos m=1 w=1.5u ++ l=130.00n ng=1 nrd=0 nrs=0 +MB_TWP<1> B_BLT<1> B_BLT_PMOS_DRIVE<1> VDD VDD sg13_lv_pmos m=1 w=1.5u ++ l=130.00n ng=1 nrd=0 nrs=0 +MB_TWP<0> B_BLT<0> B_BLT_PMOS_DRIVE<0> VDD VDD sg13_lv_pmos m=1 w=1.5u ++ l=130.00n ng=1 nrd=0 nrs=0 +MB_TSP<3> B_BLT_SEL B_SEL_N<3> B_BLT<3> VDD sg13_lv_pmos m=1 w=1.5u ++ l=130.00n ng=1 nrd=0 nrs=0 +MB_TSP<2> B_BLT_SEL B_SEL_N<2> B_BLT<2> VDD sg13_lv_pmos m=1 w=1.5u ++ l=130.00n ng=1 nrd=0 nrs=0 +MB_TSP<1> B_BLT_SEL B_SEL_N<1> B_BLT<1> VDD sg13_lv_pmos m=1 w=1.5u ++ l=130.00n ng=1 nrd=0 nrs=0 +MB_TSP<0> B_BLT_SEL B_SEL_N<0> B_BLT<0> VDD sg13_lv_pmos m=1 w=1.5u ++ l=130.00n ng=1 nrd=0 nrs=0 +MB_TPR<3> B_BLT<3> B_PRE_N VDD VDD sg13_lv_pmos m=1 w=3.000u l=130.00n ++ ng=2 nrd=0 nrs=0 +MB_TPR<2> B_BLT<2> B_PRE_N VDD VDD sg13_lv_pmos m=1 w=3.000u l=130.00n ++ ng=2 nrd=0 nrs=0 +MB_TPR<1> B_BLT<1> B_PRE_N VDD VDD sg13_lv_pmos m=1 w=3.000u l=130.00n ++ ng=2 nrd=0 nrs=0 +MB_TPR<0> B_BLT<0> B_PRE_N VDD VDD sg13_lv_pmos m=1 w=3.000u l=130.00n ++ ng=2 nrd=0 nrs=0 +MB_CSP<3> B_BLC_SEL B_SEL_N<3> B_BLC<3> VDD sg13_lv_pmos m=1 w=1.5u ++ l=130.00n ng=1 nrd=0 nrs=0 +MB_CSP<2> B_BLC_SEL B_SEL_N<2> B_BLC<2> VDD sg13_lv_pmos m=1 w=1.5u ++ l=130.00n ng=1 nrd=0 nrs=0 +MB_CSP<1> B_BLC_SEL B_SEL_N<1> B_BLC<1> VDD sg13_lv_pmos m=1 w=1.5u ++ l=130.00n ng=1 nrd=0 nrs=0 +MB_CSP<0> B_BLC_SEL B_SEL_N<0> B_BLC<0> VDD sg13_lv_pmos m=1 w=1.5u ++ l=130.00n ng=1 nrd=0 nrs=0 +MB_CPR<3> B_BLC<3> B_PRE_N VDD VDD sg13_lv_pmos m=1 w=3.000u l=130.00n ++ ng=2 nrd=0 nrs=0 +MB_CPR<2> B_BLC<2> B_PRE_N VDD VDD sg13_lv_pmos m=1 w=3.000u l=130.00n ++ ng=2 nrd=0 nrs=0 +MB_CPR<1> B_BLC<1> B_PRE_N VDD VDD sg13_lv_pmos m=1 w=3.000u l=130.00n ++ ng=2 nrd=0 nrs=0 +MB_CPR<0> B_BLC<0> B_PRE_N VDD VDD sg13_lv_pmos m=1 w=3.000u l=130.00n ++ ng=2 nrd=0 nrs=0 +XA_SEL<3> A_SEL_P<3> A_SEL_N<3> VDD VSS / RSC_IHPSG13_INVX2 +XA_SEL<2> A_SEL_P<2> A_SEL_N<2> VDD VSS / RSC_IHPSG13_INVX2 +XA_SEL<1> A_SEL_P<1> A_SEL_N<1> VDD VSS / RSC_IHPSG13_INVX2 +XA_SEL<0> A_SEL_P<0> A_SEL_N<0> VDD VSS / RSC_IHPSG13_INVX2 +XA_CINV<3> A_BLT_PMOS_DRIVE<3> A_BLC_NMOS_DRIVE<3> VDD VSS / ++ RSC_IHPSG13_INVX2 +XA_CINV<2> A_BLT_PMOS_DRIVE<2> A_BLC_NMOS_DRIVE<2> VDD VSS / ++ RSC_IHPSG13_INVX2 +XA_CINV<1> A_BLT_PMOS_DRIVE<1> A_BLC_NMOS_DRIVE<1> VDD VSS / ++ RSC_IHPSG13_INVX2 +XA_CINV<0> A_BLT_PMOS_DRIVE<0> A_BLC_NMOS_DRIVE<0> VDD VSS / ++ RSC_IHPSG13_INVX2 +XA_TINV<3> A_BLC_PMOS_DRIVE<3> A_BLT_NMOS_DRIVE<3> VDD VSS / ++ RSC_IHPSG13_INVX2 +XA_TINV<2> A_BLC_PMOS_DRIVE<2> A_BLT_NMOS_DRIVE<2> VDD VSS / ++ RSC_IHPSG13_INVX2 +XA_TINV<1> A_BLC_PMOS_DRIVE<1> A_BLT_NMOS_DRIVE<1> VDD VSS / ++ RSC_IHPSG13_INVX2 +XA_TINV<0> A_BLC_PMOS_DRIVE<0> A_BLT_NMOS_DRIVE<0> VDD VSS / ++ RSC_IHPSG13_INVX2 +XB_SEL<3> B_SEL_P<3> B_SEL_N<3> VDD VSS / RSC_IHPSG13_INVX2 +XB_SEL<2> B_SEL_P<2> B_SEL_N<2> VDD VSS / RSC_IHPSG13_INVX2 +XB_SEL<1> B_SEL_P<1> B_SEL_N<1> VDD VSS / RSC_IHPSG13_INVX2 +XB_SEL<0> B_SEL_P<0> B_SEL_N<0> VDD VSS / RSC_IHPSG13_INVX2 +XB_TINV<3> B_BLC_PMOS_DRIVE<3> B_BLT_NMOS_DRIVE<3> VDD VSS / ++ RSC_IHPSG13_INVX2 +XB_TINV<2> B_BLC_PMOS_DRIVE<2> B_BLT_NMOS_DRIVE<2> VDD VSS / ++ RSC_IHPSG13_INVX2 +XB_TINV<1> B_BLC_PMOS_DRIVE<1> B_BLT_NMOS_DRIVE<1> VDD VSS / ++ RSC_IHPSG13_INVX2 +XB_TINV<0> B_BLC_PMOS_DRIVE<0> B_BLT_NMOS_DRIVE<0> VDD VSS / ++ RSC_IHPSG13_INVX2 +XB_CINV<3> B_BLT_PMOS_DRIVE<3> B_BLC_NMOS_DRIVE<3> VDD VSS / ++ RSC_IHPSG13_INVX2 +XB_CINV<2> B_BLT_PMOS_DRIVE<2> B_BLC_NMOS_DRIVE<2> VDD VSS / ++ RSC_IHPSG13_INVX2 +XB_CINV<1> B_BLT_PMOS_DRIVE<1> B_BLC_NMOS_DRIVE<1> VDD VSS / ++ RSC_IHPSG13_INVX2 +XB_CINV<0> B_BLT_PMOS_DRIVE<0> B_BLC_NMOS_DRIVE<0> VDD VSS / ++ RSC_IHPSG13_INVX2 +XA_TDEC<3> A_SEL_P<3> A_WR_ONE A_BLT_PMOS_DRIVE<3> VDD VSS / ++ RSC_IHPSG13_NAND2X2 +XA_TDEC<2> A_SEL_P<2> A_WR_ONE A_BLT_PMOS_DRIVE<2> VDD VSS / ++ RSC_IHPSG13_NAND2X2 +XA_TDEC<1> A_SEL_P<1> A_WR_ONE A_BLT_PMOS_DRIVE<1> VDD VSS / ++ RSC_IHPSG13_NAND2X2 +XA_TDEC<0> A_SEL_P<0> A_WR_ONE A_BLT_PMOS_DRIVE<0> VDD VSS / ++ RSC_IHPSG13_NAND2X2 +XA_CDEC<3> A_SEL_P<3> A_WR_ZERO A_BLC_PMOS_DRIVE<3> VDD VSS / ++ RSC_IHPSG13_NAND2X2 +XA_CDEC<2> A_SEL_P<2> A_WR_ZERO A_BLC_PMOS_DRIVE<2> VDD VSS / ++ RSC_IHPSG13_NAND2X2 +XA_CDEC<1> A_SEL_P<1> A_WR_ZERO A_BLC_PMOS_DRIVE<1> VDD VSS / ++ RSC_IHPSG13_NAND2X2 +XA_CDEC<0> A_SEL_P<0> A_WR_ZERO A_BLC_PMOS_DRIVE<0> VDD VSS / ++ RSC_IHPSG13_NAND2X2 +XB_CDEC<3> B_SEL_P<3> B_WR_ZERO B_BLC_PMOS_DRIVE<3> VDD VSS / ++ RSC_IHPSG13_NAND2X2 +XB_CDEC<2> B_SEL_P<2> B_WR_ZERO B_BLC_PMOS_DRIVE<2> VDD VSS / ++ RSC_IHPSG13_NAND2X2 +XB_CDEC<1> B_SEL_P<1> B_WR_ZERO B_BLC_PMOS_DRIVE<1> VDD VSS / ++ RSC_IHPSG13_NAND2X2 +XB_CDEC<0> B_SEL_P<0> B_WR_ZERO B_BLC_PMOS_DRIVE<0> VDD VSS / ++ RSC_IHPSG13_NAND2X2 +XB_TDEC<3> B_SEL_P<3> B_WR_ONE B_BLT_PMOS_DRIVE<3> VDD VSS / ++ RSC_IHPSG13_NAND2X2 +XB_TDEC<2> B_SEL_P<2> B_WR_ONE B_BLT_PMOS_DRIVE<2> VDD VSS / ++ RSC_IHPSG13_NAND2X2 +XB_TDEC<1> B_SEL_P<1> B_WR_ONE B_BLT_PMOS_DRIVE<1> VDD VSS / ++ RSC_IHPSG13_NAND2X2 +XB_TDEC<0> B_SEL_P<0> B_WR_ONE B_BLT_PMOS_DRIVE<0> VDD VSS / ++ RSC_IHPSG13_NAND2X2 +.ENDS +.SUBCKT RSC_IHPSG13_AND2X6 A B Z VDD VSS +MN3 Z net6 VSS VSS sg13_lv_nmos m=1 w=2.94u l=130.00n ng=3 nrd=0 nrs=0 +MN4 net9 B VSS VSS sg13_lv_nmos m=1 w=500.0n l=130.00n ng=1 nrd=0 nrs=0 +MN6 net6 A net9 VSS sg13_lv_nmos m=1 w=500.0n l=130.00n ng=1 nrd=0 nrs=0 +MP2 Z net6 VDD VDD sg13_lv_pmos m=1 w=4.86u l=130.00n ng=3 nrd=0 nrs=0 +MP0 net6 B VDD VDD sg13_lv_pmos m=1 w=860.00n l=130.00n ng=1 nrd=0 ++ nrs=0 +MP1 net6 A VDD VDD sg13_lv_pmos m=1 w=860.00n l=130.00n ng=1 nrd=0 ++ nrs=0 +.ENDS +.SUBCKT RM_IHPSG13_512x16_c2_2P_COLCTRL5 A_ADDR_COL<1> A_ADDR_COL<0> A_ADDR_DEC<7> ++ A_ADDR_DEC<6> A_ADDR_DEC<5> A_ADDR_DEC<4> A_ADDR_DEC<3> A_ADDR_DEC<2> ++ A_ADDR_DEC<1> A_ADDR_DEC<0> A_BIST_BM_I A_BIST_DW_I A_BIST_EN_I A_BLC<31> ++ A_BLC<30> A_BLC<29> A_BLC<28> A_BLC<27> A_BLC<26> A_BLC<25> A_BLC<24> ++ A_BLC<23> A_BLC<22> A_BLC<21> A_BLC<20> A_BLC<19> A_BLC<18> A_BLC<17> ++ A_BLC<16> A_BLC<15> A_BLC<14> A_BLC<13> A_BLC<12> A_BLC<11> A_BLC<10> ++ A_BLC<9> A_BLC<8> A_BLC<7> A_BLC<6> A_BLC<5> A_BLC<4> A_BLC<3> A_BLC<2> ++ A_BLC<1> A_BLC<0> A_BLT<31> A_BLT<30> A_BLT<29> A_BLT<28> A_BLT<27> ++ A_BLT<26> A_BLT<25> A_BLT<24> A_BLT<23> A_BLT<22> A_BLT<21> A_BLT<20> ++ A_BLT<19> A_BLT<18> A_BLT<17> A_BLT<16> A_BLT<15> A_BLT<14> A_BLT<13> ++ A_BLT<12> A_BLT<11> A_BLT<10> A_BLT<9> A_BLT<8> A_BLT<7> A_BLT<6> A_BLT<5> ++ A_BLT<4> A_BLT<3> A_BLT<2> A_BLT<1> A_BLT<0> A_BM_I A_DCLK_B_L A_DCLK_B_R ++ A_DCLK_L A_DCLK_R A_DR_O A_DW_I A_RCLK_B_L A_RCLK_B_R A_RCLK_L A_RCLK_R ++ A_TIEH_O A_WCLK_B_L A_WCLK_B_R A_WCLK_L A_WCLK_R B_ADDR_COL<1> B_ADDR_COL<0> ++ B_ADDR_DEC<7> B_ADDR_DEC<6> B_ADDR_DEC<5> B_ADDR_DEC<4> B_ADDR_DEC<3> ++ B_ADDR_DEC<2> B_ADDR_DEC<1> B_ADDR_DEC<0> B_BIST_BM_I B_BIST_DW_I ++ B_BIST_EN_I B_BLC<31> B_BLC<30> B_BLC<29> B_BLC<28> B_BLC<27> B_BLC<26> ++ B_BLC<25> B_BLC<24> B_BLC<23> B_BLC<22> B_BLC<21> B_BLC<20> B_BLC<19> ++ B_BLC<18> B_BLC<17> B_BLC<16> B_BLC<15> B_BLC<14> B_BLC<13> B_BLC<12> ++ B_BLC<11> B_BLC<10> B_BLC<9> B_BLC<8> B_BLC<7> B_BLC<6> B_BLC<5> B_BLC<4> ++ B_BLC<3> B_BLC<2> B_BLC<1> B_BLC<0> B_BLT<31> B_BLT<30> B_BLT<29> B_BLT<28> ++ B_BLT<27> B_BLT<26> B_BLT<25> B_BLT<24> B_BLT<23> B_BLT<22> B_BLT<21> ++ B_BLT<20> B_BLT<19> B_BLT<18> B_BLT<17> B_BLT<16> B_BLT<15> B_BLT<14> ++ B_BLT<13> B_BLT<12> B_BLT<11> B_BLT<10> B_BLT<9> B_BLT<8> B_BLT<7> B_BLT<6> ++ B_BLT<5> B_BLT<4> B_BLT<3> B_BLT<2> B_BLT<1> B_BLT<0> B_BM_I B_DCLK_B_L ++ B_DCLK_B_R B_DCLK_L B_DCLK_R B_DR_O B_DW_I B_RCLK_B_L B_RCLK_B_R B_RCLK_L ++ B_RCLK_R B_TIEH_O B_WCLK_B_L B_WCLK_B_R B_WCLK_L B_WCLK_R VDD VSS +XB_I80<1> B_WCLK_B_L B_RCLK_B_L B_W_nor_R<1> VDD VSS / ++ RSC_IHPSG13_AND2X2 +XB_I80<0> B_WCLK_B_L B_RCLK_B_L B_W_nor_R<0> VDD VSS / ++ RSC_IHPSG13_AND2X2 +XA_I80<1> A_WCLK_B_L A_RCLK_B_L A_W_nor_R<1> VDD VSS / ++ RSC_IHPSG13_AND2X2 +XA_I80<0> A_WCLK_B_L A_RCLK_B_L A_W_nor_R<0> VDD VSS / ++ RSC_IHPSG13_AND2X2 +XB_I44 B_BM_N B_WCLK_B_L B_DO_WRITE_P VDD VSS / RSC_IHPSG13_NOR2X2 +XA_I44 A_BM_N A_WCLK_B_L A_DO_WRITE_P VDD VSS / RSC_IHPSG13_NOR2X2 +XI_FILL4<16> VDD VSS / RSC_IHPSG13_FILLCAP4 +XI_FILL4<15> VDD VSS / RSC_IHPSG13_FILLCAP4 +XI_FILL4<14> VDD VSS / RSC_IHPSG13_FILLCAP4 +XI_FILL4<13> VDD VSS / RSC_IHPSG13_FILLCAP4 +XI_FILL4<12> VDD VSS / RSC_IHPSG13_FILLCAP4 +XI_FILL4<11> VDD VSS / RSC_IHPSG13_FILLCAP4 +XI_FILL4<10> VDD VSS / RSC_IHPSG13_FILLCAP4 +XI_FILL4<9> VDD VSS / RSC_IHPSG13_FILLCAP4 +XI_FILL4<8> VDD VSS / RSC_IHPSG13_FILLCAP4 +XI_FILL4<7> VDD VSS / RSC_IHPSG13_FILLCAP4 +XI_FILL4<6> VDD VSS / RSC_IHPSG13_FILLCAP4 +XI_FILL4<5> VDD VSS / RSC_IHPSG13_FILLCAP4 +XI_FILL4<4> VDD VSS / RSC_IHPSG13_FILLCAP4 +XI_FILL4<3> VDD VSS / RSC_IHPSG13_FILLCAP4 +XI_FILL4<2> VDD VSS / RSC_IHPSG13_FILLCAP4 +XI_FILL4<1> VDD VSS / RSC_IHPSG13_FILLCAP4 +XB_INV<6> B_N1<1> B_P1<1> VDD VSS / RSC_IHPSG13_CINVX4 +XB_INV<5> B_N0<1> B_P0<1> VDD VSS / RSC_IHPSG13_CINVX4 +XB_INV<4> B_N0<0> B_P0<0> VDD VSS / RSC_IHPSG13_CINVX4 +XB_INV<3> B_ADDR_COL<1> B_N1<1> VDD VSS / RSC_IHPSG13_CINVX4 +XB_INV<2> B_ADDR_COL<1> B_N1<0> VDD VSS / RSC_IHPSG13_CINVX4 +XB_INV<1> B_ADDR_COL<0> B_N0<1> VDD VSS / RSC_IHPSG13_CINVX4 +XB_INV<0> B_ADDR_COL<0> B_N0<0> VDD VSS / RSC_IHPSG13_CINVX4 +XA_INV<6> A_N1<1> A_P1<1> VDD VSS / RSC_IHPSG13_CINVX4 +XA_INV<5> A_N0<1> A_P0<1> VDD VSS / RSC_IHPSG13_CINVX4 +XA_INV<4> A_N0<0> A_P0<0> VDD VSS / RSC_IHPSG13_CINVX4 +XA_INV<3> A_ADDR_COL<1> A_N1<1> VDD VSS / RSC_IHPSG13_CINVX4 +XA_INV<2> A_ADDR_COL<1> A_N1<0> VDD VSS / RSC_IHPSG13_CINVX4 +XA_INV<1> A_ADDR_COL<0> A_N0<1> VDD VSS / RSC_IHPSG13_CINVX4 +XA_INV<0> A_ADDR_COL<0> A_N0<0> VDD VSS / RSC_IHPSG13_CINVX4 +XB_I81<3> B_W_nor_R<1> B_PRE_N VDD VSS / RSC_IHPSG13_CINVX4_WN +XB_I81<2> B_W_nor_R<1> B_PRE_N VDD VSS / RSC_IHPSG13_CINVX4_WN +XB_I81<1> B_W_nor_R<0> B_PRE_N VDD VSS / RSC_IHPSG13_CINVX4_WN +XB_I81<0> B_W_nor_R<0> B_PRE_N VDD VSS / RSC_IHPSG13_CINVX4_WN +XA_I81<3> A_W_nor_R<1> A_PRE_N VDD VSS / RSC_IHPSG13_CINVX4_WN +XA_I81<2> A_W_nor_R<1> A_PRE_N VDD VSS / RSC_IHPSG13_CINVX4_WN +XA_I81<1> A_W_nor_R<0> A_PRE_N VDD VSS / RSC_IHPSG13_CINVX4_WN +XA_I81<0> A_W_nor_R<0> A_PRE_N VDD VSS / RSC_IHPSG13_CINVX4_WN +XI_FILL8<78> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI_FILL8<77> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI_FILL8<76> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI_FILL8<75> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI_FILL8<74> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI_FILL8<73> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI_FILL8<72> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI_FILL8<71> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI_FILL8<70> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI_FILL8<69> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI_FILL8<68> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI_FILL8<67> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI_FILL8<66> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI_FILL8<65> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI_FILL8<64> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI_FILL8<63> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI_FILL8<62> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI_FILL8<61> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI_FILL8<60> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI_FILL8<59> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI_FILL8<58> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI_FILL8<57> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI_FILL8<56> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI_FILL8<55> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI_FILL8<54> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI_FILL8<53> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI_FILL8<52> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI_FILL8<51> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI_FILL8<50> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI_FILL8<49> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI_FILL8<48> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI_FILL8<47> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI_FILL8<46> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI_FILL8<45> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI_FILL8<44> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI_FILL8<43> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI_FILL8<42> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI_FILL8<41> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI_FILL8<40> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI_FILL8<39> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI_FILL8<38> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI_FILL8<37> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI_FILL8<36> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI_FILL8<35> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI_FILL8<34> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI_FILL8<33> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI_FILL8<32> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI_FILL8<31> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI_FILL8<30> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI_FILL8<29> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI_FILL8<28> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI_FILL8<27> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI_FILL8<26> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI_FILL8<25> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI_FILL8<24> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI_FILL8<23> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI_FILL8<22> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI_FILL8<21> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI_FILL8<20> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI_FILL8<19> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI_FILL8<18> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI_FILL8<17> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI_FILL8<16> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI_FILL8<15> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI_FILL8<14> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI_FILL8<13> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI_FILL8<12> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI_FILL8<11> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI_FILL8<10> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI_FILL8<9> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI_FILL8<8> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI_FILL8<7> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI_FILL8<6> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI_FILL8<5> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI_FILL8<4> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI_FILL8<3> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI_FILL8<2> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI_FILL8<1> VDD VSS / RSC_IHPSG13_FILLCAP8 +XAB_BLMUX<7> A_BLC<31> A_BLC<30> A_BLC<29> A_BLC<28> A_BLC_SEL A_BLT<31> ++ A_BLT<30> A_BLT<29> A_BLT<28> A_BLT_SEL A_PRE_N A_SEL_P<31> A_SEL_P<30> ++ A_SEL_P<29> A_SEL_P<28> A_WR_ONE A_WR_ZERO B_BLC<31> B_BLC<30> B_BLC<29> ++ B_BLC<28> B_BLC_SEL B_BLT<31> B_BLT<30> B_BLT<29> B_BLT<28> B_BLT_SEL ++ B_PRE_N B_SEL_P<31> B_SEL_P<30> B_SEL_P<29> B_SEL_P<28> B_WR_ONE B_WR_ZERO ++ VDD VSS / RM_IHPSG13_512x16_c2_2P_BLDRV +XAB_BLMUX<6> A_BLC<27> A_BLC<26> A_BLC<25> A_BLC<24> A_BLC_SEL A_BLT<27> ++ A_BLT<26> A_BLT<25> A_BLT<24> A_BLT_SEL A_PRE_N A_SEL_P<27> A_SEL_P<26> ++ A_SEL_P<25> A_SEL_P<24> A_WR_ONE A_WR_ZERO B_BLC<27> B_BLC<26> B_BLC<25> ++ B_BLC<24> B_BLC_SEL B_BLT<27> B_BLT<26> B_BLT<25> B_BLT<24> B_BLT_SEL ++ B_PRE_N B_SEL_P<27> B_SEL_P<26> B_SEL_P<25> B_SEL_P<24> B_WR_ONE B_WR_ZERO ++ VDD VSS / RM_IHPSG13_512x16_c2_2P_BLDRV +XAB_BLMUX<5> A_BLC<23> A_BLC<22> A_BLC<21> A_BLC<20> A_BLC_SEL A_BLT<23> ++ A_BLT<22> A_BLT<21> A_BLT<20> A_BLT_SEL A_PRE_N A_SEL_P<23> A_SEL_P<22> ++ A_SEL_P<21> A_SEL_P<20> A_WR_ONE A_WR_ZERO B_BLC<23> B_BLC<22> B_BLC<21> ++ B_BLC<20> B_BLC_SEL B_BLT<23> B_BLT<22> B_BLT<21> B_BLT<20> B_BLT_SEL ++ B_PRE_N B_SEL_P<23> B_SEL_P<22> B_SEL_P<21> B_SEL_P<20> B_WR_ONE B_WR_ZERO ++ VDD VSS / RM_IHPSG13_512x16_c2_2P_BLDRV +XAB_BLMUX<4> A_BLC<19> A_BLC<18> A_BLC<17> A_BLC<16> A_BLC_SEL A_BLT<19> ++ A_BLT<18> A_BLT<17> A_BLT<16> A_BLT_SEL A_PRE_N A_SEL_P<19> A_SEL_P<18> ++ A_SEL_P<17> A_SEL_P<16> A_WR_ONE A_WR_ZERO B_BLC<19> B_BLC<18> B_BLC<17> ++ B_BLC<16> B_BLC_SEL B_BLT<19> B_BLT<18> B_BLT<17> B_BLT<16> B_BLT_SEL ++ B_PRE_N B_SEL_P<19> B_SEL_P<18> B_SEL_P<17> B_SEL_P<16> B_WR_ONE B_WR_ZERO ++ VDD VSS / RM_IHPSG13_512x16_c2_2P_BLDRV +XAB_BLMUX<3> A_BLC<15> A_BLC<14> A_BLC<13> A_BLC<12> A_BLC_SEL A_BLT<15> ++ A_BLT<14> A_BLT<13> A_BLT<12> A_BLT_SEL A_PRE_N A_SEL_P<15> A_SEL_P<14> ++ A_SEL_P<13> A_SEL_P<12> A_WR_ONE A_WR_ZERO B_BLC<15> B_BLC<14> B_BLC<13> ++ B_BLC<12> B_BLC_SEL B_BLT<15> B_BLT<14> B_BLT<13> B_BLT<12> B_BLT_SEL ++ B_PRE_N B_SEL_P<15> B_SEL_P<14> B_SEL_P<13> B_SEL_P<12> B_WR_ONE B_WR_ZERO ++ VDD VSS / RM_IHPSG13_512x16_c2_2P_BLDRV +XAB_BLMUX<2> A_BLC<11> A_BLC<10> A_BLC<9> A_BLC<8> A_BLC_SEL A_BLT<11> ++ A_BLT<10> A_BLT<9> A_BLT<8> A_BLT_SEL A_PRE_N A_SEL_P<11> A_SEL_P<10> ++ A_SEL_P<9> A_SEL_P<8> A_WR_ONE A_WR_ZERO B_BLC<11> B_BLC<10> B_BLC<9> ++ B_BLC<8> B_BLC_SEL B_BLT<11> B_BLT<10> B_BLT<9> B_BLT<8> B_BLT_SEL B_PRE_N ++ B_SEL_P<11> B_SEL_P<10> B_SEL_P<9> B_SEL_P<8> B_WR_ONE B_WR_ZERO VDD ++ VSS / RM_IHPSG13_512x16_c2_2P_BLDRV +XAB_BLMUX<1> A_BLC<7> A_BLC<6> A_BLC<5> A_BLC<4> A_BLC_SEL A_BLT<7> A_BLT<6> ++ A_BLT<5> A_BLT<4> A_BLT_SEL A_PRE_N A_SEL_P<7> A_SEL_P<6> A_SEL_P<5> ++ A_SEL_P<4> A_WR_ONE A_WR_ZERO B_BLC<7> B_BLC<6> B_BLC<5> B_BLC<4> B_BLC_SEL ++ B_BLT<7> B_BLT<6> B_BLT<5> B_BLT<4> B_BLT_SEL B_PRE_N B_SEL_P<7> B_SEL_P<6> ++ B_SEL_P<5> B_SEL_P<4> B_WR_ONE B_WR_ZERO VDD VSS / ++ RM_IHPSG13_512x16_c2_2P_BLDRV +XAB_BLMUX<0> A_BLC<3> A_BLC<2> A_BLC<1> A_BLC<0> A_BLC_SEL A_BLT<3> A_BLT<2> ++ A_BLT<1> A_BLT<0> A_BLT_SEL A_PRE_N A_SEL_P<3> A_SEL_P<2> A_SEL_P<1> ++ A_SEL_P<0> A_WR_ONE A_WR_ZERO B_BLC<3> B_BLC<2> B_BLC<1> B_BLC<0> B_BLC_SEL ++ B_BLT<3> B_BLT<2> B_BLT<1> B_BLT<0> B_BLT_SEL B_PRE_N B_SEL_P<3> B_SEL_P<2> ++ B_SEL_P<1> B_SEL_P<0> B_WR_ONE B_WR_ZERO VDD VSS / ++ RM_IHPSG13_512x16_c2_2P_BLDRV +XB_I51 net037 B_DR_O VDD VSS / RSC_IHPSG13_INVX4 +XA_I51 net19 A_DR_O VDD VSS / RSC_IHPSG13_INVX4 +XB_I78 B_RCLK_B_L B_SAE VDD VSS / RSC_IHPSG13_CBUFX2 +XA_I78 A_RCLK_B_L A_SAE VDD VSS / RSC_IHPSG13_CBUFX2 +XB_I69 B_DCLK_L B_DCLK_B_L VDD VSS / RSC_IHPSG13_CINVX8 +XB_I50 B_WCLK_L B_WCLK_B_L VDD VSS / RSC_IHPSG13_CINVX8 +XB_EBUF B_RCLK_L B_RCLK_B_L VDD VSS / RSC_IHPSG13_CINVX8 +XA_I69 A_DCLK_L A_DCLK_B_L VDD VSS / RSC_IHPSG13_CINVX8 +XA_I50 A_WCLK_L A_WCLK_B_L VDD VSS / RSC_IHPSG13_CINVX8 +XA_EBUF A_RCLK_L A_RCLK_B_L VDD VSS / RSC_IHPSG13_CINVX8 +XB_I76 B_DI_N B_DO_WRITE_P B_WR_ZERO VDD VSS / RSC_IHPSG13_AND2X6 +XB_I75 B_DI_R B_DO_WRITE_P B_WR_ONE VDD VSS / RSC_IHPSG13_AND2X6 +XA_I76 A_DI_N A_DO_WRITE_P A_WR_ZERO VDD VSS / RSC_IHPSG13_AND2X6 +XA_I75 A_DI_R A_DO_WRITE_P A_WR_ONE VDD VSS / RSC_IHPSG13_AND2X6 +XB_I83 B_BM_R B_BM_N VDD VSS / RSC_IHPSG13_INVX2 +XB_DEC3INV<31> net041<0> B_SEL_P<31> VDD VSS / RSC_IHPSG13_INVX2 +XB_DEC3INV<30> net041<1> B_SEL_P<30> VDD VSS / RSC_IHPSG13_INVX2 +XB_DEC3INV<29> net041<2> B_SEL_P<29> VDD VSS / RSC_IHPSG13_INVX2 +XB_DEC3INV<28> net041<3> B_SEL_P<28> VDD VSS / RSC_IHPSG13_INVX2 +XB_DEC3INV<27> net041<4> B_SEL_P<27> VDD VSS / RSC_IHPSG13_INVX2 +XB_DEC3INV<26> net041<5> B_SEL_P<26> VDD VSS / RSC_IHPSG13_INVX2 +XB_DEC3INV<25> net041<6> B_SEL_P<25> VDD VSS / RSC_IHPSG13_INVX2 +XB_DEC3INV<24> net041<7> B_SEL_P<24> VDD VSS / RSC_IHPSG13_INVX2 +XB_DEC3INV<23> net041<8> B_SEL_P<23> VDD VSS / RSC_IHPSG13_INVX2 +XB_DEC3INV<22> net041<9> B_SEL_P<22> VDD VSS / RSC_IHPSG13_INVX2 +XB_DEC3INV<21> net041<10> B_SEL_P<21> VDD VSS / RSC_IHPSG13_INVX2 +XB_DEC3INV<20> net041<11> B_SEL_P<20> VDD VSS / RSC_IHPSG13_INVX2 +XB_DEC3INV<19> net041<12> B_SEL_P<19> VDD VSS / RSC_IHPSG13_INVX2 +XB_DEC3INV<18> net041<13> B_SEL_P<18> VDD VSS / RSC_IHPSG13_INVX2 +XB_DEC3INV<17> net041<14> B_SEL_P<17> VDD VSS / RSC_IHPSG13_INVX2 +XB_DEC3INV<16> net041<15> B_SEL_P<16> VDD VSS / RSC_IHPSG13_INVX2 +XB_DEC3INV<15> net041<16> B_SEL_P<15> VDD VSS / RSC_IHPSG13_INVX2 +XB_DEC3INV<14> net041<17> B_SEL_P<14> VDD VSS / RSC_IHPSG13_INVX2 +XB_DEC3INV<13> net041<18> B_SEL_P<13> VDD VSS / RSC_IHPSG13_INVX2 +XB_DEC3INV<12> net041<19> B_SEL_P<12> VDD VSS / RSC_IHPSG13_INVX2 +XB_DEC3INV<11> net041<20> B_SEL_P<11> VDD VSS / RSC_IHPSG13_INVX2 +XB_DEC3INV<10> net041<21> B_SEL_P<10> VDD VSS / RSC_IHPSG13_INVX2 +XB_DEC3INV<9> net041<22> B_SEL_P<9> VDD VSS / RSC_IHPSG13_INVX2 +XB_DEC3INV<8> net041<23> B_SEL_P<8> VDD VSS / RSC_IHPSG13_INVX2 +XB_DEC3INV<7> net041<24> B_SEL_P<7> VDD VSS / RSC_IHPSG13_INVX2 +XB_DEC3INV<6> net041<25> B_SEL_P<6> VDD VSS / RSC_IHPSG13_INVX2 +XB_DEC3INV<5> net041<26> B_SEL_P<5> VDD VSS / RSC_IHPSG13_INVX2 +XB_DEC3INV<4> net041<27> B_SEL_P<4> VDD VSS / RSC_IHPSG13_INVX2 +XB_DEC3INV<3> net041<28> B_SEL_P<3> VDD VSS / RSC_IHPSG13_INVX2 +XB_DEC3INV<2> net041<29> B_SEL_P<2> VDD VSS / RSC_IHPSG13_INVX2 +XB_DEC3INV<1> net041<30> B_SEL_P<1> VDD VSS / RSC_IHPSG13_INVX2 +XB_DEC3INV<0> net041<31> B_SEL_P<0> VDD VSS / RSC_IHPSG13_INVX2 +XB_I49 B_DI_R B_DI_N VDD VSS / RSC_IHPSG13_INVX2 +XA_I83 A_BM_R A_BM_N VDD VSS / RSC_IHPSG13_INVX2 +XA_DEC3INV<31> net23<0> A_SEL_P<31> VDD VSS / RSC_IHPSG13_INVX2 +XA_DEC3INV<30> net23<1> A_SEL_P<30> VDD VSS / RSC_IHPSG13_INVX2 +XA_DEC3INV<29> net23<2> A_SEL_P<29> VDD VSS / RSC_IHPSG13_INVX2 +XA_DEC3INV<28> net23<3> A_SEL_P<28> VDD VSS / RSC_IHPSG13_INVX2 +XA_DEC3INV<27> net23<4> A_SEL_P<27> VDD VSS / RSC_IHPSG13_INVX2 +XA_DEC3INV<26> net23<5> A_SEL_P<26> VDD VSS / RSC_IHPSG13_INVX2 +XA_DEC3INV<25> net23<6> A_SEL_P<25> VDD VSS / RSC_IHPSG13_INVX2 +XA_DEC3INV<24> net23<7> A_SEL_P<24> VDD VSS / RSC_IHPSG13_INVX2 +XA_DEC3INV<23> net23<8> A_SEL_P<23> VDD VSS / RSC_IHPSG13_INVX2 +XA_DEC3INV<22> net23<9> A_SEL_P<22> VDD VSS / RSC_IHPSG13_INVX2 +XA_DEC3INV<21> net23<10> A_SEL_P<21> VDD VSS / RSC_IHPSG13_INVX2 +XA_DEC3INV<20> net23<11> A_SEL_P<20> VDD VSS / RSC_IHPSG13_INVX2 +XA_DEC3INV<19> net23<12> A_SEL_P<19> VDD VSS / RSC_IHPSG13_INVX2 +XA_DEC3INV<18> net23<13> A_SEL_P<18> VDD VSS / RSC_IHPSG13_INVX2 +XA_DEC3INV<17> net23<14> A_SEL_P<17> VDD VSS / RSC_IHPSG13_INVX2 +XA_DEC3INV<16> net23<15> A_SEL_P<16> VDD VSS / RSC_IHPSG13_INVX2 +XA_DEC3INV<15> net23<16> A_SEL_P<15> VDD VSS / RSC_IHPSG13_INVX2 +XA_DEC3INV<14> net23<17> A_SEL_P<14> VDD VSS / RSC_IHPSG13_INVX2 +XA_DEC3INV<13> net23<18> A_SEL_P<13> VDD VSS / RSC_IHPSG13_INVX2 +XA_DEC3INV<12> net23<19> A_SEL_P<12> VDD VSS / RSC_IHPSG13_INVX2 +XA_DEC3INV<11> net23<20> A_SEL_P<11> VDD VSS / RSC_IHPSG13_INVX2 +XA_DEC3INV<10> net23<21> A_SEL_P<10> VDD VSS / RSC_IHPSG13_INVX2 +XA_DEC3INV<9> net23<22> A_SEL_P<9> VDD VSS / RSC_IHPSG13_INVX2 +XA_DEC3INV<8> net23<23> A_SEL_P<8> VDD VSS / RSC_IHPSG13_INVX2 +XA_DEC3INV<7> net23<24> A_SEL_P<7> VDD VSS / RSC_IHPSG13_INVX2 +XA_DEC3INV<6> net23<25> A_SEL_P<6> VDD VSS / RSC_IHPSG13_INVX2 +XA_DEC3INV<5> net23<26> A_SEL_P<5> VDD VSS / RSC_IHPSG13_INVX2 +XA_DEC3INV<4> net23<27> A_SEL_P<4> VDD VSS / RSC_IHPSG13_INVX2 +XA_DEC3INV<3> net23<28> A_SEL_P<3> VDD VSS / RSC_IHPSG13_INVX2 +XA_DEC3INV<2> net23<29> A_SEL_P<2> VDD VSS / RSC_IHPSG13_INVX2 +XA_DEC3INV<1> net23<30> A_SEL_P<1> VDD VSS / RSC_IHPSG13_INVX2 +XA_DEC3INV<0> net23<31> A_SEL_P<0> VDD VSS / RSC_IHPSG13_INVX2 +XA_I49 A_DI_R A_DI_N VDD VSS / RSC_IHPSG13_INVX2 +XB_ISENSE B_SAE B_BLC_SEL B_BLT_SEL net037 net038 VDD VSS / ++ RSC_IHPSG13_DFPQD_MSAFFX2 +XA_ISENSE A_SAE A_BLC_SEL A_BLT_SEL net19 net20 VDD VSS / ++ RSC_IHPSG13_DFPQD_MSAFFX2 +XB_DREG B_BIST_EN_I B_BIST_DW_I B_DCLK_B_L B_DW_I B_DI_R net042 VDD ++ VSS / RSC_IHPSG13_DFNQMX2IX1 +XB_BREG B_BIST_EN_I B_BIST_BM_I B_DCLK_B_L B_BM_I B_BM_R net043 VDD ++ VSS / RSC_IHPSG13_DFNQMX2IX1 +XA_DREG A_BIST_EN_I A_BIST_DW_I A_DCLK_B_L A_DW_I A_DI_R net22 VDD VSS ++ / RSC_IHPSG13_DFNQMX2IX1 +XA_BREG A_BIST_EN_I A_BIST_BM_I A_DCLK_B_L A_BM_I A_BM_R net21 VDD VSS ++ / RSC_IHPSG13_DFNQMX2IX1 +XB_DEC3<31> B_P1<1> B_P0<1> B_ADDR_DEC<7> net041<0> VDD VSS / ++ RSC_IHPSG13_NAND3X2 +XB_DEC3<30> B_P1<1> B_P0<1> B_ADDR_DEC<6> net041<1> VDD VSS / ++ RSC_IHPSG13_NAND3X2 +XB_DEC3<29> B_P1<1> B_P0<1> B_ADDR_DEC<5> net041<2> VDD VSS / ++ RSC_IHPSG13_NAND3X2 +XB_DEC3<28> B_P1<1> B_P0<1> B_ADDR_DEC<4> net041<3> VDD VSS / ++ RSC_IHPSG13_NAND3X2 +XB_DEC3<27> B_P1<1> B_P0<1> B_ADDR_DEC<3> net041<4> VDD VSS / ++ RSC_IHPSG13_NAND3X2 +XB_DEC3<26> B_P1<1> B_P0<1> B_ADDR_DEC<2> net041<5> VDD VSS / ++ RSC_IHPSG13_NAND3X2 +XB_DEC3<25> B_P1<1> B_P0<1> B_ADDR_DEC<1> net041<6> VDD VSS / ++ RSC_IHPSG13_NAND3X2 +XB_DEC3<24> B_P1<1> B_P0<1> B_ADDR_DEC<0> net041<7> VDD VSS / ++ RSC_IHPSG13_NAND3X2 +XB_DEC3<23> B_P1<1> B_N0<1> B_ADDR_DEC<7> net041<8> VDD VSS / ++ RSC_IHPSG13_NAND3X2 +XB_DEC3<22> B_P1<1> B_N0<1> B_ADDR_DEC<6> net041<9> VDD VSS / ++ RSC_IHPSG13_NAND3X2 +XB_DEC3<21> B_P1<1> B_N0<1> B_ADDR_DEC<5> net041<10> VDD VSS / ++ RSC_IHPSG13_NAND3X2 +XB_DEC3<20> B_P1<1> B_N0<1> B_ADDR_DEC<4> net041<11> VDD VSS / ++ RSC_IHPSG13_NAND3X2 +XB_DEC3<19> B_P1<1> B_N0<1> B_ADDR_DEC<3> net041<12> VDD VSS / ++ RSC_IHPSG13_NAND3X2 +XB_DEC3<18> B_P1<1> B_N0<1> B_ADDR_DEC<2> net041<13> VDD VSS / ++ RSC_IHPSG13_NAND3X2 +XB_DEC3<17> B_P1<1> B_N0<1> B_ADDR_DEC<1> net041<14> VDD VSS / ++ RSC_IHPSG13_NAND3X2 +XB_DEC3<16> B_P1<1> B_N0<1> B_ADDR_DEC<0> net041<15> VDD VSS / ++ RSC_IHPSG13_NAND3X2 +XB_DEC3<15> B_N1<0> B_P0<0> B_ADDR_DEC<7> net041<16> VDD VSS / ++ RSC_IHPSG13_NAND3X2 +XB_DEC3<14> B_N1<0> B_P0<0> B_ADDR_DEC<6> net041<17> VDD VSS / ++ RSC_IHPSG13_NAND3X2 +XB_DEC3<13> B_N1<0> B_P0<0> B_ADDR_DEC<5> net041<18> VDD VSS / ++ RSC_IHPSG13_NAND3X2 +XB_DEC3<12> B_N1<0> B_P0<0> B_ADDR_DEC<4> net041<19> VDD VSS / ++ RSC_IHPSG13_NAND3X2 +XB_DEC3<11> B_N1<0> B_P0<0> B_ADDR_DEC<3> net041<20> VDD VSS / ++ RSC_IHPSG13_NAND3X2 +XB_DEC3<10> B_N1<0> B_P0<0> B_ADDR_DEC<2> net041<21> VDD VSS / ++ RSC_IHPSG13_NAND3X2 +XB_DEC3<9> B_N1<0> B_P0<0> B_ADDR_DEC<1> net041<22> VDD VSS / ++ RSC_IHPSG13_NAND3X2 +XB_DEC3<8> B_N1<0> B_P0<0> B_ADDR_DEC<0> net041<23> VDD VSS / ++ RSC_IHPSG13_NAND3X2 +XB_DEC3<7> B_N1<0> B_N0<0> B_ADDR_DEC<7> net041<24> VDD VSS / ++ RSC_IHPSG13_NAND3X2 +XB_DEC3<6> B_N1<0> B_N0<0> B_ADDR_DEC<6> net041<25> VDD VSS / ++ RSC_IHPSG13_NAND3X2 +XB_DEC3<5> B_N1<0> B_N0<0> B_ADDR_DEC<5> net041<26> VDD VSS / ++ RSC_IHPSG13_NAND3X2 +XB_DEC3<4> B_N1<0> B_N0<0> B_ADDR_DEC<4> net041<27> VDD VSS / ++ RSC_IHPSG13_NAND3X2 +XB_DEC3<3> B_N1<0> B_N0<0> B_ADDR_DEC<3> net041<28> VDD VSS / ++ RSC_IHPSG13_NAND3X2 +XB_DEC3<2> B_N1<0> B_N0<0> B_ADDR_DEC<2> net041<29> VDD VSS / ++ RSC_IHPSG13_NAND3X2 +XB_DEC3<1> B_N1<0> B_N0<0> B_ADDR_DEC<1> net041<30> VDD VSS / ++ RSC_IHPSG13_NAND3X2 +XB_DEC3<0> B_N1<0> B_N0<0> B_ADDR_DEC<0> net041<31> VDD VSS / ++ RSC_IHPSG13_NAND3X2 +XA_DEC3<31> A_P1<1> A_P0<1> A_ADDR_DEC<7> net23<0> VDD VSS / ++ RSC_IHPSG13_NAND3X2 +XA_DEC3<30> A_P1<1> A_P0<1> A_ADDR_DEC<6> net23<1> VDD VSS / ++ RSC_IHPSG13_NAND3X2 +XA_DEC3<29> A_P1<1> A_P0<1> A_ADDR_DEC<5> net23<2> VDD VSS / ++ RSC_IHPSG13_NAND3X2 +XA_DEC3<28> A_P1<1> A_P0<1> A_ADDR_DEC<4> net23<3> VDD VSS / ++ RSC_IHPSG13_NAND3X2 +XA_DEC3<27> A_P1<1> A_P0<1> A_ADDR_DEC<3> net23<4> VDD VSS / ++ RSC_IHPSG13_NAND3X2 +XA_DEC3<26> A_P1<1> A_P0<1> A_ADDR_DEC<2> net23<5> VDD VSS / ++ RSC_IHPSG13_NAND3X2 +XA_DEC3<25> A_P1<1> A_P0<1> A_ADDR_DEC<1> net23<6> VDD VSS / ++ RSC_IHPSG13_NAND3X2 +XA_DEC3<24> A_P1<1> A_P0<1> A_ADDR_DEC<0> net23<7> VDD VSS / ++ RSC_IHPSG13_NAND3X2 +XA_DEC3<23> A_P1<1> A_N0<1> A_ADDR_DEC<7> net23<8> VDD VSS / ++ RSC_IHPSG13_NAND3X2 +XA_DEC3<22> A_P1<1> A_N0<1> A_ADDR_DEC<6> net23<9> VDD VSS / ++ RSC_IHPSG13_NAND3X2 +XA_DEC3<21> A_P1<1> A_N0<1> A_ADDR_DEC<5> net23<10> VDD VSS / ++ RSC_IHPSG13_NAND3X2 +XA_DEC3<20> A_P1<1> A_N0<1> A_ADDR_DEC<4> net23<11> VDD VSS / ++ RSC_IHPSG13_NAND3X2 +XA_DEC3<19> A_P1<1> A_N0<1> A_ADDR_DEC<3> net23<12> VDD VSS / ++ RSC_IHPSG13_NAND3X2 +XA_DEC3<18> A_P1<1> A_N0<1> A_ADDR_DEC<2> net23<13> VDD VSS / ++ RSC_IHPSG13_NAND3X2 +XA_DEC3<17> A_P1<1> A_N0<1> A_ADDR_DEC<1> net23<14> VDD VSS / ++ RSC_IHPSG13_NAND3X2 +XA_DEC3<16> A_P1<1> A_N0<1> A_ADDR_DEC<0> net23<15> VDD VSS / ++ RSC_IHPSG13_NAND3X2 +XA_DEC3<15> A_N1<0> A_P0<0> A_ADDR_DEC<7> net23<16> VDD VSS / ++ RSC_IHPSG13_NAND3X2 +XA_DEC3<14> A_N1<0> A_P0<0> A_ADDR_DEC<6> net23<17> VDD VSS / ++ RSC_IHPSG13_NAND3X2 +XA_DEC3<13> A_N1<0> A_P0<0> A_ADDR_DEC<5> net23<18> VDD VSS / ++ RSC_IHPSG13_NAND3X2 +XA_DEC3<12> A_N1<0> A_P0<0> A_ADDR_DEC<4> net23<19> VDD VSS / ++ RSC_IHPSG13_NAND3X2 +XA_DEC3<11> A_N1<0> A_P0<0> A_ADDR_DEC<3> net23<20> VDD VSS / ++ RSC_IHPSG13_NAND3X2 +XA_DEC3<10> A_N1<0> A_P0<0> A_ADDR_DEC<2> net23<21> VDD VSS / ++ RSC_IHPSG13_NAND3X2 +XA_DEC3<9> A_N1<0> A_P0<0> A_ADDR_DEC<1> net23<22> VDD VSS / ++ RSC_IHPSG13_NAND3X2 +XA_DEC3<8> A_N1<0> A_P0<0> A_ADDR_DEC<0> net23<23> VDD VSS / ++ RSC_IHPSG13_NAND3X2 +XA_DEC3<7> A_N1<0> A_N0<0> A_ADDR_DEC<7> net23<24> VDD VSS / ++ RSC_IHPSG13_NAND3X2 +XA_DEC3<6> A_N1<0> A_N0<0> A_ADDR_DEC<6> net23<25> VDD VSS / ++ RSC_IHPSG13_NAND3X2 +XA_DEC3<5> A_N1<0> A_N0<0> A_ADDR_DEC<5> net23<26> VDD VSS / ++ RSC_IHPSG13_NAND3X2 +XA_DEC3<4> A_N1<0> A_N0<0> A_ADDR_DEC<4> net23<27> VDD VSS / ++ RSC_IHPSG13_NAND3X2 +XA_DEC3<3> A_N1<0> A_N0<0> A_ADDR_DEC<3> net23<28> VDD VSS / ++ RSC_IHPSG13_NAND3X2 +XA_DEC3<2> A_N1<0> A_N0<0> A_ADDR_DEC<2> net23<29> VDD VSS / ++ RSC_IHPSG13_NAND3X2 +XA_DEC3<1> A_N1<0> A_N0<0> A_ADDR_DEC<1> net23<30> VDD VSS / ++ RSC_IHPSG13_NAND3X2 +XA_DEC3<0> A_N1<0> A_N0<0> A_ADDR_DEC<0> net23<31> VDD VSS / ++ RSC_IHPSG13_NAND3X2 +XB_I89 B_DCLK_B_L B_DCLK_B_R / RSC_IHPSG13_MET3RES +XB_I91 B_RCLK_B_L B_RCLK_B_R / RSC_IHPSG13_MET3RES +XB_I90 B_WCLK_B_L B_WCLK_B_R / RSC_IHPSG13_MET3RES +XB_I88 B_DCLK_L B_DCLK_R / RSC_IHPSG13_MET3RES +XB_I87 B_WCLK_L B_WCLK_R / RSC_IHPSG13_MET3RES +XB_R2 B_RCLK_L B_RCLK_R / RSC_IHPSG13_MET3RES +XA_I89 A_DCLK_B_L A_DCLK_B_R / RSC_IHPSG13_MET3RES +XA_I91 A_RCLK_B_L A_RCLK_B_R / RSC_IHPSG13_MET3RES +XA_I90 A_WCLK_B_L A_WCLK_B_R / RSC_IHPSG13_MET3RES +XA_I88 A_DCLK_L A_DCLK_R / RSC_IHPSG13_MET3RES +XA_I87 A_WCLK_L A_WCLK_R / RSC_IHPSG13_MET3RES +XA_R2 A_RCLK_L A_RCLK_R / RSC_IHPSG13_MET3RES +XB_BM_TIEH B_TIEH_O VDD VSS / RSC_IHPSG13_TIEH +XA_BM_TIEH A_TIEH_O VDD VSS / RSC_IHPSG13_TIEH +.ENDS +.SUBCKT RM_IHPSG13_512x16_c2_2P_COLDRV13_FILL4 VDD VSS +XI0<11> VDD VSS / RSC_IHPSG13_FILLCAP4 +XI0<10> VDD VSS / RSC_IHPSG13_FILLCAP4 +XI0<9> VDD VSS / RSC_IHPSG13_FILLCAP4 +XI0<8> VDD VSS / RSC_IHPSG13_FILLCAP4 +XI0<7> VDD VSS / RSC_IHPSG13_FILLCAP4 +XI0<6> VDD VSS / RSC_IHPSG13_FILLCAP4 +XI0<5> VDD VSS / RSC_IHPSG13_FILLCAP4 +XI0<4> VDD VSS / RSC_IHPSG13_FILLCAP4 +XI0<3> VDD VSS / RSC_IHPSG13_FILLCAP4 +XI0<2> VDD VSS / RSC_IHPSG13_FILLCAP4 +XI0<1> VDD VSS / RSC_IHPSG13_FILLCAP4 +.ENDS + + +.SUBCKT RSC_IHPSG13_CBUFX16 A Z VDD VSS +MN0 net4 A VSS VSS sg13_lv_nmos m=1 w=2.115u l=130.00n ng=3 nrd=0 nrs=0 +MN1 Z net4 VSS VSS sg13_lv_nmos m=1 w=5.64u l=130.00n ng=8 nrd=0 nrs=0 +MP1 Z net4 VDD VDD sg13_lv_pmos m=1 w=13.000u l=130.00n ng=8 nrd=0 ++ nrs=0 +MP0 net4 A VDD VDD sg13_lv_pmos m=1 w=4.89u l=130.00n ng=3 nrd=0 nrs=0 +.ENDS +.SUBCKT RM_IHPSG13_512x16_c2_1P_COLDRV13X16 ADDR_COL_I<1> ADDR_COL_I<0> ADDR_COL_O<1> ++ ADDR_COL_O<0> ADDR_DEC_I<7> ADDR_DEC_I<6> ADDR_DEC_I<5> ADDR_DEC_I<4> ++ ADDR_DEC_I<3> ADDR_DEC_I<2> ADDR_DEC_I<1> ADDR_DEC_I<0> ADDR_DEC_O<7> ++ ADDR_DEC_O<6> ADDR_DEC_O<5> ADDR_DEC_O<4> ADDR_DEC_O<3> ADDR_DEC_O<2> ++ ADDR_DEC_O<1> ADDR_DEC_O<0> DCLK_I DCLK_O RCLK_I RCLK_O WCLK_I WCLK_O ++ VDD VSS +XI1<1> VDD VSS / RSC_IHPSG13_FILLCAP4 +XI1<0> VDD VSS / RSC_IHPSG13_FILLCAP4 +XI0<3> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI0<2> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI0<1> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI0<0> VDD VSS / RSC_IHPSG13_FILLCAP8 +XADDR_COL_DRV<1> ADDR_COL_I<1> ADDR_COL_O<1> VDD VSS / ++ RSC_IHPSG13_CBUFX16 +XADDR_COL_DRV<0> ADDR_COL_I<0> ADDR_COL_O<0> VDD VSS / ++ RSC_IHPSG13_CBUFX16 +XADDR_DEC_DRV<7> ADDR_DEC_I<7> ADDR_DEC_O<7> VDD VSS / ++ RSC_IHPSG13_CBUFX16 +XADDR_DEC_DRV<6> ADDR_DEC_I<6> ADDR_DEC_O<6> VDD VSS / ++ RSC_IHPSG13_CBUFX16 +XADDR_DEC_DRV<5> ADDR_DEC_I<5> ADDR_DEC_O<5> VDD VSS / ++ RSC_IHPSG13_CBUFX16 +XADDR_DEC_DRV<4> ADDR_DEC_I<4> ADDR_DEC_O<4> VDD VSS / ++ RSC_IHPSG13_CBUFX16 +XADDR_DEC_DRV<3> ADDR_DEC_I<3> ADDR_DEC_O<3> VDD VSS / ++ RSC_IHPSG13_CBUFX16 +XADDR_DEC_DRV<2> ADDR_DEC_I<2> ADDR_DEC_O<2> VDD VSS / ++ RSC_IHPSG13_CBUFX16 +XADDR_DEC_DRV<1> ADDR_DEC_I<1> ADDR_DEC_O<1> VDD VSS / ++ RSC_IHPSG13_CBUFX16 +XADDR_DEC_DRV<0> ADDR_DEC_I<0> ADDR_DEC_O<0> VDD VSS / ++ RSC_IHPSG13_CBUFX16 +XDCLK_DRV DCLK_I DCLK_O VDD VSS / RSC_IHPSG13_CBUFX16 +XRCLK_DRV RCLK_I RCLK_O VDD VSS / RSC_IHPSG13_CBUFX16 +XWCLK_DRV WCLK_I WCLK_O VDD VSS / RSC_IHPSG13_CBUFX16 +.ENDS +.SUBCKT RSC_IHPSG13_WLDRVX16 A Z VDD VSS +MN1 Z net6 VSS VSS sg13_lv_nmos m=1 w=1.41u l=130.00n ng=2 nrd=0 nrs=0 +MN0 net6 A VSS VSS sg13_lv_nmos m=1 w=1.8u l=130.00n ng=2 nrd=0 nrs=0 +MP1 Z net6 VDD VDD sg13_lv_pmos m=1 w=12.96u l=130.00n ng=8 nrd=0 nrs=0 +MP0 net6 A VDD VDD sg13_lv_pmos m=1 w=900.0n l=130.00n ng=1 nrd=0 nrs=0 +.ENDS +.SUBCKT RM_IHPSG13_512x16_c2_1P_WLDRV16X16 A<15> A<14> A<13> A<12> A<11> A<10> A<9> A<8> ++ A<7> A<6> A<5> A<4> A<3> A<2> A<1> A<0> Z<15> Z<14> Z<13> Z<12> Z<11> Z<10> ++ Z<9> Z<8> Z<7> Z<6> Z<5> Z<4> Z<3> Z<2> Z<1> Z<0> VDD VSS +XBUF<15> A<15> Z<15> VDD VSS / RSC_IHPSG13_WLDRVX16 +XBUF<14> A<14> Z<14> VDD VSS / RSC_IHPSG13_WLDRVX16 +XBUF<13> A<13> Z<13> VDD VSS / RSC_IHPSG13_WLDRVX16 +XBUF<12> A<12> Z<12> VDD VSS / RSC_IHPSG13_WLDRVX16 +XBUF<11> A<11> Z<11> VDD VSS / RSC_IHPSG13_WLDRVX16 +XBUF<10> A<10> Z<10> VDD VSS / RSC_IHPSG13_WLDRVX16 +XBUF<9> A<9> Z<9> VDD VSS / RSC_IHPSG13_WLDRVX16 +XBUF<8> A<8> Z<8> VDD VSS / RSC_IHPSG13_WLDRVX16 +XBUF<7> A<7> Z<7> VDD VSS / RSC_IHPSG13_WLDRVX16 +XBUF<6> A<6> Z<6> VDD VSS / RSC_IHPSG13_WLDRVX16 +XBUF<5> A<5> Z<5> VDD VSS / RSC_IHPSG13_WLDRVX16 +XBUF<4> A<4> Z<4> VDD VSS / RSC_IHPSG13_WLDRVX16 +XBUF<3> A<3> Z<3> VDD VSS / RSC_IHPSG13_WLDRVX16 +XBUF<2> A<2> Z<2> VDD VSS / RSC_IHPSG13_WLDRVX16 +XBUF<1> A<1> Z<1> VDD VSS / RSC_IHPSG13_WLDRVX16 +XBUF<0> A<0> Z<0> VDD VSS / RSC_IHPSG13_WLDRVX16 +.ENDS + + +.SUBCKT RM_IHPSG13_512x16_c2_2P_COLDRV13X4 ADDR_COL_I<1> ADDR_COL_I<0> ADDR_COL_O<1> ++ ADDR_COL_O<0> ADDR_DEC_I<7> ADDR_DEC_I<6> ADDR_DEC_I<5> ADDR_DEC_I<4> ++ ADDR_DEC_I<3> ADDR_DEC_I<2> ADDR_DEC_I<1> ADDR_DEC_I<0> ADDR_DEC_O<7> ++ ADDR_DEC_O<6> ADDR_DEC_O<5> ADDR_DEC_O<4> ADDR_DEC_O<3> ADDR_DEC_O<2> ++ ADDR_DEC_O<1> ADDR_DEC_O<0> DCLK_I DCLK_O RCLK_I RCLK_O WCLK_I WCLK_O ++ VDD VSS +XWCLK_DRV WCLK_I WCLK_O VDD VSS / RSC_IHPSG13_CBUFX4 +XRCLK_DRV RCLK_I RCLK_O VDD VSS / RSC_IHPSG13_CBUFX4 +XDCLK_DRV DCLK_I DCLK_O VDD VSS / RSC_IHPSG13_CBUFX4 +XADDR_COL_DRV<1> ADDR_COL_I<1> ADDR_COL_O<1> VDD VSS / ++ RSC_IHPSG13_CBUFX4 +XADDR_COL_DRV<0> ADDR_COL_I<0> ADDR_COL_O<0> VDD VSS / ++ RSC_IHPSG13_CBUFX4 +XADDR_DEC_DRV<7> ADDR_DEC_I<7> ADDR_DEC_O<7> VDD VSS / ++ RSC_IHPSG13_CBUFX4 +XADDR_DEC_DRV<6> ADDR_DEC_I<6> ADDR_DEC_O<6> VDD VSS / ++ RSC_IHPSG13_CBUFX4 +XADDR_DEC_DRV<5> ADDR_DEC_I<5> ADDR_DEC_O<5> VDD VSS / ++ RSC_IHPSG13_CBUFX4 +XADDR_DEC_DRV<4> ADDR_DEC_I<4> ADDR_DEC_O<4> VDD VSS / ++ RSC_IHPSG13_CBUFX4 +XADDR_DEC_DRV<3> ADDR_DEC_I<3> ADDR_DEC_O<3> VDD VSS / ++ RSC_IHPSG13_CBUFX4 +XADDR_DEC_DRV<2> ADDR_DEC_I<2> ADDR_DEC_O<2> VDD VSS / ++ RSC_IHPSG13_CBUFX4 +XADDR_DEC_DRV<1> ADDR_DEC_I<1> ADDR_DEC_O<1> VDD VSS / ++ RSC_IHPSG13_CBUFX4 +XADDR_DEC_DRV<0> ADDR_DEC_I<0> ADDR_DEC_O<0> VDD VSS / ++ RSC_IHPSG13_CBUFX4 +XI0<6> VDD VSS / RSC_IHPSG13_FILLCAP4 +XI0<5> VDD VSS / RSC_IHPSG13_FILLCAP4 +XI0<4> VDD VSS / RSC_IHPSG13_FILLCAP4 +XI0<3> VDD VSS / RSC_IHPSG13_FILLCAP4 +XI0<2> VDD VSS / RSC_IHPSG13_FILLCAP4 +XI0<1> VDD VSS / RSC_IHPSG13_FILLCAP4 +XI1 VDD VSS / RSC_IHPSG13_FILLCAP8 +.ENDS +.SUBCKT RM_IHPSG13_512x16_c2_2P_WLDRV16X4 A<15> A<14> A<13> A<12> A<11> A<10> A<9> A<8> ++ A<7> A<6> A<5> A<4> A<3> A<2> A<1> A<0> Z<15> Z<14> Z<13> Z<12> Z<11> Z<10> ++ Z<9> Z<8> Z<7> Z<6> Z<5> Z<4> Z<3> Z<2> Z<1> Z<0> VDD VSS +XBUF<15> A<15> Z<15> VDD VSS / RSC_IHPSG13_WLDRVX4 +XBUF<14> A<14> Z<14> VDD VSS / RSC_IHPSG13_WLDRVX4 +XBUF<13> A<13> Z<13> VDD VSS / RSC_IHPSG13_WLDRVX4 +XBUF<12> A<12> Z<12> VDD VSS / RSC_IHPSG13_WLDRVX4 +XBUF<11> A<11> Z<11> VDD VSS / RSC_IHPSG13_WLDRVX4 +XBUF<10> A<10> Z<10> VDD VSS / RSC_IHPSG13_WLDRVX4 +XBUF<9> A<9> Z<9> VDD VSS / RSC_IHPSG13_WLDRVX4 +XBUF<8> A<8> Z<8> VDD VSS / RSC_IHPSG13_WLDRVX4 +XBUF<7> A<7> Z<7> VDD VSS / RSC_IHPSG13_WLDRVX4 +XBUF<6> A<6> Z<6> VDD VSS / RSC_IHPSG13_WLDRVX4 +XBUF<5> A<5> Z<5> VDD VSS / RSC_IHPSG13_WLDRVX4 +XBUF<4> A<4> Z<4> VDD VSS / RSC_IHPSG13_WLDRVX4 +XBUF<3> A<3> Z<3> VDD VSS / RSC_IHPSG13_WLDRVX4 +XBUF<2> A<2> Z<2> VDD VSS / RSC_IHPSG13_WLDRVX4 +XBUF<1> A<1> Z<1> VDD VSS / RSC_IHPSG13_WLDRVX4 +XBUF<0> A<0> Z<0> VDD VSS / RSC_IHPSG13_WLDRVX4 +.ENDS +.SUBCKT RM_IHPSG13_512x16_c2_2P_ROWDEC8 ADDR_N_I<7> ADDR_N_I<6> ADDR_N_I<5> ADDR_N_I<4> ++ ADDR_N_I<3> ADDR_N_I<2> ADDR_N_I<1> ADDR_N_I<0> CS_I ECLK_I WL_O<255> ++ WL_O<254> WL_O<253> WL_O<252> WL_O<251> WL_O<250> WL_O<249> WL_O<248> ++ WL_O<247> WL_O<246> WL_O<245> WL_O<244> WL_O<243> WL_O<242> WL_O<241> ++ WL_O<240> WL_O<239> WL_O<238> WL_O<237> WL_O<236> WL_O<235> WL_O<234> ++ WL_O<233> WL_O<232> WL_O<231> WL_O<230> WL_O<229> WL_O<228> WL_O<227> ++ WL_O<226> WL_O<225> WL_O<224> WL_O<223> WL_O<222> WL_O<221> WL_O<220> ++ WL_O<219> WL_O<218> WL_O<217> WL_O<216> WL_O<215> WL_O<214> WL_O<213> ++ WL_O<212> WL_O<211> WL_O<210> WL_O<209> WL_O<208> WL_O<207> WL_O<206> ++ WL_O<205> WL_O<204> WL_O<203> WL_O<202> WL_O<201> WL_O<200> WL_O<199> ++ WL_O<198> WL_O<197> WL_O<196> WL_O<195> WL_O<194> WL_O<193> WL_O<192> ++ WL_O<191> WL_O<190> WL_O<189> WL_O<188> WL_O<187> WL_O<186> WL_O<185> ++ WL_O<184> WL_O<183> WL_O<182> WL_O<181> WL_O<180> WL_O<179> WL_O<178> ++ WL_O<177> WL_O<176> WL_O<175> WL_O<174> WL_O<173> WL_O<172> WL_O<171> ++ WL_O<170> WL_O<169> WL_O<168> WL_O<167> WL_O<166> WL_O<165> WL_O<164> ++ WL_O<163> WL_O<162> WL_O<161> WL_O<160> WL_O<159> WL_O<158> WL_O<157> ++ WL_O<156> WL_O<155> WL_O<154> WL_O<153> WL_O<152> WL_O<151> WL_O<150> ++ WL_O<149> WL_O<148> WL_O<147> WL_O<146> WL_O<145> WL_O<144> WL_O<143> ++ WL_O<142> WL_O<141> WL_O<140> WL_O<139> WL_O<138> WL_O<137> WL_O<136> ++ WL_O<135> WL_O<134> WL_O<133> WL_O<132> WL_O<131> WL_O<130> WL_O<129> ++ WL_O<128> WL_O<127> WL_O<126> WL_O<125> WL_O<124> WL_O<123> WL_O<122> ++ WL_O<121> WL_O<120> WL_O<119> WL_O<118> WL_O<117> WL_O<116> WL_O<115> ++ WL_O<114> WL_O<113> WL_O<112> WL_O<111> WL_O<110> WL_O<109> WL_O<108> ++ WL_O<107> WL_O<106> WL_O<105> WL_O<104> WL_O<103> WL_O<102> WL_O<101> ++ WL_O<100> WL_O<99> WL_O<98> WL_O<97> WL_O<96> WL_O<95> WL_O<94> WL_O<93> ++ WL_O<92> WL_O<91> WL_O<90> WL_O<89> WL_O<88> WL_O<87> WL_O<86> WL_O<85> ++ WL_O<84> WL_O<83> WL_O<82> WL_O<81> WL_O<80> WL_O<79> WL_O<78> WL_O<77> ++ WL_O<76> WL_O<75> WL_O<74> WL_O<73> WL_O<72> WL_O<71> WL_O<70> WL_O<69> ++ WL_O<68> WL_O<67> WL_O<66> WL_O<65> WL_O<64> WL_O<63> WL_O<62> WL_O<61> ++ WL_O<60> WL_O<59> WL_O<58> WL_O<57> WL_O<56> WL_O<55> WL_O<54> WL_O<53> ++ WL_O<52> WL_O<51> WL_O<50> WL_O<49> WL_O<48> WL_O<47> WL_O<46> WL_O<45> ++ WL_O<44> WL_O<43> WL_O<42> WL_O<41> WL_O<40> WL_O<39> WL_O<38> WL_O<37> ++ WL_O<36> WL_O<35> WL_O<34> WL_O<33> WL_O<32> WL_O<31> WL_O<30> WL_O<29> ++ WL_O<28> WL_O<27> WL_O<26> WL_O<25> WL_O<24> WL_O<23> WL_O<22> WL_O<21> ++ WL_O<20> WL_O<19> WL_O<18> WL_O<17> WL_O<16> WL_O<15> WL_O<14> WL_O<13> ++ WL_O<12> WL_O<11> WL_O<10> WL_O<9> WL_O<8> WL_O<7> WL_O<6> WL_O<5> WL_O<4> ++ WL_O<3> WL_O<2> WL_O<1> WL_O<0> VDD VSS +XDEC11<4> ADDR_N_I<7> ADDR_N_I<6> CS_I CS04<3> VDD VSS / ++ RM_IHPSG13_512x16_c2_2P_DEC03 +XDEC11<3> ADDR_N_I<5> ADDR_N_I<4> CS04<3> CS00<15> VDD VSS / ++ RM_IHPSG13_512x16_c2_2P_DEC03 +XDEC11<2> ADDR_N_I<5> ADDR_N_I<4> CS04<2> CS00<11> VDD VSS / ++ RM_IHPSG13_512x16_c2_2P_DEC03 +XDEC11<1> ADDR_N_I<5> ADDR_N_I<4> CS04<1> CS00<7> VDD VSS / ++ RM_IHPSG13_512x16_c2_2P_DEC03 +XDEC11<0> ADDR_N_I<5> ADDR_N_I<4> CS04<0> CS00<3> VDD VSS / ++ RM_IHPSG13_512x16_c2_2P_DEC03 +XSEL<15> ADDR_N_I<3> ADDR_N_I<2> ADDR_N_I<1> ADDR_N_I<0> CS00<15> ECLK_H<15> ++ ECLK_H<16> ECLK_B<15> ECLK_B<16> WL_O<255> WL_O<254> WL_O<253> WL_O<252> ++ WL_O<251> WL_O<250> WL_O<249> WL_O<248> WL_O<247> WL_O<246> WL_O<245> ++ WL_O<244> WL_O<243> WL_O<242> WL_O<241> WL_O<240> VDD VSS / ++ RM_IHPSG13_512x16_c2_2P_DEC04 +XSEL<14> ADDR_N_I<3> ADDR_N_I<2> ADDR_N_I<1> ADDR_N_I<0> CS00<14> ECLK_H<14> ++ ECLK_H<15> ECLK_B<14> ECLK_B<15> WL_O<239> WL_O<238> WL_O<237> WL_O<236> ++ WL_O<235> WL_O<234> WL_O<233> WL_O<232> WL_O<231> WL_O<230> WL_O<229> ++ WL_O<228> WL_O<227> WL_O<226> WL_O<225> WL_O<224> VDD VSS / ++ RM_IHPSG13_512x16_c2_2P_DEC04 +XSEL<13> ADDR_N_I<3> ADDR_N_I<2> ADDR_N_I<1> ADDR_N_I<0> CS00<13> ECLK_H<13> ++ ECLK_H<14> ECLK_B<13> ECLK_B<14> WL_O<223> WL_O<222> WL_O<221> WL_O<220> ++ WL_O<219> WL_O<218> WL_O<217> WL_O<216> WL_O<215> WL_O<214> WL_O<213> ++ WL_O<212> WL_O<211> WL_O<210> WL_O<209> WL_O<208> VDD VSS / ++ RM_IHPSG13_512x16_c2_2P_DEC04 +XSEL<12> ADDR_N_I<3> ADDR_N_I<2> ADDR_N_I<1> ADDR_N_I<0> CS00<12> ECLK_H<12> ++ ECLK_H<13> ECLK_B<12> ECLK_B<13> WL_O<207> WL_O<206> WL_O<205> WL_O<204> ++ WL_O<203> WL_O<202> WL_O<201> WL_O<200> WL_O<199> WL_O<198> WL_O<197> ++ WL_O<196> WL_O<195> WL_O<194> WL_O<193> WL_O<192> VDD VSS / ++ RM_IHPSG13_512x16_c2_2P_DEC04 +XSEL<11> ADDR_N_I<3> ADDR_N_I<2> ADDR_N_I<1> ADDR_N_I<0> CS00<11> ECLK_H<11> ++ ECLK_H<12> ECLK_B<11> ECLK_B<12> WL_O<191> WL_O<190> WL_O<189> WL_O<188> ++ WL_O<187> WL_O<186> WL_O<185> WL_O<184> WL_O<183> WL_O<182> WL_O<181> ++ WL_O<180> WL_O<179> WL_O<178> WL_O<177> WL_O<176> VDD VSS / ++ RM_IHPSG13_512x16_c2_2P_DEC04 +XSEL<10> ADDR_N_I<3> ADDR_N_I<2> ADDR_N_I<1> ADDR_N_I<0> CS00<10> ECLK_H<10> ++ ECLK_H<11> ECLK_B<10> ECLK_B<11> WL_O<175> WL_O<174> WL_O<173> WL_O<172> ++ WL_O<171> WL_O<170> WL_O<169> WL_O<168> WL_O<167> WL_O<166> WL_O<165> ++ WL_O<164> WL_O<163> WL_O<162> WL_O<161> WL_O<160> VDD VSS / ++ RM_IHPSG13_512x16_c2_2P_DEC04 +XSEL<9> ADDR_N_I<3> ADDR_N_I<2> ADDR_N_I<1> ADDR_N_I<0> CS00<9> ECLK_H<9> ++ ECLK_H<10> ECLK_B<9> ECLK_B<10> WL_O<159> WL_O<158> WL_O<157> WL_O<156> ++ WL_O<155> WL_O<154> WL_O<153> WL_O<152> WL_O<151> WL_O<150> WL_O<149> ++ WL_O<148> WL_O<147> WL_O<146> WL_O<145> WL_O<144> VDD VSS / ++ RM_IHPSG13_512x16_c2_2P_DEC04 +XSEL<8> ADDR_N_I<3> ADDR_N_I<2> ADDR_N_I<1> ADDR_N_I<0> CS00<8> ECLK_H<8> ++ ECLK_H<9> ECLK_B<8> ECLK_B<9> WL_O<143> WL_O<142> WL_O<141> WL_O<140> ++ WL_O<139> WL_O<138> WL_O<137> WL_O<136> WL_O<135> WL_O<134> WL_O<133> ++ WL_O<132> WL_O<131> WL_O<130> WL_O<129> WL_O<128> VDD VSS / ++ RM_IHPSG13_512x16_c2_2P_DEC04 +XSEL<7> ADDR_N_I<3> ADDR_N_I<2> ADDR_N_I<1> ADDR_N_I<0> CS00<7> ECLK_H<7> ++ ECLK_H<8> ECLK_B<7> ECLK_B<8> WL_O<127> WL_O<126> WL_O<125> WL_O<124> ++ WL_O<123> WL_O<122> WL_O<121> WL_O<120> WL_O<119> WL_O<118> WL_O<117> ++ WL_O<116> WL_O<115> WL_O<114> WL_O<113> WL_O<112> VDD VSS / ++ RM_IHPSG13_512x16_c2_2P_DEC04 +XSEL<6> ADDR_N_I<3> ADDR_N_I<2> ADDR_N_I<1> ADDR_N_I<0> CS00<6> ECLK_H<6> ++ ECLK_H<7> ECLK_B<6> ECLK_B<7> WL_O<111> WL_O<110> WL_O<109> WL_O<108> ++ WL_O<107> WL_O<106> WL_O<105> WL_O<104> WL_O<103> WL_O<102> WL_O<101> ++ WL_O<100> WL_O<99> WL_O<98> WL_O<97> WL_O<96> VDD VSS / ++ RM_IHPSG13_512x16_c2_2P_DEC04 +XSEL<5> ADDR_N_I<3> ADDR_N_I<2> ADDR_N_I<1> ADDR_N_I<0> CS00<5> ECLK_H<5> ++ ECLK_H<6> ECLK_B<5> ECLK_B<6> WL_O<95> WL_O<94> WL_O<93> WL_O<92> WL_O<91> ++ WL_O<90> WL_O<89> WL_O<88> WL_O<87> WL_O<86> WL_O<85> WL_O<84> WL_O<83> ++ WL_O<82> WL_O<81> WL_O<80> VDD VSS / RM_IHPSG13_512x16_c2_2P_DEC04 +XSEL<4> ADDR_N_I<3> ADDR_N_I<2> ADDR_N_I<1> ADDR_N_I<0> CS00<4> ECLK_H<4> ++ ECLK_H<5> ECLK_B<4> ECLK_B<5> WL_O<79> WL_O<78> WL_O<77> WL_O<76> WL_O<75> ++ WL_O<74> WL_O<73> WL_O<72> WL_O<71> WL_O<70> WL_O<69> WL_O<68> WL_O<67> ++ WL_O<66> WL_O<65> WL_O<64> VDD VSS / RM_IHPSG13_512x16_c2_2P_DEC04 +XSEL<3> ADDR_N_I<3> ADDR_N_I<2> ADDR_N_I<1> ADDR_N_I<0> CS00<3> ECLK_H<3> ++ ECLK_H<4> ECLK_B<3> ECLK_B<4> WL_O<63> WL_O<62> WL_O<61> WL_O<60> WL_O<59> ++ WL_O<58> WL_O<57> WL_O<56> WL_O<55> WL_O<54> WL_O<53> WL_O<52> WL_O<51> ++ WL_O<50> WL_O<49> WL_O<48> VDD VSS / RM_IHPSG13_512x16_c2_2P_DEC04 +XSEL<2> ADDR_N_I<3> ADDR_N_I<2> ADDR_N_I<1> ADDR_N_I<0> CS00<2> ECLK_H<2> ++ ECLK_H<3> ECLK_B<2> ECLK_B<3> WL_O<47> WL_O<46> WL_O<45> WL_O<44> WL_O<43> ++ WL_O<42> WL_O<41> WL_O<40> WL_O<39> WL_O<38> WL_O<37> WL_O<36> WL_O<35> ++ WL_O<34> WL_O<33> WL_O<32> VDD VSS / RM_IHPSG13_512x16_c2_2P_DEC04 +XSEL<1> ADDR_N_I<3> ADDR_N_I<2> ADDR_N_I<1> ADDR_N_I<0> CS00<1> ECLK_H<1> ++ ECLK_H<2> ECLK_B<1> ECLK_B<2> WL_O<31> WL_O<30> WL_O<29> WL_O<28> WL_O<27> ++ WL_O<26> WL_O<25> WL_O<24> WL_O<23> WL_O<22> WL_O<21> WL_O<20> WL_O<19> ++ WL_O<18> WL_O<17> WL_O<16> VDD VSS / RM_IHPSG13_512x16_c2_2P_DEC04 +XSEL<0> ADDR_N_I<3> ADDR_N_I<2> ADDR_N_I<1> ADDR_N_I<0> CS00<0> ECLK_I ++ ECLK_H<1> ECLK_B<0> ECLK_B<1> WL_O<15> WL_O<14> WL_O<13> WL_O<12> WL_O<11> ++ WL_O<10> WL_O<9> WL_O<8> WL_O<7> WL_O<6> WL_O<5> WL_O<4> WL_O<3> WL_O<2> ++ WL_O<1> WL_O<0> VDD VSS / RM_IHPSG13_512x16_c2_2P_DEC04 +XDEC10<4> ADDR_N_I<7> ADDR_N_I<6> CS_I CS04<2> VDD VSS / ++ RM_IHPSG13_512x16_c2_2P_DEC02 +XDEC10<3> ADDR_N_I<5> ADDR_N_I<4> CS04<3> CS00<14> VDD VSS / ++ RM_IHPSG13_512x16_c2_2P_DEC02 +XDEC10<2> ADDR_N_I<5> ADDR_N_I<4> CS04<2> CS00<10> VDD VSS / ++ RM_IHPSG13_512x16_c2_2P_DEC02 +XDEC10<1> ADDR_N_I<5> ADDR_N_I<4> CS04<1> CS00<6> VDD VSS / ++ RM_IHPSG13_512x16_c2_2P_DEC02 +XDEC10<0> ADDR_N_I<5> ADDR_N_I<4> CS04<0> CS00<2> VDD VSS / ++ RM_IHPSG13_512x16_c2_2P_DEC02 +XL2<132> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<131> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<130> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<129> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<128> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<127> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<126> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<125> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<124> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<123> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<122> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<121> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<120> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<119> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<118> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<117> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<116> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<115> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<114> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<113> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<112> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<111> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<110> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<109> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<108> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<107> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<106> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<105> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<104> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<103> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<102> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<101> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<100> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<99> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<98> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<97> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<96> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<95> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<94> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<93> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<92> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<91> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<90> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<89> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<88> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<87> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<86> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<85> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<84> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<83> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<82> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<81> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<80> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<79> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<78> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<77> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<76> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<75> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<74> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<73> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<72> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<71> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<70> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<69> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<68> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<67> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<66> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<65> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<64> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<63> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<62> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<61> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<60> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<59> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<58> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<57> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<56> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<55> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<54> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<53> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<52> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<51> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<50> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<49> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<48> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<47> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<46> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<45> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<44> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<43> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<42> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<41> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<40> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<39> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<38> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<37> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<36> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<35> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<34> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<33> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<32> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<31> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<30> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<29> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<28> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<27> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<26> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<25> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<24> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<23> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<22> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<21> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<20> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<19> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<18> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<17> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<16> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<15> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<14> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<13> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<12> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<11> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<10> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<9> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<8> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<7> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<6> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<5> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<4> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<3> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<2> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<1> VDD VSS / RSC_IHPSG13_FILLCAP8 +XDEC00<4> ADDR_N_I<7> ADDR_N_I<6> CS_I CS04<0> VDD VSS / ++ RM_IHPSG13_512x16_c2_2P_DEC00 +XDEC00<3> ADDR_N_I<5> ADDR_N_I<4> CS04<3> CS00<12> VDD VSS / ++ RM_IHPSG13_512x16_c2_2P_DEC00 +XDEC00<2> ADDR_N_I<5> ADDR_N_I<4> CS04<2> CS00<8> VDD VSS / ++ RM_IHPSG13_512x16_c2_2P_DEC00 +XDEC00<1> ADDR_N_I<5> ADDR_N_I<4> CS04<1> CS00<4> VDD VSS / ++ RM_IHPSG13_512x16_c2_2P_DEC00 +XDEC00<0> ADDR_N_I<5> ADDR_N_I<4> CS04<0> CS00<0> VDD VSS / ++ RM_IHPSG13_512x16_c2_2P_DEC00 +XDEC01<4> ADDR_N_I<7> ADDR_N_I<6> CS_I CS04<1> VDD VSS / ++ RM_IHPSG13_512x16_c2_2P_DEC01 +XDEC01<3> ADDR_N_I<5> ADDR_N_I<4> CS04<3> CS00<13> VDD VSS / ++ RM_IHPSG13_512x16_c2_2P_DEC01 +XDEC01<2> ADDR_N_I<5> ADDR_N_I<4> CS04<2> CS00<9> VDD VSS / ++ RM_IHPSG13_512x16_c2_2P_DEC01 +XDEC01<1> ADDR_N_I<5> ADDR_N_I<4> CS04<1> CS00<5> VDD VSS / ++ RM_IHPSG13_512x16_c2_2P_DEC01 +XDEC01<0> ADDR_N_I<5> ADDR_N_I<4> CS04<0> CS00<1> VDD VSS / ++ RM_IHPSG13_512x16_c2_2P_DEC01 +.ENDS +.SUBCKT RM_IHPSG13_512x16_c2_2P_ROWREG8 ACLK_N_I ADDR_I<7> ADDR_I<6> ADDR_I<5> ADDR_I<4> ++ ADDR_I<3> ADDR_I<2> ADDR_I<1> ADDR_I<0> ADDR_N_O<7> ADDR_N_O<6> ADDR_N_O<5> ++ ADDR_N_O<4> ADDR_N_O<3> ADDR_N_O<2> ADDR_N_O<1> ADDR_N_O<0> BIST_ADDR_I<7> ++ BIST_ADDR_I<6> BIST_ADDR_I<5> BIST_ADDR_I<4> BIST_ADDR_I<3> BIST_ADDR_I<2> ++ BIST_ADDR_I<1> BIST_ADDR_I<0> BIST_EN_I VDD VSS +XINV<7> q_int<7> qn_int<7> VDD VSS / RSC_IHPSG13_CINVX2 +XINV<6> q_int<6> qn_int<6> VDD VSS / RSC_IHPSG13_CINVX2 +XINV<5> q_int<5> qn_int<5> VDD VSS / RSC_IHPSG13_CINVX2 +XINV<4> q_int<4> qn_int<4> VDD VSS / RSC_IHPSG13_CINVX2 +XINV<3> q_int<3> qn_int<3> VDD VSS / RSC_IHPSG13_CINVX2 +XINV<2> q_int<2> qn_int<2> VDD VSS / RSC_IHPSG13_CINVX2 +XINV<1> q_int<1> qn_int<1> VDD VSS / RSC_IHPSG13_CINVX2 +XINV<0> q_int<0> qn_int<0> VDD VSS / RSC_IHPSG13_CINVX2 +XDRV<7> qn_int<7> ADDR_N_O<7> VDD VSS / RSC_IHPSG13_CINVX8 +XDRV<6> qn_int<6> ADDR_N_O<6> VDD VSS / RSC_IHPSG13_CINVX8 +XDRV<5> qn_int<5> ADDR_N_O<5> VDD VSS / RSC_IHPSG13_CINVX8 +XDRV<4> qn_int<4> ADDR_N_O<4> VDD VSS / RSC_IHPSG13_CINVX8 +XDRV<3> qn_int<3> ADDR_N_O<3> VDD VSS / RSC_IHPSG13_CINVX8 +XDRV<2> qn_int<2> ADDR_N_O<2> VDD VSS / RSC_IHPSG13_CINVX8 +XDRV<1> qn_int<1> ADDR_N_O<1> VDD VSS / RSC_IHPSG13_CINVX8 +XDRV<0> qn_int<0> ADDR_N_O<0> VDD VSS / RSC_IHPSG13_CINVX8 +XDFF<7> BIST_EN_I BIST_ADDR_I<7> ACLK_N_I ADDR_I<7> q_int<7> net2<0> VDD ++ VSS / RSC_IHPSG13_DFNQMX2IX1 +XDFF<6> BIST_EN_I BIST_ADDR_I<6> ACLK_N_I ADDR_I<6> q_int<6> net2<1> VDD ++ VSS / RSC_IHPSG13_DFNQMX2IX1 +XDFF<5> BIST_EN_I BIST_ADDR_I<5> ACLK_N_I ADDR_I<5> q_int<5> net2<2> VDD ++ VSS / RSC_IHPSG13_DFNQMX2IX1 +XDFF<4> BIST_EN_I BIST_ADDR_I<4> ACLK_N_I ADDR_I<4> q_int<4> net2<3> VDD ++ VSS / RSC_IHPSG13_DFNQMX2IX1 +XDFF<3> BIST_EN_I BIST_ADDR_I<3> ACLK_N_I ADDR_I<3> q_int<3> net2<4> VDD ++ VSS / RSC_IHPSG13_DFNQMX2IX1 +XDFF<2> BIST_EN_I BIST_ADDR_I<2> ACLK_N_I ADDR_I<2> q_int<2> net2<5> VDD ++ VSS / RSC_IHPSG13_DFNQMX2IX1 +XDFF<1> BIST_EN_I BIST_ADDR_I<1> ACLK_N_I ADDR_I<1> q_int<1> net2<6> VDD ++ VSS / RSC_IHPSG13_DFNQMX2IX1 +XDFF<0> BIST_EN_I BIST_ADDR_I<0> ACLK_N_I ADDR_I<0> q_int<0> net2<7> VDD ++ VSS / RSC_IHPSG13_DFNQMX2IX1 +XI11<4> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI11<3> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI11<2> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI11<1> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI10 VDD VSS / RSC_IHPSG13_FILLCAP4 +.ENDS +.SUBCKT RM_IHPSG13_512x16_c2_2P_COLDEC4 ACLK_N ADDR<3> ADDR<2> ADDR<1> ADDR<0> ++ ADDR_COL<1> ADDR_COL<0> ADDR_DEC<7> ADDR_DEC<6> ADDR_DEC<5> ADDR_DEC<4> ++ ADDR_DEC<3> ADDR_DEC<2> ADDR_DEC<1> ADDR_DEC<0> BIST_ADDR<3> BIST_ADDR<2> ++ BIST_ADDR<1> BIST_ADDR<0> BIST_EN_I VDD VSS +XI1<7> PADR<0> PADR<1> PADR<2> addr_n<7> VDD VSS / RSC_IHPSG13_NAND3X2 +XI1<6> NADR<0> PADR<1> PADR<2> addr_n<6> VDD VSS / RSC_IHPSG13_NAND3X2 +XI1<5> PADR<0> NADR<1> PADR<2> addr_n<5> VDD VSS / RSC_IHPSG13_NAND3X2 +XI1<4> NADR<0> NADR<1> PADR<2> addr_n<4> VDD VSS / RSC_IHPSG13_NAND3X2 +XI1<3> PADR<0> PADR<1> NADR<2> addr_n<3> VDD VSS / RSC_IHPSG13_NAND3X2 +XI1<2> NADR<0> PADR<1> NADR<2> addr_n<2> VDD VSS / RSC_IHPSG13_NAND3X2 +XI1<1> PADR<0> NADR<1> NADR<2> addr_n<1> VDD VSS / RSC_IHPSG13_NAND3X2 +XI1<0> NADR<0> NADR<1> NADR<2> addr_n<0> VDD VSS / RSC_IHPSG13_NAND3X2 +XDFF<3> BIST_EN_I BIST_ADDR<3> ACLK_N ADDR<3> addr_int net12<0> VDD ++ VSS / RSC_IHPSG13_DFNQMX2IX1 +XDFF<2> BIST_EN_I BIST_ADDR<2> ACLK_N ADDR<2> padr_int<2> net12<1> VDD ++ VSS / RSC_IHPSG13_DFNQMX2IX1 +XDFF<1> BIST_EN_I BIST_ADDR<1> ACLK_N ADDR<1> padr_int<1> net12<2> VDD ++ VSS / RSC_IHPSG13_DFNQMX2IX1 +XDFF<0> BIST_EN_I BIST_ADDR<0> ACLK_N ADDR<0> padr_int<0> net12<3> VDD ++ VSS / RSC_IHPSG13_DFNQMX2IX1 +XI17<4> VDD VSS / RSC_IHPSG13_FILLCAP4 +XI17<3> VDD VSS / RSC_IHPSG13_FILLCAP4 +XI17<2> VDD VSS / RSC_IHPSG13_FILLCAP4 +XI17<1> VDD VSS / RSC_IHPSG13_FILLCAP4 +XI13<2> NADR<2> PADR<2> VDD VSS / RSC_IHPSG13_INVX2 +XI13<1> NADR<1> PADR<1> VDD VSS / RSC_IHPSG13_INVX2 +XI13<0> NADR<0> PADR<0> VDD VSS / RSC_IHPSG13_INVX2 +XI2<7> addr_n<7> ADDR_DEC<7> VDD VSS / RSC_IHPSG13_INVX2 +XI2<6> addr_n<6> ADDR_DEC<6> VDD VSS / RSC_IHPSG13_INVX2 +XI2<5> addr_n<5> ADDR_DEC<5> VDD VSS / RSC_IHPSG13_INVX2 +XI2<4> addr_n<4> ADDR_DEC<4> VDD VSS / RSC_IHPSG13_INVX2 +XI2<3> addr_n<3> ADDR_DEC<3> VDD VSS / RSC_IHPSG13_INVX2 +XI2<2> addr_n<2> ADDR_DEC<2> VDD VSS / RSC_IHPSG13_INVX2 +XI2<1> addr_n<1> ADDR_DEC<1> VDD VSS / RSC_IHPSG13_INVX2 +XI2<0> addr_n<0> ADDR_DEC<0> VDD VSS / RSC_IHPSG13_INVX2 +XI3<2> padr_int<2> NADR<2> VDD VSS / RSC_IHPSG13_INVX2 +XI3<1> padr_int<1> NADR<1> VDD VSS / RSC_IHPSG13_INVX2 +XI3<0> padr_int<0> NADR<0> VDD VSS / RSC_IHPSG13_INVX2 +XI14 addr_int ADDR_COL<0> VDD VSS / RSC_IHPSG13_CBUFX2 +XI16<8> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI16<7> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI16<6> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI16<5> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI16<4> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI16<3> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI16<2> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI16<1> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI15 ADDR_COL<1> VDD VSS / RSC_IHPSG13_TIEL +.ENDS +.SUBCKT RM_IHPSG13_512x16_c2_2P_COLCTRL4 A_ADDR_COL A_ADDR_DEC<7> A_ADDR_DEC<6> ++ A_ADDR_DEC<5> A_ADDR_DEC<4> A_ADDR_DEC<3> A_ADDR_DEC<2> A_ADDR_DEC<1> ++ A_ADDR_DEC<0> A_BIST_BM_I A_BIST_DW_I A_BIST_EN_I A_BLC<15> A_BLC<14> ++ A_BLC<13> A_BLC<12> A_BLC<11> A_BLC<10> A_BLC<9> A_BLC<8> A_BLC<7> A_BLC<6> ++ A_BLC<5> A_BLC<4> A_BLC<3> A_BLC<2> A_BLC<1> A_BLC<0> A_BLT<15> A_BLT<14> ++ A_BLT<13> A_BLT<12> A_BLT<11> A_BLT<10> A_BLT<9> A_BLT<8> A_BLT<7> A_BLT<6> ++ A_BLT<5> A_BLT<4> A_BLT<3> A_BLT<2> A_BLT<1> A_BLT<0> A_BM_I A_DCLK_B_L ++ A_DCLK_B_R A_DCLK_L A_DCLK_R A_DR_O A_DW_I A_RCLK_B_L A_RCLK_B_R A_RCLK_L ++ A_RCLK_R A_TIEH_O A_WCLK_B_L A_WCLK_B_R A_WCLK_L A_WCLK_R B_ADDR_COL ++ B_ADDR_DEC<7> B_ADDR_DEC<6> B_ADDR_DEC<5> B_ADDR_DEC<4> B_ADDR_DEC<3> ++ B_ADDR_DEC<2> B_ADDR_DEC<1> B_ADDR_DEC<0> B_BIST_BM_I B_BIST_DW_I ++ B_BIST_EN_I B_BLC<15> B_BLC<14> B_BLC<13> B_BLC<12> B_BLC<11> B_BLC<10> ++ B_BLC<9> B_BLC<8> B_BLC<7> B_BLC<6> B_BLC<5> B_BLC<4> B_BLC<3> B_BLC<2> ++ B_BLC<1> B_BLC<0> B_BLT<15> B_BLT<14> B_BLT<13> B_BLT<12> B_BLT<11> ++ B_BLT<10> B_BLT<9> B_BLT<8> B_BLT<7> B_BLT<6> B_BLT<5> B_BLT<4> B_BLT<3> ++ B_BLT<2> B_BLT<1> B_BLT<0> B_BM_I B_DCLK_B_L B_DCLK_B_R B_DCLK_L B_DCLK_R ++ B_DR_O B_DW_I B_RCLK_B_L B_RCLK_B_R B_RCLK_L B_RCLK_R B_TIEH_O B_WCLK_B_L ++ B_WCLK_B_R B_WCLK_L B_WCLK_R VDD VSS +XB_I80 B_RCLK_B_L B_WCLK_B_L net041 VDD VSS / RSC_IHPSG13_AND2X2 +XA_I80 A_RCLK_B_L A_WCLK_B_L net21 VDD VSS / RSC_IHPSG13_AND2X2 +XB_I76 B_DI_N B_DO_WRITE_P B_WR_ZERO VDD VSS / RSC_IHPSG13_AND2X4 +XB_I75 B_DI_R B_DO_WRITE_P B_WR_ONE VDD VSS / RSC_IHPSG13_AND2X4 +XA_I76 A_DI_N A_DO_WRITE_P A_WR_ZERO VDD VSS / RSC_IHPSG13_AND2X4 +XA_I75 A_DI_R A_DO_WRITE_P A_WR_ONE VDD VSS / RSC_IHPSG13_AND2X4 +XI_FILL4<26> VDD VSS / RSC_IHPSG13_FILLCAP4 +XI_FILL4<25> VDD VSS / RSC_IHPSG13_FILLCAP4 +XI_FILL4<24> VDD VSS / RSC_IHPSG13_FILLCAP4 +XI_FILL4<23> VDD VSS / RSC_IHPSG13_FILLCAP4 +XI_FILL4<22> VDD VSS / RSC_IHPSG13_FILLCAP4 +XI_FILL4<21> VDD VSS / RSC_IHPSG13_FILLCAP4 +XI_FILL4<20> VDD VSS / RSC_IHPSG13_FILLCAP4 +XI_FILL4<19> VDD VSS / RSC_IHPSG13_FILLCAP4 +XI_FILL4<18> VDD VSS / RSC_IHPSG13_FILLCAP4 +XI_FILL4<17> VDD VSS / RSC_IHPSG13_FILLCAP4 +XI_FILL4<16> VDD VSS / RSC_IHPSG13_FILLCAP4 +XI_FILL4<15> VDD VSS / RSC_IHPSG13_FILLCAP4 +XI_FILL4<14> VDD VSS / RSC_IHPSG13_FILLCAP4 +XI_FILL4<13> VDD VSS / RSC_IHPSG13_FILLCAP4 +XI_FILL4<12> VDD VSS / RSC_IHPSG13_FILLCAP4 +XI_FILL4<11> VDD VSS / RSC_IHPSG13_FILLCAP4 +XI_FILL4<10> VDD VSS / RSC_IHPSG13_FILLCAP4 +XI_FILL4<9> VDD VSS / RSC_IHPSG13_FILLCAP4 +XI_FILL4<8> VDD VSS / RSC_IHPSG13_FILLCAP4 +XI_FILL4<7> VDD VSS / RSC_IHPSG13_FILLCAP4 +XI_FILL4<6> VDD VSS / RSC_IHPSG13_FILLCAP4 +XI_FILL4<5> VDD VSS / RSC_IHPSG13_FILLCAP4 +XI_FILL4<4> VDD VSS / RSC_IHPSG13_FILLCAP4 +XI_FILL4<3> VDD VSS / RSC_IHPSG13_FILLCAP4 +XI_FILL4<2> VDD VSS / RSC_IHPSG13_FILLCAP4 +XI_FILL4<1> VDD VSS / RSC_IHPSG13_FILLCAP4 +XB_I69 B_DCLK_L B_DCLK_B_L VDD VSS / RSC_IHPSG13_CINVX4 +XB_I50 B_WCLK_L B_WCLK_B_L VDD VSS / RSC_IHPSG13_CINVX4 +XB_EBUF B_RCLK_L B_RCLK_B_L VDD VSS / RSC_IHPSG13_CINVX4 +XB_INV<1> B_N0 B_P0 VDD VSS / RSC_IHPSG13_CINVX4 +XB_INV<0> B_ADDR_COL B_N0 VDD VSS / RSC_IHPSG13_CINVX4 +XA_I69 A_DCLK_L A_DCLK_B_L VDD VSS / RSC_IHPSG13_CINVX4 +XA_I50 A_WCLK_L A_WCLK_B_L VDD VSS / RSC_IHPSG13_CINVX4 +XA_EBUF A_RCLK_L A_RCLK_B_L VDD VSS / RSC_IHPSG13_CINVX4 +XA_INV<1> A_N0 A_P0 VDD VSS / RSC_IHPSG13_CINVX4 +XA_INV<0> A_ADDR_COL A_N0 VDD VSS / RSC_IHPSG13_CINVX4 +XB_I81<1> net041 B_PRE_N VDD VSS / RSC_IHPSG13_CINVX4_WN +XB_I81<0> net041 B_PRE_N VDD VSS / RSC_IHPSG13_CINVX4_WN +XA_I81<1> net21 A_PRE_N VDD VSS / RSC_IHPSG13_CINVX4_WN +XA_I81<0> net21 A_PRE_N VDD VSS / RSC_IHPSG13_CINVX4_WN +XA_R2 A_RCLK_L A_RCLK_R / RSC_IHPSG13_MET3RES +XA_I87 A_WCLK_L A_WCLK_R / RSC_IHPSG13_MET3RES +XA_I88 A_DCLK_L A_DCLK_R / RSC_IHPSG13_MET3RES +XA_I89 A_DCLK_B_L A_DCLK_B_R / RSC_IHPSG13_MET3RES +XA_I90 A_WCLK_B_L A_WCLK_B_R / RSC_IHPSG13_MET3RES +XA_I91 A_RCLK_B_L A_RCLK_B_R / RSC_IHPSG13_MET3RES +XB_R2 B_RCLK_L B_RCLK_R / RSC_IHPSG13_MET3RES +XB_I87 B_WCLK_L B_WCLK_R / RSC_IHPSG13_MET3RES +XB_I88 B_DCLK_L B_DCLK_R / RSC_IHPSG13_MET3RES +XB_I89 B_DCLK_B_L B_DCLK_B_R / RSC_IHPSG13_MET3RES +XB_I90 B_WCLK_B_L B_WCLK_B_R / RSC_IHPSG13_MET3RES +XB_I91 B_RCLK_B_L B_RCLK_B_R / RSC_IHPSG13_MET3RES +XA_ISENSE A_SAE A_BLC_SEL A_BLT_SEL net19 net20 VDD VSS / ++ RSC_IHPSG13_DFPQD_MSAFFX2 +XB_ISENSE B_SAE B_BLC_SEL B_BLT_SEL net037 net038 VDD VSS / ++ RSC_IHPSG13_DFPQD_MSAFFX2 +XAB_BLMUX<3> A_BLC<15> A_BLC<14> A_BLC<13> A_BLC<12> A_BLC_SEL A_BLT<15> ++ A_BLT<14> A_BLT<13> A_BLT<12> A_BLT_SEL A_PRE_N A_SEL_P<15> A_SEL_P<14> ++ A_SEL_P<13> A_SEL_P<12> A_WR_ONE A_WR_ZERO B_BLC<15> B_BLC<14> B_BLC<13> ++ B_BLC<12> B_BLC_SEL B_BLT<15> B_BLT<14> B_BLT<13> B_BLT<12> B_BLT_SEL ++ B_PRE_N B_SEL_P<15> B_SEL_P<14> B_SEL_P<13> B_SEL_P<12> B_WR_ONE B_WR_ZERO ++ VDD VSS / RM_IHPSG13_512x16_c2_2P_BLDRV +XAB_BLMUX<2> A_BLC<11> A_BLC<10> A_BLC<9> A_BLC<8> A_BLC_SEL A_BLT<11> ++ A_BLT<10> A_BLT<9> A_BLT<8> A_BLT_SEL A_PRE_N A_SEL_P<11> A_SEL_P<10> ++ A_SEL_P<9> A_SEL_P<8> A_WR_ONE A_WR_ZERO B_BLC<11> B_BLC<10> B_BLC<9> ++ B_BLC<8> B_BLC_SEL B_BLT<11> B_BLT<10> B_BLT<9> B_BLT<8> B_BLT_SEL B_PRE_N ++ B_SEL_P<11> B_SEL_P<10> B_SEL_P<9> B_SEL_P<8> B_WR_ONE B_WR_ZERO VDD ++ VSS / RM_IHPSG13_512x16_c2_2P_BLDRV +XAB_BLMUX<1> A_BLC<7> A_BLC<6> A_BLC<5> A_BLC<4> A_BLC_SEL A_BLT<7> A_BLT<6> ++ A_BLT<5> A_BLT<4> A_BLT_SEL A_PRE_N A_SEL_P<7> A_SEL_P<6> A_SEL_P<5> ++ A_SEL_P<4> A_WR_ONE A_WR_ZERO B_BLC<7> B_BLC<6> B_BLC<5> B_BLC<4> B_BLC_SEL ++ B_BLT<7> B_BLT<6> B_BLT<5> B_BLT<4> B_BLT_SEL B_PRE_N B_SEL_P<7> B_SEL_P<6> ++ B_SEL_P<5> B_SEL_P<4> B_WR_ONE B_WR_ZERO VDD VSS / ++ RM_IHPSG13_512x16_c2_2P_BLDRV +XAB_BLMUX<0> A_BLC<3> A_BLC<2> A_BLC<1> A_BLC<0> A_BLC_SEL A_BLT<3> A_BLT<2> ++ A_BLT<1> A_BLT<0> A_BLT_SEL A_PRE_N A_SEL_P<3> A_SEL_P<2> A_SEL_P<1> ++ A_SEL_P<0> A_WR_ONE A_WR_ZERO B_BLC<3> B_BLC<2> B_BLC<1> B_BLC<0> B_BLC_SEL ++ B_BLT<3> B_BLT<2> B_BLT<1> B_BLT<0> B_BLT_SEL B_PRE_N B_SEL_P<3> B_SEL_P<2> ++ B_SEL_P<1> B_SEL_P<0> B_WR_ONE B_WR_ZERO VDD VSS / ++ RM_IHPSG13_512x16_c2_2P_BLDRV +XA_I51 net19 A_DR_O VDD VSS / RSC_IHPSG13_INVX4 +XB_I51 net037 B_DR_O VDD VSS / RSC_IHPSG13_INVX4 +XA_I78 A_RCLK_B_L A_SAE VDD VSS / RSC_IHPSG13_CBUFX2 +XB_I78 B_RCLK_B_L B_SAE VDD VSS / RSC_IHPSG13_CBUFX2 +XA_DREG A_BIST_EN_I A_BIST_DW_I A_DCLK_B_L A_DW_I A_DI_R net22 VDD VSS ++ / RSC_IHPSG13_DFNQMX2IX1 +XB_DREG B_BIST_EN_I B_BIST_DW_I B_DCLK_B_L B_DW_I B_DI_R net046 VDD ++ VSS / RSC_IHPSG13_DFNQMX2IX1 +XB_BREG B_BIST_EN_I B_BIST_BM_I B_DCLK_B_L B_BM_I B_BM_R net045 VDD ++ VSS / RSC_IHPSG13_DFNQMX2IX1 +XA_BREG A_BIST_EN_I A_BIST_BM_I A_DCLK_B_L A_BM_I A_BM_R net24 VDD VSS ++ / RSC_IHPSG13_DFNQMX2IX1 +XA_DEC3INV<15> net23<0> A_SEL_P<15> VDD VSS / RSC_IHPSG13_INVX2 +XA_DEC3INV<14> net23<1> A_SEL_P<14> VDD VSS / RSC_IHPSG13_INVX2 +XA_DEC3INV<13> net23<2> A_SEL_P<13> VDD VSS / RSC_IHPSG13_INVX2 +XA_DEC3INV<12> net23<3> A_SEL_P<12> VDD VSS / RSC_IHPSG13_INVX2 +XA_DEC3INV<11> net23<4> A_SEL_P<11> VDD VSS / RSC_IHPSG13_INVX2 +XA_DEC3INV<10> net23<5> A_SEL_P<10> VDD VSS / RSC_IHPSG13_INVX2 +XA_DEC3INV<9> net23<6> A_SEL_P<9> VDD VSS / RSC_IHPSG13_INVX2 +XA_DEC3INV<8> net23<7> A_SEL_P<8> VDD VSS / RSC_IHPSG13_INVX2 +XA_DEC3INV<7> net23<8> A_SEL_P<7> VDD VSS / RSC_IHPSG13_INVX2 +XA_DEC3INV<6> net23<9> A_SEL_P<6> VDD VSS / RSC_IHPSG13_INVX2 +XA_DEC3INV<5> net23<10> A_SEL_P<5> VDD VSS / RSC_IHPSG13_INVX2 +XA_DEC3INV<4> net23<11> A_SEL_P<4> VDD VSS / RSC_IHPSG13_INVX2 +XA_DEC3INV<3> net23<12> A_SEL_P<3> VDD VSS / RSC_IHPSG13_INVX2 +XA_DEC3INV<2> net23<13> A_SEL_P<2> VDD VSS / RSC_IHPSG13_INVX2 +XA_DEC3INV<1> net23<14> A_SEL_P<1> VDD VSS / RSC_IHPSG13_INVX2 +XA_DEC3INV<0> net23<15> A_SEL_P<0> VDD VSS / RSC_IHPSG13_INVX2 +XA_I83 A_BM_R A_BM_N VDD VSS / RSC_IHPSG13_INVX2 +XA_I49 A_DI_R A_DI_N VDD VSS / RSC_IHPSG13_INVX2 +XB_DEC3INV<15> net044<0> B_SEL_P<15> VDD VSS / RSC_IHPSG13_INVX2 +XB_DEC3INV<14> net044<1> B_SEL_P<14> VDD VSS / RSC_IHPSG13_INVX2 +XB_DEC3INV<13> net044<2> B_SEL_P<13> VDD VSS / RSC_IHPSG13_INVX2 +XB_DEC3INV<12> net044<3> B_SEL_P<12> VDD VSS / RSC_IHPSG13_INVX2 +XB_DEC3INV<11> net044<4> B_SEL_P<11> VDD VSS / RSC_IHPSG13_INVX2 +XB_DEC3INV<10> net044<5> B_SEL_P<10> VDD VSS / RSC_IHPSG13_INVX2 +XB_DEC3INV<9> net044<6> B_SEL_P<9> VDD VSS / RSC_IHPSG13_INVX2 +XB_DEC3INV<8> net044<7> B_SEL_P<8> VDD VSS / RSC_IHPSG13_INVX2 +XB_DEC3INV<7> net044<8> B_SEL_P<7> VDD VSS / RSC_IHPSG13_INVX2 +XB_DEC3INV<6> net044<9> B_SEL_P<6> VDD VSS / RSC_IHPSG13_INVX2 +XB_DEC3INV<5> net044<10> B_SEL_P<5> VDD VSS / RSC_IHPSG13_INVX2 +XB_DEC3INV<4> net044<11> B_SEL_P<4> VDD VSS / RSC_IHPSG13_INVX2 +XB_DEC3INV<3> net044<12> B_SEL_P<3> VDD VSS / RSC_IHPSG13_INVX2 +XB_DEC3INV<2> net044<13> B_SEL_P<2> VDD VSS / RSC_IHPSG13_INVX2 +XB_DEC3INV<1> net044<14> B_SEL_P<1> VDD VSS / RSC_IHPSG13_INVX2 +XB_DEC3INV<0> net044<15> B_SEL_P<0> VDD VSS / RSC_IHPSG13_INVX2 +XB_I83 B_BM_R B_BM_N VDD VSS / RSC_IHPSG13_INVX2 +XB_I49 B_DI_R B_DI_N VDD VSS / RSC_IHPSG13_INVX2 +XI_FILL8<20> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI_FILL8<19> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI_FILL8<18> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI_FILL8<17> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI_FILL8<16> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI_FILL8<15> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI_FILL8<14> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI_FILL8<13> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI_FILL8<12> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI_FILL8<11> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI_FILL8<10> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI_FILL8<9> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI_FILL8<8> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI_FILL8<7> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI_FILL8<6> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI_FILL8<5> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI_FILL8<4> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI_FILL8<3> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI_FILL8<2> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI_FILL8<1> VDD VSS / RSC_IHPSG13_FILLCAP8 +XA_I44 A_BM_N A_WCLK_B_L A_DO_WRITE_P VDD VSS / RSC_IHPSG13_NOR2X2 +XB_I44 B_BM_N B_WCLK_B_L B_DO_WRITE_P VDD VSS / RSC_IHPSG13_NOR2X2 +XA_DEC3<15> A_P0 A_ADDR_DEC<7> net23<0> VDD VSS / RSC_IHPSG13_NAND2X2 +XA_DEC3<14> A_P0 A_ADDR_DEC<6> net23<1> VDD VSS / RSC_IHPSG13_NAND2X2 +XA_DEC3<13> A_P0 A_ADDR_DEC<5> net23<2> VDD VSS / RSC_IHPSG13_NAND2X2 +XA_DEC3<12> A_P0 A_ADDR_DEC<4> net23<3> VDD VSS / RSC_IHPSG13_NAND2X2 +XA_DEC3<11> A_P0 A_ADDR_DEC<3> net23<4> VDD VSS / RSC_IHPSG13_NAND2X2 +XA_DEC3<10> A_P0 A_ADDR_DEC<2> net23<5> VDD VSS / RSC_IHPSG13_NAND2X2 +XA_DEC3<9> A_P0 A_ADDR_DEC<1> net23<6> VDD VSS / RSC_IHPSG13_NAND2X2 +XA_DEC3<8> A_P0 A_ADDR_DEC<0> net23<7> VDD VSS / RSC_IHPSG13_NAND2X2 +XA_DEC3<7> A_N0 A_ADDR_DEC<7> net23<8> VDD VSS / RSC_IHPSG13_NAND2X2 +XA_DEC3<6> A_N0 A_ADDR_DEC<6> net23<9> VDD VSS / RSC_IHPSG13_NAND2X2 +XA_DEC3<5> A_N0 A_ADDR_DEC<5> net23<10> VDD VSS / RSC_IHPSG13_NAND2X2 +XA_DEC3<4> A_N0 A_ADDR_DEC<4> net23<11> VDD VSS / RSC_IHPSG13_NAND2X2 +XA_DEC3<3> A_N0 A_ADDR_DEC<3> net23<12> VDD VSS / RSC_IHPSG13_NAND2X2 +XA_DEC3<2> A_N0 A_ADDR_DEC<2> net23<13> VDD VSS / RSC_IHPSG13_NAND2X2 +XA_DEC3<1> A_N0 A_ADDR_DEC<1> net23<14> VDD VSS / RSC_IHPSG13_NAND2X2 +XA_DEC3<0> A_N0 A_ADDR_DEC<0> net23<15> VDD VSS / RSC_IHPSG13_NAND2X2 +XB_DEC3<15> B_P0 B_ADDR_DEC<7> net044<0> VDD VSS / RSC_IHPSG13_NAND2X2 +XB_DEC3<14> B_P0 B_ADDR_DEC<6> net044<1> VDD VSS / RSC_IHPSG13_NAND2X2 +XB_DEC3<13> B_P0 B_ADDR_DEC<5> net044<2> VDD VSS / RSC_IHPSG13_NAND2X2 +XB_DEC3<12> B_P0 B_ADDR_DEC<4> net044<3> VDD VSS / RSC_IHPSG13_NAND2X2 +XB_DEC3<11> B_P0 B_ADDR_DEC<3> net044<4> VDD VSS / RSC_IHPSG13_NAND2X2 +XB_DEC3<10> B_P0 B_ADDR_DEC<2> net044<5> VDD VSS / RSC_IHPSG13_NAND2X2 +XB_DEC3<9> B_P0 B_ADDR_DEC<1> net044<6> VDD VSS / RSC_IHPSG13_NAND2X2 +XB_DEC3<8> B_P0 B_ADDR_DEC<0> net044<7> VDD VSS / RSC_IHPSG13_NAND2X2 +XB_DEC3<7> B_N0 B_ADDR_DEC<7> net044<8> VDD VSS / RSC_IHPSG13_NAND2X2 +XB_DEC3<6> B_N0 B_ADDR_DEC<6> net044<9> VDD VSS / RSC_IHPSG13_NAND2X2 +XB_DEC3<5> B_N0 B_ADDR_DEC<5> net044<10> VDD VSS / RSC_IHPSG13_NAND2X2 +XB_DEC3<4> B_N0 B_ADDR_DEC<4> net044<11> VDD VSS / RSC_IHPSG13_NAND2X2 +XB_DEC3<3> B_N0 B_ADDR_DEC<3> net044<12> VDD VSS / RSC_IHPSG13_NAND2X2 +XB_DEC3<2> B_N0 B_ADDR_DEC<2> net044<13> VDD VSS / RSC_IHPSG13_NAND2X2 +XB_DEC3<1> B_N0 B_ADDR_DEC<1> net044<14> VDD VSS / RSC_IHPSG13_NAND2X2 +XB_DEC3<0> B_N0 B_ADDR_DEC<0> net044<15> VDD VSS / RSC_IHPSG13_NAND2X2 +XB_BM_TIEH B_TIEH_O VDD VSS / RSC_IHPSG13_TIEH +XA_BM_TIEH A_TIEH_O VDD VSS / RSC_IHPSG13_TIEH +.ENDS + + +.SUBCKT RM_IHPSG13_512x16_c2_2P_ROWDEC5 ADDR_N_I<4> ADDR_N_I<3> ADDR_N_I<2> ADDR_N_I<1> ++ ADDR_N_I<0> CS_I ECLK_I WL_O<31> WL_O<30> WL_O<29> WL_O<28> WL_O<27> ++ WL_O<26> WL_O<25> WL_O<24> WL_O<23> WL_O<22> WL_O<21> WL_O<20> WL_O<19> ++ WL_O<18> WL_O<17> WL_O<16> WL_O<15> WL_O<14> WL_O<13> WL_O<12> WL_O<11> ++ WL_O<10> WL_O<9> WL_O<8> WL_O<7> WL_O<6> WL_O<5> WL_O<4> WL_O<3> WL_O<2> ++ WL_O<1> WL_O<0> VDD VSS +XDEC00 ADDR_N_I<5> ADDR_N_I<4> CS_I CS00<0> VDD VSS / ++ RM_IHPSG13_512x16_c2_2P_DEC00 +XSEL<1> ADDR_N_I<3> ADDR_N_I<2> ADDR_N_I<1> ADDR_N_I<0> CS00<1> ECLK_H<1> ++ ECLK_H<2> ECLK_B<1> ECLK_B<2> WL_O<31> WL_O<30> WL_O<29> WL_O<28> WL_O<27> ++ WL_O<26> WL_O<25> WL_O<24> WL_O<23> WL_O<22> WL_O<21> WL_O<20> WL_O<19> ++ WL_O<18> WL_O<17> WL_O<16> VDD VSS / RM_IHPSG13_512x16_c2_2P_DEC04 +XSEL<0> ADDR_N_I<3> ADDR_N_I<2> ADDR_N_I<1> ADDR_N_I<0> CS00<0> ECLK_I ++ ECLK_H<1> ECLK_B<0> ECLK_B<1> WL_O<15> WL_O<14> WL_O<13> WL_O<12> WL_O<11> ++ WL_O<10> WL_O<9> WL_O<8> WL_O<7> WL_O<6> WL_O<5> WL_O<4> WL_O<3> WL_O<2> ++ WL_O<1> WL_O<0> VDD VSS / RM_IHPSG13_512x16_c2_2P_DEC04 +XDEC01 ADDR_N_I<5> ADDR_N_I<4> CS_I CS00<1> VDD VSS / ++ RM_IHPSG13_512x16_c2_2P_DEC01 +XL2<18> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<17> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<16> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<15> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<14> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<13> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<12> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<11> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<10> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<9> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<8> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<7> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<6> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<5> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<4> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<3> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<2> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<1> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI0 ADDR_N_I<5> VDD VSS / RSC_IHPSG13_TIEL +.ENDS +.SUBCKT RM_IHPSG13_512x16_c2_2P_ROWREG5 ACLK_N_I ADDR_I<4> ADDR_I<3> ADDR_I<2> ADDR_I<1> ++ ADDR_I<0> ADDR_N_O<4> ADDR_N_O<3> ADDR_N_O<2> ADDR_N_O<1> ADDR_N_O<0> ++ BIST_ADDR_I<4> BIST_ADDR_I<3> BIST_ADDR_I<2> BIST_ADDR_I<1> BIST_ADDR_I<0> ++ BIST_EN_I VDD VSS +XINV<4> q_int<4> qn_int<4> VDD VSS / RSC_IHPSG13_CINVX2 +XINV<3> q_int<3> qn_int<3> VDD VSS / RSC_IHPSG13_CINVX2 +XINV<2> q_int<2> qn_int<2> VDD VSS / RSC_IHPSG13_CINVX2 +XINV<1> q_int<1> qn_int<1> VDD VSS / RSC_IHPSG13_CINVX2 +XINV<0> q_int<0> qn_int<0> VDD VSS / RSC_IHPSG13_CINVX2 +XDRV<4> qn_int<4> ADDR_N_O<4> VDD VSS / RSC_IHPSG13_CINVX8 +XDRV<3> qn_int<3> ADDR_N_O<3> VDD VSS / RSC_IHPSG13_CINVX8 +XDRV<2> qn_int<2> ADDR_N_O<2> VDD VSS / RSC_IHPSG13_CINVX8 +XDRV<1> qn_int<1> ADDR_N_O<1> VDD VSS / RSC_IHPSG13_CINVX8 +XDRV<0> qn_int<0> ADDR_N_O<0> VDD VSS / RSC_IHPSG13_CINVX8 +XDFF<4> BIST_EN_I BIST_ADDR_I<4> ACLK_N_I ADDR_I<4> q_int<4> net2<0> VDD ++ VSS / RSC_IHPSG13_DFNQMX2IX1 +XDFF<3> BIST_EN_I BIST_ADDR_I<3> ACLK_N_I ADDR_I<3> q_int<3> net2<1> VDD ++ VSS / RSC_IHPSG13_DFNQMX2IX1 +XDFF<2> BIST_EN_I BIST_ADDR_I<2> ACLK_N_I ADDR_I<2> q_int<2> net2<2> VDD ++ VSS / RSC_IHPSG13_DFNQMX2IX1 +XDFF<1> BIST_EN_I BIST_ADDR_I<1> ACLK_N_I ADDR_I<1> q_int<1> net2<3> VDD ++ VSS / RSC_IHPSG13_DFNQMX2IX1 +XDFF<0> BIST_EN_I BIST_ADDR_I<0> ACLK_N_I ADDR_I<0> q_int<0> net2<4> VDD ++ VSS / RSC_IHPSG13_DFNQMX2IX1 +XI11<16> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI11<15> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI11<14> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI11<13> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI11<12> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI11<11> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI11<10> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI11<9> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI11<8> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI11<7> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI11<6> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI11<5> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI11<4> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI11<3> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI11<2> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI11<1> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI12<3> VDD VSS / RSC_IHPSG13_FILLCAP4 +XI12<2> VDD VSS / RSC_IHPSG13_FILLCAP4 +XI12<1> VDD VSS / RSC_IHPSG13_FILLCAP4 +XI12<0> VDD VSS / RSC_IHPSG13_FILLCAP4 +.ENDS + + +.SUBCKT RM_IHPSG13_512x16_c2_2P_COLDEC3 ACLK_N ADDR<2> ADDR<1> ADDR<0> ADDR_COL<1> ++ ADDR_COL<0> ADDR_DEC<7> ADDR_DEC<6> ADDR_DEC<5> ADDR_DEC<4> ADDR_DEC<3> ++ ADDR_DEC<2> ADDR_DEC<1> ADDR_DEC<0> BIST_ADDR<2> BIST_ADDR<1> BIST_ADDR<0> ++ BIST_EN_I VDD VSS +XI1<7> PADR<0> PADR<1> PADR<2> addr_n<7> VDD VSS / RSC_IHPSG13_NAND3X2 +XI1<6> NADR<0> PADR<1> PADR<2> addr_n<6> VDD VSS / RSC_IHPSG13_NAND3X2 +XI1<5> PADR<0> NADR<1> PADR<2> addr_n<5> VDD VSS / RSC_IHPSG13_NAND3X2 +XI1<4> NADR<0> NADR<1> PADR<2> addr_n<4> VDD VSS / RSC_IHPSG13_NAND3X2 +XI1<3> PADR<0> PADR<1> NADR<2> addr_n<3> VDD VSS / RSC_IHPSG13_NAND3X2 +XI1<2> NADR<0> PADR<1> NADR<2> addr_n<2> VDD VSS / RSC_IHPSG13_NAND3X2 +XI1<1> PADR<0> NADR<1> NADR<2> addr_n<1> VDD VSS / RSC_IHPSG13_NAND3X2 +XI1<0> NADR<0> NADR<1> NADR<2> addr_n<0> VDD VSS / RSC_IHPSG13_NAND3X2 +XDFF<2> BIST_EN_I BIST_ADDR<2> ACLK_N ADDR<2> padr_int<2> net13<0> VDD ++ VSS / RSC_IHPSG13_DFNQMX2IX1 +XDFF<1> BIST_EN_I BIST_ADDR<1> ACLK_N ADDR<1> padr_int<1> net13<1> VDD ++ VSS / RSC_IHPSG13_DFNQMX2IX1 +XDFF<0> BIST_EN_I BIST_ADDR<0> ACLK_N ADDR<0> padr_int<0> net13<2> VDD ++ VSS / RSC_IHPSG13_DFNQMX2IX1 +XI15<1> ADDR_COL<1> VDD VSS / RSC_IHPSG13_TIEL +XI15<0> ADDR_COL<0> VDD VSS / RSC_IHPSG13_TIEL +XI13<2> NADR<2> PADR<2> VDD VSS / RSC_IHPSG13_INVX2 +XI13<1> NADR<1> PADR<1> VDD VSS / RSC_IHPSG13_INVX2 +XI13<0> NADR<0> PADR<0> VDD VSS / RSC_IHPSG13_INVX2 +XI3<2> padr_int<2> NADR<2> VDD VSS / RSC_IHPSG13_INVX2 +XI3<1> padr_int<1> NADR<1> VDD VSS / RSC_IHPSG13_INVX2 +XI3<0> padr_int<0> NADR<0> VDD VSS / RSC_IHPSG13_INVX2 +XI2<7> addr_n<7> ADDR_DEC<7> VDD VSS / RSC_IHPSG13_INVX2 +XI2<6> addr_n<6> ADDR_DEC<6> VDD VSS / RSC_IHPSG13_INVX2 +XI2<5> addr_n<5> ADDR_DEC<5> VDD VSS / RSC_IHPSG13_INVX2 +XI2<4> addr_n<4> ADDR_DEC<4> VDD VSS / RSC_IHPSG13_INVX2 +XI2<3> addr_n<3> ADDR_DEC<3> VDD VSS / RSC_IHPSG13_INVX2 +XI2<2> addr_n<2> ADDR_DEC<2> VDD VSS / RSC_IHPSG13_INVX2 +XI2<1> addr_n<1> ADDR_DEC<1> VDD VSS / RSC_IHPSG13_INVX2 +XI2<0> addr_n<0> ADDR_DEC<0> VDD VSS / RSC_IHPSG13_INVX2 +XI17<4> VDD VSS / RSC_IHPSG13_FILLCAP4 +XI17<3> VDD VSS / RSC_IHPSG13_FILLCAP4 +XI17<2> VDD VSS / RSC_IHPSG13_FILLCAP4 +XI17<1> VDD VSS / RSC_IHPSG13_FILLCAP4 +XI16<11> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI16<10> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI16<9> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI16<8> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI16<7> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI16<6> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI16<5> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI16<4> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI16<3> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI16<2> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI16<1> VDD VSS / RSC_IHPSG13_FILLCAP8 +.ENDS +.SUBCKT RSC_IHPSG13_DFPQD_MSAFFX2P CP DN DP QN QP VDD VSS +XI_AMP CP DN DP QN QP VDD VSS / RSC_IHPSG13_DFPQD_MSAFFX2 +.ENDS +.SUBCKT RM_IHPSG13_512x16_c2_2P_COLCTRL3 A_ADDR_DEC<7> A_ADDR_DEC<6> A_ADDR_DEC<5> ++ A_ADDR_DEC<4> A_ADDR_DEC<3> A_ADDR_DEC<2> A_ADDR_DEC<1> A_ADDR_DEC<0> ++ A_BIST_BM_I A_BIST_DW_I A_BIST_EN_I A_BLC<7> A_BLC<6> A_BLC<5> A_BLC<4> ++ A_BLC<3> A_BLC<2> A_BLC<1> A_BLC<0> A_BLT<7> A_BLT<6> A_BLT<5> A_BLT<4> ++ A_BLT<3> A_BLT<2> A_BLT<1> A_BLT<0> A_BM_I A_DCLK_B_L A_DCLK_B_R A_DCLK_L ++ A_DCLK_R A_DR_O A_DW_I A_RCLK_B_L A_RCLK_B_R A_RCLK_L A_RCLK_R A_TIEH_O ++ A_WCLK_B_L A_WCLK_B_R A_WCLK_L A_WCLK_R B_ADDR_DEC<7> B_ADDR_DEC<6> ++ B_ADDR_DEC<5> B_ADDR_DEC<4> B_ADDR_DEC<3> B_ADDR_DEC<2> B_ADDR_DEC<1> ++ B_ADDR_DEC<0> B_BIST_BM_I B_BIST_DW_I B_BIST_EN_I B_BLC<7> B_BLC<6> B_BLC<5> ++ B_BLC<4> B_BLC<3> B_BLC<2> B_BLC<1> B_BLC<0> B_BLT<7> B_BLT<6> B_BLT<5> ++ B_BLT<4> B_BLT<3> B_BLT<2> B_BLT<1> B_BLT<0> B_BM_I B_DCLK_B_L B_DCLK_B_R ++ B_DCLK_L B_DCLK_R B_DR_O B_DW_I B_RCLK_B_L B_RCLK_B_R B_RCLK_L B_RCLK_R ++ B_TIEH_O B_WCLK_B_L B_WCLK_B_R B_WCLK_L B_WCLK_R VDD VSS +XB_DREG B_BIST_EN_I B_BIST_DW_I B_DCLK_B_L B_DW_I B_DI_R net044 VDD ++ VSS / RSC_IHPSG13_DFNQMX2IX1 +XB_BREG B_BIST_EN_I B_BIST_BM_I B_DCLK_B_L B_BM_I B_BM_R net043 VDD ++ VSS / RSC_IHPSG13_DFNQMX2IX1 +XA_DREG A_BIST_EN_I A_BIST_DW_I A_DCLK_B_L A_DW_I A_DI_R net22 VDD VSS ++ / RSC_IHPSG13_DFNQMX2IX1 +XA_BREG A_BIST_EN_I A_BIST_BM_I A_DCLK_B_L A_BM_I A_BM_R net23 VDD VSS ++ / RSC_IHPSG13_DFNQMX2IX1 +XI_FILL8<11> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI_FILL8<10> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI_FILL8<9> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI_FILL8<8> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI_FILL8<7> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI_FILL8<6> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI_FILL8<5> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI_FILL8<4> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI_FILL8<3> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI_FILL8<2> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI_FILL8<1> VDD VSS / RSC_IHPSG13_FILLCAP8 +XB_I51 net037 B_DR_O VDD VSS / RSC_IHPSG13_INVX4 +XA_I51 net19 A_DR_O VDD VSS / RSC_IHPSG13_INVX4 +XB_I44 B_BM_N B_WCLK_B_L B_DO_WRITE_P VDD VSS / RSC_IHPSG13_NOR2X2 +XA_I44 A_BM_N A_WCLK_B_L A_DO_WRITE_P VDD VSS / RSC_IHPSG13_NOR2X2 +XB_BM_TIEH B_TIEH_O VDD VSS / RSC_IHPSG13_TIEH +XA_BM_TIEH A_TIEH_O VDD VSS / RSC_IHPSG13_TIEH +XB_ISENSE B_SAE B_BLC_SEL B_BLT_SEL net037 net038 VDD VSS / ++ RSC_IHPSG13_DFPQD_MSAFFX2P +XA_ISENSE A_SAE A_BLC_SEL A_BLT_SEL net19 net20 VDD VSS / ++ RSC_IHPSG13_DFPQD_MSAFFX2P +XB_I49 B_DI_R B_DI_N VDD VSS / RSC_IHPSG13_INVX2 +XB_I83 B_BM_R B_BM_N VDD VSS / RSC_IHPSG13_INVX2 +XA_I49 A_DI_R A_DI_N VDD VSS / RSC_IHPSG13_INVX2 +XA_I83 A_BM_R A_BM_N VDD VSS / RSC_IHPSG13_INVX2 +XB_I69 B_DCLK_L B_DCLK_B_L VDD VSS / RSC_IHPSG13_CINVX2 +XB_I50 B_WCLK_L B_WCLK_B_L VDD VSS / RSC_IHPSG13_CINVX2 +XB_EBUF B_RCLK_L B_RCLK_B_L VDD VSS / RSC_IHPSG13_CINVX2 +XA_I69 A_DCLK_L A_DCLK_B_L VDD VSS / RSC_IHPSG13_CINVX2 +XA_I50 A_WCLK_L A_WCLK_B_L VDD VSS / RSC_IHPSG13_CINVX2 +XA_EBUF A_RCLK_L A_RCLK_B_L VDD VSS / RSC_IHPSG13_CINVX2 +XAB_BLMUX<1> A_BLC<7> A_BLC<6> A_BLC<5> A_BLC<4> A_BLC_SEL A_BLT<7> A_BLT<6> ++ A_BLT<5> A_BLT<4> A_BLT_SEL A_PRE_N A_ADDR_DEC<7> A_ADDR_DEC<6> ++ A_ADDR_DEC<5> A_ADDR_DEC<4> A_WR_ONE A_WR_ZERO B_BLC<7> B_BLC<6> B_BLC<5> ++ B_BLC<4> B_BLC_SEL B_BLT<7> B_BLT<6> B_BLT<5> B_BLT<4> B_BLT_SEL B_PRE_N ++ B_ADDR_DEC<7> B_ADDR_DEC<6> B_ADDR_DEC<5> B_ADDR_DEC<4> B_WR_ONE B_WR_ZERO ++ VDD VSS / RM_IHPSG13_512x16_c2_2P_BLDRV +XAB_BLMUX<0> A_BLC<3> A_BLC<2> A_BLC<1> A_BLC<0> A_BLC_SEL A_BLT<3> A_BLT<2> ++ A_BLT<1> A_BLT<0> A_BLT_SEL A_PRE_N A_ADDR_DEC<3> A_ADDR_DEC<2> ++ A_ADDR_DEC<1> A_ADDR_DEC<0> A_WR_ONE A_WR_ZERO B_BLC<3> B_BLC<2> B_BLC<1> ++ B_BLC<0> B_BLC_SEL B_BLT<3> B_BLT<2> B_BLT<1> B_BLT<0> B_BLT_SEL B_PRE_N ++ B_ADDR_DEC<3> B_ADDR_DEC<2> B_ADDR_DEC<1> B_ADDR_DEC<0> B_WR_ONE B_WR_ZERO ++ VDD VSS / RM_IHPSG13_512x16_c2_2P_BLDRV +XB_I78 B_RCLK_B_L B_SAE VDD VSS / RSC_IHPSG13_CBUFX2 +XA_I78 A_RCLK_B_L A_SAE VDD VSS / RSC_IHPSG13_CBUFX2 +XB_I88 B_DCLK_L B_DCLK_R / RSC_IHPSG13_MET3RES +XB_I87 B_WCLK_L B_WCLK_R / RSC_IHPSG13_MET3RES +XB_R2 B_RCLK_L B_RCLK_R / RSC_IHPSG13_MET3RES +XB_I91 B_RCLK_B_L B_RCLK_B_R / RSC_IHPSG13_MET3RES +XB_I90 B_WCLK_B_L B_WCLK_B_R / RSC_IHPSG13_MET3RES +XB_I89 B_DCLK_B_L B_DCLK_B_R / RSC_IHPSG13_MET3RES +XA_I88 A_DCLK_L A_DCLK_R / RSC_IHPSG13_MET3RES +XA_I87 A_WCLK_L A_WCLK_R / RSC_IHPSG13_MET3RES +XA_R2 A_RCLK_L A_RCLK_R / RSC_IHPSG13_MET3RES +XA_I91 A_RCLK_B_L A_RCLK_B_R / RSC_IHPSG13_MET3RES +XA_I90 A_WCLK_B_L A_WCLK_B_R / RSC_IHPSG13_MET3RES +XA_I89 A_DCLK_B_L A_DCLK_B_R / RSC_IHPSG13_MET3RES +XB_I80 B_WCLK_B_L B_RCLK_B_L net041 VDD VSS / RSC_IHPSG13_AND2X2 +XB_I76 B_DO_WRITE_P B_DI_N B_WR_ZERO VDD VSS / RSC_IHPSG13_AND2X2 +XB_I75 B_DO_WRITE_P B_DI_R B_WR_ONE VDD VSS / RSC_IHPSG13_AND2X2 +XA_I80 A_WCLK_B_L A_RCLK_B_L net21 VDD VSS / RSC_IHPSG13_AND2X2 +XA_I76 A_DI_N A_DO_WRITE_P A_WR_ZERO VDD VSS / RSC_IHPSG13_AND2X2 +XA_I75 A_DI_R A_DO_WRITE_P A_WR_ONE VDD VSS / RSC_IHPSG13_AND2X2 +XB_I81 net041 B_PRE_N VDD VSS / RSC_IHPSG13_CINVX4_WN +XA_I81 net21 A_PRE_N VDD VSS / RSC_IHPSG13_CINVX4_WN +XI_FILL4<10> VDD VSS / RSC_IHPSG13_FILLCAP4 +XI_FILL4<9> VDD VSS / RSC_IHPSG13_FILLCAP4 +XI_FILL4<8> VDD VSS / RSC_IHPSG13_FILLCAP4 +XI_FILL4<7> VDD VSS / RSC_IHPSG13_FILLCAP4 +XI_FILL4<6> VDD VSS / RSC_IHPSG13_FILLCAP4 +XI_FILL4<5> VDD VSS / RSC_IHPSG13_FILLCAP4 +XI_FILL4<4> VDD VSS / RSC_IHPSG13_FILLCAP4 +XI_FILL4<3> VDD VSS / RSC_IHPSG13_FILLCAP4 +XI_FILL4<2> VDD VSS / RSC_IHPSG13_FILLCAP4 +XI_FILL4<1> VDD VSS / RSC_IHPSG13_FILLCAP4 +.ENDS + +.SUBCKT RM_IHPSG13_512x16_c2_2P_ROWDEC6 ADDR_N_I<5> ADDR_N_I<4> ADDR_N_I<3> ADDR_N_I<2> ++ ADDR_N_I<1> ADDR_N_I<0> CS_I ECLK_I WL_O<63> WL_O<62> WL_O<61> WL_O<60> ++ WL_O<59> WL_O<58> WL_O<57> WL_O<56> WL_O<55> WL_O<54> WL_O<53> WL_O<52> ++ WL_O<51> WL_O<50> WL_O<49> WL_O<48> WL_O<47> WL_O<46> WL_O<45> WL_O<44> ++ WL_O<43> WL_O<42> WL_O<41> WL_O<40> WL_O<39> WL_O<38> WL_O<37> WL_O<36> ++ WL_O<35> WL_O<34> WL_O<33> WL_O<32> WL_O<31> WL_O<30> WL_O<29> WL_O<28> ++ WL_O<27> WL_O<26> WL_O<25> WL_O<24> WL_O<23> WL_O<22> WL_O<21> WL_O<20> ++ WL_O<19> WL_O<18> WL_O<17> WL_O<16> WL_O<15> WL_O<14> WL_O<13> WL_O<12> ++ WL_O<11> WL_O<10> WL_O<9> WL_O<8> WL_O<7> WL_O<6> WL_O<5> WL_O<4> WL_O<3> ++ WL_O<2> WL_O<1> WL_O<0> VDD VSS +XDEC10 ADDR_N_I<5> ADDR_N_I<4> CS_I CS00<2> VDD VSS / ++ RM_IHPSG13_512x16_c2_2P_DEC02 +XDEC00 ADDR_N_I<5> ADDR_N_I<4> CS_I CS00<0> VDD VSS / ++ RM_IHPSG13_512x16_c2_2P_DEC00 +XSEL<3> ADDR_N_I<3> ADDR_N_I<2> ADDR_N_I<1> ADDR_N_I<0> CS00<3> ECLK_H<3> ++ ECLK_H<4> ECLK_B<3> ECLK_B<4> WL_O<63> WL_O<62> WL_O<61> WL_O<60> WL_O<59> ++ WL_O<58> WL_O<57> WL_O<56> WL_O<55> WL_O<54> WL_O<53> WL_O<52> WL_O<51> ++ WL_O<50> WL_O<49> WL_O<48> VDD VSS / RM_IHPSG13_512x16_c2_2P_DEC04 +XSEL<2> ADDR_N_I<3> ADDR_N_I<2> ADDR_N_I<1> ADDR_N_I<0> CS00<2> ECLK_H<2> ++ ECLK_H<3> ECLK_B<2> ECLK_B<3> WL_O<47> WL_O<46> WL_O<45> WL_O<44> WL_O<43> ++ WL_O<42> WL_O<41> WL_O<40> WL_O<39> WL_O<38> WL_O<37> WL_O<36> WL_O<35> ++ WL_O<34> WL_O<33> WL_O<32> VDD VSS / RM_IHPSG13_512x16_c2_2P_DEC04 +XSEL<1> ADDR_N_I<3> ADDR_N_I<2> ADDR_N_I<1> ADDR_N_I<0> CS00<1> ECLK_H<1> ++ ECLK_H<2> ECLK_B<1> ECLK_B<2> WL_O<31> WL_O<30> WL_O<29> WL_O<28> WL_O<27> ++ WL_O<26> WL_O<25> WL_O<24> WL_O<23> WL_O<22> WL_O<21> WL_O<20> WL_O<19> ++ WL_O<18> WL_O<17> WL_O<16> VDD VSS / RM_IHPSG13_512x16_c2_2P_DEC04 +XSEL<0> ADDR_N_I<3> ADDR_N_I<2> ADDR_N_I<1> ADDR_N_I<0> CS00<0> ECLK_I ++ ECLK_H<1> ECLK_B<0> ECLK_B<1> WL_O<15> WL_O<14> WL_O<13> WL_O<12> WL_O<11> ++ WL_O<10> WL_O<9> WL_O<8> WL_O<7> WL_O<6> WL_O<5> WL_O<4> WL_O<3> WL_O<2> ++ WL_O<1> WL_O<0> VDD VSS / RM_IHPSG13_512x16_c2_2P_DEC04 +XDEC11 ADDR_N_I<5> ADDR_N_I<4> CS_I CS00<3> VDD VSS / ++ RM_IHPSG13_512x16_c2_2P_DEC03 +XL2<36> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<35> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<34> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<33> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<32> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<31> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<30> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<29> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<28> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<27> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<26> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<25> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<24> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<23> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<22> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<21> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<20> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<19> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<18> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<17> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<16> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<15> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<14> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<13> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<12> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<11> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<10> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<9> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<8> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<7> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<6> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<5> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<4> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<3> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<2> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<1> VDD VSS / RSC_IHPSG13_FILLCAP8 +XDEC01 ADDR_N_I<5> ADDR_N_I<4> CS_I CS00<1> VDD VSS / ++ RM_IHPSG13_512x16_c2_2P_DEC01 +.ENDS +.SUBCKT RM_IHPSG13_512x16_c2_2P_ROWREG6 ACLK_N_I ADDR_I<5> ADDR_I<4> ADDR_I<3> ADDR_I<2> ++ ADDR_I<1> ADDR_I<0> ADDR_N_O<5> ADDR_N_O<4> ADDR_N_O<3> ADDR_N_O<2> ++ ADDR_N_O<1> ADDR_N_O<0> BIST_ADDR_I<5> BIST_ADDR_I<4> BIST_ADDR_I<3> ++ BIST_ADDR_I<2> BIST_ADDR_I<1> BIST_ADDR_I<0> BIST_EN_I VDD VSS +XINV<5> q_int<5> qn_int<5> VDD VSS / RSC_IHPSG13_CINVX2 +XINV<4> q_int<4> qn_int<4> VDD VSS / RSC_IHPSG13_CINVX2 +XINV<3> q_int<3> qn_int<3> VDD VSS / RSC_IHPSG13_CINVX2 +XINV<2> q_int<2> qn_int<2> VDD VSS / RSC_IHPSG13_CINVX2 +XINV<1> q_int<1> qn_int<1> VDD VSS / RSC_IHPSG13_CINVX2 +XINV<0> q_int<0> qn_int<0> VDD VSS / RSC_IHPSG13_CINVX2 +XDRV<5> qn_int<5> ADDR_N_O<5> VDD VSS / RSC_IHPSG13_CINVX8 +XDRV<4> qn_int<4> ADDR_N_O<4> VDD VSS / RSC_IHPSG13_CINVX8 +XDRV<3> qn_int<3> ADDR_N_O<3> VDD VSS / RSC_IHPSG13_CINVX8 +XDRV<2> qn_int<2> ADDR_N_O<2> VDD VSS / RSC_IHPSG13_CINVX8 +XDRV<1> qn_int<1> ADDR_N_O<1> VDD VSS / RSC_IHPSG13_CINVX8 +XDRV<0> qn_int<0> ADDR_N_O<0> VDD VSS / RSC_IHPSG13_CINVX8 +XDFF<5> BIST_EN_I BIST_ADDR_I<5> ACLK_N_I ADDR_I<5> q_int<5> net2<0> VDD ++ VSS / RSC_IHPSG13_DFNQMX2IX1 +XDFF<4> BIST_EN_I BIST_ADDR_I<4> ACLK_N_I ADDR_I<4> q_int<4> net2<1> VDD ++ VSS / RSC_IHPSG13_DFNQMX2IX1 +XDFF<3> BIST_EN_I BIST_ADDR_I<3> ACLK_N_I ADDR_I<3> q_int<3> net2<2> VDD ++ VSS / RSC_IHPSG13_DFNQMX2IX1 +XDFF<2> BIST_EN_I BIST_ADDR_I<2> ACLK_N_I ADDR_I<2> q_int<2> net2<3> VDD ++ VSS / RSC_IHPSG13_DFNQMX2IX1 +XDFF<1> BIST_EN_I BIST_ADDR_I<1> ACLK_N_I ADDR_I<1> q_int<1> net2<4> VDD ++ VSS / RSC_IHPSG13_DFNQMX2IX1 +XDFF<0> BIST_EN_I BIST_ADDR_I<0> ACLK_N_I ADDR_I<0> q_int<0> net2<5> VDD ++ VSS / RSC_IHPSG13_DFNQMX2IX1 +XI11<12> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI11<11> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI11<10> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI11<9> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI11<8> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI11<7> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI11<6> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI11<5> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI11<4> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI11<3> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI11<2> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI11<1> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI12<2> VDD VSS / RSC_IHPSG13_FILLCAP4 +XI12<1> VDD VSS / RSC_IHPSG13_FILLCAP4 +XI12<0> VDD VSS / RSC_IHPSG13_FILLCAP4 +.ENDS + +.SUBCKT RM_IHPSG13_512x16_c2_2P_COLDRV13X16 ADDR_COL_I<1> ADDR_COL_I<0> ADDR_COL_O<1> ++ ADDR_COL_O<0> ADDR_DEC_I<7> ADDR_DEC_I<6> ADDR_DEC_I<5> ADDR_DEC_I<4> ++ ADDR_DEC_I<3> ADDR_DEC_I<2> ADDR_DEC_I<1> ADDR_DEC_I<0> ADDR_DEC_O<7> ++ ADDR_DEC_O<6> ADDR_DEC_O<5> ADDR_DEC_O<4> ADDR_DEC_O<3> ADDR_DEC_O<2> ++ ADDR_DEC_O<1> ADDR_DEC_O<0> DCLK_I DCLK_O RCLK_I RCLK_O WCLK_I WCLK_O ++ VDD VSS +XI0<7> VDD VSS / RSC_IHPSG13_FILLCAP4 +XI0<6> VDD VSS / RSC_IHPSG13_FILLCAP4 +XI0<5> VDD VSS / RSC_IHPSG13_FILLCAP4 +XI0<4> VDD VSS / RSC_IHPSG13_FILLCAP4 +XI0<3> VDD VSS / RSC_IHPSG13_FILLCAP4 +XI0<2> VDD VSS / RSC_IHPSG13_FILLCAP4 +XI0<1> VDD VSS / RSC_IHPSG13_FILLCAP4 +XWCLK_DRV WCLK_I WCLK_O VDD VSS / RSC_IHPSG13_CBUFX16 +XRCLK_DRV RCLK_I RCLK_O VDD VSS / RSC_IHPSG13_CBUFX16 +XDCLK_DRV DCLK_I DCLK_O VDD VSS / RSC_IHPSG13_CBUFX16 +XADDR_COL_DRV<1> ADDR_COL_I<1> ADDR_COL_O<1> VDD VSS / ++ RSC_IHPSG13_CBUFX16 +XADDR_COL_DRV<0> ADDR_COL_I<0> ADDR_COL_O<0> VDD VSS / ++ RSC_IHPSG13_CBUFX16 +XADDR_DEC_DRV<7> ADDR_DEC_I<7> ADDR_DEC_O<7> VDD VSS / ++ RSC_IHPSG13_CBUFX16 +XADDR_DEC_DRV<6> ADDR_DEC_I<6> ADDR_DEC_O<6> VDD VSS / ++ RSC_IHPSG13_CBUFX16 +XADDR_DEC_DRV<5> ADDR_DEC_I<5> ADDR_DEC_O<5> VDD VSS / ++ RSC_IHPSG13_CBUFX16 +XADDR_DEC_DRV<4> ADDR_DEC_I<4> ADDR_DEC_O<4> VDD VSS / ++ RSC_IHPSG13_CBUFX16 +XADDR_DEC_DRV<3> ADDR_DEC_I<3> ADDR_DEC_O<3> VDD VSS / ++ RSC_IHPSG13_CBUFX16 +XADDR_DEC_DRV<2> ADDR_DEC_I<2> ADDR_DEC_O<2> VDD VSS / ++ RSC_IHPSG13_CBUFX16 +XADDR_DEC_DRV<1> ADDR_DEC_I<1> ADDR_DEC_O<1> VDD VSS / ++ RSC_IHPSG13_CBUFX16 +XADDR_DEC_DRV<0> ADDR_DEC_I<0> ADDR_DEC_O<0> VDD VSS / ++ RSC_IHPSG13_CBUFX16 +XI1<5> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI1<4> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI1<3> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI1<2> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI1<1> VDD VSS / RSC_IHPSG13_FILLCAP8 +.ENDS +.SUBCKT RM_IHPSG13_512x16_c2_2P_WLDRV16X16 A<15> A<14> A<13> A<12> A<11> A<10> A<9> A<8> ++ A<7> A<6> A<5> A<4> A<3> A<2> A<1> A<0> Z<15> Z<14> Z<13> Z<12> Z<11> Z<10> ++ Z<9> Z<8> Z<7> Z<6> Z<5> Z<4> Z<3> Z<2> Z<1> Z<0> VDD VSS +XBUF<15> A<15> Z<15> VDD VSS / RSC_IHPSG13_WLDRVX16 +XBUF<14> A<14> Z<14> VDD VSS / RSC_IHPSG13_WLDRVX16 +XBUF<13> A<13> Z<13> VDD VSS / RSC_IHPSG13_WLDRVX16 +XBUF<12> A<12> Z<12> VDD VSS / RSC_IHPSG13_WLDRVX16 +XBUF<11> A<11> Z<11> VDD VSS / RSC_IHPSG13_WLDRVX16 +XBUF<10> A<10> Z<10> VDD VSS / RSC_IHPSG13_WLDRVX16 +XBUF<9> A<9> Z<9> VDD VSS / RSC_IHPSG13_WLDRVX16 +XBUF<8> A<8> Z<8> VDD VSS / RSC_IHPSG13_WLDRVX16 +XBUF<7> A<7> Z<7> VDD VSS / RSC_IHPSG13_WLDRVX16 +XBUF<6> A<6> Z<6> VDD VSS / RSC_IHPSG13_WLDRVX16 +XBUF<5> A<5> Z<5> VDD VSS / RSC_IHPSG13_WLDRVX16 +XBUF<4> A<4> Z<4> VDD VSS / RSC_IHPSG13_WLDRVX16 +XBUF<3> A<3> Z<3> VDD VSS / RSC_IHPSG13_WLDRVX16 +XBUF<2> A<2> Z<2> VDD VSS / RSC_IHPSG13_WLDRVX16 +XBUF<1> A<1> Z<1> VDD VSS / RSC_IHPSG13_WLDRVX16 +XBUF<0> A<0> Z<0> VDD VSS / RSC_IHPSG13_WLDRVX16 +.ENDS + + +.SUBCKT RM_IHPSG13_512x16_c2_1P_DEC01 ADDR<1> ADDR<0> CS CS_OUT VDD VSS +XDECINV net1 CS_OUT VDD VSS / RSC_IHPSG13_INVX4 +XDEC NADDR<1> ADDR<0> CS net1 VDD VSS / RSC_IHPSG13_NAND3X2 +XI2 VDD VSS / RSC_IHPSG13_FILLCAP4 +XADDRINV ADDR<1> NADDR<1> VDD VSS / RSC_IHPSG13_INVX2 +.ENDS +.SUBCKT RM_IHPSG13_512x16_c2_1P_DEC00 ADDR<1> ADDR<0> CS CS_OUT VDD VSS +XDECINV net1 CS_OUT VDD VSS / RSC_IHPSG13_INVX4 +XDEC NADDR<1> NADDR<0> CS net1 VDD VSS / RSC_IHPSG13_NAND3X2 +XADDRINV<1> ADDR<1> NADDR<1> VDD VSS / RSC_IHPSG13_INVX2 +XADDRINV<0> ADDR<0> NADDR<0> VDD VSS / RSC_IHPSG13_INVX2 +XI1 VDD VSS / RSC_IHPSG13_FILLCAP4 +.ENDS +.SUBCKT RM_IHPSG13_512x16_c2_1P_ROWDEC5 ADDR_N_I<4> ADDR_N_I<3> ADDR_N_I<2> ADDR_N_I<1> ++ ADDR_N_I<0> CS_I ECLK_I WL_O<31> WL_O<30> WL_O<29> WL_O<28> WL_O<27> ++ WL_O<26> WL_O<25> WL_O<24> WL_O<23> WL_O<22> WL_O<21> WL_O<20> WL_O<19> ++ WL_O<18> WL_O<17> WL_O<16> WL_O<15> WL_O<14> WL_O<13> WL_O<12> WL_O<11> ++ WL_O<10> WL_O<9> WL_O<8> WL_O<7> WL_O<6> WL_O<5> WL_O<4> WL_O<3> WL_O<2> ++ WL_O<1> WL_O<0> VDD VSS +XL2<12> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<11> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<10> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<9> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<8> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<7> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<6> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<5> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<4> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<3> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<2> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<1> VDD VSS / RSC_IHPSG13_FILLCAP8 +XDEC01 ADDR_N_I<5> ADDR_N_I<4> CS_I CS00<1> VDD VSS / ++ RM_IHPSG13_512x16_c2_1P_DEC01 +XDEC00 ADDR_N_I<5> ADDR_N_I<4> CS_I CS00<0> VDD VSS / ++ RM_IHPSG13_512x16_c2_1P_DEC00 +XSEL<1> ADDR_N_I<3> ADDR_N_I<2> ADDR_N_I<1> ADDR_N_I<0> CS00<1> ECLK_H<1> ++ ECLK_H<2> ECLK_B<1> ECLK_B<2> WL_O<31> WL_O<30> WL_O<29> WL_O<28> WL_O<27> ++ WL_O<26> WL_O<25> WL_O<24> WL_O<23> WL_O<22> WL_O<21> WL_O<20> WL_O<19> ++ WL_O<18> WL_O<17> WL_O<16> VDD VSS / RM_IHPSG13_512x16_c2_1P_DEC04 +XSEL<0> ADDR_N_I<3> ADDR_N_I<2> ADDR_N_I<1> ADDR_N_I<0> CS00<0> ECLK_I ++ ECLK_H<1> ECLK_B<0> ECLK_B<1> WL_O<15> WL_O<14> WL_O<13> WL_O<12> WL_O<11> ++ WL_O<10> WL_O<9> WL_O<8> WL_O<7> WL_O<6> WL_O<5> WL_O<4> WL_O<3> WL_O<2> ++ WL_O<1> WL_O<0> VDD VSS / RM_IHPSG13_512x16_c2_1P_DEC04 +XI0 ADDR_N_I<5> VDD VSS / RSC_IHPSG13_TIEL +.ENDS +.SUBCKT RM_IHPSG13_512x16_c2_1P_ROWREG5 ACLK_N_I ADDR_I<4> ADDR_I<3> ADDR_I<2> ADDR_I<1> ++ ADDR_I<0> ADDR_N_O<4> ADDR_N_O<3> ADDR_N_O<2> ADDR_N_O<1> ADDR_N_O<0> ++ BIST_ADDR_I<4> BIST_ADDR_I<3> BIST_ADDR_I<2> BIST_ADDR_I<1> BIST_ADDR_I<0> ++ BIST_EN_I VDD VSS +XINV<4> q_int<4> qn_int<4> VDD VSS / RSC_IHPSG13_CINVX2 +XINV<3> q_int<3> qn_int<3> VDD VSS / RSC_IHPSG13_CINVX2 +XINV<2> q_int<2> qn_int<2> VDD VSS / RSC_IHPSG13_CINVX2 +XINV<1> q_int<1> qn_int<1> VDD VSS / RSC_IHPSG13_CINVX2 +XINV<0> q_int<0> qn_int<0> VDD VSS / RSC_IHPSG13_CINVX2 +XDRV<4> qn_int<4> ADDR_N_O<4> VDD VSS / RSC_IHPSG13_CINVX8 +XDRV<3> qn_int<3> ADDR_N_O<3> VDD VSS / RSC_IHPSG13_CINVX8 +XDRV<2> qn_int<2> ADDR_N_O<2> VDD VSS / RSC_IHPSG13_CINVX8 +XDRV<1> qn_int<1> ADDR_N_O<1> VDD VSS / RSC_IHPSG13_CINVX8 +XDRV<0> qn_int<0> ADDR_N_O<0> VDD VSS / RSC_IHPSG13_CINVX8 +XDFF<4> BIST_EN_I BIST_ADDR_I<4> ACLK_N_I ADDR_I<4> q_int<4> net2<0> VDD ++ VSS / RSC_IHPSG13_DFNQMX2IX1 +XDFF<3> BIST_EN_I BIST_ADDR_I<3> ACLK_N_I ADDR_I<3> q_int<3> net2<1> VDD ++ VSS / RSC_IHPSG13_DFNQMX2IX1 +XDFF<2> BIST_EN_I BIST_ADDR_I<2> ACLK_N_I ADDR_I<2> q_int<2> net2<2> VDD ++ VSS / RSC_IHPSG13_DFNQMX2IX1 +XDFF<1> BIST_EN_I BIST_ADDR_I<1> ACLK_N_I ADDR_I<1> q_int<1> net2<3> VDD ++ VSS / RSC_IHPSG13_DFNQMX2IX1 +XDFF<0> BIST_EN_I BIST_ADDR_I<0> ACLK_N_I ADDR_I<0> q_int<0> net2<4> VDD ++ VSS / RSC_IHPSG13_DFNQMX2IX1 +XI11<16> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI11<15> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI11<14> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI11<13> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI11<12> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI11<11> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI11<10> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI11<9> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI11<8> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI11<7> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI11<6> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI11<5> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI11<4> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI11<3> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI11<2> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI11<1> VDD VSS / RSC_IHPSG13_FILLCAP8 +.ENDS + + +.SUBCKT RM_IHPSG13_512x16_c2_1P_COLDEC5 ACLK_N ADDR<4> ADDR<3> ADDR<2> ADDR<1> ADDR<0> ++ ADDR_COL<1> ADDR_COL<0> ADDR_DEC<7> ADDR_DEC<6> ADDR_DEC<5> ADDR_DEC<4> ++ ADDR_DEC<3> ADDR_DEC<2> ADDR_DEC<1> ADDR_DEC<0> BIST_ADDR<4> BIST_ADDR<3> ++ BIST_ADDR<2> BIST_ADDR<1> BIST_ADDR<0> BIST_EN_I VDD VSS +XI17<2> VDD VSS / RSC_IHPSG13_FILLCAP4 +XI17<1> VDD VSS / RSC_IHPSG13_FILLCAP4 +XI13<1> addr_int<1> ADDR_COL<1> VDD VSS / RSC_IHPSG13_CBUFX2 +XI13<0> addr_int<0> ADDR_COL<0> VDD VSS / RSC_IHPSG13_CBUFX2 +XDFF<4> BIST_EN_I BIST_ADDR<4> ACLK_N ADDR<4> addr_int<1> net7<0> VDD ++ VSS / RSC_IHPSG13_DFNQMX2IX1 +XDFF<3> BIST_EN_I BIST_ADDR<3> ACLK_N ADDR<3> addr_int<0> net7<1> VDD ++ VSS / RSC_IHPSG13_DFNQMX2IX1 +XDFF<2> BIST_EN_I BIST_ADDR<2> ACLK_N ADDR<2> padr_int<2> net7<2> VDD ++ VSS / RSC_IHPSG13_DFNQMX2IX1 +XDFF<1> BIST_EN_I BIST_ADDR<1> ACLK_N ADDR<1> padr_int<1> net7<3> VDD ++ VSS / RSC_IHPSG13_DFNQMX2IX1 +XDFF<0> BIST_EN_I BIST_ADDR<0> ACLK_N ADDR<0> padr_int<0> net7<4> VDD ++ VSS / RSC_IHPSG13_DFNQMX2IX1 +XI1<7> PADR<0> PADR<1> PADR<2> addr_n<7> VDD VSS / RSC_IHPSG13_NAND3X2 +XI1<6> NADR<0> PADR<1> PADR<2> addr_n<6> VDD VSS / RSC_IHPSG13_NAND3X2 +XI1<5> PADR<0> NADR<1> PADR<2> addr_n<5> VDD VSS / RSC_IHPSG13_NAND3X2 +XI1<4> NADR<0> NADR<1> PADR<2> addr_n<4> VDD VSS / RSC_IHPSG13_NAND3X2 +XI1<3> PADR<0> PADR<1> NADR<2> addr_n<3> VDD VSS / RSC_IHPSG13_NAND3X2 +XI1<2> NADR<0> PADR<1> NADR<2> addr_n<2> VDD VSS / RSC_IHPSG13_NAND3X2 +XI1<1> PADR<0> NADR<1> NADR<2> addr_n<1> VDD VSS / RSC_IHPSG13_NAND3X2 +XI1<0> NADR<0> NADR<1> NADR<2> addr_n<0> VDD VSS / RSC_IHPSG13_NAND3X2 +XI15<2> NADR<2> PADR<2> VDD VSS / RSC_IHPSG13_INVX2 +XI15<1> NADR<1> PADR<1> VDD VSS / RSC_IHPSG13_INVX2 +XI15<0> NADR<0> PADR<0> VDD VSS / RSC_IHPSG13_INVX2 +XI3<2> padr_int<2> NADR<2> VDD VSS / RSC_IHPSG13_INVX2 +XI3<1> padr_int<1> NADR<1> VDD VSS / RSC_IHPSG13_INVX2 +XI3<0> padr_int<0> NADR<0> VDD VSS / RSC_IHPSG13_INVX2 +XI2<7> addr_n<7> ADDR_DEC<7> VDD VSS / RSC_IHPSG13_INVX2 +XI2<6> addr_n<6> ADDR_DEC<6> VDD VSS / RSC_IHPSG13_INVX2 +XI2<5> addr_n<5> ADDR_DEC<5> VDD VSS / RSC_IHPSG13_INVX2 +XI2<4> addr_n<4> ADDR_DEC<4> VDD VSS / RSC_IHPSG13_INVX2 +XI2<3> addr_n<3> ADDR_DEC<3> VDD VSS / RSC_IHPSG13_INVX2 +XI2<2> addr_n<2> ADDR_DEC<2> VDD VSS / RSC_IHPSG13_INVX2 +XI2<1> addr_n<1> ADDR_DEC<1> VDD VSS / RSC_IHPSG13_INVX2 +XI2<0> addr_n<0> ADDR_DEC<0> VDD VSS / RSC_IHPSG13_INVX2 +.ENDS +.SUBCKT RM_IHPSG13_512x16_c2_1P_COLCTRL5 A_ADDR_COL<1> A_ADDR_COL<0> A_ADDR_DEC<7> ++ A_ADDR_DEC<6> A_ADDR_DEC<5> A_ADDR_DEC<4> A_ADDR_DEC<3> A_ADDR_DEC<2> ++ A_ADDR_DEC<1> A_ADDR_DEC<0> A_BIST_BM_I A_BIST_DW_I A_BIST_EN_I A_BLC<31> ++ A_BLC<30> A_BLC<29> A_BLC<28> A_BLC<27> A_BLC<26> A_BLC<25> A_BLC<24> ++ A_BLC<23> A_BLC<22> A_BLC<21> A_BLC<20> A_BLC<19> A_BLC<18> A_BLC<17> ++ A_BLC<16> A_BLC<15> A_BLC<14> A_BLC<13> A_BLC<12> A_BLC<11> A_BLC<10> ++ A_BLC<9> A_BLC<8> A_BLC<7> A_BLC<6> A_BLC<5> A_BLC<4> A_BLC<3> A_BLC<2> ++ A_BLC<1> A_BLC<0> A_BLT<31> A_BLT<30> A_BLT<29> A_BLT<28> A_BLT<27> ++ A_BLT<26> A_BLT<25> A_BLT<24> A_BLT<23> A_BLT<22> A_BLT<21> A_BLT<20> ++ A_BLT<19> A_BLT<18> A_BLT<17> A_BLT<16> A_BLT<15> A_BLT<14> A_BLT<13> ++ A_BLT<12> A_BLT<11> A_BLT<10> A_BLT<9> A_BLT<8> A_BLT<7> A_BLT<6> A_BLT<5> ++ A_BLT<4> A_BLT<3> A_BLT<2> A_BLT<1> A_BLT<0> A_BM_I A_DCLK_B_L A_DCLK_B_R ++ A_DCLK_L A_DCLK_R A_DR_O A_DW_I A_RCLK_B_L A_RCLK_B_R A_RCLK_L A_RCLK_R ++ A_TIEH_O A_WCLK_B_L A_WCLK_B_R A_WCLK_L A_WCLK_R VDD VSS +XA_I80<1> A_WCLK_B_L A_RCLK_B_L A_W_nor_R<1> VDD VSS / ++ RSC_IHPSG13_AND2X2 +XA_I80<0> A_WCLK_B_L A_RCLK_B_L A_W_nor_R<0> VDD VSS / ++ RSC_IHPSG13_AND2X2 +XA_I44 A_BM_N A_WCLK_B_L A_DO_WRITE_P VDD VSS / RSC_IHPSG13_NOR2X2 +XI80<29> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI80<28> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI80<27> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI80<26> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI80<25> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI80<24> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI80<23> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI80<22> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI80<21> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI80<20> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI80<19> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI80<18> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI80<17> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI80<16> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI80<15> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI80<14> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI80<13> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI80<12> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI80<11> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI80<10> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI80<9> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI80<8> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI80<7> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI80<6> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI80<5> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI80<4> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI80<3> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI80<2> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI80<1> VDD VSS / RSC_IHPSG13_FILLCAP8 +XA_I74<16> VDD VSS / RSC_IHPSG13_FILLCAP8 +XA_I74<15> VDD VSS / RSC_IHPSG13_FILLCAP8 +XA_I74<14> VDD VSS / RSC_IHPSG13_FILLCAP8 +XA_I74<13> VDD VSS / RSC_IHPSG13_FILLCAP8 +XA_I74<12> VDD VSS / RSC_IHPSG13_FILLCAP8 +XA_I74<11> VDD VSS / RSC_IHPSG13_FILLCAP8 +XA_I74<10> VDD VSS / RSC_IHPSG13_FILLCAP8 +XA_I74<9> VDD VSS / RSC_IHPSG13_FILLCAP8 +XA_I74<8> VDD VSS / RSC_IHPSG13_FILLCAP8 +XA_I74<7> VDD VSS / RSC_IHPSG13_FILLCAP8 +XA_I74<6> VDD VSS / RSC_IHPSG13_FILLCAP8 +XA_I74<5> VDD VSS / RSC_IHPSG13_FILLCAP8 +XA_I74<4> VDD VSS / RSC_IHPSG13_FILLCAP8 +XA_I74<3> VDD VSS / RSC_IHPSG13_FILLCAP8 +XA_I74<2> VDD VSS / RSC_IHPSG13_FILLCAP8 +XA_I74<1> VDD VSS / RSC_IHPSG13_FILLCAP8 +XA_INV<6> A_N1<1> A_P1<1> VDD VSS / RSC_IHPSG13_CINVX4 +XA_INV<5> A_N0<1> A_P0<1> VDD VSS / RSC_IHPSG13_CINVX4 +XA_INV<4> A_N0<0> A_P0<0> VDD VSS / RSC_IHPSG13_CINVX4 +XA_INV<3> A_ADDR_COL<1> A_N1<1> VDD VSS / RSC_IHPSG13_CINVX4 +XA_INV<2> A_ADDR_COL<1> A_N1<0> VDD VSS / RSC_IHPSG13_CINVX4 +XA_INV<1> A_ADDR_COL<0> A_N0<1> VDD VSS / RSC_IHPSG13_CINVX4 +XA_INV<0> A_ADDR_COL<0> A_N0<0> VDD VSS / RSC_IHPSG13_CINVX4 +XA_I81<3> A_W_nor_R<1> A_PRE_N VDD VSS / RSC_IHPSG13_CINVX4_WN +XA_I81<2> A_W_nor_R<1> A_PRE_N VDD VSS / RSC_IHPSG13_CINVX4_WN +XA_I81<1> A_W_nor_R<0> A_PRE_N VDD VSS / RSC_IHPSG13_CINVX4_WN +XA_I81<0> A_W_nor_R<0> A_PRE_N VDD VSS / RSC_IHPSG13_CINVX4_WN +XA_BLTMUX<31> A_BLC<31> A_BLC_SEL A_BLT<31> A_BLT_SEL A_PRE_N A_SEL_P<31> ++ A_WR_ONE A_WR_ZERO VDD VSS / RM_IHPSG13_512x16_c2_1P_BLDRV +XA_BLTMUX<30> A_BLC<30> A_BLC_SEL A_BLT<30> A_BLT_SEL A_PRE_N A_SEL_P<30> ++ A_WR_ONE A_WR_ZERO VDD VSS / RM_IHPSG13_512x16_c2_1P_BLDRV +XA_BLTMUX<29> A_BLC<29> A_BLC_SEL A_BLT<29> A_BLT_SEL A_PRE_N A_SEL_P<29> ++ A_WR_ONE A_WR_ZERO VDD VSS / RM_IHPSG13_512x16_c2_1P_BLDRV +XA_BLTMUX<28> A_BLC<28> A_BLC_SEL A_BLT<28> A_BLT_SEL A_PRE_N A_SEL_P<28> ++ A_WR_ONE A_WR_ZERO VDD VSS / RM_IHPSG13_512x16_c2_1P_BLDRV +XA_BLTMUX<27> A_BLC<27> A_BLC_SEL A_BLT<27> A_BLT_SEL A_PRE_N A_SEL_P<27> ++ A_WR_ONE A_WR_ZERO VDD VSS / RM_IHPSG13_512x16_c2_1P_BLDRV +XA_BLTMUX<26> A_BLC<26> A_BLC_SEL A_BLT<26> A_BLT_SEL A_PRE_N A_SEL_P<26> ++ A_WR_ONE A_WR_ZERO VDD VSS / RM_IHPSG13_512x16_c2_1P_BLDRV +XA_BLTMUX<25> A_BLC<25> A_BLC_SEL A_BLT<25> A_BLT_SEL A_PRE_N A_SEL_P<25> ++ A_WR_ONE A_WR_ZERO VDD VSS / RM_IHPSG13_512x16_c2_1P_BLDRV +XA_BLTMUX<24> A_BLC<24> A_BLC_SEL A_BLT<24> A_BLT_SEL A_PRE_N A_SEL_P<24> ++ A_WR_ONE A_WR_ZERO VDD VSS / RM_IHPSG13_512x16_c2_1P_BLDRV +XA_BLTMUX<23> A_BLC<23> A_BLC_SEL A_BLT<23> A_BLT_SEL A_PRE_N A_SEL_P<23> ++ A_WR_ONE A_WR_ZERO VDD VSS / RM_IHPSG13_512x16_c2_1P_BLDRV +XA_BLTMUX<22> A_BLC<22> A_BLC_SEL A_BLT<22> A_BLT_SEL A_PRE_N A_SEL_P<22> ++ A_WR_ONE A_WR_ZERO VDD VSS / RM_IHPSG13_512x16_c2_1P_BLDRV +XA_BLTMUX<21> A_BLC<21> A_BLC_SEL A_BLT<21> A_BLT_SEL A_PRE_N A_SEL_P<21> ++ A_WR_ONE A_WR_ZERO VDD VSS / RM_IHPSG13_512x16_c2_1P_BLDRV +XA_BLTMUX<20> A_BLC<20> A_BLC_SEL A_BLT<20> A_BLT_SEL A_PRE_N A_SEL_P<20> ++ A_WR_ONE A_WR_ZERO VDD VSS / RM_IHPSG13_512x16_c2_1P_BLDRV +XA_BLTMUX<19> A_BLC<19> A_BLC_SEL A_BLT<19> A_BLT_SEL A_PRE_N A_SEL_P<19> ++ A_WR_ONE A_WR_ZERO VDD VSS / RM_IHPSG13_512x16_c2_1P_BLDRV +XA_BLTMUX<18> A_BLC<18> A_BLC_SEL A_BLT<18> A_BLT_SEL A_PRE_N A_SEL_P<18> ++ A_WR_ONE A_WR_ZERO VDD VSS / RM_IHPSG13_512x16_c2_1P_BLDRV +XA_BLTMUX<17> A_BLC<17> A_BLC_SEL A_BLT<17> A_BLT_SEL A_PRE_N A_SEL_P<17> ++ A_WR_ONE A_WR_ZERO VDD VSS / RM_IHPSG13_512x16_c2_1P_BLDRV +XA_BLTMUX<16> A_BLC<16> A_BLC_SEL A_BLT<16> A_BLT_SEL A_PRE_N A_SEL_P<16> ++ A_WR_ONE A_WR_ZERO VDD VSS / RM_IHPSG13_512x16_c2_1P_BLDRV +XA_BLTMUX<15> A_BLC<15> A_BLC_SEL A_BLT<15> A_BLT_SEL A_PRE_N A_SEL_P<15> ++ A_WR_ONE A_WR_ZERO VDD VSS / RM_IHPSG13_512x16_c2_1P_BLDRV +XA_BLTMUX<14> A_BLC<14> A_BLC_SEL A_BLT<14> A_BLT_SEL A_PRE_N A_SEL_P<14> ++ A_WR_ONE A_WR_ZERO VDD VSS / RM_IHPSG13_512x16_c2_1P_BLDRV +XA_BLTMUX<13> A_BLC<13> A_BLC_SEL A_BLT<13> A_BLT_SEL A_PRE_N A_SEL_P<13> ++ A_WR_ONE A_WR_ZERO VDD VSS / RM_IHPSG13_512x16_c2_1P_BLDRV +XA_BLTMUX<12> A_BLC<12> A_BLC_SEL A_BLT<12> A_BLT_SEL A_PRE_N A_SEL_P<12> ++ A_WR_ONE A_WR_ZERO VDD VSS / RM_IHPSG13_512x16_c2_1P_BLDRV +XA_BLTMUX<11> A_BLC<11> A_BLC_SEL A_BLT<11> A_BLT_SEL A_PRE_N A_SEL_P<11> ++ A_WR_ONE A_WR_ZERO VDD VSS / RM_IHPSG13_512x16_c2_1P_BLDRV +XA_BLTMUX<10> A_BLC<10> A_BLC_SEL A_BLT<10> A_BLT_SEL A_PRE_N A_SEL_P<10> ++ A_WR_ONE A_WR_ZERO VDD VSS / RM_IHPSG13_512x16_c2_1P_BLDRV +XA_BLTMUX<9> A_BLC<9> A_BLC_SEL A_BLT<9> A_BLT_SEL A_PRE_N A_SEL_P<9> A_WR_ONE ++ A_WR_ZERO VDD VSS / RM_IHPSG13_512x16_c2_1P_BLDRV +XA_BLTMUX<8> A_BLC<8> A_BLC_SEL A_BLT<8> A_BLT_SEL A_PRE_N A_SEL_P<8> A_WR_ONE ++ A_WR_ZERO VDD VSS / RM_IHPSG13_512x16_c2_1P_BLDRV +XA_BLTMUX<7> A_BLC<7> A_BLC_SEL A_BLT<7> A_BLT_SEL A_PRE_N A_SEL_P<7> A_WR_ONE ++ A_WR_ZERO VDD VSS / RM_IHPSG13_512x16_c2_1P_BLDRV +XA_BLTMUX<6> A_BLC<6> A_BLC_SEL A_BLT<6> A_BLT_SEL A_PRE_N A_SEL_P<6> A_WR_ONE ++ A_WR_ZERO VDD VSS / RM_IHPSG13_512x16_c2_1P_BLDRV +XA_BLTMUX<5> A_BLC<5> A_BLC_SEL A_BLT<5> A_BLT_SEL A_PRE_N A_SEL_P<5> A_WR_ONE ++ A_WR_ZERO VDD VSS / RM_IHPSG13_512x16_c2_1P_BLDRV +XA_BLTMUX<4> A_BLC<4> A_BLC_SEL A_BLT<4> A_BLT_SEL A_PRE_N A_SEL_P<4> A_WR_ONE ++ A_WR_ZERO VDD VSS / RM_IHPSG13_512x16_c2_1P_BLDRV +XA_BLTMUX<3> A_BLC<3> A_BLC_SEL A_BLT<3> A_BLT_SEL A_PRE_N A_SEL_P<3> A_WR_ONE ++ A_WR_ZERO VDD VSS / RM_IHPSG13_512x16_c2_1P_BLDRV +XA_BLTMUX<2> A_BLC<2> A_BLC_SEL A_BLT<2> A_BLT_SEL A_PRE_N A_SEL_P<2> A_WR_ONE ++ A_WR_ZERO VDD VSS / RM_IHPSG13_512x16_c2_1P_BLDRV +XA_BLTMUX<1> A_BLC<1> A_BLC_SEL A_BLT<1> A_BLT_SEL A_PRE_N A_SEL_P<1> A_WR_ONE ++ A_WR_ZERO VDD VSS / RM_IHPSG13_512x16_c2_1P_BLDRV +XA_BLTMUX<0> A_BLC<0> A_BLC_SEL A_BLT<0> A_BLT_SEL A_PRE_N A_SEL_P<0> A_WR_ONE ++ A_WR_ZERO VDD VSS / RM_IHPSG13_512x16_c2_1P_BLDRV +XA_CAPS<17> VDD VSS / RSC_IHPSG13_FILLCAP4 +XA_CAPS<16> VDD VSS / RSC_IHPSG13_FILLCAP4 +XA_CAPS<15> VDD VSS / RSC_IHPSG13_FILLCAP4 +XA_CAPS<14> VDD VSS / RSC_IHPSG13_FILLCAP4 +XA_CAPS<13> VDD VSS / RSC_IHPSG13_FILLCAP4 +XA_CAPS<12> VDD VSS / RSC_IHPSG13_FILLCAP4 +XA_CAPS<11> VDD VSS / RSC_IHPSG13_FILLCAP4 +XA_CAPS<10> VDD VSS / RSC_IHPSG13_FILLCAP4 +XA_CAPS<9> VDD VSS / RSC_IHPSG13_FILLCAP4 +XA_CAPS<8> VDD VSS / RSC_IHPSG13_FILLCAP4 +XA_CAPS<7> VDD VSS / RSC_IHPSG13_FILLCAP4 +XA_CAPS<6> VDD VSS / RSC_IHPSG13_FILLCAP4 +XA_CAPS<5> VDD VSS / RSC_IHPSG13_FILLCAP4 +XA_CAPS<4> VDD VSS / RSC_IHPSG13_FILLCAP4 +XA_CAPS<3> VDD VSS / RSC_IHPSG13_FILLCAP4 +XA_CAPS<2> VDD VSS / RSC_IHPSG13_FILLCAP4 +XA_CAPS<1> VDD VSS / RSC_IHPSG13_FILLCAP4 +XA_I51 net19 A_DR_O VDD VSS / RSC_IHPSG13_INVX4 +XA_I78 A_RCLK_B_L A_SAE VDD VSS / RSC_IHPSG13_CBUFX2 +XA_I69 A_DCLK_L A_DCLK_B_L VDD VSS / RSC_IHPSG13_CINVX8 +XA_I50 A_WCLK_L A_WCLK_B_L VDD VSS / RSC_IHPSG13_CINVX8 +XA_EBUF A_RCLK_L A_RCLK_B_L VDD VSS / RSC_IHPSG13_CINVX8 +XA_I76 A_DI_N A_DO_WRITE_P A_WR_ZERO VDD VSS / RSC_IHPSG13_AND2X6 +XA_I75 A_DI_R A_DO_WRITE_P A_WR_ONE VDD VSS / RSC_IHPSG13_AND2X6 +XA_I83 A_BM_R A_BM_N VDD VSS / RSC_IHPSG13_INVX2 +XA_DEC3INV<31> net23<0> A_SEL_P<31> VDD VSS / RSC_IHPSG13_INVX2 +XA_DEC3INV<30> net23<1> A_SEL_P<30> VDD VSS / RSC_IHPSG13_INVX2 +XA_DEC3INV<29> net23<2> A_SEL_P<29> VDD VSS / RSC_IHPSG13_INVX2 +XA_DEC3INV<28> net23<3> A_SEL_P<28> VDD VSS / RSC_IHPSG13_INVX2 +XA_DEC3INV<27> net23<4> A_SEL_P<27> VDD VSS / RSC_IHPSG13_INVX2 +XA_DEC3INV<26> net23<5> A_SEL_P<26> VDD VSS / RSC_IHPSG13_INVX2 +XA_DEC3INV<25> net23<6> A_SEL_P<25> VDD VSS / RSC_IHPSG13_INVX2 +XA_DEC3INV<24> net23<7> A_SEL_P<24> VDD VSS / RSC_IHPSG13_INVX2 +XA_DEC3INV<23> net23<8> A_SEL_P<23> VDD VSS / RSC_IHPSG13_INVX2 +XA_DEC3INV<22> net23<9> A_SEL_P<22> VDD VSS / RSC_IHPSG13_INVX2 +XA_DEC3INV<21> net23<10> A_SEL_P<21> VDD VSS / RSC_IHPSG13_INVX2 +XA_DEC3INV<20> net23<11> A_SEL_P<20> VDD VSS / RSC_IHPSG13_INVX2 +XA_DEC3INV<19> net23<12> A_SEL_P<19> VDD VSS / RSC_IHPSG13_INVX2 +XA_DEC3INV<18> net23<13> A_SEL_P<18> VDD VSS / RSC_IHPSG13_INVX2 +XA_DEC3INV<17> net23<14> A_SEL_P<17> VDD VSS / RSC_IHPSG13_INVX2 +XA_DEC3INV<16> net23<15> A_SEL_P<16> VDD VSS / RSC_IHPSG13_INVX2 +XA_DEC3INV<15> net23<16> A_SEL_P<15> VDD VSS / RSC_IHPSG13_INVX2 +XA_DEC3INV<14> net23<17> A_SEL_P<14> VDD VSS / RSC_IHPSG13_INVX2 +XA_DEC3INV<13> net23<18> A_SEL_P<13> VDD VSS / RSC_IHPSG13_INVX2 +XA_DEC3INV<12> net23<19> A_SEL_P<12> VDD VSS / RSC_IHPSG13_INVX2 +XA_DEC3INV<11> net23<20> A_SEL_P<11> VDD VSS / RSC_IHPSG13_INVX2 +XA_DEC3INV<10> net23<21> A_SEL_P<10> VDD VSS / RSC_IHPSG13_INVX2 +XA_DEC3INV<9> net23<22> A_SEL_P<9> VDD VSS / RSC_IHPSG13_INVX2 +XA_DEC3INV<8> net23<23> A_SEL_P<8> VDD VSS / RSC_IHPSG13_INVX2 +XA_DEC3INV<7> net23<24> A_SEL_P<7> VDD VSS / RSC_IHPSG13_INVX2 +XA_DEC3INV<6> net23<25> A_SEL_P<6> VDD VSS / RSC_IHPSG13_INVX2 +XA_DEC3INV<5> net23<26> A_SEL_P<5> VDD VSS / RSC_IHPSG13_INVX2 +XA_DEC3INV<4> net23<27> A_SEL_P<4> VDD VSS / RSC_IHPSG13_INVX2 +XA_DEC3INV<3> net23<28> A_SEL_P<3> VDD VSS / RSC_IHPSG13_INVX2 +XA_DEC3INV<2> net23<29> A_SEL_P<2> VDD VSS / RSC_IHPSG13_INVX2 +XA_DEC3INV<1> net23<30> A_SEL_P<1> VDD VSS / RSC_IHPSG13_INVX2 +XA_DEC3INV<0> net23<31> A_SEL_P<0> VDD VSS / RSC_IHPSG13_INVX2 +XA_I49 A_DI_R A_DI_N VDD VSS / RSC_IHPSG13_INVX2 +XA_ISENSE A_SAE A_BLC_SEL A_BLT_SEL net19 net20 VDD VSS / ++ RSC_IHPSG13_DFPQD_MSAFFX2 +XA_DREG A_BIST_EN_I A_BIST_DW_I A_DCLK_B_L A_DW_I A_DI_R net22 VDD VSS ++ / RSC_IHPSG13_DFNQMX2IX1 +XA_BREG A_BIST_EN_I A_BIST_BM_I A_DCLK_B_L A_BM_I A_BM_R net21 VDD VSS ++ / RSC_IHPSG13_DFNQMX2IX1 +XA_DEC3<31> A_P1<1> A_P0<1> A_ADDR_DEC<7> net23<0> VDD VSS / ++ RSC_IHPSG13_NAND3X2 +XA_DEC3<30> A_P1<1> A_P0<1> A_ADDR_DEC<6> net23<1> VDD VSS / ++ RSC_IHPSG13_NAND3X2 +XA_DEC3<29> A_P1<1> A_P0<1> A_ADDR_DEC<5> net23<2> VDD VSS / ++ RSC_IHPSG13_NAND3X2 +XA_DEC3<28> A_P1<1> A_P0<1> A_ADDR_DEC<4> net23<3> VDD VSS / ++ RSC_IHPSG13_NAND3X2 +XA_DEC3<27> A_P1<1> A_P0<1> A_ADDR_DEC<3> net23<4> VDD VSS / ++ RSC_IHPSG13_NAND3X2 +XA_DEC3<26> A_P1<1> A_P0<1> A_ADDR_DEC<2> net23<5> VDD VSS / ++ RSC_IHPSG13_NAND3X2 +XA_DEC3<25> A_P1<1> A_P0<1> A_ADDR_DEC<1> net23<6> VDD VSS / ++ RSC_IHPSG13_NAND3X2 +XA_DEC3<24> A_P1<1> A_P0<1> A_ADDR_DEC<0> net23<7> VDD VSS / ++ RSC_IHPSG13_NAND3X2 +XA_DEC3<23> A_P1<1> A_N0<1> A_ADDR_DEC<7> net23<8> VDD VSS / ++ RSC_IHPSG13_NAND3X2 +XA_DEC3<22> A_P1<1> A_N0<1> A_ADDR_DEC<6> net23<9> VDD VSS / ++ RSC_IHPSG13_NAND3X2 +XA_DEC3<21> A_P1<1> A_N0<1> A_ADDR_DEC<5> net23<10> VDD VSS / ++ RSC_IHPSG13_NAND3X2 +XA_DEC3<20> A_P1<1> A_N0<1> A_ADDR_DEC<4> net23<11> VDD VSS / ++ RSC_IHPSG13_NAND3X2 +XA_DEC3<19> A_P1<1> A_N0<1> A_ADDR_DEC<3> net23<12> VDD VSS / ++ RSC_IHPSG13_NAND3X2 +XA_DEC3<18> A_P1<1> A_N0<1> A_ADDR_DEC<2> net23<13> VDD VSS / ++ RSC_IHPSG13_NAND3X2 +XA_DEC3<17> A_P1<1> A_N0<1> A_ADDR_DEC<1> net23<14> VDD VSS / ++ RSC_IHPSG13_NAND3X2 +XA_DEC3<16> A_P1<1> A_N0<1> A_ADDR_DEC<0> net23<15> VDD VSS / ++ RSC_IHPSG13_NAND3X2 +XA_DEC3<15> A_N1<0> A_P0<0> A_ADDR_DEC<7> net23<16> VDD VSS / ++ RSC_IHPSG13_NAND3X2 +XA_DEC3<14> A_N1<0> A_P0<0> A_ADDR_DEC<6> net23<17> VDD VSS / ++ RSC_IHPSG13_NAND3X2 +XA_DEC3<13> A_N1<0> A_P0<0> A_ADDR_DEC<5> net23<18> VDD VSS / ++ RSC_IHPSG13_NAND3X2 +XA_DEC3<12> A_N1<0> A_P0<0> A_ADDR_DEC<4> net23<19> VDD VSS / ++ RSC_IHPSG13_NAND3X2 +XA_DEC3<11> A_N1<0> A_P0<0> A_ADDR_DEC<3> net23<20> VDD VSS / ++ RSC_IHPSG13_NAND3X2 +XA_DEC3<10> A_N1<0> A_P0<0> A_ADDR_DEC<2> net23<21> VDD VSS / ++ RSC_IHPSG13_NAND3X2 +XA_DEC3<9> A_N1<0> A_P0<0> A_ADDR_DEC<1> net23<22> VDD VSS / ++ RSC_IHPSG13_NAND3X2 +XA_DEC3<8> A_N1<0> A_P0<0> A_ADDR_DEC<0> net23<23> VDD VSS / ++ RSC_IHPSG13_NAND3X2 +XA_DEC3<7> A_N1<0> A_N0<0> A_ADDR_DEC<7> net23<24> VDD VSS / ++ RSC_IHPSG13_NAND3X2 +XA_DEC3<6> A_N1<0> A_N0<0> A_ADDR_DEC<6> net23<25> VDD VSS / ++ RSC_IHPSG13_NAND3X2 +XA_DEC3<5> A_N1<0> A_N0<0> A_ADDR_DEC<5> net23<26> VDD VSS / ++ RSC_IHPSG13_NAND3X2 +XA_DEC3<4> A_N1<0> A_N0<0> A_ADDR_DEC<4> net23<27> VDD VSS / ++ RSC_IHPSG13_NAND3X2 +XA_DEC3<3> A_N1<0> A_N0<0> A_ADDR_DEC<3> net23<28> VDD VSS / ++ RSC_IHPSG13_NAND3X2 +XA_DEC3<2> A_N1<0> A_N0<0> A_ADDR_DEC<2> net23<29> VDD VSS / ++ RSC_IHPSG13_NAND3X2 +XA_DEC3<1> A_N1<0> A_N0<0> A_ADDR_DEC<1> net23<30> VDD VSS / ++ RSC_IHPSG13_NAND3X2 +XA_DEC3<0> A_N1<0> A_N0<0> A_ADDR_DEC<0> net23<31> VDD VSS / ++ RSC_IHPSG13_NAND3X2 +XA_I89 A_DCLK_B_L A_DCLK_B_R / RSC_IHPSG13_MET3RES +XA_I91 A_RCLK_B_L A_RCLK_B_R / RSC_IHPSG13_MET3RES +XA_I90 A_WCLK_B_L A_WCLK_B_R / RSC_IHPSG13_MET3RES +XA_I88 A_DCLK_L A_DCLK_R / RSC_IHPSG13_MET3RES +XA_I87 A_WCLK_L A_WCLK_R / RSC_IHPSG13_MET3RES +XA_R2 A_RCLK_L A_RCLK_R / RSC_IHPSG13_MET3RES +XA_BM_TIEH A_TIEH_O VDD VSS / RSC_IHPSG13_TIEH +.ENDS + +.SUBCKT RM_IHPSG13_512x16_c2_1P_COLDRV13X12 ADDR_COL_I<1> ADDR_COL_I<0> ADDR_COL_O<1> ++ ADDR_COL_O<0> ADDR_DEC_I<7> ADDR_DEC_I<6> ADDR_DEC_I<5> ADDR_DEC_I<4> ++ ADDR_DEC_I<3> ADDR_DEC_I<2> ADDR_DEC_I<1> ADDR_DEC_I<0> ADDR_DEC_O<7> ++ ADDR_DEC_O<6> ADDR_DEC_O<5> ADDR_DEC_O<4> ADDR_DEC_O<3> ADDR_DEC_O<2> ++ ADDR_DEC_O<1> ADDR_DEC_O<0> DCLK_I DCLK_O RCLK_I RCLK_O WCLK_I WCLK_O ++ VDD VSS +XI1<1> VDD VSS / RSC_IHPSG13_FILLCAP4 +XI1<0> VDD VSS / RSC_IHPSG13_FILLCAP4 +XI0<1> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI0<0> VDD VSS / RSC_IHPSG13_FILLCAP8 +XADDR_COL_DRV<1> ADDR_COL_I<1> ADDR_COL_O<1> VDD VSS / ++ RSC_IHPSG13_CBUFX12 +XADDR_COL_DRV<0> ADDR_COL_I<0> ADDR_COL_O<0> VDD VSS / ++ RSC_IHPSG13_CBUFX12 +XADDR_DEC_DRV<7> ADDR_DEC_I<7> ADDR_DEC_O<7> VDD VSS / ++ RSC_IHPSG13_CBUFX12 +XADDR_DEC_DRV<6> ADDR_DEC_I<6> ADDR_DEC_O<6> VDD VSS / ++ RSC_IHPSG13_CBUFX12 +XADDR_DEC_DRV<5> ADDR_DEC_I<5> ADDR_DEC_O<5> VDD VSS / ++ RSC_IHPSG13_CBUFX12 +XADDR_DEC_DRV<4> ADDR_DEC_I<4> ADDR_DEC_O<4> VDD VSS / ++ RSC_IHPSG13_CBUFX12 +XADDR_DEC_DRV<3> ADDR_DEC_I<3> ADDR_DEC_O<3> VDD VSS / ++ RSC_IHPSG13_CBUFX12 +XADDR_DEC_DRV<2> ADDR_DEC_I<2> ADDR_DEC_O<2> VDD VSS / ++ RSC_IHPSG13_CBUFX12 +XADDR_DEC_DRV<1> ADDR_DEC_I<1> ADDR_DEC_O<1> VDD VSS / ++ RSC_IHPSG13_CBUFX12 +XADDR_DEC_DRV<0> ADDR_DEC_I<0> ADDR_DEC_O<0> VDD VSS / ++ RSC_IHPSG13_CBUFX12 +XDCLK_DRV DCLK_I DCLK_O VDD VSS / RSC_IHPSG13_CBUFX12 +XRCLK_DRV RCLK_I RCLK_O VDD VSS / RSC_IHPSG13_CBUFX12 +XWCLK_DRV WCLK_I WCLK_O VDD VSS / RSC_IHPSG13_CBUFX12 +.ENDS +.SUBCKT RM_IHPSG13_512x16_c2_1P_WLDRV16X12 A<15> A<14> A<13> A<12> A<11> A<10> A<9> A<8> ++ A<7> A<6> A<5> A<4> A<3> A<2> A<1> A<0> Z<15> Z<14> Z<13> Z<12> Z<11> Z<10> ++ Z<9> Z<8> Z<7> Z<6> Z<5> Z<4> Z<3> Z<2> Z<1> Z<0> VDD VSS +XBUF<15> A<15> Z<15> VDD VSS / RSC_IHPSG13_WLDRVX12 +XBUF<14> A<14> Z<14> VDD VSS / RSC_IHPSG13_WLDRVX12 +XBUF<13> A<13> Z<13> VDD VSS / RSC_IHPSG13_WLDRVX12 +XBUF<12> A<12> Z<12> VDD VSS / RSC_IHPSG13_WLDRVX12 +XBUF<11> A<11> Z<11> VDD VSS / RSC_IHPSG13_WLDRVX12 +XBUF<10> A<10> Z<10> VDD VSS / RSC_IHPSG13_WLDRVX12 +XBUF<9> A<9> Z<9> VDD VSS / RSC_IHPSG13_WLDRVX12 +XBUF<8> A<8> Z<8> VDD VSS / RSC_IHPSG13_WLDRVX12 +XBUF<7> A<7> Z<7> VDD VSS / RSC_IHPSG13_WLDRVX12 +XBUF<6> A<6> Z<6> VDD VSS / RSC_IHPSG13_WLDRVX12 +XBUF<5> A<5> Z<5> VDD VSS / RSC_IHPSG13_WLDRVX12 +XBUF<4> A<4> Z<4> VDD VSS / RSC_IHPSG13_WLDRVX12 +XBUF<3> A<3> Z<3> VDD VSS / RSC_IHPSG13_WLDRVX12 +XBUF<2> A<2> Z<2> VDD VSS / RSC_IHPSG13_WLDRVX12 +XBUF<1> A<1> Z<1> VDD VSS / RSC_IHPSG13_WLDRVX12 +XBUF<0> A<0> Z<0> VDD VSS / RSC_IHPSG13_WLDRVX12 +.ENDS + + + +.SUBCKT RM_IHPSG13_512x16_c2_2P_COLDRV13X8 ADDR_COL_I<1> ADDR_COL_I<0> ADDR_COL_O<1> ++ ADDR_COL_O<0> ADDR_DEC_I<7> ADDR_DEC_I<6> ADDR_DEC_I<5> ADDR_DEC_I<4> ++ ADDR_DEC_I<3> ADDR_DEC_I<2> ADDR_DEC_I<1> ADDR_DEC_I<0> ADDR_DEC_O<7> ++ ADDR_DEC_O<6> ADDR_DEC_O<5> ADDR_DEC_O<4> ADDR_DEC_O<3> ADDR_DEC_O<2> ++ ADDR_DEC_O<1> ADDR_DEC_O<0> DCLK_I DCLK_O RCLK_I RCLK_O WCLK_I WCLK_O ++ VDD VSS +XI0<5> VDD VSS / RSC_IHPSG13_FILLCAP4 +XI0<4> VDD VSS / RSC_IHPSG13_FILLCAP4 +XI0<3> VDD VSS / RSC_IHPSG13_FILLCAP4 +XI0<2> VDD VSS / RSC_IHPSG13_FILLCAP4 +XI0<1> VDD VSS / RSC_IHPSG13_FILLCAP4 +XWCLK_DRV WCLK_I WCLK_O VDD VSS / RSC_IHPSG13_CBUFX8 +XRCLK_DRV RCLK_I RCLK_O VDD VSS / RSC_IHPSG13_CBUFX8 +XDCLK_DRV DCLK_I DCLK_O VDD VSS / RSC_IHPSG13_CBUFX8 +XADDR_COL_DRV<1> ADDR_COL_I<1> ADDR_COL_O<1> VDD VSS / ++ RSC_IHPSG13_CBUFX8 +XADDR_COL_DRV<0> ADDR_COL_I<0> ADDR_COL_O<0> VDD VSS / ++ RSC_IHPSG13_CBUFX8 +XADDR_DEC_DRV<7> ADDR_DEC_I<7> ADDR_DEC_O<7> VDD VSS / ++ RSC_IHPSG13_CBUFX8 +XADDR_DEC_DRV<6> ADDR_DEC_I<6> ADDR_DEC_O<6> VDD VSS / ++ RSC_IHPSG13_CBUFX8 +XADDR_DEC_DRV<5> ADDR_DEC_I<5> ADDR_DEC_O<5> VDD VSS / ++ RSC_IHPSG13_CBUFX8 +XADDR_DEC_DRV<4> ADDR_DEC_I<4> ADDR_DEC_O<4> VDD VSS / ++ RSC_IHPSG13_CBUFX8 +XADDR_DEC_DRV<3> ADDR_DEC_I<3> ADDR_DEC_O<3> VDD VSS / ++ RSC_IHPSG13_CBUFX8 +XADDR_DEC_DRV<2> ADDR_DEC_I<2> ADDR_DEC_O<2> VDD VSS / ++ RSC_IHPSG13_CBUFX8 +XADDR_DEC_DRV<1> ADDR_DEC_I<1> ADDR_DEC_O<1> VDD VSS / ++ RSC_IHPSG13_CBUFX8 +XADDR_DEC_DRV<0> ADDR_DEC_I<0> ADDR_DEC_O<0> VDD VSS / ++ RSC_IHPSG13_CBUFX8 +XI1<3> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI1<2> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI1<1> VDD VSS / RSC_IHPSG13_FILLCAP8 +.ENDS +.SUBCKT RSC_IHPSG13_WLDRVX8 A Z VDD VSS +MN1 Z net6 VSS VSS sg13_lv_nmos m=1 w=1.41u l=130.00n ng=2 nrd=0 nrs=0 +MN0 net6 A VSS VSS sg13_lv_nmos m=1 w=1.8u l=130.00n ng=2 nrd=0 nrs=0 +MP1 Z net6 VDD VDD sg13_lv_pmos m=1 w=6.48u l=130.00n ng=4 nrd=0 nrs=0 +MP0 net6 A VDD VDD sg13_lv_pmos m=1 w=900.0n l=130.00n ng=1 nrd=0 nrs=0 +.ENDS +.SUBCKT RM_IHPSG13_512x16_c2_2P_WLDRV16X8 A<15> A<14> A<13> A<12> A<11> A<10> A<9> A<8> ++ A<7> A<6> A<5> A<4> A<3> A<2> A<1> A<0> Z<15> Z<14> Z<13> Z<12> Z<11> Z<10> ++ Z<9> Z<8> Z<7> Z<6> Z<5> Z<4> Z<3> Z<2> Z<1> Z<0> VDD VSS +XBUF<15> A<15> Z<15> VDD VSS / RSC_IHPSG13_WLDRVX8 +XBUF<14> A<14> Z<14> VDD VSS / RSC_IHPSG13_WLDRVX8 +XBUF<13> A<13> Z<13> VDD VSS / RSC_IHPSG13_WLDRVX8 +XBUF<12> A<12> Z<12> VDD VSS / RSC_IHPSG13_WLDRVX8 +XBUF<11> A<11> Z<11> VDD VSS / RSC_IHPSG13_WLDRVX8 +XBUF<10> A<10> Z<10> VDD VSS / RSC_IHPSG13_WLDRVX8 +XBUF<9> A<9> Z<9> VDD VSS / RSC_IHPSG13_WLDRVX8 +XBUF<8> A<8> Z<8> VDD VSS / RSC_IHPSG13_WLDRVX8 +XBUF<7> A<7> Z<7> VDD VSS / RSC_IHPSG13_WLDRVX8 +XBUF<6> A<6> Z<6> VDD VSS / RSC_IHPSG13_WLDRVX8 +XBUF<5> A<5> Z<5> VDD VSS / RSC_IHPSG13_WLDRVX8 +XBUF<4> A<4> Z<4> VDD VSS / RSC_IHPSG13_WLDRVX8 +XBUF<3> A<3> Z<3> VDD VSS / RSC_IHPSG13_WLDRVX8 +XBUF<2> A<2> Z<2> VDD VSS / RSC_IHPSG13_WLDRVX8 +XBUF<1> A<1> Z<1> VDD VSS / RSC_IHPSG13_WLDRVX8 +XBUF<0> A<0> Z<0> VDD VSS / RSC_IHPSG13_WLDRVX8 +.ENDS + + + +.SUBCKT RM_IHPSG13_512x16_c2_2P_COLDEC2 ACLK_N ADDR<1> ADDR<0> ADDR_COL<1> ADDR_COL<0> ++ ADDR_DEC<7> ADDR_DEC<6> ADDR_DEC<5> ADDR_DEC<4> ADDR_DEC<3> ADDR_DEC<2> ++ ADDR_DEC<1> ADDR_DEC<0> BIST_ADDR<1> BIST_ADDR<0> BIST_EN_I VDD VSS +XI16<17> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI16<16> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI16<15> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI16<14> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI16<13> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI16<12> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI16<11> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI16<10> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI16<9> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI16<8> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI16<7> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI16<6> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI16<5> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI16<4> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI16<3> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI16<2> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI16<1> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI18<24> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI18<23> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI18<22> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI18<21> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI18<20> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI18<19> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI18<18> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI18<17> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI18<16> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI18<15> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI18<14> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI18<13> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI18<12> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI18<11> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI18<10> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI18<9> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI18<8> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI18<7> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI18<6> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI18<5> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI18<4> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI18<3> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI18<2> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI18<1> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI1<3> PADR<0> PADR<1> addr_n<3> VDD VSS / RSC_IHPSG13_NAND2X2 +XI1<2> NADR<0> PADR<1> addr_n<2> VDD VSS / RSC_IHPSG13_NAND2X2 +XI1<1> PADR<0> NADR<1> addr_n<1> VDD VSS / RSC_IHPSG13_NAND2X2 +XI1<0> NADR<0> NADR<1> addr_n<0> VDD VSS / RSC_IHPSG13_NAND2X2 +XI17<1> ADDR_COL<1> VDD VSS / RSC_IHPSG13_TIEL +XI17<0> ADDR_COL<0> VDD VSS / RSC_IHPSG13_TIEL +XI14<3> ADDR_DEC<7> VDD VSS / RSC_IHPSG13_TIEL +XI14<2> ADDR_DEC<6> VDD VSS / RSC_IHPSG13_TIEL +XI14<1> ADDR_DEC<5> VDD VSS / RSC_IHPSG13_TIEL +XI14<0> ADDR_DEC<4> VDD VSS / RSC_IHPSG13_TIEL +XI13<1> NADR<1> PADR<1> VDD VSS / RSC_IHPSG13_INVX2 +XI13<0> NADR<0> PADR<0> VDD VSS / RSC_IHPSG13_INVX2 +XI3<1> padr_int<1> NADR<1> VDD VSS / RSC_IHPSG13_INVX2 +XI3<0> padr_int<0> NADR<0> VDD VSS / RSC_IHPSG13_INVX2 +XI2<3> addr_n<3> ADDR_DEC<3> VDD VSS / RSC_IHPSG13_INVX2 +XI2<2> addr_n<2> ADDR_DEC<2> VDD VSS / RSC_IHPSG13_INVX2 +XI2<1> addr_n<1> ADDR_DEC<1> VDD VSS / RSC_IHPSG13_INVX2 +XI2<0> addr_n<0> ADDR_DEC<0> VDD VSS / RSC_IHPSG13_INVX2 +XDFF<1> BIST_EN_I BIST_ADDR<1> ACLK_N ADDR<1> padr_int<1> net12<0> VDD ++ VSS / RSC_IHPSG13_DFNQMX2IX1 +XDFF<0> BIST_EN_I BIST_ADDR<0> ACLK_N ADDR<0> padr_int<0> net12<1> VDD ++ VSS / RSC_IHPSG13_DFNQMX2IX1 +XI15<5> VDD VSS / RSC_IHPSG13_FILLCAP4 +XI15<4> VDD VSS / RSC_IHPSG13_FILLCAP4 +XI15<3> VDD VSS / RSC_IHPSG13_FILLCAP4 +XI15<2> VDD VSS / RSC_IHPSG13_FILLCAP4 +XI15<1> VDD VSS / RSC_IHPSG13_FILLCAP4 +XI19<4> VDD VSS / RSC_IHPSG13_FILLCAP4 +XI19<3> VDD VSS / RSC_IHPSG13_FILLCAP4 +XI19<2> VDD VSS / RSC_IHPSG13_FILLCAP4 +XI19<1> VDD VSS / RSC_IHPSG13_FILLCAP4 +.ENDS +.SUBCKT RM_IHPSG13_512x16_c2_2P_COLCTRL2 A_ADDR_DEC<3> A_ADDR_DEC<2> A_ADDR_DEC<1> ++ A_ADDR_DEC<0> A_BIST_BM_I A_BIST_DW_I A_BIST_EN_I A_BLC<3> A_BLC<2> A_BLC<1> ++ A_BLC<0> A_BLT<3> A_BLT<2> A_BLT<1> A_BLT<0> A_BM_I A_DCLK_B_L A_DCLK_B_R ++ A_DCLK_L A_DCLK_R A_DR_O A_DW_I A_RCLK_B_L A_RCLK_B_R A_RCLK_L A_RCLK_R ++ A_TIEH_O A_WCLK_B_L A_WCLK_B_R A_WCLK_L A_WCLK_R B_ADDR_DEC<3> B_ADDR_DEC<2> ++ B_ADDR_DEC<1> B_ADDR_DEC<0> B_BIST_BM_I B_BIST_DW_I B_BIST_EN_I B_BLC<3> ++ B_BLC<2> B_BLC<1> B_BLC<0> B_BLT<3> B_BLT<2> B_BLT<1> B_BLT<0> B_BM_I ++ B_DCLK_B_L B_DCLK_B_R B_DCLK_L B_DCLK_R B_DR_O B_DW_I B_RCLK_B_L B_RCLK_B_R ++ B_RCLK_L B_RCLK_R B_TIEH_O B_WCLK_B_L B_WCLK_B_R B_WCLK_L B_WCLK_R VDD ++ VSS +XB_DREG B_BIST_EN_I B_BIST_DW_I B_DCLK_B_L B_DW_I B_DI_R net046 VDD ++ VSS / RSC_IHPSG13_DFNQMX2IX1 +XB_BREG B_BIST_EN_I B_BIST_BM_I B_DCLK_B_L B_BM_I B_BM_R net045 VDD ++ VSS / RSC_IHPSG13_DFNQMX2IX1 +XA_DREG A_BIST_EN_I A_BIST_DW_I A_DCLK_B_L A_DW_I A_DI_R net22 VDD VSS ++ / RSC_IHPSG13_DFNQMX2IX1 +XA_BREG A_BIST_EN_I A_BIST_BM_I A_DCLK_B_L A_BM_I A_BM_R net23 VDD VSS ++ / RSC_IHPSG13_DFNQMX2IX1 +XB_CAPS VDD VSS / RSC_IHPSG13_FILLCAP4 +XA_CAPS VDD VSS / RSC_IHPSG13_FILLCAP4 +XB_I75 B_DI_R B_DO_WRITE_P B_WR_ONE VDD VSS / RSC_IHPSG13_AND2X2 +XB_I80 B_RCLK_B_L B_WCLK_B_L net041 VDD VSS / RSC_IHPSG13_AND2X2 +XB_I76 B_DI_N B_DO_WRITE_P B_WR_ZERO VDD VSS / RSC_IHPSG13_AND2X2 +XA_I80 A_RCLK_B_L A_WCLK_B_L net21 VDD VSS / RSC_IHPSG13_AND2X2 +XA_I75 A_DI_R A_DO_WRITE_P A_WR_ONE VDD VSS / RSC_IHPSG13_AND2X2 +XA_I76 A_DI_N A_DO_WRITE_P A_WR_ZERO VDD VSS / RSC_IHPSG13_AND2X2 +XB_I44 B_WCLK_B_L B_BM_N B_DO_WRITE_P VDD VSS / RSC_IHPSG13_NOR2X2 +XA_I44 A_WCLK_B_L A_BM_N A_DO_WRITE_P VDD VSS / RSC_IHPSG13_NOR2X2 +XB_I81 net041 B_PRE_N VDD VSS / RSC_IHPSG13_CINVX4_WN +XA_I81 net21 A_PRE_N VDD VSS / RSC_IHPSG13_CINVX4_WN +XB_BM_TIEH B_TIEH_O VDD VSS / RSC_IHPSG13_TIEH +XA_BM_TIEH A_TIEH_O VDD VSS / RSC_IHPSG13_TIEH +XA_I89 A_DCLK_B_L A_DCLK_B_R / RSC_IHPSG13_MET3RES +XA_I88 A_DCLK_L A_DCLK_R / RSC_IHPSG13_MET3RES +XA_I87 A_WCLK_L A_WCLK_R / RSC_IHPSG13_MET3RES +XA_I91 A_RCLK_B_L A_RCLK_B_R / RSC_IHPSG13_MET3RES +XB_I87 B_WCLK_L B_WCLK_R / RSC_IHPSG13_MET3RES +XB_I88 B_DCLK_L B_DCLK_R / RSC_IHPSG13_MET3RES +XB_I89 B_DCLK_B_L B_DCLK_B_R / RSC_IHPSG13_MET3RES +XB_I90 B_WCLK_B_L B_WCLK_B_R / RSC_IHPSG13_MET3RES +XB_R2 B_RCLK_L B_RCLK_R / RSC_IHPSG13_MET3RES +XB_I91 B_RCLK_B_L B_RCLK_B_R / RSC_IHPSG13_MET3RES +XA_R2 A_RCLK_L A_RCLK_R / RSC_IHPSG13_MET3RES +XA_I90 A_WCLK_B_L A_WCLK_B_R / RSC_IHPSG13_MET3RES +XAB_BLMUX A_BLC<3> A_BLC<2> A_BLC<1> A_BLC<0> A_BLC_SEL A_BLT<3> A_BLT<2> ++ A_BLT<1> A_BLT<0> A_BLT_SEL A_PRE_N A_ADDR_DEC<3> A_ADDR_DEC<2> ++ A_ADDR_DEC<1> A_ADDR_DEC<0> A_WR_ONE A_WR_ZERO B_BLC<3> B_BLC<2> B_BLC<1> ++ B_BLC<0> B_BLC_SEL B_BLT<3> B_BLT<2> B_BLT<1> B_BLT<0> B_BLT_SEL B_PRE_N ++ B_ADDR_DEC<3> B_ADDR_DEC<2> B_ADDR_DEC<1> B_ADDR_DEC<0> B_WR_ONE B_WR_ZERO ++ VDD VSS / RM_IHPSG13_512x16_c2_2P_BLDRV +XB_ISENSE B_SAE B_BLC_SEL B_BLT_SEL net039 net040 VDD VSS / ++ RSC_IHPSG13_DFPQD_MSAFFX2 +XA_ISENSE A_SAE A_BLC_SEL A_BLT_SEL net19 net20 VDD VSS / ++ RSC_IHPSG13_DFPQD_MSAFFX2 +XB_I78 B_RCLK_B_L B_SAE VDD VSS / RSC_IHPSG13_CBUFX2 +XA_I78 A_RCLK_B_L A_SAE VDD VSS / RSC_IHPSG13_CBUFX2 +XB_I83 B_BM_R B_BM_N VDD VSS / RSC_IHPSG13_INVX2 +XB_I49 B_DI_R B_DI_N VDD VSS / RSC_IHPSG13_INVX2 +XA_I83 A_BM_R A_BM_N VDD VSS / RSC_IHPSG13_INVX2 +XA_I49 A_DI_R A_DI_N VDD VSS / RSC_IHPSG13_INVX2 +XB_I51 net039 B_DR_O VDD VSS / RSC_IHPSG13_INVX4 +XA_I51 net19 A_DR_O VDD VSS / RSC_IHPSG13_INVX4 +XA_I69 A_DCLK_L A_DCLK_B_L VDD VSS / RSC_IHPSG13_CINVX2 +XA_I50 A_WCLK_L A_WCLK_B_L VDD VSS / RSC_IHPSG13_CINVX2 +XA_EBUF A_RCLK_L A_RCLK_B_L VDD VSS / RSC_IHPSG13_CINVX2 +XB_EBUF B_RCLK_L B_RCLK_B_L VDD VSS / RSC_IHPSG13_CINVX2 +XB_I50 B_WCLK_L B_WCLK_B_L VDD VSS / RSC_IHPSG13_CINVX2 +XB_I69 B_DCLK_L B_DCLK_B_L VDD VSS / RSC_IHPSG13_CINVX2 +.ENDS +.SUBCKT RM_IHPSG13_512x16_c2_2P_COLDRV13_FILL4C2 VDD VSS +XI0<2> VDD VSS / RSC_IHPSG13_FILLCAP4 +XI0<1> VDD VSS / RSC_IHPSG13_FILLCAP4 +.ENDS + + +.SUBCKT RM_IHPSG13_512x16_c2_2P_ROWDEC7 ADDR_N_I<6> ADDR_N_I<5> ADDR_N_I<4> ADDR_N_I<3> ++ ADDR_N_I<2> ADDR_N_I<1> ADDR_N_I<0> CS_I ECLK_I WL_O<127> WL_O<126> ++ WL_O<125> WL_O<124> WL_O<123> WL_O<122> WL_O<121> WL_O<120> WL_O<119> ++ WL_O<118> WL_O<117> WL_O<116> WL_O<115> WL_O<114> WL_O<113> WL_O<112> ++ WL_O<111> WL_O<110> WL_O<109> WL_O<108> WL_O<107> WL_O<106> WL_O<105> ++ WL_O<104> WL_O<103> WL_O<102> WL_O<101> WL_O<100> WL_O<99> WL_O<98> WL_O<97> ++ WL_O<96> WL_O<95> WL_O<94> WL_O<93> WL_O<92> WL_O<91> WL_O<90> WL_O<89> ++ WL_O<88> WL_O<87> WL_O<86> WL_O<85> WL_O<84> WL_O<83> WL_O<82> WL_O<81> ++ WL_O<80> WL_O<79> WL_O<78> WL_O<77> WL_O<76> WL_O<75> WL_O<74> WL_O<73> ++ WL_O<72> WL_O<71> WL_O<70> WL_O<69> WL_O<68> WL_O<67> WL_O<66> WL_O<65> ++ WL_O<64> WL_O<63> WL_O<62> WL_O<61> WL_O<60> WL_O<59> WL_O<58> WL_O<57> ++ WL_O<56> WL_O<55> WL_O<54> WL_O<53> WL_O<52> WL_O<51> WL_O<50> WL_O<49> ++ WL_O<48> WL_O<47> WL_O<46> WL_O<45> WL_O<44> WL_O<43> WL_O<42> WL_O<41> ++ WL_O<40> WL_O<39> WL_O<38> WL_O<37> WL_O<36> WL_O<35> WL_O<34> WL_O<33> ++ WL_O<32> WL_O<31> WL_O<30> WL_O<29> WL_O<28> WL_O<27> WL_O<26> WL_O<25> ++ WL_O<24> WL_O<23> WL_O<22> WL_O<21> WL_O<20> WL_O<19> WL_O<18> WL_O<17> ++ WL_O<16> WL_O<15> WL_O<14> WL_O<13> WL_O<12> WL_O<11> WL_O<10> WL_O<9> ++ WL_O<8> WL_O<7> WL_O<6> WL_O<5> WL_O<4> WL_O<3> WL_O<2> WL_O<1> WL_O<0> ++ VDD VSS +XSEL<7> ADDR_N_I<3> ADDR_N_I<2> ADDR_N_I<1> ADDR_N_I<0> CS00<7> ECLK_H<7> ++ ECLK_H<8> ECLK_B<7> ECLK_B<8> WL_O<127> WL_O<126> WL_O<125> WL_O<124> ++ WL_O<123> WL_O<122> WL_O<121> WL_O<120> WL_O<119> WL_O<118> WL_O<117> ++ WL_O<116> WL_O<115> WL_O<114> WL_O<113> WL_O<112> VDD VSS / ++ RM_IHPSG13_512x16_c2_2P_DEC04 +XSEL<6> ADDR_N_I<3> ADDR_N_I<2> ADDR_N_I<1> ADDR_N_I<0> CS00<6> ECLK_H<6> ++ ECLK_H<7> ECLK_B<6> ECLK_B<7> WL_O<111> WL_O<110> WL_O<109> WL_O<108> ++ WL_O<107> WL_O<106> WL_O<105> WL_O<104> WL_O<103> WL_O<102> WL_O<101> ++ WL_O<100> WL_O<99> WL_O<98> WL_O<97> WL_O<96> VDD VSS / ++ RM_IHPSG13_512x16_c2_2P_DEC04 +XSEL<5> ADDR_N_I<3> ADDR_N_I<2> ADDR_N_I<1> ADDR_N_I<0> CS00<5> ECLK_H<5> ++ ECLK_H<6> ECLK_B<5> ECLK_B<6> WL_O<95> WL_O<94> WL_O<93> WL_O<92> WL_O<91> ++ WL_O<90> WL_O<89> WL_O<88> WL_O<87> WL_O<86> WL_O<85> WL_O<84> WL_O<83> ++ WL_O<82> WL_O<81> WL_O<80> VDD VSS / RM_IHPSG13_512x16_c2_2P_DEC04 +XSEL<4> ADDR_N_I<3> ADDR_N_I<2> ADDR_N_I<1> ADDR_N_I<0> CS00<4> ECLK_H<4> ++ ECLK_H<5> ECLK_B<4> ECLK_B<5> WL_O<79> WL_O<78> WL_O<77> WL_O<76> WL_O<75> ++ WL_O<74> WL_O<73> WL_O<72> WL_O<71> WL_O<70> WL_O<69> WL_O<68> WL_O<67> ++ WL_O<66> WL_O<65> WL_O<64> VDD VSS / RM_IHPSG13_512x16_c2_2P_DEC04 +XSEL<3> ADDR_N_I<3> ADDR_N_I<2> ADDR_N_I<1> ADDR_N_I<0> CS00<3> ECLK_H<3> ++ ECLK_H<4> ECLK_B<3> ECLK_B<4> WL_O<63> WL_O<62> WL_O<61> WL_O<60> WL_O<59> ++ WL_O<58> WL_O<57> WL_O<56> WL_O<55> WL_O<54> WL_O<53> WL_O<52> WL_O<51> ++ WL_O<50> WL_O<49> WL_O<48> VDD VSS / RM_IHPSG13_512x16_c2_2P_DEC04 +XSEL<2> ADDR_N_I<3> ADDR_N_I<2> ADDR_N_I<1> ADDR_N_I<0> CS00<2> ECLK_H<2> ++ ECLK_H<3> ECLK_B<2> ECLK_B<3> WL_O<47> WL_O<46> WL_O<45> WL_O<44> WL_O<43> ++ WL_O<42> WL_O<41> WL_O<40> WL_O<39> WL_O<38> WL_O<37> WL_O<36> WL_O<35> ++ WL_O<34> WL_O<33> WL_O<32> VDD VSS / RM_IHPSG13_512x16_c2_2P_DEC04 +XSEL<1> ADDR_N_I<3> ADDR_N_I<2> ADDR_N_I<1> ADDR_N_I<0> CS00<1> ECLK_H<1> ++ ECLK_H<2> ECLK_B<1> ECLK_B<2> WL_O<31> WL_O<30> WL_O<29> WL_O<28> WL_O<27> ++ WL_O<26> WL_O<25> WL_O<24> WL_O<23> WL_O<22> WL_O<21> WL_O<20> WL_O<19> ++ WL_O<18> WL_O<17> WL_O<16> VDD VSS / RM_IHPSG13_512x16_c2_2P_DEC04 +XSEL<0> ADDR_N_I<3> ADDR_N_I<2> ADDR_N_I<1> ADDR_N_I<0> CS00<0> ECLK_I ++ ECLK_H<1> ECLK_B<0> ECLK_B<1> WL_O<15> WL_O<14> WL_O<13> WL_O<12> WL_O<11> ++ WL_O<10> WL_O<9> WL_O<8> WL_O<7> WL_O<6> WL_O<5> WL_O<4> WL_O<3> WL_O<2> ++ WL_O<1> WL_O<0> VDD VSS / RM_IHPSG13_512x16_c2_2P_DEC04 +XDEC11<1> ADDR_N_I<5> ADDR_N_I<4> CS04<1> CS00<7> VDD VSS / ++ RM_IHPSG13_512x16_c2_2P_DEC03 +XDEC11<0> ADDR_N_I<5> ADDR_N_I<4> CS04<0> CS00<3> VDD VSS / ++ RM_IHPSG13_512x16_c2_2P_DEC03 +XDEC01<2> ADDR_N_I<7> ADDR_N_I<6> CS_I CS04<1> VDD VSS / ++ RM_IHPSG13_512x16_c2_2P_DEC01 +XDEC01<1> ADDR_N_I<5> ADDR_N_I<4> CS04<1> CS00<5> VDD VSS / ++ RM_IHPSG13_512x16_c2_2P_DEC01 +XDEC01<0> ADDR_N_I<5> ADDR_N_I<4> CS04<0> CS00<1> VDD VSS / ++ RM_IHPSG13_512x16_c2_2P_DEC01 +XL2<66> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<65> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<64> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<63> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<62> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<61> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<60> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<59> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<58> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<57> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<56> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<55> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<54> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<53> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<52> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<51> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<50> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<49> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<48> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<47> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<46> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<45> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<44> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<43> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<42> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<41> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<40> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<39> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<38> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<37> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<36> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<35> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<34> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<33> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<32> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<31> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<30> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<29> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<28> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<27> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<26> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<25> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<24> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<23> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<22> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<21> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<20> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<19> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<18> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<17> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<16> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<15> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<14> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<13> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<12> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<11> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<10> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<9> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<8> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<7> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<6> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<5> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<4> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<3> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<2> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<1> VDD VSS / RSC_IHPSG13_FILLCAP8 +XDEC10<1> ADDR_N_I<5> ADDR_N_I<4> CS04<1> CS00<6> VDD VSS / ++ RM_IHPSG13_512x16_c2_2P_DEC02 +XDEC10<0> ADDR_N_I<5> ADDR_N_I<4> CS04<0> CS00<2> VDD VSS / ++ RM_IHPSG13_512x16_c2_2P_DEC02 +XDEC00<2> ADDR_N_I<7> ADDR_N_I<6> CS_I CS04<0> VDD VSS / ++ RM_IHPSG13_512x16_c2_2P_DEC00 +XDEC00<1> ADDR_N_I<5> ADDR_N_I<4> CS04<1> CS00<4> VDD VSS / ++ RM_IHPSG13_512x16_c2_2P_DEC00 +XDEC00<0> ADDR_N_I<5> ADDR_N_I<4> CS04<0> CS00<0> VDD VSS / ++ RM_IHPSG13_512x16_c2_2P_DEC00 +XI0 ADDR_N_I<7> VDD VSS / RSC_IHPSG13_TIEL +.ENDS +.SUBCKT RM_IHPSG13_512x16_c2_2P_ROWREG7 ACLK_N_I ADDR_I<6> ADDR_I<5> ADDR_I<4> ADDR_I<3> ++ ADDR_I<2> ADDR_I<1> ADDR_I<0> ADDR_N_O<6> ADDR_N_O<5> ADDR_N_O<4> ++ ADDR_N_O<3> ADDR_N_O<2> ADDR_N_O<1> ADDR_N_O<0> BIST_ADDR_I<6> ++ BIST_ADDR_I<5> BIST_ADDR_I<4> BIST_ADDR_I<3> BIST_ADDR_I<2> BIST_ADDR_I<1> ++ BIST_ADDR_I<0> BIST_EN_I VDD VSS +XINV<6> q_int<6> qn_int<6> VDD VSS / RSC_IHPSG13_CINVX2 +XINV<5> q_int<5> qn_int<5> VDD VSS / RSC_IHPSG13_CINVX2 +XINV<4> q_int<4> qn_int<4> VDD VSS / RSC_IHPSG13_CINVX2 +XINV<3> q_int<3> qn_int<3> VDD VSS / RSC_IHPSG13_CINVX2 +XINV<2> q_int<2> qn_int<2> VDD VSS / RSC_IHPSG13_CINVX2 +XINV<1> q_int<1> qn_int<1> VDD VSS / RSC_IHPSG13_CINVX2 +XINV<0> q_int<0> qn_int<0> VDD VSS / RSC_IHPSG13_CINVX2 +XDRV<6> qn_int<6> ADDR_N_O<6> VDD VSS / RSC_IHPSG13_CINVX8 +XDRV<5> qn_int<5> ADDR_N_O<5> VDD VSS / RSC_IHPSG13_CINVX8 +XDRV<4> qn_int<4> ADDR_N_O<4> VDD VSS / RSC_IHPSG13_CINVX8 +XDRV<3> qn_int<3> ADDR_N_O<3> VDD VSS / RSC_IHPSG13_CINVX8 +XDRV<2> qn_int<2> ADDR_N_O<2> VDD VSS / RSC_IHPSG13_CINVX8 +XDRV<1> qn_int<1> ADDR_N_O<1> VDD VSS / RSC_IHPSG13_CINVX8 +XDRV<0> qn_int<0> ADDR_N_O<0> VDD VSS / RSC_IHPSG13_CINVX8 +XDFF<6> BIST_EN_I BIST_ADDR_I<6> ACLK_N_I ADDR_I<6> q_int<6> net2<0> VDD ++ VSS / RSC_IHPSG13_DFNQMX2IX1 +XDFF<5> BIST_EN_I BIST_ADDR_I<5> ACLK_N_I ADDR_I<5> q_int<5> net2<1> VDD ++ VSS / RSC_IHPSG13_DFNQMX2IX1 +XDFF<4> BIST_EN_I BIST_ADDR_I<4> ACLK_N_I ADDR_I<4> q_int<4> net2<2> VDD ++ VSS / RSC_IHPSG13_DFNQMX2IX1 +XDFF<3> BIST_EN_I BIST_ADDR_I<3> ACLK_N_I ADDR_I<3> q_int<3> net2<3> VDD ++ VSS / RSC_IHPSG13_DFNQMX2IX1 +XDFF<2> BIST_EN_I BIST_ADDR_I<2> ACLK_N_I ADDR_I<2> q_int<2> net2<4> VDD ++ VSS / RSC_IHPSG13_DFNQMX2IX1 +XDFF<1> BIST_EN_I BIST_ADDR_I<1> ACLK_N_I ADDR_I<1> q_int<1> net2<5> VDD ++ VSS / RSC_IHPSG13_DFNQMX2IX1 +XDFF<0> BIST_EN_I BIST_ADDR_I<0> ACLK_N_I ADDR_I<0> q_int<0> net2<6> VDD ++ VSS / RSC_IHPSG13_DFNQMX2IX1 +XI11<7> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI11<6> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI11<5> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI11<4> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI11<3> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI11<2> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI11<1> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI11<0> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI12<1> VDD VSS / RSC_IHPSG13_FILLCAP4 +XI12<0> VDD VSS / RSC_IHPSG13_FILLCAP4 +.ENDS + +.SUBCKT RM_IHPSG13_512x16_c2_2P_ROWDEC4 ADDR_N_I<3> ADDR_N_I<2> ADDR_N_I<1> ADDR_N_I<0> ++ CS_I ECLK_I WL_O<15> WL_O<14> WL_O<13> WL_O<12> WL_O<11> WL_O<10> WL_O<9> ++ WL_O<8> WL_O<7> WL_O<6> WL_O<5> WL_O<4> WL_O<3> WL_O<2> WL_O<1> WL_O<0> ++ VDD VSS +XL2<12> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<11> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<10> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<9> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<8> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<7> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<6> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<5> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<4> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<3> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<2> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<1> VDD VSS / RSC_IHPSG13_FILLCAP8 +XSEL ADDR_N_I<3> ADDR_N_I<2> ADDR_N_I<1> ADDR_N_I<0> CS_I ECLK_I ECLK_H<1> ++ ECLK_B<0> ECLK_B<1> WL_O<15> WL_O<14> WL_O<13> WL_O<12> WL_O<11> WL_O<10> ++ WL_O<9> WL_O<8> WL_O<7> WL_O<6> WL_O<5> WL_O<4> WL_O<3> WL_O<2> WL_O<1> ++ WL_O<0> VDD VSS / RM_IHPSG13_512x16_c2_2P_DEC04 +.ENDS +.SUBCKT RM_IHPSG13_512x16_c2_2P_ROWREG4 ACLK_N_I ADDR_I<3> ADDR_I<2> ADDR_I<1> ADDR_I<0> ++ ADDR_N_O<3> ADDR_N_O<2> ADDR_N_O<1> ADDR_N_O<0> BIST_ADDR_I<3> ++ BIST_ADDR_I<2> BIST_ADDR_I<1> BIST_ADDR_I<0> BIST_EN_I VDD VSS +XINV<3> q_int<3> qn_int<3> VDD VSS / RSC_IHPSG13_CINVX2 +XINV<2> q_int<2> qn_int<2> VDD VSS / RSC_IHPSG13_CINVX2 +XINV<1> q_int<1> qn_int<1> VDD VSS / RSC_IHPSG13_CINVX2 +XINV<0> q_int<0> qn_int<0> VDD VSS / RSC_IHPSG13_CINVX2 +XDRV<3> qn_int<3> ADDR_N_O<3> VDD VSS / RSC_IHPSG13_CINVX8 +XDRV<2> qn_int<2> ADDR_N_O<2> VDD VSS / RSC_IHPSG13_CINVX8 +XDRV<1> qn_int<1> ADDR_N_O<1> VDD VSS / RSC_IHPSG13_CINVX8 +XDRV<0> qn_int<0> ADDR_N_O<0> VDD VSS / RSC_IHPSG13_CINVX8 +XDFF<3> BIST_EN_I BIST_ADDR_I<3> ACLK_N_I ADDR_I<3> q_int<3> net7<0> VDD ++ VSS / RSC_IHPSG13_DFNQMX2IX1 +XDFF<2> BIST_EN_I BIST_ADDR_I<2> ACLK_N_I ADDR_I<2> q_int<2> net7<1> VDD ++ VSS / RSC_IHPSG13_DFNQMX2IX1 +XDFF<1> BIST_EN_I BIST_ADDR_I<1> ACLK_N_I ADDR_I<1> q_int<1> net7<2> VDD ++ VSS / RSC_IHPSG13_DFNQMX2IX1 +XDFF<0> BIST_EN_I BIST_ADDR_I<0> ACLK_N_I ADDR_I<0> q_int<0> net7<3> VDD ++ VSS / RSC_IHPSG13_DFNQMX2IX1 +XI11<20> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI11<19> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI11<18> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI11<17> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI11<16> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI11<15> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI11<14> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI11<13> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI11<12> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI11<11> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI11<10> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI11<9> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI11<8> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI11<7> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI11<6> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI11<5> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI11<4> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI11<3> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI11<2> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI11<1> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI12<4> VDD VSS / RSC_IHPSG13_FILLCAP4 +XI12<3> VDD VSS / RSC_IHPSG13_FILLCAP4 +XI12<2> VDD VSS / RSC_IHPSG13_FILLCAP4 +XI12<1> VDD VSS / RSC_IHPSG13_FILLCAP4 +XI12<0> VDD VSS / RSC_IHPSG13_FILLCAP4 +.ENDS + + +.SUBCKT RM_IHPSG13_512x16_c2_1P_BITKIT_TAP BLC BLT NW PW VDD VSS +.ENDS +.SUBCKT RM_IHPSG13_512x16_c2_1P_BITKIT_16x2_TAP A_BLC<1> A_BLC<0> A_BLT<1> A_BLT<0> ++ VDD_CORE VSS +XITAP<1> A_BLC<1> A_BLT<1> VDD_CORE VSS VDD_CORE VSS ++ / RM_IHPSG13_512x16_c2_1P_BITKIT_TAP +XITAP<0> A_BLC<0> A_BLT<0> VDD_CORE VSS VDD_CORE VSS ++ / RM_IHPSG13_512x16_c2_1P_BITKIT_TAP +XIEDGEBP_COL1<1> BLC<1> BLT<1> VDD_CORE VSS VDD_CORE ++ VSS / RM_IHPSG13_512x16_c2_1P_BITKIT_EDGE_TB +XIEDGEBP_COL1<0> BLC<1> BLT<1> VDD_CORE VSS VDD_CORE ++ VSS / RM_IHPSG13_512x16_c2_1P_BITKIT_EDGE_TB +XIEDGEBP_COL2<1> BLC<0> BLT<0> VDD_CORE VSS VDD_CORE ++ VSS / RM_IHPSG13_512x16_c2_1P_BITKIT_EDGE_TB +XIEDGEBP_COL2<0> BLC<0> BLT<0> VDD_CORE VSS VDD_CORE ++ VSS / RM_IHPSG13_512x16_c2_1P_BITKIT_EDGE_TB +.ENDS +.SUBCKT RM_IHPSG13_512x16_c2_1P_BITKIT_16x2_TAP_LR VDD_CORE VSS +XCORNER<1> VDD_CORE VSS VDD_CORE VSS / ++ RM_IHPSG13_512x16_c2_1P_BITKIT_CORNER +XCORNER<0> VDD_CORE VSS VDD_CORE VSS / ++ RM_IHPSG13_512x16_c2_1P_BITKIT_CORNER +XTAP_BORDER VDD_CORE VSS VDD_CORE VSS / ++ RM_IHPSG13_512x16_c2_1P_BITKIT_TAP_LR +.ENDS +.SUBCKT RM_IHPSG13_512x16_c2_1P_DEC03 ADDR<1> ADDR<0> CS CS_OUT VDD VSS +XDECINV net1 CS_OUT VDD VSS / RSC_IHPSG13_INVX4 +XI0 VDD VSS / RSC_IHPSG13_FILLCAP4 +XDEC ADDR<1> ADDR<0> CS net1 VDD VSS / RSC_IHPSG13_NAND3X2 +.ENDS +.SUBCKT RM_IHPSG13_512x16_c2_1P_DEC02 ADDR<1> ADDR<0> CS CS_OUT VDD VSS +XDECINV net1 CS_OUT VDD VSS / RSC_IHPSG13_INVX4 +XDEC ADDR<1> NADDR<0> CS net1 VDD VSS / RSC_IHPSG13_NAND3X2 +XI2 VDD VSS / RSC_IHPSG13_FILLCAP4 +XADDRINV ADDR<0> NADDR<0> VDD VSS / RSC_IHPSG13_INVX2 +.ENDS +.SUBCKT RM_IHPSG13_512x16_c2_1P_ROWDEC8 ADDR_N_I<7> ADDR_N_I<6> ADDR_N_I<5> ADDR_N_I<4> ++ ADDR_N_I<3> ADDR_N_I<2> ADDR_N_I<1> ADDR_N_I<0> CS_I ECLK_I WL_O<255> ++ WL_O<254> WL_O<253> WL_O<252> WL_O<251> WL_O<250> WL_O<249> WL_O<248> ++ WL_O<247> WL_O<246> WL_O<245> WL_O<244> WL_O<243> WL_O<242> WL_O<241> ++ WL_O<240> WL_O<239> WL_O<238> WL_O<237> WL_O<236> WL_O<235> WL_O<234> ++ WL_O<233> WL_O<232> WL_O<231> WL_O<230> WL_O<229> WL_O<228> WL_O<227> ++ WL_O<226> WL_O<225> WL_O<224> WL_O<223> WL_O<222> WL_O<221> WL_O<220> ++ WL_O<219> WL_O<218> WL_O<217> WL_O<216> WL_O<215> WL_O<214> WL_O<213> ++ WL_O<212> WL_O<211> WL_O<210> WL_O<209> WL_O<208> WL_O<207> WL_O<206> ++ WL_O<205> WL_O<204> WL_O<203> WL_O<202> WL_O<201> WL_O<200> WL_O<199> ++ WL_O<198> WL_O<197> WL_O<196> WL_O<195> WL_O<194> WL_O<193> WL_O<192> ++ WL_O<191> WL_O<190> WL_O<189> WL_O<188> WL_O<187> WL_O<186> WL_O<185> ++ WL_O<184> WL_O<183> WL_O<182> WL_O<181> WL_O<180> WL_O<179> WL_O<178> ++ WL_O<177> WL_O<176> WL_O<175> WL_O<174> WL_O<173> WL_O<172> WL_O<171> ++ WL_O<170> WL_O<169> WL_O<168> WL_O<167> WL_O<166> WL_O<165> WL_O<164> ++ WL_O<163> WL_O<162> WL_O<161> WL_O<160> WL_O<159> WL_O<158> WL_O<157> ++ WL_O<156> WL_O<155> WL_O<154> WL_O<153> WL_O<152> WL_O<151> WL_O<150> ++ WL_O<149> WL_O<148> WL_O<147> WL_O<146> WL_O<145> WL_O<144> WL_O<143> ++ WL_O<142> WL_O<141> WL_O<140> WL_O<139> WL_O<138> WL_O<137> WL_O<136> ++ WL_O<135> WL_O<134> WL_O<133> WL_O<132> WL_O<131> WL_O<130> WL_O<129> ++ WL_O<128> WL_O<127> WL_O<126> WL_O<125> WL_O<124> WL_O<123> WL_O<122> ++ WL_O<121> WL_O<120> WL_O<119> WL_O<118> WL_O<117> WL_O<116> WL_O<115> ++ WL_O<114> WL_O<113> WL_O<112> WL_O<111> WL_O<110> WL_O<109> WL_O<108> ++ WL_O<107> WL_O<106> WL_O<105> WL_O<104> WL_O<103> WL_O<102> WL_O<101> ++ WL_O<100> WL_O<99> WL_O<98> WL_O<97> WL_O<96> WL_O<95> WL_O<94> WL_O<93> ++ WL_O<92> WL_O<91> WL_O<90> WL_O<89> WL_O<88> WL_O<87> WL_O<86> WL_O<85> ++ WL_O<84> WL_O<83> WL_O<82> WL_O<81> WL_O<80> WL_O<79> WL_O<78> WL_O<77> ++ WL_O<76> WL_O<75> WL_O<74> WL_O<73> WL_O<72> WL_O<71> WL_O<70> WL_O<69> ++ WL_O<68> WL_O<67> WL_O<66> WL_O<65> WL_O<64> WL_O<63> WL_O<62> WL_O<61> ++ WL_O<60> WL_O<59> WL_O<58> WL_O<57> WL_O<56> WL_O<55> WL_O<54> WL_O<53> ++ WL_O<52> WL_O<51> WL_O<50> WL_O<49> WL_O<48> WL_O<47> WL_O<46> WL_O<45> ++ WL_O<44> WL_O<43> WL_O<42> WL_O<41> WL_O<40> WL_O<39> WL_O<38> WL_O<37> ++ WL_O<36> WL_O<35> WL_O<34> WL_O<33> WL_O<32> WL_O<31> WL_O<30> WL_O<29> ++ WL_O<28> WL_O<27> WL_O<26> WL_O<25> WL_O<24> WL_O<23> WL_O<22> WL_O<21> ++ WL_O<20> WL_O<19> WL_O<18> WL_O<17> WL_O<16> WL_O<15> WL_O<14> WL_O<13> ++ WL_O<12> WL_O<11> WL_O<10> WL_O<9> WL_O<8> WL_O<7> WL_O<6> WL_O<5> WL_O<4> ++ WL_O<3> WL_O<2> WL_O<1> WL_O<0> VDD VSS +XDEC11<4> ADDR_N_I<7> ADDR_N_I<6> CS_I CS04<3> VDD VSS / ++ RM_IHPSG13_512x16_c2_1P_DEC03 +XDEC11<3> ADDR_N_I<5> ADDR_N_I<4> CS04<3> CS00<15> VDD VSS / ++ RM_IHPSG13_512x16_c2_1P_DEC03 +XDEC11<2> ADDR_N_I<5> ADDR_N_I<4> CS04<2> CS00<11> VDD VSS / ++ RM_IHPSG13_512x16_c2_1P_DEC03 +XDEC11<1> ADDR_N_I<5> ADDR_N_I<4> CS04<1> CS00<7> VDD VSS / ++ RM_IHPSG13_512x16_c2_1P_DEC03 +XDEC11<0> ADDR_N_I<5> ADDR_N_I<4> CS04<0> CS00<3> VDD VSS / ++ RM_IHPSG13_512x16_c2_1P_DEC03 +XL2<88> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<87> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<86> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<85> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<84> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<83> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<82> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<81> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<80> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<79> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<78> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<77> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<76> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<75> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<74> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<73> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<72> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<71> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<70> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<69> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<68> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<67> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<66> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<65> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<64> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<63> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<62> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<61> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<60> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<59> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<58> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<57> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<56> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<55> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<54> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<53> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<52> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<51> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<50> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<49> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<48> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<47> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<46> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<45> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<44> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<43> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<42> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<41> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<40> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<39> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<38> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<37> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<36> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<35> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<34> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<33> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<32> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<31> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<30> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<29> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<28> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<27> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<26> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<25> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<24> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<23> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<22> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<21> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<20> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<19> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<18> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<17> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<16> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<15> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<14> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<13> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<12> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<11> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<10> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<9> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<8> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<7> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<6> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<5> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<4> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<3> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<2> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<1> VDD VSS / RSC_IHPSG13_FILLCAP8 +XDEC10<4> ADDR_N_I<7> ADDR_N_I<6> CS_I CS04<2> VDD VSS / ++ RM_IHPSG13_512x16_c2_1P_DEC02 +XDEC10<3> ADDR_N_I<5> ADDR_N_I<4> CS04<3> CS00<14> VDD VSS / ++ RM_IHPSG13_512x16_c2_1P_DEC02 +XDEC10<2> ADDR_N_I<5> ADDR_N_I<4> CS04<2> CS00<10> VDD VSS / ++ RM_IHPSG13_512x16_c2_1P_DEC02 +XDEC10<1> ADDR_N_I<5> ADDR_N_I<4> CS04<1> CS00<6> VDD VSS / ++ RM_IHPSG13_512x16_c2_1P_DEC02 +XDEC10<0> ADDR_N_I<5> ADDR_N_I<4> CS04<0> CS00<2> VDD VSS / ++ RM_IHPSG13_512x16_c2_1P_DEC02 +XDEC00<4> ADDR_N_I<7> ADDR_N_I<6> CS_I CS04<0> VDD VSS / ++ RM_IHPSG13_512x16_c2_1P_DEC00 +XDEC00<3> ADDR_N_I<5> ADDR_N_I<4> CS04<3> CS00<12> VDD VSS / ++ RM_IHPSG13_512x16_c2_1P_DEC00 +XDEC00<2> ADDR_N_I<5> ADDR_N_I<4> CS04<2> CS00<8> VDD VSS / ++ RM_IHPSG13_512x16_c2_1P_DEC00 +XDEC00<1> ADDR_N_I<5> ADDR_N_I<4> CS04<1> CS00<4> VDD VSS / ++ RM_IHPSG13_512x16_c2_1P_DEC00 +XDEC00<0> ADDR_N_I<5> ADDR_N_I<4> CS04<0> CS00<0> VDD VSS / ++ RM_IHPSG13_512x16_c2_1P_DEC00 +XSEL<15> ADDR_N_I<3> ADDR_N_I<2> ADDR_N_I<1> ADDR_N_I<0> CS00<15> ECLK_H<15> ++ ECLK_H<16> ECLK_B<15> ECLK_B<16> WL_O<255> WL_O<254> WL_O<253> WL_O<252> ++ WL_O<251> WL_O<250> WL_O<249> WL_O<248> WL_O<247> WL_O<246> WL_O<245> ++ WL_O<244> WL_O<243> WL_O<242> WL_O<241> WL_O<240> VDD VSS / ++ RM_IHPSG13_512x16_c2_1P_DEC04 +XSEL<14> ADDR_N_I<3> ADDR_N_I<2> ADDR_N_I<1> ADDR_N_I<0> CS00<14> ECLK_H<14> ++ ECLK_H<15> ECLK_B<14> ECLK_B<15> WL_O<239> WL_O<238> WL_O<237> WL_O<236> ++ WL_O<235> WL_O<234> WL_O<233> WL_O<232> WL_O<231> WL_O<230> WL_O<229> ++ WL_O<228> WL_O<227> WL_O<226> WL_O<225> WL_O<224> VDD VSS / ++ RM_IHPSG13_512x16_c2_1P_DEC04 +XSEL<13> ADDR_N_I<3> ADDR_N_I<2> ADDR_N_I<1> ADDR_N_I<0> CS00<13> ECLK_H<13> ++ ECLK_H<14> ECLK_B<13> ECLK_B<14> WL_O<223> WL_O<222> WL_O<221> WL_O<220> ++ WL_O<219> WL_O<218> WL_O<217> WL_O<216> WL_O<215> WL_O<214> WL_O<213> ++ WL_O<212> WL_O<211> WL_O<210> WL_O<209> WL_O<208> VDD VSS / ++ RM_IHPSG13_512x16_c2_1P_DEC04 +XSEL<12> ADDR_N_I<3> ADDR_N_I<2> ADDR_N_I<1> ADDR_N_I<0> CS00<12> ECLK_H<12> ++ ECLK_H<13> ECLK_B<12> ECLK_B<13> WL_O<207> WL_O<206> WL_O<205> WL_O<204> ++ WL_O<203> WL_O<202> WL_O<201> WL_O<200> WL_O<199> WL_O<198> WL_O<197> ++ WL_O<196> WL_O<195> WL_O<194> WL_O<193> WL_O<192> VDD VSS / ++ RM_IHPSG13_512x16_c2_1P_DEC04 +XSEL<11> ADDR_N_I<3> ADDR_N_I<2> ADDR_N_I<1> ADDR_N_I<0> CS00<11> ECLK_H<11> ++ ECLK_H<12> ECLK_B<11> ECLK_B<12> WL_O<191> WL_O<190> WL_O<189> WL_O<188> ++ WL_O<187> WL_O<186> WL_O<185> WL_O<184> WL_O<183> WL_O<182> WL_O<181> ++ WL_O<180> WL_O<179> WL_O<178> WL_O<177> WL_O<176> VDD VSS / ++ RM_IHPSG13_512x16_c2_1P_DEC04 +XSEL<10> ADDR_N_I<3> ADDR_N_I<2> ADDR_N_I<1> ADDR_N_I<0> CS00<10> ECLK_H<10> ++ ECLK_H<11> ECLK_B<10> ECLK_B<11> WL_O<175> WL_O<174> WL_O<173> WL_O<172> ++ WL_O<171> WL_O<170> WL_O<169> WL_O<168> WL_O<167> WL_O<166> WL_O<165> ++ WL_O<164> WL_O<163> WL_O<162> WL_O<161> WL_O<160> VDD VSS / ++ RM_IHPSG13_512x16_c2_1P_DEC04 +XSEL<9> ADDR_N_I<3> ADDR_N_I<2> ADDR_N_I<1> ADDR_N_I<0> CS00<9> ECLK_H<9> ++ ECLK_H<10> ECLK_B<9> ECLK_B<10> WL_O<159> WL_O<158> WL_O<157> WL_O<156> ++ WL_O<155> WL_O<154> WL_O<153> WL_O<152> WL_O<151> WL_O<150> WL_O<149> ++ WL_O<148> WL_O<147> WL_O<146> WL_O<145> WL_O<144> VDD VSS / ++ RM_IHPSG13_512x16_c2_1P_DEC04 +XSEL<8> ADDR_N_I<3> ADDR_N_I<2> ADDR_N_I<1> ADDR_N_I<0> CS00<8> ECLK_H<8> ++ ECLK_H<9> ECLK_B<8> ECLK_B<9> WL_O<143> WL_O<142> WL_O<141> WL_O<140> ++ WL_O<139> WL_O<138> WL_O<137> WL_O<136> WL_O<135> WL_O<134> WL_O<133> ++ WL_O<132> WL_O<131> WL_O<130> WL_O<129> WL_O<128> VDD VSS / ++ RM_IHPSG13_512x16_c2_1P_DEC04 +XSEL<7> ADDR_N_I<3> ADDR_N_I<2> ADDR_N_I<1> ADDR_N_I<0> CS00<7> ECLK_H<7> ++ ECLK_H<8> ECLK_B<7> ECLK_B<8> WL_O<127> WL_O<126> WL_O<125> WL_O<124> ++ WL_O<123> WL_O<122> WL_O<121> WL_O<120> WL_O<119> WL_O<118> WL_O<117> ++ WL_O<116> WL_O<115> WL_O<114> WL_O<113> WL_O<112> VDD VSS / ++ RM_IHPSG13_512x16_c2_1P_DEC04 +XSEL<6> ADDR_N_I<3> ADDR_N_I<2> ADDR_N_I<1> ADDR_N_I<0> CS00<6> ECLK_H<6> ++ ECLK_H<7> ECLK_B<6> ECLK_B<7> WL_O<111> WL_O<110> WL_O<109> WL_O<108> ++ WL_O<107> WL_O<106> WL_O<105> WL_O<104> WL_O<103> WL_O<102> WL_O<101> ++ WL_O<100> WL_O<99> WL_O<98> WL_O<97> WL_O<96> VDD VSS / ++ RM_IHPSG13_512x16_c2_1P_DEC04 +XSEL<5> ADDR_N_I<3> ADDR_N_I<2> ADDR_N_I<1> ADDR_N_I<0> CS00<5> ECLK_H<5> ++ ECLK_H<6> ECLK_B<5> ECLK_B<6> WL_O<95> WL_O<94> WL_O<93> WL_O<92> WL_O<91> ++ WL_O<90> WL_O<89> WL_O<88> WL_O<87> WL_O<86> WL_O<85> WL_O<84> WL_O<83> ++ WL_O<82> WL_O<81> WL_O<80> VDD VSS / RM_IHPSG13_512x16_c2_1P_DEC04 +XSEL<4> ADDR_N_I<3> ADDR_N_I<2> ADDR_N_I<1> ADDR_N_I<0> CS00<4> ECLK_H<4> ++ ECLK_H<5> ECLK_B<4> ECLK_B<5> WL_O<79> WL_O<78> WL_O<77> WL_O<76> WL_O<75> ++ WL_O<74> WL_O<73> WL_O<72> WL_O<71> WL_O<70> WL_O<69> WL_O<68> WL_O<67> ++ WL_O<66> WL_O<65> WL_O<64> VDD VSS / RM_IHPSG13_512x16_c2_1P_DEC04 +XSEL<3> ADDR_N_I<3> ADDR_N_I<2> ADDR_N_I<1> ADDR_N_I<0> CS00<3> ECLK_H<3> ++ ECLK_H<4> ECLK_B<3> ECLK_B<4> WL_O<63> WL_O<62> WL_O<61> WL_O<60> WL_O<59> ++ WL_O<58> WL_O<57> WL_O<56> WL_O<55> WL_O<54> WL_O<53> WL_O<52> WL_O<51> ++ WL_O<50> WL_O<49> WL_O<48> VDD VSS / RM_IHPSG13_512x16_c2_1P_DEC04 +XSEL<2> ADDR_N_I<3> ADDR_N_I<2> ADDR_N_I<1> ADDR_N_I<0> CS00<2> ECLK_H<2> ++ ECLK_H<3> ECLK_B<2> ECLK_B<3> WL_O<47> WL_O<46> WL_O<45> WL_O<44> WL_O<43> ++ WL_O<42> WL_O<41> WL_O<40> WL_O<39> WL_O<38> WL_O<37> WL_O<36> WL_O<35> ++ WL_O<34> WL_O<33> WL_O<32> VDD VSS / RM_IHPSG13_512x16_c2_1P_DEC04 +XSEL<1> ADDR_N_I<3> ADDR_N_I<2> ADDR_N_I<1> ADDR_N_I<0> CS00<1> ECLK_H<1> ++ ECLK_H<2> ECLK_B<1> ECLK_B<2> WL_O<31> WL_O<30> WL_O<29> WL_O<28> WL_O<27> ++ WL_O<26> WL_O<25> WL_O<24> WL_O<23> WL_O<22> WL_O<21> WL_O<20> WL_O<19> ++ WL_O<18> WL_O<17> WL_O<16> VDD VSS / RM_IHPSG13_512x16_c2_1P_DEC04 +XSEL<0> ADDR_N_I<3> ADDR_N_I<2> ADDR_N_I<1> ADDR_N_I<0> CS00<0> ECLK_I ++ ECLK_H<1> ECLK_B<0> ECLK_B<1> WL_O<15> WL_O<14> WL_O<13> WL_O<12> WL_O<11> ++ WL_O<10> WL_O<9> WL_O<8> WL_O<7> WL_O<6> WL_O<5> WL_O<4> WL_O<3> WL_O<2> ++ WL_O<1> WL_O<0> VDD VSS / RM_IHPSG13_512x16_c2_1P_DEC04 +XDEC01<4> ADDR_N_I<7> ADDR_N_I<6> CS_I CS04<1> VDD VSS / ++ RM_IHPSG13_512x16_c2_1P_DEC01 +XDEC01<3> ADDR_N_I<5> ADDR_N_I<4> CS04<3> CS00<13> VDD VSS / ++ RM_IHPSG13_512x16_c2_1P_DEC01 +XDEC01<2> ADDR_N_I<5> ADDR_N_I<4> CS04<2> CS00<9> VDD VSS / ++ RM_IHPSG13_512x16_c2_1P_DEC01 +XDEC01<1> ADDR_N_I<5> ADDR_N_I<4> CS04<1> CS00<5> VDD VSS / ++ RM_IHPSG13_512x16_c2_1P_DEC01 +XDEC01<0> ADDR_N_I<5> ADDR_N_I<4> CS04<0> CS00<1> VDD VSS / ++ RM_IHPSG13_512x16_c2_1P_DEC01 +.ENDS +.SUBCKT RM_IHPSG13_512x16_c2_1P_ROWREG8 ACLK_N_I ADDR_I<7> ADDR_I<6> ADDR_I<5> ADDR_I<4> ++ ADDR_I<3> ADDR_I<2> ADDR_I<1> ADDR_I<0> ADDR_N_O<7> ADDR_N_O<6> ADDR_N_O<5> ++ ADDR_N_O<4> ADDR_N_O<3> ADDR_N_O<2> ADDR_N_O<1> ADDR_N_O<0> BIST_ADDR_I<7> ++ BIST_ADDR_I<6> BIST_ADDR_I<5> BIST_ADDR_I<4> BIST_ADDR_I<3> BIST_ADDR_I<2> ++ BIST_ADDR_I<1> BIST_ADDR_I<0> BIST_EN_I VDD VSS +XINV<7> q_int<7> qn_int<7> VDD VSS / RSC_IHPSG13_CINVX2 +XINV<6> q_int<6> qn_int<6> VDD VSS / RSC_IHPSG13_CINVX2 +XINV<5> q_int<5> qn_int<5> VDD VSS / RSC_IHPSG13_CINVX2 +XINV<4> q_int<4> qn_int<4> VDD VSS / RSC_IHPSG13_CINVX2 +XINV<3> q_int<3> qn_int<3> VDD VSS / RSC_IHPSG13_CINVX2 +XINV<2> q_int<2> qn_int<2> VDD VSS / RSC_IHPSG13_CINVX2 +XINV<1> q_int<1> qn_int<1> VDD VSS / RSC_IHPSG13_CINVX2 +XINV<0> q_int<0> qn_int<0> VDD VSS / RSC_IHPSG13_CINVX2 +XDRV<7> qn_int<7> ADDR_N_O<7> VDD VSS / RSC_IHPSG13_CINVX8 +XDRV<6> qn_int<6> ADDR_N_O<6> VDD VSS / RSC_IHPSG13_CINVX8 +XDRV<5> qn_int<5> ADDR_N_O<5> VDD VSS / RSC_IHPSG13_CINVX8 +XDRV<4> qn_int<4> ADDR_N_O<4> VDD VSS / RSC_IHPSG13_CINVX8 +XDRV<3> qn_int<3> ADDR_N_O<3> VDD VSS / RSC_IHPSG13_CINVX8 +XDRV<2> qn_int<2> ADDR_N_O<2> VDD VSS / RSC_IHPSG13_CINVX8 +XDRV<1> qn_int<1> ADDR_N_O<1> VDD VSS / RSC_IHPSG13_CINVX8 +XDRV<0> qn_int<0> ADDR_N_O<0> VDD VSS / RSC_IHPSG13_CINVX8 +XDFF<7> BIST_EN_I BIST_ADDR_I<7> ACLK_N_I ADDR_I<7> q_int<7> net2<0> VDD ++ VSS / RSC_IHPSG13_DFNQMX2IX1 +XDFF<6> BIST_EN_I BIST_ADDR_I<6> ACLK_N_I ADDR_I<6> q_int<6> net2<1> VDD ++ VSS / RSC_IHPSG13_DFNQMX2IX1 +XDFF<5> BIST_EN_I BIST_ADDR_I<5> ACLK_N_I ADDR_I<5> q_int<5> net2<2> VDD ++ VSS / RSC_IHPSG13_DFNQMX2IX1 +XDFF<4> BIST_EN_I BIST_ADDR_I<4> ACLK_N_I ADDR_I<4> q_int<4> net2<3> VDD ++ VSS / RSC_IHPSG13_DFNQMX2IX1 +XDFF<3> BIST_EN_I BIST_ADDR_I<3> ACLK_N_I ADDR_I<3> q_int<3> net2<4> VDD ++ VSS / RSC_IHPSG13_DFNQMX2IX1 +XDFF<2> BIST_EN_I BIST_ADDR_I<2> ACLK_N_I ADDR_I<2> q_int<2> net2<5> VDD ++ VSS / RSC_IHPSG13_DFNQMX2IX1 +XDFF<1> BIST_EN_I BIST_ADDR_I<1> ACLK_N_I ADDR_I<1> q_int<1> net2<6> VDD ++ VSS / RSC_IHPSG13_DFNQMX2IX1 +XDFF<0> BIST_EN_I BIST_ADDR_I<0> ACLK_N_I ADDR_I<0> q_int<0> net2<7> VDD ++ VSS / RSC_IHPSG13_DFNQMX2IX1 +XI11<4> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI11<3> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI11<2> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI11<1> VDD VSS / RSC_IHPSG13_FILLCAP8 +.ENDS + +.SUBCKT RM_IHPSG13_512x16_c2_1P_ROWDEC9 ADDR_N_I<8> ADDR_N_I<7> ADDR_N_I<6> ADDR_N_I<5> ++ ADDR_N_I<4> ADDR_N_I<3> ADDR_N_I<2> ADDR_N_I<1> ADDR_N_I<0> CS_I ECLK_I ++ WL_O<511> WL_O<510> WL_O<509> WL_O<508> WL_O<507> WL_O<506> WL_O<505> ++ WL_O<504> WL_O<503> WL_O<502> WL_O<501> WL_O<500> WL_O<499> WL_O<498> ++ WL_O<497> WL_O<496> WL_O<495> WL_O<494> WL_O<493> WL_O<492> WL_O<491> ++ WL_O<490> WL_O<489> WL_O<488> WL_O<487> WL_O<486> WL_O<485> WL_O<484> ++ WL_O<483> WL_O<482> WL_O<481> WL_O<480> WL_O<479> WL_O<478> WL_O<477> ++ WL_O<476> WL_O<475> WL_O<474> WL_O<473> WL_O<472> WL_O<471> WL_O<470> ++ WL_O<469> WL_O<468> WL_O<467> WL_O<466> WL_O<465> WL_O<464> WL_O<463> ++ WL_O<462> WL_O<461> WL_O<460> WL_O<459> WL_O<458> WL_O<457> WL_O<456> ++ WL_O<455> WL_O<454> WL_O<453> WL_O<452> WL_O<451> WL_O<450> WL_O<449> ++ WL_O<448> WL_O<447> WL_O<446> WL_O<445> WL_O<444> WL_O<443> WL_O<442> ++ WL_O<441> WL_O<440> WL_O<439> WL_O<438> WL_O<437> WL_O<436> WL_O<435> ++ WL_O<434> WL_O<433> WL_O<432> WL_O<431> WL_O<430> WL_O<429> WL_O<428> ++ WL_O<427> WL_O<426> WL_O<425> WL_O<424> WL_O<423> WL_O<422> WL_O<421> ++ WL_O<420> WL_O<419> WL_O<418> WL_O<417> WL_O<416> WL_O<415> WL_O<414> ++ WL_O<413> WL_O<412> WL_O<411> WL_O<410> WL_O<409> WL_O<408> WL_O<407> ++ WL_O<406> WL_O<405> WL_O<404> WL_O<403> WL_O<402> WL_O<401> WL_O<400> ++ WL_O<399> WL_O<398> WL_O<397> WL_O<396> WL_O<395> WL_O<394> WL_O<393> ++ WL_O<392> WL_O<391> WL_O<390> WL_O<389> WL_O<388> WL_O<387> WL_O<386> ++ WL_O<385> WL_O<384> WL_O<383> WL_O<382> WL_O<381> WL_O<380> WL_O<379> ++ WL_O<378> WL_O<377> WL_O<376> WL_O<375> WL_O<374> WL_O<373> WL_O<372> ++ WL_O<371> WL_O<370> WL_O<369> WL_O<368> WL_O<367> WL_O<366> WL_O<365> ++ WL_O<364> WL_O<363> WL_O<362> WL_O<361> WL_O<360> WL_O<359> WL_O<358> ++ WL_O<357> WL_O<356> WL_O<355> WL_O<354> WL_O<353> WL_O<352> WL_O<351> ++ WL_O<350> WL_O<349> WL_O<348> WL_O<347> WL_O<346> WL_O<345> WL_O<344> ++ WL_O<343> WL_O<342> WL_O<341> WL_O<340> WL_O<339> WL_O<338> WL_O<337> ++ WL_O<336> WL_O<335> WL_O<334> WL_O<333> WL_O<332> WL_O<331> WL_O<330> ++ WL_O<329> WL_O<328> WL_O<327> WL_O<326> WL_O<325> WL_O<324> WL_O<323> ++ WL_O<322> WL_O<321> WL_O<320> WL_O<319> WL_O<318> WL_O<317> WL_O<316> ++ WL_O<315> WL_O<314> WL_O<313> WL_O<312> WL_O<311> WL_O<310> WL_O<309> ++ WL_O<308> WL_O<307> WL_O<306> WL_O<305> WL_O<304> WL_O<303> WL_O<302> ++ WL_O<301> WL_O<300> WL_O<299> WL_O<298> WL_O<297> WL_O<296> WL_O<295> ++ WL_O<294> WL_O<293> WL_O<292> WL_O<291> WL_O<290> WL_O<289> WL_O<288> ++ WL_O<287> WL_O<286> WL_O<285> WL_O<284> WL_O<283> WL_O<282> WL_O<281> ++ WL_O<280> WL_O<279> WL_O<278> WL_O<277> WL_O<276> WL_O<275> WL_O<274> ++ WL_O<273> WL_O<272> WL_O<271> WL_O<270> WL_O<269> WL_O<268> WL_O<267> ++ WL_O<266> WL_O<265> WL_O<264> WL_O<263> WL_O<262> WL_O<261> WL_O<260> ++ WL_O<259> WL_O<258> WL_O<257> WL_O<256> WL_O<255> WL_O<254> WL_O<253> ++ WL_O<252> WL_O<251> WL_O<250> WL_O<249> WL_O<248> WL_O<247> WL_O<246> ++ WL_O<245> WL_O<244> WL_O<243> WL_O<242> WL_O<241> WL_O<240> WL_O<239> ++ WL_O<238> WL_O<237> WL_O<236> WL_O<235> WL_O<234> WL_O<233> WL_O<232> ++ WL_O<231> WL_O<230> WL_O<229> WL_O<228> WL_O<227> WL_O<226> WL_O<225> ++ WL_O<224> WL_O<223> WL_O<222> WL_O<221> WL_O<220> WL_O<219> WL_O<218> ++ WL_O<217> WL_O<216> WL_O<215> WL_O<214> WL_O<213> WL_O<212> WL_O<211> ++ WL_O<210> WL_O<209> WL_O<208> WL_O<207> WL_O<206> WL_O<205> WL_O<204> ++ WL_O<203> WL_O<202> WL_O<201> WL_O<200> WL_O<199> WL_O<198> WL_O<197> ++ WL_O<196> WL_O<195> WL_O<194> WL_O<193> WL_O<192> WL_O<191> WL_O<190> ++ WL_O<189> WL_O<188> WL_O<187> WL_O<186> WL_O<185> WL_O<184> WL_O<183> ++ WL_O<182> WL_O<181> WL_O<180> WL_O<179> WL_O<178> WL_O<177> WL_O<176> ++ WL_O<175> WL_O<174> WL_O<173> WL_O<172> WL_O<171> WL_O<170> WL_O<169> ++ WL_O<168> WL_O<167> WL_O<166> WL_O<165> WL_O<164> WL_O<163> WL_O<162> ++ WL_O<161> WL_O<160> WL_O<159> WL_O<158> WL_O<157> WL_O<156> WL_O<155> ++ WL_O<154> WL_O<153> WL_O<152> WL_O<151> WL_O<150> WL_O<149> WL_O<148> ++ WL_O<147> WL_O<146> WL_O<145> WL_O<144> WL_O<143> WL_O<142> WL_O<141> ++ WL_O<140> WL_O<139> WL_O<138> WL_O<137> WL_O<136> WL_O<135> WL_O<134> ++ WL_O<133> WL_O<132> WL_O<131> WL_O<130> WL_O<129> WL_O<128> WL_O<127> ++ WL_O<126> WL_O<125> WL_O<124> WL_O<123> WL_O<122> WL_O<121> WL_O<120> ++ WL_O<119> WL_O<118> WL_O<117> WL_O<116> WL_O<115> WL_O<114> WL_O<113> ++ WL_O<112> WL_O<111> WL_O<110> WL_O<109> WL_O<108> WL_O<107> WL_O<106> ++ WL_O<105> WL_O<104> WL_O<103> WL_O<102> WL_O<101> WL_O<100> WL_O<99> ++ WL_O<98> WL_O<97> WL_O<96> WL_O<95> WL_O<94> WL_O<93> WL_O<92> WL_O<91> ++ WL_O<90> WL_O<89> WL_O<88> WL_O<87> WL_O<86> WL_O<85> WL_O<84> WL_O<83> ++ WL_O<82> WL_O<81> WL_O<80> WL_O<79> WL_O<78> WL_O<77> WL_O<76> WL_O<75> ++ WL_O<74> WL_O<73> WL_O<72> WL_O<71> WL_O<70> WL_O<69> WL_O<68> WL_O<67> ++ WL_O<66> WL_O<65> WL_O<64> WL_O<63> WL_O<62> WL_O<61> WL_O<60> WL_O<59> ++ WL_O<58> WL_O<57> WL_O<56> WL_O<55> WL_O<54> WL_O<53> WL_O<52> WL_O<51> ++ WL_O<50> WL_O<49> WL_O<48> WL_O<47> WL_O<46> WL_O<45> WL_O<44> WL_O<43> ++ WL_O<42> WL_O<41> WL_O<40> WL_O<39> WL_O<38> WL_O<37> WL_O<36> WL_O<35> ++ WL_O<34> WL_O<33> WL_O<32> WL_O<31> WL_O<30> WL_O<29> WL_O<28> WL_O<27> ++ WL_O<26> WL_O<25> WL_O<24> WL_O<23> WL_O<22> WL_O<21> WL_O<20> WL_O<19> ++ WL_O<18> WL_O<17> WL_O<16> WL_O<15> WL_O<14> WL_O<13> WL_O<12> WL_O<11> ++ WL_O<10> WL_O<9> WL_O<8> WL_O<7> WL_O<6> WL_O<5> WL_O<4> WL_O<3> WL_O<2> ++ WL_O<1> WL_O<0> VDD VSS +XL2<172> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<171> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<170> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<169> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<168> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<167> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<166> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<165> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<164> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<163> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<162> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<161> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<160> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<159> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<158> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<157> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<156> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<155> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<154> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<153> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<152> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<151> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<150> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<149> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<148> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<147> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<146> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<145> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<144> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<143> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<142> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<141> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<140> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<139> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<138> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<137> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<136> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<135> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<134> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<133> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<132> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<131> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<130> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<129> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<128> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<127> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<126> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<125> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<124> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<123> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<122> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<121> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<120> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<119> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<118> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<117> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<116> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<115> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<114> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<113> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<112> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<111> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<110> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<109> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<108> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<107> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<106> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<105> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<104> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<103> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<102> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<101> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<100> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<99> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<98> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<97> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<96> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<95> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<94> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<93> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<92> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<91> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<90> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<89> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<88> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<87> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<86> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<85> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<84> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<83> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<82> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<81> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<80> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<79> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<78> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<77> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<76> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<75> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<74> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<73> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<72> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<71> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<70> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<69> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<68> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<67> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<66> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<65> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<64> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<63> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<62> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<61> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<60> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<59> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<58> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<57> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<56> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<55> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<54> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<53> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<52> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<51> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<50> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<49> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<48> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<47> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<46> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<45> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<44> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<43> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<42> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<41> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<40> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<39> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<38> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<37> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<36> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<35> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<34> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<33> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<32> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<31> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<30> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<29> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<28> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<27> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<26> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<25> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<24> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<23> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<22> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<21> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<20> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<19> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<18> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<17> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<16> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<15> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<14> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<13> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<12> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<11> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<10> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<9> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<8> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<7> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<6> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<5> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<4> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<3> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<2> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<1> VDD VSS / RSC_IHPSG13_FILLCAP8 +XDEC11<9> ADDR_N_I<7> ADDR_N_I<6> CS04<1> CS02<7> VDD VSS / ++ RM_IHPSG13_512x16_c2_1P_DEC03 +XDEC11<8> ADDR_N_I<7> ADDR_N_I<6> CS04<0> CS02<3> VDD VSS / ++ RM_IHPSG13_512x16_c2_1P_DEC03 +XDEC11<7> ADDR_N_I<5> ADDR_N_I<4> CS02<7> CS00<31> VDD VSS / ++ RM_IHPSG13_512x16_c2_1P_DEC03 +XDEC11<6> ADDR_N_I<5> ADDR_N_I<4> CS02<6> CS00<27> VDD VSS / ++ RM_IHPSG13_512x16_c2_1P_DEC03 +XDEC11<5> ADDR_N_I<5> ADDR_N_I<4> CS02<5> CS00<23> VDD VSS / ++ RM_IHPSG13_512x16_c2_1P_DEC03 +XDEC11<4> ADDR_N_I<5> ADDR_N_I<4> CS02<4> CS00<19> VDD VSS / ++ RM_IHPSG13_512x16_c2_1P_DEC03 +XDEC11<3> ADDR_N_I<5> ADDR_N_I<4> CS02<3> CS00<15> VDD VSS / ++ RM_IHPSG13_512x16_c2_1P_DEC03 +XDEC11<2> ADDR_N_I<5> ADDR_N_I<4> CS02<2> CS00<11> VDD VSS / ++ RM_IHPSG13_512x16_c2_1P_DEC03 +XDEC11<1> ADDR_N_I<5> ADDR_N_I<4> CS02<1> CS00<7> VDD VSS / ++ RM_IHPSG13_512x16_c2_1P_DEC03 +XDEC11<0> ADDR_N_I<5> ADDR_N_I<4> CS02<0> CS00<3> VDD VSS / ++ RM_IHPSG13_512x16_c2_1P_DEC03 +XDEC00<10> ADDR_N_I<9> ADDR_N_I<8> CS_I CS04<0> VDD VSS / ++ RM_IHPSG13_512x16_c2_1P_DEC00 +XDEC00<9> ADDR_N_I<7> ADDR_N_I<6> CS04<1> CS02<4> VDD VSS / ++ RM_IHPSG13_512x16_c2_1P_DEC00 +XDEC00<8> ADDR_N_I<7> ADDR_N_I<6> CS04<0> CS02<0> VDD VSS / ++ RM_IHPSG13_512x16_c2_1P_DEC00 +XDEC00<7> ADDR_N_I<5> ADDR_N_I<4> CS02<7> CS00<28> VDD VSS / ++ RM_IHPSG13_512x16_c2_1P_DEC00 +XDEC00<6> ADDR_N_I<5> ADDR_N_I<4> CS02<6> CS00<24> VDD VSS / ++ RM_IHPSG13_512x16_c2_1P_DEC00 +XDEC00<5> ADDR_N_I<5> ADDR_N_I<4> CS02<5> CS00<20> VDD VSS / ++ RM_IHPSG13_512x16_c2_1P_DEC00 +XDEC00<4> ADDR_N_I<5> ADDR_N_I<4> CS02<4> CS00<16> VDD VSS / ++ RM_IHPSG13_512x16_c2_1P_DEC00 +XDEC00<3> ADDR_N_I<5> ADDR_N_I<4> CS02<3> CS00<12> VDD VSS / ++ RM_IHPSG13_512x16_c2_1P_DEC00 +XDEC00<2> ADDR_N_I<5> ADDR_N_I<4> CS02<2> CS00<8> VDD VSS / ++ RM_IHPSG13_512x16_c2_1P_DEC00 +XDEC00<1> ADDR_N_I<5> ADDR_N_I<4> CS02<1> CS00<4> VDD VSS / ++ RM_IHPSG13_512x16_c2_1P_DEC00 +XDEC00<0> ADDR_N_I<5> ADDR_N_I<4> CS02<0> CS00<0> VDD VSS / ++ RM_IHPSG13_512x16_c2_1P_DEC00 +XSEL<31> ADDR_N_I<3> ADDR_N_I<2> ADDR_N_I<1> ADDR_N_I<0> CS00<31> ECLK_H<31> ++ ECLK_H<32> ECLK_B<31> ECLK_B<32> WL_O<511> WL_O<510> WL_O<509> WL_O<508> ++ WL_O<507> WL_O<506> WL_O<505> WL_O<504> WL_O<503> WL_O<502> WL_O<501> ++ WL_O<500> WL_O<499> WL_O<498> WL_O<497> WL_O<496> VDD VSS / ++ RM_IHPSG13_512x16_c2_1P_DEC04 +XSEL<30> ADDR_N_I<3> ADDR_N_I<2> ADDR_N_I<1> ADDR_N_I<0> CS00<30> ECLK_H<30> ++ ECLK_H<31> ECLK_B<30> ECLK_B<31> WL_O<495> WL_O<494> WL_O<493> WL_O<492> ++ WL_O<491> WL_O<490> WL_O<489> WL_O<488> WL_O<487> WL_O<486> WL_O<485> ++ WL_O<484> WL_O<483> WL_O<482> WL_O<481> WL_O<480> VDD VSS / ++ RM_IHPSG13_512x16_c2_1P_DEC04 +XSEL<29> ADDR_N_I<3> ADDR_N_I<2> ADDR_N_I<1> ADDR_N_I<0> CS00<29> ECLK_H<29> ++ ECLK_H<30> ECLK_B<29> ECLK_B<30> WL_O<479> WL_O<478> WL_O<477> WL_O<476> ++ WL_O<475> WL_O<474> WL_O<473> WL_O<472> WL_O<471> WL_O<470> WL_O<469> ++ WL_O<468> WL_O<467> WL_O<466> WL_O<465> WL_O<464> VDD VSS / ++ RM_IHPSG13_512x16_c2_1P_DEC04 +XSEL<28> ADDR_N_I<3> ADDR_N_I<2> ADDR_N_I<1> ADDR_N_I<0> CS00<28> ECLK_H<28> ++ ECLK_H<29> ECLK_B<28> ECLK_B<29> WL_O<463> WL_O<462> WL_O<461> WL_O<460> ++ WL_O<459> WL_O<458> WL_O<457> WL_O<456> WL_O<455> WL_O<454> WL_O<453> ++ WL_O<452> WL_O<451> WL_O<450> WL_O<449> WL_O<448> VDD VSS / ++ RM_IHPSG13_512x16_c2_1P_DEC04 +XSEL<27> ADDR_N_I<3> ADDR_N_I<2> ADDR_N_I<1> ADDR_N_I<0> CS00<27> ECLK_H<27> ++ ECLK_H<28> ECLK_B<27> ECLK_B<28> WL_O<447> WL_O<446> WL_O<445> WL_O<444> ++ WL_O<443> WL_O<442> WL_O<441> WL_O<440> WL_O<439> WL_O<438> WL_O<437> ++ WL_O<436> WL_O<435> WL_O<434> WL_O<433> WL_O<432> VDD VSS / ++ RM_IHPSG13_512x16_c2_1P_DEC04 +XSEL<26> ADDR_N_I<3> ADDR_N_I<2> ADDR_N_I<1> ADDR_N_I<0> CS00<26> ECLK_H<26> ++ ECLK_H<27> ECLK_B<26> ECLK_B<27> WL_O<431> WL_O<430> WL_O<429> WL_O<428> ++ WL_O<427> WL_O<426> WL_O<425> WL_O<424> WL_O<423> WL_O<422> WL_O<421> ++ WL_O<420> WL_O<419> WL_O<418> WL_O<417> WL_O<416> VDD VSS / ++ RM_IHPSG13_512x16_c2_1P_DEC04 +XSEL<25> ADDR_N_I<3> ADDR_N_I<2> ADDR_N_I<1> ADDR_N_I<0> CS00<25> ECLK_H<25> ++ ECLK_H<26> ECLK_B<25> ECLK_B<26> WL_O<415> WL_O<414> WL_O<413> WL_O<412> ++ WL_O<411> WL_O<410> WL_O<409> WL_O<408> WL_O<407> WL_O<406> WL_O<405> ++ WL_O<404> WL_O<403> WL_O<402> WL_O<401> WL_O<400> VDD VSS / ++ RM_IHPSG13_512x16_c2_1P_DEC04 +XSEL<24> ADDR_N_I<3> ADDR_N_I<2> ADDR_N_I<1> ADDR_N_I<0> CS00<24> ECLK_H<24> ++ ECLK_H<25> ECLK_B<24> ECLK_B<25> WL_O<399> WL_O<398> WL_O<397> WL_O<396> ++ WL_O<395> WL_O<394> WL_O<393> WL_O<392> WL_O<391> WL_O<390> WL_O<389> ++ WL_O<388> WL_O<387> WL_O<386> WL_O<385> WL_O<384> VDD VSS / ++ RM_IHPSG13_512x16_c2_1P_DEC04 +XSEL<23> ADDR_N_I<3> ADDR_N_I<2> ADDR_N_I<1> ADDR_N_I<0> CS00<23> ECLK_H<23> ++ ECLK_H<24> ECLK_B<23> ECLK_B<24> WL_O<383> WL_O<382> WL_O<381> WL_O<380> ++ WL_O<379> WL_O<378> WL_O<377> WL_O<376> WL_O<375> WL_O<374> WL_O<373> ++ WL_O<372> WL_O<371> WL_O<370> WL_O<369> WL_O<368> VDD VSS / ++ RM_IHPSG13_512x16_c2_1P_DEC04 +XSEL<22> ADDR_N_I<3> ADDR_N_I<2> ADDR_N_I<1> ADDR_N_I<0> CS00<22> ECLK_H<22> ++ ECLK_H<23> ECLK_B<22> ECLK_B<23> WL_O<367> WL_O<366> WL_O<365> WL_O<364> ++ WL_O<363> WL_O<362> WL_O<361> WL_O<360> WL_O<359> WL_O<358> WL_O<357> ++ WL_O<356> WL_O<355> WL_O<354> WL_O<353> WL_O<352> VDD VSS / ++ RM_IHPSG13_512x16_c2_1P_DEC04 +XSEL<21> ADDR_N_I<3> ADDR_N_I<2> ADDR_N_I<1> ADDR_N_I<0> CS00<21> ECLK_H<21> ++ ECLK_H<22> ECLK_B<21> ECLK_B<22> WL_O<351> WL_O<350> WL_O<349> WL_O<348> ++ WL_O<347> WL_O<346> WL_O<345> WL_O<344> WL_O<343> WL_O<342> WL_O<341> ++ WL_O<340> WL_O<339> WL_O<338> WL_O<337> WL_O<336> VDD VSS / ++ RM_IHPSG13_512x16_c2_1P_DEC04 +XSEL<20> ADDR_N_I<3> ADDR_N_I<2> ADDR_N_I<1> ADDR_N_I<0> CS00<20> ECLK_H<20> ++ ECLK_H<21> ECLK_B<20> ECLK_B<21> WL_O<335> WL_O<334> WL_O<333> WL_O<332> ++ WL_O<331> WL_O<330> WL_O<329> WL_O<328> WL_O<327> WL_O<326> WL_O<325> ++ WL_O<324> WL_O<323> WL_O<322> WL_O<321> WL_O<320> VDD VSS / ++ RM_IHPSG13_512x16_c2_1P_DEC04 +XSEL<19> ADDR_N_I<3> ADDR_N_I<2> ADDR_N_I<1> ADDR_N_I<0> CS00<19> ECLK_H<19> ++ ECLK_H<20> ECLK_B<19> ECLK_B<20> WL_O<319> WL_O<318> WL_O<317> WL_O<316> ++ WL_O<315> WL_O<314> WL_O<313> WL_O<312> WL_O<311> WL_O<310> WL_O<309> ++ WL_O<308> WL_O<307> WL_O<306> WL_O<305> WL_O<304> VDD VSS / ++ RM_IHPSG13_512x16_c2_1P_DEC04 +XSEL<18> ADDR_N_I<3> ADDR_N_I<2> ADDR_N_I<1> ADDR_N_I<0> CS00<18> ECLK_H<18> ++ ECLK_H<19> ECLK_B<18> ECLK_B<19> WL_O<303> WL_O<302> WL_O<301> WL_O<300> ++ WL_O<299> WL_O<298> WL_O<297> WL_O<296> WL_O<295> WL_O<294> WL_O<293> ++ WL_O<292> WL_O<291> WL_O<290> WL_O<289> WL_O<288> VDD VSS / ++ RM_IHPSG13_512x16_c2_1P_DEC04 +XSEL<17> ADDR_N_I<3> ADDR_N_I<2> ADDR_N_I<1> ADDR_N_I<0> CS00<17> ECLK_H<17> ++ ECLK_H<18> ECLK_B<17> ECLK_B<18> WL_O<287> WL_O<286> WL_O<285> WL_O<284> ++ WL_O<283> WL_O<282> WL_O<281> WL_O<280> WL_O<279> WL_O<278> WL_O<277> ++ WL_O<276> WL_O<275> WL_O<274> WL_O<273> WL_O<272> VDD VSS / ++ RM_IHPSG13_512x16_c2_1P_DEC04 +XSEL<16> ADDR_N_I<3> ADDR_N_I<2> ADDR_N_I<1> ADDR_N_I<0> CS00<16> ECLK_H<16> ++ ECLK_H<17> ECLK_B<16> ECLK_B<17> WL_O<271> WL_O<270> WL_O<269> WL_O<268> ++ WL_O<267> WL_O<266> WL_O<265> WL_O<264> WL_O<263> WL_O<262> WL_O<261> ++ WL_O<260> WL_O<259> WL_O<258> WL_O<257> WL_O<256> VDD VSS / ++ RM_IHPSG13_512x16_c2_1P_DEC04 +XSEL<15> ADDR_N_I<3> ADDR_N_I<2> ADDR_N_I<1> ADDR_N_I<0> CS00<15> ECLK_H<15> ++ ECLK_H<16> ECLK_B<15> ECLK_B<16> WL_O<255> WL_O<254> WL_O<253> WL_O<252> ++ WL_O<251> WL_O<250> WL_O<249> WL_O<248> WL_O<247> WL_O<246> WL_O<245> ++ WL_O<244> WL_O<243> WL_O<242> WL_O<241> WL_O<240> VDD VSS / ++ RM_IHPSG13_512x16_c2_1P_DEC04 +XSEL<14> ADDR_N_I<3> ADDR_N_I<2> ADDR_N_I<1> ADDR_N_I<0> CS00<14> ECLK_H<14> ++ ECLK_H<15> ECLK_B<14> ECLK_B<15> WL_O<239> WL_O<238> WL_O<237> WL_O<236> ++ WL_O<235> WL_O<234> WL_O<233> WL_O<232> WL_O<231> WL_O<230> WL_O<229> ++ WL_O<228> WL_O<227> WL_O<226> WL_O<225> WL_O<224> VDD VSS / ++ RM_IHPSG13_512x16_c2_1P_DEC04 +XSEL<13> ADDR_N_I<3> ADDR_N_I<2> ADDR_N_I<1> ADDR_N_I<0> CS00<13> ECLK_H<13> ++ ECLK_H<14> ECLK_B<13> ECLK_B<14> WL_O<223> WL_O<222> WL_O<221> WL_O<220> ++ WL_O<219> WL_O<218> WL_O<217> WL_O<216> WL_O<215> WL_O<214> WL_O<213> ++ WL_O<212> WL_O<211> WL_O<210> WL_O<209> WL_O<208> VDD VSS / ++ RM_IHPSG13_512x16_c2_1P_DEC04 +XSEL<12> ADDR_N_I<3> ADDR_N_I<2> ADDR_N_I<1> ADDR_N_I<0> CS00<12> ECLK_H<12> ++ ECLK_H<13> ECLK_B<12> ECLK_B<13> WL_O<207> WL_O<206> WL_O<205> WL_O<204> ++ WL_O<203> WL_O<202> WL_O<201> WL_O<200> WL_O<199> WL_O<198> WL_O<197> ++ WL_O<196> WL_O<195> WL_O<194> WL_O<193> WL_O<192> VDD VSS / ++ RM_IHPSG13_512x16_c2_1P_DEC04 +XSEL<11> ADDR_N_I<3> ADDR_N_I<2> ADDR_N_I<1> ADDR_N_I<0> CS00<11> ECLK_H<11> ++ ECLK_H<12> ECLK_B<11> ECLK_B<12> WL_O<191> WL_O<190> WL_O<189> WL_O<188> ++ WL_O<187> WL_O<186> WL_O<185> WL_O<184> WL_O<183> WL_O<182> WL_O<181> ++ WL_O<180> WL_O<179> WL_O<178> WL_O<177> WL_O<176> VDD VSS / ++ RM_IHPSG13_512x16_c2_1P_DEC04 +XSEL<10> ADDR_N_I<3> ADDR_N_I<2> ADDR_N_I<1> ADDR_N_I<0> CS00<10> ECLK_H<10> ++ ECLK_H<11> ECLK_B<10> ECLK_B<11> WL_O<175> WL_O<174> WL_O<173> WL_O<172> ++ WL_O<171> WL_O<170> WL_O<169> WL_O<168> WL_O<167> WL_O<166> WL_O<165> ++ WL_O<164> WL_O<163> WL_O<162> WL_O<161> WL_O<160> VDD VSS / ++ RM_IHPSG13_512x16_c2_1P_DEC04 +XSEL<9> ADDR_N_I<3> ADDR_N_I<2> ADDR_N_I<1> ADDR_N_I<0> CS00<9> ECLK_H<9> ++ ECLK_H<10> ECLK_B<9> ECLK_B<10> WL_O<159> WL_O<158> WL_O<157> WL_O<156> ++ WL_O<155> WL_O<154> WL_O<153> WL_O<152> WL_O<151> WL_O<150> WL_O<149> ++ WL_O<148> WL_O<147> WL_O<146> WL_O<145> WL_O<144> VDD VSS / ++ RM_IHPSG13_512x16_c2_1P_DEC04 +XSEL<8> ADDR_N_I<3> ADDR_N_I<2> ADDR_N_I<1> ADDR_N_I<0> CS00<8> ECLK_H<8> ++ ECLK_H<9> ECLK_B<8> ECLK_B<9> WL_O<143> WL_O<142> WL_O<141> WL_O<140> ++ WL_O<139> WL_O<138> WL_O<137> WL_O<136> WL_O<135> WL_O<134> WL_O<133> ++ WL_O<132> WL_O<131> WL_O<130> WL_O<129> WL_O<128> VDD VSS / ++ RM_IHPSG13_512x16_c2_1P_DEC04 +XSEL<7> ADDR_N_I<3> ADDR_N_I<2> ADDR_N_I<1> ADDR_N_I<0> CS00<7> ECLK_H<7> ++ ECLK_H<8> ECLK_B<7> ECLK_B<8> WL_O<127> WL_O<126> WL_O<125> WL_O<124> ++ WL_O<123> WL_O<122> WL_O<121> WL_O<120> WL_O<119> WL_O<118> WL_O<117> ++ WL_O<116> WL_O<115> WL_O<114> WL_O<113> WL_O<112> VDD VSS / ++ RM_IHPSG13_512x16_c2_1P_DEC04 +XSEL<6> ADDR_N_I<3> ADDR_N_I<2> ADDR_N_I<1> ADDR_N_I<0> CS00<6> ECLK_H<6> ++ ECLK_H<7> ECLK_B<6> ECLK_B<7> WL_O<111> WL_O<110> WL_O<109> WL_O<108> ++ WL_O<107> WL_O<106> WL_O<105> WL_O<104> WL_O<103> WL_O<102> WL_O<101> ++ WL_O<100> WL_O<99> WL_O<98> WL_O<97> WL_O<96> VDD VSS / ++ RM_IHPSG13_512x16_c2_1P_DEC04 +XSEL<5> ADDR_N_I<3> ADDR_N_I<2> ADDR_N_I<1> ADDR_N_I<0> CS00<5> ECLK_H<5> ++ ECLK_H<6> ECLK_B<5> ECLK_B<6> WL_O<95> WL_O<94> WL_O<93> WL_O<92> WL_O<91> ++ WL_O<90> WL_O<89> WL_O<88> WL_O<87> WL_O<86> WL_O<85> WL_O<84> WL_O<83> ++ WL_O<82> WL_O<81> WL_O<80> VDD VSS / RM_IHPSG13_512x16_c2_1P_DEC04 +XSEL<4> ADDR_N_I<3> ADDR_N_I<2> ADDR_N_I<1> ADDR_N_I<0> CS00<4> ECLK_H<4> ++ ECLK_H<5> ECLK_B<4> ECLK_B<5> WL_O<79> WL_O<78> WL_O<77> WL_O<76> WL_O<75> ++ WL_O<74> WL_O<73> WL_O<72> WL_O<71> WL_O<70> WL_O<69> WL_O<68> WL_O<67> ++ WL_O<66> WL_O<65> WL_O<64> VDD VSS / RM_IHPSG13_512x16_c2_1P_DEC04 +XSEL<3> ADDR_N_I<3> ADDR_N_I<2> ADDR_N_I<1> ADDR_N_I<0> CS00<3> ECLK_H<3> ++ ECLK_H<4> ECLK_B<3> ECLK_B<4> WL_O<63> WL_O<62> WL_O<61> WL_O<60> WL_O<59> ++ WL_O<58> WL_O<57> WL_O<56> WL_O<55> WL_O<54> WL_O<53> WL_O<52> WL_O<51> ++ WL_O<50> WL_O<49> WL_O<48> VDD VSS / RM_IHPSG13_512x16_c2_1P_DEC04 +XSEL<2> ADDR_N_I<3> ADDR_N_I<2> ADDR_N_I<1> ADDR_N_I<0> CS00<2> ECLK_H<2> ++ ECLK_H<3> ECLK_B<2> ECLK_B<3> WL_O<47> WL_O<46> WL_O<45> WL_O<44> WL_O<43> ++ WL_O<42> WL_O<41> WL_O<40> WL_O<39> WL_O<38> WL_O<37> WL_O<36> WL_O<35> ++ WL_O<34> WL_O<33> WL_O<32> VDD VSS / RM_IHPSG13_512x16_c2_1P_DEC04 +XSEL<1> ADDR_N_I<3> ADDR_N_I<2> ADDR_N_I<1> ADDR_N_I<0> CS00<1> ECLK_H<1> ++ ECLK_H<2> ECLK_B<1> ECLK_B<2> WL_O<31> WL_O<30> WL_O<29> WL_O<28> WL_O<27> ++ WL_O<26> WL_O<25> WL_O<24> WL_O<23> WL_O<22> WL_O<21> WL_O<20> WL_O<19> ++ WL_O<18> WL_O<17> WL_O<16> VDD VSS / RM_IHPSG13_512x16_c2_1P_DEC04 +XSEL<0> ADDR_N_I<3> ADDR_N_I<2> ADDR_N_I<1> ADDR_N_I<0> CS00<0> ECLK_I ++ ECLK_H<1> ECLK_B<0> ECLK_B<1> WL_O<15> WL_O<14> WL_O<13> WL_O<12> WL_O<11> ++ WL_O<10> WL_O<9> WL_O<8> WL_O<7> WL_O<6> WL_O<5> WL_O<4> WL_O<3> WL_O<2> ++ WL_O<1> WL_O<0> VDD VSS / RM_IHPSG13_512x16_c2_1P_DEC04 +XDEC01<10> ADDR_N_I<9> ADDR_N_I<8> CS_I CS04<1> VDD VSS / ++ RM_IHPSG13_512x16_c2_1P_DEC01 +XDEC01<9> ADDR_N_I<7> ADDR_N_I<6> CS04<1> CS02<5> VDD VSS / ++ RM_IHPSG13_512x16_c2_1P_DEC01 +XDEC01<8> ADDR_N_I<7> ADDR_N_I<6> CS04<0> CS02<1> VDD VSS / ++ RM_IHPSG13_512x16_c2_1P_DEC01 +XDEC01<7> ADDR_N_I<5> ADDR_N_I<4> CS02<7> CS00<29> VDD VSS / ++ RM_IHPSG13_512x16_c2_1P_DEC01 +XDEC01<6> ADDR_N_I<5> ADDR_N_I<4> CS02<6> CS00<25> VDD VSS / ++ RM_IHPSG13_512x16_c2_1P_DEC01 +XDEC01<5> ADDR_N_I<5> ADDR_N_I<4> CS02<5> CS00<21> VDD VSS / ++ RM_IHPSG13_512x16_c2_1P_DEC01 +XDEC01<4> ADDR_N_I<5> ADDR_N_I<4> CS02<4> CS00<17> VDD VSS / ++ RM_IHPSG13_512x16_c2_1P_DEC01 +XDEC01<3> ADDR_N_I<5> ADDR_N_I<4> CS02<3> CS00<13> VDD VSS / ++ RM_IHPSG13_512x16_c2_1P_DEC01 +XDEC01<2> ADDR_N_I<5> ADDR_N_I<4> CS02<2> CS00<9> VDD VSS / ++ RM_IHPSG13_512x16_c2_1P_DEC01 +XDEC01<1> ADDR_N_I<5> ADDR_N_I<4> CS02<1> CS00<5> VDD VSS / ++ RM_IHPSG13_512x16_c2_1P_DEC01 +XDEC01<0> ADDR_N_I<5> ADDR_N_I<4> CS02<0> CS00<1> VDD VSS / ++ RM_IHPSG13_512x16_c2_1P_DEC01 +XDEC10<9> ADDR_N_I<7> ADDR_N_I<6> CS04<1> CS02<6> VDD VSS / ++ RM_IHPSG13_512x16_c2_1P_DEC02 +XDEC10<8> ADDR_N_I<7> ADDR_N_I<6> CS04<0> CS02<2> VDD VSS / ++ RM_IHPSG13_512x16_c2_1P_DEC02 +XDEC10<7> ADDR_N_I<5> ADDR_N_I<4> CS02<7> CS00<30> VDD VSS / ++ RM_IHPSG13_512x16_c2_1P_DEC02 +XDEC10<6> ADDR_N_I<5> ADDR_N_I<4> CS02<6> CS00<26> VDD VSS / ++ RM_IHPSG13_512x16_c2_1P_DEC02 +XDEC10<5> ADDR_N_I<5> ADDR_N_I<4> CS02<5> CS00<22> VDD VSS / ++ RM_IHPSG13_512x16_c2_1P_DEC02 +XDEC10<4> ADDR_N_I<5> ADDR_N_I<4> CS02<4> CS00<18> VDD VSS / ++ RM_IHPSG13_512x16_c2_1P_DEC02 +XDEC10<3> ADDR_N_I<5> ADDR_N_I<4> CS02<3> CS00<14> VDD VSS / ++ RM_IHPSG13_512x16_c2_1P_DEC02 +XDEC10<2> ADDR_N_I<5> ADDR_N_I<4> CS02<2> CS00<10> VDD VSS / ++ RM_IHPSG13_512x16_c2_1P_DEC02 +XDEC10<1> ADDR_N_I<5> ADDR_N_I<4> CS02<1> CS00<6> VDD VSS / ++ RM_IHPSG13_512x16_c2_1P_DEC02 +XDEC10<0> ADDR_N_I<5> ADDR_N_I<4> CS02<0> CS00<2> VDD VSS / ++ RM_IHPSG13_512x16_c2_1P_DEC02 +XI0 ADDR_N_I<9> VDD VSS / RSC_IHPSG13_TIEL +.ENDS +.SUBCKT RM_IHPSG13_512x16_c2_1P_ROWREG9 ACLK_N_I ADDR_I<8> ADDR_I<7> ADDR_I<6> ADDR_I<5> ++ ADDR_I<4> ADDR_I<3> ADDR_I<2> ADDR_I<1> ADDR_I<0> ADDR_N_O<8> ADDR_N_O<7> ++ ADDR_N_O<6> ADDR_N_O<5> ADDR_N_O<4> ADDR_N_O<3> ADDR_N_O<2> ADDR_N_O<1> ++ ADDR_N_O<0> BIST_ADDR_I<8> BIST_ADDR_I<7> BIST_ADDR_I<6> BIST_ADDR_I<5> ++ BIST_ADDR_I<4> BIST_ADDR_I<3> BIST_ADDR_I<2> BIST_ADDR_I<1> BIST_ADDR_I<0> ++ BIST_EN_I VDD VSS +XINV<8> q_int<8> qn_int<8> VDD VSS / RSC_IHPSG13_CINVX2 +XINV<7> q_int<7> qn_int<7> VDD VSS / RSC_IHPSG13_CINVX2 +XINV<6> q_int<6> qn_int<6> VDD VSS / RSC_IHPSG13_CINVX2 +XINV<5> q_int<5> qn_int<5> VDD VSS / RSC_IHPSG13_CINVX2 +XINV<4> q_int<4> qn_int<4> VDD VSS / RSC_IHPSG13_CINVX2 +XINV<3> q_int<3> qn_int<3> VDD VSS / RSC_IHPSG13_CINVX2 +XINV<2> q_int<2> qn_int<2> VDD VSS / RSC_IHPSG13_CINVX2 +XINV<1> q_int<1> qn_int<1> VDD VSS / RSC_IHPSG13_CINVX2 +XINV<0> q_int<0> qn_int<0> VDD VSS / RSC_IHPSG13_CINVX2 +XDRV<8> qn_int<8> ADDR_N_O<8> VDD VSS / RSC_IHPSG13_CINVX8 +XDRV<7> qn_int<7> ADDR_N_O<7> VDD VSS / RSC_IHPSG13_CINVX8 +XDRV<6> qn_int<6> ADDR_N_O<6> VDD VSS / RSC_IHPSG13_CINVX8 +XDRV<5> qn_int<5> ADDR_N_O<5> VDD VSS / RSC_IHPSG13_CINVX8 +XDRV<4> qn_int<4> ADDR_N_O<4> VDD VSS / RSC_IHPSG13_CINVX8 +XDRV<3> qn_int<3> ADDR_N_O<3> VDD VSS / RSC_IHPSG13_CINVX8 +XDRV<2> qn_int<2> ADDR_N_O<2> VDD VSS / RSC_IHPSG13_CINVX8 +XDRV<1> qn_int<1> ADDR_N_O<1> VDD VSS / RSC_IHPSG13_CINVX8 +XDRV<0> qn_int<0> ADDR_N_O<0> VDD VSS / RSC_IHPSG13_CINVX8 +XDFF<8> BIST_EN_I BIST_ADDR_I<8> ACLK_N_I ADDR_I<8> q_int<8> net04<0> VDD ++ VSS / RSC_IHPSG13_DFNQMX2IX1 +XDFF<7> BIST_EN_I BIST_ADDR_I<7> ACLK_N_I ADDR_I<7> q_int<7> net04<1> VDD ++ VSS / RSC_IHPSG13_DFNQMX2IX1 +XDFF<6> BIST_EN_I BIST_ADDR_I<6> ACLK_N_I ADDR_I<6> q_int<6> net04<2> VDD ++ VSS / RSC_IHPSG13_DFNQMX2IX1 +XDFF<5> BIST_EN_I BIST_ADDR_I<5> ACLK_N_I ADDR_I<5> q_int<5> net04<3> VDD ++ VSS / RSC_IHPSG13_DFNQMX2IX1 +XDFF<4> BIST_EN_I BIST_ADDR_I<4> ACLK_N_I ADDR_I<4> q_int<4> net04<4> VDD ++ VSS / RSC_IHPSG13_DFNQMX2IX1 +XDFF<3> BIST_EN_I BIST_ADDR_I<3> ACLK_N_I ADDR_I<3> q_int<3> net04<5> VDD ++ VSS / RSC_IHPSG13_DFNQMX2IX1 +XDFF<2> BIST_EN_I BIST_ADDR_I<2> ACLK_N_I ADDR_I<2> q_int<2> net04<6> VDD ++ VSS / RSC_IHPSG13_DFNQMX2IX1 +XDFF<1> BIST_EN_I BIST_ADDR_I<1> ACLK_N_I ADDR_I<1> q_int<1> net04<7> VDD ++ VSS / RSC_IHPSG13_DFNQMX2IX1 +XDFF<0> BIST_EN_I BIST_ADDR_I<0> ACLK_N_I ADDR_I<0> q_int<0> net04<8> VDD ++ VSS / RSC_IHPSG13_DFNQMX2IX1 +.ENDS + +.SUBCKT RM_IHPSG13_512x16_c2_1P_ROWDEC7 ADDR_N_I<6> ADDR_N_I<5> ADDR_N_I<4> ADDR_N_I<3> ++ ADDR_N_I<2> ADDR_N_I<1> ADDR_N_I<0> CS_I ECLK_I WL_O<127> WL_O<126> ++ WL_O<125> WL_O<124> WL_O<123> WL_O<122> WL_O<121> WL_O<120> WL_O<119> ++ WL_O<118> WL_O<117> WL_O<116> WL_O<115> WL_O<114> WL_O<113> WL_O<112> ++ WL_O<111> WL_O<110> WL_O<109> WL_O<108> WL_O<107> WL_O<106> WL_O<105> ++ WL_O<104> WL_O<103> WL_O<102> WL_O<101> WL_O<100> WL_O<99> WL_O<98> WL_O<97> ++ WL_O<96> WL_O<95> WL_O<94> WL_O<93> WL_O<92> WL_O<91> WL_O<90> WL_O<89> ++ WL_O<88> WL_O<87> WL_O<86> WL_O<85> WL_O<84> WL_O<83> WL_O<82> WL_O<81> ++ WL_O<80> WL_O<79> WL_O<78> WL_O<77> WL_O<76> WL_O<75> WL_O<74> WL_O<73> ++ WL_O<72> WL_O<71> WL_O<70> WL_O<69> WL_O<68> WL_O<67> WL_O<66> WL_O<65> ++ WL_O<64> WL_O<63> WL_O<62> WL_O<61> WL_O<60> WL_O<59> WL_O<58> WL_O<57> ++ WL_O<56> WL_O<55> WL_O<54> WL_O<53> WL_O<52> WL_O<51> WL_O<50> WL_O<49> ++ WL_O<48> WL_O<47> WL_O<46> WL_O<45> WL_O<44> WL_O<43> WL_O<42> WL_O<41> ++ WL_O<40> WL_O<39> WL_O<38> WL_O<37> WL_O<36> WL_O<35> WL_O<34> WL_O<33> ++ WL_O<32> WL_O<31> WL_O<30> WL_O<29> WL_O<28> WL_O<27> WL_O<26> WL_O<25> ++ WL_O<24> WL_O<23> WL_O<22> WL_O<21> WL_O<20> WL_O<19> WL_O<18> WL_O<17> ++ WL_O<16> WL_O<15> WL_O<14> WL_O<13> WL_O<12> WL_O<11> WL_O<10> WL_O<9> ++ WL_O<8> WL_O<7> WL_O<6> WL_O<5> WL_O<4> WL_O<3> WL_O<2> WL_O<1> WL_O<0> ++ VDD VSS +XDEC11<1> ADDR_N_I<5> ADDR_N_I<4> CS04<1> CS00<7> VDD VSS / ++ RM_IHPSG13_512x16_c2_1P_DEC03 +XDEC11<0> ADDR_N_I<5> ADDR_N_I<4> CS04<0> CS00<3> VDD VSS / ++ RM_IHPSG13_512x16_c2_1P_DEC03 +XDEC10<1> ADDR_N_I<5> ADDR_N_I<4> CS04<1> CS00<6> VDD VSS / ++ RM_IHPSG13_512x16_c2_1P_DEC02 +XDEC10<0> ADDR_N_I<5> ADDR_N_I<4> CS04<0> CS00<2> VDD VSS / ++ RM_IHPSG13_512x16_c2_1P_DEC02 +XSEL<7> ADDR_N_I<3> ADDR_N_I<2> ADDR_N_I<1> ADDR_N_I<0> CS00<7> ECLK_H<7> ++ ECLK_H<8> ECLK_B<7> ECLK_B<8> WL_O<127> WL_O<126> WL_O<125> WL_O<124> ++ WL_O<123> WL_O<122> WL_O<121> WL_O<120> WL_O<119> WL_O<118> WL_O<117> ++ WL_O<116> WL_O<115> WL_O<114> WL_O<113> WL_O<112> VDD VSS / ++ RM_IHPSG13_512x16_c2_1P_DEC04 +XSEL<6> ADDR_N_I<3> ADDR_N_I<2> ADDR_N_I<1> ADDR_N_I<0> CS00<6> ECLK_H<6> ++ ECLK_H<7> ECLK_B<6> ECLK_B<7> WL_O<111> WL_O<110> WL_O<109> WL_O<108> ++ WL_O<107> WL_O<106> WL_O<105> WL_O<104> WL_O<103> WL_O<102> WL_O<101> ++ WL_O<100> WL_O<99> WL_O<98> WL_O<97> WL_O<96> VDD VSS / ++ RM_IHPSG13_512x16_c2_1P_DEC04 +XSEL<5> ADDR_N_I<3> ADDR_N_I<2> ADDR_N_I<1> ADDR_N_I<0> CS00<5> ECLK_H<5> ++ ECLK_H<6> ECLK_B<5> ECLK_B<6> WL_O<95> WL_O<94> WL_O<93> WL_O<92> WL_O<91> ++ WL_O<90> WL_O<89> WL_O<88> WL_O<87> WL_O<86> WL_O<85> WL_O<84> WL_O<83> ++ WL_O<82> WL_O<81> WL_O<80> VDD VSS / RM_IHPSG13_512x16_c2_1P_DEC04 +XSEL<4> ADDR_N_I<3> ADDR_N_I<2> ADDR_N_I<1> ADDR_N_I<0> CS00<4> ECLK_H<4> ++ ECLK_H<5> ECLK_B<4> ECLK_B<5> WL_O<79> WL_O<78> WL_O<77> WL_O<76> WL_O<75> ++ WL_O<74> WL_O<73> WL_O<72> WL_O<71> WL_O<70> WL_O<69> WL_O<68> WL_O<67> ++ WL_O<66> WL_O<65> WL_O<64> VDD VSS / RM_IHPSG13_512x16_c2_1P_DEC04 +XSEL<3> ADDR_N_I<3> ADDR_N_I<2> ADDR_N_I<1> ADDR_N_I<0> CS00<3> ECLK_H<3> ++ ECLK_H<4> ECLK_B<3> ECLK_B<4> WL_O<63> WL_O<62> WL_O<61> WL_O<60> WL_O<59> ++ WL_O<58> WL_O<57> WL_O<56> WL_O<55> WL_O<54> WL_O<53> WL_O<52> WL_O<51> ++ WL_O<50> WL_O<49> WL_O<48> VDD VSS / RM_IHPSG13_512x16_c2_1P_DEC04 +XSEL<2> ADDR_N_I<3> ADDR_N_I<2> ADDR_N_I<1> ADDR_N_I<0> CS00<2> ECLK_H<2> ++ ECLK_H<3> ECLK_B<2> ECLK_B<3> WL_O<47> WL_O<46> WL_O<45> WL_O<44> WL_O<43> ++ WL_O<42> WL_O<41> WL_O<40> WL_O<39> WL_O<38> WL_O<37> WL_O<36> WL_O<35> ++ WL_O<34> WL_O<33> WL_O<32> VDD VSS / RM_IHPSG13_512x16_c2_1P_DEC04 +XSEL<1> ADDR_N_I<3> ADDR_N_I<2> ADDR_N_I<1> ADDR_N_I<0> CS00<1> ECLK_H<1> ++ ECLK_H<2> ECLK_B<1> ECLK_B<2> WL_O<31> WL_O<30> WL_O<29> WL_O<28> WL_O<27> ++ WL_O<26> WL_O<25> WL_O<24> WL_O<23> WL_O<22> WL_O<21> WL_O<20> WL_O<19> ++ WL_O<18> WL_O<17> WL_O<16> VDD VSS / RM_IHPSG13_512x16_c2_1P_DEC04 +XSEL<0> ADDR_N_I<3> ADDR_N_I<2> ADDR_N_I<1> ADDR_N_I<0> CS00<0> ECLK_I ++ ECLK_H<1> ECLK_B<0> ECLK_B<1> WL_O<15> WL_O<14> WL_O<13> WL_O<12> WL_O<11> ++ WL_O<10> WL_O<9> WL_O<8> WL_O<7> WL_O<6> WL_O<5> WL_O<4> WL_O<3> WL_O<2> ++ WL_O<1> WL_O<0> VDD VSS / RM_IHPSG13_512x16_c2_1P_DEC04 +XDEC00<2> ADDR_N_I<7> ADDR_N_I<6> CS_I CS04<0> VDD VSS / ++ RM_IHPSG13_512x16_c2_1P_DEC00 +XDEC00<1> ADDR_N_I<5> ADDR_N_I<4> CS04<1> CS00<4> VDD VSS / ++ RM_IHPSG13_512x16_c2_1P_DEC00 +XDEC00<0> ADDR_N_I<5> ADDR_N_I<4> CS04<0> CS00<0> VDD VSS / ++ RM_IHPSG13_512x16_c2_1P_DEC00 +XDEC01<2> ADDR_N_I<7> ADDR_N_I<6> CS_I CS04<1> VDD VSS / ++ RM_IHPSG13_512x16_c2_1P_DEC01 +XDEC01<1> ADDR_N_I<5> ADDR_N_I<4> CS04<1> CS00<5> VDD VSS / ++ RM_IHPSG13_512x16_c2_1P_DEC01 +XDEC01<0> ADDR_N_I<5> ADDR_N_I<4> CS04<0> CS00<1> VDD VSS / ++ RM_IHPSG13_512x16_c2_1P_DEC01 +XL2<44> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<43> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<42> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<41> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<40> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<39> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<38> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<37> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<36> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<35> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<34> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<33> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<32> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<31> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<30> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<29> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<28> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<27> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<26> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<25> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<24> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<23> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<22> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<21> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<20> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<19> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<18> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<17> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<16> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<15> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<14> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<13> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<12> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<11> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<10> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<9> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<8> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<7> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<6> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<5> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<4> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<3> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<2> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<1> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI0 ADDR_N_I<7> VDD VSS / RSC_IHPSG13_TIEL +.ENDS +.SUBCKT RM_IHPSG13_512x16_c2_1P_ROWREG7 ACLK_N_I ADDR_I<6> ADDR_I<5> ADDR_I<4> ADDR_I<3> ++ ADDR_I<2> ADDR_I<1> ADDR_I<0> ADDR_N_O<6> ADDR_N_O<5> ADDR_N_O<4> ++ ADDR_N_O<3> ADDR_N_O<2> ADDR_N_O<1> ADDR_N_O<0> BIST_ADDR_I<6> ++ BIST_ADDR_I<5> BIST_ADDR_I<4> BIST_ADDR_I<3> BIST_ADDR_I<2> BIST_ADDR_I<1> ++ BIST_ADDR_I<0> BIST_EN_I VDD VSS +XINV<6> q_int<6> qn_int<6> VDD VSS / RSC_IHPSG13_CINVX2 +XINV<5> q_int<5> qn_int<5> VDD VSS / RSC_IHPSG13_CINVX2 +XINV<4> q_int<4> qn_int<4> VDD VSS / RSC_IHPSG13_CINVX2 +XINV<3> q_int<3> qn_int<3> VDD VSS / RSC_IHPSG13_CINVX2 +XINV<2> q_int<2> qn_int<2> VDD VSS / RSC_IHPSG13_CINVX2 +XINV<1> q_int<1> qn_int<1> VDD VSS / RSC_IHPSG13_CINVX2 +XINV<0> q_int<0> qn_int<0> VDD VSS / RSC_IHPSG13_CINVX2 +XDRV<6> qn_int<6> ADDR_N_O<6> VDD VSS / RSC_IHPSG13_CINVX8 +XDRV<5> qn_int<5> ADDR_N_O<5> VDD VSS / RSC_IHPSG13_CINVX8 +XDRV<4> qn_int<4> ADDR_N_O<4> VDD VSS / RSC_IHPSG13_CINVX8 +XDRV<3> qn_int<3> ADDR_N_O<3> VDD VSS / RSC_IHPSG13_CINVX8 +XDRV<2> qn_int<2> ADDR_N_O<2> VDD VSS / RSC_IHPSG13_CINVX8 +XDRV<1> qn_int<1> ADDR_N_O<1> VDD VSS / RSC_IHPSG13_CINVX8 +XDRV<0> qn_int<0> ADDR_N_O<0> VDD VSS / RSC_IHPSG13_CINVX8 +XDFF<6> BIST_EN_I BIST_ADDR_I<6> ACLK_N_I ADDR_I<6> q_int<6> net2<0> VDD ++ VSS / RSC_IHPSG13_DFNQMX2IX1 +XDFF<5> BIST_EN_I BIST_ADDR_I<5> ACLK_N_I ADDR_I<5> q_int<5> net2<1> VDD ++ VSS / RSC_IHPSG13_DFNQMX2IX1 +XDFF<4> BIST_EN_I BIST_ADDR_I<4> ACLK_N_I ADDR_I<4> q_int<4> net2<2> VDD ++ VSS / RSC_IHPSG13_DFNQMX2IX1 +XDFF<3> BIST_EN_I BIST_ADDR_I<3> ACLK_N_I ADDR_I<3> q_int<3> net2<3> VDD ++ VSS / RSC_IHPSG13_DFNQMX2IX1 +XDFF<2> BIST_EN_I BIST_ADDR_I<2> ACLK_N_I ADDR_I<2> q_int<2> net2<4> VDD ++ VSS / RSC_IHPSG13_DFNQMX2IX1 +XDFF<1> BIST_EN_I BIST_ADDR_I<1> ACLK_N_I ADDR_I<1> q_int<1> net2<5> VDD ++ VSS / RSC_IHPSG13_DFNQMX2IX1 +XDFF<0> BIST_EN_I BIST_ADDR_I<0> ACLK_N_I ADDR_I<0> q_int<0> net2<6> VDD ++ VSS / RSC_IHPSG13_DFNQMX2IX1 +XI11<8> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI11<7> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI11<6> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI11<5> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI11<4> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI11<3> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI11<2> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI11<1> VDD VSS / RSC_IHPSG13_FILLCAP8 +.ENDS + +.SUBCKT RM_IHPSG13_512x16_c2_1P_COLDRV13X8 ADDR_COL_I<1> ADDR_COL_I<0> ADDR_COL_O<1> ++ ADDR_COL_O<0> ADDR_DEC_I<7> ADDR_DEC_I<6> ADDR_DEC_I<5> ADDR_DEC_I<4> ++ ADDR_DEC_I<3> ADDR_DEC_I<2> ADDR_DEC_I<1> ADDR_DEC_I<0> ADDR_DEC_O<7> ++ ADDR_DEC_O<6> ADDR_DEC_O<5> ADDR_DEC_O<4> ADDR_DEC_O<3> ADDR_DEC_O<2> ++ ADDR_DEC_O<1> ADDR_DEC_O<0> DCLK_I DCLK_O RCLK_I RCLK_O WCLK_I WCLK_O ++ VDD VSS +XI0<1> VDD VSS / RSC_IHPSG13_FILLCAP4 +XI0<0> VDD VSS / RSC_IHPSG13_FILLCAP4 +XADDR_COL_DRV<1> ADDR_COL_I<1> ADDR_COL_O<1> VDD VSS / ++ RSC_IHPSG13_CBUFX8 +XADDR_COL_DRV<0> ADDR_COL_I<0> ADDR_COL_O<0> VDD VSS / ++ RSC_IHPSG13_CBUFX8 +XADDR_DEC_DRV<7> ADDR_DEC_I<7> ADDR_DEC_O<7> VDD VSS / ++ RSC_IHPSG13_CBUFX8 +XADDR_DEC_DRV<6> ADDR_DEC_I<6> ADDR_DEC_O<6> VDD VSS / ++ RSC_IHPSG13_CBUFX8 +XADDR_DEC_DRV<5> ADDR_DEC_I<5> ADDR_DEC_O<5> VDD VSS / ++ RSC_IHPSG13_CBUFX8 +XADDR_DEC_DRV<4> ADDR_DEC_I<4> ADDR_DEC_O<4> VDD VSS / ++ RSC_IHPSG13_CBUFX8 +XADDR_DEC_DRV<3> ADDR_DEC_I<3> ADDR_DEC_O<3> VDD VSS / ++ RSC_IHPSG13_CBUFX8 +XADDR_DEC_DRV<2> ADDR_DEC_I<2> ADDR_DEC_O<2> VDD VSS / ++ RSC_IHPSG13_CBUFX8 +XADDR_DEC_DRV<1> ADDR_DEC_I<1> ADDR_DEC_O<1> VDD VSS / ++ RSC_IHPSG13_CBUFX8 +XADDR_DEC_DRV<0> ADDR_DEC_I<0> ADDR_DEC_O<0> VDD VSS / ++ RSC_IHPSG13_CBUFX8 +XDCLK_DRV DCLK_I DCLK_O VDD VSS / RSC_IHPSG13_CBUFX8 +XRCLK_DRV RCLK_I RCLK_O VDD VSS / RSC_IHPSG13_CBUFX8 +XWCLK_DRV WCLK_I WCLK_O VDD VSS / RSC_IHPSG13_CBUFX8 +.ENDS +.SUBCKT RM_IHPSG13_512x16_c2_1P_WLDRV16X8 A<15> A<14> A<13> A<12> A<11> A<10> A<9> A<8> ++ A<7> A<6> A<5> A<4> A<3> A<2> A<1> A<0> Z<15> Z<14> Z<13> Z<12> Z<11> Z<10> ++ Z<9> Z<8> Z<7> Z<6> Z<5> Z<4> Z<3> Z<2> Z<1> Z<0> VDD VSS +XBUF<15> A<15> Z<15> VDD VSS / RSC_IHPSG13_WLDRVX8 +XBUF<14> A<14> Z<14> VDD VSS / RSC_IHPSG13_WLDRVX8 +XBUF<13> A<13> Z<13> VDD VSS / RSC_IHPSG13_WLDRVX8 +XBUF<12> A<12> Z<12> VDD VSS / RSC_IHPSG13_WLDRVX8 +XBUF<11> A<11> Z<11> VDD VSS / RSC_IHPSG13_WLDRVX8 +XBUF<10> A<10> Z<10> VDD VSS / RSC_IHPSG13_WLDRVX8 +XBUF<9> A<9> Z<9> VDD VSS / RSC_IHPSG13_WLDRVX8 +XBUF<8> A<8> Z<8> VDD VSS / RSC_IHPSG13_WLDRVX8 +XBUF<7> A<7> Z<7> VDD VSS / RSC_IHPSG13_WLDRVX8 +XBUF<6> A<6> Z<6> VDD VSS / RSC_IHPSG13_WLDRVX8 +XBUF<5> A<5> Z<5> VDD VSS / RSC_IHPSG13_WLDRVX8 +XBUF<4> A<4> Z<4> VDD VSS / RSC_IHPSG13_WLDRVX8 +XBUF<3> A<3> Z<3> VDD VSS / RSC_IHPSG13_WLDRVX8 +XBUF<2> A<2> Z<2> VDD VSS / RSC_IHPSG13_WLDRVX8 +XBUF<1> A<1> Z<1> VDD VSS / RSC_IHPSG13_WLDRVX8 +XBUF<0> A<0> Z<0> VDD VSS / RSC_IHPSG13_WLDRVX8 +.ENDS + + + +.SUBCKT RM_IHPSG13_512x16_c2_1P_ROWDEC6 ADDR_N_I<5> ADDR_N_I<4> ADDR_N_I<3> ADDR_N_I<2> ++ ADDR_N_I<1> ADDR_N_I<0> CS_I ECLK_I WL_O<63> WL_O<62> WL_O<61> WL_O<60> ++ WL_O<59> WL_O<58> WL_O<57> WL_O<56> WL_O<55> WL_O<54> WL_O<53> WL_O<52> ++ WL_O<51> WL_O<50> WL_O<49> WL_O<48> WL_O<47> WL_O<46> WL_O<45> WL_O<44> ++ WL_O<43> WL_O<42> WL_O<41> WL_O<40> WL_O<39> WL_O<38> WL_O<37> WL_O<36> ++ WL_O<35> WL_O<34> WL_O<33> WL_O<32> WL_O<31> WL_O<30> WL_O<29> WL_O<28> ++ WL_O<27> WL_O<26> WL_O<25> WL_O<24> WL_O<23> WL_O<22> WL_O<21> WL_O<20> ++ WL_O<19> WL_O<18> WL_O<17> WL_O<16> WL_O<15> WL_O<14> WL_O<13> WL_O<12> ++ WL_O<11> WL_O<10> WL_O<9> WL_O<8> WL_O<7> WL_O<6> WL_O<5> WL_O<4> WL_O<3> ++ WL_O<2> WL_O<1> WL_O<0> VDD VSS +XDEC11 ADDR_N_I<5> ADDR_N_I<4> CS_I CS00<3> VDD VSS / ++ RM_IHPSG13_512x16_c2_1P_DEC03 +XDEC00 ADDR_N_I<5> ADDR_N_I<4> CS_I CS00<0> VDD VSS / ++ RM_IHPSG13_512x16_c2_1P_DEC00 +XDEC01 ADDR_N_I<5> ADDR_N_I<4> CS_I CS00<1> VDD VSS / ++ RM_IHPSG13_512x16_c2_1P_DEC01 +XDEC10 ADDR_N_I<5> ADDR_N_I<4> CS_I CS00<2> VDD VSS / ++ RM_IHPSG13_512x16_c2_1P_DEC02 +XSEL<3> ADDR_N_I<3> ADDR_N_I<2> ADDR_N_I<1> ADDR_N_I<0> CS00<3> ECLK_H<3> ++ ECLK_H<4> ECLK_B<3> ECLK_B<4> WL_O<63> WL_O<62> WL_O<61> WL_O<60> WL_O<59> ++ WL_O<58> WL_O<57> WL_O<56> WL_O<55> WL_O<54> WL_O<53> WL_O<52> WL_O<51> ++ WL_O<50> WL_O<49> WL_O<48> VDD VSS / RM_IHPSG13_512x16_c2_1P_DEC04 +XSEL<2> ADDR_N_I<3> ADDR_N_I<2> ADDR_N_I<1> ADDR_N_I<0> CS00<2> ECLK_H<2> ++ ECLK_H<3> ECLK_B<2> ECLK_B<3> WL_O<47> WL_O<46> WL_O<45> WL_O<44> WL_O<43> ++ WL_O<42> WL_O<41> WL_O<40> WL_O<39> WL_O<38> WL_O<37> WL_O<36> WL_O<35> ++ WL_O<34> WL_O<33> WL_O<32> VDD VSS / RM_IHPSG13_512x16_c2_1P_DEC04 +XSEL<1> ADDR_N_I<3> ADDR_N_I<2> ADDR_N_I<1> ADDR_N_I<0> CS00<1> ECLK_H<1> ++ ECLK_H<2> ECLK_B<1> ECLK_B<2> WL_O<31> WL_O<30> WL_O<29> WL_O<28> WL_O<27> ++ WL_O<26> WL_O<25> WL_O<24> WL_O<23> WL_O<22> WL_O<21> WL_O<20> WL_O<19> ++ WL_O<18> WL_O<17> WL_O<16> VDD VSS / RM_IHPSG13_512x16_c2_1P_DEC04 +XSEL<0> ADDR_N_I<3> ADDR_N_I<2> ADDR_N_I<1> ADDR_N_I<0> CS00<0> ECLK_I ++ ECLK_H<1> ECLK_B<0> ECLK_B<1> WL_O<15> WL_O<14> WL_O<13> WL_O<12> WL_O<11> ++ WL_O<10> WL_O<9> WL_O<8> WL_O<7> WL_O<6> WL_O<5> WL_O<4> WL_O<3> WL_O<2> ++ WL_O<1> WL_O<0> VDD VSS / RM_IHPSG13_512x16_c2_1P_DEC04 +XL2<24> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<23> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<22> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<21> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<20> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<19> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<18> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<17> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<16> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<15> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<14> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<13> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<12> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<11> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<10> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<9> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<8> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<7> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<6> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<5> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<4> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<3> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<2> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<1> VDD VSS / RSC_IHPSG13_FILLCAP8 +.ENDS +.SUBCKT RM_IHPSG13_512x16_c2_1P_ROWREG6 ACLK_N_I ADDR_I<5> ADDR_I<4> ADDR_I<3> ADDR_I<2> ++ ADDR_I<1> ADDR_I<0> ADDR_N_O<5> ADDR_N_O<4> ADDR_N_O<3> ADDR_N_O<2> ++ ADDR_N_O<1> ADDR_N_O<0> BIST_ADDR_I<5> BIST_ADDR_I<4> BIST_ADDR_I<3> ++ BIST_ADDR_I<2> BIST_ADDR_I<1> BIST_ADDR_I<0> BIST_EN_I VDD VSS +XINV<5> q_int<5> qn_int<5> VDD VSS / RSC_IHPSG13_CINVX2 +XINV<4> q_int<4> qn_int<4> VDD VSS / RSC_IHPSG13_CINVX2 +XINV<3> q_int<3> qn_int<3> VDD VSS / RSC_IHPSG13_CINVX2 +XINV<2> q_int<2> qn_int<2> VDD VSS / RSC_IHPSG13_CINVX2 +XINV<1> q_int<1> qn_int<1> VDD VSS / RSC_IHPSG13_CINVX2 +XINV<0> q_int<0> qn_int<0> VDD VSS / RSC_IHPSG13_CINVX2 +XDRV<5> qn_int<5> ADDR_N_O<5> VDD VSS / RSC_IHPSG13_CINVX8 +XDRV<4> qn_int<4> ADDR_N_O<4> VDD VSS / RSC_IHPSG13_CINVX8 +XDRV<3> qn_int<3> ADDR_N_O<3> VDD VSS / RSC_IHPSG13_CINVX8 +XDRV<2> qn_int<2> ADDR_N_O<2> VDD VSS / RSC_IHPSG13_CINVX8 +XDRV<1> qn_int<1> ADDR_N_O<1> VDD VSS / RSC_IHPSG13_CINVX8 +XDRV<0> qn_int<0> ADDR_N_O<0> VDD VSS / RSC_IHPSG13_CINVX8 +XDFF<5> BIST_EN_I BIST_ADDR_I<5> ACLK_N_I ADDR_I<5> q_int<5> net2<0> VDD ++ VSS / RSC_IHPSG13_DFNQMX2IX1 +XDFF<4> BIST_EN_I BIST_ADDR_I<4> ACLK_N_I ADDR_I<4> q_int<4> net2<1> VDD ++ VSS / RSC_IHPSG13_DFNQMX2IX1 +XDFF<3> BIST_EN_I BIST_ADDR_I<3> ACLK_N_I ADDR_I<3> q_int<3> net2<2> VDD ++ VSS / RSC_IHPSG13_DFNQMX2IX1 +XDFF<2> BIST_EN_I BIST_ADDR_I<2> ACLK_N_I ADDR_I<2> q_int<2> net2<3> VDD ++ VSS / RSC_IHPSG13_DFNQMX2IX1 +XDFF<1> BIST_EN_I BIST_ADDR_I<1> ACLK_N_I ADDR_I<1> q_int<1> net2<4> VDD ++ VSS / RSC_IHPSG13_DFNQMX2IX1 +XDFF<0> BIST_EN_I BIST_ADDR_I<0> ACLK_N_I ADDR_I<0> q_int<0> net2<5> VDD ++ VSS / RSC_IHPSG13_DFNQMX2IX1 +XI11<12> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI11<11> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI11<10> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI11<9> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI11<8> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI11<7> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI11<6> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI11<5> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI11<4> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI11<3> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI11<2> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI11<1> VDD VSS / RSC_IHPSG13_FILLCAP8 +.ENDS + + +.SUBCKT RM_IHPSG13_512x16_c2_1P_COLUMN_pcell_0 A_BLC_BOT<1> A_BLC_BOT<0> A_BLC_TOP<1> A_BLC_TOP<0> A_BLT_BOT<1> A_BLT_BOT<0> A_BLT_TOP<1> A_BLT_TOP<0> A_LWL<127> A_LWL<126> A_LWL<125> A_LWL<124> A_LWL<123> A_LWL<122> A_LWL<121> A_LWL<120> A_LWL<119> A_LWL<118> A_LWL<117> A_LWL<116> A_LWL<115> A_LWL<114> A_LWL<113> A_LWL<112> A_LWL<111> A_LWL<110> A_LWL<109> A_LWL<108> A_LWL<107> A_LWL<106> A_LWL<105> A_LWL<104> A_LWL<103> A_LWL<102> A_LWL<101> A_LWL<100> A_LWL<99> A_LWL<98> A_LWL<97> A_LWL<96> A_LWL<95> A_LWL<94> A_LWL<93> A_LWL<92> A_LWL<91> A_LWL<90> A_LWL<89> A_LWL<88> A_LWL<87> A_LWL<86> A_LWL<85> A_LWL<84> A_LWL<83> A_LWL<82> A_LWL<81> A_LWL<80> A_LWL<79> A_LWL<78> A_LWL<77> A_LWL<76> A_LWL<75> A_LWL<74> A_LWL<73> A_LWL<72> A_LWL<71> A_LWL<70> A_LWL<69> A_LWL<68> A_LWL<67> A_LWL<66> A_LWL<65> A_LWL<64> A_LWL<63> A_LWL<62> A_LWL<61> A_LWL<60> A_LWL<59> A_LWL<58> A_LWL<57> A_LWL<56> A_LWL<55> A_LWL<54> A_LWL<53> A_LWL<52> A_LWL<51> A_LWL<50> A_LWL<49> A_LWL<48> A_LWL<47> A_LWL<46> A_LWL<45> A_LWL<44> A_LWL<43> A_LWL<42> A_LWL<41> A_LWL<40> A_LWL<39> A_LWL<38> A_LWL<37> A_LWL<36> A_LWL<35> A_LWL<34> A_LWL<33> A_LWL<32> A_LWL<31> A_LWL<30> A_LWL<29> A_LWL<28> A_LWL<27> A_LWL<26> A_LWL<25> A_LWL<24> A_LWL<23> A_LWL<22> A_LWL<21> A_LWL<20> A_LWL<19> A_LWL<18> A_LWL<17> A_LWL<16> A_LWL<15> A_LWL<14> A_LWL<13> A_LWL<12> A_LWL<11> A_LWL<10> A_LWL<9> A_LWL<8> A_LWL<7> A_LWL<6> A_LWL<5> A_LWL<4> A_LWL<3> A_LWL<2> A_LWL<1> A_LWL<0> A_RWL<127> A_RWL<126> A_RWL<125> A_RWL<124> A_RWL<123> A_RWL<122> A_RWL<121> A_RWL<120> A_RWL<119> A_RWL<118> A_RWL<117> A_RWL<116> A_RWL<115> A_RWL<114> A_RWL<113> A_RWL<112> A_RWL<111> A_RWL<110> A_RWL<109> A_RWL<108> A_RWL<107> A_RWL<106> A_RWL<105> A_RWL<104> A_RWL<103> A_RWL<102> A_RWL<101> A_RWL<100> A_RWL<99> A_RWL<98> A_RWL<97> A_RWL<96> A_RWL<95> A_RWL<94> A_RWL<93> A_RWL<92> A_RWL<91> A_RWL<90> A_RWL<89> A_RWL<88> A_RWL<87> A_RWL<86> A_RWL<85> A_RWL<84> A_RWL<83> A_RWL<82> A_RWL<81> A_RWL<80> A_RWL<79> A_RWL<78> A_RWL<77> A_RWL<76> A_RWL<75> A_RWL<74> A_RWL<73> A_RWL<72> A_RWL<71> A_RWL<70> A_RWL<69> A_RWL<68> A_RWL<67> A_RWL<66> A_RWL<65> A_RWL<64> A_RWL<63> A_RWL<62> A_RWL<61> A_RWL<60> A_RWL<59> A_RWL<58> A_RWL<57> A_RWL<56> A_RWL<55> A_RWL<54> A_RWL<53> A_RWL<52> A_RWL<51> A_RWL<50> A_RWL<49> A_RWL<48> A_RWL<47> A_RWL<46> A_RWL<45> A_RWL<44> A_RWL<43> A_RWL<42> A_RWL<41> A_RWL<40> A_RWL<39> A_RWL<38> A_RWL<37> A_RWL<36> A_RWL<35> A_RWL<34> A_RWL<33> A_RWL<32> A_RWL<31> A_RWL<30> A_RWL<29> A_RWL<28> A_RWL<27> A_RWL<26> A_RWL<25> A_RWL<24> A_RWL<23> A_RWL<22> A_RWL<21> A_RWL<20> A_RWL<19> A_RWL<18> A_RWL<17> A_RWL<16> A_RWL<15> A_RWL<14> A_RWL<13> A_RWL<12> A_RWL<11> A_RWL<10> A_RWL<9> A_RWL<8> A_RWL<7> A_RWL<6> A_RWL<5> A_RWL<4> A_RWL<3> A_RWL<2> A_RWL<1> A_RWL<0> VDD_CORE VSS +XRAM<8> A_BLC<13> A_BLC<12> A_BLC_TOP<1> A_BLC_TOP<0> A_BLT<13> A_BLT<12> A_BLT_TOP<1> A_BLT_TOP<0> A_LWL<127> A_LWL<126> A_LWL<125> A_LWL<124> A_LWL<123> A_LWL<122> A_LWL<121> A_LWL<120> A_LWL<119> A_LWL<118> A_LWL<117> A_LWL<116> A_LWL<115> A_LWL<114> A_LWL<113> A_LWL<112> A_RWL<127> A_RWL<126> A_RWL<125> A_RWL<124> A_RWL<123> A_RWL<122> A_RWL<121> A_RWL<120> A_RWL<119> A_RWL<118> A_RWL<117> A_RWL<116> A_RWL<115> A_RWL<114> A_RWL<113> A_RWL<112> VDD_CORE VSS / RM_IHPSG13_512x16_c2_1P_BITKIT_16x2_SRAM +XRAM<7> A_BLC<11> A_BLC<10> A_BLC<13> A_BLC<12> A_BLT<11> A_BLT<10> A_BLT<13> A_BLT<12> A_LWL<111> A_LWL<110> A_LWL<109> A_LWL<108> A_LWL<107> A_LWL<106> A_LWL<105> A_LWL<104> A_LWL<103> A_LWL<102> A_LWL<101> A_LWL<100> A_LWL<99> A_LWL<98> A_LWL<97> A_LWL<96> A_RWL<111> A_RWL<110> A_RWL<109> A_RWL<108> A_RWL<107> A_RWL<106> A_RWL<105> A_RWL<104> A_RWL<103> A_RWL<102> A_RWL<101> A_RWL<100> A_RWL<99> A_RWL<98> A_RWL<97> A_RWL<96> VDD_CORE VSS / RM_IHPSG13_512x16_c2_1P_BITKIT_16x2_SRAM +XRAM<6> A_BLC<9> A_BLC<8> A_BLC<11> A_BLC<10> A_BLT<9> A_BLT<8> A_BLT<11> A_BLT<10> A_LWL<95> A_LWL<94> A_LWL<93> A_LWL<92> A_LWL<91> A_LWL<90> A_LWL<89> A_LWL<88> A_LWL<87> A_LWL<86> A_LWL<85> A_LWL<84> A_LWL<83> A_LWL<82> A_LWL<81> A_LWL<80> A_RWL<95> A_RWL<94> A_RWL<93> A_RWL<92> A_RWL<91> A_RWL<90> A_RWL<89> A_RWL<88> A_RWL<87> A_RWL<86> A_RWL<85> A_RWL<84> A_RWL<83> A_RWL<82> A_RWL<81> A_RWL<80> VDD_CORE VSS / RM_IHPSG13_512x16_c2_1P_BITKIT_16x2_SRAM +XRAM<5> A_BLC<7> A_BLC<6> A_BLC<9> A_BLC<8> A_BLT<7> A_BLT<6> A_BLT<9> A_BLT<8> A_LWL<79> A_LWL<78> A_LWL<77> A_LWL<76> A_LWL<75> A_LWL<74> A_LWL<73> A_LWL<72> A_LWL<71> A_LWL<70> A_LWL<69> A_LWL<68> A_LWL<67> A_LWL<66> A_LWL<65> A_LWL<64> A_RWL<79> A_RWL<78> A_RWL<77> A_RWL<76> A_RWL<75> A_RWL<74> A_RWL<73> A_RWL<72> A_RWL<71> A_RWL<70> A_RWL<69> A_RWL<68> A_RWL<67> A_RWL<66> A_RWL<65> A_RWL<64> VDD_CORE VSS / RM_IHPSG13_512x16_c2_1P_BITKIT_16x2_SRAM +XRAM<4> A_BLC<5> A_BLC<4> A_BLC<7> A_BLC<6> A_BLT<5> A_BLT<4> A_BLT<7> A_BLT<6> A_LWL<63> A_LWL<62> A_LWL<61> A_LWL<60> A_LWL<59> A_LWL<58> A_LWL<57> A_LWL<56> A_LWL<55> A_LWL<54> A_LWL<53> A_LWL<52> A_LWL<51> A_LWL<50> A_LWL<49> A_LWL<48> A_RWL<63> A_RWL<62> A_RWL<61> A_RWL<60> A_RWL<59> A_RWL<58> A_RWL<57> A_RWL<56> A_RWL<55> A_RWL<54> A_RWL<53> A_RWL<52> A_RWL<51> A_RWL<50> A_RWL<49> A_RWL<48> VDD_CORE VSS / RM_IHPSG13_512x16_c2_1P_BITKIT_16x2_SRAM +XRAM<3> A_BLC<3> A_BLC<2> A_BLC<5> A_BLC<4> A_BLT<3> A_BLT<2> A_BLT<5> A_BLT<4> A_LWL<47> A_LWL<46> A_LWL<45> A_LWL<44> A_LWL<43> A_LWL<42> A_LWL<41> A_LWL<40> A_LWL<39> A_LWL<38> A_LWL<37> A_LWL<36> A_LWL<35> A_LWL<34> A_LWL<33> A_LWL<32> A_RWL<47> A_RWL<46> A_RWL<45> A_RWL<44> A_RWL<43> A_RWL<42> A_RWL<41> A_RWL<40> A_RWL<39> A_RWL<38> A_RWL<37> A_RWL<36> A_RWL<35> A_RWL<34> A_RWL<33> A_RWL<32> VDD_CORE VSS / RM_IHPSG13_512x16_c2_1P_BITKIT_16x2_SRAM +XRAM<2> A_BLC<1> A_BLC<0> A_BLC<3> A_BLC<2> A_BLT<1> A_BLT<0> A_BLT<3> A_BLT<2> A_LWL<31> A_LWL<30> A_LWL<29> A_LWL<28> A_LWL<27> A_LWL<26> A_LWL<25> A_LWL<24> A_LWL<23> A_LWL<22> A_LWL<21> A_LWL<20> A_LWL<19> A_LWL<18> A_LWL<17> A_LWL<16> A_RWL<31> A_RWL<30> A_RWL<29> A_RWL<28> A_RWL<27> A_RWL<26> A_RWL<25> A_RWL<24> A_RWL<23> A_RWL<22> A_RWL<21> A_RWL<20> A_RWL<19> A_RWL<18> A_RWL<17> A_RWL<16> VDD_CORE VSS / RM_IHPSG13_512x16_c2_1P_BITKIT_16x2_SRAM +XRAM<1> A_BLC_BOT<1> A_BLC_BOT<0> A_BLC<1> A_BLC<0> A_BLT_BOT<1> A_BLT_BOT<0> A_BLT<1> A_BLT<0> A_LWL<15> A_LWL<14> A_LWL<13> A_LWL<12> A_LWL<11> A_LWL<10> A_LWL<9> A_LWL<8> A_LWL<7> A_LWL<6> A_LWL<5> A_LWL<4> A_LWL<3> A_LWL<2> A_LWL<1> A_LWL<0> A_RWL<15> A_RWL<14> A_RWL<13> A_RWL<12> A_RWL<11> A_RWL<10> A_RWL<9> A_RWL<8> A_RWL<7> A_RWL<6> A_RWL<5> A_RWL<4> A_RWL<3> A_RWL<2> A_RWL<1> A_RWL<0> VDD_CORE VSS / RM_IHPSG13_512x16_c2_1P_BITKIT_16x2_SRAM +XEDGE<1> A_BLC_TOP<1> A_BLC_TOP<0> A_BLT_TOP<1> A_BLT_TOP<0> VDD_CORE VSS / RM_IHPSG13_512x16_c2_1P_BITKIT_16x2_EDGE_TB +XEDGE<0> A_BLC_BOT<1> A_BLC_BOT<0> A_BLT_BOT<1> A_BLT_BOT<0> VDD_CORE VSS / RM_IHPSG13_512x16_c2_1P_BITKIT_16x2_EDGE_TB +.ENDS + + + + +.SUBCKT RM_IHPSG13_512x16_c2_1P_MATRIX_pcell_1 A_BLC<31> A_BLC<30> A_BLC<29> A_BLC<28> A_BLC<27> A_BLC<26> A_BLC<25> A_BLC<24> A_BLC<23> A_BLC<22> A_BLC<21> A_BLC<20> A_BLC<19> A_BLC<18> A_BLC<17> A_BLC<16> A_BLC<15> A_BLC<14> A_BLC<13> A_BLC<12> A_BLC<11> A_BLC<10> A_BLC<9> A_BLC<8> A_BLC<7> A_BLC<6> A_BLC<5> A_BLC<4> A_BLC<3> A_BLC<2> A_BLC<1> A_BLC<0> A_BLT<31> A_BLT<30> A_BLT<29> A_BLT<28> A_BLT<27> A_BLT<26> A_BLT<25> A_BLT<24> A_BLT<23> A_BLT<22> A_BLT<21> A_BLT<20> A_BLT<19> A_BLT<18> A_BLT<17> A_BLT<16> A_BLT<15> A_BLT<14> A_BLT<13> A_BLT<12> A_BLT<11> A_BLT<10> A_BLT<9> A_BLT<8> A_BLT<7> A_BLT<6> A_BLT<5> A_BLT<4> A_BLT<3> A_BLT<2> A_BLT<1> A_BLT<0> A_WL<127> A_WL<126> A_WL<125> A_WL<124> A_WL<123> A_WL<122> A_WL<121> A_WL<120> A_WL<119> A_WL<118> A_WL<117> A_WL<116> A_WL<115> A_WL<114> A_WL<113> A_WL<112> A_WL<111> A_WL<110> A_WL<109> A_WL<108> A_WL<107> A_WL<106> A_WL<105> A_WL<104> A_WL<103> A_WL<102> A_WL<101> A_WL<100> A_WL<99> A_WL<98> A_WL<97> A_WL<96> A_WL<95> A_WL<94> A_WL<93> A_WL<92> A_WL<91> A_WL<90> A_WL<89> A_WL<88> A_WL<87> A_WL<86> A_WL<85> A_WL<84> A_WL<83> A_WL<82> A_WL<81> A_WL<80> A_WL<79> A_WL<78> A_WL<77> A_WL<76> A_WL<75> A_WL<74> A_WL<73> A_WL<72> A_WL<71> A_WL<70> A_WL<69> A_WL<68> A_WL<67> A_WL<66> A_WL<65> A_WL<64> A_WL<63> A_WL<62> A_WL<61> A_WL<60> A_WL<59> A_WL<58> A_WL<57> A_WL<56> A_WL<55> A_WL<54> A_WL<53> A_WL<52> A_WL<51> A_WL<50> A_WL<49> A_WL<48> A_WL<47> A_WL<46> A_WL<45> A_WL<44> A_WL<43> A_WL<42> A_WL<41> A_WL<40> A_WL<39> A_WL<38> A_WL<37> A_WL<36> A_WL<35> A_WL<34> A_WL<33> A_WL<32> A_WL<31> A_WL<30> A_WL<29> A_WL<28> A_WL<27> A_WL<26> A_WL<25> A_WL<24> A_WL<23> A_WL<22> A_WL<21> A_WL<20> A_WL<19> A_WL<18> A_WL<17> A_WL<16> A_WL<15> A_WL<14> A_WL<13> A_WL<12> A_WL<11> A_WL<10> A_WL<9> A_WL<8> A_WL<7> A_WL<6> A_WL<5> A_WL<4> A_WL<3> A_WL<2> A_WL<1> A_WL<0> VDD_CORE VSS +XCORNER<3> VDD_CORE VSS / RM_IHPSG13_512x16_c2_1P_BITKIT_16x2_CORNER +XCORNER<2> VDD_CORE VSS / RM_IHPSG13_512x16_c2_1P_BITKIT_16x2_CORNER +XCORNER<1> VDD_CORE VSS / RM_IHPSG13_512x16_c2_1P_BITKIT_16x2_CORNER +XCORNER<0> VDD_CORE VSS / RM_IHPSG13_512x16_c2_1P_BITKIT_16x2_CORNER +XRAMEDGE_L<7> A_WL<127> A_WL<126> A_WL<125> A_WL<124> A_WL<123> A_WL<122> A_WL<121> A_WL<120> A_WL<119> A_WL<118> A_WL<117> A_WL<116> A_WL<115> A_WL<114> A_WL<113> A_WL<112> VDD_CORE VSS / RM_IHPSG13_512x16_c2_1P_BITKIT_16x2_EDGE_LR +XRAMEDGE_L<6> A_WL<111> A_WL<110> A_WL<109> A_WL<108> A_WL<107> A_WL<106> A_WL<105> A_WL<104> A_WL<103> A_WL<102> A_WL<101> A_WL<100> A_WL<99> A_WL<98> A_WL<97> A_WL<96> VDD_CORE VSS / RM_IHPSG13_512x16_c2_1P_BITKIT_16x2_EDGE_LR +XRAMEDGE_L<5> A_WL<95> A_WL<94> A_WL<93> A_WL<92> A_WL<91> A_WL<90> A_WL<89> A_WL<88> A_WL<87> A_WL<86> A_WL<85> A_WL<84> A_WL<83> A_WL<82> A_WL<81> A_WL<80> VDD_CORE VSS / RM_IHPSG13_512x16_c2_1P_BITKIT_16x2_EDGE_LR +XRAMEDGE_L<4> A_WL<79> A_WL<78> A_WL<77> A_WL<76> A_WL<75> A_WL<74> A_WL<73> A_WL<72> A_WL<71> A_WL<70> A_WL<69> A_WL<68> A_WL<67> A_WL<66> A_WL<65> A_WL<64> VDD_CORE VSS / RM_IHPSG13_512x16_c2_1P_BITKIT_16x2_EDGE_LR +XRAMEDGE_L<3> A_WL<63> A_WL<62> A_WL<61> A_WL<60> A_WL<59> A_WL<58> A_WL<57> A_WL<56> A_WL<55> A_WL<54> A_WL<53> A_WL<52> A_WL<51> A_WL<50> A_WL<49> A_WL<48> VDD_CORE VSS / RM_IHPSG13_512x16_c2_1P_BITKIT_16x2_EDGE_LR +XRAMEDGE_L<2> A_WL<47> A_WL<46> A_WL<45> A_WL<44> A_WL<43> A_WL<42> A_WL<41> A_WL<40> A_WL<39> A_WL<38> A_WL<37> A_WL<36> A_WL<35> A_WL<34> A_WL<33> A_WL<32> VDD_CORE VSS / RM_IHPSG13_512x16_c2_1P_BITKIT_16x2_EDGE_LR +XRAMEDGE_L<1> A_WL<31> A_WL<30> A_WL<29> A_WL<28> A_WL<27> A_WL<26> A_WL<25> A_WL<24> A_WL<23> A_WL<22> A_WL<21> A_WL<20> A_WL<19> A_WL<18> A_WL<17> A_WL<16> VDD_CORE VSS / RM_IHPSG13_512x16_c2_1P_BITKIT_16x2_EDGE_LR +XRAMEDGE_L<0> A_WL<15> A_WL<14> A_WL<13> A_WL<12> A_WL<11> A_WL<10> A_WL<9> A_WL<8> A_WL<7> A_WL<6> A_WL<5> A_WL<4> A_WL<3> A_WL<2> A_WL<1> A_WL<0> VDD_CORE VSS / RM_IHPSG13_512x16_c2_1P_BITKIT_16x2_EDGE_LR +XRAMEDGE_R<7> A_IWL<2047> A_IWL<2046> A_IWL<2045> A_IWL<2044> A_IWL<2043> A_IWL<2042> A_IWL<2041> A_IWL<2040> A_IWL<2039> A_IWL<2038> A_IWL<2037> A_IWL<2036> A_IWL<2035> A_IWL<2034> A_IWL<2033> A_IWL<2032> VDD_CORE VSS / RM_IHPSG13_512x16_c2_1P_BITKIT_16x2_EDGE_LR +XRAMEDGE_R<6> A_IWL<2031> A_IWL<2030> A_IWL<2029> A_IWL<2028> A_IWL<2027> A_IWL<2026> A_IWL<2025> A_IWL<2024> A_IWL<2023> A_IWL<2022> A_IWL<2021> A_IWL<2020> A_IWL<2019> A_IWL<2018> A_IWL<2017> A_IWL<2016> VDD_CORE VSS / RM_IHPSG13_512x16_c2_1P_BITKIT_16x2_EDGE_LR +XRAMEDGE_R<5> A_IWL<2015> A_IWL<2014> A_IWL<2013> A_IWL<2012> A_IWL<2011> A_IWL<2010> A_IWL<2009> A_IWL<2008> A_IWL<2007> A_IWL<2006> A_IWL<2005> A_IWL<2004> A_IWL<2003> A_IWL<2002> A_IWL<2001> A_IWL<2000> VDD_CORE VSS / RM_IHPSG13_512x16_c2_1P_BITKIT_16x2_EDGE_LR +XRAMEDGE_R<4> A_IWL<1999> A_IWL<1998> A_IWL<1997> A_IWL<1996> A_IWL<1995> A_IWL<1994> A_IWL<1993> A_IWL<1992> A_IWL<1991> A_IWL<1990> A_IWL<1989> A_IWL<1988> A_IWL<1987> A_IWL<1986> A_IWL<1985> A_IWL<1984> VDD_CORE VSS / RM_IHPSG13_512x16_c2_1P_BITKIT_16x2_EDGE_LR +XRAMEDGE_R<3> A_IWL<1983> A_IWL<1982> A_IWL<1981> A_IWL<1980> A_IWL<1979> A_IWL<1978> A_IWL<1977> A_IWL<1976> A_IWL<1975> A_IWL<1974> A_IWL<1973> A_IWL<1972> A_IWL<1971> A_IWL<1970> A_IWL<1969> A_IWL<1968> VDD_CORE VSS / RM_IHPSG13_512x16_c2_1P_BITKIT_16x2_EDGE_LR +XRAMEDGE_R<2> A_IWL<1967> A_IWL<1966> A_IWL<1965> A_IWL<1964> A_IWL<1963> A_IWL<1962> A_IWL<1961> A_IWL<1960> A_IWL<1959> A_IWL<1958> A_IWL<1957> A_IWL<1956> A_IWL<1955> A_IWL<1954> A_IWL<1953> A_IWL<1952> VDD_CORE VSS / RM_IHPSG13_512x16_c2_1P_BITKIT_16x2_EDGE_LR +XRAMEDGE_R<1> A_IWL<1951> A_IWL<1950> A_IWL<1949> A_IWL<1948> A_IWL<1947> A_IWL<1946> A_IWL<1945> A_IWL<1944> A_IWL<1943> A_IWL<1942> A_IWL<1941> A_IWL<1940> A_IWL<1939> A_IWL<1938> A_IWL<1937> A_IWL<1936> VDD_CORE VSS / RM_IHPSG13_512x16_c2_1P_BITKIT_16x2_EDGE_LR +XRAMEDGE_R<0> A_IWL<1935> A_IWL<1934> A_IWL<1933> A_IWL<1932> A_IWL<1931> A_IWL<1930> A_IWL<1929> A_IWL<1928> A_IWL<1927> A_IWL<1926> A_IWL<1925> A_IWL<1924> A_IWL<1923> A_IWL<1922> A_IWL<1921> A_IWL<1920> VDD_CORE VSS / RM_IHPSG13_512x16_c2_1P_BITKIT_16x2_EDGE_LR +XCOL<15> A_BLC<31> A_BLC<30> A_BLC_TOP<31> A_BLC_TOP<30> A_BLT<31> A_BLT<30> A_BLT_TOP<31> A_BLT_TOP<30> A_IWL<1919> A_IWL<1918> A_IWL<1917> A_IWL<1916> A_IWL<1915> A_IWL<1914> A_IWL<1913> A_IWL<1912> A_IWL<1911> A_IWL<1910> A_IWL<1909> A_IWL<1908> A_IWL<1907> A_IWL<1906> A_IWL<1905> A_IWL<1904> A_IWL<1903> A_IWL<1902> A_IWL<1901> A_IWL<1900> A_IWL<1899> A_IWL<1898> A_IWL<1897> A_IWL<1896> A_IWL<1895> A_IWL<1894> A_IWL<1893> A_IWL<1892> A_IWL<1891> A_IWL<1890> A_IWL<1889> A_IWL<1888> A_IWL<1887> A_IWL<1886> A_IWL<1885> A_IWL<1884> A_IWL<1883> A_IWL<1882> A_IWL<1881> A_IWL<1880> A_IWL<1879> A_IWL<1878> A_IWL<1877> A_IWL<1876> A_IWL<1875> A_IWL<1874> A_IWL<1873> A_IWL<1872> A_IWL<1871> A_IWL<1870> A_IWL<1869> A_IWL<1868> A_IWL<1867> A_IWL<1866> A_IWL<1865> A_IWL<1864> A_IWL<1863> A_IWL<1862> A_IWL<1861> A_IWL<1860> A_IWL<1859> A_IWL<1858> A_IWL<1857> A_IWL<1856> A_IWL<1855> A_IWL<1854> A_IWL<1853> A_IWL<1852> A_IWL<1851> A_IWL<1850> A_IWL<1849> A_IWL<1848> A_IWL<1847> A_IWL<1846> A_IWL<1845> A_IWL<1844> A_IWL<1843> A_IWL<1842> A_IWL<1841> A_IWL<1840> A_IWL<1839> A_IWL<1838> A_IWL<1837> A_IWL<1836> A_IWL<1835> A_IWL<1834> A_IWL<1833> A_IWL<1832> A_IWL<1831> A_IWL<1830> A_IWL<1829> A_IWL<1828> A_IWL<1827> A_IWL<1826> A_IWL<1825> A_IWL<1824> A_IWL<1823> A_IWL<1822> A_IWL<1821> A_IWL<1820> A_IWL<1819> A_IWL<1818> A_IWL<1817> A_IWL<1816> A_IWL<1815> A_IWL<1814> A_IWL<1813> A_IWL<1812> A_IWL<1811> A_IWL<1810> A_IWL<1809> A_IWL<1808> A_IWL<1807> A_IWL<1806> A_IWL<1805> A_IWL<1804> A_IWL<1803> A_IWL<1802> A_IWL<1801> A_IWL<1800> A_IWL<1799> A_IWL<1798> A_IWL<1797> A_IWL<1796> A_IWL<1795> A_IWL<1794> A_IWL<1793> A_IWL<1792> A_IWL<2047> A_IWL<2046> A_IWL<2045> A_IWL<2044> A_IWL<2043> A_IWL<2042> A_IWL<2041> A_IWL<2040> A_IWL<2039> A_IWL<2038> A_IWL<2037> A_IWL<2036> A_IWL<2035> A_IWL<2034> A_IWL<2033> A_IWL<2032> A_IWL<2031> A_IWL<2030> A_IWL<2029> A_IWL<2028> A_IWL<2027> A_IWL<2026> A_IWL<2025> A_IWL<2024> A_IWL<2023> A_IWL<2022> A_IWL<2021> A_IWL<2020> A_IWL<2019> A_IWL<2018> A_IWL<2017> A_IWL<2016> A_IWL<2015> A_IWL<2014> A_IWL<2013> A_IWL<2012> A_IWL<2011> A_IWL<2010> A_IWL<2009> A_IWL<2008> A_IWL<2007> A_IWL<2006> A_IWL<2005> A_IWL<2004> A_IWL<2003> A_IWL<2002> A_IWL<2001> A_IWL<2000> A_IWL<1999> A_IWL<1998> A_IWL<1997> A_IWL<1996> A_IWL<1995> A_IWL<1994> A_IWL<1993> A_IWL<1992> A_IWL<1991> A_IWL<1990> A_IWL<1989> A_IWL<1988> A_IWL<1987> A_IWL<1986> A_IWL<1985> A_IWL<1984> A_IWL<1983> A_IWL<1982> A_IWL<1981> A_IWL<1980> A_IWL<1979> A_IWL<1978> A_IWL<1977> A_IWL<1976> A_IWL<1975> A_IWL<1974> A_IWL<1973> A_IWL<1972> A_IWL<1971> A_IWL<1970> A_IWL<1969> A_IWL<1968> A_IWL<1967> A_IWL<1966> A_IWL<1965> A_IWL<1964> A_IWL<1963> A_IWL<1962> A_IWL<1961> A_IWL<1960> A_IWL<1959> A_IWL<1958> A_IWL<1957> A_IWL<1956> A_IWL<1955> A_IWL<1954> A_IWL<1953> A_IWL<1952> A_IWL<1951> A_IWL<1950> A_IWL<1949> A_IWL<1948> A_IWL<1947> A_IWL<1946> A_IWL<1945> A_IWL<1944> A_IWL<1943> A_IWL<1942> A_IWL<1941> A_IWL<1940> A_IWL<1939> A_IWL<1938> A_IWL<1937> A_IWL<1936> A_IWL<1935> A_IWL<1934> A_IWL<1933> A_IWL<1932> A_IWL<1931> A_IWL<1930> A_IWL<1929> A_IWL<1928> A_IWL<1927> A_IWL<1926> A_IWL<1925> A_IWL<1924> A_IWL<1923> A_IWL<1922> A_IWL<1921> A_IWL<1920> VDD_CORE VSS / RM_IHPSG13_512x16_c2_1P_COLUMN_pcell_0 +XCOL<14> A_BLC<29> A_BLC<28> A_BLC_TOP<29> A_BLC_TOP<28> A_BLT<29> A_BLT<28> A_BLT_TOP<29> A_BLT_TOP<28> A_IWL<1791> A_IWL<1790> A_IWL<1789> A_IWL<1788> A_IWL<1787> A_IWL<1786> A_IWL<1785> A_IWL<1784> A_IWL<1783> A_IWL<1782> A_IWL<1781> A_IWL<1780> A_IWL<1779> A_IWL<1778> A_IWL<1777> A_IWL<1776> A_IWL<1775> A_IWL<1774> A_IWL<1773> A_IWL<1772> A_IWL<1771> A_IWL<1770> A_IWL<1769> A_IWL<1768> A_IWL<1767> A_IWL<1766> A_IWL<1765> A_IWL<1764> A_IWL<1763> A_IWL<1762> A_IWL<1761> A_IWL<1760> A_IWL<1759> A_IWL<1758> A_IWL<1757> A_IWL<1756> A_IWL<1755> A_IWL<1754> A_IWL<1753> A_IWL<1752> A_IWL<1751> A_IWL<1750> A_IWL<1749> A_IWL<1748> A_IWL<1747> A_IWL<1746> A_IWL<1745> A_IWL<1744> A_IWL<1743> A_IWL<1742> A_IWL<1741> A_IWL<1740> A_IWL<1739> A_IWL<1738> A_IWL<1737> A_IWL<1736> A_IWL<1735> A_IWL<1734> A_IWL<1733> A_IWL<1732> A_IWL<1731> A_IWL<1730> A_IWL<1729> A_IWL<1728> A_IWL<1727> A_IWL<1726> A_IWL<1725> A_IWL<1724> A_IWL<1723> A_IWL<1722> A_IWL<1721> A_IWL<1720> A_IWL<1719> A_IWL<1718> A_IWL<1717> A_IWL<1716> A_IWL<1715> A_IWL<1714> A_IWL<1713> A_IWL<1712> A_IWL<1711> A_IWL<1710> A_IWL<1709> A_IWL<1708> A_IWL<1707> A_IWL<1706> A_IWL<1705> A_IWL<1704> A_IWL<1703> A_IWL<1702> A_IWL<1701> A_IWL<1700> A_IWL<1699> A_IWL<1698> A_IWL<1697> A_IWL<1696> A_IWL<1695> A_IWL<1694> A_IWL<1693> A_IWL<1692> A_IWL<1691> A_IWL<1690> A_IWL<1689> A_IWL<1688> A_IWL<1687> A_IWL<1686> A_IWL<1685> A_IWL<1684> A_IWL<1683> A_IWL<1682> A_IWL<1681> A_IWL<1680> A_IWL<1679> A_IWL<1678> A_IWL<1677> A_IWL<1676> A_IWL<1675> A_IWL<1674> A_IWL<1673> A_IWL<1672> A_IWL<1671> A_IWL<1670> A_IWL<1669> A_IWL<1668> A_IWL<1667> A_IWL<1666> A_IWL<1665> A_IWL<1664> A_IWL<1919> A_IWL<1918> A_IWL<1917> A_IWL<1916> A_IWL<1915> A_IWL<1914> A_IWL<1913> A_IWL<1912> A_IWL<1911> A_IWL<1910> A_IWL<1909> A_IWL<1908> A_IWL<1907> A_IWL<1906> A_IWL<1905> A_IWL<1904> A_IWL<1903> A_IWL<1902> A_IWL<1901> A_IWL<1900> A_IWL<1899> A_IWL<1898> A_IWL<1897> A_IWL<1896> A_IWL<1895> A_IWL<1894> A_IWL<1893> A_IWL<1892> A_IWL<1891> A_IWL<1890> A_IWL<1889> A_IWL<1888> A_IWL<1887> A_IWL<1886> A_IWL<1885> A_IWL<1884> A_IWL<1883> A_IWL<1882> A_IWL<1881> A_IWL<1880> A_IWL<1879> A_IWL<1878> A_IWL<1877> A_IWL<1876> A_IWL<1875> A_IWL<1874> A_IWL<1873> A_IWL<1872> A_IWL<1871> A_IWL<1870> A_IWL<1869> A_IWL<1868> A_IWL<1867> A_IWL<1866> A_IWL<1865> A_IWL<1864> A_IWL<1863> A_IWL<1862> A_IWL<1861> A_IWL<1860> A_IWL<1859> A_IWL<1858> A_IWL<1857> A_IWL<1856> A_IWL<1855> A_IWL<1854> A_IWL<1853> A_IWL<1852> A_IWL<1851> A_IWL<1850> A_IWL<1849> A_IWL<1848> A_IWL<1847> A_IWL<1846> A_IWL<1845> A_IWL<1844> A_IWL<1843> A_IWL<1842> A_IWL<1841> A_IWL<1840> A_IWL<1839> A_IWL<1838> A_IWL<1837> A_IWL<1836> A_IWL<1835> A_IWL<1834> A_IWL<1833> A_IWL<1832> A_IWL<1831> A_IWL<1830> A_IWL<1829> A_IWL<1828> A_IWL<1827> A_IWL<1826> A_IWL<1825> A_IWL<1824> A_IWL<1823> A_IWL<1822> A_IWL<1821> A_IWL<1820> A_IWL<1819> A_IWL<1818> A_IWL<1817> A_IWL<1816> A_IWL<1815> A_IWL<1814> A_IWL<1813> A_IWL<1812> A_IWL<1811> A_IWL<1810> A_IWL<1809> A_IWL<1808> A_IWL<1807> A_IWL<1806> A_IWL<1805> A_IWL<1804> A_IWL<1803> A_IWL<1802> A_IWL<1801> A_IWL<1800> A_IWL<1799> A_IWL<1798> A_IWL<1797> A_IWL<1796> A_IWL<1795> A_IWL<1794> A_IWL<1793> A_IWL<1792> VDD_CORE VSS / RM_IHPSG13_512x16_c2_1P_COLUMN_pcell_0 +XCOL<13> A_BLC<27> A_BLC<26> A_BLC_TOP<27> A_BLC_TOP<26> A_BLT<27> A_BLT<26> A_BLT_TOP<27> A_BLT_TOP<26> A_IWL<1663> A_IWL<1662> A_IWL<1661> A_IWL<1660> A_IWL<1659> A_IWL<1658> A_IWL<1657> A_IWL<1656> A_IWL<1655> A_IWL<1654> A_IWL<1653> A_IWL<1652> A_IWL<1651> A_IWL<1650> A_IWL<1649> A_IWL<1648> A_IWL<1647> A_IWL<1646> A_IWL<1645> A_IWL<1644> A_IWL<1643> A_IWL<1642> A_IWL<1641> A_IWL<1640> A_IWL<1639> A_IWL<1638> A_IWL<1637> A_IWL<1636> A_IWL<1635> A_IWL<1634> A_IWL<1633> A_IWL<1632> A_IWL<1631> A_IWL<1630> A_IWL<1629> A_IWL<1628> A_IWL<1627> A_IWL<1626> A_IWL<1625> A_IWL<1624> A_IWL<1623> A_IWL<1622> A_IWL<1621> A_IWL<1620> A_IWL<1619> A_IWL<1618> A_IWL<1617> A_IWL<1616> A_IWL<1615> A_IWL<1614> A_IWL<1613> A_IWL<1612> A_IWL<1611> A_IWL<1610> A_IWL<1609> A_IWL<1608> A_IWL<1607> A_IWL<1606> A_IWL<1605> A_IWL<1604> A_IWL<1603> A_IWL<1602> A_IWL<1601> A_IWL<1600> A_IWL<1599> A_IWL<1598> A_IWL<1597> A_IWL<1596> A_IWL<1595> A_IWL<1594> A_IWL<1593> A_IWL<1592> A_IWL<1591> A_IWL<1590> A_IWL<1589> A_IWL<1588> A_IWL<1587> A_IWL<1586> A_IWL<1585> A_IWL<1584> A_IWL<1583> A_IWL<1582> A_IWL<1581> A_IWL<1580> A_IWL<1579> A_IWL<1578> A_IWL<1577> A_IWL<1576> A_IWL<1575> A_IWL<1574> A_IWL<1573> A_IWL<1572> A_IWL<1571> A_IWL<1570> A_IWL<1569> A_IWL<1568> A_IWL<1567> A_IWL<1566> A_IWL<1565> A_IWL<1564> A_IWL<1563> A_IWL<1562> A_IWL<1561> A_IWL<1560> A_IWL<1559> A_IWL<1558> A_IWL<1557> A_IWL<1556> A_IWL<1555> A_IWL<1554> A_IWL<1553> A_IWL<1552> A_IWL<1551> A_IWL<1550> A_IWL<1549> A_IWL<1548> A_IWL<1547> A_IWL<1546> A_IWL<1545> A_IWL<1544> A_IWL<1543> A_IWL<1542> A_IWL<1541> A_IWL<1540> A_IWL<1539> A_IWL<1538> A_IWL<1537> A_IWL<1536> A_IWL<1791> A_IWL<1790> A_IWL<1789> A_IWL<1788> A_IWL<1787> A_IWL<1786> A_IWL<1785> A_IWL<1784> A_IWL<1783> A_IWL<1782> A_IWL<1781> A_IWL<1780> A_IWL<1779> A_IWL<1778> A_IWL<1777> A_IWL<1776> A_IWL<1775> A_IWL<1774> A_IWL<1773> A_IWL<1772> A_IWL<1771> A_IWL<1770> A_IWL<1769> A_IWL<1768> A_IWL<1767> A_IWL<1766> A_IWL<1765> A_IWL<1764> A_IWL<1763> A_IWL<1762> A_IWL<1761> A_IWL<1760> A_IWL<1759> A_IWL<1758> A_IWL<1757> A_IWL<1756> A_IWL<1755> A_IWL<1754> A_IWL<1753> A_IWL<1752> A_IWL<1751> A_IWL<1750> A_IWL<1749> A_IWL<1748> A_IWL<1747> A_IWL<1746> A_IWL<1745> A_IWL<1744> A_IWL<1743> A_IWL<1742> A_IWL<1741> A_IWL<1740> A_IWL<1739> A_IWL<1738> A_IWL<1737> A_IWL<1736> A_IWL<1735> A_IWL<1734> A_IWL<1733> A_IWL<1732> A_IWL<1731> A_IWL<1730> A_IWL<1729> A_IWL<1728> A_IWL<1727> A_IWL<1726> A_IWL<1725> A_IWL<1724> A_IWL<1723> A_IWL<1722> A_IWL<1721> A_IWL<1720> A_IWL<1719> A_IWL<1718> A_IWL<1717> A_IWL<1716> A_IWL<1715> A_IWL<1714> A_IWL<1713> A_IWL<1712> A_IWL<1711> A_IWL<1710> A_IWL<1709> A_IWL<1708> A_IWL<1707> A_IWL<1706> A_IWL<1705> A_IWL<1704> A_IWL<1703> A_IWL<1702> A_IWL<1701> A_IWL<1700> A_IWL<1699> A_IWL<1698> A_IWL<1697> A_IWL<1696> A_IWL<1695> A_IWL<1694> A_IWL<1693> A_IWL<1692> A_IWL<1691> A_IWL<1690> A_IWL<1689> A_IWL<1688> A_IWL<1687> A_IWL<1686> A_IWL<1685> A_IWL<1684> A_IWL<1683> A_IWL<1682> A_IWL<1681> A_IWL<1680> A_IWL<1679> A_IWL<1678> A_IWL<1677> A_IWL<1676> A_IWL<1675> A_IWL<1674> A_IWL<1673> A_IWL<1672> A_IWL<1671> A_IWL<1670> A_IWL<1669> A_IWL<1668> A_IWL<1667> A_IWL<1666> A_IWL<1665> A_IWL<1664> VDD_CORE VSS / RM_IHPSG13_512x16_c2_1P_COLUMN_pcell_0 +XCOL<12> A_BLC<25> A_BLC<24> A_BLC_TOP<25> A_BLC_TOP<24> A_BLT<25> A_BLT<24> A_BLT_TOP<25> A_BLT_TOP<24> A_IWL<1535> A_IWL<1534> A_IWL<1533> A_IWL<1532> A_IWL<1531> A_IWL<1530> A_IWL<1529> A_IWL<1528> A_IWL<1527> A_IWL<1526> A_IWL<1525> A_IWL<1524> A_IWL<1523> A_IWL<1522> A_IWL<1521> A_IWL<1520> A_IWL<1519> A_IWL<1518> A_IWL<1517> A_IWL<1516> A_IWL<1515> A_IWL<1514> A_IWL<1513> A_IWL<1512> A_IWL<1511> A_IWL<1510> A_IWL<1509> A_IWL<1508> A_IWL<1507> A_IWL<1506> A_IWL<1505> A_IWL<1504> A_IWL<1503> A_IWL<1502> A_IWL<1501> A_IWL<1500> A_IWL<1499> A_IWL<1498> A_IWL<1497> A_IWL<1496> A_IWL<1495> A_IWL<1494> A_IWL<1493> A_IWL<1492> A_IWL<1491> A_IWL<1490> A_IWL<1489> A_IWL<1488> A_IWL<1487> A_IWL<1486> A_IWL<1485> A_IWL<1484> A_IWL<1483> A_IWL<1482> A_IWL<1481> A_IWL<1480> A_IWL<1479> A_IWL<1478> A_IWL<1477> A_IWL<1476> A_IWL<1475> A_IWL<1474> A_IWL<1473> A_IWL<1472> A_IWL<1471> A_IWL<1470> A_IWL<1469> A_IWL<1468> A_IWL<1467> A_IWL<1466> A_IWL<1465> A_IWL<1464> A_IWL<1463> A_IWL<1462> A_IWL<1461> A_IWL<1460> A_IWL<1459> A_IWL<1458> A_IWL<1457> A_IWL<1456> A_IWL<1455> A_IWL<1454> A_IWL<1453> A_IWL<1452> A_IWL<1451> A_IWL<1450> A_IWL<1449> A_IWL<1448> A_IWL<1447> A_IWL<1446> A_IWL<1445> A_IWL<1444> A_IWL<1443> A_IWL<1442> A_IWL<1441> A_IWL<1440> A_IWL<1439> A_IWL<1438> A_IWL<1437> A_IWL<1436> A_IWL<1435> A_IWL<1434> A_IWL<1433> A_IWL<1432> A_IWL<1431> A_IWL<1430> A_IWL<1429> A_IWL<1428> A_IWL<1427> A_IWL<1426> A_IWL<1425> A_IWL<1424> A_IWL<1423> A_IWL<1422> A_IWL<1421> A_IWL<1420> A_IWL<1419> A_IWL<1418> A_IWL<1417> A_IWL<1416> A_IWL<1415> A_IWL<1414> A_IWL<1413> A_IWL<1412> A_IWL<1411> A_IWL<1410> A_IWL<1409> A_IWL<1408> A_IWL<1663> A_IWL<1662> A_IWL<1661> A_IWL<1660> A_IWL<1659> A_IWL<1658> A_IWL<1657> A_IWL<1656> A_IWL<1655> A_IWL<1654> A_IWL<1653> A_IWL<1652> A_IWL<1651> A_IWL<1650> A_IWL<1649> A_IWL<1648> A_IWL<1647> A_IWL<1646> A_IWL<1645> A_IWL<1644> A_IWL<1643> A_IWL<1642> A_IWL<1641> A_IWL<1640> A_IWL<1639> A_IWL<1638> A_IWL<1637> A_IWL<1636> A_IWL<1635> A_IWL<1634> A_IWL<1633> A_IWL<1632> A_IWL<1631> A_IWL<1630> A_IWL<1629> A_IWL<1628> A_IWL<1627> A_IWL<1626> A_IWL<1625> A_IWL<1624> A_IWL<1623> A_IWL<1622> A_IWL<1621> A_IWL<1620> A_IWL<1619> A_IWL<1618> A_IWL<1617> A_IWL<1616> A_IWL<1615> A_IWL<1614> A_IWL<1613> A_IWL<1612> A_IWL<1611> A_IWL<1610> A_IWL<1609> A_IWL<1608> A_IWL<1607> A_IWL<1606> A_IWL<1605> A_IWL<1604> A_IWL<1603> A_IWL<1602> A_IWL<1601> A_IWL<1600> A_IWL<1599> A_IWL<1598> A_IWL<1597> A_IWL<1596> A_IWL<1595> A_IWL<1594> A_IWL<1593> A_IWL<1592> A_IWL<1591> A_IWL<1590> A_IWL<1589> A_IWL<1588> A_IWL<1587> A_IWL<1586> A_IWL<1585> A_IWL<1584> A_IWL<1583> A_IWL<1582> A_IWL<1581> A_IWL<1580> A_IWL<1579> A_IWL<1578> A_IWL<1577> A_IWL<1576> A_IWL<1575> A_IWL<1574> A_IWL<1573> A_IWL<1572> A_IWL<1571> A_IWL<1570> A_IWL<1569> A_IWL<1568> A_IWL<1567> A_IWL<1566> A_IWL<1565> A_IWL<1564> A_IWL<1563> A_IWL<1562> A_IWL<1561> A_IWL<1560> A_IWL<1559> A_IWL<1558> A_IWL<1557> A_IWL<1556> A_IWL<1555> A_IWL<1554> A_IWL<1553> A_IWL<1552> A_IWL<1551> A_IWL<1550> A_IWL<1549> A_IWL<1548> A_IWL<1547> A_IWL<1546> A_IWL<1545> A_IWL<1544> A_IWL<1543> A_IWL<1542> A_IWL<1541> A_IWL<1540> A_IWL<1539> A_IWL<1538> A_IWL<1537> A_IWL<1536> VDD_CORE VSS / RM_IHPSG13_512x16_c2_1P_COLUMN_pcell_0 +XCOL<11> A_BLC<23> A_BLC<22> A_BLC_TOP<23> A_BLC_TOP<22> A_BLT<23> A_BLT<22> A_BLT_TOP<23> A_BLT_TOP<22> A_IWL<1407> A_IWL<1406> A_IWL<1405> A_IWL<1404> A_IWL<1403> A_IWL<1402> A_IWL<1401> A_IWL<1400> A_IWL<1399> A_IWL<1398> A_IWL<1397> A_IWL<1396> A_IWL<1395> A_IWL<1394> A_IWL<1393> A_IWL<1392> A_IWL<1391> A_IWL<1390> A_IWL<1389> A_IWL<1388> A_IWL<1387> A_IWL<1386> A_IWL<1385> A_IWL<1384> A_IWL<1383> A_IWL<1382> A_IWL<1381> A_IWL<1380> A_IWL<1379> A_IWL<1378> A_IWL<1377> A_IWL<1376> A_IWL<1375> A_IWL<1374> A_IWL<1373> A_IWL<1372> A_IWL<1371> A_IWL<1370> A_IWL<1369> A_IWL<1368> A_IWL<1367> A_IWL<1366> A_IWL<1365> A_IWL<1364> A_IWL<1363> A_IWL<1362> A_IWL<1361> A_IWL<1360> A_IWL<1359> A_IWL<1358> A_IWL<1357> A_IWL<1356> A_IWL<1355> A_IWL<1354> A_IWL<1353> A_IWL<1352> A_IWL<1351> A_IWL<1350> A_IWL<1349> A_IWL<1348> A_IWL<1347> A_IWL<1346> A_IWL<1345> A_IWL<1344> A_IWL<1343> A_IWL<1342> A_IWL<1341> A_IWL<1340> A_IWL<1339> A_IWL<1338> A_IWL<1337> A_IWL<1336> A_IWL<1335> A_IWL<1334> A_IWL<1333> A_IWL<1332> A_IWL<1331> A_IWL<1330> A_IWL<1329> A_IWL<1328> A_IWL<1327> A_IWL<1326> A_IWL<1325> A_IWL<1324> A_IWL<1323> A_IWL<1322> A_IWL<1321> A_IWL<1320> A_IWL<1319> A_IWL<1318> A_IWL<1317> A_IWL<1316> A_IWL<1315> A_IWL<1314> A_IWL<1313> A_IWL<1312> A_IWL<1311> A_IWL<1310> A_IWL<1309> A_IWL<1308> A_IWL<1307> A_IWL<1306> A_IWL<1305> A_IWL<1304> A_IWL<1303> A_IWL<1302> A_IWL<1301> A_IWL<1300> A_IWL<1299> A_IWL<1298> A_IWL<1297> A_IWL<1296> A_IWL<1295> A_IWL<1294> A_IWL<1293> A_IWL<1292> A_IWL<1291> A_IWL<1290> A_IWL<1289> A_IWL<1288> A_IWL<1287> A_IWL<1286> A_IWL<1285> A_IWL<1284> A_IWL<1283> A_IWL<1282> A_IWL<1281> A_IWL<1280> A_IWL<1535> A_IWL<1534> A_IWL<1533> A_IWL<1532> A_IWL<1531> A_IWL<1530> A_IWL<1529> A_IWL<1528> A_IWL<1527> A_IWL<1526> A_IWL<1525> A_IWL<1524> A_IWL<1523> A_IWL<1522> A_IWL<1521> A_IWL<1520> A_IWL<1519> A_IWL<1518> A_IWL<1517> A_IWL<1516> A_IWL<1515> A_IWL<1514> A_IWL<1513> A_IWL<1512> A_IWL<1511> A_IWL<1510> A_IWL<1509> A_IWL<1508> A_IWL<1507> A_IWL<1506> A_IWL<1505> A_IWL<1504> A_IWL<1503> A_IWL<1502> A_IWL<1501> A_IWL<1500> A_IWL<1499> A_IWL<1498> A_IWL<1497> A_IWL<1496> A_IWL<1495> A_IWL<1494> A_IWL<1493> A_IWL<1492> A_IWL<1491> A_IWL<1490> A_IWL<1489> A_IWL<1488> A_IWL<1487> A_IWL<1486> A_IWL<1485> A_IWL<1484> A_IWL<1483> A_IWL<1482> A_IWL<1481> A_IWL<1480> A_IWL<1479> A_IWL<1478> A_IWL<1477> A_IWL<1476> A_IWL<1475> A_IWL<1474> A_IWL<1473> A_IWL<1472> A_IWL<1471> A_IWL<1470> A_IWL<1469> A_IWL<1468> A_IWL<1467> A_IWL<1466> A_IWL<1465> A_IWL<1464> A_IWL<1463> A_IWL<1462> A_IWL<1461> A_IWL<1460> A_IWL<1459> A_IWL<1458> A_IWL<1457> A_IWL<1456> A_IWL<1455> A_IWL<1454> A_IWL<1453> A_IWL<1452> A_IWL<1451> A_IWL<1450> A_IWL<1449> A_IWL<1448> A_IWL<1447> A_IWL<1446> A_IWL<1445> A_IWL<1444> A_IWL<1443> A_IWL<1442> A_IWL<1441> A_IWL<1440> A_IWL<1439> A_IWL<1438> A_IWL<1437> A_IWL<1436> A_IWL<1435> A_IWL<1434> A_IWL<1433> A_IWL<1432> A_IWL<1431> A_IWL<1430> A_IWL<1429> A_IWL<1428> A_IWL<1427> A_IWL<1426> A_IWL<1425> A_IWL<1424> A_IWL<1423> A_IWL<1422> A_IWL<1421> A_IWL<1420> A_IWL<1419> A_IWL<1418> A_IWL<1417> A_IWL<1416> A_IWL<1415> A_IWL<1414> A_IWL<1413> A_IWL<1412> A_IWL<1411> A_IWL<1410> A_IWL<1409> A_IWL<1408> VDD_CORE VSS / RM_IHPSG13_512x16_c2_1P_COLUMN_pcell_0 +XCOL<10> A_BLC<21> A_BLC<20> A_BLC_TOP<21> A_BLC_TOP<20> A_BLT<21> A_BLT<20> A_BLT_TOP<21> A_BLT_TOP<20> A_IWL<1279> A_IWL<1278> A_IWL<1277> A_IWL<1276> A_IWL<1275> A_IWL<1274> A_IWL<1273> A_IWL<1272> A_IWL<1271> A_IWL<1270> A_IWL<1269> A_IWL<1268> A_IWL<1267> A_IWL<1266> A_IWL<1265> A_IWL<1264> A_IWL<1263> A_IWL<1262> A_IWL<1261> A_IWL<1260> A_IWL<1259> A_IWL<1258> A_IWL<1257> A_IWL<1256> A_IWL<1255> A_IWL<1254> A_IWL<1253> A_IWL<1252> A_IWL<1251> A_IWL<1250> A_IWL<1249> A_IWL<1248> A_IWL<1247> A_IWL<1246> A_IWL<1245> A_IWL<1244> A_IWL<1243> A_IWL<1242> A_IWL<1241> A_IWL<1240> A_IWL<1239> A_IWL<1238> A_IWL<1237> A_IWL<1236> A_IWL<1235> A_IWL<1234> A_IWL<1233> A_IWL<1232> A_IWL<1231> A_IWL<1230> A_IWL<1229> A_IWL<1228> A_IWL<1227> A_IWL<1226> A_IWL<1225> A_IWL<1224> A_IWL<1223> A_IWL<1222> A_IWL<1221> A_IWL<1220> A_IWL<1219> A_IWL<1218> A_IWL<1217> A_IWL<1216> A_IWL<1215> A_IWL<1214> A_IWL<1213> A_IWL<1212> A_IWL<1211> A_IWL<1210> A_IWL<1209> A_IWL<1208> A_IWL<1207> A_IWL<1206> A_IWL<1205> A_IWL<1204> A_IWL<1203> A_IWL<1202> A_IWL<1201> A_IWL<1200> A_IWL<1199> A_IWL<1198> A_IWL<1197> A_IWL<1196> A_IWL<1195> A_IWL<1194> A_IWL<1193> A_IWL<1192> A_IWL<1191> A_IWL<1190> A_IWL<1189> A_IWL<1188> A_IWL<1187> A_IWL<1186> A_IWL<1185> A_IWL<1184> A_IWL<1183> A_IWL<1182> A_IWL<1181> A_IWL<1180> A_IWL<1179> A_IWL<1178> A_IWL<1177> A_IWL<1176> A_IWL<1175> A_IWL<1174> A_IWL<1173> A_IWL<1172> A_IWL<1171> A_IWL<1170> A_IWL<1169> A_IWL<1168> A_IWL<1167> A_IWL<1166> A_IWL<1165> A_IWL<1164> A_IWL<1163> A_IWL<1162> A_IWL<1161> A_IWL<1160> A_IWL<1159> A_IWL<1158> A_IWL<1157> A_IWL<1156> A_IWL<1155> A_IWL<1154> A_IWL<1153> A_IWL<1152> A_IWL<1407> A_IWL<1406> A_IWL<1405> A_IWL<1404> A_IWL<1403> A_IWL<1402> A_IWL<1401> A_IWL<1400> A_IWL<1399> A_IWL<1398> A_IWL<1397> A_IWL<1396> A_IWL<1395> A_IWL<1394> A_IWL<1393> A_IWL<1392> A_IWL<1391> A_IWL<1390> A_IWL<1389> A_IWL<1388> A_IWL<1387> A_IWL<1386> A_IWL<1385> A_IWL<1384> A_IWL<1383> A_IWL<1382> A_IWL<1381> A_IWL<1380> A_IWL<1379> A_IWL<1378> A_IWL<1377> A_IWL<1376> A_IWL<1375> A_IWL<1374> A_IWL<1373> A_IWL<1372> A_IWL<1371> A_IWL<1370> A_IWL<1369> A_IWL<1368> A_IWL<1367> A_IWL<1366> A_IWL<1365> A_IWL<1364> A_IWL<1363> A_IWL<1362> A_IWL<1361> A_IWL<1360> A_IWL<1359> A_IWL<1358> A_IWL<1357> A_IWL<1356> A_IWL<1355> A_IWL<1354> A_IWL<1353> A_IWL<1352> A_IWL<1351> A_IWL<1350> A_IWL<1349> A_IWL<1348> A_IWL<1347> A_IWL<1346> A_IWL<1345> A_IWL<1344> A_IWL<1343> A_IWL<1342> A_IWL<1341> A_IWL<1340> A_IWL<1339> A_IWL<1338> A_IWL<1337> A_IWL<1336> A_IWL<1335> A_IWL<1334> A_IWL<1333> A_IWL<1332> A_IWL<1331> A_IWL<1330> A_IWL<1329> A_IWL<1328> A_IWL<1327> A_IWL<1326> A_IWL<1325> A_IWL<1324> A_IWL<1323> A_IWL<1322> A_IWL<1321> A_IWL<1320> A_IWL<1319> A_IWL<1318> A_IWL<1317> A_IWL<1316> A_IWL<1315> A_IWL<1314> A_IWL<1313> A_IWL<1312> A_IWL<1311> A_IWL<1310> A_IWL<1309> A_IWL<1308> A_IWL<1307> A_IWL<1306> A_IWL<1305> A_IWL<1304> A_IWL<1303> A_IWL<1302> A_IWL<1301> A_IWL<1300> A_IWL<1299> A_IWL<1298> A_IWL<1297> A_IWL<1296> A_IWL<1295> A_IWL<1294> A_IWL<1293> A_IWL<1292> A_IWL<1291> A_IWL<1290> A_IWL<1289> A_IWL<1288> A_IWL<1287> A_IWL<1286> A_IWL<1285> A_IWL<1284> A_IWL<1283> A_IWL<1282> A_IWL<1281> A_IWL<1280> VDD_CORE VSS / RM_IHPSG13_512x16_c2_1P_COLUMN_pcell_0 +XCOL<9> A_BLC<19> A_BLC<18> A_BLC_TOP<19> A_BLC_TOP<18> A_BLT<19> A_BLT<18> A_BLT_TOP<19> A_BLT_TOP<18> A_IWL<1151> A_IWL<1150> A_IWL<1149> A_IWL<1148> A_IWL<1147> A_IWL<1146> A_IWL<1145> A_IWL<1144> A_IWL<1143> A_IWL<1142> A_IWL<1141> A_IWL<1140> A_IWL<1139> A_IWL<1138> A_IWL<1137> A_IWL<1136> A_IWL<1135> A_IWL<1134> A_IWL<1133> A_IWL<1132> A_IWL<1131> A_IWL<1130> A_IWL<1129> A_IWL<1128> A_IWL<1127> A_IWL<1126> A_IWL<1125> A_IWL<1124> A_IWL<1123> A_IWL<1122> A_IWL<1121> A_IWL<1120> A_IWL<1119> A_IWL<1118> A_IWL<1117> A_IWL<1116> A_IWL<1115> A_IWL<1114> A_IWL<1113> A_IWL<1112> A_IWL<1111> A_IWL<1110> A_IWL<1109> A_IWL<1108> A_IWL<1107> A_IWL<1106> A_IWL<1105> A_IWL<1104> A_IWL<1103> A_IWL<1102> A_IWL<1101> A_IWL<1100> A_IWL<1099> A_IWL<1098> A_IWL<1097> A_IWL<1096> A_IWL<1095> A_IWL<1094> A_IWL<1093> A_IWL<1092> A_IWL<1091> A_IWL<1090> A_IWL<1089> A_IWL<1088> A_IWL<1087> A_IWL<1086> A_IWL<1085> A_IWL<1084> A_IWL<1083> A_IWL<1082> A_IWL<1081> A_IWL<1080> A_IWL<1079> A_IWL<1078> A_IWL<1077> A_IWL<1076> A_IWL<1075> A_IWL<1074> A_IWL<1073> A_IWL<1072> A_IWL<1071> A_IWL<1070> A_IWL<1069> A_IWL<1068> A_IWL<1067> A_IWL<1066> A_IWL<1065> A_IWL<1064> A_IWL<1063> A_IWL<1062> A_IWL<1061> A_IWL<1060> A_IWL<1059> A_IWL<1058> A_IWL<1057> A_IWL<1056> A_IWL<1055> A_IWL<1054> A_IWL<1053> A_IWL<1052> A_IWL<1051> A_IWL<1050> A_IWL<1049> A_IWL<1048> A_IWL<1047> A_IWL<1046> A_IWL<1045> A_IWL<1044> A_IWL<1043> A_IWL<1042> A_IWL<1041> A_IWL<1040> A_IWL<1039> A_IWL<1038> A_IWL<1037> A_IWL<1036> A_IWL<1035> A_IWL<1034> A_IWL<1033> A_IWL<1032> A_IWL<1031> A_IWL<1030> A_IWL<1029> A_IWL<1028> A_IWL<1027> A_IWL<1026> A_IWL<1025> A_IWL<1024> A_IWL<1279> A_IWL<1278> A_IWL<1277> A_IWL<1276> A_IWL<1275> A_IWL<1274> A_IWL<1273> A_IWL<1272> A_IWL<1271> A_IWL<1270> A_IWL<1269> A_IWL<1268> A_IWL<1267> A_IWL<1266> A_IWL<1265> A_IWL<1264> A_IWL<1263> A_IWL<1262> A_IWL<1261> A_IWL<1260> A_IWL<1259> A_IWL<1258> A_IWL<1257> A_IWL<1256> A_IWL<1255> A_IWL<1254> A_IWL<1253> A_IWL<1252> A_IWL<1251> A_IWL<1250> A_IWL<1249> A_IWL<1248> A_IWL<1247> A_IWL<1246> A_IWL<1245> A_IWL<1244> A_IWL<1243> A_IWL<1242> A_IWL<1241> A_IWL<1240> A_IWL<1239> A_IWL<1238> A_IWL<1237> A_IWL<1236> A_IWL<1235> A_IWL<1234> A_IWL<1233> A_IWL<1232> A_IWL<1231> A_IWL<1230> A_IWL<1229> A_IWL<1228> A_IWL<1227> A_IWL<1226> A_IWL<1225> A_IWL<1224> A_IWL<1223> A_IWL<1222> A_IWL<1221> A_IWL<1220> A_IWL<1219> A_IWL<1218> A_IWL<1217> A_IWL<1216> A_IWL<1215> A_IWL<1214> A_IWL<1213> A_IWL<1212> A_IWL<1211> A_IWL<1210> A_IWL<1209> A_IWL<1208> A_IWL<1207> A_IWL<1206> A_IWL<1205> A_IWL<1204> A_IWL<1203> A_IWL<1202> A_IWL<1201> A_IWL<1200> A_IWL<1199> A_IWL<1198> A_IWL<1197> A_IWL<1196> A_IWL<1195> A_IWL<1194> A_IWL<1193> A_IWL<1192> A_IWL<1191> A_IWL<1190> A_IWL<1189> A_IWL<1188> A_IWL<1187> A_IWL<1186> A_IWL<1185> A_IWL<1184> A_IWL<1183> A_IWL<1182> A_IWL<1181> A_IWL<1180> A_IWL<1179> A_IWL<1178> A_IWL<1177> A_IWL<1176> A_IWL<1175> A_IWL<1174> A_IWL<1173> A_IWL<1172> A_IWL<1171> A_IWL<1170> A_IWL<1169> A_IWL<1168> A_IWL<1167> A_IWL<1166> A_IWL<1165> A_IWL<1164> A_IWL<1163> A_IWL<1162> A_IWL<1161> A_IWL<1160> A_IWL<1159> A_IWL<1158> A_IWL<1157> A_IWL<1156> A_IWL<1155> A_IWL<1154> A_IWL<1153> A_IWL<1152> VDD_CORE VSS / RM_IHPSG13_512x16_c2_1P_COLUMN_pcell_0 +XCOL<8> A_BLC<17> A_BLC<16> A_BLC_TOP<17> A_BLC_TOP<16> A_BLT<17> A_BLT<16> A_BLT_TOP<17> A_BLT_TOP<16> A_IWL<1023> A_IWL<1022> A_IWL<1021> A_IWL<1020> A_IWL<1019> A_IWL<1018> A_IWL<1017> A_IWL<1016> A_IWL<1015> A_IWL<1014> A_IWL<1013> A_IWL<1012> A_IWL<1011> A_IWL<1010> A_IWL<1009> A_IWL<1008> A_IWL<1007> A_IWL<1006> A_IWL<1005> A_IWL<1004> A_IWL<1003> A_IWL<1002> A_IWL<1001> A_IWL<1000> A_IWL<999> A_IWL<998> A_IWL<997> A_IWL<996> A_IWL<995> A_IWL<994> A_IWL<993> A_IWL<992> A_IWL<991> A_IWL<990> A_IWL<989> A_IWL<988> A_IWL<987> A_IWL<986> A_IWL<985> A_IWL<984> A_IWL<983> A_IWL<982> A_IWL<981> A_IWL<980> A_IWL<979> A_IWL<978> A_IWL<977> A_IWL<976> A_IWL<975> A_IWL<974> A_IWL<973> A_IWL<972> A_IWL<971> A_IWL<970> A_IWL<969> A_IWL<968> A_IWL<967> A_IWL<966> A_IWL<965> A_IWL<964> A_IWL<963> A_IWL<962> A_IWL<961> A_IWL<960> A_IWL<959> A_IWL<958> A_IWL<957> A_IWL<956> A_IWL<955> A_IWL<954> A_IWL<953> A_IWL<952> A_IWL<951> A_IWL<950> A_IWL<949> A_IWL<948> A_IWL<947> A_IWL<946> A_IWL<945> A_IWL<944> A_IWL<943> A_IWL<942> A_IWL<941> A_IWL<940> A_IWL<939> A_IWL<938> A_IWL<937> A_IWL<936> A_IWL<935> A_IWL<934> A_IWL<933> A_IWL<932> A_IWL<931> A_IWL<930> A_IWL<929> A_IWL<928> A_IWL<927> A_IWL<926> A_IWL<925> A_IWL<924> A_IWL<923> A_IWL<922> A_IWL<921> A_IWL<920> A_IWL<919> A_IWL<918> A_IWL<917> A_IWL<916> A_IWL<915> A_IWL<914> A_IWL<913> A_IWL<912> A_IWL<911> A_IWL<910> A_IWL<909> A_IWL<908> A_IWL<907> A_IWL<906> A_IWL<905> A_IWL<904> A_IWL<903> A_IWL<902> A_IWL<901> A_IWL<900> A_IWL<899> A_IWL<898> A_IWL<897> A_IWL<896> A_IWL<1151> A_IWL<1150> A_IWL<1149> A_IWL<1148> A_IWL<1147> A_IWL<1146> A_IWL<1145> A_IWL<1144> A_IWL<1143> A_IWL<1142> A_IWL<1141> A_IWL<1140> A_IWL<1139> A_IWL<1138> A_IWL<1137> A_IWL<1136> A_IWL<1135> A_IWL<1134> A_IWL<1133> A_IWL<1132> A_IWL<1131> A_IWL<1130> A_IWL<1129> A_IWL<1128> A_IWL<1127> A_IWL<1126> A_IWL<1125> A_IWL<1124> A_IWL<1123> A_IWL<1122> A_IWL<1121> A_IWL<1120> A_IWL<1119> A_IWL<1118> A_IWL<1117> A_IWL<1116> A_IWL<1115> A_IWL<1114> A_IWL<1113> A_IWL<1112> A_IWL<1111> A_IWL<1110> A_IWL<1109> A_IWL<1108> A_IWL<1107> A_IWL<1106> A_IWL<1105> A_IWL<1104> A_IWL<1103> A_IWL<1102> A_IWL<1101> A_IWL<1100> A_IWL<1099> A_IWL<1098> A_IWL<1097> A_IWL<1096> A_IWL<1095> A_IWL<1094> A_IWL<1093> A_IWL<1092> A_IWL<1091> A_IWL<1090> A_IWL<1089> A_IWL<1088> A_IWL<1087> A_IWL<1086> A_IWL<1085> A_IWL<1084> A_IWL<1083> A_IWL<1082> A_IWL<1081> A_IWL<1080> A_IWL<1079> A_IWL<1078> A_IWL<1077> A_IWL<1076> A_IWL<1075> A_IWL<1074> A_IWL<1073> A_IWL<1072> A_IWL<1071> A_IWL<1070> A_IWL<1069> A_IWL<1068> A_IWL<1067> A_IWL<1066> A_IWL<1065> A_IWL<1064> A_IWL<1063> A_IWL<1062> A_IWL<1061> A_IWL<1060> A_IWL<1059> A_IWL<1058> A_IWL<1057> A_IWL<1056> A_IWL<1055> A_IWL<1054> A_IWL<1053> A_IWL<1052> A_IWL<1051> A_IWL<1050> A_IWL<1049> A_IWL<1048> A_IWL<1047> A_IWL<1046> A_IWL<1045> A_IWL<1044> A_IWL<1043> A_IWL<1042> A_IWL<1041> A_IWL<1040> A_IWL<1039> A_IWL<1038> A_IWL<1037> A_IWL<1036> A_IWL<1035> A_IWL<1034> A_IWL<1033> A_IWL<1032> A_IWL<1031> A_IWL<1030> A_IWL<1029> A_IWL<1028> A_IWL<1027> A_IWL<1026> A_IWL<1025> A_IWL<1024> VDD_CORE VSS / RM_IHPSG13_512x16_c2_1P_COLUMN_pcell_0 +XCOL<7> A_BLC<15> A_BLC<14> A_BLC_TOP<15> A_BLC_TOP<14> A_BLT<15> A_BLT<14> A_BLT_TOP<15> A_BLT_TOP<14> A_IWL<895> A_IWL<894> A_IWL<893> A_IWL<892> A_IWL<891> A_IWL<890> A_IWL<889> A_IWL<888> A_IWL<887> A_IWL<886> A_IWL<885> A_IWL<884> A_IWL<883> A_IWL<882> A_IWL<881> A_IWL<880> A_IWL<879> A_IWL<878> A_IWL<877> A_IWL<876> A_IWL<875> A_IWL<874> A_IWL<873> A_IWL<872> A_IWL<871> A_IWL<870> A_IWL<869> A_IWL<868> A_IWL<867> A_IWL<866> A_IWL<865> A_IWL<864> A_IWL<863> A_IWL<862> A_IWL<861> A_IWL<860> A_IWL<859> A_IWL<858> A_IWL<857> A_IWL<856> A_IWL<855> A_IWL<854> A_IWL<853> A_IWL<852> A_IWL<851> A_IWL<850> A_IWL<849> A_IWL<848> A_IWL<847> A_IWL<846> A_IWL<845> A_IWL<844> A_IWL<843> A_IWL<842> A_IWL<841> A_IWL<840> A_IWL<839> A_IWL<838> A_IWL<837> A_IWL<836> A_IWL<835> A_IWL<834> A_IWL<833> A_IWL<832> A_IWL<831> A_IWL<830> A_IWL<829> A_IWL<828> A_IWL<827> A_IWL<826> A_IWL<825> A_IWL<824> A_IWL<823> A_IWL<822> A_IWL<821> A_IWL<820> A_IWL<819> A_IWL<818> A_IWL<817> A_IWL<816> A_IWL<815> A_IWL<814> A_IWL<813> A_IWL<812> A_IWL<811> A_IWL<810> A_IWL<809> A_IWL<808> A_IWL<807> A_IWL<806> A_IWL<805> A_IWL<804> A_IWL<803> A_IWL<802> A_IWL<801> A_IWL<800> A_IWL<799> A_IWL<798> A_IWL<797> A_IWL<796> A_IWL<795> A_IWL<794> A_IWL<793> A_IWL<792> A_IWL<791> A_IWL<790> A_IWL<789> A_IWL<788> A_IWL<787> A_IWL<786> A_IWL<785> A_IWL<784> A_IWL<783> A_IWL<782> A_IWL<781> A_IWL<780> A_IWL<779> A_IWL<778> A_IWL<777> A_IWL<776> A_IWL<775> A_IWL<774> A_IWL<773> A_IWL<772> A_IWL<771> A_IWL<770> A_IWL<769> A_IWL<768> A_IWL<1023> A_IWL<1022> A_IWL<1021> A_IWL<1020> A_IWL<1019> A_IWL<1018> A_IWL<1017> A_IWL<1016> A_IWL<1015> A_IWL<1014> A_IWL<1013> A_IWL<1012> A_IWL<1011> A_IWL<1010> A_IWL<1009> A_IWL<1008> A_IWL<1007> A_IWL<1006> A_IWL<1005> A_IWL<1004> A_IWL<1003> A_IWL<1002> A_IWL<1001> A_IWL<1000> A_IWL<999> A_IWL<998> A_IWL<997> A_IWL<996> A_IWL<995> A_IWL<994> A_IWL<993> A_IWL<992> A_IWL<991> A_IWL<990> A_IWL<989> A_IWL<988> A_IWL<987> A_IWL<986> A_IWL<985> A_IWL<984> A_IWL<983> A_IWL<982> A_IWL<981> A_IWL<980> A_IWL<979> A_IWL<978> A_IWL<977> A_IWL<976> A_IWL<975> A_IWL<974> A_IWL<973> A_IWL<972> A_IWL<971> A_IWL<970> A_IWL<969> A_IWL<968> A_IWL<967> A_IWL<966> A_IWL<965> A_IWL<964> A_IWL<963> A_IWL<962> A_IWL<961> A_IWL<960> A_IWL<959> A_IWL<958> A_IWL<957> A_IWL<956> A_IWL<955> A_IWL<954> A_IWL<953> A_IWL<952> A_IWL<951> A_IWL<950> A_IWL<949> A_IWL<948> A_IWL<947> A_IWL<946> A_IWL<945> A_IWL<944> A_IWL<943> A_IWL<942> A_IWL<941> A_IWL<940> A_IWL<939> A_IWL<938> A_IWL<937> A_IWL<936> A_IWL<935> A_IWL<934> A_IWL<933> A_IWL<932> A_IWL<931> A_IWL<930> A_IWL<929> A_IWL<928> A_IWL<927> A_IWL<926> A_IWL<925> A_IWL<924> A_IWL<923> A_IWL<922> A_IWL<921> A_IWL<920> A_IWL<919> A_IWL<918> A_IWL<917> A_IWL<916> A_IWL<915> A_IWL<914> A_IWL<913> A_IWL<912> A_IWL<911> A_IWL<910> A_IWL<909> A_IWL<908> A_IWL<907> A_IWL<906> A_IWL<905> A_IWL<904> A_IWL<903> A_IWL<902> A_IWL<901> A_IWL<900> A_IWL<899> A_IWL<898> A_IWL<897> A_IWL<896> VDD_CORE VSS / RM_IHPSG13_512x16_c2_1P_COLUMN_pcell_0 +XCOL<6> A_BLC<13> A_BLC<12> A_BLC_TOP<13> A_BLC_TOP<12> A_BLT<13> A_BLT<12> A_BLT_TOP<13> A_BLT_TOP<12> A_IWL<767> A_IWL<766> A_IWL<765> A_IWL<764> A_IWL<763> A_IWL<762> A_IWL<761> A_IWL<760> A_IWL<759> A_IWL<758> A_IWL<757> A_IWL<756> A_IWL<755> A_IWL<754> A_IWL<753> A_IWL<752> A_IWL<751> A_IWL<750> A_IWL<749> A_IWL<748> A_IWL<747> A_IWL<746> A_IWL<745> A_IWL<744> A_IWL<743> A_IWL<742> A_IWL<741> A_IWL<740> A_IWL<739> A_IWL<738> A_IWL<737> A_IWL<736> A_IWL<735> A_IWL<734> A_IWL<733> A_IWL<732> A_IWL<731> A_IWL<730> A_IWL<729> A_IWL<728> A_IWL<727> A_IWL<726> A_IWL<725> A_IWL<724> A_IWL<723> A_IWL<722> A_IWL<721> A_IWL<720> A_IWL<719> A_IWL<718> A_IWL<717> A_IWL<716> A_IWL<715> A_IWL<714> A_IWL<713> A_IWL<712> A_IWL<711> A_IWL<710> A_IWL<709> A_IWL<708> A_IWL<707> A_IWL<706> A_IWL<705> A_IWL<704> A_IWL<703> A_IWL<702> A_IWL<701> A_IWL<700> A_IWL<699> A_IWL<698> A_IWL<697> A_IWL<696> A_IWL<695> A_IWL<694> A_IWL<693> A_IWL<692> A_IWL<691> A_IWL<690> A_IWL<689> A_IWL<688> A_IWL<687> A_IWL<686> A_IWL<685> A_IWL<684> A_IWL<683> A_IWL<682> A_IWL<681> A_IWL<680> A_IWL<679> A_IWL<678> A_IWL<677> A_IWL<676> A_IWL<675> A_IWL<674> A_IWL<673> A_IWL<672> A_IWL<671> A_IWL<670> A_IWL<669> A_IWL<668> A_IWL<667> A_IWL<666> A_IWL<665> A_IWL<664> A_IWL<663> A_IWL<662> A_IWL<661> A_IWL<660> A_IWL<659> A_IWL<658> A_IWL<657> A_IWL<656> A_IWL<655> A_IWL<654> A_IWL<653> A_IWL<652> A_IWL<651> A_IWL<650> A_IWL<649> A_IWL<648> A_IWL<647> A_IWL<646> A_IWL<645> A_IWL<644> A_IWL<643> A_IWL<642> A_IWL<641> A_IWL<640> A_IWL<895> A_IWL<894> A_IWL<893> A_IWL<892> A_IWL<891> A_IWL<890> A_IWL<889> A_IWL<888> A_IWL<887> A_IWL<886> A_IWL<885> A_IWL<884> A_IWL<883> A_IWL<882> A_IWL<881> A_IWL<880> A_IWL<879> A_IWL<878> A_IWL<877> A_IWL<876> A_IWL<875> A_IWL<874> A_IWL<873> A_IWL<872> A_IWL<871> A_IWL<870> A_IWL<869> A_IWL<868> A_IWL<867> A_IWL<866> A_IWL<865> A_IWL<864> A_IWL<863> A_IWL<862> A_IWL<861> A_IWL<860> A_IWL<859> A_IWL<858> A_IWL<857> A_IWL<856> A_IWL<855> A_IWL<854> A_IWL<853> A_IWL<852> A_IWL<851> A_IWL<850> A_IWL<849> A_IWL<848> A_IWL<847> A_IWL<846> A_IWL<845> A_IWL<844> A_IWL<843> A_IWL<842> A_IWL<841> A_IWL<840> A_IWL<839> A_IWL<838> A_IWL<837> A_IWL<836> A_IWL<835> A_IWL<834> A_IWL<833> A_IWL<832> A_IWL<831> A_IWL<830> A_IWL<829> A_IWL<828> A_IWL<827> A_IWL<826> A_IWL<825> A_IWL<824> A_IWL<823> A_IWL<822> A_IWL<821> A_IWL<820> A_IWL<819> A_IWL<818> A_IWL<817> A_IWL<816> A_IWL<815> A_IWL<814> A_IWL<813> A_IWL<812> A_IWL<811> A_IWL<810> A_IWL<809> A_IWL<808> A_IWL<807> A_IWL<806> A_IWL<805> A_IWL<804> A_IWL<803> A_IWL<802> A_IWL<801> A_IWL<800> A_IWL<799> A_IWL<798> A_IWL<797> A_IWL<796> A_IWL<795> A_IWL<794> A_IWL<793> A_IWL<792> A_IWL<791> A_IWL<790> A_IWL<789> A_IWL<788> A_IWL<787> A_IWL<786> A_IWL<785> A_IWL<784> A_IWL<783> A_IWL<782> A_IWL<781> A_IWL<780> A_IWL<779> A_IWL<778> A_IWL<777> A_IWL<776> A_IWL<775> A_IWL<774> A_IWL<773> A_IWL<772> A_IWL<771> A_IWL<770> A_IWL<769> A_IWL<768> VDD_CORE VSS / RM_IHPSG13_512x16_c2_1P_COLUMN_pcell_0 +XCOL<5> A_BLC<11> A_BLC<10> A_BLC_TOP<11> A_BLC_TOP<10> A_BLT<11> A_BLT<10> A_BLT_TOP<11> A_BLT_TOP<10> A_IWL<639> A_IWL<638> A_IWL<637> A_IWL<636> A_IWL<635> A_IWL<634> A_IWL<633> A_IWL<632> A_IWL<631> A_IWL<630> A_IWL<629> A_IWL<628> A_IWL<627> A_IWL<626> A_IWL<625> A_IWL<624> A_IWL<623> A_IWL<622> A_IWL<621> A_IWL<620> A_IWL<619> A_IWL<618> A_IWL<617> A_IWL<616> A_IWL<615> A_IWL<614> A_IWL<613> A_IWL<612> A_IWL<611> A_IWL<610> A_IWL<609> A_IWL<608> A_IWL<607> A_IWL<606> A_IWL<605> A_IWL<604> A_IWL<603> A_IWL<602> A_IWL<601> A_IWL<600> A_IWL<599> A_IWL<598> A_IWL<597> A_IWL<596> A_IWL<595> A_IWL<594> A_IWL<593> A_IWL<592> A_IWL<591> A_IWL<590> A_IWL<589> A_IWL<588> A_IWL<587> A_IWL<586> A_IWL<585> A_IWL<584> A_IWL<583> A_IWL<582> A_IWL<581> A_IWL<580> A_IWL<579> A_IWL<578> A_IWL<577> A_IWL<576> A_IWL<575> A_IWL<574> A_IWL<573> A_IWL<572> A_IWL<571> A_IWL<570> A_IWL<569> A_IWL<568> A_IWL<567> A_IWL<566> A_IWL<565> A_IWL<564> A_IWL<563> A_IWL<562> A_IWL<561> A_IWL<560> A_IWL<559> A_IWL<558> A_IWL<557> A_IWL<556> A_IWL<555> A_IWL<554> A_IWL<553> A_IWL<552> A_IWL<551> A_IWL<550> A_IWL<549> A_IWL<548> A_IWL<547> A_IWL<546> A_IWL<545> A_IWL<544> A_IWL<543> A_IWL<542> A_IWL<541> A_IWL<540> A_IWL<539> A_IWL<538> A_IWL<537> A_IWL<536> A_IWL<535> A_IWL<534> A_IWL<533> A_IWL<532> A_IWL<531> A_IWL<530> A_IWL<529> A_IWL<528> A_IWL<527> A_IWL<526> A_IWL<525> A_IWL<524> A_IWL<523> A_IWL<522> A_IWL<521> A_IWL<520> A_IWL<519> A_IWL<518> A_IWL<517> A_IWL<516> A_IWL<515> A_IWL<514> A_IWL<513> A_IWL<512> A_IWL<767> A_IWL<766> A_IWL<765> A_IWL<764> A_IWL<763> A_IWL<762> A_IWL<761> A_IWL<760> A_IWL<759> A_IWL<758> A_IWL<757> A_IWL<756> A_IWL<755> A_IWL<754> A_IWL<753> A_IWL<752> A_IWL<751> A_IWL<750> A_IWL<749> A_IWL<748> A_IWL<747> A_IWL<746> A_IWL<745> A_IWL<744> A_IWL<743> A_IWL<742> A_IWL<741> A_IWL<740> A_IWL<739> A_IWL<738> A_IWL<737> A_IWL<736> A_IWL<735> A_IWL<734> A_IWL<733> A_IWL<732> A_IWL<731> A_IWL<730> A_IWL<729> A_IWL<728> A_IWL<727> A_IWL<726> A_IWL<725> A_IWL<724> A_IWL<723> A_IWL<722> A_IWL<721> A_IWL<720> A_IWL<719> A_IWL<718> A_IWL<717> A_IWL<716> A_IWL<715> A_IWL<714> A_IWL<713> A_IWL<712> A_IWL<711> A_IWL<710> A_IWL<709> A_IWL<708> A_IWL<707> A_IWL<706> A_IWL<705> A_IWL<704> A_IWL<703> A_IWL<702> A_IWL<701> A_IWL<700> A_IWL<699> A_IWL<698> A_IWL<697> A_IWL<696> A_IWL<695> A_IWL<694> A_IWL<693> A_IWL<692> A_IWL<691> A_IWL<690> A_IWL<689> A_IWL<688> A_IWL<687> A_IWL<686> A_IWL<685> A_IWL<684> A_IWL<683> A_IWL<682> A_IWL<681> A_IWL<680> A_IWL<679> A_IWL<678> A_IWL<677> A_IWL<676> A_IWL<675> A_IWL<674> A_IWL<673> A_IWL<672> A_IWL<671> A_IWL<670> A_IWL<669> A_IWL<668> A_IWL<667> A_IWL<666> A_IWL<665> A_IWL<664> A_IWL<663> A_IWL<662> A_IWL<661> A_IWL<660> A_IWL<659> A_IWL<658> A_IWL<657> A_IWL<656> A_IWL<655> A_IWL<654> A_IWL<653> A_IWL<652> A_IWL<651> A_IWL<650> A_IWL<649> A_IWL<648> A_IWL<647> A_IWL<646> A_IWL<645> A_IWL<644> A_IWL<643> A_IWL<642> A_IWL<641> A_IWL<640> VDD_CORE VSS / RM_IHPSG13_512x16_c2_1P_COLUMN_pcell_0 +XCOL<4> A_BLC<9> A_BLC<8> A_BLC_TOP<9> A_BLC_TOP<8> A_BLT<9> A_BLT<8> A_BLT_TOP<9> A_BLT_TOP<8> A_IWL<511> A_IWL<510> A_IWL<509> A_IWL<508> A_IWL<507> A_IWL<506> A_IWL<505> A_IWL<504> A_IWL<503> A_IWL<502> A_IWL<501> A_IWL<500> A_IWL<499> A_IWL<498> A_IWL<497> A_IWL<496> A_IWL<495> A_IWL<494> A_IWL<493> A_IWL<492> A_IWL<491> A_IWL<490> A_IWL<489> A_IWL<488> A_IWL<487> A_IWL<486> A_IWL<485> A_IWL<484> A_IWL<483> A_IWL<482> A_IWL<481> A_IWL<480> A_IWL<479> A_IWL<478> A_IWL<477> A_IWL<476> A_IWL<475> A_IWL<474> A_IWL<473> A_IWL<472> A_IWL<471> A_IWL<470> A_IWL<469> A_IWL<468> A_IWL<467> A_IWL<466> A_IWL<465> A_IWL<464> A_IWL<463> A_IWL<462> A_IWL<461> A_IWL<460> A_IWL<459> A_IWL<458> A_IWL<457> A_IWL<456> A_IWL<455> A_IWL<454> A_IWL<453> A_IWL<452> A_IWL<451> A_IWL<450> A_IWL<449> A_IWL<448> A_IWL<447> A_IWL<446> A_IWL<445> A_IWL<444> A_IWL<443> A_IWL<442> A_IWL<441> A_IWL<440> A_IWL<439> A_IWL<438> A_IWL<437> A_IWL<436> A_IWL<435> A_IWL<434> A_IWL<433> A_IWL<432> A_IWL<431> A_IWL<430> A_IWL<429> A_IWL<428> A_IWL<427> A_IWL<426> A_IWL<425> A_IWL<424> A_IWL<423> A_IWL<422> A_IWL<421> A_IWL<420> A_IWL<419> A_IWL<418> A_IWL<417> A_IWL<416> A_IWL<415> A_IWL<414> A_IWL<413> A_IWL<412> A_IWL<411> A_IWL<410> A_IWL<409> A_IWL<408> A_IWL<407> A_IWL<406> A_IWL<405> A_IWL<404> A_IWL<403> A_IWL<402> A_IWL<401> A_IWL<400> A_IWL<399> A_IWL<398> A_IWL<397> A_IWL<396> A_IWL<395> A_IWL<394> A_IWL<393> A_IWL<392> A_IWL<391> A_IWL<390> A_IWL<389> A_IWL<388> A_IWL<387> A_IWL<386> A_IWL<385> A_IWL<384> A_IWL<639> A_IWL<638> A_IWL<637> A_IWL<636> A_IWL<635> A_IWL<634> A_IWL<633> A_IWL<632> A_IWL<631> A_IWL<630> A_IWL<629> A_IWL<628> A_IWL<627> A_IWL<626> A_IWL<625> A_IWL<624> A_IWL<623> A_IWL<622> A_IWL<621> A_IWL<620> A_IWL<619> A_IWL<618> A_IWL<617> A_IWL<616> A_IWL<615> A_IWL<614> A_IWL<613> A_IWL<612> A_IWL<611> A_IWL<610> A_IWL<609> A_IWL<608> A_IWL<607> A_IWL<606> A_IWL<605> A_IWL<604> A_IWL<603> A_IWL<602> A_IWL<601> A_IWL<600> A_IWL<599> A_IWL<598> A_IWL<597> A_IWL<596> A_IWL<595> A_IWL<594> A_IWL<593> A_IWL<592> A_IWL<591> A_IWL<590> A_IWL<589> A_IWL<588> A_IWL<587> A_IWL<586> A_IWL<585> A_IWL<584> A_IWL<583> A_IWL<582> A_IWL<581> A_IWL<580> A_IWL<579> A_IWL<578> A_IWL<577> A_IWL<576> A_IWL<575> A_IWL<574> A_IWL<573> A_IWL<572> A_IWL<571> A_IWL<570> A_IWL<569> A_IWL<568> A_IWL<567> A_IWL<566> A_IWL<565> A_IWL<564> A_IWL<563> A_IWL<562> A_IWL<561> A_IWL<560> A_IWL<559> A_IWL<558> A_IWL<557> A_IWL<556> A_IWL<555> A_IWL<554> A_IWL<553> A_IWL<552> A_IWL<551> A_IWL<550> A_IWL<549> A_IWL<548> A_IWL<547> A_IWL<546> A_IWL<545> A_IWL<544> A_IWL<543> A_IWL<542> A_IWL<541> A_IWL<540> A_IWL<539> A_IWL<538> A_IWL<537> A_IWL<536> A_IWL<535> A_IWL<534> A_IWL<533> A_IWL<532> A_IWL<531> A_IWL<530> A_IWL<529> A_IWL<528> A_IWL<527> A_IWL<526> A_IWL<525> A_IWL<524> A_IWL<523> A_IWL<522> A_IWL<521> A_IWL<520> A_IWL<519> A_IWL<518> A_IWL<517> A_IWL<516> A_IWL<515> A_IWL<514> A_IWL<513> A_IWL<512> VDD_CORE VSS / RM_IHPSG13_512x16_c2_1P_COLUMN_pcell_0 +XCOL<3> A_BLC<7> A_BLC<6> A_BLC_TOP<7> A_BLC_TOP<6> A_BLT<7> A_BLT<6> A_BLT_TOP<7> A_BLT_TOP<6> A_IWL<383> A_IWL<382> A_IWL<381> A_IWL<380> A_IWL<379> A_IWL<378> A_IWL<377> A_IWL<376> A_IWL<375> A_IWL<374> A_IWL<373> A_IWL<372> A_IWL<371> A_IWL<370> A_IWL<369> A_IWL<368> A_IWL<367> A_IWL<366> A_IWL<365> A_IWL<364> A_IWL<363> A_IWL<362> A_IWL<361> A_IWL<360> A_IWL<359> A_IWL<358> A_IWL<357> A_IWL<356> A_IWL<355> A_IWL<354> A_IWL<353> A_IWL<352> A_IWL<351> A_IWL<350> A_IWL<349> A_IWL<348> A_IWL<347> A_IWL<346> A_IWL<345> A_IWL<344> A_IWL<343> A_IWL<342> A_IWL<341> A_IWL<340> A_IWL<339> A_IWL<338> A_IWL<337> A_IWL<336> A_IWL<335> A_IWL<334> A_IWL<333> A_IWL<332> A_IWL<331> A_IWL<330> A_IWL<329> A_IWL<328> A_IWL<327> A_IWL<326> A_IWL<325> A_IWL<324> A_IWL<323> A_IWL<322> A_IWL<321> A_IWL<320> A_IWL<319> A_IWL<318> A_IWL<317> A_IWL<316> A_IWL<315> A_IWL<314> A_IWL<313> A_IWL<312> A_IWL<311> A_IWL<310> A_IWL<309> A_IWL<308> A_IWL<307> A_IWL<306> A_IWL<305> A_IWL<304> A_IWL<303> A_IWL<302> A_IWL<301> A_IWL<300> A_IWL<299> A_IWL<298> A_IWL<297> A_IWL<296> A_IWL<295> A_IWL<294> A_IWL<293> A_IWL<292> A_IWL<291> A_IWL<290> A_IWL<289> A_IWL<288> A_IWL<287> A_IWL<286> A_IWL<285> A_IWL<284> A_IWL<283> A_IWL<282> A_IWL<281> A_IWL<280> A_IWL<279> A_IWL<278> A_IWL<277> A_IWL<276> A_IWL<275> A_IWL<274> A_IWL<273> A_IWL<272> A_IWL<271> A_IWL<270> A_IWL<269> A_IWL<268> A_IWL<267> A_IWL<266> A_IWL<265> A_IWL<264> A_IWL<263> A_IWL<262> A_IWL<261> A_IWL<260> A_IWL<259> A_IWL<258> A_IWL<257> A_IWL<256> A_IWL<511> A_IWL<510> A_IWL<509> A_IWL<508> A_IWL<507> A_IWL<506> A_IWL<505> A_IWL<504> A_IWL<503> A_IWL<502> A_IWL<501> A_IWL<500> A_IWL<499> A_IWL<498> A_IWL<497> A_IWL<496> A_IWL<495> A_IWL<494> A_IWL<493> A_IWL<492> A_IWL<491> A_IWL<490> A_IWL<489> A_IWL<488> A_IWL<487> A_IWL<486> A_IWL<485> A_IWL<484> A_IWL<483> A_IWL<482> A_IWL<481> A_IWL<480> A_IWL<479> A_IWL<478> A_IWL<477> A_IWL<476> A_IWL<475> A_IWL<474> A_IWL<473> A_IWL<472> A_IWL<471> A_IWL<470> A_IWL<469> A_IWL<468> A_IWL<467> A_IWL<466> A_IWL<465> A_IWL<464> A_IWL<463> A_IWL<462> A_IWL<461> A_IWL<460> A_IWL<459> A_IWL<458> A_IWL<457> A_IWL<456> A_IWL<455> A_IWL<454> A_IWL<453> A_IWL<452> A_IWL<451> A_IWL<450> A_IWL<449> A_IWL<448> A_IWL<447> A_IWL<446> A_IWL<445> A_IWL<444> A_IWL<443> A_IWL<442> A_IWL<441> A_IWL<440> A_IWL<439> A_IWL<438> A_IWL<437> A_IWL<436> A_IWL<435> A_IWL<434> A_IWL<433> A_IWL<432> A_IWL<431> A_IWL<430> A_IWL<429> A_IWL<428> A_IWL<427> A_IWL<426> A_IWL<425> A_IWL<424> A_IWL<423> A_IWL<422> A_IWL<421> A_IWL<420> A_IWL<419> A_IWL<418> A_IWL<417> A_IWL<416> A_IWL<415> A_IWL<414> A_IWL<413> A_IWL<412> A_IWL<411> A_IWL<410> A_IWL<409> A_IWL<408> A_IWL<407> A_IWL<406> A_IWL<405> A_IWL<404> A_IWL<403> A_IWL<402> A_IWL<401> A_IWL<400> A_IWL<399> A_IWL<398> A_IWL<397> A_IWL<396> A_IWL<395> A_IWL<394> A_IWL<393> A_IWL<392> A_IWL<391> A_IWL<390> A_IWL<389> A_IWL<388> A_IWL<387> A_IWL<386> A_IWL<385> A_IWL<384> VDD_CORE VSS / RM_IHPSG13_512x16_c2_1P_COLUMN_pcell_0 +XCOL<2> A_BLC<5> A_BLC<4> A_BLC_TOP<5> A_BLC_TOP<4> A_BLT<5> A_BLT<4> A_BLT_TOP<5> A_BLT_TOP<4> A_IWL<255> A_IWL<254> A_IWL<253> A_IWL<252> A_IWL<251> A_IWL<250> A_IWL<249> A_IWL<248> A_IWL<247> A_IWL<246> A_IWL<245> A_IWL<244> A_IWL<243> A_IWL<242> A_IWL<241> A_IWL<240> A_IWL<239> A_IWL<238> A_IWL<237> A_IWL<236> A_IWL<235> A_IWL<234> A_IWL<233> A_IWL<232> A_IWL<231> A_IWL<230> A_IWL<229> A_IWL<228> A_IWL<227> A_IWL<226> A_IWL<225> A_IWL<224> A_IWL<223> A_IWL<222> A_IWL<221> A_IWL<220> A_IWL<219> A_IWL<218> A_IWL<217> A_IWL<216> A_IWL<215> A_IWL<214> A_IWL<213> A_IWL<212> A_IWL<211> A_IWL<210> A_IWL<209> A_IWL<208> A_IWL<207> A_IWL<206> A_IWL<205> A_IWL<204> A_IWL<203> A_IWL<202> A_IWL<201> A_IWL<200> A_IWL<199> A_IWL<198> A_IWL<197> A_IWL<196> A_IWL<195> A_IWL<194> A_IWL<193> A_IWL<192> A_IWL<191> A_IWL<190> A_IWL<189> A_IWL<188> A_IWL<187> A_IWL<186> A_IWL<185> A_IWL<184> A_IWL<183> A_IWL<182> A_IWL<181> A_IWL<180> A_IWL<179> A_IWL<178> A_IWL<177> A_IWL<176> A_IWL<175> A_IWL<174> A_IWL<173> A_IWL<172> A_IWL<171> A_IWL<170> A_IWL<169> A_IWL<168> A_IWL<167> A_IWL<166> A_IWL<165> A_IWL<164> A_IWL<163> A_IWL<162> A_IWL<161> A_IWL<160> A_IWL<159> A_IWL<158> A_IWL<157> A_IWL<156> A_IWL<155> A_IWL<154> A_IWL<153> A_IWL<152> A_IWL<151> A_IWL<150> A_IWL<149> A_IWL<148> A_IWL<147> A_IWL<146> A_IWL<145> A_IWL<144> A_IWL<143> A_IWL<142> A_IWL<141> A_IWL<140> A_IWL<139> A_IWL<138> A_IWL<137> A_IWL<136> A_IWL<135> A_IWL<134> A_IWL<133> A_IWL<132> A_IWL<131> A_IWL<130> A_IWL<129> A_IWL<128> A_IWL<383> A_IWL<382> A_IWL<381> A_IWL<380> A_IWL<379> A_IWL<378> A_IWL<377> A_IWL<376> A_IWL<375> A_IWL<374> A_IWL<373> A_IWL<372> A_IWL<371> A_IWL<370> A_IWL<369> A_IWL<368> A_IWL<367> A_IWL<366> A_IWL<365> A_IWL<364> A_IWL<363> A_IWL<362> A_IWL<361> A_IWL<360> A_IWL<359> A_IWL<358> A_IWL<357> A_IWL<356> A_IWL<355> A_IWL<354> A_IWL<353> A_IWL<352> A_IWL<351> A_IWL<350> A_IWL<349> A_IWL<348> A_IWL<347> A_IWL<346> A_IWL<345> A_IWL<344> A_IWL<343> A_IWL<342> A_IWL<341> A_IWL<340> A_IWL<339> A_IWL<338> A_IWL<337> A_IWL<336> A_IWL<335> A_IWL<334> A_IWL<333> A_IWL<332> A_IWL<331> A_IWL<330> A_IWL<329> A_IWL<328> A_IWL<327> A_IWL<326> A_IWL<325> A_IWL<324> A_IWL<323> A_IWL<322> A_IWL<321> A_IWL<320> A_IWL<319> A_IWL<318> A_IWL<317> A_IWL<316> A_IWL<315> A_IWL<314> A_IWL<313> A_IWL<312> A_IWL<311> A_IWL<310> A_IWL<309> A_IWL<308> A_IWL<307> A_IWL<306> A_IWL<305> A_IWL<304> A_IWL<303> A_IWL<302> A_IWL<301> A_IWL<300> A_IWL<299> A_IWL<298> A_IWL<297> A_IWL<296> A_IWL<295> A_IWL<294> A_IWL<293> A_IWL<292> A_IWL<291> A_IWL<290> A_IWL<289> A_IWL<288> A_IWL<287> A_IWL<286> A_IWL<285> A_IWL<284> A_IWL<283> A_IWL<282> A_IWL<281> A_IWL<280> A_IWL<279> A_IWL<278> A_IWL<277> A_IWL<276> A_IWL<275> A_IWL<274> A_IWL<273> A_IWL<272> A_IWL<271> A_IWL<270> A_IWL<269> A_IWL<268> A_IWL<267> A_IWL<266> A_IWL<265> A_IWL<264> A_IWL<263> A_IWL<262> A_IWL<261> A_IWL<260> A_IWL<259> A_IWL<258> A_IWL<257> A_IWL<256> VDD_CORE VSS / RM_IHPSG13_512x16_c2_1P_COLUMN_pcell_0 +XCOL<1> A_BLC<3> A_BLC<2> A_BLC_TOP<3> A_BLC_TOP<2> A_BLT<3> A_BLT<2> A_BLT_TOP<3> A_BLT_TOP<2> A_IWL<127> A_IWL<126> A_IWL<125> A_IWL<124> A_IWL<123> A_IWL<122> A_IWL<121> A_IWL<120> A_IWL<119> A_IWL<118> A_IWL<117> A_IWL<116> A_IWL<115> A_IWL<114> A_IWL<113> A_IWL<112> A_IWL<111> A_IWL<110> A_IWL<109> A_IWL<108> A_IWL<107> A_IWL<106> A_IWL<105> A_IWL<104> A_IWL<103> A_IWL<102> A_IWL<101> A_IWL<100> A_IWL<99> A_IWL<98> A_IWL<97> A_IWL<96> A_IWL<95> A_IWL<94> A_IWL<93> A_IWL<92> A_IWL<91> A_IWL<90> A_IWL<89> A_IWL<88> A_IWL<87> A_IWL<86> A_IWL<85> A_IWL<84> A_IWL<83> A_IWL<82> A_IWL<81> A_IWL<80> A_IWL<79> A_IWL<78> A_IWL<77> A_IWL<76> A_IWL<75> A_IWL<74> A_IWL<73> A_IWL<72> A_IWL<71> A_IWL<70> A_IWL<69> A_IWL<68> A_IWL<67> A_IWL<66> A_IWL<65> A_IWL<64> A_IWL<63> A_IWL<62> A_IWL<61> A_IWL<60> A_IWL<59> A_IWL<58> A_IWL<57> A_IWL<56> A_IWL<55> A_IWL<54> A_IWL<53> A_IWL<52> A_IWL<51> A_IWL<50> A_IWL<49> A_IWL<48> A_IWL<47> A_IWL<46> A_IWL<45> A_IWL<44> A_IWL<43> A_IWL<42> A_IWL<41> A_IWL<40> A_IWL<39> A_IWL<38> A_IWL<37> A_IWL<36> A_IWL<35> A_IWL<34> A_IWL<33> A_IWL<32> A_IWL<31> A_IWL<30> A_IWL<29> A_IWL<28> A_IWL<27> A_IWL<26> A_IWL<25> A_IWL<24> A_IWL<23> A_IWL<22> A_IWL<21> A_IWL<20> A_IWL<19> A_IWL<18> A_IWL<17> A_IWL<16> A_IWL<15> A_IWL<14> A_IWL<13> A_IWL<12> A_IWL<11> A_IWL<10> A_IWL<9> A_IWL<8> A_IWL<7> A_IWL<6> A_IWL<5> A_IWL<4> A_IWL<3> A_IWL<2> A_IWL<1> A_IWL<0> A_IWL<255> A_IWL<254> A_IWL<253> A_IWL<252> A_IWL<251> A_IWL<250> A_IWL<249> A_IWL<248> A_IWL<247> A_IWL<246> A_IWL<245> A_IWL<244> A_IWL<243> A_IWL<242> A_IWL<241> A_IWL<240> A_IWL<239> A_IWL<238> A_IWL<237> A_IWL<236> A_IWL<235> A_IWL<234> A_IWL<233> A_IWL<232> A_IWL<231> A_IWL<230> A_IWL<229> A_IWL<228> A_IWL<227> A_IWL<226> A_IWL<225> A_IWL<224> A_IWL<223> A_IWL<222> A_IWL<221> A_IWL<220> A_IWL<219> A_IWL<218> A_IWL<217> A_IWL<216> A_IWL<215> A_IWL<214> A_IWL<213> A_IWL<212> A_IWL<211> A_IWL<210> A_IWL<209> A_IWL<208> A_IWL<207> A_IWL<206> A_IWL<205> A_IWL<204> A_IWL<203> A_IWL<202> A_IWL<201> A_IWL<200> A_IWL<199> A_IWL<198> A_IWL<197> A_IWL<196> A_IWL<195> A_IWL<194> A_IWL<193> A_IWL<192> A_IWL<191> A_IWL<190> A_IWL<189> A_IWL<188> A_IWL<187> A_IWL<186> A_IWL<185> A_IWL<184> A_IWL<183> A_IWL<182> A_IWL<181> A_IWL<180> A_IWL<179> A_IWL<178> A_IWL<177> A_IWL<176> A_IWL<175> A_IWL<174> A_IWL<173> A_IWL<172> A_IWL<171> A_IWL<170> A_IWL<169> A_IWL<168> A_IWL<167> A_IWL<166> A_IWL<165> A_IWL<164> A_IWL<163> A_IWL<162> A_IWL<161> A_IWL<160> A_IWL<159> A_IWL<158> A_IWL<157> A_IWL<156> A_IWL<155> A_IWL<154> A_IWL<153> A_IWL<152> A_IWL<151> A_IWL<150> A_IWL<149> A_IWL<148> A_IWL<147> A_IWL<146> A_IWL<145> A_IWL<144> A_IWL<143> A_IWL<142> A_IWL<141> A_IWL<140> A_IWL<139> A_IWL<138> A_IWL<137> A_IWL<136> A_IWL<135> A_IWL<134> A_IWL<133> A_IWL<132> A_IWL<131> A_IWL<130> A_IWL<129> A_IWL<128> VDD_CORE VSS / RM_IHPSG13_512x16_c2_1P_COLUMN_pcell_0 +XCOL<0> A_BLC<1> A_BLC<0> A_BLC_TOP<1> A_BLC_TOP<0> A_BLT<1> A_BLT<0> A_BLT_TOP<1> A_BLT_TOP<0> A_WL<127> A_WL<126> A_WL<125> A_WL<124> A_WL<123> A_WL<122> A_WL<121> A_WL<120> A_WL<119> A_WL<118> A_WL<117> A_WL<116> A_WL<115> A_WL<114> A_WL<113> A_WL<112> A_WL<111> A_WL<110> A_WL<109> A_WL<108> A_WL<107> A_WL<106> A_WL<105> A_WL<104> A_WL<103> A_WL<102> A_WL<101> A_WL<100> A_WL<99> A_WL<98> A_WL<97> A_WL<96> A_WL<95> A_WL<94> A_WL<93> A_WL<92> A_WL<91> A_WL<90> A_WL<89> A_WL<88> A_WL<87> A_WL<86> A_WL<85> A_WL<84> A_WL<83> A_WL<82> A_WL<81> A_WL<80> A_WL<79> A_WL<78> A_WL<77> A_WL<76> A_WL<75> A_WL<74> A_WL<73> A_WL<72> A_WL<71> A_WL<70> A_WL<69> A_WL<68> A_WL<67> A_WL<66> A_WL<65> A_WL<64> A_WL<63> A_WL<62> A_WL<61> A_WL<60> A_WL<59> A_WL<58> A_WL<57> A_WL<56> A_WL<55> A_WL<54> A_WL<53> A_WL<52> A_WL<51> A_WL<50> A_WL<49> A_WL<48> A_WL<47> A_WL<46> A_WL<45> A_WL<44> A_WL<43> A_WL<42> A_WL<41> A_WL<40> A_WL<39> A_WL<38> A_WL<37> A_WL<36> A_WL<35> A_WL<34> A_WL<33> A_WL<32> A_WL<31> A_WL<30> A_WL<29> A_WL<28> A_WL<27> A_WL<26> A_WL<25> A_WL<24> A_WL<23> A_WL<22> A_WL<21> A_WL<20> A_WL<19> A_WL<18> A_WL<17> A_WL<16> A_WL<15> A_WL<14> A_WL<13> A_WL<12> A_WL<11> A_WL<10> A_WL<9> A_WL<8> A_WL<7> A_WL<6> A_WL<5> A_WL<4> A_WL<3> A_WL<2> A_WL<1> A_WL<0> A_IWL<127> A_IWL<126> A_IWL<125> A_IWL<124> A_IWL<123> A_IWL<122> A_IWL<121> A_IWL<120> A_IWL<119> A_IWL<118> A_IWL<117> A_IWL<116> A_IWL<115> A_IWL<114> A_IWL<113> A_IWL<112> A_IWL<111> A_IWL<110> A_IWL<109> A_IWL<108> A_IWL<107> A_IWL<106> A_IWL<105> A_IWL<104> A_IWL<103> A_IWL<102> A_IWL<101> A_IWL<100> A_IWL<99> A_IWL<98> A_IWL<97> A_IWL<96> A_IWL<95> A_IWL<94> A_IWL<93> A_IWL<92> A_IWL<91> A_IWL<90> A_IWL<89> A_IWL<88> A_IWL<87> A_IWL<86> A_IWL<85> A_IWL<84> A_IWL<83> A_IWL<82> A_IWL<81> A_IWL<80> A_IWL<79> A_IWL<78> A_IWL<77> A_IWL<76> A_IWL<75> A_IWL<74> A_IWL<73> A_IWL<72> A_IWL<71> A_IWL<70> A_IWL<69> A_IWL<68> A_IWL<67> A_IWL<66> A_IWL<65> A_IWL<64> A_IWL<63> A_IWL<62> A_IWL<61> A_IWL<60> A_IWL<59> A_IWL<58> A_IWL<57> A_IWL<56> A_IWL<55> A_IWL<54> A_IWL<53> A_IWL<52> A_IWL<51> A_IWL<50> A_IWL<49> A_IWL<48> A_IWL<47> A_IWL<46> A_IWL<45> A_IWL<44> A_IWL<43> A_IWL<42> A_IWL<41> A_IWL<40> A_IWL<39> A_IWL<38> A_IWL<37> A_IWL<36> A_IWL<35> A_IWL<34> A_IWL<33> A_IWL<32> A_IWL<31> A_IWL<30> A_IWL<29> A_IWL<28> A_IWL<27> A_IWL<26> A_IWL<25> A_IWL<24> A_IWL<23> A_IWL<22> A_IWL<21> A_IWL<20> A_IWL<19> A_IWL<18> A_IWL<17> A_IWL<16> A_IWL<15> A_IWL<14> A_IWL<13> A_IWL<12> A_IWL<11> A_IWL<10> A_IWL<9> A_IWL<8> A_IWL<7> A_IWL<6> A_IWL<5> A_IWL<4> A_IWL<3> A_IWL<2> A_IWL<1> A_IWL<0> VDD_CORE VSS / RM_IHPSG13_512x16_c2_1P_COLUMN_pcell_0 +.ENDS + + + + +.SUBCKT RM_IHPSG13_512x16_c2_1P_DLY_pcell_2 A Z VDD VSS + XIDL<2> D<7> Z VDD VSS / RSC_IHPSG13_CDLYX1 + XIDL<1> D<6> D<7> VDD VSS / RSC_IHPSG13_CDLYX1 + XIDM<6> D<5> D<6> VDD VSS / RSC_IHPSG13_CDLYX1_DUMMY + XIDM<5> D<4> D<5> VDD VSS / RSC_IHPSG13_CDLYX1_DUMMY + XIDM<4> D<3> D<4> VDD VSS / RSC_IHPSG13_CDLYX1_DUMMY + XIDM<3> D<2> D<3> VDD VSS / RSC_IHPSG13_CDLYX1_DUMMY + XIDM<2> D<1> D<2> VDD VSS / RSC_IHPSG13_CDLYX1_DUMMY + XIDM<1> A D<1> VDD VSS / RSC_IHPSG13_CDLYX1_DUMMY +.ENDS + + +.SUBCKT RM_IHPSG13_512x16_c2_1P_DLY_pcell_3 A Z VDD VSS + XIDL<2> D<7> Z VDD VSS / RSC_IHPSG13_CDLYX1 + XIDL<1> D<6> D<7> VDD VSS / RSC_IHPSG13_CDLYX1 + XIDM<6> D<5> D<6> VDD VSS / RSC_IHPSG13_CDLYX1_DUMMY + XIDM<5> D<4> D<5> VDD VSS / RSC_IHPSG13_CDLYX1_DUMMY + XIDM<4> D<3> D<4> VDD VSS / RSC_IHPSG13_CDLYX1_DUMMY + XIDM<3> D<2> D<3> VDD VSS / RSC_IHPSG13_CDLYX1_DUMMY + XIDM<2> D<1> D<2> VDD VSS / RSC_IHPSG13_CDLYX1_DUMMY + XIDM<1> A D<1> VDD VSS / RSC_IHPSG13_CDLYX1_DUMMY +.ENDS + + + +.SUBCKT RM_IHPSG13_1P_512x16_c2_bm_bist A_ADDR<8> A_ADDR<7> A_ADDR<6> A_ADDR<5> A_ADDR<4> A_ADDR<3> A_ADDR<2> A_ADDR<1> A_ADDR<0> A_BIST_ADDR<8> A_BIST_ADDR<7> A_BIST_ADDR<6> A_BIST_ADDR<5> A_BIST_ADDR<4> A_BIST_ADDR<3> A_BIST_ADDR<2> A_BIST_ADDR<1> A_BIST_ADDR<0> A_BIST_BM<15> A_BIST_BM<14> A_BIST_BM<13> A_BIST_BM<12> A_BIST_BM<11> A_BIST_BM<10> A_BIST_BM<9> A_BIST_BM<8> A_BIST_BM<7> A_BIST_BM<6> A_BIST_BM<5> A_BIST_BM<4> A_BIST_BM<3> A_BIST_BM<2> A_BIST_BM<1> A_BIST_BM<0> A_BIST_CLK A_BIST_DIN<15> A_BIST_DIN<14> A_BIST_DIN<13> A_BIST_DIN<12> A_BIST_DIN<11> A_BIST_DIN<10> A_BIST_DIN<9> A_BIST_DIN<8> A_BIST_DIN<7> A_BIST_DIN<6> A_BIST_DIN<5> A_BIST_DIN<4> A_BIST_DIN<3> A_BIST_DIN<2> A_BIST_DIN<1> A_BIST_DIN<0> A_BIST_EN A_BIST_MEN A_BIST_REN A_BIST_WEN A_BM<15> A_BM<14> A_BM<13> A_BM<12> A_BM<11> A_BM<10> A_BM<9> A_BM<8> A_BM<7> A_BM<6> A_BM<5> A_BM<4> A_BM<3> A_BM<2> A_BM<1> A_BM<0> A_CLK A_DIN<15> A_DIN<14> A_DIN<13> A_DIN<12> A_DIN<11> A_DIN<10> A_DIN<9> A_DIN<8> A_DIN<7> A_DIN<6> A_DIN<5> A_DIN<4> A_DIN<3> A_DIN<2> A_DIN<1> A_DIN<0> A_DLY A_DOUT<15> A_DOUT<14> A_DOUT<13> A_DOUT<12> A_DOUT<11> A_DOUT<10> A_DOUT<9> A_DOUT<8> A_DOUT<7> A_DOUT<6> A_DOUT<5> A_DOUT<4> A_DOUT<3> A_DOUT<2> A_DOUT<1> A_DOUT<0> A_MEN A_REN A_WEN VDD! VDDARRAY! VSS! + + +XRAM<1> a_blc_r<31> a_blc_r<30> a_blc_r<29> a_blc_r<28> a_blc_r<27> a_blc_r<26> a_blc_r<25> a_blc_r<24> a_blc_r<23> a_blc_r<22> a_blc_r<21> a_blc_r<20> a_blc_r<19> a_blc_r<18> a_blc_r<17> a_blc_r<16> a_blc_r<15> a_blc_r<14> a_blc_r<13> a_blc_r<12> a_blc_r<11> a_blc_r<10> a_blc_r<9> a_blc_r<8> a_blc_r<7> a_blc_r<6> a_blc_r<5> a_blc_r<4> a_blc_r<3> a_blc_r<2> a_blc_r<1> a_blc_r<0> a_blt_r<31> a_blt_r<30> a_blt_r<29> a_blt_r<28> a_blt_r<27> a_blt_r<26> a_blt_r<25> a_blt_r<24> a_blt_r<23> a_blt_r<22> a_blt_r<21> a_blt_r<20> a_blt_r<19> a_blt_r<18> a_blt_r<17> a_blt_r<16> a_blt_r<15> a_blt_r<14> a_blt_r<13> a_blt_r<12> a_blt_r<11> a_blt_r<10> a_blt_r<9> a_blt_r<8> a_blt_r<7> a_blt_r<6> a_blt_r<5> a_blt_r<4> a_blt_r<3> a_blt_r<2> a_blt_r<1> a_blt_r<0> a_wl_r<127> a_wl_r<126> a_wl_r<125> a_wl_r<124> a_wl_r<123> a_wl_r<122> a_wl_r<121> a_wl_r<120> a_wl_r<119> a_wl_r<118> a_wl_r<117> a_wl_r<116> a_wl_r<115> a_wl_r<114> a_wl_r<113> a_wl_r<112> a_wl_r<111> a_wl_r<110> a_wl_r<109> a_wl_r<108> a_wl_r<107> a_wl_r<106> a_wl_r<105> a_wl_r<104> a_wl_r<103> a_wl_r<102> a_wl_r<101> a_wl_r<100> a_wl_r<99> a_wl_r<98> a_wl_r<97> a_wl_r<96> a_wl_r<95> a_wl_r<94> a_wl_r<93> a_wl_r<92> a_wl_r<91> a_wl_r<90> a_wl_r<89> a_wl_r<88> a_wl_r<87> a_wl_r<86> a_wl_r<85> a_wl_r<84> a_wl_r<83> a_wl_r<82> a_wl_r<81> a_wl_r<80> a_wl_r<79> a_wl_r<78> a_wl_r<77> a_wl_r<76> a_wl_r<75> a_wl_r<74> a_wl_r<73> a_wl_r<72> a_wl_r<71> a_wl_r<70> a_wl_r<69> a_wl_r<68> a_wl_r<67> a_wl_r<66> a_wl_r<65> a_wl_r<64> a_wl_r<63> a_wl_r<62> a_wl_r<61> a_wl_r<60> a_wl_r<59> a_wl_r<58> a_wl_r<57> a_wl_r<56> a_wl_r<55> a_wl_r<54> a_wl_r<53> a_wl_r<52> a_wl_r<51> a_wl_r<50> a_wl_r<49> a_wl_r<48> a_wl_r<47> a_wl_r<46> a_wl_r<45> a_wl_r<44> a_wl_r<43> a_wl_r<42> a_wl_r<41> a_wl_r<40> a_wl_r<39> a_wl_r<38> a_wl_r<37> a_wl_r<36> a_wl_r<35> a_wl_r<34> a_wl_r<33> a_wl_r<32> a_wl_r<31> a_wl_r<30> a_wl_r<29> a_wl_r<28> a_wl_r<27> a_wl_r<26> a_wl_r<25> a_wl_r<24> a_wl_r<23> a_wl_r<22> a_wl_r<21> a_wl_r<20> a_wl_r<19> a_wl_r<18> a_wl_r<17> a_wl_r<16> a_wl_r<15> a_wl_r<14> a_wl_r<13> a_wl_r<12> a_wl_r<11> a_wl_r<10> a_wl_r<9> a_wl_r<8> a_wl_r<7> a_wl_r<6> a_wl_r<5> a_wl_r<4> a_wl_r<3> a_wl_r<2> a_wl_r<1> a_wl_r<0> VDDARRAY! VSS! / RM_IHPSG13_512x16_c2_1P_MATRIX_pcell_1 +XRAM<0> a_blc_l<31> a_blc_l<30> a_blc_l<29> a_blc_l<28> a_blc_l<27> a_blc_l<26> a_blc_l<25> a_blc_l<24> a_blc_l<23> a_blc_l<22> a_blc_l<21> a_blc_l<20> a_blc_l<19> a_blc_l<18> a_blc_l<17> a_blc_l<16> a_blc_l<15> a_blc_l<14> a_blc_l<13> a_blc_l<12> a_blc_l<11> a_blc_l<10> a_blc_l<9> a_blc_l<8> a_blc_l<7> a_blc_l<6> a_blc_l<5> a_blc_l<4> a_blc_l<3> a_blc_l<2> a_blc_l<1> a_blc_l<0> a_blt_l<31> a_blt_l<30> a_blt_l<29> a_blt_l<28> a_blt_l<27> a_blt_l<26> a_blt_l<25> a_blt_l<24> a_blt_l<23> a_blt_l<22> a_blt_l<21> a_blt_l<20> a_blt_l<19> a_blt_l<18> a_blt_l<17> a_blt_l<16> a_blt_l<15> a_blt_l<14> a_blt_l<13> a_blt_l<12> a_blt_l<11> a_blt_l<10> a_blt_l<9> a_blt_l<8> a_blt_l<7> a_blt_l<6> a_blt_l<5> a_blt_l<4> a_blt_l<3> a_blt_l<2> a_blt_l<1> a_blt_l<0> a_wl_l<127> a_wl_l<126> a_wl_l<125> a_wl_l<124> a_wl_l<123> a_wl_l<122> a_wl_l<121> a_wl_l<120> a_wl_l<119> a_wl_l<118> a_wl_l<117> a_wl_l<116> a_wl_l<115> a_wl_l<114> a_wl_l<113> a_wl_l<112> a_wl_l<111> a_wl_l<110> a_wl_l<109> a_wl_l<108> a_wl_l<107> a_wl_l<106> a_wl_l<105> a_wl_l<104> a_wl_l<103> a_wl_l<102> a_wl_l<101> a_wl_l<100> a_wl_l<99> a_wl_l<98> a_wl_l<97> a_wl_l<96> a_wl_l<95> a_wl_l<94> a_wl_l<93> a_wl_l<92> a_wl_l<91> a_wl_l<90> a_wl_l<89> a_wl_l<88> a_wl_l<87> a_wl_l<86> a_wl_l<85> a_wl_l<84> a_wl_l<83> a_wl_l<82> a_wl_l<81> a_wl_l<80> a_wl_l<79> a_wl_l<78> a_wl_l<77> a_wl_l<76> a_wl_l<75> a_wl_l<74> a_wl_l<73> a_wl_l<72> a_wl_l<71> a_wl_l<70> a_wl_l<69> a_wl_l<68> a_wl_l<67> a_wl_l<66> a_wl_l<65> a_wl_l<64> a_wl_l<63> a_wl_l<62> a_wl_l<61> a_wl_l<60> a_wl_l<59> a_wl_l<58> a_wl_l<57> a_wl_l<56> a_wl_l<55> a_wl_l<54> a_wl_l<53> a_wl_l<52> a_wl_l<51> a_wl_l<50> a_wl_l<49> a_wl_l<48> a_wl_l<47> a_wl_l<46> a_wl_l<45> a_wl_l<44> a_wl_l<43> a_wl_l<42> a_wl_l<41> a_wl_l<40> a_wl_l<39> a_wl_l<38> a_wl_l<37> a_wl_l<36> a_wl_l<35> a_wl_l<34> a_wl_l<33> a_wl_l<32> a_wl_l<31> a_wl_l<30> a_wl_l<29> a_wl_l<28> a_wl_l<27> a_wl_l<26> a_wl_l<25> a_wl_l<24> a_wl_l<23> a_wl_l<22> a_wl_l<21> a_wl_l<20> a_wl_l<19> a_wl_l<18> a_wl_l<17> a_wl_l<16> a_wl_l<15> a_wl_l<14> a_wl_l<13> a_wl_l<12> a_wl_l<11> a_wl_l<10> a_wl_l<9> a_wl_l<8> a_wl_l<7> a_wl_l<6> a_wl_l<5> a_wl_l<4> a_wl_l<3> a_wl_l<2> a_wl_l<1> a_wl_l<0> VDDARRAY! VSS! / RM_IHPSG13_512x16_c2_1P_MATRIX_pcell_1 + + +XA_COLDRV<1> a_addr_col<1> a_addr_col<0> a_addr_col_r<1> a_addr_col_r<0> a_addr_dec<7> a_addr_dec<6> a_addr_dec<5> a_addr_dec<4> a_addr_dec<3> a_addr_dec<2> a_addr_dec<1> a_addr_dec<0> a_addr_dec_r<7> a_addr_dec_r<6> a_addr_dec_r<5> a_addr_dec_r<4> a_addr_dec_r<3> a_addr_dec_r<2> a_addr_dec_r<1> a_addr_dec_r<0> a_dclk a_dclk_p_r<0> a_rclk a_rclk_p_r<0> a_wclk a_wclk_p_r<0> VDD! VSS! / RM_IHPSG13_512x16_c2_1P_COLDRV13X4 +XA_COLDRV<0> a_addr_col<1> a_addr_col<0> a_addr_col_l<1> a_addr_col_l<0> a_addr_dec<7> a_addr_dec<6> a_addr_dec<5> a_addr_dec<4> a_addr_dec<3> a_addr_dec<2> a_addr_dec<1> a_addr_dec<0> a_addr_dec_l<7> a_addr_dec_l<6> a_addr_dec_l<5> a_addr_dec_l<4> a_addr_dec_l<3> a_addr_dec_l<2> a_addr_dec_l<1> a_addr_dec_l<0> a_dclk a_dclk_p_l<0> a_rclk a_rclk_p_l<0> a_wclk a_wclk_p_l<0> VDD! VSS! / RM_IHPSG13_512x16_c2_1P_COLDRV13X4 + + +XA_WLDRV<15> a_wi<127> a_wi<126> a_wi<125> a_wi<124> a_wi<123> a_wi<122> a_wi<121> a_wi<120> a_wi<119> a_wi<118> a_wi<117> a_wi<116> a_wi<115> a_wi<114> a_wi<113> a_wi<112> a_wl_r<127> a_wl_r<126> a_wl_r<125> a_wl_r<124> a_wl_r<123> a_wl_r<122> a_wl_r<121> a_wl_r<120> a_wl_r<119> a_wl_r<118> a_wl_r<117> a_wl_r<116> a_wl_r<115> a_wl_r<114> a_wl_r<113> a_wl_r<112> VDD! VSS! / RM_IHPSG13_512x16_c2_1P_WLDRV16X4 +XA_WLDRV<14> a_wi<111> a_wi<110> a_wi<109> a_wi<108> a_wi<107> a_wi<106> a_wi<105> a_wi<104> a_wi<103> a_wi<102> a_wi<101> a_wi<100> a_wi<99> a_wi<98> a_wi<97> a_wi<96> a_wl_r<111> a_wl_r<110> a_wl_r<109> a_wl_r<108> a_wl_r<107> a_wl_r<106> a_wl_r<105> a_wl_r<104> a_wl_r<103> a_wl_r<102> a_wl_r<101> a_wl_r<100> a_wl_r<99> a_wl_r<98> a_wl_r<97> a_wl_r<96> VDD! VSS! / RM_IHPSG13_512x16_c2_1P_WLDRV16X4 +XA_WLDRV<13> a_wi<95> a_wi<94> a_wi<93> a_wi<92> a_wi<91> a_wi<90> a_wi<89> a_wi<88> a_wi<87> a_wi<86> a_wi<85> a_wi<84> a_wi<83> a_wi<82> a_wi<81> a_wi<80> a_wl_r<95> a_wl_r<94> a_wl_r<93> a_wl_r<92> a_wl_r<91> a_wl_r<90> a_wl_r<89> a_wl_r<88> a_wl_r<87> a_wl_r<86> a_wl_r<85> a_wl_r<84> a_wl_r<83> a_wl_r<82> a_wl_r<81> a_wl_r<80> VDD! VSS! / RM_IHPSG13_512x16_c2_1P_WLDRV16X4 +XA_WLDRV<12> a_wi<79> a_wi<78> a_wi<77> a_wi<76> a_wi<75> a_wi<74> a_wi<73> a_wi<72> a_wi<71> a_wi<70> a_wi<69> a_wi<68> a_wi<67> a_wi<66> a_wi<65> a_wi<64> a_wl_r<79> a_wl_r<78> a_wl_r<77> a_wl_r<76> a_wl_r<75> a_wl_r<74> a_wl_r<73> a_wl_r<72> a_wl_r<71> a_wl_r<70> a_wl_r<69> a_wl_r<68> a_wl_r<67> a_wl_r<66> a_wl_r<65> a_wl_r<64> VDD! VSS! / RM_IHPSG13_512x16_c2_1P_WLDRV16X4 +XA_WLDRV<11> a_wi<63> a_wi<62> a_wi<61> a_wi<60> a_wi<59> a_wi<58> a_wi<57> a_wi<56> a_wi<55> a_wi<54> a_wi<53> a_wi<52> a_wi<51> a_wi<50> a_wi<49> a_wi<48> a_wl_r<63> a_wl_r<62> a_wl_r<61> a_wl_r<60> a_wl_r<59> a_wl_r<58> a_wl_r<57> a_wl_r<56> a_wl_r<55> a_wl_r<54> a_wl_r<53> a_wl_r<52> a_wl_r<51> a_wl_r<50> a_wl_r<49> a_wl_r<48> VDD! VSS! / RM_IHPSG13_512x16_c2_1P_WLDRV16X4 +XA_WLDRV<10> a_wi<47> a_wi<46> a_wi<45> a_wi<44> a_wi<43> a_wi<42> a_wi<41> a_wi<40> a_wi<39> a_wi<38> a_wi<37> a_wi<36> a_wi<35> a_wi<34> a_wi<33> a_wi<32> a_wl_r<47> a_wl_r<46> a_wl_r<45> a_wl_r<44> a_wl_r<43> a_wl_r<42> a_wl_r<41> a_wl_r<40> a_wl_r<39> a_wl_r<38> a_wl_r<37> a_wl_r<36> a_wl_r<35> a_wl_r<34> a_wl_r<33> a_wl_r<32> VDD! VSS! / RM_IHPSG13_512x16_c2_1P_WLDRV16X4 +XA_WLDRV<9> a_wi<31> a_wi<30> a_wi<29> a_wi<28> a_wi<27> a_wi<26> a_wi<25> a_wi<24> a_wi<23> a_wi<22> a_wi<21> a_wi<20> a_wi<19> a_wi<18> a_wi<17> a_wi<16> a_wl_r<31> a_wl_r<30> a_wl_r<29> a_wl_r<28> a_wl_r<27> a_wl_r<26> a_wl_r<25> a_wl_r<24> a_wl_r<23> a_wl_r<22> a_wl_r<21> a_wl_r<20> a_wl_r<19> a_wl_r<18> a_wl_r<17> a_wl_r<16> VDD! VSS! / RM_IHPSG13_512x16_c2_1P_WLDRV16X4 +XA_WLDRV<8> a_wi<15> a_wi<14> a_wi<13> a_wi<12> a_wi<11> a_wi<10> a_wi<9> a_wi<8> a_wi<7> a_wi<6> a_wi<5> a_wi<4> a_wi<3> a_wi<2> a_wi<1> a_wi<0> a_wl_r<15> a_wl_r<14> a_wl_r<13> a_wl_r<12> a_wl_r<11> a_wl_r<10> a_wl_r<9> a_wl_r<8> a_wl_r<7> a_wl_r<6> a_wl_r<5> a_wl_r<4> a_wl_r<3> a_wl_r<2> a_wl_r<1> a_wl_r<0> VDD! VSS! / RM_IHPSG13_512x16_c2_1P_WLDRV16X4 +XA_WLDRV<7> a_wi<127> a_wi<126> a_wi<125> a_wi<124> a_wi<123> a_wi<122> a_wi<121> a_wi<120> a_wi<119> a_wi<118> a_wi<117> a_wi<116> a_wi<115> a_wi<114> a_wi<113> a_wi<112> a_wl_l<127> a_wl_l<126> a_wl_l<125> a_wl_l<124> a_wl_l<123> a_wl_l<122> a_wl_l<121> a_wl_l<120> a_wl_l<119> a_wl_l<118> a_wl_l<117> a_wl_l<116> a_wl_l<115> a_wl_l<114> a_wl_l<113> a_wl_l<112> VDD! VSS! / RM_IHPSG13_512x16_c2_1P_WLDRV16X4 +XA_WLDRV<6> a_wi<111> a_wi<110> a_wi<109> a_wi<108> a_wi<107> a_wi<106> a_wi<105> a_wi<104> a_wi<103> a_wi<102> a_wi<101> a_wi<100> a_wi<99> a_wi<98> a_wi<97> a_wi<96> a_wl_l<111> a_wl_l<110> a_wl_l<109> a_wl_l<108> a_wl_l<107> a_wl_l<106> a_wl_l<105> a_wl_l<104> a_wl_l<103> a_wl_l<102> a_wl_l<101> a_wl_l<100> a_wl_l<99> a_wl_l<98> a_wl_l<97> a_wl_l<96> VDD! VSS! / RM_IHPSG13_512x16_c2_1P_WLDRV16X4 +XA_WLDRV<5> a_wi<95> a_wi<94> a_wi<93> a_wi<92> a_wi<91> a_wi<90> a_wi<89> a_wi<88> a_wi<87> a_wi<86> a_wi<85> a_wi<84> a_wi<83> a_wi<82> a_wi<81> a_wi<80> a_wl_l<95> a_wl_l<94> a_wl_l<93> a_wl_l<92> a_wl_l<91> a_wl_l<90> a_wl_l<89> a_wl_l<88> a_wl_l<87> a_wl_l<86> a_wl_l<85> a_wl_l<84> a_wl_l<83> a_wl_l<82> a_wl_l<81> a_wl_l<80> VDD! VSS! / RM_IHPSG13_512x16_c2_1P_WLDRV16X4 +XA_WLDRV<4> a_wi<79> a_wi<78> a_wi<77> a_wi<76> a_wi<75> a_wi<74> a_wi<73> a_wi<72> a_wi<71> a_wi<70> a_wi<69> a_wi<68> a_wi<67> a_wi<66> a_wi<65> a_wi<64> a_wl_l<79> a_wl_l<78> a_wl_l<77> a_wl_l<76> a_wl_l<75> a_wl_l<74> a_wl_l<73> a_wl_l<72> a_wl_l<71> a_wl_l<70> a_wl_l<69> a_wl_l<68> a_wl_l<67> a_wl_l<66> a_wl_l<65> a_wl_l<64> VDD! VSS! / RM_IHPSG13_512x16_c2_1P_WLDRV16X4 +XA_WLDRV<3> a_wi<63> a_wi<62> a_wi<61> a_wi<60> a_wi<59> a_wi<58> a_wi<57> a_wi<56> a_wi<55> a_wi<54> a_wi<53> a_wi<52> a_wi<51> a_wi<50> a_wi<49> a_wi<48> a_wl_l<63> a_wl_l<62> a_wl_l<61> a_wl_l<60> a_wl_l<59> a_wl_l<58> a_wl_l<57> a_wl_l<56> a_wl_l<55> a_wl_l<54> a_wl_l<53> a_wl_l<52> a_wl_l<51> a_wl_l<50> a_wl_l<49> a_wl_l<48> VDD! VSS! / RM_IHPSG13_512x16_c2_1P_WLDRV16X4 +XA_WLDRV<2> a_wi<47> a_wi<46> a_wi<45> a_wi<44> a_wi<43> a_wi<42> a_wi<41> a_wi<40> a_wi<39> a_wi<38> a_wi<37> a_wi<36> a_wi<35> a_wi<34> a_wi<33> a_wi<32> a_wl_l<47> a_wl_l<46> a_wl_l<45> a_wl_l<44> a_wl_l<43> a_wl_l<42> a_wl_l<41> a_wl_l<40> a_wl_l<39> a_wl_l<38> a_wl_l<37> a_wl_l<36> a_wl_l<35> a_wl_l<34> a_wl_l<33> a_wl_l<32> VDD! VSS! / RM_IHPSG13_512x16_c2_1P_WLDRV16X4 +XA_WLDRV<1> a_wi<31> a_wi<30> a_wi<29> a_wi<28> a_wi<27> a_wi<26> a_wi<25> a_wi<24> a_wi<23> a_wi<22> a_wi<21> a_wi<20> a_wi<19> a_wi<18> a_wi<17> a_wi<16> a_wl_l<31> a_wl_l<30> a_wl_l<29> a_wl_l<28> a_wl_l<27> a_wl_l<26> a_wl_l<25> a_wl_l<24> a_wl_l<23> a_wl_l<22> a_wl_l<21> a_wl_l<20> a_wl_l<19> a_wl_l<18> a_wl_l<17> a_wl_l<16> VDD! VSS! / RM_IHPSG13_512x16_c2_1P_WLDRV16X4 +XA_WLDRV<0> a_wi<15> a_wi<14> a_wi<13> a_wi<12> a_wi<11> a_wi<10> a_wi<9> a_wi<8> a_wi<7> a_wi<6> a_wi<5> a_wi<4> a_wi<3> a_wi<2> a_wi<1> a_wi<0> a_wl_l<15> a_wl_l<14> a_wl_l<13> a_wl_l<12> a_wl_l<11> a_wl_l<10> a_wl_l<9> a_wl_l<8> a_wl_l<7> a_wl_l<6> a_wl_l<5> a_wl_l<4> a_wl_l<3> a_wl_l<2> a_wl_l<1> a_wl_l<0> VDD! VSS! / RM_IHPSG13_512x16_c2_1P_WLDRV16X4 + + +XA_CTRL a_aclk_n A_BIST_CLK A_BIST_MEN A_BIST_EN A_BIST_REN A_BIST_WEN a_tiel A_CLK A_MEN a_dclk a_eclk a_pulse_h a_pulse_l a_pulse a_rclk A_REN a_cs a_wclk A_WEN VDD! VSS! / RM_IHPSG13_512x16_c2_1P_CTRL + + +XA_ROWDEC a_addr_row<6> a_addr_row<5> a_addr_row<4> a_addr_row<3> a_addr_row<2> a_addr_row<1> a_addr_row<0> a_cs a_eclk a_wi<127> a_wi<126> a_wi<125> a_wi<124> a_wi<123> a_wi<122> a_wi<121> a_wi<120> a_wi<119> a_wi<118> a_wi<117> a_wi<116> a_wi<115> a_wi<114> a_wi<113> a_wi<112> a_wi<111> a_wi<110> a_wi<109> a_wi<108> a_wi<107> a_wi<106> a_wi<105> a_wi<104> a_wi<103> a_wi<102> a_wi<101> a_wi<100> a_wi<99> a_wi<98> a_wi<97> a_wi<96> a_wi<95> a_wi<94> a_wi<93> a_wi<92> a_wi<91> a_wi<90> a_wi<89> a_wi<88> a_wi<87> a_wi<86> a_wi<85> a_wi<84> a_wi<83> a_wi<82> a_wi<81> a_wi<80> a_wi<79> a_wi<78> a_wi<77> a_wi<76> a_wi<75> a_wi<74> a_wi<73> a_wi<72> a_wi<71> a_wi<70> a_wi<69> a_wi<68> a_wi<67> a_wi<66> a_wi<65> a_wi<64> a_wi<63> a_wi<62> a_wi<61> a_wi<60> a_wi<59> a_wi<58> a_wi<57> a_wi<56> a_wi<55> a_wi<54> a_wi<53> a_wi<52> a_wi<51> a_wi<50> a_wi<49> a_wi<48> a_wi<47> a_wi<46> a_wi<45> a_wi<44> a_wi<43> a_wi<42> a_wi<41> a_wi<40> a_wi<39> a_wi<38> a_wi<37> a_wi<36> a_wi<35> a_wi<34> a_wi<33> a_wi<32> a_wi<31> a_wi<30> a_wi<29> a_wi<28> a_wi<27> a_wi<26> a_wi<25> a_wi<24> a_wi<23> a_wi<22> a_wi<21> a_wi<20> a_wi<19> a_wi<18> a_wi<17> a_wi<16> a_wi<15> a_wi<14> a_wi<13> a_wi<12> a_wi<11> a_wi<10> a_wi<9> a_wi<8> a_wi<7> a_wi<6> a_wi<5> a_wi<4> a_wi<3> a_wi<2> a_wi<1> a_wi<0> VDD! VSS! / RM_IHPSG13_512x16_c2_1P_ROWDEC7 +XA_ROWREG a_aclk_n A_ADDR<8> A_ADDR<7> A_ADDR<6> A_ADDR<5> A_ADDR<4> A_ADDR<3> A_ADDR<2> a_addr_row<6> a_addr_row<5> a_addr_row<4> a_addr_row<3> a_addr_row<2> a_addr_row<1> a_addr_row<0> A_BIST_ADDR<8> A_BIST_ADDR<7> A_BIST_ADDR<6> A_BIST_ADDR<5> A_BIST_ADDR<4> A_BIST_ADDR<3> A_BIST_ADDR<2> A_BIST_EN VDD! VSS! / RM_IHPSG13_512x16_c2_1P_ROWREG7 +XA_COLDEC a_aclk_n A_ADDR<1> A_ADDR<0> a_addr_col<1> a_addr_col<0> a_addr_dec<7> a_addr_dec<6> a_addr_dec<5> a_addr_dec<4> a_addr_dec<3> a_addr_dec<2> a_addr_dec<1> a_addr_dec<0> A_BIST_ADDR<1> A_BIST_ADDR<0> A_BIST_EN VDD! VSS! / RM_IHPSG13_512x16_c2_1P_COLDEC2 + + +XA_DLYH a_pulse a_pulse_h VDD! VSS! / RM_IHPSG13_512x16_c2_1P_DLY_pcell_2 +XA_DLYL a_pulse_x a_pulse_l VDD! VSS! / RM_IHPSG13_512x16_c2_1P_DLY_pcell_3 +XA_DLYMUX a_pulse_h A_DLY a_pulse_x VDD! VSS! / RM_IHPSG13_512x16_c2_1P_DLY_MUX + +XCOLCTRL<15> a_addr_dec_r<3> a_addr_dec_r<2> a_addr_dec_r<1> a_addr_dec_r<0> A_BIST_BM<15> A_BIST_DIN<15> A_BIST_EN a_blc_r<31> a_blc_r<30> a_blc_r<29> a_blc_r<28> a_blt_r<31> a_blt_r<30> a_blt_r<29> a_blt_r<28> A_BM<15> a_dclk_n_r<7> a_dclk_n_r<8> a_dclk_p_r<7> a_dclk_p_r<8> A_DOUT<15> A_DIN<15> a_rclk_n_r<7> a_rclk_n_r<8> a_rclk_p_r<7> a_rclk_p_r<8> a_tieh<15> a_wclk_n_r<7> a_wclk_n_r<8> a_wclk_p_r<7> a_wclk_p_r<8> VDD! VSS! / RM_IHPSG13_512x16_c2_1P_COLCTRL2 +XCOLCTRL<14> a_addr_dec_r<3> a_addr_dec_r<2> a_addr_dec_r<1> a_addr_dec_r<0> A_BIST_BM<14> A_BIST_DIN<14> A_BIST_EN a_blc_r<27> a_blc_r<26> a_blc_r<25> a_blc_r<24> a_blt_r<27> a_blt_r<26> a_blt_r<25> a_blt_r<24> A_BM<14> a_dclk_n_r<6> a_dclk_n_r<7> a_dclk_p_r<6> a_dclk_p_r<7> A_DOUT<14> A_DIN<14> a_rclk_n_r<6> a_rclk_n_r<7> a_rclk_p_r<6> a_rclk_p_r<7> a_tieh<14> a_wclk_n_r<6> a_wclk_n_r<7> a_wclk_p_r<6> a_wclk_p_r<7> VDD! VSS! / RM_IHPSG13_512x16_c2_1P_COLCTRL2 +XCOLCTRL<13> a_addr_dec_r<3> a_addr_dec_r<2> a_addr_dec_r<1> a_addr_dec_r<0> A_BIST_BM<13> A_BIST_DIN<13> A_BIST_EN a_blc_r<23> a_blc_r<22> a_blc_r<21> a_blc_r<20> a_blt_r<23> a_blt_r<22> a_blt_r<21> a_blt_r<20> A_BM<13> a_dclk_n_r<5> a_dclk_n_r<6> a_dclk_p_r<5> a_dclk_p_r<6> A_DOUT<13> A_DIN<13> a_rclk_n_r<5> a_rclk_n_r<6> a_rclk_p_r<5> a_rclk_p_r<6> a_tieh<13> a_wclk_n_r<5> a_wclk_n_r<6> a_wclk_p_r<5> a_wclk_p_r<6> VDD! VSS! / RM_IHPSG13_512x16_c2_1P_COLCTRL2 +XCOLCTRL<12> a_addr_dec_r<3> a_addr_dec_r<2> a_addr_dec_r<1> a_addr_dec_r<0> A_BIST_BM<12> A_BIST_DIN<12> A_BIST_EN a_blc_r<19> a_blc_r<18> a_blc_r<17> a_blc_r<16> a_blt_r<19> a_blt_r<18> a_blt_r<17> a_blt_r<16> A_BM<12> a_dclk_n_r<4> a_dclk_n_r<5> a_dclk_p_r<4> a_dclk_p_r<5> A_DOUT<12> A_DIN<12> a_rclk_n_r<4> a_rclk_n_r<5> a_rclk_p_r<4> a_rclk_p_r<5> a_tieh<12> a_wclk_n_r<4> a_wclk_n_r<5> a_wclk_p_r<4> a_wclk_p_r<5> VDD! VSS! / RM_IHPSG13_512x16_c2_1P_COLCTRL2 +XCOLCTRL<11> a_addr_dec_r<3> a_addr_dec_r<2> a_addr_dec_r<1> a_addr_dec_r<0> A_BIST_BM<11> A_BIST_DIN<11> A_BIST_EN a_blc_r<15> a_blc_r<14> a_blc_r<13> a_blc_r<12> a_blt_r<15> a_blt_r<14> a_blt_r<13> a_blt_r<12> A_BM<11> a_dclk_n_r<3> a_dclk_n_r<4> a_dclk_p_r<3> a_dclk_p_r<4> A_DOUT<11> A_DIN<11> a_rclk_n_r<3> a_rclk_n_r<4> a_rclk_p_r<3> a_rclk_p_r<4> a_tieh<11> a_wclk_n_r<3> a_wclk_n_r<4> a_wclk_p_r<3> a_wclk_p_r<4> VDD! VSS! / RM_IHPSG13_512x16_c2_1P_COLCTRL2 +XCOLCTRL<10> a_addr_dec_r<3> a_addr_dec_r<2> a_addr_dec_r<1> a_addr_dec_r<0> A_BIST_BM<10> A_BIST_DIN<10> A_BIST_EN a_blc_r<11> a_blc_r<10> a_blc_r<9> a_blc_r<8> a_blt_r<11> a_blt_r<10> a_blt_r<9> a_blt_r<8> A_BM<10> a_dclk_n_r<2> a_dclk_n_r<3> a_dclk_p_r<2> a_dclk_p_r<3> A_DOUT<10> A_DIN<10> a_rclk_n_r<2> a_rclk_n_r<3> a_rclk_p_r<2> a_rclk_p_r<3> a_tieh<10> a_wclk_n_r<2> a_wclk_n_r<3> a_wclk_p_r<2> a_wclk_p_r<3> VDD! VSS! / RM_IHPSG13_512x16_c2_1P_COLCTRL2 +XCOLCTRL<9> a_addr_dec_r<3> a_addr_dec_r<2> a_addr_dec_r<1> a_addr_dec_r<0> A_BIST_BM<9> A_BIST_DIN<9> A_BIST_EN a_blc_r<7> a_blc_r<6> a_blc_r<5> a_blc_r<4> a_blt_r<7> a_blt_r<6> a_blt_r<5> a_blt_r<4> A_BM<9> a_dclk_n_r<1> a_dclk_n_r<2> a_dclk_p_r<1> a_dclk_p_r<2> A_DOUT<9> A_DIN<9> a_rclk_n_r<1> a_rclk_n_r<2> a_rclk_p_r<1> a_rclk_p_r<2> a_tieh<9> a_wclk_n_r<1> a_wclk_n_r<2> a_wclk_p_r<1> a_wclk_p_r<2> VDD! VSS! / RM_IHPSG13_512x16_c2_1P_COLCTRL2 +XCOLCTRL<8> a_addr_dec_r<3> a_addr_dec_r<2> a_addr_dec_r<1> a_addr_dec_r<0> A_BIST_BM<8> A_BIST_DIN<8> A_BIST_EN a_blc_r<3> a_blc_r<2> a_blc_r<1> a_blc_r<0> a_blt_r<3> a_blt_r<2> a_blt_r<1> a_blt_r<0> A_BM<8> a_dclk_n_r<0> a_dclk_n_r<1> a_dclk_p_r<0> a_dclk_p_r<1> A_DOUT<8> A_DIN<8> a_rclk_n_r<0> a_rclk_n_r<1> a_rclk_p_r<0> a_rclk_p_r<1> a_tieh<8> a_wclk_n_r<0> a_wclk_n_r<1> a_wclk_p_r<0> a_wclk_p_r<1> VDD! VSS! / RM_IHPSG13_512x16_c2_1P_COLCTRL2 +XCOLCTRL<7> a_addr_dec_l<3> a_addr_dec_l<2> a_addr_dec_l<1> a_addr_dec_l<0> A_BIST_BM<0> A_BIST_DIN<0> A_BIST_EN a_blc_l<31> a_blc_l<30> a_blc_l<29> a_blc_l<28> a_blt_l<31> a_blt_l<30> a_blt_l<29> a_blt_l<28> A_BM<0> a_dclk_n_l<7> a_dclk_n_l<8> a_dclk_p_l<7> a_dclk_p_l<8> A_DOUT<0> A_DIN<0> a_rclk_n_l<7> a_rclk_n_l<8> a_rclk_p_l<7> a_rclk_p_l<8> a_tieh<0> a_wclk_n_l<7> a_wclk_n_l<8> a_wclk_p_l<7> a_wclk_p_l<8> VDD! VSS! / RM_IHPSG13_512x16_c2_1P_COLCTRL2 +XCOLCTRL<6> a_addr_dec_l<3> a_addr_dec_l<2> a_addr_dec_l<1> a_addr_dec_l<0> A_BIST_BM<1> A_BIST_DIN<1> A_BIST_EN a_blc_l<27> a_blc_l<26> a_blc_l<25> a_blc_l<24> a_blt_l<27> a_blt_l<26> a_blt_l<25> a_blt_l<24> A_BM<1> a_dclk_n_l<6> a_dclk_n_l<7> a_dclk_p_l<6> a_dclk_p_l<7> A_DOUT<1> A_DIN<1> a_rclk_n_l<6> a_rclk_n_l<7> a_rclk_p_l<6> a_rclk_p_l<7> a_tieh<1> a_wclk_n_l<6> a_wclk_n_l<7> a_wclk_p_l<6> a_wclk_p_l<7> VDD! VSS! / RM_IHPSG13_512x16_c2_1P_COLCTRL2 +XCOLCTRL<5> a_addr_dec_l<3> a_addr_dec_l<2> a_addr_dec_l<1> a_addr_dec_l<0> A_BIST_BM<2> A_BIST_DIN<2> A_BIST_EN a_blc_l<23> a_blc_l<22> a_blc_l<21> a_blc_l<20> a_blt_l<23> a_blt_l<22> a_blt_l<21> a_blt_l<20> A_BM<2> a_dclk_n_l<5> a_dclk_n_l<6> a_dclk_p_l<5> a_dclk_p_l<6> A_DOUT<2> A_DIN<2> a_rclk_n_l<5> a_rclk_n_l<6> a_rclk_p_l<5> a_rclk_p_l<6> a_tieh<2> a_wclk_n_l<5> a_wclk_n_l<6> a_wclk_p_l<5> a_wclk_p_l<6> VDD! VSS! / RM_IHPSG13_512x16_c2_1P_COLCTRL2 +XCOLCTRL<4> a_addr_dec_l<3> a_addr_dec_l<2> a_addr_dec_l<1> a_addr_dec_l<0> A_BIST_BM<3> A_BIST_DIN<3> A_BIST_EN a_blc_l<19> a_blc_l<18> a_blc_l<17> a_blc_l<16> a_blt_l<19> a_blt_l<18> a_blt_l<17> a_blt_l<16> A_BM<3> a_dclk_n_l<4> a_dclk_n_l<5> a_dclk_p_l<4> a_dclk_p_l<5> A_DOUT<3> A_DIN<3> a_rclk_n_l<4> a_rclk_n_l<5> a_rclk_p_l<4> a_rclk_p_l<5> a_tieh<3> a_wclk_n_l<4> a_wclk_n_l<5> a_wclk_p_l<4> a_wclk_p_l<5> VDD! VSS! / RM_IHPSG13_512x16_c2_1P_COLCTRL2 +XCOLCTRL<3> a_addr_dec_l<3> a_addr_dec_l<2> a_addr_dec_l<1> a_addr_dec_l<0> A_BIST_BM<4> A_BIST_DIN<4> A_BIST_EN a_blc_l<15> a_blc_l<14> a_blc_l<13> a_blc_l<12> a_blt_l<15> a_blt_l<14> a_blt_l<13> a_blt_l<12> A_BM<4> a_dclk_n_l<3> a_dclk_n_l<4> a_dclk_p_l<3> a_dclk_p_l<4> A_DOUT<4> A_DIN<4> a_rclk_n_l<3> a_rclk_n_l<4> a_rclk_p_l<3> a_rclk_p_l<4> a_tieh<4> a_wclk_n_l<3> a_wclk_n_l<4> a_wclk_p_l<3> a_wclk_p_l<4> VDD! VSS! / RM_IHPSG13_512x16_c2_1P_COLCTRL2 +XCOLCTRL<2> a_addr_dec_l<3> a_addr_dec_l<2> a_addr_dec_l<1> a_addr_dec_l<0> A_BIST_BM<5> A_BIST_DIN<5> A_BIST_EN a_blc_l<11> a_blc_l<10> a_blc_l<9> a_blc_l<8> a_blt_l<11> a_blt_l<10> a_blt_l<9> a_blt_l<8> A_BM<5> a_dclk_n_l<2> a_dclk_n_l<3> a_dclk_p_l<2> a_dclk_p_l<3> A_DOUT<5> A_DIN<5> a_rclk_n_l<2> a_rclk_n_l<3> a_rclk_p_l<2> a_rclk_p_l<3> a_tieh<5> a_wclk_n_l<2> a_wclk_n_l<3> a_wclk_p_l<2> a_wclk_p_l<3> VDD! VSS! / RM_IHPSG13_512x16_c2_1P_COLCTRL2 +XCOLCTRL<1> a_addr_dec_l<3> a_addr_dec_l<2> a_addr_dec_l<1> a_addr_dec_l<0> A_BIST_BM<6> A_BIST_DIN<6> A_BIST_EN a_blc_l<7> a_blc_l<6> a_blc_l<5> a_blc_l<4> a_blt_l<7> a_blt_l<6> a_blt_l<5> a_blt_l<4> A_BM<6> a_dclk_n_l<1> a_dclk_n_l<2> a_dclk_p_l<1> a_dclk_p_l<2> A_DOUT<6> A_DIN<6> a_rclk_n_l<1> a_rclk_n_l<2> a_rclk_p_l<1> a_rclk_p_l<2> a_tieh<6> a_wclk_n_l<1> a_wclk_n_l<2> a_wclk_p_l<1> a_wclk_p_l<2> VDD! VSS! / RM_IHPSG13_512x16_c2_1P_COLCTRL2 +XCOLCTRL<0> a_addr_dec_l<3> a_addr_dec_l<2> a_addr_dec_l<1> a_addr_dec_l<0> A_BIST_BM<7> A_BIST_DIN<7> A_BIST_EN a_blc_l<3> a_blc_l<2> a_blc_l<1> a_blc_l<0> a_blt_l<3> a_blt_l<2> a_blt_l<1> a_blt_l<0> A_BM<7> a_dclk_n_l<0> a_dclk_n_l<1> a_dclk_p_l<0> a_dclk_p_l<1> A_DOUT<7> A_DIN<7> a_rclk_n_l<0> a_rclk_n_l<1> a_rclk_p_l<0> a_rclk_p_l<1> a_tieh<7> a_wclk_n_l<0> a_wclk_n_l<1> a_wclk_p_l<0> a_wclk_p_l<1> VDD! VSS! / RM_IHPSG13_512x16_c2_1P_COLCTRL2 + + +XDRVFILL4<1> VDD! VSS! / RM_IHPSG13_512x16_c2_1P_COLDRV13_FILL4 +XDRVFILL4<2> VDD! VSS! / RM_IHPSG13_512x16_c2_1P_COLDRV13_FILL4 +XCOLFILL4<1> VDD! VSS! / RM_IHPSG13_512x16_c2_1P_COLDRV13_FILL4C2 +XCOLFILL4<2> VDD! VSS! / RM_IHPSG13_512x16_c2_1P_COLDRV13_FILL4C2 +XCOLFILL4<3> VDD! VSS! / RM_IHPSG13_512x16_c2_1P_COLDRV13_FILL4C2 +XCOLFILL4<4> VDD! VSS! / RM_IHPSG13_512x16_c2_1P_COLDRV13_FILL4C2 +XCOLFILL4<5> VDD! VSS! / RM_IHPSG13_512x16_c2_1P_COLDRV13_FILL4C2 +XCOLFILL4<6> VDD! VSS! / RM_IHPSG13_512x16_c2_1P_COLDRV13_FILL4C2 +.ENDS diff --git a/flow/platforms/ihp-sg13g2/cdl/RM_IHPSG13_1P_512x32_c2_bm_bist.cdl b/flow/platforms/ihp-sg13g2/cdl/RM_IHPSG13_1P_512x32_c2_bm_bist.cdl new file mode 100644 index 0000000000..1b58ff2ff6 --- /dev/null +++ b/flow/platforms/ihp-sg13g2/cdl/RM_IHPSG13_1P_512x32_c2_bm_bist.cdl @@ -0,0 +1,6383 @@ +* ------------------------------------------------------ +* +* Copyright 2023 IHP PDK Authors +* +* Licensed under the Apache License, Version 2.0 (the "License"); +* you may not use this file except in compliance with the License. +* You may obtain a copy of the License at +* +* https://www.apache.org/licenses/LICENSE-2.0 +* +* Unless required by applicable law or agreed to in writing, software +* distributed under the License is distributed on an "AS IS" BASIS, +* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +* See the License for the specific language governing permissions and +* limitations under the License. +* +* Generated on Wed Apr 2 16:02:47 2025 +* +* ------------------------------------------------------ + +.SUBCKT RM_IHPSG13_512x32_c2_1P_BITKIT_CORNER NW PW VDD VSS +.ENDS +.SUBCKT RM_IHPSG13_512x32_c2_1P_BITKIT_16x2_CORNER VDD_CORE VSS +XI16 VDD_CORE VSS VDD_CORE VSS / ++ RM_IHPSG13_512x32_c2_1P_BITKIT_CORNER +.ENDS +.SUBCKT RM_IHPSG13_512x32_c2_1P_BITKIT_EDGE_LR LWL NW PW VDD VSS +MN1 VSS LWL VSS VSS sg13_lv_nmos m=1 w=300.0n l=130.00n ng=1 nrd=0 nrs=0 +MN0 VSS net9 VSS VSS sg13_lv_nmos m=1 w=300.0n l=130.00n ng=1 nrd=0 nrs=0 +.ENDS +.SUBCKT RM_IHPSG13_512x32_c2_1P_BITKIT_16x2_EDGE_LR A_WL<15> A_WL<14> A_WL<13> A_WL<12> ++ A_WL<11> A_WL<10> A_WL<9> A_WL<8> A_WL<7> A_WL<6> A_WL<5> A_WL<4> A_WL<3> ++ A_WL<2> A_WL<1> A_WL<0> VDD_CORE VSS +XI0<15> A_WL<15> VDD_CORE VSS VDD_CORE VSS / ++ RM_IHPSG13_512x32_c2_1P_BITKIT_EDGE_LR +XI0<14> A_WL<14> VDD_CORE VSS VDD_CORE VSS / ++ RM_IHPSG13_512x32_c2_1P_BITKIT_EDGE_LR +XI0<13> A_WL<13> VDD_CORE VSS VDD_CORE VSS / ++ RM_IHPSG13_512x32_c2_1P_BITKIT_EDGE_LR +XI0<12> A_WL<12> VDD_CORE VSS VDD_CORE VSS / ++ RM_IHPSG13_512x32_c2_1P_BITKIT_EDGE_LR +XI0<11> A_WL<11> VDD_CORE VSS VDD_CORE VSS / ++ RM_IHPSG13_512x32_c2_1P_BITKIT_EDGE_LR +XI0<10> A_WL<10> VDD_CORE VSS VDD_CORE VSS / ++ RM_IHPSG13_512x32_c2_1P_BITKIT_EDGE_LR +XI0<9> A_WL<9> VDD_CORE VSS VDD_CORE VSS / ++ RM_IHPSG13_512x32_c2_1P_BITKIT_EDGE_LR +XI0<8> A_WL<8> VDD_CORE VSS VDD_CORE VSS / ++ RM_IHPSG13_512x32_c2_1P_BITKIT_EDGE_LR +XI0<7> A_WL<7> VDD_CORE VSS VDD_CORE VSS / ++ RM_IHPSG13_512x32_c2_1P_BITKIT_EDGE_LR +XI0<6> A_WL<6> VDD_CORE VSS VDD_CORE VSS / ++ RM_IHPSG13_512x32_c2_1P_BITKIT_EDGE_LR +XI0<5> A_WL<5> VDD_CORE VSS VDD_CORE VSS / ++ RM_IHPSG13_512x32_c2_1P_BITKIT_EDGE_LR +XI0<4> A_WL<4> VDD_CORE VSS VDD_CORE VSS / ++ RM_IHPSG13_512x32_c2_1P_BITKIT_EDGE_LR +XI0<3> A_WL<3> VDD_CORE VSS VDD_CORE VSS / ++ RM_IHPSG13_512x32_c2_1P_BITKIT_EDGE_LR +XI0<2> A_WL<2> VDD_CORE VSS VDD_CORE VSS / ++ RM_IHPSG13_512x32_c2_1P_BITKIT_EDGE_LR +XI0<1> A_WL<1> VDD_CORE VSS VDD_CORE VSS / ++ RM_IHPSG13_512x32_c2_1P_BITKIT_EDGE_LR +XI0<0> A_WL<0> VDD_CORE VSS VDD_CORE VSS / ++ RM_IHPSG13_512x32_c2_1P_BITKIT_EDGE_LR +.ENDS +.SUBCKT RM_IHPSG13_512x32_c2_1P_BITKIT_CELL BLC_BOT BLC_TOP BLT_BOT BLT_TOP LWL NW PW ++ RWL VDD VSS +MN0 NC NT VSS PW sg13_lv_nmos m=1 w=300.0n l=130.00n ng=1 nrd=0 nrs=0 +MN1 NT NC VSS PW sg13_lv_nmos m=1 w=300.0n l=130.00n ng=1 nrd=0 nrs=0 +MN3 NC RWL BLC_TOP PW sg13_lv_nmos m=1 w=300.0n l=130.00n ng=1 nrd=0 nrs=0 +MN2 BLT_BOT LWL NT PW sg13_lv_nmos m=1 w=300.0n l=130.00n ng=1 nrd=0 nrs=0 +MP1 NT NC VDD NW sg13_lv_pmos m=1 w=150.00n l=130.00n ng=1 nrd=0 nrs=0 +MP0 NC NT VDD NW sg13_lv_pmos m=1 w=150.00n l=130.00n ng=1 nrd=0 nrs=0 +R1 BLC_BOT BLC_TOP lvsres w=2.6e-07 l=6e-07 +R0 BLT_BOT BLT_TOP lvsres w=2.6e-07 l=6e-07 +R2 RWL LWL lvsres w=2.6e-07 l=6e-07 +.ENDS +.SUBCKT RM_IHPSG13_512x32_c2_1P_BITKIT_16x2_SRAM A_BLC_BOT<1> A_BLC_BOT<0> A_BLC_TOP<1> ++ A_BLC_TOP<0> A_BLT_BOT<1> A_BLT_BOT<0> A_BLT_TOP<1> A_BLT_TOP<0> A_LWL<15> ++ A_LWL<14> A_LWL<13> A_LWL<12> A_LWL<11> A_LWL<10> A_LWL<9> A_LWL<8> A_LWL<7> ++ A_LWL<6> A_LWL<5> A_LWL<4> A_LWL<3> A_LWL<2> A_LWL<1> A_LWL<0> A_RWL<15> ++ A_RWL<14> A_RWL<13> A_RWL<12> A_RWL<11> A_RWL<10> A_RWL<9> A_RWL<8> A_RWL<7> ++ A_RWL<6> A_RWL<5> A_RWL<4> A_RWL<3> A_RWL<2> A_RWL<1> A_RWL<0> VDD_CORE ++ VSS +XCELL<31> A_BLC_TOP<1> A_RBLC<15> A_BLT_TOP<1> A_RBLT<15> A_RWL<15> ++ VDD_CORE VSS A_XWL<15> VDD_CORE VSS / ++ RM_IHPSG13_512x32_c2_1P_BITKIT_CELL +XCELL<30> A_RBLC<14> A_RBLC<15> A_RBLT<14> A_RBLT<15> A_RWL<14> VDD_CORE ++ VSS A_XWL<14> VDD_CORE VSS / RM_IHPSG13_512x32_c2_1P_BITKIT_CELL +XCELL<29> A_RBLC<14> A_RBLC<13> A_RBLT<14> A_RBLT<13> A_RWL<13> VDD_CORE ++ VSS A_XWL<13> VDD_CORE VSS / RM_IHPSG13_512x32_c2_1P_BITKIT_CELL +XCELL<28> A_RBLC<12> A_RBLC<13> A_RBLT<12> A_RBLT<13> A_RWL<12> VDD_CORE ++ VSS A_XWL<12> VDD_CORE VSS / RM_IHPSG13_512x32_c2_1P_BITKIT_CELL +XCELL<27> A_RBLC<12> A_RBLC<11> A_RBLT<12> A_RBLT<11> A_RWL<11> VDD_CORE ++ VSS A_XWL<11> VDD_CORE VSS / RM_IHPSG13_512x32_c2_1P_BITKIT_CELL +XCELL<26> A_RBLC<10> A_RBLC<11> A_RBLT<10> A_RBLT<11> A_RWL<10> VDD_CORE ++ VSS A_XWL<10> VDD_CORE VSS / RM_IHPSG13_512x32_c2_1P_BITKIT_CELL +XCELL<25> A_RBLC<10> A_RBLC<9> A_RBLT<10> A_RBLT<9> A_RWL<9> VDD_CORE ++ VSS A_XWL<9> VDD_CORE VSS / RM_IHPSG13_512x32_c2_1P_BITKIT_CELL +XCELL<24> A_RBLC<8> A_RBLC<9> A_RBLT<8> A_RBLT<9> A_RWL<8> VDD_CORE ++ VSS A_XWL<8> VDD_CORE VSS / RM_IHPSG13_512x32_c2_1P_BITKIT_CELL +XCELL<23> A_RBLC<8> A_RBLC<7> A_RBLT<8> A_RBLT<7> A_RWL<7> VDD_CORE ++ VSS A_XWL<7> VDD_CORE VSS / RM_IHPSG13_512x32_c2_1P_BITKIT_CELL +XCELL<22> A_RBLC<6> A_RBLC<7> A_RBLT<6> A_RBLT<7> A_RWL<6> VDD_CORE ++ VSS A_XWL<6> VDD_CORE VSS / RM_IHPSG13_512x32_c2_1P_BITKIT_CELL +XCELL<21> A_RBLC<6> A_RBLC<5> A_RBLT<6> A_RBLT<5> A_RWL<5> VDD_CORE ++ VSS A_XWL<5> VDD_CORE VSS / RM_IHPSG13_512x32_c2_1P_BITKIT_CELL +XCELL<20> A_RBLC<4> A_RBLC<5> A_RBLT<4> A_RBLT<5> A_RWL<4> VDD_CORE ++ VSS A_XWL<4> VDD_CORE VSS / RM_IHPSG13_512x32_c2_1P_BITKIT_CELL +XCELL<19> A_RBLC<4> A_RBLC<3> A_RBLT<4> A_RBLT<3> A_RWL<3> VDD_CORE ++ VSS A_XWL<3> VDD_CORE VSS / RM_IHPSG13_512x32_c2_1P_BITKIT_CELL +XCELL<18> A_RBLC<2> A_RBLC<3> A_RBLT<2> A_RBLT<3> A_RWL<2> VDD_CORE ++ VSS A_XWL<2> VDD_CORE VSS / RM_IHPSG13_512x32_c2_1P_BITKIT_CELL +XCELL<17> A_RBLC<2> A_RBLC<1> A_RBLT<2> A_RBLT<1> A_RWL<1> VDD_CORE ++ VSS A_XWL<1> VDD_CORE VSS / RM_IHPSG13_512x32_c2_1P_BITKIT_CELL +XCELL<16> A_BLC_BOT<1> A_RBLC<1> A_BLT_BOT<1> A_RBLT<1> A_RWL<0> VDD_CORE ++ VSS A_XWL<0> VDD_CORE VSS / RM_IHPSG13_512x32_c2_1P_BITKIT_CELL +XCELL<15> A_BLC_TOP<0> A_LBLC<15> A_BLT_TOP<0> A_LBLT<15> A_LWL<15> ++ VDD_CORE VSS A_XWL<15> VDD_CORE VSS / ++ RM_IHPSG13_512x32_c2_1P_BITKIT_CELL +XCELL<14> A_LBLC<14> A_LBLC<15> A_LBLT<14> A_LBLT<15> A_LWL<14> VDD_CORE ++ VSS A_XWL<14> VDD_CORE VSS / RM_IHPSG13_512x32_c2_1P_BITKIT_CELL +XCELL<13> A_LBLC<14> A_LBLC<13> A_LBLT<14> A_LBLT<13> A_LWL<13> VDD_CORE ++ VSS A_XWL<13> VDD_CORE VSS / RM_IHPSG13_512x32_c2_1P_BITKIT_CELL +XCELL<12> A_LBLC<12> A_LBLC<13> A_LBLT<12> A_LBLT<13> A_LWL<12> VDD_CORE ++ VSS A_XWL<12> VDD_CORE VSS / RM_IHPSG13_512x32_c2_1P_BITKIT_CELL +XCELL<11> A_LBLC<12> A_LBLC<11> A_LBLT<12> A_LBLT<11> A_LWL<11> VDD_CORE ++ VSS A_XWL<11> VDD_CORE VSS / RM_IHPSG13_512x32_c2_1P_BITKIT_CELL +XCELL<10> A_LBLC<10> A_LBLC<11> A_LBLT<10> A_LBLT<11> A_LWL<10> VDD_CORE ++ VSS A_XWL<10> VDD_CORE VSS / RM_IHPSG13_512x32_c2_1P_BITKIT_CELL +XCELL<9> A_LBLC<10> A_LBLC<9> A_LBLT<10> A_LBLT<9> A_LWL<9> VDD_CORE ++ VSS A_XWL<9> VDD_CORE VSS / RM_IHPSG13_512x32_c2_1P_BITKIT_CELL +XCELL<8> A_LBLC<8> A_LBLC<9> A_LBLT<8> A_LBLT<9> A_LWL<8> VDD_CORE ++ VSS A_XWL<8> VDD_CORE VSS / RM_IHPSG13_512x32_c2_1P_BITKIT_CELL +XCELL<7> A_LBLC<8> A_LBLC<7> A_LBLT<8> A_LBLT<7> A_LWL<7> VDD_CORE ++ VSS A_XWL<7> VDD_CORE VSS / RM_IHPSG13_512x32_c2_1P_BITKIT_CELL +XCELL<6> A_LBLC<6> A_LBLC<7> A_LBLT<6> A_LBLT<7> A_LWL<6> VDD_CORE ++ VSS A_XWL<6> VDD_CORE VSS / RM_IHPSG13_512x32_c2_1P_BITKIT_CELL +XCELL<5> A_LBLC<6> A_LBLC<5> A_LBLT<6> A_LBLT<5> A_LWL<5> VDD_CORE ++ VSS A_XWL<5> VDD_CORE VSS / RM_IHPSG13_512x32_c2_1P_BITKIT_CELL +XCELL<4> A_LBLC<4> A_LBLC<5> A_LBLT<4> A_LBLT<5> A_LWL<4> VDD_CORE ++ VSS A_XWL<4> VDD_CORE VSS / RM_IHPSG13_512x32_c2_1P_BITKIT_CELL +XCELL<3> A_LBLC<4> A_LBLC<3> A_LBLT<4> A_LBLT<3> A_LWL<3> VDD_CORE ++ VSS A_XWL<3> VDD_CORE VSS / RM_IHPSG13_512x32_c2_1P_BITKIT_CELL +XCELL<2> A_LBLC<2> A_LBLC<3> A_LBLT<2> A_LBLT<3> A_LWL<2> VDD_CORE ++ VSS A_XWL<2> VDD_CORE VSS / RM_IHPSG13_512x32_c2_1P_BITKIT_CELL +XCELL<1> A_LBLC<2> A_LBLC<1> A_LBLT<2> A_LBLT<1> A_LWL<1> VDD_CORE ++ VSS A_XWL<1> VDD_CORE VSS / RM_IHPSG13_512x32_c2_1P_BITKIT_CELL +XCELL<0> A_BLC_BOT<0> A_LBLC<1> A_BLT_BOT<0> A_LBLT<1> A_LWL<0> VDD_CORE ++ VSS A_XWL<0> VDD_CORE VSS / RM_IHPSG13_512x32_c2_1P_BITKIT_CELL +.ENDS +.SUBCKT RM_IHPSG13_512x32_c2_1P_BITKIT_EDGE_TB BLC BLT NW PW VDD VSS +.ENDS +.SUBCKT RM_IHPSG13_512x32_c2_1P_BITKIT_16x2_EDGE_TB A_BLC<1> A_BLC<0> A_BLT<1> A_BLT<0> ++ VDD_CORE VSS +XEDGE<1> A_BLC<1> A_BLT<1> VDD_CORE VSS VDD_CORE VSS ++ / RM_IHPSG13_512x32_c2_1P_BITKIT_EDGE_TB +XEDGE<0> A_BLC<0> A_BLT<0> VDD_CORE VSS VDD_CORE VSS ++ / RM_IHPSG13_512x32_c2_1P_BITKIT_EDGE_TB +.ENDS + +.SUBCKT RSC_IHPSG13_CBUFX4 A Z VDD VSS +MN0 net9 A VSS VSS sg13_lv_nmos m=1 w=705.000n l=130.00n ng=1 nrd=0 ++ nrs=0 +MN1 Z net9 VSS VSS sg13_lv_nmos m=1 w=1.41u l=130.00n ng=2 nrd=0 nrs=0 +MP0 net9 A VDD VDD sg13_lv_pmos m=1 w=1.62u l=130.00n ng=1 nrd=0 nrs=0 +MP1 Z net9 VDD VDD sg13_lv_pmos m=1 w=3.24u l=130.00n ng=2 nrd=0 nrs=0 +.ENDS +.SUBCKT RM_IHPSG13_512x32_c2_1P_COLDRV13X4 ADDR_COL_I<1> ADDR_COL_I<0> ADDR_COL_O<1> ++ ADDR_COL_O<0> ADDR_DEC_I<7> ADDR_DEC_I<6> ADDR_DEC_I<5> ADDR_DEC_I<4> ++ ADDR_DEC_I<3> ADDR_DEC_I<2> ADDR_DEC_I<1> ADDR_DEC_I<0> ADDR_DEC_O<7> ++ ADDR_DEC_O<6> ADDR_DEC_O<5> ADDR_DEC_O<4> ADDR_DEC_O<3> ADDR_DEC_O<2> ++ ADDR_DEC_O<1> ADDR_DEC_O<0> DCLK_I DCLK_O RCLK_I RCLK_O WCLK_I WCLK_O ++ VDD VSS +XADDR_COL_DRV<1> ADDR_COL_I<1> ADDR_COL_O<1> VDD VSS / ++ RSC_IHPSG13_CBUFX4 +XADDR_COL_DRV<0> ADDR_COL_I<0> ADDR_COL_O<0> VDD VSS / ++ RSC_IHPSG13_CBUFX4 +XADDR_DEC_DRV<7> ADDR_DEC_I<7> ADDR_DEC_O<7> VDD VSS / ++ RSC_IHPSG13_CBUFX4 +XADDR_DEC_DRV<6> ADDR_DEC_I<6> ADDR_DEC_O<6> VDD VSS / ++ RSC_IHPSG13_CBUFX4 +XADDR_DEC_DRV<5> ADDR_DEC_I<5> ADDR_DEC_O<5> VDD VSS / ++ RSC_IHPSG13_CBUFX4 +XADDR_DEC_DRV<4> ADDR_DEC_I<4> ADDR_DEC_O<4> VDD VSS / ++ RSC_IHPSG13_CBUFX4 +XADDR_DEC_DRV<3> ADDR_DEC_I<3> ADDR_DEC_O<3> VDD VSS / ++ RSC_IHPSG13_CBUFX4 +XADDR_DEC_DRV<2> ADDR_DEC_I<2> ADDR_DEC_O<2> VDD VSS / ++ RSC_IHPSG13_CBUFX4 +XADDR_DEC_DRV<1> ADDR_DEC_I<1> ADDR_DEC_O<1> VDD VSS / ++ RSC_IHPSG13_CBUFX4 +XADDR_DEC_DRV<0> ADDR_DEC_I<0> ADDR_DEC_O<0> VDD VSS / ++ RSC_IHPSG13_CBUFX4 +XDCLK_DRV DCLK_I DCLK_O VDD VSS / RSC_IHPSG13_CBUFX4 +XRCLK_DRV RCLK_I RCLK_O VDD VSS / RSC_IHPSG13_CBUFX4 +XWCLK_DRV WCLK_I WCLK_O VDD VSS / RSC_IHPSG13_CBUFX4 +.ENDS +.SUBCKT RSC_IHPSG13_WLDRVX4 A Z VDD VSS +MN1 Z net6 VSS VSS sg13_lv_nmos m=1 w=705.000n l=130.00n ng=1 nrd=0 ++ nrs=0 +MN0 net6 A VSS VSS sg13_lv_nmos m=1 w=900.0n l=130.00n ng=1 nrd=0 nrs=0 +MP1 Z net6 VDD VDD sg13_lv_pmos m=1 w=3.24u l=130.00n ng=2 nrd=0 nrs=0 +MP0 net6 A VDD VDD sg13_lv_pmos m=1 w=900.0n l=130.00n ng=1 nrd=0 nrs=0 +.ENDS +.SUBCKT RM_IHPSG13_512x32_c2_1P_WLDRV16X4 A<15> A<14> A<13> A<12> A<11> A<10> A<9> A<8> ++ A<7> A<6> A<5> A<4> A<3> A<2> A<1> A<0> Z<15> Z<14> Z<13> Z<12> Z<11> Z<10> ++ Z<9> Z<8> Z<7> Z<6> Z<5> Z<4> Z<3> Z<2> Z<1> Z<0> VDD VSS +XBUF<15> A<15> Z<15> VDD VSS / RSC_IHPSG13_WLDRVX4 +XBUF<14> A<14> Z<14> VDD VSS / RSC_IHPSG13_WLDRVX4 +XBUF<13> A<13> Z<13> VDD VSS / RSC_IHPSG13_WLDRVX4 +XBUF<12> A<12> Z<12> VDD VSS / RSC_IHPSG13_WLDRVX4 +XBUF<11> A<11> Z<11> VDD VSS / RSC_IHPSG13_WLDRVX4 +XBUF<10> A<10> Z<10> VDD VSS / RSC_IHPSG13_WLDRVX4 +XBUF<9> A<9> Z<9> VDD VSS / RSC_IHPSG13_WLDRVX4 +XBUF<8> A<8> Z<8> VDD VSS / RSC_IHPSG13_WLDRVX4 +XBUF<7> A<7> Z<7> VDD VSS / RSC_IHPSG13_WLDRVX4 +XBUF<6> A<6> Z<6> VDD VSS / RSC_IHPSG13_WLDRVX4 +XBUF<5> A<5> Z<5> VDD VSS / RSC_IHPSG13_WLDRVX4 +XBUF<4> A<4> Z<4> VDD VSS / RSC_IHPSG13_WLDRVX4 +XBUF<3> A<3> Z<3> VDD VSS / RSC_IHPSG13_WLDRVX4 +XBUF<2> A<2> Z<2> VDD VSS / RSC_IHPSG13_WLDRVX4 +XBUF<1> A<1> Z<1> VDD VSS / RSC_IHPSG13_WLDRVX4 +XBUF<0> A<0> Z<0> VDD VSS / RSC_IHPSG13_WLDRVX4 +.ENDS +.SUBCKT RSC_IHPSG13_FILLCAP8 VDD VSS +MN0 vss_r vdd_r VSS VSS sg13_lv_nmos m=1 w=4.98u l=130.00n ng=6 nrd=0 ++ nrs=0 +MP0 vdd_r vss_r VDD VDD sg13_lv_pmos m=1 w=6.48u l=385.000n ng=4 nrd=0 ++ nrs=0 +.ENDS +.SUBCKT RSC_IHPSG13_LHPQX2 CP D Q VDD VSS +MN3 QIN CPN net14 VSS sg13_lv_nmos m=1 w=480.00n l=130.00n ng=1 nrd=0 nrs=0 +MN2 net14 net10 VSS VSS sg13_lv_nmos m=1 w=480.00n l=130.00n ng=1 ++ nrd=0 nrs=0 +MN5 net21 D VSS VSS sg13_lv_nmos m=1 w=870.00n l=130.00n ng=1 nrd=0 ++ nrs=0 +MN6 QIN CP net21 VSS sg13_lv_nmos m=1 w=870.00n l=130.00n ng=1 nrd=0 nrs=0 +MN1 net10 QIN VSS VSS sg13_lv_nmos m=1 w=480.00n l=130.00n ng=1 nrd=0 ++ nrs=0 +MN0 CPN CP VSS VSS sg13_lv_nmos m=1 w=480.00n l=130.00n ng=1 nrd=0 ++ nrs=0 +MN4 Q QIN VSS VSS sg13_lv_nmos m=1 w=980.00n l=130.00n ng=1 nrd=0 nrs=0 +MP2 QIN CP net16 VDD sg13_lv_pmos m=1 w=480.00n l=130.00n ng=1 nrd=0 nrs=0 +MP0 CPN CP VDD VDD sg13_lv_pmos m=1 w=480.00n l=130.00n ng=1 nrd=0 ++ nrs=0 +MP4 Q QIN VDD VDD sg13_lv_pmos m=1 w=1.62u l=130.00n ng=1 nrd=0 nrs=0 +MP3 net10 QIN VDD VDD sg13_lv_pmos m=1 w=480.00n l=130.00n ng=1 nrd=0 ++ nrs=0 +MP1 net16 net10 VDD VDD sg13_lv_pmos m=1 w=480.00n l=130.00n ng=1 ++ nrd=0 nrs=0 +MP6 QIN CPN net20 VDD sg13_lv_pmos m=1 w=975.000n l=130.00n ng=1 nrd=0 ++ nrs=0 +MP5 net20 D VDD VDD sg13_lv_pmos m=1 w=975.000n l=130.00n ng=1 nrd=0 ++ nrs=0 +.ENDS +.SUBCKT RSC_IHPSG13_NAND2X2 A B Z VDD VSS +MP1 Z B VDD VDD sg13_lv_pmos m=1 w=1.62u l=130.00n ng=1 nrd=0 nrs=0 +MP0 Z A VDD VDD sg13_lv_pmos m=1 w=1.62u l=130.00n ng=1 nrd=0 nrs=0 +MN0 Z B net7 VSS sg13_lv_nmos m=1 w=980.00n l=130.00n ng=1 nrd=0 nrs=0 +MN1 net7 A VSS VSS sg13_lv_nmos m=1 w=980.00n l=130.00n ng=1 nrd=0 ++ nrs=0 +.ENDS +.SUBCKT RSC_IHPSG13_CINVX4 A Z VDD VSS +MN0 Z A VSS VSS sg13_lv_nmos m=1 w=1.41u l=130.00n ng=2 nrd=0 nrs=0 +MP0 Z A VDD VDD sg13_lv_pmos m=1 w=3.24u l=130.00n ng=2 nrd=0 nrs=0 +.ENDS +.SUBCKT RSC_IHPSG13_CINVX2 A Z VDD VSS +MN0 Z A VSS VSS sg13_lv_nmos m=1 w=705.000n l=130.00n ng=1 nrd=0 nrs=0 +MP0 Z A VDD VDD sg13_lv_pmos m=1 w=1.62u l=130.00n ng=1 nrd=0 nrs=0 +.ENDS +.SUBCKT RSC_IHPSG13_INVX2 A Z VDD VSS +MN0 Z A VSS VSS sg13_lv_nmos m=1 w=980.00n l=130.00n ng=1 nrd=0 nrs=0 +MP0 Z A VDD VDD sg13_lv_pmos m=1 w=1.62u l=130.00n ng=1 nrd=0 nrs=0 +.ENDS +.SUBCKT RSC_IHPSG13_NAND3X2 A B C Z VDD VSS +MP2 Z A VDD VDD sg13_lv_pmos m=1 w=1.62u l=130.00n ng=1 nrd=0 nrs=0 +MP1 Z B VDD VDD sg13_lv_pmos m=1 w=1.62u l=130.00n ng=1 nrd=0 nrs=0 +MP0 Z C VDD VDD sg13_lv_pmos m=1 w=1.62u l=130.00n ng=1 nrd=0 nrs=0 +MN1 net12 B net16 VSS sg13_lv_nmos m=1 w=980.00n l=130.00n ng=1 nrd=0 nrs=0 +MN0 Z C net12 VSS sg13_lv_nmos m=1 w=980.00n l=130.00n ng=1 nrd=0 nrs=0 +MN2 net16 A VSS VSS sg13_lv_nmos m=1 w=980.00n l=130.00n ng=1 nrd=0 ++ nrs=0 +.ENDS +.SUBCKT RSC_IHPSG13_NOR3X2 A B C Z VDD VSS +MP0 net13 A VDD VDD sg13_lv_pmos m=1 w=1.62u l=130.00n ng=1 nrd=0 nrs=0 +MP2 Z C net10 VDD sg13_lv_pmos m=1 w=1.62u l=130.00n ng=1 nrd=0 nrs=0 +MP1 net10 B net13 VDD sg13_lv_pmos m=1 w=1.62u l=130.00n ng=1 nrd=0 nrs=0 +MN1 Z B VSS VSS sg13_lv_nmos m=1 w=875.000n l=130.00n ng=1 nrd=0 nrs=0 +MN0 Z C VSS VSS sg13_lv_nmos m=1 w=875.000n l=130.00n ng=1 nrd=0 nrs=0 +MN2 Z A VSS VSS sg13_lv_nmos m=1 w=875.000n l=130.00n ng=1 nrd=0 nrs=0 +.ENDS +.SUBCKT RSC_IHPSG13_FILLCAP4 VDD VSS +MN0 vss_r vdd_r VSS VSS sg13_lv_nmos m=1 w=2.49u l=130.00n ng=3 nrd=0 ++ nrs=0 +MP0 vdd_r vss_r VDD VDD sg13_lv_pmos m=1 w=3.24u l=385.000n ng=2 nrd=0 ++ nrs=0 +.ENDS +.SUBCKT RSC_IHPSG13_MET2RES A B +R0 B A lvsres w=2.6e-07 l=6e-07 +.ENDS +.SUBCKT RM_IHPSG13_512x32_c2_1P_DEC04 ADDR<3> ADDR<2> ADDR<1> ADDR<0> CS ECLK_H_BOT ++ ECLK_H_TOP ECLK_L_BOT ECLK_L_TOP WL<15> WL<14> WL<13> WL<12> WL<11> WL<10> ++ WL<9> WL<8> WL<7> WL<6> WL<5> WL<4> WL<3> WL<2> WL<1> WL<0> VDD VSS +XLATCH<3> CS ADDR<3> PADR<3> VDD VSS / RSC_IHPSG13_LHPQX2 +XLATCH<2> CS ADDR<2> PADR<2> VDD VSS / RSC_IHPSG13_LHPQX2 +XLATCH<1> CS ADDR<1> PADR<1> VDD VSS / RSC_IHPSG13_LHPQX2 +XLATCH<0> CS ADDR<0> PADR<0> VDD VSS / RSC_IHPSG13_LHPQX2 +XI0<3> PADR<1> PADR<0> sel01<3> VDD VSS / RSC_IHPSG13_NAND2X2 +XI0<2> PADR<1> NADR<0> sel01<2> VDD VSS / RSC_IHPSG13_NAND2X2 +XI0<1> NADR<1> PADR<0> sel01<1> VDD VSS / RSC_IHPSG13_NAND2X2 +XI0<0> NADR<1> NADR<0> sel01<0> VDD VSS / RSC_IHPSG13_NAND2X2 +XI4 ECLK_L_BOT EN VDD VSS / RSC_IHPSG13_CINVX4 +XI5 ECLK_H_BOT ECLK_L_BOT VDD VSS / RSC_IHPSG13_CINVX2 +XI3<3> PADR<3> NADR<3> VDD VSS / RSC_IHPSG13_INVX2 +XI3<2> PADR<2> NADR<2> VDD VSS / RSC_IHPSG13_INVX2 +XI3<1> PADR<1> NADR<1> VDD VSS / RSC_IHPSG13_INVX2 +XI3<0> PADR<0> NADR<0> VDD VSS / RSC_IHPSG13_INVX2 +XI1<3> PADR<2> PADR<3> CS sel23<3> VDD VSS / RSC_IHPSG13_NAND3X2 +XI1<2> NADR<2> PADR<3> CS sel23<2> VDD VSS / RSC_IHPSG13_NAND3X2 +XI1<1> PADR<2> NADR<3> CS sel23<1> VDD VSS / RSC_IHPSG13_NAND3X2 +XI1<0> NADR<2> NADR<3> CS sel23<0> VDD VSS / RSC_IHPSG13_NAND3X2 +XI2<15> sel23<3> sel01<3> EN WL<15> VDD VSS / RSC_IHPSG13_NOR3X2 +XI2<14> sel23<3> sel01<2> EN WL<14> VDD VSS / RSC_IHPSG13_NOR3X2 +XI2<13> sel23<3> sel01<1> EN WL<13> VDD VSS / RSC_IHPSG13_NOR3X2 +XI2<12> sel23<3> sel01<0> EN WL<12> VDD VSS / RSC_IHPSG13_NOR3X2 +XI2<11> sel23<2> sel01<3> EN WL<11> VDD VSS / RSC_IHPSG13_NOR3X2 +XI2<10> sel23<2> sel01<2> EN WL<10> VDD VSS / RSC_IHPSG13_NOR3X2 +XI2<9> sel23<2> sel01<1> EN WL<9> VDD VSS / RSC_IHPSG13_NOR3X2 +XI2<8> sel23<2> sel01<0> EN WL<8> VDD VSS / RSC_IHPSG13_NOR3X2 +XI2<7> sel23<1> sel01<3> EN WL<7> VDD VSS / RSC_IHPSG13_NOR3X2 +XI2<6> sel23<1> sel01<2> EN WL<6> VDD VSS / RSC_IHPSG13_NOR3X2 +XI2<5> sel23<1> sel01<1> EN WL<5> VDD VSS / RSC_IHPSG13_NOR3X2 +XI2<4> sel23<1> sel01<0> EN WL<4> VDD VSS / RSC_IHPSG13_NOR3X2 +XI2<3> sel23<0> sel01<3> EN WL<3> VDD VSS / RSC_IHPSG13_NOR3X2 +XI2<2> sel23<0> sel01<2> EN WL<2> VDD VSS / RSC_IHPSG13_NOR3X2 +XI2<1> sel23<0> sel01<1> EN WL<1> VDD VSS / RSC_IHPSG13_NOR3X2 +XI2<0> sel23<0> sel01<0> EN WL<0> VDD VSS / RSC_IHPSG13_NOR3X2 +XCAPS4 VDD VSS / RSC_IHPSG13_FILLCAP4 +XI11 ECLK_L_BOT ECLK_L_TOP / RSC_IHPSG13_MET2RES +XR0 ECLK_H_BOT ECLK_H_TOP / RSC_IHPSG13_MET2RES +.ENDS +.SUBCKT RM_IHPSG13_512x32_c2_1P_ROWDEC4 ADDR_N_I<3> ADDR_N_I<2> ADDR_N_I<1> ADDR_N_I<0> ++ CS_I ECLK_I WL_O<15> WL_O<14> WL_O<13> WL_O<12> WL_O<11> WL_O<10> WL_O<9> ++ WL_O<8> WL_O<7> WL_O<6> WL_O<5> WL_O<4> WL_O<3> WL_O<2> WL_O<1> WL_O<0> ++ VDD VSS +XL2<8> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<7> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<6> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<5> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<4> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<3> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<2> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<1> VDD VSS / RSC_IHPSG13_FILLCAP8 +XSEL ADDR_N_I<3> ADDR_N_I<2> ADDR_N_I<1> ADDR_N_I<0> CS_I ECLK_I ECLK_H<1> ++ ECLK_B<0> ECLK_B<1> WL_O<15> WL_O<14> WL_O<13> WL_O<12> WL_O<11> WL_O<10> ++ WL_O<9> WL_O<8> WL_O<7> WL_O<6> WL_O<5> WL_O<4> WL_O<3> WL_O<2> WL_O<1> ++ WL_O<0> VDD VSS / RM_IHPSG13_512x32_c2_1P_DEC04 +.ENDS +.SUBCKT RSC_IHPSG13_CINVX8 A Z VDD VSS +MN0 Z A VSS VSS sg13_lv_nmos m=1 w=2.82u l=130.00n ng=4 nrd=0 nrs=0 +MP0 Z A VDD VDD sg13_lv_pmos m=1 w=6.48u l=130.00n ng=4 nrd=0 nrs=0 +.ENDS +.SUBCKT RSC_IHPSG13_DFNQMX2IX1 BE BI CN D QI QIN VDD VSS +MN15 net026 BI VSS VSS sg13_lv_nmos m=1 w=560.00n l=130.00n ng=1 nrd=0 ++ nrs=0 +MN14 MXI_OUT BE net026 VSS sg13_lv_nmos m=1 w=560.00n l=130.00n ng=1 nrd=0 ++ nrs=0 +MN1 net025 D VSS VSS sg13_lv_nmos m=1 w=560.00n l=130.00n ng=1 nrd=0 ++ nrs=0 +MN0 MXI_OUT BEN net025 VSS sg13_lv_nmos m=1 w=560.00n l=130.00n ng=1 nrd=0 ++ nrs=0 +MN10 QI CNN net21 VSS sg13_lv_nmos m=1 w=850.00n l=130.00n ng=1 nrd=0 nrs=0 +MN11 net21 QI_MS VSS VSS sg13_lv_nmos m=1 w=850.00n l=130.00n ng=1 ++ nrd=0 nrs=0 +MN7 net30 QI_MS VSS VSS sg13_lv_nmos m=1 w=480.00n l=130.00n ng=1 ++ nrd=0 nrs=0 +MN6 QIN_MS CNN net30 VSS sg13_lv_nmos m=1 w=480.00n l=130.00n ng=1 nrd=0 ++ nrs=0 +MN3 QI_MS QIN_MS VSS VSS sg13_lv_nmos m=1 w=480.00n l=130.00n ng=1 ++ nrd=0 nrs=0 +MN12 CNN CN VSS VSS sg13_lv_nmos m=1 w=495.000n l=130.00n ng=1 nrd=0 ++ nrs=0 +MN9 net37 MXI_OUT VSS VSS sg13_lv_nmos m=1 w=870.00n l=130.00n ng=1 ++ nrd=0 nrs=0 +MN8 QIN_MS CN net37 VSS sg13_lv_nmos m=1 w=870.00n l=130.00n ng=1 nrd=0 ++ nrs=0 +MN5 QI CN net25 VSS sg13_lv_nmos m=1 w=480.00n l=130.00n ng=1 nrd=0 nrs=0 +MN4 net25 QIN VSS VSS sg13_lv_nmos m=1 w=480.00n l=130.00n ng=1 nrd=0 ++ nrs=0 +MN2 QIN QI VSS VSS sg13_lv_nmos m=1 w=480.00n l=130.00n ng=1 nrd=0 ++ nrs=0 +MN13 BEN BE VSS VSS sg13_lv_nmos m=1 w=560.00n l=130.00n ng=1 nrd=0 ++ nrs=0 +MP15 MXI_OUT BEN net027 VDD sg13_lv_pmos m=1 w=985.000n l=130.00n ng=1 ++ nrd=0 nrs=0 +MP14 net027 BI VDD VDD sg13_lv_pmos m=1 w=985.000n l=130.00n ng=1 ++ nrd=0 nrs=0 +MP1 MXI_OUT BE net024 VDD sg13_lv_pmos m=1 w=985.000n l=130.00n ng=1 nrd=0 ++ nrs=0 +MP0 net024 D VDD VDD sg13_lv_pmos m=1 w=985.000n l=130.00n ng=1 nrd=0 ++ nrs=0 +MP13 BEN BE VDD VDD sg13_lv_pmos m=1 w=645.000n l=130.00n ng=1 nrd=0 ++ nrs=0 +MP6 QI_MS QIN_MS VDD VDD sg13_lv_pmos m=1 w=480.00n l=130.00n ng=1 ++ nrd=0 nrs=0 +MP3 QI CNN net27 VDD sg13_lv_pmos m=1 w=480.00n l=130.00n ng=1 nrd=0 nrs=0 +MP2 net27 QIN VDD VDD sg13_lv_pmos m=1 w=480.00n l=130.00n ng=1 nrd=0 ++ nrs=0 +MP10 net36 MXI_OUT VDD VDD sg13_lv_pmos m=1 w=975.000n l=130.00n ng=1 ++ nrd=0 nrs=0 +MP11 QIN_MS CNN net36 VDD sg13_lv_pmos m=1 w=975.000n l=130.00n ng=1 nrd=0 ++ nrs=0 +MP4 net32 QI_MS VDD VDD sg13_lv_pmos m=1 w=480.00n l=130.00n ng=1 ++ nrd=0 nrs=0 +MP5 QIN_MS CN net32 VDD sg13_lv_pmos m=1 w=480.00n l=130.00n ng=1 nrd=0 ++ nrs=0 +MP7 QIN QI VDD VDD sg13_lv_pmos m=1 w=480.00n l=130.00n ng=1 nrd=0 ++ nrs=0 +MP12 CNN CN VDD VDD sg13_lv_pmos m=1 w=480.00n l=130.00n ng=1 nrd=0 ++ nrs=0 +MP9 QI CN net19 VDD sg13_lv_pmos m=1 w=990.00n l=130.00n ng=1 nrd=0 nrs=0 +MP8 net19 QI_MS VDD VDD sg13_lv_pmos m=1 w=990.00n l=130.00n ng=1 ++ nrd=0 nrs=0 +.ENDS +.SUBCKT RM_IHPSG13_512x32_c2_1P_ROWREG4 ACLK_N_I ADDR_I<3> ADDR_I<2> ADDR_I<1> ADDR_I<0> ++ ADDR_N_O<3> ADDR_N_O<2> ADDR_N_O<1> ADDR_N_O<0> BIST_ADDR_I<3> ++ BIST_ADDR_I<2> BIST_ADDR_I<1> BIST_ADDR_I<0> BIST_EN_I VDD VSS +XINV<3> q_int<3> qn_int<3> VDD VSS / RSC_IHPSG13_CINVX2 +XINV<2> q_int<2> qn_int<2> VDD VSS / RSC_IHPSG13_CINVX2 +XINV<1> q_int<1> qn_int<1> VDD VSS / RSC_IHPSG13_CINVX2 +XINV<0> q_int<0> qn_int<0> VDD VSS / RSC_IHPSG13_CINVX2 +XDRV<3> qn_int<3> ADDR_N_O<3> VDD VSS / RSC_IHPSG13_CINVX8 +XDRV<2> qn_int<2> ADDR_N_O<2> VDD VSS / RSC_IHPSG13_CINVX8 +XDRV<1> qn_int<1> ADDR_N_O<1> VDD VSS / RSC_IHPSG13_CINVX8 +XDRV<0> qn_int<0> ADDR_N_O<0> VDD VSS / RSC_IHPSG13_CINVX8 +XDFF<3> BIST_EN_I BIST_ADDR_I<3> ACLK_N_I ADDR_I<3> q_int<3> net2<0> VDD ++ VSS / RSC_IHPSG13_DFNQMX2IX1 +XDFF<2> BIST_EN_I BIST_ADDR_I<2> ACLK_N_I ADDR_I<2> q_int<2> net2<1> VDD ++ VSS / RSC_IHPSG13_DFNQMX2IX1 +XDFF<1> BIST_EN_I BIST_ADDR_I<1> ACLK_N_I ADDR_I<1> q_int<1> net2<2> VDD ++ VSS / RSC_IHPSG13_DFNQMX2IX1 +XDFF<0> BIST_EN_I BIST_ADDR_I<0> ACLK_N_I ADDR_I<0> q_int<0> net2<3> VDD ++ VSS / RSC_IHPSG13_DFNQMX2IX1 +XI11<20> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI11<19> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI11<18> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI11<17> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI11<16> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI11<15> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI11<14> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI11<13> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI11<12> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI11<11> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI11<10> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI11<9> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI11<8> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI11<7> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI11<6> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI11<5> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI11<4> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI11<3> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI11<2> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI11<1> VDD VSS / RSC_IHPSG13_FILLCAP8 +.ENDS +.SUBCKT RSC_IHPSG13_CDLYX1 A Z VDD VSS +MN1 net010 net032 VSS VSS sg13_lv_nmos m=1 w=300.0n l=160.00n ng=1 ++ nrd=0 nrs=0 +MN2 net032 A net014 VSS sg13_lv_nmos m=1 w=300.0n l=160.00n ng=1 nrd=0 ++ nrs=0 +MN0 Z net032 net010 VSS sg13_lv_nmos m=1 w=300.0n l=160.00n ng=1 nrd=0 ++ nrs=0 +MN3 net014 A VSS VSS sg13_lv_nmos m=1 w=300.0n l=160.00n ng=1 nrd=0 ++ nrs=0 +MP1 Z net032 net07 VDD sg13_lv_pmos m=1 w=720.00n l=160.00n ng=1 nrd=0 ++ nrs=0 +MP3 net011 A VDD VDD sg13_lv_pmos m=1 w=720.00n l=160.00n ng=1 nrd=0 ++ nrs=0 +MP0 net07 net032 VDD VDD sg13_lv_pmos m=1 w=720.00n l=160.00n ng=1 ++ nrd=0 nrs=0 +MP2 net032 A net011 VDD sg13_lv_pmos m=1 w=720.00n l=160.00n ng=1 nrd=0 ++ nrs=0 +.ENDS +.SUBCKT RSC_IHPSG13_CDLYX1_DUMMY A Z VDD VSS +MN0 vss_r vdd_r VSS VSS sg13_lv_nmos m=1 w=2.49u l=300.0n ng=3 nrd=0 ++ nrs=0 +MP0 vdd_r vss_r VDD VDD sg13_lv_pmos m=1 w=3.24u l=640.00n ng=2 nrd=0 ++ nrs=0 +R0 Z A lvsres w=2.6e-07 l=6e-07 +.ENDS + +.SUBCKT RSC_IHPSG13_MX2IX1 A0 A1 S ZN VDD VSS +MP4 SN S VDD VDD sg13_lv_pmos m=1 w=645.000n l=130.00n ng=1 nrd=0 nrs=0 +MP3 ZN SN net12 VDD sg13_lv_pmos m=1 w=985.000n l=130.00n ng=1 nrd=0 nrs=0 +MP2 net12 A1 VDD VDD sg13_lv_pmos m=1 w=985.000n l=130.00n ng=1 nrd=0 ++ nrs=0 +MP1 ZN S net17 VDD sg13_lv_pmos m=1 w=985.000n l=130.00n ng=1 nrd=0 nrs=0 +MP0 net17 A0 VDD VDD sg13_lv_pmos m=1 w=985.000n l=130.00n ng=1 nrd=0 ++ nrs=0 +MN5 SN S VSS VSS sg13_lv_nmos m=1 w=480.00n l=130.00n ng=1 nrd=0 nrs=0 +MN3 net13 A1 VSS VSS sg13_lv_nmos m=1 w=480.00n l=130.00n ng=1 nrd=0 ++ nrs=0 +MN2 ZN S net13 VSS sg13_lv_nmos m=1 w=480.00n l=130.00n ng=1 nrd=0 nrs=0 +MN1 net15 A0 VSS VSS sg13_lv_nmos m=1 w=480.00n l=130.00n ng=1 nrd=0 ++ nrs=0 +MN0 ZN SN net15 VSS sg13_lv_nmos m=1 w=480.00n l=130.00n ng=1 nrd=0 nrs=0 +.ENDS +.SUBCKT RM_IHPSG13_512x32_c2_1P_DLY_MUX A SEL Z VDD VSS +XI11 net4 Z VDD VSS / RSC_IHPSG13_CINVX2 +XI8 A D<3> SEL net4 VDD VSS / RSC_IHPSG13_MX2IX1 +XI20<3> D<2> D<3> VDD VSS / RSC_IHPSG13_CDLYX1 +XI20<2> D<1> D<2> VDD VSS / RSC_IHPSG13_CDLYX1 +XI20<1> A D<1> VDD VSS / RSC_IHPSG13_CDLYX1 +.ENDS +.SUBCKT RSC_IHPSG13_DFNQX2 CN D Q VDD VSS +MN0 Q QIN_SL VSS VSS sg13_lv_nmos m=1 w=980.00n l=130.00n ng=1 nrd=0 ++ nrs=0 +MN10 QIN_SL CNN net21 VSS sg13_lv_nmos m=1 w=850.00n l=130.00n ng=1 nrd=0 ++ nrs=0 +MN11 net21 QI_MS VSS VSS sg13_lv_nmos m=1 w=850.00n l=130.00n ng=1 ++ nrd=0 nrs=0 +MN7 net30 QI_MS VSS VSS sg13_lv_nmos m=1 w=480.00n l=130.00n ng=1 ++ nrd=0 nrs=0 +MN6 QIN_MS CNN net30 VSS sg13_lv_nmos m=1 w=480.00n l=130.00n ng=1 nrd=0 ++ nrs=0 +MN3 QI_MS QIN_MS VSS VSS sg13_lv_nmos m=1 w=480.00n l=130.00n ng=1 ++ nrd=0 nrs=0 +MN12 CNN CN VSS VSS sg13_lv_nmos m=1 w=495.000n l=130.00n ng=1 nrd=0 ++ nrs=0 +MN9 net37 D VSS VSS sg13_lv_nmos m=1 w=870.00n l=130.00n ng=1 nrd=0 ++ nrs=0 +MN8 QIN_MS CN net37 VSS sg13_lv_nmos m=1 w=870.00n l=130.00n ng=1 nrd=0 ++ nrs=0 +MN5 QIN_SL CN net25 VSS sg13_lv_nmos m=1 w=480.00n l=130.00n ng=1 nrd=0 ++ nrs=0 +MN4 net25 QI_SL VSS VSS sg13_lv_nmos m=1 w=480.00n l=130.00n ng=1 ++ nrd=0 nrs=0 +MN2 QI_SL QIN_SL VSS VSS sg13_lv_nmos m=1 w=480.00n l=130.00n ng=1 ++ nrd=0 nrs=0 +MP0 Q QIN_SL VDD VDD sg13_lv_pmos m=1 w=1.62u l=130.00n ng=1 nrd=0 ++ nrs=0 +MP6 QI_MS QIN_MS VDD VDD sg13_lv_pmos m=1 w=480.00n l=130.00n ng=1 ++ nrd=0 nrs=0 +MP3 QIN_SL CNN net27 VDD sg13_lv_pmos m=1 w=480.00n l=130.00n ng=1 nrd=0 ++ nrs=0 +MP2 net27 QI_SL VDD VDD sg13_lv_pmos m=1 w=480.00n l=130.00n ng=1 ++ nrd=0 nrs=0 +MP10 net36 D VDD VDD sg13_lv_pmos m=1 w=975.000n l=130.00n ng=1 nrd=0 ++ nrs=0 +MP11 QIN_MS CNN net36 VDD sg13_lv_pmos m=1 w=975.000n l=130.00n ng=1 nrd=0 ++ nrs=0 +MP4 net32 QI_MS VDD VDD sg13_lv_pmos m=1 w=480.00n l=130.00n ng=1 ++ nrd=0 nrs=0 +MP5 QIN_MS CN net32 VDD sg13_lv_pmos m=1 w=480.00n l=130.00n ng=1 nrd=0 ++ nrs=0 +MP7 QI_SL QIN_SL VDD VDD sg13_lv_pmos m=1 w=480.00n l=130.00n ng=1 ++ nrd=0 nrs=0 +MP12 CNN CN VDD VDD sg13_lv_pmos m=1 w=480.00n l=130.00n ng=1 nrd=0 ++ nrs=0 +MP9 QIN_SL CN net19 VDD sg13_lv_pmos m=1 w=990.00n l=130.00n ng=1 nrd=0 ++ nrs=0 +MP8 net19 QI_MS VDD VDD sg13_lv_pmos m=1 w=990.00n l=130.00n ng=1 ++ nrd=0 nrs=0 +.ENDS +.SUBCKT RSC_IHPSG13_CNAND2X2 A B Z VDD VSS +MN0 Z B net6 VSS sg13_lv_nmos m=1 w=980.00n l=130.00n ng=1 nrd=0 nrs=0 +MN1 net6 A VSS VSS sg13_lv_nmos m=1 w=980.00n l=130.00n ng=1 nrd=0 ++ nrs=0 +MP1 Z B VDD VDD sg13_lv_pmos m=1 w=1.62u l=130.00n ng=1 nrd=0 nrs=0 +MP0 Z A VDD VDD sg13_lv_pmos m=1 w=1.62u l=130.00n ng=1 nrd=0 nrs=0 +.ENDS +.SUBCKT RSC_IHPSG13_CGATEPX4 CP E Q VDD VSS +MN1 net08 QIN VSS VSS sg13_lv_nmos m=1 w=480.00n l=130.00n ng=1 nrd=0 ++ nrs=0 +MN2 net019 net08 VSS VSS sg13_lv_nmos m=1 w=480.00n l=130.00n ng=1 ++ nrd=0 nrs=0 +MN3 QIN CP net019 VSS sg13_lv_nmos m=1 w=480.00n l=130.00n ng=1 nrd=0 nrs=0 +MN6 Q net015 VSS VSS sg13_lv_nmos m=1 w=1.41u l=130.00n ng=2 nrd=0 ++ nrs=0 +MN5 net015 net08 net018 VSS sg13_lv_nmos m=1 w=980.00n l=130.00n ng=1 ++ nrd=0 nrs=0 +MN8 QIN CPN net023 VSS sg13_lv_nmos m=1 w=870.00n l=130.00n ng=1 nrd=0 ++ nrs=0 +MN7 net023 E VSS VSS sg13_lv_nmos m=1 w=870.00n l=130.00n ng=1 nrd=0 ++ nrs=0 +MN4 net018 CP VSS VSS sg13_lv_nmos m=1 w=980.00n l=130.00n ng=1 nrd=0 ++ nrs=0 +MN0 CPN CP VSS VSS sg13_lv_nmos m=1 w=500.0n l=130.00n ng=1 nrd=0 nrs=0 +MP3 net08 QIN VDD VDD sg13_lv_pmos m=1 w=480.00n l=130.00n ng=1 nrd=0 ++ nrs=0 +MP2 QIN CPN net017 VDD sg13_lv_pmos m=1 w=480.00n l=130.00n ng=1 nrd=0 ++ nrs=0 +MP1 net017 net08 VDD VDD sg13_lv_pmos m=1 w=480.00n l=130.00n ng=1 ++ nrd=0 nrs=0 +MP0 CPN CP VDD VDD sg13_lv_pmos m=1 w=500.0n l=130.00n ng=1 nrd=0 nrs=0 +MP8 QIN CP net024 VDD sg13_lv_pmos m=1 w=975.000n l=130.00n ng=1 nrd=0 ++ nrs=0 +MP7 net024 E VDD VDD sg13_lv_pmos m=1 w=975.000n l=130.00n ng=1 nrd=0 ++ nrs=0 +MP4 net015 CP VDD VDD sg13_lv_pmos m=1 w=1.27u l=130.00n ng=1 nrd=0 ++ nrs=0 +MP6 Q net015 VDD VDD sg13_lv_pmos m=1 w=3.24u l=130.00n ng=2 nrd=0 ++ nrs=0 +MP5 net015 net08 VDD VDD sg13_lv_pmos m=1 w=1.27u l=130.00n ng=1 nrd=0 ++ nrs=0 +.ENDS +.SUBCKT RSC_IHPSG13_CBUFX8 A Z VDD VSS +MP0 net4 A VDD VDD sg13_lv_pmos m=1 w=3.24u l=130.00n ng=2 nrd=0 nrs=0 +MP1 Z net4 VDD VDD sg13_lv_pmos m=1 w=6.48u l=130.00n ng=4 nrd=0 nrs=0 +MN1 Z net4 VSS VSS sg13_lv_nmos m=1 w=2.82u l=130.00n ng=4 nrd=0 nrs=0 +MN0 net4 A VSS VSS sg13_lv_nmos m=1 w=1.41u l=130.00n ng=2 nrd=0 nrs=0 +.ENDS +.SUBCKT RSC_IHPSG13_CDLYX2 A Z VDD VSS +MN2 net4 A net9 VSS sg13_lv_nmos m=1 w=320.00n l=200.0n ng=1 nrd=0 nrs=0 +MN0 Z net4 VSS VSS sg13_lv_nmos m=1 w=705.000n l=130.00n ng=1 nrd=0 ++ nrs=0 +MN1 net9 A VSS VSS sg13_lv_nmos m=1 w=320.00n l=200.0n ng=1 nrd=0 nrs=0 +MP2 net4 A net10 VDD sg13_lv_pmos m=1 w=1.2u l=200.0n ng=1 nrd=0 nrs=0 +MP1 net10 A VDD VDD sg13_lv_pmos m=1 w=1.2u l=200.0n ng=1 nrd=0 nrs=0 +MP0 Z net4 VDD VDD sg13_lv_pmos m=1 w=1.62u l=130.00n ng=1 nrd=0 nrs=0 +.ENDS +.SUBCKT RSC_IHPSG13_MX2X2 A0 A1 S Z VDD VSS +MP6 Z net010 VDD VDD sg13_lv_pmos m=1 w=1.62u l=130.00n ng=1 nrd=0 ++ nrs=0 +MP4 SN S VDD VDD sg13_lv_pmos m=1 w=645.000n l=130.00n ng=1 nrd=0 nrs=0 +MP3 net010 SN net12 VDD sg13_lv_pmos m=1 w=985.000n l=130.00n ng=1 nrd=0 ++ nrs=0 +MP2 net12 A1 VDD VDD sg13_lv_pmos m=1 w=985.000n l=130.00n ng=1 nrd=0 ++ nrs=0 +MP1 net010 S net17 VDD sg13_lv_pmos m=1 w=985.000n l=130.00n ng=1 nrd=0 ++ nrs=0 +MP0 net17 A0 VDD VDD sg13_lv_pmos m=1 w=985.000n l=130.00n ng=1 nrd=0 ++ nrs=0 +MN6 Z net010 VSS VSS sg13_lv_nmos m=1 w=705.000n l=130.00n ng=1 nrd=0 ++ nrs=0 +MN5 SN S VSS VSS sg13_lv_nmos m=1 w=560.00n l=130.00n ng=1 nrd=0 nrs=0 +MN3 net13 A1 VSS VSS sg13_lv_nmos m=1 w=560.00n l=130.00n ng=1 nrd=0 ++ nrs=0 +MN2 net010 S net13 VSS sg13_lv_nmos m=1 w=560.00n l=130.00n ng=1 nrd=0 ++ nrs=0 +MN1 net15 A0 VSS VSS sg13_lv_nmos m=1 w=560.00n l=130.00n ng=1 nrd=0 ++ nrs=0 +MN0 net010 SN net15 VSS sg13_lv_nmos m=1 w=560.00n l=130.00n ng=1 nrd=0 ++ nrs=0 +.ENDS +.SUBCKT RSC_IHPSG13_AND2X2 A B Z VDD VSS +MN3 Z net6 VSS VSS sg13_lv_nmos m=1 w=980.00n l=130.00n ng=1 nrd=0 ++ nrs=0 +MN4 net9 B VSS VSS sg13_lv_nmos m=1 w=500.0n l=130.00n ng=1 nrd=0 nrs=0 +MN6 net6 A net9 VSS sg13_lv_nmos m=1 w=500.0n l=130.00n ng=1 nrd=0 nrs=0 +MP2 Z net6 VDD VDD sg13_lv_pmos m=1 w=1.62u l=130.00n ng=1 nrd=0 nrs=0 +MP0 net6 B VDD VDD sg13_lv_pmos m=1 w=860.00n l=130.00n ng=1 nrd=0 ++ nrs=0 +MP1 net6 A VDD VDD sg13_lv_pmos m=1 w=860.00n l=130.00n ng=1 nrd=0 ++ nrs=0 +.ENDS +.SUBCKT RSC_IHPSG13_TIEL Z VDD VSS +MN0 Z net2 VSS VSS sg13_lv_nmos m=1 w=480.00n l=130.00n ng=1 nrd=0 ++ nrs=0 +MP0 net2 net2 VDD VDD sg13_lv_pmos m=1 w=480.00n l=130.00n ng=1 nrd=0 ++ nrs=0 +.ENDS +.SUBCKT RSC_IHPSG13_XOR2X2 A B Z VDD VSS +MP8 net012 B net7 VDD sg13_lv_pmos m=1 w=825.000n l=130.00n ng=1 nrd=0 ++ nrs=0 +MP7 net011 net3 net012 VDD sg13_lv_pmos m=1 w=825.000n l=130.00n ng=1 ++ nrd=0 nrs=0 +MP6 Z net012 VDD VDD sg13_lv_pmos m=1 w=1.535u l=130.00n ng=1 nrd=0 ++ nrs=0 +MP2 net7 A VDD VDD sg13_lv_pmos m=1 w=825.000n l=130.00n ng=1 nrd=0 ++ nrs=0 +MP4 net011 net7 VDD VDD sg13_lv_pmos m=1 w=825.000n l=130.00n ng=1 ++ nrd=0 nrs=0 +MP5 net3 B VDD VDD sg13_lv_pmos m=1 w=580.00n l=130.00n ng=1 nrd=0 ++ nrs=0 +MN7 net012 B net011 VSS sg13_lv_nmos m=1 w=555.000n l=130.00n ng=1 nrd=0 ++ nrs=0 +MN6 net7 net3 net012 VSS sg13_lv_nmos m=1 w=555.000n l=130.00n ng=1 nrd=0 ++ nrs=0 +MN5 Z net012 VSS VSS sg13_lv_nmos m=1 w=775.000n l=130.00n ng=1 nrd=0 ++ nrs=0 +MN2 net7 A VSS VSS sg13_lv_nmos m=1 w=555.000n l=130.00n ng=1 nrd=0 ++ nrs=0 +MN4 net3 B VSS VSS sg13_lv_nmos m=1 w=480.00n l=130.00n ng=1 nrd=0 ++ nrs=0 +MN3 net011 net7 VSS VSS sg13_lv_nmos m=1 w=555.000n l=130.00n ng=1 ++ nrd=0 nrs=0 +.ENDS +.SUBCKT RSC_IHPSG13_OA12X1 A B C Z VDD VSS +MN2 net7 C VSS VSS sg13_lv_nmos m=1 w=980.00n l=130.00n ng=1 nrd=0 ++ nrs=0 +MN3 Z net17 VSS VSS sg13_lv_nmos m=1 w=500.0n l=130.00n ng=1 nrd=0 ++ nrs=0 +MN1 net17 B net7 VSS sg13_lv_nmos m=1 w=980.00n l=130.00n ng=1 nrd=0 nrs=0 +MN0 net17 A net7 VSS sg13_lv_nmos m=1 w=980.00n l=130.00n ng=1 nrd=0 nrs=0 +MP0 net24 A VDD VDD sg13_lv_pmos m=1 w=1.62u l=130.00n ng=1 nrd=0 nrs=0 +MP3 Z net17 VDD VDD sg13_lv_pmos m=1 w=905.000n l=130.00n ng=1 nrd=0 ++ nrs=0 +MP1 net17 B net24 VDD sg13_lv_pmos m=1 w=1.62u l=130.00n ng=1 nrd=0 nrs=0 +MP2 net17 C VDD VDD sg13_lv_pmos m=1 w=905.000n l=130.00n ng=1 nrd=0 ++ nrs=0 +.ENDS +.SUBCKT RM_IHPSG13_512x32_c2_1P_CTRL ACLK_N BIST_CK_I BIST_CS_I BIST_EN BIST_RE_I ++ BIST_WE_I B_TIEL_O CK_I CS_I DCLK ECLK PULSE_H PULSE_L PULSE_O RCLK RE_I ++ ROW_CS WCLK WE_I VDD VSS +XI17 ck_regs we col_we VDD VSS / RSC_IHPSG13_DFNQX2 +XI16 ck_regs re col_re VDD VSS / RSC_IHPSG13_DFNQX2 +XI18 ck_regs cs net7 VDD VSS / RSC_IHPSG13_DFNQX2 +XI71 ACLK_N net012 PULSE_O VDD VSS / RSC_IHPSG13_DFNQX2 +XI77 col_we net9 net016 VDD VSS / RSC_IHPSG13_CNAND2X2 +XI76 col_re net9 net018 VDD VSS / RSC_IHPSG13_CNAND2X2 +XI15 ck_dly WEorREandCS aclk VDD VSS / RSC_IHPSG13_CGATEPX4 +XI14 ck WEandCS DCLK VDD VSS / RSC_IHPSG13_CGATEPX4 +XI60 net7 ROW_CS VDD VSS / RSC_IHPSG13_CBUFX8 +XI73 PULSE_O net012 VDD VSS / RSC_IHPSG13_CINVX2 +XI8 net9 net8 VDD VSS / RSC_IHPSG13_CINVX2 +XI64 ck ck_dly VDD VSS / RSC_IHPSG13_CDLYX2 +XI86 CS_I BIST_CS_I BIST_EN cs VDD VSS / RSC_IHPSG13_MX2X2 +XI87 CK_I BIST_CK_I BIST_EN ck VDD VSS / RSC_IHPSG13_MX2X2 +XI85 WE_I BIST_WE_I BIST_EN we VDD VSS / RSC_IHPSG13_MX2X2 +XI84 RE_I BIST_RE_I BIST_EN re VDD VSS / RSC_IHPSG13_MX2X2 +XI22 we cs WEandCS VDD VSS / RSC_IHPSG13_AND2X2 +XBM_TIEL B_TIEL_O VDD VSS / RSC_IHPSG13_TIEL +XI48 ck_dly ck_regs VDD VSS / RSC_IHPSG13_CINVX4 +XI81 net016 WCLK VDD VSS / RSC_IHPSG13_CINVX4 +XI80 net018 RCLK VDD VSS / RSC_IHPSG13_CINVX4 +XI78 net8 net020 VDD VSS / RSC_IHPSG13_CINVX4 +XI6 PULSE_L PULSE_H net9 VDD VSS / RSC_IHPSG13_XOR2X2 +XI79 net020 ECLK VDD VSS / RSC_IHPSG13_CINVX8 +XI63 aclk ACLK_N VDD VSS / RSC_IHPSG13_CINVX8 +XI21 re we cs WEorREandCS VDD VSS / RSC_IHPSG13_OA12X1 +.ENDS +.SUBCKT RM_IHPSG13_512x32_c2_1P_COLDEC2 ACLK_N ADDR<1> ADDR<0> ADDR_COL<1> ADDR_COL<0> ++ ADDR_DEC<7> ADDR_DEC<6> ADDR_DEC<5> ADDR_DEC<4> ADDR_DEC<3> ADDR_DEC<2> ++ ADDR_DEC<1> ADDR_DEC<0> BIST_ADDR<1> BIST_ADDR<0> BIST_EN_I VDD VSS +XI14<5> VDD VSS / RSC_IHPSG13_FILLCAP4 +XI14<4> VDD VSS / RSC_IHPSG13_FILLCAP4 +XI14<3> VDD VSS / RSC_IHPSG13_FILLCAP4 +XI14<2> VDD VSS / RSC_IHPSG13_FILLCAP4 +XI14<1> VDD VSS / RSC_IHPSG13_FILLCAP4 +XDFF<1> BIST_EN_I BIST_ADDR<1> ACLK_N ADDR<1> padr_int<1> net6<0> VDD ++ VSS / RSC_IHPSG13_DFNQMX2IX1 +XDFF<0> BIST_EN_I BIST_ADDR<0> ACLK_N ADDR<0> padr_int<0> net6<1> VDD ++ VSS / RSC_IHPSG13_DFNQMX2IX1 +XI1<3> PADR<1> PADR<0> addr_n<3> VDD VSS / RSC_IHPSG13_NAND2X2 +XI1<2> PADR<1> NADR<0> addr_n<2> VDD VSS / RSC_IHPSG13_NAND2X2 +XI1<1> NADR<1> PADR<0> addr_n<1> VDD VSS / RSC_IHPSG13_NAND2X2 +XI1<0> NADR<1> NADR<0> addr_n<0> VDD VSS / RSC_IHPSG13_NAND2X2 +XI16<37> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI16<36> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI16<35> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI16<34> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI16<33> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI16<32> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI16<31> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI16<30> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI16<29> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI16<28> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI16<27> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI16<26> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI16<25> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI16<24> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI16<23> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI16<22> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI16<21> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI16<20> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI16<19> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI16<18> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI16<17> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI16<16> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI16<15> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI16<14> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI16<13> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI16<12> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI16<11> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI16<10> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI16<9> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI16<8> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI16<7> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI16<6> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI16<5> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI16<4> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI16<3> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI16<2> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI16<1> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI3<1> padr_int<1> NADR<1> VDD VSS / RSC_IHPSG13_INVX2 +XI3<0> padr_int<0> NADR<0> VDD VSS / RSC_IHPSG13_INVX2 +XI13<1> NADR<1> PADR<1> VDD VSS / RSC_IHPSG13_INVX2 +XI13<0> NADR<0> PADR<0> VDD VSS / RSC_IHPSG13_INVX2 +XI2<3> addr_n<3> ADDR_DEC<3> VDD VSS / RSC_IHPSG13_INVX2 +XI2<2> addr_n<2> ADDR_DEC<2> VDD VSS / RSC_IHPSG13_INVX2 +XI2<1> addr_n<1> ADDR_DEC<1> VDD VSS / RSC_IHPSG13_INVX2 +XI2<0> addr_n<0> ADDR_DEC<0> VDD VSS / RSC_IHPSG13_INVX2 +XI15<1> ADDR_COL<1> VDD VSS / RSC_IHPSG13_TIEL +XI15<0> ADDR_COL<0> VDD VSS / RSC_IHPSG13_TIEL +XI17<3> ADDR_DEC<7> VDD VSS / RSC_IHPSG13_TIEL +XI17<2> ADDR_DEC<6> VDD VSS / RSC_IHPSG13_TIEL +XI17<1> ADDR_DEC<5> VDD VSS / RSC_IHPSG13_TIEL +XI17<0> ADDR_DEC<4> VDD VSS / RSC_IHPSG13_TIEL +.ENDS +.SUBCKT RSC_IHPSG13_NOR2X2 A B Z VDD VSS +MP1 Z B net9 VDD sg13_lv_pmos m=1 w=1.62u l=130.00n ng=1 nrd=0 nrs=0 +MP0 net9 A VDD VDD sg13_lv_pmos m=1 w=1.62u l=130.00n ng=1 nrd=0 nrs=0 +MN0 Z B VSS VSS sg13_lv_nmos m=1 w=980.00n l=130.00n ng=1 nrd=0 nrs=0 +MN1 Z A VSS VSS sg13_lv_nmos m=1 w=980.00n l=130.00n ng=1 nrd=0 nrs=0 +.ENDS +.SUBCKT RSC_IHPSG13_CINVX4_WN A Z VDD VSS +MN0 Z A VSS VSS sg13_lv_nmos m=1 w=705.000n l=130.00n ng=1 nrd=0 nrs=0 +MP0 Z A VDD VDD sg13_lv_pmos m=1 w=3.24u l=130.00n ng=2 nrd=0 nrs=0 +.ENDS +.SUBCKT RM_IHPSG13_512x32_c2_1P_BLDRV BLC BLC_SEL BLT BLT_SEL PRE_N SEL_P WR_ONE WR_ZERO ++ VDD VSS +XCDEC SEL_P WR_ZERO BLC_PMOS_DRIVE VDD VSS / RSC_IHPSG13_NAND2X2 +XTDEC SEL_P WR_ONE BLT_PMOS_DRIVE VDD VSS / RSC_IHPSG13_NAND2X2 +MTWN BLT BLT_NMOS_DRIVE VSS VSS sg13_lv_nmos m=1 w=4.82u l=130.00n ++ ng=2 nrd=0 nrs=0 +MCWN BLC BLC_NMOS_DRIVE VSS VSS sg13_lv_nmos m=1 w=4.82u l=130.00n ++ ng=2 nrd=0 nrs=0 +MCWP BLC BLC_PMOS_DRIVE VDD VDD sg13_lv_pmos m=1 w=1.5u l=130.00n ng=1 ++ nrd=0 nrs=0 +MTWP BLT BLT_PMOS_DRIVE VDD VDD sg13_lv_pmos m=1 w=1.5u l=130.00n ng=1 ++ nrd=0 nrs=0 +MTSP BLT_SEL SEL_N BLT VDD sg13_lv_pmos m=1 w=1.5u l=130.00n ng=1 nrd=0 ++ nrs=0 +MTPR BLT PRE_N VDD VDD sg13_lv_pmos m=1 w=3.000u l=130.00n ng=2 nrd=0 ++ nrs=0 +MCSP BLC_SEL SEL_N BLC VDD sg13_lv_pmos m=1 w=1.5u l=130.00n ng=1 nrd=0 ++ nrs=0 +MCPR BLC PRE_N VDD VDD sg13_lv_pmos m=1 w=3.000u l=130.00n ng=2 nrd=0 ++ nrs=0 +XI86 SEL_P SEL_N VDD VSS / RSC_IHPSG13_INVX2 +XTINV BLC_PMOS_DRIVE BLT_NMOS_DRIVE VDD VSS / RSC_IHPSG13_INVX2 +XCINV BLT_PMOS_DRIVE BLC_NMOS_DRIVE VDD VSS / RSC_IHPSG13_INVX2 +.ENDS +.SUBCKT RSC_IHPSG13_TIEH Z VDD VSS +MN0 net2 net2 VSS VSS sg13_lv_nmos m=1 w=480.00n l=130.00n ng=1 nrd=0 ++ nrs=0 +MP0 Z net2 VDD VDD sg13_lv_pmos m=1 w=480.00n l=130.00n ng=1 nrd=0 ++ nrs=0 +.ENDS +.SUBCKT RSC_IHPSG13_MET3RES A B +R0 B A lvsres w=2.6e-07 l=6e-07 +.ENDS +.SUBCKT RSC_IHPSG13_DFPQD_MSAFFX2 CP DN DP QN QP VDD VSS +MN12 SN RN DIFFP VSS sg13_lv_nmos m=1 w=2.4u l=200.0n ng=2 nrd=0 nrs=0 +MN13 TAIL CP VSS VSS sg13_lv_nmos m=1 w=2.4u l=130.00n ng=2 nrd=0 nrs=0 +MN9 DIFFP DP TAIL VSS sg13_lv_nmos m=1 w=2.4u l=200.0n ng=2 nrd=0 nrs=0 +MN10 DIFFN DN TAIL VSS sg13_lv_nmos m=1 w=2.4u l=200.0n ng=2 nrd=0 nrs=0 +MN11 RN SN DIFFN VSS sg13_lv_nmos m=1 w=2.4u l=200.0n ng=2 nrd=0 nrs=0 +MN19 net33 SN VSS VSS sg13_lv_nmos m=1 w=980.00n l=130.00n ng=1 nrd=0 ++ nrs=0 +MN20 QN QP net37 VSS sg13_lv_nmos m=1 w=980.00n l=130.00n ng=1 nrd=0 nrs=0 +MN18 net37 RN VSS VSS sg13_lv_nmos m=1 w=980.00n l=130.00n ng=1 nrd=0 ++ nrs=0 +MN17 QP QN net33 VSS sg13_lv_nmos m=1 w=980.00n l=130.00n ng=1 nrd=0 nrs=0 +MP15 SN RN VDD VDD sg13_lv_pmos m=1 w=800.0n l=130.00n ng=1 nrd=0 nrs=0 +MP16 RN CP VDD VDD sg13_lv_pmos m=1 w=800.0n l=130.00n ng=1 nrd=0 nrs=0 +MP14 DIFFP CP VDD VDD sg13_lv_pmos m=1 w=800.0n l=130.00n ng=1 nrd=0 ++ nrs=0 +MP12 RN SN VDD VDD sg13_lv_pmos m=1 w=800.0n l=130.00n ng=1 nrd=0 nrs=0 +MP13 DIFFN CP VDD VDD sg13_lv_pmos m=1 w=800.0n l=130.00n ng=1 nrd=0 ++ nrs=0 +MP11 SN CP VDD VDD sg13_lv_pmos m=1 w=800.0n l=130.00n ng=1 nrd=0 nrs=0 +MP19 QN QP VDD VDD sg13_lv_pmos m=1 w=900.0n l=130.00n ng=1 nrd=0 nrs=0 +MP20 QP SN VDD VDD sg13_lv_pmos m=1 w=1.8u l=130.00n ng=2 nrd=0 nrs=0 +MP18 QN RN VDD VDD sg13_lv_pmos m=1 w=1.8u l=130.00n ng=2 nrd=0 nrs=0 +MP17 QP QN VDD VDD sg13_lv_pmos m=1 w=900.0n l=130.00n ng=1 nrd=0 nrs=0 +.ENDS +.SUBCKT RSC_IHPSG13_CBUFX2 A Z VDD VSS +MN1 Z net4 VSS VSS sg13_lv_nmos m=1 w=705.000n l=130.00n ng=1 nrd=0 ++ nrs=0 +MN0 net4 A VSS VSS sg13_lv_nmos m=1 w=540.00n l=130.00n ng=1 nrd=0 ++ nrs=0 +MP1 Z net4 VDD VDD sg13_lv_pmos m=1 w=1.62u l=130.00n ng=1 nrd=0 nrs=0 +MP0 net4 A VDD VDD sg13_lv_pmos m=1 w=1.1u l=130.00n ng=1 nrd=0 nrs=0 +.ENDS +.SUBCKT RSC_IHPSG13_INVX4 A Z VDD VSS +MN0 Z A VSS VSS sg13_lv_nmos m=1 w=1.96u l=130.00n ng=2 nrd=0 nrs=0 +MP0 Z A VDD VDD sg13_lv_pmos m=1 w=3.24u l=130.00n ng=2 nrd=0 nrs=0 +.ENDS +.SUBCKT RM_IHPSG13_512x32_c2_1P_COLCTRL2 A_ADDR_DEC<3> A_ADDR_DEC<2> A_ADDR_DEC<1> ++ A_ADDR_DEC<0> A_BIST_BM_I A_BIST_DW_I A_BIST_EN_I A_BLC<3> A_BLC<2> A_BLC<1> ++ A_BLC<0> A_BLT<3> A_BLT<2> A_BLT<1> A_BLT<0> A_BM_I A_DCLK_B_L A_DCLK_B_R ++ A_DCLK_L A_DCLK_R A_DR_O A_DW_I A_RCLK_B_L A_RCLK_B_R A_RCLK_L A_RCLK_R ++ A_TIEH_O A_WCLK_B_L A_WCLK_B_R A_WCLK_L A_WCLK_R VDD VSS +XA_DREG A_BIST_EN_I A_BIST_DW_I A_DCLK_B_L A_DW_I A_DI_R net22 VDD VSS ++ / RSC_IHPSG13_DFNQMX2IX1 +XA_BREG A_BIST_EN_I A_BIST_BM_I A_DCLK_B_L A_BM_I A_BM_R net23 VDD VSS ++ / RSC_IHPSG13_DFNQMX2IX1 +XA_CAPS<5> VDD VSS / RSC_IHPSG13_FILLCAP4 +XA_CAPS<4> VDD VSS / RSC_IHPSG13_FILLCAP4 +XA_CAPS<3> VDD VSS / RSC_IHPSG13_FILLCAP4 +XA_CAPS<2> VDD VSS / RSC_IHPSG13_FILLCAP4 +XA_CAPS<1> VDD VSS / RSC_IHPSG13_FILLCAP4 +XA_I80 A_WCLK_B_R A_RCLK_B_R net21 VDD VSS / RSC_IHPSG13_AND2X2 +XA_I75 A_DI_R A_DO_WRITE_P A_WR_ONE VDD VSS / RSC_IHPSG13_AND2X2 +XA_I76 A_DI_N A_DO_WRITE_P A_WR_ZERO VDD VSS / RSC_IHPSG13_AND2X2 +XA_I44 A_WCLK_B_R A_BM_N A_DO_WRITE_P VDD VSS / RSC_IHPSG13_NOR2X2 +XA_I81 net21 A_PRE_N VDD VSS / RSC_IHPSG13_CINVX4_WN +XA_BLTMUX<3> A_BLC<3> A_BLC_SEL A_BLT<3> A_BLT_SEL A_PRE_N A_ADDR_DEC<3> ++ A_WR_ONE A_WR_ZERO VDD VSS / RM_IHPSG13_512x32_c2_1P_BLDRV +XA_BLTMUX<2> A_BLC<2> A_BLC_SEL A_BLT<2> A_BLT_SEL A_PRE_N A_ADDR_DEC<2> ++ A_WR_ONE A_WR_ZERO VDD VSS / RM_IHPSG13_512x32_c2_1P_BLDRV +XA_BLTMUX<1> A_BLC<1> A_BLC_SEL A_BLT<1> A_BLT_SEL A_PRE_N A_ADDR_DEC<1> ++ A_WR_ONE A_WR_ZERO VDD VSS / RM_IHPSG13_512x32_c2_1P_BLDRV +XA_BLTMUX<0> A_BLC<0> A_BLC_SEL A_BLT<0> A_BLT_SEL A_PRE_N A_ADDR_DEC<0> ++ A_WR_ONE A_WR_ZERO VDD VSS / RM_IHPSG13_512x32_c2_1P_BLDRV +XA_BM_TIEH A_TIEH_O VDD VSS / RSC_IHPSG13_TIEH +XA_I89 A_DCLK_B_L A_DCLK_B_R / RSC_IHPSG13_MET3RES +XA_I88 A_DCLK_L A_DCLK_R / RSC_IHPSG13_MET3RES +XA_I87 A_WCLK_L A_WCLK_R / RSC_IHPSG13_MET3RES +XA_I91 A_RCLK_B_R A_RCLK_B_L / RSC_IHPSG13_MET3RES +XA_R2 A_RCLK_R A_RCLK_L / RSC_IHPSG13_MET3RES +XA_I90 A_WCLK_B_R A_WCLK_B_L / RSC_IHPSG13_MET3RES +XA_ISENSE A_SAE A_BLC_SEL A_BLT_SEL net19 net20 VDD VSS / ++ RSC_IHPSG13_DFPQD_MSAFFX2 +XA_I78 A_RCLK_B_R A_SAE VDD VSS / RSC_IHPSG13_CBUFX2 +XA_I83 A_BM_R A_BM_N VDD VSS / RSC_IHPSG13_INVX2 +XA_I49 A_DI_R A_DI_N VDD VSS / RSC_IHPSG13_INVX2 +XA_I51 net19 A_DR_O VDD VSS / RSC_IHPSG13_INVX4 +XA_I69 A_DCLK_L A_DCLK_B_L VDD VSS / RSC_IHPSG13_CINVX2 +XA_I50 A_WCLK_L A_WCLK_B_R VDD VSS / RSC_IHPSG13_CINVX2 +XA_EBUF A_RCLK_R A_RCLK_B_R VDD VSS / RSC_IHPSG13_CINVX2 +.ENDS +.SUBCKT RM_IHPSG13_512x32_c2_1P_COLDRV13_FILL4 VDD VSS +XI0<9> VDD VSS / RSC_IHPSG13_FILLCAP4 +XI0<8> VDD VSS / RSC_IHPSG13_FILLCAP4 +XI0<7> VDD VSS / RSC_IHPSG13_FILLCAP4 +XI0<6> VDD VSS / RSC_IHPSG13_FILLCAP4 +XI0<5> VDD VSS / RSC_IHPSG13_FILLCAP4 +XI0<4> VDD VSS / RSC_IHPSG13_FILLCAP4 +XI0<3> VDD VSS / RSC_IHPSG13_FILLCAP4 +XI0<2> VDD VSS / RSC_IHPSG13_FILLCAP4 +XI0<1> VDD VSS / RSC_IHPSG13_FILLCAP4 +.ENDS +.SUBCKT RM_IHPSG13_512x32_c2_1P_COLDRV13_FILL4C2 VDD VSS +XI0<2> VDD VSS / RSC_IHPSG13_FILLCAP4 +XI0<1> VDD VSS / RSC_IHPSG13_FILLCAP4 +.ENDS + + +.SUBCKT RM_IHPSG13_512x32_c2_1P_COLDEC4 ACLK_N ADDR<3> ADDR<2> ADDR<1> ADDR<0> ++ ADDR_COL<1> ADDR_COL<0> ADDR_DEC<7> ADDR_DEC<6> ADDR_DEC<5> ADDR_DEC<4> ++ ADDR_DEC<3> ADDR_DEC<2> ADDR_DEC<1> ADDR_DEC<0> BIST_ADDR<3> BIST_ADDR<2> ++ BIST_ADDR<1> BIST_ADDR<0> BIST_EN_I VDD VSS +XI15 ADDR_COL<1> VDD VSS / RSC_IHPSG13_TIEL +XI14 addr_int ADDR_COL<0> VDD VSS / RSC_IHPSG13_CBUFX2 +XDFF<3> BIST_EN_I BIST_ADDR<3> ACLK_N ADDR<3> addr_int net7<0> VDD VSS ++ / RSC_IHPSG13_DFNQMX2IX1 +XDFF<2> BIST_EN_I BIST_ADDR<2> ACLK_N ADDR<2> padr_int<2> net7<1> VDD ++ VSS / RSC_IHPSG13_DFNQMX2IX1 +XDFF<1> BIST_EN_I BIST_ADDR<1> ACLK_N ADDR<1> padr_int<1> net7<2> VDD ++ VSS / RSC_IHPSG13_DFNQMX2IX1 +XDFF<0> BIST_EN_I BIST_ADDR<0> ACLK_N ADDR<0> padr_int<0> net7<3> VDD ++ VSS / RSC_IHPSG13_DFNQMX2IX1 +XI1<7> PADR<0> PADR<1> PADR<2> addr_n<7> VDD VSS / RSC_IHPSG13_NAND3X2 +XI1<6> NADR<0> PADR<1> PADR<2> addr_n<6> VDD VSS / RSC_IHPSG13_NAND3X2 +XI1<5> PADR<0> NADR<1> PADR<2> addr_n<5> VDD VSS / RSC_IHPSG13_NAND3X2 +XI1<4> NADR<0> NADR<1> PADR<2> addr_n<4> VDD VSS / RSC_IHPSG13_NAND3X2 +XI1<3> PADR<0> PADR<1> NADR<2> addr_n<3> VDD VSS / RSC_IHPSG13_NAND3X2 +XI1<2> NADR<0> PADR<1> NADR<2> addr_n<2> VDD VSS / RSC_IHPSG13_NAND3X2 +XI1<1> PADR<0> NADR<1> NADR<2> addr_n<1> VDD VSS / RSC_IHPSG13_NAND3X2 +XI1<0> NADR<0> NADR<1> NADR<2> addr_n<0> VDD VSS / RSC_IHPSG13_NAND3X2 +XI13<2> NADR<2> PADR<2> VDD VSS / RSC_IHPSG13_INVX2 +XI13<1> NADR<1> PADR<1> VDD VSS / RSC_IHPSG13_INVX2 +XI13<0> NADR<0> PADR<0> VDD VSS / RSC_IHPSG13_INVX2 +XI3<2> padr_int<2> NADR<2> VDD VSS / RSC_IHPSG13_INVX2 +XI3<1> padr_int<1> NADR<1> VDD VSS / RSC_IHPSG13_INVX2 +XI3<0> padr_int<0> NADR<0> VDD VSS / RSC_IHPSG13_INVX2 +XI2<7> addr_n<7> ADDR_DEC<7> VDD VSS / RSC_IHPSG13_INVX2 +XI2<6> addr_n<6> ADDR_DEC<6> VDD VSS / RSC_IHPSG13_INVX2 +XI2<5> addr_n<5> ADDR_DEC<5> VDD VSS / RSC_IHPSG13_INVX2 +XI2<4> addr_n<4> ADDR_DEC<4> VDD VSS / RSC_IHPSG13_INVX2 +XI2<3> addr_n<3> ADDR_DEC<3> VDD VSS / RSC_IHPSG13_INVX2 +XI2<2> addr_n<2> ADDR_DEC<2> VDD VSS / RSC_IHPSG13_INVX2 +XI2<1> addr_n<1> ADDR_DEC<1> VDD VSS / RSC_IHPSG13_INVX2 +XI2<0> addr_n<0> ADDR_DEC<0> VDD VSS / RSC_IHPSG13_INVX2 +XI16<3> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI16<2> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI16<1> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI17<2> VDD VSS / RSC_IHPSG13_FILLCAP4 +XI17<1> VDD VSS / RSC_IHPSG13_FILLCAP4 +.ENDS +.SUBCKT RSC_IHPSG13_AND2X4 A B Z VDD VSS +MN3 Z net6 VSS VSS sg13_lv_nmos m=1 w=1.96u l=130.00n ng=2 nrd=0 nrs=0 +MN4 net9 B VSS VSS sg13_lv_nmos m=1 w=500.0n l=130.00n ng=1 nrd=0 nrs=0 +MN6 net6 A net9 VSS sg13_lv_nmos m=1 w=500.0n l=130.00n ng=1 nrd=0 nrs=0 +MP2 Z net6 VDD VDD sg13_lv_pmos m=1 w=3.24u l=130.00n ng=2 nrd=0 nrs=0 +MP0 net6 B VDD VDD sg13_lv_pmos m=1 w=860.00n l=130.00n ng=1 nrd=0 ++ nrs=0 +MP1 net6 A VDD VDD sg13_lv_pmos m=1 w=860.00n l=130.00n ng=1 nrd=0 ++ nrs=0 +.ENDS +.SUBCKT RM_IHPSG13_512x32_c2_1P_COLCTRL4 A_ADDR_COL A_ADDR_DEC<7> A_ADDR_DEC<6> ++ A_ADDR_DEC<5> A_ADDR_DEC<4> A_ADDR_DEC<3> A_ADDR_DEC<2> A_ADDR_DEC<1> ++ A_ADDR_DEC<0> A_BIST_BM_I A_BIST_DW_I A_BIST_EN_I A_BLC<15> A_BLC<14> ++ A_BLC<13> A_BLC<12> A_BLC<11> A_BLC<10> A_BLC<9> A_BLC<8> A_BLC<7> A_BLC<6> ++ A_BLC<5> A_BLC<4> A_BLC<3> A_BLC<2> A_BLC<1> A_BLC<0> A_BLT<15> A_BLT<14> ++ A_BLT<13> A_BLT<12> A_BLT<11> A_BLT<10> A_BLT<9> A_BLT<8> A_BLT<7> A_BLT<6> ++ A_BLT<5> A_BLT<4> A_BLT<3> A_BLT<2> A_BLT<1> A_BLT<0> A_BM_I A_DCLK_B_L ++ A_DCLK_B_R A_DCLK_L A_DCLK_R A_DR_O A_DW_I A_RCLK_B_L A_RCLK_B_R A_RCLK_L ++ A_RCLK_R A_TIEH_O A_WCLK_B_L A_WCLK_B_R A_WCLK_L A_WCLK_R VDD VSS +XA_I80 A_WCLK_B_L A_RCLK_B_L net21 VDD VSS / RSC_IHPSG13_AND2X2 +XA_I76 A_DO_WRITE_P A_DI_N A_WR_ZERO VDD VSS / RSC_IHPSG13_AND2X4 +XA_I75 A_DI_R A_DO_WRITE_P A_WR_ONE VDD VSS / RSC_IHPSG13_AND2X4 +XA_CAPS<8> VDD VSS / RSC_IHPSG13_FILLCAP4 +XA_CAPS<7> VDD VSS / RSC_IHPSG13_FILLCAP4 +XA_CAPS<6> VDD VSS / RSC_IHPSG13_FILLCAP4 +XA_CAPS<5> VDD VSS / RSC_IHPSG13_FILLCAP4 +XA_CAPS<4> VDD VSS / RSC_IHPSG13_FILLCAP4 +XA_CAPS<3> VDD VSS / RSC_IHPSG13_FILLCAP4 +XA_CAPS<2> VDD VSS / RSC_IHPSG13_FILLCAP4 +XA_CAPS<1> VDD VSS / RSC_IHPSG13_FILLCAP4 +XA_I69 A_DCLK_L A_DCLK_B_L VDD VSS / RSC_IHPSG13_CINVX4 +XA_I50 A_WCLK_L A_WCLK_B_L VDD VSS / RSC_IHPSG13_CINVX4 +XA_EBUF A_RCLK_L A_RCLK_B_L VDD VSS / RSC_IHPSG13_CINVX4 +XA_INV<1> A_N0 A_P0 VDD VSS / RSC_IHPSG13_CINVX4 +XA_INV<0> A_ADDR_COL A_N0 VDD VSS / RSC_IHPSG13_CINVX4 +XA_I81<1> net21 A_PRE_N VDD VSS / RSC_IHPSG13_CINVX4_WN +XA_I81<0> net21 A_PRE_N VDD VSS / RSC_IHPSG13_CINVX4_WN +XA_BLTMUX<15> A_BLC<15> A_BLC_SEL A_BLT<15> A_BLT_SEL A_PRE_N A_SEL_P<15> ++ A_WR_ONE A_WR_ZERO VDD VSS / RM_IHPSG13_512x32_c2_1P_BLDRV +XA_BLTMUX<14> A_BLC<14> A_BLC_SEL A_BLT<14> A_BLT_SEL A_PRE_N A_SEL_P<14> ++ A_WR_ONE A_WR_ZERO VDD VSS / RM_IHPSG13_512x32_c2_1P_BLDRV +XA_BLTMUX<13> A_BLC<13> A_BLC_SEL A_BLT<13> A_BLT_SEL A_PRE_N A_SEL_P<13> ++ A_WR_ONE A_WR_ZERO VDD VSS / RM_IHPSG13_512x32_c2_1P_BLDRV +XA_BLTMUX<12> A_BLC<12> A_BLC_SEL A_BLT<12> A_BLT_SEL A_PRE_N A_SEL_P<12> ++ A_WR_ONE A_WR_ZERO VDD VSS / RM_IHPSG13_512x32_c2_1P_BLDRV +XA_BLTMUX<11> A_BLC<11> A_BLC_SEL A_BLT<11> A_BLT_SEL A_PRE_N A_SEL_P<11> ++ A_WR_ONE A_WR_ZERO VDD VSS / RM_IHPSG13_512x32_c2_1P_BLDRV +XA_BLTMUX<10> A_BLC<10> A_BLC_SEL A_BLT<10> A_BLT_SEL A_PRE_N A_SEL_P<10> ++ A_WR_ONE A_WR_ZERO VDD VSS / RM_IHPSG13_512x32_c2_1P_BLDRV +XA_BLTMUX<9> A_BLC<9> A_BLC_SEL A_BLT<9> A_BLT_SEL A_PRE_N A_SEL_P<9> A_WR_ONE ++ A_WR_ZERO VDD VSS / RM_IHPSG13_512x32_c2_1P_BLDRV +XA_BLTMUX<8> A_BLC<8> A_BLC_SEL A_BLT<8> A_BLT_SEL A_PRE_N A_SEL_P<8> A_WR_ONE ++ A_WR_ZERO VDD VSS / RM_IHPSG13_512x32_c2_1P_BLDRV +XA_BLTMUX<7> A_BLC<7> A_BLC_SEL A_BLT<7> A_BLT_SEL A_PRE_N A_SEL_P<7> A_WR_ONE ++ A_WR_ZERO VDD VSS / RM_IHPSG13_512x32_c2_1P_BLDRV +XA_BLTMUX<6> A_BLC<6> A_BLC_SEL A_BLT<6> A_BLT_SEL A_PRE_N A_SEL_P<6> A_WR_ONE ++ A_WR_ZERO VDD VSS / RM_IHPSG13_512x32_c2_1P_BLDRV +XA_BLTMUX<5> A_BLC<5> A_BLC_SEL A_BLT<5> A_BLT_SEL A_PRE_N A_SEL_P<5> A_WR_ONE ++ A_WR_ZERO VDD VSS / RM_IHPSG13_512x32_c2_1P_BLDRV +XA_BLTMUX<4> A_BLC<4> A_BLC_SEL A_BLT<4> A_BLT_SEL A_PRE_N A_SEL_P<4> A_WR_ONE ++ A_WR_ZERO VDD VSS / RM_IHPSG13_512x32_c2_1P_BLDRV +XA_BLTMUX<3> A_BLC<3> A_BLC_SEL A_BLT<3> A_BLT_SEL A_PRE_N A_SEL_P<3> A_WR_ONE ++ A_WR_ZERO VDD VSS / RM_IHPSG13_512x32_c2_1P_BLDRV +XA_BLTMUX<2> A_BLC<2> A_BLC_SEL A_BLT<2> A_BLT_SEL A_PRE_N A_SEL_P<2> A_WR_ONE ++ A_WR_ZERO VDD VSS / RM_IHPSG13_512x32_c2_1P_BLDRV +XA_BLTMUX<1> A_BLC<1> A_BLC_SEL A_BLT<1> A_BLT_SEL A_PRE_N A_SEL_P<1> A_WR_ONE ++ A_WR_ZERO VDD VSS / RM_IHPSG13_512x32_c2_1P_BLDRV +XA_BLTMUX<0> A_BLC<0> A_BLC_SEL A_BLT<0> A_BLT_SEL A_PRE_N A_SEL_P<0> A_WR_ONE ++ A_WR_ZERO VDD VSS / RM_IHPSG13_512x32_c2_1P_BLDRV +XA_R2 A_RCLK_L A_RCLK_R / RSC_IHPSG13_MET3RES +XA_I87 A_WCLK_L A_WCLK_R / RSC_IHPSG13_MET3RES +XA_I88 A_DCLK_L A_DCLK_R / RSC_IHPSG13_MET3RES +XA_I89 A_DCLK_B_L A_DCLK_B_R / RSC_IHPSG13_MET3RES +XA_I90 A_WCLK_B_L A_WCLK_B_R / RSC_IHPSG13_MET3RES +XA_I91 A_RCLK_B_L A_RCLK_B_R / RSC_IHPSG13_MET3RES +XA_ISENSE A_SAE A_BLC_SEL A_BLT_SEL net19 net20 VDD VSS / ++ RSC_IHPSG13_DFPQD_MSAFFX2 +XA_I51 net19 A_DR_O VDD VSS / RSC_IHPSG13_INVX4 +XA_I78 A_RCLK_B_L A_SAE VDD VSS / RSC_IHPSG13_CBUFX2 +XA_DREG A_BIST_EN_I A_BIST_DW_I A_DCLK_B_L A_DW_I A_DI_R net22 VDD VSS ++ / RSC_IHPSG13_DFNQMX2IX1 +XA_BREG A_BIST_EN_I A_BIST_BM_I A_DCLK_B_L A_BM_I A_BM_R net24 VDD VSS ++ / RSC_IHPSG13_DFNQMX2IX1 +XA_DEC3INV<15> net23<0> A_SEL_P<15> VDD VSS / RSC_IHPSG13_INVX2 +XA_DEC3INV<14> net23<1> A_SEL_P<14> VDD VSS / RSC_IHPSG13_INVX2 +XA_DEC3INV<13> net23<2> A_SEL_P<13> VDD VSS / RSC_IHPSG13_INVX2 +XA_DEC3INV<12> net23<3> A_SEL_P<12> VDD VSS / RSC_IHPSG13_INVX2 +XA_DEC3INV<11> net23<4> A_SEL_P<11> VDD VSS / RSC_IHPSG13_INVX2 +XA_DEC3INV<10> net23<5> A_SEL_P<10> VDD VSS / RSC_IHPSG13_INVX2 +XA_DEC3INV<9> net23<6> A_SEL_P<9> VDD VSS / RSC_IHPSG13_INVX2 +XA_DEC3INV<8> net23<7> A_SEL_P<8> VDD VSS / RSC_IHPSG13_INVX2 +XA_DEC3INV<7> net23<8> A_SEL_P<7> VDD VSS / RSC_IHPSG13_INVX2 +XA_DEC3INV<6> net23<9> A_SEL_P<6> VDD VSS / RSC_IHPSG13_INVX2 +XA_DEC3INV<5> net23<10> A_SEL_P<5> VDD VSS / RSC_IHPSG13_INVX2 +XA_DEC3INV<4> net23<11> A_SEL_P<4> VDD VSS / RSC_IHPSG13_INVX2 +XA_DEC3INV<3> net23<12> A_SEL_P<3> VDD VSS / RSC_IHPSG13_INVX2 +XA_DEC3INV<2> net23<13> A_SEL_P<2> VDD VSS / RSC_IHPSG13_INVX2 +XA_DEC3INV<1> net23<14> A_SEL_P<1> VDD VSS / RSC_IHPSG13_INVX2 +XA_DEC3INV<0> net23<15> A_SEL_P<0> VDD VSS / RSC_IHPSG13_INVX2 +XA_I83 A_BM_R A_BM_N VDD VSS / RSC_IHPSG13_INVX2 +XA_I49 A_DI_R A_DI_N VDD VSS / RSC_IHPSG13_INVX2 +XA_I70<4> VDD VSS / RSC_IHPSG13_FILLCAP8 +XA_I70<3> VDD VSS / RSC_IHPSG13_FILLCAP8 +XA_I70<2> VDD VSS / RSC_IHPSG13_FILLCAP8 +XA_I70<1> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI73<14> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI73<13> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI73<12> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI73<11> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI73<10> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI73<9> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI73<8> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI73<7> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI73<6> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI73<5> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI73<4> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI73<3> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI73<2> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI73<1> VDD VSS / RSC_IHPSG13_FILLCAP8 +XA_I44 A_BM_N A_WCLK_B_L A_DO_WRITE_P VDD VSS / RSC_IHPSG13_NOR2X2 +XA_DEC3<15> A_P0 A_ADDR_DEC<7> net23<0> VDD VSS / RSC_IHPSG13_NAND2X2 +XA_DEC3<14> A_P0 A_ADDR_DEC<6> net23<1> VDD VSS / RSC_IHPSG13_NAND2X2 +XA_DEC3<13> A_P0 A_ADDR_DEC<5> net23<2> VDD VSS / RSC_IHPSG13_NAND2X2 +XA_DEC3<12> A_P0 A_ADDR_DEC<4> net23<3> VDD VSS / RSC_IHPSG13_NAND2X2 +XA_DEC3<11> A_P0 A_ADDR_DEC<3> net23<4> VDD VSS / RSC_IHPSG13_NAND2X2 +XA_DEC3<10> A_P0 A_ADDR_DEC<2> net23<5> VDD VSS / RSC_IHPSG13_NAND2X2 +XA_DEC3<9> A_P0 A_ADDR_DEC<1> net23<6> VDD VSS / RSC_IHPSG13_NAND2X2 +XA_DEC3<8> A_P0 A_ADDR_DEC<0> net23<7> VDD VSS / RSC_IHPSG13_NAND2X2 +XA_DEC3<7> A_N0 A_ADDR_DEC<7> net23<8> VDD VSS / RSC_IHPSG13_NAND2X2 +XA_DEC3<6> A_N0 A_ADDR_DEC<6> net23<9> VDD VSS / RSC_IHPSG13_NAND2X2 +XA_DEC3<5> A_N0 A_ADDR_DEC<5> net23<10> VDD VSS / RSC_IHPSG13_NAND2X2 +XA_DEC3<4> A_N0 A_ADDR_DEC<4> net23<11> VDD VSS / RSC_IHPSG13_NAND2X2 +XA_DEC3<3> A_N0 A_ADDR_DEC<3> net23<12> VDD VSS / RSC_IHPSG13_NAND2X2 +XA_DEC3<2> A_N0 A_ADDR_DEC<2> net23<13> VDD VSS / RSC_IHPSG13_NAND2X2 +XA_DEC3<1> A_N0 A_ADDR_DEC<1> net23<14> VDD VSS / RSC_IHPSG13_NAND2X2 +XA_DEC3<0> A_N0 A_ADDR_DEC<0> net23<15> VDD VSS / RSC_IHPSG13_NAND2X2 +XA_BM_TIEH A_TIEH_O VDD VSS / RSC_IHPSG13_TIEH +.ENDS + + +.SUBCKT RM_IHPSG13_512x32_c2_1P_COLDEC3 ACLK_N ADDR<2> ADDR<1> ADDR<0> ADDR_COL<1> ++ ADDR_COL<0> ADDR_DEC<7> ADDR_DEC<6> ADDR_DEC<5> ADDR_DEC<4> ADDR_DEC<3> ++ ADDR_DEC<2> ADDR_DEC<1> ADDR_DEC<0> BIST_ADDR<2> BIST_ADDR<1> BIST_ADDR<0> ++ BIST_EN_I VDD VSS +XI15<1> ADDR_COL<1> VDD VSS / RSC_IHPSG13_TIEL +XI15<0> ADDR_COL<0> VDD VSS / RSC_IHPSG13_TIEL +XI1<7> PADR<0> PADR<1> PADR<2> addr_n<7> VDD VSS / RSC_IHPSG13_NAND3X2 +XI1<6> NADR<0> PADR<1> PADR<2> addr_n<6> VDD VSS / RSC_IHPSG13_NAND3X2 +XI1<5> PADR<0> NADR<1> PADR<2> addr_n<5> VDD VSS / RSC_IHPSG13_NAND3X2 +XI1<4> NADR<0> NADR<1> PADR<2> addr_n<4> VDD VSS / RSC_IHPSG13_NAND3X2 +XI1<3> PADR<0> PADR<1> NADR<2> addr_n<3> VDD VSS / RSC_IHPSG13_NAND3X2 +XI1<2> NADR<0> PADR<1> NADR<2> addr_n<2> VDD VSS / RSC_IHPSG13_NAND3X2 +XI1<1> PADR<0> NADR<1> NADR<2> addr_n<1> VDD VSS / RSC_IHPSG13_NAND3X2 +XI1<0> NADR<0> NADR<1> NADR<2> addr_n<0> VDD VSS / RSC_IHPSG13_NAND3X2 +XDFF<2> BIST_EN_I BIST_ADDR<2> ACLK_N ADDR<2> padr_int<2> net6<0> VDD ++ VSS / RSC_IHPSG13_DFNQMX2IX1 +XDFF<1> BIST_EN_I BIST_ADDR<1> ACLK_N ADDR<1> padr_int<1> net6<1> VDD ++ VSS / RSC_IHPSG13_DFNQMX2IX1 +XDFF<0> BIST_EN_I BIST_ADDR<0> ACLK_N ADDR<0> padr_int<0> net6<2> VDD ++ VSS / RSC_IHPSG13_DFNQMX2IX1 +XI17<2> VDD VSS / RSC_IHPSG13_FILLCAP4 +XI17<1> VDD VSS / RSC_IHPSG13_FILLCAP4 +XI13<2> NADR<2> PADR<2> VDD VSS / RSC_IHPSG13_INVX2 +XI13<1> NADR<1> PADR<1> VDD VSS / RSC_IHPSG13_INVX2 +XI13<0> NADR<0> PADR<0> VDD VSS / RSC_IHPSG13_INVX2 +XI3<2> padr_int<2> NADR<2> VDD VSS / RSC_IHPSG13_INVX2 +XI3<1> padr_int<1> NADR<1> VDD VSS / RSC_IHPSG13_INVX2 +XI3<0> padr_int<0> NADR<0> VDD VSS / RSC_IHPSG13_INVX2 +XI2<7> addr_n<7> ADDR_DEC<7> VDD VSS / RSC_IHPSG13_INVX2 +XI2<6> addr_n<6> ADDR_DEC<6> VDD VSS / RSC_IHPSG13_INVX2 +XI2<5> addr_n<5> ADDR_DEC<5> VDD VSS / RSC_IHPSG13_INVX2 +XI2<4> addr_n<4> ADDR_DEC<4> VDD VSS / RSC_IHPSG13_INVX2 +XI2<3> addr_n<3> ADDR_DEC<3> VDD VSS / RSC_IHPSG13_INVX2 +XI2<2> addr_n<2> ADDR_DEC<2> VDD VSS / RSC_IHPSG13_INVX2 +XI2<1> addr_n<1> ADDR_DEC<1> VDD VSS / RSC_IHPSG13_INVX2 +XI2<0> addr_n<0> ADDR_DEC<0> VDD VSS / RSC_IHPSG13_INVX2 +XI16<6> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI16<5> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI16<4> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI16<3> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI16<2> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI16<1> VDD VSS / RSC_IHPSG13_FILLCAP8 +.ENDS +.SUBCKT RM_IHPSG13_512x32_c2_1P_COLCTRL3 A_ADDR_DEC<7> A_ADDR_DEC<6> A_ADDR_DEC<5> ++ A_ADDR_DEC<4> A_ADDR_DEC<3> A_ADDR_DEC<2> A_ADDR_DEC<1> A_ADDR_DEC<0> ++ A_BIST_BM_I A_BIST_DW_I A_BIST_EN_I A_BLC<7> A_BLC<6> A_BLC<5> A_BLC<4> ++ A_BLC<3> A_BLC<2> A_BLC<1> A_BLC<0> A_BLT<7> A_BLT<6> A_BLT<5> A_BLT<4> ++ A_BLT<3> A_BLT<2> A_BLT<1> A_BLT<0> A_BM_I A_DCLK_B_L A_DCLK_B_R A_DCLK_L ++ A_DCLK_R A_DR_O A_DW_I A_RCLK_B_L A_RCLK_B_R A_RCLK_L A_RCLK_R A_TIEH_O ++ A_WCLK_B_L A_WCLK_B_R A_WCLK_L A_WCLK_R VDD VSS +XA_DREG A_BIST_EN_I A_BIST_DW_I A_DCLK_B_L A_DW_I A_DI_R net22 VDD VSS ++ / RSC_IHPSG13_DFNQMX2IX1 +XA_BREG A_BIST_EN_I A_BIST_BM_I A_DCLK_B_R A_BM_I A_BM_R net23 VDD VSS ++ / RSC_IHPSG13_DFNQMX2IX1 +XA_I70<8> VDD VSS / RSC_IHPSG13_FILLCAP8 +XA_I70<7> VDD VSS / RSC_IHPSG13_FILLCAP8 +XA_I70<6> VDD VSS / RSC_IHPSG13_FILLCAP8 +XA_I70<5> VDD VSS / RSC_IHPSG13_FILLCAP8 +XA_I70<4> VDD VSS / RSC_IHPSG13_FILLCAP8 +XA_I70<3> VDD VSS / RSC_IHPSG13_FILLCAP8 +XA_I70<2> VDD VSS / RSC_IHPSG13_FILLCAP8 +XA_I70<1> VDD VSS / RSC_IHPSG13_FILLCAP8 +XA_I51 net19 A_DR_O VDD VSS / RSC_IHPSG13_INVX4 +XA_I44 A_BM_N A_WCLK_B_R A_DO_WRITE_P VDD VSS / RSC_IHPSG13_NOR2X2 +XA_BM_TIEH A_TIEH_O VDD VSS / RSC_IHPSG13_TIEH +XA_BLTMUX<7> A_BLC<7> A_BLC_SEL A_BLT<7> A_BLT_SEL A_PRE_N A_ADDR_DEC<7> ++ A_WR_ONE A_WR_ZERO VDD VSS / RM_IHPSG13_512x32_c2_1P_BLDRV +XA_BLTMUX<6> A_BLC<6> A_BLC_SEL A_BLT<6> A_BLT_SEL A_PRE_N A_ADDR_DEC<6> ++ A_WR_ONE A_WR_ZERO VDD VSS / RM_IHPSG13_512x32_c2_1P_BLDRV +XA_BLTMUX<5> A_BLC<5> A_BLC_SEL A_BLT<5> A_BLT_SEL A_PRE_N A_ADDR_DEC<5> ++ A_WR_ONE A_WR_ZERO VDD VSS / RM_IHPSG13_512x32_c2_1P_BLDRV +XA_BLTMUX<4> A_BLC<4> A_BLC_SEL A_BLT<4> A_BLT_SEL A_PRE_N A_ADDR_DEC<4> ++ A_WR_ONE A_WR_ZERO VDD VSS / RM_IHPSG13_512x32_c2_1P_BLDRV +XA_BLTMUX<3> A_BLC<3> A_BLC_SEL A_BLT<3> A_BLT_SEL A_PRE_N A_ADDR_DEC<3> ++ A_WR_ONE A_WR_ZERO VDD VSS / RM_IHPSG13_512x32_c2_1P_BLDRV +XA_BLTMUX<2> A_BLC<2> A_BLC_SEL A_BLT<2> A_BLT_SEL A_PRE_N A_ADDR_DEC<2> ++ A_WR_ONE A_WR_ZERO VDD VSS / RM_IHPSG13_512x32_c2_1P_BLDRV +XA_BLTMUX<1> A_BLC<1> A_BLC_SEL A_BLT<1> A_BLT_SEL A_PRE_N A_ADDR_DEC<1> ++ A_WR_ONE A_WR_ZERO VDD VSS / RM_IHPSG13_512x32_c2_1P_BLDRV +XA_BLTMUX<0> A_BLC<0> A_BLC_SEL A_BLT<0> A_BLT_SEL A_PRE_N A_ADDR_DEC<0> ++ A_WR_ONE A_WR_ZERO VDD VSS / RM_IHPSG13_512x32_c2_1P_BLDRV +XA_I49 A_DI_R A_DI_N VDD VSS / RSC_IHPSG13_INVX2 +XA_I83 A_BM_R A_BM_N VDD VSS / RSC_IHPSG13_INVX2 +XA_I69 A_DCLK_L A_DCLK_B_L VDD VSS / RSC_IHPSG13_CINVX2 +XA_I50 A_WCLK_L A_WCLK_B_L VDD VSS / RSC_IHPSG13_CINVX2 +XA_EBUF A_RCLK_L A_RCLK_B_L VDD VSS / RSC_IHPSG13_CINVX2 +XA_I78 A_RCLK_B_L A_SAE VDD VSS / RSC_IHPSG13_CBUFX2 +XA_I88 A_DCLK_L A_DCLK_R / RSC_IHPSG13_MET3RES +XA_I87 A_WCLK_L A_WCLK_R / RSC_IHPSG13_MET3RES +XA_R2 A_RCLK_L A_RCLK_R / RSC_IHPSG13_MET3RES +XA_I91 A_RCLK_B_L A_RCLK_B_R / RSC_IHPSG13_MET3RES +XA_I90 A_WCLK_B_L A_WCLK_B_R / RSC_IHPSG13_MET3RES +XA_I89 A_DCLK_B_L A_DCLK_B_R / RSC_IHPSG13_MET3RES +XA_I80 A_WCLK_B_R A_RCLK_B_R net21 VDD VSS / RSC_IHPSG13_AND2X2 +XA_I76 A_DI_N A_DO_WRITE_P A_WR_ZERO VDD VSS / RSC_IHPSG13_AND2X2 +XA_I75 A_DI_R A_DO_WRITE_P A_WR_ONE VDD VSS / RSC_IHPSG13_AND2X2 +XA_ISENSE A_SAE A_BLC_SEL A_BLT_SEL net19 net20 VDD VSS / ++ RSC_IHPSG13_DFPQD_MSAFFX2 +XA_I81 net21 A_PRE_N VDD VSS / RSC_IHPSG13_CINVX4_WN +XA_CAPS<5> VDD VSS / RSC_IHPSG13_FILLCAP4 +XA_CAPS<4> VDD VSS / RSC_IHPSG13_FILLCAP4 +XA_CAPS<3> VDD VSS / RSC_IHPSG13_FILLCAP4 +XA_CAPS<2> VDD VSS / RSC_IHPSG13_FILLCAP4 +XA_CAPS<1> VDD VSS / RSC_IHPSG13_FILLCAP4 +.ENDS + +.SUBCKT RM_IHPSG13_512x32_c2_2P_BITKIT_16x2_CORNER VDD_CORE VSS +XI16 VDD_CORE VSS VDD_CORE VSS / ++ RM_IHPSG13_512x32_c2_1P_BITKIT_CORNER +.ENDS +.SUBCKT RM_IHPSG13_512x32_c2_2P_BITKIT_EDGE_LR A_WL B_WL NW PW VDD VSS +MN1 VSS A_WL VSS VSS sg13_lv_nmos m=1 w=300.0n l=130.00n ng=1 nrd=0 nrs=0 +MN0 VSS B_WL VSS VSS sg13_lv_nmos m=1 w=300.0n l=130.00n ng=1 nrd=0 nrs=0 +.ENDS +.SUBCKT RM_IHPSG13_512x32_c2_2P_BITKIT_16x2_EDGE_LR A_WL<15> A_WL<14> A_WL<13> A_WL<12> ++ A_WL<11> A_WL<10> A_WL<9> A_WL<8> A_WL<7> A_WL<6> A_WL<5> A_WL<4> A_WL<3> ++ A_WL<2> A_WL<1> A_WL<0> B_WL<15> B_WL<14> B_WL<13> B_WL<12> B_WL<11> ++ B_WL<10> B_WL<9> B_WL<8> B_WL<7> B_WL<6> B_WL<5> B_WL<4> B_WL<3> B_WL<2> ++ B_WL<1> B_WL<0> VDD_CORE VSS +XI0<15> A_WL<15> B_WL<15> VDD_CORE VSS VDD_CORE VSS ++ / RM_IHPSG13_512x32_c2_2P_BITKIT_EDGE_LR +XI0<14> A_WL<14> B_WL<14> VDD_CORE VSS VDD_CORE VSS ++ / RM_IHPSG13_512x32_c2_2P_BITKIT_EDGE_LR +XI0<13> A_WL<13> B_WL<13> VDD_CORE VSS VDD_CORE VSS ++ / RM_IHPSG13_512x32_c2_2P_BITKIT_EDGE_LR +XI0<12> A_WL<12> B_WL<12> VDD_CORE VSS VDD_CORE VSS ++ / RM_IHPSG13_512x32_c2_2P_BITKIT_EDGE_LR +XI0<11> A_WL<11> B_WL<11> VDD_CORE VSS VDD_CORE VSS ++ / RM_IHPSG13_512x32_c2_2P_BITKIT_EDGE_LR +XI0<10> A_WL<10> B_WL<10> VDD_CORE VSS VDD_CORE VSS ++ / RM_IHPSG13_512x32_c2_2P_BITKIT_EDGE_LR +XI0<9> A_WL<9> B_WL<9> VDD_CORE VSS VDD_CORE VSS / ++ RM_IHPSG13_512x32_c2_2P_BITKIT_EDGE_LR +XI0<8> A_WL<8> B_WL<8> VDD_CORE VSS VDD_CORE VSS / ++ RM_IHPSG13_512x32_c2_2P_BITKIT_EDGE_LR +XI0<7> A_WL<7> B_WL<7> VDD_CORE VSS VDD_CORE VSS / ++ RM_IHPSG13_512x32_c2_2P_BITKIT_EDGE_LR +XI0<6> A_WL<6> B_WL<6> VDD_CORE VSS VDD_CORE VSS / ++ RM_IHPSG13_512x32_c2_2P_BITKIT_EDGE_LR +XI0<5> A_WL<5> B_WL<5> VDD_CORE VSS VDD_CORE VSS / ++ RM_IHPSG13_512x32_c2_2P_BITKIT_EDGE_LR +XI0<4> A_WL<4> B_WL<4> VDD_CORE VSS VDD_CORE VSS / ++ RM_IHPSG13_512x32_c2_2P_BITKIT_EDGE_LR +XI0<3> A_WL<3> B_WL<3> VDD_CORE VSS VDD_CORE VSS / ++ RM_IHPSG13_512x32_c2_2P_BITKIT_EDGE_LR +XI0<2> A_WL<2> B_WL<2> VDD_CORE VSS VDD_CORE VSS / ++ RM_IHPSG13_512x32_c2_2P_BITKIT_EDGE_LR +XI0<1> A_WL<1> B_WL<1> VDD_CORE VSS VDD_CORE VSS / ++ RM_IHPSG13_512x32_c2_2P_BITKIT_EDGE_LR +XI0<0> A_WL<0> B_WL<0> VDD_CORE VSS VDD_CORE VSS / ++ RM_IHPSG13_512x32_c2_2P_BITKIT_EDGE_LR +.ENDS +.SUBCKT RM_IHPSG13_512x32_c2_2P_BITKIT_CELL A_BLC_BOT A_BLC_TOP A_BLT_BOT A_BLT_TOP ++ A_LWL A_RWL B_BLC_BOT B_BLC_TOP B_BLT_BOT B_BLT_TOP B_LWL B_RWL NW PW VDD VSS +MN5 NC B_RWL B_BLC_BOT PW sg13_lv_nmos m=1 w=300.0n l=130.00n ng=1 nrd=0 nrs=0 +MN4 B_BLT_BOT B_LWL NT PW sg13_lv_nmos m=1 w=300.0n l=130.00n ng=1 nrd=0 nrs=0 +MN0 NC NT VSS PW sg13_lv_nmos m=1 w=600.0n l=130.00n ng=2 nrd=0 nrs=0 +MN1 NT NC VSS PW sg13_lv_nmos m=1 w=600.0n l=130.00n ng=2 nrd=0 nrs=0 +MN3 NC A_RWL A_BLC_TOP PW sg13_lv_nmos m=1 w=300.0n l=130.00n ng=1 nrd=0 nrs=0 +MN2 A_BLT_TOP A_LWL NT PW sg13_lv_nmos m=1 w=300.0n l=130.00n ng=1 nrd=0 nrs=0 +MP1 NT NC VDD NW sg13_lv_pmos m=1 w=150.00n l=130.00n ng=1 nrd=0 nrs=0 +MP0 NC NT VDD NW sg13_lv_pmos m=1 w=150.00n l=130.00n ng=1 nrd=0 nrs=0 +R5 B_RWL B_LWL lvsres w=2.6e-07 l=6e-07 +R4 B_BLC_BOT B_BLC_TOP lvsres w=2.6e-07 l=6e-07 +R3 B_BLT_BOT B_BLT_TOP lvsres w=2.6e-07 l=6e-07 +R1 A_BLC_BOT A_BLC_TOP lvsres w=2.6e-07 l=6e-07 +R0 A_BLT_BOT A_BLT_TOP lvsres w=2.6e-07 l=6e-07 +R2 A_RWL A_LWL lvsres w=2.6e-07 l=6e-07 +.ENDS +.SUBCKT RM_IHPSG13_512x32_c2_2P_BITKIT_16x2_SRAM A_BLC_BOT<1> A_BLC_BOT<0> A_BLC_TOP<1> ++ A_BLC_TOP<0> A_BLT_BOT<1> A_BLT_BOT<0> A_BLT_TOP<1> A_BLT_TOP<0> A_LWL<15> ++ A_LWL<14> A_LWL<13> A_LWL<12> A_LWL<11> A_LWL<10> A_LWL<9> A_LWL<8> A_LWL<7> ++ A_LWL<6> A_LWL<5> A_LWL<4> A_LWL<3> A_LWL<2> A_LWL<1> A_LWL<0> A_RWL<15> ++ A_RWL<14> A_RWL<13> A_RWL<12> A_RWL<11> A_RWL<10> A_RWL<9> A_RWL<8> A_RWL<7> ++ A_RWL<6> A_RWL<5> A_RWL<4> A_RWL<3> A_RWL<2> A_RWL<1> A_RWL<0> B_BLC_BOT<1> ++ B_BLC_BOT<0> B_BLC_TOP<1> B_BLC_TOP<0> B_BLT_BOT<1> B_BLT_BOT<0> ++ B_BLT_TOP<1> B_BLT_TOP<0> B_LWL<15> B_LWL<14> B_LWL<13> B_LWL<12> B_LWL<11> ++ B_LWL<10> B_LWL<9> B_LWL<8> B_LWL<7> B_LWL<6> B_LWL<5> B_LWL<4> B_LWL<3> ++ B_LWL<2> B_LWL<1> B_LWL<0> B_RWL<15> B_RWL<14> B_RWL<13> B_RWL<12> B_RWL<11> ++ B_RWL<10> B_RWL<9> B_RWL<8> B_RWL<7> B_RWL<6> B_RWL<5> B_RWL<4> B_RWL<3> ++ B_RWL<2> B_RWL<1> B_RWL<0> VDD_CORE VSS +XCELL<31> A_BLC_TOP<1> A_RBLC<15> A_BLT_TOP<1> A_RBLT<15> A_XWL<15> A_RWL<15> ++ B_BLC_TOP<1> B_RBLC<15> B_BLT_TOP<1> B_RBLT<15> B_XWL<15> B_RWL<15> ++ VDD_CORE VSS VDD_CORE VSS / ++ RM_IHPSG13_512x32_c2_2P_BITKIT_CELL +XCELL<30> A_RBLC<14> A_RBLC<15> A_RBLT<14> A_RBLT<15> A_XWL<14> A_RWL<14> ++ B_RBLC<14> B_RBLC<15> B_RBLT<14> B_RBLT<15> B_XWL<14> B_RWL<14> VDD_CORE ++ VSS VDD_CORE VSS / RM_IHPSG13_512x32_c2_2P_BITKIT_CELL +XCELL<29> A_RBLC<14> A_RBLC<13> A_RBLT<14> A_RBLT<13> A_XWL<13> A_RWL<13> ++ B_RBLC<14> B_RBLC<13> B_RBLT<14> B_RBLT<13> B_XWL<13> B_RWL<13> VDD_CORE ++ VSS VDD_CORE VSS / RM_IHPSG13_512x32_c2_2P_BITKIT_CELL +XCELL<28> A_RBLC<12> A_RBLC<13> A_RBLT<12> A_RBLT<13> A_XWL<12> A_RWL<12> ++ B_RBLC<12> B_RBLC<13> B_RBLT<12> B_RBLT<13> B_XWL<12> B_RWL<12> VDD_CORE ++ VSS VDD_CORE VSS / RM_IHPSG13_512x32_c2_2P_BITKIT_CELL +XCELL<27> A_RBLC<12> A_RBLC<11> A_RBLT<12> A_RBLT<11> A_XWL<11> A_RWL<11> ++ B_RBLC<12> B_RBLC<11> B_RBLT<12> B_RBLT<11> B_XWL<11> B_RWL<11> VDD_CORE ++ VSS VDD_CORE VSS / RM_IHPSG13_512x32_c2_2P_BITKIT_CELL +XCELL<26> A_RBLC<10> A_RBLC<11> A_RBLT<10> A_RBLT<11> A_XWL<10> A_RWL<10> ++ B_RBLC<10> B_RBLC<11> B_RBLT<10> B_RBLT<11> B_XWL<10> B_RWL<10> VDD_CORE ++ VSS VDD_CORE VSS / RM_IHPSG13_512x32_c2_2P_BITKIT_CELL +XCELL<25> A_RBLC<10> A_RBLC<9> A_RBLT<10> A_RBLT<9> A_XWL<9> A_RWL<9> ++ B_RBLC<10> B_RBLC<9> B_RBLT<10> B_RBLT<9> B_XWL<9> B_RWL<9> VDD_CORE ++ VSS VDD_CORE VSS / RM_IHPSG13_512x32_c2_2P_BITKIT_CELL +XCELL<24> A_RBLC<8> A_RBLC<9> A_RBLT<8> A_RBLT<9> A_XWL<8> A_RWL<8> B_RBLC<8> ++ B_RBLC<9> B_RBLT<8> B_RBLT<9> B_XWL<8> B_RWL<8> VDD_CORE VSS ++ VDD_CORE VSS / RM_IHPSG13_512x32_c2_2P_BITKIT_CELL +XCELL<23> A_RBLC<8> A_RBLC<7> A_RBLT<8> A_RBLT<7> A_XWL<7> A_RWL<7> B_RBLC<8> ++ B_RBLC<7> B_RBLT<8> B_RBLT<7> B_XWL<7> B_RWL<7> VDD_CORE VSS ++ VDD_CORE VSS / RM_IHPSG13_512x32_c2_2P_BITKIT_CELL +XCELL<22> A_RBLC<6> A_RBLC<7> A_RBLT<6> A_RBLT<7> A_XWL<6> A_RWL<6> B_RBLC<6> ++ B_RBLC<7> B_RBLT<6> B_RBLT<7> B_XWL<6> B_RWL<6> VDD_CORE VSS ++ VDD_CORE VSS / RM_IHPSG13_512x32_c2_2P_BITKIT_CELL +XCELL<21> A_RBLC<6> A_RBLC<5> A_RBLT<6> A_RBLT<5> A_XWL<5> A_RWL<5> B_RBLC<6> ++ B_RBLC<5> B_RBLT<6> B_RBLT<5> B_XWL<5> B_RWL<5> VDD_CORE VSS ++ VDD_CORE VSS / RM_IHPSG13_512x32_c2_2P_BITKIT_CELL +XCELL<20> A_RBLC<4> A_RBLC<5> A_RBLT<4> A_RBLT<5> A_XWL<4> A_RWL<4> B_RBLC<4> ++ B_RBLC<5> B_RBLT<4> B_RBLT<5> B_XWL<4> B_RWL<4> VDD_CORE VSS ++ VDD_CORE VSS / RM_IHPSG13_512x32_c2_2P_BITKIT_CELL +XCELL<19> A_RBLC<4> A_RBLC<3> A_RBLT<4> A_RBLT<3> A_XWL<3> A_RWL<3> B_RBLC<4> ++ B_RBLC<3> B_RBLT<4> B_RBLT<3> B_XWL<3> B_RWL<3> VDD_CORE VSS ++ VDD_CORE VSS / RM_IHPSG13_512x32_c2_2P_BITKIT_CELL +XCELL<18> A_RBLC<2> A_RBLC<3> A_RBLT<2> A_RBLT<3> A_XWL<2> A_RWL<2> B_RBLC<2> ++ B_RBLC<3> B_RBLT<2> B_RBLT<3> B_XWL<2> B_RWL<2> VDD_CORE VSS ++ VDD_CORE VSS / RM_IHPSG13_512x32_c2_2P_BITKIT_CELL +XCELL<17> A_RBLC<2> A_RBLC<1> A_RBLT<2> A_RBLT<1> A_XWL<1> A_RWL<1> B_RBLC<2> ++ B_RBLC<1> B_RBLT<2> B_RBLT<1> B_XWL<1> B_RWL<1> VDD_CORE VSS ++ VDD_CORE VSS / RM_IHPSG13_512x32_c2_2P_BITKIT_CELL +XCELL<16> A_BLC_BOT<1> A_RBLC<1> A_BLT_BOT<1> A_RBLT<1> A_XWL<0> A_RWL<0> ++ B_BLC_BOT<1> B_RBLC<1> B_BLT_BOT<1> B_RBLT<1> B_XWL<0> B_RWL<0> VDD_CORE ++ VSS VDD_CORE VSS / RM_IHPSG13_512x32_c2_2P_BITKIT_CELL +XCELL<15> A_BLC_TOP<0> A_LBLC<15> A_BLT_TOP<0> A_LBLT<15> A_LWL<15> A_XWL<15> ++ B_BLC_TOP<0> B_LBLC<15> B_BLT_TOP<0> B_LBLT<15> B_LWL<15> B_XWL<15> ++ VDD_CORE VSS VDD_CORE VSS / ++ RM_IHPSG13_512x32_c2_2P_BITKIT_CELL +XCELL<14> A_LBLC<14> A_LBLC<15> A_LBLT<14> A_LBLT<15> A_LWL<14> A_XWL<14> ++ B_LBLC<14> B_LBLC<15> B_LBLT<14> B_LBLT<15> B_LWL<14> B_XWL<14> VDD_CORE ++ VSS VDD_CORE VSS / RM_IHPSG13_512x32_c2_2P_BITKIT_CELL +XCELL<13> A_LBLC<14> A_LBLC<13> A_LBLT<14> A_LBLT<13> A_LWL<13> A_XWL<13> ++ B_LBLC<14> B_LBLC<13> B_LBLT<14> B_LBLT<13> B_LWL<13> B_XWL<13> VDD_CORE ++ VSS VDD_CORE VSS / RM_IHPSG13_512x32_c2_2P_BITKIT_CELL +XCELL<12> A_LBLC<12> A_LBLC<13> A_LBLT<12> A_LBLT<13> A_LWL<12> A_XWL<12> ++ B_LBLC<12> B_LBLC<13> B_LBLT<12> B_LBLT<13> B_LWL<12> B_XWL<12> VDD_CORE ++ VSS VDD_CORE VSS / RM_IHPSG13_512x32_c2_2P_BITKIT_CELL +XCELL<11> A_LBLC<12> A_LBLC<11> A_LBLT<12> A_LBLT<11> A_LWL<11> A_XWL<11> ++ B_LBLC<12> B_LBLC<11> B_LBLT<12> B_LBLT<11> B_LWL<11> B_XWL<11> VDD_CORE ++ VSS VDD_CORE VSS / RM_IHPSG13_512x32_c2_2P_BITKIT_CELL +XCELL<10> A_LBLC<10> A_LBLC<11> A_LBLT<10> A_LBLT<11> A_LWL<10> A_XWL<10> ++ B_LBLC<10> B_LBLC<11> B_LBLT<10> B_LBLT<11> B_LWL<10> B_XWL<10> VDD_CORE ++ VSS VDD_CORE VSS / RM_IHPSG13_512x32_c2_2P_BITKIT_CELL +XCELL<9> A_LBLC<10> A_LBLC<9> A_LBLT<10> A_LBLT<9> A_LWL<9> A_XWL<9> ++ B_LBLC<10> B_LBLC<9> B_LBLT<10> B_LBLT<9> B_LWL<9> B_XWL<9> VDD_CORE ++ VSS VDD_CORE VSS / RM_IHPSG13_512x32_c2_2P_BITKIT_CELL +XCELL<8> A_LBLC<8> A_LBLC<9> A_LBLT<8> A_LBLT<9> A_LWL<8> A_XWL<8> B_LBLC<8> ++ B_LBLC<9> B_LBLT<8> B_LBLT<9> B_LWL<8> B_XWL<8> VDD_CORE VSS ++ VDD_CORE VSS / RM_IHPSG13_512x32_c2_2P_BITKIT_CELL +XCELL<7> A_LBLC<8> A_LBLC<7> A_LBLT<8> A_LBLT<7> A_LWL<7> A_XWL<7> B_LBLC<8> ++ B_LBLC<7> B_LBLT<8> B_LBLT<7> B_LWL<7> B_XWL<7> VDD_CORE VSS ++ VDD_CORE VSS / RM_IHPSG13_512x32_c2_2P_BITKIT_CELL +XCELL<6> A_LBLC<6> A_LBLC<7> A_LBLT<6> A_LBLT<7> A_LWL<6> A_XWL<6> B_LBLC<6> ++ B_LBLC<7> B_LBLT<6> B_LBLT<7> B_LWL<6> B_XWL<6> VDD_CORE VSS ++ VDD_CORE VSS / RM_IHPSG13_512x32_c2_2P_BITKIT_CELL +XCELL<5> A_LBLC<6> A_LBLC<5> A_LBLT<6> A_LBLT<5> A_LWL<5> A_XWL<5> B_LBLC<6> ++ B_LBLC<5> B_LBLT<6> B_LBLT<5> B_LWL<5> B_XWL<5> VDD_CORE VSS ++ VDD_CORE VSS / RM_IHPSG13_512x32_c2_2P_BITKIT_CELL +XCELL<4> A_LBLC<4> A_LBLC<5> A_LBLT<4> A_LBLT<5> A_LWL<4> A_XWL<4> B_LBLC<4> ++ B_LBLC<5> B_LBLT<4> B_LBLT<5> B_LWL<4> B_XWL<4> VDD_CORE VSS ++ VDD_CORE VSS / RM_IHPSG13_512x32_c2_2P_BITKIT_CELL +XCELL<3> A_LBLC<4> A_LBLC<3> A_LBLT<4> A_LBLT<3> A_LWL<3> A_XWL<3> B_LBLC<4> ++ B_LBLC<3> B_LBLT<4> B_LBLT<3> B_LWL<3> B_XWL<3> VDD_CORE VSS ++ VDD_CORE VSS / RM_IHPSG13_512x32_c2_2P_BITKIT_CELL +XCELL<2> A_LBLC<2> A_LBLC<3> A_LBLT<2> A_LBLT<3> A_LWL<2> A_XWL<2> B_LBLC<2> ++ B_LBLC<3> B_LBLT<2> B_LBLT<3> B_LWL<2> B_XWL<2> VDD_CORE VSS ++ VDD_CORE VSS / RM_IHPSG13_512x32_c2_2P_BITKIT_CELL +XCELL<1> A_LBLC<2> A_LBLC<1> A_LBLT<2> A_LBLT<1> A_LWL<1> A_XWL<1> B_LBLC<2> ++ B_LBLC<1> B_LBLT<2> B_LBLT<1> B_LWL<1> B_XWL<1> VDD_CORE VSS ++ VDD_CORE VSS / RM_IHPSG13_512x32_c2_2P_BITKIT_CELL +XCELL<0> A_BLC_BOT<0> A_LBLC<1> A_BLT_BOT<0> A_LBLT<1> A_LWL<0> A_XWL<0> ++ B_BLC_BOT<0> B_LBLC<1> B_BLT_BOT<0> B_LBLT<1> B_LWL<0> B_XWL<0> VDD_CORE ++ VSS VDD_CORE VSS / RM_IHPSG13_512x32_c2_2P_BITKIT_CELL +.ENDS +.SUBCKT RM_IHPSG13_512x32_c2_2P_BITKIT_EDGE_TB A_BLC A_BLT B_BLC B_BLT NW PW VDD VSS +.ENDS +.SUBCKT RM_IHPSG13_512x32_c2_2P_BITKIT_16x2_EDGE_TB A_BLC<1> A_BLC<0> A_BLT<1> A_BLT<0> ++ B_BLC<1> B_BLC<0> B_BLT<1> B_BLT<0> VDD_CORE VSS +XEDGE<1> A_BLC<1> A_BLT<1> B_BLC<1> B_BLT<1> VDD_CORE VSS ++ VDD_CORE VSS / RM_IHPSG13_512x32_c2_2P_BITKIT_EDGE_TB +XEDGE<0> A_BLC<0> A_BLT<0> B_BLC<0> B_BLT<0> VDD_CORE VSS ++ VDD_CORE VSS / RM_IHPSG13_512x32_c2_2P_BITKIT_EDGE_TB +.ENDS +.SUBCKT RM_IHPSG13_512x32_c2_2P_BITKIT_TAP A_BLC A_BLT B_BLC B_BLT NW PW VDD VSS +.ENDS +.SUBCKT RM_IHPSG13_512x32_c2_2P_BITKIT_16x2_TAP A_BLC<1> A_BLC<0> A_BLT<1> A_BLT<0> ++ B_BLC<1> B_BLC<0> B_BLT<1> B_BLT<0> VDD_CORE VSS +XIEDGEBP_COL1<1> A_BLC<1> A_BLT<1> B_BLC<1> B_BLT<1> VDD_CORE VSS ++ VDD_CORE VSS / RM_IHPSG13_512x32_c2_2P_BITKIT_EDGE_TB +XIEDGEBP_COL1<0> A_BLC<1> A_BLT<1> B_BLC<1> B_BLT<1> VDD_CORE VSS ++ VDD_CORE VSS / RM_IHPSG13_512x32_c2_2P_BITKIT_EDGE_TB +XIEDGEBP_COL2<1> A_BLC<0> A_BLT<0> B_BLC<0> B_BLT<0> VDD_CORE VSS ++ VDD_CORE VSS / RM_IHPSG13_512x32_c2_2P_BITKIT_EDGE_TB +XIEDGEBP_COL2<0> A_BLC<0> A_BLT<0> B_BLC<0> B_BLT<0> VDD_CORE VSS ++ VDD_CORE VSS / RM_IHPSG13_512x32_c2_2P_BITKIT_EDGE_TB +XITAP<1> A_BLC<1> A_BLT<1> B_BLC<1> B_BLT<1> VDD_CORE VSS ++ VDD_CORE VSS / RM_IHPSG13_512x32_c2_2P_BITKIT_TAP +XITAP<0> A_BLC<0> A_BLT<0> B_BLC<0> B_BLT<0> VDD_CORE VSS ++ VDD_CORE VSS / RM_IHPSG13_512x32_c2_2P_BITKIT_TAP +.ENDS + + +.SUBCKT RM_IHPSG13_512x32_c2_1P_BITKIT_TAP_LR NW PW VDD VSS +.ENDS +.SUBCKT RM_IHPSG13_512x32_c2_2P_BITKIT_16x2_TAP_LR VDD_CORE VSS +XCORNER<1> VDD_CORE VSS VDD_CORE VSS / ++ RM_IHPSG13_512x32_c2_1P_BITKIT_CORNER +XCORNER<0> VDD_CORE VSS VDD_CORE VSS / ++ RM_IHPSG13_512x32_c2_1P_BITKIT_CORNER +XTAP_BORDER VDD_CORE VSS VDD_CORE VSS / ++ RM_IHPSG13_512x32_c2_1P_BITKIT_TAP_LR +.ENDS + +.SUBCKT RSC_IHPSG13_CBUFX12 A Z VDD VSS +MN1 Z net6 VSS VSS sg13_lv_nmos m=1 w=4.23u l=130.00n ng=6 nrd=0 nrs=0 +MN0 net6 A VSS VSS sg13_lv_nmos m=1 w=1.41u l=130.00n ng=2 nrd=0 nrs=0 +MP1 Z net6 VDD VDD sg13_lv_pmos m=1 w=9.72u l=130.00n ng=6 nrd=0 nrs=0 +MP0 net6 A VDD VDD sg13_lv_pmos m=1 w=3.24u l=130.00n ng=2 nrd=0 nrs=0 +.ENDS +.SUBCKT RM_IHPSG13_512x32_c2_2P_COLDRV13X12 ADDR_COL_I<1> ADDR_COL_I<0> ADDR_COL_O<1> ++ ADDR_COL_O<0> ADDR_DEC_I<7> ADDR_DEC_I<6> ADDR_DEC_I<5> ADDR_DEC_I<4> ++ ADDR_DEC_I<3> ADDR_DEC_I<2> ADDR_DEC_I<1> ADDR_DEC_I<0> ADDR_DEC_O<7> ++ ADDR_DEC_O<6> ADDR_DEC_O<5> ADDR_DEC_O<4> ADDR_DEC_O<3> ADDR_DEC_O<2> ++ ADDR_DEC_O<1> ADDR_DEC_O<0> DCLK_I DCLK_O RCLK_I RCLK_O WCLK_I WCLK_O ++ VDD VSS +XI1<3> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI1<2> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI1<1> VDD VSS / RSC_IHPSG13_FILLCAP8 +XWCLK_DRV WCLK_I WCLK_O VDD VSS / RSC_IHPSG13_CBUFX12 +XRCLK_DRV RCLK_I RCLK_O VDD VSS / RSC_IHPSG13_CBUFX12 +XDCLK_DRV DCLK_I DCLK_O VDD VSS / RSC_IHPSG13_CBUFX12 +XADDR_COL_DRV<1> ADDR_COL_I<1> ADDR_COL_O<1> VDD VSS / ++ RSC_IHPSG13_CBUFX12 +XADDR_COL_DRV<0> ADDR_COL_I<0> ADDR_COL_O<0> VDD VSS / ++ RSC_IHPSG13_CBUFX12 +XADDR_DEC_DRV<7> ADDR_DEC_I<7> ADDR_DEC_O<7> VDD VSS / ++ RSC_IHPSG13_CBUFX12 +XADDR_DEC_DRV<6> ADDR_DEC_I<6> ADDR_DEC_O<6> VDD VSS / ++ RSC_IHPSG13_CBUFX12 +XADDR_DEC_DRV<5> ADDR_DEC_I<5> ADDR_DEC_O<5> VDD VSS / ++ RSC_IHPSG13_CBUFX12 +XADDR_DEC_DRV<4> ADDR_DEC_I<4> ADDR_DEC_O<4> VDD VSS / ++ RSC_IHPSG13_CBUFX12 +XADDR_DEC_DRV<3> ADDR_DEC_I<3> ADDR_DEC_O<3> VDD VSS / ++ RSC_IHPSG13_CBUFX12 +XADDR_DEC_DRV<2> ADDR_DEC_I<2> ADDR_DEC_O<2> VDD VSS / ++ RSC_IHPSG13_CBUFX12 +XADDR_DEC_DRV<1> ADDR_DEC_I<1> ADDR_DEC_O<1> VDD VSS / ++ RSC_IHPSG13_CBUFX12 +XADDR_DEC_DRV<0> ADDR_DEC_I<0> ADDR_DEC_O<0> VDD VSS / ++ RSC_IHPSG13_CBUFX12 +XI0<6> VDD VSS / RSC_IHPSG13_FILLCAP4 +XI0<5> VDD VSS / RSC_IHPSG13_FILLCAP4 +XI0<4> VDD VSS / RSC_IHPSG13_FILLCAP4 +XI0<3> VDD VSS / RSC_IHPSG13_FILLCAP4 +XI0<2> VDD VSS / RSC_IHPSG13_FILLCAP4 +XI0<1> VDD VSS / RSC_IHPSG13_FILLCAP4 +.ENDS +.SUBCKT RSC_IHPSG13_WLDRVX12 A Z VDD VSS +MN1 Z net6 VSS VSS sg13_lv_nmos m=1 w=1.41u l=130.00n ng=2 nrd=0 nrs=0 +MN0 net6 A VSS VSS sg13_lv_nmos m=1 w=1.8u l=130.00n ng=2 nrd=0 nrs=0 +MP1 Z net6 VDD VDD sg13_lv_pmos m=1 w=9.72u l=130.00n ng=6 nrd=0 nrs=0 +MP0 net6 A VDD VDD sg13_lv_pmos m=1 w=900.0n l=130.00n ng=1 nrd=0 nrs=0 +.ENDS +.SUBCKT RM_IHPSG13_512x32_c2_2P_WLDRV16X12 A<15> A<14> A<13> A<12> A<11> A<10> A<9> A<8> ++ A<7> A<6> A<5> A<4> A<3> A<2> A<1> A<0> Z<15> Z<14> Z<13> Z<12> Z<11> Z<10> ++ Z<9> Z<8> Z<7> Z<6> Z<5> Z<4> Z<3> Z<2> Z<1> Z<0> VDD VSS +XBUF<15> A<15> Z<15> VDD VSS / RSC_IHPSG13_WLDRVX12 +XBUF<14> A<14> Z<14> VDD VSS / RSC_IHPSG13_WLDRVX12 +XBUF<13> A<13> Z<13> VDD VSS / RSC_IHPSG13_WLDRVX12 +XBUF<12> A<12> Z<12> VDD VSS / RSC_IHPSG13_WLDRVX12 +XBUF<11> A<11> Z<11> VDD VSS / RSC_IHPSG13_WLDRVX12 +XBUF<10> A<10> Z<10> VDD VSS / RSC_IHPSG13_WLDRVX12 +XBUF<9> A<9> Z<9> VDD VSS / RSC_IHPSG13_WLDRVX12 +XBUF<8> A<8> Z<8> VDD VSS / RSC_IHPSG13_WLDRVX12 +XBUF<7> A<7> Z<7> VDD VSS / RSC_IHPSG13_WLDRVX12 +XBUF<6> A<6> Z<6> VDD VSS / RSC_IHPSG13_WLDRVX12 +XBUF<5> A<5> Z<5> VDD VSS / RSC_IHPSG13_WLDRVX12 +XBUF<4> A<4> Z<4> VDD VSS / RSC_IHPSG13_WLDRVX12 +XBUF<3> A<3> Z<3> VDD VSS / RSC_IHPSG13_WLDRVX12 +XBUF<2> A<2> Z<2> VDD VSS / RSC_IHPSG13_WLDRVX12 +XBUF<1> A<1> Z<1> VDD VSS / RSC_IHPSG13_WLDRVX12 +XBUF<0> A<0> Z<0> VDD VSS / RSC_IHPSG13_WLDRVX12 +.ENDS +.SUBCKT RM_IHPSG13_512x32_c2_2P_DEC04 ADDR<3> ADDR<2> ADDR<1> ADDR<0> CS ECLK_H_BOT ++ ECLK_H_TOP ECLK_L_BOT ECLK_L_TOP WL<15> WL<14> WL<13> WL<12> WL<11> WL<10> ++ WL<9> WL<8> WL<7> WL<6> WL<5> WL<4> WL<3> WL<2> WL<1> WL<0> VDD VSS +XI0<3> PADR<1> PADR<0> sel01<3> VDD VSS / RSC_IHPSG13_NAND2X2 +XI0<2> PADR<1> NADR<0> sel01<2> VDD VSS / RSC_IHPSG13_NAND2X2 +XI0<1> NADR<1> PADR<0> sel01<1> VDD VSS / RSC_IHPSG13_NAND2X2 +XI0<0> NADR<1> NADR<0> sel01<0> VDD VSS / RSC_IHPSG13_NAND2X2 +XI4 ECLK_L_BOT EN VDD VSS / RSC_IHPSG13_CINVX4 +XI5 ECLK_H_BOT ECLK_L_BOT VDD VSS / RSC_IHPSG13_CINVX2 +XI3<3> PADR<3> NADR<3> VDD VSS / RSC_IHPSG13_INVX2 +XI3<2> PADR<2> NADR<2> VDD VSS / RSC_IHPSG13_INVX2 +XI3<1> PADR<1> NADR<1> VDD VSS / RSC_IHPSG13_INVX2 +XI3<0> PADR<0> NADR<0> VDD VSS / RSC_IHPSG13_INVX2 +XR0 ECLK_H_BOT ECLK_H_TOP / RSC_IHPSG13_MET2RES +XI11 ECLK_L_BOT ECLK_L_TOP / RSC_IHPSG13_MET2RES +XI1<3> PADR<2> PADR<3> CS sel23<3> VDD VSS / RSC_IHPSG13_NAND3X2 +XI1<2> NADR<2> PADR<3> CS sel23<2> VDD VSS / RSC_IHPSG13_NAND3X2 +XI1<1> PADR<2> NADR<3> CS sel23<1> VDD VSS / RSC_IHPSG13_NAND3X2 +XI1<0> NADR<2> NADR<3> CS sel23<0> VDD VSS / RSC_IHPSG13_NAND3X2 +XI2<15> sel23<3> sel01<3> EN WL<15> VDD VSS / RSC_IHPSG13_NOR3X2 +XI2<14> sel23<3> sel01<2> EN WL<14> VDD VSS / RSC_IHPSG13_NOR3X2 +XI2<13> sel23<3> sel01<1> EN WL<13> VDD VSS / RSC_IHPSG13_NOR3X2 +XI2<12> sel23<3> sel01<0> EN WL<12> VDD VSS / RSC_IHPSG13_NOR3X2 +XI2<11> sel23<2> sel01<3> EN WL<11> VDD VSS / RSC_IHPSG13_NOR3X2 +XI2<10> sel23<2> sel01<2> EN WL<10> VDD VSS / RSC_IHPSG13_NOR3X2 +XI2<9> sel23<2> sel01<1> EN WL<9> VDD VSS / RSC_IHPSG13_NOR3X2 +XI2<8> sel23<2> sel01<0> EN WL<8> VDD VSS / RSC_IHPSG13_NOR3X2 +XI2<7> sel23<1> sel01<3> EN WL<7> VDD VSS / RSC_IHPSG13_NOR3X2 +XI2<6> sel23<1> sel01<2> EN WL<6> VDD VSS / RSC_IHPSG13_NOR3X2 +XI2<5> sel23<1> sel01<1> EN WL<5> VDD VSS / RSC_IHPSG13_NOR3X2 +XI2<4> sel23<1> sel01<0> EN WL<4> VDD VSS / RSC_IHPSG13_NOR3X2 +XI2<3> sel23<0> sel01<3> EN WL<3> VDD VSS / RSC_IHPSG13_NOR3X2 +XI2<2> sel23<0> sel01<2> EN WL<2> VDD VSS / RSC_IHPSG13_NOR3X2 +XI2<1> sel23<0> sel01<1> EN WL<1> VDD VSS / RSC_IHPSG13_NOR3X2 +XI2<0> sel23<0> sel01<0> EN WL<0> VDD VSS / RSC_IHPSG13_NOR3X2 +XCAPS4 VDD VSS / RSC_IHPSG13_FILLCAP4 +XLATCH<3> CS ADDR<3> PADR<3> VDD VSS / RSC_IHPSG13_LHPQX2 +XLATCH<2> CS ADDR<2> PADR<2> VDD VSS / RSC_IHPSG13_LHPQX2 +XLATCH<1> CS ADDR<1> PADR<1> VDD VSS / RSC_IHPSG13_LHPQX2 +XLATCH<0> CS ADDR<0> PADR<0> VDD VSS / RSC_IHPSG13_LHPQX2 +.ENDS +.SUBCKT RM_IHPSG13_512x32_c2_2P_DEC02 ADDR<1> ADDR<0> CS CS_OUT VDD VSS +XDEC ADDR<1> NADDR<0> CS net1 VDD VSS / RSC_IHPSG13_NAND3X2 +XADDRINV ADDR<0> NADDR<0> VDD VSS / RSC_IHPSG13_INVX2 +XDECINV net1 CS_OUT VDD VSS / RSC_IHPSG13_INVX4 +XI2<1> VDD VSS / RSC_IHPSG13_FILLCAP4 +XI2<0> VDD VSS / RSC_IHPSG13_FILLCAP4 +.ENDS +.SUBCKT RM_IHPSG13_512x32_c2_2P_DEC01 ADDR<1> ADDR<0> CS CS_OUT VDD VSS +XDEC NADDR<1> ADDR<0> CS net1 VDD VSS / RSC_IHPSG13_NAND3X2 +XADDRINV ADDR<1> NADDR<1> VDD VSS / RSC_IHPSG13_INVX2 +XDECINV net1 CS_OUT VDD VSS / RSC_IHPSG13_INVX4 +XI2<1> VDD VSS / RSC_IHPSG13_FILLCAP4 +XI2<0> VDD VSS / RSC_IHPSG13_FILLCAP4 +.ENDS +.SUBCKT RM_IHPSG13_512x32_c2_2P_DEC00 ADDR<1> ADDR<0> CS CS_OUT VDD VSS +XDEC NADDR<1> NADDR<0> CS net1 VDD VSS / RSC_IHPSG13_NAND3X2 +XADDRINV<1> ADDR<1> NADDR<1> VDD VSS / RSC_IHPSG13_INVX2 +XADDRINV<0> ADDR<0> NADDR<0> VDD VSS / RSC_IHPSG13_INVX2 +XI1<1> VDD VSS / RSC_IHPSG13_FILLCAP4 +XI1<0> VDD VSS / RSC_IHPSG13_FILLCAP4 +XDECINV net1 CS_OUT VDD VSS / RSC_IHPSG13_INVX4 +.ENDS +.SUBCKT RM_IHPSG13_512x32_c2_2P_DEC03 ADDR<1> ADDR<0> CS CS_OUT VDD VSS +XDEC ADDR<1> ADDR<0> CS net1 VDD VSS / RSC_IHPSG13_NAND3X2 +XDECINV net1 CS_OUT VDD VSS / RSC_IHPSG13_INVX4 +XI0<1> VDD VSS / RSC_IHPSG13_FILLCAP4 +XI0<0> VDD VSS / RSC_IHPSG13_FILLCAP4 +.ENDS +.SUBCKT RM_IHPSG13_512x32_c2_2P_ROWDEC9 ADDR_N_I<8> ADDR_N_I<7> ADDR_N_I<6> ADDR_N_I<5> ++ ADDR_N_I<4> ADDR_N_I<3> ADDR_N_I<2> ADDR_N_I<1> ADDR_N_I<0> CS_I ECLK_I ++ WL_O<511> WL_O<510> WL_O<509> WL_O<508> WL_O<507> WL_O<506> WL_O<505> ++ WL_O<504> WL_O<503> WL_O<502> WL_O<501> WL_O<500> WL_O<499> WL_O<498> ++ WL_O<497> WL_O<496> WL_O<495> WL_O<494> WL_O<493> WL_O<492> WL_O<491> ++ WL_O<490> WL_O<489> WL_O<488> WL_O<487> WL_O<486> WL_O<485> WL_O<484> ++ WL_O<483> WL_O<482> WL_O<481> WL_O<480> WL_O<479> WL_O<478> WL_O<477> ++ WL_O<476> WL_O<475> WL_O<474> WL_O<473> WL_O<472> WL_O<471> WL_O<470> ++ WL_O<469> WL_O<468> WL_O<467> WL_O<466> WL_O<465> WL_O<464> WL_O<463> ++ WL_O<462> WL_O<461> WL_O<460> WL_O<459> WL_O<458> WL_O<457> WL_O<456> ++ WL_O<455> WL_O<454> WL_O<453> WL_O<452> WL_O<451> WL_O<450> WL_O<449> ++ WL_O<448> WL_O<447> WL_O<446> WL_O<445> WL_O<444> WL_O<443> WL_O<442> ++ WL_O<441> WL_O<440> WL_O<439> WL_O<438> WL_O<437> WL_O<436> WL_O<435> ++ WL_O<434> WL_O<433> WL_O<432> WL_O<431> WL_O<430> WL_O<429> WL_O<428> ++ WL_O<427> WL_O<426> WL_O<425> WL_O<424> WL_O<423> WL_O<422> WL_O<421> ++ WL_O<420> WL_O<419> WL_O<418> WL_O<417> WL_O<416> WL_O<415> WL_O<414> ++ WL_O<413> WL_O<412> WL_O<411> WL_O<410> WL_O<409> WL_O<408> WL_O<407> ++ WL_O<406> WL_O<405> WL_O<404> WL_O<403> WL_O<402> WL_O<401> WL_O<400> ++ WL_O<399> WL_O<398> WL_O<397> WL_O<396> WL_O<395> WL_O<394> WL_O<393> ++ WL_O<392> WL_O<391> WL_O<390> WL_O<389> WL_O<388> WL_O<387> WL_O<386> ++ WL_O<385> WL_O<384> WL_O<383> WL_O<382> WL_O<381> WL_O<380> WL_O<379> ++ WL_O<378> WL_O<377> WL_O<376> WL_O<375> WL_O<374> WL_O<373> WL_O<372> ++ WL_O<371> WL_O<370> WL_O<369> WL_O<368> WL_O<367> WL_O<366> WL_O<365> ++ WL_O<364> WL_O<363> WL_O<362> WL_O<361> WL_O<360> WL_O<359> WL_O<358> ++ WL_O<357> WL_O<356> WL_O<355> WL_O<354> WL_O<353> WL_O<352> WL_O<351> ++ WL_O<350> WL_O<349> WL_O<348> WL_O<347> WL_O<346> WL_O<345> WL_O<344> ++ WL_O<343> WL_O<342> WL_O<341> WL_O<340> WL_O<339> WL_O<338> WL_O<337> ++ WL_O<336> WL_O<335> WL_O<334> WL_O<333> WL_O<332> WL_O<331> WL_O<330> ++ WL_O<329> WL_O<328> WL_O<327> WL_O<326> WL_O<325> WL_O<324> WL_O<323> ++ WL_O<322> WL_O<321> WL_O<320> WL_O<319> WL_O<318> WL_O<317> WL_O<316> ++ WL_O<315> WL_O<314> WL_O<313> WL_O<312> WL_O<311> WL_O<310> WL_O<309> ++ WL_O<308> WL_O<307> WL_O<306> WL_O<305> WL_O<304> WL_O<303> WL_O<302> ++ WL_O<301> WL_O<300> WL_O<299> WL_O<298> WL_O<297> WL_O<296> WL_O<295> ++ WL_O<294> WL_O<293> WL_O<292> WL_O<291> WL_O<290> WL_O<289> WL_O<288> ++ WL_O<287> WL_O<286> WL_O<285> WL_O<284> WL_O<283> WL_O<282> WL_O<281> ++ WL_O<280> WL_O<279> WL_O<278> WL_O<277> WL_O<276> WL_O<275> WL_O<274> ++ WL_O<273> WL_O<272> WL_O<271> WL_O<270> WL_O<269> WL_O<268> WL_O<267> ++ WL_O<266> WL_O<265> WL_O<264> WL_O<263> WL_O<262> WL_O<261> WL_O<260> ++ WL_O<259> WL_O<258> WL_O<257> WL_O<256> WL_O<255> WL_O<254> WL_O<253> ++ WL_O<252> WL_O<251> WL_O<250> WL_O<249> WL_O<248> WL_O<247> WL_O<246> ++ WL_O<245> WL_O<244> WL_O<243> WL_O<242> WL_O<241> WL_O<240> WL_O<239> ++ WL_O<238> WL_O<237> WL_O<236> WL_O<235> WL_O<234> WL_O<233> WL_O<232> ++ WL_O<231> WL_O<230> WL_O<229> WL_O<228> WL_O<227> WL_O<226> WL_O<225> ++ WL_O<224> WL_O<223> WL_O<222> WL_O<221> WL_O<220> WL_O<219> WL_O<218> ++ WL_O<217> WL_O<216> WL_O<215> WL_O<214> WL_O<213> WL_O<212> WL_O<211> ++ WL_O<210> WL_O<209> WL_O<208> WL_O<207> WL_O<206> WL_O<205> WL_O<204> ++ WL_O<203> WL_O<202> WL_O<201> WL_O<200> WL_O<199> WL_O<198> WL_O<197> ++ WL_O<196> WL_O<195> WL_O<194> WL_O<193> WL_O<192> WL_O<191> WL_O<190> ++ WL_O<189> WL_O<188> WL_O<187> WL_O<186> WL_O<185> WL_O<184> WL_O<183> ++ WL_O<182> WL_O<181> WL_O<180> WL_O<179> WL_O<178> WL_O<177> WL_O<176> ++ WL_O<175> WL_O<174> WL_O<173> WL_O<172> WL_O<171> WL_O<170> WL_O<169> ++ WL_O<168> WL_O<167> WL_O<166> WL_O<165> WL_O<164> WL_O<163> WL_O<162> ++ WL_O<161> WL_O<160> WL_O<159> WL_O<158> WL_O<157> WL_O<156> WL_O<155> ++ WL_O<154> WL_O<153> WL_O<152> WL_O<151> WL_O<150> WL_O<149> WL_O<148> ++ WL_O<147> WL_O<146> WL_O<145> WL_O<144> WL_O<143> WL_O<142> WL_O<141> ++ WL_O<140> WL_O<139> WL_O<138> WL_O<137> WL_O<136> WL_O<135> WL_O<134> ++ WL_O<133> WL_O<132> WL_O<131> WL_O<130> WL_O<129> WL_O<128> WL_O<127> ++ WL_O<126> WL_O<125> WL_O<124> WL_O<123> WL_O<122> WL_O<121> WL_O<120> ++ WL_O<119> WL_O<118> WL_O<117> WL_O<116> WL_O<115> WL_O<114> WL_O<113> ++ WL_O<112> WL_O<111> WL_O<110> WL_O<109> WL_O<108> WL_O<107> WL_O<106> ++ WL_O<105> WL_O<104> WL_O<103> WL_O<102> WL_O<101> WL_O<100> WL_O<99> ++ WL_O<98> WL_O<97> WL_O<96> WL_O<95> WL_O<94> WL_O<93> WL_O<92> WL_O<91> ++ WL_O<90> WL_O<89> WL_O<88> WL_O<87> WL_O<86> WL_O<85> WL_O<84> WL_O<83> ++ WL_O<82> WL_O<81> WL_O<80> WL_O<79> WL_O<78> WL_O<77> WL_O<76> WL_O<75> ++ WL_O<74> WL_O<73> WL_O<72> WL_O<71> WL_O<70> WL_O<69> WL_O<68> WL_O<67> ++ WL_O<66> WL_O<65> WL_O<64> WL_O<63> WL_O<62> WL_O<61> WL_O<60> WL_O<59> ++ WL_O<58> WL_O<57> WL_O<56> WL_O<55> WL_O<54> WL_O<53> WL_O<52> WL_O<51> ++ WL_O<50> WL_O<49> WL_O<48> WL_O<47> WL_O<46> WL_O<45> WL_O<44> WL_O<43> ++ WL_O<42> WL_O<41> WL_O<40> WL_O<39> WL_O<38> WL_O<37> WL_O<36> WL_O<35> ++ WL_O<34> WL_O<33> WL_O<32> WL_O<31> WL_O<30> WL_O<29> WL_O<28> WL_O<27> ++ WL_O<26> WL_O<25> WL_O<24> WL_O<23> WL_O<22> WL_O<21> WL_O<20> WL_O<19> ++ WL_O<18> WL_O<17> WL_O<16> WL_O<15> WL_O<14> WL_O<13> WL_O<12> WL_O<11> ++ WL_O<10> WL_O<9> WL_O<8> WL_O<7> WL_O<6> WL_O<5> WL_O<4> WL_O<3> WL_O<2> ++ WL_O<1> WL_O<0> VDD VSS +XSEL<31> ADDR_N_I<3> ADDR_N_I<2> ADDR_N_I<1> ADDR_N_I<0> CS00<31> ECLK_H<31> ++ ECLK_H<32> ECLK_B<31> ECLK_B<32> WL_O<511> WL_O<510> WL_O<509> WL_O<508> ++ WL_O<507> WL_O<506> WL_O<505> WL_O<504> WL_O<503> WL_O<502> WL_O<501> ++ WL_O<500> WL_O<499> WL_O<498> WL_O<497> WL_O<496> VDD VSS / ++ RM_IHPSG13_512x32_c2_2P_DEC04 +XSEL<30> ADDR_N_I<3> ADDR_N_I<2> ADDR_N_I<1> ADDR_N_I<0> CS00<30> ECLK_H<30> ++ ECLK_H<31> ECLK_B<30> ECLK_B<31> WL_O<495> WL_O<494> WL_O<493> WL_O<492> ++ WL_O<491> WL_O<490> WL_O<489> WL_O<488> WL_O<487> WL_O<486> WL_O<485> ++ WL_O<484> WL_O<483> WL_O<482> WL_O<481> WL_O<480> VDD VSS / ++ RM_IHPSG13_512x32_c2_2P_DEC04 +XSEL<29> ADDR_N_I<3> ADDR_N_I<2> ADDR_N_I<1> ADDR_N_I<0> CS00<29> ECLK_H<29> ++ ECLK_H<30> ECLK_B<29> ECLK_B<30> WL_O<479> WL_O<478> WL_O<477> WL_O<476> ++ WL_O<475> WL_O<474> WL_O<473> WL_O<472> WL_O<471> WL_O<470> WL_O<469> ++ WL_O<468> WL_O<467> WL_O<466> WL_O<465> WL_O<464> VDD VSS / ++ RM_IHPSG13_512x32_c2_2P_DEC04 +XSEL<28> ADDR_N_I<3> ADDR_N_I<2> ADDR_N_I<1> ADDR_N_I<0> CS00<28> ECLK_H<28> ++ ECLK_H<29> ECLK_B<28> ECLK_B<29> WL_O<463> WL_O<462> WL_O<461> WL_O<460> ++ WL_O<459> WL_O<458> WL_O<457> WL_O<456> WL_O<455> WL_O<454> WL_O<453> ++ WL_O<452> WL_O<451> WL_O<450> WL_O<449> WL_O<448> VDD VSS / ++ RM_IHPSG13_512x32_c2_2P_DEC04 +XSEL<27> ADDR_N_I<3> ADDR_N_I<2> ADDR_N_I<1> ADDR_N_I<0> CS00<27> ECLK_H<27> ++ ECLK_H<28> ECLK_B<27> ECLK_B<28> WL_O<447> WL_O<446> WL_O<445> WL_O<444> ++ WL_O<443> WL_O<442> WL_O<441> WL_O<440> WL_O<439> WL_O<438> WL_O<437> ++ WL_O<436> WL_O<435> WL_O<434> WL_O<433> WL_O<432> VDD VSS / ++ RM_IHPSG13_512x32_c2_2P_DEC04 +XSEL<26> ADDR_N_I<3> ADDR_N_I<2> ADDR_N_I<1> ADDR_N_I<0> CS00<26> ECLK_H<26> ++ ECLK_H<27> ECLK_B<26> ECLK_B<27> WL_O<431> WL_O<430> WL_O<429> WL_O<428> ++ WL_O<427> WL_O<426> WL_O<425> WL_O<424> WL_O<423> WL_O<422> WL_O<421> ++ WL_O<420> WL_O<419> WL_O<418> WL_O<417> WL_O<416> VDD VSS / ++ RM_IHPSG13_512x32_c2_2P_DEC04 +XSEL<25> ADDR_N_I<3> ADDR_N_I<2> ADDR_N_I<1> ADDR_N_I<0> CS00<25> ECLK_H<25> ++ ECLK_H<26> ECLK_B<25> ECLK_B<26> WL_O<415> WL_O<414> WL_O<413> WL_O<412> ++ WL_O<411> WL_O<410> WL_O<409> WL_O<408> WL_O<407> WL_O<406> WL_O<405> ++ WL_O<404> WL_O<403> WL_O<402> WL_O<401> WL_O<400> VDD VSS / ++ RM_IHPSG13_512x32_c2_2P_DEC04 +XSEL<24> ADDR_N_I<3> ADDR_N_I<2> ADDR_N_I<1> ADDR_N_I<0> CS00<24> ECLK_H<24> ++ ECLK_H<25> ECLK_B<24> ECLK_B<25> WL_O<399> WL_O<398> WL_O<397> WL_O<396> ++ WL_O<395> WL_O<394> WL_O<393> WL_O<392> WL_O<391> WL_O<390> WL_O<389> ++ WL_O<388> WL_O<387> WL_O<386> WL_O<385> WL_O<384> VDD VSS / ++ RM_IHPSG13_512x32_c2_2P_DEC04 +XSEL<23> ADDR_N_I<3> ADDR_N_I<2> ADDR_N_I<1> ADDR_N_I<0> CS00<23> ECLK_H<23> ++ ECLK_H<24> ECLK_B<23> ECLK_B<24> WL_O<383> WL_O<382> WL_O<381> WL_O<380> ++ WL_O<379> WL_O<378> WL_O<377> WL_O<376> WL_O<375> WL_O<374> WL_O<373> ++ WL_O<372> WL_O<371> WL_O<370> WL_O<369> WL_O<368> VDD VSS / ++ RM_IHPSG13_512x32_c2_2P_DEC04 +XSEL<22> ADDR_N_I<3> ADDR_N_I<2> ADDR_N_I<1> ADDR_N_I<0> CS00<22> ECLK_H<22> ++ ECLK_H<23> ECLK_B<22> ECLK_B<23> WL_O<367> WL_O<366> WL_O<365> WL_O<364> ++ WL_O<363> WL_O<362> WL_O<361> WL_O<360> WL_O<359> WL_O<358> WL_O<357> ++ WL_O<356> WL_O<355> WL_O<354> WL_O<353> WL_O<352> VDD VSS / ++ RM_IHPSG13_512x32_c2_2P_DEC04 +XSEL<21> ADDR_N_I<3> ADDR_N_I<2> ADDR_N_I<1> ADDR_N_I<0> CS00<21> ECLK_H<21> ++ ECLK_H<22> ECLK_B<21> ECLK_B<22> WL_O<351> WL_O<350> WL_O<349> WL_O<348> ++ WL_O<347> WL_O<346> WL_O<345> WL_O<344> WL_O<343> WL_O<342> WL_O<341> ++ WL_O<340> WL_O<339> WL_O<338> WL_O<337> WL_O<336> VDD VSS / ++ RM_IHPSG13_512x32_c2_2P_DEC04 +XSEL<20> ADDR_N_I<3> ADDR_N_I<2> ADDR_N_I<1> ADDR_N_I<0> CS00<20> ECLK_H<20> ++ ECLK_H<21> ECLK_B<20> ECLK_B<21> WL_O<335> WL_O<334> WL_O<333> WL_O<332> ++ WL_O<331> WL_O<330> WL_O<329> WL_O<328> WL_O<327> WL_O<326> WL_O<325> ++ WL_O<324> WL_O<323> WL_O<322> WL_O<321> WL_O<320> VDD VSS / ++ RM_IHPSG13_512x32_c2_2P_DEC04 +XSEL<19> ADDR_N_I<3> ADDR_N_I<2> ADDR_N_I<1> ADDR_N_I<0> CS00<19> ECLK_H<19> ++ ECLK_H<20> ECLK_B<19> ECLK_B<20> WL_O<319> WL_O<318> WL_O<317> WL_O<316> ++ WL_O<315> WL_O<314> WL_O<313> WL_O<312> WL_O<311> WL_O<310> WL_O<309> ++ WL_O<308> WL_O<307> WL_O<306> WL_O<305> WL_O<304> VDD VSS / ++ RM_IHPSG13_512x32_c2_2P_DEC04 +XSEL<18> ADDR_N_I<3> ADDR_N_I<2> ADDR_N_I<1> ADDR_N_I<0> CS00<18> ECLK_H<18> ++ ECLK_H<19> ECLK_B<18> ECLK_B<19> WL_O<303> WL_O<302> WL_O<301> WL_O<300> ++ WL_O<299> WL_O<298> WL_O<297> WL_O<296> WL_O<295> WL_O<294> WL_O<293> ++ WL_O<292> WL_O<291> WL_O<290> WL_O<289> WL_O<288> VDD VSS / ++ RM_IHPSG13_512x32_c2_2P_DEC04 +XSEL<17> ADDR_N_I<3> ADDR_N_I<2> ADDR_N_I<1> ADDR_N_I<0> CS00<17> ECLK_H<17> ++ ECLK_H<18> ECLK_B<17> ECLK_B<18> WL_O<287> WL_O<286> WL_O<285> WL_O<284> ++ WL_O<283> WL_O<282> WL_O<281> WL_O<280> WL_O<279> WL_O<278> WL_O<277> ++ WL_O<276> WL_O<275> WL_O<274> WL_O<273> WL_O<272> VDD VSS / ++ RM_IHPSG13_512x32_c2_2P_DEC04 +XSEL<16> ADDR_N_I<3> ADDR_N_I<2> ADDR_N_I<1> ADDR_N_I<0> CS00<16> ECLK_H<16> ++ ECLK_H<17> ECLK_B<16> ECLK_B<17> WL_O<271> WL_O<270> WL_O<269> WL_O<268> ++ WL_O<267> WL_O<266> WL_O<265> WL_O<264> WL_O<263> WL_O<262> WL_O<261> ++ WL_O<260> WL_O<259> WL_O<258> WL_O<257> WL_O<256> VDD VSS / ++ RM_IHPSG13_512x32_c2_2P_DEC04 +XSEL<15> ADDR_N_I<3> ADDR_N_I<2> ADDR_N_I<1> ADDR_N_I<0> CS00<15> ECLK_H<15> ++ ECLK_H<16> ECLK_B<15> ECLK_B<16> WL_O<255> WL_O<254> WL_O<253> WL_O<252> ++ WL_O<251> WL_O<250> WL_O<249> WL_O<248> WL_O<247> WL_O<246> WL_O<245> ++ WL_O<244> WL_O<243> WL_O<242> WL_O<241> WL_O<240> VDD VSS / ++ RM_IHPSG13_512x32_c2_2P_DEC04 +XSEL<14> ADDR_N_I<3> ADDR_N_I<2> ADDR_N_I<1> ADDR_N_I<0> CS00<14> ECLK_H<14> ++ ECLK_H<15> ECLK_B<14> ECLK_B<15> WL_O<239> WL_O<238> WL_O<237> WL_O<236> ++ WL_O<235> WL_O<234> WL_O<233> WL_O<232> WL_O<231> WL_O<230> WL_O<229> ++ WL_O<228> WL_O<227> WL_O<226> WL_O<225> WL_O<224> VDD VSS / ++ RM_IHPSG13_512x32_c2_2P_DEC04 +XSEL<13> ADDR_N_I<3> ADDR_N_I<2> ADDR_N_I<1> ADDR_N_I<0> CS00<13> ECLK_H<13> ++ ECLK_H<14> ECLK_B<13> ECLK_B<14> WL_O<223> WL_O<222> WL_O<221> WL_O<220> ++ WL_O<219> WL_O<218> WL_O<217> WL_O<216> WL_O<215> WL_O<214> WL_O<213> ++ WL_O<212> WL_O<211> WL_O<210> WL_O<209> WL_O<208> VDD VSS / ++ RM_IHPSG13_512x32_c2_2P_DEC04 +XSEL<12> ADDR_N_I<3> ADDR_N_I<2> ADDR_N_I<1> ADDR_N_I<0> CS00<12> ECLK_H<12> ++ ECLK_H<13> ECLK_B<12> ECLK_B<13> WL_O<207> WL_O<206> WL_O<205> WL_O<204> ++ WL_O<203> WL_O<202> WL_O<201> WL_O<200> WL_O<199> WL_O<198> WL_O<197> ++ WL_O<196> WL_O<195> WL_O<194> WL_O<193> WL_O<192> VDD VSS / ++ RM_IHPSG13_512x32_c2_2P_DEC04 +XSEL<11> ADDR_N_I<3> ADDR_N_I<2> ADDR_N_I<1> ADDR_N_I<0> CS00<11> ECLK_H<11> ++ ECLK_H<12> ECLK_B<11> ECLK_B<12> WL_O<191> WL_O<190> WL_O<189> WL_O<188> ++ WL_O<187> WL_O<186> WL_O<185> WL_O<184> WL_O<183> WL_O<182> WL_O<181> ++ WL_O<180> WL_O<179> WL_O<178> WL_O<177> WL_O<176> VDD VSS / ++ RM_IHPSG13_512x32_c2_2P_DEC04 +XSEL<10> ADDR_N_I<3> ADDR_N_I<2> ADDR_N_I<1> ADDR_N_I<0> CS00<10> ECLK_H<10> ++ ECLK_H<11> ECLK_B<10> ECLK_B<11> WL_O<175> WL_O<174> WL_O<173> WL_O<172> ++ WL_O<171> WL_O<170> WL_O<169> WL_O<168> WL_O<167> WL_O<166> WL_O<165> ++ WL_O<164> WL_O<163> WL_O<162> WL_O<161> WL_O<160> VDD VSS / ++ RM_IHPSG13_512x32_c2_2P_DEC04 +XSEL<9> ADDR_N_I<3> ADDR_N_I<2> ADDR_N_I<1> ADDR_N_I<0> CS00<9> ECLK_H<9> ++ ECLK_H<10> ECLK_B<9> ECLK_B<10> WL_O<159> WL_O<158> WL_O<157> WL_O<156> ++ WL_O<155> WL_O<154> WL_O<153> WL_O<152> WL_O<151> WL_O<150> WL_O<149> ++ WL_O<148> WL_O<147> WL_O<146> WL_O<145> WL_O<144> VDD VSS / ++ RM_IHPSG13_512x32_c2_2P_DEC04 +XSEL<8> ADDR_N_I<3> ADDR_N_I<2> ADDR_N_I<1> ADDR_N_I<0> CS00<8> ECLK_H<8> ++ ECLK_H<9> ECLK_B<8> ECLK_B<9> WL_O<143> WL_O<142> WL_O<141> WL_O<140> ++ WL_O<139> WL_O<138> WL_O<137> WL_O<136> WL_O<135> WL_O<134> WL_O<133> ++ WL_O<132> WL_O<131> WL_O<130> WL_O<129> WL_O<128> VDD VSS / ++ RM_IHPSG13_512x32_c2_2P_DEC04 +XSEL<7> ADDR_N_I<3> ADDR_N_I<2> ADDR_N_I<1> ADDR_N_I<0> CS00<7> ECLK_H<7> ++ ECLK_H<8> ECLK_B<7> ECLK_B<8> WL_O<127> WL_O<126> WL_O<125> WL_O<124> ++ WL_O<123> WL_O<122> WL_O<121> WL_O<120> WL_O<119> WL_O<118> WL_O<117> ++ WL_O<116> WL_O<115> WL_O<114> WL_O<113> WL_O<112> VDD VSS / ++ RM_IHPSG13_512x32_c2_2P_DEC04 +XSEL<6> ADDR_N_I<3> ADDR_N_I<2> ADDR_N_I<1> ADDR_N_I<0> CS00<6> ECLK_H<6> ++ ECLK_H<7> ECLK_B<6> ECLK_B<7> WL_O<111> WL_O<110> WL_O<109> WL_O<108> ++ WL_O<107> WL_O<106> WL_O<105> WL_O<104> WL_O<103> WL_O<102> WL_O<101> ++ WL_O<100> WL_O<99> WL_O<98> WL_O<97> WL_O<96> VDD VSS / ++ RM_IHPSG13_512x32_c2_2P_DEC04 +XSEL<5> ADDR_N_I<3> ADDR_N_I<2> ADDR_N_I<1> ADDR_N_I<0> CS00<5> ECLK_H<5> ++ ECLK_H<6> ECLK_B<5> ECLK_B<6> WL_O<95> WL_O<94> WL_O<93> WL_O<92> WL_O<91> ++ WL_O<90> WL_O<89> WL_O<88> WL_O<87> WL_O<86> WL_O<85> WL_O<84> WL_O<83> ++ WL_O<82> WL_O<81> WL_O<80> VDD VSS / RM_IHPSG13_512x32_c2_2P_DEC04 +XSEL<4> ADDR_N_I<3> ADDR_N_I<2> ADDR_N_I<1> ADDR_N_I<0> CS00<4> ECLK_H<4> ++ ECLK_H<5> ECLK_B<4> ECLK_B<5> WL_O<79> WL_O<78> WL_O<77> WL_O<76> WL_O<75> ++ WL_O<74> WL_O<73> WL_O<72> WL_O<71> WL_O<70> WL_O<69> WL_O<68> WL_O<67> ++ WL_O<66> WL_O<65> WL_O<64> VDD VSS / RM_IHPSG13_512x32_c2_2P_DEC04 +XSEL<3> ADDR_N_I<3> ADDR_N_I<2> ADDR_N_I<1> ADDR_N_I<0> CS00<3> ECLK_H<3> ++ ECLK_H<4> ECLK_B<3> ECLK_B<4> WL_O<63> WL_O<62> WL_O<61> WL_O<60> WL_O<59> ++ WL_O<58> WL_O<57> WL_O<56> WL_O<55> WL_O<54> WL_O<53> WL_O<52> WL_O<51> ++ WL_O<50> WL_O<49> WL_O<48> VDD VSS / RM_IHPSG13_512x32_c2_2P_DEC04 +XSEL<2> ADDR_N_I<3> ADDR_N_I<2> ADDR_N_I<1> ADDR_N_I<0> CS00<2> ECLK_H<2> ++ ECLK_H<3> ECLK_B<2> ECLK_B<3> WL_O<47> WL_O<46> WL_O<45> WL_O<44> WL_O<43> ++ WL_O<42> WL_O<41> WL_O<40> WL_O<39> WL_O<38> WL_O<37> WL_O<36> WL_O<35> ++ WL_O<34> WL_O<33> WL_O<32> VDD VSS / RM_IHPSG13_512x32_c2_2P_DEC04 +XSEL<1> ADDR_N_I<3> ADDR_N_I<2> ADDR_N_I<1> ADDR_N_I<0> CS00<1> ECLK_H<1> ++ ECLK_H<2> ECLK_B<1> ECLK_B<2> WL_O<31> WL_O<30> WL_O<29> WL_O<28> WL_O<27> ++ WL_O<26> WL_O<25> WL_O<24> WL_O<23> WL_O<22> WL_O<21> WL_O<20> WL_O<19> ++ WL_O<18> WL_O<17> WL_O<16> VDD VSS / RM_IHPSG13_512x32_c2_2P_DEC04 +XSEL<0> ADDR_N_I<3> ADDR_N_I<2> ADDR_N_I<1> ADDR_N_I<0> CS00<0> ECLK_I ++ ECLK_H<1> ECLK_B<0> ECLK_B<1> WL_O<15> WL_O<14> WL_O<13> WL_O<12> WL_O<11> ++ WL_O<10> WL_O<9> WL_O<8> WL_O<7> WL_O<6> WL_O<5> WL_O<4> WL_O<3> WL_O<2> ++ WL_O<1> WL_O<0> VDD VSS / RM_IHPSG13_512x32_c2_2P_DEC04 +XDEC10<9> ADDR_N_I<7> ADDR_N_I<6> CS04<1> CS02<6> VDD VSS / ++ RM_IHPSG13_512x32_c2_2P_DEC02 +XDEC10<8> ADDR_N_I<7> ADDR_N_I<6> CS04<0> CS02<2> VDD VSS / ++ RM_IHPSG13_512x32_c2_2P_DEC02 +XDEC10<7> ADDR_N_I<5> ADDR_N_I<4> CS02<7> CS00<30> VDD VSS / ++ RM_IHPSG13_512x32_c2_2P_DEC02 +XDEC10<6> ADDR_N_I<5> ADDR_N_I<4> CS02<6> CS00<26> VDD VSS / ++ RM_IHPSG13_512x32_c2_2P_DEC02 +XDEC10<5> ADDR_N_I<5> ADDR_N_I<4> CS02<5> CS00<22> VDD VSS / ++ RM_IHPSG13_512x32_c2_2P_DEC02 +XDEC10<4> ADDR_N_I<5> ADDR_N_I<4> CS02<4> CS00<18> VDD VSS / ++ RM_IHPSG13_512x32_c2_2P_DEC02 +XDEC10<3> ADDR_N_I<5> ADDR_N_I<4> CS02<3> CS00<14> VDD VSS / ++ RM_IHPSG13_512x32_c2_2P_DEC02 +XDEC10<2> ADDR_N_I<5> ADDR_N_I<4> CS02<2> CS00<10> VDD VSS / ++ RM_IHPSG13_512x32_c2_2P_DEC02 +XDEC10<1> ADDR_N_I<5> ADDR_N_I<4> CS02<1> CS00<6> VDD VSS / ++ RM_IHPSG13_512x32_c2_2P_DEC02 +XDEC10<0> ADDR_N_I<5> ADDR_N_I<4> CS02<0> CS00<2> VDD VSS / ++ RM_IHPSG13_512x32_c2_2P_DEC02 +XDEC01<10> ADDR_N_I<9> ADDR_N_I<8> CS_I CS04<1> VDD VSS / ++ RM_IHPSG13_512x32_c2_2P_DEC01 +XDEC01<9> ADDR_N_I<7> ADDR_N_I<6> CS04<1> CS02<5> VDD VSS / ++ RM_IHPSG13_512x32_c2_2P_DEC01 +XDEC01<8> ADDR_N_I<7> ADDR_N_I<6> CS04<0> CS02<1> VDD VSS / ++ RM_IHPSG13_512x32_c2_2P_DEC01 +XDEC01<7> ADDR_N_I<5> ADDR_N_I<4> CS02<7> CS00<29> VDD VSS / ++ RM_IHPSG13_512x32_c2_2P_DEC01 +XDEC01<6> ADDR_N_I<5> ADDR_N_I<4> CS02<6> CS00<25> VDD VSS / ++ RM_IHPSG13_512x32_c2_2P_DEC01 +XDEC01<5> ADDR_N_I<5> ADDR_N_I<4> CS02<5> CS00<21> VDD VSS / ++ RM_IHPSG13_512x32_c2_2P_DEC01 +XDEC01<4> ADDR_N_I<5> ADDR_N_I<4> CS02<4> CS00<17> VDD VSS / ++ RM_IHPSG13_512x32_c2_2P_DEC01 +XDEC01<3> ADDR_N_I<5> ADDR_N_I<4> CS02<3> CS00<13> VDD VSS / ++ RM_IHPSG13_512x32_c2_2P_DEC01 +XDEC01<2> ADDR_N_I<5> ADDR_N_I<4> CS02<2> CS00<9> VDD VSS / ++ RM_IHPSG13_512x32_c2_2P_DEC01 +XDEC01<1> ADDR_N_I<5> ADDR_N_I<4> CS02<1> CS00<5> VDD VSS / ++ RM_IHPSG13_512x32_c2_2P_DEC01 +XDEC01<0> ADDR_N_I<5> ADDR_N_I<4> CS02<0> CS00<1> VDD VSS / ++ RM_IHPSG13_512x32_c2_2P_DEC01 +XL2<258> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<257> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<256> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<255> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<254> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<253> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<252> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<251> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<250> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<249> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<248> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<247> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<246> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<245> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<244> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<243> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<242> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<241> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<240> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<239> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<238> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<237> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<236> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<235> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<234> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<233> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<232> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<231> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<230> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<229> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<228> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<227> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<226> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<225> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<224> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<223> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<222> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<221> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<220> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<219> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<218> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<217> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<216> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<215> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<214> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<213> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<212> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<211> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<210> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<209> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<208> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<207> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<206> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<205> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<204> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<203> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<202> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<201> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<200> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<199> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<198> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<197> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<196> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<195> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<194> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<193> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<192> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<191> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<190> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<189> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<188> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<187> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<186> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<185> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<184> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<183> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<182> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<181> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<180> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<179> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<178> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<177> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<176> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<175> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<174> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<173> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<172> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<171> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<170> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<169> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<168> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<167> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<166> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<165> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<164> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<163> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<162> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<161> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<160> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<159> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<158> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<157> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<156> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<155> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<154> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<153> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<152> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<151> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<150> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<149> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<148> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<147> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<146> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<145> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<144> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<143> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<142> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<141> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<140> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<139> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<138> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<137> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<136> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<135> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<134> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<133> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<132> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<131> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<130> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<129> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<128> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<127> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<126> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<125> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<124> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<123> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<122> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<121> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<120> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<119> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<118> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<117> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<116> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<115> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<114> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<113> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<112> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<111> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<110> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<109> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<108> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<107> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<106> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<105> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<104> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<103> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<102> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<101> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<100> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<99> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<98> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<97> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<96> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<95> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<94> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<93> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<92> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<91> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<90> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<89> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<88> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<87> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<86> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<85> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<84> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<83> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<82> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<81> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<80> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<79> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<78> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<77> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<76> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<75> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<74> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<73> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<72> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<71> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<70> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<69> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<68> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<67> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<66> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<65> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<64> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<63> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<62> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<61> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<60> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<59> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<58> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<57> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<56> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<55> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<54> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<53> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<52> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<51> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<50> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<49> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<48> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<47> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<46> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<45> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<44> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<43> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<42> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<41> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<40> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<39> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<38> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<37> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<36> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<35> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<34> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<33> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<32> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<31> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<30> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<29> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<28> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<27> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<26> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<25> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<24> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<23> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<22> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<21> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<20> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<19> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<18> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<17> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<16> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<15> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<14> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<13> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<12> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<11> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<10> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<9> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<8> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<7> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<6> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<5> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<4> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<3> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<2> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<1> VDD VSS / RSC_IHPSG13_FILLCAP8 +XDEC00<10> ADDR_N_I<9> ADDR_N_I<8> CS_I CS04<0> VDD VSS / ++ RM_IHPSG13_512x32_c2_2P_DEC00 +XDEC00<9> ADDR_N_I<7> ADDR_N_I<6> CS04<1> CS02<4> VDD VSS / ++ RM_IHPSG13_512x32_c2_2P_DEC00 +XDEC00<8> ADDR_N_I<7> ADDR_N_I<6> CS04<0> CS02<0> VDD VSS / ++ RM_IHPSG13_512x32_c2_2P_DEC00 +XDEC00<7> ADDR_N_I<5> ADDR_N_I<4> CS02<7> CS00<28> VDD VSS / ++ RM_IHPSG13_512x32_c2_2P_DEC00 +XDEC00<6> ADDR_N_I<5> ADDR_N_I<4> CS02<6> CS00<24> VDD VSS / ++ RM_IHPSG13_512x32_c2_2P_DEC00 +XDEC00<5> ADDR_N_I<5> ADDR_N_I<4> CS02<5> CS00<20> VDD VSS / ++ RM_IHPSG13_512x32_c2_2P_DEC00 +XDEC00<4> ADDR_N_I<5> ADDR_N_I<4> CS02<4> CS00<16> VDD VSS / ++ RM_IHPSG13_512x32_c2_2P_DEC00 +XDEC00<3> ADDR_N_I<5> ADDR_N_I<4> CS02<3> CS00<12> VDD VSS / ++ RM_IHPSG13_512x32_c2_2P_DEC00 +XDEC00<2> ADDR_N_I<5> ADDR_N_I<4> CS02<2> CS00<8> VDD VSS / ++ RM_IHPSG13_512x32_c2_2P_DEC00 +XDEC00<1> ADDR_N_I<5> ADDR_N_I<4> CS02<1> CS00<4> VDD VSS / ++ RM_IHPSG13_512x32_c2_2P_DEC00 +XDEC00<0> ADDR_N_I<5> ADDR_N_I<4> CS02<0> CS00<0> VDD VSS / ++ RM_IHPSG13_512x32_c2_2P_DEC00 +XDEC11<9> ADDR_N_I<7> ADDR_N_I<6> CS04<1> CS02<7> VDD VSS / ++ RM_IHPSG13_512x32_c2_2P_DEC03 +XDEC11<8> ADDR_N_I<7> ADDR_N_I<6> CS04<0> CS02<3> VDD VSS / ++ RM_IHPSG13_512x32_c2_2P_DEC03 +XDEC11<7> ADDR_N_I<5> ADDR_N_I<4> CS02<7> CS00<31> VDD VSS / ++ RM_IHPSG13_512x32_c2_2P_DEC03 +XDEC11<6> ADDR_N_I<5> ADDR_N_I<4> CS02<6> CS00<27> VDD VSS / ++ RM_IHPSG13_512x32_c2_2P_DEC03 +XDEC11<5> ADDR_N_I<5> ADDR_N_I<4> CS02<5> CS00<23> VDD VSS / ++ RM_IHPSG13_512x32_c2_2P_DEC03 +XDEC11<4> ADDR_N_I<5> ADDR_N_I<4> CS02<4> CS00<19> VDD VSS / ++ RM_IHPSG13_512x32_c2_2P_DEC03 +XDEC11<3> ADDR_N_I<5> ADDR_N_I<4> CS02<3> CS00<15> VDD VSS / ++ RM_IHPSG13_512x32_c2_2P_DEC03 +XDEC11<2> ADDR_N_I<5> ADDR_N_I<4> CS02<2> CS00<11> VDD VSS / ++ RM_IHPSG13_512x32_c2_2P_DEC03 +XDEC11<1> ADDR_N_I<5> ADDR_N_I<4> CS02<1> CS00<7> VDD VSS / ++ RM_IHPSG13_512x32_c2_2P_DEC03 +XDEC11<0> ADDR_N_I<5> ADDR_N_I<4> CS02<0> CS00<3> VDD VSS / ++ RM_IHPSG13_512x32_c2_2P_DEC03 +XI0 ADDR_N_I<9> VDD VSS / RSC_IHPSG13_TIEL +.ENDS +.SUBCKT RM_IHPSG13_512x32_c2_2P_ROWREG9 ACLK_N_I ADDR_I<8> ADDR_I<7> ADDR_I<6> ADDR_I<5> ++ ADDR_I<4> ADDR_I<3> ADDR_I<2> ADDR_I<1> ADDR_I<0> ADDR_N_O<8> ADDR_N_O<7> ++ ADDR_N_O<6> ADDR_N_O<5> ADDR_N_O<4> ADDR_N_O<3> ADDR_N_O<2> ADDR_N_O<1> ++ ADDR_N_O<0> BIST_ADDR_I<8> BIST_ADDR_I<7> BIST_ADDR_I<6> BIST_ADDR_I<5> ++ BIST_ADDR_I<4> BIST_ADDR_I<3> BIST_ADDR_I<2> BIST_ADDR_I<1> BIST_ADDR_I<0> ++ BIST_EN_I VDD VSS +XDFF<8> BIST_EN_I BIST_ADDR_I<8> ACLK_N_I ADDR_I<8> q_int<8> net04<0> VDD ++ VSS / RSC_IHPSG13_DFNQMX2IX1 +XDFF<7> BIST_EN_I BIST_ADDR_I<7> ACLK_N_I ADDR_I<7> q_int<7> net04<1> VDD ++ VSS / RSC_IHPSG13_DFNQMX2IX1 +XDFF<6> BIST_EN_I BIST_ADDR_I<6> ACLK_N_I ADDR_I<6> q_int<6> net04<2> VDD ++ VSS / RSC_IHPSG13_DFNQMX2IX1 +XDFF<5> BIST_EN_I BIST_ADDR_I<5> ACLK_N_I ADDR_I<5> q_int<5> net04<3> VDD ++ VSS / RSC_IHPSG13_DFNQMX2IX1 +XDFF<4> BIST_EN_I BIST_ADDR_I<4> ACLK_N_I ADDR_I<4> q_int<4> net04<4> VDD ++ VSS / RSC_IHPSG13_DFNQMX2IX1 +XDFF<3> BIST_EN_I BIST_ADDR_I<3> ACLK_N_I ADDR_I<3> q_int<3> net04<5> VDD ++ VSS / RSC_IHPSG13_DFNQMX2IX1 +XDFF<2> BIST_EN_I BIST_ADDR_I<2> ACLK_N_I ADDR_I<2> q_int<2> net04<6> VDD ++ VSS / RSC_IHPSG13_DFNQMX2IX1 +XDFF<1> BIST_EN_I BIST_ADDR_I<1> ACLK_N_I ADDR_I<1> q_int<1> net04<7> VDD ++ VSS / RSC_IHPSG13_DFNQMX2IX1 +XDFF<0> BIST_EN_I BIST_ADDR_I<0> ACLK_N_I ADDR_I<0> q_int<0> net04<8> VDD ++ VSS / RSC_IHPSG13_DFNQMX2IX1 +XDRV<8> qn_int<8> ADDR_N_O<8> VDD VSS / RSC_IHPSG13_CINVX8 +XDRV<7> qn_int<7> ADDR_N_O<7> VDD VSS / RSC_IHPSG13_CINVX8 +XDRV<6> qn_int<6> ADDR_N_O<6> VDD VSS / RSC_IHPSG13_CINVX8 +XDRV<5> qn_int<5> ADDR_N_O<5> VDD VSS / RSC_IHPSG13_CINVX8 +XDRV<4> qn_int<4> ADDR_N_O<4> VDD VSS / RSC_IHPSG13_CINVX8 +XDRV<3> qn_int<3> ADDR_N_O<3> VDD VSS / RSC_IHPSG13_CINVX8 +XDRV<2> qn_int<2> ADDR_N_O<2> VDD VSS / RSC_IHPSG13_CINVX8 +XDRV<1> qn_int<1> ADDR_N_O<1> VDD VSS / RSC_IHPSG13_CINVX8 +XDRV<0> qn_int<0> ADDR_N_O<0> VDD VSS / RSC_IHPSG13_CINVX8 +XINV<8> q_int<8> qn_int<8> VDD VSS / RSC_IHPSG13_CINVX2 +XINV<7> q_int<7> qn_int<7> VDD VSS / RSC_IHPSG13_CINVX2 +XINV<6> q_int<6> qn_int<6> VDD VSS / RSC_IHPSG13_CINVX2 +XINV<5> q_int<5> qn_int<5> VDD VSS / RSC_IHPSG13_CINVX2 +XINV<4> q_int<4> qn_int<4> VDD VSS / RSC_IHPSG13_CINVX2 +XINV<3> q_int<3> qn_int<3> VDD VSS / RSC_IHPSG13_CINVX2 +XINV<2> q_int<2> qn_int<2> VDD VSS / RSC_IHPSG13_CINVX2 +XINV<1> q_int<1> qn_int<1> VDD VSS / RSC_IHPSG13_CINVX2 +XINV<0> q_int<0> qn_int<0> VDD VSS / RSC_IHPSG13_CINVX2 +.ENDS + +.SUBCKT RM_IHPSG13_512x32_c2_2P_DLY_MUX A SEL Z VDD VSS +XI11 net4 Z VDD VSS / RSC_IHPSG13_CINVX2 +XI8 A D<3> SEL net4 VDD VSS / RSC_IHPSG13_MX2IX1 +XI20<3> D<2> D<3> VDD VSS / RSC_IHPSG13_CDLYX1 +XI20<2> D<1> D<2> VDD VSS / RSC_IHPSG13_CDLYX1 +XI20<1> A D<1> VDD VSS / RSC_IHPSG13_CDLYX1 +.ENDS +.SUBCKT RM_IHPSG13_512x32_c2_2P_CTRL ACLK_N BIST_CK_I BIST_CS_I BIST_EN BIST_RE_I ++ BIST_WE_I B_TIEL_O CK_I CS_I DCLK ECLK PULSE_H PULSE_L PULSE_O RCLK RE_I ++ ROW_CS WCLK WE_I VDD VSS +XI17 ck_regs we col_we VDD VSS / RSC_IHPSG13_DFNQX2 +XI16 ck_regs re col_re VDD VSS / RSC_IHPSG13_DFNQX2 +XI18 ck_regs cs net7 VDD VSS / RSC_IHPSG13_DFNQX2 +XI71 ACLK_N net012 PULSE_O VDD VSS / RSC_IHPSG13_DFNQX2 +XI77 col_we net017 net016 VDD VSS / RSC_IHPSG13_CNAND2X2 +XI76 col_re net017 net018 VDD VSS / RSC_IHPSG13_CNAND2X2 +XI15 ck_dly WEorREandCS aclk VDD VSS / RSC_IHPSG13_CGATEPX4 +XI14 ck WEandCS DCLK VDD VSS / RSC_IHPSG13_CGATEPX4 +XI60 net7 ROW_CS VDD VSS / RSC_IHPSG13_CBUFX8 +XI73 PULSE_O net012 VDD VSS / RSC_IHPSG13_CINVX2 +XI8 net017 net8 VDD VSS / RSC_IHPSG13_CINVX2 +XCAPS4<7> VDD VSS / RSC_IHPSG13_FILLCAP4 +XCAPS4<6> VDD VSS / RSC_IHPSG13_FILLCAP4 +XCAPS4<5> VDD VSS / RSC_IHPSG13_FILLCAP4 +XCAPS4<4> VDD VSS / RSC_IHPSG13_FILLCAP4 +XCAPS4<3> VDD VSS / RSC_IHPSG13_FILLCAP4 +XCAPS4<2> VDD VSS / RSC_IHPSG13_FILLCAP4 +XCAPS4<1> VDD VSS / RSC_IHPSG13_FILLCAP4 +XBM_TIEL B_TIEL_O VDD VSS / RSC_IHPSG13_TIEL +XI64 ck ck_dly VDD VSS / RSC_IHPSG13_CDLYX2 +XI86 CS_I BIST_CS_I BIST_EN cs VDD VSS / RSC_IHPSG13_MX2X2 +XI87 CK_I BIST_CK_I BIST_EN ck VDD VSS / RSC_IHPSG13_MX2X2 +XI85 WE_I BIST_WE_I BIST_EN we VDD VSS / RSC_IHPSG13_MX2X2 +XI84 RE_I BIST_RE_I BIST_EN re VDD VSS / RSC_IHPSG13_MX2X2 +XI48 ck_dly ck_regs VDD VSS / RSC_IHPSG13_CINVX4 +XI81 net016 WCLK VDD VSS / RSC_IHPSG13_CINVX4 +XI80 net018 RCLK VDD VSS / RSC_IHPSG13_CINVX4 +XI78 net8 net020 VDD VSS / RSC_IHPSG13_CINVX4 +XCAPS8<7> VDD VSS / RSC_IHPSG13_FILLCAP8 +XCAPS8<6> VDD VSS / RSC_IHPSG13_FILLCAP8 +XCAPS8<5> VDD VSS / RSC_IHPSG13_FILLCAP8 +XCAPS8<4> VDD VSS / RSC_IHPSG13_FILLCAP8 +XCAPS8<3> VDD VSS / RSC_IHPSG13_FILLCAP8 +XCAPS8<2> VDD VSS / RSC_IHPSG13_FILLCAP8 +XCAPS8<1> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI6 PULSE_L PULSE_H net017 VDD VSS / RSC_IHPSG13_XOR2X2 +XI22 we cs WEandCS VDD VSS / RSC_IHPSG13_AND2X2 +XI79 net020 ECLK VDD VSS / RSC_IHPSG13_CINVX8 +XI63 aclk ACLK_N VDD VSS / RSC_IHPSG13_CINVX8 +XI21 re we cs WEorREandCS VDD VSS / RSC_IHPSG13_OA12X1 +.ENDS +.SUBCKT RM_IHPSG13_512x32_c2_2P_COLDEC5 ACLK_N ADDR<4> ADDR<3> ADDR<2> ADDR<1> ADDR<0> ++ ADDR_COL<1> ADDR_COL<0> ADDR_DEC<7> ADDR_DEC<6> ADDR_DEC<5> ADDR_DEC<4> ++ ADDR_DEC<3> ADDR_DEC<2> ADDR_DEC<1> ADDR_DEC<0> BIST_ADDR<4> BIST_ADDR<3> ++ BIST_ADDR<2> BIST_ADDR<1> BIST_ADDR<0> BIST_EN_I VDD VSS +XI17<4> VDD VSS / RSC_IHPSG13_FILLCAP4 +XI17<3> VDD VSS / RSC_IHPSG13_FILLCAP4 +XI17<2> VDD VSS / RSC_IHPSG13_FILLCAP4 +XI17<1> VDD VSS / RSC_IHPSG13_FILLCAP4 +XI1<7> PADR<0> PADR<1> PADR<2> addr_n<7> VDD VSS / RSC_IHPSG13_NAND3X2 +XI1<6> NADR<0> PADR<1> PADR<2> addr_n<6> VDD VSS / RSC_IHPSG13_NAND3X2 +XI1<5> PADR<0> NADR<1> PADR<2> addr_n<5> VDD VSS / RSC_IHPSG13_NAND3X2 +XI1<4> NADR<0> NADR<1> PADR<2> addr_n<4> VDD VSS / RSC_IHPSG13_NAND3X2 +XI1<3> PADR<0> PADR<1> NADR<2> addr_n<3> VDD VSS / RSC_IHPSG13_NAND3X2 +XI1<2> NADR<0> PADR<1> NADR<2> addr_n<2> VDD VSS / RSC_IHPSG13_NAND3X2 +XI1<1> PADR<0> NADR<1> NADR<2> addr_n<1> VDD VSS / RSC_IHPSG13_NAND3X2 +XI1<0> NADR<0> NADR<1> NADR<2> addr_n<0> VDD VSS / RSC_IHPSG13_NAND3X2 +XDFF<4> BIST_EN_I BIST_ADDR<4> ACLK_N ADDR<4> addr_int<1> net13<0> VDD ++ VSS / RSC_IHPSG13_DFNQMX2IX1 +XDFF<3> BIST_EN_I BIST_ADDR<3> ACLK_N ADDR<3> addr_int<0> net13<1> VDD ++ VSS / RSC_IHPSG13_DFNQMX2IX1 +XDFF<2> BIST_EN_I BIST_ADDR<2> ACLK_N ADDR<2> padr_int<2> net13<2> VDD ++ VSS / RSC_IHPSG13_DFNQMX2IX1 +XDFF<1> BIST_EN_I BIST_ADDR<1> ACLK_N ADDR<1> padr_int<1> net13<3> VDD ++ VSS / RSC_IHPSG13_DFNQMX2IX1 +XDFF<0> BIST_EN_I BIST_ADDR<0> ACLK_N ADDR<0> padr_int<0> net13<4> VDD ++ VSS / RSC_IHPSG13_DFNQMX2IX1 +XI3<2> padr_int<2> NADR<2> VDD VSS / RSC_IHPSG13_INVX2 +XI3<1> padr_int<1> NADR<1> VDD VSS / RSC_IHPSG13_INVX2 +XI3<0> padr_int<0> NADR<0> VDD VSS / RSC_IHPSG13_INVX2 +XI2<7> addr_n<7> ADDR_DEC<7> VDD VSS / RSC_IHPSG13_INVX2 +XI2<6> addr_n<6> ADDR_DEC<6> VDD VSS / RSC_IHPSG13_INVX2 +XI2<5> addr_n<5> ADDR_DEC<5> VDD VSS / RSC_IHPSG13_INVX2 +XI2<4> addr_n<4> ADDR_DEC<4> VDD VSS / RSC_IHPSG13_INVX2 +XI2<3> addr_n<3> ADDR_DEC<3> VDD VSS / RSC_IHPSG13_INVX2 +XI2<2> addr_n<2> ADDR_DEC<2> VDD VSS / RSC_IHPSG13_INVX2 +XI2<1> addr_n<1> ADDR_DEC<1> VDD VSS / RSC_IHPSG13_INVX2 +XI2<0> addr_n<0> ADDR_DEC<0> VDD VSS / RSC_IHPSG13_INVX2 +XI15<2> NADR<2> PADR<2> VDD VSS / RSC_IHPSG13_INVX2 +XI15<1> NADR<1> PADR<1> VDD VSS / RSC_IHPSG13_INVX2 +XI15<0> NADR<0> PADR<0> VDD VSS / RSC_IHPSG13_INVX2 +XI13<1> addr_int<1> ADDR_COL<1> VDD VSS / RSC_IHPSG13_CBUFX2 +XI13<0> addr_int<0> ADDR_COL<0> VDD VSS / RSC_IHPSG13_CBUFX2 +XI14<5> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI14<4> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI14<3> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI14<2> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI14<1> VDD VSS / RSC_IHPSG13_FILLCAP8 +.ENDS +.SUBCKT RM_IHPSG13_512x32_c2_2P_BLDRV A_BLC<3> A_BLC<2> A_BLC<1> A_BLC<0> A_BLC_SEL ++ A_BLT<3> A_BLT<2> A_BLT<1> A_BLT<0> A_BLT_SEL A_PRE_N A_SEL_P<3> A_SEL_P<2> ++ A_SEL_P<1> A_SEL_P<0> A_WR_ONE A_WR_ZERO B_BLC<3> B_BLC<2> B_BLC<1> B_BLC<0> ++ B_BLC_SEL B_BLT<3> B_BLT<2> B_BLT<1> B_BLT<0> B_BLT_SEL B_PRE_N B_SEL_P<3> ++ B_SEL_P<2> B_SEL_P<1> B_SEL_P<0> B_WR_ONE B_WR_ZERO VDD VSS +MA_CWN<3> A_BLC<3> A_BLC_NMOS_DRIVE<3> VSS VSS sg13_lv_nmos m=1 ++ w=4.82u l=130.00n ng=2 nrd=0 nrs=0 +MA_CWN<2> A_BLC<2> A_BLC_NMOS_DRIVE<2> VSS VSS sg13_lv_nmos m=1 ++ w=4.82u l=130.00n ng=2 nrd=0 nrs=0 +MA_CWN<1> A_BLC<1> A_BLC_NMOS_DRIVE<1> VSS VSS sg13_lv_nmos m=1 ++ w=4.82u l=130.00n ng=2 nrd=0 nrs=0 +MA_CWN<0> A_BLC<0> A_BLC_NMOS_DRIVE<0> VSS VSS sg13_lv_nmos m=1 ++ w=4.82u l=130.00n ng=2 nrd=0 nrs=0 +MA_TWN<3> A_BLT<3> A_BLT_NMOS_DRIVE<3> VSS VSS sg13_lv_nmos m=1 ++ w=4.82u l=130.00n ng=2 nrd=0 nrs=0 +MA_TWN<2> A_BLT<2> A_BLT_NMOS_DRIVE<2> VSS VSS sg13_lv_nmos m=1 ++ w=4.82u l=130.00n ng=2 nrd=0 nrs=0 +MA_TWN<1> A_BLT<1> A_BLT_NMOS_DRIVE<1> VSS VSS sg13_lv_nmos m=1 ++ w=4.82u l=130.00n ng=2 nrd=0 nrs=0 +MA_TWN<0> A_BLT<0> A_BLT_NMOS_DRIVE<0> VSS VSS sg13_lv_nmos m=1 ++ w=4.82u l=130.00n ng=2 nrd=0 nrs=0 +MB_TWN<3> B_BLT<3> B_BLT_NMOS_DRIVE<3> VSS VSS sg13_lv_nmos m=1 ++ w=4.82u l=130.00n ng=2 nrd=0 nrs=0 +MB_TWN<2> B_BLT<2> B_BLT_NMOS_DRIVE<2> VSS VSS sg13_lv_nmos m=1 ++ w=4.82u l=130.00n ng=2 nrd=0 nrs=0 +MB_TWN<1> B_BLT<1> B_BLT_NMOS_DRIVE<1> VSS VSS sg13_lv_nmos m=1 ++ w=4.82u l=130.00n ng=2 nrd=0 nrs=0 +MB_TWN<0> B_BLT<0> B_BLT_NMOS_DRIVE<0> VSS VSS sg13_lv_nmos m=1 ++ w=4.82u l=130.00n ng=2 nrd=0 nrs=0 +MB_CWN<3> B_BLC<3> B_BLC_NMOS_DRIVE<3> VSS VSS sg13_lv_nmos m=1 ++ w=4.82u l=130.00n ng=2 nrd=0 nrs=0 +MB_CWN<2> B_BLC<2> B_BLC_NMOS_DRIVE<2> VSS VSS sg13_lv_nmos m=1 ++ w=4.82u l=130.00n ng=2 nrd=0 nrs=0 +MB_CWN<1> B_BLC<1> B_BLC_NMOS_DRIVE<1> VSS VSS sg13_lv_nmos m=1 ++ w=4.82u l=130.00n ng=2 nrd=0 nrs=0 +MB_CWN<0> B_BLC<0> B_BLC_NMOS_DRIVE<0> VSS VSS sg13_lv_nmos m=1 ++ w=4.82u l=130.00n ng=2 nrd=0 nrs=0 +MA_CPR<3> A_BLC<3> A_PRE_N VDD VDD sg13_lv_pmos m=1 w=3.000u l=130.00n ++ ng=2 nrd=0 nrs=0 +MA_CPR<2> A_BLC<2> A_PRE_N VDD VDD sg13_lv_pmos m=1 w=3.000u l=130.00n ++ ng=2 nrd=0 nrs=0 +MA_CPR<1> A_BLC<1> A_PRE_N VDD VDD sg13_lv_pmos m=1 w=3.000u l=130.00n ++ ng=2 nrd=0 nrs=0 +MA_CPR<0> A_BLC<0> A_PRE_N VDD VDD sg13_lv_pmos m=1 w=3.000u l=130.00n ++ ng=2 nrd=0 nrs=0 +MA_TWP<3> A_BLT<3> A_BLT_PMOS_DRIVE<3> VDD VDD sg13_lv_pmos m=1 w=1.5u ++ l=130.00n ng=1 nrd=0 nrs=0 +MA_TWP<2> A_BLT<2> A_BLT_PMOS_DRIVE<2> VDD VDD sg13_lv_pmos m=1 w=1.5u ++ l=130.00n ng=1 nrd=0 nrs=0 +MA_TWP<1> A_BLT<1> A_BLT_PMOS_DRIVE<1> VDD VDD sg13_lv_pmos m=1 w=1.5u ++ l=130.00n ng=1 nrd=0 nrs=0 +MA_TWP<0> A_BLT<0> A_BLT_PMOS_DRIVE<0> VDD VDD sg13_lv_pmos m=1 w=1.5u ++ l=130.00n ng=1 nrd=0 nrs=0 +MA_CWP<3> A_BLC<3> A_BLC_PMOS_DRIVE<3> VDD VDD sg13_lv_pmos m=1 w=1.5u ++ l=130.00n ng=1 nrd=0 nrs=0 +MA_CWP<2> A_BLC<2> A_BLC_PMOS_DRIVE<2> VDD VDD sg13_lv_pmos m=1 w=1.5u ++ l=130.00n ng=1 nrd=0 nrs=0 +MA_CWP<1> A_BLC<1> A_BLC_PMOS_DRIVE<1> VDD VDD sg13_lv_pmos m=1 w=1.5u ++ l=130.00n ng=1 nrd=0 nrs=0 +MA_CWP<0> A_BLC<0> A_BLC_PMOS_DRIVE<0> VDD VDD sg13_lv_pmos m=1 w=1.5u ++ l=130.00n ng=1 nrd=0 nrs=0 +MA_TPR<3> A_BLT<3> A_PRE_N VDD VDD sg13_lv_pmos m=1 w=3.000u l=130.00n ++ ng=2 nrd=0 nrs=0 +MA_TPR<2> A_BLT<2> A_PRE_N VDD VDD sg13_lv_pmos m=1 w=3.000u l=130.00n ++ ng=2 nrd=0 nrs=0 +MA_TPR<1> A_BLT<1> A_PRE_N VDD VDD sg13_lv_pmos m=1 w=3.000u l=130.00n ++ ng=2 nrd=0 nrs=0 +MA_TPR<0> A_BLT<0> A_PRE_N VDD VDD sg13_lv_pmos m=1 w=3.000u l=130.00n ++ ng=2 nrd=0 nrs=0 +MA_TSP<3> A_BLT_SEL A_SEL_N<3> A_BLT<3> VDD sg13_lv_pmos m=1 w=1.5u ++ l=130.00n ng=1 nrd=0 nrs=0 +MA_TSP<2> A_BLT_SEL A_SEL_N<2> A_BLT<2> VDD sg13_lv_pmos m=1 w=1.5u ++ l=130.00n ng=1 nrd=0 nrs=0 +MA_TSP<1> A_BLT_SEL A_SEL_N<1> A_BLT<1> VDD sg13_lv_pmos m=1 w=1.5u ++ l=130.00n ng=1 nrd=0 nrs=0 +MA_TSP<0> A_BLT_SEL A_SEL_N<0> A_BLT<0> VDD sg13_lv_pmos m=1 w=1.5u ++ l=130.00n ng=1 nrd=0 nrs=0 +MA_CSP<3> A_BLC_SEL A_SEL_N<3> A_BLC<3> VDD sg13_lv_pmos m=1 w=1.5u ++ l=130.00n ng=1 nrd=0 nrs=0 +MA_CSP<2> A_BLC_SEL A_SEL_N<2> A_BLC<2> VDD sg13_lv_pmos m=1 w=1.5u ++ l=130.00n ng=1 nrd=0 nrs=0 +MA_CSP<1> A_BLC_SEL A_SEL_N<1> A_BLC<1> VDD sg13_lv_pmos m=1 w=1.5u ++ l=130.00n ng=1 nrd=0 nrs=0 +MA_CSP<0> A_BLC_SEL A_SEL_N<0> A_BLC<0> VDD sg13_lv_pmos m=1 w=1.5u ++ l=130.00n ng=1 nrd=0 nrs=0 +MB_CWP<3> B_BLC<3> B_BLC_PMOS_DRIVE<3> VDD VDD sg13_lv_pmos m=1 w=1.5u ++ l=130.00n ng=1 nrd=0 nrs=0 +MB_CWP<2> B_BLC<2> B_BLC_PMOS_DRIVE<2> VDD VDD sg13_lv_pmos m=1 w=1.5u ++ l=130.00n ng=1 nrd=0 nrs=0 +MB_CWP<1> B_BLC<1> B_BLC_PMOS_DRIVE<1> VDD VDD sg13_lv_pmos m=1 w=1.5u ++ l=130.00n ng=1 nrd=0 nrs=0 +MB_CWP<0> B_BLC<0> B_BLC_PMOS_DRIVE<0> VDD VDD sg13_lv_pmos m=1 w=1.5u ++ l=130.00n ng=1 nrd=0 nrs=0 +MB_TWP<3> B_BLT<3> B_BLT_PMOS_DRIVE<3> VDD VDD sg13_lv_pmos m=1 w=1.5u ++ l=130.00n ng=1 nrd=0 nrs=0 +MB_TWP<2> B_BLT<2> B_BLT_PMOS_DRIVE<2> VDD VDD sg13_lv_pmos m=1 w=1.5u ++ l=130.00n ng=1 nrd=0 nrs=0 +MB_TWP<1> B_BLT<1> B_BLT_PMOS_DRIVE<1> VDD VDD sg13_lv_pmos m=1 w=1.5u ++ l=130.00n ng=1 nrd=0 nrs=0 +MB_TWP<0> B_BLT<0> B_BLT_PMOS_DRIVE<0> VDD VDD sg13_lv_pmos m=1 w=1.5u ++ l=130.00n ng=1 nrd=0 nrs=0 +MB_TSP<3> B_BLT_SEL B_SEL_N<3> B_BLT<3> VDD sg13_lv_pmos m=1 w=1.5u ++ l=130.00n ng=1 nrd=0 nrs=0 +MB_TSP<2> B_BLT_SEL B_SEL_N<2> B_BLT<2> VDD sg13_lv_pmos m=1 w=1.5u ++ l=130.00n ng=1 nrd=0 nrs=0 +MB_TSP<1> B_BLT_SEL B_SEL_N<1> B_BLT<1> VDD sg13_lv_pmos m=1 w=1.5u ++ l=130.00n ng=1 nrd=0 nrs=0 +MB_TSP<0> B_BLT_SEL B_SEL_N<0> B_BLT<0> VDD sg13_lv_pmos m=1 w=1.5u ++ l=130.00n ng=1 nrd=0 nrs=0 +MB_TPR<3> B_BLT<3> B_PRE_N VDD VDD sg13_lv_pmos m=1 w=3.000u l=130.00n ++ ng=2 nrd=0 nrs=0 +MB_TPR<2> B_BLT<2> B_PRE_N VDD VDD sg13_lv_pmos m=1 w=3.000u l=130.00n ++ ng=2 nrd=0 nrs=0 +MB_TPR<1> B_BLT<1> B_PRE_N VDD VDD sg13_lv_pmos m=1 w=3.000u l=130.00n ++ ng=2 nrd=0 nrs=0 +MB_TPR<0> B_BLT<0> B_PRE_N VDD VDD sg13_lv_pmos m=1 w=3.000u l=130.00n ++ ng=2 nrd=0 nrs=0 +MB_CSP<3> B_BLC_SEL B_SEL_N<3> B_BLC<3> VDD sg13_lv_pmos m=1 w=1.5u ++ l=130.00n ng=1 nrd=0 nrs=0 +MB_CSP<2> B_BLC_SEL B_SEL_N<2> B_BLC<2> VDD sg13_lv_pmos m=1 w=1.5u ++ l=130.00n ng=1 nrd=0 nrs=0 +MB_CSP<1> B_BLC_SEL B_SEL_N<1> B_BLC<1> VDD sg13_lv_pmos m=1 w=1.5u ++ l=130.00n ng=1 nrd=0 nrs=0 +MB_CSP<0> B_BLC_SEL B_SEL_N<0> B_BLC<0> VDD sg13_lv_pmos m=1 w=1.5u ++ l=130.00n ng=1 nrd=0 nrs=0 +MB_CPR<3> B_BLC<3> B_PRE_N VDD VDD sg13_lv_pmos m=1 w=3.000u l=130.00n ++ ng=2 nrd=0 nrs=0 +MB_CPR<2> B_BLC<2> B_PRE_N VDD VDD sg13_lv_pmos m=1 w=3.000u l=130.00n ++ ng=2 nrd=0 nrs=0 +MB_CPR<1> B_BLC<1> B_PRE_N VDD VDD sg13_lv_pmos m=1 w=3.000u l=130.00n ++ ng=2 nrd=0 nrs=0 +MB_CPR<0> B_BLC<0> B_PRE_N VDD VDD sg13_lv_pmos m=1 w=3.000u l=130.00n ++ ng=2 nrd=0 nrs=0 +XA_SEL<3> A_SEL_P<3> A_SEL_N<3> VDD VSS / RSC_IHPSG13_INVX2 +XA_SEL<2> A_SEL_P<2> A_SEL_N<2> VDD VSS / RSC_IHPSG13_INVX2 +XA_SEL<1> A_SEL_P<1> A_SEL_N<1> VDD VSS / RSC_IHPSG13_INVX2 +XA_SEL<0> A_SEL_P<0> A_SEL_N<0> VDD VSS / RSC_IHPSG13_INVX2 +XA_CINV<3> A_BLT_PMOS_DRIVE<3> A_BLC_NMOS_DRIVE<3> VDD VSS / ++ RSC_IHPSG13_INVX2 +XA_CINV<2> A_BLT_PMOS_DRIVE<2> A_BLC_NMOS_DRIVE<2> VDD VSS / ++ RSC_IHPSG13_INVX2 +XA_CINV<1> A_BLT_PMOS_DRIVE<1> A_BLC_NMOS_DRIVE<1> VDD VSS / ++ RSC_IHPSG13_INVX2 +XA_CINV<0> A_BLT_PMOS_DRIVE<0> A_BLC_NMOS_DRIVE<0> VDD VSS / ++ RSC_IHPSG13_INVX2 +XA_TINV<3> A_BLC_PMOS_DRIVE<3> A_BLT_NMOS_DRIVE<3> VDD VSS / ++ RSC_IHPSG13_INVX2 +XA_TINV<2> A_BLC_PMOS_DRIVE<2> A_BLT_NMOS_DRIVE<2> VDD VSS / ++ RSC_IHPSG13_INVX2 +XA_TINV<1> A_BLC_PMOS_DRIVE<1> A_BLT_NMOS_DRIVE<1> VDD VSS / ++ RSC_IHPSG13_INVX2 +XA_TINV<0> A_BLC_PMOS_DRIVE<0> A_BLT_NMOS_DRIVE<0> VDD VSS / ++ RSC_IHPSG13_INVX2 +XB_SEL<3> B_SEL_P<3> B_SEL_N<3> VDD VSS / RSC_IHPSG13_INVX2 +XB_SEL<2> B_SEL_P<2> B_SEL_N<2> VDD VSS / RSC_IHPSG13_INVX2 +XB_SEL<1> B_SEL_P<1> B_SEL_N<1> VDD VSS / RSC_IHPSG13_INVX2 +XB_SEL<0> B_SEL_P<0> B_SEL_N<0> VDD VSS / RSC_IHPSG13_INVX2 +XB_TINV<3> B_BLC_PMOS_DRIVE<3> B_BLT_NMOS_DRIVE<3> VDD VSS / ++ RSC_IHPSG13_INVX2 +XB_TINV<2> B_BLC_PMOS_DRIVE<2> B_BLT_NMOS_DRIVE<2> VDD VSS / ++ RSC_IHPSG13_INVX2 +XB_TINV<1> B_BLC_PMOS_DRIVE<1> B_BLT_NMOS_DRIVE<1> VDD VSS / ++ RSC_IHPSG13_INVX2 +XB_TINV<0> B_BLC_PMOS_DRIVE<0> B_BLT_NMOS_DRIVE<0> VDD VSS / ++ RSC_IHPSG13_INVX2 +XB_CINV<3> B_BLT_PMOS_DRIVE<3> B_BLC_NMOS_DRIVE<3> VDD VSS / ++ RSC_IHPSG13_INVX2 +XB_CINV<2> B_BLT_PMOS_DRIVE<2> B_BLC_NMOS_DRIVE<2> VDD VSS / ++ RSC_IHPSG13_INVX2 +XB_CINV<1> B_BLT_PMOS_DRIVE<1> B_BLC_NMOS_DRIVE<1> VDD VSS / ++ RSC_IHPSG13_INVX2 +XB_CINV<0> B_BLT_PMOS_DRIVE<0> B_BLC_NMOS_DRIVE<0> VDD VSS / ++ RSC_IHPSG13_INVX2 +XA_TDEC<3> A_SEL_P<3> A_WR_ONE A_BLT_PMOS_DRIVE<3> VDD VSS / ++ RSC_IHPSG13_NAND2X2 +XA_TDEC<2> A_SEL_P<2> A_WR_ONE A_BLT_PMOS_DRIVE<2> VDD VSS / ++ RSC_IHPSG13_NAND2X2 +XA_TDEC<1> A_SEL_P<1> A_WR_ONE A_BLT_PMOS_DRIVE<1> VDD VSS / ++ RSC_IHPSG13_NAND2X2 +XA_TDEC<0> A_SEL_P<0> A_WR_ONE A_BLT_PMOS_DRIVE<0> VDD VSS / ++ RSC_IHPSG13_NAND2X2 +XA_CDEC<3> A_SEL_P<3> A_WR_ZERO A_BLC_PMOS_DRIVE<3> VDD VSS / ++ RSC_IHPSG13_NAND2X2 +XA_CDEC<2> A_SEL_P<2> A_WR_ZERO A_BLC_PMOS_DRIVE<2> VDD VSS / ++ RSC_IHPSG13_NAND2X2 +XA_CDEC<1> A_SEL_P<1> A_WR_ZERO A_BLC_PMOS_DRIVE<1> VDD VSS / ++ RSC_IHPSG13_NAND2X2 +XA_CDEC<0> A_SEL_P<0> A_WR_ZERO A_BLC_PMOS_DRIVE<0> VDD VSS / ++ RSC_IHPSG13_NAND2X2 +XB_CDEC<3> B_SEL_P<3> B_WR_ZERO B_BLC_PMOS_DRIVE<3> VDD VSS / ++ RSC_IHPSG13_NAND2X2 +XB_CDEC<2> B_SEL_P<2> B_WR_ZERO B_BLC_PMOS_DRIVE<2> VDD VSS / ++ RSC_IHPSG13_NAND2X2 +XB_CDEC<1> B_SEL_P<1> B_WR_ZERO B_BLC_PMOS_DRIVE<1> VDD VSS / ++ RSC_IHPSG13_NAND2X2 +XB_CDEC<0> B_SEL_P<0> B_WR_ZERO B_BLC_PMOS_DRIVE<0> VDD VSS / ++ RSC_IHPSG13_NAND2X2 +XB_TDEC<3> B_SEL_P<3> B_WR_ONE B_BLT_PMOS_DRIVE<3> VDD VSS / ++ RSC_IHPSG13_NAND2X2 +XB_TDEC<2> B_SEL_P<2> B_WR_ONE B_BLT_PMOS_DRIVE<2> VDD VSS / ++ RSC_IHPSG13_NAND2X2 +XB_TDEC<1> B_SEL_P<1> B_WR_ONE B_BLT_PMOS_DRIVE<1> VDD VSS / ++ RSC_IHPSG13_NAND2X2 +XB_TDEC<0> B_SEL_P<0> B_WR_ONE B_BLT_PMOS_DRIVE<0> VDD VSS / ++ RSC_IHPSG13_NAND2X2 +.ENDS +.SUBCKT RSC_IHPSG13_AND2X6 A B Z VDD VSS +MN3 Z net6 VSS VSS sg13_lv_nmos m=1 w=2.94u l=130.00n ng=3 nrd=0 nrs=0 +MN4 net9 B VSS VSS sg13_lv_nmos m=1 w=500.0n l=130.00n ng=1 nrd=0 nrs=0 +MN6 net6 A net9 VSS sg13_lv_nmos m=1 w=500.0n l=130.00n ng=1 nrd=0 nrs=0 +MP2 Z net6 VDD VDD sg13_lv_pmos m=1 w=4.86u l=130.00n ng=3 nrd=0 nrs=0 +MP0 net6 B VDD VDD sg13_lv_pmos m=1 w=860.00n l=130.00n ng=1 nrd=0 ++ nrs=0 +MP1 net6 A VDD VDD sg13_lv_pmos m=1 w=860.00n l=130.00n ng=1 nrd=0 ++ nrs=0 +.ENDS +.SUBCKT RM_IHPSG13_512x32_c2_2P_COLCTRL5 A_ADDR_COL<1> A_ADDR_COL<0> A_ADDR_DEC<7> ++ A_ADDR_DEC<6> A_ADDR_DEC<5> A_ADDR_DEC<4> A_ADDR_DEC<3> A_ADDR_DEC<2> ++ A_ADDR_DEC<1> A_ADDR_DEC<0> A_BIST_BM_I A_BIST_DW_I A_BIST_EN_I A_BLC<31> ++ A_BLC<30> A_BLC<29> A_BLC<28> A_BLC<27> A_BLC<26> A_BLC<25> A_BLC<24> ++ A_BLC<23> A_BLC<22> A_BLC<21> A_BLC<20> A_BLC<19> A_BLC<18> A_BLC<17> ++ A_BLC<16> A_BLC<15> A_BLC<14> A_BLC<13> A_BLC<12> A_BLC<11> A_BLC<10> ++ A_BLC<9> A_BLC<8> A_BLC<7> A_BLC<6> A_BLC<5> A_BLC<4> A_BLC<3> A_BLC<2> ++ A_BLC<1> A_BLC<0> A_BLT<31> A_BLT<30> A_BLT<29> A_BLT<28> A_BLT<27> ++ A_BLT<26> A_BLT<25> A_BLT<24> A_BLT<23> A_BLT<22> A_BLT<21> A_BLT<20> ++ A_BLT<19> A_BLT<18> A_BLT<17> A_BLT<16> A_BLT<15> A_BLT<14> A_BLT<13> ++ A_BLT<12> A_BLT<11> A_BLT<10> A_BLT<9> A_BLT<8> A_BLT<7> A_BLT<6> A_BLT<5> ++ A_BLT<4> A_BLT<3> A_BLT<2> A_BLT<1> A_BLT<0> A_BM_I A_DCLK_B_L A_DCLK_B_R ++ A_DCLK_L A_DCLK_R A_DR_O A_DW_I A_RCLK_B_L A_RCLK_B_R A_RCLK_L A_RCLK_R ++ A_TIEH_O A_WCLK_B_L A_WCLK_B_R A_WCLK_L A_WCLK_R B_ADDR_COL<1> B_ADDR_COL<0> ++ B_ADDR_DEC<7> B_ADDR_DEC<6> B_ADDR_DEC<5> B_ADDR_DEC<4> B_ADDR_DEC<3> ++ B_ADDR_DEC<2> B_ADDR_DEC<1> B_ADDR_DEC<0> B_BIST_BM_I B_BIST_DW_I ++ B_BIST_EN_I B_BLC<31> B_BLC<30> B_BLC<29> B_BLC<28> B_BLC<27> B_BLC<26> ++ B_BLC<25> B_BLC<24> B_BLC<23> B_BLC<22> B_BLC<21> B_BLC<20> B_BLC<19> ++ B_BLC<18> B_BLC<17> B_BLC<16> B_BLC<15> B_BLC<14> B_BLC<13> B_BLC<12> ++ B_BLC<11> B_BLC<10> B_BLC<9> B_BLC<8> B_BLC<7> B_BLC<6> B_BLC<5> B_BLC<4> ++ B_BLC<3> B_BLC<2> B_BLC<1> B_BLC<0> B_BLT<31> B_BLT<30> B_BLT<29> B_BLT<28> ++ B_BLT<27> B_BLT<26> B_BLT<25> B_BLT<24> B_BLT<23> B_BLT<22> B_BLT<21> ++ B_BLT<20> B_BLT<19> B_BLT<18> B_BLT<17> B_BLT<16> B_BLT<15> B_BLT<14> ++ B_BLT<13> B_BLT<12> B_BLT<11> B_BLT<10> B_BLT<9> B_BLT<8> B_BLT<7> B_BLT<6> ++ B_BLT<5> B_BLT<4> B_BLT<3> B_BLT<2> B_BLT<1> B_BLT<0> B_BM_I B_DCLK_B_L ++ B_DCLK_B_R B_DCLK_L B_DCLK_R B_DR_O B_DW_I B_RCLK_B_L B_RCLK_B_R B_RCLK_L ++ B_RCLK_R B_TIEH_O B_WCLK_B_L B_WCLK_B_R B_WCLK_L B_WCLK_R VDD VSS +XB_I80<1> B_WCLK_B_L B_RCLK_B_L B_W_nor_R<1> VDD VSS / ++ RSC_IHPSG13_AND2X2 +XB_I80<0> B_WCLK_B_L B_RCLK_B_L B_W_nor_R<0> VDD VSS / ++ RSC_IHPSG13_AND2X2 +XA_I80<1> A_WCLK_B_L A_RCLK_B_L A_W_nor_R<1> VDD VSS / ++ RSC_IHPSG13_AND2X2 +XA_I80<0> A_WCLK_B_L A_RCLK_B_L A_W_nor_R<0> VDD VSS / ++ RSC_IHPSG13_AND2X2 +XB_I44 B_BM_N B_WCLK_B_L B_DO_WRITE_P VDD VSS / RSC_IHPSG13_NOR2X2 +XA_I44 A_BM_N A_WCLK_B_L A_DO_WRITE_P VDD VSS / RSC_IHPSG13_NOR2X2 +XI_FILL4<16> VDD VSS / RSC_IHPSG13_FILLCAP4 +XI_FILL4<15> VDD VSS / RSC_IHPSG13_FILLCAP4 +XI_FILL4<14> VDD VSS / RSC_IHPSG13_FILLCAP4 +XI_FILL4<13> VDD VSS / RSC_IHPSG13_FILLCAP4 +XI_FILL4<12> VDD VSS / RSC_IHPSG13_FILLCAP4 +XI_FILL4<11> VDD VSS / RSC_IHPSG13_FILLCAP4 +XI_FILL4<10> VDD VSS / RSC_IHPSG13_FILLCAP4 +XI_FILL4<9> VDD VSS / RSC_IHPSG13_FILLCAP4 +XI_FILL4<8> VDD VSS / RSC_IHPSG13_FILLCAP4 +XI_FILL4<7> VDD VSS / RSC_IHPSG13_FILLCAP4 +XI_FILL4<6> VDD VSS / RSC_IHPSG13_FILLCAP4 +XI_FILL4<5> VDD VSS / RSC_IHPSG13_FILLCAP4 +XI_FILL4<4> VDD VSS / RSC_IHPSG13_FILLCAP4 +XI_FILL4<3> VDD VSS / RSC_IHPSG13_FILLCAP4 +XI_FILL4<2> VDD VSS / RSC_IHPSG13_FILLCAP4 +XI_FILL4<1> VDD VSS / RSC_IHPSG13_FILLCAP4 +XB_INV<6> B_N1<1> B_P1<1> VDD VSS / RSC_IHPSG13_CINVX4 +XB_INV<5> B_N0<1> B_P0<1> VDD VSS / RSC_IHPSG13_CINVX4 +XB_INV<4> B_N0<0> B_P0<0> VDD VSS / RSC_IHPSG13_CINVX4 +XB_INV<3> B_ADDR_COL<1> B_N1<1> VDD VSS / RSC_IHPSG13_CINVX4 +XB_INV<2> B_ADDR_COL<1> B_N1<0> VDD VSS / RSC_IHPSG13_CINVX4 +XB_INV<1> B_ADDR_COL<0> B_N0<1> VDD VSS / RSC_IHPSG13_CINVX4 +XB_INV<0> B_ADDR_COL<0> B_N0<0> VDD VSS / RSC_IHPSG13_CINVX4 +XA_INV<6> A_N1<1> A_P1<1> VDD VSS / RSC_IHPSG13_CINVX4 +XA_INV<5> A_N0<1> A_P0<1> VDD VSS / RSC_IHPSG13_CINVX4 +XA_INV<4> A_N0<0> A_P0<0> VDD VSS / RSC_IHPSG13_CINVX4 +XA_INV<3> A_ADDR_COL<1> A_N1<1> VDD VSS / RSC_IHPSG13_CINVX4 +XA_INV<2> A_ADDR_COL<1> A_N1<0> VDD VSS / RSC_IHPSG13_CINVX4 +XA_INV<1> A_ADDR_COL<0> A_N0<1> VDD VSS / RSC_IHPSG13_CINVX4 +XA_INV<0> A_ADDR_COL<0> A_N0<0> VDD VSS / RSC_IHPSG13_CINVX4 +XB_I81<3> B_W_nor_R<1> B_PRE_N VDD VSS / RSC_IHPSG13_CINVX4_WN +XB_I81<2> B_W_nor_R<1> B_PRE_N VDD VSS / RSC_IHPSG13_CINVX4_WN +XB_I81<1> B_W_nor_R<0> B_PRE_N VDD VSS / RSC_IHPSG13_CINVX4_WN +XB_I81<0> B_W_nor_R<0> B_PRE_N VDD VSS / RSC_IHPSG13_CINVX4_WN +XA_I81<3> A_W_nor_R<1> A_PRE_N VDD VSS / RSC_IHPSG13_CINVX4_WN +XA_I81<2> A_W_nor_R<1> A_PRE_N VDD VSS / RSC_IHPSG13_CINVX4_WN +XA_I81<1> A_W_nor_R<0> A_PRE_N VDD VSS / RSC_IHPSG13_CINVX4_WN +XA_I81<0> A_W_nor_R<0> A_PRE_N VDD VSS / RSC_IHPSG13_CINVX4_WN +XI_FILL8<78> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI_FILL8<77> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI_FILL8<76> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI_FILL8<75> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI_FILL8<74> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI_FILL8<73> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI_FILL8<72> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI_FILL8<71> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI_FILL8<70> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI_FILL8<69> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI_FILL8<68> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI_FILL8<67> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI_FILL8<66> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI_FILL8<65> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI_FILL8<64> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI_FILL8<63> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI_FILL8<62> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI_FILL8<61> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI_FILL8<60> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI_FILL8<59> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI_FILL8<58> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI_FILL8<57> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI_FILL8<56> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI_FILL8<55> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI_FILL8<54> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI_FILL8<53> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI_FILL8<52> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI_FILL8<51> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI_FILL8<50> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI_FILL8<49> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI_FILL8<48> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI_FILL8<47> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI_FILL8<46> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI_FILL8<45> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI_FILL8<44> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI_FILL8<43> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI_FILL8<42> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI_FILL8<41> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI_FILL8<40> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI_FILL8<39> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI_FILL8<38> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI_FILL8<37> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI_FILL8<36> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI_FILL8<35> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI_FILL8<34> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI_FILL8<33> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI_FILL8<32> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI_FILL8<31> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI_FILL8<30> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI_FILL8<29> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI_FILL8<28> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI_FILL8<27> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI_FILL8<26> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI_FILL8<25> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI_FILL8<24> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI_FILL8<23> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI_FILL8<22> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI_FILL8<21> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI_FILL8<20> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI_FILL8<19> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI_FILL8<18> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI_FILL8<17> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI_FILL8<16> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI_FILL8<15> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI_FILL8<14> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI_FILL8<13> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI_FILL8<12> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI_FILL8<11> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI_FILL8<10> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI_FILL8<9> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI_FILL8<8> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI_FILL8<7> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI_FILL8<6> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI_FILL8<5> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI_FILL8<4> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI_FILL8<3> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI_FILL8<2> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI_FILL8<1> VDD VSS / RSC_IHPSG13_FILLCAP8 +XAB_BLMUX<7> A_BLC<31> A_BLC<30> A_BLC<29> A_BLC<28> A_BLC_SEL A_BLT<31> ++ A_BLT<30> A_BLT<29> A_BLT<28> A_BLT_SEL A_PRE_N A_SEL_P<31> A_SEL_P<30> ++ A_SEL_P<29> A_SEL_P<28> A_WR_ONE A_WR_ZERO B_BLC<31> B_BLC<30> B_BLC<29> ++ B_BLC<28> B_BLC_SEL B_BLT<31> B_BLT<30> B_BLT<29> B_BLT<28> B_BLT_SEL ++ B_PRE_N B_SEL_P<31> B_SEL_P<30> B_SEL_P<29> B_SEL_P<28> B_WR_ONE B_WR_ZERO ++ VDD VSS / RM_IHPSG13_512x32_c2_2P_BLDRV +XAB_BLMUX<6> A_BLC<27> A_BLC<26> A_BLC<25> A_BLC<24> A_BLC_SEL A_BLT<27> ++ A_BLT<26> A_BLT<25> A_BLT<24> A_BLT_SEL A_PRE_N A_SEL_P<27> A_SEL_P<26> ++ A_SEL_P<25> A_SEL_P<24> A_WR_ONE A_WR_ZERO B_BLC<27> B_BLC<26> B_BLC<25> ++ B_BLC<24> B_BLC_SEL B_BLT<27> B_BLT<26> B_BLT<25> B_BLT<24> B_BLT_SEL ++ B_PRE_N B_SEL_P<27> B_SEL_P<26> B_SEL_P<25> B_SEL_P<24> B_WR_ONE B_WR_ZERO ++ VDD VSS / RM_IHPSG13_512x32_c2_2P_BLDRV +XAB_BLMUX<5> A_BLC<23> A_BLC<22> A_BLC<21> A_BLC<20> A_BLC_SEL A_BLT<23> ++ A_BLT<22> A_BLT<21> A_BLT<20> A_BLT_SEL A_PRE_N A_SEL_P<23> A_SEL_P<22> ++ A_SEL_P<21> A_SEL_P<20> A_WR_ONE A_WR_ZERO B_BLC<23> B_BLC<22> B_BLC<21> ++ B_BLC<20> B_BLC_SEL B_BLT<23> B_BLT<22> B_BLT<21> B_BLT<20> B_BLT_SEL ++ B_PRE_N B_SEL_P<23> B_SEL_P<22> B_SEL_P<21> B_SEL_P<20> B_WR_ONE B_WR_ZERO ++ VDD VSS / RM_IHPSG13_512x32_c2_2P_BLDRV +XAB_BLMUX<4> A_BLC<19> A_BLC<18> A_BLC<17> A_BLC<16> A_BLC_SEL A_BLT<19> ++ A_BLT<18> A_BLT<17> A_BLT<16> A_BLT_SEL A_PRE_N A_SEL_P<19> A_SEL_P<18> ++ A_SEL_P<17> A_SEL_P<16> A_WR_ONE A_WR_ZERO B_BLC<19> B_BLC<18> B_BLC<17> ++ B_BLC<16> B_BLC_SEL B_BLT<19> B_BLT<18> B_BLT<17> B_BLT<16> B_BLT_SEL ++ B_PRE_N B_SEL_P<19> B_SEL_P<18> B_SEL_P<17> B_SEL_P<16> B_WR_ONE B_WR_ZERO ++ VDD VSS / RM_IHPSG13_512x32_c2_2P_BLDRV +XAB_BLMUX<3> A_BLC<15> A_BLC<14> A_BLC<13> A_BLC<12> A_BLC_SEL A_BLT<15> ++ A_BLT<14> A_BLT<13> A_BLT<12> A_BLT_SEL A_PRE_N A_SEL_P<15> A_SEL_P<14> ++ A_SEL_P<13> A_SEL_P<12> A_WR_ONE A_WR_ZERO B_BLC<15> B_BLC<14> B_BLC<13> ++ B_BLC<12> B_BLC_SEL B_BLT<15> B_BLT<14> B_BLT<13> B_BLT<12> B_BLT_SEL ++ B_PRE_N B_SEL_P<15> B_SEL_P<14> B_SEL_P<13> B_SEL_P<12> B_WR_ONE B_WR_ZERO ++ VDD VSS / RM_IHPSG13_512x32_c2_2P_BLDRV +XAB_BLMUX<2> A_BLC<11> A_BLC<10> A_BLC<9> A_BLC<8> A_BLC_SEL A_BLT<11> ++ A_BLT<10> A_BLT<9> A_BLT<8> A_BLT_SEL A_PRE_N A_SEL_P<11> A_SEL_P<10> ++ A_SEL_P<9> A_SEL_P<8> A_WR_ONE A_WR_ZERO B_BLC<11> B_BLC<10> B_BLC<9> ++ B_BLC<8> B_BLC_SEL B_BLT<11> B_BLT<10> B_BLT<9> B_BLT<8> B_BLT_SEL B_PRE_N ++ B_SEL_P<11> B_SEL_P<10> B_SEL_P<9> B_SEL_P<8> B_WR_ONE B_WR_ZERO VDD ++ VSS / RM_IHPSG13_512x32_c2_2P_BLDRV +XAB_BLMUX<1> A_BLC<7> A_BLC<6> A_BLC<5> A_BLC<4> A_BLC_SEL A_BLT<7> A_BLT<6> ++ A_BLT<5> A_BLT<4> A_BLT_SEL A_PRE_N A_SEL_P<7> A_SEL_P<6> A_SEL_P<5> ++ A_SEL_P<4> A_WR_ONE A_WR_ZERO B_BLC<7> B_BLC<6> B_BLC<5> B_BLC<4> B_BLC_SEL ++ B_BLT<7> B_BLT<6> B_BLT<5> B_BLT<4> B_BLT_SEL B_PRE_N B_SEL_P<7> B_SEL_P<6> ++ B_SEL_P<5> B_SEL_P<4> B_WR_ONE B_WR_ZERO VDD VSS / ++ RM_IHPSG13_512x32_c2_2P_BLDRV +XAB_BLMUX<0> A_BLC<3> A_BLC<2> A_BLC<1> A_BLC<0> A_BLC_SEL A_BLT<3> A_BLT<2> ++ A_BLT<1> A_BLT<0> A_BLT_SEL A_PRE_N A_SEL_P<3> A_SEL_P<2> A_SEL_P<1> ++ A_SEL_P<0> A_WR_ONE A_WR_ZERO B_BLC<3> B_BLC<2> B_BLC<1> B_BLC<0> B_BLC_SEL ++ B_BLT<3> B_BLT<2> B_BLT<1> B_BLT<0> B_BLT_SEL B_PRE_N B_SEL_P<3> B_SEL_P<2> ++ B_SEL_P<1> B_SEL_P<0> B_WR_ONE B_WR_ZERO VDD VSS / ++ RM_IHPSG13_512x32_c2_2P_BLDRV +XB_I51 net037 B_DR_O VDD VSS / RSC_IHPSG13_INVX4 +XA_I51 net19 A_DR_O VDD VSS / RSC_IHPSG13_INVX4 +XB_I78 B_RCLK_B_L B_SAE VDD VSS / RSC_IHPSG13_CBUFX2 +XA_I78 A_RCLK_B_L A_SAE VDD VSS / RSC_IHPSG13_CBUFX2 +XB_I69 B_DCLK_L B_DCLK_B_L VDD VSS / RSC_IHPSG13_CINVX8 +XB_I50 B_WCLK_L B_WCLK_B_L VDD VSS / RSC_IHPSG13_CINVX8 +XB_EBUF B_RCLK_L B_RCLK_B_L VDD VSS / RSC_IHPSG13_CINVX8 +XA_I69 A_DCLK_L A_DCLK_B_L VDD VSS / RSC_IHPSG13_CINVX8 +XA_I50 A_WCLK_L A_WCLK_B_L VDD VSS / RSC_IHPSG13_CINVX8 +XA_EBUF A_RCLK_L A_RCLK_B_L VDD VSS / RSC_IHPSG13_CINVX8 +XB_I76 B_DI_N B_DO_WRITE_P B_WR_ZERO VDD VSS / RSC_IHPSG13_AND2X6 +XB_I75 B_DI_R B_DO_WRITE_P B_WR_ONE VDD VSS / RSC_IHPSG13_AND2X6 +XA_I76 A_DI_N A_DO_WRITE_P A_WR_ZERO VDD VSS / RSC_IHPSG13_AND2X6 +XA_I75 A_DI_R A_DO_WRITE_P A_WR_ONE VDD VSS / RSC_IHPSG13_AND2X6 +XB_I83 B_BM_R B_BM_N VDD VSS / RSC_IHPSG13_INVX2 +XB_DEC3INV<31> net041<0> B_SEL_P<31> VDD VSS / RSC_IHPSG13_INVX2 +XB_DEC3INV<30> net041<1> B_SEL_P<30> VDD VSS / RSC_IHPSG13_INVX2 +XB_DEC3INV<29> net041<2> B_SEL_P<29> VDD VSS / RSC_IHPSG13_INVX2 +XB_DEC3INV<28> net041<3> B_SEL_P<28> VDD VSS / RSC_IHPSG13_INVX2 +XB_DEC3INV<27> net041<4> B_SEL_P<27> VDD VSS / RSC_IHPSG13_INVX2 +XB_DEC3INV<26> net041<5> B_SEL_P<26> VDD VSS / RSC_IHPSG13_INVX2 +XB_DEC3INV<25> net041<6> B_SEL_P<25> VDD VSS / RSC_IHPSG13_INVX2 +XB_DEC3INV<24> net041<7> B_SEL_P<24> VDD VSS / RSC_IHPSG13_INVX2 +XB_DEC3INV<23> net041<8> B_SEL_P<23> VDD VSS / RSC_IHPSG13_INVX2 +XB_DEC3INV<22> net041<9> B_SEL_P<22> VDD VSS / RSC_IHPSG13_INVX2 +XB_DEC3INV<21> net041<10> B_SEL_P<21> VDD VSS / RSC_IHPSG13_INVX2 +XB_DEC3INV<20> net041<11> B_SEL_P<20> VDD VSS / RSC_IHPSG13_INVX2 +XB_DEC3INV<19> net041<12> B_SEL_P<19> VDD VSS / RSC_IHPSG13_INVX2 +XB_DEC3INV<18> net041<13> B_SEL_P<18> VDD VSS / RSC_IHPSG13_INVX2 +XB_DEC3INV<17> net041<14> B_SEL_P<17> VDD VSS / RSC_IHPSG13_INVX2 +XB_DEC3INV<16> net041<15> B_SEL_P<16> VDD VSS / RSC_IHPSG13_INVX2 +XB_DEC3INV<15> net041<16> B_SEL_P<15> VDD VSS / RSC_IHPSG13_INVX2 +XB_DEC3INV<14> net041<17> B_SEL_P<14> VDD VSS / RSC_IHPSG13_INVX2 +XB_DEC3INV<13> net041<18> B_SEL_P<13> VDD VSS / RSC_IHPSG13_INVX2 +XB_DEC3INV<12> net041<19> B_SEL_P<12> VDD VSS / RSC_IHPSG13_INVX2 +XB_DEC3INV<11> net041<20> B_SEL_P<11> VDD VSS / RSC_IHPSG13_INVX2 +XB_DEC3INV<10> net041<21> B_SEL_P<10> VDD VSS / RSC_IHPSG13_INVX2 +XB_DEC3INV<9> net041<22> B_SEL_P<9> VDD VSS / RSC_IHPSG13_INVX2 +XB_DEC3INV<8> net041<23> B_SEL_P<8> VDD VSS / RSC_IHPSG13_INVX2 +XB_DEC3INV<7> net041<24> B_SEL_P<7> VDD VSS / RSC_IHPSG13_INVX2 +XB_DEC3INV<6> net041<25> B_SEL_P<6> VDD VSS / RSC_IHPSG13_INVX2 +XB_DEC3INV<5> net041<26> B_SEL_P<5> VDD VSS / RSC_IHPSG13_INVX2 +XB_DEC3INV<4> net041<27> B_SEL_P<4> VDD VSS / RSC_IHPSG13_INVX2 +XB_DEC3INV<3> net041<28> B_SEL_P<3> VDD VSS / RSC_IHPSG13_INVX2 +XB_DEC3INV<2> net041<29> B_SEL_P<2> VDD VSS / RSC_IHPSG13_INVX2 +XB_DEC3INV<1> net041<30> B_SEL_P<1> VDD VSS / RSC_IHPSG13_INVX2 +XB_DEC3INV<0> net041<31> B_SEL_P<0> VDD VSS / RSC_IHPSG13_INVX2 +XB_I49 B_DI_R B_DI_N VDD VSS / RSC_IHPSG13_INVX2 +XA_I83 A_BM_R A_BM_N VDD VSS / RSC_IHPSG13_INVX2 +XA_DEC3INV<31> net23<0> A_SEL_P<31> VDD VSS / RSC_IHPSG13_INVX2 +XA_DEC3INV<30> net23<1> A_SEL_P<30> VDD VSS / RSC_IHPSG13_INVX2 +XA_DEC3INV<29> net23<2> A_SEL_P<29> VDD VSS / RSC_IHPSG13_INVX2 +XA_DEC3INV<28> net23<3> A_SEL_P<28> VDD VSS / RSC_IHPSG13_INVX2 +XA_DEC3INV<27> net23<4> A_SEL_P<27> VDD VSS / RSC_IHPSG13_INVX2 +XA_DEC3INV<26> net23<5> A_SEL_P<26> VDD VSS / RSC_IHPSG13_INVX2 +XA_DEC3INV<25> net23<6> A_SEL_P<25> VDD VSS / RSC_IHPSG13_INVX2 +XA_DEC3INV<24> net23<7> A_SEL_P<24> VDD VSS / RSC_IHPSG13_INVX2 +XA_DEC3INV<23> net23<8> A_SEL_P<23> VDD VSS / RSC_IHPSG13_INVX2 +XA_DEC3INV<22> net23<9> A_SEL_P<22> VDD VSS / RSC_IHPSG13_INVX2 +XA_DEC3INV<21> net23<10> A_SEL_P<21> VDD VSS / RSC_IHPSG13_INVX2 +XA_DEC3INV<20> net23<11> A_SEL_P<20> VDD VSS / RSC_IHPSG13_INVX2 +XA_DEC3INV<19> net23<12> A_SEL_P<19> VDD VSS / RSC_IHPSG13_INVX2 +XA_DEC3INV<18> net23<13> A_SEL_P<18> VDD VSS / RSC_IHPSG13_INVX2 +XA_DEC3INV<17> net23<14> A_SEL_P<17> VDD VSS / RSC_IHPSG13_INVX2 +XA_DEC3INV<16> net23<15> A_SEL_P<16> VDD VSS / RSC_IHPSG13_INVX2 +XA_DEC3INV<15> net23<16> A_SEL_P<15> VDD VSS / RSC_IHPSG13_INVX2 +XA_DEC3INV<14> net23<17> A_SEL_P<14> VDD VSS / RSC_IHPSG13_INVX2 +XA_DEC3INV<13> net23<18> A_SEL_P<13> VDD VSS / RSC_IHPSG13_INVX2 +XA_DEC3INV<12> net23<19> A_SEL_P<12> VDD VSS / RSC_IHPSG13_INVX2 +XA_DEC3INV<11> net23<20> A_SEL_P<11> VDD VSS / RSC_IHPSG13_INVX2 +XA_DEC3INV<10> net23<21> A_SEL_P<10> VDD VSS / RSC_IHPSG13_INVX2 +XA_DEC3INV<9> net23<22> A_SEL_P<9> VDD VSS / RSC_IHPSG13_INVX2 +XA_DEC3INV<8> net23<23> A_SEL_P<8> VDD VSS / RSC_IHPSG13_INVX2 +XA_DEC3INV<7> net23<24> A_SEL_P<7> VDD VSS / RSC_IHPSG13_INVX2 +XA_DEC3INV<6> net23<25> A_SEL_P<6> VDD VSS / RSC_IHPSG13_INVX2 +XA_DEC3INV<5> net23<26> A_SEL_P<5> VDD VSS / RSC_IHPSG13_INVX2 +XA_DEC3INV<4> net23<27> A_SEL_P<4> VDD VSS / RSC_IHPSG13_INVX2 +XA_DEC3INV<3> net23<28> A_SEL_P<3> VDD VSS / RSC_IHPSG13_INVX2 +XA_DEC3INV<2> net23<29> A_SEL_P<2> VDD VSS / RSC_IHPSG13_INVX2 +XA_DEC3INV<1> net23<30> A_SEL_P<1> VDD VSS / RSC_IHPSG13_INVX2 +XA_DEC3INV<0> net23<31> A_SEL_P<0> VDD VSS / RSC_IHPSG13_INVX2 +XA_I49 A_DI_R A_DI_N VDD VSS / RSC_IHPSG13_INVX2 +XB_ISENSE B_SAE B_BLC_SEL B_BLT_SEL net037 net038 VDD VSS / ++ RSC_IHPSG13_DFPQD_MSAFFX2 +XA_ISENSE A_SAE A_BLC_SEL A_BLT_SEL net19 net20 VDD VSS / ++ RSC_IHPSG13_DFPQD_MSAFFX2 +XB_DREG B_BIST_EN_I B_BIST_DW_I B_DCLK_B_L B_DW_I B_DI_R net042 VDD ++ VSS / RSC_IHPSG13_DFNQMX2IX1 +XB_BREG B_BIST_EN_I B_BIST_BM_I B_DCLK_B_L B_BM_I B_BM_R net043 VDD ++ VSS / RSC_IHPSG13_DFNQMX2IX1 +XA_DREG A_BIST_EN_I A_BIST_DW_I A_DCLK_B_L A_DW_I A_DI_R net22 VDD VSS ++ / RSC_IHPSG13_DFNQMX2IX1 +XA_BREG A_BIST_EN_I A_BIST_BM_I A_DCLK_B_L A_BM_I A_BM_R net21 VDD VSS ++ / RSC_IHPSG13_DFNQMX2IX1 +XB_DEC3<31> B_P1<1> B_P0<1> B_ADDR_DEC<7> net041<0> VDD VSS / ++ RSC_IHPSG13_NAND3X2 +XB_DEC3<30> B_P1<1> B_P0<1> B_ADDR_DEC<6> net041<1> VDD VSS / ++ RSC_IHPSG13_NAND3X2 +XB_DEC3<29> B_P1<1> B_P0<1> B_ADDR_DEC<5> net041<2> VDD VSS / ++ RSC_IHPSG13_NAND3X2 +XB_DEC3<28> B_P1<1> B_P0<1> B_ADDR_DEC<4> net041<3> VDD VSS / ++ RSC_IHPSG13_NAND3X2 +XB_DEC3<27> B_P1<1> B_P0<1> B_ADDR_DEC<3> net041<4> VDD VSS / ++ RSC_IHPSG13_NAND3X2 +XB_DEC3<26> B_P1<1> B_P0<1> B_ADDR_DEC<2> net041<5> VDD VSS / ++ RSC_IHPSG13_NAND3X2 +XB_DEC3<25> B_P1<1> B_P0<1> B_ADDR_DEC<1> net041<6> VDD VSS / ++ RSC_IHPSG13_NAND3X2 +XB_DEC3<24> B_P1<1> B_P0<1> B_ADDR_DEC<0> net041<7> VDD VSS / ++ RSC_IHPSG13_NAND3X2 +XB_DEC3<23> B_P1<1> B_N0<1> B_ADDR_DEC<7> net041<8> VDD VSS / ++ RSC_IHPSG13_NAND3X2 +XB_DEC3<22> B_P1<1> B_N0<1> B_ADDR_DEC<6> net041<9> VDD VSS / ++ RSC_IHPSG13_NAND3X2 +XB_DEC3<21> B_P1<1> B_N0<1> B_ADDR_DEC<5> net041<10> VDD VSS / ++ RSC_IHPSG13_NAND3X2 +XB_DEC3<20> B_P1<1> B_N0<1> B_ADDR_DEC<4> net041<11> VDD VSS / ++ RSC_IHPSG13_NAND3X2 +XB_DEC3<19> B_P1<1> B_N0<1> B_ADDR_DEC<3> net041<12> VDD VSS / ++ RSC_IHPSG13_NAND3X2 +XB_DEC3<18> B_P1<1> B_N0<1> B_ADDR_DEC<2> net041<13> VDD VSS / ++ RSC_IHPSG13_NAND3X2 +XB_DEC3<17> B_P1<1> B_N0<1> B_ADDR_DEC<1> net041<14> VDD VSS / ++ RSC_IHPSG13_NAND3X2 +XB_DEC3<16> B_P1<1> B_N0<1> B_ADDR_DEC<0> net041<15> VDD VSS / ++ RSC_IHPSG13_NAND3X2 +XB_DEC3<15> B_N1<0> B_P0<0> B_ADDR_DEC<7> net041<16> VDD VSS / ++ RSC_IHPSG13_NAND3X2 +XB_DEC3<14> B_N1<0> B_P0<0> B_ADDR_DEC<6> net041<17> VDD VSS / ++ RSC_IHPSG13_NAND3X2 +XB_DEC3<13> B_N1<0> B_P0<0> B_ADDR_DEC<5> net041<18> VDD VSS / ++ RSC_IHPSG13_NAND3X2 +XB_DEC3<12> B_N1<0> B_P0<0> B_ADDR_DEC<4> net041<19> VDD VSS / ++ RSC_IHPSG13_NAND3X2 +XB_DEC3<11> B_N1<0> B_P0<0> B_ADDR_DEC<3> net041<20> VDD VSS / ++ RSC_IHPSG13_NAND3X2 +XB_DEC3<10> B_N1<0> B_P0<0> B_ADDR_DEC<2> net041<21> VDD VSS / ++ RSC_IHPSG13_NAND3X2 +XB_DEC3<9> B_N1<0> B_P0<0> B_ADDR_DEC<1> net041<22> VDD VSS / ++ RSC_IHPSG13_NAND3X2 +XB_DEC3<8> B_N1<0> B_P0<0> B_ADDR_DEC<0> net041<23> VDD VSS / ++ RSC_IHPSG13_NAND3X2 +XB_DEC3<7> B_N1<0> B_N0<0> B_ADDR_DEC<7> net041<24> VDD VSS / ++ RSC_IHPSG13_NAND3X2 +XB_DEC3<6> B_N1<0> B_N0<0> B_ADDR_DEC<6> net041<25> VDD VSS / ++ RSC_IHPSG13_NAND3X2 +XB_DEC3<5> B_N1<0> B_N0<0> B_ADDR_DEC<5> net041<26> VDD VSS / ++ RSC_IHPSG13_NAND3X2 +XB_DEC3<4> B_N1<0> B_N0<0> B_ADDR_DEC<4> net041<27> VDD VSS / ++ RSC_IHPSG13_NAND3X2 +XB_DEC3<3> B_N1<0> B_N0<0> B_ADDR_DEC<3> net041<28> VDD VSS / ++ RSC_IHPSG13_NAND3X2 +XB_DEC3<2> B_N1<0> B_N0<0> B_ADDR_DEC<2> net041<29> VDD VSS / ++ RSC_IHPSG13_NAND3X2 +XB_DEC3<1> B_N1<0> B_N0<0> B_ADDR_DEC<1> net041<30> VDD VSS / ++ RSC_IHPSG13_NAND3X2 +XB_DEC3<0> B_N1<0> B_N0<0> B_ADDR_DEC<0> net041<31> VDD VSS / ++ RSC_IHPSG13_NAND3X2 +XA_DEC3<31> A_P1<1> A_P0<1> A_ADDR_DEC<7> net23<0> VDD VSS / ++ RSC_IHPSG13_NAND3X2 +XA_DEC3<30> A_P1<1> A_P0<1> A_ADDR_DEC<6> net23<1> VDD VSS / ++ RSC_IHPSG13_NAND3X2 +XA_DEC3<29> A_P1<1> A_P0<1> A_ADDR_DEC<5> net23<2> VDD VSS / ++ RSC_IHPSG13_NAND3X2 +XA_DEC3<28> A_P1<1> A_P0<1> A_ADDR_DEC<4> net23<3> VDD VSS / ++ RSC_IHPSG13_NAND3X2 +XA_DEC3<27> A_P1<1> A_P0<1> A_ADDR_DEC<3> net23<4> VDD VSS / ++ RSC_IHPSG13_NAND3X2 +XA_DEC3<26> A_P1<1> A_P0<1> A_ADDR_DEC<2> net23<5> VDD VSS / ++ RSC_IHPSG13_NAND3X2 +XA_DEC3<25> A_P1<1> A_P0<1> A_ADDR_DEC<1> net23<6> VDD VSS / ++ RSC_IHPSG13_NAND3X2 +XA_DEC3<24> A_P1<1> A_P0<1> A_ADDR_DEC<0> net23<7> VDD VSS / ++ RSC_IHPSG13_NAND3X2 +XA_DEC3<23> A_P1<1> A_N0<1> A_ADDR_DEC<7> net23<8> VDD VSS / ++ RSC_IHPSG13_NAND3X2 +XA_DEC3<22> A_P1<1> A_N0<1> A_ADDR_DEC<6> net23<9> VDD VSS / ++ RSC_IHPSG13_NAND3X2 +XA_DEC3<21> A_P1<1> A_N0<1> A_ADDR_DEC<5> net23<10> VDD VSS / ++ RSC_IHPSG13_NAND3X2 +XA_DEC3<20> A_P1<1> A_N0<1> A_ADDR_DEC<4> net23<11> VDD VSS / ++ RSC_IHPSG13_NAND3X2 +XA_DEC3<19> A_P1<1> A_N0<1> A_ADDR_DEC<3> net23<12> VDD VSS / ++ RSC_IHPSG13_NAND3X2 +XA_DEC3<18> A_P1<1> A_N0<1> A_ADDR_DEC<2> net23<13> VDD VSS / ++ RSC_IHPSG13_NAND3X2 +XA_DEC3<17> A_P1<1> A_N0<1> A_ADDR_DEC<1> net23<14> VDD VSS / ++ RSC_IHPSG13_NAND3X2 +XA_DEC3<16> A_P1<1> A_N0<1> A_ADDR_DEC<0> net23<15> VDD VSS / ++ RSC_IHPSG13_NAND3X2 +XA_DEC3<15> A_N1<0> A_P0<0> A_ADDR_DEC<7> net23<16> VDD VSS / ++ RSC_IHPSG13_NAND3X2 +XA_DEC3<14> A_N1<0> A_P0<0> A_ADDR_DEC<6> net23<17> VDD VSS / ++ RSC_IHPSG13_NAND3X2 +XA_DEC3<13> A_N1<0> A_P0<0> A_ADDR_DEC<5> net23<18> VDD VSS / ++ RSC_IHPSG13_NAND3X2 +XA_DEC3<12> A_N1<0> A_P0<0> A_ADDR_DEC<4> net23<19> VDD VSS / ++ RSC_IHPSG13_NAND3X2 +XA_DEC3<11> A_N1<0> A_P0<0> A_ADDR_DEC<3> net23<20> VDD VSS / ++ RSC_IHPSG13_NAND3X2 +XA_DEC3<10> A_N1<0> A_P0<0> A_ADDR_DEC<2> net23<21> VDD VSS / ++ RSC_IHPSG13_NAND3X2 +XA_DEC3<9> A_N1<0> A_P0<0> A_ADDR_DEC<1> net23<22> VDD VSS / ++ RSC_IHPSG13_NAND3X2 +XA_DEC3<8> A_N1<0> A_P0<0> A_ADDR_DEC<0> net23<23> VDD VSS / ++ RSC_IHPSG13_NAND3X2 +XA_DEC3<7> A_N1<0> A_N0<0> A_ADDR_DEC<7> net23<24> VDD VSS / ++ RSC_IHPSG13_NAND3X2 +XA_DEC3<6> A_N1<0> A_N0<0> A_ADDR_DEC<6> net23<25> VDD VSS / ++ RSC_IHPSG13_NAND3X2 +XA_DEC3<5> A_N1<0> A_N0<0> A_ADDR_DEC<5> net23<26> VDD VSS / ++ RSC_IHPSG13_NAND3X2 +XA_DEC3<4> A_N1<0> A_N0<0> A_ADDR_DEC<4> net23<27> VDD VSS / ++ RSC_IHPSG13_NAND3X2 +XA_DEC3<3> A_N1<0> A_N0<0> A_ADDR_DEC<3> net23<28> VDD VSS / ++ RSC_IHPSG13_NAND3X2 +XA_DEC3<2> A_N1<0> A_N0<0> A_ADDR_DEC<2> net23<29> VDD VSS / ++ RSC_IHPSG13_NAND3X2 +XA_DEC3<1> A_N1<0> A_N0<0> A_ADDR_DEC<1> net23<30> VDD VSS / ++ RSC_IHPSG13_NAND3X2 +XA_DEC3<0> A_N1<0> A_N0<0> A_ADDR_DEC<0> net23<31> VDD VSS / ++ RSC_IHPSG13_NAND3X2 +XB_I89 B_DCLK_B_L B_DCLK_B_R / RSC_IHPSG13_MET3RES +XB_I91 B_RCLK_B_L B_RCLK_B_R / RSC_IHPSG13_MET3RES +XB_I90 B_WCLK_B_L B_WCLK_B_R / RSC_IHPSG13_MET3RES +XB_I88 B_DCLK_L B_DCLK_R / RSC_IHPSG13_MET3RES +XB_I87 B_WCLK_L B_WCLK_R / RSC_IHPSG13_MET3RES +XB_R2 B_RCLK_L B_RCLK_R / RSC_IHPSG13_MET3RES +XA_I89 A_DCLK_B_L A_DCLK_B_R / RSC_IHPSG13_MET3RES +XA_I91 A_RCLK_B_L A_RCLK_B_R / RSC_IHPSG13_MET3RES +XA_I90 A_WCLK_B_L A_WCLK_B_R / RSC_IHPSG13_MET3RES +XA_I88 A_DCLK_L A_DCLK_R / RSC_IHPSG13_MET3RES +XA_I87 A_WCLK_L A_WCLK_R / RSC_IHPSG13_MET3RES +XA_R2 A_RCLK_L A_RCLK_R / RSC_IHPSG13_MET3RES +XB_BM_TIEH B_TIEH_O VDD VSS / RSC_IHPSG13_TIEH +XA_BM_TIEH A_TIEH_O VDD VSS / RSC_IHPSG13_TIEH +.ENDS +.SUBCKT RM_IHPSG13_512x32_c2_2P_COLDRV13_FILL4 VDD VSS +XI0<11> VDD VSS / RSC_IHPSG13_FILLCAP4 +XI0<10> VDD VSS / RSC_IHPSG13_FILLCAP4 +XI0<9> VDD VSS / RSC_IHPSG13_FILLCAP4 +XI0<8> VDD VSS / RSC_IHPSG13_FILLCAP4 +XI0<7> VDD VSS / RSC_IHPSG13_FILLCAP4 +XI0<6> VDD VSS / RSC_IHPSG13_FILLCAP4 +XI0<5> VDD VSS / RSC_IHPSG13_FILLCAP4 +XI0<4> VDD VSS / RSC_IHPSG13_FILLCAP4 +XI0<3> VDD VSS / RSC_IHPSG13_FILLCAP4 +XI0<2> VDD VSS / RSC_IHPSG13_FILLCAP4 +XI0<1> VDD VSS / RSC_IHPSG13_FILLCAP4 +.ENDS + + +.SUBCKT RSC_IHPSG13_CBUFX16 A Z VDD VSS +MN0 net4 A VSS VSS sg13_lv_nmos m=1 w=2.115u l=130.00n ng=3 nrd=0 nrs=0 +MN1 Z net4 VSS VSS sg13_lv_nmos m=1 w=5.64u l=130.00n ng=8 nrd=0 nrs=0 +MP1 Z net4 VDD VDD sg13_lv_pmos m=1 w=13.000u l=130.00n ng=8 nrd=0 ++ nrs=0 +MP0 net4 A VDD VDD sg13_lv_pmos m=1 w=4.89u l=130.00n ng=3 nrd=0 nrs=0 +.ENDS +.SUBCKT RM_IHPSG13_512x32_c2_1P_COLDRV13X16 ADDR_COL_I<1> ADDR_COL_I<0> ADDR_COL_O<1> ++ ADDR_COL_O<0> ADDR_DEC_I<7> ADDR_DEC_I<6> ADDR_DEC_I<5> ADDR_DEC_I<4> ++ ADDR_DEC_I<3> ADDR_DEC_I<2> ADDR_DEC_I<1> ADDR_DEC_I<0> ADDR_DEC_O<7> ++ ADDR_DEC_O<6> ADDR_DEC_O<5> ADDR_DEC_O<4> ADDR_DEC_O<3> ADDR_DEC_O<2> ++ ADDR_DEC_O<1> ADDR_DEC_O<0> DCLK_I DCLK_O RCLK_I RCLK_O WCLK_I WCLK_O ++ VDD VSS +XI1<1> VDD VSS / RSC_IHPSG13_FILLCAP4 +XI1<0> VDD VSS / RSC_IHPSG13_FILLCAP4 +XI0<3> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI0<2> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI0<1> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI0<0> VDD VSS / RSC_IHPSG13_FILLCAP8 +XADDR_COL_DRV<1> ADDR_COL_I<1> ADDR_COL_O<1> VDD VSS / ++ RSC_IHPSG13_CBUFX16 +XADDR_COL_DRV<0> ADDR_COL_I<0> ADDR_COL_O<0> VDD VSS / ++ RSC_IHPSG13_CBUFX16 +XADDR_DEC_DRV<7> ADDR_DEC_I<7> ADDR_DEC_O<7> VDD VSS / ++ RSC_IHPSG13_CBUFX16 +XADDR_DEC_DRV<6> ADDR_DEC_I<6> ADDR_DEC_O<6> VDD VSS / ++ RSC_IHPSG13_CBUFX16 +XADDR_DEC_DRV<5> ADDR_DEC_I<5> ADDR_DEC_O<5> VDD VSS / ++ RSC_IHPSG13_CBUFX16 +XADDR_DEC_DRV<4> ADDR_DEC_I<4> ADDR_DEC_O<4> VDD VSS / ++ RSC_IHPSG13_CBUFX16 +XADDR_DEC_DRV<3> ADDR_DEC_I<3> ADDR_DEC_O<3> VDD VSS / ++ RSC_IHPSG13_CBUFX16 +XADDR_DEC_DRV<2> ADDR_DEC_I<2> ADDR_DEC_O<2> VDD VSS / ++ RSC_IHPSG13_CBUFX16 +XADDR_DEC_DRV<1> ADDR_DEC_I<1> ADDR_DEC_O<1> VDD VSS / ++ RSC_IHPSG13_CBUFX16 +XADDR_DEC_DRV<0> ADDR_DEC_I<0> ADDR_DEC_O<0> VDD VSS / ++ RSC_IHPSG13_CBUFX16 +XDCLK_DRV DCLK_I DCLK_O VDD VSS / RSC_IHPSG13_CBUFX16 +XRCLK_DRV RCLK_I RCLK_O VDD VSS / RSC_IHPSG13_CBUFX16 +XWCLK_DRV WCLK_I WCLK_O VDD VSS / RSC_IHPSG13_CBUFX16 +.ENDS +.SUBCKT RSC_IHPSG13_WLDRVX16 A Z VDD VSS +MN1 Z net6 VSS VSS sg13_lv_nmos m=1 w=1.41u l=130.00n ng=2 nrd=0 nrs=0 +MN0 net6 A VSS VSS sg13_lv_nmos m=1 w=1.8u l=130.00n ng=2 nrd=0 nrs=0 +MP1 Z net6 VDD VDD sg13_lv_pmos m=1 w=12.96u l=130.00n ng=8 nrd=0 nrs=0 +MP0 net6 A VDD VDD sg13_lv_pmos m=1 w=900.0n l=130.00n ng=1 nrd=0 nrs=0 +.ENDS +.SUBCKT RM_IHPSG13_512x32_c2_1P_WLDRV16X16 A<15> A<14> A<13> A<12> A<11> A<10> A<9> A<8> ++ A<7> A<6> A<5> A<4> A<3> A<2> A<1> A<0> Z<15> Z<14> Z<13> Z<12> Z<11> Z<10> ++ Z<9> Z<8> Z<7> Z<6> Z<5> Z<4> Z<3> Z<2> Z<1> Z<0> VDD VSS +XBUF<15> A<15> Z<15> VDD VSS / RSC_IHPSG13_WLDRVX16 +XBUF<14> A<14> Z<14> VDD VSS / RSC_IHPSG13_WLDRVX16 +XBUF<13> A<13> Z<13> VDD VSS / RSC_IHPSG13_WLDRVX16 +XBUF<12> A<12> Z<12> VDD VSS / RSC_IHPSG13_WLDRVX16 +XBUF<11> A<11> Z<11> VDD VSS / RSC_IHPSG13_WLDRVX16 +XBUF<10> A<10> Z<10> VDD VSS / RSC_IHPSG13_WLDRVX16 +XBUF<9> A<9> Z<9> VDD VSS / RSC_IHPSG13_WLDRVX16 +XBUF<8> A<8> Z<8> VDD VSS / RSC_IHPSG13_WLDRVX16 +XBUF<7> A<7> Z<7> VDD VSS / RSC_IHPSG13_WLDRVX16 +XBUF<6> A<6> Z<6> VDD VSS / RSC_IHPSG13_WLDRVX16 +XBUF<5> A<5> Z<5> VDD VSS / RSC_IHPSG13_WLDRVX16 +XBUF<4> A<4> Z<4> VDD VSS / RSC_IHPSG13_WLDRVX16 +XBUF<3> A<3> Z<3> VDD VSS / RSC_IHPSG13_WLDRVX16 +XBUF<2> A<2> Z<2> VDD VSS / RSC_IHPSG13_WLDRVX16 +XBUF<1> A<1> Z<1> VDD VSS / RSC_IHPSG13_WLDRVX16 +XBUF<0> A<0> Z<0> VDD VSS / RSC_IHPSG13_WLDRVX16 +.ENDS + + +.SUBCKT RM_IHPSG13_512x32_c2_2P_COLDRV13X4 ADDR_COL_I<1> ADDR_COL_I<0> ADDR_COL_O<1> ++ ADDR_COL_O<0> ADDR_DEC_I<7> ADDR_DEC_I<6> ADDR_DEC_I<5> ADDR_DEC_I<4> ++ ADDR_DEC_I<3> ADDR_DEC_I<2> ADDR_DEC_I<1> ADDR_DEC_I<0> ADDR_DEC_O<7> ++ ADDR_DEC_O<6> ADDR_DEC_O<5> ADDR_DEC_O<4> ADDR_DEC_O<3> ADDR_DEC_O<2> ++ ADDR_DEC_O<1> ADDR_DEC_O<0> DCLK_I DCLK_O RCLK_I RCLK_O WCLK_I WCLK_O ++ VDD VSS +XWCLK_DRV WCLK_I WCLK_O VDD VSS / RSC_IHPSG13_CBUFX4 +XRCLK_DRV RCLK_I RCLK_O VDD VSS / RSC_IHPSG13_CBUFX4 +XDCLK_DRV DCLK_I DCLK_O VDD VSS / RSC_IHPSG13_CBUFX4 +XADDR_COL_DRV<1> ADDR_COL_I<1> ADDR_COL_O<1> VDD VSS / ++ RSC_IHPSG13_CBUFX4 +XADDR_COL_DRV<0> ADDR_COL_I<0> ADDR_COL_O<0> VDD VSS / ++ RSC_IHPSG13_CBUFX4 +XADDR_DEC_DRV<7> ADDR_DEC_I<7> ADDR_DEC_O<7> VDD VSS / ++ RSC_IHPSG13_CBUFX4 +XADDR_DEC_DRV<6> ADDR_DEC_I<6> ADDR_DEC_O<6> VDD VSS / ++ RSC_IHPSG13_CBUFX4 +XADDR_DEC_DRV<5> ADDR_DEC_I<5> ADDR_DEC_O<5> VDD VSS / ++ RSC_IHPSG13_CBUFX4 +XADDR_DEC_DRV<4> ADDR_DEC_I<4> ADDR_DEC_O<4> VDD VSS / ++ RSC_IHPSG13_CBUFX4 +XADDR_DEC_DRV<3> ADDR_DEC_I<3> ADDR_DEC_O<3> VDD VSS / ++ RSC_IHPSG13_CBUFX4 +XADDR_DEC_DRV<2> ADDR_DEC_I<2> ADDR_DEC_O<2> VDD VSS / ++ RSC_IHPSG13_CBUFX4 +XADDR_DEC_DRV<1> ADDR_DEC_I<1> ADDR_DEC_O<1> VDD VSS / ++ RSC_IHPSG13_CBUFX4 +XADDR_DEC_DRV<0> ADDR_DEC_I<0> ADDR_DEC_O<0> VDD VSS / ++ RSC_IHPSG13_CBUFX4 +XI0<6> VDD VSS / RSC_IHPSG13_FILLCAP4 +XI0<5> VDD VSS / RSC_IHPSG13_FILLCAP4 +XI0<4> VDD VSS / RSC_IHPSG13_FILLCAP4 +XI0<3> VDD VSS / RSC_IHPSG13_FILLCAP4 +XI0<2> VDD VSS / RSC_IHPSG13_FILLCAP4 +XI0<1> VDD VSS / RSC_IHPSG13_FILLCAP4 +XI1 VDD VSS / RSC_IHPSG13_FILLCAP8 +.ENDS +.SUBCKT RM_IHPSG13_512x32_c2_2P_WLDRV16X4 A<15> A<14> A<13> A<12> A<11> A<10> A<9> A<8> ++ A<7> A<6> A<5> A<4> A<3> A<2> A<1> A<0> Z<15> Z<14> Z<13> Z<12> Z<11> Z<10> ++ Z<9> Z<8> Z<7> Z<6> Z<5> Z<4> Z<3> Z<2> Z<1> Z<0> VDD VSS +XBUF<15> A<15> Z<15> VDD VSS / RSC_IHPSG13_WLDRVX4 +XBUF<14> A<14> Z<14> VDD VSS / RSC_IHPSG13_WLDRVX4 +XBUF<13> A<13> Z<13> VDD VSS / RSC_IHPSG13_WLDRVX4 +XBUF<12> A<12> Z<12> VDD VSS / RSC_IHPSG13_WLDRVX4 +XBUF<11> A<11> Z<11> VDD VSS / RSC_IHPSG13_WLDRVX4 +XBUF<10> A<10> Z<10> VDD VSS / RSC_IHPSG13_WLDRVX4 +XBUF<9> A<9> Z<9> VDD VSS / RSC_IHPSG13_WLDRVX4 +XBUF<8> A<8> Z<8> VDD VSS / RSC_IHPSG13_WLDRVX4 +XBUF<7> A<7> Z<7> VDD VSS / RSC_IHPSG13_WLDRVX4 +XBUF<6> A<6> Z<6> VDD VSS / RSC_IHPSG13_WLDRVX4 +XBUF<5> A<5> Z<5> VDD VSS / RSC_IHPSG13_WLDRVX4 +XBUF<4> A<4> Z<4> VDD VSS / RSC_IHPSG13_WLDRVX4 +XBUF<3> A<3> Z<3> VDD VSS / RSC_IHPSG13_WLDRVX4 +XBUF<2> A<2> Z<2> VDD VSS / RSC_IHPSG13_WLDRVX4 +XBUF<1> A<1> Z<1> VDD VSS / RSC_IHPSG13_WLDRVX4 +XBUF<0> A<0> Z<0> VDD VSS / RSC_IHPSG13_WLDRVX4 +.ENDS +.SUBCKT RM_IHPSG13_512x32_c2_2P_ROWDEC8 ADDR_N_I<7> ADDR_N_I<6> ADDR_N_I<5> ADDR_N_I<4> ++ ADDR_N_I<3> ADDR_N_I<2> ADDR_N_I<1> ADDR_N_I<0> CS_I ECLK_I WL_O<255> ++ WL_O<254> WL_O<253> WL_O<252> WL_O<251> WL_O<250> WL_O<249> WL_O<248> ++ WL_O<247> WL_O<246> WL_O<245> WL_O<244> WL_O<243> WL_O<242> WL_O<241> ++ WL_O<240> WL_O<239> WL_O<238> WL_O<237> WL_O<236> WL_O<235> WL_O<234> ++ WL_O<233> WL_O<232> WL_O<231> WL_O<230> WL_O<229> WL_O<228> WL_O<227> ++ WL_O<226> WL_O<225> WL_O<224> WL_O<223> WL_O<222> WL_O<221> WL_O<220> ++ WL_O<219> WL_O<218> WL_O<217> WL_O<216> WL_O<215> WL_O<214> WL_O<213> ++ WL_O<212> WL_O<211> WL_O<210> WL_O<209> WL_O<208> WL_O<207> WL_O<206> ++ WL_O<205> WL_O<204> WL_O<203> WL_O<202> WL_O<201> WL_O<200> WL_O<199> ++ WL_O<198> WL_O<197> WL_O<196> WL_O<195> WL_O<194> WL_O<193> WL_O<192> ++ WL_O<191> WL_O<190> WL_O<189> WL_O<188> WL_O<187> WL_O<186> WL_O<185> ++ WL_O<184> WL_O<183> WL_O<182> WL_O<181> WL_O<180> WL_O<179> WL_O<178> ++ WL_O<177> WL_O<176> WL_O<175> WL_O<174> WL_O<173> WL_O<172> WL_O<171> ++ WL_O<170> WL_O<169> WL_O<168> WL_O<167> WL_O<166> WL_O<165> WL_O<164> ++ WL_O<163> WL_O<162> WL_O<161> WL_O<160> WL_O<159> WL_O<158> WL_O<157> ++ WL_O<156> WL_O<155> WL_O<154> WL_O<153> WL_O<152> WL_O<151> WL_O<150> ++ WL_O<149> WL_O<148> WL_O<147> WL_O<146> WL_O<145> WL_O<144> WL_O<143> ++ WL_O<142> WL_O<141> WL_O<140> WL_O<139> WL_O<138> WL_O<137> WL_O<136> ++ WL_O<135> WL_O<134> WL_O<133> WL_O<132> WL_O<131> WL_O<130> WL_O<129> ++ WL_O<128> WL_O<127> WL_O<126> WL_O<125> WL_O<124> WL_O<123> WL_O<122> ++ WL_O<121> WL_O<120> WL_O<119> WL_O<118> WL_O<117> WL_O<116> WL_O<115> ++ WL_O<114> WL_O<113> WL_O<112> WL_O<111> WL_O<110> WL_O<109> WL_O<108> ++ WL_O<107> WL_O<106> WL_O<105> WL_O<104> WL_O<103> WL_O<102> WL_O<101> ++ WL_O<100> WL_O<99> WL_O<98> WL_O<97> WL_O<96> WL_O<95> WL_O<94> WL_O<93> ++ WL_O<92> WL_O<91> WL_O<90> WL_O<89> WL_O<88> WL_O<87> WL_O<86> WL_O<85> ++ WL_O<84> WL_O<83> WL_O<82> WL_O<81> WL_O<80> WL_O<79> WL_O<78> WL_O<77> ++ WL_O<76> WL_O<75> WL_O<74> WL_O<73> WL_O<72> WL_O<71> WL_O<70> WL_O<69> ++ WL_O<68> WL_O<67> WL_O<66> WL_O<65> WL_O<64> WL_O<63> WL_O<62> WL_O<61> ++ WL_O<60> WL_O<59> WL_O<58> WL_O<57> WL_O<56> WL_O<55> WL_O<54> WL_O<53> ++ WL_O<52> WL_O<51> WL_O<50> WL_O<49> WL_O<48> WL_O<47> WL_O<46> WL_O<45> ++ WL_O<44> WL_O<43> WL_O<42> WL_O<41> WL_O<40> WL_O<39> WL_O<38> WL_O<37> ++ WL_O<36> WL_O<35> WL_O<34> WL_O<33> WL_O<32> WL_O<31> WL_O<30> WL_O<29> ++ WL_O<28> WL_O<27> WL_O<26> WL_O<25> WL_O<24> WL_O<23> WL_O<22> WL_O<21> ++ WL_O<20> WL_O<19> WL_O<18> WL_O<17> WL_O<16> WL_O<15> WL_O<14> WL_O<13> ++ WL_O<12> WL_O<11> WL_O<10> WL_O<9> WL_O<8> WL_O<7> WL_O<6> WL_O<5> WL_O<4> ++ WL_O<3> WL_O<2> WL_O<1> WL_O<0> VDD VSS +XDEC11<4> ADDR_N_I<7> ADDR_N_I<6> CS_I CS04<3> VDD VSS / ++ RM_IHPSG13_512x32_c2_2P_DEC03 +XDEC11<3> ADDR_N_I<5> ADDR_N_I<4> CS04<3> CS00<15> VDD VSS / ++ RM_IHPSG13_512x32_c2_2P_DEC03 +XDEC11<2> ADDR_N_I<5> ADDR_N_I<4> CS04<2> CS00<11> VDD VSS / ++ RM_IHPSG13_512x32_c2_2P_DEC03 +XDEC11<1> ADDR_N_I<5> ADDR_N_I<4> CS04<1> CS00<7> VDD VSS / ++ RM_IHPSG13_512x32_c2_2P_DEC03 +XDEC11<0> ADDR_N_I<5> ADDR_N_I<4> CS04<0> CS00<3> VDD VSS / ++ RM_IHPSG13_512x32_c2_2P_DEC03 +XSEL<15> ADDR_N_I<3> ADDR_N_I<2> ADDR_N_I<1> ADDR_N_I<0> CS00<15> ECLK_H<15> ++ ECLK_H<16> ECLK_B<15> ECLK_B<16> WL_O<255> WL_O<254> WL_O<253> WL_O<252> ++ WL_O<251> WL_O<250> WL_O<249> WL_O<248> WL_O<247> WL_O<246> WL_O<245> ++ WL_O<244> WL_O<243> WL_O<242> WL_O<241> WL_O<240> VDD VSS / ++ RM_IHPSG13_512x32_c2_2P_DEC04 +XSEL<14> ADDR_N_I<3> ADDR_N_I<2> ADDR_N_I<1> ADDR_N_I<0> CS00<14> ECLK_H<14> ++ ECLK_H<15> ECLK_B<14> ECLK_B<15> WL_O<239> WL_O<238> WL_O<237> WL_O<236> ++ WL_O<235> WL_O<234> WL_O<233> WL_O<232> WL_O<231> WL_O<230> WL_O<229> ++ WL_O<228> WL_O<227> WL_O<226> WL_O<225> WL_O<224> VDD VSS / ++ RM_IHPSG13_512x32_c2_2P_DEC04 +XSEL<13> ADDR_N_I<3> ADDR_N_I<2> ADDR_N_I<1> ADDR_N_I<0> CS00<13> ECLK_H<13> ++ ECLK_H<14> ECLK_B<13> ECLK_B<14> WL_O<223> WL_O<222> WL_O<221> WL_O<220> ++ WL_O<219> WL_O<218> WL_O<217> WL_O<216> WL_O<215> WL_O<214> WL_O<213> ++ WL_O<212> WL_O<211> WL_O<210> WL_O<209> WL_O<208> VDD VSS / ++ RM_IHPSG13_512x32_c2_2P_DEC04 +XSEL<12> ADDR_N_I<3> ADDR_N_I<2> ADDR_N_I<1> ADDR_N_I<0> CS00<12> ECLK_H<12> ++ ECLK_H<13> ECLK_B<12> ECLK_B<13> WL_O<207> WL_O<206> WL_O<205> WL_O<204> ++ WL_O<203> WL_O<202> WL_O<201> WL_O<200> WL_O<199> WL_O<198> WL_O<197> ++ WL_O<196> WL_O<195> WL_O<194> WL_O<193> WL_O<192> VDD VSS / ++ RM_IHPSG13_512x32_c2_2P_DEC04 +XSEL<11> ADDR_N_I<3> ADDR_N_I<2> ADDR_N_I<1> ADDR_N_I<0> CS00<11> ECLK_H<11> ++ ECLK_H<12> ECLK_B<11> ECLK_B<12> WL_O<191> WL_O<190> WL_O<189> WL_O<188> ++ WL_O<187> WL_O<186> WL_O<185> WL_O<184> WL_O<183> WL_O<182> WL_O<181> ++ WL_O<180> WL_O<179> WL_O<178> WL_O<177> WL_O<176> VDD VSS / ++ RM_IHPSG13_512x32_c2_2P_DEC04 +XSEL<10> ADDR_N_I<3> ADDR_N_I<2> ADDR_N_I<1> ADDR_N_I<0> CS00<10> ECLK_H<10> ++ ECLK_H<11> ECLK_B<10> ECLK_B<11> WL_O<175> WL_O<174> WL_O<173> WL_O<172> ++ WL_O<171> WL_O<170> WL_O<169> WL_O<168> WL_O<167> WL_O<166> WL_O<165> ++ WL_O<164> WL_O<163> WL_O<162> WL_O<161> WL_O<160> VDD VSS / ++ RM_IHPSG13_512x32_c2_2P_DEC04 +XSEL<9> ADDR_N_I<3> ADDR_N_I<2> ADDR_N_I<1> ADDR_N_I<0> CS00<9> ECLK_H<9> ++ ECLK_H<10> ECLK_B<9> ECLK_B<10> WL_O<159> WL_O<158> WL_O<157> WL_O<156> ++ WL_O<155> WL_O<154> WL_O<153> WL_O<152> WL_O<151> WL_O<150> WL_O<149> ++ WL_O<148> WL_O<147> WL_O<146> WL_O<145> WL_O<144> VDD VSS / ++ RM_IHPSG13_512x32_c2_2P_DEC04 +XSEL<8> ADDR_N_I<3> ADDR_N_I<2> ADDR_N_I<1> ADDR_N_I<0> CS00<8> ECLK_H<8> ++ ECLK_H<9> ECLK_B<8> ECLK_B<9> WL_O<143> WL_O<142> WL_O<141> WL_O<140> ++ WL_O<139> WL_O<138> WL_O<137> WL_O<136> WL_O<135> WL_O<134> WL_O<133> ++ WL_O<132> WL_O<131> WL_O<130> WL_O<129> WL_O<128> VDD VSS / ++ RM_IHPSG13_512x32_c2_2P_DEC04 +XSEL<7> ADDR_N_I<3> ADDR_N_I<2> ADDR_N_I<1> ADDR_N_I<0> CS00<7> ECLK_H<7> ++ ECLK_H<8> ECLK_B<7> ECLK_B<8> WL_O<127> WL_O<126> WL_O<125> WL_O<124> ++ WL_O<123> WL_O<122> WL_O<121> WL_O<120> WL_O<119> WL_O<118> WL_O<117> ++ WL_O<116> WL_O<115> WL_O<114> WL_O<113> WL_O<112> VDD VSS / ++ RM_IHPSG13_512x32_c2_2P_DEC04 +XSEL<6> ADDR_N_I<3> ADDR_N_I<2> ADDR_N_I<1> ADDR_N_I<0> CS00<6> ECLK_H<6> ++ ECLK_H<7> ECLK_B<6> ECLK_B<7> WL_O<111> WL_O<110> WL_O<109> WL_O<108> ++ WL_O<107> WL_O<106> WL_O<105> WL_O<104> WL_O<103> WL_O<102> WL_O<101> ++ WL_O<100> WL_O<99> WL_O<98> WL_O<97> WL_O<96> VDD VSS / ++ RM_IHPSG13_512x32_c2_2P_DEC04 +XSEL<5> ADDR_N_I<3> ADDR_N_I<2> ADDR_N_I<1> ADDR_N_I<0> CS00<5> ECLK_H<5> ++ ECLK_H<6> ECLK_B<5> ECLK_B<6> WL_O<95> WL_O<94> WL_O<93> WL_O<92> WL_O<91> ++ WL_O<90> WL_O<89> WL_O<88> WL_O<87> WL_O<86> WL_O<85> WL_O<84> WL_O<83> ++ WL_O<82> WL_O<81> WL_O<80> VDD VSS / RM_IHPSG13_512x32_c2_2P_DEC04 +XSEL<4> ADDR_N_I<3> ADDR_N_I<2> ADDR_N_I<1> ADDR_N_I<0> CS00<4> ECLK_H<4> ++ ECLK_H<5> ECLK_B<4> ECLK_B<5> WL_O<79> WL_O<78> WL_O<77> WL_O<76> WL_O<75> ++ WL_O<74> WL_O<73> WL_O<72> WL_O<71> WL_O<70> WL_O<69> WL_O<68> WL_O<67> ++ WL_O<66> WL_O<65> WL_O<64> VDD VSS / RM_IHPSG13_512x32_c2_2P_DEC04 +XSEL<3> ADDR_N_I<3> ADDR_N_I<2> ADDR_N_I<1> ADDR_N_I<0> CS00<3> ECLK_H<3> ++ ECLK_H<4> ECLK_B<3> ECLK_B<4> WL_O<63> WL_O<62> WL_O<61> WL_O<60> WL_O<59> ++ WL_O<58> WL_O<57> WL_O<56> WL_O<55> WL_O<54> WL_O<53> WL_O<52> WL_O<51> ++ WL_O<50> WL_O<49> WL_O<48> VDD VSS / RM_IHPSG13_512x32_c2_2P_DEC04 +XSEL<2> ADDR_N_I<3> ADDR_N_I<2> ADDR_N_I<1> ADDR_N_I<0> CS00<2> ECLK_H<2> ++ ECLK_H<3> ECLK_B<2> ECLK_B<3> WL_O<47> WL_O<46> WL_O<45> WL_O<44> WL_O<43> ++ WL_O<42> WL_O<41> WL_O<40> WL_O<39> WL_O<38> WL_O<37> WL_O<36> WL_O<35> ++ WL_O<34> WL_O<33> WL_O<32> VDD VSS / RM_IHPSG13_512x32_c2_2P_DEC04 +XSEL<1> ADDR_N_I<3> ADDR_N_I<2> ADDR_N_I<1> ADDR_N_I<0> CS00<1> ECLK_H<1> ++ ECLK_H<2> ECLK_B<1> ECLK_B<2> WL_O<31> WL_O<30> WL_O<29> WL_O<28> WL_O<27> ++ WL_O<26> WL_O<25> WL_O<24> WL_O<23> WL_O<22> WL_O<21> WL_O<20> WL_O<19> ++ WL_O<18> WL_O<17> WL_O<16> VDD VSS / RM_IHPSG13_512x32_c2_2P_DEC04 +XSEL<0> ADDR_N_I<3> ADDR_N_I<2> ADDR_N_I<1> ADDR_N_I<0> CS00<0> ECLK_I ++ ECLK_H<1> ECLK_B<0> ECLK_B<1> WL_O<15> WL_O<14> WL_O<13> WL_O<12> WL_O<11> ++ WL_O<10> WL_O<9> WL_O<8> WL_O<7> WL_O<6> WL_O<5> WL_O<4> WL_O<3> WL_O<2> ++ WL_O<1> WL_O<0> VDD VSS / RM_IHPSG13_512x32_c2_2P_DEC04 +XDEC10<4> ADDR_N_I<7> ADDR_N_I<6> CS_I CS04<2> VDD VSS / ++ RM_IHPSG13_512x32_c2_2P_DEC02 +XDEC10<3> ADDR_N_I<5> ADDR_N_I<4> CS04<3> CS00<14> VDD VSS / ++ RM_IHPSG13_512x32_c2_2P_DEC02 +XDEC10<2> ADDR_N_I<5> ADDR_N_I<4> CS04<2> CS00<10> VDD VSS / ++ RM_IHPSG13_512x32_c2_2P_DEC02 +XDEC10<1> ADDR_N_I<5> ADDR_N_I<4> CS04<1> CS00<6> VDD VSS / ++ RM_IHPSG13_512x32_c2_2P_DEC02 +XDEC10<0> ADDR_N_I<5> ADDR_N_I<4> CS04<0> CS00<2> VDD VSS / ++ RM_IHPSG13_512x32_c2_2P_DEC02 +XL2<132> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<131> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<130> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<129> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<128> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<127> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<126> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<125> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<124> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<123> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<122> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<121> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<120> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<119> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<118> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<117> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<116> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<115> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<114> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<113> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<112> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<111> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<110> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<109> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<108> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<107> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<106> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<105> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<104> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<103> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<102> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<101> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<100> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<99> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<98> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<97> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<96> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<95> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<94> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<93> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<92> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<91> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<90> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<89> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<88> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<87> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<86> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<85> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<84> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<83> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<82> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<81> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<80> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<79> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<78> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<77> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<76> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<75> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<74> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<73> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<72> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<71> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<70> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<69> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<68> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<67> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<66> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<65> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<64> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<63> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<62> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<61> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<60> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<59> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<58> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<57> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<56> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<55> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<54> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<53> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<52> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<51> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<50> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<49> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<48> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<47> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<46> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<45> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<44> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<43> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<42> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<41> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<40> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<39> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<38> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<37> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<36> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<35> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<34> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<33> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<32> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<31> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<30> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<29> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<28> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<27> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<26> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<25> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<24> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<23> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<22> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<21> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<20> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<19> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<18> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<17> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<16> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<15> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<14> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<13> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<12> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<11> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<10> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<9> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<8> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<7> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<6> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<5> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<4> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<3> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<2> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<1> VDD VSS / RSC_IHPSG13_FILLCAP8 +XDEC00<4> ADDR_N_I<7> ADDR_N_I<6> CS_I CS04<0> VDD VSS / ++ RM_IHPSG13_512x32_c2_2P_DEC00 +XDEC00<3> ADDR_N_I<5> ADDR_N_I<4> CS04<3> CS00<12> VDD VSS / ++ RM_IHPSG13_512x32_c2_2P_DEC00 +XDEC00<2> ADDR_N_I<5> ADDR_N_I<4> CS04<2> CS00<8> VDD VSS / ++ RM_IHPSG13_512x32_c2_2P_DEC00 +XDEC00<1> ADDR_N_I<5> ADDR_N_I<4> CS04<1> CS00<4> VDD VSS / ++ RM_IHPSG13_512x32_c2_2P_DEC00 +XDEC00<0> ADDR_N_I<5> ADDR_N_I<4> CS04<0> CS00<0> VDD VSS / ++ RM_IHPSG13_512x32_c2_2P_DEC00 +XDEC01<4> ADDR_N_I<7> ADDR_N_I<6> CS_I CS04<1> VDD VSS / ++ RM_IHPSG13_512x32_c2_2P_DEC01 +XDEC01<3> ADDR_N_I<5> ADDR_N_I<4> CS04<3> CS00<13> VDD VSS / ++ RM_IHPSG13_512x32_c2_2P_DEC01 +XDEC01<2> ADDR_N_I<5> ADDR_N_I<4> CS04<2> CS00<9> VDD VSS / ++ RM_IHPSG13_512x32_c2_2P_DEC01 +XDEC01<1> ADDR_N_I<5> ADDR_N_I<4> CS04<1> CS00<5> VDD VSS / ++ RM_IHPSG13_512x32_c2_2P_DEC01 +XDEC01<0> ADDR_N_I<5> ADDR_N_I<4> CS04<0> CS00<1> VDD VSS / ++ RM_IHPSG13_512x32_c2_2P_DEC01 +.ENDS +.SUBCKT RM_IHPSG13_512x32_c2_2P_ROWREG8 ACLK_N_I ADDR_I<7> ADDR_I<6> ADDR_I<5> ADDR_I<4> ++ ADDR_I<3> ADDR_I<2> ADDR_I<1> ADDR_I<0> ADDR_N_O<7> ADDR_N_O<6> ADDR_N_O<5> ++ ADDR_N_O<4> ADDR_N_O<3> ADDR_N_O<2> ADDR_N_O<1> ADDR_N_O<0> BIST_ADDR_I<7> ++ BIST_ADDR_I<6> BIST_ADDR_I<5> BIST_ADDR_I<4> BIST_ADDR_I<3> BIST_ADDR_I<2> ++ BIST_ADDR_I<1> BIST_ADDR_I<0> BIST_EN_I VDD VSS +XINV<7> q_int<7> qn_int<7> VDD VSS / RSC_IHPSG13_CINVX2 +XINV<6> q_int<6> qn_int<6> VDD VSS / RSC_IHPSG13_CINVX2 +XINV<5> q_int<5> qn_int<5> VDD VSS / RSC_IHPSG13_CINVX2 +XINV<4> q_int<4> qn_int<4> VDD VSS / RSC_IHPSG13_CINVX2 +XINV<3> q_int<3> qn_int<3> VDD VSS / RSC_IHPSG13_CINVX2 +XINV<2> q_int<2> qn_int<2> VDD VSS / RSC_IHPSG13_CINVX2 +XINV<1> q_int<1> qn_int<1> VDD VSS / RSC_IHPSG13_CINVX2 +XINV<0> q_int<0> qn_int<0> VDD VSS / RSC_IHPSG13_CINVX2 +XDRV<7> qn_int<7> ADDR_N_O<7> VDD VSS / RSC_IHPSG13_CINVX8 +XDRV<6> qn_int<6> ADDR_N_O<6> VDD VSS / RSC_IHPSG13_CINVX8 +XDRV<5> qn_int<5> ADDR_N_O<5> VDD VSS / RSC_IHPSG13_CINVX8 +XDRV<4> qn_int<4> ADDR_N_O<4> VDD VSS / RSC_IHPSG13_CINVX8 +XDRV<3> qn_int<3> ADDR_N_O<3> VDD VSS / RSC_IHPSG13_CINVX8 +XDRV<2> qn_int<2> ADDR_N_O<2> VDD VSS / RSC_IHPSG13_CINVX8 +XDRV<1> qn_int<1> ADDR_N_O<1> VDD VSS / RSC_IHPSG13_CINVX8 +XDRV<0> qn_int<0> ADDR_N_O<0> VDD VSS / RSC_IHPSG13_CINVX8 +XDFF<7> BIST_EN_I BIST_ADDR_I<7> ACLK_N_I ADDR_I<7> q_int<7> net2<0> VDD ++ VSS / RSC_IHPSG13_DFNQMX2IX1 +XDFF<6> BIST_EN_I BIST_ADDR_I<6> ACLK_N_I ADDR_I<6> q_int<6> net2<1> VDD ++ VSS / RSC_IHPSG13_DFNQMX2IX1 +XDFF<5> BIST_EN_I BIST_ADDR_I<5> ACLK_N_I ADDR_I<5> q_int<5> net2<2> VDD ++ VSS / RSC_IHPSG13_DFNQMX2IX1 +XDFF<4> BIST_EN_I BIST_ADDR_I<4> ACLK_N_I ADDR_I<4> q_int<4> net2<3> VDD ++ VSS / RSC_IHPSG13_DFNQMX2IX1 +XDFF<3> BIST_EN_I BIST_ADDR_I<3> ACLK_N_I ADDR_I<3> q_int<3> net2<4> VDD ++ VSS / RSC_IHPSG13_DFNQMX2IX1 +XDFF<2> BIST_EN_I BIST_ADDR_I<2> ACLK_N_I ADDR_I<2> q_int<2> net2<5> VDD ++ VSS / RSC_IHPSG13_DFNQMX2IX1 +XDFF<1> BIST_EN_I BIST_ADDR_I<1> ACLK_N_I ADDR_I<1> q_int<1> net2<6> VDD ++ VSS / RSC_IHPSG13_DFNQMX2IX1 +XDFF<0> BIST_EN_I BIST_ADDR_I<0> ACLK_N_I ADDR_I<0> q_int<0> net2<7> VDD ++ VSS / RSC_IHPSG13_DFNQMX2IX1 +XI11<4> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI11<3> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI11<2> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI11<1> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI10 VDD VSS / RSC_IHPSG13_FILLCAP4 +.ENDS +.SUBCKT RM_IHPSG13_512x32_c2_2P_COLDEC4 ACLK_N ADDR<3> ADDR<2> ADDR<1> ADDR<0> ++ ADDR_COL<1> ADDR_COL<0> ADDR_DEC<7> ADDR_DEC<6> ADDR_DEC<5> ADDR_DEC<4> ++ ADDR_DEC<3> ADDR_DEC<2> ADDR_DEC<1> ADDR_DEC<0> BIST_ADDR<3> BIST_ADDR<2> ++ BIST_ADDR<1> BIST_ADDR<0> BIST_EN_I VDD VSS +XI1<7> PADR<0> PADR<1> PADR<2> addr_n<7> VDD VSS / RSC_IHPSG13_NAND3X2 +XI1<6> NADR<0> PADR<1> PADR<2> addr_n<6> VDD VSS / RSC_IHPSG13_NAND3X2 +XI1<5> PADR<0> NADR<1> PADR<2> addr_n<5> VDD VSS / RSC_IHPSG13_NAND3X2 +XI1<4> NADR<0> NADR<1> PADR<2> addr_n<4> VDD VSS / RSC_IHPSG13_NAND3X2 +XI1<3> PADR<0> PADR<1> NADR<2> addr_n<3> VDD VSS / RSC_IHPSG13_NAND3X2 +XI1<2> NADR<0> PADR<1> NADR<2> addr_n<2> VDD VSS / RSC_IHPSG13_NAND3X2 +XI1<1> PADR<0> NADR<1> NADR<2> addr_n<1> VDD VSS / RSC_IHPSG13_NAND3X2 +XI1<0> NADR<0> NADR<1> NADR<2> addr_n<0> VDD VSS / RSC_IHPSG13_NAND3X2 +XDFF<3> BIST_EN_I BIST_ADDR<3> ACLK_N ADDR<3> addr_int net12<0> VDD ++ VSS / RSC_IHPSG13_DFNQMX2IX1 +XDFF<2> BIST_EN_I BIST_ADDR<2> ACLK_N ADDR<2> padr_int<2> net12<1> VDD ++ VSS / RSC_IHPSG13_DFNQMX2IX1 +XDFF<1> BIST_EN_I BIST_ADDR<1> ACLK_N ADDR<1> padr_int<1> net12<2> VDD ++ VSS / RSC_IHPSG13_DFNQMX2IX1 +XDFF<0> BIST_EN_I BIST_ADDR<0> ACLK_N ADDR<0> padr_int<0> net12<3> VDD ++ VSS / RSC_IHPSG13_DFNQMX2IX1 +XI17<4> VDD VSS / RSC_IHPSG13_FILLCAP4 +XI17<3> VDD VSS / RSC_IHPSG13_FILLCAP4 +XI17<2> VDD VSS / RSC_IHPSG13_FILLCAP4 +XI17<1> VDD VSS / RSC_IHPSG13_FILLCAP4 +XI13<2> NADR<2> PADR<2> VDD VSS / RSC_IHPSG13_INVX2 +XI13<1> NADR<1> PADR<1> VDD VSS / RSC_IHPSG13_INVX2 +XI13<0> NADR<0> PADR<0> VDD VSS / RSC_IHPSG13_INVX2 +XI2<7> addr_n<7> ADDR_DEC<7> VDD VSS / RSC_IHPSG13_INVX2 +XI2<6> addr_n<6> ADDR_DEC<6> VDD VSS / RSC_IHPSG13_INVX2 +XI2<5> addr_n<5> ADDR_DEC<5> VDD VSS / RSC_IHPSG13_INVX2 +XI2<4> addr_n<4> ADDR_DEC<4> VDD VSS / RSC_IHPSG13_INVX2 +XI2<3> addr_n<3> ADDR_DEC<3> VDD VSS / RSC_IHPSG13_INVX2 +XI2<2> addr_n<2> ADDR_DEC<2> VDD VSS / RSC_IHPSG13_INVX2 +XI2<1> addr_n<1> ADDR_DEC<1> VDD VSS / RSC_IHPSG13_INVX2 +XI2<0> addr_n<0> ADDR_DEC<0> VDD VSS / RSC_IHPSG13_INVX2 +XI3<2> padr_int<2> NADR<2> VDD VSS / RSC_IHPSG13_INVX2 +XI3<1> padr_int<1> NADR<1> VDD VSS / RSC_IHPSG13_INVX2 +XI3<0> padr_int<0> NADR<0> VDD VSS / RSC_IHPSG13_INVX2 +XI14 addr_int ADDR_COL<0> VDD VSS / RSC_IHPSG13_CBUFX2 +XI16<8> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI16<7> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI16<6> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI16<5> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI16<4> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI16<3> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI16<2> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI16<1> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI15 ADDR_COL<1> VDD VSS / RSC_IHPSG13_TIEL +.ENDS +.SUBCKT RM_IHPSG13_512x32_c2_2P_COLCTRL4 A_ADDR_COL A_ADDR_DEC<7> A_ADDR_DEC<6> ++ A_ADDR_DEC<5> A_ADDR_DEC<4> A_ADDR_DEC<3> A_ADDR_DEC<2> A_ADDR_DEC<1> ++ A_ADDR_DEC<0> A_BIST_BM_I A_BIST_DW_I A_BIST_EN_I A_BLC<15> A_BLC<14> ++ A_BLC<13> A_BLC<12> A_BLC<11> A_BLC<10> A_BLC<9> A_BLC<8> A_BLC<7> A_BLC<6> ++ A_BLC<5> A_BLC<4> A_BLC<3> A_BLC<2> A_BLC<1> A_BLC<0> A_BLT<15> A_BLT<14> ++ A_BLT<13> A_BLT<12> A_BLT<11> A_BLT<10> A_BLT<9> A_BLT<8> A_BLT<7> A_BLT<6> ++ A_BLT<5> A_BLT<4> A_BLT<3> A_BLT<2> A_BLT<1> A_BLT<0> A_BM_I A_DCLK_B_L ++ A_DCLK_B_R A_DCLK_L A_DCLK_R A_DR_O A_DW_I A_RCLK_B_L A_RCLK_B_R A_RCLK_L ++ A_RCLK_R A_TIEH_O A_WCLK_B_L A_WCLK_B_R A_WCLK_L A_WCLK_R B_ADDR_COL ++ B_ADDR_DEC<7> B_ADDR_DEC<6> B_ADDR_DEC<5> B_ADDR_DEC<4> B_ADDR_DEC<3> ++ B_ADDR_DEC<2> B_ADDR_DEC<1> B_ADDR_DEC<0> B_BIST_BM_I B_BIST_DW_I ++ B_BIST_EN_I B_BLC<15> B_BLC<14> B_BLC<13> B_BLC<12> B_BLC<11> B_BLC<10> ++ B_BLC<9> B_BLC<8> B_BLC<7> B_BLC<6> B_BLC<5> B_BLC<4> B_BLC<3> B_BLC<2> ++ B_BLC<1> B_BLC<0> B_BLT<15> B_BLT<14> B_BLT<13> B_BLT<12> B_BLT<11> ++ B_BLT<10> B_BLT<9> B_BLT<8> B_BLT<7> B_BLT<6> B_BLT<5> B_BLT<4> B_BLT<3> ++ B_BLT<2> B_BLT<1> B_BLT<0> B_BM_I B_DCLK_B_L B_DCLK_B_R B_DCLK_L B_DCLK_R ++ B_DR_O B_DW_I B_RCLK_B_L B_RCLK_B_R B_RCLK_L B_RCLK_R B_TIEH_O B_WCLK_B_L ++ B_WCLK_B_R B_WCLK_L B_WCLK_R VDD VSS +XB_I80 B_RCLK_B_L B_WCLK_B_L net041 VDD VSS / RSC_IHPSG13_AND2X2 +XA_I80 A_RCLK_B_L A_WCLK_B_L net21 VDD VSS / RSC_IHPSG13_AND2X2 +XB_I76 B_DI_N B_DO_WRITE_P B_WR_ZERO VDD VSS / RSC_IHPSG13_AND2X4 +XB_I75 B_DI_R B_DO_WRITE_P B_WR_ONE VDD VSS / RSC_IHPSG13_AND2X4 +XA_I76 A_DI_N A_DO_WRITE_P A_WR_ZERO VDD VSS / RSC_IHPSG13_AND2X4 +XA_I75 A_DI_R A_DO_WRITE_P A_WR_ONE VDD VSS / RSC_IHPSG13_AND2X4 +XI_FILL4<26> VDD VSS / RSC_IHPSG13_FILLCAP4 +XI_FILL4<25> VDD VSS / RSC_IHPSG13_FILLCAP4 +XI_FILL4<24> VDD VSS / RSC_IHPSG13_FILLCAP4 +XI_FILL4<23> VDD VSS / RSC_IHPSG13_FILLCAP4 +XI_FILL4<22> VDD VSS / RSC_IHPSG13_FILLCAP4 +XI_FILL4<21> VDD VSS / RSC_IHPSG13_FILLCAP4 +XI_FILL4<20> VDD VSS / RSC_IHPSG13_FILLCAP4 +XI_FILL4<19> VDD VSS / RSC_IHPSG13_FILLCAP4 +XI_FILL4<18> VDD VSS / RSC_IHPSG13_FILLCAP4 +XI_FILL4<17> VDD VSS / RSC_IHPSG13_FILLCAP4 +XI_FILL4<16> VDD VSS / RSC_IHPSG13_FILLCAP4 +XI_FILL4<15> VDD VSS / RSC_IHPSG13_FILLCAP4 +XI_FILL4<14> VDD VSS / RSC_IHPSG13_FILLCAP4 +XI_FILL4<13> VDD VSS / RSC_IHPSG13_FILLCAP4 +XI_FILL4<12> VDD VSS / RSC_IHPSG13_FILLCAP4 +XI_FILL4<11> VDD VSS / RSC_IHPSG13_FILLCAP4 +XI_FILL4<10> VDD VSS / RSC_IHPSG13_FILLCAP4 +XI_FILL4<9> VDD VSS / RSC_IHPSG13_FILLCAP4 +XI_FILL4<8> VDD VSS / RSC_IHPSG13_FILLCAP4 +XI_FILL4<7> VDD VSS / RSC_IHPSG13_FILLCAP4 +XI_FILL4<6> VDD VSS / RSC_IHPSG13_FILLCAP4 +XI_FILL4<5> VDD VSS / RSC_IHPSG13_FILLCAP4 +XI_FILL4<4> VDD VSS / RSC_IHPSG13_FILLCAP4 +XI_FILL4<3> VDD VSS / RSC_IHPSG13_FILLCAP4 +XI_FILL4<2> VDD VSS / RSC_IHPSG13_FILLCAP4 +XI_FILL4<1> VDD VSS / RSC_IHPSG13_FILLCAP4 +XB_I69 B_DCLK_L B_DCLK_B_L VDD VSS / RSC_IHPSG13_CINVX4 +XB_I50 B_WCLK_L B_WCLK_B_L VDD VSS / RSC_IHPSG13_CINVX4 +XB_EBUF B_RCLK_L B_RCLK_B_L VDD VSS / RSC_IHPSG13_CINVX4 +XB_INV<1> B_N0 B_P0 VDD VSS / RSC_IHPSG13_CINVX4 +XB_INV<0> B_ADDR_COL B_N0 VDD VSS / RSC_IHPSG13_CINVX4 +XA_I69 A_DCLK_L A_DCLK_B_L VDD VSS / RSC_IHPSG13_CINVX4 +XA_I50 A_WCLK_L A_WCLK_B_L VDD VSS / RSC_IHPSG13_CINVX4 +XA_EBUF A_RCLK_L A_RCLK_B_L VDD VSS / RSC_IHPSG13_CINVX4 +XA_INV<1> A_N0 A_P0 VDD VSS / RSC_IHPSG13_CINVX4 +XA_INV<0> A_ADDR_COL A_N0 VDD VSS / RSC_IHPSG13_CINVX4 +XB_I81<1> net041 B_PRE_N VDD VSS / RSC_IHPSG13_CINVX4_WN +XB_I81<0> net041 B_PRE_N VDD VSS / RSC_IHPSG13_CINVX4_WN +XA_I81<1> net21 A_PRE_N VDD VSS / RSC_IHPSG13_CINVX4_WN +XA_I81<0> net21 A_PRE_N VDD VSS / RSC_IHPSG13_CINVX4_WN +XA_R2 A_RCLK_L A_RCLK_R / RSC_IHPSG13_MET3RES +XA_I87 A_WCLK_L A_WCLK_R / RSC_IHPSG13_MET3RES +XA_I88 A_DCLK_L A_DCLK_R / RSC_IHPSG13_MET3RES +XA_I89 A_DCLK_B_L A_DCLK_B_R / RSC_IHPSG13_MET3RES +XA_I90 A_WCLK_B_L A_WCLK_B_R / RSC_IHPSG13_MET3RES +XA_I91 A_RCLK_B_L A_RCLK_B_R / RSC_IHPSG13_MET3RES +XB_R2 B_RCLK_L B_RCLK_R / RSC_IHPSG13_MET3RES +XB_I87 B_WCLK_L B_WCLK_R / RSC_IHPSG13_MET3RES +XB_I88 B_DCLK_L B_DCLK_R / RSC_IHPSG13_MET3RES +XB_I89 B_DCLK_B_L B_DCLK_B_R / RSC_IHPSG13_MET3RES +XB_I90 B_WCLK_B_L B_WCLK_B_R / RSC_IHPSG13_MET3RES +XB_I91 B_RCLK_B_L B_RCLK_B_R / RSC_IHPSG13_MET3RES +XA_ISENSE A_SAE A_BLC_SEL A_BLT_SEL net19 net20 VDD VSS / ++ RSC_IHPSG13_DFPQD_MSAFFX2 +XB_ISENSE B_SAE B_BLC_SEL B_BLT_SEL net037 net038 VDD VSS / ++ RSC_IHPSG13_DFPQD_MSAFFX2 +XAB_BLMUX<3> A_BLC<15> A_BLC<14> A_BLC<13> A_BLC<12> A_BLC_SEL A_BLT<15> ++ A_BLT<14> A_BLT<13> A_BLT<12> A_BLT_SEL A_PRE_N A_SEL_P<15> A_SEL_P<14> ++ A_SEL_P<13> A_SEL_P<12> A_WR_ONE A_WR_ZERO B_BLC<15> B_BLC<14> B_BLC<13> ++ B_BLC<12> B_BLC_SEL B_BLT<15> B_BLT<14> B_BLT<13> B_BLT<12> B_BLT_SEL ++ B_PRE_N B_SEL_P<15> B_SEL_P<14> B_SEL_P<13> B_SEL_P<12> B_WR_ONE B_WR_ZERO ++ VDD VSS / RM_IHPSG13_512x32_c2_2P_BLDRV +XAB_BLMUX<2> A_BLC<11> A_BLC<10> A_BLC<9> A_BLC<8> A_BLC_SEL A_BLT<11> ++ A_BLT<10> A_BLT<9> A_BLT<8> A_BLT_SEL A_PRE_N A_SEL_P<11> A_SEL_P<10> ++ A_SEL_P<9> A_SEL_P<8> A_WR_ONE A_WR_ZERO B_BLC<11> B_BLC<10> B_BLC<9> ++ B_BLC<8> B_BLC_SEL B_BLT<11> B_BLT<10> B_BLT<9> B_BLT<8> B_BLT_SEL B_PRE_N ++ B_SEL_P<11> B_SEL_P<10> B_SEL_P<9> B_SEL_P<8> B_WR_ONE B_WR_ZERO VDD ++ VSS / RM_IHPSG13_512x32_c2_2P_BLDRV +XAB_BLMUX<1> A_BLC<7> A_BLC<6> A_BLC<5> A_BLC<4> A_BLC_SEL A_BLT<7> A_BLT<6> ++ A_BLT<5> A_BLT<4> A_BLT_SEL A_PRE_N A_SEL_P<7> A_SEL_P<6> A_SEL_P<5> ++ A_SEL_P<4> A_WR_ONE A_WR_ZERO B_BLC<7> B_BLC<6> B_BLC<5> B_BLC<4> B_BLC_SEL ++ B_BLT<7> B_BLT<6> B_BLT<5> B_BLT<4> B_BLT_SEL B_PRE_N B_SEL_P<7> B_SEL_P<6> ++ B_SEL_P<5> B_SEL_P<4> B_WR_ONE B_WR_ZERO VDD VSS / ++ RM_IHPSG13_512x32_c2_2P_BLDRV +XAB_BLMUX<0> A_BLC<3> A_BLC<2> A_BLC<1> A_BLC<0> A_BLC_SEL A_BLT<3> A_BLT<2> ++ A_BLT<1> A_BLT<0> A_BLT_SEL A_PRE_N A_SEL_P<3> A_SEL_P<2> A_SEL_P<1> ++ A_SEL_P<0> A_WR_ONE A_WR_ZERO B_BLC<3> B_BLC<2> B_BLC<1> B_BLC<0> B_BLC_SEL ++ B_BLT<3> B_BLT<2> B_BLT<1> B_BLT<0> B_BLT_SEL B_PRE_N B_SEL_P<3> B_SEL_P<2> ++ B_SEL_P<1> B_SEL_P<0> B_WR_ONE B_WR_ZERO VDD VSS / ++ RM_IHPSG13_512x32_c2_2P_BLDRV +XA_I51 net19 A_DR_O VDD VSS / RSC_IHPSG13_INVX4 +XB_I51 net037 B_DR_O VDD VSS / RSC_IHPSG13_INVX4 +XA_I78 A_RCLK_B_L A_SAE VDD VSS / RSC_IHPSG13_CBUFX2 +XB_I78 B_RCLK_B_L B_SAE VDD VSS / RSC_IHPSG13_CBUFX2 +XA_DREG A_BIST_EN_I A_BIST_DW_I A_DCLK_B_L A_DW_I A_DI_R net22 VDD VSS ++ / RSC_IHPSG13_DFNQMX2IX1 +XB_DREG B_BIST_EN_I B_BIST_DW_I B_DCLK_B_L B_DW_I B_DI_R net046 VDD ++ VSS / RSC_IHPSG13_DFNQMX2IX1 +XB_BREG B_BIST_EN_I B_BIST_BM_I B_DCLK_B_L B_BM_I B_BM_R net045 VDD ++ VSS / RSC_IHPSG13_DFNQMX2IX1 +XA_BREG A_BIST_EN_I A_BIST_BM_I A_DCLK_B_L A_BM_I A_BM_R net24 VDD VSS ++ / RSC_IHPSG13_DFNQMX2IX1 +XA_DEC3INV<15> net23<0> A_SEL_P<15> VDD VSS / RSC_IHPSG13_INVX2 +XA_DEC3INV<14> net23<1> A_SEL_P<14> VDD VSS / RSC_IHPSG13_INVX2 +XA_DEC3INV<13> net23<2> A_SEL_P<13> VDD VSS / RSC_IHPSG13_INVX2 +XA_DEC3INV<12> net23<3> A_SEL_P<12> VDD VSS / RSC_IHPSG13_INVX2 +XA_DEC3INV<11> net23<4> A_SEL_P<11> VDD VSS / RSC_IHPSG13_INVX2 +XA_DEC3INV<10> net23<5> A_SEL_P<10> VDD VSS / RSC_IHPSG13_INVX2 +XA_DEC3INV<9> net23<6> A_SEL_P<9> VDD VSS / RSC_IHPSG13_INVX2 +XA_DEC3INV<8> net23<7> A_SEL_P<8> VDD VSS / RSC_IHPSG13_INVX2 +XA_DEC3INV<7> net23<8> A_SEL_P<7> VDD VSS / RSC_IHPSG13_INVX2 +XA_DEC3INV<6> net23<9> A_SEL_P<6> VDD VSS / RSC_IHPSG13_INVX2 +XA_DEC3INV<5> net23<10> A_SEL_P<5> VDD VSS / RSC_IHPSG13_INVX2 +XA_DEC3INV<4> net23<11> A_SEL_P<4> VDD VSS / RSC_IHPSG13_INVX2 +XA_DEC3INV<3> net23<12> A_SEL_P<3> VDD VSS / RSC_IHPSG13_INVX2 +XA_DEC3INV<2> net23<13> A_SEL_P<2> VDD VSS / RSC_IHPSG13_INVX2 +XA_DEC3INV<1> net23<14> A_SEL_P<1> VDD VSS / RSC_IHPSG13_INVX2 +XA_DEC3INV<0> net23<15> A_SEL_P<0> VDD VSS / RSC_IHPSG13_INVX2 +XA_I83 A_BM_R A_BM_N VDD VSS / RSC_IHPSG13_INVX2 +XA_I49 A_DI_R A_DI_N VDD VSS / RSC_IHPSG13_INVX2 +XB_DEC3INV<15> net044<0> B_SEL_P<15> VDD VSS / RSC_IHPSG13_INVX2 +XB_DEC3INV<14> net044<1> B_SEL_P<14> VDD VSS / RSC_IHPSG13_INVX2 +XB_DEC3INV<13> net044<2> B_SEL_P<13> VDD VSS / RSC_IHPSG13_INVX2 +XB_DEC3INV<12> net044<3> B_SEL_P<12> VDD VSS / RSC_IHPSG13_INVX2 +XB_DEC3INV<11> net044<4> B_SEL_P<11> VDD VSS / RSC_IHPSG13_INVX2 +XB_DEC3INV<10> net044<5> B_SEL_P<10> VDD VSS / RSC_IHPSG13_INVX2 +XB_DEC3INV<9> net044<6> B_SEL_P<9> VDD VSS / RSC_IHPSG13_INVX2 +XB_DEC3INV<8> net044<7> B_SEL_P<8> VDD VSS / RSC_IHPSG13_INVX2 +XB_DEC3INV<7> net044<8> B_SEL_P<7> VDD VSS / RSC_IHPSG13_INVX2 +XB_DEC3INV<6> net044<9> B_SEL_P<6> VDD VSS / RSC_IHPSG13_INVX2 +XB_DEC3INV<5> net044<10> B_SEL_P<5> VDD VSS / RSC_IHPSG13_INVX2 +XB_DEC3INV<4> net044<11> B_SEL_P<4> VDD VSS / RSC_IHPSG13_INVX2 +XB_DEC3INV<3> net044<12> B_SEL_P<3> VDD VSS / RSC_IHPSG13_INVX2 +XB_DEC3INV<2> net044<13> B_SEL_P<2> VDD VSS / RSC_IHPSG13_INVX2 +XB_DEC3INV<1> net044<14> B_SEL_P<1> VDD VSS / RSC_IHPSG13_INVX2 +XB_DEC3INV<0> net044<15> B_SEL_P<0> VDD VSS / RSC_IHPSG13_INVX2 +XB_I83 B_BM_R B_BM_N VDD VSS / RSC_IHPSG13_INVX2 +XB_I49 B_DI_R B_DI_N VDD VSS / RSC_IHPSG13_INVX2 +XI_FILL8<20> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI_FILL8<19> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI_FILL8<18> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI_FILL8<17> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI_FILL8<16> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI_FILL8<15> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI_FILL8<14> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI_FILL8<13> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI_FILL8<12> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI_FILL8<11> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI_FILL8<10> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI_FILL8<9> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI_FILL8<8> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI_FILL8<7> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI_FILL8<6> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI_FILL8<5> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI_FILL8<4> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI_FILL8<3> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI_FILL8<2> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI_FILL8<1> VDD VSS / RSC_IHPSG13_FILLCAP8 +XA_I44 A_BM_N A_WCLK_B_L A_DO_WRITE_P VDD VSS / RSC_IHPSG13_NOR2X2 +XB_I44 B_BM_N B_WCLK_B_L B_DO_WRITE_P VDD VSS / RSC_IHPSG13_NOR2X2 +XA_DEC3<15> A_P0 A_ADDR_DEC<7> net23<0> VDD VSS / RSC_IHPSG13_NAND2X2 +XA_DEC3<14> A_P0 A_ADDR_DEC<6> net23<1> VDD VSS / RSC_IHPSG13_NAND2X2 +XA_DEC3<13> A_P0 A_ADDR_DEC<5> net23<2> VDD VSS / RSC_IHPSG13_NAND2X2 +XA_DEC3<12> A_P0 A_ADDR_DEC<4> net23<3> VDD VSS / RSC_IHPSG13_NAND2X2 +XA_DEC3<11> A_P0 A_ADDR_DEC<3> net23<4> VDD VSS / RSC_IHPSG13_NAND2X2 +XA_DEC3<10> A_P0 A_ADDR_DEC<2> net23<5> VDD VSS / RSC_IHPSG13_NAND2X2 +XA_DEC3<9> A_P0 A_ADDR_DEC<1> net23<6> VDD VSS / RSC_IHPSG13_NAND2X2 +XA_DEC3<8> A_P0 A_ADDR_DEC<0> net23<7> VDD VSS / RSC_IHPSG13_NAND2X2 +XA_DEC3<7> A_N0 A_ADDR_DEC<7> net23<8> VDD VSS / RSC_IHPSG13_NAND2X2 +XA_DEC3<6> A_N0 A_ADDR_DEC<6> net23<9> VDD VSS / RSC_IHPSG13_NAND2X2 +XA_DEC3<5> A_N0 A_ADDR_DEC<5> net23<10> VDD VSS / RSC_IHPSG13_NAND2X2 +XA_DEC3<4> A_N0 A_ADDR_DEC<4> net23<11> VDD VSS / RSC_IHPSG13_NAND2X2 +XA_DEC3<3> A_N0 A_ADDR_DEC<3> net23<12> VDD VSS / RSC_IHPSG13_NAND2X2 +XA_DEC3<2> A_N0 A_ADDR_DEC<2> net23<13> VDD VSS / RSC_IHPSG13_NAND2X2 +XA_DEC3<1> A_N0 A_ADDR_DEC<1> net23<14> VDD VSS / RSC_IHPSG13_NAND2X2 +XA_DEC3<0> A_N0 A_ADDR_DEC<0> net23<15> VDD VSS / RSC_IHPSG13_NAND2X2 +XB_DEC3<15> B_P0 B_ADDR_DEC<7> net044<0> VDD VSS / RSC_IHPSG13_NAND2X2 +XB_DEC3<14> B_P0 B_ADDR_DEC<6> net044<1> VDD VSS / RSC_IHPSG13_NAND2X2 +XB_DEC3<13> B_P0 B_ADDR_DEC<5> net044<2> VDD VSS / RSC_IHPSG13_NAND2X2 +XB_DEC3<12> B_P0 B_ADDR_DEC<4> net044<3> VDD VSS / RSC_IHPSG13_NAND2X2 +XB_DEC3<11> B_P0 B_ADDR_DEC<3> net044<4> VDD VSS / RSC_IHPSG13_NAND2X2 +XB_DEC3<10> B_P0 B_ADDR_DEC<2> net044<5> VDD VSS / RSC_IHPSG13_NAND2X2 +XB_DEC3<9> B_P0 B_ADDR_DEC<1> net044<6> VDD VSS / RSC_IHPSG13_NAND2X2 +XB_DEC3<8> B_P0 B_ADDR_DEC<0> net044<7> VDD VSS / RSC_IHPSG13_NAND2X2 +XB_DEC3<7> B_N0 B_ADDR_DEC<7> net044<8> VDD VSS / RSC_IHPSG13_NAND2X2 +XB_DEC3<6> B_N0 B_ADDR_DEC<6> net044<9> VDD VSS / RSC_IHPSG13_NAND2X2 +XB_DEC3<5> B_N0 B_ADDR_DEC<5> net044<10> VDD VSS / RSC_IHPSG13_NAND2X2 +XB_DEC3<4> B_N0 B_ADDR_DEC<4> net044<11> VDD VSS / RSC_IHPSG13_NAND2X2 +XB_DEC3<3> B_N0 B_ADDR_DEC<3> net044<12> VDD VSS / RSC_IHPSG13_NAND2X2 +XB_DEC3<2> B_N0 B_ADDR_DEC<2> net044<13> VDD VSS / RSC_IHPSG13_NAND2X2 +XB_DEC3<1> B_N0 B_ADDR_DEC<1> net044<14> VDD VSS / RSC_IHPSG13_NAND2X2 +XB_DEC3<0> B_N0 B_ADDR_DEC<0> net044<15> VDD VSS / RSC_IHPSG13_NAND2X2 +XB_BM_TIEH B_TIEH_O VDD VSS / RSC_IHPSG13_TIEH +XA_BM_TIEH A_TIEH_O VDD VSS / RSC_IHPSG13_TIEH +.ENDS + + +.SUBCKT RM_IHPSG13_512x32_c2_2P_ROWDEC5 ADDR_N_I<4> ADDR_N_I<3> ADDR_N_I<2> ADDR_N_I<1> ++ ADDR_N_I<0> CS_I ECLK_I WL_O<31> WL_O<30> WL_O<29> WL_O<28> WL_O<27> ++ WL_O<26> WL_O<25> WL_O<24> WL_O<23> WL_O<22> WL_O<21> WL_O<20> WL_O<19> ++ WL_O<18> WL_O<17> WL_O<16> WL_O<15> WL_O<14> WL_O<13> WL_O<12> WL_O<11> ++ WL_O<10> WL_O<9> WL_O<8> WL_O<7> WL_O<6> WL_O<5> WL_O<4> WL_O<3> WL_O<2> ++ WL_O<1> WL_O<0> VDD VSS +XDEC00 ADDR_N_I<5> ADDR_N_I<4> CS_I CS00<0> VDD VSS / ++ RM_IHPSG13_512x32_c2_2P_DEC00 +XSEL<1> ADDR_N_I<3> ADDR_N_I<2> ADDR_N_I<1> ADDR_N_I<0> CS00<1> ECLK_H<1> ++ ECLK_H<2> ECLK_B<1> ECLK_B<2> WL_O<31> WL_O<30> WL_O<29> WL_O<28> WL_O<27> ++ WL_O<26> WL_O<25> WL_O<24> WL_O<23> WL_O<22> WL_O<21> WL_O<20> WL_O<19> ++ WL_O<18> WL_O<17> WL_O<16> VDD VSS / RM_IHPSG13_512x32_c2_2P_DEC04 +XSEL<0> ADDR_N_I<3> ADDR_N_I<2> ADDR_N_I<1> ADDR_N_I<0> CS00<0> ECLK_I ++ ECLK_H<1> ECLK_B<0> ECLK_B<1> WL_O<15> WL_O<14> WL_O<13> WL_O<12> WL_O<11> ++ WL_O<10> WL_O<9> WL_O<8> WL_O<7> WL_O<6> WL_O<5> WL_O<4> WL_O<3> WL_O<2> ++ WL_O<1> WL_O<0> VDD VSS / RM_IHPSG13_512x32_c2_2P_DEC04 +XDEC01 ADDR_N_I<5> ADDR_N_I<4> CS_I CS00<1> VDD VSS / ++ RM_IHPSG13_512x32_c2_2P_DEC01 +XL2<18> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<17> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<16> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<15> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<14> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<13> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<12> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<11> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<10> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<9> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<8> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<7> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<6> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<5> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<4> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<3> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<2> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<1> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI0 ADDR_N_I<5> VDD VSS / RSC_IHPSG13_TIEL +.ENDS +.SUBCKT RM_IHPSG13_512x32_c2_2P_ROWREG5 ACLK_N_I ADDR_I<4> ADDR_I<3> ADDR_I<2> ADDR_I<1> ++ ADDR_I<0> ADDR_N_O<4> ADDR_N_O<3> ADDR_N_O<2> ADDR_N_O<1> ADDR_N_O<0> ++ BIST_ADDR_I<4> BIST_ADDR_I<3> BIST_ADDR_I<2> BIST_ADDR_I<1> BIST_ADDR_I<0> ++ BIST_EN_I VDD VSS +XINV<4> q_int<4> qn_int<4> VDD VSS / RSC_IHPSG13_CINVX2 +XINV<3> q_int<3> qn_int<3> VDD VSS / RSC_IHPSG13_CINVX2 +XINV<2> q_int<2> qn_int<2> VDD VSS / RSC_IHPSG13_CINVX2 +XINV<1> q_int<1> qn_int<1> VDD VSS / RSC_IHPSG13_CINVX2 +XINV<0> q_int<0> qn_int<0> VDD VSS / RSC_IHPSG13_CINVX2 +XDRV<4> qn_int<4> ADDR_N_O<4> VDD VSS / RSC_IHPSG13_CINVX8 +XDRV<3> qn_int<3> ADDR_N_O<3> VDD VSS / RSC_IHPSG13_CINVX8 +XDRV<2> qn_int<2> ADDR_N_O<2> VDD VSS / RSC_IHPSG13_CINVX8 +XDRV<1> qn_int<1> ADDR_N_O<1> VDD VSS / RSC_IHPSG13_CINVX8 +XDRV<0> qn_int<0> ADDR_N_O<0> VDD VSS / RSC_IHPSG13_CINVX8 +XDFF<4> BIST_EN_I BIST_ADDR_I<4> ACLK_N_I ADDR_I<4> q_int<4> net2<0> VDD ++ VSS / RSC_IHPSG13_DFNQMX2IX1 +XDFF<3> BIST_EN_I BIST_ADDR_I<3> ACLK_N_I ADDR_I<3> q_int<3> net2<1> VDD ++ VSS / RSC_IHPSG13_DFNQMX2IX1 +XDFF<2> BIST_EN_I BIST_ADDR_I<2> ACLK_N_I ADDR_I<2> q_int<2> net2<2> VDD ++ VSS / RSC_IHPSG13_DFNQMX2IX1 +XDFF<1> BIST_EN_I BIST_ADDR_I<1> ACLK_N_I ADDR_I<1> q_int<1> net2<3> VDD ++ VSS / RSC_IHPSG13_DFNQMX2IX1 +XDFF<0> BIST_EN_I BIST_ADDR_I<0> ACLK_N_I ADDR_I<0> q_int<0> net2<4> VDD ++ VSS / RSC_IHPSG13_DFNQMX2IX1 +XI11<16> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI11<15> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI11<14> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI11<13> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI11<12> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI11<11> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI11<10> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI11<9> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI11<8> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI11<7> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI11<6> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI11<5> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI11<4> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI11<3> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI11<2> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI11<1> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI12<3> VDD VSS / RSC_IHPSG13_FILLCAP4 +XI12<2> VDD VSS / RSC_IHPSG13_FILLCAP4 +XI12<1> VDD VSS / RSC_IHPSG13_FILLCAP4 +XI12<0> VDD VSS / RSC_IHPSG13_FILLCAP4 +.ENDS + + +.SUBCKT RM_IHPSG13_512x32_c2_2P_COLDEC3 ACLK_N ADDR<2> ADDR<1> ADDR<0> ADDR_COL<1> ++ ADDR_COL<0> ADDR_DEC<7> ADDR_DEC<6> ADDR_DEC<5> ADDR_DEC<4> ADDR_DEC<3> ++ ADDR_DEC<2> ADDR_DEC<1> ADDR_DEC<0> BIST_ADDR<2> BIST_ADDR<1> BIST_ADDR<0> ++ BIST_EN_I VDD VSS +XI1<7> PADR<0> PADR<1> PADR<2> addr_n<7> VDD VSS / RSC_IHPSG13_NAND3X2 +XI1<6> NADR<0> PADR<1> PADR<2> addr_n<6> VDD VSS / RSC_IHPSG13_NAND3X2 +XI1<5> PADR<0> NADR<1> PADR<2> addr_n<5> VDD VSS / RSC_IHPSG13_NAND3X2 +XI1<4> NADR<0> NADR<1> PADR<2> addr_n<4> VDD VSS / RSC_IHPSG13_NAND3X2 +XI1<3> PADR<0> PADR<1> NADR<2> addr_n<3> VDD VSS / RSC_IHPSG13_NAND3X2 +XI1<2> NADR<0> PADR<1> NADR<2> addr_n<2> VDD VSS / RSC_IHPSG13_NAND3X2 +XI1<1> PADR<0> NADR<1> NADR<2> addr_n<1> VDD VSS / RSC_IHPSG13_NAND3X2 +XI1<0> NADR<0> NADR<1> NADR<2> addr_n<0> VDD VSS / RSC_IHPSG13_NAND3X2 +XDFF<2> BIST_EN_I BIST_ADDR<2> ACLK_N ADDR<2> padr_int<2> net13<0> VDD ++ VSS / RSC_IHPSG13_DFNQMX2IX1 +XDFF<1> BIST_EN_I BIST_ADDR<1> ACLK_N ADDR<1> padr_int<1> net13<1> VDD ++ VSS / RSC_IHPSG13_DFNQMX2IX1 +XDFF<0> BIST_EN_I BIST_ADDR<0> ACLK_N ADDR<0> padr_int<0> net13<2> VDD ++ VSS / RSC_IHPSG13_DFNQMX2IX1 +XI15<1> ADDR_COL<1> VDD VSS / RSC_IHPSG13_TIEL +XI15<0> ADDR_COL<0> VDD VSS / RSC_IHPSG13_TIEL +XI13<2> NADR<2> PADR<2> VDD VSS / RSC_IHPSG13_INVX2 +XI13<1> NADR<1> PADR<1> VDD VSS / RSC_IHPSG13_INVX2 +XI13<0> NADR<0> PADR<0> VDD VSS / RSC_IHPSG13_INVX2 +XI3<2> padr_int<2> NADR<2> VDD VSS / RSC_IHPSG13_INVX2 +XI3<1> padr_int<1> NADR<1> VDD VSS / RSC_IHPSG13_INVX2 +XI3<0> padr_int<0> NADR<0> VDD VSS / RSC_IHPSG13_INVX2 +XI2<7> addr_n<7> ADDR_DEC<7> VDD VSS / RSC_IHPSG13_INVX2 +XI2<6> addr_n<6> ADDR_DEC<6> VDD VSS / RSC_IHPSG13_INVX2 +XI2<5> addr_n<5> ADDR_DEC<5> VDD VSS / RSC_IHPSG13_INVX2 +XI2<4> addr_n<4> ADDR_DEC<4> VDD VSS / RSC_IHPSG13_INVX2 +XI2<3> addr_n<3> ADDR_DEC<3> VDD VSS / RSC_IHPSG13_INVX2 +XI2<2> addr_n<2> ADDR_DEC<2> VDD VSS / RSC_IHPSG13_INVX2 +XI2<1> addr_n<1> ADDR_DEC<1> VDD VSS / RSC_IHPSG13_INVX2 +XI2<0> addr_n<0> ADDR_DEC<0> VDD VSS / RSC_IHPSG13_INVX2 +XI17<4> VDD VSS / RSC_IHPSG13_FILLCAP4 +XI17<3> VDD VSS / RSC_IHPSG13_FILLCAP4 +XI17<2> VDD VSS / RSC_IHPSG13_FILLCAP4 +XI17<1> VDD VSS / RSC_IHPSG13_FILLCAP4 +XI16<11> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI16<10> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI16<9> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI16<8> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI16<7> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI16<6> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI16<5> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI16<4> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI16<3> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI16<2> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI16<1> VDD VSS / RSC_IHPSG13_FILLCAP8 +.ENDS +.SUBCKT RSC_IHPSG13_DFPQD_MSAFFX2P CP DN DP QN QP VDD VSS +XI_AMP CP DN DP QN QP VDD VSS / RSC_IHPSG13_DFPQD_MSAFFX2 +.ENDS +.SUBCKT RM_IHPSG13_512x32_c2_2P_COLCTRL3 A_ADDR_DEC<7> A_ADDR_DEC<6> A_ADDR_DEC<5> ++ A_ADDR_DEC<4> A_ADDR_DEC<3> A_ADDR_DEC<2> A_ADDR_DEC<1> A_ADDR_DEC<0> ++ A_BIST_BM_I A_BIST_DW_I A_BIST_EN_I A_BLC<7> A_BLC<6> A_BLC<5> A_BLC<4> ++ A_BLC<3> A_BLC<2> A_BLC<1> A_BLC<0> A_BLT<7> A_BLT<6> A_BLT<5> A_BLT<4> ++ A_BLT<3> A_BLT<2> A_BLT<1> A_BLT<0> A_BM_I A_DCLK_B_L A_DCLK_B_R A_DCLK_L ++ A_DCLK_R A_DR_O A_DW_I A_RCLK_B_L A_RCLK_B_R A_RCLK_L A_RCLK_R A_TIEH_O ++ A_WCLK_B_L A_WCLK_B_R A_WCLK_L A_WCLK_R B_ADDR_DEC<7> B_ADDR_DEC<6> ++ B_ADDR_DEC<5> B_ADDR_DEC<4> B_ADDR_DEC<3> B_ADDR_DEC<2> B_ADDR_DEC<1> ++ B_ADDR_DEC<0> B_BIST_BM_I B_BIST_DW_I B_BIST_EN_I B_BLC<7> B_BLC<6> B_BLC<5> ++ B_BLC<4> B_BLC<3> B_BLC<2> B_BLC<1> B_BLC<0> B_BLT<7> B_BLT<6> B_BLT<5> ++ B_BLT<4> B_BLT<3> B_BLT<2> B_BLT<1> B_BLT<0> B_BM_I B_DCLK_B_L B_DCLK_B_R ++ B_DCLK_L B_DCLK_R B_DR_O B_DW_I B_RCLK_B_L B_RCLK_B_R B_RCLK_L B_RCLK_R ++ B_TIEH_O B_WCLK_B_L B_WCLK_B_R B_WCLK_L B_WCLK_R VDD VSS +XB_DREG B_BIST_EN_I B_BIST_DW_I B_DCLK_B_L B_DW_I B_DI_R net044 VDD ++ VSS / RSC_IHPSG13_DFNQMX2IX1 +XB_BREG B_BIST_EN_I B_BIST_BM_I B_DCLK_B_L B_BM_I B_BM_R net043 VDD ++ VSS / RSC_IHPSG13_DFNQMX2IX1 +XA_DREG A_BIST_EN_I A_BIST_DW_I A_DCLK_B_L A_DW_I A_DI_R net22 VDD VSS ++ / RSC_IHPSG13_DFNQMX2IX1 +XA_BREG A_BIST_EN_I A_BIST_BM_I A_DCLK_B_L A_BM_I A_BM_R net23 VDD VSS ++ / RSC_IHPSG13_DFNQMX2IX1 +XI_FILL8<11> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI_FILL8<10> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI_FILL8<9> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI_FILL8<8> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI_FILL8<7> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI_FILL8<6> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI_FILL8<5> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI_FILL8<4> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI_FILL8<3> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI_FILL8<2> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI_FILL8<1> VDD VSS / RSC_IHPSG13_FILLCAP8 +XB_I51 net037 B_DR_O VDD VSS / RSC_IHPSG13_INVX4 +XA_I51 net19 A_DR_O VDD VSS / RSC_IHPSG13_INVX4 +XB_I44 B_BM_N B_WCLK_B_L B_DO_WRITE_P VDD VSS / RSC_IHPSG13_NOR2X2 +XA_I44 A_BM_N A_WCLK_B_L A_DO_WRITE_P VDD VSS / RSC_IHPSG13_NOR2X2 +XB_BM_TIEH B_TIEH_O VDD VSS / RSC_IHPSG13_TIEH +XA_BM_TIEH A_TIEH_O VDD VSS / RSC_IHPSG13_TIEH +XB_ISENSE B_SAE B_BLC_SEL B_BLT_SEL net037 net038 VDD VSS / ++ RSC_IHPSG13_DFPQD_MSAFFX2P +XA_ISENSE A_SAE A_BLC_SEL A_BLT_SEL net19 net20 VDD VSS / ++ RSC_IHPSG13_DFPQD_MSAFFX2P +XB_I49 B_DI_R B_DI_N VDD VSS / RSC_IHPSG13_INVX2 +XB_I83 B_BM_R B_BM_N VDD VSS / RSC_IHPSG13_INVX2 +XA_I49 A_DI_R A_DI_N VDD VSS / RSC_IHPSG13_INVX2 +XA_I83 A_BM_R A_BM_N VDD VSS / RSC_IHPSG13_INVX2 +XB_I69 B_DCLK_L B_DCLK_B_L VDD VSS / RSC_IHPSG13_CINVX2 +XB_I50 B_WCLK_L B_WCLK_B_L VDD VSS / RSC_IHPSG13_CINVX2 +XB_EBUF B_RCLK_L B_RCLK_B_L VDD VSS / RSC_IHPSG13_CINVX2 +XA_I69 A_DCLK_L A_DCLK_B_L VDD VSS / RSC_IHPSG13_CINVX2 +XA_I50 A_WCLK_L A_WCLK_B_L VDD VSS / RSC_IHPSG13_CINVX2 +XA_EBUF A_RCLK_L A_RCLK_B_L VDD VSS / RSC_IHPSG13_CINVX2 +XAB_BLMUX<1> A_BLC<7> A_BLC<6> A_BLC<5> A_BLC<4> A_BLC_SEL A_BLT<7> A_BLT<6> ++ A_BLT<5> A_BLT<4> A_BLT_SEL A_PRE_N A_ADDR_DEC<7> A_ADDR_DEC<6> ++ A_ADDR_DEC<5> A_ADDR_DEC<4> A_WR_ONE A_WR_ZERO B_BLC<7> B_BLC<6> B_BLC<5> ++ B_BLC<4> B_BLC_SEL B_BLT<7> B_BLT<6> B_BLT<5> B_BLT<4> B_BLT_SEL B_PRE_N ++ B_ADDR_DEC<7> B_ADDR_DEC<6> B_ADDR_DEC<5> B_ADDR_DEC<4> B_WR_ONE B_WR_ZERO ++ VDD VSS / RM_IHPSG13_512x32_c2_2P_BLDRV +XAB_BLMUX<0> A_BLC<3> A_BLC<2> A_BLC<1> A_BLC<0> A_BLC_SEL A_BLT<3> A_BLT<2> ++ A_BLT<1> A_BLT<0> A_BLT_SEL A_PRE_N A_ADDR_DEC<3> A_ADDR_DEC<2> ++ A_ADDR_DEC<1> A_ADDR_DEC<0> A_WR_ONE A_WR_ZERO B_BLC<3> B_BLC<2> B_BLC<1> ++ B_BLC<0> B_BLC_SEL B_BLT<3> B_BLT<2> B_BLT<1> B_BLT<0> B_BLT_SEL B_PRE_N ++ B_ADDR_DEC<3> B_ADDR_DEC<2> B_ADDR_DEC<1> B_ADDR_DEC<0> B_WR_ONE B_WR_ZERO ++ VDD VSS / RM_IHPSG13_512x32_c2_2P_BLDRV +XB_I78 B_RCLK_B_L B_SAE VDD VSS / RSC_IHPSG13_CBUFX2 +XA_I78 A_RCLK_B_L A_SAE VDD VSS / RSC_IHPSG13_CBUFX2 +XB_I88 B_DCLK_L B_DCLK_R / RSC_IHPSG13_MET3RES +XB_I87 B_WCLK_L B_WCLK_R / RSC_IHPSG13_MET3RES +XB_R2 B_RCLK_L B_RCLK_R / RSC_IHPSG13_MET3RES +XB_I91 B_RCLK_B_L B_RCLK_B_R / RSC_IHPSG13_MET3RES +XB_I90 B_WCLK_B_L B_WCLK_B_R / RSC_IHPSG13_MET3RES +XB_I89 B_DCLK_B_L B_DCLK_B_R / RSC_IHPSG13_MET3RES +XA_I88 A_DCLK_L A_DCLK_R / RSC_IHPSG13_MET3RES +XA_I87 A_WCLK_L A_WCLK_R / RSC_IHPSG13_MET3RES +XA_R2 A_RCLK_L A_RCLK_R / RSC_IHPSG13_MET3RES +XA_I91 A_RCLK_B_L A_RCLK_B_R / RSC_IHPSG13_MET3RES +XA_I90 A_WCLK_B_L A_WCLK_B_R / RSC_IHPSG13_MET3RES +XA_I89 A_DCLK_B_L A_DCLK_B_R / RSC_IHPSG13_MET3RES +XB_I80 B_WCLK_B_L B_RCLK_B_L net041 VDD VSS / RSC_IHPSG13_AND2X2 +XB_I76 B_DO_WRITE_P B_DI_N B_WR_ZERO VDD VSS / RSC_IHPSG13_AND2X2 +XB_I75 B_DO_WRITE_P B_DI_R B_WR_ONE VDD VSS / RSC_IHPSG13_AND2X2 +XA_I80 A_WCLK_B_L A_RCLK_B_L net21 VDD VSS / RSC_IHPSG13_AND2X2 +XA_I76 A_DI_N A_DO_WRITE_P A_WR_ZERO VDD VSS / RSC_IHPSG13_AND2X2 +XA_I75 A_DI_R A_DO_WRITE_P A_WR_ONE VDD VSS / RSC_IHPSG13_AND2X2 +XB_I81 net041 B_PRE_N VDD VSS / RSC_IHPSG13_CINVX4_WN +XA_I81 net21 A_PRE_N VDD VSS / RSC_IHPSG13_CINVX4_WN +XI_FILL4<10> VDD VSS / RSC_IHPSG13_FILLCAP4 +XI_FILL4<9> VDD VSS / RSC_IHPSG13_FILLCAP4 +XI_FILL4<8> VDD VSS / RSC_IHPSG13_FILLCAP4 +XI_FILL4<7> VDD VSS / RSC_IHPSG13_FILLCAP4 +XI_FILL4<6> VDD VSS / RSC_IHPSG13_FILLCAP4 +XI_FILL4<5> VDD VSS / RSC_IHPSG13_FILLCAP4 +XI_FILL4<4> VDD VSS / RSC_IHPSG13_FILLCAP4 +XI_FILL4<3> VDD VSS / RSC_IHPSG13_FILLCAP4 +XI_FILL4<2> VDD VSS / RSC_IHPSG13_FILLCAP4 +XI_FILL4<1> VDD VSS / RSC_IHPSG13_FILLCAP4 +.ENDS + +.SUBCKT RM_IHPSG13_512x32_c2_2P_ROWDEC6 ADDR_N_I<5> ADDR_N_I<4> ADDR_N_I<3> ADDR_N_I<2> ++ ADDR_N_I<1> ADDR_N_I<0> CS_I ECLK_I WL_O<63> WL_O<62> WL_O<61> WL_O<60> ++ WL_O<59> WL_O<58> WL_O<57> WL_O<56> WL_O<55> WL_O<54> WL_O<53> WL_O<52> ++ WL_O<51> WL_O<50> WL_O<49> WL_O<48> WL_O<47> WL_O<46> WL_O<45> WL_O<44> ++ WL_O<43> WL_O<42> WL_O<41> WL_O<40> WL_O<39> WL_O<38> WL_O<37> WL_O<36> ++ WL_O<35> WL_O<34> WL_O<33> WL_O<32> WL_O<31> WL_O<30> WL_O<29> WL_O<28> ++ WL_O<27> WL_O<26> WL_O<25> WL_O<24> WL_O<23> WL_O<22> WL_O<21> WL_O<20> ++ WL_O<19> WL_O<18> WL_O<17> WL_O<16> WL_O<15> WL_O<14> WL_O<13> WL_O<12> ++ WL_O<11> WL_O<10> WL_O<9> WL_O<8> WL_O<7> WL_O<6> WL_O<5> WL_O<4> WL_O<3> ++ WL_O<2> WL_O<1> WL_O<0> VDD VSS +XDEC10 ADDR_N_I<5> ADDR_N_I<4> CS_I CS00<2> VDD VSS / ++ RM_IHPSG13_512x32_c2_2P_DEC02 +XDEC00 ADDR_N_I<5> ADDR_N_I<4> CS_I CS00<0> VDD VSS / ++ RM_IHPSG13_512x32_c2_2P_DEC00 +XSEL<3> ADDR_N_I<3> ADDR_N_I<2> ADDR_N_I<1> ADDR_N_I<0> CS00<3> ECLK_H<3> ++ ECLK_H<4> ECLK_B<3> ECLK_B<4> WL_O<63> WL_O<62> WL_O<61> WL_O<60> WL_O<59> ++ WL_O<58> WL_O<57> WL_O<56> WL_O<55> WL_O<54> WL_O<53> WL_O<52> WL_O<51> ++ WL_O<50> WL_O<49> WL_O<48> VDD VSS / RM_IHPSG13_512x32_c2_2P_DEC04 +XSEL<2> ADDR_N_I<3> ADDR_N_I<2> ADDR_N_I<1> ADDR_N_I<0> CS00<2> ECLK_H<2> ++ ECLK_H<3> ECLK_B<2> ECLK_B<3> WL_O<47> WL_O<46> WL_O<45> WL_O<44> WL_O<43> ++ WL_O<42> WL_O<41> WL_O<40> WL_O<39> WL_O<38> WL_O<37> WL_O<36> WL_O<35> ++ WL_O<34> WL_O<33> WL_O<32> VDD VSS / RM_IHPSG13_512x32_c2_2P_DEC04 +XSEL<1> ADDR_N_I<3> ADDR_N_I<2> ADDR_N_I<1> ADDR_N_I<0> CS00<1> ECLK_H<1> ++ ECLK_H<2> ECLK_B<1> ECLK_B<2> WL_O<31> WL_O<30> WL_O<29> WL_O<28> WL_O<27> ++ WL_O<26> WL_O<25> WL_O<24> WL_O<23> WL_O<22> WL_O<21> WL_O<20> WL_O<19> ++ WL_O<18> WL_O<17> WL_O<16> VDD VSS / RM_IHPSG13_512x32_c2_2P_DEC04 +XSEL<0> ADDR_N_I<3> ADDR_N_I<2> ADDR_N_I<1> ADDR_N_I<0> CS00<0> ECLK_I ++ ECLK_H<1> ECLK_B<0> ECLK_B<1> WL_O<15> WL_O<14> WL_O<13> WL_O<12> WL_O<11> ++ WL_O<10> WL_O<9> WL_O<8> WL_O<7> WL_O<6> WL_O<5> WL_O<4> WL_O<3> WL_O<2> ++ WL_O<1> WL_O<0> VDD VSS / RM_IHPSG13_512x32_c2_2P_DEC04 +XDEC11 ADDR_N_I<5> ADDR_N_I<4> CS_I CS00<3> VDD VSS / ++ RM_IHPSG13_512x32_c2_2P_DEC03 +XL2<36> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<35> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<34> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<33> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<32> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<31> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<30> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<29> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<28> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<27> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<26> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<25> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<24> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<23> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<22> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<21> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<20> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<19> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<18> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<17> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<16> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<15> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<14> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<13> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<12> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<11> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<10> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<9> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<8> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<7> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<6> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<5> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<4> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<3> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<2> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<1> VDD VSS / RSC_IHPSG13_FILLCAP8 +XDEC01 ADDR_N_I<5> ADDR_N_I<4> CS_I CS00<1> VDD VSS / ++ RM_IHPSG13_512x32_c2_2P_DEC01 +.ENDS +.SUBCKT RM_IHPSG13_512x32_c2_2P_ROWREG6 ACLK_N_I ADDR_I<5> ADDR_I<4> ADDR_I<3> ADDR_I<2> ++ ADDR_I<1> ADDR_I<0> ADDR_N_O<5> ADDR_N_O<4> ADDR_N_O<3> ADDR_N_O<2> ++ ADDR_N_O<1> ADDR_N_O<0> BIST_ADDR_I<5> BIST_ADDR_I<4> BIST_ADDR_I<3> ++ BIST_ADDR_I<2> BIST_ADDR_I<1> BIST_ADDR_I<0> BIST_EN_I VDD VSS +XINV<5> q_int<5> qn_int<5> VDD VSS / RSC_IHPSG13_CINVX2 +XINV<4> q_int<4> qn_int<4> VDD VSS / RSC_IHPSG13_CINVX2 +XINV<3> q_int<3> qn_int<3> VDD VSS / RSC_IHPSG13_CINVX2 +XINV<2> q_int<2> qn_int<2> VDD VSS / RSC_IHPSG13_CINVX2 +XINV<1> q_int<1> qn_int<1> VDD VSS / RSC_IHPSG13_CINVX2 +XINV<0> q_int<0> qn_int<0> VDD VSS / RSC_IHPSG13_CINVX2 +XDRV<5> qn_int<5> ADDR_N_O<5> VDD VSS / RSC_IHPSG13_CINVX8 +XDRV<4> qn_int<4> ADDR_N_O<4> VDD VSS / RSC_IHPSG13_CINVX8 +XDRV<3> qn_int<3> ADDR_N_O<3> VDD VSS / RSC_IHPSG13_CINVX8 +XDRV<2> qn_int<2> ADDR_N_O<2> VDD VSS / RSC_IHPSG13_CINVX8 +XDRV<1> qn_int<1> ADDR_N_O<1> VDD VSS / RSC_IHPSG13_CINVX8 +XDRV<0> qn_int<0> ADDR_N_O<0> VDD VSS / RSC_IHPSG13_CINVX8 +XDFF<5> BIST_EN_I BIST_ADDR_I<5> ACLK_N_I ADDR_I<5> q_int<5> net2<0> VDD ++ VSS / RSC_IHPSG13_DFNQMX2IX1 +XDFF<4> BIST_EN_I BIST_ADDR_I<4> ACLK_N_I ADDR_I<4> q_int<4> net2<1> VDD ++ VSS / RSC_IHPSG13_DFNQMX2IX1 +XDFF<3> BIST_EN_I BIST_ADDR_I<3> ACLK_N_I ADDR_I<3> q_int<3> net2<2> VDD ++ VSS / RSC_IHPSG13_DFNQMX2IX1 +XDFF<2> BIST_EN_I BIST_ADDR_I<2> ACLK_N_I ADDR_I<2> q_int<2> net2<3> VDD ++ VSS / RSC_IHPSG13_DFNQMX2IX1 +XDFF<1> BIST_EN_I BIST_ADDR_I<1> ACLK_N_I ADDR_I<1> q_int<1> net2<4> VDD ++ VSS / RSC_IHPSG13_DFNQMX2IX1 +XDFF<0> BIST_EN_I BIST_ADDR_I<0> ACLK_N_I ADDR_I<0> q_int<0> net2<5> VDD ++ VSS / RSC_IHPSG13_DFNQMX2IX1 +XI11<12> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI11<11> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI11<10> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI11<9> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI11<8> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI11<7> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI11<6> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI11<5> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI11<4> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI11<3> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI11<2> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI11<1> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI12<2> VDD VSS / RSC_IHPSG13_FILLCAP4 +XI12<1> VDD VSS / RSC_IHPSG13_FILLCAP4 +XI12<0> VDD VSS / RSC_IHPSG13_FILLCAP4 +.ENDS + +.SUBCKT RM_IHPSG13_512x32_c2_2P_COLDRV13X16 ADDR_COL_I<1> ADDR_COL_I<0> ADDR_COL_O<1> ++ ADDR_COL_O<0> ADDR_DEC_I<7> ADDR_DEC_I<6> ADDR_DEC_I<5> ADDR_DEC_I<4> ++ ADDR_DEC_I<3> ADDR_DEC_I<2> ADDR_DEC_I<1> ADDR_DEC_I<0> ADDR_DEC_O<7> ++ ADDR_DEC_O<6> ADDR_DEC_O<5> ADDR_DEC_O<4> ADDR_DEC_O<3> ADDR_DEC_O<2> ++ ADDR_DEC_O<1> ADDR_DEC_O<0> DCLK_I DCLK_O RCLK_I RCLK_O WCLK_I WCLK_O ++ VDD VSS +XI0<7> VDD VSS / RSC_IHPSG13_FILLCAP4 +XI0<6> VDD VSS / RSC_IHPSG13_FILLCAP4 +XI0<5> VDD VSS / RSC_IHPSG13_FILLCAP4 +XI0<4> VDD VSS / RSC_IHPSG13_FILLCAP4 +XI0<3> VDD VSS / RSC_IHPSG13_FILLCAP4 +XI0<2> VDD VSS / RSC_IHPSG13_FILLCAP4 +XI0<1> VDD VSS / RSC_IHPSG13_FILLCAP4 +XWCLK_DRV WCLK_I WCLK_O VDD VSS / RSC_IHPSG13_CBUFX16 +XRCLK_DRV RCLK_I RCLK_O VDD VSS / RSC_IHPSG13_CBUFX16 +XDCLK_DRV DCLK_I DCLK_O VDD VSS / RSC_IHPSG13_CBUFX16 +XADDR_COL_DRV<1> ADDR_COL_I<1> ADDR_COL_O<1> VDD VSS / ++ RSC_IHPSG13_CBUFX16 +XADDR_COL_DRV<0> ADDR_COL_I<0> ADDR_COL_O<0> VDD VSS / ++ RSC_IHPSG13_CBUFX16 +XADDR_DEC_DRV<7> ADDR_DEC_I<7> ADDR_DEC_O<7> VDD VSS / ++ RSC_IHPSG13_CBUFX16 +XADDR_DEC_DRV<6> ADDR_DEC_I<6> ADDR_DEC_O<6> VDD VSS / ++ RSC_IHPSG13_CBUFX16 +XADDR_DEC_DRV<5> ADDR_DEC_I<5> ADDR_DEC_O<5> VDD VSS / ++ RSC_IHPSG13_CBUFX16 +XADDR_DEC_DRV<4> ADDR_DEC_I<4> ADDR_DEC_O<4> VDD VSS / ++ RSC_IHPSG13_CBUFX16 +XADDR_DEC_DRV<3> ADDR_DEC_I<3> ADDR_DEC_O<3> VDD VSS / ++ RSC_IHPSG13_CBUFX16 +XADDR_DEC_DRV<2> ADDR_DEC_I<2> ADDR_DEC_O<2> VDD VSS / ++ RSC_IHPSG13_CBUFX16 +XADDR_DEC_DRV<1> ADDR_DEC_I<1> ADDR_DEC_O<1> VDD VSS / ++ RSC_IHPSG13_CBUFX16 +XADDR_DEC_DRV<0> ADDR_DEC_I<0> ADDR_DEC_O<0> VDD VSS / ++ RSC_IHPSG13_CBUFX16 +XI1<5> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI1<4> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI1<3> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI1<2> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI1<1> VDD VSS / RSC_IHPSG13_FILLCAP8 +.ENDS +.SUBCKT RM_IHPSG13_512x32_c2_2P_WLDRV16X16 A<15> A<14> A<13> A<12> A<11> A<10> A<9> A<8> ++ A<7> A<6> A<5> A<4> A<3> A<2> A<1> A<0> Z<15> Z<14> Z<13> Z<12> Z<11> Z<10> ++ Z<9> Z<8> Z<7> Z<6> Z<5> Z<4> Z<3> Z<2> Z<1> Z<0> VDD VSS +XBUF<15> A<15> Z<15> VDD VSS / RSC_IHPSG13_WLDRVX16 +XBUF<14> A<14> Z<14> VDD VSS / RSC_IHPSG13_WLDRVX16 +XBUF<13> A<13> Z<13> VDD VSS / RSC_IHPSG13_WLDRVX16 +XBUF<12> A<12> Z<12> VDD VSS / RSC_IHPSG13_WLDRVX16 +XBUF<11> A<11> Z<11> VDD VSS / RSC_IHPSG13_WLDRVX16 +XBUF<10> A<10> Z<10> VDD VSS / RSC_IHPSG13_WLDRVX16 +XBUF<9> A<9> Z<9> VDD VSS / RSC_IHPSG13_WLDRVX16 +XBUF<8> A<8> Z<8> VDD VSS / RSC_IHPSG13_WLDRVX16 +XBUF<7> A<7> Z<7> VDD VSS / RSC_IHPSG13_WLDRVX16 +XBUF<6> A<6> Z<6> VDD VSS / RSC_IHPSG13_WLDRVX16 +XBUF<5> A<5> Z<5> VDD VSS / RSC_IHPSG13_WLDRVX16 +XBUF<4> A<4> Z<4> VDD VSS / RSC_IHPSG13_WLDRVX16 +XBUF<3> A<3> Z<3> VDD VSS / RSC_IHPSG13_WLDRVX16 +XBUF<2> A<2> Z<2> VDD VSS / RSC_IHPSG13_WLDRVX16 +XBUF<1> A<1> Z<1> VDD VSS / RSC_IHPSG13_WLDRVX16 +XBUF<0> A<0> Z<0> VDD VSS / RSC_IHPSG13_WLDRVX16 +.ENDS + + +.SUBCKT RM_IHPSG13_512x32_c2_1P_DEC01 ADDR<1> ADDR<0> CS CS_OUT VDD VSS +XDECINV net1 CS_OUT VDD VSS / RSC_IHPSG13_INVX4 +XDEC NADDR<1> ADDR<0> CS net1 VDD VSS / RSC_IHPSG13_NAND3X2 +XI2 VDD VSS / RSC_IHPSG13_FILLCAP4 +XADDRINV ADDR<1> NADDR<1> VDD VSS / RSC_IHPSG13_INVX2 +.ENDS +.SUBCKT RM_IHPSG13_512x32_c2_1P_DEC00 ADDR<1> ADDR<0> CS CS_OUT VDD VSS +XDECINV net1 CS_OUT VDD VSS / RSC_IHPSG13_INVX4 +XDEC NADDR<1> NADDR<0> CS net1 VDD VSS / RSC_IHPSG13_NAND3X2 +XADDRINV<1> ADDR<1> NADDR<1> VDD VSS / RSC_IHPSG13_INVX2 +XADDRINV<0> ADDR<0> NADDR<0> VDD VSS / RSC_IHPSG13_INVX2 +XI1 VDD VSS / RSC_IHPSG13_FILLCAP4 +.ENDS +.SUBCKT RM_IHPSG13_512x32_c2_1P_ROWDEC5 ADDR_N_I<4> ADDR_N_I<3> ADDR_N_I<2> ADDR_N_I<1> ++ ADDR_N_I<0> CS_I ECLK_I WL_O<31> WL_O<30> WL_O<29> WL_O<28> WL_O<27> ++ WL_O<26> WL_O<25> WL_O<24> WL_O<23> WL_O<22> WL_O<21> WL_O<20> WL_O<19> ++ WL_O<18> WL_O<17> WL_O<16> WL_O<15> WL_O<14> WL_O<13> WL_O<12> WL_O<11> ++ WL_O<10> WL_O<9> WL_O<8> WL_O<7> WL_O<6> WL_O<5> WL_O<4> WL_O<3> WL_O<2> ++ WL_O<1> WL_O<0> VDD VSS +XL2<12> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<11> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<10> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<9> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<8> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<7> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<6> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<5> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<4> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<3> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<2> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<1> VDD VSS / RSC_IHPSG13_FILLCAP8 +XDEC01 ADDR_N_I<5> ADDR_N_I<4> CS_I CS00<1> VDD VSS / ++ RM_IHPSG13_512x32_c2_1P_DEC01 +XDEC00 ADDR_N_I<5> ADDR_N_I<4> CS_I CS00<0> VDD VSS / ++ RM_IHPSG13_512x32_c2_1P_DEC00 +XSEL<1> ADDR_N_I<3> ADDR_N_I<2> ADDR_N_I<1> ADDR_N_I<0> CS00<1> ECLK_H<1> ++ ECLK_H<2> ECLK_B<1> ECLK_B<2> WL_O<31> WL_O<30> WL_O<29> WL_O<28> WL_O<27> ++ WL_O<26> WL_O<25> WL_O<24> WL_O<23> WL_O<22> WL_O<21> WL_O<20> WL_O<19> ++ WL_O<18> WL_O<17> WL_O<16> VDD VSS / RM_IHPSG13_512x32_c2_1P_DEC04 +XSEL<0> ADDR_N_I<3> ADDR_N_I<2> ADDR_N_I<1> ADDR_N_I<0> CS00<0> ECLK_I ++ ECLK_H<1> ECLK_B<0> ECLK_B<1> WL_O<15> WL_O<14> WL_O<13> WL_O<12> WL_O<11> ++ WL_O<10> WL_O<9> WL_O<8> WL_O<7> WL_O<6> WL_O<5> WL_O<4> WL_O<3> WL_O<2> ++ WL_O<1> WL_O<0> VDD VSS / RM_IHPSG13_512x32_c2_1P_DEC04 +XI0 ADDR_N_I<5> VDD VSS / RSC_IHPSG13_TIEL +.ENDS +.SUBCKT RM_IHPSG13_512x32_c2_1P_ROWREG5 ACLK_N_I ADDR_I<4> ADDR_I<3> ADDR_I<2> ADDR_I<1> ++ ADDR_I<0> ADDR_N_O<4> ADDR_N_O<3> ADDR_N_O<2> ADDR_N_O<1> ADDR_N_O<0> ++ BIST_ADDR_I<4> BIST_ADDR_I<3> BIST_ADDR_I<2> BIST_ADDR_I<1> BIST_ADDR_I<0> ++ BIST_EN_I VDD VSS +XINV<4> q_int<4> qn_int<4> VDD VSS / RSC_IHPSG13_CINVX2 +XINV<3> q_int<3> qn_int<3> VDD VSS / RSC_IHPSG13_CINVX2 +XINV<2> q_int<2> qn_int<2> VDD VSS / RSC_IHPSG13_CINVX2 +XINV<1> q_int<1> qn_int<1> VDD VSS / RSC_IHPSG13_CINVX2 +XINV<0> q_int<0> qn_int<0> VDD VSS / RSC_IHPSG13_CINVX2 +XDRV<4> qn_int<4> ADDR_N_O<4> VDD VSS / RSC_IHPSG13_CINVX8 +XDRV<3> qn_int<3> ADDR_N_O<3> VDD VSS / RSC_IHPSG13_CINVX8 +XDRV<2> qn_int<2> ADDR_N_O<2> VDD VSS / RSC_IHPSG13_CINVX8 +XDRV<1> qn_int<1> ADDR_N_O<1> VDD VSS / RSC_IHPSG13_CINVX8 +XDRV<0> qn_int<0> ADDR_N_O<0> VDD VSS / RSC_IHPSG13_CINVX8 +XDFF<4> BIST_EN_I BIST_ADDR_I<4> ACLK_N_I ADDR_I<4> q_int<4> net2<0> VDD ++ VSS / RSC_IHPSG13_DFNQMX2IX1 +XDFF<3> BIST_EN_I BIST_ADDR_I<3> ACLK_N_I ADDR_I<3> q_int<3> net2<1> VDD ++ VSS / RSC_IHPSG13_DFNQMX2IX1 +XDFF<2> BIST_EN_I BIST_ADDR_I<2> ACLK_N_I ADDR_I<2> q_int<2> net2<2> VDD ++ VSS / RSC_IHPSG13_DFNQMX2IX1 +XDFF<1> BIST_EN_I BIST_ADDR_I<1> ACLK_N_I ADDR_I<1> q_int<1> net2<3> VDD ++ VSS / RSC_IHPSG13_DFNQMX2IX1 +XDFF<0> BIST_EN_I BIST_ADDR_I<0> ACLK_N_I ADDR_I<0> q_int<0> net2<4> VDD ++ VSS / RSC_IHPSG13_DFNQMX2IX1 +XI11<16> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI11<15> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI11<14> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI11<13> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI11<12> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI11<11> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI11<10> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI11<9> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI11<8> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI11<7> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI11<6> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI11<5> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI11<4> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI11<3> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI11<2> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI11<1> VDD VSS / RSC_IHPSG13_FILLCAP8 +.ENDS + + +.SUBCKT RM_IHPSG13_512x32_c2_1P_COLDEC5 ACLK_N ADDR<4> ADDR<3> ADDR<2> ADDR<1> ADDR<0> ++ ADDR_COL<1> ADDR_COL<0> ADDR_DEC<7> ADDR_DEC<6> ADDR_DEC<5> ADDR_DEC<4> ++ ADDR_DEC<3> ADDR_DEC<2> ADDR_DEC<1> ADDR_DEC<0> BIST_ADDR<4> BIST_ADDR<3> ++ BIST_ADDR<2> BIST_ADDR<1> BIST_ADDR<0> BIST_EN_I VDD VSS +XI17<2> VDD VSS / RSC_IHPSG13_FILLCAP4 +XI17<1> VDD VSS / RSC_IHPSG13_FILLCAP4 +XI13<1> addr_int<1> ADDR_COL<1> VDD VSS / RSC_IHPSG13_CBUFX2 +XI13<0> addr_int<0> ADDR_COL<0> VDD VSS / RSC_IHPSG13_CBUFX2 +XDFF<4> BIST_EN_I BIST_ADDR<4> ACLK_N ADDR<4> addr_int<1> net7<0> VDD ++ VSS / RSC_IHPSG13_DFNQMX2IX1 +XDFF<3> BIST_EN_I BIST_ADDR<3> ACLK_N ADDR<3> addr_int<0> net7<1> VDD ++ VSS / RSC_IHPSG13_DFNQMX2IX1 +XDFF<2> BIST_EN_I BIST_ADDR<2> ACLK_N ADDR<2> padr_int<2> net7<2> VDD ++ VSS / RSC_IHPSG13_DFNQMX2IX1 +XDFF<1> BIST_EN_I BIST_ADDR<1> ACLK_N ADDR<1> padr_int<1> net7<3> VDD ++ VSS / RSC_IHPSG13_DFNQMX2IX1 +XDFF<0> BIST_EN_I BIST_ADDR<0> ACLK_N ADDR<0> padr_int<0> net7<4> VDD ++ VSS / RSC_IHPSG13_DFNQMX2IX1 +XI1<7> PADR<0> PADR<1> PADR<2> addr_n<7> VDD VSS / RSC_IHPSG13_NAND3X2 +XI1<6> NADR<0> PADR<1> PADR<2> addr_n<6> VDD VSS / RSC_IHPSG13_NAND3X2 +XI1<5> PADR<0> NADR<1> PADR<2> addr_n<5> VDD VSS / RSC_IHPSG13_NAND3X2 +XI1<4> NADR<0> NADR<1> PADR<2> addr_n<4> VDD VSS / RSC_IHPSG13_NAND3X2 +XI1<3> PADR<0> PADR<1> NADR<2> addr_n<3> VDD VSS / RSC_IHPSG13_NAND3X2 +XI1<2> NADR<0> PADR<1> NADR<2> addr_n<2> VDD VSS / RSC_IHPSG13_NAND3X2 +XI1<1> PADR<0> NADR<1> NADR<2> addr_n<1> VDD VSS / RSC_IHPSG13_NAND3X2 +XI1<0> NADR<0> NADR<1> NADR<2> addr_n<0> VDD VSS / RSC_IHPSG13_NAND3X2 +XI15<2> NADR<2> PADR<2> VDD VSS / RSC_IHPSG13_INVX2 +XI15<1> NADR<1> PADR<1> VDD VSS / RSC_IHPSG13_INVX2 +XI15<0> NADR<0> PADR<0> VDD VSS / RSC_IHPSG13_INVX2 +XI3<2> padr_int<2> NADR<2> VDD VSS / RSC_IHPSG13_INVX2 +XI3<1> padr_int<1> NADR<1> VDD VSS / RSC_IHPSG13_INVX2 +XI3<0> padr_int<0> NADR<0> VDD VSS / RSC_IHPSG13_INVX2 +XI2<7> addr_n<7> ADDR_DEC<7> VDD VSS / RSC_IHPSG13_INVX2 +XI2<6> addr_n<6> ADDR_DEC<6> VDD VSS / RSC_IHPSG13_INVX2 +XI2<5> addr_n<5> ADDR_DEC<5> VDD VSS / RSC_IHPSG13_INVX2 +XI2<4> addr_n<4> ADDR_DEC<4> VDD VSS / RSC_IHPSG13_INVX2 +XI2<3> addr_n<3> ADDR_DEC<3> VDD VSS / RSC_IHPSG13_INVX2 +XI2<2> addr_n<2> ADDR_DEC<2> VDD VSS / RSC_IHPSG13_INVX2 +XI2<1> addr_n<1> ADDR_DEC<1> VDD VSS / RSC_IHPSG13_INVX2 +XI2<0> addr_n<0> ADDR_DEC<0> VDD VSS / RSC_IHPSG13_INVX2 +.ENDS +.SUBCKT RM_IHPSG13_512x32_c2_1P_COLCTRL5 A_ADDR_COL<1> A_ADDR_COL<0> A_ADDR_DEC<7> ++ A_ADDR_DEC<6> A_ADDR_DEC<5> A_ADDR_DEC<4> A_ADDR_DEC<3> A_ADDR_DEC<2> ++ A_ADDR_DEC<1> A_ADDR_DEC<0> A_BIST_BM_I A_BIST_DW_I A_BIST_EN_I A_BLC<31> ++ A_BLC<30> A_BLC<29> A_BLC<28> A_BLC<27> A_BLC<26> A_BLC<25> A_BLC<24> ++ A_BLC<23> A_BLC<22> A_BLC<21> A_BLC<20> A_BLC<19> A_BLC<18> A_BLC<17> ++ A_BLC<16> A_BLC<15> A_BLC<14> A_BLC<13> A_BLC<12> A_BLC<11> A_BLC<10> ++ A_BLC<9> A_BLC<8> A_BLC<7> A_BLC<6> A_BLC<5> A_BLC<4> A_BLC<3> A_BLC<2> ++ A_BLC<1> A_BLC<0> A_BLT<31> A_BLT<30> A_BLT<29> A_BLT<28> A_BLT<27> ++ A_BLT<26> A_BLT<25> A_BLT<24> A_BLT<23> A_BLT<22> A_BLT<21> A_BLT<20> ++ A_BLT<19> A_BLT<18> A_BLT<17> A_BLT<16> A_BLT<15> A_BLT<14> A_BLT<13> ++ A_BLT<12> A_BLT<11> A_BLT<10> A_BLT<9> A_BLT<8> A_BLT<7> A_BLT<6> A_BLT<5> ++ A_BLT<4> A_BLT<3> A_BLT<2> A_BLT<1> A_BLT<0> A_BM_I A_DCLK_B_L A_DCLK_B_R ++ A_DCLK_L A_DCLK_R A_DR_O A_DW_I A_RCLK_B_L A_RCLK_B_R A_RCLK_L A_RCLK_R ++ A_TIEH_O A_WCLK_B_L A_WCLK_B_R A_WCLK_L A_WCLK_R VDD VSS +XA_I80<1> A_WCLK_B_L A_RCLK_B_L A_W_nor_R<1> VDD VSS / ++ RSC_IHPSG13_AND2X2 +XA_I80<0> A_WCLK_B_L A_RCLK_B_L A_W_nor_R<0> VDD VSS / ++ RSC_IHPSG13_AND2X2 +XA_I44 A_BM_N A_WCLK_B_L A_DO_WRITE_P VDD VSS / RSC_IHPSG13_NOR2X2 +XI80<29> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI80<28> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI80<27> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI80<26> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI80<25> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI80<24> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI80<23> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI80<22> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI80<21> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI80<20> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI80<19> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI80<18> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI80<17> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI80<16> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI80<15> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI80<14> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI80<13> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI80<12> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI80<11> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI80<10> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI80<9> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI80<8> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI80<7> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI80<6> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI80<5> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI80<4> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI80<3> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI80<2> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI80<1> VDD VSS / RSC_IHPSG13_FILLCAP8 +XA_I74<16> VDD VSS / RSC_IHPSG13_FILLCAP8 +XA_I74<15> VDD VSS / RSC_IHPSG13_FILLCAP8 +XA_I74<14> VDD VSS / RSC_IHPSG13_FILLCAP8 +XA_I74<13> VDD VSS / RSC_IHPSG13_FILLCAP8 +XA_I74<12> VDD VSS / RSC_IHPSG13_FILLCAP8 +XA_I74<11> VDD VSS / RSC_IHPSG13_FILLCAP8 +XA_I74<10> VDD VSS / RSC_IHPSG13_FILLCAP8 +XA_I74<9> VDD VSS / RSC_IHPSG13_FILLCAP8 +XA_I74<8> VDD VSS / RSC_IHPSG13_FILLCAP8 +XA_I74<7> VDD VSS / RSC_IHPSG13_FILLCAP8 +XA_I74<6> VDD VSS / RSC_IHPSG13_FILLCAP8 +XA_I74<5> VDD VSS / RSC_IHPSG13_FILLCAP8 +XA_I74<4> VDD VSS / RSC_IHPSG13_FILLCAP8 +XA_I74<3> VDD VSS / RSC_IHPSG13_FILLCAP8 +XA_I74<2> VDD VSS / RSC_IHPSG13_FILLCAP8 +XA_I74<1> VDD VSS / RSC_IHPSG13_FILLCAP8 +XA_INV<6> A_N1<1> A_P1<1> VDD VSS / RSC_IHPSG13_CINVX4 +XA_INV<5> A_N0<1> A_P0<1> VDD VSS / RSC_IHPSG13_CINVX4 +XA_INV<4> A_N0<0> A_P0<0> VDD VSS / RSC_IHPSG13_CINVX4 +XA_INV<3> A_ADDR_COL<1> A_N1<1> VDD VSS / RSC_IHPSG13_CINVX4 +XA_INV<2> A_ADDR_COL<1> A_N1<0> VDD VSS / RSC_IHPSG13_CINVX4 +XA_INV<1> A_ADDR_COL<0> A_N0<1> VDD VSS / RSC_IHPSG13_CINVX4 +XA_INV<0> A_ADDR_COL<0> A_N0<0> VDD VSS / RSC_IHPSG13_CINVX4 +XA_I81<3> A_W_nor_R<1> A_PRE_N VDD VSS / RSC_IHPSG13_CINVX4_WN +XA_I81<2> A_W_nor_R<1> A_PRE_N VDD VSS / RSC_IHPSG13_CINVX4_WN +XA_I81<1> A_W_nor_R<0> A_PRE_N VDD VSS / RSC_IHPSG13_CINVX4_WN +XA_I81<0> A_W_nor_R<0> A_PRE_N VDD VSS / RSC_IHPSG13_CINVX4_WN +XA_BLTMUX<31> A_BLC<31> A_BLC_SEL A_BLT<31> A_BLT_SEL A_PRE_N A_SEL_P<31> ++ A_WR_ONE A_WR_ZERO VDD VSS / RM_IHPSG13_512x32_c2_1P_BLDRV +XA_BLTMUX<30> A_BLC<30> A_BLC_SEL A_BLT<30> A_BLT_SEL A_PRE_N A_SEL_P<30> ++ A_WR_ONE A_WR_ZERO VDD VSS / RM_IHPSG13_512x32_c2_1P_BLDRV +XA_BLTMUX<29> A_BLC<29> A_BLC_SEL A_BLT<29> A_BLT_SEL A_PRE_N A_SEL_P<29> ++ A_WR_ONE A_WR_ZERO VDD VSS / RM_IHPSG13_512x32_c2_1P_BLDRV +XA_BLTMUX<28> A_BLC<28> A_BLC_SEL A_BLT<28> A_BLT_SEL A_PRE_N A_SEL_P<28> ++ A_WR_ONE A_WR_ZERO VDD VSS / RM_IHPSG13_512x32_c2_1P_BLDRV +XA_BLTMUX<27> A_BLC<27> A_BLC_SEL A_BLT<27> A_BLT_SEL A_PRE_N A_SEL_P<27> ++ A_WR_ONE A_WR_ZERO VDD VSS / RM_IHPSG13_512x32_c2_1P_BLDRV +XA_BLTMUX<26> A_BLC<26> A_BLC_SEL A_BLT<26> A_BLT_SEL A_PRE_N A_SEL_P<26> ++ A_WR_ONE A_WR_ZERO VDD VSS / RM_IHPSG13_512x32_c2_1P_BLDRV +XA_BLTMUX<25> A_BLC<25> A_BLC_SEL A_BLT<25> A_BLT_SEL A_PRE_N A_SEL_P<25> ++ A_WR_ONE A_WR_ZERO VDD VSS / RM_IHPSG13_512x32_c2_1P_BLDRV +XA_BLTMUX<24> A_BLC<24> A_BLC_SEL A_BLT<24> A_BLT_SEL A_PRE_N A_SEL_P<24> ++ A_WR_ONE A_WR_ZERO VDD VSS / RM_IHPSG13_512x32_c2_1P_BLDRV +XA_BLTMUX<23> A_BLC<23> A_BLC_SEL A_BLT<23> A_BLT_SEL A_PRE_N A_SEL_P<23> ++ A_WR_ONE A_WR_ZERO VDD VSS / RM_IHPSG13_512x32_c2_1P_BLDRV +XA_BLTMUX<22> A_BLC<22> A_BLC_SEL A_BLT<22> A_BLT_SEL A_PRE_N A_SEL_P<22> ++ A_WR_ONE A_WR_ZERO VDD VSS / RM_IHPSG13_512x32_c2_1P_BLDRV +XA_BLTMUX<21> A_BLC<21> A_BLC_SEL A_BLT<21> A_BLT_SEL A_PRE_N A_SEL_P<21> ++ A_WR_ONE A_WR_ZERO VDD VSS / RM_IHPSG13_512x32_c2_1P_BLDRV +XA_BLTMUX<20> A_BLC<20> A_BLC_SEL A_BLT<20> A_BLT_SEL A_PRE_N A_SEL_P<20> ++ A_WR_ONE A_WR_ZERO VDD VSS / RM_IHPSG13_512x32_c2_1P_BLDRV +XA_BLTMUX<19> A_BLC<19> A_BLC_SEL A_BLT<19> A_BLT_SEL A_PRE_N A_SEL_P<19> ++ A_WR_ONE A_WR_ZERO VDD VSS / RM_IHPSG13_512x32_c2_1P_BLDRV +XA_BLTMUX<18> A_BLC<18> A_BLC_SEL A_BLT<18> A_BLT_SEL A_PRE_N A_SEL_P<18> ++ A_WR_ONE A_WR_ZERO VDD VSS / RM_IHPSG13_512x32_c2_1P_BLDRV +XA_BLTMUX<17> A_BLC<17> A_BLC_SEL A_BLT<17> A_BLT_SEL A_PRE_N A_SEL_P<17> ++ A_WR_ONE A_WR_ZERO VDD VSS / RM_IHPSG13_512x32_c2_1P_BLDRV +XA_BLTMUX<16> A_BLC<16> A_BLC_SEL A_BLT<16> A_BLT_SEL A_PRE_N A_SEL_P<16> ++ A_WR_ONE A_WR_ZERO VDD VSS / RM_IHPSG13_512x32_c2_1P_BLDRV +XA_BLTMUX<15> A_BLC<15> A_BLC_SEL A_BLT<15> A_BLT_SEL A_PRE_N A_SEL_P<15> ++ A_WR_ONE A_WR_ZERO VDD VSS / RM_IHPSG13_512x32_c2_1P_BLDRV +XA_BLTMUX<14> A_BLC<14> A_BLC_SEL A_BLT<14> A_BLT_SEL A_PRE_N A_SEL_P<14> ++ A_WR_ONE A_WR_ZERO VDD VSS / RM_IHPSG13_512x32_c2_1P_BLDRV +XA_BLTMUX<13> A_BLC<13> A_BLC_SEL A_BLT<13> A_BLT_SEL A_PRE_N A_SEL_P<13> ++ A_WR_ONE A_WR_ZERO VDD VSS / RM_IHPSG13_512x32_c2_1P_BLDRV +XA_BLTMUX<12> A_BLC<12> A_BLC_SEL A_BLT<12> A_BLT_SEL A_PRE_N A_SEL_P<12> ++ A_WR_ONE A_WR_ZERO VDD VSS / RM_IHPSG13_512x32_c2_1P_BLDRV +XA_BLTMUX<11> A_BLC<11> A_BLC_SEL A_BLT<11> A_BLT_SEL A_PRE_N A_SEL_P<11> ++ A_WR_ONE A_WR_ZERO VDD VSS / RM_IHPSG13_512x32_c2_1P_BLDRV +XA_BLTMUX<10> A_BLC<10> A_BLC_SEL A_BLT<10> A_BLT_SEL A_PRE_N A_SEL_P<10> ++ A_WR_ONE A_WR_ZERO VDD VSS / RM_IHPSG13_512x32_c2_1P_BLDRV +XA_BLTMUX<9> A_BLC<9> A_BLC_SEL A_BLT<9> A_BLT_SEL A_PRE_N A_SEL_P<9> A_WR_ONE ++ A_WR_ZERO VDD VSS / RM_IHPSG13_512x32_c2_1P_BLDRV +XA_BLTMUX<8> A_BLC<8> A_BLC_SEL A_BLT<8> A_BLT_SEL A_PRE_N A_SEL_P<8> A_WR_ONE ++ A_WR_ZERO VDD VSS / RM_IHPSG13_512x32_c2_1P_BLDRV +XA_BLTMUX<7> A_BLC<7> A_BLC_SEL A_BLT<7> A_BLT_SEL A_PRE_N A_SEL_P<7> A_WR_ONE ++ A_WR_ZERO VDD VSS / RM_IHPSG13_512x32_c2_1P_BLDRV +XA_BLTMUX<6> A_BLC<6> A_BLC_SEL A_BLT<6> A_BLT_SEL A_PRE_N A_SEL_P<6> A_WR_ONE ++ A_WR_ZERO VDD VSS / RM_IHPSG13_512x32_c2_1P_BLDRV +XA_BLTMUX<5> A_BLC<5> A_BLC_SEL A_BLT<5> A_BLT_SEL A_PRE_N A_SEL_P<5> A_WR_ONE ++ A_WR_ZERO VDD VSS / RM_IHPSG13_512x32_c2_1P_BLDRV +XA_BLTMUX<4> A_BLC<4> A_BLC_SEL A_BLT<4> A_BLT_SEL A_PRE_N A_SEL_P<4> A_WR_ONE ++ A_WR_ZERO VDD VSS / RM_IHPSG13_512x32_c2_1P_BLDRV +XA_BLTMUX<3> A_BLC<3> A_BLC_SEL A_BLT<3> A_BLT_SEL A_PRE_N A_SEL_P<3> A_WR_ONE ++ A_WR_ZERO VDD VSS / RM_IHPSG13_512x32_c2_1P_BLDRV +XA_BLTMUX<2> A_BLC<2> A_BLC_SEL A_BLT<2> A_BLT_SEL A_PRE_N A_SEL_P<2> A_WR_ONE ++ A_WR_ZERO VDD VSS / RM_IHPSG13_512x32_c2_1P_BLDRV +XA_BLTMUX<1> A_BLC<1> A_BLC_SEL A_BLT<1> A_BLT_SEL A_PRE_N A_SEL_P<1> A_WR_ONE ++ A_WR_ZERO VDD VSS / RM_IHPSG13_512x32_c2_1P_BLDRV +XA_BLTMUX<0> A_BLC<0> A_BLC_SEL A_BLT<0> A_BLT_SEL A_PRE_N A_SEL_P<0> A_WR_ONE ++ A_WR_ZERO VDD VSS / RM_IHPSG13_512x32_c2_1P_BLDRV +XA_CAPS<17> VDD VSS / RSC_IHPSG13_FILLCAP4 +XA_CAPS<16> VDD VSS / RSC_IHPSG13_FILLCAP4 +XA_CAPS<15> VDD VSS / RSC_IHPSG13_FILLCAP4 +XA_CAPS<14> VDD VSS / RSC_IHPSG13_FILLCAP4 +XA_CAPS<13> VDD VSS / RSC_IHPSG13_FILLCAP4 +XA_CAPS<12> VDD VSS / RSC_IHPSG13_FILLCAP4 +XA_CAPS<11> VDD VSS / RSC_IHPSG13_FILLCAP4 +XA_CAPS<10> VDD VSS / RSC_IHPSG13_FILLCAP4 +XA_CAPS<9> VDD VSS / RSC_IHPSG13_FILLCAP4 +XA_CAPS<8> VDD VSS / RSC_IHPSG13_FILLCAP4 +XA_CAPS<7> VDD VSS / RSC_IHPSG13_FILLCAP4 +XA_CAPS<6> VDD VSS / RSC_IHPSG13_FILLCAP4 +XA_CAPS<5> VDD VSS / RSC_IHPSG13_FILLCAP4 +XA_CAPS<4> VDD VSS / RSC_IHPSG13_FILLCAP4 +XA_CAPS<3> VDD VSS / RSC_IHPSG13_FILLCAP4 +XA_CAPS<2> VDD VSS / RSC_IHPSG13_FILLCAP4 +XA_CAPS<1> VDD VSS / RSC_IHPSG13_FILLCAP4 +XA_I51 net19 A_DR_O VDD VSS / RSC_IHPSG13_INVX4 +XA_I78 A_RCLK_B_L A_SAE VDD VSS / RSC_IHPSG13_CBUFX2 +XA_I69 A_DCLK_L A_DCLK_B_L VDD VSS / RSC_IHPSG13_CINVX8 +XA_I50 A_WCLK_L A_WCLK_B_L VDD VSS / RSC_IHPSG13_CINVX8 +XA_EBUF A_RCLK_L A_RCLK_B_L VDD VSS / RSC_IHPSG13_CINVX8 +XA_I76 A_DI_N A_DO_WRITE_P A_WR_ZERO VDD VSS / RSC_IHPSG13_AND2X6 +XA_I75 A_DI_R A_DO_WRITE_P A_WR_ONE VDD VSS / RSC_IHPSG13_AND2X6 +XA_I83 A_BM_R A_BM_N VDD VSS / RSC_IHPSG13_INVX2 +XA_DEC3INV<31> net23<0> A_SEL_P<31> VDD VSS / RSC_IHPSG13_INVX2 +XA_DEC3INV<30> net23<1> A_SEL_P<30> VDD VSS / RSC_IHPSG13_INVX2 +XA_DEC3INV<29> net23<2> A_SEL_P<29> VDD VSS / RSC_IHPSG13_INVX2 +XA_DEC3INV<28> net23<3> A_SEL_P<28> VDD VSS / RSC_IHPSG13_INVX2 +XA_DEC3INV<27> net23<4> A_SEL_P<27> VDD VSS / RSC_IHPSG13_INVX2 +XA_DEC3INV<26> net23<5> A_SEL_P<26> VDD VSS / RSC_IHPSG13_INVX2 +XA_DEC3INV<25> net23<6> A_SEL_P<25> VDD VSS / RSC_IHPSG13_INVX2 +XA_DEC3INV<24> net23<7> A_SEL_P<24> VDD VSS / RSC_IHPSG13_INVX2 +XA_DEC3INV<23> net23<8> A_SEL_P<23> VDD VSS / RSC_IHPSG13_INVX2 +XA_DEC3INV<22> net23<9> A_SEL_P<22> VDD VSS / RSC_IHPSG13_INVX2 +XA_DEC3INV<21> net23<10> A_SEL_P<21> VDD VSS / RSC_IHPSG13_INVX2 +XA_DEC3INV<20> net23<11> A_SEL_P<20> VDD VSS / RSC_IHPSG13_INVX2 +XA_DEC3INV<19> net23<12> A_SEL_P<19> VDD VSS / RSC_IHPSG13_INVX2 +XA_DEC3INV<18> net23<13> A_SEL_P<18> VDD VSS / RSC_IHPSG13_INVX2 +XA_DEC3INV<17> net23<14> A_SEL_P<17> VDD VSS / RSC_IHPSG13_INVX2 +XA_DEC3INV<16> net23<15> A_SEL_P<16> VDD VSS / RSC_IHPSG13_INVX2 +XA_DEC3INV<15> net23<16> A_SEL_P<15> VDD VSS / RSC_IHPSG13_INVX2 +XA_DEC3INV<14> net23<17> A_SEL_P<14> VDD VSS / RSC_IHPSG13_INVX2 +XA_DEC3INV<13> net23<18> A_SEL_P<13> VDD VSS / RSC_IHPSG13_INVX2 +XA_DEC3INV<12> net23<19> A_SEL_P<12> VDD VSS / RSC_IHPSG13_INVX2 +XA_DEC3INV<11> net23<20> A_SEL_P<11> VDD VSS / RSC_IHPSG13_INVX2 +XA_DEC3INV<10> net23<21> A_SEL_P<10> VDD VSS / RSC_IHPSG13_INVX2 +XA_DEC3INV<9> net23<22> A_SEL_P<9> VDD VSS / RSC_IHPSG13_INVX2 +XA_DEC3INV<8> net23<23> A_SEL_P<8> VDD VSS / RSC_IHPSG13_INVX2 +XA_DEC3INV<7> net23<24> A_SEL_P<7> VDD VSS / RSC_IHPSG13_INVX2 +XA_DEC3INV<6> net23<25> A_SEL_P<6> VDD VSS / RSC_IHPSG13_INVX2 +XA_DEC3INV<5> net23<26> A_SEL_P<5> VDD VSS / RSC_IHPSG13_INVX2 +XA_DEC3INV<4> net23<27> A_SEL_P<4> VDD VSS / RSC_IHPSG13_INVX2 +XA_DEC3INV<3> net23<28> A_SEL_P<3> VDD VSS / RSC_IHPSG13_INVX2 +XA_DEC3INV<2> net23<29> A_SEL_P<2> VDD VSS / RSC_IHPSG13_INVX2 +XA_DEC3INV<1> net23<30> A_SEL_P<1> VDD VSS / RSC_IHPSG13_INVX2 +XA_DEC3INV<0> net23<31> A_SEL_P<0> VDD VSS / RSC_IHPSG13_INVX2 +XA_I49 A_DI_R A_DI_N VDD VSS / RSC_IHPSG13_INVX2 +XA_ISENSE A_SAE A_BLC_SEL A_BLT_SEL net19 net20 VDD VSS / ++ RSC_IHPSG13_DFPQD_MSAFFX2 +XA_DREG A_BIST_EN_I A_BIST_DW_I A_DCLK_B_L A_DW_I A_DI_R net22 VDD VSS ++ / RSC_IHPSG13_DFNQMX2IX1 +XA_BREG A_BIST_EN_I A_BIST_BM_I A_DCLK_B_L A_BM_I A_BM_R net21 VDD VSS ++ / RSC_IHPSG13_DFNQMX2IX1 +XA_DEC3<31> A_P1<1> A_P0<1> A_ADDR_DEC<7> net23<0> VDD VSS / ++ RSC_IHPSG13_NAND3X2 +XA_DEC3<30> A_P1<1> A_P0<1> A_ADDR_DEC<6> net23<1> VDD VSS / ++ RSC_IHPSG13_NAND3X2 +XA_DEC3<29> A_P1<1> A_P0<1> A_ADDR_DEC<5> net23<2> VDD VSS / ++ RSC_IHPSG13_NAND3X2 +XA_DEC3<28> A_P1<1> A_P0<1> A_ADDR_DEC<4> net23<3> VDD VSS / ++ RSC_IHPSG13_NAND3X2 +XA_DEC3<27> A_P1<1> A_P0<1> A_ADDR_DEC<3> net23<4> VDD VSS / ++ RSC_IHPSG13_NAND3X2 +XA_DEC3<26> A_P1<1> A_P0<1> A_ADDR_DEC<2> net23<5> VDD VSS / ++ RSC_IHPSG13_NAND3X2 +XA_DEC3<25> A_P1<1> A_P0<1> A_ADDR_DEC<1> net23<6> VDD VSS / ++ RSC_IHPSG13_NAND3X2 +XA_DEC3<24> A_P1<1> A_P0<1> A_ADDR_DEC<0> net23<7> VDD VSS / ++ RSC_IHPSG13_NAND3X2 +XA_DEC3<23> A_P1<1> A_N0<1> A_ADDR_DEC<7> net23<8> VDD VSS / ++ RSC_IHPSG13_NAND3X2 +XA_DEC3<22> A_P1<1> A_N0<1> A_ADDR_DEC<6> net23<9> VDD VSS / ++ RSC_IHPSG13_NAND3X2 +XA_DEC3<21> A_P1<1> A_N0<1> A_ADDR_DEC<5> net23<10> VDD VSS / ++ RSC_IHPSG13_NAND3X2 +XA_DEC3<20> A_P1<1> A_N0<1> A_ADDR_DEC<4> net23<11> VDD VSS / ++ RSC_IHPSG13_NAND3X2 +XA_DEC3<19> A_P1<1> A_N0<1> A_ADDR_DEC<3> net23<12> VDD VSS / ++ RSC_IHPSG13_NAND3X2 +XA_DEC3<18> A_P1<1> A_N0<1> A_ADDR_DEC<2> net23<13> VDD VSS / ++ RSC_IHPSG13_NAND3X2 +XA_DEC3<17> A_P1<1> A_N0<1> A_ADDR_DEC<1> net23<14> VDD VSS / ++ RSC_IHPSG13_NAND3X2 +XA_DEC3<16> A_P1<1> A_N0<1> A_ADDR_DEC<0> net23<15> VDD VSS / ++ RSC_IHPSG13_NAND3X2 +XA_DEC3<15> A_N1<0> A_P0<0> A_ADDR_DEC<7> net23<16> VDD VSS / ++ RSC_IHPSG13_NAND3X2 +XA_DEC3<14> A_N1<0> A_P0<0> A_ADDR_DEC<6> net23<17> VDD VSS / ++ RSC_IHPSG13_NAND3X2 +XA_DEC3<13> A_N1<0> A_P0<0> A_ADDR_DEC<5> net23<18> VDD VSS / ++ RSC_IHPSG13_NAND3X2 +XA_DEC3<12> A_N1<0> A_P0<0> A_ADDR_DEC<4> net23<19> VDD VSS / ++ RSC_IHPSG13_NAND3X2 +XA_DEC3<11> A_N1<0> A_P0<0> A_ADDR_DEC<3> net23<20> VDD VSS / ++ RSC_IHPSG13_NAND3X2 +XA_DEC3<10> A_N1<0> A_P0<0> A_ADDR_DEC<2> net23<21> VDD VSS / ++ RSC_IHPSG13_NAND3X2 +XA_DEC3<9> A_N1<0> A_P0<0> A_ADDR_DEC<1> net23<22> VDD VSS / ++ RSC_IHPSG13_NAND3X2 +XA_DEC3<8> A_N1<0> A_P0<0> A_ADDR_DEC<0> net23<23> VDD VSS / ++ RSC_IHPSG13_NAND3X2 +XA_DEC3<7> A_N1<0> A_N0<0> A_ADDR_DEC<7> net23<24> VDD VSS / ++ RSC_IHPSG13_NAND3X2 +XA_DEC3<6> A_N1<0> A_N0<0> A_ADDR_DEC<6> net23<25> VDD VSS / ++ RSC_IHPSG13_NAND3X2 +XA_DEC3<5> A_N1<0> A_N0<0> A_ADDR_DEC<5> net23<26> VDD VSS / ++ RSC_IHPSG13_NAND3X2 +XA_DEC3<4> A_N1<0> A_N0<0> A_ADDR_DEC<4> net23<27> VDD VSS / ++ RSC_IHPSG13_NAND3X2 +XA_DEC3<3> A_N1<0> A_N0<0> A_ADDR_DEC<3> net23<28> VDD VSS / ++ RSC_IHPSG13_NAND3X2 +XA_DEC3<2> A_N1<0> A_N0<0> A_ADDR_DEC<2> net23<29> VDD VSS / ++ RSC_IHPSG13_NAND3X2 +XA_DEC3<1> A_N1<0> A_N0<0> A_ADDR_DEC<1> net23<30> VDD VSS / ++ RSC_IHPSG13_NAND3X2 +XA_DEC3<0> A_N1<0> A_N0<0> A_ADDR_DEC<0> net23<31> VDD VSS / ++ RSC_IHPSG13_NAND3X2 +XA_I89 A_DCLK_B_L A_DCLK_B_R / RSC_IHPSG13_MET3RES +XA_I91 A_RCLK_B_L A_RCLK_B_R / RSC_IHPSG13_MET3RES +XA_I90 A_WCLK_B_L A_WCLK_B_R / RSC_IHPSG13_MET3RES +XA_I88 A_DCLK_L A_DCLK_R / RSC_IHPSG13_MET3RES +XA_I87 A_WCLK_L A_WCLK_R / RSC_IHPSG13_MET3RES +XA_R2 A_RCLK_L A_RCLK_R / RSC_IHPSG13_MET3RES +XA_BM_TIEH A_TIEH_O VDD VSS / RSC_IHPSG13_TIEH +.ENDS + +.SUBCKT RM_IHPSG13_512x32_c2_1P_COLDRV13X12 ADDR_COL_I<1> ADDR_COL_I<0> ADDR_COL_O<1> ++ ADDR_COL_O<0> ADDR_DEC_I<7> ADDR_DEC_I<6> ADDR_DEC_I<5> ADDR_DEC_I<4> ++ ADDR_DEC_I<3> ADDR_DEC_I<2> ADDR_DEC_I<1> ADDR_DEC_I<0> ADDR_DEC_O<7> ++ ADDR_DEC_O<6> ADDR_DEC_O<5> ADDR_DEC_O<4> ADDR_DEC_O<3> ADDR_DEC_O<2> ++ ADDR_DEC_O<1> ADDR_DEC_O<0> DCLK_I DCLK_O RCLK_I RCLK_O WCLK_I WCLK_O ++ VDD VSS +XI1<1> VDD VSS / RSC_IHPSG13_FILLCAP4 +XI1<0> VDD VSS / RSC_IHPSG13_FILLCAP4 +XI0<1> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI0<0> VDD VSS / RSC_IHPSG13_FILLCAP8 +XADDR_COL_DRV<1> ADDR_COL_I<1> ADDR_COL_O<1> VDD VSS / ++ RSC_IHPSG13_CBUFX12 +XADDR_COL_DRV<0> ADDR_COL_I<0> ADDR_COL_O<0> VDD VSS / ++ RSC_IHPSG13_CBUFX12 +XADDR_DEC_DRV<7> ADDR_DEC_I<7> ADDR_DEC_O<7> VDD VSS / ++ RSC_IHPSG13_CBUFX12 +XADDR_DEC_DRV<6> ADDR_DEC_I<6> ADDR_DEC_O<6> VDD VSS / ++ RSC_IHPSG13_CBUFX12 +XADDR_DEC_DRV<5> ADDR_DEC_I<5> ADDR_DEC_O<5> VDD VSS / ++ RSC_IHPSG13_CBUFX12 +XADDR_DEC_DRV<4> ADDR_DEC_I<4> ADDR_DEC_O<4> VDD VSS / ++ RSC_IHPSG13_CBUFX12 +XADDR_DEC_DRV<3> ADDR_DEC_I<3> ADDR_DEC_O<3> VDD VSS / ++ RSC_IHPSG13_CBUFX12 +XADDR_DEC_DRV<2> ADDR_DEC_I<2> ADDR_DEC_O<2> VDD VSS / ++ RSC_IHPSG13_CBUFX12 +XADDR_DEC_DRV<1> ADDR_DEC_I<1> ADDR_DEC_O<1> VDD VSS / ++ RSC_IHPSG13_CBUFX12 +XADDR_DEC_DRV<0> ADDR_DEC_I<0> ADDR_DEC_O<0> VDD VSS / ++ RSC_IHPSG13_CBUFX12 +XDCLK_DRV DCLK_I DCLK_O VDD VSS / RSC_IHPSG13_CBUFX12 +XRCLK_DRV RCLK_I RCLK_O VDD VSS / RSC_IHPSG13_CBUFX12 +XWCLK_DRV WCLK_I WCLK_O VDD VSS / RSC_IHPSG13_CBUFX12 +.ENDS +.SUBCKT RM_IHPSG13_512x32_c2_1P_WLDRV16X12 A<15> A<14> A<13> A<12> A<11> A<10> A<9> A<8> ++ A<7> A<6> A<5> A<4> A<3> A<2> A<1> A<0> Z<15> Z<14> Z<13> Z<12> Z<11> Z<10> ++ Z<9> Z<8> Z<7> Z<6> Z<5> Z<4> Z<3> Z<2> Z<1> Z<0> VDD VSS +XBUF<15> A<15> Z<15> VDD VSS / RSC_IHPSG13_WLDRVX12 +XBUF<14> A<14> Z<14> VDD VSS / RSC_IHPSG13_WLDRVX12 +XBUF<13> A<13> Z<13> VDD VSS / RSC_IHPSG13_WLDRVX12 +XBUF<12> A<12> Z<12> VDD VSS / RSC_IHPSG13_WLDRVX12 +XBUF<11> A<11> Z<11> VDD VSS / RSC_IHPSG13_WLDRVX12 +XBUF<10> A<10> Z<10> VDD VSS / RSC_IHPSG13_WLDRVX12 +XBUF<9> A<9> Z<9> VDD VSS / RSC_IHPSG13_WLDRVX12 +XBUF<8> A<8> Z<8> VDD VSS / RSC_IHPSG13_WLDRVX12 +XBUF<7> A<7> Z<7> VDD VSS / RSC_IHPSG13_WLDRVX12 +XBUF<6> A<6> Z<6> VDD VSS / RSC_IHPSG13_WLDRVX12 +XBUF<5> A<5> Z<5> VDD VSS / RSC_IHPSG13_WLDRVX12 +XBUF<4> A<4> Z<4> VDD VSS / RSC_IHPSG13_WLDRVX12 +XBUF<3> A<3> Z<3> VDD VSS / RSC_IHPSG13_WLDRVX12 +XBUF<2> A<2> Z<2> VDD VSS / RSC_IHPSG13_WLDRVX12 +XBUF<1> A<1> Z<1> VDD VSS / RSC_IHPSG13_WLDRVX12 +XBUF<0> A<0> Z<0> VDD VSS / RSC_IHPSG13_WLDRVX12 +.ENDS + + + +.SUBCKT RM_IHPSG13_512x32_c2_2P_COLDRV13X8 ADDR_COL_I<1> ADDR_COL_I<0> ADDR_COL_O<1> ++ ADDR_COL_O<0> ADDR_DEC_I<7> ADDR_DEC_I<6> ADDR_DEC_I<5> ADDR_DEC_I<4> ++ ADDR_DEC_I<3> ADDR_DEC_I<2> ADDR_DEC_I<1> ADDR_DEC_I<0> ADDR_DEC_O<7> ++ ADDR_DEC_O<6> ADDR_DEC_O<5> ADDR_DEC_O<4> ADDR_DEC_O<3> ADDR_DEC_O<2> ++ ADDR_DEC_O<1> ADDR_DEC_O<0> DCLK_I DCLK_O RCLK_I RCLK_O WCLK_I WCLK_O ++ VDD VSS +XI0<5> VDD VSS / RSC_IHPSG13_FILLCAP4 +XI0<4> VDD VSS / RSC_IHPSG13_FILLCAP4 +XI0<3> VDD VSS / RSC_IHPSG13_FILLCAP4 +XI0<2> VDD VSS / RSC_IHPSG13_FILLCAP4 +XI0<1> VDD VSS / RSC_IHPSG13_FILLCAP4 +XWCLK_DRV WCLK_I WCLK_O VDD VSS / RSC_IHPSG13_CBUFX8 +XRCLK_DRV RCLK_I RCLK_O VDD VSS / RSC_IHPSG13_CBUFX8 +XDCLK_DRV DCLK_I DCLK_O VDD VSS / RSC_IHPSG13_CBUFX8 +XADDR_COL_DRV<1> ADDR_COL_I<1> ADDR_COL_O<1> VDD VSS / ++ RSC_IHPSG13_CBUFX8 +XADDR_COL_DRV<0> ADDR_COL_I<0> ADDR_COL_O<0> VDD VSS / ++ RSC_IHPSG13_CBUFX8 +XADDR_DEC_DRV<7> ADDR_DEC_I<7> ADDR_DEC_O<7> VDD VSS / ++ RSC_IHPSG13_CBUFX8 +XADDR_DEC_DRV<6> ADDR_DEC_I<6> ADDR_DEC_O<6> VDD VSS / ++ RSC_IHPSG13_CBUFX8 +XADDR_DEC_DRV<5> ADDR_DEC_I<5> ADDR_DEC_O<5> VDD VSS / ++ RSC_IHPSG13_CBUFX8 +XADDR_DEC_DRV<4> ADDR_DEC_I<4> ADDR_DEC_O<4> VDD VSS / ++ RSC_IHPSG13_CBUFX8 +XADDR_DEC_DRV<3> ADDR_DEC_I<3> ADDR_DEC_O<3> VDD VSS / ++ RSC_IHPSG13_CBUFX8 +XADDR_DEC_DRV<2> ADDR_DEC_I<2> ADDR_DEC_O<2> VDD VSS / ++ RSC_IHPSG13_CBUFX8 +XADDR_DEC_DRV<1> ADDR_DEC_I<1> ADDR_DEC_O<1> VDD VSS / ++ RSC_IHPSG13_CBUFX8 +XADDR_DEC_DRV<0> ADDR_DEC_I<0> ADDR_DEC_O<0> VDD VSS / ++ RSC_IHPSG13_CBUFX8 +XI1<3> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI1<2> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI1<1> VDD VSS / RSC_IHPSG13_FILLCAP8 +.ENDS +.SUBCKT RSC_IHPSG13_WLDRVX8 A Z VDD VSS +MN1 Z net6 VSS VSS sg13_lv_nmos m=1 w=1.41u l=130.00n ng=2 nrd=0 nrs=0 +MN0 net6 A VSS VSS sg13_lv_nmos m=1 w=1.8u l=130.00n ng=2 nrd=0 nrs=0 +MP1 Z net6 VDD VDD sg13_lv_pmos m=1 w=6.48u l=130.00n ng=4 nrd=0 nrs=0 +MP0 net6 A VDD VDD sg13_lv_pmos m=1 w=900.0n l=130.00n ng=1 nrd=0 nrs=0 +.ENDS +.SUBCKT RM_IHPSG13_512x32_c2_2P_WLDRV16X8 A<15> A<14> A<13> A<12> A<11> A<10> A<9> A<8> ++ A<7> A<6> A<5> A<4> A<3> A<2> A<1> A<0> Z<15> Z<14> Z<13> Z<12> Z<11> Z<10> ++ Z<9> Z<8> Z<7> Z<6> Z<5> Z<4> Z<3> Z<2> Z<1> Z<0> VDD VSS +XBUF<15> A<15> Z<15> VDD VSS / RSC_IHPSG13_WLDRVX8 +XBUF<14> A<14> Z<14> VDD VSS / RSC_IHPSG13_WLDRVX8 +XBUF<13> A<13> Z<13> VDD VSS / RSC_IHPSG13_WLDRVX8 +XBUF<12> A<12> Z<12> VDD VSS / RSC_IHPSG13_WLDRVX8 +XBUF<11> A<11> Z<11> VDD VSS / RSC_IHPSG13_WLDRVX8 +XBUF<10> A<10> Z<10> VDD VSS / RSC_IHPSG13_WLDRVX8 +XBUF<9> A<9> Z<9> VDD VSS / RSC_IHPSG13_WLDRVX8 +XBUF<8> A<8> Z<8> VDD VSS / RSC_IHPSG13_WLDRVX8 +XBUF<7> A<7> Z<7> VDD VSS / RSC_IHPSG13_WLDRVX8 +XBUF<6> A<6> Z<6> VDD VSS / RSC_IHPSG13_WLDRVX8 +XBUF<5> A<5> Z<5> VDD VSS / RSC_IHPSG13_WLDRVX8 +XBUF<4> A<4> Z<4> VDD VSS / RSC_IHPSG13_WLDRVX8 +XBUF<3> A<3> Z<3> VDD VSS / RSC_IHPSG13_WLDRVX8 +XBUF<2> A<2> Z<2> VDD VSS / RSC_IHPSG13_WLDRVX8 +XBUF<1> A<1> Z<1> VDD VSS / RSC_IHPSG13_WLDRVX8 +XBUF<0> A<0> Z<0> VDD VSS / RSC_IHPSG13_WLDRVX8 +.ENDS + + + +.SUBCKT RM_IHPSG13_512x32_c2_2P_COLDEC2 ACLK_N ADDR<1> ADDR<0> ADDR_COL<1> ADDR_COL<0> ++ ADDR_DEC<7> ADDR_DEC<6> ADDR_DEC<5> ADDR_DEC<4> ADDR_DEC<3> ADDR_DEC<2> ++ ADDR_DEC<1> ADDR_DEC<0> BIST_ADDR<1> BIST_ADDR<0> BIST_EN_I VDD VSS +XI16<17> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI16<16> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI16<15> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI16<14> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI16<13> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI16<12> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI16<11> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI16<10> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI16<9> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI16<8> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI16<7> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI16<6> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI16<5> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI16<4> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI16<3> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI16<2> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI16<1> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI18<24> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI18<23> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI18<22> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI18<21> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI18<20> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI18<19> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI18<18> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI18<17> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI18<16> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI18<15> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI18<14> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI18<13> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI18<12> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI18<11> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI18<10> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI18<9> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI18<8> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI18<7> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI18<6> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI18<5> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI18<4> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI18<3> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI18<2> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI18<1> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI1<3> PADR<0> PADR<1> addr_n<3> VDD VSS / RSC_IHPSG13_NAND2X2 +XI1<2> NADR<0> PADR<1> addr_n<2> VDD VSS / RSC_IHPSG13_NAND2X2 +XI1<1> PADR<0> NADR<1> addr_n<1> VDD VSS / RSC_IHPSG13_NAND2X2 +XI1<0> NADR<0> NADR<1> addr_n<0> VDD VSS / RSC_IHPSG13_NAND2X2 +XI17<1> ADDR_COL<1> VDD VSS / RSC_IHPSG13_TIEL +XI17<0> ADDR_COL<0> VDD VSS / RSC_IHPSG13_TIEL +XI14<3> ADDR_DEC<7> VDD VSS / RSC_IHPSG13_TIEL +XI14<2> ADDR_DEC<6> VDD VSS / RSC_IHPSG13_TIEL +XI14<1> ADDR_DEC<5> VDD VSS / RSC_IHPSG13_TIEL +XI14<0> ADDR_DEC<4> VDD VSS / RSC_IHPSG13_TIEL +XI13<1> NADR<1> PADR<1> VDD VSS / RSC_IHPSG13_INVX2 +XI13<0> NADR<0> PADR<0> VDD VSS / RSC_IHPSG13_INVX2 +XI3<1> padr_int<1> NADR<1> VDD VSS / RSC_IHPSG13_INVX2 +XI3<0> padr_int<0> NADR<0> VDD VSS / RSC_IHPSG13_INVX2 +XI2<3> addr_n<3> ADDR_DEC<3> VDD VSS / RSC_IHPSG13_INVX2 +XI2<2> addr_n<2> ADDR_DEC<2> VDD VSS / RSC_IHPSG13_INVX2 +XI2<1> addr_n<1> ADDR_DEC<1> VDD VSS / RSC_IHPSG13_INVX2 +XI2<0> addr_n<0> ADDR_DEC<0> VDD VSS / RSC_IHPSG13_INVX2 +XDFF<1> BIST_EN_I BIST_ADDR<1> ACLK_N ADDR<1> padr_int<1> net12<0> VDD ++ VSS / RSC_IHPSG13_DFNQMX2IX1 +XDFF<0> BIST_EN_I BIST_ADDR<0> ACLK_N ADDR<0> padr_int<0> net12<1> VDD ++ VSS / RSC_IHPSG13_DFNQMX2IX1 +XI15<5> VDD VSS / RSC_IHPSG13_FILLCAP4 +XI15<4> VDD VSS / RSC_IHPSG13_FILLCAP4 +XI15<3> VDD VSS / RSC_IHPSG13_FILLCAP4 +XI15<2> VDD VSS / RSC_IHPSG13_FILLCAP4 +XI15<1> VDD VSS / RSC_IHPSG13_FILLCAP4 +XI19<4> VDD VSS / RSC_IHPSG13_FILLCAP4 +XI19<3> VDD VSS / RSC_IHPSG13_FILLCAP4 +XI19<2> VDD VSS / RSC_IHPSG13_FILLCAP4 +XI19<1> VDD VSS / RSC_IHPSG13_FILLCAP4 +.ENDS +.SUBCKT RM_IHPSG13_512x32_c2_2P_COLCTRL2 A_ADDR_DEC<3> A_ADDR_DEC<2> A_ADDR_DEC<1> ++ A_ADDR_DEC<0> A_BIST_BM_I A_BIST_DW_I A_BIST_EN_I A_BLC<3> A_BLC<2> A_BLC<1> ++ A_BLC<0> A_BLT<3> A_BLT<2> A_BLT<1> A_BLT<0> A_BM_I A_DCLK_B_L A_DCLK_B_R ++ A_DCLK_L A_DCLK_R A_DR_O A_DW_I A_RCLK_B_L A_RCLK_B_R A_RCLK_L A_RCLK_R ++ A_TIEH_O A_WCLK_B_L A_WCLK_B_R A_WCLK_L A_WCLK_R B_ADDR_DEC<3> B_ADDR_DEC<2> ++ B_ADDR_DEC<1> B_ADDR_DEC<0> B_BIST_BM_I B_BIST_DW_I B_BIST_EN_I B_BLC<3> ++ B_BLC<2> B_BLC<1> B_BLC<0> B_BLT<3> B_BLT<2> B_BLT<1> B_BLT<0> B_BM_I ++ B_DCLK_B_L B_DCLK_B_R B_DCLK_L B_DCLK_R B_DR_O B_DW_I B_RCLK_B_L B_RCLK_B_R ++ B_RCLK_L B_RCLK_R B_TIEH_O B_WCLK_B_L B_WCLK_B_R B_WCLK_L B_WCLK_R VDD ++ VSS +XB_DREG B_BIST_EN_I B_BIST_DW_I B_DCLK_B_L B_DW_I B_DI_R net046 VDD ++ VSS / RSC_IHPSG13_DFNQMX2IX1 +XB_BREG B_BIST_EN_I B_BIST_BM_I B_DCLK_B_L B_BM_I B_BM_R net045 VDD ++ VSS / RSC_IHPSG13_DFNQMX2IX1 +XA_DREG A_BIST_EN_I A_BIST_DW_I A_DCLK_B_L A_DW_I A_DI_R net22 VDD VSS ++ / RSC_IHPSG13_DFNQMX2IX1 +XA_BREG A_BIST_EN_I A_BIST_BM_I A_DCLK_B_L A_BM_I A_BM_R net23 VDD VSS ++ / RSC_IHPSG13_DFNQMX2IX1 +XB_CAPS VDD VSS / RSC_IHPSG13_FILLCAP4 +XA_CAPS VDD VSS / RSC_IHPSG13_FILLCAP4 +XB_I75 B_DI_R B_DO_WRITE_P B_WR_ONE VDD VSS / RSC_IHPSG13_AND2X2 +XB_I80 B_RCLK_B_L B_WCLK_B_L net041 VDD VSS / RSC_IHPSG13_AND2X2 +XB_I76 B_DI_N B_DO_WRITE_P B_WR_ZERO VDD VSS / RSC_IHPSG13_AND2X2 +XA_I80 A_RCLK_B_L A_WCLK_B_L net21 VDD VSS / RSC_IHPSG13_AND2X2 +XA_I75 A_DI_R A_DO_WRITE_P A_WR_ONE VDD VSS / RSC_IHPSG13_AND2X2 +XA_I76 A_DI_N A_DO_WRITE_P A_WR_ZERO VDD VSS / RSC_IHPSG13_AND2X2 +XB_I44 B_WCLK_B_L B_BM_N B_DO_WRITE_P VDD VSS / RSC_IHPSG13_NOR2X2 +XA_I44 A_WCLK_B_L A_BM_N A_DO_WRITE_P VDD VSS / RSC_IHPSG13_NOR2X2 +XB_I81 net041 B_PRE_N VDD VSS / RSC_IHPSG13_CINVX4_WN +XA_I81 net21 A_PRE_N VDD VSS / RSC_IHPSG13_CINVX4_WN +XB_BM_TIEH B_TIEH_O VDD VSS / RSC_IHPSG13_TIEH +XA_BM_TIEH A_TIEH_O VDD VSS / RSC_IHPSG13_TIEH +XA_I89 A_DCLK_B_L A_DCLK_B_R / RSC_IHPSG13_MET3RES +XA_I88 A_DCLK_L A_DCLK_R / RSC_IHPSG13_MET3RES +XA_I87 A_WCLK_L A_WCLK_R / RSC_IHPSG13_MET3RES +XA_I91 A_RCLK_B_L A_RCLK_B_R / RSC_IHPSG13_MET3RES +XB_I87 B_WCLK_L B_WCLK_R / RSC_IHPSG13_MET3RES +XB_I88 B_DCLK_L B_DCLK_R / RSC_IHPSG13_MET3RES +XB_I89 B_DCLK_B_L B_DCLK_B_R / RSC_IHPSG13_MET3RES +XB_I90 B_WCLK_B_L B_WCLK_B_R / RSC_IHPSG13_MET3RES +XB_R2 B_RCLK_L B_RCLK_R / RSC_IHPSG13_MET3RES +XB_I91 B_RCLK_B_L B_RCLK_B_R / RSC_IHPSG13_MET3RES +XA_R2 A_RCLK_L A_RCLK_R / RSC_IHPSG13_MET3RES +XA_I90 A_WCLK_B_L A_WCLK_B_R / RSC_IHPSG13_MET3RES +XAB_BLMUX A_BLC<3> A_BLC<2> A_BLC<1> A_BLC<0> A_BLC_SEL A_BLT<3> A_BLT<2> ++ A_BLT<1> A_BLT<0> A_BLT_SEL A_PRE_N A_ADDR_DEC<3> A_ADDR_DEC<2> ++ A_ADDR_DEC<1> A_ADDR_DEC<0> A_WR_ONE A_WR_ZERO B_BLC<3> B_BLC<2> B_BLC<1> ++ B_BLC<0> B_BLC_SEL B_BLT<3> B_BLT<2> B_BLT<1> B_BLT<0> B_BLT_SEL B_PRE_N ++ B_ADDR_DEC<3> B_ADDR_DEC<2> B_ADDR_DEC<1> B_ADDR_DEC<0> B_WR_ONE B_WR_ZERO ++ VDD VSS / RM_IHPSG13_512x32_c2_2P_BLDRV +XB_ISENSE B_SAE B_BLC_SEL B_BLT_SEL net039 net040 VDD VSS / ++ RSC_IHPSG13_DFPQD_MSAFFX2 +XA_ISENSE A_SAE A_BLC_SEL A_BLT_SEL net19 net20 VDD VSS / ++ RSC_IHPSG13_DFPQD_MSAFFX2 +XB_I78 B_RCLK_B_L B_SAE VDD VSS / RSC_IHPSG13_CBUFX2 +XA_I78 A_RCLK_B_L A_SAE VDD VSS / RSC_IHPSG13_CBUFX2 +XB_I83 B_BM_R B_BM_N VDD VSS / RSC_IHPSG13_INVX2 +XB_I49 B_DI_R B_DI_N VDD VSS / RSC_IHPSG13_INVX2 +XA_I83 A_BM_R A_BM_N VDD VSS / RSC_IHPSG13_INVX2 +XA_I49 A_DI_R A_DI_N VDD VSS / RSC_IHPSG13_INVX2 +XB_I51 net039 B_DR_O VDD VSS / RSC_IHPSG13_INVX4 +XA_I51 net19 A_DR_O VDD VSS / RSC_IHPSG13_INVX4 +XA_I69 A_DCLK_L A_DCLK_B_L VDD VSS / RSC_IHPSG13_CINVX2 +XA_I50 A_WCLK_L A_WCLK_B_L VDD VSS / RSC_IHPSG13_CINVX2 +XA_EBUF A_RCLK_L A_RCLK_B_L VDD VSS / RSC_IHPSG13_CINVX2 +XB_EBUF B_RCLK_L B_RCLK_B_L VDD VSS / RSC_IHPSG13_CINVX2 +XB_I50 B_WCLK_L B_WCLK_B_L VDD VSS / RSC_IHPSG13_CINVX2 +XB_I69 B_DCLK_L B_DCLK_B_L VDD VSS / RSC_IHPSG13_CINVX2 +.ENDS +.SUBCKT RM_IHPSG13_512x32_c2_2P_COLDRV13_FILL4C2 VDD VSS +XI0<2> VDD VSS / RSC_IHPSG13_FILLCAP4 +XI0<1> VDD VSS / RSC_IHPSG13_FILLCAP4 +.ENDS + + +.SUBCKT RM_IHPSG13_512x32_c2_2P_ROWDEC7 ADDR_N_I<6> ADDR_N_I<5> ADDR_N_I<4> ADDR_N_I<3> ++ ADDR_N_I<2> ADDR_N_I<1> ADDR_N_I<0> CS_I ECLK_I WL_O<127> WL_O<126> ++ WL_O<125> WL_O<124> WL_O<123> WL_O<122> WL_O<121> WL_O<120> WL_O<119> ++ WL_O<118> WL_O<117> WL_O<116> WL_O<115> WL_O<114> WL_O<113> WL_O<112> ++ WL_O<111> WL_O<110> WL_O<109> WL_O<108> WL_O<107> WL_O<106> WL_O<105> ++ WL_O<104> WL_O<103> WL_O<102> WL_O<101> WL_O<100> WL_O<99> WL_O<98> WL_O<97> ++ WL_O<96> WL_O<95> WL_O<94> WL_O<93> WL_O<92> WL_O<91> WL_O<90> WL_O<89> ++ WL_O<88> WL_O<87> WL_O<86> WL_O<85> WL_O<84> WL_O<83> WL_O<82> WL_O<81> ++ WL_O<80> WL_O<79> WL_O<78> WL_O<77> WL_O<76> WL_O<75> WL_O<74> WL_O<73> ++ WL_O<72> WL_O<71> WL_O<70> WL_O<69> WL_O<68> WL_O<67> WL_O<66> WL_O<65> ++ WL_O<64> WL_O<63> WL_O<62> WL_O<61> WL_O<60> WL_O<59> WL_O<58> WL_O<57> ++ WL_O<56> WL_O<55> WL_O<54> WL_O<53> WL_O<52> WL_O<51> WL_O<50> WL_O<49> ++ WL_O<48> WL_O<47> WL_O<46> WL_O<45> WL_O<44> WL_O<43> WL_O<42> WL_O<41> ++ WL_O<40> WL_O<39> WL_O<38> WL_O<37> WL_O<36> WL_O<35> WL_O<34> WL_O<33> ++ WL_O<32> WL_O<31> WL_O<30> WL_O<29> WL_O<28> WL_O<27> WL_O<26> WL_O<25> ++ WL_O<24> WL_O<23> WL_O<22> WL_O<21> WL_O<20> WL_O<19> WL_O<18> WL_O<17> ++ WL_O<16> WL_O<15> WL_O<14> WL_O<13> WL_O<12> WL_O<11> WL_O<10> WL_O<9> ++ WL_O<8> WL_O<7> WL_O<6> WL_O<5> WL_O<4> WL_O<3> WL_O<2> WL_O<1> WL_O<0> ++ VDD VSS +XSEL<7> ADDR_N_I<3> ADDR_N_I<2> ADDR_N_I<1> ADDR_N_I<0> CS00<7> ECLK_H<7> ++ ECLK_H<8> ECLK_B<7> ECLK_B<8> WL_O<127> WL_O<126> WL_O<125> WL_O<124> ++ WL_O<123> WL_O<122> WL_O<121> WL_O<120> WL_O<119> WL_O<118> WL_O<117> ++ WL_O<116> WL_O<115> WL_O<114> WL_O<113> WL_O<112> VDD VSS / ++ RM_IHPSG13_512x32_c2_2P_DEC04 +XSEL<6> ADDR_N_I<3> ADDR_N_I<2> ADDR_N_I<1> ADDR_N_I<0> CS00<6> ECLK_H<6> ++ ECLK_H<7> ECLK_B<6> ECLK_B<7> WL_O<111> WL_O<110> WL_O<109> WL_O<108> ++ WL_O<107> WL_O<106> WL_O<105> WL_O<104> WL_O<103> WL_O<102> WL_O<101> ++ WL_O<100> WL_O<99> WL_O<98> WL_O<97> WL_O<96> VDD VSS / ++ RM_IHPSG13_512x32_c2_2P_DEC04 +XSEL<5> ADDR_N_I<3> ADDR_N_I<2> ADDR_N_I<1> ADDR_N_I<0> CS00<5> ECLK_H<5> ++ ECLK_H<6> ECLK_B<5> ECLK_B<6> WL_O<95> WL_O<94> WL_O<93> WL_O<92> WL_O<91> ++ WL_O<90> WL_O<89> WL_O<88> WL_O<87> WL_O<86> WL_O<85> WL_O<84> WL_O<83> ++ WL_O<82> WL_O<81> WL_O<80> VDD VSS / RM_IHPSG13_512x32_c2_2P_DEC04 +XSEL<4> ADDR_N_I<3> ADDR_N_I<2> ADDR_N_I<1> ADDR_N_I<0> CS00<4> ECLK_H<4> ++ ECLK_H<5> ECLK_B<4> ECLK_B<5> WL_O<79> WL_O<78> WL_O<77> WL_O<76> WL_O<75> ++ WL_O<74> WL_O<73> WL_O<72> WL_O<71> WL_O<70> WL_O<69> WL_O<68> WL_O<67> ++ WL_O<66> WL_O<65> WL_O<64> VDD VSS / RM_IHPSG13_512x32_c2_2P_DEC04 +XSEL<3> ADDR_N_I<3> ADDR_N_I<2> ADDR_N_I<1> ADDR_N_I<0> CS00<3> ECLK_H<3> ++ ECLK_H<4> ECLK_B<3> ECLK_B<4> WL_O<63> WL_O<62> WL_O<61> WL_O<60> WL_O<59> ++ WL_O<58> WL_O<57> WL_O<56> WL_O<55> WL_O<54> WL_O<53> WL_O<52> WL_O<51> ++ WL_O<50> WL_O<49> WL_O<48> VDD VSS / RM_IHPSG13_512x32_c2_2P_DEC04 +XSEL<2> ADDR_N_I<3> ADDR_N_I<2> ADDR_N_I<1> ADDR_N_I<0> CS00<2> ECLK_H<2> ++ ECLK_H<3> ECLK_B<2> ECLK_B<3> WL_O<47> WL_O<46> WL_O<45> WL_O<44> WL_O<43> ++ WL_O<42> WL_O<41> WL_O<40> WL_O<39> WL_O<38> WL_O<37> WL_O<36> WL_O<35> ++ WL_O<34> WL_O<33> WL_O<32> VDD VSS / RM_IHPSG13_512x32_c2_2P_DEC04 +XSEL<1> ADDR_N_I<3> ADDR_N_I<2> ADDR_N_I<1> ADDR_N_I<0> CS00<1> ECLK_H<1> ++ ECLK_H<2> ECLK_B<1> ECLK_B<2> WL_O<31> WL_O<30> WL_O<29> WL_O<28> WL_O<27> ++ WL_O<26> WL_O<25> WL_O<24> WL_O<23> WL_O<22> WL_O<21> WL_O<20> WL_O<19> ++ WL_O<18> WL_O<17> WL_O<16> VDD VSS / RM_IHPSG13_512x32_c2_2P_DEC04 +XSEL<0> ADDR_N_I<3> ADDR_N_I<2> ADDR_N_I<1> ADDR_N_I<0> CS00<0> ECLK_I ++ ECLK_H<1> ECLK_B<0> ECLK_B<1> WL_O<15> WL_O<14> WL_O<13> WL_O<12> WL_O<11> ++ WL_O<10> WL_O<9> WL_O<8> WL_O<7> WL_O<6> WL_O<5> WL_O<4> WL_O<3> WL_O<2> ++ WL_O<1> WL_O<0> VDD VSS / RM_IHPSG13_512x32_c2_2P_DEC04 +XDEC11<1> ADDR_N_I<5> ADDR_N_I<4> CS04<1> CS00<7> VDD VSS / ++ RM_IHPSG13_512x32_c2_2P_DEC03 +XDEC11<0> ADDR_N_I<5> ADDR_N_I<4> CS04<0> CS00<3> VDD VSS / ++ RM_IHPSG13_512x32_c2_2P_DEC03 +XDEC01<2> ADDR_N_I<7> ADDR_N_I<6> CS_I CS04<1> VDD VSS / ++ RM_IHPSG13_512x32_c2_2P_DEC01 +XDEC01<1> ADDR_N_I<5> ADDR_N_I<4> CS04<1> CS00<5> VDD VSS / ++ RM_IHPSG13_512x32_c2_2P_DEC01 +XDEC01<0> ADDR_N_I<5> ADDR_N_I<4> CS04<0> CS00<1> VDD VSS / ++ RM_IHPSG13_512x32_c2_2P_DEC01 +XL2<66> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<65> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<64> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<63> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<62> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<61> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<60> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<59> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<58> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<57> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<56> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<55> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<54> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<53> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<52> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<51> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<50> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<49> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<48> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<47> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<46> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<45> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<44> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<43> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<42> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<41> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<40> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<39> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<38> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<37> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<36> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<35> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<34> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<33> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<32> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<31> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<30> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<29> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<28> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<27> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<26> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<25> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<24> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<23> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<22> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<21> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<20> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<19> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<18> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<17> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<16> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<15> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<14> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<13> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<12> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<11> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<10> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<9> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<8> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<7> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<6> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<5> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<4> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<3> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<2> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<1> VDD VSS / RSC_IHPSG13_FILLCAP8 +XDEC10<1> ADDR_N_I<5> ADDR_N_I<4> CS04<1> CS00<6> VDD VSS / ++ RM_IHPSG13_512x32_c2_2P_DEC02 +XDEC10<0> ADDR_N_I<5> ADDR_N_I<4> CS04<0> CS00<2> VDD VSS / ++ RM_IHPSG13_512x32_c2_2P_DEC02 +XDEC00<2> ADDR_N_I<7> ADDR_N_I<6> CS_I CS04<0> VDD VSS / ++ RM_IHPSG13_512x32_c2_2P_DEC00 +XDEC00<1> ADDR_N_I<5> ADDR_N_I<4> CS04<1> CS00<4> VDD VSS / ++ RM_IHPSG13_512x32_c2_2P_DEC00 +XDEC00<0> ADDR_N_I<5> ADDR_N_I<4> CS04<0> CS00<0> VDD VSS / ++ RM_IHPSG13_512x32_c2_2P_DEC00 +XI0 ADDR_N_I<7> VDD VSS / RSC_IHPSG13_TIEL +.ENDS +.SUBCKT RM_IHPSG13_512x32_c2_2P_ROWREG7 ACLK_N_I ADDR_I<6> ADDR_I<5> ADDR_I<4> ADDR_I<3> ++ ADDR_I<2> ADDR_I<1> ADDR_I<0> ADDR_N_O<6> ADDR_N_O<5> ADDR_N_O<4> ++ ADDR_N_O<3> ADDR_N_O<2> ADDR_N_O<1> ADDR_N_O<0> BIST_ADDR_I<6> ++ BIST_ADDR_I<5> BIST_ADDR_I<4> BIST_ADDR_I<3> BIST_ADDR_I<2> BIST_ADDR_I<1> ++ BIST_ADDR_I<0> BIST_EN_I VDD VSS +XINV<6> q_int<6> qn_int<6> VDD VSS / RSC_IHPSG13_CINVX2 +XINV<5> q_int<5> qn_int<5> VDD VSS / RSC_IHPSG13_CINVX2 +XINV<4> q_int<4> qn_int<4> VDD VSS / RSC_IHPSG13_CINVX2 +XINV<3> q_int<3> qn_int<3> VDD VSS / RSC_IHPSG13_CINVX2 +XINV<2> q_int<2> qn_int<2> VDD VSS / RSC_IHPSG13_CINVX2 +XINV<1> q_int<1> qn_int<1> VDD VSS / RSC_IHPSG13_CINVX2 +XINV<0> q_int<0> qn_int<0> VDD VSS / RSC_IHPSG13_CINVX2 +XDRV<6> qn_int<6> ADDR_N_O<6> VDD VSS / RSC_IHPSG13_CINVX8 +XDRV<5> qn_int<5> ADDR_N_O<5> VDD VSS / RSC_IHPSG13_CINVX8 +XDRV<4> qn_int<4> ADDR_N_O<4> VDD VSS / RSC_IHPSG13_CINVX8 +XDRV<3> qn_int<3> ADDR_N_O<3> VDD VSS / RSC_IHPSG13_CINVX8 +XDRV<2> qn_int<2> ADDR_N_O<2> VDD VSS / RSC_IHPSG13_CINVX8 +XDRV<1> qn_int<1> ADDR_N_O<1> VDD VSS / RSC_IHPSG13_CINVX8 +XDRV<0> qn_int<0> ADDR_N_O<0> VDD VSS / RSC_IHPSG13_CINVX8 +XDFF<6> BIST_EN_I BIST_ADDR_I<6> ACLK_N_I ADDR_I<6> q_int<6> net2<0> VDD ++ VSS / RSC_IHPSG13_DFNQMX2IX1 +XDFF<5> BIST_EN_I BIST_ADDR_I<5> ACLK_N_I ADDR_I<5> q_int<5> net2<1> VDD ++ VSS / RSC_IHPSG13_DFNQMX2IX1 +XDFF<4> BIST_EN_I BIST_ADDR_I<4> ACLK_N_I ADDR_I<4> q_int<4> net2<2> VDD ++ VSS / RSC_IHPSG13_DFNQMX2IX1 +XDFF<3> BIST_EN_I BIST_ADDR_I<3> ACLK_N_I ADDR_I<3> q_int<3> net2<3> VDD ++ VSS / RSC_IHPSG13_DFNQMX2IX1 +XDFF<2> BIST_EN_I BIST_ADDR_I<2> ACLK_N_I ADDR_I<2> q_int<2> net2<4> VDD ++ VSS / RSC_IHPSG13_DFNQMX2IX1 +XDFF<1> BIST_EN_I BIST_ADDR_I<1> ACLK_N_I ADDR_I<1> q_int<1> net2<5> VDD ++ VSS / RSC_IHPSG13_DFNQMX2IX1 +XDFF<0> BIST_EN_I BIST_ADDR_I<0> ACLK_N_I ADDR_I<0> q_int<0> net2<6> VDD ++ VSS / RSC_IHPSG13_DFNQMX2IX1 +XI11<7> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI11<6> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI11<5> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI11<4> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI11<3> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI11<2> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI11<1> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI11<0> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI12<1> VDD VSS / RSC_IHPSG13_FILLCAP4 +XI12<0> VDD VSS / RSC_IHPSG13_FILLCAP4 +.ENDS + +.SUBCKT RM_IHPSG13_512x32_c2_2P_ROWDEC4 ADDR_N_I<3> ADDR_N_I<2> ADDR_N_I<1> ADDR_N_I<0> ++ CS_I ECLK_I WL_O<15> WL_O<14> WL_O<13> WL_O<12> WL_O<11> WL_O<10> WL_O<9> ++ WL_O<8> WL_O<7> WL_O<6> WL_O<5> WL_O<4> WL_O<3> WL_O<2> WL_O<1> WL_O<0> ++ VDD VSS +XL2<12> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<11> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<10> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<9> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<8> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<7> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<6> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<5> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<4> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<3> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<2> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<1> VDD VSS / RSC_IHPSG13_FILLCAP8 +XSEL ADDR_N_I<3> ADDR_N_I<2> ADDR_N_I<1> ADDR_N_I<0> CS_I ECLK_I ECLK_H<1> ++ ECLK_B<0> ECLK_B<1> WL_O<15> WL_O<14> WL_O<13> WL_O<12> WL_O<11> WL_O<10> ++ WL_O<9> WL_O<8> WL_O<7> WL_O<6> WL_O<5> WL_O<4> WL_O<3> WL_O<2> WL_O<1> ++ WL_O<0> VDD VSS / RM_IHPSG13_512x32_c2_2P_DEC04 +.ENDS +.SUBCKT RM_IHPSG13_512x32_c2_2P_ROWREG4 ACLK_N_I ADDR_I<3> ADDR_I<2> ADDR_I<1> ADDR_I<0> ++ ADDR_N_O<3> ADDR_N_O<2> ADDR_N_O<1> ADDR_N_O<0> BIST_ADDR_I<3> ++ BIST_ADDR_I<2> BIST_ADDR_I<1> BIST_ADDR_I<0> BIST_EN_I VDD VSS +XINV<3> q_int<3> qn_int<3> VDD VSS / RSC_IHPSG13_CINVX2 +XINV<2> q_int<2> qn_int<2> VDD VSS / RSC_IHPSG13_CINVX2 +XINV<1> q_int<1> qn_int<1> VDD VSS / RSC_IHPSG13_CINVX2 +XINV<0> q_int<0> qn_int<0> VDD VSS / RSC_IHPSG13_CINVX2 +XDRV<3> qn_int<3> ADDR_N_O<3> VDD VSS / RSC_IHPSG13_CINVX8 +XDRV<2> qn_int<2> ADDR_N_O<2> VDD VSS / RSC_IHPSG13_CINVX8 +XDRV<1> qn_int<1> ADDR_N_O<1> VDD VSS / RSC_IHPSG13_CINVX8 +XDRV<0> qn_int<0> ADDR_N_O<0> VDD VSS / RSC_IHPSG13_CINVX8 +XDFF<3> BIST_EN_I BIST_ADDR_I<3> ACLK_N_I ADDR_I<3> q_int<3> net7<0> VDD ++ VSS / RSC_IHPSG13_DFNQMX2IX1 +XDFF<2> BIST_EN_I BIST_ADDR_I<2> ACLK_N_I ADDR_I<2> q_int<2> net7<1> VDD ++ VSS / RSC_IHPSG13_DFNQMX2IX1 +XDFF<1> BIST_EN_I BIST_ADDR_I<1> ACLK_N_I ADDR_I<1> q_int<1> net7<2> VDD ++ VSS / RSC_IHPSG13_DFNQMX2IX1 +XDFF<0> BIST_EN_I BIST_ADDR_I<0> ACLK_N_I ADDR_I<0> q_int<0> net7<3> VDD ++ VSS / RSC_IHPSG13_DFNQMX2IX1 +XI11<20> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI11<19> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI11<18> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI11<17> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI11<16> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI11<15> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI11<14> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI11<13> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI11<12> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI11<11> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI11<10> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI11<9> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI11<8> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI11<7> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI11<6> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI11<5> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI11<4> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI11<3> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI11<2> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI11<1> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI12<4> VDD VSS / RSC_IHPSG13_FILLCAP4 +XI12<3> VDD VSS / RSC_IHPSG13_FILLCAP4 +XI12<2> VDD VSS / RSC_IHPSG13_FILLCAP4 +XI12<1> VDD VSS / RSC_IHPSG13_FILLCAP4 +XI12<0> VDD VSS / RSC_IHPSG13_FILLCAP4 +.ENDS + + +.SUBCKT RM_IHPSG13_512x32_c2_1P_BITKIT_TAP BLC BLT NW PW VDD VSS +.ENDS +.SUBCKT RM_IHPSG13_512x32_c2_1P_BITKIT_16x2_TAP A_BLC<1> A_BLC<0> A_BLT<1> A_BLT<0> ++ VDD_CORE VSS +XITAP<1> A_BLC<1> A_BLT<1> VDD_CORE VSS VDD_CORE VSS ++ / RM_IHPSG13_512x32_c2_1P_BITKIT_TAP +XITAP<0> A_BLC<0> A_BLT<0> VDD_CORE VSS VDD_CORE VSS ++ / RM_IHPSG13_512x32_c2_1P_BITKIT_TAP +XIEDGEBP_COL1<1> BLC<1> BLT<1> VDD_CORE VSS VDD_CORE ++ VSS / RM_IHPSG13_512x32_c2_1P_BITKIT_EDGE_TB +XIEDGEBP_COL1<0> BLC<1> BLT<1> VDD_CORE VSS VDD_CORE ++ VSS / RM_IHPSG13_512x32_c2_1P_BITKIT_EDGE_TB +XIEDGEBP_COL2<1> BLC<0> BLT<0> VDD_CORE VSS VDD_CORE ++ VSS / RM_IHPSG13_512x32_c2_1P_BITKIT_EDGE_TB +XIEDGEBP_COL2<0> BLC<0> BLT<0> VDD_CORE VSS VDD_CORE ++ VSS / RM_IHPSG13_512x32_c2_1P_BITKIT_EDGE_TB +.ENDS +.SUBCKT RM_IHPSG13_512x32_c2_1P_BITKIT_16x2_TAP_LR VDD_CORE VSS +XCORNER<1> VDD_CORE VSS VDD_CORE VSS / ++ RM_IHPSG13_512x32_c2_1P_BITKIT_CORNER +XCORNER<0> VDD_CORE VSS VDD_CORE VSS / ++ RM_IHPSG13_512x32_c2_1P_BITKIT_CORNER +XTAP_BORDER VDD_CORE VSS VDD_CORE VSS / ++ RM_IHPSG13_512x32_c2_1P_BITKIT_TAP_LR +.ENDS +.SUBCKT RM_IHPSG13_512x32_c2_1P_DEC03 ADDR<1> ADDR<0> CS CS_OUT VDD VSS +XDECINV net1 CS_OUT VDD VSS / RSC_IHPSG13_INVX4 +XI0 VDD VSS / RSC_IHPSG13_FILLCAP4 +XDEC ADDR<1> ADDR<0> CS net1 VDD VSS / RSC_IHPSG13_NAND3X2 +.ENDS +.SUBCKT RM_IHPSG13_512x32_c2_1P_DEC02 ADDR<1> ADDR<0> CS CS_OUT VDD VSS +XDECINV net1 CS_OUT VDD VSS / RSC_IHPSG13_INVX4 +XDEC ADDR<1> NADDR<0> CS net1 VDD VSS / RSC_IHPSG13_NAND3X2 +XI2 VDD VSS / RSC_IHPSG13_FILLCAP4 +XADDRINV ADDR<0> NADDR<0> VDD VSS / RSC_IHPSG13_INVX2 +.ENDS +.SUBCKT RM_IHPSG13_512x32_c2_1P_ROWDEC8 ADDR_N_I<7> ADDR_N_I<6> ADDR_N_I<5> ADDR_N_I<4> ++ ADDR_N_I<3> ADDR_N_I<2> ADDR_N_I<1> ADDR_N_I<0> CS_I ECLK_I WL_O<255> ++ WL_O<254> WL_O<253> WL_O<252> WL_O<251> WL_O<250> WL_O<249> WL_O<248> ++ WL_O<247> WL_O<246> WL_O<245> WL_O<244> WL_O<243> WL_O<242> WL_O<241> ++ WL_O<240> WL_O<239> WL_O<238> WL_O<237> WL_O<236> WL_O<235> WL_O<234> ++ WL_O<233> WL_O<232> WL_O<231> WL_O<230> WL_O<229> WL_O<228> WL_O<227> ++ WL_O<226> WL_O<225> WL_O<224> WL_O<223> WL_O<222> WL_O<221> WL_O<220> ++ WL_O<219> WL_O<218> WL_O<217> WL_O<216> WL_O<215> WL_O<214> WL_O<213> ++ WL_O<212> WL_O<211> WL_O<210> WL_O<209> WL_O<208> WL_O<207> WL_O<206> ++ WL_O<205> WL_O<204> WL_O<203> WL_O<202> WL_O<201> WL_O<200> WL_O<199> ++ WL_O<198> WL_O<197> WL_O<196> WL_O<195> WL_O<194> WL_O<193> WL_O<192> ++ WL_O<191> WL_O<190> WL_O<189> WL_O<188> WL_O<187> WL_O<186> WL_O<185> ++ WL_O<184> WL_O<183> WL_O<182> WL_O<181> WL_O<180> WL_O<179> WL_O<178> ++ WL_O<177> WL_O<176> WL_O<175> WL_O<174> WL_O<173> WL_O<172> WL_O<171> ++ WL_O<170> WL_O<169> WL_O<168> WL_O<167> WL_O<166> WL_O<165> WL_O<164> ++ WL_O<163> WL_O<162> WL_O<161> WL_O<160> WL_O<159> WL_O<158> WL_O<157> ++ WL_O<156> WL_O<155> WL_O<154> WL_O<153> WL_O<152> WL_O<151> WL_O<150> ++ WL_O<149> WL_O<148> WL_O<147> WL_O<146> WL_O<145> WL_O<144> WL_O<143> ++ WL_O<142> WL_O<141> WL_O<140> WL_O<139> WL_O<138> WL_O<137> WL_O<136> ++ WL_O<135> WL_O<134> WL_O<133> WL_O<132> WL_O<131> WL_O<130> WL_O<129> ++ WL_O<128> WL_O<127> WL_O<126> WL_O<125> WL_O<124> WL_O<123> WL_O<122> ++ WL_O<121> WL_O<120> WL_O<119> WL_O<118> WL_O<117> WL_O<116> WL_O<115> ++ WL_O<114> WL_O<113> WL_O<112> WL_O<111> WL_O<110> WL_O<109> WL_O<108> ++ WL_O<107> WL_O<106> WL_O<105> WL_O<104> WL_O<103> WL_O<102> WL_O<101> ++ WL_O<100> WL_O<99> WL_O<98> WL_O<97> WL_O<96> WL_O<95> WL_O<94> WL_O<93> ++ WL_O<92> WL_O<91> WL_O<90> WL_O<89> WL_O<88> WL_O<87> WL_O<86> WL_O<85> ++ WL_O<84> WL_O<83> WL_O<82> WL_O<81> WL_O<80> WL_O<79> WL_O<78> WL_O<77> ++ WL_O<76> WL_O<75> WL_O<74> WL_O<73> WL_O<72> WL_O<71> WL_O<70> WL_O<69> ++ WL_O<68> WL_O<67> WL_O<66> WL_O<65> WL_O<64> WL_O<63> WL_O<62> WL_O<61> ++ WL_O<60> WL_O<59> WL_O<58> WL_O<57> WL_O<56> WL_O<55> WL_O<54> WL_O<53> ++ WL_O<52> WL_O<51> WL_O<50> WL_O<49> WL_O<48> WL_O<47> WL_O<46> WL_O<45> ++ WL_O<44> WL_O<43> WL_O<42> WL_O<41> WL_O<40> WL_O<39> WL_O<38> WL_O<37> ++ WL_O<36> WL_O<35> WL_O<34> WL_O<33> WL_O<32> WL_O<31> WL_O<30> WL_O<29> ++ WL_O<28> WL_O<27> WL_O<26> WL_O<25> WL_O<24> WL_O<23> WL_O<22> WL_O<21> ++ WL_O<20> WL_O<19> WL_O<18> WL_O<17> WL_O<16> WL_O<15> WL_O<14> WL_O<13> ++ WL_O<12> WL_O<11> WL_O<10> WL_O<9> WL_O<8> WL_O<7> WL_O<6> WL_O<5> WL_O<4> ++ WL_O<3> WL_O<2> WL_O<1> WL_O<0> VDD VSS +XDEC11<4> ADDR_N_I<7> ADDR_N_I<6> CS_I CS04<3> VDD VSS / ++ RM_IHPSG13_512x32_c2_1P_DEC03 +XDEC11<3> ADDR_N_I<5> ADDR_N_I<4> CS04<3> CS00<15> VDD VSS / ++ RM_IHPSG13_512x32_c2_1P_DEC03 +XDEC11<2> ADDR_N_I<5> ADDR_N_I<4> CS04<2> CS00<11> VDD VSS / ++ RM_IHPSG13_512x32_c2_1P_DEC03 +XDEC11<1> ADDR_N_I<5> ADDR_N_I<4> CS04<1> CS00<7> VDD VSS / ++ RM_IHPSG13_512x32_c2_1P_DEC03 +XDEC11<0> ADDR_N_I<5> ADDR_N_I<4> CS04<0> CS00<3> VDD VSS / ++ RM_IHPSG13_512x32_c2_1P_DEC03 +XL2<88> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<87> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<86> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<85> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<84> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<83> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<82> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<81> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<80> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<79> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<78> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<77> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<76> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<75> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<74> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<73> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<72> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<71> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<70> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<69> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<68> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<67> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<66> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<65> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<64> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<63> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<62> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<61> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<60> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<59> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<58> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<57> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<56> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<55> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<54> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<53> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<52> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<51> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<50> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<49> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<48> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<47> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<46> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<45> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<44> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<43> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<42> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<41> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<40> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<39> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<38> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<37> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<36> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<35> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<34> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<33> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<32> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<31> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<30> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<29> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<28> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<27> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<26> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<25> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<24> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<23> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<22> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<21> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<20> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<19> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<18> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<17> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<16> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<15> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<14> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<13> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<12> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<11> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<10> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<9> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<8> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<7> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<6> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<5> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<4> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<3> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<2> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<1> VDD VSS / RSC_IHPSG13_FILLCAP8 +XDEC10<4> ADDR_N_I<7> ADDR_N_I<6> CS_I CS04<2> VDD VSS / ++ RM_IHPSG13_512x32_c2_1P_DEC02 +XDEC10<3> ADDR_N_I<5> ADDR_N_I<4> CS04<3> CS00<14> VDD VSS / ++ RM_IHPSG13_512x32_c2_1P_DEC02 +XDEC10<2> ADDR_N_I<5> ADDR_N_I<4> CS04<2> CS00<10> VDD VSS / ++ RM_IHPSG13_512x32_c2_1P_DEC02 +XDEC10<1> ADDR_N_I<5> ADDR_N_I<4> CS04<1> CS00<6> VDD VSS / ++ RM_IHPSG13_512x32_c2_1P_DEC02 +XDEC10<0> ADDR_N_I<5> ADDR_N_I<4> CS04<0> CS00<2> VDD VSS / ++ RM_IHPSG13_512x32_c2_1P_DEC02 +XDEC00<4> ADDR_N_I<7> ADDR_N_I<6> CS_I CS04<0> VDD VSS / ++ RM_IHPSG13_512x32_c2_1P_DEC00 +XDEC00<3> ADDR_N_I<5> ADDR_N_I<4> CS04<3> CS00<12> VDD VSS / ++ RM_IHPSG13_512x32_c2_1P_DEC00 +XDEC00<2> ADDR_N_I<5> ADDR_N_I<4> CS04<2> CS00<8> VDD VSS / ++ RM_IHPSG13_512x32_c2_1P_DEC00 +XDEC00<1> ADDR_N_I<5> ADDR_N_I<4> CS04<1> CS00<4> VDD VSS / ++ RM_IHPSG13_512x32_c2_1P_DEC00 +XDEC00<0> ADDR_N_I<5> ADDR_N_I<4> CS04<0> CS00<0> VDD VSS / ++ RM_IHPSG13_512x32_c2_1P_DEC00 +XSEL<15> ADDR_N_I<3> ADDR_N_I<2> ADDR_N_I<1> ADDR_N_I<0> CS00<15> ECLK_H<15> ++ ECLK_H<16> ECLK_B<15> ECLK_B<16> WL_O<255> WL_O<254> WL_O<253> WL_O<252> ++ WL_O<251> WL_O<250> WL_O<249> WL_O<248> WL_O<247> WL_O<246> WL_O<245> ++ WL_O<244> WL_O<243> WL_O<242> WL_O<241> WL_O<240> VDD VSS / ++ RM_IHPSG13_512x32_c2_1P_DEC04 +XSEL<14> ADDR_N_I<3> ADDR_N_I<2> ADDR_N_I<1> ADDR_N_I<0> CS00<14> ECLK_H<14> ++ ECLK_H<15> ECLK_B<14> ECLK_B<15> WL_O<239> WL_O<238> WL_O<237> WL_O<236> ++ WL_O<235> WL_O<234> WL_O<233> WL_O<232> WL_O<231> WL_O<230> WL_O<229> ++ WL_O<228> WL_O<227> WL_O<226> WL_O<225> WL_O<224> VDD VSS / ++ RM_IHPSG13_512x32_c2_1P_DEC04 +XSEL<13> ADDR_N_I<3> ADDR_N_I<2> ADDR_N_I<1> ADDR_N_I<0> CS00<13> ECLK_H<13> ++ ECLK_H<14> ECLK_B<13> ECLK_B<14> WL_O<223> WL_O<222> WL_O<221> WL_O<220> ++ WL_O<219> WL_O<218> WL_O<217> WL_O<216> WL_O<215> WL_O<214> WL_O<213> ++ WL_O<212> WL_O<211> WL_O<210> WL_O<209> WL_O<208> VDD VSS / ++ RM_IHPSG13_512x32_c2_1P_DEC04 +XSEL<12> ADDR_N_I<3> ADDR_N_I<2> ADDR_N_I<1> ADDR_N_I<0> CS00<12> ECLK_H<12> ++ ECLK_H<13> ECLK_B<12> ECLK_B<13> WL_O<207> WL_O<206> WL_O<205> WL_O<204> ++ WL_O<203> WL_O<202> WL_O<201> WL_O<200> WL_O<199> WL_O<198> WL_O<197> ++ WL_O<196> WL_O<195> WL_O<194> WL_O<193> WL_O<192> VDD VSS / ++ RM_IHPSG13_512x32_c2_1P_DEC04 +XSEL<11> ADDR_N_I<3> ADDR_N_I<2> ADDR_N_I<1> ADDR_N_I<0> CS00<11> ECLK_H<11> ++ ECLK_H<12> ECLK_B<11> ECLK_B<12> WL_O<191> WL_O<190> WL_O<189> WL_O<188> ++ WL_O<187> WL_O<186> WL_O<185> WL_O<184> WL_O<183> WL_O<182> WL_O<181> ++ WL_O<180> WL_O<179> WL_O<178> WL_O<177> WL_O<176> VDD VSS / ++ RM_IHPSG13_512x32_c2_1P_DEC04 +XSEL<10> ADDR_N_I<3> ADDR_N_I<2> ADDR_N_I<1> ADDR_N_I<0> CS00<10> ECLK_H<10> ++ ECLK_H<11> ECLK_B<10> ECLK_B<11> WL_O<175> WL_O<174> WL_O<173> WL_O<172> ++ WL_O<171> WL_O<170> WL_O<169> WL_O<168> WL_O<167> WL_O<166> WL_O<165> ++ WL_O<164> WL_O<163> WL_O<162> WL_O<161> WL_O<160> VDD VSS / ++ RM_IHPSG13_512x32_c2_1P_DEC04 +XSEL<9> ADDR_N_I<3> ADDR_N_I<2> ADDR_N_I<1> ADDR_N_I<0> CS00<9> ECLK_H<9> ++ ECLK_H<10> ECLK_B<9> ECLK_B<10> WL_O<159> WL_O<158> WL_O<157> WL_O<156> ++ WL_O<155> WL_O<154> WL_O<153> WL_O<152> WL_O<151> WL_O<150> WL_O<149> ++ WL_O<148> WL_O<147> WL_O<146> WL_O<145> WL_O<144> VDD VSS / ++ RM_IHPSG13_512x32_c2_1P_DEC04 +XSEL<8> ADDR_N_I<3> ADDR_N_I<2> ADDR_N_I<1> ADDR_N_I<0> CS00<8> ECLK_H<8> ++ ECLK_H<9> ECLK_B<8> ECLK_B<9> WL_O<143> WL_O<142> WL_O<141> WL_O<140> ++ WL_O<139> WL_O<138> WL_O<137> WL_O<136> WL_O<135> WL_O<134> WL_O<133> ++ WL_O<132> WL_O<131> WL_O<130> WL_O<129> WL_O<128> VDD VSS / ++ RM_IHPSG13_512x32_c2_1P_DEC04 +XSEL<7> ADDR_N_I<3> ADDR_N_I<2> ADDR_N_I<1> ADDR_N_I<0> CS00<7> ECLK_H<7> ++ ECLK_H<8> ECLK_B<7> ECLK_B<8> WL_O<127> WL_O<126> WL_O<125> WL_O<124> ++ WL_O<123> WL_O<122> WL_O<121> WL_O<120> WL_O<119> WL_O<118> WL_O<117> ++ WL_O<116> WL_O<115> WL_O<114> WL_O<113> WL_O<112> VDD VSS / ++ RM_IHPSG13_512x32_c2_1P_DEC04 +XSEL<6> ADDR_N_I<3> ADDR_N_I<2> ADDR_N_I<1> ADDR_N_I<0> CS00<6> ECLK_H<6> ++ ECLK_H<7> ECLK_B<6> ECLK_B<7> WL_O<111> WL_O<110> WL_O<109> WL_O<108> ++ WL_O<107> WL_O<106> WL_O<105> WL_O<104> WL_O<103> WL_O<102> WL_O<101> ++ WL_O<100> WL_O<99> WL_O<98> WL_O<97> WL_O<96> VDD VSS / ++ RM_IHPSG13_512x32_c2_1P_DEC04 +XSEL<5> ADDR_N_I<3> ADDR_N_I<2> ADDR_N_I<1> ADDR_N_I<0> CS00<5> ECLK_H<5> ++ ECLK_H<6> ECLK_B<5> ECLK_B<6> WL_O<95> WL_O<94> WL_O<93> WL_O<92> WL_O<91> ++ WL_O<90> WL_O<89> WL_O<88> WL_O<87> WL_O<86> WL_O<85> WL_O<84> WL_O<83> ++ WL_O<82> WL_O<81> WL_O<80> VDD VSS / RM_IHPSG13_512x32_c2_1P_DEC04 +XSEL<4> ADDR_N_I<3> ADDR_N_I<2> ADDR_N_I<1> ADDR_N_I<0> CS00<4> ECLK_H<4> ++ ECLK_H<5> ECLK_B<4> ECLK_B<5> WL_O<79> WL_O<78> WL_O<77> WL_O<76> WL_O<75> ++ WL_O<74> WL_O<73> WL_O<72> WL_O<71> WL_O<70> WL_O<69> WL_O<68> WL_O<67> ++ WL_O<66> WL_O<65> WL_O<64> VDD VSS / RM_IHPSG13_512x32_c2_1P_DEC04 +XSEL<3> ADDR_N_I<3> ADDR_N_I<2> ADDR_N_I<1> ADDR_N_I<0> CS00<3> ECLK_H<3> ++ ECLK_H<4> ECLK_B<3> ECLK_B<4> WL_O<63> WL_O<62> WL_O<61> WL_O<60> WL_O<59> ++ WL_O<58> WL_O<57> WL_O<56> WL_O<55> WL_O<54> WL_O<53> WL_O<52> WL_O<51> ++ WL_O<50> WL_O<49> WL_O<48> VDD VSS / RM_IHPSG13_512x32_c2_1P_DEC04 +XSEL<2> ADDR_N_I<3> ADDR_N_I<2> ADDR_N_I<1> ADDR_N_I<0> CS00<2> ECLK_H<2> ++ ECLK_H<3> ECLK_B<2> ECLK_B<3> WL_O<47> WL_O<46> WL_O<45> WL_O<44> WL_O<43> ++ WL_O<42> WL_O<41> WL_O<40> WL_O<39> WL_O<38> WL_O<37> WL_O<36> WL_O<35> ++ WL_O<34> WL_O<33> WL_O<32> VDD VSS / RM_IHPSG13_512x32_c2_1P_DEC04 +XSEL<1> ADDR_N_I<3> ADDR_N_I<2> ADDR_N_I<1> ADDR_N_I<0> CS00<1> ECLK_H<1> ++ ECLK_H<2> ECLK_B<1> ECLK_B<2> WL_O<31> WL_O<30> WL_O<29> WL_O<28> WL_O<27> ++ WL_O<26> WL_O<25> WL_O<24> WL_O<23> WL_O<22> WL_O<21> WL_O<20> WL_O<19> ++ WL_O<18> WL_O<17> WL_O<16> VDD VSS / RM_IHPSG13_512x32_c2_1P_DEC04 +XSEL<0> ADDR_N_I<3> ADDR_N_I<2> ADDR_N_I<1> ADDR_N_I<0> CS00<0> ECLK_I ++ ECLK_H<1> ECLK_B<0> ECLK_B<1> WL_O<15> WL_O<14> WL_O<13> WL_O<12> WL_O<11> ++ WL_O<10> WL_O<9> WL_O<8> WL_O<7> WL_O<6> WL_O<5> WL_O<4> WL_O<3> WL_O<2> ++ WL_O<1> WL_O<0> VDD VSS / RM_IHPSG13_512x32_c2_1P_DEC04 +XDEC01<4> ADDR_N_I<7> ADDR_N_I<6> CS_I CS04<1> VDD VSS / ++ RM_IHPSG13_512x32_c2_1P_DEC01 +XDEC01<3> ADDR_N_I<5> ADDR_N_I<4> CS04<3> CS00<13> VDD VSS / ++ RM_IHPSG13_512x32_c2_1P_DEC01 +XDEC01<2> ADDR_N_I<5> ADDR_N_I<4> CS04<2> CS00<9> VDD VSS / ++ RM_IHPSG13_512x32_c2_1P_DEC01 +XDEC01<1> ADDR_N_I<5> ADDR_N_I<4> CS04<1> CS00<5> VDD VSS / ++ RM_IHPSG13_512x32_c2_1P_DEC01 +XDEC01<0> ADDR_N_I<5> ADDR_N_I<4> CS04<0> CS00<1> VDD VSS / ++ RM_IHPSG13_512x32_c2_1P_DEC01 +.ENDS +.SUBCKT RM_IHPSG13_512x32_c2_1P_ROWREG8 ACLK_N_I ADDR_I<7> ADDR_I<6> ADDR_I<5> ADDR_I<4> ++ ADDR_I<3> ADDR_I<2> ADDR_I<1> ADDR_I<0> ADDR_N_O<7> ADDR_N_O<6> ADDR_N_O<5> ++ ADDR_N_O<4> ADDR_N_O<3> ADDR_N_O<2> ADDR_N_O<1> ADDR_N_O<0> BIST_ADDR_I<7> ++ BIST_ADDR_I<6> BIST_ADDR_I<5> BIST_ADDR_I<4> BIST_ADDR_I<3> BIST_ADDR_I<2> ++ BIST_ADDR_I<1> BIST_ADDR_I<0> BIST_EN_I VDD VSS +XINV<7> q_int<7> qn_int<7> VDD VSS / RSC_IHPSG13_CINVX2 +XINV<6> q_int<6> qn_int<6> VDD VSS / RSC_IHPSG13_CINVX2 +XINV<5> q_int<5> qn_int<5> VDD VSS / RSC_IHPSG13_CINVX2 +XINV<4> q_int<4> qn_int<4> VDD VSS / RSC_IHPSG13_CINVX2 +XINV<3> q_int<3> qn_int<3> VDD VSS / RSC_IHPSG13_CINVX2 +XINV<2> q_int<2> qn_int<2> VDD VSS / RSC_IHPSG13_CINVX2 +XINV<1> q_int<1> qn_int<1> VDD VSS / RSC_IHPSG13_CINVX2 +XINV<0> q_int<0> qn_int<0> VDD VSS / RSC_IHPSG13_CINVX2 +XDRV<7> qn_int<7> ADDR_N_O<7> VDD VSS / RSC_IHPSG13_CINVX8 +XDRV<6> qn_int<6> ADDR_N_O<6> VDD VSS / RSC_IHPSG13_CINVX8 +XDRV<5> qn_int<5> ADDR_N_O<5> VDD VSS / RSC_IHPSG13_CINVX8 +XDRV<4> qn_int<4> ADDR_N_O<4> VDD VSS / RSC_IHPSG13_CINVX8 +XDRV<3> qn_int<3> ADDR_N_O<3> VDD VSS / RSC_IHPSG13_CINVX8 +XDRV<2> qn_int<2> ADDR_N_O<2> VDD VSS / RSC_IHPSG13_CINVX8 +XDRV<1> qn_int<1> ADDR_N_O<1> VDD VSS / RSC_IHPSG13_CINVX8 +XDRV<0> qn_int<0> ADDR_N_O<0> VDD VSS / RSC_IHPSG13_CINVX8 +XDFF<7> BIST_EN_I BIST_ADDR_I<7> ACLK_N_I ADDR_I<7> q_int<7> net2<0> VDD ++ VSS / RSC_IHPSG13_DFNQMX2IX1 +XDFF<6> BIST_EN_I BIST_ADDR_I<6> ACLK_N_I ADDR_I<6> q_int<6> net2<1> VDD ++ VSS / RSC_IHPSG13_DFNQMX2IX1 +XDFF<5> BIST_EN_I BIST_ADDR_I<5> ACLK_N_I ADDR_I<5> q_int<5> net2<2> VDD ++ VSS / RSC_IHPSG13_DFNQMX2IX1 +XDFF<4> BIST_EN_I BIST_ADDR_I<4> ACLK_N_I ADDR_I<4> q_int<4> net2<3> VDD ++ VSS / RSC_IHPSG13_DFNQMX2IX1 +XDFF<3> BIST_EN_I BIST_ADDR_I<3> ACLK_N_I ADDR_I<3> q_int<3> net2<4> VDD ++ VSS / RSC_IHPSG13_DFNQMX2IX1 +XDFF<2> BIST_EN_I BIST_ADDR_I<2> ACLK_N_I ADDR_I<2> q_int<2> net2<5> VDD ++ VSS / RSC_IHPSG13_DFNQMX2IX1 +XDFF<1> BIST_EN_I BIST_ADDR_I<1> ACLK_N_I ADDR_I<1> q_int<1> net2<6> VDD ++ VSS / RSC_IHPSG13_DFNQMX2IX1 +XDFF<0> BIST_EN_I BIST_ADDR_I<0> ACLK_N_I ADDR_I<0> q_int<0> net2<7> VDD ++ VSS / RSC_IHPSG13_DFNQMX2IX1 +XI11<4> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI11<3> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI11<2> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI11<1> VDD VSS / RSC_IHPSG13_FILLCAP8 +.ENDS + +.SUBCKT RM_IHPSG13_512x32_c2_1P_ROWDEC9 ADDR_N_I<8> ADDR_N_I<7> ADDR_N_I<6> ADDR_N_I<5> ++ ADDR_N_I<4> ADDR_N_I<3> ADDR_N_I<2> ADDR_N_I<1> ADDR_N_I<0> CS_I ECLK_I ++ WL_O<511> WL_O<510> WL_O<509> WL_O<508> WL_O<507> WL_O<506> WL_O<505> ++ WL_O<504> WL_O<503> WL_O<502> WL_O<501> WL_O<500> WL_O<499> WL_O<498> ++ WL_O<497> WL_O<496> WL_O<495> WL_O<494> WL_O<493> WL_O<492> WL_O<491> ++ WL_O<490> WL_O<489> WL_O<488> WL_O<487> WL_O<486> WL_O<485> WL_O<484> ++ WL_O<483> WL_O<482> WL_O<481> WL_O<480> WL_O<479> WL_O<478> WL_O<477> ++ WL_O<476> WL_O<475> WL_O<474> WL_O<473> WL_O<472> WL_O<471> WL_O<470> ++ WL_O<469> WL_O<468> WL_O<467> WL_O<466> WL_O<465> WL_O<464> WL_O<463> ++ WL_O<462> WL_O<461> WL_O<460> WL_O<459> WL_O<458> WL_O<457> WL_O<456> ++ WL_O<455> WL_O<454> WL_O<453> WL_O<452> WL_O<451> WL_O<450> WL_O<449> ++ WL_O<448> WL_O<447> WL_O<446> WL_O<445> WL_O<444> WL_O<443> WL_O<442> ++ WL_O<441> WL_O<440> WL_O<439> WL_O<438> WL_O<437> WL_O<436> WL_O<435> ++ WL_O<434> WL_O<433> WL_O<432> WL_O<431> WL_O<430> WL_O<429> WL_O<428> ++ WL_O<427> WL_O<426> WL_O<425> WL_O<424> WL_O<423> WL_O<422> WL_O<421> ++ WL_O<420> WL_O<419> WL_O<418> WL_O<417> WL_O<416> WL_O<415> WL_O<414> ++ WL_O<413> WL_O<412> WL_O<411> WL_O<410> WL_O<409> WL_O<408> WL_O<407> ++ WL_O<406> WL_O<405> WL_O<404> WL_O<403> WL_O<402> WL_O<401> WL_O<400> ++ WL_O<399> WL_O<398> WL_O<397> WL_O<396> WL_O<395> WL_O<394> WL_O<393> ++ WL_O<392> WL_O<391> WL_O<390> WL_O<389> WL_O<388> WL_O<387> WL_O<386> ++ WL_O<385> WL_O<384> WL_O<383> WL_O<382> WL_O<381> WL_O<380> WL_O<379> ++ WL_O<378> WL_O<377> WL_O<376> WL_O<375> WL_O<374> WL_O<373> WL_O<372> ++ WL_O<371> WL_O<370> WL_O<369> WL_O<368> WL_O<367> WL_O<366> WL_O<365> ++ WL_O<364> WL_O<363> WL_O<362> WL_O<361> WL_O<360> WL_O<359> WL_O<358> ++ WL_O<357> WL_O<356> WL_O<355> WL_O<354> WL_O<353> WL_O<352> WL_O<351> ++ WL_O<350> WL_O<349> WL_O<348> WL_O<347> WL_O<346> WL_O<345> WL_O<344> ++ WL_O<343> WL_O<342> WL_O<341> WL_O<340> WL_O<339> WL_O<338> WL_O<337> ++ WL_O<336> WL_O<335> WL_O<334> WL_O<333> WL_O<332> WL_O<331> WL_O<330> ++ WL_O<329> WL_O<328> WL_O<327> WL_O<326> WL_O<325> WL_O<324> WL_O<323> ++ WL_O<322> WL_O<321> WL_O<320> WL_O<319> WL_O<318> WL_O<317> WL_O<316> ++ WL_O<315> WL_O<314> WL_O<313> WL_O<312> WL_O<311> WL_O<310> WL_O<309> ++ WL_O<308> WL_O<307> WL_O<306> WL_O<305> WL_O<304> WL_O<303> WL_O<302> ++ WL_O<301> WL_O<300> WL_O<299> WL_O<298> WL_O<297> WL_O<296> WL_O<295> ++ WL_O<294> WL_O<293> WL_O<292> WL_O<291> WL_O<290> WL_O<289> WL_O<288> ++ WL_O<287> WL_O<286> WL_O<285> WL_O<284> WL_O<283> WL_O<282> WL_O<281> ++ WL_O<280> WL_O<279> WL_O<278> WL_O<277> WL_O<276> WL_O<275> WL_O<274> ++ WL_O<273> WL_O<272> WL_O<271> WL_O<270> WL_O<269> WL_O<268> WL_O<267> ++ WL_O<266> WL_O<265> WL_O<264> WL_O<263> WL_O<262> WL_O<261> WL_O<260> ++ WL_O<259> WL_O<258> WL_O<257> WL_O<256> WL_O<255> WL_O<254> WL_O<253> ++ WL_O<252> WL_O<251> WL_O<250> WL_O<249> WL_O<248> WL_O<247> WL_O<246> ++ WL_O<245> WL_O<244> WL_O<243> WL_O<242> WL_O<241> WL_O<240> WL_O<239> ++ WL_O<238> WL_O<237> WL_O<236> WL_O<235> WL_O<234> WL_O<233> WL_O<232> ++ WL_O<231> WL_O<230> WL_O<229> WL_O<228> WL_O<227> WL_O<226> WL_O<225> ++ WL_O<224> WL_O<223> WL_O<222> WL_O<221> WL_O<220> WL_O<219> WL_O<218> ++ WL_O<217> WL_O<216> WL_O<215> WL_O<214> WL_O<213> WL_O<212> WL_O<211> ++ WL_O<210> WL_O<209> WL_O<208> WL_O<207> WL_O<206> WL_O<205> WL_O<204> ++ WL_O<203> WL_O<202> WL_O<201> WL_O<200> WL_O<199> WL_O<198> WL_O<197> ++ WL_O<196> WL_O<195> WL_O<194> WL_O<193> WL_O<192> WL_O<191> WL_O<190> ++ WL_O<189> WL_O<188> WL_O<187> WL_O<186> WL_O<185> WL_O<184> WL_O<183> ++ WL_O<182> WL_O<181> WL_O<180> WL_O<179> WL_O<178> WL_O<177> WL_O<176> ++ WL_O<175> WL_O<174> WL_O<173> WL_O<172> WL_O<171> WL_O<170> WL_O<169> ++ WL_O<168> WL_O<167> WL_O<166> WL_O<165> WL_O<164> WL_O<163> WL_O<162> ++ WL_O<161> WL_O<160> WL_O<159> WL_O<158> WL_O<157> WL_O<156> WL_O<155> ++ WL_O<154> WL_O<153> WL_O<152> WL_O<151> WL_O<150> WL_O<149> WL_O<148> ++ WL_O<147> WL_O<146> WL_O<145> WL_O<144> WL_O<143> WL_O<142> WL_O<141> ++ WL_O<140> WL_O<139> WL_O<138> WL_O<137> WL_O<136> WL_O<135> WL_O<134> ++ WL_O<133> WL_O<132> WL_O<131> WL_O<130> WL_O<129> WL_O<128> WL_O<127> ++ WL_O<126> WL_O<125> WL_O<124> WL_O<123> WL_O<122> WL_O<121> WL_O<120> ++ WL_O<119> WL_O<118> WL_O<117> WL_O<116> WL_O<115> WL_O<114> WL_O<113> ++ WL_O<112> WL_O<111> WL_O<110> WL_O<109> WL_O<108> WL_O<107> WL_O<106> ++ WL_O<105> WL_O<104> WL_O<103> WL_O<102> WL_O<101> WL_O<100> WL_O<99> ++ WL_O<98> WL_O<97> WL_O<96> WL_O<95> WL_O<94> WL_O<93> WL_O<92> WL_O<91> ++ WL_O<90> WL_O<89> WL_O<88> WL_O<87> WL_O<86> WL_O<85> WL_O<84> WL_O<83> ++ WL_O<82> WL_O<81> WL_O<80> WL_O<79> WL_O<78> WL_O<77> WL_O<76> WL_O<75> ++ WL_O<74> WL_O<73> WL_O<72> WL_O<71> WL_O<70> WL_O<69> WL_O<68> WL_O<67> ++ WL_O<66> WL_O<65> WL_O<64> WL_O<63> WL_O<62> WL_O<61> WL_O<60> WL_O<59> ++ WL_O<58> WL_O<57> WL_O<56> WL_O<55> WL_O<54> WL_O<53> WL_O<52> WL_O<51> ++ WL_O<50> WL_O<49> WL_O<48> WL_O<47> WL_O<46> WL_O<45> WL_O<44> WL_O<43> ++ WL_O<42> WL_O<41> WL_O<40> WL_O<39> WL_O<38> WL_O<37> WL_O<36> WL_O<35> ++ WL_O<34> WL_O<33> WL_O<32> WL_O<31> WL_O<30> WL_O<29> WL_O<28> WL_O<27> ++ WL_O<26> WL_O<25> WL_O<24> WL_O<23> WL_O<22> WL_O<21> WL_O<20> WL_O<19> ++ WL_O<18> WL_O<17> WL_O<16> WL_O<15> WL_O<14> WL_O<13> WL_O<12> WL_O<11> ++ WL_O<10> WL_O<9> WL_O<8> WL_O<7> WL_O<6> WL_O<5> WL_O<4> WL_O<3> WL_O<2> ++ WL_O<1> WL_O<0> VDD VSS +XL2<172> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<171> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<170> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<169> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<168> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<167> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<166> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<165> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<164> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<163> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<162> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<161> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<160> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<159> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<158> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<157> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<156> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<155> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<154> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<153> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<152> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<151> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<150> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<149> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<148> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<147> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<146> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<145> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<144> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<143> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<142> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<141> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<140> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<139> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<138> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<137> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<136> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<135> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<134> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<133> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<132> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<131> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<130> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<129> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<128> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<127> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<126> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<125> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<124> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<123> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<122> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<121> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<120> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<119> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<118> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<117> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<116> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<115> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<114> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<113> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<112> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<111> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<110> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<109> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<108> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<107> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<106> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<105> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<104> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<103> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<102> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<101> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<100> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<99> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<98> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<97> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<96> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<95> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<94> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<93> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<92> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<91> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<90> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<89> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<88> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<87> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<86> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<85> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<84> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<83> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<82> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<81> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<80> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<79> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<78> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<77> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<76> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<75> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<74> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<73> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<72> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<71> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<70> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<69> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<68> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<67> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<66> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<65> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<64> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<63> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<62> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<61> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<60> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<59> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<58> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<57> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<56> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<55> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<54> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<53> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<52> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<51> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<50> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<49> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<48> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<47> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<46> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<45> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<44> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<43> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<42> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<41> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<40> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<39> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<38> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<37> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<36> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<35> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<34> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<33> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<32> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<31> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<30> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<29> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<28> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<27> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<26> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<25> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<24> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<23> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<22> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<21> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<20> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<19> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<18> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<17> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<16> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<15> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<14> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<13> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<12> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<11> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<10> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<9> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<8> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<7> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<6> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<5> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<4> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<3> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<2> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<1> VDD VSS / RSC_IHPSG13_FILLCAP8 +XDEC11<9> ADDR_N_I<7> ADDR_N_I<6> CS04<1> CS02<7> VDD VSS / ++ RM_IHPSG13_512x32_c2_1P_DEC03 +XDEC11<8> ADDR_N_I<7> ADDR_N_I<6> CS04<0> CS02<3> VDD VSS / ++ RM_IHPSG13_512x32_c2_1P_DEC03 +XDEC11<7> ADDR_N_I<5> ADDR_N_I<4> CS02<7> CS00<31> VDD VSS / ++ RM_IHPSG13_512x32_c2_1P_DEC03 +XDEC11<6> ADDR_N_I<5> ADDR_N_I<4> CS02<6> CS00<27> VDD VSS / ++ RM_IHPSG13_512x32_c2_1P_DEC03 +XDEC11<5> ADDR_N_I<5> ADDR_N_I<4> CS02<5> CS00<23> VDD VSS / ++ RM_IHPSG13_512x32_c2_1P_DEC03 +XDEC11<4> ADDR_N_I<5> ADDR_N_I<4> CS02<4> CS00<19> VDD VSS / ++ RM_IHPSG13_512x32_c2_1P_DEC03 +XDEC11<3> ADDR_N_I<5> ADDR_N_I<4> CS02<3> CS00<15> VDD VSS / ++ RM_IHPSG13_512x32_c2_1P_DEC03 +XDEC11<2> ADDR_N_I<5> ADDR_N_I<4> CS02<2> CS00<11> VDD VSS / ++ RM_IHPSG13_512x32_c2_1P_DEC03 +XDEC11<1> ADDR_N_I<5> ADDR_N_I<4> CS02<1> CS00<7> VDD VSS / ++ RM_IHPSG13_512x32_c2_1P_DEC03 +XDEC11<0> ADDR_N_I<5> ADDR_N_I<4> CS02<0> CS00<3> VDD VSS / ++ RM_IHPSG13_512x32_c2_1P_DEC03 +XDEC00<10> ADDR_N_I<9> ADDR_N_I<8> CS_I CS04<0> VDD VSS / ++ RM_IHPSG13_512x32_c2_1P_DEC00 +XDEC00<9> ADDR_N_I<7> ADDR_N_I<6> CS04<1> CS02<4> VDD VSS / ++ RM_IHPSG13_512x32_c2_1P_DEC00 +XDEC00<8> ADDR_N_I<7> ADDR_N_I<6> CS04<0> CS02<0> VDD VSS / ++ RM_IHPSG13_512x32_c2_1P_DEC00 +XDEC00<7> ADDR_N_I<5> ADDR_N_I<4> CS02<7> CS00<28> VDD VSS / ++ RM_IHPSG13_512x32_c2_1P_DEC00 +XDEC00<6> ADDR_N_I<5> ADDR_N_I<4> CS02<6> CS00<24> VDD VSS / ++ RM_IHPSG13_512x32_c2_1P_DEC00 +XDEC00<5> ADDR_N_I<5> ADDR_N_I<4> CS02<5> CS00<20> VDD VSS / ++ RM_IHPSG13_512x32_c2_1P_DEC00 +XDEC00<4> ADDR_N_I<5> ADDR_N_I<4> CS02<4> CS00<16> VDD VSS / ++ RM_IHPSG13_512x32_c2_1P_DEC00 +XDEC00<3> ADDR_N_I<5> ADDR_N_I<4> CS02<3> CS00<12> VDD VSS / ++ RM_IHPSG13_512x32_c2_1P_DEC00 +XDEC00<2> ADDR_N_I<5> ADDR_N_I<4> CS02<2> CS00<8> VDD VSS / ++ RM_IHPSG13_512x32_c2_1P_DEC00 +XDEC00<1> ADDR_N_I<5> ADDR_N_I<4> CS02<1> CS00<4> VDD VSS / ++ RM_IHPSG13_512x32_c2_1P_DEC00 +XDEC00<0> ADDR_N_I<5> ADDR_N_I<4> CS02<0> CS00<0> VDD VSS / ++ RM_IHPSG13_512x32_c2_1P_DEC00 +XSEL<31> ADDR_N_I<3> ADDR_N_I<2> ADDR_N_I<1> ADDR_N_I<0> CS00<31> ECLK_H<31> ++ ECLK_H<32> ECLK_B<31> ECLK_B<32> WL_O<511> WL_O<510> WL_O<509> WL_O<508> ++ WL_O<507> WL_O<506> WL_O<505> WL_O<504> WL_O<503> WL_O<502> WL_O<501> ++ WL_O<500> WL_O<499> WL_O<498> WL_O<497> WL_O<496> VDD VSS / ++ RM_IHPSG13_512x32_c2_1P_DEC04 +XSEL<30> ADDR_N_I<3> ADDR_N_I<2> ADDR_N_I<1> ADDR_N_I<0> CS00<30> ECLK_H<30> ++ ECLK_H<31> ECLK_B<30> ECLK_B<31> WL_O<495> WL_O<494> WL_O<493> WL_O<492> ++ WL_O<491> WL_O<490> WL_O<489> WL_O<488> WL_O<487> WL_O<486> WL_O<485> ++ WL_O<484> WL_O<483> WL_O<482> WL_O<481> WL_O<480> VDD VSS / ++ RM_IHPSG13_512x32_c2_1P_DEC04 +XSEL<29> ADDR_N_I<3> ADDR_N_I<2> ADDR_N_I<1> ADDR_N_I<0> CS00<29> ECLK_H<29> ++ ECLK_H<30> ECLK_B<29> ECLK_B<30> WL_O<479> WL_O<478> WL_O<477> WL_O<476> ++ WL_O<475> WL_O<474> WL_O<473> WL_O<472> WL_O<471> WL_O<470> WL_O<469> ++ WL_O<468> WL_O<467> WL_O<466> WL_O<465> WL_O<464> VDD VSS / ++ RM_IHPSG13_512x32_c2_1P_DEC04 +XSEL<28> ADDR_N_I<3> ADDR_N_I<2> ADDR_N_I<1> ADDR_N_I<0> CS00<28> ECLK_H<28> ++ ECLK_H<29> ECLK_B<28> ECLK_B<29> WL_O<463> WL_O<462> WL_O<461> WL_O<460> ++ WL_O<459> WL_O<458> WL_O<457> WL_O<456> WL_O<455> WL_O<454> WL_O<453> ++ WL_O<452> WL_O<451> WL_O<450> WL_O<449> WL_O<448> VDD VSS / ++ RM_IHPSG13_512x32_c2_1P_DEC04 +XSEL<27> ADDR_N_I<3> ADDR_N_I<2> ADDR_N_I<1> ADDR_N_I<0> CS00<27> ECLK_H<27> ++ ECLK_H<28> ECLK_B<27> ECLK_B<28> WL_O<447> WL_O<446> WL_O<445> WL_O<444> ++ WL_O<443> WL_O<442> WL_O<441> WL_O<440> WL_O<439> WL_O<438> WL_O<437> ++ WL_O<436> WL_O<435> WL_O<434> WL_O<433> WL_O<432> VDD VSS / ++ RM_IHPSG13_512x32_c2_1P_DEC04 +XSEL<26> ADDR_N_I<3> ADDR_N_I<2> ADDR_N_I<1> ADDR_N_I<0> CS00<26> ECLK_H<26> ++ ECLK_H<27> ECLK_B<26> ECLK_B<27> WL_O<431> WL_O<430> WL_O<429> WL_O<428> ++ WL_O<427> WL_O<426> WL_O<425> WL_O<424> WL_O<423> WL_O<422> WL_O<421> ++ WL_O<420> WL_O<419> WL_O<418> WL_O<417> WL_O<416> VDD VSS / ++ RM_IHPSG13_512x32_c2_1P_DEC04 +XSEL<25> ADDR_N_I<3> ADDR_N_I<2> ADDR_N_I<1> ADDR_N_I<0> CS00<25> ECLK_H<25> ++ ECLK_H<26> ECLK_B<25> ECLK_B<26> WL_O<415> WL_O<414> WL_O<413> WL_O<412> ++ WL_O<411> WL_O<410> WL_O<409> WL_O<408> WL_O<407> WL_O<406> WL_O<405> ++ WL_O<404> WL_O<403> WL_O<402> WL_O<401> WL_O<400> VDD VSS / ++ RM_IHPSG13_512x32_c2_1P_DEC04 +XSEL<24> ADDR_N_I<3> ADDR_N_I<2> ADDR_N_I<1> ADDR_N_I<0> CS00<24> ECLK_H<24> ++ ECLK_H<25> ECLK_B<24> ECLK_B<25> WL_O<399> WL_O<398> WL_O<397> WL_O<396> ++ WL_O<395> WL_O<394> WL_O<393> WL_O<392> WL_O<391> WL_O<390> WL_O<389> ++ WL_O<388> WL_O<387> WL_O<386> WL_O<385> WL_O<384> VDD VSS / ++ RM_IHPSG13_512x32_c2_1P_DEC04 +XSEL<23> ADDR_N_I<3> ADDR_N_I<2> ADDR_N_I<1> ADDR_N_I<0> CS00<23> ECLK_H<23> ++ ECLK_H<24> ECLK_B<23> ECLK_B<24> WL_O<383> WL_O<382> WL_O<381> WL_O<380> ++ WL_O<379> WL_O<378> WL_O<377> WL_O<376> WL_O<375> WL_O<374> WL_O<373> ++ WL_O<372> WL_O<371> WL_O<370> WL_O<369> WL_O<368> VDD VSS / ++ RM_IHPSG13_512x32_c2_1P_DEC04 +XSEL<22> ADDR_N_I<3> ADDR_N_I<2> ADDR_N_I<1> ADDR_N_I<0> CS00<22> ECLK_H<22> ++ ECLK_H<23> ECLK_B<22> ECLK_B<23> WL_O<367> WL_O<366> WL_O<365> WL_O<364> ++ WL_O<363> WL_O<362> WL_O<361> WL_O<360> WL_O<359> WL_O<358> WL_O<357> ++ WL_O<356> WL_O<355> WL_O<354> WL_O<353> WL_O<352> VDD VSS / ++ RM_IHPSG13_512x32_c2_1P_DEC04 +XSEL<21> ADDR_N_I<3> ADDR_N_I<2> ADDR_N_I<1> ADDR_N_I<0> CS00<21> ECLK_H<21> ++ ECLK_H<22> ECLK_B<21> ECLK_B<22> WL_O<351> WL_O<350> WL_O<349> WL_O<348> ++ WL_O<347> WL_O<346> WL_O<345> WL_O<344> WL_O<343> WL_O<342> WL_O<341> ++ WL_O<340> WL_O<339> WL_O<338> WL_O<337> WL_O<336> VDD VSS / ++ RM_IHPSG13_512x32_c2_1P_DEC04 +XSEL<20> ADDR_N_I<3> ADDR_N_I<2> ADDR_N_I<1> ADDR_N_I<0> CS00<20> ECLK_H<20> ++ ECLK_H<21> ECLK_B<20> ECLK_B<21> WL_O<335> WL_O<334> WL_O<333> WL_O<332> ++ WL_O<331> WL_O<330> WL_O<329> WL_O<328> WL_O<327> WL_O<326> WL_O<325> ++ WL_O<324> WL_O<323> WL_O<322> WL_O<321> WL_O<320> VDD VSS / ++ RM_IHPSG13_512x32_c2_1P_DEC04 +XSEL<19> ADDR_N_I<3> ADDR_N_I<2> ADDR_N_I<1> ADDR_N_I<0> CS00<19> ECLK_H<19> ++ ECLK_H<20> ECLK_B<19> ECLK_B<20> WL_O<319> WL_O<318> WL_O<317> WL_O<316> ++ WL_O<315> WL_O<314> WL_O<313> WL_O<312> WL_O<311> WL_O<310> WL_O<309> ++ WL_O<308> WL_O<307> WL_O<306> WL_O<305> WL_O<304> VDD VSS / ++ RM_IHPSG13_512x32_c2_1P_DEC04 +XSEL<18> ADDR_N_I<3> ADDR_N_I<2> ADDR_N_I<1> ADDR_N_I<0> CS00<18> ECLK_H<18> ++ ECLK_H<19> ECLK_B<18> ECLK_B<19> WL_O<303> WL_O<302> WL_O<301> WL_O<300> ++ WL_O<299> WL_O<298> WL_O<297> WL_O<296> WL_O<295> WL_O<294> WL_O<293> ++ WL_O<292> WL_O<291> WL_O<290> WL_O<289> WL_O<288> VDD VSS / ++ RM_IHPSG13_512x32_c2_1P_DEC04 +XSEL<17> ADDR_N_I<3> ADDR_N_I<2> ADDR_N_I<1> ADDR_N_I<0> CS00<17> ECLK_H<17> ++ ECLK_H<18> ECLK_B<17> ECLK_B<18> WL_O<287> WL_O<286> WL_O<285> WL_O<284> ++ WL_O<283> WL_O<282> WL_O<281> WL_O<280> WL_O<279> WL_O<278> WL_O<277> ++ WL_O<276> WL_O<275> WL_O<274> WL_O<273> WL_O<272> VDD VSS / ++ RM_IHPSG13_512x32_c2_1P_DEC04 +XSEL<16> ADDR_N_I<3> ADDR_N_I<2> ADDR_N_I<1> ADDR_N_I<0> CS00<16> ECLK_H<16> ++ ECLK_H<17> ECLK_B<16> ECLK_B<17> WL_O<271> WL_O<270> WL_O<269> WL_O<268> ++ WL_O<267> WL_O<266> WL_O<265> WL_O<264> WL_O<263> WL_O<262> WL_O<261> ++ WL_O<260> WL_O<259> WL_O<258> WL_O<257> WL_O<256> VDD VSS / ++ RM_IHPSG13_512x32_c2_1P_DEC04 +XSEL<15> ADDR_N_I<3> ADDR_N_I<2> ADDR_N_I<1> ADDR_N_I<0> CS00<15> ECLK_H<15> ++ ECLK_H<16> ECLK_B<15> ECLK_B<16> WL_O<255> WL_O<254> WL_O<253> WL_O<252> ++ WL_O<251> WL_O<250> WL_O<249> WL_O<248> WL_O<247> WL_O<246> WL_O<245> ++ WL_O<244> WL_O<243> WL_O<242> WL_O<241> WL_O<240> VDD VSS / ++ RM_IHPSG13_512x32_c2_1P_DEC04 +XSEL<14> ADDR_N_I<3> ADDR_N_I<2> ADDR_N_I<1> ADDR_N_I<0> CS00<14> ECLK_H<14> ++ ECLK_H<15> ECLK_B<14> ECLK_B<15> WL_O<239> WL_O<238> WL_O<237> WL_O<236> ++ WL_O<235> WL_O<234> WL_O<233> WL_O<232> WL_O<231> WL_O<230> WL_O<229> ++ WL_O<228> WL_O<227> WL_O<226> WL_O<225> WL_O<224> VDD VSS / ++ RM_IHPSG13_512x32_c2_1P_DEC04 +XSEL<13> ADDR_N_I<3> ADDR_N_I<2> ADDR_N_I<1> ADDR_N_I<0> CS00<13> ECLK_H<13> ++ ECLK_H<14> ECLK_B<13> ECLK_B<14> WL_O<223> WL_O<222> WL_O<221> WL_O<220> ++ WL_O<219> WL_O<218> WL_O<217> WL_O<216> WL_O<215> WL_O<214> WL_O<213> ++ WL_O<212> WL_O<211> WL_O<210> WL_O<209> WL_O<208> VDD VSS / ++ RM_IHPSG13_512x32_c2_1P_DEC04 +XSEL<12> ADDR_N_I<3> ADDR_N_I<2> ADDR_N_I<1> ADDR_N_I<0> CS00<12> ECLK_H<12> ++ ECLK_H<13> ECLK_B<12> ECLK_B<13> WL_O<207> WL_O<206> WL_O<205> WL_O<204> ++ WL_O<203> WL_O<202> WL_O<201> WL_O<200> WL_O<199> WL_O<198> WL_O<197> ++ WL_O<196> WL_O<195> WL_O<194> WL_O<193> WL_O<192> VDD VSS / ++ RM_IHPSG13_512x32_c2_1P_DEC04 +XSEL<11> ADDR_N_I<3> ADDR_N_I<2> ADDR_N_I<1> ADDR_N_I<0> CS00<11> ECLK_H<11> ++ ECLK_H<12> ECLK_B<11> ECLK_B<12> WL_O<191> WL_O<190> WL_O<189> WL_O<188> ++ WL_O<187> WL_O<186> WL_O<185> WL_O<184> WL_O<183> WL_O<182> WL_O<181> ++ WL_O<180> WL_O<179> WL_O<178> WL_O<177> WL_O<176> VDD VSS / ++ RM_IHPSG13_512x32_c2_1P_DEC04 +XSEL<10> ADDR_N_I<3> ADDR_N_I<2> ADDR_N_I<1> ADDR_N_I<0> CS00<10> ECLK_H<10> ++ ECLK_H<11> ECLK_B<10> ECLK_B<11> WL_O<175> WL_O<174> WL_O<173> WL_O<172> ++ WL_O<171> WL_O<170> WL_O<169> WL_O<168> WL_O<167> WL_O<166> WL_O<165> ++ WL_O<164> WL_O<163> WL_O<162> WL_O<161> WL_O<160> VDD VSS / ++ RM_IHPSG13_512x32_c2_1P_DEC04 +XSEL<9> ADDR_N_I<3> ADDR_N_I<2> ADDR_N_I<1> ADDR_N_I<0> CS00<9> ECLK_H<9> ++ ECLK_H<10> ECLK_B<9> ECLK_B<10> WL_O<159> WL_O<158> WL_O<157> WL_O<156> ++ WL_O<155> WL_O<154> WL_O<153> WL_O<152> WL_O<151> WL_O<150> WL_O<149> ++ WL_O<148> WL_O<147> WL_O<146> WL_O<145> WL_O<144> VDD VSS / ++ RM_IHPSG13_512x32_c2_1P_DEC04 +XSEL<8> ADDR_N_I<3> ADDR_N_I<2> ADDR_N_I<1> ADDR_N_I<0> CS00<8> ECLK_H<8> ++ ECLK_H<9> ECLK_B<8> ECLK_B<9> WL_O<143> WL_O<142> WL_O<141> WL_O<140> ++ WL_O<139> WL_O<138> WL_O<137> WL_O<136> WL_O<135> WL_O<134> WL_O<133> ++ WL_O<132> WL_O<131> WL_O<130> WL_O<129> WL_O<128> VDD VSS / ++ RM_IHPSG13_512x32_c2_1P_DEC04 +XSEL<7> ADDR_N_I<3> ADDR_N_I<2> ADDR_N_I<1> ADDR_N_I<0> CS00<7> ECLK_H<7> ++ ECLK_H<8> ECLK_B<7> ECLK_B<8> WL_O<127> WL_O<126> WL_O<125> WL_O<124> ++ WL_O<123> WL_O<122> WL_O<121> WL_O<120> WL_O<119> WL_O<118> WL_O<117> ++ WL_O<116> WL_O<115> WL_O<114> WL_O<113> WL_O<112> VDD VSS / ++ RM_IHPSG13_512x32_c2_1P_DEC04 +XSEL<6> ADDR_N_I<3> ADDR_N_I<2> ADDR_N_I<1> ADDR_N_I<0> CS00<6> ECLK_H<6> ++ ECLK_H<7> ECLK_B<6> ECLK_B<7> WL_O<111> WL_O<110> WL_O<109> WL_O<108> ++ WL_O<107> WL_O<106> WL_O<105> WL_O<104> WL_O<103> WL_O<102> WL_O<101> ++ WL_O<100> WL_O<99> WL_O<98> WL_O<97> WL_O<96> VDD VSS / ++ RM_IHPSG13_512x32_c2_1P_DEC04 +XSEL<5> ADDR_N_I<3> ADDR_N_I<2> ADDR_N_I<1> ADDR_N_I<0> CS00<5> ECLK_H<5> ++ ECLK_H<6> ECLK_B<5> ECLK_B<6> WL_O<95> WL_O<94> WL_O<93> WL_O<92> WL_O<91> ++ WL_O<90> WL_O<89> WL_O<88> WL_O<87> WL_O<86> WL_O<85> WL_O<84> WL_O<83> ++ WL_O<82> WL_O<81> WL_O<80> VDD VSS / RM_IHPSG13_512x32_c2_1P_DEC04 +XSEL<4> ADDR_N_I<3> ADDR_N_I<2> ADDR_N_I<1> ADDR_N_I<0> CS00<4> ECLK_H<4> ++ ECLK_H<5> ECLK_B<4> ECLK_B<5> WL_O<79> WL_O<78> WL_O<77> WL_O<76> WL_O<75> ++ WL_O<74> WL_O<73> WL_O<72> WL_O<71> WL_O<70> WL_O<69> WL_O<68> WL_O<67> ++ WL_O<66> WL_O<65> WL_O<64> VDD VSS / RM_IHPSG13_512x32_c2_1P_DEC04 +XSEL<3> ADDR_N_I<3> ADDR_N_I<2> ADDR_N_I<1> ADDR_N_I<0> CS00<3> ECLK_H<3> ++ ECLK_H<4> ECLK_B<3> ECLK_B<4> WL_O<63> WL_O<62> WL_O<61> WL_O<60> WL_O<59> ++ WL_O<58> WL_O<57> WL_O<56> WL_O<55> WL_O<54> WL_O<53> WL_O<52> WL_O<51> ++ WL_O<50> WL_O<49> WL_O<48> VDD VSS / RM_IHPSG13_512x32_c2_1P_DEC04 +XSEL<2> ADDR_N_I<3> ADDR_N_I<2> ADDR_N_I<1> ADDR_N_I<0> CS00<2> ECLK_H<2> ++ ECLK_H<3> ECLK_B<2> ECLK_B<3> WL_O<47> WL_O<46> WL_O<45> WL_O<44> WL_O<43> ++ WL_O<42> WL_O<41> WL_O<40> WL_O<39> WL_O<38> WL_O<37> WL_O<36> WL_O<35> ++ WL_O<34> WL_O<33> WL_O<32> VDD VSS / RM_IHPSG13_512x32_c2_1P_DEC04 +XSEL<1> ADDR_N_I<3> ADDR_N_I<2> ADDR_N_I<1> ADDR_N_I<0> CS00<1> ECLK_H<1> ++ ECLK_H<2> ECLK_B<1> ECLK_B<2> WL_O<31> WL_O<30> WL_O<29> WL_O<28> WL_O<27> ++ WL_O<26> WL_O<25> WL_O<24> WL_O<23> WL_O<22> WL_O<21> WL_O<20> WL_O<19> ++ WL_O<18> WL_O<17> WL_O<16> VDD VSS / RM_IHPSG13_512x32_c2_1P_DEC04 +XSEL<0> ADDR_N_I<3> ADDR_N_I<2> ADDR_N_I<1> ADDR_N_I<0> CS00<0> ECLK_I ++ ECLK_H<1> ECLK_B<0> ECLK_B<1> WL_O<15> WL_O<14> WL_O<13> WL_O<12> WL_O<11> ++ WL_O<10> WL_O<9> WL_O<8> WL_O<7> WL_O<6> WL_O<5> WL_O<4> WL_O<3> WL_O<2> ++ WL_O<1> WL_O<0> VDD VSS / RM_IHPSG13_512x32_c2_1P_DEC04 +XDEC01<10> ADDR_N_I<9> ADDR_N_I<8> CS_I CS04<1> VDD VSS / ++ RM_IHPSG13_512x32_c2_1P_DEC01 +XDEC01<9> ADDR_N_I<7> ADDR_N_I<6> CS04<1> CS02<5> VDD VSS / ++ RM_IHPSG13_512x32_c2_1P_DEC01 +XDEC01<8> ADDR_N_I<7> ADDR_N_I<6> CS04<0> CS02<1> VDD VSS / ++ RM_IHPSG13_512x32_c2_1P_DEC01 +XDEC01<7> ADDR_N_I<5> ADDR_N_I<4> CS02<7> CS00<29> VDD VSS / ++ RM_IHPSG13_512x32_c2_1P_DEC01 +XDEC01<6> ADDR_N_I<5> ADDR_N_I<4> CS02<6> CS00<25> VDD VSS / ++ RM_IHPSG13_512x32_c2_1P_DEC01 +XDEC01<5> ADDR_N_I<5> ADDR_N_I<4> CS02<5> CS00<21> VDD VSS / ++ RM_IHPSG13_512x32_c2_1P_DEC01 +XDEC01<4> ADDR_N_I<5> ADDR_N_I<4> CS02<4> CS00<17> VDD VSS / ++ RM_IHPSG13_512x32_c2_1P_DEC01 +XDEC01<3> ADDR_N_I<5> ADDR_N_I<4> CS02<3> CS00<13> VDD VSS / ++ RM_IHPSG13_512x32_c2_1P_DEC01 +XDEC01<2> ADDR_N_I<5> ADDR_N_I<4> CS02<2> CS00<9> VDD VSS / ++ RM_IHPSG13_512x32_c2_1P_DEC01 +XDEC01<1> ADDR_N_I<5> ADDR_N_I<4> CS02<1> CS00<5> VDD VSS / ++ RM_IHPSG13_512x32_c2_1P_DEC01 +XDEC01<0> ADDR_N_I<5> ADDR_N_I<4> CS02<0> CS00<1> VDD VSS / ++ RM_IHPSG13_512x32_c2_1P_DEC01 +XDEC10<9> ADDR_N_I<7> ADDR_N_I<6> CS04<1> CS02<6> VDD VSS / ++ RM_IHPSG13_512x32_c2_1P_DEC02 +XDEC10<8> ADDR_N_I<7> ADDR_N_I<6> CS04<0> CS02<2> VDD VSS / ++ RM_IHPSG13_512x32_c2_1P_DEC02 +XDEC10<7> ADDR_N_I<5> ADDR_N_I<4> CS02<7> CS00<30> VDD VSS / ++ RM_IHPSG13_512x32_c2_1P_DEC02 +XDEC10<6> ADDR_N_I<5> ADDR_N_I<4> CS02<6> CS00<26> VDD VSS / ++ RM_IHPSG13_512x32_c2_1P_DEC02 +XDEC10<5> ADDR_N_I<5> ADDR_N_I<4> CS02<5> CS00<22> VDD VSS / ++ RM_IHPSG13_512x32_c2_1P_DEC02 +XDEC10<4> ADDR_N_I<5> ADDR_N_I<4> CS02<4> CS00<18> VDD VSS / ++ RM_IHPSG13_512x32_c2_1P_DEC02 +XDEC10<3> ADDR_N_I<5> ADDR_N_I<4> CS02<3> CS00<14> VDD VSS / ++ RM_IHPSG13_512x32_c2_1P_DEC02 +XDEC10<2> ADDR_N_I<5> ADDR_N_I<4> CS02<2> CS00<10> VDD VSS / ++ RM_IHPSG13_512x32_c2_1P_DEC02 +XDEC10<1> ADDR_N_I<5> ADDR_N_I<4> CS02<1> CS00<6> VDD VSS / ++ RM_IHPSG13_512x32_c2_1P_DEC02 +XDEC10<0> ADDR_N_I<5> ADDR_N_I<4> CS02<0> CS00<2> VDD VSS / ++ RM_IHPSG13_512x32_c2_1P_DEC02 +XI0 ADDR_N_I<9> VDD VSS / RSC_IHPSG13_TIEL +.ENDS +.SUBCKT RM_IHPSG13_512x32_c2_1P_ROWREG9 ACLK_N_I ADDR_I<8> ADDR_I<7> ADDR_I<6> ADDR_I<5> ++ ADDR_I<4> ADDR_I<3> ADDR_I<2> ADDR_I<1> ADDR_I<0> ADDR_N_O<8> ADDR_N_O<7> ++ ADDR_N_O<6> ADDR_N_O<5> ADDR_N_O<4> ADDR_N_O<3> ADDR_N_O<2> ADDR_N_O<1> ++ ADDR_N_O<0> BIST_ADDR_I<8> BIST_ADDR_I<7> BIST_ADDR_I<6> BIST_ADDR_I<5> ++ BIST_ADDR_I<4> BIST_ADDR_I<3> BIST_ADDR_I<2> BIST_ADDR_I<1> BIST_ADDR_I<0> ++ BIST_EN_I VDD VSS +XINV<8> q_int<8> qn_int<8> VDD VSS / RSC_IHPSG13_CINVX2 +XINV<7> q_int<7> qn_int<7> VDD VSS / RSC_IHPSG13_CINVX2 +XINV<6> q_int<6> qn_int<6> VDD VSS / RSC_IHPSG13_CINVX2 +XINV<5> q_int<5> qn_int<5> VDD VSS / RSC_IHPSG13_CINVX2 +XINV<4> q_int<4> qn_int<4> VDD VSS / RSC_IHPSG13_CINVX2 +XINV<3> q_int<3> qn_int<3> VDD VSS / RSC_IHPSG13_CINVX2 +XINV<2> q_int<2> qn_int<2> VDD VSS / RSC_IHPSG13_CINVX2 +XINV<1> q_int<1> qn_int<1> VDD VSS / RSC_IHPSG13_CINVX2 +XINV<0> q_int<0> qn_int<0> VDD VSS / RSC_IHPSG13_CINVX2 +XDRV<8> qn_int<8> ADDR_N_O<8> VDD VSS / RSC_IHPSG13_CINVX8 +XDRV<7> qn_int<7> ADDR_N_O<7> VDD VSS / RSC_IHPSG13_CINVX8 +XDRV<6> qn_int<6> ADDR_N_O<6> VDD VSS / RSC_IHPSG13_CINVX8 +XDRV<5> qn_int<5> ADDR_N_O<5> VDD VSS / RSC_IHPSG13_CINVX8 +XDRV<4> qn_int<4> ADDR_N_O<4> VDD VSS / RSC_IHPSG13_CINVX8 +XDRV<3> qn_int<3> ADDR_N_O<3> VDD VSS / RSC_IHPSG13_CINVX8 +XDRV<2> qn_int<2> ADDR_N_O<2> VDD VSS / RSC_IHPSG13_CINVX8 +XDRV<1> qn_int<1> ADDR_N_O<1> VDD VSS / RSC_IHPSG13_CINVX8 +XDRV<0> qn_int<0> ADDR_N_O<0> VDD VSS / RSC_IHPSG13_CINVX8 +XDFF<8> BIST_EN_I BIST_ADDR_I<8> ACLK_N_I ADDR_I<8> q_int<8> net04<0> VDD ++ VSS / RSC_IHPSG13_DFNQMX2IX1 +XDFF<7> BIST_EN_I BIST_ADDR_I<7> ACLK_N_I ADDR_I<7> q_int<7> net04<1> VDD ++ VSS / RSC_IHPSG13_DFNQMX2IX1 +XDFF<6> BIST_EN_I BIST_ADDR_I<6> ACLK_N_I ADDR_I<6> q_int<6> net04<2> VDD ++ VSS / RSC_IHPSG13_DFNQMX2IX1 +XDFF<5> BIST_EN_I BIST_ADDR_I<5> ACLK_N_I ADDR_I<5> q_int<5> net04<3> VDD ++ VSS / RSC_IHPSG13_DFNQMX2IX1 +XDFF<4> BIST_EN_I BIST_ADDR_I<4> ACLK_N_I ADDR_I<4> q_int<4> net04<4> VDD ++ VSS / RSC_IHPSG13_DFNQMX2IX1 +XDFF<3> BIST_EN_I BIST_ADDR_I<3> ACLK_N_I ADDR_I<3> q_int<3> net04<5> VDD ++ VSS / RSC_IHPSG13_DFNQMX2IX1 +XDFF<2> BIST_EN_I BIST_ADDR_I<2> ACLK_N_I ADDR_I<2> q_int<2> net04<6> VDD ++ VSS / RSC_IHPSG13_DFNQMX2IX1 +XDFF<1> BIST_EN_I BIST_ADDR_I<1> ACLK_N_I ADDR_I<1> q_int<1> net04<7> VDD ++ VSS / RSC_IHPSG13_DFNQMX2IX1 +XDFF<0> BIST_EN_I BIST_ADDR_I<0> ACLK_N_I ADDR_I<0> q_int<0> net04<8> VDD ++ VSS / RSC_IHPSG13_DFNQMX2IX1 +.ENDS + +.SUBCKT RM_IHPSG13_512x32_c2_1P_ROWDEC7 ADDR_N_I<6> ADDR_N_I<5> ADDR_N_I<4> ADDR_N_I<3> ++ ADDR_N_I<2> ADDR_N_I<1> ADDR_N_I<0> CS_I ECLK_I WL_O<127> WL_O<126> ++ WL_O<125> WL_O<124> WL_O<123> WL_O<122> WL_O<121> WL_O<120> WL_O<119> ++ WL_O<118> WL_O<117> WL_O<116> WL_O<115> WL_O<114> WL_O<113> WL_O<112> ++ WL_O<111> WL_O<110> WL_O<109> WL_O<108> WL_O<107> WL_O<106> WL_O<105> ++ WL_O<104> WL_O<103> WL_O<102> WL_O<101> WL_O<100> WL_O<99> WL_O<98> WL_O<97> ++ WL_O<96> WL_O<95> WL_O<94> WL_O<93> WL_O<92> WL_O<91> WL_O<90> WL_O<89> ++ WL_O<88> WL_O<87> WL_O<86> WL_O<85> WL_O<84> WL_O<83> WL_O<82> WL_O<81> ++ WL_O<80> WL_O<79> WL_O<78> WL_O<77> WL_O<76> WL_O<75> WL_O<74> WL_O<73> ++ WL_O<72> WL_O<71> WL_O<70> WL_O<69> WL_O<68> WL_O<67> WL_O<66> WL_O<65> ++ WL_O<64> WL_O<63> WL_O<62> WL_O<61> WL_O<60> WL_O<59> WL_O<58> WL_O<57> ++ WL_O<56> WL_O<55> WL_O<54> WL_O<53> WL_O<52> WL_O<51> WL_O<50> WL_O<49> ++ WL_O<48> WL_O<47> WL_O<46> WL_O<45> WL_O<44> WL_O<43> WL_O<42> WL_O<41> ++ WL_O<40> WL_O<39> WL_O<38> WL_O<37> WL_O<36> WL_O<35> WL_O<34> WL_O<33> ++ WL_O<32> WL_O<31> WL_O<30> WL_O<29> WL_O<28> WL_O<27> WL_O<26> WL_O<25> ++ WL_O<24> WL_O<23> WL_O<22> WL_O<21> WL_O<20> WL_O<19> WL_O<18> WL_O<17> ++ WL_O<16> WL_O<15> WL_O<14> WL_O<13> WL_O<12> WL_O<11> WL_O<10> WL_O<9> ++ WL_O<8> WL_O<7> WL_O<6> WL_O<5> WL_O<4> WL_O<3> WL_O<2> WL_O<1> WL_O<0> ++ VDD VSS +XDEC11<1> ADDR_N_I<5> ADDR_N_I<4> CS04<1> CS00<7> VDD VSS / ++ RM_IHPSG13_512x32_c2_1P_DEC03 +XDEC11<0> ADDR_N_I<5> ADDR_N_I<4> CS04<0> CS00<3> VDD VSS / ++ RM_IHPSG13_512x32_c2_1P_DEC03 +XDEC10<1> ADDR_N_I<5> ADDR_N_I<4> CS04<1> CS00<6> VDD VSS / ++ RM_IHPSG13_512x32_c2_1P_DEC02 +XDEC10<0> ADDR_N_I<5> ADDR_N_I<4> CS04<0> CS00<2> VDD VSS / ++ RM_IHPSG13_512x32_c2_1P_DEC02 +XSEL<7> ADDR_N_I<3> ADDR_N_I<2> ADDR_N_I<1> ADDR_N_I<0> CS00<7> ECLK_H<7> ++ ECLK_H<8> ECLK_B<7> ECLK_B<8> WL_O<127> WL_O<126> WL_O<125> WL_O<124> ++ WL_O<123> WL_O<122> WL_O<121> WL_O<120> WL_O<119> WL_O<118> WL_O<117> ++ WL_O<116> WL_O<115> WL_O<114> WL_O<113> WL_O<112> VDD VSS / ++ RM_IHPSG13_512x32_c2_1P_DEC04 +XSEL<6> ADDR_N_I<3> ADDR_N_I<2> ADDR_N_I<1> ADDR_N_I<0> CS00<6> ECLK_H<6> ++ ECLK_H<7> ECLK_B<6> ECLK_B<7> WL_O<111> WL_O<110> WL_O<109> WL_O<108> ++ WL_O<107> WL_O<106> WL_O<105> WL_O<104> WL_O<103> WL_O<102> WL_O<101> ++ WL_O<100> WL_O<99> WL_O<98> WL_O<97> WL_O<96> VDD VSS / ++ RM_IHPSG13_512x32_c2_1P_DEC04 +XSEL<5> ADDR_N_I<3> ADDR_N_I<2> ADDR_N_I<1> ADDR_N_I<0> CS00<5> ECLK_H<5> ++ ECLK_H<6> ECLK_B<5> ECLK_B<6> WL_O<95> WL_O<94> WL_O<93> WL_O<92> WL_O<91> ++ WL_O<90> WL_O<89> WL_O<88> WL_O<87> WL_O<86> WL_O<85> WL_O<84> WL_O<83> ++ WL_O<82> WL_O<81> WL_O<80> VDD VSS / RM_IHPSG13_512x32_c2_1P_DEC04 +XSEL<4> ADDR_N_I<3> ADDR_N_I<2> ADDR_N_I<1> ADDR_N_I<0> CS00<4> ECLK_H<4> ++ ECLK_H<5> ECLK_B<4> ECLK_B<5> WL_O<79> WL_O<78> WL_O<77> WL_O<76> WL_O<75> ++ WL_O<74> WL_O<73> WL_O<72> WL_O<71> WL_O<70> WL_O<69> WL_O<68> WL_O<67> ++ WL_O<66> WL_O<65> WL_O<64> VDD VSS / RM_IHPSG13_512x32_c2_1P_DEC04 +XSEL<3> ADDR_N_I<3> ADDR_N_I<2> ADDR_N_I<1> ADDR_N_I<0> CS00<3> ECLK_H<3> ++ ECLK_H<4> ECLK_B<3> ECLK_B<4> WL_O<63> WL_O<62> WL_O<61> WL_O<60> WL_O<59> ++ WL_O<58> WL_O<57> WL_O<56> WL_O<55> WL_O<54> WL_O<53> WL_O<52> WL_O<51> ++ WL_O<50> WL_O<49> WL_O<48> VDD VSS / RM_IHPSG13_512x32_c2_1P_DEC04 +XSEL<2> ADDR_N_I<3> ADDR_N_I<2> ADDR_N_I<1> ADDR_N_I<0> CS00<2> ECLK_H<2> ++ ECLK_H<3> ECLK_B<2> ECLK_B<3> WL_O<47> WL_O<46> WL_O<45> WL_O<44> WL_O<43> ++ WL_O<42> WL_O<41> WL_O<40> WL_O<39> WL_O<38> WL_O<37> WL_O<36> WL_O<35> ++ WL_O<34> WL_O<33> WL_O<32> VDD VSS / RM_IHPSG13_512x32_c2_1P_DEC04 +XSEL<1> ADDR_N_I<3> ADDR_N_I<2> ADDR_N_I<1> ADDR_N_I<0> CS00<1> ECLK_H<1> ++ ECLK_H<2> ECLK_B<1> ECLK_B<2> WL_O<31> WL_O<30> WL_O<29> WL_O<28> WL_O<27> ++ WL_O<26> WL_O<25> WL_O<24> WL_O<23> WL_O<22> WL_O<21> WL_O<20> WL_O<19> ++ WL_O<18> WL_O<17> WL_O<16> VDD VSS / RM_IHPSG13_512x32_c2_1P_DEC04 +XSEL<0> ADDR_N_I<3> ADDR_N_I<2> ADDR_N_I<1> ADDR_N_I<0> CS00<0> ECLK_I ++ ECLK_H<1> ECLK_B<0> ECLK_B<1> WL_O<15> WL_O<14> WL_O<13> WL_O<12> WL_O<11> ++ WL_O<10> WL_O<9> WL_O<8> WL_O<7> WL_O<6> WL_O<5> WL_O<4> WL_O<3> WL_O<2> ++ WL_O<1> WL_O<0> VDD VSS / RM_IHPSG13_512x32_c2_1P_DEC04 +XDEC00<2> ADDR_N_I<7> ADDR_N_I<6> CS_I CS04<0> VDD VSS / ++ RM_IHPSG13_512x32_c2_1P_DEC00 +XDEC00<1> ADDR_N_I<5> ADDR_N_I<4> CS04<1> CS00<4> VDD VSS / ++ RM_IHPSG13_512x32_c2_1P_DEC00 +XDEC00<0> ADDR_N_I<5> ADDR_N_I<4> CS04<0> CS00<0> VDD VSS / ++ RM_IHPSG13_512x32_c2_1P_DEC00 +XDEC01<2> ADDR_N_I<7> ADDR_N_I<6> CS_I CS04<1> VDD VSS / ++ RM_IHPSG13_512x32_c2_1P_DEC01 +XDEC01<1> ADDR_N_I<5> ADDR_N_I<4> CS04<1> CS00<5> VDD VSS / ++ RM_IHPSG13_512x32_c2_1P_DEC01 +XDEC01<0> ADDR_N_I<5> ADDR_N_I<4> CS04<0> CS00<1> VDD VSS / ++ RM_IHPSG13_512x32_c2_1P_DEC01 +XL2<44> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<43> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<42> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<41> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<40> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<39> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<38> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<37> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<36> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<35> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<34> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<33> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<32> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<31> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<30> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<29> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<28> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<27> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<26> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<25> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<24> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<23> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<22> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<21> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<20> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<19> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<18> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<17> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<16> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<15> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<14> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<13> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<12> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<11> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<10> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<9> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<8> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<7> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<6> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<5> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<4> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<3> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<2> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<1> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI0 ADDR_N_I<7> VDD VSS / RSC_IHPSG13_TIEL +.ENDS +.SUBCKT RM_IHPSG13_512x32_c2_1P_ROWREG7 ACLK_N_I ADDR_I<6> ADDR_I<5> ADDR_I<4> ADDR_I<3> ++ ADDR_I<2> ADDR_I<1> ADDR_I<0> ADDR_N_O<6> ADDR_N_O<5> ADDR_N_O<4> ++ ADDR_N_O<3> ADDR_N_O<2> ADDR_N_O<1> ADDR_N_O<0> BIST_ADDR_I<6> ++ BIST_ADDR_I<5> BIST_ADDR_I<4> BIST_ADDR_I<3> BIST_ADDR_I<2> BIST_ADDR_I<1> ++ BIST_ADDR_I<0> BIST_EN_I VDD VSS +XINV<6> q_int<6> qn_int<6> VDD VSS / RSC_IHPSG13_CINVX2 +XINV<5> q_int<5> qn_int<5> VDD VSS / RSC_IHPSG13_CINVX2 +XINV<4> q_int<4> qn_int<4> VDD VSS / RSC_IHPSG13_CINVX2 +XINV<3> q_int<3> qn_int<3> VDD VSS / RSC_IHPSG13_CINVX2 +XINV<2> q_int<2> qn_int<2> VDD VSS / RSC_IHPSG13_CINVX2 +XINV<1> q_int<1> qn_int<1> VDD VSS / RSC_IHPSG13_CINVX2 +XINV<0> q_int<0> qn_int<0> VDD VSS / RSC_IHPSG13_CINVX2 +XDRV<6> qn_int<6> ADDR_N_O<6> VDD VSS / RSC_IHPSG13_CINVX8 +XDRV<5> qn_int<5> ADDR_N_O<5> VDD VSS / RSC_IHPSG13_CINVX8 +XDRV<4> qn_int<4> ADDR_N_O<4> VDD VSS / RSC_IHPSG13_CINVX8 +XDRV<3> qn_int<3> ADDR_N_O<3> VDD VSS / RSC_IHPSG13_CINVX8 +XDRV<2> qn_int<2> ADDR_N_O<2> VDD VSS / RSC_IHPSG13_CINVX8 +XDRV<1> qn_int<1> ADDR_N_O<1> VDD VSS / RSC_IHPSG13_CINVX8 +XDRV<0> qn_int<0> ADDR_N_O<0> VDD VSS / RSC_IHPSG13_CINVX8 +XDFF<6> BIST_EN_I BIST_ADDR_I<6> ACLK_N_I ADDR_I<6> q_int<6> net2<0> VDD ++ VSS / RSC_IHPSG13_DFNQMX2IX1 +XDFF<5> BIST_EN_I BIST_ADDR_I<5> ACLK_N_I ADDR_I<5> q_int<5> net2<1> VDD ++ VSS / RSC_IHPSG13_DFNQMX2IX1 +XDFF<4> BIST_EN_I BIST_ADDR_I<4> ACLK_N_I ADDR_I<4> q_int<4> net2<2> VDD ++ VSS / RSC_IHPSG13_DFNQMX2IX1 +XDFF<3> BIST_EN_I BIST_ADDR_I<3> ACLK_N_I ADDR_I<3> q_int<3> net2<3> VDD ++ VSS / RSC_IHPSG13_DFNQMX2IX1 +XDFF<2> BIST_EN_I BIST_ADDR_I<2> ACLK_N_I ADDR_I<2> q_int<2> net2<4> VDD ++ VSS / RSC_IHPSG13_DFNQMX2IX1 +XDFF<1> BIST_EN_I BIST_ADDR_I<1> ACLK_N_I ADDR_I<1> q_int<1> net2<5> VDD ++ VSS / RSC_IHPSG13_DFNQMX2IX1 +XDFF<0> BIST_EN_I BIST_ADDR_I<0> ACLK_N_I ADDR_I<0> q_int<0> net2<6> VDD ++ VSS / RSC_IHPSG13_DFNQMX2IX1 +XI11<8> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI11<7> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI11<6> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI11<5> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI11<4> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI11<3> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI11<2> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI11<1> VDD VSS / RSC_IHPSG13_FILLCAP8 +.ENDS + +.SUBCKT RM_IHPSG13_512x32_c2_1P_COLDRV13X8 ADDR_COL_I<1> ADDR_COL_I<0> ADDR_COL_O<1> ++ ADDR_COL_O<0> ADDR_DEC_I<7> ADDR_DEC_I<6> ADDR_DEC_I<5> ADDR_DEC_I<4> ++ ADDR_DEC_I<3> ADDR_DEC_I<2> ADDR_DEC_I<1> ADDR_DEC_I<0> ADDR_DEC_O<7> ++ ADDR_DEC_O<6> ADDR_DEC_O<5> ADDR_DEC_O<4> ADDR_DEC_O<3> ADDR_DEC_O<2> ++ ADDR_DEC_O<1> ADDR_DEC_O<0> DCLK_I DCLK_O RCLK_I RCLK_O WCLK_I WCLK_O ++ VDD VSS +XI0<1> VDD VSS / RSC_IHPSG13_FILLCAP4 +XI0<0> VDD VSS / RSC_IHPSG13_FILLCAP4 +XADDR_COL_DRV<1> ADDR_COL_I<1> ADDR_COL_O<1> VDD VSS / ++ RSC_IHPSG13_CBUFX8 +XADDR_COL_DRV<0> ADDR_COL_I<0> ADDR_COL_O<0> VDD VSS / ++ RSC_IHPSG13_CBUFX8 +XADDR_DEC_DRV<7> ADDR_DEC_I<7> ADDR_DEC_O<7> VDD VSS / ++ RSC_IHPSG13_CBUFX8 +XADDR_DEC_DRV<6> ADDR_DEC_I<6> ADDR_DEC_O<6> VDD VSS / ++ RSC_IHPSG13_CBUFX8 +XADDR_DEC_DRV<5> ADDR_DEC_I<5> ADDR_DEC_O<5> VDD VSS / ++ RSC_IHPSG13_CBUFX8 +XADDR_DEC_DRV<4> ADDR_DEC_I<4> ADDR_DEC_O<4> VDD VSS / ++ RSC_IHPSG13_CBUFX8 +XADDR_DEC_DRV<3> ADDR_DEC_I<3> ADDR_DEC_O<3> VDD VSS / ++ RSC_IHPSG13_CBUFX8 +XADDR_DEC_DRV<2> ADDR_DEC_I<2> ADDR_DEC_O<2> VDD VSS / ++ RSC_IHPSG13_CBUFX8 +XADDR_DEC_DRV<1> ADDR_DEC_I<1> ADDR_DEC_O<1> VDD VSS / ++ RSC_IHPSG13_CBUFX8 +XADDR_DEC_DRV<0> ADDR_DEC_I<0> ADDR_DEC_O<0> VDD VSS / ++ RSC_IHPSG13_CBUFX8 +XDCLK_DRV DCLK_I DCLK_O VDD VSS / RSC_IHPSG13_CBUFX8 +XRCLK_DRV RCLK_I RCLK_O VDD VSS / RSC_IHPSG13_CBUFX8 +XWCLK_DRV WCLK_I WCLK_O VDD VSS / RSC_IHPSG13_CBUFX8 +.ENDS +.SUBCKT RM_IHPSG13_512x32_c2_1P_WLDRV16X8 A<15> A<14> A<13> A<12> A<11> A<10> A<9> A<8> ++ A<7> A<6> A<5> A<4> A<3> A<2> A<1> A<0> Z<15> Z<14> Z<13> Z<12> Z<11> Z<10> ++ Z<9> Z<8> Z<7> Z<6> Z<5> Z<4> Z<3> Z<2> Z<1> Z<0> VDD VSS +XBUF<15> A<15> Z<15> VDD VSS / RSC_IHPSG13_WLDRVX8 +XBUF<14> A<14> Z<14> VDD VSS / RSC_IHPSG13_WLDRVX8 +XBUF<13> A<13> Z<13> VDD VSS / RSC_IHPSG13_WLDRVX8 +XBUF<12> A<12> Z<12> VDD VSS / RSC_IHPSG13_WLDRVX8 +XBUF<11> A<11> Z<11> VDD VSS / RSC_IHPSG13_WLDRVX8 +XBUF<10> A<10> Z<10> VDD VSS / RSC_IHPSG13_WLDRVX8 +XBUF<9> A<9> Z<9> VDD VSS / RSC_IHPSG13_WLDRVX8 +XBUF<8> A<8> Z<8> VDD VSS / RSC_IHPSG13_WLDRVX8 +XBUF<7> A<7> Z<7> VDD VSS / RSC_IHPSG13_WLDRVX8 +XBUF<6> A<6> Z<6> VDD VSS / RSC_IHPSG13_WLDRVX8 +XBUF<5> A<5> Z<5> VDD VSS / RSC_IHPSG13_WLDRVX8 +XBUF<4> A<4> Z<4> VDD VSS / RSC_IHPSG13_WLDRVX8 +XBUF<3> A<3> Z<3> VDD VSS / RSC_IHPSG13_WLDRVX8 +XBUF<2> A<2> Z<2> VDD VSS / RSC_IHPSG13_WLDRVX8 +XBUF<1> A<1> Z<1> VDD VSS / RSC_IHPSG13_WLDRVX8 +XBUF<0> A<0> Z<0> VDD VSS / RSC_IHPSG13_WLDRVX8 +.ENDS + + + +.SUBCKT RM_IHPSG13_512x32_c2_1P_ROWDEC6 ADDR_N_I<5> ADDR_N_I<4> ADDR_N_I<3> ADDR_N_I<2> ++ ADDR_N_I<1> ADDR_N_I<0> CS_I ECLK_I WL_O<63> WL_O<62> WL_O<61> WL_O<60> ++ WL_O<59> WL_O<58> WL_O<57> WL_O<56> WL_O<55> WL_O<54> WL_O<53> WL_O<52> ++ WL_O<51> WL_O<50> WL_O<49> WL_O<48> WL_O<47> WL_O<46> WL_O<45> WL_O<44> ++ WL_O<43> WL_O<42> WL_O<41> WL_O<40> WL_O<39> WL_O<38> WL_O<37> WL_O<36> ++ WL_O<35> WL_O<34> WL_O<33> WL_O<32> WL_O<31> WL_O<30> WL_O<29> WL_O<28> ++ WL_O<27> WL_O<26> WL_O<25> WL_O<24> WL_O<23> WL_O<22> WL_O<21> WL_O<20> ++ WL_O<19> WL_O<18> WL_O<17> WL_O<16> WL_O<15> WL_O<14> WL_O<13> WL_O<12> ++ WL_O<11> WL_O<10> WL_O<9> WL_O<8> WL_O<7> WL_O<6> WL_O<5> WL_O<4> WL_O<3> ++ WL_O<2> WL_O<1> WL_O<0> VDD VSS +XDEC11 ADDR_N_I<5> ADDR_N_I<4> CS_I CS00<3> VDD VSS / ++ RM_IHPSG13_512x32_c2_1P_DEC03 +XDEC00 ADDR_N_I<5> ADDR_N_I<4> CS_I CS00<0> VDD VSS / ++ RM_IHPSG13_512x32_c2_1P_DEC00 +XDEC01 ADDR_N_I<5> ADDR_N_I<4> CS_I CS00<1> VDD VSS / ++ RM_IHPSG13_512x32_c2_1P_DEC01 +XDEC10 ADDR_N_I<5> ADDR_N_I<4> CS_I CS00<2> VDD VSS / ++ RM_IHPSG13_512x32_c2_1P_DEC02 +XSEL<3> ADDR_N_I<3> ADDR_N_I<2> ADDR_N_I<1> ADDR_N_I<0> CS00<3> ECLK_H<3> ++ ECLK_H<4> ECLK_B<3> ECLK_B<4> WL_O<63> WL_O<62> WL_O<61> WL_O<60> WL_O<59> ++ WL_O<58> WL_O<57> WL_O<56> WL_O<55> WL_O<54> WL_O<53> WL_O<52> WL_O<51> ++ WL_O<50> WL_O<49> WL_O<48> VDD VSS / RM_IHPSG13_512x32_c2_1P_DEC04 +XSEL<2> ADDR_N_I<3> ADDR_N_I<2> ADDR_N_I<1> ADDR_N_I<0> CS00<2> ECLK_H<2> ++ ECLK_H<3> ECLK_B<2> ECLK_B<3> WL_O<47> WL_O<46> WL_O<45> WL_O<44> WL_O<43> ++ WL_O<42> WL_O<41> WL_O<40> WL_O<39> WL_O<38> WL_O<37> WL_O<36> WL_O<35> ++ WL_O<34> WL_O<33> WL_O<32> VDD VSS / RM_IHPSG13_512x32_c2_1P_DEC04 +XSEL<1> ADDR_N_I<3> ADDR_N_I<2> ADDR_N_I<1> ADDR_N_I<0> CS00<1> ECLK_H<1> ++ ECLK_H<2> ECLK_B<1> ECLK_B<2> WL_O<31> WL_O<30> WL_O<29> WL_O<28> WL_O<27> ++ WL_O<26> WL_O<25> WL_O<24> WL_O<23> WL_O<22> WL_O<21> WL_O<20> WL_O<19> ++ WL_O<18> WL_O<17> WL_O<16> VDD VSS / RM_IHPSG13_512x32_c2_1P_DEC04 +XSEL<0> ADDR_N_I<3> ADDR_N_I<2> ADDR_N_I<1> ADDR_N_I<0> CS00<0> ECLK_I ++ ECLK_H<1> ECLK_B<0> ECLK_B<1> WL_O<15> WL_O<14> WL_O<13> WL_O<12> WL_O<11> ++ WL_O<10> WL_O<9> WL_O<8> WL_O<7> WL_O<6> WL_O<5> WL_O<4> WL_O<3> WL_O<2> ++ WL_O<1> WL_O<0> VDD VSS / RM_IHPSG13_512x32_c2_1P_DEC04 +XL2<24> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<23> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<22> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<21> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<20> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<19> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<18> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<17> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<16> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<15> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<14> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<13> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<12> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<11> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<10> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<9> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<8> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<7> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<6> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<5> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<4> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<3> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<2> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<1> VDD VSS / RSC_IHPSG13_FILLCAP8 +.ENDS +.SUBCKT RM_IHPSG13_512x32_c2_1P_ROWREG6 ACLK_N_I ADDR_I<5> ADDR_I<4> ADDR_I<3> ADDR_I<2> ++ ADDR_I<1> ADDR_I<0> ADDR_N_O<5> ADDR_N_O<4> ADDR_N_O<3> ADDR_N_O<2> ++ ADDR_N_O<1> ADDR_N_O<0> BIST_ADDR_I<5> BIST_ADDR_I<4> BIST_ADDR_I<3> ++ BIST_ADDR_I<2> BIST_ADDR_I<1> BIST_ADDR_I<0> BIST_EN_I VDD VSS +XINV<5> q_int<5> qn_int<5> VDD VSS / RSC_IHPSG13_CINVX2 +XINV<4> q_int<4> qn_int<4> VDD VSS / RSC_IHPSG13_CINVX2 +XINV<3> q_int<3> qn_int<3> VDD VSS / RSC_IHPSG13_CINVX2 +XINV<2> q_int<2> qn_int<2> VDD VSS / RSC_IHPSG13_CINVX2 +XINV<1> q_int<1> qn_int<1> VDD VSS / RSC_IHPSG13_CINVX2 +XINV<0> q_int<0> qn_int<0> VDD VSS / RSC_IHPSG13_CINVX2 +XDRV<5> qn_int<5> ADDR_N_O<5> VDD VSS / RSC_IHPSG13_CINVX8 +XDRV<4> qn_int<4> ADDR_N_O<4> VDD VSS / RSC_IHPSG13_CINVX8 +XDRV<3> qn_int<3> ADDR_N_O<3> VDD VSS / RSC_IHPSG13_CINVX8 +XDRV<2> qn_int<2> ADDR_N_O<2> VDD VSS / RSC_IHPSG13_CINVX8 +XDRV<1> qn_int<1> ADDR_N_O<1> VDD VSS / RSC_IHPSG13_CINVX8 +XDRV<0> qn_int<0> ADDR_N_O<0> VDD VSS / RSC_IHPSG13_CINVX8 +XDFF<5> BIST_EN_I BIST_ADDR_I<5> ACLK_N_I ADDR_I<5> q_int<5> net2<0> VDD ++ VSS / RSC_IHPSG13_DFNQMX2IX1 +XDFF<4> BIST_EN_I BIST_ADDR_I<4> ACLK_N_I ADDR_I<4> q_int<4> net2<1> VDD ++ VSS / RSC_IHPSG13_DFNQMX2IX1 +XDFF<3> BIST_EN_I BIST_ADDR_I<3> ACLK_N_I ADDR_I<3> q_int<3> net2<2> VDD ++ VSS / RSC_IHPSG13_DFNQMX2IX1 +XDFF<2> BIST_EN_I BIST_ADDR_I<2> ACLK_N_I ADDR_I<2> q_int<2> net2<3> VDD ++ VSS / RSC_IHPSG13_DFNQMX2IX1 +XDFF<1> BIST_EN_I BIST_ADDR_I<1> ACLK_N_I ADDR_I<1> q_int<1> net2<4> VDD ++ VSS / RSC_IHPSG13_DFNQMX2IX1 +XDFF<0> BIST_EN_I BIST_ADDR_I<0> ACLK_N_I ADDR_I<0> q_int<0> net2<5> VDD ++ VSS / RSC_IHPSG13_DFNQMX2IX1 +XI11<12> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI11<11> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI11<10> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI11<9> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI11<8> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI11<7> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI11<6> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI11<5> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI11<4> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI11<3> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI11<2> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI11<1> VDD VSS / RSC_IHPSG13_FILLCAP8 +.ENDS + + +.SUBCKT RM_IHPSG13_512x32_c2_1P_COLUMN_pcell_0 A_BLC_BOT<1> A_BLC_BOT<0> A_BLC_TOP<1> A_BLC_TOP<0> A_BLT_BOT<1> A_BLT_BOT<0> A_BLT_TOP<1> A_BLT_TOP<0> A_LWL<127> A_LWL<126> A_LWL<125> A_LWL<124> A_LWL<123> A_LWL<122> A_LWL<121> A_LWL<120> A_LWL<119> A_LWL<118> A_LWL<117> A_LWL<116> A_LWL<115> A_LWL<114> A_LWL<113> A_LWL<112> A_LWL<111> A_LWL<110> A_LWL<109> A_LWL<108> A_LWL<107> A_LWL<106> A_LWL<105> A_LWL<104> A_LWL<103> A_LWL<102> A_LWL<101> A_LWL<100> A_LWL<99> A_LWL<98> A_LWL<97> A_LWL<96> A_LWL<95> A_LWL<94> A_LWL<93> A_LWL<92> A_LWL<91> A_LWL<90> A_LWL<89> A_LWL<88> A_LWL<87> A_LWL<86> A_LWL<85> A_LWL<84> A_LWL<83> A_LWL<82> A_LWL<81> A_LWL<80> A_LWL<79> A_LWL<78> A_LWL<77> A_LWL<76> A_LWL<75> A_LWL<74> A_LWL<73> A_LWL<72> A_LWL<71> A_LWL<70> A_LWL<69> A_LWL<68> A_LWL<67> A_LWL<66> A_LWL<65> A_LWL<64> A_LWL<63> A_LWL<62> A_LWL<61> A_LWL<60> A_LWL<59> A_LWL<58> A_LWL<57> A_LWL<56> A_LWL<55> A_LWL<54> A_LWL<53> A_LWL<52> A_LWL<51> A_LWL<50> A_LWL<49> A_LWL<48> A_LWL<47> A_LWL<46> A_LWL<45> A_LWL<44> A_LWL<43> A_LWL<42> A_LWL<41> A_LWL<40> A_LWL<39> A_LWL<38> A_LWL<37> A_LWL<36> A_LWL<35> A_LWL<34> A_LWL<33> A_LWL<32> A_LWL<31> A_LWL<30> A_LWL<29> A_LWL<28> A_LWL<27> A_LWL<26> A_LWL<25> A_LWL<24> A_LWL<23> A_LWL<22> A_LWL<21> A_LWL<20> A_LWL<19> A_LWL<18> A_LWL<17> A_LWL<16> A_LWL<15> A_LWL<14> A_LWL<13> A_LWL<12> A_LWL<11> A_LWL<10> A_LWL<9> A_LWL<8> A_LWL<7> A_LWL<6> A_LWL<5> A_LWL<4> A_LWL<3> A_LWL<2> A_LWL<1> A_LWL<0> A_RWL<127> A_RWL<126> A_RWL<125> A_RWL<124> A_RWL<123> A_RWL<122> A_RWL<121> A_RWL<120> A_RWL<119> A_RWL<118> A_RWL<117> A_RWL<116> A_RWL<115> A_RWL<114> A_RWL<113> A_RWL<112> A_RWL<111> A_RWL<110> A_RWL<109> A_RWL<108> A_RWL<107> A_RWL<106> A_RWL<105> A_RWL<104> A_RWL<103> A_RWL<102> A_RWL<101> A_RWL<100> A_RWL<99> A_RWL<98> A_RWL<97> A_RWL<96> A_RWL<95> A_RWL<94> A_RWL<93> A_RWL<92> A_RWL<91> A_RWL<90> A_RWL<89> A_RWL<88> A_RWL<87> A_RWL<86> A_RWL<85> A_RWL<84> A_RWL<83> A_RWL<82> A_RWL<81> A_RWL<80> A_RWL<79> A_RWL<78> A_RWL<77> A_RWL<76> A_RWL<75> A_RWL<74> A_RWL<73> A_RWL<72> A_RWL<71> A_RWL<70> A_RWL<69> A_RWL<68> A_RWL<67> A_RWL<66> A_RWL<65> A_RWL<64> A_RWL<63> A_RWL<62> A_RWL<61> A_RWL<60> A_RWL<59> A_RWL<58> A_RWL<57> A_RWL<56> A_RWL<55> A_RWL<54> A_RWL<53> A_RWL<52> A_RWL<51> A_RWL<50> A_RWL<49> A_RWL<48> A_RWL<47> A_RWL<46> A_RWL<45> A_RWL<44> A_RWL<43> A_RWL<42> A_RWL<41> A_RWL<40> A_RWL<39> A_RWL<38> A_RWL<37> A_RWL<36> A_RWL<35> A_RWL<34> A_RWL<33> A_RWL<32> A_RWL<31> A_RWL<30> A_RWL<29> A_RWL<28> A_RWL<27> A_RWL<26> A_RWL<25> A_RWL<24> A_RWL<23> A_RWL<22> A_RWL<21> A_RWL<20> A_RWL<19> A_RWL<18> A_RWL<17> A_RWL<16> A_RWL<15> A_RWL<14> A_RWL<13> A_RWL<12> A_RWL<11> A_RWL<10> A_RWL<9> A_RWL<8> A_RWL<7> A_RWL<6> A_RWL<5> A_RWL<4> A_RWL<3> A_RWL<2> A_RWL<1> A_RWL<0> VDD_CORE VSS +XRAM<8> A_BLC<13> A_BLC<12> A_BLC_TOP<1> A_BLC_TOP<0> A_BLT<13> A_BLT<12> A_BLT_TOP<1> A_BLT_TOP<0> A_LWL<127> A_LWL<126> A_LWL<125> A_LWL<124> A_LWL<123> A_LWL<122> A_LWL<121> A_LWL<120> A_LWL<119> A_LWL<118> A_LWL<117> A_LWL<116> A_LWL<115> A_LWL<114> A_LWL<113> A_LWL<112> A_RWL<127> A_RWL<126> A_RWL<125> A_RWL<124> A_RWL<123> A_RWL<122> A_RWL<121> A_RWL<120> A_RWL<119> A_RWL<118> A_RWL<117> A_RWL<116> A_RWL<115> A_RWL<114> A_RWL<113> A_RWL<112> VDD_CORE VSS / RM_IHPSG13_512x32_c2_1P_BITKIT_16x2_SRAM +XRAM<7> A_BLC<11> A_BLC<10> A_BLC<13> A_BLC<12> A_BLT<11> A_BLT<10> A_BLT<13> A_BLT<12> A_LWL<111> A_LWL<110> A_LWL<109> A_LWL<108> A_LWL<107> A_LWL<106> A_LWL<105> A_LWL<104> A_LWL<103> A_LWL<102> A_LWL<101> A_LWL<100> A_LWL<99> A_LWL<98> A_LWL<97> A_LWL<96> A_RWL<111> A_RWL<110> A_RWL<109> A_RWL<108> A_RWL<107> A_RWL<106> A_RWL<105> A_RWL<104> A_RWL<103> A_RWL<102> A_RWL<101> A_RWL<100> A_RWL<99> A_RWL<98> A_RWL<97> A_RWL<96> VDD_CORE VSS / RM_IHPSG13_512x32_c2_1P_BITKIT_16x2_SRAM +XRAM<6> A_BLC<9> A_BLC<8> A_BLC<11> A_BLC<10> A_BLT<9> A_BLT<8> A_BLT<11> A_BLT<10> A_LWL<95> A_LWL<94> A_LWL<93> A_LWL<92> A_LWL<91> A_LWL<90> A_LWL<89> A_LWL<88> A_LWL<87> A_LWL<86> A_LWL<85> A_LWL<84> A_LWL<83> A_LWL<82> A_LWL<81> A_LWL<80> A_RWL<95> A_RWL<94> A_RWL<93> A_RWL<92> A_RWL<91> A_RWL<90> A_RWL<89> A_RWL<88> A_RWL<87> A_RWL<86> A_RWL<85> A_RWL<84> A_RWL<83> A_RWL<82> A_RWL<81> A_RWL<80> VDD_CORE VSS / RM_IHPSG13_512x32_c2_1P_BITKIT_16x2_SRAM +XRAM<5> A_BLC<7> A_BLC<6> A_BLC<9> A_BLC<8> A_BLT<7> A_BLT<6> A_BLT<9> A_BLT<8> A_LWL<79> A_LWL<78> A_LWL<77> A_LWL<76> A_LWL<75> A_LWL<74> A_LWL<73> A_LWL<72> A_LWL<71> A_LWL<70> A_LWL<69> A_LWL<68> A_LWL<67> A_LWL<66> A_LWL<65> A_LWL<64> A_RWL<79> A_RWL<78> A_RWL<77> A_RWL<76> A_RWL<75> A_RWL<74> A_RWL<73> A_RWL<72> A_RWL<71> A_RWL<70> A_RWL<69> A_RWL<68> A_RWL<67> A_RWL<66> A_RWL<65> A_RWL<64> VDD_CORE VSS / RM_IHPSG13_512x32_c2_1P_BITKIT_16x2_SRAM +XRAM<4> A_BLC<5> A_BLC<4> A_BLC<7> A_BLC<6> A_BLT<5> A_BLT<4> A_BLT<7> A_BLT<6> A_LWL<63> A_LWL<62> A_LWL<61> A_LWL<60> A_LWL<59> A_LWL<58> A_LWL<57> A_LWL<56> A_LWL<55> A_LWL<54> A_LWL<53> A_LWL<52> A_LWL<51> A_LWL<50> A_LWL<49> A_LWL<48> A_RWL<63> A_RWL<62> A_RWL<61> A_RWL<60> A_RWL<59> A_RWL<58> A_RWL<57> A_RWL<56> A_RWL<55> A_RWL<54> A_RWL<53> A_RWL<52> A_RWL<51> A_RWL<50> A_RWL<49> A_RWL<48> VDD_CORE VSS / RM_IHPSG13_512x32_c2_1P_BITKIT_16x2_SRAM +XRAM<3> A_BLC<3> A_BLC<2> A_BLC<5> A_BLC<4> A_BLT<3> A_BLT<2> A_BLT<5> A_BLT<4> A_LWL<47> A_LWL<46> A_LWL<45> A_LWL<44> A_LWL<43> A_LWL<42> A_LWL<41> A_LWL<40> A_LWL<39> A_LWL<38> A_LWL<37> A_LWL<36> A_LWL<35> A_LWL<34> A_LWL<33> A_LWL<32> A_RWL<47> A_RWL<46> A_RWL<45> A_RWL<44> A_RWL<43> A_RWL<42> A_RWL<41> A_RWL<40> A_RWL<39> A_RWL<38> A_RWL<37> A_RWL<36> A_RWL<35> A_RWL<34> A_RWL<33> A_RWL<32> VDD_CORE VSS / RM_IHPSG13_512x32_c2_1P_BITKIT_16x2_SRAM +XRAM<2> A_BLC<1> A_BLC<0> A_BLC<3> A_BLC<2> A_BLT<1> A_BLT<0> A_BLT<3> A_BLT<2> A_LWL<31> A_LWL<30> A_LWL<29> A_LWL<28> A_LWL<27> A_LWL<26> A_LWL<25> A_LWL<24> A_LWL<23> A_LWL<22> A_LWL<21> A_LWL<20> A_LWL<19> A_LWL<18> A_LWL<17> A_LWL<16> A_RWL<31> A_RWL<30> A_RWL<29> A_RWL<28> A_RWL<27> A_RWL<26> A_RWL<25> A_RWL<24> A_RWL<23> A_RWL<22> A_RWL<21> A_RWL<20> A_RWL<19> A_RWL<18> A_RWL<17> A_RWL<16> VDD_CORE VSS / RM_IHPSG13_512x32_c2_1P_BITKIT_16x2_SRAM +XRAM<1> A_BLC_BOT<1> A_BLC_BOT<0> A_BLC<1> A_BLC<0> A_BLT_BOT<1> A_BLT_BOT<0> A_BLT<1> A_BLT<0> A_LWL<15> A_LWL<14> A_LWL<13> A_LWL<12> A_LWL<11> A_LWL<10> A_LWL<9> A_LWL<8> A_LWL<7> A_LWL<6> A_LWL<5> A_LWL<4> A_LWL<3> A_LWL<2> A_LWL<1> A_LWL<0> A_RWL<15> A_RWL<14> A_RWL<13> A_RWL<12> A_RWL<11> A_RWL<10> A_RWL<9> A_RWL<8> A_RWL<7> A_RWL<6> A_RWL<5> A_RWL<4> A_RWL<3> A_RWL<2> A_RWL<1> A_RWL<0> VDD_CORE VSS / RM_IHPSG13_512x32_c2_1P_BITKIT_16x2_SRAM +XEDGE<1> A_BLC_TOP<1> A_BLC_TOP<0> A_BLT_TOP<1> A_BLT_TOP<0> VDD_CORE VSS / RM_IHPSG13_512x32_c2_1P_BITKIT_16x2_EDGE_TB +XEDGE<0> A_BLC_BOT<1> A_BLC_BOT<0> A_BLT_BOT<1> A_BLT_BOT<0> VDD_CORE VSS / RM_IHPSG13_512x32_c2_1P_BITKIT_16x2_EDGE_TB +.ENDS + + + + +.SUBCKT RM_IHPSG13_512x32_c2_1P_MATRIX_pcell_1 A_BLC<63> A_BLC<62> A_BLC<61> A_BLC<60> A_BLC<59> A_BLC<58> A_BLC<57> A_BLC<56> A_BLC<55> A_BLC<54> A_BLC<53> A_BLC<52> A_BLC<51> A_BLC<50> A_BLC<49> A_BLC<48> A_BLC<47> A_BLC<46> A_BLC<45> A_BLC<44> A_BLC<43> A_BLC<42> A_BLC<41> A_BLC<40> A_BLC<39> A_BLC<38> A_BLC<37> A_BLC<36> A_BLC<35> A_BLC<34> A_BLC<33> A_BLC<32> A_BLC<31> A_BLC<30> A_BLC<29> A_BLC<28> A_BLC<27> A_BLC<26> A_BLC<25> A_BLC<24> A_BLC<23> A_BLC<22> A_BLC<21> A_BLC<20> A_BLC<19> A_BLC<18> A_BLC<17> A_BLC<16> A_BLC<15> A_BLC<14> A_BLC<13> A_BLC<12> A_BLC<11> A_BLC<10> A_BLC<9> A_BLC<8> A_BLC<7> A_BLC<6> A_BLC<5> A_BLC<4> A_BLC<3> A_BLC<2> A_BLC<1> A_BLC<0> A_BLT<63> A_BLT<62> A_BLT<61> A_BLT<60> A_BLT<59> A_BLT<58> A_BLT<57> A_BLT<56> A_BLT<55> A_BLT<54> A_BLT<53> A_BLT<52> A_BLT<51> A_BLT<50> A_BLT<49> A_BLT<48> A_BLT<47> A_BLT<46> A_BLT<45> A_BLT<44> A_BLT<43> A_BLT<42> A_BLT<41> A_BLT<40> A_BLT<39> A_BLT<38> A_BLT<37> A_BLT<36> A_BLT<35> A_BLT<34> A_BLT<33> A_BLT<32> A_BLT<31> A_BLT<30> A_BLT<29> A_BLT<28> A_BLT<27> A_BLT<26> A_BLT<25> A_BLT<24> A_BLT<23> A_BLT<22> A_BLT<21> A_BLT<20> A_BLT<19> A_BLT<18> A_BLT<17> A_BLT<16> A_BLT<15> A_BLT<14> A_BLT<13> A_BLT<12> A_BLT<11> A_BLT<10> A_BLT<9> A_BLT<8> A_BLT<7> A_BLT<6> A_BLT<5> A_BLT<4> A_BLT<3> A_BLT<2> A_BLT<1> A_BLT<0> A_WL<127> A_WL<126> A_WL<125> A_WL<124> A_WL<123> A_WL<122> A_WL<121> A_WL<120> A_WL<119> A_WL<118> A_WL<117> A_WL<116> A_WL<115> A_WL<114> A_WL<113> A_WL<112> A_WL<111> A_WL<110> A_WL<109> A_WL<108> A_WL<107> A_WL<106> A_WL<105> A_WL<104> A_WL<103> A_WL<102> A_WL<101> A_WL<100> A_WL<99> A_WL<98> A_WL<97> A_WL<96> A_WL<95> A_WL<94> A_WL<93> A_WL<92> A_WL<91> A_WL<90> A_WL<89> A_WL<88> A_WL<87> A_WL<86> A_WL<85> A_WL<84> A_WL<83> A_WL<82> A_WL<81> A_WL<80> A_WL<79> A_WL<78> A_WL<77> A_WL<76> A_WL<75> A_WL<74> A_WL<73> A_WL<72> A_WL<71> A_WL<70> A_WL<69> A_WL<68> A_WL<67> A_WL<66> A_WL<65> A_WL<64> A_WL<63> A_WL<62> A_WL<61> A_WL<60> A_WL<59> A_WL<58> A_WL<57> A_WL<56> A_WL<55> A_WL<54> A_WL<53> A_WL<52> A_WL<51> A_WL<50> A_WL<49> A_WL<48> A_WL<47> A_WL<46> A_WL<45> A_WL<44> A_WL<43> A_WL<42> A_WL<41> A_WL<40> A_WL<39> A_WL<38> A_WL<37> A_WL<36> A_WL<35> A_WL<34> A_WL<33> A_WL<32> A_WL<31> A_WL<30> A_WL<29> A_WL<28> A_WL<27> A_WL<26> A_WL<25> A_WL<24> A_WL<23> A_WL<22> A_WL<21> A_WL<20> A_WL<19> A_WL<18> A_WL<17> A_WL<16> A_WL<15> A_WL<14> A_WL<13> A_WL<12> A_WL<11> A_WL<10> A_WL<9> A_WL<8> A_WL<7> A_WL<6> A_WL<5> A_WL<4> A_WL<3> A_WL<2> A_WL<1> A_WL<0> VDD_CORE VSS +XCORNER<3> VDD_CORE VSS / RM_IHPSG13_512x32_c2_1P_BITKIT_16x2_CORNER +XCORNER<2> VDD_CORE VSS / RM_IHPSG13_512x32_c2_1P_BITKIT_16x2_CORNER +XCORNER<1> VDD_CORE VSS / RM_IHPSG13_512x32_c2_1P_BITKIT_16x2_CORNER +XCORNER<0> VDD_CORE VSS / RM_IHPSG13_512x32_c2_1P_BITKIT_16x2_CORNER +XRAMEDGE_L<7> A_WL<127> A_WL<126> A_WL<125> A_WL<124> A_WL<123> A_WL<122> A_WL<121> A_WL<120> A_WL<119> A_WL<118> A_WL<117> A_WL<116> A_WL<115> A_WL<114> A_WL<113> A_WL<112> VDD_CORE VSS / RM_IHPSG13_512x32_c2_1P_BITKIT_16x2_EDGE_LR +XRAMEDGE_L<6> A_WL<111> A_WL<110> A_WL<109> A_WL<108> A_WL<107> A_WL<106> A_WL<105> A_WL<104> A_WL<103> A_WL<102> A_WL<101> A_WL<100> A_WL<99> A_WL<98> A_WL<97> A_WL<96> VDD_CORE VSS / RM_IHPSG13_512x32_c2_1P_BITKIT_16x2_EDGE_LR +XRAMEDGE_L<5> A_WL<95> A_WL<94> A_WL<93> A_WL<92> A_WL<91> A_WL<90> A_WL<89> A_WL<88> A_WL<87> A_WL<86> A_WL<85> A_WL<84> A_WL<83> A_WL<82> A_WL<81> A_WL<80> VDD_CORE VSS / RM_IHPSG13_512x32_c2_1P_BITKIT_16x2_EDGE_LR +XRAMEDGE_L<4> A_WL<79> A_WL<78> A_WL<77> A_WL<76> A_WL<75> A_WL<74> A_WL<73> A_WL<72> A_WL<71> A_WL<70> A_WL<69> A_WL<68> A_WL<67> A_WL<66> A_WL<65> A_WL<64> VDD_CORE VSS / RM_IHPSG13_512x32_c2_1P_BITKIT_16x2_EDGE_LR +XRAMEDGE_L<3> A_WL<63> A_WL<62> A_WL<61> A_WL<60> A_WL<59> A_WL<58> A_WL<57> A_WL<56> A_WL<55> A_WL<54> A_WL<53> A_WL<52> A_WL<51> A_WL<50> A_WL<49> A_WL<48> VDD_CORE VSS / RM_IHPSG13_512x32_c2_1P_BITKIT_16x2_EDGE_LR +XRAMEDGE_L<2> A_WL<47> A_WL<46> A_WL<45> A_WL<44> A_WL<43> A_WL<42> A_WL<41> A_WL<40> A_WL<39> A_WL<38> A_WL<37> A_WL<36> A_WL<35> A_WL<34> A_WL<33> A_WL<32> VDD_CORE VSS / RM_IHPSG13_512x32_c2_1P_BITKIT_16x2_EDGE_LR +XRAMEDGE_L<1> A_WL<31> A_WL<30> A_WL<29> A_WL<28> A_WL<27> A_WL<26> A_WL<25> A_WL<24> A_WL<23> A_WL<22> A_WL<21> A_WL<20> A_WL<19> A_WL<18> A_WL<17> A_WL<16> VDD_CORE VSS / RM_IHPSG13_512x32_c2_1P_BITKIT_16x2_EDGE_LR +XRAMEDGE_L<0> A_WL<15> A_WL<14> A_WL<13> A_WL<12> A_WL<11> A_WL<10> A_WL<9> A_WL<8> A_WL<7> A_WL<6> A_WL<5> A_WL<4> A_WL<3> A_WL<2> A_WL<1> A_WL<0> VDD_CORE VSS / RM_IHPSG13_512x32_c2_1P_BITKIT_16x2_EDGE_LR +XRAMEDGE_R<7> A_IWL<4095> A_IWL<4094> A_IWL<4093> A_IWL<4092> A_IWL<4091> A_IWL<4090> A_IWL<4089> A_IWL<4088> A_IWL<4087> A_IWL<4086> A_IWL<4085> A_IWL<4084> A_IWL<4083> A_IWL<4082> A_IWL<4081> A_IWL<4080> VDD_CORE VSS / RM_IHPSG13_512x32_c2_1P_BITKIT_16x2_EDGE_LR +XRAMEDGE_R<6> A_IWL<4079> A_IWL<4078> A_IWL<4077> A_IWL<4076> A_IWL<4075> A_IWL<4074> A_IWL<4073> A_IWL<4072> A_IWL<4071> A_IWL<4070> A_IWL<4069> A_IWL<4068> A_IWL<4067> A_IWL<4066> A_IWL<4065> A_IWL<4064> VDD_CORE VSS / RM_IHPSG13_512x32_c2_1P_BITKIT_16x2_EDGE_LR +XRAMEDGE_R<5> A_IWL<4063> A_IWL<4062> A_IWL<4061> A_IWL<4060> A_IWL<4059> A_IWL<4058> A_IWL<4057> A_IWL<4056> A_IWL<4055> A_IWL<4054> A_IWL<4053> A_IWL<4052> A_IWL<4051> A_IWL<4050> A_IWL<4049> A_IWL<4048> VDD_CORE VSS / RM_IHPSG13_512x32_c2_1P_BITKIT_16x2_EDGE_LR +XRAMEDGE_R<4> A_IWL<4047> A_IWL<4046> A_IWL<4045> A_IWL<4044> A_IWL<4043> A_IWL<4042> A_IWL<4041> A_IWL<4040> A_IWL<4039> A_IWL<4038> A_IWL<4037> A_IWL<4036> A_IWL<4035> A_IWL<4034> A_IWL<4033> A_IWL<4032> VDD_CORE VSS / RM_IHPSG13_512x32_c2_1P_BITKIT_16x2_EDGE_LR +XRAMEDGE_R<3> A_IWL<4031> A_IWL<4030> A_IWL<4029> A_IWL<4028> A_IWL<4027> A_IWL<4026> A_IWL<4025> A_IWL<4024> A_IWL<4023> A_IWL<4022> A_IWL<4021> A_IWL<4020> A_IWL<4019> A_IWL<4018> A_IWL<4017> A_IWL<4016> VDD_CORE VSS / RM_IHPSG13_512x32_c2_1P_BITKIT_16x2_EDGE_LR +XRAMEDGE_R<2> A_IWL<4015> A_IWL<4014> A_IWL<4013> A_IWL<4012> A_IWL<4011> A_IWL<4010> A_IWL<4009> A_IWL<4008> A_IWL<4007> A_IWL<4006> A_IWL<4005> A_IWL<4004> A_IWL<4003> A_IWL<4002> A_IWL<4001> A_IWL<4000> VDD_CORE VSS / RM_IHPSG13_512x32_c2_1P_BITKIT_16x2_EDGE_LR +XRAMEDGE_R<1> A_IWL<3999> A_IWL<3998> A_IWL<3997> A_IWL<3996> A_IWL<3995> A_IWL<3994> A_IWL<3993> A_IWL<3992> A_IWL<3991> A_IWL<3990> A_IWL<3989> A_IWL<3988> A_IWL<3987> A_IWL<3986> A_IWL<3985> A_IWL<3984> VDD_CORE VSS / RM_IHPSG13_512x32_c2_1P_BITKIT_16x2_EDGE_LR +XRAMEDGE_R<0> A_IWL<3983> A_IWL<3982> A_IWL<3981> A_IWL<3980> A_IWL<3979> A_IWL<3978> A_IWL<3977> A_IWL<3976> A_IWL<3975> A_IWL<3974> A_IWL<3973> A_IWL<3972> A_IWL<3971> A_IWL<3970> A_IWL<3969> A_IWL<3968> VDD_CORE VSS / RM_IHPSG13_512x32_c2_1P_BITKIT_16x2_EDGE_LR +XCOL<31> A_BLC<63> A_BLC<62> A_BLC_TOP<63> A_BLC_TOP<62> A_BLT<63> A_BLT<62> A_BLT_TOP<63> A_BLT_TOP<62> A_IWL<3967> A_IWL<3966> A_IWL<3965> A_IWL<3964> A_IWL<3963> A_IWL<3962> A_IWL<3961> A_IWL<3960> A_IWL<3959> A_IWL<3958> A_IWL<3957> A_IWL<3956> A_IWL<3955> A_IWL<3954> A_IWL<3953> A_IWL<3952> A_IWL<3951> A_IWL<3950> A_IWL<3949> A_IWL<3948> A_IWL<3947> A_IWL<3946> A_IWL<3945> A_IWL<3944> A_IWL<3943> A_IWL<3942> A_IWL<3941> A_IWL<3940> A_IWL<3939> A_IWL<3938> A_IWL<3937> A_IWL<3936> A_IWL<3935> A_IWL<3934> A_IWL<3933> A_IWL<3932> A_IWL<3931> A_IWL<3930> A_IWL<3929> A_IWL<3928> A_IWL<3927> A_IWL<3926> A_IWL<3925> A_IWL<3924> A_IWL<3923> A_IWL<3922> A_IWL<3921> A_IWL<3920> A_IWL<3919> A_IWL<3918> A_IWL<3917> A_IWL<3916> A_IWL<3915> A_IWL<3914> A_IWL<3913> A_IWL<3912> A_IWL<3911> A_IWL<3910> A_IWL<3909> A_IWL<3908> A_IWL<3907> A_IWL<3906> A_IWL<3905> A_IWL<3904> A_IWL<3903> A_IWL<3902> A_IWL<3901> A_IWL<3900> A_IWL<3899> A_IWL<3898> A_IWL<3897> A_IWL<3896> A_IWL<3895> A_IWL<3894> A_IWL<3893> A_IWL<3892> A_IWL<3891> A_IWL<3890> A_IWL<3889> A_IWL<3888> A_IWL<3887> A_IWL<3886> A_IWL<3885> A_IWL<3884> A_IWL<3883> A_IWL<3882> A_IWL<3881> A_IWL<3880> A_IWL<3879> A_IWL<3878> A_IWL<3877> A_IWL<3876> A_IWL<3875> A_IWL<3874> A_IWL<3873> A_IWL<3872> A_IWL<3871> A_IWL<3870> A_IWL<3869> A_IWL<3868> A_IWL<3867> A_IWL<3866> A_IWL<3865> A_IWL<3864> A_IWL<3863> A_IWL<3862> A_IWL<3861> A_IWL<3860> A_IWL<3859> A_IWL<3858> A_IWL<3857> A_IWL<3856> A_IWL<3855> A_IWL<3854> A_IWL<3853> A_IWL<3852> A_IWL<3851> A_IWL<3850> A_IWL<3849> A_IWL<3848> A_IWL<3847> A_IWL<3846> A_IWL<3845> A_IWL<3844> A_IWL<3843> A_IWL<3842> A_IWL<3841> A_IWL<3840> A_IWL<4095> A_IWL<4094> A_IWL<4093> A_IWL<4092> A_IWL<4091> A_IWL<4090> A_IWL<4089> A_IWL<4088> A_IWL<4087> A_IWL<4086> A_IWL<4085> A_IWL<4084> A_IWL<4083> A_IWL<4082> A_IWL<4081> A_IWL<4080> A_IWL<4079> A_IWL<4078> A_IWL<4077> A_IWL<4076> A_IWL<4075> A_IWL<4074> A_IWL<4073> A_IWL<4072> A_IWL<4071> A_IWL<4070> A_IWL<4069> A_IWL<4068> A_IWL<4067> A_IWL<4066> A_IWL<4065> A_IWL<4064> A_IWL<4063> A_IWL<4062> A_IWL<4061> A_IWL<4060> A_IWL<4059> A_IWL<4058> A_IWL<4057> A_IWL<4056> A_IWL<4055> A_IWL<4054> A_IWL<4053> A_IWL<4052> A_IWL<4051> A_IWL<4050> A_IWL<4049> A_IWL<4048> A_IWL<4047> A_IWL<4046> A_IWL<4045> A_IWL<4044> A_IWL<4043> A_IWL<4042> A_IWL<4041> A_IWL<4040> A_IWL<4039> A_IWL<4038> A_IWL<4037> A_IWL<4036> A_IWL<4035> A_IWL<4034> A_IWL<4033> A_IWL<4032> A_IWL<4031> A_IWL<4030> A_IWL<4029> A_IWL<4028> A_IWL<4027> A_IWL<4026> A_IWL<4025> A_IWL<4024> A_IWL<4023> A_IWL<4022> A_IWL<4021> A_IWL<4020> A_IWL<4019> A_IWL<4018> A_IWL<4017> A_IWL<4016> A_IWL<4015> A_IWL<4014> A_IWL<4013> A_IWL<4012> A_IWL<4011> A_IWL<4010> A_IWL<4009> A_IWL<4008> A_IWL<4007> A_IWL<4006> A_IWL<4005> A_IWL<4004> A_IWL<4003> A_IWL<4002> A_IWL<4001> A_IWL<4000> A_IWL<3999> A_IWL<3998> A_IWL<3997> A_IWL<3996> A_IWL<3995> A_IWL<3994> A_IWL<3993> A_IWL<3992> A_IWL<3991> A_IWL<3990> A_IWL<3989> A_IWL<3988> A_IWL<3987> A_IWL<3986> A_IWL<3985> A_IWL<3984> A_IWL<3983> A_IWL<3982> A_IWL<3981> A_IWL<3980> A_IWL<3979> A_IWL<3978> A_IWL<3977> A_IWL<3976> A_IWL<3975> A_IWL<3974> A_IWL<3973> A_IWL<3972> A_IWL<3971> A_IWL<3970> A_IWL<3969> A_IWL<3968> VDD_CORE VSS / RM_IHPSG13_512x32_c2_1P_COLUMN_pcell_0 +XCOL<30> A_BLC<61> A_BLC<60> A_BLC_TOP<61> A_BLC_TOP<60> A_BLT<61> A_BLT<60> A_BLT_TOP<61> A_BLT_TOP<60> A_IWL<3839> A_IWL<3838> A_IWL<3837> A_IWL<3836> A_IWL<3835> A_IWL<3834> A_IWL<3833> A_IWL<3832> A_IWL<3831> A_IWL<3830> A_IWL<3829> A_IWL<3828> A_IWL<3827> A_IWL<3826> A_IWL<3825> A_IWL<3824> A_IWL<3823> A_IWL<3822> A_IWL<3821> A_IWL<3820> A_IWL<3819> A_IWL<3818> A_IWL<3817> A_IWL<3816> A_IWL<3815> A_IWL<3814> A_IWL<3813> A_IWL<3812> A_IWL<3811> A_IWL<3810> A_IWL<3809> A_IWL<3808> A_IWL<3807> A_IWL<3806> A_IWL<3805> A_IWL<3804> A_IWL<3803> A_IWL<3802> A_IWL<3801> A_IWL<3800> A_IWL<3799> A_IWL<3798> A_IWL<3797> A_IWL<3796> A_IWL<3795> A_IWL<3794> A_IWL<3793> A_IWL<3792> A_IWL<3791> A_IWL<3790> A_IWL<3789> A_IWL<3788> A_IWL<3787> A_IWL<3786> A_IWL<3785> A_IWL<3784> A_IWL<3783> A_IWL<3782> A_IWL<3781> A_IWL<3780> A_IWL<3779> A_IWL<3778> A_IWL<3777> A_IWL<3776> A_IWL<3775> A_IWL<3774> A_IWL<3773> A_IWL<3772> A_IWL<3771> A_IWL<3770> A_IWL<3769> A_IWL<3768> A_IWL<3767> A_IWL<3766> A_IWL<3765> A_IWL<3764> A_IWL<3763> A_IWL<3762> A_IWL<3761> A_IWL<3760> A_IWL<3759> A_IWL<3758> A_IWL<3757> A_IWL<3756> A_IWL<3755> A_IWL<3754> A_IWL<3753> A_IWL<3752> A_IWL<3751> A_IWL<3750> A_IWL<3749> A_IWL<3748> A_IWL<3747> A_IWL<3746> A_IWL<3745> A_IWL<3744> A_IWL<3743> A_IWL<3742> A_IWL<3741> A_IWL<3740> A_IWL<3739> A_IWL<3738> A_IWL<3737> A_IWL<3736> A_IWL<3735> A_IWL<3734> A_IWL<3733> A_IWL<3732> A_IWL<3731> A_IWL<3730> A_IWL<3729> A_IWL<3728> A_IWL<3727> A_IWL<3726> A_IWL<3725> A_IWL<3724> A_IWL<3723> A_IWL<3722> A_IWL<3721> A_IWL<3720> A_IWL<3719> A_IWL<3718> A_IWL<3717> A_IWL<3716> A_IWL<3715> A_IWL<3714> A_IWL<3713> A_IWL<3712> A_IWL<3967> A_IWL<3966> A_IWL<3965> A_IWL<3964> A_IWL<3963> A_IWL<3962> A_IWL<3961> A_IWL<3960> A_IWL<3959> A_IWL<3958> A_IWL<3957> A_IWL<3956> A_IWL<3955> A_IWL<3954> A_IWL<3953> A_IWL<3952> A_IWL<3951> A_IWL<3950> A_IWL<3949> A_IWL<3948> A_IWL<3947> A_IWL<3946> A_IWL<3945> A_IWL<3944> A_IWL<3943> A_IWL<3942> A_IWL<3941> A_IWL<3940> A_IWL<3939> A_IWL<3938> A_IWL<3937> A_IWL<3936> A_IWL<3935> A_IWL<3934> A_IWL<3933> A_IWL<3932> A_IWL<3931> A_IWL<3930> A_IWL<3929> A_IWL<3928> A_IWL<3927> A_IWL<3926> A_IWL<3925> A_IWL<3924> A_IWL<3923> A_IWL<3922> A_IWL<3921> A_IWL<3920> A_IWL<3919> A_IWL<3918> A_IWL<3917> A_IWL<3916> A_IWL<3915> A_IWL<3914> A_IWL<3913> A_IWL<3912> A_IWL<3911> A_IWL<3910> A_IWL<3909> A_IWL<3908> A_IWL<3907> A_IWL<3906> A_IWL<3905> A_IWL<3904> A_IWL<3903> A_IWL<3902> A_IWL<3901> A_IWL<3900> A_IWL<3899> A_IWL<3898> A_IWL<3897> A_IWL<3896> A_IWL<3895> A_IWL<3894> A_IWL<3893> A_IWL<3892> A_IWL<3891> A_IWL<3890> A_IWL<3889> A_IWL<3888> A_IWL<3887> A_IWL<3886> A_IWL<3885> A_IWL<3884> A_IWL<3883> A_IWL<3882> A_IWL<3881> A_IWL<3880> A_IWL<3879> A_IWL<3878> A_IWL<3877> A_IWL<3876> A_IWL<3875> A_IWL<3874> A_IWL<3873> A_IWL<3872> A_IWL<3871> A_IWL<3870> A_IWL<3869> A_IWL<3868> A_IWL<3867> A_IWL<3866> A_IWL<3865> A_IWL<3864> A_IWL<3863> A_IWL<3862> A_IWL<3861> A_IWL<3860> A_IWL<3859> A_IWL<3858> A_IWL<3857> A_IWL<3856> A_IWL<3855> A_IWL<3854> A_IWL<3853> A_IWL<3852> A_IWL<3851> A_IWL<3850> A_IWL<3849> A_IWL<3848> A_IWL<3847> A_IWL<3846> A_IWL<3845> A_IWL<3844> A_IWL<3843> A_IWL<3842> A_IWL<3841> A_IWL<3840> VDD_CORE VSS / RM_IHPSG13_512x32_c2_1P_COLUMN_pcell_0 +XCOL<29> A_BLC<59> A_BLC<58> A_BLC_TOP<59> A_BLC_TOP<58> A_BLT<59> A_BLT<58> A_BLT_TOP<59> A_BLT_TOP<58> A_IWL<3711> A_IWL<3710> A_IWL<3709> A_IWL<3708> A_IWL<3707> A_IWL<3706> A_IWL<3705> A_IWL<3704> A_IWL<3703> A_IWL<3702> A_IWL<3701> A_IWL<3700> A_IWL<3699> A_IWL<3698> A_IWL<3697> A_IWL<3696> A_IWL<3695> A_IWL<3694> A_IWL<3693> A_IWL<3692> A_IWL<3691> A_IWL<3690> A_IWL<3689> A_IWL<3688> A_IWL<3687> A_IWL<3686> A_IWL<3685> A_IWL<3684> A_IWL<3683> A_IWL<3682> A_IWL<3681> A_IWL<3680> A_IWL<3679> A_IWL<3678> A_IWL<3677> A_IWL<3676> A_IWL<3675> A_IWL<3674> A_IWL<3673> A_IWL<3672> A_IWL<3671> A_IWL<3670> A_IWL<3669> A_IWL<3668> A_IWL<3667> A_IWL<3666> A_IWL<3665> A_IWL<3664> A_IWL<3663> A_IWL<3662> A_IWL<3661> A_IWL<3660> A_IWL<3659> A_IWL<3658> A_IWL<3657> A_IWL<3656> A_IWL<3655> A_IWL<3654> A_IWL<3653> A_IWL<3652> A_IWL<3651> A_IWL<3650> A_IWL<3649> A_IWL<3648> A_IWL<3647> A_IWL<3646> A_IWL<3645> A_IWL<3644> A_IWL<3643> A_IWL<3642> A_IWL<3641> A_IWL<3640> A_IWL<3639> A_IWL<3638> A_IWL<3637> A_IWL<3636> A_IWL<3635> A_IWL<3634> A_IWL<3633> A_IWL<3632> A_IWL<3631> A_IWL<3630> A_IWL<3629> A_IWL<3628> A_IWL<3627> A_IWL<3626> A_IWL<3625> A_IWL<3624> A_IWL<3623> A_IWL<3622> A_IWL<3621> A_IWL<3620> A_IWL<3619> A_IWL<3618> A_IWL<3617> A_IWL<3616> A_IWL<3615> A_IWL<3614> A_IWL<3613> A_IWL<3612> A_IWL<3611> A_IWL<3610> A_IWL<3609> A_IWL<3608> A_IWL<3607> A_IWL<3606> A_IWL<3605> A_IWL<3604> A_IWL<3603> A_IWL<3602> A_IWL<3601> A_IWL<3600> A_IWL<3599> A_IWL<3598> A_IWL<3597> A_IWL<3596> A_IWL<3595> A_IWL<3594> A_IWL<3593> A_IWL<3592> A_IWL<3591> A_IWL<3590> A_IWL<3589> A_IWL<3588> A_IWL<3587> A_IWL<3586> A_IWL<3585> A_IWL<3584> A_IWL<3839> A_IWL<3838> A_IWL<3837> A_IWL<3836> A_IWL<3835> A_IWL<3834> A_IWL<3833> A_IWL<3832> A_IWL<3831> A_IWL<3830> A_IWL<3829> A_IWL<3828> A_IWL<3827> A_IWL<3826> A_IWL<3825> A_IWL<3824> A_IWL<3823> A_IWL<3822> A_IWL<3821> A_IWL<3820> A_IWL<3819> A_IWL<3818> A_IWL<3817> A_IWL<3816> A_IWL<3815> A_IWL<3814> A_IWL<3813> A_IWL<3812> A_IWL<3811> A_IWL<3810> A_IWL<3809> A_IWL<3808> A_IWL<3807> A_IWL<3806> A_IWL<3805> A_IWL<3804> A_IWL<3803> A_IWL<3802> A_IWL<3801> A_IWL<3800> A_IWL<3799> A_IWL<3798> A_IWL<3797> A_IWL<3796> A_IWL<3795> A_IWL<3794> A_IWL<3793> A_IWL<3792> A_IWL<3791> A_IWL<3790> A_IWL<3789> A_IWL<3788> A_IWL<3787> A_IWL<3786> A_IWL<3785> A_IWL<3784> A_IWL<3783> A_IWL<3782> A_IWL<3781> A_IWL<3780> A_IWL<3779> A_IWL<3778> A_IWL<3777> A_IWL<3776> A_IWL<3775> A_IWL<3774> A_IWL<3773> A_IWL<3772> A_IWL<3771> A_IWL<3770> A_IWL<3769> A_IWL<3768> A_IWL<3767> A_IWL<3766> A_IWL<3765> A_IWL<3764> A_IWL<3763> A_IWL<3762> A_IWL<3761> A_IWL<3760> A_IWL<3759> A_IWL<3758> A_IWL<3757> A_IWL<3756> A_IWL<3755> A_IWL<3754> A_IWL<3753> A_IWL<3752> A_IWL<3751> A_IWL<3750> A_IWL<3749> A_IWL<3748> A_IWL<3747> A_IWL<3746> A_IWL<3745> A_IWL<3744> A_IWL<3743> A_IWL<3742> A_IWL<3741> A_IWL<3740> A_IWL<3739> A_IWL<3738> A_IWL<3737> A_IWL<3736> A_IWL<3735> A_IWL<3734> A_IWL<3733> A_IWL<3732> A_IWL<3731> A_IWL<3730> A_IWL<3729> A_IWL<3728> A_IWL<3727> A_IWL<3726> A_IWL<3725> A_IWL<3724> A_IWL<3723> A_IWL<3722> A_IWL<3721> A_IWL<3720> A_IWL<3719> A_IWL<3718> A_IWL<3717> A_IWL<3716> A_IWL<3715> A_IWL<3714> A_IWL<3713> A_IWL<3712> VDD_CORE VSS / RM_IHPSG13_512x32_c2_1P_COLUMN_pcell_0 +XCOL<28> A_BLC<57> A_BLC<56> A_BLC_TOP<57> A_BLC_TOP<56> A_BLT<57> A_BLT<56> A_BLT_TOP<57> A_BLT_TOP<56> A_IWL<3583> A_IWL<3582> A_IWL<3581> A_IWL<3580> A_IWL<3579> A_IWL<3578> A_IWL<3577> A_IWL<3576> A_IWL<3575> A_IWL<3574> A_IWL<3573> A_IWL<3572> A_IWL<3571> A_IWL<3570> A_IWL<3569> A_IWL<3568> A_IWL<3567> A_IWL<3566> A_IWL<3565> A_IWL<3564> A_IWL<3563> A_IWL<3562> A_IWL<3561> A_IWL<3560> A_IWL<3559> A_IWL<3558> A_IWL<3557> A_IWL<3556> A_IWL<3555> A_IWL<3554> A_IWL<3553> A_IWL<3552> A_IWL<3551> A_IWL<3550> A_IWL<3549> A_IWL<3548> A_IWL<3547> A_IWL<3546> A_IWL<3545> A_IWL<3544> A_IWL<3543> A_IWL<3542> A_IWL<3541> A_IWL<3540> A_IWL<3539> A_IWL<3538> A_IWL<3537> A_IWL<3536> A_IWL<3535> A_IWL<3534> A_IWL<3533> A_IWL<3532> A_IWL<3531> A_IWL<3530> A_IWL<3529> A_IWL<3528> A_IWL<3527> A_IWL<3526> A_IWL<3525> A_IWL<3524> A_IWL<3523> A_IWL<3522> A_IWL<3521> A_IWL<3520> A_IWL<3519> A_IWL<3518> A_IWL<3517> A_IWL<3516> A_IWL<3515> A_IWL<3514> A_IWL<3513> A_IWL<3512> A_IWL<3511> A_IWL<3510> A_IWL<3509> A_IWL<3508> A_IWL<3507> A_IWL<3506> A_IWL<3505> A_IWL<3504> A_IWL<3503> A_IWL<3502> A_IWL<3501> A_IWL<3500> A_IWL<3499> A_IWL<3498> A_IWL<3497> A_IWL<3496> A_IWL<3495> A_IWL<3494> A_IWL<3493> A_IWL<3492> A_IWL<3491> A_IWL<3490> A_IWL<3489> A_IWL<3488> A_IWL<3487> A_IWL<3486> A_IWL<3485> A_IWL<3484> A_IWL<3483> A_IWL<3482> A_IWL<3481> A_IWL<3480> A_IWL<3479> A_IWL<3478> A_IWL<3477> A_IWL<3476> A_IWL<3475> A_IWL<3474> A_IWL<3473> A_IWL<3472> A_IWL<3471> A_IWL<3470> A_IWL<3469> A_IWL<3468> A_IWL<3467> A_IWL<3466> A_IWL<3465> A_IWL<3464> A_IWL<3463> A_IWL<3462> A_IWL<3461> A_IWL<3460> A_IWL<3459> A_IWL<3458> A_IWL<3457> A_IWL<3456> A_IWL<3711> A_IWL<3710> A_IWL<3709> A_IWL<3708> A_IWL<3707> A_IWL<3706> A_IWL<3705> A_IWL<3704> A_IWL<3703> A_IWL<3702> A_IWL<3701> A_IWL<3700> A_IWL<3699> A_IWL<3698> A_IWL<3697> A_IWL<3696> A_IWL<3695> A_IWL<3694> A_IWL<3693> A_IWL<3692> A_IWL<3691> A_IWL<3690> A_IWL<3689> A_IWL<3688> A_IWL<3687> A_IWL<3686> A_IWL<3685> A_IWL<3684> A_IWL<3683> A_IWL<3682> A_IWL<3681> A_IWL<3680> A_IWL<3679> A_IWL<3678> A_IWL<3677> A_IWL<3676> A_IWL<3675> A_IWL<3674> A_IWL<3673> A_IWL<3672> A_IWL<3671> A_IWL<3670> A_IWL<3669> A_IWL<3668> A_IWL<3667> A_IWL<3666> A_IWL<3665> A_IWL<3664> A_IWL<3663> A_IWL<3662> A_IWL<3661> A_IWL<3660> A_IWL<3659> A_IWL<3658> A_IWL<3657> A_IWL<3656> A_IWL<3655> A_IWL<3654> A_IWL<3653> A_IWL<3652> A_IWL<3651> A_IWL<3650> A_IWL<3649> A_IWL<3648> A_IWL<3647> A_IWL<3646> A_IWL<3645> A_IWL<3644> A_IWL<3643> A_IWL<3642> A_IWL<3641> A_IWL<3640> A_IWL<3639> A_IWL<3638> A_IWL<3637> A_IWL<3636> A_IWL<3635> A_IWL<3634> A_IWL<3633> A_IWL<3632> A_IWL<3631> A_IWL<3630> A_IWL<3629> A_IWL<3628> A_IWL<3627> A_IWL<3626> A_IWL<3625> A_IWL<3624> A_IWL<3623> A_IWL<3622> A_IWL<3621> A_IWL<3620> A_IWL<3619> A_IWL<3618> A_IWL<3617> A_IWL<3616> A_IWL<3615> A_IWL<3614> A_IWL<3613> A_IWL<3612> A_IWL<3611> A_IWL<3610> A_IWL<3609> A_IWL<3608> A_IWL<3607> A_IWL<3606> A_IWL<3605> A_IWL<3604> A_IWL<3603> A_IWL<3602> A_IWL<3601> A_IWL<3600> A_IWL<3599> A_IWL<3598> A_IWL<3597> A_IWL<3596> A_IWL<3595> A_IWL<3594> A_IWL<3593> A_IWL<3592> A_IWL<3591> A_IWL<3590> A_IWL<3589> A_IWL<3588> A_IWL<3587> A_IWL<3586> A_IWL<3585> A_IWL<3584> VDD_CORE VSS / RM_IHPSG13_512x32_c2_1P_COLUMN_pcell_0 +XCOL<27> A_BLC<55> A_BLC<54> A_BLC_TOP<55> A_BLC_TOP<54> A_BLT<55> A_BLT<54> A_BLT_TOP<55> A_BLT_TOP<54> A_IWL<3455> A_IWL<3454> A_IWL<3453> A_IWL<3452> A_IWL<3451> A_IWL<3450> A_IWL<3449> A_IWL<3448> A_IWL<3447> A_IWL<3446> A_IWL<3445> A_IWL<3444> A_IWL<3443> A_IWL<3442> A_IWL<3441> A_IWL<3440> A_IWL<3439> A_IWL<3438> A_IWL<3437> A_IWL<3436> A_IWL<3435> A_IWL<3434> A_IWL<3433> A_IWL<3432> A_IWL<3431> A_IWL<3430> A_IWL<3429> A_IWL<3428> A_IWL<3427> A_IWL<3426> A_IWL<3425> A_IWL<3424> A_IWL<3423> A_IWL<3422> A_IWL<3421> A_IWL<3420> A_IWL<3419> A_IWL<3418> A_IWL<3417> A_IWL<3416> A_IWL<3415> A_IWL<3414> A_IWL<3413> A_IWL<3412> A_IWL<3411> A_IWL<3410> A_IWL<3409> A_IWL<3408> A_IWL<3407> A_IWL<3406> A_IWL<3405> A_IWL<3404> A_IWL<3403> A_IWL<3402> A_IWL<3401> A_IWL<3400> A_IWL<3399> A_IWL<3398> A_IWL<3397> A_IWL<3396> A_IWL<3395> A_IWL<3394> A_IWL<3393> A_IWL<3392> A_IWL<3391> A_IWL<3390> A_IWL<3389> A_IWL<3388> A_IWL<3387> A_IWL<3386> A_IWL<3385> A_IWL<3384> A_IWL<3383> A_IWL<3382> A_IWL<3381> A_IWL<3380> A_IWL<3379> A_IWL<3378> A_IWL<3377> A_IWL<3376> A_IWL<3375> A_IWL<3374> A_IWL<3373> A_IWL<3372> A_IWL<3371> A_IWL<3370> A_IWL<3369> A_IWL<3368> A_IWL<3367> A_IWL<3366> A_IWL<3365> A_IWL<3364> A_IWL<3363> A_IWL<3362> A_IWL<3361> A_IWL<3360> A_IWL<3359> A_IWL<3358> A_IWL<3357> A_IWL<3356> A_IWL<3355> A_IWL<3354> A_IWL<3353> A_IWL<3352> A_IWL<3351> A_IWL<3350> A_IWL<3349> A_IWL<3348> A_IWL<3347> A_IWL<3346> A_IWL<3345> A_IWL<3344> A_IWL<3343> A_IWL<3342> A_IWL<3341> A_IWL<3340> A_IWL<3339> A_IWL<3338> A_IWL<3337> A_IWL<3336> A_IWL<3335> A_IWL<3334> A_IWL<3333> A_IWL<3332> A_IWL<3331> A_IWL<3330> A_IWL<3329> A_IWL<3328> A_IWL<3583> A_IWL<3582> A_IWL<3581> A_IWL<3580> A_IWL<3579> A_IWL<3578> A_IWL<3577> A_IWL<3576> A_IWL<3575> A_IWL<3574> A_IWL<3573> A_IWL<3572> A_IWL<3571> A_IWL<3570> A_IWL<3569> A_IWL<3568> A_IWL<3567> A_IWL<3566> A_IWL<3565> A_IWL<3564> A_IWL<3563> A_IWL<3562> A_IWL<3561> A_IWL<3560> A_IWL<3559> A_IWL<3558> A_IWL<3557> A_IWL<3556> A_IWL<3555> A_IWL<3554> A_IWL<3553> A_IWL<3552> A_IWL<3551> A_IWL<3550> A_IWL<3549> A_IWL<3548> A_IWL<3547> A_IWL<3546> A_IWL<3545> A_IWL<3544> A_IWL<3543> A_IWL<3542> A_IWL<3541> A_IWL<3540> A_IWL<3539> A_IWL<3538> A_IWL<3537> A_IWL<3536> A_IWL<3535> A_IWL<3534> A_IWL<3533> A_IWL<3532> A_IWL<3531> A_IWL<3530> A_IWL<3529> A_IWL<3528> A_IWL<3527> A_IWL<3526> A_IWL<3525> A_IWL<3524> A_IWL<3523> A_IWL<3522> A_IWL<3521> A_IWL<3520> A_IWL<3519> A_IWL<3518> A_IWL<3517> A_IWL<3516> A_IWL<3515> A_IWL<3514> A_IWL<3513> A_IWL<3512> A_IWL<3511> A_IWL<3510> A_IWL<3509> A_IWL<3508> A_IWL<3507> A_IWL<3506> A_IWL<3505> A_IWL<3504> A_IWL<3503> A_IWL<3502> A_IWL<3501> A_IWL<3500> A_IWL<3499> A_IWL<3498> A_IWL<3497> A_IWL<3496> A_IWL<3495> A_IWL<3494> A_IWL<3493> A_IWL<3492> A_IWL<3491> A_IWL<3490> A_IWL<3489> A_IWL<3488> A_IWL<3487> A_IWL<3486> A_IWL<3485> A_IWL<3484> A_IWL<3483> A_IWL<3482> A_IWL<3481> A_IWL<3480> A_IWL<3479> A_IWL<3478> A_IWL<3477> A_IWL<3476> A_IWL<3475> A_IWL<3474> A_IWL<3473> A_IWL<3472> A_IWL<3471> A_IWL<3470> A_IWL<3469> A_IWL<3468> A_IWL<3467> A_IWL<3466> A_IWL<3465> A_IWL<3464> A_IWL<3463> A_IWL<3462> A_IWL<3461> A_IWL<3460> A_IWL<3459> A_IWL<3458> A_IWL<3457> A_IWL<3456> VDD_CORE VSS / RM_IHPSG13_512x32_c2_1P_COLUMN_pcell_0 +XCOL<26> A_BLC<53> A_BLC<52> A_BLC_TOP<53> A_BLC_TOP<52> A_BLT<53> A_BLT<52> A_BLT_TOP<53> A_BLT_TOP<52> A_IWL<3327> A_IWL<3326> A_IWL<3325> A_IWL<3324> A_IWL<3323> A_IWL<3322> A_IWL<3321> A_IWL<3320> A_IWL<3319> A_IWL<3318> A_IWL<3317> A_IWL<3316> A_IWL<3315> A_IWL<3314> A_IWL<3313> A_IWL<3312> A_IWL<3311> A_IWL<3310> A_IWL<3309> A_IWL<3308> A_IWL<3307> A_IWL<3306> A_IWL<3305> A_IWL<3304> A_IWL<3303> A_IWL<3302> A_IWL<3301> A_IWL<3300> A_IWL<3299> A_IWL<3298> A_IWL<3297> A_IWL<3296> A_IWL<3295> A_IWL<3294> A_IWL<3293> A_IWL<3292> A_IWL<3291> A_IWL<3290> A_IWL<3289> A_IWL<3288> A_IWL<3287> A_IWL<3286> A_IWL<3285> A_IWL<3284> A_IWL<3283> A_IWL<3282> A_IWL<3281> A_IWL<3280> A_IWL<3279> A_IWL<3278> A_IWL<3277> A_IWL<3276> A_IWL<3275> A_IWL<3274> A_IWL<3273> A_IWL<3272> A_IWL<3271> A_IWL<3270> A_IWL<3269> A_IWL<3268> A_IWL<3267> A_IWL<3266> A_IWL<3265> A_IWL<3264> A_IWL<3263> A_IWL<3262> A_IWL<3261> A_IWL<3260> A_IWL<3259> A_IWL<3258> A_IWL<3257> A_IWL<3256> A_IWL<3255> A_IWL<3254> A_IWL<3253> A_IWL<3252> A_IWL<3251> A_IWL<3250> A_IWL<3249> A_IWL<3248> A_IWL<3247> A_IWL<3246> A_IWL<3245> A_IWL<3244> A_IWL<3243> A_IWL<3242> A_IWL<3241> A_IWL<3240> A_IWL<3239> A_IWL<3238> A_IWL<3237> A_IWL<3236> A_IWL<3235> A_IWL<3234> A_IWL<3233> A_IWL<3232> A_IWL<3231> A_IWL<3230> A_IWL<3229> A_IWL<3228> A_IWL<3227> A_IWL<3226> A_IWL<3225> A_IWL<3224> A_IWL<3223> A_IWL<3222> A_IWL<3221> A_IWL<3220> A_IWL<3219> A_IWL<3218> A_IWL<3217> A_IWL<3216> A_IWL<3215> A_IWL<3214> A_IWL<3213> A_IWL<3212> A_IWL<3211> A_IWL<3210> A_IWL<3209> A_IWL<3208> A_IWL<3207> A_IWL<3206> A_IWL<3205> A_IWL<3204> A_IWL<3203> A_IWL<3202> A_IWL<3201> A_IWL<3200> A_IWL<3455> A_IWL<3454> A_IWL<3453> A_IWL<3452> A_IWL<3451> A_IWL<3450> A_IWL<3449> A_IWL<3448> A_IWL<3447> A_IWL<3446> A_IWL<3445> A_IWL<3444> A_IWL<3443> A_IWL<3442> A_IWL<3441> A_IWL<3440> A_IWL<3439> A_IWL<3438> A_IWL<3437> A_IWL<3436> A_IWL<3435> A_IWL<3434> A_IWL<3433> A_IWL<3432> A_IWL<3431> A_IWL<3430> A_IWL<3429> A_IWL<3428> A_IWL<3427> A_IWL<3426> A_IWL<3425> A_IWL<3424> A_IWL<3423> A_IWL<3422> A_IWL<3421> A_IWL<3420> A_IWL<3419> A_IWL<3418> A_IWL<3417> A_IWL<3416> A_IWL<3415> A_IWL<3414> A_IWL<3413> A_IWL<3412> A_IWL<3411> A_IWL<3410> A_IWL<3409> A_IWL<3408> A_IWL<3407> A_IWL<3406> A_IWL<3405> A_IWL<3404> A_IWL<3403> A_IWL<3402> A_IWL<3401> A_IWL<3400> A_IWL<3399> A_IWL<3398> A_IWL<3397> A_IWL<3396> A_IWL<3395> A_IWL<3394> A_IWL<3393> A_IWL<3392> A_IWL<3391> A_IWL<3390> A_IWL<3389> A_IWL<3388> A_IWL<3387> A_IWL<3386> A_IWL<3385> A_IWL<3384> A_IWL<3383> A_IWL<3382> A_IWL<3381> A_IWL<3380> A_IWL<3379> A_IWL<3378> A_IWL<3377> A_IWL<3376> A_IWL<3375> A_IWL<3374> A_IWL<3373> A_IWL<3372> A_IWL<3371> A_IWL<3370> A_IWL<3369> A_IWL<3368> A_IWL<3367> A_IWL<3366> A_IWL<3365> A_IWL<3364> A_IWL<3363> A_IWL<3362> A_IWL<3361> A_IWL<3360> A_IWL<3359> A_IWL<3358> A_IWL<3357> A_IWL<3356> A_IWL<3355> A_IWL<3354> A_IWL<3353> A_IWL<3352> A_IWL<3351> A_IWL<3350> A_IWL<3349> A_IWL<3348> A_IWL<3347> A_IWL<3346> A_IWL<3345> A_IWL<3344> A_IWL<3343> A_IWL<3342> A_IWL<3341> A_IWL<3340> A_IWL<3339> A_IWL<3338> A_IWL<3337> A_IWL<3336> A_IWL<3335> A_IWL<3334> A_IWL<3333> A_IWL<3332> A_IWL<3331> A_IWL<3330> A_IWL<3329> A_IWL<3328> VDD_CORE VSS / RM_IHPSG13_512x32_c2_1P_COLUMN_pcell_0 +XCOL<25> A_BLC<51> A_BLC<50> A_BLC_TOP<51> A_BLC_TOP<50> A_BLT<51> A_BLT<50> A_BLT_TOP<51> A_BLT_TOP<50> A_IWL<3199> A_IWL<3198> A_IWL<3197> A_IWL<3196> A_IWL<3195> A_IWL<3194> A_IWL<3193> A_IWL<3192> A_IWL<3191> A_IWL<3190> A_IWL<3189> A_IWL<3188> A_IWL<3187> A_IWL<3186> A_IWL<3185> A_IWL<3184> A_IWL<3183> A_IWL<3182> A_IWL<3181> A_IWL<3180> A_IWL<3179> A_IWL<3178> A_IWL<3177> A_IWL<3176> A_IWL<3175> A_IWL<3174> A_IWL<3173> A_IWL<3172> A_IWL<3171> A_IWL<3170> A_IWL<3169> A_IWL<3168> A_IWL<3167> A_IWL<3166> A_IWL<3165> A_IWL<3164> A_IWL<3163> A_IWL<3162> A_IWL<3161> A_IWL<3160> A_IWL<3159> A_IWL<3158> A_IWL<3157> A_IWL<3156> A_IWL<3155> A_IWL<3154> A_IWL<3153> A_IWL<3152> A_IWL<3151> A_IWL<3150> A_IWL<3149> A_IWL<3148> A_IWL<3147> A_IWL<3146> A_IWL<3145> A_IWL<3144> A_IWL<3143> A_IWL<3142> A_IWL<3141> A_IWL<3140> A_IWL<3139> A_IWL<3138> A_IWL<3137> A_IWL<3136> A_IWL<3135> A_IWL<3134> A_IWL<3133> A_IWL<3132> A_IWL<3131> A_IWL<3130> A_IWL<3129> A_IWL<3128> A_IWL<3127> A_IWL<3126> A_IWL<3125> A_IWL<3124> A_IWL<3123> A_IWL<3122> A_IWL<3121> A_IWL<3120> A_IWL<3119> A_IWL<3118> A_IWL<3117> A_IWL<3116> A_IWL<3115> A_IWL<3114> A_IWL<3113> A_IWL<3112> A_IWL<3111> A_IWL<3110> A_IWL<3109> A_IWL<3108> A_IWL<3107> A_IWL<3106> A_IWL<3105> A_IWL<3104> A_IWL<3103> A_IWL<3102> A_IWL<3101> A_IWL<3100> A_IWL<3099> A_IWL<3098> A_IWL<3097> A_IWL<3096> A_IWL<3095> A_IWL<3094> A_IWL<3093> A_IWL<3092> A_IWL<3091> A_IWL<3090> A_IWL<3089> A_IWL<3088> A_IWL<3087> A_IWL<3086> A_IWL<3085> A_IWL<3084> A_IWL<3083> A_IWL<3082> A_IWL<3081> A_IWL<3080> A_IWL<3079> A_IWL<3078> A_IWL<3077> A_IWL<3076> A_IWL<3075> A_IWL<3074> A_IWL<3073> A_IWL<3072> A_IWL<3327> A_IWL<3326> A_IWL<3325> A_IWL<3324> A_IWL<3323> A_IWL<3322> A_IWL<3321> A_IWL<3320> A_IWL<3319> A_IWL<3318> A_IWL<3317> A_IWL<3316> A_IWL<3315> A_IWL<3314> A_IWL<3313> A_IWL<3312> A_IWL<3311> A_IWL<3310> A_IWL<3309> A_IWL<3308> A_IWL<3307> A_IWL<3306> A_IWL<3305> A_IWL<3304> A_IWL<3303> A_IWL<3302> A_IWL<3301> A_IWL<3300> A_IWL<3299> A_IWL<3298> A_IWL<3297> A_IWL<3296> A_IWL<3295> A_IWL<3294> A_IWL<3293> A_IWL<3292> A_IWL<3291> A_IWL<3290> A_IWL<3289> A_IWL<3288> A_IWL<3287> A_IWL<3286> A_IWL<3285> A_IWL<3284> A_IWL<3283> A_IWL<3282> A_IWL<3281> A_IWL<3280> A_IWL<3279> A_IWL<3278> A_IWL<3277> A_IWL<3276> A_IWL<3275> A_IWL<3274> A_IWL<3273> A_IWL<3272> A_IWL<3271> A_IWL<3270> A_IWL<3269> A_IWL<3268> A_IWL<3267> A_IWL<3266> A_IWL<3265> A_IWL<3264> A_IWL<3263> A_IWL<3262> A_IWL<3261> A_IWL<3260> A_IWL<3259> A_IWL<3258> A_IWL<3257> A_IWL<3256> A_IWL<3255> A_IWL<3254> A_IWL<3253> A_IWL<3252> A_IWL<3251> A_IWL<3250> A_IWL<3249> A_IWL<3248> A_IWL<3247> A_IWL<3246> A_IWL<3245> A_IWL<3244> A_IWL<3243> A_IWL<3242> A_IWL<3241> A_IWL<3240> A_IWL<3239> A_IWL<3238> A_IWL<3237> A_IWL<3236> A_IWL<3235> A_IWL<3234> A_IWL<3233> A_IWL<3232> A_IWL<3231> A_IWL<3230> A_IWL<3229> A_IWL<3228> A_IWL<3227> A_IWL<3226> A_IWL<3225> A_IWL<3224> A_IWL<3223> A_IWL<3222> A_IWL<3221> A_IWL<3220> A_IWL<3219> A_IWL<3218> A_IWL<3217> A_IWL<3216> A_IWL<3215> A_IWL<3214> A_IWL<3213> A_IWL<3212> A_IWL<3211> A_IWL<3210> A_IWL<3209> A_IWL<3208> A_IWL<3207> A_IWL<3206> A_IWL<3205> A_IWL<3204> A_IWL<3203> A_IWL<3202> A_IWL<3201> A_IWL<3200> VDD_CORE VSS / RM_IHPSG13_512x32_c2_1P_COLUMN_pcell_0 +XCOL<24> A_BLC<49> A_BLC<48> A_BLC_TOP<49> A_BLC_TOP<48> A_BLT<49> A_BLT<48> A_BLT_TOP<49> A_BLT_TOP<48> A_IWL<3071> A_IWL<3070> A_IWL<3069> A_IWL<3068> A_IWL<3067> A_IWL<3066> A_IWL<3065> A_IWL<3064> A_IWL<3063> A_IWL<3062> A_IWL<3061> A_IWL<3060> A_IWL<3059> A_IWL<3058> A_IWL<3057> A_IWL<3056> A_IWL<3055> A_IWL<3054> A_IWL<3053> A_IWL<3052> A_IWL<3051> A_IWL<3050> A_IWL<3049> A_IWL<3048> A_IWL<3047> A_IWL<3046> A_IWL<3045> A_IWL<3044> A_IWL<3043> A_IWL<3042> A_IWL<3041> A_IWL<3040> A_IWL<3039> A_IWL<3038> A_IWL<3037> A_IWL<3036> A_IWL<3035> A_IWL<3034> A_IWL<3033> A_IWL<3032> A_IWL<3031> A_IWL<3030> A_IWL<3029> A_IWL<3028> A_IWL<3027> A_IWL<3026> A_IWL<3025> A_IWL<3024> A_IWL<3023> A_IWL<3022> A_IWL<3021> A_IWL<3020> A_IWL<3019> A_IWL<3018> A_IWL<3017> A_IWL<3016> A_IWL<3015> A_IWL<3014> A_IWL<3013> A_IWL<3012> A_IWL<3011> A_IWL<3010> A_IWL<3009> A_IWL<3008> A_IWL<3007> A_IWL<3006> A_IWL<3005> A_IWL<3004> A_IWL<3003> A_IWL<3002> A_IWL<3001> A_IWL<3000> A_IWL<2999> A_IWL<2998> A_IWL<2997> A_IWL<2996> A_IWL<2995> A_IWL<2994> A_IWL<2993> A_IWL<2992> A_IWL<2991> A_IWL<2990> A_IWL<2989> A_IWL<2988> A_IWL<2987> A_IWL<2986> A_IWL<2985> A_IWL<2984> A_IWL<2983> A_IWL<2982> A_IWL<2981> A_IWL<2980> A_IWL<2979> A_IWL<2978> A_IWL<2977> A_IWL<2976> A_IWL<2975> A_IWL<2974> A_IWL<2973> A_IWL<2972> A_IWL<2971> A_IWL<2970> A_IWL<2969> A_IWL<2968> A_IWL<2967> A_IWL<2966> A_IWL<2965> A_IWL<2964> A_IWL<2963> A_IWL<2962> A_IWL<2961> A_IWL<2960> A_IWL<2959> A_IWL<2958> A_IWL<2957> A_IWL<2956> A_IWL<2955> A_IWL<2954> A_IWL<2953> A_IWL<2952> A_IWL<2951> A_IWL<2950> A_IWL<2949> A_IWL<2948> A_IWL<2947> A_IWL<2946> A_IWL<2945> A_IWL<2944> A_IWL<3199> A_IWL<3198> A_IWL<3197> A_IWL<3196> A_IWL<3195> A_IWL<3194> A_IWL<3193> A_IWL<3192> A_IWL<3191> A_IWL<3190> A_IWL<3189> A_IWL<3188> A_IWL<3187> A_IWL<3186> A_IWL<3185> A_IWL<3184> A_IWL<3183> A_IWL<3182> A_IWL<3181> A_IWL<3180> A_IWL<3179> A_IWL<3178> A_IWL<3177> A_IWL<3176> A_IWL<3175> A_IWL<3174> A_IWL<3173> A_IWL<3172> A_IWL<3171> A_IWL<3170> A_IWL<3169> A_IWL<3168> A_IWL<3167> A_IWL<3166> A_IWL<3165> A_IWL<3164> A_IWL<3163> A_IWL<3162> A_IWL<3161> A_IWL<3160> A_IWL<3159> A_IWL<3158> A_IWL<3157> A_IWL<3156> A_IWL<3155> A_IWL<3154> A_IWL<3153> A_IWL<3152> A_IWL<3151> A_IWL<3150> A_IWL<3149> A_IWL<3148> A_IWL<3147> A_IWL<3146> A_IWL<3145> A_IWL<3144> A_IWL<3143> A_IWL<3142> A_IWL<3141> A_IWL<3140> A_IWL<3139> A_IWL<3138> A_IWL<3137> A_IWL<3136> A_IWL<3135> A_IWL<3134> A_IWL<3133> A_IWL<3132> A_IWL<3131> A_IWL<3130> A_IWL<3129> A_IWL<3128> A_IWL<3127> A_IWL<3126> A_IWL<3125> A_IWL<3124> A_IWL<3123> A_IWL<3122> A_IWL<3121> A_IWL<3120> A_IWL<3119> A_IWL<3118> A_IWL<3117> A_IWL<3116> A_IWL<3115> A_IWL<3114> A_IWL<3113> A_IWL<3112> A_IWL<3111> A_IWL<3110> A_IWL<3109> A_IWL<3108> A_IWL<3107> A_IWL<3106> A_IWL<3105> A_IWL<3104> A_IWL<3103> A_IWL<3102> A_IWL<3101> A_IWL<3100> A_IWL<3099> A_IWL<3098> A_IWL<3097> A_IWL<3096> A_IWL<3095> A_IWL<3094> A_IWL<3093> A_IWL<3092> A_IWL<3091> A_IWL<3090> A_IWL<3089> A_IWL<3088> A_IWL<3087> A_IWL<3086> A_IWL<3085> A_IWL<3084> A_IWL<3083> A_IWL<3082> A_IWL<3081> A_IWL<3080> A_IWL<3079> A_IWL<3078> A_IWL<3077> A_IWL<3076> A_IWL<3075> A_IWL<3074> A_IWL<3073> A_IWL<3072> VDD_CORE VSS / RM_IHPSG13_512x32_c2_1P_COLUMN_pcell_0 +XCOL<23> A_BLC<47> A_BLC<46> A_BLC_TOP<47> A_BLC_TOP<46> A_BLT<47> A_BLT<46> A_BLT_TOP<47> A_BLT_TOP<46> A_IWL<2943> A_IWL<2942> A_IWL<2941> A_IWL<2940> A_IWL<2939> A_IWL<2938> A_IWL<2937> A_IWL<2936> A_IWL<2935> A_IWL<2934> A_IWL<2933> A_IWL<2932> A_IWL<2931> A_IWL<2930> A_IWL<2929> A_IWL<2928> A_IWL<2927> A_IWL<2926> A_IWL<2925> A_IWL<2924> A_IWL<2923> A_IWL<2922> A_IWL<2921> A_IWL<2920> A_IWL<2919> A_IWL<2918> A_IWL<2917> A_IWL<2916> A_IWL<2915> A_IWL<2914> A_IWL<2913> A_IWL<2912> A_IWL<2911> A_IWL<2910> A_IWL<2909> A_IWL<2908> A_IWL<2907> A_IWL<2906> A_IWL<2905> A_IWL<2904> A_IWL<2903> A_IWL<2902> A_IWL<2901> A_IWL<2900> A_IWL<2899> A_IWL<2898> A_IWL<2897> A_IWL<2896> A_IWL<2895> A_IWL<2894> A_IWL<2893> A_IWL<2892> A_IWL<2891> A_IWL<2890> A_IWL<2889> A_IWL<2888> A_IWL<2887> A_IWL<2886> A_IWL<2885> A_IWL<2884> A_IWL<2883> A_IWL<2882> A_IWL<2881> A_IWL<2880> A_IWL<2879> A_IWL<2878> A_IWL<2877> A_IWL<2876> A_IWL<2875> A_IWL<2874> A_IWL<2873> A_IWL<2872> A_IWL<2871> A_IWL<2870> A_IWL<2869> A_IWL<2868> A_IWL<2867> A_IWL<2866> A_IWL<2865> A_IWL<2864> A_IWL<2863> A_IWL<2862> A_IWL<2861> A_IWL<2860> A_IWL<2859> A_IWL<2858> A_IWL<2857> A_IWL<2856> A_IWL<2855> A_IWL<2854> A_IWL<2853> A_IWL<2852> A_IWL<2851> A_IWL<2850> A_IWL<2849> A_IWL<2848> A_IWL<2847> A_IWL<2846> A_IWL<2845> A_IWL<2844> A_IWL<2843> A_IWL<2842> A_IWL<2841> A_IWL<2840> A_IWL<2839> A_IWL<2838> A_IWL<2837> A_IWL<2836> A_IWL<2835> A_IWL<2834> A_IWL<2833> A_IWL<2832> A_IWL<2831> A_IWL<2830> A_IWL<2829> A_IWL<2828> A_IWL<2827> A_IWL<2826> A_IWL<2825> A_IWL<2824> A_IWL<2823> A_IWL<2822> A_IWL<2821> A_IWL<2820> A_IWL<2819> A_IWL<2818> A_IWL<2817> A_IWL<2816> A_IWL<3071> A_IWL<3070> A_IWL<3069> A_IWL<3068> A_IWL<3067> A_IWL<3066> A_IWL<3065> A_IWL<3064> A_IWL<3063> A_IWL<3062> A_IWL<3061> A_IWL<3060> A_IWL<3059> A_IWL<3058> A_IWL<3057> A_IWL<3056> A_IWL<3055> A_IWL<3054> A_IWL<3053> A_IWL<3052> A_IWL<3051> A_IWL<3050> A_IWL<3049> A_IWL<3048> A_IWL<3047> A_IWL<3046> A_IWL<3045> A_IWL<3044> A_IWL<3043> A_IWL<3042> A_IWL<3041> A_IWL<3040> A_IWL<3039> A_IWL<3038> A_IWL<3037> A_IWL<3036> A_IWL<3035> A_IWL<3034> A_IWL<3033> A_IWL<3032> A_IWL<3031> A_IWL<3030> A_IWL<3029> A_IWL<3028> A_IWL<3027> A_IWL<3026> A_IWL<3025> A_IWL<3024> A_IWL<3023> A_IWL<3022> A_IWL<3021> A_IWL<3020> A_IWL<3019> A_IWL<3018> A_IWL<3017> A_IWL<3016> A_IWL<3015> A_IWL<3014> A_IWL<3013> A_IWL<3012> A_IWL<3011> A_IWL<3010> A_IWL<3009> A_IWL<3008> A_IWL<3007> A_IWL<3006> A_IWL<3005> A_IWL<3004> A_IWL<3003> A_IWL<3002> A_IWL<3001> A_IWL<3000> A_IWL<2999> A_IWL<2998> A_IWL<2997> A_IWL<2996> A_IWL<2995> A_IWL<2994> A_IWL<2993> A_IWL<2992> A_IWL<2991> A_IWL<2990> A_IWL<2989> A_IWL<2988> A_IWL<2987> A_IWL<2986> A_IWL<2985> A_IWL<2984> A_IWL<2983> A_IWL<2982> A_IWL<2981> A_IWL<2980> A_IWL<2979> A_IWL<2978> A_IWL<2977> A_IWL<2976> A_IWL<2975> A_IWL<2974> A_IWL<2973> A_IWL<2972> A_IWL<2971> A_IWL<2970> A_IWL<2969> A_IWL<2968> A_IWL<2967> A_IWL<2966> A_IWL<2965> A_IWL<2964> A_IWL<2963> A_IWL<2962> A_IWL<2961> A_IWL<2960> A_IWL<2959> A_IWL<2958> A_IWL<2957> A_IWL<2956> A_IWL<2955> A_IWL<2954> A_IWL<2953> A_IWL<2952> A_IWL<2951> A_IWL<2950> A_IWL<2949> A_IWL<2948> A_IWL<2947> A_IWL<2946> A_IWL<2945> A_IWL<2944> VDD_CORE VSS / RM_IHPSG13_512x32_c2_1P_COLUMN_pcell_0 +XCOL<22> A_BLC<45> A_BLC<44> A_BLC_TOP<45> A_BLC_TOP<44> A_BLT<45> A_BLT<44> A_BLT_TOP<45> A_BLT_TOP<44> A_IWL<2815> A_IWL<2814> A_IWL<2813> A_IWL<2812> A_IWL<2811> A_IWL<2810> A_IWL<2809> A_IWL<2808> A_IWL<2807> A_IWL<2806> A_IWL<2805> A_IWL<2804> A_IWL<2803> A_IWL<2802> A_IWL<2801> A_IWL<2800> A_IWL<2799> A_IWL<2798> A_IWL<2797> A_IWL<2796> A_IWL<2795> A_IWL<2794> A_IWL<2793> A_IWL<2792> A_IWL<2791> A_IWL<2790> A_IWL<2789> A_IWL<2788> A_IWL<2787> A_IWL<2786> A_IWL<2785> A_IWL<2784> A_IWL<2783> A_IWL<2782> A_IWL<2781> A_IWL<2780> A_IWL<2779> A_IWL<2778> A_IWL<2777> A_IWL<2776> A_IWL<2775> A_IWL<2774> A_IWL<2773> A_IWL<2772> A_IWL<2771> A_IWL<2770> A_IWL<2769> A_IWL<2768> A_IWL<2767> A_IWL<2766> A_IWL<2765> A_IWL<2764> A_IWL<2763> A_IWL<2762> A_IWL<2761> A_IWL<2760> A_IWL<2759> A_IWL<2758> A_IWL<2757> A_IWL<2756> A_IWL<2755> A_IWL<2754> A_IWL<2753> A_IWL<2752> A_IWL<2751> A_IWL<2750> A_IWL<2749> A_IWL<2748> A_IWL<2747> A_IWL<2746> A_IWL<2745> A_IWL<2744> A_IWL<2743> A_IWL<2742> A_IWL<2741> A_IWL<2740> A_IWL<2739> A_IWL<2738> A_IWL<2737> A_IWL<2736> A_IWL<2735> A_IWL<2734> A_IWL<2733> A_IWL<2732> A_IWL<2731> A_IWL<2730> A_IWL<2729> A_IWL<2728> A_IWL<2727> A_IWL<2726> A_IWL<2725> A_IWL<2724> A_IWL<2723> A_IWL<2722> A_IWL<2721> A_IWL<2720> A_IWL<2719> A_IWL<2718> A_IWL<2717> A_IWL<2716> A_IWL<2715> A_IWL<2714> A_IWL<2713> A_IWL<2712> A_IWL<2711> A_IWL<2710> A_IWL<2709> A_IWL<2708> A_IWL<2707> A_IWL<2706> A_IWL<2705> A_IWL<2704> A_IWL<2703> A_IWL<2702> A_IWL<2701> A_IWL<2700> A_IWL<2699> A_IWL<2698> A_IWL<2697> A_IWL<2696> A_IWL<2695> A_IWL<2694> A_IWL<2693> A_IWL<2692> A_IWL<2691> A_IWL<2690> A_IWL<2689> A_IWL<2688> A_IWL<2943> A_IWL<2942> A_IWL<2941> A_IWL<2940> A_IWL<2939> A_IWL<2938> A_IWL<2937> A_IWL<2936> A_IWL<2935> A_IWL<2934> A_IWL<2933> A_IWL<2932> A_IWL<2931> A_IWL<2930> A_IWL<2929> A_IWL<2928> A_IWL<2927> A_IWL<2926> A_IWL<2925> A_IWL<2924> A_IWL<2923> A_IWL<2922> A_IWL<2921> A_IWL<2920> A_IWL<2919> A_IWL<2918> A_IWL<2917> A_IWL<2916> A_IWL<2915> A_IWL<2914> A_IWL<2913> A_IWL<2912> A_IWL<2911> A_IWL<2910> A_IWL<2909> A_IWL<2908> A_IWL<2907> A_IWL<2906> A_IWL<2905> A_IWL<2904> A_IWL<2903> A_IWL<2902> A_IWL<2901> A_IWL<2900> A_IWL<2899> A_IWL<2898> A_IWL<2897> A_IWL<2896> A_IWL<2895> A_IWL<2894> A_IWL<2893> A_IWL<2892> A_IWL<2891> A_IWL<2890> A_IWL<2889> A_IWL<2888> A_IWL<2887> A_IWL<2886> A_IWL<2885> A_IWL<2884> A_IWL<2883> A_IWL<2882> A_IWL<2881> A_IWL<2880> A_IWL<2879> A_IWL<2878> A_IWL<2877> A_IWL<2876> A_IWL<2875> A_IWL<2874> A_IWL<2873> A_IWL<2872> A_IWL<2871> A_IWL<2870> A_IWL<2869> A_IWL<2868> A_IWL<2867> A_IWL<2866> A_IWL<2865> A_IWL<2864> A_IWL<2863> A_IWL<2862> A_IWL<2861> A_IWL<2860> A_IWL<2859> A_IWL<2858> A_IWL<2857> A_IWL<2856> A_IWL<2855> A_IWL<2854> A_IWL<2853> A_IWL<2852> A_IWL<2851> A_IWL<2850> A_IWL<2849> A_IWL<2848> A_IWL<2847> A_IWL<2846> A_IWL<2845> A_IWL<2844> A_IWL<2843> A_IWL<2842> A_IWL<2841> A_IWL<2840> A_IWL<2839> A_IWL<2838> A_IWL<2837> A_IWL<2836> A_IWL<2835> A_IWL<2834> A_IWL<2833> A_IWL<2832> A_IWL<2831> A_IWL<2830> A_IWL<2829> A_IWL<2828> A_IWL<2827> A_IWL<2826> A_IWL<2825> A_IWL<2824> A_IWL<2823> A_IWL<2822> A_IWL<2821> A_IWL<2820> A_IWL<2819> A_IWL<2818> A_IWL<2817> A_IWL<2816> VDD_CORE VSS / RM_IHPSG13_512x32_c2_1P_COLUMN_pcell_0 +XCOL<21> A_BLC<43> A_BLC<42> A_BLC_TOP<43> A_BLC_TOP<42> A_BLT<43> A_BLT<42> A_BLT_TOP<43> A_BLT_TOP<42> A_IWL<2687> A_IWL<2686> A_IWL<2685> A_IWL<2684> A_IWL<2683> A_IWL<2682> A_IWL<2681> A_IWL<2680> A_IWL<2679> A_IWL<2678> A_IWL<2677> A_IWL<2676> A_IWL<2675> A_IWL<2674> A_IWL<2673> A_IWL<2672> A_IWL<2671> A_IWL<2670> A_IWL<2669> A_IWL<2668> A_IWL<2667> A_IWL<2666> A_IWL<2665> A_IWL<2664> A_IWL<2663> A_IWL<2662> A_IWL<2661> A_IWL<2660> A_IWL<2659> A_IWL<2658> A_IWL<2657> A_IWL<2656> A_IWL<2655> A_IWL<2654> A_IWL<2653> A_IWL<2652> A_IWL<2651> A_IWL<2650> A_IWL<2649> A_IWL<2648> A_IWL<2647> A_IWL<2646> A_IWL<2645> A_IWL<2644> A_IWL<2643> A_IWL<2642> A_IWL<2641> A_IWL<2640> A_IWL<2639> A_IWL<2638> A_IWL<2637> A_IWL<2636> A_IWL<2635> A_IWL<2634> A_IWL<2633> A_IWL<2632> A_IWL<2631> A_IWL<2630> A_IWL<2629> A_IWL<2628> A_IWL<2627> A_IWL<2626> A_IWL<2625> A_IWL<2624> A_IWL<2623> A_IWL<2622> A_IWL<2621> A_IWL<2620> A_IWL<2619> A_IWL<2618> A_IWL<2617> A_IWL<2616> A_IWL<2615> A_IWL<2614> A_IWL<2613> A_IWL<2612> A_IWL<2611> A_IWL<2610> A_IWL<2609> A_IWL<2608> A_IWL<2607> A_IWL<2606> A_IWL<2605> A_IWL<2604> A_IWL<2603> A_IWL<2602> A_IWL<2601> A_IWL<2600> A_IWL<2599> A_IWL<2598> A_IWL<2597> A_IWL<2596> A_IWL<2595> A_IWL<2594> A_IWL<2593> A_IWL<2592> A_IWL<2591> A_IWL<2590> A_IWL<2589> A_IWL<2588> A_IWL<2587> A_IWL<2586> A_IWL<2585> A_IWL<2584> A_IWL<2583> A_IWL<2582> A_IWL<2581> A_IWL<2580> A_IWL<2579> A_IWL<2578> A_IWL<2577> A_IWL<2576> A_IWL<2575> A_IWL<2574> A_IWL<2573> A_IWL<2572> A_IWL<2571> A_IWL<2570> A_IWL<2569> A_IWL<2568> A_IWL<2567> A_IWL<2566> A_IWL<2565> A_IWL<2564> A_IWL<2563> A_IWL<2562> A_IWL<2561> A_IWL<2560> A_IWL<2815> A_IWL<2814> A_IWL<2813> A_IWL<2812> A_IWL<2811> A_IWL<2810> A_IWL<2809> A_IWL<2808> A_IWL<2807> A_IWL<2806> A_IWL<2805> A_IWL<2804> A_IWL<2803> A_IWL<2802> A_IWL<2801> A_IWL<2800> A_IWL<2799> A_IWL<2798> A_IWL<2797> A_IWL<2796> A_IWL<2795> A_IWL<2794> A_IWL<2793> A_IWL<2792> A_IWL<2791> A_IWL<2790> A_IWL<2789> A_IWL<2788> A_IWL<2787> A_IWL<2786> A_IWL<2785> A_IWL<2784> A_IWL<2783> A_IWL<2782> A_IWL<2781> A_IWL<2780> A_IWL<2779> A_IWL<2778> A_IWL<2777> A_IWL<2776> A_IWL<2775> A_IWL<2774> A_IWL<2773> A_IWL<2772> A_IWL<2771> A_IWL<2770> A_IWL<2769> A_IWL<2768> A_IWL<2767> A_IWL<2766> A_IWL<2765> A_IWL<2764> A_IWL<2763> A_IWL<2762> A_IWL<2761> A_IWL<2760> A_IWL<2759> A_IWL<2758> A_IWL<2757> A_IWL<2756> A_IWL<2755> A_IWL<2754> A_IWL<2753> A_IWL<2752> A_IWL<2751> A_IWL<2750> A_IWL<2749> A_IWL<2748> A_IWL<2747> A_IWL<2746> A_IWL<2745> A_IWL<2744> A_IWL<2743> A_IWL<2742> A_IWL<2741> A_IWL<2740> A_IWL<2739> A_IWL<2738> A_IWL<2737> A_IWL<2736> A_IWL<2735> A_IWL<2734> A_IWL<2733> A_IWL<2732> A_IWL<2731> A_IWL<2730> A_IWL<2729> A_IWL<2728> A_IWL<2727> A_IWL<2726> A_IWL<2725> A_IWL<2724> A_IWL<2723> A_IWL<2722> A_IWL<2721> A_IWL<2720> A_IWL<2719> A_IWL<2718> A_IWL<2717> A_IWL<2716> A_IWL<2715> A_IWL<2714> A_IWL<2713> A_IWL<2712> A_IWL<2711> A_IWL<2710> A_IWL<2709> A_IWL<2708> A_IWL<2707> A_IWL<2706> A_IWL<2705> A_IWL<2704> A_IWL<2703> A_IWL<2702> A_IWL<2701> A_IWL<2700> A_IWL<2699> A_IWL<2698> A_IWL<2697> A_IWL<2696> A_IWL<2695> A_IWL<2694> A_IWL<2693> A_IWL<2692> A_IWL<2691> A_IWL<2690> A_IWL<2689> A_IWL<2688> VDD_CORE VSS / RM_IHPSG13_512x32_c2_1P_COLUMN_pcell_0 +XCOL<20> A_BLC<41> A_BLC<40> A_BLC_TOP<41> A_BLC_TOP<40> A_BLT<41> A_BLT<40> A_BLT_TOP<41> A_BLT_TOP<40> A_IWL<2559> A_IWL<2558> A_IWL<2557> A_IWL<2556> A_IWL<2555> A_IWL<2554> A_IWL<2553> A_IWL<2552> A_IWL<2551> A_IWL<2550> A_IWL<2549> A_IWL<2548> A_IWL<2547> A_IWL<2546> A_IWL<2545> A_IWL<2544> A_IWL<2543> A_IWL<2542> A_IWL<2541> A_IWL<2540> A_IWL<2539> A_IWL<2538> A_IWL<2537> A_IWL<2536> A_IWL<2535> A_IWL<2534> A_IWL<2533> A_IWL<2532> A_IWL<2531> A_IWL<2530> A_IWL<2529> A_IWL<2528> A_IWL<2527> A_IWL<2526> A_IWL<2525> A_IWL<2524> A_IWL<2523> A_IWL<2522> A_IWL<2521> A_IWL<2520> A_IWL<2519> A_IWL<2518> A_IWL<2517> A_IWL<2516> A_IWL<2515> A_IWL<2514> A_IWL<2513> A_IWL<2512> A_IWL<2511> A_IWL<2510> A_IWL<2509> A_IWL<2508> A_IWL<2507> A_IWL<2506> A_IWL<2505> A_IWL<2504> A_IWL<2503> A_IWL<2502> A_IWL<2501> A_IWL<2500> A_IWL<2499> A_IWL<2498> A_IWL<2497> A_IWL<2496> A_IWL<2495> A_IWL<2494> A_IWL<2493> A_IWL<2492> A_IWL<2491> A_IWL<2490> A_IWL<2489> A_IWL<2488> A_IWL<2487> A_IWL<2486> A_IWL<2485> A_IWL<2484> A_IWL<2483> A_IWL<2482> A_IWL<2481> A_IWL<2480> A_IWL<2479> A_IWL<2478> A_IWL<2477> A_IWL<2476> A_IWL<2475> A_IWL<2474> A_IWL<2473> A_IWL<2472> A_IWL<2471> A_IWL<2470> A_IWL<2469> A_IWL<2468> A_IWL<2467> A_IWL<2466> A_IWL<2465> A_IWL<2464> A_IWL<2463> A_IWL<2462> A_IWL<2461> A_IWL<2460> A_IWL<2459> A_IWL<2458> A_IWL<2457> A_IWL<2456> A_IWL<2455> A_IWL<2454> A_IWL<2453> A_IWL<2452> A_IWL<2451> A_IWL<2450> A_IWL<2449> A_IWL<2448> A_IWL<2447> A_IWL<2446> A_IWL<2445> A_IWL<2444> A_IWL<2443> A_IWL<2442> A_IWL<2441> A_IWL<2440> A_IWL<2439> A_IWL<2438> A_IWL<2437> A_IWL<2436> A_IWL<2435> A_IWL<2434> A_IWL<2433> A_IWL<2432> A_IWL<2687> A_IWL<2686> A_IWL<2685> A_IWL<2684> A_IWL<2683> A_IWL<2682> A_IWL<2681> A_IWL<2680> A_IWL<2679> A_IWL<2678> A_IWL<2677> A_IWL<2676> A_IWL<2675> A_IWL<2674> A_IWL<2673> A_IWL<2672> A_IWL<2671> A_IWL<2670> A_IWL<2669> A_IWL<2668> A_IWL<2667> A_IWL<2666> A_IWL<2665> A_IWL<2664> A_IWL<2663> A_IWL<2662> A_IWL<2661> A_IWL<2660> A_IWL<2659> A_IWL<2658> A_IWL<2657> A_IWL<2656> A_IWL<2655> A_IWL<2654> A_IWL<2653> A_IWL<2652> A_IWL<2651> A_IWL<2650> A_IWL<2649> A_IWL<2648> A_IWL<2647> A_IWL<2646> A_IWL<2645> A_IWL<2644> A_IWL<2643> A_IWL<2642> A_IWL<2641> A_IWL<2640> A_IWL<2639> A_IWL<2638> A_IWL<2637> A_IWL<2636> A_IWL<2635> A_IWL<2634> A_IWL<2633> A_IWL<2632> A_IWL<2631> A_IWL<2630> A_IWL<2629> A_IWL<2628> A_IWL<2627> A_IWL<2626> A_IWL<2625> A_IWL<2624> A_IWL<2623> A_IWL<2622> A_IWL<2621> A_IWL<2620> A_IWL<2619> A_IWL<2618> A_IWL<2617> A_IWL<2616> A_IWL<2615> A_IWL<2614> A_IWL<2613> A_IWL<2612> A_IWL<2611> A_IWL<2610> A_IWL<2609> A_IWL<2608> A_IWL<2607> A_IWL<2606> A_IWL<2605> A_IWL<2604> A_IWL<2603> A_IWL<2602> A_IWL<2601> A_IWL<2600> A_IWL<2599> A_IWL<2598> A_IWL<2597> A_IWL<2596> A_IWL<2595> A_IWL<2594> A_IWL<2593> A_IWL<2592> A_IWL<2591> A_IWL<2590> A_IWL<2589> A_IWL<2588> A_IWL<2587> A_IWL<2586> A_IWL<2585> A_IWL<2584> A_IWL<2583> A_IWL<2582> A_IWL<2581> A_IWL<2580> A_IWL<2579> A_IWL<2578> A_IWL<2577> A_IWL<2576> A_IWL<2575> A_IWL<2574> A_IWL<2573> A_IWL<2572> A_IWL<2571> A_IWL<2570> A_IWL<2569> A_IWL<2568> A_IWL<2567> A_IWL<2566> A_IWL<2565> A_IWL<2564> A_IWL<2563> A_IWL<2562> A_IWL<2561> A_IWL<2560> VDD_CORE VSS / RM_IHPSG13_512x32_c2_1P_COLUMN_pcell_0 +XCOL<19> A_BLC<39> A_BLC<38> A_BLC_TOP<39> A_BLC_TOP<38> A_BLT<39> A_BLT<38> A_BLT_TOP<39> A_BLT_TOP<38> A_IWL<2431> A_IWL<2430> A_IWL<2429> A_IWL<2428> A_IWL<2427> A_IWL<2426> A_IWL<2425> A_IWL<2424> A_IWL<2423> A_IWL<2422> A_IWL<2421> A_IWL<2420> A_IWL<2419> A_IWL<2418> A_IWL<2417> A_IWL<2416> A_IWL<2415> A_IWL<2414> A_IWL<2413> A_IWL<2412> A_IWL<2411> A_IWL<2410> A_IWL<2409> A_IWL<2408> A_IWL<2407> A_IWL<2406> A_IWL<2405> A_IWL<2404> A_IWL<2403> A_IWL<2402> A_IWL<2401> A_IWL<2400> A_IWL<2399> A_IWL<2398> A_IWL<2397> A_IWL<2396> A_IWL<2395> A_IWL<2394> A_IWL<2393> A_IWL<2392> A_IWL<2391> A_IWL<2390> A_IWL<2389> A_IWL<2388> A_IWL<2387> A_IWL<2386> A_IWL<2385> A_IWL<2384> A_IWL<2383> A_IWL<2382> A_IWL<2381> A_IWL<2380> A_IWL<2379> A_IWL<2378> A_IWL<2377> A_IWL<2376> A_IWL<2375> A_IWL<2374> A_IWL<2373> A_IWL<2372> A_IWL<2371> A_IWL<2370> A_IWL<2369> A_IWL<2368> A_IWL<2367> A_IWL<2366> A_IWL<2365> A_IWL<2364> A_IWL<2363> A_IWL<2362> A_IWL<2361> A_IWL<2360> A_IWL<2359> A_IWL<2358> A_IWL<2357> A_IWL<2356> A_IWL<2355> A_IWL<2354> A_IWL<2353> A_IWL<2352> A_IWL<2351> A_IWL<2350> A_IWL<2349> A_IWL<2348> A_IWL<2347> A_IWL<2346> A_IWL<2345> A_IWL<2344> A_IWL<2343> A_IWL<2342> A_IWL<2341> A_IWL<2340> A_IWL<2339> A_IWL<2338> A_IWL<2337> A_IWL<2336> A_IWL<2335> A_IWL<2334> A_IWL<2333> A_IWL<2332> A_IWL<2331> A_IWL<2330> A_IWL<2329> A_IWL<2328> A_IWL<2327> A_IWL<2326> A_IWL<2325> A_IWL<2324> A_IWL<2323> A_IWL<2322> A_IWL<2321> A_IWL<2320> A_IWL<2319> A_IWL<2318> A_IWL<2317> A_IWL<2316> A_IWL<2315> A_IWL<2314> A_IWL<2313> A_IWL<2312> A_IWL<2311> A_IWL<2310> A_IWL<2309> A_IWL<2308> A_IWL<2307> A_IWL<2306> A_IWL<2305> A_IWL<2304> A_IWL<2559> A_IWL<2558> A_IWL<2557> A_IWL<2556> A_IWL<2555> A_IWL<2554> A_IWL<2553> A_IWL<2552> A_IWL<2551> A_IWL<2550> A_IWL<2549> A_IWL<2548> A_IWL<2547> A_IWL<2546> A_IWL<2545> A_IWL<2544> A_IWL<2543> A_IWL<2542> A_IWL<2541> A_IWL<2540> A_IWL<2539> A_IWL<2538> A_IWL<2537> A_IWL<2536> A_IWL<2535> A_IWL<2534> A_IWL<2533> A_IWL<2532> A_IWL<2531> A_IWL<2530> A_IWL<2529> A_IWL<2528> A_IWL<2527> A_IWL<2526> A_IWL<2525> A_IWL<2524> A_IWL<2523> A_IWL<2522> A_IWL<2521> A_IWL<2520> A_IWL<2519> A_IWL<2518> A_IWL<2517> A_IWL<2516> A_IWL<2515> A_IWL<2514> A_IWL<2513> A_IWL<2512> A_IWL<2511> A_IWL<2510> A_IWL<2509> A_IWL<2508> A_IWL<2507> A_IWL<2506> A_IWL<2505> A_IWL<2504> A_IWL<2503> A_IWL<2502> A_IWL<2501> A_IWL<2500> A_IWL<2499> A_IWL<2498> A_IWL<2497> A_IWL<2496> A_IWL<2495> A_IWL<2494> A_IWL<2493> A_IWL<2492> A_IWL<2491> A_IWL<2490> A_IWL<2489> A_IWL<2488> A_IWL<2487> A_IWL<2486> A_IWL<2485> A_IWL<2484> A_IWL<2483> A_IWL<2482> A_IWL<2481> A_IWL<2480> A_IWL<2479> A_IWL<2478> A_IWL<2477> A_IWL<2476> A_IWL<2475> A_IWL<2474> A_IWL<2473> A_IWL<2472> A_IWL<2471> A_IWL<2470> A_IWL<2469> A_IWL<2468> A_IWL<2467> A_IWL<2466> A_IWL<2465> A_IWL<2464> A_IWL<2463> A_IWL<2462> A_IWL<2461> A_IWL<2460> A_IWL<2459> A_IWL<2458> A_IWL<2457> A_IWL<2456> A_IWL<2455> A_IWL<2454> A_IWL<2453> A_IWL<2452> A_IWL<2451> A_IWL<2450> A_IWL<2449> A_IWL<2448> A_IWL<2447> A_IWL<2446> A_IWL<2445> A_IWL<2444> A_IWL<2443> A_IWL<2442> A_IWL<2441> A_IWL<2440> A_IWL<2439> A_IWL<2438> A_IWL<2437> A_IWL<2436> A_IWL<2435> A_IWL<2434> A_IWL<2433> A_IWL<2432> VDD_CORE VSS / RM_IHPSG13_512x32_c2_1P_COLUMN_pcell_0 +XCOL<18> A_BLC<37> A_BLC<36> A_BLC_TOP<37> A_BLC_TOP<36> A_BLT<37> A_BLT<36> A_BLT_TOP<37> A_BLT_TOP<36> A_IWL<2303> A_IWL<2302> A_IWL<2301> A_IWL<2300> A_IWL<2299> A_IWL<2298> A_IWL<2297> A_IWL<2296> A_IWL<2295> A_IWL<2294> A_IWL<2293> A_IWL<2292> A_IWL<2291> A_IWL<2290> A_IWL<2289> A_IWL<2288> A_IWL<2287> A_IWL<2286> A_IWL<2285> A_IWL<2284> A_IWL<2283> A_IWL<2282> A_IWL<2281> A_IWL<2280> A_IWL<2279> A_IWL<2278> A_IWL<2277> A_IWL<2276> A_IWL<2275> A_IWL<2274> A_IWL<2273> A_IWL<2272> A_IWL<2271> A_IWL<2270> A_IWL<2269> A_IWL<2268> A_IWL<2267> A_IWL<2266> A_IWL<2265> A_IWL<2264> A_IWL<2263> A_IWL<2262> A_IWL<2261> A_IWL<2260> A_IWL<2259> A_IWL<2258> A_IWL<2257> A_IWL<2256> A_IWL<2255> A_IWL<2254> A_IWL<2253> A_IWL<2252> A_IWL<2251> A_IWL<2250> A_IWL<2249> A_IWL<2248> A_IWL<2247> A_IWL<2246> A_IWL<2245> A_IWL<2244> A_IWL<2243> A_IWL<2242> A_IWL<2241> A_IWL<2240> A_IWL<2239> A_IWL<2238> A_IWL<2237> A_IWL<2236> A_IWL<2235> A_IWL<2234> A_IWL<2233> A_IWL<2232> A_IWL<2231> A_IWL<2230> A_IWL<2229> A_IWL<2228> A_IWL<2227> A_IWL<2226> A_IWL<2225> A_IWL<2224> A_IWL<2223> A_IWL<2222> A_IWL<2221> A_IWL<2220> A_IWL<2219> A_IWL<2218> A_IWL<2217> A_IWL<2216> A_IWL<2215> A_IWL<2214> A_IWL<2213> A_IWL<2212> A_IWL<2211> A_IWL<2210> A_IWL<2209> A_IWL<2208> A_IWL<2207> A_IWL<2206> A_IWL<2205> A_IWL<2204> A_IWL<2203> A_IWL<2202> A_IWL<2201> A_IWL<2200> A_IWL<2199> A_IWL<2198> A_IWL<2197> A_IWL<2196> A_IWL<2195> A_IWL<2194> A_IWL<2193> A_IWL<2192> A_IWL<2191> A_IWL<2190> A_IWL<2189> A_IWL<2188> A_IWL<2187> A_IWL<2186> A_IWL<2185> A_IWL<2184> A_IWL<2183> A_IWL<2182> A_IWL<2181> A_IWL<2180> A_IWL<2179> A_IWL<2178> A_IWL<2177> A_IWL<2176> A_IWL<2431> A_IWL<2430> A_IWL<2429> A_IWL<2428> A_IWL<2427> A_IWL<2426> A_IWL<2425> A_IWL<2424> A_IWL<2423> A_IWL<2422> A_IWL<2421> A_IWL<2420> A_IWL<2419> A_IWL<2418> A_IWL<2417> A_IWL<2416> A_IWL<2415> A_IWL<2414> A_IWL<2413> A_IWL<2412> A_IWL<2411> A_IWL<2410> A_IWL<2409> A_IWL<2408> A_IWL<2407> A_IWL<2406> A_IWL<2405> A_IWL<2404> A_IWL<2403> A_IWL<2402> A_IWL<2401> A_IWL<2400> A_IWL<2399> A_IWL<2398> A_IWL<2397> A_IWL<2396> A_IWL<2395> A_IWL<2394> A_IWL<2393> A_IWL<2392> A_IWL<2391> A_IWL<2390> A_IWL<2389> A_IWL<2388> A_IWL<2387> A_IWL<2386> A_IWL<2385> A_IWL<2384> A_IWL<2383> A_IWL<2382> A_IWL<2381> A_IWL<2380> A_IWL<2379> A_IWL<2378> A_IWL<2377> A_IWL<2376> A_IWL<2375> A_IWL<2374> A_IWL<2373> A_IWL<2372> A_IWL<2371> A_IWL<2370> A_IWL<2369> A_IWL<2368> A_IWL<2367> A_IWL<2366> A_IWL<2365> A_IWL<2364> A_IWL<2363> A_IWL<2362> A_IWL<2361> A_IWL<2360> A_IWL<2359> A_IWL<2358> A_IWL<2357> A_IWL<2356> A_IWL<2355> A_IWL<2354> A_IWL<2353> A_IWL<2352> A_IWL<2351> A_IWL<2350> A_IWL<2349> A_IWL<2348> A_IWL<2347> A_IWL<2346> A_IWL<2345> A_IWL<2344> A_IWL<2343> A_IWL<2342> A_IWL<2341> A_IWL<2340> A_IWL<2339> A_IWL<2338> A_IWL<2337> A_IWL<2336> A_IWL<2335> A_IWL<2334> A_IWL<2333> A_IWL<2332> A_IWL<2331> A_IWL<2330> A_IWL<2329> A_IWL<2328> A_IWL<2327> A_IWL<2326> A_IWL<2325> A_IWL<2324> A_IWL<2323> A_IWL<2322> A_IWL<2321> A_IWL<2320> A_IWL<2319> A_IWL<2318> A_IWL<2317> A_IWL<2316> A_IWL<2315> A_IWL<2314> A_IWL<2313> A_IWL<2312> A_IWL<2311> A_IWL<2310> A_IWL<2309> A_IWL<2308> A_IWL<2307> A_IWL<2306> A_IWL<2305> A_IWL<2304> VDD_CORE VSS / RM_IHPSG13_512x32_c2_1P_COLUMN_pcell_0 +XCOL<17> A_BLC<35> A_BLC<34> A_BLC_TOP<35> A_BLC_TOP<34> A_BLT<35> A_BLT<34> A_BLT_TOP<35> A_BLT_TOP<34> A_IWL<2175> A_IWL<2174> A_IWL<2173> A_IWL<2172> A_IWL<2171> A_IWL<2170> A_IWL<2169> A_IWL<2168> A_IWL<2167> A_IWL<2166> A_IWL<2165> A_IWL<2164> A_IWL<2163> A_IWL<2162> A_IWL<2161> A_IWL<2160> A_IWL<2159> A_IWL<2158> A_IWL<2157> A_IWL<2156> A_IWL<2155> A_IWL<2154> A_IWL<2153> A_IWL<2152> A_IWL<2151> A_IWL<2150> A_IWL<2149> A_IWL<2148> A_IWL<2147> A_IWL<2146> A_IWL<2145> A_IWL<2144> A_IWL<2143> A_IWL<2142> A_IWL<2141> A_IWL<2140> A_IWL<2139> A_IWL<2138> A_IWL<2137> A_IWL<2136> A_IWL<2135> A_IWL<2134> A_IWL<2133> A_IWL<2132> A_IWL<2131> A_IWL<2130> A_IWL<2129> A_IWL<2128> A_IWL<2127> A_IWL<2126> A_IWL<2125> A_IWL<2124> A_IWL<2123> A_IWL<2122> A_IWL<2121> A_IWL<2120> A_IWL<2119> A_IWL<2118> A_IWL<2117> A_IWL<2116> A_IWL<2115> A_IWL<2114> A_IWL<2113> A_IWL<2112> A_IWL<2111> A_IWL<2110> A_IWL<2109> A_IWL<2108> A_IWL<2107> A_IWL<2106> A_IWL<2105> A_IWL<2104> A_IWL<2103> A_IWL<2102> A_IWL<2101> A_IWL<2100> A_IWL<2099> A_IWL<2098> A_IWL<2097> A_IWL<2096> A_IWL<2095> A_IWL<2094> A_IWL<2093> A_IWL<2092> A_IWL<2091> A_IWL<2090> A_IWL<2089> A_IWL<2088> A_IWL<2087> A_IWL<2086> A_IWL<2085> A_IWL<2084> A_IWL<2083> A_IWL<2082> A_IWL<2081> A_IWL<2080> A_IWL<2079> A_IWL<2078> A_IWL<2077> A_IWL<2076> A_IWL<2075> A_IWL<2074> A_IWL<2073> A_IWL<2072> A_IWL<2071> A_IWL<2070> A_IWL<2069> A_IWL<2068> A_IWL<2067> A_IWL<2066> A_IWL<2065> A_IWL<2064> A_IWL<2063> A_IWL<2062> A_IWL<2061> A_IWL<2060> A_IWL<2059> A_IWL<2058> A_IWL<2057> A_IWL<2056> A_IWL<2055> A_IWL<2054> A_IWL<2053> A_IWL<2052> A_IWL<2051> A_IWL<2050> A_IWL<2049> A_IWL<2048> A_IWL<2303> A_IWL<2302> A_IWL<2301> A_IWL<2300> A_IWL<2299> A_IWL<2298> A_IWL<2297> A_IWL<2296> A_IWL<2295> A_IWL<2294> A_IWL<2293> A_IWL<2292> A_IWL<2291> A_IWL<2290> A_IWL<2289> A_IWL<2288> A_IWL<2287> A_IWL<2286> A_IWL<2285> A_IWL<2284> A_IWL<2283> A_IWL<2282> A_IWL<2281> A_IWL<2280> A_IWL<2279> A_IWL<2278> A_IWL<2277> A_IWL<2276> A_IWL<2275> A_IWL<2274> A_IWL<2273> A_IWL<2272> A_IWL<2271> A_IWL<2270> A_IWL<2269> A_IWL<2268> A_IWL<2267> A_IWL<2266> A_IWL<2265> A_IWL<2264> A_IWL<2263> A_IWL<2262> A_IWL<2261> A_IWL<2260> A_IWL<2259> A_IWL<2258> A_IWL<2257> A_IWL<2256> A_IWL<2255> A_IWL<2254> A_IWL<2253> A_IWL<2252> A_IWL<2251> A_IWL<2250> A_IWL<2249> A_IWL<2248> A_IWL<2247> A_IWL<2246> A_IWL<2245> A_IWL<2244> A_IWL<2243> A_IWL<2242> A_IWL<2241> A_IWL<2240> A_IWL<2239> A_IWL<2238> A_IWL<2237> A_IWL<2236> A_IWL<2235> A_IWL<2234> A_IWL<2233> A_IWL<2232> A_IWL<2231> A_IWL<2230> A_IWL<2229> A_IWL<2228> A_IWL<2227> A_IWL<2226> A_IWL<2225> A_IWL<2224> A_IWL<2223> A_IWL<2222> A_IWL<2221> A_IWL<2220> A_IWL<2219> A_IWL<2218> A_IWL<2217> A_IWL<2216> A_IWL<2215> A_IWL<2214> A_IWL<2213> A_IWL<2212> A_IWL<2211> A_IWL<2210> A_IWL<2209> A_IWL<2208> A_IWL<2207> A_IWL<2206> A_IWL<2205> A_IWL<2204> A_IWL<2203> A_IWL<2202> A_IWL<2201> A_IWL<2200> A_IWL<2199> A_IWL<2198> A_IWL<2197> A_IWL<2196> A_IWL<2195> A_IWL<2194> A_IWL<2193> A_IWL<2192> A_IWL<2191> A_IWL<2190> A_IWL<2189> A_IWL<2188> A_IWL<2187> A_IWL<2186> A_IWL<2185> A_IWL<2184> A_IWL<2183> A_IWL<2182> A_IWL<2181> A_IWL<2180> A_IWL<2179> A_IWL<2178> A_IWL<2177> A_IWL<2176> VDD_CORE VSS / RM_IHPSG13_512x32_c2_1P_COLUMN_pcell_0 +XCOL<16> A_BLC<33> A_BLC<32> A_BLC_TOP<33> A_BLC_TOP<32> A_BLT<33> A_BLT<32> A_BLT_TOP<33> A_BLT_TOP<32> A_IWL<2047> A_IWL<2046> A_IWL<2045> A_IWL<2044> A_IWL<2043> A_IWL<2042> A_IWL<2041> A_IWL<2040> A_IWL<2039> A_IWL<2038> A_IWL<2037> A_IWL<2036> A_IWL<2035> A_IWL<2034> A_IWL<2033> A_IWL<2032> A_IWL<2031> A_IWL<2030> A_IWL<2029> A_IWL<2028> A_IWL<2027> A_IWL<2026> A_IWL<2025> A_IWL<2024> A_IWL<2023> A_IWL<2022> A_IWL<2021> A_IWL<2020> A_IWL<2019> A_IWL<2018> A_IWL<2017> A_IWL<2016> A_IWL<2015> A_IWL<2014> A_IWL<2013> A_IWL<2012> A_IWL<2011> A_IWL<2010> A_IWL<2009> A_IWL<2008> A_IWL<2007> A_IWL<2006> A_IWL<2005> A_IWL<2004> A_IWL<2003> A_IWL<2002> A_IWL<2001> A_IWL<2000> A_IWL<1999> A_IWL<1998> A_IWL<1997> A_IWL<1996> A_IWL<1995> A_IWL<1994> A_IWL<1993> A_IWL<1992> A_IWL<1991> A_IWL<1990> A_IWL<1989> A_IWL<1988> A_IWL<1987> A_IWL<1986> A_IWL<1985> A_IWL<1984> A_IWL<1983> A_IWL<1982> A_IWL<1981> A_IWL<1980> A_IWL<1979> A_IWL<1978> A_IWL<1977> A_IWL<1976> A_IWL<1975> A_IWL<1974> A_IWL<1973> A_IWL<1972> A_IWL<1971> A_IWL<1970> A_IWL<1969> A_IWL<1968> A_IWL<1967> A_IWL<1966> A_IWL<1965> A_IWL<1964> A_IWL<1963> A_IWL<1962> A_IWL<1961> A_IWL<1960> A_IWL<1959> A_IWL<1958> A_IWL<1957> A_IWL<1956> A_IWL<1955> A_IWL<1954> A_IWL<1953> A_IWL<1952> A_IWL<1951> A_IWL<1950> A_IWL<1949> A_IWL<1948> A_IWL<1947> A_IWL<1946> A_IWL<1945> A_IWL<1944> A_IWL<1943> A_IWL<1942> A_IWL<1941> A_IWL<1940> A_IWL<1939> A_IWL<1938> A_IWL<1937> A_IWL<1936> A_IWL<1935> A_IWL<1934> A_IWL<1933> A_IWL<1932> A_IWL<1931> A_IWL<1930> A_IWL<1929> A_IWL<1928> A_IWL<1927> A_IWL<1926> A_IWL<1925> A_IWL<1924> A_IWL<1923> A_IWL<1922> A_IWL<1921> A_IWL<1920> A_IWL<2175> A_IWL<2174> A_IWL<2173> A_IWL<2172> A_IWL<2171> A_IWL<2170> A_IWL<2169> A_IWL<2168> A_IWL<2167> A_IWL<2166> A_IWL<2165> A_IWL<2164> A_IWL<2163> A_IWL<2162> A_IWL<2161> A_IWL<2160> A_IWL<2159> A_IWL<2158> A_IWL<2157> A_IWL<2156> A_IWL<2155> A_IWL<2154> A_IWL<2153> A_IWL<2152> A_IWL<2151> A_IWL<2150> A_IWL<2149> A_IWL<2148> A_IWL<2147> A_IWL<2146> A_IWL<2145> A_IWL<2144> A_IWL<2143> A_IWL<2142> A_IWL<2141> A_IWL<2140> A_IWL<2139> A_IWL<2138> A_IWL<2137> A_IWL<2136> A_IWL<2135> A_IWL<2134> A_IWL<2133> A_IWL<2132> A_IWL<2131> A_IWL<2130> A_IWL<2129> A_IWL<2128> A_IWL<2127> A_IWL<2126> A_IWL<2125> A_IWL<2124> A_IWL<2123> A_IWL<2122> A_IWL<2121> A_IWL<2120> A_IWL<2119> A_IWL<2118> A_IWL<2117> A_IWL<2116> A_IWL<2115> A_IWL<2114> A_IWL<2113> A_IWL<2112> A_IWL<2111> A_IWL<2110> A_IWL<2109> A_IWL<2108> A_IWL<2107> A_IWL<2106> A_IWL<2105> A_IWL<2104> A_IWL<2103> A_IWL<2102> A_IWL<2101> A_IWL<2100> A_IWL<2099> A_IWL<2098> A_IWL<2097> A_IWL<2096> A_IWL<2095> A_IWL<2094> A_IWL<2093> A_IWL<2092> A_IWL<2091> A_IWL<2090> A_IWL<2089> A_IWL<2088> A_IWL<2087> A_IWL<2086> A_IWL<2085> A_IWL<2084> A_IWL<2083> A_IWL<2082> A_IWL<2081> A_IWL<2080> A_IWL<2079> A_IWL<2078> A_IWL<2077> A_IWL<2076> A_IWL<2075> A_IWL<2074> A_IWL<2073> A_IWL<2072> A_IWL<2071> A_IWL<2070> A_IWL<2069> A_IWL<2068> A_IWL<2067> A_IWL<2066> A_IWL<2065> A_IWL<2064> A_IWL<2063> A_IWL<2062> A_IWL<2061> A_IWL<2060> A_IWL<2059> A_IWL<2058> A_IWL<2057> A_IWL<2056> A_IWL<2055> A_IWL<2054> A_IWL<2053> A_IWL<2052> A_IWL<2051> A_IWL<2050> A_IWL<2049> A_IWL<2048> VDD_CORE VSS / RM_IHPSG13_512x32_c2_1P_COLUMN_pcell_0 +XCOL<15> A_BLC<31> A_BLC<30> A_BLC_TOP<31> A_BLC_TOP<30> A_BLT<31> A_BLT<30> A_BLT_TOP<31> A_BLT_TOP<30> A_IWL<1919> A_IWL<1918> A_IWL<1917> A_IWL<1916> A_IWL<1915> A_IWL<1914> A_IWL<1913> A_IWL<1912> A_IWL<1911> A_IWL<1910> A_IWL<1909> A_IWL<1908> A_IWL<1907> A_IWL<1906> A_IWL<1905> A_IWL<1904> A_IWL<1903> A_IWL<1902> A_IWL<1901> A_IWL<1900> A_IWL<1899> A_IWL<1898> A_IWL<1897> A_IWL<1896> A_IWL<1895> A_IWL<1894> A_IWL<1893> A_IWL<1892> A_IWL<1891> A_IWL<1890> A_IWL<1889> A_IWL<1888> A_IWL<1887> A_IWL<1886> A_IWL<1885> A_IWL<1884> A_IWL<1883> A_IWL<1882> A_IWL<1881> A_IWL<1880> A_IWL<1879> A_IWL<1878> A_IWL<1877> A_IWL<1876> A_IWL<1875> A_IWL<1874> A_IWL<1873> A_IWL<1872> A_IWL<1871> A_IWL<1870> A_IWL<1869> A_IWL<1868> A_IWL<1867> A_IWL<1866> A_IWL<1865> A_IWL<1864> A_IWL<1863> A_IWL<1862> A_IWL<1861> A_IWL<1860> A_IWL<1859> A_IWL<1858> A_IWL<1857> A_IWL<1856> A_IWL<1855> A_IWL<1854> A_IWL<1853> A_IWL<1852> A_IWL<1851> A_IWL<1850> A_IWL<1849> A_IWL<1848> A_IWL<1847> A_IWL<1846> A_IWL<1845> A_IWL<1844> A_IWL<1843> A_IWL<1842> A_IWL<1841> A_IWL<1840> A_IWL<1839> A_IWL<1838> A_IWL<1837> A_IWL<1836> A_IWL<1835> A_IWL<1834> A_IWL<1833> A_IWL<1832> A_IWL<1831> A_IWL<1830> A_IWL<1829> A_IWL<1828> A_IWL<1827> A_IWL<1826> A_IWL<1825> A_IWL<1824> A_IWL<1823> A_IWL<1822> A_IWL<1821> A_IWL<1820> A_IWL<1819> A_IWL<1818> A_IWL<1817> A_IWL<1816> A_IWL<1815> A_IWL<1814> A_IWL<1813> A_IWL<1812> A_IWL<1811> A_IWL<1810> A_IWL<1809> A_IWL<1808> A_IWL<1807> A_IWL<1806> A_IWL<1805> A_IWL<1804> A_IWL<1803> A_IWL<1802> A_IWL<1801> A_IWL<1800> A_IWL<1799> A_IWL<1798> A_IWL<1797> A_IWL<1796> A_IWL<1795> A_IWL<1794> A_IWL<1793> A_IWL<1792> A_IWL<2047> A_IWL<2046> A_IWL<2045> A_IWL<2044> A_IWL<2043> A_IWL<2042> A_IWL<2041> A_IWL<2040> A_IWL<2039> A_IWL<2038> A_IWL<2037> A_IWL<2036> A_IWL<2035> A_IWL<2034> A_IWL<2033> A_IWL<2032> A_IWL<2031> A_IWL<2030> A_IWL<2029> A_IWL<2028> A_IWL<2027> A_IWL<2026> A_IWL<2025> A_IWL<2024> A_IWL<2023> A_IWL<2022> A_IWL<2021> A_IWL<2020> A_IWL<2019> A_IWL<2018> A_IWL<2017> A_IWL<2016> A_IWL<2015> A_IWL<2014> A_IWL<2013> A_IWL<2012> A_IWL<2011> A_IWL<2010> A_IWL<2009> A_IWL<2008> A_IWL<2007> A_IWL<2006> A_IWL<2005> A_IWL<2004> A_IWL<2003> A_IWL<2002> A_IWL<2001> A_IWL<2000> A_IWL<1999> A_IWL<1998> A_IWL<1997> A_IWL<1996> A_IWL<1995> A_IWL<1994> A_IWL<1993> A_IWL<1992> A_IWL<1991> A_IWL<1990> A_IWL<1989> A_IWL<1988> A_IWL<1987> A_IWL<1986> A_IWL<1985> A_IWL<1984> A_IWL<1983> A_IWL<1982> A_IWL<1981> A_IWL<1980> A_IWL<1979> A_IWL<1978> A_IWL<1977> A_IWL<1976> A_IWL<1975> A_IWL<1974> A_IWL<1973> A_IWL<1972> A_IWL<1971> A_IWL<1970> A_IWL<1969> A_IWL<1968> A_IWL<1967> A_IWL<1966> A_IWL<1965> A_IWL<1964> A_IWL<1963> A_IWL<1962> A_IWL<1961> A_IWL<1960> A_IWL<1959> A_IWL<1958> A_IWL<1957> A_IWL<1956> A_IWL<1955> A_IWL<1954> A_IWL<1953> A_IWL<1952> A_IWL<1951> A_IWL<1950> A_IWL<1949> A_IWL<1948> A_IWL<1947> A_IWL<1946> A_IWL<1945> A_IWL<1944> A_IWL<1943> A_IWL<1942> A_IWL<1941> A_IWL<1940> A_IWL<1939> A_IWL<1938> A_IWL<1937> A_IWL<1936> A_IWL<1935> A_IWL<1934> A_IWL<1933> A_IWL<1932> A_IWL<1931> A_IWL<1930> A_IWL<1929> A_IWL<1928> A_IWL<1927> A_IWL<1926> A_IWL<1925> A_IWL<1924> A_IWL<1923> A_IWL<1922> A_IWL<1921> A_IWL<1920> VDD_CORE VSS / RM_IHPSG13_512x32_c2_1P_COLUMN_pcell_0 +XCOL<14> A_BLC<29> A_BLC<28> A_BLC_TOP<29> A_BLC_TOP<28> A_BLT<29> A_BLT<28> A_BLT_TOP<29> A_BLT_TOP<28> A_IWL<1791> A_IWL<1790> A_IWL<1789> A_IWL<1788> A_IWL<1787> A_IWL<1786> A_IWL<1785> A_IWL<1784> A_IWL<1783> A_IWL<1782> A_IWL<1781> A_IWL<1780> A_IWL<1779> A_IWL<1778> A_IWL<1777> A_IWL<1776> A_IWL<1775> A_IWL<1774> A_IWL<1773> A_IWL<1772> A_IWL<1771> A_IWL<1770> A_IWL<1769> A_IWL<1768> A_IWL<1767> A_IWL<1766> A_IWL<1765> A_IWL<1764> A_IWL<1763> A_IWL<1762> A_IWL<1761> A_IWL<1760> A_IWL<1759> A_IWL<1758> A_IWL<1757> A_IWL<1756> A_IWL<1755> A_IWL<1754> A_IWL<1753> A_IWL<1752> A_IWL<1751> A_IWL<1750> A_IWL<1749> A_IWL<1748> A_IWL<1747> A_IWL<1746> A_IWL<1745> A_IWL<1744> A_IWL<1743> A_IWL<1742> A_IWL<1741> A_IWL<1740> A_IWL<1739> A_IWL<1738> A_IWL<1737> A_IWL<1736> A_IWL<1735> A_IWL<1734> A_IWL<1733> A_IWL<1732> A_IWL<1731> A_IWL<1730> A_IWL<1729> A_IWL<1728> A_IWL<1727> A_IWL<1726> A_IWL<1725> A_IWL<1724> A_IWL<1723> A_IWL<1722> A_IWL<1721> A_IWL<1720> A_IWL<1719> A_IWL<1718> A_IWL<1717> A_IWL<1716> A_IWL<1715> A_IWL<1714> A_IWL<1713> A_IWL<1712> A_IWL<1711> A_IWL<1710> A_IWL<1709> A_IWL<1708> A_IWL<1707> A_IWL<1706> A_IWL<1705> A_IWL<1704> A_IWL<1703> A_IWL<1702> A_IWL<1701> A_IWL<1700> A_IWL<1699> A_IWL<1698> A_IWL<1697> A_IWL<1696> A_IWL<1695> A_IWL<1694> A_IWL<1693> A_IWL<1692> A_IWL<1691> A_IWL<1690> A_IWL<1689> A_IWL<1688> A_IWL<1687> A_IWL<1686> A_IWL<1685> A_IWL<1684> A_IWL<1683> A_IWL<1682> A_IWL<1681> A_IWL<1680> A_IWL<1679> A_IWL<1678> A_IWL<1677> A_IWL<1676> A_IWL<1675> A_IWL<1674> A_IWL<1673> A_IWL<1672> A_IWL<1671> A_IWL<1670> A_IWL<1669> A_IWL<1668> A_IWL<1667> A_IWL<1666> A_IWL<1665> A_IWL<1664> A_IWL<1919> A_IWL<1918> A_IWL<1917> A_IWL<1916> A_IWL<1915> A_IWL<1914> A_IWL<1913> A_IWL<1912> A_IWL<1911> A_IWL<1910> A_IWL<1909> A_IWL<1908> A_IWL<1907> A_IWL<1906> A_IWL<1905> A_IWL<1904> A_IWL<1903> A_IWL<1902> A_IWL<1901> A_IWL<1900> A_IWL<1899> A_IWL<1898> A_IWL<1897> A_IWL<1896> A_IWL<1895> A_IWL<1894> A_IWL<1893> A_IWL<1892> A_IWL<1891> A_IWL<1890> A_IWL<1889> A_IWL<1888> A_IWL<1887> A_IWL<1886> A_IWL<1885> A_IWL<1884> A_IWL<1883> A_IWL<1882> A_IWL<1881> A_IWL<1880> A_IWL<1879> A_IWL<1878> A_IWL<1877> A_IWL<1876> A_IWL<1875> A_IWL<1874> A_IWL<1873> A_IWL<1872> A_IWL<1871> A_IWL<1870> A_IWL<1869> A_IWL<1868> A_IWL<1867> A_IWL<1866> A_IWL<1865> A_IWL<1864> A_IWL<1863> A_IWL<1862> A_IWL<1861> A_IWL<1860> A_IWL<1859> A_IWL<1858> A_IWL<1857> A_IWL<1856> A_IWL<1855> A_IWL<1854> A_IWL<1853> A_IWL<1852> A_IWL<1851> A_IWL<1850> A_IWL<1849> A_IWL<1848> A_IWL<1847> A_IWL<1846> A_IWL<1845> A_IWL<1844> A_IWL<1843> A_IWL<1842> A_IWL<1841> A_IWL<1840> A_IWL<1839> A_IWL<1838> A_IWL<1837> A_IWL<1836> A_IWL<1835> A_IWL<1834> A_IWL<1833> A_IWL<1832> A_IWL<1831> A_IWL<1830> A_IWL<1829> A_IWL<1828> A_IWL<1827> A_IWL<1826> A_IWL<1825> A_IWL<1824> A_IWL<1823> A_IWL<1822> A_IWL<1821> A_IWL<1820> A_IWL<1819> A_IWL<1818> A_IWL<1817> A_IWL<1816> A_IWL<1815> A_IWL<1814> A_IWL<1813> A_IWL<1812> A_IWL<1811> A_IWL<1810> A_IWL<1809> A_IWL<1808> A_IWL<1807> A_IWL<1806> A_IWL<1805> A_IWL<1804> A_IWL<1803> A_IWL<1802> A_IWL<1801> A_IWL<1800> A_IWL<1799> A_IWL<1798> A_IWL<1797> A_IWL<1796> A_IWL<1795> A_IWL<1794> A_IWL<1793> A_IWL<1792> VDD_CORE VSS / RM_IHPSG13_512x32_c2_1P_COLUMN_pcell_0 +XCOL<13> A_BLC<27> A_BLC<26> A_BLC_TOP<27> A_BLC_TOP<26> A_BLT<27> A_BLT<26> A_BLT_TOP<27> A_BLT_TOP<26> A_IWL<1663> A_IWL<1662> A_IWL<1661> A_IWL<1660> A_IWL<1659> A_IWL<1658> A_IWL<1657> A_IWL<1656> A_IWL<1655> A_IWL<1654> A_IWL<1653> A_IWL<1652> A_IWL<1651> A_IWL<1650> A_IWL<1649> A_IWL<1648> A_IWL<1647> A_IWL<1646> A_IWL<1645> A_IWL<1644> A_IWL<1643> A_IWL<1642> A_IWL<1641> A_IWL<1640> A_IWL<1639> A_IWL<1638> A_IWL<1637> A_IWL<1636> A_IWL<1635> A_IWL<1634> A_IWL<1633> A_IWL<1632> A_IWL<1631> A_IWL<1630> A_IWL<1629> A_IWL<1628> A_IWL<1627> A_IWL<1626> A_IWL<1625> A_IWL<1624> A_IWL<1623> A_IWL<1622> A_IWL<1621> A_IWL<1620> A_IWL<1619> A_IWL<1618> A_IWL<1617> A_IWL<1616> A_IWL<1615> A_IWL<1614> A_IWL<1613> A_IWL<1612> A_IWL<1611> A_IWL<1610> A_IWL<1609> A_IWL<1608> A_IWL<1607> A_IWL<1606> A_IWL<1605> A_IWL<1604> A_IWL<1603> A_IWL<1602> A_IWL<1601> A_IWL<1600> A_IWL<1599> A_IWL<1598> A_IWL<1597> A_IWL<1596> A_IWL<1595> A_IWL<1594> A_IWL<1593> A_IWL<1592> A_IWL<1591> A_IWL<1590> A_IWL<1589> A_IWL<1588> A_IWL<1587> A_IWL<1586> A_IWL<1585> A_IWL<1584> A_IWL<1583> A_IWL<1582> A_IWL<1581> A_IWL<1580> A_IWL<1579> A_IWL<1578> A_IWL<1577> A_IWL<1576> A_IWL<1575> A_IWL<1574> A_IWL<1573> A_IWL<1572> A_IWL<1571> A_IWL<1570> A_IWL<1569> A_IWL<1568> A_IWL<1567> A_IWL<1566> A_IWL<1565> A_IWL<1564> A_IWL<1563> A_IWL<1562> A_IWL<1561> A_IWL<1560> A_IWL<1559> A_IWL<1558> A_IWL<1557> A_IWL<1556> A_IWL<1555> A_IWL<1554> A_IWL<1553> A_IWL<1552> A_IWL<1551> A_IWL<1550> A_IWL<1549> A_IWL<1548> A_IWL<1547> A_IWL<1546> A_IWL<1545> A_IWL<1544> A_IWL<1543> A_IWL<1542> A_IWL<1541> A_IWL<1540> A_IWL<1539> A_IWL<1538> A_IWL<1537> A_IWL<1536> A_IWL<1791> A_IWL<1790> A_IWL<1789> A_IWL<1788> A_IWL<1787> A_IWL<1786> A_IWL<1785> A_IWL<1784> A_IWL<1783> A_IWL<1782> A_IWL<1781> A_IWL<1780> A_IWL<1779> A_IWL<1778> A_IWL<1777> A_IWL<1776> A_IWL<1775> A_IWL<1774> A_IWL<1773> A_IWL<1772> A_IWL<1771> A_IWL<1770> A_IWL<1769> A_IWL<1768> A_IWL<1767> A_IWL<1766> A_IWL<1765> A_IWL<1764> A_IWL<1763> A_IWL<1762> A_IWL<1761> A_IWL<1760> A_IWL<1759> A_IWL<1758> A_IWL<1757> A_IWL<1756> A_IWL<1755> A_IWL<1754> A_IWL<1753> A_IWL<1752> A_IWL<1751> A_IWL<1750> A_IWL<1749> A_IWL<1748> A_IWL<1747> A_IWL<1746> A_IWL<1745> A_IWL<1744> A_IWL<1743> A_IWL<1742> A_IWL<1741> A_IWL<1740> A_IWL<1739> A_IWL<1738> A_IWL<1737> A_IWL<1736> A_IWL<1735> A_IWL<1734> A_IWL<1733> A_IWL<1732> A_IWL<1731> A_IWL<1730> A_IWL<1729> A_IWL<1728> A_IWL<1727> A_IWL<1726> A_IWL<1725> A_IWL<1724> A_IWL<1723> A_IWL<1722> A_IWL<1721> A_IWL<1720> A_IWL<1719> A_IWL<1718> A_IWL<1717> A_IWL<1716> A_IWL<1715> A_IWL<1714> A_IWL<1713> A_IWL<1712> A_IWL<1711> A_IWL<1710> A_IWL<1709> A_IWL<1708> A_IWL<1707> A_IWL<1706> A_IWL<1705> A_IWL<1704> A_IWL<1703> A_IWL<1702> A_IWL<1701> A_IWL<1700> A_IWL<1699> A_IWL<1698> A_IWL<1697> A_IWL<1696> A_IWL<1695> A_IWL<1694> A_IWL<1693> A_IWL<1692> A_IWL<1691> A_IWL<1690> A_IWL<1689> A_IWL<1688> A_IWL<1687> A_IWL<1686> A_IWL<1685> A_IWL<1684> A_IWL<1683> A_IWL<1682> A_IWL<1681> A_IWL<1680> A_IWL<1679> A_IWL<1678> A_IWL<1677> A_IWL<1676> A_IWL<1675> A_IWL<1674> A_IWL<1673> A_IWL<1672> A_IWL<1671> A_IWL<1670> A_IWL<1669> A_IWL<1668> A_IWL<1667> A_IWL<1666> A_IWL<1665> A_IWL<1664> VDD_CORE VSS / RM_IHPSG13_512x32_c2_1P_COLUMN_pcell_0 +XCOL<12> A_BLC<25> A_BLC<24> A_BLC_TOP<25> A_BLC_TOP<24> A_BLT<25> A_BLT<24> A_BLT_TOP<25> A_BLT_TOP<24> A_IWL<1535> A_IWL<1534> A_IWL<1533> A_IWL<1532> A_IWL<1531> A_IWL<1530> A_IWL<1529> A_IWL<1528> A_IWL<1527> A_IWL<1526> A_IWL<1525> A_IWL<1524> A_IWL<1523> A_IWL<1522> A_IWL<1521> A_IWL<1520> A_IWL<1519> A_IWL<1518> A_IWL<1517> A_IWL<1516> A_IWL<1515> A_IWL<1514> A_IWL<1513> A_IWL<1512> A_IWL<1511> A_IWL<1510> A_IWL<1509> A_IWL<1508> A_IWL<1507> A_IWL<1506> A_IWL<1505> A_IWL<1504> A_IWL<1503> A_IWL<1502> A_IWL<1501> A_IWL<1500> A_IWL<1499> A_IWL<1498> A_IWL<1497> A_IWL<1496> A_IWL<1495> A_IWL<1494> A_IWL<1493> A_IWL<1492> A_IWL<1491> A_IWL<1490> A_IWL<1489> A_IWL<1488> A_IWL<1487> A_IWL<1486> A_IWL<1485> A_IWL<1484> A_IWL<1483> A_IWL<1482> A_IWL<1481> A_IWL<1480> A_IWL<1479> A_IWL<1478> A_IWL<1477> A_IWL<1476> A_IWL<1475> A_IWL<1474> A_IWL<1473> A_IWL<1472> A_IWL<1471> A_IWL<1470> A_IWL<1469> A_IWL<1468> A_IWL<1467> A_IWL<1466> A_IWL<1465> A_IWL<1464> A_IWL<1463> A_IWL<1462> A_IWL<1461> A_IWL<1460> A_IWL<1459> A_IWL<1458> A_IWL<1457> A_IWL<1456> A_IWL<1455> A_IWL<1454> A_IWL<1453> A_IWL<1452> A_IWL<1451> A_IWL<1450> A_IWL<1449> A_IWL<1448> A_IWL<1447> A_IWL<1446> A_IWL<1445> A_IWL<1444> A_IWL<1443> A_IWL<1442> A_IWL<1441> A_IWL<1440> A_IWL<1439> A_IWL<1438> A_IWL<1437> A_IWL<1436> A_IWL<1435> A_IWL<1434> A_IWL<1433> A_IWL<1432> A_IWL<1431> A_IWL<1430> A_IWL<1429> A_IWL<1428> A_IWL<1427> A_IWL<1426> A_IWL<1425> A_IWL<1424> A_IWL<1423> A_IWL<1422> A_IWL<1421> A_IWL<1420> A_IWL<1419> A_IWL<1418> A_IWL<1417> A_IWL<1416> A_IWL<1415> A_IWL<1414> A_IWL<1413> A_IWL<1412> A_IWL<1411> A_IWL<1410> A_IWL<1409> A_IWL<1408> A_IWL<1663> A_IWL<1662> A_IWL<1661> A_IWL<1660> A_IWL<1659> A_IWL<1658> A_IWL<1657> A_IWL<1656> A_IWL<1655> A_IWL<1654> A_IWL<1653> A_IWL<1652> A_IWL<1651> A_IWL<1650> A_IWL<1649> A_IWL<1648> A_IWL<1647> A_IWL<1646> A_IWL<1645> A_IWL<1644> A_IWL<1643> A_IWL<1642> A_IWL<1641> A_IWL<1640> A_IWL<1639> A_IWL<1638> A_IWL<1637> A_IWL<1636> A_IWL<1635> A_IWL<1634> A_IWL<1633> A_IWL<1632> A_IWL<1631> A_IWL<1630> A_IWL<1629> A_IWL<1628> A_IWL<1627> A_IWL<1626> A_IWL<1625> A_IWL<1624> A_IWL<1623> A_IWL<1622> A_IWL<1621> A_IWL<1620> A_IWL<1619> A_IWL<1618> A_IWL<1617> A_IWL<1616> A_IWL<1615> A_IWL<1614> A_IWL<1613> A_IWL<1612> A_IWL<1611> A_IWL<1610> A_IWL<1609> A_IWL<1608> A_IWL<1607> A_IWL<1606> A_IWL<1605> A_IWL<1604> A_IWL<1603> A_IWL<1602> A_IWL<1601> A_IWL<1600> A_IWL<1599> A_IWL<1598> A_IWL<1597> A_IWL<1596> A_IWL<1595> A_IWL<1594> A_IWL<1593> A_IWL<1592> A_IWL<1591> A_IWL<1590> A_IWL<1589> A_IWL<1588> A_IWL<1587> A_IWL<1586> A_IWL<1585> A_IWL<1584> A_IWL<1583> A_IWL<1582> A_IWL<1581> A_IWL<1580> A_IWL<1579> A_IWL<1578> A_IWL<1577> A_IWL<1576> A_IWL<1575> A_IWL<1574> A_IWL<1573> A_IWL<1572> A_IWL<1571> A_IWL<1570> A_IWL<1569> A_IWL<1568> A_IWL<1567> A_IWL<1566> A_IWL<1565> A_IWL<1564> A_IWL<1563> A_IWL<1562> A_IWL<1561> A_IWL<1560> A_IWL<1559> A_IWL<1558> A_IWL<1557> A_IWL<1556> A_IWL<1555> A_IWL<1554> A_IWL<1553> A_IWL<1552> A_IWL<1551> A_IWL<1550> A_IWL<1549> A_IWL<1548> A_IWL<1547> A_IWL<1546> A_IWL<1545> A_IWL<1544> A_IWL<1543> A_IWL<1542> A_IWL<1541> A_IWL<1540> A_IWL<1539> A_IWL<1538> A_IWL<1537> A_IWL<1536> VDD_CORE VSS / RM_IHPSG13_512x32_c2_1P_COLUMN_pcell_0 +XCOL<11> A_BLC<23> A_BLC<22> A_BLC_TOP<23> A_BLC_TOP<22> A_BLT<23> A_BLT<22> A_BLT_TOP<23> A_BLT_TOP<22> A_IWL<1407> A_IWL<1406> A_IWL<1405> A_IWL<1404> A_IWL<1403> A_IWL<1402> A_IWL<1401> A_IWL<1400> A_IWL<1399> A_IWL<1398> A_IWL<1397> A_IWL<1396> A_IWL<1395> A_IWL<1394> A_IWL<1393> A_IWL<1392> A_IWL<1391> A_IWL<1390> A_IWL<1389> A_IWL<1388> A_IWL<1387> A_IWL<1386> A_IWL<1385> A_IWL<1384> A_IWL<1383> A_IWL<1382> A_IWL<1381> A_IWL<1380> A_IWL<1379> A_IWL<1378> A_IWL<1377> A_IWL<1376> A_IWL<1375> A_IWL<1374> A_IWL<1373> A_IWL<1372> A_IWL<1371> A_IWL<1370> A_IWL<1369> A_IWL<1368> A_IWL<1367> A_IWL<1366> A_IWL<1365> A_IWL<1364> A_IWL<1363> A_IWL<1362> A_IWL<1361> A_IWL<1360> A_IWL<1359> A_IWL<1358> A_IWL<1357> A_IWL<1356> A_IWL<1355> A_IWL<1354> A_IWL<1353> A_IWL<1352> A_IWL<1351> A_IWL<1350> A_IWL<1349> A_IWL<1348> A_IWL<1347> A_IWL<1346> A_IWL<1345> A_IWL<1344> A_IWL<1343> A_IWL<1342> A_IWL<1341> A_IWL<1340> A_IWL<1339> A_IWL<1338> A_IWL<1337> A_IWL<1336> A_IWL<1335> A_IWL<1334> A_IWL<1333> A_IWL<1332> A_IWL<1331> A_IWL<1330> A_IWL<1329> A_IWL<1328> A_IWL<1327> A_IWL<1326> A_IWL<1325> A_IWL<1324> A_IWL<1323> A_IWL<1322> A_IWL<1321> A_IWL<1320> A_IWL<1319> A_IWL<1318> A_IWL<1317> A_IWL<1316> A_IWL<1315> A_IWL<1314> A_IWL<1313> A_IWL<1312> A_IWL<1311> A_IWL<1310> A_IWL<1309> A_IWL<1308> A_IWL<1307> A_IWL<1306> A_IWL<1305> A_IWL<1304> A_IWL<1303> A_IWL<1302> A_IWL<1301> A_IWL<1300> A_IWL<1299> A_IWL<1298> A_IWL<1297> A_IWL<1296> A_IWL<1295> A_IWL<1294> A_IWL<1293> A_IWL<1292> A_IWL<1291> A_IWL<1290> A_IWL<1289> A_IWL<1288> A_IWL<1287> A_IWL<1286> A_IWL<1285> A_IWL<1284> A_IWL<1283> A_IWL<1282> A_IWL<1281> A_IWL<1280> A_IWL<1535> A_IWL<1534> A_IWL<1533> A_IWL<1532> A_IWL<1531> A_IWL<1530> A_IWL<1529> A_IWL<1528> A_IWL<1527> A_IWL<1526> A_IWL<1525> A_IWL<1524> A_IWL<1523> A_IWL<1522> A_IWL<1521> A_IWL<1520> A_IWL<1519> A_IWL<1518> A_IWL<1517> A_IWL<1516> A_IWL<1515> A_IWL<1514> A_IWL<1513> A_IWL<1512> A_IWL<1511> A_IWL<1510> A_IWL<1509> A_IWL<1508> A_IWL<1507> A_IWL<1506> A_IWL<1505> A_IWL<1504> A_IWL<1503> A_IWL<1502> A_IWL<1501> A_IWL<1500> A_IWL<1499> A_IWL<1498> A_IWL<1497> A_IWL<1496> A_IWL<1495> A_IWL<1494> A_IWL<1493> A_IWL<1492> A_IWL<1491> A_IWL<1490> A_IWL<1489> A_IWL<1488> A_IWL<1487> A_IWL<1486> A_IWL<1485> A_IWL<1484> A_IWL<1483> A_IWL<1482> A_IWL<1481> A_IWL<1480> A_IWL<1479> A_IWL<1478> A_IWL<1477> A_IWL<1476> A_IWL<1475> A_IWL<1474> A_IWL<1473> A_IWL<1472> A_IWL<1471> A_IWL<1470> A_IWL<1469> A_IWL<1468> A_IWL<1467> A_IWL<1466> A_IWL<1465> A_IWL<1464> A_IWL<1463> A_IWL<1462> A_IWL<1461> A_IWL<1460> A_IWL<1459> A_IWL<1458> A_IWL<1457> A_IWL<1456> A_IWL<1455> A_IWL<1454> A_IWL<1453> A_IWL<1452> A_IWL<1451> A_IWL<1450> A_IWL<1449> A_IWL<1448> A_IWL<1447> A_IWL<1446> A_IWL<1445> A_IWL<1444> A_IWL<1443> A_IWL<1442> A_IWL<1441> A_IWL<1440> A_IWL<1439> A_IWL<1438> A_IWL<1437> A_IWL<1436> A_IWL<1435> A_IWL<1434> A_IWL<1433> A_IWL<1432> A_IWL<1431> A_IWL<1430> A_IWL<1429> A_IWL<1428> A_IWL<1427> A_IWL<1426> A_IWL<1425> A_IWL<1424> A_IWL<1423> A_IWL<1422> A_IWL<1421> A_IWL<1420> A_IWL<1419> A_IWL<1418> A_IWL<1417> A_IWL<1416> A_IWL<1415> A_IWL<1414> A_IWL<1413> A_IWL<1412> A_IWL<1411> A_IWL<1410> A_IWL<1409> A_IWL<1408> VDD_CORE VSS / RM_IHPSG13_512x32_c2_1P_COLUMN_pcell_0 +XCOL<10> A_BLC<21> A_BLC<20> A_BLC_TOP<21> A_BLC_TOP<20> A_BLT<21> A_BLT<20> A_BLT_TOP<21> A_BLT_TOP<20> A_IWL<1279> A_IWL<1278> A_IWL<1277> A_IWL<1276> A_IWL<1275> A_IWL<1274> A_IWL<1273> A_IWL<1272> A_IWL<1271> A_IWL<1270> A_IWL<1269> A_IWL<1268> A_IWL<1267> A_IWL<1266> A_IWL<1265> A_IWL<1264> A_IWL<1263> A_IWL<1262> A_IWL<1261> A_IWL<1260> A_IWL<1259> A_IWL<1258> A_IWL<1257> A_IWL<1256> A_IWL<1255> A_IWL<1254> A_IWL<1253> A_IWL<1252> A_IWL<1251> A_IWL<1250> A_IWL<1249> A_IWL<1248> A_IWL<1247> A_IWL<1246> A_IWL<1245> A_IWL<1244> A_IWL<1243> A_IWL<1242> A_IWL<1241> A_IWL<1240> A_IWL<1239> A_IWL<1238> A_IWL<1237> A_IWL<1236> A_IWL<1235> A_IWL<1234> A_IWL<1233> A_IWL<1232> A_IWL<1231> A_IWL<1230> A_IWL<1229> A_IWL<1228> A_IWL<1227> A_IWL<1226> A_IWL<1225> A_IWL<1224> A_IWL<1223> A_IWL<1222> A_IWL<1221> A_IWL<1220> A_IWL<1219> A_IWL<1218> A_IWL<1217> A_IWL<1216> A_IWL<1215> A_IWL<1214> A_IWL<1213> A_IWL<1212> A_IWL<1211> A_IWL<1210> A_IWL<1209> A_IWL<1208> A_IWL<1207> A_IWL<1206> A_IWL<1205> A_IWL<1204> A_IWL<1203> A_IWL<1202> A_IWL<1201> A_IWL<1200> A_IWL<1199> A_IWL<1198> A_IWL<1197> A_IWL<1196> A_IWL<1195> A_IWL<1194> A_IWL<1193> A_IWL<1192> A_IWL<1191> A_IWL<1190> A_IWL<1189> A_IWL<1188> A_IWL<1187> A_IWL<1186> A_IWL<1185> A_IWL<1184> A_IWL<1183> A_IWL<1182> A_IWL<1181> A_IWL<1180> A_IWL<1179> A_IWL<1178> A_IWL<1177> A_IWL<1176> A_IWL<1175> A_IWL<1174> A_IWL<1173> A_IWL<1172> A_IWL<1171> A_IWL<1170> A_IWL<1169> A_IWL<1168> A_IWL<1167> A_IWL<1166> A_IWL<1165> A_IWL<1164> A_IWL<1163> A_IWL<1162> A_IWL<1161> A_IWL<1160> A_IWL<1159> A_IWL<1158> A_IWL<1157> A_IWL<1156> A_IWL<1155> A_IWL<1154> A_IWL<1153> A_IWL<1152> A_IWL<1407> A_IWL<1406> A_IWL<1405> A_IWL<1404> A_IWL<1403> A_IWL<1402> A_IWL<1401> A_IWL<1400> A_IWL<1399> A_IWL<1398> A_IWL<1397> A_IWL<1396> A_IWL<1395> A_IWL<1394> A_IWL<1393> A_IWL<1392> A_IWL<1391> A_IWL<1390> A_IWL<1389> A_IWL<1388> A_IWL<1387> A_IWL<1386> A_IWL<1385> A_IWL<1384> A_IWL<1383> A_IWL<1382> A_IWL<1381> A_IWL<1380> A_IWL<1379> A_IWL<1378> A_IWL<1377> A_IWL<1376> A_IWL<1375> A_IWL<1374> A_IWL<1373> A_IWL<1372> A_IWL<1371> A_IWL<1370> A_IWL<1369> A_IWL<1368> A_IWL<1367> A_IWL<1366> A_IWL<1365> A_IWL<1364> A_IWL<1363> A_IWL<1362> A_IWL<1361> A_IWL<1360> A_IWL<1359> A_IWL<1358> A_IWL<1357> A_IWL<1356> A_IWL<1355> A_IWL<1354> A_IWL<1353> A_IWL<1352> A_IWL<1351> A_IWL<1350> A_IWL<1349> A_IWL<1348> A_IWL<1347> A_IWL<1346> A_IWL<1345> A_IWL<1344> A_IWL<1343> A_IWL<1342> A_IWL<1341> A_IWL<1340> A_IWL<1339> A_IWL<1338> A_IWL<1337> A_IWL<1336> A_IWL<1335> A_IWL<1334> A_IWL<1333> A_IWL<1332> A_IWL<1331> A_IWL<1330> A_IWL<1329> A_IWL<1328> A_IWL<1327> A_IWL<1326> A_IWL<1325> A_IWL<1324> A_IWL<1323> A_IWL<1322> A_IWL<1321> A_IWL<1320> A_IWL<1319> A_IWL<1318> A_IWL<1317> A_IWL<1316> A_IWL<1315> A_IWL<1314> A_IWL<1313> A_IWL<1312> A_IWL<1311> A_IWL<1310> A_IWL<1309> A_IWL<1308> A_IWL<1307> A_IWL<1306> A_IWL<1305> A_IWL<1304> A_IWL<1303> A_IWL<1302> A_IWL<1301> A_IWL<1300> A_IWL<1299> A_IWL<1298> A_IWL<1297> A_IWL<1296> A_IWL<1295> A_IWL<1294> A_IWL<1293> A_IWL<1292> A_IWL<1291> A_IWL<1290> A_IWL<1289> A_IWL<1288> A_IWL<1287> A_IWL<1286> A_IWL<1285> A_IWL<1284> A_IWL<1283> A_IWL<1282> A_IWL<1281> A_IWL<1280> VDD_CORE VSS / RM_IHPSG13_512x32_c2_1P_COLUMN_pcell_0 +XCOL<9> A_BLC<19> A_BLC<18> A_BLC_TOP<19> A_BLC_TOP<18> A_BLT<19> A_BLT<18> A_BLT_TOP<19> A_BLT_TOP<18> A_IWL<1151> A_IWL<1150> A_IWL<1149> A_IWL<1148> A_IWL<1147> A_IWL<1146> A_IWL<1145> A_IWL<1144> A_IWL<1143> A_IWL<1142> A_IWL<1141> A_IWL<1140> A_IWL<1139> A_IWL<1138> A_IWL<1137> A_IWL<1136> A_IWL<1135> A_IWL<1134> A_IWL<1133> A_IWL<1132> A_IWL<1131> A_IWL<1130> A_IWL<1129> A_IWL<1128> A_IWL<1127> A_IWL<1126> A_IWL<1125> A_IWL<1124> A_IWL<1123> A_IWL<1122> A_IWL<1121> A_IWL<1120> A_IWL<1119> A_IWL<1118> A_IWL<1117> A_IWL<1116> A_IWL<1115> A_IWL<1114> A_IWL<1113> A_IWL<1112> A_IWL<1111> A_IWL<1110> A_IWL<1109> A_IWL<1108> A_IWL<1107> A_IWL<1106> A_IWL<1105> A_IWL<1104> A_IWL<1103> A_IWL<1102> A_IWL<1101> A_IWL<1100> A_IWL<1099> A_IWL<1098> A_IWL<1097> A_IWL<1096> A_IWL<1095> A_IWL<1094> A_IWL<1093> A_IWL<1092> A_IWL<1091> A_IWL<1090> A_IWL<1089> A_IWL<1088> A_IWL<1087> A_IWL<1086> A_IWL<1085> A_IWL<1084> A_IWL<1083> A_IWL<1082> A_IWL<1081> A_IWL<1080> A_IWL<1079> A_IWL<1078> A_IWL<1077> A_IWL<1076> A_IWL<1075> A_IWL<1074> A_IWL<1073> A_IWL<1072> A_IWL<1071> A_IWL<1070> A_IWL<1069> A_IWL<1068> A_IWL<1067> A_IWL<1066> A_IWL<1065> A_IWL<1064> A_IWL<1063> A_IWL<1062> A_IWL<1061> A_IWL<1060> A_IWL<1059> A_IWL<1058> A_IWL<1057> A_IWL<1056> A_IWL<1055> A_IWL<1054> A_IWL<1053> A_IWL<1052> A_IWL<1051> A_IWL<1050> A_IWL<1049> A_IWL<1048> A_IWL<1047> A_IWL<1046> A_IWL<1045> A_IWL<1044> A_IWL<1043> A_IWL<1042> A_IWL<1041> A_IWL<1040> A_IWL<1039> A_IWL<1038> A_IWL<1037> A_IWL<1036> A_IWL<1035> A_IWL<1034> A_IWL<1033> A_IWL<1032> A_IWL<1031> A_IWL<1030> A_IWL<1029> A_IWL<1028> A_IWL<1027> A_IWL<1026> A_IWL<1025> A_IWL<1024> A_IWL<1279> A_IWL<1278> A_IWL<1277> A_IWL<1276> A_IWL<1275> A_IWL<1274> A_IWL<1273> A_IWL<1272> A_IWL<1271> A_IWL<1270> A_IWL<1269> A_IWL<1268> A_IWL<1267> A_IWL<1266> A_IWL<1265> A_IWL<1264> A_IWL<1263> A_IWL<1262> A_IWL<1261> A_IWL<1260> A_IWL<1259> A_IWL<1258> A_IWL<1257> A_IWL<1256> A_IWL<1255> A_IWL<1254> A_IWL<1253> A_IWL<1252> A_IWL<1251> A_IWL<1250> A_IWL<1249> A_IWL<1248> A_IWL<1247> A_IWL<1246> A_IWL<1245> A_IWL<1244> A_IWL<1243> A_IWL<1242> A_IWL<1241> A_IWL<1240> A_IWL<1239> A_IWL<1238> A_IWL<1237> A_IWL<1236> A_IWL<1235> A_IWL<1234> A_IWL<1233> A_IWL<1232> A_IWL<1231> A_IWL<1230> A_IWL<1229> A_IWL<1228> A_IWL<1227> A_IWL<1226> A_IWL<1225> A_IWL<1224> A_IWL<1223> A_IWL<1222> A_IWL<1221> A_IWL<1220> A_IWL<1219> A_IWL<1218> A_IWL<1217> A_IWL<1216> A_IWL<1215> A_IWL<1214> A_IWL<1213> A_IWL<1212> A_IWL<1211> A_IWL<1210> A_IWL<1209> A_IWL<1208> A_IWL<1207> A_IWL<1206> A_IWL<1205> A_IWL<1204> A_IWL<1203> A_IWL<1202> A_IWL<1201> A_IWL<1200> A_IWL<1199> A_IWL<1198> A_IWL<1197> A_IWL<1196> A_IWL<1195> A_IWL<1194> A_IWL<1193> A_IWL<1192> A_IWL<1191> A_IWL<1190> A_IWL<1189> A_IWL<1188> A_IWL<1187> A_IWL<1186> A_IWL<1185> A_IWL<1184> A_IWL<1183> A_IWL<1182> A_IWL<1181> A_IWL<1180> A_IWL<1179> A_IWL<1178> A_IWL<1177> A_IWL<1176> A_IWL<1175> A_IWL<1174> A_IWL<1173> A_IWL<1172> A_IWL<1171> A_IWL<1170> A_IWL<1169> A_IWL<1168> A_IWL<1167> A_IWL<1166> A_IWL<1165> A_IWL<1164> A_IWL<1163> A_IWL<1162> A_IWL<1161> A_IWL<1160> A_IWL<1159> A_IWL<1158> A_IWL<1157> A_IWL<1156> A_IWL<1155> A_IWL<1154> A_IWL<1153> A_IWL<1152> VDD_CORE VSS / RM_IHPSG13_512x32_c2_1P_COLUMN_pcell_0 +XCOL<8> A_BLC<17> A_BLC<16> A_BLC_TOP<17> A_BLC_TOP<16> A_BLT<17> A_BLT<16> A_BLT_TOP<17> A_BLT_TOP<16> A_IWL<1023> A_IWL<1022> A_IWL<1021> A_IWL<1020> A_IWL<1019> A_IWL<1018> A_IWL<1017> A_IWL<1016> A_IWL<1015> A_IWL<1014> A_IWL<1013> A_IWL<1012> A_IWL<1011> A_IWL<1010> A_IWL<1009> A_IWL<1008> A_IWL<1007> A_IWL<1006> A_IWL<1005> A_IWL<1004> A_IWL<1003> A_IWL<1002> A_IWL<1001> A_IWL<1000> A_IWL<999> A_IWL<998> A_IWL<997> A_IWL<996> A_IWL<995> A_IWL<994> A_IWL<993> A_IWL<992> A_IWL<991> A_IWL<990> A_IWL<989> A_IWL<988> A_IWL<987> A_IWL<986> A_IWL<985> A_IWL<984> A_IWL<983> A_IWL<982> A_IWL<981> A_IWL<980> A_IWL<979> A_IWL<978> A_IWL<977> A_IWL<976> A_IWL<975> A_IWL<974> A_IWL<973> A_IWL<972> A_IWL<971> A_IWL<970> A_IWL<969> A_IWL<968> A_IWL<967> A_IWL<966> A_IWL<965> A_IWL<964> A_IWL<963> A_IWL<962> A_IWL<961> A_IWL<960> A_IWL<959> A_IWL<958> A_IWL<957> A_IWL<956> A_IWL<955> A_IWL<954> A_IWL<953> A_IWL<952> A_IWL<951> A_IWL<950> A_IWL<949> A_IWL<948> A_IWL<947> A_IWL<946> A_IWL<945> A_IWL<944> A_IWL<943> A_IWL<942> A_IWL<941> A_IWL<940> A_IWL<939> A_IWL<938> A_IWL<937> A_IWL<936> A_IWL<935> A_IWL<934> A_IWL<933> A_IWL<932> A_IWL<931> A_IWL<930> A_IWL<929> A_IWL<928> A_IWL<927> A_IWL<926> A_IWL<925> A_IWL<924> A_IWL<923> A_IWL<922> A_IWL<921> A_IWL<920> A_IWL<919> A_IWL<918> A_IWL<917> A_IWL<916> A_IWL<915> A_IWL<914> A_IWL<913> A_IWL<912> A_IWL<911> A_IWL<910> A_IWL<909> A_IWL<908> A_IWL<907> A_IWL<906> A_IWL<905> A_IWL<904> A_IWL<903> A_IWL<902> A_IWL<901> A_IWL<900> A_IWL<899> A_IWL<898> A_IWL<897> A_IWL<896> A_IWL<1151> A_IWL<1150> A_IWL<1149> A_IWL<1148> A_IWL<1147> A_IWL<1146> A_IWL<1145> A_IWL<1144> A_IWL<1143> A_IWL<1142> A_IWL<1141> A_IWL<1140> A_IWL<1139> A_IWL<1138> A_IWL<1137> A_IWL<1136> A_IWL<1135> A_IWL<1134> A_IWL<1133> A_IWL<1132> A_IWL<1131> A_IWL<1130> A_IWL<1129> A_IWL<1128> A_IWL<1127> A_IWL<1126> A_IWL<1125> A_IWL<1124> A_IWL<1123> A_IWL<1122> A_IWL<1121> A_IWL<1120> A_IWL<1119> A_IWL<1118> A_IWL<1117> A_IWL<1116> A_IWL<1115> A_IWL<1114> A_IWL<1113> A_IWL<1112> A_IWL<1111> A_IWL<1110> A_IWL<1109> A_IWL<1108> A_IWL<1107> A_IWL<1106> A_IWL<1105> A_IWL<1104> A_IWL<1103> A_IWL<1102> A_IWL<1101> A_IWL<1100> A_IWL<1099> A_IWL<1098> A_IWL<1097> A_IWL<1096> A_IWL<1095> A_IWL<1094> A_IWL<1093> A_IWL<1092> A_IWL<1091> A_IWL<1090> A_IWL<1089> A_IWL<1088> A_IWL<1087> A_IWL<1086> A_IWL<1085> A_IWL<1084> A_IWL<1083> A_IWL<1082> A_IWL<1081> A_IWL<1080> A_IWL<1079> A_IWL<1078> A_IWL<1077> A_IWL<1076> A_IWL<1075> A_IWL<1074> A_IWL<1073> A_IWL<1072> A_IWL<1071> A_IWL<1070> A_IWL<1069> A_IWL<1068> A_IWL<1067> A_IWL<1066> A_IWL<1065> A_IWL<1064> A_IWL<1063> A_IWL<1062> A_IWL<1061> A_IWL<1060> A_IWL<1059> A_IWL<1058> A_IWL<1057> A_IWL<1056> A_IWL<1055> A_IWL<1054> A_IWL<1053> A_IWL<1052> A_IWL<1051> A_IWL<1050> A_IWL<1049> A_IWL<1048> A_IWL<1047> A_IWL<1046> A_IWL<1045> A_IWL<1044> A_IWL<1043> A_IWL<1042> A_IWL<1041> A_IWL<1040> A_IWL<1039> A_IWL<1038> A_IWL<1037> A_IWL<1036> A_IWL<1035> A_IWL<1034> A_IWL<1033> A_IWL<1032> A_IWL<1031> A_IWL<1030> A_IWL<1029> A_IWL<1028> A_IWL<1027> A_IWL<1026> A_IWL<1025> A_IWL<1024> VDD_CORE VSS / RM_IHPSG13_512x32_c2_1P_COLUMN_pcell_0 +XCOL<7> A_BLC<15> A_BLC<14> A_BLC_TOP<15> A_BLC_TOP<14> A_BLT<15> A_BLT<14> A_BLT_TOP<15> A_BLT_TOP<14> A_IWL<895> A_IWL<894> A_IWL<893> A_IWL<892> A_IWL<891> A_IWL<890> A_IWL<889> A_IWL<888> A_IWL<887> A_IWL<886> A_IWL<885> A_IWL<884> A_IWL<883> A_IWL<882> A_IWL<881> A_IWL<880> A_IWL<879> A_IWL<878> A_IWL<877> A_IWL<876> A_IWL<875> A_IWL<874> A_IWL<873> A_IWL<872> A_IWL<871> A_IWL<870> A_IWL<869> A_IWL<868> A_IWL<867> A_IWL<866> A_IWL<865> A_IWL<864> A_IWL<863> A_IWL<862> A_IWL<861> A_IWL<860> A_IWL<859> A_IWL<858> A_IWL<857> A_IWL<856> A_IWL<855> A_IWL<854> A_IWL<853> A_IWL<852> A_IWL<851> A_IWL<850> A_IWL<849> A_IWL<848> A_IWL<847> A_IWL<846> A_IWL<845> A_IWL<844> A_IWL<843> A_IWL<842> A_IWL<841> A_IWL<840> A_IWL<839> A_IWL<838> A_IWL<837> A_IWL<836> A_IWL<835> A_IWL<834> A_IWL<833> A_IWL<832> A_IWL<831> A_IWL<830> A_IWL<829> A_IWL<828> A_IWL<827> A_IWL<826> A_IWL<825> A_IWL<824> A_IWL<823> A_IWL<822> A_IWL<821> A_IWL<820> A_IWL<819> A_IWL<818> A_IWL<817> A_IWL<816> A_IWL<815> A_IWL<814> A_IWL<813> A_IWL<812> A_IWL<811> A_IWL<810> A_IWL<809> A_IWL<808> A_IWL<807> A_IWL<806> A_IWL<805> A_IWL<804> A_IWL<803> A_IWL<802> A_IWL<801> A_IWL<800> A_IWL<799> A_IWL<798> A_IWL<797> A_IWL<796> A_IWL<795> A_IWL<794> A_IWL<793> A_IWL<792> A_IWL<791> A_IWL<790> A_IWL<789> A_IWL<788> A_IWL<787> A_IWL<786> A_IWL<785> A_IWL<784> A_IWL<783> A_IWL<782> A_IWL<781> A_IWL<780> A_IWL<779> A_IWL<778> A_IWL<777> A_IWL<776> A_IWL<775> A_IWL<774> A_IWL<773> A_IWL<772> A_IWL<771> A_IWL<770> A_IWL<769> A_IWL<768> A_IWL<1023> A_IWL<1022> A_IWL<1021> A_IWL<1020> A_IWL<1019> A_IWL<1018> A_IWL<1017> A_IWL<1016> A_IWL<1015> A_IWL<1014> A_IWL<1013> A_IWL<1012> A_IWL<1011> A_IWL<1010> A_IWL<1009> A_IWL<1008> A_IWL<1007> A_IWL<1006> A_IWL<1005> A_IWL<1004> A_IWL<1003> A_IWL<1002> A_IWL<1001> A_IWL<1000> A_IWL<999> A_IWL<998> A_IWL<997> A_IWL<996> A_IWL<995> A_IWL<994> A_IWL<993> A_IWL<992> A_IWL<991> A_IWL<990> A_IWL<989> A_IWL<988> A_IWL<987> A_IWL<986> A_IWL<985> A_IWL<984> A_IWL<983> A_IWL<982> A_IWL<981> A_IWL<980> A_IWL<979> A_IWL<978> A_IWL<977> A_IWL<976> A_IWL<975> A_IWL<974> A_IWL<973> A_IWL<972> A_IWL<971> A_IWL<970> A_IWL<969> A_IWL<968> A_IWL<967> A_IWL<966> A_IWL<965> A_IWL<964> A_IWL<963> A_IWL<962> A_IWL<961> A_IWL<960> A_IWL<959> A_IWL<958> A_IWL<957> A_IWL<956> A_IWL<955> A_IWL<954> A_IWL<953> A_IWL<952> A_IWL<951> A_IWL<950> A_IWL<949> A_IWL<948> A_IWL<947> A_IWL<946> A_IWL<945> A_IWL<944> A_IWL<943> A_IWL<942> A_IWL<941> A_IWL<940> A_IWL<939> A_IWL<938> A_IWL<937> A_IWL<936> A_IWL<935> A_IWL<934> A_IWL<933> A_IWL<932> A_IWL<931> A_IWL<930> A_IWL<929> A_IWL<928> A_IWL<927> A_IWL<926> A_IWL<925> A_IWL<924> A_IWL<923> A_IWL<922> A_IWL<921> A_IWL<920> A_IWL<919> A_IWL<918> A_IWL<917> A_IWL<916> A_IWL<915> A_IWL<914> A_IWL<913> A_IWL<912> A_IWL<911> A_IWL<910> A_IWL<909> A_IWL<908> A_IWL<907> A_IWL<906> A_IWL<905> A_IWL<904> A_IWL<903> A_IWL<902> A_IWL<901> A_IWL<900> A_IWL<899> A_IWL<898> A_IWL<897> A_IWL<896> VDD_CORE VSS / RM_IHPSG13_512x32_c2_1P_COLUMN_pcell_0 +XCOL<6> A_BLC<13> A_BLC<12> A_BLC_TOP<13> A_BLC_TOP<12> A_BLT<13> A_BLT<12> A_BLT_TOP<13> A_BLT_TOP<12> A_IWL<767> A_IWL<766> A_IWL<765> A_IWL<764> A_IWL<763> A_IWL<762> A_IWL<761> A_IWL<760> A_IWL<759> A_IWL<758> A_IWL<757> A_IWL<756> A_IWL<755> A_IWL<754> A_IWL<753> A_IWL<752> A_IWL<751> A_IWL<750> A_IWL<749> A_IWL<748> A_IWL<747> A_IWL<746> A_IWL<745> A_IWL<744> A_IWL<743> A_IWL<742> A_IWL<741> A_IWL<740> A_IWL<739> A_IWL<738> A_IWL<737> A_IWL<736> A_IWL<735> A_IWL<734> A_IWL<733> A_IWL<732> A_IWL<731> A_IWL<730> A_IWL<729> A_IWL<728> A_IWL<727> A_IWL<726> A_IWL<725> A_IWL<724> A_IWL<723> A_IWL<722> A_IWL<721> A_IWL<720> A_IWL<719> A_IWL<718> A_IWL<717> A_IWL<716> A_IWL<715> A_IWL<714> A_IWL<713> A_IWL<712> A_IWL<711> A_IWL<710> A_IWL<709> A_IWL<708> A_IWL<707> A_IWL<706> A_IWL<705> A_IWL<704> A_IWL<703> A_IWL<702> A_IWL<701> A_IWL<700> A_IWL<699> A_IWL<698> A_IWL<697> A_IWL<696> A_IWL<695> A_IWL<694> A_IWL<693> A_IWL<692> A_IWL<691> A_IWL<690> A_IWL<689> A_IWL<688> A_IWL<687> A_IWL<686> A_IWL<685> A_IWL<684> A_IWL<683> A_IWL<682> A_IWL<681> A_IWL<680> A_IWL<679> A_IWL<678> A_IWL<677> A_IWL<676> A_IWL<675> A_IWL<674> A_IWL<673> A_IWL<672> A_IWL<671> A_IWL<670> A_IWL<669> A_IWL<668> A_IWL<667> A_IWL<666> A_IWL<665> A_IWL<664> A_IWL<663> A_IWL<662> A_IWL<661> A_IWL<660> A_IWL<659> A_IWL<658> A_IWL<657> A_IWL<656> A_IWL<655> A_IWL<654> A_IWL<653> A_IWL<652> A_IWL<651> A_IWL<650> A_IWL<649> A_IWL<648> A_IWL<647> A_IWL<646> A_IWL<645> A_IWL<644> A_IWL<643> A_IWL<642> A_IWL<641> A_IWL<640> A_IWL<895> A_IWL<894> A_IWL<893> A_IWL<892> A_IWL<891> A_IWL<890> A_IWL<889> A_IWL<888> A_IWL<887> A_IWL<886> A_IWL<885> A_IWL<884> A_IWL<883> A_IWL<882> A_IWL<881> A_IWL<880> A_IWL<879> A_IWL<878> A_IWL<877> A_IWL<876> A_IWL<875> A_IWL<874> A_IWL<873> A_IWL<872> A_IWL<871> A_IWL<870> A_IWL<869> A_IWL<868> A_IWL<867> A_IWL<866> A_IWL<865> A_IWL<864> A_IWL<863> A_IWL<862> A_IWL<861> A_IWL<860> A_IWL<859> A_IWL<858> A_IWL<857> A_IWL<856> A_IWL<855> A_IWL<854> A_IWL<853> A_IWL<852> A_IWL<851> A_IWL<850> A_IWL<849> A_IWL<848> A_IWL<847> A_IWL<846> A_IWL<845> A_IWL<844> A_IWL<843> A_IWL<842> A_IWL<841> A_IWL<840> A_IWL<839> A_IWL<838> A_IWL<837> A_IWL<836> A_IWL<835> A_IWL<834> A_IWL<833> A_IWL<832> A_IWL<831> A_IWL<830> A_IWL<829> A_IWL<828> A_IWL<827> A_IWL<826> A_IWL<825> A_IWL<824> A_IWL<823> A_IWL<822> A_IWL<821> A_IWL<820> A_IWL<819> A_IWL<818> A_IWL<817> A_IWL<816> A_IWL<815> A_IWL<814> A_IWL<813> A_IWL<812> A_IWL<811> A_IWL<810> A_IWL<809> A_IWL<808> A_IWL<807> A_IWL<806> A_IWL<805> A_IWL<804> A_IWL<803> A_IWL<802> A_IWL<801> A_IWL<800> A_IWL<799> A_IWL<798> A_IWL<797> A_IWL<796> A_IWL<795> A_IWL<794> A_IWL<793> A_IWL<792> A_IWL<791> A_IWL<790> A_IWL<789> A_IWL<788> A_IWL<787> A_IWL<786> A_IWL<785> A_IWL<784> A_IWL<783> A_IWL<782> A_IWL<781> A_IWL<780> A_IWL<779> A_IWL<778> A_IWL<777> A_IWL<776> A_IWL<775> A_IWL<774> A_IWL<773> A_IWL<772> A_IWL<771> A_IWL<770> A_IWL<769> A_IWL<768> VDD_CORE VSS / RM_IHPSG13_512x32_c2_1P_COLUMN_pcell_0 +XCOL<5> A_BLC<11> A_BLC<10> A_BLC_TOP<11> A_BLC_TOP<10> A_BLT<11> A_BLT<10> A_BLT_TOP<11> A_BLT_TOP<10> A_IWL<639> A_IWL<638> A_IWL<637> A_IWL<636> A_IWL<635> A_IWL<634> A_IWL<633> A_IWL<632> A_IWL<631> A_IWL<630> A_IWL<629> A_IWL<628> A_IWL<627> A_IWL<626> A_IWL<625> A_IWL<624> A_IWL<623> A_IWL<622> A_IWL<621> A_IWL<620> A_IWL<619> A_IWL<618> A_IWL<617> A_IWL<616> A_IWL<615> A_IWL<614> A_IWL<613> A_IWL<612> A_IWL<611> A_IWL<610> A_IWL<609> A_IWL<608> A_IWL<607> A_IWL<606> A_IWL<605> A_IWL<604> A_IWL<603> A_IWL<602> A_IWL<601> A_IWL<600> A_IWL<599> A_IWL<598> A_IWL<597> A_IWL<596> A_IWL<595> A_IWL<594> A_IWL<593> A_IWL<592> A_IWL<591> A_IWL<590> A_IWL<589> A_IWL<588> A_IWL<587> A_IWL<586> A_IWL<585> A_IWL<584> A_IWL<583> A_IWL<582> A_IWL<581> A_IWL<580> A_IWL<579> A_IWL<578> A_IWL<577> A_IWL<576> A_IWL<575> A_IWL<574> A_IWL<573> A_IWL<572> A_IWL<571> A_IWL<570> A_IWL<569> A_IWL<568> A_IWL<567> A_IWL<566> A_IWL<565> A_IWL<564> A_IWL<563> A_IWL<562> A_IWL<561> A_IWL<560> A_IWL<559> A_IWL<558> A_IWL<557> A_IWL<556> A_IWL<555> A_IWL<554> A_IWL<553> A_IWL<552> A_IWL<551> A_IWL<550> A_IWL<549> A_IWL<548> A_IWL<547> A_IWL<546> A_IWL<545> A_IWL<544> A_IWL<543> A_IWL<542> A_IWL<541> A_IWL<540> A_IWL<539> A_IWL<538> A_IWL<537> A_IWL<536> A_IWL<535> A_IWL<534> A_IWL<533> A_IWL<532> A_IWL<531> A_IWL<530> A_IWL<529> A_IWL<528> A_IWL<527> A_IWL<526> A_IWL<525> A_IWL<524> A_IWL<523> A_IWL<522> A_IWL<521> A_IWL<520> A_IWL<519> A_IWL<518> A_IWL<517> A_IWL<516> A_IWL<515> A_IWL<514> A_IWL<513> A_IWL<512> A_IWL<767> A_IWL<766> A_IWL<765> A_IWL<764> A_IWL<763> A_IWL<762> A_IWL<761> A_IWL<760> A_IWL<759> A_IWL<758> A_IWL<757> A_IWL<756> A_IWL<755> A_IWL<754> A_IWL<753> A_IWL<752> A_IWL<751> A_IWL<750> A_IWL<749> A_IWL<748> A_IWL<747> A_IWL<746> A_IWL<745> A_IWL<744> A_IWL<743> A_IWL<742> A_IWL<741> A_IWL<740> A_IWL<739> A_IWL<738> A_IWL<737> A_IWL<736> A_IWL<735> A_IWL<734> A_IWL<733> A_IWL<732> A_IWL<731> A_IWL<730> A_IWL<729> A_IWL<728> A_IWL<727> A_IWL<726> A_IWL<725> A_IWL<724> A_IWL<723> A_IWL<722> A_IWL<721> A_IWL<720> A_IWL<719> A_IWL<718> A_IWL<717> A_IWL<716> A_IWL<715> A_IWL<714> A_IWL<713> A_IWL<712> A_IWL<711> A_IWL<710> A_IWL<709> A_IWL<708> A_IWL<707> A_IWL<706> A_IWL<705> A_IWL<704> A_IWL<703> A_IWL<702> A_IWL<701> A_IWL<700> A_IWL<699> A_IWL<698> A_IWL<697> A_IWL<696> A_IWL<695> A_IWL<694> A_IWL<693> A_IWL<692> A_IWL<691> A_IWL<690> A_IWL<689> A_IWL<688> A_IWL<687> A_IWL<686> A_IWL<685> A_IWL<684> A_IWL<683> A_IWL<682> A_IWL<681> A_IWL<680> A_IWL<679> A_IWL<678> A_IWL<677> A_IWL<676> A_IWL<675> A_IWL<674> A_IWL<673> A_IWL<672> A_IWL<671> A_IWL<670> A_IWL<669> A_IWL<668> A_IWL<667> A_IWL<666> A_IWL<665> A_IWL<664> A_IWL<663> A_IWL<662> A_IWL<661> A_IWL<660> A_IWL<659> A_IWL<658> A_IWL<657> A_IWL<656> A_IWL<655> A_IWL<654> A_IWL<653> A_IWL<652> A_IWL<651> A_IWL<650> A_IWL<649> A_IWL<648> A_IWL<647> A_IWL<646> A_IWL<645> A_IWL<644> A_IWL<643> A_IWL<642> A_IWL<641> A_IWL<640> VDD_CORE VSS / RM_IHPSG13_512x32_c2_1P_COLUMN_pcell_0 +XCOL<4> A_BLC<9> A_BLC<8> A_BLC_TOP<9> A_BLC_TOP<8> A_BLT<9> A_BLT<8> A_BLT_TOP<9> A_BLT_TOP<8> A_IWL<511> A_IWL<510> A_IWL<509> A_IWL<508> A_IWL<507> A_IWL<506> A_IWL<505> A_IWL<504> A_IWL<503> A_IWL<502> A_IWL<501> A_IWL<500> A_IWL<499> A_IWL<498> A_IWL<497> A_IWL<496> A_IWL<495> A_IWL<494> A_IWL<493> A_IWL<492> A_IWL<491> A_IWL<490> A_IWL<489> A_IWL<488> A_IWL<487> A_IWL<486> A_IWL<485> A_IWL<484> A_IWL<483> A_IWL<482> A_IWL<481> A_IWL<480> A_IWL<479> A_IWL<478> A_IWL<477> A_IWL<476> A_IWL<475> A_IWL<474> A_IWL<473> A_IWL<472> A_IWL<471> A_IWL<470> A_IWL<469> A_IWL<468> A_IWL<467> A_IWL<466> A_IWL<465> A_IWL<464> A_IWL<463> A_IWL<462> A_IWL<461> A_IWL<460> A_IWL<459> A_IWL<458> A_IWL<457> A_IWL<456> A_IWL<455> A_IWL<454> A_IWL<453> A_IWL<452> A_IWL<451> A_IWL<450> A_IWL<449> A_IWL<448> A_IWL<447> A_IWL<446> A_IWL<445> A_IWL<444> A_IWL<443> A_IWL<442> A_IWL<441> A_IWL<440> A_IWL<439> A_IWL<438> A_IWL<437> A_IWL<436> A_IWL<435> A_IWL<434> A_IWL<433> A_IWL<432> A_IWL<431> A_IWL<430> A_IWL<429> A_IWL<428> A_IWL<427> A_IWL<426> A_IWL<425> A_IWL<424> A_IWL<423> A_IWL<422> A_IWL<421> A_IWL<420> A_IWL<419> A_IWL<418> A_IWL<417> A_IWL<416> A_IWL<415> A_IWL<414> A_IWL<413> A_IWL<412> A_IWL<411> A_IWL<410> A_IWL<409> A_IWL<408> A_IWL<407> A_IWL<406> A_IWL<405> A_IWL<404> A_IWL<403> A_IWL<402> A_IWL<401> A_IWL<400> A_IWL<399> A_IWL<398> A_IWL<397> A_IWL<396> A_IWL<395> A_IWL<394> A_IWL<393> A_IWL<392> A_IWL<391> A_IWL<390> A_IWL<389> A_IWL<388> A_IWL<387> A_IWL<386> A_IWL<385> A_IWL<384> A_IWL<639> A_IWL<638> A_IWL<637> A_IWL<636> A_IWL<635> A_IWL<634> A_IWL<633> A_IWL<632> A_IWL<631> A_IWL<630> A_IWL<629> A_IWL<628> A_IWL<627> A_IWL<626> A_IWL<625> A_IWL<624> A_IWL<623> A_IWL<622> A_IWL<621> A_IWL<620> A_IWL<619> A_IWL<618> A_IWL<617> A_IWL<616> A_IWL<615> A_IWL<614> A_IWL<613> A_IWL<612> A_IWL<611> A_IWL<610> A_IWL<609> A_IWL<608> A_IWL<607> A_IWL<606> A_IWL<605> A_IWL<604> A_IWL<603> A_IWL<602> A_IWL<601> A_IWL<600> A_IWL<599> A_IWL<598> A_IWL<597> A_IWL<596> A_IWL<595> A_IWL<594> A_IWL<593> A_IWL<592> A_IWL<591> A_IWL<590> A_IWL<589> A_IWL<588> A_IWL<587> A_IWL<586> A_IWL<585> A_IWL<584> A_IWL<583> A_IWL<582> A_IWL<581> A_IWL<580> A_IWL<579> A_IWL<578> A_IWL<577> A_IWL<576> A_IWL<575> A_IWL<574> A_IWL<573> A_IWL<572> A_IWL<571> A_IWL<570> A_IWL<569> A_IWL<568> A_IWL<567> A_IWL<566> A_IWL<565> A_IWL<564> A_IWL<563> A_IWL<562> A_IWL<561> A_IWL<560> A_IWL<559> A_IWL<558> A_IWL<557> A_IWL<556> A_IWL<555> A_IWL<554> A_IWL<553> A_IWL<552> A_IWL<551> A_IWL<550> A_IWL<549> A_IWL<548> A_IWL<547> A_IWL<546> A_IWL<545> A_IWL<544> A_IWL<543> A_IWL<542> A_IWL<541> A_IWL<540> A_IWL<539> A_IWL<538> A_IWL<537> A_IWL<536> A_IWL<535> A_IWL<534> A_IWL<533> A_IWL<532> A_IWL<531> A_IWL<530> A_IWL<529> A_IWL<528> A_IWL<527> A_IWL<526> A_IWL<525> A_IWL<524> A_IWL<523> A_IWL<522> A_IWL<521> A_IWL<520> A_IWL<519> A_IWL<518> A_IWL<517> A_IWL<516> A_IWL<515> A_IWL<514> A_IWL<513> A_IWL<512> VDD_CORE VSS / RM_IHPSG13_512x32_c2_1P_COLUMN_pcell_0 +XCOL<3> A_BLC<7> A_BLC<6> A_BLC_TOP<7> A_BLC_TOP<6> A_BLT<7> A_BLT<6> A_BLT_TOP<7> A_BLT_TOP<6> A_IWL<383> A_IWL<382> A_IWL<381> A_IWL<380> A_IWL<379> A_IWL<378> A_IWL<377> A_IWL<376> A_IWL<375> A_IWL<374> A_IWL<373> A_IWL<372> A_IWL<371> A_IWL<370> A_IWL<369> A_IWL<368> A_IWL<367> A_IWL<366> A_IWL<365> A_IWL<364> A_IWL<363> A_IWL<362> A_IWL<361> A_IWL<360> A_IWL<359> A_IWL<358> A_IWL<357> A_IWL<356> A_IWL<355> A_IWL<354> A_IWL<353> A_IWL<352> A_IWL<351> A_IWL<350> A_IWL<349> A_IWL<348> A_IWL<347> A_IWL<346> A_IWL<345> A_IWL<344> A_IWL<343> A_IWL<342> A_IWL<341> A_IWL<340> A_IWL<339> A_IWL<338> A_IWL<337> A_IWL<336> A_IWL<335> A_IWL<334> A_IWL<333> A_IWL<332> A_IWL<331> A_IWL<330> A_IWL<329> A_IWL<328> A_IWL<327> A_IWL<326> A_IWL<325> A_IWL<324> A_IWL<323> A_IWL<322> A_IWL<321> A_IWL<320> A_IWL<319> A_IWL<318> A_IWL<317> A_IWL<316> A_IWL<315> A_IWL<314> A_IWL<313> A_IWL<312> A_IWL<311> A_IWL<310> A_IWL<309> A_IWL<308> A_IWL<307> A_IWL<306> A_IWL<305> A_IWL<304> A_IWL<303> A_IWL<302> A_IWL<301> A_IWL<300> A_IWL<299> A_IWL<298> A_IWL<297> A_IWL<296> A_IWL<295> A_IWL<294> A_IWL<293> A_IWL<292> A_IWL<291> A_IWL<290> A_IWL<289> A_IWL<288> A_IWL<287> A_IWL<286> A_IWL<285> A_IWL<284> A_IWL<283> A_IWL<282> A_IWL<281> A_IWL<280> A_IWL<279> A_IWL<278> A_IWL<277> A_IWL<276> A_IWL<275> A_IWL<274> A_IWL<273> A_IWL<272> A_IWL<271> A_IWL<270> A_IWL<269> A_IWL<268> A_IWL<267> A_IWL<266> A_IWL<265> A_IWL<264> A_IWL<263> A_IWL<262> A_IWL<261> A_IWL<260> A_IWL<259> A_IWL<258> A_IWL<257> A_IWL<256> A_IWL<511> A_IWL<510> A_IWL<509> A_IWL<508> A_IWL<507> A_IWL<506> A_IWL<505> A_IWL<504> A_IWL<503> A_IWL<502> A_IWL<501> A_IWL<500> A_IWL<499> A_IWL<498> A_IWL<497> A_IWL<496> A_IWL<495> A_IWL<494> A_IWL<493> A_IWL<492> A_IWL<491> A_IWL<490> A_IWL<489> A_IWL<488> A_IWL<487> A_IWL<486> A_IWL<485> A_IWL<484> A_IWL<483> A_IWL<482> A_IWL<481> A_IWL<480> A_IWL<479> A_IWL<478> A_IWL<477> A_IWL<476> A_IWL<475> A_IWL<474> A_IWL<473> A_IWL<472> A_IWL<471> A_IWL<470> A_IWL<469> A_IWL<468> A_IWL<467> A_IWL<466> A_IWL<465> A_IWL<464> A_IWL<463> A_IWL<462> A_IWL<461> A_IWL<460> A_IWL<459> A_IWL<458> A_IWL<457> A_IWL<456> A_IWL<455> A_IWL<454> A_IWL<453> A_IWL<452> A_IWL<451> A_IWL<450> A_IWL<449> A_IWL<448> A_IWL<447> A_IWL<446> A_IWL<445> A_IWL<444> A_IWL<443> A_IWL<442> A_IWL<441> A_IWL<440> A_IWL<439> A_IWL<438> A_IWL<437> A_IWL<436> A_IWL<435> A_IWL<434> A_IWL<433> A_IWL<432> A_IWL<431> A_IWL<430> A_IWL<429> A_IWL<428> A_IWL<427> A_IWL<426> A_IWL<425> A_IWL<424> A_IWL<423> A_IWL<422> A_IWL<421> A_IWL<420> A_IWL<419> A_IWL<418> A_IWL<417> A_IWL<416> A_IWL<415> A_IWL<414> A_IWL<413> A_IWL<412> A_IWL<411> A_IWL<410> A_IWL<409> A_IWL<408> A_IWL<407> A_IWL<406> A_IWL<405> A_IWL<404> A_IWL<403> A_IWL<402> A_IWL<401> A_IWL<400> A_IWL<399> A_IWL<398> A_IWL<397> A_IWL<396> A_IWL<395> A_IWL<394> A_IWL<393> A_IWL<392> A_IWL<391> A_IWL<390> A_IWL<389> A_IWL<388> A_IWL<387> A_IWL<386> A_IWL<385> A_IWL<384> VDD_CORE VSS / RM_IHPSG13_512x32_c2_1P_COLUMN_pcell_0 +XCOL<2> A_BLC<5> A_BLC<4> A_BLC_TOP<5> A_BLC_TOP<4> A_BLT<5> A_BLT<4> A_BLT_TOP<5> A_BLT_TOP<4> A_IWL<255> A_IWL<254> A_IWL<253> A_IWL<252> A_IWL<251> A_IWL<250> A_IWL<249> A_IWL<248> A_IWL<247> A_IWL<246> A_IWL<245> A_IWL<244> A_IWL<243> A_IWL<242> A_IWL<241> A_IWL<240> A_IWL<239> A_IWL<238> A_IWL<237> A_IWL<236> A_IWL<235> A_IWL<234> A_IWL<233> A_IWL<232> A_IWL<231> A_IWL<230> A_IWL<229> A_IWL<228> A_IWL<227> A_IWL<226> A_IWL<225> A_IWL<224> A_IWL<223> A_IWL<222> A_IWL<221> A_IWL<220> A_IWL<219> A_IWL<218> A_IWL<217> A_IWL<216> A_IWL<215> A_IWL<214> A_IWL<213> A_IWL<212> A_IWL<211> A_IWL<210> A_IWL<209> A_IWL<208> A_IWL<207> A_IWL<206> A_IWL<205> A_IWL<204> A_IWL<203> A_IWL<202> A_IWL<201> A_IWL<200> A_IWL<199> A_IWL<198> A_IWL<197> A_IWL<196> A_IWL<195> A_IWL<194> A_IWL<193> A_IWL<192> A_IWL<191> A_IWL<190> A_IWL<189> A_IWL<188> A_IWL<187> A_IWL<186> A_IWL<185> A_IWL<184> A_IWL<183> A_IWL<182> A_IWL<181> A_IWL<180> A_IWL<179> A_IWL<178> A_IWL<177> A_IWL<176> A_IWL<175> A_IWL<174> A_IWL<173> A_IWL<172> A_IWL<171> A_IWL<170> A_IWL<169> A_IWL<168> A_IWL<167> A_IWL<166> A_IWL<165> A_IWL<164> A_IWL<163> A_IWL<162> A_IWL<161> A_IWL<160> A_IWL<159> A_IWL<158> A_IWL<157> A_IWL<156> A_IWL<155> A_IWL<154> A_IWL<153> A_IWL<152> A_IWL<151> A_IWL<150> A_IWL<149> A_IWL<148> A_IWL<147> A_IWL<146> A_IWL<145> A_IWL<144> A_IWL<143> A_IWL<142> A_IWL<141> A_IWL<140> A_IWL<139> A_IWL<138> A_IWL<137> A_IWL<136> A_IWL<135> A_IWL<134> A_IWL<133> A_IWL<132> A_IWL<131> A_IWL<130> A_IWL<129> A_IWL<128> A_IWL<383> A_IWL<382> A_IWL<381> A_IWL<380> A_IWL<379> A_IWL<378> A_IWL<377> A_IWL<376> A_IWL<375> A_IWL<374> A_IWL<373> A_IWL<372> A_IWL<371> A_IWL<370> A_IWL<369> A_IWL<368> A_IWL<367> A_IWL<366> A_IWL<365> A_IWL<364> A_IWL<363> A_IWL<362> A_IWL<361> A_IWL<360> A_IWL<359> A_IWL<358> A_IWL<357> A_IWL<356> A_IWL<355> A_IWL<354> A_IWL<353> A_IWL<352> A_IWL<351> A_IWL<350> A_IWL<349> A_IWL<348> A_IWL<347> A_IWL<346> A_IWL<345> A_IWL<344> A_IWL<343> A_IWL<342> A_IWL<341> A_IWL<340> A_IWL<339> A_IWL<338> A_IWL<337> A_IWL<336> A_IWL<335> A_IWL<334> A_IWL<333> A_IWL<332> A_IWL<331> A_IWL<330> A_IWL<329> A_IWL<328> A_IWL<327> A_IWL<326> A_IWL<325> A_IWL<324> A_IWL<323> A_IWL<322> A_IWL<321> A_IWL<320> A_IWL<319> A_IWL<318> A_IWL<317> A_IWL<316> A_IWL<315> A_IWL<314> A_IWL<313> A_IWL<312> A_IWL<311> A_IWL<310> A_IWL<309> A_IWL<308> A_IWL<307> A_IWL<306> A_IWL<305> A_IWL<304> A_IWL<303> A_IWL<302> A_IWL<301> A_IWL<300> A_IWL<299> A_IWL<298> A_IWL<297> A_IWL<296> A_IWL<295> A_IWL<294> A_IWL<293> A_IWL<292> A_IWL<291> A_IWL<290> A_IWL<289> A_IWL<288> A_IWL<287> A_IWL<286> A_IWL<285> A_IWL<284> A_IWL<283> A_IWL<282> A_IWL<281> A_IWL<280> A_IWL<279> A_IWL<278> A_IWL<277> A_IWL<276> A_IWL<275> A_IWL<274> A_IWL<273> A_IWL<272> A_IWL<271> A_IWL<270> A_IWL<269> A_IWL<268> A_IWL<267> A_IWL<266> A_IWL<265> A_IWL<264> A_IWL<263> A_IWL<262> A_IWL<261> A_IWL<260> A_IWL<259> A_IWL<258> A_IWL<257> A_IWL<256> VDD_CORE VSS / RM_IHPSG13_512x32_c2_1P_COLUMN_pcell_0 +XCOL<1> A_BLC<3> A_BLC<2> A_BLC_TOP<3> A_BLC_TOP<2> A_BLT<3> A_BLT<2> A_BLT_TOP<3> A_BLT_TOP<2> A_IWL<127> A_IWL<126> A_IWL<125> A_IWL<124> A_IWL<123> A_IWL<122> A_IWL<121> A_IWL<120> A_IWL<119> A_IWL<118> A_IWL<117> A_IWL<116> A_IWL<115> A_IWL<114> A_IWL<113> A_IWL<112> A_IWL<111> A_IWL<110> A_IWL<109> A_IWL<108> A_IWL<107> A_IWL<106> A_IWL<105> A_IWL<104> A_IWL<103> A_IWL<102> A_IWL<101> A_IWL<100> A_IWL<99> A_IWL<98> A_IWL<97> A_IWL<96> A_IWL<95> A_IWL<94> A_IWL<93> A_IWL<92> A_IWL<91> A_IWL<90> A_IWL<89> A_IWL<88> A_IWL<87> A_IWL<86> A_IWL<85> A_IWL<84> A_IWL<83> A_IWL<82> A_IWL<81> A_IWL<80> A_IWL<79> A_IWL<78> A_IWL<77> A_IWL<76> A_IWL<75> A_IWL<74> A_IWL<73> A_IWL<72> A_IWL<71> A_IWL<70> A_IWL<69> A_IWL<68> A_IWL<67> A_IWL<66> A_IWL<65> A_IWL<64> A_IWL<63> A_IWL<62> A_IWL<61> A_IWL<60> A_IWL<59> A_IWL<58> A_IWL<57> A_IWL<56> A_IWL<55> A_IWL<54> A_IWL<53> A_IWL<52> A_IWL<51> A_IWL<50> A_IWL<49> A_IWL<48> A_IWL<47> A_IWL<46> A_IWL<45> A_IWL<44> A_IWL<43> A_IWL<42> A_IWL<41> A_IWL<40> A_IWL<39> A_IWL<38> A_IWL<37> A_IWL<36> A_IWL<35> A_IWL<34> A_IWL<33> A_IWL<32> A_IWL<31> A_IWL<30> A_IWL<29> A_IWL<28> A_IWL<27> A_IWL<26> A_IWL<25> A_IWL<24> A_IWL<23> A_IWL<22> A_IWL<21> A_IWL<20> A_IWL<19> A_IWL<18> A_IWL<17> A_IWL<16> A_IWL<15> A_IWL<14> A_IWL<13> A_IWL<12> A_IWL<11> A_IWL<10> A_IWL<9> A_IWL<8> A_IWL<7> A_IWL<6> A_IWL<5> A_IWL<4> A_IWL<3> A_IWL<2> A_IWL<1> A_IWL<0> A_IWL<255> A_IWL<254> A_IWL<253> A_IWL<252> A_IWL<251> A_IWL<250> A_IWL<249> A_IWL<248> A_IWL<247> A_IWL<246> A_IWL<245> A_IWL<244> A_IWL<243> A_IWL<242> A_IWL<241> A_IWL<240> A_IWL<239> A_IWL<238> A_IWL<237> A_IWL<236> A_IWL<235> A_IWL<234> A_IWL<233> A_IWL<232> A_IWL<231> A_IWL<230> A_IWL<229> A_IWL<228> A_IWL<227> A_IWL<226> A_IWL<225> A_IWL<224> A_IWL<223> A_IWL<222> A_IWL<221> A_IWL<220> A_IWL<219> A_IWL<218> A_IWL<217> A_IWL<216> A_IWL<215> A_IWL<214> A_IWL<213> A_IWL<212> A_IWL<211> A_IWL<210> A_IWL<209> A_IWL<208> A_IWL<207> A_IWL<206> A_IWL<205> A_IWL<204> A_IWL<203> A_IWL<202> A_IWL<201> A_IWL<200> A_IWL<199> A_IWL<198> A_IWL<197> A_IWL<196> A_IWL<195> A_IWL<194> A_IWL<193> A_IWL<192> A_IWL<191> A_IWL<190> A_IWL<189> A_IWL<188> A_IWL<187> A_IWL<186> A_IWL<185> A_IWL<184> A_IWL<183> A_IWL<182> A_IWL<181> A_IWL<180> A_IWL<179> A_IWL<178> A_IWL<177> A_IWL<176> A_IWL<175> A_IWL<174> A_IWL<173> A_IWL<172> A_IWL<171> A_IWL<170> A_IWL<169> A_IWL<168> A_IWL<167> A_IWL<166> A_IWL<165> A_IWL<164> A_IWL<163> A_IWL<162> A_IWL<161> A_IWL<160> A_IWL<159> A_IWL<158> A_IWL<157> A_IWL<156> A_IWL<155> A_IWL<154> A_IWL<153> A_IWL<152> A_IWL<151> A_IWL<150> A_IWL<149> A_IWL<148> A_IWL<147> A_IWL<146> A_IWL<145> A_IWL<144> A_IWL<143> A_IWL<142> A_IWL<141> A_IWL<140> A_IWL<139> A_IWL<138> A_IWL<137> A_IWL<136> A_IWL<135> A_IWL<134> A_IWL<133> A_IWL<132> A_IWL<131> A_IWL<130> A_IWL<129> A_IWL<128> VDD_CORE VSS / RM_IHPSG13_512x32_c2_1P_COLUMN_pcell_0 +XCOL<0> A_BLC<1> A_BLC<0> A_BLC_TOP<1> A_BLC_TOP<0> A_BLT<1> A_BLT<0> A_BLT_TOP<1> A_BLT_TOP<0> A_WL<127> A_WL<126> A_WL<125> A_WL<124> A_WL<123> A_WL<122> A_WL<121> A_WL<120> A_WL<119> A_WL<118> A_WL<117> A_WL<116> A_WL<115> A_WL<114> A_WL<113> A_WL<112> A_WL<111> A_WL<110> A_WL<109> A_WL<108> A_WL<107> A_WL<106> A_WL<105> A_WL<104> A_WL<103> A_WL<102> A_WL<101> A_WL<100> A_WL<99> A_WL<98> A_WL<97> A_WL<96> A_WL<95> A_WL<94> A_WL<93> A_WL<92> A_WL<91> A_WL<90> A_WL<89> A_WL<88> A_WL<87> A_WL<86> A_WL<85> A_WL<84> A_WL<83> A_WL<82> A_WL<81> A_WL<80> A_WL<79> A_WL<78> A_WL<77> A_WL<76> A_WL<75> A_WL<74> A_WL<73> A_WL<72> A_WL<71> A_WL<70> A_WL<69> A_WL<68> A_WL<67> A_WL<66> A_WL<65> A_WL<64> A_WL<63> A_WL<62> A_WL<61> A_WL<60> A_WL<59> A_WL<58> A_WL<57> A_WL<56> A_WL<55> A_WL<54> A_WL<53> A_WL<52> A_WL<51> A_WL<50> A_WL<49> A_WL<48> A_WL<47> A_WL<46> A_WL<45> A_WL<44> A_WL<43> A_WL<42> A_WL<41> A_WL<40> A_WL<39> A_WL<38> A_WL<37> A_WL<36> A_WL<35> A_WL<34> A_WL<33> A_WL<32> A_WL<31> A_WL<30> A_WL<29> A_WL<28> A_WL<27> A_WL<26> A_WL<25> A_WL<24> A_WL<23> A_WL<22> A_WL<21> A_WL<20> A_WL<19> A_WL<18> A_WL<17> A_WL<16> A_WL<15> A_WL<14> A_WL<13> A_WL<12> A_WL<11> A_WL<10> A_WL<9> A_WL<8> A_WL<7> A_WL<6> A_WL<5> A_WL<4> A_WL<3> A_WL<2> A_WL<1> A_WL<0> A_IWL<127> A_IWL<126> A_IWL<125> A_IWL<124> A_IWL<123> A_IWL<122> A_IWL<121> A_IWL<120> A_IWL<119> A_IWL<118> A_IWL<117> A_IWL<116> A_IWL<115> A_IWL<114> A_IWL<113> A_IWL<112> A_IWL<111> A_IWL<110> A_IWL<109> A_IWL<108> A_IWL<107> A_IWL<106> A_IWL<105> A_IWL<104> A_IWL<103> A_IWL<102> A_IWL<101> A_IWL<100> A_IWL<99> A_IWL<98> A_IWL<97> A_IWL<96> A_IWL<95> A_IWL<94> A_IWL<93> A_IWL<92> A_IWL<91> A_IWL<90> A_IWL<89> A_IWL<88> A_IWL<87> A_IWL<86> A_IWL<85> A_IWL<84> A_IWL<83> A_IWL<82> A_IWL<81> A_IWL<80> A_IWL<79> A_IWL<78> A_IWL<77> A_IWL<76> A_IWL<75> A_IWL<74> A_IWL<73> A_IWL<72> A_IWL<71> A_IWL<70> A_IWL<69> A_IWL<68> A_IWL<67> A_IWL<66> A_IWL<65> A_IWL<64> A_IWL<63> A_IWL<62> A_IWL<61> A_IWL<60> A_IWL<59> A_IWL<58> A_IWL<57> A_IWL<56> A_IWL<55> A_IWL<54> A_IWL<53> A_IWL<52> A_IWL<51> A_IWL<50> A_IWL<49> A_IWL<48> A_IWL<47> A_IWL<46> A_IWL<45> A_IWL<44> A_IWL<43> A_IWL<42> A_IWL<41> A_IWL<40> A_IWL<39> A_IWL<38> A_IWL<37> A_IWL<36> A_IWL<35> A_IWL<34> A_IWL<33> A_IWL<32> A_IWL<31> A_IWL<30> A_IWL<29> A_IWL<28> A_IWL<27> A_IWL<26> A_IWL<25> A_IWL<24> A_IWL<23> A_IWL<22> A_IWL<21> A_IWL<20> A_IWL<19> A_IWL<18> A_IWL<17> A_IWL<16> A_IWL<15> A_IWL<14> A_IWL<13> A_IWL<12> A_IWL<11> A_IWL<10> A_IWL<9> A_IWL<8> A_IWL<7> A_IWL<6> A_IWL<5> A_IWL<4> A_IWL<3> A_IWL<2> A_IWL<1> A_IWL<0> VDD_CORE VSS / RM_IHPSG13_512x32_c2_1P_COLUMN_pcell_0 +.ENDS + + + + +.SUBCKT RM_IHPSG13_512x32_c2_1P_DLY_pcell_2 A Z VDD VSS + XIDL<2> D<7> Z VDD VSS / RSC_IHPSG13_CDLYX1 + XIDL<1> D<6> D<7> VDD VSS / RSC_IHPSG13_CDLYX1 + XIDM<6> D<5> D<6> VDD VSS / RSC_IHPSG13_CDLYX1_DUMMY + XIDM<5> D<4> D<5> VDD VSS / RSC_IHPSG13_CDLYX1_DUMMY + XIDM<4> D<3> D<4> VDD VSS / RSC_IHPSG13_CDLYX1_DUMMY + XIDM<3> D<2> D<3> VDD VSS / RSC_IHPSG13_CDLYX1_DUMMY + XIDM<2> D<1> D<2> VDD VSS / RSC_IHPSG13_CDLYX1_DUMMY + XIDM<1> A D<1> VDD VSS / RSC_IHPSG13_CDLYX1_DUMMY +.ENDS + + +.SUBCKT RM_IHPSG13_512x32_c2_1P_DLY_pcell_3 A Z VDD VSS + XIDL<2> D<7> Z VDD VSS / RSC_IHPSG13_CDLYX1 + XIDL<1> D<6> D<7> VDD VSS / RSC_IHPSG13_CDLYX1 + XIDM<6> D<5> D<6> VDD VSS / RSC_IHPSG13_CDLYX1_DUMMY + XIDM<5> D<4> D<5> VDD VSS / RSC_IHPSG13_CDLYX1_DUMMY + XIDM<4> D<3> D<4> VDD VSS / RSC_IHPSG13_CDLYX1_DUMMY + XIDM<3> D<2> D<3> VDD VSS / RSC_IHPSG13_CDLYX1_DUMMY + XIDM<2> D<1> D<2> VDD VSS / RSC_IHPSG13_CDLYX1_DUMMY + XIDM<1> A D<1> VDD VSS / RSC_IHPSG13_CDLYX1_DUMMY +.ENDS + + + +.SUBCKT RM_IHPSG13_1P_512x32_c2_bm_bist A_ADDR<8> A_ADDR<7> A_ADDR<6> A_ADDR<5> A_ADDR<4> A_ADDR<3> A_ADDR<2> A_ADDR<1> A_ADDR<0> A_BIST_ADDR<8> A_BIST_ADDR<7> A_BIST_ADDR<6> A_BIST_ADDR<5> A_BIST_ADDR<4> A_BIST_ADDR<3> A_BIST_ADDR<2> A_BIST_ADDR<1> A_BIST_ADDR<0> A_BIST_BM<31> A_BIST_BM<30> A_BIST_BM<29> A_BIST_BM<28> A_BIST_BM<27> A_BIST_BM<26> A_BIST_BM<25> A_BIST_BM<24> A_BIST_BM<23> A_BIST_BM<22> A_BIST_BM<21> A_BIST_BM<20> A_BIST_BM<19> A_BIST_BM<18> A_BIST_BM<17> A_BIST_BM<16> A_BIST_BM<15> A_BIST_BM<14> A_BIST_BM<13> A_BIST_BM<12> A_BIST_BM<11> A_BIST_BM<10> A_BIST_BM<9> A_BIST_BM<8> A_BIST_BM<7> A_BIST_BM<6> A_BIST_BM<5> A_BIST_BM<4> A_BIST_BM<3> A_BIST_BM<2> A_BIST_BM<1> A_BIST_BM<0> A_BIST_CLK A_BIST_DIN<31> A_BIST_DIN<30> A_BIST_DIN<29> A_BIST_DIN<28> A_BIST_DIN<27> A_BIST_DIN<26> A_BIST_DIN<25> A_BIST_DIN<24> A_BIST_DIN<23> A_BIST_DIN<22> A_BIST_DIN<21> A_BIST_DIN<20> A_BIST_DIN<19> A_BIST_DIN<18> A_BIST_DIN<17> A_BIST_DIN<16> A_BIST_DIN<15> A_BIST_DIN<14> A_BIST_DIN<13> A_BIST_DIN<12> A_BIST_DIN<11> A_BIST_DIN<10> A_BIST_DIN<9> A_BIST_DIN<8> A_BIST_DIN<7> A_BIST_DIN<6> A_BIST_DIN<5> A_BIST_DIN<4> A_BIST_DIN<3> A_BIST_DIN<2> A_BIST_DIN<1> A_BIST_DIN<0> A_BIST_EN A_BIST_MEN A_BIST_REN A_BIST_WEN A_BM<31> A_BM<30> A_BM<29> A_BM<28> A_BM<27> A_BM<26> A_BM<25> A_BM<24> A_BM<23> A_BM<22> A_BM<21> A_BM<20> A_BM<19> A_BM<18> A_BM<17> A_BM<16> A_BM<15> A_BM<14> A_BM<13> A_BM<12> A_BM<11> A_BM<10> A_BM<9> A_BM<8> A_BM<7> A_BM<6> A_BM<5> A_BM<4> A_BM<3> A_BM<2> A_BM<1> A_BM<0> A_CLK A_DIN<31> A_DIN<30> A_DIN<29> A_DIN<28> A_DIN<27> A_DIN<26> A_DIN<25> A_DIN<24> A_DIN<23> A_DIN<22> A_DIN<21> A_DIN<20> A_DIN<19> A_DIN<18> A_DIN<17> A_DIN<16> A_DIN<15> A_DIN<14> A_DIN<13> A_DIN<12> A_DIN<11> A_DIN<10> A_DIN<9> A_DIN<8> A_DIN<7> A_DIN<6> A_DIN<5> A_DIN<4> A_DIN<3> A_DIN<2> A_DIN<1> A_DIN<0> A_DLY A_DOUT<31> A_DOUT<30> A_DOUT<29> A_DOUT<28> A_DOUT<27> A_DOUT<26> A_DOUT<25> A_DOUT<24> A_DOUT<23> A_DOUT<22> A_DOUT<21> A_DOUT<20> A_DOUT<19> A_DOUT<18> A_DOUT<17> A_DOUT<16> A_DOUT<15> A_DOUT<14> A_DOUT<13> A_DOUT<12> A_DOUT<11> A_DOUT<10> A_DOUT<9> A_DOUT<8> A_DOUT<7> A_DOUT<6> A_DOUT<5> A_DOUT<4> A_DOUT<3> A_DOUT<2> A_DOUT<1> A_DOUT<0> A_MEN A_REN A_WEN VDD! VDDARRAY! VSS! + + +XRAM<1> a_blc_r<63> a_blc_r<62> a_blc_r<61> a_blc_r<60> a_blc_r<59> a_blc_r<58> a_blc_r<57> a_blc_r<56> a_blc_r<55> a_blc_r<54> a_blc_r<53> a_blc_r<52> a_blc_r<51> a_blc_r<50> a_blc_r<49> a_blc_r<48> a_blc_r<47> a_blc_r<46> a_blc_r<45> a_blc_r<44> a_blc_r<43> a_blc_r<42> a_blc_r<41> a_blc_r<40> a_blc_r<39> a_blc_r<38> a_blc_r<37> a_blc_r<36> a_blc_r<35> a_blc_r<34> a_blc_r<33> a_blc_r<32> a_blc_r<31> a_blc_r<30> a_blc_r<29> a_blc_r<28> a_blc_r<27> a_blc_r<26> a_blc_r<25> a_blc_r<24> a_blc_r<23> a_blc_r<22> a_blc_r<21> a_blc_r<20> a_blc_r<19> a_blc_r<18> a_blc_r<17> a_blc_r<16> a_blc_r<15> a_blc_r<14> a_blc_r<13> a_blc_r<12> a_blc_r<11> a_blc_r<10> a_blc_r<9> a_blc_r<8> a_blc_r<7> a_blc_r<6> a_blc_r<5> a_blc_r<4> a_blc_r<3> a_blc_r<2> a_blc_r<1> a_blc_r<0> a_blt_r<63> a_blt_r<62> a_blt_r<61> a_blt_r<60> a_blt_r<59> a_blt_r<58> a_blt_r<57> a_blt_r<56> a_blt_r<55> a_blt_r<54> a_blt_r<53> a_blt_r<52> a_blt_r<51> a_blt_r<50> a_blt_r<49> a_blt_r<48> a_blt_r<47> a_blt_r<46> a_blt_r<45> a_blt_r<44> a_blt_r<43> a_blt_r<42> a_blt_r<41> a_blt_r<40> a_blt_r<39> a_blt_r<38> a_blt_r<37> a_blt_r<36> a_blt_r<35> a_blt_r<34> a_blt_r<33> a_blt_r<32> a_blt_r<31> a_blt_r<30> a_blt_r<29> a_blt_r<28> a_blt_r<27> a_blt_r<26> a_blt_r<25> a_blt_r<24> a_blt_r<23> a_blt_r<22> a_blt_r<21> a_blt_r<20> a_blt_r<19> a_blt_r<18> a_blt_r<17> a_blt_r<16> a_blt_r<15> a_blt_r<14> a_blt_r<13> a_blt_r<12> a_blt_r<11> a_blt_r<10> a_blt_r<9> a_blt_r<8> a_blt_r<7> a_blt_r<6> a_blt_r<5> a_blt_r<4> a_blt_r<3> a_blt_r<2> a_blt_r<1> a_blt_r<0> a_wl_r<127> a_wl_r<126> a_wl_r<125> a_wl_r<124> a_wl_r<123> a_wl_r<122> a_wl_r<121> a_wl_r<120> a_wl_r<119> a_wl_r<118> a_wl_r<117> a_wl_r<116> a_wl_r<115> a_wl_r<114> a_wl_r<113> a_wl_r<112> a_wl_r<111> a_wl_r<110> a_wl_r<109> a_wl_r<108> a_wl_r<107> a_wl_r<106> a_wl_r<105> a_wl_r<104> a_wl_r<103> a_wl_r<102> a_wl_r<101> a_wl_r<100> a_wl_r<99> a_wl_r<98> a_wl_r<97> a_wl_r<96> a_wl_r<95> a_wl_r<94> a_wl_r<93> a_wl_r<92> a_wl_r<91> a_wl_r<90> a_wl_r<89> a_wl_r<88> a_wl_r<87> a_wl_r<86> a_wl_r<85> a_wl_r<84> a_wl_r<83> a_wl_r<82> a_wl_r<81> a_wl_r<80> a_wl_r<79> a_wl_r<78> a_wl_r<77> a_wl_r<76> a_wl_r<75> a_wl_r<74> a_wl_r<73> a_wl_r<72> a_wl_r<71> a_wl_r<70> a_wl_r<69> a_wl_r<68> a_wl_r<67> a_wl_r<66> a_wl_r<65> a_wl_r<64> a_wl_r<63> a_wl_r<62> a_wl_r<61> a_wl_r<60> a_wl_r<59> a_wl_r<58> a_wl_r<57> a_wl_r<56> a_wl_r<55> a_wl_r<54> a_wl_r<53> a_wl_r<52> a_wl_r<51> a_wl_r<50> a_wl_r<49> a_wl_r<48> a_wl_r<47> a_wl_r<46> a_wl_r<45> a_wl_r<44> a_wl_r<43> a_wl_r<42> a_wl_r<41> a_wl_r<40> a_wl_r<39> a_wl_r<38> a_wl_r<37> a_wl_r<36> a_wl_r<35> a_wl_r<34> a_wl_r<33> a_wl_r<32> a_wl_r<31> a_wl_r<30> a_wl_r<29> a_wl_r<28> a_wl_r<27> a_wl_r<26> a_wl_r<25> a_wl_r<24> a_wl_r<23> a_wl_r<22> a_wl_r<21> a_wl_r<20> a_wl_r<19> a_wl_r<18> a_wl_r<17> a_wl_r<16> a_wl_r<15> a_wl_r<14> a_wl_r<13> a_wl_r<12> a_wl_r<11> a_wl_r<10> a_wl_r<9> a_wl_r<8> a_wl_r<7> a_wl_r<6> a_wl_r<5> a_wl_r<4> a_wl_r<3> a_wl_r<2> a_wl_r<1> a_wl_r<0> VDDARRAY! VSS! / RM_IHPSG13_512x32_c2_1P_MATRIX_pcell_1 +XRAM<0> a_blc_l<63> a_blc_l<62> a_blc_l<61> a_blc_l<60> a_blc_l<59> a_blc_l<58> a_blc_l<57> a_blc_l<56> a_blc_l<55> a_blc_l<54> a_blc_l<53> a_blc_l<52> a_blc_l<51> a_blc_l<50> a_blc_l<49> a_blc_l<48> a_blc_l<47> a_blc_l<46> a_blc_l<45> a_blc_l<44> a_blc_l<43> a_blc_l<42> a_blc_l<41> a_blc_l<40> a_blc_l<39> a_blc_l<38> a_blc_l<37> a_blc_l<36> a_blc_l<35> a_blc_l<34> a_blc_l<33> a_blc_l<32> a_blc_l<31> a_blc_l<30> a_blc_l<29> a_blc_l<28> a_blc_l<27> a_blc_l<26> a_blc_l<25> a_blc_l<24> a_blc_l<23> a_blc_l<22> a_blc_l<21> a_blc_l<20> a_blc_l<19> a_blc_l<18> a_blc_l<17> a_blc_l<16> a_blc_l<15> a_blc_l<14> a_blc_l<13> a_blc_l<12> a_blc_l<11> a_blc_l<10> a_blc_l<9> a_blc_l<8> a_blc_l<7> a_blc_l<6> a_blc_l<5> a_blc_l<4> a_blc_l<3> a_blc_l<2> a_blc_l<1> a_blc_l<0> a_blt_l<63> a_blt_l<62> a_blt_l<61> a_blt_l<60> a_blt_l<59> a_blt_l<58> a_blt_l<57> a_blt_l<56> a_blt_l<55> a_blt_l<54> a_blt_l<53> a_blt_l<52> a_blt_l<51> a_blt_l<50> a_blt_l<49> a_blt_l<48> a_blt_l<47> a_blt_l<46> a_blt_l<45> a_blt_l<44> a_blt_l<43> a_blt_l<42> a_blt_l<41> a_blt_l<40> a_blt_l<39> a_blt_l<38> a_blt_l<37> a_blt_l<36> a_blt_l<35> a_blt_l<34> a_blt_l<33> a_blt_l<32> a_blt_l<31> a_blt_l<30> a_blt_l<29> a_blt_l<28> a_blt_l<27> a_blt_l<26> a_blt_l<25> a_blt_l<24> a_blt_l<23> a_blt_l<22> a_blt_l<21> a_blt_l<20> a_blt_l<19> a_blt_l<18> a_blt_l<17> a_blt_l<16> a_blt_l<15> a_blt_l<14> a_blt_l<13> a_blt_l<12> a_blt_l<11> a_blt_l<10> a_blt_l<9> a_blt_l<8> a_blt_l<7> a_blt_l<6> a_blt_l<5> a_blt_l<4> a_blt_l<3> a_blt_l<2> a_blt_l<1> a_blt_l<0> a_wl_l<127> a_wl_l<126> a_wl_l<125> a_wl_l<124> a_wl_l<123> a_wl_l<122> a_wl_l<121> a_wl_l<120> a_wl_l<119> a_wl_l<118> a_wl_l<117> a_wl_l<116> a_wl_l<115> a_wl_l<114> a_wl_l<113> a_wl_l<112> a_wl_l<111> a_wl_l<110> a_wl_l<109> a_wl_l<108> a_wl_l<107> a_wl_l<106> a_wl_l<105> a_wl_l<104> a_wl_l<103> a_wl_l<102> a_wl_l<101> a_wl_l<100> a_wl_l<99> a_wl_l<98> a_wl_l<97> a_wl_l<96> a_wl_l<95> a_wl_l<94> a_wl_l<93> a_wl_l<92> a_wl_l<91> a_wl_l<90> a_wl_l<89> a_wl_l<88> a_wl_l<87> a_wl_l<86> a_wl_l<85> a_wl_l<84> a_wl_l<83> a_wl_l<82> a_wl_l<81> a_wl_l<80> a_wl_l<79> a_wl_l<78> a_wl_l<77> a_wl_l<76> a_wl_l<75> a_wl_l<74> a_wl_l<73> a_wl_l<72> a_wl_l<71> a_wl_l<70> a_wl_l<69> a_wl_l<68> a_wl_l<67> a_wl_l<66> a_wl_l<65> a_wl_l<64> a_wl_l<63> a_wl_l<62> a_wl_l<61> a_wl_l<60> a_wl_l<59> a_wl_l<58> a_wl_l<57> a_wl_l<56> a_wl_l<55> a_wl_l<54> a_wl_l<53> a_wl_l<52> a_wl_l<51> a_wl_l<50> a_wl_l<49> a_wl_l<48> a_wl_l<47> a_wl_l<46> a_wl_l<45> a_wl_l<44> a_wl_l<43> a_wl_l<42> a_wl_l<41> a_wl_l<40> a_wl_l<39> a_wl_l<38> a_wl_l<37> a_wl_l<36> a_wl_l<35> a_wl_l<34> a_wl_l<33> a_wl_l<32> a_wl_l<31> a_wl_l<30> a_wl_l<29> a_wl_l<28> a_wl_l<27> a_wl_l<26> a_wl_l<25> a_wl_l<24> a_wl_l<23> a_wl_l<22> a_wl_l<21> a_wl_l<20> a_wl_l<19> a_wl_l<18> a_wl_l<17> a_wl_l<16> a_wl_l<15> a_wl_l<14> a_wl_l<13> a_wl_l<12> a_wl_l<11> a_wl_l<10> a_wl_l<9> a_wl_l<8> a_wl_l<7> a_wl_l<6> a_wl_l<5> a_wl_l<4> a_wl_l<3> a_wl_l<2> a_wl_l<1> a_wl_l<0> VDDARRAY! VSS! / RM_IHPSG13_512x32_c2_1P_MATRIX_pcell_1 + + +XA_COLDRV<1> a_addr_col<1> a_addr_col<0> a_addr_col_r<1> a_addr_col_r<0> a_addr_dec<7> a_addr_dec<6> a_addr_dec<5> a_addr_dec<4> a_addr_dec<3> a_addr_dec<2> a_addr_dec<1> a_addr_dec<0> a_addr_dec_r<7> a_addr_dec_r<6> a_addr_dec_r<5> a_addr_dec_r<4> a_addr_dec_r<3> a_addr_dec_r<2> a_addr_dec_r<1> a_addr_dec_r<0> a_dclk a_dclk_p_r<0> a_rclk a_rclk_p_r<0> a_wclk a_wclk_p_r<0> VDD! VSS! / RM_IHPSG13_512x32_c2_1P_COLDRV13X4 +XA_COLDRV<0> a_addr_col<1> a_addr_col<0> a_addr_col_l<1> a_addr_col_l<0> a_addr_dec<7> a_addr_dec<6> a_addr_dec<5> a_addr_dec<4> a_addr_dec<3> a_addr_dec<2> a_addr_dec<1> a_addr_dec<0> a_addr_dec_l<7> a_addr_dec_l<6> a_addr_dec_l<5> a_addr_dec_l<4> a_addr_dec_l<3> a_addr_dec_l<2> a_addr_dec_l<1> a_addr_dec_l<0> a_dclk a_dclk_p_l<0> a_rclk a_rclk_p_l<0> a_wclk a_wclk_p_l<0> VDD! VSS! / RM_IHPSG13_512x32_c2_1P_COLDRV13X4 + + +XA_WLDRV<15> a_wi<127> a_wi<126> a_wi<125> a_wi<124> a_wi<123> a_wi<122> a_wi<121> a_wi<120> a_wi<119> a_wi<118> a_wi<117> a_wi<116> a_wi<115> a_wi<114> a_wi<113> a_wi<112> a_wl_r<127> a_wl_r<126> a_wl_r<125> a_wl_r<124> a_wl_r<123> a_wl_r<122> a_wl_r<121> a_wl_r<120> a_wl_r<119> a_wl_r<118> a_wl_r<117> a_wl_r<116> a_wl_r<115> a_wl_r<114> a_wl_r<113> a_wl_r<112> VDD! VSS! / RM_IHPSG13_512x32_c2_1P_WLDRV16X4 +XA_WLDRV<14> a_wi<111> a_wi<110> a_wi<109> a_wi<108> a_wi<107> a_wi<106> a_wi<105> a_wi<104> a_wi<103> a_wi<102> a_wi<101> a_wi<100> a_wi<99> a_wi<98> a_wi<97> a_wi<96> a_wl_r<111> a_wl_r<110> a_wl_r<109> a_wl_r<108> a_wl_r<107> a_wl_r<106> a_wl_r<105> a_wl_r<104> a_wl_r<103> a_wl_r<102> a_wl_r<101> a_wl_r<100> a_wl_r<99> a_wl_r<98> a_wl_r<97> a_wl_r<96> VDD! VSS! / RM_IHPSG13_512x32_c2_1P_WLDRV16X4 +XA_WLDRV<13> a_wi<95> a_wi<94> a_wi<93> a_wi<92> a_wi<91> a_wi<90> a_wi<89> a_wi<88> a_wi<87> a_wi<86> a_wi<85> a_wi<84> a_wi<83> a_wi<82> a_wi<81> a_wi<80> a_wl_r<95> a_wl_r<94> a_wl_r<93> a_wl_r<92> a_wl_r<91> a_wl_r<90> a_wl_r<89> a_wl_r<88> a_wl_r<87> a_wl_r<86> a_wl_r<85> a_wl_r<84> a_wl_r<83> a_wl_r<82> a_wl_r<81> a_wl_r<80> VDD! VSS! / RM_IHPSG13_512x32_c2_1P_WLDRV16X4 +XA_WLDRV<12> a_wi<79> a_wi<78> a_wi<77> a_wi<76> a_wi<75> a_wi<74> a_wi<73> a_wi<72> a_wi<71> a_wi<70> a_wi<69> a_wi<68> a_wi<67> a_wi<66> a_wi<65> a_wi<64> a_wl_r<79> a_wl_r<78> a_wl_r<77> a_wl_r<76> a_wl_r<75> a_wl_r<74> a_wl_r<73> a_wl_r<72> a_wl_r<71> a_wl_r<70> a_wl_r<69> a_wl_r<68> a_wl_r<67> a_wl_r<66> a_wl_r<65> a_wl_r<64> VDD! VSS! / RM_IHPSG13_512x32_c2_1P_WLDRV16X4 +XA_WLDRV<11> a_wi<63> a_wi<62> a_wi<61> a_wi<60> a_wi<59> a_wi<58> a_wi<57> a_wi<56> a_wi<55> a_wi<54> a_wi<53> a_wi<52> a_wi<51> a_wi<50> a_wi<49> a_wi<48> a_wl_r<63> a_wl_r<62> a_wl_r<61> a_wl_r<60> a_wl_r<59> a_wl_r<58> a_wl_r<57> a_wl_r<56> a_wl_r<55> a_wl_r<54> a_wl_r<53> a_wl_r<52> a_wl_r<51> a_wl_r<50> a_wl_r<49> a_wl_r<48> VDD! VSS! / RM_IHPSG13_512x32_c2_1P_WLDRV16X4 +XA_WLDRV<10> a_wi<47> a_wi<46> a_wi<45> a_wi<44> a_wi<43> a_wi<42> a_wi<41> a_wi<40> a_wi<39> a_wi<38> a_wi<37> a_wi<36> a_wi<35> a_wi<34> a_wi<33> a_wi<32> a_wl_r<47> a_wl_r<46> a_wl_r<45> a_wl_r<44> a_wl_r<43> a_wl_r<42> a_wl_r<41> a_wl_r<40> a_wl_r<39> a_wl_r<38> a_wl_r<37> a_wl_r<36> a_wl_r<35> a_wl_r<34> a_wl_r<33> a_wl_r<32> VDD! VSS! / RM_IHPSG13_512x32_c2_1P_WLDRV16X4 +XA_WLDRV<9> a_wi<31> a_wi<30> a_wi<29> a_wi<28> a_wi<27> a_wi<26> a_wi<25> a_wi<24> a_wi<23> a_wi<22> a_wi<21> a_wi<20> a_wi<19> a_wi<18> a_wi<17> a_wi<16> a_wl_r<31> a_wl_r<30> a_wl_r<29> a_wl_r<28> a_wl_r<27> a_wl_r<26> a_wl_r<25> a_wl_r<24> a_wl_r<23> a_wl_r<22> a_wl_r<21> a_wl_r<20> a_wl_r<19> a_wl_r<18> a_wl_r<17> a_wl_r<16> VDD! VSS! / RM_IHPSG13_512x32_c2_1P_WLDRV16X4 +XA_WLDRV<8> a_wi<15> a_wi<14> a_wi<13> a_wi<12> a_wi<11> a_wi<10> a_wi<9> a_wi<8> a_wi<7> a_wi<6> a_wi<5> a_wi<4> a_wi<3> a_wi<2> a_wi<1> a_wi<0> a_wl_r<15> a_wl_r<14> a_wl_r<13> a_wl_r<12> a_wl_r<11> a_wl_r<10> a_wl_r<9> a_wl_r<8> a_wl_r<7> a_wl_r<6> a_wl_r<5> a_wl_r<4> a_wl_r<3> a_wl_r<2> a_wl_r<1> a_wl_r<0> VDD! VSS! / RM_IHPSG13_512x32_c2_1P_WLDRV16X4 +XA_WLDRV<7> a_wi<127> a_wi<126> a_wi<125> a_wi<124> a_wi<123> a_wi<122> a_wi<121> a_wi<120> a_wi<119> a_wi<118> a_wi<117> a_wi<116> a_wi<115> a_wi<114> a_wi<113> a_wi<112> a_wl_l<127> a_wl_l<126> a_wl_l<125> a_wl_l<124> a_wl_l<123> a_wl_l<122> a_wl_l<121> a_wl_l<120> a_wl_l<119> a_wl_l<118> a_wl_l<117> a_wl_l<116> a_wl_l<115> a_wl_l<114> a_wl_l<113> a_wl_l<112> VDD! VSS! / RM_IHPSG13_512x32_c2_1P_WLDRV16X4 +XA_WLDRV<6> a_wi<111> a_wi<110> a_wi<109> a_wi<108> a_wi<107> a_wi<106> a_wi<105> a_wi<104> a_wi<103> a_wi<102> a_wi<101> a_wi<100> a_wi<99> a_wi<98> a_wi<97> a_wi<96> a_wl_l<111> a_wl_l<110> a_wl_l<109> a_wl_l<108> a_wl_l<107> a_wl_l<106> a_wl_l<105> a_wl_l<104> a_wl_l<103> a_wl_l<102> a_wl_l<101> a_wl_l<100> a_wl_l<99> a_wl_l<98> a_wl_l<97> a_wl_l<96> VDD! VSS! / RM_IHPSG13_512x32_c2_1P_WLDRV16X4 +XA_WLDRV<5> a_wi<95> a_wi<94> a_wi<93> a_wi<92> a_wi<91> a_wi<90> a_wi<89> a_wi<88> a_wi<87> a_wi<86> a_wi<85> a_wi<84> a_wi<83> a_wi<82> a_wi<81> a_wi<80> a_wl_l<95> a_wl_l<94> a_wl_l<93> a_wl_l<92> a_wl_l<91> a_wl_l<90> a_wl_l<89> a_wl_l<88> a_wl_l<87> a_wl_l<86> a_wl_l<85> a_wl_l<84> a_wl_l<83> a_wl_l<82> a_wl_l<81> a_wl_l<80> VDD! VSS! / RM_IHPSG13_512x32_c2_1P_WLDRV16X4 +XA_WLDRV<4> a_wi<79> a_wi<78> a_wi<77> a_wi<76> a_wi<75> a_wi<74> a_wi<73> a_wi<72> a_wi<71> a_wi<70> a_wi<69> a_wi<68> a_wi<67> a_wi<66> a_wi<65> a_wi<64> a_wl_l<79> a_wl_l<78> a_wl_l<77> a_wl_l<76> a_wl_l<75> a_wl_l<74> a_wl_l<73> a_wl_l<72> a_wl_l<71> a_wl_l<70> a_wl_l<69> a_wl_l<68> a_wl_l<67> a_wl_l<66> a_wl_l<65> a_wl_l<64> VDD! VSS! / RM_IHPSG13_512x32_c2_1P_WLDRV16X4 +XA_WLDRV<3> a_wi<63> a_wi<62> a_wi<61> a_wi<60> a_wi<59> a_wi<58> a_wi<57> a_wi<56> a_wi<55> a_wi<54> a_wi<53> a_wi<52> a_wi<51> a_wi<50> a_wi<49> a_wi<48> a_wl_l<63> a_wl_l<62> a_wl_l<61> a_wl_l<60> a_wl_l<59> a_wl_l<58> a_wl_l<57> a_wl_l<56> a_wl_l<55> a_wl_l<54> a_wl_l<53> a_wl_l<52> a_wl_l<51> a_wl_l<50> a_wl_l<49> a_wl_l<48> VDD! VSS! / RM_IHPSG13_512x32_c2_1P_WLDRV16X4 +XA_WLDRV<2> a_wi<47> a_wi<46> a_wi<45> a_wi<44> a_wi<43> a_wi<42> a_wi<41> a_wi<40> a_wi<39> a_wi<38> a_wi<37> a_wi<36> a_wi<35> a_wi<34> a_wi<33> a_wi<32> a_wl_l<47> a_wl_l<46> a_wl_l<45> a_wl_l<44> a_wl_l<43> a_wl_l<42> a_wl_l<41> a_wl_l<40> a_wl_l<39> a_wl_l<38> a_wl_l<37> a_wl_l<36> a_wl_l<35> a_wl_l<34> a_wl_l<33> a_wl_l<32> VDD! VSS! / RM_IHPSG13_512x32_c2_1P_WLDRV16X4 +XA_WLDRV<1> a_wi<31> a_wi<30> a_wi<29> a_wi<28> a_wi<27> a_wi<26> a_wi<25> a_wi<24> a_wi<23> a_wi<22> a_wi<21> a_wi<20> a_wi<19> a_wi<18> a_wi<17> a_wi<16> a_wl_l<31> a_wl_l<30> a_wl_l<29> a_wl_l<28> a_wl_l<27> a_wl_l<26> a_wl_l<25> a_wl_l<24> a_wl_l<23> a_wl_l<22> a_wl_l<21> a_wl_l<20> a_wl_l<19> a_wl_l<18> a_wl_l<17> a_wl_l<16> VDD! VSS! / RM_IHPSG13_512x32_c2_1P_WLDRV16X4 +XA_WLDRV<0> a_wi<15> a_wi<14> a_wi<13> a_wi<12> a_wi<11> a_wi<10> a_wi<9> a_wi<8> a_wi<7> a_wi<6> a_wi<5> a_wi<4> a_wi<3> a_wi<2> a_wi<1> a_wi<0> a_wl_l<15> a_wl_l<14> a_wl_l<13> a_wl_l<12> a_wl_l<11> a_wl_l<10> a_wl_l<9> a_wl_l<8> a_wl_l<7> a_wl_l<6> a_wl_l<5> a_wl_l<4> a_wl_l<3> a_wl_l<2> a_wl_l<1> a_wl_l<0> VDD! VSS! / RM_IHPSG13_512x32_c2_1P_WLDRV16X4 + + +XA_CTRL a_aclk_n A_BIST_CLK A_BIST_MEN A_BIST_EN A_BIST_REN A_BIST_WEN a_tiel A_CLK A_MEN a_dclk a_eclk a_pulse_h a_pulse_l a_pulse a_rclk A_REN a_cs a_wclk A_WEN VDD! VSS! / RM_IHPSG13_512x32_c2_1P_CTRL + + +XA_ROWDEC a_addr_row<6> a_addr_row<5> a_addr_row<4> a_addr_row<3> a_addr_row<2> a_addr_row<1> a_addr_row<0> a_cs a_eclk a_wi<127> a_wi<126> a_wi<125> a_wi<124> a_wi<123> a_wi<122> a_wi<121> a_wi<120> a_wi<119> a_wi<118> a_wi<117> a_wi<116> a_wi<115> a_wi<114> a_wi<113> a_wi<112> a_wi<111> a_wi<110> a_wi<109> a_wi<108> a_wi<107> a_wi<106> a_wi<105> a_wi<104> a_wi<103> a_wi<102> a_wi<101> a_wi<100> a_wi<99> a_wi<98> a_wi<97> a_wi<96> a_wi<95> a_wi<94> a_wi<93> a_wi<92> a_wi<91> a_wi<90> a_wi<89> a_wi<88> a_wi<87> a_wi<86> a_wi<85> a_wi<84> a_wi<83> a_wi<82> a_wi<81> a_wi<80> a_wi<79> a_wi<78> a_wi<77> a_wi<76> a_wi<75> a_wi<74> a_wi<73> a_wi<72> a_wi<71> a_wi<70> a_wi<69> a_wi<68> a_wi<67> a_wi<66> a_wi<65> a_wi<64> a_wi<63> a_wi<62> a_wi<61> a_wi<60> a_wi<59> a_wi<58> a_wi<57> a_wi<56> a_wi<55> a_wi<54> a_wi<53> a_wi<52> a_wi<51> a_wi<50> a_wi<49> a_wi<48> a_wi<47> a_wi<46> a_wi<45> a_wi<44> a_wi<43> a_wi<42> a_wi<41> a_wi<40> a_wi<39> a_wi<38> a_wi<37> a_wi<36> a_wi<35> a_wi<34> a_wi<33> a_wi<32> a_wi<31> a_wi<30> a_wi<29> a_wi<28> a_wi<27> a_wi<26> a_wi<25> a_wi<24> a_wi<23> a_wi<22> a_wi<21> a_wi<20> a_wi<19> a_wi<18> a_wi<17> a_wi<16> a_wi<15> a_wi<14> a_wi<13> a_wi<12> a_wi<11> a_wi<10> a_wi<9> a_wi<8> a_wi<7> a_wi<6> a_wi<5> a_wi<4> a_wi<3> a_wi<2> a_wi<1> a_wi<0> VDD! VSS! / RM_IHPSG13_512x32_c2_1P_ROWDEC7 +XA_ROWREG a_aclk_n A_ADDR<8> A_ADDR<7> A_ADDR<6> A_ADDR<5> A_ADDR<4> A_ADDR<3> A_ADDR<2> a_addr_row<6> a_addr_row<5> a_addr_row<4> a_addr_row<3> a_addr_row<2> a_addr_row<1> a_addr_row<0> A_BIST_ADDR<8> A_BIST_ADDR<7> A_BIST_ADDR<6> A_BIST_ADDR<5> A_BIST_ADDR<4> A_BIST_ADDR<3> A_BIST_ADDR<2> A_BIST_EN VDD! VSS! / RM_IHPSG13_512x32_c2_1P_ROWREG7 +XA_COLDEC a_aclk_n A_ADDR<1> A_ADDR<0> a_addr_col<1> a_addr_col<0> a_addr_dec<7> a_addr_dec<6> a_addr_dec<5> a_addr_dec<4> a_addr_dec<3> a_addr_dec<2> a_addr_dec<1> a_addr_dec<0> A_BIST_ADDR<1> A_BIST_ADDR<0> A_BIST_EN VDD! VSS! / RM_IHPSG13_512x32_c2_1P_COLDEC2 + + +XA_DLYH a_pulse a_pulse_h VDD! VSS! / RM_IHPSG13_512x32_c2_1P_DLY_pcell_2 +XA_DLYL a_pulse_x a_pulse_l VDD! VSS! / RM_IHPSG13_512x32_c2_1P_DLY_pcell_3 +XA_DLYMUX a_pulse_h A_DLY a_pulse_x VDD! VSS! / RM_IHPSG13_512x32_c2_1P_DLY_MUX + +XCOLCTRL<31> a_addr_dec_r<3> a_addr_dec_r<2> a_addr_dec_r<1> a_addr_dec_r<0> A_BIST_BM<31> A_BIST_DIN<31> A_BIST_EN a_blc_r<63> a_blc_r<62> a_blc_r<61> a_blc_r<60> a_blt_r<63> a_blt_r<62> a_blt_r<61> a_blt_r<60> A_BM<31> a_dclk_n_r<15> a_dclk_n_r<16> a_dclk_p_r<15> a_dclk_p_r<16> A_DOUT<31> A_DIN<31> a_rclk_n_r<15> a_rclk_n_r<16> a_rclk_p_r<15> a_rclk_p_r<16> a_tieh<31> a_wclk_n_r<15> a_wclk_n_r<16> a_wclk_p_r<15> a_wclk_p_r<16> VDD! VSS! / RM_IHPSG13_512x32_c2_1P_COLCTRL2 +XCOLCTRL<30> a_addr_dec_r<3> a_addr_dec_r<2> a_addr_dec_r<1> a_addr_dec_r<0> A_BIST_BM<30> A_BIST_DIN<30> A_BIST_EN a_blc_r<59> a_blc_r<58> a_blc_r<57> a_blc_r<56> a_blt_r<59> a_blt_r<58> a_blt_r<57> a_blt_r<56> A_BM<30> a_dclk_n_r<14> a_dclk_n_r<15> a_dclk_p_r<14> a_dclk_p_r<15> A_DOUT<30> A_DIN<30> a_rclk_n_r<14> a_rclk_n_r<15> a_rclk_p_r<14> a_rclk_p_r<15> a_tieh<30> a_wclk_n_r<14> a_wclk_n_r<15> a_wclk_p_r<14> a_wclk_p_r<15> VDD! VSS! / RM_IHPSG13_512x32_c2_1P_COLCTRL2 +XCOLCTRL<29> a_addr_dec_r<3> a_addr_dec_r<2> a_addr_dec_r<1> a_addr_dec_r<0> A_BIST_BM<29> A_BIST_DIN<29> A_BIST_EN a_blc_r<55> a_blc_r<54> a_blc_r<53> a_blc_r<52> a_blt_r<55> a_blt_r<54> a_blt_r<53> a_blt_r<52> A_BM<29> a_dclk_n_r<13> a_dclk_n_r<14> a_dclk_p_r<13> a_dclk_p_r<14> A_DOUT<29> A_DIN<29> a_rclk_n_r<13> a_rclk_n_r<14> a_rclk_p_r<13> a_rclk_p_r<14> a_tieh<29> a_wclk_n_r<13> a_wclk_n_r<14> a_wclk_p_r<13> a_wclk_p_r<14> VDD! VSS! / RM_IHPSG13_512x32_c2_1P_COLCTRL2 +XCOLCTRL<28> a_addr_dec_r<3> a_addr_dec_r<2> a_addr_dec_r<1> a_addr_dec_r<0> A_BIST_BM<28> A_BIST_DIN<28> A_BIST_EN a_blc_r<51> a_blc_r<50> a_blc_r<49> a_blc_r<48> a_blt_r<51> a_blt_r<50> a_blt_r<49> a_blt_r<48> A_BM<28> a_dclk_n_r<12> a_dclk_n_r<13> a_dclk_p_r<12> a_dclk_p_r<13> A_DOUT<28> A_DIN<28> a_rclk_n_r<12> a_rclk_n_r<13> a_rclk_p_r<12> a_rclk_p_r<13> a_tieh<28> a_wclk_n_r<12> a_wclk_n_r<13> a_wclk_p_r<12> a_wclk_p_r<13> VDD! VSS! / RM_IHPSG13_512x32_c2_1P_COLCTRL2 +XCOLCTRL<27> a_addr_dec_r<3> a_addr_dec_r<2> a_addr_dec_r<1> a_addr_dec_r<0> A_BIST_BM<27> A_BIST_DIN<27> A_BIST_EN a_blc_r<47> a_blc_r<46> a_blc_r<45> a_blc_r<44> a_blt_r<47> a_blt_r<46> a_blt_r<45> a_blt_r<44> A_BM<27> a_dclk_n_r<11> a_dclk_n_r<12> a_dclk_p_r<11> a_dclk_p_r<12> A_DOUT<27> A_DIN<27> a_rclk_n_r<11> a_rclk_n_r<12> a_rclk_p_r<11> a_rclk_p_r<12> a_tieh<27> a_wclk_n_r<11> a_wclk_n_r<12> a_wclk_p_r<11> a_wclk_p_r<12> VDD! VSS! / RM_IHPSG13_512x32_c2_1P_COLCTRL2 +XCOLCTRL<26> a_addr_dec_r<3> a_addr_dec_r<2> a_addr_dec_r<1> a_addr_dec_r<0> A_BIST_BM<26> A_BIST_DIN<26> A_BIST_EN a_blc_r<43> a_blc_r<42> a_blc_r<41> a_blc_r<40> a_blt_r<43> a_blt_r<42> a_blt_r<41> a_blt_r<40> A_BM<26> a_dclk_n_r<10> a_dclk_n_r<11> a_dclk_p_r<10> a_dclk_p_r<11> A_DOUT<26> A_DIN<26> a_rclk_n_r<10> a_rclk_n_r<11> a_rclk_p_r<10> a_rclk_p_r<11> a_tieh<26> a_wclk_n_r<10> a_wclk_n_r<11> a_wclk_p_r<10> a_wclk_p_r<11> VDD! VSS! / RM_IHPSG13_512x32_c2_1P_COLCTRL2 +XCOLCTRL<25> a_addr_dec_r<3> a_addr_dec_r<2> a_addr_dec_r<1> a_addr_dec_r<0> A_BIST_BM<25> A_BIST_DIN<25> A_BIST_EN a_blc_r<39> a_blc_r<38> a_blc_r<37> a_blc_r<36> a_blt_r<39> a_blt_r<38> a_blt_r<37> a_blt_r<36> A_BM<25> a_dclk_n_r<9> a_dclk_n_r<10> a_dclk_p_r<9> a_dclk_p_r<10> A_DOUT<25> A_DIN<25> a_rclk_n_r<9> a_rclk_n_r<10> a_rclk_p_r<9> a_rclk_p_r<10> a_tieh<25> a_wclk_n_r<9> a_wclk_n_r<10> a_wclk_p_r<9> a_wclk_p_r<10> VDD! VSS! / RM_IHPSG13_512x32_c2_1P_COLCTRL2 +XCOLCTRL<24> a_addr_dec_r<3> a_addr_dec_r<2> a_addr_dec_r<1> a_addr_dec_r<0> A_BIST_BM<24> A_BIST_DIN<24> A_BIST_EN a_blc_r<35> a_blc_r<34> a_blc_r<33> a_blc_r<32> a_blt_r<35> a_blt_r<34> a_blt_r<33> a_blt_r<32> A_BM<24> a_dclk_n_r<8> a_dclk_n_r<9> a_dclk_p_r<8> a_dclk_p_r<9> A_DOUT<24> A_DIN<24> a_rclk_n_r<8> a_rclk_n_r<9> a_rclk_p_r<8> a_rclk_p_r<9> a_tieh<24> a_wclk_n_r<8> a_wclk_n_r<9> a_wclk_p_r<8> a_wclk_p_r<9> VDD! VSS! / RM_IHPSG13_512x32_c2_1P_COLCTRL2 +XCOLCTRL<23> a_addr_dec_r<3> a_addr_dec_r<2> a_addr_dec_r<1> a_addr_dec_r<0> A_BIST_BM<23> A_BIST_DIN<23> A_BIST_EN a_blc_r<31> a_blc_r<30> a_blc_r<29> a_blc_r<28> a_blt_r<31> a_blt_r<30> a_blt_r<29> a_blt_r<28> A_BM<23> a_dclk_n_r<7> a_dclk_n_r<8> a_dclk_p_r<7> a_dclk_p_r<8> A_DOUT<23> A_DIN<23> a_rclk_n_r<7> a_rclk_n_r<8> a_rclk_p_r<7> a_rclk_p_r<8> a_tieh<23> a_wclk_n_r<7> a_wclk_n_r<8> a_wclk_p_r<7> a_wclk_p_r<8> VDD! VSS! / RM_IHPSG13_512x32_c2_1P_COLCTRL2 +XCOLCTRL<22> a_addr_dec_r<3> a_addr_dec_r<2> a_addr_dec_r<1> a_addr_dec_r<0> A_BIST_BM<22> A_BIST_DIN<22> A_BIST_EN a_blc_r<27> a_blc_r<26> a_blc_r<25> a_blc_r<24> a_blt_r<27> a_blt_r<26> a_blt_r<25> a_blt_r<24> A_BM<22> a_dclk_n_r<6> a_dclk_n_r<7> a_dclk_p_r<6> a_dclk_p_r<7> A_DOUT<22> A_DIN<22> a_rclk_n_r<6> a_rclk_n_r<7> a_rclk_p_r<6> a_rclk_p_r<7> a_tieh<22> a_wclk_n_r<6> a_wclk_n_r<7> a_wclk_p_r<6> a_wclk_p_r<7> VDD! VSS! / RM_IHPSG13_512x32_c2_1P_COLCTRL2 +XCOLCTRL<21> a_addr_dec_r<3> a_addr_dec_r<2> a_addr_dec_r<1> a_addr_dec_r<0> A_BIST_BM<21> A_BIST_DIN<21> A_BIST_EN a_blc_r<23> a_blc_r<22> a_blc_r<21> a_blc_r<20> a_blt_r<23> a_blt_r<22> a_blt_r<21> a_blt_r<20> A_BM<21> a_dclk_n_r<5> a_dclk_n_r<6> a_dclk_p_r<5> a_dclk_p_r<6> A_DOUT<21> A_DIN<21> a_rclk_n_r<5> a_rclk_n_r<6> a_rclk_p_r<5> a_rclk_p_r<6> a_tieh<21> a_wclk_n_r<5> a_wclk_n_r<6> a_wclk_p_r<5> a_wclk_p_r<6> VDD! VSS! / RM_IHPSG13_512x32_c2_1P_COLCTRL2 +XCOLCTRL<20> a_addr_dec_r<3> a_addr_dec_r<2> a_addr_dec_r<1> a_addr_dec_r<0> A_BIST_BM<20> A_BIST_DIN<20> A_BIST_EN a_blc_r<19> a_blc_r<18> a_blc_r<17> a_blc_r<16> a_blt_r<19> a_blt_r<18> a_blt_r<17> a_blt_r<16> A_BM<20> a_dclk_n_r<4> a_dclk_n_r<5> a_dclk_p_r<4> a_dclk_p_r<5> A_DOUT<20> A_DIN<20> a_rclk_n_r<4> a_rclk_n_r<5> a_rclk_p_r<4> a_rclk_p_r<5> a_tieh<20> a_wclk_n_r<4> a_wclk_n_r<5> a_wclk_p_r<4> a_wclk_p_r<5> VDD! VSS! / RM_IHPSG13_512x32_c2_1P_COLCTRL2 +XCOLCTRL<19> a_addr_dec_r<3> a_addr_dec_r<2> a_addr_dec_r<1> a_addr_dec_r<0> A_BIST_BM<19> A_BIST_DIN<19> A_BIST_EN a_blc_r<15> a_blc_r<14> a_blc_r<13> a_blc_r<12> a_blt_r<15> a_blt_r<14> a_blt_r<13> a_blt_r<12> A_BM<19> a_dclk_n_r<3> a_dclk_n_r<4> a_dclk_p_r<3> a_dclk_p_r<4> A_DOUT<19> A_DIN<19> a_rclk_n_r<3> a_rclk_n_r<4> a_rclk_p_r<3> a_rclk_p_r<4> a_tieh<19> a_wclk_n_r<3> a_wclk_n_r<4> a_wclk_p_r<3> a_wclk_p_r<4> VDD! VSS! / RM_IHPSG13_512x32_c2_1P_COLCTRL2 +XCOLCTRL<18> a_addr_dec_r<3> a_addr_dec_r<2> a_addr_dec_r<1> a_addr_dec_r<0> A_BIST_BM<18> A_BIST_DIN<18> A_BIST_EN a_blc_r<11> a_blc_r<10> a_blc_r<9> a_blc_r<8> a_blt_r<11> a_blt_r<10> a_blt_r<9> a_blt_r<8> A_BM<18> a_dclk_n_r<2> a_dclk_n_r<3> a_dclk_p_r<2> a_dclk_p_r<3> A_DOUT<18> A_DIN<18> a_rclk_n_r<2> a_rclk_n_r<3> a_rclk_p_r<2> a_rclk_p_r<3> a_tieh<18> a_wclk_n_r<2> a_wclk_n_r<3> a_wclk_p_r<2> a_wclk_p_r<3> VDD! VSS! / RM_IHPSG13_512x32_c2_1P_COLCTRL2 +XCOLCTRL<17> a_addr_dec_r<3> a_addr_dec_r<2> a_addr_dec_r<1> a_addr_dec_r<0> A_BIST_BM<17> A_BIST_DIN<17> A_BIST_EN a_blc_r<7> a_blc_r<6> a_blc_r<5> a_blc_r<4> a_blt_r<7> a_blt_r<6> a_blt_r<5> a_blt_r<4> A_BM<17> a_dclk_n_r<1> a_dclk_n_r<2> a_dclk_p_r<1> a_dclk_p_r<2> A_DOUT<17> A_DIN<17> a_rclk_n_r<1> a_rclk_n_r<2> a_rclk_p_r<1> a_rclk_p_r<2> a_tieh<17> a_wclk_n_r<1> a_wclk_n_r<2> a_wclk_p_r<1> a_wclk_p_r<2> VDD! VSS! / RM_IHPSG13_512x32_c2_1P_COLCTRL2 +XCOLCTRL<16> a_addr_dec_r<3> a_addr_dec_r<2> a_addr_dec_r<1> a_addr_dec_r<0> A_BIST_BM<16> A_BIST_DIN<16> A_BIST_EN a_blc_r<3> a_blc_r<2> a_blc_r<1> a_blc_r<0> a_blt_r<3> a_blt_r<2> a_blt_r<1> a_blt_r<0> A_BM<16> a_dclk_n_r<0> a_dclk_n_r<1> a_dclk_p_r<0> a_dclk_p_r<1> A_DOUT<16> A_DIN<16> a_rclk_n_r<0> a_rclk_n_r<1> a_rclk_p_r<0> a_rclk_p_r<1> a_tieh<16> a_wclk_n_r<0> a_wclk_n_r<1> a_wclk_p_r<0> a_wclk_p_r<1> VDD! VSS! / RM_IHPSG13_512x32_c2_1P_COLCTRL2 +XCOLCTRL<15> a_addr_dec_l<3> a_addr_dec_l<2> a_addr_dec_l<1> a_addr_dec_l<0> A_BIST_BM<0> A_BIST_DIN<0> A_BIST_EN a_blc_l<63> a_blc_l<62> a_blc_l<61> a_blc_l<60> a_blt_l<63> a_blt_l<62> a_blt_l<61> a_blt_l<60> A_BM<0> a_dclk_n_l<15> a_dclk_n_l<16> a_dclk_p_l<15> a_dclk_p_l<16> A_DOUT<0> A_DIN<0> a_rclk_n_l<15> a_rclk_n_l<16> a_rclk_p_l<15> a_rclk_p_l<16> a_tieh<0> a_wclk_n_l<15> a_wclk_n_l<16> a_wclk_p_l<15> a_wclk_p_l<16> VDD! VSS! / RM_IHPSG13_512x32_c2_1P_COLCTRL2 +XCOLCTRL<14> a_addr_dec_l<3> a_addr_dec_l<2> a_addr_dec_l<1> a_addr_dec_l<0> A_BIST_BM<1> A_BIST_DIN<1> A_BIST_EN a_blc_l<59> a_blc_l<58> a_blc_l<57> a_blc_l<56> a_blt_l<59> a_blt_l<58> a_blt_l<57> a_blt_l<56> A_BM<1> a_dclk_n_l<14> a_dclk_n_l<15> a_dclk_p_l<14> a_dclk_p_l<15> A_DOUT<1> A_DIN<1> a_rclk_n_l<14> a_rclk_n_l<15> a_rclk_p_l<14> a_rclk_p_l<15> a_tieh<1> a_wclk_n_l<14> a_wclk_n_l<15> a_wclk_p_l<14> a_wclk_p_l<15> VDD! VSS! / RM_IHPSG13_512x32_c2_1P_COLCTRL2 +XCOLCTRL<13> a_addr_dec_l<3> a_addr_dec_l<2> a_addr_dec_l<1> a_addr_dec_l<0> A_BIST_BM<2> A_BIST_DIN<2> A_BIST_EN a_blc_l<55> a_blc_l<54> a_blc_l<53> a_blc_l<52> a_blt_l<55> a_blt_l<54> a_blt_l<53> a_blt_l<52> A_BM<2> a_dclk_n_l<13> a_dclk_n_l<14> a_dclk_p_l<13> a_dclk_p_l<14> A_DOUT<2> A_DIN<2> a_rclk_n_l<13> a_rclk_n_l<14> a_rclk_p_l<13> a_rclk_p_l<14> a_tieh<2> a_wclk_n_l<13> a_wclk_n_l<14> a_wclk_p_l<13> a_wclk_p_l<14> VDD! VSS! / RM_IHPSG13_512x32_c2_1P_COLCTRL2 +XCOLCTRL<12> a_addr_dec_l<3> a_addr_dec_l<2> a_addr_dec_l<1> a_addr_dec_l<0> A_BIST_BM<3> A_BIST_DIN<3> A_BIST_EN a_blc_l<51> a_blc_l<50> a_blc_l<49> a_blc_l<48> a_blt_l<51> a_blt_l<50> a_blt_l<49> a_blt_l<48> A_BM<3> a_dclk_n_l<12> a_dclk_n_l<13> a_dclk_p_l<12> a_dclk_p_l<13> A_DOUT<3> A_DIN<3> a_rclk_n_l<12> a_rclk_n_l<13> a_rclk_p_l<12> a_rclk_p_l<13> a_tieh<3> a_wclk_n_l<12> a_wclk_n_l<13> a_wclk_p_l<12> a_wclk_p_l<13> VDD! VSS! / RM_IHPSG13_512x32_c2_1P_COLCTRL2 +XCOLCTRL<11> a_addr_dec_l<3> a_addr_dec_l<2> a_addr_dec_l<1> a_addr_dec_l<0> A_BIST_BM<4> A_BIST_DIN<4> A_BIST_EN a_blc_l<47> a_blc_l<46> a_blc_l<45> a_blc_l<44> a_blt_l<47> a_blt_l<46> a_blt_l<45> a_blt_l<44> A_BM<4> a_dclk_n_l<11> a_dclk_n_l<12> a_dclk_p_l<11> a_dclk_p_l<12> A_DOUT<4> A_DIN<4> a_rclk_n_l<11> a_rclk_n_l<12> a_rclk_p_l<11> a_rclk_p_l<12> a_tieh<4> a_wclk_n_l<11> a_wclk_n_l<12> a_wclk_p_l<11> a_wclk_p_l<12> VDD! VSS! / RM_IHPSG13_512x32_c2_1P_COLCTRL2 +XCOLCTRL<10> a_addr_dec_l<3> a_addr_dec_l<2> a_addr_dec_l<1> a_addr_dec_l<0> A_BIST_BM<5> A_BIST_DIN<5> A_BIST_EN a_blc_l<43> a_blc_l<42> a_blc_l<41> a_blc_l<40> a_blt_l<43> a_blt_l<42> a_blt_l<41> a_blt_l<40> A_BM<5> a_dclk_n_l<10> a_dclk_n_l<11> a_dclk_p_l<10> a_dclk_p_l<11> A_DOUT<5> A_DIN<5> a_rclk_n_l<10> a_rclk_n_l<11> a_rclk_p_l<10> a_rclk_p_l<11> a_tieh<5> a_wclk_n_l<10> a_wclk_n_l<11> a_wclk_p_l<10> a_wclk_p_l<11> VDD! VSS! / RM_IHPSG13_512x32_c2_1P_COLCTRL2 +XCOLCTRL<9> a_addr_dec_l<3> a_addr_dec_l<2> a_addr_dec_l<1> a_addr_dec_l<0> A_BIST_BM<6> A_BIST_DIN<6> A_BIST_EN a_blc_l<39> a_blc_l<38> a_blc_l<37> a_blc_l<36> a_blt_l<39> a_blt_l<38> a_blt_l<37> a_blt_l<36> A_BM<6> a_dclk_n_l<9> a_dclk_n_l<10> a_dclk_p_l<9> a_dclk_p_l<10> A_DOUT<6> A_DIN<6> a_rclk_n_l<9> a_rclk_n_l<10> a_rclk_p_l<9> a_rclk_p_l<10> a_tieh<6> a_wclk_n_l<9> a_wclk_n_l<10> a_wclk_p_l<9> a_wclk_p_l<10> VDD! VSS! / RM_IHPSG13_512x32_c2_1P_COLCTRL2 +XCOLCTRL<8> a_addr_dec_l<3> a_addr_dec_l<2> a_addr_dec_l<1> a_addr_dec_l<0> A_BIST_BM<7> A_BIST_DIN<7> A_BIST_EN a_blc_l<35> a_blc_l<34> a_blc_l<33> a_blc_l<32> a_blt_l<35> a_blt_l<34> a_blt_l<33> a_blt_l<32> A_BM<7> a_dclk_n_l<8> a_dclk_n_l<9> a_dclk_p_l<8> a_dclk_p_l<9> A_DOUT<7> A_DIN<7> a_rclk_n_l<8> a_rclk_n_l<9> a_rclk_p_l<8> a_rclk_p_l<9> a_tieh<7> a_wclk_n_l<8> a_wclk_n_l<9> a_wclk_p_l<8> a_wclk_p_l<9> VDD! VSS! / RM_IHPSG13_512x32_c2_1P_COLCTRL2 +XCOLCTRL<7> a_addr_dec_l<3> a_addr_dec_l<2> a_addr_dec_l<1> a_addr_dec_l<0> A_BIST_BM<8> A_BIST_DIN<8> A_BIST_EN a_blc_l<31> a_blc_l<30> a_blc_l<29> a_blc_l<28> a_blt_l<31> a_blt_l<30> a_blt_l<29> a_blt_l<28> A_BM<8> a_dclk_n_l<7> a_dclk_n_l<8> a_dclk_p_l<7> a_dclk_p_l<8> A_DOUT<8> A_DIN<8> a_rclk_n_l<7> a_rclk_n_l<8> a_rclk_p_l<7> a_rclk_p_l<8> a_tieh<8> a_wclk_n_l<7> a_wclk_n_l<8> a_wclk_p_l<7> a_wclk_p_l<8> VDD! VSS! / RM_IHPSG13_512x32_c2_1P_COLCTRL2 +XCOLCTRL<6> a_addr_dec_l<3> a_addr_dec_l<2> a_addr_dec_l<1> a_addr_dec_l<0> A_BIST_BM<9> A_BIST_DIN<9> A_BIST_EN a_blc_l<27> a_blc_l<26> a_blc_l<25> a_blc_l<24> a_blt_l<27> a_blt_l<26> a_blt_l<25> a_blt_l<24> A_BM<9> a_dclk_n_l<6> a_dclk_n_l<7> a_dclk_p_l<6> a_dclk_p_l<7> A_DOUT<9> A_DIN<9> a_rclk_n_l<6> a_rclk_n_l<7> a_rclk_p_l<6> a_rclk_p_l<7> a_tieh<9> a_wclk_n_l<6> a_wclk_n_l<7> a_wclk_p_l<6> a_wclk_p_l<7> VDD! VSS! / RM_IHPSG13_512x32_c2_1P_COLCTRL2 +XCOLCTRL<5> a_addr_dec_l<3> a_addr_dec_l<2> a_addr_dec_l<1> a_addr_dec_l<0> A_BIST_BM<10> A_BIST_DIN<10> A_BIST_EN a_blc_l<23> a_blc_l<22> a_blc_l<21> a_blc_l<20> a_blt_l<23> a_blt_l<22> a_blt_l<21> a_blt_l<20> A_BM<10> a_dclk_n_l<5> a_dclk_n_l<6> a_dclk_p_l<5> a_dclk_p_l<6> A_DOUT<10> A_DIN<10> a_rclk_n_l<5> a_rclk_n_l<6> a_rclk_p_l<5> a_rclk_p_l<6> a_tieh<10> a_wclk_n_l<5> a_wclk_n_l<6> a_wclk_p_l<5> a_wclk_p_l<6> VDD! VSS! / RM_IHPSG13_512x32_c2_1P_COLCTRL2 +XCOLCTRL<4> a_addr_dec_l<3> a_addr_dec_l<2> a_addr_dec_l<1> a_addr_dec_l<0> A_BIST_BM<11> A_BIST_DIN<11> A_BIST_EN a_blc_l<19> a_blc_l<18> a_blc_l<17> a_blc_l<16> a_blt_l<19> a_blt_l<18> a_blt_l<17> a_blt_l<16> A_BM<11> a_dclk_n_l<4> a_dclk_n_l<5> a_dclk_p_l<4> a_dclk_p_l<5> A_DOUT<11> A_DIN<11> a_rclk_n_l<4> a_rclk_n_l<5> a_rclk_p_l<4> a_rclk_p_l<5> a_tieh<11> a_wclk_n_l<4> a_wclk_n_l<5> a_wclk_p_l<4> a_wclk_p_l<5> VDD! VSS! / RM_IHPSG13_512x32_c2_1P_COLCTRL2 +XCOLCTRL<3> a_addr_dec_l<3> a_addr_dec_l<2> a_addr_dec_l<1> a_addr_dec_l<0> A_BIST_BM<12> A_BIST_DIN<12> A_BIST_EN a_blc_l<15> a_blc_l<14> a_blc_l<13> a_blc_l<12> a_blt_l<15> a_blt_l<14> a_blt_l<13> a_blt_l<12> A_BM<12> a_dclk_n_l<3> a_dclk_n_l<4> a_dclk_p_l<3> a_dclk_p_l<4> A_DOUT<12> A_DIN<12> a_rclk_n_l<3> a_rclk_n_l<4> a_rclk_p_l<3> a_rclk_p_l<4> a_tieh<12> a_wclk_n_l<3> a_wclk_n_l<4> a_wclk_p_l<3> a_wclk_p_l<4> VDD! VSS! / RM_IHPSG13_512x32_c2_1P_COLCTRL2 +XCOLCTRL<2> a_addr_dec_l<3> a_addr_dec_l<2> a_addr_dec_l<1> a_addr_dec_l<0> A_BIST_BM<13> A_BIST_DIN<13> A_BIST_EN a_blc_l<11> a_blc_l<10> a_blc_l<9> a_blc_l<8> a_blt_l<11> a_blt_l<10> a_blt_l<9> a_blt_l<8> A_BM<13> a_dclk_n_l<2> a_dclk_n_l<3> a_dclk_p_l<2> a_dclk_p_l<3> A_DOUT<13> A_DIN<13> a_rclk_n_l<2> a_rclk_n_l<3> a_rclk_p_l<2> a_rclk_p_l<3> a_tieh<13> a_wclk_n_l<2> a_wclk_n_l<3> a_wclk_p_l<2> a_wclk_p_l<3> VDD! VSS! / RM_IHPSG13_512x32_c2_1P_COLCTRL2 +XCOLCTRL<1> a_addr_dec_l<3> a_addr_dec_l<2> a_addr_dec_l<1> a_addr_dec_l<0> A_BIST_BM<14> A_BIST_DIN<14> A_BIST_EN a_blc_l<7> a_blc_l<6> a_blc_l<5> a_blc_l<4> a_blt_l<7> a_blt_l<6> a_blt_l<5> a_blt_l<4> A_BM<14> a_dclk_n_l<1> a_dclk_n_l<2> a_dclk_p_l<1> a_dclk_p_l<2> A_DOUT<14> A_DIN<14> a_rclk_n_l<1> a_rclk_n_l<2> a_rclk_p_l<1> a_rclk_p_l<2> a_tieh<14> a_wclk_n_l<1> a_wclk_n_l<2> a_wclk_p_l<1> a_wclk_p_l<2> VDD! VSS! / RM_IHPSG13_512x32_c2_1P_COLCTRL2 +XCOLCTRL<0> a_addr_dec_l<3> a_addr_dec_l<2> a_addr_dec_l<1> a_addr_dec_l<0> A_BIST_BM<15> A_BIST_DIN<15> A_BIST_EN a_blc_l<3> a_blc_l<2> a_blc_l<1> a_blc_l<0> a_blt_l<3> a_blt_l<2> a_blt_l<1> a_blt_l<0> A_BM<15> a_dclk_n_l<0> a_dclk_n_l<1> a_dclk_p_l<0> a_dclk_p_l<1> A_DOUT<15> A_DIN<15> a_rclk_n_l<0> a_rclk_n_l<1> a_rclk_p_l<0> a_rclk_p_l<1> a_tieh<15> a_wclk_n_l<0> a_wclk_n_l<1> a_wclk_p_l<0> a_wclk_p_l<1> VDD! VSS! / RM_IHPSG13_512x32_c2_1P_COLCTRL2 + + +XDRVFILL4<1> VDD! VSS! / RM_IHPSG13_512x32_c2_1P_COLDRV13_FILL4 +XDRVFILL4<2> VDD! VSS! / RM_IHPSG13_512x32_c2_1P_COLDRV13_FILL4 +XCOLFILL4<1> VDD! VSS! / RM_IHPSG13_512x32_c2_1P_COLDRV13_FILL4C2 +XCOLFILL4<2> VDD! VSS! / RM_IHPSG13_512x32_c2_1P_COLDRV13_FILL4C2 +XCOLFILL4<3> VDD! VSS! / RM_IHPSG13_512x32_c2_1P_COLDRV13_FILL4C2 +XCOLFILL4<4> VDD! VSS! / RM_IHPSG13_512x32_c2_1P_COLDRV13_FILL4C2 +XCOLFILL4<5> VDD! VSS! / RM_IHPSG13_512x32_c2_1P_COLDRV13_FILL4C2 +XCOLFILL4<6> VDD! VSS! / RM_IHPSG13_512x32_c2_1P_COLDRV13_FILL4C2 +.ENDS diff --git a/flow/platforms/ihp-sg13g2/cdl/RM_IHPSG13_1P_512x8_c3_bm_bist.cdl b/flow/platforms/ihp-sg13g2/cdl/RM_IHPSG13_1P_512x8_c3_bm_bist.cdl new file mode 100644 index 0000000000..2caeb7151f --- /dev/null +++ b/flow/platforms/ihp-sg13g2/cdl/RM_IHPSG13_1P_512x8_c3_bm_bist.cdl @@ -0,0 +1,6317 @@ +* ------------------------------------------------------ +* +* Copyright 2025 IHP PDK Authors +* +* Licensed under the Apache License, Version 2.0 (the "License"); +* you may not use this file except in compliance with the License. +* You may obtain a copy of the License at +* +* https://www.apache.org/licenses/LICENSE-2.0 +* +* Unless required by applicable law or agreed to in writing, software +* distributed under the License is distributed on an "AS IS" BASIS, +* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +* See the License for the specific language governing permissions and +* limitations under the License. +* +* Generated on Wed Aug 27 16:20:24 2025 +* +* ------------------------------------------------------ + +.SUBCKT RM_IHPSG13_512x8_c3_1P_BITKIT_CORNER NW PW VDD VSS +.ENDS +.SUBCKT RM_IHPSG13_512x8_c3_1P_BITKIT_16x2_CORNER VDD_CORE VSS +XI16 VDD_CORE VSS VDD_CORE VSS / ++ RM_IHPSG13_512x8_c3_1P_BITKIT_CORNER +.ENDS +.SUBCKT RM_IHPSG13_512x8_c3_1P_BITKIT_EDGE_LR LWL NW PW VDD VSS +MN1 VSS LWL VSS VSS sg13_lv_nmos m=1 w=300.0n l=130.00n ng=1 nrd=0 nrs=0 +MN0 VSS net9 VSS VSS sg13_lv_nmos m=1 w=300.0n l=130.00n ng=1 nrd=0 nrs=0 +.ENDS +.SUBCKT RM_IHPSG13_512x8_c3_1P_BITKIT_16x2_EDGE_LR A_WL<15> A_WL<14> A_WL<13> A_WL<12> ++ A_WL<11> A_WL<10> A_WL<9> A_WL<8> A_WL<7> A_WL<6> A_WL<5> A_WL<4> A_WL<3> ++ A_WL<2> A_WL<1> A_WL<0> VDD_CORE VSS +XI0<15> A_WL<15> VDD_CORE VSS VDD_CORE VSS / ++ RM_IHPSG13_512x8_c3_1P_BITKIT_EDGE_LR +XI0<14> A_WL<14> VDD_CORE VSS VDD_CORE VSS / ++ RM_IHPSG13_512x8_c3_1P_BITKIT_EDGE_LR +XI0<13> A_WL<13> VDD_CORE VSS VDD_CORE VSS / ++ RM_IHPSG13_512x8_c3_1P_BITKIT_EDGE_LR +XI0<12> A_WL<12> VDD_CORE VSS VDD_CORE VSS / ++ RM_IHPSG13_512x8_c3_1P_BITKIT_EDGE_LR +XI0<11> A_WL<11> VDD_CORE VSS VDD_CORE VSS / ++ RM_IHPSG13_512x8_c3_1P_BITKIT_EDGE_LR +XI0<10> A_WL<10> VDD_CORE VSS VDD_CORE VSS / ++ RM_IHPSG13_512x8_c3_1P_BITKIT_EDGE_LR +XI0<9> A_WL<9> VDD_CORE VSS VDD_CORE VSS / ++ RM_IHPSG13_512x8_c3_1P_BITKIT_EDGE_LR +XI0<8> A_WL<8> VDD_CORE VSS VDD_CORE VSS / ++ RM_IHPSG13_512x8_c3_1P_BITKIT_EDGE_LR +XI0<7> A_WL<7> VDD_CORE VSS VDD_CORE VSS / ++ RM_IHPSG13_512x8_c3_1P_BITKIT_EDGE_LR +XI0<6> A_WL<6> VDD_CORE VSS VDD_CORE VSS / ++ RM_IHPSG13_512x8_c3_1P_BITKIT_EDGE_LR +XI0<5> A_WL<5> VDD_CORE VSS VDD_CORE VSS / ++ RM_IHPSG13_512x8_c3_1P_BITKIT_EDGE_LR +XI0<4> A_WL<4> VDD_CORE VSS VDD_CORE VSS / ++ RM_IHPSG13_512x8_c3_1P_BITKIT_EDGE_LR +XI0<3> A_WL<3> VDD_CORE VSS VDD_CORE VSS / ++ RM_IHPSG13_512x8_c3_1P_BITKIT_EDGE_LR +XI0<2> A_WL<2> VDD_CORE VSS VDD_CORE VSS / ++ RM_IHPSG13_512x8_c3_1P_BITKIT_EDGE_LR +XI0<1> A_WL<1> VDD_CORE VSS VDD_CORE VSS / ++ RM_IHPSG13_512x8_c3_1P_BITKIT_EDGE_LR +XI0<0> A_WL<0> VDD_CORE VSS VDD_CORE VSS / ++ RM_IHPSG13_512x8_c3_1P_BITKIT_EDGE_LR +.ENDS +.SUBCKT RM_IHPSG13_512x8_c3_1P_BITKIT_CELL BLC_BOT BLC_TOP BLT_BOT BLT_TOP LWL NW PW ++ RWL VDD VSS +MN0 NC NT VSS PW sg13_lv_nmos m=1 w=300.0n l=130.00n ng=1 nrd=0 nrs=0 +MN1 NT NC VSS PW sg13_lv_nmos m=1 w=300.0n l=130.00n ng=1 nrd=0 nrs=0 +MN3 NC RWL BLC_TOP PW sg13_lv_nmos m=1 w=300.0n l=130.00n ng=1 nrd=0 nrs=0 +MN2 BLT_BOT LWL NT PW sg13_lv_nmos m=1 w=300.0n l=130.00n ng=1 nrd=0 nrs=0 +MP1 NT NC VDD NW sg13_lv_pmos m=1 w=150.00n l=130.00n ng=1 nrd=0 nrs=0 +MP0 NC NT VDD NW sg13_lv_pmos m=1 w=150.00n l=130.00n ng=1 nrd=0 nrs=0 +R1 BLC_BOT BLC_TOP lvsres w=2.6e-07 l=6e-07 +R0 BLT_BOT BLT_TOP lvsres w=2.6e-07 l=6e-07 +R2 RWL LWL lvsres w=2.6e-07 l=6e-07 +.ENDS +.SUBCKT RM_IHPSG13_512x8_c3_1P_BITKIT_16x2_SRAM A_BLC_BOT<1> A_BLC_BOT<0> A_BLC_TOP<1> ++ A_BLC_TOP<0> A_BLT_BOT<1> A_BLT_BOT<0> A_BLT_TOP<1> A_BLT_TOP<0> A_LWL<15> ++ A_LWL<14> A_LWL<13> A_LWL<12> A_LWL<11> A_LWL<10> A_LWL<9> A_LWL<8> A_LWL<7> ++ A_LWL<6> A_LWL<5> A_LWL<4> A_LWL<3> A_LWL<2> A_LWL<1> A_LWL<0> A_RWL<15> ++ A_RWL<14> A_RWL<13> A_RWL<12> A_RWL<11> A_RWL<10> A_RWL<9> A_RWL<8> A_RWL<7> ++ A_RWL<6> A_RWL<5> A_RWL<4> A_RWL<3> A_RWL<2> A_RWL<1> A_RWL<0> VDD_CORE ++ VSS +XCELL<31> A_BLC_TOP<1> A_RBLC<15> A_BLT_TOP<1> A_RBLT<15> A_RWL<15> ++ VDD_CORE VSS A_XWL<15> VDD_CORE VSS / ++ RM_IHPSG13_512x8_c3_1P_BITKIT_CELL +XCELL<30> A_RBLC<14> A_RBLC<15> A_RBLT<14> A_RBLT<15> A_RWL<14> VDD_CORE ++ VSS A_XWL<14> VDD_CORE VSS / RM_IHPSG13_512x8_c3_1P_BITKIT_CELL +XCELL<29> A_RBLC<14> A_RBLC<13> A_RBLT<14> A_RBLT<13> A_RWL<13> VDD_CORE ++ VSS A_XWL<13> VDD_CORE VSS / RM_IHPSG13_512x8_c3_1P_BITKIT_CELL +XCELL<28> A_RBLC<12> A_RBLC<13> A_RBLT<12> A_RBLT<13> A_RWL<12> VDD_CORE ++ VSS A_XWL<12> VDD_CORE VSS / RM_IHPSG13_512x8_c3_1P_BITKIT_CELL +XCELL<27> A_RBLC<12> A_RBLC<11> A_RBLT<12> A_RBLT<11> A_RWL<11> VDD_CORE ++ VSS A_XWL<11> VDD_CORE VSS / RM_IHPSG13_512x8_c3_1P_BITKIT_CELL +XCELL<26> A_RBLC<10> A_RBLC<11> A_RBLT<10> A_RBLT<11> A_RWL<10> VDD_CORE ++ VSS A_XWL<10> VDD_CORE VSS / RM_IHPSG13_512x8_c3_1P_BITKIT_CELL +XCELL<25> A_RBLC<10> A_RBLC<9> A_RBLT<10> A_RBLT<9> A_RWL<9> VDD_CORE ++ VSS A_XWL<9> VDD_CORE VSS / RM_IHPSG13_512x8_c3_1P_BITKIT_CELL +XCELL<24> A_RBLC<8> A_RBLC<9> A_RBLT<8> A_RBLT<9> A_RWL<8> VDD_CORE ++ VSS A_XWL<8> VDD_CORE VSS / RM_IHPSG13_512x8_c3_1P_BITKIT_CELL +XCELL<23> A_RBLC<8> A_RBLC<7> A_RBLT<8> A_RBLT<7> A_RWL<7> VDD_CORE ++ VSS A_XWL<7> VDD_CORE VSS / RM_IHPSG13_512x8_c3_1P_BITKIT_CELL +XCELL<22> A_RBLC<6> A_RBLC<7> A_RBLT<6> A_RBLT<7> A_RWL<6> VDD_CORE ++ VSS A_XWL<6> VDD_CORE VSS / RM_IHPSG13_512x8_c3_1P_BITKIT_CELL +XCELL<21> A_RBLC<6> A_RBLC<5> A_RBLT<6> A_RBLT<5> A_RWL<5> VDD_CORE ++ VSS A_XWL<5> VDD_CORE VSS / RM_IHPSG13_512x8_c3_1P_BITKIT_CELL +XCELL<20> A_RBLC<4> A_RBLC<5> A_RBLT<4> A_RBLT<5> A_RWL<4> VDD_CORE ++ VSS A_XWL<4> VDD_CORE VSS / RM_IHPSG13_512x8_c3_1P_BITKIT_CELL +XCELL<19> A_RBLC<4> A_RBLC<3> A_RBLT<4> A_RBLT<3> A_RWL<3> VDD_CORE ++ VSS A_XWL<3> VDD_CORE VSS / RM_IHPSG13_512x8_c3_1P_BITKIT_CELL +XCELL<18> A_RBLC<2> A_RBLC<3> A_RBLT<2> A_RBLT<3> A_RWL<2> VDD_CORE ++ VSS A_XWL<2> VDD_CORE VSS / RM_IHPSG13_512x8_c3_1P_BITKIT_CELL +XCELL<17> A_RBLC<2> A_RBLC<1> A_RBLT<2> A_RBLT<1> A_RWL<1> VDD_CORE ++ VSS A_XWL<1> VDD_CORE VSS / RM_IHPSG13_512x8_c3_1P_BITKIT_CELL +XCELL<16> A_BLC_BOT<1> A_RBLC<1> A_BLT_BOT<1> A_RBLT<1> A_RWL<0> VDD_CORE ++ VSS A_XWL<0> VDD_CORE VSS / RM_IHPSG13_512x8_c3_1P_BITKIT_CELL +XCELL<15> A_BLC_TOP<0> A_LBLC<15> A_BLT_TOP<0> A_LBLT<15> A_LWL<15> ++ VDD_CORE VSS A_XWL<15> VDD_CORE VSS / ++ RM_IHPSG13_512x8_c3_1P_BITKIT_CELL +XCELL<14> A_LBLC<14> A_LBLC<15> A_LBLT<14> A_LBLT<15> A_LWL<14> VDD_CORE ++ VSS A_XWL<14> VDD_CORE VSS / RM_IHPSG13_512x8_c3_1P_BITKIT_CELL +XCELL<13> A_LBLC<14> A_LBLC<13> A_LBLT<14> A_LBLT<13> A_LWL<13> VDD_CORE ++ VSS A_XWL<13> VDD_CORE VSS / RM_IHPSG13_512x8_c3_1P_BITKIT_CELL +XCELL<12> A_LBLC<12> A_LBLC<13> A_LBLT<12> A_LBLT<13> A_LWL<12> VDD_CORE ++ VSS A_XWL<12> VDD_CORE VSS / RM_IHPSG13_512x8_c3_1P_BITKIT_CELL +XCELL<11> A_LBLC<12> A_LBLC<11> A_LBLT<12> A_LBLT<11> A_LWL<11> VDD_CORE ++ VSS A_XWL<11> VDD_CORE VSS / RM_IHPSG13_512x8_c3_1P_BITKIT_CELL +XCELL<10> A_LBLC<10> A_LBLC<11> A_LBLT<10> A_LBLT<11> A_LWL<10> VDD_CORE ++ VSS A_XWL<10> VDD_CORE VSS / RM_IHPSG13_512x8_c3_1P_BITKIT_CELL +XCELL<9> A_LBLC<10> A_LBLC<9> A_LBLT<10> A_LBLT<9> A_LWL<9> VDD_CORE ++ VSS A_XWL<9> VDD_CORE VSS / RM_IHPSG13_512x8_c3_1P_BITKIT_CELL +XCELL<8> A_LBLC<8> A_LBLC<9> A_LBLT<8> A_LBLT<9> A_LWL<8> VDD_CORE ++ VSS A_XWL<8> VDD_CORE VSS / RM_IHPSG13_512x8_c3_1P_BITKIT_CELL +XCELL<7> A_LBLC<8> A_LBLC<7> A_LBLT<8> A_LBLT<7> A_LWL<7> VDD_CORE ++ VSS A_XWL<7> VDD_CORE VSS / RM_IHPSG13_512x8_c3_1P_BITKIT_CELL +XCELL<6> A_LBLC<6> A_LBLC<7> A_LBLT<6> A_LBLT<7> A_LWL<6> VDD_CORE ++ VSS A_XWL<6> VDD_CORE VSS / RM_IHPSG13_512x8_c3_1P_BITKIT_CELL +XCELL<5> A_LBLC<6> A_LBLC<5> A_LBLT<6> A_LBLT<5> A_LWL<5> VDD_CORE ++ VSS A_XWL<5> VDD_CORE VSS / RM_IHPSG13_512x8_c3_1P_BITKIT_CELL +XCELL<4> A_LBLC<4> A_LBLC<5> A_LBLT<4> A_LBLT<5> A_LWL<4> VDD_CORE ++ VSS A_XWL<4> VDD_CORE VSS / RM_IHPSG13_512x8_c3_1P_BITKIT_CELL +XCELL<3> A_LBLC<4> A_LBLC<3> A_LBLT<4> A_LBLT<3> A_LWL<3> VDD_CORE ++ VSS A_XWL<3> VDD_CORE VSS / RM_IHPSG13_512x8_c3_1P_BITKIT_CELL +XCELL<2> A_LBLC<2> A_LBLC<3> A_LBLT<2> A_LBLT<3> A_LWL<2> VDD_CORE ++ VSS A_XWL<2> VDD_CORE VSS / RM_IHPSG13_512x8_c3_1P_BITKIT_CELL +XCELL<1> A_LBLC<2> A_LBLC<1> A_LBLT<2> A_LBLT<1> A_LWL<1> VDD_CORE ++ VSS A_XWL<1> VDD_CORE VSS / RM_IHPSG13_512x8_c3_1P_BITKIT_CELL +XCELL<0> A_BLC_BOT<0> A_LBLC<1> A_BLT_BOT<0> A_LBLT<1> A_LWL<0> VDD_CORE ++ VSS A_XWL<0> VDD_CORE VSS / RM_IHPSG13_512x8_c3_1P_BITKIT_CELL +.ENDS +.SUBCKT RM_IHPSG13_512x8_c3_1P_BITKIT_EDGE_TB BLC BLT NW PW VDD VSS +.ENDS +.SUBCKT RM_IHPSG13_512x8_c3_1P_BITKIT_16x2_EDGE_TB A_BLC<1> A_BLC<0> A_BLT<1> A_BLT<0> ++ VDD_CORE VSS +XEDGE<1> A_BLC<1> A_BLT<1> VDD_CORE VSS VDD_CORE VSS ++ / RM_IHPSG13_512x8_c3_1P_BITKIT_EDGE_TB +XEDGE<0> A_BLC<0> A_BLT<0> VDD_CORE VSS VDD_CORE VSS ++ / RM_IHPSG13_512x8_c3_1P_BITKIT_EDGE_TB +.ENDS + +.SUBCKT RSC_IHPSG13_CBUFX4 A Z VDD VSS +MN0 net9 A VSS VSS sg13_lv_nmos m=1 w=705.000n l=130.00n ng=1 nrd=0 ++ nrs=0 +MN1 Z net9 VSS VSS sg13_lv_nmos m=1 w=1.41u l=130.00n ng=2 nrd=0 nrs=0 +MP0 net9 A VDD VDD sg13_lv_pmos m=1 w=1.62u l=130.00n ng=1 nrd=0 nrs=0 +MP1 Z net9 VDD VDD sg13_lv_pmos m=1 w=3.24u l=130.00n ng=2 nrd=0 nrs=0 +.ENDS +.SUBCKT RM_IHPSG13_512x8_c3_1P_COLDRV13X4 ADDR_COL_I<1> ADDR_COL_I<0> ADDR_COL_O<1> ++ ADDR_COL_O<0> ADDR_DEC_I<7> ADDR_DEC_I<6> ADDR_DEC_I<5> ADDR_DEC_I<4> ++ ADDR_DEC_I<3> ADDR_DEC_I<2> ADDR_DEC_I<1> ADDR_DEC_I<0> ADDR_DEC_O<7> ++ ADDR_DEC_O<6> ADDR_DEC_O<5> ADDR_DEC_O<4> ADDR_DEC_O<3> ADDR_DEC_O<2> ++ ADDR_DEC_O<1> ADDR_DEC_O<0> DCLK_I DCLK_O RCLK_I RCLK_O WCLK_I WCLK_O ++ VDD VSS +XADDR_COL_DRV<1> ADDR_COL_I<1> ADDR_COL_O<1> VDD VSS / ++ RSC_IHPSG13_CBUFX4 +XADDR_COL_DRV<0> ADDR_COL_I<0> ADDR_COL_O<0> VDD VSS / ++ RSC_IHPSG13_CBUFX4 +XADDR_DEC_DRV<7> ADDR_DEC_I<7> ADDR_DEC_O<7> VDD VSS / ++ RSC_IHPSG13_CBUFX4 +XADDR_DEC_DRV<6> ADDR_DEC_I<6> ADDR_DEC_O<6> VDD VSS / ++ RSC_IHPSG13_CBUFX4 +XADDR_DEC_DRV<5> ADDR_DEC_I<5> ADDR_DEC_O<5> VDD VSS / ++ RSC_IHPSG13_CBUFX4 +XADDR_DEC_DRV<4> ADDR_DEC_I<4> ADDR_DEC_O<4> VDD VSS / ++ RSC_IHPSG13_CBUFX4 +XADDR_DEC_DRV<3> ADDR_DEC_I<3> ADDR_DEC_O<3> VDD VSS / ++ RSC_IHPSG13_CBUFX4 +XADDR_DEC_DRV<2> ADDR_DEC_I<2> ADDR_DEC_O<2> VDD VSS / ++ RSC_IHPSG13_CBUFX4 +XADDR_DEC_DRV<1> ADDR_DEC_I<1> ADDR_DEC_O<1> VDD VSS / ++ RSC_IHPSG13_CBUFX4 +XADDR_DEC_DRV<0> ADDR_DEC_I<0> ADDR_DEC_O<0> VDD VSS / ++ RSC_IHPSG13_CBUFX4 +XDCLK_DRV DCLK_I DCLK_O VDD VSS / RSC_IHPSG13_CBUFX4 +XRCLK_DRV RCLK_I RCLK_O VDD VSS / RSC_IHPSG13_CBUFX4 +XWCLK_DRV WCLK_I WCLK_O VDD VSS / RSC_IHPSG13_CBUFX4 +.ENDS +.SUBCKT RSC_IHPSG13_WLDRVX4 A Z VDD VSS +MN1 Z net6 VSS VSS sg13_lv_nmos m=1 w=705.000n l=130.00n ng=1 nrd=0 ++ nrs=0 +MN0 net6 A VSS VSS sg13_lv_nmos m=1 w=900.0n l=130.00n ng=1 nrd=0 nrs=0 +MP1 Z net6 VDD VDD sg13_lv_pmos m=1 w=3.24u l=130.00n ng=2 nrd=0 nrs=0 +MP0 net6 A VDD VDD sg13_lv_pmos m=1 w=900.0n l=130.00n ng=1 nrd=0 nrs=0 +.ENDS +.SUBCKT RM_IHPSG13_512x8_c3_1P_WLDRV16X4 A<15> A<14> A<13> A<12> A<11> A<10> A<9> A<8> ++ A<7> A<6> A<5> A<4> A<3> A<2> A<1> A<0> Z<15> Z<14> Z<13> Z<12> Z<11> Z<10> ++ Z<9> Z<8> Z<7> Z<6> Z<5> Z<4> Z<3> Z<2> Z<1> Z<0> VDD VSS +XBUF<15> A<15> Z<15> VDD VSS / RSC_IHPSG13_WLDRVX4 +XBUF<14> A<14> Z<14> VDD VSS / RSC_IHPSG13_WLDRVX4 +XBUF<13> A<13> Z<13> VDD VSS / RSC_IHPSG13_WLDRVX4 +XBUF<12> A<12> Z<12> VDD VSS / RSC_IHPSG13_WLDRVX4 +XBUF<11> A<11> Z<11> VDD VSS / RSC_IHPSG13_WLDRVX4 +XBUF<10> A<10> Z<10> VDD VSS / RSC_IHPSG13_WLDRVX4 +XBUF<9> A<9> Z<9> VDD VSS / RSC_IHPSG13_WLDRVX4 +XBUF<8> A<8> Z<8> VDD VSS / RSC_IHPSG13_WLDRVX4 +XBUF<7> A<7> Z<7> VDD VSS / RSC_IHPSG13_WLDRVX4 +XBUF<6> A<6> Z<6> VDD VSS / RSC_IHPSG13_WLDRVX4 +XBUF<5> A<5> Z<5> VDD VSS / RSC_IHPSG13_WLDRVX4 +XBUF<4> A<4> Z<4> VDD VSS / RSC_IHPSG13_WLDRVX4 +XBUF<3> A<3> Z<3> VDD VSS / RSC_IHPSG13_WLDRVX4 +XBUF<2> A<2> Z<2> VDD VSS / RSC_IHPSG13_WLDRVX4 +XBUF<1> A<1> Z<1> VDD VSS / RSC_IHPSG13_WLDRVX4 +XBUF<0> A<0> Z<0> VDD VSS / RSC_IHPSG13_WLDRVX4 +.ENDS +.SUBCKT RSC_IHPSG13_FILLCAP8 VDD VSS +MN0 vss_r vdd_r VSS VSS sg13_lv_nmos m=1 w=4.98u l=130.00n ng=6 nrd=0 ++ nrs=0 +MP0 vdd_r vss_r VDD VDD sg13_lv_pmos m=1 w=6.48u l=385.000n ng=4 nrd=0 ++ nrs=0 +.ENDS +.SUBCKT RSC_IHPSG13_LHPQX2 CP D Q VDD VSS +MN3 QIN CPN net14 VSS sg13_lv_nmos m=1 w=480.00n l=130.00n ng=1 nrd=0 nrs=0 +MN2 net14 net10 VSS VSS sg13_lv_nmos m=1 w=480.00n l=130.00n ng=1 ++ nrd=0 nrs=0 +MN5 net21 D VSS VSS sg13_lv_nmos m=1 w=870.00n l=130.00n ng=1 nrd=0 ++ nrs=0 +MN6 QIN CP net21 VSS sg13_lv_nmos m=1 w=870.00n l=130.00n ng=1 nrd=0 nrs=0 +MN1 net10 QIN VSS VSS sg13_lv_nmos m=1 w=480.00n l=130.00n ng=1 nrd=0 ++ nrs=0 +MN0 CPN CP VSS VSS sg13_lv_nmos m=1 w=480.00n l=130.00n ng=1 nrd=0 ++ nrs=0 +MN4 Q QIN VSS VSS sg13_lv_nmos m=1 w=980.00n l=130.00n ng=1 nrd=0 nrs=0 +MP2 QIN CP net16 VDD sg13_lv_pmos m=1 w=480.00n l=130.00n ng=1 nrd=0 nrs=0 +MP0 CPN CP VDD VDD sg13_lv_pmos m=1 w=480.00n l=130.00n ng=1 nrd=0 ++ nrs=0 +MP4 Q QIN VDD VDD sg13_lv_pmos m=1 w=1.62u l=130.00n ng=1 nrd=0 nrs=0 +MP3 net10 QIN VDD VDD sg13_lv_pmos m=1 w=480.00n l=130.00n ng=1 nrd=0 ++ nrs=0 +MP1 net16 net10 VDD VDD sg13_lv_pmos m=1 w=480.00n l=130.00n ng=1 ++ nrd=0 nrs=0 +MP6 QIN CPN net20 VDD sg13_lv_pmos m=1 w=975.000n l=130.00n ng=1 nrd=0 ++ nrs=0 +MP5 net20 D VDD VDD sg13_lv_pmos m=1 w=975.000n l=130.00n ng=1 nrd=0 ++ nrs=0 +.ENDS +.SUBCKT RSC_IHPSG13_NAND2X2 A B Z VDD VSS +MP1 Z B VDD VDD sg13_lv_pmos m=1 w=1.62u l=130.00n ng=1 nrd=0 nrs=0 +MP0 Z A VDD VDD sg13_lv_pmos m=1 w=1.62u l=130.00n ng=1 nrd=0 nrs=0 +MN0 Z B net7 VSS sg13_lv_nmos m=1 w=980.00n l=130.00n ng=1 nrd=0 nrs=0 +MN1 net7 A VSS VSS sg13_lv_nmos m=1 w=980.00n l=130.00n ng=1 nrd=0 ++ nrs=0 +.ENDS +.SUBCKT RSC_IHPSG13_CINVX4 A Z VDD VSS +MN0 Z A VSS VSS sg13_lv_nmos m=1 w=1.41u l=130.00n ng=2 nrd=0 nrs=0 +MP0 Z A VDD VDD sg13_lv_pmos m=1 w=3.24u l=130.00n ng=2 nrd=0 nrs=0 +.ENDS +.SUBCKT RSC_IHPSG13_CINVX2 A Z VDD VSS +MN0 Z A VSS VSS sg13_lv_nmos m=1 w=705.000n l=130.00n ng=1 nrd=0 nrs=0 +MP0 Z A VDD VDD sg13_lv_pmos m=1 w=1.62u l=130.00n ng=1 nrd=0 nrs=0 +.ENDS +.SUBCKT RSC_IHPSG13_INVX2 A Z VDD VSS +MN0 Z A VSS VSS sg13_lv_nmos m=1 w=980.00n l=130.00n ng=1 nrd=0 nrs=0 +MP0 Z A VDD VDD sg13_lv_pmos m=1 w=1.62u l=130.00n ng=1 nrd=0 nrs=0 +.ENDS +.SUBCKT RSC_IHPSG13_NAND3X2 A B C Z VDD VSS +MP2 Z A VDD VDD sg13_lv_pmos m=1 w=1.62u l=130.00n ng=1 nrd=0 nrs=0 +MP1 Z B VDD VDD sg13_lv_pmos m=1 w=1.62u l=130.00n ng=1 nrd=0 nrs=0 +MP0 Z C VDD VDD sg13_lv_pmos m=1 w=1.62u l=130.00n ng=1 nrd=0 nrs=0 +MN1 net12 B net16 VSS sg13_lv_nmos m=1 w=980.00n l=130.00n ng=1 nrd=0 nrs=0 +MN0 Z C net12 VSS sg13_lv_nmos m=1 w=980.00n l=130.00n ng=1 nrd=0 nrs=0 +MN2 net16 A VSS VSS sg13_lv_nmos m=1 w=980.00n l=130.00n ng=1 nrd=0 ++ nrs=0 +.ENDS +.SUBCKT RSC_IHPSG13_NOR3X2 A B C Z VDD VSS +MP0 net13 A VDD VDD sg13_lv_pmos m=1 w=1.62u l=130.00n ng=1 nrd=0 nrs=0 +MP2 Z C net10 VDD sg13_lv_pmos m=1 w=1.62u l=130.00n ng=1 nrd=0 nrs=0 +MP1 net10 B net13 VDD sg13_lv_pmos m=1 w=1.62u l=130.00n ng=1 nrd=0 nrs=0 +MN1 Z B VSS VSS sg13_lv_nmos m=1 w=875.000n l=130.00n ng=1 nrd=0 nrs=0 +MN0 Z C VSS VSS sg13_lv_nmos m=1 w=875.000n l=130.00n ng=1 nrd=0 nrs=0 +MN2 Z A VSS VSS sg13_lv_nmos m=1 w=875.000n l=130.00n ng=1 nrd=0 nrs=0 +.ENDS +.SUBCKT RSC_IHPSG13_FILLCAP4 VDD VSS +MN0 vss_r vdd_r VSS VSS sg13_lv_nmos m=1 w=2.49u l=130.00n ng=3 nrd=0 ++ nrs=0 +MP0 vdd_r vss_r VDD VDD sg13_lv_pmos m=1 w=3.24u l=385.000n ng=2 nrd=0 ++ nrs=0 +.ENDS +.SUBCKT RSC_IHPSG13_MET2RES A B +R0 B A lvsres w=2.6e-07 l=6e-07 +.ENDS +.SUBCKT RM_IHPSG13_512x8_c3_1P_DEC04 ADDR<3> ADDR<2> ADDR<1> ADDR<0> CS ECLK_H_BOT ++ ECLK_H_TOP ECLK_L_BOT ECLK_L_TOP WL<15> WL<14> WL<13> WL<12> WL<11> WL<10> ++ WL<9> WL<8> WL<7> WL<6> WL<5> WL<4> WL<3> WL<2> WL<1> WL<0> VDD VSS +XLATCH<3> CS ADDR<3> PADR<3> VDD VSS / RSC_IHPSG13_LHPQX2 +XLATCH<2> CS ADDR<2> PADR<2> VDD VSS / RSC_IHPSG13_LHPQX2 +XLATCH<1> CS ADDR<1> PADR<1> VDD VSS / RSC_IHPSG13_LHPQX2 +XLATCH<0> CS ADDR<0> PADR<0> VDD VSS / RSC_IHPSG13_LHPQX2 +XI0<3> PADR<1> PADR<0> sel01<3> VDD VSS / RSC_IHPSG13_NAND2X2 +XI0<2> PADR<1> NADR<0> sel01<2> VDD VSS / RSC_IHPSG13_NAND2X2 +XI0<1> NADR<1> PADR<0> sel01<1> VDD VSS / RSC_IHPSG13_NAND2X2 +XI0<0> NADR<1> NADR<0> sel01<0> VDD VSS / RSC_IHPSG13_NAND2X2 +XI4 ECLK_L_BOT EN VDD VSS / RSC_IHPSG13_CINVX4 +XI5 ECLK_H_BOT ECLK_L_BOT VDD VSS / RSC_IHPSG13_CINVX2 +XI3<3> PADR<3> NADR<3> VDD VSS / RSC_IHPSG13_INVX2 +XI3<2> PADR<2> NADR<2> VDD VSS / RSC_IHPSG13_INVX2 +XI3<1> PADR<1> NADR<1> VDD VSS / RSC_IHPSG13_INVX2 +XI3<0> PADR<0> NADR<0> VDD VSS / RSC_IHPSG13_INVX2 +XI1<3> PADR<2> PADR<3> CS sel23<3> VDD VSS / RSC_IHPSG13_NAND3X2 +XI1<2> NADR<2> PADR<3> CS sel23<2> VDD VSS / RSC_IHPSG13_NAND3X2 +XI1<1> PADR<2> NADR<3> CS sel23<1> VDD VSS / RSC_IHPSG13_NAND3X2 +XI1<0> NADR<2> NADR<3> CS sel23<0> VDD VSS / RSC_IHPSG13_NAND3X2 +XI2<15> sel23<3> sel01<3> EN WL<15> VDD VSS / RSC_IHPSG13_NOR3X2 +XI2<14> sel23<3> sel01<2> EN WL<14> VDD VSS / RSC_IHPSG13_NOR3X2 +XI2<13> sel23<3> sel01<1> EN WL<13> VDD VSS / RSC_IHPSG13_NOR3X2 +XI2<12> sel23<3> sel01<0> EN WL<12> VDD VSS / RSC_IHPSG13_NOR3X2 +XI2<11> sel23<2> sel01<3> EN WL<11> VDD VSS / RSC_IHPSG13_NOR3X2 +XI2<10> sel23<2> sel01<2> EN WL<10> VDD VSS / RSC_IHPSG13_NOR3X2 +XI2<9> sel23<2> sel01<1> EN WL<9> VDD VSS / RSC_IHPSG13_NOR3X2 +XI2<8> sel23<2> sel01<0> EN WL<8> VDD VSS / RSC_IHPSG13_NOR3X2 +XI2<7> sel23<1> sel01<3> EN WL<7> VDD VSS / RSC_IHPSG13_NOR3X2 +XI2<6> sel23<1> sel01<2> EN WL<6> VDD VSS / RSC_IHPSG13_NOR3X2 +XI2<5> sel23<1> sel01<1> EN WL<5> VDD VSS / RSC_IHPSG13_NOR3X2 +XI2<4> sel23<1> sel01<0> EN WL<4> VDD VSS / RSC_IHPSG13_NOR3X2 +XI2<3> sel23<0> sel01<3> EN WL<3> VDD VSS / RSC_IHPSG13_NOR3X2 +XI2<2> sel23<0> sel01<2> EN WL<2> VDD VSS / RSC_IHPSG13_NOR3X2 +XI2<1> sel23<0> sel01<1> EN WL<1> VDD VSS / RSC_IHPSG13_NOR3X2 +XI2<0> sel23<0> sel01<0> EN WL<0> VDD VSS / RSC_IHPSG13_NOR3X2 +XCAPS4 VDD VSS / RSC_IHPSG13_FILLCAP4 +XI11 ECLK_L_BOT ECLK_L_TOP / RSC_IHPSG13_MET2RES +XR0 ECLK_H_BOT ECLK_H_TOP / RSC_IHPSG13_MET2RES +.ENDS +.SUBCKT RM_IHPSG13_512x8_c3_1P_ROWDEC4 ADDR_N_I<3> ADDR_N_I<2> ADDR_N_I<1> ADDR_N_I<0> ++ CS_I ECLK_I WL_O<15> WL_O<14> WL_O<13> WL_O<12> WL_O<11> WL_O<10> WL_O<9> ++ WL_O<8> WL_O<7> WL_O<6> WL_O<5> WL_O<4> WL_O<3> WL_O<2> WL_O<1> WL_O<0> ++ VDD VSS +XL2<8> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<7> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<6> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<5> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<4> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<3> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<2> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<1> VDD VSS / RSC_IHPSG13_FILLCAP8 +XSEL ADDR_N_I<3> ADDR_N_I<2> ADDR_N_I<1> ADDR_N_I<0> CS_I ECLK_I ECLK_H<1> ++ ECLK_B<0> ECLK_B<1> WL_O<15> WL_O<14> WL_O<13> WL_O<12> WL_O<11> WL_O<10> ++ WL_O<9> WL_O<8> WL_O<7> WL_O<6> WL_O<5> WL_O<4> WL_O<3> WL_O<2> WL_O<1> ++ WL_O<0> VDD VSS / RM_IHPSG13_512x8_c3_1P_DEC04 +.ENDS +.SUBCKT RSC_IHPSG13_CINVX8 A Z VDD VSS +MN0 Z A VSS VSS sg13_lv_nmos m=1 w=2.82u l=130.00n ng=4 nrd=0 nrs=0 +MP0 Z A VDD VDD sg13_lv_pmos m=1 w=6.48u l=130.00n ng=4 nrd=0 nrs=0 +.ENDS +.SUBCKT RSC_IHPSG13_DFNQMX2IX1 BE BI CN D QI QIN VDD VSS +MN15 net026 BI VSS VSS sg13_lv_nmos m=1 w=560.00n l=130.00n ng=1 nrd=0 ++ nrs=0 +MN14 MXI_OUT BE net026 VSS sg13_lv_nmos m=1 w=560.00n l=130.00n ng=1 nrd=0 ++ nrs=0 +MN1 net025 D VSS VSS sg13_lv_nmos m=1 w=560.00n l=130.00n ng=1 nrd=0 ++ nrs=0 +MN0 MXI_OUT BEN net025 VSS sg13_lv_nmos m=1 w=560.00n l=130.00n ng=1 nrd=0 ++ nrs=0 +MN10 QI CNN net21 VSS sg13_lv_nmos m=1 w=850.00n l=130.00n ng=1 nrd=0 nrs=0 +MN11 net21 QI_MS VSS VSS sg13_lv_nmos m=1 w=850.00n l=130.00n ng=1 ++ nrd=0 nrs=0 +MN7 net30 QI_MS VSS VSS sg13_lv_nmos m=1 w=480.00n l=130.00n ng=1 ++ nrd=0 nrs=0 +MN6 QIN_MS CNN net30 VSS sg13_lv_nmos m=1 w=480.00n l=130.00n ng=1 nrd=0 ++ nrs=0 +MN3 QI_MS QIN_MS VSS VSS sg13_lv_nmos m=1 w=480.00n l=130.00n ng=1 ++ nrd=0 nrs=0 +MN12 CNN CN VSS VSS sg13_lv_nmos m=1 w=495.000n l=130.00n ng=1 nrd=0 ++ nrs=0 +MN9 net37 MXI_OUT VSS VSS sg13_lv_nmos m=1 w=870.00n l=130.00n ng=1 ++ nrd=0 nrs=0 +MN8 QIN_MS CN net37 VSS sg13_lv_nmos m=1 w=870.00n l=130.00n ng=1 nrd=0 ++ nrs=0 +MN5 QI CN net25 VSS sg13_lv_nmos m=1 w=480.00n l=130.00n ng=1 nrd=0 nrs=0 +MN4 net25 QIN VSS VSS sg13_lv_nmos m=1 w=480.00n l=130.00n ng=1 nrd=0 ++ nrs=0 +MN2 QIN QI VSS VSS sg13_lv_nmos m=1 w=480.00n l=130.00n ng=1 nrd=0 ++ nrs=0 +MN13 BEN BE VSS VSS sg13_lv_nmos m=1 w=560.00n l=130.00n ng=1 nrd=0 ++ nrs=0 +MP15 MXI_OUT BEN net027 VDD sg13_lv_pmos m=1 w=985.000n l=130.00n ng=1 ++ nrd=0 nrs=0 +MP14 net027 BI VDD VDD sg13_lv_pmos m=1 w=985.000n l=130.00n ng=1 ++ nrd=0 nrs=0 +MP1 MXI_OUT BE net024 VDD sg13_lv_pmos m=1 w=985.000n l=130.00n ng=1 nrd=0 ++ nrs=0 +MP0 net024 D VDD VDD sg13_lv_pmos m=1 w=985.000n l=130.00n ng=1 nrd=0 ++ nrs=0 +MP13 BEN BE VDD VDD sg13_lv_pmos m=1 w=645.000n l=130.00n ng=1 nrd=0 ++ nrs=0 +MP6 QI_MS QIN_MS VDD VDD sg13_lv_pmos m=1 w=480.00n l=130.00n ng=1 ++ nrd=0 nrs=0 +MP3 QI CNN net27 VDD sg13_lv_pmos m=1 w=480.00n l=130.00n ng=1 nrd=0 nrs=0 +MP2 net27 QIN VDD VDD sg13_lv_pmos m=1 w=480.00n l=130.00n ng=1 nrd=0 ++ nrs=0 +MP10 net36 MXI_OUT VDD VDD sg13_lv_pmos m=1 w=975.000n l=130.00n ng=1 ++ nrd=0 nrs=0 +MP11 QIN_MS CNN net36 VDD sg13_lv_pmos m=1 w=975.000n l=130.00n ng=1 nrd=0 ++ nrs=0 +MP4 net32 QI_MS VDD VDD sg13_lv_pmos m=1 w=480.00n l=130.00n ng=1 ++ nrd=0 nrs=0 +MP5 QIN_MS CN net32 VDD sg13_lv_pmos m=1 w=480.00n l=130.00n ng=1 nrd=0 ++ nrs=0 +MP7 QIN QI VDD VDD sg13_lv_pmos m=1 w=480.00n l=130.00n ng=1 nrd=0 ++ nrs=0 +MP12 CNN CN VDD VDD sg13_lv_pmos m=1 w=480.00n l=130.00n ng=1 nrd=0 ++ nrs=0 +MP9 QI CN net19 VDD sg13_lv_pmos m=1 w=990.00n l=130.00n ng=1 nrd=0 nrs=0 +MP8 net19 QI_MS VDD VDD sg13_lv_pmos m=1 w=990.00n l=130.00n ng=1 ++ nrd=0 nrs=0 +.ENDS +.SUBCKT RM_IHPSG13_512x8_c3_1P_ROWREG4 ACLK_N_I ADDR_I<3> ADDR_I<2> ADDR_I<1> ADDR_I<0> ++ ADDR_N_O<3> ADDR_N_O<2> ADDR_N_O<1> ADDR_N_O<0> BIST_ADDR_I<3> ++ BIST_ADDR_I<2> BIST_ADDR_I<1> BIST_ADDR_I<0> BIST_EN_I VDD VSS +XINV<3> q_int<3> qn_int<3> VDD VSS / RSC_IHPSG13_CINVX2 +XINV<2> q_int<2> qn_int<2> VDD VSS / RSC_IHPSG13_CINVX2 +XINV<1> q_int<1> qn_int<1> VDD VSS / RSC_IHPSG13_CINVX2 +XINV<0> q_int<0> qn_int<0> VDD VSS / RSC_IHPSG13_CINVX2 +XDRV<3> qn_int<3> ADDR_N_O<3> VDD VSS / RSC_IHPSG13_CINVX8 +XDRV<2> qn_int<2> ADDR_N_O<2> VDD VSS / RSC_IHPSG13_CINVX8 +XDRV<1> qn_int<1> ADDR_N_O<1> VDD VSS / RSC_IHPSG13_CINVX8 +XDRV<0> qn_int<0> ADDR_N_O<0> VDD VSS / RSC_IHPSG13_CINVX8 +XDFF<3> BIST_EN_I BIST_ADDR_I<3> ACLK_N_I ADDR_I<3> q_int<3> net2<0> VDD ++ VSS / RSC_IHPSG13_DFNQMX2IX1 +XDFF<2> BIST_EN_I BIST_ADDR_I<2> ACLK_N_I ADDR_I<2> q_int<2> net2<1> VDD ++ VSS / RSC_IHPSG13_DFNQMX2IX1 +XDFF<1> BIST_EN_I BIST_ADDR_I<1> ACLK_N_I ADDR_I<1> q_int<1> net2<2> VDD ++ VSS / RSC_IHPSG13_DFNQMX2IX1 +XDFF<0> BIST_EN_I BIST_ADDR_I<0> ACLK_N_I ADDR_I<0> q_int<0> net2<3> VDD ++ VSS / RSC_IHPSG13_DFNQMX2IX1 +XI11<20> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI11<19> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI11<18> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI11<17> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI11<16> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI11<15> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI11<14> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI11<13> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI11<12> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI11<11> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI11<10> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI11<9> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI11<8> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI11<7> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI11<6> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI11<5> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI11<4> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI11<3> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI11<2> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI11<1> VDD VSS / RSC_IHPSG13_FILLCAP8 +.ENDS +.SUBCKT RSC_IHPSG13_CDLYX1 A Z VDD VSS +MN1 net010 net032 VSS VSS sg13_lv_nmos m=1 w=300.0n l=160.00n ng=1 ++ nrd=0 nrs=0 +MN2 net032 A net014 VSS sg13_lv_nmos m=1 w=300.0n l=160.00n ng=1 nrd=0 ++ nrs=0 +MN0 Z net032 net010 VSS sg13_lv_nmos m=1 w=300.0n l=160.00n ng=1 nrd=0 ++ nrs=0 +MN3 net014 A VSS VSS sg13_lv_nmos m=1 w=300.0n l=160.00n ng=1 nrd=0 ++ nrs=0 +MP1 Z net032 net07 VDD sg13_lv_pmos m=1 w=720.00n l=160.00n ng=1 nrd=0 ++ nrs=0 +MP3 net011 A VDD VDD sg13_lv_pmos m=1 w=720.00n l=160.00n ng=1 nrd=0 ++ nrs=0 +MP0 net07 net032 VDD VDD sg13_lv_pmos m=1 w=720.00n l=160.00n ng=1 ++ nrd=0 nrs=0 +MP2 net032 A net011 VDD sg13_lv_pmos m=1 w=720.00n l=160.00n ng=1 nrd=0 ++ nrs=0 +.ENDS +.SUBCKT RSC_IHPSG13_CDLYX1_DUMMY A Z VDD VSS +MN0 vss_r vdd_r VSS VSS sg13_lv_nmos m=1 w=2.49u l=300.0n ng=3 nrd=0 ++ nrs=0 +MP0 vdd_r vss_r VDD VDD sg13_lv_pmos m=1 w=3.24u l=640.00n ng=2 nrd=0 ++ nrs=0 +R0 Z A lvsres w=2.6e-07 l=6e-07 +.ENDS + +.SUBCKT RSC_IHPSG13_MX2IX1 A0 A1 S ZN VDD VSS +MP4 SN S VDD VDD sg13_lv_pmos m=1 w=645.000n l=130.00n ng=1 nrd=0 nrs=0 +MP3 ZN SN net12 VDD sg13_lv_pmos m=1 w=985.000n l=130.00n ng=1 nrd=0 nrs=0 +MP2 net12 A1 VDD VDD sg13_lv_pmos m=1 w=985.000n l=130.00n ng=1 nrd=0 ++ nrs=0 +MP1 ZN S net17 VDD sg13_lv_pmos m=1 w=985.000n l=130.00n ng=1 nrd=0 nrs=0 +MP0 net17 A0 VDD VDD sg13_lv_pmos m=1 w=985.000n l=130.00n ng=1 nrd=0 ++ nrs=0 +MN5 SN S VSS VSS sg13_lv_nmos m=1 w=480.00n l=130.00n ng=1 nrd=0 nrs=0 +MN3 net13 A1 VSS VSS sg13_lv_nmos m=1 w=480.00n l=130.00n ng=1 nrd=0 ++ nrs=0 +MN2 ZN S net13 VSS sg13_lv_nmos m=1 w=480.00n l=130.00n ng=1 nrd=0 nrs=0 +MN1 net15 A0 VSS VSS sg13_lv_nmos m=1 w=480.00n l=130.00n ng=1 nrd=0 ++ nrs=0 +MN0 ZN SN net15 VSS sg13_lv_nmos m=1 w=480.00n l=130.00n ng=1 nrd=0 nrs=0 +.ENDS +.SUBCKT RM_IHPSG13_512x8_c3_1P_DLY_MUX A SEL Z VDD VSS +XI11 net4 Z VDD VSS / RSC_IHPSG13_CINVX2 +XI8 A D<3> SEL net4 VDD VSS / RSC_IHPSG13_MX2IX1 +XI20<3> D<2> D<3> VDD VSS / RSC_IHPSG13_CDLYX1 +XI20<2> D<1> D<2> VDD VSS / RSC_IHPSG13_CDLYX1 +XI20<1> A D<1> VDD VSS / RSC_IHPSG13_CDLYX1 +.ENDS +.SUBCKT RSC_IHPSG13_DFNQX2 CN D Q VDD VSS +MN0 Q QIN_SL VSS VSS sg13_lv_nmos m=1 w=980.00n l=130.00n ng=1 nrd=0 ++ nrs=0 +MN10 QIN_SL CNN net21 VSS sg13_lv_nmos m=1 w=850.00n l=130.00n ng=1 nrd=0 ++ nrs=0 +MN11 net21 QI_MS VSS VSS sg13_lv_nmos m=1 w=850.00n l=130.00n ng=1 ++ nrd=0 nrs=0 +MN7 net30 QI_MS VSS VSS sg13_lv_nmos m=1 w=480.00n l=130.00n ng=1 ++ nrd=0 nrs=0 +MN6 QIN_MS CNN net30 VSS sg13_lv_nmos m=1 w=480.00n l=130.00n ng=1 nrd=0 ++ nrs=0 +MN3 QI_MS QIN_MS VSS VSS sg13_lv_nmos m=1 w=480.00n l=130.00n ng=1 ++ nrd=0 nrs=0 +MN12 CNN CN VSS VSS sg13_lv_nmos m=1 w=495.000n l=130.00n ng=1 nrd=0 ++ nrs=0 +MN9 net37 D VSS VSS sg13_lv_nmos m=1 w=870.00n l=130.00n ng=1 nrd=0 ++ nrs=0 +MN8 QIN_MS CN net37 VSS sg13_lv_nmos m=1 w=870.00n l=130.00n ng=1 nrd=0 ++ nrs=0 +MN5 QIN_SL CN net25 VSS sg13_lv_nmos m=1 w=480.00n l=130.00n ng=1 nrd=0 ++ nrs=0 +MN4 net25 QI_SL VSS VSS sg13_lv_nmos m=1 w=480.00n l=130.00n ng=1 ++ nrd=0 nrs=0 +MN2 QI_SL QIN_SL VSS VSS sg13_lv_nmos m=1 w=480.00n l=130.00n ng=1 ++ nrd=0 nrs=0 +MP0 Q QIN_SL VDD VDD sg13_lv_pmos m=1 w=1.62u l=130.00n ng=1 nrd=0 ++ nrs=0 +MP6 QI_MS QIN_MS VDD VDD sg13_lv_pmos m=1 w=480.00n l=130.00n ng=1 ++ nrd=0 nrs=0 +MP3 QIN_SL CNN net27 VDD sg13_lv_pmos m=1 w=480.00n l=130.00n ng=1 nrd=0 ++ nrs=0 +MP2 net27 QI_SL VDD VDD sg13_lv_pmos m=1 w=480.00n l=130.00n ng=1 ++ nrd=0 nrs=0 +MP10 net36 D VDD VDD sg13_lv_pmos m=1 w=975.000n l=130.00n ng=1 nrd=0 ++ nrs=0 +MP11 QIN_MS CNN net36 VDD sg13_lv_pmos m=1 w=975.000n l=130.00n ng=1 nrd=0 ++ nrs=0 +MP4 net32 QI_MS VDD VDD sg13_lv_pmos m=1 w=480.00n l=130.00n ng=1 ++ nrd=0 nrs=0 +MP5 QIN_MS CN net32 VDD sg13_lv_pmos m=1 w=480.00n l=130.00n ng=1 nrd=0 ++ nrs=0 +MP7 QI_SL QIN_SL VDD VDD sg13_lv_pmos m=1 w=480.00n l=130.00n ng=1 ++ nrd=0 nrs=0 +MP12 CNN CN VDD VDD sg13_lv_pmos m=1 w=480.00n l=130.00n ng=1 nrd=0 ++ nrs=0 +MP9 QIN_SL CN net19 VDD sg13_lv_pmos m=1 w=990.00n l=130.00n ng=1 nrd=0 ++ nrs=0 +MP8 net19 QI_MS VDD VDD sg13_lv_pmos m=1 w=990.00n l=130.00n ng=1 ++ nrd=0 nrs=0 +.ENDS +.SUBCKT RSC_IHPSG13_CNAND2X2 A B Z VDD VSS +MN0 Z B net6 VSS sg13_lv_nmos m=1 w=980.00n l=130.00n ng=1 nrd=0 nrs=0 +MN1 net6 A VSS VSS sg13_lv_nmos m=1 w=980.00n l=130.00n ng=1 nrd=0 ++ nrs=0 +MP1 Z B VDD VDD sg13_lv_pmos m=1 w=1.62u l=130.00n ng=1 nrd=0 nrs=0 +MP0 Z A VDD VDD sg13_lv_pmos m=1 w=1.62u l=130.00n ng=1 nrd=0 nrs=0 +.ENDS +.SUBCKT RSC_IHPSG13_CGATEPX4 CP E Q VDD VSS +MN1 net08 QIN VSS VSS sg13_lv_nmos m=1 w=480.00n l=130.00n ng=1 nrd=0 ++ nrs=0 +MN2 net019 net08 VSS VSS sg13_lv_nmos m=1 w=480.00n l=130.00n ng=1 ++ nrd=0 nrs=0 +MN3 QIN CP net019 VSS sg13_lv_nmos m=1 w=480.00n l=130.00n ng=1 nrd=0 nrs=0 +MN6 Q net015 VSS VSS sg13_lv_nmos m=1 w=1.41u l=130.00n ng=2 nrd=0 ++ nrs=0 +MN5 net015 net08 net018 VSS sg13_lv_nmos m=1 w=980.00n l=130.00n ng=1 ++ nrd=0 nrs=0 +MN8 QIN CPN net023 VSS sg13_lv_nmos m=1 w=870.00n l=130.00n ng=1 nrd=0 ++ nrs=0 +MN7 net023 E VSS VSS sg13_lv_nmos m=1 w=870.00n l=130.00n ng=1 nrd=0 ++ nrs=0 +MN4 net018 CP VSS VSS sg13_lv_nmos m=1 w=980.00n l=130.00n ng=1 nrd=0 ++ nrs=0 +MN0 CPN CP VSS VSS sg13_lv_nmos m=1 w=500.0n l=130.00n ng=1 nrd=0 nrs=0 +MP3 net08 QIN VDD VDD sg13_lv_pmos m=1 w=480.00n l=130.00n ng=1 nrd=0 ++ nrs=0 +MP2 QIN CPN net017 VDD sg13_lv_pmos m=1 w=480.00n l=130.00n ng=1 nrd=0 ++ nrs=0 +MP1 net017 net08 VDD VDD sg13_lv_pmos m=1 w=480.00n l=130.00n ng=1 ++ nrd=0 nrs=0 +MP0 CPN CP VDD VDD sg13_lv_pmos m=1 w=500.0n l=130.00n ng=1 nrd=0 nrs=0 +MP8 QIN CP net024 VDD sg13_lv_pmos m=1 w=975.000n l=130.00n ng=1 nrd=0 ++ nrs=0 +MP7 net024 E VDD VDD sg13_lv_pmos m=1 w=975.000n l=130.00n ng=1 nrd=0 ++ nrs=0 +MP4 net015 CP VDD VDD sg13_lv_pmos m=1 w=1.27u l=130.00n ng=1 nrd=0 ++ nrs=0 +MP6 Q net015 VDD VDD sg13_lv_pmos m=1 w=3.24u l=130.00n ng=2 nrd=0 ++ nrs=0 +MP5 net015 net08 VDD VDD sg13_lv_pmos m=1 w=1.27u l=130.00n ng=1 nrd=0 ++ nrs=0 +.ENDS +.SUBCKT RSC_IHPSG13_CBUFX8 A Z VDD VSS +MP0 net4 A VDD VDD sg13_lv_pmos m=1 w=3.24u l=130.00n ng=2 nrd=0 nrs=0 +MP1 Z net4 VDD VDD sg13_lv_pmos m=1 w=6.48u l=130.00n ng=4 nrd=0 nrs=0 +MN1 Z net4 VSS VSS sg13_lv_nmos m=1 w=2.82u l=130.00n ng=4 nrd=0 nrs=0 +MN0 net4 A VSS VSS sg13_lv_nmos m=1 w=1.41u l=130.00n ng=2 nrd=0 nrs=0 +.ENDS +.SUBCKT RSC_IHPSG13_CDLYX2 A Z VDD VSS +MN2 net4 A net9 VSS sg13_lv_nmos m=1 w=320.00n l=200.0n ng=1 nrd=0 nrs=0 +MN0 Z net4 VSS VSS sg13_lv_nmos m=1 w=705.000n l=130.00n ng=1 nrd=0 ++ nrs=0 +MN1 net9 A VSS VSS sg13_lv_nmos m=1 w=320.00n l=200.0n ng=1 nrd=0 nrs=0 +MP2 net4 A net10 VDD sg13_lv_pmos m=1 w=1.2u l=200.0n ng=1 nrd=0 nrs=0 +MP1 net10 A VDD VDD sg13_lv_pmos m=1 w=1.2u l=200.0n ng=1 nrd=0 nrs=0 +MP0 Z net4 VDD VDD sg13_lv_pmos m=1 w=1.62u l=130.00n ng=1 nrd=0 nrs=0 +.ENDS +.SUBCKT RSC_IHPSG13_MX2X2 A0 A1 S Z VDD VSS +MP6 Z net010 VDD VDD sg13_lv_pmos m=1 w=1.62u l=130.00n ng=1 nrd=0 ++ nrs=0 +MP4 SN S VDD VDD sg13_lv_pmos m=1 w=645.000n l=130.00n ng=1 nrd=0 nrs=0 +MP3 net010 SN net12 VDD sg13_lv_pmos m=1 w=985.000n l=130.00n ng=1 nrd=0 ++ nrs=0 +MP2 net12 A1 VDD VDD sg13_lv_pmos m=1 w=985.000n l=130.00n ng=1 nrd=0 ++ nrs=0 +MP1 net010 S net17 VDD sg13_lv_pmos m=1 w=985.000n l=130.00n ng=1 nrd=0 ++ nrs=0 +MP0 net17 A0 VDD VDD sg13_lv_pmos m=1 w=985.000n l=130.00n ng=1 nrd=0 ++ nrs=0 +MN6 Z net010 VSS VSS sg13_lv_nmos m=1 w=705.000n l=130.00n ng=1 nrd=0 ++ nrs=0 +MN5 SN S VSS VSS sg13_lv_nmos m=1 w=560.00n l=130.00n ng=1 nrd=0 nrs=0 +MN3 net13 A1 VSS VSS sg13_lv_nmos m=1 w=560.00n l=130.00n ng=1 nrd=0 ++ nrs=0 +MN2 net010 S net13 VSS sg13_lv_nmos m=1 w=560.00n l=130.00n ng=1 nrd=0 ++ nrs=0 +MN1 net15 A0 VSS VSS sg13_lv_nmos m=1 w=560.00n l=130.00n ng=1 nrd=0 ++ nrs=0 +MN0 net010 SN net15 VSS sg13_lv_nmos m=1 w=560.00n l=130.00n ng=1 nrd=0 ++ nrs=0 +.ENDS +.SUBCKT RSC_IHPSG13_AND2X2 A B Z VDD VSS +MN3 Z net6 VSS VSS sg13_lv_nmos m=1 w=980.00n l=130.00n ng=1 nrd=0 ++ nrs=0 +MN4 net9 B VSS VSS sg13_lv_nmos m=1 w=500.0n l=130.00n ng=1 nrd=0 nrs=0 +MN6 net6 A net9 VSS sg13_lv_nmos m=1 w=500.0n l=130.00n ng=1 nrd=0 nrs=0 +MP2 Z net6 VDD VDD sg13_lv_pmos m=1 w=1.62u l=130.00n ng=1 nrd=0 nrs=0 +MP0 net6 B VDD VDD sg13_lv_pmos m=1 w=860.00n l=130.00n ng=1 nrd=0 ++ nrs=0 +MP1 net6 A VDD VDD sg13_lv_pmos m=1 w=860.00n l=130.00n ng=1 nrd=0 ++ nrs=0 +.ENDS +.SUBCKT RSC_IHPSG13_TIEL Z VDD VSS +MN0 Z net2 VSS VSS sg13_lv_nmos m=1 w=480.00n l=130.00n ng=1 nrd=0 ++ nrs=0 +MP0 net2 net2 VDD VDD sg13_lv_pmos m=1 w=480.00n l=130.00n ng=1 nrd=0 ++ nrs=0 +.ENDS +.SUBCKT RSC_IHPSG13_XOR2X2 A B Z VDD VSS +MP8 net012 B net7 VDD sg13_lv_pmos m=1 w=825.000n l=130.00n ng=1 nrd=0 ++ nrs=0 +MP7 net011 net3 net012 VDD sg13_lv_pmos m=1 w=825.000n l=130.00n ng=1 ++ nrd=0 nrs=0 +MP6 Z net012 VDD VDD sg13_lv_pmos m=1 w=1.535u l=130.00n ng=1 nrd=0 ++ nrs=0 +MP2 net7 A VDD VDD sg13_lv_pmos m=1 w=825.000n l=130.00n ng=1 nrd=0 ++ nrs=0 +MP4 net011 net7 VDD VDD sg13_lv_pmos m=1 w=825.000n l=130.00n ng=1 ++ nrd=0 nrs=0 +MP5 net3 B VDD VDD sg13_lv_pmos m=1 w=580.00n l=130.00n ng=1 nrd=0 ++ nrs=0 +MN7 net012 B net011 VSS sg13_lv_nmos m=1 w=555.000n l=130.00n ng=1 nrd=0 ++ nrs=0 +MN6 net7 net3 net012 VSS sg13_lv_nmos m=1 w=555.000n l=130.00n ng=1 nrd=0 ++ nrs=0 +MN5 Z net012 VSS VSS sg13_lv_nmos m=1 w=775.000n l=130.00n ng=1 nrd=0 ++ nrs=0 +MN2 net7 A VSS VSS sg13_lv_nmos m=1 w=555.000n l=130.00n ng=1 nrd=0 ++ nrs=0 +MN4 net3 B VSS VSS sg13_lv_nmos m=1 w=480.00n l=130.00n ng=1 nrd=0 ++ nrs=0 +MN3 net011 net7 VSS VSS sg13_lv_nmos m=1 w=555.000n l=130.00n ng=1 ++ nrd=0 nrs=0 +.ENDS +.SUBCKT RSC_IHPSG13_OA12X1 A B C Z VDD VSS +MN2 net7 C VSS VSS sg13_lv_nmos m=1 w=980.00n l=130.00n ng=1 nrd=0 ++ nrs=0 +MN3 Z net17 VSS VSS sg13_lv_nmos m=1 w=500.0n l=130.00n ng=1 nrd=0 ++ nrs=0 +MN1 net17 B net7 VSS sg13_lv_nmos m=1 w=980.00n l=130.00n ng=1 nrd=0 nrs=0 +MN0 net17 A net7 VSS sg13_lv_nmos m=1 w=980.00n l=130.00n ng=1 nrd=0 nrs=0 +MP0 net24 A VDD VDD sg13_lv_pmos m=1 w=1.62u l=130.00n ng=1 nrd=0 nrs=0 +MP3 Z net17 VDD VDD sg13_lv_pmos m=1 w=905.000n l=130.00n ng=1 nrd=0 ++ nrs=0 +MP1 net17 B net24 VDD sg13_lv_pmos m=1 w=1.62u l=130.00n ng=1 nrd=0 nrs=0 +MP2 net17 C VDD VDD sg13_lv_pmos m=1 w=905.000n l=130.00n ng=1 nrd=0 ++ nrs=0 +.ENDS +.SUBCKT RM_IHPSG13_512x8_c3_1P_CTRL ACLK_N BIST_CK_I BIST_CS_I BIST_EN BIST_RE_I ++ BIST_WE_I B_TIEL_O CK_I CS_I DCLK ECLK PULSE_H PULSE_L PULSE_O RCLK RE_I ++ ROW_CS WCLK WE_I VDD VSS +XI17 ck_regs we col_we VDD VSS / RSC_IHPSG13_DFNQX2 +XI16 ck_regs re col_re VDD VSS / RSC_IHPSG13_DFNQX2 +XI18 ck_regs cs net7 VDD VSS / RSC_IHPSG13_DFNQX2 +XI71 ACLK_N net012 PULSE_O VDD VSS / RSC_IHPSG13_DFNQX2 +XI77 col_we net9 net016 VDD VSS / RSC_IHPSG13_CNAND2X2 +XI76 col_re net9 net018 VDD VSS / RSC_IHPSG13_CNAND2X2 +XI15 ck_dly WEorREandCS aclk VDD VSS / RSC_IHPSG13_CGATEPX4 +XI14 ck WEandCS DCLK VDD VSS / RSC_IHPSG13_CGATEPX4 +XI60 net7 ROW_CS VDD VSS / RSC_IHPSG13_CBUFX8 +XI73 PULSE_O net012 VDD VSS / RSC_IHPSG13_CINVX2 +XI8 net9 net8 VDD VSS / RSC_IHPSG13_CINVX2 +XI64 ck ck_dly VDD VSS / RSC_IHPSG13_CDLYX2 +XI86 CS_I BIST_CS_I BIST_EN cs VDD VSS / RSC_IHPSG13_MX2X2 +XI87 CK_I BIST_CK_I BIST_EN ck VDD VSS / RSC_IHPSG13_MX2X2 +XI85 WE_I BIST_WE_I BIST_EN we VDD VSS / RSC_IHPSG13_MX2X2 +XI84 RE_I BIST_RE_I BIST_EN re VDD VSS / RSC_IHPSG13_MX2X2 +XI22 we cs WEandCS VDD VSS / RSC_IHPSG13_AND2X2 +XBM_TIEL B_TIEL_O VDD VSS / RSC_IHPSG13_TIEL +XI48 ck_dly ck_regs VDD VSS / RSC_IHPSG13_CINVX4 +XI81 net016 WCLK VDD VSS / RSC_IHPSG13_CINVX4 +XI80 net018 RCLK VDD VSS / RSC_IHPSG13_CINVX4 +XI78 net8 net020 VDD VSS / RSC_IHPSG13_CINVX4 +XI6 PULSE_L PULSE_H net9 VDD VSS / RSC_IHPSG13_XOR2X2 +XI79 net020 ECLK VDD VSS / RSC_IHPSG13_CINVX8 +XI63 aclk ACLK_N VDD VSS / RSC_IHPSG13_CINVX8 +XI21 re we cs WEorREandCS VDD VSS / RSC_IHPSG13_OA12X1 +.ENDS +.SUBCKT RM_IHPSG13_512x8_c3_1P_COLDEC2 ACLK_N ADDR<1> ADDR<0> ADDR_COL<1> ADDR_COL<0> ++ ADDR_DEC<7> ADDR_DEC<6> ADDR_DEC<5> ADDR_DEC<4> ADDR_DEC<3> ADDR_DEC<2> ++ ADDR_DEC<1> ADDR_DEC<0> BIST_ADDR<1> BIST_ADDR<0> BIST_EN_I VDD VSS +XI14<5> VDD VSS / RSC_IHPSG13_FILLCAP4 +XI14<4> VDD VSS / RSC_IHPSG13_FILLCAP4 +XI14<3> VDD VSS / RSC_IHPSG13_FILLCAP4 +XI14<2> VDD VSS / RSC_IHPSG13_FILLCAP4 +XI14<1> VDD VSS / RSC_IHPSG13_FILLCAP4 +XDFF<1> BIST_EN_I BIST_ADDR<1> ACLK_N ADDR<1> padr_int<1> net6<0> VDD ++ VSS / RSC_IHPSG13_DFNQMX2IX1 +XDFF<0> BIST_EN_I BIST_ADDR<0> ACLK_N ADDR<0> padr_int<0> net6<1> VDD ++ VSS / RSC_IHPSG13_DFNQMX2IX1 +XI1<3> PADR<1> PADR<0> addr_n<3> VDD VSS / RSC_IHPSG13_NAND2X2 +XI1<2> PADR<1> NADR<0> addr_n<2> VDD VSS / RSC_IHPSG13_NAND2X2 +XI1<1> NADR<1> PADR<0> addr_n<1> VDD VSS / RSC_IHPSG13_NAND2X2 +XI1<0> NADR<1> NADR<0> addr_n<0> VDD VSS / RSC_IHPSG13_NAND2X2 +XI16<37> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI16<36> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI16<35> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI16<34> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI16<33> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI16<32> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI16<31> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI16<30> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI16<29> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI16<28> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI16<27> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI16<26> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI16<25> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI16<24> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI16<23> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI16<22> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI16<21> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI16<20> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI16<19> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI16<18> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI16<17> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI16<16> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI16<15> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI16<14> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI16<13> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI16<12> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI16<11> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI16<10> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI16<9> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI16<8> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI16<7> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI16<6> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI16<5> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI16<4> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI16<3> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI16<2> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI16<1> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI3<1> padr_int<1> NADR<1> VDD VSS / RSC_IHPSG13_INVX2 +XI3<0> padr_int<0> NADR<0> VDD VSS / RSC_IHPSG13_INVX2 +XI13<1> NADR<1> PADR<1> VDD VSS / RSC_IHPSG13_INVX2 +XI13<0> NADR<0> PADR<0> VDD VSS / RSC_IHPSG13_INVX2 +XI2<3> addr_n<3> ADDR_DEC<3> VDD VSS / RSC_IHPSG13_INVX2 +XI2<2> addr_n<2> ADDR_DEC<2> VDD VSS / RSC_IHPSG13_INVX2 +XI2<1> addr_n<1> ADDR_DEC<1> VDD VSS / RSC_IHPSG13_INVX2 +XI2<0> addr_n<0> ADDR_DEC<0> VDD VSS / RSC_IHPSG13_INVX2 +XI15<1> ADDR_COL<1> VDD VSS / RSC_IHPSG13_TIEL +XI15<0> ADDR_COL<0> VDD VSS / RSC_IHPSG13_TIEL +XI17<3> ADDR_DEC<7> VDD VSS / RSC_IHPSG13_TIEL +XI17<2> ADDR_DEC<6> VDD VSS / RSC_IHPSG13_TIEL +XI17<1> ADDR_DEC<5> VDD VSS / RSC_IHPSG13_TIEL +XI17<0> ADDR_DEC<4> VDD VSS / RSC_IHPSG13_TIEL +.ENDS +.SUBCKT RSC_IHPSG13_NOR2X2 A B Z VDD VSS +MP1 Z B net9 VDD sg13_lv_pmos m=1 w=1.62u l=130.00n ng=1 nrd=0 nrs=0 +MP0 net9 A VDD VDD sg13_lv_pmos m=1 w=1.62u l=130.00n ng=1 nrd=0 nrs=0 +MN0 Z B VSS VSS sg13_lv_nmos m=1 w=980.00n l=130.00n ng=1 nrd=0 nrs=0 +MN1 Z A VSS VSS sg13_lv_nmos m=1 w=980.00n l=130.00n ng=1 nrd=0 nrs=0 +.ENDS +.SUBCKT RSC_IHPSG13_CINVX4_WN A Z VDD VSS +MN0 Z A VSS VSS sg13_lv_nmos m=1 w=705.000n l=130.00n ng=1 nrd=0 nrs=0 +MP0 Z A VDD VDD sg13_lv_pmos m=1 w=3.24u l=130.00n ng=2 nrd=0 nrs=0 +.ENDS +.SUBCKT RM_IHPSG13_512x8_c3_1P_BLDRV BLC BLC_SEL BLT BLT_SEL PRE_N SEL_P WR_ONE WR_ZERO ++ VDD VSS +XCDEC SEL_P WR_ZERO BLC_PMOS_DRIVE VDD VSS / RSC_IHPSG13_NAND2X2 +XTDEC SEL_P WR_ONE BLT_PMOS_DRIVE VDD VSS / RSC_IHPSG13_NAND2X2 +MTWN BLT BLT_NMOS_DRIVE VSS VSS sg13_lv_nmos m=1 w=4.82u l=130.00n ++ ng=2 nrd=0 nrs=0 +MCWN BLC BLC_NMOS_DRIVE VSS VSS sg13_lv_nmos m=1 w=4.82u l=130.00n ++ ng=2 nrd=0 nrs=0 +MCWP BLC BLC_PMOS_DRIVE VDD VDD sg13_lv_pmos m=1 w=1.5u l=130.00n ng=1 ++ nrd=0 nrs=0 +MTWP BLT BLT_PMOS_DRIVE VDD VDD sg13_lv_pmos m=1 w=1.5u l=130.00n ng=1 ++ nrd=0 nrs=0 +MTSP BLT_SEL SEL_N BLT VDD sg13_lv_pmos m=1 w=1.5u l=130.00n ng=1 nrd=0 ++ nrs=0 +MTPR BLT PRE_N VDD VDD sg13_lv_pmos m=1 w=3.000u l=130.00n ng=2 nrd=0 ++ nrs=0 +MCSP BLC_SEL SEL_N BLC VDD sg13_lv_pmos m=1 w=1.5u l=130.00n ng=1 nrd=0 ++ nrs=0 +MCPR BLC PRE_N VDD VDD sg13_lv_pmos m=1 w=3.000u l=130.00n ng=2 nrd=0 ++ nrs=0 +XI86 SEL_P SEL_N VDD VSS / RSC_IHPSG13_INVX2 +XTINV BLC_PMOS_DRIVE BLT_NMOS_DRIVE VDD VSS / RSC_IHPSG13_INVX2 +XCINV BLT_PMOS_DRIVE BLC_NMOS_DRIVE VDD VSS / RSC_IHPSG13_INVX2 +.ENDS +.SUBCKT RSC_IHPSG13_TIEH Z VDD VSS +MN0 net2 net2 VSS VSS sg13_lv_nmos m=1 w=480.00n l=130.00n ng=1 nrd=0 ++ nrs=0 +MP0 Z net2 VDD VDD sg13_lv_pmos m=1 w=480.00n l=130.00n ng=1 nrd=0 ++ nrs=0 +.ENDS +.SUBCKT RSC_IHPSG13_MET3RES A B +R0 B A lvsres w=2.6e-07 l=6e-07 +.ENDS +.SUBCKT RSC_IHPSG13_DFPQD_MSAFFX2 CP DN DP QN QP VDD VSS +MN12 SN RN DIFFP VSS sg13_lv_nmos m=1 w=2.4u l=200.0n ng=2 nrd=0 nrs=0 +MN13 TAIL CP VSS VSS sg13_lv_nmos m=1 w=2.4u l=130.00n ng=2 nrd=0 nrs=0 +MN9 DIFFP DP TAIL VSS sg13_lv_nmos m=1 w=2.4u l=200.0n ng=2 nrd=0 nrs=0 +MN10 DIFFN DN TAIL VSS sg13_lv_nmos m=1 w=2.4u l=200.0n ng=2 nrd=0 nrs=0 +MN11 RN SN DIFFN VSS sg13_lv_nmos m=1 w=2.4u l=200.0n ng=2 nrd=0 nrs=0 +MN19 net33 SN VSS VSS sg13_lv_nmos m=1 w=980.00n l=130.00n ng=1 nrd=0 ++ nrs=0 +MN20 QN QP net37 VSS sg13_lv_nmos m=1 w=980.00n l=130.00n ng=1 nrd=0 nrs=0 +MN18 net37 RN VSS VSS sg13_lv_nmos m=1 w=980.00n l=130.00n ng=1 nrd=0 ++ nrs=0 +MN17 QP QN net33 VSS sg13_lv_nmos m=1 w=980.00n l=130.00n ng=1 nrd=0 nrs=0 +MP15 SN RN VDD VDD sg13_lv_pmos m=1 w=800.0n l=130.00n ng=1 nrd=0 nrs=0 +MP16 RN CP VDD VDD sg13_lv_pmos m=1 w=800.0n l=130.00n ng=1 nrd=0 nrs=0 +MP14 DIFFP CP VDD VDD sg13_lv_pmos m=1 w=800.0n l=130.00n ng=1 nrd=0 ++ nrs=0 +MP12 RN SN VDD VDD sg13_lv_pmos m=1 w=800.0n l=130.00n ng=1 nrd=0 nrs=0 +MP13 DIFFN CP VDD VDD sg13_lv_pmos m=1 w=800.0n l=130.00n ng=1 nrd=0 ++ nrs=0 +MP11 SN CP VDD VDD sg13_lv_pmos m=1 w=800.0n l=130.00n ng=1 nrd=0 nrs=0 +MP19 QN QP VDD VDD sg13_lv_pmos m=1 w=900.0n l=130.00n ng=1 nrd=0 nrs=0 +MP20 QP SN VDD VDD sg13_lv_pmos m=1 w=1.8u l=130.00n ng=2 nrd=0 nrs=0 +MP18 QN RN VDD VDD sg13_lv_pmos m=1 w=1.8u l=130.00n ng=2 nrd=0 nrs=0 +MP17 QP QN VDD VDD sg13_lv_pmos m=1 w=900.0n l=130.00n ng=1 nrd=0 nrs=0 +.ENDS +.SUBCKT RSC_IHPSG13_CBUFX2 A Z VDD VSS +MN1 Z net4 VSS VSS sg13_lv_nmos m=1 w=705.000n l=130.00n ng=1 nrd=0 ++ nrs=0 +MN0 net4 A VSS VSS sg13_lv_nmos m=1 w=540.00n l=130.00n ng=1 nrd=0 ++ nrs=0 +MP1 Z net4 VDD VDD sg13_lv_pmos m=1 w=1.62u l=130.00n ng=1 nrd=0 nrs=0 +MP0 net4 A VDD VDD sg13_lv_pmos m=1 w=1.1u l=130.00n ng=1 nrd=0 nrs=0 +.ENDS +.SUBCKT RSC_IHPSG13_INVX4 A Z VDD VSS +MN0 Z A VSS VSS sg13_lv_nmos m=1 w=1.96u l=130.00n ng=2 nrd=0 nrs=0 +MP0 Z A VDD VDD sg13_lv_pmos m=1 w=3.24u l=130.00n ng=2 nrd=0 nrs=0 +.ENDS +.SUBCKT RM_IHPSG13_512x8_c3_1P_COLCTRL2 A_ADDR_DEC<3> A_ADDR_DEC<2> A_ADDR_DEC<1> ++ A_ADDR_DEC<0> A_BIST_BM_I A_BIST_DW_I A_BIST_EN_I A_BLC<3> A_BLC<2> A_BLC<1> ++ A_BLC<0> A_BLT<3> A_BLT<2> A_BLT<1> A_BLT<0> A_BM_I A_DCLK_B_L A_DCLK_B_R ++ A_DCLK_L A_DCLK_R A_DR_O A_DW_I A_RCLK_B_L A_RCLK_B_R A_RCLK_L A_RCLK_R ++ A_TIEH_O A_WCLK_B_L A_WCLK_B_R A_WCLK_L A_WCLK_R VDD VSS +XA_DREG A_BIST_EN_I A_BIST_DW_I A_DCLK_B_L A_DW_I A_DI_R net22 VDD VSS ++ / RSC_IHPSG13_DFNQMX2IX1 +XA_BREG A_BIST_EN_I A_BIST_BM_I A_DCLK_B_L A_BM_I A_BM_R net23 VDD VSS ++ / RSC_IHPSG13_DFNQMX2IX1 +XA_CAPS<5> VDD VSS / RSC_IHPSG13_FILLCAP4 +XA_CAPS<4> VDD VSS / RSC_IHPSG13_FILLCAP4 +XA_CAPS<3> VDD VSS / RSC_IHPSG13_FILLCAP4 +XA_CAPS<2> VDD VSS / RSC_IHPSG13_FILLCAP4 +XA_CAPS<1> VDD VSS / RSC_IHPSG13_FILLCAP4 +XA_I80 A_WCLK_B_R A_RCLK_B_R net21 VDD VSS / RSC_IHPSG13_AND2X2 +XA_I75 A_DI_R A_DO_WRITE_P A_WR_ONE VDD VSS / RSC_IHPSG13_AND2X2 +XA_I76 A_DI_N A_DO_WRITE_P A_WR_ZERO VDD VSS / RSC_IHPSG13_AND2X2 +XA_I44 A_WCLK_B_R A_BM_N A_DO_WRITE_P VDD VSS / RSC_IHPSG13_NOR2X2 +XA_I81 net21 A_PRE_N VDD VSS / RSC_IHPSG13_CINVX4_WN +XA_BLTMUX<3> A_BLC<3> A_BLC_SEL A_BLT<3> A_BLT_SEL A_PRE_N A_ADDR_DEC<3> ++ A_WR_ONE A_WR_ZERO VDD VSS / RM_IHPSG13_512x8_c3_1P_BLDRV +XA_BLTMUX<2> A_BLC<2> A_BLC_SEL A_BLT<2> A_BLT_SEL A_PRE_N A_ADDR_DEC<2> ++ A_WR_ONE A_WR_ZERO VDD VSS / RM_IHPSG13_512x8_c3_1P_BLDRV +XA_BLTMUX<1> A_BLC<1> A_BLC_SEL A_BLT<1> A_BLT_SEL A_PRE_N A_ADDR_DEC<1> ++ A_WR_ONE A_WR_ZERO VDD VSS / RM_IHPSG13_512x8_c3_1P_BLDRV +XA_BLTMUX<0> A_BLC<0> A_BLC_SEL A_BLT<0> A_BLT_SEL A_PRE_N A_ADDR_DEC<0> ++ A_WR_ONE A_WR_ZERO VDD VSS / RM_IHPSG13_512x8_c3_1P_BLDRV +XA_BM_TIEH A_TIEH_O VDD VSS / RSC_IHPSG13_TIEH +XA_I89 A_DCLK_B_L A_DCLK_B_R / RSC_IHPSG13_MET3RES +XA_I88 A_DCLK_L A_DCLK_R / RSC_IHPSG13_MET3RES +XA_I87 A_WCLK_L A_WCLK_R / RSC_IHPSG13_MET3RES +XA_I91 A_RCLK_B_R A_RCLK_B_L / RSC_IHPSG13_MET3RES +XA_R2 A_RCLK_R A_RCLK_L / RSC_IHPSG13_MET3RES +XA_I90 A_WCLK_B_R A_WCLK_B_L / RSC_IHPSG13_MET3RES +XA_ISENSE A_SAE A_BLC_SEL A_BLT_SEL net19 net20 VDD VSS / ++ RSC_IHPSG13_DFPQD_MSAFFX2 +XA_I78 A_RCLK_B_R A_SAE VDD VSS / RSC_IHPSG13_CBUFX2 +XA_I83 A_BM_R A_BM_N VDD VSS / RSC_IHPSG13_INVX2 +XA_I49 A_DI_R A_DI_N VDD VSS / RSC_IHPSG13_INVX2 +XA_I51 net19 A_DR_O VDD VSS / RSC_IHPSG13_INVX4 +XA_I69 A_DCLK_L A_DCLK_B_L VDD VSS / RSC_IHPSG13_CINVX2 +XA_I50 A_WCLK_L A_WCLK_B_R VDD VSS / RSC_IHPSG13_CINVX2 +XA_EBUF A_RCLK_R A_RCLK_B_R VDD VSS / RSC_IHPSG13_CINVX2 +.ENDS +.SUBCKT RM_IHPSG13_512x8_c3_1P_COLDRV13_FILL4 VDD VSS +XI0<9> VDD VSS / RSC_IHPSG13_FILLCAP4 +XI0<8> VDD VSS / RSC_IHPSG13_FILLCAP4 +XI0<7> VDD VSS / RSC_IHPSG13_FILLCAP4 +XI0<6> VDD VSS / RSC_IHPSG13_FILLCAP4 +XI0<5> VDD VSS / RSC_IHPSG13_FILLCAP4 +XI0<4> VDD VSS / RSC_IHPSG13_FILLCAP4 +XI0<3> VDD VSS / RSC_IHPSG13_FILLCAP4 +XI0<2> VDD VSS / RSC_IHPSG13_FILLCAP4 +XI0<1> VDD VSS / RSC_IHPSG13_FILLCAP4 +.ENDS +.SUBCKT RM_IHPSG13_512x8_c3_1P_COLDRV13_FILL4C2 VDD VSS +XI0<2> VDD VSS / RSC_IHPSG13_FILLCAP4 +XI0<1> VDD VSS / RSC_IHPSG13_FILLCAP4 +.ENDS + + +.SUBCKT RM_IHPSG13_512x8_c3_1P_COLDEC4 ACLK_N ADDR<3> ADDR<2> ADDR<1> ADDR<0> ++ ADDR_COL<1> ADDR_COL<0> ADDR_DEC<7> ADDR_DEC<6> ADDR_DEC<5> ADDR_DEC<4> ++ ADDR_DEC<3> ADDR_DEC<2> ADDR_DEC<1> ADDR_DEC<0> BIST_ADDR<3> BIST_ADDR<2> ++ BIST_ADDR<1> BIST_ADDR<0> BIST_EN_I VDD VSS +XI15 ADDR_COL<1> VDD VSS / RSC_IHPSG13_TIEL +XI14 addr_int ADDR_COL<0> VDD VSS / RSC_IHPSG13_CBUFX2 +XDFF<3> BIST_EN_I BIST_ADDR<3> ACLK_N ADDR<3> addr_int net7<0> VDD VSS ++ / RSC_IHPSG13_DFNQMX2IX1 +XDFF<2> BIST_EN_I BIST_ADDR<2> ACLK_N ADDR<2> padr_int<2> net7<1> VDD ++ VSS / RSC_IHPSG13_DFNQMX2IX1 +XDFF<1> BIST_EN_I BIST_ADDR<1> ACLK_N ADDR<1> padr_int<1> net7<2> VDD ++ VSS / RSC_IHPSG13_DFNQMX2IX1 +XDFF<0> BIST_EN_I BIST_ADDR<0> ACLK_N ADDR<0> padr_int<0> net7<3> VDD ++ VSS / RSC_IHPSG13_DFNQMX2IX1 +XI1<7> PADR<0> PADR<1> PADR<2> addr_n<7> VDD VSS / RSC_IHPSG13_NAND3X2 +XI1<6> NADR<0> PADR<1> PADR<2> addr_n<6> VDD VSS / RSC_IHPSG13_NAND3X2 +XI1<5> PADR<0> NADR<1> PADR<2> addr_n<5> VDD VSS / RSC_IHPSG13_NAND3X2 +XI1<4> NADR<0> NADR<1> PADR<2> addr_n<4> VDD VSS / RSC_IHPSG13_NAND3X2 +XI1<3> PADR<0> PADR<1> NADR<2> addr_n<3> VDD VSS / RSC_IHPSG13_NAND3X2 +XI1<2> NADR<0> PADR<1> NADR<2> addr_n<2> VDD VSS / RSC_IHPSG13_NAND3X2 +XI1<1> PADR<0> NADR<1> NADR<2> addr_n<1> VDD VSS / RSC_IHPSG13_NAND3X2 +XI1<0> NADR<0> NADR<1> NADR<2> addr_n<0> VDD VSS / RSC_IHPSG13_NAND3X2 +XI13<2> NADR<2> PADR<2> VDD VSS / RSC_IHPSG13_INVX2 +XI13<1> NADR<1> PADR<1> VDD VSS / RSC_IHPSG13_INVX2 +XI13<0> NADR<0> PADR<0> VDD VSS / RSC_IHPSG13_INVX2 +XI3<2> padr_int<2> NADR<2> VDD VSS / RSC_IHPSG13_INVX2 +XI3<1> padr_int<1> NADR<1> VDD VSS / RSC_IHPSG13_INVX2 +XI3<0> padr_int<0> NADR<0> VDD VSS / RSC_IHPSG13_INVX2 +XI2<7> addr_n<7> ADDR_DEC<7> VDD VSS / RSC_IHPSG13_INVX2 +XI2<6> addr_n<6> ADDR_DEC<6> VDD VSS / RSC_IHPSG13_INVX2 +XI2<5> addr_n<5> ADDR_DEC<5> VDD VSS / RSC_IHPSG13_INVX2 +XI2<4> addr_n<4> ADDR_DEC<4> VDD VSS / RSC_IHPSG13_INVX2 +XI2<3> addr_n<3> ADDR_DEC<3> VDD VSS / RSC_IHPSG13_INVX2 +XI2<2> addr_n<2> ADDR_DEC<2> VDD VSS / RSC_IHPSG13_INVX2 +XI2<1> addr_n<1> ADDR_DEC<1> VDD VSS / RSC_IHPSG13_INVX2 +XI2<0> addr_n<0> ADDR_DEC<0> VDD VSS / RSC_IHPSG13_INVX2 +XI16<3> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI16<2> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI16<1> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI17<2> VDD VSS / RSC_IHPSG13_FILLCAP4 +XI17<1> VDD VSS / RSC_IHPSG13_FILLCAP4 +.ENDS +.SUBCKT RSC_IHPSG13_AND2X4 A B Z VDD VSS +MN3 Z net6 VSS VSS sg13_lv_nmos m=1 w=1.96u l=130.00n ng=2 nrd=0 nrs=0 +MN4 net9 B VSS VSS sg13_lv_nmos m=1 w=500.0n l=130.00n ng=1 nrd=0 nrs=0 +MN6 net6 A net9 VSS sg13_lv_nmos m=1 w=500.0n l=130.00n ng=1 nrd=0 nrs=0 +MP2 Z net6 VDD VDD sg13_lv_pmos m=1 w=3.24u l=130.00n ng=2 nrd=0 nrs=0 +MP0 net6 B VDD VDD sg13_lv_pmos m=1 w=860.00n l=130.00n ng=1 nrd=0 ++ nrs=0 +MP1 net6 A VDD VDD sg13_lv_pmos m=1 w=860.00n l=130.00n ng=1 nrd=0 ++ nrs=0 +.ENDS +.SUBCKT RM_IHPSG13_512x8_c3_1P_COLCTRL4 A_ADDR_COL A_ADDR_DEC<7> A_ADDR_DEC<6> ++ A_ADDR_DEC<5> A_ADDR_DEC<4> A_ADDR_DEC<3> A_ADDR_DEC<2> A_ADDR_DEC<1> ++ A_ADDR_DEC<0> A_BIST_BM_I A_BIST_DW_I A_BIST_EN_I A_BLC<15> A_BLC<14> ++ A_BLC<13> A_BLC<12> A_BLC<11> A_BLC<10> A_BLC<9> A_BLC<8> A_BLC<7> A_BLC<6> ++ A_BLC<5> A_BLC<4> A_BLC<3> A_BLC<2> A_BLC<1> A_BLC<0> A_BLT<15> A_BLT<14> ++ A_BLT<13> A_BLT<12> A_BLT<11> A_BLT<10> A_BLT<9> A_BLT<8> A_BLT<7> A_BLT<6> ++ A_BLT<5> A_BLT<4> A_BLT<3> A_BLT<2> A_BLT<1> A_BLT<0> A_BM_I A_DCLK_B_L ++ A_DCLK_B_R A_DCLK_L A_DCLK_R A_DR_O A_DW_I A_RCLK_B_L A_RCLK_B_R A_RCLK_L ++ A_RCLK_R A_TIEH_O A_WCLK_B_L A_WCLK_B_R A_WCLK_L A_WCLK_R VDD VSS +XA_I80 A_WCLK_B_L A_RCLK_B_L net21 VDD VSS / RSC_IHPSG13_AND2X2 +XA_I76 A_DO_WRITE_P A_DI_N A_WR_ZERO VDD VSS / RSC_IHPSG13_AND2X4 +XA_I75 A_DI_R A_DO_WRITE_P A_WR_ONE VDD VSS / RSC_IHPSG13_AND2X4 +XA_CAPS<8> VDD VSS / RSC_IHPSG13_FILLCAP4 +XA_CAPS<7> VDD VSS / RSC_IHPSG13_FILLCAP4 +XA_CAPS<6> VDD VSS / RSC_IHPSG13_FILLCAP4 +XA_CAPS<5> VDD VSS / RSC_IHPSG13_FILLCAP4 +XA_CAPS<4> VDD VSS / RSC_IHPSG13_FILLCAP4 +XA_CAPS<3> VDD VSS / RSC_IHPSG13_FILLCAP4 +XA_CAPS<2> VDD VSS / RSC_IHPSG13_FILLCAP4 +XA_CAPS<1> VDD VSS / RSC_IHPSG13_FILLCAP4 +XA_I69 A_DCLK_L A_DCLK_B_L VDD VSS / RSC_IHPSG13_CINVX4 +XA_I50 A_WCLK_L A_WCLK_B_L VDD VSS / RSC_IHPSG13_CINVX4 +XA_EBUF A_RCLK_L A_RCLK_B_L VDD VSS / RSC_IHPSG13_CINVX4 +XA_INV<1> A_N0 A_P0 VDD VSS / RSC_IHPSG13_CINVX4 +XA_INV<0> A_ADDR_COL A_N0 VDD VSS / RSC_IHPSG13_CINVX4 +XA_I81<1> net21 A_PRE_N VDD VSS / RSC_IHPSG13_CINVX4_WN +XA_I81<0> net21 A_PRE_N VDD VSS / RSC_IHPSG13_CINVX4_WN +XA_BLTMUX<15> A_BLC<15> A_BLC_SEL A_BLT<15> A_BLT_SEL A_PRE_N A_SEL_P<15> ++ A_WR_ONE A_WR_ZERO VDD VSS / RM_IHPSG13_512x8_c3_1P_BLDRV +XA_BLTMUX<14> A_BLC<14> A_BLC_SEL A_BLT<14> A_BLT_SEL A_PRE_N A_SEL_P<14> ++ A_WR_ONE A_WR_ZERO VDD VSS / RM_IHPSG13_512x8_c3_1P_BLDRV +XA_BLTMUX<13> A_BLC<13> A_BLC_SEL A_BLT<13> A_BLT_SEL A_PRE_N A_SEL_P<13> ++ A_WR_ONE A_WR_ZERO VDD VSS / RM_IHPSG13_512x8_c3_1P_BLDRV +XA_BLTMUX<12> A_BLC<12> A_BLC_SEL A_BLT<12> A_BLT_SEL A_PRE_N A_SEL_P<12> ++ A_WR_ONE A_WR_ZERO VDD VSS / RM_IHPSG13_512x8_c3_1P_BLDRV +XA_BLTMUX<11> A_BLC<11> A_BLC_SEL A_BLT<11> A_BLT_SEL A_PRE_N A_SEL_P<11> ++ A_WR_ONE A_WR_ZERO VDD VSS / RM_IHPSG13_512x8_c3_1P_BLDRV +XA_BLTMUX<10> A_BLC<10> A_BLC_SEL A_BLT<10> A_BLT_SEL A_PRE_N A_SEL_P<10> ++ A_WR_ONE A_WR_ZERO VDD VSS / RM_IHPSG13_512x8_c3_1P_BLDRV +XA_BLTMUX<9> A_BLC<9> A_BLC_SEL A_BLT<9> A_BLT_SEL A_PRE_N A_SEL_P<9> A_WR_ONE ++ A_WR_ZERO VDD VSS / RM_IHPSG13_512x8_c3_1P_BLDRV +XA_BLTMUX<8> A_BLC<8> A_BLC_SEL A_BLT<8> A_BLT_SEL A_PRE_N A_SEL_P<8> A_WR_ONE ++ A_WR_ZERO VDD VSS / RM_IHPSG13_512x8_c3_1P_BLDRV +XA_BLTMUX<7> A_BLC<7> A_BLC_SEL A_BLT<7> A_BLT_SEL A_PRE_N A_SEL_P<7> A_WR_ONE ++ A_WR_ZERO VDD VSS / RM_IHPSG13_512x8_c3_1P_BLDRV +XA_BLTMUX<6> A_BLC<6> A_BLC_SEL A_BLT<6> A_BLT_SEL A_PRE_N A_SEL_P<6> A_WR_ONE ++ A_WR_ZERO VDD VSS / RM_IHPSG13_512x8_c3_1P_BLDRV +XA_BLTMUX<5> A_BLC<5> A_BLC_SEL A_BLT<5> A_BLT_SEL A_PRE_N A_SEL_P<5> A_WR_ONE ++ A_WR_ZERO VDD VSS / RM_IHPSG13_512x8_c3_1P_BLDRV +XA_BLTMUX<4> A_BLC<4> A_BLC_SEL A_BLT<4> A_BLT_SEL A_PRE_N A_SEL_P<4> A_WR_ONE ++ A_WR_ZERO VDD VSS / RM_IHPSG13_512x8_c3_1P_BLDRV +XA_BLTMUX<3> A_BLC<3> A_BLC_SEL A_BLT<3> A_BLT_SEL A_PRE_N A_SEL_P<3> A_WR_ONE ++ A_WR_ZERO VDD VSS / RM_IHPSG13_512x8_c3_1P_BLDRV +XA_BLTMUX<2> A_BLC<2> A_BLC_SEL A_BLT<2> A_BLT_SEL A_PRE_N A_SEL_P<2> A_WR_ONE ++ A_WR_ZERO VDD VSS / RM_IHPSG13_512x8_c3_1P_BLDRV +XA_BLTMUX<1> A_BLC<1> A_BLC_SEL A_BLT<1> A_BLT_SEL A_PRE_N A_SEL_P<1> A_WR_ONE ++ A_WR_ZERO VDD VSS / RM_IHPSG13_512x8_c3_1P_BLDRV +XA_BLTMUX<0> A_BLC<0> A_BLC_SEL A_BLT<0> A_BLT_SEL A_PRE_N A_SEL_P<0> A_WR_ONE ++ A_WR_ZERO VDD VSS / RM_IHPSG13_512x8_c3_1P_BLDRV +XA_R2 A_RCLK_L A_RCLK_R / RSC_IHPSG13_MET3RES +XA_I87 A_WCLK_L A_WCLK_R / RSC_IHPSG13_MET3RES +XA_I88 A_DCLK_L A_DCLK_R / RSC_IHPSG13_MET3RES +XA_I89 A_DCLK_B_L A_DCLK_B_R / RSC_IHPSG13_MET3RES +XA_I90 A_WCLK_B_L A_WCLK_B_R / RSC_IHPSG13_MET3RES +XA_I91 A_RCLK_B_L A_RCLK_B_R / RSC_IHPSG13_MET3RES +XA_ISENSE A_SAE A_BLC_SEL A_BLT_SEL net19 net20 VDD VSS / ++ RSC_IHPSG13_DFPQD_MSAFFX2 +XA_I51 net19 A_DR_O VDD VSS / RSC_IHPSG13_INVX4 +XA_I78 A_RCLK_B_L A_SAE VDD VSS / RSC_IHPSG13_CBUFX2 +XA_DREG A_BIST_EN_I A_BIST_DW_I A_DCLK_B_L A_DW_I A_DI_R net22 VDD VSS ++ / RSC_IHPSG13_DFNQMX2IX1 +XA_BREG A_BIST_EN_I A_BIST_BM_I A_DCLK_B_L A_BM_I A_BM_R net24 VDD VSS ++ / RSC_IHPSG13_DFNQMX2IX1 +XA_DEC3INV<15> net23<0> A_SEL_P<15> VDD VSS / RSC_IHPSG13_INVX2 +XA_DEC3INV<14> net23<1> A_SEL_P<14> VDD VSS / RSC_IHPSG13_INVX2 +XA_DEC3INV<13> net23<2> A_SEL_P<13> VDD VSS / RSC_IHPSG13_INVX2 +XA_DEC3INV<12> net23<3> A_SEL_P<12> VDD VSS / RSC_IHPSG13_INVX2 +XA_DEC3INV<11> net23<4> A_SEL_P<11> VDD VSS / RSC_IHPSG13_INVX2 +XA_DEC3INV<10> net23<5> A_SEL_P<10> VDD VSS / RSC_IHPSG13_INVX2 +XA_DEC3INV<9> net23<6> A_SEL_P<9> VDD VSS / RSC_IHPSG13_INVX2 +XA_DEC3INV<8> net23<7> A_SEL_P<8> VDD VSS / RSC_IHPSG13_INVX2 +XA_DEC3INV<7> net23<8> A_SEL_P<7> VDD VSS / RSC_IHPSG13_INVX2 +XA_DEC3INV<6> net23<9> A_SEL_P<6> VDD VSS / RSC_IHPSG13_INVX2 +XA_DEC3INV<5> net23<10> A_SEL_P<5> VDD VSS / RSC_IHPSG13_INVX2 +XA_DEC3INV<4> net23<11> A_SEL_P<4> VDD VSS / RSC_IHPSG13_INVX2 +XA_DEC3INV<3> net23<12> A_SEL_P<3> VDD VSS / RSC_IHPSG13_INVX2 +XA_DEC3INV<2> net23<13> A_SEL_P<2> VDD VSS / RSC_IHPSG13_INVX2 +XA_DEC3INV<1> net23<14> A_SEL_P<1> VDD VSS / RSC_IHPSG13_INVX2 +XA_DEC3INV<0> net23<15> A_SEL_P<0> VDD VSS / RSC_IHPSG13_INVX2 +XA_I83 A_BM_R A_BM_N VDD VSS / RSC_IHPSG13_INVX2 +XA_I49 A_DI_R A_DI_N VDD VSS / RSC_IHPSG13_INVX2 +XA_I70<4> VDD VSS / RSC_IHPSG13_FILLCAP8 +XA_I70<3> VDD VSS / RSC_IHPSG13_FILLCAP8 +XA_I70<2> VDD VSS / RSC_IHPSG13_FILLCAP8 +XA_I70<1> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI73<14> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI73<13> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI73<12> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI73<11> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI73<10> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI73<9> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI73<8> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI73<7> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI73<6> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI73<5> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI73<4> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI73<3> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI73<2> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI73<1> VDD VSS / RSC_IHPSG13_FILLCAP8 +XA_I44 A_BM_N A_WCLK_B_L A_DO_WRITE_P VDD VSS / RSC_IHPSG13_NOR2X2 +XA_DEC3<15> A_P0 A_ADDR_DEC<7> net23<0> VDD VSS / RSC_IHPSG13_NAND2X2 +XA_DEC3<14> A_P0 A_ADDR_DEC<6> net23<1> VDD VSS / RSC_IHPSG13_NAND2X2 +XA_DEC3<13> A_P0 A_ADDR_DEC<5> net23<2> VDD VSS / RSC_IHPSG13_NAND2X2 +XA_DEC3<12> A_P0 A_ADDR_DEC<4> net23<3> VDD VSS / RSC_IHPSG13_NAND2X2 +XA_DEC3<11> A_P0 A_ADDR_DEC<3> net23<4> VDD VSS / RSC_IHPSG13_NAND2X2 +XA_DEC3<10> A_P0 A_ADDR_DEC<2> net23<5> VDD VSS / RSC_IHPSG13_NAND2X2 +XA_DEC3<9> A_P0 A_ADDR_DEC<1> net23<6> VDD VSS / RSC_IHPSG13_NAND2X2 +XA_DEC3<8> A_P0 A_ADDR_DEC<0> net23<7> VDD VSS / RSC_IHPSG13_NAND2X2 +XA_DEC3<7> A_N0 A_ADDR_DEC<7> net23<8> VDD VSS / RSC_IHPSG13_NAND2X2 +XA_DEC3<6> A_N0 A_ADDR_DEC<6> net23<9> VDD VSS / RSC_IHPSG13_NAND2X2 +XA_DEC3<5> A_N0 A_ADDR_DEC<5> net23<10> VDD VSS / RSC_IHPSG13_NAND2X2 +XA_DEC3<4> A_N0 A_ADDR_DEC<4> net23<11> VDD VSS / RSC_IHPSG13_NAND2X2 +XA_DEC3<3> A_N0 A_ADDR_DEC<3> net23<12> VDD VSS / RSC_IHPSG13_NAND2X2 +XA_DEC3<2> A_N0 A_ADDR_DEC<2> net23<13> VDD VSS / RSC_IHPSG13_NAND2X2 +XA_DEC3<1> A_N0 A_ADDR_DEC<1> net23<14> VDD VSS / RSC_IHPSG13_NAND2X2 +XA_DEC3<0> A_N0 A_ADDR_DEC<0> net23<15> VDD VSS / RSC_IHPSG13_NAND2X2 +XA_BM_TIEH A_TIEH_O VDD VSS / RSC_IHPSG13_TIEH +.ENDS + + +.SUBCKT RM_IHPSG13_512x8_c3_1P_COLDEC3 ACLK_N ADDR<2> ADDR<1> ADDR<0> ADDR_COL<1> ++ ADDR_COL<0> ADDR_DEC<7> ADDR_DEC<6> ADDR_DEC<5> ADDR_DEC<4> ADDR_DEC<3> ++ ADDR_DEC<2> ADDR_DEC<1> ADDR_DEC<0> BIST_ADDR<2> BIST_ADDR<1> BIST_ADDR<0> ++ BIST_EN_I VDD VSS +XI15<1> ADDR_COL<1> VDD VSS / RSC_IHPSG13_TIEL +XI15<0> ADDR_COL<0> VDD VSS / RSC_IHPSG13_TIEL +XI1<7> PADR<0> PADR<1> PADR<2> addr_n<7> VDD VSS / RSC_IHPSG13_NAND3X2 +XI1<6> NADR<0> PADR<1> PADR<2> addr_n<6> VDD VSS / RSC_IHPSG13_NAND3X2 +XI1<5> PADR<0> NADR<1> PADR<2> addr_n<5> VDD VSS / RSC_IHPSG13_NAND3X2 +XI1<4> NADR<0> NADR<1> PADR<2> addr_n<4> VDD VSS / RSC_IHPSG13_NAND3X2 +XI1<3> PADR<0> PADR<1> NADR<2> addr_n<3> VDD VSS / RSC_IHPSG13_NAND3X2 +XI1<2> NADR<0> PADR<1> NADR<2> addr_n<2> VDD VSS / RSC_IHPSG13_NAND3X2 +XI1<1> PADR<0> NADR<1> NADR<2> addr_n<1> VDD VSS / RSC_IHPSG13_NAND3X2 +XI1<0> NADR<0> NADR<1> NADR<2> addr_n<0> VDD VSS / RSC_IHPSG13_NAND3X2 +XDFF<2> BIST_EN_I BIST_ADDR<2> ACLK_N ADDR<2> padr_int<2> net6<0> VDD ++ VSS / RSC_IHPSG13_DFNQMX2IX1 +XDFF<1> BIST_EN_I BIST_ADDR<1> ACLK_N ADDR<1> padr_int<1> net6<1> VDD ++ VSS / RSC_IHPSG13_DFNQMX2IX1 +XDFF<0> BIST_EN_I BIST_ADDR<0> ACLK_N ADDR<0> padr_int<0> net6<2> VDD ++ VSS / RSC_IHPSG13_DFNQMX2IX1 +XI17<2> VDD VSS / RSC_IHPSG13_FILLCAP4 +XI17<1> VDD VSS / RSC_IHPSG13_FILLCAP4 +XI13<2> NADR<2> PADR<2> VDD VSS / RSC_IHPSG13_INVX2 +XI13<1> NADR<1> PADR<1> VDD VSS / RSC_IHPSG13_INVX2 +XI13<0> NADR<0> PADR<0> VDD VSS / RSC_IHPSG13_INVX2 +XI3<2> padr_int<2> NADR<2> VDD VSS / RSC_IHPSG13_INVX2 +XI3<1> padr_int<1> NADR<1> VDD VSS / RSC_IHPSG13_INVX2 +XI3<0> padr_int<0> NADR<0> VDD VSS / RSC_IHPSG13_INVX2 +XI2<7> addr_n<7> ADDR_DEC<7> VDD VSS / RSC_IHPSG13_INVX2 +XI2<6> addr_n<6> ADDR_DEC<6> VDD VSS / RSC_IHPSG13_INVX2 +XI2<5> addr_n<5> ADDR_DEC<5> VDD VSS / RSC_IHPSG13_INVX2 +XI2<4> addr_n<4> ADDR_DEC<4> VDD VSS / RSC_IHPSG13_INVX2 +XI2<3> addr_n<3> ADDR_DEC<3> VDD VSS / RSC_IHPSG13_INVX2 +XI2<2> addr_n<2> ADDR_DEC<2> VDD VSS / RSC_IHPSG13_INVX2 +XI2<1> addr_n<1> ADDR_DEC<1> VDD VSS / RSC_IHPSG13_INVX2 +XI2<0> addr_n<0> ADDR_DEC<0> VDD VSS / RSC_IHPSG13_INVX2 +XI16<6> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI16<5> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI16<4> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI16<3> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI16<2> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI16<1> VDD VSS / RSC_IHPSG13_FILLCAP8 +.ENDS +.SUBCKT RM_IHPSG13_512x8_c3_1P_COLCTRL3 A_ADDR_DEC<7> A_ADDR_DEC<6> A_ADDR_DEC<5> ++ A_ADDR_DEC<4> A_ADDR_DEC<3> A_ADDR_DEC<2> A_ADDR_DEC<1> A_ADDR_DEC<0> ++ A_BIST_BM_I A_BIST_DW_I A_BIST_EN_I A_BLC<7> A_BLC<6> A_BLC<5> A_BLC<4> ++ A_BLC<3> A_BLC<2> A_BLC<1> A_BLC<0> A_BLT<7> A_BLT<6> A_BLT<5> A_BLT<4> ++ A_BLT<3> A_BLT<2> A_BLT<1> A_BLT<0> A_BM_I A_DCLK_B_L A_DCLK_B_R A_DCLK_L ++ A_DCLK_R A_DR_O A_DW_I A_RCLK_B_L A_RCLK_B_R A_RCLK_L A_RCLK_R A_TIEH_O ++ A_WCLK_B_L A_WCLK_B_R A_WCLK_L A_WCLK_R VDD VSS +XA_DREG A_BIST_EN_I A_BIST_DW_I A_DCLK_B_L A_DW_I A_DI_R net22 VDD VSS ++ / RSC_IHPSG13_DFNQMX2IX1 +XA_BREG A_BIST_EN_I A_BIST_BM_I A_DCLK_B_R A_BM_I A_BM_R net23 VDD VSS ++ / RSC_IHPSG13_DFNQMX2IX1 +XA_I70<8> VDD VSS / RSC_IHPSG13_FILLCAP8 +XA_I70<7> VDD VSS / RSC_IHPSG13_FILLCAP8 +XA_I70<6> VDD VSS / RSC_IHPSG13_FILLCAP8 +XA_I70<5> VDD VSS / RSC_IHPSG13_FILLCAP8 +XA_I70<4> VDD VSS / RSC_IHPSG13_FILLCAP8 +XA_I70<3> VDD VSS / RSC_IHPSG13_FILLCAP8 +XA_I70<2> VDD VSS / RSC_IHPSG13_FILLCAP8 +XA_I70<1> VDD VSS / RSC_IHPSG13_FILLCAP8 +XA_I51 net19 A_DR_O VDD VSS / RSC_IHPSG13_INVX4 +XA_I44 A_BM_N A_WCLK_B_R A_DO_WRITE_P VDD VSS / RSC_IHPSG13_NOR2X2 +XA_BM_TIEH A_TIEH_O VDD VSS / RSC_IHPSG13_TIEH +XA_BLTMUX<7> A_BLC<7> A_BLC_SEL A_BLT<7> A_BLT_SEL A_PRE_N A_ADDR_DEC<7> ++ A_WR_ONE A_WR_ZERO VDD VSS / RM_IHPSG13_512x8_c3_1P_BLDRV +XA_BLTMUX<6> A_BLC<6> A_BLC_SEL A_BLT<6> A_BLT_SEL A_PRE_N A_ADDR_DEC<6> ++ A_WR_ONE A_WR_ZERO VDD VSS / RM_IHPSG13_512x8_c3_1P_BLDRV +XA_BLTMUX<5> A_BLC<5> A_BLC_SEL A_BLT<5> A_BLT_SEL A_PRE_N A_ADDR_DEC<5> ++ A_WR_ONE A_WR_ZERO VDD VSS / RM_IHPSG13_512x8_c3_1P_BLDRV +XA_BLTMUX<4> A_BLC<4> A_BLC_SEL A_BLT<4> A_BLT_SEL A_PRE_N A_ADDR_DEC<4> ++ A_WR_ONE A_WR_ZERO VDD VSS / RM_IHPSG13_512x8_c3_1P_BLDRV +XA_BLTMUX<3> A_BLC<3> A_BLC_SEL A_BLT<3> A_BLT_SEL A_PRE_N A_ADDR_DEC<3> ++ A_WR_ONE A_WR_ZERO VDD VSS / RM_IHPSG13_512x8_c3_1P_BLDRV +XA_BLTMUX<2> A_BLC<2> A_BLC_SEL A_BLT<2> A_BLT_SEL A_PRE_N A_ADDR_DEC<2> ++ A_WR_ONE A_WR_ZERO VDD VSS / RM_IHPSG13_512x8_c3_1P_BLDRV +XA_BLTMUX<1> A_BLC<1> A_BLC_SEL A_BLT<1> A_BLT_SEL A_PRE_N A_ADDR_DEC<1> ++ A_WR_ONE A_WR_ZERO VDD VSS / RM_IHPSG13_512x8_c3_1P_BLDRV +XA_BLTMUX<0> A_BLC<0> A_BLC_SEL A_BLT<0> A_BLT_SEL A_PRE_N A_ADDR_DEC<0> ++ A_WR_ONE A_WR_ZERO VDD VSS / RM_IHPSG13_512x8_c3_1P_BLDRV +XA_I49 A_DI_R A_DI_N VDD VSS / RSC_IHPSG13_INVX2 +XA_I83 A_BM_R A_BM_N VDD VSS / RSC_IHPSG13_INVX2 +XA_I69 A_DCLK_L A_DCLK_B_L VDD VSS / RSC_IHPSG13_CINVX2 +XA_I50 A_WCLK_L A_WCLK_B_L VDD VSS / RSC_IHPSG13_CINVX2 +XA_EBUF A_RCLK_L A_RCLK_B_L VDD VSS / RSC_IHPSG13_CINVX2 +XA_I78 A_RCLK_B_L A_SAE VDD VSS / RSC_IHPSG13_CBUFX2 +XA_I88 A_DCLK_L A_DCLK_R / RSC_IHPSG13_MET3RES +XA_I87 A_WCLK_L A_WCLK_R / RSC_IHPSG13_MET3RES +XA_R2 A_RCLK_L A_RCLK_R / RSC_IHPSG13_MET3RES +XA_I91 A_RCLK_B_L A_RCLK_B_R / RSC_IHPSG13_MET3RES +XA_I90 A_WCLK_B_L A_WCLK_B_R / RSC_IHPSG13_MET3RES +XA_I89 A_DCLK_B_L A_DCLK_B_R / RSC_IHPSG13_MET3RES +XA_I80 A_WCLK_B_R A_RCLK_B_R net21 VDD VSS / RSC_IHPSG13_AND2X2 +XA_I76 A_DI_N A_DO_WRITE_P A_WR_ZERO VDD VSS / RSC_IHPSG13_AND2X2 +XA_I75 A_DI_R A_DO_WRITE_P A_WR_ONE VDD VSS / RSC_IHPSG13_AND2X2 +XA_ISENSE A_SAE A_BLC_SEL A_BLT_SEL net19 net20 VDD VSS / ++ RSC_IHPSG13_DFPQD_MSAFFX2 +XA_I81 net21 A_PRE_N VDD VSS / RSC_IHPSG13_CINVX4_WN +XA_CAPS<5> VDD VSS / RSC_IHPSG13_FILLCAP4 +XA_CAPS<4> VDD VSS / RSC_IHPSG13_FILLCAP4 +XA_CAPS<3> VDD VSS / RSC_IHPSG13_FILLCAP4 +XA_CAPS<2> VDD VSS / RSC_IHPSG13_FILLCAP4 +XA_CAPS<1> VDD VSS / RSC_IHPSG13_FILLCAP4 +.ENDS + +.SUBCKT RM_IHPSG13_512x8_c3_2P_BITKIT_16x2_CORNER VDD_CORE VSS +XI16 VDD_CORE VSS VDD_CORE VSS / ++ RM_IHPSG13_512x8_c3_1P_BITKIT_CORNER +.ENDS +.SUBCKT RM_IHPSG13_512x8_c3_2P_BITKIT_EDGE_LR A_WL B_WL NW PW VDD VSS +MN1 VSS A_WL VSS VSS sg13_lv_nmos m=1 w=300.0n l=130.00n ng=1 nrd=0 nrs=0 +MN0 VSS B_WL VSS VSS sg13_lv_nmos m=1 w=300.0n l=130.00n ng=1 nrd=0 nrs=0 +.ENDS +.SUBCKT RM_IHPSG13_512x8_c3_2P_BITKIT_16x2_EDGE_LR A_WL<15> A_WL<14> A_WL<13> A_WL<12> ++ A_WL<11> A_WL<10> A_WL<9> A_WL<8> A_WL<7> A_WL<6> A_WL<5> A_WL<4> A_WL<3> ++ A_WL<2> A_WL<1> A_WL<0> B_WL<15> B_WL<14> B_WL<13> B_WL<12> B_WL<11> ++ B_WL<10> B_WL<9> B_WL<8> B_WL<7> B_WL<6> B_WL<5> B_WL<4> B_WL<3> B_WL<2> ++ B_WL<1> B_WL<0> VDD_CORE VSS +XI0<15> A_WL<15> B_WL<15> VDD_CORE VSS VDD_CORE VSS ++ / RM_IHPSG13_512x8_c3_2P_BITKIT_EDGE_LR +XI0<14> A_WL<14> B_WL<14> VDD_CORE VSS VDD_CORE VSS ++ / RM_IHPSG13_512x8_c3_2P_BITKIT_EDGE_LR +XI0<13> A_WL<13> B_WL<13> VDD_CORE VSS VDD_CORE VSS ++ / RM_IHPSG13_512x8_c3_2P_BITKIT_EDGE_LR +XI0<12> A_WL<12> B_WL<12> VDD_CORE VSS VDD_CORE VSS ++ / RM_IHPSG13_512x8_c3_2P_BITKIT_EDGE_LR +XI0<11> A_WL<11> B_WL<11> VDD_CORE VSS VDD_CORE VSS ++ / RM_IHPSG13_512x8_c3_2P_BITKIT_EDGE_LR +XI0<10> A_WL<10> B_WL<10> VDD_CORE VSS VDD_CORE VSS ++ / RM_IHPSG13_512x8_c3_2P_BITKIT_EDGE_LR +XI0<9> A_WL<9> B_WL<9> VDD_CORE VSS VDD_CORE VSS / ++ RM_IHPSG13_512x8_c3_2P_BITKIT_EDGE_LR +XI0<8> A_WL<8> B_WL<8> VDD_CORE VSS VDD_CORE VSS / ++ RM_IHPSG13_512x8_c3_2P_BITKIT_EDGE_LR +XI0<7> A_WL<7> B_WL<7> VDD_CORE VSS VDD_CORE VSS / ++ RM_IHPSG13_512x8_c3_2P_BITKIT_EDGE_LR +XI0<6> A_WL<6> B_WL<6> VDD_CORE VSS VDD_CORE VSS / ++ RM_IHPSG13_512x8_c3_2P_BITKIT_EDGE_LR +XI0<5> A_WL<5> B_WL<5> VDD_CORE VSS VDD_CORE VSS / ++ RM_IHPSG13_512x8_c3_2P_BITKIT_EDGE_LR +XI0<4> A_WL<4> B_WL<4> VDD_CORE VSS VDD_CORE VSS / ++ RM_IHPSG13_512x8_c3_2P_BITKIT_EDGE_LR +XI0<3> A_WL<3> B_WL<3> VDD_CORE VSS VDD_CORE VSS / ++ RM_IHPSG13_512x8_c3_2P_BITKIT_EDGE_LR +XI0<2> A_WL<2> B_WL<2> VDD_CORE VSS VDD_CORE VSS / ++ RM_IHPSG13_512x8_c3_2P_BITKIT_EDGE_LR +XI0<1> A_WL<1> B_WL<1> VDD_CORE VSS VDD_CORE VSS / ++ RM_IHPSG13_512x8_c3_2P_BITKIT_EDGE_LR +XI0<0> A_WL<0> B_WL<0> VDD_CORE VSS VDD_CORE VSS / ++ RM_IHPSG13_512x8_c3_2P_BITKIT_EDGE_LR +.ENDS +.SUBCKT RM_IHPSG13_512x8_c3_2P_BITKIT_CELL A_BLC_BOT A_BLC_TOP A_BLT_BOT A_BLT_TOP ++ A_LWL A_RWL B_BLC_BOT B_BLC_TOP B_BLT_BOT B_BLT_TOP B_LWL B_RWL NW PW VDD VSS +MN5 NC B_RWL B_BLC_BOT PW sg13_lv_nmos m=1 w=300.0n l=130.00n ng=1 nrd=0 nrs=0 +MN4 B_BLT_BOT B_LWL NT PW sg13_lv_nmos m=1 w=300.0n l=130.00n ng=1 nrd=0 nrs=0 +MN0 NC NT VSS PW sg13_lv_nmos m=1 w=600.0n l=130.00n ng=2 nrd=0 nrs=0 +MN1 NT NC VSS PW sg13_lv_nmos m=1 w=600.0n l=130.00n ng=2 nrd=0 nrs=0 +MN3 NC A_RWL A_BLC_TOP PW sg13_lv_nmos m=1 w=300.0n l=130.00n ng=1 nrd=0 nrs=0 +MN2 A_BLT_TOP A_LWL NT PW sg13_lv_nmos m=1 w=300.0n l=130.00n ng=1 nrd=0 nrs=0 +MP1 NT NC VDD NW sg13_lv_pmos m=1 w=150.00n l=130.00n ng=1 nrd=0 nrs=0 +MP0 NC NT VDD NW sg13_lv_pmos m=1 w=150.00n l=130.00n ng=1 nrd=0 nrs=0 +R5 B_RWL B_LWL lvsres w=2.6e-07 l=6e-07 +R4 B_BLC_BOT B_BLC_TOP lvsres w=2.6e-07 l=6e-07 +R3 B_BLT_BOT B_BLT_TOP lvsres w=2.6e-07 l=6e-07 +R1 A_BLC_BOT A_BLC_TOP lvsres w=2.6e-07 l=6e-07 +R0 A_BLT_BOT A_BLT_TOP lvsres w=2.6e-07 l=6e-07 +R2 A_RWL A_LWL lvsres w=2.6e-07 l=6e-07 +.ENDS +.SUBCKT RM_IHPSG13_512x8_c3_2P_BITKIT_16x2_SRAM A_BLC_BOT<1> A_BLC_BOT<0> A_BLC_TOP<1> ++ A_BLC_TOP<0> A_BLT_BOT<1> A_BLT_BOT<0> A_BLT_TOP<1> A_BLT_TOP<0> A_LWL<15> ++ A_LWL<14> A_LWL<13> A_LWL<12> A_LWL<11> A_LWL<10> A_LWL<9> A_LWL<8> A_LWL<7> ++ A_LWL<6> A_LWL<5> A_LWL<4> A_LWL<3> A_LWL<2> A_LWL<1> A_LWL<0> A_RWL<15> ++ A_RWL<14> A_RWL<13> A_RWL<12> A_RWL<11> A_RWL<10> A_RWL<9> A_RWL<8> A_RWL<7> ++ A_RWL<6> A_RWL<5> A_RWL<4> A_RWL<3> A_RWL<2> A_RWL<1> A_RWL<0> B_BLC_BOT<1> ++ B_BLC_BOT<0> B_BLC_TOP<1> B_BLC_TOP<0> B_BLT_BOT<1> B_BLT_BOT<0> ++ B_BLT_TOP<1> B_BLT_TOP<0> B_LWL<15> B_LWL<14> B_LWL<13> B_LWL<12> B_LWL<11> ++ B_LWL<10> B_LWL<9> B_LWL<8> B_LWL<7> B_LWL<6> B_LWL<5> B_LWL<4> B_LWL<3> ++ B_LWL<2> B_LWL<1> B_LWL<0> B_RWL<15> B_RWL<14> B_RWL<13> B_RWL<12> B_RWL<11> ++ B_RWL<10> B_RWL<9> B_RWL<8> B_RWL<7> B_RWL<6> B_RWL<5> B_RWL<4> B_RWL<3> ++ B_RWL<2> B_RWL<1> B_RWL<0> VDD_CORE VSS +XCELL<31> A_BLC_TOP<1> A_RBLC<15> A_BLT_TOP<1> A_RBLT<15> A_XWL<15> A_RWL<15> ++ B_BLC_TOP<1> B_RBLC<15> B_BLT_TOP<1> B_RBLT<15> B_XWL<15> B_RWL<15> ++ VDD_CORE VSS VDD_CORE VSS / ++ RM_IHPSG13_512x8_c3_2P_BITKIT_CELL +XCELL<30> A_RBLC<14> A_RBLC<15> A_RBLT<14> A_RBLT<15> A_XWL<14> A_RWL<14> ++ B_RBLC<14> B_RBLC<15> B_RBLT<14> B_RBLT<15> B_XWL<14> B_RWL<14> VDD_CORE ++ VSS VDD_CORE VSS / RM_IHPSG13_512x8_c3_2P_BITKIT_CELL +XCELL<29> A_RBLC<14> A_RBLC<13> A_RBLT<14> A_RBLT<13> A_XWL<13> A_RWL<13> ++ B_RBLC<14> B_RBLC<13> B_RBLT<14> B_RBLT<13> B_XWL<13> B_RWL<13> VDD_CORE ++ VSS VDD_CORE VSS / RM_IHPSG13_512x8_c3_2P_BITKIT_CELL +XCELL<28> A_RBLC<12> A_RBLC<13> A_RBLT<12> A_RBLT<13> A_XWL<12> A_RWL<12> ++ B_RBLC<12> B_RBLC<13> B_RBLT<12> B_RBLT<13> B_XWL<12> B_RWL<12> VDD_CORE ++ VSS VDD_CORE VSS / RM_IHPSG13_512x8_c3_2P_BITKIT_CELL +XCELL<27> A_RBLC<12> A_RBLC<11> A_RBLT<12> A_RBLT<11> A_XWL<11> A_RWL<11> ++ B_RBLC<12> B_RBLC<11> B_RBLT<12> B_RBLT<11> B_XWL<11> B_RWL<11> VDD_CORE ++ VSS VDD_CORE VSS / RM_IHPSG13_512x8_c3_2P_BITKIT_CELL +XCELL<26> A_RBLC<10> A_RBLC<11> A_RBLT<10> A_RBLT<11> A_XWL<10> A_RWL<10> ++ B_RBLC<10> B_RBLC<11> B_RBLT<10> B_RBLT<11> B_XWL<10> B_RWL<10> VDD_CORE ++ VSS VDD_CORE VSS / RM_IHPSG13_512x8_c3_2P_BITKIT_CELL +XCELL<25> A_RBLC<10> A_RBLC<9> A_RBLT<10> A_RBLT<9> A_XWL<9> A_RWL<9> ++ B_RBLC<10> B_RBLC<9> B_RBLT<10> B_RBLT<9> B_XWL<9> B_RWL<9> VDD_CORE ++ VSS VDD_CORE VSS / RM_IHPSG13_512x8_c3_2P_BITKIT_CELL +XCELL<24> A_RBLC<8> A_RBLC<9> A_RBLT<8> A_RBLT<9> A_XWL<8> A_RWL<8> B_RBLC<8> ++ B_RBLC<9> B_RBLT<8> B_RBLT<9> B_XWL<8> B_RWL<8> VDD_CORE VSS ++ VDD_CORE VSS / RM_IHPSG13_512x8_c3_2P_BITKIT_CELL +XCELL<23> A_RBLC<8> A_RBLC<7> A_RBLT<8> A_RBLT<7> A_XWL<7> A_RWL<7> B_RBLC<8> ++ B_RBLC<7> B_RBLT<8> B_RBLT<7> B_XWL<7> B_RWL<7> VDD_CORE VSS ++ VDD_CORE VSS / RM_IHPSG13_512x8_c3_2P_BITKIT_CELL +XCELL<22> A_RBLC<6> A_RBLC<7> A_RBLT<6> A_RBLT<7> A_XWL<6> A_RWL<6> B_RBLC<6> ++ B_RBLC<7> B_RBLT<6> B_RBLT<7> B_XWL<6> B_RWL<6> VDD_CORE VSS ++ VDD_CORE VSS / RM_IHPSG13_512x8_c3_2P_BITKIT_CELL +XCELL<21> A_RBLC<6> A_RBLC<5> A_RBLT<6> A_RBLT<5> A_XWL<5> A_RWL<5> B_RBLC<6> ++ B_RBLC<5> B_RBLT<6> B_RBLT<5> B_XWL<5> B_RWL<5> VDD_CORE VSS ++ VDD_CORE VSS / RM_IHPSG13_512x8_c3_2P_BITKIT_CELL +XCELL<20> A_RBLC<4> A_RBLC<5> A_RBLT<4> A_RBLT<5> A_XWL<4> A_RWL<4> B_RBLC<4> ++ B_RBLC<5> B_RBLT<4> B_RBLT<5> B_XWL<4> B_RWL<4> VDD_CORE VSS ++ VDD_CORE VSS / RM_IHPSG13_512x8_c3_2P_BITKIT_CELL +XCELL<19> A_RBLC<4> A_RBLC<3> A_RBLT<4> A_RBLT<3> A_XWL<3> A_RWL<3> B_RBLC<4> ++ B_RBLC<3> B_RBLT<4> B_RBLT<3> B_XWL<3> B_RWL<3> VDD_CORE VSS ++ VDD_CORE VSS / RM_IHPSG13_512x8_c3_2P_BITKIT_CELL +XCELL<18> A_RBLC<2> A_RBLC<3> A_RBLT<2> A_RBLT<3> A_XWL<2> A_RWL<2> B_RBLC<2> ++ B_RBLC<3> B_RBLT<2> B_RBLT<3> B_XWL<2> B_RWL<2> VDD_CORE VSS ++ VDD_CORE VSS / RM_IHPSG13_512x8_c3_2P_BITKIT_CELL +XCELL<17> A_RBLC<2> A_RBLC<1> A_RBLT<2> A_RBLT<1> A_XWL<1> A_RWL<1> B_RBLC<2> ++ B_RBLC<1> B_RBLT<2> B_RBLT<1> B_XWL<1> B_RWL<1> VDD_CORE VSS ++ VDD_CORE VSS / RM_IHPSG13_512x8_c3_2P_BITKIT_CELL +XCELL<16> A_BLC_BOT<1> A_RBLC<1> A_BLT_BOT<1> A_RBLT<1> A_XWL<0> A_RWL<0> ++ B_BLC_BOT<1> B_RBLC<1> B_BLT_BOT<1> B_RBLT<1> B_XWL<0> B_RWL<0> VDD_CORE ++ VSS VDD_CORE VSS / RM_IHPSG13_512x8_c3_2P_BITKIT_CELL +XCELL<15> A_BLC_TOP<0> A_LBLC<15> A_BLT_TOP<0> A_LBLT<15> A_LWL<15> A_XWL<15> ++ B_BLC_TOP<0> B_LBLC<15> B_BLT_TOP<0> B_LBLT<15> B_LWL<15> B_XWL<15> ++ VDD_CORE VSS VDD_CORE VSS / ++ RM_IHPSG13_512x8_c3_2P_BITKIT_CELL +XCELL<14> A_LBLC<14> A_LBLC<15> A_LBLT<14> A_LBLT<15> A_LWL<14> A_XWL<14> ++ B_LBLC<14> B_LBLC<15> B_LBLT<14> B_LBLT<15> B_LWL<14> B_XWL<14> VDD_CORE ++ VSS VDD_CORE VSS / RM_IHPSG13_512x8_c3_2P_BITKIT_CELL +XCELL<13> A_LBLC<14> A_LBLC<13> A_LBLT<14> A_LBLT<13> A_LWL<13> A_XWL<13> ++ B_LBLC<14> B_LBLC<13> B_LBLT<14> B_LBLT<13> B_LWL<13> B_XWL<13> VDD_CORE ++ VSS VDD_CORE VSS / RM_IHPSG13_512x8_c3_2P_BITKIT_CELL +XCELL<12> A_LBLC<12> A_LBLC<13> A_LBLT<12> A_LBLT<13> A_LWL<12> A_XWL<12> ++ B_LBLC<12> B_LBLC<13> B_LBLT<12> B_LBLT<13> B_LWL<12> B_XWL<12> VDD_CORE ++ VSS VDD_CORE VSS / RM_IHPSG13_512x8_c3_2P_BITKIT_CELL +XCELL<11> A_LBLC<12> A_LBLC<11> A_LBLT<12> A_LBLT<11> A_LWL<11> A_XWL<11> ++ B_LBLC<12> B_LBLC<11> B_LBLT<12> B_LBLT<11> B_LWL<11> B_XWL<11> VDD_CORE ++ VSS VDD_CORE VSS / RM_IHPSG13_512x8_c3_2P_BITKIT_CELL +XCELL<10> A_LBLC<10> A_LBLC<11> A_LBLT<10> A_LBLT<11> A_LWL<10> A_XWL<10> ++ B_LBLC<10> B_LBLC<11> B_LBLT<10> B_LBLT<11> B_LWL<10> B_XWL<10> VDD_CORE ++ VSS VDD_CORE VSS / RM_IHPSG13_512x8_c3_2P_BITKIT_CELL +XCELL<9> A_LBLC<10> A_LBLC<9> A_LBLT<10> A_LBLT<9> A_LWL<9> A_XWL<9> ++ B_LBLC<10> B_LBLC<9> B_LBLT<10> B_LBLT<9> B_LWL<9> B_XWL<9> VDD_CORE ++ VSS VDD_CORE VSS / RM_IHPSG13_512x8_c3_2P_BITKIT_CELL +XCELL<8> A_LBLC<8> A_LBLC<9> A_LBLT<8> A_LBLT<9> A_LWL<8> A_XWL<8> B_LBLC<8> ++ B_LBLC<9> B_LBLT<8> B_LBLT<9> B_LWL<8> B_XWL<8> VDD_CORE VSS ++ VDD_CORE VSS / RM_IHPSG13_512x8_c3_2P_BITKIT_CELL +XCELL<7> A_LBLC<8> A_LBLC<7> A_LBLT<8> A_LBLT<7> A_LWL<7> A_XWL<7> B_LBLC<8> ++ B_LBLC<7> B_LBLT<8> B_LBLT<7> B_LWL<7> B_XWL<7> VDD_CORE VSS ++ VDD_CORE VSS / RM_IHPSG13_512x8_c3_2P_BITKIT_CELL +XCELL<6> A_LBLC<6> A_LBLC<7> A_LBLT<6> A_LBLT<7> A_LWL<6> A_XWL<6> B_LBLC<6> ++ B_LBLC<7> B_LBLT<6> B_LBLT<7> B_LWL<6> B_XWL<6> VDD_CORE VSS ++ VDD_CORE VSS / RM_IHPSG13_512x8_c3_2P_BITKIT_CELL +XCELL<5> A_LBLC<6> A_LBLC<5> A_LBLT<6> A_LBLT<5> A_LWL<5> A_XWL<5> B_LBLC<6> ++ B_LBLC<5> B_LBLT<6> B_LBLT<5> B_LWL<5> B_XWL<5> VDD_CORE VSS ++ VDD_CORE VSS / RM_IHPSG13_512x8_c3_2P_BITKIT_CELL +XCELL<4> A_LBLC<4> A_LBLC<5> A_LBLT<4> A_LBLT<5> A_LWL<4> A_XWL<4> B_LBLC<4> ++ B_LBLC<5> B_LBLT<4> B_LBLT<5> B_LWL<4> B_XWL<4> VDD_CORE VSS ++ VDD_CORE VSS / RM_IHPSG13_512x8_c3_2P_BITKIT_CELL +XCELL<3> A_LBLC<4> A_LBLC<3> A_LBLT<4> A_LBLT<3> A_LWL<3> A_XWL<3> B_LBLC<4> ++ B_LBLC<3> B_LBLT<4> B_LBLT<3> B_LWL<3> B_XWL<3> VDD_CORE VSS ++ VDD_CORE VSS / RM_IHPSG13_512x8_c3_2P_BITKIT_CELL +XCELL<2> A_LBLC<2> A_LBLC<3> A_LBLT<2> A_LBLT<3> A_LWL<2> A_XWL<2> B_LBLC<2> ++ B_LBLC<3> B_LBLT<2> B_LBLT<3> B_LWL<2> B_XWL<2> VDD_CORE VSS ++ VDD_CORE VSS / RM_IHPSG13_512x8_c3_2P_BITKIT_CELL +XCELL<1> A_LBLC<2> A_LBLC<1> A_LBLT<2> A_LBLT<1> A_LWL<1> A_XWL<1> B_LBLC<2> ++ B_LBLC<1> B_LBLT<2> B_LBLT<1> B_LWL<1> B_XWL<1> VDD_CORE VSS ++ VDD_CORE VSS / RM_IHPSG13_512x8_c3_2P_BITKIT_CELL +XCELL<0> A_BLC_BOT<0> A_LBLC<1> A_BLT_BOT<0> A_LBLT<1> A_LWL<0> A_XWL<0> ++ B_BLC_BOT<0> B_LBLC<1> B_BLT_BOT<0> B_LBLT<1> B_LWL<0> B_XWL<0> VDD_CORE ++ VSS VDD_CORE VSS / RM_IHPSG13_512x8_c3_2P_BITKIT_CELL +.ENDS +.SUBCKT RM_IHPSG13_512x8_c3_2P_BITKIT_EDGE_TB A_BLC A_BLT B_BLC B_BLT NW PW VDD VSS +.ENDS +.SUBCKT RM_IHPSG13_512x8_c3_2P_BITKIT_16x2_EDGE_TB A_BLC<1> A_BLC<0> A_BLT<1> A_BLT<0> ++ B_BLC<1> B_BLC<0> B_BLT<1> B_BLT<0> VDD_CORE VSS +XEDGE<1> A_BLC<1> A_BLT<1> B_BLC<1> B_BLT<1> VDD_CORE VSS ++ VDD_CORE VSS / RM_IHPSG13_512x8_c3_2P_BITKIT_EDGE_TB +XEDGE<0> A_BLC<0> A_BLT<0> B_BLC<0> B_BLT<0> VDD_CORE VSS ++ VDD_CORE VSS / RM_IHPSG13_512x8_c3_2P_BITKIT_EDGE_TB +.ENDS +.SUBCKT RM_IHPSG13_512x8_c3_2P_BITKIT_TAP A_BLC A_BLT B_BLC B_BLT NW PW VDD VSS +.ENDS +.SUBCKT RM_IHPSG13_512x8_c3_2P_BITKIT_16x2_TAP A_BLC<1> A_BLC<0> A_BLT<1> A_BLT<0> ++ B_BLC<1> B_BLC<0> B_BLT<1> B_BLT<0> VDD_CORE VSS +XIEDGEBP_COL1<1> A_BLC<1> A_BLT<1> B_BLC<1> B_BLT<1> VDD_CORE VSS ++ VDD_CORE VSS / RM_IHPSG13_512x8_c3_2P_BITKIT_EDGE_TB +XIEDGEBP_COL1<0> A_BLC<1> A_BLT<1> B_BLC<1> B_BLT<1> VDD_CORE VSS ++ VDD_CORE VSS / RM_IHPSG13_512x8_c3_2P_BITKIT_EDGE_TB +XIEDGEBP_COL2<1> A_BLC<0> A_BLT<0> B_BLC<0> B_BLT<0> VDD_CORE VSS ++ VDD_CORE VSS / RM_IHPSG13_512x8_c3_2P_BITKIT_EDGE_TB +XIEDGEBP_COL2<0> A_BLC<0> A_BLT<0> B_BLC<0> B_BLT<0> VDD_CORE VSS ++ VDD_CORE VSS / RM_IHPSG13_512x8_c3_2P_BITKIT_EDGE_TB +XITAP<1> A_BLC<1> A_BLT<1> B_BLC<1> B_BLT<1> VDD_CORE VSS ++ VDD_CORE VSS / RM_IHPSG13_512x8_c3_2P_BITKIT_TAP +XITAP<0> A_BLC<0> A_BLT<0> B_BLC<0> B_BLT<0> VDD_CORE VSS ++ VDD_CORE VSS / RM_IHPSG13_512x8_c3_2P_BITKIT_TAP +.ENDS + + +.SUBCKT RM_IHPSG13_512x8_c3_1P_BITKIT_TAP_LR NW PW VDD VSS +.ENDS +.SUBCKT RM_IHPSG13_512x8_c3_2P_BITKIT_16x2_TAP_LR VDD_CORE VSS +XCORNER<1> VDD_CORE VSS VDD_CORE VSS / ++ RM_IHPSG13_512x8_c3_1P_BITKIT_CORNER +XCORNER<0> VDD_CORE VSS VDD_CORE VSS / ++ RM_IHPSG13_512x8_c3_1P_BITKIT_CORNER +XTAP_BORDER VDD_CORE VSS VDD_CORE VSS / ++ RM_IHPSG13_512x8_c3_1P_BITKIT_TAP_LR +.ENDS + +.SUBCKT RSC_IHPSG13_CBUFX12 A Z VDD VSS +MN1 Z net6 VSS VSS sg13_lv_nmos m=1 w=4.23u l=130.00n ng=6 nrd=0 nrs=0 +MN0 net6 A VSS VSS sg13_lv_nmos m=1 w=1.41u l=130.00n ng=2 nrd=0 nrs=0 +MP1 Z net6 VDD VDD sg13_lv_pmos m=1 w=9.72u l=130.00n ng=6 nrd=0 nrs=0 +MP0 net6 A VDD VDD sg13_lv_pmos m=1 w=3.24u l=130.00n ng=2 nrd=0 nrs=0 +.ENDS +.SUBCKT RM_IHPSG13_512x8_c3_2P_COLDRV13X12 ADDR_COL_I<1> ADDR_COL_I<0> ADDR_COL_O<1> ++ ADDR_COL_O<0> ADDR_DEC_I<7> ADDR_DEC_I<6> ADDR_DEC_I<5> ADDR_DEC_I<4> ++ ADDR_DEC_I<3> ADDR_DEC_I<2> ADDR_DEC_I<1> ADDR_DEC_I<0> ADDR_DEC_O<7> ++ ADDR_DEC_O<6> ADDR_DEC_O<5> ADDR_DEC_O<4> ADDR_DEC_O<3> ADDR_DEC_O<2> ++ ADDR_DEC_O<1> ADDR_DEC_O<0> DCLK_I DCLK_O RCLK_I RCLK_O WCLK_I WCLK_O ++ VDD VSS +XI1<3> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI1<2> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI1<1> VDD VSS / RSC_IHPSG13_FILLCAP8 +XWCLK_DRV WCLK_I WCLK_O VDD VSS / RSC_IHPSG13_CBUFX12 +XRCLK_DRV RCLK_I RCLK_O VDD VSS / RSC_IHPSG13_CBUFX12 +XDCLK_DRV DCLK_I DCLK_O VDD VSS / RSC_IHPSG13_CBUFX12 +XADDR_COL_DRV<1> ADDR_COL_I<1> ADDR_COL_O<1> VDD VSS / ++ RSC_IHPSG13_CBUFX12 +XADDR_COL_DRV<0> ADDR_COL_I<0> ADDR_COL_O<0> VDD VSS / ++ RSC_IHPSG13_CBUFX12 +XADDR_DEC_DRV<7> ADDR_DEC_I<7> ADDR_DEC_O<7> VDD VSS / ++ RSC_IHPSG13_CBUFX12 +XADDR_DEC_DRV<6> ADDR_DEC_I<6> ADDR_DEC_O<6> VDD VSS / ++ RSC_IHPSG13_CBUFX12 +XADDR_DEC_DRV<5> ADDR_DEC_I<5> ADDR_DEC_O<5> VDD VSS / ++ RSC_IHPSG13_CBUFX12 +XADDR_DEC_DRV<4> ADDR_DEC_I<4> ADDR_DEC_O<4> VDD VSS / ++ RSC_IHPSG13_CBUFX12 +XADDR_DEC_DRV<3> ADDR_DEC_I<3> ADDR_DEC_O<3> VDD VSS / ++ RSC_IHPSG13_CBUFX12 +XADDR_DEC_DRV<2> ADDR_DEC_I<2> ADDR_DEC_O<2> VDD VSS / ++ RSC_IHPSG13_CBUFX12 +XADDR_DEC_DRV<1> ADDR_DEC_I<1> ADDR_DEC_O<1> VDD VSS / ++ RSC_IHPSG13_CBUFX12 +XADDR_DEC_DRV<0> ADDR_DEC_I<0> ADDR_DEC_O<0> VDD VSS / ++ RSC_IHPSG13_CBUFX12 +XI0<6> VDD VSS / RSC_IHPSG13_FILLCAP4 +XI0<5> VDD VSS / RSC_IHPSG13_FILLCAP4 +XI0<4> VDD VSS / RSC_IHPSG13_FILLCAP4 +XI0<3> VDD VSS / RSC_IHPSG13_FILLCAP4 +XI0<2> VDD VSS / RSC_IHPSG13_FILLCAP4 +XI0<1> VDD VSS / RSC_IHPSG13_FILLCAP4 +.ENDS +.SUBCKT RSC_IHPSG13_WLDRVX12 A Z VDD VSS +MN1 Z net6 VSS VSS sg13_lv_nmos m=1 w=1.41u l=130.00n ng=2 nrd=0 nrs=0 +MN0 net6 A VSS VSS sg13_lv_nmos m=1 w=1.8u l=130.00n ng=2 nrd=0 nrs=0 +MP1 Z net6 VDD VDD sg13_lv_pmos m=1 w=9.72u l=130.00n ng=6 nrd=0 nrs=0 +MP0 net6 A VDD VDD sg13_lv_pmos m=1 w=900.0n l=130.00n ng=1 nrd=0 nrs=0 +.ENDS +.SUBCKT RM_IHPSG13_512x8_c3_2P_WLDRV16X12 A<15> A<14> A<13> A<12> A<11> A<10> A<9> A<8> ++ A<7> A<6> A<5> A<4> A<3> A<2> A<1> A<0> Z<15> Z<14> Z<13> Z<12> Z<11> Z<10> ++ Z<9> Z<8> Z<7> Z<6> Z<5> Z<4> Z<3> Z<2> Z<1> Z<0> VDD VSS +XBUF<15> A<15> Z<15> VDD VSS / RSC_IHPSG13_WLDRVX12 +XBUF<14> A<14> Z<14> VDD VSS / RSC_IHPSG13_WLDRVX12 +XBUF<13> A<13> Z<13> VDD VSS / RSC_IHPSG13_WLDRVX12 +XBUF<12> A<12> Z<12> VDD VSS / RSC_IHPSG13_WLDRVX12 +XBUF<11> A<11> Z<11> VDD VSS / RSC_IHPSG13_WLDRVX12 +XBUF<10> A<10> Z<10> VDD VSS / RSC_IHPSG13_WLDRVX12 +XBUF<9> A<9> Z<9> VDD VSS / RSC_IHPSG13_WLDRVX12 +XBUF<8> A<8> Z<8> VDD VSS / RSC_IHPSG13_WLDRVX12 +XBUF<7> A<7> Z<7> VDD VSS / RSC_IHPSG13_WLDRVX12 +XBUF<6> A<6> Z<6> VDD VSS / RSC_IHPSG13_WLDRVX12 +XBUF<5> A<5> Z<5> VDD VSS / RSC_IHPSG13_WLDRVX12 +XBUF<4> A<4> Z<4> VDD VSS / RSC_IHPSG13_WLDRVX12 +XBUF<3> A<3> Z<3> VDD VSS / RSC_IHPSG13_WLDRVX12 +XBUF<2> A<2> Z<2> VDD VSS / RSC_IHPSG13_WLDRVX12 +XBUF<1> A<1> Z<1> VDD VSS / RSC_IHPSG13_WLDRVX12 +XBUF<0> A<0> Z<0> VDD VSS / RSC_IHPSG13_WLDRVX12 +.ENDS +.SUBCKT RM_IHPSG13_512x8_c3_2P_DEC04 ADDR<3> ADDR<2> ADDR<1> ADDR<0> CS ECLK_H_BOT ++ ECLK_H_TOP ECLK_L_BOT ECLK_L_TOP WL<15> WL<14> WL<13> WL<12> WL<11> WL<10> ++ WL<9> WL<8> WL<7> WL<6> WL<5> WL<4> WL<3> WL<2> WL<1> WL<0> VDD VSS +XI0<3> PADR<1> PADR<0> sel01<3> VDD VSS / RSC_IHPSG13_NAND2X2 +XI0<2> PADR<1> NADR<0> sel01<2> VDD VSS / RSC_IHPSG13_NAND2X2 +XI0<1> NADR<1> PADR<0> sel01<1> VDD VSS / RSC_IHPSG13_NAND2X2 +XI0<0> NADR<1> NADR<0> sel01<0> VDD VSS / RSC_IHPSG13_NAND2X2 +XI4 ECLK_L_BOT EN VDD VSS / RSC_IHPSG13_CINVX4 +XI5 ECLK_H_BOT ECLK_L_BOT VDD VSS / RSC_IHPSG13_CINVX2 +XI3<3> PADR<3> NADR<3> VDD VSS / RSC_IHPSG13_INVX2 +XI3<2> PADR<2> NADR<2> VDD VSS / RSC_IHPSG13_INVX2 +XI3<1> PADR<1> NADR<1> VDD VSS / RSC_IHPSG13_INVX2 +XI3<0> PADR<0> NADR<0> VDD VSS / RSC_IHPSG13_INVX2 +XR0 ECLK_H_BOT ECLK_H_TOP / RSC_IHPSG13_MET2RES +XI11 ECLK_L_BOT ECLK_L_TOP / RSC_IHPSG13_MET2RES +XI1<3> PADR<2> PADR<3> CS sel23<3> VDD VSS / RSC_IHPSG13_NAND3X2 +XI1<2> NADR<2> PADR<3> CS sel23<2> VDD VSS / RSC_IHPSG13_NAND3X2 +XI1<1> PADR<2> NADR<3> CS sel23<1> VDD VSS / RSC_IHPSG13_NAND3X2 +XI1<0> NADR<2> NADR<3> CS sel23<0> VDD VSS / RSC_IHPSG13_NAND3X2 +XI2<15> sel23<3> sel01<3> EN WL<15> VDD VSS / RSC_IHPSG13_NOR3X2 +XI2<14> sel23<3> sel01<2> EN WL<14> VDD VSS / RSC_IHPSG13_NOR3X2 +XI2<13> sel23<3> sel01<1> EN WL<13> VDD VSS / RSC_IHPSG13_NOR3X2 +XI2<12> sel23<3> sel01<0> EN WL<12> VDD VSS / RSC_IHPSG13_NOR3X2 +XI2<11> sel23<2> sel01<3> EN WL<11> VDD VSS / RSC_IHPSG13_NOR3X2 +XI2<10> sel23<2> sel01<2> EN WL<10> VDD VSS / RSC_IHPSG13_NOR3X2 +XI2<9> sel23<2> sel01<1> EN WL<9> VDD VSS / RSC_IHPSG13_NOR3X2 +XI2<8> sel23<2> sel01<0> EN WL<8> VDD VSS / RSC_IHPSG13_NOR3X2 +XI2<7> sel23<1> sel01<3> EN WL<7> VDD VSS / RSC_IHPSG13_NOR3X2 +XI2<6> sel23<1> sel01<2> EN WL<6> VDD VSS / RSC_IHPSG13_NOR3X2 +XI2<5> sel23<1> sel01<1> EN WL<5> VDD VSS / RSC_IHPSG13_NOR3X2 +XI2<4> sel23<1> sel01<0> EN WL<4> VDD VSS / RSC_IHPSG13_NOR3X2 +XI2<3> sel23<0> sel01<3> EN WL<3> VDD VSS / RSC_IHPSG13_NOR3X2 +XI2<2> sel23<0> sel01<2> EN WL<2> VDD VSS / RSC_IHPSG13_NOR3X2 +XI2<1> sel23<0> sel01<1> EN WL<1> VDD VSS / RSC_IHPSG13_NOR3X2 +XI2<0> sel23<0> sel01<0> EN WL<0> VDD VSS / RSC_IHPSG13_NOR3X2 +XCAPS4 VDD VSS / RSC_IHPSG13_FILLCAP4 +XLATCH<3> CS ADDR<3> PADR<3> VDD VSS / RSC_IHPSG13_LHPQX2 +XLATCH<2> CS ADDR<2> PADR<2> VDD VSS / RSC_IHPSG13_LHPQX2 +XLATCH<1> CS ADDR<1> PADR<1> VDD VSS / RSC_IHPSG13_LHPQX2 +XLATCH<0> CS ADDR<0> PADR<0> VDD VSS / RSC_IHPSG13_LHPQX2 +.ENDS +.SUBCKT RM_IHPSG13_512x8_c3_2P_DEC02 ADDR<1> ADDR<0> CS CS_OUT VDD VSS +XDEC ADDR<1> NADDR<0> CS net1 VDD VSS / RSC_IHPSG13_NAND3X2 +XADDRINV ADDR<0> NADDR<0> VDD VSS / RSC_IHPSG13_INVX2 +XDECINV net1 CS_OUT VDD VSS / RSC_IHPSG13_INVX4 +XI2<1> VDD VSS / RSC_IHPSG13_FILLCAP4 +XI2<0> VDD VSS / RSC_IHPSG13_FILLCAP4 +.ENDS +.SUBCKT RM_IHPSG13_512x8_c3_2P_DEC01 ADDR<1> ADDR<0> CS CS_OUT VDD VSS +XDEC NADDR<1> ADDR<0> CS net1 VDD VSS / RSC_IHPSG13_NAND3X2 +XADDRINV ADDR<1> NADDR<1> VDD VSS / RSC_IHPSG13_INVX2 +XDECINV net1 CS_OUT VDD VSS / RSC_IHPSG13_INVX4 +XI2<1> VDD VSS / RSC_IHPSG13_FILLCAP4 +XI2<0> VDD VSS / RSC_IHPSG13_FILLCAP4 +.ENDS +.SUBCKT RM_IHPSG13_512x8_c3_2P_DEC00 ADDR<1> ADDR<0> CS CS_OUT VDD VSS +XDEC NADDR<1> NADDR<0> CS net1 VDD VSS / RSC_IHPSG13_NAND3X2 +XADDRINV<1> ADDR<1> NADDR<1> VDD VSS / RSC_IHPSG13_INVX2 +XADDRINV<0> ADDR<0> NADDR<0> VDD VSS / RSC_IHPSG13_INVX2 +XI1<1> VDD VSS / RSC_IHPSG13_FILLCAP4 +XI1<0> VDD VSS / RSC_IHPSG13_FILLCAP4 +XDECINV net1 CS_OUT VDD VSS / RSC_IHPSG13_INVX4 +.ENDS +.SUBCKT RM_IHPSG13_512x8_c3_2P_DEC03 ADDR<1> ADDR<0> CS CS_OUT VDD VSS +XDEC ADDR<1> ADDR<0> CS net1 VDD VSS / RSC_IHPSG13_NAND3X2 +XDECINV net1 CS_OUT VDD VSS / RSC_IHPSG13_INVX4 +XI0<1> VDD VSS / RSC_IHPSG13_FILLCAP4 +XI0<0> VDD VSS / RSC_IHPSG13_FILLCAP4 +.ENDS +.SUBCKT RM_IHPSG13_512x8_c3_2P_ROWDEC9 ADDR_N_I<8> ADDR_N_I<7> ADDR_N_I<6> ADDR_N_I<5> ++ ADDR_N_I<4> ADDR_N_I<3> ADDR_N_I<2> ADDR_N_I<1> ADDR_N_I<0> CS_I ECLK_I ++ WL_O<511> WL_O<510> WL_O<509> WL_O<508> WL_O<507> WL_O<506> WL_O<505> ++ WL_O<504> WL_O<503> WL_O<502> WL_O<501> WL_O<500> WL_O<499> WL_O<498> ++ WL_O<497> WL_O<496> WL_O<495> WL_O<494> WL_O<493> WL_O<492> WL_O<491> ++ WL_O<490> WL_O<489> WL_O<488> WL_O<487> WL_O<486> WL_O<485> WL_O<484> ++ WL_O<483> WL_O<482> WL_O<481> WL_O<480> WL_O<479> WL_O<478> WL_O<477> ++ WL_O<476> WL_O<475> WL_O<474> WL_O<473> WL_O<472> WL_O<471> WL_O<470> ++ WL_O<469> WL_O<468> WL_O<467> WL_O<466> WL_O<465> WL_O<464> WL_O<463> ++ WL_O<462> WL_O<461> WL_O<460> WL_O<459> WL_O<458> WL_O<457> WL_O<456> ++ WL_O<455> WL_O<454> WL_O<453> WL_O<452> WL_O<451> WL_O<450> WL_O<449> ++ WL_O<448> WL_O<447> WL_O<446> WL_O<445> WL_O<444> WL_O<443> WL_O<442> ++ WL_O<441> WL_O<440> WL_O<439> WL_O<438> WL_O<437> WL_O<436> WL_O<435> ++ WL_O<434> WL_O<433> WL_O<432> WL_O<431> WL_O<430> WL_O<429> WL_O<428> ++ WL_O<427> WL_O<426> WL_O<425> WL_O<424> WL_O<423> WL_O<422> WL_O<421> ++ WL_O<420> WL_O<419> WL_O<418> WL_O<417> WL_O<416> WL_O<415> WL_O<414> ++ WL_O<413> WL_O<412> WL_O<411> WL_O<410> WL_O<409> WL_O<408> WL_O<407> ++ WL_O<406> WL_O<405> WL_O<404> WL_O<403> WL_O<402> WL_O<401> WL_O<400> ++ WL_O<399> WL_O<398> WL_O<397> WL_O<396> WL_O<395> WL_O<394> WL_O<393> ++ WL_O<392> WL_O<391> WL_O<390> WL_O<389> WL_O<388> WL_O<387> WL_O<386> ++ WL_O<385> WL_O<384> WL_O<383> WL_O<382> WL_O<381> WL_O<380> WL_O<379> ++ WL_O<378> WL_O<377> WL_O<376> WL_O<375> WL_O<374> WL_O<373> WL_O<372> ++ WL_O<371> WL_O<370> WL_O<369> WL_O<368> WL_O<367> WL_O<366> WL_O<365> ++ WL_O<364> WL_O<363> WL_O<362> WL_O<361> WL_O<360> WL_O<359> WL_O<358> ++ WL_O<357> WL_O<356> WL_O<355> WL_O<354> WL_O<353> WL_O<352> WL_O<351> ++ WL_O<350> WL_O<349> WL_O<348> WL_O<347> WL_O<346> WL_O<345> WL_O<344> ++ WL_O<343> WL_O<342> WL_O<341> WL_O<340> WL_O<339> WL_O<338> WL_O<337> ++ WL_O<336> WL_O<335> WL_O<334> WL_O<333> WL_O<332> WL_O<331> WL_O<330> ++ WL_O<329> WL_O<328> WL_O<327> WL_O<326> WL_O<325> WL_O<324> WL_O<323> ++ WL_O<322> WL_O<321> WL_O<320> WL_O<319> WL_O<318> WL_O<317> WL_O<316> ++ WL_O<315> WL_O<314> WL_O<313> WL_O<312> WL_O<311> WL_O<310> WL_O<309> ++ WL_O<308> WL_O<307> WL_O<306> WL_O<305> WL_O<304> WL_O<303> WL_O<302> ++ WL_O<301> WL_O<300> WL_O<299> WL_O<298> WL_O<297> WL_O<296> WL_O<295> ++ WL_O<294> WL_O<293> WL_O<292> WL_O<291> WL_O<290> WL_O<289> WL_O<288> ++ WL_O<287> WL_O<286> WL_O<285> WL_O<284> WL_O<283> WL_O<282> WL_O<281> ++ WL_O<280> WL_O<279> WL_O<278> WL_O<277> WL_O<276> WL_O<275> WL_O<274> ++ WL_O<273> WL_O<272> WL_O<271> WL_O<270> WL_O<269> WL_O<268> WL_O<267> ++ WL_O<266> WL_O<265> WL_O<264> WL_O<263> WL_O<262> WL_O<261> WL_O<260> ++ WL_O<259> WL_O<258> WL_O<257> WL_O<256> WL_O<255> WL_O<254> WL_O<253> ++ WL_O<252> WL_O<251> WL_O<250> WL_O<249> WL_O<248> WL_O<247> WL_O<246> ++ WL_O<245> WL_O<244> WL_O<243> WL_O<242> WL_O<241> WL_O<240> WL_O<239> ++ WL_O<238> WL_O<237> WL_O<236> WL_O<235> WL_O<234> WL_O<233> WL_O<232> ++ WL_O<231> WL_O<230> WL_O<229> WL_O<228> WL_O<227> WL_O<226> WL_O<225> ++ WL_O<224> WL_O<223> WL_O<222> WL_O<221> WL_O<220> WL_O<219> WL_O<218> ++ WL_O<217> WL_O<216> WL_O<215> WL_O<214> WL_O<213> WL_O<212> WL_O<211> ++ WL_O<210> WL_O<209> WL_O<208> WL_O<207> WL_O<206> WL_O<205> WL_O<204> ++ WL_O<203> WL_O<202> WL_O<201> WL_O<200> WL_O<199> WL_O<198> WL_O<197> ++ WL_O<196> WL_O<195> WL_O<194> WL_O<193> WL_O<192> WL_O<191> WL_O<190> ++ WL_O<189> WL_O<188> WL_O<187> WL_O<186> WL_O<185> WL_O<184> WL_O<183> ++ WL_O<182> WL_O<181> WL_O<180> WL_O<179> WL_O<178> WL_O<177> WL_O<176> ++ WL_O<175> WL_O<174> WL_O<173> WL_O<172> WL_O<171> WL_O<170> WL_O<169> ++ WL_O<168> WL_O<167> WL_O<166> WL_O<165> WL_O<164> WL_O<163> WL_O<162> ++ WL_O<161> WL_O<160> WL_O<159> WL_O<158> WL_O<157> WL_O<156> WL_O<155> ++ WL_O<154> WL_O<153> WL_O<152> WL_O<151> WL_O<150> WL_O<149> WL_O<148> ++ WL_O<147> WL_O<146> WL_O<145> WL_O<144> WL_O<143> WL_O<142> WL_O<141> ++ WL_O<140> WL_O<139> WL_O<138> WL_O<137> WL_O<136> WL_O<135> WL_O<134> ++ WL_O<133> WL_O<132> WL_O<131> WL_O<130> WL_O<129> WL_O<128> WL_O<127> ++ WL_O<126> WL_O<125> WL_O<124> WL_O<123> WL_O<122> WL_O<121> WL_O<120> ++ WL_O<119> WL_O<118> WL_O<117> WL_O<116> WL_O<115> WL_O<114> WL_O<113> ++ WL_O<112> WL_O<111> WL_O<110> WL_O<109> WL_O<108> WL_O<107> WL_O<106> ++ WL_O<105> WL_O<104> WL_O<103> WL_O<102> WL_O<101> WL_O<100> WL_O<99> ++ WL_O<98> WL_O<97> WL_O<96> WL_O<95> WL_O<94> WL_O<93> WL_O<92> WL_O<91> ++ WL_O<90> WL_O<89> WL_O<88> WL_O<87> WL_O<86> WL_O<85> WL_O<84> WL_O<83> ++ WL_O<82> WL_O<81> WL_O<80> WL_O<79> WL_O<78> WL_O<77> WL_O<76> WL_O<75> ++ WL_O<74> WL_O<73> WL_O<72> WL_O<71> WL_O<70> WL_O<69> WL_O<68> WL_O<67> ++ WL_O<66> WL_O<65> WL_O<64> WL_O<63> WL_O<62> WL_O<61> WL_O<60> WL_O<59> ++ WL_O<58> WL_O<57> WL_O<56> WL_O<55> WL_O<54> WL_O<53> WL_O<52> WL_O<51> ++ WL_O<50> WL_O<49> WL_O<48> WL_O<47> WL_O<46> WL_O<45> WL_O<44> WL_O<43> ++ WL_O<42> WL_O<41> WL_O<40> WL_O<39> WL_O<38> WL_O<37> WL_O<36> WL_O<35> ++ WL_O<34> WL_O<33> WL_O<32> WL_O<31> WL_O<30> WL_O<29> WL_O<28> WL_O<27> ++ WL_O<26> WL_O<25> WL_O<24> WL_O<23> WL_O<22> WL_O<21> WL_O<20> WL_O<19> ++ WL_O<18> WL_O<17> WL_O<16> WL_O<15> WL_O<14> WL_O<13> WL_O<12> WL_O<11> ++ WL_O<10> WL_O<9> WL_O<8> WL_O<7> WL_O<6> WL_O<5> WL_O<4> WL_O<3> WL_O<2> ++ WL_O<1> WL_O<0> VDD VSS +XSEL<31> ADDR_N_I<3> ADDR_N_I<2> ADDR_N_I<1> ADDR_N_I<0> CS00<31> ECLK_H<31> ++ ECLK_H<32> ECLK_B<31> ECLK_B<32> WL_O<511> WL_O<510> WL_O<509> WL_O<508> ++ WL_O<507> WL_O<506> WL_O<505> WL_O<504> WL_O<503> WL_O<502> WL_O<501> ++ WL_O<500> WL_O<499> WL_O<498> WL_O<497> WL_O<496> VDD VSS / ++ RM_IHPSG13_512x8_c3_2P_DEC04 +XSEL<30> ADDR_N_I<3> ADDR_N_I<2> ADDR_N_I<1> ADDR_N_I<0> CS00<30> ECLK_H<30> ++ ECLK_H<31> ECLK_B<30> ECLK_B<31> WL_O<495> WL_O<494> WL_O<493> WL_O<492> ++ WL_O<491> WL_O<490> WL_O<489> WL_O<488> WL_O<487> WL_O<486> WL_O<485> ++ WL_O<484> WL_O<483> WL_O<482> WL_O<481> WL_O<480> VDD VSS / ++ RM_IHPSG13_512x8_c3_2P_DEC04 +XSEL<29> ADDR_N_I<3> ADDR_N_I<2> ADDR_N_I<1> ADDR_N_I<0> CS00<29> ECLK_H<29> ++ ECLK_H<30> ECLK_B<29> ECLK_B<30> WL_O<479> WL_O<478> WL_O<477> WL_O<476> ++ WL_O<475> WL_O<474> WL_O<473> WL_O<472> WL_O<471> WL_O<470> WL_O<469> ++ WL_O<468> WL_O<467> WL_O<466> WL_O<465> WL_O<464> VDD VSS / ++ RM_IHPSG13_512x8_c3_2P_DEC04 +XSEL<28> ADDR_N_I<3> ADDR_N_I<2> ADDR_N_I<1> ADDR_N_I<0> CS00<28> ECLK_H<28> ++ ECLK_H<29> ECLK_B<28> ECLK_B<29> WL_O<463> WL_O<462> WL_O<461> WL_O<460> ++ WL_O<459> WL_O<458> WL_O<457> WL_O<456> WL_O<455> WL_O<454> WL_O<453> ++ WL_O<452> WL_O<451> WL_O<450> WL_O<449> WL_O<448> VDD VSS / ++ RM_IHPSG13_512x8_c3_2P_DEC04 +XSEL<27> ADDR_N_I<3> ADDR_N_I<2> ADDR_N_I<1> ADDR_N_I<0> CS00<27> ECLK_H<27> ++ ECLK_H<28> ECLK_B<27> ECLK_B<28> WL_O<447> WL_O<446> WL_O<445> WL_O<444> ++ WL_O<443> WL_O<442> WL_O<441> WL_O<440> WL_O<439> WL_O<438> WL_O<437> ++ WL_O<436> WL_O<435> WL_O<434> WL_O<433> WL_O<432> VDD VSS / ++ RM_IHPSG13_512x8_c3_2P_DEC04 +XSEL<26> ADDR_N_I<3> ADDR_N_I<2> ADDR_N_I<1> ADDR_N_I<0> CS00<26> ECLK_H<26> ++ ECLK_H<27> ECLK_B<26> ECLK_B<27> WL_O<431> WL_O<430> WL_O<429> WL_O<428> ++ WL_O<427> WL_O<426> WL_O<425> WL_O<424> WL_O<423> WL_O<422> WL_O<421> ++ WL_O<420> WL_O<419> WL_O<418> WL_O<417> WL_O<416> VDD VSS / ++ RM_IHPSG13_512x8_c3_2P_DEC04 +XSEL<25> ADDR_N_I<3> ADDR_N_I<2> ADDR_N_I<1> ADDR_N_I<0> CS00<25> ECLK_H<25> ++ ECLK_H<26> ECLK_B<25> ECLK_B<26> WL_O<415> WL_O<414> WL_O<413> WL_O<412> ++ WL_O<411> WL_O<410> WL_O<409> WL_O<408> WL_O<407> WL_O<406> WL_O<405> ++ WL_O<404> WL_O<403> WL_O<402> WL_O<401> WL_O<400> VDD VSS / ++ RM_IHPSG13_512x8_c3_2P_DEC04 +XSEL<24> ADDR_N_I<3> ADDR_N_I<2> ADDR_N_I<1> ADDR_N_I<0> CS00<24> ECLK_H<24> ++ ECLK_H<25> ECLK_B<24> ECLK_B<25> WL_O<399> WL_O<398> WL_O<397> WL_O<396> ++ WL_O<395> WL_O<394> WL_O<393> WL_O<392> WL_O<391> WL_O<390> WL_O<389> ++ WL_O<388> WL_O<387> WL_O<386> WL_O<385> WL_O<384> VDD VSS / ++ RM_IHPSG13_512x8_c3_2P_DEC04 +XSEL<23> ADDR_N_I<3> ADDR_N_I<2> ADDR_N_I<1> ADDR_N_I<0> CS00<23> ECLK_H<23> ++ ECLK_H<24> ECLK_B<23> ECLK_B<24> WL_O<383> WL_O<382> WL_O<381> WL_O<380> ++ WL_O<379> WL_O<378> WL_O<377> WL_O<376> WL_O<375> WL_O<374> WL_O<373> ++ WL_O<372> WL_O<371> WL_O<370> WL_O<369> WL_O<368> VDD VSS / ++ RM_IHPSG13_512x8_c3_2P_DEC04 +XSEL<22> ADDR_N_I<3> ADDR_N_I<2> ADDR_N_I<1> ADDR_N_I<0> CS00<22> ECLK_H<22> ++ ECLK_H<23> ECLK_B<22> ECLK_B<23> WL_O<367> WL_O<366> WL_O<365> WL_O<364> ++ WL_O<363> WL_O<362> WL_O<361> WL_O<360> WL_O<359> WL_O<358> WL_O<357> ++ WL_O<356> WL_O<355> WL_O<354> WL_O<353> WL_O<352> VDD VSS / ++ RM_IHPSG13_512x8_c3_2P_DEC04 +XSEL<21> ADDR_N_I<3> ADDR_N_I<2> ADDR_N_I<1> ADDR_N_I<0> CS00<21> ECLK_H<21> ++ ECLK_H<22> ECLK_B<21> ECLK_B<22> WL_O<351> WL_O<350> WL_O<349> WL_O<348> ++ WL_O<347> WL_O<346> WL_O<345> WL_O<344> WL_O<343> WL_O<342> WL_O<341> ++ WL_O<340> WL_O<339> WL_O<338> WL_O<337> WL_O<336> VDD VSS / ++ RM_IHPSG13_512x8_c3_2P_DEC04 +XSEL<20> ADDR_N_I<3> ADDR_N_I<2> ADDR_N_I<1> ADDR_N_I<0> CS00<20> ECLK_H<20> ++ ECLK_H<21> ECLK_B<20> ECLK_B<21> WL_O<335> WL_O<334> WL_O<333> WL_O<332> ++ WL_O<331> WL_O<330> WL_O<329> WL_O<328> WL_O<327> WL_O<326> WL_O<325> ++ WL_O<324> WL_O<323> WL_O<322> WL_O<321> WL_O<320> VDD VSS / ++ RM_IHPSG13_512x8_c3_2P_DEC04 +XSEL<19> ADDR_N_I<3> ADDR_N_I<2> ADDR_N_I<1> ADDR_N_I<0> CS00<19> ECLK_H<19> ++ ECLK_H<20> ECLK_B<19> ECLK_B<20> WL_O<319> WL_O<318> WL_O<317> WL_O<316> ++ WL_O<315> WL_O<314> WL_O<313> WL_O<312> WL_O<311> WL_O<310> WL_O<309> ++ WL_O<308> WL_O<307> WL_O<306> WL_O<305> WL_O<304> VDD VSS / ++ RM_IHPSG13_512x8_c3_2P_DEC04 +XSEL<18> ADDR_N_I<3> ADDR_N_I<2> ADDR_N_I<1> ADDR_N_I<0> CS00<18> ECLK_H<18> ++ ECLK_H<19> ECLK_B<18> ECLK_B<19> WL_O<303> WL_O<302> WL_O<301> WL_O<300> ++ WL_O<299> WL_O<298> WL_O<297> WL_O<296> WL_O<295> WL_O<294> WL_O<293> ++ WL_O<292> WL_O<291> WL_O<290> WL_O<289> WL_O<288> VDD VSS / ++ RM_IHPSG13_512x8_c3_2P_DEC04 +XSEL<17> ADDR_N_I<3> ADDR_N_I<2> ADDR_N_I<1> ADDR_N_I<0> CS00<17> ECLK_H<17> ++ ECLK_H<18> ECLK_B<17> ECLK_B<18> WL_O<287> WL_O<286> WL_O<285> WL_O<284> ++ WL_O<283> WL_O<282> WL_O<281> WL_O<280> WL_O<279> WL_O<278> WL_O<277> ++ WL_O<276> WL_O<275> WL_O<274> WL_O<273> WL_O<272> VDD VSS / ++ RM_IHPSG13_512x8_c3_2P_DEC04 +XSEL<16> ADDR_N_I<3> ADDR_N_I<2> ADDR_N_I<1> ADDR_N_I<0> CS00<16> ECLK_H<16> ++ ECLK_H<17> ECLK_B<16> ECLK_B<17> WL_O<271> WL_O<270> WL_O<269> WL_O<268> ++ WL_O<267> WL_O<266> WL_O<265> WL_O<264> WL_O<263> WL_O<262> WL_O<261> ++ WL_O<260> WL_O<259> WL_O<258> WL_O<257> WL_O<256> VDD VSS / ++ RM_IHPSG13_512x8_c3_2P_DEC04 +XSEL<15> ADDR_N_I<3> ADDR_N_I<2> ADDR_N_I<1> ADDR_N_I<0> CS00<15> ECLK_H<15> ++ ECLK_H<16> ECLK_B<15> ECLK_B<16> WL_O<255> WL_O<254> WL_O<253> WL_O<252> ++ WL_O<251> WL_O<250> WL_O<249> WL_O<248> WL_O<247> WL_O<246> WL_O<245> ++ WL_O<244> WL_O<243> WL_O<242> WL_O<241> WL_O<240> VDD VSS / ++ RM_IHPSG13_512x8_c3_2P_DEC04 +XSEL<14> ADDR_N_I<3> ADDR_N_I<2> ADDR_N_I<1> ADDR_N_I<0> CS00<14> ECLK_H<14> ++ ECLK_H<15> ECLK_B<14> ECLK_B<15> WL_O<239> WL_O<238> WL_O<237> WL_O<236> ++ WL_O<235> WL_O<234> WL_O<233> WL_O<232> WL_O<231> WL_O<230> WL_O<229> ++ WL_O<228> WL_O<227> WL_O<226> WL_O<225> WL_O<224> VDD VSS / ++ RM_IHPSG13_512x8_c3_2P_DEC04 +XSEL<13> ADDR_N_I<3> ADDR_N_I<2> ADDR_N_I<1> ADDR_N_I<0> CS00<13> ECLK_H<13> ++ ECLK_H<14> ECLK_B<13> ECLK_B<14> WL_O<223> WL_O<222> WL_O<221> WL_O<220> ++ WL_O<219> WL_O<218> WL_O<217> WL_O<216> WL_O<215> WL_O<214> WL_O<213> ++ WL_O<212> WL_O<211> WL_O<210> WL_O<209> WL_O<208> VDD VSS / ++ RM_IHPSG13_512x8_c3_2P_DEC04 +XSEL<12> ADDR_N_I<3> ADDR_N_I<2> ADDR_N_I<1> ADDR_N_I<0> CS00<12> ECLK_H<12> ++ ECLK_H<13> ECLK_B<12> ECLK_B<13> WL_O<207> WL_O<206> WL_O<205> WL_O<204> ++ WL_O<203> WL_O<202> WL_O<201> WL_O<200> WL_O<199> WL_O<198> WL_O<197> ++ WL_O<196> WL_O<195> WL_O<194> WL_O<193> WL_O<192> VDD VSS / ++ RM_IHPSG13_512x8_c3_2P_DEC04 +XSEL<11> ADDR_N_I<3> ADDR_N_I<2> ADDR_N_I<1> ADDR_N_I<0> CS00<11> ECLK_H<11> ++ ECLK_H<12> ECLK_B<11> ECLK_B<12> WL_O<191> WL_O<190> WL_O<189> WL_O<188> ++ WL_O<187> WL_O<186> WL_O<185> WL_O<184> WL_O<183> WL_O<182> WL_O<181> ++ WL_O<180> WL_O<179> WL_O<178> WL_O<177> WL_O<176> VDD VSS / ++ RM_IHPSG13_512x8_c3_2P_DEC04 +XSEL<10> ADDR_N_I<3> ADDR_N_I<2> ADDR_N_I<1> ADDR_N_I<0> CS00<10> ECLK_H<10> ++ ECLK_H<11> ECLK_B<10> ECLK_B<11> WL_O<175> WL_O<174> WL_O<173> WL_O<172> ++ WL_O<171> WL_O<170> WL_O<169> WL_O<168> WL_O<167> WL_O<166> WL_O<165> ++ WL_O<164> WL_O<163> WL_O<162> WL_O<161> WL_O<160> VDD VSS / ++ RM_IHPSG13_512x8_c3_2P_DEC04 +XSEL<9> ADDR_N_I<3> ADDR_N_I<2> ADDR_N_I<1> ADDR_N_I<0> CS00<9> ECLK_H<9> ++ ECLK_H<10> ECLK_B<9> ECLK_B<10> WL_O<159> WL_O<158> WL_O<157> WL_O<156> ++ WL_O<155> WL_O<154> WL_O<153> WL_O<152> WL_O<151> WL_O<150> WL_O<149> ++ WL_O<148> WL_O<147> WL_O<146> WL_O<145> WL_O<144> VDD VSS / ++ RM_IHPSG13_512x8_c3_2P_DEC04 +XSEL<8> ADDR_N_I<3> ADDR_N_I<2> ADDR_N_I<1> ADDR_N_I<0> CS00<8> ECLK_H<8> ++ ECLK_H<9> ECLK_B<8> ECLK_B<9> WL_O<143> WL_O<142> WL_O<141> WL_O<140> ++ WL_O<139> WL_O<138> WL_O<137> WL_O<136> WL_O<135> WL_O<134> WL_O<133> ++ WL_O<132> WL_O<131> WL_O<130> WL_O<129> WL_O<128> VDD VSS / ++ RM_IHPSG13_512x8_c3_2P_DEC04 +XSEL<7> ADDR_N_I<3> ADDR_N_I<2> ADDR_N_I<1> ADDR_N_I<0> CS00<7> ECLK_H<7> ++ ECLK_H<8> ECLK_B<7> ECLK_B<8> WL_O<127> WL_O<126> WL_O<125> WL_O<124> ++ WL_O<123> WL_O<122> WL_O<121> WL_O<120> WL_O<119> WL_O<118> WL_O<117> ++ WL_O<116> WL_O<115> WL_O<114> WL_O<113> WL_O<112> VDD VSS / ++ RM_IHPSG13_512x8_c3_2P_DEC04 +XSEL<6> ADDR_N_I<3> ADDR_N_I<2> ADDR_N_I<1> ADDR_N_I<0> CS00<6> ECLK_H<6> ++ ECLK_H<7> ECLK_B<6> ECLK_B<7> WL_O<111> WL_O<110> WL_O<109> WL_O<108> ++ WL_O<107> WL_O<106> WL_O<105> WL_O<104> WL_O<103> WL_O<102> WL_O<101> ++ WL_O<100> WL_O<99> WL_O<98> WL_O<97> WL_O<96> VDD VSS / ++ RM_IHPSG13_512x8_c3_2P_DEC04 +XSEL<5> ADDR_N_I<3> ADDR_N_I<2> ADDR_N_I<1> ADDR_N_I<0> CS00<5> ECLK_H<5> ++ ECLK_H<6> ECLK_B<5> ECLK_B<6> WL_O<95> WL_O<94> WL_O<93> WL_O<92> WL_O<91> ++ WL_O<90> WL_O<89> WL_O<88> WL_O<87> WL_O<86> WL_O<85> WL_O<84> WL_O<83> ++ WL_O<82> WL_O<81> WL_O<80> VDD VSS / RM_IHPSG13_512x8_c3_2P_DEC04 +XSEL<4> ADDR_N_I<3> ADDR_N_I<2> ADDR_N_I<1> ADDR_N_I<0> CS00<4> ECLK_H<4> ++ ECLK_H<5> ECLK_B<4> ECLK_B<5> WL_O<79> WL_O<78> WL_O<77> WL_O<76> WL_O<75> ++ WL_O<74> WL_O<73> WL_O<72> WL_O<71> WL_O<70> WL_O<69> WL_O<68> WL_O<67> ++ WL_O<66> WL_O<65> WL_O<64> VDD VSS / RM_IHPSG13_512x8_c3_2P_DEC04 +XSEL<3> ADDR_N_I<3> ADDR_N_I<2> ADDR_N_I<1> ADDR_N_I<0> CS00<3> ECLK_H<3> ++ ECLK_H<4> ECLK_B<3> ECLK_B<4> WL_O<63> WL_O<62> WL_O<61> WL_O<60> WL_O<59> ++ WL_O<58> WL_O<57> WL_O<56> WL_O<55> WL_O<54> WL_O<53> WL_O<52> WL_O<51> ++ WL_O<50> WL_O<49> WL_O<48> VDD VSS / RM_IHPSG13_512x8_c3_2P_DEC04 +XSEL<2> ADDR_N_I<3> ADDR_N_I<2> ADDR_N_I<1> ADDR_N_I<0> CS00<2> ECLK_H<2> ++ ECLK_H<3> ECLK_B<2> ECLK_B<3> WL_O<47> WL_O<46> WL_O<45> WL_O<44> WL_O<43> ++ WL_O<42> WL_O<41> WL_O<40> WL_O<39> WL_O<38> WL_O<37> WL_O<36> WL_O<35> ++ WL_O<34> WL_O<33> WL_O<32> VDD VSS / RM_IHPSG13_512x8_c3_2P_DEC04 +XSEL<1> ADDR_N_I<3> ADDR_N_I<2> ADDR_N_I<1> ADDR_N_I<0> CS00<1> ECLK_H<1> ++ ECLK_H<2> ECLK_B<1> ECLK_B<2> WL_O<31> WL_O<30> WL_O<29> WL_O<28> WL_O<27> ++ WL_O<26> WL_O<25> WL_O<24> WL_O<23> WL_O<22> WL_O<21> WL_O<20> WL_O<19> ++ WL_O<18> WL_O<17> WL_O<16> VDD VSS / RM_IHPSG13_512x8_c3_2P_DEC04 +XSEL<0> ADDR_N_I<3> ADDR_N_I<2> ADDR_N_I<1> ADDR_N_I<0> CS00<0> ECLK_I ++ ECLK_H<1> ECLK_B<0> ECLK_B<1> WL_O<15> WL_O<14> WL_O<13> WL_O<12> WL_O<11> ++ WL_O<10> WL_O<9> WL_O<8> WL_O<7> WL_O<6> WL_O<5> WL_O<4> WL_O<3> WL_O<2> ++ WL_O<1> WL_O<0> VDD VSS / RM_IHPSG13_512x8_c3_2P_DEC04 +XDEC10<9> ADDR_N_I<7> ADDR_N_I<6> CS04<1> CS02<6> VDD VSS / ++ RM_IHPSG13_512x8_c3_2P_DEC02 +XDEC10<8> ADDR_N_I<7> ADDR_N_I<6> CS04<0> CS02<2> VDD VSS / ++ RM_IHPSG13_512x8_c3_2P_DEC02 +XDEC10<7> ADDR_N_I<5> ADDR_N_I<4> CS02<7> CS00<30> VDD VSS / ++ RM_IHPSG13_512x8_c3_2P_DEC02 +XDEC10<6> ADDR_N_I<5> ADDR_N_I<4> CS02<6> CS00<26> VDD VSS / ++ RM_IHPSG13_512x8_c3_2P_DEC02 +XDEC10<5> ADDR_N_I<5> ADDR_N_I<4> CS02<5> CS00<22> VDD VSS / ++ RM_IHPSG13_512x8_c3_2P_DEC02 +XDEC10<4> ADDR_N_I<5> ADDR_N_I<4> CS02<4> CS00<18> VDD VSS / ++ RM_IHPSG13_512x8_c3_2P_DEC02 +XDEC10<3> ADDR_N_I<5> ADDR_N_I<4> CS02<3> CS00<14> VDD VSS / ++ RM_IHPSG13_512x8_c3_2P_DEC02 +XDEC10<2> ADDR_N_I<5> ADDR_N_I<4> CS02<2> CS00<10> VDD VSS / ++ RM_IHPSG13_512x8_c3_2P_DEC02 +XDEC10<1> ADDR_N_I<5> ADDR_N_I<4> CS02<1> CS00<6> VDD VSS / ++ RM_IHPSG13_512x8_c3_2P_DEC02 +XDEC10<0> ADDR_N_I<5> ADDR_N_I<4> CS02<0> CS00<2> VDD VSS / ++ RM_IHPSG13_512x8_c3_2P_DEC02 +XDEC01<10> ADDR_N_I<9> ADDR_N_I<8> CS_I CS04<1> VDD VSS / ++ RM_IHPSG13_512x8_c3_2P_DEC01 +XDEC01<9> ADDR_N_I<7> ADDR_N_I<6> CS04<1> CS02<5> VDD VSS / ++ RM_IHPSG13_512x8_c3_2P_DEC01 +XDEC01<8> ADDR_N_I<7> ADDR_N_I<6> CS04<0> CS02<1> VDD VSS / ++ RM_IHPSG13_512x8_c3_2P_DEC01 +XDEC01<7> ADDR_N_I<5> ADDR_N_I<4> CS02<7> CS00<29> VDD VSS / ++ RM_IHPSG13_512x8_c3_2P_DEC01 +XDEC01<6> ADDR_N_I<5> ADDR_N_I<4> CS02<6> CS00<25> VDD VSS / ++ RM_IHPSG13_512x8_c3_2P_DEC01 +XDEC01<5> ADDR_N_I<5> ADDR_N_I<4> CS02<5> CS00<21> VDD VSS / ++ RM_IHPSG13_512x8_c3_2P_DEC01 +XDEC01<4> ADDR_N_I<5> ADDR_N_I<4> CS02<4> CS00<17> VDD VSS / ++ RM_IHPSG13_512x8_c3_2P_DEC01 +XDEC01<3> ADDR_N_I<5> ADDR_N_I<4> CS02<3> CS00<13> VDD VSS / ++ RM_IHPSG13_512x8_c3_2P_DEC01 +XDEC01<2> ADDR_N_I<5> ADDR_N_I<4> CS02<2> CS00<9> VDD VSS / ++ RM_IHPSG13_512x8_c3_2P_DEC01 +XDEC01<1> ADDR_N_I<5> ADDR_N_I<4> CS02<1> CS00<5> VDD VSS / ++ RM_IHPSG13_512x8_c3_2P_DEC01 +XDEC01<0> ADDR_N_I<5> ADDR_N_I<4> CS02<0> CS00<1> VDD VSS / ++ RM_IHPSG13_512x8_c3_2P_DEC01 +XL2<258> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<257> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<256> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<255> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<254> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<253> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<252> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<251> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<250> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<249> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<248> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<247> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<246> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<245> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<244> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<243> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<242> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<241> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<240> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<239> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<238> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<237> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<236> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<235> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<234> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<233> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<232> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<231> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<230> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<229> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<228> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<227> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<226> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<225> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<224> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<223> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<222> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<221> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<220> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<219> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<218> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<217> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<216> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<215> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<214> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<213> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<212> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<211> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<210> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<209> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<208> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<207> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<206> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<205> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<204> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<203> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<202> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<201> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<200> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<199> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<198> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<197> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<196> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<195> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<194> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<193> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<192> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<191> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<190> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<189> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<188> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<187> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<186> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<185> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<184> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<183> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<182> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<181> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<180> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<179> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<178> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<177> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<176> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<175> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<174> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<173> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<172> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<171> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<170> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<169> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<168> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<167> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<166> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<165> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<164> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<163> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<162> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<161> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<160> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<159> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<158> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<157> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<156> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<155> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<154> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<153> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<152> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<151> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<150> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<149> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<148> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<147> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<146> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<145> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<144> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<143> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<142> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<141> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<140> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<139> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<138> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<137> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<136> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<135> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<134> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<133> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<132> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<131> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<130> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<129> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<128> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<127> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<126> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<125> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<124> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<123> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<122> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<121> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<120> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<119> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<118> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<117> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<116> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<115> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<114> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<113> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<112> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<111> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<110> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<109> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<108> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<107> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<106> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<105> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<104> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<103> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<102> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<101> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<100> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<99> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<98> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<97> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<96> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<95> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<94> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<93> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<92> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<91> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<90> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<89> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<88> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<87> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<86> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<85> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<84> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<83> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<82> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<81> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<80> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<79> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<78> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<77> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<76> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<75> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<74> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<73> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<72> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<71> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<70> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<69> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<68> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<67> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<66> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<65> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<64> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<63> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<62> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<61> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<60> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<59> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<58> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<57> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<56> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<55> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<54> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<53> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<52> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<51> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<50> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<49> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<48> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<47> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<46> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<45> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<44> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<43> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<42> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<41> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<40> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<39> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<38> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<37> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<36> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<35> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<34> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<33> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<32> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<31> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<30> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<29> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<28> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<27> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<26> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<25> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<24> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<23> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<22> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<21> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<20> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<19> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<18> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<17> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<16> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<15> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<14> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<13> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<12> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<11> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<10> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<9> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<8> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<7> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<6> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<5> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<4> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<3> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<2> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<1> VDD VSS / RSC_IHPSG13_FILLCAP8 +XDEC00<10> ADDR_N_I<9> ADDR_N_I<8> CS_I CS04<0> VDD VSS / ++ RM_IHPSG13_512x8_c3_2P_DEC00 +XDEC00<9> ADDR_N_I<7> ADDR_N_I<6> CS04<1> CS02<4> VDD VSS / ++ RM_IHPSG13_512x8_c3_2P_DEC00 +XDEC00<8> ADDR_N_I<7> ADDR_N_I<6> CS04<0> CS02<0> VDD VSS / ++ RM_IHPSG13_512x8_c3_2P_DEC00 +XDEC00<7> ADDR_N_I<5> ADDR_N_I<4> CS02<7> CS00<28> VDD VSS / ++ RM_IHPSG13_512x8_c3_2P_DEC00 +XDEC00<6> ADDR_N_I<5> ADDR_N_I<4> CS02<6> CS00<24> VDD VSS / ++ RM_IHPSG13_512x8_c3_2P_DEC00 +XDEC00<5> ADDR_N_I<5> ADDR_N_I<4> CS02<5> CS00<20> VDD VSS / ++ RM_IHPSG13_512x8_c3_2P_DEC00 +XDEC00<4> ADDR_N_I<5> ADDR_N_I<4> CS02<4> CS00<16> VDD VSS / ++ RM_IHPSG13_512x8_c3_2P_DEC00 +XDEC00<3> ADDR_N_I<5> ADDR_N_I<4> CS02<3> CS00<12> VDD VSS / ++ RM_IHPSG13_512x8_c3_2P_DEC00 +XDEC00<2> ADDR_N_I<5> ADDR_N_I<4> CS02<2> CS00<8> VDD VSS / ++ RM_IHPSG13_512x8_c3_2P_DEC00 +XDEC00<1> ADDR_N_I<5> ADDR_N_I<4> CS02<1> CS00<4> VDD VSS / ++ RM_IHPSG13_512x8_c3_2P_DEC00 +XDEC00<0> ADDR_N_I<5> ADDR_N_I<4> CS02<0> CS00<0> VDD VSS / ++ RM_IHPSG13_512x8_c3_2P_DEC00 +XDEC11<9> ADDR_N_I<7> ADDR_N_I<6> CS04<1> CS02<7> VDD VSS / ++ RM_IHPSG13_512x8_c3_2P_DEC03 +XDEC11<8> ADDR_N_I<7> ADDR_N_I<6> CS04<0> CS02<3> VDD VSS / ++ RM_IHPSG13_512x8_c3_2P_DEC03 +XDEC11<7> ADDR_N_I<5> ADDR_N_I<4> CS02<7> CS00<31> VDD VSS / ++ RM_IHPSG13_512x8_c3_2P_DEC03 +XDEC11<6> ADDR_N_I<5> ADDR_N_I<4> CS02<6> CS00<27> VDD VSS / ++ RM_IHPSG13_512x8_c3_2P_DEC03 +XDEC11<5> ADDR_N_I<5> ADDR_N_I<4> CS02<5> CS00<23> VDD VSS / ++ RM_IHPSG13_512x8_c3_2P_DEC03 +XDEC11<4> ADDR_N_I<5> ADDR_N_I<4> CS02<4> CS00<19> VDD VSS / ++ RM_IHPSG13_512x8_c3_2P_DEC03 +XDEC11<3> ADDR_N_I<5> ADDR_N_I<4> CS02<3> CS00<15> VDD VSS / ++ RM_IHPSG13_512x8_c3_2P_DEC03 +XDEC11<2> ADDR_N_I<5> ADDR_N_I<4> CS02<2> CS00<11> VDD VSS / ++ RM_IHPSG13_512x8_c3_2P_DEC03 +XDEC11<1> ADDR_N_I<5> ADDR_N_I<4> CS02<1> CS00<7> VDD VSS / ++ RM_IHPSG13_512x8_c3_2P_DEC03 +XDEC11<0> ADDR_N_I<5> ADDR_N_I<4> CS02<0> CS00<3> VDD VSS / ++ RM_IHPSG13_512x8_c3_2P_DEC03 +XI0 ADDR_N_I<9> VDD VSS / RSC_IHPSG13_TIEL +.ENDS +.SUBCKT RM_IHPSG13_512x8_c3_2P_ROWREG9 ACLK_N_I ADDR_I<8> ADDR_I<7> ADDR_I<6> ADDR_I<5> ++ ADDR_I<4> ADDR_I<3> ADDR_I<2> ADDR_I<1> ADDR_I<0> ADDR_N_O<8> ADDR_N_O<7> ++ ADDR_N_O<6> ADDR_N_O<5> ADDR_N_O<4> ADDR_N_O<3> ADDR_N_O<2> ADDR_N_O<1> ++ ADDR_N_O<0> BIST_ADDR_I<8> BIST_ADDR_I<7> BIST_ADDR_I<6> BIST_ADDR_I<5> ++ BIST_ADDR_I<4> BIST_ADDR_I<3> BIST_ADDR_I<2> BIST_ADDR_I<1> BIST_ADDR_I<0> ++ BIST_EN_I VDD VSS +XDFF<8> BIST_EN_I BIST_ADDR_I<8> ACLK_N_I ADDR_I<8> q_int<8> net04<0> VDD ++ VSS / RSC_IHPSG13_DFNQMX2IX1 +XDFF<7> BIST_EN_I BIST_ADDR_I<7> ACLK_N_I ADDR_I<7> q_int<7> net04<1> VDD ++ VSS / RSC_IHPSG13_DFNQMX2IX1 +XDFF<6> BIST_EN_I BIST_ADDR_I<6> ACLK_N_I ADDR_I<6> q_int<6> net04<2> VDD ++ VSS / RSC_IHPSG13_DFNQMX2IX1 +XDFF<5> BIST_EN_I BIST_ADDR_I<5> ACLK_N_I ADDR_I<5> q_int<5> net04<3> VDD ++ VSS / RSC_IHPSG13_DFNQMX2IX1 +XDFF<4> BIST_EN_I BIST_ADDR_I<4> ACLK_N_I ADDR_I<4> q_int<4> net04<4> VDD ++ VSS / RSC_IHPSG13_DFNQMX2IX1 +XDFF<3> BIST_EN_I BIST_ADDR_I<3> ACLK_N_I ADDR_I<3> q_int<3> net04<5> VDD ++ VSS / RSC_IHPSG13_DFNQMX2IX1 +XDFF<2> BIST_EN_I BIST_ADDR_I<2> ACLK_N_I ADDR_I<2> q_int<2> net04<6> VDD ++ VSS / RSC_IHPSG13_DFNQMX2IX1 +XDFF<1> BIST_EN_I BIST_ADDR_I<1> ACLK_N_I ADDR_I<1> q_int<1> net04<7> VDD ++ VSS / RSC_IHPSG13_DFNQMX2IX1 +XDFF<0> BIST_EN_I BIST_ADDR_I<0> ACLK_N_I ADDR_I<0> q_int<0> net04<8> VDD ++ VSS / RSC_IHPSG13_DFNQMX2IX1 +XDRV<8> qn_int<8> ADDR_N_O<8> VDD VSS / RSC_IHPSG13_CINVX8 +XDRV<7> qn_int<7> ADDR_N_O<7> VDD VSS / RSC_IHPSG13_CINVX8 +XDRV<6> qn_int<6> ADDR_N_O<6> VDD VSS / RSC_IHPSG13_CINVX8 +XDRV<5> qn_int<5> ADDR_N_O<5> VDD VSS / RSC_IHPSG13_CINVX8 +XDRV<4> qn_int<4> ADDR_N_O<4> VDD VSS / RSC_IHPSG13_CINVX8 +XDRV<3> qn_int<3> ADDR_N_O<3> VDD VSS / RSC_IHPSG13_CINVX8 +XDRV<2> qn_int<2> ADDR_N_O<2> VDD VSS / RSC_IHPSG13_CINVX8 +XDRV<1> qn_int<1> ADDR_N_O<1> VDD VSS / RSC_IHPSG13_CINVX8 +XDRV<0> qn_int<0> ADDR_N_O<0> VDD VSS / RSC_IHPSG13_CINVX8 +XINV<8> q_int<8> qn_int<8> VDD VSS / RSC_IHPSG13_CINVX2 +XINV<7> q_int<7> qn_int<7> VDD VSS / RSC_IHPSG13_CINVX2 +XINV<6> q_int<6> qn_int<6> VDD VSS / RSC_IHPSG13_CINVX2 +XINV<5> q_int<5> qn_int<5> VDD VSS / RSC_IHPSG13_CINVX2 +XINV<4> q_int<4> qn_int<4> VDD VSS / RSC_IHPSG13_CINVX2 +XINV<3> q_int<3> qn_int<3> VDD VSS / RSC_IHPSG13_CINVX2 +XINV<2> q_int<2> qn_int<2> VDD VSS / RSC_IHPSG13_CINVX2 +XINV<1> q_int<1> qn_int<1> VDD VSS / RSC_IHPSG13_CINVX2 +XINV<0> q_int<0> qn_int<0> VDD VSS / RSC_IHPSG13_CINVX2 +.ENDS + +.SUBCKT RM_IHPSG13_512x8_c3_2P_DLY_MUX A SEL Z VDD VSS +XI11 net4 Z VDD VSS / RSC_IHPSG13_CINVX2 +XI8 A D<3> SEL net4 VDD VSS / RSC_IHPSG13_MX2IX1 +XI20<3> D<2> D<3> VDD VSS / RSC_IHPSG13_CDLYX1 +XI20<2> D<1> D<2> VDD VSS / RSC_IHPSG13_CDLYX1 +XI20<1> A D<1> VDD VSS / RSC_IHPSG13_CDLYX1 +.ENDS +.SUBCKT RM_IHPSG13_512x8_c3_2P_CTRL ACLK_N BIST_CK_I BIST_CS_I BIST_EN BIST_RE_I ++ BIST_WE_I B_TIEL_O CK_I CS_I DCLK ECLK PULSE_H PULSE_L PULSE_O RCLK RE_I ++ ROW_CS WCLK WE_I VDD VSS +XI17 ck_regs we col_we VDD VSS / RSC_IHPSG13_DFNQX2 +XI16 ck_regs re col_re VDD VSS / RSC_IHPSG13_DFNQX2 +XI18 ck_regs cs net7 VDD VSS / RSC_IHPSG13_DFNQX2 +XI71 ACLK_N net012 PULSE_O VDD VSS / RSC_IHPSG13_DFNQX2 +XI77 col_we net017 net016 VDD VSS / RSC_IHPSG13_CNAND2X2 +XI76 col_re net017 net018 VDD VSS / RSC_IHPSG13_CNAND2X2 +XI15 ck_dly WEorREandCS aclk VDD VSS / RSC_IHPSG13_CGATEPX4 +XI14 ck WEandCS DCLK VDD VSS / RSC_IHPSG13_CGATEPX4 +XI60 net7 ROW_CS VDD VSS / RSC_IHPSG13_CBUFX8 +XI73 PULSE_O net012 VDD VSS / RSC_IHPSG13_CINVX2 +XI8 net017 net8 VDD VSS / RSC_IHPSG13_CINVX2 +XCAPS4<7> VDD VSS / RSC_IHPSG13_FILLCAP4 +XCAPS4<6> VDD VSS / RSC_IHPSG13_FILLCAP4 +XCAPS4<5> VDD VSS / RSC_IHPSG13_FILLCAP4 +XCAPS4<4> VDD VSS / RSC_IHPSG13_FILLCAP4 +XCAPS4<3> VDD VSS / RSC_IHPSG13_FILLCAP4 +XCAPS4<2> VDD VSS / RSC_IHPSG13_FILLCAP4 +XCAPS4<1> VDD VSS / RSC_IHPSG13_FILLCAP4 +XBM_TIEL B_TIEL_O VDD VSS / RSC_IHPSG13_TIEL +XI64 ck ck_dly VDD VSS / RSC_IHPSG13_CDLYX2 +XI86 CS_I BIST_CS_I BIST_EN cs VDD VSS / RSC_IHPSG13_MX2X2 +XI87 CK_I BIST_CK_I BIST_EN ck VDD VSS / RSC_IHPSG13_MX2X2 +XI85 WE_I BIST_WE_I BIST_EN we VDD VSS / RSC_IHPSG13_MX2X2 +XI84 RE_I BIST_RE_I BIST_EN re VDD VSS / RSC_IHPSG13_MX2X2 +XI48 ck_dly ck_regs VDD VSS / RSC_IHPSG13_CINVX4 +XI81 net016 WCLK VDD VSS / RSC_IHPSG13_CINVX4 +XI80 net018 RCLK VDD VSS / RSC_IHPSG13_CINVX4 +XI78 net8 net020 VDD VSS / RSC_IHPSG13_CINVX4 +XCAPS8<7> VDD VSS / RSC_IHPSG13_FILLCAP8 +XCAPS8<6> VDD VSS / RSC_IHPSG13_FILLCAP8 +XCAPS8<5> VDD VSS / RSC_IHPSG13_FILLCAP8 +XCAPS8<4> VDD VSS / RSC_IHPSG13_FILLCAP8 +XCAPS8<3> VDD VSS / RSC_IHPSG13_FILLCAP8 +XCAPS8<2> VDD VSS / RSC_IHPSG13_FILLCAP8 +XCAPS8<1> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI6 PULSE_L PULSE_H net017 VDD VSS / RSC_IHPSG13_XOR2X2 +XI22 we cs WEandCS VDD VSS / RSC_IHPSG13_AND2X2 +XI79 net020 ECLK VDD VSS / RSC_IHPSG13_CINVX8 +XI63 aclk ACLK_N VDD VSS / RSC_IHPSG13_CINVX8 +XI21 re we cs WEorREandCS VDD VSS / RSC_IHPSG13_OA12X1 +.ENDS +.SUBCKT RM_IHPSG13_512x8_c3_2P_COLDEC5 ACLK_N ADDR<4> ADDR<3> ADDR<2> ADDR<1> ADDR<0> ++ ADDR_COL<1> ADDR_COL<0> ADDR_DEC<7> ADDR_DEC<6> ADDR_DEC<5> ADDR_DEC<4> ++ ADDR_DEC<3> ADDR_DEC<2> ADDR_DEC<1> ADDR_DEC<0> BIST_ADDR<4> BIST_ADDR<3> ++ BIST_ADDR<2> BIST_ADDR<1> BIST_ADDR<0> BIST_EN_I VDD VSS +XI17<4> VDD VSS / RSC_IHPSG13_FILLCAP4 +XI17<3> VDD VSS / RSC_IHPSG13_FILLCAP4 +XI17<2> VDD VSS / RSC_IHPSG13_FILLCAP4 +XI17<1> VDD VSS / RSC_IHPSG13_FILLCAP4 +XI1<7> PADR<0> PADR<1> PADR<2> addr_n<7> VDD VSS / RSC_IHPSG13_NAND3X2 +XI1<6> NADR<0> PADR<1> PADR<2> addr_n<6> VDD VSS / RSC_IHPSG13_NAND3X2 +XI1<5> PADR<0> NADR<1> PADR<2> addr_n<5> VDD VSS / RSC_IHPSG13_NAND3X2 +XI1<4> NADR<0> NADR<1> PADR<2> addr_n<4> VDD VSS / RSC_IHPSG13_NAND3X2 +XI1<3> PADR<0> PADR<1> NADR<2> addr_n<3> VDD VSS / RSC_IHPSG13_NAND3X2 +XI1<2> NADR<0> PADR<1> NADR<2> addr_n<2> VDD VSS / RSC_IHPSG13_NAND3X2 +XI1<1> PADR<0> NADR<1> NADR<2> addr_n<1> VDD VSS / RSC_IHPSG13_NAND3X2 +XI1<0> NADR<0> NADR<1> NADR<2> addr_n<0> VDD VSS / RSC_IHPSG13_NAND3X2 +XDFF<4> BIST_EN_I BIST_ADDR<4> ACLK_N ADDR<4> addr_int<1> net13<0> VDD ++ VSS / RSC_IHPSG13_DFNQMX2IX1 +XDFF<3> BIST_EN_I BIST_ADDR<3> ACLK_N ADDR<3> addr_int<0> net13<1> VDD ++ VSS / RSC_IHPSG13_DFNQMX2IX1 +XDFF<2> BIST_EN_I BIST_ADDR<2> ACLK_N ADDR<2> padr_int<2> net13<2> VDD ++ VSS / RSC_IHPSG13_DFNQMX2IX1 +XDFF<1> BIST_EN_I BIST_ADDR<1> ACLK_N ADDR<1> padr_int<1> net13<3> VDD ++ VSS / RSC_IHPSG13_DFNQMX2IX1 +XDFF<0> BIST_EN_I BIST_ADDR<0> ACLK_N ADDR<0> padr_int<0> net13<4> VDD ++ VSS / RSC_IHPSG13_DFNQMX2IX1 +XI3<2> padr_int<2> NADR<2> VDD VSS / RSC_IHPSG13_INVX2 +XI3<1> padr_int<1> NADR<1> VDD VSS / RSC_IHPSG13_INVX2 +XI3<0> padr_int<0> NADR<0> VDD VSS / RSC_IHPSG13_INVX2 +XI2<7> addr_n<7> ADDR_DEC<7> VDD VSS / RSC_IHPSG13_INVX2 +XI2<6> addr_n<6> ADDR_DEC<6> VDD VSS / RSC_IHPSG13_INVX2 +XI2<5> addr_n<5> ADDR_DEC<5> VDD VSS / RSC_IHPSG13_INVX2 +XI2<4> addr_n<4> ADDR_DEC<4> VDD VSS / RSC_IHPSG13_INVX2 +XI2<3> addr_n<3> ADDR_DEC<3> VDD VSS / RSC_IHPSG13_INVX2 +XI2<2> addr_n<2> ADDR_DEC<2> VDD VSS / RSC_IHPSG13_INVX2 +XI2<1> addr_n<1> ADDR_DEC<1> VDD VSS / RSC_IHPSG13_INVX2 +XI2<0> addr_n<0> ADDR_DEC<0> VDD VSS / RSC_IHPSG13_INVX2 +XI15<2> NADR<2> PADR<2> VDD VSS / RSC_IHPSG13_INVX2 +XI15<1> NADR<1> PADR<1> VDD VSS / RSC_IHPSG13_INVX2 +XI15<0> NADR<0> PADR<0> VDD VSS / RSC_IHPSG13_INVX2 +XI13<1> addr_int<1> ADDR_COL<1> VDD VSS / RSC_IHPSG13_CBUFX2 +XI13<0> addr_int<0> ADDR_COL<0> VDD VSS / RSC_IHPSG13_CBUFX2 +XI14<5> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI14<4> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI14<3> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI14<2> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI14<1> VDD VSS / RSC_IHPSG13_FILLCAP8 +.ENDS +.SUBCKT RM_IHPSG13_512x8_c3_2P_BLDRV A_BLC<3> A_BLC<2> A_BLC<1> A_BLC<0> A_BLC_SEL ++ A_BLT<3> A_BLT<2> A_BLT<1> A_BLT<0> A_BLT_SEL A_PRE_N A_SEL_P<3> A_SEL_P<2> ++ A_SEL_P<1> A_SEL_P<0> A_WR_ONE A_WR_ZERO B_BLC<3> B_BLC<2> B_BLC<1> B_BLC<0> ++ B_BLC_SEL B_BLT<3> B_BLT<2> B_BLT<1> B_BLT<0> B_BLT_SEL B_PRE_N B_SEL_P<3> ++ B_SEL_P<2> B_SEL_P<1> B_SEL_P<0> B_WR_ONE B_WR_ZERO VDD VSS +MA_CWN<3> A_BLC<3> A_BLC_NMOS_DRIVE<3> VSS VSS sg13_lv_nmos m=1 ++ w=4.82u l=130.00n ng=2 nrd=0 nrs=0 +MA_CWN<2> A_BLC<2> A_BLC_NMOS_DRIVE<2> VSS VSS sg13_lv_nmos m=1 ++ w=4.82u l=130.00n ng=2 nrd=0 nrs=0 +MA_CWN<1> A_BLC<1> A_BLC_NMOS_DRIVE<1> VSS VSS sg13_lv_nmos m=1 ++ w=4.82u l=130.00n ng=2 nrd=0 nrs=0 +MA_CWN<0> A_BLC<0> A_BLC_NMOS_DRIVE<0> VSS VSS sg13_lv_nmos m=1 ++ w=4.82u l=130.00n ng=2 nrd=0 nrs=0 +MA_TWN<3> A_BLT<3> A_BLT_NMOS_DRIVE<3> VSS VSS sg13_lv_nmos m=1 ++ w=4.82u l=130.00n ng=2 nrd=0 nrs=0 +MA_TWN<2> A_BLT<2> A_BLT_NMOS_DRIVE<2> VSS VSS sg13_lv_nmos m=1 ++ w=4.82u l=130.00n ng=2 nrd=0 nrs=0 +MA_TWN<1> A_BLT<1> A_BLT_NMOS_DRIVE<1> VSS VSS sg13_lv_nmos m=1 ++ w=4.82u l=130.00n ng=2 nrd=0 nrs=0 +MA_TWN<0> A_BLT<0> A_BLT_NMOS_DRIVE<0> VSS VSS sg13_lv_nmos m=1 ++ w=4.82u l=130.00n ng=2 nrd=0 nrs=0 +MB_TWN<3> B_BLT<3> B_BLT_NMOS_DRIVE<3> VSS VSS sg13_lv_nmos m=1 ++ w=4.82u l=130.00n ng=2 nrd=0 nrs=0 +MB_TWN<2> B_BLT<2> B_BLT_NMOS_DRIVE<2> VSS VSS sg13_lv_nmos m=1 ++ w=4.82u l=130.00n ng=2 nrd=0 nrs=0 +MB_TWN<1> B_BLT<1> B_BLT_NMOS_DRIVE<1> VSS VSS sg13_lv_nmos m=1 ++ w=4.82u l=130.00n ng=2 nrd=0 nrs=0 +MB_TWN<0> B_BLT<0> B_BLT_NMOS_DRIVE<0> VSS VSS sg13_lv_nmos m=1 ++ w=4.82u l=130.00n ng=2 nrd=0 nrs=0 +MB_CWN<3> B_BLC<3> B_BLC_NMOS_DRIVE<3> VSS VSS sg13_lv_nmos m=1 ++ w=4.82u l=130.00n ng=2 nrd=0 nrs=0 +MB_CWN<2> B_BLC<2> B_BLC_NMOS_DRIVE<2> VSS VSS sg13_lv_nmos m=1 ++ w=4.82u l=130.00n ng=2 nrd=0 nrs=0 +MB_CWN<1> B_BLC<1> B_BLC_NMOS_DRIVE<1> VSS VSS sg13_lv_nmos m=1 ++ w=4.82u l=130.00n ng=2 nrd=0 nrs=0 +MB_CWN<0> B_BLC<0> B_BLC_NMOS_DRIVE<0> VSS VSS sg13_lv_nmos m=1 ++ w=4.82u l=130.00n ng=2 nrd=0 nrs=0 +MA_CPR<3> A_BLC<3> A_PRE_N VDD VDD sg13_lv_pmos m=1 w=3.000u l=130.00n ++ ng=2 nrd=0 nrs=0 +MA_CPR<2> A_BLC<2> A_PRE_N VDD VDD sg13_lv_pmos m=1 w=3.000u l=130.00n ++ ng=2 nrd=0 nrs=0 +MA_CPR<1> A_BLC<1> A_PRE_N VDD VDD sg13_lv_pmos m=1 w=3.000u l=130.00n ++ ng=2 nrd=0 nrs=0 +MA_CPR<0> A_BLC<0> A_PRE_N VDD VDD sg13_lv_pmos m=1 w=3.000u l=130.00n ++ ng=2 nrd=0 nrs=0 +MA_TWP<3> A_BLT<3> A_BLT_PMOS_DRIVE<3> VDD VDD sg13_lv_pmos m=1 w=1.5u ++ l=130.00n ng=1 nrd=0 nrs=0 +MA_TWP<2> A_BLT<2> A_BLT_PMOS_DRIVE<2> VDD VDD sg13_lv_pmos m=1 w=1.5u ++ l=130.00n ng=1 nrd=0 nrs=0 +MA_TWP<1> A_BLT<1> A_BLT_PMOS_DRIVE<1> VDD VDD sg13_lv_pmos m=1 w=1.5u ++ l=130.00n ng=1 nrd=0 nrs=0 +MA_TWP<0> A_BLT<0> A_BLT_PMOS_DRIVE<0> VDD VDD sg13_lv_pmos m=1 w=1.5u ++ l=130.00n ng=1 nrd=0 nrs=0 +MA_CWP<3> A_BLC<3> A_BLC_PMOS_DRIVE<3> VDD VDD sg13_lv_pmos m=1 w=1.5u ++ l=130.00n ng=1 nrd=0 nrs=0 +MA_CWP<2> A_BLC<2> A_BLC_PMOS_DRIVE<2> VDD VDD sg13_lv_pmos m=1 w=1.5u ++ l=130.00n ng=1 nrd=0 nrs=0 +MA_CWP<1> A_BLC<1> A_BLC_PMOS_DRIVE<1> VDD VDD sg13_lv_pmos m=1 w=1.5u ++ l=130.00n ng=1 nrd=0 nrs=0 +MA_CWP<0> A_BLC<0> A_BLC_PMOS_DRIVE<0> VDD VDD sg13_lv_pmos m=1 w=1.5u ++ l=130.00n ng=1 nrd=0 nrs=0 +MA_TPR<3> A_BLT<3> A_PRE_N VDD VDD sg13_lv_pmos m=1 w=3.000u l=130.00n ++ ng=2 nrd=0 nrs=0 +MA_TPR<2> A_BLT<2> A_PRE_N VDD VDD sg13_lv_pmos m=1 w=3.000u l=130.00n ++ ng=2 nrd=0 nrs=0 +MA_TPR<1> A_BLT<1> A_PRE_N VDD VDD sg13_lv_pmos m=1 w=3.000u l=130.00n ++ ng=2 nrd=0 nrs=0 +MA_TPR<0> A_BLT<0> A_PRE_N VDD VDD sg13_lv_pmos m=1 w=3.000u l=130.00n ++ ng=2 nrd=0 nrs=0 +MA_TSP<3> A_BLT_SEL A_SEL_N<3> A_BLT<3> VDD sg13_lv_pmos m=1 w=1.5u ++ l=130.00n ng=1 nrd=0 nrs=0 +MA_TSP<2> A_BLT_SEL A_SEL_N<2> A_BLT<2> VDD sg13_lv_pmos m=1 w=1.5u ++ l=130.00n ng=1 nrd=0 nrs=0 +MA_TSP<1> A_BLT_SEL A_SEL_N<1> A_BLT<1> VDD sg13_lv_pmos m=1 w=1.5u ++ l=130.00n ng=1 nrd=0 nrs=0 +MA_TSP<0> A_BLT_SEL A_SEL_N<0> A_BLT<0> VDD sg13_lv_pmos m=1 w=1.5u ++ l=130.00n ng=1 nrd=0 nrs=0 +MA_CSP<3> A_BLC_SEL A_SEL_N<3> A_BLC<3> VDD sg13_lv_pmos m=1 w=1.5u ++ l=130.00n ng=1 nrd=0 nrs=0 +MA_CSP<2> A_BLC_SEL A_SEL_N<2> A_BLC<2> VDD sg13_lv_pmos m=1 w=1.5u ++ l=130.00n ng=1 nrd=0 nrs=0 +MA_CSP<1> A_BLC_SEL A_SEL_N<1> A_BLC<1> VDD sg13_lv_pmos m=1 w=1.5u ++ l=130.00n ng=1 nrd=0 nrs=0 +MA_CSP<0> A_BLC_SEL A_SEL_N<0> A_BLC<0> VDD sg13_lv_pmos m=1 w=1.5u ++ l=130.00n ng=1 nrd=0 nrs=0 +MB_CWP<3> B_BLC<3> B_BLC_PMOS_DRIVE<3> VDD VDD sg13_lv_pmos m=1 w=1.5u ++ l=130.00n ng=1 nrd=0 nrs=0 +MB_CWP<2> B_BLC<2> B_BLC_PMOS_DRIVE<2> VDD VDD sg13_lv_pmos m=1 w=1.5u ++ l=130.00n ng=1 nrd=0 nrs=0 +MB_CWP<1> B_BLC<1> B_BLC_PMOS_DRIVE<1> VDD VDD sg13_lv_pmos m=1 w=1.5u ++ l=130.00n ng=1 nrd=0 nrs=0 +MB_CWP<0> B_BLC<0> B_BLC_PMOS_DRIVE<0> VDD VDD sg13_lv_pmos m=1 w=1.5u ++ l=130.00n ng=1 nrd=0 nrs=0 +MB_TWP<3> B_BLT<3> B_BLT_PMOS_DRIVE<3> VDD VDD sg13_lv_pmos m=1 w=1.5u ++ l=130.00n ng=1 nrd=0 nrs=0 +MB_TWP<2> B_BLT<2> B_BLT_PMOS_DRIVE<2> VDD VDD sg13_lv_pmos m=1 w=1.5u ++ l=130.00n ng=1 nrd=0 nrs=0 +MB_TWP<1> B_BLT<1> B_BLT_PMOS_DRIVE<1> VDD VDD sg13_lv_pmos m=1 w=1.5u ++ l=130.00n ng=1 nrd=0 nrs=0 +MB_TWP<0> B_BLT<0> B_BLT_PMOS_DRIVE<0> VDD VDD sg13_lv_pmos m=1 w=1.5u ++ l=130.00n ng=1 nrd=0 nrs=0 +MB_TSP<3> B_BLT_SEL B_SEL_N<3> B_BLT<3> VDD sg13_lv_pmos m=1 w=1.5u ++ l=130.00n ng=1 nrd=0 nrs=0 +MB_TSP<2> B_BLT_SEL B_SEL_N<2> B_BLT<2> VDD sg13_lv_pmos m=1 w=1.5u ++ l=130.00n ng=1 nrd=0 nrs=0 +MB_TSP<1> B_BLT_SEL B_SEL_N<1> B_BLT<1> VDD sg13_lv_pmos m=1 w=1.5u ++ l=130.00n ng=1 nrd=0 nrs=0 +MB_TSP<0> B_BLT_SEL B_SEL_N<0> B_BLT<0> VDD sg13_lv_pmos m=1 w=1.5u ++ l=130.00n ng=1 nrd=0 nrs=0 +MB_TPR<3> B_BLT<3> B_PRE_N VDD VDD sg13_lv_pmos m=1 w=3.000u l=130.00n ++ ng=2 nrd=0 nrs=0 +MB_TPR<2> B_BLT<2> B_PRE_N VDD VDD sg13_lv_pmos m=1 w=3.000u l=130.00n ++ ng=2 nrd=0 nrs=0 +MB_TPR<1> B_BLT<1> B_PRE_N VDD VDD sg13_lv_pmos m=1 w=3.000u l=130.00n ++ ng=2 nrd=0 nrs=0 +MB_TPR<0> B_BLT<0> B_PRE_N VDD VDD sg13_lv_pmos m=1 w=3.000u l=130.00n ++ ng=2 nrd=0 nrs=0 +MB_CSP<3> B_BLC_SEL B_SEL_N<3> B_BLC<3> VDD sg13_lv_pmos m=1 w=1.5u ++ l=130.00n ng=1 nrd=0 nrs=0 +MB_CSP<2> B_BLC_SEL B_SEL_N<2> B_BLC<2> VDD sg13_lv_pmos m=1 w=1.5u ++ l=130.00n ng=1 nrd=0 nrs=0 +MB_CSP<1> B_BLC_SEL B_SEL_N<1> B_BLC<1> VDD sg13_lv_pmos m=1 w=1.5u ++ l=130.00n ng=1 nrd=0 nrs=0 +MB_CSP<0> B_BLC_SEL B_SEL_N<0> B_BLC<0> VDD sg13_lv_pmos m=1 w=1.5u ++ l=130.00n ng=1 nrd=0 nrs=0 +MB_CPR<3> B_BLC<3> B_PRE_N VDD VDD sg13_lv_pmos m=1 w=3.000u l=130.00n ++ ng=2 nrd=0 nrs=0 +MB_CPR<2> B_BLC<2> B_PRE_N VDD VDD sg13_lv_pmos m=1 w=3.000u l=130.00n ++ ng=2 nrd=0 nrs=0 +MB_CPR<1> B_BLC<1> B_PRE_N VDD VDD sg13_lv_pmos m=1 w=3.000u l=130.00n ++ ng=2 nrd=0 nrs=0 +MB_CPR<0> B_BLC<0> B_PRE_N VDD VDD sg13_lv_pmos m=1 w=3.000u l=130.00n ++ ng=2 nrd=0 nrs=0 +XA_SEL<3> A_SEL_P<3> A_SEL_N<3> VDD VSS / RSC_IHPSG13_INVX2 +XA_SEL<2> A_SEL_P<2> A_SEL_N<2> VDD VSS / RSC_IHPSG13_INVX2 +XA_SEL<1> A_SEL_P<1> A_SEL_N<1> VDD VSS / RSC_IHPSG13_INVX2 +XA_SEL<0> A_SEL_P<0> A_SEL_N<0> VDD VSS / RSC_IHPSG13_INVX2 +XA_CINV<3> A_BLT_PMOS_DRIVE<3> A_BLC_NMOS_DRIVE<3> VDD VSS / ++ RSC_IHPSG13_INVX2 +XA_CINV<2> A_BLT_PMOS_DRIVE<2> A_BLC_NMOS_DRIVE<2> VDD VSS / ++ RSC_IHPSG13_INVX2 +XA_CINV<1> A_BLT_PMOS_DRIVE<1> A_BLC_NMOS_DRIVE<1> VDD VSS / ++ RSC_IHPSG13_INVX2 +XA_CINV<0> A_BLT_PMOS_DRIVE<0> A_BLC_NMOS_DRIVE<0> VDD VSS / ++ RSC_IHPSG13_INVX2 +XA_TINV<3> A_BLC_PMOS_DRIVE<3> A_BLT_NMOS_DRIVE<3> VDD VSS / ++ RSC_IHPSG13_INVX2 +XA_TINV<2> A_BLC_PMOS_DRIVE<2> A_BLT_NMOS_DRIVE<2> VDD VSS / ++ RSC_IHPSG13_INVX2 +XA_TINV<1> A_BLC_PMOS_DRIVE<1> A_BLT_NMOS_DRIVE<1> VDD VSS / ++ RSC_IHPSG13_INVX2 +XA_TINV<0> A_BLC_PMOS_DRIVE<0> A_BLT_NMOS_DRIVE<0> VDD VSS / ++ RSC_IHPSG13_INVX2 +XB_SEL<3> B_SEL_P<3> B_SEL_N<3> VDD VSS / RSC_IHPSG13_INVX2 +XB_SEL<2> B_SEL_P<2> B_SEL_N<2> VDD VSS / RSC_IHPSG13_INVX2 +XB_SEL<1> B_SEL_P<1> B_SEL_N<1> VDD VSS / RSC_IHPSG13_INVX2 +XB_SEL<0> B_SEL_P<0> B_SEL_N<0> VDD VSS / RSC_IHPSG13_INVX2 +XB_TINV<3> B_BLC_PMOS_DRIVE<3> B_BLT_NMOS_DRIVE<3> VDD VSS / ++ RSC_IHPSG13_INVX2 +XB_TINV<2> B_BLC_PMOS_DRIVE<2> B_BLT_NMOS_DRIVE<2> VDD VSS / ++ RSC_IHPSG13_INVX2 +XB_TINV<1> B_BLC_PMOS_DRIVE<1> B_BLT_NMOS_DRIVE<1> VDD VSS / ++ RSC_IHPSG13_INVX2 +XB_TINV<0> B_BLC_PMOS_DRIVE<0> B_BLT_NMOS_DRIVE<0> VDD VSS / ++ RSC_IHPSG13_INVX2 +XB_CINV<3> B_BLT_PMOS_DRIVE<3> B_BLC_NMOS_DRIVE<3> VDD VSS / ++ RSC_IHPSG13_INVX2 +XB_CINV<2> B_BLT_PMOS_DRIVE<2> B_BLC_NMOS_DRIVE<2> VDD VSS / ++ RSC_IHPSG13_INVX2 +XB_CINV<1> B_BLT_PMOS_DRIVE<1> B_BLC_NMOS_DRIVE<1> VDD VSS / ++ RSC_IHPSG13_INVX2 +XB_CINV<0> B_BLT_PMOS_DRIVE<0> B_BLC_NMOS_DRIVE<0> VDD VSS / ++ RSC_IHPSG13_INVX2 +XA_TDEC<3> A_SEL_P<3> A_WR_ONE A_BLT_PMOS_DRIVE<3> VDD VSS / ++ RSC_IHPSG13_NAND2X2 +XA_TDEC<2> A_SEL_P<2> A_WR_ONE A_BLT_PMOS_DRIVE<2> VDD VSS / ++ RSC_IHPSG13_NAND2X2 +XA_TDEC<1> A_SEL_P<1> A_WR_ONE A_BLT_PMOS_DRIVE<1> VDD VSS / ++ RSC_IHPSG13_NAND2X2 +XA_TDEC<0> A_SEL_P<0> A_WR_ONE A_BLT_PMOS_DRIVE<0> VDD VSS / ++ RSC_IHPSG13_NAND2X2 +XA_CDEC<3> A_SEL_P<3> A_WR_ZERO A_BLC_PMOS_DRIVE<3> VDD VSS / ++ RSC_IHPSG13_NAND2X2 +XA_CDEC<2> A_SEL_P<2> A_WR_ZERO A_BLC_PMOS_DRIVE<2> VDD VSS / ++ RSC_IHPSG13_NAND2X2 +XA_CDEC<1> A_SEL_P<1> A_WR_ZERO A_BLC_PMOS_DRIVE<1> VDD VSS / ++ RSC_IHPSG13_NAND2X2 +XA_CDEC<0> A_SEL_P<0> A_WR_ZERO A_BLC_PMOS_DRIVE<0> VDD VSS / ++ RSC_IHPSG13_NAND2X2 +XB_CDEC<3> B_SEL_P<3> B_WR_ZERO B_BLC_PMOS_DRIVE<3> VDD VSS / ++ RSC_IHPSG13_NAND2X2 +XB_CDEC<2> B_SEL_P<2> B_WR_ZERO B_BLC_PMOS_DRIVE<2> VDD VSS / ++ RSC_IHPSG13_NAND2X2 +XB_CDEC<1> B_SEL_P<1> B_WR_ZERO B_BLC_PMOS_DRIVE<1> VDD VSS / ++ RSC_IHPSG13_NAND2X2 +XB_CDEC<0> B_SEL_P<0> B_WR_ZERO B_BLC_PMOS_DRIVE<0> VDD VSS / ++ RSC_IHPSG13_NAND2X2 +XB_TDEC<3> B_SEL_P<3> B_WR_ONE B_BLT_PMOS_DRIVE<3> VDD VSS / ++ RSC_IHPSG13_NAND2X2 +XB_TDEC<2> B_SEL_P<2> B_WR_ONE B_BLT_PMOS_DRIVE<2> VDD VSS / ++ RSC_IHPSG13_NAND2X2 +XB_TDEC<1> B_SEL_P<1> B_WR_ONE B_BLT_PMOS_DRIVE<1> VDD VSS / ++ RSC_IHPSG13_NAND2X2 +XB_TDEC<0> B_SEL_P<0> B_WR_ONE B_BLT_PMOS_DRIVE<0> VDD VSS / ++ RSC_IHPSG13_NAND2X2 +.ENDS +.SUBCKT RSC_IHPSG13_AND2X6 A B Z VDD VSS +MN3 Z net6 VSS VSS sg13_lv_nmos m=1 w=2.94u l=130.00n ng=3 nrd=0 nrs=0 +MN4 net9 B VSS VSS sg13_lv_nmos m=1 w=500.0n l=130.00n ng=1 nrd=0 nrs=0 +MN6 net6 A net9 VSS sg13_lv_nmos m=1 w=500.0n l=130.00n ng=1 nrd=0 nrs=0 +MP2 Z net6 VDD VDD sg13_lv_pmos m=1 w=4.86u l=130.00n ng=3 nrd=0 nrs=0 +MP0 net6 B VDD VDD sg13_lv_pmos m=1 w=860.00n l=130.00n ng=1 nrd=0 ++ nrs=0 +MP1 net6 A VDD VDD sg13_lv_pmos m=1 w=860.00n l=130.00n ng=1 nrd=0 ++ nrs=0 +.ENDS +.SUBCKT RM_IHPSG13_512x8_c3_2P_COLCTRL5 A_ADDR_COL<1> A_ADDR_COL<0> A_ADDR_DEC<7> ++ A_ADDR_DEC<6> A_ADDR_DEC<5> A_ADDR_DEC<4> A_ADDR_DEC<3> A_ADDR_DEC<2> ++ A_ADDR_DEC<1> A_ADDR_DEC<0> A_BIST_BM_I A_BIST_DW_I A_BIST_EN_I A_BLC<31> ++ A_BLC<30> A_BLC<29> A_BLC<28> A_BLC<27> A_BLC<26> A_BLC<25> A_BLC<24> ++ A_BLC<23> A_BLC<22> A_BLC<21> A_BLC<20> A_BLC<19> A_BLC<18> A_BLC<17> ++ A_BLC<16> A_BLC<15> A_BLC<14> A_BLC<13> A_BLC<12> A_BLC<11> A_BLC<10> ++ A_BLC<9> A_BLC<8> A_BLC<7> A_BLC<6> A_BLC<5> A_BLC<4> A_BLC<3> A_BLC<2> ++ A_BLC<1> A_BLC<0> A_BLT<31> A_BLT<30> A_BLT<29> A_BLT<28> A_BLT<27> ++ A_BLT<26> A_BLT<25> A_BLT<24> A_BLT<23> A_BLT<22> A_BLT<21> A_BLT<20> ++ A_BLT<19> A_BLT<18> A_BLT<17> A_BLT<16> A_BLT<15> A_BLT<14> A_BLT<13> ++ A_BLT<12> A_BLT<11> A_BLT<10> A_BLT<9> A_BLT<8> A_BLT<7> A_BLT<6> A_BLT<5> ++ A_BLT<4> A_BLT<3> A_BLT<2> A_BLT<1> A_BLT<0> A_BM_I A_DCLK_B_L A_DCLK_B_R ++ A_DCLK_L A_DCLK_R A_DR_O A_DW_I A_RCLK_B_L A_RCLK_B_R A_RCLK_L A_RCLK_R ++ A_TIEH_O A_WCLK_B_L A_WCLK_B_R A_WCLK_L A_WCLK_R B_ADDR_COL<1> B_ADDR_COL<0> ++ B_ADDR_DEC<7> B_ADDR_DEC<6> B_ADDR_DEC<5> B_ADDR_DEC<4> B_ADDR_DEC<3> ++ B_ADDR_DEC<2> B_ADDR_DEC<1> B_ADDR_DEC<0> B_BIST_BM_I B_BIST_DW_I ++ B_BIST_EN_I B_BLC<31> B_BLC<30> B_BLC<29> B_BLC<28> B_BLC<27> B_BLC<26> ++ B_BLC<25> B_BLC<24> B_BLC<23> B_BLC<22> B_BLC<21> B_BLC<20> B_BLC<19> ++ B_BLC<18> B_BLC<17> B_BLC<16> B_BLC<15> B_BLC<14> B_BLC<13> B_BLC<12> ++ B_BLC<11> B_BLC<10> B_BLC<9> B_BLC<8> B_BLC<7> B_BLC<6> B_BLC<5> B_BLC<4> ++ B_BLC<3> B_BLC<2> B_BLC<1> B_BLC<0> B_BLT<31> B_BLT<30> B_BLT<29> B_BLT<28> ++ B_BLT<27> B_BLT<26> B_BLT<25> B_BLT<24> B_BLT<23> B_BLT<22> B_BLT<21> ++ B_BLT<20> B_BLT<19> B_BLT<18> B_BLT<17> B_BLT<16> B_BLT<15> B_BLT<14> ++ B_BLT<13> B_BLT<12> B_BLT<11> B_BLT<10> B_BLT<9> B_BLT<8> B_BLT<7> B_BLT<6> ++ B_BLT<5> B_BLT<4> B_BLT<3> B_BLT<2> B_BLT<1> B_BLT<0> B_BM_I B_DCLK_B_L ++ B_DCLK_B_R B_DCLK_L B_DCLK_R B_DR_O B_DW_I B_RCLK_B_L B_RCLK_B_R B_RCLK_L ++ B_RCLK_R B_TIEH_O B_WCLK_B_L B_WCLK_B_R B_WCLK_L B_WCLK_R VDD VSS +XB_I80<1> B_WCLK_B_L B_RCLK_B_L B_W_nor_R<1> VDD VSS / ++ RSC_IHPSG13_AND2X2 +XB_I80<0> B_WCLK_B_L B_RCLK_B_L B_W_nor_R<0> VDD VSS / ++ RSC_IHPSG13_AND2X2 +XA_I80<1> A_WCLK_B_L A_RCLK_B_L A_W_nor_R<1> VDD VSS / ++ RSC_IHPSG13_AND2X2 +XA_I80<0> A_WCLK_B_L A_RCLK_B_L A_W_nor_R<0> VDD VSS / ++ RSC_IHPSG13_AND2X2 +XB_I44 B_BM_N B_WCLK_B_L B_DO_WRITE_P VDD VSS / RSC_IHPSG13_NOR2X2 +XA_I44 A_BM_N A_WCLK_B_L A_DO_WRITE_P VDD VSS / RSC_IHPSG13_NOR2X2 +XI_FILL4<16> VDD VSS / RSC_IHPSG13_FILLCAP4 +XI_FILL4<15> VDD VSS / RSC_IHPSG13_FILLCAP4 +XI_FILL4<14> VDD VSS / RSC_IHPSG13_FILLCAP4 +XI_FILL4<13> VDD VSS / RSC_IHPSG13_FILLCAP4 +XI_FILL4<12> VDD VSS / RSC_IHPSG13_FILLCAP4 +XI_FILL4<11> VDD VSS / RSC_IHPSG13_FILLCAP4 +XI_FILL4<10> VDD VSS / RSC_IHPSG13_FILLCAP4 +XI_FILL4<9> VDD VSS / RSC_IHPSG13_FILLCAP4 +XI_FILL4<8> VDD VSS / RSC_IHPSG13_FILLCAP4 +XI_FILL4<7> VDD VSS / RSC_IHPSG13_FILLCAP4 +XI_FILL4<6> VDD VSS / RSC_IHPSG13_FILLCAP4 +XI_FILL4<5> VDD VSS / RSC_IHPSG13_FILLCAP4 +XI_FILL4<4> VDD VSS / RSC_IHPSG13_FILLCAP4 +XI_FILL4<3> VDD VSS / RSC_IHPSG13_FILLCAP4 +XI_FILL4<2> VDD VSS / RSC_IHPSG13_FILLCAP4 +XI_FILL4<1> VDD VSS / RSC_IHPSG13_FILLCAP4 +XB_INV<6> B_N1<1> B_P1<1> VDD VSS / RSC_IHPSG13_CINVX4 +XB_INV<5> B_N0<1> B_P0<1> VDD VSS / RSC_IHPSG13_CINVX4 +XB_INV<4> B_N0<0> B_P0<0> VDD VSS / RSC_IHPSG13_CINVX4 +XB_INV<3> B_ADDR_COL<1> B_N1<1> VDD VSS / RSC_IHPSG13_CINVX4 +XB_INV<2> B_ADDR_COL<1> B_N1<0> VDD VSS / RSC_IHPSG13_CINVX4 +XB_INV<1> B_ADDR_COL<0> B_N0<1> VDD VSS / RSC_IHPSG13_CINVX4 +XB_INV<0> B_ADDR_COL<0> B_N0<0> VDD VSS / RSC_IHPSG13_CINVX4 +XA_INV<6> A_N1<1> A_P1<1> VDD VSS / RSC_IHPSG13_CINVX4 +XA_INV<5> A_N0<1> A_P0<1> VDD VSS / RSC_IHPSG13_CINVX4 +XA_INV<4> A_N0<0> A_P0<0> VDD VSS / RSC_IHPSG13_CINVX4 +XA_INV<3> A_ADDR_COL<1> A_N1<1> VDD VSS / RSC_IHPSG13_CINVX4 +XA_INV<2> A_ADDR_COL<1> A_N1<0> VDD VSS / RSC_IHPSG13_CINVX4 +XA_INV<1> A_ADDR_COL<0> A_N0<1> VDD VSS / RSC_IHPSG13_CINVX4 +XA_INV<0> A_ADDR_COL<0> A_N0<0> VDD VSS / RSC_IHPSG13_CINVX4 +XB_I81<3> B_W_nor_R<1> B_PRE_N VDD VSS / RSC_IHPSG13_CINVX4_WN +XB_I81<2> B_W_nor_R<1> B_PRE_N VDD VSS / RSC_IHPSG13_CINVX4_WN +XB_I81<1> B_W_nor_R<0> B_PRE_N VDD VSS / RSC_IHPSG13_CINVX4_WN +XB_I81<0> B_W_nor_R<0> B_PRE_N VDD VSS / RSC_IHPSG13_CINVX4_WN +XA_I81<3> A_W_nor_R<1> A_PRE_N VDD VSS / RSC_IHPSG13_CINVX4_WN +XA_I81<2> A_W_nor_R<1> A_PRE_N VDD VSS / RSC_IHPSG13_CINVX4_WN +XA_I81<1> A_W_nor_R<0> A_PRE_N VDD VSS / RSC_IHPSG13_CINVX4_WN +XA_I81<0> A_W_nor_R<0> A_PRE_N VDD VSS / RSC_IHPSG13_CINVX4_WN +XI_FILL8<78> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI_FILL8<77> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI_FILL8<76> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI_FILL8<75> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI_FILL8<74> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI_FILL8<73> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI_FILL8<72> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI_FILL8<71> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI_FILL8<70> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI_FILL8<69> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI_FILL8<68> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI_FILL8<67> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI_FILL8<66> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI_FILL8<65> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI_FILL8<64> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI_FILL8<63> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI_FILL8<62> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI_FILL8<61> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI_FILL8<60> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI_FILL8<59> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI_FILL8<58> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI_FILL8<57> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI_FILL8<56> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI_FILL8<55> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI_FILL8<54> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI_FILL8<53> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI_FILL8<52> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI_FILL8<51> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI_FILL8<50> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI_FILL8<49> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI_FILL8<48> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI_FILL8<47> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI_FILL8<46> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI_FILL8<45> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI_FILL8<44> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI_FILL8<43> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI_FILL8<42> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI_FILL8<41> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI_FILL8<40> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI_FILL8<39> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI_FILL8<38> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI_FILL8<37> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI_FILL8<36> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI_FILL8<35> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI_FILL8<34> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI_FILL8<33> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI_FILL8<32> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI_FILL8<31> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI_FILL8<30> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI_FILL8<29> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI_FILL8<28> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI_FILL8<27> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI_FILL8<26> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI_FILL8<25> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI_FILL8<24> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI_FILL8<23> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI_FILL8<22> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI_FILL8<21> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI_FILL8<20> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI_FILL8<19> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI_FILL8<18> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI_FILL8<17> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI_FILL8<16> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI_FILL8<15> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI_FILL8<14> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI_FILL8<13> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI_FILL8<12> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI_FILL8<11> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI_FILL8<10> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI_FILL8<9> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI_FILL8<8> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI_FILL8<7> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI_FILL8<6> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI_FILL8<5> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI_FILL8<4> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI_FILL8<3> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI_FILL8<2> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI_FILL8<1> VDD VSS / RSC_IHPSG13_FILLCAP8 +XAB_BLMUX<7> A_BLC<31> A_BLC<30> A_BLC<29> A_BLC<28> A_BLC_SEL A_BLT<31> ++ A_BLT<30> A_BLT<29> A_BLT<28> A_BLT_SEL A_PRE_N A_SEL_P<31> A_SEL_P<30> ++ A_SEL_P<29> A_SEL_P<28> A_WR_ONE A_WR_ZERO B_BLC<31> B_BLC<30> B_BLC<29> ++ B_BLC<28> B_BLC_SEL B_BLT<31> B_BLT<30> B_BLT<29> B_BLT<28> B_BLT_SEL ++ B_PRE_N B_SEL_P<31> B_SEL_P<30> B_SEL_P<29> B_SEL_P<28> B_WR_ONE B_WR_ZERO ++ VDD VSS / RM_IHPSG13_512x8_c3_2P_BLDRV +XAB_BLMUX<6> A_BLC<27> A_BLC<26> A_BLC<25> A_BLC<24> A_BLC_SEL A_BLT<27> ++ A_BLT<26> A_BLT<25> A_BLT<24> A_BLT_SEL A_PRE_N A_SEL_P<27> A_SEL_P<26> ++ A_SEL_P<25> A_SEL_P<24> A_WR_ONE A_WR_ZERO B_BLC<27> B_BLC<26> B_BLC<25> ++ B_BLC<24> B_BLC_SEL B_BLT<27> B_BLT<26> B_BLT<25> B_BLT<24> B_BLT_SEL ++ B_PRE_N B_SEL_P<27> B_SEL_P<26> B_SEL_P<25> B_SEL_P<24> B_WR_ONE B_WR_ZERO ++ VDD VSS / RM_IHPSG13_512x8_c3_2P_BLDRV +XAB_BLMUX<5> A_BLC<23> A_BLC<22> A_BLC<21> A_BLC<20> A_BLC_SEL A_BLT<23> ++ A_BLT<22> A_BLT<21> A_BLT<20> A_BLT_SEL A_PRE_N A_SEL_P<23> A_SEL_P<22> ++ A_SEL_P<21> A_SEL_P<20> A_WR_ONE A_WR_ZERO B_BLC<23> B_BLC<22> B_BLC<21> ++ B_BLC<20> B_BLC_SEL B_BLT<23> B_BLT<22> B_BLT<21> B_BLT<20> B_BLT_SEL ++ B_PRE_N B_SEL_P<23> B_SEL_P<22> B_SEL_P<21> B_SEL_P<20> B_WR_ONE B_WR_ZERO ++ VDD VSS / RM_IHPSG13_512x8_c3_2P_BLDRV +XAB_BLMUX<4> A_BLC<19> A_BLC<18> A_BLC<17> A_BLC<16> A_BLC_SEL A_BLT<19> ++ A_BLT<18> A_BLT<17> A_BLT<16> A_BLT_SEL A_PRE_N A_SEL_P<19> A_SEL_P<18> ++ A_SEL_P<17> A_SEL_P<16> A_WR_ONE A_WR_ZERO B_BLC<19> B_BLC<18> B_BLC<17> ++ B_BLC<16> B_BLC_SEL B_BLT<19> B_BLT<18> B_BLT<17> B_BLT<16> B_BLT_SEL ++ B_PRE_N B_SEL_P<19> B_SEL_P<18> B_SEL_P<17> B_SEL_P<16> B_WR_ONE B_WR_ZERO ++ VDD VSS / RM_IHPSG13_512x8_c3_2P_BLDRV +XAB_BLMUX<3> A_BLC<15> A_BLC<14> A_BLC<13> A_BLC<12> A_BLC_SEL A_BLT<15> ++ A_BLT<14> A_BLT<13> A_BLT<12> A_BLT_SEL A_PRE_N A_SEL_P<15> A_SEL_P<14> ++ A_SEL_P<13> A_SEL_P<12> A_WR_ONE A_WR_ZERO B_BLC<15> B_BLC<14> B_BLC<13> ++ B_BLC<12> B_BLC_SEL B_BLT<15> B_BLT<14> B_BLT<13> B_BLT<12> B_BLT_SEL ++ B_PRE_N B_SEL_P<15> B_SEL_P<14> B_SEL_P<13> B_SEL_P<12> B_WR_ONE B_WR_ZERO ++ VDD VSS / RM_IHPSG13_512x8_c3_2P_BLDRV +XAB_BLMUX<2> A_BLC<11> A_BLC<10> A_BLC<9> A_BLC<8> A_BLC_SEL A_BLT<11> ++ A_BLT<10> A_BLT<9> A_BLT<8> A_BLT_SEL A_PRE_N A_SEL_P<11> A_SEL_P<10> ++ A_SEL_P<9> A_SEL_P<8> A_WR_ONE A_WR_ZERO B_BLC<11> B_BLC<10> B_BLC<9> ++ B_BLC<8> B_BLC_SEL B_BLT<11> B_BLT<10> B_BLT<9> B_BLT<8> B_BLT_SEL B_PRE_N ++ B_SEL_P<11> B_SEL_P<10> B_SEL_P<9> B_SEL_P<8> B_WR_ONE B_WR_ZERO VDD ++ VSS / RM_IHPSG13_512x8_c3_2P_BLDRV +XAB_BLMUX<1> A_BLC<7> A_BLC<6> A_BLC<5> A_BLC<4> A_BLC_SEL A_BLT<7> A_BLT<6> ++ A_BLT<5> A_BLT<4> A_BLT_SEL A_PRE_N A_SEL_P<7> A_SEL_P<6> A_SEL_P<5> ++ A_SEL_P<4> A_WR_ONE A_WR_ZERO B_BLC<7> B_BLC<6> B_BLC<5> B_BLC<4> B_BLC_SEL ++ B_BLT<7> B_BLT<6> B_BLT<5> B_BLT<4> B_BLT_SEL B_PRE_N B_SEL_P<7> B_SEL_P<6> ++ B_SEL_P<5> B_SEL_P<4> B_WR_ONE B_WR_ZERO VDD VSS / ++ RM_IHPSG13_512x8_c3_2P_BLDRV +XAB_BLMUX<0> A_BLC<3> A_BLC<2> A_BLC<1> A_BLC<0> A_BLC_SEL A_BLT<3> A_BLT<2> ++ A_BLT<1> A_BLT<0> A_BLT_SEL A_PRE_N A_SEL_P<3> A_SEL_P<2> A_SEL_P<1> ++ A_SEL_P<0> A_WR_ONE A_WR_ZERO B_BLC<3> B_BLC<2> B_BLC<1> B_BLC<0> B_BLC_SEL ++ B_BLT<3> B_BLT<2> B_BLT<1> B_BLT<0> B_BLT_SEL B_PRE_N B_SEL_P<3> B_SEL_P<2> ++ B_SEL_P<1> B_SEL_P<0> B_WR_ONE B_WR_ZERO VDD VSS / ++ RM_IHPSG13_512x8_c3_2P_BLDRV +XB_I51 net037 B_DR_O VDD VSS / RSC_IHPSG13_INVX4 +XA_I51 net19 A_DR_O VDD VSS / RSC_IHPSG13_INVX4 +XB_I78 B_RCLK_B_L B_SAE VDD VSS / RSC_IHPSG13_CBUFX2 +XA_I78 A_RCLK_B_L A_SAE VDD VSS / RSC_IHPSG13_CBUFX2 +XB_I69 B_DCLK_L B_DCLK_B_L VDD VSS / RSC_IHPSG13_CINVX8 +XB_I50 B_WCLK_L B_WCLK_B_L VDD VSS / RSC_IHPSG13_CINVX8 +XB_EBUF B_RCLK_L B_RCLK_B_L VDD VSS / RSC_IHPSG13_CINVX8 +XA_I69 A_DCLK_L A_DCLK_B_L VDD VSS / RSC_IHPSG13_CINVX8 +XA_I50 A_WCLK_L A_WCLK_B_L VDD VSS / RSC_IHPSG13_CINVX8 +XA_EBUF A_RCLK_L A_RCLK_B_L VDD VSS / RSC_IHPSG13_CINVX8 +XB_I76 B_DI_N B_DO_WRITE_P B_WR_ZERO VDD VSS / RSC_IHPSG13_AND2X6 +XB_I75 B_DI_R B_DO_WRITE_P B_WR_ONE VDD VSS / RSC_IHPSG13_AND2X6 +XA_I76 A_DI_N A_DO_WRITE_P A_WR_ZERO VDD VSS / RSC_IHPSG13_AND2X6 +XA_I75 A_DI_R A_DO_WRITE_P A_WR_ONE VDD VSS / RSC_IHPSG13_AND2X6 +XB_I83 B_BM_R B_BM_N VDD VSS / RSC_IHPSG13_INVX2 +XB_DEC3INV<31> net041<0> B_SEL_P<31> VDD VSS / RSC_IHPSG13_INVX2 +XB_DEC3INV<30> net041<1> B_SEL_P<30> VDD VSS / RSC_IHPSG13_INVX2 +XB_DEC3INV<29> net041<2> B_SEL_P<29> VDD VSS / RSC_IHPSG13_INVX2 +XB_DEC3INV<28> net041<3> B_SEL_P<28> VDD VSS / RSC_IHPSG13_INVX2 +XB_DEC3INV<27> net041<4> B_SEL_P<27> VDD VSS / RSC_IHPSG13_INVX2 +XB_DEC3INV<26> net041<5> B_SEL_P<26> VDD VSS / RSC_IHPSG13_INVX2 +XB_DEC3INV<25> net041<6> B_SEL_P<25> VDD VSS / RSC_IHPSG13_INVX2 +XB_DEC3INV<24> net041<7> B_SEL_P<24> VDD VSS / RSC_IHPSG13_INVX2 +XB_DEC3INV<23> net041<8> B_SEL_P<23> VDD VSS / RSC_IHPSG13_INVX2 +XB_DEC3INV<22> net041<9> B_SEL_P<22> VDD VSS / RSC_IHPSG13_INVX2 +XB_DEC3INV<21> net041<10> B_SEL_P<21> VDD VSS / RSC_IHPSG13_INVX2 +XB_DEC3INV<20> net041<11> B_SEL_P<20> VDD VSS / RSC_IHPSG13_INVX2 +XB_DEC3INV<19> net041<12> B_SEL_P<19> VDD VSS / RSC_IHPSG13_INVX2 +XB_DEC3INV<18> net041<13> B_SEL_P<18> VDD VSS / RSC_IHPSG13_INVX2 +XB_DEC3INV<17> net041<14> B_SEL_P<17> VDD VSS / RSC_IHPSG13_INVX2 +XB_DEC3INV<16> net041<15> B_SEL_P<16> VDD VSS / RSC_IHPSG13_INVX2 +XB_DEC3INV<15> net041<16> B_SEL_P<15> VDD VSS / RSC_IHPSG13_INVX2 +XB_DEC3INV<14> net041<17> B_SEL_P<14> VDD VSS / RSC_IHPSG13_INVX2 +XB_DEC3INV<13> net041<18> B_SEL_P<13> VDD VSS / RSC_IHPSG13_INVX2 +XB_DEC3INV<12> net041<19> B_SEL_P<12> VDD VSS / RSC_IHPSG13_INVX2 +XB_DEC3INV<11> net041<20> B_SEL_P<11> VDD VSS / RSC_IHPSG13_INVX2 +XB_DEC3INV<10> net041<21> B_SEL_P<10> VDD VSS / RSC_IHPSG13_INVX2 +XB_DEC3INV<9> net041<22> B_SEL_P<9> VDD VSS / RSC_IHPSG13_INVX2 +XB_DEC3INV<8> net041<23> B_SEL_P<8> VDD VSS / RSC_IHPSG13_INVX2 +XB_DEC3INV<7> net041<24> B_SEL_P<7> VDD VSS / RSC_IHPSG13_INVX2 +XB_DEC3INV<6> net041<25> B_SEL_P<6> VDD VSS / RSC_IHPSG13_INVX2 +XB_DEC3INV<5> net041<26> B_SEL_P<5> VDD VSS / RSC_IHPSG13_INVX2 +XB_DEC3INV<4> net041<27> B_SEL_P<4> VDD VSS / RSC_IHPSG13_INVX2 +XB_DEC3INV<3> net041<28> B_SEL_P<3> VDD VSS / RSC_IHPSG13_INVX2 +XB_DEC3INV<2> net041<29> B_SEL_P<2> VDD VSS / RSC_IHPSG13_INVX2 +XB_DEC3INV<1> net041<30> B_SEL_P<1> VDD VSS / RSC_IHPSG13_INVX2 +XB_DEC3INV<0> net041<31> B_SEL_P<0> VDD VSS / RSC_IHPSG13_INVX2 +XB_I49 B_DI_R B_DI_N VDD VSS / RSC_IHPSG13_INVX2 +XA_I83 A_BM_R A_BM_N VDD VSS / RSC_IHPSG13_INVX2 +XA_DEC3INV<31> net23<0> A_SEL_P<31> VDD VSS / RSC_IHPSG13_INVX2 +XA_DEC3INV<30> net23<1> A_SEL_P<30> VDD VSS / RSC_IHPSG13_INVX2 +XA_DEC3INV<29> net23<2> A_SEL_P<29> VDD VSS / RSC_IHPSG13_INVX2 +XA_DEC3INV<28> net23<3> A_SEL_P<28> VDD VSS / RSC_IHPSG13_INVX2 +XA_DEC3INV<27> net23<4> A_SEL_P<27> VDD VSS / RSC_IHPSG13_INVX2 +XA_DEC3INV<26> net23<5> A_SEL_P<26> VDD VSS / RSC_IHPSG13_INVX2 +XA_DEC3INV<25> net23<6> A_SEL_P<25> VDD VSS / RSC_IHPSG13_INVX2 +XA_DEC3INV<24> net23<7> A_SEL_P<24> VDD VSS / RSC_IHPSG13_INVX2 +XA_DEC3INV<23> net23<8> A_SEL_P<23> VDD VSS / RSC_IHPSG13_INVX2 +XA_DEC3INV<22> net23<9> A_SEL_P<22> VDD VSS / RSC_IHPSG13_INVX2 +XA_DEC3INV<21> net23<10> A_SEL_P<21> VDD VSS / RSC_IHPSG13_INVX2 +XA_DEC3INV<20> net23<11> A_SEL_P<20> VDD VSS / RSC_IHPSG13_INVX2 +XA_DEC3INV<19> net23<12> A_SEL_P<19> VDD VSS / RSC_IHPSG13_INVX2 +XA_DEC3INV<18> net23<13> A_SEL_P<18> VDD VSS / RSC_IHPSG13_INVX2 +XA_DEC3INV<17> net23<14> A_SEL_P<17> VDD VSS / RSC_IHPSG13_INVX2 +XA_DEC3INV<16> net23<15> A_SEL_P<16> VDD VSS / RSC_IHPSG13_INVX2 +XA_DEC3INV<15> net23<16> A_SEL_P<15> VDD VSS / RSC_IHPSG13_INVX2 +XA_DEC3INV<14> net23<17> A_SEL_P<14> VDD VSS / RSC_IHPSG13_INVX2 +XA_DEC3INV<13> net23<18> A_SEL_P<13> VDD VSS / RSC_IHPSG13_INVX2 +XA_DEC3INV<12> net23<19> A_SEL_P<12> VDD VSS / RSC_IHPSG13_INVX2 +XA_DEC3INV<11> net23<20> A_SEL_P<11> VDD VSS / RSC_IHPSG13_INVX2 +XA_DEC3INV<10> net23<21> A_SEL_P<10> VDD VSS / RSC_IHPSG13_INVX2 +XA_DEC3INV<9> net23<22> A_SEL_P<9> VDD VSS / RSC_IHPSG13_INVX2 +XA_DEC3INV<8> net23<23> A_SEL_P<8> VDD VSS / RSC_IHPSG13_INVX2 +XA_DEC3INV<7> net23<24> A_SEL_P<7> VDD VSS / RSC_IHPSG13_INVX2 +XA_DEC3INV<6> net23<25> A_SEL_P<6> VDD VSS / RSC_IHPSG13_INVX2 +XA_DEC3INV<5> net23<26> A_SEL_P<5> VDD VSS / RSC_IHPSG13_INVX2 +XA_DEC3INV<4> net23<27> A_SEL_P<4> VDD VSS / RSC_IHPSG13_INVX2 +XA_DEC3INV<3> net23<28> A_SEL_P<3> VDD VSS / RSC_IHPSG13_INVX2 +XA_DEC3INV<2> net23<29> A_SEL_P<2> VDD VSS / RSC_IHPSG13_INVX2 +XA_DEC3INV<1> net23<30> A_SEL_P<1> VDD VSS / RSC_IHPSG13_INVX2 +XA_DEC3INV<0> net23<31> A_SEL_P<0> VDD VSS / RSC_IHPSG13_INVX2 +XA_I49 A_DI_R A_DI_N VDD VSS / RSC_IHPSG13_INVX2 +XB_ISENSE B_SAE B_BLC_SEL B_BLT_SEL net037 net038 VDD VSS / ++ RSC_IHPSG13_DFPQD_MSAFFX2 +XA_ISENSE A_SAE A_BLC_SEL A_BLT_SEL net19 net20 VDD VSS / ++ RSC_IHPSG13_DFPQD_MSAFFX2 +XB_DREG B_BIST_EN_I B_BIST_DW_I B_DCLK_B_L B_DW_I B_DI_R net042 VDD ++ VSS / RSC_IHPSG13_DFNQMX2IX1 +XB_BREG B_BIST_EN_I B_BIST_BM_I B_DCLK_B_L B_BM_I B_BM_R net043 VDD ++ VSS / RSC_IHPSG13_DFNQMX2IX1 +XA_DREG A_BIST_EN_I A_BIST_DW_I A_DCLK_B_L A_DW_I A_DI_R net22 VDD VSS ++ / RSC_IHPSG13_DFNQMX2IX1 +XA_BREG A_BIST_EN_I A_BIST_BM_I A_DCLK_B_L A_BM_I A_BM_R net21 VDD VSS ++ / RSC_IHPSG13_DFNQMX2IX1 +XB_DEC3<31> B_P1<1> B_P0<1> B_ADDR_DEC<7> net041<0> VDD VSS / ++ RSC_IHPSG13_NAND3X2 +XB_DEC3<30> B_P1<1> B_P0<1> B_ADDR_DEC<6> net041<1> VDD VSS / ++ RSC_IHPSG13_NAND3X2 +XB_DEC3<29> B_P1<1> B_P0<1> B_ADDR_DEC<5> net041<2> VDD VSS / ++ RSC_IHPSG13_NAND3X2 +XB_DEC3<28> B_P1<1> B_P0<1> B_ADDR_DEC<4> net041<3> VDD VSS / ++ RSC_IHPSG13_NAND3X2 +XB_DEC3<27> B_P1<1> B_P0<1> B_ADDR_DEC<3> net041<4> VDD VSS / ++ RSC_IHPSG13_NAND3X2 +XB_DEC3<26> B_P1<1> B_P0<1> B_ADDR_DEC<2> net041<5> VDD VSS / ++ RSC_IHPSG13_NAND3X2 +XB_DEC3<25> B_P1<1> B_P0<1> B_ADDR_DEC<1> net041<6> VDD VSS / ++ RSC_IHPSG13_NAND3X2 +XB_DEC3<24> B_P1<1> B_P0<1> B_ADDR_DEC<0> net041<7> VDD VSS / ++ RSC_IHPSG13_NAND3X2 +XB_DEC3<23> B_P1<1> B_N0<1> B_ADDR_DEC<7> net041<8> VDD VSS / ++ RSC_IHPSG13_NAND3X2 +XB_DEC3<22> B_P1<1> B_N0<1> B_ADDR_DEC<6> net041<9> VDD VSS / ++ RSC_IHPSG13_NAND3X2 +XB_DEC3<21> B_P1<1> B_N0<1> B_ADDR_DEC<5> net041<10> VDD VSS / ++ RSC_IHPSG13_NAND3X2 +XB_DEC3<20> B_P1<1> B_N0<1> B_ADDR_DEC<4> net041<11> VDD VSS / ++ RSC_IHPSG13_NAND3X2 +XB_DEC3<19> B_P1<1> B_N0<1> B_ADDR_DEC<3> net041<12> VDD VSS / ++ RSC_IHPSG13_NAND3X2 +XB_DEC3<18> B_P1<1> B_N0<1> B_ADDR_DEC<2> net041<13> VDD VSS / ++ RSC_IHPSG13_NAND3X2 +XB_DEC3<17> B_P1<1> B_N0<1> B_ADDR_DEC<1> net041<14> VDD VSS / ++ RSC_IHPSG13_NAND3X2 +XB_DEC3<16> B_P1<1> B_N0<1> B_ADDR_DEC<0> net041<15> VDD VSS / ++ RSC_IHPSG13_NAND3X2 +XB_DEC3<15> B_N1<0> B_P0<0> B_ADDR_DEC<7> net041<16> VDD VSS / ++ RSC_IHPSG13_NAND3X2 +XB_DEC3<14> B_N1<0> B_P0<0> B_ADDR_DEC<6> net041<17> VDD VSS / ++ RSC_IHPSG13_NAND3X2 +XB_DEC3<13> B_N1<0> B_P0<0> B_ADDR_DEC<5> net041<18> VDD VSS / ++ RSC_IHPSG13_NAND3X2 +XB_DEC3<12> B_N1<0> B_P0<0> B_ADDR_DEC<4> net041<19> VDD VSS / ++ RSC_IHPSG13_NAND3X2 +XB_DEC3<11> B_N1<0> B_P0<0> B_ADDR_DEC<3> net041<20> VDD VSS / ++ RSC_IHPSG13_NAND3X2 +XB_DEC3<10> B_N1<0> B_P0<0> B_ADDR_DEC<2> net041<21> VDD VSS / ++ RSC_IHPSG13_NAND3X2 +XB_DEC3<9> B_N1<0> B_P0<0> B_ADDR_DEC<1> net041<22> VDD VSS / ++ RSC_IHPSG13_NAND3X2 +XB_DEC3<8> B_N1<0> B_P0<0> B_ADDR_DEC<0> net041<23> VDD VSS / ++ RSC_IHPSG13_NAND3X2 +XB_DEC3<7> B_N1<0> B_N0<0> B_ADDR_DEC<7> net041<24> VDD VSS / ++ RSC_IHPSG13_NAND3X2 +XB_DEC3<6> B_N1<0> B_N0<0> B_ADDR_DEC<6> net041<25> VDD VSS / ++ RSC_IHPSG13_NAND3X2 +XB_DEC3<5> B_N1<0> B_N0<0> B_ADDR_DEC<5> net041<26> VDD VSS / ++ RSC_IHPSG13_NAND3X2 +XB_DEC3<4> B_N1<0> B_N0<0> B_ADDR_DEC<4> net041<27> VDD VSS / ++ RSC_IHPSG13_NAND3X2 +XB_DEC3<3> B_N1<0> B_N0<0> B_ADDR_DEC<3> net041<28> VDD VSS / ++ RSC_IHPSG13_NAND3X2 +XB_DEC3<2> B_N1<0> B_N0<0> B_ADDR_DEC<2> net041<29> VDD VSS / ++ RSC_IHPSG13_NAND3X2 +XB_DEC3<1> B_N1<0> B_N0<0> B_ADDR_DEC<1> net041<30> VDD VSS / ++ RSC_IHPSG13_NAND3X2 +XB_DEC3<0> B_N1<0> B_N0<0> B_ADDR_DEC<0> net041<31> VDD VSS / ++ RSC_IHPSG13_NAND3X2 +XA_DEC3<31> A_P1<1> A_P0<1> A_ADDR_DEC<7> net23<0> VDD VSS / ++ RSC_IHPSG13_NAND3X2 +XA_DEC3<30> A_P1<1> A_P0<1> A_ADDR_DEC<6> net23<1> VDD VSS / ++ RSC_IHPSG13_NAND3X2 +XA_DEC3<29> A_P1<1> A_P0<1> A_ADDR_DEC<5> net23<2> VDD VSS / ++ RSC_IHPSG13_NAND3X2 +XA_DEC3<28> A_P1<1> A_P0<1> A_ADDR_DEC<4> net23<3> VDD VSS / ++ RSC_IHPSG13_NAND3X2 +XA_DEC3<27> A_P1<1> A_P0<1> A_ADDR_DEC<3> net23<4> VDD VSS / ++ RSC_IHPSG13_NAND3X2 +XA_DEC3<26> A_P1<1> A_P0<1> A_ADDR_DEC<2> net23<5> VDD VSS / ++ RSC_IHPSG13_NAND3X2 +XA_DEC3<25> A_P1<1> A_P0<1> A_ADDR_DEC<1> net23<6> VDD VSS / ++ RSC_IHPSG13_NAND3X2 +XA_DEC3<24> A_P1<1> A_P0<1> A_ADDR_DEC<0> net23<7> VDD VSS / ++ RSC_IHPSG13_NAND3X2 +XA_DEC3<23> A_P1<1> A_N0<1> A_ADDR_DEC<7> net23<8> VDD VSS / ++ RSC_IHPSG13_NAND3X2 +XA_DEC3<22> A_P1<1> A_N0<1> A_ADDR_DEC<6> net23<9> VDD VSS / ++ RSC_IHPSG13_NAND3X2 +XA_DEC3<21> A_P1<1> A_N0<1> A_ADDR_DEC<5> net23<10> VDD VSS / ++ RSC_IHPSG13_NAND3X2 +XA_DEC3<20> A_P1<1> A_N0<1> A_ADDR_DEC<4> net23<11> VDD VSS / ++ RSC_IHPSG13_NAND3X2 +XA_DEC3<19> A_P1<1> A_N0<1> A_ADDR_DEC<3> net23<12> VDD VSS / ++ RSC_IHPSG13_NAND3X2 +XA_DEC3<18> A_P1<1> A_N0<1> A_ADDR_DEC<2> net23<13> VDD VSS / ++ RSC_IHPSG13_NAND3X2 +XA_DEC3<17> A_P1<1> A_N0<1> A_ADDR_DEC<1> net23<14> VDD VSS / ++ RSC_IHPSG13_NAND3X2 +XA_DEC3<16> A_P1<1> A_N0<1> A_ADDR_DEC<0> net23<15> VDD VSS / ++ RSC_IHPSG13_NAND3X2 +XA_DEC3<15> A_N1<0> A_P0<0> A_ADDR_DEC<7> net23<16> VDD VSS / ++ RSC_IHPSG13_NAND3X2 +XA_DEC3<14> A_N1<0> A_P0<0> A_ADDR_DEC<6> net23<17> VDD VSS / ++ RSC_IHPSG13_NAND3X2 +XA_DEC3<13> A_N1<0> A_P0<0> A_ADDR_DEC<5> net23<18> VDD VSS / ++ RSC_IHPSG13_NAND3X2 +XA_DEC3<12> A_N1<0> A_P0<0> A_ADDR_DEC<4> net23<19> VDD VSS / ++ RSC_IHPSG13_NAND3X2 +XA_DEC3<11> A_N1<0> A_P0<0> A_ADDR_DEC<3> net23<20> VDD VSS / ++ RSC_IHPSG13_NAND3X2 +XA_DEC3<10> A_N1<0> A_P0<0> A_ADDR_DEC<2> net23<21> VDD VSS / ++ RSC_IHPSG13_NAND3X2 +XA_DEC3<9> A_N1<0> A_P0<0> A_ADDR_DEC<1> net23<22> VDD VSS / ++ RSC_IHPSG13_NAND3X2 +XA_DEC3<8> A_N1<0> A_P0<0> A_ADDR_DEC<0> net23<23> VDD VSS / ++ RSC_IHPSG13_NAND3X2 +XA_DEC3<7> A_N1<0> A_N0<0> A_ADDR_DEC<7> net23<24> VDD VSS / ++ RSC_IHPSG13_NAND3X2 +XA_DEC3<6> A_N1<0> A_N0<0> A_ADDR_DEC<6> net23<25> VDD VSS / ++ RSC_IHPSG13_NAND3X2 +XA_DEC3<5> A_N1<0> A_N0<0> A_ADDR_DEC<5> net23<26> VDD VSS / ++ RSC_IHPSG13_NAND3X2 +XA_DEC3<4> A_N1<0> A_N0<0> A_ADDR_DEC<4> net23<27> VDD VSS / ++ RSC_IHPSG13_NAND3X2 +XA_DEC3<3> A_N1<0> A_N0<0> A_ADDR_DEC<3> net23<28> VDD VSS / ++ RSC_IHPSG13_NAND3X2 +XA_DEC3<2> A_N1<0> A_N0<0> A_ADDR_DEC<2> net23<29> VDD VSS / ++ RSC_IHPSG13_NAND3X2 +XA_DEC3<1> A_N1<0> A_N0<0> A_ADDR_DEC<1> net23<30> VDD VSS / ++ RSC_IHPSG13_NAND3X2 +XA_DEC3<0> A_N1<0> A_N0<0> A_ADDR_DEC<0> net23<31> VDD VSS / ++ RSC_IHPSG13_NAND3X2 +XB_I89 B_DCLK_B_L B_DCLK_B_R / RSC_IHPSG13_MET3RES +XB_I91 B_RCLK_B_L B_RCLK_B_R / RSC_IHPSG13_MET3RES +XB_I90 B_WCLK_B_L B_WCLK_B_R / RSC_IHPSG13_MET3RES +XB_I88 B_DCLK_L B_DCLK_R / RSC_IHPSG13_MET3RES +XB_I87 B_WCLK_L B_WCLK_R / RSC_IHPSG13_MET3RES +XB_R2 B_RCLK_L B_RCLK_R / RSC_IHPSG13_MET3RES +XA_I89 A_DCLK_B_L A_DCLK_B_R / RSC_IHPSG13_MET3RES +XA_I91 A_RCLK_B_L A_RCLK_B_R / RSC_IHPSG13_MET3RES +XA_I90 A_WCLK_B_L A_WCLK_B_R / RSC_IHPSG13_MET3RES +XA_I88 A_DCLK_L A_DCLK_R / RSC_IHPSG13_MET3RES +XA_I87 A_WCLK_L A_WCLK_R / RSC_IHPSG13_MET3RES +XA_R2 A_RCLK_L A_RCLK_R / RSC_IHPSG13_MET3RES +XB_BM_TIEH B_TIEH_O VDD VSS / RSC_IHPSG13_TIEH +XA_BM_TIEH A_TIEH_O VDD VSS / RSC_IHPSG13_TIEH +.ENDS +.SUBCKT RM_IHPSG13_512x8_c3_2P_COLDRV13_FILL4 VDD VSS +XI0<11> VDD VSS / RSC_IHPSG13_FILLCAP4 +XI0<10> VDD VSS / RSC_IHPSG13_FILLCAP4 +XI0<9> VDD VSS / RSC_IHPSG13_FILLCAP4 +XI0<8> VDD VSS / RSC_IHPSG13_FILLCAP4 +XI0<7> VDD VSS / RSC_IHPSG13_FILLCAP4 +XI0<6> VDD VSS / RSC_IHPSG13_FILLCAP4 +XI0<5> VDD VSS / RSC_IHPSG13_FILLCAP4 +XI0<4> VDD VSS / RSC_IHPSG13_FILLCAP4 +XI0<3> VDD VSS / RSC_IHPSG13_FILLCAP4 +XI0<2> VDD VSS / RSC_IHPSG13_FILLCAP4 +XI0<1> VDD VSS / RSC_IHPSG13_FILLCAP4 +.ENDS + + +.SUBCKT RSC_IHPSG13_CBUFX16 A Z VDD VSS +MN0 net4 A VSS VSS sg13_lv_nmos m=1 w=2.115u l=130.00n ng=3 nrd=0 nrs=0 +MN1 Z net4 VSS VSS sg13_lv_nmos m=1 w=5.64u l=130.00n ng=8 nrd=0 nrs=0 +MP1 Z net4 VDD VDD sg13_lv_pmos m=1 w=13.000u l=130.00n ng=8 nrd=0 ++ nrs=0 +MP0 net4 A VDD VDD sg13_lv_pmos m=1 w=4.89u l=130.00n ng=3 nrd=0 nrs=0 +.ENDS +.SUBCKT RM_IHPSG13_512x8_c3_1P_COLDRV13X16 ADDR_COL_I<1> ADDR_COL_I<0> ADDR_COL_O<1> ++ ADDR_COL_O<0> ADDR_DEC_I<7> ADDR_DEC_I<6> ADDR_DEC_I<5> ADDR_DEC_I<4> ++ ADDR_DEC_I<3> ADDR_DEC_I<2> ADDR_DEC_I<1> ADDR_DEC_I<0> ADDR_DEC_O<7> ++ ADDR_DEC_O<6> ADDR_DEC_O<5> ADDR_DEC_O<4> ADDR_DEC_O<3> ADDR_DEC_O<2> ++ ADDR_DEC_O<1> ADDR_DEC_O<0> DCLK_I DCLK_O RCLK_I RCLK_O WCLK_I WCLK_O ++ VDD VSS +XI1<1> VDD VSS / RSC_IHPSG13_FILLCAP4 +XI1<0> VDD VSS / RSC_IHPSG13_FILLCAP4 +XI0<3> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI0<2> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI0<1> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI0<0> VDD VSS / RSC_IHPSG13_FILLCAP8 +XADDR_COL_DRV<1> ADDR_COL_I<1> ADDR_COL_O<1> VDD VSS / ++ RSC_IHPSG13_CBUFX16 +XADDR_COL_DRV<0> ADDR_COL_I<0> ADDR_COL_O<0> VDD VSS / ++ RSC_IHPSG13_CBUFX16 +XADDR_DEC_DRV<7> ADDR_DEC_I<7> ADDR_DEC_O<7> VDD VSS / ++ RSC_IHPSG13_CBUFX16 +XADDR_DEC_DRV<6> ADDR_DEC_I<6> ADDR_DEC_O<6> VDD VSS / ++ RSC_IHPSG13_CBUFX16 +XADDR_DEC_DRV<5> ADDR_DEC_I<5> ADDR_DEC_O<5> VDD VSS / ++ RSC_IHPSG13_CBUFX16 +XADDR_DEC_DRV<4> ADDR_DEC_I<4> ADDR_DEC_O<4> VDD VSS / ++ RSC_IHPSG13_CBUFX16 +XADDR_DEC_DRV<3> ADDR_DEC_I<3> ADDR_DEC_O<3> VDD VSS / ++ RSC_IHPSG13_CBUFX16 +XADDR_DEC_DRV<2> ADDR_DEC_I<2> ADDR_DEC_O<2> VDD VSS / ++ RSC_IHPSG13_CBUFX16 +XADDR_DEC_DRV<1> ADDR_DEC_I<1> ADDR_DEC_O<1> VDD VSS / ++ RSC_IHPSG13_CBUFX16 +XADDR_DEC_DRV<0> ADDR_DEC_I<0> ADDR_DEC_O<0> VDD VSS / ++ RSC_IHPSG13_CBUFX16 +XDCLK_DRV DCLK_I DCLK_O VDD VSS / RSC_IHPSG13_CBUFX16 +XRCLK_DRV RCLK_I RCLK_O VDD VSS / RSC_IHPSG13_CBUFX16 +XWCLK_DRV WCLK_I WCLK_O VDD VSS / RSC_IHPSG13_CBUFX16 +.ENDS +.SUBCKT RSC_IHPSG13_WLDRVX16 A Z VDD VSS +MN1 Z net6 VSS VSS sg13_lv_nmos m=1 w=1.41u l=130.00n ng=2 nrd=0 nrs=0 +MN0 net6 A VSS VSS sg13_lv_nmos m=1 w=1.8u l=130.00n ng=2 nrd=0 nrs=0 +MP1 Z net6 VDD VDD sg13_lv_pmos m=1 w=12.96u l=130.00n ng=8 nrd=0 nrs=0 +MP0 net6 A VDD VDD sg13_lv_pmos m=1 w=900.0n l=130.00n ng=1 nrd=0 nrs=0 +.ENDS +.SUBCKT RM_IHPSG13_512x8_c3_1P_WLDRV16X16 A<15> A<14> A<13> A<12> A<11> A<10> A<9> A<8> ++ A<7> A<6> A<5> A<4> A<3> A<2> A<1> A<0> Z<15> Z<14> Z<13> Z<12> Z<11> Z<10> ++ Z<9> Z<8> Z<7> Z<6> Z<5> Z<4> Z<3> Z<2> Z<1> Z<0> VDD VSS +XBUF<15> A<15> Z<15> VDD VSS / RSC_IHPSG13_WLDRVX16 +XBUF<14> A<14> Z<14> VDD VSS / RSC_IHPSG13_WLDRVX16 +XBUF<13> A<13> Z<13> VDD VSS / RSC_IHPSG13_WLDRVX16 +XBUF<12> A<12> Z<12> VDD VSS / RSC_IHPSG13_WLDRVX16 +XBUF<11> A<11> Z<11> VDD VSS / RSC_IHPSG13_WLDRVX16 +XBUF<10> A<10> Z<10> VDD VSS / RSC_IHPSG13_WLDRVX16 +XBUF<9> A<9> Z<9> VDD VSS / RSC_IHPSG13_WLDRVX16 +XBUF<8> A<8> Z<8> VDD VSS / RSC_IHPSG13_WLDRVX16 +XBUF<7> A<7> Z<7> VDD VSS / RSC_IHPSG13_WLDRVX16 +XBUF<6> A<6> Z<6> VDD VSS / RSC_IHPSG13_WLDRVX16 +XBUF<5> A<5> Z<5> VDD VSS / RSC_IHPSG13_WLDRVX16 +XBUF<4> A<4> Z<4> VDD VSS / RSC_IHPSG13_WLDRVX16 +XBUF<3> A<3> Z<3> VDD VSS / RSC_IHPSG13_WLDRVX16 +XBUF<2> A<2> Z<2> VDD VSS / RSC_IHPSG13_WLDRVX16 +XBUF<1> A<1> Z<1> VDD VSS / RSC_IHPSG13_WLDRVX16 +XBUF<0> A<0> Z<0> VDD VSS / RSC_IHPSG13_WLDRVX16 +.ENDS + + +.SUBCKT RM_IHPSG13_512x8_c3_2P_COLDRV13X4 ADDR_COL_I<1> ADDR_COL_I<0> ADDR_COL_O<1> ++ ADDR_COL_O<0> ADDR_DEC_I<7> ADDR_DEC_I<6> ADDR_DEC_I<5> ADDR_DEC_I<4> ++ ADDR_DEC_I<3> ADDR_DEC_I<2> ADDR_DEC_I<1> ADDR_DEC_I<0> ADDR_DEC_O<7> ++ ADDR_DEC_O<6> ADDR_DEC_O<5> ADDR_DEC_O<4> ADDR_DEC_O<3> ADDR_DEC_O<2> ++ ADDR_DEC_O<1> ADDR_DEC_O<0> DCLK_I DCLK_O RCLK_I RCLK_O WCLK_I WCLK_O ++ VDD VSS +XWCLK_DRV WCLK_I WCLK_O VDD VSS / RSC_IHPSG13_CBUFX4 +XRCLK_DRV RCLK_I RCLK_O VDD VSS / RSC_IHPSG13_CBUFX4 +XDCLK_DRV DCLK_I DCLK_O VDD VSS / RSC_IHPSG13_CBUFX4 +XADDR_COL_DRV<1> ADDR_COL_I<1> ADDR_COL_O<1> VDD VSS / ++ RSC_IHPSG13_CBUFX4 +XADDR_COL_DRV<0> ADDR_COL_I<0> ADDR_COL_O<0> VDD VSS / ++ RSC_IHPSG13_CBUFX4 +XADDR_DEC_DRV<7> ADDR_DEC_I<7> ADDR_DEC_O<7> VDD VSS / ++ RSC_IHPSG13_CBUFX4 +XADDR_DEC_DRV<6> ADDR_DEC_I<6> ADDR_DEC_O<6> VDD VSS / ++ RSC_IHPSG13_CBUFX4 +XADDR_DEC_DRV<5> ADDR_DEC_I<5> ADDR_DEC_O<5> VDD VSS / ++ RSC_IHPSG13_CBUFX4 +XADDR_DEC_DRV<4> ADDR_DEC_I<4> ADDR_DEC_O<4> VDD VSS / ++ RSC_IHPSG13_CBUFX4 +XADDR_DEC_DRV<3> ADDR_DEC_I<3> ADDR_DEC_O<3> VDD VSS / ++ RSC_IHPSG13_CBUFX4 +XADDR_DEC_DRV<2> ADDR_DEC_I<2> ADDR_DEC_O<2> VDD VSS / ++ RSC_IHPSG13_CBUFX4 +XADDR_DEC_DRV<1> ADDR_DEC_I<1> ADDR_DEC_O<1> VDD VSS / ++ RSC_IHPSG13_CBUFX4 +XADDR_DEC_DRV<0> ADDR_DEC_I<0> ADDR_DEC_O<0> VDD VSS / ++ RSC_IHPSG13_CBUFX4 +XI0<6> VDD VSS / RSC_IHPSG13_FILLCAP4 +XI0<5> VDD VSS / RSC_IHPSG13_FILLCAP4 +XI0<4> VDD VSS / RSC_IHPSG13_FILLCAP4 +XI0<3> VDD VSS / RSC_IHPSG13_FILLCAP4 +XI0<2> VDD VSS / RSC_IHPSG13_FILLCAP4 +XI0<1> VDD VSS / RSC_IHPSG13_FILLCAP4 +XI1 VDD VSS / RSC_IHPSG13_FILLCAP8 +.ENDS +.SUBCKT RM_IHPSG13_512x8_c3_2P_WLDRV16X4 A<15> A<14> A<13> A<12> A<11> A<10> A<9> A<8> ++ A<7> A<6> A<5> A<4> A<3> A<2> A<1> A<0> Z<15> Z<14> Z<13> Z<12> Z<11> Z<10> ++ Z<9> Z<8> Z<7> Z<6> Z<5> Z<4> Z<3> Z<2> Z<1> Z<0> VDD VSS +XBUF<15> A<15> Z<15> VDD VSS / RSC_IHPSG13_WLDRVX4 +XBUF<14> A<14> Z<14> VDD VSS / RSC_IHPSG13_WLDRVX4 +XBUF<13> A<13> Z<13> VDD VSS / RSC_IHPSG13_WLDRVX4 +XBUF<12> A<12> Z<12> VDD VSS / RSC_IHPSG13_WLDRVX4 +XBUF<11> A<11> Z<11> VDD VSS / RSC_IHPSG13_WLDRVX4 +XBUF<10> A<10> Z<10> VDD VSS / RSC_IHPSG13_WLDRVX4 +XBUF<9> A<9> Z<9> VDD VSS / RSC_IHPSG13_WLDRVX4 +XBUF<8> A<8> Z<8> VDD VSS / RSC_IHPSG13_WLDRVX4 +XBUF<7> A<7> Z<7> VDD VSS / RSC_IHPSG13_WLDRVX4 +XBUF<6> A<6> Z<6> VDD VSS / RSC_IHPSG13_WLDRVX4 +XBUF<5> A<5> Z<5> VDD VSS / RSC_IHPSG13_WLDRVX4 +XBUF<4> A<4> Z<4> VDD VSS / RSC_IHPSG13_WLDRVX4 +XBUF<3> A<3> Z<3> VDD VSS / RSC_IHPSG13_WLDRVX4 +XBUF<2> A<2> Z<2> VDD VSS / RSC_IHPSG13_WLDRVX4 +XBUF<1> A<1> Z<1> VDD VSS / RSC_IHPSG13_WLDRVX4 +XBUF<0> A<0> Z<0> VDD VSS / RSC_IHPSG13_WLDRVX4 +.ENDS +.SUBCKT RM_IHPSG13_512x8_c3_2P_ROWDEC8 ADDR_N_I<7> ADDR_N_I<6> ADDR_N_I<5> ADDR_N_I<4> ++ ADDR_N_I<3> ADDR_N_I<2> ADDR_N_I<1> ADDR_N_I<0> CS_I ECLK_I WL_O<255> ++ WL_O<254> WL_O<253> WL_O<252> WL_O<251> WL_O<250> WL_O<249> WL_O<248> ++ WL_O<247> WL_O<246> WL_O<245> WL_O<244> WL_O<243> WL_O<242> WL_O<241> ++ WL_O<240> WL_O<239> WL_O<238> WL_O<237> WL_O<236> WL_O<235> WL_O<234> ++ WL_O<233> WL_O<232> WL_O<231> WL_O<230> WL_O<229> WL_O<228> WL_O<227> ++ WL_O<226> WL_O<225> WL_O<224> WL_O<223> WL_O<222> WL_O<221> WL_O<220> ++ WL_O<219> WL_O<218> WL_O<217> WL_O<216> WL_O<215> WL_O<214> WL_O<213> ++ WL_O<212> WL_O<211> WL_O<210> WL_O<209> WL_O<208> WL_O<207> WL_O<206> ++ WL_O<205> WL_O<204> WL_O<203> WL_O<202> WL_O<201> WL_O<200> WL_O<199> ++ WL_O<198> WL_O<197> WL_O<196> WL_O<195> WL_O<194> WL_O<193> WL_O<192> ++ WL_O<191> WL_O<190> WL_O<189> WL_O<188> WL_O<187> WL_O<186> WL_O<185> ++ WL_O<184> WL_O<183> WL_O<182> WL_O<181> WL_O<180> WL_O<179> WL_O<178> ++ WL_O<177> WL_O<176> WL_O<175> WL_O<174> WL_O<173> WL_O<172> WL_O<171> ++ WL_O<170> WL_O<169> WL_O<168> WL_O<167> WL_O<166> WL_O<165> WL_O<164> ++ WL_O<163> WL_O<162> WL_O<161> WL_O<160> WL_O<159> WL_O<158> WL_O<157> ++ WL_O<156> WL_O<155> WL_O<154> WL_O<153> WL_O<152> WL_O<151> WL_O<150> ++ WL_O<149> WL_O<148> WL_O<147> WL_O<146> WL_O<145> WL_O<144> WL_O<143> ++ WL_O<142> WL_O<141> WL_O<140> WL_O<139> WL_O<138> WL_O<137> WL_O<136> ++ WL_O<135> WL_O<134> WL_O<133> WL_O<132> WL_O<131> WL_O<130> WL_O<129> ++ WL_O<128> WL_O<127> WL_O<126> WL_O<125> WL_O<124> WL_O<123> WL_O<122> ++ WL_O<121> WL_O<120> WL_O<119> WL_O<118> WL_O<117> WL_O<116> WL_O<115> ++ WL_O<114> WL_O<113> WL_O<112> WL_O<111> WL_O<110> WL_O<109> WL_O<108> ++ WL_O<107> WL_O<106> WL_O<105> WL_O<104> WL_O<103> WL_O<102> WL_O<101> ++ WL_O<100> WL_O<99> WL_O<98> WL_O<97> WL_O<96> WL_O<95> WL_O<94> WL_O<93> ++ WL_O<92> WL_O<91> WL_O<90> WL_O<89> WL_O<88> WL_O<87> WL_O<86> WL_O<85> ++ WL_O<84> WL_O<83> WL_O<82> WL_O<81> WL_O<80> WL_O<79> WL_O<78> WL_O<77> ++ WL_O<76> WL_O<75> WL_O<74> WL_O<73> WL_O<72> WL_O<71> WL_O<70> WL_O<69> ++ WL_O<68> WL_O<67> WL_O<66> WL_O<65> WL_O<64> WL_O<63> WL_O<62> WL_O<61> ++ WL_O<60> WL_O<59> WL_O<58> WL_O<57> WL_O<56> WL_O<55> WL_O<54> WL_O<53> ++ WL_O<52> WL_O<51> WL_O<50> WL_O<49> WL_O<48> WL_O<47> WL_O<46> WL_O<45> ++ WL_O<44> WL_O<43> WL_O<42> WL_O<41> WL_O<40> WL_O<39> WL_O<38> WL_O<37> ++ WL_O<36> WL_O<35> WL_O<34> WL_O<33> WL_O<32> WL_O<31> WL_O<30> WL_O<29> ++ WL_O<28> WL_O<27> WL_O<26> WL_O<25> WL_O<24> WL_O<23> WL_O<22> WL_O<21> ++ WL_O<20> WL_O<19> WL_O<18> WL_O<17> WL_O<16> WL_O<15> WL_O<14> WL_O<13> ++ WL_O<12> WL_O<11> WL_O<10> WL_O<9> WL_O<8> WL_O<7> WL_O<6> WL_O<5> WL_O<4> ++ WL_O<3> WL_O<2> WL_O<1> WL_O<0> VDD VSS +XDEC11<4> ADDR_N_I<7> ADDR_N_I<6> CS_I CS04<3> VDD VSS / ++ RM_IHPSG13_512x8_c3_2P_DEC03 +XDEC11<3> ADDR_N_I<5> ADDR_N_I<4> CS04<3> CS00<15> VDD VSS / ++ RM_IHPSG13_512x8_c3_2P_DEC03 +XDEC11<2> ADDR_N_I<5> ADDR_N_I<4> CS04<2> CS00<11> VDD VSS / ++ RM_IHPSG13_512x8_c3_2P_DEC03 +XDEC11<1> ADDR_N_I<5> ADDR_N_I<4> CS04<1> CS00<7> VDD VSS / ++ RM_IHPSG13_512x8_c3_2P_DEC03 +XDEC11<0> ADDR_N_I<5> ADDR_N_I<4> CS04<0> CS00<3> VDD VSS / ++ RM_IHPSG13_512x8_c3_2P_DEC03 +XSEL<15> ADDR_N_I<3> ADDR_N_I<2> ADDR_N_I<1> ADDR_N_I<0> CS00<15> ECLK_H<15> ++ ECLK_H<16> ECLK_B<15> ECLK_B<16> WL_O<255> WL_O<254> WL_O<253> WL_O<252> ++ WL_O<251> WL_O<250> WL_O<249> WL_O<248> WL_O<247> WL_O<246> WL_O<245> ++ WL_O<244> WL_O<243> WL_O<242> WL_O<241> WL_O<240> VDD VSS / ++ RM_IHPSG13_512x8_c3_2P_DEC04 +XSEL<14> ADDR_N_I<3> ADDR_N_I<2> ADDR_N_I<1> ADDR_N_I<0> CS00<14> ECLK_H<14> ++ ECLK_H<15> ECLK_B<14> ECLK_B<15> WL_O<239> WL_O<238> WL_O<237> WL_O<236> ++ WL_O<235> WL_O<234> WL_O<233> WL_O<232> WL_O<231> WL_O<230> WL_O<229> ++ WL_O<228> WL_O<227> WL_O<226> WL_O<225> WL_O<224> VDD VSS / ++ RM_IHPSG13_512x8_c3_2P_DEC04 +XSEL<13> ADDR_N_I<3> ADDR_N_I<2> ADDR_N_I<1> ADDR_N_I<0> CS00<13> ECLK_H<13> ++ ECLK_H<14> ECLK_B<13> ECLK_B<14> WL_O<223> WL_O<222> WL_O<221> WL_O<220> ++ WL_O<219> WL_O<218> WL_O<217> WL_O<216> WL_O<215> WL_O<214> WL_O<213> ++ WL_O<212> WL_O<211> WL_O<210> WL_O<209> WL_O<208> VDD VSS / ++ RM_IHPSG13_512x8_c3_2P_DEC04 +XSEL<12> ADDR_N_I<3> ADDR_N_I<2> ADDR_N_I<1> ADDR_N_I<0> CS00<12> ECLK_H<12> ++ ECLK_H<13> ECLK_B<12> ECLK_B<13> WL_O<207> WL_O<206> WL_O<205> WL_O<204> ++ WL_O<203> WL_O<202> WL_O<201> WL_O<200> WL_O<199> WL_O<198> WL_O<197> ++ WL_O<196> WL_O<195> WL_O<194> WL_O<193> WL_O<192> VDD VSS / ++ RM_IHPSG13_512x8_c3_2P_DEC04 +XSEL<11> ADDR_N_I<3> ADDR_N_I<2> ADDR_N_I<1> ADDR_N_I<0> CS00<11> ECLK_H<11> ++ ECLK_H<12> ECLK_B<11> ECLK_B<12> WL_O<191> WL_O<190> WL_O<189> WL_O<188> ++ WL_O<187> WL_O<186> WL_O<185> WL_O<184> WL_O<183> WL_O<182> WL_O<181> ++ WL_O<180> WL_O<179> WL_O<178> WL_O<177> WL_O<176> VDD VSS / ++ RM_IHPSG13_512x8_c3_2P_DEC04 +XSEL<10> ADDR_N_I<3> ADDR_N_I<2> ADDR_N_I<1> ADDR_N_I<0> CS00<10> ECLK_H<10> ++ ECLK_H<11> ECLK_B<10> ECLK_B<11> WL_O<175> WL_O<174> WL_O<173> WL_O<172> ++ WL_O<171> WL_O<170> WL_O<169> WL_O<168> WL_O<167> WL_O<166> WL_O<165> ++ WL_O<164> WL_O<163> WL_O<162> WL_O<161> WL_O<160> VDD VSS / ++ RM_IHPSG13_512x8_c3_2P_DEC04 +XSEL<9> ADDR_N_I<3> ADDR_N_I<2> ADDR_N_I<1> ADDR_N_I<0> CS00<9> ECLK_H<9> ++ ECLK_H<10> ECLK_B<9> ECLK_B<10> WL_O<159> WL_O<158> WL_O<157> WL_O<156> ++ WL_O<155> WL_O<154> WL_O<153> WL_O<152> WL_O<151> WL_O<150> WL_O<149> ++ WL_O<148> WL_O<147> WL_O<146> WL_O<145> WL_O<144> VDD VSS / ++ RM_IHPSG13_512x8_c3_2P_DEC04 +XSEL<8> ADDR_N_I<3> ADDR_N_I<2> ADDR_N_I<1> ADDR_N_I<0> CS00<8> ECLK_H<8> ++ ECLK_H<9> ECLK_B<8> ECLK_B<9> WL_O<143> WL_O<142> WL_O<141> WL_O<140> ++ WL_O<139> WL_O<138> WL_O<137> WL_O<136> WL_O<135> WL_O<134> WL_O<133> ++ WL_O<132> WL_O<131> WL_O<130> WL_O<129> WL_O<128> VDD VSS / ++ RM_IHPSG13_512x8_c3_2P_DEC04 +XSEL<7> ADDR_N_I<3> ADDR_N_I<2> ADDR_N_I<1> ADDR_N_I<0> CS00<7> ECLK_H<7> ++ ECLK_H<8> ECLK_B<7> ECLK_B<8> WL_O<127> WL_O<126> WL_O<125> WL_O<124> ++ WL_O<123> WL_O<122> WL_O<121> WL_O<120> WL_O<119> WL_O<118> WL_O<117> ++ WL_O<116> WL_O<115> WL_O<114> WL_O<113> WL_O<112> VDD VSS / ++ RM_IHPSG13_512x8_c3_2P_DEC04 +XSEL<6> ADDR_N_I<3> ADDR_N_I<2> ADDR_N_I<1> ADDR_N_I<0> CS00<6> ECLK_H<6> ++ ECLK_H<7> ECLK_B<6> ECLK_B<7> WL_O<111> WL_O<110> WL_O<109> WL_O<108> ++ WL_O<107> WL_O<106> WL_O<105> WL_O<104> WL_O<103> WL_O<102> WL_O<101> ++ WL_O<100> WL_O<99> WL_O<98> WL_O<97> WL_O<96> VDD VSS / ++ RM_IHPSG13_512x8_c3_2P_DEC04 +XSEL<5> ADDR_N_I<3> ADDR_N_I<2> ADDR_N_I<1> ADDR_N_I<0> CS00<5> ECLK_H<5> ++ ECLK_H<6> ECLK_B<5> ECLK_B<6> WL_O<95> WL_O<94> WL_O<93> WL_O<92> WL_O<91> ++ WL_O<90> WL_O<89> WL_O<88> WL_O<87> WL_O<86> WL_O<85> WL_O<84> WL_O<83> ++ WL_O<82> WL_O<81> WL_O<80> VDD VSS / RM_IHPSG13_512x8_c3_2P_DEC04 +XSEL<4> ADDR_N_I<3> ADDR_N_I<2> ADDR_N_I<1> ADDR_N_I<0> CS00<4> ECLK_H<4> ++ ECLK_H<5> ECLK_B<4> ECLK_B<5> WL_O<79> WL_O<78> WL_O<77> WL_O<76> WL_O<75> ++ WL_O<74> WL_O<73> WL_O<72> WL_O<71> WL_O<70> WL_O<69> WL_O<68> WL_O<67> ++ WL_O<66> WL_O<65> WL_O<64> VDD VSS / RM_IHPSG13_512x8_c3_2P_DEC04 +XSEL<3> ADDR_N_I<3> ADDR_N_I<2> ADDR_N_I<1> ADDR_N_I<0> CS00<3> ECLK_H<3> ++ ECLK_H<4> ECLK_B<3> ECLK_B<4> WL_O<63> WL_O<62> WL_O<61> WL_O<60> WL_O<59> ++ WL_O<58> WL_O<57> WL_O<56> WL_O<55> WL_O<54> WL_O<53> WL_O<52> WL_O<51> ++ WL_O<50> WL_O<49> WL_O<48> VDD VSS / RM_IHPSG13_512x8_c3_2P_DEC04 +XSEL<2> ADDR_N_I<3> ADDR_N_I<2> ADDR_N_I<1> ADDR_N_I<0> CS00<2> ECLK_H<2> ++ ECLK_H<3> ECLK_B<2> ECLK_B<3> WL_O<47> WL_O<46> WL_O<45> WL_O<44> WL_O<43> ++ WL_O<42> WL_O<41> WL_O<40> WL_O<39> WL_O<38> WL_O<37> WL_O<36> WL_O<35> ++ WL_O<34> WL_O<33> WL_O<32> VDD VSS / RM_IHPSG13_512x8_c3_2P_DEC04 +XSEL<1> ADDR_N_I<3> ADDR_N_I<2> ADDR_N_I<1> ADDR_N_I<0> CS00<1> ECLK_H<1> ++ ECLK_H<2> ECLK_B<1> ECLK_B<2> WL_O<31> WL_O<30> WL_O<29> WL_O<28> WL_O<27> ++ WL_O<26> WL_O<25> WL_O<24> WL_O<23> WL_O<22> WL_O<21> WL_O<20> WL_O<19> ++ WL_O<18> WL_O<17> WL_O<16> VDD VSS / RM_IHPSG13_512x8_c3_2P_DEC04 +XSEL<0> ADDR_N_I<3> ADDR_N_I<2> ADDR_N_I<1> ADDR_N_I<0> CS00<0> ECLK_I ++ ECLK_H<1> ECLK_B<0> ECLK_B<1> WL_O<15> WL_O<14> WL_O<13> WL_O<12> WL_O<11> ++ WL_O<10> WL_O<9> WL_O<8> WL_O<7> WL_O<6> WL_O<5> WL_O<4> WL_O<3> WL_O<2> ++ WL_O<1> WL_O<0> VDD VSS / RM_IHPSG13_512x8_c3_2P_DEC04 +XDEC10<4> ADDR_N_I<7> ADDR_N_I<6> CS_I CS04<2> VDD VSS / ++ RM_IHPSG13_512x8_c3_2P_DEC02 +XDEC10<3> ADDR_N_I<5> ADDR_N_I<4> CS04<3> CS00<14> VDD VSS / ++ RM_IHPSG13_512x8_c3_2P_DEC02 +XDEC10<2> ADDR_N_I<5> ADDR_N_I<4> CS04<2> CS00<10> VDD VSS / ++ RM_IHPSG13_512x8_c3_2P_DEC02 +XDEC10<1> ADDR_N_I<5> ADDR_N_I<4> CS04<1> CS00<6> VDD VSS / ++ RM_IHPSG13_512x8_c3_2P_DEC02 +XDEC10<0> ADDR_N_I<5> ADDR_N_I<4> CS04<0> CS00<2> VDD VSS / ++ RM_IHPSG13_512x8_c3_2P_DEC02 +XL2<132> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<131> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<130> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<129> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<128> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<127> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<126> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<125> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<124> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<123> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<122> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<121> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<120> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<119> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<118> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<117> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<116> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<115> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<114> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<113> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<112> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<111> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<110> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<109> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<108> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<107> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<106> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<105> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<104> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<103> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<102> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<101> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<100> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<99> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<98> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<97> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<96> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<95> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<94> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<93> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<92> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<91> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<90> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<89> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<88> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<87> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<86> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<85> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<84> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<83> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<82> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<81> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<80> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<79> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<78> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<77> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<76> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<75> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<74> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<73> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<72> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<71> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<70> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<69> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<68> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<67> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<66> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<65> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<64> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<63> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<62> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<61> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<60> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<59> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<58> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<57> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<56> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<55> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<54> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<53> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<52> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<51> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<50> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<49> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<48> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<47> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<46> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<45> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<44> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<43> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<42> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<41> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<40> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<39> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<38> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<37> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<36> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<35> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<34> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<33> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<32> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<31> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<30> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<29> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<28> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<27> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<26> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<25> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<24> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<23> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<22> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<21> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<20> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<19> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<18> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<17> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<16> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<15> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<14> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<13> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<12> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<11> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<10> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<9> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<8> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<7> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<6> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<5> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<4> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<3> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<2> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<1> VDD VSS / RSC_IHPSG13_FILLCAP8 +XDEC00<4> ADDR_N_I<7> ADDR_N_I<6> CS_I CS04<0> VDD VSS / ++ RM_IHPSG13_512x8_c3_2P_DEC00 +XDEC00<3> ADDR_N_I<5> ADDR_N_I<4> CS04<3> CS00<12> VDD VSS / ++ RM_IHPSG13_512x8_c3_2P_DEC00 +XDEC00<2> ADDR_N_I<5> ADDR_N_I<4> CS04<2> CS00<8> VDD VSS / ++ RM_IHPSG13_512x8_c3_2P_DEC00 +XDEC00<1> ADDR_N_I<5> ADDR_N_I<4> CS04<1> CS00<4> VDD VSS / ++ RM_IHPSG13_512x8_c3_2P_DEC00 +XDEC00<0> ADDR_N_I<5> ADDR_N_I<4> CS04<0> CS00<0> VDD VSS / ++ RM_IHPSG13_512x8_c3_2P_DEC00 +XDEC01<4> ADDR_N_I<7> ADDR_N_I<6> CS_I CS04<1> VDD VSS / ++ RM_IHPSG13_512x8_c3_2P_DEC01 +XDEC01<3> ADDR_N_I<5> ADDR_N_I<4> CS04<3> CS00<13> VDD VSS / ++ RM_IHPSG13_512x8_c3_2P_DEC01 +XDEC01<2> ADDR_N_I<5> ADDR_N_I<4> CS04<2> CS00<9> VDD VSS / ++ RM_IHPSG13_512x8_c3_2P_DEC01 +XDEC01<1> ADDR_N_I<5> ADDR_N_I<4> CS04<1> CS00<5> VDD VSS / ++ RM_IHPSG13_512x8_c3_2P_DEC01 +XDEC01<0> ADDR_N_I<5> ADDR_N_I<4> CS04<0> CS00<1> VDD VSS / ++ RM_IHPSG13_512x8_c3_2P_DEC01 +.ENDS +.SUBCKT RM_IHPSG13_512x8_c3_2P_ROWREG8 ACLK_N_I ADDR_I<7> ADDR_I<6> ADDR_I<5> ADDR_I<4> ++ ADDR_I<3> ADDR_I<2> ADDR_I<1> ADDR_I<0> ADDR_N_O<7> ADDR_N_O<6> ADDR_N_O<5> ++ ADDR_N_O<4> ADDR_N_O<3> ADDR_N_O<2> ADDR_N_O<1> ADDR_N_O<0> BIST_ADDR_I<7> ++ BIST_ADDR_I<6> BIST_ADDR_I<5> BIST_ADDR_I<4> BIST_ADDR_I<3> BIST_ADDR_I<2> ++ BIST_ADDR_I<1> BIST_ADDR_I<0> BIST_EN_I VDD VSS +XINV<7> q_int<7> qn_int<7> VDD VSS / RSC_IHPSG13_CINVX2 +XINV<6> q_int<6> qn_int<6> VDD VSS / RSC_IHPSG13_CINVX2 +XINV<5> q_int<5> qn_int<5> VDD VSS / RSC_IHPSG13_CINVX2 +XINV<4> q_int<4> qn_int<4> VDD VSS / RSC_IHPSG13_CINVX2 +XINV<3> q_int<3> qn_int<3> VDD VSS / RSC_IHPSG13_CINVX2 +XINV<2> q_int<2> qn_int<2> VDD VSS / RSC_IHPSG13_CINVX2 +XINV<1> q_int<1> qn_int<1> VDD VSS / RSC_IHPSG13_CINVX2 +XINV<0> q_int<0> qn_int<0> VDD VSS / RSC_IHPSG13_CINVX2 +XDRV<7> qn_int<7> ADDR_N_O<7> VDD VSS / RSC_IHPSG13_CINVX8 +XDRV<6> qn_int<6> ADDR_N_O<6> VDD VSS / RSC_IHPSG13_CINVX8 +XDRV<5> qn_int<5> ADDR_N_O<5> VDD VSS / RSC_IHPSG13_CINVX8 +XDRV<4> qn_int<4> ADDR_N_O<4> VDD VSS / RSC_IHPSG13_CINVX8 +XDRV<3> qn_int<3> ADDR_N_O<3> VDD VSS / RSC_IHPSG13_CINVX8 +XDRV<2> qn_int<2> ADDR_N_O<2> VDD VSS / RSC_IHPSG13_CINVX8 +XDRV<1> qn_int<1> ADDR_N_O<1> VDD VSS / RSC_IHPSG13_CINVX8 +XDRV<0> qn_int<0> ADDR_N_O<0> VDD VSS / RSC_IHPSG13_CINVX8 +XDFF<7> BIST_EN_I BIST_ADDR_I<7> ACLK_N_I ADDR_I<7> q_int<7> net2<0> VDD ++ VSS / RSC_IHPSG13_DFNQMX2IX1 +XDFF<6> BIST_EN_I BIST_ADDR_I<6> ACLK_N_I ADDR_I<6> q_int<6> net2<1> VDD ++ VSS / RSC_IHPSG13_DFNQMX2IX1 +XDFF<5> BIST_EN_I BIST_ADDR_I<5> ACLK_N_I ADDR_I<5> q_int<5> net2<2> VDD ++ VSS / RSC_IHPSG13_DFNQMX2IX1 +XDFF<4> BIST_EN_I BIST_ADDR_I<4> ACLK_N_I ADDR_I<4> q_int<4> net2<3> VDD ++ VSS / RSC_IHPSG13_DFNQMX2IX1 +XDFF<3> BIST_EN_I BIST_ADDR_I<3> ACLK_N_I ADDR_I<3> q_int<3> net2<4> VDD ++ VSS / RSC_IHPSG13_DFNQMX2IX1 +XDFF<2> BIST_EN_I BIST_ADDR_I<2> ACLK_N_I ADDR_I<2> q_int<2> net2<5> VDD ++ VSS / RSC_IHPSG13_DFNQMX2IX1 +XDFF<1> BIST_EN_I BIST_ADDR_I<1> ACLK_N_I ADDR_I<1> q_int<1> net2<6> VDD ++ VSS / RSC_IHPSG13_DFNQMX2IX1 +XDFF<0> BIST_EN_I BIST_ADDR_I<0> ACLK_N_I ADDR_I<0> q_int<0> net2<7> VDD ++ VSS / RSC_IHPSG13_DFNQMX2IX1 +XI11<4> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI11<3> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI11<2> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI11<1> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI10 VDD VSS / RSC_IHPSG13_FILLCAP4 +.ENDS +.SUBCKT RM_IHPSG13_512x8_c3_2P_COLDEC4 ACLK_N ADDR<3> ADDR<2> ADDR<1> ADDR<0> ++ ADDR_COL<1> ADDR_COL<0> ADDR_DEC<7> ADDR_DEC<6> ADDR_DEC<5> ADDR_DEC<4> ++ ADDR_DEC<3> ADDR_DEC<2> ADDR_DEC<1> ADDR_DEC<0> BIST_ADDR<3> BIST_ADDR<2> ++ BIST_ADDR<1> BIST_ADDR<0> BIST_EN_I VDD VSS +XI1<7> PADR<0> PADR<1> PADR<2> addr_n<7> VDD VSS / RSC_IHPSG13_NAND3X2 +XI1<6> NADR<0> PADR<1> PADR<2> addr_n<6> VDD VSS / RSC_IHPSG13_NAND3X2 +XI1<5> PADR<0> NADR<1> PADR<2> addr_n<5> VDD VSS / RSC_IHPSG13_NAND3X2 +XI1<4> NADR<0> NADR<1> PADR<2> addr_n<4> VDD VSS / RSC_IHPSG13_NAND3X2 +XI1<3> PADR<0> PADR<1> NADR<2> addr_n<3> VDD VSS / RSC_IHPSG13_NAND3X2 +XI1<2> NADR<0> PADR<1> NADR<2> addr_n<2> VDD VSS / RSC_IHPSG13_NAND3X2 +XI1<1> PADR<0> NADR<1> NADR<2> addr_n<1> VDD VSS / RSC_IHPSG13_NAND3X2 +XI1<0> NADR<0> NADR<1> NADR<2> addr_n<0> VDD VSS / RSC_IHPSG13_NAND3X2 +XDFF<3> BIST_EN_I BIST_ADDR<3> ACLK_N ADDR<3> addr_int net12<0> VDD ++ VSS / RSC_IHPSG13_DFNQMX2IX1 +XDFF<2> BIST_EN_I BIST_ADDR<2> ACLK_N ADDR<2> padr_int<2> net12<1> VDD ++ VSS / RSC_IHPSG13_DFNQMX2IX1 +XDFF<1> BIST_EN_I BIST_ADDR<1> ACLK_N ADDR<1> padr_int<1> net12<2> VDD ++ VSS / RSC_IHPSG13_DFNQMX2IX1 +XDFF<0> BIST_EN_I BIST_ADDR<0> ACLK_N ADDR<0> padr_int<0> net12<3> VDD ++ VSS / RSC_IHPSG13_DFNQMX2IX1 +XI17<4> VDD VSS / RSC_IHPSG13_FILLCAP4 +XI17<3> VDD VSS / RSC_IHPSG13_FILLCAP4 +XI17<2> VDD VSS / RSC_IHPSG13_FILLCAP4 +XI17<1> VDD VSS / RSC_IHPSG13_FILLCAP4 +XI13<2> NADR<2> PADR<2> VDD VSS / RSC_IHPSG13_INVX2 +XI13<1> NADR<1> PADR<1> VDD VSS / RSC_IHPSG13_INVX2 +XI13<0> NADR<0> PADR<0> VDD VSS / RSC_IHPSG13_INVX2 +XI2<7> addr_n<7> ADDR_DEC<7> VDD VSS / RSC_IHPSG13_INVX2 +XI2<6> addr_n<6> ADDR_DEC<6> VDD VSS / RSC_IHPSG13_INVX2 +XI2<5> addr_n<5> ADDR_DEC<5> VDD VSS / RSC_IHPSG13_INVX2 +XI2<4> addr_n<4> ADDR_DEC<4> VDD VSS / RSC_IHPSG13_INVX2 +XI2<3> addr_n<3> ADDR_DEC<3> VDD VSS / RSC_IHPSG13_INVX2 +XI2<2> addr_n<2> ADDR_DEC<2> VDD VSS / RSC_IHPSG13_INVX2 +XI2<1> addr_n<1> ADDR_DEC<1> VDD VSS / RSC_IHPSG13_INVX2 +XI2<0> addr_n<0> ADDR_DEC<0> VDD VSS / RSC_IHPSG13_INVX2 +XI3<2> padr_int<2> NADR<2> VDD VSS / RSC_IHPSG13_INVX2 +XI3<1> padr_int<1> NADR<1> VDD VSS / RSC_IHPSG13_INVX2 +XI3<0> padr_int<0> NADR<0> VDD VSS / RSC_IHPSG13_INVX2 +XI14 addr_int ADDR_COL<0> VDD VSS / RSC_IHPSG13_CBUFX2 +XI16<8> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI16<7> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI16<6> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI16<5> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI16<4> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI16<3> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI16<2> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI16<1> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI15 ADDR_COL<1> VDD VSS / RSC_IHPSG13_TIEL +.ENDS +.SUBCKT RM_IHPSG13_512x8_c3_2P_COLCTRL4 A_ADDR_COL A_ADDR_DEC<7> A_ADDR_DEC<6> ++ A_ADDR_DEC<5> A_ADDR_DEC<4> A_ADDR_DEC<3> A_ADDR_DEC<2> A_ADDR_DEC<1> ++ A_ADDR_DEC<0> A_BIST_BM_I A_BIST_DW_I A_BIST_EN_I A_BLC<15> A_BLC<14> ++ A_BLC<13> A_BLC<12> A_BLC<11> A_BLC<10> A_BLC<9> A_BLC<8> A_BLC<7> A_BLC<6> ++ A_BLC<5> A_BLC<4> A_BLC<3> A_BLC<2> A_BLC<1> A_BLC<0> A_BLT<15> A_BLT<14> ++ A_BLT<13> A_BLT<12> A_BLT<11> A_BLT<10> A_BLT<9> A_BLT<8> A_BLT<7> A_BLT<6> ++ A_BLT<5> A_BLT<4> A_BLT<3> A_BLT<2> A_BLT<1> A_BLT<0> A_BM_I A_DCLK_B_L ++ A_DCLK_B_R A_DCLK_L A_DCLK_R A_DR_O A_DW_I A_RCLK_B_L A_RCLK_B_R A_RCLK_L ++ A_RCLK_R A_TIEH_O A_WCLK_B_L A_WCLK_B_R A_WCLK_L A_WCLK_R B_ADDR_COL ++ B_ADDR_DEC<7> B_ADDR_DEC<6> B_ADDR_DEC<5> B_ADDR_DEC<4> B_ADDR_DEC<3> ++ B_ADDR_DEC<2> B_ADDR_DEC<1> B_ADDR_DEC<0> B_BIST_BM_I B_BIST_DW_I ++ B_BIST_EN_I B_BLC<15> B_BLC<14> B_BLC<13> B_BLC<12> B_BLC<11> B_BLC<10> ++ B_BLC<9> B_BLC<8> B_BLC<7> B_BLC<6> B_BLC<5> B_BLC<4> B_BLC<3> B_BLC<2> ++ B_BLC<1> B_BLC<0> B_BLT<15> B_BLT<14> B_BLT<13> B_BLT<12> B_BLT<11> ++ B_BLT<10> B_BLT<9> B_BLT<8> B_BLT<7> B_BLT<6> B_BLT<5> B_BLT<4> B_BLT<3> ++ B_BLT<2> B_BLT<1> B_BLT<0> B_BM_I B_DCLK_B_L B_DCLK_B_R B_DCLK_L B_DCLK_R ++ B_DR_O B_DW_I B_RCLK_B_L B_RCLK_B_R B_RCLK_L B_RCLK_R B_TIEH_O B_WCLK_B_L ++ B_WCLK_B_R B_WCLK_L B_WCLK_R VDD VSS +XB_I80 B_RCLK_B_L B_WCLK_B_L net041 VDD VSS / RSC_IHPSG13_AND2X2 +XA_I80 A_RCLK_B_L A_WCLK_B_L net21 VDD VSS / RSC_IHPSG13_AND2X2 +XB_I76 B_DI_N B_DO_WRITE_P B_WR_ZERO VDD VSS / RSC_IHPSG13_AND2X4 +XB_I75 B_DI_R B_DO_WRITE_P B_WR_ONE VDD VSS / RSC_IHPSG13_AND2X4 +XA_I76 A_DI_N A_DO_WRITE_P A_WR_ZERO VDD VSS / RSC_IHPSG13_AND2X4 +XA_I75 A_DI_R A_DO_WRITE_P A_WR_ONE VDD VSS / RSC_IHPSG13_AND2X4 +XI_FILL4<26> VDD VSS / RSC_IHPSG13_FILLCAP4 +XI_FILL4<25> VDD VSS / RSC_IHPSG13_FILLCAP4 +XI_FILL4<24> VDD VSS / RSC_IHPSG13_FILLCAP4 +XI_FILL4<23> VDD VSS / RSC_IHPSG13_FILLCAP4 +XI_FILL4<22> VDD VSS / RSC_IHPSG13_FILLCAP4 +XI_FILL4<21> VDD VSS / RSC_IHPSG13_FILLCAP4 +XI_FILL4<20> VDD VSS / RSC_IHPSG13_FILLCAP4 +XI_FILL4<19> VDD VSS / RSC_IHPSG13_FILLCAP4 +XI_FILL4<18> VDD VSS / RSC_IHPSG13_FILLCAP4 +XI_FILL4<17> VDD VSS / RSC_IHPSG13_FILLCAP4 +XI_FILL4<16> VDD VSS / RSC_IHPSG13_FILLCAP4 +XI_FILL4<15> VDD VSS / RSC_IHPSG13_FILLCAP4 +XI_FILL4<14> VDD VSS / RSC_IHPSG13_FILLCAP4 +XI_FILL4<13> VDD VSS / RSC_IHPSG13_FILLCAP4 +XI_FILL4<12> VDD VSS / RSC_IHPSG13_FILLCAP4 +XI_FILL4<11> VDD VSS / RSC_IHPSG13_FILLCAP4 +XI_FILL4<10> VDD VSS / RSC_IHPSG13_FILLCAP4 +XI_FILL4<9> VDD VSS / RSC_IHPSG13_FILLCAP4 +XI_FILL4<8> VDD VSS / RSC_IHPSG13_FILLCAP4 +XI_FILL4<7> VDD VSS / RSC_IHPSG13_FILLCAP4 +XI_FILL4<6> VDD VSS / RSC_IHPSG13_FILLCAP4 +XI_FILL4<5> VDD VSS / RSC_IHPSG13_FILLCAP4 +XI_FILL4<4> VDD VSS / RSC_IHPSG13_FILLCAP4 +XI_FILL4<3> VDD VSS / RSC_IHPSG13_FILLCAP4 +XI_FILL4<2> VDD VSS / RSC_IHPSG13_FILLCAP4 +XI_FILL4<1> VDD VSS / RSC_IHPSG13_FILLCAP4 +XB_I69 B_DCLK_L B_DCLK_B_L VDD VSS / RSC_IHPSG13_CINVX4 +XB_I50 B_WCLK_L B_WCLK_B_L VDD VSS / RSC_IHPSG13_CINVX4 +XB_EBUF B_RCLK_L B_RCLK_B_L VDD VSS / RSC_IHPSG13_CINVX4 +XB_INV<1> B_N0 B_P0 VDD VSS / RSC_IHPSG13_CINVX4 +XB_INV<0> B_ADDR_COL B_N0 VDD VSS / RSC_IHPSG13_CINVX4 +XA_I69 A_DCLK_L A_DCLK_B_L VDD VSS / RSC_IHPSG13_CINVX4 +XA_I50 A_WCLK_L A_WCLK_B_L VDD VSS / RSC_IHPSG13_CINVX4 +XA_EBUF A_RCLK_L A_RCLK_B_L VDD VSS / RSC_IHPSG13_CINVX4 +XA_INV<1> A_N0 A_P0 VDD VSS / RSC_IHPSG13_CINVX4 +XA_INV<0> A_ADDR_COL A_N0 VDD VSS / RSC_IHPSG13_CINVX4 +XB_I81<1> net041 B_PRE_N VDD VSS / RSC_IHPSG13_CINVX4_WN +XB_I81<0> net041 B_PRE_N VDD VSS / RSC_IHPSG13_CINVX4_WN +XA_I81<1> net21 A_PRE_N VDD VSS / RSC_IHPSG13_CINVX4_WN +XA_I81<0> net21 A_PRE_N VDD VSS / RSC_IHPSG13_CINVX4_WN +XA_R2 A_RCLK_L A_RCLK_R / RSC_IHPSG13_MET3RES +XA_I87 A_WCLK_L A_WCLK_R / RSC_IHPSG13_MET3RES +XA_I88 A_DCLK_L A_DCLK_R / RSC_IHPSG13_MET3RES +XA_I89 A_DCLK_B_L A_DCLK_B_R / RSC_IHPSG13_MET3RES +XA_I90 A_WCLK_B_L A_WCLK_B_R / RSC_IHPSG13_MET3RES +XA_I91 A_RCLK_B_L A_RCLK_B_R / RSC_IHPSG13_MET3RES +XB_R2 B_RCLK_L B_RCLK_R / RSC_IHPSG13_MET3RES +XB_I87 B_WCLK_L B_WCLK_R / RSC_IHPSG13_MET3RES +XB_I88 B_DCLK_L B_DCLK_R / RSC_IHPSG13_MET3RES +XB_I89 B_DCLK_B_L B_DCLK_B_R / RSC_IHPSG13_MET3RES +XB_I90 B_WCLK_B_L B_WCLK_B_R / RSC_IHPSG13_MET3RES +XB_I91 B_RCLK_B_L B_RCLK_B_R / RSC_IHPSG13_MET3RES +XA_ISENSE A_SAE A_BLC_SEL A_BLT_SEL net19 net20 VDD VSS / ++ RSC_IHPSG13_DFPQD_MSAFFX2 +XB_ISENSE B_SAE B_BLC_SEL B_BLT_SEL net037 net038 VDD VSS / ++ RSC_IHPSG13_DFPQD_MSAFFX2 +XAB_BLMUX<3> A_BLC<15> A_BLC<14> A_BLC<13> A_BLC<12> A_BLC_SEL A_BLT<15> ++ A_BLT<14> A_BLT<13> A_BLT<12> A_BLT_SEL A_PRE_N A_SEL_P<15> A_SEL_P<14> ++ A_SEL_P<13> A_SEL_P<12> A_WR_ONE A_WR_ZERO B_BLC<15> B_BLC<14> B_BLC<13> ++ B_BLC<12> B_BLC_SEL B_BLT<15> B_BLT<14> B_BLT<13> B_BLT<12> B_BLT_SEL ++ B_PRE_N B_SEL_P<15> B_SEL_P<14> B_SEL_P<13> B_SEL_P<12> B_WR_ONE B_WR_ZERO ++ VDD VSS / RM_IHPSG13_512x8_c3_2P_BLDRV +XAB_BLMUX<2> A_BLC<11> A_BLC<10> A_BLC<9> A_BLC<8> A_BLC_SEL A_BLT<11> ++ A_BLT<10> A_BLT<9> A_BLT<8> A_BLT_SEL A_PRE_N A_SEL_P<11> A_SEL_P<10> ++ A_SEL_P<9> A_SEL_P<8> A_WR_ONE A_WR_ZERO B_BLC<11> B_BLC<10> B_BLC<9> ++ B_BLC<8> B_BLC_SEL B_BLT<11> B_BLT<10> B_BLT<9> B_BLT<8> B_BLT_SEL B_PRE_N ++ B_SEL_P<11> B_SEL_P<10> B_SEL_P<9> B_SEL_P<8> B_WR_ONE B_WR_ZERO VDD ++ VSS / RM_IHPSG13_512x8_c3_2P_BLDRV +XAB_BLMUX<1> A_BLC<7> A_BLC<6> A_BLC<5> A_BLC<4> A_BLC_SEL A_BLT<7> A_BLT<6> ++ A_BLT<5> A_BLT<4> A_BLT_SEL A_PRE_N A_SEL_P<7> A_SEL_P<6> A_SEL_P<5> ++ A_SEL_P<4> A_WR_ONE A_WR_ZERO B_BLC<7> B_BLC<6> B_BLC<5> B_BLC<4> B_BLC_SEL ++ B_BLT<7> B_BLT<6> B_BLT<5> B_BLT<4> B_BLT_SEL B_PRE_N B_SEL_P<7> B_SEL_P<6> ++ B_SEL_P<5> B_SEL_P<4> B_WR_ONE B_WR_ZERO VDD VSS / ++ RM_IHPSG13_512x8_c3_2P_BLDRV +XAB_BLMUX<0> A_BLC<3> A_BLC<2> A_BLC<1> A_BLC<0> A_BLC_SEL A_BLT<3> A_BLT<2> ++ A_BLT<1> A_BLT<0> A_BLT_SEL A_PRE_N A_SEL_P<3> A_SEL_P<2> A_SEL_P<1> ++ A_SEL_P<0> A_WR_ONE A_WR_ZERO B_BLC<3> B_BLC<2> B_BLC<1> B_BLC<0> B_BLC_SEL ++ B_BLT<3> B_BLT<2> B_BLT<1> B_BLT<0> B_BLT_SEL B_PRE_N B_SEL_P<3> B_SEL_P<2> ++ B_SEL_P<1> B_SEL_P<0> B_WR_ONE B_WR_ZERO VDD VSS / ++ RM_IHPSG13_512x8_c3_2P_BLDRV +XA_I51 net19 A_DR_O VDD VSS / RSC_IHPSG13_INVX4 +XB_I51 net037 B_DR_O VDD VSS / RSC_IHPSG13_INVX4 +XA_I78 A_RCLK_B_L A_SAE VDD VSS / RSC_IHPSG13_CBUFX2 +XB_I78 B_RCLK_B_L B_SAE VDD VSS / RSC_IHPSG13_CBUFX2 +XA_DREG A_BIST_EN_I A_BIST_DW_I A_DCLK_B_L A_DW_I A_DI_R net22 VDD VSS ++ / RSC_IHPSG13_DFNQMX2IX1 +XB_DREG B_BIST_EN_I B_BIST_DW_I B_DCLK_B_L B_DW_I B_DI_R net046 VDD ++ VSS / RSC_IHPSG13_DFNQMX2IX1 +XB_BREG B_BIST_EN_I B_BIST_BM_I B_DCLK_B_L B_BM_I B_BM_R net045 VDD ++ VSS / RSC_IHPSG13_DFNQMX2IX1 +XA_BREG A_BIST_EN_I A_BIST_BM_I A_DCLK_B_L A_BM_I A_BM_R net24 VDD VSS ++ / RSC_IHPSG13_DFNQMX2IX1 +XA_DEC3INV<15> net23<0> A_SEL_P<15> VDD VSS / RSC_IHPSG13_INVX2 +XA_DEC3INV<14> net23<1> A_SEL_P<14> VDD VSS / RSC_IHPSG13_INVX2 +XA_DEC3INV<13> net23<2> A_SEL_P<13> VDD VSS / RSC_IHPSG13_INVX2 +XA_DEC3INV<12> net23<3> A_SEL_P<12> VDD VSS / RSC_IHPSG13_INVX2 +XA_DEC3INV<11> net23<4> A_SEL_P<11> VDD VSS / RSC_IHPSG13_INVX2 +XA_DEC3INV<10> net23<5> A_SEL_P<10> VDD VSS / RSC_IHPSG13_INVX2 +XA_DEC3INV<9> net23<6> A_SEL_P<9> VDD VSS / RSC_IHPSG13_INVX2 +XA_DEC3INV<8> net23<7> A_SEL_P<8> VDD VSS / RSC_IHPSG13_INVX2 +XA_DEC3INV<7> net23<8> A_SEL_P<7> VDD VSS / RSC_IHPSG13_INVX2 +XA_DEC3INV<6> net23<9> A_SEL_P<6> VDD VSS / RSC_IHPSG13_INVX2 +XA_DEC3INV<5> net23<10> A_SEL_P<5> VDD VSS / RSC_IHPSG13_INVX2 +XA_DEC3INV<4> net23<11> A_SEL_P<4> VDD VSS / RSC_IHPSG13_INVX2 +XA_DEC3INV<3> net23<12> A_SEL_P<3> VDD VSS / RSC_IHPSG13_INVX2 +XA_DEC3INV<2> net23<13> A_SEL_P<2> VDD VSS / RSC_IHPSG13_INVX2 +XA_DEC3INV<1> net23<14> A_SEL_P<1> VDD VSS / RSC_IHPSG13_INVX2 +XA_DEC3INV<0> net23<15> A_SEL_P<0> VDD VSS / RSC_IHPSG13_INVX2 +XA_I83 A_BM_R A_BM_N VDD VSS / RSC_IHPSG13_INVX2 +XA_I49 A_DI_R A_DI_N VDD VSS / RSC_IHPSG13_INVX2 +XB_DEC3INV<15> net044<0> B_SEL_P<15> VDD VSS / RSC_IHPSG13_INVX2 +XB_DEC3INV<14> net044<1> B_SEL_P<14> VDD VSS / RSC_IHPSG13_INVX2 +XB_DEC3INV<13> net044<2> B_SEL_P<13> VDD VSS / RSC_IHPSG13_INVX2 +XB_DEC3INV<12> net044<3> B_SEL_P<12> VDD VSS / RSC_IHPSG13_INVX2 +XB_DEC3INV<11> net044<4> B_SEL_P<11> VDD VSS / RSC_IHPSG13_INVX2 +XB_DEC3INV<10> net044<5> B_SEL_P<10> VDD VSS / RSC_IHPSG13_INVX2 +XB_DEC3INV<9> net044<6> B_SEL_P<9> VDD VSS / RSC_IHPSG13_INVX2 +XB_DEC3INV<8> net044<7> B_SEL_P<8> VDD VSS / RSC_IHPSG13_INVX2 +XB_DEC3INV<7> net044<8> B_SEL_P<7> VDD VSS / RSC_IHPSG13_INVX2 +XB_DEC3INV<6> net044<9> B_SEL_P<6> VDD VSS / RSC_IHPSG13_INVX2 +XB_DEC3INV<5> net044<10> B_SEL_P<5> VDD VSS / RSC_IHPSG13_INVX2 +XB_DEC3INV<4> net044<11> B_SEL_P<4> VDD VSS / RSC_IHPSG13_INVX2 +XB_DEC3INV<3> net044<12> B_SEL_P<3> VDD VSS / RSC_IHPSG13_INVX2 +XB_DEC3INV<2> net044<13> B_SEL_P<2> VDD VSS / RSC_IHPSG13_INVX2 +XB_DEC3INV<1> net044<14> B_SEL_P<1> VDD VSS / RSC_IHPSG13_INVX2 +XB_DEC3INV<0> net044<15> B_SEL_P<0> VDD VSS / RSC_IHPSG13_INVX2 +XB_I83 B_BM_R B_BM_N VDD VSS / RSC_IHPSG13_INVX2 +XB_I49 B_DI_R B_DI_N VDD VSS / RSC_IHPSG13_INVX2 +XI_FILL8<20> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI_FILL8<19> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI_FILL8<18> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI_FILL8<17> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI_FILL8<16> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI_FILL8<15> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI_FILL8<14> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI_FILL8<13> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI_FILL8<12> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI_FILL8<11> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI_FILL8<10> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI_FILL8<9> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI_FILL8<8> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI_FILL8<7> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI_FILL8<6> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI_FILL8<5> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI_FILL8<4> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI_FILL8<3> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI_FILL8<2> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI_FILL8<1> VDD VSS / RSC_IHPSG13_FILLCAP8 +XA_I44 A_BM_N A_WCLK_B_L A_DO_WRITE_P VDD VSS / RSC_IHPSG13_NOR2X2 +XB_I44 B_BM_N B_WCLK_B_L B_DO_WRITE_P VDD VSS / RSC_IHPSG13_NOR2X2 +XA_DEC3<15> A_P0 A_ADDR_DEC<7> net23<0> VDD VSS / RSC_IHPSG13_NAND2X2 +XA_DEC3<14> A_P0 A_ADDR_DEC<6> net23<1> VDD VSS / RSC_IHPSG13_NAND2X2 +XA_DEC3<13> A_P0 A_ADDR_DEC<5> net23<2> VDD VSS / RSC_IHPSG13_NAND2X2 +XA_DEC3<12> A_P0 A_ADDR_DEC<4> net23<3> VDD VSS / RSC_IHPSG13_NAND2X2 +XA_DEC3<11> A_P0 A_ADDR_DEC<3> net23<4> VDD VSS / RSC_IHPSG13_NAND2X2 +XA_DEC3<10> A_P0 A_ADDR_DEC<2> net23<5> VDD VSS / RSC_IHPSG13_NAND2X2 +XA_DEC3<9> A_P0 A_ADDR_DEC<1> net23<6> VDD VSS / RSC_IHPSG13_NAND2X2 +XA_DEC3<8> A_P0 A_ADDR_DEC<0> net23<7> VDD VSS / RSC_IHPSG13_NAND2X2 +XA_DEC3<7> A_N0 A_ADDR_DEC<7> net23<8> VDD VSS / RSC_IHPSG13_NAND2X2 +XA_DEC3<6> A_N0 A_ADDR_DEC<6> net23<9> VDD VSS / RSC_IHPSG13_NAND2X2 +XA_DEC3<5> A_N0 A_ADDR_DEC<5> net23<10> VDD VSS / RSC_IHPSG13_NAND2X2 +XA_DEC3<4> A_N0 A_ADDR_DEC<4> net23<11> VDD VSS / RSC_IHPSG13_NAND2X2 +XA_DEC3<3> A_N0 A_ADDR_DEC<3> net23<12> VDD VSS / RSC_IHPSG13_NAND2X2 +XA_DEC3<2> A_N0 A_ADDR_DEC<2> net23<13> VDD VSS / RSC_IHPSG13_NAND2X2 +XA_DEC3<1> A_N0 A_ADDR_DEC<1> net23<14> VDD VSS / RSC_IHPSG13_NAND2X2 +XA_DEC3<0> A_N0 A_ADDR_DEC<0> net23<15> VDD VSS / RSC_IHPSG13_NAND2X2 +XB_DEC3<15> B_P0 B_ADDR_DEC<7> net044<0> VDD VSS / RSC_IHPSG13_NAND2X2 +XB_DEC3<14> B_P0 B_ADDR_DEC<6> net044<1> VDD VSS / RSC_IHPSG13_NAND2X2 +XB_DEC3<13> B_P0 B_ADDR_DEC<5> net044<2> VDD VSS / RSC_IHPSG13_NAND2X2 +XB_DEC3<12> B_P0 B_ADDR_DEC<4> net044<3> VDD VSS / RSC_IHPSG13_NAND2X2 +XB_DEC3<11> B_P0 B_ADDR_DEC<3> net044<4> VDD VSS / RSC_IHPSG13_NAND2X2 +XB_DEC3<10> B_P0 B_ADDR_DEC<2> net044<5> VDD VSS / RSC_IHPSG13_NAND2X2 +XB_DEC3<9> B_P0 B_ADDR_DEC<1> net044<6> VDD VSS / RSC_IHPSG13_NAND2X2 +XB_DEC3<8> B_P0 B_ADDR_DEC<0> net044<7> VDD VSS / RSC_IHPSG13_NAND2X2 +XB_DEC3<7> B_N0 B_ADDR_DEC<7> net044<8> VDD VSS / RSC_IHPSG13_NAND2X2 +XB_DEC3<6> B_N0 B_ADDR_DEC<6> net044<9> VDD VSS / RSC_IHPSG13_NAND2X2 +XB_DEC3<5> B_N0 B_ADDR_DEC<5> net044<10> VDD VSS / RSC_IHPSG13_NAND2X2 +XB_DEC3<4> B_N0 B_ADDR_DEC<4> net044<11> VDD VSS / RSC_IHPSG13_NAND2X2 +XB_DEC3<3> B_N0 B_ADDR_DEC<3> net044<12> VDD VSS / RSC_IHPSG13_NAND2X2 +XB_DEC3<2> B_N0 B_ADDR_DEC<2> net044<13> VDD VSS / RSC_IHPSG13_NAND2X2 +XB_DEC3<1> B_N0 B_ADDR_DEC<1> net044<14> VDD VSS / RSC_IHPSG13_NAND2X2 +XB_DEC3<0> B_N0 B_ADDR_DEC<0> net044<15> VDD VSS / RSC_IHPSG13_NAND2X2 +XB_BM_TIEH B_TIEH_O VDD VSS / RSC_IHPSG13_TIEH +XA_BM_TIEH A_TIEH_O VDD VSS / RSC_IHPSG13_TIEH +.ENDS + + +.SUBCKT RM_IHPSG13_512x8_c3_2P_ROWDEC5 ADDR_N_I<4> ADDR_N_I<3> ADDR_N_I<2> ADDR_N_I<1> ++ ADDR_N_I<0> CS_I ECLK_I WL_O<31> WL_O<30> WL_O<29> WL_O<28> WL_O<27> ++ WL_O<26> WL_O<25> WL_O<24> WL_O<23> WL_O<22> WL_O<21> WL_O<20> WL_O<19> ++ WL_O<18> WL_O<17> WL_O<16> WL_O<15> WL_O<14> WL_O<13> WL_O<12> WL_O<11> ++ WL_O<10> WL_O<9> WL_O<8> WL_O<7> WL_O<6> WL_O<5> WL_O<4> WL_O<3> WL_O<2> ++ WL_O<1> WL_O<0> VDD VSS +XDEC00 ADDR_N_I<5> ADDR_N_I<4> CS_I CS00<0> VDD VSS / ++ RM_IHPSG13_512x8_c3_2P_DEC00 +XSEL<1> ADDR_N_I<3> ADDR_N_I<2> ADDR_N_I<1> ADDR_N_I<0> CS00<1> ECLK_H<1> ++ ECLK_H<2> ECLK_B<1> ECLK_B<2> WL_O<31> WL_O<30> WL_O<29> WL_O<28> WL_O<27> ++ WL_O<26> WL_O<25> WL_O<24> WL_O<23> WL_O<22> WL_O<21> WL_O<20> WL_O<19> ++ WL_O<18> WL_O<17> WL_O<16> VDD VSS / RM_IHPSG13_512x8_c3_2P_DEC04 +XSEL<0> ADDR_N_I<3> ADDR_N_I<2> ADDR_N_I<1> ADDR_N_I<0> CS00<0> ECLK_I ++ ECLK_H<1> ECLK_B<0> ECLK_B<1> WL_O<15> WL_O<14> WL_O<13> WL_O<12> WL_O<11> ++ WL_O<10> WL_O<9> WL_O<8> WL_O<7> WL_O<6> WL_O<5> WL_O<4> WL_O<3> WL_O<2> ++ WL_O<1> WL_O<0> VDD VSS / RM_IHPSG13_512x8_c3_2P_DEC04 +XDEC01 ADDR_N_I<5> ADDR_N_I<4> CS_I CS00<1> VDD VSS / ++ RM_IHPSG13_512x8_c3_2P_DEC01 +XL2<18> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<17> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<16> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<15> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<14> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<13> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<12> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<11> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<10> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<9> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<8> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<7> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<6> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<5> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<4> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<3> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<2> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<1> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI0 ADDR_N_I<5> VDD VSS / RSC_IHPSG13_TIEL +.ENDS +.SUBCKT RM_IHPSG13_512x8_c3_2P_ROWREG5 ACLK_N_I ADDR_I<4> ADDR_I<3> ADDR_I<2> ADDR_I<1> ++ ADDR_I<0> ADDR_N_O<4> ADDR_N_O<3> ADDR_N_O<2> ADDR_N_O<1> ADDR_N_O<0> ++ BIST_ADDR_I<4> BIST_ADDR_I<3> BIST_ADDR_I<2> BIST_ADDR_I<1> BIST_ADDR_I<0> ++ BIST_EN_I VDD VSS +XINV<4> q_int<4> qn_int<4> VDD VSS / RSC_IHPSG13_CINVX2 +XINV<3> q_int<3> qn_int<3> VDD VSS / RSC_IHPSG13_CINVX2 +XINV<2> q_int<2> qn_int<2> VDD VSS / RSC_IHPSG13_CINVX2 +XINV<1> q_int<1> qn_int<1> VDD VSS / RSC_IHPSG13_CINVX2 +XINV<0> q_int<0> qn_int<0> VDD VSS / RSC_IHPSG13_CINVX2 +XDRV<4> qn_int<4> ADDR_N_O<4> VDD VSS / RSC_IHPSG13_CINVX8 +XDRV<3> qn_int<3> ADDR_N_O<3> VDD VSS / RSC_IHPSG13_CINVX8 +XDRV<2> qn_int<2> ADDR_N_O<2> VDD VSS / RSC_IHPSG13_CINVX8 +XDRV<1> qn_int<1> ADDR_N_O<1> VDD VSS / RSC_IHPSG13_CINVX8 +XDRV<0> qn_int<0> ADDR_N_O<0> VDD VSS / RSC_IHPSG13_CINVX8 +XDFF<4> BIST_EN_I BIST_ADDR_I<4> ACLK_N_I ADDR_I<4> q_int<4> net2<0> VDD ++ VSS / RSC_IHPSG13_DFNQMX2IX1 +XDFF<3> BIST_EN_I BIST_ADDR_I<3> ACLK_N_I ADDR_I<3> q_int<3> net2<1> VDD ++ VSS / RSC_IHPSG13_DFNQMX2IX1 +XDFF<2> BIST_EN_I BIST_ADDR_I<2> ACLK_N_I ADDR_I<2> q_int<2> net2<2> VDD ++ VSS / RSC_IHPSG13_DFNQMX2IX1 +XDFF<1> BIST_EN_I BIST_ADDR_I<1> ACLK_N_I ADDR_I<1> q_int<1> net2<3> VDD ++ VSS / RSC_IHPSG13_DFNQMX2IX1 +XDFF<0> BIST_EN_I BIST_ADDR_I<0> ACLK_N_I ADDR_I<0> q_int<0> net2<4> VDD ++ VSS / RSC_IHPSG13_DFNQMX2IX1 +XI11<16> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI11<15> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI11<14> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI11<13> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI11<12> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI11<11> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI11<10> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI11<9> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI11<8> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI11<7> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI11<6> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI11<5> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI11<4> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI11<3> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI11<2> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI11<1> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI12<3> VDD VSS / RSC_IHPSG13_FILLCAP4 +XI12<2> VDD VSS / RSC_IHPSG13_FILLCAP4 +XI12<1> VDD VSS / RSC_IHPSG13_FILLCAP4 +XI12<0> VDD VSS / RSC_IHPSG13_FILLCAP4 +.ENDS + + +.SUBCKT RM_IHPSG13_512x8_c3_2P_COLDEC3 ACLK_N ADDR<2> ADDR<1> ADDR<0> ADDR_COL<1> ++ ADDR_COL<0> ADDR_DEC<7> ADDR_DEC<6> ADDR_DEC<5> ADDR_DEC<4> ADDR_DEC<3> ++ ADDR_DEC<2> ADDR_DEC<1> ADDR_DEC<0> BIST_ADDR<2> BIST_ADDR<1> BIST_ADDR<0> ++ BIST_EN_I VDD VSS +XI1<7> PADR<0> PADR<1> PADR<2> addr_n<7> VDD VSS / RSC_IHPSG13_NAND3X2 +XI1<6> NADR<0> PADR<1> PADR<2> addr_n<6> VDD VSS / RSC_IHPSG13_NAND3X2 +XI1<5> PADR<0> NADR<1> PADR<2> addr_n<5> VDD VSS / RSC_IHPSG13_NAND3X2 +XI1<4> NADR<0> NADR<1> PADR<2> addr_n<4> VDD VSS / RSC_IHPSG13_NAND3X2 +XI1<3> PADR<0> PADR<1> NADR<2> addr_n<3> VDD VSS / RSC_IHPSG13_NAND3X2 +XI1<2> NADR<0> PADR<1> NADR<2> addr_n<2> VDD VSS / RSC_IHPSG13_NAND3X2 +XI1<1> PADR<0> NADR<1> NADR<2> addr_n<1> VDD VSS / RSC_IHPSG13_NAND3X2 +XI1<0> NADR<0> NADR<1> NADR<2> addr_n<0> VDD VSS / RSC_IHPSG13_NAND3X2 +XDFF<2> BIST_EN_I BIST_ADDR<2> ACLK_N ADDR<2> padr_int<2> net13<0> VDD ++ VSS / RSC_IHPSG13_DFNQMX2IX1 +XDFF<1> BIST_EN_I BIST_ADDR<1> ACLK_N ADDR<1> padr_int<1> net13<1> VDD ++ VSS / RSC_IHPSG13_DFNQMX2IX1 +XDFF<0> BIST_EN_I BIST_ADDR<0> ACLK_N ADDR<0> padr_int<0> net13<2> VDD ++ VSS / RSC_IHPSG13_DFNQMX2IX1 +XI15<1> ADDR_COL<1> VDD VSS / RSC_IHPSG13_TIEL +XI15<0> ADDR_COL<0> VDD VSS / RSC_IHPSG13_TIEL +XI13<2> NADR<2> PADR<2> VDD VSS / RSC_IHPSG13_INVX2 +XI13<1> NADR<1> PADR<1> VDD VSS / RSC_IHPSG13_INVX2 +XI13<0> NADR<0> PADR<0> VDD VSS / RSC_IHPSG13_INVX2 +XI3<2> padr_int<2> NADR<2> VDD VSS / RSC_IHPSG13_INVX2 +XI3<1> padr_int<1> NADR<1> VDD VSS / RSC_IHPSG13_INVX2 +XI3<0> padr_int<0> NADR<0> VDD VSS / RSC_IHPSG13_INVX2 +XI2<7> addr_n<7> ADDR_DEC<7> VDD VSS / RSC_IHPSG13_INVX2 +XI2<6> addr_n<6> ADDR_DEC<6> VDD VSS / RSC_IHPSG13_INVX2 +XI2<5> addr_n<5> ADDR_DEC<5> VDD VSS / RSC_IHPSG13_INVX2 +XI2<4> addr_n<4> ADDR_DEC<4> VDD VSS / RSC_IHPSG13_INVX2 +XI2<3> addr_n<3> ADDR_DEC<3> VDD VSS / RSC_IHPSG13_INVX2 +XI2<2> addr_n<2> ADDR_DEC<2> VDD VSS / RSC_IHPSG13_INVX2 +XI2<1> addr_n<1> ADDR_DEC<1> VDD VSS / RSC_IHPSG13_INVX2 +XI2<0> addr_n<0> ADDR_DEC<0> VDD VSS / RSC_IHPSG13_INVX2 +XI17<4> VDD VSS / RSC_IHPSG13_FILLCAP4 +XI17<3> VDD VSS / RSC_IHPSG13_FILLCAP4 +XI17<2> VDD VSS / RSC_IHPSG13_FILLCAP4 +XI17<1> VDD VSS / RSC_IHPSG13_FILLCAP4 +XI16<11> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI16<10> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI16<9> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI16<8> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI16<7> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI16<6> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI16<5> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI16<4> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI16<3> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI16<2> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI16<1> VDD VSS / RSC_IHPSG13_FILLCAP8 +.ENDS +.SUBCKT RSC_IHPSG13_DFPQD_MSAFFX2P CP DN DP QN QP VDD VSS +XI_AMP CP DN DP QN QP VDD VSS / RSC_IHPSG13_DFPQD_MSAFFX2 +.ENDS +.SUBCKT RM_IHPSG13_512x8_c3_2P_COLCTRL3 A_ADDR_DEC<7> A_ADDR_DEC<6> A_ADDR_DEC<5> ++ A_ADDR_DEC<4> A_ADDR_DEC<3> A_ADDR_DEC<2> A_ADDR_DEC<1> A_ADDR_DEC<0> ++ A_BIST_BM_I A_BIST_DW_I A_BIST_EN_I A_BLC<7> A_BLC<6> A_BLC<5> A_BLC<4> ++ A_BLC<3> A_BLC<2> A_BLC<1> A_BLC<0> A_BLT<7> A_BLT<6> A_BLT<5> A_BLT<4> ++ A_BLT<3> A_BLT<2> A_BLT<1> A_BLT<0> A_BM_I A_DCLK_B_L A_DCLK_B_R A_DCLK_L ++ A_DCLK_R A_DR_O A_DW_I A_RCLK_B_L A_RCLK_B_R A_RCLK_L A_RCLK_R A_TIEH_O ++ A_WCLK_B_L A_WCLK_B_R A_WCLK_L A_WCLK_R B_ADDR_DEC<7> B_ADDR_DEC<6> ++ B_ADDR_DEC<5> B_ADDR_DEC<4> B_ADDR_DEC<3> B_ADDR_DEC<2> B_ADDR_DEC<1> ++ B_ADDR_DEC<0> B_BIST_BM_I B_BIST_DW_I B_BIST_EN_I B_BLC<7> B_BLC<6> B_BLC<5> ++ B_BLC<4> B_BLC<3> B_BLC<2> B_BLC<1> B_BLC<0> B_BLT<7> B_BLT<6> B_BLT<5> ++ B_BLT<4> B_BLT<3> B_BLT<2> B_BLT<1> B_BLT<0> B_BM_I B_DCLK_B_L B_DCLK_B_R ++ B_DCLK_L B_DCLK_R B_DR_O B_DW_I B_RCLK_B_L B_RCLK_B_R B_RCLK_L B_RCLK_R ++ B_TIEH_O B_WCLK_B_L B_WCLK_B_R B_WCLK_L B_WCLK_R VDD VSS +XB_DREG B_BIST_EN_I B_BIST_DW_I B_DCLK_B_L B_DW_I B_DI_R net044 VDD ++ VSS / RSC_IHPSG13_DFNQMX2IX1 +XB_BREG B_BIST_EN_I B_BIST_BM_I B_DCLK_B_L B_BM_I B_BM_R net043 VDD ++ VSS / RSC_IHPSG13_DFNQMX2IX1 +XA_DREG A_BIST_EN_I A_BIST_DW_I A_DCLK_B_L A_DW_I A_DI_R net22 VDD VSS ++ / RSC_IHPSG13_DFNQMX2IX1 +XA_BREG A_BIST_EN_I A_BIST_BM_I A_DCLK_B_L A_BM_I A_BM_R net23 VDD VSS ++ / RSC_IHPSG13_DFNQMX2IX1 +XI_FILL8<11> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI_FILL8<10> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI_FILL8<9> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI_FILL8<8> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI_FILL8<7> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI_FILL8<6> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI_FILL8<5> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI_FILL8<4> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI_FILL8<3> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI_FILL8<2> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI_FILL8<1> VDD VSS / RSC_IHPSG13_FILLCAP8 +XB_I51 net037 B_DR_O VDD VSS / RSC_IHPSG13_INVX4 +XA_I51 net19 A_DR_O VDD VSS / RSC_IHPSG13_INVX4 +XB_I44 B_BM_N B_WCLK_B_L B_DO_WRITE_P VDD VSS / RSC_IHPSG13_NOR2X2 +XA_I44 A_BM_N A_WCLK_B_L A_DO_WRITE_P VDD VSS / RSC_IHPSG13_NOR2X2 +XB_BM_TIEH B_TIEH_O VDD VSS / RSC_IHPSG13_TIEH +XA_BM_TIEH A_TIEH_O VDD VSS / RSC_IHPSG13_TIEH +XB_ISENSE B_SAE B_BLC_SEL B_BLT_SEL net037 net038 VDD VSS / ++ RSC_IHPSG13_DFPQD_MSAFFX2P +XA_ISENSE A_SAE A_BLC_SEL A_BLT_SEL net19 net20 VDD VSS / ++ RSC_IHPSG13_DFPQD_MSAFFX2P +XB_I49 B_DI_R B_DI_N VDD VSS / RSC_IHPSG13_INVX2 +XB_I83 B_BM_R B_BM_N VDD VSS / RSC_IHPSG13_INVX2 +XA_I49 A_DI_R A_DI_N VDD VSS / RSC_IHPSG13_INVX2 +XA_I83 A_BM_R A_BM_N VDD VSS / RSC_IHPSG13_INVX2 +XB_I69 B_DCLK_L B_DCLK_B_L VDD VSS / RSC_IHPSG13_CINVX2 +XB_I50 B_WCLK_L B_WCLK_B_L VDD VSS / RSC_IHPSG13_CINVX2 +XB_EBUF B_RCLK_L B_RCLK_B_L VDD VSS / RSC_IHPSG13_CINVX2 +XA_I69 A_DCLK_L A_DCLK_B_L VDD VSS / RSC_IHPSG13_CINVX2 +XA_I50 A_WCLK_L A_WCLK_B_L VDD VSS / RSC_IHPSG13_CINVX2 +XA_EBUF A_RCLK_L A_RCLK_B_L VDD VSS / RSC_IHPSG13_CINVX2 +XAB_BLMUX<1> A_BLC<7> A_BLC<6> A_BLC<5> A_BLC<4> A_BLC_SEL A_BLT<7> A_BLT<6> ++ A_BLT<5> A_BLT<4> A_BLT_SEL A_PRE_N A_ADDR_DEC<7> A_ADDR_DEC<6> ++ A_ADDR_DEC<5> A_ADDR_DEC<4> A_WR_ONE A_WR_ZERO B_BLC<7> B_BLC<6> B_BLC<5> ++ B_BLC<4> B_BLC_SEL B_BLT<7> B_BLT<6> B_BLT<5> B_BLT<4> B_BLT_SEL B_PRE_N ++ B_ADDR_DEC<7> B_ADDR_DEC<6> B_ADDR_DEC<5> B_ADDR_DEC<4> B_WR_ONE B_WR_ZERO ++ VDD VSS / RM_IHPSG13_512x8_c3_2P_BLDRV +XAB_BLMUX<0> A_BLC<3> A_BLC<2> A_BLC<1> A_BLC<0> A_BLC_SEL A_BLT<3> A_BLT<2> ++ A_BLT<1> A_BLT<0> A_BLT_SEL A_PRE_N A_ADDR_DEC<3> A_ADDR_DEC<2> ++ A_ADDR_DEC<1> A_ADDR_DEC<0> A_WR_ONE A_WR_ZERO B_BLC<3> B_BLC<2> B_BLC<1> ++ B_BLC<0> B_BLC_SEL B_BLT<3> B_BLT<2> B_BLT<1> B_BLT<0> B_BLT_SEL B_PRE_N ++ B_ADDR_DEC<3> B_ADDR_DEC<2> B_ADDR_DEC<1> B_ADDR_DEC<0> B_WR_ONE B_WR_ZERO ++ VDD VSS / RM_IHPSG13_512x8_c3_2P_BLDRV +XB_I78 B_RCLK_B_L B_SAE VDD VSS / RSC_IHPSG13_CBUFX2 +XA_I78 A_RCLK_B_L A_SAE VDD VSS / RSC_IHPSG13_CBUFX2 +XB_I88 B_DCLK_L B_DCLK_R / RSC_IHPSG13_MET3RES +XB_I87 B_WCLK_L B_WCLK_R / RSC_IHPSG13_MET3RES +XB_R2 B_RCLK_L B_RCLK_R / RSC_IHPSG13_MET3RES +XB_I91 B_RCLK_B_L B_RCLK_B_R / RSC_IHPSG13_MET3RES +XB_I90 B_WCLK_B_L B_WCLK_B_R / RSC_IHPSG13_MET3RES +XB_I89 B_DCLK_B_L B_DCLK_B_R / RSC_IHPSG13_MET3RES +XA_I88 A_DCLK_L A_DCLK_R / RSC_IHPSG13_MET3RES +XA_I87 A_WCLK_L A_WCLK_R / RSC_IHPSG13_MET3RES +XA_R2 A_RCLK_L A_RCLK_R / RSC_IHPSG13_MET3RES +XA_I91 A_RCLK_B_L A_RCLK_B_R / RSC_IHPSG13_MET3RES +XA_I90 A_WCLK_B_L A_WCLK_B_R / RSC_IHPSG13_MET3RES +XA_I89 A_DCLK_B_L A_DCLK_B_R / RSC_IHPSG13_MET3RES +XB_I80 B_WCLK_B_L B_RCLK_B_L net041 VDD VSS / RSC_IHPSG13_AND2X2 +XB_I76 B_DO_WRITE_P B_DI_N B_WR_ZERO VDD VSS / RSC_IHPSG13_AND2X2 +XB_I75 B_DO_WRITE_P B_DI_R B_WR_ONE VDD VSS / RSC_IHPSG13_AND2X2 +XA_I80 A_WCLK_B_L A_RCLK_B_L net21 VDD VSS / RSC_IHPSG13_AND2X2 +XA_I76 A_DI_N A_DO_WRITE_P A_WR_ZERO VDD VSS / RSC_IHPSG13_AND2X2 +XA_I75 A_DI_R A_DO_WRITE_P A_WR_ONE VDD VSS / RSC_IHPSG13_AND2X2 +XB_I81 net041 B_PRE_N VDD VSS / RSC_IHPSG13_CINVX4_WN +XA_I81 net21 A_PRE_N VDD VSS / RSC_IHPSG13_CINVX4_WN +XI_FILL4<10> VDD VSS / RSC_IHPSG13_FILLCAP4 +XI_FILL4<9> VDD VSS / RSC_IHPSG13_FILLCAP4 +XI_FILL4<8> VDD VSS / RSC_IHPSG13_FILLCAP4 +XI_FILL4<7> VDD VSS / RSC_IHPSG13_FILLCAP4 +XI_FILL4<6> VDD VSS / RSC_IHPSG13_FILLCAP4 +XI_FILL4<5> VDD VSS / RSC_IHPSG13_FILLCAP4 +XI_FILL4<4> VDD VSS / RSC_IHPSG13_FILLCAP4 +XI_FILL4<3> VDD VSS / RSC_IHPSG13_FILLCAP4 +XI_FILL4<2> VDD VSS / RSC_IHPSG13_FILLCAP4 +XI_FILL4<1> VDD VSS / RSC_IHPSG13_FILLCAP4 +.ENDS + +.SUBCKT RM_IHPSG13_512x8_c3_2P_ROWDEC6 ADDR_N_I<5> ADDR_N_I<4> ADDR_N_I<3> ADDR_N_I<2> ++ ADDR_N_I<1> ADDR_N_I<0> CS_I ECLK_I WL_O<63> WL_O<62> WL_O<61> WL_O<60> ++ WL_O<59> WL_O<58> WL_O<57> WL_O<56> WL_O<55> WL_O<54> WL_O<53> WL_O<52> ++ WL_O<51> WL_O<50> WL_O<49> WL_O<48> WL_O<47> WL_O<46> WL_O<45> WL_O<44> ++ WL_O<43> WL_O<42> WL_O<41> WL_O<40> WL_O<39> WL_O<38> WL_O<37> WL_O<36> ++ WL_O<35> WL_O<34> WL_O<33> WL_O<32> WL_O<31> WL_O<30> WL_O<29> WL_O<28> ++ WL_O<27> WL_O<26> WL_O<25> WL_O<24> WL_O<23> WL_O<22> WL_O<21> WL_O<20> ++ WL_O<19> WL_O<18> WL_O<17> WL_O<16> WL_O<15> WL_O<14> WL_O<13> WL_O<12> ++ WL_O<11> WL_O<10> WL_O<9> WL_O<8> WL_O<7> WL_O<6> WL_O<5> WL_O<4> WL_O<3> ++ WL_O<2> WL_O<1> WL_O<0> VDD VSS +XDEC10 ADDR_N_I<5> ADDR_N_I<4> CS_I CS00<2> VDD VSS / ++ RM_IHPSG13_512x8_c3_2P_DEC02 +XDEC00 ADDR_N_I<5> ADDR_N_I<4> CS_I CS00<0> VDD VSS / ++ RM_IHPSG13_512x8_c3_2P_DEC00 +XSEL<3> ADDR_N_I<3> ADDR_N_I<2> ADDR_N_I<1> ADDR_N_I<0> CS00<3> ECLK_H<3> ++ ECLK_H<4> ECLK_B<3> ECLK_B<4> WL_O<63> WL_O<62> WL_O<61> WL_O<60> WL_O<59> ++ WL_O<58> WL_O<57> WL_O<56> WL_O<55> WL_O<54> WL_O<53> WL_O<52> WL_O<51> ++ WL_O<50> WL_O<49> WL_O<48> VDD VSS / RM_IHPSG13_512x8_c3_2P_DEC04 +XSEL<2> ADDR_N_I<3> ADDR_N_I<2> ADDR_N_I<1> ADDR_N_I<0> CS00<2> ECLK_H<2> ++ ECLK_H<3> ECLK_B<2> ECLK_B<3> WL_O<47> WL_O<46> WL_O<45> WL_O<44> WL_O<43> ++ WL_O<42> WL_O<41> WL_O<40> WL_O<39> WL_O<38> WL_O<37> WL_O<36> WL_O<35> ++ WL_O<34> WL_O<33> WL_O<32> VDD VSS / RM_IHPSG13_512x8_c3_2P_DEC04 +XSEL<1> ADDR_N_I<3> ADDR_N_I<2> ADDR_N_I<1> ADDR_N_I<0> CS00<1> ECLK_H<1> ++ ECLK_H<2> ECLK_B<1> ECLK_B<2> WL_O<31> WL_O<30> WL_O<29> WL_O<28> WL_O<27> ++ WL_O<26> WL_O<25> WL_O<24> WL_O<23> WL_O<22> WL_O<21> WL_O<20> WL_O<19> ++ WL_O<18> WL_O<17> WL_O<16> VDD VSS / RM_IHPSG13_512x8_c3_2P_DEC04 +XSEL<0> ADDR_N_I<3> ADDR_N_I<2> ADDR_N_I<1> ADDR_N_I<0> CS00<0> ECLK_I ++ ECLK_H<1> ECLK_B<0> ECLK_B<1> WL_O<15> WL_O<14> WL_O<13> WL_O<12> WL_O<11> ++ WL_O<10> WL_O<9> WL_O<8> WL_O<7> WL_O<6> WL_O<5> WL_O<4> WL_O<3> WL_O<2> ++ WL_O<1> WL_O<0> VDD VSS / RM_IHPSG13_512x8_c3_2P_DEC04 +XDEC11 ADDR_N_I<5> ADDR_N_I<4> CS_I CS00<3> VDD VSS / ++ RM_IHPSG13_512x8_c3_2P_DEC03 +XL2<36> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<35> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<34> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<33> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<32> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<31> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<30> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<29> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<28> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<27> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<26> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<25> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<24> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<23> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<22> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<21> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<20> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<19> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<18> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<17> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<16> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<15> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<14> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<13> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<12> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<11> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<10> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<9> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<8> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<7> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<6> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<5> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<4> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<3> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<2> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<1> VDD VSS / RSC_IHPSG13_FILLCAP8 +XDEC01 ADDR_N_I<5> ADDR_N_I<4> CS_I CS00<1> VDD VSS / ++ RM_IHPSG13_512x8_c3_2P_DEC01 +.ENDS +.SUBCKT RM_IHPSG13_512x8_c3_2P_ROWREG6 ACLK_N_I ADDR_I<5> ADDR_I<4> ADDR_I<3> ADDR_I<2> ++ ADDR_I<1> ADDR_I<0> ADDR_N_O<5> ADDR_N_O<4> ADDR_N_O<3> ADDR_N_O<2> ++ ADDR_N_O<1> ADDR_N_O<0> BIST_ADDR_I<5> BIST_ADDR_I<4> BIST_ADDR_I<3> ++ BIST_ADDR_I<2> BIST_ADDR_I<1> BIST_ADDR_I<0> BIST_EN_I VDD VSS +XINV<5> q_int<5> qn_int<5> VDD VSS / RSC_IHPSG13_CINVX2 +XINV<4> q_int<4> qn_int<4> VDD VSS / RSC_IHPSG13_CINVX2 +XINV<3> q_int<3> qn_int<3> VDD VSS / RSC_IHPSG13_CINVX2 +XINV<2> q_int<2> qn_int<2> VDD VSS / RSC_IHPSG13_CINVX2 +XINV<1> q_int<1> qn_int<1> VDD VSS / RSC_IHPSG13_CINVX2 +XINV<0> q_int<0> qn_int<0> VDD VSS / RSC_IHPSG13_CINVX2 +XDRV<5> qn_int<5> ADDR_N_O<5> VDD VSS / RSC_IHPSG13_CINVX8 +XDRV<4> qn_int<4> ADDR_N_O<4> VDD VSS / RSC_IHPSG13_CINVX8 +XDRV<3> qn_int<3> ADDR_N_O<3> VDD VSS / RSC_IHPSG13_CINVX8 +XDRV<2> qn_int<2> ADDR_N_O<2> VDD VSS / RSC_IHPSG13_CINVX8 +XDRV<1> qn_int<1> ADDR_N_O<1> VDD VSS / RSC_IHPSG13_CINVX8 +XDRV<0> qn_int<0> ADDR_N_O<0> VDD VSS / RSC_IHPSG13_CINVX8 +XDFF<5> BIST_EN_I BIST_ADDR_I<5> ACLK_N_I ADDR_I<5> q_int<5> net2<0> VDD ++ VSS / RSC_IHPSG13_DFNQMX2IX1 +XDFF<4> BIST_EN_I BIST_ADDR_I<4> ACLK_N_I ADDR_I<4> q_int<4> net2<1> VDD ++ VSS / RSC_IHPSG13_DFNQMX2IX1 +XDFF<3> BIST_EN_I BIST_ADDR_I<3> ACLK_N_I ADDR_I<3> q_int<3> net2<2> VDD ++ VSS / RSC_IHPSG13_DFNQMX2IX1 +XDFF<2> BIST_EN_I BIST_ADDR_I<2> ACLK_N_I ADDR_I<2> q_int<2> net2<3> VDD ++ VSS / RSC_IHPSG13_DFNQMX2IX1 +XDFF<1> BIST_EN_I BIST_ADDR_I<1> ACLK_N_I ADDR_I<1> q_int<1> net2<4> VDD ++ VSS / RSC_IHPSG13_DFNQMX2IX1 +XDFF<0> BIST_EN_I BIST_ADDR_I<0> ACLK_N_I ADDR_I<0> q_int<0> net2<5> VDD ++ VSS / RSC_IHPSG13_DFNQMX2IX1 +XI11<12> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI11<11> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI11<10> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI11<9> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI11<8> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI11<7> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI11<6> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI11<5> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI11<4> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI11<3> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI11<2> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI11<1> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI12<2> VDD VSS / RSC_IHPSG13_FILLCAP4 +XI12<1> VDD VSS / RSC_IHPSG13_FILLCAP4 +XI12<0> VDD VSS / RSC_IHPSG13_FILLCAP4 +.ENDS + +.SUBCKT RM_IHPSG13_512x8_c3_2P_COLDRV13X16 ADDR_COL_I<1> ADDR_COL_I<0> ADDR_COL_O<1> ++ ADDR_COL_O<0> ADDR_DEC_I<7> ADDR_DEC_I<6> ADDR_DEC_I<5> ADDR_DEC_I<4> ++ ADDR_DEC_I<3> ADDR_DEC_I<2> ADDR_DEC_I<1> ADDR_DEC_I<0> ADDR_DEC_O<7> ++ ADDR_DEC_O<6> ADDR_DEC_O<5> ADDR_DEC_O<4> ADDR_DEC_O<3> ADDR_DEC_O<2> ++ ADDR_DEC_O<1> ADDR_DEC_O<0> DCLK_I DCLK_O RCLK_I RCLK_O WCLK_I WCLK_O ++ VDD VSS +XI0<7> VDD VSS / RSC_IHPSG13_FILLCAP4 +XI0<6> VDD VSS / RSC_IHPSG13_FILLCAP4 +XI0<5> VDD VSS / RSC_IHPSG13_FILLCAP4 +XI0<4> VDD VSS / RSC_IHPSG13_FILLCAP4 +XI0<3> VDD VSS / RSC_IHPSG13_FILLCAP4 +XI0<2> VDD VSS / RSC_IHPSG13_FILLCAP4 +XI0<1> VDD VSS / RSC_IHPSG13_FILLCAP4 +XWCLK_DRV WCLK_I WCLK_O VDD VSS / RSC_IHPSG13_CBUFX16 +XRCLK_DRV RCLK_I RCLK_O VDD VSS / RSC_IHPSG13_CBUFX16 +XDCLK_DRV DCLK_I DCLK_O VDD VSS / RSC_IHPSG13_CBUFX16 +XADDR_COL_DRV<1> ADDR_COL_I<1> ADDR_COL_O<1> VDD VSS / ++ RSC_IHPSG13_CBUFX16 +XADDR_COL_DRV<0> ADDR_COL_I<0> ADDR_COL_O<0> VDD VSS / ++ RSC_IHPSG13_CBUFX16 +XADDR_DEC_DRV<7> ADDR_DEC_I<7> ADDR_DEC_O<7> VDD VSS / ++ RSC_IHPSG13_CBUFX16 +XADDR_DEC_DRV<6> ADDR_DEC_I<6> ADDR_DEC_O<6> VDD VSS / ++ RSC_IHPSG13_CBUFX16 +XADDR_DEC_DRV<5> ADDR_DEC_I<5> ADDR_DEC_O<5> VDD VSS / ++ RSC_IHPSG13_CBUFX16 +XADDR_DEC_DRV<4> ADDR_DEC_I<4> ADDR_DEC_O<4> VDD VSS / ++ RSC_IHPSG13_CBUFX16 +XADDR_DEC_DRV<3> ADDR_DEC_I<3> ADDR_DEC_O<3> VDD VSS / ++ RSC_IHPSG13_CBUFX16 +XADDR_DEC_DRV<2> ADDR_DEC_I<2> ADDR_DEC_O<2> VDD VSS / ++ RSC_IHPSG13_CBUFX16 +XADDR_DEC_DRV<1> ADDR_DEC_I<1> ADDR_DEC_O<1> VDD VSS / ++ RSC_IHPSG13_CBUFX16 +XADDR_DEC_DRV<0> ADDR_DEC_I<0> ADDR_DEC_O<0> VDD VSS / ++ RSC_IHPSG13_CBUFX16 +XI1<5> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI1<4> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI1<3> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI1<2> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI1<1> VDD VSS / RSC_IHPSG13_FILLCAP8 +.ENDS +.SUBCKT RM_IHPSG13_512x8_c3_2P_WLDRV16X16 A<15> A<14> A<13> A<12> A<11> A<10> A<9> A<8> ++ A<7> A<6> A<5> A<4> A<3> A<2> A<1> A<0> Z<15> Z<14> Z<13> Z<12> Z<11> Z<10> ++ Z<9> Z<8> Z<7> Z<6> Z<5> Z<4> Z<3> Z<2> Z<1> Z<0> VDD VSS +XBUF<15> A<15> Z<15> VDD VSS / RSC_IHPSG13_WLDRVX16 +XBUF<14> A<14> Z<14> VDD VSS / RSC_IHPSG13_WLDRVX16 +XBUF<13> A<13> Z<13> VDD VSS / RSC_IHPSG13_WLDRVX16 +XBUF<12> A<12> Z<12> VDD VSS / RSC_IHPSG13_WLDRVX16 +XBUF<11> A<11> Z<11> VDD VSS / RSC_IHPSG13_WLDRVX16 +XBUF<10> A<10> Z<10> VDD VSS / RSC_IHPSG13_WLDRVX16 +XBUF<9> A<9> Z<9> VDD VSS / RSC_IHPSG13_WLDRVX16 +XBUF<8> A<8> Z<8> VDD VSS / RSC_IHPSG13_WLDRVX16 +XBUF<7> A<7> Z<7> VDD VSS / RSC_IHPSG13_WLDRVX16 +XBUF<6> A<6> Z<6> VDD VSS / RSC_IHPSG13_WLDRVX16 +XBUF<5> A<5> Z<5> VDD VSS / RSC_IHPSG13_WLDRVX16 +XBUF<4> A<4> Z<4> VDD VSS / RSC_IHPSG13_WLDRVX16 +XBUF<3> A<3> Z<3> VDD VSS / RSC_IHPSG13_WLDRVX16 +XBUF<2> A<2> Z<2> VDD VSS / RSC_IHPSG13_WLDRVX16 +XBUF<1> A<1> Z<1> VDD VSS / RSC_IHPSG13_WLDRVX16 +XBUF<0> A<0> Z<0> VDD VSS / RSC_IHPSG13_WLDRVX16 +.ENDS + + +.SUBCKT RM_IHPSG13_512x8_c3_1P_DEC01 ADDR<1> ADDR<0> CS CS_OUT VDD VSS +XDECINV net1 CS_OUT VDD VSS / RSC_IHPSG13_INVX4 +XDEC NADDR<1> ADDR<0> CS net1 VDD VSS / RSC_IHPSG13_NAND3X2 +XI2 VDD VSS / RSC_IHPSG13_FILLCAP4 +XADDRINV ADDR<1> NADDR<1> VDD VSS / RSC_IHPSG13_INVX2 +.ENDS +.SUBCKT RM_IHPSG13_512x8_c3_1P_DEC00 ADDR<1> ADDR<0> CS CS_OUT VDD VSS +XDECINV net1 CS_OUT VDD VSS / RSC_IHPSG13_INVX4 +XDEC NADDR<1> NADDR<0> CS net1 VDD VSS / RSC_IHPSG13_NAND3X2 +XADDRINV<1> ADDR<1> NADDR<1> VDD VSS / RSC_IHPSG13_INVX2 +XADDRINV<0> ADDR<0> NADDR<0> VDD VSS / RSC_IHPSG13_INVX2 +XI1 VDD VSS / RSC_IHPSG13_FILLCAP4 +.ENDS +.SUBCKT RM_IHPSG13_512x8_c3_1P_ROWDEC5 ADDR_N_I<4> ADDR_N_I<3> ADDR_N_I<2> ADDR_N_I<1> ++ ADDR_N_I<0> CS_I ECLK_I WL_O<31> WL_O<30> WL_O<29> WL_O<28> WL_O<27> ++ WL_O<26> WL_O<25> WL_O<24> WL_O<23> WL_O<22> WL_O<21> WL_O<20> WL_O<19> ++ WL_O<18> WL_O<17> WL_O<16> WL_O<15> WL_O<14> WL_O<13> WL_O<12> WL_O<11> ++ WL_O<10> WL_O<9> WL_O<8> WL_O<7> WL_O<6> WL_O<5> WL_O<4> WL_O<3> WL_O<2> ++ WL_O<1> WL_O<0> VDD VSS +XL2<12> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<11> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<10> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<9> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<8> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<7> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<6> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<5> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<4> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<3> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<2> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<1> VDD VSS / RSC_IHPSG13_FILLCAP8 +XDEC01 ADDR_N_I<5> ADDR_N_I<4> CS_I CS00<1> VDD VSS / ++ RM_IHPSG13_512x8_c3_1P_DEC01 +XDEC00 ADDR_N_I<5> ADDR_N_I<4> CS_I CS00<0> VDD VSS / ++ RM_IHPSG13_512x8_c3_1P_DEC00 +XSEL<1> ADDR_N_I<3> ADDR_N_I<2> ADDR_N_I<1> ADDR_N_I<0> CS00<1> ECLK_H<1> ++ ECLK_H<2> ECLK_B<1> ECLK_B<2> WL_O<31> WL_O<30> WL_O<29> WL_O<28> WL_O<27> ++ WL_O<26> WL_O<25> WL_O<24> WL_O<23> WL_O<22> WL_O<21> WL_O<20> WL_O<19> ++ WL_O<18> WL_O<17> WL_O<16> VDD VSS / RM_IHPSG13_512x8_c3_1P_DEC04 +XSEL<0> ADDR_N_I<3> ADDR_N_I<2> ADDR_N_I<1> ADDR_N_I<0> CS00<0> ECLK_I ++ ECLK_H<1> ECLK_B<0> ECLK_B<1> WL_O<15> WL_O<14> WL_O<13> WL_O<12> WL_O<11> ++ WL_O<10> WL_O<9> WL_O<8> WL_O<7> WL_O<6> WL_O<5> WL_O<4> WL_O<3> WL_O<2> ++ WL_O<1> WL_O<0> VDD VSS / RM_IHPSG13_512x8_c3_1P_DEC04 +XI0 ADDR_N_I<5> VDD VSS / RSC_IHPSG13_TIEL +.ENDS +.SUBCKT RM_IHPSG13_512x8_c3_1P_ROWREG5 ACLK_N_I ADDR_I<4> ADDR_I<3> ADDR_I<2> ADDR_I<1> ++ ADDR_I<0> ADDR_N_O<4> ADDR_N_O<3> ADDR_N_O<2> ADDR_N_O<1> ADDR_N_O<0> ++ BIST_ADDR_I<4> BIST_ADDR_I<3> BIST_ADDR_I<2> BIST_ADDR_I<1> BIST_ADDR_I<0> ++ BIST_EN_I VDD VSS +XINV<4> q_int<4> qn_int<4> VDD VSS / RSC_IHPSG13_CINVX2 +XINV<3> q_int<3> qn_int<3> VDD VSS / RSC_IHPSG13_CINVX2 +XINV<2> q_int<2> qn_int<2> VDD VSS / RSC_IHPSG13_CINVX2 +XINV<1> q_int<1> qn_int<1> VDD VSS / RSC_IHPSG13_CINVX2 +XINV<0> q_int<0> qn_int<0> VDD VSS / RSC_IHPSG13_CINVX2 +XDRV<4> qn_int<4> ADDR_N_O<4> VDD VSS / RSC_IHPSG13_CINVX8 +XDRV<3> qn_int<3> ADDR_N_O<3> VDD VSS / RSC_IHPSG13_CINVX8 +XDRV<2> qn_int<2> ADDR_N_O<2> VDD VSS / RSC_IHPSG13_CINVX8 +XDRV<1> qn_int<1> ADDR_N_O<1> VDD VSS / RSC_IHPSG13_CINVX8 +XDRV<0> qn_int<0> ADDR_N_O<0> VDD VSS / RSC_IHPSG13_CINVX8 +XDFF<4> BIST_EN_I BIST_ADDR_I<4> ACLK_N_I ADDR_I<4> q_int<4> net2<0> VDD ++ VSS / RSC_IHPSG13_DFNQMX2IX1 +XDFF<3> BIST_EN_I BIST_ADDR_I<3> ACLK_N_I ADDR_I<3> q_int<3> net2<1> VDD ++ VSS / RSC_IHPSG13_DFNQMX2IX1 +XDFF<2> BIST_EN_I BIST_ADDR_I<2> ACLK_N_I ADDR_I<2> q_int<2> net2<2> VDD ++ VSS / RSC_IHPSG13_DFNQMX2IX1 +XDFF<1> BIST_EN_I BIST_ADDR_I<1> ACLK_N_I ADDR_I<1> q_int<1> net2<3> VDD ++ VSS / RSC_IHPSG13_DFNQMX2IX1 +XDFF<0> BIST_EN_I BIST_ADDR_I<0> ACLK_N_I ADDR_I<0> q_int<0> net2<4> VDD ++ VSS / RSC_IHPSG13_DFNQMX2IX1 +XI11<16> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI11<15> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI11<14> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI11<13> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI11<12> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI11<11> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI11<10> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI11<9> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI11<8> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI11<7> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI11<6> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI11<5> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI11<4> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI11<3> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI11<2> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI11<1> VDD VSS / RSC_IHPSG13_FILLCAP8 +.ENDS + + +.SUBCKT RM_IHPSG13_512x8_c3_1P_COLDEC5 ACLK_N ADDR<4> ADDR<3> ADDR<2> ADDR<1> ADDR<0> ++ ADDR_COL<1> ADDR_COL<0> ADDR_DEC<7> ADDR_DEC<6> ADDR_DEC<5> ADDR_DEC<4> ++ ADDR_DEC<3> ADDR_DEC<2> ADDR_DEC<1> ADDR_DEC<0> BIST_ADDR<4> BIST_ADDR<3> ++ BIST_ADDR<2> BIST_ADDR<1> BIST_ADDR<0> BIST_EN_I VDD VSS +XI17<2> VDD VSS / RSC_IHPSG13_FILLCAP4 +XI17<1> VDD VSS / RSC_IHPSG13_FILLCAP4 +XI13<1> addr_int<1> ADDR_COL<1> VDD VSS / RSC_IHPSG13_CBUFX2 +XI13<0> addr_int<0> ADDR_COL<0> VDD VSS / RSC_IHPSG13_CBUFX2 +XDFF<4> BIST_EN_I BIST_ADDR<4> ACLK_N ADDR<4> addr_int<1> net7<0> VDD ++ VSS / RSC_IHPSG13_DFNQMX2IX1 +XDFF<3> BIST_EN_I BIST_ADDR<3> ACLK_N ADDR<3> addr_int<0> net7<1> VDD ++ VSS / RSC_IHPSG13_DFNQMX2IX1 +XDFF<2> BIST_EN_I BIST_ADDR<2> ACLK_N ADDR<2> padr_int<2> net7<2> VDD ++ VSS / RSC_IHPSG13_DFNQMX2IX1 +XDFF<1> BIST_EN_I BIST_ADDR<1> ACLK_N ADDR<1> padr_int<1> net7<3> VDD ++ VSS / RSC_IHPSG13_DFNQMX2IX1 +XDFF<0> BIST_EN_I BIST_ADDR<0> ACLK_N ADDR<0> padr_int<0> net7<4> VDD ++ VSS / RSC_IHPSG13_DFNQMX2IX1 +XI1<7> PADR<0> PADR<1> PADR<2> addr_n<7> VDD VSS / RSC_IHPSG13_NAND3X2 +XI1<6> NADR<0> PADR<1> PADR<2> addr_n<6> VDD VSS / RSC_IHPSG13_NAND3X2 +XI1<5> PADR<0> NADR<1> PADR<2> addr_n<5> VDD VSS / RSC_IHPSG13_NAND3X2 +XI1<4> NADR<0> NADR<1> PADR<2> addr_n<4> VDD VSS / RSC_IHPSG13_NAND3X2 +XI1<3> PADR<0> PADR<1> NADR<2> addr_n<3> VDD VSS / RSC_IHPSG13_NAND3X2 +XI1<2> NADR<0> PADR<1> NADR<2> addr_n<2> VDD VSS / RSC_IHPSG13_NAND3X2 +XI1<1> PADR<0> NADR<1> NADR<2> addr_n<1> VDD VSS / RSC_IHPSG13_NAND3X2 +XI1<0> NADR<0> NADR<1> NADR<2> addr_n<0> VDD VSS / RSC_IHPSG13_NAND3X2 +XI15<2> NADR<2> PADR<2> VDD VSS / RSC_IHPSG13_INVX2 +XI15<1> NADR<1> PADR<1> VDD VSS / RSC_IHPSG13_INVX2 +XI15<0> NADR<0> PADR<0> VDD VSS / RSC_IHPSG13_INVX2 +XI3<2> padr_int<2> NADR<2> VDD VSS / RSC_IHPSG13_INVX2 +XI3<1> padr_int<1> NADR<1> VDD VSS / RSC_IHPSG13_INVX2 +XI3<0> padr_int<0> NADR<0> VDD VSS / RSC_IHPSG13_INVX2 +XI2<7> addr_n<7> ADDR_DEC<7> VDD VSS / RSC_IHPSG13_INVX2 +XI2<6> addr_n<6> ADDR_DEC<6> VDD VSS / RSC_IHPSG13_INVX2 +XI2<5> addr_n<5> ADDR_DEC<5> VDD VSS / RSC_IHPSG13_INVX2 +XI2<4> addr_n<4> ADDR_DEC<4> VDD VSS / RSC_IHPSG13_INVX2 +XI2<3> addr_n<3> ADDR_DEC<3> VDD VSS / RSC_IHPSG13_INVX2 +XI2<2> addr_n<2> ADDR_DEC<2> VDD VSS / RSC_IHPSG13_INVX2 +XI2<1> addr_n<1> ADDR_DEC<1> VDD VSS / RSC_IHPSG13_INVX2 +XI2<0> addr_n<0> ADDR_DEC<0> VDD VSS / RSC_IHPSG13_INVX2 +.ENDS +.SUBCKT RM_IHPSG13_512x8_c3_1P_COLCTRL5 A_ADDR_COL<1> A_ADDR_COL<0> A_ADDR_DEC<7> ++ A_ADDR_DEC<6> A_ADDR_DEC<5> A_ADDR_DEC<4> A_ADDR_DEC<3> A_ADDR_DEC<2> ++ A_ADDR_DEC<1> A_ADDR_DEC<0> A_BIST_BM_I A_BIST_DW_I A_BIST_EN_I A_BLC<31> ++ A_BLC<30> A_BLC<29> A_BLC<28> A_BLC<27> A_BLC<26> A_BLC<25> A_BLC<24> ++ A_BLC<23> A_BLC<22> A_BLC<21> A_BLC<20> A_BLC<19> A_BLC<18> A_BLC<17> ++ A_BLC<16> A_BLC<15> A_BLC<14> A_BLC<13> A_BLC<12> A_BLC<11> A_BLC<10> ++ A_BLC<9> A_BLC<8> A_BLC<7> A_BLC<6> A_BLC<5> A_BLC<4> A_BLC<3> A_BLC<2> ++ A_BLC<1> A_BLC<0> A_BLT<31> A_BLT<30> A_BLT<29> A_BLT<28> A_BLT<27> ++ A_BLT<26> A_BLT<25> A_BLT<24> A_BLT<23> A_BLT<22> A_BLT<21> A_BLT<20> ++ A_BLT<19> A_BLT<18> A_BLT<17> A_BLT<16> A_BLT<15> A_BLT<14> A_BLT<13> ++ A_BLT<12> A_BLT<11> A_BLT<10> A_BLT<9> A_BLT<8> A_BLT<7> A_BLT<6> A_BLT<5> ++ A_BLT<4> A_BLT<3> A_BLT<2> A_BLT<1> A_BLT<0> A_BM_I A_DCLK_B_L A_DCLK_B_R ++ A_DCLK_L A_DCLK_R A_DR_O A_DW_I A_RCLK_B_L A_RCLK_B_R A_RCLK_L A_RCLK_R ++ A_TIEH_O A_WCLK_B_L A_WCLK_B_R A_WCLK_L A_WCLK_R VDD VSS +XA_I80<1> A_WCLK_B_L A_RCLK_B_L A_W_nor_R<1> VDD VSS / ++ RSC_IHPSG13_AND2X2 +XA_I80<0> A_WCLK_B_L A_RCLK_B_L A_W_nor_R<0> VDD VSS / ++ RSC_IHPSG13_AND2X2 +XA_I44 A_BM_N A_WCLK_B_L A_DO_WRITE_P VDD VSS / RSC_IHPSG13_NOR2X2 +XI80<29> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI80<28> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI80<27> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI80<26> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI80<25> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI80<24> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI80<23> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI80<22> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI80<21> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI80<20> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI80<19> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI80<18> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI80<17> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI80<16> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI80<15> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI80<14> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI80<13> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI80<12> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI80<11> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI80<10> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI80<9> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI80<8> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI80<7> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI80<6> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI80<5> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI80<4> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI80<3> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI80<2> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI80<1> VDD VSS / RSC_IHPSG13_FILLCAP8 +XA_I74<16> VDD VSS / RSC_IHPSG13_FILLCAP8 +XA_I74<15> VDD VSS / RSC_IHPSG13_FILLCAP8 +XA_I74<14> VDD VSS / RSC_IHPSG13_FILLCAP8 +XA_I74<13> VDD VSS / RSC_IHPSG13_FILLCAP8 +XA_I74<12> VDD VSS / RSC_IHPSG13_FILLCAP8 +XA_I74<11> VDD VSS / RSC_IHPSG13_FILLCAP8 +XA_I74<10> VDD VSS / RSC_IHPSG13_FILLCAP8 +XA_I74<9> VDD VSS / RSC_IHPSG13_FILLCAP8 +XA_I74<8> VDD VSS / RSC_IHPSG13_FILLCAP8 +XA_I74<7> VDD VSS / RSC_IHPSG13_FILLCAP8 +XA_I74<6> VDD VSS / RSC_IHPSG13_FILLCAP8 +XA_I74<5> VDD VSS / RSC_IHPSG13_FILLCAP8 +XA_I74<4> VDD VSS / RSC_IHPSG13_FILLCAP8 +XA_I74<3> VDD VSS / RSC_IHPSG13_FILLCAP8 +XA_I74<2> VDD VSS / RSC_IHPSG13_FILLCAP8 +XA_I74<1> VDD VSS / RSC_IHPSG13_FILLCAP8 +XA_INV<6> A_N1<1> A_P1<1> VDD VSS / RSC_IHPSG13_CINVX4 +XA_INV<5> A_N0<1> A_P0<1> VDD VSS / RSC_IHPSG13_CINVX4 +XA_INV<4> A_N0<0> A_P0<0> VDD VSS / RSC_IHPSG13_CINVX4 +XA_INV<3> A_ADDR_COL<1> A_N1<1> VDD VSS / RSC_IHPSG13_CINVX4 +XA_INV<2> A_ADDR_COL<1> A_N1<0> VDD VSS / RSC_IHPSG13_CINVX4 +XA_INV<1> A_ADDR_COL<0> A_N0<1> VDD VSS / RSC_IHPSG13_CINVX4 +XA_INV<0> A_ADDR_COL<0> A_N0<0> VDD VSS / RSC_IHPSG13_CINVX4 +XA_I81<3> A_W_nor_R<1> A_PRE_N VDD VSS / RSC_IHPSG13_CINVX4_WN +XA_I81<2> A_W_nor_R<1> A_PRE_N VDD VSS / RSC_IHPSG13_CINVX4_WN +XA_I81<1> A_W_nor_R<0> A_PRE_N VDD VSS / RSC_IHPSG13_CINVX4_WN +XA_I81<0> A_W_nor_R<0> A_PRE_N VDD VSS / RSC_IHPSG13_CINVX4_WN +XA_BLTMUX<31> A_BLC<31> A_BLC_SEL A_BLT<31> A_BLT_SEL A_PRE_N A_SEL_P<31> ++ A_WR_ONE A_WR_ZERO VDD VSS / RM_IHPSG13_512x8_c3_1P_BLDRV +XA_BLTMUX<30> A_BLC<30> A_BLC_SEL A_BLT<30> A_BLT_SEL A_PRE_N A_SEL_P<30> ++ A_WR_ONE A_WR_ZERO VDD VSS / RM_IHPSG13_512x8_c3_1P_BLDRV +XA_BLTMUX<29> A_BLC<29> A_BLC_SEL A_BLT<29> A_BLT_SEL A_PRE_N A_SEL_P<29> ++ A_WR_ONE A_WR_ZERO VDD VSS / RM_IHPSG13_512x8_c3_1P_BLDRV +XA_BLTMUX<28> A_BLC<28> A_BLC_SEL A_BLT<28> A_BLT_SEL A_PRE_N A_SEL_P<28> ++ A_WR_ONE A_WR_ZERO VDD VSS / RM_IHPSG13_512x8_c3_1P_BLDRV +XA_BLTMUX<27> A_BLC<27> A_BLC_SEL A_BLT<27> A_BLT_SEL A_PRE_N A_SEL_P<27> ++ A_WR_ONE A_WR_ZERO VDD VSS / RM_IHPSG13_512x8_c3_1P_BLDRV +XA_BLTMUX<26> A_BLC<26> A_BLC_SEL A_BLT<26> A_BLT_SEL A_PRE_N A_SEL_P<26> ++ A_WR_ONE A_WR_ZERO VDD VSS / RM_IHPSG13_512x8_c3_1P_BLDRV +XA_BLTMUX<25> A_BLC<25> A_BLC_SEL A_BLT<25> A_BLT_SEL A_PRE_N A_SEL_P<25> ++ A_WR_ONE A_WR_ZERO VDD VSS / RM_IHPSG13_512x8_c3_1P_BLDRV +XA_BLTMUX<24> A_BLC<24> A_BLC_SEL A_BLT<24> A_BLT_SEL A_PRE_N A_SEL_P<24> ++ A_WR_ONE A_WR_ZERO VDD VSS / RM_IHPSG13_512x8_c3_1P_BLDRV +XA_BLTMUX<23> A_BLC<23> A_BLC_SEL A_BLT<23> A_BLT_SEL A_PRE_N A_SEL_P<23> ++ A_WR_ONE A_WR_ZERO VDD VSS / RM_IHPSG13_512x8_c3_1P_BLDRV +XA_BLTMUX<22> A_BLC<22> A_BLC_SEL A_BLT<22> A_BLT_SEL A_PRE_N A_SEL_P<22> ++ A_WR_ONE A_WR_ZERO VDD VSS / RM_IHPSG13_512x8_c3_1P_BLDRV +XA_BLTMUX<21> A_BLC<21> A_BLC_SEL A_BLT<21> A_BLT_SEL A_PRE_N A_SEL_P<21> ++ A_WR_ONE A_WR_ZERO VDD VSS / RM_IHPSG13_512x8_c3_1P_BLDRV +XA_BLTMUX<20> A_BLC<20> A_BLC_SEL A_BLT<20> A_BLT_SEL A_PRE_N A_SEL_P<20> ++ A_WR_ONE A_WR_ZERO VDD VSS / RM_IHPSG13_512x8_c3_1P_BLDRV +XA_BLTMUX<19> A_BLC<19> A_BLC_SEL A_BLT<19> A_BLT_SEL A_PRE_N A_SEL_P<19> ++ A_WR_ONE A_WR_ZERO VDD VSS / RM_IHPSG13_512x8_c3_1P_BLDRV +XA_BLTMUX<18> A_BLC<18> A_BLC_SEL A_BLT<18> A_BLT_SEL A_PRE_N A_SEL_P<18> ++ A_WR_ONE A_WR_ZERO VDD VSS / RM_IHPSG13_512x8_c3_1P_BLDRV +XA_BLTMUX<17> A_BLC<17> A_BLC_SEL A_BLT<17> A_BLT_SEL A_PRE_N A_SEL_P<17> ++ A_WR_ONE A_WR_ZERO VDD VSS / RM_IHPSG13_512x8_c3_1P_BLDRV +XA_BLTMUX<16> A_BLC<16> A_BLC_SEL A_BLT<16> A_BLT_SEL A_PRE_N A_SEL_P<16> ++ A_WR_ONE A_WR_ZERO VDD VSS / RM_IHPSG13_512x8_c3_1P_BLDRV +XA_BLTMUX<15> A_BLC<15> A_BLC_SEL A_BLT<15> A_BLT_SEL A_PRE_N A_SEL_P<15> ++ A_WR_ONE A_WR_ZERO VDD VSS / RM_IHPSG13_512x8_c3_1P_BLDRV +XA_BLTMUX<14> A_BLC<14> A_BLC_SEL A_BLT<14> A_BLT_SEL A_PRE_N A_SEL_P<14> ++ A_WR_ONE A_WR_ZERO VDD VSS / RM_IHPSG13_512x8_c3_1P_BLDRV +XA_BLTMUX<13> A_BLC<13> A_BLC_SEL A_BLT<13> A_BLT_SEL A_PRE_N A_SEL_P<13> ++ A_WR_ONE A_WR_ZERO VDD VSS / RM_IHPSG13_512x8_c3_1P_BLDRV +XA_BLTMUX<12> A_BLC<12> A_BLC_SEL A_BLT<12> A_BLT_SEL A_PRE_N A_SEL_P<12> ++ A_WR_ONE A_WR_ZERO VDD VSS / RM_IHPSG13_512x8_c3_1P_BLDRV +XA_BLTMUX<11> A_BLC<11> A_BLC_SEL A_BLT<11> A_BLT_SEL A_PRE_N A_SEL_P<11> ++ A_WR_ONE A_WR_ZERO VDD VSS / RM_IHPSG13_512x8_c3_1P_BLDRV +XA_BLTMUX<10> A_BLC<10> A_BLC_SEL A_BLT<10> A_BLT_SEL A_PRE_N A_SEL_P<10> ++ A_WR_ONE A_WR_ZERO VDD VSS / RM_IHPSG13_512x8_c3_1P_BLDRV +XA_BLTMUX<9> A_BLC<9> A_BLC_SEL A_BLT<9> A_BLT_SEL A_PRE_N A_SEL_P<9> A_WR_ONE ++ A_WR_ZERO VDD VSS / RM_IHPSG13_512x8_c3_1P_BLDRV +XA_BLTMUX<8> A_BLC<8> A_BLC_SEL A_BLT<8> A_BLT_SEL A_PRE_N A_SEL_P<8> A_WR_ONE ++ A_WR_ZERO VDD VSS / RM_IHPSG13_512x8_c3_1P_BLDRV +XA_BLTMUX<7> A_BLC<7> A_BLC_SEL A_BLT<7> A_BLT_SEL A_PRE_N A_SEL_P<7> A_WR_ONE ++ A_WR_ZERO VDD VSS / RM_IHPSG13_512x8_c3_1P_BLDRV +XA_BLTMUX<6> A_BLC<6> A_BLC_SEL A_BLT<6> A_BLT_SEL A_PRE_N A_SEL_P<6> A_WR_ONE ++ A_WR_ZERO VDD VSS / RM_IHPSG13_512x8_c3_1P_BLDRV +XA_BLTMUX<5> A_BLC<5> A_BLC_SEL A_BLT<5> A_BLT_SEL A_PRE_N A_SEL_P<5> A_WR_ONE ++ A_WR_ZERO VDD VSS / RM_IHPSG13_512x8_c3_1P_BLDRV +XA_BLTMUX<4> A_BLC<4> A_BLC_SEL A_BLT<4> A_BLT_SEL A_PRE_N A_SEL_P<4> A_WR_ONE ++ A_WR_ZERO VDD VSS / RM_IHPSG13_512x8_c3_1P_BLDRV +XA_BLTMUX<3> A_BLC<3> A_BLC_SEL A_BLT<3> A_BLT_SEL A_PRE_N A_SEL_P<3> A_WR_ONE ++ A_WR_ZERO VDD VSS / RM_IHPSG13_512x8_c3_1P_BLDRV +XA_BLTMUX<2> A_BLC<2> A_BLC_SEL A_BLT<2> A_BLT_SEL A_PRE_N A_SEL_P<2> A_WR_ONE ++ A_WR_ZERO VDD VSS / RM_IHPSG13_512x8_c3_1P_BLDRV +XA_BLTMUX<1> A_BLC<1> A_BLC_SEL A_BLT<1> A_BLT_SEL A_PRE_N A_SEL_P<1> A_WR_ONE ++ A_WR_ZERO VDD VSS / RM_IHPSG13_512x8_c3_1P_BLDRV +XA_BLTMUX<0> A_BLC<0> A_BLC_SEL A_BLT<0> A_BLT_SEL A_PRE_N A_SEL_P<0> A_WR_ONE ++ A_WR_ZERO VDD VSS / RM_IHPSG13_512x8_c3_1P_BLDRV +XA_CAPS<17> VDD VSS / RSC_IHPSG13_FILLCAP4 +XA_CAPS<16> VDD VSS / RSC_IHPSG13_FILLCAP4 +XA_CAPS<15> VDD VSS / RSC_IHPSG13_FILLCAP4 +XA_CAPS<14> VDD VSS / RSC_IHPSG13_FILLCAP4 +XA_CAPS<13> VDD VSS / RSC_IHPSG13_FILLCAP4 +XA_CAPS<12> VDD VSS / RSC_IHPSG13_FILLCAP4 +XA_CAPS<11> VDD VSS / RSC_IHPSG13_FILLCAP4 +XA_CAPS<10> VDD VSS / RSC_IHPSG13_FILLCAP4 +XA_CAPS<9> VDD VSS / RSC_IHPSG13_FILLCAP4 +XA_CAPS<8> VDD VSS / RSC_IHPSG13_FILLCAP4 +XA_CAPS<7> VDD VSS / RSC_IHPSG13_FILLCAP4 +XA_CAPS<6> VDD VSS / RSC_IHPSG13_FILLCAP4 +XA_CAPS<5> VDD VSS / RSC_IHPSG13_FILLCAP4 +XA_CAPS<4> VDD VSS / RSC_IHPSG13_FILLCAP4 +XA_CAPS<3> VDD VSS / RSC_IHPSG13_FILLCAP4 +XA_CAPS<2> VDD VSS / RSC_IHPSG13_FILLCAP4 +XA_CAPS<1> VDD VSS / RSC_IHPSG13_FILLCAP4 +XA_I51 net19 A_DR_O VDD VSS / RSC_IHPSG13_INVX4 +XA_I78 A_RCLK_B_L A_SAE VDD VSS / RSC_IHPSG13_CBUFX2 +XA_I69 A_DCLK_L A_DCLK_B_L VDD VSS / RSC_IHPSG13_CINVX8 +XA_I50 A_WCLK_L A_WCLK_B_L VDD VSS / RSC_IHPSG13_CINVX8 +XA_EBUF A_RCLK_L A_RCLK_B_L VDD VSS / RSC_IHPSG13_CINVX8 +XA_I76 A_DI_N A_DO_WRITE_P A_WR_ZERO VDD VSS / RSC_IHPSG13_AND2X6 +XA_I75 A_DI_R A_DO_WRITE_P A_WR_ONE VDD VSS / RSC_IHPSG13_AND2X6 +XA_I83 A_BM_R A_BM_N VDD VSS / RSC_IHPSG13_INVX2 +XA_DEC3INV<31> net23<0> A_SEL_P<31> VDD VSS / RSC_IHPSG13_INVX2 +XA_DEC3INV<30> net23<1> A_SEL_P<30> VDD VSS / RSC_IHPSG13_INVX2 +XA_DEC3INV<29> net23<2> A_SEL_P<29> VDD VSS / RSC_IHPSG13_INVX2 +XA_DEC3INV<28> net23<3> A_SEL_P<28> VDD VSS / RSC_IHPSG13_INVX2 +XA_DEC3INV<27> net23<4> A_SEL_P<27> VDD VSS / RSC_IHPSG13_INVX2 +XA_DEC3INV<26> net23<5> A_SEL_P<26> VDD VSS / RSC_IHPSG13_INVX2 +XA_DEC3INV<25> net23<6> A_SEL_P<25> VDD VSS / RSC_IHPSG13_INVX2 +XA_DEC3INV<24> net23<7> A_SEL_P<24> VDD VSS / RSC_IHPSG13_INVX2 +XA_DEC3INV<23> net23<8> A_SEL_P<23> VDD VSS / RSC_IHPSG13_INVX2 +XA_DEC3INV<22> net23<9> A_SEL_P<22> VDD VSS / RSC_IHPSG13_INVX2 +XA_DEC3INV<21> net23<10> A_SEL_P<21> VDD VSS / RSC_IHPSG13_INVX2 +XA_DEC3INV<20> net23<11> A_SEL_P<20> VDD VSS / RSC_IHPSG13_INVX2 +XA_DEC3INV<19> net23<12> A_SEL_P<19> VDD VSS / RSC_IHPSG13_INVX2 +XA_DEC3INV<18> net23<13> A_SEL_P<18> VDD VSS / RSC_IHPSG13_INVX2 +XA_DEC3INV<17> net23<14> A_SEL_P<17> VDD VSS / RSC_IHPSG13_INVX2 +XA_DEC3INV<16> net23<15> A_SEL_P<16> VDD VSS / RSC_IHPSG13_INVX2 +XA_DEC3INV<15> net23<16> A_SEL_P<15> VDD VSS / RSC_IHPSG13_INVX2 +XA_DEC3INV<14> net23<17> A_SEL_P<14> VDD VSS / RSC_IHPSG13_INVX2 +XA_DEC3INV<13> net23<18> A_SEL_P<13> VDD VSS / RSC_IHPSG13_INVX2 +XA_DEC3INV<12> net23<19> A_SEL_P<12> VDD VSS / RSC_IHPSG13_INVX2 +XA_DEC3INV<11> net23<20> A_SEL_P<11> VDD VSS / RSC_IHPSG13_INVX2 +XA_DEC3INV<10> net23<21> A_SEL_P<10> VDD VSS / RSC_IHPSG13_INVX2 +XA_DEC3INV<9> net23<22> A_SEL_P<9> VDD VSS / RSC_IHPSG13_INVX2 +XA_DEC3INV<8> net23<23> A_SEL_P<8> VDD VSS / RSC_IHPSG13_INVX2 +XA_DEC3INV<7> net23<24> A_SEL_P<7> VDD VSS / RSC_IHPSG13_INVX2 +XA_DEC3INV<6> net23<25> A_SEL_P<6> VDD VSS / RSC_IHPSG13_INVX2 +XA_DEC3INV<5> net23<26> A_SEL_P<5> VDD VSS / RSC_IHPSG13_INVX2 +XA_DEC3INV<4> net23<27> A_SEL_P<4> VDD VSS / RSC_IHPSG13_INVX2 +XA_DEC3INV<3> net23<28> A_SEL_P<3> VDD VSS / RSC_IHPSG13_INVX2 +XA_DEC3INV<2> net23<29> A_SEL_P<2> VDD VSS / RSC_IHPSG13_INVX2 +XA_DEC3INV<1> net23<30> A_SEL_P<1> VDD VSS / RSC_IHPSG13_INVX2 +XA_DEC3INV<0> net23<31> A_SEL_P<0> VDD VSS / RSC_IHPSG13_INVX2 +XA_I49 A_DI_R A_DI_N VDD VSS / RSC_IHPSG13_INVX2 +XA_ISENSE A_SAE A_BLC_SEL A_BLT_SEL net19 net20 VDD VSS / ++ RSC_IHPSG13_DFPQD_MSAFFX2 +XA_DREG A_BIST_EN_I A_BIST_DW_I A_DCLK_B_L A_DW_I A_DI_R net22 VDD VSS ++ / RSC_IHPSG13_DFNQMX2IX1 +XA_BREG A_BIST_EN_I A_BIST_BM_I A_DCLK_B_L A_BM_I A_BM_R net21 VDD VSS ++ / RSC_IHPSG13_DFNQMX2IX1 +XA_DEC3<31> A_P1<1> A_P0<1> A_ADDR_DEC<7> net23<0> VDD VSS / ++ RSC_IHPSG13_NAND3X2 +XA_DEC3<30> A_P1<1> A_P0<1> A_ADDR_DEC<6> net23<1> VDD VSS / ++ RSC_IHPSG13_NAND3X2 +XA_DEC3<29> A_P1<1> A_P0<1> A_ADDR_DEC<5> net23<2> VDD VSS / ++ RSC_IHPSG13_NAND3X2 +XA_DEC3<28> A_P1<1> A_P0<1> A_ADDR_DEC<4> net23<3> VDD VSS / ++ RSC_IHPSG13_NAND3X2 +XA_DEC3<27> A_P1<1> A_P0<1> A_ADDR_DEC<3> net23<4> VDD VSS / ++ RSC_IHPSG13_NAND3X2 +XA_DEC3<26> A_P1<1> A_P0<1> A_ADDR_DEC<2> net23<5> VDD VSS / ++ RSC_IHPSG13_NAND3X2 +XA_DEC3<25> A_P1<1> A_P0<1> A_ADDR_DEC<1> net23<6> VDD VSS / ++ RSC_IHPSG13_NAND3X2 +XA_DEC3<24> A_P1<1> A_P0<1> A_ADDR_DEC<0> net23<7> VDD VSS / ++ RSC_IHPSG13_NAND3X2 +XA_DEC3<23> A_P1<1> A_N0<1> A_ADDR_DEC<7> net23<8> VDD VSS / ++ RSC_IHPSG13_NAND3X2 +XA_DEC3<22> A_P1<1> A_N0<1> A_ADDR_DEC<6> net23<9> VDD VSS / ++ RSC_IHPSG13_NAND3X2 +XA_DEC3<21> A_P1<1> A_N0<1> A_ADDR_DEC<5> net23<10> VDD VSS / ++ RSC_IHPSG13_NAND3X2 +XA_DEC3<20> A_P1<1> A_N0<1> A_ADDR_DEC<4> net23<11> VDD VSS / ++ RSC_IHPSG13_NAND3X2 +XA_DEC3<19> A_P1<1> A_N0<1> A_ADDR_DEC<3> net23<12> VDD VSS / ++ RSC_IHPSG13_NAND3X2 +XA_DEC3<18> A_P1<1> A_N0<1> A_ADDR_DEC<2> net23<13> VDD VSS / ++ RSC_IHPSG13_NAND3X2 +XA_DEC3<17> A_P1<1> A_N0<1> A_ADDR_DEC<1> net23<14> VDD VSS / ++ RSC_IHPSG13_NAND3X2 +XA_DEC3<16> A_P1<1> A_N0<1> A_ADDR_DEC<0> net23<15> VDD VSS / ++ RSC_IHPSG13_NAND3X2 +XA_DEC3<15> A_N1<0> A_P0<0> A_ADDR_DEC<7> net23<16> VDD VSS / ++ RSC_IHPSG13_NAND3X2 +XA_DEC3<14> A_N1<0> A_P0<0> A_ADDR_DEC<6> net23<17> VDD VSS / ++ RSC_IHPSG13_NAND3X2 +XA_DEC3<13> A_N1<0> A_P0<0> A_ADDR_DEC<5> net23<18> VDD VSS / ++ RSC_IHPSG13_NAND3X2 +XA_DEC3<12> A_N1<0> A_P0<0> A_ADDR_DEC<4> net23<19> VDD VSS / ++ RSC_IHPSG13_NAND3X2 +XA_DEC3<11> A_N1<0> A_P0<0> A_ADDR_DEC<3> net23<20> VDD VSS / ++ RSC_IHPSG13_NAND3X2 +XA_DEC3<10> A_N1<0> A_P0<0> A_ADDR_DEC<2> net23<21> VDD VSS / ++ RSC_IHPSG13_NAND3X2 +XA_DEC3<9> A_N1<0> A_P0<0> A_ADDR_DEC<1> net23<22> VDD VSS / ++ RSC_IHPSG13_NAND3X2 +XA_DEC3<8> A_N1<0> A_P0<0> A_ADDR_DEC<0> net23<23> VDD VSS / ++ RSC_IHPSG13_NAND3X2 +XA_DEC3<7> A_N1<0> A_N0<0> A_ADDR_DEC<7> net23<24> VDD VSS / ++ RSC_IHPSG13_NAND3X2 +XA_DEC3<6> A_N1<0> A_N0<0> A_ADDR_DEC<6> net23<25> VDD VSS / ++ RSC_IHPSG13_NAND3X2 +XA_DEC3<5> A_N1<0> A_N0<0> A_ADDR_DEC<5> net23<26> VDD VSS / ++ RSC_IHPSG13_NAND3X2 +XA_DEC3<4> A_N1<0> A_N0<0> A_ADDR_DEC<4> net23<27> VDD VSS / ++ RSC_IHPSG13_NAND3X2 +XA_DEC3<3> A_N1<0> A_N0<0> A_ADDR_DEC<3> net23<28> VDD VSS / ++ RSC_IHPSG13_NAND3X2 +XA_DEC3<2> A_N1<0> A_N0<0> A_ADDR_DEC<2> net23<29> VDD VSS / ++ RSC_IHPSG13_NAND3X2 +XA_DEC3<1> A_N1<0> A_N0<0> A_ADDR_DEC<1> net23<30> VDD VSS / ++ RSC_IHPSG13_NAND3X2 +XA_DEC3<0> A_N1<0> A_N0<0> A_ADDR_DEC<0> net23<31> VDD VSS / ++ RSC_IHPSG13_NAND3X2 +XA_I89 A_DCLK_B_L A_DCLK_B_R / RSC_IHPSG13_MET3RES +XA_I91 A_RCLK_B_L A_RCLK_B_R / RSC_IHPSG13_MET3RES +XA_I90 A_WCLK_B_L A_WCLK_B_R / RSC_IHPSG13_MET3RES +XA_I88 A_DCLK_L A_DCLK_R / RSC_IHPSG13_MET3RES +XA_I87 A_WCLK_L A_WCLK_R / RSC_IHPSG13_MET3RES +XA_R2 A_RCLK_L A_RCLK_R / RSC_IHPSG13_MET3RES +XA_BM_TIEH A_TIEH_O VDD VSS / RSC_IHPSG13_TIEH +.ENDS + +.SUBCKT RM_IHPSG13_512x8_c3_1P_COLDRV13X12 ADDR_COL_I<1> ADDR_COL_I<0> ADDR_COL_O<1> ++ ADDR_COL_O<0> ADDR_DEC_I<7> ADDR_DEC_I<6> ADDR_DEC_I<5> ADDR_DEC_I<4> ++ ADDR_DEC_I<3> ADDR_DEC_I<2> ADDR_DEC_I<1> ADDR_DEC_I<0> ADDR_DEC_O<7> ++ ADDR_DEC_O<6> ADDR_DEC_O<5> ADDR_DEC_O<4> ADDR_DEC_O<3> ADDR_DEC_O<2> ++ ADDR_DEC_O<1> ADDR_DEC_O<0> DCLK_I DCLK_O RCLK_I RCLK_O WCLK_I WCLK_O ++ VDD VSS +XI1<1> VDD VSS / RSC_IHPSG13_FILLCAP4 +XI1<0> VDD VSS / RSC_IHPSG13_FILLCAP4 +XI0<1> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI0<0> VDD VSS / RSC_IHPSG13_FILLCAP8 +XADDR_COL_DRV<1> ADDR_COL_I<1> ADDR_COL_O<1> VDD VSS / ++ RSC_IHPSG13_CBUFX12 +XADDR_COL_DRV<0> ADDR_COL_I<0> ADDR_COL_O<0> VDD VSS / ++ RSC_IHPSG13_CBUFX12 +XADDR_DEC_DRV<7> ADDR_DEC_I<7> ADDR_DEC_O<7> VDD VSS / ++ RSC_IHPSG13_CBUFX12 +XADDR_DEC_DRV<6> ADDR_DEC_I<6> ADDR_DEC_O<6> VDD VSS / ++ RSC_IHPSG13_CBUFX12 +XADDR_DEC_DRV<5> ADDR_DEC_I<5> ADDR_DEC_O<5> VDD VSS / ++ RSC_IHPSG13_CBUFX12 +XADDR_DEC_DRV<4> ADDR_DEC_I<4> ADDR_DEC_O<4> VDD VSS / ++ RSC_IHPSG13_CBUFX12 +XADDR_DEC_DRV<3> ADDR_DEC_I<3> ADDR_DEC_O<3> VDD VSS / ++ RSC_IHPSG13_CBUFX12 +XADDR_DEC_DRV<2> ADDR_DEC_I<2> ADDR_DEC_O<2> VDD VSS / ++ RSC_IHPSG13_CBUFX12 +XADDR_DEC_DRV<1> ADDR_DEC_I<1> ADDR_DEC_O<1> VDD VSS / ++ RSC_IHPSG13_CBUFX12 +XADDR_DEC_DRV<0> ADDR_DEC_I<0> ADDR_DEC_O<0> VDD VSS / ++ RSC_IHPSG13_CBUFX12 +XDCLK_DRV DCLK_I DCLK_O VDD VSS / RSC_IHPSG13_CBUFX12 +XRCLK_DRV RCLK_I RCLK_O VDD VSS / RSC_IHPSG13_CBUFX12 +XWCLK_DRV WCLK_I WCLK_O VDD VSS / RSC_IHPSG13_CBUFX12 +.ENDS +.SUBCKT RM_IHPSG13_512x8_c3_1P_WLDRV16X12 A<15> A<14> A<13> A<12> A<11> A<10> A<9> A<8> ++ A<7> A<6> A<5> A<4> A<3> A<2> A<1> A<0> Z<15> Z<14> Z<13> Z<12> Z<11> Z<10> ++ Z<9> Z<8> Z<7> Z<6> Z<5> Z<4> Z<3> Z<2> Z<1> Z<0> VDD VSS +XBUF<15> A<15> Z<15> VDD VSS / RSC_IHPSG13_WLDRVX12 +XBUF<14> A<14> Z<14> VDD VSS / RSC_IHPSG13_WLDRVX12 +XBUF<13> A<13> Z<13> VDD VSS / RSC_IHPSG13_WLDRVX12 +XBUF<12> A<12> Z<12> VDD VSS / RSC_IHPSG13_WLDRVX12 +XBUF<11> A<11> Z<11> VDD VSS / RSC_IHPSG13_WLDRVX12 +XBUF<10> A<10> Z<10> VDD VSS / RSC_IHPSG13_WLDRVX12 +XBUF<9> A<9> Z<9> VDD VSS / RSC_IHPSG13_WLDRVX12 +XBUF<8> A<8> Z<8> VDD VSS / RSC_IHPSG13_WLDRVX12 +XBUF<7> A<7> Z<7> VDD VSS / RSC_IHPSG13_WLDRVX12 +XBUF<6> A<6> Z<6> VDD VSS / RSC_IHPSG13_WLDRVX12 +XBUF<5> A<5> Z<5> VDD VSS / RSC_IHPSG13_WLDRVX12 +XBUF<4> A<4> Z<4> VDD VSS / RSC_IHPSG13_WLDRVX12 +XBUF<3> A<3> Z<3> VDD VSS / RSC_IHPSG13_WLDRVX12 +XBUF<2> A<2> Z<2> VDD VSS / RSC_IHPSG13_WLDRVX12 +XBUF<1> A<1> Z<1> VDD VSS / RSC_IHPSG13_WLDRVX12 +XBUF<0> A<0> Z<0> VDD VSS / RSC_IHPSG13_WLDRVX12 +.ENDS + + + +.SUBCKT RM_IHPSG13_512x8_c3_2P_COLDRV13X8 ADDR_COL_I<1> ADDR_COL_I<0> ADDR_COL_O<1> ++ ADDR_COL_O<0> ADDR_DEC_I<7> ADDR_DEC_I<6> ADDR_DEC_I<5> ADDR_DEC_I<4> ++ ADDR_DEC_I<3> ADDR_DEC_I<2> ADDR_DEC_I<1> ADDR_DEC_I<0> ADDR_DEC_O<7> ++ ADDR_DEC_O<6> ADDR_DEC_O<5> ADDR_DEC_O<4> ADDR_DEC_O<3> ADDR_DEC_O<2> ++ ADDR_DEC_O<1> ADDR_DEC_O<0> DCLK_I DCLK_O RCLK_I RCLK_O WCLK_I WCLK_O ++ VDD VSS +XI0<5> VDD VSS / RSC_IHPSG13_FILLCAP4 +XI0<4> VDD VSS / RSC_IHPSG13_FILLCAP4 +XI0<3> VDD VSS / RSC_IHPSG13_FILLCAP4 +XI0<2> VDD VSS / RSC_IHPSG13_FILLCAP4 +XI0<1> VDD VSS / RSC_IHPSG13_FILLCAP4 +XWCLK_DRV WCLK_I WCLK_O VDD VSS / RSC_IHPSG13_CBUFX8 +XRCLK_DRV RCLK_I RCLK_O VDD VSS / RSC_IHPSG13_CBUFX8 +XDCLK_DRV DCLK_I DCLK_O VDD VSS / RSC_IHPSG13_CBUFX8 +XADDR_COL_DRV<1> ADDR_COL_I<1> ADDR_COL_O<1> VDD VSS / ++ RSC_IHPSG13_CBUFX8 +XADDR_COL_DRV<0> ADDR_COL_I<0> ADDR_COL_O<0> VDD VSS / ++ RSC_IHPSG13_CBUFX8 +XADDR_DEC_DRV<7> ADDR_DEC_I<7> ADDR_DEC_O<7> VDD VSS / ++ RSC_IHPSG13_CBUFX8 +XADDR_DEC_DRV<6> ADDR_DEC_I<6> ADDR_DEC_O<6> VDD VSS / ++ RSC_IHPSG13_CBUFX8 +XADDR_DEC_DRV<5> ADDR_DEC_I<5> ADDR_DEC_O<5> VDD VSS / ++ RSC_IHPSG13_CBUFX8 +XADDR_DEC_DRV<4> ADDR_DEC_I<4> ADDR_DEC_O<4> VDD VSS / ++ RSC_IHPSG13_CBUFX8 +XADDR_DEC_DRV<3> ADDR_DEC_I<3> ADDR_DEC_O<3> VDD VSS / ++ RSC_IHPSG13_CBUFX8 +XADDR_DEC_DRV<2> ADDR_DEC_I<2> ADDR_DEC_O<2> VDD VSS / ++ RSC_IHPSG13_CBUFX8 +XADDR_DEC_DRV<1> ADDR_DEC_I<1> ADDR_DEC_O<1> VDD VSS / ++ RSC_IHPSG13_CBUFX8 +XADDR_DEC_DRV<0> ADDR_DEC_I<0> ADDR_DEC_O<0> VDD VSS / ++ RSC_IHPSG13_CBUFX8 +XI1<3> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI1<2> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI1<1> VDD VSS / RSC_IHPSG13_FILLCAP8 +.ENDS +.SUBCKT RSC_IHPSG13_WLDRVX8 A Z VDD VSS +MN1 Z net6 VSS VSS sg13_lv_nmos m=1 w=1.41u l=130.00n ng=2 nrd=0 nrs=0 +MN0 net6 A VSS VSS sg13_lv_nmos m=1 w=1.8u l=130.00n ng=2 nrd=0 nrs=0 +MP1 Z net6 VDD VDD sg13_lv_pmos m=1 w=6.48u l=130.00n ng=4 nrd=0 nrs=0 +MP0 net6 A VDD VDD sg13_lv_pmos m=1 w=900.0n l=130.00n ng=1 nrd=0 nrs=0 +.ENDS +.SUBCKT RM_IHPSG13_512x8_c3_2P_WLDRV16X8 A<15> A<14> A<13> A<12> A<11> A<10> A<9> A<8> ++ A<7> A<6> A<5> A<4> A<3> A<2> A<1> A<0> Z<15> Z<14> Z<13> Z<12> Z<11> Z<10> ++ Z<9> Z<8> Z<7> Z<6> Z<5> Z<4> Z<3> Z<2> Z<1> Z<0> VDD VSS +XBUF<15> A<15> Z<15> VDD VSS / RSC_IHPSG13_WLDRVX8 +XBUF<14> A<14> Z<14> VDD VSS / RSC_IHPSG13_WLDRVX8 +XBUF<13> A<13> Z<13> VDD VSS / RSC_IHPSG13_WLDRVX8 +XBUF<12> A<12> Z<12> VDD VSS / RSC_IHPSG13_WLDRVX8 +XBUF<11> A<11> Z<11> VDD VSS / RSC_IHPSG13_WLDRVX8 +XBUF<10> A<10> Z<10> VDD VSS / RSC_IHPSG13_WLDRVX8 +XBUF<9> A<9> Z<9> VDD VSS / RSC_IHPSG13_WLDRVX8 +XBUF<8> A<8> Z<8> VDD VSS / RSC_IHPSG13_WLDRVX8 +XBUF<7> A<7> Z<7> VDD VSS / RSC_IHPSG13_WLDRVX8 +XBUF<6> A<6> Z<6> VDD VSS / RSC_IHPSG13_WLDRVX8 +XBUF<5> A<5> Z<5> VDD VSS / RSC_IHPSG13_WLDRVX8 +XBUF<4> A<4> Z<4> VDD VSS / RSC_IHPSG13_WLDRVX8 +XBUF<3> A<3> Z<3> VDD VSS / RSC_IHPSG13_WLDRVX8 +XBUF<2> A<2> Z<2> VDD VSS / RSC_IHPSG13_WLDRVX8 +XBUF<1> A<1> Z<1> VDD VSS / RSC_IHPSG13_WLDRVX8 +XBUF<0> A<0> Z<0> VDD VSS / RSC_IHPSG13_WLDRVX8 +.ENDS + + + +.SUBCKT RM_IHPSG13_512x8_c3_2P_COLDEC2 ACLK_N ADDR<1> ADDR<0> ADDR_COL<1> ADDR_COL<0> ++ ADDR_DEC<7> ADDR_DEC<6> ADDR_DEC<5> ADDR_DEC<4> ADDR_DEC<3> ADDR_DEC<2> ++ ADDR_DEC<1> ADDR_DEC<0> BIST_ADDR<1> BIST_ADDR<0> BIST_EN_I VDD VSS +XI16<17> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI16<16> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI16<15> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI16<14> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI16<13> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI16<12> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI16<11> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI16<10> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI16<9> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI16<8> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI16<7> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI16<6> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI16<5> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI16<4> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI16<3> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI16<2> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI16<1> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI18<24> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI18<23> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI18<22> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI18<21> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI18<20> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI18<19> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI18<18> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI18<17> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI18<16> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI18<15> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI18<14> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI18<13> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI18<12> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI18<11> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI18<10> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI18<9> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI18<8> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI18<7> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI18<6> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI18<5> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI18<4> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI18<3> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI18<2> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI18<1> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI1<3> PADR<0> PADR<1> addr_n<3> VDD VSS / RSC_IHPSG13_NAND2X2 +XI1<2> NADR<0> PADR<1> addr_n<2> VDD VSS / RSC_IHPSG13_NAND2X2 +XI1<1> PADR<0> NADR<1> addr_n<1> VDD VSS / RSC_IHPSG13_NAND2X2 +XI1<0> NADR<0> NADR<1> addr_n<0> VDD VSS / RSC_IHPSG13_NAND2X2 +XI17<1> ADDR_COL<1> VDD VSS / RSC_IHPSG13_TIEL +XI17<0> ADDR_COL<0> VDD VSS / RSC_IHPSG13_TIEL +XI14<3> ADDR_DEC<7> VDD VSS / RSC_IHPSG13_TIEL +XI14<2> ADDR_DEC<6> VDD VSS / RSC_IHPSG13_TIEL +XI14<1> ADDR_DEC<5> VDD VSS / RSC_IHPSG13_TIEL +XI14<0> ADDR_DEC<4> VDD VSS / RSC_IHPSG13_TIEL +XI13<1> NADR<1> PADR<1> VDD VSS / RSC_IHPSG13_INVX2 +XI13<0> NADR<0> PADR<0> VDD VSS / RSC_IHPSG13_INVX2 +XI3<1> padr_int<1> NADR<1> VDD VSS / RSC_IHPSG13_INVX2 +XI3<0> padr_int<0> NADR<0> VDD VSS / RSC_IHPSG13_INVX2 +XI2<3> addr_n<3> ADDR_DEC<3> VDD VSS / RSC_IHPSG13_INVX2 +XI2<2> addr_n<2> ADDR_DEC<2> VDD VSS / RSC_IHPSG13_INVX2 +XI2<1> addr_n<1> ADDR_DEC<1> VDD VSS / RSC_IHPSG13_INVX2 +XI2<0> addr_n<0> ADDR_DEC<0> VDD VSS / RSC_IHPSG13_INVX2 +XDFF<1> BIST_EN_I BIST_ADDR<1> ACLK_N ADDR<1> padr_int<1> net12<0> VDD ++ VSS / RSC_IHPSG13_DFNQMX2IX1 +XDFF<0> BIST_EN_I BIST_ADDR<0> ACLK_N ADDR<0> padr_int<0> net12<1> VDD ++ VSS / RSC_IHPSG13_DFNQMX2IX1 +XI15<5> VDD VSS / RSC_IHPSG13_FILLCAP4 +XI15<4> VDD VSS / RSC_IHPSG13_FILLCAP4 +XI15<3> VDD VSS / RSC_IHPSG13_FILLCAP4 +XI15<2> VDD VSS / RSC_IHPSG13_FILLCAP4 +XI15<1> VDD VSS / RSC_IHPSG13_FILLCAP4 +XI19<4> VDD VSS / RSC_IHPSG13_FILLCAP4 +XI19<3> VDD VSS / RSC_IHPSG13_FILLCAP4 +XI19<2> VDD VSS / RSC_IHPSG13_FILLCAP4 +XI19<1> VDD VSS / RSC_IHPSG13_FILLCAP4 +.ENDS +.SUBCKT RM_IHPSG13_512x8_c3_2P_COLCTRL2 A_ADDR_DEC<3> A_ADDR_DEC<2> A_ADDR_DEC<1> ++ A_ADDR_DEC<0> A_BIST_BM_I A_BIST_DW_I A_BIST_EN_I A_BLC<3> A_BLC<2> A_BLC<1> ++ A_BLC<0> A_BLT<3> A_BLT<2> A_BLT<1> A_BLT<0> A_BM_I A_DCLK_B_L A_DCLK_B_R ++ A_DCLK_L A_DCLK_R A_DR_O A_DW_I A_RCLK_B_L A_RCLK_B_R A_RCLK_L A_RCLK_R ++ A_TIEH_O A_WCLK_B_L A_WCLK_B_R A_WCLK_L A_WCLK_R B_ADDR_DEC<3> B_ADDR_DEC<2> ++ B_ADDR_DEC<1> B_ADDR_DEC<0> B_BIST_BM_I B_BIST_DW_I B_BIST_EN_I B_BLC<3> ++ B_BLC<2> B_BLC<1> B_BLC<0> B_BLT<3> B_BLT<2> B_BLT<1> B_BLT<0> B_BM_I ++ B_DCLK_B_L B_DCLK_B_R B_DCLK_L B_DCLK_R B_DR_O B_DW_I B_RCLK_B_L B_RCLK_B_R ++ B_RCLK_L B_RCLK_R B_TIEH_O B_WCLK_B_L B_WCLK_B_R B_WCLK_L B_WCLK_R VDD ++ VSS +XB_DREG B_BIST_EN_I B_BIST_DW_I B_DCLK_B_L B_DW_I B_DI_R net046 VDD ++ VSS / RSC_IHPSG13_DFNQMX2IX1 +XB_BREG B_BIST_EN_I B_BIST_BM_I B_DCLK_B_L B_BM_I B_BM_R net045 VDD ++ VSS / RSC_IHPSG13_DFNQMX2IX1 +XA_DREG A_BIST_EN_I A_BIST_DW_I A_DCLK_B_L A_DW_I A_DI_R net22 VDD VSS ++ / RSC_IHPSG13_DFNQMX2IX1 +XA_BREG A_BIST_EN_I A_BIST_BM_I A_DCLK_B_L A_BM_I A_BM_R net23 VDD VSS ++ / RSC_IHPSG13_DFNQMX2IX1 +XB_CAPS VDD VSS / RSC_IHPSG13_FILLCAP4 +XA_CAPS VDD VSS / RSC_IHPSG13_FILLCAP4 +XB_I75 B_DI_R B_DO_WRITE_P B_WR_ONE VDD VSS / RSC_IHPSG13_AND2X2 +XB_I80 B_RCLK_B_L B_WCLK_B_L net041 VDD VSS / RSC_IHPSG13_AND2X2 +XB_I76 B_DI_N B_DO_WRITE_P B_WR_ZERO VDD VSS / RSC_IHPSG13_AND2X2 +XA_I80 A_RCLK_B_L A_WCLK_B_L net21 VDD VSS / RSC_IHPSG13_AND2X2 +XA_I75 A_DI_R A_DO_WRITE_P A_WR_ONE VDD VSS / RSC_IHPSG13_AND2X2 +XA_I76 A_DI_N A_DO_WRITE_P A_WR_ZERO VDD VSS / RSC_IHPSG13_AND2X2 +XB_I44 B_WCLK_B_L B_BM_N B_DO_WRITE_P VDD VSS / RSC_IHPSG13_NOR2X2 +XA_I44 A_WCLK_B_L A_BM_N A_DO_WRITE_P VDD VSS / RSC_IHPSG13_NOR2X2 +XB_I81 net041 B_PRE_N VDD VSS / RSC_IHPSG13_CINVX4_WN +XA_I81 net21 A_PRE_N VDD VSS / RSC_IHPSG13_CINVX4_WN +XB_BM_TIEH B_TIEH_O VDD VSS / RSC_IHPSG13_TIEH +XA_BM_TIEH A_TIEH_O VDD VSS / RSC_IHPSG13_TIEH +XA_I89 A_DCLK_B_L A_DCLK_B_R / RSC_IHPSG13_MET3RES +XA_I88 A_DCLK_L A_DCLK_R / RSC_IHPSG13_MET3RES +XA_I87 A_WCLK_L A_WCLK_R / RSC_IHPSG13_MET3RES +XA_I91 A_RCLK_B_L A_RCLK_B_R / RSC_IHPSG13_MET3RES +XB_I87 B_WCLK_L B_WCLK_R / RSC_IHPSG13_MET3RES +XB_I88 B_DCLK_L B_DCLK_R / RSC_IHPSG13_MET3RES +XB_I89 B_DCLK_B_L B_DCLK_B_R / RSC_IHPSG13_MET3RES +XB_I90 B_WCLK_B_L B_WCLK_B_R / RSC_IHPSG13_MET3RES +XB_R2 B_RCLK_L B_RCLK_R / RSC_IHPSG13_MET3RES +XB_I91 B_RCLK_B_L B_RCLK_B_R / RSC_IHPSG13_MET3RES +XA_R2 A_RCLK_L A_RCLK_R / RSC_IHPSG13_MET3RES +XA_I90 A_WCLK_B_L A_WCLK_B_R / RSC_IHPSG13_MET3RES +XAB_BLMUX A_BLC<3> A_BLC<2> A_BLC<1> A_BLC<0> A_BLC_SEL A_BLT<3> A_BLT<2> ++ A_BLT<1> A_BLT<0> A_BLT_SEL A_PRE_N A_ADDR_DEC<3> A_ADDR_DEC<2> ++ A_ADDR_DEC<1> A_ADDR_DEC<0> A_WR_ONE A_WR_ZERO B_BLC<3> B_BLC<2> B_BLC<1> ++ B_BLC<0> B_BLC_SEL B_BLT<3> B_BLT<2> B_BLT<1> B_BLT<0> B_BLT_SEL B_PRE_N ++ B_ADDR_DEC<3> B_ADDR_DEC<2> B_ADDR_DEC<1> B_ADDR_DEC<0> B_WR_ONE B_WR_ZERO ++ VDD VSS / RM_IHPSG13_512x8_c3_2P_BLDRV +XB_ISENSE B_SAE B_BLC_SEL B_BLT_SEL net039 net040 VDD VSS / ++ RSC_IHPSG13_DFPQD_MSAFFX2 +XA_ISENSE A_SAE A_BLC_SEL A_BLT_SEL net19 net20 VDD VSS / ++ RSC_IHPSG13_DFPQD_MSAFFX2 +XB_I78 B_RCLK_B_L B_SAE VDD VSS / RSC_IHPSG13_CBUFX2 +XA_I78 A_RCLK_B_L A_SAE VDD VSS / RSC_IHPSG13_CBUFX2 +XB_I83 B_BM_R B_BM_N VDD VSS / RSC_IHPSG13_INVX2 +XB_I49 B_DI_R B_DI_N VDD VSS / RSC_IHPSG13_INVX2 +XA_I83 A_BM_R A_BM_N VDD VSS / RSC_IHPSG13_INVX2 +XA_I49 A_DI_R A_DI_N VDD VSS / RSC_IHPSG13_INVX2 +XB_I51 net039 B_DR_O VDD VSS / RSC_IHPSG13_INVX4 +XA_I51 net19 A_DR_O VDD VSS / RSC_IHPSG13_INVX4 +XA_I69 A_DCLK_L A_DCLK_B_L VDD VSS / RSC_IHPSG13_CINVX2 +XA_I50 A_WCLK_L A_WCLK_B_L VDD VSS / RSC_IHPSG13_CINVX2 +XA_EBUF A_RCLK_L A_RCLK_B_L VDD VSS / RSC_IHPSG13_CINVX2 +XB_EBUF B_RCLK_L B_RCLK_B_L VDD VSS / RSC_IHPSG13_CINVX2 +XB_I50 B_WCLK_L B_WCLK_B_L VDD VSS / RSC_IHPSG13_CINVX2 +XB_I69 B_DCLK_L B_DCLK_B_L VDD VSS / RSC_IHPSG13_CINVX2 +.ENDS +.SUBCKT RM_IHPSG13_512x8_c3_2P_COLDRV13_FILL4C2 VDD VSS +XI0<2> VDD VSS / RSC_IHPSG13_FILLCAP4 +XI0<1> VDD VSS / RSC_IHPSG13_FILLCAP4 +.ENDS + + +.SUBCKT RM_IHPSG13_512x8_c3_2P_ROWDEC7 ADDR_N_I<6> ADDR_N_I<5> ADDR_N_I<4> ADDR_N_I<3> ++ ADDR_N_I<2> ADDR_N_I<1> ADDR_N_I<0> CS_I ECLK_I WL_O<127> WL_O<126> ++ WL_O<125> WL_O<124> WL_O<123> WL_O<122> WL_O<121> WL_O<120> WL_O<119> ++ WL_O<118> WL_O<117> WL_O<116> WL_O<115> WL_O<114> WL_O<113> WL_O<112> ++ WL_O<111> WL_O<110> WL_O<109> WL_O<108> WL_O<107> WL_O<106> WL_O<105> ++ WL_O<104> WL_O<103> WL_O<102> WL_O<101> WL_O<100> WL_O<99> WL_O<98> WL_O<97> ++ WL_O<96> WL_O<95> WL_O<94> WL_O<93> WL_O<92> WL_O<91> WL_O<90> WL_O<89> ++ WL_O<88> WL_O<87> WL_O<86> WL_O<85> WL_O<84> WL_O<83> WL_O<82> WL_O<81> ++ WL_O<80> WL_O<79> WL_O<78> WL_O<77> WL_O<76> WL_O<75> WL_O<74> WL_O<73> ++ WL_O<72> WL_O<71> WL_O<70> WL_O<69> WL_O<68> WL_O<67> WL_O<66> WL_O<65> ++ WL_O<64> WL_O<63> WL_O<62> WL_O<61> WL_O<60> WL_O<59> WL_O<58> WL_O<57> ++ WL_O<56> WL_O<55> WL_O<54> WL_O<53> WL_O<52> WL_O<51> WL_O<50> WL_O<49> ++ WL_O<48> WL_O<47> WL_O<46> WL_O<45> WL_O<44> WL_O<43> WL_O<42> WL_O<41> ++ WL_O<40> WL_O<39> WL_O<38> WL_O<37> WL_O<36> WL_O<35> WL_O<34> WL_O<33> ++ WL_O<32> WL_O<31> WL_O<30> WL_O<29> WL_O<28> WL_O<27> WL_O<26> WL_O<25> ++ WL_O<24> WL_O<23> WL_O<22> WL_O<21> WL_O<20> WL_O<19> WL_O<18> WL_O<17> ++ WL_O<16> WL_O<15> WL_O<14> WL_O<13> WL_O<12> WL_O<11> WL_O<10> WL_O<9> ++ WL_O<8> WL_O<7> WL_O<6> WL_O<5> WL_O<4> WL_O<3> WL_O<2> WL_O<1> WL_O<0> ++ VDD VSS +XSEL<7> ADDR_N_I<3> ADDR_N_I<2> ADDR_N_I<1> ADDR_N_I<0> CS00<7> ECLK_H<7> ++ ECLK_H<8> ECLK_B<7> ECLK_B<8> WL_O<127> WL_O<126> WL_O<125> WL_O<124> ++ WL_O<123> WL_O<122> WL_O<121> WL_O<120> WL_O<119> WL_O<118> WL_O<117> ++ WL_O<116> WL_O<115> WL_O<114> WL_O<113> WL_O<112> VDD VSS / ++ RM_IHPSG13_512x8_c3_2P_DEC04 +XSEL<6> ADDR_N_I<3> ADDR_N_I<2> ADDR_N_I<1> ADDR_N_I<0> CS00<6> ECLK_H<6> ++ ECLK_H<7> ECLK_B<6> ECLK_B<7> WL_O<111> WL_O<110> WL_O<109> WL_O<108> ++ WL_O<107> WL_O<106> WL_O<105> WL_O<104> WL_O<103> WL_O<102> WL_O<101> ++ WL_O<100> WL_O<99> WL_O<98> WL_O<97> WL_O<96> VDD VSS / ++ RM_IHPSG13_512x8_c3_2P_DEC04 +XSEL<5> ADDR_N_I<3> ADDR_N_I<2> ADDR_N_I<1> ADDR_N_I<0> CS00<5> ECLK_H<5> ++ ECLK_H<6> ECLK_B<5> ECLK_B<6> WL_O<95> WL_O<94> WL_O<93> WL_O<92> WL_O<91> ++ WL_O<90> WL_O<89> WL_O<88> WL_O<87> WL_O<86> WL_O<85> WL_O<84> WL_O<83> ++ WL_O<82> WL_O<81> WL_O<80> VDD VSS / RM_IHPSG13_512x8_c3_2P_DEC04 +XSEL<4> ADDR_N_I<3> ADDR_N_I<2> ADDR_N_I<1> ADDR_N_I<0> CS00<4> ECLK_H<4> ++ ECLK_H<5> ECLK_B<4> ECLK_B<5> WL_O<79> WL_O<78> WL_O<77> WL_O<76> WL_O<75> ++ WL_O<74> WL_O<73> WL_O<72> WL_O<71> WL_O<70> WL_O<69> WL_O<68> WL_O<67> ++ WL_O<66> WL_O<65> WL_O<64> VDD VSS / RM_IHPSG13_512x8_c3_2P_DEC04 +XSEL<3> ADDR_N_I<3> ADDR_N_I<2> ADDR_N_I<1> ADDR_N_I<0> CS00<3> ECLK_H<3> ++ ECLK_H<4> ECLK_B<3> ECLK_B<4> WL_O<63> WL_O<62> WL_O<61> WL_O<60> WL_O<59> ++ WL_O<58> WL_O<57> WL_O<56> WL_O<55> WL_O<54> WL_O<53> WL_O<52> WL_O<51> ++ WL_O<50> WL_O<49> WL_O<48> VDD VSS / RM_IHPSG13_512x8_c3_2P_DEC04 +XSEL<2> ADDR_N_I<3> ADDR_N_I<2> ADDR_N_I<1> ADDR_N_I<0> CS00<2> ECLK_H<2> ++ ECLK_H<3> ECLK_B<2> ECLK_B<3> WL_O<47> WL_O<46> WL_O<45> WL_O<44> WL_O<43> ++ WL_O<42> WL_O<41> WL_O<40> WL_O<39> WL_O<38> WL_O<37> WL_O<36> WL_O<35> ++ WL_O<34> WL_O<33> WL_O<32> VDD VSS / RM_IHPSG13_512x8_c3_2P_DEC04 +XSEL<1> ADDR_N_I<3> ADDR_N_I<2> ADDR_N_I<1> ADDR_N_I<0> CS00<1> ECLK_H<1> ++ ECLK_H<2> ECLK_B<1> ECLK_B<2> WL_O<31> WL_O<30> WL_O<29> WL_O<28> WL_O<27> ++ WL_O<26> WL_O<25> WL_O<24> WL_O<23> WL_O<22> WL_O<21> WL_O<20> WL_O<19> ++ WL_O<18> WL_O<17> WL_O<16> VDD VSS / RM_IHPSG13_512x8_c3_2P_DEC04 +XSEL<0> ADDR_N_I<3> ADDR_N_I<2> ADDR_N_I<1> ADDR_N_I<0> CS00<0> ECLK_I ++ ECLK_H<1> ECLK_B<0> ECLK_B<1> WL_O<15> WL_O<14> WL_O<13> WL_O<12> WL_O<11> ++ WL_O<10> WL_O<9> WL_O<8> WL_O<7> WL_O<6> WL_O<5> WL_O<4> WL_O<3> WL_O<2> ++ WL_O<1> WL_O<0> VDD VSS / RM_IHPSG13_512x8_c3_2P_DEC04 +XDEC11<1> ADDR_N_I<5> ADDR_N_I<4> CS04<1> CS00<7> VDD VSS / ++ RM_IHPSG13_512x8_c3_2P_DEC03 +XDEC11<0> ADDR_N_I<5> ADDR_N_I<4> CS04<0> CS00<3> VDD VSS / ++ RM_IHPSG13_512x8_c3_2P_DEC03 +XDEC01<2> ADDR_N_I<7> ADDR_N_I<6> CS_I CS04<1> VDD VSS / ++ RM_IHPSG13_512x8_c3_2P_DEC01 +XDEC01<1> ADDR_N_I<5> ADDR_N_I<4> CS04<1> CS00<5> VDD VSS / ++ RM_IHPSG13_512x8_c3_2P_DEC01 +XDEC01<0> ADDR_N_I<5> ADDR_N_I<4> CS04<0> CS00<1> VDD VSS / ++ RM_IHPSG13_512x8_c3_2P_DEC01 +XL2<66> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<65> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<64> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<63> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<62> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<61> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<60> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<59> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<58> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<57> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<56> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<55> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<54> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<53> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<52> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<51> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<50> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<49> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<48> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<47> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<46> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<45> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<44> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<43> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<42> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<41> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<40> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<39> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<38> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<37> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<36> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<35> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<34> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<33> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<32> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<31> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<30> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<29> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<28> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<27> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<26> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<25> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<24> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<23> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<22> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<21> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<20> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<19> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<18> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<17> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<16> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<15> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<14> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<13> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<12> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<11> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<10> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<9> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<8> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<7> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<6> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<5> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<4> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<3> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<2> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<1> VDD VSS / RSC_IHPSG13_FILLCAP8 +XDEC10<1> ADDR_N_I<5> ADDR_N_I<4> CS04<1> CS00<6> VDD VSS / ++ RM_IHPSG13_512x8_c3_2P_DEC02 +XDEC10<0> ADDR_N_I<5> ADDR_N_I<4> CS04<0> CS00<2> VDD VSS / ++ RM_IHPSG13_512x8_c3_2P_DEC02 +XDEC00<2> ADDR_N_I<7> ADDR_N_I<6> CS_I CS04<0> VDD VSS / ++ RM_IHPSG13_512x8_c3_2P_DEC00 +XDEC00<1> ADDR_N_I<5> ADDR_N_I<4> CS04<1> CS00<4> VDD VSS / ++ RM_IHPSG13_512x8_c3_2P_DEC00 +XDEC00<0> ADDR_N_I<5> ADDR_N_I<4> CS04<0> CS00<0> VDD VSS / ++ RM_IHPSG13_512x8_c3_2P_DEC00 +XI0 ADDR_N_I<7> VDD VSS / RSC_IHPSG13_TIEL +.ENDS +.SUBCKT RM_IHPSG13_512x8_c3_2P_ROWREG7 ACLK_N_I ADDR_I<6> ADDR_I<5> ADDR_I<4> ADDR_I<3> ++ ADDR_I<2> ADDR_I<1> ADDR_I<0> ADDR_N_O<6> ADDR_N_O<5> ADDR_N_O<4> ++ ADDR_N_O<3> ADDR_N_O<2> ADDR_N_O<1> ADDR_N_O<0> BIST_ADDR_I<6> ++ BIST_ADDR_I<5> BIST_ADDR_I<4> BIST_ADDR_I<3> BIST_ADDR_I<2> BIST_ADDR_I<1> ++ BIST_ADDR_I<0> BIST_EN_I VDD VSS +XINV<6> q_int<6> qn_int<6> VDD VSS / RSC_IHPSG13_CINVX2 +XINV<5> q_int<5> qn_int<5> VDD VSS / RSC_IHPSG13_CINVX2 +XINV<4> q_int<4> qn_int<4> VDD VSS / RSC_IHPSG13_CINVX2 +XINV<3> q_int<3> qn_int<3> VDD VSS / RSC_IHPSG13_CINVX2 +XINV<2> q_int<2> qn_int<2> VDD VSS / RSC_IHPSG13_CINVX2 +XINV<1> q_int<1> qn_int<1> VDD VSS / RSC_IHPSG13_CINVX2 +XINV<0> q_int<0> qn_int<0> VDD VSS / RSC_IHPSG13_CINVX2 +XDRV<6> qn_int<6> ADDR_N_O<6> VDD VSS / RSC_IHPSG13_CINVX8 +XDRV<5> qn_int<5> ADDR_N_O<5> VDD VSS / RSC_IHPSG13_CINVX8 +XDRV<4> qn_int<4> ADDR_N_O<4> VDD VSS / RSC_IHPSG13_CINVX8 +XDRV<3> qn_int<3> ADDR_N_O<3> VDD VSS / RSC_IHPSG13_CINVX8 +XDRV<2> qn_int<2> ADDR_N_O<2> VDD VSS / RSC_IHPSG13_CINVX8 +XDRV<1> qn_int<1> ADDR_N_O<1> VDD VSS / RSC_IHPSG13_CINVX8 +XDRV<0> qn_int<0> ADDR_N_O<0> VDD VSS / RSC_IHPSG13_CINVX8 +XDFF<6> BIST_EN_I BIST_ADDR_I<6> ACLK_N_I ADDR_I<6> q_int<6> net2<0> VDD ++ VSS / RSC_IHPSG13_DFNQMX2IX1 +XDFF<5> BIST_EN_I BIST_ADDR_I<5> ACLK_N_I ADDR_I<5> q_int<5> net2<1> VDD ++ VSS / RSC_IHPSG13_DFNQMX2IX1 +XDFF<4> BIST_EN_I BIST_ADDR_I<4> ACLK_N_I ADDR_I<4> q_int<4> net2<2> VDD ++ VSS / RSC_IHPSG13_DFNQMX2IX1 +XDFF<3> BIST_EN_I BIST_ADDR_I<3> ACLK_N_I ADDR_I<3> q_int<3> net2<3> VDD ++ VSS / RSC_IHPSG13_DFNQMX2IX1 +XDFF<2> BIST_EN_I BIST_ADDR_I<2> ACLK_N_I ADDR_I<2> q_int<2> net2<4> VDD ++ VSS / RSC_IHPSG13_DFNQMX2IX1 +XDFF<1> BIST_EN_I BIST_ADDR_I<1> ACLK_N_I ADDR_I<1> q_int<1> net2<5> VDD ++ VSS / RSC_IHPSG13_DFNQMX2IX1 +XDFF<0> BIST_EN_I BIST_ADDR_I<0> ACLK_N_I ADDR_I<0> q_int<0> net2<6> VDD ++ VSS / RSC_IHPSG13_DFNQMX2IX1 +XI11<7> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI11<6> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI11<5> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI11<4> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI11<3> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI11<2> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI11<1> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI11<0> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI12<1> VDD VSS / RSC_IHPSG13_FILLCAP4 +XI12<0> VDD VSS / RSC_IHPSG13_FILLCAP4 +.ENDS + +.SUBCKT RM_IHPSG13_512x8_c3_2P_ROWDEC4 ADDR_N_I<3> ADDR_N_I<2> ADDR_N_I<1> ADDR_N_I<0> ++ CS_I ECLK_I WL_O<15> WL_O<14> WL_O<13> WL_O<12> WL_O<11> WL_O<10> WL_O<9> ++ WL_O<8> WL_O<7> WL_O<6> WL_O<5> WL_O<4> WL_O<3> WL_O<2> WL_O<1> WL_O<0> ++ VDD VSS +XL2<12> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<11> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<10> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<9> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<8> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<7> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<6> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<5> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<4> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<3> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<2> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<1> VDD VSS / RSC_IHPSG13_FILLCAP8 +XSEL ADDR_N_I<3> ADDR_N_I<2> ADDR_N_I<1> ADDR_N_I<0> CS_I ECLK_I ECLK_H<1> ++ ECLK_B<0> ECLK_B<1> WL_O<15> WL_O<14> WL_O<13> WL_O<12> WL_O<11> WL_O<10> ++ WL_O<9> WL_O<8> WL_O<7> WL_O<6> WL_O<5> WL_O<4> WL_O<3> WL_O<2> WL_O<1> ++ WL_O<0> VDD VSS / RM_IHPSG13_512x8_c3_2P_DEC04 +.ENDS +.SUBCKT RM_IHPSG13_512x8_c3_2P_ROWREG4 ACLK_N_I ADDR_I<3> ADDR_I<2> ADDR_I<1> ADDR_I<0> ++ ADDR_N_O<3> ADDR_N_O<2> ADDR_N_O<1> ADDR_N_O<0> BIST_ADDR_I<3> ++ BIST_ADDR_I<2> BIST_ADDR_I<1> BIST_ADDR_I<0> BIST_EN_I VDD VSS +XINV<3> q_int<3> qn_int<3> VDD VSS / RSC_IHPSG13_CINVX2 +XINV<2> q_int<2> qn_int<2> VDD VSS / RSC_IHPSG13_CINVX2 +XINV<1> q_int<1> qn_int<1> VDD VSS / RSC_IHPSG13_CINVX2 +XINV<0> q_int<0> qn_int<0> VDD VSS / RSC_IHPSG13_CINVX2 +XDRV<3> qn_int<3> ADDR_N_O<3> VDD VSS / RSC_IHPSG13_CINVX8 +XDRV<2> qn_int<2> ADDR_N_O<2> VDD VSS / RSC_IHPSG13_CINVX8 +XDRV<1> qn_int<1> ADDR_N_O<1> VDD VSS / RSC_IHPSG13_CINVX8 +XDRV<0> qn_int<0> ADDR_N_O<0> VDD VSS / RSC_IHPSG13_CINVX8 +XDFF<3> BIST_EN_I BIST_ADDR_I<3> ACLK_N_I ADDR_I<3> q_int<3> net7<0> VDD ++ VSS / RSC_IHPSG13_DFNQMX2IX1 +XDFF<2> BIST_EN_I BIST_ADDR_I<2> ACLK_N_I ADDR_I<2> q_int<2> net7<1> VDD ++ VSS / RSC_IHPSG13_DFNQMX2IX1 +XDFF<1> BIST_EN_I BIST_ADDR_I<1> ACLK_N_I ADDR_I<1> q_int<1> net7<2> VDD ++ VSS / RSC_IHPSG13_DFNQMX2IX1 +XDFF<0> BIST_EN_I BIST_ADDR_I<0> ACLK_N_I ADDR_I<0> q_int<0> net7<3> VDD ++ VSS / RSC_IHPSG13_DFNQMX2IX1 +XI11<20> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI11<19> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI11<18> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI11<17> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI11<16> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI11<15> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI11<14> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI11<13> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI11<12> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI11<11> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI11<10> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI11<9> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI11<8> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI11<7> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI11<6> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI11<5> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI11<4> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI11<3> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI11<2> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI11<1> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI12<4> VDD VSS / RSC_IHPSG13_FILLCAP4 +XI12<3> VDD VSS / RSC_IHPSG13_FILLCAP4 +XI12<2> VDD VSS / RSC_IHPSG13_FILLCAP4 +XI12<1> VDD VSS / RSC_IHPSG13_FILLCAP4 +XI12<0> VDD VSS / RSC_IHPSG13_FILLCAP4 +.ENDS + + +.SUBCKT RM_IHPSG13_512x8_c3_1P_BITKIT_TAP BLC BLT NW PW VDD VSS +.ENDS +.SUBCKT RM_IHPSG13_512x8_c3_1P_BITKIT_16x2_TAP A_BLC<1> A_BLC<0> A_BLT<1> A_BLT<0> ++ VDD_CORE VSS +XITAP<1> A_BLC<1> A_BLT<1> VDD_CORE VSS VDD_CORE VSS ++ / RM_IHPSG13_512x8_c3_1P_BITKIT_TAP +XITAP<0> A_BLC<0> A_BLT<0> VDD_CORE VSS VDD_CORE VSS ++ / RM_IHPSG13_512x8_c3_1P_BITKIT_TAP +XIEDGEBP_COL1<1> BLC<1> BLT<1> VDD_CORE VSS VDD_CORE ++ VSS / RM_IHPSG13_512x8_c3_1P_BITKIT_EDGE_TB +XIEDGEBP_COL1<0> BLC<1> BLT<1> VDD_CORE VSS VDD_CORE ++ VSS / RM_IHPSG13_512x8_c3_1P_BITKIT_EDGE_TB +XIEDGEBP_COL2<1> BLC<0> BLT<0> VDD_CORE VSS VDD_CORE ++ VSS / RM_IHPSG13_512x8_c3_1P_BITKIT_EDGE_TB +XIEDGEBP_COL2<0> BLC<0> BLT<0> VDD_CORE VSS VDD_CORE ++ VSS / RM_IHPSG13_512x8_c3_1P_BITKIT_EDGE_TB +.ENDS +.SUBCKT RM_IHPSG13_512x8_c3_1P_BITKIT_16x2_TAP_LR VDD_CORE VSS +XCORNER<1> VDD_CORE VSS VDD_CORE VSS / ++ RM_IHPSG13_512x8_c3_1P_BITKIT_CORNER +XCORNER<0> VDD_CORE VSS VDD_CORE VSS / ++ RM_IHPSG13_512x8_c3_1P_BITKIT_CORNER +XTAP_BORDER VDD_CORE VSS VDD_CORE VSS / ++ RM_IHPSG13_512x8_c3_1P_BITKIT_TAP_LR +.ENDS +.SUBCKT RM_IHPSG13_512x8_c3_1P_DEC03 ADDR<1> ADDR<0> CS CS_OUT VDD VSS +XDECINV net1 CS_OUT VDD VSS / RSC_IHPSG13_INVX4 +XI0 VDD VSS / RSC_IHPSG13_FILLCAP4 +XDEC ADDR<1> ADDR<0> CS net1 VDD VSS / RSC_IHPSG13_NAND3X2 +.ENDS +.SUBCKT RM_IHPSG13_512x8_c3_1P_DEC02 ADDR<1> ADDR<0> CS CS_OUT VDD VSS +XDECINV net1 CS_OUT VDD VSS / RSC_IHPSG13_INVX4 +XDEC ADDR<1> NADDR<0> CS net1 VDD VSS / RSC_IHPSG13_NAND3X2 +XI2 VDD VSS / RSC_IHPSG13_FILLCAP4 +XADDRINV ADDR<0> NADDR<0> VDD VSS / RSC_IHPSG13_INVX2 +.ENDS +.SUBCKT RM_IHPSG13_512x8_c3_1P_ROWDEC8 ADDR_N_I<7> ADDR_N_I<6> ADDR_N_I<5> ADDR_N_I<4> ++ ADDR_N_I<3> ADDR_N_I<2> ADDR_N_I<1> ADDR_N_I<0> CS_I ECLK_I WL_O<255> ++ WL_O<254> WL_O<253> WL_O<252> WL_O<251> WL_O<250> WL_O<249> WL_O<248> ++ WL_O<247> WL_O<246> WL_O<245> WL_O<244> WL_O<243> WL_O<242> WL_O<241> ++ WL_O<240> WL_O<239> WL_O<238> WL_O<237> WL_O<236> WL_O<235> WL_O<234> ++ WL_O<233> WL_O<232> WL_O<231> WL_O<230> WL_O<229> WL_O<228> WL_O<227> ++ WL_O<226> WL_O<225> WL_O<224> WL_O<223> WL_O<222> WL_O<221> WL_O<220> ++ WL_O<219> WL_O<218> WL_O<217> WL_O<216> WL_O<215> WL_O<214> WL_O<213> ++ WL_O<212> WL_O<211> WL_O<210> WL_O<209> WL_O<208> WL_O<207> WL_O<206> ++ WL_O<205> WL_O<204> WL_O<203> WL_O<202> WL_O<201> WL_O<200> WL_O<199> ++ WL_O<198> WL_O<197> WL_O<196> WL_O<195> WL_O<194> WL_O<193> WL_O<192> ++ WL_O<191> WL_O<190> WL_O<189> WL_O<188> WL_O<187> WL_O<186> WL_O<185> ++ WL_O<184> WL_O<183> WL_O<182> WL_O<181> WL_O<180> WL_O<179> WL_O<178> ++ WL_O<177> WL_O<176> WL_O<175> WL_O<174> WL_O<173> WL_O<172> WL_O<171> ++ WL_O<170> WL_O<169> WL_O<168> WL_O<167> WL_O<166> WL_O<165> WL_O<164> ++ WL_O<163> WL_O<162> WL_O<161> WL_O<160> WL_O<159> WL_O<158> WL_O<157> ++ WL_O<156> WL_O<155> WL_O<154> WL_O<153> WL_O<152> WL_O<151> WL_O<150> ++ WL_O<149> WL_O<148> WL_O<147> WL_O<146> WL_O<145> WL_O<144> WL_O<143> ++ WL_O<142> WL_O<141> WL_O<140> WL_O<139> WL_O<138> WL_O<137> WL_O<136> ++ WL_O<135> WL_O<134> WL_O<133> WL_O<132> WL_O<131> WL_O<130> WL_O<129> ++ WL_O<128> WL_O<127> WL_O<126> WL_O<125> WL_O<124> WL_O<123> WL_O<122> ++ WL_O<121> WL_O<120> WL_O<119> WL_O<118> WL_O<117> WL_O<116> WL_O<115> ++ WL_O<114> WL_O<113> WL_O<112> WL_O<111> WL_O<110> WL_O<109> WL_O<108> ++ WL_O<107> WL_O<106> WL_O<105> WL_O<104> WL_O<103> WL_O<102> WL_O<101> ++ WL_O<100> WL_O<99> WL_O<98> WL_O<97> WL_O<96> WL_O<95> WL_O<94> WL_O<93> ++ WL_O<92> WL_O<91> WL_O<90> WL_O<89> WL_O<88> WL_O<87> WL_O<86> WL_O<85> ++ WL_O<84> WL_O<83> WL_O<82> WL_O<81> WL_O<80> WL_O<79> WL_O<78> WL_O<77> ++ WL_O<76> WL_O<75> WL_O<74> WL_O<73> WL_O<72> WL_O<71> WL_O<70> WL_O<69> ++ WL_O<68> WL_O<67> WL_O<66> WL_O<65> WL_O<64> WL_O<63> WL_O<62> WL_O<61> ++ WL_O<60> WL_O<59> WL_O<58> WL_O<57> WL_O<56> WL_O<55> WL_O<54> WL_O<53> ++ WL_O<52> WL_O<51> WL_O<50> WL_O<49> WL_O<48> WL_O<47> WL_O<46> WL_O<45> ++ WL_O<44> WL_O<43> WL_O<42> WL_O<41> WL_O<40> WL_O<39> WL_O<38> WL_O<37> ++ WL_O<36> WL_O<35> WL_O<34> WL_O<33> WL_O<32> WL_O<31> WL_O<30> WL_O<29> ++ WL_O<28> WL_O<27> WL_O<26> WL_O<25> WL_O<24> WL_O<23> WL_O<22> WL_O<21> ++ WL_O<20> WL_O<19> WL_O<18> WL_O<17> WL_O<16> WL_O<15> WL_O<14> WL_O<13> ++ WL_O<12> WL_O<11> WL_O<10> WL_O<9> WL_O<8> WL_O<7> WL_O<6> WL_O<5> WL_O<4> ++ WL_O<3> WL_O<2> WL_O<1> WL_O<0> VDD VSS +XDEC11<4> ADDR_N_I<7> ADDR_N_I<6> CS_I CS04<3> VDD VSS / ++ RM_IHPSG13_512x8_c3_1P_DEC03 +XDEC11<3> ADDR_N_I<5> ADDR_N_I<4> CS04<3> CS00<15> VDD VSS / ++ RM_IHPSG13_512x8_c3_1P_DEC03 +XDEC11<2> ADDR_N_I<5> ADDR_N_I<4> CS04<2> CS00<11> VDD VSS / ++ RM_IHPSG13_512x8_c3_1P_DEC03 +XDEC11<1> ADDR_N_I<5> ADDR_N_I<4> CS04<1> CS00<7> VDD VSS / ++ RM_IHPSG13_512x8_c3_1P_DEC03 +XDEC11<0> ADDR_N_I<5> ADDR_N_I<4> CS04<0> CS00<3> VDD VSS / ++ RM_IHPSG13_512x8_c3_1P_DEC03 +XL2<88> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<87> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<86> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<85> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<84> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<83> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<82> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<81> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<80> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<79> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<78> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<77> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<76> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<75> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<74> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<73> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<72> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<71> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<70> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<69> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<68> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<67> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<66> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<65> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<64> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<63> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<62> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<61> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<60> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<59> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<58> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<57> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<56> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<55> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<54> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<53> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<52> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<51> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<50> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<49> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<48> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<47> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<46> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<45> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<44> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<43> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<42> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<41> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<40> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<39> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<38> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<37> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<36> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<35> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<34> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<33> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<32> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<31> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<30> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<29> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<28> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<27> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<26> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<25> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<24> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<23> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<22> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<21> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<20> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<19> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<18> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<17> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<16> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<15> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<14> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<13> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<12> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<11> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<10> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<9> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<8> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<7> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<6> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<5> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<4> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<3> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<2> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<1> VDD VSS / RSC_IHPSG13_FILLCAP8 +XDEC10<4> ADDR_N_I<7> ADDR_N_I<6> CS_I CS04<2> VDD VSS / ++ RM_IHPSG13_512x8_c3_1P_DEC02 +XDEC10<3> ADDR_N_I<5> ADDR_N_I<4> CS04<3> CS00<14> VDD VSS / ++ RM_IHPSG13_512x8_c3_1P_DEC02 +XDEC10<2> ADDR_N_I<5> ADDR_N_I<4> CS04<2> CS00<10> VDD VSS / ++ RM_IHPSG13_512x8_c3_1P_DEC02 +XDEC10<1> ADDR_N_I<5> ADDR_N_I<4> CS04<1> CS00<6> VDD VSS / ++ RM_IHPSG13_512x8_c3_1P_DEC02 +XDEC10<0> ADDR_N_I<5> ADDR_N_I<4> CS04<0> CS00<2> VDD VSS / ++ RM_IHPSG13_512x8_c3_1P_DEC02 +XDEC00<4> ADDR_N_I<7> ADDR_N_I<6> CS_I CS04<0> VDD VSS / ++ RM_IHPSG13_512x8_c3_1P_DEC00 +XDEC00<3> ADDR_N_I<5> ADDR_N_I<4> CS04<3> CS00<12> VDD VSS / ++ RM_IHPSG13_512x8_c3_1P_DEC00 +XDEC00<2> ADDR_N_I<5> ADDR_N_I<4> CS04<2> CS00<8> VDD VSS / ++ RM_IHPSG13_512x8_c3_1P_DEC00 +XDEC00<1> ADDR_N_I<5> ADDR_N_I<4> CS04<1> CS00<4> VDD VSS / ++ RM_IHPSG13_512x8_c3_1P_DEC00 +XDEC00<0> ADDR_N_I<5> ADDR_N_I<4> CS04<0> CS00<0> VDD VSS / ++ RM_IHPSG13_512x8_c3_1P_DEC00 +XSEL<15> ADDR_N_I<3> ADDR_N_I<2> ADDR_N_I<1> ADDR_N_I<0> CS00<15> ECLK_H<15> ++ ECLK_H<16> ECLK_B<15> ECLK_B<16> WL_O<255> WL_O<254> WL_O<253> WL_O<252> ++ WL_O<251> WL_O<250> WL_O<249> WL_O<248> WL_O<247> WL_O<246> WL_O<245> ++ WL_O<244> WL_O<243> WL_O<242> WL_O<241> WL_O<240> VDD VSS / ++ RM_IHPSG13_512x8_c3_1P_DEC04 +XSEL<14> ADDR_N_I<3> ADDR_N_I<2> ADDR_N_I<1> ADDR_N_I<0> CS00<14> ECLK_H<14> ++ ECLK_H<15> ECLK_B<14> ECLK_B<15> WL_O<239> WL_O<238> WL_O<237> WL_O<236> ++ WL_O<235> WL_O<234> WL_O<233> WL_O<232> WL_O<231> WL_O<230> WL_O<229> ++ WL_O<228> WL_O<227> WL_O<226> WL_O<225> WL_O<224> VDD VSS / ++ RM_IHPSG13_512x8_c3_1P_DEC04 +XSEL<13> ADDR_N_I<3> ADDR_N_I<2> ADDR_N_I<1> ADDR_N_I<0> CS00<13> ECLK_H<13> ++ ECLK_H<14> ECLK_B<13> ECLK_B<14> WL_O<223> WL_O<222> WL_O<221> WL_O<220> ++ WL_O<219> WL_O<218> WL_O<217> WL_O<216> WL_O<215> WL_O<214> WL_O<213> ++ WL_O<212> WL_O<211> WL_O<210> WL_O<209> WL_O<208> VDD VSS / ++ RM_IHPSG13_512x8_c3_1P_DEC04 +XSEL<12> ADDR_N_I<3> ADDR_N_I<2> ADDR_N_I<1> ADDR_N_I<0> CS00<12> ECLK_H<12> ++ ECLK_H<13> ECLK_B<12> ECLK_B<13> WL_O<207> WL_O<206> WL_O<205> WL_O<204> ++ WL_O<203> WL_O<202> WL_O<201> WL_O<200> WL_O<199> WL_O<198> WL_O<197> ++ WL_O<196> WL_O<195> WL_O<194> WL_O<193> WL_O<192> VDD VSS / ++ RM_IHPSG13_512x8_c3_1P_DEC04 +XSEL<11> ADDR_N_I<3> ADDR_N_I<2> ADDR_N_I<1> ADDR_N_I<0> CS00<11> ECLK_H<11> ++ ECLK_H<12> ECLK_B<11> ECLK_B<12> WL_O<191> WL_O<190> WL_O<189> WL_O<188> ++ WL_O<187> WL_O<186> WL_O<185> WL_O<184> WL_O<183> WL_O<182> WL_O<181> ++ WL_O<180> WL_O<179> WL_O<178> WL_O<177> WL_O<176> VDD VSS / ++ RM_IHPSG13_512x8_c3_1P_DEC04 +XSEL<10> ADDR_N_I<3> ADDR_N_I<2> ADDR_N_I<1> ADDR_N_I<0> CS00<10> ECLK_H<10> ++ ECLK_H<11> ECLK_B<10> ECLK_B<11> WL_O<175> WL_O<174> WL_O<173> WL_O<172> ++ WL_O<171> WL_O<170> WL_O<169> WL_O<168> WL_O<167> WL_O<166> WL_O<165> ++ WL_O<164> WL_O<163> WL_O<162> WL_O<161> WL_O<160> VDD VSS / ++ RM_IHPSG13_512x8_c3_1P_DEC04 +XSEL<9> ADDR_N_I<3> ADDR_N_I<2> ADDR_N_I<1> ADDR_N_I<0> CS00<9> ECLK_H<9> ++ ECLK_H<10> ECLK_B<9> ECLK_B<10> WL_O<159> WL_O<158> WL_O<157> WL_O<156> ++ WL_O<155> WL_O<154> WL_O<153> WL_O<152> WL_O<151> WL_O<150> WL_O<149> ++ WL_O<148> WL_O<147> WL_O<146> WL_O<145> WL_O<144> VDD VSS / ++ RM_IHPSG13_512x8_c3_1P_DEC04 +XSEL<8> ADDR_N_I<3> ADDR_N_I<2> ADDR_N_I<1> ADDR_N_I<0> CS00<8> ECLK_H<8> ++ ECLK_H<9> ECLK_B<8> ECLK_B<9> WL_O<143> WL_O<142> WL_O<141> WL_O<140> ++ WL_O<139> WL_O<138> WL_O<137> WL_O<136> WL_O<135> WL_O<134> WL_O<133> ++ WL_O<132> WL_O<131> WL_O<130> WL_O<129> WL_O<128> VDD VSS / ++ RM_IHPSG13_512x8_c3_1P_DEC04 +XSEL<7> ADDR_N_I<3> ADDR_N_I<2> ADDR_N_I<1> ADDR_N_I<0> CS00<7> ECLK_H<7> ++ ECLK_H<8> ECLK_B<7> ECLK_B<8> WL_O<127> WL_O<126> WL_O<125> WL_O<124> ++ WL_O<123> WL_O<122> WL_O<121> WL_O<120> WL_O<119> WL_O<118> WL_O<117> ++ WL_O<116> WL_O<115> WL_O<114> WL_O<113> WL_O<112> VDD VSS / ++ RM_IHPSG13_512x8_c3_1P_DEC04 +XSEL<6> ADDR_N_I<3> ADDR_N_I<2> ADDR_N_I<1> ADDR_N_I<0> CS00<6> ECLK_H<6> ++ ECLK_H<7> ECLK_B<6> ECLK_B<7> WL_O<111> WL_O<110> WL_O<109> WL_O<108> ++ WL_O<107> WL_O<106> WL_O<105> WL_O<104> WL_O<103> WL_O<102> WL_O<101> ++ WL_O<100> WL_O<99> WL_O<98> WL_O<97> WL_O<96> VDD VSS / ++ RM_IHPSG13_512x8_c3_1P_DEC04 +XSEL<5> ADDR_N_I<3> ADDR_N_I<2> ADDR_N_I<1> ADDR_N_I<0> CS00<5> ECLK_H<5> ++ ECLK_H<6> ECLK_B<5> ECLK_B<6> WL_O<95> WL_O<94> WL_O<93> WL_O<92> WL_O<91> ++ WL_O<90> WL_O<89> WL_O<88> WL_O<87> WL_O<86> WL_O<85> WL_O<84> WL_O<83> ++ WL_O<82> WL_O<81> WL_O<80> VDD VSS / RM_IHPSG13_512x8_c3_1P_DEC04 +XSEL<4> ADDR_N_I<3> ADDR_N_I<2> ADDR_N_I<1> ADDR_N_I<0> CS00<4> ECLK_H<4> ++ ECLK_H<5> ECLK_B<4> ECLK_B<5> WL_O<79> WL_O<78> WL_O<77> WL_O<76> WL_O<75> ++ WL_O<74> WL_O<73> WL_O<72> WL_O<71> WL_O<70> WL_O<69> WL_O<68> WL_O<67> ++ WL_O<66> WL_O<65> WL_O<64> VDD VSS / RM_IHPSG13_512x8_c3_1P_DEC04 +XSEL<3> ADDR_N_I<3> ADDR_N_I<2> ADDR_N_I<1> ADDR_N_I<0> CS00<3> ECLK_H<3> ++ ECLK_H<4> ECLK_B<3> ECLK_B<4> WL_O<63> WL_O<62> WL_O<61> WL_O<60> WL_O<59> ++ WL_O<58> WL_O<57> WL_O<56> WL_O<55> WL_O<54> WL_O<53> WL_O<52> WL_O<51> ++ WL_O<50> WL_O<49> WL_O<48> VDD VSS / RM_IHPSG13_512x8_c3_1P_DEC04 +XSEL<2> ADDR_N_I<3> ADDR_N_I<2> ADDR_N_I<1> ADDR_N_I<0> CS00<2> ECLK_H<2> ++ ECLK_H<3> ECLK_B<2> ECLK_B<3> WL_O<47> WL_O<46> WL_O<45> WL_O<44> WL_O<43> ++ WL_O<42> WL_O<41> WL_O<40> WL_O<39> WL_O<38> WL_O<37> WL_O<36> WL_O<35> ++ WL_O<34> WL_O<33> WL_O<32> VDD VSS / RM_IHPSG13_512x8_c3_1P_DEC04 +XSEL<1> ADDR_N_I<3> ADDR_N_I<2> ADDR_N_I<1> ADDR_N_I<0> CS00<1> ECLK_H<1> ++ ECLK_H<2> ECLK_B<1> ECLK_B<2> WL_O<31> WL_O<30> WL_O<29> WL_O<28> WL_O<27> ++ WL_O<26> WL_O<25> WL_O<24> WL_O<23> WL_O<22> WL_O<21> WL_O<20> WL_O<19> ++ WL_O<18> WL_O<17> WL_O<16> VDD VSS / RM_IHPSG13_512x8_c3_1P_DEC04 +XSEL<0> ADDR_N_I<3> ADDR_N_I<2> ADDR_N_I<1> ADDR_N_I<0> CS00<0> ECLK_I ++ ECLK_H<1> ECLK_B<0> ECLK_B<1> WL_O<15> WL_O<14> WL_O<13> WL_O<12> WL_O<11> ++ WL_O<10> WL_O<9> WL_O<8> WL_O<7> WL_O<6> WL_O<5> WL_O<4> WL_O<3> WL_O<2> ++ WL_O<1> WL_O<0> VDD VSS / RM_IHPSG13_512x8_c3_1P_DEC04 +XDEC01<4> ADDR_N_I<7> ADDR_N_I<6> CS_I CS04<1> VDD VSS / ++ RM_IHPSG13_512x8_c3_1P_DEC01 +XDEC01<3> ADDR_N_I<5> ADDR_N_I<4> CS04<3> CS00<13> VDD VSS / ++ RM_IHPSG13_512x8_c3_1P_DEC01 +XDEC01<2> ADDR_N_I<5> ADDR_N_I<4> CS04<2> CS00<9> VDD VSS / ++ RM_IHPSG13_512x8_c3_1P_DEC01 +XDEC01<1> ADDR_N_I<5> ADDR_N_I<4> CS04<1> CS00<5> VDD VSS / ++ RM_IHPSG13_512x8_c3_1P_DEC01 +XDEC01<0> ADDR_N_I<5> ADDR_N_I<4> CS04<0> CS00<1> VDD VSS / ++ RM_IHPSG13_512x8_c3_1P_DEC01 +.ENDS +.SUBCKT RM_IHPSG13_512x8_c3_1P_ROWREG8 ACLK_N_I ADDR_I<7> ADDR_I<6> ADDR_I<5> ADDR_I<4> ++ ADDR_I<3> ADDR_I<2> ADDR_I<1> ADDR_I<0> ADDR_N_O<7> ADDR_N_O<6> ADDR_N_O<5> ++ ADDR_N_O<4> ADDR_N_O<3> ADDR_N_O<2> ADDR_N_O<1> ADDR_N_O<0> BIST_ADDR_I<7> ++ BIST_ADDR_I<6> BIST_ADDR_I<5> BIST_ADDR_I<4> BIST_ADDR_I<3> BIST_ADDR_I<2> ++ BIST_ADDR_I<1> BIST_ADDR_I<0> BIST_EN_I VDD VSS +XINV<7> q_int<7> qn_int<7> VDD VSS / RSC_IHPSG13_CINVX2 +XINV<6> q_int<6> qn_int<6> VDD VSS / RSC_IHPSG13_CINVX2 +XINV<5> q_int<5> qn_int<5> VDD VSS / RSC_IHPSG13_CINVX2 +XINV<4> q_int<4> qn_int<4> VDD VSS / RSC_IHPSG13_CINVX2 +XINV<3> q_int<3> qn_int<3> VDD VSS / RSC_IHPSG13_CINVX2 +XINV<2> q_int<2> qn_int<2> VDD VSS / RSC_IHPSG13_CINVX2 +XINV<1> q_int<1> qn_int<1> VDD VSS / RSC_IHPSG13_CINVX2 +XINV<0> q_int<0> qn_int<0> VDD VSS / RSC_IHPSG13_CINVX2 +XDRV<7> qn_int<7> ADDR_N_O<7> VDD VSS / RSC_IHPSG13_CINVX8 +XDRV<6> qn_int<6> ADDR_N_O<6> VDD VSS / RSC_IHPSG13_CINVX8 +XDRV<5> qn_int<5> ADDR_N_O<5> VDD VSS / RSC_IHPSG13_CINVX8 +XDRV<4> qn_int<4> ADDR_N_O<4> VDD VSS / RSC_IHPSG13_CINVX8 +XDRV<3> qn_int<3> ADDR_N_O<3> VDD VSS / RSC_IHPSG13_CINVX8 +XDRV<2> qn_int<2> ADDR_N_O<2> VDD VSS / RSC_IHPSG13_CINVX8 +XDRV<1> qn_int<1> ADDR_N_O<1> VDD VSS / RSC_IHPSG13_CINVX8 +XDRV<0> qn_int<0> ADDR_N_O<0> VDD VSS / RSC_IHPSG13_CINVX8 +XDFF<7> BIST_EN_I BIST_ADDR_I<7> ACLK_N_I ADDR_I<7> q_int<7> net2<0> VDD ++ VSS / RSC_IHPSG13_DFNQMX2IX1 +XDFF<6> BIST_EN_I BIST_ADDR_I<6> ACLK_N_I ADDR_I<6> q_int<6> net2<1> VDD ++ VSS / RSC_IHPSG13_DFNQMX2IX1 +XDFF<5> BIST_EN_I BIST_ADDR_I<5> ACLK_N_I ADDR_I<5> q_int<5> net2<2> VDD ++ VSS / RSC_IHPSG13_DFNQMX2IX1 +XDFF<4> BIST_EN_I BIST_ADDR_I<4> ACLK_N_I ADDR_I<4> q_int<4> net2<3> VDD ++ VSS / RSC_IHPSG13_DFNQMX2IX1 +XDFF<3> BIST_EN_I BIST_ADDR_I<3> ACLK_N_I ADDR_I<3> q_int<3> net2<4> VDD ++ VSS / RSC_IHPSG13_DFNQMX2IX1 +XDFF<2> BIST_EN_I BIST_ADDR_I<2> ACLK_N_I ADDR_I<2> q_int<2> net2<5> VDD ++ VSS / RSC_IHPSG13_DFNQMX2IX1 +XDFF<1> BIST_EN_I BIST_ADDR_I<1> ACLK_N_I ADDR_I<1> q_int<1> net2<6> VDD ++ VSS / RSC_IHPSG13_DFNQMX2IX1 +XDFF<0> BIST_EN_I BIST_ADDR_I<0> ACLK_N_I ADDR_I<0> q_int<0> net2<7> VDD ++ VSS / RSC_IHPSG13_DFNQMX2IX1 +XI11<4> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI11<3> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI11<2> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI11<1> VDD VSS / RSC_IHPSG13_FILLCAP8 +.ENDS + +.SUBCKT RM_IHPSG13_512x8_c3_1P_ROWDEC9 ADDR_N_I<8> ADDR_N_I<7> ADDR_N_I<6> ADDR_N_I<5> ++ ADDR_N_I<4> ADDR_N_I<3> ADDR_N_I<2> ADDR_N_I<1> ADDR_N_I<0> CS_I ECLK_I ++ WL_O<511> WL_O<510> WL_O<509> WL_O<508> WL_O<507> WL_O<506> WL_O<505> ++ WL_O<504> WL_O<503> WL_O<502> WL_O<501> WL_O<500> WL_O<499> WL_O<498> ++ WL_O<497> WL_O<496> WL_O<495> WL_O<494> WL_O<493> WL_O<492> WL_O<491> ++ WL_O<490> WL_O<489> WL_O<488> WL_O<487> WL_O<486> WL_O<485> WL_O<484> ++ WL_O<483> WL_O<482> WL_O<481> WL_O<480> WL_O<479> WL_O<478> WL_O<477> ++ WL_O<476> WL_O<475> WL_O<474> WL_O<473> WL_O<472> WL_O<471> WL_O<470> ++ WL_O<469> WL_O<468> WL_O<467> WL_O<466> WL_O<465> WL_O<464> WL_O<463> ++ WL_O<462> WL_O<461> WL_O<460> WL_O<459> WL_O<458> WL_O<457> WL_O<456> ++ WL_O<455> WL_O<454> WL_O<453> WL_O<452> WL_O<451> WL_O<450> WL_O<449> ++ WL_O<448> WL_O<447> WL_O<446> WL_O<445> WL_O<444> WL_O<443> WL_O<442> ++ WL_O<441> WL_O<440> WL_O<439> WL_O<438> WL_O<437> WL_O<436> WL_O<435> ++ WL_O<434> WL_O<433> WL_O<432> WL_O<431> WL_O<430> WL_O<429> WL_O<428> ++ WL_O<427> WL_O<426> WL_O<425> WL_O<424> WL_O<423> WL_O<422> WL_O<421> ++ WL_O<420> WL_O<419> WL_O<418> WL_O<417> WL_O<416> WL_O<415> WL_O<414> ++ WL_O<413> WL_O<412> WL_O<411> WL_O<410> WL_O<409> WL_O<408> WL_O<407> ++ WL_O<406> WL_O<405> WL_O<404> WL_O<403> WL_O<402> WL_O<401> WL_O<400> ++ WL_O<399> WL_O<398> WL_O<397> WL_O<396> WL_O<395> WL_O<394> WL_O<393> ++ WL_O<392> WL_O<391> WL_O<390> WL_O<389> WL_O<388> WL_O<387> WL_O<386> ++ WL_O<385> WL_O<384> WL_O<383> WL_O<382> WL_O<381> WL_O<380> WL_O<379> ++ WL_O<378> WL_O<377> WL_O<376> WL_O<375> WL_O<374> WL_O<373> WL_O<372> ++ WL_O<371> WL_O<370> WL_O<369> WL_O<368> WL_O<367> WL_O<366> WL_O<365> ++ WL_O<364> WL_O<363> WL_O<362> WL_O<361> WL_O<360> WL_O<359> WL_O<358> ++ WL_O<357> WL_O<356> WL_O<355> WL_O<354> WL_O<353> WL_O<352> WL_O<351> ++ WL_O<350> WL_O<349> WL_O<348> WL_O<347> WL_O<346> WL_O<345> WL_O<344> ++ WL_O<343> WL_O<342> WL_O<341> WL_O<340> WL_O<339> WL_O<338> WL_O<337> ++ WL_O<336> WL_O<335> WL_O<334> WL_O<333> WL_O<332> WL_O<331> WL_O<330> ++ WL_O<329> WL_O<328> WL_O<327> WL_O<326> WL_O<325> WL_O<324> WL_O<323> ++ WL_O<322> WL_O<321> WL_O<320> WL_O<319> WL_O<318> WL_O<317> WL_O<316> ++ WL_O<315> WL_O<314> WL_O<313> WL_O<312> WL_O<311> WL_O<310> WL_O<309> ++ WL_O<308> WL_O<307> WL_O<306> WL_O<305> WL_O<304> WL_O<303> WL_O<302> ++ WL_O<301> WL_O<300> WL_O<299> WL_O<298> WL_O<297> WL_O<296> WL_O<295> ++ WL_O<294> WL_O<293> WL_O<292> WL_O<291> WL_O<290> WL_O<289> WL_O<288> ++ WL_O<287> WL_O<286> WL_O<285> WL_O<284> WL_O<283> WL_O<282> WL_O<281> ++ WL_O<280> WL_O<279> WL_O<278> WL_O<277> WL_O<276> WL_O<275> WL_O<274> ++ WL_O<273> WL_O<272> WL_O<271> WL_O<270> WL_O<269> WL_O<268> WL_O<267> ++ WL_O<266> WL_O<265> WL_O<264> WL_O<263> WL_O<262> WL_O<261> WL_O<260> ++ WL_O<259> WL_O<258> WL_O<257> WL_O<256> WL_O<255> WL_O<254> WL_O<253> ++ WL_O<252> WL_O<251> WL_O<250> WL_O<249> WL_O<248> WL_O<247> WL_O<246> ++ WL_O<245> WL_O<244> WL_O<243> WL_O<242> WL_O<241> WL_O<240> WL_O<239> ++ WL_O<238> WL_O<237> WL_O<236> WL_O<235> WL_O<234> WL_O<233> WL_O<232> ++ WL_O<231> WL_O<230> WL_O<229> WL_O<228> WL_O<227> WL_O<226> WL_O<225> ++ WL_O<224> WL_O<223> WL_O<222> WL_O<221> WL_O<220> WL_O<219> WL_O<218> ++ WL_O<217> WL_O<216> WL_O<215> WL_O<214> WL_O<213> WL_O<212> WL_O<211> ++ WL_O<210> WL_O<209> WL_O<208> WL_O<207> WL_O<206> WL_O<205> WL_O<204> ++ WL_O<203> WL_O<202> WL_O<201> WL_O<200> WL_O<199> WL_O<198> WL_O<197> ++ WL_O<196> WL_O<195> WL_O<194> WL_O<193> WL_O<192> WL_O<191> WL_O<190> ++ WL_O<189> WL_O<188> WL_O<187> WL_O<186> WL_O<185> WL_O<184> WL_O<183> ++ WL_O<182> WL_O<181> WL_O<180> WL_O<179> WL_O<178> WL_O<177> WL_O<176> ++ WL_O<175> WL_O<174> WL_O<173> WL_O<172> WL_O<171> WL_O<170> WL_O<169> ++ WL_O<168> WL_O<167> WL_O<166> WL_O<165> WL_O<164> WL_O<163> WL_O<162> ++ WL_O<161> WL_O<160> WL_O<159> WL_O<158> WL_O<157> WL_O<156> WL_O<155> ++ WL_O<154> WL_O<153> WL_O<152> WL_O<151> WL_O<150> WL_O<149> WL_O<148> ++ WL_O<147> WL_O<146> WL_O<145> WL_O<144> WL_O<143> WL_O<142> WL_O<141> ++ WL_O<140> WL_O<139> WL_O<138> WL_O<137> WL_O<136> WL_O<135> WL_O<134> ++ WL_O<133> WL_O<132> WL_O<131> WL_O<130> WL_O<129> WL_O<128> WL_O<127> ++ WL_O<126> WL_O<125> WL_O<124> WL_O<123> WL_O<122> WL_O<121> WL_O<120> ++ WL_O<119> WL_O<118> WL_O<117> WL_O<116> WL_O<115> WL_O<114> WL_O<113> ++ WL_O<112> WL_O<111> WL_O<110> WL_O<109> WL_O<108> WL_O<107> WL_O<106> ++ WL_O<105> WL_O<104> WL_O<103> WL_O<102> WL_O<101> WL_O<100> WL_O<99> ++ WL_O<98> WL_O<97> WL_O<96> WL_O<95> WL_O<94> WL_O<93> WL_O<92> WL_O<91> ++ WL_O<90> WL_O<89> WL_O<88> WL_O<87> WL_O<86> WL_O<85> WL_O<84> WL_O<83> ++ WL_O<82> WL_O<81> WL_O<80> WL_O<79> WL_O<78> WL_O<77> WL_O<76> WL_O<75> ++ WL_O<74> WL_O<73> WL_O<72> WL_O<71> WL_O<70> WL_O<69> WL_O<68> WL_O<67> ++ WL_O<66> WL_O<65> WL_O<64> WL_O<63> WL_O<62> WL_O<61> WL_O<60> WL_O<59> ++ WL_O<58> WL_O<57> WL_O<56> WL_O<55> WL_O<54> WL_O<53> WL_O<52> WL_O<51> ++ WL_O<50> WL_O<49> WL_O<48> WL_O<47> WL_O<46> WL_O<45> WL_O<44> WL_O<43> ++ WL_O<42> WL_O<41> WL_O<40> WL_O<39> WL_O<38> WL_O<37> WL_O<36> WL_O<35> ++ WL_O<34> WL_O<33> WL_O<32> WL_O<31> WL_O<30> WL_O<29> WL_O<28> WL_O<27> ++ WL_O<26> WL_O<25> WL_O<24> WL_O<23> WL_O<22> WL_O<21> WL_O<20> WL_O<19> ++ WL_O<18> WL_O<17> WL_O<16> WL_O<15> WL_O<14> WL_O<13> WL_O<12> WL_O<11> ++ WL_O<10> WL_O<9> WL_O<8> WL_O<7> WL_O<6> WL_O<5> WL_O<4> WL_O<3> WL_O<2> ++ WL_O<1> WL_O<0> VDD VSS +XL2<172> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<171> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<170> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<169> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<168> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<167> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<166> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<165> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<164> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<163> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<162> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<161> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<160> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<159> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<158> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<157> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<156> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<155> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<154> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<153> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<152> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<151> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<150> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<149> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<148> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<147> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<146> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<145> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<144> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<143> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<142> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<141> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<140> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<139> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<138> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<137> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<136> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<135> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<134> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<133> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<132> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<131> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<130> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<129> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<128> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<127> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<126> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<125> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<124> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<123> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<122> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<121> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<120> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<119> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<118> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<117> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<116> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<115> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<114> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<113> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<112> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<111> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<110> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<109> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<108> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<107> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<106> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<105> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<104> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<103> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<102> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<101> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<100> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<99> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<98> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<97> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<96> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<95> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<94> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<93> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<92> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<91> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<90> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<89> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<88> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<87> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<86> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<85> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<84> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<83> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<82> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<81> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<80> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<79> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<78> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<77> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<76> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<75> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<74> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<73> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<72> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<71> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<70> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<69> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<68> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<67> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<66> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<65> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<64> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<63> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<62> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<61> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<60> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<59> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<58> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<57> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<56> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<55> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<54> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<53> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<52> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<51> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<50> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<49> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<48> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<47> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<46> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<45> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<44> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<43> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<42> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<41> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<40> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<39> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<38> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<37> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<36> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<35> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<34> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<33> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<32> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<31> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<30> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<29> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<28> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<27> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<26> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<25> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<24> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<23> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<22> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<21> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<20> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<19> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<18> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<17> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<16> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<15> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<14> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<13> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<12> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<11> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<10> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<9> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<8> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<7> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<6> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<5> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<4> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<3> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<2> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<1> VDD VSS / RSC_IHPSG13_FILLCAP8 +XDEC11<9> ADDR_N_I<7> ADDR_N_I<6> CS04<1> CS02<7> VDD VSS / ++ RM_IHPSG13_512x8_c3_1P_DEC03 +XDEC11<8> ADDR_N_I<7> ADDR_N_I<6> CS04<0> CS02<3> VDD VSS / ++ RM_IHPSG13_512x8_c3_1P_DEC03 +XDEC11<7> ADDR_N_I<5> ADDR_N_I<4> CS02<7> CS00<31> VDD VSS / ++ RM_IHPSG13_512x8_c3_1P_DEC03 +XDEC11<6> ADDR_N_I<5> ADDR_N_I<4> CS02<6> CS00<27> VDD VSS / ++ RM_IHPSG13_512x8_c3_1P_DEC03 +XDEC11<5> ADDR_N_I<5> ADDR_N_I<4> CS02<5> CS00<23> VDD VSS / ++ RM_IHPSG13_512x8_c3_1P_DEC03 +XDEC11<4> ADDR_N_I<5> ADDR_N_I<4> CS02<4> CS00<19> VDD VSS / ++ RM_IHPSG13_512x8_c3_1P_DEC03 +XDEC11<3> ADDR_N_I<5> ADDR_N_I<4> CS02<3> CS00<15> VDD VSS / ++ RM_IHPSG13_512x8_c3_1P_DEC03 +XDEC11<2> ADDR_N_I<5> ADDR_N_I<4> CS02<2> CS00<11> VDD VSS / ++ RM_IHPSG13_512x8_c3_1P_DEC03 +XDEC11<1> ADDR_N_I<5> ADDR_N_I<4> CS02<1> CS00<7> VDD VSS / ++ RM_IHPSG13_512x8_c3_1P_DEC03 +XDEC11<0> ADDR_N_I<5> ADDR_N_I<4> CS02<0> CS00<3> VDD VSS / ++ RM_IHPSG13_512x8_c3_1P_DEC03 +XDEC00<10> ADDR_N_I<9> ADDR_N_I<8> CS_I CS04<0> VDD VSS / ++ RM_IHPSG13_512x8_c3_1P_DEC00 +XDEC00<9> ADDR_N_I<7> ADDR_N_I<6> CS04<1> CS02<4> VDD VSS / ++ RM_IHPSG13_512x8_c3_1P_DEC00 +XDEC00<8> ADDR_N_I<7> ADDR_N_I<6> CS04<0> CS02<0> VDD VSS / ++ RM_IHPSG13_512x8_c3_1P_DEC00 +XDEC00<7> ADDR_N_I<5> ADDR_N_I<4> CS02<7> CS00<28> VDD VSS / ++ RM_IHPSG13_512x8_c3_1P_DEC00 +XDEC00<6> ADDR_N_I<5> ADDR_N_I<4> CS02<6> CS00<24> VDD VSS / ++ RM_IHPSG13_512x8_c3_1P_DEC00 +XDEC00<5> ADDR_N_I<5> ADDR_N_I<4> CS02<5> CS00<20> VDD VSS / ++ RM_IHPSG13_512x8_c3_1P_DEC00 +XDEC00<4> ADDR_N_I<5> ADDR_N_I<4> CS02<4> CS00<16> VDD VSS / ++ RM_IHPSG13_512x8_c3_1P_DEC00 +XDEC00<3> ADDR_N_I<5> ADDR_N_I<4> CS02<3> CS00<12> VDD VSS / ++ RM_IHPSG13_512x8_c3_1P_DEC00 +XDEC00<2> ADDR_N_I<5> ADDR_N_I<4> CS02<2> CS00<8> VDD VSS / ++ RM_IHPSG13_512x8_c3_1P_DEC00 +XDEC00<1> ADDR_N_I<5> ADDR_N_I<4> CS02<1> CS00<4> VDD VSS / ++ RM_IHPSG13_512x8_c3_1P_DEC00 +XDEC00<0> ADDR_N_I<5> ADDR_N_I<4> CS02<0> CS00<0> VDD VSS / ++ RM_IHPSG13_512x8_c3_1P_DEC00 +XSEL<31> ADDR_N_I<3> ADDR_N_I<2> ADDR_N_I<1> ADDR_N_I<0> CS00<31> ECLK_H<31> ++ ECLK_H<32> ECLK_B<31> ECLK_B<32> WL_O<511> WL_O<510> WL_O<509> WL_O<508> ++ WL_O<507> WL_O<506> WL_O<505> WL_O<504> WL_O<503> WL_O<502> WL_O<501> ++ WL_O<500> WL_O<499> WL_O<498> WL_O<497> WL_O<496> VDD VSS / ++ RM_IHPSG13_512x8_c3_1P_DEC04 +XSEL<30> ADDR_N_I<3> ADDR_N_I<2> ADDR_N_I<1> ADDR_N_I<0> CS00<30> ECLK_H<30> ++ ECLK_H<31> ECLK_B<30> ECLK_B<31> WL_O<495> WL_O<494> WL_O<493> WL_O<492> ++ WL_O<491> WL_O<490> WL_O<489> WL_O<488> WL_O<487> WL_O<486> WL_O<485> ++ WL_O<484> WL_O<483> WL_O<482> WL_O<481> WL_O<480> VDD VSS / ++ RM_IHPSG13_512x8_c3_1P_DEC04 +XSEL<29> ADDR_N_I<3> ADDR_N_I<2> ADDR_N_I<1> ADDR_N_I<0> CS00<29> ECLK_H<29> ++ ECLK_H<30> ECLK_B<29> ECLK_B<30> WL_O<479> WL_O<478> WL_O<477> WL_O<476> ++ WL_O<475> WL_O<474> WL_O<473> WL_O<472> WL_O<471> WL_O<470> WL_O<469> ++ WL_O<468> WL_O<467> WL_O<466> WL_O<465> WL_O<464> VDD VSS / ++ RM_IHPSG13_512x8_c3_1P_DEC04 +XSEL<28> ADDR_N_I<3> ADDR_N_I<2> ADDR_N_I<1> ADDR_N_I<0> CS00<28> ECLK_H<28> ++ ECLK_H<29> ECLK_B<28> ECLK_B<29> WL_O<463> WL_O<462> WL_O<461> WL_O<460> ++ WL_O<459> WL_O<458> WL_O<457> WL_O<456> WL_O<455> WL_O<454> WL_O<453> ++ WL_O<452> WL_O<451> WL_O<450> WL_O<449> WL_O<448> VDD VSS / ++ RM_IHPSG13_512x8_c3_1P_DEC04 +XSEL<27> ADDR_N_I<3> ADDR_N_I<2> ADDR_N_I<1> ADDR_N_I<0> CS00<27> ECLK_H<27> ++ ECLK_H<28> ECLK_B<27> ECLK_B<28> WL_O<447> WL_O<446> WL_O<445> WL_O<444> ++ WL_O<443> WL_O<442> WL_O<441> WL_O<440> WL_O<439> WL_O<438> WL_O<437> ++ WL_O<436> WL_O<435> WL_O<434> WL_O<433> WL_O<432> VDD VSS / ++ RM_IHPSG13_512x8_c3_1P_DEC04 +XSEL<26> ADDR_N_I<3> ADDR_N_I<2> ADDR_N_I<1> ADDR_N_I<0> CS00<26> ECLK_H<26> ++ ECLK_H<27> ECLK_B<26> ECLK_B<27> WL_O<431> WL_O<430> WL_O<429> WL_O<428> ++ WL_O<427> WL_O<426> WL_O<425> WL_O<424> WL_O<423> WL_O<422> WL_O<421> ++ WL_O<420> WL_O<419> WL_O<418> WL_O<417> WL_O<416> VDD VSS / ++ RM_IHPSG13_512x8_c3_1P_DEC04 +XSEL<25> ADDR_N_I<3> ADDR_N_I<2> ADDR_N_I<1> ADDR_N_I<0> CS00<25> ECLK_H<25> ++ ECLK_H<26> ECLK_B<25> ECLK_B<26> WL_O<415> WL_O<414> WL_O<413> WL_O<412> ++ WL_O<411> WL_O<410> WL_O<409> WL_O<408> WL_O<407> WL_O<406> WL_O<405> ++ WL_O<404> WL_O<403> WL_O<402> WL_O<401> WL_O<400> VDD VSS / ++ RM_IHPSG13_512x8_c3_1P_DEC04 +XSEL<24> ADDR_N_I<3> ADDR_N_I<2> ADDR_N_I<1> ADDR_N_I<0> CS00<24> ECLK_H<24> ++ ECLK_H<25> ECLK_B<24> ECLK_B<25> WL_O<399> WL_O<398> WL_O<397> WL_O<396> ++ WL_O<395> WL_O<394> WL_O<393> WL_O<392> WL_O<391> WL_O<390> WL_O<389> ++ WL_O<388> WL_O<387> WL_O<386> WL_O<385> WL_O<384> VDD VSS / ++ RM_IHPSG13_512x8_c3_1P_DEC04 +XSEL<23> ADDR_N_I<3> ADDR_N_I<2> ADDR_N_I<1> ADDR_N_I<0> CS00<23> ECLK_H<23> ++ ECLK_H<24> ECLK_B<23> ECLK_B<24> WL_O<383> WL_O<382> WL_O<381> WL_O<380> ++ WL_O<379> WL_O<378> WL_O<377> WL_O<376> WL_O<375> WL_O<374> WL_O<373> ++ WL_O<372> WL_O<371> WL_O<370> WL_O<369> WL_O<368> VDD VSS / ++ RM_IHPSG13_512x8_c3_1P_DEC04 +XSEL<22> ADDR_N_I<3> ADDR_N_I<2> ADDR_N_I<1> ADDR_N_I<0> CS00<22> ECLK_H<22> ++ ECLK_H<23> ECLK_B<22> ECLK_B<23> WL_O<367> WL_O<366> WL_O<365> WL_O<364> ++ WL_O<363> WL_O<362> WL_O<361> WL_O<360> WL_O<359> WL_O<358> WL_O<357> ++ WL_O<356> WL_O<355> WL_O<354> WL_O<353> WL_O<352> VDD VSS / ++ RM_IHPSG13_512x8_c3_1P_DEC04 +XSEL<21> ADDR_N_I<3> ADDR_N_I<2> ADDR_N_I<1> ADDR_N_I<0> CS00<21> ECLK_H<21> ++ ECLK_H<22> ECLK_B<21> ECLK_B<22> WL_O<351> WL_O<350> WL_O<349> WL_O<348> ++ WL_O<347> WL_O<346> WL_O<345> WL_O<344> WL_O<343> WL_O<342> WL_O<341> ++ WL_O<340> WL_O<339> WL_O<338> WL_O<337> WL_O<336> VDD VSS / ++ RM_IHPSG13_512x8_c3_1P_DEC04 +XSEL<20> ADDR_N_I<3> ADDR_N_I<2> ADDR_N_I<1> ADDR_N_I<0> CS00<20> ECLK_H<20> ++ ECLK_H<21> ECLK_B<20> ECLK_B<21> WL_O<335> WL_O<334> WL_O<333> WL_O<332> ++ WL_O<331> WL_O<330> WL_O<329> WL_O<328> WL_O<327> WL_O<326> WL_O<325> ++ WL_O<324> WL_O<323> WL_O<322> WL_O<321> WL_O<320> VDD VSS / ++ RM_IHPSG13_512x8_c3_1P_DEC04 +XSEL<19> ADDR_N_I<3> ADDR_N_I<2> ADDR_N_I<1> ADDR_N_I<0> CS00<19> ECLK_H<19> ++ ECLK_H<20> ECLK_B<19> ECLK_B<20> WL_O<319> WL_O<318> WL_O<317> WL_O<316> ++ WL_O<315> WL_O<314> WL_O<313> WL_O<312> WL_O<311> WL_O<310> WL_O<309> ++ WL_O<308> WL_O<307> WL_O<306> WL_O<305> WL_O<304> VDD VSS / ++ RM_IHPSG13_512x8_c3_1P_DEC04 +XSEL<18> ADDR_N_I<3> ADDR_N_I<2> ADDR_N_I<1> ADDR_N_I<0> CS00<18> ECLK_H<18> ++ ECLK_H<19> ECLK_B<18> ECLK_B<19> WL_O<303> WL_O<302> WL_O<301> WL_O<300> ++ WL_O<299> WL_O<298> WL_O<297> WL_O<296> WL_O<295> WL_O<294> WL_O<293> ++ WL_O<292> WL_O<291> WL_O<290> WL_O<289> WL_O<288> VDD VSS / ++ RM_IHPSG13_512x8_c3_1P_DEC04 +XSEL<17> ADDR_N_I<3> ADDR_N_I<2> ADDR_N_I<1> ADDR_N_I<0> CS00<17> ECLK_H<17> ++ ECLK_H<18> ECLK_B<17> ECLK_B<18> WL_O<287> WL_O<286> WL_O<285> WL_O<284> ++ WL_O<283> WL_O<282> WL_O<281> WL_O<280> WL_O<279> WL_O<278> WL_O<277> ++ WL_O<276> WL_O<275> WL_O<274> WL_O<273> WL_O<272> VDD VSS / ++ RM_IHPSG13_512x8_c3_1P_DEC04 +XSEL<16> ADDR_N_I<3> ADDR_N_I<2> ADDR_N_I<1> ADDR_N_I<0> CS00<16> ECLK_H<16> ++ ECLK_H<17> ECLK_B<16> ECLK_B<17> WL_O<271> WL_O<270> WL_O<269> WL_O<268> ++ WL_O<267> WL_O<266> WL_O<265> WL_O<264> WL_O<263> WL_O<262> WL_O<261> ++ WL_O<260> WL_O<259> WL_O<258> WL_O<257> WL_O<256> VDD VSS / ++ RM_IHPSG13_512x8_c3_1P_DEC04 +XSEL<15> ADDR_N_I<3> ADDR_N_I<2> ADDR_N_I<1> ADDR_N_I<0> CS00<15> ECLK_H<15> ++ ECLK_H<16> ECLK_B<15> ECLK_B<16> WL_O<255> WL_O<254> WL_O<253> WL_O<252> ++ WL_O<251> WL_O<250> WL_O<249> WL_O<248> WL_O<247> WL_O<246> WL_O<245> ++ WL_O<244> WL_O<243> WL_O<242> WL_O<241> WL_O<240> VDD VSS / ++ RM_IHPSG13_512x8_c3_1P_DEC04 +XSEL<14> ADDR_N_I<3> ADDR_N_I<2> ADDR_N_I<1> ADDR_N_I<0> CS00<14> ECLK_H<14> ++ ECLK_H<15> ECLK_B<14> ECLK_B<15> WL_O<239> WL_O<238> WL_O<237> WL_O<236> ++ WL_O<235> WL_O<234> WL_O<233> WL_O<232> WL_O<231> WL_O<230> WL_O<229> ++ WL_O<228> WL_O<227> WL_O<226> WL_O<225> WL_O<224> VDD VSS / ++ RM_IHPSG13_512x8_c3_1P_DEC04 +XSEL<13> ADDR_N_I<3> ADDR_N_I<2> ADDR_N_I<1> ADDR_N_I<0> CS00<13> ECLK_H<13> ++ ECLK_H<14> ECLK_B<13> ECLK_B<14> WL_O<223> WL_O<222> WL_O<221> WL_O<220> ++ WL_O<219> WL_O<218> WL_O<217> WL_O<216> WL_O<215> WL_O<214> WL_O<213> ++ WL_O<212> WL_O<211> WL_O<210> WL_O<209> WL_O<208> VDD VSS / ++ RM_IHPSG13_512x8_c3_1P_DEC04 +XSEL<12> ADDR_N_I<3> ADDR_N_I<2> ADDR_N_I<1> ADDR_N_I<0> CS00<12> ECLK_H<12> ++ ECLK_H<13> ECLK_B<12> ECLK_B<13> WL_O<207> WL_O<206> WL_O<205> WL_O<204> ++ WL_O<203> WL_O<202> WL_O<201> WL_O<200> WL_O<199> WL_O<198> WL_O<197> ++ WL_O<196> WL_O<195> WL_O<194> WL_O<193> WL_O<192> VDD VSS / ++ RM_IHPSG13_512x8_c3_1P_DEC04 +XSEL<11> ADDR_N_I<3> ADDR_N_I<2> ADDR_N_I<1> ADDR_N_I<0> CS00<11> ECLK_H<11> ++ ECLK_H<12> ECLK_B<11> ECLK_B<12> WL_O<191> WL_O<190> WL_O<189> WL_O<188> ++ WL_O<187> WL_O<186> WL_O<185> WL_O<184> WL_O<183> WL_O<182> WL_O<181> ++ WL_O<180> WL_O<179> WL_O<178> WL_O<177> WL_O<176> VDD VSS / ++ RM_IHPSG13_512x8_c3_1P_DEC04 +XSEL<10> ADDR_N_I<3> ADDR_N_I<2> ADDR_N_I<1> ADDR_N_I<0> CS00<10> ECLK_H<10> ++ ECLK_H<11> ECLK_B<10> ECLK_B<11> WL_O<175> WL_O<174> WL_O<173> WL_O<172> ++ WL_O<171> WL_O<170> WL_O<169> WL_O<168> WL_O<167> WL_O<166> WL_O<165> ++ WL_O<164> WL_O<163> WL_O<162> WL_O<161> WL_O<160> VDD VSS / ++ RM_IHPSG13_512x8_c3_1P_DEC04 +XSEL<9> ADDR_N_I<3> ADDR_N_I<2> ADDR_N_I<1> ADDR_N_I<0> CS00<9> ECLK_H<9> ++ ECLK_H<10> ECLK_B<9> ECLK_B<10> WL_O<159> WL_O<158> WL_O<157> WL_O<156> ++ WL_O<155> WL_O<154> WL_O<153> WL_O<152> WL_O<151> WL_O<150> WL_O<149> ++ WL_O<148> WL_O<147> WL_O<146> WL_O<145> WL_O<144> VDD VSS / ++ RM_IHPSG13_512x8_c3_1P_DEC04 +XSEL<8> ADDR_N_I<3> ADDR_N_I<2> ADDR_N_I<1> ADDR_N_I<0> CS00<8> ECLK_H<8> ++ ECLK_H<9> ECLK_B<8> ECLK_B<9> WL_O<143> WL_O<142> WL_O<141> WL_O<140> ++ WL_O<139> WL_O<138> WL_O<137> WL_O<136> WL_O<135> WL_O<134> WL_O<133> ++ WL_O<132> WL_O<131> WL_O<130> WL_O<129> WL_O<128> VDD VSS / ++ RM_IHPSG13_512x8_c3_1P_DEC04 +XSEL<7> ADDR_N_I<3> ADDR_N_I<2> ADDR_N_I<1> ADDR_N_I<0> CS00<7> ECLK_H<7> ++ ECLK_H<8> ECLK_B<7> ECLK_B<8> WL_O<127> WL_O<126> WL_O<125> WL_O<124> ++ WL_O<123> WL_O<122> WL_O<121> WL_O<120> WL_O<119> WL_O<118> WL_O<117> ++ WL_O<116> WL_O<115> WL_O<114> WL_O<113> WL_O<112> VDD VSS / ++ RM_IHPSG13_512x8_c3_1P_DEC04 +XSEL<6> ADDR_N_I<3> ADDR_N_I<2> ADDR_N_I<1> ADDR_N_I<0> CS00<6> ECLK_H<6> ++ ECLK_H<7> ECLK_B<6> ECLK_B<7> WL_O<111> WL_O<110> WL_O<109> WL_O<108> ++ WL_O<107> WL_O<106> WL_O<105> WL_O<104> WL_O<103> WL_O<102> WL_O<101> ++ WL_O<100> WL_O<99> WL_O<98> WL_O<97> WL_O<96> VDD VSS / ++ RM_IHPSG13_512x8_c3_1P_DEC04 +XSEL<5> ADDR_N_I<3> ADDR_N_I<2> ADDR_N_I<1> ADDR_N_I<0> CS00<5> ECLK_H<5> ++ ECLK_H<6> ECLK_B<5> ECLK_B<6> WL_O<95> WL_O<94> WL_O<93> WL_O<92> WL_O<91> ++ WL_O<90> WL_O<89> WL_O<88> WL_O<87> WL_O<86> WL_O<85> WL_O<84> WL_O<83> ++ WL_O<82> WL_O<81> WL_O<80> VDD VSS / RM_IHPSG13_512x8_c3_1P_DEC04 +XSEL<4> ADDR_N_I<3> ADDR_N_I<2> ADDR_N_I<1> ADDR_N_I<0> CS00<4> ECLK_H<4> ++ ECLK_H<5> ECLK_B<4> ECLK_B<5> WL_O<79> WL_O<78> WL_O<77> WL_O<76> WL_O<75> ++ WL_O<74> WL_O<73> WL_O<72> WL_O<71> WL_O<70> WL_O<69> WL_O<68> WL_O<67> ++ WL_O<66> WL_O<65> WL_O<64> VDD VSS / RM_IHPSG13_512x8_c3_1P_DEC04 +XSEL<3> ADDR_N_I<3> ADDR_N_I<2> ADDR_N_I<1> ADDR_N_I<0> CS00<3> ECLK_H<3> ++ ECLK_H<4> ECLK_B<3> ECLK_B<4> WL_O<63> WL_O<62> WL_O<61> WL_O<60> WL_O<59> ++ WL_O<58> WL_O<57> WL_O<56> WL_O<55> WL_O<54> WL_O<53> WL_O<52> WL_O<51> ++ WL_O<50> WL_O<49> WL_O<48> VDD VSS / RM_IHPSG13_512x8_c3_1P_DEC04 +XSEL<2> ADDR_N_I<3> ADDR_N_I<2> ADDR_N_I<1> ADDR_N_I<0> CS00<2> ECLK_H<2> ++ ECLK_H<3> ECLK_B<2> ECLK_B<3> WL_O<47> WL_O<46> WL_O<45> WL_O<44> WL_O<43> ++ WL_O<42> WL_O<41> WL_O<40> WL_O<39> WL_O<38> WL_O<37> WL_O<36> WL_O<35> ++ WL_O<34> WL_O<33> WL_O<32> VDD VSS / RM_IHPSG13_512x8_c3_1P_DEC04 +XSEL<1> ADDR_N_I<3> ADDR_N_I<2> ADDR_N_I<1> ADDR_N_I<0> CS00<1> ECLK_H<1> ++ ECLK_H<2> ECLK_B<1> ECLK_B<2> WL_O<31> WL_O<30> WL_O<29> WL_O<28> WL_O<27> ++ WL_O<26> WL_O<25> WL_O<24> WL_O<23> WL_O<22> WL_O<21> WL_O<20> WL_O<19> ++ WL_O<18> WL_O<17> WL_O<16> VDD VSS / RM_IHPSG13_512x8_c3_1P_DEC04 +XSEL<0> ADDR_N_I<3> ADDR_N_I<2> ADDR_N_I<1> ADDR_N_I<0> CS00<0> ECLK_I ++ ECLK_H<1> ECLK_B<0> ECLK_B<1> WL_O<15> WL_O<14> WL_O<13> WL_O<12> WL_O<11> ++ WL_O<10> WL_O<9> WL_O<8> WL_O<7> WL_O<6> WL_O<5> WL_O<4> WL_O<3> WL_O<2> ++ WL_O<1> WL_O<0> VDD VSS / RM_IHPSG13_512x8_c3_1P_DEC04 +XDEC01<10> ADDR_N_I<9> ADDR_N_I<8> CS_I CS04<1> VDD VSS / ++ RM_IHPSG13_512x8_c3_1P_DEC01 +XDEC01<9> ADDR_N_I<7> ADDR_N_I<6> CS04<1> CS02<5> VDD VSS / ++ RM_IHPSG13_512x8_c3_1P_DEC01 +XDEC01<8> ADDR_N_I<7> ADDR_N_I<6> CS04<0> CS02<1> VDD VSS / ++ RM_IHPSG13_512x8_c3_1P_DEC01 +XDEC01<7> ADDR_N_I<5> ADDR_N_I<4> CS02<7> CS00<29> VDD VSS / ++ RM_IHPSG13_512x8_c3_1P_DEC01 +XDEC01<6> ADDR_N_I<5> ADDR_N_I<4> CS02<6> CS00<25> VDD VSS / ++ RM_IHPSG13_512x8_c3_1P_DEC01 +XDEC01<5> ADDR_N_I<5> ADDR_N_I<4> CS02<5> CS00<21> VDD VSS / ++ RM_IHPSG13_512x8_c3_1P_DEC01 +XDEC01<4> ADDR_N_I<5> ADDR_N_I<4> CS02<4> CS00<17> VDD VSS / ++ RM_IHPSG13_512x8_c3_1P_DEC01 +XDEC01<3> ADDR_N_I<5> ADDR_N_I<4> CS02<3> CS00<13> VDD VSS / ++ RM_IHPSG13_512x8_c3_1P_DEC01 +XDEC01<2> ADDR_N_I<5> ADDR_N_I<4> CS02<2> CS00<9> VDD VSS / ++ RM_IHPSG13_512x8_c3_1P_DEC01 +XDEC01<1> ADDR_N_I<5> ADDR_N_I<4> CS02<1> CS00<5> VDD VSS / ++ RM_IHPSG13_512x8_c3_1P_DEC01 +XDEC01<0> ADDR_N_I<5> ADDR_N_I<4> CS02<0> CS00<1> VDD VSS / ++ RM_IHPSG13_512x8_c3_1P_DEC01 +XDEC10<9> ADDR_N_I<7> ADDR_N_I<6> CS04<1> CS02<6> VDD VSS / ++ RM_IHPSG13_512x8_c3_1P_DEC02 +XDEC10<8> ADDR_N_I<7> ADDR_N_I<6> CS04<0> CS02<2> VDD VSS / ++ RM_IHPSG13_512x8_c3_1P_DEC02 +XDEC10<7> ADDR_N_I<5> ADDR_N_I<4> CS02<7> CS00<30> VDD VSS / ++ RM_IHPSG13_512x8_c3_1P_DEC02 +XDEC10<6> ADDR_N_I<5> ADDR_N_I<4> CS02<6> CS00<26> VDD VSS / ++ RM_IHPSG13_512x8_c3_1P_DEC02 +XDEC10<5> ADDR_N_I<5> ADDR_N_I<4> CS02<5> CS00<22> VDD VSS / ++ RM_IHPSG13_512x8_c3_1P_DEC02 +XDEC10<4> ADDR_N_I<5> ADDR_N_I<4> CS02<4> CS00<18> VDD VSS / ++ RM_IHPSG13_512x8_c3_1P_DEC02 +XDEC10<3> ADDR_N_I<5> ADDR_N_I<4> CS02<3> CS00<14> VDD VSS / ++ RM_IHPSG13_512x8_c3_1P_DEC02 +XDEC10<2> ADDR_N_I<5> ADDR_N_I<4> CS02<2> CS00<10> VDD VSS / ++ RM_IHPSG13_512x8_c3_1P_DEC02 +XDEC10<1> ADDR_N_I<5> ADDR_N_I<4> CS02<1> CS00<6> VDD VSS / ++ RM_IHPSG13_512x8_c3_1P_DEC02 +XDEC10<0> ADDR_N_I<5> ADDR_N_I<4> CS02<0> CS00<2> VDD VSS / ++ RM_IHPSG13_512x8_c3_1P_DEC02 +XI0 ADDR_N_I<9> VDD VSS / RSC_IHPSG13_TIEL +.ENDS +.SUBCKT RM_IHPSG13_512x8_c3_1P_ROWREG9 ACLK_N_I ADDR_I<8> ADDR_I<7> ADDR_I<6> ADDR_I<5> ++ ADDR_I<4> ADDR_I<3> ADDR_I<2> ADDR_I<1> ADDR_I<0> ADDR_N_O<8> ADDR_N_O<7> ++ ADDR_N_O<6> ADDR_N_O<5> ADDR_N_O<4> ADDR_N_O<3> ADDR_N_O<2> ADDR_N_O<1> ++ ADDR_N_O<0> BIST_ADDR_I<8> BIST_ADDR_I<7> BIST_ADDR_I<6> BIST_ADDR_I<5> ++ BIST_ADDR_I<4> BIST_ADDR_I<3> BIST_ADDR_I<2> BIST_ADDR_I<1> BIST_ADDR_I<0> ++ BIST_EN_I VDD VSS +XINV<8> q_int<8> qn_int<8> VDD VSS / RSC_IHPSG13_CINVX2 +XINV<7> q_int<7> qn_int<7> VDD VSS / RSC_IHPSG13_CINVX2 +XINV<6> q_int<6> qn_int<6> VDD VSS / RSC_IHPSG13_CINVX2 +XINV<5> q_int<5> qn_int<5> VDD VSS / RSC_IHPSG13_CINVX2 +XINV<4> q_int<4> qn_int<4> VDD VSS / RSC_IHPSG13_CINVX2 +XINV<3> q_int<3> qn_int<3> VDD VSS / RSC_IHPSG13_CINVX2 +XINV<2> q_int<2> qn_int<2> VDD VSS / RSC_IHPSG13_CINVX2 +XINV<1> q_int<1> qn_int<1> VDD VSS / RSC_IHPSG13_CINVX2 +XINV<0> q_int<0> qn_int<0> VDD VSS / RSC_IHPSG13_CINVX2 +XDRV<8> qn_int<8> ADDR_N_O<8> VDD VSS / RSC_IHPSG13_CINVX8 +XDRV<7> qn_int<7> ADDR_N_O<7> VDD VSS / RSC_IHPSG13_CINVX8 +XDRV<6> qn_int<6> ADDR_N_O<6> VDD VSS / RSC_IHPSG13_CINVX8 +XDRV<5> qn_int<5> ADDR_N_O<5> VDD VSS / RSC_IHPSG13_CINVX8 +XDRV<4> qn_int<4> ADDR_N_O<4> VDD VSS / RSC_IHPSG13_CINVX8 +XDRV<3> qn_int<3> ADDR_N_O<3> VDD VSS / RSC_IHPSG13_CINVX8 +XDRV<2> qn_int<2> ADDR_N_O<2> VDD VSS / RSC_IHPSG13_CINVX8 +XDRV<1> qn_int<1> ADDR_N_O<1> VDD VSS / RSC_IHPSG13_CINVX8 +XDRV<0> qn_int<0> ADDR_N_O<0> VDD VSS / RSC_IHPSG13_CINVX8 +XDFF<8> BIST_EN_I BIST_ADDR_I<8> ACLK_N_I ADDR_I<8> q_int<8> net04<0> VDD ++ VSS / RSC_IHPSG13_DFNQMX2IX1 +XDFF<7> BIST_EN_I BIST_ADDR_I<7> ACLK_N_I ADDR_I<7> q_int<7> net04<1> VDD ++ VSS / RSC_IHPSG13_DFNQMX2IX1 +XDFF<6> BIST_EN_I BIST_ADDR_I<6> ACLK_N_I ADDR_I<6> q_int<6> net04<2> VDD ++ VSS / RSC_IHPSG13_DFNQMX2IX1 +XDFF<5> BIST_EN_I BIST_ADDR_I<5> ACLK_N_I ADDR_I<5> q_int<5> net04<3> VDD ++ VSS / RSC_IHPSG13_DFNQMX2IX1 +XDFF<4> BIST_EN_I BIST_ADDR_I<4> ACLK_N_I ADDR_I<4> q_int<4> net04<4> VDD ++ VSS / RSC_IHPSG13_DFNQMX2IX1 +XDFF<3> BIST_EN_I BIST_ADDR_I<3> ACLK_N_I ADDR_I<3> q_int<3> net04<5> VDD ++ VSS / RSC_IHPSG13_DFNQMX2IX1 +XDFF<2> BIST_EN_I BIST_ADDR_I<2> ACLK_N_I ADDR_I<2> q_int<2> net04<6> VDD ++ VSS / RSC_IHPSG13_DFNQMX2IX1 +XDFF<1> BIST_EN_I BIST_ADDR_I<1> ACLK_N_I ADDR_I<1> q_int<1> net04<7> VDD ++ VSS / RSC_IHPSG13_DFNQMX2IX1 +XDFF<0> BIST_EN_I BIST_ADDR_I<0> ACLK_N_I ADDR_I<0> q_int<0> net04<8> VDD ++ VSS / RSC_IHPSG13_DFNQMX2IX1 +.ENDS + +.SUBCKT RM_IHPSG13_512x8_c3_1P_ROWDEC7 ADDR_N_I<6> ADDR_N_I<5> ADDR_N_I<4> ADDR_N_I<3> ++ ADDR_N_I<2> ADDR_N_I<1> ADDR_N_I<0> CS_I ECLK_I WL_O<127> WL_O<126> ++ WL_O<125> WL_O<124> WL_O<123> WL_O<122> WL_O<121> WL_O<120> WL_O<119> ++ WL_O<118> WL_O<117> WL_O<116> WL_O<115> WL_O<114> WL_O<113> WL_O<112> ++ WL_O<111> WL_O<110> WL_O<109> WL_O<108> WL_O<107> WL_O<106> WL_O<105> ++ WL_O<104> WL_O<103> WL_O<102> WL_O<101> WL_O<100> WL_O<99> WL_O<98> WL_O<97> ++ WL_O<96> WL_O<95> WL_O<94> WL_O<93> WL_O<92> WL_O<91> WL_O<90> WL_O<89> ++ WL_O<88> WL_O<87> WL_O<86> WL_O<85> WL_O<84> WL_O<83> WL_O<82> WL_O<81> ++ WL_O<80> WL_O<79> WL_O<78> WL_O<77> WL_O<76> WL_O<75> WL_O<74> WL_O<73> ++ WL_O<72> WL_O<71> WL_O<70> WL_O<69> WL_O<68> WL_O<67> WL_O<66> WL_O<65> ++ WL_O<64> WL_O<63> WL_O<62> WL_O<61> WL_O<60> WL_O<59> WL_O<58> WL_O<57> ++ WL_O<56> WL_O<55> WL_O<54> WL_O<53> WL_O<52> WL_O<51> WL_O<50> WL_O<49> ++ WL_O<48> WL_O<47> WL_O<46> WL_O<45> WL_O<44> WL_O<43> WL_O<42> WL_O<41> ++ WL_O<40> WL_O<39> WL_O<38> WL_O<37> WL_O<36> WL_O<35> WL_O<34> WL_O<33> ++ WL_O<32> WL_O<31> WL_O<30> WL_O<29> WL_O<28> WL_O<27> WL_O<26> WL_O<25> ++ WL_O<24> WL_O<23> WL_O<22> WL_O<21> WL_O<20> WL_O<19> WL_O<18> WL_O<17> ++ WL_O<16> WL_O<15> WL_O<14> WL_O<13> WL_O<12> WL_O<11> WL_O<10> WL_O<9> ++ WL_O<8> WL_O<7> WL_O<6> WL_O<5> WL_O<4> WL_O<3> WL_O<2> WL_O<1> WL_O<0> ++ VDD VSS +XDEC11<1> ADDR_N_I<5> ADDR_N_I<4> CS04<1> CS00<7> VDD VSS / ++ RM_IHPSG13_512x8_c3_1P_DEC03 +XDEC11<0> ADDR_N_I<5> ADDR_N_I<4> CS04<0> CS00<3> VDD VSS / ++ RM_IHPSG13_512x8_c3_1P_DEC03 +XDEC10<1> ADDR_N_I<5> ADDR_N_I<4> CS04<1> CS00<6> VDD VSS / ++ RM_IHPSG13_512x8_c3_1P_DEC02 +XDEC10<0> ADDR_N_I<5> ADDR_N_I<4> CS04<0> CS00<2> VDD VSS / ++ RM_IHPSG13_512x8_c3_1P_DEC02 +XSEL<7> ADDR_N_I<3> ADDR_N_I<2> ADDR_N_I<1> ADDR_N_I<0> CS00<7> ECLK_H<7> ++ ECLK_H<8> ECLK_B<7> ECLK_B<8> WL_O<127> WL_O<126> WL_O<125> WL_O<124> ++ WL_O<123> WL_O<122> WL_O<121> WL_O<120> WL_O<119> WL_O<118> WL_O<117> ++ WL_O<116> WL_O<115> WL_O<114> WL_O<113> WL_O<112> VDD VSS / ++ RM_IHPSG13_512x8_c3_1P_DEC04 +XSEL<6> ADDR_N_I<3> ADDR_N_I<2> ADDR_N_I<1> ADDR_N_I<0> CS00<6> ECLK_H<6> ++ ECLK_H<7> ECLK_B<6> ECLK_B<7> WL_O<111> WL_O<110> WL_O<109> WL_O<108> ++ WL_O<107> WL_O<106> WL_O<105> WL_O<104> WL_O<103> WL_O<102> WL_O<101> ++ WL_O<100> WL_O<99> WL_O<98> WL_O<97> WL_O<96> VDD VSS / ++ RM_IHPSG13_512x8_c3_1P_DEC04 +XSEL<5> ADDR_N_I<3> ADDR_N_I<2> ADDR_N_I<1> ADDR_N_I<0> CS00<5> ECLK_H<5> ++ ECLK_H<6> ECLK_B<5> ECLK_B<6> WL_O<95> WL_O<94> WL_O<93> WL_O<92> WL_O<91> ++ WL_O<90> WL_O<89> WL_O<88> WL_O<87> WL_O<86> WL_O<85> WL_O<84> WL_O<83> ++ WL_O<82> WL_O<81> WL_O<80> VDD VSS / RM_IHPSG13_512x8_c3_1P_DEC04 +XSEL<4> ADDR_N_I<3> ADDR_N_I<2> ADDR_N_I<1> ADDR_N_I<0> CS00<4> ECLK_H<4> ++ ECLK_H<5> ECLK_B<4> ECLK_B<5> WL_O<79> WL_O<78> WL_O<77> WL_O<76> WL_O<75> ++ WL_O<74> WL_O<73> WL_O<72> WL_O<71> WL_O<70> WL_O<69> WL_O<68> WL_O<67> ++ WL_O<66> WL_O<65> WL_O<64> VDD VSS / RM_IHPSG13_512x8_c3_1P_DEC04 +XSEL<3> ADDR_N_I<3> ADDR_N_I<2> ADDR_N_I<1> ADDR_N_I<0> CS00<3> ECLK_H<3> ++ ECLK_H<4> ECLK_B<3> ECLK_B<4> WL_O<63> WL_O<62> WL_O<61> WL_O<60> WL_O<59> ++ WL_O<58> WL_O<57> WL_O<56> WL_O<55> WL_O<54> WL_O<53> WL_O<52> WL_O<51> ++ WL_O<50> WL_O<49> WL_O<48> VDD VSS / RM_IHPSG13_512x8_c3_1P_DEC04 +XSEL<2> ADDR_N_I<3> ADDR_N_I<2> ADDR_N_I<1> ADDR_N_I<0> CS00<2> ECLK_H<2> ++ ECLK_H<3> ECLK_B<2> ECLK_B<3> WL_O<47> WL_O<46> WL_O<45> WL_O<44> WL_O<43> ++ WL_O<42> WL_O<41> WL_O<40> WL_O<39> WL_O<38> WL_O<37> WL_O<36> WL_O<35> ++ WL_O<34> WL_O<33> WL_O<32> VDD VSS / RM_IHPSG13_512x8_c3_1P_DEC04 +XSEL<1> ADDR_N_I<3> ADDR_N_I<2> ADDR_N_I<1> ADDR_N_I<0> CS00<1> ECLK_H<1> ++ ECLK_H<2> ECLK_B<1> ECLK_B<2> WL_O<31> WL_O<30> WL_O<29> WL_O<28> WL_O<27> ++ WL_O<26> WL_O<25> WL_O<24> WL_O<23> WL_O<22> WL_O<21> WL_O<20> WL_O<19> ++ WL_O<18> WL_O<17> WL_O<16> VDD VSS / RM_IHPSG13_512x8_c3_1P_DEC04 +XSEL<0> ADDR_N_I<3> ADDR_N_I<2> ADDR_N_I<1> ADDR_N_I<0> CS00<0> ECLK_I ++ ECLK_H<1> ECLK_B<0> ECLK_B<1> WL_O<15> WL_O<14> WL_O<13> WL_O<12> WL_O<11> ++ WL_O<10> WL_O<9> WL_O<8> WL_O<7> WL_O<6> WL_O<5> WL_O<4> WL_O<3> WL_O<2> ++ WL_O<1> WL_O<0> VDD VSS / RM_IHPSG13_512x8_c3_1P_DEC04 +XDEC00<2> ADDR_N_I<7> ADDR_N_I<6> CS_I CS04<0> VDD VSS / ++ RM_IHPSG13_512x8_c3_1P_DEC00 +XDEC00<1> ADDR_N_I<5> ADDR_N_I<4> CS04<1> CS00<4> VDD VSS / ++ RM_IHPSG13_512x8_c3_1P_DEC00 +XDEC00<0> ADDR_N_I<5> ADDR_N_I<4> CS04<0> CS00<0> VDD VSS / ++ RM_IHPSG13_512x8_c3_1P_DEC00 +XDEC01<2> ADDR_N_I<7> ADDR_N_I<6> CS_I CS04<1> VDD VSS / ++ RM_IHPSG13_512x8_c3_1P_DEC01 +XDEC01<1> ADDR_N_I<5> ADDR_N_I<4> CS04<1> CS00<5> VDD VSS / ++ RM_IHPSG13_512x8_c3_1P_DEC01 +XDEC01<0> ADDR_N_I<5> ADDR_N_I<4> CS04<0> CS00<1> VDD VSS / ++ RM_IHPSG13_512x8_c3_1P_DEC01 +XL2<44> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<43> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<42> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<41> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<40> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<39> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<38> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<37> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<36> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<35> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<34> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<33> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<32> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<31> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<30> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<29> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<28> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<27> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<26> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<25> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<24> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<23> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<22> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<21> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<20> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<19> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<18> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<17> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<16> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<15> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<14> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<13> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<12> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<11> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<10> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<9> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<8> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<7> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<6> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<5> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<4> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<3> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<2> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<1> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI0 ADDR_N_I<7> VDD VSS / RSC_IHPSG13_TIEL +.ENDS +.SUBCKT RM_IHPSG13_512x8_c3_1P_ROWREG7 ACLK_N_I ADDR_I<6> ADDR_I<5> ADDR_I<4> ADDR_I<3> ++ ADDR_I<2> ADDR_I<1> ADDR_I<0> ADDR_N_O<6> ADDR_N_O<5> ADDR_N_O<4> ++ ADDR_N_O<3> ADDR_N_O<2> ADDR_N_O<1> ADDR_N_O<0> BIST_ADDR_I<6> ++ BIST_ADDR_I<5> BIST_ADDR_I<4> BIST_ADDR_I<3> BIST_ADDR_I<2> BIST_ADDR_I<1> ++ BIST_ADDR_I<0> BIST_EN_I VDD VSS +XINV<6> q_int<6> qn_int<6> VDD VSS / RSC_IHPSG13_CINVX2 +XINV<5> q_int<5> qn_int<5> VDD VSS / RSC_IHPSG13_CINVX2 +XINV<4> q_int<4> qn_int<4> VDD VSS / RSC_IHPSG13_CINVX2 +XINV<3> q_int<3> qn_int<3> VDD VSS / RSC_IHPSG13_CINVX2 +XINV<2> q_int<2> qn_int<2> VDD VSS / RSC_IHPSG13_CINVX2 +XINV<1> q_int<1> qn_int<1> VDD VSS / RSC_IHPSG13_CINVX2 +XINV<0> q_int<0> qn_int<0> VDD VSS / RSC_IHPSG13_CINVX2 +XDRV<6> qn_int<6> ADDR_N_O<6> VDD VSS / RSC_IHPSG13_CINVX8 +XDRV<5> qn_int<5> ADDR_N_O<5> VDD VSS / RSC_IHPSG13_CINVX8 +XDRV<4> qn_int<4> ADDR_N_O<4> VDD VSS / RSC_IHPSG13_CINVX8 +XDRV<3> qn_int<3> ADDR_N_O<3> VDD VSS / RSC_IHPSG13_CINVX8 +XDRV<2> qn_int<2> ADDR_N_O<2> VDD VSS / RSC_IHPSG13_CINVX8 +XDRV<1> qn_int<1> ADDR_N_O<1> VDD VSS / RSC_IHPSG13_CINVX8 +XDRV<0> qn_int<0> ADDR_N_O<0> VDD VSS / RSC_IHPSG13_CINVX8 +XDFF<6> BIST_EN_I BIST_ADDR_I<6> ACLK_N_I ADDR_I<6> q_int<6> net2<0> VDD ++ VSS / RSC_IHPSG13_DFNQMX2IX1 +XDFF<5> BIST_EN_I BIST_ADDR_I<5> ACLK_N_I ADDR_I<5> q_int<5> net2<1> VDD ++ VSS / RSC_IHPSG13_DFNQMX2IX1 +XDFF<4> BIST_EN_I BIST_ADDR_I<4> ACLK_N_I ADDR_I<4> q_int<4> net2<2> VDD ++ VSS / RSC_IHPSG13_DFNQMX2IX1 +XDFF<3> BIST_EN_I BIST_ADDR_I<3> ACLK_N_I ADDR_I<3> q_int<3> net2<3> VDD ++ VSS / RSC_IHPSG13_DFNQMX2IX1 +XDFF<2> BIST_EN_I BIST_ADDR_I<2> ACLK_N_I ADDR_I<2> q_int<2> net2<4> VDD ++ VSS / RSC_IHPSG13_DFNQMX2IX1 +XDFF<1> BIST_EN_I BIST_ADDR_I<1> ACLK_N_I ADDR_I<1> q_int<1> net2<5> VDD ++ VSS / RSC_IHPSG13_DFNQMX2IX1 +XDFF<0> BIST_EN_I BIST_ADDR_I<0> ACLK_N_I ADDR_I<0> q_int<0> net2<6> VDD ++ VSS / RSC_IHPSG13_DFNQMX2IX1 +XI11<8> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI11<7> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI11<6> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI11<5> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI11<4> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI11<3> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI11<2> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI11<1> VDD VSS / RSC_IHPSG13_FILLCAP8 +.ENDS + +.SUBCKT RM_IHPSG13_512x8_c3_1P_COLDRV13X8 ADDR_COL_I<1> ADDR_COL_I<0> ADDR_COL_O<1> ++ ADDR_COL_O<0> ADDR_DEC_I<7> ADDR_DEC_I<6> ADDR_DEC_I<5> ADDR_DEC_I<4> ++ ADDR_DEC_I<3> ADDR_DEC_I<2> ADDR_DEC_I<1> ADDR_DEC_I<0> ADDR_DEC_O<7> ++ ADDR_DEC_O<6> ADDR_DEC_O<5> ADDR_DEC_O<4> ADDR_DEC_O<3> ADDR_DEC_O<2> ++ ADDR_DEC_O<1> ADDR_DEC_O<0> DCLK_I DCLK_O RCLK_I RCLK_O WCLK_I WCLK_O ++ VDD VSS +XI0<1> VDD VSS / RSC_IHPSG13_FILLCAP4 +XI0<0> VDD VSS / RSC_IHPSG13_FILLCAP4 +XADDR_COL_DRV<1> ADDR_COL_I<1> ADDR_COL_O<1> VDD VSS / ++ RSC_IHPSG13_CBUFX8 +XADDR_COL_DRV<0> ADDR_COL_I<0> ADDR_COL_O<0> VDD VSS / ++ RSC_IHPSG13_CBUFX8 +XADDR_DEC_DRV<7> ADDR_DEC_I<7> ADDR_DEC_O<7> VDD VSS / ++ RSC_IHPSG13_CBUFX8 +XADDR_DEC_DRV<6> ADDR_DEC_I<6> ADDR_DEC_O<6> VDD VSS / ++ RSC_IHPSG13_CBUFX8 +XADDR_DEC_DRV<5> ADDR_DEC_I<5> ADDR_DEC_O<5> VDD VSS / ++ RSC_IHPSG13_CBUFX8 +XADDR_DEC_DRV<4> ADDR_DEC_I<4> ADDR_DEC_O<4> VDD VSS / ++ RSC_IHPSG13_CBUFX8 +XADDR_DEC_DRV<3> ADDR_DEC_I<3> ADDR_DEC_O<3> VDD VSS / ++ RSC_IHPSG13_CBUFX8 +XADDR_DEC_DRV<2> ADDR_DEC_I<2> ADDR_DEC_O<2> VDD VSS / ++ RSC_IHPSG13_CBUFX8 +XADDR_DEC_DRV<1> ADDR_DEC_I<1> ADDR_DEC_O<1> VDD VSS / ++ RSC_IHPSG13_CBUFX8 +XADDR_DEC_DRV<0> ADDR_DEC_I<0> ADDR_DEC_O<0> VDD VSS / ++ RSC_IHPSG13_CBUFX8 +XDCLK_DRV DCLK_I DCLK_O VDD VSS / RSC_IHPSG13_CBUFX8 +XRCLK_DRV RCLK_I RCLK_O VDD VSS / RSC_IHPSG13_CBUFX8 +XWCLK_DRV WCLK_I WCLK_O VDD VSS / RSC_IHPSG13_CBUFX8 +.ENDS +.SUBCKT RM_IHPSG13_512x8_c3_1P_WLDRV16X8 A<15> A<14> A<13> A<12> A<11> A<10> A<9> A<8> ++ A<7> A<6> A<5> A<4> A<3> A<2> A<1> A<0> Z<15> Z<14> Z<13> Z<12> Z<11> Z<10> ++ Z<9> Z<8> Z<7> Z<6> Z<5> Z<4> Z<3> Z<2> Z<1> Z<0> VDD VSS +XBUF<15> A<15> Z<15> VDD VSS / RSC_IHPSG13_WLDRVX8 +XBUF<14> A<14> Z<14> VDD VSS / RSC_IHPSG13_WLDRVX8 +XBUF<13> A<13> Z<13> VDD VSS / RSC_IHPSG13_WLDRVX8 +XBUF<12> A<12> Z<12> VDD VSS / RSC_IHPSG13_WLDRVX8 +XBUF<11> A<11> Z<11> VDD VSS / RSC_IHPSG13_WLDRVX8 +XBUF<10> A<10> Z<10> VDD VSS / RSC_IHPSG13_WLDRVX8 +XBUF<9> A<9> Z<9> VDD VSS / RSC_IHPSG13_WLDRVX8 +XBUF<8> A<8> Z<8> VDD VSS / RSC_IHPSG13_WLDRVX8 +XBUF<7> A<7> Z<7> VDD VSS / RSC_IHPSG13_WLDRVX8 +XBUF<6> A<6> Z<6> VDD VSS / RSC_IHPSG13_WLDRVX8 +XBUF<5> A<5> Z<5> VDD VSS / RSC_IHPSG13_WLDRVX8 +XBUF<4> A<4> Z<4> VDD VSS / RSC_IHPSG13_WLDRVX8 +XBUF<3> A<3> Z<3> VDD VSS / RSC_IHPSG13_WLDRVX8 +XBUF<2> A<2> Z<2> VDD VSS / RSC_IHPSG13_WLDRVX8 +XBUF<1> A<1> Z<1> VDD VSS / RSC_IHPSG13_WLDRVX8 +XBUF<0> A<0> Z<0> VDD VSS / RSC_IHPSG13_WLDRVX8 +.ENDS + + + +.SUBCKT RM_IHPSG13_512x8_c3_1P_ROWDEC6 ADDR_N_I<5> ADDR_N_I<4> ADDR_N_I<3> ADDR_N_I<2> ++ ADDR_N_I<1> ADDR_N_I<0> CS_I ECLK_I WL_O<63> WL_O<62> WL_O<61> WL_O<60> ++ WL_O<59> WL_O<58> WL_O<57> WL_O<56> WL_O<55> WL_O<54> WL_O<53> WL_O<52> ++ WL_O<51> WL_O<50> WL_O<49> WL_O<48> WL_O<47> WL_O<46> WL_O<45> WL_O<44> ++ WL_O<43> WL_O<42> WL_O<41> WL_O<40> WL_O<39> WL_O<38> WL_O<37> WL_O<36> ++ WL_O<35> WL_O<34> WL_O<33> WL_O<32> WL_O<31> WL_O<30> WL_O<29> WL_O<28> ++ WL_O<27> WL_O<26> WL_O<25> WL_O<24> WL_O<23> WL_O<22> WL_O<21> WL_O<20> ++ WL_O<19> WL_O<18> WL_O<17> WL_O<16> WL_O<15> WL_O<14> WL_O<13> WL_O<12> ++ WL_O<11> WL_O<10> WL_O<9> WL_O<8> WL_O<7> WL_O<6> WL_O<5> WL_O<4> WL_O<3> ++ WL_O<2> WL_O<1> WL_O<0> VDD VSS +XDEC11 ADDR_N_I<5> ADDR_N_I<4> CS_I CS00<3> VDD VSS / ++ RM_IHPSG13_512x8_c3_1P_DEC03 +XDEC00 ADDR_N_I<5> ADDR_N_I<4> CS_I CS00<0> VDD VSS / ++ RM_IHPSG13_512x8_c3_1P_DEC00 +XDEC01 ADDR_N_I<5> ADDR_N_I<4> CS_I CS00<1> VDD VSS / ++ RM_IHPSG13_512x8_c3_1P_DEC01 +XDEC10 ADDR_N_I<5> ADDR_N_I<4> CS_I CS00<2> VDD VSS / ++ RM_IHPSG13_512x8_c3_1P_DEC02 +XSEL<3> ADDR_N_I<3> ADDR_N_I<2> ADDR_N_I<1> ADDR_N_I<0> CS00<3> ECLK_H<3> ++ ECLK_H<4> ECLK_B<3> ECLK_B<4> WL_O<63> WL_O<62> WL_O<61> WL_O<60> WL_O<59> ++ WL_O<58> WL_O<57> WL_O<56> WL_O<55> WL_O<54> WL_O<53> WL_O<52> WL_O<51> ++ WL_O<50> WL_O<49> WL_O<48> VDD VSS / RM_IHPSG13_512x8_c3_1P_DEC04 +XSEL<2> ADDR_N_I<3> ADDR_N_I<2> ADDR_N_I<1> ADDR_N_I<0> CS00<2> ECLK_H<2> ++ ECLK_H<3> ECLK_B<2> ECLK_B<3> WL_O<47> WL_O<46> WL_O<45> WL_O<44> WL_O<43> ++ WL_O<42> WL_O<41> WL_O<40> WL_O<39> WL_O<38> WL_O<37> WL_O<36> WL_O<35> ++ WL_O<34> WL_O<33> WL_O<32> VDD VSS / RM_IHPSG13_512x8_c3_1P_DEC04 +XSEL<1> ADDR_N_I<3> ADDR_N_I<2> ADDR_N_I<1> ADDR_N_I<0> CS00<1> ECLK_H<1> ++ ECLK_H<2> ECLK_B<1> ECLK_B<2> WL_O<31> WL_O<30> WL_O<29> WL_O<28> WL_O<27> ++ WL_O<26> WL_O<25> WL_O<24> WL_O<23> WL_O<22> WL_O<21> WL_O<20> WL_O<19> ++ WL_O<18> WL_O<17> WL_O<16> VDD VSS / RM_IHPSG13_512x8_c3_1P_DEC04 +XSEL<0> ADDR_N_I<3> ADDR_N_I<2> ADDR_N_I<1> ADDR_N_I<0> CS00<0> ECLK_I ++ ECLK_H<1> ECLK_B<0> ECLK_B<1> WL_O<15> WL_O<14> WL_O<13> WL_O<12> WL_O<11> ++ WL_O<10> WL_O<9> WL_O<8> WL_O<7> WL_O<6> WL_O<5> WL_O<4> WL_O<3> WL_O<2> ++ WL_O<1> WL_O<0> VDD VSS / RM_IHPSG13_512x8_c3_1P_DEC04 +XL2<24> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<23> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<22> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<21> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<20> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<19> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<18> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<17> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<16> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<15> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<14> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<13> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<12> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<11> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<10> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<9> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<8> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<7> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<6> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<5> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<4> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<3> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<2> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<1> VDD VSS / RSC_IHPSG13_FILLCAP8 +.ENDS +.SUBCKT RM_IHPSG13_512x8_c3_1P_ROWREG6 ACLK_N_I ADDR_I<5> ADDR_I<4> ADDR_I<3> ADDR_I<2> ++ ADDR_I<1> ADDR_I<0> ADDR_N_O<5> ADDR_N_O<4> ADDR_N_O<3> ADDR_N_O<2> ++ ADDR_N_O<1> ADDR_N_O<0> BIST_ADDR_I<5> BIST_ADDR_I<4> BIST_ADDR_I<3> ++ BIST_ADDR_I<2> BIST_ADDR_I<1> BIST_ADDR_I<0> BIST_EN_I VDD VSS +XINV<5> q_int<5> qn_int<5> VDD VSS / RSC_IHPSG13_CINVX2 +XINV<4> q_int<4> qn_int<4> VDD VSS / RSC_IHPSG13_CINVX2 +XINV<3> q_int<3> qn_int<3> VDD VSS / RSC_IHPSG13_CINVX2 +XINV<2> q_int<2> qn_int<2> VDD VSS / RSC_IHPSG13_CINVX2 +XINV<1> q_int<1> qn_int<1> VDD VSS / RSC_IHPSG13_CINVX2 +XINV<0> q_int<0> qn_int<0> VDD VSS / RSC_IHPSG13_CINVX2 +XDRV<5> qn_int<5> ADDR_N_O<5> VDD VSS / RSC_IHPSG13_CINVX8 +XDRV<4> qn_int<4> ADDR_N_O<4> VDD VSS / RSC_IHPSG13_CINVX8 +XDRV<3> qn_int<3> ADDR_N_O<3> VDD VSS / RSC_IHPSG13_CINVX8 +XDRV<2> qn_int<2> ADDR_N_O<2> VDD VSS / RSC_IHPSG13_CINVX8 +XDRV<1> qn_int<1> ADDR_N_O<1> VDD VSS / RSC_IHPSG13_CINVX8 +XDRV<0> qn_int<0> ADDR_N_O<0> VDD VSS / RSC_IHPSG13_CINVX8 +XDFF<5> BIST_EN_I BIST_ADDR_I<5> ACLK_N_I ADDR_I<5> q_int<5> net2<0> VDD ++ VSS / RSC_IHPSG13_DFNQMX2IX1 +XDFF<4> BIST_EN_I BIST_ADDR_I<4> ACLK_N_I ADDR_I<4> q_int<4> net2<1> VDD ++ VSS / RSC_IHPSG13_DFNQMX2IX1 +XDFF<3> BIST_EN_I BIST_ADDR_I<3> ACLK_N_I ADDR_I<3> q_int<3> net2<2> VDD ++ VSS / RSC_IHPSG13_DFNQMX2IX1 +XDFF<2> BIST_EN_I BIST_ADDR_I<2> ACLK_N_I ADDR_I<2> q_int<2> net2<3> VDD ++ VSS / RSC_IHPSG13_DFNQMX2IX1 +XDFF<1> BIST_EN_I BIST_ADDR_I<1> ACLK_N_I ADDR_I<1> q_int<1> net2<4> VDD ++ VSS / RSC_IHPSG13_DFNQMX2IX1 +XDFF<0> BIST_EN_I BIST_ADDR_I<0> ACLK_N_I ADDR_I<0> q_int<0> net2<5> VDD ++ VSS / RSC_IHPSG13_DFNQMX2IX1 +XI11<12> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI11<11> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI11<10> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI11<9> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI11<8> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI11<7> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI11<6> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI11<5> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI11<4> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI11<3> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI11<2> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI11<1> VDD VSS / RSC_IHPSG13_FILLCAP8 +.ENDS + + +.SUBCKT RM_IHPSG13_512x8_c3_1P_COLUMN_pcell_0 A_BLC_BOT<1> A_BLC_BOT<0> A_BLC_TOP<1> A_BLC_TOP<0> A_BLT_BOT<1> A_BLT_BOT<0> A_BLT_TOP<1> A_BLT_TOP<0> A_LWL<63> A_LWL<62> A_LWL<61> A_LWL<60> A_LWL<59> A_LWL<58> A_LWL<57> A_LWL<56> A_LWL<55> A_LWL<54> A_LWL<53> A_LWL<52> A_LWL<51> A_LWL<50> A_LWL<49> A_LWL<48> A_LWL<47> A_LWL<46> A_LWL<45> A_LWL<44> A_LWL<43> A_LWL<42> A_LWL<41> A_LWL<40> A_LWL<39> A_LWL<38> A_LWL<37> A_LWL<36> A_LWL<35> A_LWL<34> A_LWL<33> A_LWL<32> A_LWL<31> A_LWL<30> A_LWL<29> A_LWL<28> A_LWL<27> A_LWL<26> A_LWL<25> A_LWL<24> A_LWL<23> A_LWL<22> A_LWL<21> A_LWL<20> A_LWL<19> A_LWL<18> A_LWL<17> A_LWL<16> A_LWL<15> A_LWL<14> A_LWL<13> A_LWL<12> A_LWL<11> A_LWL<10> A_LWL<9> A_LWL<8> A_LWL<7> A_LWL<6> A_LWL<5> A_LWL<4> A_LWL<3> A_LWL<2> A_LWL<1> A_LWL<0> A_RWL<63> A_RWL<62> A_RWL<61> A_RWL<60> A_RWL<59> A_RWL<58> A_RWL<57> A_RWL<56> A_RWL<55> A_RWL<54> A_RWL<53> A_RWL<52> A_RWL<51> A_RWL<50> A_RWL<49> A_RWL<48> A_RWL<47> A_RWL<46> A_RWL<45> A_RWL<44> A_RWL<43> A_RWL<42> A_RWL<41> A_RWL<40> A_RWL<39> A_RWL<38> A_RWL<37> A_RWL<36> A_RWL<35> A_RWL<34> A_RWL<33> A_RWL<32> A_RWL<31> A_RWL<30> A_RWL<29> A_RWL<28> A_RWL<27> A_RWL<26> A_RWL<25> A_RWL<24> A_RWL<23> A_RWL<22> A_RWL<21> A_RWL<20> A_RWL<19> A_RWL<18> A_RWL<17> A_RWL<16> A_RWL<15> A_RWL<14> A_RWL<13> A_RWL<12> A_RWL<11> A_RWL<10> A_RWL<9> A_RWL<8> A_RWL<7> A_RWL<6> A_RWL<5> A_RWL<4> A_RWL<3> A_RWL<2> A_RWL<1> A_RWL<0> VDD_CORE VSS +XRAM<4> A_BLC<5> A_BLC<4> A_BLC_TOP<1> A_BLC_TOP<0> A_BLT<5> A_BLT<4> A_BLT_TOP<1> A_BLT_TOP<0> A_LWL<63> A_LWL<62> A_LWL<61> A_LWL<60> A_LWL<59> A_LWL<58> A_LWL<57> A_LWL<56> A_LWL<55> A_LWL<54> A_LWL<53> A_LWL<52> A_LWL<51> A_LWL<50> A_LWL<49> A_LWL<48> A_RWL<63> A_RWL<62> A_RWL<61> A_RWL<60> A_RWL<59> A_RWL<58> A_RWL<57> A_RWL<56> A_RWL<55> A_RWL<54> A_RWL<53> A_RWL<52> A_RWL<51> A_RWL<50> A_RWL<49> A_RWL<48> VDD_CORE VSS / RM_IHPSG13_512x8_c3_1P_BITKIT_16x2_SRAM +XRAM<3> A_BLC<3> A_BLC<2> A_BLC<5> A_BLC<4> A_BLT<3> A_BLT<2> A_BLT<5> A_BLT<4> A_LWL<47> A_LWL<46> A_LWL<45> A_LWL<44> A_LWL<43> A_LWL<42> A_LWL<41> A_LWL<40> A_LWL<39> A_LWL<38> A_LWL<37> A_LWL<36> A_LWL<35> A_LWL<34> A_LWL<33> A_LWL<32> A_RWL<47> A_RWL<46> A_RWL<45> A_RWL<44> A_RWL<43> A_RWL<42> A_RWL<41> A_RWL<40> A_RWL<39> A_RWL<38> A_RWL<37> A_RWL<36> A_RWL<35> A_RWL<34> A_RWL<33> A_RWL<32> VDD_CORE VSS / RM_IHPSG13_512x8_c3_1P_BITKIT_16x2_SRAM +XRAM<2> A_BLC<1> A_BLC<0> A_BLC<3> A_BLC<2> A_BLT<1> A_BLT<0> A_BLT<3> A_BLT<2> A_LWL<31> A_LWL<30> A_LWL<29> A_LWL<28> A_LWL<27> A_LWL<26> A_LWL<25> A_LWL<24> A_LWL<23> A_LWL<22> A_LWL<21> A_LWL<20> A_LWL<19> A_LWL<18> A_LWL<17> A_LWL<16> A_RWL<31> A_RWL<30> A_RWL<29> A_RWL<28> A_RWL<27> A_RWL<26> A_RWL<25> A_RWL<24> A_RWL<23> A_RWL<22> A_RWL<21> A_RWL<20> A_RWL<19> A_RWL<18> A_RWL<17> A_RWL<16> VDD_CORE VSS / RM_IHPSG13_512x8_c3_1P_BITKIT_16x2_SRAM +XRAM<1> A_BLC_BOT<1> A_BLC_BOT<0> A_BLC<1> A_BLC<0> A_BLT_BOT<1> A_BLT_BOT<0> A_BLT<1> A_BLT<0> A_LWL<15> A_LWL<14> A_LWL<13> A_LWL<12> A_LWL<11> A_LWL<10> A_LWL<9> A_LWL<8> A_LWL<7> A_LWL<6> A_LWL<5> A_LWL<4> A_LWL<3> A_LWL<2> A_LWL<1> A_LWL<0> A_RWL<15> A_RWL<14> A_RWL<13> A_RWL<12> A_RWL<11> A_RWL<10> A_RWL<9> A_RWL<8> A_RWL<7> A_RWL<6> A_RWL<5> A_RWL<4> A_RWL<3> A_RWL<2> A_RWL<1> A_RWL<0> VDD_CORE VSS / RM_IHPSG13_512x8_c3_1P_BITKIT_16x2_SRAM +XEDGE<1> A_BLC_TOP<1> A_BLC_TOP<0> A_BLT_TOP<1> A_BLT_TOP<0> VDD_CORE VSS / RM_IHPSG13_512x8_c3_1P_BITKIT_16x2_EDGE_TB +XEDGE<0> A_BLC_BOT<1> A_BLC_BOT<0> A_BLT_BOT<1> A_BLT_BOT<0> VDD_CORE VSS / RM_IHPSG13_512x8_c3_1P_BITKIT_16x2_EDGE_TB +.ENDS + + + + +.SUBCKT RM_IHPSG13_512x8_c3_1P_MATRIX_pcell_1 A_BLC<31> A_BLC<30> A_BLC<29> A_BLC<28> A_BLC<27> A_BLC<26> A_BLC<25> A_BLC<24> A_BLC<23> A_BLC<22> A_BLC<21> A_BLC<20> A_BLC<19> A_BLC<18> A_BLC<17> A_BLC<16> A_BLC<15> A_BLC<14> A_BLC<13> A_BLC<12> A_BLC<11> A_BLC<10> A_BLC<9> A_BLC<8> A_BLC<7> A_BLC<6> A_BLC<5> A_BLC<4> A_BLC<3> A_BLC<2> A_BLC<1> A_BLC<0> A_BLT<31> A_BLT<30> A_BLT<29> A_BLT<28> A_BLT<27> A_BLT<26> A_BLT<25> A_BLT<24> A_BLT<23> A_BLT<22> A_BLT<21> A_BLT<20> A_BLT<19> A_BLT<18> A_BLT<17> A_BLT<16> A_BLT<15> A_BLT<14> A_BLT<13> A_BLT<12> A_BLT<11> A_BLT<10> A_BLT<9> A_BLT<8> A_BLT<7> A_BLT<6> A_BLT<5> A_BLT<4> A_BLT<3> A_BLT<2> A_BLT<1> A_BLT<0> A_WL<63> A_WL<62> A_WL<61> A_WL<60> A_WL<59> A_WL<58> A_WL<57> A_WL<56> A_WL<55> A_WL<54> A_WL<53> A_WL<52> A_WL<51> A_WL<50> A_WL<49> A_WL<48> A_WL<47> A_WL<46> A_WL<45> A_WL<44> A_WL<43> A_WL<42> A_WL<41> A_WL<40> A_WL<39> A_WL<38> A_WL<37> A_WL<36> A_WL<35> A_WL<34> A_WL<33> A_WL<32> A_WL<31> A_WL<30> A_WL<29> A_WL<28> A_WL<27> A_WL<26> A_WL<25> A_WL<24> A_WL<23> A_WL<22> A_WL<21> A_WL<20> A_WL<19> A_WL<18> A_WL<17> A_WL<16> A_WL<15> A_WL<14> A_WL<13> A_WL<12> A_WL<11> A_WL<10> A_WL<9> A_WL<8> A_WL<7> A_WL<6> A_WL<5> A_WL<4> A_WL<3> A_WL<2> A_WL<1> A_WL<0> VDD_CORE VSS +XCORNER<3> VDD_CORE VSS / RM_IHPSG13_512x8_c3_1P_BITKIT_16x2_CORNER +XCORNER<2> VDD_CORE VSS / RM_IHPSG13_512x8_c3_1P_BITKIT_16x2_CORNER +XCORNER<1> VDD_CORE VSS / RM_IHPSG13_512x8_c3_1P_BITKIT_16x2_CORNER +XCORNER<0> VDD_CORE VSS / RM_IHPSG13_512x8_c3_1P_BITKIT_16x2_CORNER +XRAMEDGE_L<3> A_WL<63> A_WL<62> A_WL<61> A_WL<60> A_WL<59> A_WL<58> A_WL<57> A_WL<56> A_WL<55> A_WL<54> A_WL<53> A_WL<52> A_WL<51> A_WL<50> A_WL<49> A_WL<48> VDD_CORE VSS / RM_IHPSG13_512x8_c3_1P_BITKIT_16x2_EDGE_LR +XRAMEDGE_L<2> A_WL<47> A_WL<46> A_WL<45> A_WL<44> A_WL<43> A_WL<42> A_WL<41> A_WL<40> A_WL<39> A_WL<38> A_WL<37> A_WL<36> A_WL<35> A_WL<34> A_WL<33> A_WL<32> VDD_CORE VSS / RM_IHPSG13_512x8_c3_1P_BITKIT_16x2_EDGE_LR +XRAMEDGE_L<1> A_WL<31> A_WL<30> A_WL<29> A_WL<28> A_WL<27> A_WL<26> A_WL<25> A_WL<24> A_WL<23> A_WL<22> A_WL<21> A_WL<20> A_WL<19> A_WL<18> A_WL<17> A_WL<16> VDD_CORE VSS / RM_IHPSG13_512x8_c3_1P_BITKIT_16x2_EDGE_LR +XRAMEDGE_L<0> A_WL<15> A_WL<14> A_WL<13> A_WL<12> A_WL<11> A_WL<10> A_WL<9> A_WL<8> A_WL<7> A_WL<6> A_WL<5> A_WL<4> A_WL<3> A_WL<2> A_WL<1> A_WL<0> VDD_CORE VSS / RM_IHPSG13_512x8_c3_1P_BITKIT_16x2_EDGE_LR +XRAMEDGE_R<3> A_IWL<1023> A_IWL<1022> A_IWL<1021> A_IWL<1020> A_IWL<1019> A_IWL<1018> A_IWL<1017> A_IWL<1016> A_IWL<1015> A_IWL<1014> A_IWL<1013> A_IWL<1012> A_IWL<1011> A_IWL<1010> A_IWL<1009> A_IWL<1008> VDD_CORE VSS / RM_IHPSG13_512x8_c3_1P_BITKIT_16x2_EDGE_LR +XRAMEDGE_R<2> A_IWL<1007> A_IWL<1006> A_IWL<1005> A_IWL<1004> A_IWL<1003> A_IWL<1002> A_IWL<1001> A_IWL<1000> A_IWL<999> A_IWL<998> A_IWL<997> A_IWL<996> A_IWL<995> A_IWL<994> A_IWL<993> A_IWL<992> VDD_CORE VSS / RM_IHPSG13_512x8_c3_1P_BITKIT_16x2_EDGE_LR +XRAMEDGE_R<1> A_IWL<991> A_IWL<990> A_IWL<989> A_IWL<988> A_IWL<987> A_IWL<986> A_IWL<985> A_IWL<984> A_IWL<983> A_IWL<982> A_IWL<981> A_IWL<980> A_IWL<979> A_IWL<978> A_IWL<977> A_IWL<976> VDD_CORE VSS / RM_IHPSG13_512x8_c3_1P_BITKIT_16x2_EDGE_LR +XRAMEDGE_R<0> A_IWL<975> A_IWL<974> A_IWL<973> A_IWL<972> A_IWL<971> A_IWL<970> A_IWL<969> A_IWL<968> A_IWL<967> A_IWL<966> A_IWL<965> A_IWL<964> A_IWL<963> A_IWL<962> A_IWL<961> A_IWL<960> VDD_CORE VSS / RM_IHPSG13_512x8_c3_1P_BITKIT_16x2_EDGE_LR +XCOL<15> A_BLC<31> A_BLC<30> A_BLC_TOP<31> A_BLC_TOP<30> A_BLT<31> A_BLT<30> A_BLT_TOP<31> A_BLT_TOP<30> A_IWL<959> A_IWL<958> A_IWL<957> A_IWL<956> A_IWL<955> A_IWL<954> A_IWL<953> A_IWL<952> A_IWL<951> A_IWL<950> A_IWL<949> A_IWL<948> A_IWL<947> A_IWL<946> A_IWL<945> A_IWL<944> A_IWL<943> A_IWL<942> A_IWL<941> A_IWL<940> A_IWL<939> A_IWL<938> A_IWL<937> A_IWL<936> A_IWL<935> A_IWL<934> A_IWL<933> A_IWL<932> A_IWL<931> A_IWL<930> A_IWL<929> A_IWL<928> A_IWL<927> A_IWL<926> A_IWL<925> A_IWL<924> A_IWL<923> A_IWL<922> A_IWL<921> A_IWL<920> A_IWL<919> A_IWL<918> A_IWL<917> A_IWL<916> A_IWL<915> A_IWL<914> A_IWL<913> A_IWL<912> A_IWL<911> A_IWL<910> A_IWL<909> A_IWL<908> A_IWL<907> A_IWL<906> A_IWL<905> A_IWL<904> A_IWL<903> A_IWL<902> A_IWL<901> A_IWL<900> A_IWL<899> A_IWL<898> A_IWL<897> A_IWL<896> A_IWL<1023> A_IWL<1022> A_IWL<1021> A_IWL<1020> A_IWL<1019> A_IWL<1018> A_IWL<1017> A_IWL<1016> A_IWL<1015> A_IWL<1014> A_IWL<1013> A_IWL<1012> A_IWL<1011> A_IWL<1010> A_IWL<1009> A_IWL<1008> A_IWL<1007> A_IWL<1006> A_IWL<1005> A_IWL<1004> A_IWL<1003> A_IWL<1002> A_IWL<1001> A_IWL<1000> A_IWL<999> A_IWL<998> A_IWL<997> A_IWL<996> A_IWL<995> A_IWL<994> A_IWL<993> A_IWL<992> A_IWL<991> A_IWL<990> A_IWL<989> A_IWL<988> A_IWL<987> A_IWL<986> A_IWL<985> A_IWL<984> A_IWL<983> A_IWL<982> A_IWL<981> A_IWL<980> A_IWL<979> A_IWL<978> A_IWL<977> A_IWL<976> A_IWL<975> A_IWL<974> A_IWL<973> A_IWL<972> A_IWL<971> A_IWL<970> A_IWL<969> A_IWL<968> A_IWL<967> A_IWL<966> A_IWL<965> A_IWL<964> A_IWL<963> A_IWL<962> A_IWL<961> A_IWL<960> VDD_CORE VSS / RM_IHPSG13_512x8_c3_1P_COLUMN_pcell_0 +XCOL<14> A_BLC<29> A_BLC<28> A_BLC_TOP<29> A_BLC_TOP<28> A_BLT<29> A_BLT<28> A_BLT_TOP<29> A_BLT_TOP<28> A_IWL<895> A_IWL<894> A_IWL<893> A_IWL<892> A_IWL<891> A_IWL<890> A_IWL<889> A_IWL<888> A_IWL<887> A_IWL<886> A_IWL<885> A_IWL<884> A_IWL<883> A_IWL<882> A_IWL<881> A_IWL<880> A_IWL<879> A_IWL<878> A_IWL<877> A_IWL<876> A_IWL<875> A_IWL<874> A_IWL<873> A_IWL<872> A_IWL<871> A_IWL<870> A_IWL<869> A_IWL<868> A_IWL<867> A_IWL<866> A_IWL<865> A_IWL<864> A_IWL<863> A_IWL<862> A_IWL<861> A_IWL<860> A_IWL<859> A_IWL<858> A_IWL<857> A_IWL<856> A_IWL<855> A_IWL<854> A_IWL<853> A_IWL<852> A_IWL<851> A_IWL<850> A_IWL<849> A_IWL<848> A_IWL<847> A_IWL<846> A_IWL<845> A_IWL<844> A_IWL<843> A_IWL<842> A_IWL<841> A_IWL<840> A_IWL<839> A_IWL<838> A_IWL<837> A_IWL<836> A_IWL<835> A_IWL<834> A_IWL<833> A_IWL<832> A_IWL<959> A_IWL<958> A_IWL<957> A_IWL<956> A_IWL<955> A_IWL<954> A_IWL<953> A_IWL<952> A_IWL<951> A_IWL<950> A_IWL<949> A_IWL<948> A_IWL<947> A_IWL<946> A_IWL<945> A_IWL<944> A_IWL<943> A_IWL<942> A_IWL<941> A_IWL<940> A_IWL<939> A_IWL<938> A_IWL<937> A_IWL<936> A_IWL<935> A_IWL<934> A_IWL<933> A_IWL<932> A_IWL<931> A_IWL<930> A_IWL<929> A_IWL<928> A_IWL<927> A_IWL<926> A_IWL<925> A_IWL<924> A_IWL<923> A_IWL<922> A_IWL<921> A_IWL<920> A_IWL<919> A_IWL<918> A_IWL<917> A_IWL<916> A_IWL<915> A_IWL<914> A_IWL<913> A_IWL<912> A_IWL<911> A_IWL<910> A_IWL<909> A_IWL<908> A_IWL<907> A_IWL<906> A_IWL<905> A_IWL<904> A_IWL<903> A_IWL<902> A_IWL<901> A_IWL<900> A_IWL<899> A_IWL<898> A_IWL<897> A_IWL<896> VDD_CORE VSS / RM_IHPSG13_512x8_c3_1P_COLUMN_pcell_0 +XCOL<13> A_BLC<27> A_BLC<26> A_BLC_TOP<27> A_BLC_TOP<26> A_BLT<27> A_BLT<26> A_BLT_TOP<27> A_BLT_TOP<26> A_IWL<831> A_IWL<830> A_IWL<829> A_IWL<828> A_IWL<827> A_IWL<826> A_IWL<825> A_IWL<824> A_IWL<823> A_IWL<822> A_IWL<821> A_IWL<820> A_IWL<819> A_IWL<818> A_IWL<817> A_IWL<816> A_IWL<815> A_IWL<814> A_IWL<813> A_IWL<812> A_IWL<811> A_IWL<810> A_IWL<809> A_IWL<808> A_IWL<807> A_IWL<806> A_IWL<805> A_IWL<804> A_IWL<803> A_IWL<802> A_IWL<801> A_IWL<800> A_IWL<799> A_IWL<798> A_IWL<797> A_IWL<796> A_IWL<795> A_IWL<794> A_IWL<793> A_IWL<792> A_IWL<791> A_IWL<790> A_IWL<789> A_IWL<788> A_IWL<787> A_IWL<786> A_IWL<785> A_IWL<784> A_IWL<783> A_IWL<782> A_IWL<781> A_IWL<780> A_IWL<779> A_IWL<778> A_IWL<777> A_IWL<776> A_IWL<775> A_IWL<774> A_IWL<773> A_IWL<772> A_IWL<771> A_IWL<770> A_IWL<769> A_IWL<768> A_IWL<895> A_IWL<894> A_IWL<893> A_IWL<892> A_IWL<891> A_IWL<890> A_IWL<889> A_IWL<888> A_IWL<887> A_IWL<886> A_IWL<885> A_IWL<884> A_IWL<883> A_IWL<882> A_IWL<881> A_IWL<880> A_IWL<879> A_IWL<878> A_IWL<877> A_IWL<876> A_IWL<875> A_IWL<874> A_IWL<873> A_IWL<872> A_IWL<871> A_IWL<870> A_IWL<869> A_IWL<868> A_IWL<867> A_IWL<866> A_IWL<865> A_IWL<864> A_IWL<863> A_IWL<862> A_IWL<861> A_IWL<860> A_IWL<859> A_IWL<858> A_IWL<857> A_IWL<856> A_IWL<855> A_IWL<854> A_IWL<853> A_IWL<852> A_IWL<851> A_IWL<850> A_IWL<849> A_IWL<848> A_IWL<847> A_IWL<846> A_IWL<845> A_IWL<844> A_IWL<843> A_IWL<842> A_IWL<841> A_IWL<840> A_IWL<839> A_IWL<838> A_IWL<837> A_IWL<836> A_IWL<835> A_IWL<834> A_IWL<833> A_IWL<832> VDD_CORE VSS / RM_IHPSG13_512x8_c3_1P_COLUMN_pcell_0 +XCOL<12> A_BLC<25> A_BLC<24> A_BLC_TOP<25> A_BLC_TOP<24> A_BLT<25> A_BLT<24> A_BLT_TOP<25> A_BLT_TOP<24> A_IWL<767> A_IWL<766> A_IWL<765> A_IWL<764> A_IWL<763> A_IWL<762> A_IWL<761> A_IWL<760> A_IWL<759> A_IWL<758> A_IWL<757> A_IWL<756> A_IWL<755> A_IWL<754> A_IWL<753> A_IWL<752> A_IWL<751> A_IWL<750> A_IWL<749> A_IWL<748> A_IWL<747> A_IWL<746> A_IWL<745> A_IWL<744> A_IWL<743> A_IWL<742> A_IWL<741> A_IWL<740> A_IWL<739> A_IWL<738> A_IWL<737> A_IWL<736> A_IWL<735> A_IWL<734> A_IWL<733> A_IWL<732> A_IWL<731> A_IWL<730> A_IWL<729> A_IWL<728> A_IWL<727> A_IWL<726> A_IWL<725> A_IWL<724> A_IWL<723> A_IWL<722> A_IWL<721> A_IWL<720> A_IWL<719> A_IWL<718> A_IWL<717> A_IWL<716> A_IWL<715> A_IWL<714> A_IWL<713> A_IWL<712> A_IWL<711> A_IWL<710> A_IWL<709> A_IWL<708> A_IWL<707> A_IWL<706> A_IWL<705> A_IWL<704> A_IWL<831> A_IWL<830> A_IWL<829> A_IWL<828> A_IWL<827> A_IWL<826> A_IWL<825> A_IWL<824> A_IWL<823> A_IWL<822> A_IWL<821> A_IWL<820> A_IWL<819> A_IWL<818> A_IWL<817> A_IWL<816> A_IWL<815> A_IWL<814> A_IWL<813> A_IWL<812> A_IWL<811> A_IWL<810> A_IWL<809> A_IWL<808> A_IWL<807> A_IWL<806> A_IWL<805> A_IWL<804> A_IWL<803> A_IWL<802> A_IWL<801> A_IWL<800> A_IWL<799> A_IWL<798> A_IWL<797> A_IWL<796> A_IWL<795> A_IWL<794> A_IWL<793> A_IWL<792> A_IWL<791> A_IWL<790> A_IWL<789> A_IWL<788> A_IWL<787> A_IWL<786> A_IWL<785> A_IWL<784> A_IWL<783> A_IWL<782> A_IWL<781> A_IWL<780> A_IWL<779> A_IWL<778> A_IWL<777> A_IWL<776> A_IWL<775> A_IWL<774> A_IWL<773> A_IWL<772> A_IWL<771> A_IWL<770> A_IWL<769> A_IWL<768> VDD_CORE VSS / RM_IHPSG13_512x8_c3_1P_COLUMN_pcell_0 +XCOL<11> A_BLC<23> A_BLC<22> A_BLC_TOP<23> A_BLC_TOP<22> A_BLT<23> A_BLT<22> A_BLT_TOP<23> A_BLT_TOP<22> A_IWL<703> A_IWL<702> A_IWL<701> A_IWL<700> A_IWL<699> A_IWL<698> A_IWL<697> A_IWL<696> A_IWL<695> A_IWL<694> A_IWL<693> A_IWL<692> A_IWL<691> A_IWL<690> A_IWL<689> A_IWL<688> A_IWL<687> A_IWL<686> A_IWL<685> A_IWL<684> A_IWL<683> A_IWL<682> A_IWL<681> A_IWL<680> A_IWL<679> A_IWL<678> A_IWL<677> A_IWL<676> A_IWL<675> A_IWL<674> A_IWL<673> A_IWL<672> A_IWL<671> A_IWL<670> A_IWL<669> A_IWL<668> A_IWL<667> A_IWL<666> A_IWL<665> A_IWL<664> A_IWL<663> A_IWL<662> A_IWL<661> A_IWL<660> A_IWL<659> A_IWL<658> A_IWL<657> A_IWL<656> A_IWL<655> A_IWL<654> A_IWL<653> A_IWL<652> A_IWL<651> A_IWL<650> A_IWL<649> A_IWL<648> A_IWL<647> A_IWL<646> A_IWL<645> A_IWL<644> A_IWL<643> A_IWL<642> A_IWL<641> A_IWL<640> A_IWL<767> A_IWL<766> A_IWL<765> A_IWL<764> A_IWL<763> A_IWL<762> A_IWL<761> A_IWL<760> A_IWL<759> A_IWL<758> A_IWL<757> A_IWL<756> A_IWL<755> A_IWL<754> A_IWL<753> A_IWL<752> A_IWL<751> A_IWL<750> A_IWL<749> A_IWL<748> A_IWL<747> A_IWL<746> A_IWL<745> A_IWL<744> A_IWL<743> A_IWL<742> A_IWL<741> A_IWL<740> A_IWL<739> A_IWL<738> A_IWL<737> A_IWL<736> A_IWL<735> A_IWL<734> A_IWL<733> A_IWL<732> A_IWL<731> A_IWL<730> A_IWL<729> A_IWL<728> A_IWL<727> A_IWL<726> A_IWL<725> A_IWL<724> A_IWL<723> A_IWL<722> A_IWL<721> A_IWL<720> A_IWL<719> A_IWL<718> A_IWL<717> A_IWL<716> A_IWL<715> A_IWL<714> A_IWL<713> A_IWL<712> A_IWL<711> A_IWL<710> A_IWL<709> A_IWL<708> A_IWL<707> A_IWL<706> A_IWL<705> A_IWL<704> VDD_CORE VSS / RM_IHPSG13_512x8_c3_1P_COLUMN_pcell_0 +XCOL<10> A_BLC<21> A_BLC<20> A_BLC_TOP<21> A_BLC_TOP<20> A_BLT<21> A_BLT<20> A_BLT_TOP<21> A_BLT_TOP<20> A_IWL<639> A_IWL<638> A_IWL<637> A_IWL<636> A_IWL<635> A_IWL<634> A_IWL<633> A_IWL<632> A_IWL<631> A_IWL<630> A_IWL<629> A_IWL<628> A_IWL<627> A_IWL<626> A_IWL<625> A_IWL<624> A_IWL<623> A_IWL<622> A_IWL<621> A_IWL<620> A_IWL<619> A_IWL<618> A_IWL<617> A_IWL<616> A_IWL<615> A_IWL<614> A_IWL<613> A_IWL<612> A_IWL<611> A_IWL<610> A_IWL<609> A_IWL<608> A_IWL<607> A_IWL<606> A_IWL<605> A_IWL<604> A_IWL<603> A_IWL<602> A_IWL<601> A_IWL<600> A_IWL<599> A_IWL<598> A_IWL<597> A_IWL<596> A_IWL<595> A_IWL<594> A_IWL<593> A_IWL<592> A_IWL<591> A_IWL<590> A_IWL<589> A_IWL<588> A_IWL<587> A_IWL<586> A_IWL<585> A_IWL<584> A_IWL<583> A_IWL<582> A_IWL<581> A_IWL<580> A_IWL<579> A_IWL<578> A_IWL<577> A_IWL<576> A_IWL<703> A_IWL<702> A_IWL<701> A_IWL<700> A_IWL<699> A_IWL<698> A_IWL<697> A_IWL<696> A_IWL<695> A_IWL<694> A_IWL<693> A_IWL<692> A_IWL<691> A_IWL<690> A_IWL<689> A_IWL<688> A_IWL<687> A_IWL<686> A_IWL<685> A_IWL<684> A_IWL<683> A_IWL<682> A_IWL<681> A_IWL<680> A_IWL<679> A_IWL<678> A_IWL<677> A_IWL<676> A_IWL<675> A_IWL<674> A_IWL<673> A_IWL<672> A_IWL<671> A_IWL<670> A_IWL<669> A_IWL<668> A_IWL<667> A_IWL<666> A_IWL<665> A_IWL<664> A_IWL<663> A_IWL<662> A_IWL<661> A_IWL<660> A_IWL<659> A_IWL<658> A_IWL<657> A_IWL<656> A_IWL<655> A_IWL<654> A_IWL<653> A_IWL<652> A_IWL<651> A_IWL<650> A_IWL<649> A_IWL<648> A_IWL<647> A_IWL<646> A_IWL<645> A_IWL<644> A_IWL<643> A_IWL<642> A_IWL<641> A_IWL<640> VDD_CORE VSS / RM_IHPSG13_512x8_c3_1P_COLUMN_pcell_0 +XCOL<9> A_BLC<19> A_BLC<18> A_BLC_TOP<19> A_BLC_TOP<18> A_BLT<19> A_BLT<18> A_BLT_TOP<19> A_BLT_TOP<18> A_IWL<575> A_IWL<574> A_IWL<573> A_IWL<572> A_IWL<571> A_IWL<570> A_IWL<569> A_IWL<568> A_IWL<567> A_IWL<566> A_IWL<565> A_IWL<564> A_IWL<563> A_IWL<562> A_IWL<561> A_IWL<560> A_IWL<559> A_IWL<558> A_IWL<557> A_IWL<556> A_IWL<555> A_IWL<554> A_IWL<553> A_IWL<552> A_IWL<551> A_IWL<550> A_IWL<549> A_IWL<548> A_IWL<547> A_IWL<546> A_IWL<545> A_IWL<544> A_IWL<543> A_IWL<542> A_IWL<541> A_IWL<540> A_IWL<539> A_IWL<538> A_IWL<537> A_IWL<536> A_IWL<535> A_IWL<534> A_IWL<533> A_IWL<532> A_IWL<531> A_IWL<530> A_IWL<529> A_IWL<528> A_IWL<527> A_IWL<526> A_IWL<525> A_IWL<524> A_IWL<523> A_IWL<522> A_IWL<521> A_IWL<520> A_IWL<519> A_IWL<518> A_IWL<517> A_IWL<516> A_IWL<515> A_IWL<514> A_IWL<513> A_IWL<512> A_IWL<639> A_IWL<638> A_IWL<637> A_IWL<636> A_IWL<635> A_IWL<634> A_IWL<633> A_IWL<632> A_IWL<631> A_IWL<630> A_IWL<629> A_IWL<628> A_IWL<627> A_IWL<626> A_IWL<625> A_IWL<624> A_IWL<623> A_IWL<622> A_IWL<621> A_IWL<620> A_IWL<619> A_IWL<618> A_IWL<617> A_IWL<616> A_IWL<615> A_IWL<614> A_IWL<613> A_IWL<612> A_IWL<611> A_IWL<610> A_IWL<609> A_IWL<608> A_IWL<607> A_IWL<606> A_IWL<605> A_IWL<604> A_IWL<603> A_IWL<602> A_IWL<601> A_IWL<600> A_IWL<599> A_IWL<598> A_IWL<597> A_IWL<596> A_IWL<595> A_IWL<594> A_IWL<593> A_IWL<592> A_IWL<591> A_IWL<590> A_IWL<589> A_IWL<588> A_IWL<587> A_IWL<586> A_IWL<585> A_IWL<584> A_IWL<583> A_IWL<582> A_IWL<581> A_IWL<580> A_IWL<579> A_IWL<578> A_IWL<577> A_IWL<576> VDD_CORE VSS / RM_IHPSG13_512x8_c3_1P_COLUMN_pcell_0 +XCOL<8> A_BLC<17> A_BLC<16> A_BLC_TOP<17> A_BLC_TOP<16> A_BLT<17> A_BLT<16> A_BLT_TOP<17> A_BLT_TOP<16> A_IWL<511> A_IWL<510> A_IWL<509> A_IWL<508> A_IWL<507> A_IWL<506> A_IWL<505> A_IWL<504> A_IWL<503> A_IWL<502> A_IWL<501> A_IWL<500> A_IWL<499> A_IWL<498> A_IWL<497> A_IWL<496> A_IWL<495> A_IWL<494> A_IWL<493> A_IWL<492> A_IWL<491> A_IWL<490> A_IWL<489> A_IWL<488> A_IWL<487> A_IWL<486> A_IWL<485> A_IWL<484> A_IWL<483> A_IWL<482> A_IWL<481> A_IWL<480> A_IWL<479> A_IWL<478> A_IWL<477> A_IWL<476> A_IWL<475> A_IWL<474> A_IWL<473> A_IWL<472> A_IWL<471> A_IWL<470> A_IWL<469> A_IWL<468> A_IWL<467> A_IWL<466> A_IWL<465> A_IWL<464> A_IWL<463> A_IWL<462> A_IWL<461> A_IWL<460> A_IWL<459> A_IWL<458> A_IWL<457> A_IWL<456> A_IWL<455> A_IWL<454> A_IWL<453> A_IWL<452> A_IWL<451> A_IWL<450> A_IWL<449> A_IWL<448> A_IWL<575> A_IWL<574> A_IWL<573> A_IWL<572> A_IWL<571> A_IWL<570> A_IWL<569> A_IWL<568> A_IWL<567> A_IWL<566> A_IWL<565> A_IWL<564> A_IWL<563> A_IWL<562> A_IWL<561> A_IWL<560> A_IWL<559> A_IWL<558> A_IWL<557> A_IWL<556> A_IWL<555> A_IWL<554> A_IWL<553> A_IWL<552> A_IWL<551> A_IWL<550> A_IWL<549> A_IWL<548> A_IWL<547> A_IWL<546> A_IWL<545> A_IWL<544> A_IWL<543> A_IWL<542> A_IWL<541> A_IWL<540> A_IWL<539> A_IWL<538> A_IWL<537> A_IWL<536> A_IWL<535> A_IWL<534> A_IWL<533> A_IWL<532> A_IWL<531> A_IWL<530> A_IWL<529> A_IWL<528> A_IWL<527> A_IWL<526> A_IWL<525> A_IWL<524> A_IWL<523> A_IWL<522> A_IWL<521> A_IWL<520> A_IWL<519> A_IWL<518> A_IWL<517> A_IWL<516> A_IWL<515> A_IWL<514> A_IWL<513> A_IWL<512> VDD_CORE VSS / RM_IHPSG13_512x8_c3_1P_COLUMN_pcell_0 +XCOL<7> A_BLC<15> A_BLC<14> A_BLC_TOP<15> A_BLC_TOP<14> A_BLT<15> A_BLT<14> A_BLT_TOP<15> A_BLT_TOP<14> A_IWL<447> A_IWL<446> A_IWL<445> A_IWL<444> A_IWL<443> A_IWL<442> A_IWL<441> A_IWL<440> A_IWL<439> A_IWL<438> A_IWL<437> A_IWL<436> A_IWL<435> A_IWL<434> A_IWL<433> A_IWL<432> A_IWL<431> A_IWL<430> A_IWL<429> A_IWL<428> A_IWL<427> A_IWL<426> A_IWL<425> A_IWL<424> A_IWL<423> A_IWL<422> A_IWL<421> A_IWL<420> A_IWL<419> A_IWL<418> A_IWL<417> A_IWL<416> A_IWL<415> A_IWL<414> A_IWL<413> A_IWL<412> A_IWL<411> A_IWL<410> A_IWL<409> A_IWL<408> A_IWL<407> A_IWL<406> A_IWL<405> A_IWL<404> A_IWL<403> A_IWL<402> A_IWL<401> A_IWL<400> A_IWL<399> A_IWL<398> A_IWL<397> A_IWL<396> A_IWL<395> A_IWL<394> A_IWL<393> A_IWL<392> A_IWL<391> A_IWL<390> A_IWL<389> A_IWL<388> A_IWL<387> A_IWL<386> A_IWL<385> A_IWL<384> A_IWL<511> A_IWL<510> A_IWL<509> A_IWL<508> A_IWL<507> A_IWL<506> A_IWL<505> A_IWL<504> A_IWL<503> A_IWL<502> A_IWL<501> A_IWL<500> A_IWL<499> A_IWL<498> A_IWL<497> A_IWL<496> A_IWL<495> A_IWL<494> A_IWL<493> A_IWL<492> A_IWL<491> A_IWL<490> A_IWL<489> A_IWL<488> A_IWL<487> A_IWL<486> A_IWL<485> A_IWL<484> A_IWL<483> A_IWL<482> A_IWL<481> A_IWL<480> A_IWL<479> A_IWL<478> A_IWL<477> A_IWL<476> A_IWL<475> A_IWL<474> A_IWL<473> A_IWL<472> A_IWL<471> A_IWL<470> A_IWL<469> A_IWL<468> A_IWL<467> A_IWL<466> A_IWL<465> A_IWL<464> A_IWL<463> A_IWL<462> A_IWL<461> A_IWL<460> A_IWL<459> A_IWL<458> A_IWL<457> A_IWL<456> A_IWL<455> A_IWL<454> A_IWL<453> A_IWL<452> A_IWL<451> A_IWL<450> A_IWL<449> A_IWL<448> VDD_CORE VSS / RM_IHPSG13_512x8_c3_1P_COLUMN_pcell_0 +XCOL<6> A_BLC<13> A_BLC<12> A_BLC_TOP<13> A_BLC_TOP<12> A_BLT<13> A_BLT<12> A_BLT_TOP<13> A_BLT_TOP<12> A_IWL<383> A_IWL<382> A_IWL<381> A_IWL<380> A_IWL<379> A_IWL<378> A_IWL<377> A_IWL<376> A_IWL<375> A_IWL<374> A_IWL<373> A_IWL<372> A_IWL<371> A_IWL<370> A_IWL<369> A_IWL<368> A_IWL<367> A_IWL<366> A_IWL<365> A_IWL<364> A_IWL<363> A_IWL<362> A_IWL<361> A_IWL<360> A_IWL<359> A_IWL<358> A_IWL<357> A_IWL<356> A_IWL<355> A_IWL<354> A_IWL<353> A_IWL<352> A_IWL<351> A_IWL<350> A_IWL<349> A_IWL<348> A_IWL<347> A_IWL<346> A_IWL<345> A_IWL<344> A_IWL<343> A_IWL<342> A_IWL<341> A_IWL<340> A_IWL<339> A_IWL<338> A_IWL<337> A_IWL<336> A_IWL<335> A_IWL<334> A_IWL<333> A_IWL<332> A_IWL<331> A_IWL<330> A_IWL<329> A_IWL<328> A_IWL<327> A_IWL<326> A_IWL<325> A_IWL<324> A_IWL<323> A_IWL<322> A_IWL<321> A_IWL<320> A_IWL<447> A_IWL<446> A_IWL<445> A_IWL<444> A_IWL<443> A_IWL<442> A_IWL<441> A_IWL<440> A_IWL<439> A_IWL<438> A_IWL<437> A_IWL<436> A_IWL<435> A_IWL<434> A_IWL<433> A_IWL<432> A_IWL<431> A_IWL<430> A_IWL<429> A_IWL<428> A_IWL<427> A_IWL<426> A_IWL<425> A_IWL<424> A_IWL<423> A_IWL<422> A_IWL<421> A_IWL<420> A_IWL<419> A_IWL<418> A_IWL<417> A_IWL<416> A_IWL<415> A_IWL<414> A_IWL<413> A_IWL<412> A_IWL<411> A_IWL<410> A_IWL<409> A_IWL<408> A_IWL<407> A_IWL<406> A_IWL<405> A_IWL<404> A_IWL<403> A_IWL<402> A_IWL<401> A_IWL<400> A_IWL<399> A_IWL<398> A_IWL<397> A_IWL<396> A_IWL<395> A_IWL<394> A_IWL<393> A_IWL<392> A_IWL<391> A_IWL<390> A_IWL<389> A_IWL<388> A_IWL<387> A_IWL<386> A_IWL<385> A_IWL<384> VDD_CORE VSS / RM_IHPSG13_512x8_c3_1P_COLUMN_pcell_0 +XCOL<5> A_BLC<11> A_BLC<10> A_BLC_TOP<11> A_BLC_TOP<10> A_BLT<11> A_BLT<10> A_BLT_TOP<11> A_BLT_TOP<10> A_IWL<319> A_IWL<318> A_IWL<317> A_IWL<316> A_IWL<315> A_IWL<314> A_IWL<313> A_IWL<312> A_IWL<311> A_IWL<310> A_IWL<309> A_IWL<308> A_IWL<307> A_IWL<306> A_IWL<305> A_IWL<304> A_IWL<303> A_IWL<302> A_IWL<301> A_IWL<300> A_IWL<299> A_IWL<298> A_IWL<297> A_IWL<296> A_IWL<295> A_IWL<294> A_IWL<293> A_IWL<292> A_IWL<291> A_IWL<290> A_IWL<289> A_IWL<288> A_IWL<287> A_IWL<286> A_IWL<285> A_IWL<284> A_IWL<283> A_IWL<282> A_IWL<281> A_IWL<280> A_IWL<279> A_IWL<278> A_IWL<277> A_IWL<276> A_IWL<275> A_IWL<274> A_IWL<273> A_IWL<272> A_IWL<271> A_IWL<270> A_IWL<269> A_IWL<268> A_IWL<267> A_IWL<266> A_IWL<265> A_IWL<264> A_IWL<263> A_IWL<262> A_IWL<261> A_IWL<260> A_IWL<259> A_IWL<258> A_IWL<257> A_IWL<256> A_IWL<383> A_IWL<382> A_IWL<381> A_IWL<380> A_IWL<379> A_IWL<378> A_IWL<377> A_IWL<376> A_IWL<375> A_IWL<374> A_IWL<373> A_IWL<372> A_IWL<371> A_IWL<370> A_IWL<369> A_IWL<368> A_IWL<367> A_IWL<366> A_IWL<365> A_IWL<364> A_IWL<363> A_IWL<362> A_IWL<361> A_IWL<360> A_IWL<359> A_IWL<358> A_IWL<357> A_IWL<356> A_IWL<355> A_IWL<354> A_IWL<353> A_IWL<352> A_IWL<351> A_IWL<350> A_IWL<349> A_IWL<348> A_IWL<347> A_IWL<346> A_IWL<345> A_IWL<344> A_IWL<343> A_IWL<342> A_IWL<341> A_IWL<340> A_IWL<339> A_IWL<338> A_IWL<337> A_IWL<336> A_IWL<335> A_IWL<334> A_IWL<333> A_IWL<332> A_IWL<331> A_IWL<330> A_IWL<329> A_IWL<328> A_IWL<327> A_IWL<326> A_IWL<325> A_IWL<324> A_IWL<323> A_IWL<322> A_IWL<321> A_IWL<320> VDD_CORE VSS / RM_IHPSG13_512x8_c3_1P_COLUMN_pcell_0 +XCOL<4> A_BLC<9> A_BLC<8> A_BLC_TOP<9> A_BLC_TOP<8> A_BLT<9> A_BLT<8> A_BLT_TOP<9> A_BLT_TOP<8> A_IWL<255> A_IWL<254> A_IWL<253> A_IWL<252> A_IWL<251> A_IWL<250> A_IWL<249> A_IWL<248> A_IWL<247> A_IWL<246> A_IWL<245> A_IWL<244> A_IWL<243> A_IWL<242> A_IWL<241> A_IWL<240> A_IWL<239> A_IWL<238> A_IWL<237> A_IWL<236> A_IWL<235> A_IWL<234> A_IWL<233> A_IWL<232> A_IWL<231> A_IWL<230> A_IWL<229> A_IWL<228> A_IWL<227> A_IWL<226> A_IWL<225> A_IWL<224> A_IWL<223> A_IWL<222> A_IWL<221> A_IWL<220> A_IWL<219> A_IWL<218> A_IWL<217> A_IWL<216> A_IWL<215> A_IWL<214> A_IWL<213> A_IWL<212> A_IWL<211> A_IWL<210> A_IWL<209> A_IWL<208> A_IWL<207> A_IWL<206> A_IWL<205> A_IWL<204> A_IWL<203> A_IWL<202> A_IWL<201> A_IWL<200> A_IWL<199> A_IWL<198> A_IWL<197> A_IWL<196> A_IWL<195> A_IWL<194> A_IWL<193> A_IWL<192> A_IWL<319> A_IWL<318> A_IWL<317> A_IWL<316> A_IWL<315> A_IWL<314> A_IWL<313> A_IWL<312> A_IWL<311> A_IWL<310> A_IWL<309> A_IWL<308> A_IWL<307> A_IWL<306> A_IWL<305> A_IWL<304> A_IWL<303> A_IWL<302> A_IWL<301> A_IWL<300> A_IWL<299> A_IWL<298> A_IWL<297> A_IWL<296> A_IWL<295> A_IWL<294> A_IWL<293> A_IWL<292> A_IWL<291> A_IWL<290> A_IWL<289> A_IWL<288> A_IWL<287> A_IWL<286> A_IWL<285> A_IWL<284> A_IWL<283> A_IWL<282> A_IWL<281> A_IWL<280> A_IWL<279> A_IWL<278> A_IWL<277> A_IWL<276> A_IWL<275> A_IWL<274> A_IWL<273> A_IWL<272> A_IWL<271> A_IWL<270> A_IWL<269> A_IWL<268> A_IWL<267> A_IWL<266> A_IWL<265> A_IWL<264> A_IWL<263> A_IWL<262> A_IWL<261> A_IWL<260> A_IWL<259> A_IWL<258> A_IWL<257> A_IWL<256> VDD_CORE VSS / RM_IHPSG13_512x8_c3_1P_COLUMN_pcell_0 +XCOL<3> A_BLC<7> A_BLC<6> A_BLC_TOP<7> A_BLC_TOP<6> A_BLT<7> A_BLT<6> A_BLT_TOP<7> A_BLT_TOP<6> A_IWL<191> A_IWL<190> A_IWL<189> A_IWL<188> A_IWL<187> A_IWL<186> A_IWL<185> A_IWL<184> A_IWL<183> A_IWL<182> A_IWL<181> A_IWL<180> A_IWL<179> A_IWL<178> A_IWL<177> A_IWL<176> A_IWL<175> A_IWL<174> A_IWL<173> A_IWL<172> A_IWL<171> A_IWL<170> A_IWL<169> A_IWL<168> A_IWL<167> A_IWL<166> A_IWL<165> A_IWL<164> A_IWL<163> A_IWL<162> A_IWL<161> A_IWL<160> A_IWL<159> A_IWL<158> A_IWL<157> A_IWL<156> A_IWL<155> A_IWL<154> A_IWL<153> A_IWL<152> A_IWL<151> A_IWL<150> A_IWL<149> A_IWL<148> A_IWL<147> A_IWL<146> A_IWL<145> A_IWL<144> A_IWL<143> A_IWL<142> A_IWL<141> A_IWL<140> A_IWL<139> A_IWL<138> A_IWL<137> A_IWL<136> A_IWL<135> A_IWL<134> A_IWL<133> A_IWL<132> A_IWL<131> A_IWL<130> A_IWL<129> A_IWL<128> A_IWL<255> A_IWL<254> A_IWL<253> A_IWL<252> A_IWL<251> A_IWL<250> A_IWL<249> A_IWL<248> A_IWL<247> A_IWL<246> A_IWL<245> A_IWL<244> A_IWL<243> A_IWL<242> A_IWL<241> A_IWL<240> A_IWL<239> A_IWL<238> A_IWL<237> A_IWL<236> A_IWL<235> A_IWL<234> A_IWL<233> A_IWL<232> A_IWL<231> A_IWL<230> A_IWL<229> A_IWL<228> A_IWL<227> A_IWL<226> A_IWL<225> A_IWL<224> A_IWL<223> A_IWL<222> A_IWL<221> A_IWL<220> A_IWL<219> A_IWL<218> A_IWL<217> A_IWL<216> A_IWL<215> A_IWL<214> A_IWL<213> A_IWL<212> A_IWL<211> A_IWL<210> A_IWL<209> A_IWL<208> A_IWL<207> A_IWL<206> A_IWL<205> A_IWL<204> A_IWL<203> A_IWL<202> A_IWL<201> A_IWL<200> A_IWL<199> A_IWL<198> A_IWL<197> A_IWL<196> A_IWL<195> A_IWL<194> A_IWL<193> A_IWL<192> VDD_CORE VSS / RM_IHPSG13_512x8_c3_1P_COLUMN_pcell_0 +XCOL<2> A_BLC<5> A_BLC<4> A_BLC_TOP<5> A_BLC_TOP<4> A_BLT<5> A_BLT<4> A_BLT_TOP<5> A_BLT_TOP<4> A_IWL<127> A_IWL<126> A_IWL<125> A_IWL<124> A_IWL<123> A_IWL<122> A_IWL<121> A_IWL<120> A_IWL<119> A_IWL<118> A_IWL<117> A_IWL<116> A_IWL<115> A_IWL<114> A_IWL<113> A_IWL<112> A_IWL<111> A_IWL<110> A_IWL<109> A_IWL<108> A_IWL<107> A_IWL<106> A_IWL<105> A_IWL<104> A_IWL<103> A_IWL<102> A_IWL<101> A_IWL<100> A_IWL<99> A_IWL<98> A_IWL<97> A_IWL<96> A_IWL<95> A_IWL<94> A_IWL<93> A_IWL<92> A_IWL<91> A_IWL<90> A_IWL<89> A_IWL<88> A_IWL<87> A_IWL<86> A_IWL<85> A_IWL<84> A_IWL<83> A_IWL<82> A_IWL<81> A_IWL<80> A_IWL<79> A_IWL<78> A_IWL<77> A_IWL<76> A_IWL<75> A_IWL<74> A_IWL<73> A_IWL<72> A_IWL<71> A_IWL<70> A_IWL<69> A_IWL<68> A_IWL<67> A_IWL<66> A_IWL<65> A_IWL<64> A_IWL<191> A_IWL<190> A_IWL<189> A_IWL<188> A_IWL<187> A_IWL<186> A_IWL<185> A_IWL<184> A_IWL<183> A_IWL<182> A_IWL<181> A_IWL<180> A_IWL<179> A_IWL<178> A_IWL<177> A_IWL<176> A_IWL<175> A_IWL<174> A_IWL<173> A_IWL<172> A_IWL<171> A_IWL<170> A_IWL<169> A_IWL<168> A_IWL<167> A_IWL<166> A_IWL<165> A_IWL<164> A_IWL<163> A_IWL<162> A_IWL<161> A_IWL<160> A_IWL<159> A_IWL<158> A_IWL<157> A_IWL<156> A_IWL<155> A_IWL<154> A_IWL<153> A_IWL<152> A_IWL<151> A_IWL<150> A_IWL<149> A_IWL<148> A_IWL<147> A_IWL<146> A_IWL<145> A_IWL<144> A_IWL<143> A_IWL<142> A_IWL<141> A_IWL<140> A_IWL<139> A_IWL<138> A_IWL<137> A_IWL<136> A_IWL<135> A_IWL<134> A_IWL<133> A_IWL<132> A_IWL<131> A_IWL<130> A_IWL<129> A_IWL<128> VDD_CORE VSS / RM_IHPSG13_512x8_c3_1P_COLUMN_pcell_0 +XCOL<1> A_BLC<3> A_BLC<2> A_BLC_TOP<3> A_BLC_TOP<2> A_BLT<3> A_BLT<2> A_BLT_TOP<3> A_BLT_TOP<2> A_IWL<63> A_IWL<62> A_IWL<61> A_IWL<60> A_IWL<59> A_IWL<58> A_IWL<57> A_IWL<56> A_IWL<55> A_IWL<54> A_IWL<53> A_IWL<52> A_IWL<51> A_IWL<50> A_IWL<49> A_IWL<48> A_IWL<47> A_IWL<46> A_IWL<45> A_IWL<44> A_IWL<43> A_IWL<42> A_IWL<41> A_IWL<40> A_IWL<39> A_IWL<38> A_IWL<37> A_IWL<36> A_IWL<35> A_IWL<34> A_IWL<33> A_IWL<32> A_IWL<31> A_IWL<30> A_IWL<29> A_IWL<28> A_IWL<27> A_IWL<26> A_IWL<25> A_IWL<24> A_IWL<23> A_IWL<22> A_IWL<21> A_IWL<20> A_IWL<19> A_IWL<18> A_IWL<17> A_IWL<16> A_IWL<15> A_IWL<14> A_IWL<13> A_IWL<12> A_IWL<11> A_IWL<10> A_IWL<9> A_IWL<8> A_IWL<7> A_IWL<6> A_IWL<5> A_IWL<4> A_IWL<3> A_IWL<2> A_IWL<1> A_IWL<0> A_IWL<127> A_IWL<126> A_IWL<125> A_IWL<124> A_IWL<123> A_IWL<122> A_IWL<121> A_IWL<120> A_IWL<119> A_IWL<118> A_IWL<117> A_IWL<116> A_IWL<115> A_IWL<114> A_IWL<113> A_IWL<112> A_IWL<111> A_IWL<110> A_IWL<109> A_IWL<108> A_IWL<107> A_IWL<106> A_IWL<105> A_IWL<104> A_IWL<103> A_IWL<102> A_IWL<101> A_IWL<100> A_IWL<99> A_IWL<98> A_IWL<97> A_IWL<96> A_IWL<95> A_IWL<94> A_IWL<93> A_IWL<92> A_IWL<91> A_IWL<90> A_IWL<89> A_IWL<88> A_IWL<87> A_IWL<86> A_IWL<85> A_IWL<84> A_IWL<83> A_IWL<82> A_IWL<81> A_IWL<80> A_IWL<79> A_IWL<78> A_IWL<77> A_IWL<76> A_IWL<75> A_IWL<74> A_IWL<73> A_IWL<72> A_IWL<71> A_IWL<70> A_IWL<69> A_IWL<68> A_IWL<67> A_IWL<66> A_IWL<65> A_IWL<64> VDD_CORE VSS / RM_IHPSG13_512x8_c3_1P_COLUMN_pcell_0 +XCOL<0> A_BLC<1> A_BLC<0> A_BLC_TOP<1> A_BLC_TOP<0> A_BLT<1> A_BLT<0> A_BLT_TOP<1> A_BLT_TOP<0> A_WL<63> A_WL<62> A_WL<61> A_WL<60> A_WL<59> A_WL<58> A_WL<57> A_WL<56> A_WL<55> A_WL<54> A_WL<53> A_WL<52> A_WL<51> A_WL<50> A_WL<49> A_WL<48> A_WL<47> A_WL<46> A_WL<45> A_WL<44> A_WL<43> A_WL<42> A_WL<41> A_WL<40> A_WL<39> A_WL<38> A_WL<37> A_WL<36> A_WL<35> A_WL<34> A_WL<33> A_WL<32> A_WL<31> A_WL<30> A_WL<29> A_WL<28> A_WL<27> A_WL<26> A_WL<25> A_WL<24> A_WL<23> A_WL<22> A_WL<21> A_WL<20> A_WL<19> A_WL<18> A_WL<17> A_WL<16> A_WL<15> A_WL<14> A_WL<13> A_WL<12> A_WL<11> A_WL<10> A_WL<9> A_WL<8> A_WL<7> A_WL<6> A_WL<5> A_WL<4> A_WL<3> A_WL<2> A_WL<1> A_WL<0> A_IWL<63> A_IWL<62> A_IWL<61> A_IWL<60> A_IWL<59> A_IWL<58> A_IWL<57> A_IWL<56> A_IWL<55> A_IWL<54> A_IWL<53> A_IWL<52> A_IWL<51> A_IWL<50> A_IWL<49> A_IWL<48> A_IWL<47> A_IWL<46> A_IWL<45> A_IWL<44> A_IWL<43> A_IWL<42> A_IWL<41> A_IWL<40> A_IWL<39> A_IWL<38> A_IWL<37> A_IWL<36> A_IWL<35> A_IWL<34> A_IWL<33> A_IWL<32> A_IWL<31> A_IWL<30> A_IWL<29> A_IWL<28> A_IWL<27> A_IWL<26> A_IWL<25> A_IWL<24> A_IWL<23> A_IWL<22> A_IWL<21> A_IWL<20> A_IWL<19> A_IWL<18> A_IWL<17> A_IWL<16> A_IWL<15> A_IWL<14> A_IWL<13> A_IWL<12> A_IWL<11> A_IWL<10> A_IWL<9> A_IWL<8> A_IWL<7> A_IWL<6> A_IWL<5> A_IWL<4> A_IWL<3> A_IWL<2> A_IWL<1> A_IWL<0> VDD_CORE VSS / RM_IHPSG13_512x8_c3_1P_COLUMN_pcell_0 +.ENDS + + + + +.SUBCKT RM_IHPSG13_512x8_c3_1P_DLY_pcell_2 A Z VDD VSS + XIDL D<7> Z VDD VSS / RSC_IHPSG13_CDLYX1 + XIDM<7> D<6> D<7> VDD VSS / RSC_IHPSG13_CDLYX1_DUMMY + XIDM<6> D<5> D<6> VDD VSS / RSC_IHPSG13_CDLYX1_DUMMY + XIDM<5> D<4> D<5> VDD VSS / RSC_IHPSG13_CDLYX1_DUMMY + XIDM<4> D<3> D<4> VDD VSS / RSC_IHPSG13_CDLYX1_DUMMY + XIDM<3> D<2> D<3> VDD VSS / RSC_IHPSG13_CDLYX1_DUMMY + XIDM<2> D<1> D<2> VDD VSS / RSC_IHPSG13_CDLYX1_DUMMY + XIDM<1> A D<1> VDD VSS / RSC_IHPSG13_CDLYX1_DUMMY +.ENDS + + +.SUBCKT RM_IHPSG13_512x8_c3_1P_DLY_pcell_3 A Z VDD VSS + XIDM<8> D<7> Z VDD VSS / RSC_IHPSG13_CDLYX1_DUMMY + XIDM<7> D<6> D<7> VDD VSS / RSC_IHPSG13_CDLYX1_DUMMY + XIDM<6> D<5> D<6> VDD VSS / RSC_IHPSG13_CDLYX1_DUMMY + XIDM<5> D<4> D<5> VDD VSS / RSC_IHPSG13_CDLYX1_DUMMY + XIDM<4> D<3> D<4> VDD VSS / RSC_IHPSG13_CDLYX1_DUMMY + XIDM<3> D<2> D<3> VDD VSS / RSC_IHPSG13_CDLYX1_DUMMY + XIDM<2> D<1> D<2> VDD VSS / RSC_IHPSG13_CDLYX1_DUMMY + XIDM<1> A D<1> VDD VSS / RSC_IHPSG13_CDLYX1_DUMMY +.ENDS + + + +.SUBCKT RM_IHPSG13_1P_512x8_c3_bm_bist A_ADDR<8> A_ADDR<7> A_ADDR<6> A_ADDR<5> A_ADDR<4> A_ADDR<3> A_ADDR<2> A_ADDR<1> A_ADDR<0> A_BIST_ADDR<8> A_BIST_ADDR<7> A_BIST_ADDR<6> A_BIST_ADDR<5> A_BIST_ADDR<4> A_BIST_ADDR<3> A_BIST_ADDR<2> A_BIST_ADDR<1> A_BIST_ADDR<0> A_BIST_BM<7> A_BIST_BM<6> A_BIST_BM<5> A_BIST_BM<4> A_BIST_BM<3> A_BIST_BM<2> A_BIST_BM<1> A_BIST_BM<0> A_BIST_CLK A_BIST_DIN<7> A_BIST_DIN<6> A_BIST_DIN<5> A_BIST_DIN<4> A_BIST_DIN<3> A_BIST_DIN<2> A_BIST_DIN<1> A_BIST_DIN<0> A_BIST_EN A_BIST_MEN A_BIST_REN A_BIST_WEN A_BM<7> A_BM<6> A_BM<5> A_BM<4> A_BM<3> A_BM<2> A_BM<1> A_BM<0> A_CLK A_DIN<7> A_DIN<6> A_DIN<5> A_DIN<4> A_DIN<3> A_DIN<2> A_DIN<1> A_DIN<0> A_DLY A_DOUT<7> A_DOUT<6> A_DOUT<5> A_DOUT<4> A_DOUT<3> A_DOUT<2> A_DOUT<1> A_DOUT<0> A_MEN A_REN A_WEN VDD! VDDARRAY! VSS! + + +XRAM<1> a_blc_r<31> a_blc_r<30> a_blc_r<29> a_blc_r<28> a_blc_r<27> a_blc_r<26> a_blc_r<25> a_blc_r<24> a_blc_r<23> a_blc_r<22> a_blc_r<21> a_blc_r<20> a_blc_r<19> a_blc_r<18> a_blc_r<17> a_blc_r<16> a_blc_r<15> a_blc_r<14> a_blc_r<13> a_blc_r<12> a_blc_r<11> a_blc_r<10> a_blc_r<9> a_blc_r<8> a_blc_r<7> a_blc_r<6> a_blc_r<5> a_blc_r<4> a_blc_r<3> a_blc_r<2> a_blc_r<1> a_blc_r<0> a_blt_r<31> a_blt_r<30> a_blt_r<29> a_blt_r<28> a_blt_r<27> a_blt_r<26> a_blt_r<25> a_blt_r<24> a_blt_r<23> a_blt_r<22> a_blt_r<21> a_blt_r<20> a_blt_r<19> a_blt_r<18> a_blt_r<17> a_blt_r<16> a_blt_r<15> a_blt_r<14> a_blt_r<13> a_blt_r<12> a_blt_r<11> a_blt_r<10> a_blt_r<9> a_blt_r<8> a_blt_r<7> a_blt_r<6> a_blt_r<5> a_blt_r<4> a_blt_r<3> a_blt_r<2> a_blt_r<1> a_blt_r<0> a_wl_r<63> a_wl_r<62> a_wl_r<61> a_wl_r<60> a_wl_r<59> a_wl_r<58> a_wl_r<57> a_wl_r<56> a_wl_r<55> a_wl_r<54> a_wl_r<53> a_wl_r<52> a_wl_r<51> a_wl_r<50> a_wl_r<49> a_wl_r<48> a_wl_r<47> a_wl_r<46> a_wl_r<45> a_wl_r<44> a_wl_r<43> a_wl_r<42> a_wl_r<41> a_wl_r<40> a_wl_r<39> a_wl_r<38> a_wl_r<37> a_wl_r<36> a_wl_r<35> a_wl_r<34> a_wl_r<33> a_wl_r<32> a_wl_r<31> a_wl_r<30> a_wl_r<29> a_wl_r<28> a_wl_r<27> a_wl_r<26> a_wl_r<25> a_wl_r<24> a_wl_r<23> a_wl_r<22> a_wl_r<21> a_wl_r<20> a_wl_r<19> a_wl_r<18> a_wl_r<17> a_wl_r<16> a_wl_r<15> a_wl_r<14> a_wl_r<13> a_wl_r<12> a_wl_r<11> a_wl_r<10> a_wl_r<9> a_wl_r<8> a_wl_r<7> a_wl_r<6> a_wl_r<5> a_wl_r<4> a_wl_r<3> a_wl_r<2> a_wl_r<1> a_wl_r<0> VDDARRAY! VSS! / RM_IHPSG13_512x8_c3_1P_MATRIX_pcell_1 +XRAM<0> a_blc_l<31> a_blc_l<30> a_blc_l<29> a_blc_l<28> a_blc_l<27> a_blc_l<26> a_blc_l<25> a_blc_l<24> a_blc_l<23> a_blc_l<22> a_blc_l<21> a_blc_l<20> a_blc_l<19> a_blc_l<18> a_blc_l<17> a_blc_l<16> a_blc_l<15> a_blc_l<14> a_blc_l<13> a_blc_l<12> a_blc_l<11> a_blc_l<10> a_blc_l<9> a_blc_l<8> a_blc_l<7> a_blc_l<6> a_blc_l<5> a_blc_l<4> a_blc_l<3> a_blc_l<2> a_blc_l<1> a_blc_l<0> a_blt_l<31> a_blt_l<30> a_blt_l<29> a_blt_l<28> a_blt_l<27> a_blt_l<26> a_blt_l<25> a_blt_l<24> a_blt_l<23> a_blt_l<22> a_blt_l<21> a_blt_l<20> a_blt_l<19> a_blt_l<18> a_blt_l<17> a_blt_l<16> a_blt_l<15> a_blt_l<14> a_blt_l<13> a_blt_l<12> a_blt_l<11> a_blt_l<10> a_blt_l<9> a_blt_l<8> a_blt_l<7> a_blt_l<6> a_blt_l<5> a_blt_l<4> a_blt_l<3> a_blt_l<2> a_blt_l<1> a_blt_l<0> a_wl_l<63> a_wl_l<62> a_wl_l<61> a_wl_l<60> a_wl_l<59> a_wl_l<58> a_wl_l<57> a_wl_l<56> a_wl_l<55> a_wl_l<54> a_wl_l<53> a_wl_l<52> a_wl_l<51> a_wl_l<50> a_wl_l<49> a_wl_l<48> a_wl_l<47> a_wl_l<46> a_wl_l<45> a_wl_l<44> a_wl_l<43> a_wl_l<42> a_wl_l<41> a_wl_l<40> a_wl_l<39> a_wl_l<38> a_wl_l<37> a_wl_l<36> a_wl_l<35> a_wl_l<34> a_wl_l<33> a_wl_l<32> a_wl_l<31> a_wl_l<30> a_wl_l<29> a_wl_l<28> a_wl_l<27> a_wl_l<26> a_wl_l<25> a_wl_l<24> a_wl_l<23> a_wl_l<22> a_wl_l<21> a_wl_l<20> a_wl_l<19> a_wl_l<18> a_wl_l<17> a_wl_l<16> a_wl_l<15> a_wl_l<14> a_wl_l<13> a_wl_l<12> a_wl_l<11> a_wl_l<10> a_wl_l<9> a_wl_l<8> a_wl_l<7> a_wl_l<6> a_wl_l<5> a_wl_l<4> a_wl_l<3> a_wl_l<2> a_wl_l<1> a_wl_l<0> VDDARRAY! VSS! / RM_IHPSG13_512x8_c3_1P_MATRIX_pcell_1 + + +XA_COLDRV<1> a_addr_col<1> a_addr_col<0> a_addr_col_r<1> a_addr_col_r<0> a_addr_dec<7> a_addr_dec<6> a_addr_dec<5> a_addr_dec<4> a_addr_dec<3> a_addr_dec<2> a_addr_dec<1> a_addr_dec<0> a_addr_dec_r<7> a_addr_dec_r<6> a_addr_dec_r<5> a_addr_dec_r<4> a_addr_dec_r<3> a_addr_dec_r<2> a_addr_dec_r<1> a_addr_dec_r<0> a_dclk a_dclk_p_r<0> a_rclk a_rclk_p_r<0> a_wclk a_wclk_p_r<0> VDD! VSS! / RM_IHPSG13_512x8_c3_1P_COLDRV13X4 +XA_COLDRV<0> a_addr_col<1> a_addr_col<0> a_addr_col_l<1> a_addr_col_l<0> a_addr_dec<7> a_addr_dec<6> a_addr_dec<5> a_addr_dec<4> a_addr_dec<3> a_addr_dec<2> a_addr_dec<1> a_addr_dec<0> a_addr_dec_l<7> a_addr_dec_l<6> a_addr_dec_l<5> a_addr_dec_l<4> a_addr_dec_l<3> a_addr_dec_l<2> a_addr_dec_l<1> a_addr_dec_l<0> a_dclk a_dclk_p_l<0> a_rclk a_rclk_p_l<0> a_wclk a_wclk_p_l<0> VDD! VSS! / RM_IHPSG13_512x8_c3_1P_COLDRV13X4 + + +XA_WLDRV<7> a_wi<63> a_wi<62> a_wi<61> a_wi<60> a_wi<59> a_wi<58> a_wi<57> a_wi<56> a_wi<55> a_wi<54> a_wi<53> a_wi<52> a_wi<51> a_wi<50> a_wi<49> a_wi<48> a_wl_r<63> a_wl_r<62> a_wl_r<61> a_wl_r<60> a_wl_r<59> a_wl_r<58> a_wl_r<57> a_wl_r<56> a_wl_r<55> a_wl_r<54> a_wl_r<53> a_wl_r<52> a_wl_r<51> a_wl_r<50> a_wl_r<49> a_wl_r<48> VDD! VSS! / RM_IHPSG13_512x8_c3_1P_WLDRV16X4 +XA_WLDRV<6> a_wi<47> a_wi<46> a_wi<45> a_wi<44> a_wi<43> a_wi<42> a_wi<41> a_wi<40> a_wi<39> a_wi<38> a_wi<37> a_wi<36> a_wi<35> a_wi<34> a_wi<33> a_wi<32> a_wl_r<47> a_wl_r<46> a_wl_r<45> a_wl_r<44> a_wl_r<43> a_wl_r<42> a_wl_r<41> a_wl_r<40> a_wl_r<39> a_wl_r<38> a_wl_r<37> a_wl_r<36> a_wl_r<35> a_wl_r<34> a_wl_r<33> a_wl_r<32> VDD! VSS! / RM_IHPSG13_512x8_c3_1P_WLDRV16X4 +XA_WLDRV<5> a_wi<31> a_wi<30> a_wi<29> a_wi<28> a_wi<27> a_wi<26> a_wi<25> a_wi<24> a_wi<23> a_wi<22> a_wi<21> a_wi<20> a_wi<19> a_wi<18> a_wi<17> a_wi<16> a_wl_r<31> a_wl_r<30> a_wl_r<29> a_wl_r<28> a_wl_r<27> a_wl_r<26> a_wl_r<25> a_wl_r<24> a_wl_r<23> a_wl_r<22> a_wl_r<21> a_wl_r<20> a_wl_r<19> a_wl_r<18> a_wl_r<17> a_wl_r<16> VDD! VSS! / RM_IHPSG13_512x8_c3_1P_WLDRV16X4 +XA_WLDRV<4> a_wi<15> a_wi<14> a_wi<13> a_wi<12> a_wi<11> a_wi<10> a_wi<9> a_wi<8> a_wi<7> a_wi<6> a_wi<5> a_wi<4> a_wi<3> a_wi<2> a_wi<1> a_wi<0> a_wl_r<15> a_wl_r<14> a_wl_r<13> a_wl_r<12> a_wl_r<11> a_wl_r<10> a_wl_r<9> a_wl_r<8> a_wl_r<7> a_wl_r<6> a_wl_r<5> a_wl_r<4> a_wl_r<3> a_wl_r<2> a_wl_r<1> a_wl_r<0> VDD! VSS! / RM_IHPSG13_512x8_c3_1P_WLDRV16X4 +XA_WLDRV<3> a_wi<63> a_wi<62> a_wi<61> a_wi<60> a_wi<59> a_wi<58> a_wi<57> a_wi<56> a_wi<55> a_wi<54> a_wi<53> a_wi<52> a_wi<51> a_wi<50> a_wi<49> a_wi<48> a_wl_l<63> a_wl_l<62> a_wl_l<61> a_wl_l<60> a_wl_l<59> a_wl_l<58> a_wl_l<57> a_wl_l<56> a_wl_l<55> a_wl_l<54> a_wl_l<53> a_wl_l<52> a_wl_l<51> a_wl_l<50> a_wl_l<49> a_wl_l<48> VDD! VSS! / RM_IHPSG13_512x8_c3_1P_WLDRV16X4 +XA_WLDRV<2> a_wi<47> a_wi<46> a_wi<45> a_wi<44> a_wi<43> a_wi<42> a_wi<41> a_wi<40> a_wi<39> a_wi<38> a_wi<37> a_wi<36> a_wi<35> a_wi<34> a_wi<33> a_wi<32> a_wl_l<47> a_wl_l<46> a_wl_l<45> a_wl_l<44> a_wl_l<43> a_wl_l<42> a_wl_l<41> a_wl_l<40> a_wl_l<39> a_wl_l<38> a_wl_l<37> a_wl_l<36> a_wl_l<35> a_wl_l<34> a_wl_l<33> a_wl_l<32> VDD! VSS! / RM_IHPSG13_512x8_c3_1P_WLDRV16X4 +XA_WLDRV<1> a_wi<31> a_wi<30> a_wi<29> a_wi<28> a_wi<27> a_wi<26> a_wi<25> a_wi<24> a_wi<23> a_wi<22> a_wi<21> a_wi<20> a_wi<19> a_wi<18> a_wi<17> a_wi<16> a_wl_l<31> a_wl_l<30> a_wl_l<29> a_wl_l<28> a_wl_l<27> a_wl_l<26> a_wl_l<25> a_wl_l<24> a_wl_l<23> a_wl_l<22> a_wl_l<21> a_wl_l<20> a_wl_l<19> a_wl_l<18> a_wl_l<17> a_wl_l<16> VDD! VSS! / RM_IHPSG13_512x8_c3_1P_WLDRV16X4 +XA_WLDRV<0> a_wi<15> a_wi<14> a_wi<13> a_wi<12> a_wi<11> a_wi<10> a_wi<9> a_wi<8> a_wi<7> a_wi<6> a_wi<5> a_wi<4> a_wi<3> a_wi<2> a_wi<1> a_wi<0> a_wl_l<15> a_wl_l<14> a_wl_l<13> a_wl_l<12> a_wl_l<11> a_wl_l<10> a_wl_l<9> a_wl_l<8> a_wl_l<7> a_wl_l<6> a_wl_l<5> a_wl_l<4> a_wl_l<3> a_wl_l<2> a_wl_l<1> a_wl_l<0> VDD! VSS! / RM_IHPSG13_512x8_c3_1P_WLDRV16X4 + + +XA_CTRL a_aclk_n A_BIST_CLK A_BIST_MEN A_BIST_EN A_BIST_REN A_BIST_WEN a_tiel A_CLK A_MEN a_dclk a_eclk a_pulse_h a_pulse_l a_pulse a_rclk A_REN a_cs a_wclk A_WEN VDD! VSS! / RM_IHPSG13_512x8_c3_1P_CTRL + + +XA_ROWDEC a_addr_row<5> a_addr_row<4> a_addr_row<3> a_addr_row<2> a_addr_row<1> a_addr_row<0> a_cs a_eclk a_wi<63> a_wi<62> a_wi<61> a_wi<60> a_wi<59> a_wi<58> a_wi<57> a_wi<56> a_wi<55> a_wi<54> a_wi<53> a_wi<52> a_wi<51> a_wi<50> a_wi<49> a_wi<48> a_wi<47> a_wi<46> a_wi<45> a_wi<44> a_wi<43> a_wi<42> a_wi<41> a_wi<40> a_wi<39> a_wi<38> a_wi<37> a_wi<36> a_wi<35> a_wi<34> a_wi<33> a_wi<32> a_wi<31> a_wi<30> a_wi<29> a_wi<28> a_wi<27> a_wi<26> a_wi<25> a_wi<24> a_wi<23> a_wi<22> a_wi<21> a_wi<20> a_wi<19> a_wi<18> a_wi<17> a_wi<16> a_wi<15> a_wi<14> a_wi<13> a_wi<12> a_wi<11> a_wi<10> a_wi<9> a_wi<8> a_wi<7> a_wi<6> a_wi<5> a_wi<4> a_wi<3> a_wi<2> a_wi<1> a_wi<0> VDD! VSS! / RM_IHPSG13_512x8_c3_1P_ROWDEC6 +XA_ROWREG a_aclk_n A_ADDR<8> A_ADDR<7> A_ADDR<6> A_ADDR<5> A_ADDR<4> A_ADDR<3> a_addr_row<5> a_addr_row<4> a_addr_row<3> a_addr_row<2> a_addr_row<1> a_addr_row<0> A_BIST_ADDR<8> A_BIST_ADDR<7> A_BIST_ADDR<6> A_BIST_ADDR<5> A_BIST_ADDR<4> A_BIST_ADDR<3> A_BIST_EN VDD! VSS! / RM_IHPSG13_512x8_c3_1P_ROWREG6 +XA_COLDEC a_aclk_n A_ADDR<2> A_ADDR<1> A_ADDR<0> a_addr_col<1> a_addr_col<0> a_addr_dec<7> a_addr_dec<6> a_addr_dec<5> a_addr_dec<4> a_addr_dec<3> a_addr_dec<2> a_addr_dec<1> a_addr_dec<0> A_BIST_ADDR<2> A_BIST_ADDR<1> A_BIST_ADDR<0> A_BIST_EN VDD! VSS! / RM_IHPSG13_512x8_c3_1P_COLDEC3 + + +XA_DLYH a_pulse a_pulse_h VDD! VSS! / RM_IHPSG13_512x8_c3_1P_DLY_pcell_2 +XA_DLYL a_pulse_x a_pulse_l VDD! VSS! / RM_IHPSG13_512x8_c3_1P_DLY_pcell_3 +XA_DLYMUX a_pulse_h A_DLY a_pulse_x VDD! VSS! / RM_IHPSG13_512x8_c3_1P_DLY_MUX + +XCOLCTRL<7> a_addr_dec_r<7> a_addr_dec_r<6> a_addr_dec_r<5> a_addr_dec_r<4> a_addr_dec_r<3> a_addr_dec_r<2> a_addr_dec_r<1> a_addr_dec_r<0> A_BIST_BM<7> A_BIST_DIN<7> A_BIST_EN a_blc_r<31> a_blc_r<30> a_blc_r<29> a_blc_r<28> a_blc_r<27> a_blc_r<26> a_blc_r<25> a_blc_r<24> a_blt_r<31> a_blt_r<30> a_blt_r<29> a_blt_r<28> a_blt_r<27> a_blt_r<26> a_blt_r<25> a_blt_r<24> A_BM<7> a_dclk_n_r<3> a_dclk_n_r<4> a_dclk_p_r<3> a_dclk_p_r<4> A_DOUT<7> A_DIN<7> a_rclk_n_r<3> a_rclk_n_r<4> a_rclk_p_r<3> a_rclk_p_r<4> a_tieh<7> a_wclk_n_r<3> a_wclk_n_r<4> a_wclk_p_r<3> a_wclk_p_r<4> VDD! VSS! / RM_IHPSG13_512x8_c3_1P_COLCTRL3 +XCOLCTRL<6> a_addr_dec_r<7> a_addr_dec_r<6> a_addr_dec_r<5> a_addr_dec_r<4> a_addr_dec_r<3> a_addr_dec_r<2> a_addr_dec_r<1> a_addr_dec_r<0> A_BIST_BM<6> A_BIST_DIN<6> A_BIST_EN a_blc_r<23> a_blc_r<22> a_blc_r<21> a_blc_r<20> a_blc_r<19> a_blc_r<18> a_blc_r<17> a_blc_r<16> a_blt_r<23> a_blt_r<22> a_blt_r<21> a_blt_r<20> a_blt_r<19> a_blt_r<18> a_blt_r<17> a_blt_r<16> A_BM<6> a_dclk_n_r<2> a_dclk_n_r<3> a_dclk_p_r<2> a_dclk_p_r<3> A_DOUT<6> A_DIN<6> a_rclk_n_r<2> a_rclk_n_r<3> a_rclk_p_r<2> a_rclk_p_r<3> a_tieh<6> a_wclk_n_r<2> a_wclk_n_r<3> a_wclk_p_r<2> a_wclk_p_r<3> VDD! VSS! / RM_IHPSG13_512x8_c3_1P_COLCTRL3 +XCOLCTRL<5> a_addr_dec_r<7> a_addr_dec_r<6> a_addr_dec_r<5> a_addr_dec_r<4> a_addr_dec_r<3> a_addr_dec_r<2> a_addr_dec_r<1> a_addr_dec_r<0> A_BIST_BM<5> A_BIST_DIN<5> A_BIST_EN a_blc_r<15> a_blc_r<14> a_blc_r<13> a_blc_r<12> a_blc_r<11> a_blc_r<10> a_blc_r<9> a_blc_r<8> a_blt_r<15> a_blt_r<14> a_blt_r<13> a_blt_r<12> a_blt_r<11> a_blt_r<10> a_blt_r<9> a_blt_r<8> A_BM<5> a_dclk_n_r<1> a_dclk_n_r<2> a_dclk_p_r<1> a_dclk_p_r<2> A_DOUT<5> A_DIN<5> a_rclk_n_r<1> a_rclk_n_r<2> a_rclk_p_r<1> a_rclk_p_r<2> a_tieh<5> a_wclk_n_r<1> a_wclk_n_r<2> a_wclk_p_r<1> a_wclk_p_r<2> VDD! VSS! / RM_IHPSG13_512x8_c3_1P_COLCTRL3 +XCOLCTRL<4> a_addr_dec_r<7> a_addr_dec_r<6> a_addr_dec_r<5> a_addr_dec_r<4> a_addr_dec_r<3> a_addr_dec_r<2> a_addr_dec_r<1> a_addr_dec_r<0> A_BIST_BM<4> A_BIST_DIN<4> A_BIST_EN a_blc_r<7> a_blc_r<6> a_blc_r<5> a_blc_r<4> a_blc_r<3> a_blc_r<2> a_blc_r<1> a_blc_r<0> a_blt_r<7> a_blt_r<6> a_blt_r<5> a_blt_r<4> a_blt_r<3> a_blt_r<2> a_blt_r<1> a_blt_r<0> A_BM<4> a_dclk_n_r<0> a_dclk_n_r<1> a_dclk_p_r<0> a_dclk_p_r<1> A_DOUT<4> A_DIN<4> a_rclk_n_r<0> a_rclk_n_r<1> a_rclk_p_r<0> a_rclk_p_r<1> a_tieh<4> a_wclk_n_r<0> a_wclk_n_r<1> a_wclk_p_r<0> a_wclk_p_r<1> VDD! VSS! / RM_IHPSG13_512x8_c3_1P_COLCTRL3 +XCOLCTRL<3> a_addr_dec_l<7> a_addr_dec_l<6> a_addr_dec_l<5> a_addr_dec_l<4> a_addr_dec_l<3> a_addr_dec_l<2> a_addr_dec_l<1> a_addr_dec_l<0> A_BIST_BM<0> A_BIST_DIN<0> A_BIST_EN a_blc_l<31> a_blc_l<30> a_blc_l<29> a_blc_l<28> a_blc_l<27> a_blc_l<26> a_blc_l<25> a_blc_l<24> a_blt_l<31> a_blt_l<30> a_blt_l<29> a_blt_l<28> a_blt_l<27> a_blt_l<26> a_blt_l<25> a_blt_l<24> A_BM<0> a_dclk_n_l<3> a_dclk_n_l<4> a_dclk_p_l<3> a_dclk_p_l<4> A_DOUT<0> A_DIN<0> a_rclk_n_l<3> a_rclk_n_l<4> a_rclk_p_l<3> a_rclk_p_l<4> a_tieh<0> a_wclk_n_l<3> a_wclk_n_l<4> a_wclk_p_l<3> a_wclk_p_l<4> VDD! VSS! / RM_IHPSG13_512x8_c3_1P_COLCTRL3 +XCOLCTRL<2> a_addr_dec_l<7> a_addr_dec_l<6> a_addr_dec_l<5> a_addr_dec_l<4> a_addr_dec_l<3> a_addr_dec_l<2> a_addr_dec_l<1> a_addr_dec_l<0> A_BIST_BM<1> A_BIST_DIN<1> A_BIST_EN a_blc_l<23> a_blc_l<22> a_blc_l<21> a_blc_l<20> a_blc_l<19> a_blc_l<18> a_blc_l<17> a_blc_l<16> a_blt_l<23> a_blt_l<22> a_blt_l<21> a_blt_l<20> a_blt_l<19> a_blt_l<18> a_blt_l<17> a_blt_l<16> A_BM<1> a_dclk_n_l<2> a_dclk_n_l<3> a_dclk_p_l<2> a_dclk_p_l<3> A_DOUT<1> A_DIN<1> a_rclk_n_l<2> a_rclk_n_l<3> a_rclk_p_l<2> a_rclk_p_l<3> a_tieh<1> a_wclk_n_l<2> a_wclk_n_l<3> a_wclk_p_l<2> a_wclk_p_l<3> VDD! VSS! / RM_IHPSG13_512x8_c3_1P_COLCTRL3 +XCOLCTRL<1> a_addr_dec_l<7> a_addr_dec_l<6> a_addr_dec_l<5> a_addr_dec_l<4> a_addr_dec_l<3> a_addr_dec_l<2> a_addr_dec_l<1> a_addr_dec_l<0> A_BIST_BM<2> A_BIST_DIN<2> A_BIST_EN a_blc_l<15> a_blc_l<14> a_blc_l<13> a_blc_l<12> a_blc_l<11> a_blc_l<10> a_blc_l<9> a_blc_l<8> a_blt_l<15> a_blt_l<14> a_blt_l<13> a_blt_l<12> a_blt_l<11> a_blt_l<10> a_blt_l<9> a_blt_l<8> A_BM<2> a_dclk_n_l<1> a_dclk_n_l<2> a_dclk_p_l<1> a_dclk_p_l<2> A_DOUT<2> A_DIN<2> a_rclk_n_l<1> a_rclk_n_l<2> a_rclk_p_l<1> a_rclk_p_l<2> a_tieh<2> a_wclk_n_l<1> a_wclk_n_l<2> a_wclk_p_l<1> a_wclk_p_l<2> VDD! VSS! / RM_IHPSG13_512x8_c3_1P_COLCTRL3 +XCOLCTRL<0> a_addr_dec_l<7> a_addr_dec_l<6> a_addr_dec_l<5> a_addr_dec_l<4> a_addr_dec_l<3> a_addr_dec_l<2> a_addr_dec_l<1> a_addr_dec_l<0> A_BIST_BM<3> A_BIST_DIN<3> A_BIST_EN a_blc_l<7> a_blc_l<6> a_blc_l<5> a_blc_l<4> a_blc_l<3> a_blc_l<2> a_blc_l<1> a_blc_l<0> a_blt_l<7> a_blt_l<6> a_blt_l<5> a_blt_l<4> a_blt_l<3> a_blt_l<2> a_blt_l<1> a_blt_l<0> A_BM<3> a_dclk_n_l<0> a_dclk_n_l<1> a_dclk_p_l<0> a_dclk_p_l<1> A_DOUT<3> A_DIN<3> a_rclk_n_l<0> a_rclk_n_l<1> a_rclk_p_l<0> a_rclk_p_l<1> a_tieh<3> a_wclk_n_l<0> a_wclk_n_l<1> a_wclk_p_l<0> a_wclk_p_l<1> VDD! VSS! / RM_IHPSG13_512x8_c3_1P_COLCTRL3 + + +XDRVFILL4<1> VDD! VSS! / RM_IHPSG13_512x8_c3_1P_COLDRV13_FILL4 +XDRVFILL4<2> VDD! VSS! / RM_IHPSG13_512x8_c3_1P_COLDRV13_FILL4 +.ENDS diff --git a/flow/platforms/ihp-sg13g2/cdl/RM_IHPSG13_1P_8192x32_c4.cdl b/flow/platforms/ihp-sg13g2/cdl/RM_IHPSG13_1P_8192x32_c4.cdl new file mode 100644 index 0000000000..ad5da56260 --- /dev/null +++ b/flow/platforms/ihp-sg13g2/cdl/RM_IHPSG13_1P_8192x32_c4.cdl @@ -0,0 +1,6597 @@ +* ------------------------------------------------------ +* +* Copyright 2023 IHP PDK Authors +* +* Licensed under the Apache License, Version 2.0 (the "License"); +* you may not use this file except in compliance with the License. +* You may obtain a copy of the License at +* +* https://www.apache.org/licenses/LICENSE-2.0 +* +* Unless required by applicable law or agreed to in writing, software +* distributed under the License is distributed on an "AS IS" BASIS, +* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +* See the License for the specific language governing permissions and +* limitations under the License. +* +* Generated on Mon Apr 7 14:15:46 2025 +* +* ------------------------------------------------------ + +.SUBCKT RM_IHPSG13_8192x32_c4_1P_BITKIT_CORNER NW PW VDD VSS +.ENDS +.SUBCKT RM_IHPSG13_8192x32_c4_1P_BITKIT_16x2_CORNER VDD_CORE VSS +XI16 VDD_CORE VSS VDD_CORE VSS / ++ RM_IHPSG13_8192x32_c4_1P_BITKIT_CORNER +.ENDS +.SUBCKT RM_IHPSG13_8192x32_c4_1P_BITKIT_EDGE_LR LWL NW PW VDD VSS +MN1 VSS LWL VSS VSS sg13_lv_nmos m=1 w=300.0n l=130.00n ng=1 nrd=0 nrs=0 +MN0 VSS net9 VSS VSS sg13_lv_nmos m=1 w=300.0n l=130.00n ng=1 nrd=0 nrs=0 +.ENDS +.SUBCKT RM_IHPSG13_8192x32_c4_1P_BITKIT_16x2_EDGE_LR A_WL<15> A_WL<14> A_WL<13> A_WL<12> ++ A_WL<11> A_WL<10> A_WL<9> A_WL<8> A_WL<7> A_WL<6> A_WL<5> A_WL<4> A_WL<3> ++ A_WL<2> A_WL<1> A_WL<0> VDD_CORE VSS +XI0<15> A_WL<15> VDD_CORE VSS VDD_CORE VSS / ++ RM_IHPSG13_8192x32_c4_1P_BITKIT_EDGE_LR +XI0<14> A_WL<14> VDD_CORE VSS VDD_CORE VSS / ++ RM_IHPSG13_8192x32_c4_1P_BITKIT_EDGE_LR +XI0<13> A_WL<13> VDD_CORE VSS VDD_CORE VSS / ++ RM_IHPSG13_8192x32_c4_1P_BITKIT_EDGE_LR +XI0<12> A_WL<12> VDD_CORE VSS VDD_CORE VSS / ++ RM_IHPSG13_8192x32_c4_1P_BITKIT_EDGE_LR +XI0<11> A_WL<11> VDD_CORE VSS VDD_CORE VSS / ++ RM_IHPSG13_8192x32_c4_1P_BITKIT_EDGE_LR +XI0<10> A_WL<10> VDD_CORE VSS VDD_CORE VSS / ++ RM_IHPSG13_8192x32_c4_1P_BITKIT_EDGE_LR +XI0<9> A_WL<9> VDD_CORE VSS VDD_CORE VSS / ++ RM_IHPSG13_8192x32_c4_1P_BITKIT_EDGE_LR +XI0<8> A_WL<8> VDD_CORE VSS VDD_CORE VSS / ++ RM_IHPSG13_8192x32_c4_1P_BITKIT_EDGE_LR +XI0<7> A_WL<7> VDD_CORE VSS VDD_CORE VSS / ++ RM_IHPSG13_8192x32_c4_1P_BITKIT_EDGE_LR +XI0<6> A_WL<6> VDD_CORE VSS VDD_CORE VSS / ++ RM_IHPSG13_8192x32_c4_1P_BITKIT_EDGE_LR +XI0<5> A_WL<5> VDD_CORE VSS VDD_CORE VSS / ++ RM_IHPSG13_8192x32_c4_1P_BITKIT_EDGE_LR +XI0<4> A_WL<4> VDD_CORE VSS VDD_CORE VSS / ++ RM_IHPSG13_8192x32_c4_1P_BITKIT_EDGE_LR +XI0<3> A_WL<3> VDD_CORE VSS VDD_CORE VSS / ++ RM_IHPSG13_8192x32_c4_1P_BITKIT_EDGE_LR +XI0<2> A_WL<2> VDD_CORE VSS VDD_CORE VSS / ++ RM_IHPSG13_8192x32_c4_1P_BITKIT_EDGE_LR +XI0<1> A_WL<1> VDD_CORE VSS VDD_CORE VSS / ++ RM_IHPSG13_8192x32_c4_1P_BITKIT_EDGE_LR +XI0<0> A_WL<0> VDD_CORE VSS VDD_CORE VSS / ++ RM_IHPSG13_8192x32_c4_1P_BITKIT_EDGE_LR +.ENDS +.SUBCKT RM_IHPSG13_8192x32_c4_1P_BITKIT_CELL BLC_BOT BLC_TOP BLT_BOT BLT_TOP LWL NW PW ++ RWL VDD VSS +MN0 NC NT VSS PW sg13_lv_nmos m=1 w=300.0n l=130.00n ng=1 nrd=0 nrs=0 +MN1 NT NC VSS PW sg13_lv_nmos m=1 w=300.0n l=130.00n ng=1 nrd=0 nrs=0 +MN3 NC RWL BLC_TOP PW sg13_lv_nmos m=1 w=300.0n l=130.00n ng=1 nrd=0 nrs=0 +MN2 BLT_BOT LWL NT PW sg13_lv_nmos m=1 w=300.0n l=130.00n ng=1 nrd=0 nrs=0 +MP1 NT NC VDD NW sg13_lv_pmos m=1 w=150.00n l=130.00n ng=1 nrd=0 nrs=0 +MP0 NC NT VDD NW sg13_lv_pmos m=1 w=150.00n l=130.00n ng=1 nrd=0 nrs=0 +R1 BLC_BOT BLC_TOP lvsres w=2.6e-07 l=6e-07 +R0 BLT_BOT BLT_TOP lvsres w=2.6e-07 l=6e-07 +R2 RWL LWL lvsres w=2.6e-07 l=6e-07 +.ENDS +.SUBCKT RM_IHPSG13_8192x32_c4_1P_BITKIT_16x2_SRAM A_BLC_BOT<1> A_BLC_BOT<0> A_BLC_TOP<1> ++ A_BLC_TOP<0> A_BLT_BOT<1> A_BLT_BOT<0> A_BLT_TOP<1> A_BLT_TOP<0> A_LWL<15> ++ A_LWL<14> A_LWL<13> A_LWL<12> A_LWL<11> A_LWL<10> A_LWL<9> A_LWL<8> A_LWL<7> ++ A_LWL<6> A_LWL<5> A_LWL<4> A_LWL<3> A_LWL<2> A_LWL<1> A_LWL<0> A_RWL<15> ++ A_RWL<14> A_RWL<13> A_RWL<12> A_RWL<11> A_RWL<10> A_RWL<9> A_RWL<8> A_RWL<7> ++ A_RWL<6> A_RWL<5> A_RWL<4> A_RWL<3> A_RWL<2> A_RWL<1> A_RWL<0> VDD_CORE ++ VSS +XCELL<31> A_BLC_TOP<1> A_RBLC<15> A_BLT_TOP<1> A_RBLT<15> A_RWL<15> ++ VDD_CORE VSS A_XWL<15> VDD_CORE VSS / ++ RM_IHPSG13_8192x32_c4_1P_BITKIT_CELL +XCELL<30> A_RBLC<14> A_RBLC<15> A_RBLT<14> A_RBLT<15> A_RWL<14> VDD_CORE ++ VSS A_XWL<14> VDD_CORE VSS / RM_IHPSG13_8192x32_c4_1P_BITKIT_CELL +XCELL<29> A_RBLC<14> A_RBLC<13> A_RBLT<14> A_RBLT<13> A_RWL<13> VDD_CORE ++ VSS A_XWL<13> VDD_CORE VSS / RM_IHPSG13_8192x32_c4_1P_BITKIT_CELL +XCELL<28> A_RBLC<12> A_RBLC<13> A_RBLT<12> A_RBLT<13> A_RWL<12> VDD_CORE ++ VSS A_XWL<12> VDD_CORE VSS / RM_IHPSG13_8192x32_c4_1P_BITKIT_CELL +XCELL<27> A_RBLC<12> A_RBLC<11> A_RBLT<12> A_RBLT<11> A_RWL<11> VDD_CORE ++ VSS A_XWL<11> VDD_CORE VSS / RM_IHPSG13_8192x32_c4_1P_BITKIT_CELL +XCELL<26> A_RBLC<10> A_RBLC<11> A_RBLT<10> A_RBLT<11> A_RWL<10> VDD_CORE ++ VSS A_XWL<10> VDD_CORE VSS / RM_IHPSG13_8192x32_c4_1P_BITKIT_CELL +XCELL<25> A_RBLC<10> A_RBLC<9> A_RBLT<10> A_RBLT<9> A_RWL<9> VDD_CORE ++ VSS A_XWL<9> VDD_CORE VSS / RM_IHPSG13_8192x32_c4_1P_BITKIT_CELL +XCELL<24> A_RBLC<8> A_RBLC<9> A_RBLT<8> A_RBLT<9> A_RWL<8> VDD_CORE ++ VSS A_XWL<8> VDD_CORE VSS / RM_IHPSG13_8192x32_c4_1P_BITKIT_CELL +XCELL<23> A_RBLC<8> A_RBLC<7> A_RBLT<8> A_RBLT<7> A_RWL<7> VDD_CORE ++ VSS A_XWL<7> VDD_CORE VSS / RM_IHPSG13_8192x32_c4_1P_BITKIT_CELL +XCELL<22> A_RBLC<6> A_RBLC<7> A_RBLT<6> A_RBLT<7> A_RWL<6> VDD_CORE ++ VSS A_XWL<6> VDD_CORE VSS / RM_IHPSG13_8192x32_c4_1P_BITKIT_CELL +XCELL<21> A_RBLC<6> A_RBLC<5> A_RBLT<6> A_RBLT<5> A_RWL<5> VDD_CORE ++ VSS A_XWL<5> VDD_CORE VSS / RM_IHPSG13_8192x32_c4_1P_BITKIT_CELL +XCELL<20> A_RBLC<4> A_RBLC<5> A_RBLT<4> A_RBLT<5> A_RWL<4> VDD_CORE ++ VSS A_XWL<4> VDD_CORE VSS / RM_IHPSG13_8192x32_c4_1P_BITKIT_CELL +XCELL<19> A_RBLC<4> A_RBLC<3> A_RBLT<4> A_RBLT<3> A_RWL<3> VDD_CORE ++ VSS A_XWL<3> VDD_CORE VSS / RM_IHPSG13_8192x32_c4_1P_BITKIT_CELL +XCELL<18> A_RBLC<2> A_RBLC<3> A_RBLT<2> A_RBLT<3> A_RWL<2> VDD_CORE ++ VSS A_XWL<2> VDD_CORE VSS / RM_IHPSG13_8192x32_c4_1P_BITKIT_CELL +XCELL<17> A_RBLC<2> A_RBLC<1> A_RBLT<2> A_RBLT<1> A_RWL<1> VDD_CORE ++ VSS A_XWL<1> VDD_CORE VSS / RM_IHPSG13_8192x32_c4_1P_BITKIT_CELL +XCELL<16> A_BLC_BOT<1> A_RBLC<1> A_BLT_BOT<1> A_RBLT<1> A_RWL<0> VDD_CORE ++ VSS A_XWL<0> VDD_CORE VSS / RM_IHPSG13_8192x32_c4_1P_BITKIT_CELL +XCELL<15> A_BLC_TOP<0> A_LBLC<15> A_BLT_TOP<0> A_LBLT<15> A_LWL<15> ++ VDD_CORE VSS A_XWL<15> VDD_CORE VSS / ++ RM_IHPSG13_8192x32_c4_1P_BITKIT_CELL +XCELL<14> A_LBLC<14> A_LBLC<15> A_LBLT<14> A_LBLT<15> A_LWL<14> VDD_CORE ++ VSS A_XWL<14> VDD_CORE VSS / RM_IHPSG13_8192x32_c4_1P_BITKIT_CELL +XCELL<13> A_LBLC<14> A_LBLC<13> A_LBLT<14> A_LBLT<13> A_LWL<13> VDD_CORE ++ VSS A_XWL<13> VDD_CORE VSS / RM_IHPSG13_8192x32_c4_1P_BITKIT_CELL +XCELL<12> A_LBLC<12> A_LBLC<13> A_LBLT<12> A_LBLT<13> A_LWL<12> VDD_CORE ++ VSS A_XWL<12> VDD_CORE VSS / RM_IHPSG13_8192x32_c4_1P_BITKIT_CELL +XCELL<11> A_LBLC<12> A_LBLC<11> A_LBLT<12> A_LBLT<11> A_LWL<11> VDD_CORE ++ VSS A_XWL<11> VDD_CORE VSS / RM_IHPSG13_8192x32_c4_1P_BITKIT_CELL +XCELL<10> A_LBLC<10> A_LBLC<11> A_LBLT<10> A_LBLT<11> A_LWL<10> VDD_CORE ++ VSS A_XWL<10> VDD_CORE VSS / RM_IHPSG13_8192x32_c4_1P_BITKIT_CELL +XCELL<9> A_LBLC<10> A_LBLC<9> A_LBLT<10> A_LBLT<9> A_LWL<9> VDD_CORE ++ VSS A_XWL<9> VDD_CORE VSS / RM_IHPSG13_8192x32_c4_1P_BITKIT_CELL +XCELL<8> A_LBLC<8> A_LBLC<9> A_LBLT<8> A_LBLT<9> A_LWL<8> VDD_CORE ++ VSS A_XWL<8> VDD_CORE VSS / RM_IHPSG13_8192x32_c4_1P_BITKIT_CELL +XCELL<7> A_LBLC<8> A_LBLC<7> A_LBLT<8> A_LBLT<7> A_LWL<7> VDD_CORE ++ VSS A_XWL<7> VDD_CORE VSS / RM_IHPSG13_8192x32_c4_1P_BITKIT_CELL +XCELL<6> A_LBLC<6> A_LBLC<7> A_LBLT<6> A_LBLT<7> A_LWL<6> VDD_CORE ++ VSS A_XWL<6> VDD_CORE VSS / RM_IHPSG13_8192x32_c4_1P_BITKIT_CELL +XCELL<5> A_LBLC<6> A_LBLC<5> A_LBLT<6> A_LBLT<5> A_LWL<5> VDD_CORE ++ VSS A_XWL<5> VDD_CORE VSS / RM_IHPSG13_8192x32_c4_1P_BITKIT_CELL +XCELL<4> A_LBLC<4> A_LBLC<5> A_LBLT<4> A_LBLT<5> A_LWL<4> VDD_CORE ++ VSS A_XWL<4> VDD_CORE VSS / RM_IHPSG13_8192x32_c4_1P_BITKIT_CELL +XCELL<3> A_LBLC<4> A_LBLC<3> A_LBLT<4> A_LBLT<3> A_LWL<3> VDD_CORE ++ VSS A_XWL<3> VDD_CORE VSS / RM_IHPSG13_8192x32_c4_1P_BITKIT_CELL +XCELL<2> A_LBLC<2> A_LBLC<3> A_LBLT<2> A_LBLT<3> A_LWL<2> VDD_CORE ++ VSS A_XWL<2> VDD_CORE VSS / RM_IHPSG13_8192x32_c4_1P_BITKIT_CELL +XCELL<1> A_LBLC<2> A_LBLC<1> A_LBLT<2> A_LBLT<1> A_LWL<1> VDD_CORE ++ VSS A_XWL<1> VDD_CORE VSS / RM_IHPSG13_8192x32_c4_1P_BITKIT_CELL +XCELL<0> A_BLC_BOT<0> A_LBLC<1> A_BLT_BOT<0> A_LBLT<1> A_LWL<0> VDD_CORE ++ VSS A_XWL<0> VDD_CORE VSS / RM_IHPSG13_8192x32_c4_1P_BITKIT_CELL +.ENDS +.SUBCKT RM_IHPSG13_8192x32_c4_1P_BITKIT_EDGE_TB BLC BLT NW PW VDD VSS +.ENDS +.SUBCKT RM_IHPSG13_8192x32_c4_1P_BITKIT_16x2_EDGE_TB A_BLC<1> A_BLC<0> A_BLT<1> A_BLT<0> ++ VDD_CORE VSS +XEDGE<1> A_BLC<1> A_BLT<1> VDD_CORE VSS VDD_CORE VSS ++ / RM_IHPSG13_8192x32_c4_1P_BITKIT_EDGE_TB +XEDGE<0> A_BLC<0> A_BLT<0> VDD_CORE VSS VDD_CORE VSS ++ / RM_IHPSG13_8192x32_c4_1P_BITKIT_EDGE_TB +.ENDS + +.SUBCKT RSC_IHPSG13_CBUFX4 A Z VDD VSS +MN0 net9 A VSS VSS sg13_lv_nmos m=1 w=705.000n l=130.00n ng=1 nrd=0 ++ nrs=0 +MN1 Z net9 VSS VSS sg13_lv_nmos m=1 w=1.41u l=130.00n ng=2 nrd=0 nrs=0 +MP0 net9 A VDD VDD sg13_lv_pmos m=1 w=1.62u l=130.00n ng=1 nrd=0 nrs=0 +MP1 Z net9 VDD VDD sg13_lv_pmos m=1 w=3.24u l=130.00n ng=2 nrd=0 nrs=0 +.ENDS +.SUBCKT RM_IHPSG13_8192x32_c4_1P_COLDRV13X4 ADDR_COL_I<1> ADDR_COL_I<0> ADDR_COL_O<1> ++ ADDR_COL_O<0> ADDR_DEC_I<7> ADDR_DEC_I<6> ADDR_DEC_I<5> ADDR_DEC_I<4> ++ ADDR_DEC_I<3> ADDR_DEC_I<2> ADDR_DEC_I<1> ADDR_DEC_I<0> ADDR_DEC_O<7> ++ ADDR_DEC_O<6> ADDR_DEC_O<5> ADDR_DEC_O<4> ADDR_DEC_O<3> ADDR_DEC_O<2> ++ ADDR_DEC_O<1> ADDR_DEC_O<0> DCLK_I DCLK_O RCLK_I RCLK_O WCLK_I WCLK_O ++ VDD VSS +XADDR_COL_DRV<1> ADDR_COL_I<1> ADDR_COL_O<1> VDD VSS / ++ RSC_IHPSG13_CBUFX4 +XADDR_COL_DRV<0> ADDR_COL_I<0> ADDR_COL_O<0> VDD VSS / ++ RSC_IHPSG13_CBUFX4 +XADDR_DEC_DRV<7> ADDR_DEC_I<7> ADDR_DEC_O<7> VDD VSS / ++ RSC_IHPSG13_CBUFX4 +XADDR_DEC_DRV<6> ADDR_DEC_I<6> ADDR_DEC_O<6> VDD VSS / ++ RSC_IHPSG13_CBUFX4 +XADDR_DEC_DRV<5> ADDR_DEC_I<5> ADDR_DEC_O<5> VDD VSS / ++ RSC_IHPSG13_CBUFX4 +XADDR_DEC_DRV<4> ADDR_DEC_I<4> ADDR_DEC_O<4> VDD VSS / ++ RSC_IHPSG13_CBUFX4 +XADDR_DEC_DRV<3> ADDR_DEC_I<3> ADDR_DEC_O<3> VDD VSS / ++ RSC_IHPSG13_CBUFX4 +XADDR_DEC_DRV<2> ADDR_DEC_I<2> ADDR_DEC_O<2> VDD VSS / ++ RSC_IHPSG13_CBUFX4 +XADDR_DEC_DRV<1> ADDR_DEC_I<1> ADDR_DEC_O<1> VDD VSS / ++ RSC_IHPSG13_CBUFX4 +XADDR_DEC_DRV<0> ADDR_DEC_I<0> ADDR_DEC_O<0> VDD VSS / ++ RSC_IHPSG13_CBUFX4 +XDCLK_DRV DCLK_I DCLK_O VDD VSS / RSC_IHPSG13_CBUFX4 +XRCLK_DRV RCLK_I RCLK_O VDD VSS / RSC_IHPSG13_CBUFX4 +XWCLK_DRV WCLK_I WCLK_O VDD VSS / RSC_IHPSG13_CBUFX4 +.ENDS +.SUBCKT RSC_IHPSG13_WLDRVX4 A Z VDD VSS +MN1 Z net6 VSS VSS sg13_lv_nmos m=1 w=705.000n l=130.00n ng=1 nrd=0 ++ nrs=0 +MN0 net6 A VSS VSS sg13_lv_nmos m=1 w=900.0n l=130.00n ng=1 nrd=0 nrs=0 +MP1 Z net6 VDD VDD sg13_lv_pmos m=1 w=3.24u l=130.00n ng=2 nrd=0 nrs=0 +MP0 net6 A VDD VDD sg13_lv_pmos m=1 w=900.0n l=130.00n ng=1 nrd=0 nrs=0 +.ENDS +.SUBCKT RM_IHPSG13_8192x32_c4_1P_WLDRV16X4 A<15> A<14> A<13> A<12> A<11> A<10> A<9> A<8> ++ A<7> A<6> A<5> A<4> A<3> A<2> A<1> A<0> Z<15> Z<14> Z<13> Z<12> Z<11> Z<10> ++ Z<9> Z<8> Z<7> Z<6> Z<5> Z<4> Z<3> Z<2> Z<1> Z<0> VDD VSS +XBUF<15> A<15> Z<15> VDD VSS / RSC_IHPSG13_WLDRVX4 +XBUF<14> A<14> Z<14> VDD VSS / RSC_IHPSG13_WLDRVX4 +XBUF<13> A<13> Z<13> VDD VSS / RSC_IHPSG13_WLDRVX4 +XBUF<12> A<12> Z<12> VDD VSS / RSC_IHPSG13_WLDRVX4 +XBUF<11> A<11> Z<11> VDD VSS / RSC_IHPSG13_WLDRVX4 +XBUF<10> A<10> Z<10> VDD VSS / RSC_IHPSG13_WLDRVX4 +XBUF<9> A<9> Z<9> VDD VSS / RSC_IHPSG13_WLDRVX4 +XBUF<8> A<8> Z<8> VDD VSS / RSC_IHPSG13_WLDRVX4 +XBUF<7> A<7> Z<7> VDD VSS / RSC_IHPSG13_WLDRVX4 +XBUF<6> A<6> Z<6> VDD VSS / RSC_IHPSG13_WLDRVX4 +XBUF<5> A<5> Z<5> VDD VSS / RSC_IHPSG13_WLDRVX4 +XBUF<4> A<4> Z<4> VDD VSS / RSC_IHPSG13_WLDRVX4 +XBUF<3> A<3> Z<3> VDD VSS / RSC_IHPSG13_WLDRVX4 +XBUF<2> A<2> Z<2> VDD VSS / RSC_IHPSG13_WLDRVX4 +XBUF<1> A<1> Z<1> VDD VSS / RSC_IHPSG13_WLDRVX4 +XBUF<0> A<0> Z<0> VDD VSS / RSC_IHPSG13_WLDRVX4 +.ENDS +.SUBCKT RSC_IHPSG13_FILLCAP8 VDD VSS +MN0 vss_r vdd_r VSS VSS sg13_lv_nmos m=1 w=4.98u l=130.00n ng=6 nrd=0 ++ nrs=0 +MP0 vdd_r vss_r VDD VDD sg13_lv_pmos m=1 w=6.48u l=385.000n ng=4 nrd=0 ++ nrs=0 +.ENDS +.SUBCKT RSC_IHPSG13_LHPQX2 CP D Q VDD VSS +MN3 QIN CPN net14 VSS sg13_lv_nmos m=1 w=480.00n l=130.00n ng=1 nrd=0 nrs=0 +MN2 net14 net10 VSS VSS sg13_lv_nmos m=1 w=480.00n l=130.00n ng=1 ++ nrd=0 nrs=0 +MN5 net21 D VSS VSS sg13_lv_nmos m=1 w=870.00n l=130.00n ng=1 nrd=0 ++ nrs=0 +MN6 QIN CP net21 VSS sg13_lv_nmos m=1 w=870.00n l=130.00n ng=1 nrd=0 nrs=0 +MN1 net10 QIN VSS VSS sg13_lv_nmos m=1 w=480.00n l=130.00n ng=1 nrd=0 ++ nrs=0 +MN0 CPN CP VSS VSS sg13_lv_nmos m=1 w=480.00n l=130.00n ng=1 nrd=0 ++ nrs=0 +MN4 Q QIN VSS VSS sg13_lv_nmos m=1 w=980.00n l=130.00n ng=1 nrd=0 nrs=0 +MP2 QIN CP net16 VDD sg13_lv_pmos m=1 w=480.00n l=130.00n ng=1 nrd=0 nrs=0 +MP0 CPN CP VDD VDD sg13_lv_pmos m=1 w=480.00n l=130.00n ng=1 nrd=0 ++ nrs=0 +MP4 Q QIN VDD VDD sg13_lv_pmos m=1 w=1.62u l=130.00n ng=1 nrd=0 nrs=0 +MP3 net10 QIN VDD VDD sg13_lv_pmos m=1 w=480.00n l=130.00n ng=1 nrd=0 ++ nrs=0 +MP1 net16 net10 VDD VDD sg13_lv_pmos m=1 w=480.00n l=130.00n ng=1 ++ nrd=0 nrs=0 +MP6 QIN CPN net20 VDD sg13_lv_pmos m=1 w=975.000n l=130.00n ng=1 nrd=0 ++ nrs=0 +MP5 net20 D VDD VDD sg13_lv_pmos m=1 w=975.000n l=130.00n ng=1 nrd=0 ++ nrs=0 +.ENDS +.SUBCKT RSC_IHPSG13_NAND2X2 A B Z VDD VSS +MP1 Z B VDD VDD sg13_lv_pmos m=1 w=1.62u l=130.00n ng=1 nrd=0 nrs=0 +MP0 Z A VDD VDD sg13_lv_pmos m=1 w=1.62u l=130.00n ng=1 nrd=0 nrs=0 +MN0 Z B net7 VSS sg13_lv_nmos m=1 w=980.00n l=130.00n ng=1 nrd=0 nrs=0 +MN1 net7 A VSS VSS sg13_lv_nmos m=1 w=980.00n l=130.00n ng=1 nrd=0 ++ nrs=0 +.ENDS +.SUBCKT RSC_IHPSG13_CINVX4 A Z VDD VSS +MN0 Z A VSS VSS sg13_lv_nmos m=1 w=1.41u l=130.00n ng=2 nrd=0 nrs=0 +MP0 Z A VDD VDD sg13_lv_pmos m=1 w=3.24u l=130.00n ng=2 nrd=0 nrs=0 +.ENDS +.SUBCKT RSC_IHPSG13_CINVX2 A Z VDD VSS +MN0 Z A VSS VSS sg13_lv_nmos m=1 w=705.000n l=130.00n ng=1 nrd=0 nrs=0 +MP0 Z A VDD VDD sg13_lv_pmos m=1 w=1.62u l=130.00n ng=1 nrd=0 nrs=0 +.ENDS +.SUBCKT RSC_IHPSG13_INVX2 A Z VDD VSS +MN0 Z A VSS VSS sg13_lv_nmos m=1 w=980.00n l=130.00n ng=1 nrd=0 nrs=0 +MP0 Z A VDD VDD sg13_lv_pmos m=1 w=1.62u l=130.00n ng=1 nrd=0 nrs=0 +.ENDS +.SUBCKT RSC_IHPSG13_NAND3X2 A B C Z VDD VSS +MP2 Z A VDD VDD sg13_lv_pmos m=1 w=1.62u l=130.00n ng=1 nrd=0 nrs=0 +MP1 Z B VDD VDD sg13_lv_pmos m=1 w=1.62u l=130.00n ng=1 nrd=0 nrs=0 +MP0 Z C VDD VDD sg13_lv_pmos m=1 w=1.62u l=130.00n ng=1 nrd=0 nrs=0 +MN1 net12 B net16 VSS sg13_lv_nmos m=1 w=980.00n l=130.00n ng=1 nrd=0 nrs=0 +MN0 Z C net12 VSS sg13_lv_nmos m=1 w=980.00n l=130.00n ng=1 nrd=0 nrs=0 +MN2 net16 A VSS VSS sg13_lv_nmos m=1 w=980.00n l=130.00n ng=1 nrd=0 ++ nrs=0 +.ENDS +.SUBCKT RSC_IHPSG13_NOR3X2 A B C Z VDD VSS +MP0 net13 A VDD VDD sg13_lv_pmos m=1 w=1.62u l=130.00n ng=1 nrd=0 nrs=0 +MP2 Z C net10 VDD sg13_lv_pmos m=1 w=1.62u l=130.00n ng=1 nrd=0 nrs=0 +MP1 net10 B net13 VDD sg13_lv_pmos m=1 w=1.62u l=130.00n ng=1 nrd=0 nrs=0 +MN1 Z B VSS VSS sg13_lv_nmos m=1 w=875.000n l=130.00n ng=1 nrd=0 nrs=0 +MN0 Z C VSS VSS sg13_lv_nmos m=1 w=875.000n l=130.00n ng=1 nrd=0 nrs=0 +MN2 Z A VSS VSS sg13_lv_nmos m=1 w=875.000n l=130.00n ng=1 nrd=0 nrs=0 +.ENDS +.SUBCKT RSC_IHPSG13_FILLCAP4 VDD VSS +MN0 vss_r vdd_r VSS VSS sg13_lv_nmos m=1 w=2.49u l=130.00n ng=3 nrd=0 ++ nrs=0 +MP0 vdd_r vss_r VDD VDD sg13_lv_pmos m=1 w=3.24u l=385.000n ng=2 nrd=0 ++ nrs=0 +.ENDS +.SUBCKT RSC_IHPSG13_MET2RES A B +R0 B A lvsres w=2.6e-07 l=6e-07 +.ENDS +.SUBCKT RM_IHPSG13_8192x32_c4_1P_DEC04 ADDR<3> ADDR<2> ADDR<1> ADDR<0> CS ECLK_H_BOT ++ ECLK_H_TOP ECLK_L_BOT ECLK_L_TOP WL<15> WL<14> WL<13> WL<12> WL<11> WL<10> ++ WL<9> WL<8> WL<7> WL<6> WL<5> WL<4> WL<3> WL<2> WL<1> WL<0> VDD VSS +XLATCH<3> CS ADDR<3> PADR<3> VDD VSS / RSC_IHPSG13_LHPQX2 +XLATCH<2> CS ADDR<2> PADR<2> VDD VSS / RSC_IHPSG13_LHPQX2 +XLATCH<1> CS ADDR<1> PADR<1> VDD VSS / RSC_IHPSG13_LHPQX2 +XLATCH<0> CS ADDR<0> PADR<0> VDD VSS / RSC_IHPSG13_LHPQX2 +XI0<3> PADR<1> PADR<0> sel01<3> VDD VSS / RSC_IHPSG13_NAND2X2 +XI0<2> PADR<1> NADR<0> sel01<2> VDD VSS / RSC_IHPSG13_NAND2X2 +XI0<1> NADR<1> PADR<0> sel01<1> VDD VSS / RSC_IHPSG13_NAND2X2 +XI0<0> NADR<1> NADR<0> sel01<0> VDD VSS / RSC_IHPSG13_NAND2X2 +XI4 ECLK_L_BOT EN VDD VSS / RSC_IHPSG13_CINVX4 +XI5 ECLK_H_BOT ECLK_L_BOT VDD VSS / RSC_IHPSG13_CINVX2 +XI3<3> PADR<3> NADR<3> VDD VSS / RSC_IHPSG13_INVX2 +XI3<2> PADR<2> NADR<2> VDD VSS / RSC_IHPSG13_INVX2 +XI3<1> PADR<1> NADR<1> VDD VSS / RSC_IHPSG13_INVX2 +XI3<0> PADR<0> NADR<0> VDD VSS / RSC_IHPSG13_INVX2 +XI1<3> PADR<2> PADR<3> CS sel23<3> VDD VSS / RSC_IHPSG13_NAND3X2 +XI1<2> NADR<2> PADR<3> CS sel23<2> VDD VSS / RSC_IHPSG13_NAND3X2 +XI1<1> PADR<2> NADR<3> CS sel23<1> VDD VSS / RSC_IHPSG13_NAND3X2 +XI1<0> NADR<2> NADR<3> CS sel23<0> VDD VSS / RSC_IHPSG13_NAND3X2 +XI2<15> sel23<3> sel01<3> EN WL<15> VDD VSS / RSC_IHPSG13_NOR3X2 +XI2<14> sel23<3> sel01<2> EN WL<14> VDD VSS / RSC_IHPSG13_NOR3X2 +XI2<13> sel23<3> sel01<1> EN WL<13> VDD VSS / RSC_IHPSG13_NOR3X2 +XI2<12> sel23<3> sel01<0> EN WL<12> VDD VSS / RSC_IHPSG13_NOR3X2 +XI2<11> sel23<2> sel01<3> EN WL<11> VDD VSS / RSC_IHPSG13_NOR3X2 +XI2<10> sel23<2> sel01<2> EN WL<10> VDD VSS / RSC_IHPSG13_NOR3X2 +XI2<9> sel23<2> sel01<1> EN WL<9> VDD VSS / RSC_IHPSG13_NOR3X2 +XI2<8> sel23<2> sel01<0> EN WL<8> VDD VSS / RSC_IHPSG13_NOR3X2 +XI2<7> sel23<1> sel01<3> EN WL<7> VDD VSS / RSC_IHPSG13_NOR3X2 +XI2<6> sel23<1> sel01<2> EN WL<6> VDD VSS / RSC_IHPSG13_NOR3X2 +XI2<5> sel23<1> sel01<1> EN WL<5> VDD VSS / RSC_IHPSG13_NOR3X2 +XI2<4> sel23<1> sel01<0> EN WL<4> VDD VSS / RSC_IHPSG13_NOR3X2 +XI2<3> sel23<0> sel01<3> EN WL<3> VDD VSS / RSC_IHPSG13_NOR3X2 +XI2<2> sel23<0> sel01<2> EN WL<2> VDD VSS / RSC_IHPSG13_NOR3X2 +XI2<1> sel23<0> sel01<1> EN WL<1> VDD VSS / RSC_IHPSG13_NOR3X2 +XI2<0> sel23<0> sel01<0> EN WL<0> VDD VSS / RSC_IHPSG13_NOR3X2 +XCAPS4 VDD VSS / RSC_IHPSG13_FILLCAP4 +XI11 ECLK_L_BOT ECLK_L_TOP / RSC_IHPSG13_MET2RES +XR0 ECLK_H_BOT ECLK_H_TOP / RSC_IHPSG13_MET2RES +.ENDS +.SUBCKT RM_IHPSG13_8192x32_c4_1P_ROWDEC4 ADDR_N_I<3> ADDR_N_I<2> ADDR_N_I<1> ADDR_N_I<0> ++ CS_I ECLK_I WL_O<15> WL_O<14> WL_O<13> WL_O<12> WL_O<11> WL_O<10> WL_O<9> ++ WL_O<8> WL_O<7> WL_O<6> WL_O<5> WL_O<4> WL_O<3> WL_O<2> WL_O<1> WL_O<0> ++ VDD VSS +XL2<8> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<7> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<6> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<5> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<4> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<3> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<2> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<1> VDD VSS / RSC_IHPSG13_FILLCAP8 +XSEL ADDR_N_I<3> ADDR_N_I<2> ADDR_N_I<1> ADDR_N_I<0> CS_I ECLK_I ECLK_H<1> ++ ECLK_B<0> ECLK_B<1> WL_O<15> WL_O<14> WL_O<13> WL_O<12> WL_O<11> WL_O<10> ++ WL_O<9> WL_O<8> WL_O<7> WL_O<6> WL_O<5> WL_O<4> WL_O<3> WL_O<2> WL_O<1> ++ WL_O<0> VDD VSS / RM_IHPSG13_8192x32_c4_1P_DEC04 +.ENDS +.SUBCKT RSC_IHPSG13_CINVX8 A Z VDD VSS +MN0 Z A VSS VSS sg13_lv_nmos m=1 w=2.82u l=130.00n ng=4 nrd=0 nrs=0 +MP0 Z A VDD VDD sg13_lv_pmos m=1 w=6.48u l=130.00n ng=4 nrd=0 nrs=0 +.ENDS +.SUBCKT RSC_IHPSG13_DFNQMX2IX1 BE BI CN D QI QIN VDD VSS +MN15 net026 BI VSS VSS sg13_lv_nmos m=1 w=560.00n l=130.00n ng=1 nrd=0 ++ nrs=0 +MN14 MXI_OUT BE net026 VSS sg13_lv_nmos m=1 w=560.00n l=130.00n ng=1 nrd=0 ++ nrs=0 +MN1 net025 D VSS VSS sg13_lv_nmos m=1 w=560.00n l=130.00n ng=1 nrd=0 ++ nrs=0 +MN0 MXI_OUT BEN net025 VSS sg13_lv_nmos m=1 w=560.00n l=130.00n ng=1 nrd=0 ++ nrs=0 +MN10 QI CNN net21 VSS sg13_lv_nmos m=1 w=850.00n l=130.00n ng=1 nrd=0 nrs=0 +MN11 net21 QI_MS VSS VSS sg13_lv_nmos m=1 w=850.00n l=130.00n ng=1 ++ nrd=0 nrs=0 +MN7 net30 QI_MS VSS VSS sg13_lv_nmos m=1 w=480.00n l=130.00n ng=1 ++ nrd=0 nrs=0 +MN6 QIN_MS CNN net30 VSS sg13_lv_nmos m=1 w=480.00n l=130.00n ng=1 nrd=0 ++ nrs=0 +MN3 QI_MS QIN_MS VSS VSS sg13_lv_nmos m=1 w=480.00n l=130.00n ng=1 ++ nrd=0 nrs=0 +MN12 CNN CN VSS VSS sg13_lv_nmos m=1 w=495.000n l=130.00n ng=1 nrd=0 ++ nrs=0 +MN9 net37 MXI_OUT VSS VSS sg13_lv_nmos m=1 w=870.00n l=130.00n ng=1 ++ nrd=0 nrs=0 +MN8 QIN_MS CN net37 VSS sg13_lv_nmos m=1 w=870.00n l=130.00n ng=1 nrd=0 ++ nrs=0 +MN5 QI CN net25 VSS sg13_lv_nmos m=1 w=480.00n l=130.00n ng=1 nrd=0 nrs=0 +MN4 net25 QIN VSS VSS sg13_lv_nmos m=1 w=480.00n l=130.00n ng=1 nrd=0 ++ nrs=0 +MN2 QIN QI VSS VSS sg13_lv_nmos m=1 w=480.00n l=130.00n ng=1 nrd=0 ++ nrs=0 +MN13 BEN BE VSS VSS sg13_lv_nmos m=1 w=560.00n l=130.00n ng=1 nrd=0 ++ nrs=0 +MP15 MXI_OUT BEN net027 VDD sg13_lv_pmos m=1 w=985.000n l=130.00n ng=1 ++ nrd=0 nrs=0 +MP14 net027 BI VDD VDD sg13_lv_pmos m=1 w=985.000n l=130.00n ng=1 ++ nrd=0 nrs=0 +MP1 MXI_OUT BE net024 VDD sg13_lv_pmos m=1 w=985.000n l=130.00n ng=1 nrd=0 ++ nrs=0 +MP0 net024 D VDD VDD sg13_lv_pmos m=1 w=985.000n l=130.00n ng=1 nrd=0 ++ nrs=0 +MP13 BEN BE VDD VDD sg13_lv_pmos m=1 w=645.000n l=130.00n ng=1 nrd=0 ++ nrs=0 +MP6 QI_MS QIN_MS VDD VDD sg13_lv_pmos m=1 w=480.00n l=130.00n ng=1 ++ nrd=0 nrs=0 +MP3 QI CNN net27 VDD sg13_lv_pmos m=1 w=480.00n l=130.00n ng=1 nrd=0 nrs=0 +MP2 net27 QIN VDD VDD sg13_lv_pmos m=1 w=480.00n l=130.00n ng=1 nrd=0 ++ nrs=0 +MP10 net36 MXI_OUT VDD VDD sg13_lv_pmos m=1 w=975.000n l=130.00n ng=1 ++ nrd=0 nrs=0 +MP11 QIN_MS CNN net36 VDD sg13_lv_pmos m=1 w=975.000n l=130.00n ng=1 nrd=0 ++ nrs=0 +MP4 net32 QI_MS VDD VDD sg13_lv_pmos m=1 w=480.00n l=130.00n ng=1 ++ nrd=0 nrs=0 +MP5 QIN_MS CN net32 VDD sg13_lv_pmos m=1 w=480.00n l=130.00n ng=1 nrd=0 ++ nrs=0 +MP7 QIN QI VDD VDD sg13_lv_pmos m=1 w=480.00n l=130.00n ng=1 nrd=0 ++ nrs=0 +MP12 CNN CN VDD VDD sg13_lv_pmos m=1 w=480.00n l=130.00n ng=1 nrd=0 ++ nrs=0 +MP9 QI CN net19 VDD sg13_lv_pmos m=1 w=990.00n l=130.00n ng=1 nrd=0 nrs=0 +MP8 net19 QI_MS VDD VDD sg13_lv_pmos m=1 w=990.00n l=130.00n ng=1 ++ nrd=0 nrs=0 +.ENDS +.SUBCKT RM_IHPSG13_8192x32_c4_1P_ROWREG4 ACLK_N_I ADDR_I<3> ADDR_I<2> ADDR_I<1> ADDR_I<0> ++ ADDR_N_O<3> ADDR_N_O<2> ADDR_N_O<1> ADDR_N_O<0> BIST_ADDR_I<3> ++ BIST_ADDR_I<2> BIST_ADDR_I<1> BIST_ADDR_I<0> BIST_EN_I VDD VSS +XINV<3> q_int<3> qn_int<3> VDD VSS / RSC_IHPSG13_CINVX2 +XINV<2> q_int<2> qn_int<2> VDD VSS / RSC_IHPSG13_CINVX2 +XINV<1> q_int<1> qn_int<1> VDD VSS / RSC_IHPSG13_CINVX2 +XINV<0> q_int<0> qn_int<0> VDD VSS / RSC_IHPSG13_CINVX2 +XDRV<3> qn_int<3> ADDR_N_O<3> VDD VSS / RSC_IHPSG13_CINVX8 +XDRV<2> qn_int<2> ADDR_N_O<2> VDD VSS / RSC_IHPSG13_CINVX8 +XDRV<1> qn_int<1> ADDR_N_O<1> VDD VSS / RSC_IHPSG13_CINVX8 +XDRV<0> qn_int<0> ADDR_N_O<0> VDD VSS / RSC_IHPSG13_CINVX8 +XDFF<3> BIST_EN_I BIST_ADDR_I<3> ACLK_N_I ADDR_I<3> q_int<3> net2<0> VDD ++ VSS / RSC_IHPSG13_DFNQMX2IX1 +XDFF<2> BIST_EN_I BIST_ADDR_I<2> ACLK_N_I ADDR_I<2> q_int<2> net2<1> VDD ++ VSS / RSC_IHPSG13_DFNQMX2IX1 +XDFF<1> BIST_EN_I BIST_ADDR_I<1> ACLK_N_I ADDR_I<1> q_int<1> net2<2> VDD ++ VSS / RSC_IHPSG13_DFNQMX2IX1 +XDFF<0> BIST_EN_I BIST_ADDR_I<0> ACLK_N_I ADDR_I<0> q_int<0> net2<3> VDD ++ VSS / RSC_IHPSG13_DFNQMX2IX1 +XI11<20> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI11<19> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI11<18> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI11<17> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI11<16> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI11<15> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI11<14> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI11<13> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI11<12> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI11<11> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI11<10> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI11<9> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI11<8> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI11<7> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI11<6> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI11<5> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI11<4> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI11<3> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI11<2> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI11<1> VDD VSS / RSC_IHPSG13_FILLCAP8 +.ENDS +.SUBCKT RSC_IHPSG13_CDLYX1 A Z VDD VSS +MN1 net010 net032 VSS VSS sg13_lv_nmos m=1 w=300.0n l=160.00n ng=1 ++ nrd=0 nrs=0 +MN2 net032 A net014 VSS sg13_lv_nmos m=1 w=300.0n l=160.00n ng=1 nrd=0 ++ nrs=0 +MN0 Z net032 net010 VSS sg13_lv_nmos m=1 w=300.0n l=160.00n ng=1 nrd=0 ++ nrs=0 +MN3 net014 A VSS VSS sg13_lv_nmos m=1 w=300.0n l=160.00n ng=1 nrd=0 ++ nrs=0 +MP1 Z net032 net07 VDD sg13_lv_pmos m=1 w=720.00n l=160.00n ng=1 nrd=0 ++ nrs=0 +MP3 net011 A VDD VDD sg13_lv_pmos m=1 w=720.00n l=160.00n ng=1 nrd=0 ++ nrs=0 +MP0 net07 net032 VDD VDD sg13_lv_pmos m=1 w=720.00n l=160.00n ng=1 ++ nrd=0 nrs=0 +MP2 net032 A net011 VDD sg13_lv_pmos m=1 w=720.00n l=160.00n ng=1 nrd=0 ++ nrs=0 +.ENDS +.SUBCKT RSC_IHPSG13_CDLYX1_DUMMY A Z VDD VSS +MN0 vss_r vdd_r VSS VSS sg13_lv_nmos m=1 w=2.49u l=300.0n ng=3 nrd=0 ++ nrs=0 +MP0 vdd_r vss_r VDD VDD sg13_lv_pmos m=1 w=3.24u l=640.00n ng=2 nrd=0 ++ nrs=0 +R0 Z A lvsres w=2.6e-07 l=6e-07 +.ENDS + +.SUBCKT RSC_IHPSG13_MX2IX1 A0 A1 S ZN VDD VSS +MP4 SN S VDD VDD sg13_lv_pmos m=1 w=645.000n l=130.00n ng=1 nrd=0 nrs=0 +MP3 ZN SN net12 VDD sg13_lv_pmos m=1 w=985.000n l=130.00n ng=1 nrd=0 nrs=0 +MP2 net12 A1 VDD VDD sg13_lv_pmos m=1 w=985.000n l=130.00n ng=1 nrd=0 ++ nrs=0 +MP1 ZN S net17 VDD sg13_lv_pmos m=1 w=985.000n l=130.00n ng=1 nrd=0 nrs=0 +MP0 net17 A0 VDD VDD sg13_lv_pmos m=1 w=985.000n l=130.00n ng=1 nrd=0 ++ nrs=0 +MN5 SN S VSS VSS sg13_lv_nmos m=1 w=480.00n l=130.00n ng=1 nrd=0 nrs=0 +MN3 net13 A1 VSS VSS sg13_lv_nmos m=1 w=480.00n l=130.00n ng=1 nrd=0 ++ nrs=0 +MN2 ZN S net13 VSS sg13_lv_nmos m=1 w=480.00n l=130.00n ng=1 nrd=0 nrs=0 +MN1 net15 A0 VSS VSS sg13_lv_nmos m=1 w=480.00n l=130.00n ng=1 nrd=0 ++ nrs=0 +MN0 ZN SN net15 VSS sg13_lv_nmos m=1 w=480.00n l=130.00n ng=1 nrd=0 nrs=0 +.ENDS +.SUBCKT RM_IHPSG13_8192x32_c4_1P_DLY_MUX A SEL Z VDD VSS +XI11 net4 Z VDD VSS / RSC_IHPSG13_CINVX2 +XI8 A D<3> SEL net4 VDD VSS / RSC_IHPSG13_MX2IX1 +XI20<3> D<2> D<3> VDD VSS / RSC_IHPSG13_CDLYX1 +XI20<2> D<1> D<2> VDD VSS / RSC_IHPSG13_CDLYX1 +XI20<1> A D<1> VDD VSS / RSC_IHPSG13_CDLYX1 +.ENDS +.SUBCKT RSC_IHPSG13_DFNQX2 CN D Q VDD VSS +MN0 Q QIN_SL VSS VSS sg13_lv_nmos m=1 w=980.00n l=130.00n ng=1 nrd=0 ++ nrs=0 +MN10 QIN_SL CNN net21 VSS sg13_lv_nmos m=1 w=850.00n l=130.00n ng=1 nrd=0 ++ nrs=0 +MN11 net21 QI_MS VSS VSS sg13_lv_nmos m=1 w=850.00n l=130.00n ng=1 ++ nrd=0 nrs=0 +MN7 net30 QI_MS VSS VSS sg13_lv_nmos m=1 w=480.00n l=130.00n ng=1 ++ nrd=0 nrs=0 +MN6 QIN_MS CNN net30 VSS sg13_lv_nmos m=1 w=480.00n l=130.00n ng=1 nrd=0 ++ nrs=0 +MN3 QI_MS QIN_MS VSS VSS sg13_lv_nmos m=1 w=480.00n l=130.00n ng=1 ++ nrd=0 nrs=0 +MN12 CNN CN VSS VSS sg13_lv_nmos m=1 w=495.000n l=130.00n ng=1 nrd=0 ++ nrs=0 +MN9 net37 D VSS VSS sg13_lv_nmos m=1 w=870.00n l=130.00n ng=1 nrd=0 ++ nrs=0 +MN8 QIN_MS CN net37 VSS sg13_lv_nmos m=1 w=870.00n l=130.00n ng=1 nrd=0 ++ nrs=0 +MN5 QIN_SL CN net25 VSS sg13_lv_nmos m=1 w=480.00n l=130.00n ng=1 nrd=0 ++ nrs=0 +MN4 net25 QI_SL VSS VSS sg13_lv_nmos m=1 w=480.00n l=130.00n ng=1 ++ nrd=0 nrs=0 +MN2 QI_SL QIN_SL VSS VSS sg13_lv_nmos m=1 w=480.00n l=130.00n ng=1 ++ nrd=0 nrs=0 +MP0 Q QIN_SL VDD VDD sg13_lv_pmos m=1 w=1.62u l=130.00n ng=1 nrd=0 ++ nrs=0 +MP6 QI_MS QIN_MS VDD VDD sg13_lv_pmos m=1 w=480.00n l=130.00n ng=1 ++ nrd=0 nrs=0 +MP3 QIN_SL CNN net27 VDD sg13_lv_pmos m=1 w=480.00n l=130.00n ng=1 nrd=0 ++ nrs=0 +MP2 net27 QI_SL VDD VDD sg13_lv_pmos m=1 w=480.00n l=130.00n ng=1 ++ nrd=0 nrs=0 +MP10 net36 D VDD VDD sg13_lv_pmos m=1 w=975.000n l=130.00n ng=1 nrd=0 ++ nrs=0 +MP11 QIN_MS CNN net36 VDD sg13_lv_pmos m=1 w=975.000n l=130.00n ng=1 nrd=0 ++ nrs=0 +MP4 net32 QI_MS VDD VDD sg13_lv_pmos m=1 w=480.00n l=130.00n ng=1 ++ nrd=0 nrs=0 +MP5 QIN_MS CN net32 VDD sg13_lv_pmos m=1 w=480.00n l=130.00n ng=1 nrd=0 ++ nrs=0 +MP7 QI_SL QIN_SL VDD VDD sg13_lv_pmos m=1 w=480.00n l=130.00n ng=1 ++ nrd=0 nrs=0 +MP12 CNN CN VDD VDD sg13_lv_pmos m=1 w=480.00n l=130.00n ng=1 nrd=0 ++ nrs=0 +MP9 QIN_SL CN net19 VDD sg13_lv_pmos m=1 w=990.00n l=130.00n ng=1 nrd=0 ++ nrs=0 +MP8 net19 QI_MS VDD VDD sg13_lv_pmos m=1 w=990.00n l=130.00n ng=1 ++ nrd=0 nrs=0 +.ENDS +.SUBCKT RSC_IHPSG13_CNAND2X2 A B Z VDD VSS +MN0 Z B net6 VSS sg13_lv_nmos m=1 w=980.00n l=130.00n ng=1 nrd=0 nrs=0 +MN1 net6 A VSS VSS sg13_lv_nmos m=1 w=980.00n l=130.00n ng=1 nrd=0 ++ nrs=0 +MP1 Z B VDD VDD sg13_lv_pmos m=1 w=1.62u l=130.00n ng=1 nrd=0 nrs=0 +MP0 Z A VDD VDD sg13_lv_pmos m=1 w=1.62u l=130.00n ng=1 nrd=0 nrs=0 +.ENDS +.SUBCKT RSC_IHPSG13_CGATEPX4 CP E Q VDD VSS +MN1 net08 QIN VSS VSS sg13_lv_nmos m=1 w=480.00n l=130.00n ng=1 nrd=0 ++ nrs=0 +MN2 net019 net08 VSS VSS sg13_lv_nmos m=1 w=480.00n l=130.00n ng=1 ++ nrd=0 nrs=0 +MN3 QIN CP net019 VSS sg13_lv_nmos m=1 w=480.00n l=130.00n ng=1 nrd=0 nrs=0 +MN6 Q net015 VSS VSS sg13_lv_nmos m=1 w=1.41u l=130.00n ng=2 nrd=0 ++ nrs=0 +MN5 net015 net08 net018 VSS sg13_lv_nmos m=1 w=980.00n l=130.00n ng=1 ++ nrd=0 nrs=0 +MN8 QIN CPN net023 VSS sg13_lv_nmos m=1 w=870.00n l=130.00n ng=1 nrd=0 ++ nrs=0 +MN7 net023 E VSS VSS sg13_lv_nmos m=1 w=870.00n l=130.00n ng=1 nrd=0 ++ nrs=0 +MN4 net018 CP VSS VSS sg13_lv_nmos m=1 w=980.00n l=130.00n ng=1 nrd=0 ++ nrs=0 +MN0 CPN CP VSS VSS sg13_lv_nmos m=1 w=500.0n l=130.00n ng=1 nrd=0 nrs=0 +MP3 net08 QIN VDD VDD sg13_lv_pmos m=1 w=480.00n l=130.00n ng=1 nrd=0 ++ nrs=0 +MP2 QIN CPN net017 VDD sg13_lv_pmos m=1 w=480.00n l=130.00n ng=1 nrd=0 ++ nrs=0 +MP1 net017 net08 VDD VDD sg13_lv_pmos m=1 w=480.00n l=130.00n ng=1 ++ nrd=0 nrs=0 +MP0 CPN CP VDD VDD sg13_lv_pmos m=1 w=500.0n l=130.00n ng=1 nrd=0 nrs=0 +MP8 QIN CP net024 VDD sg13_lv_pmos m=1 w=975.000n l=130.00n ng=1 nrd=0 ++ nrs=0 +MP7 net024 E VDD VDD sg13_lv_pmos m=1 w=975.000n l=130.00n ng=1 nrd=0 ++ nrs=0 +MP4 net015 CP VDD VDD sg13_lv_pmos m=1 w=1.27u l=130.00n ng=1 nrd=0 ++ nrs=0 +MP6 Q net015 VDD VDD sg13_lv_pmos m=1 w=3.24u l=130.00n ng=2 nrd=0 ++ nrs=0 +MP5 net015 net08 VDD VDD sg13_lv_pmos m=1 w=1.27u l=130.00n ng=1 nrd=0 ++ nrs=0 +.ENDS +.SUBCKT RSC_IHPSG13_CBUFX8 A Z VDD VSS +MP0 net4 A VDD VDD sg13_lv_pmos m=1 w=3.24u l=130.00n ng=2 nrd=0 nrs=0 +MP1 Z net4 VDD VDD sg13_lv_pmos m=1 w=6.48u l=130.00n ng=4 nrd=0 nrs=0 +MN1 Z net4 VSS VSS sg13_lv_nmos m=1 w=2.82u l=130.00n ng=4 nrd=0 nrs=0 +MN0 net4 A VSS VSS sg13_lv_nmos m=1 w=1.41u l=130.00n ng=2 nrd=0 nrs=0 +.ENDS +.SUBCKT RSC_IHPSG13_CDLYX2 A Z VDD VSS +MN2 net4 A net9 VSS sg13_lv_nmos m=1 w=320.00n l=200.0n ng=1 nrd=0 nrs=0 +MN0 Z net4 VSS VSS sg13_lv_nmos m=1 w=705.000n l=130.00n ng=1 nrd=0 ++ nrs=0 +MN1 net9 A VSS VSS sg13_lv_nmos m=1 w=320.00n l=200.0n ng=1 nrd=0 nrs=0 +MP2 net4 A net10 VDD sg13_lv_pmos m=1 w=1.2u l=200.0n ng=1 nrd=0 nrs=0 +MP1 net10 A VDD VDD sg13_lv_pmos m=1 w=1.2u l=200.0n ng=1 nrd=0 nrs=0 +MP0 Z net4 VDD VDD sg13_lv_pmos m=1 w=1.62u l=130.00n ng=1 nrd=0 nrs=0 +.ENDS +.SUBCKT RSC_IHPSG13_MX2X2 A0 A1 S Z VDD VSS +MP6 Z net010 VDD VDD sg13_lv_pmos m=1 w=1.62u l=130.00n ng=1 nrd=0 ++ nrs=0 +MP4 SN S VDD VDD sg13_lv_pmos m=1 w=645.000n l=130.00n ng=1 nrd=0 nrs=0 +MP3 net010 SN net12 VDD sg13_lv_pmos m=1 w=985.000n l=130.00n ng=1 nrd=0 ++ nrs=0 +MP2 net12 A1 VDD VDD sg13_lv_pmos m=1 w=985.000n l=130.00n ng=1 nrd=0 ++ nrs=0 +MP1 net010 S net17 VDD sg13_lv_pmos m=1 w=985.000n l=130.00n ng=1 nrd=0 ++ nrs=0 +MP0 net17 A0 VDD VDD sg13_lv_pmos m=1 w=985.000n l=130.00n ng=1 nrd=0 ++ nrs=0 +MN6 Z net010 VSS VSS sg13_lv_nmos m=1 w=705.000n l=130.00n ng=1 nrd=0 ++ nrs=0 +MN5 SN S VSS VSS sg13_lv_nmos m=1 w=560.00n l=130.00n ng=1 nrd=0 nrs=0 +MN3 net13 A1 VSS VSS sg13_lv_nmos m=1 w=560.00n l=130.00n ng=1 nrd=0 ++ nrs=0 +MN2 net010 S net13 VSS sg13_lv_nmos m=1 w=560.00n l=130.00n ng=1 nrd=0 ++ nrs=0 +MN1 net15 A0 VSS VSS sg13_lv_nmos m=1 w=560.00n l=130.00n ng=1 nrd=0 ++ nrs=0 +MN0 net010 SN net15 VSS sg13_lv_nmos m=1 w=560.00n l=130.00n ng=1 nrd=0 ++ nrs=0 +.ENDS +.SUBCKT RSC_IHPSG13_AND2X2 A B Z VDD VSS +MN3 Z net6 VSS VSS sg13_lv_nmos m=1 w=980.00n l=130.00n ng=1 nrd=0 ++ nrs=0 +MN4 net9 B VSS VSS sg13_lv_nmos m=1 w=500.0n l=130.00n ng=1 nrd=0 nrs=0 +MN6 net6 A net9 VSS sg13_lv_nmos m=1 w=500.0n l=130.00n ng=1 nrd=0 nrs=0 +MP2 Z net6 VDD VDD sg13_lv_pmos m=1 w=1.62u l=130.00n ng=1 nrd=0 nrs=0 +MP0 net6 B VDD VDD sg13_lv_pmos m=1 w=860.00n l=130.00n ng=1 nrd=0 ++ nrs=0 +MP1 net6 A VDD VDD sg13_lv_pmos m=1 w=860.00n l=130.00n ng=1 nrd=0 ++ nrs=0 +.ENDS +.SUBCKT RSC_IHPSG13_TIEL Z VDD VSS +MN0 Z net2 VSS VSS sg13_lv_nmos m=1 w=480.00n l=130.00n ng=1 nrd=0 ++ nrs=0 +MP0 net2 net2 VDD VDD sg13_lv_pmos m=1 w=480.00n l=130.00n ng=1 nrd=0 ++ nrs=0 +.ENDS +.SUBCKT RSC_IHPSG13_XOR2X2 A B Z VDD VSS +MP8 net012 B net7 VDD sg13_lv_pmos m=1 w=825.000n l=130.00n ng=1 nrd=0 ++ nrs=0 +MP7 net011 net3 net012 VDD sg13_lv_pmos m=1 w=825.000n l=130.00n ng=1 ++ nrd=0 nrs=0 +MP6 Z net012 VDD VDD sg13_lv_pmos m=1 w=1.535u l=130.00n ng=1 nrd=0 ++ nrs=0 +MP2 net7 A VDD VDD sg13_lv_pmos m=1 w=825.000n l=130.00n ng=1 nrd=0 ++ nrs=0 +MP4 net011 net7 VDD VDD sg13_lv_pmos m=1 w=825.000n l=130.00n ng=1 ++ nrd=0 nrs=0 +MP5 net3 B VDD VDD sg13_lv_pmos m=1 w=580.00n l=130.00n ng=1 nrd=0 ++ nrs=0 +MN7 net012 B net011 VSS sg13_lv_nmos m=1 w=555.000n l=130.00n ng=1 nrd=0 ++ nrs=0 +MN6 net7 net3 net012 VSS sg13_lv_nmos m=1 w=555.000n l=130.00n ng=1 nrd=0 ++ nrs=0 +MN5 Z net012 VSS VSS sg13_lv_nmos m=1 w=775.000n l=130.00n ng=1 nrd=0 ++ nrs=0 +MN2 net7 A VSS VSS sg13_lv_nmos m=1 w=555.000n l=130.00n ng=1 nrd=0 ++ nrs=0 +MN4 net3 B VSS VSS sg13_lv_nmos m=1 w=480.00n l=130.00n ng=1 nrd=0 ++ nrs=0 +MN3 net011 net7 VSS VSS sg13_lv_nmos m=1 w=555.000n l=130.00n ng=1 ++ nrd=0 nrs=0 +.ENDS +.SUBCKT RSC_IHPSG13_OA12X1 A B C Z VDD VSS +MN2 net7 C VSS VSS sg13_lv_nmos m=1 w=980.00n l=130.00n ng=1 nrd=0 ++ nrs=0 +MN3 Z net17 VSS VSS sg13_lv_nmos m=1 w=500.0n l=130.00n ng=1 nrd=0 ++ nrs=0 +MN1 net17 B net7 VSS sg13_lv_nmos m=1 w=980.00n l=130.00n ng=1 nrd=0 nrs=0 +MN0 net17 A net7 VSS sg13_lv_nmos m=1 w=980.00n l=130.00n ng=1 nrd=0 nrs=0 +MP0 net24 A VDD VDD sg13_lv_pmos m=1 w=1.62u l=130.00n ng=1 nrd=0 nrs=0 +MP3 Z net17 VDD VDD sg13_lv_pmos m=1 w=905.000n l=130.00n ng=1 nrd=0 ++ nrs=0 +MP1 net17 B net24 VDD sg13_lv_pmos m=1 w=1.62u l=130.00n ng=1 nrd=0 nrs=0 +MP2 net17 C VDD VDD sg13_lv_pmos m=1 w=905.000n l=130.00n ng=1 nrd=0 ++ nrs=0 +.ENDS +.SUBCKT RM_IHPSG13_8192x32_c4_1P_CTRL ACLK_N BIST_CK_I BIST_CS_I BIST_EN BIST_RE_I ++ BIST_WE_I B_TIEL_O CK_I CS_I DCLK ECLK PULSE_H PULSE_L PULSE_O RCLK RE_I ++ ROW_CS WCLK WE_I VDD VSS +XI17 ck_regs we col_we VDD VSS / RSC_IHPSG13_DFNQX2 +XI16 ck_regs re col_re VDD VSS / RSC_IHPSG13_DFNQX2 +XI18 ck_regs cs net7 VDD VSS / RSC_IHPSG13_DFNQX2 +XI71 ACLK_N net012 PULSE_O VDD VSS / RSC_IHPSG13_DFNQX2 +XI77 col_we net9 net016 VDD VSS / RSC_IHPSG13_CNAND2X2 +XI76 col_re net9 net018 VDD VSS / RSC_IHPSG13_CNAND2X2 +XI15 ck_dly WEorREandCS aclk VDD VSS / RSC_IHPSG13_CGATEPX4 +XI14 ck WEandCS DCLK VDD VSS / RSC_IHPSG13_CGATEPX4 +XI60 net7 ROW_CS VDD VSS / RSC_IHPSG13_CBUFX8 +XI73 PULSE_O net012 VDD VSS / RSC_IHPSG13_CINVX2 +XI8 net9 net8 VDD VSS / RSC_IHPSG13_CINVX2 +XI64 ck ck_dly VDD VSS / RSC_IHPSG13_CDLYX2 +XI86 CS_I BIST_CS_I BIST_EN cs VDD VSS / RSC_IHPSG13_MX2X2 +XI87 CK_I BIST_CK_I BIST_EN ck VDD VSS / RSC_IHPSG13_MX2X2 +XI85 WE_I BIST_WE_I BIST_EN we VDD VSS / RSC_IHPSG13_MX2X2 +XI84 RE_I BIST_RE_I BIST_EN re VDD VSS / RSC_IHPSG13_MX2X2 +XI22 we cs WEandCS VDD VSS / RSC_IHPSG13_AND2X2 +XBM_TIEL B_TIEL_O VDD VSS / RSC_IHPSG13_TIEL +XI48 ck_dly ck_regs VDD VSS / RSC_IHPSG13_CINVX4 +XI81 net016 WCLK VDD VSS / RSC_IHPSG13_CINVX4 +XI80 net018 RCLK VDD VSS / RSC_IHPSG13_CINVX4 +XI78 net8 net020 VDD VSS / RSC_IHPSG13_CINVX4 +XI6 PULSE_L PULSE_H net9 VDD VSS / RSC_IHPSG13_XOR2X2 +XI79 net020 ECLK VDD VSS / RSC_IHPSG13_CINVX8 +XI63 aclk ACLK_N VDD VSS / RSC_IHPSG13_CINVX8 +XI21 re we cs WEorREandCS VDD VSS / RSC_IHPSG13_OA12X1 +.ENDS +.SUBCKT RM_IHPSG13_8192x32_c4_1P_COLDEC2 ACLK_N ADDR<1> ADDR<0> ADDR_COL<1> ADDR_COL<0> ++ ADDR_DEC<7> ADDR_DEC<6> ADDR_DEC<5> ADDR_DEC<4> ADDR_DEC<3> ADDR_DEC<2> ++ ADDR_DEC<1> ADDR_DEC<0> BIST_ADDR<1> BIST_ADDR<0> BIST_EN_I VDD VSS +XI14<5> VDD VSS / RSC_IHPSG13_FILLCAP4 +XI14<4> VDD VSS / RSC_IHPSG13_FILLCAP4 +XI14<3> VDD VSS / RSC_IHPSG13_FILLCAP4 +XI14<2> VDD VSS / RSC_IHPSG13_FILLCAP4 +XI14<1> VDD VSS / RSC_IHPSG13_FILLCAP4 +XDFF<1> BIST_EN_I BIST_ADDR<1> ACLK_N ADDR<1> padr_int<1> net6<0> VDD ++ VSS / RSC_IHPSG13_DFNQMX2IX1 +XDFF<0> BIST_EN_I BIST_ADDR<0> ACLK_N ADDR<0> padr_int<0> net6<1> VDD ++ VSS / RSC_IHPSG13_DFNQMX2IX1 +XI1<3> PADR<1> PADR<0> addr_n<3> VDD VSS / RSC_IHPSG13_NAND2X2 +XI1<2> PADR<1> NADR<0> addr_n<2> VDD VSS / RSC_IHPSG13_NAND2X2 +XI1<1> NADR<1> PADR<0> addr_n<1> VDD VSS / RSC_IHPSG13_NAND2X2 +XI1<0> NADR<1> NADR<0> addr_n<0> VDD VSS / RSC_IHPSG13_NAND2X2 +XI16<37> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI16<36> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI16<35> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI16<34> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI16<33> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI16<32> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI16<31> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI16<30> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI16<29> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI16<28> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI16<27> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI16<26> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI16<25> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI16<24> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI16<23> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI16<22> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI16<21> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI16<20> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI16<19> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI16<18> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI16<17> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI16<16> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI16<15> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI16<14> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI16<13> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI16<12> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI16<11> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI16<10> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI16<9> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI16<8> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI16<7> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI16<6> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI16<5> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI16<4> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI16<3> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI16<2> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI16<1> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI3<1> padr_int<1> NADR<1> VDD VSS / RSC_IHPSG13_INVX2 +XI3<0> padr_int<0> NADR<0> VDD VSS / RSC_IHPSG13_INVX2 +XI13<1> NADR<1> PADR<1> VDD VSS / RSC_IHPSG13_INVX2 +XI13<0> NADR<0> PADR<0> VDD VSS / RSC_IHPSG13_INVX2 +XI2<3> addr_n<3> ADDR_DEC<3> VDD VSS / RSC_IHPSG13_INVX2 +XI2<2> addr_n<2> ADDR_DEC<2> VDD VSS / RSC_IHPSG13_INVX2 +XI2<1> addr_n<1> ADDR_DEC<1> VDD VSS / RSC_IHPSG13_INVX2 +XI2<0> addr_n<0> ADDR_DEC<0> VDD VSS / RSC_IHPSG13_INVX2 +XI15<1> ADDR_COL<1> VDD VSS / RSC_IHPSG13_TIEL +XI15<0> ADDR_COL<0> VDD VSS / RSC_IHPSG13_TIEL +XI17<3> ADDR_DEC<7> VDD VSS / RSC_IHPSG13_TIEL +XI17<2> ADDR_DEC<6> VDD VSS / RSC_IHPSG13_TIEL +XI17<1> ADDR_DEC<5> VDD VSS / RSC_IHPSG13_TIEL +XI17<0> ADDR_DEC<4> VDD VSS / RSC_IHPSG13_TIEL +.ENDS +.SUBCKT RSC_IHPSG13_NOR2X2 A B Z VDD VSS +MP1 Z B net9 VDD sg13_lv_pmos m=1 w=1.62u l=130.00n ng=1 nrd=0 nrs=0 +MP0 net9 A VDD VDD sg13_lv_pmos m=1 w=1.62u l=130.00n ng=1 nrd=0 nrs=0 +MN0 Z B VSS VSS sg13_lv_nmos m=1 w=980.00n l=130.00n ng=1 nrd=0 nrs=0 +MN1 Z A VSS VSS sg13_lv_nmos m=1 w=980.00n l=130.00n ng=1 nrd=0 nrs=0 +.ENDS +.SUBCKT RSC_IHPSG13_CINVX4_WN A Z VDD VSS +MN0 Z A VSS VSS sg13_lv_nmos m=1 w=705.000n l=130.00n ng=1 nrd=0 nrs=0 +MP0 Z A VDD VDD sg13_lv_pmos m=1 w=3.24u l=130.00n ng=2 nrd=0 nrs=0 +.ENDS +.SUBCKT RM_IHPSG13_8192x32_c4_1P_BLDRV BLC BLC_SEL BLT BLT_SEL PRE_N SEL_P WR_ONE WR_ZERO ++ VDD VSS +XCDEC SEL_P WR_ZERO BLC_PMOS_DRIVE VDD VSS / RSC_IHPSG13_NAND2X2 +XTDEC SEL_P WR_ONE BLT_PMOS_DRIVE VDD VSS / RSC_IHPSG13_NAND2X2 +MTWN BLT BLT_NMOS_DRIVE VSS VSS sg13_lv_nmos m=1 w=4.82u l=130.00n ++ ng=2 nrd=0 nrs=0 +MCWN BLC BLC_NMOS_DRIVE VSS VSS sg13_lv_nmos m=1 w=4.82u l=130.00n ++ ng=2 nrd=0 nrs=0 +MCWP BLC BLC_PMOS_DRIVE VDD VDD sg13_lv_pmos m=1 w=1.5u l=130.00n ng=1 ++ nrd=0 nrs=0 +MTWP BLT BLT_PMOS_DRIVE VDD VDD sg13_lv_pmos m=1 w=1.5u l=130.00n ng=1 ++ nrd=0 nrs=0 +MTSP BLT_SEL SEL_N BLT VDD sg13_lv_pmos m=1 w=1.5u l=130.00n ng=1 nrd=0 ++ nrs=0 +MTPR BLT PRE_N VDD VDD sg13_lv_pmos m=1 w=3.000u l=130.00n ng=2 nrd=0 ++ nrs=0 +MCSP BLC_SEL SEL_N BLC VDD sg13_lv_pmos m=1 w=1.5u l=130.00n ng=1 nrd=0 ++ nrs=0 +MCPR BLC PRE_N VDD VDD sg13_lv_pmos m=1 w=3.000u l=130.00n ng=2 nrd=0 ++ nrs=0 +XI86 SEL_P SEL_N VDD VSS / RSC_IHPSG13_INVX2 +XTINV BLC_PMOS_DRIVE BLT_NMOS_DRIVE VDD VSS / RSC_IHPSG13_INVX2 +XCINV BLT_PMOS_DRIVE BLC_NMOS_DRIVE VDD VSS / RSC_IHPSG13_INVX2 +.ENDS +.SUBCKT RSC_IHPSG13_TIEH Z VDD VSS +MN0 net2 net2 VSS VSS sg13_lv_nmos m=1 w=480.00n l=130.00n ng=1 nrd=0 ++ nrs=0 +MP0 Z net2 VDD VDD sg13_lv_pmos m=1 w=480.00n l=130.00n ng=1 nrd=0 ++ nrs=0 +.ENDS +.SUBCKT RSC_IHPSG13_MET3RES A B +R0 B A lvsres w=2.6e-07 l=6e-07 +.ENDS +.SUBCKT RSC_IHPSG13_DFPQD_MSAFFX2 CP DN DP QN QP VDD VSS +MN12 SN RN DIFFP VSS sg13_lv_nmos m=1 w=2.4u l=200.0n ng=2 nrd=0 nrs=0 +MN13 TAIL CP VSS VSS sg13_lv_nmos m=1 w=2.4u l=130.00n ng=2 nrd=0 nrs=0 +MN9 DIFFP DP TAIL VSS sg13_lv_nmos m=1 w=2.4u l=200.0n ng=2 nrd=0 nrs=0 +MN10 DIFFN DN TAIL VSS sg13_lv_nmos m=1 w=2.4u l=200.0n ng=2 nrd=0 nrs=0 +MN11 RN SN DIFFN VSS sg13_lv_nmos m=1 w=2.4u l=200.0n ng=2 nrd=0 nrs=0 +MN19 net33 SN VSS VSS sg13_lv_nmos m=1 w=980.00n l=130.00n ng=1 nrd=0 ++ nrs=0 +MN20 QN QP net37 VSS sg13_lv_nmos m=1 w=980.00n l=130.00n ng=1 nrd=0 nrs=0 +MN18 net37 RN VSS VSS sg13_lv_nmos m=1 w=980.00n l=130.00n ng=1 nrd=0 ++ nrs=0 +MN17 QP QN net33 VSS sg13_lv_nmos m=1 w=980.00n l=130.00n ng=1 nrd=0 nrs=0 +MP15 SN RN VDD VDD sg13_lv_pmos m=1 w=800.0n l=130.00n ng=1 nrd=0 nrs=0 +MP16 RN CP VDD VDD sg13_lv_pmos m=1 w=800.0n l=130.00n ng=1 nrd=0 nrs=0 +MP14 DIFFP CP VDD VDD sg13_lv_pmos m=1 w=800.0n l=130.00n ng=1 nrd=0 ++ nrs=0 +MP12 RN SN VDD VDD sg13_lv_pmos m=1 w=800.0n l=130.00n ng=1 nrd=0 nrs=0 +MP13 DIFFN CP VDD VDD sg13_lv_pmos m=1 w=800.0n l=130.00n ng=1 nrd=0 ++ nrs=0 +MP11 SN CP VDD VDD sg13_lv_pmos m=1 w=800.0n l=130.00n ng=1 nrd=0 nrs=0 +MP19 QN QP VDD VDD sg13_lv_pmos m=1 w=900.0n l=130.00n ng=1 nrd=0 nrs=0 +MP20 QP SN VDD VDD sg13_lv_pmos m=1 w=1.8u l=130.00n ng=2 nrd=0 nrs=0 +MP18 QN RN VDD VDD sg13_lv_pmos m=1 w=1.8u l=130.00n ng=2 nrd=0 nrs=0 +MP17 QP QN VDD VDD sg13_lv_pmos m=1 w=900.0n l=130.00n ng=1 nrd=0 nrs=0 +.ENDS +.SUBCKT RSC_IHPSG13_CBUFX2 A Z VDD VSS +MN1 Z net4 VSS VSS sg13_lv_nmos m=1 w=705.000n l=130.00n ng=1 nrd=0 ++ nrs=0 +MN0 net4 A VSS VSS sg13_lv_nmos m=1 w=540.00n l=130.00n ng=1 nrd=0 ++ nrs=0 +MP1 Z net4 VDD VDD sg13_lv_pmos m=1 w=1.62u l=130.00n ng=1 nrd=0 nrs=0 +MP0 net4 A VDD VDD sg13_lv_pmos m=1 w=1.1u l=130.00n ng=1 nrd=0 nrs=0 +.ENDS +.SUBCKT RSC_IHPSG13_INVX4 A Z VDD VSS +MN0 Z A VSS VSS sg13_lv_nmos m=1 w=1.96u l=130.00n ng=2 nrd=0 nrs=0 +MP0 Z A VDD VDD sg13_lv_pmos m=1 w=3.24u l=130.00n ng=2 nrd=0 nrs=0 +.ENDS +.SUBCKT RM_IHPSG13_8192x32_c4_1P_COLCTRL2 A_ADDR_DEC<3> A_ADDR_DEC<2> A_ADDR_DEC<1> ++ A_ADDR_DEC<0> A_BIST_BM_I A_BIST_DW_I A_BIST_EN_I A_BLC<3> A_BLC<2> A_BLC<1> ++ A_BLC<0> A_BLT<3> A_BLT<2> A_BLT<1> A_BLT<0> A_BM_I A_DCLK_B_L A_DCLK_B_R ++ A_DCLK_L A_DCLK_R A_DR_O A_DW_I A_RCLK_B_L A_RCLK_B_R A_RCLK_L A_RCLK_R ++ A_TIEH_O A_WCLK_B_L A_WCLK_B_R A_WCLK_L A_WCLK_R VDD VSS +XA_DREG A_BIST_EN_I A_BIST_DW_I A_DCLK_B_L A_DW_I A_DI_R net22 VDD VSS ++ / RSC_IHPSG13_DFNQMX2IX1 +XA_BREG A_BIST_EN_I A_BIST_BM_I A_DCLK_B_L A_BM_I A_BM_R net23 VDD VSS ++ / RSC_IHPSG13_DFNQMX2IX1 +XA_CAPS<5> VDD VSS / RSC_IHPSG13_FILLCAP4 +XA_CAPS<4> VDD VSS / RSC_IHPSG13_FILLCAP4 +XA_CAPS<3> VDD VSS / RSC_IHPSG13_FILLCAP4 +XA_CAPS<2> VDD VSS / RSC_IHPSG13_FILLCAP4 +XA_CAPS<1> VDD VSS / RSC_IHPSG13_FILLCAP4 +XA_I80 A_WCLK_B_R A_RCLK_B_R net21 VDD VSS / RSC_IHPSG13_AND2X2 +XA_I75 A_DI_R A_DO_WRITE_P A_WR_ONE VDD VSS / RSC_IHPSG13_AND2X2 +XA_I76 A_DI_N A_DO_WRITE_P A_WR_ZERO VDD VSS / RSC_IHPSG13_AND2X2 +XA_I44 A_WCLK_B_R A_BM_N A_DO_WRITE_P VDD VSS / RSC_IHPSG13_NOR2X2 +XA_I81 net21 A_PRE_N VDD VSS / RSC_IHPSG13_CINVX4_WN +XA_BLTMUX<3> A_BLC<3> A_BLC_SEL A_BLT<3> A_BLT_SEL A_PRE_N A_ADDR_DEC<3> ++ A_WR_ONE A_WR_ZERO VDD VSS / RM_IHPSG13_8192x32_c4_1P_BLDRV +XA_BLTMUX<2> A_BLC<2> A_BLC_SEL A_BLT<2> A_BLT_SEL A_PRE_N A_ADDR_DEC<2> ++ A_WR_ONE A_WR_ZERO VDD VSS / RM_IHPSG13_8192x32_c4_1P_BLDRV +XA_BLTMUX<1> A_BLC<1> A_BLC_SEL A_BLT<1> A_BLT_SEL A_PRE_N A_ADDR_DEC<1> ++ A_WR_ONE A_WR_ZERO VDD VSS / RM_IHPSG13_8192x32_c4_1P_BLDRV +XA_BLTMUX<0> A_BLC<0> A_BLC_SEL A_BLT<0> A_BLT_SEL A_PRE_N A_ADDR_DEC<0> ++ A_WR_ONE A_WR_ZERO VDD VSS / RM_IHPSG13_8192x32_c4_1P_BLDRV +XA_BM_TIEH A_TIEH_O VDD VSS / RSC_IHPSG13_TIEH +XA_I89 A_DCLK_B_L A_DCLK_B_R / RSC_IHPSG13_MET3RES +XA_I88 A_DCLK_L A_DCLK_R / RSC_IHPSG13_MET3RES +XA_I87 A_WCLK_L A_WCLK_R / RSC_IHPSG13_MET3RES +XA_I91 A_RCLK_B_R A_RCLK_B_L / RSC_IHPSG13_MET3RES +XA_R2 A_RCLK_R A_RCLK_L / RSC_IHPSG13_MET3RES +XA_I90 A_WCLK_B_R A_WCLK_B_L / RSC_IHPSG13_MET3RES +XA_ISENSE A_SAE A_BLC_SEL A_BLT_SEL net19 net20 VDD VSS / ++ RSC_IHPSG13_DFPQD_MSAFFX2 +XA_I78 A_RCLK_B_R A_SAE VDD VSS / RSC_IHPSG13_CBUFX2 +XA_I83 A_BM_R A_BM_N VDD VSS / RSC_IHPSG13_INVX2 +XA_I49 A_DI_R A_DI_N VDD VSS / RSC_IHPSG13_INVX2 +XA_I51 net19 A_DR_O VDD VSS / RSC_IHPSG13_INVX4 +XA_I69 A_DCLK_L A_DCLK_B_L VDD VSS / RSC_IHPSG13_CINVX2 +XA_I50 A_WCLK_L A_WCLK_B_R VDD VSS / RSC_IHPSG13_CINVX2 +XA_EBUF A_RCLK_R A_RCLK_B_R VDD VSS / RSC_IHPSG13_CINVX2 +.ENDS +.SUBCKT RM_IHPSG13_8192x32_c4_1P_COLDRV13_FILL4 VDD VSS +XI0<9> VDD VSS / RSC_IHPSG13_FILLCAP4 +XI0<8> VDD VSS / RSC_IHPSG13_FILLCAP4 +XI0<7> VDD VSS / RSC_IHPSG13_FILLCAP4 +XI0<6> VDD VSS / RSC_IHPSG13_FILLCAP4 +XI0<5> VDD VSS / RSC_IHPSG13_FILLCAP4 +XI0<4> VDD VSS / RSC_IHPSG13_FILLCAP4 +XI0<3> VDD VSS / RSC_IHPSG13_FILLCAP4 +XI0<2> VDD VSS / RSC_IHPSG13_FILLCAP4 +XI0<1> VDD VSS / RSC_IHPSG13_FILLCAP4 +.ENDS +.SUBCKT RM_IHPSG13_8192x32_c4_1P_COLDRV13_FILL4C2 VDD VSS +XI0<2> VDD VSS / RSC_IHPSG13_FILLCAP4 +XI0<1> VDD VSS / RSC_IHPSG13_FILLCAP4 +.ENDS + + +.SUBCKT RM_IHPSG13_8192x32_c4_1P_COLDEC4 ACLK_N ADDR<3> ADDR<2> ADDR<1> ADDR<0> ++ ADDR_COL<1> ADDR_COL<0> ADDR_DEC<7> ADDR_DEC<6> ADDR_DEC<5> ADDR_DEC<4> ++ ADDR_DEC<3> ADDR_DEC<2> ADDR_DEC<1> ADDR_DEC<0> BIST_ADDR<3> BIST_ADDR<2> ++ BIST_ADDR<1> BIST_ADDR<0> BIST_EN_I VDD VSS +XI15 ADDR_COL<1> VDD VSS / RSC_IHPSG13_TIEL +XI14 addr_int ADDR_COL<0> VDD VSS / RSC_IHPSG13_CBUFX2 +XDFF<3> BIST_EN_I BIST_ADDR<3> ACLK_N ADDR<3> addr_int net7<0> VDD VSS ++ / RSC_IHPSG13_DFNQMX2IX1 +XDFF<2> BIST_EN_I BIST_ADDR<2> ACLK_N ADDR<2> padr_int<2> net7<1> VDD ++ VSS / RSC_IHPSG13_DFNQMX2IX1 +XDFF<1> BIST_EN_I BIST_ADDR<1> ACLK_N ADDR<1> padr_int<1> net7<2> VDD ++ VSS / RSC_IHPSG13_DFNQMX2IX1 +XDFF<0> BIST_EN_I BIST_ADDR<0> ACLK_N ADDR<0> padr_int<0> net7<3> VDD ++ VSS / RSC_IHPSG13_DFNQMX2IX1 +XI1<7> PADR<0> PADR<1> PADR<2> addr_n<7> VDD VSS / RSC_IHPSG13_NAND3X2 +XI1<6> NADR<0> PADR<1> PADR<2> addr_n<6> VDD VSS / RSC_IHPSG13_NAND3X2 +XI1<5> PADR<0> NADR<1> PADR<2> addr_n<5> VDD VSS / RSC_IHPSG13_NAND3X2 +XI1<4> NADR<0> NADR<1> PADR<2> addr_n<4> VDD VSS / RSC_IHPSG13_NAND3X2 +XI1<3> PADR<0> PADR<1> NADR<2> addr_n<3> VDD VSS / RSC_IHPSG13_NAND3X2 +XI1<2> NADR<0> PADR<1> NADR<2> addr_n<2> VDD VSS / RSC_IHPSG13_NAND3X2 +XI1<1> PADR<0> NADR<1> NADR<2> addr_n<1> VDD VSS / RSC_IHPSG13_NAND3X2 +XI1<0> NADR<0> NADR<1> NADR<2> addr_n<0> VDD VSS / RSC_IHPSG13_NAND3X2 +XI13<2> NADR<2> PADR<2> VDD VSS / RSC_IHPSG13_INVX2 +XI13<1> NADR<1> PADR<1> VDD VSS / RSC_IHPSG13_INVX2 +XI13<0> NADR<0> PADR<0> VDD VSS / RSC_IHPSG13_INVX2 +XI3<2> padr_int<2> NADR<2> VDD VSS / RSC_IHPSG13_INVX2 +XI3<1> padr_int<1> NADR<1> VDD VSS / RSC_IHPSG13_INVX2 +XI3<0> padr_int<0> NADR<0> VDD VSS / RSC_IHPSG13_INVX2 +XI2<7> addr_n<7> ADDR_DEC<7> VDD VSS / RSC_IHPSG13_INVX2 +XI2<6> addr_n<6> ADDR_DEC<6> VDD VSS / RSC_IHPSG13_INVX2 +XI2<5> addr_n<5> ADDR_DEC<5> VDD VSS / RSC_IHPSG13_INVX2 +XI2<4> addr_n<4> ADDR_DEC<4> VDD VSS / RSC_IHPSG13_INVX2 +XI2<3> addr_n<3> ADDR_DEC<3> VDD VSS / RSC_IHPSG13_INVX2 +XI2<2> addr_n<2> ADDR_DEC<2> VDD VSS / RSC_IHPSG13_INVX2 +XI2<1> addr_n<1> ADDR_DEC<1> VDD VSS / RSC_IHPSG13_INVX2 +XI2<0> addr_n<0> ADDR_DEC<0> VDD VSS / RSC_IHPSG13_INVX2 +XI16<3> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI16<2> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI16<1> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI17<2> VDD VSS / RSC_IHPSG13_FILLCAP4 +XI17<1> VDD VSS / RSC_IHPSG13_FILLCAP4 +.ENDS +.SUBCKT RSC_IHPSG13_AND2X4 A B Z VDD VSS +MN3 Z net6 VSS VSS sg13_lv_nmos m=1 w=1.96u l=130.00n ng=2 nrd=0 nrs=0 +MN4 net9 B VSS VSS sg13_lv_nmos m=1 w=500.0n l=130.00n ng=1 nrd=0 nrs=0 +MN6 net6 A net9 VSS sg13_lv_nmos m=1 w=500.0n l=130.00n ng=1 nrd=0 nrs=0 +MP2 Z net6 VDD VDD sg13_lv_pmos m=1 w=3.24u l=130.00n ng=2 nrd=0 nrs=0 +MP0 net6 B VDD VDD sg13_lv_pmos m=1 w=860.00n l=130.00n ng=1 nrd=0 ++ nrs=0 +MP1 net6 A VDD VDD sg13_lv_pmos m=1 w=860.00n l=130.00n ng=1 nrd=0 ++ nrs=0 +.ENDS +.SUBCKT RM_IHPSG13_8192x32_c4_1P_COLCTRL4 A_ADDR_COL A_ADDR_DEC<7> A_ADDR_DEC<6> ++ A_ADDR_DEC<5> A_ADDR_DEC<4> A_ADDR_DEC<3> A_ADDR_DEC<2> A_ADDR_DEC<1> ++ A_ADDR_DEC<0> A_BIST_BM_I A_BIST_DW_I A_BIST_EN_I A_BLC<15> A_BLC<14> ++ A_BLC<13> A_BLC<12> A_BLC<11> A_BLC<10> A_BLC<9> A_BLC<8> A_BLC<7> A_BLC<6> ++ A_BLC<5> A_BLC<4> A_BLC<3> A_BLC<2> A_BLC<1> A_BLC<0> A_BLT<15> A_BLT<14> ++ A_BLT<13> A_BLT<12> A_BLT<11> A_BLT<10> A_BLT<9> A_BLT<8> A_BLT<7> A_BLT<6> ++ A_BLT<5> A_BLT<4> A_BLT<3> A_BLT<2> A_BLT<1> A_BLT<0> A_BM_I A_DCLK_B_L ++ A_DCLK_B_R A_DCLK_L A_DCLK_R A_DR_O A_DW_I A_RCLK_B_L A_RCLK_B_R A_RCLK_L ++ A_RCLK_R A_TIEH_O A_WCLK_B_L A_WCLK_B_R A_WCLK_L A_WCLK_R VDD VSS +XA_I80 A_WCLK_B_L A_RCLK_B_L net21 VDD VSS / RSC_IHPSG13_AND2X2 +XA_I76 A_DO_WRITE_P A_DI_N A_WR_ZERO VDD VSS / RSC_IHPSG13_AND2X4 +XA_I75 A_DI_R A_DO_WRITE_P A_WR_ONE VDD VSS / RSC_IHPSG13_AND2X4 +XA_CAPS<8> VDD VSS / RSC_IHPSG13_FILLCAP4 +XA_CAPS<7> VDD VSS / RSC_IHPSG13_FILLCAP4 +XA_CAPS<6> VDD VSS / RSC_IHPSG13_FILLCAP4 +XA_CAPS<5> VDD VSS / RSC_IHPSG13_FILLCAP4 +XA_CAPS<4> VDD VSS / RSC_IHPSG13_FILLCAP4 +XA_CAPS<3> VDD VSS / RSC_IHPSG13_FILLCAP4 +XA_CAPS<2> VDD VSS / RSC_IHPSG13_FILLCAP4 +XA_CAPS<1> VDD VSS / RSC_IHPSG13_FILLCAP4 +XA_I69 A_DCLK_L A_DCLK_B_L VDD VSS / RSC_IHPSG13_CINVX4 +XA_I50 A_WCLK_L A_WCLK_B_L VDD VSS / RSC_IHPSG13_CINVX4 +XA_EBUF A_RCLK_L A_RCLK_B_L VDD VSS / RSC_IHPSG13_CINVX4 +XA_INV<1> A_N0 A_P0 VDD VSS / RSC_IHPSG13_CINVX4 +XA_INV<0> A_ADDR_COL A_N0 VDD VSS / RSC_IHPSG13_CINVX4 +XA_I81<1> net21 A_PRE_N VDD VSS / RSC_IHPSG13_CINVX4_WN +XA_I81<0> net21 A_PRE_N VDD VSS / RSC_IHPSG13_CINVX4_WN +XA_BLTMUX<15> A_BLC<15> A_BLC_SEL A_BLT<15> A_BLT_SEL A_PRE_N A_SEL_P<15> ++ A_WR_ONE A_WR_ZERO VDD VSS / RM_IHPSG13_8192x32_c4_1P_BLDRV +XA_BLTMUX<14> A_BLC<14> A_BLC_SEL A_BLT<14> A_BLT_SEL A_PRE_N A_SEL_P<14> ++ A_WR_ONE A_WR_ZERO VDD VSS / RM_IHPSG13_8192x32_c4_1P_BLDRV +XA_BLTMUX<13> A_BLC<13> A_BLC_SEL A_BLT<13> A_BLT_SEL A_PRE_N A_SEL_P<13> ++ A_WR_ONE A_WR_ZERO VDD VSS / RM_IHPSG13_8192x32_c4_1P_BLDRV +XA_BLTMUX<12> A_BLC<12> A_BLC_SEL A_BLT<12> A_BLT_SEL A_PRE_N A_SEL_P<12> ++ A_WR_ONE A_WR_ZERO VDD VSS / RM_IHPSG13_8192x32_c4_1P_BLDRV +XA_BLTMUX<11> A_BLC<11> A_BLC_SEL A_BLT<11> A_BLT_SEL A_PRE_N A_SEL_P<11> ++ A_WR_ONE A_WR_ZERO VDD VSS / RM_IHPSG13_8192x32_c4_1P_BLDRV +XA_BLTMUX<10> A_BLC<10> A_BLC_SEL A_BLT<10> A_BLT_SEL A_PRE_N A_SEL_P<10> ++ A_WR_ONE A_WR_ZERO VDD VSS / RM_IHPSG13_8192x32_c4_1P_BLDRV +XA_BLTMUX<9> A_BLC<9> A_BLC_SEL A_BLT<9> A_BLT_SEL A_PRE_N A_SEL_P<9> A_WR_ONE ++ A_WR_ZERO VDD VSS / RM_IHPSG13_8192x32_c4_1P_BLDRV +XA_BLTMUX<8> A_BLC<8> A_BLC_SEL A_BLT<8> A_BLT_SEL A_PRE_N A_SEL_P<8> A_WR_ONE ++ A_WR_ZERO VDD VSS / RM_IHPSG13_8192x32_c4_1P_BLDRV +XA_BLTMUX<7> A_BLC<7> A_BLC_SEL A_BLT<7> A_BLT_SEL A_PRE_N A_SEL_P<7> A_WR_ONE ++ A_WR_ZERO VDD VSS / RM_IHPSG13_8192x32_c4_1P_BLDRV +XA_BLTMUX<6> A_BLC<6> A_BLC_SEL A_BLT<6> A_BLT_SEL A_PRE_N A_SEL_P<6> A_WR_ONE ++ A_WR_ZERO VDD VSS / RM_IHPSG13_8192x32_c4_1P_BLDRV +XA_BLTMUX<5> A_BLC<5> A_BLC_SEL A_BLT<5> A_BLT_SEL A_PRE_N A_SEL_P<5> A_WR_ONE ++ A_WR_ZERO VDD VSS / RM_IHPSG13_8192x32_c4_1P_BLDRV +XA_BLTMUX<4> A_BLC<4> A_BLC_SEL A_BLT<4> A_BLT_SEL A_PRE_N A_SEL_P<4> A_WR_ONE ++ A_WR_ZERO VDD VSS / RM_IHPSG13_8192x32_c4_1P_BLDRV +XA_BLTMUX<3> A_BLC<3> A_BLC_SEL A_BLT<3> A_BLT_SEL A_PRE_N A_SEL_P<3> A_WR_ONE ++ A_WR_ZERO VDD VSS / RM_IHPSG13_8192x32_c4_1P_BLDRV +XA_BLTMUX<2> A_BLC<2> A_BLC_SEL A_BLT<2> A_BLT_SEL A_PRE_N A_SEL_P<2> A_WR_ONE ++ A_WR_ZERO VDD VSS / RM_IHPSG13_8192x32_c4_1P_BLDRV +XA_BLTMUX<1> A_BLC<1> A_BLC_SEL A_BLT<1> A_BLT_SEL A_PRE_N A_SEL_P<1> A_WR_ONE ++ A_WR_ZERO VDD VSS / RM_IHPSG13_8192x32_c4_1P_BLDRV +XA_BLTMUX<0> A_BLC<0> A_BLC_SEL A_BLT<0> A_BLT_SEL A_PRE_N A_SEL_P<0> A_WR_ONE ++ A_WR_ZERO VDD VSS / RM_IHPSG13_8192x32_c4_1P_BLDRV +XA_R2 A_RCLK_L A_RCLK_R / RSC_IHPSG13_MET3RES +XA_I87 A_WCLK_L A_WCLK_R / RSC_IHPSG13_MET3RES +XA_I88 A_DCLK_L A_DCLK_R / RSC_IHPSG13_MET3RES +XA_I89 A_DCLK_B_L A_DCLK_B_R / RSC_IHPSG13_MET3RES +XA_I90 A_WCLK_B_L A_WCLK_B_R / RSC_IHPSG13_MET3RES +XA_I91 A_RCLK_B_L A_RCLK_B_R / RSC_IHPSG13_MET3RES +XA_ISENSE A_SAE A_BLC_SEL A_BLT_SEL net19 net20 VDD VSS / ++ RSC_IHPSG13_DFPQD_MSAFFX2 +XA_I51 net19 A_DR_O VDD VSS / RSC_IHPSG13_INVX4 +XA_I78 A_RCLK_B_L A_SAE VDD VSS / RSC_IHPSG13_CBUFX2 +XA_DREG A_BIST_EN_I A_BIST_DW_I A_DCLK_B_L A_DW_I A_DI_R net22 VDD VSS ++ / RSC_IHPSG13_DFNQMX2IX1 +XA_BREG A_BIST_EN_I A_BIST_BM_I A_DCLK_B_L A_BM_I A_BM_R net24 VDD VSS ++ / RSC_IHPSG13_DFNQMX2IX1 +XA_DEC3INV<15> net23<0> A_SEL_P<15> VDD VSS / RSC_IHPSG13_INVX2 +XA_DEC3INV<14> net23<1> A_SEL_P<14> VDD VSS / RSC_IHPSG13_INVX2 +XA_DEC3INV<13> net23<2> A_SEL_P<13> VDD VSS / RSC_IHPSG13_INVX2 +XA_DEC3INV<12> net23<3> A_SEL_P<12> VDD VSS / RSC_IHPSG13_INVX2 +XA_DEC3INV<11> net23<4> A_SEL_P<11> VDD VSS / RSC_IHPSG13_INVX2 +XA_DEC3INV<10> net23<5> A_SEL_P<10> VDD VSS / RSC_IHPSG13_INVX2 +XA_DEC3INV<9> net23<6> A_SEL_P<9> VDD VSS / RSC_IHPSG13_INVX2 +XA_DEC3INV<8> net23<7> A_SEL_P<8> VDD VSS / RSC_IHPSG13_INVX2 +XA_DEC3INV<7> net23<8> A_SEL_P<7> VDD VSS / RSC_IHPSG13_INVX2 +XA_DEC3INV<6> net23<9> A_SEL_P<6> VDD VSS / RSC_IHPSG13_INVX2 +XA_DEC3INV<5> net23<10> A_SEL_P<5> VDD VSS / RSC_IHPSG13_INVX2 +XA_DEC3INV<4> net23<11> A_SEL_P<4> VDD VSS / RSC_IHPSG13_INVX2 +XA_DEC3INV<3> net23<12> A_SEL_P<3> VDD VSS / RSC_IHPSG13_INVX2 +XA_DEC3INV<2> net23<13> A_SEL_P<2> VDD VSS / RSC_IHPSG13_INVX2 +XA_DEC3INV<1> net23<14> A_SEL_P<1> VDD VSS / RSC_IHPSG13_INVX2 +XA_DEC3INV<0> net23<15> A_SEL_P<0> VDD VSS / RSC_IHPSG13_INVX2 +XA_I83 A_BM_R A_BM_N VDD VSS / RSC_IHPSG13_INVX2 +XA_I49 A_DI_R A_DI_N VDD VSS / RSC_IHPSG13_INVX2 +XA_I70<4> VDD VSS / RSC_IHPSG13_FILLCAP8 +XA_I70<3> VDD VSS / RSC_IHPSG13_FILLCAP8 +XA_I70<2> VDD VSS / RSC_IHPSG13_FILLCAP8 +XA_I70<1> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI73<14> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI73<13> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI73<12> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI73<11> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI73<10> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI73<9> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI73<8> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI73<7> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI73<6> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI73<5> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI73<4> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI73<3> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI73<2> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI73<1> VDD VSS / RSC_IHPSG13_FILLCAP8 +XA_I44 A_BM_N A_WCLK_B_L A_DO_WRITE_P VDD VSS / RSC_IHPSG13_NOR2X2 +XA_DEC3<15> A_P0 A_ADDR_DEC<7> net23<0> VDD VSS / RSC_IHPSG13_NAND2X2 +XA_DEC3<14> A_P0 A_ADDR_DEC<6> net23<1> VDD VSS / RSC_IHPSG13_NAND2X2 +XA_DEC3<13> A_P0 A_ADDR_DEC<5> net23<2> VDD VSS / RSC_IHPSG13_NAND2X2 +XA_DEC3<12> A_P0 A_ADDR_DEC<4> net23<3> VDD VSS / RSC_IHPSG13_NAND2X2 +XA_DEC3<11> A_P0 A_ADDR_DEC<3> net23<4> VDD VSS / RSC_IHPSG13_NAND2X2 +XA_DEC3<10> A_P0 A_ADDR_DEC<2> net23<5> VDD VSS / RSC_IHPSG13_NAND2X2 +XA_DEC3<9> A_P0 A_ADDR_DEC<1> net23<6> VDD VSS / RSC_IHPSG13_NAND2X2 +XA_DEC3<8> A_P0 A_ADDR_DEC<0> net23<7> VDD VSS / RSC_IHPSG13_NAND2X2 +XA_DEC3<7> A_N0 A_ADDR_DEC<7> net23<8> VDD VSS / RSC_IHPSG13_NAND2X2 +XA_DEC3<6> A_N0 A_ADDR_DEC<6> net23<9> VDD VSS / RSC_IHPSG13_NAND2X2 +XA_DEC3<5> A_N0 A_ADDR_DEC<5> net23<10> VDD VSS / RSC_IHPSG13_NAND2X2 +XA_DEC3<4> A_N0 A_ADDR_DEC<4> net23<11> VDD VSS / RSC_IHPSG13_NAND2X2 +XA_DEC3<3> A_N0 A_ADDR_DEC<3> net23<12> VDD VSS / RSC_IHPSG13_NAND2X2 +XA_DEC3<2> A_N0 A_ADDR_DEC<2> net23<13> VDD VSS / RSC_IHPSG13_NAND2X2 +XA_DEC3<1> A_N0 A_ADDR_DEC<1> net23<14> VDD VSS / RSC_IHPSG13_NAND2X2 +XA_DEC3<0> A_N0 A_ADDR_DEC<0> net23<15> VDD VSS / RSC_IHPSG13_NAND2X2 +XA_BM_TIEH A_TIEH_O VDD VSS / RSC_IHPSG13_TIEH +.ENDS + + +.SUBCKT RM_IHPSG13_8192x32_c4_1P_COLDEC3 ACLK_N ADDR<2> ADDR<1> ADDR<0> ADDR_COL<1> ++ ADDR_COL<0> ADDR_DEC<7> ADDR_DEC<6> ADDR_DEC<5> ADDR_DEC<4> ADDR_DEC<3> ++ ADDR_DEC<2> ADDR_DEC<1> ADDR_DEC<0> BIST_ADDR<2> BIST_ADDR<1> BIST_ADDR<0> ++ BIST_EN_I VDD VSS +XI15<1> ADDR_COL<1> VDD VSS / RSC_IHPSG13_TIEL +XI15<0> ADDR_COL<0> VDD VSS / RSC_IHPSG13_TIEL +XI1<7> PADR<0> PADR<1> PADR<2> addr_n<7> VDD VSS / RSC_IHPSG13_NAND3X2 +XI1<6> NADR<0> PADR<1> PADR<2> addr_n<6> VDD VSS / RSC_IHPSG13_NAND3X2 +XI1<5> PADR<0> NADR<1> PADR<2> addr_n<5> VDD VSS / RSC_IHPSG13_NAND3X2 +XI1<4> NADR<0> NADR<1> PADR<2> addr_n<4> VDD VSS / RSC_IHPSG13_NAND3X2 +XI1<3> PADR<0> PADR<1> NADR<2> addr_n<3> VDD VSS / RSC_IHPSG13_NAND3X2 +XI1<2> NADR<0> PADR<1> NADR<2> addr_n<2> VDD VSS / RSC_IHPSG13_NAND3X2 +XI1<1> PADR<0> NADR<1> NADR<2> addr_n<1> VDD VSS / RSC_IHPSG13_NAND3X2 +XI1<0> NADR<0> NADR<1> NADR<2> addr_n<0> VDD VSS / RSC_IHPSG13_NAND3X2 +XDFF<2> BIST_EN_I BIST_ADDR<2> ACLK_N ADDR<2> padr_int<2> net6<0> VDD ++ VSS / RSC_IHPSG13_DFNQMX2IX1 +XDFF<1> BIST_EN_I BIST_ADDR<1> ACLK_N ADDR<1> padr_int<1> net6<1> VDD ++ VSS / RSC_IHPSG13_DFNQMX2IX1 +XDFF<0> BIST_EN_I BIST_ADDR<0> ACLK_N ADDR<0> padr_int<0> net6<2> VDD ++ VSS / RSC_IHPSG13_DFNQMX2IX1 +XI17<2> VDD VSS / RSC_IHPSG13_FILLCAP4 +XI17<1> VDD VSS / RSC_IHPSG13_FILLCAP4 +XI13<2> NADR<2> PADR<2> VDD VSS / RSC_IHPSG13_INVX2 +XI13<1> NADR<1> PADR<1> VDD VSS / RSC_IHPSG13_INVX2 +XI13<0> NADR<0> PADR<0> VDD VSS / RSC_IHPSG13_INVX2 +XI3<2> padr_int<2> NADR<2> VDD VSS / RSC_IHPSG13_INVX2 +XI3<1> padr_int<1> NADR<1> VDD VSS / RSC_IHPSG13_INVX2 +XI3<0> padr_int<0> NADR<0> VDD VSS / RSC_IHPSG13_INVX2 +XI2<7> addr_n<7> ADDR_DEC<7> VDD VSS / RSC_IHPSG13_INVX2 +XI2<6> addr_n<6> ADDR_DEC<6> VDD VSS / RSC_IHPSG13_INVX2 +XI2<5> addr_n<5> ADDR_DEC<5> VDD VSS / RSC_IHPSG13_INVX2 +XI2<4> addr_n<4> ADDR_DEC<4> VDD VSS / RSC_IHPSG13_INVX2 +XI2<3> addr_n<3> ADDR_DEC<3> VDD VSS / RSC_IHPSG13_INVX2 +XI2<2> addr_n<2> ADDR_DEC<2> VDD VSS / RSC_IHPSG13_INVX2 +XI2<1> addr_n<1> ADDR_DEC<1> VDD VSS / RSC_IHPSG13_INVX2 +XI2<0> addr_n<0> ADDR_DEC<0> VDD VSS / RSC_IHPSG13_INVX2 +XI16<6> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI16<5> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI16<4> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI16<3> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI16<2> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI16<1> VDD VSS / RSC_IHPSG13_FILLCAP8 +.ENDS +.SUBCKT RM_IHPSG13_8192x32_c4_1P_COLCTRL3 A_ADDR_DEC<7> A_ADDR_DEC<6> A_ADDR_DEC<5> ++ A_ADDR_DEC<4> A_ADDR_DEC<3> A_ADDR_DEC<2> A_ADDR_DEC<1> A_ADDR_DEC<0> ++ A_BIST_BM_I A_BIST_DW_I A_BIST_EN_I A_BLC<7> A_BLC<6> A_BLC<5> A_BLC<4> ++ A_BLC<3> A_BLC<2> A_BLC<1> A_BLC<0> A_BLT<7> A_BLT<6> A_BLT<5> A_BLT<4> ++ A_BLT<3> A_BLT<2> A_BLT<1> A_BLT<0> A_BM_I A_DCLK_B_L A_DCLK_B_R A_DCLK_L ++ A_DCLK_R A_DR_O A_DW_I A_RCLK_B_L A_RCLK_B_R A_RCLK_L A_RCLK_R A_TIEH_O ++ A_WCLK_B_L A_WCLK_B_R A_WCLK_L A_WCLK_R VDD VSS +XA_DREG A_BIST_EN_I A_BIST_DW_I A_DCLK_B_L A_DW_I A_DI_R net22 VDD VSS ++ / RSC_IHPSG13_DFNQMX2IX1 +XA_BREG A_BIST_EN_I A_BIST_BM_I A_DCLK_B_R A_BM_I A_BM_R net23 VDD VSS ++ / RSC_IHPSG13_DFNQMX2IX1 +XA_I70<8> VDD VSS / RSC_IHPSG13_FILLCAP8 +XA_I70<7> VDD VSS / RSC_IHPSG13_FILLCAP8 +XA_I70<6> VDD VSS / RSC_IHPSG13_FILLCAP8 +XA_I70<5> VDD VSS / RSC_IHPSG13_FILLCAP8 +XA_I70<4> VDD VSS / RSC_IHPSG13_FILLCAP8 +XA_I70<3> VDD VSS / RSC_IHPSG13_FILLCAP8 +XA_I70<2> VDD VSS / RSC_IHPSG13_FILLCAP8 +XA_I70<1> VDD VSS / RSC_IHPSG13_FILLCAP8 +XA_I51 net19 A_DR_O VDD VSS / RSC_IHPSG13_INVX4 +XA_I44 A_BM_N A_WCLK_B_R A_DO_WRITE_P VDD VSS / RSC_IHPSG13_NOR2X2 +XA_BM_TIEH A_TIEH_O VDD VSS / RSC_IHPSG13_TIEH +XA_BLTMUX<7> A_BLC<7> A_BLC_SEL A_BLT<7> A_BLT_SEL A_PRE_N A_ADDR_DEC<7> ++ A_WR_ONE A_WR_ZERO VDD VSS / RM_IHPSG13_8192x32_c4_1P_BLDRV +XA_BLTMUX<6> A_BLC<6> A_BLC_SEL A_BLT<6> A_BLT_SEL A_PRE_N A_ADDR_DEC<6> ++ A_WR_ONE A_WR_ZERO VDD VSS / RM_IHPSG13_8192x32_c4_1P_BLDRV +XA_BLTMUX<5> A_BLC<5> A_BLC_SEL A_BLT<5> A_BLT_SEL A_PRE_N A_ADDR_DEC<5> ++ A_WR_ONE A_WR_ZERO VDD VSS / RM_IHPSG13_8192x32_c4_1P_BLDRV +XA_BLTMUX<4> A_BLC<4> A_BLC_SEL A_BLT<4> A_BLT_SEL A_PRE_N A_ADDR_DEC<4> ++ A_WR_ONE A_WR_ZERO VDD VSS / RM_IHPSG13_8192x32_c4_1P_BLDRV +XA_BLTMUX<3> A_BLC<3> A_BLC_SEL A_BLT<3> A_BLT_SEL A_PRE_N A_ADDR_DEC<3> ++ A_WR_ONE A_WR_ZERO VDD VSS / RM_IHPSG13_8192x32_c4_1P_BLDRV +XA_BLTMUX<2> A_BLC<2> A_BLC_SEL A_BLT<2> A_BLT_SEL A_PRE_N A_ADDR_DEC<2> ++ A_WR_ONE A_WR_ZERO VDD VSS / RM_IHPSG13_8192x32_c4_1P_BLDRV +XA_BLTMUX<1> A_BLC<1> A_BLC_SEL A_BLT<1> A_BLT_SEL A_PRE_N A_ADDR_DEC<1> ++ A_WR_ONE A_WR_ZERO VDD VSS / RM_IHPSG13_8192x32_c4_1P_BLDRV +XA_BLTMUX<0> A_BLC<0> A_BLC_SEL A_BLT<0> A_BLT_SEL A_PRE_N A_ADDR_DEC<0> ++ A_WR_ONE A_WR_ZERO VDD VSS / RM_IHPSG13_8192x32_c4_1P_BLDRV +XA_I49 A_DI_R A_DI_N VDD VSS / RSC_IHPSG13_INVX2 +XA_I83 A_BM_R A_BM_N VDD VSS / RSC_IHPSG13_INVX2 +XA_I69 A_DCLK_L A_DCLK_B_L VDD VSS / RSC_IHPSG13_CINVX2 +XA_I50 A_WCLK_L A_WCLK_B_L VDD VSS / RSC_IHPSG13_CINVX2 +XA_EBUF A_RCLK_L A_RCLK_B_L VDD VSS / RSC_IHPSG13_CINVX2 +XA_I78 A_RCLK_B_L A_SAE VDD VSS / RSC_IHPSG13_CBUFX2 +XA_I88 A_DCLK_L A_DCLK_R / RSC_IHPSG13_MET3RES +XA_I87 A_WCLK_L A_WCLK_R / RSC_IHPSG13_MET3RES +XA_R2 A_RCLK_L A_RCLK_R / RSC_IHPSG13_MET3RES +XA_I91 A_RCLK_B_L A_RCLK_B_R / RSC_IHPSG13_MET3RES +XA_I90 A_WCLK_B_L A_WCLK_B_R / RSC_IHPSG13_MET3RES +XA_I89 A_DCLK_B_L A_DCLK_B_R / RSC_IHPSG13_MET3RES +XA_I80 A_WCLK_B_R A_RCLK_B_R net21 VDD VSS / RSC_IHPSG13_AND2X2 +XA_I76 A_DI_N A_DO_WRITE_P A_WR_ZERO VDD VSS / RSC_IHPSG13_AND2X2 +XA_I75 A_DI_R A_DO_WRITE_P A_WR_ONE VDD VSS / RSC_IHPSG13_AND2X2 +XA_ISENSE A_SAE A_BLC_SEL A_BLT_SEL net19 net20 VDD VSS / ++ RSC_IHPSG13_DFPQD_MSAFFX2 +XA_I81 net21 A_PRE_N VDD VSS / RSC_IHPSG13_CINVX4_WN +XA_CAPS<5> VDD VSS / RSC_IHPSG13_FILLCAP4 +XA_CAPS<4> VDD VSS / RSC_IHPSG13_FILLCAP4 +XA_CAPS<3> VDD VSS / RSC_IHPSG13_FILLCAP4 +XA_CAPS<2> VDD VSS / RSC_IHPSG13_FILLCAP4 +XA_CAPS<1> VDD VSS / RSC_IHPSG13_FILLCAP4 +.ENDS + +.SUBCKT RM_IHPSG13_8192x32_c4_2P_BITKIT_16x2_CORNER VDD_CORE VSS +XI16 VDD_CORE VSS VDD_CORE VSS / ++ RM_IHPSG13_8192x32_c4_1P_BITKIT_CORNER +.ENDS +.SUBCKT RM_IHPSG13_8192x32_c4_2P_BITKIT_EDGE_LR A_WL B_WL NW PW VDD VSS +MN1 VSS A_WL VSS VSS sg13_lv_nmos m=1 w=300.0n l=130.00n ng=1 nrd=0 nrs=0 +MN0 VSS B_WL VSS VSS sg13_lv_nmos m=1 w=300.0n l=130.00n ng=1 nrd=0 nrs=0 +.ENDS +.SUBCKT RM_IHPSG13_8192x32_c4_2P_BITKIT_16x2_EDGE_LR A_WL<15> A_WL<14> A_WL<13> A_WL<12> ++ A_WL<11> A_WL<10> A_WL<9> A_WL<8> A_WL<7> A_WL<6> A_WL<5> A_WL<4> A_WL<3> ++ A_WL<2> A_WL<1> A_WL<0> B_WL<15> B_WL<14> B_WL<13> B_WL<12> B_WL<11> ++ B_WL<10> B_WL<9> B_WL<8> B_WL<7> B_WL<6> B_WL<5> B_WL<4> B_WL<3> B_WL<2> ++ B_WL<1> B_WL<0> VDD_CORE VSS +XI0<15> A_WL<15> B_WL<15> VDD_CORE VSS VDD_CORE VSS ++ / RM_IHPSG13_8192x32_c4_2P_BITKIT_EDGE_LR +XI0<14> A_WL<14> B_WL<14> VDD_CORE VSS VDD_CORE VSS ++ / RM_IHPSG13_8192x32_c4_2P_BITKIT_EDGE_LR +XI0<13> A_WL<13> B_WL<13> VDD_CORE VSS VDD_CORE VSS ++ / RM_IHPSG13_8192x32_c4_2P_BITKIT_EDGE_LR +XI0<12> A_WL<12> B_WL<12> VDD_CORE VSS VDD_CORE VSS ++ / RM_IHPSG13_8192x32_c4_2P_BITKIT_EDGE_LR +XI0<11> A_WL<11> B_WL<11> VDD_CORE VSS VDD_CORE VSS ++ / RM_IHPSG13_8192x32_c4_2P_BITKIT_EDGE_LR +XI0<10> A_WL<10> B_WL<10> VDD_CORE VSS VDD_CORE VSS ++ / RM_IHPSG13_8192x32_c4_2P_BITKIT_EDGE_LR +XI0<9> A_WL<9> B_WL<9> VDD_CORE VSS VDD_CORE VSS / ++ RM_IHPSG13_8192x32_c4_2P_BITKIT_EDGE_LR +XI0<8> A_WL<8> B_WL<8> VDD_CORE VSS VDD_CORE VSS / ++ RM_IHPSG13_8192x32_c4_2P_BITKIT_EDGE_LR +XI0<7> A_WL<7> B_WL<7> VDD_CORE VSS VDD_CORE VSS / ++ RM_IHPSG13_8192x32_c4_2P_BITKIT_EDGE_LR +XI0<6> A_WL<6> B_WL<6> VDD_CORE VSS VDD_CORE VSS / ++ RM_IHPSG13_8192x32_c4_2P_BITKIT_EDGE_LR +XI0<5> A_WL<5> B_WL<5> VDD_CORE VSS VDD_CORE VSS / ++ RM_IHPSG13_8192x32_c4_2P_BITKIT_EDGE_LR +XI0<4> A_WL<4> B_WL<4> VDD_CORE VSS VDD_CORE VSS / ++ RM_IHPSG13_8192x32_c4_2P_BITKIT_EDGE_LR +XI0<3> A_WL<3> B_WL<3> VDD_CORE VSS VDD_CORE VSS / ++ RM_IHPSG13_8192x32_c4_2P_BITKIT_EDGE_LR +XI0<2> A_WL<2> B_WL<2> VDD_CORE VSS VDD_CORE VSS / ++ RM_IHPSG13_8192x32_c4_2P_BITKIT_EDGE_LR +XI0<1> A_WL<1> B_WL<1> VDD_CORE VSS VDD_CORE VSS / ++ RM_IHPSG13_8192x32_c4_2P_BITKIT_EDGE_LR +XI0<0> A_WL<0> B_WL<0> VDD_CORE VSS VDD_CORE VSS / ++ RM_IHPSG13_8192x32_c4_2P_BITKIT_EDGE_LR +.ENDS +.SUBCKT RM_IHPSG13_8192x32_c4_2P_BITKIT_CELL A_BLC_BOT A_BLC_TOP A_BLT_BOT A_BLT_TOP ++ A_LWL A_RWL B_BLC_BOT B_BLC_TOP B_BLT_BOT B_BLT_TOP B_LWL B_RWL NW PW VDD VSS +MN5 NC B_RWL B_BLC_BOT PW sg13_lv_nmos m=1 w=300.0n l=130.00n ng=1 nrd=0 nrs=0 +MN4 B_BLT_BOT B_LWL NT PW sg13_lv_nmos m=1 w=300.0n l=130.00n ng=1 nrd=0 nrs=0 +MN0 NC NT VSS PW sg13_lv_nmos m=1 w=600.0n l=130.00n ng=2 nrd=0 nrs=0 +MN1 NT NC VSS PW sg13_lv_nmos m=1 w=600.0n l=130.00n ng=2 nrd=0 nrs=0 +MN3 NC A_RWL A_BLC_TOP PW sg13_lv_nmos m=1 w=300.0n l=130.00n ng=1 nrd=0 nrs=0 +MN2 A_BLT_TOP A_LWL NT PW sg13_lv_nmos m=1 w=300.0n l=130.00n ng=1 nrd=0 nrs=0 +MP1 NT NC VDD NW sg13_lv_pmos m=1 w=150.00n l=130.00n ng=1 nrd=0 nrs=0 +MP0 NC NT VDD NW sg13_lv_pmos m=1 w=150.00n l=130.00n ng=1 nrd=0 nrs=0 +R5 B_RWL B_LWL lvsres w=2.6e-07 l=6e-07 +R4 B_BLC_BOT B_BLC_TOP lvsres w=2.6e-07 l=6e-07 +R3 B_BLT_BOT B_BLT_TOP lvsres w=2.6e-07 l=6e-07 +R1 A_BLC_BOT A_BLC_TOP lvsres w=2.6e-07 l=6e-07 +R0 A_BLT_BOT A_BLT_TOP lvsres w=2.6e-07 l=6e-07 +R2 A_RWL A_LWL lvsres w=2.6e-07 l=6e-07 +.ENDS +.SUBCKT RM_IHPSG13_8192x32_c4_2P_BITKIT_16x2_SRAM A_BLC_BOT<1> A_BLC_BOT<0> A_BLC_TOP<1> ++ A_BLC_TOP<0> A_BLT_BOT<1> A_BLT_BOT<0> A_BLT_TOP<1> A_BLT_TOP<0> A_LWL<15> ++ A_LWL<14> A_LWL<13> A_LWL<12> A_LWL<11> A_LWL<10> A_LWL<9> A_LWL<8> A_LWL<7> ++ A_LWL<6> A_LWL<5> A_LWL<4> A_LWL<3> A_LWL<2> A_LWL<1> A_LWL<0> A_RWL<15> ++ A_RWL<14> A_RWL<13> A_RWL<12> A_RWL<11> A_RWL<10> A_RWL<9> A_RWL<8> A_RWL<7> ++ A_RWL<6> A_RWL<5> A_RWL<4> A_RWL<3> A_RWL<2> A_RWL<1> A_RWL<0> B_BLC_BOT<1> ++ B_BLC_BOT<0> B_BLC_TOP<1> B_BLC_TOP<0> B_BLT_BOT<1> B_BLT_BOT<0> ++ B_BLT_TOP<1> B_BLT_TOP<0> B_LWL<15> B_LWL<14> B_LWL<13> B_LWL<12> B_LWL<11> ++ B_LWL<10> B_LWL<9> B_LWL<8> B_LWL<7> B_LWL<6> B_LWL<5> B_LWL<4> B_LWL<3> ++ B_LWL<2> B_LWL<1> B_LWL<0> B_RWL<15> B_RWL<14> B_RWL<13> B_RWL<12> B_RWL<11> ++ B_RWL<10> B_RWL<9> B_RWL<8> B_RWL<7> B_RWL<6> B_RWL<5> B_RWL<4> B_RWL<3> ++ B_RWL<2> B_RWL<1> B_RWL<0> VDD_CORE VSS +XCELL<31> A_BLC_TOP<1> A_RBLC<15> A_BLT_TOP<1> A_RBLT<15> A_XWL<15> A_RWL<15> ++ B_BLC_TOP<1> B_RBLC<15> B_BLT_TOP<1> B_RBLT<15> B_XWL<15> B_RWL<15> ++ VDD_CORE VSS VDD_CORE VSS / ++ RM_IHPSG13_8192x32_c4_2P_BITKIT_CELL +XCELL<30> A_RBLC<14> A_RBLC<15> A_RBLT<14> A_RBLT<15> A_XWL<14> A_RWL<14> ++ B_RBLC<14> B_RBLC<15> B_RBLT<14> B_RBLT<15> B_XWL<14> B_RWL<14> VDD_CORE ++ VSS VDD_CORE VSS / RM_IHPSG13_8192x32_c4_2P_BITKIT_CELL +XCELL<29> A_RBLC<14> A_RBLC<13> A_RBLT<14> A_RBLT<13> A_XWL<13> A_RWL<13> ++ B_RBLC<14> B_RBLC<13> B_RBLT<14> B_RBLT<13> B_XWL<13> B_RWL<13> VDD_CORE ++ VSS VDD_CORE VSS / RM_IHPSG13_8192x32_c4_2P_BITKIT_CELL +XCELL<28> A_RBLC<12> A_RBLC<13> A_RBLT<12> A_RBLT<13> A_XWL<12> A_RWL<12> ++ B_RBLC<12> B_RBLC<13> B_RBLT<12> B_RBLT<13> B_XWL<12> B_RWL<12> VDD_CORE ++ VSS VDD_CORE VSS / RM_IHPSG13_8192x32_c4_2P_BITKIT_CELL +XCELL<27> A_RBLC<12> A_RBLC<11> A_RBLT<12> A_RBLT<11> A_XWL<11> A_RWL<11> ++ B_RBLC<12> B_RBLC<11> B_RBLT<12> B_RBLT<11> B_XWL<11> B_RWL<11> VDD_CORE ++ VSS VDD_CORE VSS / RM_IHPSG13_8192x32_c4_2P_BITKIT_CELL +XCELL<26> A_RBLC<10> A_RBLC<11> A_RBLT<10> A_RBLT<11> A_XWL<10> A_RWL<10> ++ B_RBLC<10> B_RBLC<11> B_RBLT<10> B_RBLT<11> B_XWL<10> B_RWL<10> VDD_CORE ++ VSS VDD_CORE VSS / RM_IHPSG13_8192x32_c4_2P_BITKIT_CELL +XCELL<25> A_RBLC<10> A_RBLC<9> A_RBLT<10> A_RBLT<9> A_XWL<9> A_RWL<9> ++ B_RBLC<10> B_RBLC<9> B_RBLT<10> B_RBLT<9> B_XWL<9> B_RWL<9> VDD_CORE ++ VSS VDD_CORE VSS / RM_IHPSG13_8192x32_c4_2P_BITKIT_CELL +XCELL<24> A_RBLC<8> A_RBLC<9> A_RBLT<8> A_RBLT<9> A_XWL<8> A_RWL<8> B_RBLC<8> ++ B_RBLC<9> B_RBLT<8> B_RBLT<9> B_XWL<8> B_RWL<8> VDD_CORE VSS ++ VDD_CORE VSS / RM_IHPSG13_8192x32_c4_2P_BITKIT_CELL +XCELL<23> A_RBLC<8> A_RBLC<7> A_RBLT<8> A_RBLT<7> A_XWL<7> A_RWL<7> B_RBLC<8> ++ B_RBLC<7> B_RBLT<8> B_RBLT<7> B_XWL<7> B_RWL<7> VDD_CORE VSS ++ VDD_CORE VSS / RM_IHPSG13_8192x32_c4_2P_BITKIT_CELL +XCELL<22> A_RBLC<6> A_RBLC<7> A_RBLT<6> A_RBLT<7> A_XWL<6> A_RWL<6> B_RBLC<6> ++ B_RBLC<7> B_RBLT<6> B_RBLT<7> B_XWL<6> B_RWL<6> VDD_CORE VSS ++ VDD_CORE VSS / RM_IHPSG13_8192x32_c4_2P_BITKIT_CELL +XCELL<21> A_RBLC<6> A_RBLC<5> A_RBLT<6> A_RBLT<5> A_XWL<5> A_RWL<5> B_RBLC<6> ++ B_RBLC<5> B_RBLT<6> B_RBLT<5> B_XWL<5> B_RWL<5> VDD_CORE VSS ++ VDD_CORE VSS / RM_IHPSG13_8192x32_c4_2P_BITKIT_CELL +XCELL<20> A_RBLC<4> A_RBLC<5> A_RBLT<4> A_RBLT<5> A_XWL<4> A_RWL<4> B_RBLC<4> ++ B_RBLC<5> B_RBLT<4> B_RBLT<5> B_XWL<4> B_RWL<4> VDD_CORE VSS ++ VDD_CORE VSS / RM_IHPSG13_8192x32_c4_2P_BITKIT_CELL +XCELL<19> A_RBLC<4> A_RBLC<3> A_RBLT<4> A_RBLT<3> A_XWL<3> A_RWL<3> B_RBLC<4> ++ B_RBLC<3> B_RBLT<4> B_RBLT<3> B_XWL<3> B_RWL<3> VDD_CORE VSS ++ VDD_CORE VSS / RM_IHPSG13_8192x32_c4_2P_BITKIT_CELL +XCELL<18> A_RBLC<2> A_RBLC<3> A_RBLT<2> A_RBLT<3> A_XWL<2> A_RWL<2> B_RBLC<2> ++ B_RBLC<3> B_RBLT<2> B_RBLT<3> B_XWL<2> B_RWL<2> VDD_CORE VSS ++ VDD_CORE VSS / RM_IHPSG13_8192x32_c4_2P_BITKIT_CELL +XCELL<17> A_RBLC<2> A_RBLC<1> A_RBLT<2> A_RBLT<1> A_XWL<1> A_RWL<1> B_RBLC<2> ++ B_RBLC<1> B_RBLT<2> B_RBLT<1> B_XWL<1> B_RWL<1> VDD_CORE VSS ++ VDD_CORE VSS / RM_IHPSG13_8192x32_c4_2P_BITKIT_CELL +XCELL<16> A_BLC_BOT<1> A_RBLC<1> A_BLT_BOT<1> A_RBLT<1> A_XWL<0> A_RWL<0> ++ B_BLC_BOT<1> B_RBLC<1> B_BLT_BOT<1> B_RBLT<1> B_XWL<0> B_RWL<0> VDD_CORE ++ VSS VDD_CORE VSS / RM_IHPSG13_8192x32_c4_2P_BITKIT_CELL +XCELL<15> A_BLC_TOP<0> A_LBLC<15> A_BLT_TOP<0> A_LBLT<15> A_LWL<15> A_XWL<15> ++ B_BLC_TOP<0> B_LBLC<15> B_BLT_TOP<0> B_LBLT<15> B_LWL<15> B_XWL<15> ++ VDD_CORE VSS VDD_CORE VSS / ++ RM_IHPSG13_8192x32_c4_2P_BITKIT_CELL +XCELL<14> A_LBLC<14> A_LBLC<15> A_LBLT<14> A_LBLT<15> A_LWL<14> A_XWL<14> ++ B_LBLC<14> B_LBLC<15> B_LBLT<14> B_LBLT<15> B_LWL<14> B_XWL<14> VDD_CORE ++ VSS VDD_CORE VSS / RM_IHPSG13_8192x32_c4_2P_BITKIT_CELL +XCELL<13> A_LBLC<14> A_LBLC<13> A_LBLT<14> A_LBLT<13> A_LWL<13> A_XWL<13> ++ B_LBLC<14> B_LBLC<13> B_LBLT<14> B_LBLT<13> B_LWL<13> B_XWL<13> VDD_CORE ++ VSS VDD_CORE VSS / RM_IHPSG13_8192x32_c4_2P_BITKIT_CELL +XCELL<12> A_LBLC<12> A_LBLC<13> A_LBLT<12> A_LBLT<13> A_LWL<12> A_XWL<12> ++ B_LBLC<12> B_LBLC<13> B_LBLT<12> B_LBLT<13> B_LWL<12> B_XWL<12> VDD_CORE ++ VSS VDD_CORE VSS / RM_IHPSG13_8192x32_c4_2P_BITKIT_CELL +XCELL<11> A_LBLC<12> A_LBLC<11> A_LBLT<12> A_LBLT<11> A_LWL<11> A_XWL<11> ++ B_LBLC<12> B_LBLC<11> B_LBLT<12> B_LBLT<11> B_LWL<11> B_XWL<11> VDD_CORE ++ VSS VDD_CORE VSS / RM_IHPSG13_8192x32_c4_2P_BITKIT_CELL +XCELL<10> A_LBLC<10> A_LBLC<11> A_LBLT<10> A_LBLT<11> A_LWL<10> A_XWL<10> ++ B_LBLC<10> B_LBLC<11> B_LBLT<10> B_LBLT<11> B_LWL<10> B_XWL<10> VDD_CORE ++ VSS VDD_CORE VSS / RM_IHPSG13_8192x32_c4_2P_BITKIT_CELL +XCELL<9> A_LBLC<10> A_LBLC<9> A_LBLT<10> A_LBLT<9> A_LWL<9> A_XWL<9> ++ B_LBLC<10> B_LBLC<9> B_LBLT<10> B_LBLT<9> B_LWL<9> B_XWL<9> VDD_CORE ++ VSS VDD_CORE VSS / RM_IHPSG13_8192x32_c4_2P_BITKIT_CELL +XCELL<8> A_LBLC<8> A_LBLC<9> A_LBLT<8> A_LBLT<9> A_LWL<8> A_XWL<8> B_LBLC<8> ++ B_LBLC<9> B_LBLT<8> B_LBLT<9> B_LWL<8> B_XWL<8> VDD_CORE VSS ++ VDD_CORE VSS / RM_IHPSG13_8192x32_c4_2P_BITKIT_CELL +XCELL<7> A_LBLC<8> A_LBLC<7> A_LBLT<8> A_LBLT<7> A_LWL<7> A_XWL<7> B_LBLC<8> ++ B_LBLC<7> B_LBLT<8> B_LBLT<7> B_LWL<7> B_XWL<7> VDD_CORE VSS ++ VDD_CORE VSS / RM_IHPSG13_8192x32_c4_2P_BITKIT_CELL +XCELL<6> A_LBLC<6> A_LBLC<7> A_LBLT<6> A_LBLT<7> A_LWL<6> A_XWL<6> B_LBLC<6> ++ B_LBLC<7> B_LBLT<6> B_LBLT<7> B_LWL<6> B_XWL<6> VDD_CORE VSS ++ VDD_CORE VSS / RM_IHPSG13_8192x32_c4_2P_BITKIT_CELL +XCELL<5> A_LBLC<6> A_LBLC<5> A_LBLT<6> A_LBLT<5> A_LWL<5> A_XWL<5> B_LBLC<6> ++ B_LBLC<5> B_LBLT<6> B_LBLT<5> B_LWL<5> B_XWL<5> VDD_CORE VSS ++ VDD_CORE VSS / RM_IHPSG13_8192x32_c4_2P_BITKIT_CELL +XCELL<4> A_LBLC<4> A_LBLC<5> A_LBLT<4> A_LBLT<5> A_LWL<4> A_XWL<4> B_LBLC<4> ++ B_LBLC<5> B_LBLT<4> B_LBLT<5> B_LWL<4> B_XWL<4> VDD_CORE VSS ++ VDD_CORE VSS / RM_IHPSG13_8192x32_c4_2P_BITKIT_CELL +XCELL<3> A_LBLC<4> A_LBLC<3> A_LBLT<4> A_LBLT<3> A_LWL<3> A_XWL<3> B_LBLC<4> ++ B_LBLC<3> B_LBLT<4> B_LBLT<3> B_LWL<3> B_XWL<3> VDD_CORE VSS ++ VDD_CORE VSS / RM_IHPSG13_8192x32_c4_2P_BITKIT_CELL +XCELL<2> A_LBLC<2> A_LBLC<3> A_LBLT<2> A_LBLT<3> A_LWL<2> A_XWL<2> B_LBLC<2> ++ B_LBLC<3> B_LBLT<2> B_LBLT<3> B_LWL<2> B_XWL<2> VDD_CORE VSS ++ VDD_CORE VSS / RM_IHPSG13_8192x32_c4_2P_BITKIT_CELL +XCELL<1> A_LBLC<2> A_LBLC<1> A_LBLT<2> A_LBLT<1> A_LWL<1> A_XWL<1> B_LBLC<2> ++ B_LBLC<1> B_LBLT<2> B_LBLT<1> B_LWL<1> B_XWL<1> VDD_CORE VSS ++ VDD_CORE VSS / RM_IHPSG13_8192x32_c4_2P_BITKIT_CELL +XCELL<0> A_BLC_BOT<0> A_LBLC<1> A_BLT_BOT<0> A_LBLT<1> A_LWL<0> A_XWL<0> ++ B_BLC_BOT<0> B_LBLC<1> B_BLT_BOT<0> B_LBLT<1> B_LWL<0> B_XWL<0> VDD_CORE ++ VSS VDD_CORE VSS / RM_IHPSG13_8192x32_c4_2P_BITKIT_CELL +.ENDS +.SUBCKT RM_IHPSG13_8192x32_c4_2P_BITKIT_EDGE_TB A_BLC A_BLT B_BLC B_BLT NW PW VDD VSS +.ENDS +.SUBCKT RM_IHPSG13_8192x32_c4_2P_BITKIT_16x2_EDGE_TB A_BLC<1> A_BLC<0> A_BLT<1> A_BLT<0> ++ B_BLC<1> B_BLC<0> B_BLT<1> B_BLT<0> VDD_CORE VSS +XEDGE<1> A_BLC<1> A_BLT<1> B_BLC<1> B_BLT<1> VDD_CORE VSS ++ VDD_CORE VSS / RM_IHPSG13_8192x32_c4_2P_BITKIT_EDGE_TB +XEDGE<0> A_BLC<0> A_BLT<0> B_BLC<0> B_BLT<0> VDD_CORE VSS ++ VDD_CORE VSS / RM_IHPSG13_8192x32_c4_2P_BITKIT_EDGE_TB +.ENDS +.SUBCKT RM_IHPSG13_8192x32_c4_2P_BITKIT_TAP A_BLC A_BLT B_BLC B_BLT NW PW VDD VSS +.ENDS +.SUBCKT RM_IHPSG13_8192x32_c4_2P_BITKIT_16x2_TAP A_BLC<1> A_BLC<0> A_BLT<1> A_BLT<0> ++ B_BLC<1> B_BLC<0> B_BLT<1> B_BLT<0> VDD_CORE VSS +XIEDGEBP_COL1<1> A_BLC<1> A_BLT<1> B_BLC<1> B_BLT<1> VDD_CORE VSS ++ VDD_CORE VSS / RM_IHPSG13_8192x32_c4_2P_BITKIT_EDGE_TB +XIEDGEBP_COL1<0> A_BLC<1> A_BLT<1> B_BLC<1> B_BLT<1> VDD_CORE VSS ++ VDD_CORE VSS / RM_IHPSG13_8192x32_c4_2P_BITKIT_EDGE_TB +XIEDGEBP_COL2<1> A_BLC<0> A_BLT<0> B_BLC<0> B_BLT<0> VDD_CORE VSS ++ VDD_CORE VSS / RM_IHPSG13_8192x32_c4_2P_BITKIT_EDGE_TB +XIEDGEBP_COL2<0> A_BLC<0> A_BLT<0> B_BLC<0> B_BLT<0> VDD_CORE VSS ++ VDD_CORE VSS / RM_IHPSG13_8192x32_c4_2P_BITKIT_EDGE_TB +XITAP<1> A_BLC<1> A_BLT<1> B_BLC<1> B_BLT<1> VDD_CORE VSS ++ VDD_CORE VSS / RM_IHPSG13_8192x32_c4_2P_BITKIT_TAP +XITAP<0> A_BLC<0> A_BLT<0> B_BLC<0> B_BLT<0> VDD_CORE VSS ++ VDD_CORE VSS / RM_IHPSG13_8192x32_c4_2P_BITKIT_TAP +.ENDS + + +.SUBCKT RM_IHPSG13_8192x32_c4_1P_BITKIT_TAP_LR NW PW VDD VSS +.ENDS +.SUBCKT RM_IHPSG13_8192x32_c4_2P_BITKIT_16x2_TAP_LR VDD_CORE VSS +XCORNER<1> VDD_CORE VSS VDD_CORE VSS / ++ RM_IHPSG13_8192x32_c4_1P_BITKIT_CORNER +XCORNER<0> VDD_CORE VSS VDD_CORE VSS / ++ RM_IHPSG13_8192x32_c4_1P_BITKIT_CORNER +XTAP_BORDER VDD_CORE VSS VDD_CORE VSS / ++ RM_IHPSG13_8192x32_c4_1P_BITKIT_TAP_LR +.ENDS + +.SUBCKT RSC_IHPSG13_CBUFX12 A Z VDD VSS +MN1 Z net6 VSS VSS sg13_lv_nmos m=1 w=4.23u l=130.00n ng=6 nrd=0 nrs=0 +MN0 net6 A VSS VSS sg13_lv_nmos m=1 w=1.41u l=130.00n ng=2 nrd=0 nrs=0 +MP1 Z net6 VDD VDD sg13_lv_pmos m=1 w=9.72u l=130.00n ng=6 nrd=0 nrs=0 +MP0 net6 A VDD VDD sg13_lv_pmos m=1 w=3.24u l=130.00n ng=2 nrd=0 nrs=0 +.ENDS +.SUBCKT RM_IHPSG13_8192x32_c4_2P_COLDRV13X12 ADDR_COL_I<1> ADDR_COL_I<0> ADDR_COL_O<1> ++ ADDR_COL_O<0> ADDR_DEC_I<7> ADDR_DEC_I<6> ADDR_DEC_I<5> ADDR_DEC_I<4> ++ ADDR_DEC_I<3> ADDR_DEC_I<2> ADDR_DEC_I<1> ADDR_DEC_I<0> ADDR_DEC_O<7> ++ ADDR_DEC_O<6> ADDR_DEC_O<5> ADDR_DEC_O<4> ADDR_DEC_O<3> ADDR_DEC_O<2> ++ ADDR_DEC_O<1> ADDR_DEC_O<0> DCLK_I DCLK_O RCLK_I RCLK_O WCLK_I WCLK_O ++ VDD VSS +XI1<3> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI1<2> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI1<1> VDD VSS / RSC_IHPSG13_FILLCAP8 +XWCLK_DRV WCLK_I WCLK_O VDD VSS / RSC_IHPSG13_CBUFX12 +XRCLK_DRV RCLK_I RCLK_O VDD VSS / RSC_IHPSG13_CBUFX12 +XDCLK_DRV DCLK_I DCLK_O VDD VSS / RSC_IHPSG13_CBUFX12 +XADDR_COL_DRV<1> ADDR_COL_I<1> ADDR_COL_O<1> VDD VSS / ++ RSC_IHPSG13_CBUFX12 +XADDR_COL_DRV<0> ADDR_COL_I<0> ADDR_COL_O<0> VDD VSS / ++ RSC_IHPSG13_CBUFX12 +XADDR_DEC_DRV<7> ADDR_DEC_I<7> ADDR_DEC_O<7> VDD VSS / ++ RSC_IHPSG13_CBUFX12 +XADDR_DEC_DRV<6> ADDR_DEC_I<6> ADDR_DEC_O<6> VDD VSS / ++ RSC_IHPSG13_CBUFX12 +XADDR_DEC_DRV<5> ADDR_DEC_I<5> ADDR_DEC_O<5> VDD VSS / ++ RSC_IHPSG13_CBUFX12 +XADDR_DEC_DRV<4> ADDR_DEC_I<4> ADDR_DEC_O<4> VDD VSS / ++ RSC_IHPSG13_CBUFX12 +XADDR_DEC_DRV<3> ADDR_DEC_I<3> ADDR_DEC_O<3> VDD VSS / ++ RSC_IHPSG13_CBUFX12 +XADDR_DEC_DRV<2> ADDR_DEC_I<2> ADDR_DEC_O<2> VDD VSS / ++ RSC_IHPSG13_CBUFX12 +XADDR_DEC_DRV<1> ADDR_DEC_I<1> ADDR_DEC_O<1> VDD VSS / ++ RSC_IHPSG13_CBUFX12 +XADDR_DEC_DRV<0> ADDR_DEC_I<0> ADDR_DEC_O<0> VDD VSS / ++ RSC_IHPSG13_CBUFX12 +XI0<6> VDD VSS / RSC_IHPSG13_FILLCAP4 +XI0<5> VDD VSS / RSC_IHPSG13_FILLCAP4 +XI0<4> VDD VSS / RSC_IHPSG13_FILLCAP4 +XI0<3> VDD VSS / RSC_IHPSG13_FILLCAP4 +XI0<2> VDD VSS / RSC_IHPSG13_FILLCAP4 +XI0<1> VDD VSS / RSC_IHPSG13_FILLCAP4 +.ENDS +.SUBCKT RSC_IHPSG13_WLDRVX12 A Z VDD VSS +MN1 Z net6 VSS VSS sg13_lv_nmos m=1 w=1.41u l=130.00n ng=2 nrd=0 nrs=0 +MN0 net6 A VSS VSS sg13_lv_nmos m=1 w=1.8u l=130.00n ng=2 nrd=0 nrs=0 +MP1 Z net6 VDD VDD sg13_lv_pmos m=1 w=9.72u l=130.00n ng=6 nrd=0 nrs=0 +MP0 net6 A VDD VDD sg13_lv_pmos m=1 w=900.0n l=130.00n ng=1 nrd=0 nrs=0 +.ENDS +.SUBCKT RM_IHPSG13_8192x32_c4_2P_WLDRV16X12 A<15> A<14> A<13> A<12> A<11> A<10> A<9> A<8> ++ A<7> A<6> A<5> A<4> A<3> A<2> A<1> A<0> Z<15> Z<14> Z<13> Z<12> Z<11> Z<10> ++ Z<9> Z<8> Z<7> Z<6> Z<5> Z<4> Z<3> Z<2> Z<1> Z<0> VDD VSS +XBUF<15> A<15> Z<15> VDD VSS / RSC_IHPSG13_WLDRVX12 +XBUF<14> A<14> Z<14> VDD VSS / RSC_IHPSG13_WLDRVX12 +XBUF<13> A<13> Z<13> VDD VSS / RSC_IHPSG13_WLDRVX12 +XBUF<12> A<12> Z<12> VDD VSS / RSC_IHPSG13_WLDRVX12 +XBUF<11> A<11> Z<11> VDD VSS / RSC_IHPSG13_WLDRVX12 +XBUF<10> A<10> Z<10> VDD VSS / RSC_IHPSG13_WLDRVX12 +XBUF<9> A<9> Z<9> VDD VSS / RSC_IHPSG13_WLDRVX12 +XBUF<8> A<8> Z<8> VDD VSS / RSC_IHPSG13_WLDRVX12 +XBUF<7> A<7> Z<7> VDD VSS / RSC_IHPSG13_WLDRVX12 +XBUF<6> A<6> Z<6> VDD VSS / RSC_IHPSG13_WLDRVX12 +XBUF<5> A<5> Z<5> VDD VSS / RSC_IHPSG13_WLDRVX12 +XBUF<4> A<4> Z<4> VDD VSS / RSC_IHPSG13_WLDRVX12 +XBUF<3> A<3> Z<3> VDD VSS / RSC_IHPSG13_WLDRVX12 +XBUF<2> A<2> Z<2> VDD VSS / RSC_IHPSG13_WLDRVX12 +XBUF<1> A<1> Z<1> VDD VSS / RSC_IHPSG13_WLDRVX12 +XBUF<0> A<0> Z<0> VDD VSS / RSC_IHPSG13_WLDRVX12 +.ENDS +.SUBCKT RM_IHPSG13_8192x32_c4_2P_DEC04 ADDR<3> ADDR<2> ADDR<1> ADDR<0> CS ECLK_H_BOT ++ ECLK_H_TOP ECLK_L_BOT ECLK_L_TOP WL<15> WL<14> WL<13> WL<12> WL<11> WL<10> ++ WL<9> WL<8> WL<7> WL<6> WL<5> WL<4> WL<3> WL<2> WL<1> WL<0> VDD VSS +XI0<3> PADR<1> PADR<0> sel01<3> VDD VSS / RSC_IHPSG13_NAND2X2 +XI0<2> PADR<1> NADR<0> sel01<2> VDD VSS / RSC_IHPSG13_NAND2X2 +XI0<1> NADR<1> PADR<0> sel01<1> VDD VSS / RSC_IHPSG13_NAND2X2 +XI0<0> NADR<1> NADR<0> sel01<0> VDD VSS / RSC_IHPSG13_NAND2X2 +XI4 ECLK_L_BOT EN VDD VSS / RSC_IHPSG13_CINVX4 +XI5 ECLK_H_BOT ECLK_L_BOT VDD VSS / RSC_IHPSG13_CINVX2 +XI3<3> PADR<3> NADR<3> VDD VSS / RSC_IHPSG13_INVX2 +XI3<2> PADR<2> NADR<2> VDD VSS / RSC_IHPSG13_INVX2 +XI3<1> PADR<1> NADR<1> VDD VSS / RSC_IHPSG13_INVX2 +XI3<0> PADR<0> NADR<0> VDD VSS / RSC_IHPSG13_INVX2 +XR0 ECLK_H_BOT ECLK_H_TOP / RSC_IHPSG13_MET2RES +XI11 ECLK_L_BOT ECLK_L_TOP / RSC_IHPSG13_MET2RES +XI1<3> PADR<2> PADR<3> CS sel23<3> VDD VSS / RSC_IHPSG13_NAND3X2 +XI1<2> NADR<2> PADR<3> CS sel23<2> VDD VSS / RSC_IHPSG13_NAND3X2 +XI1<1> PADR<2> NADR<3> CS sel23<1> VDD VSS / RSC_IHPSG13_NAND3X2 +XI1<0> NADR<2> NADR<3> CS sel23<0> VDD VSS / RSC_IHPSG13_NAND3X2 +XI2<15> sel23<3> sel01<3> EN WL<15> VDD VSS / RSC_IHPSG13_NOR3X2 +XI2<14> sel23<3> sel01<2> EN WL<14> VDD VSS / RSC_IHPSG13_NOR3X2 +XI2<13> sel23<3> sel01<1> EN WL<13> VDD VSS / RSC_IHPSG13_NOR3X2 +XI2<12> sel23<3> sel01<0> EN WL<12> VDD VSS / RSC_IHPSG13_NOR3X2 +XI2<11> sel23<2> sel01<3> EN WL<11> VDD VSS / RSC_IHPSG13_NOR3X2 +XI2<10> sel23<2> sel01<2> EN WL<10> VDD VSS / RSC_IHPSG13_NOR3X2 +XI2<9> sel23<2> sel01<1> EN WL<9> VDD VSS / RSC_IHPSG13_NOR3X2 +XI2<8> sel23<2> sel01<0> EN WL<8> VDD VSS / RSC_IHPSG13_NOR3X2 +XI2<7> sel23<1> sel01<3> EN WL<7> VDD VSS / RSC_IHPSG13_NOR3X2 +XI2<6> sel23<1> sel01<2> EN WL<6> VDD VSS / RSC_IHPSG13_NOR3X2 +XI2<5> sel23<1> sel01<1> EN WL<5> VDD VSS / RSC_IHPSG13_NOR3X2 +XI2<4> sel23<1> sel01<0> EN WL<4> VDD VSS / RSC_IHPSG13_NOR3X2 +XI2<3> sel23<0> sel01<3> EN WL<3> VDD VSS / RSC_IHPSG13_NOR3X2 +XI2<2> sel23<0> sel01<2> EN WL<2> VDD VSS / RSC_IHPSG13_NOR3X2 +XI2<1> sel23<0> sel01<1> EN WL<1> VDD VSS / RSC_IHPSG13_NOR3X2 +XI2<0> sel23<0> sel01<0> EN WL<0> VDD VSS / RSC_IHPSG13_NOR3X2 +XCAPS4 VDD VSS / RSC_IHPSG13_FILLCAP4 +XLATCH<3> CS ADDR<3> PADR<3> VDD VSS / RSC_IHPSG13_LHPQX2 +XLATCH<2> CS ADDR<2> PADR<2> VDD VSS / RSC_IHPSG13_LHPQX2 +XLATCH<1> CS ADDR<1> PADR<1> VDD VSS / RSC_IHPSG13_LHPQX2 +XLATCH<0> CS ADDR<0> PADR<0> VDD VSS / RSC_IHPSG13_LHPQX2 +.ENDS +.SUBCKT RM_IHPSG13_8192x32_c4_2P_DEC02 ADDR<1> ADDR<0> CS CS_OUT VDD VSS +XDEC ADDR<1> NADDR<0> CS net1 VDD VSS / RSC_IHPSG13_NAND3X2 +XADDRINV ADDR<0> NADDR<0> VDD VSS / RSC_IHPSG13_INVX2 +XDECINV net1 CS_OUT VDD VSS / RSC_IHPSG13_INVX4 +XI2<1> VDD VSS / RSC_IHPSG13_FILLCAP4 +XI2<0> VDD VSS / RSC_IHPSG13_FILLCAP4 +.ENDS +.SUBCKT RM_IHPSG13_8192x32_c4_2P_DEC01 ADDR<1> ADDR<0> CS CS_OUT VDD VSS +XDEC NADDR<1> ADDR<0> CS net1 VDD VSS / RSC_IHPSG13_NAND3X2 +XADDRINV ADDR<1> NADDR<1> VDD VSS / RSC_IHPSG13_INVX2 +XDECINV net1 CS_OUT VDD VSS / RSC_IHPSG13_INVX4 +XI2<1> VDD VSS / RSC_IHPSG13_FILLCAP4 +XI2<0> VDD VSS / RSC_IHPSG13_FILLCAP4 +.ENDS +.SUBCKT RM_IHPSG13_8192x32_c4_2P_DEC00 ADDR<1> ADDR<0> CS CS_OUT VDD VSS +XDEC NADDR<1> NADDR<0> CS net1 VDD VSS / RSC_IHPSG13_NAND3X2 +XADDRINV<1> ADDR<1> NADDR<1> VDD VSS / RSC_IHPSG13_INVX2 +XADDRINV<0> ADDR<0> NADDR<0> VDD VSS / RSC_IHPSG13_INVX2 +XI1<1> VDD VSS / RSC_IHPSG13_FILLCAP4 +XI1<0> VDD VSS / RSC_IHPSG13_FILLCAP4 +XDECINV net1 CS_OUT VDD VSS / RSC_IHPSG13_INVX4 +.ENDS +.SUBCKT RM_IHPSG13_8192x32_c4_2P_DEC03 ADDR<1> ADDR<0> CS CS_OUT VDD VSS +XDEC ADDR<1> ADDR<0> CS net1 VDD VSS / RSC_IHPSG13_NAND3X2 +XDECINV net1 CS_OUT VDD VSS / RSC_IHPSG13_INVX4 +XI0<1> VDD VSS / RSC_IHPSG13_FILLCAP4 +XI0<0> VDD VSS / RSC_IHPSG13_FILLCAP4 +.ENDS +.SUBCKT RM_IHPSG13_8192x32_c4_2P_ROWDEC9 ADDR_N_I<8> ADDR_N_I<7> ADDR_N_I<6> ADDR_N_I<5> ++ ADDR_N_I<4> ADDR_N_I<3> ADDR_N_I<2> ADDR_N_I<1> ADDR_N_I<0> CS_I ECLK_I ++ WL_O<511> WL_O<510> WL_O<509> WL_O<508> WL_O<507> WL_O<506> WL_O<505> ++ WL_O<504> WL_O<503> WL_O<502> WL_O<501> WL_O<500> WL_O<499> WL_O<498> ++ WL_O<497> WL_O<496> WL_O<495> WL_O<494> WL_O<493> WL_O<492> WL_O<491> ++ WL_O<490> WL_O<489> WL_O<488> WL_O<487> WL_O<486> WL_O<485> WL_O<484> ++ WL_O<483> WL_O<482> WL_O<481> WL_O<480> WL_O<479> WL_O<478> WL_O<477> ++ WL_O<476> WL_O<475> WL_O<474> WL_O<473> WL_O<472> WL_O<471> WL_O<470> ++ WL_O<469> WL_O<468> WL_O<467> WL_O<466> WL_O<465> WL_O<464> WL_O<463> ++ WL_O<462> WL_O<461> WL_O<460> WL_O<459> WL_O<458> WL_O<457> WL_O<456> ++ WL_O<455> WL_O<454> WL_O<453> WL_O<452> WL_O<451> WL_O<450> WL_O<449> ++ WL_O<448> WL_O<447> WL_O<446> WL_O<445> WL_O<444> WL_O<443> WL_O<442> ++ WL_O<441> WL_O<440> WL_O<439> WL_O<438> WL_O<437> WL_O<436> WL_O<435> ++ WL_O<434> WL_O<433> WL_O<432> WL_O<431> WL_O<430> WL_O<429> WL_O<428> ++ WL_O<427> WL_O<426> WL_O<425> WL_O<424> WL_O<423> WL_O<422> WL_O<421> ++ WL_O<420> WL_O<419> WL_O<418> WL_O<417> WL_O<416> WL_O<415> WL_O<414> ++ WL_O<413> WL_O<412> WL_O<411> WL_O<410> WL_O<409> WL_O<408> WL_O<407> ++ WL_O<406> WL_O<405> WL_O<404> WL_O<403> WL_O<402> WL_O<401> WL_O<400> ++ WL_O<399> WL_O<398> WL_O<397> WL_O<396> WL_O<395> WL_O<394> WL_O<393> ++ WL_O<392> WL_O<391> WL_O<390> WL_O<389> WL_O<388> WL_O<387> WL_O<386> ++ WL_O<385> WL_O<384> WL_O<383> WL_O<382> WL_O<381> WL_O<380> WL_O<379> ++ WL_O<378> WL_O<377> WL_O<376> WL_O<375> WL_O<374> WL_O<373> WL_O<372> ++ WL_O<371> WL_O<370> WL_O<369> WL_O<368> WL_O<367> WL_O<366> WL_O<365> ++ WL_O<364> WL_O<363> WL_O<362> WL_O<361> WL_O<360> WL_O<359> WL_O<358> ++ WL_O<357> WL_O<356> WL_O<355> WL_O<354> WL_O<353> WL_O<352> WL_O<351> ++ WL_O<350> WL_O<349> WL_O<348> WL_O<347> WL_O<346> WL_O<345> WL_O<344> ++ WL_O<343> WL_O<342> WL_O<341> WL_O<340> WL_O<339> WL_O<338> WL_O<337> ++ WL_O<336> WL_O<335> WL_O<334> WL_O<333> WL_O<332> WL_O<331> WL_O<330> ++ WL_O<329> WL_O<328> WL_O<327> WL_O<326> WL_O<325> WL_O<324> WL_O<323> ++ WL_O<322> WL_O<321> WL_O<320> WL_O<319> WL_O<318> WL_O<317> WL_O<316> ++ WL_O<315> WL_O<314> WL_O<313> WL_O<312> WL_O<311> WL_O<310> WL_O<309> ++ WL_O<308> WL_O<307> WL_O<306> WL_O<305> WL_O<304> WL_O<303> WL_O<302> ++ WL_O<301> WL_O<300> WL_O<299> WL_O<298> WL_O<297> WL_O<296> WL_O<295> ++ WL_O<294> WL_O<293> WL_O<292> WL_O<291> WL_O<290> WL_O<289> WL_O<288> ++ WL_O<287> WL_O<286> WL_O<285> WL_O<284> WL_O<283> WL_O<282> WL_O<281> ++ WL_O<280> WL_O<279> WL_O<278> WL_O<277> WL_O<276> WL_O<275> WL_O<274> ++ WL_O<273> WL_O<272> WL_O<271> WL_O<270> WL_O<269> WL_O<268> WL_O<267> ++ WL_O<266> WL_O<265> WL_O<264> WL_O<263> WL_O<262> WL_O<261> WL_O<260> ++ WL_O<259> WL_O<258> WL_O<257> WL_O<256> WL_O<255> WL_O<254> WL_O<253> ++ WL_O<252> WL_O<251> WL_O<250> WL_O<249> WL_O<248> WL_O<247> WL_O<246> ++ WL_O<245> WL_O<244> WL_O<243> WL_O<242> WL_O<241> WL_O<240> WL_O<239> ++ WL_O<238> WL_O<237> WL_O<236> WL_O<235> WL_O<234> WL_O<233> WL_O<232> ++ WL_O<231> WL_O<230> WL_O<229> WL_O<228> WL_O<227> WL_O<226> WL_O<225> ++ WL_O<224> WL_O<223> WL_O<222> WL_O<221> WL_O<220> WL_O<219> WL_O<218> ++ WL_O<217> WL_O<216> WL_O<215> WL_O<214> WL_O<213> WL_O<212> WL_O<211> ++ WL_O<210> WL_O<209> WL_O<208> WL_O<207> WL_O<206> WL_O<205> WL_O<204> ++ WL_O<203> WL_O<202> WL_O<201> WL_O<200> WL_O<199> WL_O<198> WL_O<197> ++ WL_O<196> WL_O<195> WL_O<194> WL_O<193> WL_O<192> WL_O<191> WL_O<190> ++ WL_O<189> WL_O<188> WL_O<187> WL_O<186> WL_O<185> WL_O<184> WL_O<183> ++ WL_O<182> WL_O<181> WL_O<180> WL_O<179> WL_O<178> WL_O<177> WL_O<176> ++ WL_O<175> WL_O<174> WL_O<173> WL_O<172> WL_O<171> WL_O<170> WL_O<169> ++ WL_O<168> WL_O<167> WL_O<166> WL_O<165> WL_O<164> WL_O<163> WL_O<162> ++ WL_O<161> WL_O<160> WL_O<159> WL_O<158> WL_O<157> WL_O<156> WL_O<155> ++ WL_O<154> WL_O<153> WL_O<152> WL_O<151> WL_O<150> WL_O<149> WL_O<148> ++ WL_O<147> WL_O<146> WL_O<145> WL_O<144> WL_O<143> WL_O<142> WL_O<141> ++ WL_O<140> WL_O<139> WL_O<138> WL_O<137> WL_O<136> WL_O<135> WL_O<134> ++ WL_O<133> WL_O<132> WL_O<131> WL_O<130> WL_O<129> WL_O<128> WL_O<127> ++ WL_O<126> WL_O<125> WL_O<124> WL_O<123> WL_O<122> WL_O<121> WL_O<120> ++ WL_O<119> WL_O<118> WL_O<117> WL_O<116> WL_O<115> WL_O<114> WL_O<113> ++ WL_O<112> WL_O<111> WL_O<110> WL_O<109> WL_O<108> WL_O<107> WL_O<106> ++ WL_O<105> WL_O<104> WL_O<103> WL_O<102> WL_O<101> WL_O<100> WL_O<99> ++ WL_O<98> WL_O<97> WL_O<96> WL_O<95> WL_O<94> WL_O<93> WL_O<92> WL_O<91> ++ WL_O<90> WL_O<89> WL_O<88> WL_O<87> WL_O<86> WL_O<85> WL_O<84> WL_O<83> ++ WL_O<82> WL_O<81> WL_O<80> WL_O<79> WL_O<78> WL_O<77> WL_O<76> WL_O<75> ++ WL_O<74> WL_O<73> WL_O<72> WL_O<71> WL_O<70> WL_O<69> WL_O<68> WL_O<67> ++ WL_O<66> WL_O<65> WL_O<64> WL_O<63> WL_O<62> WL_O<61> WL_O<60> WL_O<59> ++ WL_O<58> WL_O<57> WL_O<56> WL_O<55> WL_O<54> WL_O<53> WL_O<52> WL_O<51> ++ WL_O<50> WL_O<49> WL_O<48> WL_O<47> WL_O<46> WL_O<45> WL_O<44> WL_O<43> ++ WL_O<42> WL_O<41> WL_O<40> WL_O<39> WL_O<38> WL_O<37> WL_O<36> WL_O<35> ++ WL_O<34> WL_O<33> WL_O<32> WL_O<31> WL_O<30> WL_O<29> WL_O<28> WL_O<27> ++ WL_O<26> WL_O<25> WL_O<24> WL_O<23> WL_O<22> WL_O<21> WL_O<20> WL_O<19> ++ WL_O<18> WL_O<17> WL_O<16> WL_O<15> WL_O<14> WL_O<13> WL_O<12> WL_O<11> ++ WL_O<10> WL_O<9> WL_O<8> WL_O<7> WL_O<6> WL_O<5> WL_O<4> WL_O<3> WL_O<2> ++ WL_O<1> WL_O<0> VDD VSS +XSEL<31> ADDR_N_I<3> ADDR_N_I<2> ADDR_N_I<1> ADDR_N_I<0> CS00<31> ECLK_H<31> ++ ECLK_H<32> ECLK_B<31> ECLK_B<32> WL_O<511> WL_O<510> WL_O<509> WL_O<508> ++ WL_O<507> WL_O<506> WL_O<505> WL_O<504> WL_O<503> WL_O<502> WL_O<501> ++ WL_O<500> WL_O<499> WL_O<498> WL_O<497> WL_O<496> VDD VSS / ++ RM_IHPSG13_8192x32_c4_2P_DEC04 +XSEL<30> ADDR_N_I<3> ADDR_N_I<2> ADDR_N_I<1> ADDR_N_I<0> CS00<30> ECLK_H<30> ++ ECLK_H<31> ECLK_B<30> ECLK_B<31> WL_O<495> WL_O<494> WL_O<493> WL_O<492> ++ WL_O<491> WL_O<490> WL_O<489> WL_O<488> WL_O<487> WL_O<486> WL_O<485> ++ WL_O<484> WL_O<483> WL_O<482> WL_O<481> WL_O<480> VDD VSS / ++ RM_IHPSG13_8192x32_c4_2P_DEC04 +XSEL<29> ADDR_N_I<3> ADDR_N_I<2> ADDR_N_I<1> ADDR_N_I<0> CS00<29> ECLK_H<29> ++ ECLK_H<30> ECLK_B<29> ECLK_B<30> WL_O<479> WL_O<478> WL_O<477> WL_O<476> ++ WL_O<475> WL_O<474> WL_O<473> WL_O<472> WL_O<471> WL_O<470> WL_O<469> ++ WL_O<468> WL_O<467> WL_O<466> WL_O<465> WL_O<464> VDD VSS / ++ RM_IHPSG13_8192x32_c4_2P_DEC04 +XSEL<28> ADDR_N_I<3> ADDR_N_I<2> ADDR_N_I<1> ADDR_N_I<0> CS00<28> ECLK_H<28> ++ ECLK_H<29> ECLK_B<28> ECLK_B<29> WL_O<463> WL_O<462> WL_O<461> WL_O<460> ++ WL_O<459> WL_O<458> WL_O<457> WL_O<456> WL_O<455> WL_O<454> WL_O<453> ++ WL_O<452> WL_O<451> WL_O<450> WL_O<449> WL_O<448> VDD VSS / ++ RM_IHPSG13_8192x32_c4_2P_DEC04 +XSEL<27> ADDR_N_I<3> ADDR_N_I<2> ADDR_N_I<1> ADDR_N_I<0> CS00<27> ECLK_H<27> ++ ECLK_H<28> ECLK_B<27> ECLK_B<28> WL_O<447> WL_O<446> WL_O<445> WL_O<444> ++ WL_O<443> WL_O<442> WL_O<441> WL_O<440> WL_O<439> WL_O<438> WL_O<437> ++ WL_O<436> WL_O<435> WL_O<434> WL_O<433> WL_O<432> VDD VSS / ++ RM_IHPSG13_8192x32_c4_2P_DEC04 +XSEL<26> ADDR_N_I<3> ADDR_N_I<2> ADDR_N_I<1> ADDR_N_I<0> CS00<26> ECLK_H<26> ++ ECLK_H<27> ECLK_B<26> ECLK_B<27> WL_O<431> WL_O<430> WL_O<429> WL_O<428> ++ WL_O<427> WL_O<426> WL_O<425> WL_O<424> WL_O<423> WL_O<422> WL_O<421> ++ WL_O<420> WL_O<419> WL_O<418> WL_O<417> WL_O<416> VDD VSS / ++ RM_IHPSG13_8192x32_c4_2P_DEC04 +XSEL<25> ADDR_N_I<3> ADDR_N_I<2> ADDR_N_I<1> ADDR_N_I<0> CS00<25> ECLK_H<25> ++ ECLK_H<26> ECLK_B<25> ECLK_B<26> WL_O<415> WL_O<414> WL_O<413> WL_O<412> ++ WL_O<411> WL_O<410> WL_O<409> WL_O<408> WL_O<407> WL_O<406> WL_O<405> ++ WL_O<404> WL_O<403> WL_O<402> WL_O<401> WL_O<400> VDD VSS / ++ RM_IHPSG13_8192x32_c4_2P_DEC04 +XSEL<24> ADDR_N_I<3> ADDR_N_I<2> ADDR_N_I<1> ADDR_N_I<0> CS00<24> ECLK_H<24> ++ ECLK_H<25> ECLK_B<24> ECLK_B<25> WL_O<399> WL_O<398> WL_O<397> WL_O<396> ++ WL_O<395> WL_O<394> WL_O<393> WL_O<392> WL_O<391> WL_O<390> WL_O<389> ++ WL_O<388> WL_O<387> WL_O<386> WL_O<385> WL_O<384> VDD VSS / ++ RM_IHPSG13_8192x32_c4_2P_DEC04 +XSEL<23> ADDR_N_I<3> ADDR_N_I<2> ADDR_N_I<1> ADDR_N_I<0> CS00<23> ECLK_H<23> ++ ECLK_H<24> ECLK_B<23> ECLK_B<24> WL_O<383> WL_O<382> WL_O<381> WL_O<380> ++ WL_O<379> WL_O<378> WL_O<377> WL_O<376> WL_O<375> WL_O<374> WL_O<373> ++ WL_O<372> WL_O<371> WL_O<370> WL_O<369> WL_O<368> VDD VSS / ++ RM_IHPSG13_8192x32_c4_2P_DEC04 +XSEL<22> ADDR_N_I<3> ADDR_N_I<2> ADDR_N_I<1> ADDR_N_I<0> CS00<22> ECLK_H<22> ++ ECLK_H<23> ECLK_B<22> ECLK_B<23> WL_O<367> WL_O<366> WL_O<365> WL_O<364> ++ WL_O<363> WL_O<362> WL_O<361> WL_O<360> WL_O<359> WL_O<358> WL_O<357> ++ WL_O<356> WL_O<355> WL_O<354> WL_O<353> WL_O<352> VDD VSS / ++ RM_IHPSG13_8192x32_c4_2P_DEC04 +XSEL<21> ADDR_N_I<3> ADDR_N_I<2> ADDR_N_I<1> ADDR_N_I<0> CS00<21> ECLK_H<21> ++ ECLK_H<22> ECLK_B<21> ECLK_B<22> WL_O<351> WL_O<350> WL_O<349> WL_O<348> ++ WL_O<347> WL_O<346> WL_O<345> WL_O<344> WL_O<343> WL_O<342> WL_O<341> ++ WL_O<340> WL_O<339> WL_O<338> WL_O<337> WL_O<336> VDD VSS / ++ RM_IHPSG13_8192x32_c4_2P_DEC04 +XSEL<20> ADDR_N_I<3> ADDR_N_I<2> ADDR_N_I<1> ADDR_N_I<0> CS00<20> ECLK_H<20> ++ ECLK_H<21> ECLK_B<20> ECLK_B<21> WL_O<335> WL_O<334> WL_O<333> WL_O<332> ++ WL_O<331> WL_O<330> WL_O<329> WL_O<328> WL_O<327> WL_O<326> WL_O<325> ++ WL_O<324> WL_O<323> WL_O<322> WL_O<321> WL_O<320> VDD VSS / ++ RM_IHPSG13_8192x32_c4_2P_DEC04 +XSEL<19> ADDR_N_I<3> ADDR_N_I<2> ADDR_N_I<1> ADDR_N_I<0> CS00<19> ECLK_H<19> ++ ECLK_H<20> ECLK_B<19> ECLK_B<20> WL_O<319> WL_O<318> WL_O<317> WL_O<316> ++ WL_O<315> WL_O<314> WL_O<313> WL_O<312> WL_O<311> WL_O<310> WL_O<309> ++ WL_O<308> WL_O<307> WL_O<306> WL_O<305> WL_O<304> VDD VSS / ++ RM_IHPSG13_8192x32_c4_2P_DEC04 +XSEL<18> ADDR_N_I<3> ADDR_N_I<2> ADDR_N_I<1> ADDR_N_I<0> CS00<18> ECLK_H<18> ++ ECLK_H<19> ECLK_B<18> ECLK_B<19> WL_O<303> WL_O<302> WL_O<301> WL_O<300> ++ WL_O<299> WL_O<298> WL_O<297> WL_O<296> WL_O<295> WL_O<294> WL_O<293> ++ WL_O<292> WL_O<291> WL_O<290> WL_O<289> WL_O<288> VDD VSS / ++ RM_IHPSG13_8192x32_c4_2P_DEC04 +XSEL<17> ADDR_N_I<3> ADDR_N_I<2> ADDR_N_I<1> ADDR_N_I<0> CS00<17> ECLK_H<17> ++ ECLK_H<18> ECLK_B<17> ECLK_B<18> WL_O<287> WL_O<286> WL_O<285> WL_O<284> ++ WL_O<283> WL_O<282> WL_O<281> WL_O<280> WL_O<279> WL_O<278> WL_O<277> ++ WL_O<276> WL_O<275> WL_O<274> WL_O<273> WL_O<272> VDD VSS / ++ RM_IHPSG13_8192x32_c4_2P_DEC04 +XSEL<16> ADDR_N_I<3> ADDR_N_I<2> ADDR_N_I<1> ADDR_N_I<0> CS00<16> ECLK_H<16> ++ ECLK_H<17> ECLK_B<16> ECLK_B<17> WL_O<271> WL_O<270> WL_O<269> WL_O<268> ++ WL_O<267> WL_O<266> WL_O<265> WL_O<264> WL_O<263> WL_O<262> WL_O<261> ++ WL_O<260> WL_O<259> WL_O<258> WL_O<257> WL_O<256> VDD VSS / ++ RM_IHPSG13_8192x32_c4_2P_DEC04 +XSEL<15> ADDR_N_I<3> ADDR_N_I<2> ADDR_N_I<1> ADDR_N_I<0> CS00<15> ECLK_H<15> ++ ECLK_H<16> ECLK_B<15> ECLK_B<16> WL_O<255> WL_O<254> WL_O<253> WL_O<252> ++ WL_O<251> WL_O<250> WL_O<249> WL_O<248> WL_O<247> WL_O<246> WL_O<245> ++ WL_O<244> WL_O<243> WL_O<242> WL_O<241> WL_O<240> VDD VSS / ++ RM_IHPSG13_8192x32_c4_2P_DEC04 +XSEL<14> ADDR_N_I<3> ADDR_N_I<2> ADDR_N_I<1> ADDR_N_I<0> CS00<14> ECLK_H<14> ++ ECLK_H<15> ECLK_B<14> ECLK_B<15> WL_O<239> WL_O<238> WL_O<237> WL_O<236> ++ WL_O<235> WL_O<234> WL_O<233> WL_O<232> WL_O<231> WL_O<230> WL_O<229> ++ WL_O<228> WL_O<227> WL_O<226> WL_O<225> WL_O<224> VDD VSS / ++ RM_IHPSG13_8192x32_c4_2P_DEC04 +XSEL<13> ADDR_N_I<3> ADDR_N_I<2> ADDR_N_I<1> ADDR_N_I<0> CS00<13> ECLK_H<13> ++ ECLK_H<14> ECLK_B<13> ECLK_B<14> WL_O<223> WL_O<222> WL_O<221> WL_O<220> ++ WL_O<219> WL_O<218> WL_O<217> WL_O<216> WL_O<215> WL_O<214> WL_O<213> ++ WL_O<212> WL_O<211> WL_O<210> WL_O<209> WL_O<208> VDD VSS / ++ RM_IHPSG13_8192x32_c4_2P_DEC04 +XSEL<12> ADDR_N_I<3> ADDR_N_I<2> ADDR_N_I<1> ADDR_N_I<0> CS00<12> ECLK_H<12> ++ ECLK_H<13> ECLK_B<12> ECLK_B<13> WL_O<207> WL_O<206> WL_O<205> WL_O<204> ++ WL_O<203> WL_O<202> WL_O<201> WL_O<200> WL_O<199> WL_O<198> WL_O<197> ++ WL_O<196> WL_O<195> WL_O<194> WL_O<193> WL_O<192> VDD VSS / ++ RM_IHPSG13_8192x32_c4_2P_DEC04 +XSEL<11> ADDR_N_I<3> ADDR_N_I<2> ADDR_N_I<1> ADDR_N_I<0> CS00<11> ECLK_H<11> ++ ECLK_H<12> ECLK_B<11> ECLK_B<12> WL_O<191> WL_O<190> WL_O<189> WL_O<188> ++ WL_O<187> WL_O<186> WL_O<185> WL_O<184> WL_O<183> WL_O<182> WL_O<181> ++ WL_O<180> WL_O<179> WL_O<178> WL_O<177> WL_O<176> VDD VSS / ++ RM_IHPSG13_8192x32_c4_2P_DEC04 +XSEL<10> ADDR_N_I<3> ADDR_N_I<2> ADDR_N_I<1> ADDR_N_I<0> CS00<10> ECLK_H<10> ++ ECLK_H<11> ECLK_B<10> ECLK_B<11> WL_O<175> WL_O<174> WL_O<173> WL_O<172> ++ WL_O<171> WL_O<170> WL_O<169> WL_O<168> WL_O<167> WL_O<166> WL_O<165> ++ WL_O<164> WL_O<163> WL_O<162> WL_O<161> WL_O<160> VDD VSS / ++ RM_IHPSG13_8192x32_c4_2P_DEC04 +XSEL<9> ADDR_N_I<3> ADDR_N_I<2> ADDR_N_I<1> ADDR_N_I<0> CS00<9> ECLK_H<9> ++ ECLK_H<10> ECLK_B<9> ECLK_B<10> WL_O<159> WL_O<158> WL_O<157> WL_O<156> ++ WL_O<155> WL_O<154> WL_O<153> WL_O<152> WL_O<151> WL_O<150> WL_O<149> ++ WL_O<148> WL_O<147> WL_O<146> WL_O<145> WL_O<144> VDD VSS / ++ RM_IHPSG13_8192x32_c4_2P_DEC04 +XSEL<8> ADDR_N_I<3> ADDR_N_I<2> ADDR_N_I<1> ADDR_N_I<0> CS00<8> ECLK_H<8> ++ ECLK_H<9> ECLK_B<8> ECLK_B<9> WL_O<143> WL_O<142> WL_O<141> WL_O<140> ++ WL_O<139> WL_O<138> WL_O<137> WL_O<136> WL_O<135> WL_O<134> WL_O<133> ++ WL_O<132> WL_O<131> WL_O<130> WL_O<129> WL_O<128> VDD VSS / ++ RM_IHPSG13_8192x32_c4_2P_DEC04 +XSEL<7> ADDR_N_I<3> ADDR_N_I<2> ADDR_N_I<1> ADDR_N_I<0> CS00<7> ECLK_H<7> ++ ECLK_H<8> ECLK_B<7> ECLK_B<8> WL_O<127> WL_O<126> WL_O<125> WL_O<124> ++ WL_O<123> WL_O<122> WL_O<121> WL_O<120> WL_O<119> WL_O<118> WL_O<117> ++ WL_O<116> WL_O<115> WL_O<114> WL_O<113> WL_O<112> VDD VSS / ++ RM_IHPSG13_8192x32_c4_2P_DEC04 +XSEL<6> ADDR_N_I<3> ADDR_N_I<2> ADDR_N_I<1> ADDR_N_I<0> CS00<6> ECLK_H<6> ++ ECLK_H<7> ECLK_B<6> ECLK_B<7> WL_O<111> WL_O<110> WL_O<109> WL_O<108> ++ WL_O<107> WL_O<106> WL_O<105> WL_O<104> WL_O<103> WL_O<102> WL_O<101> ++ WL_O<100> WL_O<99> WL_O<98> WL_O<97> WL_O<96> VDD VSS / ++ RM_IHPSG13_8192x32_c4_2P_DEC04 +XSEL<5> ADDR_N_I<3> ADDR_N_I<2> ADDR_N_I<1> ADDR_N_I<0> CS00<5> ECLK_H<5> ++ ECLK_H<6> ECLK_B<5> ECLK_B<6> WL_O<95> WL_O<94> WL_O<93> WL_O<92> WL_O<91> ++ WL_O<90> WL_O<89> WL_O<88> WL_O<87> WL_O<86> WL_O<85> WL_O<84> WL_O<83> ++ WL_O<82> WL_O<81> WL_O<80> VDD VSS / RM_IHPSG13_8192x32_c4_2P_DEC04 +XSEL<4> ADDR_N_I<3> ADDR_N_I<2> ADDR_N_I<1> ADDR_N_I<0> CS00<4> ECLK_H<4> ++ ECLK_H<5> ECLK_B<4> ECLK_B<5> WL_O<79> WL_O<78> WL_O<77> WL_O<76> WL_O<75> ++ WL_O<74> WL_O<73> WL_O<72> WL_O<71> WL_O<70> WL_O<69> WL_O<68> WL_O<67> ++ WL_O<66> WL_O<65> WL_O<64> VDD VSS / RM_IHPSG13_8192x32_c4_2P_DEC04 +XSEL<3> ADDR_N_I<3> ADDR_N_I<2> ADDR_N_I<1> ADDR_N_I<0> CS00<3> ECLK_H<3> ++ ECLK_H<4> ECLK_B<3> ECLK_B<4> WL_O<63> WL_O<62> WL_O<61> WL_O<60> WL_O<59> ++ WL_O<58> WL_O<57> WL_O<56> WL_O<55> WL_O<54> WL_O<53> WL_O<52> WL_O<51> ++ WL_O<50> WL_O<49> WL_O<48> VDD VSS / RM_IHPSG13_8192x32_c4_2P_DEC04 +XSEL<2> ADDR_N_I<3> ADDR_N_I<2> ADDR_N_I<1> ADDR_N_I<0> CS00<2> ECLK_H<2> ++ ECLK_H<3> ECLK_B<2> ECLK_B<3> WL_O<47> WL_O<46> WL_O<45> WL_O<44> WL_O<43> ++ WL_O<42> WL_O<41> WL_O<40> WL_O<39> WL_O<38> WL_O<37> WL_O<36> WL_O<35> ++ WL_O<34> WL_O<33> WL_O<32> VDD VSS / RM_IHPSG13_8192x32_c4_2P_DEC04 +XSEL<1> ADDR_N_I<3> ADDR_N_I<2> ADDR_N_I<1> ADDR_N_I<0> CS00<1> ECLK_H<1> ++ ECLK_H<2> ECLK_B<1> ECLK_B<2> WL_O<31> WL_O<30> WL_O<29> WL_O<28> WL_O<27> ++ WL_O<26> WL_O<25> WL_O<24> WL_O<23> WL_O<22> WL_O<21> WL_O<20> WL_O<19> ++ WL_O<18> WL_O<17> WL_O<16> VDD VSS / RM_IHPSG13_8192x32_c4_2P_DEC04 +XSEL<0> ADDR_N_I<3> ADDR_N_I<2> ADDR_N_I<1> ADDR_N_I<0> CS00<0> ECLK_I ++ ECLK_H<1> ECLK_B<0> ECLK_B<1> WL_O<15> WL_O<14> WL_O<13> WL_O<12> WL_O<11> ++ WL_O<10> WL_O<9> WL_O<8> WL_O<7> WL_O<6> WL_O<5> WL_O<4> WL_O<3> WL_O<2> ++ WL_O<1> WL_O<0> VDD VSS / RM_IHPSG13_8192x32_c4_2P_DEC04 +XDEC10<9> ADDR_N_I<7> ADDR_N_I<6> CS04<1> CS02<6> VDD VSS / ++ RM_IHPSG13_8192x32_c4_2P_DEC02 +XDEC10<8> ADDR_N_I<7> ADDR_N_I<6> CS04<0> CS02<2> VDD VSS / ++ RM_IHPSG13_8192x32_c4_2P_DEC02 +XDEC10<7> ADDR_N_I<5> ADDR_N_I<4> CS02<7> CS00<30> VDD VSS / ++ RM_IHPSG13_8192x32_c4_2P_DEC02 +XDEC10<6> ADDR_N_I<5> ADDR_N_I<4> CS02<6> CS00<26> VDD VSS / ++ RM_IHPSG13_8192x32_c4_2P_DEC02 +XDEC10<5> ADDR_N_I<5> ADDR_N_I<4> CS02<5> CS00<22> VDD VSS / ++ RM_IHPSG13_8192x32_c4_2P_DEC02 +XDEC10<4> ADDR_N_I<5> ADDR_N_I<4> CS02<4> CS00<18> VDD VSS / ++ RM_IHPSG13_8192x32_c4_2P_DEC02 +XDEC10<3> ADDR_N_I<5> ADDR_N_I<4> CS02<3> CS00<14> VDD VSS / ++ RM_IHPSG13_8192x32_c4_2P_DEC02 +XDEC10<2> ADDR_N_I<5> ADDR_N_I<4> CS02<2> CS00<10> VDD VSS / ++ RM_IHPSG13_8192x32_c4_2P_DEC02 +XDEC10<1> ADDR_N_I<5> ADDR_N_I<4> CS02<1> CS00<6> VDD VSS / ++ RM_IHPSG13_8192x32_c4_2P_DEC02 +XDEC10<0> ADDR_N_I<5> ADDR_N_I<4> CS02<0> CS00<2> VDD VSS / ++ RM_IHPSG13_8192x32_c4_2P_DEC02 +XDEC01<10> ADDR_N_I<9> ADDR_N_I<8> CS_I CS04<1> VDD VSS / ++ RM_IHPSG13_8192x32_c4_2P_DEC01 +XDEC01<9> ADDR_N_I<7> ADDR_N_I<6> CS04<1> CS02<5> VDD VSS / ++ RM_IHPSG13_8192x32_c4_2P_DEC01 +XDEC01<8> ADDR_N_I<7> ADDR_N_I<6> CS04<0> CS02<1> VDD VSS / ++ RM_IHPSG13_8192x32_c4_2P_DEC01 +XDEC01<7> ADDR_N_I<5> ADDR_N_I<4> CS02<7> CS00<29> VDD VSS / ++ RM_IHPSG13_8192x32_c4_2P_DEC01 +XDEC01<6> ADDR_N_I<5> ADDR_N_I<4> CS02<6> CS00<25> VDD VSS / ++ RM_IHPSG13_8192x32_c4_2P_DEC01 +XDEC01<5> ADDR_N_I<5> ADDR_N_I<4> CS02<5> CS00<21> VDD VSS / ++ RM_IHPSG13_8192x32_c4_2P_DEC01 +XDEC01<4> ADDR_N_I<5> ADDR_N_I<4> CS02<4> CS00<17> VDD VSS / ++ RM_IHPSG13_8192x32_c4_2P_DEC01 +XDEC01<3> ADDR_N_I<5> ADDR_N_I<4> CS02<3> CS00<13> VDD VSS / ++ RM_IHPSG13_8192x32_c4_2P_DEC01 +XDEC01<2> ADDR_N_I<5> ADDR_N_I<4> CS02<2> CS00<9> VDD VSS / ++ RM_IHPSG13_8192x32_c4_2P_DEC01 +XDEC01<1> ADDR_N_I<5> ADDR_N_I<4> CS02<1> CS00<5> VDD VSS / ++ RM_IHPSG13_8192x32_c4_2P_DEC01 +XDEC01<0> ADDR_N_I<5> ADDR_N_I<4> CS02<0> CS00<1> VDD VSS / ++ RM_IHPSG13_8192x32_c4_2P_DEC01 +XL2<258> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<257> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<256> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<255> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<254> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<253> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<252> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<251> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<250> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<249> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<248> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<247> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<246> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<245> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<244> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<243> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<242> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<241> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<240> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<239> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<238> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<237> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<236> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<235> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<234> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<233> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<232> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<231> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<230> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<229> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<228> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<227> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<226> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<225> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<224> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<223> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<222> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<221> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<220> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<219> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<218> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<217> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<216> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<215> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<214> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<213> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<212> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<211> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<210> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<209> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<208> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<207> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<206> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<205> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<204> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<203> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<202> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<201> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<200> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<199> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<198> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<197> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<196> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<195> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<194> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<193> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<192> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<191> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<190> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<189> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<188> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<187> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<186> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<185> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<184> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<183> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<182> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<181> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<180> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<179> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<178> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<177> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<176> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<175> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<174> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<173> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<172> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<171> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<170> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<169> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<168> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<167> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<166> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<165> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<164> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<163> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<162> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<161> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<160> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<159> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<158> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<157> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<156> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<155> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<154> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<153> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<152> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<151> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<150> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<149> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<148> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<147> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<146> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<145> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<144> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<143> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<142> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<141> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<140> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<139> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<138> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<137> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<136> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<135> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<134> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<133> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<132> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<131> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<130> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<129> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<128> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<127> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<126> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<125> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<124> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<123> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<122> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<121> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<120> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<119> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<118> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<117> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<116> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<115> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<114> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<113> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<112> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<111> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<110> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<109> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<108> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<107> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<106> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<105> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<104> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<103> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<102> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<101> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<100> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<99> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<98> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<97> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<96> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<95> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<94> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<93> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<92> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<91> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<90> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<89> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<88> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<87> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<86> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<85> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<84> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<83> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<82> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<81> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<80> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<79> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<78> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<77> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<76> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<75> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<74> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<73> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<72> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<71> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<70> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<69> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<68> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<67> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<66> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<65> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<64> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<63> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<62> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<61> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<60> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<59> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<58> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<57> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<56> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<55> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<54> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<53> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<52> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<51> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<50> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<49> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<48> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<47> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<46> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<45> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<44> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<43> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<42> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<41> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<40> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<39> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<38> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<37> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<36> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<35> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<34> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<33> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<32> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<31> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<30> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<29> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<28> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<27> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<26> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<25> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<24> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<23> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<22> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<21> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<20> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<19> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<18> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<17> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<16> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<15> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<14> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<13> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<12> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<11> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<10> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<9> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<8> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<7> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<6> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<5> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<4> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<3> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<2> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<1> VDD VSS / RSC_IHPSG13_FILLCAP8 +XDEC00<10> ADDR_N_I<9> ADDR_N_I<8> CS_I CS04<0> VDD VSS / ++ RM_IHPSG13_8192x32_c4_2P_DEC00 +XDEC00<9> ADDR_N_I<7> ADDR_N_I<6> CS04<1> CS02<4> VDD VSS / ++ RM_IHPSG13_8192x32_c4_2P_DEC00 +XDEC00<8> ADDR_N_I<7> ADDR_N_I<6> CS04<0> CS02<0> VDD VSS / ++ RM_IHPSG13_8192x32_c4_2P_DEC00 +XDEC00<7> ADDR_N_I<5> ADDR_N_I<4> CS02<7> CS00<28> VDD VSS / ++ RM_IHPSG13_8192x32_c4_2P_DEC00 +XDEC00<6> ADDR_N_I<5> ADDR_N_I<4> CS02<6> CS00<24> VDD VSS / ++ RM_IHPSG13_8192x32_c4_2P_DEC00 +XDEC00<5> ADDR_N_I<5> ADDR_N_I<4> CS02<5> CS00<20> VDD VSS / ++ RM_IHPSG13_8192x32_c4_2P_DEC00 +XDEC00<4> ADDR_N_I<5> ADDR_N_I<4> CS02<4> CS00<16> VDD VSS / ++ RM_IHPSG13_8192x32_c4_2P_DEC00 +XDEC00<3> ADDR_N_I<5> ADDR_N_I<4> CS02<3> CS00<12> VDD VSS / ++ RM_IHPSG13_8192x32_c4_2P_DEC00 +XDEC00<2> ADDR_N_I<5> ADDR_N_I<4> CS02<2> CS00<8> VDD VSS / ++ RM_IHPSG13_8192x32_c4_2P_DEC00 +XDEC00<1> ADDR_N_I<5> ADDR_N_I<4> CS02<1> CS00<4> VDD VSS / ++ RM_IHPSG13_8192x32_c4_2P_DEC00 +XDEC00<0> ADDR_N_I<5> ADDR_N_I<4> CS02<0> CS00<0> VDD VSS / ++ RM_IHPSG13_8192x32_c4_2P_DEC00 +XDEC11<9> ADDR_N_I<7> ADDR_N_I<6> CS04<1> CS02<7> VDD VSS / ++ RM_IHPSG13_8192x32_c4_2P_DEC03 +XDEC11<8> ADDR_N_I<7> ADDR_N_I<6> CS04<0> CS02<3> VDD VSS / ++ RM_IHPSG13_8192x32_c4_2P_DEC03 +XDEC11<7> ADDR_N_I<5> ADDR_N_I<4> CS02<7> CS00<31> VDD VSS / ++ RM_IHPSG13_8192x32_c4_2P_DEC03 +XDEC11<6> ADDR_N_I<5> ADDR_N_I<4> CS02<6> CS00<27> VDD VSS / ++ RM_IHPSG13_8192x32_c4_2P_DEC03 +XDEC11<5> ADDR_N_I<5> ADDR_N_I<4> CS02<5> CS00<23> VDD VSS / ++ RM_IHPSG13_8192x32_c4_2P_DEC03 +XDEC11<4> ADDR_N_I<5> ADDR_N_I<4> CS02<4> CS00<19> VDD VSS / ++ RM_IHPSG13_8192x32_c4_2P_DEC03 +XDEC11<3> ADDR_N_I<5> ADDR_N_I<4> CS02<3> CS00<15> VDD VSS / ++ RM_IHPSG13_8192x32_c4_2P_DEC03 +XDEC11<2> ADDR_N_I<5> ADDR_N_I<4> CS02<2> CS00<11> VDD VSS / ++ RM_IHPSG13_8192x32_c4_2P_DEC03 +XDEC11<1> ADDR_N_I<5> ADDR_N_I<4> CS02<1> CS00<7> VDD VSS / ++ RM_IHPSG13_8192x32_c4_2P_DEC03 +XDEC11<0> ADDR_N_I<5> ADDR_N_I<4> CS02<0> CS00<3> VDD VSS / ++ RM_IHPSG13_8192x32_c4_2P_DEC03 +XI0 ADDR_N_I<9> VDD VSS / RSC_IHPSG13_TIEL +.ENDS +.SUBCKT RM_IHPSG13_8192x32_c4_2P_ROWREG9 ACLK_N_I ADDR_I<8> ADDR_I<7> ADDR_I<6> ADDR_I<5> ++ ADDR_I<4> ADDR_I<3> ADDR_I<2> ADDR_I<1> ADDR_I<0> ADDR_N_O<8> ADDR_N_O<7> ++ ADDR_N_O<6> ADDR_N_O<5> ADDR_N_O<4> ADDR_N_O<3> ADDR_N_O<2> ADDR_N_O<1> ++ ADDR_N_O<0> BIST_ADDR_I<8> BIST_ADDR_I<7> BIST_ADDR_I<6> BIST_ADDR_I<5> ++ BIST_ADDR_I<4> BIST_ADDR_I<3> BIST_ADDR_I<2> BIST_ADDR_I<1> BIST_ADDR_I<0> ++ BIST_EN_I VDD VSS +XDFF<8> BIST_EN_I BIST_ADDR_I<8> ACLK_N_I ADDR_I<8> q_int<8> net04<0> VDD ++ VSS / RSC_IHPSG13_DFNQMX2IX1 +XDFF<7> BIST_EN_I BIST_ADDR_I<7> ACLK_N_I ADDR_I<7> q_int<7> net04<1> VDD ++ VSS / RSC_IHPSG13_DFNQMX2IX1 +XDFF<6> BIST_EN_I BIST_ADDR_I<6> ACLK_N_I ADDR_I<6> q_int<6> net04<2> VDD ++ VSS / RSC_IHPSG13_DFNQMX2IX1 +XDFF<5> BIST_EN_I BIST_ADDR_I<5> ACLK_N_I ADDR_I<5> q_int<5> net04<3> VDD ++ VSS / RSC_IHPSG13_DFNQMX2IX1 +XDFF<4> BIST_EN_I BIST_ADDR_I<4> ACLK_N_I ADDR_I<4> q_int<4> net04<4> VDD ++ VSS / RSC_IHPSG13_DFNQMX2IX1 +XDFF<3> BIST_EN_I BIST_ADDR_I<3> ACLK_N_I ADDR_I<3> q_int<3> net04<5> VDD ++ VSS / RSC_IHPSG13_DFNQMX2IX1 +XDFF<2> BIST_EN_I BIST_ADDR_I<2> ACLK_N_I ADDR_I<2> q_int<2> net04<6> VDD ++ VSS / RSC_IHPSG13_DFNQMX2IX1 +XDFF<1> BIST_EN_I BIST_ADDR_I<1> ACLK_N_I ADDR_I<1> q_int<1> net04<7> VDD ++ VSS / RSC_IHPSG13_DFNQMX2IX1 +XDFF<0> BIST_EN_I BIST_ADDR_I<0> ACLK_N_I ADDR_I<0> q_int<0> net04<8> VDD ++ VSS / RSC_IHPSG13_DFNQMX2IX1 +XDRV<8> qn_int<8> ADDR_N_O<8> VDD VSS / RSC_IHPSG13_CINVX8 +XDRV<7> qn_int<7> ADDR_N_O<7> VDD VSS / RSC_IHPSG13_CINVX8 +XDRV<6> qn_int<6> ADDR_N_O<6> VDD VSS / RSC_IHPSG13_CINVX8 +XDRV<5> qn_int<5> ADDR_N_O<5> VDD VSS / RSC_IHPSG13_CINVX8 +XDRV<4> qn_int<4> ADDR_N_O<4> VDD VSS / RSC_IHPSG13_CINVX8 +XDRV<3> qn_int<3> ADDR_N_O<3> VDD VSS / RSC_IHPSG13_CINVX8 +XDRV<2> qn_int<2> ADDR_N_O<2> VDD VSS / RSC_IHPSG13_CINVX8 +XDRV<1> qn_int<1> ADDR_N_O<1> VDD VSS / RSC_IHPSG13_CINVX8 +XDRV<0> qn_int<0> ADDR_N_O<0> VDD VSS / RSC_IHPSG13_CINVX8 +XINV<8> q_int<8> qn_int<8> VDD VSS / RSC_IHPSG13_CINVX2 +XINV<7> q_int<7> qn_int<7> VDD VSS / RSC_IHPSG13_CINVX2 +XINV<6> q_int<6> qn_int<6> VDD VSS / RSC_IHPSG13_CINVX2 +XINV<5> q_int<5> qn_int<5> VDD VSS / RSC_IHPSG13_CINVX2 +XINV<4> q_int<4> qn_int<4> VDD VSS / RSC_IHPSG13_CINVX2 +XINV<3> q_int<3> qn_int<3> VDD VSS / RSC_IHPSG13_CINVX2 +XINV<2> q_int<2> qn_int<2> VDD VSS / RSC_IHPSG13_CINVX2 +XINV<1> q_int<1> qn_int<1> VDD VSS / RSC_IHPSG13_CINVX2 +XINV<0> q_int<0> qn_int<0> VDD VSS / RSC_IHPSG13_CINVX2 +.ENDS + +.SUBCKT RM_IHPSG13_8192x32_c4_2P_DLY_MUX A SEL Z VDD VSS +XI11 net4 Z VDD VSS / RSC_IHPSG13_CINVX2 +XI8 A D<3> SEL net4 VDD VSS / RSC_IHPSG13_MX2IX1 +XI20<3> D<2> D<3> VDD VSS / RSC_IHPSG13_CDLYX1 +XI20<2> D<1> D<2> VDD VSS / RSC_IHPSG13_CDLYX1 +XI20<1> A D<1> VDD VSS / RSC_IHPSG13_CDLYX1 +.ENDS +.SUBCKT RM_IHPSG13_8192x32_c4_2P_CTRL ACLK_N BIST_CK_I BIST_CS_I BIST_EN BIST_RE_I ++ BIST_WE_I B_TIEL_O CK_I CS_I DCLK ECLK PULSE_H PULSE_L PULSE_O RCLK RE_I ++ ROW_CS WCLK WE_I VDD VSS +XI17 ck_regs we col_we VDD VSS / RSC_IHPSG13_DFNQX2 +XI16 ck_regs re col_re VDD VSS / RSC_IHPSG13_DFNQX2 +XI18 ck_regs cs net7 VDD VSS / RSC_IHPSG13_DFNQX2 +XI71 ACLK_N net012 PULSE_O VDD VSS / RSC_IHPSG13_DFNQX2 +XI77 col_we net017 net016 VDD VSS / RSC_IHPSG13_CNAND2X2 +XI76 col_re net017 net018 VDD VSS / RSC_IHPSG13_CNAND2X2 +XI15 ck_dly WEorREandCS aclk VDD VSS / RSC_IHPSG13_CGATEPX4 +XI14 ck WEandCS DCLK VDD VSS / RSC_IHPSG13_CGATEPX4 +XI60 net7 ROW_CS VDD VSS / RSC_IHPSG13_CBUFX8 +XI73 PULSE_O net012 VDD VSS / RSC_IHPSG13_CINVX2 +XI8 net017 net8 VDD VSS / RSC_IHPSG13_CINVX2 +XCAPS4<7> VDD VSS / RSC_IHPSG13_FILLCAP4 +XCAPS4<6> VDD VSS / RSC_IHPSG13_FILLCAP4 +XCAPS4<5> VDD VSS / RSC_IHPSG13_FILLCAP4 +XCAPS4<4> VDD VSS / RSC_IHPSG13_FILLCAP4 +XCAPS4<3> VDD VSS / RSC_IHPSG13_FILLCAP4 +XCAPS4<2> VDD VSS / RSC_IHPSG13_FILLCAP4 +XCAPS4<1> VDD VSS / RSC_IHPSG13_FILLCAP4 +XBM_TIEL B_TIEL_O VDD VSS / RSC_IHPSG13_TIEL +XI64 ck ck_dly VDD VSS / RSC_IHPSG13_CDLYX2 +XI86 CS_I BIST_CS_I BIST_EN cs VDD VSS / RSC_IHPSG13_MX2X2 +XI87 CK_I BIST_CK_I BIST_EN ck VDD VSS / RSC_IHPSG13_MX2X2 +XI85 WE_I BIST_WE_I BIST_EN we VDD VSS / RSC_IHPSG13_MX2X2 +XI84 RE_I BIST_RE_I BIST_EN re VDD VSS / RSC_IHPSG13_MX2X2 +XI48 ck_dly ck_regs VDD VSS / RSC_IHPSG13_CINVX4 +XI81 net016 WCLK VDD VSS / RSC_IHPSG13_CINVX4 +XI80 net018 RCLK VDD VSS / RSC_IHPSG13_CINVX4 +XI78 net8 net020 VDD VSS / RSC_IHPSG13_CINVX4 +XCAPS8<7> VDD VSS / RSC_IHPSG13_FILLCAP8 +XCAPS8<6> VDD VSS / RSC_IHPSG13_FILLCAP8 +XCAPS8<5> VDD VSS / RSC_IHPSG13_FILLCAP8 +XCAPS8<4> VDD VSS / RSC_IHPSG13_FILLCAP8 +XCAPS8<3> VDD VSS / RSC_IHPSG13_FILLCAP8 +XCAPS8<2> VDD VSS / RSC_IHPSG13_FILLCAP8 +XCAPS8<1> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI6 PULSE_L PULSE_H net017 VDD VSS / RSC_IHPSG13_XOR2X2 +XI22 we cs WEandCS VDD VSS / RSC_IHPSG13_AND2X2 +XI79 net020 ECLK VDD VSS / RSC_IHPSG13_CINVX8 +XI63 aclk ACLK_N VDD VSS / RSC_IHPSG13_CINVX8 +XI21 re we cs WEorREandCS VDD VSS / RSC_IHPSG13_OA12X1 +.ENDS +.SUBCKT RM_IHPSG13_8192x32_c4_2P_COLDEC5 ACLK_N ADDR<4> ADDR<3> ADDR<2> ADDR<1> ADDR<0> ++ ADDR_COL<1> ADDR_COL<0> ADDR_DEC<7> ADDR_DEC<6> ADDR_DEC<5> ADDR_DEC<4> ++ ADDR_DEC<3> ADDR_DEC<2> ADDR_DEC<1> ADDR_DEC<0> BIST_ADDR<4> BIST_ADDR<3> ++ BIST_ADDR<2> BIST_ADDR<1> BIST_ADDR<0> BIST_EN_I VDD VSS +XI17<4> VDD VSS / RSC_IHPSG13_FILLCAP4 +XI17<3> VDD VSS / RSC_IHPSG13_FILLCAP4 +XI17<2> VDD VSS / RSC_IHPSG13_FILLCAP4 +XI17<1> VDD VSS / RSC_IHPSG13_FILLCAP4 +XI1<7> PADR<0> PADR<1> PADR<2> addr_n<7> VDD VSS / RSC_IHPSG13_NAND3X2 +XI1<6> NADR<0> PADR<1> PADR<2> addr_n<6> VDD VSS / RSC_IHPSG13_NAND3X2 +XI1<5> PADR<0> NADR<1> PADR<2> addr_n<5> VDD VSS / RSC_IHPSG13_NAND3X2 +XI1<4> NADR<0> NADR<1> PADR<2> addr_n<4> VDD VSS / RSC_IHPSG13_NAND3X2 +XI1<3> PADR<0> PADR<1> NADR<2> addr_n<3> VDD VSS / RSC_IHPSG13_NAND3X2 +XI1<2> NADR<0> PADR<1> NADR<2> addr_n<2> VDD VSS / RSC_IHPSG13_NAND3X2 +XI1<1> PADR<0> NADR<1> NADR<2> addr_n<1> VDD VSS / RSC_IHPSG13_NAND3X2 +XI1<0> NADR<0> NADR<1> NADR<2> addr_n<0> VDD VSS / RSC_IHPSG13_NAND3X2 +XDFF<4> BIST_EN_I BIST_ADDR<4> ACLK_N ADDR<4> addr_int<1> net13<0> VDD ++ VSS / RSC_IHPSG13_DFNQMX2IX1 +XDFF<3> BIST_EN_I BIST_ADDR<3> ACLK_N ADDR<3> addr_int<0> net13<1> VDD ++ VSS / RSC_IHPSG13_DFNQMX2IX1 +XDFF<2> BIST_EN_I BIST_ADDR<2> ACLK_N ADDR<2> padr_int<2> net13<2> VDD ++ VSS / RSC_IHPSG13_DFNQMX2IX1 +XDFF<1> BIST_EN_I BIST_ADDR<1> ACLK_N ADDR<1> padr_int<1> net13<3> VDD ++ VSS / RSC_IHPSG13_DFNQMX2IX1 +XDFF<0> BIST_EN_I BIST_ADDR<0> ACLK_N ADDR<0> padr_int<0> net13<4> VDD ++ VSS / RSC_IHPSG13_DFNQMX2IX1 +XI3<2> padr_int<2> NADR<2> VDD VSS / RSC_IHPSG13_INVX2 +XI3<1> padr_int<1> NADR<1> VDD VSS / RSC_IHPSG13_INVX2 +XI3<0> padr_int<0> NADR<0> VDD VSS / RSC_IHPSG13_INVX2 +XI2<7> addr_n<7> ADDR_DEC<7> VDD VSS / RSC_IHPSG13_INVX2 +XI2<6> addr_n<6> ADDR_DEC<6> VDD VSS / RSC_IHPSG13_INVX2 +XI2<5> addr_n<5> ADDR_DEC<5> VDD VSS / RSC_IHPSG13_INVX2 +XI2<4> addr_n<4> ADDR_DEC<4> VDD VSS / RSC_IHPSG13_INVX2 +XI2<3> addr_n<3> ADDR_DEC<3> VDD VSS / RSC_IHPSG13_INVX2 +XI2<2> addr_n<2> ADDR_DEC<2> VDD VSS / RSC_IHPSG13_INVX2 +XI2<1> addr_n<1> ADDR_DEC<1> VDD VSS / RSC_IHPSG13_INVX2 +XI2<0> addr_n<0> ADDR_DEC<0> VDD VSS / RSC_IHPSG13_INVX2 +XI15<2> NADR<2> PADR<2> VDD VSS / RSC_IHPSG13_INVX2 +XI15<1> NADR<1> PADR<1> VDD VSS / RSC_IHPSG13_INVX2 +XI15<0> NADR<0> PADR<0> VDD VSS / RSC_IHPSG13_INVX2 +XI13<1> addr_int<1> ADDR_COL<1> VDD VSS / RSC_IHPSG13_CBUFX2 +XI13<0> addr_int<0> ADDR_COL<0> VDD VSS / RSC_IHPSG13_CBUFX2 +XI14<5> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI14<4> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI14<3> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI14<2> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI14<1> VDD VSS / RSC_IHPSG13_FILLCAP8 +.ENDS +.SUBCKT RM_IHPSG13_8192x32_c4_2P_BLDRV A_BLC<3> A_BLC<2> A_BLC<1> A_BLC<0> A_BLC_SEL ++ A_BLT<3> A_BLT<2> A_BLT<1> A_BLT<0> A_BLT_SEL A_PRE_N A_SEL_P<3> A_SEL_P<2> ++ A_SEL_P<1> A_SEL_P<0> A_WR_ONE A_WR_ZERO B_BLC<3> B_BLC<2> B_BLC<1> B_BLC<0> ++ B_BLC_SEL B_BLT<3> B_BLT<2> B_BLT<1> B_BLT<0> B_BLT_SEL B_PRE_N B_SEL_P<3> ++ B_SEL_P<2> B_SEL_P<1> B_SEL_P<0> B_WR_ONE B_WR_ZERO VDD VSS +MA_CWN<3> A_BLC<3> A_BLC_NMOS_DRIVE<3> VSS VSS sg13_lv_nmos m=1 ++ w=4.82u l=130.00n ng=2 nrd=0 nrs=0 +MA_CWN<2> A_BLC<2> A_BLC_NMOS_DRIVE<2> VSS VSS sg13_lv_nmos m=1 ++ w=4.82u l=130.00n ng=2 nrd=0 nrs=0 +MA_CWN<1> A_BLC<1> A_BLC_NMOS_DRIVE<1> VSS VSS sg13_lv_nmos m=1 ++ w=4.82u l=130.00n ng=2 nrd=0 nrs=0 +MA_CWN<0> A_BLC<0> A_BLC_NMOS_DRIVE<0> VSS VSS sg13_lv_nmos m=1 ++ w=4.82u l=130.00n ng=2 nrd=0 nrs=0 +MA_TWN<3> A_BLT<3> A_BLT_NMOS_DRIVE<3> VSS VSS sg13_lv_nmos m=1 ++ w=4.82u l=130.00n ng=2 nrd=0 nrs=0 +MA_TWN<2> A_BLT<2> A_BLT_NMOS_DRIVE<2> VSS VSS sg13_lv_nmos m=1 ++ w=4.82u l=130.00n ng=2 nrd=0 nrs=0 +MA_TWN<1> A_BLT<1> A_BLT_NMOS_DRIVE<1> VSS VSS sg13_lv_nmos m=1 ++ w=4.82u l=130.00n ng=2 nrd=0 nrs=0 +MA_TWN<0> A_BLT<0> A_BLT_NMOS_DRIVE<0> VSS VSS sg13_lv_nmos m=1 ++ w=4.82u l=130.00n ng=2 nrd=0 nrs=0 +MB_TWN<3> B_BLT<3> B_BLT_NMOS_DRIVE<3> VSS VSS sg13_lv_nmos m=1 ++ w=4.82u l=130.00n ng=2 nrd=0 nrs=0 +MB_TWN<2> B_BLT<2> B_BLT_NMOS_DRIVE<2> VSS VSS sg13_lv_nmos m=1 ++ w=4.82u l=130.00n ng=2 nrd=0 nrs=0 +MB_TWN<1> B_BLT<1> B_BLT_NMOS_DRIVE<1> VSS VSS sg13_lv_nmos m=1 ++ w=4.82u l=130.00n ng=2 nrd=0 nrs=0 +MB_TWN<0> B_BLT<0> B_BLT_NMOS_DRIVE<0> VSS VSS sg13_lv_nmos m=1 ++ w=4.82u l=130.00n ng=2 nrd=0 nrs=0 +MB_CWN<3> B_BLC<3> B_BLC_NMOS_DRIVE<3> VSS VSS sg13_lv_nmos m=1 ++ w=4.82u l=130.00n ng=2 nrd=0 nrs=0 +MB_CWN<2> B_BLC<2> B_BLC_NMOS_DRIVE<2> VSS VSS sg13_lv_nmos m=1 ++ w=4.82u l=130.00n ng=2 nrd=0 nrs=0 +MB_CWN<1> B_BLC<1> B_BLC_NMOS_DRIVE<1> VSS VSS sg13_lv_nmos m=1 ++ w=4.82u l=130.00n ng=2 nrd=0 nrs=0 +MB_CWN<0> B_BLC<0> B_BLC_NMOS_DRIVE<0> VSS VSS sg13_lv_nmos m=1 ++ w=4.82u l=130.00n ng=2 nrd=0 nrs=0 +MA_CPR<3> A_BLC<3> A_PRE_N VDD VDD sg13_lv_pmos m=1 w=3.000u l=130.00n ++ ng=2 nrd=0 nrs=0 +MA_CPR<2> A_BLC<2> A_PRE_N VDD VDD sg13_lv_pmos m=1 w=3.000u l=130.00n ++ ng=2 nrd=0 nrs=0 +MA_CPR<1> A_BLC<1> A_PRE_N VDD VDD sg13_lv_pmos m=1 w=3.000u l=130.00n ++ ng=2 nrd=0 nrs=0 +MA_CPR<0> A_BLC<0> A_PRE_N VDD VDD sg13_lv_pmos m=1 w=3.000u l=130.00n ++ ng=2 nrd=0 nrs=0 +MA_TWP<3> A_BLT<3> A_BLT_PMOS_DRIVE<3> VDD VDD sg13_lv_pmos m=1 w=1.5u ++ l=130.00n ng=1 nrd=0 nrs=0 +MA_TWP<2> A_BLT<2> A_BLT_PMOS_DRIVE<2> VDD VDD sg13_lv_pmos m=1 w=1.5u ++ l=130.00n ng=1 nrd=0 nrs=0 +MA_TWP<1> A_BLT<1> A_BLT_PMOS_DRIVE<1> VDD VDD sg13_lv_pmos m=1 w=1.5u ++ l=130.00n ng=1 nrd=0 nrs=0 +MA_TWP<0> A_BLT<0> A_BLT_PMOS_DRIVE<0> VDD VDD sg13_lv_pmos m=1 w=1.5u ++ l=130.00n ng=1 nrd=0 nrs=0 +MA_CWP<3> A_BLC<3> A_BLC_PMOS_DRIVE<3> VDD VDD sg13_lv_pmos m=1 w=1.5u ++ l=130.00n ng=1 nrd=0 nrs=0 +MA_CWP<2> A_BLC<2> A_BLC_PMOS_DRIVE<2> VDD VDD sg13_lv_pmos m=1 w=1.5u ++ l=130.00n ng=1 nrd=0 nrs=0 +MA_CWP<1> A_BLC<1> A_BLC_PMOS_DRIVE<1> VDD VDD sg13_lv_pmos m=1 w=1.5u ++ l=130.00n ng=1 nrd=0 nrs=0 +MA_CWP<0> A_BLC<0> A_BLC_PMOS_DRIVE<0> VDD VDD sg13_lv_pmos m=1 w=1.5u ++ l=130.00n ng=1 nrd=0 nrs=0 +MA_TPR<3> A_BLT<3> A_PRE_N VDD VDD sg13_lv_pmos m=1 w=3.000u l=130.00n ++ ng=2 nrd=0 nrs=0 +MA_TPR<2> A_BLT<2> A_PRE_N VDD VDD sg13_lv_pmos m=1 w=3.000u l=130.00n ++ ng=2 nrd=0 nrs=0 +MA_TPR<1> A_BLT<1> A_PRE_N VDD VDD sg13_lv_pmos m=1 w=3.000u l=130.00n ++ ng=2 nrd=0 nrs=0 +MA_TPR<0> A_BLT<0> A_PRE_N VDD VDD sg13_lv_pmos m=1 w=3.000u l=130.00n ++ ng=2 nrd=0 nrs=0 +MA_TSP<3> A_BLT_SEL A_SEL_N<3> A_BLT<3> VDD sg13_lv_pmos m=1 w=1.5u ++ l=130.00n ng=1 nrd=0 nrs=0 +MA_TSP<2> A_BLT_SEL A_SEL_N<2> A_BLT<2> VDD sg13_lv_pmos m=1 w=1.5u ++ l=130.00n ng=1 nrd=0 nrs=0 +MA_TSP<1> A_BLT_SEL A_SEL_N<1> A_BLT<1> VDD sg13_lv_pmos m=1 w=1.5u ++ l=130.00n ng=1 nrd=0 nrs=0 +MA_TSP<0> A_BLT_SEL A_SEL_N<0> A_BLT<0> VDD sg13_lv_pmos m=1 w=1.5u ++ l=130.00n ng=1 nrd=0 nrs=0 +MA_CSP<3> A_BLC_SEL A_SEL_N<3> A_BLC<3> VDD sg13_lv_pmos m=1 w=1.5u ++ l=130.00n ng=1 nrd=0 nrs=0 +MA_CSP<2> A_BLC_SEL A_SEL_N<2> A_BLC<2> VDD sg13_lv_pmos m=1 w=1.5u ++ l=130.00n ng=1 nrd=0 nrs=0 +MA_CSP<1> A_BLC_SEL A_SEL_N<1> A_BLC<1> VDD sg13_lv_pmos m=1 w=1.5u ++ l=130.00n ng=1 nrd=0 nrs=0 +MA_CSP<0> A_BLC_SEL A_SEL_N<0> A_BLC<0> VDD sg13_lv_pmos m=1 w=1.5u ++ l=130.00n ng=1 nrd=0 nrs=0 +MB_CWP<3> B_BLC<3> B_BLC_PMOS_DRIVE<3> VDD VDD sg13_lv_pmos m=1 w=1.5u ++ l=130.00n ng=1 nrd=0 nrs=0 +MB_CWP<2> B_BLC<2> B_BLC_PMOS_DRIVE<2> VDD VDD sg13_lv_pmos m=1 w=1.5u ++ l=130.00n ng=1 nrd=0 nrs=0 +MB_CWP<1> B_BLC<1> B_BLC_PMOS_DRIVE<1> VDD VDD sg13_lv_pmos m=1 w=1.5u ++ l=130.00n ng=1 nrd=0 nrs=0 +MB_CWP<0> B_BLC<0> B_BLC_PMOS_DRIVE<0> VDD VDD sg13_lv_pmos m=1 w=1.5u ++ l=130.00n ng=1 nrd=0 nrs=0 +MB_TWP<3> B_BLT<3> B_BLT_PMOS_DRIVE<3> VDD VDD sg13_lv_pmos m=1 w=1.5u ++ l=130.00n ng=1 nrd=0 nrs=0 +MB_TWP<2> B_BLT<2> B_BLT_PMOS_DRIVE<2> VDD VDD sg13_lv_pmos m=1 w=1.5u ++ l=130.00n ng=1 nrd=0 nrs=0 +MB_TWP<1> B_BLT<1> B_BLT_PMOS_DRIVE<1> VDD VDD sg13_lv_pmos m=1 w=1.5u ++ l=130.00n ng=1 nrd=0 nrs=0 +MB_TWP<0> B_BLT<0> B_BLT_PMOS_DRIVE<0> VDD VDD sg13_lv_pmos m=1 w=1.5u ++ l=130.00n ng=1 nrd=0 nrs=0 +MB_TSP<3> B_BLT_SEL B_SEL_N<3> B_BLT<3> VDD sg13_lv_pmos m=1 w=1.5u ++ l=130.00n ng=1 nrd=0 nrs=0 +MB_TSP<2> B_BLT_SEL B_SEL_N<2> B_BLT<2> VDD sg13_lv_pmos m=1 w=1.5u ++ l=130.00n ng=1 nrd=0 nrs=0 +MB_TSP<1> B_BLT_SEL B_SEL_N<1> B_BLT<1> VDD sg13_lv_pmos m=1 w=1.5u ++ l=130.00n ng=1 nrd=0 nrs=0 +MB_TSP<0> B_BLT_SEL B_SEL_N<0> B_BLT<0> VDD sg13_lv_pmos m=1 w=1.5u ++ l=130.00n ng=1 nrd=0 nrs=0 +MB_TPR<3> B_BLT<3> B_PRE_N VDD VDD sg13_lv_pmos m=1 w=3.000u l=130.00n ++ ng=2 nrd=0 nrs=0 +MB_TPR<2> B_BLT<2> B_PRE_N VDD VDD sg13_lv_pmos m=1 w=3.000u l=130.00n ++ ng=2 nrd=0 nrs=0 +MB_TPR<1> B_BLT<1> B_PRE_N VDD VDD sg13_lv_pmos m=1 w=3.000u l=130.00n ++ ng=2 nrd=0 nrs=0 +MB_TPR<0> B_BLT<0> B_PRE_N VDD VDD sg13_lv_pmos m=1 w=3.000u l=130.00n ++ ng=2 nrd=0 nrs=0 +MB_CSP<3> B_BLC_SEL B_SEL_N<3> B_BLC<3> VDD sg13_lv_pmos m=1 w=1.5u ++ l=130.00n ng=1 nrd=0 nrs=0 +MB_CSP<2> B_BLC_SEL B_SEL_N<2> B_BLC<2> VDD sg13_lv_pmos m=1 w=1.5u ++ l=130.00n ng=1 nrd=0 nrs=0 +MB_CSP<1> B_BLC_SEL B_SEL_N<1> B_BLC<1> VDD sg13_lv_pmos m=1 w=1.5u ++ l=130.00n ng=1 nrd=0 nrs=0 +MB_CSP<0> B_BLC_SEL B_SEL_N<0> B_BLC<0> VDD sg13_lv_pmos m=1 w=1.5u ++ l=130.00n ng=1 nrd=0 nrs=0 +MB_CPR<3> B_BLC<3> B_PRE_N VDD VDD sg13_lv_pmos m=1 w=3.000u l=130.00n ++ ng=2 nrd=0 nrs=0 +MB_CPR<2> B_BLC<2> B_PRE_N VDD VDD sg13_lv_pmos m=1 w=3.000u l=130.00n ++ ng=2 nrd=0 nrs=0 +MB_CPR<1> B_BLC<1> B_PRE_N VDD VDD sg13_lv_pmos m=1 w=3.000u l=130.00n ++ ng=2 nrd=0 nrs=0 +MB_CPR<0> B_BLC<0> B_PRE_N VDD VDD sg13_lv_pmos m=1 w=3.000u l=130.00n ++ ng=2 nrd=0 nrs=0 +XA_SEL<3> A_SEL_P<3> A_SEL_N<3> VDD VSS / RSC_IHPSG13_INVX2 +XA_SEL<2> A_SEL_P<2> A_SEL_N<2> VDD VSS / RSC_IHPSG13_INVX2 +XA_SEL<1> A_SEL_P<1> A_SEL_N<1> VDD VSS / RSC_IHPSG13_INVX2 +XA_SEL<0> A_SEL_P<0> A_SEL_N<0> VDD VSS / RSC_IHPSG13_INVX2 +XA_CINV<3> A_BLT_PMOS_DRIVE<3> A_BLC_NMOS_DRIVE<3> VDD VSS / ++ RSC_IHPSG13_INVX2 +XA_CINV<2> A_BLT_PMOS_DRIVE<2> A_BLC_NMOS_DRIVE<2> VDD VSS / ++ RSC_IHPSG13_INVX2 +XA_CINV<1> A_BLT_PMOS_DRIVE<1> A_BLC_NMOS_DRIVE<1> VDD VSS / ++ RSC_IHPSG13_INVX2 +XA_CINV<0> A_BLT_PMOS_DRIVE<0> A_BLC_NMOS_DRIVE<0> VDD VSS / ++ RSC_IHPSG13_INVX2 +XA_TINV<3> A_BLC_PMOS_DRIVE<3> A_BLT_NMOS_DRIVE<3> VDD VSS / ++ RSC_IHPSG13_INVX2 +XA_TINV<2> A_BLC_PMOS_DRIVE<2> A_BLT_NMOS_DRIVE<2> VDD VSS / ++ RSC_IHPSG13_INVX2 +XA_TINV<1> A_BLC_PMOS_DRIVE<1> A_BLT_NMOS_DRIVE<1> VDD VSS / ++ RSC_IHPSG13_INVX2 +XA_TINV<0> A_BLC_PMOS_DRIVE<0> A_BLT_NMOS_DRIVE<0> VDD VSS / ++ RSC_IHPSG13_INVX2 +XB_SEL<3> B_SEL_P<3> B_SEL_N<3> VDD VSS / RSC_IHPSG13_INVX2 +XB_SEL<2> B_SEL_P<2> B_SEL_N<2> VDD VSS / RSC_IHPSG13_INVX2 +XB_SEL<1> B_SEL_P<1> B_SEL_N<1> VDD VSS / RSC_IHPSG13_INVX2 +XB_SEL<0> B_SEL_P<0> B_SEL_N<0> VDD VSS / RSC_IHPSG13_INVX2 +XB_TINV<3> B_BLC_PMOS_DRIVE<3> B_BLT_NMOS_DRIVE<3> VDD VSS / ++ RSC_IHPSG13_INVX2 +XB_TINV<2> B_BLC_PMOS_DRIVE<2> B_BLT_NMOS_DRIVE<2> VDD VSS / ++ RSC_IHPSG13_INVX2 +XB_TINV<1> B_BLC_PMOS_DRIVE<1> B_BLT_NMOS_DRIVE<1> VDD VSS / ++ RSC_IHPSG13_INVX2 +XB_TINV<0> B_BLC_PMOS_DRIVE<0> B_BLT_NMOS_DRIVE<0> VDD VSS / ++ RSC_IHPSG13_INVX2 +XB_CINV<3> B_BLT_PMOS_DRIVE<3> B_BLC_NMOS_DRIVE<3> VDD VSS / ++ RSC_IHPSG13_INVX2 +XB_CINV<2> B_BLT_PMOS_DRIVE<2> B_BLC_NMOS_DRIVE<2> VDD VSS / ++ RSC_IHPSG13_INVX2 +XB_CINV<1> B_BLT_PMOS_DRIVE<1> B_BLC_NMOS_DRIVE<1> VDD VSS / ++ RSC_IHPSG13_INVX2 +XB_CINV<0> B_BLT_PMOS_DRIVE<0> B_BLC_NMOS_DRIVE<0> VDD VSS / ++ RSC_IHPSG13_INVX2 +XA_TDEC<3> A_SEL_P<3> A_WR_ONE A_BLT_PMOS_DRIVE<3> VDD VSS / ++ RSC_IHPSG13_NAND2X2 +XA_TDEC<2> A_SEL_P<2> A_WR_ONE A_BLT_PMOS_DRIVE<2> VDD VSS / ++ RSC_IHPSG13_NAND2X2 +XA_TDEC<1> A_SEL_P<1> A_WR_ONE A_BLT_PMOS_DRIVE<1> VDD VSS / ++ RSC_IHPSG13_NAND2X2 +XA_TDEC<0> A_SEL_P<0> A_WR_ONE A_BLT_PMOS_DRIVE<0> VDD VSS / ++ RSC_IHPSG13_NAND2X2 +XA_CDEC<3> A_SEL_P<3> A_WR_ZERO A_BLC_PMOS_DRIVE<3> VDD VSS / ++ RSC_IHPSG13_NAND2X2 +XA_CDEC<2> A_SEL_P<2> A_WR_ZERO A_BLC_PMOS_DRIVE<2> VDD VSS / ++ RSC_IHPSG13_NAND2X2 +XA_CDEC<1> A_SEL_P<1> A_WR_ZERO A_BLC_PMOS_DRIVE<1> VDD VSS / ++ RSC_IHPSG13_NAND2X2 +XA_CDEC<0> A_SEL_P<0> A_WR_ZERO A_BLC_PMOS_DRIVE<0> VDD VSS / ++ RSC_IHPSG13_NAND2X2 +XB_CDEC<3> B_SEL_P<3> B_WR_ZERO B_BLC_PMOS_DRIVE<3> VDD VSS / ++ RSC_IHPSG13_NAND2X2 +XB_CDEC<2> B_SEL_P<2> B_WR_ZERO B_BLC_PMOS_DRIVE<2> VDD VSS / ++ RSC_IHPSG13_NAND2X2 +XB_CDEC<1> B_SEL_P<1> B_WR_ZERO B_BLC_PMOS_DRIVE<1> VDD VSS / ++ RSC_IHPSG13_NAND2X2 +XB_CDEC<0> B_SEL_P<0> B_WR_ZERO B_BLC_PMOS_DRIVE<0> VDD VSS / ++ RSC_IHPSG13_NAND2X2 +XB_TDEC<3> B_SEL_P<3> B_WR_ONE B_BLT_PMOS_DRIVE<3> VDD VSS / ++ RSC_IHPSG13_NAND2X2 +XB_TDEC<2> B_SEL_P<2> B_WR_ONE B_BLT_PMOS_DRIVE<2> VDD VSS / ++ RSC_IHPSG13_NAND2X2 +XB_TDEC<1> B_SEL_P<1> B_WR_ONE B_BLT_PMOS_DRIVE<1> VDD VSS / ++ RSC_IHPSG13_NAND2X2 +XB_TDEC<0> B_SEL_P<0> B_WR_ONE B_BLT_PMOS_DRIVE<0> VDD VSS / ++ RSC_IHPSG13_NAND2X2 +.ENDS +.SUBCKT RSC_IHPSG13_AND2X6 A B Z VDD VSS +MN3 Z net6 VSS VSS sg13_lv_nmos m=1 w=2.94u l=130.00n ng=3 nrd=0 nrs=0 +MN4 net9 B VSS VSS sg13_lv_nmos m=1 w=500.0n l=130.00n ng=1 nrd=0 nrs=0 +MN6 net6 A net9 VSS sg13_lv_nmos m=1 w=500.0n l=130.00n ng=1 nrd=0 nrs=0 +MP2 Z net6 VDD VDD sg13_lv_pmos m=1 w=4.86u l=130.00n ng=3 nrd=0 nrs=0 +MP0 net6 B VDD VDD sg13_lv_pmos m=1 w=860.00n l=130.00n ng=1 nrd=0 ++ nrs=0 +MP1 net6 A VDD VDD sg13_lv_pmos m=1 w=860.00n l=130.00n ng=1 nrd=0 ++ nrs=0 +.ENDS +.SUBCKT RM_IHPSG13_8192x32_c4_2P_COLCTRL5 A_ADDR_COL<1> A_ADDR_COL<0> A_ADDR_DEC<7> ++ A_ADDR_DEC<6> A_ADDR_DEC<5> A_ADDR_DEC<4> A_ADDR_DEC<3> A_ADDR_DEC<2> ++ A_ADDR_DEC<1> A_ADDR_DEC<0> A_BIST_BM_I A_BIST_DW_I A_BIST_EN_I A_BLC<31> ++ A_BLC<30> A_BLC<29> A_BLC<28> A_BLC<27> A_BLC<26> A_BLC<25> A_BLC<24> ++ A_BLC<23> A_BLC<22> A_BLC<21> A_BLC<20> A_BLC<19> A_BLC<18> A_BLC<17> ++ A_BLC<16> A_BLC<15> A_BLC<14> A_BLC<13> A_BLC<12> A_BLC<11> A_BLC<10> ++ A_BLC<9> A_BLC<8> A_BLC<7> A_BLC<6> A_BLC<5> A_BLC<4> A_BLC<3> A_BLC<2> ++ A_BLC<1> A_BLC<0> A_BLT<31> A_BLT<30> A_BLT<29> A_BLT<28> A_BLT<27> ++ A_BLT<26> A_BLT<25> A_BLT<24> A_BLT<23> A_BLT<22> A_BLT<21> A_BLT<20> ++ A_BLT<19> A_BLT<18> A_BLT<17> A_BLT<16> A_BLT<15> A_BLT<14> A_BLT<13> ++ A_BLT<12> A_BLT<11> A_BLT<10> A_BLT<9> A_BLT<8> A_BLT<7> A_BLT<6> A_BLT<5> ++ A_BLT<4> A_BLT<3> A_BLT<2> A_BLT<1> A_BLT<0> A_BM_I A_DCLK_B_L A_DCLK_B_R ++ A_DCLK_L A_DCLK_R A_DR_O A_DW_I A_RCLK_B_L A_RCLK_B_R A_RCLK_L A_RCLK_R ++ A_TIEH_O A_WCLK_B_L A_WCLK_B_R A_WCLK_L A_WCLK_R B_ADDR_COL<1> B_ADDR_COL<0> ++ B_ADDR_DEC<7> B_ADDR_DEC<6> B_ADDR_DEC<5> B_ADDR_DEC<4> B_ADDR_DEC<3> ++ B_ADDR_DEC<2> B_ADDR_DEC<1> B_ADDR_DEC<0> B_BIST_BM_I B_BIST_DW_I ++ B_BIST_EN_I B_BLC<31> B_BLC<30> B_BLC<29> B_BLC<28> B_BLC<27> B_BLC<26> ++ B_BLC<25> B_BLC<24> B_BLC<23> B_BLC<22> B_BLC<21> B_BLC<20> B_BLC<19> ++ B_BLC<18> B_BLC<17> B_BLC<16> B_BLC<15> B_BLC<14> B_BLC<13> B_BLC<12> ++ B_BLC<11> B_BLC<10> B_BLC<9> B_BLC<8> B_BLC<7> B_BLC<6> B_BLC<5> B_BLC<4> ++ B_BLC<3> B_BLC<2> B_BLC<1> B_BLC<0> B_BLT<31> B_BLT<30> B_BLT<29> B_BLT<28> ++ B_BLT<27> B_BLT<26> B_BLT<25> B_BLT<24> B_BLT<23> B_BLT<22> B_BLT<21> ++ B_BLT<20> B_BLT<19> B_BLT<18> B_BLT<17> B_BLT<16> B_BLT<15> B_BLT<14> ++ B_BLT<13> B_BLT<12> B_BLT<11> B_BLT<10> B_BLT<9> B_BLT<8> B_BLT<7> B_BLT<6> ++ B_BLT<5> B_BLT<4> B_BLT<3> B_BLT<2> B_BLT<1> B_BLT<0> B_BM_I B_DCLK_B_L ++ B_DCLK_B_R B_DCLK_L B_DCLK_R B_DR_O B_DW_I B_RCLK_B_L B_RCLK_B_R B_RCLK_L ++ B_RCLK_R B_TIEH_O B_WCLK_B_L B_WCLK_B_R B_WCLK_L B_WCLK_R VDD VSS +XB_I80<1> B_WCLK_B_L B_RCLK_B_L B_W_nor_R<1> VDD VSS / ++ RSC_IHPSG13_AND2X2 +XB_I80<0> B_WCLK_B_L B_RCLK_B_L B_W_nor_R<0> VDD VSS / ++ RSC_IHPSG13_AND2X2 +XA_I80<1> A_WCLK_B_L A_RCLK_B_L A_W_nor_R<1> VDD VSS / ++ RSC_IHPSG13_AND2X2 +XA_I80<0> A_WCLK_B_L A_RCLK_B_L A_W_nor_R<0> VDD VSS / ++ RSC_IHPSG13_AND2X2 +XB_I44 B_BM_N B_WCLK_B_L B_DO_WRITE_P VDD VSS / RSC_IHPSG13_NOR2X2 +XA_I44 A_BM_N A_WCLK_B_L A_DO_WRITE_P VDD VSS / RSC_IHPSG13_NOR2X2 +XI_FILL4<16> VDD VSS / RSC_IHPSG13_FILLCAP4 +XI_FILL4<15> VDD VSS / RSC_IHPSG13_FILLCAP4 +XI_FILL4<14> VDD VSS / RSC_IHPSG13_FILLCAP4 +XI_FILL4<13> VDD VSS / RSC_IHPSG13_FILLCAP4 +XI_FILL4<12> VDD VSS / RSC_IHPSG13_FILLCAP4 +XI_FILL4<11> VDD VSS / RSC_IHPSG13_FILLCAP4 +XI_FILL4<10> VDD VSS / RSC_IHPSG13_FILLCAP4 +XI_FILL4<9> VDD VSS / RSC_IHPSG13_FILLCAP4 +XI_FILL4<8> VDD VSS / RSC_IHPSG13_FILLCAP4 +XI_FILL4<7> VDD VSS / RSC_IHPSG13_FILLCAP4 +XI_FILL4<6> VDD VSS / RSC_IHPSG13_FILLCAP4 +XI_FILL4<5> VDD VSS / RSC_IHPSG13_FILLCAP4 +XI_FILL4<4> VDD VSS / RSC_IHPSG13_FILLCAP4 +XI_FILL4<3> VDD VSS / RSC_IHPSG13_FILLCAP4 +XI_FILL4<2> VDD VSS / RSC_IHPSG13_FILLCAP4 +XI_FILL4<1> VDD VSS / RSC_IHPSG13_FILLCAP4 +XB_INV<6> B_N1<1> B_P1<1> VDD VSS / RSC_IHPSG13_CINVX4 +XB_INV<5> B_N0<1> B_P0<1> VDD VSS / RSC_IHPSG13_CINVX4 +XB_INV<4> B_N0<0> B_P0<0> VDD VSS / RSC_IHPSG13_CINVX4 +XB_INV<3> B_ADDR_COL<1> B_N1<1> VDD VSS / RSC_IHPSG13_CINVX4 +XB_INV<2> B_ADDR_COL<1> B_N1<0> VDD VSS / RSC_IHPSG13_CINVX4 +XB_INV<1> B_ADDR_COL<0> B_N0<1> VDD VSS / RSC_IHPSG13_CINVX4 +XB_INV<0> B_ADDR_COL<0> B_N0<0> VDD VSS / RSC_IHPSG13_CINVX4 +XA_INV<6> A_N1<1> A_P1<1> VDD VSS / RSC_IHPSG13_CINVX4 +XA_INV<5> A_N0<1> A_P0<1> VDD VSS / RSC_IHPSG13_CINVX4 +XA_INV<4> A_N0<0> A_P0<0> VDD VSS / RSC_IHPSG13_CINVX4 +XA_INV<3> A_ADDR_COL<1> A_N1<1> VDD VSS / RSC_IHPSG13_CINVX4 +XA_INV<2> A_ADDR_COL<1> A_N1<0> VDD VSS / RSC_IHPSG13_CINVX4 +XA_INV<1> A_ADDR_COL<0> A_N0<1> VDD VSS / RSC_IHPSG13_CINVX4 +XA_INV<0> A_ADDR_COL<0> A_N0<0> VDD VSS / RSC_IHPSG13_CINVX4 +XB_I81<3> B_W_nor_R<1> B_PRE_N VDD VSS / RSC_IHPSG13_CINVX4_WN +XB_I81<2> B_W_nor_R<1> B_PRE_N VDD VSS / RSC_IHPSG13_CINVX4_WN +XB_I81<1> B_W_nor_R<0> B_PRE_N VDD VSS / RSC_IHPSG13_CINVX4_WN +XB_I81<0> B_W_nor_R<0> B_PRE_N VDD VSS / RSC_IHPSG13_CINVX4_WN +XA_I81<3> A_W_nor_R<1> A_PRE_N VDD VSS / RSC_IHPSG13_CINVX4_WN +XA_I81<2> A_W_nor_R<1> A_PRE_N VDD VSS / RSC_IHPSG13_CINVX4_WN +XA_I81<1> A_W_nor_R<0> A_PRE_N VDD VSS / RSC_IHPSG13_CINVX4_WN +XA_I81<0> A_W_nor_R<0> A_PRE_N VDD VSS / RSC_IHPSG13_CINVX4_WN +XI_FILL8<78> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI_FILL8<77> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI_FILL8<76> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI_FILL8<75> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI_FILL8<74> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI_FILL8<73> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI_FILL8<72> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI_FILL8<71> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI_FILL8<70> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI_FILL8<69> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI_FILL8<68> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI_FILL8<67> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI_FILL8<66> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI_FILL8<65> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI_FILL8<64> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI_FILL8<63> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI_FILL8<62> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI_FILL8<61> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI_FILL8<60> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI_FILL8<59> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI_FILL8<58> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI_FILL8<57> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI_FILL8<56> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI_FILL8<55> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI_FILL8<54> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI_FILL8<53> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI_FILL8<52> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI_FILL8<51> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI_FILL8<50> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI_FILL8<49> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI_FILL8<48> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI_FILL8<47> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI_FILL8<46> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI_FILL8<45> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI_FILL8<44> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI_FILL8<43> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI_FILL8<42> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI_FILL8<41> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI_FILL8<40> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI_FILL8<39> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI_FILL8<38> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI_FILL8<37> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI_FILL8<36> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI_FILL8<35> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI_FILL8<34> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI_FILL8<33> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI_FILL8<32> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI_FILL8<31> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI_FILL8<30> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI_FILL8<29> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI_FILL8<28> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI_FILL8<27> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI_FILL8<26> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI_FILL8<25> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI_FILL8<24> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI_FILL8<23> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI_FILL8<22> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI_FILL8<21> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI_FILL8<20> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI_FILL8<19> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI_FILL8<18> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI_FILL8<17> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI_FILL8<16> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI_FILL8<15> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI_FILL8<14> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI_FILL8<13> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI_FILL8<12> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI_FILL8<11> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI_FILL8<10> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI_FILL8<9> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI_FILL8<8> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI_FILL8<7> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI_FILL8<6> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI_FILL8<5> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI_FILL8<4> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI_FILL8<3> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI_FILL8<2> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI_FILL8<1> VDD VSS / RSC_IHPSG13_FILLCAP8 +XAB_BLMUX<7> A_BLC<31> A_BLC<30> A_BLC<29> A_BLC<28> A_BLC_SEL A_BLT<31> ++ A_BLT<30> A_BLT<29> A_BLT<28> A_BLT_SEL A_PRE_N A_SEL_P<31> A_SEL_P<30> ++ A_SEL_P<29> A_SEL_P<28> A_WR_ONE A_WR_ZERO B_BLC<31> B_BLC<30> B_BLC<29> ++ B_BLC<28> B_BLC_SEL B_BLT<31> B_BLT<30> B_BLT<29> B_BLT<28> B_BLT_SEL ++ B_PRE_N B_SEL_P<31> B_SEL_P<30> B_SEL_P<29> B_SEL_P<28> B_WR_ONE B_WR_ZERO ++ VDD VSS / RM_IHPSG13_8192x32_c4_2P_BLDRV +XAB_BLMUX<6> A_BLC<27> A_BLC<26> A_BLC<25> A_BLC<24> A_BLC_SEL A_BLT<27> ++ A_BLT<26> A_BLT<25> A_BLT<24> A_BLT_SEL A_PRE_N A_SEL_P<27> A_SEL_P<26> ++ A_SEL_P<25> A_SEL_P<24> A_WR_ONE A_WR_ZERO B_BLC<27> B_BLC<26> B_BLC<25> ++ B_BLC<24> B_BLC_SEL B_BLT<27> B_BLT<26> B_BLT<25> B_BLT<24> B_BLT_SEL ++ B_PRE_N B_SEL_P<27> B_SEL_P<26> B_SEL_P<25> B_SEL_P<24> B_WR_ONE B_WR_ZERO ++ VDD VSS / RM_IHPSG13_8192x32_c4_2P_BLDRV +XAB_BLMUX<5> A_BLC<23> A_BLC<22> A_BLC<21> A_BLC<20> A_BLC_SEL A_BLT<23> ++ A_BLT<22> A_BLT<21> A_BLT<20> A_BLT_SEL A_PRE_N A_SEL_P<23> A_SEL_P<22> ++ A_SEL_P<21> A_SEL_P<20> A_WR_ONE A_WR_ZERO B_BLC<23> B_BLC<22> B_BLC<21> ++ B_BLC<20> B_BLC_SEL B_BLT<23> B_BLT<22> B_BLT<21> B_BLT<20> B_BLT_SEL ++ B_PRE_N B_SEL_P<23> B_SEL_P<22> B_SEL_P<21> B_SEL_P<20> B_WR_ONE B_WR_ZERO ++ VDD VSS / RM_IHPSG13_8192x32_c4_2P_BLDRV +XAB_BLMUX<4> A_BLC<19> A_BLC<18> A_BLC<17> A_BLC<16> A_BLC_SEL A_BLT<19> ++ A_BLT<18> A_BLT<17> A_BLT<16> A_BLT_SEL A_PRE_N A_SEL_P<19> A_SEL_P<18> ++ A_SEL_P<17> A_SEL_P<16> A_WR_ONE A_WR_ZERO B_BLC<19> B_BLC<18> B_BLC<17> ++ B_BLC<16> B_BLC_SEL B_BLT<19> B_BLT<18> B_BLT<17> B_BLT<16> B_BLT_SEL ++ B_PRE_N B_SEL_P<19> B_SEL_P<18> B_SEL_P<17> B_SEL_P<16> B_WR_ONE B_WR_ZERO ++ VDD VSS / RM_IHPSG13_8192x32_c4_2P_BLDRV +XAB_BLMUX<3> A_BLC<15> A_BLC<14> A_BLC<13> A_BLC<12> A_BLC_SEL A_BLT<15> ++ A_BLT<14> A_BLT<13> A_BLT<12> A_BLT_SEL A_PRE_N A_SEL_P<15> A_SEL_P<14> ++ A_SEL_P<13> A_SEL_P<12> A_WR_ONE A_WR_ZERO B_BLC<15> B_BLC<14> B_BLC<13> ++ B_BLC<12> B_BLC_SEL B_BLT<15> B_BLT<14> B_BLT<13> B_BLT<12> B_BLT_SEL ++ B_PRE_N B_SEL_P<15> B_SEL_P<14> B_SEL_P<13> B_SEL_P<12> B_WR_ONE B_WR_ZERO ++ VDD VSS / RM_IHPSG13_8192x32_c4_2P_BLDRV +XAB_BLMUX<2> A_BLC<11> A_BLC<10> A_BLC<9> A_BLC<8> A_BLC_SEL A_BLT<11> ++ A_BLT<10> A_BLT<9> A_BLT<8> A_BLT_SEL A_PRE_N A_SEL_P<11> A_SEL_P<10> ++ A_SEL_P<9> A_SEL_P<8> A_WR_ONE A_WR_ZERO B_BLC<11> B_BLC<10> B_BLC<9> ++ B_BLC<8> B_BLC_SEL B_BLT<11> B_BLT<10> B_BLT<9> B_BLT<8> B_BLT_SEL B_PRE_N ++ B_SEL_P<11> B_SEL_P<10> B_SEL_P<9> B_SEL_P<8> B_WR_ONE B_WR_ZERO VDD ++ VSS / RM_IHPSG13_8192x32_c4_2P_BLDRV +XAB_BLMUX<1> A_BLC<7> A_BLC<6> A_BLC<5> A_BLC<4> A_BLC_SEL A_BLT<7> A_BLT<6> ++ A_BLT<5> A_BLT<4> A_BLT_SEL A_PRE_N A_SEL_P<7> A_SEL_P<6> A_SEL_P<5> ++ A_SEL_P<4> A_WR_ONE A_WR_ZERO B_BLC<7> B_BLC<6> B_BLC<5> B_BLC<4> B_BLC_SEL ++ B_BLT<7> B_BLT<6> B_BLT<5> B_BLT<4> B_BLT_SEL B_PRE_N B_SEL_P<7> B_SEL_P<6> ++ B_SEL_P<5> B_SEL_P<4> B_WR_ONE B_WR_ZERO VDD VSS / ++ RM_IHPSG13_8192x32_c4_2P_BLDRV +XAB_BLMUX<0> A_BLC<3> A_BLC<2> A_BLC<1> A_BLC<0> A_BLC_SEL A_BLT<3> A_BLT<2> ++ A_BLT<1> A_BLT<0> A_BLT_SEL A_PRE_N A_SEL_P<3> A_SEL_P<2> A_SEL_P<1> ++ A_SEL_P<0> A_WR_ONE A_WR_ZERO B_BLC<3> B_BLC<2> B_BLC<1> B_BLC<0> B_BLC_SEL ++ B_BLT<3> B_BLT<2> B_BLT<1> B_BLT<0> B_BLT_SEL B_PRE_N B_SEL_P<3> B_SEL_P<2> ++ B_SEL_P<1> B_SEL_P<0> B_WR_ONE B_WR_ZERO VDD VSS / ++ RM_IHPSG13_8192x32_c4_2P_BLDRV +XB_I51 net037 B_DR_O VDD VSS / RSC_IHPSG13_INVX4 +XA_I51 net19 A_DR_O VDD VSS / RSC_IHPSG13_INVX4 +XB_I78 B_RCLK_B_L B_SAE VDD VSS / RSC_IHPSG13_CBUFX2 +XA_I78 A_RCLK_B_L A_SAE VDD VSS / RSC_IHPSG13_CBUFX2 +XB_I69 B_DCLK_L B_DCLK_B_L VDD VSS / RSC_IHPSG13_CINVX8 +XB_I50 B_WCLK_L B_WCLK_B_L VDD VSS / RSC_IHPSG13_CINVX8 +XB_EBUF B_RCLK_L B_RCLK_B_L VDD VSS / RSC_IHPSG13_CINVX8 +XA_I69 A_DCLK_L A_DCLK_B_L VDD VSS / RSC_IHPSG13_CINVX8 +XA_I50 A_WCLK_L A_WCLK_B_L VDD VSS / RSC_IHPSG13_CINVX8 +XA_EBUF A_RCLK_L A_RCLK_B_L VDD VSS / RSC_IHPSG13_CINVX8 +XB_I76 B_DI_N B_DO_WRITE_P B_WR_ZERO VDD VSS / RSC_IHPSG13_AND2X6 +XB_I75 B_DI_R B_DO_WRITE_P B_WR_ONE VDD VSS / RSC_IHPSG13_AND2X6 +XA_I76 A_DI_N A_DO_WRITE_P A_WR_ZERO VDD VSS / RSC_IHPSG13_AND2X6 +XA_I75 A_DI_R A_DO_WRITE_P A_WR_ONE VDD VSS / RSC_IHPSG13_AND2X6 +XB_I83 B_BM_R B_BM_N VDD VSS / RSC_IHPSG13_INVX2 +XB_DEC3INV<31> net041<0> B_SEL_P<31> VDD VSS / RSC_IHPSG13_INVX2 +XB_DEC3INV<30> net041<1> B_SEL_P<30> VDD VSS / RSC_IHPSG13_INVX2 +XB_DEC3INV<29> net041<2> B_SEL_P<29> VDD VSS / RSC_IHPSG13_INVX2 +XB_DEC3INV<28> net041<3> B_SEL_P<28> VDD VSS / RSC_IHPSG13_INVX2 +XB_DEC3INV<27> net041<4> B_SEL_P<27> VDD VSS / RSC_IHPSG13_INVX2 +XB_DEC3INV<26> net041<5> B_SEL_P<26> VDD VSS / RSC_IHPSG13_INVX2 +XB_DEC3INV<25> net041<6> B_SEL_P<25> VDD VSS / RSC_IHPSG13_INVX2 +XB_DEC3INV<24> net041<7> B_SEL_P<24> VDD VSS / RSC_IHPSG13_INVX2 +XB_DEC3INV<23> net041<8> B_SEL_P<23> VDD VSS / RSC_IHPSG13_INVX2 +XB_DEC3INV<22> net041<9> B_SEL_P<22> VDD VSS / RSC_IHPSG13_INVX2 +XB_DEC3INV<21> net041<10> B_SEL_P<21> VDD VSS / RSC_IHPSG13_INVX2 +XB_DEC3INV<20> net041<11> B_SEL_P<20> VDD VSS / RSC_IHPSG13_INVX2 +XB_DEC3INV<19> net041<12> B_SEL_P<19> VDD VSS / RSC_IHPSG13_INVX2 +XB_DEC3INV<18> net041<13> B_SEL_P<18> VDD VSS / RSC_IHPSG13_INVX2 +XB_DEC3INV<17> net041<14> B_SEL_P<17> VDD VSS / RSC_IHPSG13_INVX2 +XB_DEC3INV<16> net041<15> B_SEL_P<16> VDD VSS / RSC_IHPSG13_INVX2 +XB_DEC3INV<15> net041<16> B_SEL_P<15> VDD VSS / RSC_IHPSG13_INVX2 +XB_DEC3INV<14> net041<17> B_SEL_P<14> VDD VSS / RSC_IHPSG13_INVX2 +XB_DEC3INV<13> net041<18> B_SEL_P<13> VDD VSS / RSC_IHPSG13_INVX2 +XB_DEC3INV<12> net041<19> B_SEL_P<12> VDD VSS / RSC_IHPSG13_INVX2 +XB_DEC3INV<11> net041<20> B_SEL_P<11> VDD VSS / RSC_IHPSG13_INVX2 +XB_DEC3INV<10> net041<21> B_SEL_P<10> VDD VSS / RSC_IHPSG13_INVX2 +XB_DEC3INV<9> net041<22> B_SEL_P<9> VDD VSS / RSC_IHPSG13_INVX2 +XB_DEC3INV<8> net041<23> B_SEL_P<8> VDD VSS / RSC_IHPSG13_INVX2 +XB_DEC3INV<7> net041<24> B_SEL_P<7> VDD VSS / RSC_IHPSG13_INVX2 +XB_DEC3INV<6> net041<25> B_SEL_P<6> VDD VSS / RSC_IHPSG13_INVX2 +XB_DEC3INV<5> net041<26> B_SEL_P<5> VDD VSS / RSC_IHPSG13_INVX2 +XB_DEC3INV<4> net041<27> B_SEL_P<4> VDD VSS / RSC_IHPSG13_INVX2 +XB_DEC3INV<3> net041<28> B_SEL_P<3> VDD VSS / RSC_IHPSG13_INVX2 +XB_DEC3INV<2> net041<29> B_SEL_P<2> VDD VSS / RSC_IHPSG13_INVX2 +XB_DEC3INV<1> net041<30> B_SEL_P<1> VDD VSS / RSC_IHPSG13_INVX2 +XB_DEC3INV<0> net041<31> B_SEL_P<0> VDD VSS / RSC_IHPSG13_INVX2 +XB_I49 B_DI_R B_DI_N VDD VSS / RSC_IHPSG13_INVX2 +XA_I83 A_BM_R A_BM_N VDD VSS / RSC_IHPSG13_INVX2 +XA_DEC3INV<31> net23<0> A_SEL_P<31> VDD VSS / RSC_IHPSG13_INVX2 +XA_DEC3INV<30> net23<1> A_SEL_P<30> VDD VSS / RSC_IHPSG13_INVX2 +XA_DEC3INV<29> net23<2> A_SEL_P<29> VDD VSS / RSC_IHPSG13_INVX2 +XA_DEC3INV<28> net23<3> A_SEL_P<28> VDD VSS / RSC_IHPSG13_INVX2 +XA_DEC3INV<27> net23<4> A_SEL_P<27> VDD VSS / RSC_IHPSG13_INVX2 +XA_DEC3INV<26> net23<5> A_SEL_P<26> VDD VSS / RSC_IHPSG13_INVX2 +XA_DEC3INV<25> net23<6> A_SEL_P<25> VDD VSS / RSC_IHPSG13_INVX2 +XA_DEC3INV<24> net23<7> A_SEL_P<24> VDD VSS / RSC_IHPSG13_INVX2 +XA_DEC3INV<23> net23<8> A_SEL_P<23> VDD VSS / RSC_IHPSG13_INVX2 +XA_DEC3INV<22> net23<9> A_SEL_P<22> VDD VSS / RSC_IHPSG13_INVX2 +XA_DEC3INV<21> net23<10> A_SEL_P<21> VDD VSS / RSC_IHPSG13_INVX2 +XA_DEC3INV<20> net23<11> A_SEL_P<20> VDD VSS / RSC_IHPSG13_INVX2 +XA_DEC3INV<19> net23<12> A_SEL_P<19> VDD VSS / RSC_IHPSG13_INVX2 +XA_DEC3INV<18> net23<13> A_SEL_P<18> VDD VSS / RSC_IHPSG13_INVX2 +XA_DEC3INV<17> net23<14> A_SEL_P<17> VDD VSS / RSC_IHPSG13_INVX2 +XA_DEC3INV<16> net23<15> A_SEL_P<16> VDD VSS / RSC_IHPSG13_INVX2 +XA_DEC3INV<15> net23<16> A_SEL_P<15> VDD VSS / RSC_IHPSG13_INVX2 +XA_DEC3INV<14> net23<17> A_SEL_P<14> VDD VSS / RSC_IHPSG13_INVX2 +XA_DEC3INV<13> net23<18> A_SEL_P<13> VDD VSS / RSC_IHPSG13_INVX2 +XA_DEC3INV<12> net23<19> A_SEL_P<12> VDD VSS / RSC_IHPSG13_INVX2 +XA_DEC3INV<11> net23<20> A_SEL_P<11> VDD VSS / RSC_IHPSG13_INVX2 +XA_DEC3INV<10> net23<21> A_SEL_P<10> VDD VSS / RSC_IHPSG13_INVX2 +XA_DEC3INV<9> net23<22> A_SEL_P<9> VDD VSS / RSC_IHPSG13_INVX2 +XA_DEC3INV<8> net23<23> A_SEL_P<8> VDD VSS / RSC_IHPSG13_INVX2 +XA_DEC3INV<7> net23<24> A_SEL_P<7> VDD VSS / RSC_IHPSG13_INVX2 +XA_DEC3INV<6> net23<25> A_SEL_P<6> VDD VSS / RSC_IHPSG13_INVX2 +XA_DEC3INV<5> net23<26> A_SEL_P<5> VDD VSS / RSC_IHPSG13_INVX2 +XA_DEC3INV<4> net23<27> A_SEL_P<4> VDD VSS / RSC_IHPSG13_INVX2 +XA_DEC3INV<3> net23<28> A_SEL_P<3> VDD VSS / RSC_IHPSG13_INVX2 +XA_DEC3INV<2> net23<29> A_SEL_P<2> VDD VSS / RSC_IHPSG13_INVX2 +XA_DEC3INV<1> net23<30> A_SEL_P<1> VDD VSS / RSC_IHPSG13_INVX2 +XA_DEC3INV<0> net23<31> A_SEL_P<0> VDD VSS / RSC_IHPSG13_INVX2 +XA_I49 A_DI_R A_DI_N VDD VSS / RSC_IHPSG13_INVX2 +XB_ISENSE B_SAE B_BLC_SEL B_BLT_SEL net037 net038 VDD VSS / ++ RSC_IHPSG13_DFPQD_MSAFFX2 +XA_ISENSE A_SAE A_BLC_SEL A_BLT_SEL net19 net20 VDD VSS / ++ RSC_IHPSG13_DFPQD_MSAFFX2 +XB_DREG B_BIST_EN_I B_BIST_DW_I B_DCLK_B_L B_DW_I B_DI_R net042 VDD ++ VSS / RSC_IHPSG13_DFNQMX2IX1 +XB_BREG B_BIST_EN_I B_BIST_BM_I B_DCLK_B_L B_BM_I B_BM_R net043 VDD ++ VSS / RSC_IHPSG13_DFNQMX2IX1 +XA_DREG A_BIST_EN_I A_BIST_DW_I A_DCLK_B_L A_DW_I A_DI_R net22 VDD VSS ++ / RSC_IHPSG13_DFNQMX2IX1 +XA_BREG A_BIST_EN_I A_BIST_BM_I A_DCLK_B_L A_BM_I A_BM_R net21 VDD VSS ++ / RSC_IHPSG13_DFNQMX2IX1 +XB_DEC3<31> B_P1<1> B_P0<1> B_ADDR_DEC<7> net041<0> VDD VSS / ++ RSC_IHPSG13_NAND3X2 +XB_DEC3<30> B_P1<1> B_P0<1> B_ADDR_DEC<6> net041<1> VDD VSS / ++ RSC_IHPSG13_NAND3X2 +XB_DEC3<29> B_P1<1> B_P0<1> B_ADDR_DEC<5> net041<2> VDD VSS / ++ RSC_IHPSG13_NAND3X2 +XB_DEC3<28> B_P1<1> B_P0<1> B_ADDR_DEC<4> net041<3> VDD VSS / ++ RSC_IHPSG13_NAND3X2 +XB_DEC3<27> B_P1<1> B_P0<1> B_ADDR_DEC<3> net041<4> VDD VSS / ++ RSC_IHPSG13_NAND3X2 +XB_DEC3<26> B_P1<1> B_P0<1> B_ADDR_DEC<2> net041<5> VDD VSS / ++ RSC_IHPSG13_NAND3X2 +XB_DEC3<25> B_P1<1> B_P0<1> B_ADDR_DEC<1> net041<6> VDD VSS / ++ RSC_IHPSG13_NAND3X2 +XB_DEC3<24> B_P1<1> B_P0<1> B_ADDR_DEC<0> net041<7> VDD VSS / ++ RSC_IHPSG13_NAND3X2 +XB_DEC3<23> B_P1<1> B_N0<1> B_ADDR_DEC<7> net041<8> VDD VSS / ++ RSC_IHPSG13_NAND3X2 +XB_DEC3<22> B_P1<1> B_N0<1> B_ADDR_DEC<6> net041<9> VDD VSS / ++ RSC_IHPSG13_NAND3X2 +XB_DEC3<21> B_P1<1> B_N0<1> B_ADDR_DEC<5> net041<10> VDD VSS / ++ RSC_IHPSG13_NAND3X2 +XB_DEC3<20> B_P1<1> B_N0<1> B_ADDR_DEC<4> net041<11> VDD VSS / ++ RSC_IHPSG13_NAND3X2 +XB_DEC3<19> B_P1<1> B_N0<1> B_ADDR_DEC<3> net041<12> VDD VSS / ++ RSC_IHPSG13_NAND3X2 +XB_DEC3<18> B_P1<1> B_N0<1> B_ADDR_DEC<2> net041<13> VDD VSS / ++ RSC_IHPSG13_NAND3X2 +XB_DEC3<17> B_P1<1> B_N0<1> B_ADDR_DEC<1> net041<14> VDD VSS / ++ RSC_IHPSG13_NAND3X2 +XB_DEC3<16> B_P1<1> B_N0<1> B_ADDR_DEC<0> net041<15> VDD VSS / ++ RSC_IHPSG13_NAND3X2 +XB_DEC3<15> B_N1<0> B_P0<0> B_ADDR_DEC<7> net041<16> VDD VSS / ++ RSC_IHPSG13_NAND3X2 +XB_DEC3<14> B_N1<0> B_P0<0> B_ADDR_DEC<6> net041<17> VDD VSS / ++ RSC_IHPSG13_NAND3X2 +XB_DEC3<13> B_N1<0> B_P0<0> B_ADDR_DEC<5> net041<18> VDD VSS / ++ RSC_IHPSG13_NAND3X2 +XB_DEC3<12> B_N1<0> B_P0<0> B_ADDR_DEC<4> net041<19> VDD VSS / ++ RSC_IHPSG13_NAND3X2 +XB_DEC3<11> B_N1<0> B_P0<0> B_ADDR_DEC<3> net041<20> VDD VSS / ++ RSC_IHPSG13_NAND3X2 +XB_DEC3<10> B_N1<0> B_P0<0> B_ADDR_DEC<2> net041<21> VDD VSS / ++ RSC_IHPSG13_NAND3X2 +XB_DEC3<9> B_N1<0> B_P0<0> B_ADDR_DEC<1> net041<22> VDD VSS / ++ RSC_IHPSG13_NAND3X2 +XB_DEC3<8> B_N1<0> B_P0<0> B_ADDR_DEC<0> net041<23> VDD VSS / ++ RSC_IHPSG13_NAND3X2 +XB_DEC3<7> B_N1<0> B_N0<0> B_ADDR_DEC<7> net041<24> VDD VSS / ++ RSC_IHPSG13_NAND3X2 +XB_DEC3<6> B_N1<0> B_N0<0> B_ADDR_DEC<6> net041<25> VDD VSS / ++ RSC_IHPSG13_NAND3X2 +XB_DEC3<5> B_N1<0> B_N0<0> B_ADDR_DEC<5> net041<26> VDD VSS / ++ RSC_IHPSG13_NAND3X2 +XB_DEC3<4> B_N1<0> B_N0<0> B_ADDR_DEC<4> net041<27> VDD VSS / ++ RSC_IHPSG13_NAND3X2 +XB_DEC3<3> B_N1<0> B_N0<0> B_ADDR_DEC<3> net041<28> VDD VSS / ++ RSC_IHPSG13_NAND3X2 +XB_DEC3<2> B_N1<0> B_N0<0> B_ADDR_DEC<2> net041<29> VDD VSS / ++ RSC_IHPSG13_NAND3X2 +XB_DEC3<1> B_N1<0> B_N0<0> B_ADDR_DEC<1> net041<30> VDD VSS / ++ RSC_IHPSG13_NAND3X2 +XB_DEC3<0> B_N1<0> B_N0<0> B_ADDR_DEC<0> net041<31> VDD VSS / ++ RSC_IHPSG13_NAND3X2 +XA_DEC3<31> A_P1<1> A_P0<1> A_ADDR_DEC<7> net23<0> VDD VSS / ++ RSC_IHPSG13_NAND3X2 +XA_DEC3<30> A_P1<1> A_P0<1> A_ADDR_DEC<6> net23<1> VDD VSS / ++ RSC_IHPSG13_NAND3X2 +XA_DEC3<29> A_P1<1> A_P0<1> A_ADDR_DEC<5> net23<2> VDD VSS / ++ RSC_IHPSG13_NAND3X2 +XA_DEC3<28> A_P1<1> A_P0<1> A_ADDR_DEC<4> net23<3> VDD VSS / ++ RSC_IHPSG13_NAND3X2 +XA_DEC3<27> A_P1<1> A_P0<1> A_ADDR_DEC<3> net23<4> VDD VSS / ++ RSC_IHPSG13_NAND3X2 +XA_DEC3<26> A_P1<1> A_P0<1> A_ADDR_DEC<2> net23<5> VDD VSS / ++ RSC_IHPSG13_NAND3X2 +XA_DEC3<25> A_P1<1> A_P0<1> A_ADDR_DEC<1> net23<6> VDD VSS / ++ RSC_IHPSG13_NAND3X2 +XA_DEC3<24> A_P1<1> A_P0<1> A_ADDR_DEC<0> net23<7> VDD VSS / ++ RSC_IHPSG13_NAND3X2 +XA_DEC3<23> A_P1<1> A_N0<1> A_ADDR_DEC<7> net23<8> VDD VSS / ++ RSC_IHPSG13_NAND3X2 +XA_DEC3<22> A_P1<1> A_N0<1> A_ADDR_DEC<6> net23<9> VDD VSS / ++ RSC_IHPSG13_NAND3X2 +XA_DEC3<21> A_P1<1> A_N0<1> A_ADDR_DEC<5> net23<10> VDD VSS / ++ RSC_IHPSG13_NAND3X2 +XA_DEC3<20> A_P1<1> A_N0<1> A_ADDR_DEC<4> net23<11> VDD VSS / ++ RSC_IHPSG13_NAND3X2 +XA_DEC3<19> A_P1<1> A_N0<1> A_ADDR_DEC<3> net23<12> VDD VSS / ++ RSC_IHPSG13_NAND3X2 +XA_DEC3<18> A_P1<1> A_N0<1> A_ADDR_DEC<2> net23<13> VDD VSS / ++ RSC_IHPSG13_NAND3X2 +XA_DEC3<17> A_P1<1> A_N0<1> A_ADDR_DEC<1> net23<14> VDD VSS / ++ RSC_IHPSG13_NAND3X2 +XA_DEC3<16> A_P1<1> A_N0<1> A_ADDR_DEC<0> net23<15> VDD VSS / ++ RSC_IHPSG13_NAND3X2 +XA_DEC3<15> A_N1<0> A_P0<0> A_ADDR_DEC<7> net23<16> VDD VSS / ++ RSC_IHPSG13_NAND3X2 +XA_DEC3<14> A_N1<0> A_P0<0> A_ADDR_DEC<6> net23<17> VDD VSS / ++ RSC_IHPSG13_NAND3X2 +XA_DEC3<13> A_N1<0> A_P0<0> A_ADDR_DEC<5> net23<18> VDD VSS / ++ RSC_IHPSG13_NAND3X2 +XA_DEC3<12> A_N1<0> A_P0<0> A_ADDR_DEC<4> net23<19> VDD VSS / ++ RSC_IHPSG13_NAND3X2 +XA_DEC3<11> A_N1<0> A_P0<0> A_ADDR_DEC<3> net23<20> VDD VSS / ++ RSC_IHPSG13_NAND3X2 +XA_DEC3<10> A_N1<0> A_P0<0> A_ADDR_DEC<2> net23<21> VDD VSS / ++ RSC_IHPSG13_NAND3X2 +XA_DEC3<9> A_N1<0> A_P0<0> A_ADDR_DEC<1> net23<22> VDD VSS / ++ RSC_IHPSG13_NAND3X2 +XA_DEC3<8> A_N1<0> A_P0<0> A_ADDR_DEC<0> net23<23> VDD VSS / ++ RSC_IHPSG13_NAND3X2 +XA_DEC3<7> A_N1<0> A_N0<0> A_ADDR_DEC<7> net23<24> VDD VSS / ++ RSC_IHPSG13_NAND3X2 +XA_DEC3<6> A_N1<0> A_N0<0> A_ADDR_DEC<6> net23<25> VDD VSS / ++ RSC_IHPSG13_NAND3X2 +XA_DEC3<5> A_N1<0> A_N0<0> A_ADDR_DEC<5> net23<26> VDD VSS / ++ RSC_IHPSG13_NAND3X2 +XA_DEC3<4> A_N1<0> A_N0<0> A_ADDR_DEC<4> net23<27> VDD VSS / ++ RSC_IHPSG13_NAND3X2 +XA_DEC3<3> A_N1<0> A_N0<0> A_ADDR_DEC<3> net23<28> VDD VSS / ++ RSC_IHPSG13_NAND3X2 +XA_DEC3<2> A_N1<0> A_N0<0> A_ADDR_DEC<2> net23<29> VDD VSS / ++ RSC_IHPSG13_NAND3X2 +XA_DEC3<1> A_N1<0> A_N0<0> A_ADDR_DEC<1> net23<30> VDD VSS / ++ RSC_IHPSG13_NAND3X2 +XA_DEC3<0> A_N1<0> A_N0<0> A_ADDR_DEC<0> net23<31> VDD VSS / ++ RSC_IHPSG13_NAND3X2 +XB_I89 B_DCLK_B_L B_DCLK_B_R / RSC_IHPSG13_MET3RES +XB_I91 B_RCLK_B_L B_RCLK_B_R / RSC_IHPSG13_MET3RES +XB_I90 B_WCLK_B_L B_WCLK_B_R / RSC_IHPSG13_MET3RES +XB_I88 B_DCLK_L B_DCLK_R / RSC_IHPSG13_MET3RES +XB_I87 B_WCLK_L B_WCLK_R / RSC_IHPSG13_MET3RES +XB_R2 B_RCLK_L B_RCLK_R / RSC_IHPSG13_MET3RES +XA_I89 A_DCLK_B_L A_DCLK_B_R / RSC_IHPSG13_MET3RES +XA_I91 A_RCLK_B_L A_RCLK_B_R / RSC_IHPSG13_MET3RES +XA_I90 A_WCLK_B_L A_WCLK_B_R / RSC_IHPSG13_MET3RES +XA_I88 A_DCLK_L A_DCLK_R / RSC_IHPSG13_MET3RES +XA_I87 A_WCLK_L A_WCLK_R / RSC_IHPSG13_MET3RES +XA_R2 A_RCLK_L A_RCLK_R / RSC_IHPSG13_MET3RES +XB_BM_TIEH B_TIEH_O VDD VSS / RSC_IHPSG13_TIEH +XA_BM_TIEH A_TIEH_O VDD VSS / RSC_IHPSG13_TIEH +.ENDS +.SUBCKT RM_IHPSG13_8192x32_c4_2P_COLDRV13_FILL4 VDD VSS +XI0<11> VDD VSS / RSC_IHPSG13_FILLCAP4 +XI0<10> VDD VSS / RSC_IHPSG13_FILLCAP4 +XI0<9> VDD VSS / RSC_IHPSG13_FILLCAP4 +XI0<8> VDD VSS / RSC_IHPSG13_FILLCAP4 +XI0<7> VDD VSS / RSC_IHPSG13_FILLCAP4 +XI0<6> VDD VSS / RSC_IHPSG13_FILLCAP4 +XI0<5> VDD VSS / RSC_IHPSG13_FILLCAP4 +XI0<4> VDD VSS / RSC_IHPSG13_FILLCAP4 +XI0<3> VDD VSS / RSC_IHPSG13_FILLCAP4 +XI0<2> VDD VSS / RSC_IHPSG13_FILLCAP4 +XI0<1> VDD VSS / RSC_IHPSG13_FILLCAP4 +.ENDS + + +.SUBCKT RSC_IHPSG13_CBUFX16 A Z VDD VSS +MN0 net4 A VSS VSS sg13_lv_nmos m=1 w=2.115u l=130.00n ng=3 nrd=0 nrs=0 +MN1 Z net4 VSS VSS sg13_lv_nmos m=1 w=5.64u l=130.00n ng=8 nrd=0 nrs=0 +MP1 Z net4 VDD VDD sg13_lv_pmos m=1 w=13.000u l=130.00n ng=8 nrd=0 ++ nrs=0 +MP0 net4 A VDD VDD sg13_lv_pmos m=1 w=4.89u l=130.00n ng=3 nrd=0 nrs=0 +.ENDS +.SUBCKT RM_IHPSG13_8192x32_c4_1P_COLDRV13X16 ADDR_COL_I<1> ADDR_COL_I<0> ADDR_COL_O<1> ++ ADDR_COL_O<0> ADDR_DEC_I<7> ADDR_DEC_I<6> ADDR_DEC_I<5> ADDR_DEC_I<4> ++ ADDR_DEC_I<3> ADDR_DEC_I<2> ADDR_DEC_I<1> ADDR_DEC_I<0> ADDR_DEC_O<7> ++ ADDR_DEC_O<6> ADDR_DEC_O<5> ADDR_DEC_O<4> ADDR_DEC_O<3> ADDR_DEC_O<2> ++ ADDR_DEC_O<1> ADDR_DEC_O<0> DCLK_I DCLK_O RCLK_I RCLK_O WCLK_I WCLK_O ++ VDD VSS +XI1<1> VDD VSS / RSC_IHPSG13_FILLCAP4 +XI1<0> VDD VSS / RSC_IHPSG13_FILLCAP4 +XI0<3> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI0<2> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI0<1> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI0<0> VDD VSS / RSC_IHPSG13_FILLCAP8 +XADDR_COL_DRV<1> ADDR_COL_I<1> ADDR_COL_O<1> VDD VSS / ++ RSC_IHPSG13_CBUFX16 +XADDR_COL_DRV<0> ADDR_COL_I<0> ADDR_COL_O<0> VDD VSS / ++ RSC_IHPSG13_CBUFX16 +XADDR_DEC_DRV<7> ADDR_DEC_I<7> ADDR_DEC_O<7> VDD VSS / ++ RSC_IHPSG13_CBUFX16 +XADDR_DEC_DRV<6> ADDR_DEC_I<6> ADDR_DEC_O<6> VDD VSS / ++ RSC_IHPSG13_CBUFX16 +XADDR_DEC_DRV<5> ADDR_DEC_I<5> ADDR_DEC_O<5> VDD VSS / ++ RSC_IHPSG13_CBUFX16 +XADDR_DEC_DRV<4> ADDR_DEC_I<4> ADDR_DEC_O<4> VDD VSS / ++ RSC_IHPSG13_CBUFX16 +XADDR_DEC_DRV<3> ADDR_DEC_I<3> ADDR_DEC_O<3> VDD VSS / ++ RSC_IHPSG13_CBUFX16 +XADDR_DEC_DRV<2> ADDR_DEC_I<2> ADDR_DEC_O<2> VDD VSS / ++ RSC_IHPSG13_CBUFX16 +XADDR_DEC_DRV<1> ADDR_DEC_I<1> ADDR_DEC_O<1> VDD VSS / ++ RSC_IHPSG13_CBUFX16 +XADDR_DEC_DRV<0> ADDR_DEC_I<0> ADDR_DEC_O<0> VDD VSS / ++ RSC_IHPSG13_CBUFX16 +XDCLK_DRV DCLK_I DCLK_O VDD VSS / RSC_IHPSG13_CBUFX16 +XRCLK_DRV RCLK_I RCLK_O VDD VSS / RSC_IHPSG13_CBUFX16 +XWCLK_DRV WCLK_I WCLK_O VDD VSS / RSC_IHPSG13_CBUFX16 +.ENDS +.SUBCKT RSC_IHPSG13_WLDRVX16 A Z VDD VSS +MN1 Z net6 VSS VSS sg13_lv_nmos m=1 w=1.41u l=130.00n ng=2 nrd=0 nrs=0 +MN0 net6 A VSS VSS sg13_lv_nmos m=1 w=1.8u l=130.00n ng=2 nrd=0 nrs=0 +MP1 Z net6 VDD VDD sg13_lv_pmos m=1 w=12.96u l=130.00n ng=8 nrd=0 nrs=0 +MP0 net6 A VDD VDD sg13_lv_pmos m=1 w=900.0n l=130.00n ng=1 nrd=0 nrs=0 +.ENDS +.SUBCKT RM_IHPSG13_8192x32_c4_1P_WLDRV16X16 A<15> A<14> A<13> A<12> A<11> A<10> A<9> A<8> ++ A<7> A<6> A<5> A<4> A<3> A<2> A<1> A<0> Z<15> Z<14> Z<13> Z<12> Z<11> Z<10> ++ Z<9> Z<8> Z<7> Z<6> Z<5> Z<4> Z<3> Z<2> Z<1> Z<0> VDD VSS +XBUF<15> A<15> Z<15> VDD VSS / RSC_IHPSG13_WLDRVX16 +XBUF<14> A<14> Z<14> VDD VSS / RSC_IHPSG13_WLDRVX16 +XBUF<13> A<13> Z<13> VDD VSS / RSC_IHPSG13_WLDRVX16 +XBUF<12> A<12> Z<12> VDD VSS / RSC_IHPSG13_WLDRVX16 +XBUF<11> A<11> Z<11> VDD VSS / RSC_IHPSG13_WLDRVX16 +XBUF<10> A<10> Z<10> VDD VSS / RSC_IHPSG13_WLDRVX16 +XBUF<9> A<9> Z<9> VDD VSS / RSC_IHPSG13_WLDRVX16 +XBUF<8> A<8> Z<8> VDD VSS / RSC_IHPSG13_WLDRVX16 +XBUF<7> A<7> Z<7> VDD VSS / RSC_IHPSG13_WLDRVX16 +XBUF<6> A<6> Z<6> VDD VSS / RSC_IHPSG13_WLDRVX16 +XBUF<5> A<5> Z<5> VDD VSS / RSC_IHPSG13_WLDRVX16 +XBUF<4> A<4> Z<4> VDD VSS / RSC_IHPSG13_WLDRVX16 +XBUF<3> A<3> Z<3> VDD VSS / RSC_IHPSG13_WLDRVX16 +XBUF<2> A<2> Z<2> VDD VSS / RSC_IHPSG13_WLDRVX16 +XBUF<1> A<1> Z<1> VDD VSS / RSC_IHPSG13_WLDRVX16 +XBUF<0> A<0> Z<0> VDD VSS / RSC_IHPSG13_WLDRVX16 +.ENDS + + +.SUBCKT RM_IHPSG13_8192x32_c4_2P_COLDRV13X4 ADDR_COL_I<1> ADDR_COL_I<0> ADDR_COL_O<1> ++ ADDR_COL_O<0> ADDR_DEC_I<7> ADDR_DEC_I<6> ADDR_DEC_I<5> ADDR_DEC_I<4> ++ ADDR_DEC_I<3> ADDR_DEC_I<2> ADDR_DEC_I<1> ADDR_DEC_I<0> ADDR_DEC_O<7> ++ ADDR_DEC_O<6> ADDR_DEC_O<5> ADDR_DEC_O<4> ADDR_DEC_O<3> ADDR_DEC_O<2> ++ ADDR_DEC_O<1> ADDR_DEC_O<0> DCLK_I DCLK_O RCLK_I RCLK_O WCLK_I WCLK_O ++ VDD VSS +XWCLK_DRV WCLK_I WCLK_O VDD VSS / RSC_IHPSG13_CBUFX4 +XRCLK_DRV RCLK_I RCLK_O VDD VSS / RSC_IHPSG13_CBUFX4 +XDCLK_DRV DCLK_I DCLK_O VDD VSS / RSC_IHPSG13_CBUFX4 +XADDR_COL_DRV<1> ADDR_COL_I<1> ADDR_COL_O<1> VDD VSS / ++ RSC_IHPSG13_CBUFX4 +XADDR_COL_DRV<0> ADDR_COL_I<0> ADDR_COL_O<0> VDD VSS / ++ RSC_IHPSG13_CBUFX4 +XADDR_DEC_DRV<7> ADDR_DEC_I<7> ADDR_DEC_O<7> VDD VSS / ++ RSC_IHPSG13_CBUFX4 +XADDR_DEC_DRV<6> ADDR_DEC_I<6> ADDR_DEC_O<6> VDD VSS / ++ RSC_IHPSG13_CBUFX4 +XADDR_DEC_DRV<5> ADDR_DEC_I<5> ADDR_DEC_O<5> VDD VSS / ++ RSC_IHPSG13_CBUFX4 +XADDR_DEC_DRV<4> ADDR_DEC_I<4> ADDR_DEC_O<4> VDD VSS / ++ RSC_IHPSG13_CBUFX4 +XADDR_DEC_DRV<3> ADDR_DEC_I<3> ADDR_DEC_O<3> VDD VSS / ++ RSC_IHPSG13_CBUFX4 +XADDR_DEC_DRV<2> ADDR_DEC_I<2> ADDR_DEC_O<2> VDD VSS / ++ RSC_IHPSG13_CBUFX4 +XADDR_DEC_DRV<1> ADDR_DEC_I<1> ADDR_DEC_O<1> VDD VSS / ++ RSC_IHPSG13_CBUFX4 +XADDR_DEC_DRV<0> ADDR_DEC_I<0> ADDR_DEC_O<0> VDD VSS / ++ RSC_IHPSG13_CBUFX4 +XI0<6> VDD VSS / RSC_IHPSG13_FILLCAP4 +XI0<5> VDD VSS / RSC_IHPSG13_FILLCAP4 +XI0<4> VDD VSS / RSC_IHPSG13_FILLCAP4 +XI0<3> VDD VSS / RSC_IHPSG13_FILLCAP4 +XI0<2> VDD VSS / RSC_IHPSG13_FILLCAP4 +XI0<1> VDD VSS / RSC_IHPSG13_FILLCAP4 +XI1 VDD VSS / RSC_IHPSG13_FILLCAP8 +.ENDS +.SUBCKT RM_IHPSG13_8192x32_c4_2P_WLDRV16X4 A<15> A<14> A<13> A<12> A<11> A<10> A<9> A<8> ++ A<7> A<6> A<5> A<4> A<3> A<2> A<1> A<0> Z<15> Z<14> Z<13> Z<12> Z<11> Z<10> ++ Z<9> Z<8> Z<7> Z<6> Z<5> Z<4> Z<3> Z<2> Z<1> Z<0> VDD VSS +XBUF<15> A<15> Z<15> VDD VSS / RSC_IHPSG13_WLDRVX4 +XBUF<14> A<14> Z<14> VDD VSS / RSC_IHPSG13_WLDRVX4 +XBUF<13> A<13> Z<13> VDD VSS / RSC_IHPSG13_WLDRVX4 +XBUF<12> A<12> Z<12> VDD VSS / RSC_IHPSG13_WLDRVX4 +XBUF<11> A<11> Z<11> VDD VSS / RSC_IHPSG13_WLDRVX4 +XBUF<10> A<10> Z<10> VDD VSS / RSC_IHPSG13_WLDRVX4 +XBUF<9> A<9> Z<9> VDD VSS / RSC_IHPSG13_WLDRVX4 +XBUF<8> A<8> Z<8> VDD VSS / RSC_IHPSG13_WLDRVX4 +XBUF<7> A<7> Z<7> VDD VSS / RSC_IHPSG13_WLDRVX4 +XBUF<6> A<6> Z<6> VDD VSS / RSC_IHPSG13_WLDRVX4 +XBUF<5> A<5> Z<5> VDD VSS / RSC_IHPSG13_WLDRVX4 +XBUF<4> A<4> Z<4> VDD VSS / RSC_IHPSG13_WLDRVX4 +XBUF<3> A<3> Z<3> VDD VSS / RSC_IHPSG13_WLDRVX4 +XBUF<2> A<2> Z<2> VDD VSS / RSC_IHPSG13_WLDRVX4 +XBUF<1> A<1> Z<1> VDD VSS / RSC_IHPSG13_WLDRVX4 +XBUF<0> A<0> Z<0> VDD VSS / RSC_IHPSG13_WLDRVX4 +.ENDS +.SUBCKT RM_IHPSG13_8192x32_c4_2P_ROWDEC8 ADDR_N_I<7> ADDR_N_I<6> ADDR_N_I<5> ADDR_N_I<4> ++ ADDR_N_I<3> ADDR_N_I<2> ADDR_N_I<1> ADDR_N_I<0> CS_I ECLK_I WL_O<255> ++ WL_O<254> WL_O<253> WL_O<252> WL_O<251> WL_O<250> WL_O<249> WL_O<248> ++ WL_O<247> WL_O<246> WL_O<245> WL_O<244> WL_O<243> WL_O<242> WL_O<241> ++ WL_O<240> WL_O<239> WL_O<238> WL_O<237> WL_O<236> WL_O<235> WL_O<234> ++ WL_O<233> WL_O<232> WL_O<231> WL_O<230> WL_O<229> WL_O<228> WL_O<227> ++ WL_O<226> WL_O<225> WL_O<224> WL_O<223> WL_O<222> WL_O<221> WL_O<220> ++ WL_O<219> WL_O<218> WL_O<217> WL_O<216> WL_O<215> WL_O<214> WL_O<213> ++ WL_O<212> WL_O<211> WL_O<210> WL_O<209> WL_O<208> WL_O<207> WL_O<206> ++ WL_O<205> WL_O<204> WL_O<203> WL_O<202> WL_O<201> WL_O<200> WL_O<199> ++ WL_O<198> WL_O<197> WL_O<196> WL_O<195> WL_O<194> WL_O<193> WL_O<192> ++ WL_O<191> WL_O<190> WL_O<189> WL_O<188> WL_O<187> WL_O<186> WL_O<185> ++ WL_O<184> WL_O<183> WL_O<182> WL_O<181> WL_O<180> WL_O<179> WL_O<178> ++ WL_O<177> WL_O<176> WL_O<175> WL_O<174> WL_O<173> WL_O<172> WL_O<171> ++ WL_O<170> WL_O<169> WL_O<168> WL_O<167> WL_O<166> WL_O<165> WL_O<164> ++ WL_O<163> WL_O<162> WL_O<161> WL_O<160> WL_O<159> WL_O<158> WL_O<157> ++ WL_O<156> WL_O<155> WL_O<154> WL_O<153> WL_O<152> WL_O<151> WL_O<150> ++ WL_O<149> WL_O<148> WL_O<147> WL_O<146> WL_O<145> WL_O<144> WL_O<143> ++ WL_O<142> WL_O<141> WL_O<140> WL_O<139> WL_O<138> WL_O<137> WL_O<136> ++ WL_O<135> WL_O<134> WL_O<133> WL_O<132> WL_O<131> WL_O<130> WL_O<129> ++ WL_O<128> WL_O<127> WL_O<126> WL_O<125> WL_O<124> WL_O<123> WL_O<122> ++ WL_O<121> WL_O<120> WL_O<119> WL_O<118> WL_O<117> WL_O<116> WL_O<115> ++ WL_O<114> WL_O<113> WL_O<112> WL_O<111> WL_O<110> WL_O<109> WL_O<108> ++ WL_O<107> WL_O<106> WL_O<105> WL_O<104> WL_O<103> WL_O<102> WL_O<101> ++ WL_O<100> WL_O<99> WL_O<98> WL_O<97> WL_O<96> WL_O<95> WL_O<94> WL_O<93> ++ WL_O<92> WL_O<91> WL_O<90> WL_O<89> WL_O<88> WL_O<87> WL_O<86> WL_O<85> ++ WL_O<84> WL_O<83> WL_O<82> WL_O<81> WL_O<80> WL_O<79> WL_O<78> WL_O<77> ++ WL_O<76> WL_O<75> WL_O<74> WL_O<73> WL_O<72> WL_O<71> WL_O<70> WL_O<69> ++ WL_O<68> WL_O<67> WL_O<66> WL_O<65> WL_O<64> WL_O<63> WL_O<62> WL_O<61> ++ WL_O<60> WL_O<59> WL_O<58> WL_O<57> WL_O<56> WL_O<55> WL_O<54> WL_O<53> ++ WL_O<52> WL_O<51> WL_O<50> WL_O<49> WL_O<48> WL_O<47> WL_O<46> WL_O<45> ++ WL_O<44> WL_O<43> WL_O<42> WL_O<41> WL_O<40> WL_O<39> WL_O<38> WL_O<37> ++ WL_O<36> WL_O<35> WL_O<34> WL_O<33> WL_O<32> WL_O<31> WL_O<30> WL_O<29> ++ WL_O<28> WL_O<27> WL_O<26> WL_O<25> WL_O<24> WL_O<23> WL_O<22> WL_O<21> ++ WL_O<20> WL_O<19> WL_O<18> WL_O<17> WL_O<16> WL_O<15> WL_O<14> WL_O<13> ++ WL_O<12> WL_O<11> WL_O<10> WL_O<9> WL_O<8> WL_O<7> WL_O<6> WL_O<5> WL_O<4> ++ WL_O<3> WL_O<2> WL_O<1> WL_O<0> VDD VSS +XDEC11<4> ADDR_N_I<7> ADDR_N_I<6> CS_I CS04<3> VDD VSS / ++ RM_IHPSG13_8192x32_c4_2P_DEC03 +XDEC11<3> ADDR_N_I<5> ADDR_N_I<4> CS04<3> CS00<15> VDD VSS / ++ RM_IHPSG13_8192x32_c4_2P_DEC03 +XDEC11<2> ADDR_N_I<5> ADDR_N_I<4> CS04<2> CS00<11> VDD VSS / ++ RM_IHPSG13_8192x32_c4_2P_DEC03 +XDEC11<1> ADDR_N_I<5> ADDR_N_I<4> CS04<1> CS00<7> VDD VSS / ++ RM_IHPSG13_8192x32_c4_2P_DEC03 +XDEC11<0> ADDR_N_I<5> ADDR_N_I<4> CS04<0> CS00<3> VDD VSS / ++ RM_IHPSG13_8192x32_c4_2P_DEC03 +XSEL<15> ADDR_N_I<3> ADDR_N_I<2> ADDR_N_I<1> ADDR_N_I<0> CS00<15> ECLK_H<15> ++ ECLK_H<16> ECLK_B<15> ECLK_B<16> WL_O<255> WL_O<254> WL_O<253> WL_O<252> ++ WL_O<251> WL_O<250> WL_O<249> WL_O<248> WL_O<247> WL_O<246> WL_O<245> ++ WL_O<244> WL_O<243> WL_O<242> WL_O<241> WL_O<240> VDD VSS / ++ RM_IHPSG13_8192x32_c4_2P_DEC04 +XSEL<14> ADDR_N_I<3> ADDR_N_I<2> ADDR_N_I<1> ADDR_N_I<0> CS00<14> ECLK_H<14> ++ ECLK_H<15> ECLK_B<14> ECLK_B<15> WL_O<239> WL_O<238> WL_O<237> WL_O<236> ++ WL_O<235> WL_O<234> WL_O<233> WL_O<232> WL_O<231> WL_O<230> WL_O<229> ++ WL_O<228> WL_O<227> WL_O<226> WL_O<225> WL_O<224> VDD VSS / ++ RM_IHPSG13_8192x32_c4_2P_DEC04 +XSEL<13> ADDR_N_I<3> ADDR_N_I<2> ADDR_N_I<1> ADDR_N_I<0> CS00<13> ECLK_H<13> ++ ECLK_H<14> ECLK_B<13> ECLK_B<14> WL_O<223> WL_O<222> WL_O<221> WL_O<220> ++ WL_O<219> WL_O<218> WL_O<217> WL_O<216> WL_O<215> WL_O<214> WL_O<213> ++ WL_O<212> WL_O<211> WL_O<210> WL_O<209> WL_O<208> VDD VSS / ++ RM_IHPSG13_8192x32_c4_2P_DEC04 +XSEL<12> ADDR_N_I<3> ADDR_N_I<2> ADDR_N_I<1> ADDR_N_I<0> CS00<12> ECLK_H<12> ++ ECLK_H<13> ECLK_B<12> ECLK_B<13> WL_O<207> WL_O<206> WL_O<205> WL_O<204> ++ WL_O<203> WL_O<202> WL_O<201> WL_O<200> WL_O<199> WL_O<198> WL_O<197> ++ WL_O<196> WL_O<195> WL_O<194> WL_O<193> WL_O<192> VDD VSS / ++ RM_IHPSG13_8192x32_c4_2P_DEC04 +XSEL<11> ADDR_N_I<3> ADDR_N_I<2> ADDR_N_I<1> ADDR_N_I<0> CS00<11> ECLK_H<11> ++ ECLK_H<12> ECLK_B<11> ECLK_B<12> WL_O<191> WL_O<190> WL_O<189> WL_O<188> ++ WL_O<187> WL_O<186> WL_O<185> WL_O<184> WL_O<183> WL_O<182> WL_O<181> ++ WL_O<180> WL_O<179> WL_O<178> WL_O<177> WL_O<176> VDD VSS / ++ RM_IHPSG13_8192x32_c4_2P_DEC04 +XSEL<10> ADDR_N_I<3> ADDR_N_I<2> ADDR_N_I<1> ADDR_N_I<0> CS00<10> ECLK_H<10> ++ ECLK_H<11> ECLK_B<10> ECLK_B<11> WL_O<175> WL_O<174> WL_O<173> WL_O<172> ++ WL_O<171> WL_O<170> WL_O<169> WL_O<168> WL_O<167> WL_O<166> WL_O<165> ++ WL_O<164> WL_O<163> WL_O<162> WL_O<161> WL_O<160> VDD VSS / ++ RM_IHPSG13_8192x32_c4_2P_DEC04 +XSEL<9> ADDR_N_I<3> ADDR_N_I<2> ADDR_N_I<1> ADDR_N_I<0> CS00<9> ECLK_H<9> ++ ECLK_H<10> ECLK_B<9> ECLK_B<10> WL_O<159> WL_O<158> WL_O<157> WL_O<156> ++ WL_O<155> WL_O<154> WL_O<153> WL_O<152> WL_O<151> WL_O<150> WL_O<149> ++ WL_O<148> WL_O<147> WL_O<146> WL_O<145> WL_O<144> VDD VSS / ++ RM_IHPSG13_8192x32_c4_2P_DEC04 +XSEL<8> ADDR_N_I<3> ADDR_N_I<2> ADDR_N_I<1> ADDR_N_I<0> CS00<8> ECLK_H<8> ++ ECLK_H<9> ECLK_B<8> ECLK_B<9> WL_O<143> WL_O<142> WL_O<141> WL_O<140> ++ WL_O<139> WL_O<138> WL_O<137> WL_O<136> WL_O<135> WL_O<134> WL_O<133> ++ WL_O<132> WL_O<131> WL_O<130> WL_O<129> WL_O<128> VDD VSS / ++ RM_IHPSG13_8192x32_c4_2P_DEC04 +XSEL<7> ADDR_N_I<3> ADDR_N_I<2> ADDR_N_I<1> ADDR_N_I<0> CS00<7> ECLK_H<7> ++ ECLK_H<8> ECLK_B<7> ECLK_B<8> WL_O<127> WL_O<126> WL_O<125> WL_O<124> ++ WL_O<123> WL_O<122> WL_O<121> WL_O<120> WL_O<119> WL_O<118> WL_O<117> ++ WL_O<116> WL_O<115> WL_O<114> WL_O<113> WL_O<112> VDD VSS / ++ RM_IHPSG13_8192x32_c4_2P_DEC04 +XSEL<6> ADDR_N_I<3> ADDR_N_I<2> ADDR_N_I<1> ADDR_N_I<0> CS00<6> ECLK_H<6> ++ ECLK_H<7> ECLK_B<6> ECLK_B<7> WL_O<111> WL_O<110> WL_O<109> WL_O<108> ++ WL_O<107> WL_O<106> WL_O<105> WL_O<104> WL_O<103> WL_O<102> WL_O<101> ++ WL_O<100> WL_O<99> WL_O<98> WL_O<97> WL_O<96> VDD VSS / ++ RM_IHPSG13_8192x32_c4_2P_DEC04 +XSEL<5> ADDR_N_I<3> ADDR_N_I<2> ADDR_N_I<1> ADDR_N_I<0> CS00<5> ECLK_H<5> ++ ECLK_H<6> ECLK_B<5> ECLK_B<6> WL_O<95> WL_O<94> WL_O<93> WL_O<92> WL_O<91> ++ WL_O<90> WL_O<89> WL_O<88> WL_O<87> WL_O<86> WL_O<85> WL_O<84> WL_O<83> ++ WL_O<82> WL_O<81> WL_O<80> VDD VSS / RM_IHPSG13_8192x32_c4_2P_DEC04 +XSEL<4> ADDR_N_I<3> ADDR_N_I<2> ADDR_N_I<1> ADDR_N_I<0> CS00<4> ECLK_H<4> ++ ECLK_H<5> ECLK_B<4> ECLK_B<5> WL_O<79> WL_O<78> WL_O<77> WL_O<76> WL_O<75> ++ WL_O<74> WL_O<73> WL_O<72> WL_O<71> WL_O<70> WL_O<69> WL_O<68> WL_O<67> ++ WL_O<66> WL_O<65> WL_O<64> VDD VSS / RM_IHPSG13_8192x32_c4_2P_DEC04 +XSEL<3> ADDR_N_I<3> ADDR_N_I<2> ADDR_N_I<1> ADDR_N_I<0> CS00<3> ECLK_H<3> ++ ECLK_H<4> ECLK_B<3> ECLK_B<4> WL_O<63> WL_O<62> WL_O<61> WL_O<60> WL_O<59> ++ WL_O<58> WL_O<57> WL_O<56> WL_O<55> WL_O<54> WL_O<53> WL_O<52> WL_O<51> ++ WL_O<50> WL_O<49> WL_O<48> VDD VSS / RM_IHPSG13_8192x32_c4_2P_DEC04 +XSEL<2> ADDR_N_I<3> ADDR_N_I<2> ADDR_N_I<1> ADDR_N_I<0> CS00<2> ECLK_H<2> ++ ECLK_H<3> ECLK_B<2> ECLK_B<3> WL_O<47> WL_O<46> WL_O<45> WL_O<44> WL_O<43> ++ WL_O<42> WL_O<41> WL_O<40> WL_O<39> WL_O<38> WL_O<37> WL_O<36> WL_O<35> ++ WL_O<34> WL_O<33> WL_O<32> VDD VSS / RM_IHPSG13_8192x32_c4_2P_DEC04 +XSEL<1> ADDR_N_I<3> ADDR_N_I<2> ADDR_N_I<1> ADDR_N_I<0> CS00<1> ECLK_H<1> ++ ECLK_H<2> ECLK_B<1> ECLK_B<2> WL_O<31> WL_O<30> WL_O<29> WL_O<28> WL_O<27> ++ WL_O<26> WL_O<25> WL_O<24> WL_O<23> WL_O<22> WL_O<21> WL_O<20> WL_O<19> ++ WL_O<18> WL_O<17> WL_O<16> VDD VSS / RM_IHPSG13_8192x32_c4_2P_DEC04 +XSEL<0> ADDR_N_I<3> ADDR_N_I<2> ADDR_N_I<1> ADDR_N_I<0> CS00<0> ECLK_I ++ ECLK_H<1> ECLK_B<0> ECLK_B<1> WL_O<15> WL_O<14> WL_O<13> WL_O<12> WL_O<11> ++ WL_O<10> WL_O<9> WL_O<8> WL_O<7> WL_O<6> WL_O<5> WL_O<4> WL_O<3> WL_O<2> ++ WL_O<1> WL_O<0> VDD VSS / RM_IHPSG13_8192x32_c4_2P_DEC04 +XDEC10<4> ADDR_N_I<7> ADDR_N_I<6> CS_I CS04<2> VDD VSS / ++ RM_IHPSG13_8192x32_c4_2P_DEC02 +XDEC10<3> ADDR_N_I<5> ADDR_N_I<4> CS04<3> CS00<14> VDD VSS / ++ RM_IHPSG13_8192x32_c4_2P_DEC02 +XDEC10<2> ADDR_N_I<5> ADDR_N_I<4> CS04<2> CS00<10> VDD VSS / ++ RM_IHPSG13_8192x32_c4_2P_DEC02 +XDEC10<1> ADDR_N_I<5> ADDR_N_I<4> CS04<1> CS00<6> VDD VSS / ++ RM_IHPSG13_8192x32_c4_2P_DEC02 +XDEC10<0> ADDR_N_I<5> ADDR_N_I<4> CS04<0> CS00<2> VDD VSS / ++ RM_IHPSG13_8192x32_c4_2P_DEC02 +XL2<132> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<131> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<130> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<129> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<128> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<127> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<126> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<125> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<124> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<123> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<122> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<121> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<120> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<119> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<118> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<117> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<116> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<115> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<114> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<113> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<112> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<111> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<110> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<109> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<108> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<107> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<106> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<105> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<104> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<103> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<102> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<101> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<100> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<99> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<98> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<97> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<96> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<95> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<94> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<93> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<92> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<91> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<90> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<89> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<88> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<87> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<86> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<85> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<84> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<83> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<82> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<81> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<80> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<79> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<78> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<77> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<76> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<75> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<74> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<73> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<72> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<71> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<70> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<69> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<68> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<67> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<66> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<65> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<64> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<63> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<62> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<61> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<60> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<59> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<58> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<57> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<56> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<55> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<54> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<53> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<52> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<51> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<50> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<49> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<48> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<47> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<46> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<45> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<44> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<43> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<42> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<41> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<40> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<39> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<38> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<37> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<36> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<35> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<34> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<33> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<32> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<31> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<30> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<29> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<28> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<27> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<26> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<25> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<24> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<23> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<22> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<21> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<20> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<19> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<18> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<17> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<16> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<15> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<14> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<13> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<12> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<11> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<10> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<9> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<8> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<7> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<6> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<5> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<4> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<3> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<2> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<1> VDD VSS / RSC_IHPSG13_FILLCAP8 +XDEC00<4> ADDR_N_I<7> ADDR_N_I<6> CS_I CS04<0> VDD VSS / ++ RM_IHPSG13_8192x32_c4_2P_DEC00 +XDEC00<3> ADDR_N_I<5> ADDR_N_I<4> CS04<3> CS00<12> VDD VSS / ++ RM_IHPSG13_8192x32_c4_2P_DEC00 +XDEC00<2> ADDR_N_I<5> ADDR_N_I<4> CS04<2> CS00<8> VDD VSS / ++ RM_IHPSG13_8192x32_c4_2P_DEC00 +XDEC00<1> ADDR_N_I<5> ADDR_N_I<4> CS04<1> CS00<4> VDD VSS / ++ RM_IHPSG13_8192x32_c4_2P_DEC00 +XDEC00<0> ADDR_N_I<5> ADDR_N_I<4> CS04<0> CS00<0> VDD VSS / ++ RM_IHPSG13_8192x32_c4_2P_DEC00 +XDEC01<4> ADDR_N_I<7> ADDR_N_I<6> CS_I CS04<1> VDD VSS / ++ RM_IHPSG13_8192x32_c4_2P_DEC01 +XDEC01<3> ADDR_N_I<5> ADDR_N_I<4> CS04<3> CS00<13> VDD VSS / ++ RM_IHPSG13_8192x32_c4_2P_DEC01 +XDEC01<2> ADDR_N_I<5> ADDR_N_I<4> CS04<2> CS00<9> VDD VSS / ++ RM_IHPSG13_8192x32_c4_2P_DEC01 +XDEC01<1> ADDR_N_I<5> ADDR_N_I<4> CS04<1> CS00<5> VDD VSS / ++ RM_IHPSG13_8192x32_c4_2P_DEC01 +XDEC01<0> ADDR_N_I<5> ADDR_N_I<4> CS04<0> CS00<1> VDD VSS / ++ RM_IHPSG13_8192x32_c4_2P_DEC01 +.ENDS +.SUBCKT RM_IHPSG13_8192x32_c4_2P_ROWREG8 ACLK_N_I ADDR_I<7> ADDR_I<6> ADDR_I<5> ADDR_I<4> ++ ADDR_I<3> ADDR_I<2> ADDR_I<1> ADDR_I<0> ADDR_N_O<7> ADDR_N_O<6> ADDR_N_O<5> ++ ADDR_N_O<4> ADDR_N_O<3> ADDR_N_O<2> ADDR_N_O<1> ADDR_N_O<0> BIST_ADDR_I<7> ++ BIST_ADDR_I<6> BIST_ADDR_I<5> BIST_ADDR_I<4> BIST_ADDR_I<3> BIST_ADDR_I<2> ++ BIST_ADDR_I<1> BIST_ADDR_I<0> BIST_EN_I VDD VSS +XINV<7> q_int<7> qn_int<7> VDD VSS / RSC_IHPSG13_CINVX2 +XINV<6> q_int<6> qn_int<6> VDD VSS / RSC_IHPSG13_CINVX2 +XINV<5> q_int<5> qn_int<5> VDD VSS / RSC_IHPSG13_CINVX2 +XINV<4> q_int<4> qn_int<4> VDD VSS / RSC_IHPSG13_CINVX2 +XINV<3> q_int<3> qn_int<3> VDD VSS / RSC_IHPSG13_CINVX2 +XINV<2> q_int<2> qn_int<2> VDD VSS / RSC_IHPSG13_CINVX2 +XINV<1> q_int<1> qn_int<1> VDD VSS / RSC_IHPSG13_CINVX2 +XINV<0> q_int<0> qn_int<0> VDD VSS / RSC_IHPSG13_CINVX2 +XDRV<7> qn_int<7> ADDR_N_O<7> VDD VSS / RSC_IHPSG13_CINVX8 +XDRV<6> qn_int<6> ADDR_N_O<6> VDD VSS / RSC_IHPSG13_CINVX8 +XDRV<5> qn_int<5> ADDR_N_O<5> VDD VSS / RSC_IHPSG13_CINVX8 +XDRV<4> qn_int<4> ADDR_N_O<4> VDD VSS / RSC_IHPSG13_CINVX8 +XDRV<3> qn_int<3> ADDR_N_O<3> VDD VSS / RSC_IHPSG13_CINVX8 +XDRV<2> qn_int<2> ADDR_N_O<2> VDD VSS / RSC_IHPSG13_CINVX8 +XDRV<1> qn_int<1> ADDR_N_O<1> VDD VSS / RSC_IHPSG13_CINVX8 +XDRV<0> qn_int<0> ADDR_N_O<0> VDD VSS / RSC_IHPSG13_CINVX8 +XDFF<7> BIST_EN_I BIST_ADDR_I<7> ACLK_N_I ADDR_I<7> q_int<7> net2<0> VDD ++ VSS / RSC_IHPSG13_DFNQMX2IX1 +XDFF<6> BIST_EN_I BIST_ADDR_I<6> ACLK_N_I ADDR_I<6> q_int<6> net2<1> VDD ++ VSS / RSC_IHPSG13_DFNQMX2IX1 +XDFF<5> BIST_EN_I BIST_ADDR_I<5> ACLK_N_I ADDR_I<5> q_int<5> net2<2> VDD ++ VSS / RSC_IHPSG13_DFNQMX2IX1 +XDFF<4> BIST_EN_I BIST_ADDR_I<4> ACLK_N_I ADDR_I<4> q_int<4> net2<3> VDD ++ VSS / RSC_IHPSG13_DFNQMX2IX1 +XDFF<3> BIST_EN_I BIST_ADDR_I<3> ACLK_N_I ADDR_I<3> q_int<3> net2<4> VDD ++ VSS / RSC_IHPSG13_DFNQMX2IX1 +XDFF<2> BIST_EN_I BIST_ADDR_I<2> ACLK_N_I ADDR_I<2> q_int<2> net2<5> VDD ++ VSS / RSC_IHPSG13_DFNQMX2IX1 +XDFF<1> BIST_EN_I BIST_ADDR_I<1> ACLK_N_I ADDR_I<1> q_int<1> net2<6> VDD ++ VSS / RSC_IHPSG13_DFNQMX2IX1 +XDFF<0> BIST_EN_I BIST_ADDR_I<0> ACLK_N_I ADDR_I<0> q_int<0> net2<7> VDD ++ VSS / RSC_IHPSG13_DFNQMX2IX1 +XI11<4> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI11<3> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI11<2> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI11<1> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI10 VDD VSS / RSC_IHPSG13_FILLCAP4 +.ENDS +.SUBCKT RM_IHPSG13_8192x32_c4_2P_COLDEC4 ACLK_N ADDR<3> ADDR<2> ADDR<1> ADDR<0> ++ ADDR_COL<1> ADDR_COL<0> ADDR_DEC<7> ADDR_DEC<6> ADDR_DEC<5> ADDR_DEC<4> ++ ADDR_DEC<3> ADDR_DEC<2> ADDR_DEC<1> ADDR_DEC<0> BIST_ADDR<3> BIST_ADDR<2> ++ BIST_ADDR<1> BIST_ADDR<0> BIST_EN_I VDD VSS +XI1<7> PADR<0> PADR<1> PADR<2> addr_n<7> VDD VSS / RSC_IHPSG13_NAND3X2 +XI1<6> NADR<0> PADR<1> PADR<2> addr_n<6> VDD VSS / RSC_IHPSG13_NAND3X2 +XI1<5> PADR<0> NADR<1> PADR<2> addr_n<5> VDD VSS / RSC_IHPSG13_NAND3X2 +XI1<4> NADR<0> NADR<1> PADR<2> addr_n<4> VDD VSS / RSC_IHPSG13_NAND3X2 +XI1<3> PADR<0> PADR<1> NADR<2> addr_n<3> VDD VSS / RSC_IHPSG13_NAND3X2 +XI1<2> NADR<0> PADR<1> NADR<2> addr_n<2> VDD VSS / RSC_IHPSG13_NAND3X2 +XI1<1> PADR<0> NADR<1> NADR<2> addr_n<1> VDD VSS / RSC_IHPSG13_NAND3X2 +XI1<0> NADR<0> NADR<1> NADR<2> addr_n<0> VDD VSS / RSC_IHPSG13_NAND3X2 +XDFF<3> BIST_EN_I BIST_ADDR<3> ACLK_N ADDR<3> addr_int net12<0> VDD ++ VSS / RSC_IHPSG13_DFNQMX2IX1 +XDFF<2> BIST_EN_I BIST_ADDR<2> ACLK_N ADDR<2> padr_int<2> net12<1> VDD ++ VSS / RSC_IHPSG13_DFNQMX2IX1 +XDFF<1> BIST_EN_I BIST_ADDR<1> ACLK_N ADDR<1> padr_int<1> net12<2> VDD ++ VSS / RSC_IHPSG13_DFNQMX2IX1 +XDFF<0> BIST_EN_I BIST_ADDR<0> ACLK_N ADDR<0> padr_int<0> net12<3> VDD ++ VSS / RSC_IHPSG13_DFNQMX2IX1 +XI17<4> VDD VSS / RSC_IHPSG13_FILLCAP4 +XI17<3> VDD VSS / RSC_IHPSG13_FILLCAP4 +XI17<2> VDD VSS / RSC_IHPSG13_FILLCAP4 +XI17<1> VDD VSS / RSC_IHPSG13_FILLCAP4 +XI13<2> NADR<2> PADR<2> VDD VSS / RSC_IHPSG13_INVX2 +XI13<1> NADR<1> PADR<1> VDD VSS / RSC_IHPSG13_INVX2 +XI13<0> NADR<0> PADR<0> VDD VSS / RSC_IHPSG13_INVX2 +XI2<7> addr_n<7> ADDR_DEC<7> VDD VSS / RSC_IHPSG13_INVX2 +XI2<6> addr_n<6> ADDR_DEC<6> VDD VSS / RSC_IHPSG13_INVX2 +XI2<5> addr_n<5> ADDR_DEC<5> VDD VSS / RSC_IHPSG13_INVX2 +XI2<4> addr_n<4> ADDR_DEC<4> VDD VSS / RSC_IHPSG13_INVX2 +XI2<3> addr_n<3> ADDR_DEC<3> VDD VSS / RSC_IHPSG13_INVX2 +XI2<2> addr_n<2> ADDR_DEC<2> VDD VSS / RSC_IHPSG13_INVX2 +XI2<1> addr_n<1> ADDR_DEC<1> VDD VSS / RSC_IHPSG13_INVX2 +XI2<0> addr_n<0> ADDR_DEC<0> VDD VSS / RSC_IHPSG13_INVX2 +XI3<2> padr_int<2> NADR<2> VDD VSS / RSC_IHPSG13_INVX2 +XI3<1> padr_int<1> NADR<1> VDD VSS / RSC_IHPSG13_INVX2 +XI3<0> padr_int<0> NADR<0> VDD VSS / RSC_IHPSG13_INVX2 +XI14 addr_int ADDR_COL<0> VDD VSS / RSC_IHPSG13_CBUFX2 +XI16<8> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI16<7> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI16<6> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI16<5> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI16<4> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI16<3> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI16<2> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI16<1> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI15 ADDR_COL<1> VDD VSS / RSC_IHPSG13_TIEL +.ENDS +.SUBCKT RM_IHPSG13_8192x32_c4_2P_COLCTRL4 A_ADDR_COL A_ADDR_DEC<7> A_ADDR_DEC<6> ++ A_ADDR_DEC<5> A_ADDR_DEC<4> A_ADDR_DEC<3> A_ADDR_DEC<2> A_ADDR_DEC<1> ++ A_ADDR_DEC<0> A_BIST_BM_I A_BIST_DW_I A_BIST_EN_I A_BLC<15> A_BLC<14> ++ A_BLC<13> A_BLC<12> A_BLC<11> A_BLC<10> A_BLC<9> A_BLC<8> A_BLC<7> A_BLC<6> ++ A_BLC<5> A_BLC<4> A_BLC<3> A_BLC<2> A_BLC<1> A_BLC<0> A_BLT<15> A_BLT<14> ++ A_BLT<13> A_BLT<12> A_BLT<11> A_BLT<10> A_BLT<9> A_BLT<8> A_BLT<7> A_BLT<6> ++ A_BLT<5> A_BLT<4> A_BLT<3> A_BLT<2> A_BLT<1> A_BLT<0> A_BM_I A_DCLK_B_L ++ A_DCLK_B_R A_DCLK_L A_DCLK_R A_DR_O A_DW_I A_RCLK_B_L A_RCLK_B_R A_RCLK_L ++ A_RCLK_R A_TIEH_O A_WCLK_B_L A_WCLK_B_R A_WCLK_L A_WCLK_R B_ADDR_COL ++ B_ADDR_DEC<7> B_ADDR_DEC<6> B_ADDR_DEC<5> B_ADDR_DEC<4> B_ADDR_DEC<3> ++ B_ADDR_DEC<2> B_ADDR_DEC<1> B_ADDR_DEC<0> B_BIST_BM_I B_BIST_DW_I ++ B_BIST_EN_I B_BLC<15> B_BLC<14> B_BLC<13> B_BLC<12> B_BLC<11> B_BLC<10> ++ B_BLC<9> B_BLC<8> B_BLC<7> B_BLC<6> B_BLC<5> B_BLC<4> B_BLC<3> B_BLC<2> ++ B_BLC<1> B_BLC<0> B_BLT<15> B_BLT<14> B_BLT<13> B_BLT<12> B_BLT<11> ++ B_BLT<10> B_BLT<9> B_BLT<8> B_BLT<7> B_BLT<6> B_BLT<5> B_BLT<4> B_BLT<3> ++ B_BLT<2> B_BLT<1> B_BLT<0> B_BM_I B_DCLK_B_L B_DCLK_B_R B_DCLK_L B_DCLK_R ++ B_DR_O B_DW_I B_RCLK_B_L B_RCLK_B_R B_RCLK_L B_RCLK_R B_TIEH_O B_WCLK_B_L ++ B_WCLK_B_R B_WCLK_L B_WCLK_R VDD VSS +XB_I80 B_RCLK_B_L B_WCLK_B_L net041 VDD VSS / RSC_IHPSG13_AND2X2 +XA_I80 A_RCLK_B_L A_WCLK_B_L net21 VDD VSS / RSC_IHPSG13_AND2X2 +XB_I76 B_DI_N B_DO_WRITE_P B_WR_ZERO VDD VSS / RSC_IHPSG13_AND2X4 +XB_I75 B_DI_R B_DO_WRITE_P B_WR_ONE VDD VSS / RSC_IHPSG13_AND2X4 +XA_I76 A_DI_N A_DO_WRITE_P A_WR_ZERO VDD VSS / RSC_IHPSG13_AND2X4 +XA_I75 A_DI_R A_DO_WRITE_P A_WR_ONE VDD VSS / RSC_IHPSG13_AND2X4 +XI_FILL4<26> VDD VSS / RSC_IHPSG13_FILLCAP4 +XI_FILL4<25> VDD VSS / RSC_IHPSG13_FILLCAP4 +XI_FILL4<24> VDD VSS / RSC_IHPSG13_FILLCAP4 +XI_FILL4<23> VDD VSS / RSC_IHPSG13_FILLCAP4 +XI_FILL4<22> VDD VSS / RSC_IHPSG13_FILLCAP4 +XI_FILL4<21> VDD VSS / RSC_IHPSG13_FILLCAP4 +XI_FILL4<20> VDD VSS / RSC_IHPSG13_FILLCAP4 +XI_FILL4<19> VDD VSS / RSC_IHPSG13_FILLCAP4 +XI_FILL4<18> VDD VSS / RSC_IHPSG13_FILLCAP4 +XI_FILL4<17> VDD VSS / RSC_IHPSG13_FILLCAP4 +XI_FILL4<16> VDD VSS / RSC_IHPSG13_FILLCAP4 +XI_FILL4<15> VDD VSS / RSC_IHPSG13_FILLCAP4 +XI_FILL4<14> VDD VSS / RSC_IHPSG13_FILLCAP4 +XI_FILL4<13> VDD VSS / RSC_IHPSG13_FILLCAP4 +XI_FILL4<12> VDD VSS / RSC_IHPSG13_FILLCAP4 +XI_FILL4<11> VDD VSS / RSC_IHPSG13_FILLCAP4 +XI_FILL4<10> VDD VSS / RSC_IHPSG13_FILLCAP4 +XI_FILL4<9> VDD VSS / RSC_IHPSG13_FILLCAP4 +XI_FILL4<8> VDD VSS / RSC_IHPSG13_FILLCAP4 +XI_FILL4<7> VDD VSS / RSC_IHPSG13_FILLCAP4 +XI_FILL4<6> VDD VSS / RSC_IHPSG13_FILLCAP4 +XI_FILL4<5> VDD VSS / RSC_IHPSG13_FILLCAP4 +XI_FILL4<4> VDD VSS / RSC_IHPSG13_FILLCAP4 +XI_FILL4<3> VDD VSS / RSC_IHPSG13_FILLCAP4 +XI_FILL4<2> VDD VSS / RSC_IHPSG13_FILLCAP4 +XI_FILL4<1> VDD VSS / RSC_IHPSG13_FILLCAP4 +XB_I69 B_DCLK_L B_DCLK_B_L VDD VSS / RSC_IHPSG13_CINVX4 +XB_I50 B_WCLK_L B_WCLK_B_L VDD VSS / RSC_IHPSG13_CINVX4 +XB_EBUF B_RCLK_L B_RCLK_B_L VDD VSS / RSC_IHPSG13_CINVX4 +XB_INV<1> B_N0 B_P0 VDD VSS / RSC_IHPSG13_CINVX4 +XB_INV<0> B_ADDR_COL B_N0 VDD VSS / RSC_IHPSG13_CINVX4 +XA_I69 A_DCLK_L A_DCLK_B_L VDD VSS / RSC_IHPSG13_CINVX4 +XA_I50 A_WCLK_L A_WCLK_B_L VDD VSS / RSC_IHPSG13_CINVX4 +XA_EBUF A_RCLK_L A_RCLK_B_L VDD VSS / RSC_IHPSG13_CINVX4 +XA_INV<1> A_N0 A_P0 VDD VSS / RSC_IHPSG13_CINVX4 +XA_INV<0> A_ADDR_COL A_N0 VDD VSS / RSC_IHPSG13_CINVX4 +XB_I81<1> net041 B_PRE_N VDD VSS / RSC_IHPSG13_CINVX4_WN +XB_I81<0> net041 B_PRE_N VDD VSS / RSC_IHPSG13_CINVX4_WN +XA_I81<1> net21 A_PRE_N VDD VSS / RSC_IHPSG13_CINVX4_WN +XA_I81<0> net21 A_PRE_N VDD VSS / RSC_IHPSG13_CINVX4_WN +XA_R2 A_RCLK_L A_RCLK_R / RSC_IHPSG13_MET3RES +XA_I87 A_WCLK_L A_WCLK_R / RSC_IHPSG13_MET3RES +XA_I88 A_DCLK_L A_DCLK_R / RSC_IHPSG13_MET3RES +XA_I89 A_DCLK_B_L A_DCLK_B_R / RSC_IHPSG13_MET3RES +XA_I90 A_WCLK_B_L A_WCLK_B_R / RSC_IHPSG13_MET3RES +XA_I91 A_RCLK_B_L A_RCLK_B_R / RSC_IHPSG13_MET3RES +XB_R2 B_RCLK_L B_RCLK_R / RSC_IHPSG13_MET3RES +XB_I87 B_WCLK_L B_WCLK_R / RSC_IHPSG13_MET3RES +XB_I88 B_DCLK_L B_DCLK_R / RSC_IHPSG13_MET3RES +XB_I89 B_DCLK_B_L B_DCLK_B_R / RSC_IHPSG13_MET3RES +XB_I90 B_WCLK_B_L B_WCLK_B_R / RSC_IHPSG13_MET3RES +XB_I91 B_RCLK_B_L B_RCLK_B_R / RSC_IHPSG13_MET3RES +XA_ISENSE A_SAE A_BLC_SEL A_BLT_SEL net19 net20 VDD VSS / ++ RSC_IHPSG13_DFPQD_MSAFFX2 +XB_ISENSE B_SAE B_BLC_SEL B_BLT_SEL net037 net038 VDD VSS / ++ RSC_IHPSG13_DFPQD_MSAFFX2 +XAB_BLMUX<3> A_BLC<15> A_BLC<14> A_BLC<13> A_BLC<12> A_BLC_SEL A_BLT<15> ++ A_BLT<14> A_BLT<13> A_BLT<12> A_BLT_SEL A_PRE_N A_SEL_P<15> A_SEL_P<14> ++ A_SEL_P<13> A_SEL_P<12> A_WR_ONE A_WR_ZERO B_BLC<15> B_BLC<14> B_BLC<13> ++ B_BLC<12> B_BLC_SEL B_BLT<15> B_BLT<14> B_BLT<13> B_BLT<12> B_BLT_SEL ++ B_PRE_N B_SEL_P<15> B_SEL_P<14> B_SEL_P<13> B_SEL_P<12> B_WR_ONE B_WR_ZERO ++ VDD VSS / RM_IHPSG13_8192x32_c4_2P_BLDRV +XAB_BLMUX<2> A_BLC<11> A_BLC<10> A_BLC<9> A_BLC<8> A_BLC_SEL A_BLT<11> ++ A_BLT<10> A_BLT<9> A_BLT<8> A_BLT_SEL A_PRE_N A_SEL_P<11> A_SEL_P<10> ++ A_SEL_P<9> A_SEL_P<8> A_WR_ONE A_WR_ZERO B_BLC<11> B_BLC<10> B_BLC<9> ++ B_BLC<8> B_BLC_SEL B_BLT<11> B_BLT<10> B_BLT<9> B_BLT<8> B_BLT_SEL B_PRE_N ++ B_SEL_P<11> B_SEL_P<10> B_SEL_P<9> B_SEL_P<8> B_WR_ONE B_WR_ZERO VDD ++ VSS / RM_IHPSG13_8192x32_c4_2P_BLDRV +XAB_BLMUX<1> A_BLC<7> A_BLC<6> A_BLC<5> A_BLC<4> A_BLC_SEL A_BLT<7> A_BLT<6> ++ A_BLT<5> A_BLT<4> A_BLT_SEL A_PRE_N A_SEL_P<7> A_SEL_P<6> A_SEL_P<5> ++ A_SEL_P<4> A_WR_ONE A_WR_ZERO B_BLC<7> B_BLC<6> B_BLC<5> B_BLC<4> B_BLC_SEL ++ B_BLT<7> B_BLT<6> B_BLT<5> B_BLT<4> B_BLT_SEL B_PRE_N B_SEL_P<7> B_SEL_P<6> ++ B_SEL_P<5> B_SEL_P<4> B_WR_ONE B_WR_ZERO VDD VSS / ++ RM_IHPSG13_8192x32_c4_2P_BLDRV +XAB_BLMUX<0> A_BLC<3> A_BLC<2> A_BLC<1> A_BLC<0> A_BLC_SEL A_BLT<3> A_BLT<2> ++ A_BLT<1> A_BLT<0> A_BLT_SEL A_PRE_N A_SEL_P<3> A_SEL_P<2> A_SEL_P<1> ++ A_SEL_P<0> A_WR_ONE A_WR_ZERO B_BLC<3> B_BLC<2> B_BLC<1> B_BLC<0> B_BLC_SEL ++ B_BLT<3> B_BLT<2> B_BLT<1> B_BLT<0> B_BLT_SEL B_PRE_N B_SEL_P<3> B_SEL_P<2> ++ B_SEL_P<1> B_SEL_P<0> B_WR_ONE B_WR_ZERO VDD VSS / ++ RM_IHPSG13_8192x32_c4_2P_BLDRV +XA_I51 net19 A_DR_O VDD VSS / RSC_IHPSG13_INVX4 +XB_I51 net037 B_DR_O VDD VSS / RSC_IHPSG13_INVX4 +XA_I78 A_RCLK_B_L A_SAE VDD VSS / RSC_IHPSG13_CBUFX2 +XB_I78 B_RCLK_B_L B_SAE VDD VSS / RSC_IHPSG13_CBUFX2 +XA_DREG A_BIST_EN_I A_BIST_DW_I A_DCLK_B_L A_DW_I A_DI_R net22 VDD VSS ++ / RSC_IHPSG13_DFNQMX2IX1 +XB_DREG B_BIST_EN_I B_BIST_DW_I B_DCLK_B_L B_DW_I B_DI_R net046 VDD ++ VSS / RSC_IHPSG13_DFNQMX2IX1 +XB_BREG B_BIST_EN_I B_BIST_BM_I B_DCLK_B_L B_BM_I B_BM_R net045 VDD ++ VSS / RSC_IHPSG13_DFNQMX2IX1 +XA_BREG A_BIST_EN_I A_BIST_BM_I A_DCLK_B_L A_BM_I A_BM_R net24 VDD VSS ++ / RSC_IHPSG13_DFNQMX2IX1 +XA_DEC3INV<15> net23<0> A_SEL_P<15> VDD VSS / RSC_IHPSG13_INVX2 +XA_DEC3INV<14> net23<1> A_SEL_P<14> VDD VSS / RSC_IHPSG13_INVX2 +XA_DEC3INV<13> net23<2> A_SEL_P<13> VDD VSS / RSC_IHPSG13_INVX2 +XA_DEC3INV<12> net23<3> A_SEL_P<12> VDD VSS / RSC_IHPSG13_INVX2 +XA_DEC3INV<11> net23<4> A_SEL_P<11> VDD VSS / RSC_IHPSG13_INVX2 +XA_DEC3INV<10> net23<5> A_SEL_P<10> VDD VSS / RSC_IHPSG13_INVX2 +XA_DEC3INV<9> net23<6> A_SEL_P<9> VDD VSS / RSC_IHPSG13_INVX2 +XA_DEC3INV<8> net23<7> A_SEL_P<8> VDD VSS / RSC_IHPSG13_INVX2 +XA_DEC3INV<7> net23<8> A_SEL_P<7> VDD VSS / RSC_IHPSG13_INVX2 +XA_DEC3INV<6> net23<9> A_SEL_P<6> VDD VSS / RSC_IHPSG13_INVX2 +XA_DEC3INV<5> net23<10> A_SEL_P<5> VDD VSS / RSC_IHPSG13_INVX2 +XA_DEC3INV<4> net23<11> A_SEL_P<4> VDD VSS / RSC_IHPSG13_INVX2 +XA_DEC3INV<3> net23<12> A_SEL_P<3> VDD VSS / RSC_IHPSG13_INVX2 +XA_DEC3INV<2> net23<13> A_SEL_P<2> VDD VSS / RSC_IHPSG13_INVX2 +XA_DEC3INV<1> net23<14> A_SEL_P<1> VDD VSS / RSC_IHPSG13_INVX2 +XA_DEC3INV<0> net23<15> A_SEL_P<0> VDD VSS / RSC_IHPSG13_INVX2 +XA_I83 A_BM_R A_BM_N VDD VSS / RSC_IHPSG13_INVX2 +XA_I49 A_DI_R A_DI_N VDD VSS / RSC_IHPSG13_INVX2 +XB_DEC3INV<15> net044<0> B_SEL_P<15> VDD VSS / RSC_IHPSG13_INVX2 +XB_DEC3INV<14> net044<1> B_SEL_P<14> VDD VSS / RSC_IHPSG13_INVX2 +XB_DEC3INV<13> net044<2> B_SEL_P<13> VDD VSS / RSC_IHPSG13_INVX2 +XB_DEC3INV<12> net044<3> B_SEL_P<12> VDD VSS / RSC_IHPSG13_INVX2 +XB_DEC3INV<11> net044<4> B_SEL_P<11> VDD VSS / RSC_IHPSG13_INVX2 +XB_DEC3INV<10> net044<5> B_SEL_P<10> VDD VSS / RSC_IHPSG13_INVX2 +XB_DEC3INV<9> net044<6> B_SEL_P<9> VDD VSS / RSC_IHPSG13_INVX2 +XB_DEC3INV<8> net044<7> B_SEL_P<8> VDD VSS / RSC_IHPSG13_INVX2 +XB_DEC3INV<7> net044<8> B_SEL_P<7> VDD VSS / RSC_IHPSG13_INVX2 +XB_DEC3INV<6> net044<9> B_SEL_P<6> VDD VSS / RSC_IHPSG13_INVX2 +XB_DEC3INV<5> net044<10> B_SEL_P<5> VDD VSS / RSC_IHPSG13_INVX2 +XB_DEC3INV<4> net044<11> B_SEL_P<4> VDD VSS / RSC_IHPSG13_INVX2 +XB_DEC3INV<3> net044<12> B_SEL_P<3> VDD VSS / RSC_IHPSG13_INVX2 +XB_DEC3INV<2> net044<13> B_SEL_P<2> VDD VSS / RSC_IHPSG13_INVX2 +XB_DEC3INV<1> net044<14> B_SEL_P<1> VDD VSS / RSC_IHPSG13_INVX2 +XB_DEC3INV<0> net044<15> B_SEL_P<0> VDD VSS / RSC_IHPSG13_INVX2 +XB_I83 B_BM_R B_BM_N VDD VSS / RSC_IHPSG13_INVX2 +XB_I49 B_DI_R B_DI_N VDD VSS / RSC_IHPSG13_INVX2 +XI_FILL8<20> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI_FILL8<19> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI_FILL8<18> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI_FILL8<17> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI_FILL8<16> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI_FILL8<15> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI_FILL8<14> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI_FILL8<13> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI_FILL8<12> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI_FILL8<11> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI_FILL8<10> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI_FILL8<9> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI_FILL8<8> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI_FILL8<7> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI_FILL8<6> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI_FILL8<5> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI_FILL8<4> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI_FILL8<3> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI_FILL8<2> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI_FILL8<1> VDD VSS / RSC_IHPSG13_FILLCAP8 +XA_I44 A_BM_N A_WCLK_B_L A_DO_WRITE_P VDD VSS / RSC_IHPSG13_NOR2X2 +XB_I44 B_BM_N B_WCLK_B_L B_DO_WRITE_P VDD VSS / RSC_IHPSG13_NOR2X2 +XA_DEC3<15> A_P0 A_ADDR_DEC<7> net23<0> VDD VSS / RSC_IHPSG13_NAND2X2 +XA_DEC3<14> A_P0 A_ADDR_DEC<6> net23<1> VDD VSS / RSC_IHPSG13_NAND2X2 +XA_DEC3<13> A_P0 A_ADDR_DEC<5> net23<2> VDD VSS / RSC_IHPSG13_NAND2X2 +XA_DEC3<12> A_P0 A_ADDR_DEC<4> net23<3> VDD VSS / RSC_IHPSG13_NAND2X2 +XA_DEC3<11> A_P0 A_ADDR_DEC<3> net23<4> VDD VSS / RSC_IHPSG13_NAND2X2 +XA_DEC3<10> A_P0 A_ADDR_DEC<2> net23<5> VDD VSS / RSC_IHPSG13_NAND2X2 +XA_DEC3<9> A_P0 A_ADDR_DEC<1> net23<6> VDD VSS / RSC_IHPSG13_NAND2X2 +XA_DEC3<8> A_P0 A_ADDR_DEC<0> net23<7> VDD VSS / RSC_IHPSG13_NAND2X2 +XA_DEC3<7> A_N0 A_ADDR_DEC<7> net23<8> VDD VSS / RSC_IHPSG13_NAND2X2 +XA_DEC3<6> A_N0 A_ADDR_DEC<6> net23<9> VDD VSS / RSC_IHPSG13_NAND2X2 +XA_DEC3<5> A_N0 A_ADDR_DEC<5> net23<10> VDD VSS / RSC_IHPSG13_NAND2X2 +XA_DEC3<4> A_N0 A_ADDR_DEC<4> net23<11> VDD VSS / RSC_IHPSG13_NAND2X2 +XA_DEC3<3> A_N0 A_ADDR_DEC<3> net23<12> VDD VSS / RSC_IHPSG13_NAND2X2 +XA_DEC3<2> A_N0 A_ADDR_DEC<2> net23<13> VDD VSS / RSC_IHPSG13_NAND2X2 +XA_DEC3<1> A_N0 A_ADDR_DEC<1> net23<14> VDD VSS / RSC_IHPSG13_NAND2X2 +XA_DEC3<0> A_N0 A_ADDR_DEC<0> net23<15> VDD VSS / RSC_IHPSG13_NAND2X2 +XB_DEC3<15> B_P0 B_ADDR_DEC<7> net044<0> VDD VSS / RSC_IHPSG13_NAND2X2 +XB_DEC3<14> B_P0 B_ADDR_DEC<6> net044<1> VDD VSS / RSC_IHPSG13_NAND2X2 +XB_DEC3<13> B_P0 B_ADDR_DEC<5> net044<2> VDD VSS / RSC_IHPSG13_NAND2X2 +XB_DEC3<12> B_P0 B_ADDR_DEC<4> net044<3> VDD VSS / RSC_IHPSG13_NAND2X2 +XB_DEC3<11> B_P0 B_ADDR_DEC<3> net044<4> VDD VSS / RSC_IHPSG13_NAND2X2 +XB_DEC3<10> B_P0 B_ADDR_DEC<2> net044<5> VDD VSS / RSC_IHPSG13_NAND2X2 +XB_DEC3<9> B_P0 B_ADDR_DEC<1> net044<6> VDD VSS / RSC_IHPSG13_NAND2X2 +XB_DEC3<8> B_P0 B_ADDR_DEC<0> net044<7> VDD VSS / RSC_IHPSG13_NAND2X2 +XB_DEC3<7> B_N0 B_ADDR_DEC<7> net044<8> VDD VSS / RSC_IHPSG13_NAND2X2 +XB_DEC3<6> B_N0 B_ADDR_DEC<6> net044<9> VDD VSS / RSC_IHPSG13_NAND2X2 +XB_DEC3<5> B_N0 B_ADDR_DEC<5> net044<10> VDD VSS / RSC_IHPSG13_NAND2X2 +XB_DEC3<4> B_N0 B_ADDR_DEC<4> net044<11> VDD VSS / RSC_IHPSG13_NAND2X2 +XB_DEC3<3> B_N0 B_ADDR_DEC<3> net044<12> VDD VSS / RSC_IHPSG13_NAND2X2 +XB_DEC3<2> B_N0 B_ADDR_DEC<2> net044<13> VDD VSS / RSC_IHPSG13_NAND2X2 +XB_DEC3<1> B_N0 B_ADDR_DEC<1> net044<14> VDD VSS / RSC_IHPSG13_NAND2X2 +XB_DEC3<0> B_N0 B_ADDR_DEC<0> net044<15> VDD VSS / RSC_IHPSG13_NAND2X2 +XB_BM_TIEH B_TIEH_O VDD VSS / RSC_IHPSG13_TIEH +XA_BM_TIEH A_TIEH_O VDD VSS / RSC_IHPSG13_TIEH +.ENDS + + +.SUBCKT RM_IHPSG13_8192x32_c4_2P_ROWDEC5 ADDR_N_I<4> ADDR_N_I<3> ADDR_N_I<2> ADDR_N_I<1> ++ ADDR_N_I<0> CS_I ECLK_I WL_O<31> WL_O<30> WL_O<29> WL_O<28> WL_O<27> ++ WL_O<26> WL_O<25> WL_O<24> WL_O<23> WL_O<22> WL_O<21> WL_O<20> WL_O<19> ++ WL_O<18> WL_O<17> WL_O<16> WL_O<15> WL_O<14> WL_O<13> WL_O<12> WL_O<11> ++ WL_O<10> WL_O<9> WL_O<8> WL_O<7> WL_O<6> WL_O<5> WL_O<4> WL_O<3> WL_O<2> ++ WL_O<1> WL_O<0> VDD VSS +XDEC00 ADDR_N_I<5> ADDR_N_I<4> CS_I CS00<0> VDD VSS / ++ RM_IHPSG13_8192x32_c4_2P_DEC00 +XSEL<1> ADDR_N_I<3> ADDR_N_I<2> ADDR_N_I<1> ADDR_N_I<0> CS00<1> ECLK_H<1> ++ ECLK_H<2> ECLK_B<1> ECLK_B<2> WL_O<31> WL_O<30> WL_O<29> WL_O<28> WL_O<27> ++ WL_O<26> WL_O<25> WL_O<24> WL_O<23> WL_O<22> WL_O<21> WL_O<20> WL_O<19> ++ WL_O<18> WL_O<17> WL_O<16> VDD VSS / RM_IHPSG13_8192x32_c4_2P_DEC04 +XSEL<0> ADDR_N_I<3> ADDR_N_I<2> ADDR_N_I<1> ADDR_N_I<0> CS00<0> ECLK_I ++ ECLK_H<1> ECLK_B<0> ECLK_B<1> WL_O<15> WL_O<14> WL_O<13> WL_O<12> WL_O<11> ++ WL_O<10> WL_O<9> WL_O<8> WL_O<7> WL_O<6> WL_O<5> WL_O<4> WL_O<3> WL_O<2> ++ WL_O<1> WL_O<0> VDD VSS / RM_IHPSG13_8192x32_c4_2P_DEC04 +XDEC01 ADDR_N_I<5> ADDR_N_I<4> CS_I CS00<1> VDD VSS / ++ RM_IHPSG13_8192x32_c4_2P_DEC01 +XL2<18> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<17> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<16> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<15> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<14> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<13> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<12> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<11> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<10> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<9> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<8> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<7> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<6> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<5> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<4> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<3> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<2> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<1> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI0 ADDR_N_I<5> VDD VSS / RSC_IHPSG13_TIEL +.ENDS +.SUBCKT RM_IHPSG13_8192x32_c4_2P_ROWREG5 ACLK_N_I ADDR_I<4> ADDR_I<3> ADDR_I<2> ADDR_I<1> ++ ADDR_I<0> ADDR_N_O<4> ADDR_N_O<3> ADDR_N_O<2> ADDR_N_O<1> ADDR_N_O<0> ++ BIST_ADDR_I<4> BIST_ADDR_I<3> BIST_ADDR_I<2> BIST_ADDR_I<1> BIST_ADDR_I<0> ++ BIST_EN_I VDD VSS +XINV<4> q_int<4> qn_int<4> VDD VSS / RSC_IHPSG13_CINVX2 +XINV<3> q_int<3> qn_int<3> VDD VSS / RSC_IHPSG13_CINVX2 +XINV<2> q_int<2> qn_int<2> VDD VSS / RSC_IHPSG13_CINVX2 +XINV<1> q_int<1> qn_int<1> VDD VSS / RSC_IHPSG13_CINVX2 +XINV<0> q_int<0> qn_int<0> VDD VSS / RSC_IHPSG13_CINVX2 +XDRV<4> qn_int<4> ADDR_N_O<4> VDD VSS / RSC_IHPSG13_CINVX8 +XDRV<3> qn_int<3> ADDR_N_O<3> VDD VSS / RSC_IHPSG13_CINVX8 +XDRV<2> qn_int<2> ADDR_N_O<2> VDD VSS / RSC_IHPSG13_CINVX8 +XDRV<1> qn_int<1> ADDR_N_O<1> VDD VSS / RSC_IHPSG13_CINVX8 +XDRV<0> qn_int<0> ADDR_N_O<0> VDD VSS / RSC_IHPSG13_CINVX8 +XDFF<4> BIST_EN_I BIST_ADDR_I<4> ACLK_N_I ADDR_I<4> q_int<4> net2<0> VDD ++ VSS / RSC_IHPSG13_DFNQMX2IX1 +XDFF<3> BIST_EN_I BIST_ADDR_I<3> ACLK_N_I ADDR_I<3> q_int<3> net2<1> VDD ++ VSS / RSC_IHPSG13_DFNQMX2IX1 +XDFF<2> BIST_EN_I BIST_ADDR_I<2> ACLK_N_I ADDR_I<2> q_int<2> net2<2> VDD ++ VSS / RSC_IHPSG13_DFNQMX2IX1 +XDFF<1> BIST_EN_I BIST_ADDR_I<1> ACLK_N_I ADDR_I<1> q_int<1> net2<3> VDD ++ VSS / RSC_IHPSG13_DFNQMX2IX1 +XDFF<0> BIST_EN_I BIST_ADDR_I<0> ACLK_N_I ADDR_I<0> q_int<0> net2<4> VDD ++ VSS / RSC_IHPSG13_DFNQMX2IX1 +XI11<16> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI11<15> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI11<14> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI11<13> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI11<12> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI11<11> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI11<10> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI11<9> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI11<8> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI11<7> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI11<6> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI11<5> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI11<4> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI11<3> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI11<2> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI11<1> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI12<3> VDD VSS / RSC_IHPSG13_FILLCAP4 +XI12<2> VDD VSS / RSC_IHPSG13_FILLCAP4 +XI12<1> VDD VSS / RSC_IHPSG13_FILLCAP4 +XI12<0> VDD VSS / RSC_IHPSG13_FILLCAP4 +.ENDS + + +.SUBCKT RM_IHPSG13_8192x32_c4_2P_COLDEC3 ACLK_N ADDR<2> ADDR<1> ADDR<0> ADDR_COL<1> ++ ADDR_COL<0> ADDR_DEC<7> ADDR_DEC<6> ADDR_DEC<5> ADDR_DEC<4> ADDR_DEC<3> ++ ADDR_DEC<2> ADDR_DEC<1> ADDR_DEC<0> BIST_ADDR<2> BIST_ADDR<1> BIST_ADDR<0> ++ BIST_EN_I VDD VSS +XI1<7> PADR<0> PADR<1> PADR<2> addr_n<7> VDD VSS / RSC_IHPSG13_NAND3X2 +XI1<6> NADR<0> PADR<1> PADR<2> addr_n<6> VDD VSS / RSC_IHPSG13_NAND3X2 +XI1<5> PADR<0> NADR<1> PADR<2> addr_n<5> VDD VSS / RSC_IHPSG13_NAND3X2 +XI1<4> NADR<0> NADR<1> PADR<2> addr_n<4> VDD VSS / RSC_IHPSG13_NAND3X2 +XI1<3> PADR<0> PADR<1> NADR<2> addr_n<3> VDD VSS / RSC_IHPSG13_NAND3X2 +XI1<2> NADR<0> PADR<1> NADR<2> addr_n<2> VDD VSS / RSC_IHPSG13_NAND3X2 +XI1<1> PADR<0> NADR<1> NADR<2> addr_n<1> VDD VSS / RSC_IHPSG13_NAND3X2 +XI1<0> NADR<0> NADR<1> NADR<2> addr_n<0> VDD VSS / RSC_IHPSG13_NAND3X2 +XDFF<2> BIST_EN_I BIST_ADDR<2> ACLK_N ADDR<2> padr_int<2> net13<0> VDD ++ VSS / RSC_IHPSG13_DFNQMX2IX1 +XDFF<1> BIST_EN_I BIST_ADDR<1> ACLK_N ADDR<1> padr_int<1> net13<1> VDD ++ VSS / RSC_IHPSG13_DFNQMX2IX1 +XDFF<0> BIST_EN_I BIST_ADDR<0> ACLK_N ADDR<0> padr_int<0> net13<2> VDD ++ VSS / RSC_IHPSG13_DFNQMX2IX1 +XI15<1> ADDR_COL<1> VDD VSS / RSC_IHPSG13_TIEL +XI15<0> ADDR_COL<0> VDD VSS / RSC_IHPSG13_TIEL +XI13<2> NADR<2> PADR<2> VDD VSS / RSC_IHPSG13_INVX2 +XI13<1> NADR<1> PADR<1> VDD VSS / RSC_IHPSG13_INVX2 +XI13<0> NADR<0> PADR<0> VDD VSS / RSC_IHPSG13_INVX2 +XI3<2> padr_int<2> NADR<2> VDD VSS / RSC_IHPSG13_INVX2 +XI3<1> padr_int<1> NADR<1> VDD VSS / RSC_IHPSG13_INVX2 +XI3<0> padr_int<0> NADR<0> VDD VSS / RSC_IHPSG13_INVX2 +XI2<7> addr_n<7> ADDR_DEC<7> VDD VSS / RSC_IHPSG13_INVX2 +XI2<6> addr_n<6> ADDR_DEC<6> VDD VSS / RSC_IHPSG13_INVX2 +XI2<5> addr_n<5> ADDR_DEC<5> VDD VSS / RSC_IHPSG13_INVX2 +XI2<4> addr_n<4> ADDR_DEC<4> VDD VSS / RSC_IHPSG13_INVX2 +XI2<3> addr_n<3> ADDR_DEC<3> VDD VSS / RSC_IHPSG13_INVX2 +XI2<2> addr_n<2> ADDR_DEC<2> VDD VSS / RSC_IHPSG13_INVX2 +XI2<1> addr_n<1> ADDR_DEC<1> VDD VSS / RSC_IHPSG13_INVX2 +XI2<0> addr_n<0> ADDR_DEC<0> VDD VSS / RSC_IHPSG13_INVX2 +XI17<4> VDD VSS / RSC_IHPSG13_FILLCAP4 +XI17<3> VDD VSS / RSC_IHPSG13_FILLCAP4 +XI17<2> VDD VSS / RSC_IHPSG13_FILLCAP4 +XI17<1> VDD VSS / RSC_IHPSG13_FILLCAP4 +XI16<11> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI16<10> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI16<9> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI16<8> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI16<7> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI16<6> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI16<5> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI16<4> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI16<3> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI16<2> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI16<1> VDD VSS / RSC_IHPSG13_FILLCAP8 +.ENDS +.SUBCKT RSC_IHPSG13_DFPQD_MSAFFX2P CP DN DP QN QP VDD VSS +XI_AMP CP DN DP QN QP VDD VSS / RSC_IHPSG13_DFPQD_MSAFFX2 +.ENDS +.SUBCKT RM_IHPSG13_8192x32_c4_2P_COLCTRL3 A_ADDR_DEC<7> A_ADDR_DEC<6> A_ADDR_DEC<5> ++ A_ADDR_DEC<4> A_ADDR_DEC<3> A_ADDR_DEC<2> A_ADDR_DEC<1> A_ADDR_DEC<0> ++ A_BIST_BM_I A_BIST_DW_I A_BIST_EN_I A_BLC<7> A_BLC<6> A_BLC<5> A_BLC<4> ++ A_BLC<3> A_BLC<2> A_BLC<1> A_BLC<0> A_BLT<7> A_BLT<6> A_BLT<5> A_BLT<4> ++ A_BLT<3> A_BLT<2> A_BLT<1> A_BLT<0> A_BM_I A_DCLK_B_L A_DCLK_B_R A_DCLK_L ++ A_DCLK_R A_DR_O A_DW_I A_RCLK_B_L A_RCLK_B_R A_RCLK_L A_RCLK_R A_TIEH_O ++ A_WCLK_B_L A_WCLK_B_R A_WCLK_L A_WCLK_R B_ADDR_DEC<7> B_ADDR_DEC<6> ++ B_ADDR_DEC<5> B_ADDR_DEC<4> B_ADDR_DEC<3> B_ADDR_DEC<2> B_ADDR_DEC<1> ++ B_ADDR_DEC<0> B_BIST_BM_I B_BIST_DW_I B_BIST_EN_I B_BLC<7> B_BLC<6> B_BLC<5> ++ B_BLC<4> B_BLC<3> B_BLC<2> B_BLC<1> B_BLC<0> B_BLT<7> B_BLT<6> B_BLT<5> ++ B_BLT<4> B_BLT<3> B_BLT<2> B_BLT<1> B_BLT<0> B_BM_I B_DCLK_B_L B_DCLK_B_R ++ B_DCLK_L B_DCLK_R B_DR_O B_DW_I B_RCLK_B_L B_RCLK_B_R B_RCLK_L B_RCLK_R ++ B_TIEH_O B_WCLK_B_L B_WCLK_B_R B_WCLK_L B_WCLK_R VDD VSS +XB_DREG B_BIST_EN_I B_BIST_DW_I B_DCLK_B_L B_DW_I B_DI_R net044 VDD ++ VSS / RSC_IHPSG13_DFNQMX2IX1 +XB_BREG B_BIST_EN_I B_BIST_BM_I B_DCLK_B_L B_BM_I B_BM_R net043 VDD ++ VSS / RSC_IHPSG13_DFNQMX2IX1 +XA_DREG A_BIST_EN_I A_BIST_DW_I A_DCLK_B_L A_DW_I A_DI_R net22 VDD VSS ++ / RSC_IHPSG13_DFNQMX2IX1 +XA_BREG A_BIST_EN_I A_BIST_BM_I A_DCLK_B_L A_BM_I A_BM_R net23 VDD VSS ++ / RSC_IHPSG13_DFNQMX2IX1 +XI_FILL8<11> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI_FILL8<10> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI_FILL8<9> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI_FILL8<8> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI_FILL8<7> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI_FILL8<6> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI_FILL8<5> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI_FILL8<4> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI_FILL8<3> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI_FILL8<2> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI_FILL8<1> VDD VSS / RSC_IHPSG13_FILLCAP8 +XB_I51 net037 B_DR_O VDD VSS / RSC_IHPSG13_INVX4 +XA_I51 net19 A_DR_O VDD VSS / RSC_IHPSG13_INVX4 +XB_I44 B_BM_N B_WCLK_B_L B_DO_WRITE_P VDD VSS / RSC_IHPSG13_NOR2X2 +XA_I44 A_BM_N A_WCLK_B_L A_DO_WRITE_P VDD VSS / RSC_IHPSG13_NOR2X2 +XB_BM_TIEH B_TIEH_O VDD VSS / RSC_IHPSG13_TIEH +XA_BM_TIEH A_TIEH_O VDD VSS / RSC_IHPSG13_TIEH +XB_ISENSE B_SAE B_BLC_SEL B_BLT_SEL net037 net038 VDD VSS / ++ RSC_IHPSG13_DFPQD_MSAFFX2P +XA_ISENSE A_SAE A_BLC_SEL A_BLT_SEL net19 net20 VDD VSS / ++ RSC_IHPSG13_DFPQD_MSAFFX2P +XB_I49 B_DI_R B_DI_N VDD VSS / RSC_IHPSG13_INVX2 +XB_I83 B_BM_R B_BM_N VDD VSS / RSC_IHPSG13_INVX2 +XA_I49 A_DI_R A_DI_N VDD VSS / RSC_IHPSG13_INVX2 +XA_I83 A_BM_R A_BM_N VDD VSS / RSC_IHPSG13_INVX2 +XB_I69 B_DCLK_L B_DCLK_B_L VDD VSS / RSC_IHPSG13_CINVX2 +XB_I50 B_WCLK_L B_WCLK_B_L VDD VSS / RSC_IHPSG13_CINVX2 +XB_EBUF B_RCLK_L B_RCLK_B_L VDD VSS / RSC_IHPSG13_CINVX2 +XA_I69 A_DCLK_L A_DCLK_B_L VDD VSS / RSC_IHPSG13_CINVX2 +XA_I50 A_WCLK_L A_WCLK_B_L VDD VSS / RSC_IHPSG13_CINVX2 +XA_EBUF A_RCLK_L A_RCLK_B_L VDD VSS / RSC_IHPSG13_CINVX2 +XAB_BLMUX<1> A_BLC<7> A_BLC<6> A_BLC<5> A_BLC<4> A_BLC_SEL A_BLT<7> A_BLT<6> ++ A_BLT<5> A_BLT<4> A_BLT_SEL A_PRE_N A_ADDR_DEC<7> A_ADDR_DEC<6> ++ A_ADDR_DEC<5> A_ADDR_DEC<4> A_WR_ONE A_WR_ZERO B_BLC<7> B_BLC<6> B_BLC<5> ++ B_BLC<4> B_BLC_SEL B_BLT<7> B_BLT<6> B_BLT<5> B_BLT<4> B_BLT_SEL B_PRE_N ++ B_ADDR_DEC<7> B_ADDR_DEC<6> B_ADDR_DEC<5> B_ADDR_DEC<4> B_WR_ONE B_WR_ZERO ++ VDD VSS / RM_IHPSG13_8192x32_c4_2P_BLDRV +XAB_BLMUX<0> A_BLC<3> A_BLC<2> A_BLC<1> A_BLC<0> A_BLC_SEL A_BLT<3> A_BLT<2> ++ A_BLT<1> A_BLT<0> A_BLT_SEL A_PRE_N A_ADDR_DEC<3> A_ADDR_DEC<2> ++ A_ADDR_DEC<1> A_ADDR_DEC<0> A_WR_ONE A_WR_ZERO B_BLC<3> B_BLC<2> B_BLC<1> ++ B_BLC<0> B_BLC_SEL B_BLT<3> B_BLT<2> B_BLT<1> B_BLT<0> B_BLT_SEL B_PRE_N ++ B_ADDR_DEC<3> B_ADDR_DEC<2> B_ADDR_DEC<1> B_ADDR_DEC<0> B_WR_ONE B_WR_ZERO ++ VDD VSS / RM_IHPSG13_8192x32_c4_2P_BLDRV +XB_I78 B_RCLK_B_L B_SAE VDD VSS / RSC_IHPSG13_CBUFX2 +XA_I78 A_RCLK_B_L A_SAE VDD VSS / RSC_IHPSG13_CBUFX2 +XB_I88 B_DCLK_L B_DCLK_R / RSC_IHPSG13_MET3RES +XB_I87 B_WCLK_L B_WCLK_R / RSC_IHPSG13_MET3RES +XB_R2 B_RCLK_L B_RCLK_R / RSC_IHPSG13_MET3RES +XB_I91 B_RCLK_B_L B_RCLK_B_R / RSC_IHPSG13_MET3RES +XB_I90 B_WCLK_B_L B_WCLK_B_R / RSC_IHPSG13_MET3RES +XB_I89 B_DCLK_B_L B_DCLK_B_R / RSC_IHPSG13_MET3RES +XA_I88 A_DCLK_L A_DCLK_R / RSC_IHPSG13_MET3RES +XA_I87 A_WCLK_L A_WCLK_R / RSC_IHPSG13_MET3RES +XA_R2 A_RCLK_L A_RCLK_R / RSC_IHPSG13_MET3RES +XA_I91 A_RCLK_B_L A_RCLK_B_R / RSC_IHPSG13_MET3RES +XA_I90 A_WCLK_B_L A_WCLK_B_R / RSC_IHPSG13_MET3RES +XA_I89 A_DCLK_B_L A_DCLK_B_R / RSC_IHPSG13_MET3RES +XB_I80 B_WCLK_B_L B_RCLK_B_L net041 VDD VSS / RSC_IHPSG13_AND2X2 +XB_I76 B_DO_WRITE_P B_DI_N B_WR_ZERO VDD VSS / RSC_IHPSG13_AND2X2 +XB_I75 B_DO_WRITE_P B_DI_R B_WR_ONE VDD VSS / RSC_IHPSG13_AND2X2 +XA_I80 A_WCLK_B_L A_RCLK_B_L net21 VDD VSS / RSC_IHPSG13_AND2X2 +XA_I76 A_DI_N A_DO_WRITE_P A_WR_ZERO VDD VSS / RSC_IHPSG13_AND2X2 +XA_I75 A_DI_R A_DO_WRITE_P A_WR_ONE VDD VSS / RSC_IHPSG13_AND2X2 +XB_I81 net041 B_PRE_N VDD VSS / RSC_IHPSG13_CINVX4_WN +XA_I81 net21 A_PRE_N VDD VSS / RSC_IHPSG13_CINVX4_WN +XI_FILL4<10> VDD VSS / RSC_IHPSG13_FILLCAP4 +XI_FILL4<9> VDD VSS / RSC_IHPSG13_FILLCAP4 +XI_FILL4<8> VDD VSS / RSC_IHPSG13_FILLCAP4 +XI_FILL4<7> VDD VSS / RSC_IHPSG13_FILLCAP4 +XI_FILL4<6> VDD VSS / RSC_IHPSG13_FILLCAP4 +XI_FILL4<5> VDD VSS / RSC_IHPSG13_FILLCAP4 +XI_FILL4<4> VDD VSS / RSC_IHPSG13_FILLCAP4 +XI_FILL4<3> VDD VSS / RSC_IHPSG13_FILLCAP4 +XI_FILL4<2> VDD VSS / RSC_IHPSG13_FILLCAP4 +XI_FILL4<1> VDD VSS / RSC_IHPSG13_FILLCAP4 +.ENDS + +.SUBCKT RM_IHPSG13_8192x32_c4_2P_ROWDEC6 ADDR_N_I<5> ADDR_N_I<4> ADDR_N_I<3> ADDR_N_I<2> ++ ADDR_N_I<1> ADDR_N_I<0> CS_I ECLK_I WL_O<63> WL_O<62> WL_O<61> WL_O<60> ++ WL_O<59> WL_O<58> WL_O<57> WL_O<56> WL_O<55> WL_O<54> WL_O<53> WL_O<52> ++ WL_O<51> WL_O<50> WL_O<49> WL_O<48> WL_O<47> WL_O<46> WL_O<45> WL_O<44> ++ WL_O<43> WL_O<42> WL_O<41> WL_O<40> WL_O<39> WL_O<38> WL_O<37> WL_O<36> ++ WL_O<35> WL_O<34> WL_O<33> WL_O<32> WL_O<31> WL_O<30> WL_O<29> WL_O<28> ++ WL_O<27> WL_O<26> WL_O<25> WL_O<24> WL_O<23> WL_O<22> WL_O<21> WL_O<20> ++ WL_O<19> WL_O<18> WL_O<17> WL_O<16> WL_O<15> WL_O<14> WL_O<13> WL_O<12> ++ WL_O<11> WL_O<10> WL_O<9> WL_O<8> WL_O<7> WL_O<6> WL_O<5> WL_O<4> WL_O<3> ++ WL_O<2> WL_O<1> WL_O<0> VDD VSS +XDEC10 ADDR_N_I<5> ADDR_N_I<4> CS_I CS00<2> VDD VSS / ++ RM_IHPSG13_8192x32_c4_2P_DEC02 +XDEC00 ADDR_N_I<5> ADDR_N_I<4> CS_I CS00<0> VDD VSS / ++ RM_IHPSG13_8192x32_c4_2P_DEC00 +XSEL<3> ADDR_N_I<3> ADDR_N_I<2> ADDR_N_I<1> ADDR_N_I<0> CS00<3> ECLK_H<3> ++ ECLK_H<4> ECLK_B<3> ECLK_B<4> WL_O<63> WL_O<62> WL_O<61> WL_O<60> WL_O<59> ++ WL_O<58> WL_O<57> WL_O<56> WL_O<55> WL_O<54> WL_O<53> WL_O<52> WL_O<51> ++ WL_O<50> WL_O<49> WL_O<48> VDD VSS / RM_IHPSG13_8192x32_c4_2P_DEC04 +XSEL<2> ADDR_N_I<3> ADDR_N_I<2> ADDR_N_I<1> ADDR_N_I<0> CS00<2> ECLK_H<2> ++ ECLK_H<3> ECLK_B<2> ECLK_B<3> WL_O<47> WL_O<46> WL_O<45> WL_O<44> WL_O<43> ++ WL_O<42> WL_O<41> WL_O<40> WL_O<39> WL_O<38> WL_O<37> WL_O<36> WL_O<35> ++ WL_O<34> WL_O<33> WL_O<32> VDD VSS / RM_IHPSG13_8192x32_c4_2P_DEC04 +XSEL<1> ADDR_N_I<3> ADDR_N_I<2> ADDR_N_I<1> ADDR_N_I<0> CS00<1> ECLK_H<1> ++ ECLK_H<2> ECLK_B<1> ECLK_B<2> WL_O<31> WL_O<30> WL_O<29> WL_O<28> WL_O<27> ++ WL_O<26> WL_O<25> WL_O<24> WL_O<23> WL_O<22> WL_O<21> WL_O<20> WL_O<19> ++ WL_O<18> WL_O<17> WL_O<16> VDD VSS / RM_IHPSG13_8192x32_c4_2P_DEC04 +XSEL<0> ADDR_N_I<3> ADDR_N_I<2> ADDR_N_I<1> ADDR_N_I<0> CS00<0> ECLK_I ++ ECLK_H<1> ECLK_B<0> ECLK_B<1> WL_O<15> WL_O<14> WL_O<13> WL_O<12> WL_O<11> ++ WL_O<10> WL_O<9> WL_O<8> WL_O<7> WL_O<6> WL_O<5> WL_O<4> WL_O<3> WL_O<2> ++ WL_O<1> WL_O<0> VDD VSS / RM_IHPSG13_8192x32_c4_2P_DEC04 +XDEC11 ADDR_N_I<5> ADDR_N_I<4> CS_I CS00<3> VDD VSS / ++ RM_IHPSG13_8192x32_c4_2P_DEC03 +XL2<36> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<35> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<34> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<33> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<32> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<31> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<30> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<29> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<28> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<27> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<26> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<25> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<24> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<23> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<22> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<21> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<20> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<19> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<18> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<17> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<16> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<15> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<14> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<13> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<12> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<11> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<10> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<9> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<8> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<7> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<6> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<5> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<4> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<3> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<2> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<1> VDD VSS / RSC_IHPSG13_FILLCAP8 +XDEC01 ADDR_N_I<5> ADDR_N_I<4> CS_I CS00<1> VDD VSS / ++ RM_IHPSG13_8192x32_c4_2P_DEC01 +.ENDS +.SUBCKT RM_IHPSG13_8192x32_c4_2P_ROWREG6 ACLK_N_I ADDR_I<5> ADDR_I<4> ADDR_I<3> ADDR_I<2> ++ ADDR_I<1> ADDR_I<0> ADDR_N_O<5> ADDR_N_O<4> ADDR_N_O<3> ADDR_N_O<2> ++ ADDR_N_O<1> ADDR_N_O<0> BIST_ADDR_I<5> BIST_ADDR_I<4> BIST_ADDR_I<3> ++ BIST_ADDR_I<2> BIST_ADDR_I<1> BIST_ADDR_I<0> BIST_EN_I VDD VSS +XINV<5> q_int<5> qn_int<5> VDD VSS / RSC_IHPSG13_CINVX2 +XINV<4> q_int<4> qn_int<4> VDD VSS / RSC_IHPSG13_CINVX2 +XINV<3> q_int<3> qn_int<3> VDD VSS / RSC_IHPSG13_CINVX2 +XINV<2> q_int<2> qn_int<2> VDD VSS / RSC_IHPSG13_CINVX2 +XINV<1> q_int<1> qn_int<1> VDD VSS / RSC_IHPSG13_CINVX2 +XINV<0> q_int<0> qn_int<0> VDD VSS / RSC_IHPSG13_CINVX2 +XDRV<5> qn_int<5> ADDR_N_O<5> VDD VSS / RSC_IHPSG13_CINVX8 +XDRV<4> qn_int<4> ADDR_N_O<4> VDD VSS / RSC_IHPSG13_CINVX8 +XDRV<3> qn_int<3> ADDR_N_O<3> VDD VSS / RSC_IHPSG13_CINVX8 +XDRV<2> qn_int<2> ADDR_N_O<2> VDD VSS / RSC_IHPSG13_CINVX8 +XDRV<1> qn_int<1> ADDR_N_O<1> VDD VSS / RSC_IHPSG13_CINVX8 +XDRV<0> qn_int<0> ADDR_N_O<0> VDD VSS / RSC_IHPSG13_CINVX8 +XDFF<5> BIST_EN_I BIST_ADDR_I<5> ACLK_N_I ADDR_I<5> q_int<5> net2<0> VDD ++ VSS / RSC_IHPSG13_DFNQMX2IX1 +XDFF<4> BIST_EN_I BIST_ADDR_I<4> ACLK_N_I ADDR_I<4> q_int<4> net2<1> VDD ++ VSS / RSC_IHPSG13_DFNQMX2IX1 +XDFF<3> BIST_EN_I BIST_ADDR_I<3> ACLK_N_I ADDR_I<3> q_int<3> net2<2> VDD ++ VSS / RSC_IHPSG13_DFNQMX2IX1 +XDFF<2> BIST_EN_I BIST_ADDR_I<2> ACLK_N_I ADDR_I<2> q_int<2> net2<3> VDD ++ VSS / RSC_IHPSG13_DFNQMX2IX1 +XDFF<1> BIST_EN_I BIST_ADDR_I<1> ACLK_N_I ADDR_I<1> q_int<1> net2<4> VDD ++ VSS / RSC_IHPSG13_DFNQMX2IX1 +XDFF<0> BIST_EN_I BIST_ADDR_I<0> ACLK_N_I ADDR_I<0> q_int<0> net2<5> VDD ++ VSS / RSC_IHPSG13_DFNQMX2IX1 +XI11<12> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI11<11> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI11<10> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI11<9> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI11<8> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI11<7> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI11<6> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI11<5> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI11<4> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI11<3> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI11<2> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI11<1> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI12<2> VDD VSS / RSC_IHPSG13_FILLCAP4 +XI12<1> VDD VSS / RSC_IHPSG13_FILLCAP4 +XI12<0> VDD VSS / RSC_IHPSG13_FILLCAP4 +.ENDS + +.SUBCKT RM_IHPSG13_8192x32_c4_2P_COLDRV13X16 ADDR_COL_I<1> ADDR_COL_I<0> ADDR_COL_O<1> ++ ADDR_COL_O<0> ADDR_DEC_I<7> ADDR_DEC_I<6> ADDR_DEC_I<5> ADDR_DEC_I<4> ++ ADDR_DEC_I<3> ADDR_DEC_I<2> ADDR_DEC_I<1> ADDR_DEC_I<0> ADDR_DEC_O<7> ++ ADDR_DEC_O<6> ADDR_DEC_O<5> ADDR_DEC_O<4> ADDR_DEC_O<3> ADDR_DEC_O<2> ++ ADDR_DEC_O<1> ADDR_DEC_O<0> DCLK_I DCLK_O RCLK_I RCLK_O WCLK_I WCLK_O ++ VDD VSS +XI0<7> VDD VSS / RSC_IHPSG13_FILLCAP4 +XI0<6> VDD VSS / RSC_IHPSG13_FILLCAP4 +XI0<5> VDD VSS / RSC_IHPSG13_FILLCAP4 +XI0<4> VDD VSS / RSC_IHPSG13_FILLCAP4 +XI0<3> VDD VSS / RSC_IHPSG13_FILLCAP4 +XI0<2> VDD VSS / RSC_IHPSG13_FILLCAP4 +XI0<1> VDD VSS / RSC_IHPSG13_FILLCAP4 +XWCLK_DRV WCLK_I WCLK_O VDD VSS / RSC_IHPSG13_CBUFX16 +XRCLK_DRV RCLK_I RCLK_O VDD VSS / RSC_IHPSG13_CBUFX16 +XDCLK_DRV DCLK_I DCLK_O VDD VSS / RSC_IHPSG13_CBUFX16 +XADDR_COL_DRV<1> ADDR_COL_I<1> ADDR_COL_O<1> VDD VSS / ++ RSC_IHPSG13_CBUFX16 +XADDR_COL_DRV<0> ADDR_COL_I<0> ADDR_COL_O<0> VDD VSS / ++ RSC_IHPSG13_CBUFX16 +XADDR_DEC_DRV<7> ADDR_DEC_I<7> ADDR_DEC_O<7> VDD VSS / ++ RSC_IHPSG13_CBUFX16 +XADDR_DEC_DRV<6> ADDR_DEC_I<6> ADDR_DEC_O<6> VDD VSS / ++ RSC_IHPSG13_CBUFX16 +XADDR_DEC_DRV<5> ADDR_DEC_I<5> ADDR_DEC_O<5> VDD VSS / ++ RSC_IHPSG13_CBUFX16 +XADDR_DEC_DRV<4> ADDR_DEC_I<4> ADDR_DEC_O<4> VDD VSS / ++ RSC_IHPSG13_CBUFX16 +XADDR_DEC_DRV<3> ADDR_DEC_I<3> ADDR_DEC_O<3> VDD VSS / ++ RSC_IHPSG13_CBUFX16 +XADDR_DEC_DRV<2> ADDR_DEC_I<2> ADDR_DEC_O<2> VDD VSS / ++ RSC_IHPSG13_CBUFX16 +XADDR_DEC_DRV<1> ADDR_DEC_I<1> ADDR_DEC_O<1> VDD VSS / ++ RSC_IHPSG13_CBUFX16 +XADDR_DEC_DRV<0> ADDR_DEC_I<0> ADDR_DEC_O<0> VDD VSS / ++ RSC_IHPSG13_CBUFX16 +XI1<5> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI1<4> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI1<3> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI1<2> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI1<1> VDD VSS / RSC_IHPSG13_FILLCAP8 +.ENDS +.SUBCKT RM_IHPSG13_8192x32_c4_2P_WLDRV16X16 A<15> A<14> A<13> A<12> A<11> A<10> A<9> A<8> ++ A<7> A<6> A<5> A<4> A<3> A<2> A<1> A<0> Z<15> Z<14> Z<13> Z<12> Z<11> Z<10> ++ Z<9> Z<8> Z<7> Z<6> Z<5> Z<4> Z<3> Z<2> Z<1> Z<0> VDD VSS +XBUF<15> A<15> Z<15> VDD VSS / RSC_IHPSG13_WLDRVX16 +XBUF<14> A<14> Z<14> VDD VSS / RSC_IHPSG13_WLDRVX16 +XBUF<13> A<13> Z<13> VDD VSS / RSC_IHPSG13_WLDRVX16 +XBUF<12> A<12> Z<12> VDD VSS / RSC_IHPSG13_WLDRVX16 +XBUF<11> A<11> Z<11> VDD VSS / RSC_IHPSG13_WLDRVX16 +XBUF<10> A<10> Z<10> VDD VSS / RSC_IHPSG13_WLDRVX16 +XBUF<9> A<9> Z<9> VDD VSS / RSC_IHPSG13_WLDRVX16 +XBUF<8> A<8> Z<8> VDD VSS / RSC_IHPSG13_WLDRVX16 +XBUF<7> A<7> Z<7> VDD VSS / RSC_IHPSG13_WLDRVX16 +XBUF<6> A<6> Z<6> VDD VSS / RSC_IHPSG13_WLDRVX16 +XBUF<5> A<5> Z<5> VDD VSS / RSC_IHPSG13_WLDRVX16 +XBUF<4> A<4> Z<4> VDD VSS / RSC_IHPSG13_WLDRVX16 +XBUF<3> A<3> Z<3> VDD VSS / RSC_IHPSG13_WLDRVX16 +XBUF<2> A<2> Z<2> VDD VSS / RSC_IHPSG13_WLDRVX16 +XBUF<1> A<1> Z<1> VDD VSS / RSC_IHPSG13_WLDRVX16 +XBUF<0> A<0> Z<0> VDD VSS / RSC_IHPSG13_WLDRVX16 +.ENDS + + +.SUBCKT RM_IHPSG13_8192x32_c4_1P_DEC01 ADDR<1> ADDR<0> CS CS_OUT VDD VSS +XDECINV net1 CS_OUT VDD VSS / RSC_IHPSG13_INVX4 +XDEC NADDR<1> ADDR<0> CS net1 VDD VSS / RSC_IHPSG13_NAND3X2 +XI2 VDD VSS / RSC_IHPSG13_FILLCAP4 +XADDRINV ADDR<1> NADDR<1> VDD VSS / RSC_IHPSG13_INVX2 +.ENDS +.SUBCKT RM_IHPSG13_8192x32_c4_1P_DEC00 ADDR<1> ADDR<0> CS CS_OUT VDD VSS +XDECINV net1 CS_OUT VDD VSS / RSC_IHPSG13_INVX4 +XDEC NADDR<1> NADDR<0> CS net1 VDD VSS / RSC_IHPSG13_NAND3X2 +XADDRINV<1> ADDR<1> NADDR<1> VDD VSS / RSC_IHPSG13_INVX2 +XADDRINV<0> ADDR<0> NADDR<0> VDD VSS / RSC_IHPSG13_INVX2 +XI1 VDD VSS / RSC_IHPSG13_FILLCAP4 +.ENDS +.SUBCKT RM_IHPSG13_8192x32_c4_1P_ROWDEC5 ADDR_N_I<4> ADDR_N_I<3> ADDR_N_I<2> ADDR_N_I<1> ++ ADDR_N_I<0> CS_I ECLK_I WL_O<31> WL_O<30> WL_O<29> WL_O<28> WL_O<27> ++ WL_O<26> WL_O<25> WL_O<24> WL_O<23> WL_O<22> WL_O<21> WL_O<20> WL_O<19> ++ WL_O<18> WL_O<17> WL_O<16> WL_O<15> WL_O<14> WL_O<13> WL_O<12> WL_O<11> ++ WL_O<10> WL_O<9> WL_O<8> WL_O<7> WL_O<6> WL_O<5> WL_O<4> WL_O<3> WL_O<2> ++ WL_O<1> WL_O<0> VDD VSS +XL2<12> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<11> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<10> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<9> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<8> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<7> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<6> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<5> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<4> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<3> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<2> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<1> VDD VSS / RSC_IHPSG13_FILLCAP8 +XDEC01 ADDR_N_I<5> ADDR_N_I<4> CS_I CS00<1> VDD VSS / ++ RM_IHPSG13_8192x32_c4_1P_DEC01 +XDEC00 ADDR_N_I<5> ADDR_N_I<4> CS_I CS00<0> VDD VSS / ++ RM_IHPSG13_8192x32_c4_1P_DEC00 +XSEL<1> ADDR_N_I<3> ADDR_N_I<2> ADDR_N_I<1> ADDR_N_I<0> CS00<1> ECLK_H<1> ++ ECLK_H<2> ECLK_B<1> ECLK_B<2> WL_O<31> WL_O<30> WL_O<29> WL_O<28> WL_O<27> ++ WL_O<26> WL_O<25> WL_O<24> WL_O<23> WL_O<22> WL_O<21> WL_O<20> WL_O<19> ++ WL_O<18> WL_O<17> WL_O<16> VDD VSS / RM_IHPSG13_8192x32_c4_1P_DEC04 +XSEL<0> ADDR_N_I<3> ADDR_N_I<2> ADDR_N_I<1> ADDR_N_I<0> CS00<0> ECLK_I ++ ECLK_H<1> ECLK_B<0> ECLK_B<1> WL_O<15> WL_O<14> WL_O<13> WL_O<12> WL_O<11> ++ WL_O<10> WL_O<9> WL_O<8> WL_O<7> WL_O<6> WL_O<5> WL_O<4> WL_O<3> WL_O<2> ++ WL_O<1> WL_O<0> VDD VSS / RM_IHPSG13_8192x32_c4_1P_DEC04 +XI0 ADDR_N_I<5> VDD VSS / RSC_IHPSG13_TIEL +.ENDS +.SUBCKT RM_IHPSG13_8192x32_c4_1P_ROWREG5 ACLK_N_I ADDR_I<4> ADDR_I<3> ADDR_I<2> ADDR_I<1> ++ ADDR_I<0> ADDR_N_O<4> ADDR_N_O<3> ADDR_N_O<2> ADDR_N_O<1> ADDR_N_O<0> ++ BIST_ADDR_I<4> BIST_ADDR_I<3> BIST_ADDR_I<2> BIST_ADDR_I<1> BIST_ADDR_I<0> ++ BIST_EN_I VDD VSS +XINV<4> q_int<4> qn_int<4> VDD VSS / RSC_IHPSG13_CINVX2 +XINV<3> q_int<3> qn_int<3> VDD VSS / RSC_IHPSG13_CINVX2 +XINV<2> q_int<2> qn_int<2> VDD VSS / RSC_IHPSG13_CINVX2 +XINV<1> q_int<1> qn_int<1> VDD VSS / RSC_IHPSG13_CINVX2 +XINV<0> q_int<0> qn_int<0> VDD VSS / RSC_IHPSG13_CINVX2 +XDRV<4> qn_int<4> ADDR_N_O<4> VDD VSS / RSC_IHPSG13_CINVX8 +XDRV<3> qn_int<3> ADDR_N_O<3> VDD VSS / RSC_IHPSG13_CINVX8 +XDRV<2> qn_int<2> ADDR_N_O<2> VDD VSS / RSC_IHPSG13_CINVX8 +XDRV<1> qn_int<1> ADDR_N_O<1> VDD VSS / RSC_IHPSG13_CINVX8 +XDRV<0> qn_int<0> ADDR_N_O<0> VDD VSS / RSC_IHPSG13_CINVX8 +XDFF<4> BIST_EN_I BIST_ADDR_I<4> ACLK_N_I ADDR_I<4> q_int<4> net2<0> VDD ++ VSS / RSC_IHPSG13_DFNQMX2IX1 +XDFF<3> BIST_EN_I BIST_ADDR_I<3> ACLK_N_I ADDR_I<3> q_int<3> net2<1> VDD ++ VSS / RSC_IHPSG13_DFNQMX2IX1 +XDFF<2> BIST_EN_I BIST_ADDR_I<2> ACLK_N_I ADDR_I<2> q_int<2> net2<2> VDD ++ VSS / RSC_IHPSG13_DFNQMX2IX1 +XDFF<1> BIST_EN_I BIST_ADDR_I<1> ACLK_N_I ADDR_I<1> q_int<1> net2<3> VDD ++ VSS / RSC_IHPSG13_DFNQMX2IX1 +XDFF<0> BIST_EN_I BIST_ADDR_I<0> ACLK_N_I ADDR_I<0> q_int<0> net2<4> VDD ++ VSS / RSC_IHPSG13_DFNQMX2IX1 +XI11<16> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI11<15> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI11<14> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI11<13> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI11<12> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI11<11> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI11<10> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI11<9> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI11<8> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI11<7> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI11<6> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI11<5> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI11<4> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI11<3> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI11<2> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI11<1> VDD VSS / RSC_IHPSG13_FILLCAP8 +.ENDS + + +.SUBCKT RM_IHPSG13_8192x32_c4_1P_COLDEC5 ACLK_N ADDR<4> ADDR<3> ADDR<2> ADDR<1> ADDR<0> ++ ADDR_COL<1> ADDR_COL<0> ADDR_DEC<7> ADDR_DEC<6> ADDR_DEC<5> ADDR_DEC<4> ++ ADDR_DEC<3> ADDR_DEC<2> ADDR_DEC<1> ADDR_DEC<0> BIST_ADDR<4> BIST_ADDR<3> ++ BIST_ADDR<2> BIST_ADDR<1> BIST_ADDR<0> BIST_EN_I VDD VSS +XI17<2> VDD VSS / RSC_IHPSG13_FILLCAP4 +XI17<1> VDD VSS / RSC_IHPSG13_FILLCAP4 +XI13<1> addr_int<1> ADDR_COL<1> VDD VSS / RSC_IHPSG13_CBUFX2 +XI13<0> addr_int<0> ADDR_COL<0> VDD VSS / RSC_IHPSG13_CBUFX2 +XDFF<4> BIST_EN_I BIST_ADDR<4> ACLK_N ADDR<4> addr_int<1> net7<0> VDD ++ VSS / RSC_IHPSG13_DFNQMX2IX1 +XDFF<3> BIST_EN_I BIST_ADDR<3> ACLK_N ADDR<3> addr_int<0> net7<1> VDD ++ VSS / RSC_IHPSG13_DFNQMX2IX1 +XDFF<2> BIST_EN_I BIST_ADDR<2> ACLK_N ADDR<2> padr_int<2> net7<2> VDD ++ VSS / RSC_IHPSG13_DFNQMX2IX1 +XDFF<1> BIST_EN_I BIST_ADDR<1> ACLK_N ADDR<1> padr_int<1> net7<3> VDD ++ VSS / RSC_IHPSG13_DFNQMX2IX1 +XDFF<0> BIST_EN_I BIST_ADDR<0> ACLK_N ADDR<0> padr_int<0> net7<4> VDD ++ VSS / RSC_IHPSG13_DFNQMX2IX1 +XI1<7> PADR<0> PADR<1> PADR<2> addr_n<7> VDD VSS / RSC_IHPSG13_NAND3X2 +XI1<6> NADR<0> PADR<1> PADR<2> addr_n<6> VDD VSS / RSC_IHPSG13_NAND3X2 +XI1<5> PADR<0> NADR<1> PADR<2> addr_n<5> VDD VSS / RSC_IHPSG13_NAND3X2 +XI1<4> NADR<0> NADR<1> PADR<2> addr_n<4> VDD VSS / RSC_IHPSG13_NAND3X2 +XI1<3> PADR<0> PADR<1> NADR<2> addr_n<3> VDD VSS / RSC_IHPSG13_NAND3X2 +XI1<2> NADR<0> PADR<1> NADR<2> addr_n<2> VDD VSS / RSC_IHPSG13_NAND3X2 +XI1<1> PADR<0> NADR<1> NADR<2> addr_n<1> VDD VSS / RSC_IHPSG13_NAND3X2 +XI1<0> NADR<0> NADR<1> NADR<2> addr_n<0> VDD VSS / RSC_IHPSG13_NAND3X2 +XI15<2> NADR<2> PADR<2> VDD VSS / RSC_IHPSG13_INVX2 +XI15<1> NADR<1> PADR<1> VDD VSS / RSC_IHPSG13_INVX2 +XI15<0> NADR<0> PADR<0> VDD VSS / RSC_IHPSG13_INVX2 +XI3<2> padr_int<2> NADR<2> VDD VSS / RSC_IHPSG13_INVX2 +XI3<1> padr_int<1> NADR<1> VDD VSS / RSC_IHPSG13_INVX2 +XI3<0> padr_int<0> NADR<0> VDD VSS / RSC_IHPSG13_INVX2 +XI2<7> addr_n<7> ADDR_DEC<7> VDD VSS / RSC_IHPSG13_INVX2 +XI2<6> addr_n<6> ADDR_DEC<6> VDD VSS / RSC_IHPSG13_INVX2 +XI2<5> addr_n<5> ADDR_DEC<5> VDD VSS / RSC_IHPSG13_INVX2 +XI2<4> addr_n<4> ADDR_DEC<4> VDD VSS / RSC_IHPSG13_INVX2 +XI2<3> addr_n<3> ADDR_DEC<3> VDD VSS / RSC_IHPSG13_INVX2 +XI2<2> addr_n<2> ADDR_DEC<2> VDD VSS / RSC_IHPSG13_INVX2 +XI2<1> addr_n<1> ADDR_DEC<1> VDD VSS / RSC_IHPSG13_INVX2 +XI2<0> addr_n<0> ADDR_DEC<0> VDD VSS / RSC_IHPSG13_INVX2 +.ENDS +.SUBCKT RM_IHPSG13_8192x32_c4_1P_COLCTRL5 A_ADDR_COL<1> A_ADDR_COL<0> A_ADDR_DEC<7> ++ A_ADDR_DEC<6> A_ADDR_DEC<5> A_ADDR_DEC<4> A_ADDR_DEC<3> A_ADDR_DEC<2> ++ A_ADDR_DEC<1> A_ADDR_DEC<0> A_BIST_BM_I A_BIST_DW_I A_BIST_EN_I A_BLC<31> ++ A_BLC<30> A_BLC<29> A_BLC<28> A_BLC<27> A_BLC<26> A_BLC<25> A_BLC<24> ++ A_BLC<23> A_BLC<22> A_BLC<21> A_BLC<20> A_BLC<19> A_BLC<18> A_BLC<17> ++ A_BLC<16> A_BLC<15> A_BLC<14> A_BLC<13> A_BLC<12> A_BLC<11> A_BLC<10> ++ A_BLC<9> A_BLC<8> A_BLC<7> A_BLC<6> A_BLC<5> A_BLC<4> A_BLC<3> A_BLC<2> ++ A_BLC<1> A_BLC<0> A_BLT<31> A_BLT<30> A_BLT<29> A_BLT<28> A_BLT<27> ++ A_BLT<26> A_BLT<25> A_BLT<24> A_BLT<23> A_BLT<22> A_BLT<21> A_BLT<20> ++ A_BLT<19> A_BLT<18> A_BLT<17> A_BLT<16> A_BLT<15> A_BLT<14> A_BLT<13> ++ A_BLT<12> A_BLT<11> A_BLT<10> A_BLT<9> A_BLT<8> A_BLT<7> A_BLT<6> A_BLT<5> ++ A_BLT<4> A_BLT<3> A_BLT<2> A_BLT<1> A_BLT<0> A_BM_I A_DCLK_B_L A_DCLK_B_R ++ A_DCLK_L A_DCLK_R A_DR_O A_DW_I A_RCLK_B_L A_RCLK_B_R A_RCLK_L A_RCLK_R ++ A_TIEH_O A_WCLK_B_L A_WCLK_B_R A_WCLK_L A_WCLK_R VDD VSS +XA_I80<1> A_WCLK_B_L A_RCLK_B_L A_W_nor_R<1> VDD VSS / ++ RSC_IHPSG13_AND2X2 +XA_I80<0> A_WCLK_B_L A_RCLK_B_L A_W_nor_R<0> VDD VSS / ++ RSC_IHPSG13_AND2X2 +XA_I44 A_BM_N A_WCLK_B_L A_DO_WRITE_P VDD VSS / RSC_IHPSG13_NOR2X2 +XI80<29> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI80<28> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI80<27> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI80<26> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI80<25> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI80<24> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI80<23> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI80<22> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI80<21> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI80<20> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI80<19> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI80<18> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI80<17> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI80<16> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI80<15> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI80<14> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI80<13> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI80<12> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI80<11> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI80<10> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI80<9> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI80<8> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI80<7> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI80<6> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI80<5> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI80<4> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI80<3> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI80<2> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI80<1> VDD VSS / RSC_IHPSG13_FILLCAP8 +XA_I74<16> VDD VSS / RSC_IHPSG13_FILLCAP8 +XA_I74<15> VDD VSS / RSC_IHPSG13_FILLCAP8 +XA_I74<14> VDD VSS / RSC_IHPSG13_FILLCAP8 +XA_I74<13> VDD VSS / RSC_IHPSG13_FILLCAP8 +XA_I74<12> VDD VSS / RSC_IHPSG13_FILLCAP8 +XA_I74<11> VDD VSS / RSC_IHPSG13_FILLCAP8 +XA_I74<10> VDD VSS / RSC_IHPSG13_FILLCAP8 +XA_I74<9> VDD VSS / RSC_IHPSG13_FILLCAP8 +XA_I74<8> VDD VSS / RSC_IHPSG13_FILLCAP8 +XA_I74<7> VDD VSS / RSC_IHPSG13_FILLCAP8 +XA_I74<6> VDD VSS / RSC_IHPSG13_FILLCAP8 +XA_I74<5> VDD VSS / RSC_IHPSG13_FILLCAP8 +XA_I74<4> VDD VSS / RSC_IHPSG13_FILLCAP8 +XA_I74<3> VDD VSS / RSC_IHPSG13_FILLCAP8 +XA_I74<2> VDD VSS / RSC_IHPSG13_FILLCAP8 +XA_I74<1> VDD VSS / RSC_IHPSG13_FILLCAP8 +XA_INV<6> A_N1<1> A_P1<1> VDD VSS / RSC_IHPSG13_CINVX4 +XA_INV<5> A_N0<1> A_P0<1> VDD VSS / RSC_IHPSG13_CINVX4 +XA_INV<4> A_N0<0> A_P0<0> VDD VSS / RSC_IHPSG13_CINVX4 +XA_INV<3> A_ADDR_COL<1> A_N1<1> VDD VSS / RSC_IHPSG13_CINVX4 +XA_INV<2> A_ADDR_COL<1> A_N1<0> VDD VSS / RSC_IHPSG13_CINVX4 +XA_INV<1> A_ADDR_COL<0> A_N0<1> VDD VSS / RSC_IHPSG13_CINVX4 +XA_INV<0> A_ADDR_COL<0> A_N0<0> VDD VSS / RSC_IHPSG13_CINVX4 +XA_I81<3> A_W_nor_R<1> A_PRE_N VDD VSS / RSC_IHPSG13_CINVX4_WN +XA_I81<2> A_W_nor_R<1> A_PRE_N VDD VSS / RSC_IHPSG13_CINVX4_WN +XA_I81<1> A_W_nor_R<0> A_PRE_N VDD VSS / RSC_IHPSG13_CINVX4_WN +XA_I81<0> A_W_nor_R<0> A_PRE_N VDD VSS / RSC_IHPSG13_CINVX4_WN +XA_BLTMUX<31> A_BLC<31> A_BLC_SEL A_BLT<31> A_BLT_SEL A_PRE_N A_SEL_P<31> ++ A_WR_ONE A_WR_ZERO VDD VSS / RM_IHPSG13_8192x32_c4_1P_BLDRV +XA_BLTMUX<30> A_BLC<30> A_BLC_SEL A_BLT<30> A_BLT_SEL A_PRE_N A_SEL_P<30> ++ A_WR_ONE A_WR_ZERO VDD VSS / RM_IHPSG13_8192x32_c4_1P_BLDRV +XA_BLTMUX<29> A_BLC<29> A_BLC_SEL A_BLT<29> A_BLT_SEL A_PRE_N A_SEL_P<29> ++ A_WR_ONE A_WR_ZERO VDD VSS / RM_IHPSG13_8192x32_c4_1P_BLDRV +XA_BLTMUX<28> A_BLC<28> A_BLC_SEL A_BLT<28> A_BLT_SEL A_PRE_N A_SEL_P<28> ++ A_WR_ONE A_WR_ZERO VDD VSS / RM_IHPSG13_8192x32_c4_1P_BLDRV +XA_BLTMUX<27> A_BLC<27> A_BLC_SEL A_BLT<27> A_BLT_SEL A_PRE_N A_SEL_P<27> ++ A_WR_ONE A_WR_ZERO VDD VSS / RM_IHPSG13_8192x32_c4_1P_BLDRV +XA_BLTMUX<26> A_BLC<26> A_BLC_SEL A_BLT<26> A_BLT_SEL A_PRE_N A_SEL_P<26> ++ A_WR_ONE A_WR_ZERO VDD VSS / RM_IHPSG13_8192x32_c4_1P_BLDRV +XA_BLTMUX<25> A_BLC<25> A_BLC_SEL A_BLT<25> A_BLT_SEL A_PRE_N A_SEL_P<25> ++ A_WR_ONE A_WR_ZERO VDD VSS / RM_IHPSG13_8192x32_c4_1P_BLDRV +XA_BLTMUX<24> A_BLC<24> A_BLC_SEL A_BLT<24> A_BLT_SEL A_PRE_N A_SEL_P<24> ++ A_WR_ONE A_WR_ZERO VDD VSS / RM_IHPSG13_8192x32_c4_1P_BLDRV +XA_BLTMUX<23> A_BLC<23> A_BLC_SEL A_BLT<23> A_BLT_SEL A_PRE_N A_SEL_P<23> ++ A_WR_ONE A_WR_ZERO VDD VSS / RM_IHPSG13_8192x32_c4_1P_BLDRV +XA_BLTMUX<22> A_BLC<22> A_BLC_SEL A_BLT<22> A_BLT_SEL A_PRE_N A_SEL_P<22> ++ A_WR_ONE A_WR_ZERO VDD VSS / RM_IHPSG13_8192x32_c4_1P_BLDRV +XA_BLTMUX<21> A_BLC<21> A_BLC_SEL A_BLT<21> A_BLT_SEL A_PRE_N A_SEL_P<21> ++ A_WR_ONE A_WR_ZERO VDD VSS / RM_IHPSG13_8192x32_c4_1P_BLDRV +XA_BLTMUX<20> A_BLC<20> A_BLC_SEL A_BLT<20> A_BLT_SEL A_PRE_N A_SEL_P<20> ++ A_WR_ONE A_WR_ZERO VDD VSS / RM_IHPSG13_8192x32_c4_1P_BLDRV +XA_BLTMUX<19> A_BLC<19> A_BLC_SEL A_BLT<19> A_BLT_SEL A_PRE_N A_SEL_P<19> ++ A_WR_ONE A_WR_ZERO VDD VSS / RM_IHPSG13_8192x32_c4_1P_BLDRV +XA_BLTMUX<18> A_BLC<18> A_BLC_SEL A_BLT<18> A_BLT_SEL A_PRE_N A_SEL_P<18> ++ A_WR_ONE A_WR_ZERO VDD VSS / RM_IHPSG13_8192x32_c4_1P_BLDRV +XA_BLTMUX<17> A_BLC<17> A_BLC_SEL A_BLT<17> A_BLT_SEL A_PRE_N A_SEL_P<17> ++ A_WR_ONE A_WR_ZERO VDD VSS / RM_IHPSG13_8192x32_c4_1P_BLDRV +XA_BLTMUX<16> A_BLC<16> A_BLC_SEL A_BLT<16> A_BLT_SEL A_PRE_N A_SEL_P<16> ++ A_WR_ONE A_WR_ZERO VDD VSS / RM_IHPSG13_8192x32_c4_1P_BLDRV +XA_BLTMUX<15> A_BLC<15> A_BLC_SEL A_BLT<15> A_BLT_SEL A_PRE_N A_SEL_P<15> ++ A_WR_ONE A_WR_ZERO VDD VSS / RM_IHPSG13_8192x32_c4_1P_BLDRV +XA_BLTMUX<14> A_BLC<14> A_BLC_SEL A_BLT<14> A_BLT_SEL A_PRE_N A_SEL_P<14> ++ A_WR_ONE A_WR_ZERO VDD VSS / RM_IHPSG13_8192x32_c4_1P_BLDRV +XA_BLTMUX<13> A_BLC<13> A_BLC_SEL A_BLT<13> A_BLT_SEL A_PRE_N A_SEL_P<13> ++ A_WR_ONE A_WR_ZERO VDD VSS / RM_IHPSG13_8192x32_c4_1P_BLDRV +XA_BLTMUX<12> A_BLC<12> A_BLC_SEL A_BLT<12> A_BLT_SEL A_PRE_N A_SEL_P<12> ++ A_WR_ONE A_WR_ZERO VDD VSS / RM_IHPSG13_8192x32_c4_1P_BLDRV +XA_BLTMUX<11> A_BLC<11> A_BLC_SEL A_BLT<11> A_BLT_SEL A_PRE_N A_SEL_P<11> ++ A_WR_ONE A_WR_ZERO VDD VSS / RM_IHPSG13_8192x32_c4_1P_BLDRV +XA_BLTMUX<10> A_BLC<10> A_BLC_SEL A_BLT<10> A_BLT_SEL A_PRE_N A_SEL_P<10> ++ A_WR_ONE A_WR_ZERO VDD VSS / RM_IHPSG13_8192x32_c4_1P_BLDRV +XA_BLTMUX<9> A_BLC<9> A_BLC_SEL A_BLT<9> A_BLT_SEL A_PRE_N A_SEL_P<9> A_WR_ONE ++ A_WR_ZERO VDD VSS / RM_IHPSG13_8192x32_c4_1P_BLDRV +XA_BLTMUX<8> A_BLC<8> A_BLC_SEL A_BLT<8> A_BLT_SEL A_PRE_N A_SEL_P<8> A_WR_ONE ++ A_WR_ZERO VDD VSS / RM_IHPSG13_8192x32_c4_1P_BLDRV +XA_BLTMUX<7> A_BLC<7> A_BLC_SEL A_BLT<7> A_BLT_SEL A_PRE_N A_SEL_P<7> A_WR_ONE ++ A_WR_ZERO VDD VSS / RM_IHPSG13_8192x32_c4_1P_BLDRV +XA_BLTMUX<6> A_BLC<6> A_BLC_SEL A_BLT<6> A_BLT_SEL A_PRE_N A_SEL_P<6> A_WR_ONE ++ A_WR_ZERO VDD VSS / RM_IHPSG13_8192x32_c4_1P_BLDRV +XA_BLTMUX<5> A_BLC<5> A_BLC_SEL A_BLT<5> A_BLT_SEL A_PRE_N A_SEL_P<5> A_WR_ONE ++ A_WR_ZERO VDD VSS / RM_IHPSG13_8192x32_c4_1P_BLDRV +XA_BLTMUX<4> A_BLC<4> A_BLC_SEL A_BLT<4> A_BLT_SEL A_PRE_N A_SEL_P<4> A_WR_ONE ++ A_WR_ZERO VDD VSS / RM_IHPSG13_8192x32_c4_1P_BLDRV +XA_BLTMUX<3> A_BLC<3> A_BLC_SEL A_BLT<3> A_BLT_SEL A_PRE_N A_SEL_P<3> A_WR_ONE ++ A_WR_ZERO VDD VSS / RM_IHPSG13_8192x32_c4_1P_BLDRV +XA_BLTMUX<2> A_BLC<2> A_BLC_SEL A_BLT<2> A_BLT_SEL A_PRE_N A_SEL_P<2> A_WR_ONE ++ A_WR_ZERO VDD VSS / RM_IHPSG13_8192x32_c4_1P_BLDRV +XA_BLTMUX<1> A_BLC<1> A_BLC_SEL A_BLT<1> A_BLT_SEL A_PRE_N A_SEL_P<1> A_WR_ONE ++ A_WR_ZERO VDD VSS / RM_IHPSG13_8192x32_c4_1P_BLDRV +XA_BLTMUX<0> A_BLC<0> A_BLC_SEL A_BLT<0> A_BLT_SEL A_PRE_N A_SEL_P<0> A_WR_ONE ++ A_WR_ZERO VDD VSS / RM_IHPSG13_8192x32_c4_1P_BLDRV +XA_CAPS<17> VDD VSS / RSC_IHPSG13_FILLCAP4 +XA_CAPS<16> VDD VSS / RSC_IHPSG13_FILLCAP4 +XA_CAPS<15> VDD VSS / RSC_IHPSG13_FILLCAP4 +XA_CAPS<14> VDD VSS / RSC_IHPSG13_FILLCAP4 +XA_CAPS<13> VDD VSS / RSC_IHPSG13_FILLCAP4 +XA_CAPS<12> VDD VSS / RSC_IHPSG13_FILLCAP4 +XA_CAPS<11> VDD VSS / RSC_IHPSG13_FILLCAP4 +XA_CAPS<10> VDD VSS / RSC_IHPSG13_FILLCAP4 +XA_CAPS<9> VDD VSS / RSC_IHPSG13_FILLCAP4 +XA_CAPS<8> VDD VSS / RSC_IHPSG13_FILLCAP4 +XA_CAPS<7> VDD VSS / RSC_IHPSG13_FILLCAP4 +XA_CAPS<6> VDD VSS / RSC_IHPSG13_FILLCAP4 +XA_CAPS<5> VDD VSS / RSC_IHPSG13_FILLCAP4 +XA_CAPS<4> VDD VSS / RSC_IHPSG13_FILLCAP4 +XA_CAPS<3> VDD VSS / RSC_IHPSG13_FILLCAP4 +XA_CAPS<2> VDD VSS / RSC_IHPSG13_FILLCAP4 +XA_CAPS<1> VDD VSS / RSC_IHPSG13_FILLCAP4 +XA_I51 net19 A_DR_O VDD VSS / RSC_IHPSG13_INVX4 +XA_I78 A_RCLK_B_L A_SAE VDD VSS / RSC_IHPSG13_CBUFX2 +XA_I69 A_DCLK_L A_DCLK_B_L VDD VSS / RSC_IHPSG13_CINVX8 +XA_I50 A_WCLK_L A_WCLK_B_L VDD VSS / RSC_IHPSG13_CINVX8 +XA_EBUF A_RCLK_L A_RCLK_B_L VDD VSS / RSC_IHPSG13_CINVX8 +XA_I76 A_DI_N A_DO_WRITE_P A_WR_ZERO VDD VSS / RSC_IHPSG13_AND2X6 +XA_I75 A_DI_R A_DO_WRITE_P A_WR_ONE VDD VSS / RSC_IHPSG13_AND2X6 +XA_I83 A_BM_R A_BM_N VDD VSS / RSC_IHPSG13_INVX2 +XA_DEC3INV<31> net23<0> A_SEL_P<31> VDD VSS / RSC_IHPSG13_INVX2 +XA_DEC3INV<30> net23<1> A_SEL_P<30> VDD VSS / RSC_IHPSG13_INVX2 +XA_DEC3INV<29> net23<2> A_SEL_P<29> VDD VSS / RSC_IHPSG13_INVX2 +XA_DEC3INV<28> net23<3> A_SEL_P<28> VDD VSS / RSC_IHPSG13_INVX2 +XA_DEC3INV<27> net23<4> A_SEL_P<27> VDD VSS / RSC_IHPSG13_INVX2 +XA_DEC3INV<26> net23<5> A_SEL_P<26> VDD VSS / RSC_IHPSG13_INVX2 +XA_DEC3INV<25> net23<6> A_SEL_P<25> VDD VSS / RSC_IHPSG13_INVX2 +XA_DEC3INV<24> net23<7> A_SEL_P<24> VDD VSS / RSC_IHPSG13_INVX2 +XA_DEC3INV<23> net23<8> A_SEL_P<23> VDD VSS / RSC_IHPSG13_INVX2 +XA_DEC3INV<22> net23<9> A_SEL_P<22> VDD VSS / RSC_IHPSG13_INVX2 +XA_DEC3INV<21> net23<10> A_SEL_P<21> VDD VSS / RSC_IHPSG13_INVX2 +XA_DEC3INV<20> net23<11> A_SEL_P<20> VDD VSS / RSC_IHPSG13_INVX2 +XA_DEC3INV<19> net23<12> A_SEL_P<19> VDD VSS / RSC_IHPSG13_INVX2 +XA_DEC3INV<18> net23<13> A_SEL_P<18> VDD VSS / RSC_IHPSG13_INVX2 +XA_DEC3INV<17> net23<14> A_SEL_P<17> VDD VSS / RSC_IHPSG13_INVX2 +XA_DEC3INV<16> net23<15> A_SEL_P<16> VDD VSS / RSC_IHPSG13_INVX2 +XA_DEC3INV<15> net23<16> A_SEL_P<15> VDD VSS / RSC_IHPSG13_INVX2 +XA_DEC3INV<14> net23<17> A_SEL_P<14> VDD VSS / RSC_IHPSG13_INVX2 +XA_DEC3INV<13> net23<18> A_SEL_P<13> VDD VSS / RSC_IHPSG13_INVX2 +XA_DEC3INV<12> net23<19> A_SEL_P<12> VDD VSS / RSC_IHPSG13_INVX2 +XA_DEC3INV<11> net23<20> A_SEL_P<11> VDD VSS / RSC_IHPSG13_INVX2 +XA_DEC3INV<10> net23<21> A_SEL_P<10> VDD VSS / RSC_IHPSG13_INVX2 +XA_DEC3INV<9> net23<22> A_SEL_P<9> VDD VSS / RSC_IHPSG13_INVX2 +XA_DEC3INV<8> net23<23> A_SEL_P<8> VDD VSS / RSC_IHPSG13_INVX2 +XA_DEC3INV<7> net23<24> A_SEL_P<7> VDD VSS / RSC_IHPSG13_INVX2 +XA_DEC3INV<6> net23<25> A_SEL_P<6> VDD VSS / RSC_IHPSG13_INVX2 +XA_DEC3INV<5> net23<26> A_SEL_P<5> VDD VSS / RSC_IHPSG13_INVX2 +XA_DEC3INV<4> net23<27> A_SEL_P<4> VDD VSS / RSC_IHPSG13_INVX2 +XA_DEC3INV<3> net23<28> A_SEL_P<3> VDD VSS / RSC_IHPSG13_INVX2 +XA_DEC3INV<2> net23<29> A_SEL_P<2> VDD VSS / RSC_IHPSG13_INVX2 +XA_DEC3INV<1> net23<30> A_SEL_P<1> VDD VSS / RSC_IHPSG13_INVX2 +XA_DEC3INV<0> net23<31> A_SEL_P<0> VDD VSS / RSC_IHPSG13_INVX2 +XA_I49 A_DI_R A_DI_N VDD VSS / RSC_IHPSG13_INVX2 +XA_ISENSE A_SAE A_BLC_SEL A_BLT_SEL net19 net20 VDD VSS / ++ RSC_IHPSG13_DFPQD_MSAFFX2 +XA_DREG A_BIST_EN_I A_BIST_DW_I A_DCLK_B_L A_DW_I A_DI_R net22 VDD VSS ++ / RSC_IHPSG13_DFNQMX2IX1 +XA_BREG A_BIST_EN_I A_BIST_BM_I A_DCLK_B_L A_BM_I A_BM_R net21 VDD VSS ++ / RSC_IHPSG13_DFNQMX2IX1 +XA_DEC3<31> A_P1<1> A_P0<1> A_ADDR_DEC<7> net23<0> VDD VSS / ++ RSC_IHPSG13_NAND3X2 +XA_DEC3<30> A_P1<1> A_P0<1> A_ADDR_DEC<6> net23<1> VDD VSS / ++ RSC_IHPSG13_NAND3X2 +XA_DEC3<29> A_P1<1> A_P0<1> A_ADDR_DEC<5> net23<2> VDD VSS / ++ RSC_IHPSG13_NAND3X2 +XA_DEC3<28> A_P1<1> A_P0<1> A_ADDR_DEC<4> net23<3> VDD VSS / ++ RSC_IHPSG13_NAND3X2 +XA_DEC3<27> A_P1<1> A_P0<1> A_ADDR_DEC<3> net23<4> VDD VSS / ++ RSC_IHPSG13_NAND3X2 +XA_DEC3<26> A_P1<1> A_P0<1> A_ADDR_DEC<2> net23<5> VDD VSS / ++ RSC_IHPSG13_NAND3X2 +XA_DEC3<25> A_P1<1> A_P0<1> A_ADDR_DEC<1> net23<6> VDD VSS / ++ RSC_IHPSG13_NAND3X2 +XA_DEC3<24> A_P1<1> A_P0<1> A_ADDR_DEC<0> net23<7> VDD VSS / ++ RSC_IHPSG13_NAND3X2 +XA_DEC3<23> A_P1<1> A_N0<1> A_ADDR_DEC<7> net23<8> VDD VSS / ++ RSC_IHPSG13_NAND3X2 +XA_DEC3<22> A_P1<1> A_N0<1> A_ADDR_DEC<6> net23<9> VDD VSS / ++ RSC_IHPSG13_NAND3X2 +XA_DEC3<21> A_P1<1> A_N0<1> A_ADDR_DEC<5> net23<10> VDD VSS / ++ RSC_IHPSG13_NAND3X2 +XA_DEC3<20> A_P1<1> A_N0<1> A_ADDR_DEC<4> net23<11> VDD VSS / ++ RSC_IHPSG13_NAND3X2 +XA_DEC3<19> A_P1<1> A_N0<1> A_ADDR_DEC<3> net23<12> VDD VSS / ++ RSC_IHPSG13_NAND3X2 +XA_DEC3<18> A_P1<1> A_N0<1> A_ADDR_DEC<2> net23<13> VDD VSS / ++ RSC_IHPSG13_NAND3X2 +XA_DEC3<17> A_P1<1> A_N0<1> A_ADDR_DEC<1> net23<14> VDD VSS / ++ RSC_IHPSG13_NAND3X2 +XA_DEC3<16> A_P1<1> A_N0<1> A_ADDR_DEC<0> net23<15> VDD VSS / ++ RSC_IHPSG13_NAND3X2 +XA_DEC3<15> A_N1<0> A_P0<0> A_ADDR_DEC<7> net23<16> VDD VSS / ++ RSC_IHPSG13_NAND3X2 +XA_DEC3<14> A_N1<0> A_P0<0> A_ADDR_DEC<6> net23<17> VDD VSS / ++ RSC_IHPSG13_NAND3X2 +XA_DEC3<13> A_N1<0> A_P0<0> A_ADDR_DEC<5> net23<18> VDD VSS / ++ RSC_IHPSG13_NAND3X2 +XA_DEC3<12> A_N1<0> A_P0<0> A_ADDR_DEC<4> net23<19> VDD VSS / ++ RSC_IHPSG13_NAND3X2 +XA_DEC3<11> A_N1<0> A_P0<0> A_ADDR_DEC<3> net23<20> VDD VSS / ++ RSC_IHPSG13_NAND3X2 +XA_DEC3<10> A_N1<0> A_P0<0> A_ADDR_DEC<2> net23<21> VDD VSS / ++ RSC_IHPSG13_NAND3X2 +XA_DEC3<9> A_N1<0> A_P0<0> A_ADDR_DEC<1> net23<22> VDD VSS / ++ RSC_IHPSG13_NAND3X2 +XA_DEC3<8> A_N1<0> A_P0<0> A_ADDR_DEC<0> net23<23> VDD VSS / ++ RSC_IHPSG13_NAND3X2 +XA_DEC3<7> A_N1<0> A_N0<0> A_ADDR_DEC<7> net23<24> VDD VSS / ++ RSC_IHPSG13_NAND3X2 +XA_DEC3<6> A_N1<0> A_N0<0> A_ADDR_DEC<6> net23<25> VDD VSS / ++ RSC_IHPSG13_NAND3X2 +XA_DEC3<5> A_N1<0> A_N0<0> A_ADDR_DEC<5> net23<26> VDD VSS / ++ RSC_IHPSG13_NAND3X2 +XA_DEC3<4> A_N1<0> A_N0<0> A_ADDR_DEC<4> net23<27> VDD VSS / ++ RSC_IHPSG13_NAND3X2 +XA_DEC3<3> A_N1<0> A_N0<0> A_ADDR_DEC<3> net23<28> VDD VSS / ++ RSC_IHPSG13_NAND3X2 +XA_DEC3<2> A_N1<0> A_N0<0> A_ADDR_DEC<2> net23<29> VDD VSS / ++ RSC_IHPSG13_NAND3X2 +XA_DEC3<1> A_N1<0> A_N0<0> A_ADDR_DEC<1> net23<30> VDD VSS / ++ RSC_IHPSG13_NAND3X2 +XA_DEC3<0> A_N1<0> A_N0<0> A_ADDR_DEC<0> net23<31> VDD VSS / ++ RSC_IHPSG13_NAND3X2 +XA_I89 A_DCLK_B_L A_DCLK_B_R / RSC_IHPSG13_MET3RES +XA_I91 A_RCLK_B_L A_RCLK_B_R / RSC_IHPSG13_MET3RES +XA_I90 A_WCLK_B_L A_WCLK_B_R / RSC_IHPSG13_MET3RES +XA_I88 A_DCLK_L A_DCLK_R / RSC_IHPSG13_MET3RES +XA_I87 A_WCLK_L A_WCLK_R / RSC_IHPSG13_MET3RES +XA_R2 A_RCLK_L A_RCLK_R / RSC_IHPSG13_MET3RES +XA_BM_TIEH A_TIEH_O VDD VSS / RSC_IHPSG13_TIEH +.ENDS + +.SUBCKT RM_IHPSG13_8192x32_c4_1P_COLDRV13X12 ADDR_COL_I<1> ADDR_COL_I<0> ADDR_COL_O<1> ++ ADDR_COL_O<0> ADDR_DEC_I<7> ADDR_DEC_I<6> ADDR_DEC_I<5> ADDR_DEC_I<4> ++ ADDR_DEC_I<3> ADDR_DEC_I<2> ADDR_DEC_I<1> ADDR_DEC_I<0> ADDR_DEC_O<7> ++ ADDR_DEC_O<6> ADDR_DEC_O<5> ADDR_DEC_O<4> ADDR_DEC_O<3> ADDR_DEC_O<2> ++ ADDR_DEC_O<1> ADDR_DEC_O<0> DCLK_I DCLK_O RCLK_I RCLK_O WCLK_I WCLK_O ++ VDD VSS +XI1<1> VDD VSS / RSC_IHPSG13_FILLCAP4 +XI1<0> VDD VSS / RSC_IHPSG13_FILLCAP4 +XI0<1> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI0<0> VDD VSS / RSC_IHPSG13_FILLCAP8 +XADDR_COL_DRV<1> ADDR_COL_I<1> ADDR_COL_O<1> VDD VSS / ++ RSC_IHPSG13_CBUFX12 +XADDR_COL_DRV<0> ADDR_COL_I<0> ADDR_COL_O<0> VDD VSS / ++ RSC_IHPSG13_CBUFX12 +XADDR_DEC_DRV<7> ADDR_DEC_I<7> ADDR_DEC_O<7> VDD VSS / ++ RSC_IHPSG13_CBUFX12 +XADDR_DEC_DRV<6> ADDR_DEC_I<6> ADDR_DEC_O<6> VDD VSS / ++ RSC_IHPSG13_CBUFX12 +XADDR_DEC_DRV<5> ADDR_DEC_I<5> ADDR_DEC_O<5> VDD VSS / ++ RSC_IHPSG13_CBUFX12 +XADDR_DEC_DRV<4> ADDR_DEC_I<4> ADDR_DEC_O<4> VDD VSS / ++ RSC_IHPSG13_CBUFX12 +XADDR_DEC_DRV<3> ADDR_DEC_I<3> ADDR_DEC_O<3> VDD VSS / ++ RSC_IHPSG13_CBUFX12 +XADDR_DEC_DRV<2> ADDR_DEC_I<2> ADDR_DEC_O<2> VDD VSS / ++ RSC_IHPSG13_CBUFX12 +XADDR_DEC_DRV<1> ADDR_DEC_I<1> ADDR_DEC_O<1> VDD VSS / ++ RSC_IHPSG13_CBUFX12 +XADDR_DEC_DRV<0> ADDR_DEC_I<0> ADDR_DEC_O<0> VDD VSS / ++ RSC_IHPSG13_CBUFX12 +XDCLK_DRV DCLK_I DCLK_O VDD VSS / RSC_IHPSG13_CBUFX12 +XRCLK_DRV RCLK_I RCLK_O VDD VSS / RSC_IHPSG13_CBUFX12 +XWCLK_DRV WCLK_I WCLK_O VDD VSS / RSC_IHPSG13_CBUFX12 +.ENDS +.SUBCKT RM_IHPSG13_8192x32_c4_1P_WLDRV16X12 A<15> A<14> A<13> A<12> A<11> A<10> A<9> A<8> ++ A<7> A<6> A<5> A<4> A<3> A<2> A<1> A<0> Z<15> Z<14> Z<13> Z<12> Z<11> Z<10> ++ Z<9> Z<8> Z<7> Z<6> Z<5> Z<4> Z<3> Z<2> Z<1> Z<0> VDD VSS +XBUF<15> A<15> Z<15> VDD VSS / RSC_IHPSG13_WLDRVX12 +XBUF<14> A<14> Z<14> VDD VSS / RSC_IHPSG13_WLDRVX12 +XBUF<13> A<13> Z<13> VDD VSS / RSC_IHPSG13_WLDRVX12 +XBUF<12> A<12> Z<12> VDD VSS / RSC_IHPSG13_WLDRVX12 +XBUF<11> A<11> Z<11> VDD VSS / RSC_IHPSG13_WLDRVX12 +XBUF<10> A<10> Z<10> VDD VSS / RSC_IHPSG13_WLDRVX12 +XBUF<9> A<9> Z<9> VDD VSS / RSC_IHPSG13_WLDRVX12 +XBUF<8> A<8> Z<8> VDD VSS / RSC_IHPSG13_WLDRVX12 +XBUF<7> A<7> Z<7> VDD VSS / RSC_IHPSG13_WLDRVX12 +XBUF<6> A<6> Z<6> VDD VSS / RSC_IHPSG13_WLDRVX12 +XBUF<5> A<5> Z<5> VDD VSS / RSC_IHPSG13_WLDRVX12 +XBUF<4> A<4> Z<4> VDD VSS / RSC_IHPSG13_WLDRVX12 +XBUF<3> A<3> Z<3> VDD VSS / RSC_IHPSG13_WLDRVX12 +XBUF<2> A<2> Z<2> VDD VSS / RSC_IHPSG13_WLDRVX12 +XBUF<1> A<1> Z<1> VDD VSS / RSC_IHPSG13_WLDRVX12 +XBUF<0> A<0> Z<0> VDD VSS / RSC_IHPSG13_WLDRVX12 +.ENDS + + + +.SUBCKT RM_IHPSG13_8192x32_c4_2P_COLDRV13X8 ADDR_COL_I<1> ADDR_COL_I<0> ADDR_COL_O<1> ++ ADDR_COL_O<0> ADDR_DEC_I<7> ADDR_DEC_I<6> ADDR_DEC_I<5> ADDR_DEC_I<4> ++ ADDR_DEC_I<3> ADDR_DEC_I<2> ADDR_DEC_I<1> ADDR_DEC_I<0> ADDR_DEC_O<7> ++ ADDR_DEC_O<6> ADDR_DEC_O<5> ADDR_DEC_O<4> ADDR_DEC_O<3> ADDR_DEC_O<2> ++ ADDR_DEC_O<1> ADDR_DEC_O<0> DCLK_I DCLK_O RCLK_I RCLK_O WCLK_I WCLK_O ++ VDD VSS +XI0<5> VDD VSS / RSC_IHPSG13_FILLCAP4 +XI0<4> VDD VSS / RSC_IHPSG13_FILLCAP4 +XI0<3> VDD VSS / RSC_IHPSG13_FILLCAP4 +XI0<2> VDD VSS / RSC_IHPSG13_FILLCAP4 +XI0<1> VDD VSS / RSC_IHPSG13_FILLCAP4 +XWCLK_DRV WCLK_I WCLK_O VDD VSS / RSC_IHPSG13_CBUFX8 +XRCLK_DRV RCLK_I RCLK_O VDD VSS / RSC_IHPSG13_CBUFX8 +XDCLK_DRV DCLK_I DCLK_O VDD VSS / RSC_IHPSG13_CBUFX8 +XADDR_COL_DRV<1> ADDR_COL_I<1> ADDR_COL_O<1> VDD VSS / ++ RSC_IHPSG13_CBUFX8 +XADDR_COL_DRV<0> ADDR_COL_I<0> ADDR_COL_O<0> VDD VSS / ++ RSC_IHPSG13_CBUFX8 +XADDR_DEC_DRV<7> ADDR_DEC_I<7> ADDR_DEC_O<7> VDD VSS / ++ RSC_IHPSG13_CBUFX8 +XADDR_DEC_DRV<6> ADDR_DEC_I<6> ADDR_DEC_O<6> VDD VSS / ++ RSC_IHPSG13_CBUFX8 +XADDR_DEC_DRV<5> ADDR_DEC_I<5> ADDR_DEC_O<5> VDD VSS / ++ RSC_IHPSG13_CBUFX8 +XADDR_DEC_DRV<4> ADDR_DEC_I<4> ADDR_DEC_O<4> VDD VSS / ++ RSC_IHPSG13_CBUFX8 +XADDR_DEC_DRV<3> ADDR_DEC_I<3> ADDR_DEC_O<3> VDD VSS / ++ RSC_IHPSG13_CBUFX8 +XADDR_DEC_DRV<2> ADDR_DEC_I<2> ADDR_DEC_O<2> VDD VSS / ++ RSC_IHPSG13_CBUFX8 +XADDR_DEC_DRV<1> ADDR_DEC_I<1> ADDR_DEC_O<1> VDD VSS / ++ RSC_IHPSG13_CBUFX8 +XADDR_DEC_DRV<0> ADDR_DEC_I<0> ADDR_DEC_O<0> VDD VSS / ++ RSC_IHPSG13_CBUFX8 +XI1<3> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI1<2> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI1<1> VDD VSS / RSC_IHPSG13_FILLCAP8 +.ENDS +.SUBCKT RSC_IHPSG13_WLDRVX8 A Z VDD VSS +MN1 Z net6 VSS VSS sg13_lv_nmos m=1 w=1.41u l=130.00n ng=2 nrd=0 nrs=0 +MN0 net6 A VSS VSS sg13_lv_nmos m=1 w=1.8u l=130.00n ng=2 nrd=0 nrs=0 +MP1 Z net6 VDD VDD sg13_lv_pmos m=1 w=6.48u l=130.00n ng=4 nrd=0 nrs=0 +MP0 net6 A VDD VDD sg13_lv_pmos m=1 w=900.0n l=130.00n ng=1 nrd=0 nrs=0 +.ENDS +.SUBCKT RM_IHPSG13_8192x32_c4_2P_WLDRV16X8 A<15> A<14> A<13> A<12> A<11> A<10> A<9> A<8> ++ A<7> A<6> A<5> A<4> A<3> A<2> A<1> A<0> Z<15> Z<14> Z<13> Z<12> Z<11> Z<10> ++ Z<9> Z<8> Z<7> Z<6> Z<5> Z<4> Z<3> Z<2> Z<1> Z<0> VDD VSS +XBUF<15> A<15> Z<15> VDD VSS / RSC_IHPSG13_WLDRVX8 +XBUF<14> A<14> Z<14> VDD VSS / RSC_IHPSG13_WLDRVX8 +XBUF<13> A<13> Z<13> VDD VSS / RSC_IHPSG13_WLDRVX8 +XBUF<12> A<12> Z<12> VDD VSS / RSC_IHPSG13_WLDRVX8 +XBUF<11> A<11> Z<11> VDD VSS / RSC_IHPSG13_WLDRVX8 +XBUF<10> A<10> Z<10> VDD VSS / RSC_IHPSG13_WLDRVX8 +XBUF<9> A<9> Z<9> VDD VSS / RSC_IHPSG13_WLDRVX8 +XBUF<8> A<8> Z<8> VDD VSS / RSC_IHPSG13_WLDRVX8 +XBUF<7> A<7> Z<7> VDD VSS / RSC_IHPSG13_WLDRVX8 +XBUF<6> A<6> Z<6> VDD VSS / RSC_IHPSG13_WLDRVX8 +XBUF<5> A<5> Z<5> VDD VSS / RSC_IHPSG13_WLDRVX8 +XBUF<4> A<4> Z<4> VDD VSS / RSC_IHPSG13_WLDRVX8 +XBUF<3> A<3> Z<3> VDD VSS / RSC_IHPSG13_WLDRVX8 +XBUF<2> A<2> Z<2> VDD VSS / RSC_IHPSG13_WLDRVX8 +XBUF<1> A<1> Z<1> VDD VSS / RSC_IHPSG13_WLDRVX8 +XBUF<0> A<0> Z<0> VDD VSS / RSC_IHPSG13_WLDRVX8 +.ENDS + + + +.SUBCKT RM_IHPSG13_8192x32_c4_2P_COLDEC2 ACLK_N ADDR<1> ADDR<0> ADDR_COL<1> ADDR_COL<0> ++ ADDR_DEC<7> ADDR_DEC<6> ADDR_DEC<5> ADDR_DEC<4> ADDR_DEC<3> ADDR_DEC<2> ++ ADDR_DEC<1> ADDR_DEC<0> BIST_ADDR<1> BIST_ADDR<0> BIST_EN_I VDD VSS +XI16<17> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI16<16> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI16<15> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI16<14> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI16<13> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI16<12> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI16<11> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI16<10> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI16<9> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI16<8> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI16<7> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI16<6> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI16<5> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI16<4> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI16<3> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI16<2> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI16<1> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI18<24> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI18<23> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI18<22> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI18<21> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI18<20> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI18<19> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI18<18> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI18<17> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI18<16> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI18<15> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI18<14> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI18<13> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI18<12> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI18<11> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI18<10> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI18<9> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI18<8> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI18<7> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI18<6> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI18<5> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI18<4> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI18<3> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI18<2> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI18<1> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI1<3> PADR<0> PADR<1> addr_n<3> VDD VSS / RSC_IHPSG13_NAND2X2 +XI1<2> NADR<0> PADR<1> addr_n<2> VDD VSS / RSC_IHPSG13_NAND2X2 +XI1<1> PADR<0> NADR<1> addr_n<1> VDD VSS / RSC_IHPSG13_NAND2X2 +XI1<0> NADR<0> NADR<1> addr_n<0> VDD VSS / RSC_IHPSG13_NAND2X2 +XI17<1> ADDR_COL<1> VDD VSS / RSC_IHPSG13_TIEL +XI17<0> ADDR_COL<0> VDD VSS / RSC_IHPSG13_TIEL +XI14<3> ADDR_DEC<7> VDD VSS / RSC_IHPSG13_TIEL +XI14<2> ADDR_DEC<6> VDD VSS / RSC_IHPSG13_TIEL +XI14<1> ADDR_DEC<5> VDD VSS / RSC_IHPSG13_TIEL +XI14<0> ADDR_DEC<4> VDD VSS / RSC_IHPSG13_TIEL +XI13<1> NADR<1> PADR<1> VDD VSS / RSC_IHPSG13_INVX2 +XI13<0> NADR<0> PADR<0> VDD VSS / RSC_IHPSG13_INVX2 +XI3<1> padr_int<1> NADR<1> VDD VSS / RSC_IHPSG13_INVX2 +XI3<0> padr_int<0> NADR<0> VDD VSS / RSC_IHPSG13_INVX2 +XI2<3> addr_n<3> ADDR_DEC<3> VDD VSS / RSC_IHPSG13_INVX2 +XI2<2> addr_n<2> ADDR_DEC<2> VDD VSS / RSC_IHPSG13_INVX2 +XI2<1> addr_n<1> ADDR_DEC<1> VDD VSS / RSC_IHPSG13_INVX2 +XI2<0> addr_n<0> ADDR_DEC<0> VDD VSS / RSC_IHPSG13_INVX2 +XDFF<1> BIST_EN_I BIST_ADDR<1> ACLK_N ADDR<1> padr_int<1> net12<0> VDD ++ VSS / RSC_IHPSG13_DFNQMX2IX1 +XDFF<0> BIST_EN_I BIST_ADDR<0> ACLK_N ADDR<0> padr_int<0> net12<1> VDD ++ VSS / RSC_IHPSG13_DFNQMX2IX1 +XI15<5> VDD VSS / RSC_IHPSG13_FILLCAP4 +XI15<4> VDD VSS / RSC_IHPSG13_FILLCAP4 +XI15<3> VDD VSS / RSC_IHPSG13_FILLCAP4 +XI15<2> VDD VSS / RSC_IHPSG13_FILLCAP4 +XI15<1> VDD VSS / RSC_IHPSG13_FILLCAP4 +XI19<4> VDD VSS / RSC_IHPSG13_FILLCAP4 +XI19<3> VDD VSS / RSC_IHPSG13_FILLCAP4 +XI19<2> VDD VSS / RSC_IHPSG13_FILLCAP4 +XI19<1> VDD VSS / RSC_IHPSG13_FILLCAP4 +.ENDS +.SUBCKT RM_IHPSG13_8192x32_c4_2P_COLCTRL2 A_ADDR_DEC<3> A_ADDR_DEC<2> A_ADDR_DEC<1> ++ A_ADDR_DEC<0> A_BIST_BM_I A_BIST_DW_I A_BIST_EN_I A_BLC<3> A_BLC<2> A_BLC<1> ++ A_BLC<0> A_BLT<3> A_BLT<2> A_BLT<1> A_BLT<0> A_BM_I A_DCLK_B_L A_DCLK_B_R ++ A_DCLK_L A_DCLK_R A_DR_O A_DW_I A_RCLK_B_L A_RCLK_B_R A_RCLK_L A_RCLK_R ++ A_TIEH_O A_WCLK_B_L A_WCLK_B_R A_WCLK_L A_WCLK_R B_ADDR_DEC<3> B_ADDR_DEC<2> ++ B_ADDR_DEC<1> B_ADDR_DEC<0> B_BIST_BM_I B_BIST_DW_I B_BIST_EN_I B_BLC<3> ++ B_BLC<2> B_BLC<1> B_BLC<0> B_BLT<3> B_BLT<2> B_BLT<1> B_BLT<0> B_BM_I ++ B_DCLK_B_L B_DCLK_B_R B_DCLK_L B_DCLK_R B_DR_O B_DW_I B_RCLK_B_L B_RCLK_B_R ++ B_RCLK_L B_RCLK_R B_TIEH_O B_WCLK_B_L B_WCLK_B_R B_WCLK_L B_WCLK_R VDD ++ VSS +XB_DREG B_BIST_EN_I B_BIST_DW_I B_DCLK_B_L B_DW_I B_DI_R net046 VDD ++ VSS / RSC_IHPSG13_DFNQMX2IX1 +XB_BREG B_BIST_EN_I B_BIST_BM_I B_DCLK_B_L B_BM_I B_BM_R net045 VDD ++ VSS / RSC_IHPSG13_DFNQMX2IX1 +XA_DREG A_BIST_EN_I A_BIST_DW_I A_DCLK_B_L A_DW_I A_DI_R net22 VDD VSS ++ / RSC_IHPSG13_DFNQMX2IX1 +XA_BREG A_BIST_EN_I A_BIST_BM_I A_DCLK_B_L A_BM_I A_BM_R net23 VDD VSS ++ / RSC_IHPSG13_DFNQMX2IX1 +XB_CAPS VDD VSS / RSC_IHPSG13_FILLCAP4 +XA_CAPS VDD VSS / RSC_IHPSG13_FILLCAP4 +XB_I75 B_DI_R B_DO_WRITE_P B_WR_ONE VDD VSS / RSC_IHPSG13_AND2X2 +XB_I80 B_RCLK_B_L B_WCLK_B_L net041 VDD VSS / RSC_IHPSG13_AND2X2 +XB_I76 B_DI_N B_DO_WRITE_P B_WR_ZERO VDD VSS / RSC_IHPSG13_AND2X2 +XA_I80 A_RCLK_B_L A_WCLK_B_L net21 VDD VSS / RSC_IHPSG13_AND2X2 +XA_I75 A_DI_R A_DO_WRITE_P A_WR_ONE VDD VSS / RSC_IHPSG13_AND2X2 +XA_I76 A_DI_N A_DO_WRITE_P A_WR_ZERO VDD VSS / RSC_IHPSG13_AND2X2 +XB_I44 B_WCLK_B_L B_BM_N B_DO_WRITE_P VDD VSS / RSC_IHPSG13_NOR2X2 +XA_I44 A_WCLK_B_L A_BM_N A_DO_WRITE_P VDD VSS / RSC_IHPSG13_NOR2X2 +XB_I81 net041 B_PRE_N VDD VSS / RSC_IHPSG13_CINVX4_WN +XA_I81 net21 A_PRE_N VDD VSS / RSC_IHPSG13_CINVX4_WN +XB_BM_TIEH B_TIEH_O VDD VSS / RSC_IHPSG13_TIEH +XA_BM_TIEH A_TIEH_O VDD VSS / RSC_IHPSG13_TIEH +XA_I89 A_DCLK_B_L A_DCLK_B_R / RSC_IHPSG13_MET3RES +XA_I88 A_DCLK_L A_DCLK_R / RSC_IHPSG13_MET3RES +XA_I87 A_WCLK_L A_WCLK_R / RSC_IHPSG13_MET3RES +XA_I91 A_RCLK_B_L A_RCLK_B_R / RSC_IHPSG13_MET3RES +XB_I87 B_WCLK_L B_WCLK_R / RSC_IHPSG13_MET3RES +XB_I88 B_DCLK_L B_DCLK_R / RSC_IHPSG13_MET3RES +XB_I89 B_DCLK_B_L B_DCLK_B_R / RSC_IHPSG13_MET3RES +XB_I90 B_WCLK_B_L B_WCLK_B_R / RSC_IHPSG13_MET3RES +XB_R2 B_RCLK_L B_RCLK_R / RSC_IHPSG13_MET3RES +XB_I91 B_RCLK_B_L B_RCLK_B_R / RSC_IHPSG13_MET3RES +XA_R2 A_RCLK_L A_RCLK_R / RSC_IHPSG13_MET3RES +XA_I90 A_WCLK_B_L A_WCLK_B_R / RSC_IHPSG13_MET3RES +XAB_BLMUX A_BLC<3> A_BLC<2> A_BLC<1> A_BLC<0> A_BLC_SEL A_BLT<3> A_BLT<2> ++ A_BLT<1> A_BLT<0> A_BLT_SEL A_PRE_N A_ADDR_DEC<3> A_ADDR_DEC<2> ++ A_ADDR_DEC<1> A_ADDR_DEC<0> A_WR_ONE A_WR_ZERO B_BLC<3> B_BLC<2> B_BLC<1> ++ B_BLC<0> B_BLC_SEL B_BLT<3> B_BLT<2> B_BLT<1> B_BLT<0> B_BLT_SEL B_PRE_N ++ B_ADDR_DEC<3> B_ADDR_DEC<2> B_ADDR_DEC<1> B_ADDR_DEC<0> B_WR_ONE B_WR_ZERO ++ VDD VSS / RM_IHPSG13_8192x32_c4_2P_BLDRV +XB_ISENSE B_SAE B_BLC_SEL B_BLT_SEL net039 net040 VDD VSS / ++ RSC_IHPSG13_DFPQD_MSAFFX2 +XA_ISENSE A_SAE A_BLC_SEL A_BLT_SEL net19 net20 VDD VSS / ++ RSC_IHPSG13_DFPQD_MSAFFX2 +XB_I78 B_RCLK_B_L B_SAE VDD VSS / RSC_IHPSG13_CBUFX2 +XA_I78 A_RCLK_B_L A_SAE VDD VSS / RSC_IHPSG13_CBUFX2 +XB_I83 B_BM_R B_BM_N VDD VSS / RSC_IHPSG13_INVX2 +XB_I49 B_DI_R B_DI_N VDD VSS / RSC_IHPSG13_INVX2 +XA_I83 A_BM_R A_BM_N VDD VSS / RSC_IHPSG13_INVX2 +XA_I49 A_DI_R A_DI_N VDD VSS / RSC_IHPSG13_INVX2 +XB_I51 net039 B_DR_O VDD VSS / RSC_IHPSG13_INVX4 +XA_I51 net19 A_DR_O VDD VSS / RSC_IHPSG13_INVX4 +XA_I69 A_DCLK_L A_DCLK_B_L VDD VSS / RSC_IHPSG13_CINVX2 +XA_I50 A_WCLK_L A_WCLK_B_L VDD VSS / RSC_IHPSG13_CINVX2 +XA_EBUF A_RCLK_L A_RCLK_B_L VDD VSS / RSC_IHPSG13_CINVX2 +XB_EBUF B_RCLK_L B_RCLK_B_L VDD VSS / RSC_IHPSG13_CINVX2 +XB_I50 B_WCLK_L B_WCLK_B_L VDD VSS / RSC_IHPSG13_CINVX2 +XB_I69 B_DCLK_L B_DCLK_B_L VDD VSS / RSC_IHPSG13_CINVX2 +.ENDS +.SUBCKT RM_IHPSG13_8192x32_c4_2P_COLDRV13_FILL4C2 VDD VSS +XI0<2> VDD VSS / RSC_IHPSG13_FILLCAP4 +XI0<1> VDD VSS / RSC_IHPSG13_FILLCAP4 +.ENDS + + +.SUBCKT RM_IHPSG13_8192x32_c4_2P_ROWDEC7 ADDR_N_I<6> ADDR_N_I<5> ADDR_N_I<4> ADDR_N_I<3> ++ ADDR_N_I<2> ADDR_N_I<1> ADDR_N_I<0> CS_I ECLK_I WL_O<127> WL_O<126> ++ WL_O<125> WL_O<124> WL_O<123> WL_O<122> WL_O<121> WL_O<120> WL_O<119> ++ WL_O<118> WL_O<117> WL_O<116> WL_O<115> WL_O<114> WL_O<113> WL_O<112> ++ WL_O<111> WL_O<110> WL_O<109> WL_O<108> WL_O<107> WL_O<106> WL_O<105> ++ WL_O<104> WL_O<103> WL_O<102> WL_O<101> WL_O<100> WL_O<99> WL_O<98> WL_O<97> ++ WL_O<96> WL_O<95> WL_O<94> WL_O<93> WL_O<92> WL_O<91> WL_O<90> WL_O<89> ++ WL_O<88> WL_O<87> WL_O<86> WL_O<85> WL_O<84> WL_O<83> WL_O<82> WL_O<81> ++ WL_O<80> WL_O<79> WL_O<78> WL_O<77> WL_O<76> WL_O<75> WL_O<74> WL_O<73> ++ WL_O<72> WL_O<71> WL_O<70> WL_O<69> WL_O<68> WL_O<67> WL_O<66> WL_O<65> ++ WL_O<64> WL_O<63> WL_O<62> WL_O<61> WL_O<60> WL_O<59> WL_O<58> WL_O<57> ++ WL_O<56> WL_O<55> WL_O<54> WL_O<53> WL_O<52> WL_O<51> WL_O<50> WL_O<49> ++ WL_O<48> WL_O<47> WL_O<46> WL_O<45> WL_O<44> WL_O<43> WL_O<42> WL_O<41> ++ WL_O<40> WL_O<39> WL_O<38> WL_O<37> WL_O<36> WL_O<35> WL_O<34> WL_O<33> ++ WL_O<32> WL_O<31> WL_O<30> WL_O<29> WL_O<28> WL_O<27> WL_O<26> WL_O<25> ++ WL_O<24> WL_O<23> WL_O<22> WL_O<21> WL_O<20> WL_O<19> WL_O<18> WL_O<17> ++ WL_O<16> WL_O<15> WL_O<14> WL_O<13> WL_O<12> WL_O<11> WL_O<10> WL_O<9> ++ WL_O<8> WL_O<7> WL_O<6> WL_O<5> WL_O<4> WL_O<3> WL_O<2> WL_O<1> WL_O<0> ++ VDD VSS +XSEL<7> ADDR_N_I<3> ADDR_N_I<2> ADDR_N_I<1> ADDR_N_I<0> CS00<7> ECLK_H<7> ++ ECLK_H<8> ECLK_B<7> ECLK_B<8> WL_O<127> WL_O<126> WL_O<125> WL_O<124> ++ WL_O<123> WL_O<122> WL_O<121> WL_O<120> WL_O<119> WL_O<118> WL_O<117> ++ WL_O<116> WL_O<115> WL_O<114> WL_O<113> WL_O<112> VDD VSS / ++ RM_IHPSG13_8192x32_c4_2P_DEC04 +XSEL<6> ADDR_N_I<3> ADDR_N_I<2> ADDR_N_I<1> ADDR_N_I<0> CS00<6> ECLK_H<6> ++ ECLK_H<7> ECLK_B<6> ECLK_B<7> WL_O<111> WL_O<110> WL_O<109> WL_O<108> ++ WL_O<107> WL_O<106> WL_O<105> WL_O<104> WL_O<103> WL_O<102> WL_O<101> ++ WL_O<100> WL_O<99> WL_O<98> WL_O<97> WL_O<96> VDD VSS / ++ RM_IHPSG13_8192x32_c4_2P_DEC04 +XSEL<5> ADDR_N_I<3> ADDR_N_I<2> ADDR_N_I<1> ADDR_N_I<0> CS00<5> ECLK_H<5> ++ ECLK_H<6> ECLK_B<5> ECLK_B<6> WL_O<95> WL_O<94> WL_O<93> WL_O<92> WL_O<91> ++ WL_O<90> WL_O<89> WL_O<88> WL_O<87> WL_O<86> WL_O<85> WL_O<84> WL_O<83> ++ WL_O<82> WL_O<81> WL_O<80> VDD VSS / RM_IHPSG13_8192x32_c4_2P_DEC04 +XSEL<4> ADDR_N_I<3> ADDR_N_I<2> ADDR_N_I<1> ADDR_N_I<0> CS00<4> ECLK_H<4> ++ ECLK_H<5> ECLK_B<4> ECLK_B<5> WL_O<79> WL_O<78> WL_O<77> WL_O<76> WL_O<75> ++ WL_O<74> WL_O<73> WL_O<72> WL_O<71> WL_O<70> WL_O<69> WL_O<68> WL_O<67> ++ WL_O<66> WL_O<65> WL_O<64> VDD VSS / RM_IHPSG13_8192x32_c4_2P_DEC04 +XSEL<3> ADDR_N_I<3> ADDR_N_I<2> ADDR_N_I<1> ADDR_N_I<0> CS00<3> ECLK_H<3> ++ ECLK_H<4> ECLK_B<3> ECLK_B<4> WL_O<63> WL_O<62> WL_O<61> WL_O<60> WL_O<59> ++ WL_O<58> WL_O<57> WL_O<56> WL_O<55> WL_O<54> WL_O<53> WL_O<52> WL_O<51> ++ WL_O<50> WL_O<49> WL_O<48> VDD VSS / RM_IHPSG13_8192x32_c4_2P_DEC04 +XSEL<2> ADDR_N_I<3> ADDR_N_I<2> ADDR_N_I<1> ADDR_N_I<0> CS00<2> ECLK_H<2> ++ ECLK_H<3> ECLK_B<2> ECLK_B<3> WL_O<47> WL_O<46> WL_O<45> WL_O<44> WL_O<43> ++ WL_O<42> WL_O<41> WL_O<40> WL_O<39> WL_O<38> WL_O<37> WL_O<36> WL_O<35> ++ WL_O<34> WL_O<33> WL_O<32> VDD VSS / RM_IHPSG13_8192x32_c4_2P_DEC04 +XSEL<1> ADDR_N_I<3> ADDR_N_I<2> ADDR_N_I<1> ADDR_N_I<0> CS00<1> ECLK_H<1> ++ ECLK_H<2> ECLK_B<1> ECLK_B<2> WL_O<31> WL_O<30> WL_O<29> WL_O<28> WL_O<27> ++ WL_O<26> WL_O<25> WL_O<24> WL_O<23> WL_O<22> WL_O<21> WL_O<20> WL_O<19> ++ WL_O<18> WL_O<17> WL_O<16> VDD VSS / RM_IHPSG13_8192x32_c4_2P_DEC04 +XSEL<0> ADDR_N_I<3> ADDR_N_I<2> ADDR_N_I<1> ADDR_N_I<0> CS00<0> ECLK_I ++ ECLK_H<1> ECLK_B<0> ECLK_B<1> WL_O<15> WL_O<14> WL_O<13> WL_O<12> WL_O<11> ++ WL_O<10> WL_O<9> WL_O<8> WL_O<7> WL_O<6> WL_O<5> WL_O<4> WL_O<3> WL_O<2> ++ WL_O<1> WL_O<0> VDD VSS / RM_IHPSG13_8192x32_c4_2P_DEC04 +XDEC11<1> ADDR_N_I<5> ADDR_N_I<4> CS04<1> CS00<7> VDD VSS / ++ RM_IHPSG13_8192x32_c4_2P_DEC03 +XDEC11<0> ADDR_N_I<5> ADDR_N_I<4> CS04<0> CS00<3> VDD VSS / ++ RM_IHPSG13_8192x32_c4_2P_DEC03 +XDEC01<2> ADDR_N_I<7> ADDR_N_I<6> CS_I CS04<1> VDD VSS / ++ RM_IHPSG13_8192x32_c4_2P_DEC01 +XDEC01<1> ADDR_N_I<5> ADDR_N_I<4> CS04<1> CS00<5> VDD VSS / ++ RM_IHPSG13_8192x32_c4_2P_DEC01 +XDEC01<0> ADDR_N_I<5> ADDR_N_I<4> CS04<0> CS00<1> VDD VSS / ++ RM_IHPSG13_8192x32_c4_2P_DEC01 +XL2<66> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<65> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<64> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<63> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<62> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<61> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<60> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<59> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<58> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<57> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<56> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<55> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<54> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<53> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<52> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<51> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<50> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<49> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<48> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<47> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<46> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<45> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<44> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<43> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<42> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<41> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<40> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<39> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<38> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<37> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<36> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<35> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<34> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<33> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<32> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<31> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<30> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<29> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<28> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<27> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<26> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<25> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<24> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<23> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<22> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<21> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<20> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<19> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<18> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<17> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<16> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<15> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<14> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<13> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<12> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<11> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<10> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<9> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<8> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<7> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<6> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<5> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<4> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<3> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<2> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<1> VDD VSS / RSC_IHPSG13_FILLCAP8 +XDEC10<1> ADDR_N_I<5> ADDR_N_I<4> CS04<1> CS00<6> VDD VSS / ++ RM_IHPSG13_8192x32_c4_2P_DEC02 +XDEC10<0> ADDR_N_I<5> ADDR_N_I<4> CS04<0> CS00<2> VDD VSS / ++ RM_IHPSG13_8192x32_c4_2P_DEC02 +XDEC00<2> ADDR_N_I<7> ADDR_N_I<6> CS_I CS04<0> VDD VSS / ++ RM_IHPSG13_8192x32_c4_2P_DEC00 +XDEC00<1> ADDR_N_I<5> ADDR_N_I<4> CS04<1> CS00<4> VDD VSS / ++ RM_IHPSG13_8192x32_c4_2P_DEC00 +XDEC00<0> ADDR_N_I<5> ADDR_N_I<4> CS04<0> CS00<0> VDD VSS / ++ RM_IHPSG13_8192x32_c4_2P_DEC00 +XI0 ADDR_N_I<7> VDD VSS / RSC_IHPSG13_TIEL +.ENDS +.SUBCKT RM_IHPSG13_8192x32_c4_2P_ROWREG7 ACLK_N_I ADDR_I<6> ADDR_I<5> ADDR_I<4> ADDR_I<3> ++ ADDR_I<2> ADDR_I<1> ADDR_I<0> ADDR_N_O<6> ADDR_N_O<5> ADDR_N_O<4> ++ ADDR_N_O<3> ADDR_N_O<2> ADDR_N_O<1> ADDR_N_O<0> BIST_ADDR_I<6> ++ BIST_ADDR_I<5> BIST_ADDR_I<4> BIST_ADDR_I<3> BIST_ADDR_I<2> BIST_ADDR_I<1> ++ BIST_ADDR_I<0> BIST_EN_I VDD VSS +XINV<6> q_int<6> qn_int<6> VDD VSS / RSC_IHPSG13_CINVX2 +XINV<5> q_int<5> qn_int<5> VDD VSS / RSC_IHPSG13_CINVX2 +XINV<4> q_int<4> qn_int<4> VDD VSS / RSC_IHPSG13_CINVX2 +XINV<3> q_int<3> qn_int<3> VDD VSS / RSC_IHPSG13_CINVX2 +XINV<2> q_int<2> qn_int<2> VDD VSS / RSC_IHPSG13_CINVX2 +XINV<1> q_int<1> qn_int<1> VDD VSS / RSC_IHPSG13_CINVX2 +XINV<0> q_int<0> qn_int<0> VDD VSS / RSC_IHPSG13_CINVX2 +XDRV<6> qn_int<6> ADDR_N_O<6> VDD VSS / RSC_IHPSG13_CINVX8 +XDRV<5> qn_int<5> ADDR_N_O<5> VDD VSS / RSC_IHPSG13_CINVX8 +XDRV<4> qn_int<4> ADDR_N_O<4> VDD VSS / RSC_IHPSG13_CINVX8 +XDRV<3> qn_int<3> ADDR_N_O<3> VDD VSS / RSC_IHPSG13_CINVX8 +XDRV<2> qn_int<2> ADDR_N_O<2> VDD VSS / RSC_IHPSG13_CINVX8 +XDRV<1> qn_int<1> ADDR_N_O<1> VDD VSS / RSC_IHPSG13_CINVX8 +XDRV<0> qn_int<0> ADDR_N_O<0> VDD VSS / RSC_IHPSG13_CINVX8 +XDFF<6> BIST_EN_I BIST_ADDR_I<6> ACLK_N_I ADDR_I<6> q_int<6> net2<0> VDD ++ VSS / RSC_IHPSG13_DFNQMX2IX1 +XDFF<5> BIST_EN_I BIST_ADDR_I<5> ACLK_N_I ADDR_I<5> q_int<5> net2<1> VDD ++ VSS / RSC_IHPSG13_DFNQMX2IX1 +XDFF<4> BIST_EN_I BIST_ADDR_I<4> ACLK_N_I ADDR_I<4> q_int<4> net2<2> VDD ++ VSS / RSC_IHPSG13_DFNQMX2IX1 +XDFF<3> BIST_EN_I BIST_ADDR_I<3> ACLK_N_I ADDR_I<3> q_int<3> net2<3> VDD ++ VSS / RSC_IHPSG13_DFNQMX2IX1 +XDFF<2> BIST_EN_I BIST_ADDR_I<2> ACLK_N_I ADDR_I<2> q_int<2> net2<4> VDD ++ VSS / RSC_IHPSG13_DFNQMX2IX1 +XDFF<1> BIST_EN_I BIST_ADDR_I<1> ACLK_N_I ADDR_I<1> q_int<1> net2<5> VDD ++ VSS / RSC_IHPSG13_DFNQMX2IX1 +XDFF<0> BIST_EN_I BIST_ADDR_I<0> ACLK_N_I ADDR_I<0> q_int<0> net2<6> VDD ++ VSS / RSC_IHPSG13_DFNQMX2IX1 +XI11<7> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI11<6> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI11<5> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI11<4> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI11<3> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI11<2> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI11<1> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI11<0> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI12<1> VDD VSS / RSC_IHPSG13_FILLCAP4 +XI12<0> VDD VSS / RSC_IHPSG13_FILLCAP4 +.ENDS + +.SUBCKT RM_IHPSG13_8192x32_c4_2P_ROWDEC4 ADDR_N_I<3> ADDR_N_I<2> ADDR_N_I<1> ADDR_N_I<0> ++ CS_I ECLK_I WL_O<15> WL_O<14> WL_O<13> WL_O<12> WL_O<11> WL_O<10> WL_O<9> ++ WL_O<8> WL_O<7> WL_O<6> WL_O<5> WL_O<4> WL_O<3> WL_O<2> WL_O<1> WL_O<0> ++ VDD VSS +XL2<12> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<11> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<10> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<9> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<8> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<7> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<6> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<5> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<4> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<3> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<2> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<1> VDD VSS / RSC_IHPSG13_FILLCAP8 +XSEL ADDR_N_I<3> ADDR_N_I<2> ADDR_N_I<1> ADDR_N_I<0> CS_I ECLK_I ECLK_H<1> ++ ECLK_B<0> ECLK_B<1> WL_O<15> WL_O<14> WL_O<13> WL_O<12> WL_O<11> WL_O<10> ++ WL_O<9> WL_O<8> WL_O<7> WL_O<6> WL_O<5> WL_O<4> WL_O<3> WL_O<2> WL_O<1> ++ WL_O<0> VDD VSS / RM_IHPSG13_8192x32_c4_2P_DEC04 +.ENDS +.SUBCKT RM_IHPSG13_8192x32_c4_2P_ROWREG4 ACLK_N_I ADDR_I<3> ADDR_I<2> ADDR_I<1> ADDR_I<0> ++ ADDR_N_O<3> ADDR_N_O<2> ADDR_N_O<1> ADDR_N_O<0> BIST_ADDR_I<3> ++ BIST_ADDR_I<2> BIST_ADDR_I<1> BIST_ADDR_I<0> BIST_EN_I VDD VSS +XINV<3> q_int<3> qn_int<3> VDD VSS / RSC_IHPSG13_CINVX2 +XINV<2> q_int<2> qn_int<2> VDD VSS / RSC_IHPSG13_CINVX2 +XINV<1> q_int<1> qn_int<1> VDD VSS / RSC_IHPSG13_CINVX2 +XINV<0> q_int<0> qn_int<0> VDD VSS / RSC_IHPSG13_CINVX2 +XDRV<3> qn_int<3> ADDR_N_O<3> VDD VSS / RSC_IHPSG13_CINVX8 +XDRV<2> qn_int<2> ADDR_N_O<2> VDD VSS / RSC_IHPSG13_CINVX8 +XDRV<1> qn_int<1> ADDR_N_O<1> VDD VSS / RSC_IHPSG13_CINVX8 +XDRV<0> qn_int<0> ADDR_N_O<0> VDD VSS / RSC_IHPSG13_CINVX8 +XDFF<3> BIST_EN_I BIST_ADDR_I<3> ACLK_N_I ADDR_I<3> q_int<3> net7<0> VDD ++ VSS / RSC_IHPSG13_DFNQMX2IX1 +XDFF<2> BIST_EN_I BIST_ADDR_I<2> ACLK_N_I ADDR_I<2> q_int<2> net7<1> VDD ++ VSS / RSC_IHPSG13_DFNQMX2IX1 +XDFF<1> BIST_EN_I BIST_ADDR_I<1> ACLK_N_I ADDR_I<1> q_int<1> net7<2> VDD ++ VSS / RSC_IHPSG13_DFNQMX2IX1 +XDFF<0> BIST_EN_I BIST_ADDR_I<0> ACLK_N_I ADDR_I<0> q_int<0> net7<3> VDD ++ VSS / RSC_IHPSG13_DFNQMX2IX1 +XI11<20> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI11<19> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI11<18> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI11<17> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI11<16> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI11<15> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI11<14> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI11<13> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI11<12> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI11<11> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI11<10> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI11<9> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI11<8> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI11<7> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI11<6> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI11<5> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI11<4> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI11<3> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI11<2> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI11<1> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI12<4> VDD VSS / RSC_IHPSG13_FILLCAP4 +XI12<3> VDD VSS / RSC_IHPSG13_FILLCAP4 +XI12<2> VDD VSS / RSC_IHPSG13_FILLCAP4 +XI12<1> VDD VSS / RSC_IHPSG13_FILLCAP4 +XI12<0> VDD VSS / RSC_IHPSG13_FILLCAP4 +.ENDS + + +.SUBCKT RM_IHPSG13_8192x32_c4_1P_BITKIT_TAP BLC BLT NW PW VDD VSS +.ENDS +.SUBCKT RM_IHPSG13_8192x32_c4_1P_BITKIT_16x2_TAP A_BLC<1> A_BLC<0> A_BLT<1> A_BLT<0> ++ VDD_CORE VSS +XITAP<1> A_BLC<1> A_BLT<1> VDD_CORE VSS VDD_CORE VSS ++ / RM_IHPSG13_8192x32_c4_1P_BITKIT_TAP +XITAP<0> A_BLC<0> A_BLT<0> VDD_CORE VSS VDD_CORE VSS ++ / RM_IHPSG13_8192x32_c4_1P_BITKIT_TAP +XIEDGEBP_COL1<1> BLC<1> BLT<1> VDD_CORE VSS VDD_CORE ++ VSS / RM_IHPSG13_8192x32_c4_1P_BITKIT_EDGE_TB +XIEDGEBP_COL1<0> BLC<1> BLT<1> VDD_CORE VSS VDD_CORE ++ VSS / RM_IHPSG13_8192x32_c4_1P_BITKIT_EDGE_TB +XIEDGEBP_COL2<1> BLC<0> BLT<0> VDD_CORE VSS VDD_CORE ++ VSS / RM_IHPSG13_8192x32_c4_1P_BITKIT_EDGE_TB +XIEDGEBP_COL2<0> BLC<0> BLT<0> VDD_CORE VSS VDD_CORE ++ VSS / RM_IHPSG13_8192x32_c4_1P_BITKIT_EDGE_TB +.ENDS +.SUBCKT RM_IHPSG13_8192x32_c4_1P_BITKIT_16x2_TAP_LR VDD_CORE VSS +XCORNER<1> VDD_CORE VSS VDD_CORE VSS / ++ RM_IHPSG13_8192x32_c4_1P_BITKIT_CORNER +XCORNER<0> VDD_CORE VSS VDD_CORE VSS / ++ RM_IHPSG13_8192x32_c4_1P_BITKIT_CORNER +XTAP_BORDER VDD_CORE VSS VDD_CORE VSS / ++ RM_IHPSG13_8192x32_c4_1P_BITKIT_TAP_LR +.ENDS +.SUBCKT RM_IHPSG13_8192x32_c4_1P_DEC03 ADDR<1> ADDR<0> CS CS_OUT VDD VSS +XDECINV net1 CS_OUT VDD VSS / RSC_IHPSG13_INVX4 +XI0 VDD VSS / RSC_IHPSG13_FILLCAP4 +XDEC ADDR<1> ADDR<0> CS net1 VDD VSS / RSC_IHPSG13_NAND3X2 +.ENDS +.SUBCKT RM_IHPSG13_8192x32_c4_1P_DEC02 ADDR<1> ADDR<0> CS CS_OUT VDD VSS +XDECINV net1 CS_OUT VDD VSS / RSC_IHPSG13_INVX4 +XDEC ADDR<1> NADDR<0> CS net1 VDD VSS / RSC_IHPSG13_NAND3X2 +XI2 VDD VSS / RSC_IHPSG13_FILLCAP4 +XADDRINV ADDR<0> NADDR<0> VDD VSS / RSC_IHPSG13_INVX2 +.ENDS +.SUBCKT RM_IHPSG13_8192x32_c4_1P_ROWDEC8 ADDR_N_I<7> ADDR_N_I<6> ADDR_N_I<5> ADDR_N_I<4> ++ ADDR_N_I<3> ADDR_N_I<2> ADDR_N_I<1> ADDR_N_I<0> CS_I ECLK_I WL_O<255> ++ WL_O<254> WL_O<253> WL_O<252> WL_O<251> WL_O<250> WL_O<249> WL_O<248> ++ WL_O<247> WL_O<246> WL_O<245> WL_O<244> WL_O<243> WL_O<242> WL_O<241> ++ WL_O<240> WL_O<239> WL_O<238> WL_O<237> WL_O<236> WL_O<235> WL_O<234> ++ WL_O<233> WL_O<232> WL_O<231> WL_O<230> WL_O<229> WL_O<228> WL_O<227> ++ WL_O<226> WL_O<225> WL_O<224> WL_O<223> WL_O<222> WL_O<221> WL_O<220> ++ WL_O<219> WL_O<218> WL_O<217> WL_O<216> WL_O<215> WL_O<214> WL_O<213> ++ WL_O<212> WL_O<211> WL_O<210> WL_O<209> WL_O<208> WL_O<207> WL_O<206> ++ WL_O<205> WL_O<204> WL_O<203> WL_O<202> WL_O<201> WL_O<200> WL_O<199> ++ WL_O<198> WL_O<197> WL_O<196> WL_O<195> WL_O<194> WL_O<193> WL_O<192> ++ WL_O<191> WL_O<190> WL_O<189> WL_O<188> WL_O<187> WL_O<186> WL_O<185> ++ WL_O<184> WL_O<183> WL_O<182> WL_O<181> WL_O<180> WL_O<179> WL_O<178> ++ WL_O<177> WL_O<176> WL_O<175> WL_O<174> WL_O<173> WL_O<172> WL_O<171> ++ WL_O<170> WL_O<169> WL_O<168> WL_O<167> WL_O<166> WL_O<165> WL_O<164> ++ WL_O<163> WL_O<162> WL_O<161> WL_O<160> WL_O<159> WL_O<158> WL_O<157> ++ WL_O<156> WL_O<155> WL_O<154> WL_O<153> WL_O<152> WL_O<151> WL_O<150> ++ WL_O<149> WL_O<148> WL_O<147> WL_O<146> WL_O<145> WL_O<144> WL_O<143> ++ WL_O<142> WL_O<141> WL_O<140> WL_O<139> WL_O<138> WL_O<137> WL_O<136> ++ WL_O<135> WL_O<134> WL_O<133> WL_O<132> WL_O<131> WL_O<130> WL_O<129> ++ WL_O<128> WL_O<127> WL_O<126> WL_O<125> WL_O<124> WL_O<123> WL_O<122> ++ WL_O<121> WL_O<120> WL_O<119> WL_O<118> WL_O<117> WL_O<116> WL_O<115> ++ WL_O<114> WL_O<113> WL_O<112> WL_O<111> WL_O<110> WL_O<109> WL_O<108> ++ WL_O<107> WL_O<106> WL_O<105> WL_O<104> WL_O<103> WL_O<102> WL_O<101> ++ WL_O<100> WL_O<99> WL_O<98> WL_O<97> WL_O<96> WL_O<95> WL_O<94> WL_O<93> ++ WL_O<92> WL_O<91> WL_O<90> WL_O<89> WL_O<88> WL_O<87> WL_O<86> WL_O<85> ++ WL_O<84> WL_O<83> WL_O<82> WL_O<81> WL_O<80> WL_O<79> WL_O<78> WL_O<77> ++ WL_O<76> WL_O<75> WL_O<74> WL_O<73> WL_O<72> WL_O<71> WL_O<70> WL_O<69> ++ WL_O<68> WL_O<67> WL_O<66> WL_O<65> WL_O<64> WL_O<63> WL_O<62> WL_O<61> ++ WL_O<60> WL_O<59> WL_O<58> WL_O<57> WL_O<56> WL_O<55> WL_O<54> WL_O<53> ++ WL_O<52> WL_O<51> WL_O<50> WL_O<49> WL_O<48> WL_O<47> WL_O<46> WL_O<45> ++ WL_O<44> WL_O<43> WL_O<42> WL_O<41> WL_O<40> WL_O<39> WL_O<38> WL_O<37> ++ WL_O<36> WL_O<35> WL_O<34> WL_O<33> WL_O<32> WL_O<31> WL_O<30> WL_O<29> ++ WL_O<28> WL_O<27> WL_O<26> WL_O<25> WL_O<24> WL_O<23> WL_O<22> WL_O<21> ++ WL_O<20> WL_O<19> WL_O<18> WL_O<17> WL_O<16> WL_O<15> WL_O<14> WL_O<13> ++ WL_O<12> WL_O<11> WL_O<10> WL_O<9> WL_O<8> WL_O<7> WL_O<6> WL_O<5> WL_O<4> ++ WL_O<3> WL_O<2> WL_O<1> WL_O<0> VDD VSS +XDEC11<4> ADDR_N_I<7> ADDR_N_I<6> CS_I CS04<3> VDD VSS / ++ RM_IHPSG13_8192x32_c4_1P_DEC03 +XDEC11<3> ADDR_N_I<5> ADDR_N_I<4> CS04<3> CS00<15> VDD VSS / ++ RM_IHPSG13_8192x32_c4_1P_DEC03 +XDEC11<2> ADDR_N_I<5> ADDR_N_I<4> CS04<2> CS00<11> VDD VSS / ++ RM_IHPSG13_8192x32_c4_1P_DEC03 +XDEC11<1> ADDR_N_I<5> ADDR_N_I<4> CS04<1> CS00<7> VDD VSS / ++ RM_IHPSG13_8192x32_c4_1P_DEC03 +XDEC11<0> ADDR_N_I<5> ADDR_N_I<4> CS04<0> CS00<3> VDD VSS / ++ RM_IHPSG13_8192x32_c4_1P_DEC03 +XL2<88> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<87> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<86> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<85> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<84> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<83> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<82> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<81> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<80> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<79> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<78> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<77> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<76> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<75> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<74> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<73> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<72> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<71> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<70> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<69> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<68> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<67> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<66> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<65> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<64> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<63> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<62> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<61> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<60> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<59> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<58> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<57> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<56> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<55> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<54> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<53> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<52> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<51> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<50> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<49> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<48> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<47> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<46> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<45> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<44> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<43> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<42> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<41> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<40> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<39> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<38> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<37> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<36> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<35> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<34> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<33> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<32> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<31> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<30> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<29> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<28> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<27> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<26> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<25> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<24> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<23> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<22> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<21> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<20> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<19> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<18> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<17> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<16> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<15> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<14> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<13> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<12> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<11> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<10> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<9> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<8> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<7> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<6> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<5> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<4> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<3> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<2> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<1> VDD VSS / RSC_IHPSG13_FILLCAP8 +XDEC10<4> ADDR_N_I<7> ADDR_N_I<6> CS_I CS04<2> VDD VSS / ++ RM_IHPSG13_8192x32_c4_1P_DEC02 +XDEC10<3> ADDR_N_I<5> ADDR_N_I<4> CS04<3> CS00<14> VDD VSS / ++ RM_IHPSG13_8192x32_c4_1P_DEC02 +XDEC10<2> ADDR_N_I<5> ADDR_N_I<4> CS04<2> CS00<10> VDD VSS / ++ RM_IHPSG13_8192x32_c4_1P_DEC02 +XDEC10<1> ADDR_N_I<5> ADDR_N_I<4> CS04<1> CS00<6> VDD VSS / ++ RM_IHPSG13_8192x32_c4_1P_DEC02 +XDEC10<0> ADDR_N_I<5> ADDR_N_I<4> CS04<0> CS00<2> VDD VSS / ++ RM_IHPSG13_8192x32_c4_1P_DEC02 +XDEC00<4> ADDR_N_I<7> ADDR_N_I<6> CS_I CS04<0> VDD VSS / ++ RM_IHPSG13_8192x32_c4_1P_DEC00 +XDEC00<3> ADDR_N_I<5> ADDR_N_I<4> CS04<3> CS00<12> VDD VSS / ++ RM_IHPSG13_8192x32_c4_1P_DEC00 +XDEC00<2> ADDR_N_I<5> ADDR_N_I<4> CS04<2> CS00<8> VDD VSS / ++ RM_IHPSG13_8192x32_c4_1P_DEC00 +XDEC00<1> ADDR_N_I<5> ADDR_N_I<4> CS04<1> CS00<4> VDD VSS / ++ RM_IHPSG13_8192x32_c4_1P_DEC00 +XDEC00<0> ADDR_N_I<5> ADDR_N_I<4> CS04<0> CS00<0> VDD VSS / ++ RM_IHPSG13_8192x32_c4_1P_DEC00 +XSEL<15> ADDR_N_I<3> ADDR_N_I<2> ADDR_N_I<1> ADDR_N_I<0> CS00<15> ECLK_H<15> ++ ECLK_H<16> ECLK_B<15> ECLK_B<16> WL_O<255> WL_O<254> WL_O<253> WL_O<252> ++ WL_O<251> WL_O<250> WL_O<249> WL_O<248> WL_O<247> WL_O<246> WL_O<245> ++ WL_O<244> WL_O<243> WL_O<242> WL_O<241> WL_O<240> VDD VSS / ++ RM_IHPSG13_8192x32_c4_1P_DEC04 +XSEL<14> ADDR_N_I<3> ADDR_N_I<2> ADDR_N_I<1> ADDR_N_I<0> CS00<14> ECLK_H<14> ++ ECLK_H<15> ECLK_B<14> ECLK_B<15> WL_O<239> WL_O<238> WL_O<237> WL_O<236> ++ WL_O<235> WL_O<234> WL_O<233> WL_O<232> WL_O<231> WL_O<230> WL_O<229> ++ WL_O<228> WL_O<227> WL_O<226> WL_O<225> WL_O<224> VDD VSS / ++ RM_IHPSG13_8192x32_c4_1P_DEC04 +XSEL<13> ADDR_N_I<3> ADDR_N_I<2> ADDR_N_I<1> ADDR_N_I<0> CS00<13> ECLK_H<13> ++ ECLK_H<14> ECLK_B<13> ECLK_B<14> WL_O<223> WL_O<222> WL_O<221> WL_O<220> ++ WL_O<219> WL_O<218> WL_O<217> WL_O<216> WL_O<215> WL_O<214> WL_O<213> ++ WL_O<212> WL_O<211> WL_O<210> WL_O<209> WL_O<208> VDD VSS / ++ RM_IHPSG13_8192x32_c4_1P_DEC04 +XSEL<12> ADDR_N_I<3> ADDR_N_I<2> ADDR_N_I<1> ADDR_N_I<0> CS00<12> ECLK_H<12> ++ ECLK_H<13> ECLK_B<12> ECLK_B<13> WL_O<207> WL_O<206> WL_O<205> WL_O<204> ++ WL_O<203> WL_O<202> WL_O<201> WL_O<200> WL_O<199> WL_O<198> WL_O<197> ++ WL_O<196> WL_O<195> WL_O<194> WL_O<193> WL_O<192> VDD VSS / ++ RM_IHPSG13_8192x32_c4_1P_DEC04 +XSEL<11> ADDR_N_I<3> ADDR_N_I<2> ADDR_N_I<1> ADDR_N_I<0> CS00<11> ECLK_H<11> ++ ECLK_H<12> ECLK_B<11> ECLK_B<12> WL_O<191> WL_O<190> WL_O<189> WL_O<188> ++ WL_O<187> WL_O<186> WL_O<185> WL_O<184> WL_O<183> WL_O<182> WL_O<181> ++ WL_O<180> WL_O<179> WL_O<178> WL_O<177> WL_O<176> VDD VSS / ++ RM_IHPSG13_8192x32_c4_1P_DEC04 +XSEL<10> ADDR_N_I<3> ADDR_N_I<2> ADDR_N_I<1> ADDR_N_I<0> CS00<10> ECLK_H<10> ++ ECLK_H<11> ECLK_B<10> ECLK_B<11> WL_O<175> WL_O<174> WL_O<173> WL_O<172> ++ WL_O<171> WL_O<170> WL_O<169> WL_O<168> WL_O<167> WL_O<166> WL_O<165> ++ WL_O<164> WL_O<163> WL_O<162> WL_O<161> WL_O<160> VDD VSS / ++ RM_IHPSG13_8192x32_c4_1P_DEC04 +XSEL<9> ADDR_N_I<3> ADDR_N_I<2> ADDR_N_I<1> ADDR_N_I<0> CS00<9> ECLK_H<9> ++ ECLK_H<10> ECLK_B<9> ECLK_B<10> WL_O<159> WL_O<158> WL_O<157> WL_O<156> ++ WL_O<155> WL_O<154> WL_O<153> WL_O<152> WL_O<151> WL_O<150> WL_O<149> ++ WL_O<148> WL_O<147> WL_O<146> WL_O<145> WL_O<144> VDD VSS / ++ RM_IHPSG13_8192x32_c4_1P_DEC04 +XSEL<8> ADDR_N_I<3> ADDR_N_I<2> ADDR_N_I<1> ADDR_N_I<0> CS00<8> ECLK_H<8> ++ ECLK_H<9> ECLK_B<8> ECLK_B<9> WL_O<143> WL_O<142> WL_O<141> WL_O<140> ++ WL_O<139> WL_O<138> WL_O<137> WL_O<136> WL_O<135> WL_O<134> WL_O<133> ++ WL_O<132> WL_O<131> WL_O<130> WL_O<129> WL_O<128> VDD VSS / ++ RM_IHPSG13_8192x32_c4_1P_DEC04 +XSEL<7> ADDR_N_I<3> ADDR_N_I<2> ADDR_N_I<1> ADDR_N_I<0> CS00<7> ECLK_H<7> ++ ECLK_H<8> ECLK_B<7> ECLK_B<8> WL_O<127> WL_O<126> WL_O<125> WL_O<124> ++ WL_O<123> WL_O<122> WL_O<121> WL_O<120> WL_O<119> WL_O<118> WL_O<117> ++ WL_O<116> WL_O<115> WL_O<114> WL_O<113> WL_O<112> VDD VSS / ++ RM_IHPSG13_8192x32_c4_1P_DEC04 +XSEL<6> ADDR_N_I<3> ADDR_N_I<2> ADDR_N_I<1> ADDR_N_I<0> CS00<6> ECLK_H<6> ++ ECLK_H<7> ECLK_B<6> ECLK_B<7> WL_O<111> WL_O<110> WL_O<109> WL_O<108> ++ WL_O<107> WL_O<106> WL_O<105> WL_O<104> WL_O<103> WL_O<102> WL_O<101> ++ WL_O<100> WL_O<99> WL_O<98> WL_O<97> WL_O<96> VDD VSS / ++ RM_IHPSG13_8192x32_c4_1P_DEC04 +XSEL<5> ADDR_N_I<3> ADDR_N_I<2> ADDR_N_I<1> ADDR_N_I<0> CS00<5> ECLK_H<5> ++ ECLK_H<6> ECLK_B<5> ECLK_B<6> WL_O<95> WL_O<94> WL_O<93> WL_O<92> WL_O<91> ++ WL_O<90> WL_O<89> WL_O<88> WL_O<87> WL_O<86> WL_O<85> WL_O<84> WL_O<83> ++ WL_O<82> WL_O<81> WL_O<80> VDD VSS / RM_IHPSG13_8192x32_c4_1P_DEC04 +XSEL<4> ADDR_N_I<3> ADDR_N_I<2> ADDR_N_I<1> ADDR_N_I<0> CS00<4> ECLK_H<4> ++ ECLK_H<5> ECLK_B<4> ECLK_B<5> WL_O<79> WL_O<78> WL_O<77> WL_O<76> WL_O<75> ++ WL_O<74> WL_O<73> WL_O<72> WL_O<71> WL_O<70> WL_O<69> WL_O<68> WL_O<67> ++ WL_O<66> WL_O<65> WL_O<64> VDD VSS / RM_IHPSG13_8192x32_c4_1P_DEC04 +XSEL<3> ADDR_N_I<3> ADDR_N_I<2> ADDR_N_I<1> ADDR_N_I<0> CS00<3> ECLK_H<3> ++ ECLK_H<4> ECLK_B<3> ECLK_B<4> WL_O<63> WL_O<62> WL_O<61> WL_O<60> WL_O<59> ++ WL_O<58> WL_O<57> WL_O<56> WL_O<55> WL_O<54> WL_O<53> WL_O<52> WL_O<51> ++ WL_O<50> WL_O<49> WL_O<48> VDD VSS / RM_IHPSG13_8192x32_c4_1P_DEC04 +XSEL<2> ADDR_N_I<3> ADDR_N_I<2> ADDR_N_I<1> ADDR_N_I<0> CS00<2> ECLK_H<2> ++ ECLK_H<3> ECLK_B<2> ECLK_B<3> WL_O<47> WL_O<46> WL_O<45> WL_O<44> WL_O<43> ++ WL_O<42> WL_O<41> WL_O<40> WL_O<39> WL_O<38> WL_O<37> WL_O<36> WL_O<35> ++ WL_O<34> WL_O<33> WL_O<32> VDD VSS / RM_IHPSG13_8192x32_c4_1P_DEC04 +XSEL<1> ADDR_N_I<3> ADDR_N_I<2> ADDR_N_I<1> ADDR_N_I<0> CS00<1> ECLK_H<1> ++ ECLK_H<2> ECLK_B<1> ECLK_B<2> WL_O<31> WL_O<30> WL_O<29> WL_O<28> WL_O<27> ++ WL_O<26> WL_O<25> WL_O<24> WL_O<23> WL_O<22> WL_O<21> WL_O<20> WL_O<19> ++ WL_O<18> WL_O<17> WL_O<16> VDD VSS / RM_IHPSG13_8192x32_c4_1P_DEC04 +XSEL<0> ADDR_N_I<3> ADDR_N_I<2> ADDR_N_I<1> ADDR_N_I<0> CS00<0> ECLK_I ++ ECLK_H<1> ECLK_B<0> ECLK_B<1> WL_O<15> WL_O<14> WL_O<13> WL_O<12> WL_O<11> ++ WL_O<10> WL_O<9> WL_O<8> WL_O<7> WL_O<6> WL_O<5> WL_O<4> WL_O<3> WL_O<2> ++ WL_O<1> WL_O<0> VDD VSS / RM_IHPSG13_8192x32_c4_1P_DEC04 +XDEC01<4> ADDR_N_I<7> ADDR_N_I<6> CS_I CS04<1> VDD VSS / ++ RM_IHPSG13_8192x32_c4_1P_DEC01 +XDEC01<3> ADDR_N_I<5> ADDR_N_I<4> CS04<3> CS00<13> VDD VSS / ++ RM_IHPSG13_8192x32_c4_1P_DEC01 +XDEC01<2> ADDR_N_I<5> ADDR_N_I<4> CS04<2> CS00<9> VDD VSS / ++ RM_IHPSG13_8192x32_c4_1P_DEC01 +XDEC01<1> ADDR_N_I<5> ADDR_N_I<4> CS04<1> CS00<5> VDD VSS / ++ RM_IHPSG13_8192x32_c4_1P_DEC01 +XDEC01<0> ADDR_N_I<5> ADDR_N_I<4> CS04<0> CS00<1> VDD VSS / ++ RM_IHPSG13_8192x32_c4_1P_DEC01 +.ENDS +.SUBCKT RM_IHPSG13_8192x32_c4_1P_ROWREG8 ACLK_N_I ADDR_I<7> ADDR_I<6> ADDR_I<5> ADDR_I<4> ++ ADDR_I<3> ADDR_I<2> ADDR_I<1> ADDR_I<0> ADDR_N_O<7> ADDR_N_O<6> ADDR_N_O<5> ++ ADDR_N_O<4> ADDR_N_O<3> ADDR_N_O<2> ADDR_N_O<1> ADDR_N_O<0> BIST_ADDR_I<7> ++ BIST_ADDR_I<6> BIST_ADDR_I<5> BIST_ADDR_I<4> BIST_ADDR_I<3> BIST_ADDR_I<2> ++ BIST_ADDR_I<1> BIST_ADDR_I<0> BIST_EN_I VDD VSS +XINV<7> q_int<7> qn_int<7> VDD VSS / RSC_IHPSG13_CINVX2 +XINV<6> q_int<6> qn_int<6> VDD VSS / RSC_IHPSG13_CINVX2 +XINV<5> q_int<5> qn_int<5> VDD VSS / RSC_IHPSG13_CINVX2 +XINV<4> q_int<4> qn_int<4> VDD VSS / RSC_IHPSG13_CINVX2 +XINV<3> q_int<3> qn_int<3> VDD VSS / RSC_IHPSG13_CINVX2 +XINV<2> q_int<2> qn_int<2> VDD VSS / RSC_IHPSG13_CINVX2 +XINV<1> q_int<1> qn_int<1> VDD VSS / RSC_IHPSG13_CINVX2 +XINV<0> q_int<0> qn_int<0> VDD VSS / RSC_IHPSG13_CINVX2 +XDRV<7> qn_int<7> ADDR_N_O<7> VDD VSS / RSC_IHPSG13_CINVX8 +XDRV<6> qn_int<6> ADDR_N_O<6> VDD VSS / RSC_IHPSG13_CINVX8 +XDRV<5> qn_int<5> ADDR_N_O<5> VDD VSS / RSC_IHPSG13_CINVX8 +XDRV<4> qn_int<4> ADDR_N_O<4> VDD VSS / RSC_IHPSG13_CINVX8 +XDRV<3> qn_int<3> ADDR_N_O<3> VDD VSS / RSC_IHPSG13_CINVX8 +XDRV<2> qn_int<2> ADDR_N_O<2> VDD VSS / RSC_IHPSG13_CINVX8 +XDRV<1> qn_int<1> ADDR_N_O<1> VDD VSS / RSC_IHPSG13_CINVX8 +XDRV<0> qn_int<0> ADDR_N_O<0> VDD VSS / RSC_IHPSG13_CINVX8 +XDFF<7> BIST_EN_I BIST_ADDR_I<7> ACLK_N_I ADDR_I<7> q_int<7> net2<0> VDD ++ VSS / RSC_IHPSG13_DFNQMX2IX1 +XDFF<6> BIST_EN_I BIST_ADDR_I<6> ACLK_N_I ADDR_I<6> q_int<6> net2<1> VDD ++ VSS / RSC_IHPSG13_DFNQMX2IX1 +XDFF<5> BIST_EN_I BIST_ADDR_I<5> ACLK_N_I ADDR_I<5> q_int<5> net2<2> VDD ++ VSS / RSC_IHPSG13_DFNQMX2IX1 +XDFF<4> BIST_EN_I BIST_ADDR_I<4> ACLK_N_I ADDR_I<4> q_int<4> net2<3> VDD ++ VSS / RSC_IHPSG13_DFNQMX2IX1 +XDFF<3> BIST_EN_I BIST_ADDR_I<3> ACLK_N_I ADDR_I<3> q_int<3> net2<4> VDD ++ VSS / RSC_IHPSG13_DFNQMX2IX1 +XDFF<2> BIST_EN_I BIST_ADDR_I<2> ACLK_N_I ADDR_I<2> q_int<2> net2<5> VDD ++ VSS / RSC_IHPSG13_DFNQMX2IX1 +XDFF<1> BIST_EN_I BIST_ADDR_I<1> ACLK_N_I ADDR_I<1> q_int<1> net2<6> VDD ++ VSS / RSC_IHPSG13_DFNQMX2IX1 +XDFF<0> BIST_EN_I BIST_ADDR_I<0> ACLK_N_I ADDR_I<0> q_int<0> net2<7> VDD ++ VSS / RSC_IHPSG13_DFNQMX2IX1 +XI11<4> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI11<3> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI11<2> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI11<1> VDD VSS / RSC_IHPSG13_FILLCAP8 +.ENDS + +.SUBCKT RM_IHPSG13_8192x32_c4_1P_ROWDEC9 ADDR_N_I<8> ADDR_N_I<7> ADDR_N_I<6> ADDR_N_I<5> ++ ADDR_N_I<4> ADDR_N_I<3> ADDR_N_I<2> ADDR_N_I<1> ADDR_N_I<0> CS_I ECLK_I ++ WL_O<511> WL_O<510> WL_O<509> WL_O<508> WL_O<507> WL_O<506> WL_O<505> ++ WL_O<504> WL_O<503> WL_O<502> WL_O<501> WL_O<500> WL_O<499> WL_O<498> ++ WL_O<497> WL_O<496> WL_O<495> WL_O<494> WL_O<493> WL_O<492> WL_O<491> ++ WL_O<490> WL_O<489> WL_O<488> WL_O<487> WL_O<486> WL_O<485> WL_O<484> ++ WL_O<483> WL_O<482> WL_O<481> WL_O<480> WL_O<479> WL_O<478> WL_O<477> ++ WL_O<476> WL_O<475> WL_O<474> WL_O<473> WL_O<472> WL_O<471> WL_O<470> ++ WL_O<469> WL_O<468> WL_O<467> WL_O<466> WL_O<465> WL_O<464> WL_O<463> ++ WL_O<462> WL_O<461> WL_O<460> WL_O<459> WL_O<458> WL_O<457> WL_O<456> ++ WL_O<455> WL_O<454> WL_O<453> WL_O<452> WL_O<451> WL_O<450> WL_O<449> ++ WL_O<448> WL_O<447> WL_O<446> WL_O<445> WL_O<444> WL_O<443> WL_O<442> ++ WL_O<441> WL_O<440> WL_O<439> WL_O<438> WL_O<437> WL_O<436> WL_O<435> ++ WL_O<434> WL_O<433> WL_O<432> WL_O<431> WL_O<430> WL_O<429> WL_O<428> ++ WL_O<427> WL_O<426> WL_O<425> WL_O<424> WL_O<423> WL_O<422> WL_O<421> ++ WL_O<420> WL_O<419> WL_O<418> WL_O<417> WL_O<416> WL_O<415> WL_O<414> ++ WL_O<413> WL_O<412> WL_O<411> WL_O<410> WL_O<409> WL_O<408> WL_O<407> ++ WL_O<406> WL_O<405> WL_O<404> WL_O<403> WL_O<402> WL_O<401> WL_O<400> ++ WL_O<399> WL_O<398> WL_O<397> WL_O<396> WL_O<395> WL_O<394> WL_O<393> ++ WL_O<392> WL_O<391> WL_O<390> WL_O<389> WL_O<388> WL_O<387> WL_O<386> ++ WL_O<385> WL_O<384> WL_O<383> WL_O<382> WL_O<381> WL_O<380> WL_O<379> ++ WL_O<378> WL_O<377> WL_O<376> WL_O<375> WL_O<374> WL_O<373> WL_O<372> ++ WL_O<371> WL_O<370> WL_O<369> WL_O<368> WL_O<367> WL_O<366> WL_O<365> ++ WL_O<364> WL_O<363> WL_O<362> WL_O<361> WL_O<360> WL_O<359> WL_O<358> ++ WL_O<357> WL_O<356> WL_O<355> WL_O<354> WL_O<353> WL_O<352> WL_O<351> ++ WL_O<350> WL_O<349> WL_O<348> WL_O<347> WL_O<346> WL_O<345> WL_O<344> ++ WL_O<343> WL_O<342> WL_O<341> WL_O<340> WL_O<339> WL_O<338> WL_O<337> ++ WL_O<336> WL_O<335> WL_O<334> WL_O<333> WL_O<332> WL_O<331> WL_O<330> ++ WL_O<329> WL_O<328> WL_O<327> WL_O<326> WL_O<325> WL_O<324> WL_O<323> ++ WL_O<322> WL_O<321> WL_O<320> WL_O<319> WL_O<318> WL_O<317> WL_O<316> ++ WL_O<315> WL_O<314> WL_O<313> WL_O<312> WL_O<311> WL_O<310> WL_O<309> ++ WL_O<308> WL_O<307> WL_O<306> WL_O<305> WL_O<304> WL_O<303> WL_O<302> ++ WL_O<301> WL_O<300> WL_O<299> WL_O<298> WL_O<297> WL_O<296> WL_O<295> ++ WL_O<294> WL_O<293> WL_O<292> WL_O<291> WL_O<290> WL_O<289> WL_O<288> ++ WL_O<287> WL_O<286> WL_O<285> WL_O<284> WL_O<283> WL_O<282> WL_O<281> ++ WL_O<280> WL_O<279> WL_O<278> WL_O<277> WL_O<276> WL_O<275> WL_O<274> ++ WL_O<273> WL_O<272> WL_O<271> WL_O<270> WL_O<269> WL_O<268> WL_O<267> ++ WL_O<266> WL_O<265> WL_O<264> WL_O<263> WL_O<262> WL_O<261> WL_O<260> ++ WL_O<259> WL_O<258> WL_O<257> WL_O<256> WL_O<255> WL_O<254> WL_O<253> ++ WL_O<252> WL_O<251> WL_O<250> WL_O<249> WL_O<248> WL_O<247> WL_O<246> ++ WL_O<245> WL_O<244> WL_O<243> WL_O<242> WL_O<241> WL_O<240> WL_O<239> ++ WL_O<238> WL_O<237> WL_O<236> WL_O<235> WL_O<234> WL_O<233> WL_O<232> ++ WL_O<231> WL_O<230> WL_O<229> WL_O<228> WL_O<227> WL_O<226> WL_O<225> ++ WL_O<224> WL_O<223> WL_O<222> WL_O<221> WL_O<220> WL_O<219> WL_O<218> ++ WL_O<217> WL_O<216> WL_O<215> WL_O<214> WL_O<213> WL_O<212> WL_O<211> ++ WL_O<210> WL_O<209> WL_O<208> WL_O<207> WL_O<206> WL_O<205> WL_O<204> ++ WL_O<203> WL_O<202> WL_O<201> WL_O<200> WL_O<199> WL_O<198> WL_O<197> ++ WL_O<196> WL_O<195> WL_O<194> WL_O<193> WL_O<192> WL_O<191> WL_O<190> ++ WL_O<189> WL_O<188> WL_O<187> WL_O<186> WL_O<185> WL_O<184> WL_O<183> ++ WL_O<182> WL_O<181> WL_O<180> WL_O<179> WL_O<178> WL_O<177> WL_O<176> ++ WL_O<175> WL_O<174> WL_O<173> WL_O<172> WL_O<171> WL_O<170> WL_O<169> ++ WL_O<168> WL_O<167> WL_O<166> WL_O<165> WL_O<164> WL_O<163> WL_O<162> ++ WL_O<161> WL_O<160> WL_O<159> WL_O<158> WL_O<157> WL_O<156> WL_O<155> ++ WL_O<154> WL_O<153> WL_O<152> WL_O<151> WL_O<150> WL_O<149> WL_O<148> ++ WL_O<147> WL_O<146> WL_O<145> WL_O<144> WL_O<143> WL_O<142> WL_O<141> ++ WL_O<140> WL_O<139> WL_O<138> WL_O<137> WL_O<136> WL_O<135> WL_O<134> ++ WL_O<133> WL_O<132> WL_O<131> WL_O<130> WL_O<129> WL_O<128> WL_O<127> ++ WL_O<126> WL_O<125> WL_O<124> WL_O<123> WL_O<122> WL_O<121> WL_O<120> ++ WL_O<119> WL_O<118> WL_O<117> WL_O<116> WL_O<115> WL_O<114> WL_O<113> ++ WL_O<112> WL_O<111> WL_O<110> WL_O<109> WL_O<108> WL_O<107> WL_O<106> ++ WL_O<105> WL_O<104> WL_O<103> WL_O<102> WL_O<101> WL_O<100> WL_O<99> ++ WL_O<98> WL_O<97> WL_O<96> WL_O<95> WL_O<94> WL_O<93> WL_O<92> WL_O<91> ++ WL_O<90> WL_O<89> WL_O<88> WL_O<87> WL_O<86> WL_O<85> WL_O<84> WL_O<83> ++ WL_O<82> WL_O<81> WL_O<80> WL_O<79> WL_O<78> WL_O<77> WL_O<76> WL_O<75> ++ WL_O<74> WL_O<73> WL_O<72> WL_O<71> WL_O<70> WL_O<69> WL_O<68> WL_O<67> ++ WL_O<66> WL_O<65> WL_O<64> WL_O<63> WL_O<62> WL_O<61> WL_O<60> WL_O<59> ++ WL_O<58> WL_O<57> WL_O<56> WL_O<55> WL_O<54> WL_O<53> WL_O<52> WL_O<51> ++ WL_O<50> WL_O<49> WL_O<48> WL_O<47> WL_O<46> WL_O<45> WL_O<44> WL_O<43> ++ WL_O<42> WL_O<41> WL_O<40> WL_O<39> WL_O<38> WL_O<37> WL_O<36> WL_O<35> ++ WL_O<34> WL_O<33> WL_O<32> WL_O<31> WL_O<30> WL_O<29> WL_O<28> WL_O<27> ++ WL_O<26> WL_O<25> WL_O<24> WL_O<23> WL_O<22> WL_O<21> WL_O<20> WL_O<19> ++ WL_O<18> WL_O<17> WL_O<16> WL_O<15> WL_O<14> WL_O<13> WL_O<12> WL_O<11> ++ WL_O<10> WL_O<9> WL_O<8> WL_O<7> WL_O<6> WL_O<5> WL_O<4> WL_O<3> WL_O<2> ++ WL_O<1> WL_O<0> VDD VSS +XL2<172> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<171> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<170> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<169> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<168> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<167> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<166> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<165> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<164> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<163> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<162> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<161> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<160> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<159> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<158> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<157> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<156> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<155> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<154> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<153> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<152> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<151> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<150> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<149> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<148> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<147> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<146> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<145> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<144> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<143> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<142> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<141> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<140> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<139> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<138> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<137> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<136> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<135> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<134> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<133> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<132> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<131> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<130> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<129> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<128> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<127> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<126> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<125> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<124> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<123> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<122> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<121> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<120> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<119> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<118> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<117> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<116> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<115> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<114> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<113> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<112> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<111> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<110> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<109> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<108> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<107> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<106> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<105> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<104> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<103> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<102> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<101> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<100> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<99> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<98> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<97> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<96> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<95> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<94> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<93> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<92> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<91> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<90> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<89> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<88> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<87> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<86> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<85> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<84> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<83> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<82> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<81> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<80> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<79> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<78> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<77> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<76> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<75> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<74> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<73> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<72> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<71> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<70> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<69> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<68> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<67> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<66> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<65> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<64> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<63> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<62> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<61> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<60> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<59> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<58> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<57> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<56> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<55> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<54> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<53> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<52> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<51> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<50> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<49> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<48> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<47> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<46> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<45> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<44> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<43> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<42> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<41> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<40> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<39> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<38> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<37> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<36> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<35> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<34> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<33> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<32> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<31> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<30> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<29> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<28> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<27> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<26> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<25> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<24> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<23> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<22> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<21> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<20> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<19> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<18> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<17> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<16> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<15> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<14> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<13> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<12> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<11> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<10> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<9> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<8> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<7> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<6> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<5> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<4> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<3> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<2> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<1> VDD VSS / RSC_IHPSG13_FILLCAP8 +XDEC11<9> ADDR_N_I<7> ADDR_N_I<6> CS04<1> CS02<7> VDD VSS / ++ RM_IHPSG13_8192x32_c4_1P_DEC03 +XDEC11<8> ADDR_N_I<7> ADDR_N_I<6> CS04<0> CS02<3> VDD VSS / ++ RM_IHPSG13_8192x32_c4_1P_DEC03 +XDEC11<7> ADDR_N_I<5> ADDR_N_I<4> CS02<7> CS00<31> VDD VSS / ++ RM_IHPSG13_8192x32_c4_1P_DEC03 +XDEC11<6> ADDR_N_I<5> ADDR_N_I<4> CS02<6> CS00<27> VDD VSS / ++ RM_IHPSG13_8192x32_c4_1P_DEC03 +XDEC11<5> ADDR_N_I<5> ADDR_N_I<4> CS02<5> CS00<23> VDD VSS / ++ RM_IHPSG13_8192x32_c4_1P_DEC03 +XDEC11<4> ADDR_N_I<5> ADDR_N_I<4> CS02<4> CS00<19> VDD VSS / ++ RM_IHPSG13_8192x32_c4_1P_DEC03 +XDEC11<3> ADDR_N_I<5> ADDR_N_I<4> CS02<3> CS00<15> VDD VSS / ++ RM_IHPSG13_8192x32_c4_1P_DEC03 +XDEC11<2> ADDR_N_I<5> ADDR_N_I<4> CS02<2> CS00<11> VDD VSS / ++ RM_IHPSG13_8192x32_c4_1P_DEC03 +XDEC11<1> ADDR_N_I<5> ADDR_N_I<4> CS02<1> CS00<7> VDD VSS / ++ RM_IHPSG13_8192x32_c4_1P_DEC03 +XDEC11<0> ADDR_N_I<5> ADDR_N_I<4> CS02<0> CS00<3> VDD VSS / ++ RM_IHPSG13_8192x32_c4_1P_DEC03 +XDEC00<10> ADDR_N_I<9> ADDR_N_I<8> CS_I CS04<0> VDD VSS / ++ RM_IHPSG13_8192x32_c4_1P_DEC00 +XDEC00<9> ADDR_N_I<7> ADDR_N_I<6> CS04<1> CS02<4> VDD VSS / ++ RM_IHPSG13_8192x32_c4_1P_DEC00 +XDEC00<8> ADDR_N_I<7> ADDR_N_I<6> CS04<0> CS02<0> VDD VSS / ++ RM_IHPSG13_8192x32_c4_1P_DEC00 +XDEC00<7> ADDR_N_I<5> ADDR_N_I<4> CS02<7> CS00<28> VDD VSS / ++ RM_IHPSG13_8192x32_c4_1P_DEC00 +XDEC00<6> ADDR_N_I<5> ADDR_N_I<4> CS02<6> CS00<24> VDD VSS / ++ RM_IHPSG13_8192x32_c4_1P_DEC00 +XDEC00<5> ADDR_N_I<5> ADDR_N_I<4> CS02<5> CS00<20> VDD VSS / ++ RM_IHPSG13_8192x32_c4_1P_DEC00 +XDEC00<4> ADDR_N_I<5> ADDR_N_I<4> CS02<4> CS00<16> VDD VSS / ++ RM_IHPSG13_8192x32_c4_1P_DEC00 +XDEC00<3> ADDR_N_I<5> ADDR_N_I<4> CS02<3> CS00<12> VDD VSS / ++ RM_IHPSG13_8192x32_c4_1P_DEC00 +XDEC00<2> ADDR_N_I<5> ADDR_N_I<4> CS02<2> CS00<8> VDD VSS / ++ RM_IHPSG13_8192x32_c4_1P_DEC00 +XDEC00<1> ADDR_N_I<5> ADDR_N_I<4> CS02<1> CS00<4> VDD VSS / ++ RM_IHPSG13_8192x32_c4_1P_DEC00 +XDEC00<0> ADDR_N_I<5> ADDR_N_I<4> CS02<0> CS00<0> VDD VSS / ++ RM_IHPSG13_8192x32_c4_1P_DEC00 +XSEL<31> ADDR_N_I<3> ADDR_N_I<2> ADDR_N_I<1> ADDR_N_I<0> CS00<31> ECLK_H<31> ++ ECLK_H<32> ECLK_B<31> ECLK_B<32> WL_O<511> WL_O<510> WL_O<509> WL_O<508> ++ WL_O<507> WL_O<506> WL_O<505> WL_O<504> WL_O<503> WL_O<502> WL_O<501> ++ WL_O<500> WL_O<499> WL_O<498> WL_O<497> WL_O<496> VDD VSS / ++ RM_IHPSG13_8192x32_c4_1P_DEC04 +XSEL<30> ADDR_N_I<3> ADDR_N_I<2> ADDR_N_I<1> ADDR_N_I<0> CS00<30> ECLK_H<30> ++ ECLK_H<31> ECLK_B<30> ECLK_B<31> WL_O<495> WL_O<494> WL_O<493> WL_O<492> ++ WL_O<491> WL_O<490> WL_O<489> WL_O<488> WL_O<487> WL_O<486> WL_O<485> ++ WL_O<484> WL_O<483> WL_O<482> WL_O<481> WL_O<480> VDD VSS / ++ RM_IHPSG13_8192x32_c4_1P_DEC04 +XSEL<29> ADDR_N_I<3> ADDR_N_I<2> ADDR_N_I<1> ADDR_N_I<0> CS00<29> ECLK_H<29> ++ ECLK_H<30> ECLK_B<29> ECLK_B<30> WL_O<479> WL_O<478> WL_O<477> WL_O<476> ++ WL_O<475> WL_O<474> WL_O<473> WL_O<472> WL_O<471> WL_O<470> WL_O<469> ++ WL_O<468> WL_O<467> WL_O<466> WL_O<465> WL_O<464> VDD VSS / ++ RM_IHPSG13_8192x32_c4_1P_DEC04 +XSEL<28> ADDR_N_I<3> ADDR_N_I<2> ADDR_N_I<1> ADDR_N_I<0> CS00<28> ECLK_H<28> ++ ECLK_H<29> ECLK_B<28> ECLK_B<29> WL_O<463> WL_O<462> WL_O<461> WL_O<460> ++ WL_O<459> WL_O<458> WL_O<457> WL_O<456> WL_O<455> WL_O<454> WL_O<453> ++ WL_O<452> WL_O<451> WL_O<450> WL_O<449> WL_O<448> VDD VSS / ++ RM_IHPSG13_8192x32_c4_1P_DEC04 +XSEL<27> ADDR_N_I<3> ADDR_N_I<2> ADDR_N_I<1> ADDR_N_I<0> CS00<27> ECLK_H<27> ++ ECLK_H<28> ECLK_B<27> ECLK_B<28> WL_O<447> WL_O<446> WL_O<445> WL_O<444> ++ WL_O<443> WL_O<442> WL_O<441> WL_O<440> WL_O<439> WL_O<438> WL_O<437> ++ WL_O<436> WL_O<435> WL_O<434> WL_O<433> WL_O<432> VDD VSS / ++ RM_IHPSG13_8192x32_c4_1P_DEC04 +XSEL<26> ADDR_N_I<3> ADDR_N_I<2> ADDR_N_I<1> ADDR_N_I<0> CS00<26> ECLK_H<26> ++ ECLK_H<27> ECLK_B<26> ECLK_B<27> WL_O<431> WL_O<430> WL_O<429> WL_O<428> ++ WL_O<427> WL_O<426> WL_O<425> WL_O<424> WL_O<423> WL_O<422> WL_O<421> ++ WL_O<420> WL_O<419> WL_O<418> WL_O<417> WL_O<416> VDD VSS / ++ RM_IHPSG13_8192x32_c4_1P_DEC04 +XSEL<25> ADDR_N_I<3> ADDR_N_I<2> ADDR_N_I<1> ADDR_N_I<0> CS00<25> ECLK_H<25> ++ ECLK_H<26> ECLK_B<25> ECLK_B<26> WL_O<415> WL_O<414> WL_O<413> WL_O<412> ++ WL_O<411> WL_O<410> WL_O<409> WL_O<408> WL_O<407> WL_O<406> WL_O<405> ++ WL_O<404> WL_O<403> WL_O<402> WL_O<401> WL_O<400> VDD VSS / ++ RM_IHPSG13_8192x32_c4_1P_DEC04 +XSEL<24> ADDR_N_I<3> ADDR_N_I<2> ADDR_N_I<1> ADDR_N_I<0> CS00<24> ECLK_H<24> ++ ECLK_H<25> ECLK_B<24> ECLK_B<25> WL_O<399> WL_O<398> WL_O<397> WL_O<396> ++ WL_O<395> WL_O<394> WL_O<393> WL_O<392> WL_O<391> WL_O<390> WL_O<389> ++ WL_O<388> WL_O<387> WL_O<386> WL_O<385> WL_O<384> VDD VSS / ++ RM_IHPSG13_8192x32_c4_1P_DEC04 +XSEL<23> ADDR_N_I<3> ADDR_N_I<2> ADDR_N_I<1> ADDR_N_I<0> CS00<23> ECLK_H<23> ++ ECLK_H<24> ECLK_B<23> ECLK_B<24> WL_O<383> WL_O<382> WL_O<381> WL_O<380> ++ WL_O<379> WL_O<378> WL_O<377> WL_O<376> WL_O<375> WL_O<374> WL_O<373> ++ WL_O<372> WL_O<371> WL_O<370> WL_O<369> WL_O<368> VDD VSS / ++ RM_IHPSG13_8192x32_c4_1P_DEC04 +XSEL<22> ADDR_N_I<3> ADDR_N_I<2> ADDR_N_I<1> ADDR_N_I<0> CS00<22> ECLK_H<22> ++ ECLK_H<23> ECLK_B<22> ECLK_B<23> WL_O<367> WL_O<366> WL_O<365> WL_O<364> ++ WL_O<363> WL_O<362> WL_O<361> WL_O<360> WL_O<359> WL_O<358> WL_O<357> ++ WL_O<356> WL_O<355> WL_O<354> WL_O<353> WL_O<352> VDD VSS / ++ RM_IHPSG13_8192x32_c4_1P_DEC04 +XSEL<21> ADDR_N_I<3> ADDR_N_I<2> ADDR_N_I<1> ADDR_N_I<0> CS00<21> ECLK_H<21> ++ ECLK_H<22> ECLK_B<21> ECLK_B<22> WL_O<351> WL_O<350> WL_O<349> WL_O<348> ++ WL_O<347> WL_O<346> WL_O<345> WL_O<344> WL_O<343> WL_O<342> WL_O<341> ++ WL_O<340> WL_O<339> WL_O<338> WL_O<337> WL_O<336> VDD VSS / ++ RM_IHPSG13_8192x32_c4_1P_DEC04 +XSEL<20> ADDR_N_I<3> ADDR_N_I<2> ADDR_N_I<1> ADDR_N_I<0> CS00<20> ECLK_H<20> ++ ECLK_H<21> ECLK_B<20> ECLK_B<21> WL_O<335> WL_O<334> WL_O<333> WL_O<332> ++ WL_O<331> WL_O<330> WL_O<329> WL_O<328> WL_O<327> WL_O<326> WL_O<325> ++ WL_O<324> WL_O<323> WL_O<322> WL_O<321> WL_O<320> VDD VSS / ++ RM_IHPSG13_8192x32_c4_1P_DEC04 +XSEL<19> ADDR_N_I<3> ADDR_N_I<2> ADDR_N_I<1> ADDR_N_I<0> CS00<19> ECLK_H<19> ++ ECLK_H<20> ECLK_B<19> ECLK_B<20> WL_O<319> WL_O<318> WL_O<317> WL_O<316> ++ WL_O<315> WL_O<314> WL_O<313> WL_O<312> WL_O<311> WL_O<310> WL_O<309> ++ WL_O<308> WL_O<307> WL_O<306> WL_O<305> WL_O<304> VDD VSS / ++ RM_IHPSG13_8192x32_c4_1P_DEC04 +XSEL<18> ADDR_N_I<3> ADDR_N_I<2> ADDR_N_I<1> ADDR_N_I<0> CS00<18> ECLK_H<18> ++ ECLK_H<19> ECLK_B<18> ECLK_B<19> WL_O<303> WL_O<302> WL_O<301> WL_O<300> ++ WL_O<299> WL_O<298> WL_O<297> WL_O<296> WL_O<295> WL_O<294> WL_O<293> ++ WL_O<292> WL_O<291> WL_O<290> WL_O<289> WL_O<288> VDD VSS / ++ RM_IHPSG13_8192x32_c4_1P_DEC04 +XSEL<17> ADDR_N_I<3> ADDR_N_I<2> ADDR_N_I<1> ADDR_N_I<0> CS00<17> ECLK_H<17> ++ ECLK_H<18> ECLK_B<17> ECLK_B<18> WL_O<287> WL_O<286> WL_O<285> WL_O<284> ++ WL_O<283> WL_O<282> WL_O<281> WL_O<280> WL_O<279> WL_O<278> WL_O<277> ++ WL_O<276> WL_O<275> WL_O<274> WL_O<273> WL_O<272> VDD VSS / ++ RM_IHPSG13_8192x32_c4_1P_DEC04 +XSEL<16> ADDR_N_I<3> ADDR_N_I<2> ADDR_N_I<1> ADDR_N_I<0> CS00<16> ECLK_H<16> ++ ECLK_H<17> ECLK_B<16> ECLK_B<17> WL_O<271> WL_O<270> WL_O<269> WL_O<268> ++ WL_O<267> WL_O<266> WL_O<265> WL_O<264> WL_O<263> WL_O<262> WL_O<261> ++ WL_O<260> WL_O<259> WL_O<258> WL_O<257> WL_O<256> VDD VSS / ++ RM_IHPSG13_8192x32_c4_1P_DEC04 +XSEL<15> ADDR_N_I<3> ADDR_N_I<2> ADDR_N_I<1> ADDR_N_I<0> CS00<15> ECLK_H<15> ++ ECLK_H<16> ECLK_B<15> ECLK_B<16> WL_O<255> WL_O<254> WL_O<253> WL_O<252> ++ WL_O<251> WL_O<250> WL_O<249> WL_O<248> WL_O<247> WL_O<246> WL_O<245> ++ WL_O<244> WL_O<243> WL_O<242> WL_O<241> WL_O<240> VDD VSS / ++ RM_IHPSG13_8192x32_c4_1P_DEC04 +XSEL<14> ADDR_N_I<3> ADDR_N_I<2> ADDR_N_I<1> ADDR_N_I<0> CS00<14> ECLK_H<14> ++ ECLK_H<15> ECLK_B<14> ECLK_B<15> WL_O<239> WL_O<238> WL_O<237> WL_O<236> ++ WL_O<235> WL_O<234> WL_O<233> WL_O<232> WL_O<231> WL_O<230> WL_O<229> ++ WL_O<228> WL_O<227> WL_O<226> WL_O<225> WL_O<224> VDD VSS / ++ RM_IHPSG13_8192x32_c4_1P_DEC04 +XSEL<13> ADDR_N_I<3> ADDR_N_I<2> ADDR_N_I<1> ADDR_N_I<0> CS00<13> ECLK_H<13> ++ ECLK_H<14> ECLK_B<13> ECLK_B<14> WL_O<223> WL_O<222> WL_O<221> WL_O<220> ++ WL_O<219> WL_O<218> WL_O<217> WL_O<216> WL_O<215> WL_O<214> WL_O<213> ++ WL_O<212> WL_O<211> WL_O<210> WL_O<209> WL_O<208> VDD VSS / ++ RM_IHPSG13_8192x32_c4_1P_DEC04 +XSEL<12> ADDR_N_I<3> ADDR_N_I<2> ADDR_N_I<1> ADDR_N_I<0> CS00<12> ECLK_H<12> ++ ECLK_H<13> ECLK_B<12> ECLK_B<13> WL_O<207> WL_O<206> WL_O<205> WL_O<204> ++ WL_O<203> WL_O<202> WL_O<201> WL_O<200> WL_O<199> WL_O<198> WL_O<197> ++ WL_O<196> WL_O<195> WL_O<194> WL_O<193> WL_O<192> VDD VSS / ++ RM_IHPSG13_8192x32_c4_1P_DEC04 +XSEL<11> ADDR_N_I<3> ADDR_N_I<2> ADDR_N_I<1> ADDR_N_I<0> CS00<11> ECLK_H<11> ++ ECLK_H<12> ECLK_B<11> ECLK_B<12> WL_O<191> WL_O<190> WL_O<189> WL_O<188> ++ WL_O<187> WL_O<186> WL_O<185> WL_O<184> WL_O<183> WL_O<182> WL_O<181> ++ WL_O<180> WL_O<179> WL_O<178> WL_O<177> WL_O<176> VDD VSS / ++ RM_IHPSG13_8192x32_c4_1P_DEC04 +XSEL<10> ADDR_N_I<3> ADDR_N_I<2> ADDR_N_I<1> ADDR_N_I<0> CS00<10> ECLK_H<10> ++ ECLK_H<11> ECLK_B<10> ECLK_B<11> WL_O<175> WL_O<174> WL_O<173> WL_O<172> ++ WL_O<171> WL_O<170> WL_O<169> WL_O<168> WL_O<167> WL_O<166> WL_O<165> ++ WL_O<164> WL_O<163> WL_O<162> WL_O<161> WL_O<160> VDD VSS / ++ RM_IHPSG13_8192x32_c4_1P_DEC04 +XSEL<9> ADDR_N_I<3> ADDR_N_I<2> ADDR_N_I<1> ADDR_N_I<0> CS00<9> ECLK_H<9> ++ ECLK_H<10> ECLK_B<9> ECLK_B<10> WL_O<159> WL_O<158> WL_O<157> WL_O<156> ++ WL_O<155> WL_O<154> WL_O<153> WL_O<152> WL_O<151> WL_O<150> WL_O<149> ++ WL_O<148> WL_O<147> WL_O<146> WL_O<145> WL_O<144> VDD VSS / ++ RM_IHPSG13_8192x32_c4_1P_DEC04 +XSEL<8> ADDR_N_I<3> ADDR_N_I<2> ADDR_N_I<1> ADDR_N_I<0> CS00<8> ECLK_H<8> ++ ECLK_H<9> ECLK_B<8> ECLK_B<9> WL_O<143> WL_O<142> WL_O<141> WL_O<140> ++ WL_O<139> WL_O<138> WL_O<137> WL_O<136> WL_O<135> WL_O<134> WL_O<133> ++ WL_O<132> WL_O<131> WL_O<130> WL_O<129> WL_O<128> VDD VSS / ++ RM_IHPSG13_8192x32_c4_1P_DEC04 +XSEL<7> ADDR_N_I<3> ADDR_N_I<2> ADDR_N_I<1> ADDR_N_I<0> CS00<7> ECLK_H<7> ++ ECLK_H<8> ECLK_B<7> ECLK_B<8> WL_O<127> WL_O<126> WL_O<125> WL_O<124> ++ WL_O<123> WL_O<122> WL_O<121> WL_O<120> WL_O<119> WL_O<118> WL_O<117> ++ WL_O<116> WL_O<115> WL_O<114> WL_O<113> WL_O<112> VDD VSS / ++ RM_IHPSG13_8192x32_c4_1P_DEC04 +XSEL<6> ADDR_N_I<3> ADDR_N_I<2> ADDR_N_I<1> ADDR_N_I<0> CS00<6> ECLK_H<6> ++ ECLK_H<7> ECLK_B<6> ECLK_B<7> WL_O<111> WL_O<110> WL_O<109> WL_O<108> ++ WL_O<107> WL_O<106> WL_O<105> WL_O<104> WL_O<103> WL_O<102> WL_O<101> ++ WL_O<100> WL_O<99> WL_O<98> WL_O<97> WL_O<96> VDD VSS / ++ RM_IHPSG13_8192x32_c4_1P_DEC04 +XSEL<5> ADDR_N_I<3> ADDR_N_I<2> ADDR_N_I<1> ADDR_N_I<0> CS00<5> ECLK_H<5> ++ ECLK_H<6> ECLK_B<5> ECLK_B<6> WL_O<95> WL_O<94> WL_O<93> WL_O<92> WL_O<91> ++ WL_O<90> WL_O<89> WL_O<88> WL_O<87> WL_O<86> WL_O<85> WL_O<84> WL_O<83> ++ WL_O<82> WL_O<81> WL_O<80> VDD VSS / RM_IHPSG13_8192x32_c4_1P_DEC04 +XSEL<4> ADDR_N_I<3> ADDR_N_I<2> ADDR_N_I<1> ADDR_N_I<0> CS00<4> ECLK_H<4> ++ ECLK_H<5> ECLK_B<4> ECLK_B<5> WL_O<79> WL_O<78> WL_O<77> WL_O<76> WL_O<75> ++ WL_O<74> WL_O<73> WL_O<72> WL_O<71> WL_O<70> WL_O<69> WL_O<68> WL_O<67> ++ WL_O<66> WL_O<65> WL_O<64> VDD VSS / RM_IHPSG13_8192x32_c4_1P_DEC04 +XSEL<3> ADDR_N_I<3> ADDR_N_I<2> ADDR_N_I<1> ADDR_N_I<0> CS00<3> ECLK_H<3> ++ ECLK_H<4> ECLK_B<3> ECLK_B<4> WL_O<63> WL_O<62> WL_O<61> WL_O<60> WL_O<59> ++ WL_O<58> WL_O<57> WL_O<56> WL_O<55> WL_O<54> WL_O<53> WL_O<52> WL_O<51> ++ WL_O<50> WL_O<49> WL_O<48> VDD VSS / RM_IHPSG13_8192x32_c4_1P_DEC04 +XSEL<2> ADDR_N_I<3> ADDR_N_I<2> ADDR_N_I<1> ADDR_N_I<0> CS00<2> ECLK_H<2> ++ ECLK_H<3> ECLK_B<2> ECLK_B<3> WL_O<47> WL_O<46> WL_O<45> WL_O<44> WL_O<43> ++ WL_O<42> WL_O<41> WL_O<40> WL_O<39> WL_O<38> WL_O<37> WL_O<36> WL_O<35> ++ WL_O<34> WL_O<33> WL_O<32> VDD VSS / RM_IHPSG13_8192x32_c4_1P_DEC04 +XSEL<1> ADDR_N_I<3> ADDR_N_I<2> ADDR_N_I<1> ADDR_N_I<0> CS00<1> ECLK_H<1> ++ ECLK_H<2> ECLK_B<1> ECLK_B<2> WL_O<31> WL_O<30> WL_O<29> WL_O<28> WL_O<27> ++ WL_O<26> WL_O<25> WL_O<24> WL_O<23> WL_O<22> WL_O<21> WL_O<20> WL_O<19> ++ WL_O<18> WL_O<17> WL_O<16> VDD VSS / RM_IHPSG13_8192x32_c4_1P_DEC04 +XSEL<0> ADDR_N_I<3> ADDR_N_I<2> ADDR_N_I<1> ADDR_N_I<0> CS00<0> ECLK_I ++ ECLK_H<1> ECLK_B<0> ECLK_B<1> WL_O<15> WL_O<14> WL_O<13> WL_O<12> WL_O<11> ++ WL_O<10> WL_O<9> WL_O<8> WL_O<7> WL_O<6> WL_O<5> WL_O<4> WL_O<3> WL_O<2> ++ WL_O<1> WL_O<0> VDD VSS / RM_IHPSG13_8192x32_c4_1P_DEC04 +XDEC01<10> ADDR_N_I<9> ADDR_N_I<8> CS_I CS04<1> VDD VSS / ++ RM_IHPSG13_8192x32_c4_1P_DEC01 +XDEC01<9> ADDR_N_I<7> ADDR_N_I<6> CS04<1> CS02<5> VDD VSS / ++ RM_IHPSG13_8192x32_c4_1P_DEC01 +XDEC01<8> ADDR_N_I<7> ADDR_N_I<6> CS04<0> CS02<1> VDD VSS / ++ RM_IHPSG13_8192x32_c4_1P_DEC01 +XDEC01<7> ADDR_N_I<5> ADDR_N_I<4> CS02<7> CS00<29> VDD VSS / ++ RM_IHPSG13_8192x32_c4_1P_DEC01 +XDEC01<6> ADDR_N_I<5> ADDR_N_I<4> CS02<6> CS00<25> VDD VSS / ++ RM_IHPSG13_8192x32_c4_1P_DEC01 +XDEC01<5> ADDR_N_I<5> ADDR_N_I<4> CS02<5> CS00<21> VDD VSS / ++ RM_IHPSG13_8192x32_c4_1P_DEC01 +XDEC01<4> ADDR_N_I<5> ADDR_N_I<4> CS02<4> CS00<17> VDD VSS / ++ RM_IHPSG13_8192x32_c4_1P_DEC01 +XDEC01<3> ADDR_N_I<5> ADDR_N_I<4> CS02<3> CS00<13> VDD VSS / ++ RM_IHPSG13_8192x32_c4_1P_DEC01 +XDEC01<2> ADDR_N_I<5> ADDR_N_I<4> CS02<2> CS00<9> VDD VSS / ++ RM_IHPSG13_8192x32_c4_1P_DEC01 +XDEC01<1> ADDR_N_I<5> ADDR_N_I<4> CS02<1> CS00<5> VDD VSS / ++ RM_IHPSG13_8192x32_c4_1P_DEC01 +XDEC01<0> ADDR_N_I<5> ADDR_N_I<4> CS02<0> CS00<1> VDD VSS / ++ RM_IHPSG13_8192x32_c4_1P_DEC01 +XDEC10<9> ADDR_N_I<7> ADDR_N_I<6> CS04<1> CS02<6> VDD VSS / ++ RM_IHPSG13_8192x32_c4_1P_DEC02 +XDEC10<8> ADDR_N_I<7> ADDR_N_I<6> CS04<0> CS02<2> VDD VSS / ++ RM_IHPSG13_8192x32_c4_1P_DEC02 +XDEC10<7> ADDR_N_I<5> ADDR_N_I<4> CS02<7> CS00<30> VDD VSS / ++ RM_IHPSG13_8192x32_c4_1P_DEC02 +XDEC10<6> ADDR_N_I<5> ADDR_N_I<4> CS02<6> CS00<26> VDD VSS / ++ RM_IHPSG13_8192x32_c4_1P_DEC02 +XDEC10<5> ADDR_N_I<5> ADDR_N_I<4> CS02<5> CS00<22> VDD VSS / ++ RM_IHPSG13_8192x32_c4_1P_DEC02 +XDEC10<4> ADDR_N_I<5> ADDR_N_I<4> CS02<4> CS00<18> VDD VSS / ++ RM_IHPSG13_8192x32_c4_1P_DEC02 +XDEC10<3> ADDR_N_I<5> ADDR_N_I<4> CS02<3> CS00<14> VDD VSS / ++ RM_IHPSG13_8192x32_c4_1P_DEC02 +XDEC10<2> ADDR_N_I<5> ADDR_N_I<4> CS02<2> CS00<10> VDD VSS / ++ RM_IHPSG13_8192x32_c4_1P_DEC02 +XDEC10<1> ADDR_N_I<5> ADDR_N_I<4> CS02<1> CS00<6> VDD VSS / ++ RM_IHPSG13_8192x32_c4_1P_DEC02 +XDEC10<0> ADDR_N_I<5> ADDR_N_I<4> CS02<0> CS00<2> VDD VSS / ++ RM_IHPSG13_8192x32_c4_1P_DEC02 +XI0 ADDR_N_I<9> VDD VSS / RSC_IHPSG13_TIEL +.ENDS +.SUBCKT RM_IHPSG13_8192x32_c4_1P_ROWREG9 ACLK_N_I ADDR_I<8> ADDR_I<7> ADDR_I<6> ADDR_I<5> ++ ADDR_I<4> ADDR_I<3> ADDR_I<2> ADDR_I<1> ADDR_I<0> ADDR_N_O<8> ADDR_N_O<7> ++ ADDR_N_O<6> ADDR_N_O<5> ADDR_N_O<4> ADDR_N_O<3> ADDR_N_O<2> ADDR_N_O<1> ++ ADDR_N_O<0> BIST_ADDR_I<8> BIST_ADDR_I<7> BIST_ADDR_I<6> BIST_ADDR_I<5> ++ BIST_ADDR_I<4> BIST_ADDR_I<3> BIST_ADDR_I<2> BIST_ADDR_I<1> BIST_ADDR_I<0> ++ BIST_EN_I VDD VSS +XINV<8> q_int<8> qn_int<8> VDD VSS / RSC_IHPSG13_CINVX2 +XINV<7> q_int<7> qn_int<7> VDD VSS / RSC_IHPSG13_CINVX2 +XINV<6> q_int<6> qn_int<6> VDD VSS / RSC_IHPSG13_CINVX2 +XINV<5> q_int<5> qn_int<5> VDD VSS / RSC_IHPSG13_CINVX2 +XINV<4> q_int<4> qn_int<4> VDD VSS / RSC_IHPSG13_CINVX2 +XINV<3> q_int<3> qn_int<3> VDD VSS / RSC_IHPSG13_CINVX2 +XINV<2> q_int<2> qn_int<2> VDD VSS / RSC_IHPSG13_CINVX2 +XINV<1> q_int<1> qn_int<1> VDD VSS / RSC_IHPSG13_CINVX2 +XINV<0> q_int<0> qn_int<0> VDD VSS / RSC_IHPSG13_CINVX2 +XDRV<8> qn_int<8> ADDR_N_O<8> VDD VSS / RSC_IHPSG13_CINVX8 +XDRV<7> qn_int<7> ADDR_N_O<7> VDD VSS / RSC_IHPSG13_CINVX8 +XDRV<6> qn_int<6> ADDR_N_O<6> VDD VSS / RSC_IHPSG13_CINVX8 +XDRV<5> qn_int<5> ADDR_N_O<5> VDD VSS / RSC_IHPSG13_CINVX8 +XDRV<4> qn_int<4> ADDR_N_O<4> VDD VSS / RSC_IHPSG13_CINVX8 +XDRV<3> qn_int<3> ADDR_N_O<3> VDD VSS / RSC_IHPSG13_CINVX8 +XDRV<2> qn_int<2> ADDR_N_O<2> VDD VSS / RSC_IHPSG13_CINVX8 +XDRV<1> qn_int<1> ADDR_N_O<1> VDD VSS / RSC_IHPSG13_CINVX8 +XDRV<0> qn_int<0> ADDR_N_O<0> VDD VSS / RSC_IHPSG13_CINVX8 +XDFF<8> BIST_EN_I BIST_ADDR_I<8> ACLK_N_I ADDR_I<8> q_int<8> net04<0> VDD ++ VSS / RSC_IHPSG13_DFNQMX2IX1 +XDFF<7> BIST_EN_I BIST_ADDR_I<7> ACLK_N_I ADDR_I<7> q_int<7> net04<1> VDD ++ VSS / RSC_IHPSG13_DFNQMX2IX1 +XDFF<6> BIST_EN_I BIST_ADDR_I<6> ACLK_N_I ADDR_I<6> q_int<6> net04<2> VDD ++ VSS / RSC_IHPSG13_DFNQMX2IX1 +XDFF<5> BIST_EN_I BIST_ADDR_I<5> ACLK_N_I ADDR_I<5> q_int<5> net04<3> VDD ++ VSS / RSC_IHPSG13_DFNQMX2IX1 +XDFF<4> BIST_EN_I BIST_ADDR_I<4> ACLK_N_I ADDR_I<4> q_int<4> net04<4> VDD ++ VSS / RSC_IHPSG13_DFNQMX2IX1 +XDFF<3> BIST_EN_I BIST_ADDR_I<3> ACLK_N_I ADDR_I<3> q_int<3> net04<5> VDD ++ VSS / RSC_IHPSG13_DFNQMX2IX1 +XDFF<2> BIST_EN_I BIST_ADDR_I<2> ACLK_N_I ADDR_I<2> q_int<2> net04<6> VDD ++ VSS / RSC_IHPSG13_DFNQMX2IX1 +XDFF<1> BIST_EN_I BIST_ADDR_I<1> ACLK_N_I ADDR_I<1> q_int<1> net04<7> VDD ++ VSS / RSC_IHPSG13_DFNQMX2IX1 +XDFF<0> BIST_EN_I BIST_ADDR_I<0> ACLK_N_I ADDR_I<0> q_int<0> net04<8> VDD ++ VSS / RSC_IHPSG13_DFNQMX2IX1 +.ENDS + +.SUBCKT RM_IHPSG13_8192x32_c4_1P_ROWDEC7 ADDR_N_I<6> ADDR_N_I<5> ADDR_N_I<4> ADDR_N_I<3> ++ ADDR_N_I<2> ADDR_N_I<1> ADDR_N_I<0> CS_I ECLK_I WL_O<127> WL_O<126> ++ WL_O<125> WL_O<124> WL_O<123> WL_O<122> WL_O<121> WL_O<120> WL_O<119> ++ WL_O<118> WL_O<117> WL_O<116> WL_O<115> WL_O<114> WL_O<113> WL_O<112> ++ WL_O<111> WL_O<110> WL_O<109> WL_O<108> WL_O<107> WL_O<106> WL_O<105> ++ WL_O<104> WL_O<103> WL_O<102> WL_O<101> WL_O<100> WL_O<99> WL_O<98> WL_O<97> ++ WL_O<96> WL_O<95> WL_O<94> WL_O<93> WL_O<92> WL_O<91> WL_O<90> WL_O<89> ++ WL_O<88> WL_O<87> WL_O<86> WL_O<85> WL_O<84> WL_O<83> WL_O<82> WL_O<81> ++ WL_O<80> WL_O<79> WL_O<78> WL_O<77> WL_O<76> WL_O<75> WL_O<74> WL_O<73> ++ WL_O<72> WL_O<71> WL_O<70> WL_O<69> WL_O<68> WL_O<67> WL_O<66> WL_O<65> ++ WL_O<64> WL_O<63> WL_O<62> WL_O<61> WL_O<60> WL_O<59> WL_O<58> WL_O<57> ++ WL_O<56> WL_O<55> WL_O<54> WL_O<53> WL_O<52> WL_O<51> WL_O<50> WL_O<49> ++ WL_O<48> WL_O<47> WL_O<46> WL_O<45> WL_O<44> WL_O<43> WL_O<42> WL_O<41> ++ WL_O<40> WL_O<39> WL_O<38> WL_O<37> WL_O<36> WL_O<35> WL_O<34> WL_O<33> ++ WL_O<32> WL_O<31> WL_O<30> WL_O<29> WL_O<28> WL_O<27> WL_O<26> WL_O<25> ++ WL_O<24> WL_O<23> WL_O<22> WL_O<21> WL_O<20> WL_O<19> WL_O<18> WL_O<17> ++ WL_O<16> WL_O<15> WL_O<14> WL_O<13> WL_O<12> WL_O<11> WL_O<10> WL_O<9> ++ WL_O<8> WL_O<7> WL_O<6> WL_O<5> WL_O<4> WL_O<3> WL_O<2> WL_O<1> WL_O<0> ++ VDD VSS +XDEC11<1> ADDR_N_I<5> ADDR_N_I<4> CS04<1> CS00<7> VDD VSS / ++ RM_IHPSG13_8192x32_c4_1P_DEC03 +XDEC11<0> ADDR_N_I<5> ADDR_N_I<4> CS04<0> CS00<3> VDD VSS / ++ RM_IHPSG13_8192x32_c4_1P_DEC03 +XDEC10<1> ADDR_N_I<5> ADDR_N_I<4> CS04<1> CS00<6> VDD VSS / ++ RM_IHPSG13_8192x32_c4_1P_DEC02 +XDEC10<0> ADDR_N_I<5> ADDR_N_I<4> CS04<0> CS00<2> VDD VSS / ++ RM_IHPSG13_8192x32_c4_1P_DEC02 +XSEL<7> ADDR_N_I<3> ADDR_N_I<2> ADDR_N_I<1> ADDR_N_I<0> CS00<7> ECLK_H<7> ++ ECLK_H<8> ECLK_B<7> ECLK_B<8> WL_O<127> WL_O<126> WL_O<125> WL_O<124> ++ WL_O<123> WL_O<122> WL_O<121> WL_O<120> WL_O<119> WL_O<118> WL_O<117> ++ WL_O<116> WL_O<115> WL_O<114> WL_O<113> WL_O<112> VDD VSS / ++ RM_IHPSG13_8192x32_c4_1P_DEC04 +XSEL<6> ADDR_N_I<3> ADDR_N_I<2> ADDR_N_I<1> ADDR_N_I<0> CS00<6> ECLK_H<6> ++ ECLK_H<7> ECLK_B<6> ECLK_B<7> WL_O<111> WL_O<110> WL_O<109> WL_O<108> ++ WL_O<107> WL_O<106> WL_O<105> WL_O<104> WL_O<103> WL_O<102> WL_O<101> ++ WL_O<100> WL_O<99> WL_O<98> WL_O<97> WL_O<96> VDD VSS / ++ RM_IHPSG13_8192x32_c4_1P_DEC04 +XSEL<5> ADDR_N_I<3> ADDR_N_I<2> ADDR_N_I<1> ADDR_N_I<0> CS00<5> ECLK_H<5> ++ ECLK_H<6> ECLK_B<5> ECLK_B<6> WL_O<95> WL_O<94> WL_O<93> WL_O<92> WL_O<91> ++ WL_O<90> WL_O<89> WL_O<88> WL_O<87> WL_O<86> WL_O<85> WL_O<84> WL_O<83> ++ WL_O<82> WL_O<81> WL_O<80> VDD VSS / RM_IHPSG13_8192x32_c4_1P_DEC04 +XSEL<4> ADDR_N_I<3> ADDR_N_I<2> ADDR_N_I<1> ADDR_N_I<0> CS00<4> ECLK_H<4> ++ ECLK_H<5> ECLK_B<4> ECLK_B<5> WL_O<79> WL_O<78> WL_O<77> WL_O<76> WL_O<75> ++ WL_O<74> WL_O<73> WL_O<72> WL_O<71> WL_O<70> WL_O<69> WL_O<68> WL_O<67> ++ WL_O<66> WL_O<65> WL_O<64> VDD VSS / RM_IHPSG13_8192x32_c4_1P_DEC04 +XSEL<3> ADDR_N_I<3> ADDR_N_I<2> ADDR_N_I<1> ADDR_N_I<0> CS00<3> ECLK_H<3> ++ ECLK_H<4> ECLK_B<3> ECLK_B<4> WL_O<63> WL_O<62> WL_O<61> WL_O<60> WL_O<59> ++ WL_O<58> WL_O<57> WL_O<56> WL_O<55> WL_O<54> WL_O<53> WL_O<52> WL_O<51> ++ WL_O<50> WL_O<49> WL_O<48> VDD VSS / RM_IHPSG13_8192x32_c4_1P_DEC04 +XSEL<2> ADDR_N_I<3> ADDR_N_I<2> ADDR_N_I<1> ADDR_N_I<0> CS00<2> ECLK_H<2> ++ ECLK_H<3> ECLK_B<2> ECLK_B<3> WL_O<47> WL_O<46> WL_O<45> WL_O<44> WL_O<43> ++ WL_O<42> WL_O<41> WL_O<40> WL_O<39> WL_O<38> WL_O<37> WL_O<36> WL_O<35> ++ WL_O<34> WL_O<33> WL_O<32> VDD VSS / RM_IHPSG13_8192x32_c4_1P_DEC04 +XSEL<1> ADDR_N_I<3> ADDR_N_I<2> ADDR_N_I<1> ADDR_N_I<0> CS00<1> ECLK_H<1> ++ ECLK_H<2> ECLK_B<1> ECLK_B<2> WL_O<31> WL_O<30> WL_O<29> WL_O<28> WL_O<27> ++ WL_O<26> WL_O<25> WL_O<24> WL_O<23> WL_O<22> WL_O<21> WL_O<20> WL_O<19> ++ WL_O<18> WL_O<17> WL_O<16> VDD VSS / RM_IHPSG13_8192x32_c4_1P_DEC04 +XSEL<0> ADDR_N_I<3> ADDR_N_I<2> ADDR_N_I<1> ADDR_N_I<0> CS00<0> ECLK_I ++ ECLK_H<1> ECLK_B<0> ECLK_B<1> WL_O<15> WL_O<14> WL_O<13> WL_O<12> WL_O<11> ++ WL_O<10> WL_O<9> WL_O<8> WL_O<7> WL_O<6> WL_O<5> WL_O<4> WL_O<3> WL_O<2> ++ WL_O<1> WL_O<0> VDD VSS / RM_IHPSG13_8192x32_c4_1P_DEC04 +XDEC00<2> ADDR_N_I<7> ADDR_N_I<6> CS_I CS04<0> VDD VSS / ++ RM_IHPSG13_8192x32_c4_1P_DEC00 +XDEC00<1> ADDR_N_I<5> ADDR_N_I<4> CS04<1> CS00<4> VDD VSS / ++ RM_IHPSG13_8192x32_c4_1P_DEC00 +XDEC00<0> ADDR_N_I<5> ADDR_N_I<4> CS04<0> CS00<0> VDD VSS / ++ RM_IHPSG13_8192x32_c4_1P_DEC00 +XDEC01<2> ADDR_N_I<7> ADDR_N_I<6> CS_I CS04<1> VDD VSS / ++ RM_IHPSG13_8192x32_c4_1P_DEC01 +XDEC01<1> ADDR_N_I<5> ADDR_N_I<4> CS04<1> CS00<5> VDD VSS / ++ RM_IHPSG13_8192x32_c4_1P_DEC01 +XDEC01<0> ADDR_N_I<5> ADDR_N_I<4> CS04<0> CS00<1> VDD VSS / ++ RM_IHPSG13_8192x32_c4_1P_DEC01 +XL2<44> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<43> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<42> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<41> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<40> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<39> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<38> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<37> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<36> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<35> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<34> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<33> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<32> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<31> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<30> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<29> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<28> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<27> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<26> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<25> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<24> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<23> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<22> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<21> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<20> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<19> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<18> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<17> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<16> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<15> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<14> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<13> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<12> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<11> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<10> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<9> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<8> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<7> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<6> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<5> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<4> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<3> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<2> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<1> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI0 ADDR_N_I<7> VDD VSS / RSC_IHPSG13_TIEL +.ENDS +.SUBCKT RM_IHPSG13_8192x32_c4_1P_ROWREG7 ACLK_N_I ADDR_I<6> ADDR_I<5> ADDR_I<4> ADDR_I<3> ++ ADDR_I<2> ADDR_I<1> ADDR_I<0> ADDR_N_O<6> ADDR_N_O<5> ADDR_N_O<4> ++ ADDR_N_O<3> ADDR_N_O<2> ADDR_N_O<1> ADDR_N_O<0> BIST_ADDR_I<6> ++ BIST_ADDR_I<5> BIST_ADDR_I<4> BIST_ADDR_I<3> BIST_ADDR_I<2> BIST_ADDR_I<1> ++ BIST_ADDR_I<0> BIST_EN_I VDD VSS +XINV<6> q_int<6> qn_int<6> VDD VSS / RSC_IHPSG13_CINVX2 +XINV<5> q_int<5> qn_int<5> VDD VSS / RSC_IHPSG13_CINVX2 +XINV<4> q_int<4> qn_int<4> VDD VSS / RSC_IHPSG13_CINVX2 +XINV<3> q_int<3> qn_int<3> VDD VSS / RSC_IHPSG13_CINVX2 +XINV<2> q_int<2> qn_int<2> VDD VSS / RSC_IHPSG13_CINVX2 +XINV<1> q_int<1> qn_int<1> VDD VSS / RSC_IHPSG13_CINVX2 +XINV<0> q_int<0> qn_int<0> VDD VSS / RSC_IHPSG13_CINVX2 +XDRV<6> qn_int<6> ADDR_N_O<6> VDD VSS / RSC_IHPSG13_CINVX8 +XDRV<5> qn_int<5> ADDR_N_O<5> VDD VSS / RSC_IHPSG13_CINVX8 +XDRV<4> qn_int<4> ADDR_N_O<4> VDD VSS / RSC_IHPSG13_CINVX8 +XDRV<3> qn_int<3> ADDR_N_O<3> VDD VSS / RSC_IHPSG13_CINVX8 +XDRV<2> qn_int<2> ADDR_N_O<2> VDD VSS / RSC_IHPSG13_CINVX8 +XDRV<1> qn_int<1> ADDR_N_O<1> VDD VSS / RSC_IHPSG13_CINVX8 +XDRV<0> qn_int<0> ADDR_N_O<0> VDD VSS / RSC_IHPSG13_CINVX8 +XDFF<6> BIST_EN_I BIST_ADDR_I<6> ACLK_N_I ADDR_I<6> q_int<6> net2<0> VDD ++ VSS / RSC_IHPSG13_DFNQMX2IX1 +XDFF<5> BIST_EN_I BIST_ADDR_I<5> ACLK_N_I ADDR_I<5> q_int<5> net2<1> VDD ++ VSS / RSC_IHPSG13_DFNQMX2IX1 +XDFF<4> BIST_EN_I BIST_ADDR_I<4> ACLK_N_I ADDR_I<4> q_int<4> net2<2> VDD ++ VSS / RSC_IHPSG13_DFNQMX2IX1 +XDFF<3> BIST_EN_I BIST_ADDR_I<3> ACLK_N_I ADDR_I<3> q_int<3> net2<3> VDD ++ VSS / RSC_IHPSG13_DFNQMX2IX1 +XDFF<2> BIST_EN_I BIST_ADDR_I<2> ACLK_N_I ADDR_I<2> q_int<2> net2<4> VDD ++ VSS / RSC_IHPSG13_DFNQMX2IX1 +XDFF<1> BIST_EN_I BIST_ADDR_I<1> ACLK_N_I ADDR_I<1> q_int<1> net2<5> VDD ++ VSS / RSC_IHPSG13_DFNQMX2IX1 +XDFF<0> BIST_EN_I BIST_ADDR_I<0> ACLK_N_I ADDR_I<0> q_int<0> net2<6> VDD ++ VSS / RSC_IHPSG13_DFNQMX2IX1 +XI11<8> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI11<7> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI11<6> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI11<5> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI11<4> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI11<3> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI11<2> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI11<1> VDD VSS / RSC_IHPSG13_FILLCAP8 +.ENDS + +.SUBCKT RM_IHPSG13_8192x32_c4_1P_COLDRV13X8 ADDR_COL_I<1> ADDR_COL_I<0> ADDR_COL_O<1> ++ ADDR_COL_O<0> ADDR_DEC_I<7> ADDR_DEC_I<6> ADDR_DEC_I<5> ADDR_DEC_I<4> ++ ADDR_DEC_I<3> ADDR_DEC_I<2> ADDR_DEC_I<1> ADDR_DEC_I<0> ADDR_DEC_O<7> ++ ADDR_DEC_O<6> ADDR_DEC_O<5> ADDR_DEC_O<4> ADDR_DEC_O<3> ADDR_DEC_O<2> ++ ADDR_DEC_O<1> ADDR_DEC_O<0> DCLK_I DCLK_O RCLK_I RCLK_O WCLK_I WCLK_O ++ VDD VSS +XI0<1> VDD VSS / RSC_IHPSG13_FILLCAP4 +XI0<0> VDD VSS / RSC_IHPSG13_FILLCAP4 +XADDR_COL_DRV<1> ADDR_COL_I<1> ADDR_COL_O<1> VDD VSS / ++ RSC_IHPSG13_CBUFX8 +XADDR_COL_DRV<0> ADDR_COL_I<0> ADDR_COL_O<0> VDD VSS / ++ RSC_IHPSG13_CBUFX8 +XADDR_DEC_DRV<7> ADDR_DEC_I<7> ADDR_DEC_O<7> VDD VSS / ++ RSC_IHPSG13_CBUFX8 +XADDR_DEC_DRV<6> ADDR_DEC_I<6> ADDR_DEC_O<6> VDD VSS / ++ RSC_IHPSG13_CBUFX8 +XADDR_DEC_DRV<5> ADDR_DEC_I<5> ADDR_DEC_O<5> VDD VSS / ++ RSC_IHPSG13_CBUFX8 +XADDR_DEC_DRV<4> ADDR_DEC_I<4> ADDR_DEC_O<4> VDD VSS / ++ RSC_IHPSG13_CBUFX8 +XADDR_DEC_DRV<3> ADDR_DEC_I<3> ADDR_DEC_O<3> VDD VSS / ++ RSC_IHPSG13_CBUFX8 +XADDR_DEC_DRV<2> ADDR_DEC_I<2> ADDR_DEC_O<2> VDD VSS / ++ RSC_IHPSG13_CBUFX8 +XADDR_DEC_DRV<1> ADDR_DEC_I<1> ADDR_DEC_O<1> VDD VSS / ++ RSC_IHPSG13_CBUFX8 +XADDR_DEC_DRV<0> ADDR_DEC_I<0> ADDR_DEC_O<0> VDD VSS / ++ RSC_IHPSG13_CBUFX8 +XDCLK_DRV DCLK_I DCLK_O VDD VSS / RSC_IHPSG13_CBUFX8 +XRCLK_DRV RCLK_I RCLK_O VDD VSS / RSC_IHPSG13_CBUFX8 +XWCLK_DRV WCLK_I WCLK_O VDD VSS / RSC_IHPSG13_CBUFX8 +.ENDS +.SUBCKT RM_IHPSG13_8192x32_c4_1P_WLDRV16X8 A<15> A<14> A<13> A<12> A<11> A<10> A<9> A<8> ++ A<7> A<6> A<5> A<4> A<3> A<2> A<1> A<0> Z<15> Z<14> Z<13> Z<12> Z<11> Z<10> ++ Z<9> Z<8> Z<7> Z<6> Z<5> Z<4> Z<3> Z<2> Z<1> Z<0> VDD VSS +XBUF<15> A<15> Z<15> VDD VSS / RSC_IHPSG13_WLDRVX8 +XBUF<14> A<14> Z<14> VDD VSS / RSC_IHPSG13_WLDRVX8 +XBUF<13> A<13> Z<13> VDD VSS / RSC_IHPSG13_WLDRVX8 +XBUF<12> A<12> Z<12> VDD VSS / RSC_IHPSG13_WLDRVX8 +XBUF<11> A<11> Z<11> VDD VSS / RSC_IHPSG13_WLDRVX8 +XBUF<10> A<10> Z<10> VDD VSS / RSC_IHPSG13_WLDRVX8 +XBUF<9> A<9> Z<9> VDD VSS / RSC_IHPSG13_WLDRVX8 +XBUF<8> A<8> Z<8> VDD VSS / RSC_IHPSG13_WLDRVX8 +XBUF<7> A<7> Z<7> VDD VSS / RSC_IHPSG13_WLDRVX8 +XBUF<6> A<6> Z<6> VDD VSS / RSC_IHPSG13_WLDRVX8 +XBUF<5> A<5> Z<5> VDD VSS / RSC_IHPSG13_WLDRVX8 +XBUF<4> A<4> Z<4> VDD VSS / RSC_IHPSG13_WLDRVX8 +XBUF<3> A<3> Z<3> VDD VSS / RSC_IHPSG13_WLDRVX8 +XBUF<2> A<2> Z<2> VDD VSS / RSC_IHPSG13_WLDRVX8 +XBUF<1> A<1> Z<1> VDD VSS / RSC_IHPSG13_WLDRVX8 +XBUF<0> A<0> Z<0> VDD VSS / RSC_IHPSG13_WLDRVX8 +.ENDS + + + +.SUBCKT RM_IHPSG13_8192x32_c4_1P_ROWDEC6 ADDR_N_I<5> ADDR_N_I<4> ADDR_N_I<3> ADDR_N_I<2> ++ ADDR_N_I<1> ADDR_N_I<0> CS_I ECLK_I WL_O<63> WL_O<62> WL_O<61> WL_O<60> ++ WL_O<59> WL_O<58> WL_O<57> WL_O<56> WL_O<55> WL_O<54> WL_O<53> WL_O<52> ++ WL_O<51> WL_O<50> WL_O<49> WL_O<48> WL_O<47> WL_O<46> WL_O<45> WL_O<44> ++ WL_O<43> WL_O<42> WL_O<41> WL_O<40> WL_O<39> WL_O<38> WL_O<37> WL_O<36> ++ WL_O<35> WL_O<34> WL_O<33> WL_O<32> WL_O<31> WL_O<30> WL_O<29> WL_O<28> ++ WL_O<27> WL_O<26> WL_O<25> WL_O<24> WL_O<23> WL_O<22> WL_O<21> WL_O<20> ++ WL_O<19> WL_O<18> WL_O<17> WL_O<16> WL_O<15> WL_O<14> WL_O<13> WL_O<12> ++ WL_O<11> WL_O<10> WL_O<9> WL_O<8> WL_O<7> WL_O<6> WL_O<5> WL_O<4> WL_O<3> ++ WL_O<2> WL_O<1> WL_O<0> VDD VSS +XDEC11 ADDR_N_I<5> ADDR_N_I<4> CS_I CS00<3> VDD VSS / ++ RM_IHPSG13_8192x32_c4_1P_DEC03 +XDEC00 ADDR_N_I<5> ADDR_N_I<4> CS_I CS00<0> VDD VSS / ++ RM_IHPSG13_8192x32_c4_1P_DEC00 +XDEC01 ADDR_N_I<5> ADDR_N_I<4> CS_I CS00<1> VDD VSS / ++ RM_IHPSG13_8192x32_c4_1P_DEC01 +XDEC10 ADDR_N_I<5> ADDR_N_I<4> CS_I CS00<2> VDD VSS / ++ RM_IHPSG13_8192x32_c4_1P_DEC02 +XSEL<3> ADDR_N_I<3> ADDR_N_I<2> ADDR_N_I<1> ADDR_N_I<0> CS00<3> ECLK_H<3> ++ ECLK_H<4> ECLK_B<3> ECLK_B<4> WL_O<63> WL_O<62> WL_O<61> WL_O<60> WL_O<59> ++ WL_O<58> WL_O<57> WL_O<56> WL_O<55> WL_O<54> WL_O<53> WL_O<52> WL_O<51> ++ WL_O<50> WL_O<49> WL_O<48> VDD VSS / RM_IHPSG13_8192x32_c4_1P_DEC04 +XSEL<2> ADDR_N_I<3> ADDR_N_I<2> ADDR_N_I<1> ADDR_N_I<0> CS00<2> ECLK_H<2> ++ ECLK_H<3> ECLK_B<2> ECLK_B<3> WL_O<47> WL_O<46> WL_O<45> WL_O<44> WL_O<43> ++ WL_O<42> WL_O<41> WL_O<40> WL_O<39> WL_O<38> WL_O<37> WL_O<36> WL_O<35> ++ WL_O<34> WL_O<33> WL_O<32> VDD VSS / RM_IHPSG13_8192x32_c4_1P_DEC04 +XSEL<1> ADDR_N_I<3> ADDR_N_I<2> ADDR_N_I<1> ADDR_N_I<0> CS00<1> ECLK_H<1> ++ ECLK_H<2> ECLK_B<1> ECLK_B<2> WL_O<31> WL_O<30> WL_O<29> WL_O<28> WL_O<27> ++ WL_O<26> WL_O<25> WL_O<24> WL_O<23> WL_O<22> WL_O<21> WL_O<20> WL_O<19> ++ WL_O<18> WL_O<17> WL_O<16> VDD VSS / RM_IHPSG13_8192x32_c4_1P_DEC04 +XSEL<0> ADDR_N_I<3> ADDR_N_I<2> ADDR_N_I<1> ADDR_N_I<0> CS00<0> ECLK_I ++ ECLK_H<1> ECLK_B<0> ECLK_B<1> WL_O<15> WL_O<14> WL_O<13> WL_O<12> WL_O<11> ++ WL_O<10> WL_O<9> WL_O<8> WL_O<7> WL_O<6> WL_O<5> WL_O<4> WL_O<3> WL_O<2> ++ WL_O<1> WL_O<0> VDD VSS / RM_IHPSG13_8192x32_c4_1P_DEC04 +XL2<24> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<23> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<22> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<21> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<20> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<19> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<18> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<17> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<16> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<15> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<14> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<13> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<12> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<11> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<10> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<9> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<8> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<7> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<6> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<5> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<4> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<3> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<2> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<1> VDD VSS / RSC_IHPSG13_FILLCAP8 +.ENDS +.SUBCKT RM_IHPSG13_8192x32_c4_1P_ROWREG6 ACLK_N_I ADDR_I<5> ADDR_I<4> ADDR_I<3> ADDR_I<2> ++ ADDR_I<1> ADDR_I<0> ADDR_N_O<5> ADDR_N_O<4> ADDR_N_O<3> ADDR_N_O<2> ++ ADDR_N_O<1> ADDR_N_O<0> BIST_ADDR_I<5> BIST_ADDR_I<4> BIST_ADDR_I<3> ++ BIST_ADDR_I<2> BIST_ADDR_I<1> BIST_ADDR_I<0> BIST_EN_I VDD VSS +XINV<5> q_int<5> qn_int<5> VDD VSS / RSC_IHPSG13_CINVX2 +XINV<4> q_int<4> qn_int<4> VDD VSS / RSC_IHPSG13_CINVX2 +XINV<3> q_int<3> qn_int<3> VDD VSS / RSC_IHPSG13_CINVX2 +XINV<2> q_int<2> qn_int<2> VDD VSS / RSC_IHPSG13_CINVX2 +XINV<1> q_int<1> qn_int<1> VDD VSS / RSC_IHPSG13_CINVX2 +XINV<0> q_int<0> qn_int<0> VDD VSS / RSC_IHPSG13_CINVX2 +XDRV<5> qn_int<5> ADDR_N_O<5> VDD VSS / RSC_IHPSG13_CINVX8 +XDRV<4> qn_int<4> ADDR_N_O<4> VDD VSS / RSC_IHPSG13_CINVX8 +XDRV<3> qn_int<3> ADDR_N_O<3> VDD VSS / RSC_IHPSG13_CINVX8 +XDRV<2> qn_int<2> ADDR_N_O<2> VDD VSS / RSC_IHPSG13_CINVX8 +XDRV<1> qn_int<1> ADDR_N_O<1> VDD VSS / RSC_IHPSG13_CINVX8 +XDRV<0> qn_int<0> ADDR_N_O<0> VDD VSS / RSC_IHPSG13_CINVX8 +XDFF<5> BIST_EN_I BIST_ADDR_I<5> ACLK_N_I ADDR_I<5> q_int<5> net2<0> VDD ++ VSS / RSC_IHPSG13_DFNQMX2IX1 +XDFF<4> BIST_EN_I BIST_ADDR_I<4> ACLK_N_I ADDR_I<4> q_int<4> net2<1> VDD ++ VSS / RSC_IHPSG13_DFNQMX2IX1 +XDFF<3> BIST_EN_I BIST_ADDR_I<3> ACLK_N_I ADDR_I<3> q_int<3> net2<2> VDD ++ VSS / RSC_IHPSG13_DFNQMX2IX1 +XDFF<2> BIST_EN_I BIST_ADDR_I<2> ACLK_N_I ADDR_I<2> q_int<2> net2<3> VDD ++ VSS / RSC_IHPSG13_DFNQMX2IX1 +XDFF<1> BIST_EN_I BIST_ADDR_I<1> ACLK_N_I ADDR_I<1> q_int<1> net2<4> VDD ++ VSS / RSC_IHPSG13_DFNQMX2IX1 +XDFF<0> BIST_EN_I BIST_ADDR_I<0> ACLK_N_I ADDR_I<0> q_int<0> net2<5> VDD ++ VSS / RSC_IHPSG13_DFNQMX2IX1 +XI11<12> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI11<11> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI11<10> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI11<9> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI11<8> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI11<7> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI11<6> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI11<5> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI11<4> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI11<3> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI11<2> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI11<1> VDD VSS / RSC_IHPSG13_FILLCAP8 +.ENDS + + +.SUBCKT RM_IHPSG13_8192x32_c4_1P_COLUMN_pcell_0 A_BLC_BOT<1> A_BLC_BOT<0> A_BLC_TOP<1> A_BLC_TOP<0> A_BLT_BOT<1> A_BLT_BOT<0> A_BLT_TOP<1> A_BLT_TOP<0> A_LWL<511> A_LWL<510> A_LWL<509> A_LWL<508> A_LWL<507> A_LWL<506> A_LWL<505> A_LWL<504> A_LWL<503> A_LWL<502> A_LWL<501> A_LWL<500> A_LWL<499> A_LWL<498> A_LWL<497> A_LWL<496> A_LWL<495> A_LWL<494> A_LWL<493> A_LWL<492> A_LWL<491> A_LWL<490> A_LWL<489> A_LWL<488> A_LWL<487> A_LWL<486> A_LWL<485> A_LWL<484> A_LWL<483> A_LWL<482> A_LWL<481> A_LWL<480> A_LWL<479> A_LWL<478> A_LWL<477> A_LWL<476> A_LWL<475> A_LWL<474> A_LWL<473> A_LWL<472> A_LWL<471> A_LWL<470> A_LWL<469> A_LWL<468> A_LWL<467> A_LWL<466> A_LWL<465> A_LWL<464> A_LWL<463> A_LWL<462> A_LWL<461> A_LWL<460> A_LWL<459> A_LWL<458> A_LWL<457> A_LWL<456> A_LWL<455> A_LWL<454> A_LWL<453> A_LWL<452> A_LWL<451> A_LWL<450> A_LWL<449> A_LWL<448> A_LWL<447> A_LWL<446> A_LWL<445> A_LWL<444> A_LWL<443> A_LWL<442> A_LWL<441> A_LWL<440> A_LWL<439> A_LWL<438> A_LWL<437> A_LWL<436> A_LWL<435> A_LWL<434> A_LWL<433> A_LWL<432> A_LWL<431> A_LWL<430> A_LWL<429> A_LWL<428> A_LWL<427> A_LWL<426> A_LWL<425> A_LWL<424> A_LWL<423> A_LWL<422> A_LWL<421> A_LWL<420> A_LWL<419> A_LWL<418> A_LWL<417> A_LWL<416> A_LWL<415> A_LWL<414> A_LWL<413> A_LWL<412> A_LWL<411> A_LWL<410> A_LWL<409> A_LWL<408> A_LWL<407> A_LWL<406> A_LWL<405> A_LWL<404> A_LWL<403> A_LWL<402> A_LWL<401> A_LWL<400> A_LWL<399> A_LWL<398> A_LWL<397> A_LWL<396> A_LWL<395> A_LWL<394> A_LWL<393> A_LWL<392> A_LWL<391> A_LWL<390> A_LWL<389> A_LWL<388> A_LWL<387> A_LWL<386> A_LWL<385> A_LWL<384> A_LWL<383> A_LWL<382> A_LWL<381> A_LWL<380> A_LWL<379> A_LWL<378> A_LWL<377> A_LWL<376> A_LWL<375> A_LWL<374> A_LWL<373> A_LWL<372> A_LWL<371> A_LWL<370> A_LWL<369> A_LWL<368> A_LWL<367> A_LWL<366> A_LWL<365> A_LWL<364> A_LWL<363> A_LWL<362> A_LWL<361> A_LWL<360> A_LWL<359> A_LWL<358> A_LWL<357> A_LWL<356> A_LWL<355> A_LWL<354> A_LWL<353> A_LWL<352> A_LWL<351> A_LWL<350> A_LWL<349> A_LWL<348> A_LWL<347> A_LWL<346> A_LWL<345> A_LWL<344> A_LWL<343> A_LWL<342> A_LWL<341> A_LWL<340> A_LWL<339> A_LWL<338> A_LWL<337> A_LWL<336> A_LWL<335> A_LWL<334> A_LWL<333> A_LWL<332> A_LWL<331> A_LWL<330> A_LWL<329> A_LWL<328> A_LWL<327> A_LWL<326> A_LWL<325> A_LWL<324> A_LWL<323> A_LWL<322> A_LWL<321> A_LWL<320> A_LWL<319> A_LWL<318> A_LWL<317> A_LWL<316> A_LWL<315> A_LWL<314> A_LWL<313> A_LWL<312> A_LWL<311> A_LWL<310> A_LWL<309> A_LWL<308> A_LWL<307> A_LWL<306> A_LWL<305> A_LWL<304> A_LWL<303> A_LWL<302> A_LWL<301> A_LWL<300> A_LWL<299> A_LWL<298> A_LWL<297> A_LWL<296> A_LWL<295> A_LWL<294> A_LWL<293> A_LWL<292> A_LWL<291> A_LWL<290> A_LWL<289> A_LWL<288> A_LWL<287> A_LWL<286> A_LWL<285> A_LWL<284> A_LWL<283> A_LWL<282> A_LWL<281> A_LWL<280> A_LWL<279> A_LWL<278> A_LWL<277> A_LWL<276> A_LWL<275> A_LWL<274> A_LWL<273> A_LWL<272> A_LWL<271> A_LWL<270> A_LWL<269> A_LWL<268> A_LWL<267> A_LWL<266> A_LWL<265> A_LWL<264> A_LWL<263> A_LWL<262> A_LWL<261> A_LWL<260> A_LWL<259> A_LWL<258> A_LWL<257> A_LWL<256> A_LWL<255> A_LWL<254> A_LWL<253> A_LWL<252> A_LWL<251> A_LWL<250> A_LWL<249> A_LWL<248> A_LWL<247> A_LWL<246> A_LWL<245> A_LWL<244> A_LWL<243> A_LWL<242> A_LWL<241> A_LWL<240> A_LWL<239> A_LWL<238> A_LWL<237> A_LWL<236> A_LWL<235> A_LWL<234> A_LWL<233> A_LWL<232> A_LWL<231> A_LWL<230> A_LWL<229> A_LWL<228> A_LWL<227> A_LWL<226> A_LWL<225> A_LWL<224> A_LWL<223> A_LWL<222> A_LWL<221> A_LWL<220> A_LWL<219> A_LWL<218> A_LWL<217> A_LWL<216> A_LWL<215> A_LWL<214> A_LWL<213> A_LWL<212> A_LWL<211> A_LWL<210> A_LWL<209> A_LWL<208> A_LWL<207> A_LWL<206> A_LWL<205> A_LWL<204> A_LWL<203> A_LWL<202> A_LWL<201> A_LWL<200> A_LWL<199> A_LWL<198> A_LWL<197> A_LWL<196> A_LWL<195> A_LWL<194> A_LWL<193> A_LWL<192> A_LWL<191> A_LWL<190> A_LWL<189> A_LWL<188> A_LWL<187> A_LWL<186> A_LWL<185> A_LWL<184> A_LWL<183> A_LWL<182> A_LWL<181> A_LWL<180> A_LWL<179> A_LWL<178> A_LWL<177> A_LWL<176> A_LWL<175> A_LWL<174> A_LWL<173> A_LWL<172> A_LWL<171> A_LWL<170> A_LWL<169> A_LWL<168> A_LWL<167> A_LWL<166> A_LWL<165> A_LWL<164> A_LWL<163> A_LWL<162> A_LWL<161> A_LWL<160> A_LWL<159> A_LWL<158> A_LWL<157> A_LWL<156> A_LWL<155> A_LWL<154> A_LWL<153> A_LWL<152> A_LWL<151> A_LWL<150> A_LWL<149> A_LWL<148> A_LWL<147> A_LWL<146> A_LWL<145> A_LWL<144> A_LWL<143> A_LWL<142> A_LWL<141> A_LWL<140> A_LWL<139> A_LWL<138> A_LWL<137> A_LWL<136> A_LWL<135> A_LWL<134> A_LWL<133> A_LWL<132> A_LWL<131> A_LWL<130> A_LWL<129> A_LWL<128> A_LWL<127> A_LWL<126> A_LWL<125> A_LWL<124> A_LWL<123> A_LWL<122> A_LWL<121> A_LWL<120> A_LWL<119> A_LWL<118> A_LWL<117> A_LWL<116> A_LWL<115> A_LWL<114> A_LWL<113> A_LWL<112> A_LWL<111> A_LWL<110> A_LWL<109> A_LWL<108> A_LWL<107> A_LWL<106> A_LWL<105> A_LWL<104> A_LWL<103> A_LWL<102> A_LWL<101> A_LWL<100> A_LWL<99> A_LWL<98> A_LWL<97> A_LWL<96> A_LWL<95> A_LWL<94> A_LWL<93> A_LWL<92> A_LWL<91> A_LWL<90> A_LWL<89> A_LWL<88> A_LWL<87> A_LWL<86> A_LWL<85> A_LWL<84> A_LWL<83> A_LWL<82> A_LWL<81> A_LWL<80> A_LWL<79> A_LWL<78> A_LWL<77> A_LWL<76> A_LWL<75> A_LWL<74> A_LWL<73> A_LWL<72> A_LWL<71> A_LWL<70> A_LWL<69> A_LWL<68> A_LWL<67> A_LWL<66> A_LWL<65> A_LWL<64> A_LWL<63> A_LWL<62> A_LWL<61> A_LWL<60> A_LWL<59> A_LWL<58> A_LWL<57> A_LWL<56> A_LWL<55> A_LWL<54> A_LWL<53> A_LWL<52> A_LWL<51> A_LWL<50> A_LWL<49> A_LWL<48> A_LWL<47> A_LWL<46> A_LWL<45> A_LWL<44> A_LWL<43> A_LWL<42> A_LWL<41> A_LWL<40> A_LWL<39> A_LWL<38> A_LWL<37> A_LWL<36> A_LWL<35> A_LWL<34> A_LWL<33> A_LWL<32> A_LWL<31> A_LWL<30> A_LWL<29> A_LWL<28> A_LWL<27> A_LWL<26> A_LWL<25> A_LWL<24> A_LWL<23> A_LWL<22> A_LWL<21> A_LWL<20> A_LWL<19> A_LWL<18> A_LWL<17> A_LWL<16> A_LWL<15> A_LWL<14> A_LWL<13> A_LWL<12> A_LWL<11> A_LWL<10> A_LWL<9> A_LWL<8> A_LWL<7> A_LWL<6> A_LWL<5> A_LWL<4> A_LWL<3> A_LWL<2> A_LWL<1> A_LWL<0> A_RWL<511> A_RWL<510> A_RWL<509> A_RWL<508> A_RWL<507> A_RWL<506> A_RWL<505> A_RWL<504> A_RWL<503> A_RWL<502> A_RWL<501> A_RWL<500> A_RWL<499> A_RWL<498> A_RWL<497> A_RWL<496> A_RWL<495> A_RWL<494> A_RWL<493> A_RWL<492> A_RWL<491> A_RWL<490> A_RWL<489> A_RWL<488> A_RWL<487> A_RWL<486> A_RWL<485> A_RWL<484> A_RWL<483> A_RWL<482> A_RWL<481> A_RWL<480> A_RWL<479> A_RWL<478> A_RWL<477> A_RWL<476> A_RWL<475> A_RWL<474> A_RWL<473> A_RWL<472> A_RWL<471> A_RWL<470> A_RWL<469> A_RWL<468> A_RWL<467> A_RWL<466> A_RWL<465> A_RWL<464> A_RWL<463> A_RWL<462> A_RWL<461> A_RWL<460> A_RWL<459> A_RWL<458> A_RWL<457> A_RWL<456> A_RWL<455> A_RWL<454> A_RWL<453> A_RWL<452> A_RWL<451> A_RWL<450> A_RWL<449> A_RWL<448> A_RWL<447> A_RWL<446> A_RWL<445> A_RWL<444> A_RWL<443> A_RWL<442> A_RWL<441> A_RWL<440> A_RWL<439> A_RWL<438> A_RWL<437> A_RWL<436> A_RWL<435> A_RWL<434> A_RWL<433> A_RWL<432> A_RWL<431> A_RWL<430> A_RWL<429> A_RWL<428> A_RWL<427> A_RWL<426> A_RWL<425> A_RWL<424> A_RWL<423> A_RWL<422> A_RWL<421> A_RWL<420> A_RWL<419> A_RWL<418> A_RWL<417> A_RWL<416> A_RWL<415> A_RWL<414> A_RWL<413> A_RWL<412> A_RWL<411> A_RWL<410> A_RWL<409> A_RWL<408> A_RWL<407> A_RWL<406> A_RWL<405> A_RWL<404> A_RWL<403> A_RWL<402> A_RWL<401> A_RWL<400> A_RWL<399> A_RWL<398> A_RWL<397> A_RWL<396> A_RWL<395> A_RWL<394> A_RWL<393> A_RWL<392> A_RWL<391> A_RWL<390> A_RWL<389> A_RWL<388> A_RWL<387> A_RWL<386> A_RWL<385> A_RWL<384> A_RWL<383> A_RWL<382> A_RWL<381> A_RWL<380> A_RWL<379> A_RWL<378> A_RWL<377> A_RWL<376> A_RWL<375> A_RWL<374> A_RWL<373> A_RWL<372> A_RWL<371> A_RWL<370> A_RWL<369> A_RWL<368> A_RWL<367> A_RWL<366> A_RWL<365> A_RWL<364> A_RWL<363> A_RWL<362> A_RWL<361> A_RWL<360> A_RWL<359> A_RWL<358> A_RWL<357> A_RWL<356> A_RWL<355> A_RWL<354> A_RWL<353> A_RWL<352> A_RWL<351> A_RWL<350> A_RWL<349> A_RWL<348> A_RWL<347> A_RWL<346> A_RWL<345> A_RWL<344> A_RWL<343> A_RWL<342> A_RWL<341> A_RWL<340> A_RWL<339> A_RWL<338> A_RWL<337> A_RWL<336> A_RWL<335> A_RWL<334> A_RWL<333> A_RWL<332> A_RWL<331> A_RWL<330> A_RWL<329> A_RWL<328> A_RWL<327> A_RWL<326> A_RWL<325> A_RWL<324> A_RWL<323> A_RWL<322> A_RWL<321> A_RWL<320> A_RWL<319> A_RWL<318> A_RWL<317> A_RWL<316> A_RWL<315> A_RWL<314> A_RWL<313> A_RWL<312> A_RWL<311> A_RWL<310> A_RWL<309> A_RWL<308> A_RWL<307> A_RWL<306> A_RWL<305> A_RWL<304> A_RWL<303> A_RWL<302> A_RWL<301> A_RWL<300> A_RWL<299> A_RWL<298> A_RWL<297> A_RWL<296> A_RWL<295> A_RWL<294> A_RWL<293> A_RWL<292> A_RWL<291> A_RWL<290> A_RWL<289> A_RWL<288> A_RWL<287> A_RWL<286> A_RWL<285> A_RWL<284> A_RWL<283> A_RWL<282> A_RWL<281> A_RWL<280> A_RWL<279> A_RWL<278> A_RWL<277> A_RWL<276> A_RWL<275> A_RWL<274> A_RWL<273> A_RWL<272> A_RWL<271> A_RWL<270> A_RWL<269> A_RWL<268> A_RWL<267> A_RWL<266> A_RWL<265> A_RWL<264> A_RWL<263> A_RWL<262> A_RWL<261> A_RWL<260> A_RWL<259> A_RWL<258> A_RWL<257> A_RWL<256> A_RWL<255> A_RWL<254> A_RWL<253> A_RWL<252> A_RWL<251> A_RWL<250> A_RWL<249> A_RWL<248> A_RWL<247> A_RWL<246> A_RWL<245> A_RWL<244> A_RWL<243> A_RWL<242> A_RWL<241> A_RWL<240> A_RWL<239> A_RWL<238> A_RWL<237> A_RWL<236> A_RWL<235> A_RWL<234> A_RWL<233> A_RWL<232> A_RWL<231> A_RWL<230> A_RWL<229> A_RWL<228> A_RWL<227> A_RWL<226> A_RWL<225> A_RWL<224> A_RWL<223> A_RWL<222> A_RWL<221> A_RWL<220> A_RWL<219> A_RWL<218> A_RWL<217> A_RWL<216> A_RWL<215> A_RWL<214> A_RWL<213> A_RWL<212> A_RWL<211> A_RWL<210> A_RWL<209> A_RWL<208> A_RWL<207> A_RWL<206> A_RWL<205> A_RWL<204> A_RWL<203> A_RWL<202> A_RWL<201> A_RWL<200> A_RWL<199> A_RWL<198> A_RWL<197> A_RWL<196> A_RWL<195> A_RWL<194> A_RWL<193> A_RWL<192> A_RWL<191> A_RWL<190> A_RWL<189> A_RWL<188> A_RWL<187> A_RWL<186> A_RWL<185> A_RWL<184> A_RWL<183> A_RWL<182> A_RWL<181> A_RWL<180> A_RWL<179> A_RWL<178> A_RWL<177> A_RWL<176> A_RWL<175> A_RWL<174> A_RWL<173> A_RWL<172> A_RWL<171> A_RWL<170> A_RWL<169> A_RWL<168> A_RWL<167> A_RWL<166> A_RWL<165> A_RWL<164> A_RWL<163> A_RWL<162> A_RWL<161> A_RWL<160> A_RWL<159> A_RWL<158> A_RWL<157> A_RWL<156> A_RWL<155> A_RWL<154> A_RWL<153> A_RWL<152> A_RWL<151> A_RWL<150> A_RWL<149> A_RWL<148> A_RWL<147> A_RWL<146> A_RWL<145> A_RWL<144> A_RWL<143> A_RWL<142> A_RWL<141> A_RWL<140> A_RWL<139> A_RWL<138> A_RWL<137> A_RWL<136> A_RWL<135> A_RWL<134> A_RWL<133> A_RWL<132> A_RWL<131> A_RWL<130> A_RWL<129> A_RWL<128> A_RWL<127> A_RWL<126> A_RWL<125> A_RWL<124> A_RWL<123> A_RWL<122> A_RWL<121> A_RWL<120> A_RWL<119> A_RWL<118> A_RWL<117> A_RWL<116> A_RWL<115> A_RWL<114> A_RWL<113> A_RWL<112> A_RWL<111> A_RWL<110> A_RWL<109> A_RWL<108> A_RWL<107> A_RWL<106> A_RWL<105> A_RWL<104> A_RWL<103> A_RWL<102> A_RWL<101> A_RWL<100> A_RWL<99> A_RWL<98> A_RWL<97> A_RWL<96> A_RWL<95> A_RWL<94> A_RWL<93> A_RWL<92> A_RWL<91> A_RWL<90> A_RWL<89> A_RWL<88> A_RWL<87> A_RWL<86> A_RWL<85> A_RWL<84> A_RWL<83> A_RWL<82> A_RWL<81> A_RWL<80> A_RWL<79> A_RWL<78> A_RWL<77> A_RWL<76> A_RWL<75> A_RWL<74> A_RWL<73> A_RWL<72> A_RWL<71> A_RWL<70> A_RWL<69> A_RWL<68> A_RWL<67> A_RWL<66> A_RWL<65> A_RWL<64> A_RWL<63> A_RWL<62> A_RWL<61> A_RWL<60> A_RWL<59> A_RWL<58> A_RWL<57> A_RWL<56> A_RWL<55> A_RWL<54> A_RWL<53> A_RWL<52> A_RWL<51> A_RWL<50> A_RWL<49> A_RWL<48> A_RWL<47> A_RWL<46> A_RWL<45> A_RWL<44> A_RWL<43> A_RWL<42> A_RWL<41> A_RWL<40> A_RWL<39> A_RWL<38> A_RWL<37> A_RWL<36> A_RWL<35> A_RWL<34> A_RWL<33> A_RWL<32> A_RWL<31> A_RWL<30> A_RWL<29> A_RWL<28> A_RWL<27> A_RWL<26> A_RWL<25> A_RWL<24> A_RWL<23> A_RWL<22> A_RWL<21> A_RWL<20> A_RWL<19> A_RWL<18> A_RWL<17> A_RWL<16> A_RWL<15> A_RWL<14> A_RWL<13> A_RWL<12> A_RWL<11> A_RWL<10> A_RWL<9> A_RWL<8> A_RWL<7> A_RWL<6> A_RWL<5> A_RWL<4> A_RWL<3> A_RWL<2> A_RWL<1> A_RWL<0> VDD_CORE VSS +XRAM<32> A_BLC<61> A_BLC<60> A_BLC_TOP<1> A_BLC_TOP<0> A_BLT<61> A_BLT<60> A_BLT_TOP<1> A_BLT_TOP<0> A_LWL<511> A_LWL<510> A_LWL<509> A_LWL<508> A_LWL<507> A_LWL<506> A_LWL<505> A_LWL<504> A_LWL<503> A_LWL<502> A_LWL<501> A_LWL<500> A_LWL<499> A_LWL<498> A_LWL<497> A_LWL<496> A_RWL<511> A_RWL<510> A_RWL<509> A_RWL<508> A_RWL<507> A_RWL<506> A_RWL<505> A_RWL<504> A_RWL<503> A_RWL<502> A_RWL<501> A_RWL<500> A_RWL<499> A_RWL<498> A_RWL<497> A_RWL<496> VDD_CORE VSS / RM_IHPSG13_8192x32_c4_1P_BITKIT_16x2_SRAM +XRAM<31> A_BLC<59> A_BLC<58> A_BLC<61> A_BLC<60> A_BLT<59> A_BLT<58> A_BLT<61> A_BLT<60> A_LWL<495> A_LWL<494> A_LWL<493> A_LWL<492> A_LWL<491> A_LWL<490> A_LWL<489> A_LWL<488> A_LWL<487> A_LWL<486> A_LWL<485> A_LWL<484> A_LWL<483> A_LWL<482> A_LWL<481> A_LWL<480> A_RWL<495> A_RWL<494> A_RWL<493> A_RWL<492> A_RWL<491> A_RWL<490> A_RWL<489> A_RWL<488> A_RWL<487> A_RWL<486> A_RWL<485> A_RWL<484> A_RWL<483> A_RWL<482> A_RWL<481> A_RWL<480> VDD_CORE VSS / RM_IHPSG13_8192x32_c4_1P_BITKIT_16x2_SRAM +XRAM<30> A_BLC<57> A_BLC<56> A_BLC<59> A_BLC<58> A_BLT<57> A_BLT<56> A_BLT<59> A_BLT<58> A_LWL<479> A_LWL<478> A_LWL<477> A_LWL<476> A_LWL<475> A_LWL<474> A_LWL<473> A_LWL<472> A_LWL<471> A_LWL<470> A_LWL<469> A_LWL<468> A_LWL<467> A_LWL<466> A_LWL<465> A_LWL<464> A_RWL<479> A_RWL<478> A_RWL<477> A_RWL<476> A_RWL<475> A_RWL<474> A_RWL<473> A_RWL<472> A_RWL<471> A_RWL<470> A_RWL<469> A_RWL<468> A_RWL<467> A_RWL<466> A_RWL<465> A_RWL<464> VDD_CORE VSS / RM_IHPSG13_8192x32_c4_1P_BITKIT_16x2_SRAM +XRAM<29> A_BLC<55> A_BLC<54> A_BLC<57> A_BLC<56> A_BLT<55> A_BLT<54> A_BLT<57> A_BLT<56> A_LWL<463> A_LWL<462> A_LWL<461> A_LWL<460> A_LWL<459> A_LWL<458> A_LWL<457> A_LWL<456> A_LWL<455> A_LWL<454> A_LWL<453> A_LWL<452> A_LWL<451> A_LWL<450> A_LWL<449> A_LWL<448> A_RWL<463> A_RWL<462> A_RWL<461> A_RWL<460> A_RWL<459> A_RWL<458> A_RWL<457> A_RWL<456> A_RWL<455> A_RWL<454> A_RWL<453> A_RWL<452> A_RWL<451> A_RWL<450> A_RWL<449> A_RWL<448> VDD_CORE VSS / RM_IHPSG13_8192x32_c4_1P_BITKIT_16x2_SRAM +XRAM<28> A_BLC<53> A_BLC<52> A_BLC<55> A_BLC<54> A_BLT<53> A_BLT<52> A_BLT<55> A_BLT<54> A_LWL<447> A_LWL<446> A_LWL<445> A_LWL<444> A_LWL<443> A_LWL<442> A_LWL<441> A_LWL<440> A_LWL<439> A_LWL<438> A_LWL<437> A_LWL<436> A_LWL<435> A_LWL<434> A_LWL<433> A_LWL<432> A_RWL<447> A_RWL<446> A_RWL<445> A_RWL<444> A_RWL<443> A_RWL<442> A_RWL<441> A_RWL<440> A_RWL<439> A_RWL<438> A_RWL<437> A_RWL<436> A_RWL<435> A_RWL<434> A_RWL<433> A_RWL<432> VDD_CORE VSS / RM_IHPSG13_8192x32_c4_1P_BITKIT_16x2_SRAM +XRAM<27> A_BLC<51> A_BLC<50> A_BLC<53> A_BLC<52> A_BLT<51> A_BLT<50> A_BLT<53> A_BLT<52> A_LWL<431> A_LWL<430> A_LWL<429> A_LWL<428> A_LWL<427> A_LWL<426> A_LWL<425> A_LWL<424> A_LWL<423> A_LWL<422> A_LWL<421> A_LWL<420> A_LWL<419> A_LWL<418> A_LWL<417> A_LWL<416> A_RWL<431> A_RWL<430> A_RWL<429> A_RWL<428> A_RWL<427> A_RWL<426> A_RWL<425> A_RWL<424> A_RWL<423> A_RWL<422> A_RWL<421> A_RWL<420> A_RWL<419> A_RWL<418> A_RWL<417> A_RWL<416> VDD_CORE VSS / RM_IHPSG13_8192x32_c4_1P_BITKIT_16x2_SRAM +XRAM<26> A_BLC<49> A_BLC<48> A_BLC<51> A_BLC<50> A_BLT<49> A_BLT<48> A_BLT<51> A_BLT<50> A_LWL<415> A_LWL<414> A_LWL<413> A_LWL<412> A_LWL<411> A_LWL<410> A_LWL<409> A_LWL<408> A_LWL<407> A_LWL<406> A_LWL<405> A_LWL<404> A_LWL<403> A_LWL<402> A_LWL<401> A_LWL<400> A_RWL<415> A_RWL<414> A_RWL<413> A_RWL<412> A_RWL<411> A_RWL<410> A_RWL<409> A_RWL<408> A_RWL<407> A_RWL<406> A_RWL<405> A_RWL<404> A_RWL<403> A_RWL<402> A_RWL<401> A_RWL<400> VDD_CORE VSS / RM_IHPSG13_8192x32_c4_1P_BITKIT_16x2_SRAM +XRAM<25> A_BLC<47> A_BLC<46> A_BLC<49> A_BLC<48> A_BLT<47> A_BLT<46> A_BLT<49> A_BLT<48> A_LWL<399> A_LWL<398> A_LWL<397> A_LWL<396> A_LWL<395> A_LWL<394> A_LWL<393> A_LWL<392> A_LWL<391> A_LWL<390> A_LWL<389> A_LWL<388> A_LWL<387> A_LWL<386> A_LWL<385> A_LWL<384> A_RWL<399> A_RWL<398> A_RWL<397> A_RWL<396> A_RWL<395> A_RWL<394> A_RWL<393> A_RWL<392> A_RWL<391> A_RWL<390> A_RWL<389> A_RWL<388> A_RWL<387> A_RWL<386> A_RWL<385> A_RWL<384> VDD_CORE VSS / RM_IHPSG13_8192x32_c4_1P_BITKIT_16x2_SRAM +XRAM<24> A_BLC<45> A_BLC<44> A_BLC<47> A_BLC<46> A_BLT<45> A_BLT<44> A_BLT<47> A_BLT<46> A_LWL<383> A_LWL<382> A_LWL<381> A_LWL<380> A_LWL<379> A_LWL<378> A_LWL<377> A_LWL<376> A_LWL<375> A_LWL<374> A_LWL<373> A_LWL<372> A_LWL<371> A_LWL<370> A_LWL<369> A_LWL<368> A_RWL<383> A_RWL<382> A_RWL<381> A_RWL<380> A_RWL<379> A_RWL<378> A_RWL<377> A_RWL<376> A_RWL<375> A_RWL<374> A_RWL<373> A_RWL<372> A_RWL<371> A_RWL<370> A_RWL<369> A_RWL<368> VDD_CORE VSS / RM_IHPSG13_8192x32_c4_1P_BITKIT_16x2_SRAM +XRAM<23> A_BLC<43> A_BLC<42> A_BLC<45> A_BLC<44> A_BLT<43> A_BLT<42> A_BLT<45> A_BLT<44> A_LWL<367> A_LWL<366> A_LWL<365> A_LWL<364> A_LWL<363> A_LWL<362> A_LWL<361> A_LWL<360> A_LWL<359> A_LWL<358> A_LWL<357> A_LWL<356> A_LWL<355> A_LWL<354> A_LWL<353> A_LWL<352> A_RWL<367> A_RWL<366> A_RWL<365> A_RWL<364> A_RWL<363> A_RWL<362> A_RWL<361> A_RWL<360> A_RWL<359> A_RWL<358> A_RWL<357> A_RWL<356> A_RWL<355> A_RWL<354> A_RWL<353> A_RWL<352> VDD_CORE VSS / RM_IHPSG13_8192x32_c4_1P_BITKIT_16x2_SRAM +XRAM<22> A_BLC<41> A_BLC<40> A_BLC<43> A_BLC<42> A_BLT<41> A_BLT<40> A_BLT<43> A_BLT<42> A_LWL<351> A_LWL<350> A_LWL<349> A_LWL<348> A_LWL<347> A_LWL<346> A_LWL<345> A_LWL<344> A_LWL<343> A_LWL<342> A_LWL<341> A_LWL<340> A_LWL<339> A_LWL<338> A_LWL<337> A_LWL<336> A_RWL<351> A_RWL<350> A_RWL<349> A_RWL<348> A_RWL<347> A_RWL<346> A_RWL<345> A_RWL<344> A_RWL<343> A_RWL<342> A_RWL<341> A_RWL<340> A_RWL<339> A_RWL<338> A_RWL<337> A_RWL<336> VDD_CORE VSS / RM_IHPSG13_8192x32_c4_1P_BITKIT_16x2_SRAM +XRAM<21> A_BLC<39> A_BLC<38> A_BLC<41> A_BLC<40> A_BLT<39> A_BLT<38> A_BLT<41> A_BLT<40> A_LWL<335> A_LWL<334> A_LWL<333> A_LWL<332> A_LWL<331> A_LWL<330> A_LWL<329> A_LWL<328> A_LWL<327> A_LWL<326> A_LWL<325> A_LWL<324> A_LWL<323> A_LWL<322> A_LWL<321> A_LWL<320> A_RWL<335> A_RWL<334> A_RWL<333> A_RWL<332> A_RWL<331> A_RWL<330> A_RWL<329> A_RWL<328> A_RWL<327> A_RWL<326> A_RWL<325> A_RWL<324> A_RWL<323> A_RWL<322> A_RWL<321> A_RWL<320> VDD_CORE VSS / RM_IHPSG13_8192x32_c4_1P_BITKIT_16x2_SRAM +XRAM<20> A_BLC<37> A_BLC<36> A_BLC<39> A_BLC<38> A_BLT<37> A_BLT<36> A_BLT<39> A_BLT<38> A_LWL<319> A_LWL<318> A_LWL<317> A_LWL<316> A_LWL<315> A_LWL<314> A_LWL<313> A_LWL<312> A_LWL<311> A_LWL<310> A_LWL<309> A_LWL<308> A_LWL<307> A_LWL<306> A_LWL<305> A_LWL<304> A_RWL<319> A_RWL<318> A_RWL<317> A_RWL<316> A_RWL<315> A_RWL<314> A_RWL<313> A_RWL<312> A_RWL<311> A_RWL<310> A_RWL<309> A_RWL<308> A_RWL<307> A_RWL<306> A_RWL<305> A_RWL<304> VDD_CORE VSS / RM_IHPSG13_8192x32_c4_1P_BITKIT_16x2_SRAM +XRAM<19> A_BLC<35> A_BLC<34> A_BLC<37> A_BLC<36> A_BLT<35> A_BLT<34> A_BLT<37> A_BLT<36> A_LWL<303> A_LWL<302> A_LWL<301> A_LWL<300> A_LWL<299> A_LWL<298> A_LWL<297> A_LWL<296> A_LWL<295> A_LWL<294> A_LWL<293> A_LWL<292> A_LWL<291> A_LWL<290> A_LWL<289> A_LWL<288> A_RWL<303> A_RWL<302> A_RWL<301> A_RWL<300> A_RWL<299> A_RWL<298> A_RWL<297> A_RWL<296> A_RWL<295> A_RWL<294> A_RWL<293> A_RWL<292> A_RWL<291> A_RWL<290> A_RWL<289> A_RWL<288> VDD_CORE VSS / RM_IHPSG13_8192x32_c4_1P_BITKIT_16x2_SRAM +XRAM<18> A_BLC<33> A_BLC<32> A_BLC<35> A_BLC<34> A_BLT<33> A_BLT<32> A_BLT<35> A_BLT<34> A_LWL<287> A_LWL<286> A_LWL<285> A_LWL<284> A_LWL<283> A_LWL<282> A_LWL<281> A_LWL<280> A_LWL<279> A_LWL<278> A_LWL<277> A_LWL<276> A_LWL<275> A_LWL<274> A_LWL<273> A_LWL<272> A_RWL<287> A_RWL<286> A_RWL<285> A_RWL<284> A_RWL<283> A_RWL<282> A_RWL<281> A_RWL<280> A_RWL<279> A_RWL<278> A_RWL<277> A_RWL<276> A_RWL<275> A_RWL<274> A_RWL<273> A_RWL<272> VDD_CORE VSS / RM_IHPSG13_8192x32_c4_1P_BITKIT_16x2_SRAM +XRAM<17> A_BLC<31> A_BLC<30> A_BLC<33> A_BLC<32> A_BLT<31> A_BLT<30> A_BLT<33> A_BLT<32> A_LWL<271> A_LWL<270> A_LWL<269> A_LWL<268> A_LWL<267> A_LWL<266> A_LWL<265> A_LWL<264> A_LWL<263> A_LWL<262> A_LWL<261> A_LWL<260> A_LWL<259> A_LWL<258> A_LWL<257> A_LWL<256> A_RWL<271> A_RWL<270> A_RWL<269> A_RWL<268> A_RWL<267> A_RWL<266> A_RWL<265> A_RWL<264> A_RWL<263> A_RWL<262> A_RWL<261> A_RWL<260> A_RWL<259> A_RWL<258> A_RWL<257> A_RWL<256> VDD_CORE VSS / RM_IHPSG13_8192x32_c4_1P_BITKIT_16x2_SRAM +XRAM<16> A_BLC<29> A_BLC<28> A_BLC<31> A_BLC<30> A_BLT<29> A_BLT<28> A_BLT<31> A_BLT<30> A_LWL<255> A_LWL<254> A_LWL<253> A_LWL<252> A_LWL<251> A_LWL<250> A_LWL<249> A_LWL<248> A_LWL<247> A_LWL<246> A_LWL<245> A_LWL<244> A_LWL<243> A_LWL<242> A_LWL<241> A_LWL<240> A_RWL<255> A_RWL<254> A_RWL<253> A_RWL<252> A_RWL<251> A_RWL<250> A_RWL<249> A_RWL<248> A_RWL<247> A_RWL<246> A_RWL<245> A_RWL<244> A_RWL<243> A_RWL<242> A_RWL<241> A_RWL<240> VDD_CORE VSS / RM_IHPSG13_8192x32_c4_1P_BITKIT_16x2_SRAM +XRAM<15> A_BLC<27> A_BLC<26> A_BLC<29> A_BLC<28> A_BLT<27> A_BLT<26> A_BLT<29> A_BLT<28> A_LWL<239> A_LWL<238> A_LWL<237> A_LWL<236> A_LWL<235> A_LWL<234> A_LWL<233> A_LWL<232> A_LWL<231> A_LWL<230> A_LWL<229> A_LWL<228> A_LWL<227> A_LWL<226> A_LWL<225> A_LWL<224> A_RWL<239> A_RWL<238> A_RWL<237> A_RWL<236> A_RWL<235> A_RWL<234> A_RWL<233> A_RWL<232> A_RWL<231> A_RWL<230> A_RWL<229> A_RWL<228> A_RWL<227> A_RWL<226> A_RWL<225> A_RWL<224> VDD_CORE VSS / RM_IHPSG13_8192x32_c4_1P_BITKIT_16x2_SRAM +XRAM<14> A_BLC<25> A_BLC<24> A_BLC<27> A_BLC<26> A_BLT<25> A_BLT<24> A_BLT<27> A_BLT<26> A_LWL<223> A_LWL<222> A_LWL<221> A_LWL<220> A_LWL<219> A_LWL<218> A_LWL<217> A_LWL<216> A_LWL<215> A_LWL<214> A_LWL<213> A_LWL<212> A_LWL<211> A_LWL<210> A_LWL<209> A_LWL<208> A_RWL<223> A_RWL<222> A_RWL<221> A_RWL<220> A_RWL<219> A_RWL<218> A_RWL<217> A_RWL<216> A_RWL<215> A_RWL<214> A_RWL<213> A_RWL<212> A_RWL<211> A_RWL<210> A_RWL<209> A_RWL<208> VDD_CORE VSS / RM_IHPSG13_8192x32_c4_1P_BITKIT_16x2_SRAM +XRAM<13> A_BLC<23> A_BLC<22> A_BLC<25> A_BLC<24> A_BLT<23> A_BLT<22> A_BLT<25> A_BLT<24> A_LWL<207> A_LWL<206> A_LWL<205> A_LWL<204> A_LWL<203> A_LWL<202> A_LWL<201> A_LWL<200> A_LWL<199> A_LWL<198> A_LWL<197> A_LWL<196> A_LWL<195> A_LWL<194> A_LWL<193> A_LWL<192> A_RWL<207> A_RWL<206> A_RWL<205> A_RWL<204> A_RWL<203> A_RWL<202> A_RWL<201> A_RWL<200> A_RWL<199> A_RWL<198> A_RWL<197> A_RWL<196> A_RWL<195> A_RWL<194> A_RWL<193> A_RWL<192> VDD_CORE VSS / RM_IHPSG13_8192x32_c4_1P_BITKIT_16x2_SRAM +XRAM<12> A_BLC<21> A_BLC<20> A_BLC<23> A_BLC<22> A_BLT<21> A_BLT<20> A_BLT<23> A_BLT<22> A_LWL<191> A_LWL<190> A_LWL<189> A_LWL<188> A_LWL<187> A_LWL<186> A_LWL<185> A_LWL<184> A_LWL<183> A_LWL<182> A_LWL<181> A_LWL<180> A_LWL<179> A_LWL<178> A_LWL<177> A_LWL<176> A_RWL<191> A_RWL<190> A_RWL<189> A_RWL<188> A_RWL<187> A_RWL<186> A_RWL<185> A_RWL<184> A_RWL<183> A_RWL<182> A_RWL<181> A_RWL<180> A_RWL<179> A_RWL<178> A_RWL<177> A_RWL<176> VDD_CORE VSS / RM_IHPSG13_8192x32_c4_1P_BITKIT_16x2_SRAM +XRAM<11> A_BLC<19> A_BLC<18> A_BLC<21> A_BLC<20> A_BLT<19> A_BLT<18> A_BLT<21> A_BLT<20> A_LWL<175> A_LWL<174> A_LWL<173> A_LWL<172> A_LWL<171> A_LWL<170> A_LWL<169> A_LWL<168> A_LWL<167> A_LWL<166> A_LWL<165> A_LWL<164> A_LWL<163> A_LWL<162> A_LWL<161> A_LWL<160> A_RWL<175> A_RWL<174> A_RWL<173> A_RWL<172> A_RWL<171> A_RWL<170> A_RWL<169> A_RWL<168> A_RWL<167> A_RWL<166> A_RWL<165> A_RWL<164> A_RWL<163> A_RWL<162> A_RWL<161> A_RWL<160> VDD_CORE VSS / RM_IHPSG13_8192x32_c4_1P_BITKIT_16x2_SRAM +XRAM<10> A_BLC<17> A_BLC<16> A_BLC<19> A_BLC<18> A_BLT<17> A_BLT<16> A_BLT<19> A_BLT<18> A_LWL<159> A_LWL<158> A_LWL<157> A_LWL<156> A_LWL<155> A_LWL<154> A_LWL<153> A_LWL<152> A_LWL<151> A_LWL<150> A_LWL<149> A_LWL<148> A_LWL<147> A_LWL<146> A_LWL<145> A_LWL<144> A_RWL<159> A_RWL<158> A_RWL<157> A_RWL<156> A_RWL<155> A_RWL<154> A_RWL<153> A_RWL<152> A_RWL<151> A_RWL<150> A_RWL<149> A_RWL<148> A_RWL<147> A_RWL<146> A_RWL<145> A_RWL<144> VDD_CORE VSS / RM_IHPSG13_8192x32_c4_1P_BITKIT_16x2_SRAM +XRAM<9> A_BLC<15> A_BLC<14> A_BLC<17> A_BLC<16> A_BLT<15> A_BLT<14> A_BLT<17> A_BLT<16> A_LWL<143> A_LWL<142> A_LWL<141> A_LWL<140> A_LWL<139> A_LWL<138> A_LWL<137> A_LWL<136> A_LWL<135> A_LWL<134> A_LWL<133> A_LWL<132> A_LWL<131> A_LWL<130> A_LWL<129> A_LWL<128> A_RWL<143> A_RWL<142> A_RWL<141> A_RWL<140> A_RWL<139> A_RWL<138> A_RWL<137> A_RWL<136> A_RWL<135> A_RWL<134> A_RWL<133> A_RWL<132> A_RWL<131> A_RWL<130> A_RWL<129> A_RWL<128> VDD_CORE VSS / RM_IHPSG13_8192x32_c4_1P_BITKIT_16x2_SRAM +XRAM<8> A_BLC<13> A_BLC<12> A_BLC<15> A_BLC<14> A_BLT<13> A_BLT<12> A_BLT<15> A_BLT<14> A_LWL<127> A_LWL<126> A_LWL<125> A_LWL<124> A_LWL<123> A_LWL<122> A_LWL<121> A_LWL<120> A_LWL<119> A_LWL<118> A_LWL<117> A_LWL<116> A_LWL<115> A_LWL<114> A_LWL<113> A_LWL<112> A_RWL<127> A_RWL<126> A_RWL<125> A_RWL<124> A_RWL<123> A_RWL<122> A_RWL<121> A_RWL<120> A_RWL<119> A_RWL<118> A_RWL<117> A_RWL<116> A_RWL<115> A_RWL<114> A_RWL<113> A_RWL<112> VDD_CORE VSS / RM_IHPSG13_8192x32_c4_1P_BITKIT_16x2_SRAM +XRAM<7> A_BLC<11> A_BLC<10> A_BLC<13> A_BLC<12> A_BLT<11> A_BLT<10> A_BLT<13> A_BLT<12> A_LWL<111> A_LWL<110> A_LWL<109> A_LWL<108> A_LWL<107> A_LWL<106> A_LWL<105> A_LWL<104> A_LWL<103> A_LWL<102> A_LWL<101> A_LWL<100> A_LWL<99> A_LWL<98> A_LWL<97> A_LWL<96> A_RWL<111> A_RWL<110> A_RWL<109> A_RWL<108> A_RWL<107> A_RWL<106> A_RWL<105> A_RWL<104> A_RWL<103> A_RWL<102> A_RWL<101> A_RWL<100> A_RWL<99> A_RWL<98> A_RWL<97> A_RWL<96> VDD_CORE VSS / RM_IHPSG13_8192x32_c4_1P_BITKIT_16x2_SRAM +XRAM<6> A_BLC<9> A_BLC<8> A_BLC<11> A_BLC<10> A_BLT<9> A_BLT<8> A_BLT<11> A_BLT<10> A_LWL<95> A_LWL<94> A_LWL<93> A_LWL<92> A_LWL<91> A_LWL<90> A_LWL<89> A_LWL<88> A_LWL<87> A_LWL<86> A_LWL<85> A_LWL<84> A_LWL<83> A_LWL<82> A_LWL<81> A_LWL<80> A_RWL<95> A_RWL<94> A_RWL<93> A_RWL<92> A_RWL<91> A_RWL<90> A_RWL<89> A_RWL<88> A_RWL<87> A_RWL<86> A_RWL<85> A_RWL<84> A_RWL<83> A_RWL<82> A_RWL<81> A_RWL<80> VDD_CORE VSS / RM_IHPSG13_8192x32_c4_1P_BITKIT_16x2_SRAM +XRAM<5> A_BLC<7> A_BLC<6> A_BLC<9> A_BLC<8> A_BLT<7> A_BLT<6> A_BLT<9> A_BLT<8> A_LWL<79> A_LWL<78> A_LWL<77> A_LWL<76> A_LWL<75> A_LWL<74> A_LWL<73> A_LWL<72> A_LWL<71> A_LWL<70> A_LWL<69> A_LWL<68> A_LWL<67> A_LWL<66> A_LWL<65> A_LWL<64> A_RWL<79> A_RWL<78> A_RWL<77> A_RWL<76> A_RWL<75> A_RWL<74> A_RWL<73> A_RWL<72> A_RWL<71> A_RWL<70> A_RWL<69> A_RWL<68> A_RWL<67> A_RWL<66> A_RWL<65> A_RWL<64> VDD_CORE VSS / RM_IHPSG13_8192x32_c4_1P_BITKIT_16x2_SRAM +XRAM<4> A_BLC<5> A_BLC<4> A_BLC<7> A_BLC<6> A_BLT<5> A_BLT<4> A_BLT<7> A_BLT<6> A_LWL<63> A_LWL<62> A_LWL<61> A_LWL<60> A_LWL<59> A_LWL<58> A_LWL<57> A_LWL<56> A_LWL<55> A_LWL<54> A_LWL<53> A_LWL<52> A_LWL<51> A_LWL<50> A_LWL<49> A_LWL<48> A_RWL<63> A_RWL<62> A_RWL<61> A_RWL<60> A_RWL<59> A_RWL<58> A_RWL<57> A_RWL<56> A_RWL<55> A_RWL<54> A_RWL<53> A_RWL<52> A_RWL<51> A_RWL<50> A_RWL<49> A_RWL<48> VDD_CORE VSS / RM_IHPSG13_8192x32_c4_1P_BITKIT_16x2_SRAM +XRAM<3> A_BLC<3> A_BLC<2> A_BLC<5> A_BLC<4> A_BLT<3> A_BLT<2> A_BLT<5> A_BLT<4> A_LWL<47> A_LWL<46> A_LWL<45> A_LWL<44> A_LWL<43> A_LWL<42> A_LWL<41> A_LWL<40> A_LWL<39> A_LWL<38> A_LWL<37> A_LWL<36> A_LWL<35> A_LWL<34> A_LWL<33> A_LWL<32> A_RWL<47> A_RWL<46> A_RWL<45> A_RWL<44> A_RWL<43> A_RWL<42> A_RWL<41> A_RWL<40> A_RWL<39> A_RWL<38> A_RWL<37> A_RWL<36> A_RWL<35> A_RWL<34> A_RWL<33> A_RWL<32> VDD_CORE VSS / RM_IHPSG13_8192x32_c4_1P_BITKIT_16x2_SRAM +XRAM<2> A_BLC<1> A_BLC<0> A_BLC<3> A_BLC<2> A_BLT<1> A_BLT<0> A_BLT<3> A_BLT<2> A_LWL<31> A_LWL<30> A_LWL<29> A_LWL<28> A_LWL<27> A_LWL<26> A_LWL<25> A_LWL<24> A_LWL<23> A_LWL<22> A_LWL<21> A_LWL<20> A_LWL<19> A_LWL<18> A_LWL<17> A_LWL<16> A_RWL<31> A_RWL<30> A_RWL<29> A_RWL<28> A_RWL<27> A_RWL<26> A_RWL<25> A_RWL<24> A_RWL<23> A_RWL<22> A_RWL<21> A_RWL<20> A_RWL<19> A_RWL<18> A_RWL<17> A_RWL<16> VDD_CORE VSS / RM_IHPSG13_8192x32_c4_1P_BITKIT_16x2_SRAM +XRAM<1> A_BLC_BOT<1> A_BLC_BOT<0> A_BLC<1> A_BLC<0> A_BLT_BOT<1> A_BLT_BOT<0> A_BLT<1> A_BLT<0> A_LWL<15> A_LWL<14> A_LWL<13> A_LWL<12> A_LWL<11> A_LWL<10> A_LWL<9> A_LWL<8> A_LWL<7> A_LWL<6> A_LWL<5> A_LWL<4> A_LWL<3> A_LWL<2> A_LWL<1> A_LWL<0> A_RWL<15> A_RWL<14> A_RWL<13> A_RWL<12> A_RWL<11> A_RWL<10> A_RWL<9> A_RWL<8> A_RWL<7> A_RWL<6> A_RWL<5> A_RWL<4> A_RWL<3> A_RWL<2> A_RWL<1> A_RWL<0> VDD_CORE VSS / RM_IHPSG13_8192x32_c4_1P_BITKIT_16x2_SRAM +XEDGE<1> A_BLC_TOP<1> A_BLC_TOP<0> A_BLT_TOP<1> A_BLT_TOP<0> VDD_CORE VSS / RM_IHPSG13_8192x32_c4_1P_BITKIT_16x2_EDGE_TB +XEDGE<0> A_BLC_BOT<1> A_BLC_BOT<0> A_BLT_BOT<1> A_BLT_BOT<0> VDD_CORE VSS / RM_IHPSG13_8192x32_c4_1P_BITKIT_16x2_EDGE_TB +.ENDS + + + + +.SUBCKT RM_IHPSG13_8192x32_c4_1P_MATRIX_pcell_1 A_BLC<255> A_BLC<254> A_BLC<253> A_BLC<252> A_BLC<251> A_BLC<250> A_BLC<249> A_BLC<248> A_BLC<247> A_BLC<246> A_BLC<245> A_BLC<244> A_BLC<243> A_BLC<242> A_BLC<241> A_BLC<240> A_BLC<239> A_BLC<238> A_BLC<237> A_BLC<236> A_BLC<235> A_BLC<234> A_BLC<233> A_BLC<232> A_BLC<231> A_BLC<230> A_BLC<229> A_BLC<228> A_BLC<227> A_BLC<226> A_BLC<225> A_BLC<224> A_BLC<223> A_BLC<222> A_BLC<221> A_BLC<220> A_BLC<219> A_BLC<218> A_BLC<217> A_BLC<216> A_BLC<215> A_BLC<214> A_BLC<213> A_BLC<212> A_BLC<211> A_BLC<210> A_BLC<209> A_BLC<208> A_BLC<207> A_BLC<206> A_BLC<205> A_BLC<204> A_BLC<203> A_BLC<202> A_BLC<201> A_BLC<200> A_BLC<199> A_BLC<198> A_BLC<197> A_BLC<196> A_BLC<195> A_BLC<194> A_BLC<193> A_BLC<192> A_BLC<191> A_BLC<190> A_BLC<189> A_BLC<188> A_BLC<187> A_BLC<186> A_BLC<185> A_BLC<184> A_BLC<183> A_BLC<182> A_BLC<181> A_BLC<180> A_BLC<179> A_BLC<178> A_BLC<177> A_BLC<176> A_BLC<175> A_BLC<174> A_BLC<173> A_BLC<172> A_BLC<171> A_BLC<170> A_BLC<169> A_BLC<168> A_BLC<167> A_BLC<166> A_BLC<165> A_BLC<164> A_BLC<163> A_BLC<162> A_BLC<161> A_BLC<160> A_BLC<159> A_BLC<158> A_BLC<157> A_BLC<156> A_BLC<155> A_BLC<154> A_BLC<153> A_BLC<152> A_BLC<151> A_BLC<150> A_BLC<149> A_BLC<148> A_BLC<147> A_BLC<146> A_BLC<145> A_BLC<144> A_BLC<143> A_BLC<142> A_BLC<141> A_BLC<140> A_BLC<139> A_BLC<138> A_BLC<137> A_BLC<136> A_BLC<135> A_BLC<134> A_BLC<133> A_BLC<132> A_BLC<131> A_BLC<130> A_BLC<129> A_BLC<128> A_BLC<127> A_BLC<126> A_BLC<125> A_BLC<124> A_BLC<123> A_BLC<122> A_BLC<121> A_BLC<120> A_BLC<119> A_BLC<118> A_BLC<117> A_BLC<116> A_BLC<115> A_BLC<114> A_BLC<113> A_BLC<112> A_BLC<111> A_BLC<110> A_BLC<109> A_BLC<108> A_BLC<107> A_BLC<106> A_BLC<105> A_BLC<104> A_BLC<103> A_BLC<102> A_BLC<101> A_BLC<100> A_BLC<99> A_BLC<98> A_BLC<97> A_BLC<96> A_BLC<95> A_BLC<94> A_BLC<93> A_BLC<92> A_BLC<91> A_BLC<90> A_BLC<89> A_BLC<88> A_BLC<87> A_BLC<86> A_BLC<85> A_BLC<84> A_BLC<83> A_BLC<82> A_BLC<81> A_BLC<80> A_BLC<79> A_BLC<78> A_BLC<77> A_BLC<76> A_BLC<75> A_BLC<74> A_BLC<73> A_BLC<72> A_BLC<71> A_BLC<70> A_BLC<69> A_BLC<68> A_BLC<67> A_BLC<66> A_BLC<65> A_BLC<64> A_BLC<63> A_BLC<62> A_BLC<61> A_BLC<60> A_BLC<59> A_BLC<58> A_BLC<57> A_BLC<56> A_BLC<55> A_BLC<54> A_BLC<53> A_BLC<52> A_BLC<51> A_BLC<50> A_BLC<49> A_BLC<48> A_BLC<47> A_BLC<46> A_BLC<45> A_BLC<44> A_BLC<43> A_BLC<42> A_BLC<41> A_BLC<40> A_BLC<39> A_BLC<38> A_BLC<37> A_BLC<36> A_BLC<35> A_BLC<34> A_BLC<33> A_BLC<32> A_BLC<31> A_BLC<30> A_BLC<29> A_BLC<28> A_BLC<27> A_BLC<26> A_BLC<25> A_BLC<24> A_BLC<23> A_BLC<22> A_BLC<21> A_BLC<20> A_BLC<19> A_BLC<18> A_BLC<17> A_BLC<16> A_BLC<15> A_BLC<14> A_BLC<13> A_BLC<12> A_BLC<11> A_BLC<10> A_BLC<9> A_BLC<8> A_BLC<7> A_BLC<6> A_BLC<5> A_BLC<4> A_BLC<3> A_BLC<2> A_BLC<1> A_BLC<0> A_BLT<255> A_BLT<254> A_BLT<253> A_BLT<252> A_BLT<251> A_BLT<250> A_BLT<249> A_BLT<248> A_BLT<247> A_BLT<246> A_BLT<245> A_BLT<244> A_BLT<243> A_BLT<242> A_BLT<241> A_BLT<240> A_BLT<239> A_BLT<238> A_BLT<237> A_BLT<236> A_BLT<235> A_BLT<234> A_BLT<233> A_BLT<232> A_BLT<231> A_BLT<230> A_BLT<229> A_BLT<228> A_BLT<227> A_BLT<226> A_BLT<225> A_BLT<224> A_BLT<223> A_BLT<222> A_BLT<221> A_BLT<220> A_BLT<219> A_BLT<218> A_BLT<217> A_BLT<216> A_BLT<215> A_BLT<214> A_BLT<213> A_BLT<212> A_BLT<211> A_BLT<210> A_BLT<209> A_BLT<208> A_BLT<207> A_BLT<206> A_BLT<205> A_BLT<204> A_BLT<203> A_BLT<202> A_BLT<201> A_BLT<200> A_BLT<199> A_BLT<198> A_BLT<197> A_BLT<196> A_BLT<195> A_BLT<194> A_BLT<193> A_BLT<192> A_BLT<191> A_BLT<190> A_BLT<189> A_BLT<188> A_BLT<187> A_BLT<186> A_BLT<185> A_BLT<184> A_BLT<183> A_BLT<182> A_BLT<181> A_BLT<180> A_BLT<179> A_BLT<178> A_BLT<177> A_BLT<176> A_BLT<175> A_BLT<174> A_BLT<173> A_BLT<172> A_BLT<171> A_BLT<170> A_BLT<169> A_BLT<168> A_BLT<167> A_BLT<166> A_BLT<165> A_BLT<164> A_BLT<163> A_BLT<162> A_BLT<161> A_BLT<160> A_BLT<159> A_BLT<158> A_BLT<157> A_BLT<156> A_BLT<155> A_BLT<154> A_BLT<153> A_BLT<152> A_BLT<151> A_BLT<150> A_BLT<149> A_BLT<148> A_BLT<147> A_BLT<146> A_BLT<145> A_BLT<144> A_BLT<143> A_BLT<142> A_BLT<141> A_BLT<140> A_BLT<139> A_BLT<138> A_BLT<137> A_BLT<136> A_BLT<135> A_BLT<134> A_BLT<133> A_BLT<132> A_BLT<131> A_BLT<130> A_BLT<129> A_BLT<128> A_BLT<127> A_BLT<126> A_BLT<125> A_BLT<124> A_BLT<123> A_BLT<122> A_BLT<121> A_BLT<120> A_BLT<119> A_BLT<118> A_BLT<117> A_BLT<116> A_BLT<115> A_BLT<114> A_BLT<113> A_BLT<112> A_BLT<111> A_BLT<110> A_BLT<109> A_BLT<108> A_BLT<107> A_BLT<106> A_BLT<105> A_BLT<104> A_BLT<103> A_BLT<102> A_BLT<101> A_BLT<100> A_BLT<99> A_BLT<98> A_BLT<97> A_BLT<96> A_BLT<95> A_BLT<94> A_BLT<93> A_BLT<92> A_BLT<91> A_BLT<90> A_BLT<89> A_BLT<88> A_BLT<87> A_BLT<86> A_BLT<85> A_BLT<84> A_BLT<83> A_BLT<82> A_BLT<81> A_BLT<80> A_BLT<79> A_BLT<78> A_BLT<77> A_BLT<76> A_BLT<75> A_BLT<74> A_BLT<73> A_BLT<72> A_BLT<71> A_BLT<70> A_BLT<69> A_BLT<68> A_BLT<67> A_BLT<66> A_BLT<65> A_BLT<64> A_BLT<63> A_BLT<62> A_BLT<61> A_BLT<60> A_BLT<59> A_BLT<58> A_BLT<57> A_BLT<56> A_BLT<55> A_BLT<54> A_BLT<53> A_BLT<52> A_BLT<51> A_BLT<50> A_BLT<49> A_BLT<48> A_BLT<47> A_BLT<46> A_BLT<45> A_BLT<44> A_BLT<43> A_BLT<42> A_BLT<41> A_BLT<40> A_BLT<39> A_BLT<38> A_BLT<37> A_BLT<36> A_BLT<35> A_BLT<34> A_BLT<33> A_BLT<32> A_BLT<31> A_BLT<30> A_BLT<29> A_BLT<28> A_BLT<27> A_BLT<26> A_BLT<25> A_BLT<24> A_BLT<23> A_BLT<22> A_BLT<21> A_BLT<20> A_BLT<19> A_BLT<18> A_BLT<17> A_BLT<16> A_BLT<15> A_BLT<14> A_BLT<13> A_BLT<12> A_BLT<11> A_BLT<10> A_BLT<9> A_BLT<8> A_BLT<7> A_BLT<6> A_BLT<5> A_BLT<4> A_BLT<3> A_BLT<2> A_BLT<1> A_BLT<0> A_WL<511> A_WL<510> A_WL<509> A_WL<508> A_WL<507> A_WL<506> A_WL<505> A_WL<504> A_WL<503> A_WL<502> A_WL<501> A_WL<500> A_WL<499> A_WL<498> A_WL<497> A_WL<496> A_WL<495> A_WL<494> A_WL<493> A_WL<492> A_WL<491> A_WL<490> A_WL<489> A_WL<488> A_WL<487> A_WL<486> A_WL<485> A_WL<484> A_WL<483> A_WL<482> A_WL<481> A_WL<480> A_WL<479> A_WL<478> A_WL<477> A_WL<476> A_WL<475> A_WL<474> A_WL<473> A_WL<472> A_WL<471> A_WL<470> A_WL<469> A_WL<468> A_WL<467> A_WL<466> A_WL<465> A_WL<464> A_WL<463> A_WL<462> A_WL<461> A_WL<460> A_WL<459> A_WL<458> A_WL<457> A_WL<456> A_WL<455> A_WL<454> A_WL<453> A_WL<452> A_WL<451> A_WL<450> A_WL<449> A_WL<448> A_WL<447> A_WL<446> A_WL<445> A_WL<444> A_WL<443> A_WL<442> A_WL<441> A_WL<440> A_WL<439> A_WL<438> A_WL<437> A_WL<436> A_WL<435> A_WL<434> A_WL<433> A_WL<432> A_WL<431> A_WL<430> A_WL<429> A_WL<428> A_WL<427> A_WL<426> A_WL<425> A_WL<424> A_WL<423> A_WL<422> A_WL<421> A_WL<420> A_WL<419> A_WL<418> A_WL<417> A_WL<416> A_WL<415> A_WL<414> A_WL<413> A_WL<412> A_WL<411> A_WL<410> A_WL<409> A_WL<408> A_WL<407> A_WL<406> A_WL<405> A_WL<404> A_WL<403> A_WL<402> A_WL<401> A_WL<400> A_WL<399> A_WL<398> A_WL<397> A_WL<396> A_WL<395> A_WL<394> A_WL<393> A_WL<392> A_WL<391> A_WL<390> A_WL<389> A_WL<388> A_WL<387> A_WL<386> A_WL<385> A_WL<384> A_WL<383> A_WL<382> A_WL<381> A_WL<380> A_WL<379> A_WL<378> A_WL<377> A_WL<376> A_WL<375> A_WL<374> A_WL<373> A_WL<372> A_WL<371> A_WL<370> A_WL<369> A_WL<368> A_WL<367> A_WL<366> A_WL<365> A_WL<364> A_WL<363> A_WL<362> A_WL<361> A_WL<360> A_WL<359> A_WL<358> A_WL<357> A_WL<356> A_WL<355> A_WL<354> A_WL<353> A_WL<352> A_WL<351> A_WL<350> A_WL<349> A_WL<348> A_WL<347> A_WL<346> A_WL<345> A_WL<344> A_WL<343> A_WL<342> A_WL<341> A_WL<340> A_WL<339> A_WL<338> A_WL<337> A_WL<336> A_WL<335> A_WL<334> A_WL<333> A_WL<332> A_WL<331> A_WL<330> A_WL<329> A_WL<328> A_WL<327> A_WL<326> A_WL<325> A_WL<324> A_WL<323> A_WL<322> A_WL<321> A_WL<320> A_WL<319> A_WL<318> A_WL<317> A_WL<316> A_WL<315> A_WL<314> A_WL<313> A_WL<312> A_WL<311> A_WL<310> A_WL<309> A_WL<308> A_WL<307> A_WL<306> A_WL<305> A_WL<304> A_WL<303> A_WL<302> A_WL<301> A_WL<300> A_WL<299> A_WL<298> A_WL<297> A_WL<296> A_WL<295> A_WL<294> A_WL<293> A_WL<292> A_WL<291> A_WL<290> A_WL<289> A_WL<288> A_WL<287> A_WL<286> A_WL<285> A_WL<284> A_WL<283> A_WL<282> A_WL<281> A_WL<280> A_WL<279> A_WL<278> A_WL<277> A_WL<276> A_WL<275> A_WL<274> A_WL<273> A_WL<272> A_WL<271> A_WL<270> A_WL<269> A_WL<268> A_WL<267> A_WL<266> A_WL<265> A_WL<264> A_WL<263> A_WL<262> A_WL<261> A_WL<260> A_WL<259> A_WL<258> A_WL<257> A_WL<256> A_WL<255> A_WL<254> A_WL<253> A_WL<252> A_WL<251> A_WL<250> A_WL<249> A_WL<248> A_WL<247> A_WL<246> A_WL<245> A_WL<244> A_WL<243> A_WL<242> A_WL<241> A_WL<240> A_WL<239> A_WL<238> A_WL<237> A_WL<236> A_WL<235> A_WL<234> A_WL<233> A_WL<232> A_WL<231> A_WL<230> A_WL<229> A_WL<228> A_WL<227> A_WL<226> A_WL<225> A_WL<224> A_WL<223> A_WL<222> A_WL<221> A_WL<220> A_WL<219> A_WL<218> A_WL<217> A_WL<216> A_WL<215> A_WL<214> A_WL<213> A_WL<212> A_WL<211> A_WL<210> A_WL<209> A_WL<208> A_WL<207> A_WL<206> A_WL<205> A_WL<204> A_WL<203> A_WL<202> A_WL<201> A_WL<200> A_WL<199> A_WL<198> A_WL<197> A_WL<196> A_WL<195> A_WL<194> A_WL<193> A_WL<192> A_WL<191> A_WL<190> A_WL<189> A_WL<188> A_WL<187> A_WL<186> A_WL<185> A_WL<184> A_WL<183> A_WL<182> A_WL<181> A_WL<180> A_WL<179> A_WL<178> A_WL<177> A_WL<176> A_WL<175> A_WL<174> A_WL<173> A_WL<172> A_WL<171> A_WL<170> A_WL<169> A_WL<168> A_WL<167> A_WL<166> A_WL<165> A_WL<164> A_WL<163> A_WL<162> A_WL<161> A_WL<160> A_WL<159> A_WL<158> A_WL<157> A_WL<156> A_WL<155> A_WL<154> A_WL<153> A_WL<152> A_WL<151> A_WL<150> A_WL<149> A_WL<148> A_WL<147> A_WL<146> A_WL<145> A_WL<144> A_WL<143> A_WL<142> A_WL<141> A_WL<140> A_WL<139> A_WL<138> A_WL<137> A_WL<136> A_WL<135> A_WL<134> A_WL<133> A_WL<132> A_WL<131> A_WL<130> A_WL<129> A_WL<128> A_WL<127> A_WL<126> A_WL<125> A_WL<124> A_WL<123> A_WL<122> A_WL<121> A_WL<120> A_WL<119> A_WL<118> A_WL<117> A_WL<116> A_WL<115> A_WL<114> A_WL<113> A_WL<112> A_WL<111> A_WL<110> A_WL<109> A_WL<108> A_WL<107> A_WL<106> A_WL<105> A_WL<104> A_WL<103> A_WL<102> A_WL<101> A_WL<100> A_WL<99> A_WL<98> A_WL<97> A_WL<96> A_WL<95> A_WL<94> A_WL<93> A_WL<92> A_WL<91> A_WL<90> A_WL<89> A_WL<88> A_WL<87> A_WL<86> A_WL<85> A_WL<84> A_WL<83> A_WL<82> A_WL<81> A_WL<80> A_WL<79> A_WL<78> A_WL<77> A_WL<76> A_WL<75> A_WL<74> A_WL<73> A_WL<72> A_WL<71> A_WL<70> A_WL<69> A_WL<68> A_WL<67> A_WL<66> A_WL<65> A_WL<64> A_WL<63> A_WL<62> A_WL<61> A_WL<60> A_WL<59> A_WL<58> A_WL<57> A_WL<56> A_WL<55> A_WL<54> A_WL<53> A_WL<52> A_WL<51> A_WL<50> A_WL<49> A_WL<48> A_WL<47> A_WL<46> A_WL<45> A_WL<44> A_WL<43> A_WL<42> A_WL<41> A_WL<40> A_WL<39> A_WL<38> A_WL<37> A_WL<36> A_WL<35> A_WL<34> A_WL<33> A_WL<32> A_WL<31> A_WL<30> A_WL<29> A_WL<28> A_WL<27> A_WL<26> A_WL<25> A_WL<24> A_WL<23> A_WL<22> A_WL<21> A_WL<20> A_WL<19> A_WL<18> A_WL<17> A_WL<16> A_WL<15> A_WL<14> A_WL<13> A_WL<12> A_WL<11> A_WL<10> A_WL<9> A_WL<8> A_WL<7> A_WL<6> A_WL<5> A_WL<4> A_WL<3> A_WL<2> A_WL<1> A_WL<0> VDD_CORE VSS +XCORNER<3> VDD_CORE VSS / RM_IHPSG13_8192x32_c4_1P_BITKIT_16x2_CORNER +XCORNER<2> VDD_CORE VSS / RM_IHPSG13_8192x32_c4_1P_BITKIT_16x2_CORNER +XCORNER<1> VDD_CORE VSS / RM_IHPSG13_8192x32_c4_1P_BITKIT_16x2_CORNER +XCORNER<0> VDD_CORE VSS / RM_IHPSG13_8192x32_c4_1P_BITKIT_16x2_CORNER +XRAMEDGE_L<31> A_WL<511> A_WL<510> A_WL<509> A_WL<508> A_WL<507> A_WL<506> A_WL<505> A_WL<504> A_WL<503> A_WL<502> A_WL<501> A_WL<500> A_WL<499> A_WL<498> A_WL<497> A_WL<496> VDD_CORE VSS / RM_IHPSG13_8192x32_c4_1P_BITKIT_16x2_EDGE_LR +XRAMEDGE_L<30> A_WL<495> A_WL<494> A_WL<493> A_WL<492> A_WL<491> A_WL<490> A_WL<489> A_WL<488> A_WL<487> A_WL<486> A_WL<485> A_WL<484> A_WL<483> A_WL<482> A_WL<481> A_WL<480> VDD_CORE VSS / RM_IHPSG13_8192x32_c4_1P_BITKIT_16x2_EDGE_LR +XRAMEDGE_L<29> A_WL<479> A_WL<478> A_WL<477> A_WL<476> A_WL<475> A_WL<474> A_WL<473> A_WL<472> A_WL<471> A_WL<470> A_WL<469> A_WL<468> A_WL<467> A_WL<466> A_WL<465> A_WL<464> VDD_CORE VSS / RM_IHPSG13_8192x32_c4_1P_BITKIT_16x2_EDGE_LR +XRAMEDGE_L<28> A_WL<463> A_WL<462> A_WL<461> A_WL<460> A_WL<459> A_WL<458> A_WL<457> A_WL<456> A_WL<455> A_WL<454> A_WL<453> A_WL<452> A_WL<451> A_WL<450> A_WL<449> A_WL<448> VDD_CORE VSS / RM_IHPSG13_8192x32_c4_1P_BITKIT_16x2_EDGE_LR +XRAMEDGE_L<27> A_WL<447> A_WL<446> A_WL<445> A_WL<444> A_WL<443> A_WL<442> A_WL<441> A_WL<440> A_WL<439> A_WL<438> A_WL<437> A_WL<436> A_WL<435> A_WL<434> A_WL<433> A_WL<432> VDD_CORE VSS / RM_IHPSG13_8192x32_c4_1P_BITKIT_16x2_EDGE_LR +XRAMEDGE_L<26> A_WL<431> A_WL<430> A_WL<429> A_WL<428> A_WL<427> A_WL<426> A_WL<425> A_WL<424> A_WL<423> A_WL<422> A_WL<421> A_WL<420> A_WL<419> A_WL<418> A_WL<417> A_WL<416> VDD_CORE VSS / RM_IHPSG13_8192x32_c4_1P_BITKIT_16x2_EDGE_LR +XRAMEDGE_L<25> A_WL<415> A_WL<414> A_WL<413> A_WL<412> A_WL<411> A_WL<410> A_WL<409> A_WL<408> A_WL<407> A_WL<406> A_WL<405> A_WL<404> A_WL<403> A_WL<402> A_WL<401> A_WL<400> VDD_CORE VSS / RM_IHPSG13_8192x32_c4_1P_BITKIT_16x2_EDGE_LR +XRAMEDGE_L<24> A_WL<399> A_WL<398> A_WL<397> A_WL<396> A_WL<395> A_WL<394> A_WL<393> A_WL<392> A_WL<391> A_WL<390> A_WL<389> A_WL<388> A_WL<387> A_WL<386> A_WL<385> A_WL<384> VDD_CORE VSS / RM_IHPSG13_8192x32_c4_1P_BITKIT_16x2_EDGE_LR +XRAMEDGE_L<23> A_WL<383> A_WL<382> A_WL<381> A_WL<380> A_WL<379> A_WL<378> A_WL<377> A_WL<376> A_WL<375> A_WL<374> A_WL<373> A_WL<372> A_WL<371> A_WL<370> A_WL<369> A_WL<368> VDD_CORE VSS / RM_IHPSG13_8192x32_c4_1P_BITKIT_16x2_EDGE_LR +XRAMEDGE_L<22> A_WL<367> A_WL<366> A_WL<365> A_WL<364> A_WL<363> A_WL<362> A_WL<361> A_WL<360> A_WL<359> A_WL<358> A_WL<357> A_WL<356> A_WL<355> A_WL<354> A_WL<353> A_WL<352> VDD_CORE VSS / RM_IHPSG13_8192x32_c4_1P_BITKIT_16x2_EDGE_LR +XRAMEDGE_L<21> A_WL<351> A_WL<350> A_WL<349> A_WL<348> A_WL<347> A_WL<346> A_WL<345> A_WL<344> A_WL<343> A_WL<342> A_WL<341> A_WL<340> A_WL<339> A_WL<338> A_WL<337> A_WL<336> VDD_CORE VSS / RM_IHPSG13_8192x32_c4_1P_BITKIT_16x2_EDGE_LR +XRAMEDGE_L<20> A_WL<335> A_WL<334> A_WL<333> A_WL<332> A_WL<331> A_WL<330> A_WL<329> A_WL<328> A_WL<327> A_WL<326> A_WL<325> A_WL<324> A_WL<323> A_WL<322> A_WL<321> A_WL<320> VDD_CORE VSS / RM_IHPSG13_8192x32_c4_1P_BITKIT_16x2_EDGE_LR +XRAMEDGE_L<19> A_WL<319> A_WL<318> A_WL<317> A_WL<316> A_WL<315> A_WL<314> A_WL<313> A_WL<312> A_WL<311> A_WL<310> A_WL<309> A_WL<308> A_WL<307> A_WL<306> A_WL<305> A_WL<304> VDD_CORE VSS / RM_IHPSG13_8192x32_c4_1P_BITKIT_16x2_EDGE_LR +XRAMEDGE_L<18> A_WL<303> A_WL<302> A_WL<301> A_WL<300> A_WL<299> A_WL<298> A_WL<297> A_WL<296> A_WL<295> A_WL<294> A_WL<293> A_WL<292> A_WL<291> A_WL<290> A_WL<289> A_WL<288> VDD_CORE VSS / RM_IHPSG13_8192x32_c4_1P_BITKIT_16x2_EDGE_LR +XRAMEDGE_L<17> A_WL<287> A_WL<286> A_WL<285> A_WL<284> A_WL<283> A_WL<282> A_WL<281> A_WL<280> A_WL<279> A_WL<278> A_WL<277> A_WL<276> A_WL<275> A_WL<274> A_WL<273> A_WL<272> VDD_CORE VSS / RM_IHPSG13_8192x32_c4_1P_BITKIT_16x2_EDGE_LR +XRAMEDGE_L<16> A_WL<271> A_WL<270> A_WL<269> A_WL<268> A_WL<267> A_WL<266> A_WL<265> A_WL<264> A_WL<263> A_WL<262> A_WL<261> A_WL<260> A_WL<259> A_WL<258> A_WL<257> A_WL<256> VDD_CORE VSS / RM_IHPSG13_8192x32_c4_1P_BITKIT_16x2_EDGE_LR +XRAMEDGE_L<15> A_WL<255> A_WL<254> A_WL<253> A_WL<252> A_WL<251> A_WL<250> A_WL<249> A_WL<248> A_WL<247> A_WL<246> A_WL<245> A_WL<244> A_WL<243> A_WL<242> A_WL<241> A_WL<240> VDD_CORE VSS / RM_IHPSG13_8192x32_c4_1P_BITKIT_16x2_EDGE_LR +XRAMEDGE_L<14> A_WL<239> A_WL<238> A_WL<237> A_WL<236> A_WL<235> A_WL<234> A_WL<233> A_WL<232> A_WL<231> A_WL<230> A_WL<229> A_WL<228> A_WL<227> A_WL<226> A_WL<225> A_WL<224> VDD_CORE VSS / RM_IHPSG13_8192x32_c4_1P_BITKIT_16x2_EDGE_LR +XRAMEDGE_L<13> A_WL<223> A_WL<222> A_WL<221> A_WL<220> A_WL<219> A_WL<218> A_WL<217> A_WL<216> A_WL<215> A_WL<214> A_WL<213> A_WL<212> A_WL<211> A_WL<210> A_WL<209> A_WL<208> VDD_CORE VSS / RM_IHPSG13_8192x32_c4_1P_BITKIT_16x2_EDGE_LR +XRAMEDGE_L<12> A_WL<207> A_WL<206> A_WL<205> A_WL<204> A_WL<203> A_WL<202> A_WL<201> A_WL<200> A_WL<199> A_WL<198> A_WL<197> A_WL<196> A_WL<195> A_WL<194> A_WL<193> A_WL<192> VDD_CORE VSS / RM_IHPSG13_8192x32_c4_1P_BITKIT_16x2_EDGE_LR +XRAMEDGE_L<11> A_WL<191> A_WL<190> A_WL<189> A_WL<188> A_WL<187> A_WL<186> A_WL<185> A_WL<184> A_WL<183> A_WL<182> A_WL<181> A_WL<180> A_WL<179> A_WL<178> A_WL<177> A_WL<176> VDD_CORE VSS / RM_IHPSG13_8192x32_c4_1P_BITKIT_16x2_EDGE_LR +XRAMEDGE_L<10> A_WL<175> A_WL<174> A_WL<173> A_WL<172> A_WL<171> A_WL<170> A_WL<169> A_WL<168> A_WL<167> A_WL<166> A_WL<165> A_WL<164> A_WL<163> A_WL<162> A_WL<161> A_WL<160> VDD_CORE VSS / RM_IHPSG13_8192x32_c4_1P_BITKIT_16x2_EDGE_LR +XRAMEDGE_L<9> A_WL<159> A_WL<158> A_WL<157> A_WL<156> A_WL<155> A_WL<154> A_WL<153> A_WL<152> A_WL<151> A_WL<150> A_WL<149> A_WL<148> A_WL<147> A_WL<146> A_WL<145> A_WL<144> VDD_CORE VSS / RM_IHPSG13_8192x32_c4_1P_BITKIT_16x2_EDGE_LR +XRAMEDGE_L<8> A_WL<143> A_WL<142> A_WL<141> A_WL<140> A_WL<139> A_WL<138> A_WL<137> A_WL<136> A_WL<135> A_WL<134> A_WL<133> A_WL<132> A_WL<131> A_WL<130> A_WL<129> A_WL<128> VDD_CORE VSS / RM_IHPSG13_8192x32_c4_1P_BITKIT_16x2_EDGE_LR +XRAMEDGE_L<7> A_WL<127> A_WL<126> A_WL<125> A_WL<124> A_WL<123> A_WL<122> A_WL<121> A_WL<120> A_WL<119> A_WL<118> A_WL<117> A_WL<116> A_WL<115> A_WL<114> A_WL<113> A_WL<112> VDD_CORE VSS / RM_IHPSG13_8192x32_c4_1P_BITKIT_16x2_EDGE_LR +XRAMEDGE_L<6> A_WL<111> A_WL<110> A_WL<109> A_WL<108> A_WL<107> A_WL<106> A_WL<105> A_WL<104> A_WL<103> A_WL<102> A_WL<101> A_WL<100> A_WL<99> A_WL<98> A_WL<97> A_WL<96> VDD_CORE VSS / RM_IHPSG13_8192x32_c4_1P_BITKIT_16x2_EDGE_LR +XRAMEDGE_L<5> A_WL<95> A_WL<94> A_WL<93> A_WL<92> A_WL<91> A_WL<90> A_WL<89> A_WL<88> A_WL<87> A_WL<86> A_WL<85> A_WL<84> A_WL<83> A_WL<82> A_WL<81> A_WL<80> VDD_CORE VSS / RM_IHPSG13_8192x32_c4_1P_BITKIT_16x2_EDGE_LR +XRAMEDGE_L<4> A_WL<79> A_WL<78> A_WL<77> A_WL<76> A_WL<75> A_WL<74> A_WL<73> A_WL<72> A_WL<71> A_WL<70> A_WL<69> A_WL<68> A_WL<67> A_WL<66> A_WL<65> A_WL<64> VDD_CORE VSS / RM_IHPSG13_8192x32_c4_1P_BITKIT_16x2_EDGE_LR +XRAMEDGE_L<3> A_WL<63> A_WL<62> A_WL<61> A_WL<60> A_WL<59> A_WL<58> A_WL<57> A_WL<56> A_WL<55> A_WL<54> A_WL<53> A_WL<52> A_WL<51> A_WL<50> A_WL<49> A_WL<48> VDD_CORE VSS / RM_IHPSG13_8192x32_c4_1P_BITKIT_16x2_EDGE_LR +XRAMEDGE_L<2> A_WL<47> A_WL<46> A_WL<45> A_WL<44> A_WL<43> A_WL<42> A_WL<41> A_WL<40> A_WL<39> A_WL<38> A_WL<37> A_WL<36> A_WL<35> A_WL<34> A_WL<33> A_WL<32> VDD_CORE VSS / RM_IHPSG13_8192x32_c4_1P_BITKIT_16x2_EDGE_LR +XRAMEDGE_L<1> A_WL<31> A_WL<30> A_WL<29> A_WL<28> A_WL<27> A_WL<26> A_WL<25> A_WL<24> A_WL<23> A_WL<22> A_WL<21> A_WL<20> A_WL<19> A_WL<18> A_WL<17> A_WL<16> VDD_CORE VSS / RM_IHPSG13_8192x32_c4_1P_BITKIT_16x2_EDGE_LR +XRAMEDGE_L<0> A_WL<15> A_WL<14> A_WL<13> A_WL<12> A_WL<11> A_WL<10> A_WL<9> A_WL<8> A_WL<7> A_WL<6> A_WL<5> A_WL<4> A_WL<3> A_WL<2> A_WL<1> A_WL<0> VDD_CORE VSS / RM_IHPSG13_8192x32_c4_1P_BITKIT_16x2_EDGE_LR +XRAMEDGE_R<31> A_IWL<65535> A_IWL<65534> A_IWL<65533> A_IWL<65532> A_IWL<65531> A_IWL<65530> A_IWL<65529> A_IWL<65528> A_IWL<65527> A_IWL<65526> A_IWL<65525> A_IWL<65524> A_IWL<65523> A_IWL<65522> A_IWL<65521> A_IWL<65520> VDD_CORE VSS / RM_IHPSG13_8192x32_c4_1P_BITKIT_16x2_EDGE_LR +XRAMEDGE_R<30> A_IWL<65519> A_IWL<65518> A_IWL<65517> A_IWL<65516> A_IWL<65515> A_IWL<65514> A_IWL<65513> A_IWL<65512> A_IWL<65511> A_IWL<65510> A_IWL<65509> A_IWL<65508> A_IWL<65507> A_IWL<65506> A_IWL<65505> A_IWL<65504> VDD_CORE VSS / RM_IHPSG13_8192x32_c4_1P_BITKIT_16x2_EDGE_LR +XRAMEDGE_R<29> A_IWL<65503> A_IWL<65502> A_IWL<65501> A_IWL<65500> A_IWL<65499> A_IWL<65498> A_IWL<65497> A_IWL<65496> A_IWL<65495> A_IWL<65494> A_IWL<65493> A_IWL<65492> A_IWL<65491> A_IWL<65490> A_IWL<65489> A_IWL<65488> VDD_CORE VSS / RM_IHPSG13_8192x32_c4_1P_BITKIT_16x2_EDGE_LR +XRAMEDGE_R<28> A_IWL<65487> A_IWL<65486> A_IWL<65485> A_IWL<65484> A_IWL<65483> A_IWL<65482> A_IWL<65481> A_IWL<65480> A_IWL<65479> A_IWL<65478> A_IWL<65477> A_IWL<65476> A_IWL<65475> A_IWL<65474> A_IWL<65473> A_IWL<65472> VDD_CORE VSS / RM_IHPSG13_8192x32_c4_1P_BITKIT_16x2_EDGE_LR +XRAMEDGE_R<27> A_IWL<65471> A_IWL<65470> A_IWL<65469> A_IWL<65468> A_IWL<65467> A_IWL<65466> A_IWL<65465> A_IWL<65464> A_IWL<65463> A_IWL<65462> A_IWL<65461> A_IWL<65460> A_IWL<65459> A_IWL<65458> A_IWL<65457> A_IWL<65456> VDD_CORE VSS / RM_IHPSG13_8192x32_c4_1P_BITKIT_16x2_EDGE_LR +XRAMEDGE_R<26> A_IWL<65455> A_IWL<65454> A_IWL<65453> A_IWL<65452> A_IWL<65451> A_IWL<65450> A_IWL<65449> A_IWL<65448> A_IWL<65447> A_IWL<65446> A_IWL<65445> A_IWL<65444> A_IWL<65443> A_IWL<65442> A_IWL<65441> A_IWL<65440> VDD_CORE VSS / RM_IHPSG13_8192x32_c4_1P_BITKIT_16x2_EDGE_LR +XRAMEDGE_R<25> A_IWL<65439> A_IWL<65438> A_IWL<65437> A_IWL<65436> A_IWL<65435> A_IWL<65434> A_IWL<65433> A_IWL<65432> A_IWL<65431> A_IWL<65430> A_IWL<65429> A_IWL<65428> A_IWL<65427> A_IWL<65426> A_IWL<65425> A_IWL<65424> VDD_CORE VSS / RM_IHPSG13_8192x32_c4_1P_BITKIT_16x2_EDGE_LR +XRAMEDGE_R<24> A_IWL<65423> A_IWL<65422> A_IWL<65421> A_IWL<65420> A_IWL<65419> A_IWL<65418> A_IWL<65417> A_IWL<65416> A_IWL<65415> A_IWL<65414> A_IWL<65413> A_IWL<65412> A_IWL<65411> A_IWL<65410> A_IWL<65409> A_IWL<65408> VDD_CORE VSS / RM_IHPSG13_8192x32_c4_1P_BITKIT_16x2_EDGE_LR +XRAMEDGE_R<23> A_IWL<65407> A_IWL<65406> A_IWL<65405> A_IWL<65404> A_IWL<65403> A_IWL<65402> A_IWL<65401> A_IWL<65400> A_IWL<65399> A_IWL<65398> A_IWL<65397> A_IWL<65396> A_IWL<65395> A_IWL<65394> A_IWL<65393> A_IWL<65392> VDD_CORE VSS / RM_IHPSG13_8192x32_c4_1P_BITKIT_16x2_EDGE_LR +XRAMEDGE_R<22> A_IWL<65391> A_IWL<65390> A_IWL<65389> A_IWL<65388> A_IWL<65387> A_IWL<65386> A_IWL<65385> A_IWL<65384> A_IWL<65383> A_IWL<65382> A_IWL<65381> A_IWL<65380> A_IWL<65379> A_IWL<65378> A_IWL<65377> A_IWL<65376> VDD_CORE VSS / RM_IHPSG13_8192x32_c4_1P_BITKIT_16x2_EDGE_LR +XRAMEDGE_R<21> A_IWL<65375> A_IWL<65374> A_IWL<65373> A_IWL<65372> A_IWL<65371> A_IWL<65370> A_IWL<65369> A_IWL<65368> A_IWL<65367> A_IWL<65366> A_IWL<65365> A_IWL<65364> A_IWL<65363> A_IWL<65362> A_IWL<65361> A_IWL<65360> VDD_CORE VSS / RM_IHPSG13_8192x32_c4_1P_BITKIT_16x2_EDGE_LR +XRAMEDGE_R<20> A_IWL<65359> A_IWL<65358> A_IWL<65357> A_IWL<65356> A_IWL<65355> A_IWL<65354> A_IWL<65353> A_IWL<65352> A_IWL<65351> A_IWL<65350> A_IWL<65349> A_IWL<65348> A_IWL<65347> A_IWL<65346> A_IWL<65345> A_IWL<65344> VDD_CORE VSS / RM_IHPSG13_8192x32_c4_1P_BITKIT_16x2_EDGE_LR +XRAMEDGE_R<19> A_IWL<65343> A_IWL<65342> A_IWL<65341> A_IWL<65340> A_IWL<65339> A_IWL<65338> A_IWL<65337> A_IWL<65336> A_IWL<65335> A_IWL<65334> A_IWL<65333> A_IWL<65332> A_IWL<65331> A_IWL<65330> A_IWL<65329> A_IWL<65328> VDD_CORE VSS / RM_IHPSG13_8192x32_c4_1P_BITKIT_16x2_EDGE_LR +XRAMEDGE_R<18> A_IWL<65327> A_IWL<65326> A_IWL<65325> A_IWL<65324> A_IWL<65323> A_IWL<65322> A_IWL<65321> A_IWL<65320> A_IWL<65319> A_IWL<65318> A_IWL<65317> A_IWL<65316> A_IWL<65315> A_IWL<65314> A_IWL<65313> A_IWL<65312> VDD_CORE VSS / RM_IHPSG13_8192x32_c4_1P_BITKIT_16x2_EDGE_LR +XRAMEDGE_R<17> A_IWL<65311> A_IWL<65310> A_IWL<65309> A_IWL<65308> A_IWL<65307> A_IWL<65306> A_IWL<65305> A_IWL<65304> A_IWL<65303> A_IWL<65302> A_IWL<65301> A_IWL<65300> A_IWL<65299> A_IWL<65298> A_IWL<65297> A_IWL<65296> VDD_CORE VSS / RM_IHPSG13_8192x32_c4_1P_BITKIT_16x2_EDGE_LR +XRAMEDGE_R<16> A_IWL<65295> A_IWL<65294> A_IWL<65293> A_IWL<65292> A_IWL<65291> A_IWL<65290> A_IWL<65289> A_IWL<65288> A_IWL<65287> A_IWL<65286> A_IWL<65285> A_IWL<65284> A_IWL<65283> A_IWL<65282> A_IWL<65281> A_IWL<65280> VDD_CORE VSS / RM_IHPSG13_8192x32_c4_1P_BITKIT_16x2_EDGE_LR +XRAMEDGE_R<15> A_IWL<65279> A_IWL<65278> A_IWL<65277> A_IWL<65276> A_IWL<65275> A_IWL<65274> A_IWL<65273> A_IWL<65272> A_IWL<65271> A_IWL<65270> A_IWL<65269> A_IWL<65268> A_IWL<65267> A_IWL<65266> A_IWL<65265> A_IWL<65264> VDD_CORE VSS / RM_IHPSG13_8192x32_c4_1P_BITKIT_16x2_EDGE_LR +XRAMEDGE_R<14> A_IWL<65263> A_IWL<65262> A_IWL<65261> A_IWL<65260> A_IWL<65259> A_IWL<65258> A_IWL<65257> A_IWL<65256> A_IWL<65255> A_IWL<65254> A_IWL<65253> A_IWL<65252> A_IWL<65251> A_IWL<65250> A_IWL<65249> A_IWL<65248> VDD_CORE VSS / RM_IHPSG13_8192x32_c4_1P_BITKIT_16x2_EDGE_LR +XRAMEDGE_R<13> A_IWL<65247> A_IWL<65246> A_IWL<65245> A_IWL<65244> A_IWL<65243> A_IWL<65242> A_IWL<65241> A_IWL<65240> A_IWL<65239> A_IWL<65238> A_IWL<65237> A_IWL<65236> A_IWL<65235> A_IWL<65234> A_IWL<65233> A_IWL<65232> VDD_CORE VSS / RM_IHPSG13_8192x32_c4_1P_BITKIT_16x2_EDGE_LR +XRAMEDGE_R<12> A_IWL<65231> A_IWL<65230> A_IWL<65229> A_IWL<65228> A_IWL<65227> A_IWL<65226> A_IWL<65225> A_IWL<65224> A_IWL<65223> A_IWL<65222> A_IWL<65221> A_IWL<65220> A_IWL<65219> A_IWL<65218> A_IWL<65217> A_IWL<65216> VDD_CORE VSS / RM_IHPSG13_8192x32_c4_1P_BITKIT_16x2_EDGE_LR +XRAMEDGE_R<11> A_IWL<65215> A_IWL<65214> A_IWL<65213> A_IWL<65212> A_IWL<65211> A_IWL<65210> A_IWL<65209> A_IWL<65208> A_IWL<65207> A_IWL<65206> A_IWL<65205> A_IWL<65204> A_IWL<65203> A_IWL<65202> A_IWL<65201> A_IWL<65200> VDD_CORE VSS / RM_IHPSG13_8192x32_c4_1P_BITKIT_16x2_EDGE_LR +XRAMEDGE_R<10> A_IWL<65199> A_IWL<65198> A_IWL<65197> A_IWL<65196> A_IWL<65195> A_IWL<65194> A_IWL<65193> A_IWL<65192> A_IWL<65191> A_IWL<65190> A_IWL<65189> A_IWL<65188> A_IWL<65187> A_IWL<65186> A_IWL<65185> A_IWL<65184> VDD_CORE VSS / RM_IHPSG13_8192x32_c4_1P_BITKIT_16x2_EDGE_LR +XRAMEDGE_R<9> A_IWL<65183> A_IWL<65182> A_IWL<65181> A_IWL<65180> A_IWL<65179> A_IWL<65178> A_IWL<65177> A_IWL<65176> A_IWL<65175> A_IWL<65174> A_IWL<65173> A_IWL<65172> A_IWL<65171> A_IWL<65170> A_IWL<65169> A_IWL<65168> VDD_CORE VSS / RM_IHPSG13_8192x32_c4_1P_BITKIT_16x2_EDGE_LR +XRAMEDGE_R<8> A_IWL<65167> A_IWL<65166> A_IWL<65165> A_IWL<65164> A_IWL<65163> A_IWL<65162> A_IWL<65161> A_IWL<65160> A_IWL<65159> A_IWL<65158> A_IWL<65157> A_IWL<65156> A_IWL<65155> A_IWL<65154> A_IWL<65153> A_IWL<65152> VDD_CORE VSS / RM_IHPSG13_8192x32_c4_1P_BITKIT_16x2_EDGE_LR +XRAMEDGE_R<7> A_IWL<65151> A_IWL<65150> A_IWL<65149> A_IWL<65148> A_IWL<65147> A_IWL<65146> A_IWL<65145> A_IWL<65144> A_IWL<65143> A_IWL<65142> A_IWL<65141> A_IWL<65140> A_IWL<65139> A_IWL<65138> A_IWL<65137> A_IWL<65136> VDD_CORE VSS / RM_IHPSG13_8192x32_c4_1P_BITKIT_16x2_EDGE_LR +XRAMEDGE_R<6> A_IWL<65135> A_IWL<65134> A_IWL<65133> A_IWL<65132> A_IWL<65131> A_IWL<65130> A_IWL<65129> A_IWL<65128> A_IWL<65127> A_IWL<65126> A_IWL<65125> A_IWL<65124> A_IWL<65123> A_IWL<65122> A_IWL<65121> A_IWL<65120> VDD_CORE VSS / RM_IHPSG13_8192x32_c4_1P_BITKIT_16x2_EDGE_LR +XRAMEDGE_R<5> A_IWL<65119> A_IWL<65118> A_IWL<65117> A_IWL<65116> A_IWL<65115> A_IWL<65114> A_IWL<65113> A_IWL<65112> A_IWL<65111> A_IWL<65110> A_IWL<65109> A_IWL<65108> A_IWL<65107> A_IWL<65106> A_IWL<65105> A_IWL<65104> VDD_CORE VSS / RM_IHPSG13_8192x32_c4_1P_BITKIT_16x2_EDGE_LR +XRAMEDGE_R<4> A_IWL<65103> A_IWL<65102> A_IWL<65101> A_IWL<65100> A_IWL<65099> A_IWL<65098> A_IWL<65097> A_IWL<65096> A_IWL<65095> A_IWL<65094> A_IWL<65093> A_IWL<65092> A_IWL<65091> A_IWL<65090> A_IWL<65089> A_IWL<65088> VDD_CORE VSS / RM_IHPSG13_8192x32_c4_1P_BITKIT_16x2_EDGE_LR +XRAMEDGE_R<3> A_IWL<65087> A_IWL<65086> A_IWL<65085> A_IWL<65084> A_IWL<65083> A_IWL<65082> A_IWL<65081> A_IWL<65080> A_IWL<65079> A_IWL<65078> A_IWL<65077> A_IWL<65076> A_IWL<65075> A_IWL<65074> A_IWL<65073> A_IWL<65072> VDD_CORE VSS / RM_IHPSG13_8192x32_c4_1P_BITKIT_16x2_EDGE_LR +XRAMEDGE_R<2> A_IWL<65071> A_IWL<65070> A_IWL<65069> A_IWL<65068> A_IWL<65067> A_IWL<65066> A_IWL<65065> A_IWL<65064> A_IWL<65063> A_IWL<65062> A_IWL<65061> A_IWL<65060> A_IWL<65059> A_IWL<65058> A_IWL<65057> A_IWL<65056> VDD_CORE VSS / RM_IHPSG13_8192x32_c4_1P_BITKIT_16x2_EDGE_LR +XRAMEDGE_R<1> A_IWL<65055> A_IWL<65054> A_IWL<65053> A_IWL<65052> A_IWL<65051> A_IWL<65050> A_IWL<65049> A_IWL<65048> A_IWL<65047> A_IWL<65046> A_IWL<65045> A_IWL<65044> A_IWL<65043> A_IWL<65042> A_IWL<65041> A_IWL<65040> VDD_CORE VSS / RM_IHPSG13_8192x32_c4_1P_BITKIT_16x2_EDGE_LR +XRAMEDGE_R<0> A_IWL<65039> A_IWL<65038> A_IWL<65037> A_IWL<65036> A_IWL<65035> A_IWL<65034> A_IWL<65033> A_IWL<65032> A_IWL<65031> A_IWL<65030> A_IWL<65029> A_IWL<65028> A_IWL<65027> A_IWL<65026> A_IWL<65025> A_IWL<65024> VDD_CORE VSS / RM_IHPSG13_8192x32_c4_1P_BITKIT_16x2_EDGE_LR +XCOL<127> A_BLC<255> A_BLC<254> A_BLC_TOP<255> A_BLC_TOP<254> A_BLT<255> A_BLT<254> A_BLT_TOP<255> A_BLT_TOP<254> A_IWL<65023> A_IWL<65022> A_IWL<65021> A_IWL<65020> A_IWL<65019> A_IWL<65018> A_IWL<65017> A_IWL<65016> A_IWL<65015> A_IWL<65014> A_IWL<65013> A_IWL<65012> A_IWL<65011> A_IWL<65010> A_IWL<65009> A_IWL<65008> A_IWL<65007> A_IWL<65006> A_IWL<65005> A_IWL<65004> A_IWL<65003> A_IWL<65002> A_IWL<65001> A_IWL<65000> A_IWL<64999> A_IWL<64998> A_IWL<64997> A_IWL<64996> A_IWL<64995> A_IWL<64994> A_IWL<64993> A_IWL<64992> A_IWL<64991> A_IWL<64990> A_IWL<64989> A_IWL<64988> A_IWL<64987> A_IWL<64986> A_IWL<64985> A_IWL<64984> A_IWL<64983> A_IWL<64982> A_IWL<64981> A_IWL<64980> A_IWL<64979> A_IWL<64978> A_IWL<64977> A_IWL<64976> A_IWL<64975> A_IWL<64974> A_IWL<64973> A_IWL<64972> A_IWL<64971> A_IWL<64970> A_IWL<64969> A_IWL<64968> A_IWL<64967> A_IWL<64966> A_IWL<64965> A_IWL<64964> A_IWL<64963> A_IWL<64962> A_IWL<64961> A_IWL<64960> A_IWL<64959> A_IWL<64958> A_IWL<64957> A_IWL<64956> A_IWL<64955> A_IWL<64954> A_IWL<64953> A_IWL<64952> A_IWL<64951> A_IWL<64950> A_IWL<64949> A_IWL<64948> A_IWL<64947> A_IWL<64946> A_IWL<64945> A_IWL<64944> A_IWL<64943> A_IWL<64942> A_IWL<64941> A_IWL<64940> A_IWL<64939> A_IWL<64938> A_IWL<64937> A_IWL<64936> A_IWL<64935> A_IWL<64934> A_IWL<64933> A_IWL<64932> A_IWL<64931> A_IWL<64930> A_IWL<64929> A_IWL<64928> A_IWL<64927> A_IWL<64926> A_IWL<64925> A_IWL<64924> A_IWL<64923> A_IWL<64922> A_IWL<64921> A_IWL<64920> A_IWL<64919> A_IWL<64918> A_IWL<64917> A_IWL<64916> A_IWL<64915> A_IWL<64914> A_IWL<64913> A_IWL<64912> A_IWL<64911> A_IWL<64910> A_IWL<64909> A_IWL<64908> A_IWL<64907> A_IWL<64906> A_IWL<64905> A_IWL<64904> A_IWL<64903> A_IWL<64902> A_IWL<64901> A_IWL<64900> A_IWL<64899> A_IWL<64898> A_IWL<64897> A_IWL<64896> A_IWL<64895> A_IWL<64894> A_IWL<64893> A_IWL<64892> A_IWL<64891> A_IWL<64890> A_IWL<64889> A_IWL<64888> A_IWL<64887> A_IWL<64886> A_IWL<64885> A_IWL<64884> A_IWL<64883> A_IWL<64882> A_IWL<64881> A_IWL<64880> A_IWL<64879> A_IWL<64878> A_IWL<64877> A_IWL<64876> A_IWL<64875> A_IWL<64874> A_IWL<64873> A_IWL<64872> A_IWL<64871> A_IWL<64870> A_IWL<64869> A_IWL<64868> A_IWL<64867> A_IWL<64866> A_IWL<64865> A_IWL<64864> A_IWL<64863> A_IWL<64862> A_IWL<64861> A_IWL<64860> A_IWL<64859> A_IWL<64858> A_IWL<64857> A_IWL<64856> A_IWL<64855> A_IWL<64854> A_IWL<64853> A_IWL<64852> A_IWL<64851> A_IWL<64850> A_IWL<64849> A_IWL<64848> A_IWL<64847> A_IWL<64846> A_IWL<64845> A_IWL<64844> A_IWL<64843> A_IWL<64842> A_IWL<64841> A_IWL<64840> A_IWL<64839> A_IWL<64838> A_IWL<64837> A_IWL<64836> A_IWL<64835> A_IWL<64834> A_IWL<64833> A_IWL<64832> A_IWL<64831> A_IWL<64830> A_IWL<64829> A_IWL<64828> A_IWL<64827> A_IWL<64826> A_IWL<64825> A_IWL<64824> A_IWL<64823> A_IWL<64822> A_IWL<64821> A_IWL<64820> A_IWL<64819> A_IWL<64818> A_IWL<64817> A_IWL<64816> A_IWL<64815> A_IWL<64814> A_IWL<64813> A_IWL<64812> A_IWL<64811> A_IWL<64810> A_IWL<64809> A_IWL<64808> A_IWL<64807> A_IWL<64806> A_IWL<64805> A_IWL<64804> A_IWL<64803> A_IWL<64802> A_IWL<64801> A_IWL<64800> A_IWL<64799> A_IWL<64798> A_IWL<64797> A_IWL<64796> A_IWL<64795> A_IWL<64794> A_IWL<64793> A_IWL<64792> A_IWL<64791> A_IWL<64790> A_IWL<64789> A_IWL<64788> A_IWL<64787> A_IWL<64786> A_IWL<64785> A_IWL<64784> A_IWL<64783> A_IWL<64782> A_IWL<64781> A_IWL<64780> A_IWL<64779> A_IWL<64778> A_IWL<64777> A_IWL<64776> A_IWL<64775> A_IWL<64774> A_IWL<64773> A_IWL<64772> A_IWL<64771> A_IWL<64770> A_IWL<64769> A_IWL<64768> A_IWL<64767> A_IWL<64766> A_IWL<64765> A_IWL<64764> A_IWL<64763> A_IWL<64762> A_IWL<64761> A_IWL<64760> A_IWL<64759> A_IWL<64758> A_IWL<64757> A_IWL<64756> A_IWL<64755> A_IWL<64754> A_IWL<64753> A_IWL<64752> A_IWL<64751> A_IWL<64750> A_IWL<64749> A_IWL<64748> A_IWL<64747> A_IWL<64746> A_IWL<64745> A_IWL<64744> A_IWL<64743> A_IWL<64742> A_IWL<64741> A_IWL<64740> A_IWL<64739> A_IWL<64738> A_IWL<64737> A_IWL<64736> A_IWL<64735> A_IWL<64734> A_IWL<64733> A_IWL<64732> A_IWL<64731> A_IWL<64730> A_IWL<64729> A_IWL<64728> A_IWL<64727> A_IWL<64726> A_IWL<64725> A_IWL<64724> A_IWL<64723> A_IWL<64722> A_IWL<64721> A_IWL<64720> A_IWL<64719> A_IWL<64718> A_IWL<64717> A_IWL<64716> A_IWL<64715> A_IWL<64714> A_IWL<64713> A_IWL<64712> A_IWL<64711> A_IWL<64710> A_IWL<64709> A_IWL<64708> A_IWL<64707> A_IWL<64706> A_IWL<64705> A_IWL<64704> A_IWL<64703> A_IWL<64702> A_IWL<64701> A_IWL<64700> A_IWL<64699> A_IWL<64698> A_IWL<64697> A_IWL<64696> A_IWL<64695> A_IWL<64694> A_IWL<64693> A_IWL<64692> A_IWL<64691> A_IWL<64690> A_IWL<64689> A_IWL<64688> A_IWL<64687> A_IWL<64686> A_IWL<64685> A_IWL<64684> A_IWL<64683> A_IWL<64682> A_IWL<64681> A_IWL<64680> A_IWL<64679> A_IWL<64678> A_IWL<64677> A_IWL<64676> A_IWL<64675> A_IWL<64674> A_IWL<64673> A_IWL<64672> A_IWL<64671> A_IWL<64670> A_IWL<64669> A_IWL<64668> A_IWL<64667> A_IWL<64666> A_IWL<64665> A_IWL<64664> A_IWL<64663> A_IWL<64662> A_IWL<64661> A_IWL<64660> A_IWL<64659> A_IWL<64658> A_IWL<64657> A_IWL<64656> A_IWL<64655> A_IWL<64654> A_IWL<64653> A_IWL<64652> A_IWL<64651> A_IWL<64650> A_IWL<64649> A_IWL<64648> A_IWL<64647> A_IWL<64646> A_IWL<64645> A_IWL<64644> A_IWL<64643> A_IWL<64642> A_IWL<64641> A_IWL<64640> A_IWL<64639> A_IWL<64638> A_IWL<64637> A_IWL<64636> A_IWL<64635> A_IWL<64634> A_IWL<64633> A_IWL<64632> A_IWL<64631> A_IWL<64630> A_IWL<64629> A_IWL<64628> A_IWL<64627> A_IWL<64626> A_IWL<64625> A_IWL<64624> A_IWL<64623> A_IWL<64622> A_IWL<64621> A_IWL<64620> A_IWL<64619> A_IWL<64618> A_IWL<64617> A_IWL<64616> A_IWL<64615> A_IWL<64614> A_IWL<64613> A_IWL<64612> A_IWL<64611> A_IWL<64610> A_IWL<64609> A_IWL<64608> A_IWL<64607> A_IWL<64606> A_IWL<64605> A_IWL<64604> A_IWL<64603> A_IWL<64602> A_IWL<64601> A_IWL<64600> A_IWL<64599> A_IWL<64598> A_IWL<64597> A_IWL<64596> A_IWL<64595> A_IWL<64594> A_IWL<64593> A_IWL<64592> A_IWL<64591> A_IWL<64590> A_IWL<64589> A_IWL<64588> A_IWL<64587> A_IWL<64586> A_IWL<64585> A_IWL<64584> A_IWL<64583> A_IWL<64582> A_IWL<64581> A_IWL<64580> A_IWL<64579> A_IWL<64578> A_IWL<64577> A_IWL<64576> A_IWL<64575> A_IWL<64574> A_IWL<64573> A_IWL<64572> A_IWL<64571> A_IWL<64570> A_IWL<64569> A_IWL<64568> A_IWL<64567> A_IWL<64566> A_IWL<64565> A_IWL<64564> A_IWL<64563> A_IWL<64562> A_IWL<64561> A_IWL<64560> A_IWL<64559> A_IWL<64558> A_IWL<64557> A_IWL<64556> A_IWL<64555> A_IWL<64554> A_IWL<64553> A_IWL<64552> A_IWL<64551> A_IWL<64550> A_IWL<64549> A_IWL<64548> A_IWL<64547> A_IWL<64546> A_IWL<64545> A_IWL<64544> A_IWL<64543> A_IWL<64542> A_IWL<64541> A_IWL<64540> A_IWL<64539> A_IWL<64538> A_IWL<64537> A_IWL<64536> A_IWL<64535> A_IWL<64534> A_IWL<64533> A_IWL<64532> A_IWL<64531> A_IWL<64530> A_IWL<64529> A_IWL<64528> A_IWL<64527> A_IWL<64526> A_IWL<64525> A_IWL<64524> A_IWL<64523> A_IWL<64522> A_IWL<64521> A_IWL<64520> A_IWL<64519> A_IWL<64518> A_IWL<64517> A_IWL<64516> A_IWL<64515> A_IWL<64514> A_IWL<64513> A_IWL<64512> A_IWL<65535> A_IWL<65534> A_IWL<65533> A_IWL<65532> A_IWL<65531> A_IWL<65530> A_IWL<65529> A_IWL<65528> A_IWL<65527> A_IWL<65526> A_IWL<65525> A_IWL<65524> A_IWL<65523> A_IWL<65522> A_IWL<65521> A_IWL<65520> A_IWL<65519> A_IWL<65518> A_IWL<65517> A_IWL<65516> A_IWL<65515> A_IWL<65514> A_IWL<65513> A_IWL<65512> A_IWL<65511> A_IWL<65510> A_IWL<65509> A_IWL<65508> A_IWL<65507> A_IWL<65506> A_IWL<65505> A_IWL<65504> A_IWL<65503> A_IWL<65502> A_IWL<65501> A_IWL<65500> A_IWL<65499> A_IWL<65498> A_IWL<65497> A_IWL<65496> A_IWL<65495> A_IWL<65494> A_IWL<65493> A_IWL<65492> A_IWL<65491> A_IWL<65490> A_IWL<65489> A_IWL<65488> A_IWL<65487> A_IWL<65486> A_IWL<65485> A_IWL<65484> A_IWL<65483> A_IWL<65482> A_IWL<65481> A_IWL<65480> A_IWL<65479> A_IWL<65478> A_IWL<65477> A_IWL<65476> A_IWL<65475> A_IWL<65474> A_IWL<65473> A_IWL<65472> A_IWL<65471> A_IWL<65470> A_IWL<65469> A_IWL<65468> A_IWL<65467> A_IWL<65466> A_IWL<65465> A_IWL<65464> A_IWL<65463> A_IWL<65462> A_IWL<65461> A_IWL<65460> A_IWL<65459> A_IWL<65458> A_IWL<65457> A_IWL<65456> A_IWL<65455> A_IWL<65454> A_IWL<65453> A_IWL<65452> A_IWL<65451> A_IWL<65450> A_IWL<65449> A_IWL<65448> A_IWL<65447> A_IWL<65446> A_IWL<65445> A_IWL<65444> A_IWL<65443> A_IWL<65442> A_IWL<65441> A_IWL<65440> A_IWL<65439> A_IWL<65438> A_IWL<65437> A_IWL<65436> A_IWL<65435> A_IWL<65434> A_IWL<65433> A_IWL<65432> A_IWL<65431> A_IWL<65430> A_IWL<65429> A_IWL<65428> A_IWL<65427> A_IWL<65426> A_IWL<65425> A_IWL<65424> A_IWL<65423> A_IWL<65422> A_IWL<65421> A_IWL<65420> A_IWL<65419> A_IWL<65418> A_IWL<65417> A_IWL<65416> A_IWL<65415> A_IWL<65414> A_IWL<65413> A_IWL<65412> A_IWL<65411> A_IWL<65410> A_IWL<65409> A_IWL<65408> A_IWL<65407> A_IWL<65406> A_IWL<65405> A_IWL<65404> A_IWL<65403> A_IWL<65402> A_IWL<65401> A_IWL<65400> A_IWL<65399> A_IWL<65398> A_IWL<65397> A_IWL<65396> A_IWL<65395> A_IWL<65394> A_IWL<65393> A_IWL<65392> A_IWL<65391> A_IWL<65390> A_IWL<65389> A_IWL<65388> A_IWL<65387> A_IWL<65386> A_IWL<65385> A_IWL<65384> A_IWL<65383> A_IWL<65382> A_IWL<65381> A_IWL<65380> A_IWL<65379> A_IWL<65378> A_IWL<65377> A_IWL<65376> A_IWL<65375> A_IWL<65374> A_IWL<65373> A_IWL<65372> A_IWL<65371> A_IWL<65370> A_IWL<65369> A_IWL<65368> A_IWL<65367> A_IWL<65366> A_IWL<65365> A_IWL<65364> A_IWL<65363> A_IWL<65362> A_IWL<65361> A_IWL<65360> A_IWL<65359> A_IWL<65358> A_IWL<65357> A_IWL<65356> A_IWL<65355> A_IWL<65354> A_IWL<65353> A_IWL<65352> A_IWL<65351> A_IWL<65350> A_IWL<65349> A_IWL<65348> A_IWL<65347> A_IWL<65346> A_IWL<65345> A_IWL<65344> A_IWL<65343> A_IWL<65342> A_IWL<65341> A_IWL<65340> A_IWL<65339> A_IWL<65338> A_IWL<65337> A_IWL<65336> A_IWL<65335> A_IWL<65334> A_IWL<65333> A_IWL<65332> A_IWL<65331> A_IWL<65330> A_IWL<65329> A_IWL<65328> A_IWL<65327> A_IWL<65326> A_IWL<65325> A_IWL<65324> A_IWL<65323> A_IWL<65322> A_IWL<65321> A_IWL<65320> A_IWL<65319> A_IWL<65318> A_IWL<65317> A_IWL<65316> A_IWL<65315> A_IWL<65314> A_IWL<65313> A_IWL<65312> A_IWL<65311> A_IWL<65310> A_IWL<65309> A_IWL<65308> A_IWL<65307> A_IWL<65306> A_IWL<65305> A_IWL<65304> A_IWL<65303> A_IWL<65302> A_IWL<65301> A_IWL<65300> A_IWL<65299> A_IWL<65298> A_IWL<65297> A_IWL<65296> A_IWL<65295> A_IWL<65294> A_IWL<65293> A_IWL<65292> A_IWL<65291> A_IWL<65290> A_IWL<65289> A_IWL<65288> A_IWL<65287> A_IWL<65286> A_IWL<65285> A_IWL<65284> A_IWL<65283> A_IWL<65282> A_IWL<65281> A_IWL<65280> A_IWL<65279> A_IWL<65278> A_IWL<65277> A_IWL<65276> A_IWL<65275> A_IWL<65274> A_IWL<65273> A_IWL<65272> A_IWL<65271> A_IWL<65270> A_IWL<65269> A_IWL<65268> A_IWL<65267> A_IWL<65266> A_IWL<65265> A_IWL<65264> A_IWL<65263> A_IWL<65262> A_IWL<65261> A_IWL<65260> A_IWL<65259> A_IWL<65258> A_IWL<65257> A_IWL<65256> A_IWL<65255> A_IWL<65254> A_IWL<65253> A_IWL<65252> A_IWL<65251> A_IWL<65250> A_IWL<65249> A_IWL<65248> A_IWL<65247> A_IWL<65246> A_IWL<65245> A_IWL<65244> A_IWL<65243> A_IWL<65242> A_IWL<65241> A_IWL<65240> A_IWL<65239> A_IWL<65238> A_IWL<65237> A_IWL<65236> A_IWL<65235> A_IWL<65234> A_IWL<65233> A_IWL<65232> A_IWL<65231> A_IWL<65230> A_IWL<65229> A_IWL<65228> A_IWL<65227> A_IWL<65226> A_IWL<65225> A_IWL<65224> A_IWL<65223> A_IWL<65222> A_IWL<65221> A_IWL<65220> A_IWL<65219> A_IWL<65218> A_IWL<65217> A_IWL<65216> A_IWL<65215> A_IWL<65214> A_IWL<65213> A_IWL<65212> A_IWL<65211> A_IWL<65210> A_IWL<65209> A_IWL<65208> A_IWL<65207> A_IWL<65206> A_IWL<65205> A_IWL<65204> A_IWL<65203> A_IWL<65202> A_IWL<65201> A_IWL<65200> A_IWL<65199> A_IWL<65198> A_IWL<65197> A_IWL<65196> A_IWL<65195> A_IWL<65194> A_IWL<65193> A_IWL<65192> A_IWL<65191> A_IWL<65190> A_IWL<65189> A_IWL<65188> A_IWL<65187> A_IWL<65186> A_IWL<65185> A_IWL<65184> A_IWL<65183> A_IWL<65182> A_IWL<65181> A_IWL<65180> A_IWL<65179> A_IWL<65178> A_IWL<65177> A_IWL<65176> A_IWL<65175> A_IWL<65174> A_IWL<65173> A_IWL<65172> A_IWL<65171> A_IWL<65170> A_IWL<65169> A_IWL<65168> A_IWL<65167> A_IWL<65166> A_IWL<65165> A_IWL<65164> A_IWL<65163> A_IWL<65162> A_IWL<65161> A_IWL<65160> A_IWL<65159> A_IWL<65158> A_IWL<65157> A_IWL<65156> A_IWL<65155> A_IWL<65154> A_IWL<65153> A_IWL<65152> A_IWL<65151> A_IWL<65150> A_IWL<65149> A_IWL<65148> A_IWL<65147> A_IWL<65146> A_IWL<65145> A_IWL<65144> A_IWL<65143> A_IWL<65142> A_IWL<65141> A_IWL<65140> A_IWL<65139> A_IWL<65138> A_IWL<65137> A_IWL<65136> A_IWL<65135> A_IWL<65134> A_IWL<65133> A_IWL<65132> A_IWL<65131> A_IWL<65130> A_IWL<65129> A_IWL<65128> A_IWL<65127> A_IWL<65126> A_IWL<65125> A_IWL<65124> A_IWL<65123> A_IWL<65122> A_IWL<65121> A_IWL<65120> A_IWL<65119> A_IWL<65118> A_IWL<65117> A_IWL<65116> A_IWL<65115> A_IWL<65114> A_IWL<65113> A_IWL<65112> A_IWL<65111> A_IWL<65110> A_IWL<65109> A_IWL<65108> A_IWL<65107> A_IWL<65106> A_IWL<65105> A_IWL<65104> A_IWL<65103> A_IWL<65102> A_IWL<65101> A_IWL<65100> A_IWL<65099> A_IWL<65098> A_IWL<65097> A_IWL<65096> A_IWL<65095> A_IWL<65094> A_IWL<65093> A_IWL<65092> A_IWL<65091> A_IWL<65090> A_IWL<65089> A_IWL<65088> A_IWL<65087> A_IWL<65086> A_IWL<65085> A_IWL<65084> A_IWL<65083> A_IWL<65082> A_IWL<65081> A_IWL<65080> A_IWL<65079> A_IWL<65078> A_IWL<65077> A_IWL<65076> A_IWL<65075> A_IWL<65074> A_IWL<65073> A_IWL<65072> A_IWL<65071> A_IWL<65070> A_IWL<65069> A_IWL<65068> A_IWL<65067> A_IWL<65066> A_IWL<65065> A_IWL<65064> A_IWL<65063> A_IWL<65062> A_IWL<65061> A_IWL<65060> A_IWL<65059> A_IWL<65058> A_IWL<65057> A_IWL<65056> A_IWL<65055> A_IWL<65054> A_IWL<65053> A_IWL<65052> A_IWL<65051> A_IWL<65050> A_IWL<65049> A_IWL<65048> A_IWL<65047> A_IWL<65046> A_IWL<65045> A_IWL<65044> A_IWL<65043> A_IWL<65042> A_IWL<65041> A_IWL<65040> A_IWL<65039> A_IWL<65038> A_IWL<65037> A_IWL<65036> A_IWL<65035> A_IWL<65034> A_IWL<65033> A_IWL<65032> A_IWL<65031> A_IWL<65030> A_IWL<65029> A_IWL<65028> A_IWL<65027> A_IWL<65026> A_IWL<65025> A_IWL<65024> VDD_CORE VSS / RM_IHPSG13_8192x32_c4_1P_COLUMN_pcell_0 +XCOL<126> A_BLC<253> A_BLC<252> A_BLC_TOP<253> A_BLC_TOP<252> A_BLT<253> A_BLT<252> A_BLT_TOP<253> A_BLT_TOP<252> A_IWL<64511> A_IWL<64510> A_IWL<64509> A_IWL<64508> A_IWL<64507> A_IWL<64506> A_IWL<64505> A_IWL<64504> A_IWL<64503> A_IWL<64502> A_IWL<64501> A_IWL<64500> A_IWL<64499> A_IWL<64498> A_IWL<64497> A_IWL<64496> A_IWL<64495> A_IWL<64494> A_IWL<64493> A_IWL<64492> A_IWL<64491> A_IWL<64490> A_IWL<64489> A_IWL<64488> A_IWL<64487> A_IWL<64486> A_IWL<64485> A_IWL<64484> A_IWL<64483> A_IWL<64482> A_IWL<64481> A_IWL<64480> A_IWL<64479> A_IWL<64478> A_IWL<64477> A_IWL<64476> A_IWL<64475> A_IWL<64474> A_IWL<64473> A_IWL<64472> A_IWL<64471> A_IWL<64470> A_IWL<64469> A_IWL<64468> A_IWL<64467> A_IWL<64466> A_IWL<64465> A_IWL<64464> A_IWL<64463> A_IWL<64462> A_IWL<64461> A_IWL<64460> A_IWL<64459> A_IWL<64458> A_IWL<64457> A_IWL<64456> A_IWL<64455> A_IWL<64454> A_IWL<64453> A_IWL<64452> A_IWL<64451> A_IWL<64450> A_IWL<64449> A_IWL<64448> A_IWL<64447> A_IWL<64446> A_IWL<64445> A_IWL<64444> A_IWL<64443> A_IWL<64442> A_IWL<64441> A_IWL<64440> A_IWL<64439> A_IWL<64438> A_IWL<64437> A_IWL<64436> A_IWL<64435> A_IWL<64434> A_IWL<64433> A_IWL<64432> A_IWL<64431> A_IWL<64430> A_IWL<64429> A_IWL<64428> A_IWL<64427> A_IWL<64426> A_IWL<64425> A_IWL<64424> A_IWL<64423> A_IWL<64422> A_IWL<64421> A_IWL<64420> A_IWL<64419> A_IWL<64418> A_IWL<64417> A_IWL<64416> A_IWL<64415> A_IWL<64414> A_IWL<64413> A_IWL<64412> A_IWL<64411> A_IWL<64410> A_IWL<64409> A_IWL<64408> A_IWL<64407> A_IWL<64406> A_IWL<64405> A_IWL<64404> A_IWL<64403> A_IWL<64402> A_IWL<64401> A_IWL<64400> A_IWL<64399> A_IWL<64398> A_IWL<64397> A_IWL<64396> A_IWL<64395> A_IWL<64394> A_IWL<64393> A_IWL<64392> A_IWL<64391> A_IWL<64390> A_IWL<64389> A_IWL<64388> A_IWL<64387> A_IWL<64386> A_IWL<64385> A_IWL<64384> A_IWL<64383> A_IWL<64382> A_IWL<64381> A_IWL<64380> A_IWL<64379> A_IWL<64378> A_IWL<64377> A_IWL<64376> A_IWL<64375> A_IWL<64374> A_IWL<64373> A_IWL<64372> A_IWL<64371> A_IWL<64370> A_IWL<64369> A_IWL<64368> A_IWL<64367> A_IWL<64366> A_IWL<64365> A_IWL<64364> A_IWL<64363> A_IWL<64362> A_IWL<64361> A_IWL<64360> A_IWL<64359> A_IWL<64358> A_IWL<64357> A_IWL<64356> A_IWL<64355> A_IWL<64354> A_IWL<64353> A_IWL<64352> A_IWL<64351> A_IWL<64350> A_IWL<64349> A_IWL<64348> A_IWL<64347> A_IWL<64346> A_IWL<64345> A_IWL<64344> A_IWL<64343> A_IWL<64342> A_IWL<64341> A_IWL<64340> A_IWL<64339> A_IWL<64338> A_IWL<64337> A_IWL<64336> A_IWL<64335> A_IWL<64334> A_IWL<64333> A_IWL<64332> A_IWL<64331> A_IWL<64330> A_IWL<64329> A_IWL<64328> A_IWL<64327> A_IWL<64326> A_IWL<64325> A_IWL<64324> A_IWL<64323> A_IWL<64322> A_IWL<64321> A_IWL<64320> A_IWL<64319> A_IWL<64318> A_IWL<64317> A_IWL<64316> A_IWL<64315> A_IWL<64314> A_IWL<64313> A_IWL<64312> A_IWL<64311> A_IWL<64310> A_IWL<64309> A_IWL<64308> A_IWL<64307> A_IWL<64306> A_IWL<64305> A_IWL<64304> A_IWL<64303> A_IWL<64302> A_IWL<64301> A_IWL<64300> A_IWL<64299> A_IWL<64298> A_IWL<64297> A_IWL<64296> A_IWL<64295> A_IWL<64294> A_IWL<64293> A_IWL<64292> A_IWL<64291> A_IWL<64290> A_IWL<64289> A_IWL<64288> A_IWL<64287> A_IWL<64286> A_IWL<64285> A_IWL<64284> A_IWL<64283> A_IWL<64282> A_IWL<64281> A_IWL<64280> A_IWL<64279> A_IWL<64278> A_IWL<64277> A_IWL<64276> A_IWL<64275> A_IWL<64274> A_IWL<64273> A_IWL<64272> A_IWL<64271> A_IWL<64270> A_IWL<64269> A_IWL<64268> A_IWL<64267> A_IWL<64266> A_IWL<64265> A_IWL<64264> A_IWL<64263> A_IWL<64262> A_IWL<64261> A_IWL<64260> A_IWL<64259> A_IWL<64258> A_IWL<64257> A_IWL<64256> A_IWL<64255> A_IWL<64254> A_IWL<64253> A_IWL<64252> A_IWL<64251> A_IWL<64250> A_IWL<64249> A_IWL<64248> A_IWL<64247> A_IWL<64246> A_IWL<64245> A_IWL<64244> A_IWL<64243> A_IWL<64242> A_IWL<64241> A_IWL<64240> A_IWL<64239> A_IWL<64238> A_IWL<64237> A_IWL<64236> A_IWL<64235> A_IWL<64234> A_IWL<64233> A_IWL<64232> A_IWL<64231> A_IWL<64230> A_IWL<64229> A_IWL<64228> A_IWL<64227> A_IWL<64226> A_IWL<64225> A_IWL<64224> A_IWL<64223> A_IWL<64222> A_IWL<64221> A_IWL<64220> A_IWL<64219> A_IWL<64218> A_IWL<64217> A_IWL<64216> A_IWL<64215> A_IWL<64214> A_IWL<64213> A_IWL<64212> A_IWL<64211> A_IWL<64210> A_IWL<64209> A_IWL<64208> A_IWL<64207> A_IWL<64206> A_IWL<64205> A_IWL<64204> A_IWL<64203> A_IWL<64202> A_IWL<64201> A_IWL<64200> A_IWL<64199> A_IWL<64198> A_IWL<64197> A_IWL<64196> A_IWL<64195> A_IWL<64194> A_IWL<64193> A_IWL<64192> A_IWL<64191> A_IWL<64190> A_IWL<64189> A_IWL<64188> A_IWL<64187> A_IWL<64186> A_IWL<64185> A_IWL<64184> A_IWL<64183> A_IWL<64182> A_IWL<64181> A_IWL<64180> A_IWL<64179> A_IWL<64178> A_IWL<64177> A_IWL<64176> A_IWL<64175> A_IWL<64174> A_IWL<64173> A_IWL<64172> A_IWL<64171> A_IWL<64170> A_IWL<64169> A_IWL<64168> A_IWL<64167> A_IWL<64166> A_IWL<64165> A_IWL<64164> A_IWL<64163> A_IWL<64162> A_IWL<64161> A_IWL<64160> A_IWL<64159> A_IWL<64158> A_IWL<64157> A_IWL<64156> A_IWL<64155> A_IWL<64154> A_IWL<64153> A_IWL<64152> A_IWL<64151> A_IWL<64150> A_IWL<64149> A_IWL<64148> A_IWL<64147> A_IWL<64146> A_IWL<64145> A_IWL<64144> A_IWL<64143> A_IWL<64142> A_IWL<64141> A_IWL<64140> A_IWL<64139> A_IWL<64138> A_IWL<64137> A_IWL<64136> A_IWL<64135> A_IWL<64134> A_IWL<64133> A_IWL<64132> A_IWL<64131> A_IWL<64130> A_IWL<64129> A_IWL<64128> A_IWL<64127> A_IWL<64126> A_IWL<64125> A_IWL<64124> A_IWL<64123> A_IWL<64122> A_IWL<64121> A_IWL<64120> A_IWL<64119> A_IWL<64118> A_IWL<64117> A_IWL<64116> A_IWL<64115> A_IWL<64114> A_IWL<64113> A_IWL<64112> A_IWL<64111> A_IWL<64110> A_IWL<64109> A_IWL<64108> A_IWL<64107> A_IWL<64106> A_IWL<64105> A_IWL<64104> A_IWL<64103> A_IWL<64102> A_IWL<64101> A_IWL<64100> A_IWL<64099> A_IWL<64098> A_IWL<64097> A_IWL<64096> A_IWL<64095> A_IWL<64094> A_IWL<64093> A_IWL<64092> A_IWL<64091> A_IWL<64090> A_IWL<64089> A_IWL<64088> A_IWL<64087> A_IWL<64086> A_IWL<64085> A_IWL<64084> A_IWL<64083> A_IWL<64082> A_IWL<64081> A_IWL<64080> A_IWL<64079> A_IWL<64078> A_IWL<64077> A_IWL<64076> A_IWL<64075> A_IWL<64074> A_IWL<64073> A_IWL<64072> A_IWL<64071> A_IWL<64070> A_IWL<64069> A_IWL<64068> A_IWL<64067> A_IWL<64066> A_IWL<64065> A_IWL<64064> A_IWL<64063> A_IWL<64062> A_IWL<64061> A_IWL<64060> A_IWL<64059> A_IWL<64058> A_IWL<64057> A_IWL<64056> A_IWL<64055> A_IWL<64054> A_IWL<64053> A_IWL<64052> A_IWL<64051> A_IWL<64050> A_IWL<64049> A_IWL<64048> A_IWL<64047> A_IWL<64046> A_IWL<64045> A_IWL<64044> A_IWL<64043> A_IWL<64042> A_IWL<64041> A_IWL<64040> A_IWL<64039> A_IWL<64038> A_IWL<64037> A_IWL<64036> A_IWL<64035> A_IWL<64034> A_IWL<64033> A_IWL<64032> A_IWL<64031> A_IWL<64030> A_IWL<64029> A_IWL<64028> A_IWL<64027> A_IWL<64026> A_IWL<64025> A_IWL<64024> A_IWL<64023> A_IWL<64022> A_IWL<64021> A_IWL<64020> A_IWL<64019> A_IWL<64018> A_IWL<64017> A_IWL<64016> A_IWL<64015> A_IWL<64014> A_IWL<64013> A_IWL<64012> A_IWL<64011> A_IWL<64010> A_IWL<64009> A_IWL<64008> A_IWL<64007> A_IWL<64006> A_IWL<64005> A_IWL<64004> A_IWL<64003> A_IWL<64002> A_IWL<64001> A_IWL<64000> A_IWL<65023> A_IWL<65022> A_IWL<65021> A_IWL<65020> A_IWL<65019> A_IWL<65018> A_IWL<65017> A_IWL<65016> A_IWL<65015> A_IWL<65014> A_IWL<65013> A_IWL<65012> A_IWL<65011> A_IWL<65010> A_IWL<65009> A_IWL<65008> A_IWL<65007> A_IWL<65006> A_IWL<65005> A_IWL<65004> A_IWL<65003> A_IWL<65002> A_IWL<65001> A_IWL<65000> A_IWL<64999> A_IWL<64998> A_IWL<64997> A_IWL<64996> A_IWL<64995> A_IWL<64994> A_IWL<64993> A_IWL<64992> A_IWL<64991> A_IWL<64990> A_IWL<64989> A_IWL<64988> A_IWL<64987> A_IWL<64986> A_IWL<64985> A_IWL<64984> A_IWL<64983> A_IWL<64982> A_IWL<64981> A_IWL<64980> A_IWL<64979> A_IWL<64978> A_IWL<64977> A_IWL<64976> A_IWL<64975> A_IWL<64974> A_IWL<64973> A_IWL<64972> A_IWL<64971> A_IWL<64970> A_IWL<64969> A_IWL<64968> A_IWL<64967> A_IWL<64966> A_IWL<64965> A_IWL<64964> A_IWL<64963> A_IWL<64962> A_IWL<64961> A_IWL<64960> A_IWL<64959> A_IWL<64958> A_IWL<64957> A_IWL<64956> A_IWL<64955> A_IWL<64954> A_IWL<64953> A_IWL<64952> A_IWL<64951> A_IWL<64950> A_IWL<64949> A_IWL<64948> A_IWL<64947> A_IWL<64946> A_IWL<64945> A_IWL<64944> A_IWL<64943> A_IWL<64942> A_IWL<64941> A_IWL<64940> A_IWL<64939> A_IWL<64938> A_IWL<64937> A_IWL<64936> A_IWL<64935> A_IWL<64934> A_IWL<64933> A_IWL<64932> A_IWL<64931> A_IWL<64930> A_IWL<64929> A_IWL<64928> A_IWL<64927> A_IWL<64926> A_IWL<64925> A_IWL<64924> A_IWL<64923> A_IWL<64922> A_IWL<64921> A_IWL<64920> A_IWL<64919> A_IWL<64918> A_IWL<64917> A_IWL<64916> A_IWL<64915> A_IWL<64914> A_IWL<64913> A_IWL<64912> A_IWL<64911> A_IWL<64910> A_IWL<64909> A_IWL<64908> A_IWL<64907> A_IWL<64906> A_IWL<64905> A_IWL<64904> A_IWL<64903> A_IWL<64902> A_IWL<64901> A_IWL<64900> A_IWL<64899> A_IWL<64898> A_IWL<64897> A_IWL<64896> A_IWL<64895> A_IWL<64894> A_IWL<64893> A_IWL<64892> A_IWL<64891> A_IWL<64890> A_IWL<64889> A_IWL<64888> A_IWL<64887> A_IWL<64886> A_IWL<64885> A_IWL<64884> A_IWL<64883> A_IWL<64882> A_IWL<64881> A_IWL<64880> A_IWL<64879> A_IWL<64878> A_IWL<64877> A_IWL<64876> A_IWL<64875> A_IWL<64874> A_IWL<64873> A_IWL<64872> A_IWL<64871> A_IWL<64870> A_IWL<64869> A_IWL<64868> A_IWL<64867> A_IWL<64866> A_IWL<64865> A_IWL<64864> A_IWL<64863> A_IWL<64862> A_IWL<64861> A_IWL<64860> A_IWL<64859> A_IWL<64858> A_IWL<64857> A_IWL<64856> A_IWL<64855> A_IWL<64854> A_IWL<64853> A_IWL<64852> A_IWL<64851> A_IWL<64850> A_IWL<64849> A_IWL<64848> A_IWL<64847> A_IWL<64846> A_IWL<64845> A_IWL<64844> A_IWL<64843> A_IWL<64842> A_IWL<64841> A_IWL<64840> A_IWL<64839> A_IWL<64838> A_IWL<64837> A_IWL<64836> A_IWL<64835> A_IWL<64834> A_IWL<64833> A_IWL<64832> A_IWL<64831> A_IWL<64830> A_IWL<64829> A_IWL<64828> A_IWL<64827> A_IWL<64826> A_IWL<64825> A_IWL<64824> A_IWL<64823> A_IWL<64822> A_IWL<64821> A_IWL<64820> A_IWL<64819> A_IWL<64818> A_IWL<64817> A_IWL<64816> A_IWL<64815> A_IWL<64814> A_IWL<64813> A_IWL<64812> A_IWL<64811> A_IWL<64810> A_IWL<64809> A_IWL<64808> A_IWL<64807> A_IWL<64806> A_IWL<64805> A_IWL<64804> A_IWL<64803> A_IWL<64802> A_IWL<64801> A_IWL<64800> A_IWL<64799> A_IWL<64798> A_IWL<64797> A_IWL<64796> A_IWL<64795> A_IWL<64794> A_IWL<64793> A_IWL<64792> A_IWL<64791> A_IWL<64790> A_IWL<64789> A_IWL<64788> A_IWL<64787> A_IWL<64786> A_IWL<64785> A_IWL<64784> A_IWL<64783> A_IWL<64782> A_IWL<64781> A_IWL<64780> A_IWL<64779> A_IWL<64778> A_IWL<64777> A_IWL<64776> A_IWL<64775> A_IWL<64774> A_IWL<64773> A_IWL<64772> A_IWL<64771> A_IWL<64770> A_IWL<64769> A_IWL<64768> A_IWL<64767> A_IWL<64766> A_IWL<64765> A_IWL<64764> A_IWL<64763> A_IWL<64762> A_IWL<64761> A_IWL<64760> A_IWL<64759> A_IWL<64758> A_IWL<64757> A_IWL<64756> A_IWL<64755> A_IWL<64754> A_IWL<64753> A_IWL<64752> A_IWL<64751> A_IWL<64750> A_IWL<64749> A_IWL<64748> A_IWL<64747> A_IWL<64746> A_IWL<64745> A_IWL<64744> A_IWL<64743> A_IWL<64742> A_IWL<64741> A_IWL<64740> A_IWL<64739> A_IWL<64738> A_IWL<64737> A_IWL<64736> A_IWL<64735> A_IWL<64734> A_IWL<64733> A_IWL<64732> A_IWL<64731> A_IWL<64730> A_IWL<64729> A_IWL<64728> A_IWL<64727> A_IWL<64726> A_IWL<64725> A_IWL<64724> A_IWL<64723> A_IWL<64722> A_IWL<64721> A_IWL<64720> A_IWL<64719> A_IWL<64718> A_IWL<64717> A_IWL<64716> A_IWL<64715> A_IWL<64714> A_IWL<64713> A_IWL<64712> A_IWL<64711> A_IWL<64710> A_IWL<64709> A_IWL<64708> A_IWL<64707> A_IWL<64706> A_IWL<64705> A_IWL<64704> A_IWL<64703> A_IWL<64702> A_IWL<64701> A_IWL<64700> A_IWL<64699> A_IWL<64698> A_IWL<64697> A_IWL<64696> A_IWL<64695> A_IWL<64694> A_IWL<64693> A_IWL<64692> A_IWL<64691> A_IWL<64690> A_IWL<64689> A_IWL<64688> A_IWL<64687> A_IWL<64686> A_IWL<64685> A_IWL<64684> A_IWL<64683> A_IWL<64682> A_IWL<64681> A_IWL<64680> A_IWL<64679> A_IWL<64678> A_IWL<64677> A_IWL<64676> A_IWL<64675> A_IWL<64674> A_IWL<64673> A_IWL<64672> A_IWL<64671> A_IWL<64670> A_IWL<64669> A_IWL<64668> A_IWL<64667> A_IWL<64666> A_IWL<64665> A_IWL<64664> A_IWL<64663> A_IWL<64662> A_IWL<64661> A_IWL<64660> A_IWL<64659> A_IWL<64658> A_IWL<64657> A_IWL<64656> A_IWL<64655> A_IWL<64654> A_IWL<64653> A_IWL<64652> A_IWL<64651> A_IWL<64650> A_IWL<64649> A_IWL<64648> A_IWL<64647> A_IWL<64646> A_IWL<64645> A_IWL<64644> A_IWL<64643> A_IWL<64642> A_IWL<64641> A_IWL<64640> A_IWL<64639> A_IWL<64638> A_IWL<64637> A_IWL<64636> A_IWL<64635> A_IWL<64634> A_IWL<64633> A_IWL<64632> A_IWL<64631> A_IWL<64630> A_IWL<64629> A_IWL<64628> A_IWL<64627> A_IWL<64626> A_IWL<64625> A_IWL<64624> A_IWL<64623> A_IWL<64622> A_IWL<64621> A_IWL<64620> A_IWL<64619> A_IWL<64618> A_IWL<64617> A_IWL<64616> A_IWL<64615> A_IWL<64614> A_IWL<64613> A_IWL<64612> A_IWL<64611> A_IWL<64610> A_IWL<64609> A_IWL<64608> A_IWL<64607> A_IWL<64606> A_IWL<64605> A_IWL<64604> A_IWL<64603> A_IWL<64602> A_IWL<64601> A_IWL<64600> A_IWL<64599> A_IWL<64598> A_IWL<64597> A_IWL<64596> A_IWL<64595> A_IWL<64594> A_IWL<64593> A_IWL<64592> A_IWL<64591> A_IWL<64590> A_IWL<64589> A_IWL<64588> A_IWL<64587> A_IWL<64586> A_IWL<64585> A_IWL<64584> A_IWL<64583> A_IWL<64582> A_IWL<64581> A_IWL<64580> A_IWL<64579> A_IWL<64578> A_IWL<64577> A_IWL<64576> A_IWL<64575> A_IWL<64574> A_IWL<64573> A_IWL<64572> A_IWL<64571> A_IWL<64570> A_IWL<64569> A_IWL<64568> A_IWL<64567> A_IWL<64566> A_IWL<64565> A_IWL<64564> A_IWL<64563> A_IWL<64562> A_IWL<64561> A_IWL<64560> A_IWL<64559> A_IWL<64558> A_IWL<64557> A_IWL<64556> A_IWL<64555> A_IWL<64554> A_IWL<64553> A_IWL<64552> A_IWL<64551> A_IWL<64550> A_IWL<64549> A_IWL<64548> A_IWL<64547> A_IWL<64546> A_IWL<64545> A_IWL<64544> A_IWL<64543> A_IWL<64542> A_IWL<64541> A_IWL<64540> A_IWL<64539> A_IWL<64538> A_IWL<64537> A_IWL<64536> A_IWL<64535> A_IWL<64534> A_IWL<64533> A_IWL<64532> A_IWL<64531> A_IWL<64530> A_IWL<64529> A_IWL<64528> A_IWL<64527> A_IWL<64526> A_IWL<64525> A_IWL<64524> A_IWL<64523> A_IWL<64522> A_IWL<64521> A_IWL<64520> A_IWL<64519> A_IWL<64518> A_IWL<64517> A_IWL<64516> A_IWL<64515> A_IWL<64514> A_IWL<64513> A_IWL<64512> VDD_CORE VSS / RM_IHPSG13_8192x32_c4_1P_COLUMN_pcell_0 +XCOL<125> A_BLC<251> A_BLC<250> A_BLC_TOP<251> A_BLC_TOP<250> A_BLT<251> A_BLT<250> A_BLT_TOP<251> A_BLT_TOP<250> A_IWL<63999> A_IWL<63998> A_IWL<63997> A_IWL<63996> A_IWL<63995> A_IWL<63994> A_IWL<63993> A_IWL<63992> A_IWL<63991> A_IWL<63990> A_IWL<63989> A_IWL<63988> A_IWL<63987> A_IWL<63986> A_IWL<63985> A_IWL<63984> A_IWL<63983> A_IWL<63982> A_IWL<63981> A_IWL<63980> A_IWL<63979> A_IWL<63978> A_IWL<63977> A_IWL<63976> A_IWL<63975> A_IWL<63974> A_IWL<63973> A_IWL<63972> A_IWL<63971> A_IWL<63970> A_IWL<63969> A_IWL<63968> A_IWL<63967> A_IWL<63966> A_IWL<63965> A_IWL<63964> A_IWL<63963> A_IWL<63962> A_IWL<63961> A_IWL<63960> A_IWL<63959> A_IWL<63958> A_IWL<63957> A_IWL<63956> A_IWL<63955> A_IWL<63954> A_IWL<63953> A_IWL<63952> A_IWL<63951> A_IWL<63950> A_IWL<63949> A_IWL<63948> A_IWL<63947> A_IWL<63946> A_IWL<63945> A_IWL<63944> A_IWL<63943> A_IWL<63942> A_IWL<63941> A_IWL<63940> A_IWL<63939> A_IWL<63938> A_IWL<63937> A_IWL<63936> A_IWL<63935> A_IWL<63934> A_IWL<63933> A_IWL<63932> A_IWL<63931> A_IWL<63930> A_IWL<63929> A_IWL<63928> A_IWL<63927> A_IWL<63926> A_IWL<63925> A_IWL<63924> A_IWL<63923> A_IWL<63922> A_IWL<63921> A_IWL<63920> A_IWL<63919> A_IWL<63918> A_IWL<63917> A_IWL<63916> A_IWL<63915> A_IWL<63914> A_IWL<63913> A_IWL<63912> A_IWL<63911> A_IWL<63910> A_IWL<63909> A_IWL<63908> A_IWL<63907> A_IWL<63906> A_IWL<63905> A_IWL<63904> A_IWL<63903> A_IWL<63902> A_IWL<63901> A_IWL<63900> A_IWL<63899> A_IWL<63898> A_IWL<63897> A_IWL<63896> A_IWL<63895> A_IWL<63894> A_IWL<63893> A_IWL<63892> A_IWL<63891> A_IWL<63890> A_IWL<63889> A_IWL<63888> A_IWL<63887> A_IWL<63886> A_IWL<63885> A_IWL<63884> A_IWL<63883> A_IWL<63882> A_IWL<63881> A_IWL<63880> A_IWL<63879> A_IWL<63878> A_IWL<63877> A_IWL<63876> A_IWL<63875> A_IWL<63874> A_IWL<63873> A_IWL<63872> A_IWL<63871> A_IWL<63870> A_IWL<63869> A_IWL<63868> A_IWL<63867> A_IWL<63866> A_IWL<63865> A_IWL<63864> A_IWL<63863> A_IWL<63862> A_IWL<63861> A_IWL<63860> A_IWL<63859> A_IWL<63858> A_IWL<63857> A_IWL<63856> A_IWL<63855> A_IWL<63854> A_IWL<63853> A_IWL<63852> A_IWL<63851> A_IWL<63850> A_IWL<63849> A_IWL<63848> A_IWL<63847> A_IWL<63846> A_IWL<63845> A_IWL<63844> A_IWL<63843> A_IWL<63842> A_IWL<63841> A_IWL<63840> A_IWL<63839> A_IWL<63838> A_IWL<63837> A_IWL<63836> A_IWL<63835> A_IWL<63834> A_IWL<63833> A_IWL<63832> A_IWL<63831> A_IWL<63830> A_IWL<63829> A_IWL<63828> A_IWL<63827> A_IWL<63826> A_IWL<63825> A_IWL<63824> A_IWL<63823> A_IWL<63822> A_IWL<63821> A_IWL<63820> A_IWL<63819> A_IWL<63818> A_IWL<63817> A_IWL<63816> A_IWL<63815> A_IWL<63814> A_IWL<63813> A_IWL<63812> A_IWL<63811> A_IWL<63810> A_IWL<63809> A_IWL<63808> A_IWL<63807> A_IWL<63806> A_IWL<63805> A_IWL<63804> A_IWL<63803> A_IWL<63802> A_IWL<63801> A_IWL<63800> A_IWL<63799> A_IWL<63798> A_IWL<63797> A_IWL<63796> A_IWL<63795> A_IWL<63794> A_IWL<63793> A_IWL<63792> A_IWL<63791> A_IWL<63790> A_IWL<63789> A_IWL<63788> A_IWL<63787> A_IWL<63786> A_IWL<63785> A_IWL<63784> A_IWL<63783> A_IWL<63782> A_IWL<63781> A_IWL<63780> A_IWL<63779> A_IWL<63778> A_IWL<63777> A_IWL<63776> A_IWL<63775> A_IWL<63774> A_IWL<63773> A_IWL<63772> A_IWL<63771> A_IWL<63770> A_IWL<63769> A_IWL<63768> A_IWL<63767> A_IWL<63766> A_IWL<63765> A_IWL<63764> A_IWL<63763> A_IWL<63762> A_IWL<63761> A_IWL<63760> A_IWL<63759> A_IWL<63758> A_IWL<63757> A_IWL<63756> A_IWL<63755> A_IWL<63754> A_IWL<63753> A_IWL<63752> A_IWL<63751> A_IWL<63750> A_IWL<63749> A_IWL<63748> A_IWL<63747> A_IWL<63746> A_IWL<63745> A_IWL<63744> A_IWL<63743> A_IWL<63742> A_IWL<63741> A_IWL<63740> A_IWL<63739> A_IWL<63738> A_IWL<63737> A_IWL<63736> A_IWL<63735> A_IWL<63734> A_IWL<63733> A_IWL<63732> A_IWL<63731> A_IWL<63730> A_IWL<63729> A_IWL<63728> A_IWL<63727> A_IWL<63726> A_IWL<63725> A_IWL<63724> A_IWL<63723> A_IWL<63722> A_IWL<63721> A_IWL<63720> A_IWL<63719> A_IWL<63718> A_IWL<63717> A_IWL<63716> A_IWL<63715> A_IWL<63714> A_IWL<63713> A_IWL<63712> A_IWL<63711> A_IWL<63710> A_IWL<63709> A_IWL<63708> A_IWL<63707> A_IWL<63706> A_IWL<63705> A_IWL<63704> A_IWL<63703> A_IWL<63702> A_IWL<63701> A_IWL<63700> A_IWL<63699> A_IWL<63698> A_IWL<63697> A_IWL<63696> A_IWL<63695> A_IWL<63694> A_IWL<63693> A_IWL<63692> A_IWL<63691> A_IWL<63690> A_IWL<63689> A_IWL<63688> A_IWL<63687> A_IWL<63686> A_IWL<63685> A_IWL<63684> A_IWL<63683> A_IWL<63682> A_IWL<63681> A_IWL<63680> A_IWL<63679> A_IWL<63678> A_IWL<63677> A_IWL<63676> A_IWL<63675> A_IWL<63674> A_IWL<63673> A_IWL<63672> A_IWL<63671> A_IWL<63670> A_IWL<63669> A_IWL<63668> A_IWL<63667> A_IWL<63666> A_IWL<63665> A_IWL<63664> A_IWL<63663> A_IWL<63662> A_IWL<63661> A_IWL<63660> A_IWL<63659> A_IWL<63658> A_IWL<63657> A_IWL<63656> A_IWL<63655> A_IWL<63654> A_IWL<63653> A_IWL<63652> A_IWL<63651> A_IWL<63650> A_IWL<63649> A_IWL<63648> A_IWL<63647> A_IWL<63646> A_IWL<63645> A_IWL<63644> A_IWL<63643> A_IWL<63642> A_IWL<63641> A_IWL<63640> A_IWL<63639> A_IWL<63638> A_IWL<63637> A_IWL<63636> A_IWL<63635> A_IWL<63634> A_IWL<63633> A_IWL<63632> A_IWL<63631> A_IWL<63630> A_IWL<63629> A_IWL<63628> A_IWL<63627> A_IWL<63626> A_IWL<63625> A_IWL<63624> A_IWL<63623> A_IWL<63622> A_IWL<63621> A_IWL<63620> A_IWL<63619> A_IWL<63618> A_IWL<63617> A_IWL<63616> A_IWL<63615> A_IWL<63614> A_IWL<63613> A_IWL<63612> A_IWL<63611> A_IWL<63610> A_IWL<63609> A_IWL<63608> A_IWL<63607> A_IWL<63606> A_IWL<63605> A_IWL<63604> A_IWL<63603> A_IWL<63602> A_IWL<63601> A_IWL<63600> A_IWL<63599> A_IWL<63598> A_IWL<63597> A_IWL<63596> A_IWL<63595> A_IWL<63594> A_IWL<63593> A_IWL<63592> A_IWL<63591> A_IWL<63590> A_IWL<63589> A_IWL<63588> A_IWL<63587> A_IWL<63586> A_IWL<63585> A_IWL<63584> A_IWL<63583> A_IWL<63582> A_IWL<63581> A_IWL<63580> A_IWL<63579> A_IWL<63578> A_IWL<63577> A_IWL<63576> A_IWL<63575> A_IWL<63574> A_IWL<63573> A_IWL<63572> A_IWL<63571> A_IWL<63570> A_IWL<63569> A_IWL<63568> A_IWL<63567> A_IWL<63566> A_IWL<63565> A_IWL<63564> A_IWL<63563> A_IWL<63562> A_IWL<63561> A_IWL<63560> A_IWL<63559> A_IWL<63558> A_IWL<63557> A_IWL<63556> A_IWL<63555> A_IWL<63554> A_IWL<63553> A_IWL<63552> A_IWL<63551> A_IWL<63550> A_IWL<63549> A_IWL<63548> A_IWL<63547> A_IWL<63546> A_IWL<63545> A_IWL<63544> A_IWL<63543> A_IWL<63542> A_IWL<63541> A_IWL<63540> A_IWL<63539> A_IWL<63538> A_IWL<63537> A_IWL<63536> A_IWL<63535> A_IWL<63534> A_IWL<63533> A_IWL<63532> A_IWL<63531> A_IWL<63530> A_IWL<63529> A_IWL<63528> A_IWL<63527> A_IWL<63526> A_IWL<63525> A_IWL<63524> A_IWL<63523> A_IWL<63522> A_IWL<63521> A_IWL<63520> A_IWL<63519> A_IWL<63518> A_IWL<63517> A_IWL<63516> A_IWL<63515> A_IWL<63514> A_IWL<63513> A_IWL<63512> A_IWL<63511> A_IWL<63510> A_IWL<63509> A_IWL<63508> A_IWL<63507> A_IWL<63506> A_IWL<63505> A_IWL<63504> A_IWL<63503> A_IWL<63502> A_IWL<63501> A_IWL<63500> A_IWL<63499> A_IWL<63498> A_IWL<63497> A_IWL<63496> A_IWL<63495> A_IWL<63494> A_IWL<63493> A_IWL<63492> A_IWL<63491> A_IWL<63490> A_IWL<63489> A_IWL<63488> A_IWL<64511> A_IWL<64510> A_IWL<64509> A_IWL<64508> A_IWL<64507> A_IWL<64506> A_IWL<64505> A_IWL<64504> A_IWL<64503> A_IWL<64502> A_IWL<64501> A_IWL<64500> A_IWL<64499> A_IWL<64498> A_IWL<64497> A_IWL<64496> A_IWL<64495> A_IWL<64494> A_IWL<64493> A_IWL<64492> A_IWL<64491> A_IWL<64490> A_IWL<64489> A_IWL<64488> A_IWL<64487> A_IWL<64486> A_IWL<64485> A_IWL<64484> A_IWL<64483> A_IWL<64482> A_IWL<64481> A_IWL<64480> A_IWL<64479> A_IWL<64478> A_IWL<64477> A_IWL<64476> A_IWL<64475> A_IWL<64474> A_IWL<64473> A_IWL<64472> A_IWL<64471> A_IWL<64470> A_IWL<64469> A_IWL<64468> A_IWL<64467> A_IWL<64466> A_IWL<64465> A_IWL<64464> A_IWL<64463> A_IWL<64462> A_IWL<64461> A_IWL<64460> A_IWL<64459> A_IWL<64458> A_IWL<64457> A_IWL<64456> A_IWL<64455> A_IWL<64454> A_IWL<64453> A_IWL<64452> A_IWL<64451> A_IWL<64450> A_IWL<64449> A_IWL<64448> A_IWL<64447> A_IWL<64446> A_IWL<64445> A_IWL<64444> A_IWL<64443> A_IWL<64442> A_IWL<64441> A_IWL<64440> A_IWL<64439> A_IWL<64438> A_IWL<64437> A_IWL<64436> A_IWL<64435> A_IWL<64434> A_IWL<64433> A_IWL<64432> A_IWL<64431> A_IWL<64430> A_IWL<64429> A_IWL<64428> A_IWL<64427> A_IWL<64426> A_IWL<64425> A_IWL<64424> A_IWL<64423> A_IWL<64422> A_IWL<64421> A_IWL<64420> A_IWL<64419> A_IWL<64418> A_IWL<64417> A_IWL<64416> A_IWL<64415> A_IWL<64414> A_IWL<64413> A_IWL<64412> A_IWL<64411> A_IWL<64410> A_IWL<64409> A_IWL<64408> A_IWL<64407> A_IWL<64406> A_IWL<64405> A_IWL<64404> A_IWL<64403> A_IWL<64402> A_IWL<64401> A_IWL<64400> A_IWL<64399> A_IWL<64398> A_IWL<64397> A_IWL<64396> A_IWL<64395> A_IWL<64394> A_IWL<64393> A_IWL<64392> A_IWL<64391> A_IWL<64390> A_IWL<64389> A_IWL<64388> A_IWL<64387> A_IWL<64386> A_IWL<64385> A_IWL<64384> A_IWL<64383> A_IWL<64382> A_IWL<64381> A_IWL<64380> A_IWL<64379> A_IWL<64378> A_IWL<64377> A_IWL<64376> A_IWL<64375> A_IWL<64374> A_IWL<64373> A_IWL<64372> A_IWL<64371> A_IWL<64370> A_IWL<64369> A_IWL<64368> A_IWL<64367> A_IWL<64366> A_IWL<64365> A_IWL<64364> A_IWL<64363> A_IWL<64362> A_IWL<64361> A_IWL<64360> A_IWL<64359> A_IWL<64358> A_IWL<64357> A_IWL<64356> A_IWL<64355> A_IWL<64354> A_IWL<64353> A_IWL<64352> A_IWL<64351> A_IWL<64350> A_IWL<64349> A_IWL<64348> A_IWL<64347> A_IWL<64346> A_IWL<64345> A_IWL<64344> A_IWL<64343> A_IWL<64342> A_IWL<64341> A_IWL<64340> A_IWL<64339> A_IWL<64338> A_IWL<64337> A_IWL<64336> A_IWL<64335> A_IWL<64334> A_IWL<64333> A_IWL<64332> A_IWL<64331> A_IWL<64330> A_IWL<64329> A_IWL<64328> A_IWL<64327> A_IWL<64326> A_IWL<64325> A_IWL<64324> A_IWL<64323> A_IWL<64322> A_IWL<64321> A_IWL<64320> A_IWL<64319> A_IWL<64318> A_IWL<64317> A_IWL<64316> A_IWL<64315> A_IWL<64314> A_IWL<64313> A_IWL<64312> A_IWL<64311> A_IWL<64310> A_IWL<64309> A_IWL<64308> A_IWL<64307> A_IWL<64306> A_IWL<64305> A_IWL<64304> A_IWL<64303> A_IWL<64302> A_IWL<64301> A_IWL<64300> A_IWL<64299> A_IWL<64298> A_IWL<64297> A_IWL<64296> A_IWL<64295> A_IWL<64294> A_IWL<64293> A_IWL<64292> A_IWL<64291> A_IWL<64290> A_IWL<64289> A_IWL<64288> A_IWL<64287> A_IWL<64286> A_IWL<64285> A_IWL<64284> A_IWL<64283> A_IWL<64282> A_IWL<64281> A_IWL<64280> A_IWL<64279> A_IWL<64278> A_IWL<64277> A_IWL<64276> A_IWL<64275> A_IWL<64274> A_IWL<64273> A_IWL<64272> A_IWL<64271> A_IWL<64270> A_IWL<64269> A_IWL<64268> A_IWL<64267> A_IWL<64266> A_IWL<64265> A_IWL<64264> A_IWL<64263> A_IWL<64262> A_IWL<64261> A_IWL<64260> A_IWL<64259> A_IWL<64258> A_IWL<64257> A_IWL<64256> A_IWL<64255> A_IWL<64254> A_IWL<64253> A_IWL<64252> A_IWL<64251> A_IWL<64250> A_IWL<64249> A_IWL<64248> A_IWL<64247> A_IWL<64246> A_IWL<64245> A_IWL<64244> A_IWL<64243> A_IWL<64242> A_IWL<64241> A_IWL<64240> A_IWL<64239> A_IWL<64238> A_IWL<64237> A_IWL<64236> A_IWL<64235> A_IWL<64234> A_IWL<64233> A_IWL<64232> A_IWL<64231> A_IWL<64230> A_IWL<64229> A_IWL<64228> A_IWL<64227> A_IWL<64226> A_IWL<64225> A_IWL<64224> A_IWL<64223> A_IWL<64222> A_IWL<64221> A_IWL<64220> A_IWL<64219> A_IWL<64218> A_IWL<64217> A_IWL<64216> A_IWL<64215> A_IWL<64214> A_IWL<64213> A_IWL<64212> A_IWL<64211> A_IWL<64210> A_IWL<64209> A_IWL<64208> A_IWL<64207> A_IWL<64206> A_IWL<64205> A_IWL<64204> A_IWL<64203> A_IWL<64202> A_IWL<64201> A_IWL<64200> A_IWL<64199> A_IWL<64198> A_IWL<64197> A_IWL<64196> A_IWL<64195> A_IWL<64194> A_IWL<64193> A_IWL<64192> A_IWL<64191> A_IWL<64190> A_IWL<64189> A_IWL<64188> A_IWL<64187> A_IWL<64186> A_IWL<64185> A_IWL<64184> A_IWL<64183> A_IWL<64182> A_IWL<64181> A_IWL<64180> A_IWL<64179> A_IWL<64178> A_IWL<64177> A_IWL<64176> A_IWL<64175> A_IWL<64174> A_IWL<64173> A_IWL<64172> A_IWL<64171> A_IWL<64170> A_IWL<64169> A_IWL<64168> A_IWL<64167> A_IWL<64166> A_IWL<64165> A_IWL<64164> A_IWL<64163> A_IWL<64162> A_IWL<64161> A_IWL<64160> A_IWL<64159> A_IWL<64158> A_IWL<64157> A_IWL<64156> A_IWL<64155> A_IWL<64154> A_IWL<64153> A_IWL<64152> A_IWL<64151> A_IWL<64150> A_IWL<64149> A_IWL<64148> A_IWL<64147> A_IWL<64146> A_IWL<64145> A_IWL<64144> A_IWL<64143> A_IWL<64142> A_IWL<64141> A_IWL<64140> A_IWL<64139> A_IWL<64138> A_IWL<64137> A_IWL<64136> A_IWL<64135> A_IWL<64134> A_IWL<64133> A_IWL<64132> A_IWL<64131> A_IWL<64130> A_IWL<64129> A_IWL<64128> A_IWL<64127> A_IWL<64126> A_IWL<64125> A_IWL<64124> A_IWL<64123> A_IWL<64122> A_IWL<64121> A_IWL<64120> A_IWL<64119> A_IWL<64118> A_IWL<64117> A_IWL<64116> A_IWL<64115> A_IWL<64114> A_IWL<64113> A_IWL<64112> A_IWL<64111> A_IWL<64110> A_IWL<64109> A_IWL<64108> A_IWL<64107> A_IWL<64106> A_IWL<64105> A_IWL<64104> A_IWL<64103> A_IWL<64102> A_IWL<64101> A_IWL<64100> A_IWL<64099> A_IWL<64098> A_IWL<64097> A_IWL<64096> A_IWL<64095> A_IWL<64094> A_IWL<64093> A_IWL<64092> A_IWL<64091> A_IWL<64090> A_IWL<64089> A_IWL<64088> A_IWL<64087> A_IWL<64086> A_IWL<64085> A_IWL<64084> A_IWL<64083> A_IWL<64082> A_IWL<64081> A_IWL<64080> A_IWL<64079> A_IWL<64078> A_IWL<64077> A_IWL<64076> A_IWL<64075> A_IWL<64074> A_IWL<64073> A_IWL<64072> A_IWL<64071> A_IWL<64070> A_IWL<64069> A_IWL<64068> A_IWL<64067> A_IWL<64066> A_IWL<64065> A_IWL<64064> A_IWL<64063> A_IWL<64062> A_IWL<64061> A_IWL<64060> A_IWL<64059> A_IWL<64058> A_IWL<64057> A_IWL<64056> A_IWL<64055> A_IWL<64054> A_IWL<64053> A_IWL<64052> A_IWL<64051> A_IWL<64050> A_IWL<64049> A_IWL<64048> A_IWL<64047> A_IWL<64046> A_IWL<64045> A_IWL<64044> A_IWL<64043> A_IWL<64042> A_IWL<64041> A_IWL<64040> A_IWL<64039> A_IWL<64038> A_IWL<64037> A_IWL<64036> A_IWL<64035> A_IWL<64034> A_IWL<64033> A_IWL<64032> A_IWL<64031> A_IWL<64030> A_IWL<64029> A_IWL<64028> A_IWL<64027> A_IWL<64026> A_IWL<64025> A_IWL<64024> A_IWL<64023> A_IWL<64022> A_IWL<64021> A_IWL<64020> A_IWL<64019> A_IWL<64018> A_IWL<64017> A_IWL<64016> A_IWL<64015> A_IWL<64014> A_IWL<64013> A_IWL<64012> A_IWL<64011> A_IWL<64010> A_IWL<64009> A_IWL<64008> A_IWL<64007> A_IWL<64006> A_IWL<64005> A_IWL<64004> A_IWL<64003> A_IWL<64002> A_IWL<64001> A_IWL<64000> VDD_CORE VSS / RM_IHPSG13_8192x32_c4_1P_COLUMN_pcell_0 +XCOL<124> A_BLC<249> A_BLC<248> A_BLC_TOP<249> A_BLC_TOP<248> A_BLT<249> A_BLT<248> A_BLT_TOP<249> A_BLT_TOP<248> A_IWL<63487> A_IWL<63486> A_IWL<63485> A_IWL<63484> A_IWL<63483> A_IWL<63482> A_IWL<63481> A_IWL<63480> A_IWL<63479> A_IWL<63478> A_IWL<63477> A_IWL<63476> A_IWL<63475> A_IWL<63474> A_IWL<63473> A_IWL<63472> A_IWL<63471> A_IWL<63470> A_IWL<63469> A_IWL<63468> A_IWL<63467> A_IWL<63466> A_IWL<63465> A_IWL<63464> A_IWL<63463> A_IWL<63462> A_IWL<63461> A_IWL<63460> A_IWL<63459> A_IWL<63458> A_IWL<63457> A_IWL<63456> A_IWL<63455> A_IWL<63454> A_IWL<63453> A_IWL<63452> A_IWL<63451> A_IWL<63450> A_IWL<63449> A_IWL<63448> A_IWL<63447> A_IWL<63446> A_IWL<63445> A_IWL<63444> A_IWL<63443> A_IWL<63442> A_IWL<63441> A_IWL<63440> A_IWL<63439> A_IWL<63438> A_IWL<63437> A_IWL<63436> A_IWL<63435> A_IWL<63434> A_IWL<63433> A_IWL<63432> A_IWL<63431> A_IWL<63430> A_IWL<63429> A_IWL<63428> A_IWL<63427> A_IWL<63426> A_IWL<63425> A_IWL<63424> A_IWL<63423> A_IWL<63422> A_IWL<63421> A_IWL<63420> A_IWL<63419> A_IWL<63418> A_IWL<63417> A_IWL<63416> A_IWL<63415> A_IWL<63414> A_IWL<63413> A_IWL<63412> A_IWL<63411> A_IWL<63410> A_IWL<63409> A_IWL<63408> A_IWL<63407> A_IWL<63406> A_IWL<63405> A_IWL<63404> A_IWL<63403> A_IWL<63402> A_IWL<63401> A_IWL<63400> A_IWL<63399> A_IWL<63398> A_IWL<63397> A_IWL<63396> A_IWL<63395> A_IWL<63394> A_IWL<63393> A_IWL<63392> A_IWL<63391> A_IWL<63390> A_IWL<63389> A_IWL<63388> A_IWL<63387> A_IWL<63386> A_IWL<63385> A_IWL<63384> A_IWL<63383> A_IWL<63382> A_IWL<63381> A_IWL<63380> A_IWL<63379> A_IWL<63378> A_IWL<63377> A_IWL<63376> A_IWL<63375> A_IWL<63374> A_IWL<63373> A_IWL<63372> A_IWL<63371> A_IWL<63370> A_IWL<63369> A_IWL<63368> A_IWL<63367> A_IWL<63366> A_IWL<63365> A_IWL<63364> A_IWL<63363> A_IWL<63362> A_IWL<63361> A_IWL<63360> A_IWL<63359> A_IWL<63358> A_IWL<63357> A_IWL<63356> A_IWL<63355> A_IWL<63354> A_IWL<63353> A_IWL<63352> A_IWL<63351> A_IWL<63350> A_IWL<63349> A_IWL<63348> A_IWL<63347> A_IWL<63346> A_IWL<63345> A_IWL<63344> A_IWL<63343> A_IWL<63342> A_IWL<63341> A_IWL<63340> A_IWL<63339> A_IWL<63338> A_IWL<63337> A_IWL<63336> A_IWL<63335> A_IWL<63334> A_IWL<63333> A_IWL<63332> A_IWL<63331> A_IWL<63330> A_IWL<63329> A_IWL<63328> A_IWL<63327> A_IWL<63326> A_IWL<63325> A_IWL<63324> A_IWL<63323> A_IWL<63322> A_IWL<63321> A_IWL<63320> A_IWL<63319> A_IWL<63318> A_IWL<63317> A_IWL<63316> A_IWL<63315> A_IWL<63314> A_IWL<63313> A_IWL<63312> A_IWL<63311> A_IWL<63310> A_IWL<63309> A_IWL<63308> A_IWL<63307> A_IWL<63306> A_IWL<63305> A_IWL<63304> A_IWL<63303> A_IWL<63302> A_IWL<63301> A_IWL<63300> A_IWL<63299> A_IWL<63298> A_IWL<63297> A_IWL<63296> A_IWL<63295> A_IWL<63294> A_IWL<63293> A_IWL<63292> A_IWL<63291> A_IWL<63290> A_IWL<63289> A_IWL<63288> A_IWL<63287> A_IWL<63286> A_IWL<63285> A_IWL<63284> A_IWL<63283> A_IWL<63282> A_IWL<63281> A_IWL<63280> A_IWL<63279> A_IWL<63278> A_IWL<63277> A_IWL<63276> A_IWL<63275> A_IWL<63274> A_IWL<63273> A_IWL<63272> A_IWL<63271> A_IWL<63270> A_IWL<63269> A_IWL<63268> A_IWL<63267> A_IWL<63266> A_IWL<63265> A_IWL<63264> A_IWL<63263> A_IWL<63262> A_IWL<63261> A_IWL<63260> A_IWL<63259> A_IWL<63258> A_IWL<63257> A_IWL<63256> A_IWL<63255> A_IWL<63254> A_IWL<63253> A_IWL<63252> A_IWL<63251> A_IWL<63250> A_IWL<63249> A_IWL<63248> A_IWL<63247> A_IWL<63246> A_IWL<63245> A_IWL<63244> A_IWL<63243> A_IWL<63242> A_IWL<63241> A_IWL<63240> A_IWL<63239> A_IWL<63238> A_IWL<63237> A_IWL<63236> A_IWL<63235> A_IWL<63234> A_IWL<63233> A_IWL<63232> A_IWL<63231> A_IWL<63230> A_IWL<63229> A_IWL<63228> A_IWL<63227> A_IWL<63226> A_IWL<63225> A_IWL<63224> A_IWL<63223> A_IWL<63222> A_IWL<63221> A_IWL<63220> A_IWL<63219> A_IWL<63218> A_IWL<63217> A_IWL<63216> A_IWL<63215> A_IWL<63214> A_IWL<63213> A_IWL<63212> A_IWL<63211> A_IWL<63210> A_IWL<63209> A_IWL<63208> A_IWL<63207> A_IWL<63206> A_IWL<63205> A_IWL<63204> A_IWL<63203> A_IWL<63202> A_IWL<63201> A_IWL<63200> A_IWL<63199> A_IWL<63198> A_IWL<63197> A_IWL<63196> A_IWL<63195> A_IWL<63194> A_IWL<63193> A_IWL<63192> A_IWL<63191> A_IWL<63190> A_IWL<63189> A_IWL<63188> A_IWL<63187> A_IWL<63186> A_IWL<63185> A_IWL<63184> A_IWL<63183> A_IWL<63182> A_IWL<63181> A_IWL<63180> A_IWL<63179> A_IWL<63178> A_IWL<63177> A_IWL<63176> A_IWL<63175> A_IWL<63174> A_IWL<63173> A_IWL<63172> A_IWL<63171> A_IWL<63170> A_IWL<63169> A_IWL<63168> A_IWL<63167> A_IWL<63166> A_IWL<63165> A_IWL<63164> A_IWL<63163> A_IWL<63162> A_IWL<63161> A_IWL<63160> A_IWL<63159> A_IWL<63158> A_IWL<63157> A_IWL<63156> A_IWL<63155> A_IWL<63154> A_IWL<63153> A_IWL<63152> A_IWL<63151> A_IWL<63150> A_IWL<63149> A_IWL<63148> A_IWL<63147> A_IWL<63146> A_IWL<63145> A_IWL<63144> A_IWL<63143> A_IWL<63142> A_IWL<63141> A_IWL<63140> A_IWL<63139> A_IWL<63138> A_IWL<63137> A_IWL<63136> A_IWL<63135> A_IWL<63134> A_IWL<63133> A_IWL<63132> A_IWL<63131> A_IWL<63130> A_IWL<63129> A_IWL<63128> A_IWL<63127> A_IWL<63126> A_IWL<63125> A_IWL<63124> A_IWL<63123> A_IWL<63122> A_IWL<63121> A_IWL<63120> A_IWL<63119> A_IWL<63118> A_IWL<63117> A_IWL<63116> A_IWL<63115> A_IWL<63114> A_IWL<63113> A_IWL<63112> A_IWL<63111> A_IWL<63110> A_IWL<63109> A_IWL<63108> A_IWL<63107> A_IWL<63106> A_IWL<63105> A_IWL<63104> A_IWL<63103> A_IWL<63102> A_IWL<63101> A_IWL<63100> A_IWL<63099> A_IWL<63098> A_IWL<63097> A_IWL<63096> A_IWL<63095> A_IWL<63094> A_IWL<63093> A_IWL<63092> A_IWL<63091> A_IWL<63090> A_IWL<63089> A_IWL<63088> A_IWL<63087> A_IWL<63086> A_IWL<63085> A_IWL<63084> A_IWL<63083> A_IWL<63082> A_IWL<63081> A_IWL<63080> A_IWL<63079> A_IWL<63078> A_IWL<63077> A_IWL<63076> A_IWL<63075> A_IWL<63074> A_IWL<63073> A_IWL<63072> A_IWL<63071> A_IWL<63070> A_IWL<63069> A_IWL<63068> A_IWL<63067> A_IWL<63066> A_IWL<63065> A_IWL<63064> A_IWL<63063> A_IWL<63062> A_IWL<63061> A_IWL<63060> A_IWL<63059> A_IWL<63058> A_IWL<63057> A_IWL<63056> A_IWL<63055> A_IWL<63054> A_IWL<63053> A_IWL<63052> A_IWL<63051> A_IWL<63050> A_IWL<63049> A_IWL<63048> A_IWL<63047> A_IWL<63046> A_IWL<63045> A_IWL<63044> A_IWL<63043> A_IWL<63042> A_IWL<63041> A_IWL<63040> A_IWL<63039> A_IWL<63038> A_IWL<63037> A_IWL<63036> A_IWL<63035> A_IWL<63034> A_IWL<63033> A_IWL<63032> A_IWL<63031> A_IWL<63030> A_IWL<63029> A_IWL<63028> A_IWL<63027> A_IWL<63026> A_IWL<63025> A_IWL<63024> A_IWL<63023> A_IWL<63022> A_IWL<63021> A_IWL<63020> A_IWL<63019> A_IWL<63018> A_IWL<63017> A_IWL<63016> A_IWL<63015> A_IWL<63014> A_IWL<63013> A_IWL<63012> A_IWL<63011> A_IWL<63010> A_IWL<63009> A_IWL<63008> A_IWL<63007> A_IWL<63006> A_IWL<63005> A_IWL<63004> A_IWL<63003> A_IWL<63002> A_IWL<63001> A_IWL<63000> A_IWL<62999> A_IWL<62998> A_IWL<62997> A_IWL<62996> A_IWL<62995> A_IWL<62994> A_IWL<62993> A_IWL<62992> A_IWL<62991> A_IWL<62990> A_IWL<62989> A_IWL<62988> A_IWL<62987> A_IWL<62986> A_IWL<62985> A_IWL<62984> A_IWL<62983> A_IWL<62982> A_IWL<62981> A_IWL<62980> A_IWL<62979> A_IWL<62978> A_IWL<62977> A_IWL<62976> A_IWL<63999> A_IWL<63998> A_IWL<63997> A_IWL<63996> A_IWL<63995> A_IWL<63994> A_IWL<63993> A_IWL<63992> A_IWL<63991> A_IWL<63990> A_IWL<63989> A_IWL<63988> A_IWL<63987> A_IWL<63986> A_IWL<63985> A_IWL<63984> A_IWL<63983> A_IWL<63982> A_IWL<63981> A_IWL<63980> A_IWL<63979> A_IWL<63978> A_IWL<63977> A_IWL<63976> A_IWL<63975> A_IWL<63974> A_IWL<63973> A_IWL<63972> A_IWL<63971> A_IWL<63970> A_IWL<63969> A_IWL<63968> A_IWL<63967> A_IWL<63966> A_IWL<63965> A_IWL<63964> A_IWL<63963> A_IWL<63962> A_IWL<63961> A_IWL<63960> A_IWL<63959> A_IWL<63958> A_IWL<63957> A_IWL<63956> A_IWL<63955> A_IWL<63954> A_IWL<63953> A_IWL<63952> A_IWL<63951> A_IWL<63950> A_IWL<63949> A_IWL<63948> A_IWL<63947> A_IWL<63946> A_IWL<63945> A_IWL<63944> A_IWL<63943> A_IWL<63942> A_IWL<63941> A_IWL<63940> A_IWL<63939> A_IWL<63938> A_IWL<63937> A_IWL<63936> A_IWL<63935> A_IWL<63934> A_IWL<63933> A_IWL<63932> A_IWL<63931> A_IWL<63930> A_IWL<63929> A_IWL<63928> A_IWL<63927> A_IWL<63926> A_IWL<63925> A_IWL<63924> A_IWL<63923> A_IWL<63922> A_IWL<63921> A_IWL<63920> A_IWL<63919> A_IWL<63918> A_IWL<63917> A_IWL<63916> A_IWL<63915> A_IWL<63914> A_IWL<63913> A_IWL<63912> A_IWL<63911> A_IWL<63910> A_IWL<63909> A_IWL<63908> A_IWL<63907> A_IWL<63906> A_IWL<63905> A_IWL<63904> A_IWL<63903> A_IWL<63902> A_IWL<63901> A_IWL<63900> A_IWL<63899> A_IWL<63898> A_IWL<63897> A_IWL<63896> A_IWL<63895> A_IWL<63894> A_IWL<63893> A_IWL<63892> A_IWL<63891> A_IWL<63890> A_IWL<63889> A_IWL<63888> A_IWL<63887> A_IWL<63886> A_IWL<63885> A_IWL<63884> A_IWL<63883> A_IWL<63882> A_IWL<63881> A_IWL<63880> A_IWL<63879> A_IWL<63878> A_IWL<63877> A_IWL<63876> A_IWL<63875> A_IWL<63874> A_IWL<63873> A_IWL<63872> A_IWL<63871> A_IWL<63870> A_IWL<63869> A_IWL<63868> A_IWL<63867> A_IWL<63866> A_IWL<63865> A_IWL<63864> A_IWL<63863> A_IWL<63862> A_IWL<63861> A_IWL<63860> A_IWL<63859> A_IWL<63858> A_IWL<63857> A_IWL<63856> A_IWL<63855> A_IWL<63854> A_IWL<63853> A_IWL<63852> A_IWL<63851> A_IWL<63850> A_IWL<63849> A_IWL<63848> A_IWL<63847> A_IWL<63846> A_IWL<63845> A_IWL<63844> A_IWL<63843> A_IWL<63842> A_IWL<63841> A_IWL<63840> A_IWL<63839> A_IWL<63838> A_IWL<63837> A_IWL<63836> A_IWL<63835> A_IWL<63834> A_IWL<63833> A_IWL<63832> A_IWL<63831> A_IWL<63830> A_IWL<63829> A_IWL<63828> A_IWL<63827> A_IWL<63826> A_IWL<63825> A_IWL<63824> A_IWL<63823> A_IWL<63822> A_IWL<63821> A_IWL<63820> A_IWL<63819> A_IWL<63818> A_IWL<63817> A_IWL<63816> A_IWL<63815> A_IWL<63814> A_IWL<63813> A_IWL<63812> A_IWL<63811> A_IWL<63810> A_IWL<63809> A_IWL<63808> A_IWL<63807> A_IWL<63806> A_IWL<63805> A_IWL<63804> A_IWL<63803> A_IWL<63802> A_IWL<63801> A_IWL<63800> A_IWL<63799> A_IWL<63798> A_IWL<63797> A_IWL<63796> A_IWL<63795> A_IWL<63794> A_IWL<63793> A_IWL<63792> A_IWL<63791> A_IWL<63790> A_IWL<63789> A_IWL<63788> A_IWL<63787> A_IWL<63786> A_IWL<63785> A_IWL<63784> A_IWL<63783> A_IWL<63782> A_IWL<63781> A_IWL<63780> A_IWL<63779> A_IWL<63778> A_IWL<63777> A_IWL<63776> A_IWL<63775> A_IWL<63774> A_IWL<63773> A_IWL<63772> A_IWL<63771> A_IWL<63770> A_IWL<63769> A_IWL<63768> A_IWL<63767> A_IWL<63766> A_IWL<63765> A_IWL<63764> A_IWL<63763> A_IWL<63762> A_IWL<63761> A_IWL<63760> A_IWL<63759> A_IWL<63758> A_IWL<63757> A_IWL<63756> A_IWL<63755> A_IWL<63754> A_IWL<63753> A_IWL<63752> A_IWL<63751> A_IWL<63750> A_IWL<63749> A_IWL<63748> A_IWL<63747> A_IWL<63746> A_IWL<63745> A_IWL<63744> A_IWL<63743> A_IWL<63742> A_IWL<63741> A_IWL<63740> A_IWL<63739> A_IWL<63738> A_IWL<63737> A_IWL<63736> A_IWL<63735> A_IWL<63734> A_IWL<63733> A_IWL<63732> A_IWL<63731> A_IWL<63730> A_IWL<63729> A_IWL<63728> A_IWL<63727> A_IWL<63726> A_IWL<63725> A_IWL<63724> A_IWL<63723> A_IWL<63722> A_IWL<63721> A_IWL<63720> A_IWL<63719> A_IWL<63718> A_IWL<63717> A_IWL<63716> A_IWL<63715> A_IWL<63714> A_IWL<63713> A_IWL<63712> A_IWL<63711> A_IWL<63710> A_IWL<63709> A_IWL<63708> A_IWL<63707> A_IWL<63706> A_IWL<63705> A_IWL<63704> A_IWL<63703> A_IWL<63702> A_IWL<63701> A_IWL<63700> A_IWL<63699> A_IWL<63698> A_IWL<63697> A_IWL<63696> A_IWL<63695> A_IWL<63694> A_IWL<63693> A_IWL<63692> A_IWL<63691> A_IWL<63690> A_IWL<63689> A_IWL<63688> A_IWL<63687> A_IWL<63686> A_IWL<63685> A_IWL<63684> A_IWL<63683> A_IWL<63682> A_IWL<63681> A_IWL<63680> A_IWL<63679> A_IWL<63678> A_IWL<63677> A_IWL<63676> A_IWL<63675> A_IWL<63674> A_IWL<63673> A_IWL<63672> A_IWL<63671> A_IWL<63670> A_IWL<63669> A_IWL<63668> A_IWL<63667> A_IWL<63666> A_IWL<63665> A_IWL<63664> A_IWL<63663> A_IWL<63662> A_IWL<63661> A_IWL<63660> A_IWL<63659> A_IWL<63658> A_IWL<63657> A_IWL<63656> A_IWL<63655> A_IWL<63654> A_IWL<63653> A_IWL<63652> A_IWL<63651> A_IWL<63650> A_IWL<63649> A_IWL<63648> A_IWL<63647> A_IWL<63646> A_IWL<63645> A_IWL<63644> A_IWL<63643> A_IWL<63642> A_IWL<63641> A_IWL<63640> A_IWL<63639> A_IWL<63638> A_IWL<63637> A_IWL<63636> A_IWL<63635> A_IWL<63634> A_IWL<63633> A_IWL<63632> A_IWL<63631> A_IWL<63630> A_IWL<63629> A_IWL<63628> A_IWL<63627> A_IWL<63626> A_IWL<63625> A_IWL<63624> A_IWL<63623> A_IWL<63622> A_IWL<63621> A_IWL<63620> A_IWL<63619> A_IWL<63618> A_IWL<63617> A_IWL<63616> A_IWL<63615> A_IWL<63614> A_IWL<63613> A_IWL<63612> A_IWL<63611> A_IWL<63610> A_IWL<63609> A_IWL<63608> A_IWL<63607> A_IWL<63606> A_IWL<63605> A_IWL<63604> A_IWL<63603> A_IWL<63602> A_IWL<63601> A_IWL<63600> A_IWL<63599> A_IWL<63598> A_IWL<63597> A_IWL<63596> A_IWL<63595> A_IWL<63594> A_IWL<63593> A_IWL<63592> A_IWL<63591> A_IWL<63590> A_IWL<63589> A_IWL<63588> A_IWL<63587> A_IWL<63586> A_IWL<63585> A_IWL<63584> A_IWL<63583> A_IWL<63582> A_IWL<63581> A_IWL<63580> A_IWL<63579> A_IWL<63578> A_IWL<63577> A_IWL<63576> A_IWL<63575> A_IWL<63574> A_IWL<63573> A_IWL<63572> A_IWL<63571> A_IWL<63570> A_IWL<63569> A_IWL<63568> A_IWL<63567> A_IWL<63566> A_IWL<63565> A_IWL<63564> A_IWL<63563> A_IWL<63562> A_IWL<63561> A_IWL<63560> A_IWL<63559> A_IWL<63558> A_IWL<63557> A_IWL<63556> A_IWL<63555> A_IWL<63554> A_IWL<63553> A_IWL<63552> A_IWL<63551> A_IWL<63550> A_IWL<63549> A_IWL<63548> A_IWL<63547> A_IWL<63546> A_IWL<63545> A_IWL<63544> A_IWL<63543> A_IWL<63542> A_IWL<63541> A_IWL<63540> A_IWL<63539> A_IWL<63538> A_IWL<63537> A_IWL<63536> A_IWL<63535> A_IWL<63534> A_IWL<63533> A_IWL<63532> A_IWL<63531> A_IWL<63530> A_IWL<63529> A_IWL<63528> A_IWL<63527> A_IWL<63526> A_IWL<63525> A_IWL<63524> A_IWL<63523> A_IWL<63522> A_IWL<63521> A_IWL<63520> A_IWL<63519> A_IWL<63518> A_IWL<63517> A_IWL<63516> A_IWL<63515> A_IWL<63514> A_IWL<63513> A_IWL<63512> A_IWL<63511> A_IWL<63510> A_IWL<63509> A_IWL<63508> A_IWL<63507> A_IWL<63506> A_IWL<63505> A_IWL<63504> A_IWL<63503> A_IWL<63502> A_IWL<63501> A_IWL<63500> A_IWL<63499> A_IWL<63498> A_IWL<63497> A_IWL<63496> A_IWL<63495> A_IWL<63494> A_IWL<63493> A_IWL<63492> A_IWL<63491> A_IWL<63490> A_IWL<63489> A_IWL<63488> VDD_CORE VSS / RM_IHPSG13_8192x32_c4_1P_COLUMN_pcell_0 +XCOL<123> A_BLC<247> A_BLC<246> A_BLC_TOP<247> A_BLC_TOP<246> A_BLT<247> A_BLT<246> A_BLT_TOP<247> A_BLT_TOP<246> A_IWL<62975> A_IWL<62974> A_IWL<62973> A_IWL<62972> A_IWL<62971> A_IWL<62970> A_IWL<62969> A_IWL<62968> A_IWL<62967> A_IWL<62966> A_IWL<62965> A_IWL<62964> A_IWL<62963> A_IWL<62962> A_IWL<62961> A_IWL<62960> A_IWL<62959> A_IWL<62958> A_IWL<62957> A_IWL<62956> A_IWL<62955> A_IWL<62954> A_IWL<62953> A_IWL<62952> A_IWL<62951> A_IWL<62950> A_IWL<62949> A_IWL<62948> A_IWL<62947> A_IWL<62946> A_IWL<62945> A_IWL<62944> A_IWL<62943> A_IWL<62942> A_IWL<62941> A_IWL<62940> A_IWL<62939> A_IWL<62938> A_IWL<62937> A_IWL<62936> A_IWL<62935> A_IWL<62934> A_IWL<62933> A_IWL<62932> A_IWL<62931> A_IWL<62930> A_IWL<62929> A_IWL<62928> A_IWL<62927> A_IWL<62926> A_IWL<62925> A_IWL<62924> A_IWL<62923> A_IWL<62922> A_IWL<62921> A_IWL<62920> A_IWL<62919> A_IWL<62918> A_IWL<62917> A_IWL<62916> A_IWL<62915> A_IWL<62914> A_IWL<62913> A_IWL<62912> A_IWL<62911> A_IWL<62910> A_IWL<62909> A_IWL<62908> A_IWL<62907> A_IWL<62906> A_IWL<62905> A_IWL<62904> A_IWL<62903> A_IWL<62902> A_IWL<62901> A_IWL<62900> A_IWL<62899> A_IWL<62898> A_IWL<62897> A_IWL<62896> A_IWL<62895> A_IWL<62894> A_IWL<62893> A_IWL<62892> A_IWL<62891> A_IWL<62890> A_IWL<62889> A_IWL<62888> A_IWL<62887> A_IWL<62886> A_IWL<62885> A_IWL<62884> A_IWL<62883> A_IWL<62882> A_IWL<62881> A_IWL<62880> A_IWL<62879> A_IWL<62878> A_IWL<62877> A_IWL<62876> A_IWL<62875> A_IWL<62874> A_IWL<62873> A_IWL<62872> A_IWL<62871> A_IWL<62870> A_IWL<62869> A_IWL<62868> A_IWL<62867> A_IWL<62866> A_IWL<62865> A_IWL<62864> A_IWL<62863> A_IWL<62862> A_IWL<62861> A_IWL<62860> A_IWL<62859> A_IWL<62858> A_IWL<62857> A_IWL<62856> A_IWL<62855> A_IWL<62854> A_IWL<62853> A_IWL<62852> A_IWL<62851> A_IWL<62850> A_IWL<62849> A_IWL<62848> A_IWL<62847> A_IWL<62846> A_IWL<62845> A_IWL<62844> A_IWL<62843> A_IWL<62842> A_IWL<62841> A_IWL<62840> A_IWL<62839> A_IWL<62838> A_IWL<62837> A_IWL<62836> A_IWL<62835> A_IWL<62834> A_IWL<62833> A_IWL<62832> A_IWL<62831> A_IWL<62830> A_IWL<62829> A_IWL<62828> A_IWL<62827> A_IWL<62826> A_IWL<62825> A_IWL<62824> A_IWL<62823> A_IWL<62822> A_IWL<62821> A_IWL<62820> A_IWL<62819> A_IWL<62818> A_IWL<62817> A_IWL<62816> A_IWL<62815> A_IWL<62814> A_IWL<62813> A_IWL<62812> A_IWL<62811> A_IWL<62810> A_IWL<62809> A_IWL<62808> A_IWL<62807> A_IWL<62806> A_IWL<62805> A_IWL<62804> A_IWL<62803> A_IWL<62802> A_IWL<62801> A_IWL<62800> A_IWL<62799> A_IWL<62798> A_IWL<62797> A_IWL<62796> A_IWL<62795> A_IWL<62794> A_IWL<62793> A_IWL<62792> A_IWL<62791> A_IWL<62790> A_IWL<62789> A_IWL<62788> A_IWL<62787> A_IWL<62786> A_IWL<62785> A_IWL<62784> A_IWL<62783> A_IWL<62782> A_IWL<62781> A_IWL<62780> A_IWL<62779> A_IWL<62778> A_IWL<62777> A_IWL<62776> A_IWL<62775> A_IWL<62774> A_IWL<62773> A_IWL<62772> A_IWL<62771> A_IWL<62770> A_IWL<62769> A_IWL<62768> A_IWL<62767> A_IWL<62766> A_IWL<62765> A_IWL<62764> A_IWL<62763> A_IWL<62762> A_IWL<62761> A_IWL<62760> A_IWL<62759> A_IWL<62758> A_IWL<62757> A_IWL<62756> A_IWL<62755> A_IWL<62754> A_IWL<62753> A_IWL<62752> A_IWL<62751> A_IWL<62750> A_IWL<62749> A_IWL<62748> A_IWL<62747> A_IWL<62746> A_IWL<62745> A_IWL<62744> A_IWL<62743> A_IWL<62742> A_IWL<62741> A_IWL<62740> A_IWL<62739> A_IWL<62738> A_IWL<62737> A_IWL<62736> A_IWL<62735> A_IWL<62734> A_IWL<62733> A_IWL<62732> A_IWL<62731> A_IWL<62730> A_IWL<62729> A_IWL<62728> A_IWL<62727> A_IWL<62726> A_IWL<62725> A_IWL<62724> A_IWL<62723> A_IWL<62722> A_IWL<62721> A_IWL<62720> A_IWL<62719> A_IWL<62718> A_IWL<62717> A_IWL<62716> A_IWL<62715> A_IWL<62714> A_IWL<62713> A_IWL<62712> A_IWL<62711> A_IWL<62710> A_IWL<62709> A_IWL<62708> A_IWL<62707> A_IWL<62706> A_IWL<62705> A_IWL<62704> A_IWL<62703> A_IWL<62702> A_IWL<62701> A_IWL<62700> A_IWL<62699> A_IWL<62698> A_IWL<62697> A_IWL<62696> A_IWL<62695> A_IWL<62694> A_IWL<62693> A_IWL<62692> A_IWL<62691> A_IWL<62690> A_IWL<62689> A_IWL<62688> A_IWL<62687> A_IWL<62686> A_IWL<62685> A_IWL<62684> A_IWL<62683> A_IWL<62682> A_IWL<62681> A_IWL<62680> A_IWL<62679> A_IWL<62678> A_IWL<62677> A_IWL<62676> A_IWL<62675> A_IWL<62674> A_IWL<62673> A_IWL<62672> A_IWL<62671> A_IWL<62670> A_IWL<62669> A_IWL<62668> A_IWL<62667> A_IWL<62666> A_IWL<62665> A_IWL<62664> A_IWL<62663> A_IWL<62662> A_IWL<62661> A_IWL<62660> A_IWL<62659> A_IWL<62658> A_IWL<62657> A_IWL<62656> A_IWL<62655> A_IWL<62654> A_IWL<62653> A_IWL<62652> A_IWL<62651> A_IWL<62650> A_IWL<62649> A_IWL<62648> A_IWL<62647> A_IWL<62646> A_IWL<62645> A_IWL<62644> A_IWL<62643> A_IWL<62642> A_IWL<62641> A_IWL<62640> A_IWL<62639> A_IWL<62638> A_IWL<62637> A_IWL<62636> A_IWL<62635> A_IWL<62634> A_IWL<62633> A_IWL<62632> A_IWL<62631> A_IWL<62630> A_IWL<62629> A_IWL<62628> A_IWL<62627> A_IWL<62626> A_IWL<62625> A_IWL<62624> A_IWL<62623> A_IWL<62622> A_IWL<62621> A_IWL<62620> A_IWL<62619> A_IWL<62618> A_IWL<62617> A_IWL<62616> A_IWL<62615> A_IWL<62614> A_IWL<62613> A_IWL<62612> A_IWL<62611> A_IWL<62610> A_IWL<62609> A_IWL<62608> A_IWL<62607> A_IWL<62606> A_IWL<62605> A_IWL<62604> A_IWL<62603> A_IWL<62602> A_IWL<62601> A_IWL<62600> A_IWL<62599> A_IWL<62598> A_IWL<62597> A_IWL<62596> A_IWL<62595> A_IWL<62594> A_IWL<62593> A_IWL<62592> A_IWL<62591> A_IWL<62590> A_IWL<62589> A_IWL<62588> A_IWL<62587> A_IWL<62586> A_IWL<62585> A_IWL<62584> A_IWL<62583> A_IWL<62582> A_IWL<62581> A_IWL<62580> A_IWL<62579> A_IWL<62578> A_IWL<62577> A_IWL<62576> A_IWL<62575> A_IWL<62574> A_IWL<62573> A_IWL<62572> A_IWL<62571> A_IWL<62570> A_IWL<62569> A_IWL<62568> A_IWL<62567> A_IWL<62566> A_IWL<62565> A_IWL<62564> A_IWL<62563> A_IWL<62562> A_IWL<62561> A_IWL<62560> A_IWL<62559> A_IWL<62558> A_IWL<62557> A_IWL<62556> A_IWL<62555> A_IWL<62554> A_IWL<62553> A_IWL<62552> A_IWL<62551> A_IWL<62550> A_IWL<62549> A_IWL<62548> A_IWL<62547> A_IWL<62546> A_IWL<62545> A_IWL<62544> A_IWL<62543> A_IWL<62542> A_IWL<62541> A_IWL<62540> A_IWL<62539> A_IWL<62538> A_IWL<62537> A_IWL<62536> A_IWL<62535> A_IWL<62534> A_IWL<62533> A_IWL<62532> A_IWL<62531> A_IWL<62530> A_IWL<62529> A_IWL<62528> A_IWL<62527> A_IWL<62526> A_IWL<62525> A_IWL<62524> A_IWL<62523> A_IWL<62522> A_IWL<62521> A_IWL<62520> A_IWL<62519> A_IWL<62518> A_IWL<62517> A_IWL<62516> A_IWL<62515> A_IWL<62514> A_IWL<62513> A_IWL<62512> A_IWL<62511> A_IWL<62510> A_IWL<62509> A_IWL<62508> A_IWL<62507> A_IWL<62506> A_IWL<62505> A_IWL<62504> A_IWL<62503> A_IWL<62502> A_IWL<62501> A_IWL<62500> A_IWL<62499> A_IWL<62498> A_IWL<62497> A_IWL<62496> A_IWL<62495> A_IWL<62494> A_IWL<62493> A_IWL<62492> A_IWL<62491> A_IWL<62490> A_IWL<62489> A_IWL<62488> A_IWL<62487> A_IWL<62486> A_IWL<62485> A_IWL<62484> A_IWL<62483> A_IWL<62482> A_IWL<62481> A_IWL<62480> A_IWL<62479> A_IWL<62478> A_IWL<62477> A_IWL<62476> A_IWL<62475> A_IWL<62474> A_IWL<62473> A_IWL<62472> A_IWL<62471> A_IWL<62470> A_IWL<62469> A_IWL<62468> A_IWL<62467> A_IWL<62466> A_IWL<62465> A_IWL<62464> A_IWL<63487> A_IWL<63486> A_IWL<63485> A_IWL<63484> A_IWL<63483> A_IWL<63482> A_IWL<63481> A_IWL<63480> A_IWL<63479> A_IWL<63478> A_IWL<63477> A_IWL<63476> A_IWL<63475> A_IWL<63474> A_IWL<63473> A_IWL<63472> A_IWL<63471> A_IWL<63470> A_IWL<63469> A_IWL<63468> A_IWL<63467> A_IWL<63466> A_IWL<63465> A_IWL<63464> A_IWL<63463> A_IWL<63462> A_IWL<63461> A_IWL<63460> A_IWL<63459> A_IWL<63458> A_IWL<63457> A_IWL<63456> A_IWL<63455> A_IWL<63454> A_IWL<63453> A_IWL<63452> A_IWL<63451> A_IWL<63450> A_IWL<63449> A_IWL<63448> A_IWL<63447> A_IWL<63446> A_IWL<63445> A_IWL<63444> A_IWL<63443> A_IWL<63442> A_IWL<63441> A_IWL<63440> A_IWL<63439> A_IWL<63438> A_IWL<63437> A_IWL<63436> A_IWL<63435> A_IWL<63434> A_IWL<63433> A_IWL<63432> A_IWL<63431> A_IWL<63430> A_IWL<63429> A_IWL<63428> A_IWL<63427> A_IWL<63426> A_IWL<63425> A_IWL<63424> A_IWL<63423> A_IWL<63422> A_IWL<63421> A_IWL<63420> A_IWL<63419> A_IWL<63418> A_IWL<63417> A_IWL<63416> A_IWL<63415> A_IWL<63414> A_IWL<63413> A_IWL<63412> A_IWL<63411> A_IWL<63410> A_IWL<63409> A_IWL<63408> A_IWL<63407> A_IWL<63406> A_IWL<63405> A_IWL<63404> A_IWL<63403> A_IWL<63402> A_IWL<63401> A_IWL<63400> A_IWL<63399> A_IWL<63398> A_IWL<63397> A_IWL<63396> A_IWL<63395> A_IWL<63394> A_IWL<63393> A_IWL<63392> A_IWL<63391> A_IWL<63390> A_IWL<63389> A_IWL<63388> A_IWL<63387> A_IWL<63386> A_IWL<63385> A_IWL<63384> A_IWL<63383> A_IWL<63382> A_IWL<63381> A_IWL<63380> A_IWL<63379> A_IWL<63378> A_IWL<63377> A_IWL<63376> A_IWL<63375> A_IWL<63374> A_IWL<63373> A_IWL<63372> A_IWL<63371> A_IWL<63370> A_IWL<63369> A_IWL<63368> A_IWL<63367> A_IWL<63366> A_IWL<63365> A_IWL<63364> A_IWL<63363> A_IWL<63362> A_IWL<63361> A_IWL<63360> A_IWL<63359> A_IWL<63358> A_IWL<63357> A_IWL<63356> A_IWL<63355> A_IWL<63354> A_IWL<63353> A_IWL<63352> A_IWL<63351> A_IWL<63350> A_IWL<63349> A_IWL<63348> A_IWL<63347> A_IWL<63346> A_IWL<63345> A_IWL<63344> A_IWL<63343> A_IWL<63342> A_IWL<63341> A_IWL<63340> A_IWL<63339> A_IWL<63338> A_IWL<63337> A_IWL<63336> A_IWL<63335> A_IWL<63334> A_IWL<63333> A_IWL<63332> A_IWL<63331> A_IWL<63330> A_IWL<63329> A_IWL<63328> A_IWL<63327> A_IWL<63326> A_IWL<63325> A_IWL<63324> A_IWL<63323> A_IWL<63322> A_IWL<63321> A_IWL<63320> A_IWL<63319> A_IWL<63318> A_IWL<63317> A_IWL<63316> A_IWL<63315> A_IWL<63314> A_IWL<63313> A_IWL<63312> A_IWL<63311> A_IWL<63310> A_IWL<63309> A_IWL<63308> A_IWL<63307> A_IWL<63306> A_IWL<63305> A_IWL<63304> A_IWL<63303> A_IWL<63302> A_IWL<63301> A_IWL<63300> A_IWL<63299> A_IWL<63298> A_IWL<63297> A_IWL<63296> A_IWL<63295> A_IWL<63294> A_IWL<63293> A_IWL<63292> A_IWL<63291> A_IWL<63290> A_IWL<63289> A_IWL<63288> A_IWL<63287> A_IWL<63286> A_IWL<63285> A_IWL<63284> A_IWL<63283> A_IWL<63282> A_IWL<63281> A_IWL<63280> A_IWL<63279> A_IWL<63278> A_IWL<63277> A_IWL<63276> A_IWL<63275> A_IWL<63274> A_IWL<63273> A_IWL<63272> A_IWL<63271> A_IWL<63270> A_IWL<63269> A_IWL<63268> A_IWL<63267> A_IWL<63266> A_IWL<63265> A_IWL<63264> A_IWL<63263> A_IWL<63262> A_IWL<63261> A_IWL<63260> A_IWL<63259> A_IWL<63258> A_IWL<63257> A_IWL<63256> A_IWL<63255> A_IWL<63254> A_IWL<63253> A_IWL<63252> A_IWL<63251> A_IWL<63250> A_IWL<63249> A_IWL<63248> A_IWL<63247> A_IWL<63246> A_IWL<63245> A_IWL<63244> A_IWL<63243> A_IWL<63242> A_IWL<63241> A_IWL<63240> A_IWL<63239> A_IWL<63238> A_IWL<63237> A_IWL<63236> A_IWL<63235> A_IWL<63234> A_IWL<63233> A_IWL<63232> A_IWL<63231> A_IWL<63230> A_IWL<63229> A_IWL<63228> A_IWL<63227> A_IWL<63226> A_IWL<63225> A_IWL<63224> A_IWL<63223> A_IWL<63222> A_IWL<63221> A_IWL<63220> A_IWL<63219> A_IWL<63218> A_IWL<63217> A_IWL<63216> A_IWL<63215> A_IWL<63214> A_IWL<63213> A_IWL<63212> A_IWL<63211> A_IWL<63210> A_IWL<63209> A_IWL<63208> A_IWL<63207> A_IWL<63206> A_IWL<63205> A_IWL<63204> A_IWL<63203> A_IWL<63202> A_IWL<63201> A_IWL<63200> A_IWL<63199> A_IWL<63198> A_IWL<63197> A_IWL<63196> A_IWL<63195> A_IWL<63194> A_IWL<63193> A_IWL<63192> A_IWL<63191> A_IWL<63190> A_IWL<63189> A_IWL<63188> A_IWL<63187> A_IWL<63186> A_IWL<63185> A_IWL<63184> A_IWL<63183> A_IWL<63182> A_IWL<63181> A_IWL<63180> A_IWL<63179> A_IWL<63178> A_IWL<63177> A_IWL<63176> A_IWL<63175> A_IWL<63174> A_IWL<63173> A_IWL<63172> A_IWL<63171> A_IWL<63170> A_IWL<63169> A_IWL<63168> A_IWL<63167> A_IWL<63166> A_IWL<63165> A_IWL<63164> A_IWL<63163> A_IWL<63162> A_IWL<63161> A_IWL<63160> A_IWL<63159> A_IWL<63158> A_IWL<63157> A_IWL<63156> A_IWL<63155> A_IWL<63154> A_IWL<63153> A_IWL<63152> A_IWL<63151> A_IWL<63150> A_IWL<63149> A_IWL<63148> A_IWL<63147> A_IWL<63146> A_IWL<63145> A_IWL<63144> A_IWL<63143> A_IWL<63142> A_IWL<63141> A_IWL<63140> A_IWL<63139> A_IWL<63138> A_IWL<63137> A_IWL<63136> A_IWL<63135> A_IWL<63134> A_IWL<63133> A_IWL<63132> A_IWL<63131> A_IWL<63130> A_IWL<63129> A_IWL<63128> A_IWL<63127> A_IWL<63126> A_IWL<63125> A_IWL<63124> A_IWL<63123> A_IWL<63122> A_IWL<63121> A_IWL<63120> A_IWL<63119> A_IWL<63118> A_IWL<63117> A_IWL<63116> A_IWL<63115> A_IWL<63114> A_IWL<63113> A_IWL<63112> A_IWL<63111> A_IWL<63110> A_IWL<63109> A_IWL<63108> A_IWL<63107> A_IWL<63106> A_IWL<63105> A_IWL<63104> A_IWL<63103> A_IWL<63102> A_IWL<63101> A_IWL<63100> A_IWL<63099> A_IWL<63098> A_IWL<63097> A_IWL<63096> A_IWL<63095> A_IWL<63094> A_IWL<63093> A_IWL<63092> A_IWL<63091> A_IWL<63090> A_IWL<63089> A_IWL<63088> A_IWL<63087> A_IWL<63086> A_IWL<63085> A_IWL<63084> A_IWL<63083> A_IWL<63082> A_IWL<63081> A_IWL<63080> A_IWL<63079> A_IWL<63078> A_IWL<63077> A_IWL<63076> A_IWL<63075> A_IWL<63074> A_IWL<63073> A_IWL<63072> A_IWL<63071> A_IWL<63070> A_IWL<63069> A_IWL<63068> A_IWL<63067> A_IWL<63066> A_IWL<63065> A_IWL<63064> A_IWL<63063> A_IWL<63062> A_IWL<63061> A_IWL<63060> A_IWL<63059> A_IWL<63058> A_IWL<63057> A_IWL<63056> A_IWL<63055> A_IWL<63054> A_IWL<63053> A_IWL<63052> A_IWL<63051> A_IWL<63050> A_IWL<63049> A_IWL<63048> A_IWL<63047> A_IWL<63046> A_IWL<63045> A_IWL<63044> A_IWL<63043> A_IWL<63042> A_IWL<63041> A_IWL<63040> A_IWL<63039> A_IWL<63038> A_IWL<63037> A_IWL<63036> A_IWL<63035> A_IWL<63034> A_IWL<63033> A_IWL<63032> A_IWL<63031> A_IWL<63030> A_IWL<63029> A_IWL<63028> A_IWL<63027> A_IWL<63026> A_IWL<63025> A_IWL<63024> A_IWL<63023> A_IWL<63022> A_IWL<63021> A_IWL<63020> A_IWL<63019> A_IWL<63018> A_IWL<63017> A_IWL<63016> A_IWL<63015> A_IWL<63014> A_IWL<63013> A_IWL<63012> A_IWL<63011> A_IWL<63010> A_IWL<63009> A_IWL<63008> A_IWL<63007> A_IWL<63006> A_IWL<63005> A_IWL<63004> A_IWL<63003> A_IWL<63002> A_IWL<63001> A_IWL<63000> A_IWL<62999> A_IWL<62998> A_IWL<62997> A_IWL<62996> A_IWL<62995> A_IWL<62994> A_IWL<62993> A_IWL<62992> A_IWL<62991> A_IWL<62990> A_IWL<62989> A_IWL<62988> A_IWL<62987> A_IWL<62986> A_IWL<62985> A_IWL<62984> A_IWL<62983> A_IWL<62982> A_IWL<62981> A_IWL<62980> A_IWL<62979> A_IWL<62978> A_IWL<62977> A_IWL<62976> VDD_CORE VSS / RM_IHPSG13_8192x32_c4_1P_COLUMN_pcell_0 +XCOL<122> A_BLC<245> A_BLC<244> A_BLC_TOP<245> A_BLC_TOP<244> A_BLT<245> A_BLT<244> A_BLT_TOP<245> A_BLT_TOP<244> A_IWL<62463> A_IWL<62462> A_IWL<62461> A_IWL<62460> A_IWL<62459> A_IWL<62458> A_IWL<62457> A_IWL<62456> A_IWL<62455> A_IWL<62454> A_IWL<62453> A_IWL<62452> A_IWL<62451> A_IWL<62450> A_IWL<62449> A_IWL<62448> A_IWL<62447> A_IWL<62446> A_IWL<62445> A_IWL<62444> A_IWL<62443> A_IWL<62442> A_IWL<62441> A_IWL<62440> A_IWL<62439> A_IWL<62438> A_IWL<62437> A_IWL<62436> A_IWL<62435> A_IWL<62434> A_IWL<62433> A_IWL<62432> A_IWL<62431> A_IWL<62430> A_IWL<62429> A_IWL<62428> A_IWL<62427> A_IWL<62426> A_IWL<62425> A_IWL<62424> A_IWL<62423> A_IWL<62422> A_IWL<62421> A_IWL<62420> A_IWL<62419> A_IWL<62418> A_IWL<62417> A_IWL<62416> A_IWL<62415> A_IWL<62414> A_IWL<62413> A_IWL<62412> A_IWL<62411> A_IWL<62410> A_IWL<62409> A_IWL<62408> A_IWL<62407> A_IWL<62406> A_IWL<62405> A_IWL<62404> A_IWL<62403> A_IWL<62402> A_IWL<62401> A_IWL<62400> A_IWL<62399> A_IWL<62398> A_IWL<62397> A_IWL<62396> A_IWL<62395> A_IWL<62394> A_IWL<62393> A_IWL<62392> A_IWL<62391> A_IWL<62390> A_IWL<62389> A_IWL<62388> A_IWL<62387> A_IWL<62386> A_IWL<62385> A_IWL<62384> A_IWL<62383> A_IWL<62382> A_IWL<62381> A_IWL<62380> A_IWL<62379> A_IWL<62378> A_IWL<62377> A_IWL<62376> A_IWL<62375> A_IWL<62374> A_IWL<62373> A_IWL<62372> A_IWL<62371> A_IWL<62370> A_IWL<62369> A_IWL<62368> A_IWL<62367> A_IWL<62366> A_IWL<62365> A_IWL<62364> A_IWL<62363> A_IWL<62362> A_IWL<62361> A_IWL<62360> A_IWL<62359> A_IWL<62358> A_IWL<62357> A_IWL<62356> A_IWL<62355> A_IWL<62354> A_IWL<62353> A_IWL<62352> A_IWL<62351> A_IWL<62350> A_IWL<62349> A_IWL<62348> A_IWL<62347> A_IWL<62346> A_IWL<62345> A_IWL<62344> A_IWL<62343> A_IWL<62342> A_IWL<62341> A_IWL<62340> A_IWL<62339> A_IWL<62338> A_IWL<62337> A_IWL<62336> A_IWL<62335> A_IWL<62334> A_IWL<62333> A_IWL<62332> A_IWL<62331> A_IWL<62330> A_IWL<62329> A_IWL<62328> A_IWL<62327> A_IWL<62326> A_IWL<62325> A_IWL<62324> A_IWL<62323> A_IWL<62322> A_IWL<62321> A_IWL<62320> A_IWL<62319> A_IWL<62318> A_IWL<62317> A_IWL<62316> A_IWL<62315> A_IWL<62314> A_IWL<62313> A_IWL<62312> A_IWL<62311> A_IWL<62310> A_IWL<62309> A_IWL<62308> A_IWL<62307> A_IWL<62306> A_IWL<62305> A_IWL<62304> A_IWL<62303> A_IWL<62302> A_IWL<62301> A_IWL<62300> A_IWL<62299> A_IWL<62298> A_IWL<62297> A_IWL<62296> A_IWL<62295> A_IWL<62294> A_IWL<62293> A_IWL<62292> A_IWL<62291> A_IWL<62290> A_IWL<62289> A_IWL<62288> A_IWL<62287> A_IWL<62286> A_IWL<62285> A_IWL<62284> A_IWL<62283> A_IWL<62282> A_IWL<62281> A_IWL<62280> A_IWL<62279> A_IWL<62278> A_IWL<62277> A_IWL<62276> A_IWL<62275> A_IWL<62274> A_IWL<62273> A_IWL<62272> A_IWL<62271> A_IWL<62270> A_IWL<62269> A_IWL<62268> A_IWL<62267> A_IWL<62266> A_IWL<62265> A_IWL<62264> A_IWL<62263> A_IWL<62262> A_IWL<62261> A_IWL<62260> A_IWL<62259> A_IWL<62258> A_IWL<62257> A_IWL<62256> A_IWL<62255> A_IWL<62254> A_IWL<62253> A_IWL<62252> A_IWL<62251> A_IWL<62250> A_IWL<62249> A_IWL<62248> A_IWL<62247> A_IWL<62246> A_IWL<62245> A_IWL<62244> A_IWL<62243> A_IWL<62242> A_IWL<62241> A_IWL<62240> A_IWL<62239> A_IWL<62238> A_IWL<62237> A_IWL<62236> A_IWL<62235> A_IWL<62234> A_IWL<62233> A_IWL<62232> A_IWL<62231> A_IWL<62230> A_IWL<62229> A_IWL<62228> A_IWL<62227> A_IWL<62226> A_IWL<62225> A_IWL<62224> A_IWL<62223> A_IWL<62222> A_IWL<62221> A_IWL<62220> A_IWL<62219> A_IWL<62218> A_IWL<62217> A_IWL<62216> A_IWL<62215> A_IWL<62214> A_IWL<62213> A_IWL<62212> A_IWL<62211> A_IWL<62210> A_IWL<62209> A_IWL<62208> A_IWL<62207> A_IWL<62206> A_IWL<62205> A_IWL<62204> A_IWL<62203> A_IWL<62202> A_IWL<62201> A_IWL<62200> A_IWL<62199> A_IWL<62198> A_IWL<62197> A_IWL<62196> A_IWL<62195> A_IWL<62194> A_IWL<62193> A_IWL<62192> A_IWL<62191> A_IWL<62190> A_IWL<62189> A_IWL<62188> A_IWL<62187> A_IWL<62186> A_IWL<62185> A_IWL<62184> A_IWL<62183> A_IWL<62182> A_IWL<62181> A_IWL<62180> A_IWL<62179> A_IWL<62178> A_IWL<62177> A_IWL<62176> A_IWL<62175> A_IWL<62174> A_IWL<62173> A_IWL<62172> A_IWL<62171> A_IWL<62170> A_IWL<62169> A_IWL<62168> A_IWL<62167> A_IWL<62166> A_IWL<62165> A_IWL<62164> A_IWL<62163> A_IWL<62162> A_IWL<62161> A_IWL<62160> A_IWL<62159> A_IWL<62158> A_IWL<62157> A_IWL<62156> A_IWL<62155> A_IWL<62154> A_IWL<62153> A_IWL<62152> A_IWL<62151> A_IWL<62150> A_IWL<62149> A_IWL<62148> A_IWL<62147> A_IWL<62146> A_IWL<62145> A_IWL<62144> A_IWL<62143> A_IWL<62142> A_IWL<62141> A_IWL<62140> A_IWL<62139> A_IWL<62138> A_IWL<62137> A_IWL<62136> A_IWL<62135> A_IWL<62134> A_IWL<62133> A_IWL<62132> A_IWL<62131> A_IWL<62130> A_IWL<62129> A_IWL<62128> A_IWL<62127> A_IWL<62126> A_IWL<62125> A_IWL<62124> A_IWL<62123> A_IWL<62122> A_IWL<62121> A_IWL<62120> A_IWL<62119> A_IWL<62118> A_IWL<62117> A_IWL<62116> A_IWL<62115> A_IWL<62114> A_IWL<62113> A_IWL<62112> A_IWL<62111> A_IWL<62110> A_IWL<62109> A_IWL<62108> A_IWL<62107> A_IWL<62106> A_IWL<62105> A_IWL<62104> A_IWL<62103> A_IWL<62102> A_IWL<62101> A_IWL<62100> A_IWL<62099> A_IWL<62098> A_IWL<62097> A_IWL<62096> A_IWL<62095> A_IWL<62094> A_IWL<62093> A_IWL<62092> A_IWL<62091> A_IWL<62090> A_IWL<62089> A_IWL<62088> A_IWL<62087> A_IWL<62086> A_IWL<62085> A_IWL<62084> A_IWL<62083> A_IWL<62082> A_IWL<62081> A_IWL<62080> A_IWL<62079> A_IWL<62078> A_IWL<62077> A_IWL<62076> A_IWL<62075> A_IWL<62074> A_IWL<62073> A_IWL<62072> A_IWL<62071> A_IWL<62070> A_IWL<62069> A_IWL<62068> A_IWL<62067> A_IWL<62066> A_IWL<62065> A_IWL<62064> A_IWL<62063> A_IWL<62062> A_IWL<62061> A_IWL<62060> A_IWL<62059> A_IWL<62058> A_IWL<62057> A_IWL<62056> A_IWL<62055> A_IWL<62054> A_IWL<62053> A_IWL<62052> A_IWL<62051> A_IWL<62050> A_IWL<62049> A_IWL<62048> A_IWL<62047> A_IWL<62046> A_IWL<62045> A_IWL<62044> A_IWL<62043> A_IWL<62042> A_IWL<62041> A_IWL<62040> A_IWL<62039> A_IWL<62038> A_IWL<62037> A_IWL<62036> A_IWL<62035> A_IWL<62034> A_IWL<62033> A_IWL<62032> A_IWL<62031> A_IWL<62030> A_IWL<62029> A_IWL<62028> A_IWL<62027> A_IWL<62026> A_IWL<62025> A_IWL<62024> A_IWL<62023> A_IWL<62022> A_IWL<62021> A_IWL<62020> A_IWL<62019> A_IWL<62018> A_IWL<62017> A_IWL<62016> A_IWL<62015> A_IWL<62014> A_IWL<62013> A_IWL<62012> A_IWL<62011> A_IWL<62010> A_IWL<62009> A_IWL<62008> A_IWL<62007> A_IWL<62006> A_IWL<62005> A_IWL<62004> A_IWL<62003> A_IWL<62002> A_IWL<62001> A_IWL<62000> A_IWL<61999> A_IWL<61998> A_IWL<61997> A_IWL<61996> A_IWL<61995> A_IWL<61994> A_IWL<61993> A_IWL<61992> A_IWL<61991> A_IWL<61990> A_IWL<61989> A_IWL<61988> A_IWL<61987> A_IWL<61986> A_IWL<61985> A_IWL<61984> A_IWL<61983> A_IWL<61982> A_IWL<61981> A_IWL<61980> A_IWL<61979> A_IWL<61978> A_IWL<61977> A_IWL<61976> A_IWL<61975> A_IWL<61974> A_IWL<61973> A_IWL<61972> A_IWL<61971> A_IWL<61970> A_IWL<61969> A_IWL<61968> A_IWL<61967> A_IWL<61966> A_IWL<61965> A_IWL<61964> A_IWL<61963> A_IWL<61962> A_IWL<61961> A_IWL<61960> A_IWL<61959> A_IWL<61958> A_IWL<61957> A_IWL<61956> A_IWL<61955> A_IWL<61954> A_IWL<61953> A_IWL<61952> A_IWL<62975> A_IWL<62974> A_IWL<62973> A_IWL<62972> A_IWL<62971> A_IWL<62970> A_IWL<62969> A_IWL<62968> A_IWL<62967> A_IWL<62966> A_IWL<62965> A_IWL<62964> A_IWL<62963> A_IWL<62962> A_IWL<62961> A_IWL<62960> A_IWL<62959> A_IWL<62958> A_IWL<62957> A_IWL<62956> A_IWL<62955> A_IWL<62954> A_IWL<62953> A_IWL<62952> A_IWL<62951> A_IWL<62950> A_IWL<62949> A_IWL<62948> A_IWL<62947> A_IWL<62946> A_IWL<62945> A_IWL<62944> A_IWL<62943> A_IWL<62942> A_IWL<62941> A_IWL<62940> A_IWL<62939> A_IWL<62938> A_IWL<62937> A_IWL<62936> A_IWL<62935> A_IWL<62934> A_IWL<62933> A_IWL<62932> A_IWL<62931> A_IWL<62930> A_IWL<62929> A_IWL<62928> A_IWL<62927> A_IWL<62926> A_IWL<62925> A_IWL<62924> A_IWL<62923> A_IWL<62922> A_IWL<62921> A_IWL<62920> A_IWL<62919> A_IWL<62918> A_IWL<62917> A_IWL<62916> A_IWL<62915> A_IWL<62914> A_IWL<62913> A_IWL<62912> A_IWL<62911> A_IWL<62910> A_IWL<62909> A_IWL<62908> A_IWL<62907> A_IWL<62906> A_IWL<62905> A_IWL<62904> A_IWL<62903> A_IWL<62902> A_IWL<62901> A_IWL<62900> A_IWL<62899> A_IWL<62898> A_IWL<62897> A_IWL<62896> A_IWL<62895> A_IWL<62894> A_IWL<62893> A_IWL<62892> A_IWL<62891> A_IWL<62890> A_IWL<62889> A_IWL<62888> A_IWL<62887> A_IWL<62886> A_IWL<62885> A_IWL<62884> A_IWL<62883> A_IWL<62882> A_IWL<62881> A_IWL<62880> A_IWL<62879> A_IWL<62878> A_IWL<62877> A_IWL<62876> A_IWL<62875> A_IWL<62874> A_IWL<62873> A_IWL<62872> A_IWL<62871> A_IWL<62870> A_IWL<62869> A_IWL<62868> A_IWL<62867> A_IWL<62866> A_IWL<62865> A_IWL<62864> A_IWL<62863> A_IWL<62862> A_IWL<62861> A_IWL<62860> A_IWL<62859> A_IWL<62858> A_IWL<62857> A_IWL<62856> A_IWL<62855> A_IWL<62854> A_IWL<62853> A_IWL<62852> A_IWL<62851> A_IWL<62850> A_IWL<62849> A_IWL<62848> A_IWL<62847> A_IWL<62846> A_IWL<62845> A_IWL<62844> A_IWL<62843> A_IWL<62842> A_IWL<62841> A_IWL<62840> A_IWL<62839> A_IWL<62838> A_IWL<62837> A_IWL<62836> A_IWL<62835> A_IWL<62834> A_IWL<62833> A_IWL<62832> A_IWL<62831> A_IWL<62830> A_IWL<62829> A_IWL<62828> A_IWL<62827> A_IWL<62826> A_IWL<62825> A_IWL<62824> A_IWL<62823> A_IWL<62822> A_IWL<62821> A_IWL<62820> A_IWL<62819> A_IWL<62818> A_IWL<62817> A_IWL<62816> A_IWL<62815> A_IWL<62814> A_IWL<62813> A_IWL<62812> A_IWL<62811> A_IWL<62810> A_IWL<62809> A_IWL<62808> A_IWL<62807> A_IWL<62806> A_IWL<62805> A_IWL<62804> A_IWL<62803> A_IWL<62802> A_IWL<62801> A_IWL<62800> A_IWL<62799> A_IWL<62798> A_IWL<62797> A_IWL<62796> A_IWL<62795> A_IWL<62794> A_IWL<62793> A_IWL<62792> A_IWL<62791> A_IWL<62790> A_IWL<62789> A_IWL<62788> A_IWL<62787> A_IWL<62786> A_IWL<62785> A_IWL<62784> A_IWL<62783> A_IWL<62782> A_IWL<62781> A_IWL<62780> A_IWL<62779> A_IWL<62778> A_IWL<62777> A_IWL<62776> A_IWL<62775> A_IWL<62774> A_IWL<62773> A_IWL<62772> A_IWL<62771> A_IWL<62770> A_IWL<62769> A_IWL<62768> A_IWL<62767> A_IWL<62766> A_IWL<62765> A_IWL<62764> A_IWL<62763> A_IWL<62762> A_IWL<62761> A_IWL<62760> A_IWL<62759> A_IWL<62758> A_IWL<62757> A_IWL<62756> A_IWL<62755> A_IWL<62754> A_IWL<62753> A_IWL<62752> A_IWL<62751> A_IWL<62750> A_IWL<62749> A_IWL<62748> A_IWL<62747> A_IWL<62746> A_IWL<62745> A_IWL<62744> A_IWL<62743> A_IWL<62742> A_IWL<62741> A_IWL<62740> A_IWL<62739> A_IWL<62738> A_IWL<62737> A_IWL<62736> A_IWL<62735> A_IWL<62734> A_IWL<62733> A_IWL<62732> A_IWL<62731> A_IWL<62730> A_IWL<62729> A_IWL<62728> A_IWL<62727> A_IWL<62726> A_IWL<62725> A_IWL<62724> A_IWL<62723> A_IWL<62722> A_IWL<62721> A_IWL<62720> A_IWL<62719> A_IWL<62718> A_IWL<62717> A_IWL<62716> A_IWL<62715> A_IWL<62714> A_IWL<62713> A_IWL<62712> A_IWL<62711> A_IWL<62710> A_IWL<62709> A_IWL<62708> A_IWL<62707> A_IWL<62706> A_IWL<62705> A_IWL<62704> A_IWL<62703> A_IWL<62702> A_IWL<62701> A_IWL<62700> A_IWL<62699> A_IWL<62698> A_IWL<62697> A_IWL<62696> A_IWL<62695> A_IWL<62694> A_IWL<62693> A_IWL<62692> A_IWL<62691> A_IWL<62690> A_IWL<62689> A_IWL<62688> A_IWL<62687> A_IWL<62686> A_IWL<62685> A_IWL<62684> A_IWL<62683> A_IWL<62682> A_IWL<62681> A_IWL<62680> A_IWL<62679> A_IWL<62678> A_IWL<62677> A_IWL<62676> A_IWL<62675> A_IWL<62674> A_IWL<62673> A_IWL<62672> A_IWL<62671> A_IWL<62670> A_IWL<62669> A_IWL<62668> A_IWL<62667> A_IWL<62666> A_IWL<62665> A_IWL<62664> A_IWL<62663> A_IWL<62662> A_IWL<62661> A_IWL<62660> A_IWL<62659> A_IWL<62658> A_IWL<62657> A_IWL<62656> A_IWL<62655> A_IWL<62654> A_IWL<62653> A_IWL<62652> A_IWL<62651> A_IWL<62650> A_IWL<62649> A_IWL<62648> A_IWL<62647> A_IWL<62646> A_IWL<62645> A_IWL<62644> A_IWL<62643> A_IWL<62642> A_IWL<62641> A_IWL<62640> A_IWL<62639> A_IWL<62638> A_IWL<62637> A_IWL<62636> A_IWL<62635> A_IWL<62634> A_IWL<62633> A_IWL<62632> A_IWL<62631> A_IWL<62630> A_IWL<62629> A_IWL<62628> A_IWL<62627> A_IWL<62626> A_IWL<62625> A_IWL<62624> A_IWL<62623> A_IWL<62622> A_IWL<62621> A_IWL<62620> A_IWL<62619> A_IWL<62618> A_IWL<62617> A_IWL<62616> A_IWL<62615> A_IWL<62614> A_IWL<62613> A_IWL<62612> A_IWL<62611> A_IWL<62610> A_IWL<62609> A_IWL<62608> A_IWL<62607> A_IWL<62606> A_IWL<62605> A_IWL<62604> A_IWL<62603> A_IWL<62602> A_IWL<62601> A_IWL<62600> A_IWL<62599> A_IWL<62598> A_IWL<62597> A_IWL<62596> A_IWL<62595> A_IWL<62594> A_IWL<62593> A_IWL<62592> A_IWL<62591> A_IWL<62590> A_IWL<62589> A_IWL<62588> A_IWL<62587> A_IWL<62586> A_IWL<62585> A_IWL<62584> A_IWL<62583> A_IWL<62582> A_IWL<62581> A_IWL<62580> A_IWL<62579> A_IWL<62578> A_IWL<62577> A_IWL<62576> A_IWL<62575> A_IWL<62574> A_IWL<62573> A_IWL<62572> A_IWL<62571> A_IWL<62570> A_IWL<62569> A_IWL<62568> A_IWL<62567> A_IWL<62566> A_IWL<62565> A_IWL<62564> A_IWL<62563> A_IWL<62562> A_IWL<62561> A_IWL<62560> A_IWL<62559> A_IWL<62558> A_IWL<62557> A_IWL<62556> A_IWL<62555> A_IWL<62554> A_IWL<62553> A_IWL<62552> A_IWL<62551> A_IWL<62550> A_IWL<62549> A_IWL<62548> A_IWL<62547> A_IWL<62546> A_IWL<62545> A_IWL<62544> A_IWL<62543> A_IWL<62542> A_IWL<62541> A_IWL<62540> A_IWL<62539> A_IWL<62538> A_IWL<62537> A_IWL<62536> A_IWL<62535> A_IWL<62534> A_IWL<62533> A_IWL<62532> A_IWL<62531> A_IWL<62530> A_IWL<62529> A_IWL<62528> A_IWL<62527> A_IWL<62526> A_IWL<62525> A_IWL<62524> A_IWL<62523> A_IWL<62522> A_IWL<62521> A_IWL<62520> A_IWL<62519> A_IWL<62518> A_IWL<62517> A_IWL<62516> A_IWL<62515> A_IWL<62514> A_IWL<62513> A_IWL<62512> A_IWL<62511> A_IWL<62510> A_IWL<62509> A_IWL<62508> A_IWL<62507> A_IWL<62506> A_IWL<62505> A_IWL<62504> A_IWL<62503> A_IWL<62502> A_IWL<62501> A_IWL<62500> A_IWL<62499> A_IWL<62498> A_IWL<62497> A_IWL<62496> A_IWL<62495> A_IWL<62494> A_IWL<62493> A_IWL<62492> A_IWL<62491> A_IWL<62490> A_IWL<62489> A_IWL<62488> A_IWL<62487> A_IWL<62486> A_IWL<62485> A_IWL<62484> A_IWL<62483> A_IWL<62482> A_IWL<62481> A_IWL<62480> A_IWL<62479> A_IWL<62478> A_IWL<62477> A_IWL<62476> A_IWL<62475> A_IWL<62474> A_IWL<62473> A_IWL<62472> A_IWL<62471> A_IWL<62470> A_IWL<62469> A_IWL<62468> A_IWL<62467> A_IWL<62466> A_IWL<62465> A_IWL<62464> VDD_CORE VSS / RM_IHPSG13_8192x32_c4_1P_COLUMN_pcell_0 +XCOL<121> A_BLC<243> A_BLC<242> A_BLC_TOP<243> A_BLC_TOP<242> A_BLT<243> A_BLT<242> A_BLT_TOP<243> A_BLT_TOP<242> A_IWL<61951> A_IWL<61950> A_IWL<61949> A_IWL<61948> A_IWL<61947> A_IWL<61946> A_IWL<61945> A_IWL<61944> A_IWL<61943> A_IWL<61942> A_IWL<61941> A_IWL<61940> A_IWL<61939> A_IWL<61938> A_IWL<61937> A_IWL<61936> A_IWL<61935> A_IWL<61934> A_IWL<61933> A_IWL<61932> A_IWL<61931> A_IWL<61930> A_IWL<61929> A_IWL<61928> A_IWL<61927> A_IWL<61926> A_IWL<61925> A_IWL<61924> A_IWL<61923> A_IWL<61922> A_IWL<61921> A_IWL<61920> A_IWL<61919> A_IWL<61918> A_IWL<61917> A_IWL<61916> A_IWL<61915> A_IWL<61914> A_IWL<61913> A_IWL<61912> A_IWL<61911> A_IWL<61910> A_IWL<61909> A_IWL<61908> A_IWL<61907> A_IWL<61906> A_IWL<61905> A_IWL<61904> A_IWL<61903> A_IWL<61902> A_IWL<61901> A_IWL<61900> A_IWL<61899> A_IWL<61898> A_IWL<61897> A_IWL<61896> A_IWL<61895> A_IWL<61894> A_IWL<61893> A_IWL<61892> A_IWL<61891> A_IWL<61890> A_IWL<61889> A_IWL<61888> A_IWL<61887> A_IWL<61886> A_IWL<61885> A_IWL<61884> A_IWL<61883> A_IWL<61882> A_IWL<61881> A_IWL<61880> A_IWL<61879> A_IWL<61878> A_IWL<61877> A_IWL<61876> A_IWL<61875> A_IWL<61874> A_IWL<61873> A_IWL<61872> A_IWL<61871> A_IWL<61870> A_IWL<61869> A_IWL<61868> A_IWL<61867> A_IWL<61866> A_IWL<61865> A_IWL<61864> A_IWL<61863> A_IWL<61862> A_IWL<61861> A_IWL<61860> A_IWL<61859> A_IWL<61858> A_IWL<61857> A_IWL<61856> A_IWL<61855> A_IWL<61854> A_IWL<61853> A_IWL<61852> A_IWL<61851> A_IWL<61850> A_IWL<61849> A_IWL<61848> A_IWL<61847> A_IWL<61846> A_IWL<61845> A_IWL<61844> A_IWL<61843> A_IWL<61842> A_IWL<61841> A_IWL<61840> A_IWL<61839> A_IWL<61838> A_IWL<61837> A_IWL<61836> A_IWL<61835> A_IWL<61834> A_IWL<61833> A_IWL<61832> A_IWL<61831> A_IWL<61830> A_IWL<61829> A_IWL<61828> A_IWL<61827> A_IWL<61826> A_IWL<61825> A_IWL<61824> A_IWL<61823> A_IWL<61822> A_IWL<61821> A_IWL<61820> A_IWL<61819> A_IWL<61818> A_IWL<61817> A_IWL<61816> A_IWL<61815> A_IWL<61814> A_IWL<61813> A_IWL<61812> A_IWL<61811> A_IWL<61810> A_IWL<61809> A_IWL<61808> A_IWL<61807> A_IWL<61806> A_IWL<61805> A_IWL<61804> A_IWL<61803> A_IWL<61802> A_IWL<61801> A_IWL<61800> A_IWL<61799> A_IWL<61798> A_IWL<61797> A_IWL<61796> A_IWL<61795> A_IWL<61794> A_IWL<61793> A_IWL<61792> A_IWL<61791> A_IWL<61790> A_IWL<61789> A_IWL<61788> A_IWL<61787> A_IWL<61786> A_IWL<61785> A_IWL<61784> A_IWL<61783> A_IWL<61782> A_IWL<61781> A_IWL<61780> A_IWL<61779> A_IWL<61778> A_IWL<61777> A_IWL<61776> A_IWL<61775> A_IWL<61774> A_IWL<61773> A_IWL<61772> A_IWL<61771> A_IWL<61770> A_IWL<61769> A_IWL<61768> A_IWL<61767> A_IWL<61766> A_IWL<61765> A_IWL<61764> A_IWL<61763> A_IWL<61762> A_IWL<61761> A_IWL<61760> A_IWL<61759> A_IWL<61758> A_IWL<61757> A_IWL<61756> A_IWL<61755> A_IWL<61754> A_IWL<61753> A_IWL<61752> A_IWL<61751> A_IWL<61750> A_IWL<61749> A_IWL<61748> A_IWL<61747> A_IWL<61746> A_IWL<61745> A_IWL<61744> A_IWL<61743> A_IWL<61742> A_IWL<61741> A_IWL<61740> A_IWL<61739> A_IWL<61738> A_IWL<61737> A_IWL<61736> A_IWL<61735> A_IWL<61734> A_IWL<61733> A_IWL<61732> A_IWL<61731> A_IWL<61730> A_IWL<61729> A_IWL<61728> A_IWL<61727> A_IWL<61726> A_IWL<61725> A_IWL<61724> A_IWL<61723> A_IWL<61722> A_IWL<61721> A_IWL<61720> A_IWL<61719> A_IWL<61718> A_IWL<61717> A_IWL<61716> A_IWL<61715> A_IWL<61714> A_IWL<61713> A_IWL<61712> A_IWL<61711> A_IWL<61710> A_IWL<61709> A_IWL<61708> A_IWL<61707> A_IWL<61706> A_IWL<61705> A_IWL<61704> A_IWL<61703> A_IWL<61702> A_IWL<61701> A_IWL<61700> A_IWL<61699> A_IWL<61698> A_IWL<61697> A_IWL<61696> A_IWL<61695> A_IWL<61694> A_IWL<61693> A_IWL<61692> A_IWL<61691> A_IWL<61690> A_IWL<61689> A_IWL<61688> A_IWL<61687> A_IWL<61686> A_IWL<61685> A_IWL<61684> A_IWL<61683> A_IWL<61682> A_IWL<61681> A_IWL<61680> A_IWL<61679> A_IWL<61678> A_IWL<61677> A_IWL<61676> A_IWL<61675> A_IWL<61674> A_IWL<61673> A_IWL<61672> A_IWL<61671> A_IWL<61670> A_IWL<61669> A_IWL<61668> A_IWL<61667> A_IWL<61666> A_IWL<61665> A_IWL<61664> A_IWL<61663> A_IWL<61662> A_IWL<61661> A_IWL<61660> A_IWL<61659> A_IWL<61658> A_IWL<61657> A_IWL<61656> A_IWL<61655> A_IWL<61654> A_IWL<61653> A_IWL<61652> A_IWL<61651> A_IWL<61650> A_IWL<61649> A_IWL<61648> A_IWL<61647> A_IWL<61646> A_IWL<61645> A_IWL<61644> A_IWL<61643> A_IWL<61642> A_IWL<61641> A_IWL<61640> A_IWL<61639> A_IWL<61638> A_IWL<61637> A_IWL<61636> A_IWL<61635> A_IWL<61634> A_IWL<61633> A_IWL<61632> A_IWL<61631> A_IWL<61630> A_IWL<61629> A_IWL<61628> A_IWL<61627> A_IWL<61626> A_IWL<61625> A_IWL<61624> A_IWL<61623> A_IWL<61622> A_IWL<61621> A_IWL<61620> A_IWL<61619> A_IWL<61618> A_IWL<61617> A_IWL<61616> A_IWL<61615> A_IWL<61614> A_IWL<61613> A_IWL<61612> A_IWL<61611> A_IWL<61610> A_IWL<61609> A_IWL<61608> A_IWL<61607> A_IWL<61606> A_IWL<61605> A_IWL<61604> A_IWL<61603> A_IWL<61602> A_IWL<61601> A_IWL<61600> A_IWL<61599> A_IWL<61598> A_IWL<61597> A_IWL<61596> A_IWL<61595> A_IWL<61594> A_IWL<61593> A_IWL<61592> A_IWL<61591> A_IWL<61590> A_IWL<61589> A_IWL<61588> A_IWL<61587> A_IWL<61586> A_IWL<61585> A_IWL<61584> A_IWL<61583> A_IWL<61582> A_IWL<61581> A_IWL<61580> A_IWL<61579> A_IWL<61578> A_IWL<61577> A_IWL<61576> A_IWL<61575> A_IWL<61574> A_IWL<61573> A_IWL<61572> A_IWL<61571> A_IWL<61570> A_IWL<61569> A_IWL<61568> A_IWL<61567> A_IWL<61566> A_IWL<61565> A_IWL<61564> A_IWL<61563> A_IWL<61562> A_IWL<61561> A_IWL<61560> A_IWL<61559> A_IWL<61558> A_IWL<61557> A_IWL<61556> A_IWL<61555> A_IWL<61554> A_IWL<61553> A_IWL<61552> A_IWL<61551> A_IWL<61550> A_IWL<61549> A_IWL<61548> A_IWL<61547> A_IWL<61546> A_IWL<61545> A_IWL<61544> A_IWL<61543> A_IWL<61542> A_IWL<61541> A_IWL<61540> A_IWL<61539> A_IWL<61538> A_IWL<61537> A_IWL<61536> A_IWL<61535> A_IWL<61534> A_IWL<61533> A_IWL<61532> A_IWL<61531> A_IWL<61530> A_IWL<61529> A_IWL<61528> A_IWL<61527> A_IWL<61526> A_IWL<61525> A_IWL<61524> A_IWL<61523> A_IWL<61522> A_IWL<61521> A_IWL<61520> A_IWL<61519> A_IWL<61518> A_IWL<61517> A_IWL<61516> A_IWL<61515> A_IWL<61514> A_IWL<61513> A_IWL<61512> A_IWL<61511> A_IWL<61510> A_IWL<61509> A_IWL<61508> A_IWL<61507> A_IWL<61506> A_IWL<61505> A_IWL<61504> A_IWL<61503> A_IWL<61502> A_IWL<61501> A_IWL<61500> A_IWL<61499> A_IWL<61498> A_IWL<61497> A_IWL<61496> A_IWL<61495> A_IWL<61494> A_IWL<61493> A_IWL<61492> A_IWL<61491> A_IWL<61490> A_IWL<61489> A_IWL<61488> A_IWL<61487> A_IWL<61486> A_IWL<61485> A_IWL<61484> A_IWL<61483> A_IWL<61482> A_IWL<61481> A_IWL<61480> A_IWL<61479> A_IWL<61478> A_IWL<61477> A_IWL<61476> A_IWL<61475> A_IWL<61474> A_IWL<61473> A_IWL<61472> A_IWL<61471> A_IWL<61470> A_IWL<61469> A_IWL<61468> A_IWL<61467> A_IWL<61466> A_IWL<61465> A_IWL<61464> A_IWL<61463> A_IWL<61462> A_IWL<61461> A_IWL<61460> A_IWL<61459> A_IWL<61458> A_IWL<61457> A_IWL<61456> A_IWL<61455> A_IWL<61454> A_IWL<61453> A_IWL<61452> A_IWL<61451> A_IWL<61450> A_IWL<61449> A_IWL<61448> A_IWL<61447> A_IWL<61446> A_IWL<61445> A_IWL<61444> A_IWL<61443> A_IWL<61442> A_IWL<61441> A_IWL<61440> A_IWL<62463> A_IWL<62462> A_IWL<62461> A_IWL<62460> A_IWL<62459> A_IWL<62458> A_IWL<62457> A_IWL<62456> A_IWL<62455> A_IWL<62454> A_IWL<62453> A_IWL<62452> A_IWL<62451> A_IWL<62450> A_IWL<62449> A_IWL<62448> A_IWL<62447> A_IWL<62446> A_IWL<62445> A_IWL<62444> A_IWL<62443> A_IWL<62442> A_IWL<62441> A_IWL<62440> A_IWL<62439> A_IWL<62438> A_IWL<62437> A_IWL<62436> A_IWL<62435> A_IWL<62434> A_IWL<62433> A_IWL<62432> A_IWL<62431> A_IWL<62430> A_IWL<62429> A_IWL<62428> A_IWL<62427> A_IWL<62426> A_IWL<62425> A_IWL<62424> A_IWL<62423> A_IWL<62422> A_IWL<62421> A_IWL<62420> A_IWL<62419> A_IWL<62418> A_IWL<62417> A_IWL<62416> A_IWL<62415> A_IWL<62414> A_IWL<62413> A_IWL<62412> A_IWL<62411> A_IWL<62410> A_IWL<62409> A_IWL<62408> A_IWL<62407> A_IWL<62406> A_IWL<62405> A_IWL<62404> A_IWL<62403> A_IWL<62402> A_IWL<62401> A_IWL<62400> A_IWL<62399> A_IWL<62398> A_IWL<62397> A_IWL<62396> A_IWL<62395> A_IWL<62394> A_IWL<62393> A_IWL<62392> A_IWL<62391> A_IWL<62390> A_IWL<62389> A_IWL<62388> A_IWL<62387> A_IWL<62386> A_IWL<62385> A_IWL<62384> A_IWL<62383> A_IWL<62382> A_IWL<62381> A_IWL<62380> A_IWL<62379> A_IWL<62378> A_IWL<62377> A_IWL<62376> A_IWL<62375> A_IWL<62374> A_IWL<62373> A_IWL<62372> A_IWL<62371> A_IWL<62370> A_IWL<62369> A_IWL<62368> A_IWL<62367> A_IWL<62366> A_IWL<62365> A_IWL<62364> A_IWL<62363> A_IWL<62362> A_IWL<62361> A_IWL<62360> A_IWL<62359> A_IWL<62358> A_IWL<62357> A_IWL<62356> A_IWL<62355> A_IWL<62354> A_IWL<62353> A_IWL<62352> A_IWL<62351> A_IWL<62350> A_IWL<62349> A_IWL<62348> A_IWL<62347> A_IWL<62346> A_IWL<62345> A_IWL<62344> A_IWL<62343> A_IWL<62342> A_IWL<62341> A_IWL<62340> A_IWL<62339> A_IWL<62338> A_IWL<62337> A_IWL<62336> A_IWL<62335> A_IWL<62334> A_IWL<62333> A_IWL<62332> A_IWL<62331> A_IWL<62330> A_IWL<62329> A_IWL<62328> A_IWL<62327> A_IWL<62326> A_IWL<62325> A_IWL<62324> A_IWL<62323> A_IWL<62322> A_IWL<62321> A_IWL<62320> A_IWL<62319> A_IWL<62318> A_IWL<62317> A_IWL<62316> A_IWL<62315> A_IWL<62314> A_IWL<62313> A_IWL<62312> A_IWL<62311> A_IWL<62310> A_IWL<62309> A_IWL<62308> A_IWL<62307> A_IWL<62306> A_IWL<62305> A_IWL<62304> A_IWL<62303> A_IWL<62302> A_IWL<62301> A_IWL<62300> A_IWL<62299> A_IWL<62298> A_IWL<62297> A_IWL<62296> A_IWL<62295> A_IWL<62294> A_IWL<62293> A_IWL<62292> A_IWL<62291> A_IWL<62290> A_IWL<62289> A_IWL<62288> A_IWL<62287> A_IWL<62286> A_IWL<62285> A_IWL<62284> A_IWL<62283> A_IWL<62282> A_IWL<62281> A_IWL<62280> A_IWL<62279> A_IWL<62278> A_IWL<62277> A_IWL<62276> A_IWL<62275> A_IWL<62274> A_IWL<62273> A_IWL<62272> A_IWL<62271> A_IWL<62270> A_IWL<62269> A_IWL<62268> A_IWL<62267> A_IWL<62266> A_IWL<62265> A_IWL<62264> A_IWL<62263> A_IWL<62262> A_IWL<62261> A_IWL<62260> A_IWL<62259> A_IWL<62258> A_IWL<62257> A_IWL<62256> A_IWL<62255> A_IWL<62254> A_IWL<62253> A_IWL<62252> A_IWL<62251> A_IWL<62250> A_IWL<62249> A_IWL<62248> A_IWL<62247> A_IWL<62246> A_IWL<62245> A_IWL<62244> A_IWL<62243> A_IWL<62242> A_IWL<62241> A_IWL<62240> A_IWL<62239> A_IWL<62238> A_IWL<62237> A_IWL<62236> A_IWL<62235> A_IWL<62234> A_IWL<62233> A_IWL<62232> A_IWL<62231> A_IWL<62230> A_IWL<62229> A_IWL<62228> A_IWL<62227> A_IWL<62226> A_IWL<62225> A_IWL<62224> A_IWL<62223> A_IWL<62222> A_IWL<62221> A_IWL<62220> A_IWL<62219> A_IWL<62218> A_IWL<62217> A_IWL<62216> A_IWL<62215> A_IWL<62214> A_IWL<62213> A_IWL<62212> A_IWL<62211> A_IWL<62210> A_IWL<62209> A_IWL<62208> A_IWL<62207> A_IWL<62206> A_IWL<62205> A_IWL<62204> A_IWL<62203> A_IWL<62202> A_IWL<62201> A_IWL<62200> A_IWL<62199> A_IWL<62198> A_IWL<62197> A_IWL<62196> A_IWL<62195> A_IWL<62194> A_IWL<62193> A_IWL<62192> A_IWL<62191> A_IWL<62190> A_IWL<62189> A_IWL<62188> A_IWL<62187> A_IWL<62186> A_IWL<62185> A_IWL<62184> A_IWL<62183> A_IWL<62182> A_IWL<62181> A_IWL<62180> A_IWL<62179> A_IWL<62178> A_IWL<62177> A_IWL<62176> A_IWL<62175> A_IWL<62174> A_IWL<62173> A_IWL<62172> A_IWL<62171> A_IWL<62170> A_IWL<62169> A_IWL<62168> A_IWL<62167> A_IWL<62166> A_IWL<62165> A_IWL<62164> A_IWL<62163> A_IWL<62162> A_IWL<62161> A_IWL<62160> A_IWL<62159> A_IWL<62158> A_IWL<62157> A_IWL<62156> A_IWL<62155> A_IWL<62154> A_IWL<62153> A_IWL<62152> A_IWL<62151> A_IWL<62150> A_IWL<62149> A_IWL<62148> A_IWL<62147> A_IWL<62146> A_IWL<62145> A_IWL<62144> A_IWL<62143> A_IWL<62142> A_IWL<62141> A_IWL<62140> A_IWL<62139> A_IWL<62138> A_IWL<62137> A_IWL<62136> A_IWL<62135> A_IWL<62134> A_IWL<62133> A_IWL<62132> A_IWL<62131> A_IWL<62130> A_IWL<62129> A_IWL<62128> A_IWL<62127> A_IWL<62126> A_IWL<62125> A_IWL<62124> A_IWL<62123> A_IWL<62122> A_IWL<62121> A_IWL<62120> A_IWL<62119> A_IWL<62118> A_IWL<62117> A_IWL<62116> A_IWL<62115> A_IWL<62114> A_IWL<62113> A_IWL<62112> A_IWL<62111> A_IWL<62110> A_IWL<62109> A_IWL<62108> A_IWL<62107> A_IWL<62106> A_IWL<62105> A_IWL<62104> A_IWL<62103> A_IWL<62102> A_IWL<62101> A_IWL<62100> A_IWL<62099> A_IWL<62098> A_IWL<62097> A_IWL<62096> A_IWL<62095> A_IWL<62094> A_IWL<62093> A_IWL<62092> A_IWL<62091> A_IWL<62090> A_IWL<62089> A_IWL<62088> A_IWL<62087> A_IWL<62086> A_IWL<62085> A_IWL<62084> A_IWL<62083> A_IWL<62082> A_IWL<62081> A_IWL<62080> A_IWL<62079> A_IWL<62078> A_IWL<62077> A_IWL<62076> A_IWL<62075> A_IWL<62074> A_IWL<62073> A_IWL<62072> A_IWL<62071> A_IWL<62070> A_IWL<62069> A_IWL<62068> A_IWL<62067> A_IWL<62066> A_IWL<62065> A_IWL<62064> A_IWL<62063> A_IWL<62062> A_IWL<62061> A_IWL<62060> A_IWL<62059> A_IWL<62058> A_IWL<62057> A_IWL<62056> A_IWL<62055> A_IWL<62054> A_IWL<62053> A_IWL<62052> A_IWL<62051> A_IWL<62050> A_IWL<62049> A_IWL<62048> A_IWL<62047> A_IWL<62046> A_IWL<62045> A_IWL<62044> A_IWL<62043> A_IWL<62042> A_IWL<62041> A_IWL<62040> A_IWL<62039> A_IWL<62038> A_IWL<62037> A_IWL<62036> A_IWL<62035> A_IWL<62034> A_IWL<62033> A_IWL<62032> A_IWL<62031> A_IWL<62030> A_IWL<62029> A_IWL<62028> A_IWL<62027> A_IWL<62026> A_IWL<62025> A_IWL<62024> A_IWL<62023> A_IWL<62022> A_IWL<62021> A_IWL<62020> A_IWL<62019> A_IWL<62018> A_IWL<62017> A_IWL<62016> A_IWL<62015> A_IWL<62014> A_IWL<62013> A_IWL<62012> A_IWL<62011> A_IWL<62010> A_IWL<62009> A_IWL<62008> A_IWL<62007> A_IWL<62006> A_IWL<62005> A_IWL<62004> A_IWL<62003> A_IWL<62002> A_IWL<62001> A_IWL<62000> A_IWL<61999> A_IWL<61998> A_IWL<61997> A_IWL<61996> A_IWL<61995> A_IWL<61994> A_IWL<61993> A_IWL<61992> A_IWL<61991> A_IWL<61990> A_IWL<61989> A_IWL<61988> A_IWL<61987> A_IWL<61986> A_IWL<61985> A_IWL<61984> A_IWL<61983> A_IWL<61982> A_IWL<61981> A_IWL<61980> A_IWL<61979> A_IWL<61978> A_IWL<61977> A_IWL<61976> A_IWL<61975> A_IWL<61974> A_IWL<61973> A_IWL<61972> A_IWL<61971> A_IWL<61970> A_IWL<61969> A_IWL<61968> A_IWL<61967> A_IWL<61966> A_IWL<61965> A_IWL<61964> A_IWL<61963> A_IWL<61962> A_IWL<61961> A_IWL<61960> A_IWL<61959> A_IWL<61958> A_IWL<61957> A_IWL<61956> A_IWL<61955> A_IWL<61954> A_IWL<61953> A_IWL<61952> VDD_CORE VSS / RM_IHPSG13_8192x32_c4_1P_COLUMN_pcell_0 +XCOL<120> A_BLC<241> A_BLC<240> A_BLC_TOP<241> A_BLC_TOP<240> A_BLT<241> A_BLT<240> A_BLT_TOP<241> A_BLT_TOP<240> A_IWL<61439> A_IWL<61438> A_IWL<61437> A_IWL<61436> A_IWL<61435> A_IWL<61434> A_IWL<61433> A_IWL<61432> A_IWL<61431> A_IWL<61430> A_IWL<61429> A_IWL<61428> A_IWL<61427> A_IWL<61426> A_IWL<61425> A_IWL<61424> A_IWL<61423> A_IWL<61422> A_IWL<61421> A_IWL<61420> A_IWL<61419> A_IWL<61418> A_IWL<61417> A_IWL<61416> A_IWL<61415> A_IWL<61414> A_IWL<61413> A_IWL<61412> A_IWL<61411> A_IWL<61410> A_IWL<61409> A_IWL<61408> A_IWL<61407> A_IWL<61406> A_IWL<61405> A_IWL<61404> A_IWL<61403> A_IWL<61402> A_IWL<61401> A_IWL<61400> A_IWL<61399> A_IWL<61398> A_IWL<61397> A_IWL<61396> A_IWL<61395> A_IWL<61394> A_IWL<61393> A_IWL<61392> A_IWL<61391> A_IWL<61390> A_IWL<61389> A_IWL<61388> A_IWL<61387> A_IWL<61386> A_IWL<61385> A_IWL<61384> A_IWL<61383> A_IWL<61382> A_IWL<61381> A_IWL<61380> A_IWL<61379> A_IWL<61378> A_IWL<61377> A_IWL<61376> A_IWL<61375> A_IWL<61374> A_IWL<61373> A_IWL<61372> A_IWL<61371> A_IWL<61370> A_IWL<61369> A_IWL<61368> A_IWL<61367> A_IWL<61366> A_IWL<61365> A_IWL<61364> A_IWL<61363> A_IWL<61362> A_IWL<61361> A_IWL<61360> A_IWL<61359> A_IWL<61358> A_IWL<61357> A_IWL<61356> A_IWL<61355> A_IWL<61354> A_IWL<61353> A_IWL<61352> A_IWL<61351> A_IWL<61350> A_IWL<61349> A_IWL<61348> A_IWL<61347> A_IWL<61346> A_IWL<61345> A_IWL<61344> A_IWL<61343> A_IWL<61342> A_IWL<61341> A_IWL<61340> A_IWL<61339> A_IWL<61338> A_IWL<61337> A_IWL<61336> A_IWL<61335> A_IWL<61334> A_IWL<61333> A_IWL<61332> A_IWL<61331> A_IWL<61330> A_IWL<61329> A_IWL<61328> A_IWL<61327> A_IWL<61326> A_IWL<61325> A_IWL<61324> A_IWL<61323> A_IWL<61322> A_IWL<61321> A_IWL<61320> A_IWL<61319> A_IWL<61318> A_IWL<61317> A_IWL<61316> A_IWL<61315> A_IWL<61314> A_IWL<61313> A_IWL<61312> A_IWL<61311> A_IWL<61310> A_IWL<61309> A_IWL<61308> A_IWL<61307> A_IWL<61306> A_IWL<61305> A_IWL<61304> A_IWL<61303> A_IWL<61302> A_IWL<61301> A_IWL<61300> A_IWL<61299> A_IWL<61298> A_IWL<61297> A_IWL<61296> A_IWL<61295> A_IWL<61294> A_IWL<61293> A_IWL<61292> A_IWL<61291> A_IWL<61290> A_IWL<61289> A_IWL<61288> A_IWL<61287> A_IWL<61286> A_IWL<61285> A_IWL<61284> A_IWL<61283> A_IWL<61282> A_IWL<61281> A_IWL<61280> A_IWL<61279> A_IWL<61278> A_IWL<61277> A_IWL<61276> A_IWL<61275> A_IWL<61274> A_IWL<61273> A_IWL<61272> A_IWL<61271> A_IWL<61270> A_IWL<61269> A_IWL<61268> A_IWL<61267> A_IWL<61266> A_IWL<61265> A_IWL<61264> A_IWL<61263> A_IWL<61262> A_IWL<61261> A_IWL<61260> A_IWL<61259> A_IWL<61258> A_IWL<61257> A_IWL<61256> A_IWL<61255> A_IWL<61254> A_IWL<61253> A_IWL<61252> A_IWL<61251> A_IWL<61250> A_IWL<61249> A_IWL<61248> A_IWL<61247> A_IWL<61246> A_IWL<61245> A_IWL<61244> A_IWL<61243> A_IWL<61242> A_IWL<61241> A_IWL<61240> A_IWL<61239> A_IWL<61238> A_IWL<61237> A_IWL<61236> A_IWL<61235> A_IWL<61234> A_IWL<61233> A_IWL<61232> A_IWL<61231> A_IWL<61230> A_IWL<61229> A_IWL<61228> A_IWL<61227> A_IWL<61226> A_IWL<61225> A_IWL<61224> A_IWL<61223> A_IWL<61222> A_IWL<61221> A_IWL<61220> A_IWL<61219> A_IWL<61218> A_IWL<61217> A_IWL<61216> A_IWL<61215> A_IWL<61214> A_IWL<61213> A_IWL<61212> A_IWL<61211> A_IWL<61210> A_IWL<61209> A_IWL<61208> A_IWL<61207> A_IWL<61206> A_IWL<61205> A_IWL<61204> A_IWL<61203> A_IWL<61202> A_IWL<61201> A_IWL<61200> A_IWL<61199> A_IWL<61198> A_IWL<61197> A_IWL<61196> A_IWL<61195> A_IWL<61194> A_IWL<61193> A_IWL<61192> A_IWL<61191> A_IWL<61190> A_IWL<61189> A_IWL<61188> A_IWL<61187> A_IWL<61186> A_IWL<61185> A_IWL<61184> A_IWL<61183> A_IWL<61182> A_IWL<61181> A_IWL<61180> A_IWL<61179> A_IWL<61178> A_IWL<61177> A_IWL<61176> A_IWL<61175> A_IWL<61174> A_IWL<61173> A_IWL<61172> A_IWL<61171> A_IWL<61170> A_IWL<61169> A_IWL<61168> A_IWL<61167> A_IWL<61166> A_IWL<61165> A_IWL<61164> A_IWL<61163> A_IWL<61162> A_IWL<61161> A_IWL<61160> A_IWL<61159> A_IWL<61158> A_IWL<61157> A_IWL<61156> A_IWL<61155> A_IWL<61154> A_IWL<61153> A_IWL<61152> A_IWL<61151> A_IWL<61150> A_IWL<61149> A_IWL<61148> A_IWL<61147> A_IWL<61146> A_IWL<61145> A_IWL<61144> A_IWL<61143> A_IWL<61142> A_IWL<61141> A_IWL<61140> A_IWL<61139> A_IWL<61138> A_IWL<61137> A_IWL<61136> A_IWL<61135> A_IWL<61134> A_IWL<61133> A_IWL<61132> A_IWL<61131> A_IWL<61130> A_IWL<61129> A_IWL<61128> A_IWL<61127> A_IWL<61126> A_IWL<61125> A_IWL<61124> A_IWL<61123> A_IWL<61122> A_IWL<61121> A_IWL<61120> A_IWL<61119> A_IWL<61118> A_IWL<61117> A_IWL<61116> A_IWL<61115> A_IWL<61114> A_IWL<61113> A_IWL<61112> A_IWL<61111> A_IWL<61110> A_IWL<61109> A_IWL<61108> A_IWL<61107> A_IWL<61106> A_IWL<61105> A_IWL<61104> A_IWL<61103> A_IWL<61102> A_IWL<61101> A_IWL<61100> A_IWL<61099> A_IWL<61098> A_IWL<61097> A_IWL<61096> A_IWL<61095> A_IWL<61094> A_IWL<61093> A_IWL<61092> A_IWL<61091> A_IWL<61090> A_IWL<61089> A_IWL<61088> A_IWL<61087> A_IWL<61086> A_IWL<61085> A_IWL<61084> A_IWL<61083> A_IWL<61082> A_IWL<61081> A_IWL<61080> A_IWL<61079> A_IWL<61078> A_IWL<61077> A_IWL<61076> A_IWL<61075> A_IWL<61074> A_IWL<61073> A_IWL<61072> A_IWL<61071> A_IWL<61070> A_IWL<61069> A_IWL<61068> A_IWL<61067> A_IWL<61066> A_IWL<61065> A_IWL<61064> A_IWL<61063> A_IWL<61062> A_IWL<61061> A_IWL<61060> A_IWL<61059> A_IWL<61058> A_IWL<61057> A_IWL<61056> A_IWL<61055> A_IWL<61054> A_IWL<61053> A_IWL<61052> A_IWL<61051> A_IWL<61050> A_IWL<61049> A_IWL<61048> A_IWL<61047> A_IWL<61046> A_IWL<61045> A_IWL<61044> A_IWL<61043> A_IWL<61042> A_IWL<61041> A_IWL<61040> A_IWL<61039> A_IWL<61038> A_IWL<61037> A_IWL<61036> A_IWL<61035> A_IWL<61034> A_IWL<61033> A_IWL<61032> A_IWL<61031> A_IWL<61030> A_IWL<61029> A_IWL<61028> A_IWL<61027> A_IWL<61026> A_IWL<61025> A_IWL<61024> A_IWL<61023> A_IWL<61022> A_IWL<61021> A_IWL<61020> A_IWL<61019> A_IWL<61018> A_IWL<61017> A_IWL<61016> A_IWL<61015> A_IWL<61014> A_IWL<61013> A_IWL<61012> A_IWL<61011> A_IWL<61010> A_IWL<61009> A_IWL<61008> A_IWL<61007> A_IWL<61006> A_IWL<61005> A_IWL<61004> A_IWL<61003> A_IWL<61002> A_IWL<61001> A_IWL<61000> A_IWL<60999> A_IWL<60998> A_IWL<60997> A_IWL<60996> A_IWL<60995> A_IWL<60994> A_IWL<60993> A_IWL<60992> A_IWL<60991> A_IWL<60990> A_IWL<60989> A_IWL<60988> A_IWL<60987> A_IWL<60986> A_IWL<60985> A_IWL<60984> A_IWL<60983> A_IWL<60982> A_IWL<60981> A_IWL<60980> A_IWL<60979> A_IWL<60978> A_IWL<60977> A_IWL<60976> A_IWL<60975> A_IWL<60974> A_IWL<60973> A_IWL<60972> A_IWL<60971> A_IWL<60970> A_IWL<60969> A_IWL<60968> A_IWL<60967> A_IWL<60966> A_IWL<60965> A_IWL<60964> A_IWL<60963> A_IWL<60962> A_IWL<60961> A_IWL<60960> A_IWL<60959> A_IWL<60958> A_IWL<60957> A_IWL<60956> A_IWL<60955> A_IWL<60954> A_IWL<60953> A_IWL<60952> A_IWL<60951> A_IWL<60950> A_IWL<60949> A_IWL<60948> A_IWL<60947> A_IWL<60946> A_IWL<60945> A_IWL<60944> A_IWL<60943> A_IWL<60942> A_IWL<60941> A_IWL<60940> A_IWL<60939> A_IWL<60938> A_IWL<60937> A_IWL<60936> A_IWL<60935> A_IWL<60934> A_IWL<60933> A_IWL<60932> A_IWL<60931> A_IWL<60930> A_IWL<60929> A_IWL<60928> A_IWL<61951> A_IWL<61950> A_IWL<61949> A_IWL<61948> A_IWL<61947> A_IWL<61946> A_IWL<61945> A_IWL<61944> A_IWL<61943> A_IWL<61942> A_IWL<61941> A_IWL<61940> A_IWL<61939> A_IWL<61938> A_IWL<61937> A_IWL<61936> A_IWL<61935> A_IWL<61934> A_IWL<61933> A_IWL<61932> A_IWL<61931> A_IWL<61930> A_IWL<61929> A_IWL<61928> A_IWL<61927> A_IWL<61926> A_IWL<61925> A_IWL<61924> A_IWL<61923> A_IWL<61922> A_IWL<61921> A_IWL<61920> A_IWL<61919> A_IWL<61918> A_IWL<61917> A_IWL<61916> A_IWL<61915> A_IWL<61914> A_IWL<61913> A_IWL<61912> A_IWL<61911> A_IWL<61910> A_IWL<61909> A_IWL<61908> A_IWL<61907> A_IWL<61906> A_IWL<61905> A_IWL<61904> A_IWL<61903> A_IWL<61902> A_IWL<61901> A_IWL<61900> A_IWL<61899> A_IWL<61898> A_IWL<61897> A_IWL<61896> A_IWL<61895> A_IWL<61894> A_IWL<61893> A_IWL<61892> A_IWL<61891> A_IWL<61890> A_IWL<61889> A_IWL<61888> A_IWL<61887> A_IWL<61886> A_IWL<61885> A_IWL<61884> A_IWL<61883> A_IWL<61882> A_IWL<61881> A_IWL<61880> A_IWL<61879> A_IWL<61878> A_IWL<61877> A_IWL<61876> A_IWL<61875> A_IWL<61874> A_IWL<61873> A_IWL<61872> A_IWL<61871> A_IWL<61870> A_IWL<61869> A_IWL<61868> A_IWL<61867> A_IWL<61866> A_IWL<61865> A_IWL<61864> A_IWL<61863> A_IWL<61862> A_IWL<61861> A_IWL<61860> A_IWL<61859> A_IWL<61858> A_IWL<61857> A_IWL<61856> A_IWL<61855> A_IWL<61854> A_IWL<61853> A_IWL<61852> A_IWL<61851> A_IWL<61850> A_IWL<61849> A_IWL<61848> A_IWL<61847> A_IWL<61846> A_IWL<61845> A_IWL<61844> A_IWL<61843> A_IWL<61842> A_IWL<61841> A_IWL<61840> A_IWL<61839> A_IWL<61838> A_IWL<61837> A_IWL<61836> A_IWL<61835> A_IWL<61834> A_IWL<61833> A_IWL<61832> A_IWL<61831> A_IWL<61830> A_IWL<61829> A_IWL<61828> A_IWL<61827> A_IWL<61826> A_IWL<61825> A_IWL<61824> A_IWL<61823> A_IWL<61822> A_IWL<61821> A_IWL<61820> A_IWL<61819> A_IWL<61818> A_IWL<61817> A_IWL<61816> A_IWL<61815> A_IWL<61814> A_IWL<61813> A_IWL<61812> A_IWL<61811> A_IWL<61810> A_IWL<61809> A_IWL<61808> A_IWL<61807> A_IWL<61806> A_IWL<61805> A_IWL<61804> A_IWL<61803> A_IWL<61802> A_IWL<61801> A_IWL<61800> A_IWL<61799> A_IWL<61798> A_IWL<61797> A_IWL<61796> A_IWL<61795> A_IWL<61794> A_IWL<61793> A_IWL<61792> A_IWL<61791> A_IWL<61790> A_IWL<61789> A_IWL<61788> A_IWL<61787> A_IWL<61786> A_IWL<61785> A_IWL<61784> A_IWL<61783> A_IWL<61782> A_IWL<61781> A_IWL<61780> A_IWL<61779> A_IWL<61778> A_IWL<61777> A_IWL<61776> A_IWL<61775> A_IWL<61774> A_IWL<61773> A_IWL<61772> A_IWL<61771> A_IWL<61770> A_IWL<61769> A_IWL<61768> A_IWL<61767> A_IWL<61766> A_IWL<61765> A_IWL<61764> A_IWL<61763> A_IWL<61762> A_IWL<61761> A_IWL<61760> A_IWL<61759> A_IWL<61758> A_IWL<61757> A_IWL<61756> A_IWL<61755> A_IWL<61754> A_IWL<61753> A_IWL<61752> A_IWL<61751> A_IWL<61750> A_IWL<61749> A_IWL<61748> A_IWL<61747> A_IWL<61746> A_IWL<61745> A_IWL<61744> A_IWL<61743> A_IWL<61742> A_IWL<61741> A_IWL<61740> A_IWL<61739> A_IWL<61738> A_IWL<61737> A_IWL<61736> A_IWL<61735> A_IWL<61734> A_IWL<61733> A_IWL<61732> A_IWL<61731> A_IWL<61730> A_IWL<61729> A_IWL<61728> A_IWL<61727> A_IWL<61726> A_IWL<61725> A_IWL<61724> A_IWL<61723> A_IWL<61722> A_IWL<61721> A_IWL<61720> A_IWL<61719> A_IWL<61718> A_IWL<61717> A_IWL<61716> A_IWL<61715> A_IWL<61714> A_IWL<61713> A_IWL<61712> A_IWL<61711> A_IWL<61710> A_IWL<61709> A_IWL<61708> A_IWL<61707> A_IWL<61706> A_IWL<61705> A_IWL<61704> A_IWL<61703> A_IWL<61702> A_IWL<61701> A_IWL<61700> A_IWL<61699> A_IWL<61698> A_IWL<61697> A_IWL<61696> A_IWL<61695> A_IWL<61694> A_IWL<61693> A_IWL<61692> A_IWL<61691> A_IWL<61690> A_IWL<61689> A_IWL<61688> A_IWL<61687> A_IWL<61686> A_IWL<61685> A_IWL<61684> A_IWL<61683> A_IWL<61682> A_IWL<61681> A_IWL<61680> A_IWL<61679> A_IWL<61678> A_IWL<61677> A_IWL<61676> A_IWL<61675> A_IWL<61674> A_IWL<61673> A_IWL<61672> A_IWL<61671> A_IWL<61670> A_IWL<61669> A_IWL<61668> A_IWL<61667> A_IWL<61666> A_IWL<61665> A_IWL<61664> A_IWL<61663> A_IWL<61662> A_IWL<61661> A_IWL<61660> A_IWL<61659> A_IWL<61658> A_IWL<61657> A_IWL<61656> A_IWL<61655> A_IWL<61654> A_IWL<61653> A_IWL<61652> A_IWL<61651> A_IWL<61650> A_IWL<61649> A_IWL<61648> A_IWL<61647> A_IWL<61646> A_IWL<61645> A_IWL<61644> A_IWL<61643> A_IWL<61642> A_IWL<61641> A_IWL<61640> A_IWL<61639> A_IWL<61638> A_IWL<61637> A_IWL<61636> A_IWL<61635> A_IWL<61634> A_IWL<61633> A_IWL<61632> A_IWL<61631> A_IWL<61630> A_IWL<61629> A_IWL<61628> A_IWL<61627> A_IWL<61626> A_IWL<61625> A_IWL<61624> A_IWL<61623> A_IWL<61622> A_IWL<61621> A_IWL<61620> A_IWL<61619> A_IWL<61618> A_IWL<61617> A_IWL<61616> A_IWL<61615> A_IWL<61614> A_IWL<61613> A_IWL<61612> A_IWL<61611> A_IWL<61610> A_IWL<61609> A_IWL<61608> A_IWL<61607> A_IWL<61606> A_IWL<61605> A_IWL<61604> A_IWL<61603> A_IWL<61602> A_IWL<61601> A_IWL<61600> A_IWL<61599> A_IWL<61598> A_IWL<61597> A_IWL<61596> A_IWL<61595> A_IWL<61594> A_IWL<61593> A_IWL<61592> A_IWL<61591> A_IWL<61590> A_IWL<61589> A_IWL<61588> A_IWL<61587> A_IWL<61586> A_IWL<61585> A_IWL<61584> A_IWL<61583> A_IWL<61582> A_IWL<61581> A_IWL<61580> A_IWL<61579> A_IWL<61578> A_IWL<61577> A_IWL<61576> A_IWL<61575> A_IWL<61574> A_IWL<61573> A_IWL<61572> A_IWL<61571> A_IWL<61570> A_IWL<61569> A_IWL<61568> A_IWL<61567> A_IWL<61566> A_IWL<61565> A_IWL<61564> A_IWL<61563> A_IWL<61562> A_IWL<61561> A_IWL<61560> A_IWL<61559> A_IWL<61558> A_IWL<61557> A_IWL<61556> A_IWL<61555> A_IWL<61554> A_IWL<61553> A_IWL<61552> A_IWL<61551> A_IWL<61550> A_IWL<61549> A_IWL<61548> A_IWL<61547> A_IWL<61546> A_IWL<61545> A_IWL<61544> A_IWL<61543> A_IWL<61542> A_IWL<61541> A_IWL<61540> A_IWL<61539> A_IWL<61538> A_IWL<61537> A_IWL<61536> A_IWL<61535> A_IWL<61534> A_IWL<61533> A_IWL<61532> A_IWL<61531> A_IWL<61530> A_IWL<61529> A_IWL<61528> A_IWL<61527> A_IWL<61526> A_IWL<61525> A_IWL<61524> A_IWL<61523> A_IWL<61522> A_IWL<61521> A_IWL<61520> A_IWL<61519> A_IWL<61518> A_IWL<61517> A_IWL<61516> A_IWL<61515> A_IWL<61514> A_IWL<61513> A_IWL<61512> A_IWL<61511> A_IWL<61510> A_IWL<61509> A_IWL<61508> A_IWL<61507> A_IWL<61506> A_IWL<61505> A_IWL<61504> A_IWL<61503> A_IWL<61502> A_IWL<61501> A_IWL<61500> A_IWL<61499> A_IWL<61498> A_IWL<61497> A_IWL<61496> A_IWL<61495> A_IWL<61494> A_IWL<61493> A_IWL<61492> A_IWL<61491> A_IWL<61490> A_IWL<61489> A_IWL<61488> A_IWL<61487> A_IWL<61486> A_IWL<61485> A_IWL<61484> A_IWL<61483> A_IWL<61482> A_IWL<61481> A_IWL<61480> A_IWL<61479> A_IWL<61478> A_IWL<61477> A_IWL<61476> A_IWL<61475> A_IWL<61474> A_IWL<61473> A_IWL<61472> A_IWL<61471> A_IWL<61470> A_IWL<61469> A_IWL<61468> A_IWL<61467> A_IWL<61466> A_IWL<61465> A_IWL<61464> A_IWL<61463> A_IWL<61462> A_IWL<61461> A_IWL<61460> A_IWL<61459> A_IWL<61458> A_IWL<61457> A_IWL<61456> A_IWL<61455> A_IWL<61454> A_IWL<61453> A_IWL<61452> A_IWL<61451> A_IWL<61450> A_IWL<61449> A_IWL<61448> A_IWL<61447> A_IWL<61446> A_IWL<61445> A_IWL<61444> A_IWL<61443> A_IWL<61442> A_IWL<61441> A_IWL<61440> VDD_CORE VSS / RM_IHPSG13_8192x32_c4_1P_COLUMN_pcell_0 +XCOL<119> A_BLC<239> A_BLC<238> A_BLC_TOP<239> A_BLC_TOP<238> A_BLT<239> A_BLT<238> A_BLT_TOP<239> A_BLT_TOP<238> A_IWL<60927> A_IWL<60926> A_IWL<60925> A_IWL<60924> A_IWL<60923> A_IWL<60922> A_IWL<60921> A_IWL<60920> A_IWL<60919> A_IWL<60918> A_IWL<60917> A_IWL<60916> A_IWL<60915> A_IWL<60914> A_IWL<60913> A_IWL<60912> A_IWL<60911> A_IWL<60910> A_IWL<60909> A_IWL<60908> A_IWL<60907> A_IWL<60906> A_IWL<60905> A_IWL<60904> A_IWL<60903> A_IWL<60902> A_IWL<60901> A_IWL<60900> A_IWL<60899> A_IWL<60898> A_IWL<60897> A_IWL<60896> A_IWL<60895> A_IWL<60894> A_IWL<60893> A_IWL<60892> A_IWL<60891> A_IWL<60890> A_IWL<60889> A_IWL<60888> A_IWL<60887> A_IWL<60886> A_IWL<60885> A_IWL<60884> A_IWL<60883> A_IWL<60882> A_IWL<60881> A_IWL<60880> A_IWL<60879> A_IWL<60878> A_IWL<60877> A_IWL<60876> A_IWL<60875> A_IWL<60874> A_IWL<60873> A_IWL<60872> A_IWL<60871> A_IWL<60870> A_IWL<60869> A_IWL<60868> A_IWL<60867> A_IWL<60866> A_IWL<60865> A_IWL<60864> A_IWL<60863> A_IWL<60862> A_IWL<60861> A_IWL<60860> A_IWL<60859> A_IWL<60858> A_IWL<60857> A_IWL<60856> A_IWL<60855> A_IWL<60854> A_IWL<60853> A_IWL<60852> A_IWL<60851> A_IWL<60850> A_IWL<60849> A_IWL<60848> A_IWL<60847> A_IWL<60846> A_IWL<60845> A_IWL<60844> A_IWL<60843> A_IWL<60842> A_IWL<60841> A_IWL<60840> A_IWL<60839> A_IWL<60838> A_IWL<60837> A_IWL<60836> A_IWL<60835> A_IWL<60834> A_IWL<60833> A_IWL<60832> A_IWL<60831> A_IWL<60830> A_IWL<60829> A_IWL<60828> A_IWL<60827> A_IWL<60826> A_IWL<60825> A_IWL<60824> A_IWL<60823> A_IWL<60822> A_IWL<60821> A_IWL<60820> A_IWL<60819> A_IWL<60818> A_IWL<60817> A_IWL<60816> A_IWL<60815> A_IWL<60814> A_IWL<60813> A_IWL<60812> A_IWL<60811> A_IWL<60810> A_IWL<60809> A_IWL<60808> A_IWL<60807> A_IWL<60806> A_IWL<60805> A_IWL<60804> A_IWL<60803> A_IWL<60802> A_IWL<60801> A_IWL<60800> A_IWL<60799> A_IWL<60798> A_IWL<60797> A_IWL<60796> A_IWL<60795> A_IWL<60794> A_IWL<60793> A_IWL<60792> A_IWL<60791> A_IWL<60790> A_IWL<60789> A_IWL<60788> A_IWL<60787> A_IWL<60786> A_IWL<60785> A_IWL<60784> A_IWL<60783> A_IWL<60782> A_IWL<60781> A_IWL<60780> A_IWL<60779> A_IWL<60778> A_IWL<60777> A_IWL<60776> A_IWL<60775> A_IWL<60774> A_IWL<60773> A_IWL<60772> A_IWL<60771> A_IWL<60770> A_IWL<60769> A_IWL<60768> A_IWL<60767> A_IWL<60766> A_IWL<60765> A_IWL<60764> A_IWL<60763> A_IWL<60762> A_IWL<60761> A_IWL<60760> A_IWL<60759> A_IWL<60758> A_IWL<60757> A_IWL<60756> A_IWL<60755> A_IWL<60754> A_IWL<60753> A_IWL<60752> A_IWL<60751> A_IWL<60750> A_IWL<60749> A_IWL<60748> A_IWL<60747> A_IWL<60746> A_IWL<60745> A_IWL<60744> A_IWL<60743> A_IWL<60742> A_IWL<60741> A_IWL<60740> A_IWL<60739> A_IWL<60738> A_IWL<60737> A_IWL<60736> A_IWL<60735> A_IWL<60734> A_IWL<60733> A_IWL<60732> A_IWL<60731> A_IWL<60730> A_IWL<60729> A_IWL<60728> A_IWL<60727> A_IWL<60726> A_IWL<60725> A_IWL<60724> A_IWL<60723> A_IWL<60722> A_IWL<60721> A_IWL<60720> A_IWL<60719> A_IWL<60718> A_IWL<60717> A_IWL<60716> A_IWL<60715> A_IWL<60714> A_IWL<60713> A_IWL<60712> A_IWL<60711> A_IWL<60710> A_IWL<60709> A_IWL<60708> A_IWL<60707> A_IWL<60706> A_IWL<60705> A_IWL<60704> A_IWL<60703> A_IWL<60702> A_IWL<60701> A_IWL<60700> A_IWL<60699> A_IWL<60698> A_IWL<60697> A_IWL<60696> A_IWL<60695> A_IWL<60694> A_IWL<60693> A_IWL<60692> A_IWL<60691> A_IWL<60690> A_IWL<60689> A_IWL<60688> A_IWL<60687> A_IWL<60686> A_IWL<60685> A_IWL<60684> A_IWL<60683> A_IWL<60682> A_IWL<60681> A_IWL<60680> A_IWL<60679> A_IWL<60678> A_IWL<60677> A_IWL<60676> A_IWL<60675> A_IWL<60674> A_IWL<60673> A_IWL<60672> A_IWL<60671> A_IWL<60670> A_IWL<60669> A_IWL<60668> A_IWL<60667> A_IWL<60666> A_IWL<60665> A_IWL<60664> A_IWL<60663> A_IWL<60662> A_IWL<60661> A_IWL<60660> A_IWL<60659> A_IWL<60658> A_IWL<60657> A_IWL<60656> A_IWL<60655> A_IWL<60654> A_IWL<60653> A_IWL<60652> A_IWL<60651> A_IWL<60650> A_IWL<60649> A_IWL<60648> A_IWL<60647> A_IWL<60646> A_IWL<60645> A_IWL<60644> A_IWL<60643> A_IWL<60642> A_IWL<60641> A_IWL<60640> A_IWL<60639> A_IWL<60638> A_IWL<60637> A_IWL<60636> A_IWL<60635> A_IWL<60634> A_IWL<60633> A_IWL<60632> A_IWL<60631> A_IWL<60630> A_IWL<60629> A_IWL<60628> A_IWL<60627> A_IWL<60626> A_IWL<60625> A_IWL<60624> A_IWL<60623> A_IWL<60622> A_IWL<60621> A_IWL<60620> A_IWL<60619> A_IWL<60618> A_IWL<60617> A_IWL<60616> A_IWL<60615> A_IWL<60614> A_IWL<60613> A_IWL<60612> A_IWL<60611> A_IWL<60610> A_IWL<60609> A_IWL<60608> A_IWL<60607> A_IWL<60606> A_IWL<60605> A_IWL<60604> A_IWL<60603> A_IWL<60602> A_IWL<60601> A_IWL<60600> A_IWL<60599> A_IWL<60598> A_IWL<60597> A_IWL<60596> A_IWL<60595> A_IWL<60594> A_IWL<60593> A_IWL<60592> A_IWL<60591> A_IWL<60590> A_IWL<60589> A_IWL<60588> A_IWL<60587> A_IWL<60586> A_IWL<60585> A_IWL<60584> A_IWL<60583> A_IWL<60582> A_IWL<60581> A_IWL<60580> A_IWL<60579> A_IWL<60578> A_IWL<60577> A_IWL<60576> A_IWL<60575> A_IWL<60574> A_IWL<60573> A_IWL<60572> A_IWL<60571> A_IWL<60570> A_IWL<60569> A_IWL<60568> A_IWL<60567> A_IWL<60566> A_IWL<60565> A_IWL<60564> A_IWL<60563> A_IWL<60562> A_IWL<60561> A_IWL<60560> A_IWL<60559> A_IWL<60558> A_IWL<60557> A_IWL<60556> A_IWL<60555> A_IWL<60554> A_IWL<60553> A_IWL<60552> A_IWL<60551> A_IWL<60550> A_IWL<60549> A_IWL<60548> A_IWL<60547> A_IWL<60546> A_IWL<60545> A_IWL<60544> A_IWL<60543> A_IWL<60542> A_IWL<60541> A_IWL<60540> A_IWL<60539> A_IWL<60538> A_IWL<60537> A_IWL<60536> A_IWL<60535> A_IWL<60534> A_IWL<60533> A_IWL<60532> A_IWL<60531> A_IWL<60530> A_IWL<60529> A_IWL<60528> A_IWL<60527> A_IWL<60526> A_IWL<60525> A_IWL<60524> A_IWL<60523> A_IWL<60522> A_IWL<60521> A_IWL<60520> A_IWL<60519> A_IWL<60518> A_IWL<60517> A_IWL<60516> A_IWL<60515> A_IWL<60514> A_IWL<60513> A_IWL<60512> A_IWL<60511> A_IWL<60510> A_IWL<60509> A_IWL<60508> A_IWL<60507> A_IWL<60506> A_IWL<60505> A_IWL<60504> A_IWL<60503> A_IWL<60502> A_IWL<60501> A_IWL<60500> A_IWL<60499> A_IWL<60498> A_IWL<60497> A_IWL<60496> A_IWL<60495> A_IWL<60494> A_IWL<60493> A_IWL<60492> A_IWL<60491> A_IWL<60490> A_IWL<60489> A_IWL<60488> A_IWL<60487> A_IWL<60486> A_IWL<60485> A_IWL<60484> A_IWL<60483> A_IWL<60482> A_IWL<60481> A_IWL<60480> A_IWL<60479> A_IWL<60478> A_IWL<60477> A_IWL<60476> A_IWL<60475> A_IWL<60474> A_IWL<60473> A_IWL<60472> A_IWL<60471> A_IWL<60470> A_IWL<60469> A_IWL<60468> A_IWL<60467> A_IWL<60466> A_IWL<60465> A_IWL<60464> A_IWL<60463> A_IWL<60462> A_IWL<60461> A_IWL<60460> A_IWL<60459> A_IWL<60458> A_IWL<60457> A_IWL<60456> A_IWL<60455> A_IWL<60454> A_IWL<60453> A_IWL<60452> A_IWL<60451> A_IWL<60450> A_IWL<60449> A_IWL<60448> A_IWL<60447> A_IWL<60446> A_IWL<60445> A_IWL<60444> A_IWL<60443> A_IWL<60442> A_IWL<60441> A_IWL<60440> A_IWL<60439> A_IWL<60438> A_IWL<60437> A_IWL<60436> A_IWL<60435> A_IWL<60434> A_IWL<60433> A_IWL<60432> A_IWL<60431> A_IWL<60430> A_IWL<60429> A_IWL<60428> A_IWL<60427> A_IWL<60426> A_IWL<60425> A_IWL<60424> A_IWL<60423> A_IWL<60422> A_IWL<60421> A_IWL<60420> A_IWL<60419> A_IWL<60418> A_IWL<60417> A_IWL<60416> A_IWL<61439> A_IWL<61438> A_IWL<61437> A_IWL<61436> A_IWL<61435> A_IWL<61434> A_IWL<61433> A_IWL<61432> A_IWL<61431> A_IWL<61430> A_IWL<61429> A_IWL<61428> A_IWL<61427> A_IWL<61426> A_IWL<61425> A_IWL<61424> A_IWL<61423> A_IWL<61422> A_IWL<61421> A_IWL<61420> A_IWL<61419> A_IWL<61418> A_IWL<61417> A_IWL<61416> A_IWL<61415> A_IWL<61414> A_IWL<61413> A_IWL<61412> A_IWL<61411> A_IWL<61410> A_IWL<61409> A_IWL<61408> A_IWL<61407> A_IWL<61406> A_IWL<61405> A_IWL<61404> A_IWL<61403> A_IWL<61402> A_IWL<61401> A_IWL<61400> A_IWL<61399> A_IWL<61398> A_IWL<61397> A_IWL<61396> A_IWL<61395> A_IWL<61394> A_IWL<61393> A_IWL<61392> A_IWL<61391> A_IWL<61390> A_IWL<61389> A_IWL<61388> A_IWL<61387> A_IWL<61386> A_IWL<61385> A_IWL<61384> A_IWL<61383> A_IWL<61382> A_IWL<61381> A_IWL<61380> A_IWL<61379> A_IWL<61378> A_IWL<61377> A_IWL<61376> A_IWL<61375> A_IWL<61374> A_IWL<61373> A_IWL<61372> A_IWL<61371> A_IWL<61370> A_IWL<61369> A_IWL<61368> A_IWL<61367> A_IWL<61366> A_IWL<61365> A_IWL<61364> A_IWL<61363> A_IWL<61362> A_IWL<61361> A_IWL<61360> A_IWL<61359> A_IWL<61358> A_IWL<61357> A_IWL<61356> A_IWL<61355> A_IWL<61354> A_IWL<61353> A_IWL<61352> A_IWL<61351> A_IWL<61350> A_IWL<61349> A_IWL<61348> A_IWL<61347> A_IWL<61346> A_IWL<61345> A_IWL<61344> A_IWL<61343> A_IWL<61342> A_IWL<61341> A_IWL<61340> A_IWL<61339> A_IWL<61338> A_IWL<61337> A_IWL<61336> A_IWL<61335> A_IWL<61334> A_IWL<61333> A_IWL<61332> A_IWL<61331> A_IWL<61330> A_IWL<61329> A_IWL<61328> A_IWL<61327> A_IWL<61326> A_IWL<61325> A_IWL<61324> A_IWL<61323> A_IWL<61322> A_IWL<61321> A_IWL<61320> A_IWL<61319> A_IWL<61318> A_IWL<61317> A_IWL<61316> A_IWL<61315> A_IWL<61314> A_IWL<61313> A_IWL<61312> A_IWL<61311> A_IWL<61310> A_IWL<61309> A_IWL<61308> A_IWL<61307> A_IWL<61306> A_IWL<61305> A_IWL<61304> A_IWL<61303> A_IWL<61302> A_IWL<61301> A_IWL<61300> A_IWL<61299> A_IWL<61298> A_IWL<61297> A_IWL<61296> A_IWL<61295> A_IWL<61294> A_IWL<61293> A_IWL<61292> A_IWL<61291> A_IWL<61290> A_IWL<61289> A_IWL<61288> A_IWL<61287> A_IWL<61286> A_IWL<61285> A_IWL<61284> A_IWL<61283> A_IWL<61282> A_IWL<61281> A_IWL<61280> A_IWL<61279> A_IWL<61278> A_IWL<61277> A_IWL<61276> A_IWL<61275> A_IWL<61274> A_IWL<61273> A_IWL<61272> A_IWL<61271> A_IWL<61270> A_IWL<61269> A_IWL<61268> A_IWL<61267> A_IWL<61266> A_IWL<61265> A_IWL<61264> A_IWL<61263> A_IWL<61262> A_IWL<61261> A_IWL<61260> A_IWL<61259> A_IWL<61258> A_IWL<61257> A_IWL<61256> A_IWL<61255> A_IWL<61254> A_IWL<61253> A_IWL<61252> A_IWL<61251> A_IWL<61250> A_IWL<61249> A_IWL<61248> A_IWL<61247> A_IWL<61246> A_IWL<61245> A_IWL<61244> A_IWL<61243> A_IWL<61242> A_IWL<61241> A_IWL<61240> A_IWL<61239> A_IWL<61238> A_IWL<61237> A_IWL<61236> A_IWL<61235> A_IWL<61234> A_IWL<61233> A_IWL<61232> A_IWL<61231> A_IWL<61230> A_IWL<61229> A_IWL<61228> A_IWL<61227> A_IWL<61226> A_IWL<61225> A_IWL<61224> A_IWL<61223> A_IWL<61222> A_IWL<61221> A_IWL<61220> A_IWL<61219> A_IWL<61218> A_IWL<61217> A_IWL<61216> A_IWL<61215> A_IWL<61214> A_IWL<61213> A_IWL<61212> A_IWL<61211> A_IWL<61210> A_IWL<61209> A_IWL<61208> A_IWL<61207> A_IWL<61206> A_IWL<61205> A_IWL<61204> A_IWL<61203> A_IWL<61202> A_IWL<61201> A_IWL<61200> A_IWL<61199> A_IWL<61198> A_IWL<61197> A_IWL<61196> A_IWL<61195> A_IWL<61194> A_IWL<61193> A_IWL<61192> A_IWL<61191> A_IWL<61190> A_IWL<61189> A_IWL<61188> A_IWL<61187> A_IWL<61186> A_IWL<61185> A_IWL<61184> A_IWL<61183> A_IWL<61182> A_IWL<61181> A_IWL<61180> A_IWL<61179> A_IWL<61178> A_IWL<61177> A_IWL<61176> A_IWL<61175> A_IWL<61174> A_IWL<61173> A_IWL<61172> A_IWL<61171> A_IWL<61170> A_IWL<61169> A_IWL<61168> A_IWL<61167> A_IWL<61166> A_IWL<61165> A_IWL<61164> A_IWL<61163> A_IWL<61162> A_IWL<61161> A_IWL<61160> A_IWL<61159> A_IWL<61158> A_IWL<61157> A_IWL<61156> A_IWL<61155> A_IWL<61154> A_IWL<61153> A_IWL<61152> A_IWL<61151> A_IWL<61150> A_IWL<61149> A_IWL<61148> A_IWL<61147> A_IWL<61146> A_IWL<61145> A_IWL<61144> A_IWL<61143> A_IWL<61142> A_IWL<61141> A_IWL<61140> A_IWL<61139> A_IWL<61138> A_IWL<61137> A_IWL<61136> A_IWL<61135> A_IWL<61134> A_IWL<61133> A_IWL<61132> A_IWL<61131> A_IWL<61130> A_IWL<61129> A_IWL<61128> A_IWL<61127> A_IWL<61126> A_IWL<61125> A_IWL<61124> A_IWL<61123> A_IWL<61122> A_IWL<61121> A_IWL<61120> A_IWL<61119> A_IWL<61118> A_IWL<61117> A_IWL<61116> A_IWL<61115> A_IWL<61114> A_IWL<61113> A_IWL<61112> A_IWL<61111> A_IWL<61110> A_IWL<61109> A_IWL<61108> A_IWL<61107> A_IWL<61106> A_IWL<61105> A_IWL<61104> A_IWL<61103> A_IWL<61102> A_IWL<61101> A_IWL<61100> A_IWL<61099> A_IWL<61098> A_IWL<61097> A_IWL<61096> A_IWL<61095> A_IWL<61094> A_IWL<61093> A_IWL<61092> A_IWL<61091> A_IWL<61090> A_IWL<61089> A_IWL<61088> A_IWL<61087> A_IWL<61086> A_IWL<61085> A_IWL<61084> A_IWL<61083> A_IWL<61082> A_IWL<61081> A_IWL<61080> A_IWL<61079> A_IWL<61078> A_IWL<61077> A_IWL<61076> A_IWL<61075> A_IWL<61074> A_IWL<61073> A_IWL<61072> A_IWL<61071> A_IWL<61070> A_IWL<61069> A_IWL<61068> A_IWL<61067> A_IWL<61066> A_IWL<61065> A_IWL<61064> A_IWL<61063> A_IWL<61062> A_IWL<61061> A_IWL<61060> A_IWL<61059> A_IWL<61058> A_IWL<61057> A_IWL<61056> A_IWL<61055> A_IWL<61054> A_IWL<61053> A_IWL<61052> A_IWL<61051> A_IWL<61050> A_IWL<61049> A_IWL<61048> A_IWL<61047> A_IWL<61046> A_IWL<61045> A_IWL<61044> A_IWL<61043> A_IWL<61042> A_IWL<61041> A_IWL<61040> A_IWL<61039> A_IWL<61038> A_IWL<61037> A_IWL<61036> A_IWL<61035> A_IWL<61034> A_IWL<61033> A_IWL<61032> A_IWL<61031> A_IWL<61030> A_IWL<61029> A_IWL<61028> A_IWL<61027> A_IWL<61026> A_IWL<61025> A_IWL<61024> A_IWL<61023> A_IWL<61022> A_IWL<61021> A_IWL<61020> A_IWL<61019> A_IWL<61018> A_IWL<61017> A_IWL<61016> A_IWL<61015> A_IWL<61014> A_IWL<61013> A_IWL<61012> A_IWL<61011> A_IWL<61010> A_IWL<61009> A_IWL<61008> A_IWL<61007> A_IWL<61006> A_IWL<61005> A_IWL<61004> A_IWL<61003> A_IWL<61002> A_IWL<61001> A_IWL<61000> A_IWL<60999> A_IWL<60998> A_IWL<60997> A_IWL<60996> A_IWL<60995> A_IWL<60994> A_IWL<60993> A_IWL<60992> A_IWL<60991> A_IWL<60990> A_IWL<60989> A_IWL<60988> A_IWL<60987> A_IWL<60986> A_IWL<60985> A_IWL<60984> A_IWL<60983> A_IWL<60982> A_IWL<60981> A_IWL<60980> A_IWL<60979> A_IWL<60978> A_IWL<60977> A_IWL<60976> A_IWL<60975> A_IWL<60974> A_IWL<60973> A_IWL<60972> A_IWL<60971> A_IWL<60970> A_IWL<60969> A_IWL<60968> A_IWL<60967> A_IWL<60966> A_IWL<60965> A_IWL<60964> A_IWL<60963> A_IWL<60962> A_IWL<60961> A_IWL<60960> A_IWL<60959> A_IWL<60958> A_IWL<60957> A_IWL<60956> A_IWL<60955> A_IWL<60954> A_IWL<60953> A_IWL<60952> A_IWL<60951> A_IWL<60950> A_IWL<60949> A_IWL<60948> A_IWL<60947> A_IWL<60946> A_IWL<60945> A_IWL<60944> A_IWL<60943> A_IWL<60942> A_IWL<60941> A_IWL<60940> A_IWL<60939> A_IWL<60938> A_IWL<60937> A_IWL<60936> A_IWL<60935> A_IWL<60934> A_IWL<60933> A_IWL<60932> A_IWL<60931> A_IWL<60930> A_IWL<60929> A_IWL<60928> VDD_CORE VSS / RM_IHPSG13_8192x32_c4_1P_COLUMN_pcell_0 +XCOL<118> A_BLC<237> A_BLC<236> A_BLC_TOP<237> A_BLC_TOP<236> A_BLT<237> A_BLT<236> A_BLT_TOP<237> A_BLT_TOP<236> A_IWL<60415> A_IWL<60414> A_IWL<60413> A_IWL<60412> A_IWL<60411> A_IWL<60410> A_IWL<60409> A_IWL<60408> A_IWL<60407> A_IWL<60406> A_IWL<60405> A_IWL<60404> A_IWL<60403> A_IWL<60402> A_IWL<60401> A_IWL<60400> A_IWL<60399> A_IWL<60398> A_IWL<60397> A_IWL<60396> A_IWL<60395> A_IWL<60394> A_IWL<60393> A_IWL<60392> A_IWL<60391> A_IWL<60390> A_IWL<60389> A_IWL<60388> A_IWL<60387> A_IWL<60386> A_IWL<60385> A_IWL<60384> A_IWL<60383> A_IWL<60382> A_IWL<60381> A_IWL<60380> A_IWL<60379> A_IWL<60378> A_IWL<60377> A_IWL<60376> A_IWL<60375> A_IWL<60374> A_IWL<60373> A_IWL<60372> A_IWL<60371> A_IWL<60370> A_IWL<60369> A_IWL<60368> A_IWL<60367> A_IWL<60366> A_IWL<60365> A_IWL<60364> A_IWL<60363> A_IWL<60362> A_IWL<60361> A_IWL<60360> A_IWL<60359> A_IWL<60358> A_IWL<60357> A_IWL<60356> A_IWL<60355> A_IWL<60354> A_IWL<60353> A_IWL<60352> A_IWL<60351> A_IWL<60350> A_IWL<60349> A_IWL<60348> A_IWL<60347> A_IWL<60346> A_IWL<60345> A_IWL<60344> A_IWL<60343> A_IWL<60342> A_IWL<60341> A_IWL<60340> A_IWL<60339> A_IWL<60338> A_IWL<60337> A_IWL<60336> A_IWL<60335> A_IWL<60334> A_IWL<60333> A_IWL<60332> A_IWL<60331> A_IWL<60330> A_IWL<60329> A_IWL<60328> A_IWL<60327> A_IWL<60326> A_IWL<60325> A_IWL<60324> A_IWL<60323> A_IWL<60322> A_IWL<60321> A_IWL<60320> A_IWL<60319> A_IWL<60318> A_IWL<60317> A_IWL<60316> A_IWL<60315> A_IWL<60314> A_IWL<60313> A_IWL<60312> A_IWL<60311> A_IWL<60310> A_IWL<60309> A_IWL<60308> A_IWL<60307> A_IWL<60306> A_IWL<60305> A_IWL<60304> A_IWL<60303> A_IWL<60302> A_IWL<60301> A_IWL<60300> A_IWL<60299> A_IWL<60298> A_IWL<60297> A_IWL<60296> A_IWL<60295> A_IWL<60294> A_IWL<60293> A_IWL<60292> A_IWL<60291> A_IWL<60290> A_IWL<60289> A_IWL<60288> A_IWL<60287> A_IWL<60286> A_IWL<60285> A_IWL<60284> A_IWL<60283> A_IWL<60282> A_IWL<60281> A_IWL<60280> A_IWL<60279> A_IWL<60278> A_IWL<60277> A_IWL<60276> A_IWL<60275> A_IWL<60274> A_IWL<60273> A_IWL<60272> A_IWL<60271> A_IWL<60270> A_IWL<60269> A_IWL<60268> A_IWL<60267> A_IWL<60266> A_IWL<60265> A_IWL<60264> A_IWL<60263> A_IWL<60262> A_IWL<60261> A_IWL<60260> A_IWL<60259> A_IWL<60258> A_IWL<60257> A_IWL<60256> A_IWL<60255> A_IWL<60254> A_IWL<60253> A_IWL<60252> A_IWL<60251> A_IWL<60250> A_IWL<60249> A_IWL<60248> A_IWL<60247> A_IWL<60246> A_IWL<60245> A_IWL<60244> A_IWL<60243> A_IWL<60242> A_IWL<60241> A_IWL<60240> A_IWL<60239> A_IWL<60238> A_IWL<60237> A_IWL<60236> A_IWL<60235> A_IWL<60234> A_IWL<60233> A_IWL<60232> A_IWL<60231> A_IWL<60230> A_IWL<60229> A_IWL<60228> A_IWL<60227> A_IWL<60226> A_IWL<60225> A_IWL<60224> A_IWL<60223> A_IWL<60222> A_IWL<60221> A_IWL<60220> A_IWL<60219> A_IWL<60218> A_IWL<60217> A_IWL<60216> A_IWL<60215> A_IWL<60214> A_IWL<60213> A_IWL<60212> A_IWL<60211> A_IWL<60210> A_IWL<60209> A_IWL<60208> A_IWL<60207> A_IWL<60206> A_IWL<60205> A_IWL<60204> A_IWL<60203> A_IWL<60202> A_IWL<60201> A_IWL<60200> A_IWL<60199> A_IWL<60198> A_IWL<60197> A_IWL<60196> A_IWL<60195> A_IWL<60194> A_IWL<60193> A_IWL<60192> A_IWL<60191> A_IWL<60190> A_IWL<60189> A_IWL<60188> A_IWL<60187> A_IWL<60186> A_IWL<60185> A_IWL<60184> A_IWL<60183> A_IWL<60182> A_IWL<60181> A_IWL<60180> A_IWL<60179> A_IWL<60178> A_IWL<60177> A_IWL<60176> A_IWL<60175> A_IWL<60174> A_IWL<60173> A_IWL<60172> A_IWL<60171> A_IWL<60170> A_IWL<60169> A_IWL<60168> A_IWL<60167> A_IWL<60166> A_IWL<60165> A_IWL<60164> A_IWL<60163> A_IWL<60162> A_IWL<60161> A_IWL<60160> A_IWL<60159> A_IWL<60158> A_IWL<60157> A_IWL<60156> A_IWL<60155> A_IWL<60154> A_IWL<60153> A_IWL<60152> A_IWL<60151> A_IWL<60150> A_IWL<60149> A_IWL<60148> A_IWL<60147> A_IWL<60146> A_IWL<60145> A_IWL<60144> A_IWL<60143> A_IWL<60142> A_IWL<60141> A_IWL<60140> A_IWL<60139> A_IWL<60138> A_IWL<60137> A_IWL<60136> A_IWL<60135> A_IWL<60134> A_IWL<60133> A_IWL<60132> A_IWL<60131> A_IWL<60130> A_IWL<60129> A_IWL<60128> A_IWL<60127> A_IWL<60126> A_IWL<60125> A_IWL<60124> A_IWL<60123> A_IWL<60122> A_IWL<60121> A_IWL<60120> A_IWL<60119> A_IWL<60118> A_IWL<60117> A_IWL<60116> A_IWL<60115> A_IWL<60114> A_IWL<60113> A_IWL<60112> A_IWL<60111> A_IWL<60110> A_IWL<60109> A_IWL<60108> A_IWL<60107> A_IWL<60106> A_IWL<60105> A_IWL<60104> A_IWL<60103> A_IWL<60102> A_IWL<60101> A_IWL<60100> A_IWL<60099> A_IWL<60098> A_IWL<60097> A_IWL<60096> A_IWL<60095> A_IWL<60094> A_IWL<60093> A_IWL<60092> A_IWL<60091> A_IWL<60090> A_IWL<60089> A_IWL<60088> A_IWL<60087> A_IWL<60086> A_IWL<60085> A_IWL<60084> A_IWL<60083> A_IWL<60082> A_IWL<60081> A_IWL<60080> A_IWL<60079> A_IWL<60078> A_IWL<60077> A_IWL<60076> A_IWL<60075> A_IWL<60074> A_IWL<60073> A_IWL<60072> A_IWL<60071> A_IWL<60070> A_IWL<60069> A_IWL<60068> A_IWL<60067> A_IWL<60066> A_IWL<60065> A_IWL<60064> A_IWL<60063> A_IWL<60062> A_IWL<60061> A_IWL<60060> A_IWL<60059> A_IWL<60058> A_IWL<60057> A_IWL<60056> A_IWL<60055> A_IWL<60054> A_IWL<60053> A_IWL<60052> A_IWL<60051> A_IWL<60050> A_IWL<60049> A_IWL<60048> A_IWL<60047> A_IWL<60046> A_IWL<60045> A_IWL<60044> A_IWL<60043> A_IWL<60042> A_IWL<60041> A_IWL<60040> A_IWL<60039> A_IWL<60038> A_IWL<60037> A_IWL<60036> A_IWL<60035> A_IWL<60034> A_IWL<60033> A_IWL<60032> A_IWL<60031> A_IWL<60030> A_IWL<60029> A_IWL<60028> A_IWL<60027> A_IWL<60026> A_IWL<60025> A_IWL<60024> A_IWL<60023> A_IWL<60022> A_IWL<60021> A_IWL<60020> A_IWL<60019> A_IWL<60018> A_IWL<60017> A_IWL<60016> A_IWL<60015> A_IWL<60014> A_IWL<60013> A_IWL<60012> A_IWL<60011> A_IWL<60010> A_IWL<60009> A_IWL<60008> A_IWL<60007> A_IWL<60006> A_IWL<60005> A_IWL<60004> A_IWL<60003> A_IWL<60002> A_IWL<60001> A_IWL<60000> A_IWL<59999> A_IWL<59998> A_IWL<59997> A_IWL<59996> A_IWL<59995> A_IWL<59994> A_IWL<59993> A_IWL<59992> A_IWL<59991> A_IWL<59990> A_IWL<59989> A_IWL<59988> A_IWL<59987> A_IWL<59986> A_IWL<59985> A_IWL<59984> A_IWL<59983> A_IWL<59982> A_IWL<59981> A_IWL<59980> A_IWL<59979> A_IWL<59978> A_IWL<59977> A_IWL<59976> A_IWL<59975> A_IWL<59974> A_IWL<59973> A_IWL<59972> A_IWL<59971> A_IWL<59970> A_IWL<59969> A_IWL<59968> A_IWL<59967> A_IWL<59966> A_IWL<59965> A_IWL<59964> A_IWL<59963> A_IWL<59962> A_IWL<59961> A_IWL<59960> A_IWL<59959> A_IWL<59958> A_IWL<59957> A_IWL<59956> A_IWL<59955> A_IWL<59954> A_IWL<59953> A_IWL<59952> A_IWL<59951> A_IWL<59950> A_IWL<59949> A_IWL<59948> A_IWL<59947> A_IWL<59946> A_IWL<59945> A_IWL<59944> A_IWL<59943> A_IWL<59942> A_IWL<59941> A_IWL<59940> A_IWL<59939> A_IWL<59938> A_IWL<59937> A_IWL<59936> A_IWL<59935> A_IWL<59934> A_IWL<59933> A_IWL<59932> A_IWL<59931> A_IWL<59930> A_IWL<59929> A_IWL<59928> A_IWL<59927> A_IWL<59926> A_IWL<59925> A_IWL<59924> A_IWL<59923> A_IWL<59922> A_IWL<59921> A_IWL<59920> A_IWL<59919> A_IWL<59918> A_IWL<59917> A_IWL<59916> A_IWL<59915> A_IWL<59914> A_IWL<59913> A_IWL<59912> A_IWL<59911> A_IWL<59910> A_IWL<59909> A_IWL<59908> A_IWL<59907> A_IWL<59906> A_IWL<59905> A_IWL<59904> A_IWL<60927> A_IWL<60926> A_IWL<60925> A_IWL<60924> A_IWL<60923> A_IWL<60922> A_IWL<60921> A_IWL<60920> A_IWL<60919> A_IWL<60918> A_IWL<60917> A_IWL<60916> A_IWL<60915> A_IWL<60914> A_IWL<60913> A_IWL<60912> A_IWL<60911> A_IWL<60910> A_IWL<60909> A_IWL<60908> A_IWL<60907> A_IWL<60906> A_IWL<60905> A_IWL<60904> A_IWL<60903> A_IWL<60902> A_IWL<60901> A_IWL<60900> A_IWL<60899> A_IWL<60898> A_IWL<60897> A_IWL<60896> A_IWL<60895> A_IWL<60894> A_IWL<60893> A_IWL<60892> A_IWL<60891> A_IWL<60890> A_IWL<60889> A_IWL<60888> A_IWL<60887> A_IWL<60886> A_IWL<60885> A_IWL<60884> A_IWL<60883> A_IWL<60882> A_IWL<60881> A_IWL<60880> A_IWL<60879> A_IWL<60878> A_IWL<60877> A_IWL<60876> A_IWL<60875> A_IWL<60874> A_IWL<60873> A_IWL<60872> A_IWL<60871> A_IWL<60870> A_IWL<60869> A_IWL<60868> A_IWL<60867> A_IWL<60866> A_IWL<60865> A_IWL<60864> A_IWL<60863> A_IWL<60862> A_IWL<60861> A_IWL<60860> A_IWL<60859> A_IWL<60858> A_IWL<60857> A_IWL<60856> A_IWL<60855> A_IWL<60854> A_IWL<60853> A_IWL<60852> A_IWL<60851> A_IWL<60850> A_IWL<60849> A_IWL<60848> A_IWL<60847> A_IWL<60846> A_IWL<60845> A_IWL<60844> A_IWL<60843> A_IWL<60842> A_IWL<60841> A_IWL<60840> A_IWL<60839> A_IWL<60838> A_IWL<60837> A_IWL<60836> A_IWL<60835> A_IWL<60834> A_IWL<60833> A_IWL<60832> A_IWL<60831> A_IWL<60830> A_IWL<60829> A_IWL<60828> A_IWL<60827> A_IWL<60826> A_IWL<60825> A_IWL<60824> A_IWL<60823> A_IWL<60822> A_IWL<60821> A_IWL<60820> A_IWL<60819> A_IWL<60818> A_IWL<60817> A_IWL<60816> A_IWL<60815> A_IWL<60814> A_IWL<60813> A_IWL<60812> A_IWL<60811> A_IWL<60810> A_IWL<60809> A_IWL<60808> A_IWL<60807> A_IWL<60806> A_IWL<60805> A_IWL<60804> A_IWL<60803> A_IWL<60802> A_IWL<60801> A_IWL<60800> A_IWL<60799> A_IWL<60798> A_IWL<60797> A_IWL<60796> A_IWL<60795> A_IWL<60794> A_IWL<60793> A_IWL<60792> A_IWL<60791> A_IWL<60790> A_IWL<60789> A_IWL<60788> A_IWL<60787> A_IWL<60786> A_IWL<60785> A_IWL<60784> A_IWL<60783> A_IWL<60782> A_IWL<60781> A_IWL<60780> A_IWL<60779> A_IWL<60778> A_IWL<60777> A_IWL<60776> A_IWL<60775> A_IWL<60774> A_IWL<60773> A_IWL<60772> A_IWL<60771> A_IWL<60770> A_IWL<60769> A_IWL<60768> A_IWL<60767> A_IWL<60766> A_IWL<60765> A_IWL<60764> A_IWL<60763> A_IWL<60762> A_IWL<60761> A_IWL<60760> A_IWL<60759> A_IWL<60758> A_IWL<60757> A_IWL<60756> A_IWL<60755> A_IWL<60754> A_IWL<60753> A_IWL<60752> A_IWL<60751> A_IWL<60750> A_IWL<60749> A_IWL<60748> A_IWL<60747> A_IWL<60746> A_IWL<60745> A_IWL<60744> A_IWL<60743> A_IWL<60742> A_IWL<60741> A_IWL<60740> A_IWL<60739> A_IWL<60738> A_IWL<60737> A_IWL<60736> A_IWL<60735> A_IWL<60734> A_IWL<60733> A_IWL<60732> A_IWL<60731> A_IWL<60730> A_IWL<60729> A_IWL<60728> A_IWL<60727> A_IWL<60726> A_IWL<60725> A_IWL<60724> A_IWL<60723> A_IWL<60722> A_IWL<60721> A_IWL<60720> A_IWL<60719> A_IWL<60718> A_IWL<60717> A_IWL<60716> A_IWL<60715> A_IWL<60714> A_IWL<60713> A_IWL<60712> A_IWL<60711> A_IWL<60710> A_IWL<60709> A_IWL<60708> A_IWL<60707> A_IWL<60706> A_IWL<60705> A_IWL<60704> A_IWL<60703> A_IWL<60702> A_IWL<60701> A_IWL<60700> A_IWL<60699> A_IWL<60698> A_IWL<60697> A_IWL<60696> A_IWL<60695> A_IWL<60694> A_IWL<60693> A_IWL<60692> A_IWL<60691> A_IWL<60690> A_IWL<60689> A_IWL<60688> A_IWL<60687> A_IWL<60686> A_IWL<60685> A_IWL<60684> A_IWL<60683> A_IWL<60682> A_IWL<60681> A_IWL<60680> A_IWL<60679> A_IWL<60678> A_IWL<60677> A_IWL<60676> A_IWL<60675> A_IWL<60674> A_IWL<60673> A_IWL<60672> A_IWL<60671> A_IWL<60670> A_IWL<60669> A_IWL<60668> A_IWL<60667> A_IWL<60666> A_IWL<60665> A_IWL<60664> A_IWL<60663> A_IWL<60662> A_IWL<60661> A_IWL<60660> A_IWL<60659> A_IWL<60658> A_IWL<60657> A_IWL<60656> A_IWL<60655> A_IWL<60654> A_IWL<60653> A_IWL<60652> A_IWL<60651> A_IWL<60650> A_IWL<60649> A_IWL<60648> A_IWL<60647> A_IWL<60646> A_IWL<60645> A_IWL<60644> A_IWL<60643> A_IWL<60642> A_IWL<60641> A_IWL<60640> A_IWL<60639> A_IWL<60638> A_IWL<60637> A_IWL<60636> A_IWL<60635> A_IWL<60634> A_IWL<60633> A_IWL<60632> A_IWL<60631> A_IWL<60630> A_IWL<60629> A_IWL<60628> A_IWL<60627> A_IWL<60626> A_IWL<60625> A_IWL<60624> A_IWL<60623> A_IWL<60622> A_IWL<60621> A_IWL<60620> A_IWL<60619> A_IWL<60618> A_IWL<60617> A_IWL<60616> A_IWL<60615> A_IWL<60614> A_IWL<60613> A_IWL<60612> A_IWL<60611> A_IWL<60610> A_IWL<60609> A_IWL<60608> A_IWL<60607> A_IWL<60606> A_IWL<60605> A_IWL<60604> A_IWL<60603> A_IWL<60602> A_IWL<60601> A_IWL<60600> A_IWL<60599> A_IWL<60598> A_IWL<60597> A_IWL<60596> A_IWL<60595> A_IWL<60594> A_IWL<60593> A_IWL<60592> A_IWL<60591> A_IWL<60590> A_IWL<60589> A_IWL<60588> A_IWL<60587> A_IWL<60586> A_IWL<60585> A_IWL<60584> A_IWL<60583> A_IWL<60582> A_IWL<60581> A_IWL<60580> A_IWL<60579> A_IWL<60578> A_IWL<60577> A_IWL<60576> A_IWL<60575> A_IWL<60574> A_IWL<60573> A_IWL<60572> A_IWL<60571> A_IWL<60570> A_IWL<60569> A_IWL<60568> A_IWL<60567> A_IWL<60566> A_IWL<60565> A_IWL<60564> A_IWL<60563> A_IWL<60562> A_IWL<60561> A_IWL<60560> A_IWL<60559> A_IWL<60558> A_IWL<60557> A_IWL<60556> A_IWL<60555> A_IWL<60554> A_IWL<60553> A_IWL<60552> A_IWL<60551> A_IWL<60550> A_IWL<60549> A_IWL<60548> A_IWL<60547> A_IWL<60546> A_IWL<60545> A_IWL<60544> A_IWL<60543> A_IWL<60542> A_IWL<60541> A_IWL<60540> A_IWL<60539> A_IWL<60538> A_IWL<60537> A_IWL<60536> A_IWL<60535> A_IWL<60534> A_IWL<60533> A_IWL<60532> A_IWL<60531> A_IWL<60530> A_IWL<60529> A_IWL<60528> A_IWL<60527> A_IWL<60526> A_IWL<60525> A_IWL<60524> A_IWL<60523> A_IWL<60522> A_IWL<60521> A_IWL<60520> A_IWL<60519> A_IWL<60518> A_IWL<60517> A_IWL<60516> A_IWL<60515> A_IWL<60514> A_IWL<60513> A_IWL<60512> A_IWL<60511> A_IWL<60510> A_IWL<60509> A_IWL<60508> A_IWL<60507> A_IWL<60506> A_IWL<60505> A_IWL<60504> A_IWL<60503> A_IWL<60502> A_IWL<60501> A_IWL<60500> A_IWL<60499> A_IWL<60498> A_IWL<60497> A_IWL<60496> A_IWL<60495> A_IWL<60494> A_IWL<60493> A_IWL<60492> A_IWL<60491> A_IWL<60490> A_IWL<60489> A_IWL<60488> A_IWL<60487> A_IWL<60486> A_IWL<60485> A_IWL<60484> A_IWL<60483> A_IWL<60482> A_IWL<60481> A_IWL<60480> A_IWL<60479> A_IWL<60478> A_IWL<60477> A_IWL<60476> A_IWL<60475> A_IWL<60474> A_IWL<60473> A_IWL<60472> A_IWL<60471> A_IWL<60470> A_IWL<60469> A_IWL<60468> A_IWL<60467> A_IWL<60466> A_IWL<60465> A_IWL<60464> A_IWL<60463> A_IWL<60462> A_IWL<60461> A_IWL<60460> A_IWL<60459> A_IWL<60458> A_IWL<60457> A_IWL<60456> A_IWL<60455> A_IWL<60454> A_IWL<60453> A_IWL<60452> A_IWL<60451> A_IWL<60450> A_IWL<60449> A_IWL<60448> A_IWL<60447> A_IWL<60446> A_IWL<60445> A_IWL<60444> A_IWL<60443> A_IWL<60442> A_IWL<60441> A_IWL<60440> A_IWL<60439> A_IWL<60438> A_IWL<60437> A_IWL<60436> A_IWL<60435> A_IWL<60434> A_IWL<60433> A_IWL<60432> A_IWL<60431> A_IWL<60430> A_IWL<60429> A_IWL<60428> A_IWL<60427> A_IWL<60426> A_IWL<60425> A_IWL<60424> A_IWL<60423> A_IWL<60422> A_IWL<60421> A_IWL<60420> A_IWL<60419> A_IWL<60418> A_IWL<60417> A_IWL<60416> VDD_CORE VSS / RM_IHPSG13_8192x32_c4_1P_COLUMN_pcell_0 +XCOL<117> A_BLC<235> A_BLC<234> A_BLC_TOP<235> A_BLC_TOP<234> A_BLT<235> A_BLT<234> A_BLT_TOP<235> A_BLT_TOP<234> A_IWL<59903> A_IWL<59902> A_IWL<59901> A_IWL<59900> A_IWL<59899> A_IWL<59898> A_IWL<59897> A_IWL<59896> A_IWL<59895> A_IWL<59894> A_IWL<59893> A_IWL<59892> A_IWL<59891> A_IWL<59890> A_IWL<59889> A_IWL<59888> A_IWL<59887> A_IWL<59886> A_IWL<59885> A_IWL<59884> A_IWL<59883> A_IWL<59882> A_IWL<59881> A_IWL<59880> A_IWL<59879> A_IWL<59878> A_IWL<59877> A_IWL<59876> A_IWL<59875> A_IWL<59874> A_IWL<59873> A_IWL<59872> A_IWL<59871> A_IWL<59870> A_IWL<59869> A_IWL<59868> A_IWL<59867> A_IWL<59866> A_IWL<59865> A_IWL<59864> A_IWL<59863> A_IWL<59862> A_IWL<59861> A_IWL<59860> A_IWL<59859> A_IWL<59858> A_IWL<59857> A_IWL<59856> A_IWL<59855> A_IWL<59854> A_IWL<59853> A_IWL<59852> A_IWL<59851> A_IWL<59850> A_IWL<59849> A_IWL<59848> A_IWL<59847> A_IWL<59846> A_IWL<59845> A_IWL<59844> A_IWL<59843> A_IWL<59842> A_IWL<59841> A_IWL<59840> A_IWL<59839> A_IWL<59838> A_IWL<59837> A_IWL<59836> A_IWL<59835> A_IWL<59834> A_IWL<59833> A_IWL<59832> A_IWL<59831> A_IWL<59830> A_IWL<59829> A_IWL<59828> A_IWL<59827> A_IWL<59826> A_IWL<59825> A_IWL<59824> A_IWL<59823> A_IWL<59822> A_IWL<59821> A_IWL<59820> A_IWL<59819> A_IWL<59818> A_IWL<59817> A_IWL<59816> A_IWL<59815> A_IWL<59814> A_IWL<59813> A_IWL<59812> A_IWL<59811> A_IWL<59810> A_IWL<59809> A_IWL<59808> A_IWL<59807> A_IWL<59806> A_IWL<59805> A_IWL<59804> A_IWL<59803> A_IWL<59802> A_IWL<59801> A_IWL<59800> A_IWL<59799> A_IWL<59798> A_IWL<59797> A_IWL<59796> A_IWL<59795> A_IWL<59794> A_IWL<59793> A_IWL<59792> A_IWL<59791> A_IWL<59790> A_IWL<59789> A_IWL<59788> A_IWL<59787> A_IWL<59786> A_IWL<59785> A_IWL<59784> A_IWL<59783> A_IWL<59782> A_IWL<59781> A_IWL<59780> A_IWL<59779> A_IWL<59778> A_IWL<59777> A_IWL<59776> A_IWL<59775> A_IWL<59774> A_IWL<59773> A_IWL<59772> A_IWL<59771> A_IWL<59770> A_IWL<59769> A_IWL<59768> A_IWL<59767> A_IWL<59766> A_IWL<59765> A_IWL<59764> A_IWL<59763> A_IWL<59762> A_IWL<59761> A_IWL<59760> A_IWL<59759> A_IWL<59758> A_IWL<59757> A_IWL<59756> A_IWL<59755> A_IWL<59754> A_IWL<59753> A_IWL<59752> A_IWL<59751> A_IWL<59750> A_IWL<59749> A_IWL<59748> A_IWL<59747> A_IWL<59746> A_IWL<59745> A_IWL<59744> A_IWL<59743> A_IWL<59742> A_IWL<59741> A_IWL<59740> A_IWL<59739> A_IWL<59738> A_IWL<59737> A_IWL<59736> A_IWL<59735> A_IWL<59734> A_IWL<59733> A_IWL<59732> A_IWL<59731> A_IWL<59730> A_IWL<59729> A_IWL<59728> A_IWL<59727> A_IWL<59726> A_IWL<59725> A_IWL<59724> A_IWL<59723> A_IWL<59722> A_IWL<59721> A_IWL<59720> A_IWL<59719> A_IWL<59718> A_IWL<59717> A_IWL<59716> A_IWL<59715> A_IWL<59714> A_IWL<59713> A_IWL<59712> A_IWL<59711> A_IWL<59710> A_IWL<59709> A_IWL<59708> A_IWL<59707> A_IWL<59706> A_IWL<59705> A_IWL<59704> A_IWL<59703> A_IWL<59702> A_IWL<59701> A_IWL<59700> A_IWL<59699> A_IWL<59698> A_IWL<59697> A_IWL<59696> A_IWL<59695> A_IWL<59694> A_IWL<59693> A_IWL<59692> A_IWL<59691> A_IWL<59690> A_IWL<59689> A_IWL<59688> A_IWL<59687> A_IWL<59686> A_IWL<59685> A_IWL<59684> A_IWL<59683> A_IWL<59682> A_IWL<59681> A_IWL<59680> A_IWL<59679> A_IWL<59678> A_IWL<59677> A_IWL<59676> A_IWL<59675> A_IWL<59674> A_IWL<59673> A_IWL<59672> A_IWL<59671> A_IWL<59670> A_IWL<59669> A_IWL<59668> A_IWL<59667> A_IWL<59666> A_IWL<59665> A_IWL<59664> A_IWL<59663> A_IWL<59662> A_IWL<59661> A_IWL<59660> A_IWL<59659> A_IWL<59658> A_IWL<59657> A_IWL<59656> A_IWL<59655> A_IWL<59654> A_IWL<59653> A_IWL<59652> A_IWL<59651> A_IWL<59650> A_IWL<59649> A_IWL<59648> A_IWL<59647> A_IWL<59646> A_IWL<59645> A_IWL<59644> A_IWL<59643> A_IWL<59642> A_IWL<59641> A_IWL<59640> A_IWL<59639> A_IWL<59638> A_IWL<59637> A_IWL<59636> A_IWL<59635> A_IWL<59634> A_IWL<59633> A_IWL<59632> A_IWL<59631> A_IWL<59630> A_IWL<59629> A_IWL<59628> A_IWL<59627> A_IWL<59626> A_IWL<59625> A_IWL<59624> A_IWL<59623> A_IWL<59622> A_IWL<59621> A_IWL<59620> A_IWL<59619> A_IWL<59618> A_IWL<59617> A_IWL<59616> A_IWL<59615> A_IWL<59614> A_IWL<59613> A_IWL<59612> A_IWL<59611> A_IWL<59610> A_IWL<59609> A_IWL<59608> A_IWL<59607> A_IWL<59606> A_IWL<59605> A_IWL<59604> A_IWL<59603> A_IWL<59602> A_IWL<59601> A_IWL<59600> A_IWL<59599> A_IWL<59598> A_IWL<59597> A_IWL<59596> A_IWL<59595> A_IWL<59594> A_IWL<59593> A_IWL<59592> A_IWL<59591> A_IWL<59590> A_IWL<59589> A_IWL<59588> A_IWL<59587> A_IWL<59586> A_IWL<59585> A_IWL<59584> A_IWL<59583> A_IWL<59582> A_IWL<59581> A_IWL<59580> A_IWL<59579> A_IWL<59578> A_IWL<59577> A_IWL<59576> A_IWL<59575> A_IWL<59574> A_IWL<59573> A_IWL<59572> A_IWL<59571> A_IWL<59570> A_IWL<59569> A_IWL<59568> A_IWL<59567> A_IWL<59566> A_IWL<59565> A_IWL<59564> A_IWL<59563> A_IWL<59562> A_IWL<59561> A_IWL<59560> A_IWL<59559> A_IWL<59558> A_IWL<59557> A_IWL<59556> A_IWL<59555> A_IWL<59554> A_IWL<59553> A_IWL<59552> A_IWL<59551> A_IWL<59550> A_IWL<59549> A_IWL<59548> A_IWL<59547> A_IWL<59546> A_IWL<59545> A_IWL<59544> A_IWL<59543> A_IWL<59542> A_IWL<59541> A_IWL<59540> A_IWL<59539> A_IWL<59538> A_IWL<59537> A_IWL<59536> A_IWL<59535> A_IWL<59534> A_IWL<59533> A_IWL<59532> A_IWL<59531> A_IWL<59530> A_IWL<59529> A_IWL<59528> A_IWL<59527> A_IWL<59526> A_IWL<59525> A_IWL<59524> A_IWL<59523> A_IWL<59522> A_IWL<59521> A_IWL<59520> A_IWL<59519> A_IWL<59518> A_IWL<59517> A_IWL<59516> A_IWL<59515> A_IWL<59514> A_IWL<59513> A_IWL<59512> A_IWL<59511> A_IWL<59510> A_IWL<59509> A_IWL<59508> A_IWL<59507> A_IWL<59506> A_IWL<59505> A_IWL<59504> A_IWL<59503> A_IWL<59502> A_IWL<59501> A_IWL<59500> A_IWL<59499> A_IWL<59498> A_IWL<59497> A_IWL<59496> A_IWL<59495> A_IWL<59494> A_IWL<59493> A_IWL<59492> A_IWL<59491> A_IWL<59490> A_IWL<59489> A_IWL<59488> A_IWL<59487> A_IWL<59486> A_IWL<59485> A_IWL<59484> A_IWL<59483> A_IWL<59482> A_IWL<59481> A_IWL<59480> A_IWL<59479> A_IWL<59478> A_IWL<59477> A_IWL<59476> A_IWL<59475> A_IWL<59474> A_IWL<59473> A_IWL<59472> A_IWL<59471> A_IWL<59470> A_IWL<59469> A_IWL<59468> A_IWL<59467> A_IWL<59466> A_IWL<59465> A_IWL<59464> A_IWL<59463> A_IWL<59462> A_IWL<59461> A_IWL<59460> A_IWL<59459> A_IWL<59458> A_IWL<59457> A_IWL<59456> A_IWL<59455> A_IWL<59454> A_IWL<59453> A_IWL<59452> A_IWL<59451> A_IWL<59450> A_IWL<59449> A_IWL<59448> A_IWL<59447> A_IWL<59446> A_IWL<59445> A_IWL<59444> A_IWL<59443> A_IWL<59442> A_IWL<59441> A_IWL<59440> A_IWL<59439> A_IWL<59438> A_IWL<59437> A_IWL<59436> A_IWL<59435> A_IWL<59434> A_IWL<59433> A_IWL<59432> A_IWL<59431> A_IWL<59430> A_IWL<59429> A_IWL<59428> A_IWL<59427> A_IWL<59426> A_IWL<59425> A_IWL<59424> A_IWL<59423> A_IWL<59422> A_IWL<59421> A_IWL<59420> A_IWL<59419> A_IWL<59418> A_IWL<59417> A_IWL<59416> A_IWL<59415> A_IWL<59414> A_IWL<59413> A_IWL<59412> A_IWL<59411> A_IWL<59410> A_IWL<59409> A_IWL<59408> A_IWL<59407> A_IWL<59406> A_IWL<59405> A_IWL<59404> A_IWL<59403> A_IWL<59402> A_IWL<59401> A_IWL<59400> A_IWL<59399> A_IWL<59398> A_IWL<59397> A_IWL<59396> A_IWL<59395> A_IWL<59394> A_IWL<59393> A_IWL<59392> A_IWL<60415> A_IWL<60414> A_IWL<60413> A_IWL<60412> A_IWL<60411> A_IWL<60410> A_IWL<60409> A_IWL<60408> A_IWL<60407> A_IWL<60406> A_IWL<60405> A_IWL<60404> A_IWL<60403> A_IWL<60402> A_IWL<60401> A_IWL<60400> A_IWL<60399> A_IWL<60398> A_IWL<60397> A_IWL<60396> A_IWL<60395> A_IWL<60394> A_IWL<60393> A_IWL<60392> A_IWL<60391> A_IWL<60390> A_IWL<60389> A_IWL<60388> A_IWL<60387> A_IWL<60386> A_IWL<60385> A_IWL<60384> A_IWL<60383> A_IWL<60382> A_IWL<60381> A_IWL<60380> A_IWL<60379> A_IWL<60378> A_IWL<60377> A_IWL<60376> A_IWL<60375> A_IWL<60374> A_IWL<60373> A_IWL<60372> A_IWL<60371> A_IWL<60370> A_IWL<60369> A_IWL<60368> A_IWL<60367> A_IWL<60366> A_IWL<60365> A_IWL<60364> A_IWL<60363> A_IWL<60362> A_IWL<60361> A_IWL<60360> A_IWL<60359> A_IWL<60358> A_IWL<60357> A_IWL<60356> A_IWL<60355> A_IWL<60354> A_IWL<60353> A_IWL<60352> A_IWL<60351> A_IWL<60350> A_IWL<60349> A_IWL<60348> A_IWL<60347> A_IWL<60346> A_IWL<60345> A_IWL<60344> A_IWL<60343> A_IWL<60342> A_IWL<60341> A_IWL<60340> A_IWL<60339> A_IWL<60338> A_IWL<60337> A_IWL<60336> A_IWL<60335> A_IWL<60334> A_IWL<60333> A_IWL<60332> A_IWL<60331> A_IWL<60330> A_IWL<60329> A_IWL<60328> A_IWL<60327> A_IWL<60326> A_IWL<60325> A_IWL<60324> A_IWL<60323> A_IWL<60322> A_IWL<60321> A_IWL<60320> A_IWL<60319> A_IWL<60318> A_IWL<60317> A_IWL<60316> A_IWL<60315> A_IWL<60314> A_IWL<60313> A_IWL<60312> A_IWL<60311> A_IWL<60310> A_IWL<60309> A_IWL<60308> A_IWL<60307> A_IWL<60306> A_IWL<60305> A_IWL<60304> A_IWL<60303> A_IWL<60302> A_IWL<60301> A_IWL<60300> A_IWL<60299> A_IWL<60298> A_IWL<60297> A_IWL<60296> A_IWL<60295> A_IWL<60294> A_IWL<60293> A_IWL<60292> A_IWL<60291> A_IWL<60290> A_IWL<60289> A_IWL<60288> A_IWL<60287> A_IWL<60286> A_IWL<60285> A_IWL<60284> A_IWL<60283> A_IWL<60282> A_IWL<60281> A_IWL<60280> A_IWL<60279> A_IWL<60278> A_IWL<60277> A_IWL<60276> A_IWL<60275> A_IWL<60274> A_IWL<60273> A_IWL<60272> A_IWL<60271> A_IWL<60270> A_IWL<60269> A_IWL<60268> A_IWL<60267> A_IWL<60266> A_IWL<60265> A_IWL<60264> A_IWL<60263> A_IWL<60262> A_IWL<60261> A_IWL<60260> A_IWL<60259> A_IWL<60258> A_IWL<60257> A_IWL<60256> A_IWL<60255> A_IWL<60254> A_IWL<60253> A_IWL<60252> A_IWL<60251> A_IWL<60250> A_IWL<60249> A_IWL<60248> A_IWL<60247> A_IWL<60246> A_IWL<60245> A_IWL<60244> A_IWL<60243> A_IWL<60242> A_IWL<60241> A_IWL<60240> A_IWL<60239> A_IWL<60238> A_IWL<60237> A_IWL<60236> A_IWL<60235> A_IWL<60234> A_IWL<60233> A_IWL<60232> A_IWL<60231> A_IWL<60230> A_IWL<60229> A_IWL<60228> A_IWL<60227> A_IWL<60226> A_IWL<60225> A_IWL<60224> A_IWL<60223> A_IWL<60222> A_IWL<60221> A_IWL<60220> A_IWL<60219> A_IWL<60218> A_IWL<60217> A_IWL<60216> A_IWL<60215> A_IWL<60214> A_IWL<60213> A_IWL<60212> A_IWL<60211> A_IWL<60210> A_IWL<60209> A_IWL<60208> A_IWL<60207> A_IWL<60206> A_IWL<60205> A_IWL<60204> A_IWL<60203> A_IWL<60202> A_IWL<60201> A_IWL<60200> A_IWL<60199> A_IWL<60198> A_IWL<60197> A_IWL<60196> A_IWL<60195> A_IWL<60194> A_IWL<60193> A_IWL<60192> A_IWL<60191> A_IWL<60190> A_IWL<60189> A_IWL<60188> A_IWL<60187> A_IWL<60186> A_IWL<60185> A_IWL<60184> A_IWL<60183> A_IWL<60182> A_IWL<60181> A_IWL<60180> A_IWL<60179> A_IWL<60178> A_IWL<60177> A_IWL<60176> A_IWL<60175> A_IWL<60174> A_IWL<60173> A_IWL<60172> A_IWL<60171> A_IWL<60170> A_IWL<60169> A_IWL<60168> A_IWL<60167> A_IWL<60166> A_IWL<60165> A_IWL<60164> A_IWL<60163> A_IWL<60162> A_IWL<60161> A_IWL<60160> A_IWL<60159> A_IWL<60158> A_IWL<60157> A_IWL<60156> A_IWL<60155> A_IWL<60154> A_IWL<60153> A_IWL<60152> A_IWL<60151> A_IWL<60150> A_IWL<60149> A_IWL<60148> A_IWL<60147> A_IWL<60146> A_IWL<60145> A_IWL<60144> A_IWL<60143> A_IWL<60142> A_IWL<60141> A_IWL<60140> A_IWL<60139> A_IWL<60138> A_IWL<60137> A_IWL<60136> A_IWL<60135> A_IWL<60134> A_IWL<60133> A_IWL<60132> A_IWL<60131> A_IWL<60130> A_IWL<60129> A_IWL<60128> A_IWL<60127> A_IWL<60126> A_IWL<60125> A_IWL<60124> A_IWL<60123> A_IWL<60122> A_IWL<60121> A_IWL<60120> A_IWL<60119> A_IWL<60118> A_IWL<60117> A_IWL<60116> A_IWL<60115> A_IWL<60114> A_IWL<60113> A_IWL<60112> A_IWL<60111> A_IWL<60110> A_IWL<60109> A_IWL<60108> A_IWL<60107> A_IWL<60106> A_IWL<60105> A_IWL<60104> A_IWL<60103> A_IWL<60102> A_IWL<60101> A_IWL<60100> A_IWL<60099> A_IWL<60098> A_IWL<60097> A_IWL<60096> A_IWL<60095> A_IWL<60094> A_IWL<60093> A_IWL<60092> A_IWL<60091> A_IWL<60090> A_IWL<60089> A_IWL<60088> A_IWL<60087> A_IWL<60086> A_IWL<60085> A_IWL<60084> A_IWL<60083> A_IWL<60082> A_IWL<60081> A_IWL<60080> A_IWL<60079> A_IWL<60078> A_IWL<60077> A_IWL<60076> A_IWL<60075> A_IWL<60074> A_IWL<60073> A_IWL<60072> A_IWL<60071> A_IWL<60070> A_IWL<60069> A_IWL<60068> A_IWL<60067> A_IWL<60066> A_IWL<60065> A_IWL<60064> A_IWL<60063> A_IWL<60062> A_IWL<60061> A_IWL<60060> A_IWL<60059> A_IWL<60058> A_IWL<60057> A_IWL<60056> A_IWL<60055> A_IWL<60054> A_IWL<60053> A_IWL<60052> A_IWL<60051> A_IWL<60050> A_IWL<60049> A_IWL<60048> A_IWL<60047> A_IWL<60046> A_IWL<60045> A_IWL<60044> A_IWL<60043> A_IWL<60042> A_IWL<60041> A_IWL<60040> A_IWL<60039> A_IWL<60038> A_IWL<60037> A_IWL<60036> A_IWL<60035> A_IWL<60034> A_IWL<60033> A_IWL<60032> A_IWL<60031> A_IWL<60030> A_IWL<60029> A_IWL<60028> A_IWL<60027> A_IWL<60026> A_IWL<60025> A_IWL<60024> A_IWL<60023> A_IWL<60022> A_IWL<60021> A_IWL<60020> A_IWL<60019> A_IWL<60018> A_IWL<60017> A_IWL<60016> A_IWL<60015> A_IWL<60014> A_IWL<60013> A_IWL<60012> A_IWL<60011> A_IWL<60010> A_IWL<60009> A_IWL<60008> A_IWL<60007> A_IWL<60006> A_IWL<60005> A_IWL<60004> A_IWL<60003> A_IWL<60002> A_IWL<60001> A_IWL<60000> A_IWL<59999> A_IWL<59998> A_IWL<59997> A_IWL<59996> A_IWL<59995> A_IWL<59994> A_IWL<59993> A_IWL<59992> A_IWL<59991> A_IWL<59990> A_IWL<59989> A_IWL<59988> A_IWL<59987> A_IWL<59986> A_IWL<59985> A_IWL<59984> A_IWL<59983> A_IWL<59982> A_IWL<59981> A_IWL<59980> A_IWL<59979> A_IWL<59978> A_IWL<59977> A_IWL<59976> A_IWL<59975> A_IWL<59974> A_IWL<59973> A_IWL<59972> A_IWL<59971> A_IWL<59970> A_IWL<59969> A_IWL<59968> A_IWL<59967> A_IWL<59966> A_IWL<59965> A_IWL<59964> A_IWL<59963> A_IWL<59962> A_IWL<59961> A_IWL<59960> A_IWL<59959> A_IWL<59958> A_IWL<59957> A_IWL<59956> A_IWL<59955> A_IWL<59954> A_IWL<59953> A_IWL<59952> A_IWL<59951> A_IWL<59950> A_IWL<59949> A_IWL<59948> A_IWL<59947> A_IWL<59946> A_IWL<59945> A_IWL<59944> A_IWL<59943> A_IWL<59942> A_IWL<59941> A_IWL<59940> A_IWL<59939> A_IWL<59938> A_IWL<59937> A_IWL<59936> A_IWL<59935> A_IWL<59934> A_IWL<59933> A_IWL<59932> A_IWL<59931> A_IWL<59930> A_IWL<59929> A_IWL<59928> A_IWL<59927> A_IWL<59926> A_IWL<59925> A_IWL<59924> A_IWL<59923> A_IWL<59922> A_IWL<59921> A_IWL<59920> A_IWL<59919> A_IWL<59918> A_IWL<59917> A_IWL<59916> A_IWL<59915> A_IWL<59914> A_IWL<59913> A_IWL<59912> A_IWL<59911> A_IWL<59910> A_IWL<59909> A_IWL<59908> A_IWL<59907> A_IWL<59906> A_IWL<59905> A_IWL<59904> VDD_CORE VSS / RM_IHPSG13_8192x32_c4_1P_COLUMN_pcell_0 +XCOL<116> A_BLC<233> A_BLC<232> A_BLC_TOP<233> A_BLC_TOP<232> A_BLT<233> A_BLT<232> A_BLT_TOP<233> A_BLT_TOP<232> A_IWL<59391> A_IWL<59390> A_IWL<59389> A_IWL<59388> A_IWL<59387> A_IWL<59386> A_IWL<59385> A_IWL<59384> A_IWL<59383> A_IWL<59382> A_IWL<59381> A_IWL<59380> A_IWL<59379> A_IWL<59378> A_IWL<59377> A_IWL<59376> A_IWL<59375> A_IWL<59374> A_IWL<59373> A_IWL<59372> A_IWL<59371> A_IWL<59370> A_IWL<59369> A_IWL<59368> A_IWL<59367> A_IWL<59366> A_IWL<59365> A_IWL<59364> A_IWL<59363> A_IWL<59362> A_IWL<59361> A_IWL<59360> A_IWL<59359> A_IWL<59358> A_IWL<59357> A_IWL<59356> A_IWL<59355> A_IWL<59354> A_IWL<59353> A_IWL<59352> A_IWL<59351> A_IWL<59350> A_IWL<59349> A_IWL<59348> A_IWL<59347> A_IWL<59346> A_IWL<59345> A_IWL<59344> A_IWL<59343> A_IWL<59342> A_IWL<59341> A_IWL<59340> A_IWL<59339> A_IWL<59338> A_IWL<59337> A_IWL<59336> A_IWL<59335> A_IWL<59334> A_IWL<59333> A_IWL<59332> A_IWL<59331> A_IWL<59330> A_IWL<59329> A_IWL<59328> A_IWL<59327> A_IWL<59326> A_IWL<59325> A_IWL<59324> A_IWL<59323> A_IWL<59322> A_IWL<59321> A_IWL<59320> A_IWL<59319> A_IWL<59318> A_IWL<59317> A_IWL<59316> A_IWL<59315> A_IWL<59314> A_IWL<59313> A_IWL<59312> A_IWL<59311> A_IWL<59310> A_IWL<59309> A_IWL<59308> A_IWL<59307> A_IWL<59306> A_IWL<59305> A_IWL<59304> A_IWL<59303> A_IWL<59302> A_IWL<59301> A_IWL<59300> A_IWL<59299> A_IWL<59298> A_IWL<59297> A_IWL<59296> A_IWL<59295> A_IWL<59294> A_IWL<59293> A_IWL<59292> A_IWL<59291> A_IWL<59290> A_IWL<59289> A_IWL<59288> A_IWL<59287> A_IWL<59286> A_IWL<59285> A_IWL<59284> A_IWL<59283> A_IWL<59282> A_IWL<59281> A_IWL<59280> A_IWL<59279> A_IWL<59278> A_IWL<59277> A_IWL<59276> A_IWL<59275> A_IWL<59274> A_IWL<59273> A_IWL<59272> A_IWL<59271> A_IWL<59270> A_IWL<59269> A_IWL<59268> A_IWL<59267> A_IWL<59266> A_IWL<59265> A_IWL<59264> A_IWL<59263> A_IWL<59262> A_IWL<59261> A_IWL<59260> A_IWL<59259> A_IWL<59258> A_IWL<59257> A_IWL<59256> A_IWL<59255> A_IWL<59254> A_IWL<59253> A_IWL<59252> A_IWL<59251> A_IWL<59250> A_IWL<59249> A_IWL<59248> A_IWL<59247> A_IWL<59246> A_IWL<59245> A_IWL<59244> A_IWL<59243> A_IWL<59242> A_IWL<59241> A_IWL<59240> A_IWL<59239> A_IWL<59238> A_IWL<59237> A_IWL<59236> A_IWL<59235> A_IWL<59234> A_IWL<59233> A_IWL<59232> A_IWL<59231> A_IWL<59230> A_IWL<59229> A_IWL<59228> A_IWL<59227> A_IWL<59226> A_IWL<59225> A_IWL<59224> A_IWL<59223> A_IWL<59222> A_IWL<59221> A_IWL<59220> A_IWL<59219> A_IWL<59218> A_IWL<59217> A_IWL<59216> A_IWL<59215> A_IWL<59214> A_IWL<59213> A_IWL<59212> A_IWL<59211> A_IWL<59210> A_IWL<59209> A_IWL<59208> A_IWL<59207> A_IWL<59206> A_IWL<59205> A_IWL<59204> A_IWL<59203> A_IWL<59202> A_IWL<59201> A_IWL<59200> A_IWL<59199> A_IWL<59198> A_IWL<59197> A_IWL<59196> A_IWL<59195> A_IWL<59194> A_IWL<59193> A_IWL<59192> A_IWL<59191> A_IWL<59190> A_IWL<59189> A_IWL<59188> A_IWL<59187> A_IWL<59186> A_IWL<59185> A_IWL<59184> A_IWL<59183> A_IWL<59182> A_IWL<59181> A_IWL<59180> A_IWL<59179> A_IWL<59178> A_IWL<59177> A_IWL<59176> A_IWL<59175> A_IWL<59174> A_IWL<59173> A_IWL<59172> A_IWL<59171> A_IWL<59170> A_IWL<59169> A_IWL<59168> A_IWL<59167> A_IWL<59166> A_IWL<59165> A_IWL<59164> A_IWL<59163> A_IWL<59162> A_IWL<59161> A_IWL<59160> A_IWL<59159> A_IWL<59158> A_IWL<59157> A_IWL<59156> A_IWL<59155> A_IWL<59154> A_IWL<59153> A_IWL<59152> A_IWL<59151> A_IWL<59150> A_IWL<59149> A_IWL<59148> A_IWL<59147> A_IWL<59146> A_IWL<59145> A_IWL<59144> A_IWL<59143> A_IWL<59142> A_IWL<59141> A_IWL<59140> A_IWL<59139> A_IWL<59138> A_IWL<59137> A_IWL<59136> A_IWL<59135> A_IWL<59134> A_IWL<59133> A_IWL<59132> A_IWL<59131> A_IWL<59130> A_IWL<59129> A_IWL<59128> A_IWL<59127> A_IWL<59126> A_IWL<59125> A_IWL<59124> A_IWL<59123> A_IWL<59122> A_IWL<59121> A_IWL<59120> A_IWL<59119> A_IWL<59118> A_IWL<59117> A_IWL<59116> A_IWL<59115> A_IWL<59114> A_IWL<59113> A_IWL<59112> A_IWL<59111> A_IWL<59110> A_IWL<59109> A_IWL<59108> A_IWL<59107> A_IWL<59106> A_IWL<59105> A_IWL<59104> A_IWL<59103> A_IWL<59102> A_IWL<59101> A_IWL<59100> A_IWL<59099> A_IWL<59098> A_IWL<59097> A_IWL<59096> A_IWL<59095> A_IWL<59094> A_IWL<59093> A_IWL<59092> A_IWL<59091> A_IWL<59090> A_IWL<59089> A_IWL<59088> A_IWL<59087> A_IWL<59086> A_IWL<59085> A_IWL<59084> A_IWL<59083> A_IWL<59082> A_IWL<59081> A_IWL<59080> A_IWL<59079> A_IWL<59078> A_IWL<59077> A_IWL<59076> A_IWL<59075> A_IWL<59074> A_IWL<59073> A_IWL<59072> A_IWL<59071> A_IWL<59070> A_IWL<59069> A_IWL<59068> A_IWL<59067> A_IWL<59066> A_IWL<59065> A_IWL<59064> A_IWL<59063> A_IWL<59062> A_IWL<59061> A_IWL<59060> A_IWL<59059> A_IWL<59058> A_IWL<59057> A_IWL<59056> A_IWL<59055> A_IWL<59054> A_IWL<59053> A_IWL<59052> A_IWL<59051> A_IWL<59050> A_IWL<59049> A_IWL<59048> A_IWL<59047> A_IWL<59046> A_IWL<59045> A_IWL<59044> A_IWL<59043> A_IWL<59042> A_IWL<59041> A_IWL<59040> A_IWL<59039> A_IWL<59038> A_IWL<59037> A_IWL<59036> A_IWL<59035> A_IWL<59034> A_IWL<59033> A_IWL<59032> A_IWL<59031> A_IWL<59030> A_IWL<59029> A_IWL<59028> A_IWL<59027> A_IWL<59026> A_IWL<59025> A_IWL<59024> A_IWL<59023> A_IWL<59022> A_IWL<59021> A_IWL<59020> A_IWL<59019> A_IWL<59018> A_IWL<59017> A_IWL<59016> A_IWL<59015> A_IWL<59014> A_IWL<59013> A_IWL<59012> A_IWL<59011> A_IWL<59010> A_IWL<59009> A_IWL<59008> A_IWL<59007> A_IWL<59006> A_IWL<59005> A_IWL<59004> A_IWL<59003> A_IWL<59002> A_IWL<59001> A_IWL<59000> A_IWL<58999> A_IWL<58998> A_IWL<58997> A_IWL<58996> A_IWL<58995> A_IWL<58994> A_IWL<58993> A_IWL<58992> A_IWL<58991> A_IWL<58990> A_IWL<58989> A_IWL<58988> A_IWL<58987> A_IWL<58986> A_IWL<58985> A_IWL<58984> A_IWL<58983> A_IWL<58982> A_IWL<58981> A_IWL<58980> A_IWL<58979> A_IWL<58978> A_IWL<58977> A_IWL<58976> A_IWL<58975> A_IWL<58974> A_IWL<58973> A_IWL<58972> A_IWL<58971> A_IWL<58970> A_IWL<58969> A_IWL<58968> A_IWL<58967> A_IWL<58966> A_IWL<58965> A_IWL<58964> A_IWL<58963> A_IWL<58962> A_IWL<58961> A_IWL<58960> A_IWL<58959> A_IWL<58958> A_IWL<58957> A_IWL<58956> A_IWL<58955> A_IWL<58954> A_IWL<58953> A_IWL<58952> A_IWL<58951> A_IWL<58950> A_IWL<58949> A_IWL<58948> A_IWL<58947> A_IWL<58946> A_IWL<58945> A_IWL<58944> A_IWL<58943> A_IWL<58942> A_IWL<58941> A_IWL<58940> A_IWL<58939> A_IWL<58938> A_IWL<58937> A_IWL<58936> A_IWL<58935> A_IWL<58934> A_IWL<58933> A_IWL<58932> A_IWL<58931> A_IWL<58930> A_IWL<58929> A_IWL<58928> A_IWL<58927> A_IWL<58926> A_IWL<58925> A_IWL<58924> A_IWL<58923> A_IWL<58922> A_IWL<58921> A_IWL<58920> A_IWL<58919> A_IWL<58918> A_IWL<58917> A_IWL<58916> A_IWL<58915> A_IWL<58914> A_IWL<58913> A_IWL<58912> A_IWL<58911> A_IWL<58910> A_IWL<58909> A_IWL<58908> A_IWL<58907> A_IWL<58906> A_IWL<58905> A_IWL<58904> A_IWL<58903> A_IWL<58902> A_IWL<58901> A_IWL<58900> A_IWL<58899> A_IWL<58898> A_IWL<58897> A_IWL<58896> A_IWL<58895> A_IWL<58894> A_IWL<58893> A_IWL<58892> A_IWL<58891> A_IWL<58890> A_IWL<58889> A_IWL<58888> A_IWL<58887> A_IWL<58886> A_IWL<58885> A_IWL<58884> A_IWL<58883> A_IWL<58882> A_IWL<58881> A_IWL<58880> A_IWL<59903> A_IWL<59902> A_IWL<59901> A_IWL<59900> A_IWL<59899> A_IWL<59898> A_IWL<59897> A_IWL<59896> A_IWL<59895> A_IWL<59894> A_IWL<59893> A_IWL<59892> A_IWL<59891> A_IWL<59890> A_IWL<59889> A_IWL<59888> A_IWL<59887> A_IWL<59886> A_IWL<59885> A_IWL<59884> A_IWL<59883> A_IWL<59882> A_IWL<59881> A_IWL<59880> A_IWL<59879> A_IWL<59878> A_IWL<59877> A_IWL<59876> A_IWL<59875> A_IWL<59874> A_IWL<59873> A_IWL<59872> A_IWL<59871> A_IWL<59870> A_IWL<59869> A_IWL<59868> A_IWL<59867> A_IWL<59866> A_IWL<59865> A_IWL<59864> A_IWL<59863> A_IWL<59862> A_IWL<59861> A_IWL<59860> A_IWL<59859> A_IWL<59858> A_IWL<59857> A_IWL<59856> A_IWL<59855> A_IWL<59854> A_IWL<59853> A_IWL<59852> A_IWL<59851> A_IWL<59850> A_IWL<59849> A_IWL<59848> A_IWL<59847> A_IWL<59846> A_IWL<59845> A_IWL<59844> A_IWL<59843> A_IWL<59842> A_IWL<59841> A_IWL<59840> A_IWL<59839> A_IWL<59838> A_IWL<59837> A_IWL<59836> A_IWL<59835> A_IWL<59834> A_IWL<59833> A_IWL<59832> A_IWL<59831> A_IWL<59830> A_IWL<59829> A_IWL<59828> A_IWL<59827> A_IWL<59826> A_IWL<59825> A_IWL<59824> A_IWL<59823> A_IWL<59822> A_IWL<59821> A_IWL<59820> A_IWL<59819> A_IWL<59818> A_IWL<59817> A_IWL<59816> A_IWL<59815> A_IWL<59814> A_IWL<59813> A_IWL<59812> A_IWL<59811> A_IWL<59810> A_IWL<59809> A_IWL<59808> A_IWL<59807> A_IWL<59806> A_IWL<59805> A_IWL<59804> A_IWL<59803> A_IWL<59802> A_IWL<59801> A_IWL<59800> A_IWL<59799> A_IWL<59798> A_IWL<59797> A_IWL<59796> A_IWL<59795> A_IWL<59794> A_IWL<59793> A_IWL<59792> A_IWL<59791> A_IWL<59790> A_IWL<59789> A_IWL<59788> A_IWL<59787> A_IWL<59786> A_IWL<59785> A_IWL<59784> A_IWL<59783> A_IWL<59782> A_IWL<59781> A_IWL<59780> A_IWL<59779> A_IWL<59778> A_IWL<59777> A_IWL<59776> A_IWL<59775> A_IWL<59774> A_IWL<59773> A_IWL<59772> A_IWL<59771> A_IWL<59770> A_IWL<59769> A_IWL<59768> A_IWL<59767> A_IWL<59766> A_IWL<59765> A_IWL<59764> A_IWL<59763> A_IWL<59762> A_IWL<59761> A_IWL<59760> A_IWL<59759> A_IWL<59758> A_IWL<59757> A_IWL<59756> A_IWL<59755> A_IWL<59754> A_IWL<59753> A_IWL<59752> A_IWL<59751> A_IWL<59750> A_IWL<59749> A_IWL<59748> A_IWL<59747> A_IWL<59746> A_IWL<59745> A_IWL<59744> A_IWL<59743> A_IWL<59742> A_IWL<59741> A_IWL<59740> A_IWL<59739> A_IWL<59738> A_IWL<59737> A_IWL<59736> A_IWL<59735> A_IWL<59734> A_IWL<59733> A_IWL<59732> A_IWL<59731> A_IWL<59730> A_IWL<59729> A_IWL<59728> A_IWL<59727> A_IWL<59726> A_IWL<59725> A_IWL<59724> A_IWL<59723> A_IWL<59722> A_IWL<59721> A_IWL<59720> A_IWL<59719> A_IWL<59718> A_IWL<59717> A_IWL<59716> A_IWL<59715> A_IWL<59714> A_IWL<59713> A_IWL<59712> A_IWL<59711> A_IWL<59710> A_IWL<59709> A_IWL<59708> A_IWL<59707> A_IWL<59706> A_IWL<59705> A_IWL<59704> A_IWL<59703> A_IWL<59702> A_IWL<59701> A_IWL<59700> A_IWL<59699> A_IWL<59698> A_IWL<59697> A_IWL<59696> A_IWL<59695> A_IWL<59694> A_IWL<59693> A_IWL<59692> A_IWL<59691> A_IWL<59690> A_IWL<59689> A_IWL<59688> A_IWL<59687> A_IWL<59686> A_IWL<59685> A_IWL<59684> A_IWL<59683> A_IWL<59682> A_IWL<59681> A_IWL<59680> A_IWL<59679> A_IWL<59678> A_IWL<59677> A_IWL<59676> A_IWL<59675> A_IWL<59674> A_IWL<59673> A_IWL<59672> A_IWL<59671> A_IWL<59670> A_IWL<59669> A_IWL<59668> A_IWL<59667> A_IWL<59666> A_IWL<59665> A_IWL<59664> A_IWL<59663> A_IWL<59662> A_IWL<59661> A_IWL<59660> A_IWL<59659> A_IWL<59658> A_IWL<59657> A_IWL<59656> A_IWL<59655> A_IWL<59654> A_IWL<59653> A_IWL<59652> A_IWL<59651> A_IWL<59650> A_IWL<59649> A_IWL<59648> A_IWL<59647> A_IWL<59646> A_IWL<59645> A_IWL<59644> A_IWL<59643> A_IWL<59642> A_IWL<59641> A_IWL<59640> A_IWL<59639> A_IWL<59638> A_IWL<59637> A_IWL<59636> A_IWL<59635> A_IWL<59634> A_IWL<59633> A_IWL<59632> A_IWL<59631> A_IWL<59630> A_IWL<59629> A_IWL<59628> A_IWL<59627> A_IWL<59626> A_IWL<59625> A_IWL<59624> A_IWL<59623> A_IWL<59622> A_IWL<59621> A_IWL<59620> A_IWL<59619> A_IWL<59618> A_IWL<59617> A_IWL<59616> A_IWL<59615> A_IWL<59614> A_IWL<59613> A_IWL<59612> A_IWL<59611> A_IWL<59610> A_IWL<59609> A_IWL<59608> A_IWL<59607> A_IWL<59606> A_IWL<59605> A_IWL<59604> A_IWL<59603> A_IWL<59602> A_IWL<59601> A_IWL<59600> A_IWL<59599> A_IWL<59598> A_IWL<59597> A_IWL<59596> A_IWL<59595> A_IWL<59594> A_IWL<59593> A_IWL<59592> A_IWL<59591> A_IWL<59590> A_IWL<59589> A_IWL<59588> A_IWL<59587> A_IWL<59586> A_IWL<59585> A_IWL<59584> A_IWL<59583> A_IWL<59582> A_IWL<59581> A_IWL<59580> A_IWL<59579> A_IWL<59578> A_IWL<59577> A_IWL<59576> A_IWL<59575> A_IWL<59574> A_IWL<59573> A_IWL<59572> A_IWL<59571> A_IWL<59570> A_IWL<59569> A_IWL<59568> A_IWL<59567> A_IWL<59566> A_IWL<59565> A_IWL<59564> A_IWL<59563> A_IWL<59562> A_IWL<59561> A_IWL<59560> A_IWL<59559> A_IWL<59558> A_IWL<59557> A_IWL<59556> A_IWL<59555> A_IWL<59554> A_IWL<59553> A_IWL<59552> A_IWL<59551> A_IWL<59550> A_IWL<59549> A_IWL<59548> A_IWL<59547> A_IWL<59546> A_IWL<59545> A_IWL<59544> A_IWL<59543> A_IWL<59542> A_IWL<59541> A_IWL<59540> A_IWL<59539> A_IWL<59538> A_IWL<59537> A_IWL<59536> A_IWL<59535> A_IWL<59534> A_IWL<59533> A_IWL<59532> A_IWL<59531> A_IWL<59530> A_IWL<59529> A_IWL<59528> A_IWL<59527> A_IWL<59526> A_IWL<59525> A_IWL<59524> A_IWL<59523> A_IWL<59522> A_IWL<59521> A_IWL<59520> A_IWL<59519> A_IWL<59518> A_IWL<59517> A_IWL<59516> A_IWL<59515> A_IWL<59514> A_IWL<59513> A_IWL<59512> A_IWL<59511> A_IWL<59510> A_IWL<59509> A_IWL<59508> A_IWL<59507> A_IWL<59506> A_IWL<59505> A_IWL<59504> A_IWL<59503> A_IWL<59502> A_IWL<59501> A_IWL<59500> A_IWL<59499> A_IWL<59498> A_IWL<59497> A_IWL<59496> A_IWL<59495> A_IWL<59494> A_IWL<59493> A_IWL<59492> A_IWL<59491> A_IWL<59490> A_IWL<59489> A_IWL<59488> A_IWL<59487> A_IWL<59486> A_IWL<59485> A_IWL<59484> A_IWL<59483> A_IWL<59482> A_IWL<59481> A_IWL<59480> A_IWL<59479> A_IWL<59478> A_IWL<59477> A_IWL<59476> A_IWL<59475> A_IWL<59474> A_IWL<59473> A_IWL<59472> A_IWL<59471> A_IWL<59470> A_IWL<59469> A_IWL<59468> A_IWL<59467> A_IWL<59466> A_IWL<59465> A_IWL<59464> A_IWL<59463> A_IWL<59462> A_IWL<59461> A_IWL<59460> A_IWL<59459> A_IWL<59458> A_IWL<59457> A_IWL<59456> A_IWL<59455> A_IWL<59454> A_IWL<59453> A_IWL<59452> A_IWL<59451> A_IWL<59450> A_IWL<59449> A_IWL<59448> A_IWL<59447> A_IWL<59446> A_IWL<59445> A_IWL<59444> A_IWL<59443> A_IWL<59442> A_IWL<59441> A_IWL<59440> A_IWL<59439> A_IWL<59438> A_IWL<59437> A_IWL<59436> A_IWL<59435> A_IWL<59434> A_IWL<59433> A_IWL<59432> A_IWL<59431> A_IWL<59430> A_IWL<59429> A_IWL<59428> A_IWL<59427> A_IWL<59426> A_IWL<59425> A_IWL<59424> A_IWL<59423> A_IWL<59422> A_IWL<59421> A_IWL<59420> A_IWL<59419> A_IWL<59418> A_IWL<59417> A_IWL<59416> A_IWL<59415> A_IWL<59414> A_IWL<59413> A_IWL<59412> A_IWL<59411> A_IWL<59410> A_IWL<59409> A_IWL<59408> A_IWL<59407> A_IWL<59406> A_IWL<59405> A_IWL<59404> A_IWL<59403> A_IWL<59402> A_IWL<59401> A_IWL<59400> A_IWL<59399> A_IWL<59398> A_IWL<59397> A_IWL<59396> A_IWL<59395> A_IWL<59394> A_IWL<59393> A_IWL<59392> VDD_CORE VSS / RM_IHPSG13_8192x32_c4_1P_COLUMN_pcell_0 +XCOL<115> A_BLC<231> A_BLC<230> A_BLC_TOP<231> A_BLC_TOP<230> A_BLT<231> A_BLT<230> A_BLT_TOP<231> A_BLT_TOP<230> A_IWL<58879> A_IWL<58878> A_IWL<58877> A_IWL<58876> A_IWL<58875> A_IWL<58874> A_IWL<58873> A_IWL<58872> A_IWL<58871> A_IWL<58870> A_IWL<58869> A_IWL<58868> A_IWL<58867> A_IWL<58866> A_IWL<58865> A_IWL<58864> A_IWL<58863> A_IWL<58862> A_IWL<58861> A_IWL<58860> A_IWL<58859> A_IWL<58858> A_IWL<58857> A_IWL<58856> A_IWL<58855> A_IWL<58854> A_IWL<58853> A_IWL<58852> A_IWL<58851> A_IWL<58850> A_IWL<58849> A_IWL<58848> A_IWL<58847> A_IWL<58846> A_IWL<58845> A_IWL<58844> A_IWL<58843> A_IWL<58842> A_IWL<58841> A_IWL<58840> A_IWL<58839> A_IWL<58838> A_IWL<58837> A_IWL<58836> A_IWL<58835> A_IWL<58834> A_IWL<58833> A_IWL<58832> A_IWL<58831> A_IWL<58830> A_IWL<58829> A_IWL<58828> A_IWL<58827> A_IWL<58826> A_IWL<58825> A_IWL<58824> A_IWL<58823> A_IWL<58822> A_IWL<58821> A_IWL<58820> A_IWL<58819> A_IWL<58818> A_IWL<58817> A_IWL<58816> A_IWL<58815> A_IWL<58814> A_IWL<58813> A_IWL<58812> A_IWL<58811> A_IWL<58810> A_IWL<58809> A_IWL<58808> A_IWL<58807> A_IWL<58806> A_IWL<58805> A_IWL<58804> A_IWL<58803> A_IWL<58802> A_IWL<58801> A_IWL<58800> A_IWL<58799> A_IWL<58798> A_IWL<58797> A_IWL<58796> A_IWL<58795> A_IWL<58794> A_IWL<58793> A_IWL<58792> A_IWL<58791> A_IWL<58790> A_IWL<58789> A_IWL<58788> A_IWL<58787> A_IWL<58786> A_IWL<58785> A_IWL<58784> A_IWL<58783> A_IWL<58782> A_IWL<58781> A_IWL<58780> A_IWL<58779> A_IWL<58778> A_IWL<58777> A_IWL<58776> A_IWL<58775> A_IWL<58774> A_IWL<58773> A_IWL<58772> A_IWL<58771> A_IWL<58770> A_IWL<58769> A_IWL<58768> A_IWL<58767> A_IWL<58766> A_IWL<58765> A_IWL<58764> A_IWL<58763> A_IWL<58762> A_IWL<58761> A_IWL<58760> A_IWL<58759> A_IWL<58758> A_IWL<58757> A_IWL<58756> A_IWL<58755> A_IWL<58754> A_IWL<58753> A_IWL<58752> A_IWL<58751> A_IWL<58750> A_IWL<58749> A_IWL<58748> A_IWL<58747> A_IWL<58746> A_IWL<58745> A_IWL<58744> A_IWL<58743> A_IWL<58742> A_IWL<58741> A_IWL<58740> A_IWL<58739> A_IWL<58738> A_IWL<58737> A_IWL<58736> A_IWL<58735> A_IWL<58734> A_IWL<58733> A_IWL<58732> A_IWL<58731> A_IWL<58730> A_IWL<58729> A_IWL<58728> A_IWL<58727> A_IWL<58726> A_IWL<58725> A_IWL<58724> A_IWL<58723> A_IWL<58722> A_IWL<58721> A_IWL<58720> A_IWL<58719> A_IWL<58718> A_IWL<58717> A_IWL<58716> A_IWL<58715> A_IWL<58714> A_IWL<58713> A_IWL<58712> A_IWL<58711> A_IWL<58710> A_IWL<58709> A_IWL<58708> A_IWL<58707> A_IWL<58706> A_IWL<58705> A_IWL<58704> A_IWL<58703> A_IWL<58702> A_IWL<58701> A_IWL<58700> A_IWL<58699> A_IWL<58698> A_IWL<58697> A_IWL<58696> A_IWL<58695> A_IWL<58694> A_IWL<58693> A_IWL<58692> A_IWL<58691> A_IWL<58690> A_IWL<58689> A_IWL<58688> A_IWL<58687> A_IWL<58686> A_IWL<58685> A_IWL<58684> A_IWL<58683> A_IWL<58682> A_IWL<58681> A_IWL<58680> A_IWL<58679> A_IWL<58678> A_IWL<58677> A_IWL<58676> A_IWL<58675> A_IWL<58674> A_IWL<58673> A_IWL<58672> A_IWL<58671> A_IWL<58670> A_IWL<58669> A_IWL<58668> A_IWL<58667> A_IWL<58666> A_IWL<58665> A_IWL<58664> A_IWL<58663> A_IWL<58662> A_IWL<58661> A_IWL<58660> A_IWL<58659> A_IWL<58658> A_IWL<58657> A_IWL<58656> A_IWL<58655> A_IWL<58654> A_IWL<58653> A_IWL<58652> A_IWL<58651> A_IWL<58650> A_IWL<58649> A_IWL<58648> A_IWL<58647> A_IWL<58646> A_IWL<58645> A_IWL<58644> A_IWL<58643> A_IWL<58642> A_IWL<58641> A_IWL<58640> A_IWL<58639> A_IWL<58638> A_IWL<58637> A_IWL<58636> A_IWL<58635> A_IWL<58634> A_IWL<58633> A_IWL<58632> A_IWL<58631> A_IWL<58630> A_IWL<58629> A_IWL<58628> A_IWL<58627> A_IWL<58626> A_IWL<58625> A_IWL<58624> A_IWL<58623> A_IWL<58622> A_IWL<58621> A_IWL<58620> A_IWL<58619> A_IWL<58618> A_IWL<58617> A_IWL<58616> A_IWL<58615> A_IWL<58614> A_IWL<58613> A_IWL<58612> A_IWL<58611> A_IWL<58610> A_IWL<58609> A_IWL<58608> A_IWL<58607> A_IWL<58606> A_IWL<58605> A_IWL<58604> A_IWL<58603> A_IWL<58602> A_IWL<58601> A_IWL<58600> A_IWL<58599> A_IWL<58598> A_IWL<58597> A_IWL<58596> A_IWL<58595> A_IWL<58594> A_IWL<58593> A_IWL<58592> A_IWL<58591> A_IWL<58590> A_IWL<58589> A_IWL<58588> A_IWL<58587> A_IWL<58586> A_IWL<58585> A_IWL<58584> A_IWL<58583> A_IWL<58582> A_IWL<58581> A_IWL<58580> A_IWL<58579> A_IWL<58578> A_IWL<58577> A_IWL<58576> A_IWL<58575> A_IWL<58574> A_IWL<58573> A_IWL<58572> A_IWL<58571> A_IWL<58570> A_IWL<58569> A_IWL<58568> A_IWL<58567> A_IWL<58566> A_IWL<58565> A_IWL<58564> A_IWL<58563> A_IWL<58562> A_IWL<58561> A_IWL<58560> A_IWL<58559> A_IWL<58558> A_IWL<58557> A_IWL<58556> A_IWL<58555> A_IWL<58554> A_IWL<58553> A_IWL<58552> A_IWL<58551> A_IWL<58550> A_IWL<58549> A_IWL<58548> A_IWL<58547> A_IWL<58546> A_IWL<58545> A_IWL<58544> A_IWL<58543> A_IWL<58542> A_IWL<58541> A_IWL<58540> A_IWL<58539> A_IWL<58538> A_IWL<58537> A_IWL<58536> A_IWL<58535> A_IWL<58534> A_IWL<58533> A_IWL<58532> A_IWL<58531> A_IWL<58530> A_IWL<58529> A_IWL<58528> A_IWL<58527> A_IWL<58526> A_IWL<58525> A_IWL<58524> A_IWL<58523> A_IWL<58522> A_IWL<58521> A_IWL<58520> A_IWL<58519> A_IWL<58518> A_IWL<58517> A_IWL<58516> A_IWL<58515> A_IWL<58514> A_IWL<58513> A_IWL<58512> A_IWL<58511> A_IWL<58510> A_IWL<58509> A_IWL<58508> A_IWL<58507> A_IWL<58506> A_IWL<58505> A_IWL<58504> A_IWL<58503> A_IWL<58502> A_IWL<58501> A_IWL<58500> A_IWL<58499> A_IWL<58498> A_IWL<58497> A_IWL<58496> A_IWL<58495> A_IWL<58494> A_IWL<58493> A_IWL<58492> A_IWL<58491> A_IWL<58490> A_IWL<58489> A_IWL<58488> A_IWL<58487> A_IWL<58486> A_IWL<58485> A_IWL<58484> A_IWL<58483> A_IWL<58482> A_IWL<58481> A_IWL<58480> A_IWL<58479> A_IWL<58478> A_IWL<58477> A_IWL<58476> A_IWL<58475> A_IWL<58474> A_IWL<58473> A_IWL<58472> A_IWL<58471> A_IWL<58470> A_IWL<58469> A_IWL<58468> A_IWL<58467> A_IWL<58466> A_IWL<58465> A_IWL<58464> A_IWL<58463> A_IWL<58462> A_IWL<58461> A_IWL<58460> A_IWL<58459> A_IWL<58458> A_IWL<58457> A_IWL<58456> A_IWL<58455> A_IWL<58454> A_IWL<58453> A_IWL<58452> A_IWL<58451> A_IWL<58450> A_IWL<58449> A_IWL<58448> A_IWL<58447> A_IWL<58446> A_IWL<58445> A_IWL<58444> A_IWL<58443> A_IWL<58442> A_IWL<58441> A_IWL<58440> A_IWL<58439> A_IWL<58438> A_IWL<58437> A_IWL<58436> A_IWL<58435> A_IWL<58434> A_IWL<58433> A_IWL<58432> A_IWL<58431> A_IWL<58430> A_IWL<58429> A_IWL<58428> A_IWL<58427> A_IWL<58426> A_IWL<58425> A_IWL<58424> A_IWL<58423> A_IWL<58422> A_IWL<58421> A_IWL<58420> A_IWL<58419> A_IWL<58418> A_IWL<58417> A_IWL<58416> A_IWL<58415> A_IWL<58414> A_IWL<58413> A_IWL<58412> A_IWL<58411> A_IWL<58410> A_IWL<58409> A_IWL<58408> A_IWL<58407> A_IWL<58406> A_IWL<58405> A_IWL<58404> A_IWL<58403> A_IWL<58402> A_IWL<58401> A_IWL<58400> A_IWL<58399> A_IWL<58398> A_IWL<58397> A_IWL<58396> A_IWL<58395> A_IWL<58394> A_IWL<58393> A_IWL<58392> A_IWL<58391> A_IWL<58390> A_IWL<58389> A_IWL<58388> A_IWL<58387> A_IWL<58386> A_IWL<58385> A_IWL<58384> A_IWL<58383> A_IWL<58382> A_IWL<58381> A_IWL<58380> A_IWL<58379> A_IWL<58378> A_IWL<58377> A_IWL<58376> A_IWL<58375> A_IWL<58374> A_IWL<58373> A_IWL<58372> A_IWL<58371> A_IWL<58370> A_IWL<58369> A_IWL<58368> A_IWL<59391> A_IWL<59390> A_IWL<59389> A_IWL<59388> A_IWL<59387> A_IWL<59386> A_IWL<59385> A_IWL<59384> A_IWL<59383> A_IWL<59382> A_IWL<59381> A_IWL<59380> A_IWL<59379> A_IWL<59378> A_IWL<59377> A_IWL<59376> A_IWL<59375> A_IWL<59374> A_IWL<59373> A_IWL<59372> A_IWL<59371> A_IWL<59370> A_IWL<59369> A_IWL<59368> A_IWL<59367> A_IWL<59366> A_IWL<59365> A_IWL<59364> A_IWL<59363> A_IWL<59362> A_IWL<59361> A_IWL<59360> A_IWL<59359> A_IWL<59358> A_IWL<59357> A_IWL<59356> A_IWL<59355> A_IWL<59354> A_IWL<59353> A_IWL<59352> A_IWL<59351> A_IWL<59350> A_IWL<59349> A_IWL<59348> A_IWL<59347> A_IWL<59346> A_IWL<59345> A_IWL<59344> A_IWL<59343> A_IWL<59342> A_IWL<59341> A_IWL<59340> A_IWL<59339> A_IWL<59338> A_IWL<59337> A_IWL<59336> A_IWL<59335> A_IWL<59334> A_IWL<59333> A_IWL<59332> A_IWL<59331> A_IWL<59330> A_IWL<59329> A_IWL<59328> A_IWL<59327> A_IWL<59326> A_IWL<59325> A_IWL<59324> A_IWL<59323> A_IWL<59322> A_IWL<59321> A_IWL<59320> A_IWL<59319> A_IWL<59318> A_IWL<59317> A_IWL<59316> A_IWL<59315> A_IWL<59314> A_IWL<59313> A_IWL<59312> A_IWL<59311> A_IWL<59310> A_IWL<59309> A_IWL<59308> A_IWL<59307> A_IWL<59306> A_IWL<59305> A_IWL<59304> A_IWL<59303> A_IWL<59302> A_IWL<59301> A_IWL<59300> A_IWL<59299> A_IWL<59298> A_IWL<59297> A_IWL<59296> A_IWL<59295> A_IWL<59294> A_IWL<59293> A_IWL<59292> A_IWL<59291> A_IWL<59290> A_IWL<59289> A_IWL<59288> A_IWL<59287> A_IWL<59286> A_IWL<59285> A_IWL<59284> A_IWL<59283> A_IWL<59282> A_IWL<59281> A_IWL<59280> A_IWL<59279> A_IWL<59278> A_IWL<59277> A_IWL<59276> A_IWL<59275> A_IWL<59274> A_IWL<59273> A_IWL<59272> A_IWL<59271> A_IWL<59270> A_IWL<59269> A_IWL<59268> A_IWL<59267> A_IWL<59266> A_IWL<59265> A_IWL<59264> A_IWL<59263> A_IWL<59262> A_IWL<59261> A_IWL<59260> A_IWL<59259> A_IWL<59258> A_IWL<59257> A_IWL<59256> A_IWL<59255> A_IWL<59254> A_IWL<59253> A_IWL<59252> A_IWL<59251> A_IWL<59250> A_IWL<59249> A_IWL<59248> A_IWL<59247> A_IWL<59246> A_IWL<59245> A_IWL<59244> A_IWL<59243> A_IWL<59242> A_IWL<59241> A_IWL<59240> A_IWL<59239> A_IWL<59238> A_IWL<59237> A_IWL<59236> A_IWL<59235> A_IWL<59234> A_IWL<59233> A_IWL<59232> A_IWL<59231> A_IWL<59230> A_IWL<59229> A_IWL<59228> A_IWL<59227> A_IWL<59226> A_IWL<59225> A_IWL<59224> A_IWL<59223> A_IWL<59222> A_IWL<59221> A_IWL<59220> A_IWL<59219> A_IWL<59218> A_IWL<59217> A_IWL<59216> A_IWL<59215> A_IWL<59214> A_IWL<59213> A_IWL<59212> A_IWL<59211> A_IWL<59210> A_IWL<59209> A_IWL<59208> A_IWL<59207> A_IWL<59206> A_IWL<59205> A_IWL<59204> A_IWL<59203> A_IWL<59202> A_IWL<59201> A_IWL<59200> A_IWL<59199> A_IWL<59198> A_IWL<59197> A_IWL<59196> A_IWL<59195> A_IWL<59194> A_IWL<59193> A_IWL<59192> A_IWL<59191> A_IWL<59190> A_IWL<59189> A_IWL<59188> A_IWL<59187> A_IWL<59186> A_IWL<59185> A_IWL<59184> A_IWL<59183> A_IWL<59182> A_IWL<59181> A_IWL<59180> A_IWL<59179> A_IWL<59178> A_IWL<59177> A_IWL<59176> A_IWL<59175> A_IWL<59174> A_IWL<59173> A_IWL<59172> A_IWL<59171> A_IWL<59170> A_IWL<59169> A_IWL<59168> A_IWL<59167> A_IWL<59166> A_IWL<59165> A_IWL<59164> A_IWL<59163> A_IWL<59162> A_IWL<59161> A_IWL<59160> A_IWL<59159> A_IWL<59158> A_IWL<59157> A_IWL<59156> A_IWL<59155> A_IWL<59154> A_IWL<59153> A_IWL<59152> A_IWL<59151> A_IWL<59150> A_IWL<59149> A_IWL<59148> A_IWL<59147> A_IWL<59146> A_IWL<59145> A_IWL<59144> A_IWL<59143> A_IWL<59142> A_IWL<59141> A_IWL<59140> A_IWL<59139> A_IWL<59138> A_IWL<59137> A_IWL<59136> A_IWL<59135> A_IWL<59134> A_IWL<59133> A_IWL<59132> A_IWL<59131> A_IWL<59130> A_IWL<59129> A_IWL<59128> A_IWL<59127> A_IWL<59126> A_IWL<59125> A_IWL<59124> A_IWL<59123> A_IWL<59122> A_IWL<59121> A_IWL<59120> A_IWL<59119> A_IWL<59118> A_IWL<59117> A_IWL<59116> A_IWL<59115> A_IWL<59114> A_IWL<59113> A_IWL<59112> A_IWL<59111> A_IWL<59110> A_IWL<59109> A_IWL<59108> A_IWL<59107> A_IWL<59106> A_IWL<59105> A_IWL<59104> A_IWL<59103> A_IWL<59102> A_IWL<59101> A_IWL<59100> A_IWL<59099> A_IWL<59098> A_IWL<59097> A_IWL<59096> A_IWL<59095> A_IWL<59094> A_IWL<59093> A_IWL<59092> A_IWL<59091> A_IWL<59090> A_IWL<59089> A_IWL<59088> A_IWL<59087> A_IWL<59086> A_IWL<59085> A_IWL<59084> A_IWL<59083> A_IWL<59082> A_IWL<59081> A_IWL<59080> A_IWL<59079> A_IWL<59078> A_IWL<59077> A_IWL<59076> A_IWL<59075> A_IWL<59074> A_IWL<59073> A_IWL<59072> A_IWL<59071> A_IWL<59070> A_IWL<59069> A_IWL<59068> A_IWL<59067> A_IWL<59066> A_IWL<59065> A_IWL<59064> A_IWL<59063> A_IWL<59062> A_IWL<59061> A_IWL<59060> A_IWL<59059> A_IWL<59058> A_IWL<59057> A_IWL<59056> A_IWL<59055> A_IWL<59054> A_IWL<59053> A_IWL<59052> A_IWL<59051> A_IWL<59050> A_IWL<59049> A_IWL<59048> A_IWL<59047> A_IWL<59046> A_IWL<59045> A_IWL<59044> A_IWL<59043> A_IWL<59042> A_IWL<59041> A_IWL<59040> A_IWL<59039> A_IWL<59038> A_IWL<59037> A_IWL<59036> A_IWL<59035> A_IWL<59034> A_IWL<59033> A_IWL<59032> A_IWL<59031> A_IWL<59030> A_IWL<59029> A_IWL<59028> A_IWL<59027> A_IWL<59026> A_IWL<59025> A_IWL<59024> A_IWL<59023> A_IWL<59022> A_IWL<59021> A_IWL<59020> A_IWL<59019> A_IWL<59018> A_IWL<59017> A_IWL<59016> A_IWL<59015> A_IWL<59014> A_IWL<59013> A_IWL<59012> A_IWL<59011> A_IWL<59010> A_IWL<59009> A_IWL<59008> A_IWL<59007> A_IWL<59006> A_IWL<59005> A_IWL<59004> A_IWL<59003> A_IWL<59002> A_IWL<59001> A_IWL<59000> A_IWL<58999> A_IWL<58998> A_IWL<58997> A_IWL<58996> A_IWL<58995> A_IWL<58994> A_IWL<58993> A_IWL<58992> A_IWL<58991> A_IWL<58990> A_IWL<58989> A_IWL<58988> A_IWL<58987> A_IWL<58986> A_IWL<58985> A_IWL<58984> A_IWL<58983> A_IWL<58982> A_IWL<58981> A_IWL<58980> A_IWL<58979> A_IWL<58978> A_IWL<58977> A_IWL<58976> A_IWL<58975> A_IWL<58974> A_IWL<58973> A_IWL<58972> A_IWL<58971> A_IWL<58970> A_IWL<58969> A_IWL<58968> A_IWL<58967> A_IWL<58966> A_IWL<58965> A_IWL<58964> A_IWL<58963> A_IWL<58962> A_IWL<58961> A_IWL<58960> A_IWL<58959> A_IWL<58958> A_IWL<58957> A_IWL<58956> A_IWL<58955> A_IWL<58954> A_IWL<58953> A_IWL<58952> A_IWL<58951> A_IWL<58950> A_IWL<58949> A_IWL<58948> A_IWL<58947> A_IWL<58946> A_IWL<58945> A_IWL<58944> A_IWL<58943> A_IWL<58942> A_IWL<58941> A_IWL<58940> A_IWL<58939> A_IWL<58938> A_IWL<58937> A_IWL<58936> A_IWL<58935> A_IWL<58934> A_IWL<58933> A_IWL<58932> A_IWL<58931> A_IWL<58930> A_IWL<58929> A_IWL<58928> A_IWL<58927> A_IWL<58926> A_IWL<58925> A_IWL<58924> A_IWL<58923> A_IWL<58922> A_IWL<58921> A_IWL<58920> A_IWL<58919> A_IWL<58918> A_IWL<58917> A_IWL<58916> A_IWL<58915> A_IWL<58914> A_IWL<58913> A_IWL<58912> A_IWL<58911> A_IWL<58910> A_IWL<58909> A_IWL<58908> A_IWL<58907> A_IWL<58906> A_IWL<58905> A_IWL<58904> A_IWL<58903> A_IWL<58902> A_IWL<58901> A_IWL<58900> A_IWL<58899> A_IWL<58898> A_IWL<58897> A_IWL<58896> A_IWL<58895> A_IWL<58894> A_IWL<58893> A_IWL<58892> A_IWL<58891> A_IWL<58890> A_IWL<58889> A_IWL<58888> A_IWL<58887> A_IWL<58886> A_IWL<58885> A_IWL<58884> A_IWL<58883> A_IWL<58882> A_IWL<58881> A_IWL<58880> VDD_CORE VSS / RM_IHPSG13_8192x32_c4_1P_COLUMN_pcell_0 +XCOL<114> A_BLC<229> A_BLC<228> A_BLC_TOP<229> A_BLC_TOP<228> A_BLT<229> A_BLT<228> A_BLT_TOP<229> A_BLT_TOP<228> A_IWL<58367> A_IWL<58366> A_IWL<58365> A_IWL<58364> A_IWL<58363> A_IWL<58362> A_IWL<58361> A_IWL<58360> A_IWL<58359> A_IWL<58358> A_IWL<58357> A_IWL<58356> A_IWL<58355> A_IWL<58354> A_IWL<58353> A_IWL<58352> A_IWL<58351> A_IWL<58350> A_IWL<58349> A_IWL<58348> A_IWL<58347> A_IWL<58346> A_IWL<58345> A_IWL<58344> A_IWL<58343> A_IWL<58342> A_IWL<58341> A_IWL<58340> A_IWL<58339> A_IWL<58338> A_IWL<58337> A_IWL<58336> A_IWL<58335> A_IWL<58334> A_IWL<58333> A_IWL<58332> A_IWL<58331> A_IWL<58330> A_IWL<58329> A_IWL<58328> A_IWL<58327> A_IWL<58326> A_IWL<58325> A_IWL<58324> A_IWL<58323> A_IWL<58322> A_IWL<58321> A_IWL<58320> A_IWL<58319> A_IWL<58318> A_IWL<58317> A_IWL<58316> A_IWL<58315> A_IWL<58314> A_IWL<58313> A_IWL<58312> A_IWL<58311> A_IWL<58310> A_IWL<58309> A_IWL<58308> A_IWL<58307> A_IWL<58306> A_IWL<58305> A_IWL<58304> A_IWL<58303> A_IWL<58302> A_IWL<58301> A_IWL<58300> A_IWL<58299> A_IWL<58298> A_IWL<58297> A_IWL<58296> A_IWL<58295> A_IWL<58294> A_IWL<58293> A_IWL<58292> A_IWL<58291> A_IWL<58290> A_IWL<58289> A_IWL<58288> A_IWL<58287> A_IWL<58286> A_IWL<58285> A_IWL<58284> A_IWL<58283> A_IWL<58282> A_IWL<58281> A_IWL<58280> A_IWL<58279> A_IWL<58278> A_IWL<58277> A_IWL<58276> A_IWL<58275> A_IWL<58274> A_IWL<58273> A_IWL<58272> A_IWL<58271> A_IWL<58270> A_IWL<58269> A_IWL<58268> A_IWL<58267> A_IWL<58266> A_IWL<58265> A_IWL<58264> A_IWL<58263> A_IWL<58262> A_IWL<58261> A_IWL<58260> A_IWL<58259> A_IWL<58258> A_IWL<58257> A_IWL<58256> A_IWL<58255> A_IWL<58254> A_IWL<58253> A_IWL<58252> A_IWL<58251> A_IWL<58250> A_IWL<58249> A_IWL<58248> A_IWL<58247> A_IWL<58246> A_IWL<58245> A_IWL<58244> A_IWL<58243> A_IWL<58242> A_IWL<58241> A_IWL<58240> A_IWL<58239> A_IWL<58238> A_IWL<58237> A_IWL<58236> A_IWL<58235> A_IWL<58234> A_IWL<58233> A_IWL<58232> A_IWL<58231> A_IWL<58230> A_IWL<58229> A_IWL<58228> A_IWL<58227> A_IWL<58226> A_IWL<58225> A_IWL<58224> A_IWL<58223> A_IWL<58222> A_IWL<58221> A_IWL<58220> A_IWL<58219> A_IWL<58218> A_IWL<58217> A_IWL<58216> A_IWL<58215> A_IWL<58214> A_IWL<58213> A_IWL<58212> A_IWL<58211> A_IWL<58210> A_IWL<58209> A_IWL<58208> A_IWL<58207> A_IWL<58206> A_IWL<58205> A_IWL<58204> A_IWL<58203> A_IWL<58202> A_IWL<58201> A_IWL<58200> A_IWL<58199> A_IWL<58198> A_IWL<58197> A_IWL<58196> A_IWL<58195> A_IWL<58194> A_IWL<58193> A_IWL<58192> A_IWL<58191> A_IWL<58190> A_IWL<58189> A_IWL<58188> A_IWL<58187> A_IWL<58186> A_IWL<58185> A_IWL<58184> A_IWL<58183> A_IWL<58182> A_IWL<58181> A_IWL<58180> A_IWL<58179> A_IWL<58178> A_IWL<58177> A_IWL<58176> A_IWL<58175> A_IWL<58174> A_IWL<58173> A_IWL<58172> A_IWL<58171> A_IWL<58170> A_IWL<58169> A_IWL<58168> A_IWL<58167> A_IWL<58166> A_IWL<58165> A_IWL<58164> A_IWL<58163> A_IWL<58162> A_IWL<58161> A_IWL<58160> A_IWL<58159> A_IWL<58158> A_IWL<58157> A_IWL<58156> A_IWL<58155> A_IWL<58154> A_IWL<58153> A_IWL<58152> A_IWL<58151> A_IWL<58150> A_IWL<58149> A_IWL<58148> A_IWL<58147> A_IWL<58146> A_IWL<58145> A_IWL<58144> A_IWL<58143> A_IWL<58142> A_IWL<58141> A_IWL<58140> A_IWL<58139> A_IWL<58138> A_IWL<58137> A_IWL<58136> A_IWL<58135> A_IWL<58134> A_IWL<58133> A_IWL<58132> A_IWL<58131> A_IWL<58130> A_IWL<58129> A_IWL<58128> A_IWL<58127> A_IWL<58126> A_IWL<58125> A_IWL<58124> A_IWL<58123> A_IWL<58122> A_IWL<58121> A_IWL<58120> A_IWL<58119> A_IWL<58118> A_IWL<58117> A_IWL<58116> A_IWL<58115> A_IWL<58114> A_IWL<58113> A_IWL<58112> A_IWL<58111> A_IWL<58110> A_IWL<58109> A_IWL<58108> A_IWL<58107> A_IWL<58106> A_IWL<58105> A_IWL<58104> A_IWL<58103> A_IWL<58102> A_IWL<58101> A_IWL<58100> A_IWL<58099> A_IWL<58098> A_IWL<58097> A_IWL<58096> A_IWL<58095> A_IWL<58094> A_IWL<58093> A_IWL<58092> A_IWL<58091> A_IWL<58090> A_IWL<58089> A_IWL<58088> A_IWL<58087> A_IWL<58086> A_IWL<58085> A_IWL<58084> A_IWL<58083> A_IWL<58082> A_IWL<58081> A_IWL<58080> A_IWL<58079> A_IWL<58078> A_IWL<58077> A_IWL<58076> A_IWL<58075> A_IWL<58074> A_IWL<58073> A_IWL<58072> A_IWL<58071> A_IWL<58070> A_IWL<58069> A_IWL<58068> A_IWL<58067> A_IWL<58066> A_IWL<58065> A_IWL<58064> A_IWL<58063> A_IWL<58062> A_IWL<58061> A_IWL<58060> A_IWL<58059> A_IWL<58058> A_IWL<58057> A_IWL<58056> A_IWL<58055> A_IWL<58054> A_IWL<58053> A_IWL<58052> A_IWL<58051> A_IWL<58050> A_IWL<58049> A_IWL<58048> A_IWL<58047> A_IWL<58046> A_IWL<58045> A_IWL<58044> A_IWL<58043> A_IWL<58042> A_IWL<58041> A_IWL<58040> A_IWL<58039> A_IWL<58038> A_IWL<58037> A_IWL<58036> A_IWL<58035> A_IWL<58034> A_IWL<58033> A_IWL<58032> A_IWL<58031> A_IWL<58030> A_IWL<58029> A_IWL<58028> A_IWL<58027> A_IWL<58026> A_IWL<58025> A_IWL<58024> A_IWL<58023> A_IWL<58022> A_IWL<58021> A_IWL<58020> A_IWL<58019> A_IWL<58018> A_IWL<58017> A_IWL<58016> A_IWL<58015> A_IWL<58014> A_IWL<58013> A_IWL<58012> A_IWL<58011> A_IWL<58010> A_IWL<58009> A_IWL<58008> A_IWL<58007> A_IWL<58006> A_IWL<58005> A_IWL<58004> A_IWL<58003> A_IWL<58002> A_IWL<58001> A_IWL<58000> A_IWL<57999> A_IWL<57998> A_IWL<57997> A_IWL<57996> A_IWL<57995> A_IWL<57994> A_IWL<57993> A_IWL<57992> A_IWL<57991> A_IWL<57990> A_IWL<57989> A_IWL<57988> A_IWL<57987> A_IWL<57986> A_IWL<57985> A_IWL<57984> A_IWL<57983> A_IWL<57982> A_IWL<57981> A_IWL<57980> A_IWL<57979> A_IWL<57978> A_IWL<57977> A_IWL<57976> A_IWL<57975> A_IWL<57974> A_IWL<57973> A_IWL<57972> A_IWL<57971> A_IWL<57970> A_IWL<57969> A_IWL<57968> A_IWL<57967> A_IWL<57966> A_IWL<57965> A_IWL<57964> A_IWL<57963> A_IWL<57962> A_IWL<57961> A_IWL<57960> A_IWL<57959> A_IWL<57958> A_IWL<57957> A_IWL<57956> A_IWL<57955> A_IWL<57954> A_IWL<57953> A_IWL<57952> A_IWL<57951> A_IWL<57950> A_IWL<57949> A_IWL<57948> A_IWL<57947> A_IWL<57946> A_IWL<57945> A_IWL<57944> A_IWL<57943> A_IWL<57942> A_IWL<57941> A_IWL<57940> A_IWL<57939> A_IWL<57938> A_IWL<57937> A_IWL<57936> A_IWL<57935> A_IWL<57934> A_IWL<57933> A_IWL<57932> A_IWL<57931> A_IWL<57930> A_IWL<57929> A_IWL<57928> A_IWL<57927> A_IWL<57926> A_IWL<57925> A_IWL<57924> A_IWL<57923> A_IWL<57922> A_IWL<57921> A_IWL<57920> A_IWL<57919> A_IWL<57918> A_IWL<57917> A_IWL<57916> A_IWL<57915> A_IWL<57914> A_IWL<57913> A_IWL<57912> A_IWL<57911> A_IWL<57910> A_IWL<57909> A_IWL<57908> A_IWL<57907> A_IWL<57906> A_IWL<57905> A_IWL<57904> A_IWL<57903> A_IWL<57902> A_IWL<57901> A_IWL<57900> A_IWL<57899> A_IWL<57898> A_IWL<57897> A_IWL<57896> A_IWL<57895> A_IWL<57894> A_IWL<57893> A_IWL<57892> A_IWL<57891> A_IWL<57890> A_IWL<57889> A_IWL<57888> A_IWL<57887> A_IWL<57886> A_IWL<57885> A_IWL<57884> A_IWL<57883> A_IWL<57882> A_IWL<57881> A_IWL<57880> A_IWL<57879> A_IWL<57878> A_IWL<57877> A_IWL<57876> A_IWL<57875> A_IWL<57874> A_IWL<57873> A_IWL<57872> A_IWL<57871> A_IWL<57870> A_IWL<57869> A_IWL<57868> A_IWL<57867> A_IWL<57866> A_IWL<57865> A_IWL<57864> A_IWL<57863> A_IWL<57862> A_IWL<57861> A_IWL<57860> A_IWL<57859> A_IWL<57858> A_IWL<57857> A_IWL<57856> A_IWL<58879> A_IWL<58878> A_IWL<58877> A_IWL<58876> A_IWL<58875> A_IWL<58874> A_IWL<58873> A_IWL<58872> A_IWL<58871> A_IWL<58870> A_IWL<58869> A_IWL<58868> A_IWL<58867> A_IWL<58866> A_IWL<58865> A_IWL<58864> A_IWL<58863> A_IWL<58862> A_IWL<58861> A_IWL<58860> A_IWL<58859> A_IWL<58858> A_IWL<58857> A_IWL<58856> A_IWL<58855> A_IWL<58854> A_IWL<58853> A_IWL<58852> A_IWL<58851> A_IWL<58850> A_IWL<58849> A_IWL<58848> A_IWL<58847> A_IWL<58846> A_IWL<58845> A_IWL<58844> A_IWL<58843> A_IWL<58842> A_IWL<58841> A_IWL<58840> A_IWL<58839> A_IWL<58838> A_IWL<58837> A_IWL<58836> A_IWL<58835> A_IWL<58834> A_IWL<58833> A_IWL<58832> A_IWL<58831> A_IWL<58830> A_IWL<58829> A_IWL<58828> A_IWL<58827> A_IWL<58826> A_IWL<58825> A_IWL<58824> A_IWL<58823> A_IWL<58822> A_IWL<58821> A_IWL<58820> A_IWL<58819> A_IWL<58818> A_IWL<58817> A_IWL<58816> A_IWL<58815> A_IWL<58814> A_IWL<58813> A_IWL<58812> A_IWL<58811> A_IWL<58810> A_IWL<58809> A_IWL<58808> A_IWL<58807> A_IWL<58806> A_IWL<58805> A_IWL<58804> A_IWL<58803> A_IWL<58802> A_IWL<58801> A_IWL<58800> A_IWL<58799> A_IWL<58798> A_IWL<58797> A_IWL<58796> A_IWL<58795> A_IWL<58794> A_IWL<58793> A_IWL<58792> A_IWL<58791> A_IWL<58790> A_IWL<58789> A_IWL<58788> A_IWL<58787> A_IWL<58786> A_IWL<58785> A_IWL<58784> A_IWL<58783> A_IWL<58782> A_IWL<58781> A_IWL<58780> A_IWL<58779> A_IWL<58778> A_IWL<58777> A_IWL<58776> A_IWL<58775> A_IWL<58774> A_IWL<58773> A_IWL<58772> A_IWL<58771> A_IWL<58770> A_IWL<58769> A_IWL<58768> A_IWL<58767> A_IWL<58766> A_IWL<58765> A_IWL<58764> A_IWL<58763> A_IWL<58762> A_IWL<58761> A_IWL<58760> A_IWL<58759> A_IWL<58758> A_IWL<58757> A_IWL<58756> A_IWL<58755> A_IWL<58754> A_IWL<58753> A_IWL<58752> A_IWL<58751> A_IWL<58750> A_IWL<58749> A_IWL<58748> A_IWL<58747> A_IWL<58746> A_IWL<58745> A_IWL<58744> A_IWL<58743> A_IWL<58742> A_IWL<58741> A_IWL<58740> A_IWL<58739> A_IWL<58738> A_IWL<58737> A_IWL<58736> A_IWL<58735> A_IWL<58734> A_IWL<58733> A_IWL<58732> A_IWL<58731> A_IWL<58730> A_IWL<58729> A_IWL<58728> A_IWL<58727> A_IWL<58726> A_IWL<58725> A_IWL<58724> A_IWL<58723> A_IWL<58722> A_IWL<58721> A_IWL<58720> A_IWL<58719> A_IWL<58718> A_IWL<58717> A_IWL<58716> A_IWL<58715> A_IWL<58714> A_IWL<58713> A_IWL<58712> A_IWL<58711> A_IWL<58710> A_IWL<58709> A_IWL<58708> A_IWL<58707> A_IWL<58706> A_IWL<58705> A_IWL<58704> A_IWL<58703> A_IWL<58702> A_IWL<58701> A_IWL<58700> A_IWL<58699> A_IWL<58698> A_IWL<58697> A_IWL<58696> A_IWL<58695> A_IWL<58694> A_IWL<58693> A_IWL<58692> A_IWL<58691> A_IWL<58690> A_IWL<58689> A_IWL<58688> A_IWL<58687> A_IWL<58686> A_IWL<58685> A_IWL<58684> A_IWL<58683> A_IWL<58682> A_IWL<58681> A_IWL<58680> A_IWL<58679> A_IWL<58678> A_IWL<58677> A_IWL<58676> A_IWL<58675> A_IWL<58674> A_IWL<58673> A_IWL<58672> A_IWL<58671> A_IWL<58670> A_IWL<58669> A_IWL<58668> A_IWL<58667> A_IWL<58666> A_IWL<58665> A_IWL<58664> A_IWL<58663> A_IWL<58662> A_IWL<58661> A_IWL<58660> A_IWL<58659> A_IWL<58658> A_IWL<58657> A_IWL<58656> A_IWL<58655> A_IWL<58654> A_IWL<58653> A_IWL<58652> A_IWL<58651> A_IWL<58650> A_IWL<58649> A_IWL<58648> A_IWL<58647> A_IWL<58646> A_IWL<58645> A_IWL<58644> A_IWL<58643> A_IWL<58642> A_IWL<58641> A_IWL<58640> A_IWL<58639> A_IWL<58638> A_IWL<58637> A_IWL<58636> A_IWL<58635> A_IWL<58634> A_IWL<58633> A_IWL<58632> A_IWL<58631> A_IWL<58630> A_IWL<58629> A_IWL<58628> A_IWL<58627> A_IWL<58626> A_IWL<58625> A_IWL<58624> A_IWL<58623> A_IWL<58622> A_IWL<58621> A_IWL<58620> A_IWL<58619> A_IWL<58618> A_IWL<58617> A_IWL<58616> A_IWL<58615> A_IWL<58614> A_IWL<58613> A_IWL<58612> A_IWL<58611> A_IWL<58610> A_IWL<58609> A_IWL<58608> A_IWL<58607> A_IWL<58606> A_IWL<58605> A_IWL<58604> A_IWL<58603> A_IWL<58602> A_IWL<58601> A_IWL<58600> A_IWL<58599> A_IWL<58598> A_IWL<58597> A_IWL<58596> A_IWL<58595> A_IWL<58594> A_IWL<58593> A_IWL<58592> A_IWL<58591> A_IWL<58590> A_IWL<58589> A_IWL<58588> A_IWL<58587> A_IWL<58586> A_IWL<58585> A_IWL<58584> A_IWL<58583> A_IWL<58582> A_IWL<58581> A_IWL<58580> A_IWL<58579> A_IWL<58578> A_IWL<58577> A_IWL<58576> A_IWL<58575> A_IWL<58574> A_IWL<58573> A_IWL<58572> A_IWL<58571> A_IWL<58570> A_IWL<58569> A_IWL<58568> A_IWL<58567> A_IWL<58566> A_IWL<58565> A_IWL<58564> A_IWL<58563> A_IWL<58562> A_IWL<58561> A_IWL<58560> A_IWL<58559> A_IWL<58558> A_IWL<58557> A_IWL<58556> A_IWL<58555> A_IWL<58554> A_IWL<58553> A_IWL<58552> A_IWL<58551> A_IWL<58550> A_IWL<58549> A_IWL<58548> A_IWL<58547> A_IWL<58546> A_IWL<58545> A_IWL<58544> A_IWL<58543> A_IWL<58542> A_IWL<58541> A_IWL<58540> A_IWL<58539> A_IWL<58538> A_IWL<58537> A_IWL<58536> A_IWL<58535> A_IWL<58534> A_IWL<58533> A_IWL<58532> A_IWL<58531> A_IWL<58530> A_IWL<58529> A_IWL<58528> A_IWL<58527> A_IWL<58526> A_IWL<58525> A_IWL<58524> A_IWL<58523> A_IWL<58522> A_IWL<58521> A_IWL<58520> A_IWL<58519> A_IWL<58518> A_IWL<58517> A_IWL<58516> A_IWL<58515> A_IWL<58514> A_IWL<58513> A_IWL<58512> A_IWL<58511> A_IWL<58510> A_IWL<58509> A_IWL<58508> A_IWL<58507> A_IWL<58506> A_IWL<58505> A_IWL<58504> A_IWL<58503> A_IWL<58502> A_IWL<58501> A_IWL<58500> A_IWL<58499> A_IWL<58498> A_IWL<58497> A_IWL<58496> A_IWL<58495> A_IWL<58494> A_IWL<58493> A_IWL<58492> A_IWL<58491> A_IWL<58490> A_IWL<58489> A_IWL<58488> A_IWL<58487> A_IWL<58486> A_IWL<58485> A_IWL<58484> A_IWL<58483> A_IWL<58482> A_IWL<58481> A_IWL<58480> A_IWL<58479> A_IWL<58478> A_IWL<58477> A_IWL<58476> A_IWL<58475> A_IWL<58474> A_IWL<58473> A_IWL<58472> A_IWL<58471> A_IWL<58470> A_IWL<58469> A_IWL<58468> A_IWL<58467> A_IWL<58466> A_IWL<58465> A_IWL<58464> A_IWL<58463> A_IWL<58462> A_IWL<58461> A_IWL<58460> A_IWL<58459> A_IWL<58458> A_IWL<58457> A_IWL<58456> A_IWL<58455> A_IWL<58454> A_IWL<58453> A_IWL<58452> A_IWL<58451> A_IWL<58450> A_IWL<58449> A_IWL<58448> A_IWL<58447> A_IWL<58446> A_IWL<58445> A_IWL<58444> A_IWL<58443> A_IWL<58442> A_IWL<58441> A_IWL<58440> A_IWL<58439> A_IWL<58438> A_IWL<58437> A_IWL<58436> A_IWL<58435> A_IWL<58434> A_IWL<58433> A_IWL<58432> A_IWL<58431> A_IWL<58430> A_IWL<58429> A_IWL<58428> A_IWL<58427> A_IWL<58426> A_IWL<58425> A_IWL<58424> A_IWL<58423> A_IWL<58422> A_IWL<58421> A_IWL<58420> A_IWL<58419> A_IWL<58418> A_IWL<58417> A_IWL<58416> A_IWL<58415> A_IWL<58414> A_IWL<58413> A_IWL<58412> A_IWL<58411> A_IWL<58410> A_IWL<58409> A_IWL<58408> A_IWL<58407> A_IWL<58406> A_IWL<58405> A_IWL<58404> A_IWL<58403> A_IWL<58402> A_IWL<58401> A_IWL<58400> A_IWL<58399> A_IWL<58398> A_IWL<58397> A_IWL<58396> A_IWL<58395> A_IWL<58394> A_IWL<58393> A_IWL<58392> A_IWL<58391> A_IWL<58390> A_IWL<58389> A_IWL<58388> A_IWL<58387> A_IWL<58386> A_IWL<58385> A_IWL<58384> A_IWL<58383> A_IWL<58382> A_IWL<58381> A_IWL<58380> A_IWL<58379> A_IWL<58378> A_IWL<58377> A_IWL<58376> A_IWL<58375> A_IWL<58374> A_IWL<58373> A_IWL<58372> A_IWL<58371> A_IWL<58370> A_IWL<58369> A_IWL<58368> VDD_CORE VSS / RM_IHPSG13_8192x32_c4_1P_COLUMN_pcell_0 +XCOL<113> A_BLC<227> A_BLC<226> A_BLC_TOP<227> A_BLC_TOP<226> A_BLT<227> A_BLT<226> A_BLT_TOP<227> A_BLT_TOP<226> A_IWL<57855> A_IWL<57854> A_IWL<57853> A_IWL<57852> A_IWL<57851> A_IWL<57850> A_IWL<57849> A_IWL<57848> A_IWL<57847> A_IWL<57846> A_IWL<57845> A_IWL<57844> A_IWL<57843> A_IWL<57842> A_IWL<57841> A_IWL<57840> A_IWL<57839> A_IWL<57838> A_IWL<57837> A_IWL<57836> A_IWL<57835> A_IWL<57834> A_IWL<57833> A_IWL<57832> A_IWL<57831> A_IWL<57830> A_IWL<57829> A_IWL<57828> A_IWL<57827> A_IWL<57826> A_IWL<57825> A_IWL<57824> A_IWL<57823> A_IWL<57822> A_IWL<57821> A_IWL<57820> A_IWL<57819> A_IWL<57818> A_IWL<57817> A_IWL<57816> A_IWL<57815> A_IWL<57814> A_IWL<57813> A_IWL<57812> A_IWL<57811> A_IWL<57810> A_IWL<57809> A_IWL<57808> A_IWL<57807> A_IWL<57806> A_IWL<57805> A_IWL<57804> A_IWL<57803> A_IWL<57802> A_IWL<57801> A_IWL<57800> A_IWL<57799> A_IWL<57798> A_IWL<57797> A_IWL<57796> A_IWL<57795> A_IWL<57794> A_IWL<57793> A_IWL<57792> A_IWL<57791> A_IWL<57790> A_IWL<57789> A_IWL<57788> A_IWL<57787> A_IWL<57786> A_IWL<57785> A_IWL<57784> A_IWL<57783> A_IWL<57782> A_IWL<57781> A_IWL<57780> A_IWL<57779> A_IWL<57778> A_IWL<57777> A_IWL<57776> A_IWL<57775> A_IWL<57774> A_IWL<57773> A_IWL<57772> A_IWL<57771> A_IWL<57770> A_IWL<57769> A_IWL<57768> A_IWL<57767> A_IWL<57766> A_IWL<57765> A_IWL<57764> A_IWL<57763> A_IWL<57762> A_IWL<57761> A_IWL<57760> A_IWL<57759> A_IWL<57758> A_IWL<57757> A_IWL<57756> A_IWL<57755> A_IWL<57754> A_IWL<57753> A_IWL<57752> A_IWL<57751> A_IWL<57750> A_IWL<57749> A_IWL<57748> A_IWL<57747> A_IWL<57746> A_IWL<57745> A_IWL<57744> A_IWL<57743> A_IWL<57742> A_IWL<57741> A_IWL<57740> A_IWL<57739> A_IWL<57738> A_IWL<57737> A_IWL<57736> A_IWL<57735> A_IWL<57734> A_IWL<57733> A_IWL<57732> A_IWL<57731> A_IWL<57730> A_IWL<57729> A_IWL<57728> A_IWL<57727> A_IWL<57726> A_IWL<57725> A_IWL<57724> A_IWL<57723> A_IWL<57722> A_IWL<57721> A_IWL<57720> A_IWL<57719> A_IWL<57718> A_IWL<57717> A_IWL<57716> A_IWL<57715> A_IWL<57714> A_IWL<57713> A_IWL<57712> A_IWL<57711> A_IWL<57710> A_IWL<57709> A_IWL<57708> A_IWL<57707> A_IWL<57706> A_IWL<57705> A_IWL<57704> A_IWL<57703> A_IWL<57702> A_IWL<57701> A_IWL<57700> A_IWL<57699> A_IWL<57698> A_IWL<57697> A_IWL<57696> A_IWL<57695> A_IWL<57694> A_IWL<57693> A_IWL<57692> A_IWL<57691> A_IWL<57690> A_IWL<57689> A_IWL<57688> A_IWL<57687> A_IWL<57686> A_IWL<57685> A_IWL<57684> A_IWL<57683> A_IWL<57682> A_IWL<57681> A_IWL<57680> A_IWL<57679> A_IWL<57678> A_IWL<57677> A_IWL<57676> A_IWL<57675> A_IWL<57674> A_IWL<57673> A_IWL<57672> A_IWL<57671> A_IWL<57670> A_IWL<57669> A_IWL<57668> A_IWL<57667> A_IWL<57666> A_IWL<57665> A_IWL<57664> A_IWL<57663> A_IWL<57662> A_IWL<57661> A_IWL<57660> A_IWL<57659> A_IWL<57658> A_IWL<57657> A_IWL<57656> A_IWL<57655> A_IWL<57654> A_IWL<57653> A_IWL<57652> A_IWL<57651> A_IWL<57650> A_IWL<57649> A_IWL<57648> A_IWL<57647> A_IWL<57646> A_IWL<57645> A_IWL<57644> A_IWL<57643> A_IWL<57642> A_IWL<57641> A_IWL<57640> A_IWL<57639> A_IWL<57638> A_IWL<57637> A_IWL<57636> A_IWL<57635> A_IWL<57634> A_IWL<57633> A_IWL<57632> A_IWL<57631> A_IWL<57630> A_IWL<57629> A_IWL<57628> A_IWL<57627> A_IWL<57626> A_IWL<57625> A_IWL<57624> A_IWL<57623> A_IWL<57622> A_IWL<57621> A_IWL<57620> A_IWL<57619> A_IWL<57618> A_IWL<57617> A_IWL<57616> A_IWL<57615> A_IWL<57614> A_IWL<57613> A_IWL<57612> A_IWL<57611> A_IWL<57610> A_IWL<57609> A_IWL<57608> A_IWL<57607> A_IWL<57606> A_IWL<57605> A_IWL<57604> A_IWL<57603> A_IWL<57602> A_IWL<57601> A_IWL<57600> A_IWL<57599> A_IWL<57598> A_IWL<57597> A_IWL<57596> A_IWL<57595> A_IWL<57594> A_IWL<57593> A_IWL<57592> A_IWL<57591> A_IWL<57590> A_IWL<57589> A_IWL<57588> A_IWL<57587> A_IWL<57586> A_IWL<57585> A_IWL<57584> A_IWL<57583> A_IWL<57582> A_IWL<57581> A_IWL<57580> A_IWL<57579> A_IWL<57578> A_IWL<57577> A_IWL<57576> A_IWL<57575> A_IWL<57574> A_IWL<57573> A_IWL<57572> A_IWL<57571> A_IWL<57570> A_IWL<57569> A_IWL<57568> A_IWL<57567> A_IWL<57566> A_IWL<57565> A_IWL<57564> A_IWL<57563> A_IWL<57562> A_IWL<57561> A_IWL<57560> A_IWL<57559> A_IWL<57558> A_IWL<57557> A_IWL<57556> A_IWL<57555> A_IWL<57554> A_IWL<57553> A_IWL<57552> A_IWL<57551> A_IWL<57550> A_IWL<57549> A_IWL<57548> A_IWL<57547> A_IWL<57546> A_IWL<57545> A_IWL<57544> A_IWL<57543> A_IWL<57542> A_IWL<57541> A_IWL<57540> A_IWL<57539> A_IWL<57538> A_IWL<57537> A_IWL<57536> A_IWL<57535> A_IWL<57534> A_IWL<57533> A_IWL<57532> A_IWL<57531> A_IWL<57530> A_IWL<57529> A_IWL<57528> A_IWL<57527> A_IWL<57526> A_IWL<57525> A_IWL<57524> A_IWL<57523> A_IWL<57522> A_IWL<57521> A_IWL<57520> A_IWL<57519> A_IWL<57518> A_IWL<57517> A_IWL<57516> A_IWL<57515> A_IWL<57514> A_IWL<57513> A_IWL<57512> A_IWL<57511> A_IWL<57510> A_IWL<57509> A_IWL<57508> A_IWL<57507> A_IWL<57506> A_IWL<57505> A_IWL<57504> A_IWL<57503> A_IWL<57502> A_IWL<57501> A_IWL<57500> A_IWL<57499> A_IWL<57498> A_IWL<57497> A_IWL<57496> A_IWL<57495> A_IWL<57494> A_IWL<57493> A_IWL<57492> A_IWL<57491> A_IWL<57490> A_IWL<57489> A_IWL<57488> A_IWL<57487> A_IWL<57486> A_IWL<57485> A_IWL<57484> A_IWL<57483> A_IWL<57482> A_IWL<57481> A_IWL<57480> A_IWL<57479> A_IWL<57478> A_IWL<57477> A_IWL<57476> A_IWL<57475> A_IWL<57474> A_IWL<57473> A_IWL<57472> A_IWL<57471> A_IWL<57470> A_IWL<57469> A_IWL<57468> A_IWL<57467> A_IWL<57466> A_IWL<57465> A_IWL<57464> A_IWL<57463> A_IWL<57462> A_IWL<57461> A_IWL<57460> A_IWL<57459> A_IWL<57458> A_IWL<57457> A_IWL<57456> A_IWL<57455> A_IWL<57454> A_IWL<57453> A_IWL<57452> A_IWL<57451> A_IWL<57450> A_IWL<57449> A_IWL<57448> A_IWL<57447> A_IWL<57446> A_IWL<57445> A_IWL<57444> A_IWL<57443> A_IWL<57442> A_IWL<57441> A_IWL<57440> A_IWL<57439> A_IWL<57438> A_IWL<57437> A_IWL<57436> A_IWL<57435> A_IWL<57434> A_IWL<57433> A_IWL<57432> A_IWL<57431> A_IWL<57430> A_IWL<57429> A_IWL<57428> A_IWL<57427> A_IWL<57426> A_IWL<57425> A_IWL<57424> A_IWL<57423> A_IWL<57422> A_IWL<57421> A_IWL<57420> A_IWL<57419> A_IWL<57418> A_IWL<57417> A_IWL<57416> A_IWL<57415> A_IWL<57414> A_IWL<57413> A_IWL<57412> A_IWL<57411> A_IWL<57410> A_IWL<57409> A_IWL<57408> A_IWL<57407> A_IWL<57406> A_IWL<57405> A_IWL<57404> A_IWL<57403> A_IWL<57402> A_IWL<57401> A_IWL<57400> A_IWL<57399> A_IWL<57398> A_IWL<57397> A_IWL<57396> A_IWL<57395> A_IWL<57394> A_IWL<57393> A_IWL<57392> A_IWL<57391> A_IWL<57390> A_IWL<57389> A_IWL<57388> A_IWL<57387> A_IWL<57386> A_IWL<57385> A_IWL<57384> A_IWL<57383> A_IWL<57382> A_IWL<57381> A_IWL<57380> A_IWL<57379> A_IWL<57378> A_IWL<57377> A_IWL<57376> A_IWL<57375> A_IWL<57374> A_IWL<57373> A_IWL<57372> A_IWL<57371> A_IWL<57370> A_IWL<57369> A_IWL<57368> A_IWL<57367> A_IWL<57366> A_IWL<57365> A_IWL<57364> A_IWL<57363> A_IWL<57362> A_IWL<57361> A_IWL<57360> A_IWL<57359> A_IWL<57358> A_IWL<57357> A_IWL<57356> A_IWL<57355> A_IWL<57354> A_IWL<57353> A_IWL<57352> A_IWL<57351> A_IWL<57350> A_IWL<57349> A_IWL<57348> A_IWL<57347> A_IWL<57346> A_IWL<57345> A_IWL<57344> A_IWL<58367> A_IWL<58366> A_IWL<58365> A_IWL<58364> A_IWL<58363> A_IWL<58362> A_IWL<58361> A_IWL<58360> A_IWL<58359> A_IWL<58358> A_IWL<58357> A_IWL<58356> A_IWL<58355> A_IWL<58354> A_IWL<58353> A_IWL<58352> A_IWL<58351> A_IWL<58350> A_IWL<58349> A_IWL<58348> A_IWL<58347> A_IWL<58346> A_IWL<58345> A_IWL<58344> A_IWL<58343> A_IWL<58342> A_IWL<58341> A_IWL<58340> A_IWL<58339> A_IWL<58338> A_IWL<58337> A_IWL<58336> A_IWL<58335> A_IWL<58334> A_IWL<58333> A_IWL<58332> A_IWL<58331> A_IWL<58330> A_IWL<58329> A_IWL<58328> A_IWL<58327> A_IWL<58326> A_IWL<58325> A_IWL<58324> A_IWL<58323> A_IWL<58322> A_IWL<58321> A_IWL<58320> A_IWL<58319> A_IWL<58318> A_IWL<58317> A_IWL<58316> A_IWL<58315> A_IWL<58314> A_IWL<58313> A_IWL<58312> A_IWL<58311> A_IWL<58310> A_IWL<58309> A_IWL<58308> A_IWL<58307> A_IWL<58306> A_IWL<58305> A_IWL<58304> A_IWL<58303> A_IWL<58302> A_IWL<58301> A_IWL<58300> A_IWL<58299> A_IWL<58298> A_IWL<58297> A_IWL<58296> A_IWL<58295> A_IWL<58294> A_IWL<58293> A_IWL<58292> A_IWL<58291> A_IWL<58290> A_IWL<58289> A_IWL<58288> A_IWL<58287> A_IWL<58286> A_IWL<58285> A_IWL<58284> A_IWL<58283> A_IWL<58282> A_IWL<58281> A_IWL<58280> A_IWL<58279> A_IWL<58278> A_IWL<58277> A_IWL<58276> A_IWL<58275> A_IWL<58274> A_IWL<58273> A_IWL<58272> A_IWL<58271> A_IWL<58270> A_IWL<58269> A_IWL<58268> A_IWL<58267> A_IWL<58266> A_IWL<58265> A_IWL<58264> A_IWL<58263> A_IWL<58262> A_IWL<58261> A_IWL<58260> A_IWL<58259> A_IWL<58258> A_IWL<58257> A_IWL<58256> A_IWL<58255> A_IWL<58254> A_IWL<58253> A_IWL<58252> A_IWL<58251> A_IWL<58250> A_IWL<58249> A_IWL<58248> A_IWL<58247> A_IWL<58246> A_IWL<58245> A_IWL<58244> A_IWL<58243> A_IWL<58242> A_IWL<58241> A_IWL<58240> A_IWL<58239> A_IWL<58238> A_IWL<58237> A_IWL<58236> A_IWL<58235> A_IWL<58234> A_IWL<58233> A_IWL<58232> A_IWL<58231> A_IWL<58230> A_IWL<58229> A_IWL<58228> A_IWL<58227> A_IWL<58226> A_IWL<58225> A_IWL<58224> A_IWL<58223> A_IWL<58222> A_IWL<58221> A_IWL<58220> A_IWL<58219> A_IWL<58218> A_IWL<58217> A_IWL<58216> A_IWL<58215> A_IWL<58214> A_IWL<58213> A_IWL<58212> A_IWL<58211> A_IWL<58210> A_IWL<58209> A_IWL<58208> A_IWL<58207> A_IWL<58206> A_IWL<58205> A_IWL<58204> A_IWL<58203> A_IWL<58202> A_IWL<58201> A_IWL<58200> A_IWL<58199> A_IWL<58198> A_IWL<58197> A_IWL<58196> A_IWL<58195> A_IWL<58194> A_IWL<58193> A_IWL<58192> A_IWL<58191> A_IWL<58190> A_IWL<58189> A_IWL<58188> A_IWL<58187> A_IWL<58186> A_IWL<58185> A_IWL<58184> A_IWL<58183> A_IWL<58182> A_IWL<58181> A_IWL<58180> A_IWL<58179> A_IWL<58178> A_IWL<58177> A_IWL<58176> A_IWL<58175> A_IWL<58174> A_IWL<58173> A_IWL<58172> A_IWL<58171> A_IWL<58170> A_IWL<58169> A_IWL<58168> A_IWL<58167> A_IWL<58166> A_IWL<58165> A_IWL<58164> A_IWL<58163> A_IWL<58162> A_IWL<58161> A_IWL<58160> A_IWL<58159> A_IWL<58158> A_IWL<58157> A_IWL<58156> A_IWL<58155> A_IWL<58154> A_IWL<58153> A_IWL<58152> A_IWL<58151> A_IWL<58150> A_IWL<58149> A_IWL<58148> A_IWL<58147> A_IWL<58146> A_IWL<58145> A_IWL<58144> A_IWL<58143> A_IWL<58142> A_IWL<58141> A_IWL<58140> A_IWL<58139> A_IWL<58138> A_IWL<58137> A_IWL<58136> A_IWL<58135> A_IWL<58134> A_IWL<58133> A_IWL<58132> A_IWL<58131> A_IWL<58130> A_IWL<58129> A_IWL<58128> A_IWL<58127> A_IWL<58126> A_IWL<58125> A_IWL<58124> A_IWL<58123> A_IWL<58122> A_IWL<58121> A_IWL<58120> A_IWL<58119> A_IWL<58118> A_IWL<58117> A_IWL<58116> A_IWL<58115> A_IWL<58114> A_IWL<58113> A_IWL<58112> A_IWL<58111> A_IWL<58110> A_IWL<58109> A_IWL<58108> A_IWL<58107> A_IWL<58106> A_IWL<58105> A_IWL<58104> A_IWL<58103> A_IWL<58102> A_IWL<58101> A_IWL<58100> A_IWL<58099> A_IWL<58098> A_IWL<58097> A_IWL<58096> A_IWL<58095> A_IWL<58094> A_IWL<58093> A_IWL<58092> A_IWL<58091> A_IWL<58090> A_IWL<58089> A_IWL<58088> A_IWL<58087> A_IWL<58086> A_IWL<58085> A_IWL<58084> A_IWL<58083> A_IWL<58082> A_IWL<58081> A_IWL<58080> A_IWL<58079> A_IWL<58078> A_IWL<58077> A_IWL<58076> A_IWL<58075> A_IWL<58074> A_IWL<58073> A_IWL<58072> A_IWL<58071> A_IWL<58070> A_IWL<58069> A_IWL<58068> A_IWL<58067> A_IWL<58066> A_IWL<58065> A_IWL<58064> A_IWL<58063> A_IWL<58062> A_IWL<58061> A_IWL<58060> A_IWL<58059> A_IWL<58058> A_IWL<58057> A_IWL<58056> A_IWL<58055> A_IWL<58054> A_IWL<58053> A_IWL<58052> A_IWL<58051> A_IWL<58050> A_IWL<58049> A_IWL<58048> A_IWL<58047> A_IWL<58046> A_IWL<58045> A_IWL<58044> A_IWL<58043> A_IWL<58042> A_IWL<58041> A_IWL<58040> A_IWL<58039> A_IWL<58038> A_IWL<58037> A_IWL<58036> A_IWL<58035> A_IWL<58034> A_IWL<58033> A_IWL<58032> A_IWL<58031> A_IWL<58030> A_IWL<58029> A_IWL<58028> A_IWL<58027> A_IWL<58026> A_IWL<58025> A_IWL<58024> A_IWL<58023> A_IWL<58022> A_IWL<58021> A_IWL<58020> A_IWL<58019> A_IWL<58018> A_IWL<58017> A_IWL<58016> A_IWL<58015> A_IWL<58014> A_IWL<58013> A_IWL<58012> A_IWL<58011> A_IWL<58010> A_IWL<58009> A_IWL<58008> A_IWL<58007> A_IWL<58006> A_IWL<58005> A_IWL<58004> A_IWL<58003> A_IWL<58002> A_IWL<58001> A_IWL<58000> A_IWL<57999> A_IWL<57998> A_IWL<57997> A_IWL<57996> A_IWL<57995> A_IWL<57994> A_IWL<57993> A_IWL<57992> A_IWL<57991> A_IWL<57990> A_IWL<57989> A_IWL<57988> A_IWL<57987> A_IWL<57986> A_IWL<57985> A_IWL<57984> A_IWL<57983> A_IWL<57982> A_IWL<57981> A_IWL<57980> A_IWL<57979> A_IWL<57978> A_IWL<57977> A_IWL<57976> A_IWL<57975> A_IWL<57974> A_IWL<57973> A_IWL<57972> A_IWL<57971> A_IWL<57970> A_IWL<57969> A_IWL<57968> A_IWL<57967> A_IWL<57966> A_IWL<57965> A_IWL<57964> A_IWL<57963> A_IWL<57962> A_IWL<57961> A_IWL<57960> A_IWL<57959> A_IWL<57958> A_IWL<57957> A_IWL<57956> A_IWL<57955> A_IWL<57954> A_IWL<57953> A_IWL<57952> A_IWL<57951> A_IWL<57950> A_IWL<57949> A_IWL<57948> A_IWL<57947> A_IWL<57946> A_IWL<57945> A_IWL<57944> A_IWL<57943> A_IWL<57942> A_IWL<57941> A_IWL<57940> A_IWL<57939> A_IWL<57938> A_IWL<57937> A_IWL<57936> A_IWL<57935> A_IWL<57934> A_IWL<57933> A_IWL<57932> A_IWL<57931> A_IWL<57930> A_IWL<57929> A_IWL<57928> A_IWL<57927> A_IWL<57926> A_IWL<57925> A_IWL<57924> A_IWL<57923> A_IWL<57922> A_IWL<57921> A_IWL<57920> A_IWL<57919> A_IWL<57918> A_IWL<57917> A_IWL<57916> A_IWL<57915> A_IWL<57914> A_IWL<57913> A_IWL<57912> A_IWL<57911> A_IWL<57910> A_IWL<57909> A_IWL<57908> A_IWL<57907> A_IWL<57906> A_IWL<57905> A_IWL<57904> A_IWL<57903> A_IWL<57902> A_IWL<57901> A_IWL<57900> A_IWL<57899> A_IWL<57898> A_IWL<57897> A_IWL<57896> A_IWL<57895> A_IWL<57894> A_IWL<57893> A_IWL<57892> A_IWL<57891> A_IWL<57890> A_IWL<57889> A_IWL<57888> A_IWL<57887> A_IWL<57886> A_IWL<57885> A_IWL<57884> A_IWL<57883> A_IWL<57882> A_IWL<57881> A_IWL<57880> A_IWL<57879> A_IWL<57878> A_IWL<57877> A_IWL<57876> A_IWL<57875> A_IWL<57874> A_IWL<57873> A_IWL<57872> A_IWL<57871> A_IWL<57870> A_IWL<57869> A_IWL<57868> A_IWL<57867> A_IWL<57866> A_IWL<57865> A_IWL<57864> A_IWL<57863> A_IWL<57862> A_IWL<57861> A_IWL<57860> A_IWL<57859> A_IWL<57858> A_IWL<57857> A_IWL<57856> VDD_CORE VSS / RM_IHPSG13_8192x32_c4_1P_COLUMN_pcell_0 +XCOL<112> A_BLC<225> A_BLC<224> A_BLC_TOP<225> A_BLC_TOP<224> A_BLT<225> A_BLT<224> A_BLT_TOP<225> A_BLT_TOP<224> A_IWL<57343> A_IWL<57342> A_IWL<57341> A_IWL<57340> A_IWL<57339> A_IWL<57338> A_IWL<57337> A_IWL<57336> A_IWL<57335> A_IWL<57334> A_IWL<57333> A_IWL<57332> A_IWL<57331> A_IWL<57330> A_IWL<57329> A_IWL<57328> A_IWL<57327> A_IWL<57326> A_IWL<57325> A_IWL<57324> A_IWL<57323> A_IWL<57322> A_IWL<57321> A_IWL<57320> A_IWL<57319> A_IWL<57318> A_IWL<57317> A_IWL<57316> A_IWL<57315> A_IWL<57314> A_IWL<57313> A_IWL<57312> A_IWL<57311> A_IWL<57310> A_IWL<57309> A_IWL<57308> A_IWL<57307> A_IWL<57306> A_IWL<57305> A_IWL<57304> A_IWL<57303> A_IWL<57302> A_IWL<57301> A_IWL<57300> A_IWL<57299> A_IWL<57298> A_IWL<57297> A_IWL<57296> A_IWL<57295> A_IWL<57294> A_IWL<57293> A_IWL<57292> A_IWL<57291> A_IWL<57290> A_IWL<57289> A_IWL<57288> A_IWL<57287> A_IWL<57286> A_IWL<57285> A_IWL<57284> A_IWL<57283> A_IWL<57282> A_IWL<57281> A_IWL<57280> A_IWL<57279> A_IWL<57278> A_IWL<57277> A_IWL<57276> A_IWL<57275> A_IWL<57274> A_IWL<57273> A_IWL<57272> A_IWL<57271> A_IWL<57270> A_IWL<57269> A_IWL<57268> A_IWL<57267> A_IWL<57266> A_IWL<57265> A_IWL<57264> A_IWL<57263> A_IWL<57262> A_IWL<57261> A_IWL<57260> A_IWL<57259> A_IWL<57258> A_IWL<57257> A_IWL<57256> A_IWL<57255> A_IWL<57254> A_IWL<57253> A_IWL<57252> A_IWL<57251> A_IWL<57250> A_IWL<57249> A_IWL<57248> A_IWL<57247> A_IWL<57246> A_IWL<57245> A_IWL<57244> A_IWL<57243> A_IWL<57242> A_IWL<57241> A_IWL<57240> A_IWL<57239> A_IWL<57238> A_IWL<57237> A_IWL<57236> A_IWL<57235> A_IWL<57234> A_IWL<57233> A_IWL<57232> A_IWL<57231> A_IWL<57230> A_IWL<57229> A_IWL<57228> A_IWL<57227> A_IWL<57226> A_IWL<57225> A_IWL<57224> A_IWL<57223> A_IWL<57222> A_IWL<57221> A_IWL<57220> A_IWL<57219> A_IWL<57218> A_IWL<57217> A_IWL<57216> A_IWL<57215> A_IWL<57214> A_IWL<57213> A_IWL<57212> A_IWL<57211> A_IWL<57210> A_IWL<57209> A_IWL<57208> A_IWL<57207> A_IWL<57206> A_IWL<57205> A_IWL<57204> A_IWL<57203> A_IWL<57202> A_IWL<57201> A_IWL<57200> A_IWL<57199> A_IWL<57198> A_IWL<57197> A_IWL<57196> A_IWL<57195> A_IWL<57194> A_IWL<57193> A_IWL<57192> A_IWL<57191> A_IWL<57190> A_IWL<57189> A_IWL<57188> A_IWL<57187> A_IWL<57186> A_IWL<57185> A_IWL<57184> A_IWL<57183> A_IWL<57182> A_IWL<57181> A_IWL<57180> A_IWL<57179> A_IWL<57178> A_IWL<57177> A_IWL<57176> A_IWL<57175> A_IWL<57174> A_IWL<57173> A_IWL<57172> A_IWL<57171> A_IWL<57170> A_IWL<57169> A_IWL<57168> A_IWL<57167> A_IWL<57166> A_IWL<57165> A_IWL<57164> A_IWL<57163> A_IWL<57162> A_IWL<57161> A_IWL<57160> A_IWL<57159> A_IWL<57158> A_IWL<57157> A_IWL<57156> A_IWL<57155> A_IWL<57154> A_IWL<57153> A_IWL<57152> A_IWL<57151> A_IWL<57150> A_IWL<57149> A_IWL<57148> A_IWL<57147> A_IWL<57146> A_IWL<57145> A_IWL<57144> A_IWL<57143> A_IWL<57142> A_IWL<57141> A_IWL<57140> A_IWL<57139> A_IWL<57138> A_IWL<57137> A_IWL<57136> A_IWL<57135> A_IWL<57134> A_IWL<57133> A_IWL<57132> A_IWL<57131> A_IWL<57130> A_IWL<57129> A_IWL<57128> A_IWL<57127> A_IWL<57126> A_IWL<57125> A_IWL<57124> A_IWL<57123> A_IWL<57122> A_IWL<57121> A_IWL<57120> A_IWL<57119> A_IWL<57118> A_IWL<57117> A_IWL<57116> A_IWL<57115> A_IWL<57114> A_IWL<57113> A_IWL<57112> A_IWL<57111> A_IWL<57110> A_IWL<57109> A_IWL<57108> A_IWL<57107> A_IWL<57106> A_IWL<57105> A_IWL<57104> A_IWL<57103> A_IWL<57102> A_IWL<57101> A_IWL<57100> A_IWL<57099> A_IWL<57098> A_IWL<57097> A_IWL<57096> A_IWL<57095> A_IWL<57094> A_IWL<57093> A_IWL<57092> A_IWL<57091> A_IWL<57090> A_IWL<57089> A_IWL<57088> A_IWL<57087> A_IWL<57086> A_IWL<57085> A_IWL<57084> A_IWL<57083> A_IWL<57082> A_IWL<57081> A_IWL<57080> A_IWL<57079> A_IWL<57078> A_IWL<57077> A_IWL<57076> A_IWL<57075> A_IWL<57074> A_IWL<57073> A_IWL<57072> A_IWL<57071> A_IWL<57070> A_IWL<57069> A_IWL<57068> A_IWL<57067> A_IWL<57066> A_IWL<57065> A_IWL<57064> A_IWL<57063> A_IWL<57062> A_IWL<57061> A_IWL<57060> A_IWL<57059> A_IWL<57058> A_IWL<57057> A_IWL<57056> A_IWL<57055> A_IWL<57054> A_IWL<57053> A_IWL<57052> A_IWL<57051> A_IWL<57050> A_IWL<57049> A_IWL<57048> A_IWL<57047> A_IWL<57046> A_IWL<57045> A_IWL<57044> A_IWL<57043> A_IWL<57042> A_IWL<57041> A_IWL<57040> A_IWL<57039> A_IWL<57038> A_IWL<57037> A_IWL<57036> A_IWL<57035> A_IWL<57034> A_IWL<57033> A_IWL<57032> A_IWL<57031> A_IWL<57030> A_IWL<57029> A_IWL<57028> A_IWL<57027> A_IWL<57026> A_IWL<57025> A_IWL<57024> A_IWL<57023> A_IWL<57022> A_IWL<57021> A_IWL<57020> A_IWL<57019> A_IWL<57018> A_IWL<57017> A_IWL<57016> A_IWL<57015> A_IWL<57014> A_IWL<57013> A_IWL<57012> A_IWL<57011> A_IWL<57010> A_IWL<57009> A_IWL<57008> A_IWL<57007> A_IWL<57006> A_IWL<57005> A_IWL<57004> A_IWL<57003> A_IWL<57002> A_IWL<57001> A_IWL<57000> A_IWL<56999> A_IWL<56998> A_IWL<56997> A_IWL<56996> A_IWL<56995> A_IWL<56994> A_IWL<56993> A_IWL<56992> A_IWL<56991> A_IWL<56990> A_IWL<56989> A_IWL<56988> A_IWL<56987> A_IWL<56986> A_IWL<56985> A_IWL<56984> A_IWL<56983> A_IWL<56982> A_IWL<56981> A_IWL<56980> A_IWL<56979> A_IWL<56978> A_IWL<56977> A_IWL<56976> A_IWL<56975> A_IWL<56974> A_IWL<56973> A_IWL<56972> A_IWL<56971> A_IWL<56970> A_IWL<56969> A_IWL<56968> A_IWL<56967> A_IWL<56966> A_IWL<56965> A_IWL<56964> A_IWL<56963> A_IWL<56962> A_IWL<56961> A_IWL<56960> A_IWL<56959> A_IWL<56958> A_IWL<56957> A_IWL<56956> A_IWL<56955> A_IWL<56954> A_IWL<56953> A_IWL<56952> A_IWL<56951> A_IWL<56950> A_IWL<56949> A_IWL<56948> A_IWL<56947> A_IWL<56946> A_IWL<56945> A_IWL<56944> A_IWL<56943> A_IWL<56942> A_IWL<56941> A_IWL<56940> A_IWL<56939> A_IWL<56938> A_IWL<56937> A_IWL<56936> A_IWL<56935> A_IWL<56934> A_IWL<56933> A_IWL<56932> A_IWL<56931> A_IWL<56930> A_IWL<56929> A_IWL<56928> A_IWL<56927> A_IWL<56926> A_IWL<56925> A_IWL<56924> A_IWL<56923> A_IWL<56922> A_IWL<56921> A_IWL<56920> A_IWL<56919> A_IWL<56918> A_IWL<56917> A_IWL<56916> A_IWL<56915> A_IWL<56914> A_IWL<56913> A_IWL<56912> A_IWL<56911> A_IWL<56910> A_IWL<56909> A_IWL<56908> A_IWL<56907> A_IWL<56906> A_IWL<56905> A_IWL<56904> A_IWL<56903> A_IWL<56902> A_IWL<56901> A_IWL<56900> A_IWL<56899> A_IWL<56898> A_IWL<56897> A_IWL<56896> A_IWL<56895> A_IWL<56894> A_IWL<56893> A_IWL<56892> A_IWL<56891> A_IWL<56890> A_IWL<56889> A_IWL<56888> A_IWL<56887> A_IWL<56886> A_IWL<56885> A_IWL<56884> A_IWL<56883> A_IWL<56882> A_IWL<56881> A_IWL<56880> A_IWL<56879> A_IWL<56878> A_IWL<56877> A_IWL<56876> A_IWL<56875> A_IWL<56874> A_IWL<56873> A_IWL<56872> A_IWL<56871> A_IWL<56870> A_IWL<56869> A_IWL<56868> A_IWL<56867> A_IWL<56866> A_IWL<56865> A_IWL<56864> A_IWL<56863> A_IWL<56862> A_IWL<56861> A_IWL<56860> A_IWL<56859> A_IWL<56858> A_IWL<56857> A_IWL<56856> A_IWL<56855> A_IWL<56854> A_IWL<56853> A_IWL<56852> A_IWL<56851> A_IWL<56850> A_IWL<56849> A_IWL<56848> A_IWL<56847> A_IWL<56846> A_IWL<56845> A_IWL<56844> A_IWL<56843> A_IWL<56842> A_IWL<56841> A_IWL<56840> A_IWL<56839> A_IWL<56838> A_IWL<56837> A_IWL<56836> A_IWL<56835> A_IWL<56834> A_IWL<56833> A_IWL<56832> A_IWL<57855> A_IWL<57854> A_IWL<57853> A_IWL<57852> A_IWL<57851> A_IWL<57850> A_IWL<57849> A_IWL<57848> A_IWL<57847> A_IWL<57846> A_IWL<57845> A_IWL<57844> A_IWL<57843> A_IWL<57842> A_IWL<57841> A_IWL<57840> A_IWL<57839> A_IWL<57838> A_IWL<57837> A_IWL<57836> A_IWL<57835> A_IWL<57834> A_IWL<57833> A_IWL<57832> A_IWL<57831> A_IWL<57830> A_IWL<57829> A_IWL<57828> A_IWL<57827> A_IWL<57826> A_IWL<57825> A_IWL<57824> A_IWL<57823> A_IWL<57822> A_IWL<57821> A_IWL<57820> A_IWL<57819> A_IWL<57818> A_IWL<57817> A_IWL<57816> A_IWL<57815> A_IWL<57814> A_IWL<57813> A_IWL<57812> A_IWL<57811> A_IWL<57810> A_IWL<57809> A_IWL<57808> A_IWL<57807> A_IWL<57806> A_IWL<57805> A_IWL<57804> A_IWL<57803> A_IWL<57802> A_IWL<57801> A_IWL<57800> A_IWL<57799> A_IWL<57798> A_IWL<57797> A_IWL<57796> A_IWL<57795> A_IWL<57794> A_IWL<57793> A_IWL<57792> A_IWL<57791> A_IWL<57790> A_IWL<57789> A_IWL<57788> A_IWL<57787> A_IWL<57786> A_IWL<57785> A_IWL<57784> A_IWL<57783> A_IWL<57782> A_IWL<57781> A_IWL<57780> A_IWL<57779> A_IWL<57778> A_IWL<57777> A_IWL<57776> A_IWL<57775> A_IWL<57774> A_IWL<57773> A_IWL<57772> A_IWL<57771> A_IWL<57770> A_IWL<57769> A_IWL<57768> A_IWL<57767> A_IWL<57766> A_IWL<57765> A_IWL<57764> A_IWL<57763> A_IWL<57762> A_IWL<57761> A_IWL<57760> A_IWL<57759> A_IWL<57758> A_IWL<57757> A_IWL<57756> A_IWL<57755> A_IWL<57754> A_IWL<57753> A_IWL<57752> A_IWL<57751> A_IWL<57750> A_IWL<57749> A_IWL<57748> A_IWL<57747> A_IWL<57746> A_IWL<57745> A_IWL<57744> A_IWL<57743> A_IWL<57742> A_IWL<57741> A_IWL<57740> A_IWL<57739> A_IWL<57738> A_IWL<57737> A_IWL<57736> A_IWL<57735> A_IWL<57734> A_IWL<57733> A_IWL<57732> A_IWL<57731> A_IWL<57730> A_IWL<57729> A_IWL<57728> A_IWL<57727> A_IWL<57726> A_IWL<57725> A_IWL<57724> A_IWL<57723> A_IWL<57722> A_IWL<57721> A_IWL<57720> A_IWL<57719> A_IWL<57718> A_IWL<57717> A_IWL<57716> A_IWL<57715> A_IWL<57714> A_IWL<57713> A_IWL<57712> A_IWL<57711> A_IWL<57710> A_IWL<57709> A_IWL<57708> A_IWL<57707> A_IWL<57706> A_IWL<57705> A_IWL<57704> A_IWL<57703> A_IWL<57702> A_IWL<57701> A_IWL<57700> A_IWL<57699> A_IWL<57698> A_IWL<57697> A_IWL<57696> A_IWL<57695> A_IWL<57694> A_IWL<57693> A_IWL<57692> A_IWL<57691> A_IWL<57690> A_IWL<57689> A_IWL<57688> A_IWL<57687> A_IWL<57686> A_IWL<57685> A_IWL<57684> A_IWL<57683> A_IWL<57682> A_IWL<57681> A_IWL<57680> A_IWL<57679> A_IWL<57678> A_IWL<57677> A_IWL<57676> A_IWL<57675> A_IWL<57674> A_IWL<57673> A_IWL<57672> A_IWL<57671> A_IWL<57670> A_IWL<57669> A_IWL<57668> A_IWL<57667> A_IWL<57666> A_IWL<57665> A_IWL<57664> A_IWL<57663> A_IWL<57662> A_IWL<57661> A_IWL<57660> A_IWL<57659> A_IWL<57658> A_IWL<57657> A_IWL<57656> A_IWL<57655> A_IWL<57654> A_IWL<57653> A_IWL<57652> A_IWL<57651> A_IWL<57650> A_IWL<57649> A_IWL<57648> A_IWL<57647> A_IWL<57646> A_IWL<57645> A_IWL<57644> A_IWL<57643> A_IWL<57642> A_IWL<57641> A_IWL<57640> A_IWL<57639> A_IWL<57638> A_IWL<57637> A_IWL<57636> A_IWL<57635> A_IWL<57634> A_IWL<57633> A_IWL<57632> A_IWL<57631> A_IWL<57630> A_IWL<57629> A_IWL<57628> A_IWL<57627> A_IWL<57626> A_IWL<57625> A_IWL<57624> A_IWL<57623> A_IWL<57622> A_IWL<57621> A_IWL<57620> A_IWL<57619> A_IWL<57618> A_IWL<57617> A_IWL<57616> A_IWL<57615> A_IWL<57614> A_IWL<57613> A_IWL<57612> A_IWL<57611> A_IWL<57610> A_IWL<57609> A_IWL<57608> A_IWL<57607> A_IWL<57606> A_IWL<57605> A_IWL<57604> A_IWL<57603> A_IWL<57602> A_IWL<57601> A_IWL<57600> A_IWL<57599> A_IWL<57598> A_IWL<57597> A_IWL<57596> A_IWL<57595> A_IWL<57594> A_IWL<57593> A_IWL<57592> A_IWL<57591> A_IWL<57590> A_IWL<57589> A_IWL<57588> A_IWL<57587> A_IWL<57586> A_IWL<57585> A_IWL<57584> A_IWL<57583> A_IWL<57582> A_IWL<57581> A_IWL<57580> A_IWL<57579> A_IWL<57578> A_IWL<57577> A_IWL<57576> A_IWL<57575> A_IWL<57574> A_IWL<57573> A_IWL<57572> A_IWL<57571> A_IWL<57570> A_IWL<57569> A_IWL<57568> A_IWL<57567> A_IWL<57566> A_IWL<57565> A_IWL<57564> A_IWL<57563> A_IWL<57562> A_IWL<57561> A_IWL<57560> A_IWL<57559> A_IWL<57558> A_IWL<57557> A_IWL<57556> A_IWL<57555> A_IWL<57554> A_IWL<57553> A_IWL<57552> A_IWL<57551> A_IWL<57550> A_IWL<57549> A_IWL<57548> A_IWL<57547> A_IWL<57546> A_IWL<57545> A_IWL<57544> A_IWL<57543> A_IWL<57542> A_IWL<57541> A_IWL<57540> A_IWL<57539> A_IWL<57538> A_IWL<57537> A_IWL<57536> A_IWL<57535> A_IWL<57534> A_IWL<57533> A_IWL<57532> A_IWL<57531> A_IWL<57530> A_IWL<57529> A_IWL<57528> A_IWL<57527> A_IWL<57526> A_IWL<57525> A_IWL<57524> A_IWL<57523> A_IWL<57522> A_IWL<57521> A_IWL<57520> A_IWL<57519> A_IWL<57518> A_IWL<57517> A_IWL<57516> A_IWL<57515> A_IWL<57514> A_IWL<57513> A_IWL<57512> A_IWL<57511> A_IWL<57510> A_IWL<57509> A_IWL<57508> A_IWL<57507> A_IWL<57506> A_IWL<57505> A_IWL<57504> A_IWL<57503> A_IWL<57502> A_IWL<57501> A_IWL<57500> A_IWL<57499> A_IWL<57498> A_IWL<57497> A_IWL<57496> A_IWL<57495> A_IWL<57494> A_IWL<57493> A_IWL<57492> A_IWL<57491> A_IWL<57490> A_IWL<57489> A_IWL<57488> A_IWL<57487> A_IWL<57486> A_IWL<57485> A_IWL<57484> A_IWL<57483> A_IWL<57482> A_IWL<57481> A_IWL<57480> A_IWL<57479> A_IWL<57478> A_IWL<57477> A_IWL<57476> A_IWL<57475> A_IWL<57474> A_IWL<57473> A_IWL<57472> A_IWL<57471> A_IWL<57470> A_IWL<57469> A_IWL<57468> A_IWL<57467> A_IWL<57466> A_IWL<57465> A_IWL<57464> A_IWL<57463> A_IWL<57462> A_IWL<57461> A_IWL<57460> A_IWL<57459> A_IWL<57458> A_IWL<57457> A_IWL<57456> A_IWL<57455> A_IWL<57454> A_IWL<57453> A_IWL<57452> A_IWL<57451> A_IWL<57450> A_IWL<57449> A_IWL<57448> A_IWL<57447> A_IWL<57446> A_IWL<57445> A_IWL<57444> A_IWL<57443> A_IWL<57442> A_IWL<57441> A_IWL<57440> A_IWL<57439> A_IWL<57438> A_IWL<57437> A_IWL<57436> A_IWL<57435> A_IWL<57434> A_IWL<57433> A_IWL<57432> A_IWL<57431> A_IWL<57430> A_IWL<57429> A_IWL<57428> A_IWL<57427> A_IWL<57426> A_IWL<57425> A_IWL<57424> A_IWL<57423> A_IWL<57422> A_IWL<57421> A_IWL<57420> A_IWL<57419> A_IWL<57418> A_IWL<57417> A_IWL<57416> A_IWL<57415> A_IWL<57414> A_IWL<57413> A_IWL<57412> A_IWL<57411> A_IWL<57410> A_IWL<57409> A_IWL<57408> A_IWL<57407> A_IWL<57406> A_IWL<57405> A_IWL<57404> A_IWL<57403> A_IWL<57402> A_IWL<57401> A_IWL<57400> A_IWL<57399> A_IWL<57398> A_IWL<57397> A_IWL<57396> A_IWL<57395> A_IWL<57394> A_IWL<57393> A_IWL<57392> A_IWL<57391> A_IWL<57390> A_IWL<57389> A_IWL<57388> A_IWL<57387> A_IWL<57386> A_IWL<57385> A_IWL<57384> A_IWL<57383> A_IWL<57382> A_IWL<57381> A_IWL<57380> A_IWL<57379> A_IWL<57378> A_IWL<57377> A_IWL<57376> A_IWL<57375> A_IWL<57374> A_IWL<57373> A_IWL<57372> A_IWL<57371> A_IWL<57370> A_IWL<57369> A_IWL<57368> A_IWL<57367> A_IWL<57366> A_IWL<57365> A_IWL<57364> A_IWL<57363> A_IWL<57362> A_IWL<57361> A_IWL<57360> A_IWL<57359> A_IWL<57358> A_IWL<57357> A_IWL<57356> A_IWL<57355> A_IWL<57354> A_IWL<57353> A_IWL<57352> A_IWL<57351> A_IWL<57350> A_IWL<57349> A_IWL<57348> A_IWL<57347> A_IWL<57346> A_IWL<57345> A_IWL<57344> VDD_CORE VSS / RM_IHPSG13_8192x32_c4_1P_COLUMN_pcell_0 +XCOL<111> A_BLC<223> A_BLC<222> A_BLC_TOP<223> A_BLC_TOP<222> A_BLT<223> A_BLT<222> A_BLT_TOP<223> A_BLT_TOP<222> A_IWL<56831> A_IWL<56830> A_IWL<56829> A_IWL<56828> A_IWL<56827> A_IWL<56826> A_IWL<56825> A_IWL<56824> A_IWL<56823> A_IWL<56822> A_IWL<56821> A_IWL<56820> A_IWL<56819> A_IWL<56818> A_IWL<56817> A_IWL<56816> A_IWL<56815> A_IWL<56814> A_IWL<56813> A_IWL<56812> A_IWL<56811> A_IWL<56810> A_IWL<56809> A_IWL<56808> A_IWL<56807> A_IWL<56806> A_IWL<56805> A_IWL<56804> A_IWL<56803> A_IWL<56802> A_IWL<56801> A_IWL<56800> A_IWL<56799> A_IWL<56798> A_IWL<56797> A_IWL<56796> A_IWL<56795> A_IWL<56794> A_IWL<56793> A_IWL<56792> A_IWL<56791> A_IWL<56790> A_IWL<56789> A_IWL<56788> A_IWL<56787> A_IWL<56786> A_IWL<56785> A_IWL<56784> A_IWL<56783> A_IWL<56782> A_IWL<56781> A_IWL<56780> A_IWL<56779> A_IWL<56778> A_IWL<56777> A_IWL<56776> A_IWL<56775> A_IWL<56774> A_IWL<56773> A_IWL<56772> A_IWL<56771> A_IWL<56770> A_IWL<56769> A_IWL<56768> A_IWL<56767> A_IWL<56766> A_IWL<56765> A_IWL<56764> A_IWL<56763> A_IWL<56762> A_IWL<56761> A_IWL<56760> A_IWL<56759> A_IWL<56758> A_IWL<56757> A_IWL<56756> A_IWL<56755> A_IWL<56754> A_IWL<56753> A_IWL<56752> A_IWL<56751> A_IWL<56750> A_IWL<56749> A_IWL<56748> A_IWL<56747> A_IWL<56746> A_IWL<56745> A_IWL<56744> A_IWL<56743> A_IWL<56742> A_IWL<56741> A_IWL<56740> A_IWL<56739> A_IWL<56738> A_IWL<56737> A_IWL<56736> A_IWL<56735> A_IWL<56734> A_IWL<56733> A_IWL<56732> A_IWL<56731> A_IWL<56730> A_IWL<56729> A_IWL<56728> A_IWL<56727> A_IWL<56726> A_IWL<56725> A_IWL<56724> A_IWL<56723> A_IWL<56722> A_IWL<56721> A_IWL<56720> A_IWL<56719> A_IWL<56718> A_IWL<56717> A_IWL<56716> A_IWL<56715> A_IWL<56714> A_IWL<56713> A_IWL<56712> A_IWL<56711> A_IWL<56710> A_IWL<56709> A_IWL<56708> A_IWL<56707> A_IWL<56706> A_IWL<56705> A_IWL<56704> A_IWL<56703> A_IWL<56702> A_IWL<56701> A_IWL<56700> A_IWL<56699> A_IWL<56698> A_IWL<56697> A_IWL<56696> A_IWL<56695> A_IWL<56694> A_IWL<56693> A_IWL<56692> A_IWL<56691> A_IWL<56690> A_IWL<56689> A_IWL<56688> A_IWL<56687> A_IWL<56686> A_IWL<56685> A_IWL<56684> A_IWL<56683> A_IWL<56682> A_IWL<56681> A_IWL<56680> A_IWL<56679> A_IWL<56678> A_IWL<56677> A_IWL<56676> A_IWL<56675> A_IWL<56674> A_IWL<56673> A_IWL<56672> A_IWL<56671> A_IWL<56670> A_IWL<56669> A_IWL<56668> A_IWL<56667> A_IWL<56666> A_IWL<56665> A_IWL<56664> A_IWL<56663> A_IWL<56662> A_IWL<56661> A_IWL<56660> A_IWL<56659> A_IWL<56658> A_IWL<56657> A_IWL<56656> A_IWL<56655> A_IWL<56654> A_IWL<56653> A_IWL<56652> A_IWL<56651> A_IWL<56650> A_IWL<56649> A_IWL<56648> A_IWL<56647> A_IWL<56646> A_IWL<56645> A_IWL<56644> A_IWL<56643> A_IWL<56642> A_IWL<56641> A_IWL<56640> A_IWL<56639> A_IWL<56638> A_IWL<56637> A_IWL<56636> A_IWL<56635> A_IWL<56634> A_IWL<56633> A_IWL<56632> A_IWL<56631> A_IWL<56630> A_IWL<56629> A_IWL<56628> A_IWL<56627> A_IWL<56626> A_IWL<56625> A_IWL<56624> A_IWL<56623> A_IWL<56622> A_IWL<56621> A_IWL<56620> A_IWL<56619> A_IWL<56618> A_IWL<56617> A_IWL<56616> A_IWL<56615> A_IWL<56614> A_IWL<56613> A_IWL<56612> A_IWL<56611> A_IWL<56610> A_IWL<56609> A_IWL<56608> A_IWL<56607> A_IWL<56606> A_IWL<56605> A_IWL<56604> A_IWL<56603> A_IWL<56602> A_IWL<56601> A_IWL<56600> A_IWL<56599> A_IWL<56598> A_IWL<56597> A_IWL<56596> A_IWL<56595> A_IWL<56594> A_IWL<56593> A_IWL<56592> A_IWL<56591> A_IWL<56590> A_IWL<56589> A_IWL<56588> A_IWL<56587> A_IWL<56586> A_IWL<56585> A_IWL<56584> A_IWL<56583> A_IWL<56582> A_IWL<56581> A_IWL<56580> A_IWL<56579> A_IWL<56578> A_IWL<56577> A_IWL<56576> A_IWL<56575> A_IWL<56574> A_IWL<56573> A_IWL<56572> A_IWL<56571> A_IWL<56570> A_IWL<56569> A_IWL<56568> A_IWL<56567> A_IWL<56566> A_IWL<56565> A_IWL<56564> A_IWL<56563> A_IWL<56562> A_IWL<56561> A_IWL<56560> A_IWL<56559> A_IWL<56558> A_IWL<56557> A_IWL<56556> A_IWL<56555> A_IWL<56554> A_IWL<56553> A_IWL<56552> A_IWL<56551> A_IWL<56550> A_IWL<56549> A_IWL<56548> A_IWL<56547> A_IWL<56546> A_IWL<56545> A_IWL<56544> A_IWL<56543> A_IWL<56542> A_IWL<56541> A_IWL<56540> A_IWL<56539> A_IWL<56538> A_IWL<56537> A_IWL<56536> A_IWL<56535> A_IWL<56534> A_IWL<56533> A_IWL<56532> A_IWL<56531> A_IWL<56530> A_IWL<56529> A_IWL<56528> A_IWL<56527> A_IWL<56526> A_IWL<56525> A_IWL<56524> A_IWL<56523> A_IWL<56522> A_IWL<56521> A_IWL<56520> A_IWL<56519> A_IWL<56518> A_IWL<56517> A_IWL<56516> A_IWL<56515> A_IWL<56514> A_IWL<56513> A_IWL<56512> A_IWL<56511> A_IWL<56510> A_IWL<56509> A_IWL<56508> A_IWL<56507> A_IWL<56506> A_IWL<56505> A_IWL<56504> A_IWL<56503> A_IWL<56502> A_IWL<56501> A_IWL<56500> A_IWL<56499> A_IWL<56498> A_IWL<56497> A_IWL<56496> A_IWL<56495> A_IWL<56494> A_IWL<56493> A_IWL<56492> A_IWL<56491> A_IWL<56490> A_IWL<56489> A_IWL<56488> A_IWL<56487> A_IWL<56486> A_IWL<56485> A_IWL<56484> A_IWL<56483> A_IWL<56482> A_IWL<56481> A_IWL<56480> A_IWL<56479> A_IWL<56478> A_IWL<56477> A_IWL<56476> A_IWL<56475> A_IWL<56474> A_IWL<56473> A_IWL<56472> A_IWL<56471> A_IWL<56470> A_IWL<56469> A_IWL<56468> A_IWL<56467> A_IWL<56466> A_IWL<56465> A_IWL<56464> A_IWL<56463> A_IWL<56462> A_IWL<56461> A_IWL<56460> A_IWL<56459> A_IWL<56458> A_IWL<56457> A_IWL<56456> A_IWL<56455> A_IWL<56454> A_IWL<56453> A_IWL<56452> A_IWL<56451> A_IWL<56450> A_IWL<56449> A_IWL<56448> A_IWL<56447> A_IWL<56446> A_IWL<56445> A_IWL<56444> A_IWL<56443> A_IWL<56442> A_IWL<56441> A_IWL<56440> A_IWL<56439> A_IWL<56438> A_IWL<56437> A_IWL<56436> A_IWL<56435> A_IWL<56434> A_IWL<56433> A_IWL<56432> A_IWL<56431> A_IWL<56430> A_IWL<56429> A_IWL<56428> A_IWL<56427> A_IWL<56426> A_IWL<56425> A_IWL<56424> A_IWL<56423> A_IWL<56422> A_IWL<56421> A_IWL<56420> A_IWL<56419> A_IWL<56418> A_IWL<56417> A_IWL<56416> A_IWL<56415> A_IWL<56414> A_IWL<56413> A_IWL<56412> A_IWL<56411> A_IWL<56410> A_IWL<56409> A_IWL<56408> A_IWL<56407> A_IWL<56406> A_IWL<56405> A_IWL<56404> A_IWL<56403> A_IWL<56402> A_IWL<56401> A_IWL<56400> A_IWL<56399> A_IWL<56398> A_IWL<56397> A_IWL<56396> A_IWL<56395> A_IWL<56394> A_IWL<56393> A_IWL<56392> A_IWL<56391> A_IWL<56390> A_IWL<56389> A_IWL<56388> A_IWL<56387> A_IWL<56386> A_IWL<56385> A_IWL<56384> A_IWL<56383> A_IWL<56382> A_IWL<56381> A_IWL<56380> A_IWL<56379> A_IWL<56378> A_IWL<56377> A_IWL<56376> A_IWL<56375> A_IWL<56374> A_IWL<56373> A_IWL<56372> A_IWL<56371> A_IWL<56370> A_IWL<56369> A_IWL<56368> A_IWL<56367> A_IWL<56366> A_IWL<56365> A_IWL<56364> A_IWL<56363> A_IWL<56362> A_IWL<56361> A_IWL<56360> A_IWL<56359> A_IWL<56358> A_IWL<56357> A_IWL<56356> A_IWL<56355> A_IWL<56354> A_IWL<56353> A_IWL<56352> A_IWL<56351> A_IWL<56350> A_IWL<56349> A_IWL<56348> A_IWL<56347> A_IWL<56346> A_IWL<56345> A_IWL<56344> A_IWL<56343> A_IWL<56342> A_IWL<56341> A_IWL<56340> A_IWL<56339> A_IWL<56338> A_IWL<56337> A_IWL<56336> A_IWL<56335> A_IWL<56334> A_IWL<56333> A_IWL<56332> A_IWL<56331> A_IWL<56330> A_IWL<56329> A_IWL<56328> A_IWL<56327> A_IWL<56326> A_IWL<56325> A_IWL<56324> A_IWL<56323> A_IWL<56322> A_IWL<56321> A_IWL<56320> A_IWL<57343> A_IWL<57342> A_IWL<57341> A_IWL<57340> A_IWL<57339> A_IWL<57338> A_IWL<57337> A_IWL<57336> A_IWL<57335> A_IWL<57334> A_IWL<57333> A_IWL<57332> A_IWL<57331> A_IWL<57330> A_IWL<57329> A_IWL<57328> A_IWL<57327> A_IWL<57326> A_IWL<57325> A_IWL<57324> A_IWL<57323> A_IWL<57322> A_IWL<57321> A_IWL<57320> A_IWL<57319> A_IWL<57318> A_IWL<57317> A_IWL<57316> A_IWL<57315> A_IWL<57314> A_IWL<57313> A_IWL<57312> A_IWL<57311> A_IWL<57310> A_IWL<57309> A_IWL<57308> A_IWL<57307> A_IWL<57306> A_IWL<57305> A_IWL<57304> A_IWL<57303> A_IWL<57302> A_IWL<57301> A_IWL<57300> A_IWL<57299> A_IWL<57298> A_IWL<57297> A_IWL<57296> A_IWL<57295> A_IWL<57294> A_IWL<57293> A_IWL<57292> A_IWL<57291> A_IWL<57290> A_IWL<57289> A_IWL<57288> A_IWL<57287> A_IWL<57286> A_IWL<57285> A_IWL<57284> A_IWL<57283> A_IWL<57282> A_IWL<57281> A_IWL<57280> A_IWL<57279> A_IWL<57278> A_IWL<57277> A_IWL<57276> A_IWL<57275> A_IWL<57274> A_IWL<57273> A_IWL<57272> A_IWL<57271> A_IWL<57270> A_IWL<57269> A_IWL<57268> A_IWL<57267> A_IWL<57266> A_IWL<57265> A_IWL<57264> A_IWL<57263> A_IWL<57262> A_IWL<57261> A_IWL<57260> A_IWL<57259> A_IWL<57258> A_IWL<57257> A_IWL<57256> A_IWL<57255> A_IWL<57254> A_IWL<57253> A_IWL<57252> A_IWL<57251> A_IWL<57250> A_IWL<57249> A_IWL<57248> A_IWL<57247> A_IWL<57246> A_IWL<57245> A_IWL<57244> A_IWL<57243> A_IWL<57242> A_IWL<57241> A_IWL<57240> A_IWL<57239> A_IWL<57238> A_IWL<57237> A_IWL<57236> A_IWL<57235> A_IWL<57234> A_IWL<57233> A_IWL<57232> A_IWL<57231> A_IWL<57230> A_IWL<57229> A_IWL<57228> A_IWL<57227> A_IWL<57226> A_IWL<57225> A_IWL<57224> A_IWL<57223> A_IWL<57222> A_IWL<57221> A_IWL<57220> A_IWL<57219> A_IWL<57218> A_IWL<57217> A_IWL<57216> A_IWL<57215> A_IWL<57214> A_IWL<57213> A_IWL<57212> A_IWL<57211> A_IWL<57210> A_IWL<57209> A_IWL<57208> A_IWL<57207> A_IWL<57206> A_IWL<57205> A_IWL<57204> A_IWL<57203> A_IWL<57202> A_IWL<57201> A_IWL<57200> A_IWL<57199> A_IWL<57198> A_IWL<57197> A_IWL<57196> A_IWL<57195> A_IWL<57194> A_IWL<57193> A_IWL<57192> A_IWL<57191> A_IWL<57190> A_IWL<57189> A_IWL<57188> A_IWL<57187> A_IWL<57186> A_IWL<57185> A_IWL<57184> A_IWL<57183> A_IWL<57182> A_IWL<57181> A_IWL<57180> A_IWL<57179> A_IWL<57178> A_IWL<57177> A_IWL<57176> A_IWL<57175> A_IWL<57174> A_IWL<57173> A_IWL<57172> A_IWL<57171> A_IWL<57170> A_IWL<57169> A_IWL<57168> A_IWL<57167> A_IWL<57166> A_IWL<57165> A_IWL<57164> A_IWL<57163> A_IWL<57162> A_IWL<57161> A_IWL<57160> A_IWL<57159> A_IWL<57158> A_IWL<57157> A_IWL<57156> A_IWL<57155> A_IWL<57154> A_IWL<57153> A_IWL<57152> A_IWL<57151> A_IWL<57150> A_IWL<57149> A_IWL<57148> A_IWL<57147> A_IWL<57146> A_IWL<57145> A_IWL<57144> A_IWL<57143> A_IWL<57142> A_IWL<57141> A_IWL<57140> A_IWL<57139> A_IWL<57138> A_IWL<57137> A_IWL<57136> A_IWL<57135> A_IWL<57134> A_IWL<57133> A_IWL<57132> A_IWL<57131> A_IWL<57130> A_IWL<57129> A_IWL<57128> A_IWL<57127> A_IWL<57126> A_IWL<57125> A_IWL<57124> A_IWL<57123> A_IWL<57122> A_IWL<57121> A_IWL<57120> A_IWL<57119> A_IWL<57118> A_IWL<57117> A_IWL<57116> A_IWL<57115> A_IWL<57114> A_IWL<57113> A_IWL<57112> A_IWL<57111> A_IWL<57110> A_IWL<57109> A_IWL<57108> A_IWL<57107> A_IWL<57106> A_IWL<57105> A_IWL<57104> A_IWL<57103> A_IWL<57102> A_IWL<57101> A_IWL<57100> A_IWL<57099> A_IWL<57098> A_IWL<57097> A_IWL<57096> A_IWL<57095> A_IWL<57094> A_IWL<57093> A_IWL<57092> A_IWL<57091> A_IWL<57090> A_IWL<57089> A_IWL<57088> A_IWL<57087> A_IWL<57086> A_IWL<57085> A_IWL<57084> A_IWL<57083> A_IWL<57082> A_IWL<57081> A_IWL<57080> A_IWL<57079> A_IWL<57078> A_IWL<57077> A_IWL<57076> A_IWL<57075> A_IWL<57074> A_IWL<57073> A_IWL<57072> A_IWL<57071> A_IWL<57070> A_IWL<57069> A_IWL<57068> A_IWL<57067> A_IWL<57066> A_IWL<57065> A_IWL<57064> A_IWL<57063> A_IWL<57062> A_IWL<57061> A_IWL<57060> A_IWL<57059> A_IWL<57058> A_IWL<57057> A_IWL<57056> A_IWL<57055> A_IWL<57054> A_IWL<57053> A_IWL<57052> A_IWL<57051> A_IWL<57050> A_IWL<57049> A_IWL<57048> A_IWL<57047> A_IWL<57046> A_IWL<57045> A_IWL<57044> A_IWL<57043> A_IWL<57042> A_IWL<57041> A_IWL<57040> A_IWL<57039> A_IWL<57038> A_IWL<57037> A_IWL<57036> A_IWL<57035> A_IWL<57034> A_IWL<57033> A_IWL<57032> A_IWL<57031> A_IWL<57030> A_IWL<57029> A_IWL<57028> A_IWL<57027> A_IWL<57026> A_IWL<57025> A_IWL<57024> A_IWL<57023> A_IWL<57022> A_IWL<57021> A_IWL<57020> A_IWL<57019> A_IWL<57018> A_IWL<57017> A_IWL<57016> A_IWL<57015> A_IWL<57014> A_IWL<57013> A_IWL<57012> A_IWL<57011> A_IWL<57010> A_IWL<57009> A_IWL<57008> A_IWL<57007> A_IWL<57006> A_IWL<57005> A_IWL<57004> A_IWL<57003> A_IWL<57002> A_IWL<57001> A_IWL<57000> A_IWL<56999> A_IWL<56998> A_IWL<56997> A_IWL<56996> A_IWL<56995> A_IWL<56994> A_IWL<56993> A_IWL<56992> A_IWL<56991> A_IWL<56990> A_IWL<56989> A_IWL<56988> A_IWL<56987> A_IWL<56986> A_IWL<56985> A_IWL<56984> A_IWL<56983> A_IWL<56982> A_IWL<56981> A_IWL<56980> A_IWL<56979> A_IWL<56978> A_IWL<56977> A_IWL<56976> A_IWL<56975> A_IWL<56974> A_IWL<56973> A_IWL<56972> A_IWL<56971> A_IWL<56970> A_IWL<56969> A_IWL<56968> A_IWL<56967> A_IWL<56966> A_IWL<56965> A_IWL<56964> A_IWL<56963> A_IWL<56962> A_IWL<56961> A_IWL<56960> A_IWL<56959> A_IWL<56958> A_IWL<56957> A_IWL<56956> A_IWL<56955> A_IWL<56954> A_IWL<56953> A_IWL<56952> A_IWL<56951> A_IWL<56950> A_IWL<56949> A_IWL<56948> A_IWL<56947> A_IWL<56946> A_IWL<56945> A_IWL<56944> A_IWL<56943> A_IWL<56942> A_IWL<56941> A_IWL<56940> A_IWL<56939> A_IWL<56938> A_IWL<56937> A_IWL<56936> A_IWL<56935> A_IWL<56934> A_IWL<56933> A_IWL<56932> A_IWL<56931> A_IWL<56930> A_IWL<56929> A_IWL<56928> A_IWL<56927> A_IWL<56926> A_IWL<56925> A_IWL<56924> A_IWL<56923> A_IWL<56922> A_IWL<56921> A_IWL<56920> A_IWL<56919> A_IWL<56918> A_IWL<56917> A_IWL<56916> A_IWL<56915> A_IWL<56914> A_IWL<56913> A_IWL<56912> A_IWL<56911> A_IWL<56910> A_IWL<56909> A_IWL<56908> A_IWL<56907> A_IWL<56906> A_IWL<56905> A_IWL<56904> A_IWL<56903> A_IWL<56902> A_IWL<56901> A_IWL<56900> A_IWL<56899> A_IWL<56898> A_IWL<56897> A_IWL<56896> A_IWL<56895> A_IWL<56894> A_IWL<56893> A_IWL<56892> A_IWL<56891> A_IWL<56890> A_IWL<56889> A_IWL<56888> A_IWL<56887> A_IWL<56886> A_IWL<56885> A_IWL<56884> A_IWL<56883> A_IWL<56882> A_IWL<56881> A_IWL<56880> A_IWL<56879> A_IWL<56878> A_IWL<56877> A_IWL<56876> A_IWL<56875> A_IWL<56874> A_IWL<56873> A_IWL<56872> A_IWL<56871> A_IWL<56870> A_IWL<56869> A_IWL<56868> A_IWL<56867> A_IWL<56866> A_IWL<56865> A_IWL<56864> A_IWL<56863> A_IWL<56862> A_IWL<56861> A_IWL<56860> A_IWL<56859> A_IWL<56858> A_IWL<56857> A_IWL<56856> A_IWL<56855> A_IWL<56854> A_IWL<56853> A_IWL<56852> A_IWL<56851> A_IWL<56850> A_IWL<56849> A_IWL<56848> A_IWL<56847> A_IWL<56846> A_IWL<56845> A_IWL<56844> A_IWL<56843> A_IWL<56842> A_IWL<56841> A_IWL<56840> A_IWL<56839> A_IWL<56838> A_IWL<56837> A_IWL<56836> A_IWL<56835> A_IWL<56834> A_IWL<56833> A_IWL<56832> VDD_CORE VSS / RM_IHPSG13_8192x32_c4_1P_COLUMN_pcell_0 +XCOL<110> A_BLC<221> A_BLC<220> A_BLC_TOP<221> A_BLC_TOP<220> A_BLT<221> A_BLT<220> A_BLT_TOP<221> A_BLT_TOP<220> A_IWL<56319> A_IWL<56318> A_IWL<56317> A_IWL<56316> A_IWL<56315> A_IWL<56314> A_IWL<56313> A_IWL<56312> A_IWL<56311> A_IWL<56310> A_IWL<56309> A_IWL<56308> A_IWL<56307> A_IWL<56306> A_IWL<56305> A_IWL<56304> A_IWL<56303> A_IWL<56302> A_IWL<56301> A_IWL<56300> A_IWL<56299> A_IWL<56298> A_IWL<56297> A_IWL<56296> A_IWL<56295> A_IWL<56294> A_IWL<56293> A_IWL<56292> A_IWL<56291> A_IWL<56290> A_IWL<56289> A_IWL<56288> A_IWL<56287> A_IWL<56286> A_IWL<56285> A_IWL<56284> A_IWL<56283> A_IWL<56282> A_IWL<56281> A_IWL<56280> A_IWL<56279> A_IWL<56278> A_IWL<56277> A_IWL<56276> A_IWL<56275> A_IWL<56274> A_IWL<56273> A_IWL<56272> A_IWL<56271> A_IWL<56270> A_IWL<56269> A_IWL<56268> A_IWL<56267> A_IWL<56266> A_IWL<56265> A_IWL<56264> A_IWL<56263> A_IWL<56262> A_IWL<56261> A_IWL<56260> A_IWL<56259> A_IWL<56258> A_IWL<56257> A_IWL<56256> A_IWL<56255> A_IWL<56254> A_IWL<56253> A_IWL<56252> A_IWL<56251> A_IWL<56250> A_IWL<56249> A_IWL<56248> A_IWL<56247> A_IWL<56246> A_IWL<56245> A_IWL<56244> A_IWL<56243> A_IWL<56242> A_IWL<56241> A_IWL<56240> A_IWL<56239> A_IWL<56238> A_IWL<56237> A_IWL<56236> A_IWL<56235> A_IWL<56234> A_IWL<56233> A_IWL<56232> A_IWL<56231> A_IWL<56230> A_IWL<56229> A_IWL<56228> A_IWL<56227> A_IWL<56226> A_IWL<56225> A_IWL<56224> A_IWL<56223> A_IWL<56222> A_IWL<56221> A_IWL<56220> A_IWL<56219> A_IWL<56218> A_IWL<56217> A_IWL<56216> A_IWL<56215> A_IWL<56214> A_IWL<56213> A_IWL<56212> A_IWL<56211> A_IWL<56210> A_IWL<56209> A_IWL<56208> A_IWL<56207> A_IWL<56206> A_IWL<56205> A_IWL<56204> A_IWL<56203> A_IWL<56202> A_IWL<56201> A_IWL<56200> A_IWL<56199> A_IWL<56198> A_IWL<56197> A_IWL<56196> A_IWL<56195> A_IWL<56194> A_IWL<56193> A_IWL<56192> A_IWL<56191> A_IWL<56190> A_IWL<56189> A_IWL<56188> A_IWL<56187> A_IWL<56186> A_IWL<56185> A_IWL<56184> A_IWL<56183> A_IWL<56182> A_IWL<56181> A_IWL<56180> A_IWL<56179> A_IWL<56178> A_IWL<56177> A_IWL<56176> A_IWL<56175> A_IWL<56174> A_IWL<56173> A_IWL<56172> A_IWL<56171> A_IWL<56170> A_IWL<56169> A_IWL<56168> A_IWL<56167> A_IWL<56166> A_IWL<56165> A_IWL<56164> A_IWL<56163> A_IWL<56162> A_IWL<56161> A_IWL<56160> A_IWL<56159> A_IWL<56158> A_IWL<56157> A_IWL<56156> A_IWL<56155> A_IWL<56154> A_IWL<56153> A_IWL<56152> A_IWL<56151> A_IWL<56150> A_IWL<56149> A_IWL<56148> A_IWL<56147> A_IWL<56146> A_IWL<56145> A_IWL<56144> A_IWL<56143> A_IWL<56142> A_IWL<56141> A_IWL<56140> A_IWL<56139> A_IWL<56138> A_IWL<56137> A_IWL<56136> A_IWL<56135> A_IWL<56134> A_IWL<56133> A_IWL<56132> A_IWL<56131> A_IWL<56130> A_IWL<56129> A_IWL<56128> A_IWL<56127> A_IWL<56126> A_IWL<56125> A_IWL<56124> A_IWL<56123> A_IWL<56122> A_IWL<56121> A_IWL<56120> A_IWL<56119> A_IWL<56118> A_IWL<56117> A_IWL<56116> A_IWL<56115> A_IWL<56114> A_IWL<56113> A_IWL<56112> A_IWL<56111> A_IWL<56110> A_IWL<56109> A_IWL<56108> A_IWL<56107> A_IWL<56106> A_IWL<56105> A_IWL<56104> A_IWL<56103> A_IWL<56102> A_IWL<56101> A_IWL<56100> A_IWL<56099> A_IWL<56098> A_IWL<56097> A_IWL<56096> A_IWL<56095> A_IWL<56094> A_IWL<56093> A_IWL<56092> A_IWL<56091> A_IWL<56090> A_IWL<56089> A_IWL<56088> A_IWL<56087> A_IWL<56086> A_IWL<56085> A_IWL<56084> A_IWL<56083> A_IWL<56082> A_IWL<56081> A_IWL<56080> A_IWL<56079> A_IWL<56078> A_IWL<56077> A_IWL<56076> A_IWL<56075> A_IWL<56074> A_IWL<56073> A_IWL<56072> A_IWL<56071> A_IWL<56070> A_IWL<56069> A_IWL<56068> A_IWL<56067> A_IWL<56066> A_IWL<56065> A_IWL<56064> A_IWL<56063> A_IWL<56062> A_IWL<56061> A_IWL<56060> A_IWL<56059> A_IWL<56058> A_IWL<56057> A_IWL<56056> A_IWL<56055> A_IWL<56054> A_IWL<56053> A_IWL<56052> A_IWL<56051> A_IWL<56050> A_IWL<56049> A_IWL<56048> A_IWL<56047> A_IWL<56046> A_IWL<56045> A_IWL<56044> A_IWL<56043> A_IWL<56042> A_IWL<56041> A_IWL<56040> A_IWL<56039> A_IWL<56038> A_IWL<56037> A_IWL<56036> A_IWL<56035> A_IWL<56034> A_IWL<56033> A_IWL<56032> A_IWL<56031> A_IWL<56030> A_IWL<56029> A_IWL<56028> A_IWL<56027> A_IWL<56026> A_IWL<56025> A_IWL<56024> A_IWL<56023> A_IWL<56022> A_IWL<56021> A_IWL<56020> A_IWL<56019> A_IWL<56018> A_IWL<56017> A_IWL<56016> A_IWL<56015> A_IWL<56014> A_IWL<56013> A_IWL<56012> A_IWL<56011> A_IWL<56010> A_IWL<56009> A_IWL<56008> A_IWL<56007> A_IWL<56006> A_IWL<56005> A_IWL<56004> A_IWL<56003> A_IWL<56002> A_IWL<56001> A_IWL<56000> A_IWL<55999> A_IWL<55998> A_IWL<55997> A_IWL<55996> A_IWL<55995> A_IWL<55994> A_IWL<55993> A_IWL<55992> A_IWL<55991> A_IWL<55990> A_IWL<55989> A_IWL<55988> A_IWL<55987> A_IWL<55986> A_IWL<55985> A_IWL<55984> A_IWL<55983> A_IWL<55982> A_IWL<55981> A_IWL<55980> A_IWL<55979> A_IWL<55978> A_IWL<55977> A_IWL<55976> A_IWL<55975> A_IWL<55974> A_IWL<55973> A_IWL<55972> A_IWL<55971> A_IWL<55970> A_IWL<55969> A_IWL<55968> A_IWL<55967> A_IWL<55966> A_IWL<55965> A_IWL<55964> A_IWL<55963> A_IWL<55962> A_IWL<55961> A_IWL<55960> A_IWL<55959> A_IWL<55958> A_IWL<55957> A_IWL<55956> A_IWL<55955> A_IWL<55954> A_IWL<55953> A_IWL<55952> A_IWL<55951> A_IWL<55950> A_IWL<55949> A_IWL<55948> A_IWL<55947> A_IWL<55946> A_IWL<55945> A_IWL<55944> A_IWL<55943> A_IWL<55942> A_IWL<55941> A_IWL<55940> A_IWL<55939> A_IWL<55938> A_IWL<55937> A_IWL<55936> A_IWL<55935> A_IWL<55934> A_IWL<55933> A_IWL<55932> A_IWL<55931> A_IWL<55930> A_IWL<55929> A_IWL<55928> A_IWL<55927> A_IWL<55926> A_IWL<55925> A_IWL<55924> A_IWL<55923> A_IWL<55922> A_IWL<55921> A_IWL<55920> A_IWL<55919> A_IWL<55918> A_IWL<55917> A_IWL<55916> A_IWL<55915> A_IWL<55914> A_IWL<55913> A_IWL<55912> A_IWL<55911> A_IWL<55910> A_IWL<55909> A_IWL<55908> A_IWL<55907> A_IWL<55906> A_IWL<55905> A_IWL<55904> A_IWL<55903> A_IWL<55902> A_IWL<55901> A_IWL<55900> A_IWL<55899> A_IWL<55898> A_IWL<55897> A_IWL<55896> A_IWL<55895> A_IWL<55894> A_IWL<55893> A_IWL<55892> A_IWL<55891> A_IWL<55890> A_IWL<55889> A_IWL<55888> A_IWL<55887> A_IWL<55886> A_IWL<55885> A_IWL<55884> A_IWL<55883> A_IWL<55882> A_IWL<55881> A_IWL<55880> A_IWL<55879> A_IWL<55878> A_IWL<55877> A_IWL<55876> A_IWL<55875> A_IWL<55874> A_IWL<55873> A_IWL<55872> A_IWL<55871> A_IWL<55870> A_IWL<55869> A_IWL<55868> A_IWL<55867> A_IWL<55866> A_IWL<55865> A_IWL<55864> A_IWL<55863> A_IWL<55862> A_IWL<55861> A_IWL<55860> A_IWL<55859> A_IWL<55858> A_IWL<55857> A_IWL<55856> A_IWL<55855> A_IWL<55854> A_IWL<55853> A_IWL<55852> A_IWL<55851> A_IWL<55850> A_IWL<55849> A_IWL<55848> A_IWL<55847> A_IWL<55846> A_IWL<55845> A_IWL<55844> A_IWL<55843> A_IWL<55842> A_IWL<55841> A_IWL<55840> A_IWL<55839> A_IWL<55838> A_IWL<55837> A_IWL<55836> A_IWL<55835> A_IWL<55834> A_IWL<55833> A_IWL<55832> A_IWL<55831> A_IWL<55830> A_IWL<55829> A_IWL<55828> A_IWL<55827> A_IWL<55826> A_IWL<55825> A_IWL<55824> A_IWL<55823> A_IWL<55822> A_IWL<55821> A_IWL<55820> A_IWL<55819> A_IWL<55818> A_IWL<55817> A_IWL<55816> A_IWL<55815> A_IWL<55814> A_IWL<55813> A_IWL<55812> A_IWL<55811> A_IWL<55810> A_IWL<55809> A_IWL<55808> A_IWL<56831> A_IWL<56830> A_IWL<56829> A_IWL<56828> A_IWL<56827> A_IWL<56826> A_IWL<56825> A_IWL<56824> A_IWL<56823> A_IWL<56822> A_IWL<56821> A_IWL<56820> A_IWL<56819> A_IWL<56818> A_IWL<56817> A_IWL<56816> A_IWL<56815> A_IWL<56814> A_IWL<56813> A_IWL<56812> A_IWL<56811> A_IWL<56810> A_IWL<56809> A_IWL<56808> A_IWL<56807> A_IWL<56806> A_IWL<56805> A_IWL<56804> A_IWL<56803> A_IWL<56802> A_IWL<56801> A_IWL<56800> A_IWL<56799> A_IWL<56798> A_IWL<56797> A_IWL<56796> A_IWL<56795> A_IWL<56794> A_IWL<56793> A_IWL<56792> A_IWL<56791> A_IWL<56790> A_IWL<56789> A_IWL<56788> A_IWL<56787> A_IWL<56786> A_IWL<56785> A_IWL<56784> A_IWL<56783> A_IWL<56782> A_IWL<56781> A_IWL<56780> A_IWL<56779> A_IWL<56778> A_IWL<56777> A_IWL<56776> A_IWL<56775> A_IWL<56774> A_IWL<56773> A_IWL<56772> A_IWL<56771> A_IWL<56770> A_IWL<56769> A_IWL<56768> A_IWL<56767> A_IWL<56766> A_IWL<56765> A_IWL<56764> A_IWL<56763> A_IWL<56762> A_IWL<56761> A_IWL<56760> A_IWL<56759> A_IWL<56758> A_IWL<56757> A_IWL<56756> A_IWL<56755> A_IWL<56754> A_IWL<56753> A_IWL<56752> A_IWL<56751> A_IWL<56750> A_IWL<56749> A_IWL<56748> A_IWL<56747> A_IWL<56746> A_IWL<56745> A_IWL<56744> A_IWL<56743> A_IWL<56742> A_IWL<56741> A_IWL<56740> A_IWL<56739> A_IWL<56738> A_IWL<56737> A_IWL<56736> A_IWL<56735> A_IWL<56734> A_IWL<56733> A_IWL<56732> A_IWL<56731> A_IWL<56730> A_IWL<56729> A_IWL<56728> A_IWL<56727> A_IWL<56726> A_IWL<56725> A_IWL<56724> A_IWL<56723> A_IWL<56722> A_IWL<56721> A_IWL<56720> A_IWL<56719> A_IWL<56718> A_IWL<56717> A_IWL<56716> A_IWL<56715> A_IWL<56714> A_IWL<56713> A_IWL<56712> A_IWL<56711> A_IWL<56710> A_IWL<56709> A_IWL<56708> A_IWL<56707> A_IWL<56706> A_IWL<56705> A_IWL<56704> A_IWL<56703> A_IWL<56702> A_IWL<56701> A_IWL<56700> A_IWL<56699> A_IWL<56698> A_IWL<56697> A_IWL<56696> A_IWL<56695> A_IWL<56694> A_IWL<56693> A_IWL<56692> A_IWL<56691> A_IWL<56690> A_IWL<56689> A_IWL<56688> A_IWL<56687> A_IWL<56686> A_IWL<56685> A_IWL<56684> A_IWL<56683> A_IWL<56682> A_IWL<56681> A_IWL<56680> A_IWL<56679> A_IWL<56678> A_IWL<56677> A_IWL<56676> A_IWL<56675> A_IWL<56674> A_IWL<56673> A_IWL<56672> A_IWL<56671> A_IWL<56670> A_IWL<56669> A_IWL<56668> A_IWL<56667> A_IWL<56666> A_IWL<56665> A_IWL<56664> A_IWL<56663> A_IWL<56662> A_IWL<56661> A_IWL<56660> A_IWL<56659> A_IWL<56658> A_IWL<56657> A_IWL<56656> A_IWL<56655> A_IWL<56654> A_IWL<56653> A_IWL<56652> A_IWL<56651> A_IWL<56650> A_IWL<56649> A_IWL<56648> A_IWL<56647> A_IWL<56646> A_IWL<56645> A_IWL<56644> A_IWL<56643> A_IWL<56642> A_IWL<56641> A_IWL<56640> A_IWL<56639> A_IWL<56638> A_IWL<56637> A_IWL<56636> A_IWL<56635> A_IWL<56634> A_IWL<56633> A_IWL<56632> A_IWL<56631> A_IWL<56630> A_IWL<56629> A_IWL<56628> A_IWL<56627> A_IWL<56626> A_IWL<56625> A_IWL<56624> A_IWL<56623> A_IWL<56622> A_IWL<56621> A_IWL<56620> A_IWL<56619> A_IWL<56618> A_IWL<56617> A_IWL<56616> A_IWL<56615> A_IWL<56614> A_IWL<56613> A_IWL<56612> A_IWL<56611> A_IWL<56610> A_IWL<56609> A_IWL<56608> A_IWL<56607> A_IWL<56606> A_IWL<56605> A_IWL<56604> A_IWL<56603> A_IWL<56602> A_IWL<56601> A_IWL<56600> A_IWL<56599> A_IWL<56598> A_IWL<56597> A_IWL<56596> A_IWL<56595> A_IWL<56594> A_IWL<56593> A_IWL<56592> A_IWL<56591> A_IWL<56590> A_IWL<56589> A_IWL<56588> A_IWL<56587> A_IWL<56586> A_IWL<56585> A_IWL<56584> A_IWL<56583> A_IWL<56582> A_IWL<56581> A_IWL<56580> A_IWL<56579> A_IWL<56578> A_IWL<56577> A_IWL<56576> A_IWL<56575> A_IWL<56574> A_IWL<56573> A_IWL<56572> A_IWL<56571> A_IWL<56570> A_IWL<56569> A_IWL<56568> A_IWL<56567> A_IWL<56566> A_IWL<56565> A_IWL<56564> A_IWL<56563> A_IWL<56562> A_IWL<56561> A_IWL<56560> A_IWL<56559> A_IWL<56558> A_IWL<56557> A_IWL<56556> A_IWL<56555> A_IWL<56554> A_IWL<56553> A_IWL<56552> A_IWL<56551> A_IWL<56550> A_IWL<56549> A_IWL<56548> A_IWL<56547> A_IWL<56546> A_IWL<56545> A_IWL<56544> A_IWL<56543> A_IWL<56542> A_IWL<56541> A_IWL<56540> A_IWL<56539> A_IWL<56538> A_IWL<56537> A_IWL<56536> A_IWL<56535> A_IWL<56534> A_IWL<56533> A_IWL<56532> A_IWL<56531> A_IWL<56530> A_IWL<56529> A_IWL<56528> A_IWL<56527> A_IWL<56526> A_IWL<56525> A_IWL<56524> A_IWL<56523> A_IWL<56522> A_IWL<56521> A_IWL<56520> A_IWL<56519> A_IWL<56518> A_IWL<56517> A_IWL<56516> A_IWL<56515> A_IWL<56514> A_IWL<56513> A_IWL<56512> A_IWL<56511> A_IWL<56510> A_IWL<56509> A_IWL<56508> A_IWL<56507> A_IWL<56506> A_IWL<56505> A_IWL<56504> A_IWL<56503> A_IWL<56502> A_IWL<56501> A_IWL<56500> A_IWL<56499> A_IWL<56498> A_IWL<56497> A_IWL<56496> A_IWL<56495> A_IWL<56494> A_IWL<56493> A_IWL<56492> A_IWL<56491> A_IWL<56490> A_IWL<56489> A_IWL<56488> A_IWL<56487> A_IWL<56486> A_IWL<56485> A_IWL<56484> A_IWL<56483> A_IWL<56482> A_IWL<56481> A_IWL<56480> A_IWL<56479> A_IWL<56478> A_IWL<56477> A_IWL<56476> A_IWL<56475> A_IWL<56474> A_IWL<56473> A_IWL<56472> A_IWL<56471> A_IWL<56470> A_IWL<56469> A_IWL<56468> A_IWL<56467> A_IWL<56466> A_IWL<56465> A_IWL<56464> A_IWL<56463> A_IWL<56462> A_IWL<56461> A_IWL<56460> A_IWL<56459> A_IWL<56458> A_IWL<56457> A_IWL<56456> A_IWL<56455> A_IWL<56454> A_IWL<56453> A_IWL<56452> A_IWL<56451> A_IWL<56450> A_IWL<56449> A_IWL<56448> A_IWL<56447> A_IWL<56446> A_IWL<56445> A_IWL<56444> A_IWL<56443> A_IWL<56442> A_IWL<56441> A_IWL<56440> A_IWL<56439> A_IWL<56438> A_IWL<56437> A_IWL<56436> A_IWL<56435> A_IWL<56434> A_IWL<56433> A_IWL<56432> A_IWL<56431> A_IWL<56430> A_IWL<56429> A_IWL<56428> A_IWL<56427> A_IWL<56426> A_IWL<56425> A_IWL<56424> A_IWL<56423> A_IWL<56422> A_IWL<56421> A_IWL<56420> A_IWL<56419> A_IWL<56418> A_IWL<56417> A_IWL<56416> A_IWL<56415> A_IWL<56414> A_IWL<56413> A_IWL<56412> A_IWL<56411> A_IWL<56410> A_IWL<56409> A_IWL<56408> A_IWL<56407> A_IWL<56406> A_IWL<56405> A_IWL<56404> A_IWL<56403> A_IWL<56402> A_IWL<56401> A_IWL<56400> A_IWL<56399> A_IWL<56398> A_IWL<56397> A_IWL<56396> A_IWL<56395> A_IWL<56394> A_IWL<56393> A_IWL<56392> A_IWL<56391> A_IWL<56390> A_IWL<56389> A_IWL<56388> A_IWL<56387> A_IWL<56386> A_IWL<56385> A_IWL<56384> A_IWL<56383> A_IWL<56382> A_IWL<56381> A_IWL<56380> A_IWL<56379> A_IWL<56378> A_IWL<56377> A_IWL<56376> A_IWL<56375> A_IWL<56374> A_IWL<56373> A_IWL<56372> A_IWL<56371> A_IWL<56370> A_IWL<56369> A_IWL<56368> A_IWL<56367> A_IWL<56366> A_IWL<56365> A_IWL<56364> A_IWL<56363> A_IWL<56362> A_IWL<56361> A_IWL<56360> A_IWL<56359> A_IWL<56358> A_IWL<56357> A_IWL<56356> A_IWL<56355> A_IWL<56354> A_IWL<56353> A_IWL<56352> A_IWL<56351> A_IWL<56350> A_IWL<56349> A_IWL<56348> A_IWL<56347> A_IWL<56346> A_IWL<56345> A_IWL<56344> A_IWL<56343> A_IWL<56342> A_IWL<56341> A_IWL<56340> A_IWL<56339> A_IWL<56338> A_IWL<56337> A_IWL<56336> A_IWL<56335> A_IWL<56334> A_IWL<56333> A_IWL<56332> A_IWL<56331> A_IWL<56330> A_IWL<56329> A_IWL<56328> A_IWL<56327> A_IWL<56326> A_IWL<56325> A_IWL<56324> A_IWL<56323> A_IWL<56322> A_IWL<56321> A_IWL<56320> VDD_CORE VSS / RM_IHPSG13_8192x32_c4_1P_COLUMN_pcell_0 +XCOL<109> A_BLC<219> A_BLC<218> A_BLC_TOP<219> A_BLC_TOP<218> A_BLT<219> A_BLT<218> A_BLT_TOP<219> A_BLT_TOP<218> A_IWL<55807> A_IWL<55806> A_IWL<55805> A_IWL<55804> A_IWL<55803> A_IWL<55802> A_IWL<55801> A_IWL<55800> A_IWL<55799> A_IWL<55798> A_IWL<55797> A_IWL<55796> A_IWL<55795> A_IWL<55794> A_IWL<55793> A_IWL<55792> A_IWL<55791> A_IWL<55790> A_IWL<55789> A_IWL<55788> A_IWL<55787> A_IWL<55786> A_IWL<55785> A_IWL<55784> A_IWL<55783> A_IWL<55782> A_IWL<55781> A_IWL<55780> A_IWL<55779> A_IWL<55778> A_IWL<55777> A_IWL<55776> A_IWL<55775> A_IWL<55774> A_IWL<55773> A_IWL<55772> A_IWL<55771> A_IWL<55770> A_IWL<55769> A_IWL<55768> A_IWL<55767> A_IWL<55766> A_IWL<55765> A_IWL<55764> A_IWL<55763> A_IWL<55762> A_IWL<55761> A_IWL<55760> A_IWL<55759> A_IWL<55758> A_IWL<55757> A_IWL<55756> A_IWL<55755> A_IWL<55754> A_IWL<55753> A_IWL<55752> A_IWL<55751> A_IWL<55750> A_IWL<55749> A_IWL<55748> A_IWL<55747> A_IWL<55746> A_IWL<55745> A_IWL<55744> A_IWL<55743> A_IWL<55742> A_IWL<55741> A_IWL<55740> A_IWL<55739> A_IWL<55738> A_IWL<55737> A_IWL<55736> A_IWL<55735> A_IWL<55734> A_IWL<55733> A_IWL<55732> A_IWL<55731> A_IWL<55730> A_IWL<55729> A_IWL<55728> A_IWL<55727> A_IWL<55726> A_IWL<55725> A_IWL<55724> A_IWL<55723> A_IWL<55722> A_IWL<55721> A_IWL<55720> A_IWL<55719> A_IWL<55718> A_IWL<55717> A_IWL<55716> A_IWL<55715> A_IWL<55714> A_IWL<55713> A_IWL<55712> A_IWL<55711> A_IWL<55710> A_IWL<55709> A_IWL<55708> A_IWL<55707> A_IWL<55706> A_IWL<55705> A_IWL<55704> A_IWL<55703> A_IWL<55702> A_IWL<55701> A_IWL<55700> A_IWL<55699> A_IWL<55698> A_IWL<55697> A_IWL<55696> A_IWL<55695> A_IWL<55694> A_IWL<55693> A_IWL<55692> A_IWL<55691> A_IWL<55690> A_IWL<55689> A_IWL<55688> A_IWL<55687> A_IWL<55686> A_IWL<55685> A_IWL<55684> A_IWL<55683> A_IWL<55682> A_IWL<55681> A_IWL<55680> A_IWL<55679> A_IWL<55678> A_IWL<55677> A_IWL<55676> A_IWL<55675> A_IWL<55674> A_IWL<55673> A_IWL<55672> A_IWL<55671> A_IWL<55670> A_IWL<55669> A_IWL<55668> A_IWL<55667> A_IWL<55666> A_IWL<55665> A_IWL<55664> A_IWL<55663> A_IWL<55662> A_IWL<55661> A_IWL<55660> A_IWL<55659> A_IWL<55658> A_IWL<55657> A_IWL<55656> A_IWL<55655> A_IWL<55654> A_IWL<55653> A_IWL<55652> A_IWL<55651> A_IWL<55650> A_IWL<55649> A_IWL<55648> A_IWL<55647> A_IWL<55646> A_IWL<55645> A_IWL<55644> A_IWL<55643> A_IWL<55642> A_IWL<55641> A_IWL<55640> A_IWL<55639> A_IWL<55638> A_IWL<55637> A_IWL<55636> A_IWL<55635> A_IWL<55634> A_IWL<55633> A_IWL<55632> A_IWL<55631> A_IWL<55630> A_IWL<55629> A_IWL<55628> A_IWL<55627> A_IWL<55626> A_IWL<55625> A_IWL<55624> A_IWL<55623> A_IWL<55622> A_IWL<55621> A_IWL<55620> A_IWL<55619> A_IWL<55618> A_IWL<55617> A_IWL<55616> A_IWL<55615> A_IWL<55614> A_IWL<55613> A_IWL<55612> A_IWL<55611> A_IWL<55610> A_IWL<55609> A_IWL<55608> A_IWL<55607> A_IWL<55606> A_IWL<55605> A_IWL<55604> A_IWL<55603> A_IWL<55602> A_IWL<55601> A_IWL<55600> A_IWL<55599> A_IWL<55598> A_IWL<55597> A_IWL<55596> A_IWL<55595> A_IWL<55594> A_IWL<55593> A_IWL<55592> A_IWL<55591> A_IWL<55590> A_IWL<55589> A_IWL<55588> A_IWL<55587> A_IWL<55586> A_IWL<55585> A_IWL<55584> A_IWL<55583> A_IWL<55582> A_IWL<55581> A_IWL<55580> A_IWL<55579> A_IWL<55578> A_IWL<55577> A_IWL<55576> A_IWL<55575> A_IWL<55574> A_IWL<55573> A_IWL<55572> A_IWL<55571> A_IWL<55570> A_IWL<55569> A_IWL<55568> A_IWL<55567> A_IWL<55566> A_IWL<55565> A_IWL<55564> A_IWL<55563> A_IWL<55562> A_IWL<55561> A_IWL<55560> A_IWL<55559> A_IWL<55558> A_IWL<55557> A_IWL<55556> A_IWL<55555> A_IWL<55554> A_IWL<55553> A_IWL<55552> A_IWL<55551> A_IWL<55550> A_IWL<55549> A_IWL<55548> A_IWL<55547> A_IWL<55546> A_IWL<55545> A_IWL<55544> A_IWL<55543> A_IWL<55542> A_IWL<55541> A_IWL<55540> A_IWL<55539> A_IWL<55538> A_IWL<55537> A_IWL<55536> A_IWL<55535> A_IWL<55534> A_IWL<55533> A_IWL<55532> A_IWL<55531> A_IWL<55530> A_IWL<55529> A_IWL<55528> A_IWL<55527> A_IWL<55526> A_IWL<55525> A_IWL<55524> A_IWL<55523> A_IWL<55522> A_IWL<55521> A_IWL<55520> A_IWL<55519> A_IWL<55518> A_IWL<55517> A_IWL<55516> A_IWL<55515> A_IWL<55514> A_IWL<55513> A_IWL<55512> A_IWL<55511> A_IWL<55510> A_IWL<55509> A_IWL<55508> A_IWL<55507> A_IWL<55506> A_IWL<55505> A_IWL<55504> A_IWL<55503> A_IWL<55502> A_IWL<55501> A_IWL<55500> A_IWL<55499> A_IWL<55498> A_IWL<55497> A_IWL<55496> A_IWL<55495> A_IWL<55494> A_IWL<55493> A_IWL<55492> A_IWL<55491> A_IWL<55490> A_IWL<55489> A_IWL<55488> A_IWL<55487> A_IWL<55486> A_IWL<55485> A_IWL<55484> A_IWL<55483> A_IWL<55482> A_IWL<55481> A_IWL<55480> A_IWL<55479> A_IWL<55478> A_IWL<55477> A_IWL<55476> A_IWL<55475> A_IWL<55474> A_IWL<55473> A_IWL<55472> A_IWL<55471> A_IWL<55470> A_IWL<55469> A_IWL<55468> A_IWL<55467> A_IWL<55466> A_IWL<55465> A_IWL<55464> A_IWL<55463> A_IWL<55462> A_IWL<55461> A_IWL<55460> A_IWL<55459> A_IWL<55458> A_IWL<55457> A_IWL<55456> A_IWL<55455> A_IWL<55454> A_IWL<55453> A_IWL<55452> A_IWL<55451> A_IWL<55450> A_IWL<55449> A_IWL<55448> A_IWL<55447> A_IWL<55446> A_IWL<55445> A_IWL<55444> A_IWL<55443> A_IWL<55442> A_IWL<55441> A_IWL<55440> A_IWL<55439> A_IWL<55438> A_IWL<55437> A_IWL<55436> A_IWL<55435> A_IWL<55434> A_IWL<55433> A_IWL<55432> A_IWL<55431> A_IWL<55430> A_IWL<55429> A_IWL<55428> A_IWL<55427> A_IWL<55426> A_IWL<55425> A_IWL<55424> A_IWL<55423> A_IWL<55422> A_IWL<55421> A_IWL<55420> A_IWL<55419> A_IWL<55418> A_IWL<55417> A_IWL<55416> A_IWL<55415> A_IWL<55414> A_IWL<55413> A_IWL<55412> A_IWL<55411> A_IWL<55410> A_IWL<55409> A_IWL<55408> A_IWL<55407> A_IWL<55406> A_IWL<55405> A_IWL<55404> A_IWL<55403> A_IWL<55402> A_IWL<55401> A_IWL<55400> A_IWL<55399> A_IWL<55398> A_IWL<55397> A_IWL<55396> A_IWL<55395> A_IWL<55394> A_IWL<55393> A_IWL<55392> A_IWL<55391> A_IWL<55390> A_IWL<55389> A_IWL<55388> A_IWL<55387> A_IWL<55386> A_IWL<55385> A_IWL<55384> A_IWL<55383> A_IWL<55382> A_IWL<55381> A_IWL<55380> A_IWL<55379> A_IWL<55378> A_IWL<55377> A_IWL<55376> A_IWL<55375> A_IWL<55374> A_IWL<55373> A_IWL<55372> A_IWL<55371> A_IWL<55370> A_IWL<55369> A_IWL<55368> A_IWL<55367> A_IWL<55366> A_IWL<55365> A_IWL<55364> A_IWL<55363> A_IWL<55362> A_IWL<55361> A_IWL<55360> A_IWL<55359> A_IWL<55358> A_IWL<55357> A_IWL<55356> A_IWL<55355> A_IWL<55354> A_IWL<55353> A_IWL<55352> A_IWL<55351> A_IWL<55350> A_IWL<55349> A_IWL<55348> A_IWL<55347> A_IWL<55346> A_IWL<55345> A_IWL<55344> A_IWL<55343> A_IWL<55342> A_IWL<55341> A_IWL<55340> A_IWL<55339> A_IWL<55338> A_IWL<55337> A_IWL<55336> A_IWL<55335> A_IWL<55334> A_IWL<55333> A_IWL<55332> A_IWL<55331> A_IWL<55330> A_IWL<55329> A_IWL<55328> A_IWL<55327> A_IWL<55326> A_IWL<55325> A_IWL<55324> A_IWL<55323> A_IWL<55322> A_IWL<55321> A_IWL<55320> A_IWL<55319> A_IWL<55318> A_IWL<55317> A_IWL<55316> A_IWL<55315> A_IWL<55314> A_IWL<55313> A_IWL<55312> A_IWL<55311> A_IWL<55310> A_IWL<55309> A_IWL<55308> A_IWL<55307> A_IWL<55306> A_IWL<55305> A_IWL<55304> A_IWL<55303> A_IWL<55302> A_IWL<55301> A_IWL<55300> A_IWL<55299> A_IWL<55298> A_IWL<55297> A_IWL<55296> A_IWL<56319> A_IWL<56318> A_IWL<56317> A_IWL<56316> A_IWL<56315> A_IWL<56314> A_IWL<56313> A_IWL<56312> A_IWL<56311> A_IWL<56310> A_IWL<56309> A_IWL<56308> A_IWL<56307> A_IWL<56306> A_IWL<56305> A_IWL<56304> A_IWL<56303> A_IWL<56302> A_IWL<56301> A_IWL<56300> A_IWL<56299> A_IWL<56298> A_IWL<56297> A_IWL<56296> A_IWL<56295> A_IWL<56294> A_IWL<56293> A_IWL<56292> A_IWL<56291> A_IWL<56290> A_IWL<56289> A_IWL<56288> A_IWL<56287> A_IWL<56286> A_IWL<56285> A_IWL<56284> A_IWL<56283> A_IWL<56282> A_IWL<56281> A_IWL<56280> A_IWL<56279> A_IWL<56278> A_IWL<56277> A_IWL<56276> A_IWL<56275> A_IWL<56274> A_IWL<56273> A_IWL<56272> A_IWL<56271> A_IWL<56270> A_IWL<56269> A_IWL<56268> A_IWL<56267> A_IWL<56266> A_IWL<56265> A_IWL<56264> A_IWL<56263> A_IWL<56262> A_IWL<56261> A_IWL<56260> A_IWL<56259> A_IWL<56258> A_IWL<56257> A_IWL<56256> A_IWL<56255> A_IWL<56254> A_IWL<56253> A_IWL<56252> A_IWL<56251> A_IWL<56250> A_IWL<56249> A_IWL<56248> A_IWL<56247> A_IWL<56246> A_IWL<56245> A_IWL<56244> A_IWL<56243> A_IWL<56242> A_IWL<56241> A_IWL<56240> A_IWL<56239> A_IWL<56238> A_IWL<56237> A_IWL<56236> A_IWL<56235> A_IWL<56234> A_IWL<56233> A_IWL<56232> A_IWL<56231> A_IWL<56230> A_IWL<56229> A_IWL<56228> A_IWL<56227> A_IWL<56226> A_IWL<56225> A_IWL<56224> A_IWL<56223> A_IWL<56222> A_IWL<56221> A_IWL<56220> A_IWL<56219> A_IWL<56218> A_IWL<56217> A_IWL<56216> A_IWL<56215> A_IWL<56214> A_IWL<56213> A_IWL<56212> A_IWL<56211> A_IWL<56210> A_IWL<56209> A_IWL<56208> A_IWL<56207> A_IWL<56206> A_IWL<56205> A_IWL<56204> A_IWL<56203> A_IWL<56202> A_IWL<56201> A_IWL<56200> A_IWL<56199> A_IWL<56198> A_IWL<56197> A_IWL<56196> A_IWL<56195> A_IWL<56194> A_IWL<56193> A_IWL<56192> A_IWL<56191> A_IWL<56190> A_IWL<56189> A_IWL<56188> A_IWL<56187> A_IWL<56186> A_IWL<56185> A_IWL<56184> A_IWL<56183> A_IWL<56182> A_IWL<56181> A_IWL<56180> A_IWL<56179> A_IWL<56178> A_IWL<56177> A_IWL<56176> A_IWL<56175> A_IWL<56174> A_IWL<56173> A_IWL<56172> A_IWL<56171> A_IWL<56170> A_IWL<56169> A_IWL<56168> A_IWL<56167> A_IWL<56166> A_IWL<56165> A_IWL<56164> A_IWL<56163> A_IWL<56162> A_IWL<56161> A_IWL<56160> A_IWL<56159> A_IWL<56158> A_IWL<56157> A_IWL<56156> A_IWL<56155> A_IWL<56154> A_IWL<56153> A_IWL<56152> A_IWL<56151> A_IWL<56150> A_IWL<56149> A_IWL<56148> A_IWL<56147> A_IWL<56146> A_IWL<56145> A_IWL<56144> A_IWL<56143> A_IWL<56142> A_IWL<56141> A_IWL<56140> A_IWL<56139> A_IWL<56138> A_IWL<56137> A_IWL<56136> A_IWL<56135> A_IWL<56134> A_IWL<56133> A_IWL<56132> A_IWL<56131> A_IWL<56130> A_IWL<56129> A_IWL<56128> A_IWL<56127> A_IWL<56126> A_IWL<56125> A_IWL<56124> A_IWL<56123> A_IWL<56122> A_IWL<56121> A_IWL<56120> A_IWL<56119> A_IWL<56118> A_IWL<56117> A_IWL<56116> A_IWL<56115> A_IWL<56114> A_IWL<56113> A_IWL<56112> A_IWL<56111> A_IWL<56110> A_IWL<56109> A_IWL<56108> A_IWL<56107> A_IWL<56106> A_IWL<56105> A_IWL<56104> A_IWL<56103> A_IWL<56102> A_IWL<56101> A_IWL<56100> A_IWL<56099> A_IWL<56098> A_IWL<56097> A_IWL<56096> A_IWL<56095> A_IWL<56094> A_IWL<56093> A_IWL<56092> A_IWL<56091> A_IWL<56090> A_IWL<56089> A_IWL<56088> A_IWL<56087> A_IWL<56086> A_IWL<56085> A_IWL<56084> A_IWL<56083> A_IWL<56082> A_IWL<56081> A_IWL<56080> A_IWL<56079> A_IWL<56078> A_IWL<56077> A_IWL<56076> A_IWL<56075> A_IWL<56074> A_IWL<56073> A_IWL<56072> A_IWL<56071> A_IWL<56070> A_IWL<56069> A_IWL<56068> A_IWL<56067> A_IWL<56066> A_IWL<56065> A_IWL<56064> A_IWL<56063> A_IWL<56062> A_IWL<56061> A_IWL<56060> A_IWL<56059> A_IWL<56058> A_IWL<56057> A_IWL<56056> A_IWL<56055> A_IWL<56054> A_IWL<56053> A_IWL<56052> A_IWL<56051> A_IWL<56050> A_IWL<56049> A_IWL<56048> A_IWL<56047> A_IWL<56046> A_IWL<56045> A_IWL<56044> A_IWL<56043> A_IWL<56042> A_IWL<56041> A_IWL<56040> A_IWL<56039> A_IWL<56038> A_IWL<56037> A_IWL<56036> A_IWL<56035> A_IWL<56034> A_IWL<56033> A_IWL<56032> A_IWL<56031> A_IWL<56030> A_IWL<56029> A_IWL<56028> A_IWL<56027> A_IWL<56026> A_IWL<56025> A_IWL<56024> A_IWL<56023> A_IWL<56022> A_IWL<56021> A_IWL<56020> A_IWL<56019> A_IWL<56018> A_IWL<56017> A_IWL<56016> A_IWL<56015> A_IWL<56014> A_IWL<56013> A_IWL<56012> A_IWL<56011> A_IWL<56010> A_IWL<56009> A_IWL<56008> A_IWL<56007> A_IWL<56006> A_IWL<56005> A_IWL<56004> A_IWL<56003> A_IWL<56002> A_IWL<56001> A_IWL<56000> A_IWL<55999> A_IWL<55998> A_IWL<55997> A_IWL<55996> A_IWL<55995> A_IWL<55994> A_IWL<55993> A_IWL<55992> A_IWL<55991> A_IWL<55990> A_IWL<55989> A_IWL<55988> A_IWL<55987> A_IWL<55986> A_IWL<55985> A_IWL<55984> A_IWL<55983> A_IWL<55982> A_IWL<55981> A_IWL<55980> A_IWL<55979> A_IWL<55978> A_IWL<55977> A_IWL<55976> A_IWL<55975> A_IWL<55974> A_IWL<55973> A_IWL<55972> A_IWL<55971> A_IWL<55970> A_IWL<55969> A_IWL<55968> A_IWL<55967> A_IWL<55966> A_IWL<55965> A_IWL<55964> A_IWL<55963> A_IWL<55962> A_IWL<55961> A_IWL<55960> A_IWL<55959> A_IWL<55958> A_IWL<55957> A_IWL<55956> A_IWL<55955> A_IWL<55954> A_IWL<55953> A_IWL<55952> A_IWL<55951> A_IWL<55950> A_IWL<55949> A_IWL<55948> A_IWL<55947> A_IWL<55946> A_IWL<55945> A_IWL<55944> A_IWL<55943> A_IWL<55942> A_IWL<55941> A_IWL<55940> A_IWL<55939> A_IWL<55938> A_IWL<55937> A_IWL<55936> A_IWL<55935> A_IWL<55934> A_IWL<55933> A_IWL<55932> A_IWL<55931> A_IWL<55930> A_IWL<55929> A_IWL<55928> A_IWL<55927> A_IWL<55926> A_IWL<55925> A_IWL<55924> A_IWL<55923> A_IWL<55922> A_IWL<55921> A_IWL<55920> A_IWL<55919> A_IWL<55918> A_IWL<55917> A_IWL<55916> A_IWL<55915> A_IWL<55914> A_IWL<55913> A_IWL<55912> A_IWL<55911> A_IWL<55910> A_IWL<55909> A_IWL<55908> A_IWL<55907> A_IWL<55906> A_IWL<55905> A_IWL<55904> A_IWL<55903> A_IWL<55902> A_IWL<55901> A_IWL<55900> A_IWL<55899> A_IWL<55898> A_IWL<55897> A_IWL<55896> A_IWL<55895> A_IWL<55894> A_IWL<55893> A_IWL<55892> A_IWL<55891> A_IWL<55890> A_IWL<55889> A_IWL<55888> A_IWL<55887> A_IWL<55886> A_IWL<55885> A_IWL<55884> A_IWL<55883> A_IWL<55882> A_IWL<55881> A_IWL<55880> A_IWL<55879> A_IWL<55878> A_IWL<55877> A_IWL<55876> A_IWL<55875> A_IWL<55874> A_IWL<55873> A_IWL<55872> A_IWL<55871> A_IWL<55870> A_IWL<55869> A_IWL<55868> A_IWL<55867> A_IWL<55866> A_IWL<55865> A_IWL<55864> A_IWL<55863> A_IWL<55862> A_IWL<55861> A_IWL<55860> A_IWL<55859> A_IWL<55858> A_IWL<55857> A_IWL<55856> A_IWL<55855> A_IWL<55854> A_IWL<55853> A_IWL<55852> A_IWL<55851> A_IWL<55850> A_IWL<55849> A_IWL<55848> A_IWL<55847> A_IWL<55846> A_IWL<55845> A_IWL<55844> A_IWL<55843> A_IWL<55842> A_IWL<55841> A_IWL<55840> A_IWL<55839> A_IWL<55838> A_IWL<55837> A_IWL<55836> A_IWL<55835> A_IWL<55834> A_IWL<55833> A_IWL<55832> A_IWL<55831> A_IWL<55830> A_IWL<55829> A_IWL<55828> A_IWL<55827> A_IWL<55826> A_IWL<55825> A_IWL<55824> A_IWL<55823> A_IWL<55822> A_IWL<55821> A_IWL<55820> A_IWL<55819> A_IWL<55818> A_IWL<55817> A_IWL<55816> A_IWL<55815> A_IWL<55814> A_IWL<55813> A_IWL<55812> A_IWL<55811> A_IWL<55810> A_IWL<55809> A_IWL<55808> VDD_CORE VSS / RM_IHPSG13_8192x32_c4_1P_COLUMN_pcell_0 +XCOL<108> A_BLC<217> A_BLC<216> A_BLC_TOP<217> A_BLC_TOP<216> A_BLT<217> A_BLT<216> A_BLT_TOP<217> A_BLT_TOP<216> A_IWL<55295> A_IWL<55294> A_IWL<55293> A_IWL<55292> A_IWL<55291> A_IWL<55290> A_IWL<55289> A_IWL<55288> A_IWL<55287> A_IWL<55286> A_IWL<55285> A_IWL<55284> A_IWL<55283> A_IWL<55282> A_IWL<55281> A_IWL<55280> A_IWL<55279> A_IWL<55278> A_IWL<55277> A_IWL<55276> A_IWL<55275> A_IWL<55274> A_IWL<55273> A_IWL<55272> A_IWL<55271> A_IWL<55270> A_IWL<55269> A_IWL<55268> A_IWL<55267> A_IWL<55266> A_IWL<55265> A_IWL<55264> A_IWL<55263> A_IWL<55262> A_IWL<55261> A_IWL<55260> A_IWL<55259> A_IWL<55258> A_IWL<55257> A_IWL<55256> A_IWL<55255> A_IWL<55254> A_IWL<55253> A_IWL<55252> A_IWL<55251> A_IWL<55250> A_IWL<55249> A_IWL<55248> A_IWL<55247> A_IWL<55246> A_IWL<55245> A_IWL<55244> A_IWL<55243> A_IWL<55242> A_IWL<55241> A_IWL<55240> A_IWL<55239> A_IWL<55238> A_IWL<55237> A_IWL<55236> A_IWL<55235> A_IWL<55234> A_IWL<55233> A_IWL<55232> A_IWL<55231> A_IWL<55230> A_IWL<55229> A_IWL<55228> A_IWL<55227> A_IWL<55226> A_IWL<55225> A_IWL<55224> A_IWL<55223> A_IWL<55222> A_IWL<55221> A_IWL<55220> A_IWL<55219> A_IWL<55218> A_IWL<55217> A_IWL<55216> A_IWL<55215> A_IWL<55214> A_IWL<55213> A_IWL<55212> A_IWL<55211> A_IWL<55210> A_IWL<55209> A_IWL<55208> A_IWL<55207> A_IWL<55206> A_IWL<55205> A_IWL<55204> A_IWL<55203> A_IWL<55202> A_IWL<55201> A_IWL<55200> A_IWL<55199> A_IWL<55198> A_IWL<55197> A_IWL<55196> A_IWL<55195> A_IWL<55194> A_IWL<55193> A_IWL<55192> A_IWL<55191> A_IWL<55190> A_IWL<55189> A_IWL<55188> A_IWL<55187> A_IWL<55186> A_IWL<55185> A_IWL<55184> A_IWL<55183> A_IWL<55182> A_IWL<55181> A_IWL<55180> A_IWL<55179> A_IWL<55178> A_IWL<55177> A_IWL<55176> A_IWL<55175> A_IWL<55174> A_IWL<55173> A_IWL<55172> A_IWL<55171> A_IWL<55170> A_IWL<55169> A_IWL<55168> A_IWL<55167> A_IWL<55166> A_IWL<55165> A_IWL<55164> A_IWL<55163> A_IWL<55162> A_IWL<55161> A_IWL<55160> A_IWL<55159> A_IWL<55158> A_IWL<55157> A_IWL<55156> A_IWL<55155> A_IWL<55154> A_IWL<55153> A_IWL<55152> A_IWL<55151> A_IWL<55150> A_IWL<55149> A_IWL<55148> A_IWL<55147> A_IWL<55146> A_IWL<55145> A_IWL<55144> A_IWL<55143> A_IWL<55142> A_IWL<55141> A_IWL<55140> A_IWL<55139> A_IWL<55138> A_IWL<55137> A_IWL<55136> A_IWL<55135> A_IWL<55134> A_IWL<55133> A_IWL<55132> A_IWL<55131> A_IWL<55130> A_IWL<55129> A_IWL<55128> A_IWL<55127> A_IWL<55126> A_IWL<55125> A_IWL<55124> A_IWL<55123> A_IWL<55122> A_IWL<55121> A_IWL<55120> A_IWL<55119> A_IWL<55118> A_IWL<55117> A_IWL<55116> A_IWL<55115> A_IWL<55114> A_IWL<55113> A_IWL<55112> A_IWL<55111> A_IWL<55110> A_IWL<55109> A_IWL<55108> A_IWL<55107> A_IWL<55106> A_IWL<55105> A_IWL<55104> A_IWL<55103> A_IWL<55102> A_IWL<55101> A_IWL<55100> A_IWL<55099> A_IWL<55098> A_IWL<55097> A_IWL<55096> A_IWL<55095> A_IWL<55094> A_IWL<55093> A_IWL<55092> A_IWL<55091> A_IWL<55090> A_IWL<55089> A_IWL<55088> A_IWL<55087> A_IWL<55086> A_IWL<55085> A_IWL<55084> A_IWL<55083> A_IWL<55082> A_IWL<55081> A_IWL<55080> A_IWL<55079> A_IWL<55078> A_IWL<55077> A_IWL<55076> A_IWL<55075> A_IWL<55074> A_IWL<55073> A_IWL<55072> A_IWL<55071> A_IWL<55070> A_IWL<55069> A_IWL<55068> A_IWL<55067> A_IWL<55066> A_IWL<55065> A_IWL<55064> A_IWL<55063> A_IWL<55062> A_IWL<55061> A_IWL<55060> A_IWL<55059> A_IWL<55058> A_IWL<55057> A_IWL<55056> A_IWL<55055> A_IWL<55054> A_IWL<55053> A_IWL<55052> A_IWL<55051> A_IWL<55050> A_IWL<55049> A_IWL<55048> A_IWL<55047> A_IWL<55046> A_IWL<55045> A_IWL<55044> A_IWL<55043> A_IWL<55042> A_IWL<55041> A_IWL<55040> A_IWL<55039> A_IWL<55038> A_IWL<55037> A_IWL<55036> A_IWL<55035> A_IWL<55034> A_IWL<55033> A_IWL<55032> A_IWL<55031> A_IWL<55030> A_IWL<55029> A_IWL<55028> A_IWL<55027> A_IWL<55026> A_IWL<55025> A_IWL<55024> A_IWL<55023> A_IWL<55022> A_IWL<55021> A_IWL<55020> A_IWL<55019> A_IWL<55018> A_IWL<55017> A_IWL<55016> A_IWL<55015> A_IWL<55014> A_IWL<55013> A_IWL<55012> A_IWL<55011> A_IWL<55010> A_IWL<55009> A_IWL<55008> A_IWL<55007> A_IWL<55006> A_IWL<55005> A_IWL<55004> A_IWL<55003> A_IWL<55002> A_IWL<55001> A_IWL<55000> A_IWL<54999> A_IWL<54998> A_IWL<54997> A_IWL<54996> A_IWL<54995> A_IWL<54994> A_IWL<54993> A_IWL<54992> A_IWL<54991> A_IWL<54990> A_IWL<54989> A_IWL<54988> A_IWL<54987> A_IWL<54986> A_IWL<54985> A_IWL<54984> A_IWL<54983> A_IWL<54982> A_IWL<54981> A_IWL<54980> A_IWL<54979> A_IWL<54978> A_IWL<54977> A_IWL<54976> A_IWL<54975> A_IWL<54974> A_IWL<54973> A_IWL<54972> A_IWL<54971> A_IWL<54970> A_IWL<54969> A_IWL<54968> A_IWL<54967> A_IWL<54966> A_IWL<54965> A_IWL<54964> A_IWL<54963> A_IWL<54962> A_IWL<54961> A_IWL<54960> A_IWL<54959> A_IWL<54958> A_IWL<54957> A_IWL<54956> A_IWL<54955> A_IWL<54954> A_IWL<54953> A_IWL<54952> A_IWL<54951> A_IWL<54950> A_IWL<54949> A_IWL<54948> A_IWL<54947> A_IWL<54946> A_IWL<54945> A_IWL<54944> A_IWL<54943> A_IWL<54942> A_IWL<54941> A_IWL<54940> A_IWL<54939> A_IWL<54938> A_IWL<54937> A_IWL<54936> A_IWL<54935> A_IWL<54934> A_IWL<54933> A_IWL<54932> A_IWL<54931> A_IWL<54930> A_IWL<54929> A_IWL<54928> A_IWL<54927> A_IWL<54926> A_IWL<54925> A_IWL<54924> A_IWL<54923> A_IWL<54922> A_IWL<54921> A_IWL<54920> A_IWL<54919> A_IWL<54918> A_IWL<54917> A_IWL<54916> A_IWL<54915> A_IWL<54914> A_IWL<54913> A_IWL<54912> A_IWL<54911> A_IWL<54910> A_IWL<54909> A_IWL<54908> A_IWL<54907> A_IWL<54906> A_IWL<54905> A_IWL<54904> A_IWL<54903> A_IWL<54902> A_IWL<54901> A_IWL<54900> A_IWL<54899> A_IWL<54898> A_IWL<54897> A_IWL<54896> A_IWL<54895> A_IWL<54894> A_IWL<54893> A_IWL<54892> A_IWL<54891> A_IWL<54890> A_IWL<54889> A_IWL<54888> A_IWL<54887> A_IWL<54886> A_IWL<54885> A_IWL<54884> A_IWL<54883> A_IWL<54882> A_IWL<54881> A_IWL<54880> A_IWL<54879> A_IWL<54878> A_IWL<54877> A_IWL<54876> A_IWL<54875> A_IWL<54874> A_IWL<54873> A_IWL<54872> A_IWL<54871> A_IWL<54870> A_IWL<54869> A_IWL<54868> A_IWL<54867> A_IWL<54866> A_IWL<54865> A_IWL<54864> A_IWL<54863> A_IWL<54862> A_IWL<54861> A_IWL<54860> A_IWL<54859> A_IWL<54858> A_IWL<54857> A_IWL<54856> A_IWL<54855> A_IWL<54854> A_IWL<54853> A_IWL<54852> A_IWL<54851> A_IWL<54850> A_IWL<54849> A_IWL<54848> A_IWL<54847> A_IWL<54846> A_IWL<54845> A_IWL<54844> A_IWL<54843> A_IWL<54842> A_IWL<54841> A_IWL<54840> A_IWL<54839> A_IWL<54838> A_IWL<54837> A_IWL<54836> A_IWL<54835> A_IWL<54834> A_IWL<54833> A_IWL<54832> A_IWL<54831> A_IWL<54830> A_IWL<54829> A_IWL<54828> A_IWL<54827> A_IWL<54826> A_IWL<54825> A_IWL<54824> A_IWL<54823> A_IWL<54822> A_IWL<54821> A_IWL<54820> A_IWL<54819> A_IWL<54818> A_IWL<54817> A_IWL<54816> A_IWL<54815> A_IWL<54814> A_IWL<54813> A_IWL<54812> A_IWL<54811> A_IWL<54810> A_IWL<54809> A_IWL<54808> A_IWL<54807> A_IWL<54806> A_IWL<54805> A_IWL<54804> A_IWL<54803> A_IWL<54802> A_IWL<54801> A_IWL<54800> A_IWL<54799> A_IWL<54798> A_IWL<54797> A_IWL<54796> A_IWL<54795> A_IWL<54794> A_IWL<54793> A_IWL<54792> A_IWL<54791> A_IWL<54790> A_IWL<54789> A_IWL<54788> A_IWL<54787> A_IWL<54786> A_IWL<54785> A_IWL<54784> A_IWL<55807> A_IWL<55806> A_IWL<55805> A_IWL<55804> A_IWL<55803> A_IWL<55802> A_IWL<55801> A_IWL<55800> A_IWL<55799> A_IWL<55798> A_IWL<55797> A_IWL<55796> A_IWL<55795> A_IWL<55794> A_IWL<55793> A_IWL<55792> A_IWL<55791> A_IWL<55790> A_IWL<55789> A_IWL<55788> A_IWL<55787> A_IWL<55786> A_IWL<55785> A_IWL<55784> A_IWL<55783> A_IWL<55782> A_IWL<55781> A_IWL<55780> A_IWL<55779> A_IWL<55778> A_IWL<55777> A_IWL<55776> A_IWL<55775> A_IWL<55774> A_IWL<55773> A_IWL<55772> A_IWL<55771> A_IWL<55770> A_IWL<55769> A_IWL<55768> A_IWL<55767> A_IWL<55766> A_IWL<55765> A_IWL<55764> A_IWL<55763> A_IWL<55762> A_IWL<55761> A_IWL<55760> A_IWL<55759> A_IWL<55758> A_IWL<55757> A_IWL<55756> A_IWL<55755> A_IWL<55754> A_IWL<55753> A_IWL<55752> A_IWL<55751> A_IWL<55750> A_IWL<55749> A_IWL<55748> A_IWL<55747> A_IWL<55746> A_IWL<55745> A_IWL<55744> A_IWL<55743> A_IWL<55742> A_IWL<55741> A_IWL<55740> A_IWL<55739> A_IWL<55738> A_IWL<55737> A_IWL<55736> A_IWL<55735> A_IWL<55734> A_IWL<55733> A_IWL<55732> A_IWL<55731> A_IWL<55730> A_IWL<55729> A_IWL<55728> A_IWL<55727> A_IWL<55726> A_IWL<55725> A_IWL<55724> A_IWL<55723> A_IWL<55722> A_IWL<55721> A_IWL<55720> A_IWL<55719> A_IWL<55718> A_IWL<55717> A_IWL<55716> A_IWL<55715> A_IWL<55714> A_IWL<55713> A_IWL<55712> A_IWL<55711> A_IWL<55710> A_IWL<55709> A_IWL<55708> A_IWL<55707> A_IWL<55706> A_IWL<55705> A_IWL<55704> A_IWL<55703> A_IWL<55702> A_IWL<55701> A_IWL<55700> A_IWL<55699> A_IWL<55698> A_IWL<55697> A_IWL<55696> A_IWL<55695> A_IWL<55694> A_IWL<55693> A_IWL<55692> A_IWL<55691> A_IWL<55690> A_IWL<55689> A_IWL<55688> A_IWL<55687> A_IWL<55686> A_IWL<55685> A_IWL<55684> A_IWL<55683> A_IWL<55682> A_IWL<55681> A_IWL<55680> A_IWL<55679> A_IWL<55678> A_IWL<55677> A_IWL<55676> A_IWL<55675> A_IWL<55674> A_IWL<55673> A_IWL<55672> A_IWL<55671> A_IWL<55670> A_IWL<55669> A_IWL<55668> A_IWL<55667> A_IWL<55666> A_IWL<55665> A_IWL<55664> A_IWL<55663> A_IWL<55662> A_IWL<55661> A_IWL<55660> A_IWL<55659> A_IWL<55658> A_IWL<55657> A_IWL<55656> A_IWL<55655> A_IWL<55654> A_IWL<55653> A_IWL<55652> A_IWL<55651> A_IWL<55650> A_IWL<55649> A_IWL<55648> A_IWL<55647> A_IWL<55646> A_IWL<55645> A_IWL<55644> A_IWL<55643> A_IWL<55642> A_IWL<55641> A_IWL<55640> A_IWL<55639> A_IWL<55638> A_IWL<55637> A_IWL<55636> A_IWL<55635> A_IWL<55634> A_IWL<55633> A_IWL<55632> A_IWL<55631> A_IWL<55630> A_IWL<55629> A_IWL<55628> A_IWL<55627> A_IWL<55626> A_IWL<55625> A_IWL<55624> A_IWL<55623> A_IWL<55622> A_IWL<55621> A_IWL<55620> A_IWL<55619> A_IWL<55618> A_IWL<55617> A_IWL<55616> A_IWL<55615> A_IWL<55614> A_IWL<55613> A_IWL<55612> A_IWL<55611> A_IWL<55610> A_IWL<55609> A_IWL<55608> A_IWL<55607> A_IWL<55606> A_IWL<55605> A_IWL<55604> A_IWL<55603> A_IWL<55602> A_IWL<55601> A_IWL<55600> A_IWL<55599> A_IWL<55598> A_IWL<55597> A_IWL<55596> A_IWL<55595> A_IWL<55594> A_IWL<55593> A_IWL<55592> A_IWL<55591> A_IWL<55590> A_IWL<55589> A_IWL<55588> A_IWL<55587> A_IWL<55586> A_IWL<55585> A_IWL<55584> A_IWL<55583> A_IWL<55582> A_IWL<55581> A_IWL<55580> A_IWL<55579> A_IWL<55578> A_IWL<55577> A_IWL<55576> A_IWL<55575> A_IWL<55574> A_IWL<55573> A_IWL<55572> A_IWL<55571> A_IWL<55570> A_IWL<55569> A_IWL<55568> A_IWL<55567> A_IWL<55566> A_IWL<55565> A_IWL<55564> A_IWL<55563> A_IWL<55562> A_IWL<55561> A_IWL<55560> A_IWL<55559> A_IWL<55558> A_IWL<55557> A_IWL<55556> A_IWL<55555> A_IWL<55554> A_IWL<55553> A_IWL<55552> A_IWL<55551> A_IWL<55550> A_IWL<55549> A_IWL<55548> A_IWL<55547> A_IWL<55546> A_IWL<55545> A_IWL<55544> A_IWL<55543> A_IWL<55542> A_IWL<55541> A_IWL<55540> A_IWL<55539> A_IWL<55538> A_IWL<55537> A_IWL<55536> A_IWL<55535> A_IWL<55534> A_IWL<55533> A_IWL<55532> A_IWL<55531> A_IWL<55530> A_IWL<55529> A_IWL<55528> A_IWL<55527> A_IWL<55526> A_IWL<55525> A_IWL<55524> A_IWL<55523> A_IWL<55522> A_IWL<55521> A_IWL<55520> A_IWL<55519> A_IWL<55518> A_IWL<55517> A_IWL<55516> A_IWL<55515> A_IWL<55514> A_IWL<55513> A_IWL<55512> A_IWL<55511> A_IWL<55510> A_IWL<55509> A_IWL<55508> A_IWL<55507> A_IWL<55506> A_IWL<55505> A_IWL<55504> A_IWL<55503> A_IWL<55502> A_IWL<55501> A_IWL<55500> A_IWL<55499> A_IWL<55498> A_IWL<55497> A_IWL<55496> A_IWL<55495> A_IWL<55494> A_IWL<55493> A_IWL<55492> A_IWL<55491> A_IWL<55490> A_IWL<55489> A_IWL<55488> A_IWL<55487> A_IWL<55486> A_IWL<55485> A_IWL<55484> A_IWL<55483> A_IWL<55482> A_IWL<55481> A_IWL<55480> A_IWL<55479> A_IWL<55478> A_IWL<55477> A_IWL<55476> A_IWL<55475> A_IWL<55474> A_IWL<55473> A_IWL<55472> A_IWL<55471> A_IWL<55470> A_IWL<55469> A_IWL<55468> A_IWL<55467> A_IWL<55466> A_IWL<55465> A_IWL<55464> A_IWL<55463> A_IWL<55462> A_IWL<55461> A_IWL<55460> A_IWL<55459> A_IWL<55458> A_IWL<55457> A_IWL<55456> A_IWL<55455> A_IWL<55454> A_IWL<55453> A_IWL<55452> A_IWL<55451> A_IWL<55450> A_IWL<55449> A_IWL<55448> A_IWL<55447> A_IWL<55446> A_IWL<55445> A_IWL<55444> A_IWL<55443> A_IWL<55442> A_IWL<55441> A_IWL<55440> A_IWL<55439> A_IWL<55438> A_IWL<55437> A_IWL<55436> A_IWL<55435> A_IWL<55434> A_IWL<55433> A_IWL<55432> A_IWL<55431> A_IWL<55430> A_IWL<55429> A_IWL<55428> A_IWL<55427> A_IWL<55426> A_IWL<55425> A_IWL<55424> A_IWL<55423> A_IWL<55422> A_IWL<55421> A_IWL<55420> A_IWL<55419> A_IWL<55418> A_IWL<55417> A_IWL<55416> A_IWL<55415> A_IWL<55414> A_IWL<55413> A_IWL<55412> A_IWL<55411> A_IWL<55410> A_IWL<55409> A_IWL<55408> A_IWL<55407> A_IWL<55406> A_IWL<55405> A_IWL<55404> A_IWL<55403> A_IWL<55402> A_IWL<55401> A_IWL<55400> A_IWL<55399> A_IWL<55398> A_IWL<55397> A_IWL<55396> A_IWL<55395> A_IWL<55394> A_IWL<55393> A_IWL<55392> A_IWL<55391> A_IWL<55390> A_IWL<55389> A_IWL<55388> A_IWL<55387> A_IWL<55386> A_IWL<55385> A_IWL<55384> A_IWL<55383> A_IWL<55382> A_IWL<55381> A_IWL<55380> A_IWL<55379> A_IWL<55378> A_IWL<55377> A_IWL<55376> A_IWL<55375> A_IWL<55374> A_IWL<55373> A_IWL<55372> A_IWL<55371> A_IWL<55370> A_IWL<55369> A_IWL<55368> A_IWL<55367> A_IWL<55366> A_IWL<55365> A_IWL<55364> A_IWL<55363> A_IWL<55362> A_IWL<55361> A_IWL<55360> A_IWL<55359> A_IWL<55358> A_IWL<55357> A_IWL<55356> A_IWL<55355> A_IWL<55354> A_IWL<55353> A_IWL<55352> A_IWL<55351> A_IWL<55350> A_IWL<55349> A_IWL<55348> A_IWL<55347> A_IWL<55346> A_IWL<55345> A_IWL<55344> A_IWL<55343> A_IWL<55342> A_IWL<55341> A_IWL<55340> A_IWL<55339> A_IWL<55338> A_IWL<55337> A_IWL<55336> A_IWL<55335> A_IWL<55334> A_IWL<55333> A_IWL<55332> A_IWL<55331> A_IWL<55330> A_IWL<55329> A_IWL<55328> A_IWL<55327> A_IWL<55326> A_IWL<55325> A_IWL<55324> A_IWL<55323> A_IWL<55322> A_IWL<55321> A_IWL<55320> A_IWL<55319> A_IWL<55318> A_IWL<55317> A_IWL<55316> A_IWL<55315> A_IWL<55314> A_IWL<55313> A_IWL<55312> A_IWL<55311> A_IWL<55310> A_IWL<55309> A_IWL<55308> A_IWL<55307> A_IWL<55306> A_IWL<55305> A_IWL<55304> A_IWL<55303> A_IWL<55302> A_IWL<55301> A_IWL<55300> A_IWL<55299> A_IWL<55298> A_IWL<55297> A_IWL<55296> VDD_CORE VSS / RM_IHPSG13_8192x32_c4_1P_COLUMN_pcell_0 +XCOL<107> A_BLC<215> A_BLC<214> A_BLC_TOP<215> A_BLC_TOP<214> A_BLT<215> A_BLT<214> A_BLT_TOP<215> A_BLT_TOP<214> A_IWL<54783> A_IWL<54782> A_IWL<54781> A_IWL<54780> A_IWL<54779> A_IWL<54778> A_IWL<54777> A_IWL<54776> A_IWL<54775> A_IWL<54774> A_IWL<54773> A_IWL<54772> A_IWL<54771> A_IWL<54770> A_IWL<54769> A_IWL<54768> A_IWL<54767> A_IWL<54766> A_IWL<54765> A_IWL<54764> A_IWL<54763> A_IWL<54762> A_IWL<54761> A_IWL<54760> A_IWL<54759> A_IWL<54758> A_IWL<54757> A_IWL<54756> A_IWL<54755> A_IWL<54754> A_IWL<54753> A_IWL<54752> A_IWL<54751> A_IWL<54750> A_IWL<54749> A_IWL<54748> A_IWL<54747> A_IWL<54746> A_IWL<54745> A_IWL<54744> A_IWL<54743> A_IWL<54742> A_IWL<54741> A_IWL<54740> A_IWL<54739> A_IWL<54738> A_IWL<54737> A_IWL<54736> A_IWL<54735> A_IWL<54734> A_IWL<54733> A_IWL<54732> A_IWL<54731> A_IWL<54730> A_IWL<54729> A_IWL<54728> A_IWL<54727> A_IWL<54726> A_IWL<54725> A_IWL<54724> A_IWL<54723> A_IWL<54722> A_IWL<54721> A_IWL<54720> A_IWL<54719> A_IWL<54718> A_IWL<54717> A_IWL<54716> A_IWL<54715> A_IWL<54714> A_IWL<54713> A_IWL<54712> A_IWL<54711> A_IWL<54710> A_IWL<54709> A_IWL<54708> A_IWL<54707> A_IWL<54706> A_IWL<54705> A_IWL<54704> A_IWL<54703> A_IWL<54702> A_IWL<54701> A_IWL<54700> A_IWL<54699> A_IWL<54698> A_IWL<54697> A_IWL<54696> A_IWL<54695> A_IWL<54694> A_IWL<54693> A_IWL<54692> A_IWL<54691> A_IWL<54690> A_IWL<54689> A_IWL<54688> A_IWL<54687> A_IWL<54686> A_IWL<54685> A_IWL<54684> A_IWL<54683> A_IWL<54682> A_IWL<54681> A_IWL<54680> A_IWL<54679> A_IWL<54678> A_IWL<54677> A_IWL<54676> A_IWL<54675> A_IWL<54674> A_IWL<54673> A_IWL<54672> A_IWL<54671> A_IWL<54670> A_IWL<54669> A_IWL<54668> A_IWL<54667> A_IWL<54666> A_IWL<54665> A_IWL<54664> A_IWL<54663> A_IWL<54662> A_IWL<54661> A_IWL<54660> A_IWL<54659> A_IWL<54658> A_IWL<54657> A_IWL<54656> A_IWL<54655> A_IWL<54654> A_IWL<54653> A_IWL<54652> A_IWL<54651> A_IWL<54650> A_IWL<54649> A_IWL<54648> A_IWL<54647> A_IWL<54646> A_IWL<54645> A_IWL<54644> A_IWL<54643> A_IWL<54642> A_IWL<54641> A_IWL<54640> A_IWL<54639> A_IWL<54638> A_IWL<54637> A_IWL<54636> A_IWL<54635> A_IWL<54634> A_IWL<54633> A_IWL<54632> A_IWL<54631> A_IWL<54630> A_IWL<54629> A_IWL<54628> A_IWL<54627> A_IWL<54626> A_IWL<54625> A_IWL<54624> A_IWL<54623> A_IWL<54622> A_IWL<54621> A_IWL<54620> A_IWL<54619> A_IWL<54618> A_IWL<54617> A_IWL<54616> A_IWL<54615> A_IWL<54614> A_IWL<54613> A_IWL<54612> A_IWL<54611> A_IWL<54610> A_IWL<54609> A_IWL<54608> A_IWL<54607> A_IWL<54606> A_IWL<54605> A_IWL<54604> A_IWL<54603> A_IWL<54602> A_IWL<54601> A_IWL<54600> A_IWL<54599> A_IWL<54598> A_IWL<54597> A_IWL<54596> A_IWL<54595> A_IWL<54594> A_IWL<54593> A_IWL<54592> A_IWL<54591> A_IWL<54590> A_IWL<54589> A_IWL<54588> A_IWL<54587> A_IWL<54586> A_IWL<54585> A_IWL<54584> A_IWL<54583> A_IWL<54582> A_IWL<54581> A_IWL<54580> A_IWL<54579> A_IWL<54578> A_IWL<54577> A_IWL<54576> A_IWL<54575> A_IWL<54574> A_IWL<54573> A_IWL<54572> A_IWL<54571> A_IWL<54570> A_IWL<54569> A_IWL<54568> A_IWL<54567> A_IWL<54566> A_IWL<54565> A_IWL<54564> A_IWL<54563> A_IWL<54562> A_IWL<54561> A_IWL<54560> A_IWL<54559> A_IWL<54558> A_IWL<54557> A_IWL<54556> A_IWL<54555> A_IWL<54554> A_IWL<54553> A_IWL<54552> A_IWL<54551> A_IWL<54550> A_IWL<54549> A_IWL<54548> A_IWL<54547> A_IWL<54546> A_IWL<54545> A_IWL<54544> A_IWL<54543> A_IWL<54542> A_IWL<54541> A_IWL<54540> A_IWL<54539> A_IWL<54538> A_IWL<54537> A_IWL<54536> A_IWL<54535> A_IWL<54534> A_IWL<54533> A_IWL<54532> A_IWL<54531> A_IWL<54530> A_IWL<54529> A_IWL<54528> A_IWL<54527> A_IWL<54526> A_IWL<54525> A_IWL<54524> A_IWL<54523> A_IWL<54522> A_IWL<54521> A_IWL<54520> A_IWL<54519> A_IWL<54518> A_IWL<54517> A_IWL<54516> A_IWL<54515> A_IWL<54514> A_IWL<54513> A_IWL<54512> A_IWL<54511> A_IWL<54510> A_IWL<54509> A_IWL<54508> A_IWL<54507> A_IWL<54506> A_IWL<54505> A_IWL<54504> A_IWL<54503> A_IWL<54502> A_IWL<54501> A_IWL<54500> A_IWL<54499> A_IWL<54498> A_IWL<54497> A_IWL<54496> A_IWL<54495> A_IWL<54494> A_IWL<54493> A_IWL<54492> A_IWL<54491> A_IWL<54490> A_IWL<54489> A_IWL<54488> A_IWL<54487> A_IWL<54486> A_IWL<54485> A_IWL<54484> A_IWL<54483> A_IWL<54482> A_IWL<54481> A_IWL<54480> A_IWL<54479> A_IWL<54478> A_IWL<54477> A_IWL<54476> A_IWL<54475> A_IWL<54474> A_IWL<54473> A_IWL<54472> A_IWL<54471> A_IWL<54470> A_IWL<54469> A_IWL<54468> A_IWL<54467> A_IWL<54466> A_IWL<54465> A_IWL<54464> A_IWL<54463> A_IWL<54462> A_IWL<54461> A_IWL<54460> A_IWL<54459> A_IWL<54458> A_IWL<54457> A_IWL<54456> A_IWL<54455> A_IWL<54454> A_IWL<54453> A_IWL<54452> A_IWL<54451> A_IWL<54450> A_IWL<54449> A_IWL<54448> A_IWL<54447> A_IWL<54446> A_IWL<54445> A_IWL<54444> A_IWL<54443> A_IWL<54442> A_IWL<54441> A_IWL<54440> A_IWL<54439> A_IWL<54438> A_IWL<54437> A_IWL<54436> A_IWL<54435> A_IWL<54434> A_IWL<54433> A_IWL<54432> A_IWL<54431> A_IWL<54430> A_IWL<54429> A_IWL<54428> A_IWL<54427> A_IWL<54426> A_IWL<54425> A_IWL<54424> A_IWL<54423> A_IWL<54422> A_IWL<54421> A_IWL<54420> A_IWL<54419> A_IWL<54418> A_IWL<54417> A_IWL<54416> A_IWL<54415> A_IWL<54414> A_IWL<54413> A_IWL<54412> A_IWL<54411> A_IWL<54410> A_IWL<54409> A_IWL<54408> A_IWL<54407> A_IWL<54406> A_IWL<54405> A_IWL<54404> A_IWL<54403> A_IWL<54402> A_IWL<54401> A_IWL<54400> A_IWL<54399> A_IWL<54398> A_IWL<54397> A_IWL<54396> A_IWL<54395> A_IWL<54394> A_IWL<54393> A_IWL<54392> A_IWL<54391> A_IWL<54390> A_IWL<54389> A_IWL<54388> A_IWL<54387> A_IWL<54386> A_IWL<54385> A_IWL<54384> A_IWL<54383> A_IWL<54382> A_IWL<54381> A_IWL<54380> A_IWL<54379> A_IWL<54378> A_IWL<54377> A_IWL<54376> A_IWL<54375> A_IWL<54374> A_IWL<54373> A_IWL<54372> A_IWL<54371> A_IWL<54370> A_IWL<54369> A_IWL<54368> A_IWL<54367> A_IWL<54366> A_IWL<54365> A_IWL<54364> A_IWL<54363> A_IWL<54362> A_IWL<54361> A_IWL<54360> A_IWL<54359> A_IWL<54358> A_IWL<54357> A_IWL<54356> A_IWL<54355> A_IWL<54354> A_IWL<54353> A_IWL<54352> A_IWL<54351> A_IWL<54350> A_IWL<54349> A_IWL<54348> A_IWL<54347> A_IWL<54346> A_IWL<54345> A_IWL<54344> A_IWL<54343> A_IWL<54342> A_IWL<54341> A_IWL<54340> A_IWL<54339> A_IWL<54338> A_IWL<54337> A_IWL<54336> A_IWL<54335> A_IWL<54334> A_IWL<54333> A_IWL<54332> A_IWL<54331> A_IWL<54330> A_IWL<54329> A_IWL<54328> A_IWL<54327> A_IWL<54326> A_IWL<54325> A_IWL<54324> A_IWL<54323> A_IWL<54322> A_IWL<54321> A_IWL<54320> A_IWL<54319> A_IWL<54318> A_IWL<54317> A_IWL<54316> A_IWL<54315> A_IWL<54314> A_IWL<54313> A_IWL<54312> A_IWL<54311> A_IWL<54310> A_IWL<54309> A_IWL<54308> A_IWL<54307> A_IWL<54306> A_IWL<54305> A_IWL<54304> A_IWL<54303> A_IWL<54302> A_IWL<54301> A_IWL<54300> A_IWL<54299> A_IWL<54298> A_IWL<54297> A_IWL<54296> A_IWL<54295> A_IWL<54294> A_IWL<54293> A_IWL<54292> A_IWL<54291> A_IWL<54290> A_IWL<54289> A_IWL<54288> A_IWL<54287> A_IWL<54286> A_IWL<54285> A_IWL<54284> A_IWL<54283> A_IWL<54282> A_IWL<54281> A_IWL<54280> A_IWL<54279> A_IWL<54278> A_IWL<54277> A_IWL<54276> A_IWL<54275> A_IWL<54274> A_IWL<54273> A_IWL<54272> A_IWL<55295> A_IWL<55294> A_IWL<55293> A_IWL<55292> A_IWL<55291> A_IWL<55290> A_IWL<55289> A_IWL<55288> A_IWL<55287> A_IWL<55286> A_IWL<55285> A_IWL<55284> A_IWL<55283> A_IWL<55282> A_IWL<55281> A_IWL<55280> A_IWL<55279> A_IWL<55278> A_IWL<55277> A_IWL<55276> A_IWL<55275> A_IWL<55274> A_IWL<55273> A_IWL<55272> A_IWL<55271> A_IWL<55270> A_IWL<55269> A_IWL<55268> A_IWL<55267> A_IWL<55266> A_IWL<55265> A_IWL<55264> A_IWL<55263> A_IWL<55262> A_IWL<55261> A_IWL<55260> A_IWL<55259> A_IWL<55258> A_IWL<55257> A_IWL<55256> A_IWL<55255> A_IWL<55254> A_IWL<55253> A_IWL<55252> A_IWL<55251> A_IWL<55250> A_IWL<55249> A_IWL<55248> A_IWL<55247> A_IWL<55246> A_IWL<55245> A_IWL<55244> A_IWL<55243> A_IWL<55242> A_IWL<55241> A_IWL<55240> A_IWL<55239> A_IWL<55238> A_IWL<55237> A_IWL<55236> A_IWL<55235> A_IWL<55234> A_IWL<55233> A_IWL<55232> A_IWL<55231> A_IWL<55230> A_IWL<55229> A_IWL<55228> A_IWL<55227> A_IWL<55226> A_IWL<55225> A_IWL<55224> A_IWL<55223> A_IWL<55222> A_IWL<55221> A_IWL<55220> A_IWL<55219> A_IWL<55218> A_IWL<55217> A_IWL<55216> A_IWL<55215> A_IWL<55214> A_IWL<55213> A_IWL<55212> A_IWL<55211> A_IWL<55210> A_IWL<55209> A_IWL<55208> A_IWL<55207> A_IWL<55206> A_IWL<55205> A_IWL<55204> A_IWL<55203> A_IWL<55202> A_IWL<55201> A_IWL<55200> A_IWL<55199> A_IWL<55198> A_IWL<55197> A_IWL<55196> A_IWL<55195> A_IWL<55194> A_IWL<55193> A_IWL<55192> A_IWL<55191> A_IWL<55190> A_IWL<55189> A_IWL<55188> A_IWL<55187> A_IWL<55186> A_IWL<55185> A_IWL<55184> A_IWL<55183> A_IWL<55182> A_IWL<55181> A_IWL<55180> A_IWL<55179> A_IWL<55178> A_IWL<55177> A_IWL<55176> A_IWL<55175> A_IWL<55174> A_IWL<55173> A_IWL<55172> A_IWL<55171> A_IWL<55170> A_IWL<55169> A_IWL<55168> A_IWL<55167> A_IWL<55166> A_IWL<55165> A_IWL<55164> A_IWL<55163> A_IWL<55162> A_IWL<55161> A_IWL<55160> A_IWL<55159> A_IWL<55158> A_IWL<55157> A_IWL<55156> A_IWL<55155> A_IWL<55154> A_IWL<55153> A_IWL<55152> A_IWL<55151> A_IWL<55150> A_IWL<55149> A_IWL<55148> A_IWL<55147> A_IWL<55146> A_IWL<55145> A_IWL<55144> A_IWL<55143> A_IWL<55142> A_IWL<55141> A_IWL<55140> A_IWL<55139> A_IWL<55138> A_IWL<55137> A_IWL<55136> A_IWL<55135> A_IWL<55134> A_IWL<55133> A_IWL<55132> A_IWL<55131> A_IWL<55130> A_IWL<55129> A_IWL<55128> A_IWL<55127> A_IWL<55126> A_IWL<55125> A_IWL<55124> A_IWL<55123> A_IWL<55122> A_IWL<55121> A_IWL<55120> A_IWL<55119> A_IWL<55118> A_IWL<55117> A_IWL<55116> A_IWL<55115> A_IWL<55114> A_IWL<55113> A_IWL<55112> A_IWL<55111> A_IWL<55110> A_IWL<55109> A_IWL<55108> A_IWL<55107> A_IWL<55106> A_IWL<55105> A_IWL<55104> A_IWL<55103> A_IWL<55102> A_IWL<55101> A_IWL<55100> A_IWL<55099> A_IWL<55098> A_IWL<55097> A_IWL<55096> A_IWL<55095> A_IWL<55094> A_IWL<55093> A_IWL<55092> A_IWL<55091> A_IWL<55090> A_IWL<55089> A_IWL<55088> A_IWL<55087> A_IWL<55086> A_IWL<55085> A_IWL<55084> A_IWL<55083> A_IWL<55082> A_IWL<55081> A_IWL<55080> A_IWL<55079> A_IWL<55078> A_IWL<55077> A_IWL<55076> A_IWL<55075> A_IWL<55074> A_IWL<55073> A_IWL<55072> A_IWL<55071> A_IWL<55070> A_IWL<55069> A_IWL<55068> A_IWL<55067> A_IWL<55066> A_IWL<55065> A_IWL<55064> A_IWL<55063> A_IWL<55062> A_IWL<55061> A_IWL<55060> A_IWL<55059> A_IWL<55058> A_IWL<55057> A_IWL<55056> A_IWL<55055> A_IWL<55054> A_IWL<55053> A_IWL<55052> A_IWL<55051> A_IWL<55050> A_IWL<55049> A_IWL<55048> A_IWL<55047> A_IWL<55046> A_IWL<55045> A_IWL<55044> A_IWL<55043> A_IWL<55042> A_IWL<55041> A_IWL<55040> A_IWL<55039> A_IWL<55038> A_IWL<55037> A_IWL<55036> A_IWL<55035> A_IWL<55034> A_IWL<55033> A_IWL<55032> A_IWL<55031> A_IWL<55030> A_IWL<55029> A_IWL<55028> A_IWL<55027> A_IWL<55026> A_IWL<55025> A_IWL<55024> A_IWL<55023> A_IWL<55022> A_IWL<55021> A_IWL<55020> A_IWL<55019> A_IWL<55018> A_IWL<55017> A_IWL<55016> A_IWL<55015> A_IWL<55014> A_IWL<55013> A_IWL<55012> A_IWL<55011> A_IWL<55010> A_IWL<55009> A_IWL<55008> A_IWL<55007> A_IWL<55006> A_IWL<55005> A_IWL<55004> A_IWL<55003> A_IWL<55002> A_IWL<55001> A_IWL<55000> A_IWL<54999> A_IWL<54998> A_IWL<54997> A_IWL<54996> A_IWL<54995> A_IWL<54994> A_IWL<54993> A_IWL<54992> A_IWL<54991> A_IWL<54990> A_IWL<54989> A_IWL<54988> A_IWL<54987> A_IWL<54986> A_IWL<54985> A_IWL<54984> A_IWL<54983> A_IWL<54982> A_IWL<54981> A_IWL<54980> A_IWL<54979> A_IWL<54978> A_IWL<54977> A_IWL<54976> A_IWL<54975> A_IWL<54974> A_IWL<54973> A_IWL<54972> A_IWL<54971> A_IWL<54970> A_IWL<54969> A_IWL<54968> A_IWL<54967> A_IWL<54966> A_IWL<54965> A_IWL<54964> A_IWL<54963> A_IWL<54962> A_IWL<54961> A_IWL<54960> A_IWL<54959> A_IWL<54958> A_IWL<54957> A_IWL<54956> A_IWL<54955> A_IWL<54954> A_IWL<54953> A_IWL<54952> A_IWL<54951> A_IWL<54950> A_IWL<54949> A_IWL<54948> A_IWL<54947> A_IWL<54946> A_IWL<54945> A_IWL<54944> A_IWL<54943> A_IWL<54942> A_IWL<54941> A_IWL<54940> A_IWL<54939> A_IWL<54938> A_IWL<54937> A_IWL<54936> A_IWL<54935> A_IWL<54934> A_IWL<54933> A_IWL<54932> A_IWL<54931> A_IWL<54930> A_IWL<54929> A_IWL<54928> A_IWL<54927> A_IWL<54926> A_IWL<54925> A_IWL<54924> A_IWL<54923> A_IWL<54922> A_IWL<54921> A_IWL<54920> A_IWL<54919> A_IWL<54918> A_IWL<54917> A_IWL<54916> A_IWL<54915> A_IWL<54914> A_IWL<54913> A_IWL<54912> A_IWL<54911> A_IWL<54910> A_IWL<54909> A_IWL<54908> A_IWL<54907> A_IWL<54906> A_IWL<54905> A_IWL<54904> A_IWL<54903> A_IWL<54902> A_IWL<54901> A_IWL<54900> A_IWL<54899> A_IWL<54898> A_IWL<54897> A_IWL<54896> A_IWL<54895> A_IWL<54894> A_IWL<54893> A_IWL<54892> A_IWL<54891> A_IWL<54890> A_IWL<54889> A_IWL<54888> A_IWL<54887> A_IWL<54886> A_IWL<54885> A_IWL<54884> A_IWL<54883> A_IWL<54882> A_IWL<54881> A_IWL<54880> A_IWL<54879> A_IWL<54878> A_IWL<54877> A_IWL<54876> A_IWL<54875> A_IWL<54874> A_IWL<54873> A_IWL<54872> A_IWL<54871> A_IWL<54870> A_IWL<54869> A_IWL<54868> A_IWL<54867> A_IWL<54866> A_IWL<54865> A_IWL<54864> A_IWL<54863> A_IWL<54862> A_IWL<54861> A_IWL<54860> A_IWL<54859> A_IWL<54858> A_IWL<54857> A_IWL<54856> A_IWL<54855> A_IWL<54854> A_IWL<54853> A_IWL<54852> A_IWL<54851> A_IWL<54850> A_IWL<54849> A_IWL<54848> A_IWL<54847> A_IWL<54846> A_IWL<54845> A_IWL<54844> A_IWL<54843> A_IWL<54842> A_IWL<54841> A_IWL<54840> A_IWL<54839> A_IWL<54838> A_IWL<54837> A_IWL<54836> A_IWL<54835> A_IWL<54834> A_IWL<54833> A_IWL<54832> A_IWL<54831> A_IWL<54830> A_IWL<54829> A_IWL<54828> A_IWL<54827> A_IWL<54826> A_IWL<54825> A_IWL<54824> A_IWL<54823> A_IWL<54822> A_IWL<54821> A_IWL<54820> A_IWL<54819> A_IWL<54818> A_IWL<54817> A_IWL<54816> A_IWL<54815> A_IWL<54814> A_IWL<54813> A_IWL<54812> A_IWL<54811> A_IWL<54810> A_IWL<54809> A_IWL<54808> A_IWL<54807> A_IWL<54806> A_IWL<54805> A_IWL<54804> A_IWL<54803> A_IWL<54802> A_IWL<54801> A_IWL<54800> A_IWL<54799> A_IWL<54798> A_IWL<54797> A_IWL<54796> A_IWL<54795> A_IWL<54794> A_IWL<54793> A_IWL<54792> A_IWL<54791> A_IWL<54790> A_IWL<54789> A_IWL<54788> A_IWL<54787> A_IWL<54786> A_IWL<54785> A_IWL<54784> VDD_CORE VSS / RM_IHPSG13_8192x32_c4_1P_COLUMN_pcell_0 +XCOL<106> A_BLC<213> A_BLC<212> A_BLC_TOP<213> A_BLC_TOP<212> A_BLT<213> A_BLT<212> A_BLT_TOP<213> A_BLT_TOP<212> A_IWL<54271> A_IWL<54270> A_IWL<54269> A_IWL<54268> A_IWL<54267> A_IWL<54266> A_IWL<54265> A_IWL<54264> A_IWL<54263> A_IWL<54262> A_IWL<54261> A_IWL<54260> A_IWL<54259> A_IWL<54258> A_IWL<54257> A_IWL<54256> A_IWL<54255> A_IWL<54254> A_IWL<54253> A_IWL<54252> A_IWL<54251> A_IWL<54250> A_IWL<54249> A_IWL<54248> A_IWL<54247> A_IWL<54246> A_IWL<54245> A_IWL<54244> A_IWL<54243> A_IWL<54242> A_IWL<54241> A_IWL<54240> A_IWL<54239> A_IWL<54238> A_IWL<54237> A_IWL<54236> A_IWL<54235> A_IWL<54234> A_IWL<54233> A_IWL<54232> A_IWL<54231> A_IWL<54230> A_IWL<54229> A_IWL<54228> A_IWL<54227> A_IWL<54226> A_IWL<54225> A_IWL<54224> A_IWL<54223> A_IWL<54222> A_IWL<54221> A_IWL<54220> A_IWL<54219> A_IWL<54218> A_IWL<54217> A_IWL<54216> A_IWL<54215> A_IWL<54214> A_IWL<54213> A_IWL<54212> A_IWL<54211> A_IWL<54210> A_IWL<54209> A_IWL<54208> A_IWL<54207> A_IWL<54206> A_IWL<54205> A_IWL<54204> A_IWL<54203> A_IWL<54202> A_IWL<54201> A_IWL<54200> A_IWL<54199> A_IWL<54198> A_IWL<54197> A_IWL<54196> A_IWL<54195> A_IWL<54194> A_IWL<54193> A_IWL<54192> A_IWL<54191> A_IWL<54190> A_IWL<54189> A_IWL<54188> A_IWL<54187> A_IWL<54186> A_IWL<54185> A_IWL<54184> A_IWL<54183> A_IWL<54182> A_IWL<54181> A_IWL<54180> A_IWL<54179> A_IWL<54178> A_IWL<54177> A_IWL<54176> A_IWL<54175> A_IWL<54174> A_IWL<54173> A_IWL<54172> A_IWL<54171> A_IWL<54170> A_IWL<54169> A_IWL<54168> A_IWL<54167> A_IWL<54166> A_IWL<54165> A_IWL<54164> A_IWL<54163> A_IWL<54162> A_IWL<54161> A_IWL<54160> A_IWL<54159> A_IWL<54158> A_IWL<54157> A_IWL<54156> A_IWL<54155> A_IWL<54154> A_IWL<54153> A_IWL<54152> A_IWL<54151> A_IWL<54150> A_IWL<54149> A_IWL<54148> A_IWL<54147> A_IWL<54146> A_IWL<54145> A_IWL<54144> A_IWL<54143> A_IWL<54142> A_IWL<54141> A_IWL<54140> A_IWL<54139> A_IWL<54138> A_IWL<54137> A_IWL<54136> A_IWL<54135> A_IWL<54134> A_IWL<54133> A_IWL<54132> A_IWL<54131> A_IWL<54130> A_IWL<54129> A_IWL<54128> A_IWL<54127> A_IWL<54126> A_IWL<54125> A_IWL<54124> A_IWL<54123> A_IWL<54122> A_IWL<54121> A_IWL<54120> A_IWL<54119> A_IWL<54118> A_IWL<54117> A_IWL<54116> A_IWL<54115> A_IWL<54114> A_IWL<54113> A_IWL<54112> A_IWL<54111> A_IWL<54110> A_IWL<54109> A_IWL<54108> A_IWL<54107> A_IWL<54106> A_IWL<54105> A_IWL<54104> A_IWL<54103> A_IWL<54102> A_IWL<54101> A_IWL<54100> A_IWL<54099> A_IWL<54098> A_IWL<54097> A_IWL<54096> A_IWL<54095> A_IWL<54094> A_IWL<54093> A_IWL<54092> A_IWL<54091> A_IWL<54090> A_IWL<54089> A_IWL<54088> A_IWL<54087> A_IWL<54086> A_IWL<54085> A_IWL<54084> A_IWL<54083> A_IWL<54082> A_IWL<54081> A_IWL<54080> A_IWL<54079> A_IWL<54078> A_IWL<54077> A_IWL<54076> A_IWL<54075> A_IWL<54074> A_IWL<54073> A_IWL<54072> A_IWL<54071> A_IWL<54070> A_IWL<54069> A_IWL<54068> A_IWL<54067> A_IWL<54066> A_IWL<54065> A_IWL<54064> A_IWL<54063> A_IWL<54062> A_IWL<54061> A_IWL<54060> A_IWL<54059> A_IWL<54058> A_IWL<54057> A_IWL<54056> A_IWL<54055> A_IWL<54054> A_IWL<54053> A_IWL<54052> A_IWL<54051> A_IWL<54050> A_IWL<54049> A_IWL<54048> A_IWL<54047> A_IWL<54046> A_IWL<54045> A_IWL<54044> A_IWL<54043> A_IWL<54042> A_IWL<54041> A_IWL<54040> A_IWL<54039> A_IWL<54038> A_IWL<54037> A_IWL<54036> A_IWL<54035> A_IWL<54034> A_IWL<54033> A_IWL<54032> A_IWL<54031> A_IWL<54030> A_IWL<54029> A_IWL<54028> A_IWL<54027> A_IWL<54026> A_IWL<54025> A_IWL<54024> A_IWL<54023> A_IWL<54022> A_IWL<54021> A_IWL<54020> A_IWL<54019> A_IWL<54018> A_IWL<54017> A_IWL<54016> A_IWL<54015> A_IWL<54014> A_IWL<54013> A_IWL<54012> A_IWL<54011> A_IWL<54010> A_IWL<54009> A_IWL<54008> A_IWL<54007> A_IWL<54006> A_IWL<54005> A_IWL<54004> A_IWL<54003> A_IWL<54002> A_IWL<54001> A_IWL<54000> A_IWL<53999> A_IWL<53998> A_IWL<53997> A_IWL<53996> A_IWL<53995> A_IWL<53994> A_IWL<53993> A_IWL<53992> A_IWL<53991> A_IWL<53990> A_IWL<53989> A_IWL<53988> A_IWL<53987> A_IWL<53986> A_IWL<53985> A_IWL<53984> A_IWL<53983> A_IWL<53982> A_IWL<53981> A_IWL<53980> A_IWL<53979> A_IWL<53978> A_IWL<53977> A_IWL<53976> A_IWL<53975> A_IWL<53974> A_IWL<53973> A_IWL<53972> A_IWL<53971> A_IWL<53970> A_IWL<53969> A_IWL<53968> A_IWL<53967> A_IWL<53966> A_IWL<53965> A_IWL<53964> A_IWL<53963> A_IWL<53962> A_IWL<53961> A_IWL<53960> A_IWL<53959> A_IWL<53958> A_IWL<53957> A_IWL<53956> A_IWL<53955> A_IWL<53954> A_IWL<53953> A_IWL<53952> A_IWL<53951> A_IWL<53950> A_IWL<53949> A_IWL<53948> A_IWL<53947> A_IWL<53946> A_IWL<53945> A_IWL<53944> A_IWL<53943> A_IWL<53942> A_IWL<53941> A_IWL<53940> A_IWL<53939> A_IWL<53938> A_IWL<53937> A_IWL<53936> A_IWL<53935> A_IWL<53934> A_IWL<53933> A_IWL<53932> A_IWL<53931> A_IWL<53930> A_IWL<53929> A_IWL<53928> A_IWL<53927> A_IWL<53926> A_IWL<53925> A_IWL<53924> A_IWL<53923> A_IWL<53922> A_IWL<53921> A_IWL<53920> A_IWL<53919> A_IWL<53918> A_IWL<53917> A_IWL<53916> A_IWL<53915> A_IWL<53914> A_IWL<53913> A_IWL<53912> A_IWL<53911> A_IWL<53910> A_IWL<53909> A_IWL<53908> A_IWL<53907> A_IWL<53906> A_IWL<53905> A_IWL<53904> A_IWL<53903> A_IWL<53902> A_IWL<53901> A_IWL<53900> A_IWL<53899> A_IWL<53898> A_IWL<53897> A_IWL<53896> A_IWL<53895> A_IWL<53894> A_IWL<53893> A_IWL<53892> A_IWL<53891> A_IWL<53890> A_IWL<53889> A_IWL<53888> A_IWL<53887> A_IWL<53886> A_IWL<53885> A_IWL<53884> A_IWL<53883> A_IWL<53882> A_IWL<53881> A_IWL<53880> A_IWL<53879> A_IWL<53878> A_IWL<53877> A_IWL<53876> A_IWL<53875> A_IWL<53874> A_IWL<53873> A_IWL<53872> A_IWL<53871> A_IWL<53870> A_IWL<53869> A_IWL<53868> A_IWL<53867> A_IWL<53866> A_IWL<53865> A_IWL<53864> A_IWL<53863> A_IWL<53862> A_IWL<53861> A_IWL<53860> A_IWL<53859> A_IWL<53858> A_IWL<53857> A_IWL<53856> A_IWL<53855> A_IWL<53854> A_IWL<53853> A_IWL<53852> A_IWL<53851> A_IWL<53850> A_IWL<53849> A_IWL<53848> A_IWL<53847> A_IWL<53846> A_IWL<53845> A_IWL<53844> A_IWL<53843> A_IWL<53842> A_IWL<53841> A_IWL<53840> A_IWL<53839> A_IWL<53838> A_IWL<53837> A_IWL<53836> A_IWL<53835> A_IWL<53834> A_IWL<53833> A_IWL<53832> A_IWL<53831> A_IWL<53830> A_IWL<53829> A_IWL<53828> A_IWL<53827> A_IWL<53826> A_IWL<53825> A_IWL<53824> A_IWL<53823> A_IWL<53822> A_IWL<53821> A_IWL<53820> A_IWL<53819> A_IWL<53818> A_IWL<53817> A_IWL<53816> A_IWL<53815> A_IWL<53814> A_IWL<53813> A_IWL<53812> A_IWL<53811> A_IWL<53810> A_IWL<53809> A_IWL<53808> A_IWL<53807> A_IWL<53806> A_IWL<53805> A_IWL<53804> A_IWL<53803> A_IWL<53802> A_IWL<53801> A_IWL<53800> A_IWL<53799> A_IWL<53798> A_IWL<53797> A_IWL<53796> A_IWL<53795> A_IWL<53794> A_IWL<53793> A_IWL<53792> A_IWL<53791> A_IWL<53790> A_IWL<53789> A_IWL<53788> A_IWL<53787> A_IWL<53786> A_IWL<53785> A_IWL<53784> A_IWL<53783> A_IWL<53782> A_IWL<53781> A_IWL<53780> A_IWL<53779> A_IWL<53778> A_IWL<53777> A_IWL<53776> A_IWL<53775> A_IWL<53774> A_IWL<53773> A_IWL<53772> A_IWL<53771> A_IWL<53770> A_IWL<53769> A_IWL<53768> A_IWL<53767> A_IWL<53766> A_IWL<53765> A_IWL<53764> A_IWL<53763> A_IWL<53762> A_IWL<53761> A_IWL<53760> A_IWL<54783> A_IWL<54782> A_IWL<54781> A_IWL<54780> A_IWL<54779> A_IWL<54778> A_IWL<54777> A_IWL<54776> A_IWL<54775> A_IWL<54774> A_IWL<54773> A_IWL<54772> A_IWL<54771> A_IWL<54770> A_IWL<54769> A_IWL<54768> A_IWL<54767> A_IWL<54766> A_IWL<54765> A_IWL<54764> A_IWL<54763> A_IWL<54762> A_IWL<54761> A_IWL<54760> A_IWL<54759> A_IWL<54758> A_IWL<54757> A_IWL<54756> A_IWL<54755> A_IWL<54754> A_IWL<54753> A_IWL<54752> A_IWL<54751> A_IWL<54750> A_IWL<54749> A_IWL<54748> A_IWL<54747> A_IWL<54746> A_IWL<54745> A_IWL<54744> A_IWL<54743> A_IWL<54742> A_IWL<54741> A_IWL<54740> A_IWL<54739> A_IWL<54738> A_IWL<54737> A_IWL<54736> A_IWL<54735> A_IWL<54734> A_IWL<54733> A_IWL<54732> A_IWL<54731> A_IWL<54730> A_IWL<54729> A_IWL<54728> A_IWL<54727> A_IWL<54726> A_IWL<54725> A_IWL<54724> A_IWL<54723> A_IWL<54722> A_IWL<54721> A_IWL<54720> A_IWL<54719> A_IWL<54718> A_IWL<54717> A_IWL<54716> A_IWL<54715> A_IWL<54714> A_IWL<54713> A_IWL<54712> A_IWL<54711> A_IWL<54710> A_IWL<54709> A_IWL<54708> A_IWL<54707> A_IWL<54706> A_IWL<54705> A_IWL<54704> A_IWL<54703> A_IWL<54702> A_IWL<54701> A_IWL<54700> A_IWL<54699> A_IWL<54698> A_IWL<54697> A_IWL<54696> A_IWL<54695> A_IWL<54694> A_IWL<54693> A_IWL<54692> A_IWL<54691> A_IWL<54690> A_IWL<54689> A_IWL<54688> A_IWL<54687> A_IWL<54686> A_IWL<54685> A_IWL<54684> A_IWL<54683> A_IWL<54682> A_IWL<54681> A_IWL<54680> A_IWL<54679> A_IWL<54678> A_IWL<54677> A_IWL<54676> A_IWL<54675> A_IWL<54674> A_IWL<54673> A_IWL<54672> A_IWL<54671> A_IWL<54670> A_IWL<54669> A_IWL<54668> A_IWL<54667> A_IWL<54666> A_IWL<54665> A_IWL<54664> A_IWL<54663> A_IWL<54662> A_IWL<54661> A_IWL<54660> A_IWL<54659> A_IWL<54658> A_IWL<54657> A_IWL<54656> A_IWL<54655> A_IWL<54654> A_IWL<54653> A_IWL<54652> A_IWL<54651> A_IWL<54650> A_IWL<54649> A_IWL<54648> A_IWL<54647> A_IWL<54646> A_IWL<54645> A_IWL<54644> A_IWL<54643> A_IWL<54642> A_IWL<54641> A_IWL<54640> A_IWL<54639> A_IWL<54638> A_IWL<54637> A_IWL<54636> A_IWL<54635> A_IWL<54634> A_IWL<54633> A_IWL<54632> A_IWL<54631> A_IWL<54630> A_IWL<54629> A_IWL<54628> A_IWL<54627> A_IWL<54626> A_IWL<54625> A_IWL<54624> A_IWL<54623> A_IWL<54622> A_IWL<54621> A_IWL<54620> A_IWL<54619> A_IWL<54618> A_IWL<54617> A_IWL<54616> A_IWL<54615> A_IWL<54614> A_IWL<54613> A_IWL<54612> A_IWL<54611> A_IWL<54610> A_IWL<54609> A_IWL<54608> A_IWL<54607> A_IWL<54606> A_IWL<54605> A_IWL<54604> A_IWL<54603> A_IWL<54602> A_IWL<54601> A_IWL<54600> A_IWL<54599> A_IWL<54598> A_IWL<54597> A_IWL<54596> A_IWL<54595> A_IWL<54594> A_IWL<54593> A_IWL<54592> A_IWL<54591> A_IWL<54590> A_IWL<54589> A_IWL<54588> A_IWL<54587> A_IWL<54586> A_IWL<54585> A_IWL<54584> A_IWL<54583> A_IWL<54582> A_IWL<54581> A_IWL<54580> A_IWL<54579> A_IWL<54578> A_IWL<54577> A_IWL<54576> A_IWL<54575> A_IWL<54574> A_IWL<54573> A_IWL<54572> A_IWL<54571> A_IWL<54570> A_IWL<54569> A_IWL<54568> A_IWL<54567> A_IWL<54566> A_IWL<54565> A_IWL<54564> A_IWL<54563> A_IWL<54562> A_IWL<54561> A_IWL<54560> A_IWL<54559> A_IWL<54558> A_IWL<54557> A_IWL<54556> A_IWL<54555> A_IWL<54554> A_IWL<54553> A_IWL<54552> A_IWL<54551> A_IWL<54550> A_IWL<54549> A_IWL<54548> A_IWL<54547> A_IWL<54546> A_IWL<54545> A_IWL<54544> A_IWL<54543> A_IWL<54542> A_IWL<54541> A_IWL<54540> A_IWL<54539> A_IWL<54538> A_IWL<54537> A_IWL<54536> A_IWL<54535> A_IWL<54534> A_IWL<54533> A_IWL<54532> A_IWL<54531> A_IWL<54530> A_IWL<54529> A_IWL<54528> A_IWL<54527> A_IWL<54526> A_IWL<54525> A_IWL<54524> A_IWL<54523> A_IWL<54522> A_IWL<54521> A_IWL<54520> A_IWL<54519> A_IWL<54518> A_IWL<54517> A_IWL<54516> A_IWL<54515> A_IWL<54514> A_IWL<54513> A_IWL<54512> A_IWL<54511> A_IWL<54510> A_IWL<54509> A_IWL<54508> A_IWL<54507> A_IWL<54506> A_IWL<54505> A_IWL<54504> A_IWL<54503> A_IWL<54502> A_IWL<54501> A_IWL<54500> A_IWL<54499> A_IWL<54498> A_IWL<54497> A_IWL<54496> A_IWL<54495> A_IWL<54494> A_IWL<54493> A_IWL<54492> A_IWL<54491> A_IWL<54490> A_IWL<54489> A_IWL<54488> A_IWL<54487> A_IWL<54486> A_IWL<54485> A_IWL<54484> A_IWL<54483> A_IWL<54482> A_IWL<54481> A_IWL<54480> A_IWL<54479> A_IWL<54478> A_IWL<54477> A_IWL<54476> A_IWL<54475> A_IWL<54474> A_IWL<54473> A_IWL<54472> A_IWL<54471> A_IWL<54470> A_IWL<54469> A_IWL<54468> A_IWL<54467> A_IWL<54466> A_IWL<54465> A_IWL<54464> A_IWL<54463> A_IWL<54462> A_IWL<54461> A_IWL<54460> A_IWL<54459> A_IWL<54458> A_IWL<54457> A_IWL<54456> A_IWL<54455> A_IWL<54454> A_IWL<54453> A_IWL<54452> A_IWL<54451> A_IWL<54450> A_IWL<54449> A_IWL<54448> A_IWL<54447> A_IWL<54446> A_IWL<54445> A_IWL<54444> A_IWL<54443> A_IWL<54442> A_IWL<54441> A_IWL<54440> A_IWL<54439> A_IWL<54438> A_IWL<54437> A_IWL<54436> A_IWL<54435> A_IWL<54434> A_IWL<54433> A_IWL<54432> A_IWL<54431> A_IWL<54430> A_IWL<54429> A_IWL<54428> A_IWL<54427> A_IWL<54426> A_IWL<54425> A_IWL<54424> A_IWL<54423> A_IWL<54422> A_IWL<54421> A_IWL<54420> A_IWL<54419> A_IWL<54418> A_IWL<54417> A_IWL<54416> A_IWL<54415> A_IWL<54414> A_IWL<54413> A_IWL<54412> A_IWL<54411> A_IWL<54410> A_IWL<54409> A_IWL<54408> A_IWL<54407> A_IWL<54406> A_IWL<54405> A_IWL<54404> A_IWL<54403> A_IWL<54402> A_IWL<54401> A_IWL<54400> A_IWL<54399> A_IWL<54398> A_IWL<54397> A_IWL<54396> A_IWL<54395> A_IWL<54394> A_IWL<54393> A_IWL<54392> A_IWL<54391> A_IWL<54390> A_IWL<54389> A_IWL<54388> A_IWL<54387> A_IWL<54386> A_IWL<54385> A_IWL<54384> A_IWL<54383> A_IWL<54382> A_IWL<54381> A_IWL<54380> A_IWL<54379> A_IWL<54378> A_IWL<54377> A_IWL<54376> A_IWL<54375> A_IWL<54374> A_IWL<54373> A_IWL<54372> A_IWL<54371> A_IWL<54370> A_IWL<54369> A_IWL<54368> A_IWL<54367> A_IWL<54366> A_IWL<54365> A_IWL<54364> A_IWL<54363> A_IWL<54362> A_IWL<54361> A_IWL<54360> A_IWL<54359> A_IWL<54358> A_IWL<54357> A_IWL<54356> A_IWL<54355> A_IWL<54354> A_IWL<54353> A_IWL<54352> A_IWL<54351> A_IWL<54350> A_IWL<54349> A_IWL<54348> A_IWL<54347> A_IWL<54346> A_IWL<54345> A_IWL<54344> A_IWL<54343> A_IWL<54342> A_IWL<54341> A_IWL<54340> A_IWL<54339> A_IWL<54338> A_IWL<54337> A_IWL<54336> A_IWL<54335> A_IWL<54334> A_IWL<54333> A_IWL<54332> A_IWL<54331> A_IWL<54330> A_IWL<54329> A_IWL<54328> A_IWL<54327> A_IWL<54326> A_IWL<54325> A_IWL<54324> A_IWL<54323> A_IWL<54322> A_IWL<54321> A_IWL<54320> A_IWL<54319> A_IWL<54318> A_IWL<54317> A_IWL<54316> A_IWL<54315> A_IWL<54314> A_IWL<54313> A_IWL<54312> A_IWL<54311> A_IWL<54310> A_IWL<54309> A_IWL<54308> A_IWL<54307> A_IWL<54306> A_IWL<54305> A_IWL<54304> A_IWL<54303> A_IWL<54302> A_IWL<54301> A_IWL<54300> A_IWL<54299> A_IWL<54298> A_IWL<54297> A_IWL<54296> A_IWL<54295> A_IWL<54294> A_IWL<54293> A_IWL<54292> A_IWL<54291> A_IWL<54290> A_IWL<54289> A_IWL<54288> A_IWL<54287> A_IWL<54286> A_IWL<54285> A_IWL<54284> A_IWL<54283> A_IWL<54282> A_IWL<54281> A_IWL<54280> A_IWL<54279> A_IWL<54278> A_IWL<54277> A_IWL<54276> A_IWL<54275> A_IWL<54274> A_IWL<54273> A_IWL<54272> VDD_CORE VSS / RM_IHPSG13_8192x32_c4_1P_COLUMN_pcell_0 +XCOL<105> A_BLC<211> A_BLC<210> A_BLC_TOP<211> A_BLC_TOP<210> A_BLT<211> A_BLT<210> A_BLT_TOP<211> A_BLT_TOP<210> A_IWL<53759> A_IWL<53758> A_IWL<53757> A_IWL<53756> A_IWL<53755> A_IWL<53754> A_IWL<53753> A_IWL<53752> A_IWL<53751> A_IWL<53750> A_IWL<53749> A_IWL<53748> A_IWL<53747> A_IWL<53746> A_IWL<53745> A_IWL<53744> A_IWL<53743> A_IWL<53742> A_IWL<53741> A_IWL<53740> A_IWL<53739> A_IWL<53738> A_IWL<53737> A_IWL<53736> A_IWL<53735> A_IWL<53734> A_IWL<53733> A_IWL<53732> A_IWL<53731> A_IWL<53730> A_IWL<53729> A_IWL<53728> A_IWL<53727> A_IWL<53726> A_IWL<53725> A_IWL<53724> A_IWL<53723> A_IWL<53722> A_IWL<53721> A_IWL<53720> A_IWL<53719> A_IWL<53718> A_IWL<53717> A_IWL<53716> A_IWL<53715> A_IWL<53714> A_IWL<53713> A_IWL<53712> A_IWL<53711> A_IWL<53710> A_IWL<53709> A_IWL<53708> A_IWL<53707> A_IWL<53706> A_IWL<53705> A_IWL<53704> A_IWL<53703> A_IWL<53702> A_IWL<53701> A_IWL<53700> A_IWL<53699> A_IWL<53698> A_IWL<53697> A_IWL<53696> A_IWL<53695> A_IWL<53694> A_IWL<53693> A_IWL<53692> A_IWL<53691> A_IWL<53690> A_IWL<53689> A_IWL<53688> A_IWL<53687> A_IWL<53686> A_IWL<53685> A_IWL<53684> A_IWL<53683> A_IWL<53682> A_IWL<53681> A_IWL<53680> A_IWL<53679> A_IWL<53678> A_IWL<53677> A_IWL<53676> A_IWL<53675> A_IWL<53674> A_IWL<53673> A_IWL<53672> A_IWL<53671> A_IWL<53670> A_IWL<53669> A_IWL<53668> A_IWL<53667> A_IWL<53666> A_IWL<53665> A_IWL<53664> A_IWL<53663> A_IWL<53662> A_IWL<53661> A_IWL<53660> A_IWL<53659> A_IWL<53658> A_IWL<53657> A_IWL<53656> A_IWL<53655> A_IWL<53654> A_IWL<53653> A_IWL<53652> A_IWL<53651> A_IWL<53650> A_IWL<53649> A_IWL<53648> A_IWL<53647> A_IWL<53646> A_IWL<53645> A_IWL<53644> A_IWL<53643> A_IWL<53642> A_IWL<53641> A_IWL<53640> A_IWL<53639> A_IWL<53638> A_IWL<53637> A_IWL<53636> A_IWL<53635> A_IWL<53634> A_IWL<53633> A_IWL<53632> A_IWL<53631> A_IWL<53630> A_IWL<53629> A_IWL<53628> A_IWL<53627> A_IWL<53626> A_IWL<53625> A_IWL<53624> A_IWL<53623> A_IWL<53622> A_IWL<53621> A_IWL<53620> A_IWL<53619> A_IWL<53618> A_IWL<53617> A_IWL<53616> A_IWL<53615> A_IWL<53614> A_IWL<53613> A_IWL<53612> A_IWL<53611> A_IWL<53610> A_IWL<53609> A_IWL<53608> A_IWL<53607> A_IWL<53606> A_IWL<53605> A_IWL<53604> A_IWL<53603> A_IWL<53602> A_IWL<53601> A_IWL<53600> A_IWL<53599> A_IWL<53598> A_IWL<53597> A_IWL<53596> A_IWL<53595> A_IWL<53594> A_IWL<53593> A_IWL<53592> A_IWL<53591> A_IWL<53590> A_IWL<53589> A_IWL<53588> A_IWL<53587> A_IWL<53586> A_IWL<53585> A_IWL<53584> A_IWL<53583> A_IWL<53582> A_IWL<53581> A_IWL<53580> A_IWL<53579> A_IWL<53578> A_IWL<53577> A_IWL<53576> A_IWL<53575> A_IWL<53574> A_IWL<53573> A_IWL<53572> A_IWL<53571> A_IWL<53570> A_IWL<53569> A_IWL<53568> A_IWL<53567> A_IWL<53566> A_IWL<53565> A_IWL<53564> A_IWL<53563> A_IWL<53562> A_IWL<53561> A_IWL<53560> A_IWL<53559> A_IWL<53558> A_IWL<53557> A_IWL<53556> A_IWL<53555> A_IWL<53554> A_IWL<53553> A_IWL<53552> A_IWL<53551> A_IWL<53550> A_IWL<53549> A_IWL<53548> A_IWL<53547> A_IWL<53546> A_IWL<53545> A_IWL<53544> A_IWL<53543> A_IWL<53542> A_IWL<53541> A_IWL<53540> A_IWL<53539> A_IWL<53538> A_IWL<53537> A_IWL<53536> A_IWL<53535> A_IWL<53534> A_IWL<53533> A_IWL<53532> A_IWL<53531> A_IWL<53530> A_IWL<53529> A_IWL<53528> A_IWL<53527> A_IWL<53526> A_IWL<53525> A_IWL<53524> A_IWL<53523> A_IWL<53522> A_IWL<53521> A_IWL<53520> A_IWL<53519> A_IWL<53518> A_IWL<53517> A_IWL<53516> A_IWL<53515> A_IWL<53514> A_IWL<53513> A_IWL<53512> A_IWL<53511> A_IWL<53510> A_IWL<53509> A_IWL<53508> A_IWL<53507> A_IWL<53506> A_IWL<53505> A_IWL<53504> A_IWL<53503> A_IWL<53502> A_IWL<53501> A_IWL<53500> A_IWL<53499> A_IWL<53498> A_IWL<53497> A_IWL<53496> A_IWL<53495> A_IWL<53494> A_IWL<53493> A_IWL<53492> A_IWL<53491> A_IWL<53490> A_IWL<53489> A_IWL<53488> A_IWL<53487> A_IWL<53486> A_IWL<53485> A_IWL<53484> A_IWL<53483> A_IWL<53482> A_IWL<53481> A_IWL<53480> A_IWL<53479> A_IWL<53478> A_IWL<53477> A_IWL<53476> A_IWL<53475> A_IWL<53474> A_IWL<53473> A_IWL<53472> A_IWL<53471> A_IWL<53470> A_IWL<53469> A_IWL<53468> A_IWL<53467> A_IWL<53466> A_IWL<53465> A_IWL<53464> A_IWL<53463> A_IWL<53462> A_IWL<53461> A_IWL<53460> A_IWL<53459> A_IWL<53458> A_IWL<53457> A_IWL<53456> A_IWL<53455> A_IWL<53454> A_IWL<53453> A_IWL<53452> A_IWL<53451> A_IWL<53450> A_IWL<53449> A_IWL<53448> A_IWL<53447> A_IWL<53446> A_IWL<53445> A_IWL<53444> A_IWL<53443> A_IWL<53442> A_IWL<53441> A_IWL<53440> A_IWL<53439> A_IWL<53438> A_IWL<53437> A_IWL<53436> A_IWL<53435> A_IWL<53434> A_IWL<53433> A_IWL<53432> A_IWL<53431> A_IWL<53430> A_IWL<53429> A_IWL<53428> A_IWL<53427> A_IWL<53426> A_IWL<53425> A_IWL<53424> A_IWL<53423> A_IWL<53422> A_IWL<53421> A_IWL<53420> A_IWL<53419> A_IWL<53418> A_IWL<53417> A_IWL<53416> A_IWL<53415> A_IWL<53414> A_IWL<53413> A_IWL<53412> A_IWL<53411> A_IWL<53410> A_IWL<53409> A_IWL<53408> A_IWL<53407> A_IWL<53406> A_IWL<53405> A_IWL<53404> A_IWL<53403> A_IWL<53402> A_IWL<53401> A_IWL<53400> A_IWL<53399> A_IWL<53398> A_IWL<53397> A_IWL<53396> A_IWL<53395> A_IWL<53394> A_IWL<53393> A_IWL<53392> A_IWL<53391> A_IWL<53390> A_IWL<53389> A_IWL<53388> A_IWL<53387> A_IWL<53386> A_IWL<53385> A_IWL<53384> A_IWL<53383> A_IWL<53382> A_IWL<53381> A_IWL<53380> A_IWL<53379> A_IWL<53378> A_IWL<53377> A_IWL<53376> A_IWL<53375> A_IWL<53374> A_IWL<53373> A_IWL<53372> A_IWL<53371> A_IWL<53370> A_IWL<53369> A_IWL<53368> A_IWL<53367> A_IWL<53366> A_IWL<53365> A_IWL<53364> A_IWL<53363> A_IWL<53362> A_IWL<53361> A_IWL<53360> A_IWL<53359> A_IWL<53358> A_IWL<53357> A_IWL<53356> A_IWL<53355> A_IWL<53354> A_IWL<53353> A_IWL<53352> A_IWL<53351> A_IWL<53350> A_IWL<53349> A_IWL<53348> A_IWL<53347> A_IWL<53346> A_IWL<53345> A_IWL<53344> A_IWL<53343> A_IWL<53342> A_IWL<53341> A_IWL<53340> A_IWL<53339> A_IWL<53338> A_IWL<53337> A_IWL<53336> A_IWL<53335> A_IWL<53334> A_IWL<53333> A_IWL<53332> A_IWL<53331> A_IWL<53330> A_IWL<53329> A_IWL<53328> A_IWL<53327> A_IWL<53326> A_IWL<53325> A_IWL<53324> A_IWL<53323> A_IWL<53322> A_IWL<53321> A_IWL<53320> A_IWL<53319> A_IWL<53318> A_IWL<53317> A_IWL<53316> A_IWL<53315> A_IWL<53314> A_IWL<53313> A_IWL<53312> A_IWL<53311> A_IWL<53310> A_IWL<53309> A_IWL<53308> A_IWL<53307> A_IWL<53306> A_IWL<53305> A_IWL<53304> A_IWL<53303> A_IWL<53302> A_IWL<53301> A_IWL<53300> A_IWL<53299> A_IWL<53298> A_IWL<53297> A_IWL<53296> A_IWL<53295> A_IWL<53294> A_IWL<53293> A_IWL<53292> A_IWL<53291> A_IWL<53290> A_IWL<53289> A_IWL<53288> A_IWL<53287> A_IWL<53286> A_IWL<53285> A_IWL<53284> A_IWL<53283> A_IWL<53282> A_IWL<53281> A_IWL<53280> A_IWL<53279> A_IWL<53278> A_IWL<53277> A_IWL<53276> A_IWL<53275> A_IWL<53274> A_IWL<53273> A_IWL<53272> A_IWL<53271> A_IWL<53270> A_IWL<53269> A_IWL<53268> A_IWL<53267> A_IWL<53266> A_IWL<53265> A_IWL<53264> A_IWL<53263> A_IWL<53262> A_IWL<53261> A_IWL<53260> A_IWL<53259> A_IWL<53258> A_IWL<53257> A_IWL<53256> A_IWL<53255> A_IWL<53254> A_IWL<53253> A_IWL<53252> A_IWL<53251> A_IWL<53250> A_IWL<53249> A_IWL<53248> A_IWL<54271> A_IWL<54270> A_IWL<54269> A_IWL<54268> A_IWL<54267> A_IWL<54266> A_IWL<54265> A_IWL<54264> A_IWL<54263> A_IWL<54262> A_IWL<54261> A_IWL<54260> A_IWL<54259> A_IWL<54258> A_IWL<54257> A_IWL<54256> A_IWL<54255> A_IWL<54254> A_IWL<54253> A_IWL<54252> A_IWL<54251> A_IWL<54250> A_IWL<54249> A_IWL<54248> A_IWL<54247> A_IWL<54246> A_IWL<54245> A_IWL<54244> A_IWL<54243> A_IWL<54242> A_IWL<54241> A_IWL<54240> A_IWL<54239> A_IWL<54238> A_IWL<54237> A_IWL<54236> A_IWL<54235> A_IWL<54234> A_IWL<54233> A_IWL<54232> A_IWL<54231> A_IWL<54230> A_IWL<54229> A_IWL<54228> A_IWL<54227> A_IWL<54226> A_IWL<54225> A_IWL<54224> A_IWL<54223> A_IWL<54222> A_IWL<54221> A_IWL<54220> A_IWL<54219> A_IWL<54218> A_IWL<54217> A_IWL<54216> A_IWL<54215> A_IWL<54214> A_IWL<54213> A_IWL<54212> A_IWL<54211> A_IWL<54210> A_IWL<54209> A_IWL<54208> A_IWL<54207> A_IWL<54206> A_IWL<54205> A_IWL<54204> A_IWL<54203> A_IWL<54202> A_IWL<54201> A_IWL<54200> A_IWL<54199> A_IWL<54198> A_IWL<54197> A_IWL<54196> A_IWL<54195> A_IWL<54194> A_IWL<54193> A_IWL<54192> A_IWL<54191> A_IWL<54190> A_IWL<54189> A_IWL<54188> A_IWL<54187> A_IWL<54186> A_IWL<54185> A_IWL<54184> A_IWL<54183> A_IWL<54182> A_IWL<54181> A_IWL<54180> A_IWL<54179> A_IWL<54178> A_IWL<54177> A_IWL<54176> A_IWL<54175> A_IWL<54174> A_IWL<54173> A_IWL<54172> A_IWL<54171> A_IWL<54170> A_IWL<54169> A_IWL<54168> A_IWL<54167> A_IWL<54166> A_IWL<54165> A_IWL<54164> A_IWL<54163> A_IWL<54162> A_IWL<54161> A_IWL<54160> A_IWL<54159> A_IWL<54158> A_IWL<54157> A_IWL<54156> A_IWL<54155> A_IWL<54154> A_IWL<54153> A_IWL<54152> A_IWL<54151> A_IWL<54150> A_IWL<54149> A_IWL<54148> A_IWL<54147> A_IWL<54146> A_IWL<54145> A_IWL<54144> A_IWL<54143> A_IWL<54142> A_IWL<54141> A_IWL<54140> A_IWL<54139> A_IWL<54138> A_IWL<54137> A_IWL<54136> A_IWL<54135> A_IWL<54134> A_IWL<54133> A_IWL<54132> A_IWL<54131> A_IWL<54130> A_IWL<54129> A_IWL<54128> A_IWL<54127> A_IWL<54126> A_IWL<54125> A_IWL<54124> A_IWL<54123> A_IWL<54122> A_IWL<54121> A_IWL<54120> A_IWL<54119> A_IWL<54118> A_IWL<54117> A_IWL<54116> A_IWL<54115> A_IWL<54114> A_IWL<54113> A_IWL<54112> A_IWL<54111> A_IWL<54110> A_IWL<54109> A_IWL<54108> A_IWL<54107> A_IWL<54106> A_IWL<54105> A_IWL<54104> A_IWL<54103> A_IWL<54102> A_IWL<54101> A_IWL<54100> A_IWL<54099> A_IWL<54098> A_IWL<54097> A_IWL<54096> A_IWL<54095> A_IWL<54094> A_IWL<54093> A_IWL<54092> A_IWL<54091> A_IWL<54090> A_IWL<54089> A_IWL<54088> A_IWL<54087> A_IWL<54086> A_IWL<54085> A_IWL<54084> A_IWL<54083> A_IWL<54082> A_IWL<54081> A_IWL<54080> A_IWL<54079> A_IWL<54078> A_IWL<54077> A_IWL<54076> A_IWL<54075> A_IWL<54074> A_IWL<54073> A_IWL<54072> A_IWL<54071> A_IWL<54070> A_IWL<54069> A_IWL<54068> A_IWL<54067> A_IWL<54066> A_IWL<54065> A_IWL<54064> A_IWL<54063> A_IWL<54062> A_IWL<54061> A_IWL<54060> A_IWL<54059> A_IWL<54058> A_IWL<54057> A_IWL<54056> A_IWL<54055> A_IWL<54054> A_IWL<54053> A_IWL<54052> A_IWL<54051> A_IWL<54050> A_IWL<54049> A_IWL<54048> A_IWL<54047> A_IWL<54046> A_IWL<54045> A_IWL<54044> A_IWL<54043> A_IWL<54042> A_IWL<54041> A_IWL<54040> A_IWL<54039> A_IWL<54038> A_IWL<54037> A_IWL<54036> A_IWL<54035> A_IWL<54034> A_IWL<54033> A_IWL<54032> A_IWL<54031> A_IWL<54030> A_IWL<54029> A_IWL<54028> A_IWL<54027> A_IWL<54026> A_IWL<54025> A_IWL<54024> A_IWL<54023> A_IWL<54022> A_IWL<54021> A_IWL<54020> A_IWL<54019> A_IWL<54018> A_IWL<54017> A_IWL<54016> A_IWL<54015> A_IWL<54014> A_IWL<54013> A_IWL<54012> A_IWL<54011> A_IWL<54010> A_IWL<54009> A_IWL<54008> A_IWL<54007> A_IWL<54006> A_IWL<54005> A_IWL<54004> A_IWL<54003> A_IWL<54002> A_IWL<54001> A_IWL<54000> A_IWL<53999> A_IWL<53998> A_IWL<53997> A_IWL<53996> A_IWL<53995> A_IWL<53994> A_IWL<53993> A_IWL<53992> A_IWL<53991> A_IWL<53990> A_IWL<53989> A_IWL<53988> A_IWL<53987> A_IWL<53986> A_IWL<53985> A_IWL<53984> A_IWL<53983> A_IWL<53982> A_IWL<53981> A_IWL<53980> A_IWL<53979> A_IWL<53978> A_IWL<53977> A_IWL<53976> A_IWL<53975> A_IWL<53974> A_IWL<53973> A_IWL<53972> A_IWL<53971> A_IWL<53970> A_IWL<53969> A_IWL<53968> A_IWL<53967> A_IWL<53966> A_IWL<53965> A_IWL<53964> A_IWL<53963> A_IWL<53962> A_IWL<53961> A_IWL<53960> A_IWL<53959> A_IWL<53958> A_IWL<53957> A_IWL<53956> A_IWL<53955> A_IWL<53954> A_IWL<53953> A_IWL<53952> A_IWL<53951> A_IWL<53950> A_IWL<53949> A_IWL<53948> A_IWL<53947> A_IWL<53946> A_IWL<53945> A_IWL<53944> A_IWL<53943> A_IWL<53942> A_IWL<53941> A_IWL<53940> A_IWL<53939> A_IWL<53938> A_IWL<53937> A_IWL<53936> A_IWL<53935> A_IWL<53934> A_IWL<53933> A_IWL<53932> A_IWL<53931> A_IWL<53930> A_IWL<53929> A_IWL<53928> A_IWL<53927> A_IWL<53926> A_IWL<53925> A_IWL<53924> A_IWL<53923> A_IWL<53922> A_IWL<53921> A_IWL<53920> A_IWL<53919> A_IWL<53918> A_IWL<53917> A_IWL<53916> A_IWL<53915> A_IWL<53914> A_IWL<53913> A_IWL<53912> A_IWL<53911> A_IWL<53910> A_IWL<53909> A_IWL<53908> A_IWL<53907> A_IWL<53906> A_IWL<53905> A_IWL<53904> A_IWL<53903> A_IWL<53902> A_IWL<53901> A_IWL<53900> A_IWL<53899> A_IWL<53898> A_IWL<53897> A_IWL<53896> A_IWL<53895> A_IWL<53894> A_IWL<53893> A_IWL<53892> A_IWL<53891> A_IWL<53890> A_IWL<53889> A_IWL<53888> A_IWL<53887> A_IWL<53886> A_IWL<53885> A_IWL<53884> A_IWL<53883> A_IWL<53882> A_IWL<53881> A_IWL<53880> A_IWL<53879> A_IWL<53878> A_IWL<53877> A_IWL<53876> A_IWL<53875> A_IWL<53874> A_IWL<53873> A_IWL<53872> A_IWL<53871> A_IWL<53870> A_IWL<53869> A_IWL<53868> A_IWL<53867> A_IWL<53866> A_IWL<53865> A_IWL<53864> A_IWL<53863> A_IWL<53862> A_IWL<53861> A_IWL<53860> A_IWL<53859> A_IWL<53858> A_IWL<53857> A_IWL<53856> A_IWL<53855> A_IWL<53854> A_IWL<53853> A_IWL<53852> A_IWL<53851> A_IWL<53850> A_IWL<53849> A_IWL<53848> A_IWL<53847> A_IWL<53846> A_IWL<53845> A_IWL<53844> A_IWL<53843> A_IWL<53842> A_IWL<53841> A_IWL<53840> A_IWL<53839> A_IWL<53838> A_IWL<53837> A_IWL<53836> A_IWL<53835> A_IWL<53834> A_IWL<53833> A_IWL<53832> A_IWL<53831> A_IWL<53830> A_IWL<53829> A_IWL<53828> A_IWL<53827> A_IWL<53826> A_IWL<53825> A_IWL<53824> A_IWL<53823> A_IWL<53822> A_IWL<53821> A_IWL<53820> A_IWL<53819> A_IWL<53818> A_IWL<53817> A_IWL<53816> A_IWL<53815> A_IWL<53814> A_IWL<53813> A_IWL<53812> A_IWL<53811> A_IWL<53810> A_IWL<53809> A_IWL<53808> A_IWL<53807> A_IWL<53806> A_IWL<53805> A_IWL<53804> A_IWL<53803> A_IWL<53802> A_IWL<53801> A_IWL<53800> A_IWL<53799> A_IWL<53798> A_IWL<53797> A_IWL<53796> A_IWL<53795> A_IWL<53794> A_IWL<53793> A_IWL<53792> A_IWL<53791> A_IWL<53790> A_IWL<53789> A_IWL<53788> A_IWL<53787> A_IWL<53786> A_IWL<53785> A_IWL<53784> A_IWL<53783> A_IWL<53782> A_IWL<53781> A_IWL<53780> A_IWL<53779> A_IWL<53778> A_IWL<53777> A_IWL<53776> A_IWL<53775> A_IWL<53774> A_IWL<53773> A_IWL<53772> A_IWL<53771> A_IWL<53770> A_IWL<53769> A_IWL<53768> A_IWL<53767> A_IWL<53766> A_IWL<53765> A_IWL<53764> A_IWL<53763> A_IWL<53762> A_IWL<53761> A_IWL<53760> VDD_CORE VSS / RM_IHPSG13_8192x32_c4_1P_COLUMN_pcell_0 +XCOL<104> A_BLC<209> A_BLC<208> A_BLC_TOP<209> A_BLC_TOP<208> A_BLT<209> A_BLT<208> A_BLT_TOP<209> A_BLT_TOP<208> A_IWL<53247> A_IWL<53246> A_IWL<53245> A_IWL<53244> A_IWL<53243> A_IWL<53242> A_IWL<53241> A_IWL<53240> A_IWL<53239> A_IWL<53238> A_IWL<53237> A_IWL<53236> A_IWL<53235> A_IWL<53234> A_IWL<53233> A_IWL<53232> A_IWL<53231> A_IWL<53230> A_IWL<53229> A_IWL<53228> A_IWL<53227> A_IWL<53226> A_IWL<53225> A_IWL<53224> A_IWL<53223> A_IWL<53222> A_IWL<53221> A_IWL<53220> A_IWL<53219> A_IWL<53218> A_IWL<53217> A_IWL<53216> A_IWL<53215> A_IWL<53214> A_IWL<53213> A_IWL<53212> A_IWL<53211> A_IWL<53210> A_IWL<53209> A_IWL<53208> A_IWL<53207> A_IWL<53206> A_IWL<53205> A_IWL<53204> A_IWL<53203> A_IWL<53202> A_IWL<53201> A_IWL<53200> A_IWL<53199> A_IWL<53198> A_IWL<53197> A_IWL<53196> A_IWL<53195> A_IWL<53194> A_IWL<53193> A_IWL<53192> A_IWL<53191> A_IWL<53190> A_IWL<53189> A_IWL<53188> A_IWL<53187> A_IWL<53186> A_IWL<53185> A_IWL<53184> A_IWL<53183> A_IWL<53182> A_IWL<53181> A_IWL<53180> A_IWL<53179> A_IWL<53178> A_IWL<53177> A_IWL<53176> A_IWL<53175> A_IWL<53174> A_IWL<53173> A_IWL<53172> A_IWL<53171> A_IWL<53170> A_IWL<53169> A_IWL<53168> A_IWL<53167> A_IWL<53166> A_IWL<53165> A_IWL<53164> A_IWL<53163> A_IWL<53162> A_IWL<53161> A_IWL<53160> A_IWL<53159> A_IWL<53158> A_IWL<53157> A_IWL<53156> A_IWL<53155> A_IWL<53154> A_IWL<53153> A_IWL<53152> A_IWL<53151> A_IWL<53150> A_IWL<53149> A_IWL<53148> A_IWL<53147> A_IWL<53146> A_IWL<53145> A_IWL<53144> A_IWL<53143> A_IWL<53142> A_IWL<53141> A_IWL<53140> A_IWL<53139> A_IWL<53138> A_IWL<53137> A_IWL<53136> A_IWL<53135> A_IWL<53134> A_IWL<53133> A_IWL<53132> A_IWL<53131> A_IWL<53130> A_IWL<53129> A_IWL<53128> A_IWL<53127> A_IWL<53126> A_IWL<53125> A_IWL<53124> A_IWL<53123> A_IWL<53122> A_IWL<53121> A_IWL<53120> A_IWL<53119> A_IWL<53118> A_IWL<53117> A_IWL<53116> A_IWL<53115> A_IWL<53114> A_IWL<53113> A_IWL<53112> A_IWL<53111> A_IWL<53110> A_IWL<53109> A_IWL<53108> A_IWL<53107> A_IWL<53106> A_IWL<53105> A_IWL<53104> A_IWL<53103> A_IWL<53102> A_IWL<53101> A_IWL<53100> A_IWL<53099> A_IWL<53098> A_IWL<53097> A_IWL<53096> A_IWL<53095> A_IWL<53094> A_IWL<53093> A_IWL<53092> A_IWL<53091> A_IWL<53090> A_IWL<53089> A_IWL<53088> A_IWL<53087> A_IWL<53086> A_IWL<53085> A_IWL<53084> A_IWL<53083> A_IWL<53082> A_IWL<53081> A_IWL<53080> A_IWL<53079> A_IWL<53078> A_IWL<53077> A_IWL<53076> A_IWL<53075> A_IWL<53074> A_IWL<53073> A_IWL<53072> A_IWL<53071> A_IWL<53070> A_IWL<53069> A_IWL<53068> A_IWL<53067> A_IWL<53066> A_IWL<53065> A_IWL<53064> A_IWL<53063> A_IWL<53062> A_IWL<53061> A_IWL<53060> A_IWL<53059> A_IWL<53058> A_IWL<53057> A_IWL<53056> A_IWL<53055> A_IWL<53054> A_IWL<53053> A_IWL<53052> A_IWL<53051> A_IWL<53050> A_IWL<53049> A_IWL<53048> A_IWL<53047> A_IWL<53046> A_IWL<53045> A_IWL<53044> A_IWL<53043> A_IWL<53042> A_IWL<53041> A_IWL<53040> A_IWL<53039> A_IWL<53038> A_IWL<53037> A_IWL<53036> A_IWL<53035> A_IWL<53034> A_IWL<53033> A_IWL<53032> A_IWL<53031> A_IWL<53030> A_IWL<53029> A_IWL<53028> A_IWL<53027> A_IWL<53026> A_IWL<53025> A_IWL<53024> A_IWL<53023> A_IWL<53022> A_IWL<53021> A_IWL<53020> A_IWL<53019> A_IWL<53018> A_IWL<53017> A_IWL<53016> A_IWL<53015> A_IWL<53014> A_IWL<53013> A_IWL<53012> A_IWL<53011> A_IWL<53010> A_IWL<53009> A_IWL<53008> A_IWL<53007> A_IWL<53006> A_IWL<53005> A_IWL<53004> A_IWL<53003> A_IWL<53002> A_IWL<53001> A_IWL<53000> A_IWL<52999> A_IWL<52998> A_IWL<52997> A_IWL<52996> A_IWL<52995> A_IWL<52994> A_IWL<52993> A_IWL<52992> A_IWL<52991> A_IWL<52990> A_IWL<52989> A_IWL<52988> A_IWL<52987> A_IWL<52986> A_IWL<52985> A_IWL<52984> A_IWL<52983> A_IWL<52982> A_IWL<52981> A_IWL<52980> A_IWL<52979> A_IWL<52978> A_IWL<52977> A_IWL<52976> A_IWL<52975> A_IWL<52974> A_IWL<52973> A_IWL<52972> A_IWL<52971> A_IWL<52970> A_IWL<52969> A_IWL<52968> A_IWL<52967> A_IWL<52966> A_IWL<52965> A_IWL<52964> A_IWL<52963> A_IWL<52962> A_IWL<52961> A_IWL<52960> A_IWL<52959> A_IWL<52958> A_IWL<52957> A_IWL<52956> A_IWL<52955> A_IWL<52954> A_IWL<52953> A_IWL<52952> A_IWL<52951> A_IWL<52950> A_IWL<52949> A_IWL<52948> A_IWL<52947> A_IWL<52946> A_IWL<52945> A_IWL<52944> A_IWL<52943> A_IWL<52942> A_IWL<52941> A_IWL<52940> A_IWL<52939> A_IWL<52938> A_IWL<52937> A_IWL<52936> A_IWL<52935> A_IWL<52934> A_IWL<52933> A_IWL<52932> A_IWL<52931> A_IWL<52930> A_IWL<52929> A_IWL<52928> A_IWL<52927> A_IWL<52926> A_IWL<52925> A_IWL<52924> A_IWL<52923> A_IWL<52922> A_IWL<52921> A_IWL<52920> A_IWL<52919> A_IWL<52918> A_IWL<52917> A_IWL<52916> A_IWL<52915> A_IWL<52914> A_IWL<52913> A_IWL<52912> A_IWL<52911> A_IWL<52910> A_IWL<52909> A_IWL<52908> A_IWL<52907> A_IWL<52906> A_IWL<52905> A_IWL<52904> A_IWL<52903> A_IWL<52902> A_IWL<52901> A_IWL<52900> A_IWL<52899> A_IWL<52898> A_IWL<52897> A_IWL<52896> A_IWL<52895> A_IWL<52894> A_IWL<52893> A_IWL<52892> A_IWL<52891> A_IWL<52890> A_IWL<52889> A_IWL<52888> A_IWL<52887> A_IWL<52886> A_IWL<52885> A_IWL<52884> A_IWL<52883> A_IWL<52882> A_IWL<52881> A_IWL<52880> A_IWL<52879> A_IWL<52878> A_IWL<52877> A_IWL<52876> A_IWL<52875> A_IWL<52874> A_IWL<52873> A_IWL<52872> A_IWL<52871> A_IWL<52870> A_IWL<52869> A_IWL<52868> A_IWL<52867> A_IWL<52866> A_IWL<52865> A_IWL<52864> A_IWL<52863> A_IWL<52862> A_IWL<52861> A_IWL<52860> A_IWL<52859> A_IWL<52858> A_IWL<52857> A_IWL<52856> A_IWL<52855> A_IWL<52854> A_IWL<52853> A_IWL<52852> A_IWL<52851> A_IWL<52850> A_IWL<52849> A_IWL<52848> A_IWL<52847> A_IWL<52846> A_IWL<52845> A_IWL<52844> A_IWL<52843> A_IWL<52842> A_IWL<52841> A_IWL<52840> A_IWL<52839> A_IWL<52838> A_IWL<52837> A_IWL<52836> A_IWL<52835> A_IWL<52834> A_IWL<52833> A_IWL<52832> A_IWL<52831> A_IWL<52830> A_IWL<52829> A_IWL<52828> A_IWL<52827> A_IWL<52826> A_IWL<52825> A_IWL<52824> A_IWL<52823> A_IWL<52822> A_IWL<52821> A_IWL<52820> A_IWL<52819> A_IWL<52818> A_IWL<52817> A_IWL<52816> A_IWL<52815> A_IWL<52814> A_IWL<52813> A_IWL<52812> A_IWL<52811> A_IWL<52810> A_IWL<52809> A_IWL<52808> A_IWL<52807> A_IWL<52806> A_IWL<52805> A_IWL<52804> A_IWL<52803> A_IWL<52802> A_IWL<52801> A_IWL<52800> A_IWL<52799> A_IWL<52798> A_IWL<52797> A_IWL<52796> A_IWL<52795> A_IWL<52794> A_IWL<52793> A_IWL<52792> A_IWL<52791> A_IWL<52790> A_IWL<52789> A_IWL<52788> A_IWL<52787> A_IWL<52786> A_IWL<52785> A_IWL<52784> A_IWL<52783> A_IWL<52782> A_IWL<52781> A_IWL<52780> A_IWL<52779> A_IWL<52778> A_IWL<52777> A_IWL<52776> A_IWL<52775> A_IWL<52774> A_IWL<52773> A_IWL<52772> A_IWL<52771> A_IWL<52770> A_IWL<52769> A_IWL<52768> A_IWL<52767> A_IWL<52766> A_IWL<52765> A_IWL<52764> A_IWL<52763> A_IWL<52762> A_IWL<52761> A_IWL<52760> A_IWL<52759> A_IWL<52758> A_IWL<52757> A_IWL<52756> A_IWL<52755> A_IWL<52754> A_IWL<52753> A_IWL<52752> A_IWL<52751> A_IWL<52750> A_IWL<52749> A_IWL<52748> A_IWL<52747> A_IWL<52746> A_IWL<52745> A_IWL<52744> A_IWL<52743> A_IWL<52742> A_IWL<52741> A_IWL<52740> A_IWL<52739> A_IWL<52738> A_IWL<52737> A_IWL<52736> A_IWL<53759> A_IWL<53758> A_IWL<53757> A_IWL<53756> A_IWL<53755> A_IWL<53754> A_IWL<53753> A_IWL<53752> A_IWL<53751> A_IWL<53750> A_IWL<53749> A_IWL<53748> A_IWL<53747> A_IWL<53746> A_IWL<53745> A_IWL<53744> A_IWL<53743> A_IWL<53742> A_IWL<53741> A_IWL<53740> A_IWL<53739> A_IWL<53738> A_IWL<53737> A_IWL<53736> A_IWL<53735> A_IWL<53734> A_IWL<53733> A_IWL<53732> A_IWL<53731> A_IWL<53730> A_IWL<53729> A_IWL<53728> A_IWL<53727> A_IWL<53726> A_IWL<53725> A_IWL<53724> A_IWL<53723> A_IWL<53722> A_IWL<53721> A_IWL<53720> A_IWL<53719> A_IWL<53718> A_IWL<53717> A_IWL<53716> A_IWL<53715> A_IWL<53714> A_IWL<53713> A_IWL<53712> A_IWL<53711> A_IWL<53710> A_IWL<53709> A_IWL<53708> A_IWL<53707> A_IWL<53706> A_IWL<53705> A_IWL<53704> A_IWL<53703> A_IWL<53702> A_IWL<53701> A_IWL<53700> A_IWL<53699> A_IWL<53698> A_IWL<53697> A_IWL<53696> A_IWL<53695> A_IWL<53694> A_IWL<53693> A_IWL<53692> A_IWL<53691> A_IWL<53690> A_IWL<53689> A_IWL<53688> A_IWL<53687> A_IWL<53686> A_IWL<53685> A_IWL<53684> A_IWL<53683> A_IWL<53682> A_IWL<53681> A_IWL<53680> A_IWL<53679> A_IWL<53678> A_IWL<53677> A_IWL<53676> A_IWL<53675> A_IWL<53674> A_IWL<53673> A_IWL<53672> A_IWL<53671> A_IWL<53670> A_IWL<53669> A_IWL<53668> A_IWL<53667> A_IWL<53666> A_IWL<53665> A_IWL<53664> A_IWL<53663> A_IWL<53662> A_IWL<53661> A_IWL<53660> A_IWL<53659> A_IWL<53658> A_IWL<53657> A_IWL<53656> A_IWL<53655> A_IWL<53654> A_IWL<53653> A_IWL<53652> A_IWL<53651> A_IWL<53650> A_IWL<53649> A_IWL<53648> A_IWL<53647> A_IWL<53646> A_IWL<53645> A_IWL<53644> A_IWL<53643> A_IWL<53642> A_IWL<53641> A_IWL<53640> A_IWL<53639> A_IWL<53638> A_IWL<53637> A_IWL<53636> A_IWL<53635> A_IWL<53634> A_IWL<53633> A_IWL<53632> A_IWL<53631> A_IWL<53630> A_IWL<53629> A_IWL<53628> A_IWL<53627> A_IWL<53626> A_IWL<53625> A_IWL<53624> A_IWL<53623> A_IWL<53622> A_IWL<53621> A_IWL<53620> A_IWL<53619> A_IWL<53618> A_IWL<53617> A_IWL<53616> A_IWL<53615> A_IWL<53614> A_IWL<53613> A_IWL<53612> A_IWL<53611> A_IWL<53610> A_IWL<53609> A_IWL<53608> A_IWL<53607> A_IWL<53606> A_IWL<53605> A_IWL<53604> A_IWL<53603> A_IWL<53602> A_IWL<53601> A_IWL<53600> A_IWL<53599> A_IWL<53598> A_IWL<53597> A_IWL<53596> A_IWL<53595> A_IWL<53594> A_IWL<53593> A_IWL<53592> A_IWL<53591> A_IWL<53590> A_IWL<53589> A_IWL<53588> A_IWL<53587> A_IWL<53586> A_IWL<53585> A_IWL<53584> A_IWL<53583> A_IWL<53582> A_IWL<53581> A_IWL<53580> A_IWL<53579> A_IWL<53578> A_IWL<53577> A_IWL<53576> A_IWL<53575> A_IWL<53574> A_IWL<53573> A_IWL<53572> A_IWL<53571> A_IWL<53570> A_IWL<53569> A_IWL<53568> A_IWL<53567> A_IWL<53566> A_IWL<53565> A_IWL<53564> A_IWL<53563> A_IWL<53562> A_IWL<53561> A_IWL<53560> A_IWL<53559> A_IWL<53558> A_IWL<53557> A_IWL<53556> A_IWL<53555> A_IWL<53554> A_IWL<53553> A_IWL<53552> A_IWL<53551> A_IWL<53550> A_IWL<53549> A_IWL<53548> A_IWL<53547> A_IWL<53546> A_IWL<53545> A_IWL<53544> A_IWL<53543> A_IWL<53542> A_IWL<53541> A_IWL<53540> A_IWL<53539> A_IWL<53538> A_IWL<53537> A_IWL<53536> A_IWL<53535> A_IWL<53534> A_IWL<53533> A_IWL<53532> A_IWL<53531> A_IWL<53530> A_IWL<53529> A_IWL<53528> A_IWL<53527> A_IWL<53526> A_IWL<53525> A_IWL<53524> A_IWL<53523> A_IWL<53522> A_IWL<53521> A_IWL<53520> A_IWL<53519> A_IWL<53518> A_IWL<53517> A_IWL<53516> A_IWL<53515> A_IWL<53514> A_IWL<53513> A_IWL<53512> A_IWL<53511> A_IWL<53510> A_IWL<53509> A_IWL<53508> A_IWL<53507> A_IWL<53506> A_IWL<53505> A_IWL<53504> A_IWL<53503> A_IWL<53502> A_IWL<53501> A_IWL<53500> A_IWL<53499> A_IWL<53498> A_IWL<53497> A_IWL<53496> A_IWL<53495> A_IWL<53494> A_IWL<53493> A_IWL<53492> A_IWL<53491> A_IWL<53490> A_IWL<53489> A_IWL<53488> A_IWL<53487> A_IWL<53486> A_IWL<53485> A_IWL<53484> A_IWL<53483> A_IWL<53482> A_IWL<53481> A_IWL<53480> A_IWL<53479> A_IWL<53478> A_IWL<53477> A_IWL<53476> A_IWL<53475> A_IWL<53474> A_IWL<53473> A_IWL<53472> A_IWL<53471> A_IWL<53470> A_IWL<53469> A_IWL<53468> A_IWL<53467> A_IWL<53466> A_IWL<53465> A_IWL<53464> A_IWL<53463> A_IWL<53462> A_IWL<53461> A_IWL<53460> A_IWL<53459> A_IWL<53458> A_IWL<53457> A_IWL<53456> A_IWL<53455> A_IWL<53454> A_IWL<53453> A_IWL<53452> A_IWL<53451> A_IWL<53450> A_IWL<53449> A_IWL<53448> A_IWL<53447> A_IWL<53446> A_IWL<53445> A_IWL<53444> A_IWL<53443> A_IWL<53442> A_IWL<53441> A_IWL<53440> A_IWL<53439> A_IWL<53438> A_IWL<53437> A_IWL<53436> A_IWL<53435> A_IWL<53434> A_IWL<53433> A_IWL<53432> A_IWL<53431> A_IWL<53430> A_IWL<53429> A_IWL<53428> A_IWL<53427> A_IWL<53426> A_IWL<53425> A_IWL<53424> A_IWL<53423> A_IWL<53422> A_IWL<53421> A_IWL<53420> A_IWL<53419> A_IWL<53418> A_IWL<53417> A_IWL<53416> A_IWL<53415> A_IWL<53414> A_IWL<53413> A_IWL<53412> A_IWL<53411> A_IWL<53410> A_IWL<53409> A_IWL<53408> A_IWL<53407> A_IWL<53406> A_IWL<53405> A_IWL<53404> A_IWL<53403> A_IWL<53402> A_IWL<53401> A_IWL<53400> A_IWL<53399> A_IWL<53398> A_IWL<53397> A_IWL<53396> A_IWL<53395> A_IWL<53394> A_IWL<53393> A_IWL<53392> A_IWL<53391> A_IWL<53390> A_IWL<53389> A_IWL<53388> A_IWL<53387> A_IWL<53386> A_IWL<53385> A_IWL<53384> A_IWL<53383> A_IWL<53382> A_IWL<53381> A_IWL<53380> A_IWL<53379> A_IWL<53378> A_IWL<53377> A_IWL<53376> A_IWL<53375> A_IWL<53374> A_IWL<53373> A_IWL<53372> A_IWL<53371> A_IWL<53370> A_IWL<53369> A_IWL<53368> A_IWL<53367> A_IWL<53366> A_IWL<53365> A_IWL<53364> A_IWL<53363> A_IWL<53362> A_IWL<53361> A_IWL<53360> A_IWL<53359> A_IWL<53358> A_IWL<53357> A_IWL<53356> A_IWL<53355> A_IWL<53354> A_IWL<53353> A_IWL<53352> A_IWL<53351> A_IWL<53350> A_IWL<53349> A_IWL<53348> A_IWL<53347> A_IWL<53346> A_IWL<53345> A_IWL<53344> A_IWL<53343> A_IWL<53342> A_IWL<53341> A_IWL<53340> A_IWL<53339> A_IWL<53338> A_IWL<53337> A_IWL<53336> A_IWL<53335> A_IWL<53334> A_IWL<53333> A_IWL<53332> A_IWL<53331> A_IWL<53330> A_IWL<53329> A_IWL<53328> A_IWL<53327> A_IWL<53326> A_IWL<53325> A_IWL<53324> A_IWL<53323> A_IWL<53322> A_IWL<53321> A_IWL<53320> A_IWL<53319> A_IWL<53318> A_IWL<53317> A_IWL<53316> A_IWL<53315> A_IWL<53314> A_IWL<53313> A_IWL<53312> A_IWL<53311> A_IWL<53310> A_IWL<53309> A_IWL<53308> A_IWL<53307> A_IWL<53306> A_IWL<53305> A_IWL<53304> A_IWL<53303> A_IWL<53302> A_IWL<53301> A_IWL<53300> A_IWL<53299> A_IWL<53298> A_IWL<53297> A_IWL<53296> A_IWL<53295> A_IWL<53294> A_IWL<53293> A_IWL<53292> A_IWL<53291> A_IWL<53290> A_IWL<53289> A_IWL<53288> A_IWL<53287> A_IWL<53286> A_IWL<53285> A_IWL<53284> A_IWL<53283> A_IWL<53282> A_IWL<53281> A_IWL<53280> A_IWL<53279> A_IWL<53278> A_IWL<53277> A_IWL<53276> A_IWL<53275> A_IWL<53274> A_IWL<53273> A_IWL<53272> A_IWL<53271> A_IWL<53270> A_IWL<53269> A_IWL<53268> A_IWL<53267> A_IWL<53266> A_IWL<53265> A_IWL<53264> A_IWL<53263> A_IWL<53262> A_IWL<53261> A_IWL<53260> A_IWL<53259> A_IWL<53258> A_IWL<53257> A_IWL<53256> A_IWL<53255> A_IWL<53254> A_IWL<53253> A_IWL<53252> A_IWL<53251> A_IWL<53250> A_IWL<53249> A_IWL<53248> VDD_CORE VSS / RM_IHPSG13_8192x32_c4_1P_COLUMN_pcell_0 +XCOL<103> A_BLC<207> A_BLC<206> A_BLC_TOP<207> A_BLC_TOP<206> A_BLT<207> A_BLT<206> A_BLT_TOP<207> A_BLT_TOP<206> A_IWL<52735> A_IWL<52734> A_IWL<52733> A_IWL<52732> A_IWL<52731> A_IWL<52730> A_IWL<52729> A_IWL<52728> A_IWL<52727> A_IWL<52726> A_IWL<52725> A_IWL<52724> A_IWL<52723> A_IWL<52722> A_IWL<52721> A_IWL<52720> A_IWL<52719> A_IWL<52718> A_IWL<52717> A_IWL<52716> A_IWL<52715> A_IWL<52714> A_IWL<52713> A_IWL<52712> A_IWL<52711> A_IWL<52710> A_IWL<52709> A_IWL<52708> A_IWL<52707> A_IWL<52706> A_IWL<52705> A_IWL<52704> A_IWL<52703> A_IWL<52702> A_IWL<52701> A_IWL<52700> A_IWL<52699> A_IWL<52698> A_IWL<52697> A_IWL<52696> A_IWL<52695> A_IWL<52694> A_IWL<52693> A_IWL<52692> A_IWL<52691> A_IWL<52690> A_IWL<52689> A_IWL<52688> A_IWL<52687> A_IWL<52686> A_IWL<52685> A_IWL<52684> A_IWL<52683> A_IWL<52682> A_IWL<52681> A_IWL<52680> A_IWL<52679> A_IWL<52678> A_IWL<52677> A_IWL<52676> A_IWL<52675> A_IWL<52674> A_IWL<52673> A_IWL<52672> A_IWL<52671> A_IWL<52670> A_IWL<52669> A_IWL<52668> A_IWL<52667> A_IWL<52666> A_IWL<52665> A_IWL<52664> A_IWL<52663> A_IWL<52662> A_IWL<52661> A_IWL<52660> A_IWL<52659> A_IWL<52658> A_IWL<52657> A_IWL<52656> A_IWL<52655> A_IWL<52654> A_IWL<52653> A_IWL<52652> A_IWL<52651> A_IWL<52650> A_IWL<52649> A_IWL<52648> A_IWL<52647> A_IWL<52646> A_IWL<52645> A_IWL<52644> A_IWL<52643> A_IWL<52642> A_IWL<52641> A_IWL<52640> A_IWL<52639> A_IWL<52638> A_IWL<52637> A_IWL<52636> A_IWL<52635> A_IWL<52634> A_IWL<52633> A_IWL<52632> A_IWL<52631> A_IWL<52630> A_IWL<52629> A_IWL<52628> A_IWL<52627> A_IWL<52626> A_IWL<52625> A_IWL<52624> A_IWL<52623> A_IWL<52622> A_IWL<52621> A_IWL<52620> A_IWL<52619> A_IWL<52618> A_IWL<52617> A_IWL<52616> A_IWL<52615> A_IWL<52614> A_IWL<52613> A_IWL<52612> A_IWL<52611> A_IWL<52610> A_IWL<52609> A_IWL<52608> A_IWL<52607> A_IWL<52606> A_IWL<52605> A_IWL<52604> A_IWL<52603> A_IWL<52602> A_IWL<52601> A_IWL<52600> A_IWL<52599> A_IWL<52598> A_IWL<52597> A_IWL<52596> A_IWL<52595> A_IWL<52594> A_IWL<52593> A_IWL<52592> A_IWL<52591> A_IWL<52590> A_IWL<52589> A_IWL<52588> A_IWL<52587> A_IWL<52586> A_IWL<52585> A_IWL<52584> A_IWL<52583> A_IWL<52582> A_IWL<52581> A_IWL<52580> A_IWL<52579> A_IWL<52578> A_IWL<52577> A_IWL<52576> A_IWL<52575> A_IWL<52574> A_IWL<52573> A_IWL<52572> A_IWL<52571> A_IWL<52570> A_IWL<52569> A_IWL<52568> A_IWL<52567> A_IWL<52566> A_IWL<52565> A_IWL<52564> A_IWL<52563> A_IWL<52562> A_IWL<52561> A_IWL<52560> A_IWL<52559> A_IWL<52558> A_IWL<52557> A_IWL<52556> A_IWL<52555> A_IWL<52554> A_IWL<52553> A_IWL<52552> A_IWL<52551> A_IWL<52550> A_IWL<52549> A_IWL<52548> A_IWL<52547> A_IWL<52546> A_IWL<52545> A_IWL<52544> A_IWL<52543> A_IWL<52542> A_IWL<52541> A_IWL<52540> A_IWL<52539> A_IWL<52538> A_IWL<52537> A_IWL<52536> A_IWL<52535> A_IWL<52534> A_IWL<52533> A_IWL<52532> A_IWL<52531> A_IWL<52530> A_IWL<52529> A_IWL<52528> A_IWL<52527> A_IWL<52526> A_IWL<52525> A_IWL<52524> A_IWL<52523> A_IWL<52522> A_IWL<52521> A_IWL<52520> A_IWL<52519> A_IWL<52518> A_IWL<52517> A_IWL<52516> A_IWL<52515> A_IWL<52514> A_IWL<52513> A_IWL<52512> A_IWL<52511> A_IWL<52510> A_IWL<52509> A_IWL<52508> A_IWL<52507> A_IWL<52506> A_IWL<52505> A_IWL<52504> A_IWL<52503> A_IWL<52502> A_IWL<52501> A_IWL<52500> A_IWL<52499> A_IWL<52498> A_IWL<52497> A_IWL<52496> A_IWL<52495> A_IWL<52494> A_IWL<52493> A_IWL<52492> A_IWL<52491> A_IWL<52490> A_IWL<52489> A_IWL<52488> A_IWL<52487> A_IWL<52486> A_IWL<52485> A_IWL<52484> A_IWL<52483> A_IWL<52482> A_IWL<52481> A_IWL<52480> A_IWL<52479> A_IWL<52478> A_IWL<52477> A_IWL<52476> A_IWL<52475> A_IWL<52474> A_IWL<52473> A_IWL<52472> A_IWL<52471> A_IWL<52470> A_IWL<52469> A_IWL<52468> A_IWL<52467> A_IWL<52466> A_IWL<52465> A_IWL<52464> A_IWL<52463> A_IWL<52462> A_IWL<52461> A_IWL<52460> A_IWL<52459> A_IWL<52458> A_IWL<52457> A_IWL<52456> A_IWL<52455> A_IWL<52454> A_IWL<52453> A_IWL<52452> A_IWL<52451> A_IWL<52450> A_IWL<52449> A_IWL<52448> A_IWL<52447> A_IWL<52446> A_IWL<52445> A_IWL<52444> A_IWL<52443> A_IWL<52442> A_IWL<52441> A_IWL<52440> A_IWL<52439> A_IWL<52438> A_IWL<52437> A_IWL<52436> A_IWL<52435> A_IWL<52434> A_IWL<52433> A_IWL<52432> A_IWL<52431> A_IWL<52430> A_IWL<52429> A_IWL<52428> A_IWL<52427> A_IWL<52426> A_IWL<52425> A_IWL<52424> A_IWL<52423> A_IWL<52422> A_IWL<52421> A_IWL<52420> A_IWL<52419> A_IWL<52418> A_IWL<52417> A_IWL<52416> A_IWL<52415> A_IWL<52414> A_IWL<52413> A_IWL<52412> A_IWL<52411> A_IWL<52410> A_IWL<52409> A_IWL<52408> A_IWL<52407> A_IWL<52406> A_IWL<52405> A_IWL<52404> A_IWL<52403> A_IWL<52402> A_IWL<52401> A_IWL<52400> A_IWL<52399> A_IWL<52398> A_IWL<52397> A_IWL<52396> A_IWL<52395> A_IWL<52394> A_IWL<52393> A_IWL<52392> A_IWL<52391> A_IWL<52390> A_IWL<52389> A_IWL<52388> A_IWL<52387> A_IWL<52386> A_IWL<52385> A_IWL<52384> A_IWL<52383> A_IWL<52382> A_IWL<52381> A_IWL<52380> A_IWL<52379> A_IWL<52378> A_IWL<52377> A_IWL<52376> A_IWL<52375> A_IWL<52374> A_IWL<52373> A_IWL<52372> A_IWL<52371> A_IWL<52370> A_IWL<52369> A_IWL<52368> A_IWL<52367> A_IWL<52366> A_IWL<52365> A_IWL<52364> A_IWL<52363> A_IWL<52362> A_IWL<52361> A_IWL<52360> A_IWL<52359> A_IWL<52358> A_IWL<52357> A_IWL<52356> A_IWL<52355> A_IWL<52354> A_IWL<52353> A_IWL<52352> A_IWL<52351> A_IWL<52350> A_IWL<52349> A_IWL<52348> A_IWL<52347> A_IWL<52346> A_IWL<52345> A_IWL<52344> A_IWL<52343> A_IWL<52342> A_IWL<52341> A_IWL<52340> A_IWL<52339> A_IWL<52338> A_IWL<52337> A_IWL<52336> A_IWL<52335> A_IWL<52334> A_IWL<52333> A_IWL<52332> A_IWL<52331> A_IWL<52330> A_IWL<52329> A_IWL<52328> A_IWL<52327> A_IWL<52326> A_IWL<52325> A_IWL<52324> A_IWL<52323> A_IWL<52322> A_IWL<52321> A_IWL<52320> A_IWL<52319> A_IWL<52318> A_IWL<52317> A_IWL<52316> A_IWL<52315> A_IWL<52314> A_IWL<52313> A_IWL<52312> A_IWL<52311> A_IWL<52310> A_IWL<52309> A_IWL<52308> A_IWL<52307> A_IWL<52306> A_IWL<52305> A_IWL<52304> A_IWL<52303> A_IWL<52302> A_IWL<52301> A_IWL<52300> A_IWL<52299> A_IWL<52298> A_IWL<52297> A_IWL<52296> A_IWL<52295> A_IWL<52294> A_IWL<52293> A_IWL<52292> A_IWL<52291> A_IWL<52290> A_IWL<52289> A_IWL<52288> A_IWL<52287> A_IWL<52286> A_IWL<52285> A_IWL<52284> A_IWL<52283> A_IWL<52282> A_IWL<52281> A_IWL<52280> A_IWL<52279> A_IWL<52278> A_IWL<52277> A_IWL<52276> A_IWL<52275> A_IWL<52274> A_IWL<52273> A_IWL<52272> A_IWL<52271> A_IWL<52270> A_IWL<52269> A_IWL<52268> A_IWL<52267> A_IWL<52266> A_IWL<52265> A_IWL<52264> A_IWL<52263> A_IWL<52262> A_IWL<52261> A_IWL<52260> A_IWL<52259> A_IWL<52258> A_IWL<52257> A_IWL<52256> A_IWL<52255> A_IWL<52254> A_IWL<52253> A_IWL<52252> A_IWL<52251> A_IWL<52250> A_IWL<52249> A_IWL<52248> A_IWL<52247> A_IWL<52246> A_IWL<52245> A_IWL<52244> A_IWL<52243> A_IWL<52242> A_IWL<52241> A_IWL<52240> A_IWL<52239> A_IWL<52238> A_IWL<52237> A_IWL<52236> A_IWL<52235> A_IWL<52234> A_IWL<52233> A_IWL<52232> A_IWL<52231> A_IWL<52230> A_IWL<52229> A_IWL<52228> A_IWL<52227> A_IWL<52226> A_IWL<52225> A_IWL<52224> A_IWL<53247> A_IWL<53246> A_IWL<53245> A_IWL<53244> A_IWL<53243> A_IWL<53242> A_IWL<53241> A_IWL<53240> A_IWL<53239> A_IWL<53238> A_IWL<53237> A_IWL<53236> A_IWL<53235> A_IWL<53234> A_IWL<53233> A_IWL<53232> A_IWL<53231> A_IWL<53230> A_IWL<53229> A_IWL<53228> A_IWL<53227> A_IWL<53226> A_IWL<53225> A_IWL<53224> A_IWL<53223> A_IWL<53222> A_IWL<53221> A_IWL<53220> A_IWL<53219> A_IWL<53218> A_IWL<53217> A_IWL<53216> A_IWL<53215> A_IWL<53214> A_IWL<53213> A_IWL<53212> A_IWL<53211> A_IWL<53210> A_IWL<53209> A_IWL<53208> A_IWL<53207> A_IWL<53206> A_IWL<53205> A_IWL<53204> A_IWL<53203> A_IWL<53202> A_IWL<53201> A_IWL<53200> A_IWL<53199> A_IWL<53198> A_IWL<53197> A_IWL<53196> A_IWL<53195> A_IWL<53194> A_IWL<53193> A_IWL<53192> A_IWL<53191> A_IWL<53190> A_IWL<53189> A_IWL<53188> A_IWL<53187> A_IWL<53186> A_IWL<53185> A_IWL<53184> A_IWL<53183> A_IWL<53182> A_IWL<53181> A_IWL<53180> A_IWL<53179> A_IWL<53178> A_IWL<53177> A_IWL<53176> A_IWL<53175> A_IWL<53174> A_IWL<53173> A_IWL<53172> A_IWL<53171> A_IWL<53170> A_IWL<53169> A_IWL<53168> A_IWL<53167> A_IWL<53166> A_IWL<53165> A_IWL<53164> A_IWL<53163> A_IWL<53162> A_IWL<53161> A_IWL<53160> A_IWL<53159> A_IWL<53158> A_IWL<53157> A_IWL<53156> A_IWL<53155> A_IWL<53154> A_IWL<53153> A_IWL<53152> A_IWL<53151> A_IWL<53150> A_IWL<53149> A_IWL<53148> A_IWL<53147> A_IWL<53146> A_IWL<53145> A_IWL<53144> A_IWL<53143> A_IWL<53142> A_IWL<53141> A_IWL<53140> A_IWL<53139> A_IWL<53138> A_IWL<53137> A_IWL<53136> A_IWL<53135> A_IWL<53134> A_IWL<53133> A_IWL<53132> A_IWL<53131> A_IWL<53130> A_IWL<53129> A_IWL<53128> A_IWL<53127> A_IWL<53126> A_IWL<53125> A_IWL<53124> A_IWL<53123> A_IWL<53122> A_IWL<53121> A_IWL<53120> A_IWL<53119> A_IWL<53118> A_IWL<53117> A_IWL<53116> A_IWL<53115> A_IWL<53114> A_IWL<53113> A_IWL<53112> A_IWL<53111> A_IWL<53110> A_IWL<53109> A_IWL<53108> A_IWL<53107> A_IWL<53106> A_IWL<53105> A_IWL<53104> A_IWL<53103> A_IWL<53102> A_IWL<53101> A_IWL<53100> A_IWL<53099> A_IWL<53098> A_IWL<53097> A_IWL<53096> A_IWL<53095> A_IWL<53094> A_IWL<53093> A_IWL<53092> A_IWL<53091> A_IWL<53090> A_IWL<53089> A_IWL<53088> A_IWL<53087> A_IWL<53086> A_IWL<53085> A_IWL<53084> A_IWL<53083> A_IWL<53082> A_IWL<53081> A_IWL<53080> A_IWL<53079> A_IWL<53078> A_IWL<53077> A_IWL<53076> A_IWL<53075> A_IWL<53074> A_IWL<53073> A_IWL<53072> A_IWL<53071> A_IWL<53070> A_IWL<53069> A_IWL<53068> A_IWL<53067> A_IWL<53066> A_IWL<53065> A_IWL<53064> A_IWL<53063> A_IWL<53062> A_IWL<53061> A_IWL<53060> A_IWL<53059> A_IWL<53058> A_IWL<53057> A_IWL<53056> A_IWL<53055> A_IWL<53054> A_IWL<53053> A_IWL<53052> A_IWL<53051> A_IWL<53050> A_IWL<53049> A_IWL<53048> A_IWL<53047> A_IWL<53046> A_IWL<53045> A_IWL<53044> A_IWL<53043> A_IWL<53042> A_IWL<53041> A_IWL<53040> A_IWL<53039> A_IWL<53038> A_IWL<53037> A_IWL<53036> A_IWL<53035> A_IWL<53034> A_IWL<53033> A_IWL<53032> A_IWL<53031> A_IWL<53030> A_IWL<53029> A_IWL<53028> A_IWL<53027> A_IWL<53026> A_IWL<53025> A_IWL<53024> A_IWL<53023> A_IWL<53022> A_IWL<53021> A_IWL<53020> A_IWL<53019> A_IWL<53018> A_IWL<53017> A_IWL<53016> A_IWL<53015> A_IWL<53014> A_IWL<53013> A_IWL<53012> A_IWL<53011> A_IWL<53010> A_IWL<53009> A_IWL<53008> A_IWL<53007> A_IWL<53006> A_IWL<53005> A_IWL<53004> A_IWL<53003> A_IWL<53002> A_IWL<53001> A_IWL<53000> A_IWL<52999> A_IWL<52998> A_IWL<52997> A_IWL<52996> A_IWL<52995> A_IWL<52994> A_IWL<52993> A_IWL<52992> A_IWL<52991> A_IWL<52990> A_IWL<52989> A_IWL<52988> A_IWL<52987> A_IWL<52986> A_IWL<52985> A_IWL<52984> A_IWL<52983> A_IWL<52982> A_IWL<52981> A_IWL<52980> A_IWL<52979> A_IWL<52978> A_IWL<52977> A_IWL<52976> A_IWL<52975> A_IWL<52974> A_IWL<52973> A_IWL<52972> A_IWL<52971> A_IWL<52970> A_IWL<52969> A_IWL<52968> A_IWL<52967> A_IWL<52966> A_IWL<52965> A_IWL<52964> A_IWL<52963> A_IWL<52962> A_IWL<52961> A_IWL<52960> A_IWL<52959> A_IWL<52958> A_IWL<52957> A_IWL<52956> A_IWL<52955> A_IWL<52954> A_IWL<52953> A_IWL<52952> A_IWL<52951> A_IWL<52950> A_IWL<52949> A_IWL<52948> A_IWL<52947> A_IWL<52946> A_IWL<52945> A_IWL<52944> A_IWL<52943> A_IWL<52942> A_IWL<52941> A_IWL<52940> A_IWL<52939> A_IWL<52938> A_IWL<52937> A_IWL<52936> A_IWL<52935> A_IWL<52934> A_IWL<52933> A_IWL<52932> A_IWL<52931> A_IWL<52930> A_IWL<52929> A_IWL<52928> A_IWL<52927> A_IWL<52926> A_IWL<52925> A_IWL<52924> A_IWL<52923> A_IWL<52922> A_IWL<52921> A_IWL<52920> A_IWL<52919> A_IWL<52918> A_IWL<52917> A_IWL<52916> A_IWL<52915> A_IWL<52914> A_IWL<52913> A_IWL<52912> A_IWL<52911> A_IWL<52910> A_IWL<52909> A_IWL<52908> A_IWL<52907> A_IWL<52906> A_IWL<52905> A_IWL<52904> A_IWL<52903> A_IWL<52902> A_IWL<52901> A_IWL<52900> A_IWL<52899> A_IWL<52898> A_IWL<52897> A_IWL<52896> A_IWL<52895> A_IWL<52894> A_IWL<52893> A_IWL<52892> A_IWL<52891> A_IWL<52890> A_IWL<52889> A_IWL<52888> A_IWL<52887> A_IWL<52886> A_IWL<52885> A_IWL<52884> A_IWL<52883> A_IWL<52882> A_IWL<52881> A_IWL<52880> A_IWL<52879> A_IWL<52878> A_IWL<52877> A_IWL<52876> A_IWL<52875> A_IWL<52874> A_IWL<52873> A_IWL<52872> A_IWL<52871> A_IWL<52870> A_IWL<52869> A_IWL<52868> A_IWL<52867> A_IWL<52866> A_IWL<52865> A_IWL<52864> A_IWL<52863> A_IWL<52862> A_IWL<52861> A_IWL<52860> A_IWL<52859> A_IWL<52858> A_IWL<52857> A_IWL<52856> A_IWL<52855> A_IWL<52854> A_IWL<52853> A_IWL<52852> A_IWL<52851> A_IWL<52850> A_IWL<52849> A_IWL<52848> A_IWL<52847> A_IWL<52846> A_IWL<52845> A_IWL<52844> A_IWL<52843> A_IWL<52842> A_IWL<52841> A_IWL<52840> A_IWL<52839> A_IWL<52838> A_IWL<52837> A_IWL<52836> A_IWL<52835> A_IWL<52834> A_IWL<52833> A_IWL<52832> A_IWL<52831> A_IWL<52830> A_IWL<52829> A_IWL<52828> A_IWL<52827> A_IWL<52826> A_IWL<52825> A_IWL<52824> A_IWL<52823> A_IWL<52822> A_IWL<52821> A_IWL<52820> A_IWL<52819> A_IWL<52818> A_IWL<52817> A_IWL<52816> A_IWL<52815> A_IWL<52814> A_IWL<52813> A_IWL<52812> A_IWL<52811> A_IWL<52810> A_IWL<52809> A_IWL<52808> A_IWL<52807> A_IWL<52806> A_IWL<52805> A_IWL<52804> A_IWL<52803> A_IWL<52802> A_IWL<52801> A_IWL<52800> A_IWL<52799> A_IWL<52798> A_IWL<52797> A_IWL<52796> A_IWL<52795> A_IWL<52794> A_IWL<52793> A_IWL<52792> A_IWL<52791> A_IWL<52790> A_IWL<52789> A_IWL<52788> A_IWL<52787> A_IWL<52786> A_IWL<52785> A_IWL<52784> A_IWL<52783> A_IWL<52782> A_IWL<52781> A_IWL<52780> A_IWL<52779> A_IWL<52778> A_IWL<52777> A_IWL<52776> A_IWL<52775> A_IWL<52774> A_IWL<52773> A_IWL<52772> A_IWL<52771> A_IWL<52770> A_IWL<52769> A_IWL<52768> A_IWL<52767> A_IWL<52766> A_IWL<52765> A_IWL<52764> A_IWL<52763> A_IWL<52762> A_IWL<52761> A_IWL<52760> A_IWL<52759> A_IWL<52758> A_IWL<52757> A_IWL<52756> A_IWL<52755> A_IWL<52754> A_IWL<52753> A_IWL<52752> A_IWL<52751> A_IWL<52750> A_IWL<52749> A_IWL<52748> A_IWL<52747> A_IWL<52746> A_IWL<52745> A_IWL<52744> A_IWL<52743> A_IWL<52742> A_IWL<52741> A_IWL<52740> A_IWL<52739> A_IWL<52738> A_IWL<52737> A_IWL<52736> VDD_CORE VSS / RM_IHPSG13_8192x32_c4_1P_COLUMN_pcell_0 +XCOL<102> A_BLC<205> A_BLC<204> A_BLC_TOP<205> A_BLC_TOP<204> A_BLT<205> A_BLT<204> A_BLT_TOP<205> A_BLT_TOP<204> A_IWL<52223> A_IWL<52222> A_IWL<52221> A_IWL<52220> A_IWL<52219> A_IWL<52218> A_IWL<52217> A_IWL<52216> A_IWL<52215> A_IWL<52214> A_IWL<52213> A_IWL<52212> A_IWL<52211> A_IWL<52210> A_IWL<52209> A_IWL<52208> A_IWL<52207> A_IWL<52206> A_IWL<52205> A_IWL<52204> A_IWL<52203> A_IWL<52202> A_IWL<52201> A_IWL<52200> A_IWL<52199> A_IWL<52198> A_IWL<52197> A_IWL<52196> A_IWL<52195> A_IWL<52194> A_IWL<52193> A_IWL<52192> A_IWL<52191> A_IWL<52190> A_IWL<52189> A_IWL<52188> A_IWL<52187> A_IWL<52186> A_IWL<52185> A_IWL<52184> A_IWL<52183> A_IWL<52182> A_IWL<52181> A_IWL<52180> A_IWL<52179> A_IWL<52178> A_IWL<52177> A_IWL<52176> A_IWL<52175> A_IWL<52174> A_IWL<52173> A_IWL<52172> A_IWL<52171> A_IWL<52170> A_IWL<52169> A_IWL<52168> A_IWL<52167> A_IWL<52166> A_IWL<52165> A_IWL<52164> A_IWL<52163> A_IWL<52162> A_IWL<52161> A_IWL<52160> A_IWL<52159> A_IWL<52158> A_IWL<52157> A_IWL<52156> A_IWL<52155> A_IWL<52154> A_IWL<52153> A_IWL<52152> A_IWL<52151> A_IWL<52150> A_IWL<52149> A_IWL<52148> A_IWL<52147> A_IWL<52146> A_IWL<52145> A_IWL<52144> A_IWL<52143> A_IWL<52142> A_IWL<52141> A_IWL<52140> A_IWL<52139> A_IWL<52138> A_IWL<52137> A_IWL<52136> A_IWL<52135> A_IWL<52134> A_IWL<52133> A_IWL<52132> A_IWL<52131> A_IWL<52130> A_IWL<52129> A_IWL<52128> A_IWL<52127> A_IWL<52126> A_IWL<52125> A_IWL<52124> A_IWL<52123> A_IWL<52122> A_IWL<52121> A_IWL<52120> A_IWL<52119> A_IWL<52118> A_IWL<52117> A_IWL<52116> A_IWL<52115> A_IWL<52114> A_IWL<52113> A_IWL<52112> A_IWL<52111> A_IWL<52110> A_IWL<52109> A_IWL<52108> A_IWL<52107> A_IWL<52106> A_IWL<52105> A_IWL<52104> A_IWL<52103> A_IWL<52102> A_IWL<52101> A_IWL<52100> A_IWL<52099> A_IWL<52098> A_IWL<52097> A_IWL<52096> A_IWL<52095> A_IWL<52094> A_IWL<52093> A_IWL<52092> A_IWL<52091> A_IWL<52090> A_IWL<52089> A_IWL<52088> A_IWL<52087> A_IWL<52086> A_IWL<52085> A_IWL<52084> A_IWL<52083> A_IWL<52082> A_IWL<52081> A_IWL<52080> A_IWL<52079> A_IWL<52078> A_IWL<52077> A_IWL<52076> A_IWL<52075> A_IWL<52074> A_IWL<52073> A_IWL<52072> A_IWL<52071> A_IWL<52070> A_IWL<52069> A_IWL<52068> A_IWL<52067> A_IWL<52066> A_IWL<52065> A_IWL<52064> A_IWL<52063> A_IWL<52062> A_IWL<52061> A_IWL<52060> A_IWL<52059> A_IWL<52058> A_IWL<52057> A_IWL<52056> A_IWL<52055> A_IWL<52054> A_IWL<52053> A_IWL<52052> A_IWL<52051> A_IWL<52050> A_IWL<52049> A_IWL<52048> A_IWL<52047> A_IWL<52046> A_IWL<52045> A_IWL<52044> A_IWL<52043> A_IWL<52042> A_IWL<52041> A_IWL<52040> A_IWL<52039> A_IWL<52038> A_IWL<52037> A_IWL<52036> A_IWL<52035> A_IWL<52034> A_IWL<52033> A_IWL<52032> A_IWL<52031> A_IWL<52030> A_IWL<52029> A_IWL<52028> A_IWL<52027> A_IWL<52026> A_IWL<52025> A_IWL<52024> A_IWL<52023> A_IWL<52022> A_IWL<52021> A_IWL<52020> A_IWL<52019> A_IWL<52018> A_IWL<52017> A_IWL<52016> A_IWL<52015> A_IWL<52014> A_IWL<52013> A_IWL<52012> A_IWL<52011> A_IWL<52010> A_IWL<52009> A_IWL<52008> A_IWL<52007> A_IWL<52006> A_IWL<52005> A_IWL<52004> A_IWL<52003> A_IWL<52002> A_IWL<52001> A_IWL<52000> A_IWL<51999> A_IWL<51998> A_IWL<51997> A_IWL<51996> A_IWL<51995> A_IWL<51994> A_IWL<51993> A_IWL<51992> A_IWL<51991> A_IWL<51990> A_IWL<51989> A_IWL<51988> A_IWL<51987> A_IWL<51986> A_IWL<51985> A_IWL<51984> A_IWL<51983> A_IWL<51982> A_IWL<51981> A_IWL<51980> A_IWL<51979> A_IWL<51978> A_IWL<51977> A_IWL<51976> A_IWL<51975> A_IWL<51974> A_IWL<51973> A_IWL<51972> A_IWL<51971> A_IWL<51970> A_IWL<51969> A_IWL<51968> A_IWL<51967> A_IWL<51966> A_IWL<51965> A_IWL<51964> A_IWL<51963> A_IWL<51962> A_IWL<51961> A_IWL<51960> A_IWL<51959> A_IWL<51958> A_IWL<51957> A_IWL<51956> A_IWL<51955> A_IWL<51954> A_IWL<51953> A_IWL<51952> A_IWL<51951> A_IWL<51950> A_IWL<51949> A_IWL<51948> A_IWL<51947> A_IWL<51946> A_IWL<51945> A_IWL<51944> A_IWL<51943> A_IWL<51942> A_IWL<51941> A_IWL<51940> A_IWL<51939> A_IWL<51938> A_IWL<51937> A_IWL<51936> A_IWL<51935> A_IWL<51934> A_IWL<51933> A_IWL<51932> A_IWL<51931> A_IWL<51930> A_IWL<51929> A_IWL<51928> A_IWL<51927> A_IWL<51926> A_IWL<51925> A_IWL<51924> A_IWL<51923> A_IWL<51922> A_IWL<51921> A_IWL<51920> A_IWL<51919> A_IWL<51918> A_IWL<51917> A_IWL<51916> A_IWL<51915> A_IWL<51914> A_IWL<51913> A_IWL<51912> A_IWL<51911> A_IWL<51910> A_IWL<51909> A_IWL<51908> A_IWL<51907> A_IWL<51906> A_IWL<51905> A_IWL<51904> A_IWL<51903> A_IWL<51902> A_IWL<51901> A_IWL<51900> A_IWL<51899> A_IWL<51898> A_IWL<51897> A_IWL<51896> A_IWL<51895> A_IWL<51894> A_IWL<51893> A_IWL<51892> A_IWL<51891> A_IWL<51890> A_IWL<51889> A_IWL<51888> A_IWL<51887> A_IWL<51886> A_IWL<51885> A_IWL<51884> A_IWL<51883> A_IWL<51882> A_IWL<51881> A_IWL<51880> A_IWL<51879> A_IWL<51878> A_IWL<51877> A_IWL<51876> A_IWL<51875> A_IWL<51874> A_IWL<51873> A_IWL<51872> A_IWL<51871> A_IWL<51870> A_IWL<51869> A_IWL<51868> A_IWL<51867> A_IWL<51866> A_IWL<51865> A_IWL<51864> A_IWL<51863> A_IWL<51862> A_IWL<51861> A_IWL<51860> A_IWL<51859> A_IWL<51858> A_IWL<51857> A_IWL<51856> A_IWL<51855> A_IWL<51854> A_IWL<51853> A_IWL<51852> A_IWL<51851> A_IWL<51850> A_IWL<51849> A_IWL<51848> A_IWL<51847> A_IWL<51846> A_IWL<51845> A_IWL<51844> A_IWL<51843> A_IWL<51842> A_IWL<51841> A_IWL<51840> A_IWL<51839> A_IWL<51838> A_IWL<51837> A_IWL<51836> A_IWL<51835> A_IWL<51834> A_IWL<51833> A_IWL<51832> A_IWL<51831> A_IWL<51830> A_IWL<51829> A_IWL<51828> A_IWL<51827> A_IWL<51826> A_IWL<51825> A_IWL<51824> A_IWL<51823> A_IWL<51822> A_IWL<51821> A_IWL<51820> A_IWL<51819> A_IWL<51818> A_IWL<51817> A_IWL<51816> A_IWL<51815> A_IWL<51814> A_IWL<51813> A_IWL<51812> A_IWL<51811> A_IWL<51810> A_IWL<51809> A_IWL<51808> A_IWL<51807> A_IWL<51806> A_IWL<51805> A_IWL<51804> A_IWL<51803> A_IWL<51802> A_IWL<51801> A_IWL<51800> A_IWL<51799> A_IWL<51798> A_IWL<51797> A_IWL<51796> A_IWL<51795> A_IWL<51794> A_IWL<51793> A_IWL<51792> A_IWL<51791> A_IWL<51790> A_IWL<51789> A_IWL<51788> A_IWL<51787> A_IWL<51786> A_IWL<51785> A_IWL<51784> A_IWL<51783> A_IWL<51782> A_IWL<51781> A_IWL<51780> A_IWL<51779> A_IWL<51778> A_IWL<51777> A_IWL<51776> A_IWL<51775> A_IWL<51774> A_IWL<51773> A_IWL<51772> A_IWL<51771> A_IWL<51770> A_IWL<51769> A_IWL<51768> A_IWL<51767> A_IWL<51766> A_IWL<51765> A_IWL<51764> A_IWL<51763> A_IWL<51762> A_IWL<51761> A_IWL<51760> A_IWL<51759> A_IWL<51758> A_IWL<51757> A_IWL<51756> A_IWL<51755> A_IWL<51754> A_IWL<51753> A_IWL<51752> A_IWL<51751> A_IWL<51750> A_IWL<51749> A_IWL<51748> A_IWL<51747> A_IWL<51746> A_IWL<51745> A_IWL<51744> A_IWL<51743> A_IWL<51742> A_IWL<51741> A_IWL<51740> A_IWL<51739> A_IWL<51738> A_IWL<51737> A_IWL<51736> A_IWL<51735> A_IWL<51734> A_IWL<51733> A_IWL<51732> A_IWL<51731> A_IWL<51730> A_IWL<51729> A_IWL<51728> A_IWL<51727> A_IWL<51726> A_IWL<51725> A_IWL<51724> A_IWL<51723> A_IWL<51722> A_IWL<51721> A_IWL<51720> A_IWL<51719> A_IWL<51718> A_IWL<51717> A_IWL<51716> A_IWL<51715> A_IWL<51714> A_IWL<51713> A_IWL<51712> A_IWL<52735> A_IWL<52734> A_IWL<52733> A_IWL<52732> A_IWL<52731> A_IWL<52730> A_IWL<52729> A_IWL<52728> A_IWL<52727> A_IWL<52726> A_IWL<52725> A_IWL<52724> A_IWL<52723> A_IWL<52722> A_IWL<52721> A_IWL<52720> A_IWL<52719> A_IWL<52718> A_IWL<52717> A_IWL<52716> A_IWL<52715> A_IWL<52714> A_IWL<52713> A_IWL<52712> A_IWL<52711> A_IWL<52710> A_IWL<52709> A_IWL<52708> A_IWL<52707> A_IWL<52706> A_IWL<52705> A_IWL<52704> A_IWL<52703> A_IWL<52702> A_IWL<52701> A_IWL<52700> A_IWL<52699> A_IWL<52698> A_IWL<52697> A_IWL<52696> A_IWL<52695> A_IWL<52694> A_IWL<52693> A_IWL<52692> A_IWL<52691> A_IWL<52690> A_IWL<52689> A_IWL<52688> A_IWL<52687> A_IWL<52686> A_IWL<52685> A_IWL<52684> A_IWL<52683> A_IWL<52682> A_IWL<52681> A_IWL<52680> A_IWL<52679> A_IWL<52678> A_IWL<52677> A_IWL<52676> A_IWL<52675> A_IWL<52674> A_IWL<52673> A_IWL<52672> A_IWL<52671> A_IWL<52670> A_IWL<52669> A_IWL<52668> A_IWL<52667> A_IWL<52666> A_IWL<52665> A_IWL<52664> A_IWL<52663> A_IWL<52662> A_IWL<52661> A_IWL<52660> A_IWL<52659> A_IWL<52658> A_IWL<52657> A_IWL<52656> A_IWL<52655> A_IWL<52654> A_IWL<52653> A_IWL<52652> A_IWL<52651> A_IWL<52650> A_IWL<52649> A_IWL<52648> A_IWL<52647> A_IWL<52646> A_IWL<52645> A_IWL<52644> A_IWL<52643> A_IWL<52642> A_IWL<52641> A_IWL<52640> A_IWL<52639> A_IWL<52638> A_IWL<52637> A_IWL<52636> A_IWL<52635> A_IWL<52634> A_IWL<52633> A_IWL<52632> A_IWL<52631> A_IWL<52630> A_IWL<52629> A_IWL<52628> A_IWL<52627> A_IWL<52626> A_IWL<52625> A_IWL<52624> A_IWL<52623> A_IWL<52622> A_IWL<52621> A_IWL<52620> A_IWL<52619> A_IWL<52618> A_IWL<52617> A_IWL<52616> A_IWL<52615> A_IWL<52614> A_IWL<52613> A_IWL<52612> A_IWL<52611> A_IWL<52610> A_IWL<52609> A_IWL<52608> A_IWL<52607> A_IWL<52606> A_IWL<52605> A_IWL<52604> A_IWL<52603> A_IWL<52602> A_IWL<52601> A_IWL<52600> A_IWL<52599> A_IWL<52598> A_IWL<52597> A_IWL<52596> A_IWL<52595> A_IWL<52594> A_IWL<52593> A_IWL<52592> A_IWL<52591> A_IWL<52590> A_IWL<52589> A_IWL<52588> A_IWL<52587> A_IWL<52586> A_IWL<52585> A_IWL<52584> A_IWL<52583> A_IWL<52582> A_IWL<52581> A_IWL<52580> A_IWL<52579> A_IWL<52578> A_IWL<52577> A_IWL<52576> A_IWL<52575> A_IWL<52574> A_IWL<52573> A_IWL<52572> A_IWL<52571> A_IWL<52570> A_IWL<52569> A_IWL<52568> A_IWL<52567> A_IWL<52566> A_IWL<52565> A_IWL<52564> A_IWL<52563> A_IWL<52562> A_IWL<52561> A_IWL<52560> A_IWL<52559> A_IWL<52558> A_IWL<52557> A_IWL<52556> A_IWL<52555> A_IWL<52554> A_IWL<52553> A_IWL<52552> A_IWL<52551> A_IWL<52550> A_IWL<52549> A_IWL<52548> A_IWL<52547> A_IWL<52546> A_IWL<52545> A_IWL<52544> A_IWL<52543> A_IWL<52542> A_IWL<52541> A_IWL<52540> A_IWL<52539> A_IWL<52538> A_IWL<52537> A_IWL<52536> A_IWL<52535> A_IWL<52534> A_IWL<52533> A_IWL<52532> A_IWL<52531> A_IWL<52530> A_IWL<52529> A_IWL<52528> A_IWL<52527> A_IWL<52526> A_IWL<52525> A_IWL<52524> A_IWL<52523> A_IWL<52522> A_IWL<52521> A_IWL<52520> A_IWL<52519> A_IWL<52518> A_IWL<52517> A_IWL<52516> A_IWL<52515> A_IWL<52514> A_IWL<52513> A_IWL<52512> A_IWL<52511> A_IWL<52510> A_IWL<52509> A_IWL<52508> A_IWL<52507> A_IWL<52506> A_IWL<52505> A_IWL<52504> A_IWL<52503> A_IWL<52502> A_IWL<52501> A_IWL<52500> A_IWL<52499> A_IWL<52498> A_IWL<52497> A_IWL<52496> A_IWL<52495> A_IWL<52494> A_IWL<52493> A_IWL<52492> A_IWL<52491> A_IWL<52490> A_IWL<52489> A_IWL<52488> A_IWL<52487> A_IWL<52486> A_IWL<52485> A_IWL<52484> A_IWL<52483> A_IWL<52482> A_IWL<52481> A_IWL<52480> A_IWL<52479> A_IWL<52478> A_IWL<52477> A_IWL<52476> A_IWL<52475> A_IWL<52474> A_IWL<52473> A_IWL<52472> A_IWL<52471> A_IWL<52470> A_IWL<52469> A_IWL<52468> A_IWL<52467> A_IWL<52466> A_IWL<52465> A_IWL<52464> A_IWL<52463> A_IWL<52462> A_IWL<52461> A_IWL<52460> A_IWL<52459> A_IWL<52458> A_IWL<52457> A_IWL<52456> A_IWL<52455> A_IWL<52454> A_IWL<52453> A_IWL<52452> A_IWL<52451> A_IWL<52450> A_IWL<52449> A_IWL<52448> A_IWL<52447> A_IWL<52446> A_IWL<52445> A_IWL<52444> A_IWL<52443> A_IWL<52442> A_IWL<52441> A_IWL<52440> A_IWL<52439> A_IWL<52438> A_IWL<52437> A_IWL<52436> A_IWL<52435> A_IWL<52434> A_IWL<52433> A_IWL<52432> A_IWL<52431> A_IWL<52430> A_IWL<52429> A_IWL<52428> A_IWL<52427> A_IWL<52426> A_IWL<52425> A_IWL<52424> A_IWL<52423> A_IWL<52422> A_IWL<52421> A_IWL<52420> A_IWL<52419> A_IWL<52418> A_IWL<52417> A_IWL<52416> A_IWL<52415> A_IWL<52414> A_IWL<52413> A_IWL<52412> A_IWL<52411> A_IWL<52410> A_IWL<52409> A_IWL<52408> A_IWL<52407> A_IWL<52406> A_IWL<52405> A_IWL<52404> A_IWL<52403> A_IWL<52402> A_IWL<52401> A_IWL<52400> A_IWL<52399> A_IWL<52398> A_IWL<52397> A_IWL<52396> A_IWL<52395> A_IWL<52394> A_IWL<52393> A_IWL<52392> A_IWL<52391> A_IWL<52390> A_IWL<52389> A_IWL<52388> A_IWL<52387> A_IWL<52386> A_IWL<52385> A_IWL<52384> A_IWL<52383> A_IWL<52382> A_IWL<52381> A_IWL<52380> A_IWL<52379> A_IWL<52378> A_IWL<52377> A_IWL<52376> A_IWL<52375> A_IWL<52374> A_IWL<52373> A_IWL<52372> A_IWL<52371> A_IWL<52370> A_IWL<52369> A_IWL<52368> A_IWL<52367> A_IWL<52366> A_IWL<52365> A_IWL<52364> A_IWL<52363> A_IWL<52362> A_IWL<52361> A_IWL<52360> A_IWL<52359> A_IWL<52358> A_IWL<52357> A_IWL<52356> A_IWL<52355> A_IWL<52354> A_IWL<52353> A_IWL<52352> A_IWL<52351> A_IWL<52350> A_IWL<52349> A_IWL<52348> A_IWL<52347> A_IWL<52346> A_IWL<52345> A_IWL<52344> A_IWL<52343> A_IWL<52342> A_IWL<52341> A_IWL<52340> A_IWL<52339> A_IWL<52338> A_IWL<52337> A_IWL<52336> A_IWL<52335> A_IWL<52334> A_IWL<52333> A_IWL<52332> A_IWL<52331> A_IWL<52330> A_IWL<52329> A_IWL<52328> A_IWL<52327> A_IWL<52326> A_IWL<52325> A_IWL<52324> A_IWL<52323> A_IWL<52322> A_IWL<52321> A_IWL<52320> A_IWL<52319> A_IWL<52318> A_IWL<52317> A_IWL<52316> A_IWL<52315> A_IWL<52314> A_IWL<52313> A_IWL<52312> A_IWL<52311> A_IWL<52310> A_IWL<52309> A_IWL<52308> A_IWL<52307> A_IWL<52306> A_IWL<52305> A_IWL<52304> A_IWL<52303> A_IWL<52302> A_IWL<52301> A_IWL<52300> A_IWL<52299> A_IWL<52298> A_IWL<52297> A_IWL<52296> A_IWL<52295> A_IWL<52294> A_IWL<52293> A_IWL<52292> A_IWL<52291> A_IWL<52290> A_IWL<52289> A_IWL<52288> A_IWL<52287> A_IWL<52286> A_IWL<52285> A_IWL<52284> A_IWL<52283> A_IWL<52282> A_IWL<52281> A_IWL<52280> A_IWL<52279> A_IWL<52278> A_IWL<52277> A_IWL<52276> A_IWL<52275> A_IWL<52274> A_IWL<52273> A_IWL<52272> A_IWL<52271> A_IWL<52270> A_IWL<52269> A_IWL<52268> A_IWL<52267> A_IWL<52266> A_IWL<52265> A_IWL<52264> A_IWL<52263> A_IWL<52262> A_IWL<52261> A_IWL<52260> A_IWL<52259> A_IWL<52258> A_IWL<52257> A_IWL<52256> A_IWL<52255> A_IWL<52254> A_IWL<52253> A_IWL<52252> A_IWL<52251> A_IWL<52250> A_IWL<52249> A_IWL<52248> A_IWL<52247> A_IWL<52246> A_IWL<52245> A_IWL<52244> A_IWL<52243> A_IWL<52242> A_IWL<52241> A_IWL<52240> A_IWL<52239> A_IWL<52238> A_IWL<52237> A_IWL<52236> A_IWL<52235> A_IWL<52234> A_IWL<52233> A_IWL<52232> A_IWL<52231> A_IWL<52230> A_IWL<52229> A_IWL<52228> A_IWL<52227> A_IWL<52226> A_IWL<52225> A_IWL<52224> VDD_CORE VSS / RM_IHPSG13_8192x32_c4_1P_COLUMN_pcell_0 +XCOL<101> A_BLC<203> A_BLC<202> A_BLC_TOP<203> A_BLC_TOP<202> A_BLT<203> A_BLT<202> A_BLT_TOP<203> A_BLT_TOP<202> A_IWL<51711> A_IWL<51710> A_IWL<51709> A_IWL<51708> A_IWL<51707> A_IWL<51706> A_IWL<51705> A_IWL<51704> A_IWL<51703> A_IWL<51702> A_IWL<51701> A_IWL<51700> A_IWL<51699> A_IWL<51698> A_IWL<51697> A_IWL<51696> A_IWL<51695> A_IWL<51694> A_IWL<51693> A_IWL<51692> A_IWL<51691> A_IWL<51690> A_IWL<51689> A_IWL<51688> A_IWL<51687> A_IWL<51686> A_IWL<51685> A_IWL<51684> A_IWL<51683> A_IWL<51682> A_IWL<51681> A_IWL<51680> A_IWL<51679> A_IWL<51678> A_IWL<51677> A_IWL<51676> A_IWL<51675> A_IWL<51674> A_IWL<51673> A_IWL<51672> A_IWL<51671> A_IWL<51670> A_IWL<51669> A_IWL<51668> A_IWL<51667> A_IWL<51666> A_IWL<51665> A_IWL<51664> A_IWL<51663> A_IWL<51662> A_IWL<51661> A_IWL<51660> A_IWL<51659> A_IWL<51658> A_IWL<51657> A_IWL<51656> A_IWL<51655> A_IWL<51654> A_IWL<51653> A_IWL<51652> A_IWL<51651> A_IWL<51650> A_IWL<51649> A_IWL<51648> A_IWL<51647> A_IWL<51646> A_IWL<51645> A_IWL<51644> A_IWL<51643> A_IWL<51642> A_IWL<51641> A_IWL<51640> A_IWL<51639> A_IWL<51638> A_IWL<51637> A_IWL<51636> A_IWL<51635> A_IWL<51634> A_IWL<51633> A_IWL<51632> A_IWL<51631> A_IWL<51630> A_IWL<51629> A_IWL<51628> A_IWL<51627> A_IWL<51626> A_IWL<51625> A_IWL<51624> A_IWL<51623> A_IWL<51622> A_IWL<51621> A_IWL<51620> A_IWL<51619> A_IWL<51618> A_IWL<51617> A_IWL<51616> A_IWL<51615> A_IWL<51614> A_IWL<51613> A_IWL<51612> A_IWL<51611> A_IWL<51610> A_IWL<51609> A_IWL<51608> A_IWL<51607> A_IWL<51606> A_IWL<51605> A_IWL<51604> A_IWL<51603> A_IWL<51602> A_IWL<51601> A_IWL<51600> A_IWL<51599> A_IWL<51598> A_IWL<51597> A_IWL<51596> A_IWL<51595> A_IWL<51594> A_IWL<51593> A_IWL<51592> A_IWL<51591> A_IWL<51590> A_IWL<51589> A_IWL<51588> A_IWL<51587> A_IWL<51586> A_IWL<51585> A_IWL<51584> A_IWL<51583> A_IWL<51582> A_IWL<51581> A_IWL<51580> A_IWL<51579> A_IWL<51578> A_IWL<51577> A_IWL<51576> A_IWL<51575> A_IWL<51574> A_IWL<51573> A_IWL<51572> A_IWL<51571> A_IWL<51570> A_IWL<51569> A_IWL<51568> A_IWL<51567> A_IWL<51566> A_IWL<51565> A_IWL<51564> A_IWL<51563> A_IWL<51562> A_IWL<51561> A_IWL<51560> A_IWL<51559> A_IWL<51558> A_IWL<51557> A_IWL<51556> A_IWL<51555> A_IWL<51554> A_IWL<51553> A_IWL<51552> A_IWL<51551> A_IWL<51550> A_IWL<51549> A_IWL<51548> A_IWL<51547> A_IWL<51546> A_IWL<51545> A_IWL<51544> A_IWL<51543> A_IWL<51542> A_IWL<51541> A_IWL<51540> A_IWL<51539> A_IWL<51538> A_IWL<51537> A_IWL<51536> A_IWL<51535> A_IWL<51534> A_IWL<51533> A_IWL<51532> A_IWL<51531> A_IWL<51530> A_IWL<51529> A_IWL<51528> A_IWL<51527> A_IWL<51526> A_IWL<51525> A_IWL<51524> A_IWL<51523> A_IWL<51522> A_IWL<51521> A_IWL<51520> A_IWL<51519> A_IWL<51518> A_IWL<51517> A_IWL<51516> A_IWL<51515> A_IWL<51514> A_IWL<51513> A_IWL<51512> A_IWL<51511> A_IWL<51510> A_IWL<51509> A_IWL<51508> A_IWL<51507> A_IWL<51506> A_IWL<51505> A_IWL<51504> A_IWL<51503> A_IWL<51502> A_IWL<51501> A_IWL<51500> A_IWL<51499> A_IWL<51498> A_IWL<51497> A_IWL<51496> A_IWL<51495> A_IWL<51494> A_IWL<51493> A_IWL<51492> A_IWL<51491> A_IWL<51490> A_IWL<51489> A_IWL<51488> A_IWL<51487> A_IWL<51486> A_IWL<51485> A_IWL<51484> A_IWL<51483> A_IWL<51482> A_IWL<51481> A_IWL<51480> A_IWL<51479> A_IWL<51478> A_IWL<51477> A_IWL<51476> A_IWL<51475> A_IWL<51474> A_IWL<51473> A_IWL<51472> A_IWL<51471> A_IWL<51470> A_IWL<51469> A_IWL<51468> A_IWL<51467> A_IWL<51466> A_IWL<51465> A_IWL<51464> A_IWL<51463> A_IWL<51462> A_IWL<51461> A_IWL<51460> A_IWL<51459> A_IWL<51458> A_IWL<51457> A_IWL<51456> A_IWL<51455> A_IWL<51454> A_IWL<51453> A_IWL<51452> A_IWL<51451> A_IWL<51450> A_IWL<51449> A_IWL<51448> A_IWL<51447> A_IWL<51446> A_IWL<51445> A_IWL<51444> A_IWL<51443> A_IWL<51442> A_IWL<51441> A_IWL<51440> A_IWL<51439> A_IWL<51438> A_IWL<51437> A_IWL<51436> A_IWL<51435> A_IWL<51434> A_IWL<51433> A_IWL<51432> A_IWL<51431> A_IWL<51430> A_IWL<51429> A_IWL<51428> A_IWL<51427> A_IWL<51426> A_IWL<51425> A_IWL<51424> A_IWL<51423> A_IWL<51422> A_IWL<51421> A_IWL<51420> A_IWL<51419> A_IWL<51418> A_IWL<51417> A_IWL<51416> A_IWL<51415> A_IWL<51414> A_IWL<51413> A_IWL<51412> A_IWL<51411> A_IWL<51410> A_IWL<51409> A_IWL<51408> A_IWL<51407> A_IWL<51406> A_IWL<51405> A_IWL<51404> A_IWL<51403> A_IWL<51402> A_IWL<51401> A_IWL<51400> A_IWL<51399> A_IWL<51398> A_IWL<51397> A_IWL<51396> A_IWL<51395> A_IWL<51394> A_IWL<51393> A_IWL<51392> A_IWL<51391> A_IWL<51390> A_IWL<51389> A_IWL<51388> A_IWL<51387> A_IWL<51386> A_IWL<51385> A_IWL<51384> A_IWL<51383> A_IWL<51382> A_IWL<51381> A_IWL<51380> A_IWL<51379> A_IWL<51378> A_IWL<51377> A_IWL<51376> A_IWL<51375> A_IWL<51374> A_IWL<51373> A_IWL<51372> A_IWL<51371> A_IWL<51370> A_IWL<51369> A_IWL<51368> A_IWL<51367> A_IWL<51366> A_IWL<51365> A_IWL<51364> A_IWL<51363> A_IWL<51362> A_IWL<51361> A_IWL<51360> A_IWL<51359> A_IWL<51358> A_IWL<51357> A_IWL<51356> A_IWL<51355> A_IWL<51354> A_IWL<51353> A_IWL<51352> A_IWL<51351> A_IWL<51350> A_IWL<51349> A_IWL<51348> A_IWL<51347> A_IWL<51346> A_IWL<51345> A_IWL<51344> A_IWL<51343> A_IWL<51342> A_IWL<51341> A_IWL<51340> A_IWL<51339> A_IWL<51338> A_IWL<51337> A_IWL<51336> A_IWL<51335> A_IWL<51334> A_IWL<51333> A_IWL<51332> A_IWL<51331> A_IWL<51330> A_IWL<51329> A_IWL<51328> A_IWL<51327> A_IWL<51326> A_IWL<51325> A_IWL<51324> A_IWL<51323> A_IWL<51322> A_IWL<51321> A_IWL<51320> A_IWL<51319> A_IWL<51318> A_IWL<51317> A_IWL<51316> A_IWL<51315> A_IWL<51314> A_IWL<51313> A_IWL<51312> A_IWL<51311> A_IWL<51310> A_IWL<51309> A_IWL<51308> A_IWL<51307> A_IWL<51306> A_IWL<51305> A_IWL<51304> A_IWL<51303> A_IWL<51302> A_IWL<51301> A_IWL<51300> A_IWL<51299> A_IWL<51298> A_IWL<51297> A_IWL<51296> A_IWL<51295> A_IWL<51294> A_IWL<51293> A_IWL<51292> A_IWL<51291> A_IWL<51290> A_IWL<51289> A_IWL<51288> A_IWL<51287> A_IWL<51286> A_IWL<51285> A_IWL<51284> A_IWL<51283> A_IWL<51282> A_IWL<51281> A_IWL<51280> A_IWL<51279> A_IWL<51278> A_IWL<51277> A_IWL<51276> A_IWL<51275> A_IWL<51274> A_IWL<51273> A_IWL<51272> A_IWL<51271> A_IWL<51270> A_IWL<51269> A_IWL<51268> A_IWL<51267> A_IWL<51266> A_IWL<51265> A_IWL<51264> A_IWL<51263> A_IWL<51262> A_IWL<51261> A_IWL<51260> A_IWL<51259> A_IWL<51258> A_IWL<51257> A_IWL<51256> A_IWL<51255> A_IWL<51254> A_IWL<51253> A_IWL<51252> A_IWL<51251> A_IWL<51250> A_IWL<51249> A_IWL<51248> A_IWL<51247> A_IWL<51246> A_IWL<51245> A_IWL<51244> A_IWL<51243> A_IWL<51242> A_IWL<51241> A_IWL<51240> A_IWL<51239> A_IWL<51238> A_IWL<51237> A_IWL<51236> A_IWL<51235> A_IWL<51234> A_IWL<51233> A_IWL<51232> A_IWL<51231> A_IWL<51230> A_IWL<51229> A_IWL<51228> A_IWL<51227> A_IWL<51226> A_IWL<51225> A_IWL<51224> A_IWL<51223> A_IWL<51222> A_IWL<51221> A_IWL<51220> A_IWL<51219> A_IWL<51218> A_IWL<51217> A_IWL<51216> A_IWL<51215> A_IWL<51214> A_IWL<51213> A_IWL<51212> A_IWL<51211> A_IWL<51210> A_IWL<51209> A_IWL<51208> A_IWL<51207> A_IWL<51206> A_IWL<51205> A_IWL<51204> A_IWL<51203> A_IWL<51202> A_IWL<51201> A_IWL<51200> A_IWL<52223> A_IWL<52222> A_IWL<52221> A_IWL<52220> A_IWL<52219> A_IWL<52218> A_IWL<52217> A_IWL<52216> A_IWL<52215> A_IWL<52214> A_IWL<52213> A_IWL<52212> A_IWL<52211> A_IWL<52210> A_IWL<52209> A_IWL<52208> A_IWL<52207> A_IWL<52206> A_IWL<52205> A_IWL<52204> A_IWL<52203> A_IWL<52202> A_IWL<52201> A_IWL<52200> A_IWL<52199> A_IWL<52198> A_IWL<52197> A_IWL<52196> A_IWL<52195> A_IWL<52194> A_IWL<52193> A_IWL<52192> A_IWL<52191> A_IWL<52190> A_IWL<52189> A_IWL<52188> A_IWL<52187> A_IWL<52186> A_IWL<52185> A_IWL<52184> A_IWL<52183> A_IWL<52182> A_IWL<52181> A_IWL<52180> A_IWL<52179> A_IWL<52178> A_IWL<52177> A_IWL<52176> A_IWL<52175> A_IWL<52174> A_IWL<52173> A_IWL<52172> A_IWL<52171> A_IWL<52170> A_IWL<52169> A_IWL<52168> A_IWL<52167> A_IWL<52166> A_IWL<52165> A_IWL<52164> A_IWL<52163> A_IWL<52162> A_IWL<52161> A_IWL<52160> A_IWL<52159> A_IWL<52158> A_IWL<52157> A_IWL<52156> A_IWL<52155> A_IWL<52154> A_IWL<52153> A_IWL<52152> A_IWL<52151> A_IWL<52150> A_IWL<52149> A_IWL<52148> A_IWL<52147> A_IWL<52146> A_IWL<52145> A_IWL<52144> A_IWL<52143> A_IWL<52142> A_IWL<52141> A_IWL<52140> A_IWL<52139> A_IWL<52138> A_IWL<52137> A_IWL<52136> A_IWL<52135> A_IWL<52134> A_IWL<52133> A_IWL<52132> A_IWL<52131> A_IWL<52130> A_IWL<52129> A_IWL<52128> A_IWL<52127> A_IWL<52126> A_IWL<52125> A_IWL<52124> A_IWL<52123> A_IWL<52122> A_IWL<52121> A_IWL<52120> A_IWL<52119> A_IWL<52118> A_IWL<52117> A_IWL<52116> A_IWL<52115> A_IWL<52114> A_IWL<52113> A_IWL<52112> A_IWL<52111> A_IWL<52110> A_IWL<52109> A_IWL<52108> A_IWL<52107> A_IWL<52106> A_IWL<52105> A_IWL<52104> A_IWL<52103> A_IWL<52102> A_IWL<52101> A_IWL<52100> A_IWL<52099> A_IWL<52098> A_IWL<52097> A_IWL<52096> A_IWL<52095> A_IWL<52094> A_IWL<52093> A_IWL<52092> A_IWL<52091> A_IWL<52090> A_IWL<52089> A_IWL<52088> A_IWL<52087> A_IWL<52086> A_IWL<52085> A_IWL<52084> A_IWL<52083> A_IWL<52082> A_IWL<52081> A_IWL<52080> A_IWL<52079> A_IWL<52078> A_IWL<52077> A_IWL<52076> A_IWL<52075> A_IWL<52074> A_IWL<52073> A_IWL<52072> A_IWL<52071> A_IWL<52070> A_IWL<52069> A_IWL<52068> A_IWL<52067> A_IWL<52066> A_IWL<52065> A_IWL<52064> A_IWL<52063> A_IWL<52062> A_IWL<52061> A_IWL<52060> A_IWL<52059> A_IWL<52058> A_IWL<52057> A_IWL<52056> A_IWL<52055> A_IWL<52054> A_IWL<52053> A_IWL<52052> A_IWL<52051> A_IWL<52050> A_IWL<52049> A_IWL<52048> A_IWL<52047> A_IWL<52046> A_IWL<52045> A_IWL<52044> A_IWL<52043> A_IWL<52042> A_IWL<52041> A_IWL<52040> A_IWL<52039> A_IWL<52038> A_IWL<52037> A_IWL<52036> A_IWL<52035> A_IWL<52034> A_IWL<52033> A_IWL<52032> A_IWL<52031> A_IWL<52030> A_IWL<52029> A_IWL<52028> A_IWL<52027> A_IWL<52026> A_IWL<52025> A_IWL<52024> A_IWL<52023> A_IWL<52022> A_IWL<52021> A_IWL<52020> A_IWL<52019> A_IWL<52018> A_IWL<52017> A_IWL<52016> A_IWL<52015> A_IWL<52014> A_IWL<52013> A_IWL<52012> A_IWL<52011> A_IWL<52010> A_IWL<52009> A_IWL<52008> A_IWL<52007> A_IWL<52006> A_IWL<52005> A_IWL<52004> A_IWL<52003> A_IWL<52002> A_IWL<52001> A_IWL<52000> A_IWL<51999> A_IWL<51998> A_IWL<51997> A_IWL<51996> A_IWL<51995> A_IWL<51994> A_IWL<51993> A_IWL<51992> A_IWL<51991> A_IWL<51990> A_IWL<51989> A_IWL<51988> A_IWL<51987> A_IWL<51986> A_IWL<51985> A_IWL<51984> A_IWL<51983> A_IWL<51982> A_IWL<51981> A_IWL<51980> A_IWL<51979> A_IWL<51978> A_IWL<51977> A_IWL<51976> A_IWL<51975> A_IWL<51974> A_IWL<51973> A_IWL<51972> A_IWL<51971> A_IWL<51970> A_IWL<51969> A_IWL<51968> A_IWL<51967> A_IWL<51966> A_IWL<51965> A_IWL<51964> A_IWL<51963> A_IWL<51962> A_IWL<51961> A_IWL<51960> A_IWL<51959> A_IWL<51958> A_IWL<51957> A_IWL<51956> A_IWL<51955> A_IWL<51954> A_IWL<51953> A_IWL<51952> A_IWL<51951> A_IWL<51950> A_IWL<51949> A_IWL<51948> A_IWL<51947> A_IWL<51946> A_IWL<51945> A_IWL<51944> A_IWL<51943> A_IWL<51942> A_IWL<51941> A_IWL<51940> A_IWL<51939> A_IWL<51938> A_IWL<51937> A_IWL<51936> A_IWL<51935> A_IWL<51934> A_IWL<51933> A_IWL<51932> A_IWL<51931> A_IWL<51930> A_IWL<51929> A_IWL<51928> A_IWL<51927> A_IWL<51926> A_IWL<51925> A_IWL<51924> A_IWL<51923> A_IWL<51922> A_IWL<51921> A_IWL<51920> A_IWL<51919> A_IWL<51918> A_IWL<51917> A_IWL<51916> A_IWL<51915> A_IWL<51914> A_IWL<51913> A_IWL<51912> A_IWL<51911> A_IWL<51910> A_IWL<51909> A_IWL<51908> A_IWL<51907> A_IWL<51906> A_IWL<51905> A_IWL<51904> A_IWL<51903> A_IWL<51902> A_IWL<51901> A_IWL<51900> A_IWL<51899> A_IWL<51898> A_IWL<51897> A_IWL<51896> A_IWL<51895> A_IWL<51894> A_IWL<51893> A_IWL<51892> A_IWL<51891> A_IWL<51890> A_IWL<51889> A_IWL<51888> A_IWL<51887> A_IWL<51886> A_IWL<51885> A_IWL<51884> A_IWL<51883> A_IWL<51882> A_IWL<51881> A_IWL<51880> A_IWL<51879> A_IWL<51878> A_IWL<51877> A_IWL<51876> A_IWL<51875> A_IWL<51874> A_IWL<51873> A_IWL<51872> A_IWL<51871> A_IWL<51870> A_IWL<51869> A_IWL<51868> A_IWL<51867> A_IWL<51866> A_IWL<51865> A_IWL<51864> A_IWL<51863> A_IWL<51862> A_IWL<51861> A_IWL<51860> A_IWL<51859> A_IWL<51858> A_IWL<51857> A_IWL<51856> A_IWL<51855> A_IWL<51854> A_IWL<51853> A_IWL<51852> A_IWL<51851> A_IWL<51850> A_IWL<51849> A_IWL<51848> A_IWL<51847> A_IWL<51846> A_IWL<51845> A_IWL<51844> A_IWL<51843> A_IWL<51842> A_IWL<51841> A_IWL<51840> A_IWL<51839> A_IWL<51838> A_IWL<51837> A_IWL<51836> A_IWL<51835> A_IWL<51834> A_IWL<51833> A_IWL<51832> A_IWL<51831> A_IWL<51830> A_IWL<51829> A_IWL<51828> A_IWL<51827> A_IWL<51826> A_IWL<51825> A_IWL<51824> A_IWL<51823> A_IWL<51822> A_IWL<51821> A_IWL<51820> A_IWL<51819> A_IWL<51818> A_IWL<51817> A_IWL<51816> A_IWL<51815> A_IWL<51814> A_IWL<51813> A_IWL<51812> A_IWL<51811> A_IWL<51810> A_IWL<51809> A_IWL<51808> A_IWL<51807> A_IWL<51806> A_IWL<51805> A_IWL<51804> A_IWL<51803> A_IWL<51802> A_IWL<51801> A_IWL<51800> A_IWL<51799> A_IWL<51798> A_IWL<51797> A_IWL<51796> A_IWL<51795> A_IWL<51794> A_IWL<51793> A_IWL<51792> A_IWL<51791> A_IWL<51790> A_IWL<51789> A_IWL<51788> A_IWL<51787> A_IWL<51786> A_IWL<51785> A_IWL<51784> A_IWL<51783> A_IWL<51782> A_IWL<51781> A_IWL<51780> A_IWL<51779> A_IWL<51778> A_IWL<51777> A_IWL<51776> A_IWL<51775> A_IWL<51774> A_IWL<51773> A_IWL<51772> A_IWL<51771> A_IWL<51770> A_IWL<51769> A_IWL<51768> A_IWL<51767> A_IWL<51766> A_IWL<51765> A_IWL<51764> A_IWL<51763> A_IWL<51762> A_IWL<51761> A_IWL<51760> A_IWL<51759> A_IWL<51758> A_IWL<51757> A_IWL<51756> A_IWL<51755> A_IWL<51754> A_IWL<51753> A_IWL<51752> A_IWL<51751> A_IWL<51750> A_IWL<51749> A_IWL<51748> A_IWL<51747> A_IWL<51746> A_IWL<51745> A_IWL<51744> A_IWL<51743> A_IWL<51742> A_IWL<51741> A_IWL<51740> A_IWL<51739> A_IWL<51738> A_IWL<51737> A_IWL<51736> A_IWL<51735> A_IWL<51734> A_IWL<51733> A_IWL<51732> A_IWL<51731> A_IWL<51730> A_IWL<51729> A_IWL<51728> A_IWL<51727> A_IWL<51726> A_IWL<51725> A_IWL<51724> A_IWL<51723> A_IWL<51722> A_IWL<51721> A_IWL<51720> A_IWL<51719> A_IWL<51718> A_IWL<51717> A_IWL<51716> A_IWL<51715> A_IWL<51714> A_IWL<51713> A_IWL<51712> VDD_CORE VSS / RM_IHPSG13_8192x32_c4_1P_COLUMN_pcell_0 +XCOL<100> A_BLC<201> A_BLC<200> A_BLC_TOP<201> A_BLC_TOP<200> A_BLT<201> A_BLT<200> A_BLT_TOP<201> A_BLT_TOP<200> A_IWL<51199> A_IWL<51198> A_IWL<51197> A_IWL<51196> A_IWL<51195> A_IWL<51194> A_IWL<51193> A_IWL<51192> A_IWL<51191> A_IWL<51190> A_IWL<51189> A_IWL<51188> A_IWL<51187> A_IWL<51186> A_IWL<51185> A_IWL<51184> A_IWL<51183> A_IWL<51182> A_IWL<51181> A_IWL<51180> A_IWL<51179> A_IWL<51178> A_IWL<51177> A_IWL<51176> A_IWL<51175> A_IWL<51174> A_IWL<51173> A_IWL<51172> A_IWL<51171> A_IWL<51170> A_IWL<51169> A_IWL<51168> A_IWL<51167> A_IWL<51166> A_IWL<51165> A_IWL<51164> A_IWL<51163> A_IWL<51162> A_IWL<51161> A_IWL<51160> A_IWL<51159> A_IWL<51158> A_IWL<51157> A_IWL<51156> A_IWL<51155> A_IWL<51154> A_IWL<51153> A_IWL<51152> A_IWL<51151> A_IWL<51150> A_IWL<51149> A_IWL<51148> A_IWL<51147> A_IWL<51146> A_IWL<51145> A_IWL<51144> A_IWL<51143> A_IWL<51142> A_IWL<51141> A_IWL<51140> A_IWL<51139> A_IWL<51138> A_IWL<51137> A_IWL<51136> A_IWL<51135> A_IWL<51134> A_IWL<51133> A_IWL<51132> A_IWL<51131> A_IWL<51130> A_IWL<51129> A_IWL<51128> A_IWL<51127> A_IWL<51126> A_IWL<51125> A_IWL<51124> A_IWL<51123> A_IWL<51122> A_IWL<51121> A_IWL<51120> A_IWL<51119> A_IWL<51118> A_IWL<51117> A_IWL<51116> A_IWL<51115> A_IWL<51114> A_IWL<51113> A_IWL<51112> A_IWL<51111> A_IWL<51110> A_IWL<51109> A_IWL<51108> A_IWL<51107> A_IWL<51106> A_IWL<51105> A_IWL<51104> A_IWL<51103> A_IWL<51102> A_IWL<51101> A_IWL<51100> A_IWL<51099> A_IWL<51098> A_IWL<51097> A_IWL<51096> A_IWL<51095> A_IWL<51094> A_IWL<51093> A_IWL<51092> A_IWL<51091> A_IWL<51090> A_IWL<51089> A_IWL<51088> A_IWL<51087> A_IWL<51086> A_IWL<51085> A_IWL<51084> A_IWL<51083> A_IWL<51082> A_IWL<51081> A_IWL<51080> A_IWL<51079> A_IWL<51078> A_IWL<51077> A_IWL<51076> A_IWL<51075> A_IWL<51074> A_IWL<51073> A_IWL<51072> A_IWL<51071> A_IWL<51070> A_IWL<51069> A_IWL<51068> A_IWL<51067> A_IWL<51066> A_IWL<51065> A_IWL<51064> A_IWL<51063> A_IWL<51062> A_IWL<51061> A_IWL<51060> A_IWL<51059> A_IWL<51058> A_IWL<51057> A_IWL<51056> A_IWL<51055> A_IWL<51054> A_IWL<51053> A_IWL<51052> A_IWL<51051> A_IWL<51050> A_IWL<51049> A_IWL<51048> A_IWL<51047> A_IWL<51046> A_IWL<51045> A_IWL<51044> A_IWL<51043> A_IWL<51042> A_IWL<51041> A_IWL<51040> A_IWL<51039> A_IWL<51038> A_IWL<51037> A_IWL<51036> A_IWL<51035> A_IWL<51034> A_IWL<51033> A_IWL<51032> A_IWL<51031> A_IWL<51030> A_IWL<51029> A_IWL<51028> A_IWL<51027> A_IWL<51026> A_IWL<51025> A_IWL<51024> A_IWL<51023> A_IWL<51022> A_IWL<51021> A_IWL<51020> A_IWL<51019> A_IWL<51018> A_IWL<51017> A_IWL<51016> A_IWL<51015> A_IWL<51014> A_IWL<51013> A_IWL<51012> A_IWL<51011> A_IWL<51010> A_IWL<51009> A_IWL<51008> A_IWL<51007> A_IWL<51006> A_IWL<51005> A_IWL<51004> A_IWL<51003> A_IWL<51002> A_IWL<51001> A_IWL<51000> A_IWL<50999> A_IWL<50998> A_IWL<50997> A_IWL<50996> A_IWL<50995> A_IWL<50994> A_IWL<50993> A_IWL<50992> A_IWL<50991> A_IWL<50990> A_IWL<50989> A_IWL<50988> A_IWL<50987> A_IWL<50986> A_IWL<50985> A_IWL<50984> A_IWL<50983> A_IWL<50982> A_IWL<50981> A_IWL<50980> A_IWL<50979> A_IWL<50978> A_IWL<50977> A_IWL<50976> A_IWL<50975> A_IWL<50974> A_IWL<50973> A_IWL<50972> A_IWL<50971> A_IWL<50970> A_IWL<50969> A_IWL<50968> A_IWL<50967> A_IWL<50966> A_IWL<50965> A_IWL<50964> A_IWL<50963> A_IWL<50962> A_IWL<50961> A_IWL<50960> A_IWL<50959> A_IWL<50958> A_IWL<50957> A_IWL<50956> A_IWL<50955> A_IWL<50954> A_IWL<50953> A_IWL<50952> A_IWL<50951> A_IWL<50950> A_IWL<50949> A_IWL<50948> A_IWL<50947> A_IWL<50946> A_IWL<50945> A_IWL<50944> A_IWL<50943> A_IWL<50942> A_IWL<50941> A_IWL<50940> A_IWL<50939> A_IWL<50938> A_IWL<50937> A_IWL<50936> A_IWL<50935> A_IWL<50934> A_IWL<50933> A_IWL<50932> A_IWL<50931> A_IWL<50930> A_IWL<50929> A_IWL<50928> A_IWL<50927> A_IWL<50926> A_IWL<50925> A_IWL<50924> A_IWL<50923> A_IWL<50922> A_IWL<50921> A_IWL<50920> A_IWL<50919> A_IWL<50918> A_IWL<50917> A_IWL<50916> A_IWL<50915> A_IWL<50914> A_IWL<50913> A_IWL<50912> A_IWL<50911> A_IWL<50910> A_IWL<50909> A_IWL<50908> A_IWL<50907> A_IWL<50906> A_IWL<50905> A_IWL<50904> A_IWL<50903> A_IWL<50902> A_IWL<50901> A_IWL<50900> A_IWL<50899> A_IWL<50898> A_IWL<50897> A_IWL<50896> A_IWL<50895> A_IWL<50894> A_IWL<50893> A_IWL<50892> A_IWL<50891> A_IWL<50890> A_IWL<50889> A_IWL<50888> A_IWL<50887> A_IWL<50886> A_IWL<50885> A_IWL<50884> A_IWL<50883> A_IWL<50882> A_IWL<50881> A_IWL<50880> A_IWL<50879> A_IWL<50878> A_IWL<50877> A_IWL<50876> A_IWL<50875> A_IWL<50874> A_IWL<50873> A_IWL<50872> A_IWL<50871> A_IWL<50870> A_IWL<50869> A_IWL<50868> A_IWL<50867> A_IWL<50866> A_IWL<50865> A_IWL<50864> A_IWL<50863> A_IWL<50862> A_IWL<50861> A_IWL<50860> A_IWL<50859> A_IWL<50858> A_IWL<50857> A_IWL<50856> A_IWL<50855> A_IWL<50854> A_IWL<50853> A_IWL<50852> A_IWL<50851> A_IWL<50850> A_IWL<50849> A_IWL<50848> A_IWL<50847> A_IWL<50846> A_IWL<50845> A_IWL<50844> A_IWL<50843> A_IWL<50842> A_IWL<50841> A_IWL<50840> A_IWL<50839> A_IWL<50838> A_IWL<50837> A_IWL<50836> A_IWL<50835> A_IWL<50834> A_IWL<50833> A_IWL<50832> A_IWL<50831> A_IWL<50830> A_IWL<50829> A_IWL<50828> A_IWL<50827> A_IWL<50826> A_IWL<50825> A_IWL<50824> A_IWL<50823> A_IWL<50822> A_IWL<50821> A_IWL<50820> A_IWL<50819> A_IWL<50818> A_IWL<50817> A_IWL<50816> A_IWL<50815> A_IWL<50814> A_IWL<50813> A_IWL<50812> A_IWL<50811> A_IWL<50810> A_IWL<50809> A_IWL<50808> A_IWL<50807> A_IWL<50806> A_IWL<50805> A_IWL<50804> A_IWL<50803> A_IWL<50802> A_IWL<50801> A_IWL<50800> A_IWL<50799> A_IWL<50798> A_IWL<50797> A_IWL<50796> A_IWL<50795> A_IWL<50794> A_IWL<50793> A_IWL<50792> A_IWL<50791> A_IWL<50790> A_IWL<50789> A_IWL<50788> A_IWL<50787> A_IWL<50786> A_IWL<50785> A_IWL<50784> A_IWL<50783> A_IWL<50782> A_IWL<50781> A_IWL<50780> A_IWL<50779> A_IWL<50778> A_IWL<50777> A_IWL<50776> A_IWL<50775> A_IWL<50774> A_IWL<50773> A_IWL<50772> A_IWL<50771> A_IWL<50770> A_IWL<50769> A_IWL<50768> A_IWL<50767> A_IWL<50766> A_IWL<50765> A_IWL<50764> A_IWL<50763> A_IWL<50762> A_IWL<50761> A_IWL<50760> A_IWL<50759> A_IWL<50758> A_IWL<50757> A_IWL<50756> A_IWL<50755> A_IWL<50754> A_IWL<50753> A_IWL<50752> A_IWL<50751> A_IWL<50750> A_IWL<50749> A_IWL<50748> A_IWL<50747> A_IWL<50746> A_IWL<50745> A_IWL<50744> A_IWL<50743> A_IWL<50742> A_IWL<50741> A_IWL<50740> A_IWL<50739> A_IWL<50738> A_IWL<50737> A_IWL<50736> A_IWL<50735> A_IWL<50734> A_IWL<50733> A_IWL<50732> A_IWL<50731> A_IWL<50730> A_IWL<50729> A_IWL<50728> A_IWL<50727> A_IWL<50726> A_IWL<50725> A_IWL<50724> A_IWL<50723> A_IWL<50722> A_IWL<50721> A_IWL<50720> A_IWL<50719> A_IWL<50718> A_IWL<50717> A_IWL<50716> A_IWL<50715> A_IWL<50714> A_IWL<50713> A_IWL<50712> A_IWL<50711> A_IWL<50710> A_IWL<50709> A_IWL<50708> A_IWL<50707> A_IWL<50706> A_IWL<50705> A_IWL<50704> A_IWL<50703> A_IWL<50702> A_IWL<50701> A_IWL<50700> A_IWL<50699> A_IWL<50698> A_IWL<50697> A_IWL<50696> A_IWL<50695> A_IWL<50694> A_IWL<50693> A_IWL<50692> A_IWL<50691> A_IWL<50690> A_IWL<50689> A_IWL<50688> A_IWL<51711> A_IWL<51710> A_IWL<51709> A_IWL<51708> A_IWL<51707> A_IWL<51706> A_IWL<51705> A_IWL<51704> A_IWL<51703> A_IWL<51702> A_IWL<51701> A_IWL<51700> A_IWL<51699> A_IWL<51698> A_IWL<51697> A_IWL<51696> A_IWL<51695> A_IWL<51694> A_IWL<51693> A_IWL<51692> A_IWL<51691> A_IWL<51690> A_IWL<51689> A_IWL<51688> A_IWL<51687> A_IWL<51686> A_IWL<51685> A_IWL<51684> A_IWL<51683> A_IWL<51682> A_IWL<51681> A_IWL<51680> A_IWL<51679> A_IWL<51678> A_IWL<51677> A_IWL<51676> A_IWL<51675> A_IWL<51674> A_IWL<51673> A_IWL<51672> A_IWL<51671> A_IWL<51670> A_IWL<51669> A_IWL<51668> A_IWL<51667> A_IWL<51666> A_IWL<51665> A_IWL<51664> A_IWL<51663> A_IWL<51662> A_IWL<51661> A_IWL<51660> A_IWL<51659> A_IWL<51658> A_IWL<51657> A_IWL<51656> A_IWL<51655> A_IWL<51654> A_IWL<51653> A_IWL<51652> A_IWL<51651> A_IWL<51650> A_IWL<51649> A_IWL<51648> A_IWL<51647> A_IWL<51646> A_IWL<51645> A_IWL<51644> A_IWL<51643> A_IWL<51642> A_IWL<51641> A_IWL<51640> A_IWL<51639> A_IWL<51638> A_IWL<51637> A_IWL<51636> A_IWL<51635> A_IWL<51634> A_IWL<51633> A_IWL<51632> A_IWL<51631> A_IWL<51630> A_IWL<51629> A_IWL<51628> A_IWL<51627> A_IWL<51626> A_IWL<51625> A_IWL<51624> A_IWL<51623> A_IWL<51622> A_IWL<51621> A_IWL<51620> A_IWL<51619> A_IWL<51618> A_IWL<51617> A_IWL<51616> A_IWL<51615> A_IWL<51614> A_IWL<51613> A_IWL<51612> A_IWL<51611> A_IWL<51610> A_IWL<51609> A_IWL<51608> A_IWL<51607> A_IWL<51606> A_IWL<51605> A_IWL<51604> A_IWL<51603> A_IWL<51602> A_IWL<51601> A_IWL<51600> A_IWL<51599> A_IWL<51598> A_IWL<51597> A_IWL<51596> A_IWL<51595> A_IWL<51594> A_IWL<51593> A_IWL<51592> A_IWL<51591> A_IWL<51590> A_IWL<51589> A_IWL<51588> A_IWL<51587> A_IWL<51586> A_IWL<51585> A_IWL<51584> A_IWL<51583> A_IWL<51582> A_IWL<51581> A_IWL<51580> A_IWL<51579> A_IWL<51578> A_IWL<51577> A_IWL<51576> A_IWL<51575> A_IWL<51574> A_IWL<51573> A_IWL<51572> A_IWL<51571> A_IWL<51570> A_IWL<51569> A_IWL<51568> A_IWL<51567> A_IWL<51566> A_IWL<51565> A_IWL<51564> A_IWL<51563> A_IWL<51562> A_IWL<51561> A_IWL<51560> A_IWL<51559> A_IWL<51558> A_IWL<51557> A_IWL<51556> A_IWL<51555> A_IWL<51554> A_IWL<51553> A_IWL<51552> A_IWL<51551> A_IWL<51550> A_IWL<51549> A_IWL<51548> A_IWL<51547> A_IWL<51546> A_IWL<51545> A_IWL<51544> A_IWL<51543> A_IWL<51542> A_IWL<51541> A_IWL<51540> A_IWL<51539> A_IWL<51538> A_IWL<51537> A_IWL<51536> A_IWL<51535> A_IWL<51534> A_IWL<51533> A_IWL<51532> A_IWL<51531> A_IWL<51530> A_IWL<51529> A_IWL<51528> A_IWL<51527> A_IWL<51526> A_IWL<51525> A_IWL<51524> A_IWL<51523> A_IWL<51522> A_IWL<51521> A_IWL<51520> A_IWL<51519> A_IWL<51518> A_IWL<51517> A_IWL<51516> A_IWL<51515> A_IWL<51514> A_IWL<51513> A_IWL<51512> A_IWL<51511> A_IWL<51510> A_IWL<51509> A_IWL<51508> A_IWL<51507> A_IWL<51506> A_IWL<51505> A_IWL<51504> A_IWL<51503> A_IWL<51502> A_IWL<51501> A_IWL<51500> A_IWL<51499> A_IWL<51498> A_IWL<51497> A_IWL<51496> A_IWL<51495> A_IWL<51494> A_IWL<51493> A_IWL<51492> A_IWL<51491> A_IWL<51490> A_IWL<51489> A_IWL<51488> A_IWL<51487> A_IWL<51486> A_IWL<51485> A_IWL<51484> A_IWL<51483> A_IWL<51482> A_IWL<51481> A_IWL<51480> A_IWL<51479> A_IWL<51478> A_IWL<51477> A_IWL<51476> A_IWL<51475> A_IWL<51474> A_IWL<51473> A_IWL<51472> A_IWL<51471> A_IWL<51470> A_IWL<51469> A_IWL<51468> A_IWL<51467> A_IWL<51466> A_IWL<51465> A_IWL<51464> A_IWL<51463> A_IWL<51462> A_IWL<51461> A_IWL<51460> A_IWL<51459> A_IWL<51458> A_IWL<51457> A_IWL<51456> A_IWL<51455> A_IWL<51454> A_IWL<51453> A_IWL<51452> A_IWL<51451> A_IWL<51450> A_IWL<51449> A_IWL<51448> A_IWL<51447> A_IWL<51446> A_IWL<51445> A_IWL<51444> A_IWL<51443> A_IWL<51442> A_IWL<51441> A_IWL<51440> A_IWL<51439> A_IWL<51438> A_IWL<51437> A_IWL<51436> A_IWL<51435> A_IWL<51434> A_IWL<51433> A_IWL<51432> A_IWL<51431> A_IWL<51430> A_IWL<51429> A_IWL<51428> A_IWL<51427> A_IWL<51426> A_IWL<51425> A_IWL<51424> A_IWL<51423> A_IWL<51422> A_IWL<51421> A_IWL<51420> A_IWL<51419> A_IWL<51418> A_IWL<51417> A_IWL<51416> A_IWL<51415> A_IWL<51414> A_IWL<51413> A_IWL<51412> A_IWL<51411> A_IWL<51410> A_IWL<51409> A_IWL<51408> A_IWL<51407> A_IWL<51406> A_IWL<51405> A_IWL<51404> A_IWL<51403> A_IWL<51402> A_IWL<51401> A_IWL<51400> A_IWL<51399> A_IWL<51398> A_IWL<51397> A_IWL<51396> A_IWL<51395> A_IWL<51394> A_IWL<51393> A_IWL<51392> A_IWL<51391> A_IWL<51390> A_IWL<51389> A_IWL<51388> A_IWL<51387> A_IWL<51386> A_IWL<51385> A_IWL<51384> A_IWL<51383> A_IWL<51382> A_IWL<51381> A_IWL<51380> A_IWL<51379> A_IWL<51378> A_IWL<51377> A_IWL<51376> A_IWL<51375> A_IWL<51374> A_IWL<51373> A_IWL<51372> A_IWL<51371> A_IWL<51370> A_IWL<51369> A_IWL<51368> A_IWL<51367> A_IWL<51366> A_IWL<51365> A_IWL<51364> A_IWL<51363> A_IWL<51362> A_IWL<51361> A_IWL<51360> A_IWL<51359> A_IWL<51358> A_IWL<51357> A_IWL<51356> A_IWL<51355> A_IWL<51354> A_IWL<51353> A_IWL<51352> A_IWL<51351> A_IWL<51350> A_IWL<51349> A_IWL<51348> A_IWL<51347> A_IWL<51346> A_IWL<51345> A_IWL<51344> A_IWL<51343> A_IWL<51342> A_IWL<51341> A_IWL<51340> A_IWL<51339> A_IWL<51338> A_IWL<51337> A_IWL<51336> A_IWL<51335> A_IWL<51334> A_IWL<51333> A_IWL<51332> A_IWL<51331> A_IWL<51330> A_IWL<51329> A_IWL<51328> A_IWL<51327> A_IWL<51326> A_IWL<51325> A_IWL<51324> A_IWL<51323> A_IWL<51322> A_IWL<51321> A_IWL<51320> A_IWL<51319> A_IWL<51318> A_IWL<51317> A_IWL<51316> A_IWL<51315> A_IWL<51314> A_IWL<51313> A_IWL<51312> A_IWL<51311> A_IWL<51310> A_IWL<51309> A_IWL<51308> A_IWL<51307> A_IWL<51306> A_IWL<51305> A_IWL<51304> A_IWL<51303> A_IWL<51302> A_IWL<51301> A_IWL<51300> A_IWL<51299> A_IWL<51298> A_IWL<51297> A_IWL<51296> A_IWL<51295> A_IWL<51294> A_IWL<51293> A_IWL<51292> A_IWL<51291> A_IWL<51290> A_IWL<51289> A_IWL<51288> A_IWL<51287> A_IWL<51286> A_IWL<51285> A_IWL<51284> A_IWL<51283> A_IWL<51282> A_IWL<51281> A_IWL<51280> A_IWL<51279> A_IWL<51278> A_IWL<51277> A_IWL<51276> A_IWL<51275> A_IWL<51274> A_IWL<51273> A_IWL<51272> A_IWL<51271> A_IWL<51270> A_IWL<51269> A_IWL<51268> A_IWL<51267> A_IWL<51266> A_IWL<51265> A_IWL<51264> A_IWL<51263> A_IWL<51262> A_IWL<51261> A_IWL<51260> A_IWL<51259> A_IWL<51258> A_IWL<51257> A_IWL<51256> A_IWL<51255> A_IWL<51254> A_IWL<51253> A_IWL<51252> A_IWL<51251> A_IWL<51250> A_IWL<51249> A_IWL<51248> A_IWL<51247> A_IWL<51246> A_IWL<51245> A_IWL<51244> A_IWL<51243> A_IWL<51242> A_IWL<51241> A_IWL<51240> A_IWL<51239> A_IWL<51238> A_IWL<51237> A_IWL<51236> A_IWL<51235> A_IWL<51234> A_IWL<51233> A_IWL<51232> A_IWL<51231> A_IWL<51230> A_IWL<51229> A_IWL<51228> A_IWL<51227> A_IWL<51226> A_IWL<51225> A_IWL<51224> A_IWL<51223> A_IWL<51222> A_IWL<51221> A_IWL<51220> A_IWL<51219> A_IWL<51218> A_IWL<51217> A_IWL<51216> A_IWL<51215> A_IWL<51214> A_IWL<51213> A_IWL<51212> A_IWL<51211> A_IWL<51210> A_IWL<51209> A_IWL<51208> A_IWL<51207> A_IWL<51206> A_IWL<51205> A_IWL<51204> A_IWL<51203> A_IWL<51202> A_IWL<51201> A_IWL<51200> VDD_CORE VSS / RM_IHPSG13_8192x32_c4_1P_COLUMN_pcell_0 +XCOL<99> A_BLC<199> A_BLC<198> A_BLC_TOP<199> A_BLC_TOP<198> A_BLT<199> A_BLT<198> A_BLT_TOP<199> A_BLT_TOP<198> A_IWL<50687> A_IWL<50686> A_IWL<50685> A_IWL<50684> A_IWL<50683> A_IWL<50682> A_IWL<50681> A_IWL<50680> A_IWL<50679> A_IWL<50678> A_IWL<50677> A_IWL<50676> A_IWL<50675> A_IWL<50674> A_IWL<50673> A_IWL<50672> A_IWL<50671> A_IWL<50670> A_IWL<50669> A_IWL<50668> A_IWL<50667> A_IWL<50666> A_IWL<50665> A_IWL<50664> A_IWL<50663> A_IWL<50662> A_IWL<50661> A_IWL<50660> A_IWL<50659> A_IWL<50658> A_IWL<50657> A_IWL<50656> A_IWL<50655> A_IWL<50654> A_IWL<50653> A_IWL<50652> A_IWL<50651> A_IWL<50650> A_IWL<50649> A_IWL<50648> A_IWL<50647> A_IWL<50646> A_IWL<50645> A_IWL<50644> A_IWL<50643> A_IWL<50642> A_IWL<50641> A_IWL<50640> A_IWL<50639> A_IWL<50638> A_IWL<50637> A_IWL<50636> A_IWL<50635> A_IWL<50634> A_IWL<50633> A_IWL<50632> A_IWL<50631> A_IWL<50630> A_IWL<50629> A_IWL<50628> A_IWL<50627> A_IWL<50626> A_IWL<50625> A_IWL<50624> A_IWL<50623> A_IWL<50622> A_IWL<50621> A_IWL<50620> A_IWL<50619> A_IWL<50618> A_IWL<50617> A_IWL<50616> A_IWL<50615> A_IWL<50614> A_IWL<50613> A_IWL<50612> A_IWL<50611> A_IWL<50610> A_IWL<50609> A_IWL<50608> A_IWL<50607> A_IWL<50606> A_IWL<50605> A_IWL<50604> A_IWL<50603> A_IWL<50602> A_IWL<50601> A_IWL<50600> A_IWL<50599> A_IWL<50598> A_IWL<50597> A_IWL<50596> A_IWL<50595> A_IWL<50594> A_IWL<50593> A_IWL<50592> A_IWL<50591> A_IWL<50590> A_IWL<50589> A_IWL<50588> A_IWL<50587> A_IWL<50586> A_IWL<50585> A_IWL<50584> A_IWL<50583> A_IWL<50582> A_IWL<50581> A_IWL<50580> A_IWL<50579> A_IWL<50578> A_IWL<50577> A_IWL<50576> A_IWL<50575> A_IWL<50574> A_IWL<50573> A_IWL<50572> A_IWL<50571> A_IWL<50570> A_IWL<50569> A_IWL<50568> A_IWL<50567> A_IWL<50566> A_IWL<50565> A_IWL<50564> A_IWL<50563> A_IWL<50562> A_IWL<50561> A_IWL<50560> A_IWL<50559> A_IWL<50558> A_IWL<50557> A_IWL<50556> A_IWL<50555> A_IWL<50554> A_IWL<50553> A_IWL<50552> A_IWL<50551> A_IWL<50550> A_IWL<50549> A_IWL<50548> A_IWL<50547> A_IWL<50546> A_IWL<50545> A_IWL<50544> A_IWL<50543> A_IWL<50542> A_IWL<50541> A_IWL<50540> A_IWL<50539> A_IWL<50538> A_IWL<50537> A_IWL<50536> A_IWL<50535> A_IWL<50534> A_IWL<50533> A_IWL<50532> A_IWL<50531> A_IWL<50530> A_IWL<50529> A_IWL<50528> A_IWL<50527> A_IWL<50526> A_IWL<50525> A_IWL<50524> A_IWL<50523> A_IWL<50522> A_IWL<50521> A_IWL<50520> A_IWL<50519> A_IWL<50518> A_IWL<50517> A_IWL<50516> A_IWL<50515> A_IWL<50514> A_IWL<50513> A_IWL<50512> A_IWL<50511> A_IWL<50510> A_IWL<50509> A_IWL<50508> A_IWL<50507> A_IWL<50506> A_IWL<50505> A_IWL<50504> A_IWL<50503> A_IWL<50502> A_IWL<50501> A_IWL<50500> A_IWL<50499> A_IWL<50498> A_IWL<50497> A_IWL<50496> A_IWL<50495> A_IWL<50494> A_IWL<50493> A_IWL<50492> A_IWL<50491> A_IWL<50490> A_IWL<50489> A_IWL<50488> A_IWL<50487> A_IWL<50486> A_IWL<50485> A_IWL<50484> A_IWL<50483> A_IWL<50482> A_IWL<50481> A_IWL<50480> A_IWL<50479> A_IWL<50478> A_IWL<50477> A_IWL<50476> A_IWL<50475> A_IWL<50474> A_IWL<50473> A_IWL<50472> A_IWL<50471> A_IWL<50470> A_IWL<50469> A_IWL<50468> A_IWL<50467> A_IWL<50466> A_IWL<50465> A_IWL<50464> A_IWL<50463> A_IWL<50462> A_IWL<50461> A_IWL<50460> A_IWL<50459> A_IWL<50458> A_IWL<50457> A_IWL<50456> A_IWL<50455> A_IWL<50454> A_IWL<50453> A_IWL<50452> A_IWL<50451> A_IWL<50450> A_IWL<50449> A_IWL<50448> A_IWL<50447> A_IWL<50446> A_IWL<50445> A_IWL<50444> A_IWL<50443> A_IWL<50442> A_IWL<50441> A_IWL<50440> A_IWL<50439> A_IWL<50438> A_IWL<50437> A_IWL<50436> A_IWL<50435> A_IWL<50434> A_IWL<50433> A_IWL<50432> A_IWL<50431> A_IWL<50430> A_IWL<50429> A_IWL<50428> A_IWL<50427> A_IWL<50426> A_IWL<50425> A_IWL<50424> A_IWL<50423> A_IWL<50422> A_IWL<50421> A_IWL<50420> A_IWL<50419> A_IWL<50418> A_IWL<50417> A_IWL<50416> A_IWL<50415> A_IWL<50414> A_IWL<50413> A_IWL<50412> A_IWL<50411> A_IWL<50410> A_IWL<50409> A_IWL<50408> A_IWL<50407> A_IWL<50406> A_IWL<50405> A_IWL<50404> A_IWL<50403> A_IWL<50402> A_IWL<50401> A_IWL<50400> A_IWL<50399> A_IWL<50398> A_IWL<50397> A_IWL<50396> A_IWL<50395> A_IWL<50394> A_IWL<50393> A_IWL<50392> A_IWL<50391> A_IWL<50390> A_IWL<50389> A_IWL<50388> A_IWL<50387> A_IWL<50386> A_IWL<50385> A_IWL<50384> A_IWL<50383> A_IWL<50382> A_IWL<50381> A_IWL<50380> A_IWL<50379> A_IWL<50378> A_IWL<50377> A_IWL<50376> A_IWL<50375> A_IWL<50374> A_IWL<50373> A_IWL<50372> A_IWL<50371> A_IWL<50370> A_IWL<50369> A_IWL<50368> A_IWL<50367> A_IWL<50366> A_IWL<50365> A_IWL<50364> A_IWL<50363> A_IWL<50362> A_IWL<50361> A_IWL<50360> A_IWL<50359> A_IWL<50358> A_IWL<50357> A_IWL<50356> A_IWL<50355> A_IWL<50354> A_IWL<50353> A_IWL<50352> A_IWL<50351> A_IWL<50350> A_IWL<50349> A_IWL<50348> A_IWL<50347> A_IWL<50346> A_IWL<50345> A_IWL<50344> A_IWL<50343> A_IWL<50342> A_IWL<50341> A_IWL<50340> A_IWL<50339> A_IWL<50338> A_IWL<50337> A_IWL<50336> A_IWL<50335> A_IWL<50334> A_IWL<50333> A_IWL<50332> A_IWL<50331> A_IWL<50330> A_IWL<50329> A_IWL<50328> A_IWL<50327> A_IWL<50326> A_IWL<50325> A_IWL<50324> A_IWL<50323> A_IWL<50322> A_IWL<50321> A_IWL<50320> A_IWL<50319> A_IWL<50318> A_IWL<50317> A_IWL<50316> A_IWL<50315> A_IWL<50314> A_IWL<50313> A_IWL<50312> A_IWL<50311> A_IWL<50310> A_IWL<50309> A_IWL<50308> A_IWL<50307> A_IWL<50306> A_IWL<50305> A_IWL<50304> A_IWL<50303> A_IWL<50302> A_IWL<50301> A_IWL<50300> A_IWL<50299> A_IWL<50298> A_IWL<50297> A_IWL<50296> A_IWL<50295> A_IWL<50294> A_IWL<50293> A_IWL<50292> A_IWL<50291> A_IWL<50290> A_IWL<50289> A_IWL<50288> A_IWL<50287> A_IWL<50286> A_IWL<50285> A_IWL<50284> A_IWL<50283> A_IWL<50282> A_IWL<50281> A_IWL<50280> A_IWL<50279> A_IWL<50278> A_IWL<50277> A_IWL<50276> A_IWL<50275> A_IWL<50274> A_IWL<50273> A_IWL<50272> A_IWL<50271> A_IWL<50270> A_IWL<50269> A_IWL<50268> A_IWL<50267> A_IWL<50266> A_IWL<50265> A_IWL<50264> A_IWL<50263> A_IWL<50262> A_IWL<50261> A_IWL<50260> A_IWL<50259> A_IWL<50258> A_IWL<50257> A_IWL<50256> A_IWL<50255> A_IWL<50254> A_IWL<50253> A_IWL<50252> A_IWL<50251> A_IWL<50250> A_IWL<50249> A_IWL<50248> A_IWL<50247> A_IWL<50246> A_IWL<50245> A_IWL<50244> A_IWL<50243> A_IWL<50242> A_IWL<50241> A_IWL<50240> A_IWL<50239> A_IWL<50238> A_IWL<50237> A_IWL<50236> A_IWL<50235> A_IWL<50234> A_IWL<50233> A_IWL<50232> A_IWL<50231> A_IWL<50230> A_IWL<50229> A_IWL<50228> A_IWL<50227> A_IWL<50226> A_IWL<50225> A_IWL<50224> A_IWL<50223> A_IWL<50222> A_IWL<50221> A_IWL<50220> A_IWL<50219> A_IWL<50218> A_IWL<50217> A_IWL<50216> A_IWL<50215> A_IWL<50214> A_IWL<50213> A_IWL<50212> A_IWL<50211> A_IWL<50210> A_IWL<50209> A_IWL<50208> A_IWL<50207> A_IWL<50206> A_IWL<50205> A_IWL<50204> A_IWL<50203> A_IWL<50202> A_IWL<50201> A_IWL<50200> A_IWL<50199> A_IWL<50198> A_IWL<50197> A_IWL<50196> A_IWL<50195> A_IWL<50194> A_IWL<50193> A_IWL<50192> A_IWL<50191> A_IWL<50190> A_IWL<50189> A_IWL<50188> A_IWL<50187> A_IWL<50186> A_IWL<50185> A_IWL<50184> A_IWL<50183> A_IWL<50182> A_IWL<50181> A_IWL<50180> A_IWL<50179> A_IWL<50178> A_IWL<50177> A_IWL<50176> A_IWL<51199> A_IWL<51198> A_IWL<51197> A_IWL<51196> A_IWL<51195> A_IWL<51194> A_IWL<51193> A_IWL<51192> A_IWL<51191> A_IWL<51190> A_IWL<51189> A_IWL<51188> A_IWL<51187> A_IWL<51186> A_IWL<51185> A_IWL<51184> A_IWL<51183> A_IWL<51182> A_IWL<51181> A_IWL<51180> A_IWL<51179> A_IWL<51178> A_IWL<51177> A_IWL<51176> A_IWL<51175> A_IWL<51174> A_IWL<51173> A_IWL<51172> A_IWL<51171> A_IWL<51170> A_IWL<51169> A_IWL<51168> A_IWL<51167> A_IWL<51166> A_IWL<51165> A_IWL<51164> A_IWL<51163> A_IWL<51162> A_IWL<51161> A_IWL<51160> A_IWL<51159> A_IWL<51158> A_IWL<51157> A_IWL<51156> A_IWL<51155> A_IWL<51154> A_IWL<51153> A_IWL<51152> A_IWL<51151> A_IWL<51150> A_IWL<51149> A_IWL<51148> A_IWL<51147> A_IWL<51146> A_IWL<51145> A_IWL<51144> A_IWL<51143> A_IWL<51142> A_IWL<51141> A_IWL<51140> A_IWL<51139> A_IWL<51138> A_IWL<51137> A_IWL<51136> A_IWL<51135> A_IWL<51134> A_IWL<51133> A_IWL<51132> A_IWL<51131> A_IWL<51130> A_IWL<51129> A_IWL<51128> A_IWL<51127> A_IWL<51126> A_IWL<51125> A_IWL<51124> A_IWL<51123> A_IWL<51122> A_IWL<51121> A_IWL<51120> A_IWL<51119> A_IWL<51118> A_IWL<51117> A_IWL<51116> A_IWL<51115> A_IWL<51114> A_IWL<51113> A_IWL<51112> A_IWL<51111> A_IWL<51110> A_IWL<51109> A_IWL<51108> A_IWL<51107> A_IWL<51106> A_IWL<51105> A_IWL<51104> A_IWL<51103> A_IWL<51102> A_IWL<51101> A_IWL<51100> A_IWL<51099> A_IWL<51098> A_IWL<51097> A_IWL<51096> A_IWL<51095> A_IWL<51094> A_IWL<51093> A_IWL<51092> A_IWL<51091> A_IWL<51090> A_IWL<51089> A_IWL<51088> A_IWL<51087> A_IWL<51086> A_IWL<51085> A_IWL<51084> A_IWL<51083> A_IWL<51082> A_IWL<51081> A_IWL<51080> A_IWL<51079> A_IWL<51078> A_IWL<51077> A_IWL<51076> A_IWL<51075> A_IWL<51074> A_IWL<51073> A_IWL<51072> A_IWL<51071> A_IWL<51070> A_IWL<51069> A_IWL<51068> A_IWL<51067> A_IWL<51066> A_IWL<51065> A_IWL<51064> A_IWL<51063> A_IWL<51062> A_IWL<51061> A_IWL<51060> A_IWL<51059> A_IWL<51058> A_IWL<51057> A_IWL<51056> A_IWL<51055> A_IWL<51054> A_IWL<51053> A_IWL<51052> A_IWL<51051> A_IWL<51050> A_IWL<51049> A_IWL<51048> A_IWL<51047> A_IWL<51046> A_IWL<51045> A_IWL<51044> A_IWL<51043> A_IWL<51042> A_IWL<51041> A_IWL<51040> A_IWL<51039> A_IWL<51038> A_IWL<51037> A_IWL<51036> A_IWL<51035> A_IWL<51034> A_IWL<51033> A_IWL<51032> A_IWL<51031> A_IWL<51030> A_IWL<51029> A_IWL<51028> A_IWL<51027> A_IWL<51026> A_IWL<51025> A_IWL<51024> A_IWL<51023> A_IWL<51022> A_IWL<51021> A_IWL<51020> A_IWL<51019> A_IWL<51018> A_IWL<51017> A_IWL<51016> A_IWL<51015> A_IWL<51014> A_IWL<51013> A_IWL<51012> A_IWL<51011> A_IWL<51010> A_IWL<51009> A_IWL<51008> A_IWL<51007> A_IWL<51006> A_IWL<51005> A_IWL<51004> A_IWL<51003> A_IWL<51002> A_IWL<51001> A_IWL<51000> A_IWL<50999> A_IWL<50998> A_IWL<50997> A_IWL<50996> A_IWL<50995> A_IWL<50994> A_IWL<50993> A_IWL<50992> A_IWL<50991> A_IWL<50990> A_IWL<50989> A_IWL<50988> A_IWL<50987> A_IWL<50986> A_IWL<50985> A_IWL<50984> A_IWL<50983> A_IWL<50982> A_IWL<50981> A_IWL<50980> A_IWL<50979> A_IWL<50978> A_IWL<50977> A_IWL<50976> A_IWL<50975> A_IWL<50974> A_IWL<50973> A_IWL<50972> A_IWL<50971> A_IWL<50970> A_IWL<50969> A_IWL<50968> A_IWL<50967> A_IWL<50966> A_IWL<50965> A_IWL<50964> A_IWL<50963> A_IWL<50962> A_IWL<50961> A_IWL<50960> A_IWL<50959> A_IWL<50958> A_IWL<50957> A_IWL<50956> A_IWL<50955> A_IWL<50954> A_IWL<50953> A_IWL<50952> A_IWL<50951> A_IWL<50950> A_IWL<50949> A_IWL<50948> A_IWL<50947> A_IWL<50946> A_IWL<50945> A_IWL<50944> A_IWL<50943> A_IWL<50942> A_IWL<50941> A_IWL<50940> A_IWL<50939> A_IWL<50938> A_IWL<50937> A_IWL<50936> A_IWL<50935> A_IWL<50934> A_IWL<50933> A_IWL<50932> A_IWL<50931> A_IWL<50930> A_IWL<50929> A_IWL<50928> A_IWL<50927> A_IWL<50926> A_IWL<50925> A_IWL<50924> A_IWL<50923> A_IWL<50922> A_IWL<50921> A_IWL<50920> A_IWL<50919> A_IWL<50918> A_IWL<50917> A_IWL<50916> A_IWL<50915> A_IWL<50914> A_IWL<50913> A_IWL<50912> A_IWL<50911> A_IWL<50910> A_IWL<50909> A_IWL<50908> A_IWL<50907> A_IWL<50906> A_IWL<50905> A_IWL<50904> A_IWL<50903> A_IWL<50902> A_IWL<50901> A_IWL<50900> A_IWL<50899> A_IWL<50898> A_IWL<50897> A_IWL<50896> A_IWL<50895> A_IWL<50894> A_IWL<50893> A_IWL<50892> A_IWL<50891> A_IWL<50890> A_IWL<50889> A_IWL<50888> A_IWL<50887> A_IWL<50886> A_IWL<50885> A_IWL<50884> A_IWL<50883> A_IWL<50882> A_IWL<50881> A_IWL<50880> A_IWL<50879> A_IWL<50878> A_IWL<50877> A_IWL<50876> A_IWL<50875> A_IWL<50874> A_IWL<50873> A_IWL<50872> A_IWL<50871> A_IWL<50870> A_IWL<50869> A_IWL<50868> A_IWL<50867> A_IWL<50866> A_IWL<50865> A_IWL<50864> A_IWL<50863> A_IWL<50862> A_IWL<50861> A_IWL<50860> A_IWL<50859> A_IWL<50858> A_IWL<50857> A_IWL<50856> A_IWL<50855> A_IWL<50854> A_IWL<50853> A_IWL<50852> A_IWL<50851> A_IWL<50850> A_IWL<50849> A_IWL<50848> A_IWL<50847> A_IWL<50846> A_IWL<50845> A_IWL<50844> A_IWL<50843> A_IWL<50842> A_IWL<50841> A_IWL<50840> A_IWL<50839> A_IWL<50838> A_IWL<50837> A_IWL<50836> A_IWL<50835> A_IWL<50834> A_IWL<50833> A_IWL<50832> A_IWL<50831> A_IWL<50830> A_IWL<50829> A_IWL<50828> A_IWL<50827> A_IWL<50826> A_IWL<50825> A_IWL<50824> A_IWL<50823> A_IWL<50822> A_IWL<50821> A_IWL<50820> A_IWL<50819> A_IWL<50818> A_IWL<50817> A_IWL<50816> A_IWL<50815> A_IWL<50814> A_IWL<50813> A_IWL<50812> A_IWL<50811> A_IWL<50810> A_IWL<50809> A_IWL<50808> A_IWL<50807> A_IWL<50806> A_IWL<50805> A_IWL<50804> A_IWL<50803> A_IWL<50802> A_IWL<50801> A_IWL<50800> A_IWL<50799> A_IWL<50798> A_IWL<50797> A_IWL<50796> A_IWL<50795> A_IWL<50794> A_IWL<50793> A_IWL<50792> A_IWL<50791> A_IWL<50790> A_IWL<50789> A_IWL<50788> A_IWL<50787> A_IWL<50786> A_IWL<50785> A_IWL<50784> A_IWL<50783> A_IWL<50782> A_IWL<50781> A_IWL<50780> A_IWL<50779> A_IWL<50778> A_IWL<50777> A_IWL<50776> A_IWL<50775> A_IWL<50774> A_IWL<50773> A_IWL<50772> A_IWL<50771> A_IWL<50770> A_IWL<50769> A_IWL<50768> A_IWL<50767> A_IWL<50766> A_IWL<50765> A_IWL<50764> A_IWL<50763> A_IWL<50762> A_IWL<50761> A_IWL<50760> A_IWL<50759> A_IWL<50758> A_IWL<50757> A_IWL<50756> A_IWL<50755> A_IWL<50754> A_IWL<50753> A_IWL<50752> A_IWL<50751> A_IWL<50750> A_IWL<50749> A_IWL<50748> A_IWL<50747> A_IWL<50746> A_IWL<50745> A_IWL<50744> A_IWL<50743> A_IWL<50742> A_IWL<50741> A_IWL<50740> A_IWL<50739> A_IWL<50738> A_IWL<50737> A_IWL<50736> A_IWL<50735> A_IWL<50734> A_IWL<50733> A_IWL<50732> A_IWL<50731> A_IWL<50730> A_IWL<50729> A_IWL<50728> A_IWL<50727> A_IWL<50726> A_IWL<50725> A_IWL<50724> A_IWL<50723> A_IWL<50722> A_IWL<50721> A_IWL<50720> A_IWL<50719> A_IWL<50718> A_IWL<50717> A_IWL<50716> A_IWL<50715> A_IWL<50714> A_IWL<50713> A_IWL<50712> A_IWL<50711> A_IWL<50710> A_IWL<50709> A_IWL<50708> A_IWL<50707> A_IWL<50706> A_IWL<50705> A_IWL<50704> A_IWL<50703> A_IWL<50702> A_IWL<50701> A_IWL<50700> A_IWL<50699> A_IWL<50698> A_IWL<50697> A_IWL<50696> A_IWL<50695> A_IWL<50694> A_IWL<50693> A_IWL<50692> A_IWL<50691> A_IWL<50690> A_IWL<50689> A_IWL<50688> VDD_CORE VSS / RM_IHPSG13_8192x32_c4_1P_COLUMN_pcell_0 +XCOL<98> A_BLC<197> A_BLC<196> A_BLC_TOP<197> A_BLC_TOP<196> A_BLT<197> A_BLT<196> A_BLT_TOP<197> A_BLT_TOP<196> A_IWL<50175> A_IWL<50174> A_IWL<50173> A_IWL<50172> A_IWL<50171> A_IWL<50170> A_IWL<50169> A_IWL<50168> A_IWL<50167> A_IWL<50166> A_IWL<50165> A_IWL<50164> A_IWL<50163> A_IWL<50162> A_IWL<50161> A_IWL<50160> A_IWL<50159> A_IWL<50158> A_IWL<50157> A_IWL<50156> A_IWL<50155> A_IWL<50154> A_IWL<50153> A_IWL<50152> A_IWL<50151> A_IWL<50150> A_IWL<50149> A_IWL<50148> A_IWL<50147> A_IWL<50146> A_IWL<50145> A_IWL<50144> A_IWL<50143> A_IWL<50142> A_IWL<50141> A_IWL<50140> A_IWL<50139> A_IWL<50138> A_IWL<50137> A_IWL<50136> A_IWL<50135> A_IWL<50134> A_IWL<50133> A_IWL<50132> A_IWL<50131> A_IWL<50130> A_IWL<50129> A_IWL<50128> A_IWL<50127> A_IWL<50126> A_IWL<50125> A_IWL<50124> A_IWL<50123> A_IWL<50122> A_IWL<50121> A_IWL<50120> A_IWL<50119> A_IWL<50118> A_IWL<50117> A_IWL<50116> A_IWL<50115> A_IWL<50114> A_IWL<50113> A_IWL<50112> A_IWL<50111> A_IWL<50110> A_IWL<50109> A_IWL<50108> A_IWL<50107> A_IWL<50106> A_IWL<50105> A_IWL<50104> A_IWL<50103> A_IWL<50102> A_IWL<50101> A_IWL<50100> A_IWL<50099> A_IWL<50098> A_IWL<50097> A_IWL<50096> A_IWL<50095> A_IWL<50094> A_IWL<50093> A_IWL<50092> A_IWL<50091> A_IWL<50090> A_IWL<50089> A_IWL<50088> A_IWL<50087> A_IWL<50086> A_IWL<50085> A_IWL<50084> A_IWL<50083> A_IWL<50082> A_IWL<50081> A_IWL<50080> A_IWL<50079> A_IWL<50078> A_IWL<50077> A_IWL<50076> A_IWL<50075> A_IWL<50074> A_IWL<50073> A_IWL<50072> A_IWL<50071> A_IWL<50070> A_IWL<50069> A_IWL<50068> A_IWL<50067> A_IWL<50066> A_IWL<50065> A_IWL<50064> A_IWL<50063> A_IWL<50062> A_IWL<50061> A_IWL<50060> A_IWL<50059> A_IWL<50058> A_IWL<50057> A_IWL<50056> A_IWL<50055> A_IWL<50054> A_IWL<50053> A_IWL<50052> A_IWL<50051> A_IWL<50050> A_IWL<50049> A_IWL<50048> A_IWL<50047> A_IWL<50046> A_IWL<50045> A_IWL<50044> A_IWL<50043> A_IWL<50042> A_IWL<50041> A_IWL<50040> A_IWL<50039> A_IWL<50038> A_IWL<50037> A_IWL<50036> A_IWL<50035> A_IWL<50034> A_IWL<50033> A_IWL<50032> A_IWL<50031> A_IWL<50030> A_IWL<50029> A_IWL<50028> A_IWL<50027> A_IWL<50026> A_IWL<50025> A_IWL<50024> A_IWL<50023> A_IWL<50022> A_IWL<50021> A_IWL<50020> A_IWL<50019> A_IWL<50018> A_IWL<50017> A_IWL<50016> A_IWL<50015> A_IWL<50014> A_IWL<50013> A_IWL<50012> A_IWL<50011> A_IWL<50010> A_IWL<50009> A_IWL<50008> A_IWL<50007> A_IWL<50006> A_IWL<50005> A_IWL<50004> A_IWL<50003> A_IWL<50002> A_IWL<50001> A_IWL<50000> A_IWL<49999> A_IWL<49998> A_IWL<49997> A_IWL<49996> A_IWL<49995> A_IWL<49994> A_IWL<49993> A_IWL<49992> A_IWL<49991> A_IWL<49990> A_IWL<49989> A_IWL<49988> A_IWL<49987> A_IWL<49986> A_IWL<49985> A_IWL<49984> A_IWL<49983> A_IWL<49982> A_IWL<49981> A_IWL<49980> A_IWL<49979> A_IWL<49978> A_IWL<49977> A_IWL<49976> A_IWL<49975> A_IWL<49974> A_IWL<49973> A_IWL<49972> A_IWL<49971> A_IWL<49970> A_IWL<49969> A_IWL<49968> A_IWL<49967> A_IWL<49966> A_IWL<49965> A_IWL<49964> A_IWL<49963> A_IWL<49962> A_IWL<49961> A_IWL<49960> A_IWL<49959> A_IWL<49958> A_IWL<49957> A_IWL<49956> A_IWL<49955> A_IWL<49954> A_IWL<49953> A_IWL<49952> A_IWL<49951> A_IWL<49950> A_IWL<49949> A_IWL<49948> A_IWL<49947> A_IWL<49946> A_IWL<49945> A_IWL<49944> A_IWL<49943> A_IWL<49942> A_IWL<49941> A_IWL<49940> A_IWL<49939> A_IWL<49938> A_IWL<49937> A_IWL<49936> A_IWL<49935> A_IWL<49934> A_IWL<49933> A_IWL<49932> A_IWL<49931> A_IWL<49930> A_IWL<49929> A_IWL<49928> A_IWL<49927> A_IWL<49926> A_IWL<49925> A_IWL<49924> A_IWL<49923> A_IWL<49922> A_IWL<49921> A_IWL<49920> A_IWL<49919> A_IWL<49918> A_IWL<49917> A_IWL<49916> A_IWL<49915> A_IWL<49914> A_IWL<49913> A_IWL<49912> A_IWL<49911> A_IWL<49910> A_IWL<49909> A_IWL<49908> A_IWL<49907> A_IWL<49906> A_IWL<49905> A_IWL<49904> A_IWL<49903> A_IWL<49902> A_IWL<49901> A_IWL<49900> A_IWL<49899> A_IWL<49898> A_IWL<49897> A_IWL<49896> A_IWL<49895> A_IWL<49894> A_IWL<49893> A_IWL<49892> A_IWL<49891> A_IWL<49890> A_IWL<49889> A_IWL<49888> A_IWL<49887> A_IWL<49886> A_IWL<49885> A_IWL<49884> A_IWL<49883> A_IWL<49882> A_IWL<49881> A_IWL<49880> A_IWL<49879> A_IWL<49878> A_IWL<49877> A_IWL<49876> A_IWL<49875> A_IWL<49874> A_IWL<49873> A_IWL<49872> A_IWL<49871> A_IWL<49870> A_IWL<49869> A_IWL<49868> A_IWL<49867> A_IWL<49866> A_IWL<49865> A_IWL<49864> A_IWL<49863> A_IWL<49862> A_IWL<49861> A_IWL<49860> A_IWL<49859> A_IWL<49858> A_IWL<49857> A_IWL<49856> A_IWL<49855> A_IWL<49854> A_IWL<49853> A_IWL<49852> A_IWL<49851> A_IWL<49850> A_IWL<49849> A_IWL<49848> A_IWL<49847> A_IWL<49846> A_IWL<49845> A_IWL<49844> A_IWL<49843> A_IWL<49842> A_IWL<49841> A_IWL<49840> A_IWL<49839> A_IWL<49838> A_IWL<49837> A_IWL<49836> A_IWL<49835> A_IWL<49834> A_IWL<49833> A_IWL<49832> A_IWL<49831> A_IWL<49830> A_IWL<49829> A_IWL<49828> A_IWL<49827> A_IWL<49826> A_IWL<49825> A_IWL<49824> A_IWL<49823> A_IWL<49822> A_IWL<49821> A_IWL<49820> A_IWL<49819> A_IWL<49818> A_IWL<49817> A_IWL<49816> A_IWL<49815> A_IWL<49814> A_IWL<49813> A_IWL<49812> A_IWL<49811> A_IWL<49810> A_IWL<49809> A_IWL<49808> A_IWL<49807> A_IWL<49806> A_IWL<49805> A_IWL<49804> A_IWL<49803> A_IWL<49802> A_IWL<49801> A_IWL<49800> A_IWL<49799> A_IWL<49798> A_IWL<49797> A_IWL<49796> A_IWL<49795> A_IWL<49794> A_IWL<49793> A_IWL<49792> A_IWL<49791> A_IWL<49790> A_IWL<49789> A_IWL<49788> A_IWL<49787> A_IWL<49786> A_IWL<49785> A_IWL<49784> A_IWL<49783> A_IWL<49782> A_IWL<49781> A_IWL<49780> A_IWL<49779> A_IWL<49778> A_IWL<49777> A_IWL<49776> A_IWL<49775> A_IWL<49774> A_IWL<49773> A_IWL<49772> A_IWL<49771> A_IWL<49770> A_IWL<49769> A_IWL<49768> A_IWL<49767> A_IWL<49766> A_IWL<49765> A_IWL<49764> A_IWL<49763> A_IWL<49762> A_IWL<49761> A_IWL<49760> A_IWL<49759> A_IWL<49758> A_IWL<49757> A_IWL<49756> A_IWL<49755> A_IWL<49754> A_IWL<49753> A_IWL<49752> A_IWL<49751> A_IWL<49750> A_IWL<49749> A_IWL<49748> A_IWL<49747> A_IWL<49746> A_IWL<49745> A_IWL<49744> A_IWL<49743> A_IWL<49742> A_IWL<49741> A_IWL<49740> A_IWL<49739> A_IWL<49738> A_IWL<49737> A_IWL<49736> A_IWL<49735> A_IWL<49734> A_IWL<49733> A_IWL<49732> A_IWL<49731> A_IWL<49730> A_IWL<49729> A_IWL<49728> A_IWL<49727> A_IWL<49726> A_IWL<49725> A_IWL<49724> A_IWL<49723> A_IWL<49722> A_IWL<49721> A_IWL<49720> A_IWL<49719> A_IWL<49718> A_IWL<49717> A_IWL<49716> A_IWL<49715> A_IWL<49714> A_IWL<49713> A_IWL<49712> A_IWL<49711> A_IWL<49710> A_IWL<49709> A_IWL<49708> A_IWL<49707> A_IWL<49706> A_IWL<49705> A_IWL<49704> A_IWL<49703> A_IWL<49702> A_IWL<49701> A_IWL<49700> A_IWL<49699> A_IWL<49698> A_IWL<49697> A_IWL<49696> A_IWL<49695> A_IWL<49694> A_IWL<49693> A_IWL<49692> A_IWL<49691> A_IWL<49690> A_IWL<49689> A_IWL<49688> A_IWL<49687> A_IWL<49686> A_IWL<49685> A_IWL<49684> A_IWL<49683> A_IWL<49682> A_IWL<49681> A_IWL<49680> A_IWL<49679> A_IWL<49678> A_IWL<49677> A_IWL<49676> A_IWL<49675> A_IWL<49674> A_IWL<49673> A_IWL<49672> A_IWL<49671> A_IWL<49670> A_IWL<49669> A_IWL<49668> A_IWL<49667> A_IWL<49666> A_IWL<49665> A_IWL<49664> A_IWL<50687> A_IWL<50686> A_IWL<50685> A_IWL<50684> A_IWL<50683> A_IWL<50682> A_IWL<50681> A_IWL<50680> A_IWL<50679> A_IWL<50678> A_IWL<50677> A_IWL<50676> A_IWL<50675> A_IWL<50674> A_IWL<50673> A_IWL<50672> A_IWL<50671> A_IWL<50670> A_IWL<50669> A_IWL<50668> A_IWL<50667> A_IWL<50666> A_IWL<50665> A_IWL<50664> A_IWL<50663> A_IWL<50662> A_IWL<50661> A_IWL<50660> A_IWL<50659> A_IWL<50658> A_IWL<50657> A_IWL<50656> A_IWL<50655> A_IWL<50654> A_IWL<50653> A_IWL<50652> A_IWL<50651> A_IWL<50650> A_IWL<50649> A_IWL<50648> A_IWL<50647> A_IWL<50646> A_IWL<50645> A_IWL<50644> A_IWL<50643> A_IWL<50642> A_IWL<50641> A_IWL<50640> A_IWL<50639> A_IWL<50638> A_IWL<50637> A_IWL<50636> A_IWL<50635> A_IWL<50634> A_IWL<50633> A_IWL<50632> A_IWL<50631> A_IWL<50630> A_IWL<50629> A_IWL<50628> A_IWL<50627> A_IWL<50626> A_IWL<50625> A_IWL<50624> A_IWL<50623> A_IWL<50622> A_IWL<50621> A_IWL<50620> A_IWL<50619> A_IWL<50618> A_IWL<50617> A_IWL<50616> A_IWL<50615> A_IWL<50614> A_IWL<50613> A_IWL<50612> A_IWL<50611> A_IWL<50610> A_IWL<50609> A_IWL<50608> A_IWL<50607> A_IWL<50606> A_IWL<50605> A_IWL<50604> A_IWL<50603> A_IWL<50602> A_IWL<50601> A_IWL<50600> A_IWL<50599> A_IWL<50598> A_IWL<50597> A_IWL<50596> A_IWL<50595> A_IWL<50594> A_IWL<50593> A_IWL<50592> A_IWL<50591> A_IWL<50590> A_IWL<50589> A_IWL<50588> A_IWL<50587> A_IWL<50586> A_IWL<50585> A_IWL<50584> A_IWL<50583> A_IWL<50582> A_IWL<50581> A_IWL<50580> A_IWL<50579> A_IWL<50578> A_IWL<50577> A_IWL<50576> A_IWL<50575> A_IWL<50574> A_IWL<50573> A_IWL<50572> A_IWL<50571> A_IWL<50570> A_IWL<50569> A_IWL<50568> A_IWL<50567> A_IWL<50566> A_IWL<50565> A_IWL<50564> A_IWL<50563> A_IWL<50562> A_IWL<50561> A_IWL<50560> A_IWL<50559> A_IWL<50558> A_IWL<50557> A_IWL<50556> A_IWL<50555> A_IWL<50554> A_IWL<50553> A_IWL<50552> A_IWL<50551> A_IWL<50550> A_IWL<50549> A_IWL<50548> A_IWL<50547> A_IWL<50546> A_IWL<50545> A_IWL<50544> A_IWL<50543> A_IWL<50542> A_IWL<50541> A_IWL<50540> A_IWL<50539> A_IWL<50538> A_IWL<50537> A_IWL<50536> A_IWL<50535> A_IWL<50534> A_IWL<50533> A_IWL<50532> A_IWL<50531> A_IWL<50530> A_IWL<50529> A_IWL<50528> A_IWL<50527> A_IWL<50526> A_IWL<50525> A_IWL<50524> A_IWL<50523> A_IWL<50522> A_IWL<50521> A_IWL<50520> A_IWL<50519> A_IWL<50518> A_IWL<50517> A_IWL<50516> A_IWL<50515> A_IWL<50514> A_IWL<50513> A_IWL<50512> A_IWL<50511> A_IWL<50510> A_IWL<50509> A_IWL<50508> A_IWL<50507> A_IWL<50506> A_IWL<50505> A_IWL<50504> A_IWL<50503> A_IWL<50502> A_IWL<50501> A_IWL<50500> A_IWL<50499> A_IWL<50498> A_IWL<50497> A_IWL<50496> A_IWL<50495> A_IWL<50494> A_IWL<50493> A_IWL<50492> A_IWL<50491> A_IWL<50490> A_IWL<50489> A_IWL<50488> A_IWL<50487> A_IWL<50486> A_IWL<50485> A_IWL<50484> A_IWL<50483> A_IWL<50482> A_IWL<50481> A_IWL<50480> A_IWL<50479> A_IWL<50478> A_IWL<50477> A_IWL<50476> A_IWL<50475> A_IWL<50474> A_IWL<50473> A_IWL<50472> A_IWL<50471> A_IWL<50470> A_IWL<50469> A_IWL<50468> A_IWL<50467> A_IWL<50466> A_IWL<50465> A_IWL<50464> A_IWL<50463> A_IWL<50462> A_IWL<50461> A_IWL<50460> A_IWL<50459> A_IWL<50458> A_IWL<50457> A_IWL<50456> A_IWL<50455> A_IWL<50454> A_IWL<50453> A_IWL<50452> A_IWL<50451> A_IWL<50450> A_IWL<50449> A_IWL<50448> A_IWL<50447> A_IWL<50446> A_IWL<50445> A_IWL<50444> A_IWL<50443> A_IWL<50442> A_IWL<50441> A_IWL<50440> A_IWL<50439> A_IWL<50438> A_IWL<50437> A_IWL<50436> A_IWL<50435> A_IWL<50434> A_IWL<50433> A_IWL<50432> A_IWL<50431> A_IWL<50430> A_IWL<50429> A_IWL<50428> A_IWL<50427> A_IWL<50426> A_IWL<50425> A_IWL<50424> A_IWL<50423> A_IWL<50422> A_IWL<50421> A_IWL<50420> A_IWL<50419> A_IWL<50418> A_IWL<50417> A_IWL<50416> A_IWL<50415> A_IWL<50414> A_IWL<50413> A_IWL<50412> A_IWL<50411> A_IWL<50410> A_IWL<50409> A_IWL<50408> A_IWL<50407> A_IWL<50406> A_IWL<50405> A_IWL<50404> A_IWL<50403> A_IWL<50402> A_IWL<50401> A_IWL<50400> A_IWL<50399> A_IWL<50398> A_IWL<50397> A_IWL<50396> A_IWL<50395> A_IWL<50394> A_IWL<50393> A_IWL<50392> A_IWL<50391> A_IWL<50390> A_IWL<50389> A_IWL<50388> A_IWL<50387> A_IWL<50386> A_IWL<50385> A_IWL<50384> A_IWL<50383> A_IWL<50382> A_IWL<50381> A_IWL<50380> A_IWL<50379> A_IWL<50378> A_IWL<50377> A_IWL<50376> A_IWL<50375> A_IWL<50374> A_IWL<50373> A_IWL<50372> A_IWL<50371> A_IWL<50370> A_IWL<50369> A_IWL<50368> A_IWL<50367> A_IWL<50366> A_IWL<50365> A_IWL<50364> A_IWL<50363> A_IWL<50362> A_IWL<50361> A_IWL<50360> A_IWL<50359> A_IWL<50358> A_IWL<50357> A_IWL<50356> A_IWL<50355> A_IWL<50354> A_IWL<50353> A_IWL<50352> A_IWL<50351> A_IWL<50350> A_IWL<50349> A_IWL<50348> A_IWL<50347> A_IWL<50346> A_IWL<50345> A_IWL<50344> A_IWL<50343> A_IWL<50342> A_IWL<50341> A_IWL<50340> A_IWL<50339> A_IWL<50338> A_IWL<50337> A_IWL<50336> A_IWL<50335> A_IWL<50334> A_IWL<50333> A_IWL<50332> A_IWL<50331> A_IWL<50330> A_IWL<50329> A_IWL<50328> A_IWL<50327> A_IWL<50326> A_IWL<50325> A_IWL<50324> A_IWL<50323> A_IWL<50322> A_IWL<50321> A_IWL<50320> A_IWL<50319> A_IWL<50318> A_IWL<50317> A_IWL<50316> A_IWL<50315> A_IWL<50314> A_IWL<50313> A_IWL<50312> A_IWL<50311> A_IWL<50310> A_IWL<50309> A_IWL<50308> A_IWL<50307> A_IWL<50306> A_IWL<50305> A_IWL<50304> A_IWL<50303> A_IWL<50302> A_IWL<50301> A_IWL<50300> A_IWL<50299> A_IWL<50298> A_IWL<50297> A_IWL<50296> A_IWL<50295> A_IWL<50294> A_IWL<50293> A_IWL<50292> A_IWL<50291> A_IWL<50290> A_IWL<50289> A_IWL<50288> A_IWL<50287> A_IWL<50286> A_IWL<50285> A_IWL<50284> A_IWL<50283> A_IWL<50282> A_IWL<50281> A_IWL<50280> A_IWL<50279> A_IWL<50278> A_IWL<50277> A_IWL<50276> A_IWL<50275> A_IWL<50274> A_IWL<50273> A_IWL<50272> A_IWL<50271> A_IWL<50270> A_IWL<50269> A_IWL<50268> A_IWL<50267> A_IWL<50266> A_IWL<50265> A_IWL<50264> A_IWL<50263> A_IWL<50262> A_IWL<50261> A_IWL<50260> A_IWL<50259> A_IWL<50258> A_IWL<50257> A_IWL<50256> A_IWL<50255> A_IWL<50254> A_IWL<50253> A_IWL<50252> A_IWL<50251> A_IWL<50250> A_IWL<50249> A_IWL<50248> A_IWL<50247> A_IWL<50246> A_IWL<50245> A_IWL<50244> A_IWL<50243> A_IWL<50242> A_IWL<50241> A_IWL<50240> A_IWL<50239> A_IWL<50238> A_IWL<50237> A_IWL<50236> A_IWL<50235> A_IWL<50234> A_IWL<50233> A_IWL<50232> A_IWL<50231> A_IWL<50230> A_IWL<50229> A_IWL<50228> A_IWL<50227> A_IWL<50226> A_IWL<50225> A_IWL<50224> A_IWL<50223> A_IWL<50222> A_IWL<50221> A_IWL<50220> A_IWL<50219> A_IWL<50218> A_IWL<50217> A_IWL<50216> A_IWL<50215> A_IWL<50214> A_IWL<50213> A_IWL<50212> A_IWL<50211> A_IWL<50210> A_IWL<50209> A_IWL<50208> A_IWL<50207> A_IWL<50206> A_IWL<50205> A_IWL<50204> A_IWL<50203> A_IWL<50202> A_IWL<50201> A_IWL<50200> A_IWL<50199> A_IWL<50198> A_IWL<50197> A_IWL<50196> A_IWL<50195> A_IWL<50194> A_IWL<50193> A_IWL<50192> A_IWL<50191> A_IWL<50190> A_IWL<50189> A_IWL<50188> A_IWL<50187> A_IWL<50186> A_IWL<50185> A_IWL<50184> A_IWL<50183> A_IWL<50182> A_IWL<50181> A_IWL<50180> A_IWL<50179> A_IWL<50178> A_IWL<50177> A_IWL<50176> VDD_CORE VSS / RM_IHPSG13_8192x32_c4_1P_COLUMN_pcell_0 +XCOL<97> A_BLC<195> A_BLC<194> A_BLC_TOP<195> A_BLC_TOP<194> A_BLT<195> A_BLT<194> A_BLT_TOP<195> A_BLT_TOP<194> A_IWL<49663> A_IWL<49662> A_IWL<49661> A_IWL<49660> A_IWL<49659> A_IWL<49658> A_IWL<49657> A_IWL<49656> A_IWL<49655> A_IWL<49654> A_IWL<49653> A_IWL<49652> A_IWL<49651> A_IWL<49650> A_IWL<49649> A_IWL<49648> A_IWL<49647> A_IWL<49646> A_IWL<49645> A_IWL<49644> A_IWL<49643> A_IWL<49642> A_IWL<49641> A_IWL<49640> A_IWL<49639> A_IWL<49638> A_IWL<49637> A_IWL<49636> A_IWL<49635> A_IWL<49634> A_IWL<49633> A_IWL<49632> A_IWL<49631> A_IWL<49630> A_IWL<49629> A_IWL<49628> A_IWL<49627> A_IWL<49626> A_IWL<49625> A_IWL<49624> A_IWL<49623> A_IWL<49622> A_IWL<49621> A_IWL<49620> A_IWL<49619> A_IWL<49618> A_IWL<49617> A_IWL<49616> A_IWL<49615> A_IWL<49614> A_IWL<49613> A_IWL<49612> A_IWL<49611> A_IWL<49610> A_IWL<49609> A_IWL<49608> A_IWL<49607> A_IWL<49606> A_IWL<49605> A_IWL<49604> A_IWL<49603> A_IWL<49602> A_IWL<49601> A_IWL<49600> A_IWL<49599> A_IWL<49598> A_IWL<49597> A_IWL<49596> A_IWL<49595> A_IWL<49594> A_IWL<49593> A_IWL<49592> A_IWL<49591> A_IWL<49590> A_IWL<49589> A_IWL<49588> A_IWL<49587> A_IWL<49586> A_IWL<49585> A_IWL<49584> A_IWL<49583> A_IWL<49582> A_IWL<49581> A_IWL<49580> A_IWL<49579> A_IWL<49578> A_IWL<49577> A_IWL<49576> A_IWL<49575> A_IWL<49574> A_IWL<49573> A_IWL<49572> A_IWL<49571> A_IWL<49570> A_IWL<49569> A_IWL<49568> A_IWL<49567> A_IWL<49566> A_IWL<49565> A_IWL<49564> A_IWL<49563> A_IWL<49562> A_IWL<49561> A_IWL<49560> A_IWL<49559> A_IWL<49558> A_IWL<49557> A_IWL<49556> A_IWL<49555> A_IWL<49554> A_IWL<49553> A_IWL<49552> A_IWL<49551> A_IWL<49550> A_IWL<49549> A_IWL<49548> A_IWL<49547> A_IWL<49546> A_IWL<49545> A_IWL<49544> A_IWL<49543> A_IWL<49542> A_IWL<49541> A_IWL<49540> A_IWL<49539> A_IWL<49538> A_IWL<49537> A_IWL<49536> A_IWL<49535> A_IWL<49534> A_IWL<49533> A_IWL<49532> A_IWL<49531> A_IWL<49530> A_IWL<49529> A_IWL<49528> A_IWL<49527> A_IWL<49526> A_IWL<49525> A_IWL<49524> A_IWL<49523> A_IWL<49522> A_IWL<49521> A_IWL<49520> A_IWL<49519> A_IWL<49518> A_IWL<49517> A_IWL<49516> A_IWL<49515> A_IWL<49514> A_IWL<49513> A_IWL<49512> A_IWL<49511> A_IWL<49510> A_IWL<49509> A_IWL<49508> A_IWL<49507> A_IWL<49506> A_IWL<49505> A_IWL<49504> A_IWL<49503> A_IWL<49502> A_IWL<49501> A_IWL<49500> A_IWL<49499> A_IWL<49498> A_IWL<49497> A_IWL<49496> A_IWL<49495> A_IWL<49494> A_IWL<49493> A_IWL<49492> A_IWL<49491> A_IWL<49490> A_IWL<49489> A_IWL<49488> A_IWL<49487> A_IWL<49486> A_IWL<49485> A_IWL<49484> A_IWL<49483> A_IWL<49482> A_IWL<49481> A_IWL<49480> A_IWL<49479> A_IWL<49478> A_IWL<49477> A_IWL<49476> A_IWL<49475> A_IWL<49474> A_IWL<49473> A_IWL<49472> A_IWL<49471> A_IWL<49470> A_IWL<49469> A_IWL<49468> A_IWL<49467> A_IWL<49466> A_IWL<49465> A_IWL<49464> A_IWL<49463> A_IWL<49462> A_IWL<49461> A_IWL<49460> A_IWL<49459> A_IWL<49458> A_IWL<49457> A_IWL<49456> A_IWL<49455> A_IWL<49454> A_IWL<49453> A_IWL<49452> A_IWL<49451> A_IWL<49450> A_IWL<49449> A_IWL<49448> A_IWL<49447> A_IWL<49446> A_IWL<49445> A_IWL<49444> A_IWL<49443> A_IWL<49442> A_IWL<49441> A_IWL<49440> A_IWL<49439> A_IWL<49438> A_IWL<49437> A_IWL<49436> A_IWL<49435> A_IWL<49434> A_IWL<49433> A_IWL<49432> A_IWL<49431> A_IWL<49430> A_IWL<49429> A_IWL<49428> A_IWL<49427> A_IWL<49426> A_IWL<49425> A_IWL<49424> A_IWL<49423> A_IWL<49422> A_IWL<49421> A_IWL<49420> A_IWL<49419> A_IWL<49418> A_IWL<49417> A_IWL<49416> A_IWL<49415> A_IWL<49414> A_IWL<49413> A_IWL<49412> A_IWL<49411> A_IWL<49410> A_IWL<49409> A_IWL<49408> A_IWL<49407> A_IWL<49406> A_IWL<49405> A_IWL<49404> A_IWL<49403> A_IWL<49402> A_IWL<49401> A_IWL<49400> A_IWL<49399> A_IWL<49398> A_IWL<49397> A_IWL<49396> A_IWL<49395> A_IWL<49394> A_IWL<49393> A_IWL<49392> A_IWL<49391> A_IWL<49390> A_IWL<49389> A_IWL<49388> A_IWL<49387> A_IWL<49386> A_IWL<49385> A_IWL<49384> A_IWL<49383> A_IWL<49382> A_IWL<49381> A_IWL<49380> A_IWL<49379> A_IWL<49378> A_IWL<49377> A_IWL<49376> A_IWL<49375> A_IWL<49374> A_IWL<49373> A_IWL<49372> A_IWL<49371> A_IWL<49370> A_IWL<49369> A_IWL<49368> A_IWL<49367> A_IWL<49366> A_IWL<49365> A_IWL<49364> A_IWL<49363> A_IWL<49362> A_IWL<49361> A_IWL<49360> A_IWL<49359> A_IWL<49358> A_IWL<49357> A_IWL<49356> A_IWL<49355> A_IWL<49354> A_IWL<49353> A_IWL<49352> A_IWL<49351> A_IWL<49350> A_IWL<49349> A_IWL<49348> A_IWL<49347> A_IWL<49346> A_IWL<49345> A_IWL<49344> A_IWL<49343> A_IWL<49342> A_IWL<49341> A_IWL<49340> A_IWL<49339> A_IWL<49338> A_IWL<49337> A_IWL<49336> A_IWL<49335> A_IWL<49334> A_IWL<49333> A_IWL<49332> A_IWL<49331> A_IWL<49330> A_IWL<49329> A_IWL<49328> A_IWL<49327> A_IWL<49326> A_IWL<49325> A_IWL<49324> A_IWL<49323> A_IWL<49322> A_IWL<49321> A_IWL<49320> A_IWL<49319> A_IWL<49318> A_IWL<49317> A_IWL<49316> A_IWL<49315> A_IWL<49314> A_IWL<49313> A_IWL<49312> A_IWL<49311> A_IWL<49310> A_IWL<49309> A_IWL<49308> A_IWL<49307> A_IWL<49306> A_IWL<49305> A_IWL<49304> A_IWL<49303> A_IWL<49302> A_IWL<49301> A_IWL<49300> A_IWL<49299> A_IWL<49298> A_IWL<49297> A_IWL<49296> A_IWL<49295> A_IWL<49294> A_IWL<49293> A_IWL<49292> A_IWL<49291> A_IWL<49290> A_IWL<49289> A_IWL<49288> A_IWL<49287> A_IWL<49286> A_IWL<49285> A_IWL<49284> A_IWL<49283> A_IWL<49282> A_IWL<49281> A_IWL<49280> A_IWL<49279> A_IWL<49278> A_IWL<49277> A_IWL<49276> A_IWL<49275> A_IWL<49274> A_IWL<49273> A_IWL<49272> A_IWL<49271> A_IWL<49270> A_IWL<49269> A_IWL<49268> A_IWL<49267> A_IWL<49266> A_IWL<49265> A_IWL<49264> A_IWL<49263> A_IWL<49262> A_IWL<49261> A_IWL<49260> A_IWL<49259> A_IWL<49258> A_IWL<49257> A_IWL<49256> A_IWL<49255> A_IWL<49254> A_IWL<49253> A_IWL<49252> A_IWL<49251> A_IWL<49250> A_IWL<49249> A_IWL<49248> A_IWL<49247> A_IWL<49246> A_IWL<49245> A_IWL<49244> A_IWL<49243> A_IWL<49242> A_IWL<49241> A_IWL<49240> A_IWL<49239> A_IWL<49238> A_IWL<49237> A_IWL<49236> A_IWL<49235> A_IWL<49234> A_IWL<49233> A_IWL<49232> A_IWL<49231> A_IWL<49230> A_IWL<49229> A_IWL<49228> A_IWL<49227> A_IWL<49226> A_IWL<49225> A_IWL<49224> A_IWL<49223> A_IWL<49222> A_IWL<49221> A_IWL<49220> A_IWL<49219> A_IWL<49218> A_IWL<49217> A_IWL<49216> A_IWL<49215> A_IWL<49214> A_IWL<49213> A_IWL<49212> A_IWL<49211> A_IWL<49210> A_IWL<49209> A_IWL<49208> A_IWL<49207> A_IWL<49206> A_IWL<49205> A_IWL<49204> A_IWL<49203> A_IWL<49202> A_IWL<49201> A_IWL<49200> A_IWL<49199> A_IWL<49198> A_IWL<49197> A_IWL<49196> A_IWL<49195> A_IWL<49194> A_IWL<49193> A_IWL<49192> A_IWL<49191> A_IWL<49190> A_IWL<49189> A_IWL<49188> A_IWL<49187> A_IWL<49186> A_IWL<49185> A_IWL<49184> A_IWL<49183> A_IWL<49182> A_IWL<49181> A_IWL<49180> A_IWL<49179> A_IWL<49178> A_IWL<49177> A_IWL<49176> A_IWL<49175> A_IWL<49174> A_IWL<49173> A_IWL<49172> A_IWL<49171> A_IWL<49170> A_IWL<49169> A_IWL<49168> A_IWL<49167> A_IWL<49166> A_IWL<49165> A_IWL<49164> A_IWL<49163> A_IWL<49162> A_IWL<49161> A_IWL<49160> A_IWL<49159> A_IWL<49158> A_IWL<49157> A_IWL<49156> A_IWL<49155> A_IWL<49154> A_IWL<49153> A_IWL<49152> A_IWL<50175> A_IWL<50174> A_IWL<50173> A_IWL<50172> A_IWL<50171> A_IWL<50170> A_IWL<50169> A_IWL<50168> A_IWL<50167> A_IWL<50166> A_IWL<50165> A_IWL<50164> A_IWL<50163> A_IWL<50162> A_IWL<50161> A_IWL<50160> A_IWL<50159> A_IWL<50158> A_IWL<50157> A_IWL<50156> A_IWL<50155> A_IWL<50154> A_IWL<50153> A_IWL<50152> A_IWL<50151> A_IWL<50150> A_IWL<50149> A_IWL<50148> A_IWL<50147> A_IWL<50146> A_IWL<50145> A_IWL<50144> A_IWL<50143> A_IWL<50142> A_IWL<50141> A_IWL<50140> A_IWL<50139> A_IWL<50138> A_IWL<50137> A_IWL<50136> A_IWL<50135> A_IWL<50134> A_IWL<50133> A_IWL<50132> A_IWL<50131> A_IWL<50130> A_IWL<50129> A_IWL<50128> A_IWL<50127> A_IWL<50126> A_IWL<50125> A_IWL<50124> A_IWL<50123> A_IWL<50122> A_IWL<50121> A_IWL<50120> A_IWL<50119> A_IWL<50118> A_IWL<50117> A_IWL<50116> A_IWL<50115> A_IWL<50114> A_IWL<50113> A_IWL<50112> A_IWL<50111> A_IWL<50110> A_IWL<50109> A_IWL<50108> A_IWL<50107> A_IWL<50106> A_IWL<50105> A_IWL<50104> A_IWL<50103> A_IWL<50102> A_IWL<50101> A_IWL<50100> A_IWL<50099> A_IWL<50098> A_IWL<50097> A_IWL<50096> A_IWL<50095> A_IWL<50094> A_IWL<50093> A_IWL<50092> A_IWL<50091> A_IWL<50090> A_IWL<50089> A_IWL<50088> A_IWL<50087> A_IWL<50086> A_IWL<50085> A_IWL<50084> A_IWL<50083> A_IWL<50082> A_IWL<50081> A_IWL<50080> A_IWL<50079> A_IWL<50078> A_IWL<50077> A_IWL<50076> A_IWL<50075> A_IWL<50074> A_IWL<50073> A_IWL<50072> A_IWL<50071> A_IWL<50070> A_IWL<50069> A_IWL<50068> A_IWL<50067> A_IWL<50066> A_IWL<50065> A_IWL<50064> A_IWL<50063> A_IWL<50062> A_IWL<50061> A_IWL<50060> A_IWL<50059> A_IWL<50058> A_IWL<50057> A_IWL<50056> A_IWL<50055> A_IWL<50054> A_IWL<50053> A_IWL<50052> A_IWL<50051> A_IWL<50050> A_IWL<50049> A_IWL<50048> A_IWL<50047> A_IWL<50046> A_IWL<50045> A_IWL<50044> A_IWL<50043> A_IWL<50042> A_IWL<50041> A_IWL<50040> A_IWL<50039> A_IWL<50038> A_IWL<50037> A_IWL<50036> A_IWL<50035> A_IWL<50034> A_IWL<50033> A_IWL<50032> A_IWL<50031> A_IWL<50030> A_IWL<50029> A_IWL<50028> A_IWL<50027> A_IWL<50026> A_IWL<50025> A_IWL<50024> A_IWL<50023> A_IWL<50022> A_IWL<50021> A_IWL<50020> A_IWL<50019> A_IWL<50018> A_IWL<50017> A_IWL<50016> A_IWL<50015> A_IWL<50014> A_IWL<50013> A_IWL<50012> A_IWL<50011> A_IWL<50010> A_IWL<50009> A_IWL<50008> A_IWL<50007> A_IWL<50006> A_IWL<50005> A_IWL<50004> A_IWL<50003> A_IWL<50002> A_IWL<50001> A_IWL<50000> A_IWL<49999> A_IWL<49998> A_IWL<49997> A_IWL<49996> A_IWL<49995> A_IWL<49994> A_IWL<49993> A_IWL<49992> A_IWL<49991> A_IWL<49990> A_IWL<49989> A_IWL<49988> A_IWL<49987> A_IWL<49986> A_IWL<49985> A_IWL<49984> A_IWL<49983> A_IWL<49982> A_IWL<49981> A_IWL<49980> A_IWL<49979> A_IWL<49978> A_IWL<49977> A_IWL<49976> A_IWL<49975> A_IWL<49974> A_IWL<49973> A_IWL<49972> A_IWL<49971> A_IWL<49970> A_IWL<49969> A_IWL<49968> A_IWL<49967> A_IWL<49966> A_IWL<49965> A_IWL<49964> A_IWL<49963> A_IWL<49962> A_IWL<49961> A_IWL<49960> A_IWL<49959> A_IWL<49958> A_IWL<49957> A_IWL<49956> A_IWL<49955> A_IWL<49954> A_IWL<49953> A_IWL<49952> A_IWL<49951> A_IWL<49950> A_IWL<49949> A_IWL<49948> A_IWL<49947> A_IWL<49946> A_IWL<49945> A_IWL<49944> A_IWL<49943> A_IWL<49942> A_IWL<49941> A_IWL<49940> A_IWL<49939> A_IWL<49938> A_IWL<49937> A_IWL<49936> A_IWL<49935> A_IWL<49934> A_IWL<49933> A_IWL<49932> A_IWL<49931> A_IWL<49930> A_IWL<49929> A_IWL<49928> A_IWL<49927> A_IWL<49926> A_IWL<49925> A_IWL<49924> A_IWL<49923> A_IWL<49922> A_IWL<49921> A_IWL<49920> A_IWL<49919> A_IWL<49918> A_IWL<49917> A_IWL<49916> A_IWL<49915> A_IWL<49914> A_IWL<49913> A_IWL<49912> A_IWL<49911> A_IWL<49910> A_IWL<49909> A_IWL<49908> A_IWL<49907> A_IWL<49906> A_IWL<49905> A_IWL<49904> A_IWL<49903> A_IWL<49902> A_IWL<49901> A_IWL<49900> A_IWL<49899> A_IWL<49898> A_IWL<49897> A_IWL<49896> A_IWL<49895> A_IWL<49894> A_IWL<49893> A_IWL<49892> A_IWL<49891> A_IWL<49890> A_IWL<49889> A_IWL<49888> A_IWL<49887> A_IWL<49886> A_IWL<49885> A_IWL<49884> A_IWL<49883> A_IWL<49882> A_IWL<49881> A_IWL<49880> A_IWL<49879> A_IWL<49878> A_IWL<49877> A_IWL<49876> A_IWL<49875> A_IWL<49874> A_IWL<49873> A_IWL<49872> A_IWL<49871> A_IWL<49870> A_IWL<49869> A_IWL<49868> A_IWL<49867> A_IWL<49866> A_IWL<49865> A_IWL<49864> A_IWL<49863> A_IWL<49862> A_IWL<49861> A_IWL<49860> A_IWL<49859> A_IWL<49858> A_IWL<49857> A_IWL<49856> A_IWL<49855> A_IWL<49854> A_IWL<49853> A_IWL<49852> A_IWL<49851> A_IWL<49850> A_IWL<49849> A_IWL<49848> A_IWL<49847> A_IWL<49846> A_IWL<49845> A_IWL<49844> A_IWL<49843> A_IWL<49842> A_IWL<49841> A_IWL<49840> A_IWL<49839> A_IWL<49838> A_IWL<49837> A_IWL<49836> A_IWL<49835> A_IWL<49834> A_IWL<49833> A_IWL<49832> A_IWL<49831> A_IWL<49830> A_IWL<49829> A_IWL<49828> A_IWL<49827> A_IWL<49826> A_IWL<49825> A_IWL<49824> A_IWL<49823> A_IWL<49822> A_IWL<49821> A_IWL<49820> A_IWL<49819> A_IWL<49818> A_IWL<49817> A_IWL<49816> A_IWL<49815> A_IWL<49814> A_IWL<49813> A_IWL<49812> A_IWL<49811> A_IWL<49810> A_IWL<49809> A_IWL<49808> A_IWL<49807> A_IWL<49806> A_IWL<49805> A_IWL<49804> A_IWL<49803> A_IWL<49802> A_IWL<49801> A_IWL<49800> A_IWL<49799> A_IWL<49798> A_IWL<49797> A_IWL<49796> A_IWL<49795> A_IWL<49794> A_IWL<49793> A_IWL<49792> A_IWL<49791> A_IWL<49790> A_IWL<49789> A_IWL<49788> A_IWL<49787> A_IWL<49786> A_IWL<49785> A_IWL<49784> A_IWL<49783> A_IWL<49782> A_IWL<49781> A_IWL<49780> A_IWL<49779> A_IWL<49778> A_IWL<49777> A_IWL<49776> A_IWL<49775> A_IWL<49774> A_IWL<49773> A_IWL<49772> A_IWL<49771> A_IWL<49770> A_IWL<49769> A_IWL<49768> A_IWL<49767> A_IWL<49766> A_IWL<49765> A_IWL<49764> A_IWL<49763> A_IWL<49762> A_IWL<49761> A_IWL<49760> A_IWL<49759> A_IWL<49758> A_IWL<49757> A_IWL<49756> A_IWL<49755> A_IWL<49754> A_IWL<49753> A_IWL<49752> A_IWL<49751> A_IWL<49750> A_IWL<49749> A_IWL<49748> A_IWL<49747> A_IWL<49746> A_IWL<49745> A_IWL<49744> A_IWL<49743> A_IWL<49742> A_IWL<49741> A_IWL<49740> A_IWL<49739> A_IWL<49738> A_IWL<49737> A_IWL<49736> A_IWL<49735> A_IWL<49734> A_IWL<49733> A_IWL<49732> A_IWL<49731> A_IWL<49730> A_IWL<49729> A_IWL<49728> A_IWL<49727> A_IWL<49726> A_IWL<49725> A_IWL<49724> A_IWL<49723> A_IWL<49722> A_IWL<49721> A_IWL<49720> A_IWL<49719> A_IWL<49718> A_IWL<49717> A_IWL<49716> A_IWL<49715> A_IWL<49714> A_IWL<49713> A_IWL<49712> A_IWL<49711> A_IWL<49710> A_IWL<49709> A_IWL<49708> A_IWL<49707> A_IWL<49706> A_IWL<49705> A_IWL<49704> A_IWL<49703> A_IWL<49702> A_IWL<49701> A_IWL<49700> A_IWL<49699> A_IWL<49698> A_IWL<49697> A_IWL<49696> A_IWL<49695> A_IWL<49694> A_IWL<49693> A_IWL<49692> A_IWL<49691> A_IWL<49690> A_IWL<49689> A_IWL<49688> A_IWL<49687> A_IWL<49686> A_IWL<49685> A_IWL<49684> A_IWL<49683> A_IWL<49682> A_IWL<49681> A_IWL<49680> A_IWL<49679> A_IWL<49678> A_IWL<49677> A_IWL<49676> A_IWL<49675> A_IWL<49674> A_IWL<49673> A_IWL<49672> A_IWL<49671> A_IWL<49670> A_IWL<49669> A_IWL<49668> A_IWL<49667> A_IWL<49666> A_IWL<49665> A_IWL<49664> VDD_CORE VSS / RM_IHPSG13_8192x32_c4_1P_COLUMN_pcell_0 +XCOL<96> A_BLC<193> A_BLC<192> A_BLC_TOP<193> A_BLC_TOP<192> A_BLT<193> A_BLT<192> A_BLT_TOP<193> A_BLT_TOP<192> A_IWL<49151> A_IWL<49150> A_IWL<49149> A_IWL<49148> A_IWL<49147> A_IWL<49146> A_IWL<49145> A_IWL<49144> A_IWL<49143> A_IWL<49142> A_IWL<49141> A_IWL<49140> A_IWL<49139> A_IWL<49138> A_IWL<49137> A_IWL<49136> A_IWL<49135> A_IWL<49134> A_IWL<49133> A_IWL<49132> A_IWL<49131> A_IWL<49130> A_IWL<49129> A_IWL<49128> A_IWL<49127> A_IWL<49126> A_IWL<49125> A_IWL<49124> A_IWL<49123> A_IWL<49122> A_IWL<49121> A_IWL<49120> A_IWL<49119> A_IWL<49118> A_IWL<49117> A_IWL<49116> A_IWL<49115> A_IWL<49114> A_IWL<49113> A_IWL<49112> A_IWL<49111> A_IWL<49110> A_IWL<49109> A_IWL<49108> A_IWL<49107> A_IWL<49106> A_IWL<49105> A_IWL<49104> A_IWL<49103> A_IWL<49102> A_IWL<49101> A_IWL<49100> A_IWL<49099> A_IWL<49098> A_IWL<49097> A_IWL<49096> A_IWL<49095> A_IWL<49094> A_IWL<49093> A_IWL<49092> A_IWL<49091> A_IWL<49090> A_IWL<49089> A_IWL<49088> A_IWL<49087> A_IWL<49086> A_IWL<49085> A_IWL<49084> A_IWL<49083> A_IWL<49082> A_IWL<49081> A_IWL<49080> A_IWL<49079> A_IWL<49078> A_IWL<49077> A_IWL<49076> A_IWL<49075> A_IWL<49074> A_IWL<49073> A_IWL<49072> A_IWL<49071> A_IWL<49070> A_IWL<49069> A_IWL<49068> A_IWL<49067> A_IWL<49066> A_IWL<49065> A_IWL<49064> A_IWL<49063> A_IWL<49062> A_IWL<49061> A_IWL<49060> A_IWL<49059> A_IWL<49058> A_IWL<49057> A_IWL<49056> A_IWL<49055> A_IWL<49054> A_IWL<49053> A_IWL<49052> A_IWL<49051> A_IWL<49050> A_IWL<49049> A_IWL<49048> A_IWL<49047> A_IWL<49046> A_IWL<49045> A_IWL<49044> A_IWL<49043> A_IWL<49042> A_IWL<49041> A_IWL<49040> A_IWL<49039> A_IWL<49038> A_IWL<49037> A_IWL<49036> A_IWL<49035> A_IWL<49034> A_IWL<49033> A_IWL<49032> A_IWL<49031> A_IWL<49030> A_IWL<49029> A_IWL<49028> A_IWL<49027> A_IWL<49026> A_IWL<49025> A_IWL<49024> A_IWL<49023> A_IWL<49022> A_IWL<49021> A_IWL<49020> A_IWL<49019> A_IWL<49018> A_IWL<49017> A_IWL<49016> A_IWL<49015> A_IWL<49014> A_IWL<49013> A_IWL<49012> A_IWL<49011> A_IWL<49010> A_IWL<49009> A_IWL<49008> A_IWL<49007> A_IWL<49006> A_IWL<49005> A_IWL<49004> A_IWL<49003> A_IWL<49002> A_IWL<49001> A_IWL<49000> A_IWL<48999> A_IWL<48998> A_IWL<48997> A_IWL<48996> A_IWL<48995> A_IWL<48994> A_IWL<48993> A_IWL<48992> A_IWL<48991> A_IWL<48990> A_IWL<48989> A_IWL<48988> A_IWL<48987> A_IWL<48986> A_IWL<48985> A_IWL<48984> A_IWL<48983> A_IWL<48982> A_IWL<48981> A_IWL<48980> A_IWL<48979> A_IWL<48978> A_IWL<48977> A_IWL<48976> A_IWL<48975> A_IWL<48974> A_IWL<48973> A_IWL<48972> A_IWL<48971> A_IWL<48970> A_IWL<48969> A_IWL<48968> A_IWL<48967> A_IWL<48966> A_IWL<48965> A_IWL<48964> A_IWL<48963> A_IWL<48962> A_IWL<48961> A_IWL<48960> A_IWL<48959> A_IWL<48958> A_IWL<48957> A_IWL<48956> A_IWL<48955> A_IWL<48954> A_IWL<48953> A_IWL<48952> A_IWL<48951> A_IWL<48950> A_IWL<48949> A_IWL<48948> A_IWL<48947> A_IWL<48946> A_IWL<48945> A_IWL<48944> A_IWL<48943> A_IWL<48942> A_IWL<48941> A_IWL<48940> A_IWL<48939> A_IWL<48938> A_IWL<48937> A_IWL<48936> A_IWL<48935> A_IWL<48934> A_IWL<48933> A_IWL<48932> A_IWL<48931> A_IWL<48930> A_IWL<48929> A_IWL<48928> A_IWL<48927> A_IWL<48926> A_IWL<48925> A_IWL<48924> A_IWL<48923> A_IWL<48922> A_IWL<48921> A_IWL<48920> A_IWL<48919> A_IWL<48918> A_IWL<48917> A_IWL<48916> A_IWL<48915> A_IWL<48914> A_IWL<48913> A_IWL<48912> A_IWL<48911> A_IWL<48910> A_IWL<48909> A_IWL<48908> A_IWL<48907> A_IWL<48906> A_IWL<48905> A_IWL<48904> A_IWL<48903> A_IWL<48902> A_IWL<48901> A_IWL<48900> A_IWL<48899> A_IWL<48898> A_IWL<48897> A_IWL<48896> A_IWL<48895> A_IWL<48894> A_IWL<48893> A_IWL<48892> A_IWL<48891> A_IWL<48890> A_IWL<48889> A_IWL<48888> A_IWL<48887> A_IWL<48886> A_IWL<48885> A_IWL<48884> A_IWL<48883> A_IWL<48882> A_IWL<48881> A_IWL<48880> A_IWL<48879> A_IWL<48878> A_IWL<48877> A_IWL<48876> A_IWL<48875> A_IWL<48874> A_IWL<48873> A_IWL<48872> A_IWL<48871> A_IWL<48870> A_IWL<48869> A_IWL<48868> A_IWL<48867> A_IWL<48866> A_IWL<48865> A_IWL<48864> A_IWL<48863> A_IWL<48862> A_IWL<48861> A_IWL<48860> A_IWL<48859> A_IWL<48858> A_IWL<48857> A_IWL<48856> A_IWL<48855> A_IWL<48854> A_IWL<48853> A_IWL<48852> A_IWL<48851> A_IWL<48850> A_IWL<48849> A_IWL<48848> A_IWL<48847> A_IWL<48846> A_IWL<48845> A_IWL<48844> A_IWL<48843> A_IWL<48842> A_IWL<48841> A_IWL<48840> A_IWL<48839> A_IWL<48838> A_IWL<48837> A_IWL<48836> A_IWL<48835> A_IWL<48834> A_IWL<48833> A_IWL<48832> A_IWL<48831> A_IWL<48830> A_IWL<48829> A_IWL<48828> A_IWL<48827> A_IWL<48826> A_IWL<48825> A_IWL<48824> A_IWL<48823> A_IWL<48822> A_IWL<48821> A_IWL<48820> A_IWL<48819> A_IWL<48818> A_IWL<48817> A_IWL<48816> A_IWL<48815> A_IWL<48814> A_IWL<48813> A_IWL<48812> A_IWL<48811> A_IWL<48810> A_IWL<48809> A_IWL<48808> A_IWL<48807> A_IWL<48806> A_IWL<48805> A_IWL<48804> A_IWL<48803> A_IWL<48802> A_IWL<48801> A_IWL<48800> A_IWL<48799> A_IWL<48798> A_IWL<48797> A_IWL<48796> A_IWL<48795> A_IWL<48794> A_IWL<48793> A_IWL<48792> A_IWL<48791> A_IWL<48790> A_IWL<48789> A_IWL<48788> A_IWL<48787> A_IWL<48786> A_IWL<48785> A_IWL<48784> A_IWL<48783> A_IWL<48782> A_IWL<48781> A_IWL<48780> A_IWL<48779> A_IWL<48778> A_IWL<48777> A_IWL<48776> A_IWL<48775> A_IWL<48774> A_IWL<48773> A_IWL<48772> A_IWL<48771> A_IWL<48770> A_IWL<48769> A_IWL<48768> A_IWL<48767> A_IWL<48766> A_IWL<48765> A_IWL<48764> A_IWL<48763> A_IWL<48762> A_IWL<48761> A_IWL<48760> A_IWL<48759> A_IWL<48758> A_IWL<48757> A_IWL<48756> A_IWL<48755> A_IWL<48754> A_IWL<48753> A_IWL<48752> A_IWL<48751> A_IWL<48750> A_IWL<48749> A_IWL<48748> A_IWL<48747> A_IWL<48746> A_IWL<48745> A_IWL<48744> A_IWL<48743> A_IWL<48742> A_IWL<48741> A_IWL<48740> A_IWL<48739> A_IWL<48738> A_IWL<48737> A_IWL<48736> A_IWL<48735> A_IWL<48734> A_IWL<48733> A_IWL<48732> A_IWL<48731> A_IWL<48730> A_IWL<48729> A_IWL<48728> A_IWL<48727> A_IWL<48726> A_IWL<48725> A_IWL<48724> A_IWL<48723> A_IWL<48722> A_IWL<48721> A_IWL<48720> A_IWL<48719> A_IWL<48718> A_IWL<48717> A_IWL<48716> A_IWL<48715> A_IWL<48714> A_IWL<48713> A_IWL<48712> A_IWL<48711> A_IWL<48710> A_IWL<48709> A_IWL<48708> A_IWL<48707> A_IWL<48706> A_IWL<48705> A_IWL<48704> A_IWL<48703> A_IWL<48702> A_IWL<48701> A_IWL<48700> A_IWL<48699> A_IWL<48698> A_IWL<48697> A_IWL<48696> A_IWL<48695> A_IWL<48694> A_IWL<48693> A_IWL<48692> A_IWL<48691> A_IWL<48690> A_IWL<48689> A_IWL<48688> A_IWL<48687> A_IWL<48686> A_IWL<48685> A_IWL<48684> A_IWL<48683> A_IWL<48682> A_IWL<48681> A_IWL<48680> A_IWL<48679> A_IWL<48678> A_IWL<48677> A_IWL<48676> A_IWL<48675> A_IWL<48674> A_IWL<48673> A_IWL<48672> A_IWL<48671> A_IWL<48670> A_IWL<48669> A_IWL<48668> A_IWL<48667> A_IWL<48666> A_IWL<48665> A_IWL<48664> A_IWL<48663> A_IWL<48662> A_IWL<48661> A_IWL<48660> A_IWL<48659> A_IWL<48658> A_IWL<48657> A_IWL<48656> A_IWL<48655> A_IWL<48654> A_IWL<48653> A_IWL<48652> A_IWL<48651> A_IWL<48650> A_IWL<48649> A_IWL<48648> A_IWL<48647> A_IWL<48646> A_IWL<48645> A_IWL<48644> A_IWL<48643> A_IWL<48642> A_IWL<48641> A_IWL<48640> A_IWL<49663> A_IWL<49662> A_IWL<49661> A_IWL<49660> A_IWL<49659> A_IWL<49658> A_IWL<49657> A_IWL<49656> A_IWL<49655> A_IWL<49654> A_IWL<49653> A_IWL<49652> A_IWL<49651> A_IWL<49650> A_IWL<49649> A_IWL<49648> A_IWL<49647> A_IWL<49646> A_IWL<49645> A_IWL<49644> A_IWL<49643> A_IWL<49642> A_IWL<49641> A_IWL<49640> A_IWL<49639> A_IWL<49638> A_IWL<49637> A_IWL<49636> A_IWL<49635> A_IWL<49634> A_IWL<49633> A_IWL<49632> A_IWL<49631> A_IWL<49630> A_IWL<49629> A_IWL<49628> A_IWL<49627> A_IWL<49626> A_IWL<49625> A_IWL<49624> A_IWL<49623> A_IWL<49622> A_IWL<49621> A_IWL<49620> A_IWL<49619> A_IWL<49618> A_IWL<49617> A_IWL<49616> A_IWL<49615> A_IWL<49614> A_IWL<49613> A_IWL<49612> A_IWL<49611> A_IWL<49610> A_IWL<49609> A_IWL<49608> A_IWL<49607> A_IWL<49606> A_IWL<49605> A_IWL<49604> A_IWL<49603> A_IWL<49602> A_IWL<49601> A_IWL<49600> A_IWL<49599> A_IWL<49598> A_IWL<49597> A_IWL<49596> A_IWL<49595> A_IWL<49594> A_IWL<49593> A_IWL<49592> A_IWL<49591> A_IWL<49590> A_IWL<49589> A_IWL<49588> A_IWL<49587> A_IWL<49586> A_IWL<49585> A_IWL<49584> A_IWL<49583> A_IWL<49582> A_IWL<49581> A_IWL<49580> A_IWL<49579> A_IWL<49578> A_IWL<49577> A_IWL<49576> A_IWL<49575> A_IWL<49574> A_IWL<49573> A_IWL<49572> A_IWL<49571> A_IWL<49570> A_IWL<49569> A_IWL<49568> A_IWL<49567> A_IWL<49566> A_IWL<49565> A_IWL<49564> A_IWL<49563> A_IWL<49562> A_IWL<49561> A_IWL<49560> A_IWL<49559> A_IWL<49558> A_IWL<49557> A_IWL<49556> A_IWL<49555> A_IWL<49554> A_IWL<49553> A_IWL<49552> A_IWL<49551> A_IWL<49550> A_IWL<49549> A_IWL<49548> A_IWL<49547> A_IWL<49546> A_IWL<49545> A_IWL<49544> A_IWL<49543> A_IWL<49542> A_IWL<49541> A_IWL<49540> A_IWL<49539> A_IWL<49538> A_IWL<49537> A_IWL<49536> A_IWL<49535> A_IWL<49534> A_IWL<49533> A_IWL<49532> A_IWL<49531> A_IWL<49530> A_IWL<49529> A_IWL<49528> A_IWL<49527> A_IWL<49526> A_IWL<49525> A_IWL<49524> A_IWL<49523> A_IWL<49522> A_IWL<49521> A_IWL<49520> A_IWL<49519> A_IWL<49518> A_IWL<49517> A_IWL<49516> A_IWL<49515> A_IWL<49514> A_IWL<49513> A_IWL<49512> A_IWL<49511> A_IWL<49510> A_IWL<49509> A_IWL<49508> A_IWL<49507> A_IWL<49506> A_IWL<49505> A_IWL<49504> A_IWL<49503> A_IWL<49502> A_IWL<49501> A_IWL<49500> A_IWL<49499> A_IWL<49498> A_IWL<49497> A_IWL<49496> A_IWL<49495> A_IWL<49494> A_IWL<49493> A_IWL<49492> A_IWL<49491> A_IWL<49490> A_IWL<49489> A_IWL<49488> A_IWL<49487> A_IWL<49486> A_IWL<49485> A_IWL<49484> A_IWL<49483> A_IWL<49482> A_IWL<49481> A_IWL<49480> A_IWL<49479> A_IWL<49478> A_IWL<49477> A_IWL<49476> A_IWL<49475> A_IWL<49474> A_IWL<49473> A_IWL<49472> A_IWL<49471> A_IWL<49470> A_IWL<49469> A_IWL<49468> A_IWL<49467> A_IWL<49466> A_IWL<49465> A_IWL<49464> A_IWL<49463> A_IWL<49462> A_IWL<49461> A_IWL<49460> A_IWL<49459> A_IWL<49458> A_IWL<49457> A_IWL<49456> A_IWL<49455> A_IWL<49454> A_IWL<49453> A_IWL<49452> A_IWL<49451> A_IWL<49450> A_IWL<49449> A_IWL<49448> A_IWL<49447> A_IWL<49446> A_IWL<49445> A_IWL<49444> A_IWL<49443> A_IWL<49442> A_IWL<49441> A_IWL<49440> A_IWL<49439> A_IWL<49438> A_IWL<49437> A_IWL<49436> A_IWL<49435> A_IWL<49434> A_IWL<49433> A_IWL<49432> A_IWL<49431> A_IWL<49430> A_IWL<49429> A_IWL<49428> A_IWL<49427> A_IWL<49426> A_IWL<49425> A_IWL<49424> A_IWL<49423> A_IWL<49422> A_IWL<49421> A_IWL<49420> A_IWL<49419> A_IWL<49418> A_IWL<49417> A_IWL<49416> A_IWL<49415> A_IWL<49414> A_IWL<49413> A_IWL<49412> A_IWL<49411> A_IWL<49410> A_IWL<49409> A_IWL<49408> A_IWL<49407> A_IWL<49406> A_IWL<49405> A_IWL<49404> A_IWL<49403> A_IWL<49402> A_IWL<49401> A_IWL<49400> A_IWL<49399> A_IWL<49398> A_IWL<49397> A_IWL<49396> A_IWL<49395> A_IWL<49394> A_IWL<49393> A_IWL<49392> A_IWL<49391> A_IWL<49390> A_IWL<49389> A_IWL<49388> A_IWL<49387> A_IWL<49386> A_IWL<49385> A_IWL<49384> A_IWL<49383> A_IWL<49382> A_IWL<49381> A_IWL<49380> A_IWL<49379> A_IWL<49378> A_IWL<49377> A_IWL<49376> A_IWL<49375> A_IWL<49374> A_IWL<49373> A_IWL<49372> A_IWL<49371> A_IWL<49370> A_IWL<49369> A_IWL<49368> A_IWL<49367> A_IWL<49366> A_IWL<49365> A_IWL<49364> A_IWL<49363> A_IWL<49362> A_IWL<49361> A_IWL<49360> A_IWL<49359> A_IWL<49358> A_IWL<49357> A_IWL<49356> A_IWL<49355> A_IWL<49354> A_IWL<49353> A_IWL<49352> A_IWL<49351> A_IWL<49350> A_IWL<49349> A_IWL<49348> A_IWL<49347> A_IWL<49346> A_IWL<49345> A_IWL<49344> A_IWL<49343> A_IWL<49342> A_IWL<49341> A_IWL<49340> A_IWL<49339> A_IWL<49338> A_IWL<49337> A_IWL<49336> A_IWL<49335> A_IWL<49334> A_IWL<49333> A_IWL<49332> A_IWL<49331> A_IWL<49330> A_IWL<49329> A_IWL<49328> A_IWL<49327> A_IWL<49326> A_IWL<49325> A_IWL<49324> A_IWL<49323> A_IWL<49322> A_IWL<49321> A_IWL<49320> A_IWL<49319> A_IWL<49318> A_IWL<49317> A_IWL<49316> A_IWL<49315> A_IWL<49314> A_IWL<49313> A_IWL<49312> A_IWL<49311> A_IWL<49310> A_IWL<49309> A_IWL<49308> A_IWL<49307> A_IWL<49306> A_IWL<49305> A_IWL<49304> A_IWL<49303> A_IWL<49302> A_IWL<49301> A_IWL<49300> A_IWL<49299> A_IWL<49298> A_IWL<49297> A_IWL<49296> A_IWL<49295> A_IWL<49294> A_IWL<49293> A_IWL<49292> A_IWL<49291> A_IWL<49290> A_IWL<49289> A_IWL<49288> A_IWL<49287> A_IWL<49286> A_IWL<49285> A_IWL<49284> A_IWL<49283> A_IWL<49282> A_IWL<49281> A_IWL<49280> A_IWL<49279> A_IWL<49278> A_IWL<49277> A_IWL<49276> A_IWL<49275> A_IWL<49274> A_IWL<49273> A_IWL<49272> A_IWL<49271> A_IWL<49270> A_IWL<49269> A_IWL<49268> A_IWL<49267> A_IWL<49266> A_IWL<49265> A_IWL<49264> A_IWL<49263> A_IWL<49262> A_IWL<49261> A_IWL<49260> A_IWL<49259> A_IWL<49258> A_IWL<49257> A_IWL<49256> A_IWL<49255> A_IWL<49254> A_IWL<49253> A_IWL<49252> A_IWL<49251> A_IWL<49250> A_IWL<49249> A_IWL<49248> A_IWL<49247> A_IWL<49246> A_IWL<49245> A_IWL<49244> A_IWL<49243> A_IWL<49242> A_IWL<49241> A_IWL<49240> A_IWL<49239> A_IWL<49238> A_IWL<49237> A_IWL<49236> A_IWL<49235> A_IWL<49234> A_IWL<49233> A_IWL<49232> A_IWL<49231> A_IWL<49230> A_IWL<49229> A_IWL<49228> A_IWL<49227> A_IWL<49226> A_IWL<49225> A_IWL<49224> A_IWL<49223> A_IWL<49222> A_IWL<49221> A_IWL<49220> A_IWL<49219> A_IWL<49218> A_IWL<49217> A_IWL<49216> A_IWL<49215> A_IWL<49214> A_IWL<49213> A_IWL<49212> A_IWL<49211> A_IWL<49210> A_IWL<49209> A_IWL<49208> A_IWL<49207> A_IWL<49206> A_IWL<49205> A_IWL<49204> A_IWL<49203> A_IWL<49202> A_IWL<49201> A_IWL<49200> A_IWL<49199> A_IWL<49198> A_IWL<49197> A_IWL<49196> A_IWL<49195> A_IWL<49194> A_IWL<49193> A_IWL<49192> A_IWL<49191> A_IWL<49190> A_IWL<49189> A_IWL<49188> A_IWL<49187> A_IWL<49186> A_IWL<49185> A_IWL<49184> A_IWL<49183> A_IWL<49182> A_IWL<49181> A_IWL<49180> A_IWL<49179> A_IWL<49178> A_IWL<49177> A_IWL<49176> A_IWL<49175> A_IWL<49174> A_IWL<49173> A_IWL<49172> A_IWL<49171> A_IWL<49170> A_IWL<49169> A_IWL<49168> A_IWL<49167> A_IWL<49166> A_IWL<49165> A_IWL<49164> A_IWL<49163> A_IWL<49162> A_IWL<49161> A_IWL<49160> A_IWL<49159> A_IWL<49158> A_IWL<49157> A_IWL<49156> A_IWL<49155> A_IWL<49154> A_IWL<49153> A_IWL<49152> VDD_CORE VSS / RM_IHPSG13_8192x32_c4_1P_COLUMN_pcell_0 +XCOL<95> A_BLC<191> A_BLC<190> A_BLC_TOP<191> A_BLC_TOP<190> A_BLT<191> A_BLT<190> A_BLT_TOP<191> A_BLT_TOP<190> A_IWL<48639> A_IWL<48638> A_IWL<48637> A_IWL<48636> A_IWL<48635> A_IWL<48634> A_IWL<48633> A_IWL<48632> A_IWL<48631> A_IWL<48630> A_IWL<48629> A_IWL<48628> A_IWL<48627> A_IWL<48626> A_IWL<48625> A_IWL<48624> A_IWL<48623> A_IWL<48622> A_IWL<48621> A_IWL<48620> A_IWL<48619> A_IWL<48618> A_IWL<48617> A_IWL<48616> A_IWL<48615> A_IWL<48614> A_IWL<48613> A_IWL<48612> A_IWL<48611> A_IWL<48610> A_IWL<48609> A_IWL<48608> A_IWL<48607> A_IWL<48606> A_IWL<48605> A_IWL<48604> A_IWL<48603> A_IWL<48602> A_IWL<48601> A_IWL<48600> A_IWL<48599> A_IWL<48598> A_IWL<48597> A_IWL<48596> A_IWL<48595> A_IWL<48594> A_IWL<48593> A_IWL<48592> A_IWL<48591> A_IWL<48590> A_IWL<48589> A_IWL<48588> A_IWL<48587> A_IWL<48586> A_IWL<48585> A_IWL<48584> A_IWL<48583> A_IWL<48582> A_IWL<48581> A_IWL<48580> A_IWL<48579> A_IWL<48578> A_IWL<48577> A_IWL<48576> A_IWL<48575> A_IWL<48574> A_IWL<48573> A_IWL<48572> A_IWL<48571> A_IWL<48570> A_IWL<48569> A_IWL<48568> A_IWL<48567> A_IWL<48566> A_IWL<48565> A_IWL<48564> A_IWL<48563> A_IWL<48562> A_IWL<48561> A_IWL<48560> A_IWL<48559> A_IWL<48558> A_IWL<48557> A_IWL<48556> A_IWL<48555> A_IWL<48554> A_IWL<48553> A_IWL<48552> A_IWL<48551> A_IWL<48550> A_IWL<48549> A_IWL<48548> A_IWL<48547> A_IWL<48546> A_IWL<48545> A_IWL<48544> A_IWL<48543> A_IWL<48542> A_IWL<48541> A_IWL<48540> A_IWL<48539> A_IWL<48538> A_IWL<48537> A_IWL<48536> A_IWL<48535> A_IWL<48534> A_IWL<48533> A_IWL<48532> A_IWL<48531> A_IWL<48530> A_IWL<48529> A_IWL<48528> A_IWL<48527> A_IWL<48526> A_IWL<48525> A_IWL<48524> A_IWL<48523> A_IWL<48522> A_IWL<48521> A_IWL<48520> A_IWL<48519> A_IWL<48518> A_IWL<48517> A_IWL<48516> A_IWL<48515> A_IWL<48514> A_IWL<48513> A_IWL<48512> A_IWL<48511> A_IWL<48510> A_IWL<48509> A_IWL<48508> A_IWL<48507> A_IWL<48506> A_IWL<48505> A_IWL<48504> A_IWL<48503> A_IWL<48502> A_IWL<48501> A_IWL<48500> A_IWL<48499> A_IWL<48498> A_IWL<48497> A_IWL<48496> A_IWL<48495> A_IWL<48494> A_IWL<48493> A_IWL<48492> A_IWL<48491> A_IWL<48490> A_IWL<48489> A_IWL<48488> A_IWL<48487> A_IWL<48486> A_IWL<48485> A_IWL<48484> A_IWL<48483> A_IWL<48482> A_IWL<48481> A_IWL<48480> A_IWL<48479> A_IWL<48478> A_IWL<48477> A_IWL<48476> A_IWL<48475> A_IWL<48474> A_IWL<48473> A_IWL<48472> A_IWL<48471> A_IWL<48470> A_IWL<48469> A_IWL<48468> A_IWL<48467> A_IWL<48466> A_IWL<48465> A_IWL<48464> A_IWL<48463> A_IWL<48462> A_IWL<48461> A_IWL<48460> A_IWL<48459> A_IWL<48458> A_IWL<48457> A_IWL<48456> A_IWL<48455> A_IWL<48454> A_IWL<48453> A_IWL<48452> A_IWL<48451> A_IWL<48450> A_IWL<48449> A_IWL<48448> A_IWL<48447> A_IWL<48446> A_IWL<48445> A_IWL<48444> A_IWL<48443> A_IWL<48442> A_IWL<48441> A_IWL<48440> A_IWL<48439> A_IWL<48438> A_IWL<48437> A_IWL<48436> A_IWL<48435> A_IWL<48434> A_IWL<48433> A_IWL<48432> A_IWL<48431> A_IWL<48430> A_IWL<48429> A_IWL<48428> A_IWL<48427> A_IWL<48426> A_IWL<48425> A_IWL<48424> A_IWL<48423> A_IWL<48422> A_IWL<48421> A_IWL<48420> A_IWL<48419> A_IWL<48418> A_IWL<48417> A_IWL<48416> A_IWL<48415> A_IWL<48414> A_IWL<48413> A_IWL<48412> A_IWL<48411> A_IWL<48410> A_IWL<48409> A_IWL<48408> A_IWL<48407> A_IWL<48406> A_IWL<48405> A_IWL<48404> A_IWL<48403> A_IWL<48402> A_IWL<48401> A_IWL<48400> A_IWL<48399> A_IWL<48398> A_IWL<48397> A_IWL<48396> A_IWL<48395> A_IWL<48394> A_IWL<48393> A_IWL<48392> A_IWL<48391> A_IWL<48390> A_IWL<48389> A_IWL<48388> A_IWL<48387> A_IWL<48386> A_IWL<48385> A_IWL<48384> A_IWL<48383> A_IWL<48382> A_IWL<48381> A_IWL<48380> A_IWL<48379> A_IWL<48378> A_IWL<48377> A_IWL<48376> A_IWL<48375> A_IWL<48374> A_IWL<48373> A_IWL<48372> A_IWL<48371> A_IWL<48370> A_IWL<48369> A_IWL<48368> A_IWL<48367> A_IWL<48366> A_IWL<48365> A_IWL<48364> A_IWL<48363> A_IWL<48362> A_IWL<48361> A_IWL<48360> A_IWL<48359> A_IWL<48358> A_IWL<48357> A_IWL<48356> A_IWL<48355> A_IWL<48354> A_IWL<48353> A_IWL<48352> A_IWL<48351> A_IWL<48350> A_IWL<48349> A_IWL<48348> A_IWL<48347> A_IWL<48346> A_IWL<48345> A_IWL<48344> A_IWL<48343> A_IWL<48342> A_IWL<48341> A_IWL<48340> A_IWL<48339> A_IWL<48338> A_IWL<48337> A_IWL<48336> A_IWL<48335> A_IWL<48334> A_IWL<48333> A_IWL<48332> A_IWL<48331> A_IWL<48330> A_IWL<48329> A_IWL<48328> A_IWL<48327> A_IWL<48326> A_IWL<48325> A_IWL<48324> A_IWL<48323> A_IWL<48322> A_IWL<48321> A_IWL<48320> A_IWL<48319> A_IWL<48318> A_IWL<48317> A_IWL<48316> A_IWL<48315> A_IWL<48314> A_IWL<48313> A_IWL<48312> A_IWL<48311> A_IWL<48310> A_IWL<48309> A_IWL<48308> A_IWL<48307> A_IWL<48306> A_IWL<48305> A_IWL<48304> A_IWL<48303> A_IWL<48302> A_IWL<48301> A_IWL<48300> A_IWL<48299> A_IWL<48298> A_IWL<48297> A_IWL<48296> A_IWL<48295> A_IWL<48294> A_IWL<48293> A_IWL<48292> A_IWL<48291> A_IWL<48290> A_IWL<48289> A_IWL<48288> A_IWL<48287> A_IWL<48286> A_IWL<48285> A_IWL<48284> A_IWL<48283> A_IWL<48282> A_IWL<48281> A_IWL<48280> A_IWL<48279> A_IWL<48278> A_IWL<48277> A_IWL<48276> A_IWL<48275> A_IWL<48274> A_IWL<48273> A_IWL<48272> A_IWL<48271> A_IWL<48270> A_IWL<48269> A_IWL<48268> A_IWL<48267> A_IWL<48266> A_IWL<48265> A_IWL<48264> A_IWL<48263> A_IWL<48262> A_IWL<48261> A_IWL<48260> A_IWL<48259> A_IWL<48258> A_IWL<48257> A_IWL<48256> A_IWL<48255> A_IWL<48254> A_IWL<48253> A_IWL<48252> A_IWL<48251> A_IWL<48250> A_IWL<48249> A_IWL<48248> A_IWL<48247> A_IWL<48246> A_IWL<48245> A_IWL<48244> A_IWL<48243> A_IWL<48242> A_IWL<48241> A_IWL<48240> A_IWL<48239> A_IWL<48238> A_IWL<48237> A_IWL<48236> A_IWL<48235> A_IWL<48234> A_IWL<48233> A_IWL<48232> A_IWL<48231> A_IWL<48230> A_IWL<48229> A_IWL<48228> A_IWL<48227> A_IWL<48226> A_IWL<48225> A_IWL<48224> A_IWL<48223> A_IWL<48222> A_IWL<48221> A_IWL<48220> A_IWL<48219> A_IWL<48218> A_IWL<48217> A_IWL<48216> A_IWL<48215> A_IWL<48214> A_IWL<48213> A_IWL<48212> A_IWL<48211> A_IWL<48210> A_IWL<48209> A_IWL<48208> A_IWL<48207> A_IWL<48206> A_IWL<48205> A_IWL<48204> A_IWL<48203> A_IWL<48202> A_IWL<48201> A_IWL<48200> A_IWL<48199> A_IWL<48198> A_IWL<48197> A_IWL<48196> A_IWL<48195> A_IWL<48194> A_IWL<48193> A_IWL<48192> A_IWL<48191> A_IWL<48190> A_IWL<48189> A_IWL<48188> A_IWL<48187> A_IWL<48186> A_IWL<48185> A_IWL<48184> A_IWL<48183> A_IWL<48182> A_IWL<48181> A_IWL<48180> A_IWL<48179> A_IWL<48178> A_IWL<48177> A_IWL<48176> A_IWL<48175> A_IWL<48174> A_IWL<48173> A_IWL<48172> A_IWL<48171> A_IWL<48170> A_IWL<48169> A_IWL<48168> A_IWL<48167> A_IWL<48166> A_IWL<48165> A_IWL<48164> A_IWL<48163> A_IWL<48162> A_IWL<48161> A_IWL<48160> A_IWL<48159> A_IWL<48158> A_IWL<48157> A_IWL<48156> A_IWL<48155> A_IWL<48154> A_IWL<48153> A_IWL<48152> A_IWL<48151> A_IWL<48150> A_IWL<48149> A_IWL<48148> A_IWL<48147> A_IWL<48146> A_IWL<48145> A_IWL<48144> A_IWL<48143> A_IWL<48142> A_IWL<48141> A_IWL<48140> A_IWL<48139> A_IWL<48138> A_IWL<48137> A_IWL<48136> A_IWL<48135> A_IWL<48134> A_IWL<48133> A_IWL<48132> A_IWL<48131> A_IWL<48130> A_IWL<48129> A_IWL<48128> A_IWL<49151> A_IWL<49150> A_IWL<49149> A_IWL<49148> A_IWL<49147> A_IWL<49146> A_IWL<49145> A_IWL<49144> A_IWL<49143> A_IWL<49142> A_IWL<49141> A_IWL<49140> A_IWL<49139> A_IWL<49138> A_IWL<49137> A_IWL<49136> A_IWL<49135> A_IWL<49134> A_IWL<49133> A_IWL<49132> A_IWL<49131> A_IWL<49130> A_IWL<49129> A_IWL<49128> A_IWL<49127> A_IWL<49126> A_IWL<49125> A_IWL<49124> A_IWL<49123> A_IWL<49122> A_IWL<49121> A_IWL<49120> A_IWL<49119> A_IWL<49118> A_IWL<49117> A_IWL<49116> A_IWL<49115> A_IWL<49114> A_IWL<49113> A_IWL<49112> A_IWL<49111> A_IWL<49110> A_IWL<49109> A_IWL<49108> A_IWL<49107> A_IWL<49106> A_IWL<49105> A_IWL<49104> A_IWL<49103> A_IWL<49102> A_IWL<49101> A_IWL<49100> A_IWL<49099> A_IWL<49098> A_IWL<49097> A_IWL<49096> A_IWL<49095> A_IWL<49094> A_IWL<49093> A_IWL<49092> A_IWL<49091> A_IWL<49090> A_IWL<49089> A_IWL<49088> A_IWL<49087> A_IWL<49086> A_IWL<49085> A_IWL<49084> A_IWL<49083> A_IWL<49082> A_IWL<49081> A_IWL<49080> A_IWL<49079> A_IWL<49078> A_IWL<49077> A_IWL<49076> A_IWL<49075> A_IWL<49074> A_IWL<49073> A_IWL<49072> A_IWL<49071> A_IWL<49070> A_IWL<49069> A_IWL<49068> A_IWL<49067> A_IWL<49066> A_IWL<49065> A_IWL<49064> A_IWL<49063> A_IWL<49062> A_IWL<49061> A_IWL<49060> A_IWL<49059> A_IWL<49058> A_IWL<49057> A_IWL<49056> A_IWL<49055> A_IWL<49054> A_IWL<49053> A_IWL<49052> A_IWL<49051> A_IWL<49050> A_IWL<49049> A_IWL<49048> A_IWL<49047> A_IWL<49046> A_IWL<49045> A_IWL<49044> A_IWL<49043> A_IWL<49042> A_IWL<49041> A_IWL<49040> A_IWL<49039> A_IWL<49038> A_IWL<49037> A_IWL<49036> A_IWL<49035> A_IWL<49034> A_IWL<49033> A_IWL<49032> A_IWL<49031> A_IWL<49030> A_IWL<49029> A_IWL<49028> A_IWL<49027> A_IWL<49026> A_IWL<49025> A_IWL<49024> A_IWL<49023> A_IWL<49022> A_IWL<49021> A_IWL<49020> A_IWL<49019> A_IWL<49018> A_IWL<49017> A_IWL<49016> A_IWL<49015> A_IWL<49014> A_IWL<49013> A_IWL<49012> A_IWL<49011> A_IWL<49010> A_IWL<49009> A_IWL<49008> A_IWL<49007> A_IWL<49006> A_IWL<49005> A_IWL<49004> A_IWL<49003> A_IWL<49002> A_IWL<49001> A_IWL<49000> A_IWL<48999> A_IWL<48998> A_IWL<48997> A_IWL<48996> A_IWL<48995> A_IWL<48994> A_IWL<48993> A_IWL<48992> A_IWL<48991> A_IWL<48990> A_IWL<48989> A_IWL<48988> A_IWL<48987> A_IWL<48986> A_IWL<48985> A_IWL<48984> A_IWL<48983> A_IWL<48982> A_IWL<48981> A_IWL<48980> A_IWL<48979> A_IWL<48978> A_IWL<48977> A_IWL<48976> A_IWL<48975> A_IWL<48974> A_IWL<48973> A_IWL<48972> A_IWL<48971> A_IWL<48970> A_IWL<48969> A_IWL<48968> A_IWL<48967> A_IWL<48966> A_IWL<48965> A_IWL<48964> A_IWL<48963> A_IWL<48962> A_IWL<48961> A_IWL<48960> A_IWL<48959> A_IWL<48958> A_IWL<48957> A_IWL<48956> A_IWL<48955> A_IWL<48954> A_IWL<48953> A_IWL<48952> A_IWL<48951> A_IWL<48950> A_IWL<48949> A_IWL<48948> A_IWL<48947> A_IWL<48946> A_IWL<48945> A_IWL<48944> A_IWL<48943> A_IWL<48942> A_IWL<48941> A_IWL<48940> A_IWL<48939> A_IWL<48938> A_IWL<48937> A_IWL<48936> A_IWL<48935> A_IWL<48934> A_IWL<48933> A_IWL<48932> A_IWL<48931> A_IWL<48930> A_IWL<48929> A_IWL<48928> A_IWL<48927> A_IWL<48926> A_IWL<48925> A_IWL<48924> A_IWL<48923> A_IWL<48922> A_IWL<48921> A_IWL<48920> A_IWL<48919> A_IWL<48918> A_IWL<48917> A_IWL<48916> A_IWL<48915> A_IWL<48914> A_IWL<48913> A_IWL<48912> A_IWL<48911> A_IWL<48910> A_IWL<48909> A_IWL<48908> A_IWL<48907> A_IWL<48906> A_IWL<48905> A_IWL<48904> A_IWL<48903> A_IWL<48902> A_IWL<48901> A_IWL<48900> A_IWL<48899> A_IWL<48898> A_IWL<48897> A_IWL<48896> A_IWL<48895> A_IWL<48894> A_IWL<48893> A_IWL<48892> A_IWL<48891> A_IWL<48890> A_IWL<48889> A_IWL<48888> A_IWL<48887> A_IWL<48886> A_IWL<48885> A_IWL<48884> A_IWL<48883> A_IWL<48882> A_IWL<48881> A_IWL<48880> A_IWL<48879> A_IWL<48878> A_IWL<48877> A_IWL<48876> A_IWL<48875> A_IWL<48874> A_IWL<48873> A_IWL<48872> A_IWL<48871> A_IWL<48870> A_IWL<48869> A_IWL<48868> A_IWL<48867> A_IWL<48866> A_IWL<48865> A_IWL<48864> A_IWL<48863> A_IWL<48862> A_IWL<48861> A_IWL<48860> A_IWL<48859> A_IWL<48858> A_IWL<48857> A_IWL<48856> A_IWL<48855> A_IWL<48854> A_IWL<48853> A_IWL<48852> A_IWL<48851> A_IWL<48850> A_IWL<48849> A_IWL<48848> A_IWL<48847> A_IWL<48846> A_IWL<48845> A_IWL<48844> A_IWL<48843> A_IWL<48842> A_IWL<48841> A_IWL<48840> A_IWL<48839> A_IWL<48838> A_IWL<48837> A_IWL<48836> A_IWL<48835> A_IWL<48834> A_IWL<48833> A_IWL<48832> A_IWL<48831> A_IWL<48830> A_IWL<48829> A_IWL<48828> A_IWL<48827> A_IWL<48826> A_IWL<48825> A_IWL<48824> A_IWL<48823> A_IWL<48822> A_IWL<48821> A_IWL<48820> A_IWL<48819> A_IWL<48818> A_IWL<48817> A_IWL<48816> A_IWL<48815> A_IWL<48814> A_IWL<48813> A_IWL<48812> A_IWL<48811> A_IWL<48810> A_IWL<48809> A_IWL<48808> A_IWL<48807> A_IWL<48806> A_IWL<48805> A_IWL<48804> A_IWL<48803> A_IWL<48802> A_IWL<48801> A_IWL<48800> A_IWL<48799> A_IWL<48798> A_IWL<48797> A_IWL<48796> A_IWL<48795> A_IWL<48794> A_IWL<48793> A_IWL<48792> A_IWL<48791> A_IWL<48790> A_IWL<48789> A_IWL<48788> A_IWL<48787> A_IWL<48786> A_IWL<48785> A_IWL<48784> A_IWL<48783> A_IWL<48782> A_IWL<48781> A_IWL<48780> A_IWL<48779> A_IWL<48778> A_IWL<48777> A_IWL<48776> A_IWL<48775> A_IWL<48774> A_IWL<48773> A_IWL<48772> A_IWL<48771> A_IWL<48770> A_IWL<48769> A_IWL<48768> A_IWL<48767> A_IWL<48766> A_IWL<48765> A_IWL<48764> A_IWL<48763> A_IWL<48762> A_IWL<48761> A_IWL<48760> A_IWL<48759> A_IWL<48758> A_IWL<48757> A_IWL<48756> A_IWL<48755> A_IWL<48754> A_IWL<48753> A_IWL<48752> A_IWL<48751> A_IWL<48750> A_IWL<48749> A_IWL<48748> A_IWL<48747> A_IWL<48746> A_IWL<48745> A_IWL<48744> A_IWL<48743> A_IWL<48742> A_IWL<48741> A_IWL<48740> A_IWL<48739> A_IWL<48738> A_IWL<48737> A_IWL<48736> A_IWL<48735> A_IWL<48734> A_IWL<48733> A_IWL<48732> A_IWL<48731> A_IWL<48730> A_IWL<48729> A_IWL<48728> A_IWL<48727> A_IWL<48726> A_IWL<48725> A_IWL<48724> A_IWL<48723> A_IWL<48722> A_IWL<48721> A_IWL<48720> A_IWL<48719> A_IWL<48718> A_IWL<48717> A_IWL<48716> A_IWL<48715> A_IWL<48714> A_IWL<48713> A_IWL<48712> A_IWL<48711> A_IWL<48710> A_IWL<48709> A_IWL<48708> A_IWL<48707> A_IWL<48706> A_IWL<48705> A_IWL<48704> A_IWL<48703> A_IWL<48702> A_IWL<48701> A_IWL<48700> A_IWL<48699> A_IWL<48698> A_IWL<48697> A_IWL<48696> A_IWL<48695> A_IWL<48694> A_IWL<48693> A_IWL<48692> A_IWL<48691> A_IWL<48690> A_IWL<48689> A_IWL<48688> A_IWL<48687> A_IWL<48686> A_IWL<48685> A_IWL<48684> A_IWL<48683> A_IWL<48682> A_IWL<48681> A_IWL<48680> A_IWL<48679> A_IWL<48678> A_IWL<48677> A_IWL<48676> A_IWL<48675> A_IWL<48674> A_IWL<48673> A_IWL<48672> A_IWL<48671> A_IWL<48670> A_IWL<48669> A_IWL<48668> A_IWL<48667> A_IWL<48666> A_IWL<48665> A_IWL<48664> A_IWL<48663> A_IWL<48662> A_IWL<48661> A_IWL<48660> A_IWL<48659> A_IWL<48658> A_IWL<48657> A_IWL<48656> A_IWL<48655> A_IWL<48654> A_IWL<48653> A_IWL<48652> A_IWL<48651> A_IWL<48650> A_IWL<48649> A_IWL<48648> A_IWL<48647> A_IWL<48646> A_IWL<48645> A_IWL<48644> A_IWL<48643> A_IWL<48642> A_IWL<48641> A_IWL<48640> VDD_CORE VSS / RM_IHPSG13_8192x32_c4_1P_COLUMN_pcell_0 +XCOL<94> A_BLC<189> A_BLC<188> A_BLC_TOP<189> A_BLC_TOP<188> A_BLT<189> A_BLT<188> A_BLT_TOP<189> A_BLT_TOP<188> A_IWL<48127> A_IWL<48126> A_IWL<48125> A_IWL<48124> A_IWL<48123> A_IWL<48122> A_IWL<48121> A_IWL<48120> A_IWL<48119> A_IWL<48118> A_IWL<48117> A_IWL<48116> A_IWL<48115> A_IWL<48114> A_IWL<48113> A_IWL<48112> A_IWL<48111> A_IWL<48110> A_IWL<48109> A_IWL<48108> A_IWL<48107> A_IWL<48106> A_IWL<48105> A_IWL<48104> A_IWL<48103> A_IWL<48102> A_IWL<48101> A_IWL<48100> A_IWL<48099> A_IWL<48098> A_IWL<48097> A_IWL<48096> A_IWL<48095> A_IWL<48094> A_IWL<48093> A_IWL<48092> A_IWL<48091> A_IWL<48090> A_IWL<48089> A_IWL<48088> A_IWL<48087> A_IWL<48086> A_IWL<48085> A_IWL<48084> A_IWL<48083> A_IWL<48082> A_IWL<48081> A_IWL<48080> A_IWL<48079> A_IWL<48078> A_IWL<48077> A_IWL<48076> A_IWL<48075> A_IWL<48074> A_IWL<48073> A_IWL<48072> A_IWL<48071> A_IWL<48070> A_IWL<48069> A_IWL<48068> A_IWL<48067> A_IWL<48066> A_IWL<48065> A_IWL<48064> A_IWL<48063> A_IWL<48062> A_IWL<48061> A_IWL<48060> A_IWL<48059> A_IWL<48058> A_IWL<48057> A_IWL<48056> A_IWL<48055> A_IWL<48054> A_IWL<48053> A_IWL<48052> A_IWL<48051> A_IWL<48050> A_IWL<48049> A_IWL<48048> A_IWL<48047> A_IWL<48046> A_IWL<48045> A_IWL<48044> A_IWL<48043> A_IWL<48042> A_IWL<48041> A_IWL<48040> A_IWL<48039> A_IWL<48038> A_IWL<48037> A_IWL<48036> A_IWL<48035> A_IWL<48034> A_IWL<48033> A_IWL<48032> A_IWL<48031> A_IWL<48030> A_IWL<48029> A_IWL<48028> A_IWL<48027> A_IWL<48026> A_IWL<48025> A_IWL<48024> A_IWL<48023> A_IWL<48022> A_IWL<48021> A_IWL<48020> A_IWL<48019> A_IWL<48018> A_IWL<48017> A_IWL<48016> A_IWL<48015> A_IWL<48014> A_IWL<48013> A_IWL<48012> A_IWL<48011> A_IWL<48010> A_IWL<48009> A_IWL<48008> A_IWL<48007> A_IWL<48006> A_IWL<48005> A_IWL<48004> A_IWL<48003> A_IWL<48002> A_IWL<48001> A_IWL<48000> A_IWL<47999> A_IWL<47998> A_IWL<47997> A_IWL<47996> A_IWL<47995> A_IWL<47994> A_IWL<47993> A_IWL<47992> A_IWL<47991> A_IWL<47990> A_IWL<47989> A_IWL<47988> A_IWL<47987> A_IWL<47986> A_IWL<47985> A_IWL<47984> A_IWL<47983> A_IWL<47982> A_IWL<47981> A_IWL<47980> A_IWL<47979> A_IWL<47978> A_IWL<47977> A_IWL<47976> A_IWL<47975> A_IWL<47974> A_IWL<47973> A_IWL<47972> A_IWL<47971> A_IWL<47970> A_IWL<47969> A_IWL<47968> A_IWL<47967> A_IWL<47966> A_IWL<47965> A_IWL<47964> A_IWL<47963> A_IWL<47962> A_IWL<47961> A_IWL<47960> A_IWL<47959> A_IWL<47958> A_IWL<47957> A_IWL<47956> A_IWL<47955> A_IWL<47954> A_IWL<47953> A_IWL<47952> A_IWL<47951> A_IWL<47950> A_IWL<47949> A_IWL<47948> A_IWL<47947> A_IWL<47946> A_IWL<47945> A_IWL<47944> A_IWL<47943> A_IWL<47942> A_IWL<47941> A_IWL<47940> A_IWL<47939> A_IWL<47938> A_IWL<47937> A_IWL<47936> A_IWL<47935> A_IWL<47934> A_IWL<47933> A_IWL<47932> A_IWL<47931> A_IWL<47930> A_IWL<47929> A_IWL<47928> A_IWL<47927> A_IWL<47926> A_IWL<47925> A_IWL<47924> A_IWL<47923> A_IWL<47922> A_IWL<47921> A_IWL<47920> A_IWL<47919> A_IWL<47918> A_IWL<47917> A_IWL<47916> A_IWL<47915> A_IWL<47914> A_IWL<47913> A_IWL<47912> A_IWL<47911> A_IWL<47910> A_IWL<47909> A_IWL<47908> A_IWL<47907> A_IWL<47906> A_IWL<47905> A_IWL<47904> A_IWL<47903> A_IWL<47902> A_IWL<47901> A_IWL<47900> A_IWL<47899> A_IWL<47898> A_IWL<47897> A_IWL<47896> A_IWL<47895> A_IWL<47894> A_IWL<47893> A_IWL<47892> A_IWL<47891> A_IWL<47890> A_IWL<47889> A_IWL<47888> A_IWL<47887> A_IWL<47886> A_IWL<47885> A_IWL<47884> A_IWL<47883> A_IWL<47882> A_IWL<47881> A_IWL<47880> A_IWL<47879> A_IWL<47878> A_IWL<47877> A_IWL<47876> A_IWL<47875> A_IWL<47874> A_IWL<47873> A_IWL<47872> A_IWL<47871> A_IWL<47870> A_IWL<47869> A_IWL<47868> A_IWL<47867> A_IWL<47866> A_IWL<47865> A_IWL<47864> A_IWL<47863> A_IWL<47862> A_IWL<47861> A_IWL<47860> A_IWL<47859> A_IWL<47858> A_IWL<47857> A_IWL<47856> A_IWL<47855> A_IWL<47854> A_IWL<47853> A_IWL<47852> A_IWL<47851> A_IWL<47850> A_IWL<47849> A_IWL<47848> A_IWL<47847> A_IWL<47846> A_IWL<47845> A_IWL<47844> A_IWL<47843> A_IWL<47842> A_IWL<47841> A_IWL<47840> A_IWL<47839> A_IWL<47838> A_IWL<47837> A_IWL<47836> A_IWL<47835> A_IWL<47834> A_IWL<47833> A_IWL<47832> A_IWL<47831> A_IWL<47830> A_IWL<47829> A_IWL<47828> A_IWL<47827> A_IWL<47826> A_IWL<47825> A_IWL<47824> A_IWL<47823> A_IWL<47822> A_IWL<47821> A_IWL<47820> A_IWL<47819> A_IWL<47818> A_IWL<47817> A_IWL<47816> A_IWL<47815> A_IWL<47814> A_IWL<47813> A_IWL<47812> A_IWL<47811> A_IWL<47810> A_IWL<47809> A_IWL<47808> A_IWL<47807> A_IWL<47806> A_IWL<47805> A_IWL<47804> A_IWL<47803> A_IWL<47802> A_IWL<47801> A_IWL<47800> A_IWL<47799> A_IWL<47798> A_IWL<47797> A_IWL<47796> A_IWL<47795> A_IWL<47794> A_IWL<47793> A_IWL<47792> A_IWL<47791> A_IWL<47790> A_IWL<47789> A_IWL<47788> A_IWL<47787> A_IWL<47786> A_IWL<47785> A_IWL<47784> A_IWL<47783> A_IWL<47782> A_IWL<47781> A_IWL<47780> A_IWL<47779> A_IWL<47778> A_IWL<47777> A_IWL<47776> A_IWL<47775> A_IWL<47774> A_IWL<47773> A_IWL<47772> A_IWL<47771> A_IWL<47770> A_IWL<47769> A_IWL<47768> A_IWL<47767> A_IWL<47766> A_IWL<47765> A_IWL<47764> A_IWL<47763> A_IWL<47762> A_IWL<47761> A_IWL<47760> A_IWL<47759> A_IWL<47758> A_IWL<47757> A_IWL<47756> A_IWL<47755> A_IWL<47754> A_IWL<47753> A_IWL<47752> A_IWL<47751> A_IWL<47750> A_IWL<47749> A_IWL<47748> A_IWL<47747> A_IWL<47746> A_IWL<47745> A_IWL<47744> A_IWL<47743> A_IWL<47742> A_IWL<47741> A_IWL<47740> A_IWL<47739> A_IWL<47738> A_IWL<47737> A_IWL<47736> A_IWL<47735> A_IWL<47734> A_IWL<47733> A_IWL<47732> A_IWL<47731> A_IWL<47730> A_IWL<47729> A_IWL<47728> A_IWL<47727> A_IWL<47726> A_IWL<47725> A_IWL<47724> A_IWL<47723> A_IWL<47722> A_IWL<47721> A_IWL<47720> A_IWL<47719> A_IWL<47718> A_IWL<47717> A_IWL<47716> A_IWL<47715> A_IWL<47714> A_IWL<47713> A_IWL<47712> A_IWL<47711> A_IWL<47710> A_IWL<47709> A_IWL<47708> A_IWL<47707> A_IWL<47706> A_IWL<47705> A_IWL<47704> A_IWL<47703> A_IWL<47702> A_IWL<47701> A_IWL<47700> A_IWL<47699> A_IWL<47698> A_IWL<47697> A_IWL<47696> A_IWL<47695> A_IWL<47694> A_IWL<47693> A_IWL<47692> A_IWL<47691> A_IWL<47690> A_IWL<47689> A_IWL<47688> A_IWL<47687> A_IWL<47686> A_IWL<47685> A_IWL<47684> A_IWL<47683> A_IWL<47682> A_IWL<47681> A_IWL<47680> A_IWL<47679> A_IWL<47678> A_IWL<47677> A_IWL<47676> A_IWL<47675> A_IWL<47674> A_IWL<47673> A_IWL<47672> A_IWL<47671> A_IWL<47670> A_IWL<47669> A_IWL<47668> A_IWL<47667> A_IWL<47666> A_IWL<47665> A_IWL<47664> A_IWL<47663> A_IWL<47662> A_IWL<47661> A_IWL<47660> A_IWL<47659> A_IWL<47658> A_IWL<47657> A_IWL<47656> A_IWL<47655> A_IWL<47654> A_IWL<47653> A_IWL<47652> A_IWL<47651> A_IWL<47650> A_IWL<47649> A_IWL<47648> A_IWL<47647> A_IWL<47646> A_IWL<47645> A_IWL<47644> A_IWL<47643> A_IWL<47642> A_IWL<47641> A_IWL<47640> A_IWL<47639> A_IWL<47638> A_IWL<47637> A_IWL<47636> A_IWL<47635> A_IWL<47634> A_IWL<47633> A_IWL<47632> A_IWL<47631> A_IWL<47630> A_IWL<47629> A_IWL<47628> A_IWL<47627> A_IWL<47626> A_IWL<47625> A_IWL<47624> A_IWL<47623> A_IWL<47622> A_IWL<47621> A_IWL<47620> A_IWL<47619> A_IWL<47618> A_IWL<47617> A_IWL<47616> A_IWL<48639> A_IWL<48638> A_IWL<48637> A_IWL<48636> A_IWL<48635> A_IWL<48634> A_IWL<48633> A_IWL<48632> A_IWL<48631> A_IWL<48630> A_IWL<48629> A_IWL<48628> A_IWL<48627> A_IWL<48626> A_IWL<48625> A_IWL<48624> A_IWL<48623> A_IWL<48622> A_IWL<48621> A_IWL<48620> A_IWL<48619> A_IWL<48618> A_IWL<48617> A_IWL<48616> A_IWL<48615> A_IWL<48614> A_IWL<48613> A_IWL<48612> A_IWL<48611> A_IWL<48610> A_IWL<48609> A_IWL<48608> A_IWL<48607> A_IWL<48606> A_IWL<48605> A_IWL<48604> A_IWL<48603> A_IWL<48602> A_IWL<48601> A_IWL<48600> A_IWL<48599> A_IWL<48598> A_IWL<48597> A_IWL<48596> A_IWL<48595> A_IWL<48594> A_IWL<48593> A_IWL<48592> A_IWL<48591> A_IWL<48590> A_IWL<48589> A_IWL<48588> A_IWL<48587> A_IWL<48586> A_IWL<48585> A_IWL<48584> A_IWL<48583> A_IWL<48582> A_IWL<48581> A_IWL<48580> A_IWL<48579> A_IWL<48578> A_IWL<48577> A_IWL<48576> A_IWL<48575> A_IWL<48574> A_IWL<48573> A_IWL<48572> A_IWL<48571> A_IWL<48570> A_IWL<48569> A_IWL<48568> A_IWL<48567> A_IWL<48566> A_IWL<48565> A_IWL<48564> A_IWL<48563> A_IWL<48562> A_IWL<48561> A_IWL<48560> A_IWL<48559> A_IWL<48558> A_IWL<48557> A_IWL<48556> A_IWL<48555> A_IWL<48554> A_IWL<48553> A_IWL<48552> A_IWL<48551> A_IWL<48550> A_IWL<48549> A_IWL<48548> A_IWL<48547> A_IWL<48546> A_IWL<48545> A_IWL<48544> A_IWL<48543> A_IWL<48542> A_IWL<48541> A_IWL<48540> A_IWL<48539> A_IWL<48538> A_IWL<48537> A_IWL<48536> A_IWL<48535> A_IWL<48534> A_IWL<48533> A_IWL<48532> A_IWL<48531> A_IWL<48530> A_IWL<48529> A_IWL<48528> A_IWL<48527> A_IWL<48526> A_IWL<48525> A_IWL<48524> A_IWL<48523> A_IWL<48522> A_IWL<48521> A_IWL<48520> A_IWL<48519> A_IWL<48518> A_IWL<48517> A_IWL<48516> A_IWL<48515> A_IWL<48514> A_IWL<48513> A_IWL<48512> A_IWL<48511> A_IWL<48510> A_IWL<48509> A_IWL<48508> A_IWL<48507> A_IWL<48506> A_IWL<48505> A_IWL<48504> A_IWL<48503> A_IWL<48502> A_IWL<48501> A_IWL<48500> A_IWL<48499> A_IWL<48498> A_IWL<48497> A_IWL<48496> A_IWL<48495> A_IWL<48494> A_IWL<48493> A_IWL<48492> A_IWL<48491> A_IWL<48490> A_IWL<48489> A_IWL<48488> A_IWL<48487> A_IWL<48486> A_IWL<48485> A_IWL<48484> A_IWL<48483> A_IWL<48482> A_IWL<48481> A_IWL<48480> A_IWL<48479> A_IWL<48478> A_IWL<48477> A_IWL<48476> A_IWL<48475> A_IWL<48474> A_IWL<48473> A_IWL<48472> A_IWL<48471> A_IWL<48470> A_IWL<48469> A_IWL<48468> A_IWL<48467> A_IWL<48466> A_IWL<48465> A_IWL<48464> A_IWL<48463> A_IWL<48462> A_IWL<48461> A_IWL<48460> A_IWL<48459> A_IWL<48458> A_IWL<48457> A_IWL<48456> A_IWL<48455> A_IWL<48454> A_IWL<48453> A_IWL<48452> A_IWL<48451> A_IWL<48450> A_IWL<48449> A_IWL<48448> A_IWL<48447> A_IWL<48446> A_IWL<48445> A_IWL<48444> A_IWL<48443> A_IWL<48442> A_IWL<48441> A_IWL<48440> A_IWL<48439> A_IWL<48438> A_IWL<48437> A_IWL<48436> A_IWL<48435> A_IWL<48434> A_IWL<48433> A_IWL<48432> A_IWL<48431> A_IWL<48430> A_IWL<48429> A_IWL<48428> A_IWL<48427> A_IWL<48426> A_IWL<48425> A_IWL<48424> A_IWL<48423> A_IWL<48422> A_IWL<48421> A_IWL<48420> A_IWL<48419> A_IWL<48418> A_IWL<48417> A_IWL<48416> A_IWL<48415> A_IWL<48414> A_IWL<48413> A_IWL<48412> A_IWL<48411> A_IWL<48410> A_IWL<48409> A_IWL<48408> A_IWL<48407> A_IWL<48406> A_IWL<48405> A_IWL<48404> A_IWL<48403> A_IWL<48402> A_IWL<48401> A_IWL<48400> A_IWL<48399> A_IWL<48398> A_IWL<48397> A_IWL<48396> A_IWL<48395> A_IWL<48394> A_IWL<48393> A_IWL<48392> A_IWL<48391> A_IWL<48390> A_IWL<48389> A_IWL<48388> A_IWL<48387> A_IWL<48386> A_IWL<48385> A_IWL<48384> A_IWL<48383> A_IWL<48382> A_IWL<48381> A_IWL<48380> A_IWL<48379> A_IWL<48378> A_IWL<48377> A_IWL<48376> A_IWL<48375> A_IWL<48374> A_IWL<48373> A_IWL<48372> A_IWL<48371> A_IWL<48370> A_IWL<48369> A_IWL<48368> A_IWL<48367> A_IWL<48366> A_IWL<48365> A_IWL<48364> A_IWL<48363> A_IWL<48362> A_IWL<48361> A_IWL<48360> A_IWL<48359> A_IWL<48358> A_IWL<48357> A_IWL<48356> A_IWL<48355> A_IWL<48354> A_IWL<48353> A_IWL<48352> A_IWL<48351> A_IWL<48350> A_IWL<48349> A_IWL<48348> A_IWL<48347> A_IWL<48346> A_IWL<48345> A_IWL<48344> A_IWL<48343> A_IWL<48342> A_IWL<48341> A_IWL<48340> A_IWL<48339> A_IWL<48338> A_IWL<48337> A_IWL<48336> A_IWL<48335> A_IWL<48334> A_IWL<48333> A_IWL<48332> A_IWL<48331> A_IWL<48330> A_IWL<48329> A_IWL<48328> A_IWL<48327> A_IWL<48326> A_IWL<48325> A_IWL<48324> A_IWL<48323> A_IWL<48322> A_IWL<48321> A_IWL<48320> A_IWL<48319> A_IWL<48318> A_IWL<48317> A_IWL<48316> A_IWL<48315> A_IWL<48314> A_IWL<48313> A_IWL<48312> A_IWL<48311> A_IWL<48310> A_IWL<48309> A_IWL<48308> A_IWL<48307> A_IWL<48306> A_IWL<48305> A_IWL<48304> A_IWL<48303> A_IWL<48302> A_IWL<48301> A_IWL<48300> A_IWL<48299> A_IWL<48298> A_IWL<48297> A_IWL<48296> A_IWL<48295> A_IWL<48294> A_IWL<48293> A_IWL<48292> A_IWL<48291> A_IWL<48290> A_IWL<48289> A_IWL<48288> A_IWL<48287> A_IWL<48286> A_IWL<48285> A_IWL<48284> A_IWL<48283> A_IWL<48282> A_IWL<48281> A_IWL<48280> A_IWL<48279> A_IWL<48278> A_IWL<48277> A_IWL<48276> A_IWL<48275> A_IWL<48274> A_IWL<48273> A_IWL<48272> A_IWL<48271> A_IWL<48270> A_IWL<48269> A_IWL<48268> A_IWL<48267> A_IWL<48266> A_IWL<48265> A_IWL<48264> A_IWL<48263> A_IWL<48262> A_IWL<48261> A_IWL<48260> A_IWL<48259> A_IWL<48258> A_IWL<48257> A_IWL<48256> A_IWL<48255> A_IWL<48254> A_IWL<48253> A_IWL<48252> A_IWL<48251> A_IWL<48250> A_IWL<48249> A_IWL<48248> A_IWL<48247> A_IWL<48246> A_IWL<48245> A_IWL<48244> A_IWL<48243> A_IWL<48242> A_IWL<48241> A_IWL<48240> A_IWL<48239> A_IWL<48238> A_IWL<48237> A_IWL<48236> A_IWL<48235> A_IWL<48234> A_IWL<48233> A_IWL<48232> A_IWL<48231> A_IWL<48230> A_IWL<48229> A_IWL<48228> A_IWL<48227> A_IWL<48226> A_IWL<48225> A_IWL<48224> A_IWL<48223> A_IWL<48222> A_IWL<48221> A_IWL<48220> A_IWL<48219> A_IWL<48218> A_IWL<48217> A_IWL<48216> A_IWL<48215> A_IWL<48214> A_IWL<48213> A_IWL<48212> A_IWL<48211> A_IWL<48210> A_IWL<48209> A_IWL<48208> A_IWL<48207> A_IWL<48206> A_IWL<48205> A_IWL<48204> A_IWL<48203> A_IWL<48202> A_IWL<48201> A_IWL<48200> A_IWL<48199> A_IWL<48198> A_IWL<48197> A_IWL<48196> A_IWL<48195> A_IWL<48194> A_IWL<48193> A_IWL<48192> A_IWL<48191> A_IWL<48190> A_IWL<48189> A_IWL<48188> A_IWL<48187> A_IWL<48186> A_IWL<48185> A_IWL<48184> A_IWL<48183> A_IWL<48182> A_IWL<48181> A_IWL<48180> A_IWL<48179> A_IWL<48178> A_IWL<48177> A_IWL<48176> A_IWL<48175> A_IWL<48174> A_IWL<48173> A_IWL<48172> A_IWL<48171> A_IWL<48170> A_IWL<48169> A_IWL<48168> A_IWL<48167> A_IWL<48166> A_IWL<48165> A_IWL<48164> A_IWL<48163> A_IWL<48162> A_IWL<48161> A_IWL<48160> A_IWL<48159> A_IWL<48158> A_IWL<48157> A_IWL<48156> A_IWL<48155> A_IWL<48154> A_IWL<48153> A_IWL<48152> A_IWL<48151> A_IWL<48150> A_IWL<48149> A_IWL<48148> A_IWL<48147> A_IWL<48146> A_IWL<48145> A_IWL<48144> A_IWL<48143> A_IWL<48142> A_IWL<48141> A_IWL<48140> A_IWL<48139> A_IWL<48138> A_IWL<48137> A_IWL<48136> A_IWL<48135> A_IWL<48134> A_IWL<48133> A_IWL<48132> A_IWL<48131> A_IWL<48130> A_IWL<48129> A_IWL<48128> VDD_CORE VSS / RM_IHPSG13_8192x32_c4_1P_COLUMN_pcell_0 +XCOL<93> A_BLC<187> A_BLC<186> A_BLC_TOP<187> A_BLC_TOP<186> A_BLT<187> A_BLT<186> A_BLT_TOP<187> A_BLT_TOP<186> A_IWL<47615> A_IWL<47614> A_IWL<47613> A_IWL<47612> A_IWL<47611> A_IWL<47610> A_IWL<47609> A_IWL<47608> A_IWL<47607> A_IWL<47606> A_IWL<47605> A_IWL<47604> A_IWL<47603> A_IWL<47602> A_IWL<47601> A_IWL<47600> A_IWL<47599> A_IWL<47598> A_IWL<47597> A_IWL<47596> A_IWL<47595> A_IWL<47594> A_IWL<47593> A_IWL<47592> A_IWL<47591> A_IWL<47590> A_IWL<47589> A_IWL<47588> A_IWL<47587> A_IWL<47586> A_IWL<47585> A_IWL<47584> A_IWL<47583> A_IWL<47582> A_IWL<47581> A_IWL<47580> A_IWL<47579> A_IWL<47578> A_IWL<47577> A_IWL<47576> A_IWL<47575> A_IWL<47574> A_IWL<47573> A_IWL<47572> A_IWL<47571> A_IWL<47570> A_IWL<47569> A_IWL<47568> A_IWL<47567> A_IWL<47566> A_IWL<47565> A_IWL<47564> A_IWL<47563> A_IWL<47562> A_IWL<47561> A_IWL<47560> A_IWL<47559> A_IWL<47558> A_IWL<47557> A_IWL<47556> A_IWL<47555> A_IWL<47554> A_IWL<47553> A_IWL<47552> A_IWL<47551> A_IWL<47550> A_IWL<47549> A_IWL<47548> A_IWL<47547> A_IWL<47546> A_IWL<47545> A_IWL<47544> A_IWL<47543> A_IWL<47542> A_IWL<47541> A_IWL<47540> A_IWL<47539> A_IWL<47538> A_IWL<47537> A_IWL<47536> A_IWL<47535> A_IWL<47534> A_IWL<47533> A_IWL<47532> A_IWL<47531> A_IWL<47530> A_IWL<47529> A_IWL<47528> A_IWL<47527> A_IWL<47526> A_IWL<47525> A_IWL<47524> A_IWL<47523> A_IWL<47522> A_IWL<47521> A_IWL<47520> A_IWL<47519> A_IWL<47518> A_IWL<47517> A_IWL<47516> A_IWL<47515> A_IWL<47514> A_IWL<47513> A_IWL<47512> A_IWL<47511> A_IWL<47510> A_IWL<47509> A_IWL<47508> A_IWL<47507> A_IWL<47506> A_IWL<47505> A_IWL<47504> A_IWL<47503> A_IWL<47502> A_IWL<47501> A_IWL<47500> A_IWL<47499> A_IWL<47498> A_IWL<47497> A_IWL<47496> A_IWL<47495> A_IWL<47494> A_IWL<47493> A_IWL<47492> A_IWL<47491> A_IWL<47490> A_IWL<47489> A_IWL<47488> A_IWL<47487> A_IWL<47486> A_IWL<47485> A_IWL<47484> A_IWL<47483> A_IWL<47482> A_IWL<47481> A_IWL<47480> A_IWL<47479> A_IWL<47478> A_IWL<47477> A_IWL<47476> A_IWL<47475> A_IWL<47474> A_IWL<47473> A_IWL<47472> A_IWL<47471> A_IWL<47470> A_IWL<47469> A_IWL<47468> A_IWL<47467> A_IWL<47466> A_IWL<47465> A_IWL<47464> A_IWL<47463> A_IWL<47462> A_IWL<47461> A_IWL<47460> A_IWL<47459> A_IWL<47458> A_IWL<47457> A_IWL<47456> A_IWL<47455> A_IWL<47454> A_IWL<47453> A_IWL<47452> A_IWL<47451> A_IWL<47450> A_IWL<47449> A_IWL<47448> A_IWL<47447> A_IWL<47446> A_IWL<47445> A_IWL<47444> A_IWL<47443> A_IWL<47442> A_IWL<47441> A_IWL<47440> A_IWL<47439> A_IWL<47438> A_IWL<47437> A_IWL<47436> A_IWL<47435> A_IWL<47434> A_IWL<47433> A_IWL<47432> A_IWL<47431> A_IWL<47430> A_IWL<47429> A_IWL<47428> A_IWL<47427> A_IWL<47426> A_IWL<47425> A_IWL<47424> A_IWL<47423> A_IWL<47422> A_IWL<47421> A_IWL<47420> A_IWL<47419> A_IWL<47418> A_IWL<47417> A_IWL<47416> A_IWL<47415> A_IWL<47414> A_IWL<47413> A_IWL<47412> A_IWL<47411> A_IWL<47410> A_IWL<47409> A_IWL<47408> A_IWL<47407> A_IWL<47406> A_IWL<47405> A_IWL<47404> A_IWL<47403> A_IWL<47402> A_IWL<47401> A_IWL<47400> A_IWL<47399> A_IWL<47398> A_IWL<47397> A_IWL<47396> A_IWL<47395> A_IWL<47394> A_IWL<47393> A_IWL<47392> A_IWL<47391> A_IWL<47390> A_IWL<47389> A_IWL<47388> A_IWL<47387> A_IWL<47386> A_IWL<47385> A_IWL<47384> A_IWL<47383> A_IWL<47382> A_IWL<47381> A_IWL<47380> A_IWL<47379> A_IWL<47378> A_IWL<47377> A_IWL<47376> A_IWL<47375> A_IWL<47374> A_IWL<47373> A_IWL<47372> A_IWL<47371> A_IWL<47370> A_IWL<47369> A_IWL<47368> A_IWL<47367> A_IWL<47366> A_IWL<47365> A_IWL<47364> A_IWL<47363> A_IWL<47362> A_IWL<47361> A_IWL<47360> A_IWL<47359> A_IWL<47358> A_IWL<47357> A_IWL<47356> A_IWL<47355> A_IWL<47354> A_IWL<47353> A_IWL<47352> A_IWL<47351> A_IWL<47350> A_IWL<47349> A_IWL<47348> A_IWL<47347> A_IWL<47346> A_IWL<47345> A_IWL<47344> A_IWL<47343> A_IWL<47342> A_IWL<47341> A_IWL<47340> A_IWL<47339> A_IWL<47338> A_IWL<47337> A_IWL<47336> A_IWL<47335> A_IWL<47334> A_IWL<47333> A_IWL<47332> A_IWL<47331> A_IWL<47330> A_IWL<47329> A_IWL<47328> A_IWL<47327> A_IWL<47326> A_IWL<47325> A_IWL<47324> A_IWL<47323> A_IWL<47322> A_IWL<47321> A_IWL<47320> A_IWL<47319> A_IWL<47318> A_IWL<47317> A_IWL<47316> A_IWL<47315> A_IWL<47314> A_IWL<47313> A_IWL<47312> A_IWL<47311> A_IWL<47310> A_IWL<47309> A_IWL<47308> A_IWL<47307> A_IWL<47306> A_IWL<47305> A_IWL<47304> A_IWL<47303> A_IWL<47302> A_IWL<47301> A_IWL<47300> A_IWL<47299> A_IWL<47298> A_IWL<47297> A_IWL<47296> A_IWL<47295> A_IWL<47294> A_IWL<47293> A_IWL<47292> A_IWL<47291> A_IWL<47290> A_IWL<47289> A_IWL<47288> A_IWL<47287> A_IWL<47286> A_IWL<47285> A_IWL<47284> A_IWL<47283> A_IWL<47282> A_IWL<47281> A_IWL<47280> A_IWL<47279> A_IWL<47278> A_IWL<47277> A_IWL<47276> A_IWL<47275> A_IWL<47274> A_IWL<47273> A_IWL<47272> A_IWL<47271> A_IWL<47270> A_IWL<47269> A_IWL<47268> A_IWL<47267> A_IWL<47266> A_IWL<47265> A_IWL<47264> A_IWL<47263> A_IWL<47262> A_IWL<47261> A_IWL<47260> A_IWL<47259> A_IWL<47258> A_IWL<47257> A_IWL<47256> A_IWL<47255> A_IWL<47254> A_IWL<47253> A_IWL<47252> A_IWL<47251> A_IWL<47250> A_IWL<47249> A_IWL<47248> A_IWL<47247> A_IWL<47246> A_IWL<47245> A_IWL<47244> A_IWL<47243> A_IWL<47242> A_IWL<47241> A_IWL<47240> A_IWL<47239> A_IWL<47238> A_IWL<47237> A_IWL<47236> A_IWL<47235> A_IWL<47234> A_IWL<47233> A_IWL<47232> A_IWL<47231> A_IWL<47230> A_IWL<47229> A_IWL<47228> A_IWL<47227> A_IWL<47226> A_IWL<47225> A_IWL<47224> A_IWL<47223> A_IWL<47222> A_IWL<47221> A_IWL<47220> A_IWL<47219> A_IWL<47218> A_IWL<47217> A_IWL<47216> A_IWL<47215> A_IWL<47214> A_IWL<47213> A_IWL<47212> A_IWL<47211> A_IWL<47210> A_IWL<47209> A_IWL<47208> A_IWL<47207> A_IWL<47206> A_IWL<47205> A_IWL<47204> A_IWL<47203> A_IWL<47202> A_IWL<47201> A_IWL<47200> A_IWL<47199> A_IWL<47198> A_IWL<47197> A_IWL<47196> A_IWL<47195> A_IWL<47194> A_IWL<47193> A_IWL<47192> A_IWL<47191> A_IWL<47190> A_IWL<47189> A_IWL<47188> A_IWL<47187> A_IWL<47186> A_IWL<47185> A_IWL<47184> A_IWL<47183> A_IWL<47182> A_IWL<47181> A_IWL<47180> A_IWL<47179> A_IWL<47178> A_IWL<47177> A_IWL<47176> A_IWL<47175> A_IWL<47174> A_IWL<47173> A_IWL<47172> A_IWL<47171> A_IWL<47170> A_IWL<47169> A_IWL<47168> A_IWL<47167> A_IWL<47166> A_IWL<47165> A_IWL<47164> A_IWL<47163> A_IWL<47162> A_IWL<47161> A_IWL<47160> A_IWL<47159> A_IWL<47158> A_IWL<47157> A_IWL<47156> A_IWL<47155> A_IWL<47154> A_IWL<47153> A_IWL<47152> A_IWL<47151> A_IWL<47150> A_IWL<47149> A_IWL<47148> A_IWL<47147> A_IWL<47146> A_IWL<47145> A_IWL<47144> A_IWL<47143> A_IWL<47142> A_IWL<47141> A_IWL<47140> A_IWL<47139> A_IWL<47138> A_IWL<47137> A_IWL<47136> A_IWL<47135> A_IWL<47134> A_IWL<47133> A_IWL<47132> A_IWL<47131> A_IWL<47130> A_IWL<47129> A_IWL<47128> A_IWL<47127> A_IWL<47126> A_IWL<47125> A_IWL<47124> A_IWL<47123> A_IWL<47122> A_IWL<47121> A_IWL<47120> A_IWL<47119> A_IWL<47118> A_IWL<47117> A_IWL<47116> A_IWL<47115> A_IWL<47114> A_IWL<47113> A_IWL<47112> A_IWL<47111> A_IWL<47110> A_IWL<47109> A_IWL<47108> A_IWL<47107> A_IWL<47106> A_IWL<47105> A_IWL<47104> A_IWL<48127> A_IWL<48126> A_IWL<48125> A_IWL<48124> A_IWL<48123> A_IWL<48122> A_IWL<48121> A_IWL<48120> A_IWL<48119> A_IWL<48118> A_IWL<48117> A_IWL<48116> A_IWL<48115> A_IWL<48114> A_IWL<48113> A_IWL<48112> A_IWL<48111> A_IWL<48110> A_IWL<48109> A_IWL<48108> A_IWL<48107> A_IWL<48106> A_IWL<48105> A_IWL<48104> A_IWL<48103> A_IWL<48102> A_IWL<48101> A_IWL<48100> A_IWL<48099> A_IWL<48098> A_IWL<48097> A_IWL<48096> A_IWL<48095> A_IWL<48094> A_IWL<48093> A_IWL<48092> A_IWL<48091> A_IWL<48090> A_IWL<48089> A_IWL<48088> A_IWL<48087> A_IWL<48086> A_IWL<48085> A_IWL<48084> A_IWL<48083> A_IWL<48082> A_IWL<48081> A_IWL<48080> A_IWL<48079> A_IWL<48078> A_IWL<48077> A_IWL<48076> A_IWL<48075> A_IWL<48074> A_IWL<48073> A_IWL<48072> A_IWL<48071> A_IWL<48070> A_IWL<48069> A_IWL<48068> A_IWL<48067> A_IWL<48066> A_IWL<48065> A_IWL<48064> A_IWL<48063> A_IWL<48062> A_IWL<48061> A_IWL<48060> A_IWL<48059> A_IWL<48058> A_IWL<48057> A_IWL<48056> A_IWL<48055> A_IWL<48054> A_IWL<48053> A_IWL<48052> A_IWL<48051> A_IWL<48050> A_IWL<48049> A_IWL<48048> A_IWL<48047> A_IWL<48046> A_IWL<48045> A_IWL<48044> A_IWL<48043> A_IWL<48042> A_IWL<48041> A_IWL<48040> A_IWL<48039> A_IWL<48038> A_IWL<48037> A_IWL<48036> A_IWL<48035> A_IWL<48034> A_IWL<48033> A_IWL<48032> A_IWL<48031> A_IWL<48030> A_IWL<48029> A_IWL<48028> A_IWL<48027> A_IWL<48026> A_IWL<48025> A_IWL<48024> A_IWL<48023> A_IWL<48022> A_IWL<48021> A_IWL<48020> A_IWL<48019> A_IWL<48018> A_IWL<48017> A_IWL<48016> A_IWL<48015> A_IWL<48014> A_IWL<48013> A_IWL<48012> A_IWL<48011> A_IWL<48010> A_IWL<48009> A_IWL<48008> A_IWL<48007> A_IWL<48006> A_IWL<48005> A_IWL<48004> A_IWL<48003> A_IWL<48002> A_IWL<48001> A_IWL<48000> A_IWL<47999> A_IWL<47998> A_IWL<47997> A_IWL<47996> A_IWL<47995> A_IWL<47994> A_IWL<47993> A_IWL<47992> A_IWL<47991> A_IWL<47990> A_IWL<47989> A_IWL<47988> A_IWL<47987> A_IWL<47986> A_IWL<47985> A_IWL<47984> A_IWL<47983> A_IWL<47982> A_IWL<47981> A_IWL<47980> A_IWL<47979> A_IWL<47978> A_IWL<47977> A_IWL<47976> A_IWL<47975> A_IWL<47974> A_IWL<47973> A_IWL<47972> A_IWL<47971> A_IWL<47970> A_IWL<47969> A_IWL<47968> A_IWL<47967> A_IWL<47966> A_IWL<47965> A_IWL<47964> A_IWL<47963> A_IWL<47962> A_IWL<47961> A_IWL<47960> A_IWL<47959> A_IWL<47958> A_IWL<47957> A_IWL<47956> A_IWL<47955> A_IWL<47954> A_IWL<47953> A_IWL<47952> A_IWL<47951> A_IWL<47950> A_IWL<47949> A_IWL<47948> A_IWL<47947> A_IWL<47946> A_IWL<47945> A_IWL<47944> A_IWL<47943> A_IWL<47942> A_IWL<47941> A_IWL<47940> A_IWL<47939> A_IWL<47938> A_IWL<47937> A_IWL<47936> A_IWL<47935> A_IWL<47934> A_IWL<47933> A_IWL<47932> A_IWL<47931> A_IWL<47930> A_IWL<47929> A_IWL<47928> A_IWL<47927> A_IWL<47926> A_IWL<47925> A_IWL<47924> A_IWL<47923> A_IWL<47922> A_IWL<47921> A_IWL<47920> A_IWL<47919> A_IWL<47918> A_IWL<47917> A_IWL<47916> A_IWL<47915> A_IWL<47914> A_IWL<47913> A_IWL<47912> A_IWL<47911> A_IWL<47910> A_IWL<47909> A_IWL<47908> A_IWL<47907> A_IWL<47906> A_IWL<47905> A_IWL<47904> A_IWL<47903> A_IWL<47902> A_IWL<47901> A_IWL<47900> A_IWL<47899> A_IWL<47898> A_IWL<47897> A_IWL<47896> A_IWL<47895> A_IWL<47894> A_IWL<47893> A_IWL<47892> A_IWL<47891> A_IWL<47890> A_IWL<47889> A_IWL<47888> A_IWL<47887> A_IWL<47886> A_IWL<47885> A_IWL<47884> A_IWL<47883> A_IWL<47882> A_IWL<47881> A_IWL<47880> A_IWL<47879> A_IWL<47878> A_IWL<47877> A_IWL<47876> A_IWL<47875> A_IWL<47874> A_IWL<47873> A_IWL<47872> A_IWL<47871> A_IWL<47870> A_IWL<47869> A_IWL<47868> A_IWL<47867> A_IWL<47866> A_IWL<47865> A_IWL<47864> A_IWL<47863> A_IWL<47862> A_IWL<47861> A_IWL<47860> A_IWL<47859> A_IWL<47858> A_IWL<47857> A_IWL<47856> A_IWL<47855> A_IWL<47854> A_IWL<47853> A_IWL<47852> A_IWL<47851> A_IWL<47850> A_IWL<47849> A_IWL<47848> A_IWL<47847> A_IWL<47846> A_IWL<47845> A_IWL<47844> A_IWL<47843> A_IWL<47842> A_IWL<47841> A_IWL<47840> A_IWL<47839> A_IWL<47838> A_IWL<47837> A_IWL<47836> A_IWL<47835> A_IWL<47834> A_IWL<47833> A_IWL<47832> A_IWL<47831> A_IWL<47830> A_IWL<47829> A_IWL<47828> A_IWL<47827> A_IWL<47826> A_IWL<47825> A_IWL<47824> A_IWL<47823> A_IWL<47822> A_IWL<47821> A_IWL<47820> A_IWL<47819> A_IWL<47818> A_IWL<47817> A_IWL<47816> A_IWL<47815> A_IWL<47814> A_IWL<47813> A_IWL<47812> A_IWL<47811> A_IWL<47810> A_IWL<47809> A_IWL<47808> A_IWL<47807> A_IWL<47806> A_IWL<47805> A_IWL<47804> A_IWL<47803> A_IWL<47802> A_IWL<47801> A_IWL<47800> A_IWL<47799> A_IWL<47798> A_IWL<47797> A_IWL<47796> A_IWL<47795> A_IWL<47794> A_IWL<47793> A_IWL<47792> A_IWL<47791> A_IWL<47790> A_IWL<47789> A_IWL<47788> A_IWL<47787> A_IWL<47786> A_IWL<47785> A_IWL<47784> A_IWL<47783> A_IWL<47782> A_IWL<47781> A_IWL<47780> A_IWL<47779> A_IWL<47778> A_IWL<47777> A_IWL<47776> A_IWL<47775> A_IWL<47774> A_IWL<47773> A_IWL<47772> A_IWL<47771> A_IWL<47770> A_IWL<47769> A_IWL<47768> A_IWL<47767> A_IWL<47766> A_IWL<47765> A_IWL<47764> A_IWL<47763> A_IWL<47762> A_IWL<47761> A_IWL<47760> A_IWL<47759> A_IWL<47758> A_IWL<47757> A_IWL<47756> A_IWL<47755> A_IWL<47754> A_IWL<47753> A_IWL<47752> A_IWL<47751> A_IWL<47750> A_IWL<47749> A_IWL<47748> A_IWL<47747> A_IWL<47746> A_IWL<47745> A_IWL<47744> A_IWL<47743> A_IWL<47742> A_IWL<47741> A_IWL<47740> A_IWL<47739> A_IWL<47738> A_IWL<47737> A_IWL<47736> A_IWL<47735> A_IWL<47734> A_IWL<47733> A_IWL<47732> A_IWL<47731> A_IWL<47730> A_IWL<47729> A_IWL<47728> A_IWL<47727> A_IWL<47726> A_IWL<47725> A_IWL<47724> A_IWL<47723> A_IWL<47722> A_IWL<47721> A_IWL<47720> A_IWL<47719> A_IWL<47718> A_IWL<47717> A_IWL<47716> A_IWL<47715> A_IWL<47714> A_IWL<47713> A_IWL<47712> A_IWL<47711> A_IWL<47710> A_IWL<47709> A_IWL<47708> A_IWL<47707> A_IWL<47706> A_IWL<47705> A_IWL<47704> A_IWL<47703> A_IWL<47702> A_IWL<47701> A_IWL<47700> A_IWL<47699> A_IWL<47698> A_IWL<47697> A_IWL<47696> A_IWL<47695> A_IWL<47694> A_IWL<47693> A_IWL<47692> A_IWL<47691> A_IWL<47690> A_IWL<47689> A_IWL<47688> A_IWL<47687> A_IWL<47686> A_IWL<47685> A_IWL<47684> A_IWL<47683> A_IWL<47682> A_IWL<47681> A_IWL<47680> A_IWL<47679> A_IWL<47678> A_IWL<47677> A_IWL<47676> A_IWL<47675> A_IWL<47674> A_IWL<47673> A_IWL<47672> A_IWL<47671> A_IWL<47670> A_IWL<47669> A_IWL<47668> A_IWL<47667> A_IWL<47666> A_IWL<47665> A_IWL<47664> A_IWL<47663> A_IWL<47662> A_IWL<47661> A_IWL<47660> A_IWL<47659> A_IWL<47658> A_IWL<47657> A_IWL<47656> A_IWL<47655> A_IWL<47654> A_IWL<47653> A_IWL<47652> A_IWL<47651> A_IWL<47650> A_IWL<47649> A_IWL<47648> A_IWL<47647> A_IWL<47646> A_IWL<47645> A_IWL<47644> A_IWL<47643> A_IWL<47642> A_IWL<47641> A_IWL<47640> A_IWL<47639> A_IWL<47638> A_IWL<47637> A_IWL<47636> A_IWL<47635> A_IWL<47634> A_IWL<47633> A_IWL<47632> A_IWL<47631> A_IWL<47630> A_IWL<47629> A_IWL<47628> A_IWL<47627> A_IWL<47626> A_IWL<47625> A_IWL<47624> A_IWL<47623> A_IWL<47622> A_IWL<47621> A_IWL<47620> A_IWL<47619> A_IWL<47618> A_IWL<47617> A_IWL<47616> VDD_CORE VSS / RM_IHPSG13_8192x32_c4_1P_COLUMN_pcell_0 +XCOL<92> A_BLC<185> A_BLC<184> A_BLC_TOP<185> A_BLC_TOP<184> A_BLT<185> A_BLT<184> A_BLT_TOP<185> A_BLT_TOP<184> A_IWL<47103> A_IWL<47102> A_IWL<47101> A_IWL<47100> A_IWL<47099> A_IWL<47098> A_IWL<47097> A_IWL<47096> A_IWL<47095> A_IWL<47094> A_IWL<47093> A_IWL<47092> A_IWL<47091> A_IWL<47090> A_IWL<47089> A_IWL<47088> A_IWL<47087> A_IWL<47086> A_IWL<47085> A_IWL<47084> A_IWL<47083> A_IWL<47082> A_IWL<47081> A_IWL<47080> A_IWL<47079> A_IWL<47078> A_IWL<47077> A_IWL<47076> A_IWL<47075> A_IWL<47074> A_IWL<47073> A_IWL<47072> A_IWL<47071> A_IWL<47070> A_IWL<47069> A_IWL<47068> A_IWL<47067> A_IWL<47066> A_IWL<47065> A_IWL<47064> A_IWL<47063> A_IWL<47062> A_IWL<47061> A_IWL<47060> A_IWL<47059> A_IWL<47058> A_IWL<47057> A_IWL<47056> A_IWL<47055> A_IWL<47054> A_IWL<47053> A_IWL<47052> A_IWL<47051> A_IWL<47050> A_IWL<47049> A_IWL<47048> A_IWL<47047> A_IWL<47046> A_IWL<47045> A_IWL<47044> A_IWL<47043> A_IWL<47042> A_IWL<47041> A_IWL<47040> A_IWL<47039> A_IWL<47038> A_IWL<47037> A_IWL<47036> A_IWL<47035> A_IWL<47034> A_IWL<47033> A_IWL<47032> A_IWL<47031> A_IWL<47030> A_IWL<47029> A_IWL<47028> A_IWL<47027> A_IWL<47026> A_IWL<47025> A_IWL<47024> A_IWL<47023> A_IWL<47022> A_IWL<47021> A_IWL<47020> A_IWL<47019> A_IWL<47018> A_IWL<47017> A_IWL<47016> A_IWL<47015> A_IWL<47014> A_IWL<47013> A_IWL<47012> A_IWL<47011> A_IWL<47010> A_IWL<47009> A_IWL<47008> A_IWL<47007> A_IWL<47006> A_IWL<47005> A_IWL<47004> A_IWL<47003> A_IWL<47002> A_IWL<47001> A_IWL<47000> A_IWL<46999> A_IWL<46998> A_IWL<46997> A_IWL<46996> A_IWL<46995> A_IWL<46994> A_IWL<46993> A_IWL<46992> A_IWL<46991> A_IWL<46990> A_IWL<46989> A_IWL<46988> A_IWL<46987> A_IWL<46986> A_IWL<46985> A_IWL<46984> A_IWL<46983> A_IWL<46982> A_IWL<46981> A_IWL<46980> A_IWL<46979> A_IWL<46978> A_IWL<46977> A_IWL<46976> A_IWL<46975> A_IWL<46974> A_IWL<46973> A_IWL<46972> A_IWL<46971> A_IWL<46970> A_IWL<46969> A_IWL<46968> A_IWL<46967> A_IWL<46966> A_IWL<46965> A_IWL<46964> A_IWL<46963> A_IWL<46962> A_IWL<46961> A_IWL<46960> A_IWL<46959> A_IWL<46958> A_IWL<46957> A_IWL<46956> A_IWL<46955> A_IWL<46954> A_IWL<46953> A_IWL<46952> A_IWL<46951> A_IWL<46950> A_IWL<46949> A_IWL<46948> A_IWL<46947> A_IWL<46946> A_IWL<46945> A_IWL<46944> A_IWL<46943> A_IWL<46942> A_IWL<46941> A_IWL<46940> A_IWL<46939> A_IWL<46938> A_IWL<46937> A_IWL<46936> A_IWL<46935> A_IWL<46934> A_IWL<46933> A_IWL<46932> A_IWL<46931> A_IWL<46930> A_IWL<46929> A_IWL<46928> A_IWL<46927> A_IWL<46926> A_IWL<46925> A_IWL<46924> A_IWL<46923> A_IWL<46922> A_IWL<46921> A_IWL<46920> A_IWL<46919> A_IWL<46918> A_IWL<46917> A_IWL<46916> A_IWL<46915> A_IWL<46914> A_IWL<46913> A_IWL<46912> A_IWL<46911> A_IWL<46910> A_IWL<46909> A_IWL<46908> A_IWL<46907> A_IWL<46906> A_IWL<46905> A_IWL<46904> A_IWL<46903> A_IWL<46902> A_IWL<46901> A_IWL<46900> A_IWL<46899> A_IWL<46898> A_IWL<46897> A_IWL<46896> A_IWL<46895> A_IWL<46894> A_IWL<46893> A_IWL<46892> A_IWL<46891> A_IWL<46890> A_IWL<46889> A_IWL<46888> A_IWL<46887> A_IWL<46886> A_IWL<46885> A_IWL<46884> A_IWL<46883> A_IWL<46882> A_IWL<46881> A_IWL<46880> A_IWL<46879> A_IWL<46878> A_IWL<46877> A_IWL<46876> A_IWL<46875> A_IWL<46874> A_IWL<46873> A_IWL<46872> A_IWL<46871> A_IWL<46870> A_IWL<46869> A_IWL<46868> A_IWL<46867> A_IWL<46866> A_IWL<46865> A_IWL<46864> A_IWL<46863> A_IWL<46862> A_IWL<46861> A_IWL<46860> A_IWL<46859> A_IWL<46858> A_IWL<46857> A_IWL<46856> A_IWL<46855> A_IWL<46854> A_IWL<46853> A_IWL<46852> A_IWL<46851> A_IWL<46850> A_IWL<46849> A_IWL<46848> A_IWL<46847> A_IWL<46846> A_IWL<46845> A_IWL<46844> A_IWL<46843> A_IWL<46842> A_IWL<46841> A_IWL<46840> A_IWL<46839> A_IWL<46838> A_IWL<46837> A_IWL<46836> A_IWL<46835> A_IWL<46834> A_IWL<46833> A_IWL<46832> A_IWL<46831> A_IWL<46830> A_IWL<46829> A_IWL<46828> A_IWL<46827> A_IWL<46826> A_IWL<46825> A_IWL<46824> A_IWL<46823> A_IWL<46822> A_IWL<46821> A_IWL<46820> A_IWL<46819> A_IWL<46818> A_IWL<46817> A_IWL<46816> A_IWL<46815> A_IWL<46814> A_IWL<46813> A_IWL<46812> A_IWL<46811> A_IWL<46810> A_IWL<46809> A_IWL<46808> A_IWL<46807> A_IWL<46806> A_IWL<46805> A_IWL<46804> A_IWL<46803> A_IWL<46802> A_IWL<46801> A_IWL<46800> A_IWL<46799> A_IWL<46798> A_IWL<46797> A_IWL<46796> A_IWL<46795> A_IWL<46794> A_IWL<46793> A_IWL<46792> A_IWL<46791> A_IWL<46790> A_IWL<46789> A_IWL<46788> A_IWL<46787> A_IWL<46786> A_IWL<46785> A_IWL<46784> A_IWL<46783> A_IWL<46782> A_IWL<46781> A_IWL<46780> A_IWL<46779> A_IWL<46778> A_IWL<46777> A_IWL<46776> A_IWL<46775> A_IWL<46774> A_IWL<46773> A_IWL<46772> A_IWL<46771> A_IWL<46770> A_IWL<46769> A_IWL<46768> A_IWL<46767> A_IWL<46766> A_IWL<46765> A_IWL<46764> A_IWL<46763> A_IWL<46762> A_IWL<46761> A_IWL<46760> A_IWL<46759> A_IWL<46758> A_IWL<46757> A_IWL<46756> A_IWL<46755> A_IWL<46754> A_IWL<46753> A_IWL<46752> A_IWL<46751> A_IWL<46750> A_IWL<46749> A_IWL<46748> A_IWL<46747> A_IWL<46746> A_IWL<46745> A_IWL<46744> A_IWL<46743> A_IWL<46742> A_IWL<46741> A_IWL<46740> A_IWL<46739> A_IWL<46738> A_IWL<46737> A_IWL<46736> A_IWL<46735> A_IWL<46734> A_IWL<46733> A_IWL<46732> A_IWL<46731> A_IWL<46730> A_IWL<46729> A_IWL<46728> A_IWL<46727> A_IWL<46726> A_IWL<46725> A_IWL<46724> A_IWL<46723> A_IWL<46722> A_IWL<46721> A_IWL<46720> A_IWL<46719> A_IWL<46718> A_IWL<46717> A_IWL<46716> A_IWL<46715> A_IWL<46714> A_IWL<46713> A_IWL<46712> A_IWL<46711> A_IWL<46710> A_IWL<46709> A_IWL<46708> A_IWL<46707> A_IWL<46706> A_IWL<46705> A_IWL<46704> A_IWL<46703> A_IWL<46702> A_IWL<46701> A_IWL<46700> A_IWL<46699> A_IWL<46698> A_IWL<46697> A_IWL<46696> A_IWL<46695> A_IWL<46694> A_IWL<46693> A_IWL<46692> A_IWL<46691> A_IWL<46690> A_IWL<46689> A_IWL<46688> A_IWL<46687> A_IWL<46686> A_IWL<46685> A_IWL<46684> A_IWL<46683> A_IWL<46682> A_IWL<46681> A_IWL<46680> A_IWL<46679> A_IWL<46678> A_IWL<46677> A_IWL<46676> A_IWL<46675> A_IWL<46674> A_IWL<46673> A_IWL<46672> A_IWL<46671> A_IWL<46670> A_IWL<46669> A_IWL<46668> A_IWL<46667> A_IWL<46666> A_IWL<46665> A_IWL<46664> A_IWL<46663> A_IWL<46662> A_IWL<46661> A_IWL<46660> A_IWL<46659> A_IWL<46658> A_IWL<46657> A_IWL<46656> A_IWL<46655> A_IWL<46654> A_IWL<46653> A_IWL<46652> A_IWL<46651> A_IWL<46650> A_IWL<46649> A_IWL<46648> A_IWL<46647> A_IWL<46646> A_IWL<46645> A_IWL<46644> A_IWL<46643> A_IWL<46642> A_IWL<46641> A_IWL<46640> A_IWL<46639> A_IWL<46638> A_IWL<46637> A_IWL<46636> A_IWL<46635> A_IWL<46634> A_IWL<46633> A_IWL<46632> A_IWL<46631> A_IWL<46630> A_IWL<46629> A_IWL<46628> A_IWL<46627> A_IWL<46626> A_IWL<46625> A_IWL<46624> A_IWL<46623> A_IWL<46622> A_IWL<46621> A_IWL<46620> A_IWL<46619> A_IWL<46618> A_IWL<46617> A_IWL<46616> A_IWL<46615> A_IWL<46614> A_IWL<46613> A_IWL<46612> A_IWL<46611> A_IWL<46610> A_IWL<46609> A_IWL<46608> A_IWL<46607> A_IWL<46606> A_IWL<46605> A_IWL<46604> A_IWL<46603> A_IWL<46602> A_IWL<46601> A_IWL<46600> A_IWL<46599> A_IWL<46598> A_IWL<46597> A_IWL<46596> A_IWL<46595> A_IWL<46594> A_IWL<46593> A_IWL<46592> A_IWL<47615> A_IWL<47614> A_IWL<47613> A_IWL<47612> A_IWL<47611> A_IWL<47610> A_IWL<47609> A_IWL<47608> A_IWL<47607> A_IWL<47606> A_IWL<47605> A_IWL<47604> A_IWL<47603> A_IWL<47602> A_IWL<47601> A_IWL<47600> A_IWL<47599> A_IWL<47598> A_IWL<47597> A_IWL<47596> A_IWL<47595> A_IWL<47594> A_IWL<47593> A_IWL<47592> A_IWL<47591> A_IWL<47590> A_IWL<47589> A_IWL<47588> A_IWL<47587> A_IWL<47586> A_IWL<47585> A_IWL<47584> A_IWL<47583> A_IWL<47582> A_IWL<47581> A_IWL<47580> A_IWL<47579> A_IWL<47578> A_IWL<47577> A_IWL<47576> A_IWL<47575> A_IWL<47574> A_IWL<47573> A_IWL<47572> A_IWL<47571> A_IWL<47570> A_IWL<47569> A_IWL<47568> A_IWL<47567> A_IWL<47566> A_IWL<47565> A_IWL<47564> A_IWL<47563> A_IWL<47562> A_IWL<47561> A_IWL<47560> A_IWL<47559> A_IWL<47558> A_IWL<47557> A_IWL<47556> A_IWL<47555> A_IWL<47554> A_IWL<47553> A_IWL<47552> A_IWL<47551> A_IWL<47550> A_IWL<47549> A_IWL<47548> A_IWL<47547> A_IWL<47546> A_IWL<47545> A_IWL<47544> A_IWL<47543> A_IWL<47542> A_IWL<47541> A_IWL<47540> A_IWL<47539> A_IWL<47538> A_IWL<47537> A_IWL<47536> A_IWL<47535> A_IWL<47534> A_IWL<47533> A_IWL<47532> A_IWL<47531> A_IWL<47530> A_IWL<47529> A_IWL<47528> A_IWL<47527> A_IWL<47526> A_IWL<47525> A_IWL<47524> A_IWL<47523> A_IWL<47522> A_IWL<47521> A_IWL<47520> A_IWL<47519> A_IWL<47518> A_IWL<47517> A_IWL<47516> A_IWL<47515> A_IWL<47514> A_IWL<47513> A_IWL<47512> A_IWL<47511> A_IWL<47510> A_IWL<47509> A_IWL<47508> A_IWL<47507> A_IWL<47506> A_IWL<47505> A_IWL<47504> A_IWL<47503> A_IWL<47502> A_IWL<47501> A_IWL<47500> A_IWL<47499> A_IWL<47498> A_IWL<47497> A_IWL<47496> A_IWL<47495> A_IWL<47494> A_IWL<47493> A_IWL<47492> A_IWL<47491> A_IWL<47490> A_IWL<47489> A_IWL<47488> A_IWL<47487> A_IWL<47486> A_IWL<47485> A_IWL<47484> A_IWL<47483> A_IWL<47482> A_IWL<47481> A_IWL<47480> A_IWL<47479> A_IWL<47478> A_IWL<47477> A_IWL<47476> A_IWL<47475> A_IWL<47474> A_IWL<47473> A_IWL<47472> A_IWL<47471> A_IWL<47470> A_IWL<47469> A_IWL<47468> A_IWL<47467> A_IWL<47466> A_IWL<47465> A_IWL<47464> A_IWL<47463> A_IWL<47462> A_IWL<47461> A_IWL<47460> A_IWL<47459> A_IWL<47458> A_IWL<47457> A_IWL<47456> A_IWL<47455> A_IWL<47454> A_IWL<47453> A_IWL<47452> A_IWL<47451> A_IWL<47450> A_IWL<47449> A_IWL<47448> A_IWL<47447> A_IWL<47446> A_IWL<47445> A_IWL<47444> A_IWL<47443> A_IWL<47442> A_IWL<47441> A_IWL<47440> A_IWL<47439> A_IWL<47438> A_IWL<47437> A_IWL<47436> A_IWL<47435> A_IWL<47434> A_IWL<47433> A_IWL<47432> A_IWL<47431> A_IWL<47430> A_IWL<47429> A_IWL<47428> A_IWL<47427> A_IWL<47426> A_IWL<47425> A_IWL<47424> A_IWL<47423> A_IWL<47422> A_IWL<47421> A_IWL<47420> A_IWL<47419> A_IWL<47418> A_IWL<47417> A_IWL<47416> A_IWL<47415> A_IWL<47414> A_IWL<47413> A_IWL<47412> A_IWL<47411> A_IWL<47410> A_IWL<47409> A_IWL<47408> A_IWL<47407> A_IWL<47406> A_IWL<47405> A_IWL<47404> A_IWL<47403> A_IWL<47402> A_IWL<47401> A_IWL<47400> A_IWL<47399> A_IWL<47398> A_IWL<47397> A_IWL<47396> A_IWL<47395> A_IWL<47394> A_IWL<47393> A_IWL<47392> A_IWL<47391> A_IWL<47390> A_IWL<47389> A_IWL<47388> A_IWL<47387> A_IWL<47386> A_IWL<47385> A_IWL<47384> A_IWL<47383> A_IWL<47382> A_IWL<47381> A_IWL<47380> A_IWL<47379> A_IWL<47378> A_IWL<47377> A_IWL<47376> A_IWL<47375> A_IWL<47374> A_IWL<47373> A_IWL<47372> A_IWL<47371> A_IWL<47370> A_IWL<47369> A_IWL<47368> A_IWL<47367> A_IWL<47366> A_IWL<47365> A_IWL<47364> A_IWL<47363> A_IWL<47362> A_IWL<47361> A_IWL<47360> A_IWL<47359> A_IWL<47358> A_IWL<47357> A_IWL<47356> A_IWL<47355> A_IWL<47354> A_IWL<47353> A_IWL<47352> A_IWL<47351> A_IWL<47350> A_IWL<47349> A_IWL<47348> A_IWL<47347> A_IWL<47346> A_IWL<47345> A_IWL<47344> A_IWL<47343> A_IWL<47342> A_IWL<47341> A_IWL<47340> A_IWL<47339> A_IWL<47338> A_IWL<47337> A_IWL<47336> A_IWL<47335> A_IWL<47334> A_IWL<47333> A_IWL<47332> A_IWL<47331> A_IWL<47330> A_IWL<47329> A_IWL<47328> A_IWL<47327> A_IWL<47326> A_IWL<47325> A_IWL<47324> A_IWL<47323> A_IWL<47322> A_IWL<47321> A_IWL<47320> A_IWL<47319> A_IWL<47318> A_IWL<47317> A_IWL<47316> A_IWL<47315> A_IWL<47314> A_IWL<47313> A_IWL<47312> A_IWL<47311> A_IWL<47310> A_IWL<47309> A_IWL<47308> A_IWL<47307> A_IWL<47306> A_IWL<47305> A_IWL<47304> A_IWL<47303> A_IWL<47302> A_IWL<47301> A_IWL<47300> A_IWL<47299> A_IWL<47298> A_IWL<47297> A_IWL<47296> A_IWL<47295> A_IWL<47294> A_IWL<47293> A_IWL<47292> A_IWL<47291> A_IWL<47290> A_IWL<47289> A_IWL<47288> A_IWL<47287> A_IWL<47286> A_IWL<47285> A_IWL<47284> A_IWL<47283> A_IWL<47282> A_IWL<47281> A_IWL<47280> A_IWL<47279> A_IWL<47278> A_IWL<47277> A_IWL<47276> A_IWL<47275> A_IWL<47274> A_IWL<47273> A_IWL<47272> A_IWL<47271> A_IWL<47270> A_IWL<47269> A_IWL<47268> A_IWL<47267> A_IWL<47266> A_IWL<47265> A_IWL<47264> A_IWL<47263> A_IWL<47262> A_IWL<47261> A_IWL<47260> A_IWL<47259> A_IWL<47258> A_IWL<47257> A_IWL<47256> A_IWL<47255> A_IWL<47254> A_IWL<47253> A_IWL<47252> A_IWL<47251> A_IWL<47250> A_IWL<47249> A_IWL<47248> A_IWL<47247> A_IWL<47246> A_IWL<47245> A_IWL<47244> A_IWL<47243> A_IWL<47242> A_IWL<47241> A_IWL<47240> A_IWL<47239> A_IWL<47238> A_IWL<47237> A_IWL<47236> A_IWL<47235> A_IWL<47234> A_IWL<47233> A_IWL<47232> A_IWL<47231> A_IWL<47230> A_IWL<47229> A_IWL<47228> A_IWL<47227> A_IWL<47226> A_IWL<47225> A_IWL<47224> A_IWL<47223> A_IWL<47222> A_IWL<47221> A_IWL<47220> A_IWL<47219> A_IWL<47218> A_IWL<47217> A_IWL<47216> A_IWL<47215> A_IWL<47214> A_IWL<47213> A_IWL<47212> A_IWL<47211> A_IWL<47210> A_IWL<47209> A_IWL<47208> A_IWL<47207> A_IWL<47206> A_IWL<47205> A_IWL<47204> A_IWL<47203> A_IWL<47202> A_IWL<47201> A_IWL<47200> A_IWL<47199> A_IWL<47198> A_IWL<47197> A_IWL<47196> A_IWL<47195> A_IWL<47194> A_IWL<47193> A_IWL<47192> A_IWL<47191> A_IWL<47190> A_IWL<47189> A_IWL<47188> A_IWL<47187> A_IWL<47186> A_IWL<47185> A_IWL<47184> A_IWL<47183> A_IWL<47182> A_IWL<47181> A_IWL<47180> A_IWL<47179> A_IWL<47178> A_IWL<47177> A_IWL<47176> A_IWL<47175> A_IWL<47174> A_IWL<47173> A_IWL<47172> A_IWL<47171> A_IWL<47170> A_IWL<47169> A_IWL<47168> A_IWL<47167> A_IWL<47166> A_IWL<47165> A_IWL<47164> A_IWL<47163> A_IWL<47162> A_IWL<47161> A_IWL<47160> A_IWL<47159> A_IWL<47158> A_IWL<47157> A_IWL<47156> A_IWL<47155> A_IWL<47154> A_IWL<47153> A_IWL<47152> A_IWL<47151> A_IWL<47150> A_IWL<47149> A_IWL<47148> A_IWL<47147> A_IWL<47146> A_IWL<47145> A_IWL<47144> A_IWL<47143> A_IWL<47142> A_IWL<47141> A_IWL<47140> A_IWL<47139> A_IWL<47138> A_IWL<47137> A_IWL<47136> A_IWL<47135> A_IWL<47134> A_IWL<47133> A_IWL<47132> A_IWL<47131> A_IWL<47130> A_IWL<47129> A_IWL<47128> A_IWL<47127> A_IWL<47126> A_IWL<47125> A_IWL<47124> A_IWL<47123> A_IWL<47122> A_IWL<47121> A_IWL<47120> A_IWL<47119> A_IWL<47118> A_IWL<47117> A_IWL<47116> A_IWL<47115> A_IWL<47114> A_IWL<47113> A_IWL<47112> A_IWL<47111> A_IWL<47110> A_IWL<47109> A_IWL<47108> A_IWL<47107> A_IWL<47106> A_IWL<47105> A_IWL<47104> VDD_CORE VSS / RM_IHPSG13_8192x32_c4_1P_COLUMN_pcell_0 +XCOL<91> A_BLC<183> A_BLC<182> A_BLC_TOP<183> A_BLC_TOP<182> A_BLT<183> A_BLT<182> A_BLT_TOP<183> A_BLT_TOP<182> A_IWL<46591> A_IWL<46590> A_IWL<46589> A_IWL<46588> A_IWL<46587> A_IWL<46586> A_IWL<46585> A_IWL<46584> A_IWL<46583> A_IWL<46582> A_IWL<46581> A_IWL<46580> A_IWL<46579> A_IWL<46578> A_IWL<46577> A_IWL<46576> A_IWL<46575> A_IWL<46574> A_IWL<46573> A_IWL<46572> A_IWL<46571> A_IWL<46570> A_IWL<46569> A_IWL<46568> A_IWL<46567> A_IWL<46566> A_IWL<46565> A_IWL<46564> A_IWL<46563> A_IWL<46562> A_IWL<46561> A_IWL<46560> A_IWL<46559> A_IWL<46558> A_IWL<46557> A_IWL<46556> A_IWL<46555> A_IWL<46554> A_IWL<46553> A_IWL<46552> A_IWL<46551> A_IWL<46550> A_IWL<46549> A_IWL<46548> A_IWL<46547> A_IWL<46546> A_IWL<46545> A_IWL<46544> A_IWL<46543> A_IWL<46542> A_IWL<46541> A_IWL<46540> A_IWL<46539> A_IWL<46538> A_IWL<46537> A_IWL<46536> A_IWL<46535> A_IWL<46534> A_IWL<46533> A_IWL<46532> A_IWL<46531> A_IWL<46530> A_IWL<46529> A_IWL<46528> A_IWL<46527> A_IWL<46526> A_IWL<46525> A_IWL<46524> A_IWL<46523> A_IWL<46522> A_IWL<46521> A_IWL<46520> A_IWL<46519> A_IWL<46518> A_IWL<46517> A_IWL<46516> A_IWL<46515> A_IWL<46514> A_IWL<46513> A_IWL<46512> A_IWL<46511> A_IWL<46510> A_IWL<46509> A_IWL<46508> A_IWL<46507> A_IWL<46506> A_IWL<46505> A_IWL<46504> A_IWL<46503> A_IWL<46502> A_IWL<46501> A_IWL<46500> A_IWL<46499> A_IWL<46498> A_IWL<46497> A_IWL<46496> A_IWL<46495> A_IWL<46494> A_IWL<46493> A_IWL<46492> A_IWL<46491> A_IWL<46490> A_IWL<46489> A_IWL<46488> A_IWL<46487> A_IWL<46486> A_IWL<46485> A_IWL<46484> A_IWL<46483> A_IWL<46482> A_IWL<46481> A_IWL<46480> A_IWL<46479> A_IWL<46478> A_IWL<46477> A_IWL<46476> A_IWL<46475> A_IWL<46474> A_IWL<46473> A_IWL<46472> A_IWL<46471> A_IWL<46470> A_IWL<46469> A_IWL<46468> A_IWL<46467> A_IWL<46466> A_IWL<46465> A_IWL<46464> A_IWL<46463> A_IWL<46462> A_IWL<46461> A_IWL<46460> A_IWL<46459> A_IWL<46458> A_IWL<46457> A_IWL<46456> A_IWL<46455> A_IWL<46454> A_IWL<46453> A_IWL<46452> A_IWL<46451> A_IWL<46450> A_IWL<46449> A_IWL<46448> A_IWL<46447> A_IWL<46446> A_IWL<46445> A_IWL<46444> A_IWL<46443> A_IWL<46442> A_IWL<46441> A_IWL<46440> A_IWL<46439> A_IWL<46438> A_IWL<46437> A_IWL<46436> A_IWL<46435> A_IWL<46434> A_IWL<46433> A_IWL<46432> A_IWL<46431> A_IWL<46430> A_IWL<46429> A_IWL<46428> A_IWL<46427> A_IWL<46426> A_IWL<46425> A_IWL<46424> A_IWL<46423> A_IWL<46422> A_IWL<46421> A_IWL<46420> A_IWL<46419> A_IWL<46418> A_IWL<46417> A_IWL<46416> A_IWL<46415> A_IWL<46414> A_IWL<46413> A_IWL<46412> A_IWL<46411> A_IWL<46410> A_IWL<46409> A_IWL<46408> A_IWL<46407> A_IWL<46406> A_IWL<46405> A_IWL<46404> A_IWL<46403> A_IWL<46402> A_IWL<46401> A_IWL<46400> A_IWL<46399> A_IWL<46398> A_IWL<46397> A_IWL<46396> A_IWL<46395> A_IWL<46394> A_IWL<46393> A_IWL<46392> A_IWL<46391> A_IWL<46390> A_IWL<46389> A_IWL<46388> A_IWL<46387> A_IWL<46386> A_IWL<46385> A_IWL<46384> A_IWL<46383> A_IWL<46382> A_IWL<46381> A_IWL<46380> A_IWL<46379> A_IWL<46378> A_IWL<46377> A_IWL<46376> A_IWL<46375> A_IWL<46374> A_IWL<46373> A_IWL<46372> A_IWL<46371> A_IWL<46370> A_IWL<46369> A_IWL<46368> A_IWL<46367> A_IWL<46366> A_IWL<46365> A_IWL<46364> A_IWL<46363> A_IWL<46362> A_IWL<46361> A_IWL<46360> A_IWL<46359> A_IWL<46358> A_IWL<46357> A_IWL<46356> A_IWL<46355> A_IWL<46354> A_IWL<46353> A_IWL<46352> A_IWL<46351> A_IWL<46350> A_IWL<46349> A_IWL<46348> A_IWL<46347> A_IWL<46346> A_IWL<46345> A_IWL<46344> A_IWL<46343> A_IWL<46342> A_IWL<46341> A_IWL<46340> A_IWL<46339> A_IWL<46338> A_IWL<46337> A_IWL<46336> A_IWL<46335> A_IWL<46334> A_IWL<46333> A_IWL<46332> A_IWL<46331> A_IWL<46330> A_IWL<46329> A_IWL<46328> A_IWL<46327> A_IWL<46326> A_IWL<46325> A_IWL<46324> A_IWL<46323> A_IWL<46322> A_IWL<46321> A_IWL<46320> A_IWL<46319> A_IWL<46318> A_IWL<46317> A_IWL<46316> A_IWL<46315> A_IWL<46314> A_IWL<46313> A_IWL<46312> A_IWL<46311> A_IWL<46310> A_IWL<46309> A_IWL<46308> A_IWL<46307> A_IWL<46306> A_IWL<46305> A_IWL<46304> A_IWL<46303> A_IWL<46302> A_IWL<46301> A_IWL<46300> A_IWL<46299> A_IWL<46298> A_IWL<46297> A_IWL<46296> A_IWL<46295> A_IWL<46294> A_IWL<46293> A_IWL<46292> A_IWL<46291> A_IWL<46290> A_IWL<46289> A_IWL<46288> A_IWL<46287> A_IWL<46286> A_IWL<46285> A_IWL<46284> A_IWL<46283> A_IWL<46282> A_IWL<46281> A_IWL<46280> A_IWL<46279> A_IWL<46278> A_IWL<46277> A_IWL<46276> A_IWL<46275> A_IWL<46274> A_IWL<46273> A_IWL<46272> A_IWL<46271> A_IWL<46270> A_IWL<46269> A_IWL<46268> A_IWL<46267> A_IWL<46266> A_IWL<46265> A_IWL<46264> A_IWL<46263> A_IWL<46262> A_IWL<46261> A_IWL<46260> A_IWL<46259> A_IWL<46258> A_IWL<46257> A_IWL<46256> A_IWL<46255> A_IWL<46254> A_IWL<46253> A_IWL<46252> A_IWL<46251> A_IWL<46250> A_IWL<46249> A_IWL<46248> A_IWL<46247> A_IWL<46246> A_IWL<46245> A_IWL<46244> A_IWL<46243> A_IWL<46242> A_IWL<46241> A_IWL<46240> A_IWL<46239> A_IWL<46238> A_IWL<46237> A_IWL<46236> A_IWL<46235> A_IWL<46234> A_IWL<46233> A_IWL<46232> A_IWL<46231> A_IWL<46230> A_IWL<46229> A_IWL<46228> A_IWL<46227> A_IWL<46226> A_IWL<46225> A_IWL<46224> A_IWL<46223> A_IWL<46222> A_IWL<46221> A_IWL<46220> A_IWL<46219> A_IWL<46218> A_IWL<46217> A_IWL<46216> A_IWL<46215> A_IWL<46214> A_IWL<46213> A_IWL<46212> A_IWL<46211> A_IWL<46210> A_IWL<46209> A_IWL<46208> A_IWL<46207> A_IWL<46206> A_IWL<46205> A_IWL<46204> A_IWL<46203> A_IWL<46202> A_IWL<46201> A_IWL<46200> A_IWL<46199> A_IWL<46198> A_IWL<46197> A_IWL<46196> A_IWL<46195> A_IWL<46194> A_IWL<46193> A_IWL<46192> A_IWL<46191> A_IWL<46190> A_IWL<46189> A_IWL<46188> A_IWL<46187> A_IWL<46186> A_IWL<46185> A_IWL<46184> A_IWL<46183> A_IWL<46182> A_IWL<46181> A_IWL<46180> A_IWL<46179> A_IWL<46178> A_IWL<46177> A_IWL<46176> A_IWL<46175> A_IWL<46174> A_IWL<46173> A_IWL<46172> A_IWL<46171> A_IWL<46170> A_IWL<46169> A_IWL<46168> A_IWL<46167> A_IWL<46166> A_IWL<46165> A_IWL<46164> A_IWL<46163> A_IWL<46162> A_IWL<46161> A_IWL<46160> A_IWL<46159> A_IWL<46158> A_IWL<46157> A_IWL<46156> A_IWL<46155> A_IWL<46154> A_IWL<46153> A_IWL<46152> A_IWL<46151> A_IWL<46150> A_IWL<46149> A_IWL<46148> A_IWL<46147> A_IWL<46146> A_IWL<46145> A_IWL<46144> A_IWL<46143> A_IWL<46142> A_IWL<46141> A_IWL<46140> A_IWL<46139> A_IWL<46138> A_IWL<46137> A_IWL<46136> A_IWL<46135> A_IWL<46134> A_IWL<46133> A_IWL<46132> A_IWL<46131> A_IWL<46130> A_IWL<46129> A_IWL<46128> A_IWL<46127> A_IWL<46126> A_IWL<46125> A_IWL<46124> A_IWL<46123> A_IWL<46122> A_IWL<46121> A_IWL<46120> A_IWL<46119> A_IWL<46118> A_IWL<46117> A_IWL<46116> A_IWL<46115> A_IWL<46114> A_IWL<46113> A_IWL<46112> A_IWL<46111> A_IWL<46110> A_IWL<46109> A_IWL<46108> A_IWL<46107> A_IWL<46106> A_IWL<46105> A_IWL<46104> A_IWL<46103> A_IWL<46102> A_IWL<46101> A_IWL<46100> A_IWL<46099> A_IWL<46098> A_IWL<46097> A_IWL<46096> A_IWL<46095> A_IWL<46094> A_IWL<46093> A_IWL<46092> A_IWL<46091> A_IWL<46090> A_IWL<46089> A_IWL<46088> A_IWL<46087> A_IWL<46086> A_IWL<46085> A_IWL<46084> A_IWL<46083> A_IWL<46082> A_IWL<46081> A_IWL<46080> A_IWL<47103> A_IWL<47102> A_IWL<47101> A_IWL<47100> A_IWL<47099> A_IWL<47098> A_IWL<47097> A_IWL<47096> A_IWL<47095> A_IWL<47094> A_IWL<47093> A_IWL<47092> A_IWL<47091> A_IWL<47090> A_IWL<47089> A_IWL<47088> A_IWL<47087> A_IWL<47086> A_IWL<47085> A_IWL<47084> A_IWL<47083> A_IWL<47082> A_IWL<47081> A_IWL<47080> A_IWL<47079> A_IWL<47078> A_IWL<47077> A_IWL<47076> A_IWL<47075> A_IWL<47074> A_IWL<47073> A_IWL<47072> A_IWL<47071> A_IWL<47070> A_IWL<47069> A_IWL<47068> A_IWL<47067> A_IWL<47066> A_IWL<47065> A_IWL<47064> A_IWL<47063> A_IWL<47062> A_IWL<47061> A_IWL<47060> A_IWL<47059> A_IWL<47058> A_IWL<47057> A_IWL<47056> A_IWL<47055> A_IWL<47054> A_IWL<47053> A_IWL<47052> A_IWL<47051> A_IWL<47050> A_IWL<47049> A_IWL<47048> A_IWL<47047> A_IWL<47046> A_IWL<47045> A_IWL<47044> A_IWL<47043> A_IWL<47042> A_IWL<47041> A_IWL<47040> A_IWL<47039> A_IWL<47038> A_IWL<47037> A_IWL<47036> A_IWL<47035> A_IWL<47034> A_IWL<47033> A_IWL<47032> A_IWL<47031> A_IWL<47030> A_IWL<47029> A_IWL<47028> A_IWL<47027> A_IWL<47026> A_IWL<47025> A_IWL<47024> A_IWL<47023> A_IWL<47022> A_IWL<47021> A_IWL<47020> A_IWL<47019> A_IWL<47018> A_IWL<47017> A_IWL<47016> A_IWL<47015> A_IWL<47014> A_IWL<47013> A_IWL<47012> A_IWL<47011> A_IWL<47010> A_IWL<47009> A_IWL<47008> A_IWL<47007> A_IWL<47006> A_IWL<47005> A_IWL<47004> A_IWL<47003> A_IWL<47002> A_IWL<47001> A_IWL<47000> A_IWL<46999> A_IWL<46998> A_IWL<46997> A_IWL<46996> A_IWL<46995> A_IWL<46994> A_IWL<46993> A_IWL<46992> A_IWL<46991> A_IWL<46990> A_IWL<46989> A_IWL<46988> A_IWL<46987> A_IWL<46986> A_IWL<46985> A_IWL<46984> A_IWL<46983> A_IWL<46982> A_IWL<46981> A_IWL<46980> A_IWL<46979> A_IWL<46978> A_IWL<46977> A_IWL<46976> A_IWL<46975> A_IWL<46974> A_IWL<46973> A_IWL<46972> A_IWL<46971> A_IWL<46970> A_IWL<46969> A_IWL<46968> A_IWL<46967> A_IWL<46966> A_IWL<46965> A_IWL<46964> A_IWL<46963> A_IWL<46962> A_IWL<46961> A_IWL<46960> A_IWL<46959> A_IWL<46958> A_IWL<46957> A_IWL<46956> A_IWL<46955> A_IWL<46954> A_IWL<46953> A_IWL<46952> A_IWL<46951> A_IWL<46950> A_IWL<46949> A_IWL<46948> A_IWL<46947> A_IWL<46946> A_IWL<46945> A_IWL<46944> A_IWL<46943> A_IWL<46942> A_IWL<46941> A_IWL<46940> A_IWL<46939> A_IWL<46938> A_IWL<46937> A_IWL<46936> A_IWL<46935> A_IWL<46934> A_IWL<46933> A_IWL<46932> A_IWL<46931> A_IWL<46930> A_IWL<46929> A_IWL<46928> A_IWL<46927> A_IWL<46926> A_IWL<46925> A_IWL<46924> A_IWL<46923> A_IWL<46922> A_IWL<46921> A_IWL<46920> A_IWL<46919> A_IWL<46918> A_IWL<46917> A_IWL<46916> A_IWL<46915> A_IWL<46914> A_IWL<46913> A_IWL<46912> A_IWL<46911> A_IWL<46910> A_IWL<46909> A_IWL<46908> A_IWL<46907> A_IWL<46906> A_IWL<46905> A_IWL<46904> A_IWL<46903> A_IWL<46902> A_IWL<46901> A_IWL<46900> A_IWL<46899> A_IWL<46898> A_IWL<46897> A_IWL<46896> A_IWL<46895> A_IWL<46894> A_IWL<46893> A_IWL<46892> A_IWL<46891> A_IWL<46890> A_IWL<46889> A_IWL<46888> A_IWL<46887> A_IWL<46886> A_IWL<46885> A_IWL<46884> A_IWL<46883> A_IWL<46882> A_IWL<46881> A_IWL<46880> A_IWL<46879> A_IWL<46878> A_IWL<46877> A_IWL<46876> A_IWL<46875> A_IWL<46874> A_IWL<46873> A_IWL<46872> A_IWL<46871> A_IWL<46870> A_IWL<46869> A_IWL<46868> A_IWL<46867> A_IWL<46866> A_IWL<46865> A_IWL<46864> A_IWL<46863> A_IWL<46862> A_IWL<46861> A_IWL<46860> A_IWL<46859> A_IWL<46858> A_IWL<46857> A_IWL<46856> A_IWL<46855> A_IWL<46854> A_IWL<46853> A_IWL<46852> A_IWL<46851> A_IWL<46850> A_IWL<46849> A_IWL<46848> A_IWL<46847> A_IWL<46846> A_IWL<46845> A_IWL<46844> A_IWL<46843> A_IWL<46842> A_IWL<46841> A_IWL<46840> A_IWL<46839> A_IWL<46838> A_IWL<46837> A_IWL<46836> A_IWL<46835> A_IWL<46834> A_IWL<46833> A_IWL<46832> A_IWL<46831> A_IWL<46830> A_IWL<46829> A_IWL<46828> A_IWL<46827> A_IWL<46826> A_IWL<46825> A_IWL<46824> A_IWL<46823> A_IWL<46822> A_IWL<46821> A_IWL<46820> A_IWL<46819> A_IWL<46818> A_IWL<46817> A_IWL<46816> A_IWL<46815> A_IWL<46814> A_IWL<46813> A_IWL<46812> A_IWL<46811> A_IWL<46810> A_IWL<46809> A_IWL<46808> A_IWL<46807> A_IWL<46806> A_IWL<46805> A_IWL<46804> A_IWL<46803> A_IWL<46802> A_IWL<46801> A_IWL<46800> A_IWL<46799> A_IWL<46798> A_IWL<46797> A_IWL<46796> A_IWL<46795> A_IWL<46794> A_IWL<46793> A_IWL<46792> A_IWL<46791> A_IWL<46790> A_IWL<46789> A_IWL<46788> A_IWL<46787> A_IWL<46786> A_IWL<46785> A_IWL<46784> A_IWL<46783> A_IWL<46782> A_IWL<46781> A_IWL<46780> A_IWL<46779> A_IWL<46778> A_IWL<46777> A_IWL<46776> A_IWL<46775> A_IWL<46774> A_IWL<46773> A_IWL<46772> A_IWL<46771> A_IWL<46770> A_IWL<46769> A_IWL<46768> A_IWL<46767> A_IWL<46766> A_IWL<46765> A_IWL<46764> A_IWL<46763> A_IWL<46762> A_IWL<46761> A_IWL<46760> A_IWL<46759> A_IWL<46758> A_IWL<46757> A_IWL<46756> A_IWL<46755> A_IWL<46754> A_IWL<46753> A_IWL<46752> A_IWL<46751> A_IWL<46750> A_IWL<46749> A_IWL<46748> A_IWL<46747> A_IWL<46746> A_IWL<46745> A_IWL<46744> A_IWL<46743> A_IWL<46742> A_IWL<46741> A_IWL<46740> A_IWL<46739> A_IWL<46738> A_IWL<46737> A_IWL<46736> A_IWL<46735> A_IWL<46734> A_IWL<46733> A_IWL<46732> A_IWL<46731> A_IWL<46730> A_IWL<46729> A_IWL<46728> A_IWL<46727> A_IWL<46726> A_IWL<46725> A_IWL<46724> A_IWL<46723> A_IWL<46722> A_IWL<46721> A_IWL<46720> A_IWL<46719> A_IWL<46718> A_IWL<46717> A_IWL<46716> A_IWL<46715> A_IWL<46714> A_IWL<46713> A_IWL<46712> A_IWL<46711> A_IWL<46710> A_IWL<46709> A_IWL<46708> A_IWL<46707> A_IWL<46706> A_IWL<46705> A_IWL<46704> A_IWL<46703> A_IWL<46702> A_IWL<46701> A_IWL<46700> A_IWL<46699> A_IWL<46698> A_IWL<46697> A_IWL<46696> A_IWL<46695> A_IWL<46694> A_IWL<46693> A_IWL<46692> A_IWL<46691> A_IWL<46690> A_IWL<46689> A_IWL<46688> A_IWL<46687> A_IWL<46686> A_IWL<46685> A_IWL<46684> A_IWL<46683> A_IWL<46682> A_IWL<46681> A_IWL<46680> A_IWL<46679> A_IWL<46678> A_IWL<46677> A_IWL<46676> A_IWL<46675> A_IWL<46674> A_IWL<46673> A_IWL<46672> A_IWL<46671> A_IWL<46670> A_IWL<46669> A_IWL<46668> A_IWL<46667> A_IWL<46666> A_IWL<46665> A_IWL<46664> A_IWL<46663> A_IWL<46662> A_IWL<46661> A_IWL<46660> A_IWL<46659> A_IWL<46658> A_IWL<46657> A_IWL<46656> A_IWL<46655> A_IWL<46654> A_IWL<46653> A_IWL<46652> A_IWL<46651> A_IWL<46650> A_IWL<46649> A_IWL<46648> A_IWL<46647> A_IWL<46646> A_IWL<46645> A_IWL<46644> A_IWL<46643> A_IWL<46642> A_IWL<46641> A_IWL<46640> A_IWL<46639> A_IWL<46638> A_IWL<46637> A_IWL<46636> A_IWL<46635> A_IWL<46634> A_IWL<46633> A_IWL<46632> A_IWL<46631> A_IWL<46630> A_IWL<46629> A_IWL<46628> A_IWL<46627> A_IWL<46626> A_IWL<46625> A_IWL<46624> A_IWL<46623> A_IWL<46622> A_IWL<46621> A_IWL<46620> A_IWL<46619> A_IWL<46618> A_IWL<46617> A_IWL<46616> A_IWL<46615> A_IWL<46614> A_IWL<46613> A_IWL<46612> A_IWL<46611> A_IWL<46610> A_IWL<46609> A_IWL<46608> A_IWL<46607> A_IWL<46606> A_IWL<46605> A_IWL<46604> A_IWL<46603> A_IWL<46602> A_IWL<46601> A_IWL<46600> A_IWL<46599> A_IWL<46598> A_IWL<46597> A_IWL<46596> A_IWL<46595> A_IWL<46594> A_IWL<46593> A_IWL<46592> VDD_CORE VSS / RM_IHPSG13_8192x32_c4_1P_COLUMN_pcell_0 +XCOL<90> A_BLC<181> A_BLC<180> A_BLC_TOP<181> A_BLC_TOP<180> A_BLT<181> A_BLT<180> A_BLT_TOP<181> A_BLT_TOP<180> A_IWL<46079> A_IWL<46078> A_IWL<46077> A_IWL<46076> A_IWL<46075> A_IWL<46074> A_IWL<46073> A_IWL<46072> A_IWL<46071> A_IWL<46070> A_IWL<46069> A_IWL<46068> A_IWL<46067> A_IWL<46066> A_IWL<46065> A_IWL<46064> A_IWL<46063> A_IWL<46062> A_IWL<46061> A_IWL<46060> A_IWL<46059> A_IWL<46058> A_IWL<46057> A_IWL<46056> A_IWL<46055> A_IWL<46054> A_IWL<46053> A_IWL<46052> A_IWL<46051> A_IWL<46050> A_IWL<46049> A_IWL<46048> A_IWL<46047> A_IWL<46046> A_IWL<46045> A_IWL<46044> A_IWL<46043> A_IWL<46042> A_IWL<46041> A_IWL<46040> A_IWL<46039> A_IWL<46038> A_IWL<46037> A_IWL<46036> A_IWL<46035> A_IWL<46034> A_IWL<46033> A_IWL<46032> A_IWL<46031> A_IWL<46030> A_IWL<46029> A_IWL<46028> A_IWL<46027> A_IWL<46026> A_IWL<46025> A_IWL<46024> A_IWL<46023> A_IWL<46022> A_IWL<46021> A_IWL<46020> A_IWL<46019> A_IWL<46018> A_IWL<46017> A_IWL<46016> A_IWL<46015> A_IWL<46014> A_IWL<46013> A_IWL<46012> A_IWL<46011> A_IWL<46010> A_IWL<46009> A_IWL<46008> A_IWL<46007> A_IWL<46006> A_IWL<46005> A_IWL<46004> A_IWL<46003> A_IWL<46002> A_IWL<46001> A_IWL<46000> A_IWL<45999> A_IWL<45998> A_IWL<45997> A_IWL<45996> A_IWL<45995> A_IWL<45994> A_IWL<45993> A_IWL<45992> A_IWL<45991> A_IWL<45990> A_IWL<45989> A_IWL<45988> A_IWL<45987> A_IWL<45986> A_IWL<45985> A_IWL<45984> A_IWL<45983> A_IWL<45982> A_IWL<45981> A_IWL<45980> A_IWL<45979> A_IWL<45978> A_IWL<45977> A_IWL<45976> A_IWL<45975> A_IWL<45974> A_IWL<45973> A_IWL<45972> A_IWL<45971> A_IWL<45970> A_IWL<45969> A_IWL<45968> A_IWL<45967> A_IWL<45966> A_IWL<45965> A_IWL<45964> A_IWL<45963> A_IWL<45962> A_IWL<45961> A_IWL<45960> A_IWL<45959> A_IWL<45958> A_IWL<45957> A_IWL<45956> A_IWL<45955> A_IWL<45954> A_IWL<45953> A_IWL<45952> A_IWL<45951> A_IWL<45950> A_IWL<45949> A_IWL<45948> A_IWL<45947> A_IWL<45946> A_IWL<45945> A_IWL<45944> A_IWL<45943> A_IWL<45942> A_IWL<45941> A_IWL<45940> A_IWL<45939> A_IWL<45938> A_IWL<45937> A_IWL<45936> A_IWL<45935> A_IWL<45934> A_IWL<45933> A_IWL<45932> A_IWL<45931> A_IWL<45930> A_IWL<45929> A_IWL<45928> A_IWL<45927> A_IWL<45926> A_IWL<45925> A_IWL<45924> A_IWL<45923> A_IWL<45922> A_IWL<45921> A_IWL<45920> A_IWL<45919> A_IWL<45918> A_IWL<45917> A_IWL<45916> A_IWL<45915> A_IWL<45914> A_IWL<45913> A_IWL<45912> A_IWL<45911> A_IWL<45910> A_IWL<45909> A_IWL<45908> A_IWL<45907> A_IWL<45906> A_IWL<45905> A_IWL<45904> A_IWL<45903> A_IWL<45902> A_IWL<45901> A_IWL<45900> A_IWL<45899> A_IWL<45898> A_IWL<45897> A_IWL<45896> A_IWL<45895> A_IWL<45894> A_IWL<45893> A_IWL<45892> A_IWL<45891> A_IWL<45890> A_IWL<45889> A_IWL<45888> A_IWL<45887> A_IWL<45886> A_IWL<45885> A_IWL<45884> A_IWL<45883> A_IWL<45882> A_IWL<45881> A_IWL<45880> A_IWL<45879> A_IWL<45878> A_IWL<45877> A_IWL<45876> A_IWL<45875> A_IWL<45874> A_IWL<45873> A_IWL<45872> A_IWL<45871> A_IWL<45870> A_IWL<45869> A_IWL<45868> A_IWL<45867> A_IWL<45866> A_IWL<45865> A_IWL<45864> A_IWL<45863> A_IWL<45862> A_IWL<45861> A_IWL<45860> A_IWL<45859> A_IWL<45858> A_IWL<45857> A_IWL<45856> A_IWL<45855> A_IWL<45854> A_IWL<45853> A_IWL<45852> A_IWL<45851> A_IWL<45850> A_IWL<45849> A_IWL<45848> A_IWL<45847> A_IWL<45846> A_IWL<45845> A_IWL<45844> A_IWL<45843> A_IWL<45842> A_IWL<45841> A_IWL<45840> A_IWL<45839> A_IWL<45838> A_IWL<45837> A_IWL<45836> A_IWL<45835> A_IWL<45834> A_IWL<45833> A_IWL<45832> A_IWL<45831> A_IWL<45830> A_IWL<45829> A_IWL<45828> A_IWL<45827> A_IWL<45826> A_IWL<45825> A_IWL<45824> A_IWL<45823> A_IWL<45822> A_IWL<45821> A_IWL<45820> A_IWL<45819> A_IWL<45818> A_IWL<45817> A_IWL<45816> A_IWL<45815> A_IWL<45814> A_IWL<45813> A_IWL<45812> A_IWL<45811> A_IWL<45810> A_IWL<45809> A_IWL<45808> A_IWL<45807> A_IWL<45806> A_IWL<45805> A_IWL<45804> A_IWL<45803> A_IWL<45802> A_IWL<45801> A_IWL<45800> A_IWL<45799> A_IWL<45798> A_IWL<45797> A_IWL<45796> A_IWL<45795> A_IWL<45794> A_IWL<45793> A_IWL<45792> A_IWL<45791> A_IWL<45790> A_IWL<45789> A_IWL<45788> A_IWL<45787> A_IWL<45786> A_IWL<45785> A_IWL<45784> A_IWL<45783> A_IWL<45782> A_IWL<45781> A_IWL<45780> A_IWL<45779> A_IWL<45778> A_IWL<45777> A_IWL<45776> A_IWL<45775> A_IWL<45774> A_IWL<45773> A_IWL<45772> A_IWL<45771> A_IWL<45770> A_IWL<45769> A_IWL<45768> A_IWL<45767> A_IWL<45766> A_IWL<45765> A_IWL<45764> A_IWL<45763> A_IWL<45762> A_IWL<45761> A_IWL<45760> A_IWL<45759> A_IWL<45758> A_IWL<45757> A_IWL<45756> A_IWL<45755> A_IWL<45754> A_IWL<45753> A_IWL<45752> A_IWL<45751> A_IWL<45750> A_IWL<45749> A_IWL<45748> A_IWL<45747> A_IWL<45746> A_IWL<45745> A_IWL<45744> A_IWL<45743> A_IWL<45742> A_IWL<45741> A_IWL<45740> A_IWL<45739> A_IWL<45738> A_IWL<45737> A_IWL<45736> A_IWL<45735> A_IWL<45734> A_IWL<45733> A_IWL<45732> A_IWL<45731> A_IWL<45730> A_IWL<45729> A_IWL<45728> A_IWL<45727> A_IWL<45726> A_IWL<45725> A_IWL<45724> A_IWL<45723> A_IWL<45722> A_IWL<45721> A_IWL<45720> A_IWL<45719> A_IWL<45718> A_IWL<45717> A_IWL<45716> A_IWL<45715> A_IWL<45714> A_IWL<45713> A_IWL<45712> A_IWL<45711> A_IWL<45710> A_IWL<45709> A_IWL<45708> A_IWL<45707> A_IWL<45706> A_IWL<45705> A_IWL<45704> A_IWL<45703> A_IWL<45702> A_IWL<45701> A_IWL<45700> A_IWL<45699> A_IWL<45698> A_IWL<45697> A_IWL<45696> A_IWL<45695> A_IWL<45694> A_IWL<45693> A_IWL<45692> A_IWL<45691> A_IWL<45690> A_IWL<45689> A_IWL<45688> A_IWL<45687> A_IWL<45686> A_IWL<45685> A_IWL<45684> A_IWL<45683> A_IWL<45682> A_IWL<45681> A_IWL<45680> A_IWL<45679> A_IWL<45678> A_IWL<45677> A_IWL<45676> A_IWL<45675> A_IWL<45674> A_IWL<45673> A_IWL<45672> A_IWL<45671> A_IWL<45670> A_IWL<45669> A_IWL<45668> A_IWL<45667> A_IWL<45666> A_IWL<45665> A_IWL<45664> A_IWL<45663> A_IWL<45662> A_IWL<45661> A_IWL<45660> A_IWL<45659> A_IWL<45658> A_IWL<45657> A_IWL<45656> A_IWL<45655> A_IWL<45654> A_IWL<45653> A_IWL<45652> A_IWL<45651> A_IWL<45650> A_IWL<45649> A_IWL<45648> A_IWL<45647> A_IWL<45646> A_IWL<45645> A_IWL<45644> A_IWL<45643> A_IWL<45642> A_IWL<45641> A_IWL<45640> A_IWL<45639> A_IWL<45638> A_IWL<45637> A_IWL<45636> A_IWL<45635> A_IWL<45634> A_IWL<45633> A_IWL<45632> A_IWL<45631> A_IWL<45630> A_IWL<45629> A_IWL<45628> A_IWL<45627> A_IWL<45626> A_IWL<45625> A_IWL<45624> A_IWL<45623> A_IWL<45622> A_IWL<45621> A_IWL<45620> A_IWL<45619> A_IWL<45618> A_IWL<45617> A_IWL<45616> A_IWL<45615> A_IWL<45614> A_IWL<45613> A_IWL<45612> A_IWL<45611> A_IWL<45610> A_IWL<45609> A_IWL<45608> A_IWL<45607> A_IWL<45606> A_IWL<45605> A_IWL<45604> A_IWL<45603> A_IWL<45602> A_IWL<45601> A_IWL<45600> A_IWL<45599> A_IWL<45598> A_IWL<45597> A_IWL<45596> A_IWL<45595> A_IWL<45594> A_IWL<45593> A_IWL<45592> A_IWL<45591> A_IWL<45590> A_IWL<45589> A_IWL<45588> A_IWL<45587> A_IWL<45586> A_IWL<45585> A_IWL<45584> A_IWL<45583> A_IWL<45582> A_IWL<45581> A_IWL<45580> A_IWL<45579> A_IWL<45578> A_IWL<45577> A_IWL<45576> A_IWL<45575> A_IWL<45574> A_IWL<45573> A_IWL<45572> A_IWL<45571> A_IWL<45570> A_IWL<45569> A_IWL<45568> A_IWL<46591> A_IWL<46590> A_IWL<46589> A_IWL<46588> A_IWL<46587> A_IWL<46586> A_IWL<46585> A_IWL<46584> A_IWL<46583> A_IWL<46582> A_IWL<46581> A_IWL<46580> A_IWL<46579> A_IWL<46578> A_IWL<46577> A_IWL<46576> A_IWL<46575> A_IWL<46574> A_IWL<46573> A_IWL<46572> A_IWL<46571> A_IWL<46570> A_IWL<46569> A_IWL<46568> A_IWL<46567> A_IWL<46566> A_IWL<46565> A_IWL<46564> A_IWL<46563> A_IWL<46562> A_IWL<46561> A_IWL<46560> A_IWL<46559> A_IWL<46558> A_IWL<46557> A_IWL<46556> A_IWL<46555> A_IWL<46554> A_IWL<46553> A_IWL<46552> A_IWL<46551> A_IWL<46550> A_IWL<46549> A_IWL<46548> A_IWL<46547> A_IWL<46546> A_IWL<46545> A_IWL<46544> A_IWL<46543> A_IWL<46542> A_IWL<46541> A_IWL<46540> A_IWL<46539> A_IWL<46538> A_IWL<46537> A_IWL<46536> A_IWL<46535> A_IWL<46534> A_IWL<46533> A_IWL<46532> A_IWL<46531> A_IWL<46530> A_IWL<46529> A_IWL<46528> A_IWL<46527> A_IWL<46526> A_IWL<46525> A_IWL<46524> A_IWL<46523> A_IWL<46522> A_IWL<46521> A_IWL<46520> A_IWL<46519> A_IWL<46518> A_IWL<46517> A_IWL<46516> A_IWL<46515> A_IWL<46514> A_IWL<46513> A_IWL<46512> A_IWL<46511> A_IWL<46510> A_IWL<46509> A_IWL<46508> A_IWL<46507> A_IWL<46506> A_IWL<46505> A_IWL<46504> A_IWL<46503> A_IWL<46502> A_IWL<46501> A_IWL<46500> A_IWL<46499> A_IWL<46498> A_IWL<46497> A_IWL<46496> A_IWL<46495> A_IWL<46494> A_IWL<46493> A_IWL<46492> A_IWL<46491> A_IWL<46490> A_IWL<46489> A_IWL<46488> A_IWL<46487> A_IWL<46486> A_IWL<46485> A_IWL<46484> A_IWL<46483> A_IWL<46482> A_IWL<46481> A_IWL<46480> A_IWL<46479> A_IWL<46478> A_IWL<46477> A_IWL<46476> A_IWL<46475> A_IWL<46474> A_IWL<46473> A_IWL<46472> A_IWL<46471> A_IWL<46470> A_IWL<46469> A_IWL<46468> A_IWL<46467> A_IWL<46466> A_IWL<46465> A_IWL<46464> A_IWL<46463> A_IWL<46462> A_IWL<46461> A_IWL<46460> A_IWL<46459> A_IWL<46458> A_IWL<46457> A_IWL<46456> A_IWL<46455> A_IWL<46454> A_IWL<46453> A_IWL<46452> A_IWL<46451> A_IWL<46450> A_IWL<46449> A_IWL<46448> A_IWL<46447> A_IWL<46446> A_IWL<46445> A_IWL<46444> A_IWL<46443> A_IWL<46442> A_IWL<46441> A_IWL<46440> A_IWL<46439> A_IWL<46438> A_IWL<46437> A_IWL<46436> A_IWL<46435> A_IWL<46434> A_IWL<46433> A_IWL<46432> A_IWL<46431> A_IWL<46430> A_IWL<46429> A_IWL<46428> A_IWL<46427> A_IWL<46426> A_IWL<46425> A_IWL<46424> A_IWL<46423> A_IWL<46422> A_IWL<46421> A_IWL<46420> A_IWL<46419> A_IWL<46418> A_IWL<46417> A_IWL<46416> A_IWL<46415> A_IWL<46414> A_IWL<46413> A_IWL<46412> A_IWL<46411> A_IWL<46410> A_IWL<46409> A_IWL<46408> A_IWL<46407> A_IWL<46406> A_IWL<46405> A_IWL<46404> A_IWL<46403> A_IWL<46402> A_IWL<46401> A_IWL<46400> A_IWL<46399> A_IWL<46398> A_IWL<46397> A_IWL<46396> A_IWL<46395> A_IWL<46394> A_IWL<46393> A_IWL<46392> A_IWL<46391> A_IWL<46390> A_IWL<46389> A_IWL<46388> A_IWL<46387> A_IWL<46386> A_IWL<46385> A_IWL<46384> A_IWL<46383> A_IWL<46382> A_IWL<46381> A_IWL<46380> A_IWL<46379> A_IWL<46378> A_IWL<46377> A_IWL<46376> A_IWL<46375> A_IWL<46374> A_IWL<46373> A_IWL<46372> A_IWL<46371> A_IWL<46370> A_IWL<46369> A_IWL<46368> A_IWL<46367> A_IWL<46366> A_IWL<46365> A_IWL<46364> A_IWL<46363> A_IWL<46362> A_IWL<46361> A_IWL<46360> A_IWL<46359> A_IWL<46358> A_IWL<46357> A_IWL<46356> A_IWL<46355> A_IWL<46354> A_IWL<46353> A_IWL<46352> A_IWL<46351> A_IWL<46350> A_IWL<46349> A_IWL<46348> A_IWL<46347> A_IWL<46346> A_IWL<46345> A_IWL<46344> A_IWL<46343> A_IWL<46342> A_IWL<46341> A_IWL<46340> A_IWL<46339> A_IWL<46338> A_IWL<46337> A_IWL<46336> A_IWL<46335> A_IWL<46334> A_IWL<46333> A_IWL<46332> A_IWL<46331> A_IWL<46330> A_IWL<46329> A_IWL<46328> A_IWL<46327> A_IWL<46326> A_IWL<46325> A_IWL<46324> A_IWL<46323> A_IWL<46322> A_IWL<46321> A_IWL<46320> A_IWL<46319> A_IWL<46318> A_IWL<46317> A_IWL<46316> A_IWL<46315> A_IWL<46314> A_IWL<46313> A_IWL<46312> A_IWL<46311> A_IWL<46310> A_IWL<46309> A_IWL<46308> A_IWL<46307> A_IWL<46306> A_IWL<46305> A_IWL<46304> A_IWL<46303> A_IWL<46302> A_IWL<46301> A_IWL<46300> A_IWL<46299> A_IWL<46298> A_IWL<46297> A_IWL<46296> A_IWL<46295> A_IWL<46294> A_IWL<46293> A_IWL<46292> A_IWL<46291> A_IWL<46290> A_IWL<46289> A_IWL<46288> A_IWL<46287> A_IWL<46286> A_IWL<46285> A_IWL<46284> A_IWL<46283> A_IWL<46282> A_IWL<46281> A_IWL<46280> A_IWL<46279> A_IWL<46278> A_IWL<46277> A_IWL<46276> A_IWL<46275> A_IWL<46274> A_IWL<46273> A_IWL<46272> A_IWL<46271> A_IWL<46270> A_IWL<46269> A_IWL<46268> A_IWL<46267> A_IWL<46266> A_IWL<46265> A_IWL<46264> A_IWL<46263> A_IWL<46262> A_IWL<46261> A_IWL<46260> A_IWL<46259> A_IWL<46258> A_IWL<46257> A_IWL<46256> A_IWL<46255> A_IWL<46254> A_IWL<46253> A_IWL<46252> A_IWL<46251> A_IWL<46250> A_IWL<46249> A_IWL<46248> A_IWL<46247> A_IWL<46246> A_IWL<46245> A_IWL<46244> A_IWL<46243> A_IWL<46242> A_IWL<46241> A_IWL<46240> A_IWL<46239> A_IWL<46238> A_IWL<46237> A_IWL<46236> A_IWL<46235> A_IWL<46234> A_IWL<46233> A_IWL<46232> A_IWL<46231> A_IWL<46230> A_IWL<46229> A_IWL<46228> A_IWL<46227> A_IWL<46226> A_IWL<46225> A_IWL<46224> A_IWL<46223> A_IWL<46222> A_IWL<46221> A_IWL<46220> A_IWL<46219> A_IWL<46218> A_IWL<46217> A_IWL<46216> A_IWL<46215> A_IWL<46214> A_IWL<46213> A_IWL<46212> A_IWL<46211> A_IWL<46210> A_IWL<46209> A_IWL<46208> A_IWL<46207> A_IWL<46206> A_IWL<46205> A_IWL<46204> A_IWL<46203> A_IWL<46202> A_IWL<46201> A_IWL<46200> A_IWL<46199> A_IWL<46198> A_IWL<46197> A_IWL<46196> A_IWL<46195> A_IWL<46194> A_IWL<46193> A_IWL<46192> A_IWL<46191> A_IWL<46190> A_IWL<46189> A_IWL<46188> A_IWL<46187> A_IWL<46186> A_IWL<46185> A_IWL<46184> A_IWL<46183> A_IWL<46182> A_IWL<46181> A_IWL<46180> A_IWL<46179> A_IWL<46178> A_IWL<46177> A_IWL<46176> A_IWL<46175> A_IWL<46174> A_IWL<46173> A_IWL<46172> A_IWL<46171> A_IWL<46170> A_IWL<46169> A_IWL<46168> A_IWL<46167> A_IWL<46166> A_IWL<46165> A_IWL<46164> A_IWL<46163> A_IWL<46162> A_IWL<46161> A_IWL<46160> A_IWL<46159> A_IWL<46158> A_IWL<46157> A_IWL<46156> A_IWL<46155> A_IWL<46154> A_IWL<46153> A_IWL<46152> A_IWL<46151> A_IWL<46150> A_IWL<46149> A_IWL<46148> A_IWL<46147> A_IWL<46146> A_IWL<46145> A_IWL<46144> A_IWL<46143> A_IWL<46142> A_IWL<46141> A_IWL<46140> A_IWL<46139> A_IWL<46138> A_IWL<46137> A_IWL<46136> A_IWL<46135> A_IWL<46134> A_IWL<46133> A_IWL<46132> A_IWL<46131> A_IWL<46130> A_IWL<46129> A_IWL<46128> A_IWL<46127> A_IWL<46126> A_IWL<46125> A_IWL<46124> A_IWL<46123> A_IWL<46122> A_IWL<46121> A_IWL<46120> A_IWL<46119> A_IWL<46118> A_IWL<46117> A_IWL<46116> A_IWL<46115> A_IWL<46114> A_IWL<46113> A_IWL<46112> A_IWL<46111> A_IWL<46110> A_IWL<46109> A_IWL<46108> A_IWL<46107> A_IWL<46106> A_IWL<46105> A_IWL<46104> A_IWL<46103> A_IWL<46102> A_IWL<46101> A_IWL<46100> A_IWL<46099> A_IWL<46098> A_IWL<46097> A_IWL<46096> A_IWL<46095> A_IWL<46094> A_IWL<46093> A_IWL<46092> A_IWL<46091> A_IWL<46090> A_IWL<46089> A_IWL<46088> A_IWL<46087> A_IWL<46086> A_IWL<46085> A_IWL<46084> A_IWL<46083> A_IWL<46082> A_IWL<46081> A_IWL<46080> VDD_CORE VSS / RM_IHPSG13_8192x32_c4_1P_COLUMN_pcell_0 +XCOL<89> A_BLC<179> A_BLC<178> A_BLC_TOP<179> A_BLC_TOP<178> A_BLT<179> A_BLT<178> A_BLT_TOP<179> A_BLT_TOP<178> A_IWL<45567> A_IWL<45566> A_IWL<45565> A_IWL<45564> A_IWL<45563> A_IWL<45562> A_IWL<45561> A_IWL<45560> A_IWL<45559> A_IWL<45558> A_IWL<45557> A_IWL<45556> A_IWL<45555> A_IWL<45554> A_IWL<45553> A_IWL<45552> A_IWL<45551> A_IWL<45550> A_IWL<45549> A_IWL<45548> A_IWL<45547> A_IWL<45546> A_IWL<45545> A_IWL<45544> A_IWL<45543> A_IWL<45542> A_IWL<45541> A_IWL<45540> A_IWL<45539> A_IWL<45538> A_IWL<45537> A_IWL<45536> A_IWL<45535> A_IWL<45534> A_IWL<45533> A_IWL<45532> A_IWL<45531> A_IWL<45530> A_IWL<45529> A_IWL<45528> A_IWL<45527> A_IWL<45526> A_IWL<45525> A_IWL<45524> A_IWL<45523> A_IWL<45522> A_IWL<45521> A_IWL<45520> A_IWL<45519> A_IWL<45518> A_IWL<45517> A_IWL<45516> A_IWL<45515> A_IWL<45514> A_IWL<45513> A_IWL<45512> A_IWL<45511> A_IWL<45510> A_IWL<45509> A_IWL<45508> A_IWL<45507> A_IWL<45506> A_IWL<45505> A_IWL<45504> A_IWL<45503> A_IWL<45502> A_IWL<45501> A_IWL<45500> A_IWL<45499> A_IWL<45498> A_IWL<45497> A_IWL<45496> A_IWL<45495> A_IWL<45494> A_IWL<45493> A_IWL<45492> A_IWL<45491> A_IWL<45490> A_IWL<45489> A_IWL<45488> A_IWL<45487> A_IWL<45486> A_IWL<45485> A_IWL<45484> A_IWL<45483> A_IWL<45482> A_IWL<45481> A_IWL<45480> A_IWL<45479> A_IWL<45478> A_IWL<45477> A_IWL<45476> A_IWL<45475> A_IWL<45474> A_IWL<45473> A_IWL<45472> A_IWL<45471> A_IWL<45470> A_IWL<45469> A_IWL<45468> A_IWL<45467> A_IWL<45466> A_IWL<45465> A_IWL<45464> A_IWL<45463> A_IWL<45462> A_IWL<45461> A_IWL<45460> A_IWL<45459> A_IWL<45458> A_IWL<45457> A_IWL<45456> A_IWL<45455> A_IWL<45454> A_IWL<45453> A_IWL<45452> A_IWL<45451> A_IWL<45450> A_IWL<45449> A_IWL<45448> A_IWL<45447> A_IWL<45446> A_IWL<45445> A_IWL<45444> A_IWL<45443> A_IWL<45442> A_IWL<45441> A_IWL<45440> A_IWL<45439> A_IWL<45438> A_IWL<45437> A_IWL<45436> A_IWL<45435> A_IWL<45434> A_IWL<45433> A_IWL<45432> A_IWL<45431> A_IWL<45430> A_IWL<45429> A_IWL<45428> A_IWL<45427> A_IWL<45426> A_IWL<45425> A_IWL<45424> A_IWL<45423> A_IWL<45422> A_IWL<45421> A_IWL<45420> A_IWL<45419> A_IWL<45418> A_IWL<45417> A_IWL<45416> A_IWL<45415> A_IWL<45414> A_IWL<45413> A_IWL<45412> A_IWL<45411> A_IWL<45410> A_IWL<45409> A_IWL<45408> A_IWL<45407> A_IWL<45406> A_IWL<45405> A_IWL<45404> A_IWL<45403> A_IWL<45402> A_IWL<45401> A_IWL<45400> A_IWL<45399> A_IWL<45398> A_IWL<45397> A_IWL<45396> A_IWL<45395> A_IWL<45394> A_IWL<45393> A_IWL<45392> A_IWL<45391> A_IWL<45390> A_IWL<45389> A_IWL<45388> A_IWL<45387> A_IWL<45386> A_IWL<45385> A_IWL<45384> A_IWL<45383> A_IWL<45382> A_IWL<45381> A_IWL<45380> A_IWL<45379> A_IWL<45378> A_IWL<45377> A_IWL<45376> A_IWL<45375> A_IWL<45374> A_IWL<45373> A_IWL<45372> A_IWL<45371> A_IWL<45370> A_IWL<45369> A_IWL<45368> A_IWL<45367> A_IWL<45366> A_IWL<45365> A_IWL<45364> A_IWL<45363> A_IWL<45362> A_IWL<45361> A_IWL<45360> A_IWL<45359> A_IWL<45358> A_IWL<45357> A_IWL<45356> A_IWL<45355> A_IWL<45354> A_IWL<45353> A_IWL<45352> A_IWL<45351> A_IWL<45350> A_IWL<45349> A_IWL<45348> A_IWL<45347> A_IWL<45346> A_IWL<45345> A_IWL<45344> A_IWL<45343> A_IWL<45342> A_IWL<45341> A_IWL<45340> A_IWL<45339> A_IWL<45338> A_IWL<45337> A_IWL<45336> A_IWL<45335> A_IWL<45334> A_IWL<45333> A_IWL<45332> A_IWL<45331> A_IWL<45330> A_IWL<45329> A_IWL<45328> A_IWL<45327> A_IWL<45326> A_IWL<45325> A_IWL<45324> A_IWL<45323> A_IWL<45322> A_IWL<45321> A_IWL<45320> A_IWL<45319> A_IWL<45318> A_IWL<45317> A_IWL<45316> A_IWL<45315> A_IWL<45314> A_IWL<45313> A_IWL<45312> A_IWL<45311> A_IWL<45310> A_IWL<45309> A_IWL<45308> A_IWL<45307> A_IWL<45306> A_IWL<45305> A_IWL<45304> A_IWL<45303> A_IWL<45302> A_IWL<45301> A_IWL<45300> A_IWL<45299> A_IWL<45298> A_IWL<45297> A_IWL<45296> A_IWL<45295> A_IWL<45294> A_IWL<45293> A_IWL<45292> A_IWL<45291> A_IWL<45290> A_IWL<45289> A_IWL<45288> A_IWL<45287> A_IWL<45286> A_IWL<45285> A_IWL<45284> A_IWL<45283> A_IWL<45282> A_IWL<45281> A_IWL<45280> A_IWL<45279> A_IWL<45278> A_IWL<45277> A_IWL<45276> A_IWL<45275> A_IWL<45274> A_IWL<45273> A_IWL<45272> A_IWL<45271> A_IWL<45270> A_IWL<45269> A_IWL<45268> A_IWL<45267> A_IWL<45266> A_IWL<45265> A_IWL<45264> A_IWL<45263> A_IWL<45262> A_IWL<45261> A_IWL<45260> A_IWL<45259> A_IWL<45258> A_IWL<45257> A_IWL<45256> A_IWL<45255> A_IWL<45254> A_IWL<45253> A_IWL<45252> A_IWL<45251> A_IWL<45250> A_IWL<45249> A_IWL<45248> A_IWL<45247> A_IWL<45246> A_IWL<45245> A_IWL<45244> A_IWL<45243> A_IWL<45242> A_IWL<45241> A_IWL<45240> A_IWL<45239> A_IWL<45238> A_IWL<45237> A_IWL<45236> A_IWL<45235> A_IWL<45234> A_IWL<45233> A_IWL<45232> A_IWL<45231> A_IWL<45230> A_IWL<45229> A_IWL<45228> A_IWL<45227> A_IWL<45226> A_IWL<45225> A_IWL<45224> A_IWL<45223> A_IWL<45222> A_IWL<45221> A_IWL<45220> A_IWL<45219> A_IWL<45218> A_IWL<45217> A_IWL<45216> A_IWL<45215> A_IWL<45214> A_IWL<45213> A_IWL<45212> A_IWL<45211> A_IWL<45210> A_IWL<45209> A_IWL<45208> A_IWL<45207> A_IWL<45206> A_IWL<45205> A_IWL<45204> A_IWL<45203> A_IWL<45202> A_IWL<45201> A_IWL<45200> A_IWL<45199> A_IWL<45198> A_IWL<45197> A_IWL<45196> A_IWL<45195> A_IWL<45194> A_IWL<45193> A_IWL<45192> A_IWL<45191> A_IWL<45190> A_IWL<45189> A_IWL<45188> A_IWL<45187> A_IWL<45186> A_IWL<45185> A_IWL<45184> A_IWL<45183> A_IWL<45182> A_IWL<45181> A_IWL<45180> A_IWL<45179> A_IWL<45178> A_IWL<45177> A_IWL<45176> A_IWL<45175> A_IWL<45174> A_IWL<45173> A_IWL<45172> A_IWL<45171> A_IWL<45170> A_IWL<45169> A_IWL<45168> A_IWL<45167> A_IWL<45166> A_IWL<45165> A_IWL<45164> A_IWL<45163> A_IWL<45162> A_IWL<45161> A_IWL<45160> A_IWL<45159> A_IWL<45158> A_IWL<45157> A_IWL<45156> A_IWL<45155> A_IWL<45154> A_IWL<45153> A_IWL<45152> A_IWL<45151> A_IWL<45150> A_IWL<45149> A_IWL<45148> A_IWL<45147> A_IWL<45146> A_IWL<45145> A_IWL<45144> A_IWL<45143> A_IWL<45142> A_IWL<45141> A_IWL<45140> A_IWL<45139> A_IWL<45138> A_IWL<45137> A_IWL<45136> A_IWL<45135> A_IWL<45134> A_IWL<45133> A_IWL<45132> A_IWL<45131> A_IWL<45130> A_IWL<45129> A_IWL<45128> A_IWL<45127> A_IWL<45126> A_IWL<45125> A_IWL<45124> A_IWL<45123> A_IWL<45122> A_IWL<45121> A_IWL<45120> A_IWL<45119> A_IWL<45118> A_IWL<45117> A_IWL<45116> A_IWL<45115> A_IWL<45114> A_IWL<45113> A_IWL<45112> A_IWL<45111> A_IWL<45110> A_IWL<45109> A_IWL<45108> A_IWL<45107> A_IWL<45106> A_IWL<45105> A_IWL<45104> A_IWL<45103> A_IWL<45102> A_IWL<45101> A_IWL<45100> A_IWL<45099> A_IWL<45098> A_IWL<45097> A_IWL<45096> A_IWL<45095> A_IWL<45094> A_IWL<45093> A_IWL<45092> A_IWL<45091> A_IWL<45090> A_IWL<45089> A_IWL<45088> A_IWL<45087> A_IWL<45086> A_IWL<45085> A_IWL<45084> A_IWL<45083> A_IWL<45082> A_IWL<45081> A_IWL<45080> A_IWL<45079> A_IWL<45078> A_IWL<45077> A_IWL<45076> A_IWL<45075> A_IWL<45074> A_IWL<45073> A_IWL<45072> A_IWL<45071> A_IWL<45070> A_IWL<45069> A_IWL<45068> A_IWL<45067> A_IWL<45066> A_IWL<45065> A_IWL<45064> A_IWL<45063> A_IWL<45062> A_IWL<45061> A_IWL<45060> A_IWL<45059> A_IWL<45058> A_IWL<45057> A_IWL<45056> A_IWL<46079> A_IWL<46078> A_IWL<46077> A_IWL<46076> A_IWL<46075> A_IWL<46074> A_IWL<46073> A_IWL<46072> A_IWL<46071> A_IWL<46070> A_IWL<46069> A_IWL<46068> A_IWL<46067> A_IWL<46066> A_IWL<46065> A_IWL<46064> A_IWL<46063> A_IWL<46062> A_IWL<46061> A_IWL<46060> A_IWL<46059> A_IWL<46058> A_IWL<46057> A_IWL<46056> A_IWL<46055> A_IWL<46054> A_IWL<46053> A_IWL<46052> A_IWL<46051> A_IWL<46050> A_IWL<46049> A_IWL<46048> A_IWL<46047> A_IWL<46046> A_IWL<46045> A_IWL<46044> A_IWL<46043> A_IWL<46042> A_IWL<46041> A_IWL<46040> A_IWL<46039> A_IWL<46038> A_IWL<46037> A_IWL<46036> A_IWL<46035> A_IWL<46034> A_IWL<46033> A_IWL<46032> A_IWL<46031> A_IWL<46030> A_IWL<46029> A_IWL<46028> A_IWL<46027> A_IWL<46026> A_IWL<46025> A_IWL<46024> A_IWL<46023> A_IWL<46022> A_IWL<46021> A_IWL<46020> A_IWL<46019> A_IWL<46018> A_IWL<46017> A_IWL<46016> A_IWL<46015> A_IWL<46014> A_IWL<46013> A_IWL<46012> A_IWL<46011> A_IWL<46010> A_IWL<46009> A_IWL<46008> A_IWL<46007> A_IWL<46006> A_IWL<46005> A_IWL<46004> A_IWL<46003> A_IWL<46002> A_IWL<46001> A_IWL<46000> A_IWL<45999> A_IWL<45998> A_IWL<45997> A_IWL<45996> A_IWL<45995> A_IWL<45994> A_IWL<45993> A_IWL<45992> A_IWL<45991> A_IWL<45990> A_IWL<45989> A_IWL<45988> A_IWL<45987> A_IWL<45986> A_IWL<45985> A_IWL<45984> A_IWL<45983> A_IWL<45982> A_IWL<45981> A_IWL<45980> A_IWL<45979> A_IWL<45978> A_IWL<45977> A_IWL<45976> A_IWL<45975> A_IWL<45974> A_IWL<45973> A_IWL<45972> A_IWL<45971> A_IWL<45970> A_IWL<45969> A_IWL<45968> A_IWL<45967> A_IWL<45966> A_IWL<45965> A_IWL<45964> A_IWL<45963> A_IWL<45962> A_IWL<45961> A_IWL<45960> A_IWL<45959> A_IWL<45958> A_IWL<45957> A_IWL<45956> A_IWL<45955> A_IWL<45954> A_IWL<45953> A_IWL<45952> A_IWL<45951> A_IWL<45950> A_IWL<45949> A_IWL<45948> A_IWL<45947> A_IWL<45946> A_IWL<45945> A_IWL<45944> A_IWL<45943> A_IWL<45942> A_IWL<45941> A_IWL<45940> A_IWL<45939> A_IWL<45938> A_IWL<45937> A_IWL<45936> A_IWL<45935> A_IWL<45934> A_IWL<45933> A_IWL<45932> A_IWL<45931> A_IWL<45930> A_IWL<45929> A_IWL<45928> A_IWL<45927> A_IWL<45926> A_IWL<45925> A_IWL<45924> A_IWL<45923> A_IWL<45922> A_IWL<45921> A_IWL<45920> A_IWL<45919> A_IWL<45918> A_IWL<45917> A_IWL<45916> A_IWL<45915> A_IWL<45914> A_IWL<45913> A_IWL<45912> A_IWL<45911> A_IWL<45910> A_IWL<45909> A_IWL<45908> A_IWL<45907> A_IWL<45906> A_IWL<45905> A_IWL<45904> A_IWL<45903> A_IWL<45902> A_IWL<45901> A_IWL<45900> A_IWL<45899> A_IWL<45898> A_IWL<45897> A_IWL<45896> A_IWL<45895> A_IWL<45894> A_IWL<45893> A_IWL<45892> A_IWL<45891> A_IWL<45890> A_IWL<45889> A_IWL<45888> A_IWL<45887> A_IWL<45886> A_IWL<45885> A_IWL<45884> A_IWL<45883> A_IWL<45882> A_IWL<45881> A_IWL<45880> A_IWL<45879> A_IWL<45878> A_IWL<45877> A_IWL<45876> A_IWL<45875> A_IWL<45874> A_IWL<45873> A_IWL<45872> A_IWL<45871> A_IWL<45870> A_IWL<45869> A_IWL<45868> A_IWL<45867> A_IWL<45866> A_IWL<45865> A_IWL<45864> A_IWL<45863> A_IWL<45862> A_IWL<45861> A_IWL<45860> A_IWL<45859> A_IWL<45858> A_IWL<45857> A_IWL<45856> A_IWL<45855> A_IWL<45854> A_IWL<45853> A_IWL<45852> A_IWL<45851> A_IWL<45850> A_IWL<45849> A_IWL<45848> A_IWL<45847> A_IWL<45846> A_IWL<45845> A_IWL<45844> A_IWL<45843> A_IWL<45842> A_IWL<45841> A_IWL<45840> A_IWL<45839> A_IWL<45838> A_IWL<45837> A_IWL<45836> A_IWL<45835> A_IWL<45834> A_IWL<45833> A_IWL<45832> A_IWL<45831> A_IWL<45830> A_IWL<45829> A_IWL<45828> A_IWL<45827> A_IWL<45826> A_IWL<45825> A_IWL<45824> A_IWL<45823> A_IWL<45822> A_IWL<45821> A_IWL<45820> A_IWL<45819> A_IWL<45818> A_IWL<45817> A_IWL<45816> A_IWL<45815> A_IWL<45814> A_IWL<45813> A_IWL<45812> A_IWL<45811> A_IWL<45810> A_IWL<45809> A_IWL<45808> A_IWL<45807> A_IWL<45806> A_IWL<45805> A_IWL<45804> A_IWL<45803> A_IWL<45802> A_IWL<45801> A_IWL<45800> A_IWL<45799> A_IWL<45798> A_IWL<45797> A_IWL<45796> A_IWL<45795> A_IWL<45794> A_IWL<45793> A_IWL<45792> A_IWL<45791> A_IWL<45790> A_IWL<45789> A_IWL<45788> A_IWL<45787> A_IWL<45786> A_IWL<45785> A_IWL<45784> A_IWL<45783> A_IWL<45782> A_IWL<45781> A_IWL<45780> A_IWL<45779> A_IWL<45778> A_IWL<45777> A_IWL<45776> A_IWL<45775> A_IWL<45774> A_IWL<45773> A_IWL<45772> A_IWL<45771> A_IWL<45770> A_IWL<45769> A_IWL<45768> A_IWL<45767> A_IWL<45766> A_IWL<45765> A_IWL<45764> A_IWL<45763> A_IWL<45762> A_IWL<45761> A_IWL<45760> A_IWL<45759> A_IWL<45758> A_IWL<45757> A_IWL<45756> A_IWL<45755> A_IWL<45754> A_IWL<45753> A_IWL<45752> A_IWL<45751> A_IWL<45750> A_IWL<45749> A_IWL<45748> A_IWL<45747> A_IWL<45746> A_IWL<45745> A_IWL<45744> A_IWL<45743> A_IWL<45742> A_IWL<45741> A_IWL<45740> A_IWL<45739> A_IWL<45738> A_IWL<45737> A_IWL<45736> A_IWL<45735> A_IWL<45734> A_IWL<45733> A_IWL<45732> A_IWL<45731> A_IWL<45730> A_IWL<45729> A_IWL<45728> A_IWL<45727> A_IWL<45726> A_IWL<45725> A_IWL<45724> A_IWL<45723> A_IWL<45722> A_IWL<45721> A_IWL<45720> A_IWL<45719> A_IWL<45718> A_IWL<45717> A_IWL<45716> A_IWL<45715> A_IWL<45714> A_IWL<45713> A_IWL<45712> A_IWL<45711> A_IWL<45710> A_IWL<45709> A_IWL<45708> A_IWL<45707> A_IWL<45706> A_IWL<45705> A_IWL<45704> A_IWL<45703> A_IWL<45702> A_IWL<45701> A_IWL<45700> A_IWL<45699> A_IWL<45698> A_IWL<45697> A_IWL<45696> A_IWL<45695> A_IWL<45694> A_IWL<45693> A_IWL<45692> A_IWL<45691> A_IWL<45690> A_IWL<45689> A_IWL<45688> A_IWL<45687> A_IWL<45686> A_IWL<45685> A_IWL<45684> A_IWL<45683> A_IWL<45682> A_IWL<45681> A_IWL<45680> A_IWL<45679> A_IWL<45678> A_IWL<45677> A_IWL<45676> A_IWL<45675> A_IWL<45674> A_IWL<45673> A_IWL<45672> A_IWL<45671> A_IWL<45670> A_IWL<45669> A_IWL<45668> A_IWL<45667> A_IWL<45666> A_IWL<45665> A_IWL<45664> A_IWL<45663> A_IWL<45662> A_IWL<45661> A_IWL<45660> A_IWL<45659> A_IWL<45658> A_IWL<45657> A_IWL<45656> A_IWL<45655> A_IWL<45654> A_IWL<45653> A_IWL<45652> A_IWL<45651> A_IWL<45650> A_IWL<45649> A_IWL<45648> A_IWL<45647> A_IWL<45646> A_IWL<45645> A_IWL<45644> A_IWL<45643> A_IWL<45642> A_IWL<45641> A_IWL<45640> A_IWL<45639> A_IWL<45638> A_IWL<45637> A_IWL<45636> A_IWL<45635> A_IWL<45634> A_IWL<45633> A_IWL<45632> A_IWL<45631> A_IWL<45630> A_IWL<45629> A_IWL<45628> A_IWL<45627> A_IWL<45626> A_IWL<45625> A_IWL<45624> A_IWL<45623> A_IWL<45622> A_IWL<45621> A_IWL<45620> A_IWL<45619> A_IWL<45618> A_IWL<45617> A_IWL<45616> A_IWL<45615> A_IWL<45614> A_IWL<45613> A_IWL<45612> A_IWL<45611> A_IWL<45610> A_IWL<45609> A_IWL<45608> A_IWL<45607> A_IWL<45606> A_IWL<45605> A_IWL<45604> A_IWL<45603> A_IWL<45602> A_IWL<45601> A_IWL<45600> A_IWL<45599> A_IWL<45598> A_IWL<45597> A_IWL<45596> A_IWL<45595> A_IWL<45594> A_IWL<45593> A_IWL<45592> A_IWL<45591> A_IWL<45590> A_IWL<45589> A_IWL<45588> A_IWL<45587> A_IWL<45586> A_IWL<45585> A_IWL<45584> A_IWL<45583> A_IWL<45582> A_IWL<45581> A_IWL<45580> A_IWL<45579> A_IWL<45578> A_IWL<45577> A_IWL<45576> A_IWL<45575> A_IWL<45574> A_IWL<45573> A_IWL<45572> A_IWL<45571> A_IWL<45570> A_IWL<45569> A_IWL<45568> VDD_CORE VSS / RM_IHPSG13_8192x32_c4_1P_COLUMN_pcell_0 +XCOL<88> A_BLC<177> A_BLC<176> A_BLC_TOP<177> A_BLC_TOP<176> A_BLT<177> A_BLT<176> A_BLT_TOP<177> A_BLT_TOP<176> A_IWL<45055> A_IWL<45054> A_IWL<45053> A_IWL<45052> A_IWL<45051> A_IWL<45050> A_IWL<45049> A_IWL<45048> A_IWL<45047> A_IWL<45046> A_IWL<45045> A_IWL<45044> A_IWL<45043> A_IWL<45042> A_IWL<45041> A_IWL<45040> A_IWL<45039> A_IWL<45038> A_IWL<45037> A_IWL<45036> A_IWL<45035> A_IWL<45034> A_IWL<45033> A_IWL<45032> A_IWL<45031> A_IWL<45030> A_IWL<45029> A_IWL<45028> A_IWL<45027> A_IWL<45026> A_IWL<45025> A_IWL<45024> A_IWL<45023> A_IWL<45022> A_IWL<45021> A_IWL<45020> A_IWL<45019> A_IWL<45018> A_IWL<45017> A_IWL<45016> A_IWL<45015> A_IWL<45014> A_IWL<45013> A_IWL<45012> A_IWL<45011> A_IWL<45010> A_IWL<45009> A_IWL<45008> A_IWL<45007> A_IWL<45006> A_IWL<45005> A_IWL<45004> A_IWL<45003> A_IWL<45002> A_IWL<45001> A_IWL<45000> A_IWL<44999> A_IWL<44998> A_IWL<44997> A_IWL<44996> A_IWL<44995> A_IWL<44994> A_IWL<44993> A_IWL<44992> A_IWL<44991> A_IWL<44990> A_IWL<44989> A_IWL<44988> A_IWL<44987> A_IWL<44986> A_IWL<44985> A_IWL<44984> A_IWL<44983> A_IWL<44982> A_IWL<44981> A_IWL<44980> A_IWL<44979> A_IWL<44978> A_IWL<44977> A_IWL<44976> A_IWL<44975> A_IWL<44974> A_IWL<44973> A_IWL<44972> A_IWL<44971> A_IWL<44970> A_IWL<44969> A_IWL<44968> A_IWL<44967> A_IWL<44966> A_IWL<44965> A_IWL<44964> A_IWL<44963> A_IWL<44962> A_IWL<44961> A_IWL<44960> A_IWL<44959> A_IWL<44958> A_IWL<44957> A_IWL<44956> A_IWL<44955> A_IWL<44954> A_IWL<44953> A_IWL<44952> A_IWL<44951> A_IWL<44950> A_IWL<44949> A_IWL<44948> A_IWL<44947> A_IWL<44946> A_IWL<44945> A_IWL<44944> A_IWL<44943> A_IWL<44942> A_IWL<44941> A_IWL<44940> A_IWL<44939> A_IWL<44938> A_IWL<44937> A_IWL<44936> A_IWL<44935> A_IWL<44934> A_IWL<44933> A_IWL<44932> A_IWL<44931> A_IWL<44930> A_IWL<44929> A_IWL<44928> A_IWL<44927> A_IWL<44926> A_IWL<44925> A_IWL<44924> A_IWL<44923> A_IWL<44922> A_IWL<44921> A_IWL<44920> A_IWL<44919> A_IWL<44918> A_IWL<44917> A_IWL<44916> A_IWL<44915> A_IWL<44914> A_IWL<44913> A_IWL<44912> A_IWL<44911> A_IWL<44910> A_IWL<44909> A_IWL<44908> A_IWL<44907> A_IWL<44906> A_IWL<44905> A_IWL<44904> A_IWL<44903> A_IWL<44902> A_IWL<44901> A_IWL<44900> A_IWL<44899> A_IWL<44898> A_IWL<44897> A_IWL<44896> A_IWL<44895> A_IWL<44894> A_IWL<44893> A_IWL<44892> A_IWL<44891> A_IWL<44890> A_IWL<44889> A_IWL<44888> A_IWL<44887> A_IWL<44886> A_IWL<44885> A_IWL<44884> A_IWL<44883> A_IWL<44882> A_IWL<44881> A_IWL<44880> A_IWL<44879> A_IWL<44878> A_IWL<44877> A_IWL<44876> A_IWL<44875> A_IWL<44874> A_IWL<44873> A_IWL<44872> A_IWL<44871> A_IWL<44870> A_IWL<44869> A_IWL<44868> A_IWL<44867> A_IWL<44866> A_IWL<44865> A_IWL<44864> A_IWL<44863> A_IWL<44862> A_IWL<44861> A_IWL<44860> A_IWL<44859> A_IWL<44858> A_IWL<44857> A_IWL<44856> A_IWL<44855> A_IWL<44854> A_IWL<44853> A_IWL<44852> A_IWL<44851> A_IWL<44850> A_IWL<44849> A_IWL<44848> A_IWL<44847> A_IWL<44846> A_IWL<44845> A_IWL<44844> A_IWL<44843> A_IWL<44842> A_IWL<44841> A_IWL<44840> A_IWL<44839> A_IWL<44838> A_IWL<44837> A_IWL<44836> A_IWL<44835> A_IWL<44834> A_IWL<44833> A_IWL<44832> A_IWL<44831> A_IWL<44830> A_IWL<44829> A_IWL<44828> A_IWL<44827> A_IWL<44826> A_IWL<44825> A_IWL<44824> A_IWL<44823> A_IWL<44822> A_IWL<44821> A_IWL<44820> A_IWL<44819> A_IWL<44818> A_IWL<44817> A_IWL<44816> A_IWL<44815> A_IWL<44814> A_IWL<44813> A_IWL<44812> A_IWL<44811> A_IWL<44810> A_IWL<44809> A_IWL<44808> A_IWL<44807> A_IWL<44806> A_IWL<44805> A_IWL<44804> A_IWL<44803> A_IWL<44802> A_IWL<44801> A_IWL<44800> A_IWL<44799> A_IWL<44798> A_IWL<44797> A_IWL<44796> A_IWL<44795> A_IWL<44794> A_IWL<44793> A_IWL<44792> A_IWL<44791> A_IWL<44790> A_IWL<44789> A_IWL<44788> A_IWL<44787> A_IWL<44786> A_IWL<44785> A_IWL<44784> A_IWL<44783> A_IWL<44782> A_IWL<44781> A_IWL<44780> A_IWL<44779> A_IWL<44778> A_IWL<44777> A_IWL<44776> A_IWL<44775> A_IWL<44774> A_IWL<44773> A_IWL<44772> A_IWL<44771> A_IWL<44770> A_IWL<44769> A_IWL<44768> A_IWL<44767> A_IWL<44766> A_IWL<44765> A_IWL<44764> A_IWL<44763> A_IWL<44762> A_IWL<44761> A_IWL<44760> A_IWL<44759> A_IWL<44758> A_IWL<44757> A_IWL<44756> A_IWL<44755> A_IWL<44754> A_IWL<44753> A_IWL<44752> A_IWL<44751> A_IWL<44750> A_IWL<44749> A_IWL<44748> A_IWL<44747> A_IWL<44746> A_IWL<44745> A_IWL<44744> A_IWL<44743> A_IWL<44742> A_IWL<44741> A_IWL<44740> A_IWL<44739> A_IWL<44738> A_IWL<44737> A_IWL<44736> A_IWL<44735> A_IWL<44734> A_IWL<44733> A_IWL<44732> A_IWL<44731> A_IWL<44730> A_IWL<44729> A_IWL<44728> A_IWL<44727> A_IWL<44726> A_IWL<44725> A_IWL<44724> A_IWL<44723> A_IWL<44722> A_IWL<44721> A_IWL<44720> A_IWL<44719> A_IWL<44718> A_IWL<44717> A_IWL<44716> A_IWL<44715> A_IWL<44714> A_IWL<44713> A_IWL<44712> A_IWL<44711> A_IWL<44710> A_IWL<44709> A_IWL<44708> A_IWL<44707> A_IWL<44706> A_IWL<44705> A_IWL<44704> A_IWL<44703> A_IWL<44702> A_IWL<44701> A_IWL<44700> A_IWL<44699> A_IWL<44698> A_IWL<44697> A_IWL<44696> A_IWL<44695> A_IWL<44694> A_IWL<44693> A_IWL<44692> A_IWL<44691> A_IWL<44690> A_IWL<44689> A_IWL<44688> A_IWL<44687> A_IWL<44686> A_IWL<44685> A_IWL<44684> A_IWL<44683> A_IWL<44682> A_IWL<44681> A_IWL<44680> A_IWL<44679> A_IWL<44678> A_IWL<44677> A_IWL<44676> A_IWL<44675> A_IWL<44674> A_IWL<44673> A_IWL<44672> A_IWL<44671> A_IWL<44670> A_IWL<44669> A_IWL<44668> A_IWL<44667> A_IWL<44666> A_IWL<44665> A_IWL<44664> A_IWL<44663> A_IWL<44662> A_IWL<44661> A_IWL<44660> A_IWL<44659> A_IWL<44658> A_IWL<44657> A_IWL<44656> A_IWL<44655> A_IWL<44654> A_IWL<44653> A_IWL<44652> A_IWL<44651> A_IWL<44650> A_IWL<44649> A_IWL<44648> A_IWL<44647> A_IWL<44646> A_IWL<44645> A_IWL<44644> A_IWL<44643> A_IWL<44642> A_IWL<44641> A_IWL<44640> A_IWL<44639> A_IWL<44638> A_IWL<44637> A_IWL<44636> A_IWL<44635> A_IWL<44634> A_IWL<44633> A_IWL<44632> A_IWL<44631> A_IWL<44630> A_IWL<44629> A_IWL<44628> A_IWL<44627> A_IWL<44626> A_IWL<44625> A_IWL<44624> A_IWL<44623> A_IWL<44622> A_IWL<44621> A_IWL<44620> A_IWL<44619> A_IWL<44618> A_IWL<44617> A_IWL<44616> A_IWL<44615> A_IWL<44614> A_IWL<44613> A_IWL<44612> A_IWL<44611> A_IWL<44610> A_IWL<44609> A_IWL<44608> A_IWL<44607> A_IWL<44606> A_IWL<44605> A_IWL<44604> A_IWL<44603> A_IWL<44602> A_IWL<44601> A_IWL<44600> A_IWL<44599> A_IWL<44598> A_IWL<44597> A_IWL<44596> A_IWL<44595> A_IWL<44594> A_IWL<44593> A_IWL<44592> A_IWL<44591> A_IWL<44590> A_IWL<44589> A_IWL<44588> A_IWL<44587> A_IWL<44586> A_IWL<44585> A_IWL<44584> A_IWL<44583> A_IWL<44582> A_IWL<44581> A_IWL<44580> A_IWL<44579> A_IWL<44578> A_IWL<44577> A_IWL<44576> A_IWL<44575> A_IWL<44574> A_IWL<44573> A_IWL<44572> A_IWL<44571> A_IWL<44570> A_IWL<44569> A_IWL<44568> A_IWL<44567> A_IWL<44566> A_IWL<44565> A_IWL<44564> A_IWL<44563> A_IWL<44562> A_IWL<44561> A_IWL<44560> A_IWL<44559> A_IWL<44558> A_IWL<44557> A_IWL<44556> A_IWL<44555> A_IWL<44554> A_IWL<44553> A_IWL<44552> A_IWL<44551> A_IWL<44550> A_IWL<44549> A_IWL<44548> A_IWL<44547> A_IWL<44546> A_IWL<44545> A_IWL<44544> A_IWL<45567> A_IWL<45566> A_IWL<45565> A_IWL<45564> A_IWL<45563> A_IWL<45562> A_IWL<45561> A_IWL<45560> A_IWL<45559> A_IWL<45558> A_IWL<45557> A_IWL<45556> A_IWL<45555> A_IWL<45554> A_IWL<45553> A_IWL<45552> A_IWL<45551> A_IWL<45550> A_IWL<45549> A_IWL<45548> A_IWL<45547> A_IWL<45546> A_IWL<45545> A_IWL<45544> A_IWL<45543> A_IWL<45542> A_IWL<45541> A_IWL<45540> A_IWL<45539> A_IWL<45538> A_IWL<45537> A_IWL<45536> A_IWL<45535> A_IWL<45534> A_IWL<45533> A_IWL<45532> A_IWL<45531> A_IWL<45530> A_IWL<45529> A_IWL<45528> A_IWL<45527> A_IWL<45526> A_IWL<45525> A_IWL<45524> A_IWL<45523> A_IWL<45522> A_IWL<45521> A_IWL<45520> A_IWL<45519> A_IWL<45518> A_IWL<45517> A_IWL<45516> A_IWL<45515> A_IWL<45514> A_IWL<45513> A_IWL<45512> A_IWL<45511> A_IWL<45510> A_IWL<45509> A_IWL<45508> A_IWL<45507> A_IWL<45506> A_IWL<45505> A_IWL<45504> A_IWL<45503> A_IWL<45502> A_IWL<45501> A_IWL<45500> A_IWL<45499> A_IWL<45498> A_IWL<45497> A_IWL<45496> A_IWL<45495> A_IWL<45494> A_IWL<45493> A_IWL<45492> A_IWL<45491> A_IWL<45490> A_IWL<45489> A_IWL<45488> A_IWL<45487> A_IWL<45486> A_IWL<45485> A_IWL<45484> A_IWL<45483> A_IWL<45482> A_IWL<45481> A_IWL<45480> A_IWL<45479> A_IWL<45478> A_IWL<45477> A_IWL<45476> A_IWL<45475> A_IWL<45474> A_IWL<45473> A_IWL<45472> A_IWL<45471> A_IWL<45470> A_IWL<45469> A_IWL<45468> A_IWL<45467> A_IWL<45466> A_IWL<45465> A_IWL<45464> A_IWL<45463> A_IWL<45462> A_IWL<45461> A_IWL<45460> A_IWL<45459> A_IWL<45458> A_IWL<45457> A_IWL<45456> A_IWL<45455> A_IWL<45454> A_IWL<45453> A_IWL<45452> A_IWL<45451> A_IWL<45450> A_IWL<45449> A_IWL<45448> A_IWL<45447> A_IWL<45446> A_IWL<45445> A_IWL<45444> A_IWL<45443> A_IWL<45442> A_IWL<45441> A_IWL<45440> A_IWL<45439> A_IWL<45438> A_IWL<45437> A_IWL<45436> A_IWL<45435> A_IWL<45434> A_IWL<45433> A_IWL<45432> A_IWL<45431> A_IWL<45430> A_IWL<45429> A_IWL<45428> A_IWL<45427> A_IWL<45426> A_IWL<45425> A_IWL<45424> A_IWL<45423> A_IWL<45422> A_IWL<45421> A_IWL<45420> A_IWL<45419> A_IWL<45418> A_IWL<45417> A_IWL<45416> A_IWL<45415> A_IWL<45414> A_IWL<45413> A_IWL<45412> A_IWL<45411> A_IWL<45410> A_IWL<45409> A_IWL<45408> A_IWL<45407> A_IWL<45406> A_IWL<45405> A_IWL<45404> A_IWL<45403> A_IWL<45402> A_IWL<45401> A_IWL<45400> A_IWL<45399> A_IWL<45398> A_IWL<45397> A_IWL<45396> A_IWL<45395> A_IWL<45394> A_IWL<45393> A_IWL<45392> A_IWL<45391> A_IWL<45390> A_IWL<45389> A_IWL<45388> A_IWL<45387> A_IWL<45386> A_IWL<45385> A_IWL<45384> A_IWL<45383> A_IWL<45382> A_IWL<45381> A_IWL<45380> A_IWL<45379> A_IWL<45378> A_IWL<45377> A_IWL<45376> A_IWL<45375> A_IWL<45374> A_IWL<45373> A_IWL<45372> A_IWL<45371> A_IWL<45370> A_IWL<45369> A_IWL<45368> A_IWL<45367> A_IWL<45366> A_IWL<45365> A_IWL<45364> A_IWL<45363> A_IWL<45362> A_IWL<45361> A_IWL<45360> A_IWL<45359> A_IWL<45358> A_IWL<45357> A_IWL<45356> A_IWL<45355> A_IWL<45354> A_IWL<45353> A_IWL<45352> A_IWL<45351> A_IWL<45350> A_IWL<45349> A_IWL<45348> A_IWL<45347> A_IWL<45346> A_IWL<45345> A_IWL<45344> A_IWL<45343> A_IWL<45342> A_IWL<45341> A_IWL<45340> A_IWL<45339> A_IWL<45338> A_IWL<45337> A_IWL<45336> A_IWL<45335> A_IWL<45334> A_IWL<45333> A_IWL<45332> A_IWL<45331> A_IWL<45330> A_IWL<45329> A_IWL<45328> A_IWL<45327> A_IWL<45326> A_IWL<45325> A_IWL<45324> A_IWL<45323> A_IWL<45322> A_IWL<45321> A_IWL<45320> A_IWL<45319> A_IWL<45318> A_IWL<45317> A_IWL<45316> A_IWL<45315> A_IWL<45314> A_IWL<45313> A_IWL<45312> A_IWL<45311> A_IWL<45310> A_IWL<45309> A_IWL<45308> A_IWL<45307> A_IWL<45306> A_IWL<45305> A_IWL<45304> A_IWL<45303> A_IWL<45302> A_IWL<45301> A_IWL<45300> A_IWL<45299> A_IWL<45298> A_IWL<45297> A_IWL<45296> A_IWL<45295> A_IWL<45294> A_IWL<45293> A_IWL<45292> A_IWL<45291> A_IWL<45290> A_IWL<45289> A_IWL<45288> A_IWL<45287> A_IWL<45286> A_IWL<45285> A_IWL<45284> A_IWL<45283> A_IWL<45282> A_IWL<45281> A_IWL<45280> A_IWL<45279> A_IWL<45278> A_IWL<45277> A_IWL<45276> A_IWL<45275> A_IWL<45274> A_IWL<45273> A_IWL<45272> A_IWL<45271> A_IWL<45270> A_IWL<45269> A_IWL<45268> A_IWL<45267> A_IWL<45266> A_IWL<45265> A_IWL<45264> A_IWL<45263> A_IWL<45262> A_IWL<45261> A_IWL<45260> A_IWL<45259> A_IWL<45258> A_IWL<45257> A_IWL<45256> A_IWL<45255> A_IWL<45254> A_IWL<45253> A_IWL<45252> A_IWL<45251> A_IWL<45250> A_IWL<45249> A_IWL<45248> A_IWL<45247> A_IWL<45246> A_IWL<45245> A_IWL<45244> A_IWL<45243> A_IWL<45242> A_IWL<45241> A_IWL<45240> A_IWL<45239> A_IWL<45238> A_IWL<45237> A_IWL<45236> A_IWL<45235> A_IWL<45234> A_IWL<45233> A_IWL<45232> A_IWL<45231> A_IWL<45230> A_IWL<45229> A_IWL<45228> A_IWL<45227> A_IWL<45226> A_IWL<45225> A_IWL<45224> A_IWL<45223> A_IWL<45222> A_IWL<45221> A_IWL<45220> A_IWL<45219> A_IWL<45218> A_IWL<45217> A_IWL<45216> A_IWL<45215> A_IWL<45214> A_IWL<45213> A_IWL<45212> A_IWL<45211> A_IWL<45210> A_IWL<45209> A_IWL<45208> A_IWL<45207> A_IWL<45206> A_IWL<45205> A_IWL<45204> A_IWL<45203> A_IWL<45202> A_IWL<45201> A_IWL<45200> A_IWL<45199> A_IWL<45198> A_IWL<45197> A_IWL<45196> A_IWL<45195> A_IWL<45194> A_IWL<45193> A_IWL<45192> A_IWL<45191> A_IWL<45190> A_IWL<45189> A_IWL<45188> A_IWL<45187> A_IWL<45186> A_IWL<45185> A_IWL<45184> A_IWL<45183> A_IWL<45182> A_IWL<45181> A_IWL<45180> A_IWL<45179> A_IWL<45178> A_IWL<45177> A_IWL<45176> A_IWL<45175> A_IWL<45174> A_IWL<45173> A_IWL<45172> A_IWL<45171> A_IWL<45170> A_IWL<45169> A_IWL<45168> A_IWL<45167> A_IWL<45166> A_IWL<45165> A_IWL<45164> A_IWL<45163> A_IWL<45162> A_IWL<45161> A_IWL<45160> A_IWL<45159> A_IWL<45158> A_IWL<45157> A_IWL<45156> A_IWL<45155> A_IWL<45154> A_IWL<45153> A_IWL<45152> A_IWL<45151> A_IWL<45150> A_IWL<45149> A_IWL<45148> A_IWL<45147> A_IWL<45146> A_IWL<45145> A_IWL<45144> A_IWL<45143> A_IWL<45142> A_IWL<45141> A_IWL<45140> A_IWL<45139> A_IWL<45138> A_IWL<45137> A_IWL<45136> A_IWL<45135> A_IWL<45134> A_IWL<45133> A_IWL<45132> A_IWL<45131> A_IWL<45130> A_IWL<45129> A_IWL<45128> A_IWL<45127> A_IWL<45126> A_IWL<45125> A_IWL<45124> A_IWL<45123> A_IWL<45122> A_IWL<45121> A_IWL<45120> A_IWL<45119> A_IWL<45118> A_IWL<45117> A_IWL<45116> A_IWL<45115> A_IWL<45114> A_IWL<45113> A_IWL<45112> A_IWL<45111> A_IWL<45110> A_IWL<45109> A_IWL<45108> A_IWL<45107> A_IWL<45106> A_IWL<45105> A_IWL<45104> A_IWL<45103> A_IWL<45102> A_IWL<45101> A_IWL<45100> A_IWL<45099> A_IWL<45098> A_IWL<45097> A_IWL<45096> A_IWL<45095> A_IWL<45094> A_IWL<45093> A_IWL<45092> A_IWL<45091> A_IWL<45090> A_IWL<45089> A_IWL<45088> A_IWL<45087> A_IWL<45086> A_IWL<45085> A_IWL<45084> A_IWL<45083> A_IWL<45082> A_IWL<45081> A_IWL<45080> A_IWL<45079> A_IWL<45078> A_IWL<45077> A_IWL<45076> A_IWL<45075> A_IWL<45074> A_IWL<45073> A_IWL<45072> A_IWL<45071> A_IWL<45070> A_IWL<45069> A_IWL<45068> A_IWL<45067> A_IWL<45066> A_IWL<45065> A_IWL<45064> A_IWL<45063> A_IWL<45062> A_IWL<45061> A_IWL<45060> A_IWL<45059> A_IWL<45058> A_IWL<45057> A_IWL<45056> VDD_CORE VSS / RM_IHPSG13_8192x32_c4_1P_COLUMN_pcell_0 +XCOL<87> A_BLC<175> A_BLC<174> A_BLC_TOP<175> A_BLC_TOP<174> A_BLT<175> A_BLT<174> A_BLT_TOP<175> A_BLT_TOP<174> A_IWL<44543> A_IWL<44542> A_IWL<44541> A_IWL<44540> A_IWL<44539> A_IWL<44538> A_IWL<44537> A_IWL<44536> A_IWL<44535> A_IWL<44534> A_IWL<44533> A_IWL<44532> A_IWL<44531> A_IWL<44530> A_IWL<44529> A_IWL<44528> A_IWL<44527> A_IWL<44526> A_IWL<44525> A_IWL<44524> A_IWL<44523> A_IWL<44522> A_IWL<44521> A_IWL<44520> A_IWL<44519> A_IWL<44518> A_IWL<44517> A_IWL<44516> A_IWL<44515> A_IWL<44514> A_IWL<44513> A_IWL<44512> A_IWL<44511> A_IWL<44510> A_IWL<44509> A_IWL<44508> A_IWL<44507> A_IWL<44506> A_IWL<44505> A_IWL<44504> A_IWL<44503> A_IWL<44502> A_IWL<44501> A_IWL<44500> A_IWL<44499> A_IWL<44498> A_IWL<44497> A_IWL<44496> A_IWL<44495> A_IWL<44494> A_IWL<44493> A_IWL<44492> A_IWL<44491> A_IWL<44490> A_IWL<44489> A_IWL<44488> A_IWL<44487> A_IWL<44486> A_IWL<44485> A_IWL<44484> A_IWL<44483> A_IWL<44482> A_IWL<44481> A_IWL<44480> A_IWL<44479> A_IWL<44478> A_IWL<44477> A_IWL<44476> A_IWL<44475> A_IWL<44474> A_IWL<44473> A_IWL<44472> A_IWL<44471> A_IWL<44470> A_IWL<44469> A_IWL<44468> A_IWL<44467> A_IWL<44466> A_IWL<44465> A_IWL<44464> A_IWL<44463> A_IWL<44462> A_IWL<44461> A_IWL<44460> A_IWL<44459> A_IWL<44458> A_IWL<44457> A_IWL<44456> A_IWL<44455> A_IWL<44454> A_IWL<44453> A_IWL<44452> A_IWL<44451> A_IWL<44450> A_IWL<44449> A_IWL<44448> A_IWL<44447> A_IWL<44446> A_IWL<44445> A_IWL<44444> A_IWL<44443> A_IWL<44442> A_IWL<44441> A_IWL<44440> A_IWL<44439> A_IWL<44438> A_IWL<44437> A_IWL<44436> A_IWL<44435> A_IWL<44434> A_IWL<44433> A_IWL<44432> A_IWL<44431> A_IWL<44430> A_IWL<44429> A_IWL<44428> A_IWL<44427> A_IWL<44426> A_IWL<44425> A_IWL<44424> A_IWL<44423> A_IWL<44422> A_IWL<44421> A_IWL<44420> A_IWL<44419> A_IWL<44418> A_IWL<44417> A_IWL<44416> A_IWL<44415> A_IWL<44414> A_IWL<44413> A_IWL<44412> A_IWL<44411> A_IWL<44410> A_IWL<44409> A_IWL<44408> A_IWL<44407> A_IWL<44406> A_IWL<44405> A_IWL<44404> A_IWL<44403> A_IWL<44402> A_IWL<44401> A_IWL<44400> A_IWL<44399> A_IWL<44398> A_IWL<44397> A_IWL<44396> A_IWL<44395> A_IWL<44394> A_IWL<44393> A_IWL<44392> A_IWL<44391> A_IWL<44390> A_IWL<44389> A_IWL<44388> A_IWL<44387> A_IWL<44386> A_IWL<44385> A_IWL<44384> A_IWL<44383> A_IWL<44382> A_IWL<44381> A_IWL<44380> A_IWL<44379> A_IWL<44378> A_IWL<44377> A_IWL<44376> A_IWL<44375> A_IWL<44374> A_IWL<44373> A_IWL<44372> A_IWL<44371> A_IWL<44370> A_IWL<44369> A_IWL<44368> A_IWL<44367> A_IWL<44366> A_IWL<44365> A_IWL<44364> A_IWL<44363> A_IWL<44362> A_IWL<44361> A_IWL<44360> A_IWL<44359> A_IWL<44358> A_IWL<44357> A_IWL<44356> A_IWL<44355> A_IWL<44354> A_IWL<44353> A_IWL<44352> A_IWL<44351> A_IWL<44350> A_IWL<44349> A_IWL<44348> A_IWL<44347> A_IWL<44346> A_IWL<44345> A_IWL<44344> A_IWL<44343> A_IWL<44342> A_IWL<44341> A_IWL<44340> A_IWL<44339> A_IWL<44338> A_IWL<44337> A_IWL<44336> A_IWL<44335> A_IWL<44334> A_IWL<44333> A_IWL<44332> A_IWL<44331> A_IWL<44330> A_IWL<44329> A_IWL<44328> A_IWL<44327> A_IWL<44326> A_IWL<44325> A_IWL<44324> A_IWL<44323> A_IWL<44322> A_IWL<44321> A_IWL<44320> A_IWL<44319> A_IWL<44318> A_IWL<44317> A_IWL<44316> A_IWL<44315> A_IWL<44314> A_IWL<44313> A_IWL<44312> A_IWL<44311> A_IWL<44310> A_IWL<44309> A_IWL<44308> A_IWL<44307> A_IWL<44306> A_IWL<44305> A_IWL<44304> A_IWL<44303> A_IWL<44302> A_IWL<44301> A_IWL<44300> A_IWL<44299> A_IWL<44298> A_IWL<44297> A_IWL<44296> A_IWL<44295> A_IWL<44294> A_IWL<44293> A_IWL<44292> A_IWL<44291> A_IWL<44290> A_IWL<44289> A_IWL<44288> A_IWL<44287> A_IWL<44286> A_IWL<44285> A_IWL<44284> A_IWL<44283> A_IWL<44282> A_IWL<44281> A_IWL<44280> A_IWL<44279> A_IWL<44278> A_IWL<44277> A_IWL<44276> A_IWL<44275> A_IWL<44274> A_IWL<44273> A_IWL<44272> A_IWL<44271> A_IWL<44270> A_IWL<44269> A_IWL<44268> A_IWL<44267> A_IWL<44266> A_IWL<44265> A_IWL<44264> A_IWL<44263> A_IWL<44262> A_IWL<44261> A_IWL<44260> A_IWL<44259> A_IWL<44258> A_IWL<44257> A_IWL<44256> A_IWL<44255> A_IWL<44254> A_IWL<44253> A_IWL<44252> A_IWL<44251> A_IWL<44250> A_IWL<44249> A_IWL<44248> A_IWL<44247> A_IWL<44246> A_IWL<44245> A_IWL<44244> A_IWL<44243> A_IWL<44242> A_IWL<44241> A_IWL<44240> A_IWL<44239> A_IWL<44238> A_IWL<44237> A_IWL<44236> A_IWL<44235> A_IWL<44234> A_IWL<44233> A_IWL<44232> A_IWL<44231> A_IWL<44230> A_IWL<44229> A_IWL<44228> A_IWL<44227> A_IWL<44226> A_IWL<44225> A_IWL<44224> A_IWL<44223> A_IWL<44222> A_IWL<44221> A_IWL<44220> A_IWL<44219> A_IWL<44218> A_IWL<44217> A_IWL<44216> A_IWL<44215> A_IWL<44214> A_IWL<44213> A_IWL<44212> A_IWL<44211> A_IWL<44210> A_IWL<44209> A_IWL<44208> A_IWL<44207> A_IWL<44206> A_IWL<44205> A_IWL<44204> A_IWL<44203> A_IWL<44202> A_IWL<44201> A_IWL<44200> A_IWL<44199> A_IWL<44198> A_IWL<44197> A_IWL<44196> A_IWL<44195> A_IWL<44194> A_IWL<44193> A_IWL<44192> A_IWL<44191> A_IWL<44190> A_IWL<44189> A_IWL<44188> A_IWL<44187> A_IWL<44186> A_IWL<44185> A_IWL<44184> A_IWL<44183> A_IWL<44182> A_IWL<44181> A_IWL<44180> A_IWL<44179> A_IWL<44178> A_IWL<44177> A_IWL<44176> A_IWL<44175> A_IWL<44174> A_IWL<44173> A_IWL<44172> A_IWL<44171> A_IWL<44170> A_IWL<44169> A_IWL<44168> A_IWL<44167> A_IWL<44166> A_IWL<44165> A_IWL<44164> A_IWL<44163> A_IWL<44162> A_IWL<44161> A_IWL<44160> A_IWL<44159> A_IWL<44158> A_IWL<44157> A_IWL<44156> A_IWL<44155> A_IWL<44154> A_IWL<44153> A_IWL<44152> A_IWL<44151> A_IWL<44150> A_IWL<44149> A_IWL<44148> A_IWL<44147> A_IWL<44146> A_IWL<44145> A_IWL<44144> A_IWL<44143> A_IWL<44142> A_IWL<44141> A_IWL<44140> A_IWL<44139> A_IWL<44138> A_IWL<44137> A_IWL<44136> A_IWL<44135> A_IWL<44134> A_IWL<44133> A_IWL<44132> A_IWL<44131> A_IWL<44130> A_IWL<44129> A_IWL<44128> A_IWL<44127> A_IWL<44126> A_IWL<44125> A_IWL<44124> A_IWL<44123> A_IWL<44122> A_IWL<44121> A_IWL<44120> A_IWL<44119> A_IWL<44118> A_IWL<44117> A_IWL<44116> A_IWL<44115> A_IWL<44114> A_IWL<44113> A_IWL<44112> A_IWL<44111> A_IWL<44110> A_IWL<44109> A_IWL<44108> A_IWL<44107> A_IWL<44106> A_IWL<44105> A_IWL<44104> A_IWL<44103> A_IWL<44102> A_IWL<44101> A_IWL<44100> A_IWL<44099> A_IWL<44098> A_IWL<44097> A_IWL<44096> A_IWL<44095> A_IWL<44094> A_IWL<44093> A_IWL<44092> A_IWL<44091> A_IWL<44090> A_IWL<44089> A_IWL<44088> A_IWL<44087> A_IWL<44086> A_IWL<44085> A_IWL<44084> A_IWL<44083> A_IWL<44082> A_IWL<44081> A_IWL<44080> A_IWL<44079> A_IWL<44078> A_IWL<44077> A_IWL<44076> A_IWL<44075> A_IWL<44074> A_IWL<44073> A_IWL<44072> A_IWL<44071> A_IWL<44070> A_IWL<44069> A_IWL<44068> A_IWL<44067> A_IWL<44066> A_IWL<44065> A_IWL<44064> A_IWL<44063> A_IWL<44062> A_IWL<44061> A_IWL<44060> A_IWL<44059> A_IWL<44058> A_IWL<44057> A_IWL<44056> A_IWL<44055> A_IWL<44054> A_IWL<44053> A_IWL<44052> A_IWL<44051> A_IWL<44050> A_IWL<44049> A_IWL<44048> A_IWL<44047> A_IWL<44046> A_IWL<44045> A_IWL<44044> A_IWL<44043> A_IWL<44042> A_IWL<44041> A_IWL<44040> A_IWL<44039> A_IWL<44038> A_IWL<44037> A_IWL<44036> A_IWL<44035> A_IWL<44034> A_IWL<44033> A_IWL<44032> A_IWL<45055> A_IWL<45054> A_IWL<45053> A_IWL<45052> A_IWL<45051> A_IWL<45050> A_IWL<45049> A_IWL<45048> A_IWL<45047> A_IWL<45046> A_IWL<45045> A_IWL<45044> A_IWL<45043> A_IWL<45042> A_IWL<45041> A_IWL<45040> A_IWL<45039> A_IWL<45038> A_IWL<45037> A_IWL<45036> A_IWL<45035> A_IWL<45034> A_IWL<45033> A_IWL<45032> A_IWL<45031> A_IWL<45030> A_IWL<45029> A_IWL<45028> A_IWL<45027> A_IWL<45026> A_IWL<45025> A_IWL<45024> A_IWL<45023> A_IWL<45022> A_IWL<45021> A_IWL<45020> A_IWL<45019> A_IWL<45018> A_IWL<45017> A_IWL<45016> A_IWL<45015> A_IWL<45014> A_IWL<45013> A_IWL<45012> A_IWL<45011> A_IWL<45010> A_IWL<45009> A_IWL<45008> A_IWL<45007> A_IWL<45006> A_IWL<45005> A_IWL<45004> A_IWL<45003> A_IWL<45002> A_IWL<45001> A_IWL<45000> A_IWL<44999> A_IWL<44998> A_IWL<44997> A_IWL<44996> A_IWL<44995> A_IWL<44994> A_IWL<44993> A_IWL<44992> A_IWL<44991> A_IWL<44990> A_IWL<44989> A_IWL<44988> A_IWL<44987> A_IWL<44986> A_IWL<44985> A_IWL<44984> A_IWL<44983> A_IWL<44982> A_IWL<44981> A_IWL<44980> A_IWL<44979> A_IWL<44978> A_IWL<44977> A_IWL<44976> A_IWL<44975> A_IWL<44974> A_IWL<44973> A_IWL<44972> A_IWL<44971> A_IWL<44970> A_IWL<44969> A_IWL<44968> A_IWL<44967> A_IWL<44966> A_IWL<44965> A_IWL<44964> A_IWL<44963> A_IWL<44962> A_IWL<44961> A_IWL<44960> A_IWL<44959> A_IWL<44958> A_IWL<44957> A_IWL<44956> A_IWL<44955> A_IWL<44954> A_IWL<44953> A_IWL<44952> A_IWL<44951> A_IWL<44950> A_IWL<44949> A_IWL<44948> A_IWL<44947> A_IWL<44946> A_IWL<44945> A_IWL<44944> A_IWL<44943> A_IWL<44942> A_IWL<44941> A_IWL<44940> A_IWL<44939> A_IWL<44938> A_IWL<44937> A_IWL<44936> A_IWL<44935> A_IWL<44934> A_IWL<44933> A_IWL<44932> A_IWL<44931> A_IWL<44930> A_IWL<44929> A_IWL<44928> A_IWL<44927> A_IWL<44926> A_IWL<44925> A_IWL<44924> A_IWL<44923> A_IWL<44922> A_IWL<44921> A_IWL<44920> A_IWL<44919> A_IWL<44918> A_IWL<44917> A_IWL<44916> A_IWL<44915> A_IWL<44914> A_IWL<44913> A_IWL<44912> A_IWL<44911> A_IWL<44910> A_IWL<44909> A_IWL<44908> A_IWL<44907> A_IWL<44906> A_IWL<44905> A_IWL<44904> A_IWL<44903> A_IWL<44902> A_IWL<44901> A_IWL<44900> A_IWL<44899> A_IWL<44898> A_IWL<44897> A_IWL<44896> A_IWL<44895> A_IWL<44894> A_IWL<44893> A_IWL<44892> A_IWL<44891> A_IWL<44890> A_IWL<44889> A_IWL<44888> A_IWL<44887> A_IWL<44886> A_IWL<44885> A_IWL<44884> A_IWL<44883> A_IWL<44882> A_IWL<44881> A_IWL<44880> A_IWL<44879> A_IWL<44878> A_IWL<44877> A_IWL<44876> A_IWL<44875> A_IWL<44874> A_IWL<44873> A_IWL<44872> A_IWL<44871> A_IWL<44870> A_IWL<44869> A_IWL<44868> A_IWL<44867> A_IWL<44866> A_IWL<44865> A_IWL<44864> A_IWL<44863> A_IWL<44862> A_IWL<44861> A_IWL<44860> A_IWL<44859> A_IWL<44858> A_IWL<44857> A_IWL<44856> A_IWL<44855> A_IWL<44854> A_IWL<44853> A_IWL<44852> A_IWL<44851> A_IWL<44850> A_IWL<44849> A_IWL<44848> A_IWL<44847> A_IWL<44846> A_IWL<44845> A_IWL<44844> A_IWL<44843> A_IWL<44842> A_IWL<44841> A_IWL<44840> A_IWL<44839> A_IWL<44838> A_IWL<44837> A_IWL<44836> A_IWL<44835> A_IWL<44834> A_IWL<44833> A_IWL<44832> A_IWL<44831> A_IWL<44830> A_IWL<44829> A_IWL<44828> A_IWL<44827> A_IWL<44826> A_IWL<44825> A_IWL<44824> A_IWL<44823> A_IWL<44822> A_IWL<44821> A_IWL<44820> A_IWL<44819> A_IWL<44818> A_IWL<44817> A_IWL<44816> A_IWL<44815> A_IWL<44814> A_IWL<44813> A_IWL<44812> A_IWL<44811> A_IWL<44810> A_IWL<44809> A_IWL<44808> A_IWL<44807> A_IWL<44806> A_IWL<44805> A_IWL<44804> A_IWL<44803> A_IWL<44802> A_IWL<44801> A_IWL<44800> A_IWL<44799> A_IWL<44798> A_IWL<44797> A_IWL<44796> A_IWL<44795> A_IWL<44794> A_IWL<44793> A_IWL<44792> A_IWL<44791> A_IWL<44790> A_IWL<44789> A_IWL<44788> A_IWL<44787> A_IWL<44786> A_IWL<44785> A_IWL<44784> A_IWL<44783> A_IWL<44782> A_IWL<44781> A_IWL<44780> A_IWL<44779> A_IWL<44778> A_IWL<44777> A_IWL<44776> A_IWL<44775> A_IWL<44774> A_IWL<44773> A_IWL<44772> A_IWL<44771> A_IWL<44770> A_IWL<44769> A_IWL<44768> A_IWL<44767> A_IWL<44766> A_IWL<44765> A_IWL<44764> A_IWL<44763> A_IWL<44762> A_IWL<44761> A_IWL<44760> A_IWL<44759> A_IWL<44758> A_IWL<44757> A_IWL<44756> A_IWL<44755> A_IWL<44754> A_IWL<44753> A_IWL<44752> A_IWL<44751> A_IWL<44750> A_IWL<44749> A_IWL<44748> A_IWL<44747> A_IWL<44746> A_IWL<44745> A_IWL<44744> A_IWL<44743> A_IWL<44742> A_IWL<44741> A_IWL<44740> A_IWL<44739> A_IWL<44738> A_IWL<44737> A_IWL<44736> A_IWL<44735> A_IWL<44734> A_IWL<44733> A_IWL<44732> A_IWL<44731> A_IWL<44730> A_IWL<44729> A_IWL<44728> A_IWL<44727> A_IWL<44726> A_IWL<44725> A_IWL<44724> A_IWL<44723> A_IWL<44722> A_IWL<44721> A_IWL<44720> A_IWL<44719> A_IWL<44718> A_IWL<44717> A_IWL<44716> A_IWL<44715> A_IWL<44714> A_IWL<44713> A_IWL<44712> A_IWL<44711> A_IWL<44710> A_IWL<44709> A_IWL<44708> A_IWL<44707> A_IWL<44706> A_IWL<44705> A_IWL<44704> A_IWL<44703> A_IWL<44702> A_IWL<44701> A_IWL<44700> A_IWL<44699> A_IWL<44698> A_IWL<44697> A_IWL<44696> A_IWL<44695> A_IWL<44694> A_IWL<44693> A_IWL<44692> A_IWL<44691> A_IWL<44690> A_IWL<44689> A_IWL<44688> A_IWL<44687> A_IWL<44686> A_IWL<44685> A_IWL<44684> A_IWL<44683> A_IWL<44682> A_IWL<44681> A_IWL<44680> A_IWL<44679> A_IWL<44678> A_IWL<44677> A_IWL<44676> A_IWL<44675> A_IWL<44674> A_IWL<44673> A_IWL<44672> A_IWL<44671> A_IWL<44670> A_IWL<44669> A_IWL<44668> A_IWL<44667> A_IWL<44666> A_IWL<44665> A_IWL<44664> A_IWL<44663> A_IWL<44662> A_IWL<44661> A_IWL<44660> A_IWL<44659> A_IWL<44658> A_IWL<44657> A_IWL<44656> A_IWL<44655> A_IWL<44654> A_IWL<44653> A_IWL<44652> A_IWL<44651> A_IWL<44650> A_IWL<44649> A_IWL<44648> A_IWL<44647> A_IWL<44646> A_IWL<44645> A_IWL<44644> A_IWL<44643> A_IWL<44642> A_IWL<44641> A_IWL<44640> A_IWL<44639> A_IWL<44638> A_IWL<44637> A_IWL<44636> A_IWL<44635> A_IWL<44634> A_IWL<44633> A_IWL<44632> A_IWL<44631> A_IWL<44630> A_IWL<44629> A_IWL<44628> A_IWL<44627> A_IWL<44626> A_IWL<44625> A_IWL<44624> A_IWL<44623> A_IWL<44622> A_IWL<44621> A_IWL<44620> A_IWL<44619> A_IWL<44618> A_IWL<44617> A_IWL<44616> A_IWL<44615> A_IWL<44614> A_IWL<44613> A_IWL<44612> A_IWL<44611> A_IWL<44610> A_IWL<44609> A_IWL<44608> A_IWL<44607> A_IWL<44606> A_IWL<44605> A_IWL<44604> A_IWL<44603> A_IWL<44602> A_IWL<44601> A_IWL<44600> A_IWL<44599> A_IWL<44598> A_IWL<44597> A_IWL<44596> A_IWL<44595> A_IWL<44594> A_IWL<44593> A_IWL<44592> A_IWL<44591> A_IWL<44590> A_IWL<44589> A_IWL<44588> A_IWL<44587> A_IWL<44586> A_IWL<44585> A_IWL<44584> A_IWL<44583> A_IWL<44582> A_IWL<44581> A_IWL<44580> A_IWL<44579> A_IWL<44578> A_IWL<44577> A_IWL<44576> A_IWL<44575> A_IWL<44574> A_IWL<44573> A_IWL<44572> A_IWL<44571> A_IWL<44570> A_IWL<44569> A_IWL<44568> A_IWL<44567> A_IWL<44566> A_IWL<44565> A_IWL<44564> A_IWL<44563> A_IWL<44562> A_IWL<44561> A_IWL<44560> A_IWL<44559> A_IWL<44558> A_IWL<44557> A_IWL<44556> A_IWL<44555> A_IWL<44554> A_IWL<44553> A_IWL<44552> A_IWL<44551> A_IWL<44550> A_IWL<44549> A_IWL<44548> A_IWL<44547> A_IWL<44546> A_IWL<44545> A_IWL<44544> VDD_CORE VSS / RM_IHPSG13_8192x32_c4_1P_COLUMN_pcell_0 +XCOL<86> A_BLC<173> A_BLC<172> A_BLC_TOP<173> A_BLC_TOP<172> A_BLT<173> A_BLT<172> A_BLT_TOP<173> A_BLT_TOP<172> A_IWL<44031> A_IWL<44030> A_IWL<44029> A_IWL<44028> A_IWL<44027> A_IWL<44026> A_IWL<44025> A_IWL<44024> A_IWL<44023> A_IWL<44022> A_IWL<44021> A_IWL<44020> A_IWL<44019> A_IWL<44018> A_IWL<44017> A_IWL<44016> A_IWL<44015> A_IWL<44014> A_IWL<44013> A_IWL<44012> A_IWL<44011> A_IWL<44010> A_IWL<44009> A_IWL<44008> A_IWL<44007> A_IWL<44006> A_IWL<44005> A_IWL<44004> A_IWL<44003> A_IWL<44002> A_IWL<44001> A_IWL<44000> A_IWL<43999> A_IWL<43998> A_IWL<43997> A_IWL<43996> A_IWL<43995> A_IWL<43994> A_IWL<43993> A_IWL<43992> A_IWL<43991> A_IWL<43990> A_IWL<43989> A_IWL<43988> A_IWL<43987> A_IWL<43986> A_IWL<43985> A_IWL<43984> A_IWL<43983> A_IWL<43982> A_IWL<43981> A_IWL<43980> A_IWL<43979> A_IWL<43978> A_IWL<43977> A_IWL<43976> A_IWL<43975> A_IWL<43974> A_IWL<43973> A_IWL<43972> A_IWL<43971> A_IWL<43970> A_IWL<43969> A_IWL<43968> A_IWL<43967> A_IWL<43966> A_IWL<43965> A_IWL<43964> A_IWL<43963> A_IWL<43962> A_IWL<43961> A_IWL<43960> A_IWL<43959> A_IWL<43958> A_IWL<43957> A_IWL<43956> A_IWL<43955> A_IWL<43954> A_IWL<43953> A_IWL<43952> A_IWL<43951> A_IWL<43950> A_IWL<43949> A_IWL<43948> A_IWL<43947> A_IWL<43946> A_IWL<43945> A_IWL<43944> A_IWL<43943> A_IWL<43942> A_IWL<43941> A_IWL<43940> A_IWL<43939> A_IWL<43938> A_IWL<43937> A_IWL<43936> A_IWL<43935> A_IWL<43934> A_IWL<43933> A_IWL<43932> A_IWL<43931> A_IWL<43930> A_IWL<43929> A_IWL<43928> A_IWL<43927> A_IWL<43926> A_IWL<43925> A_IWL<43924> A_IWL<43923> A_IWL<43922> A_IWL<43921> A_IWL<43920> A_IWL<43919> A_IWL<43918> A_IWL<43917> A_IWL<43916> A_IWL<43915> A_IWL<43914> A_IWL<43913> A_IWL<43912> A_IWL<43911> A_IWL<43910> A_IWL<43909> A_IWL<43908> A_IWL<43907> A_IWL<43906> A_IWL<43905> A_IWL<43904> A_IWL<43903> A_IWL<43902> A_IWL<43901> A_IWL<43900> A_IWL<43899> A_IWL<43898> A_IWL<43897> A_IWL<43896> A_IWL<43895> A_IWL<43894> A_IWL<43893> A_IWL<43892> A_IWL<43891> A_IWL<43890> A_IWL<43889> A_IWL<43888> A_IWL<43887> A_IWL<43886> A_IWL<43885> A_IWL<43884> A_IWL<43883> A_IWL<43882> A_IWL<43881> A_IWL<43880> A_IWL<43879> A_IWL<43878> A_IWL<43877> A_IWL<43876> A_IWL<43875> A_IWL<43874> A_IWL<43873> A_IWL<43872> A_IWL<43871> A_IWL<43870> A_IWL<43869> A_IWL<43868> A_IWL<43867> A_IWL<43866> A_IWL<43865> A_IWL<43864> A_IWL<43863> A_IWL<43862> A_IWL<43861> A_IWL<43860> A_IWL<43859> A_IWL<43858> A_IWL<43857> A_IWL<43856> A_IWL<43855> A_IWL<43854> A_IWL<43853> A_IWL<43852> A_IWL<43851> A_IWL<43850> A_IWL<43849> A_IWL<43848> A_IWL<43847> A_IWL<43846> A_IWL<43845> A_IWL<43844> A_IWL<43843> A_IWL<43842> A_IWL<43841> A_IWL<43840> A_IWL<43839> A_IWL<43838> A_IWL<43837> A_IWL<43836> A_IWL<43835> A_IWL<43834> A_IWL<43833> A_IWL<43832> A_IWL<43831> A_IWL<43830> A_IWL<43829> A_IWL<43828> A_IWL<43827> A_IWL<43826> A_IWL<43825> A_IWL<43824> A_IWL<43823> A_IWL<43822> A_IWL<43821> A_IWL<43820> A_IWL<43819> A_IWL<43818> A_IWL<43817> A_IWL<43816> A_IWL<43815> A_IWL<43814> A_IWL<43813> A_IWL<43812> A_IWL<43811> A_IWL<43810> A_IWL<43809> A_IWL<43808> A_IWL<43807> A_IWL<43806> A_IWL<43805> A_IWL<43804> A_IWL<43803> A_IWL<43802> A_IWL<43801> A_IWL<43800> A_IWL<43799> A_IWL<43798> A_IWL<43797> A_IWL<43796> A_IWL<43795> A_IWL<43794> A_IWL<43793> A_IWL<43792> A_IWL<43791> A_IWL<43790> A_IWL<43789> A_IWL<43788> A_IWL<43787> A_IWL<43786> A_IWL<43785> A_IWL<43784> A_IWL<43783> A_IWL<43782> A_IWL<43781> A_IWL<43780> A_IWL<43779> A_IWL<43778> A_IWL<43777> A_IWL<43776> A_IWL<43775> A_IWL<43774> A_IWL<43773> A_IWL<43772> A_IWL<43771> A_IWL<43770> A_IWL<43769> A_IWL<43768> A_IWL<43767> A_IWL<43766> A_IWL<43765> A_IWL<43764> A_IWL<43763> A_IWL<43762> A_IWL<43761> A_IWL<43760> A_IWL<43759> A_IWL<43758> A_IWL<43757> A_IWL<43756> A_IWL<43755> A_IWL<43754> A_IWL<43753> A_IWL<43752> A_IWL<43751> A_IWL<43750> A_IWL<43749> A_IWL<43748> A_IWL<43747> A_IWL<43746> A_IWL<43745> A_IWL<43744> A_IWL<43743> A_IWL<43742> A_IWL<43741> A_IWL<43740> A_IWL<43739> A_IWL<43738> A_IWL<43737> A_IWL<43736> A_IWL<43735> A_IWL<43734> A_IWL<43733> A_IWL<43732> A_IWL<43731> A_IWL<43730> A_IWL<43729> A_IWL<43728> A_IWL<43727> A_IWL<43726> A_IWL<43725> A_IWL<43724> A_IWL<43723> A_IWL<43722> A_IWL<43721> A_IWL<43720> A_IWL<43719> A_IWL<43718> A_IWL<43717> A_IWL<43716> A_IWL<43715> A_IWL<43714> A_IWL<43713> A_IWL<43712> A_IWL<43711> A_IWL<43710> A_IWL<43709> A_IWL<43708> A_IWL<43707> A_IWL<43706> A_IWL<43705> A_IWL<43704> A_IWL<43703> A_IWL<43702> A_IWL<43701> A_IWL<43700> A_IWL<43699> A_IWL<43698> A_IWL<43697> A_IWL<43696> A_IWL<43695> A_IWL<43694> A_IWL<43693> A_IWL<43692> A_IWL<43691> A_IWL<43690> A_IWL<43689> A_IWL<43688> A_IWL<43687> A_IWL<43686> A_IWL<43685> A_IWL<43684> A_IWL<43683> A_IWL<43682> A_IWL<43681> A_IWL<43680> A_IWL<43679> A_IWL<43678> A_IWL<43677> A_IWL<43676> A_IWL<43675> A_IWL<43674> A_IWL<43673> A_IWL<43672> A_IWL<43671> A_IWL<43670> A_IWL<43669> A_IWL<43668> A_IWL<43667> A_IWL<43666> A_IWL<43665> A_IWL<43664> A_IWL<43663> A_IWL<43662> A_IWL<43661> A_IWL<43660> A_IWL<43659> A_IWL<43658> A_IWL<43657> A_IWL<43656> A_IWL<43655> A_IWL<43654> A_IWL<43653> A_IWL<43652> A_IWL<43651> A_IWL<43650> A_IWL<43649> A_IWL<43648> A_IWL<43647> A_IWL<43646> A_IWL<43645> A_IWL<43644> A_IWL<43643> A_IWL<43642> A_IWL<43641> A_IWL<43640> A_IWL<43639> A_IWL<43638> A_IWL<43637> A_IWL<43636> A_IWL<43635> A_IWL<43634> A_IWL<43633> A_IWL<43632> A_IWL<43631> A_IWL<43630> A_IWL<43629> A_IWL<43628> A_IWL<43627> A_IWL<43626> A_IWL<43625> A_IWL<43624> A_IWL<43623> A_IWL<43622> A_IWL<43621> A_IWL<43620> A_IWL<43619> A_IWL<43618> A_IWL<43617> A_IWL<43616> A_IWL<43615> A_IWL<43614> A_IWL<43613> A_IWL<43612> A_IWL<43611> A_IWL<43610> A_IWL<43609> A_IWL<43608> A_IWL<43607> A_IWL<43606> A_IWL<43605> A_IWL<43604> A_IWL<43603> A_IWL<43602> A_IWL<43601> A_IWL<43600> A_IWL<43599> A_IWL<43598> A_IWL<43597> A_IWL<43596> A_IWL<43595> A_IWL<43594> A_IWL<43593> A_IWL<43592> A_IWL<43591> A_IWL<43590> A_IWL<43589> A_IWL<43588> A_IWL<43587> A_IWL<43586> A_IWL<43585> A_IWL<43584> A_IWL<43583> A_IWL<43582> A_IWL<43581> A_IWL<43580> A_IWL<43579> A_IWL<43578> A_IWL<43577> A_IWL<43576> A_IWL<43575> A_IWL<43574> A_IWL<43573> A_IWL<43572> A_IWL<43571> A_IWL<43570> A_IWL<43569> A_IWL<43568> A_IWL<43567> A_IWL<43566> A_IWL<43565> A_IWL<43564> A_IWL<43563> A_IWL<43562> A_IWL<43561> A_IWL<43560> A_IWL<43559> A_IWL<43558> A_IWL<43557> A_IWL<43556> A_IWL<43555> A_IWL<43554> A_IWL<43553> A_IWL<43552> A_IWL<43551> A_IWL<43550> A_IWL<43549> A_IWL<43548> A_IWL<43547> A_IWL<43546> A_IWL<43545> A_IWL<43544> A_IWL<43543> A_IWL<43542> A_IWL<43541> A_IWL<43540> A_IWL<43539> A_IWL<43538> A_IWL<43537> A_IWL<43536> A_IWL<43535> A_IWL<43534> A_IWL<43533> A_IWL<43532> A_IWL<43531> A_IWL<43530> A_IWL<43529> A_IWL<43528> A_IWL<43527> A_IWL<43526> A_IWL<43525> A_IWL<43524> A_IWL<43523> A_IWL<43522> A_IWL<43521> A_IWL<43520> A_IWL<44543> A_IWL<44542> A_IWL<44541> A_IWL<44540> A_IWL<44539> A_IWL<44538> A_IWL<44537> A_IWL<44536> A_IWL<44535> A_IWL<44534> A_IWL<44533> A_IWL<44532> A_IWL<44531> A_IWL<44530> A_IWL<44529> A_IWL<44528> A_IWL<44527> A_IWL<44526> A_IWL<44525> A_IWL<44524> A_IWL<44523> A_IWL<44522> A_IWL<44521> A_IWL<44520> A_IWL<44519> A_IWL<44518> A_IWL<44517> A_IWL<44516> A_IWL<44515> A_IWL<44514> A_IWL<44513> A_IWL<44512> A_IWL<44511> A_IWL<44510> A_IWL<44509> A_IWL<44508> A_IWL<44507> A_IWL<44506> A_IWL<44505> A_IWL<44504> A_IWL<44503> A_IWL<44502> A_IWL<44501> A_IWL<44500> A_IWL<44499> A_IWL<44498> A_IWL<44497> A_IWL<44496> A_IWL<44495> A_IWL<44494> A_IWL<44493> A_IWL<44492> A_IWL<44491> A_IWL<44490> A_IWL<44489> A_IWL<44488> A_IWL<44487> A_IWL<44486> A_IWL<44485> A_IWL<44484> A_IWL<44483> A_IWL<44482> A_IWL<44481> A_IWL<44480> A_IWL<44479> A_IWL<44478> A_IWL<44477> A_IWL<44476> A_IWL<44475> A_IWL<44474> A_IWL<44473> A_IWL<44472> A_IWL<44471> A_IWL<44470> A_IWL<44469> A_IWL<44468> A_IWL<44467> A_IWL<44466> A_IWL<44465> A_IWL<44464> A_IWL<44463> A_IWL<44462> A_IWL<44461> A_IWL<44460> A_IWL<44459> A_IWL<44458> A_IWL<44457> A_IWL<44456> A_IWL<44455> A_IWL<44454> A_IWL<44453> A_IWL<44452> A_IWL<44451> A_IWL<44450> A_IWL<44449> A_IWL<44448> A_IWL<44447> A_IWL<44446> A_IWL<44445> A_IWL<44444> A_IWL<44443> A_IWL<44442> A_IWL<44441> A_IWL<44440> A_IWL<44439> A_IWL<44438> A_IWL<44437> A_IWL<44436> A_IWL<44435> A_IWL<44434> A_IWL<44433> A_IWL<44432> A_IWL<44431> A_IWL<44430> A_IWL<44429> A_IWL<44428> A_IWL<44427> A_IWL<44426> A_IWL<44425> A_IWL<44424> A_IWL<44423> A_IWL<44422> A_IWL<44421> A_IWL<44420> A_IWL<44419> A_IWL<44418> A_IWL<44417> A_IWL<44416> A_IWL<44415> A_IWL<44414> A_IWL<44413> A_IWL<44412> A_IWL<44411> A_IWL<44410> A_IWL<44409> A_IWL<44408> A_IWL<44407> A_IWL<44406> A_IWL<44405> A_IWL<44404> A_IWL<44403> A_IWL<44402> A_IWL<44401> A_IWL<44400> A_IWL<44399> A_IWL<44398> A_IWL<44397> A_IWL<44396> A_IWL<44395> A_IWL<44394> A_IWL<44393> A_IWL<44392> A_IWL<44391> A_IWL<44390> A_IWL<44389> A_IWL<44388> A_IWL<44387> A_IWL<44386> A_IWL<44385> A_IWL<44384> A_IWL<44383> A_IWL<44382> A_IWL<44381> A_IWL<44380> A_IWL<44379> A_IWL<44378> A_IWL<44377> A_IWL<44376> A_IWL<44375> A_IWL<44374> A_IWL<44373> A_IWL<44372> A_IWL<44371> A_IWL<44370> A_IWL<44369> A_IWL<44368> A_IWL<44367> A_IWL<44366> A_IWL<44365> A_IWL<44364> A_IWL<44363> A_IWL<44362> A_IWL<44361> A_IWL<44360> A_IWL<44359> A_IWL<44358> A_IWL<44357> A_IWL<44356> A_IWL<44355> A_IWL<44354> A_IWL<44353> A_IWL<44352> A_IWL<44351> A_IWL<44350> A_IWL<44349> A_IWL<44348> A_IWL<44347> A_IWL<44346> A_IWL<44345> A_IWL<44344> A_IWL<44343> A_IWL<44342> A_IWL<44341> A_IWL<44340> A_IWL<44339> A_IWL<44338> A_IWL<44337> A_IWL<44336> A_IWL<44335> A_IWL<44334> A_IWL<44333> A_IWL<44332> A_IWL<44331> A_IWL<44330> A_IWL<44329> A_IWL<44328> A_IWL<44327> A_IWL<44326> A_IWL<44325> A_IWL<44324> A_IWL<44323> A_IWL<44322> A_IWL<44321> A_IWL<44320> A_IWL<44319> A_IWL<44318> A_IWL<44317> A_IWL<44316> A_IWL<44315> A_IWL<44314> A_IWL<44313> A_IWL<44312> A_IWL<44311> A_IWL<44310> A_IWL<44309> A_IWL<44308> A_IWL<44307> A_IWL<44306> A_IWL<44305> A_IWL<44304> A_IWL<44303> A_IWL<44302> A_IWL<44301> A_IWL<44300> A_IWL<44299> A_IWL<44298> A_IWL<44297> A_IWL<44296> A_IWL<44295> A_IWL<44294> A_IWL<44293> A_IWL<44292> A_IWL<44291> A_IWL<44290> A_IWL<44289> A_IWL<44288> A_IWL<44287> A_IWL<44286> A_IWL<44285> A_IWL<44284> A_IWL<44283> A_IWL<44282> A_IWL<44281> A_IWL<44280> A_IWL<44279> A_IWL<44278> A_IWL<44277> A_IWL<44276> A_IWL<44275> A_IWL<44274> A_IWL<44273> A_IWL<44272> A_IWL<44271> A_IWL<44270> A_IWL<44269> A_IWL<44268> A_IWL<44267> A_IWL<44266> A_IWL<44265> A_IWL<44264> A_IWL<44263> A_IWL<44262> A_IWL<44261> A_IWL<44260> A_IWL<44259> A_IWL<44258> A_IWL<44257> A_IWL<44256> A_IWL<44255> A_IWL<44254> A_IWL<44253> A_IWL<44252> A_IWL<44251> A_IWL<44250> A_IWL<44249> A_IWL<44248> A_IWL<44247> A_IWL<44246> A_IWL<44245> A_IWL<44244> A_IWL<44243> A_IWL<44242> A_IWL<44241> A_IWL<44240> A_IWL<44239> A_IWL<44238> A_IWL<44237> A_IWL<44236> A_IWL<44235> A_IWL<44234> A_IWL<44233> A_IWL<44232> A_IWL<44231> A_IWL<44230> A_IWL<44229> A_IWL<44228> A_IWL<44227> A_IWL<44226> A_IWL<44225> A_IWL<44224> A_IWL<44223> A_IWL<44222> A_IWL<44221> A_IWL<44220> A_IWL<44219> A_IWL<44218> A_IWL<44217> A_IWL<44216> A_IWL<44215> A_IWL<44214> A_IWL<44213> A_IWL<44212> A_IWL<44211> A_IWL<44210> A_IWL<44209> A_IWL<44208> A_IWL<44207> A_IWL<44206> A_IWL<44205> A_IWL<44204> A_IWL<44203> A_IWL<44202> A_IWL<44201> A_IWL<44200> A_IWL<44199> A_IWL<44198> A_IWL<44197> A_IWL<44196> A_IWL<44195> A_IWL<44194> A_IWL<44193> A_IWL<44192> A_IWL<44191> A_IWL<44190> A_IWL<44189> A_IWL<44188> A_IWL<44187> A_IWL<44186> A_IWL<44185> A_IWL<44184> A_IWL<44183> A_IWL<44182> A_IWL<44181> A_IWL<44180> A_IWL<44179> A_IWL<44178> A_IWL<44177> A_IWL<44176> A_IWL<44175> A_IWL<44174> A_IWL<44173> A_IWL<44172> A_IWL<44171> A_IWL<44170> A_IWL<44169> A_IWL<44168> A_IWL<44167> A_IWL<44166> A_IWL<44165> A_IWL<44164> A_IWL<44163> A_IWL<44162> A_IWL<44161> A_IWL<44160> A_IWL<44159> A_IWL<44158> A_IWL<44157> A_IWL<44156> A_IWL<44155> A_IWL<44154> A_IWL<44153> A_IWL<44152> A_IWL<44151> A_IWL<44150> A_IWL<44149> A_IWL<44148> A_IWL<44147> A_IWL<44146> A_IWL<44145> A_IWL<44144> A_IWL<44143> A_IWL<44142> A_IWL<44141> A_IWL<44140> A_IWL<44139> A_IWL<44138> A_IWL<44137> A_IWL<44136> A_IWL<44135> A_IWL<44134> A_IWL<44133> A_IWL<44132> A_IWL<44131> A_IWL<44130> A_IWL<44129> A_IWL<44128> A_IWL<44127> A_IWL<44126> A_IWL<44125> A_IWL<44124> A_IWL<44123> A_IWL<44122> A_IWL<44121> A_IWL<44120> A_IWL<44119> A_IWL<44118> A_IWL<44117> A_IWL<44116> A_IWL<44115> A_IWL<44114> A_IWL<44113> A_IWL<44112> A_IWL<44111> A_IWL<44110> A_IWL<44109> A_IWL<44108> A_IWL<44107> A_IWL<44106> A_IWL<44105> A_IWL<44104> A_IWL<44103> A_IWL<44102> A_IWL<44101> A_IWL<44100> A_IWL<44099> A_IWL<44098> A_IWL<44097> A_IWL<44096> A_IWL<44095> A_IWL<44094> A_IWL<44093> A_IWL<44092> A_IWL<44091> A_IWL<44090> A_IWL<44089> A_IWL<44088> A_IWL<44087> A_IWL<44086> A_IWL<44085> A_IWL<44084> A_IWL<44083> A_IWL<44082> A_IWL<44081> A_IWL<44080> A_IWL<44079> A_IWL<44078> A_IWL<44077> A_IWL<44076> A_IWL<44075> A_IWL<44074> A_IWL<44073> A_IWL<44072> A_IWL<44071> A_IWL<44070> A_IWL<44069> A_IWL<44068> A_IWL<44067> A_IWL<44066> A_IWL<44065> A_IWL<44064> A_IWL<44063> A_IWL<44062> A_IWL<44061> A_IWL<44060> A_IWL<44059> A_IWL<44058> A_IWL<44057> A_IWL<44056> A_IWL<44055> A_IWL<44054> A_IWL<44053> A_IWL<44052> A_IWL<44051> A_IWL<44050> A_IWL<44049> A_IWL<44048> A_IWL<44047> A_IWL<44046> A_IWL<44045> A_IWL<44044> A_IWL<44043> A_IWL<44042> A_IWL<44041> A_IWL<44040> A_IWL<44039> A_IWL<44038> A_IWL<44037> A_IWL<44036> A_IWL<44035> A_IWL<44034> A_IWL<44033> A_IWL<44032> VDD_CORE VSS / RM_IHPSG13_8192x32_c4_1P_COLUMN_pcell_0 +XCOL<85> A_BLC<171> A_BLC<170> A_BLC_TOP<171> A_BLC_TOP<170> A_BLT<171> A_BLT<170> A_BLT_TOP<171> A_BLT_TOP<170> A_IWL<43519> A_IWL<43518> A_IWL<43517> A_IWL<43516> A_IWL<43515> A_IWL<43514> A_IWL<43513> A_IWL<43512> A_IWL<43511> A_IWL<43510> A_IWL<43509> A_IWL<43508> A_IWL<43507> A_IWL<43506> A_IWL<43505> A_IWL<43504> A_IWL<43503> A_IWL<43502> A_IWL<43501> A_IWL<43500> A_IWL<43499> A_IWL<43498> A_IWL<43497> A_IWL<43496> A_IWL<43495> A_IWL<43494> A_IWL<43493> A_IWL<43492> A_IWL<43491> A_IWL<43490> A_IWL<43489> A_IWL<43488> A_IWL<43487> A_IWL<43486> A_IWL<43485> A_IWL<43484> A_IWL<43483> A_IWL<43482> A_IWL<43481> A_IWL<43480> A_IWL<43479> A_IWL<43478> A_IWL<43477> A_IWL<43476> A_IWL<43475> A_IWL<43474> A_IWL<43473> A_IWL<43472> A_IWL<43471> A_IWL<43470> A_IWL<43469> A_IWL<43468> A_IWL<43467> A_IWL<43466> A_IWL<43465> A_IWL<43464> A_IWL<43463> A_IWL<43462> A_IWL<43461> A_IWL<43460> A_IWL<43459> A_IWL<43458> A_IWL<43457> A_IWL<43456> A_IWL<43455> A_IWL<43454> A_IWL<43453> A_IWL<43452> A_IWL<43451> A_IWL<43450> A_IWL<43449> A_IWL<43448> A_IWL<43447> A_IWL<43446> A_IWL<43445> A_IWL<43444> A_IWL<43443> A_IWL<43442> A_IWL<43441> A_IWL<43440> A_IWL<43439> A_IWL<43438> A_IWL<43437> A_IWL<43436> A_IWL<43435> A_IWL<43434> A_IWL<43433> A_IWL<43432> A_IWL<43431> A_IWL<43430> A_IWL<43429> A_IWL<43428> A_IWL<43427> A_IWL<43426> A_IWL<43425> A_IWL<43424> A_IWL<43423> A_IWL<43422> A_IWL<43421> A_IWL<43420> A_IWL<43419> A_IWL<43418> A_IWL<43417> A_IWL<43416> A_IWL<43415> A_IWL<43414> A_IWL<43413> A_IWL<43412> A_IWL<43411> A_IWL<43410> A_IWL<43409> A_IWL<43408> A_IWL<43407> A_IWL<43406> A_IWL<43405> A_IWL<43404> A_IWL<43403> A_IWL<43402> A_IWL<43401> A_IWL<43400> A_IWL<43399> A_IWL<43398> A_IWL<43397> A_IWL<43396> A_IWL<43395> A_IWL<43394> A_IWL<43393> A_IWL<43392> A_IWL<43391> A_IWL<43390> A_IWL<43389> A_IWL<43388> A_IWL<43387> A_IWL<43386> A_IWL<43385> A_IWL<43384> A_IWL<43383> A_IWL<43382> A_IWL<43381> A_IWL<43380> A_IWL<43379> A_IWL<43378> A_IWL<43377> A_IWL<43376> A_IWL<43375> A_IWL<43374> A_IWL<43373> A_IWL<43372> A_IWL<43371> A_IWL<43370> A_IWL<43369> A_IWL<43368> A_IWL<43367> A_IWL<43366> A_IWL<43365> A_IWL<43364> A_IWL<43363> A_IWL<43362> A_IWL<43361> A_IWL<43360> A_IWL<43359> A_IWL<43358> A_IWL<43357> A_IWL<43356> A_IWL<43355> A_IWL<43354> A_IWL<43353> A_IWL<43352> A_IWL<43351> A_IWL<43350> A_IWL<43349> A_IWL<43348> A_IWL<43347> A_IWL<43346> A_IWL<43345> A_IWL<43344> A_IWL<43343> A_IWL<43342> A_IWL<43341> A_IWL<43340> A_IWL<43339> A_IWL<43338> A_IWL<43337> A_IWL<43336> A_IWL<43335> A_IWL<43334> A_IWL<43333> A_IWL<43332> A_IWL<43331> A_IWL<43330> A_IWL<43329> A_IWL<43328> A_IWL<43327> A_IWL<43326> A_IWL<43325> A_IWL<43324> A_IWL<43323> A_IWL<43322> A_IWL<43321> A_IWL<43320> A_IWL<43319> A_IWL<43318> A_IWL<43317> A_IWL<43316> A_IWL<43315> A_IWL<43314> A_IWL<43313> A_IWL<43312> A_IWL<43311> A_IWL<43310> A_IWL<43309> A_IWL<43308> A_IWL<43307> A_IWL<43306> A_IWL<43305> A_IWL<43304> A_IWL<43303> A_IWL<43302> A_IWL<43301> A_IWL<43300> A_IWL<43299> A_IWL<43298> A_IWL<43297> A_IWL<43296> A_IWL<43295> A_IWL<43294> A_IWL<43293> A_IWL<43292> A_IWL<43291> A_IWL<43290> A_IWL<43289> A_IWL<43288> A_IWL<43287> A_IWL<43286> A_IWL<43285> A_IWL<43284> A_IWL<43283> A_IWL<43282> A_IWL<43281> A_IWL<43280> A_IWL<43279> A_IWL<43278> A_IWL<43277> A_IWL<43276> A_IWL<43275> A_IWL<43274> A_IWL<43273> A_IWL<43272> A_IWL<43271> A_IWL<43270> A_IWL<43269> A_IWL<43268> A_IWL<43267> A_IWL<43266> A_IWL<43265> A_IWL<43264> A_IWL<43263> A_IWL<43262> A_IWL<43261> A_IWL<43260> A_IWL<43259> A_IWL<43258> A_IWL<43257> A_IWL<43256> A_IWL<43255> A_IWL<43254> A_IWL<43253> A_IWL<43252> A_IWL<43251> A_IWL<43250> A_IWL<43249> A_IWL<43248> A_IWL<43247> A_IWL<43246> A_IWL<43245> A_IWL<43244> A_IWL<43243> A_IWL<43242> A_IWL<43241> A_IWL<43240> A_IWL<43239> A_IWL<43238> A_IWL<43237> A_IWL<43236> A_IWL<43235> A_IWL<43234> A_IWL<43233> A_IWL<43232> A_IWL<43231> A_IWL<43230> A_IWL<43229> A_IWL<43228> A_IWL<43227> A_IWL<43226> A_IWL<43225> A_IWL<43224> A_IWL<43223> A_IWL<43222> A_IWL<43221> A_IWL<43220> A_IWL<43219> A_IWL<43218> A_IWL<43217> A_IWL<43216> A_IWL<43215> A_IWL<43214> A_IWL<43213> A_IWL<43212> A_IWL<43211> A_IWL<43210> A_IWL<43209> A_IWL<43208> A_IWL<43207> A_IWL<43206> A_IWL<43205> A_IWL<43204> A_IWL<43203> A_IWL<43202> A_IWL<43201> A_IWL<43200> A_IWL<43199> A_IWL<43198> A_IWL<43197> A_IWL<43196> A_IWL<43195> A_IWL<43194> A_IWL<43193> A_IWL<43192> A_IWL<43191> A_IWL<43190> A_IWL<43189> A_IWL<43188> A_IWL<43187> A_IWL<43186> A_IWL<43185> A_IWL<43184> A_IWL<43183> A_IWL<43182> A_IWL<43181> A_IWL<43180> A_IWL<43179> A_IWL<43178> A_IWL<43177> A_IWL<43176> A_IWL<43175> A_IWL<43174> A_IWL<43173> A_IWL<43172> A_IWL<43171> A_IWL<43170> A_IWL<43169> A_IWL<43168> A_IWL<43167> A_IWL<43166> A_IWL<43165> A_IWL<43164> A_IWL<43163> A_IWL<43162> A_IWL<43161> A_IWL<43160> A_IWL<43159> A_IWL<43158> A_IWL<43157> A_IWL<43156> A_IWL<43155> A_IWL<43154> A_IWL<43153> A_IWL<43152> A_IWL<43151> A_IWL<43150> A_IWL<43149> A_IWL<43148> A_IWL<43147> A_IWL<43146> A_IWL<43145> A_IWL<43144> A_IWL<43143> A_IWL<43142> A_IWL<43141> A_IWL<43140> A_IWL<43139> A_IWL<43138> A_IWL<43137> A_IWL<43136> A_IWL<43135> A_IWL<43134> A_IWL<43133> A_IWL<43132> A_IWL<43131> A_IWL<43130> A_IWL<43129> A_IWL<43128> A_IWL<43127> A_IWL<43126> A_IWL<43125> A_IWL<43124> A_IWL<43123> A_IWL<43122> A_IWL<43121> A_IWL<43120> A_IWL<43119> A_IWL<43118> A_IWL<43117> A_IWL<43116> A_IWL<43115> A_IWL<43114> A_IWL<43113> A_IWL<43112> A_IWL<43111> A_IWL<43110> A_IWL<43109> A_IWL<43108> A_IWL<43107> A_IWL<43106> A_IWL<43105> A_IWL<43104> A_IWL<43103> A_IWL<43102> A_IWL<43101> A_IWL<43100> A_IWL<43099> A_IWL<43098> A_IWL<43097> A_IWL<43096> A_IWL<43095> A_IWL<43094> A_IWL<43093> A_IWL<43092> A_IWL<43091> A_IWL<43090> A_IWL<43089> A_IWL<43088> A_IWL<43087> A_IWL<43086> A_IWL<43085> A_IWL<43084> A_IWL<43083> A_IWL<43082> A_IWL<43081> A_IWL<43080> A_IWL<43079> A_IWL<43078> A_IWL<43077> A_IWL<43076> A_IWL<43075> A_IWL<43074> A_IWL<43073> A_IWL<43072> A_IWL<43071> A_IWL<43070> A_IWL<43069> A_IWL<43068> A_IWL<43067> A_IWL<43066> A_IWL<43065> A_IWL<43064> A_IWL<43063> A_IWL<43062> A_IWL<43061> A_IWL<43060> A_IWL<43059> A_IWL<43058> A_IWL<43057> A_IWL<43056> A_IWL<43055> A_IWL<43054> A_IWL<43053> A_IWL<43052> A_IWL<43051> A_IWL<43050> A_IWL<43049> A_IWL<43048> A_IWL<43047> A_IWL<43046> A_IWL<43045> A_IWL<43044> A_IWL<43043> A_IWL<43042> A_IWL<43041> A_IWL<43040> A_IWL<43039> A_IWL<43038> A_IWL<43037> A_IWL<43036> A_IWL<43035> A_IWL<43034> A_IWL<43033> A_IWL<43032> A_IWL<43031> A_IWL<43030> A_IWL<43029> A_IWL<43028> A_IWL<43027> A_IWL<43026> A_IWL<43025> A_IWL<43024> A_IWL<43023> A_IWL<43022> A_IWL<43021> A_IWL<43020> A_IWL<43019> A_IWL<43018> A_IWL<43017> A_IWL<43016> A_IWL<43015> A_IWL<43014> A_IWL<43013> A_IWL<43012> A_IWL<43011> A_IWL<43010> A_IWL<43009> A_IWL<43008> A_IWL<44031> A_IWL<44030> A_IWL<44029> A_IWL<44028> A_IWL<44027> A_IWL<44026> A_IWL<44025> A_IWL<44024> A_IWL<44023> A_IWL<44022> A_IWL<44021> A_IWL<44020> A_IWL<44019> A_IWL<44018> A_IWL<44017> A_IWL<44016> A_IWL<44015> A_IWL<44014> A_IWL<44013> A_IWL<44012> A_IWL<44011> A_IWL<44010> A_IWL<44009> A_IWL<44008> A_IWL<44007> A_IWL<44006> A_IWL<44005> A_IWL<44004> A_IWL<44003> A_IWL<44002> A_IWL<44001> A_IWL<44000> A_IWL<43999> A_IWL<43998> A_IWL<43997> A_IWL<43996> A_IWL<43995> A_IWL<43994> A_IWL<43993> A_IWL<43992> A_IWL<43991> A_IWL<43990> A_IWL<43989> A_IWL<43988> A_IWL<43987> A_IWL<43986> A_IWL<43985> A_IWL<43984> A_IWL<43983> A_IWL<43982> A_IWL<43981> A_IWL<43980> A_IWL<43979> A_IWL<43978> A_IWL<43977> A_IWL<43976> A_IWL<43975> A_IWL<43974> A_IWL<43973> A_IWL<43972> A_IWL<43971> A_IWL<43970> A_IWL<43969> A_IWL<43968> A_IWL<43967> A_IWL<43966> A_IWL<43965> A_IWL<43964> A_IWL<43963> A_IWL<43962> A_IWL<43961> A_IWL<43960> A_IWL<43959> A_IWL<43958> A_IWL<43957> A_IWL<43956> A_IWL<43955> A_IWL<43954> A_IWL<43953> A_IWL<43952> A_IWL<43951> A_IWL<43950> A_IWL<43949> A_IWL<43948> A_IWL<43947> A_IWL<43946> A_IWL<43945> A_IWL<43944> A_IWL<43943> A_IWL<43942> A_IWL<43941> A_IWL<43940> A_IWL<43939> A_IWL<43938> A_IWL<43937> A_IWL<43936> A_IWL<43935> A_IWL<43934> A_IWL<43933> A_IWL<43932> A_IWL<43931> A_IWL<43930> A_IWL<43929> A_IWL<43928> A_IWL<43927> A_IWL<43926> A_IWL<43925> A_IWL<43924> A_IWL<43923> A_IWL<43922> A_IWL<43921> A_IWL<43920> A_IWL<43919> A_IWL<43918> A_IWL<43917> A_IWL<43916> A_IWL<43915> A_IWL<43914> A_IWL<43913> A_IWL<43912> A_IWL<43911> A_IWL<43910> A_IWL<43909> A_IWL<43908> A_IWL<43907> A_IWL<43906> A_IWL<43905> A_IWL<43904> A_IWL<43903> A_IWL<43902> A_IWL<43901> A_IWL<43900> A_IWL<43899> A_IWL<43898> A_IWL<43897> A_IWL<43896> A_IWL<43895> A_IWL<43894> A_IWL<43893> A_IWL<43892> A_IWL<43891> A_IWL<43890> A_IWL<43889> A_IWL<43888> A_IWL<43887> A_IWL<43886> A_IWL<43885> A_IWL<43884> A_IWL<43883> A_IWL<43882> A_IWL<43881> A_IWL<43880> A_IWL<43879> A_IWL<43878> A_IWL<43877> A_IWL<43876> A_IWL<43875> A_IWL<43874> A_IWL<43873> A_IWL<43872> A_IWL<43871> A_IWL<43870> A_IWL<43869> A_IWL<43868> A_IWL<43867> A_IWL<43866> A_IWL<43865> A_IWL<43864> A_IWL<43863> A_IWL<43862> A_IWL<43861> A_IWL<43860> A_IWL<43859> A_IWL<43858> A_IWL<43857> A_IWL<43856> A_IWL<43855> A_IWL<43854> A_IWL<43853> A_IWL<43852> A_IWL<43851> A_IWL<43850> A_IWL<43849> A_IWL<43848> A_IWL<43847> A_IWL<43846> A_IWL<43845> A_IWL<43844> A_IWL<43843> A_IWL<43842> A_IWL<43841> A_IWL<43840> A_IWL<43839> A_IWL<43838> A_IWL<43837> A_IWL<43836> A_IWL<43835> A_IWL<43834> A_IWL<43833> A_IWL<43832> A_IWL<43831> A_IWL<43830> A_IWL<43829> A_IWL<43828> A_IWL<43827> A_IWL<43826> A_IWL<43825> A_IWL<43824> A_IWL<43823> A_IWL<43822> A_IWL<43821> A_IWL<43820> A_IWL<43819> A_IWL<43818> A_IWL<43817> A_IWL<43816> A_IWL<43815> A_IWL<43814> A_IWL<43813> A_IWL<43812> A_IWL<43811> A_IWL<43810> A_IWL<43809> A_IWL<43808> A_IWL<43807> A_IWL<43806> A_IWL<43805> A_IWL<43804> A_IWL<43803> A_IWL<43802> A_IWL<43801> A_IWL<43800> A_IWL<43799> A_IWL<43798> A_IWL<43797> A_IWL<43796> A_IWL<43795> A_IWL<43794> A_IWL<43793> A_IWL<43792> A_IWL<43791> A_IWL<43790> A_IWL<43789> A_IWL<43788> A_IWL<43787> A_IWL<43786> A_IWL<43785> A_IWL<43784> A_IWL<43783> A_IWL<43782> A_IWL<43781> A_IWL<43780> A_IWL<43779> A_IWL<43778> A_IWL<43777> A_IWL<43776> A_IWL<43775> A_IWL<43774> A_IWL<43773> A_IWL<43772> A_IWL<43771> A_IWL<43770> A_IWL<43769> A_IWL<43768> A_IWL<43767> A_IWL<43766> A_IWL<43765> A_IWL<43764> A_IWL<43763> A_IWL<43762> A_IWL<43761> A_IWL<43760> A_IWL<43759> A_IWL<43758> A_IWL<43757> A_IWL<43756> A_IWL<43755> A_IWL<43754> A_IWL<43753> A_IWL<43752> A_IWL<43751> A_IWL<43750> A_IWL<43749> A_IWL<43748> A_IWL<43747> A_IWL<43746> A_IWL<43745> A_IWL<43744> A_IWL<43743> A_IWL<43742> A_IWL<43741> A_IWL<43740> A_IWL<43739> A_IWL<43738> A_IWL<43737> A_IWL<43736> A_IWL<43735> A_IWL<43734> A_IWL<43733> A_IWL<43732> A_IWL<43731> A_IWL<43730> A_IWL<43729> A_IWL<43728> A_IWL<43727> A_IWL<43726> A_IWL<43725> A_IWL<43724> A_IWL<43723> A_IWL<43722> A_IWL<43721> A_IWL<43720> A_IWL<43719> A_IWL<43718> A_IWL<43717> A_IWL<43716> A_IWL<43715> A_IWL<43714> A_IWL<43713> A_IWL<43712> A_IWL<43711> A_IWL<43710> A_IWL<43709> A_IWL<43708> A_IWL<43707> A_IWL<43706> A_IWL<43705> A_IWL<43704> A_IWL<43703> A_IWL<43702> A_IWL<43701> A_IWL<43700> A_IWL<43699> A_IWL<43698> A_IWL<43697> A_IWL<43696> A_IWL<43695> A_IWL<43694> A_IWL<43693> A_IWL<43692> A_IWL<43691> A_IWL<43690> A_IWL<43689> A_IWL<43688> A_IWL<43687> A_IWL<43686> A_IWL<43685> A_IWL<43684> A_IWL<43683> A_IWL<43682> A_IWL<43681> A_IWL<43680> A_IWL<43679> A_IWL<43678> A_IWL<43677> A_IWL<43676> A_IWL<43675> A_IWL<43674> A_IWL<43673> A_IWL<43672> A_IWL<43671> A_IWL<43670> A_IWL<43669> A_IWL<43668> A_IWL<43667> A_IWL<43666> A_IWL<43665> A_IWL<43664> A_IWL<43663> A_IWL<43662> A_IWL<43661> A_IWL<43660> A_IWL<43659> A_IWL<43658> A_IWL<43657> A_IWL<43656> A_IWL<43655> A_IWL<43654> A_IWL<43653> A_IWL<43652> A_IWL<43651> A_IWL<43650> A_IWL<43649> A_IWL<43648> A_IWL<43647> A_IWL<43646> A_IWL<43645> A_IWL<43644> A_IWL<43643> A_IWL<43642> A_IWL<43641> A_IWL<43640> A_IWL<43639> A_IWL<43638> A_IWL<43637> A_IWL<43636> A_IWL<43635> A_IWL<43634> A_IWL<43633> A_IWL<43632> A_IWL<43631> A_IWL<43630> A_IWL<43629> A_IWL<43628> A_IWL<43627> A_IWL<43626> A_IWL<43625> A_IWL<43624> A_IWL<43623> A_IWL<43622> A_IWL<43621> A_IWL<43620> A_IWL<43619> A_IWL<43618> A_IWL<43617> A_IWL<43616> A_IWL<43615> A_IWL<43614> A_IWL<43613> A_IWL<43612> A_IWL<43611> A_IWL<43610> A_IWL<43609> A_IWL<43608> A_IWL<43607> A_IWL<43606> A_IWL<43605> A_IWL<43604> A_IWL<43603> A_IWL<43602> A_IWL<43601> A_IWL<43600> A_IWL<43599> A_IWL<43598> A_IWL<43597> A_IWL<43596> A_IWL<43595> A_IWL<43594> A_IWL<43593> A_IWL<43592> A_IWL<43591> A_IWL<43590> A_IWL<43589> A_IWL<43588> A_IWL<43587> A_IWL<43586> A_IWL<43585> A_IWL<43584> A_IWL<43583> A_IWL<43582> A_IWL<43581> A_IWL<43580> A_IWL<43579> A_IWL<43578> A_IWL<43577> A_IWL<43576> A_IWL<43575> A_IWL<43574> A_IWL<43573> A_IWL<43572> A_IWL<43571> A_IWL<43570> A_IWL<43569> A_IWL<43568> A_IWL<43567> A_IWL<43566> A_IWL<43565> A_IWL<43564> A_IWL<43563> A_IWL<43562> A_IWL<43561> A_IWL<43560> A_IWL<43559> A_IWL<43558> A_IWL<43557> A_IWL<43556> A_IWL<43555> A_IWL<43554> A_IWL<43553> A_IWL<43552> A_IWL<43551> A_IWL<43550> A_IWL<43549> A_IWL<43548> A_IWL<43547> A_IWL<43546> A_IWL<43545> A_IWL<43544> A_IWL<43543> A_IWL<43542> A_IWL<43541> A_IWL<43540> A_IWL<43539> A_IWL<43538> A_IWL<43537> A_IWL<43536> A_IWL<43535> A_IWL<43534> A_IWL<43533> A_IWL<43532> A_IWL<43531> A_IWL<43530> A_IWL<43529> A_IWL<43528> A_IWL<43527> A_IWL<43526> A_IWL<43525> A_IWL<43524> A_IWL<43523> A_IWL<43522> A_IWL<43521> A_IWL<43520> VDD_CORE VSS / RM_IHPSG13_8192x32_c4_1P_COLUMN_pcell_0 +XCOL<84> A_BLC<169> A_BLC<168> A_BLC_TOP<169> A_BLC_TOP<168> A_BLT<169> A_BLT<168> A_BLT_TOP<169> A_BLT_TOP<168> A_IWL<43007> A_IWL<43006> A_IWL<43005> A_IWL<43004> A_IWL<43003> A_IWL<43002> A_IWL<43001> A_IWL<43000> A_IWL<42999> A_IWL<42998> A_IWL<42997> A_IWL<42996> A_IWL<42995> A_IWL<42994> A_IWL<42993> A_IWL<42992> A_IWL<42991> A_IWL<42990> A_IWL<42989> A_IWL<42988> A_IWL<42987> A_IWL<42986> A_IWL<42985> A_IWL<42984> A_IWL<42983> A_IWL<42982> A_IWL<42981> A_IWL<42980> A_IWL<42979> A_IWL<42978> A_IWL<42977> A_IWL<42976> A_IWL<42975> A_IWL<42974> A_IWL<42973> A_IWL<42972> A_IWL<42971> A_IWL<42970> A_IWL<42969> A_IWL<42968> A_IWL<42967> A_IWL<42966> A_IWL<42965> A_IWL<42964> A_IWL<42963> A_IWL<42962> A_IWL<42961> A_IWL<42960> A_IWL<42959> A_IWL<42958> A_IWL<42957> A_IWL<42956> A_IWL<42955> A_IWL<42954> A_IWL<42953> A_IWL<42952> A_IWL<42951> A_IWL<42950> A_IWL<42949> A_IWL<42948> A_IWL<42947> A_IWL<42946> A_IWL<42945> A_IWL<42944> A_IWL<42943> A_IWL<42942> A_IWL<42941> A_IWL<42940> A_IWL<42939> A_IWL<42938> A_IWL<42937> A_IWL<42936> A_IWL<42935> A_IWL<42934> A_IWL<42933> A_IWL<42932> A_IWL<42931> A_IWL<42930> A_IWL<42929> A_IWL<42928> A_IWL<42927> A_IWL<42926> A_IWL<42925> A_IWL<42924> A_IWL<42923> A_IWL<42922> A_IWL<42921> A_IWL<42920> A_IWL<42919> A_IWL<42918> A_IWL<42917> A_IWL<42916> A_IWL<42915> A_IWL<42914> A_IWL<42913> A_IWL<42912> A_IWL<42911> A_IWL<42910> A_IWL<42909> A_IWL<42908> A_IWL<42907> A_IWL<42906> A_IWL<42905> A_IWL<42904> A_IWL<42903> A_IWL<42902> A_IWL<42901> A_IWL<42900> A_IWL<42899> A_IWL<42898> A_IWL<42897> A_IWL<42896> A_IWL<42895> A_IWL<42894> A_IWL<42893> A_IWL<42892> A_IWL<42891> A_IWL<42890> A_IWL<42889> A_IWL<42888> A_IWL<42887> A_IWL<42886> A_IWL<42885> A_IWL<42884> A_IWL<42883> A_IWL<42882> A_IWL<42881> A_IWL<42880> A_IWL<42879> A_IWL<42878> A_IWL<42877> A_IWL<42876> A_IWL<42875> A_IWL<42874> A_IWL<42873> A_IWL<42872> A_IWL<42871> A_IWL<42870> A_IWL<42869> A_IWL<42868> A_IWL<42867> A_IWL<42866> A_IWL<42865> A_IWL<42864> A_IWL<42863> A_IWL<42862> A_IWL<42861> A_IWL<42860> A_IWL<42859> A_IWL<42858> A_IWL<42857> A_IWL<42856> A_IWL<42855> A_IWL<42854> A_IWL<42853> A_IWL<42852> A_IWL<42851> A_IWL<42850> A_IWL<42849> A_IWL<42848> A_IWL<42847> A_IWL<42846> A_IWL<42845> A_IWL<42844> A_IWL<42843> A_IWL<42842> A_IWL<42841> A_IWL<42840> A_IWL<42839> A_IWL<42838> A_IWL<42837> A_IWL<42836> A_IWL<42835> A_IWL<42834> A_IWL<42833> A_IWL<42832> A_IWL<42831> A_IWL<42830> A_IWL<42829> A_IWL<42828> A_IWL<42827> A_IWL<42826> A_IWL<42825> A_IWL<42824> A_IWL<42823> A_IWL<42822> A_IWL<42821> A_IWL<42820> A_IWL<42819> A_IWL<42818> A_IWL<42817> A_IWL<42816> A_IWL<42815> A_IWL<42814> A_IWL<42813> A_IWL<42812> A_IWL<42811> A_IWL<42810> A_IWL<42809> A_IWL<42808> A_IWL<42807> A_IWL<42806> A_IWL<42805> A_IWL<42804> A_IWL<42803> A_IWL<42802> A_IWL<42801> A_IWL<42800> A_IWL<42799> A_IWL<42798> A_IWL<42797> A_IWL<42796> A_IWL<42795> A_IWL<42794> A_IWL<42793> A_IWL<42792> A_IWL<42791> A_IWL<42790> A_IWL<42789> A_IWL<42788> A_IWL<42787> A_IWL<42786> A_IWL<42785> A_IWL<42784> A_IWL<42783> A_IWL<42782> A_IWL<42781> A_IWL<42780> A_IWL<42779> A_IWL<42778> A_IWL<42777> A_IWL<42776> A_IWL<42775> A_IWL<42774> A_IWL<42773> A_IWL<42772> A_IWL<42771> A_IWL<42770> A_IWL<42769> A_IWL<42768> A_IWL<42767> A_IWL<42766> A_IWL<42765> A_IWL<42764> A_IWL<42763> A_IWL<42762> A_IWL<42761> A_IWL<42760> A_IWL<42759> A_IWL<42758> A_IWL<42757> A_IWL<42756> A_IWL<42755> A_IWL<42754> A_IWL<42753> A_IWL<42752> A_IWL<42751> A_IWL<42750> A_IWL<42749> A_IWL<42748> A_IWL<42747> A_IWL<42746> A_IWL<42745> A_IWL<42744> A_IWL<42743> A_IWL<42742> A_IWL<42741> A_IWL<42740> A_IWL<42739> A_IWL<42738> A_IWL<42737> A_IWL<42736> A_IWL<42735> A_IWL<42734> A_IWL<42733> A_IWL<42732> A_IWL<42731> A_IWL<42730> A_IWL<42729> A_IWL<42728> A_IWL<42727> A_IWL<42726> A_IWL<42725> A_IWL<42724> A_IWL<42723> A_IWL<42722> A_IWL<42721> A_IWL<42720> A_IWL<42719> A_IWL<42718> A_IWL<42717> A_IWL<42716> A_IWL<42715> A_IWL<42714> A_IWL<42713> A_IWL<42712> A_IWL<42711> A_IWL<42710> A_IWL<42709> A_IWL<42708> A_IWL<42707> A_IWL<42706> A_IWL<42705> A_IWL<42704> A_IWL<42703> A_IWL<42702> A_IWL<42701> A_IWL<42700> A_IWL<42699> A_IWL<42698> A_IWL<42697> A_IWL<42696> A_IWL<42695> A_IWL<42694> A_IWL<42693> A_IWL<42692> A_IWL<42691> A_IWL<42690> A_IWL<42689> A_IWL<42688> A_IWL<42687> A_IWL<42686> A_IWL<42685> A_IWL<42684> A_IWL<42683> A_IWL<42682> A_IWL<42681> A_IWL<42680> A_IWL<42679> A_IWL<42678> A_IWL<42677> A_IWL<42676> A_IWL<42675> A_IWL<42674> A_IWL<42673> A_IWL<42672> A_IWL<42671> A_IWL<42670> A_IWL<42669> A_IWL<42668> A_IWL<42667> A_IWL<42666> A_IWL<42665> A_IWL<42664> A_IWL<42663> A_IWL<42662> A_IWL<42661> A_IWL<42660> A_IWL<42659> A_IWL<42658> A_IWL<42657> A_IWL<42656> A_IWL<42655> A_IWL<42654> A_IWL<42653> A_IWL<42652> A_IWL<42651> A_IWL<42650> A_IWL<42649> A_IWL<42648> A_IWL<42647> A_IWL<42646> A_IWL<42645> A_IWL<42644> A_IWL<42643> A_IWL<42642> A_IWL<42641> A_IWL<42640> A_IWL<42639> A_IWL<42638> A_IWL<42637> A_IWL<42636> A_IWL<42635> A_IWL<42634> A_IWL<42633> A_IWL<42632> A_IWL<42631> A_IWL<42630> A_IWL<42629> A_IWL<42628> A_IWL<42627> A_IWL<42626> A_IWL<42625> A_IWL<42624> A_IWL<42623> A_IWL<42622> A_IWL<42621> A_IWL<42620> A_IWL<42619> A_IWL<42618> A_IWL<42617> A_IWL<42616> A_IWL<42615> A_IWL<42614> A_IWL<42613> A_IWL<42612> A_IWL<42611> A_IWL<42610> A_IWL<42609> A_IWL<42608> A_IWL<42607> A_IWL<42606> A_IWL<42605> A_IWL<42604> A_IWL<42603> A_IWL<42602> A_IWL<42601> A_IWL<42600> A_IWL<42599> A_IWL<42598> A_IWL<42597> A_IWL<42596> A_IWL<42595> A_IWL<42594> A_IWL<42593> A_IWL<42592> A_IWL<42591> A_IWL<42590> A_IWL<42589> A_IWL<42588> A_IWL<42587> A_IWL<42586> A_IWL<42585> A_IWL<42584> A_IWL<42583> A_IWL<42582> A_IWL<42581> A_IWL<42580> A_IWL<42579> A_IWL<42578> A_IWL<42577> A_IWL<42576> A_IWL<42575> A_IWL<42574> A_IWL<42573> A_IWL<42572> A_IWL<42571> A_IWL<42570> A_IWL<42569> A_IWL<42568> A_IWL<42567> A_IWL<42566> A_IWL<42565> A_IWL<42564> A_IWL<42563> A_IWL<42562> A_IWL<42561> A_IWL<42560> A_IWL<42559> A_IWL<42558> A_IWL<42557> A_IWL<42556> A_IWL<42555> A_IWL<42554> A_IWL<42553> A_IWL<42552> A_IWL<42551> A_IWL<42550> A_IWL<42549> A_IWL<42548> A_IWL<42547> A_IWL<42546> A_IWL<42545> A_IWL<42544> A_IWL<42543> A_IWL<42542> A_IWL<42541> A_IWL<42540> A_IWL<42539> A_IWL<42538> A_IWL<42537> A_IWL<42536> A_IWL<42535> A_IWL<42534> A_IWL<42533> A_IWL<42532> A_IWL<42531> A_IWL<42530> A_IWL<42529> A_IWL<42528> A_IWL<42527> A_IWL<42526> A_IWL<42525> A_IWL<42524> A_IWL<42523> A_IWL<42522> A_IWL<42521> A_IWL<42520> A_IWL<42519> A_IWL<42518> A_IWL<42517> A_IWL<42516> A_IWL<42515> A_IWL<42514> A_IWL<42513> A_IWL<42512> A_IWL<42511> A_IWL<42510> A_IWL<42509> A_IWL<42508> A_IWL<42507> A_IWL<42506> A_IWL<42505> A_IWL<42504> A_IWL<42503> A_IWL<42502> A_IWL<42501> A_IWL<42500> A_IWL<42499> A_IWL<42498> A_IWL<42497> A_IWL<42496> A_IWL<43519> A_IWL<43518> A_IWL<43517> A_IWL<43516> A_IWL<43515> A_IWL<43514> A_IWL<43513> A_IWL<43512> A_IWL<43511> A_IWL<43510> A_IWL<43509> A_IWL<43508> A_IWL<43507> A_IWL<43506> A_IWL<43505> A_IWL<43504> A_IWL<43503> A_IWL<43502> A_IWL<43501> A_IWL<43500> A_IWL<43499> A_IWL<43498> A_IWL<43497> A_IWL<43496> A_IWL<43495> A_IWL<43494> A_IWL<43493> A_IWL<43492> A_IWL<43491> A_IWL<43490> A_IWL<43489> A_IWL<43488> A_IWL<43487> A_IWL<43486> A_IWL<43485> A_IWL<43484> A_IWL<43483> A_IWL<43482> A_IWL<43481> A_IWL<43480> A_IWL<43479> A_IWL<43478> A_IWL<43477> A_IWL<43476> A_IWL<43475> A_IWL<43474> A_IWL<43473> A_IWL<43472> A_IWL<43471> A_IWL<43470> A_IWL<43469> A_IWL<43468> A_IWL<43467> A_IWL<43466> A_IWL<43465> A_IWL<43464> A_IWL<43463> A_IWL<43462> A_IWL<43461> A_IWL<43460> A_IWL<43459> A_IWL<43458> A_IWL<43457> A_IWL<43456> A_IWL<43455> A_IWL<43454> A_IWL<43453> A_IWL<43452> A_IWL<43451> A_IWL<43450> A_IWL<43449> A_IWL<43448> A_IWL<43447> A_IWL<43446> A_IWL<43445> A_IWL<43444> A_IWL<43443> A_IWL<43442> A_IWL<43441> A_IWL<43440> A_IWL<43439> A_IWL<43438> A_IWL<43437> A_IWL<43436> A_IWL<43435> A_IWL<43434> A_IWL<43433> A_IWL<43432> A_IWL<43431> A_IWL<43430> A_IWL<43429> A_IWL<43428> A_IWL<43427> A_IWL<43426> A_IWL<43425> A_IWL<43424> A_IWL<43423> A_IWL<43422> A_IWL<43421> A_IWL<43420> A_IWL<43419> A_IWL<43418> A_IWL<43417> A_IWL<43416> A_IWL<43415> A_IWL<43414> A_IWL<43413> A_IWL<43412> A_IWL<43411> A_IWL<43410> A_IWL<43409> A_IWL<43408> A_IWL<43407> A_IWL<43406> A_IWL<43405> A_IWL<43404> A_IWL<43403> A_IWL<43402> A_IWL<43401> A_IWL<43400> A_IWL<43399> A_IWL<43398> A_IWL<43397> A_IWL<43396> A_IWL<43395> A_IWL<43394> A_IWL<43393> A_IWL<43392> A_IWL<43391> A_IWL<43390> A_IWL<43389> A_IWL<43388> A_IWL<43387> A_IWL<43386> A_IWL<43385> A_IWL<43384> A_IWL<43383> A_IWL<43382> A_IWL<43381> A_IWL<43380> A_IWL<43379> A_IWL<43378> A_IWL<43377> A_IWL<43376> A_IWL<43375> A_IWL<43374> A_IWL<43373> A_IWL<43372> A_IWL<43371> A_IWL<43370> A_IWL<43369> A_IWL<43368> A_IWL<43367> A_IWL<43366> A_IWL<43365> A_IWL<43364> A_IWL<43363> A_IWL<43362> A_IWL<43361> A_IWL<43360> A_IWL<43359> A_IWL<43358> A_IWL<43357> A_IWL<43356> A_IWL<43355> A_IWL<43354> A_IWL<43353> A_IWL<43352> A_IWL<43351> A_IWL<43350> A_IWL<43349> A_IWL<43348> A_IWL<43347> A_IWL<43346> A_IWL<43345> A_IWL<43344> A_IWL<43343> A_IWL<43342> A_IWL<43341> A_IWL<43340> A_IWL<43339> A_IWL<43338> A_IWL<43337> A_IWL<43336> A_IWL<43335> A_IWL<43334> A_IWL<43333> A_IWL<43332> A_IWL<43331> A_IWL<43330> A_IWL<43329> A_IWL<43328> A_IWL<43327> A_IWL<43326> A_IWL<43325> A_IWL<43324> A_IWL<43323> A_IWL<43322> A_IWL<43321> A_IWL<43320> A_IWL<43319> A_IWL<43318> A_IWL<43317> A_IWL<43316> A_IWL<43315> A_IWL<43314> A_IWL<43313> A_IWL<43312> A_IWL<43311> A_IWL<43310> A_IWL<43309> A_IWL<43308> A_IWL<43307> A_IWL<43306> A_IWL<43305> A_IWL<43304> A_IWL<43303> A_IWL<43302> A_IWL<43301> A_IWL<43300> A_IWL<43299> A_IWL<43298> A_IWL<43297> A_IWL<43296> A_IWL<43295> A_IWL<43294> A_IWL<43293> A_IWL<43292> A_IWL<43291> A_IWL<43290> A_IWL<43289> A_IWL<43288> A_IWL<43287> A_IWL<43286> A_IWL<43285> A_IWL<43284> A_IWL<43283> A_IWL<43282> A_IWL<43281> A_IWL<43280> A_IWL<43279> A_IWL<43278> A_IWL<43277> A_IWL<43276> A_IWL<43275> A_IWL<43274> A_IWL<43273> A_IWL<43272> A_IWL<43271> A_IWL<43270> A_IWL<43269> A_IWL<43268> A_IWL<43267> A_IWL<43266> A_IWL<43265> A_IWL<43264> A_IWL<43263> A_IWL<43262> A_IWL<43261> A_IWL<43260> A_IWL<43259> A_IWL<43258> A_IWL<43257> A_IWL<43256> A_IWL<43255> A_IWL<43254> A_IWL<43253> A_IWL<43252> A_IWL<43251> A_IWL<43250> A_IWL<43249> A_IWL<43248> A_IWL<43247> A_IWL<43246> A_IWL<43245> A_IWL<43244> A_IWL<43243> A_IWL<43242> A_IWL<43241> A_IWL<43240> A_IWL<43239> A_IWL<43238> A_IWL<43237> A_IWL<43236> A_IWL<43235> A_IWL<43234> A_IWL<43233> A_IWL<43232> A_IWL<43231> A_IWL<43230> A_IWL<43229> A_IWL<43228> A_IWL<43227> A_IWL<43226> A_IWL<43225> A_IWL<43224> A_IWL<43223> A_IWL<43222> A_IWL<43221> A_IWL<43220> A_IWL<43219> A_IWL<43218> A_IWL<43217> A_IWL<43216> A_IWL<43215> A_IWL<43214> A_IWL<43213> A_IWL<43212> A_IWL<43211> A_IWL<43210> A_IWL<43209> A_IWL<43208> A_IWL<43207> A_IWL<43206> A_IWL<43205> A_IWL<43204> A_IWL<43203> A_IWL<43202> A_IWL<43201> A_IWL<43200> A_IWL<43199> A_IWL<43198> A_IWL<43197> A_IWL<43196> A_IWL<43195> A_IWL<43194> A_IWL<43193> A_IWL<43192> A_IWL<43191> A_IWL<43190> A_IWL<43189> A_IWL<43188> A_IWL<43187> A_IWL<43186> A_IWL<43185> A_IWL<43184> A_IWL<43183> A_IWL<43182> A_IWL<43181> A_IWL<43180> A_IWL<43179> A_IWL<43178> A_IWL<43177> A_IWL<43176> A_IWL<43175> A_IWL<43174> A_IWL<43173> A_IWL<43172> A_IWL<43171> A_IWL<43170> A_IWL<43169> A_IWL<43168> A_IWL<43167> A_IWL<43166> A_IWL<43165> A_IWL<43164> A_IWL<43163> A_IWL<43162> A_IWL<43161> A_IWL<43160> A_IWL<43159> A_IWL<43158> A_IWL<43157> A_IWL<43156> A_IWL<43155> A_IWL<43154> A_IWL<43153> A_IWL<43152> A_IWL<43151> A_IWL<43150> A_IWL<43149> A_IWL<43148> A_IWL<43147> A_IWL<43146> A_IWL<43145> A_IWL<43144> A_IWL<43143> A_IWL<43142> A_IWL<43141> A_IWL<43140> A_IWL<43139> A_IWL<43138> A_IWL<43137> A_IWL<43136> A_IWL<43135> A_IWL<43134> A_IWL<43133> A_IWL<43132> A_IWL<43131> A_IWL<43130> A_IWL<43129> A_IWL<43128> A_IWL<43127> A_IWL<43126> A_IWL<43125> A_IWL<43124> A_IWL<43123> A_IWL<43122> A_IWL<43121> A_IWL<43120> A_IWL<43119> A_IWL<43118> A_IWL<43117> A_IWL<43116> A_IWL<43115> A_IWL<43114> A_IWL<43113> A_IWL<43112> A_IWL<43111> A_IWL<43110> A_IWL<43109> A_IWL<43108> A_IWL<43107> A_IWL<43106> A_IWL<43105> A_IWL<43104> A_IWL<43103> A_IWL<43102> A_IWL<43101> A_IWL<43100> A_IWL<43099> A_IWL<43098> A_IWL<43097> A_IWL<43096> A_IWL<43095> A_IWL<43094> A_IWL<43093> A_IWL<43092> A_IWL<43091> A_IWL<43090> A_IWL<43089> A_IWL<43088> A_IWL<43087> A_IWL<43086> A_IWL<43085> A_IWL<43084> A_IWL<43083> A_IWL<43082> A_IWL<43081> A_IWL<43080> A_IWL<43079> A_IWL<43078> A_IWL<43077> A_IWL<43076> A_IWL<43075> A_IWL<43074> A_IWL<43073> A_IWL<43072> A_IWL<43071> A_IWL<43070> A_IWL<43069> A_IWL<43068> A_IWL<43067> A_IWL<43066> A_IWL<43065> A_IWL<43064> A_IWL<43063> A_IWL<43062> A_IWL<43061> A_IWL<43060> A_IWL<43059> A_IWL<43058> A_IWL<43057> A_IWL<43056> A_IWL<43055> A_IWL<43054> A_IWL<43053> A_IWL<43052> A_IWL<43051> A_IWL<43050> A_IWL<43049> A_IWL<43048> A_IWL<43047> A_IWL<43046> A_IWL<43045> A_IWL<43044> A_IWL<43043> A_IWL<43042> A_IWL<43041> A_IWL<43040> A_IWL<43039> A_IWL<43038> A_IWL<43037> A_IWL<43036> A_IWL<43035> A_IWL<43034> A_IWL<43033> A_IWL<43032> A_IWL<43031> A_IWL<43030> A_IWL<43029> A_IWL<43028> A_IWL<43027> A_IWL<43026> A_IWL<43025> A_IWL<43024> A_IWL<43023> A_IWL<43022> A_IWL<43021> A_IWL<43020> A_IWL<43019> A_IWL<43018> A_IWL<43017> A_IWL<43016> A_IWL<43015> A_IWL<43014> A_IWL<43013> A_IWL<43012> A_IWL<43011> A_IWL<43010> A_IWL<43009> A_IWL<43008> VDD_CORE VSS / RM_IHPSG13_8192x32_c4_1P_COLUMN_pcell_0 +XCOL<83> A_BLC<167> A_BLC<166> A_BLC_TOP<167> A_BLC_TOP<166> A_BLT<167> A_BLT<166> A_BLT_TOP<167> A_BLT_TOP<166> A_IWL<42495> A_IWL<42494> A_IWL<42493> A_IWL<42492> A_IWL<42491> A_IWL<42490> A_IWL<42489> A_IWL<42488> A_IWL<42487> A_IWL<42486> A_IWL<42485> A_IWL<42484> A_IWL<42483> A_IWL<42482> A_IWL<42481> A_IWL<42480> A_IWL<42479> A_IWL<42478> A_IWL<42477> A_IWL<42476> A_IWL<42475> A_IWL<42474> A_IWL<42473> A_IWL<42472> A_IWL<42471> A_IWL<42470> A_IWL<42469> A_IWL<42468> A_IWL<42467> A_IWL<42466> A_IWL<42465> A_IWL<42464> A_IWL<42463> A_IWL<42462> A_IWL<42461> A_IWL<42460> A_IWL<42459> A_IWL<42458> A_IWL<42457> A_IWL<42456> A_IWL<42455> A_IWL<42454> A_IWL<42453> A_IWL<42452> A_IWL<42451> A_IWL<42450> A_IWL<42449> A_IWL<42448> A_IWL<42447> A_IWL<42446> A_IWL<42445> A_IWL<42444> A_IWL<42443> A_IWL<42442> A_IWL<42441> A_IWL<42440> A_IWL<42439> A_IWL<42438> A_IWL<42437> A_IWL<42436> A_IWL<42435> A_IWL<42434> A_IWL<42433> A_IWL<42432> A_IWL<42431> A_IWL<42430> A_IWL<42429> A_IWL<42428> A_IWL<42427> A_IWL<42426> A_IWL<42425> A_IWL<42424> A_IWL<42423> A_IWL<42422> A_IWL<42421> A_IWL<42420> A_IWL<42419> A_IWL<42418> A_IWL<42417> A_IWL<42416> A_IWL<42415> A_IWL<42414> A_IWL<42413> A_IWL<42412> A_IWL<42411> A_IWL<42410> A_IWL<42409> A_IWL<42408> A_IWL<42407> A_IWL<42406> A_IWL<42405> A_IWL<42404> A_IWL<42403> A_IWL<42402> A_IWL<42401> A_IWL<42400> A_IWL<42399> A_IWL<42398> A_IWL<42397> A_IWL<42396> A_IWL<42395> A_IWL<42394> A_IWL<42393> A_IWL<42392> A_IWL<42391> A_IWL<42390> A_IWL<42389> A_IWL<42388> A_IWL<42387> A_IWL<42386> A_IWL<42385> A_IWL<42384> A_IWL<42383> A_IWL<42382> A_IWL<42381> A_IWL<42380> A_IWL<42379> A_IWL<42378> A_IWL<42377> A_IWL<42376> A_IWL<42375> A_IWL<42374> A_IWL<42373> A_IWL<42372> A_IWL<42371> A_IWL<42370> A_IWL<42369> A_IWL<42368> A_IWL<42367> A_IWL<42366> A_IWL<42365> A_IWL<42364> A_IWL<42363> A_IWL<42362> A_IWL<42361> A_IWL<42360> A_IWL<42359> A_IWL<42358> A_IWL<42357> A_IWL<42356> A_IWL<42355> A_IWL<42354> A_IWL<42353> A_IWL<42352> A_IWL<42351> A_IWL<42350> A_IWL<42349> A_IWL<42348> A_IWL<42347> A_IWL<42346> A_IWL<42345> A_IWL<42344> A_IWL<42343> A_IWL<42342> A_IWL<42341> A_IWL<42340> A_IWL<42339> A_IWL<42338> A_IWL<42337> A_IWL<42336> A_IWL<42335> A_IWL<42334> A_IWL<42333> A_IWL<42332> A_IWL<42331> A_IWL<42330> A_IWL<42329> A_IWL<42328> A_IWL<42327> A_IWL<42326> A_IWL<42325> A_IWL<42324> A_IWL<42323> A_IWL<42322> A_IWL<42321> A_IWL<42320> A_IWL<42319> A_IWL<42318> A_IWL<42317> A_IWL<42316> A_IWL<42315> A_IWL<42314> A_IWL<42313> A_IWL<42312> A_IWL<42311> A_IWL<42310> A_IWL<42309> A_IWL<42308> A_IWL<42307> A_IWL<42306> A_IWL<42305> A_IWL<42304> A_IWL<42303> A_IWL<42302> A_IWL<42301> A_IWL<42300> A_IWL<42299> A_IWL<42298> A_IWL<42297> A_IWL<42296> A_IWL<42295> A_IWL<42294> A_IWL<42293> A_IWL<42292> A_IWL<42291> A_IWL<42290> A_IWL<42289> A_IWL<42288> A_IWL<42287> A_IWL<42286> A_IWL<42285> A_IWL<42284> A_IWL<42283> A_IWL<42282> A_IWL<42281> A_IWL<42280> A_IWL<42279> A_IWL<42278> A_IWL<42277> A_IWL<42276> A_IWL<42275> A_IWL<42274> A_IWL<42273> A_IWL<42272> A_IWL<42271> A_IWL<42270> A_IWL<42269> A_IWL<42268> A_IWL<42267> A_IWL<42266> A_IWL<42265> A_IWL<42264> A_IWL<42263> A_IWL<42262> A_IWL<42261> A_IWL<42260> A_IWL<42259> A_IWL<42258> A_IWL<42257> A_IWL<42256> A_IWL<42255> A_IWL<42254> A_IWL<42253> A_IWL<42252> A_IWL<42251> A_IWL<42250> A_IWL<42249> A_IWL<42248> A_IWL<42247> A_IWL<42246> A_IWL<42245> A_IWL<42244> A_IWL<42243> A_IWL<42242> A_IWL<42241> A_IWL<42240> A_IWL<42239> A_IWL<42238> A_IWL<42237> A_IWL<42236> A_IWL<42235> A_IWL<42234> A_IWL<42233> A_IWL<42232> A_IWL<42231> A_IWL<42230> A_IWL<42229> A_IWL<42228> A_IWL<42227> A_IWL<42226> A_IWL<42225> A_IWL<42224> A_IWL<42223> A_IWL<42222> A_IWL<42221> A_IWL<42220> A_IWL<42219> A_IWL<42218> A_IWL<42217> A_IWL<42216> A_IWL<42215> A_IWL<42214> A_IWL<42213> A_IWL<42212> A_IWL<42211> A_IWL<42210> A_IWL<42209> A_IWL<42208> A_IWL<42207> A_IWL<42206> A_IWL<42205> A_IWL<42204> A_IWL<42203> A_IWL<42202> A_IWL<42201> A_IWL<42200> A_IWL<42199> A_IWL<42198> A_IWL<42197> A_IWL<42196> A_IWL<42195> A_IWL<42194> A_IWL<42193> A_IWL<42192> A_IWL<42191> A_IWL<42190> A_IWL<42189> A_IWL<42188> A_IWL<42187> A_IWL<42186> A_IWL<42185> A_IWL<42184> A_IWL<42183> A_IWL<42182> A_IWL<42181> A_IWL<42180> A_IWL<42179> A_IWL<42178> A_IWL<42177> A_IWL<42176> A_IWL<42175> A_IWL<42174> A_IWL<42173> A_IWL<42172> A_IWL<42171> A_IWL<42170> A_IWL<42169> A_IWL<42168> A_IWL<42167> A_IWL<42166> A_IWL<42165> A_IWL<42164> A_IWL<42163> A_IWL<42162> A_IWL<42161> A_IWL<42160> A_IWL<42159> A_IWL<42158> A_IWL<42157> A_IWL<42156> A_IWL<42155> A_IWL<42154> A_IWL<42153> A_IWL<42152> A_IWL<42151> A_IWL<42150> A_IWL<42149> A_IWL<42148> A_IWL<42147> A_IWL<42146> A_IWL<42145> A_IWL<42144> A_IWL<42143> A_IWL<42142> A_IWL<42141> A_IWL<42140> A_IWL<42139> A_IWL<42138> A_IWL<42137> A_IWL<42136> A_IWL<42135> A_IWL<42134> A_IWL<42133> A_IWL<42132> A_IWL<42131> A_IWL<42130> A_IWL<42129> A_IWL<42128> A_IWL<42127> A_IWL<42126> A_IWL<42125> A_IWL<42124> A_IWL<42123> A_IWL<42122> A_IWL<42121> A_IWL<42120> A_IWL<42119> A_IWL<42118> A_IWL<42117> A_IWL<42116> A_IWL<42115> A_IWL<42114> A_IWL<42113> A_IWL<42112> A_IWL<42111> A_IWL<42110> A_IWL<42109> A_IWL<42108> A_IWL<42107> A_IWL<42106> A_IWL<42105> A_IWL<42104> A_IWL<42103> A_IWL<42102> A_IWL<42101> A_IWL<42100> A_IWL<42099> A_IWL<42098> A_IWL<42097> A_IWL<42096> A_IWL<42095> A_IWL<42094> A_IWL<42093> A_IWL<42092> A_IWL<42091> A_IWL<42090> A_IWL<42089> A_IWL<42088> A_IWL<42087> A_IWL<42086> A_IWL<42085> A_IWL<42084> A_IWL<42083> A_IWL<42082> A_IWL<42081> A_IWL<42080> A_IWL<42079> A_IWL<42078> A_IWL<42077> A_IWL<42076> A_IWL<42075> A_IWL<42074> A_IWL<42073> A_IWL<42072> A_IWL<42071> A_IWL<42070> A_IWL<42069> A_IWL<42068> A_IWL<42067> A_IWL<42066> A_IWL<42065> A_IWL<42064> A_IWL<42063> A_IWL<42062> A_IWL<42061> A_IWL<42060> A_IWL<42059> A_IWL<42058> A_IWL<42057> A_IWL<42056> A_IWL<42055> A_IWL<42054> A_IWL<42053> A_IWL<42052> A_IWL<42051> A_IWL<42050> A_IWL<42049> A_IWL<42048> A_IWL<42047> A_IWL<42046> A_IWL<42045> A_IWL<42044> A_IWL<42043> A_IWL<42042> A_IWL<42041> A_IWL<42040> A_IWL<42039> A_IWL<42038> A_IWL<42037> A_IWL<42036> A_IWL<42035> A_IWL<42034> A_IWL<42033> A_IWL<42032> A_IWL<42031> A_IWL<42030> A_IWL<42029> A_IWL<42028> A_IWL<42027> A_IWL<42026> A_IWL<42025> A_IWL<42024> A_IWL<42023> A_IWL<42022> A_IWL<42021> A_IWL<42020> A_IWL<42019> A_IWL<42018> A_IWL<42017> A_IWL<42016> A_IWL<42015> A_IWL<42014> A_IWL<42013> A_IWL<42012> A_IWL<42011> A_IWL<42010> A_IWL<42009> A_IWL<42008> A_IWL<42007> A_IWL<42006> A_IWL<42005> A_IWL<42004> A_IWL<42003> A_IWL<42002> A_IWL<42001> A_IWL<42000> A_IWL<41999> A_IWL<41998> A_IWL<41997> A_IWL<41996> A_IWL<41995> A_IWL<41994> A_IWL<41993> A_IWL<41992> A_IWL<41991> A_IWL<41990> A_IWL<41989> A_IWL<41988> A_IWL<41987> A_IWL<41986> A_IWL<41985> A_IWL<41984> A_IWL<43007> A_IWL<43006> A_IWL<43005> A_IWL<43004> A_IWL<43003> A_IWL<43002> A_IWL<43001> A_IWL<43000> A_IWL<42999> A_IWL<42998> A_IWL<42997> A_IWL<42996> A_IWL<42995> A_IWL<42994> A_IWL<42993> A_IWL<42992> A_IWL<42991> A_IWL<42990> A_IWL<42989> A_IWL<42988> A_IWL<42987> A_IWL<42986> A_IWL<42985> A_IWL<42984> A_IWL<42983> A_IWL<42982> A_IWL<42981> A_IWL<42980> A_IWL<42979> A_IWL<42978> A_IWL<42977> A_IWL<42976> A_IWL<42975> A_IWL<42974> A_IWL<42973> A_IWL<42972> A_IWL<42971> A_IWL<42970> A_IWL<42969> A_IWL<42968> A_IWL<42967> A_IWL<42966> A_IWL<42965> A_IWL<42964> A_IWL<42963> A_IWL<42962> A_IWL<42961> A_IWL<42960> A_IWL<42959> A_IWL<42958> A_IWL<42957> A_IWL<42956> A_IWL<42955> A_IWL<42954> A_IWL<42953> A_IWL<42952> A_IWL<42951> A_IWL<42950> A_IWL<42949> A_IWL<42948> A_IWL<42947> A_IWL<42946> A_IWL<42945> A_IWL<42944> A_IWL<42943> A_IWL<42942> A_IWL<42941> A_IWL<42940> A_IWL<42939> A_IWL<42938> A_IWL<42937> A_IWL<42936> A_IWL<42935> A_IWL<42934> A_IWL<42933> A_IWL<42932> A_IWL<42931> A_IWL<42930> A_IWL<42929> A_IWL<42928> A_IWL<42927> A_IWL<42926> A_IWL<42925> A_IWL<42924> A_IWL<42923> A_IWL<42922> A_IWL<42921> A_IWL<42920> A_IWL<42919> A_IWL<42918> A_IWL<42917> A_IWL<42916> A_IWL<42915> A_IWL<42914> A_IWL<42913> A_IWL<42912> A_IWL<42911> A_IWL<42910> A_IWL<42909> A_IWL<42908> A_IWL<42907> A_IWL<42906> A_IWL<42905> A_IWL<42904> A_IWL<42903> A_IWL<42902> A_IWL<42901> A_IWL<42900> A_IWL<42899> A_IWL<42898> A_IWL<42897> A_IWL<42896> A_IWL<42895> A_IWL<42894> A_IWL<42893> A_IWL<42892> A_IWL<42891> A_IWL<42890> A_IWL<42889> A_IWL<42888> A_IWL<42887> A_IWL<42886> A_IWL<42885> A_IWL<42884> A_IWL<42883> A_IWL<42882> A_IWL<42881> A_IWL<42880> A_IWL<42879> A_IWL<42878> A_IWL<42877> A_IWL<42876> A_IWL<42875> A_IWL<42874> A_IWL<42873> A_IWL<42872> A_IWL<42871> A_IWL<42870> A_IWL<42869> A_IWL<42868> A_IWL<42867> A_IWL<42866> A_IWL<42865> A_IWL<42864> A_IWL<42863> A_IWL<42862> A_IWL<42861> A_IWL<42860> A_IWL<42859> A_IWL<42858> A_IWL<42857> A_IWL<42856> A_IWL<42855> A_IWL<42854> A_IWL<42853> A_IWL<42852> A_IWL<42851> A_IWL<42850> A_IWL<42849> A_IWL<42848> A_IWL<42847> A_IWL<42846> A_IWL<42845> A_IWL<42844> A_IWL<42843> A_IWL<42842> A_IWL<42841> A_IWL<42840> A_IWL<42839> A_IWL<42838> A_IWL<42837> A_IWL<42836> A_IWL<42835> A_IWL<42834> A_IWL<42833> A_IWL<42832> A_IWL<42831> A_IWL<42830> A_IWL<42829> A_IWL<42828> A_IWL<42827> A_IWL<42826> A_IWL<42825> A_IWL<42824> A_IWL<42823> A_IWL<42822> A_IWL<42821> A_IWL<42820> A_IWL<42819> A_IWL<42818> A_IWL<42817> A_IWL<42816> A_IWL<42815> A_IWL<42814> A_IWL<42813> A_IWL<42812> A_IWL<42811> A_IWL<42810> A_IWL<42809> A_IWL<42808> A_IWL<42807> A_IWL<42806> A_IWL<42805> A_IWL<42804> A_IWL<42803> A_IWL<42802> A_IWL<42801> A_IWL<42800> A_IWL<42799> A_IWL<42798> A_IWL<42797> A_IWL<42796> A_IWL<42795> A_IWL<42794> A_IWL<42793> A_IWL<42792> A_IWL<42791> A_IWL<42790> A_IWL<42789> A_IWL<42788> A_IWL<42787> A_IWL<42786> A_IWL<42785> A_IWL<42784> A_IWL<42783> A_IWL<42782> A_IWL<42781> A_IWL<42780> A_IWL<42779> A_IWL<42778> A_IWL<42777> A_IWL<42776> A_IWL<42775> A_IWL<42774> A_IWL<42773> A_IWL<42772> A_IWL<42771> A_IWL<42770> A_IWL<42769> A_IWL<42768> A_IWL<42767> A_IWL<42766> A_IWL<42765> A_IWL<42764> A_IWL<42763> A_IWL<42762> A_IWL<42761> A_IWL<42760> A_IWL<42759> A_IWL<42758> A_IWL<42757> A_IWL<42756> A_IWL<42755> A_IWL<42754> A_IWL<42753> A_IWL<42752> A_IWL<42751> A_IWL<42750> A_IWL<42749> A_IWL<42748> A_IWL<42747> A_IWL<42746> A_IWL<42745> A_IWL<42744> A_IWL<42743> A_IWL<42742> A_IWL<42741> A_IWL<42740> A_IWL<42739> A_IWL<42738> A_IWL<42737> A_IWL<42736> A_IWL<42735> A_IWL<42734> A_IWL<42733> A_IWL<42732> A_IWL<42731> A_IWL<42730> A_IWL<42729> A_IWL<42728> A_IWL<42727> A_IWL<42726> A_IWL<42725> A_IWL<42724> A_IWL<42723> A_IWL<42722> A_IWL<42721> A_IWL<42720> A_IWL<42719> A_IWL<42718> A_IWL<42717> A_IWL<42716> A_IWL<42715> A_IWL<42714> A_IWL<42713> A_IWL<42712> A_IWL<42711> A_IWL<42710> A_IWL<42709> A_IWL<42708> A_IWL<42707> A_IWL<42706> A_IWL<42705> A_IWL<42704> A_IWL<42703> A_IWL<42702> A_IWL<42701> A_IWL<42700> A_IWL<42699> A_IWL<42698> A_IWL<42697> A_IWL<42696> A_IWL<42695> A_IWL<42694> A_IWL<42693> A_IWL<42692> A_IWL<42691> A_IWL<42690> A_IWL<42689> A_IWL<42688> A_IWL<42687> A_IWL<42686> A_IWL<42685> A_IWL<42684> A_IWL<42683> A_IWL<42682> A_IWL<42681> A_IWL<42680> A_IWL<42679> A_IWL<42678> A_IWL<42677> A_IWL<42676> A_IWL<42675> A_IWL<42674> A_IWL<42673> A_IWL<42672> A_IWL<42671> A_IWL<42670> A_IWL<42669> A_IWL<42668> A_IWL<42667> A_IWL<42666> A_IWL<42665> A_IWL<42664> A_IWL<42663> A_IWL<42662> A_IWL<42661> A_IWL<42660> A_IWL<42659> A_IWL<42658> A_IWL<42657> A_IWL<42656> A_IWL<42655> A_IWL<42654> A_IWL<42653> A_IWL<42652> A_IWL<42651> A_IWL<42650> A_IWL<42649> A_IWL<42648> A_IWL<42647> A_IWL<42646> A_IWL<42645> A_IWL<42644> A_IWL<42643> A_IWL<42642> A_IWL<42641> A_IWL<42640> A_IWL<42639> A_IWL<42638> A_IWL<42637> A_IWL<42636> A_IWL<42635> A_IWL<42634> A_IWL<42633> A_IWL<42632> A_IWL<42631> A_IWL<42630> A_IWL<42629> A_IWL<42628> A_IWL<42627> A_IWL<42626> A_IWL<42625> A_IWL<42624> A_IWL<42623> A_IWL<42622> A_IWL<42621> A_IWL<42620> A_IWL<42619> A_IWL<42618> A_IWL<42617> A_IWL<42616> A_IWL<42615> A_IWL<42614> A_IWL<42613> A_IWL<42612> A_IWL<42611> A_IWL<42610> A_IWL<42609> A_IWL<42608> A_IWL<42607> A_IWL<42606> A_IWL<42605> A_IWL<42604> A_IWL<42603> A_IWL<42602> A_IWL<42601> A_IWL<42600> A_IWL<42599> A_IWL<42598> A_IWL<42597> A_IWL<42596> A_IWL<42595> A_IWL<42594> A_IWL<42593> A_IWL<42592> A_IWL<42591> A_IWL<42590> A_IWL<42589> A_IWL<42588> A_IWL<42587> A_IWL<42586> A_IWL<42585> A_IWL<42584> A_IWL<42583> A_IWL<42582> A_IWL<42581> A_IWL<42580> A_IWL<42579> A_IWL<42578> A_IWL<42577> A_IWL<42576> A_IWL<42575> A_IWL<42574> A_IWL<42573> A_IWL<42572> A_IWL<42571> A_IWL<42570> A_IWL<42569> A_IWL<42568> A_IWL<42567> A_IWL<42566> A_IWL<42565> A_IWL<42564> A_IWL<42563> A_IWL<42562> A_IWL<42561> A_IWL<42560> A_IWL<42559> A_IWL<42558> A_IWL<42557> A_IWL<42556> A_IWL<42555> A_IWL<42554> A_IWL<42553> A_IWL<42552> A_IWL<42551> A_IWL<42550> A_IWL<42549> A_IWL<42548> A_IWL<42547> A_IWL<42546> A_IWL<42545> A_IWL<42544> A_IWL<42543> A_IWL<42542> A_IWL<42541> A_IWL<42540> A_IWL<42539> A_IWL<42538> A_IWL<42537> A_IWL<42536> A_IWL<42535> A_IWL<42534> A_IWL<42533> A_IWL<42532> A_IWL<42531> A_IWL<42530> A_IWL<42529> A_IWL<42528> A_IWL<42527> A_IWL<42526> A_IWL<42525> A_IWL<42524> A_IWL<42523> A_IWL<42522> A_IWL<42521> A_IWL<42520> A_IWL<42519> A_IWL<42518> A_IWL<42517> A_IWL<42516> A_IWL<42515> A_IWL<42514> A_IWL<42513> A_IWL<42512> A_IWL<42511> A_IWL<42510> A_IWL<42509> A_IWL<42508> A_IWL<42507> A_IWL<42506> A_IWL<42505> A_IWL<42504> A_IWL<42503> A_IWL<42502> A_IWL<42501> A_IWL<42500> A_IWL<42499> A_IWL<42498> A_IWL<42497> A_IWL<42496> VDD_CORE VSS / RM_IHPSG13_8192x32_c4_1P_COLUMN_pcell_0 +XCOL<82> A_BLC<165> A_BLC<164> A_BLC_TOP<165> A_BLC_TOP<164> A_BLT<165> A_BLT<164> A_BLT_TOP<165> A_BLT_TOP<164> A_IWL<41983> A_IWL<41982> A_IWL<41981> A_IWL<41980> A_IWL<41979> A_IWL<41978> A_IWL<41977> A_IWL<41976> A_IWL<41975> A_IWL<41974> A_IWL<41973> A_IWL<41972> A_IWL<41971> A_IWL<41970> A_IWL<41969> A_IWL<41968> A_IWL<41967> A_IWL<41966> A_IWL<41965> A_IWL<41964> A_IWL<41963> A_IWL<41962> A_IWL<41961> A_IWL<41960> A_IWL<41959> A_IWL<41958> A_IWL<41957> A_IWL<41956> A_IWL<41955> A_IWL<41954> A_IWL<41953> A_IWL<41952> A_IWL<41951> A_IWL<41950> A_IWL<41949> A_IWL<41948> A_IWL<41947> A_IWL<41946> A_IWL<41945> A_IWL<41944> A_IWL<41943> A_IWL<41942> A_IWL<41941> A_IWL<41940> A_IWL<41939> A_IWL<41938> A_IWL<41937> A_IWL<41936> A_IWL<41935> A_IWL<41934> A_IWL<41933> A_IWL<41932> A_IWL<41931> A_IWL<41930> A_IWL<41929> A_IWL<41928> A_IWL<41927> A_IWL<41926> A_IWL<41925> A_IWL<41924> A_IWL<41923> A_IWL<41922> A_IWL<41921> A_IWL<41920> A_IWL<41919> A_IWL<41918> A_IWL<41917> A_IWL<41916> A_IWL<41915> A_IWL<41914> A_IWL<41913> A_IWL<41912> A_IWL<41911> A_IWL<41910> A_IWL<41909> A_IWL<41908> A_IWL<41907> A_IWL<41906> A_IWL<41905> A_IWL<41904> A_IWL<41903> A_IWL<41902> A_IWL<41901> A_IWL<41900> A_IWL<41899> A_IWL<41898> A_IWL<41897> A_IWL<41896> A_IWL<41895> A_IWL<41894> A_IWL<41893> A_IWL<41892> A_IWL<41891> A_IWL<41890> A_IWL<41889> A_IWL<41888> A_IWL<41887> A_IWL<41886> A_IWL<41885> A_IWL<41884> A_IWL<41883> A_IWL<41882> A_IWL<41881> A_IWL<41880> A_IWL<41879> A_IWL<41878> A_IWL<41877> A_IWL<41876> A_IWL<41875> A_IWL<41874> A_IWL<41873> A_IWL<41872> A_IWL<41871> A_IWL<41870> A_IWL<41869> A_IWL<41868> A_IWL<41867> A_IWL<41866> A_IWL<41865> A_IWL<41864> A_IWL<41863> A_IWL<41862> A_IWL<41861> A_IWL<41860> A_IWL<41859> A_IWL<41858> A_IWL<41857> A_IWL<41856> A_IWL<41855> A_IWL<41854> A_IWL<41853> A_IWL<41852> A_IWL<41851> A_IWL<41850> A_IWL<41849> A_IWL<41848> A_IWL<41847> A_IWL<41846> A_IWL<41845> A_IWL<41844> A_IWL<41843> A_IWL<41842> A_IWL<41841> A_IWL<41840> A_IWL<41839> A_IWL<41838> A_IWL<41837> A_IWL<41836> A_IWL<41835> A_IWL<41834> A_IWL<41833> A_IWL<41832> A_IWL<41831> A_IWL<41830> A_IWL<41829> A_IWL<41828> A_IWL<41827> A_IWL<41826> A_IWL<41825> A_IWL<41824> A_IWL<41823> A_IWL<41822> A_IWL<41821> A_IWL<41820> A_IWL<41819> A_IWL<41818> A_IWL<41817> A_IWL<41816> A_IWL<41815> A_IWL<41814> A_IWL<41813> A_IWL<41812> A_IWL<41811> A_IWL<41810> A_IWL<41809> A_IWL<41808> A_IWL<41807> A_IWL<41806> A_IWL<41805> A_IWL<41804> A_IWL<41803> A_IWL<41802> A_IWL<41801> A_IWL<41800> A_IWL<41799> A_IWL<41798> A_IWL<41797> A_IWL<41796> A_IWL<41795> A_IWL<41794> A_IWL<41793> A_IWL<41792> A_IWL<41791> A_IWL<41790> A_IWL<41789> A_IWL<41788> A_IWL<41787> A_IWL<41786> A_IWL<41785> A_IWL<41784> A_IWL<41783> A_IWL<41782> A_IWL<41781> A_IWL<41780> A_IWL<41779> A_IWL<41778> A_IWL<41777> A_IWL<41776> A_IWL<41775> A_IWL<41774> A_IWL<41773> A_IWL<41772> A_IWL<41771> A_IWL<41770> A_IWL<41769> A_IWL<41768> A_IWL<41767> A_IWL<41766> A_IWL<41765> A_IWL<41764> A_IWL<41763> A_IWL<41762> A_IWL<41761> A_IWL<41760> A_IWL<41759> A_IWL<41758> A_IWL<41757> A_IWL<41756> A_IWL<41755> A_IWL<41754> A_IWL<41753> A_IWL<41752> A_IWL<41751> A_IWL<41750> A_IWL<41749> A_IWL<41748> A_IWL<41747> A_IWL<41746> A_IWL<41745> A_IWL<41744> A_IWL<41743> A_IWL<41742> A_IWL<41741> A_IWL<41740> A_IWL<41739> A_IWL<41738> A_IWL<41737> A_IWL<41736> A_IWL<41735> A_IWL<41734> A_IWL<41733> A_IWL<41732> A_IWL<41731> A_IWL<41730> A_IWL<41729> A_IWL<41728> A_IWL<41727> A_IWL<41726> A_IWL<41725> A_IWL<41724> A_IWL<41723> A_IWL<41722> A_IWL<41721> A_IWL<41720> A_IWL<41719> A_IWL<41718> A_IWL<41717> A_IWL<41716> A_IWL<41715> A_IWL<41714> A_IWL<41713> A_IWL<41712> A_IWL<41711> A_IWL<41710> A_IWL<41709> A_IWL<41708> A_IWL<41707> A_IWL<41706> A_IWL<41705> A_IWL<41704> A_IWL<41703> A_IWL<41702> A_IWL<41701> A_IWL<41700> A_IWL<41699> A_IWL<41698> A_IWL<41697> A_IWL<41696> A_IWL<41695> A_IWL<41694> A_IWL<41693> A_IWL<41692> A_IWL<41691> A_IWL<41690> A_IWL<41689> A_IWL<41688> A_IWL<41687> A_IWL<41686> A_IWL<41685> A_IWL<41684> A_IWL<41683> A_IWL<41682> A_IWL<41681> A_IWL<41680> A_IWL<41679> A_IWL<41678> A_IWL<41677> A_IWL<41676> A_IWL<41675> A_IWL<41674> A_IWL<41673> A_IWL<41672> A_IWL<41671> A_IWL<41670> A_IWL<41669> A_IWL<41668> A_IWL<41667> A_IWL<41666> A_IWL<41665> A_IWL<41664> A_IWL<41663> A_IWL<41662> A_IWL<41661> A_IWL<41660> A_IWL<41659> A_IWL<41658> A_IWL<41657> A_IWL<41656> A_IWL<41655> A_IWL<41654> A_IWL<41653> A_IWL<41652> A_IWL<41651> A_IWL<41650> A_IWL<41649> A_IWL<41648> A_IWL<41647> A_IWL<41646> A_IWL<41645> A_IWL<41644> A_IWL<41643> A_IWL<41642> A_IWL<41641> A_IWL<41640> A_IWL<41639> A_IWL<41638> A_IWL<41637> A_IWL<41636> A_IWL<41635> A_IWL<41634> A_IWL<41633> A_IWL<41632> A_IWL<41631> A_IWL<41630> A_IWL<41629> A_IWL<41628> A_IWL<41627> A_IWL<41626> A_IWL<41625> A_IWL<41624> A_IWL<41623> A_IWL<41622> A_IWL<41621> A_IWL<41620> A_IWL<41619> A_IWL<41618> A_IWL<41617> A_IWL<41616> A_IWL<41615> A_IWL<41614> A_IWL<41613> A_IWL<41612> A_IWL<41611> A_IWL<41610> A_IWL<41609> A_IWL<41608> A_IWL<41607> A_IWL<41606> A_IWL<41605> A_IWL<41604> A_IWL<41603> A_IWL<41602> A_IWL<41601> A_IWL<41600> A_IWL<41599> A_IWL<41598> A_IWL<41597> A_IWL<41596> A_IWL<41595> A_IWL<41594> A_IWL<41593> A_IWL<41592> A_IWL<41591> A_IWL<41590> A_IWL<41589> A_IWL<41588> A_IWL<41587> A_IWL<41586> A_IWL<41585> A_IWL<41584> A_IWL<41583> A_IWL<41582> A_IWL<41581> A_IWL<41580> A_IWL<41579> A_IWL<41578> A_IWL<41577> A_IWL<41576> A_IWL<41575> A_IWL<41574> A_IWL<41573> A_IWL<41572> A_IWL<41571> A_IWL<41570> A_IWL<41569> A_IWL<41568> A_IWL<41567> A_IWL<41566> A_IWL<41565> A_IWL<41564> A_IWL<41563> A_IWL<41562> A_IWL<41561> A_IWL<41560> A_IWL<41559> A_IWL<41558> A_IWL<41557> A_IWL<41556> A_IWL<41555> A_IWL<41554> A_IWL<41553> A_IWL<41552> A_IWL<41551> A_IWL<41550> A_IWL<41549> A_IWL<41548> A_IWL<41547> A_IWL<41546> A_IWL<41545> A_IWL<41544> A_IWL<41543> A_IWL<41542> A_IWL<41541> A_IWL<41540> A_IWL<41539> A_IWL<41538> A_IWL<41537> A_IWL<41536> A_IWL<41535> A_IWL<41534> A_IWL<41533> A_IWL<41532> A_IWL<41531> A_IWL<41530> A_IWL<41529> A_IWL<41528> A_IWL<41527> A_IWL<41526> A_IWL<41525> A_IWL<41524> A_IWL<41523> A_IWL<41522> A_IWL<41521> A_IWL<41520> A_IWL<41519> A_IWL<41518> A_IWL<41517> A_IWL<41516> A_IWL<41515> A_IWL<41514> A_IWL<41513> A_IWL<41512> A_IWL<41511> A_IWL<41510> A_IWL<41509> A_IWL<41508> A_IWL<41507> A_IWL<41506> A_IWL<41505> A_IWL<41504> A_IWL<41503> A_IWL<41502> A_IWL<41501> A_IWL<41500> A_IWL<41499> A_IWL<41498> A_IWL<41497> A_IWL<41496> A_IWL<41495> A_IWL<41494> A_IWL<41493> A_IWL<41492> A_IWL<41491> A_IWL<41490> A_IWL<41489> A_IWL<41488> A_IWL<41487> A_IWL<41486> A_IWL<41485> A_IWL<41484> A_IWL<41483> A_IWL<41482> A_IWL<41481> A_IWL<41480> A_IWL<41479> A_IWL<41478> A_IWL<41477> A_IWL<41476> A_IWL<41475> A_IWL<41474> A_IWL<41473> A_IWL<41472> A_IWL<42495> A_IWL<42494> A_IWL<42493> A_IWL<42492> A_IWL<42491> A_IWL<42490> A_IWL<42489> A_IWL<42488> A_IWL<42487> A_IWL<42486> A_IWL<42485> A_IWL<42484> A_IWL<42483> A_IWL<42482> A_IWL<42481> A_IWL<42480> A_IWL<42479> A_IWL<42478> A_IWL<42477> A_IWL<42476> A_IWL<42475> A_IWL<42474> A_IWL<42473> A_IWL<42472> A_IWL<42471> A_IWL<42470> A_IWL<42469> A_IWL<42468> A_IWL<42467> A_IWL<42466> A_IWL<42465> A_IWL<42464> A_IWL<42463> A_IWL<42462> A_IWL<42461> A_IWL<42460> A_IWL<42459> A_IWL<42458> A_IWL<42457> A_IWL<42456> A_IWL<42455> A_IWL<42454> A_IWL<42453> A_IWL<42452> A_IWL<42451> A_IWL<42450> A_IWL<42449> A_IWL<42448> A_IWL<42447> A_IWL<42446> A_IWL<42445> A_IWL<42444> A_IWL<42443> A_IWL<42442> A_IWL<42441> A_IWL<42440> A_IWL<42439> A_IWL<42438> A_IWL<42437> A_IWL<42436> A_IWL<42435> A_IWL<42434> A_IWL<42433> A_IWL<42432> A_IWL<42431> A_IWL<42430> A_IWL<42429> A_IWL<42428> A_IWL<42427> A_IWL<42426> A_IWL<42425> A_IWL<42424> A_IWL<42423> A_IWL<42422> A_IWL<42421> A_IWL<42420> A_IWL<42419> A_IWL<42418> A_IWL<42417> A_IWL<42416> A_IWL<42415> A_IWL<42414> A_IWL<42413> A_IWL<42412> A_IWL<42411> A_IWL<42410> A_IWL<42409> A_IWL<42408> A_IWL<42407> A_IWL<42406> A_IWL<42405> A_IWL<42404> A_IWL<42403> A_IWL<42402> A_IWL<42401> A_IWL<42400> A_IWL<42399> A_IWL<42398> A_IWL<42397> A_IWL<42396> A_IWL<42395> A_IWL<42394> A_IWL<42393> A_IWL<42392> A_IWL<42391> A_IWL<42390> A_IWL<42389> A_IWL<42388> A_IWL<42387> A_IWL<42386> A_IWL<42385> A_IWL<42384> A_IWL<42383> A_IWL<42382> A_IWL<42381> A_IWL<42380> A_IWL<42379> A_IWL<42378> A_IWL<42377> A_IWL<42376> A_IWL<42375> A_IWL<42374> A_IWL<42373> A_IWL<42372> A_IWL<42371> A_IWL<42370> A_IWL<42369> A_IWL<42368> A_IWL<42367> A_IWL<42366> A_IWL<42365> A_IWL<42364> A_IWL<42363> A_IWL<42362> A_IWL<42361> A_IWL<42360> A_IWL<42359> A_IWL<42358> A_IWL<42357> A_IWL<42356> A_IWL<42355> A_IWL<42354> A_IWL<42353> A_IWL<42352> A_IWL<42351> A_IWL<42350> A_IWL<42349> A_IWL<42348> A_IWL<42347> A_IWL<42346> A_IWL<42345> A_IWL<42344> A_IWL<42343> A_IWL<42342> A_IWL<42341> A_IWL<42340> A_IWL<42339> A_IWL<42338> A_IWL<42337> A_IWL<42336> A_IWL<42335> A_IWL<42334> A_IWL<42333> A_IWL<42332> A_IWL<42331> A_IWL<42330> A_IWL<42329> A_IWL<42328> A_IWL<42327> A_IWL<42326> A_IWL<42325> A_IWL<42324> A_IWL<42323> A_IWL<42322> A_IWL<42321> A_IWL<42320> A_IWL<42319> A_IWL<42318> A_IWL<42317> A_IWL<42316> A_IWL<42315> A_IWL<42314> A_IWL<42313> A_IWL<42312> A_IWL<42311> A_IWL<42310> A_IWL<42309> A_IWL<42308> A_IWL<42307> A_IWL<42306> A_IWL<42305> A_IWL<42304> A_IWL<42303> A_IWL<42302> A_IWL<42301> A_IWL<42300> A_IWL<42299> A_IWL<42298> A_IWL<42297> A_IWL<42296> A_IWL<42295> A_IWL<42294> A_IWL<42293> A_IWL<42292> A_IWL<42291> A_IWL<42290> A_IWL<42289> A_IWL<42288> A_IWL<42287> A_IWL<42286> A_IWL<42285> A_IWL<42284> A_IWL<42283> A_IWL<42282> A_IWL<42281> A_IWL<42280> A_IWL<42279> A_IWL<42278> A_IWL<42277> A_IWL<42276> A_IWL<42275> A_IWL<42274> A_IWL<42273> A_IWL<42272> A_IWL<42271> A_IWL<42270> A_IWL<42269> A_IWL<42268> A_IWL<42267> A_IWL<42266> A_IWL<42265> A_IWL<42264> A_IWL<42263> A_IWL<42262> A_IWL<42261> A_IWL<42260> A_IWL<42259> A_IWL<42258> A_IWL<42257> A_IWL<42256> A_IWL<42255> A_IWL<42254> A_IWL<42253> A_IWL<42252> A_IWL<42251> A_IWL<42250> A_IWL<42249> A_IWL<42248> A_IWL<42247> A_IWL<42246> A_IWL<42245> A_IWL<42244> A_IWL<42243> A_IWL<42242> A_IWL<42241> A_IWL<42240> A_IWL<42239> A_IWL<42238> A_IWL<42237> A_IWL<42236> A_IWL<42235> A_IWL<42234> A_IWL<42233> A_IWL<42232> A_IWL<42231> A_IWL<42230> A_IWL<42229> A_IWL<42228> A_IWL<42227> A_IWL<42226> A_IWL<42225> A_IWL<42224> A_IWL<42223> A_IWL<42222> A_IWL<42221> A_IWL<42220> A_IWL<42219> A_IWL<42218> A_IWL<42217> A_IWL<42216> A_IWL<42215> A_IWL<42214> A_IWL<42213> A_IWL<42212> A_IWL<42211> A_IWL<42210> A_IWL<42209> A_IWL<42208> A_IWL<42207> A_IWL<42206> A_IWL<42205> A_IWL<42204> A_IWL<42203> A_IWL<42202> A_IWL<42201> A_IWL<42200> A_IWL<42199> A_IWL<42198> A_IWL<42197> A_IWL<42196> A_IWL<42195> A_IWL<42194> A_IWL<42193> A_IWL<42192> A_IWL<42191> A_IWL<42190> A_IWL<42189> A_IWL<42188> A_IWL<42187> A_IWL<42186> A_IWL<42185> A_IWL<42184> A_IWL<42183> A_IWL<42182> A_IWL<42181> A_IWL<42180> A_IWL<42179> A_IWL<42178> A_IWL<42177> A_IWL<42176> A_IWL<42175> A_IWL<42174> A_IWL<42173> A_IWL<42172> A_IWL<42171> A_IWL<42170> A_IWL<42169> A_IWL<42168> A_IWL<42167> A_IWL<42166> A_IWL<42165> A_IWL<42164> A_IWL<42163> A_IWL<42162> A_IWL<42161> A_IWL<42160> A_IWL<42159> A_IWL<42158> A_IWL<42157> A_IWL<42156> A_IWL<42155> A_IWL<42154> A_IWL<42153> A_IWL<42152> A_IWL<42151> A_IWL<42150> A_IWL<42149> A_IWL<42148> A_IWL<42147> A_IWL<42146> A_IWL<42145> A_IWL<42144> A_IWL<42143> A_IWL<42142> A_IWL<42141> A_IWL<42140> A_IWL<42139> A_IWL<42138> A_IWL<42137> A_IWL<42136> A_IWL<42135> A_IWL<42134> A_IWL<42133> A_IWL<42132> A_IWL<42131> A_IWL<42130> A_IWL<42129> A_IWL<42128> A_IWL<42127> A_IWL<42126> A_IWL<42125> A_IWL<42124> A_IWL<42123> A_IWL<42122> A_IWL<42121> A_IWL<42120> A_IWL<42119> A_IWL<42118> A_IWL<42117> A_IWL<42116> A_IWL<42115> A_IWL<42114> A_IWL<42113> A_IWL<42112> A_IWL<42111> A_IWL<42110> A_IWL<42109> A_IWL<42108> A_IWL<42107> A_IWL<42106> A_IWL<42105> A_IWL<42104> A_IWL<42103> A_IWL<42102> A_IWL<42101> A_IWL<42100> A_IWL<42099> A_IWL<42098> A_IWL<42097> A_IWL<42096> A_IWL<42095> A_IWL<42094> A_IWL<42093> A_IWL<42092> A_IWL<42091> A_IWL<42090> A_IWL<42089> A_IWL<42088> A_IWL<42087> A_IWL<42086> A_IWL<42085> A_IWL<42084> A_IWL<42083> A_IWL<42082> A_IWL<42081> A_IWL<42080> A_IWL<42079> A_IWL<42078> A_IWL<42077> A_IWL<42076> A_IWL<42075> A_IWL<42074> A_IWL<42073> A_IWL<42072> A_IWL<42071> A_IWL<42070> A_IWL<42069> A_IWL<42068> A_IWL<42067> A_IWL<42066> A_IWL<42065> A_IWL<42064> A_IWL<42063> A_IWL<42062> A_IWL<42061> A_IWL<42060> A_IWL<42059> A_IWL<42058> A_IWL<42057> A_IWL<42056> A_IWL<42055> A_IWL<42054> A_IWL<42053> A_IWL<42052> A_IWL<42051> A_IWL<42050> A_IWL<42049> A_IWL<42048> A_IWL<42047> A_IWL<42046> A_IWL<42045> A_IWL<42044> A_IWL<42043> A_IWL<42042> A_IWL<42041> A_IWL<42040> A_IWL<42039> A_IWL<42038> A_IWL<42037> A_IWL<42036> A_IWL<42035> A_IWL<42034> A_IWL<42033> A_IWL<42032> A_IWL<42031> A_IWL<42030> A_IWL<42029> A_IWL<42028> A_IWL<42027> A_IWL<42026> A_IWL<42025> A_IWL<42024> A_IWL<42023> A_IWL<42022> A_IWL<42021> A_IWL<42020> A_IWL<42019> A_IWL<42018> A_IWL<42017> A_IWL<42016> A_IWL<42015> A_IWL<42014> A_IWL<42013> A_IWL<42012> A_IWL<42011> A_IWL<42010> A_IWL<42009> A_IWL<42008> A_IWL<42007> A_IWL<42006> A_IWL<42005> A_IWL<42004> A_IWL<42003> A_IWL<42002> A_IWL<42001> A_IWL<42000> A_IWL<41999> A_IWL<41998> A_IWL<41997> A_IWL<41996> A_IWL<41995> A_IWL<41994> A_IWL<41993> A_IWL<41992> A_IWL<41991> A_IWL<41990> A_IWL<41989> A_IWL<41988> A_IWL<41987> A_IWL<41986> A_IWL<41985> A_IWL<41984> VDD_CORE VSS / RM_IHPSG13_8192x32_c4_1P_COLUMN_pcell_0 +XCOL<81> A_BLC<163> A_BLC<162> A_BLC_TOP<163> A_BLC_TOP<162> A_BLT<163> A_BLT<162> A_BLT_TOP<163> A_BLT_TOP<162> A_IWL<41471> A_IWL<41470> A_IWL<41469> A_IWL<41468> A_IWL<41467> A_IWL<41466> A_IWL<41465> A_IWL<41464> A_IWL<41463> A_IWL<41462> A_IWL<41461> A_IWL<41460> A_IWL<41459> A_IWL<41458> A_IWL<41457> A_IWL<41456> A_IWL<41455> A_IWL<41454> A_IWL<41453> A_IWL<41452> A_IWL<41451> A_IWL<41450> A_IWL<41449> A_IWL<41448> A_IWL<41447> A_IWL<41446> A_IWL<41445> A_IWL<41444> A_IWL<41443> A_IWL<41442> A_IWL<41441> A_IWL<41440> A_IWL<41439> A_IWL<41438> A_IWL<41437> A_IWL<41436> A_IWL<41435> A_IWL<41434> A_IWL<41433> A_IWL<41432> A_IWL<41431> A_IWL<41430> A_IWL<41429> A_IWL<41428> A_IWL<41427> A_IWL<41426> A_IWL<41425> A_IWL<41424> A_IWL<41423> A_IWL<41422> A_IWL<41421> A_IWL<41420> A_IWL<41419> A_IWL<41418> A_IWL<41417> A_IWL<41416> A_IWL<41415> A_IWL<41414> A_IWL<41413> A_IWL<41412> A_IWL<41411> A_IWL<41410> A_IWL<41409> A_IWL<41408> A_IWL<41407> A_IWL<41406> A_IWL<41405> A_IWL<41404> A_IWL<41403> A_IWL<41402> A_IWL<41401> A_IWL<41400> A_IWL<41399> A_IWL<41398> A_IWL<41397> A_IWL<41396> A_IWL<41395> A_IWL<41394> A_IWL<41393> A_IWL<41392> A_IWL<41391> A_IWL<41390> A_IWL<41389> A_IWL<41388> A_IWL<41387> A_IWL<41386> A_IWL<41385> A_IWL<41384> A_IWL<41383> A_IWL<41382> A_IWL<41381> A_IWL<41380> A_IWL<41379> A_IWL<41378> A_IWL<41377> A_IWL<41376> A_IWL<41375> A_IWL<41374> A_IWL<41373> A_IWL<41372> A_IWL<41371> A_IWL<41370> A_IWL<41369> A_IWL<41368> A_IWL<41367> A_IWL<41366> A_IWL<41365> A_IWL<41364> A_IWL<41363> A_IWL<41362> A_IWL<41361> A_IWL<41360> A_IWL<41359> A_IWL<41358> A_IWL<41357> A_IWL<41356> A_IWL<41355> A_IWL<41354> A_IWL<41353> A_IWL<41352> A_IWL<41351> A_IWL<41350> A_IWL<41349> A_IWL<41348> A_IWL<41347> A_IWL<41346> A_IWL<41345> A_IWL<41344> A_IWL<41343> A_IWL<41342> A_IWL<41341> A_IWL<41340> A_IWL<41339> A_IWL<41338> A_IWL<41337> A_IWL<41336> A_IWL<41335> A_IWL<41334> A_IWL<41333> A_IWL<41332> A_IWL<41331> A_IWL<41330> A_IWL<41329> A_IWL<41328> A_IWL<41327> A_IWL<41326> A_IWL<41325> A_IWL<41324> A_IWL<41323> A_IWL<41322> A_IWL<41321> A_IWL<41320> A_IWL<41319> A_IWL<41318> A_IWL<41317> A_IWL<41316> A_IWL<41315> A_IWL<41314> A_IWL<41313> A_IWL<41312> A_IWL<41311> A_IWL<41310> A_IWL<41309> A_IWL<41308> A_IWL<41307> A_IWL<41306> A_IWL<41305> A_IWL<41304> A_IWL<41303> A_IWL<41302> A_IWL<41301> A_IWL<41300> A_IWL<41299> A_IWL<41298> A_IWL<41297> A_IWL<41296> A_IWL<41295> A_IWL<41294> A_IWL<41293> A_IWL<41292> A_IWL<41291> A_IWL<41290> A_IWL<41289> A_IWL<41288> A_IWL<41287> A_IWL<41286> A_IWL<41285> A_IWL<41284> A_IWL<41283> A_IWL<41282> A_IWL<41281> A_IWL<41280> A_IWL<41279> A_IWL<41278> A_IWL<41277> A_IWL<41276> A_IWL<41275> A_IWL<41274> A_IWL<41273> A_IWL<41272> A_IWL<41271> A_IWL<41270> A_IWL<41269> A_IWL<41268> A_IWL<41267> A_IWL<41266> A_IWL<41265> A_IWL<41264> A_IWL<41263> A_IWL<41262> A_IWL<41261> A_IWL<41260> A_IWL<41259> A_IWL<41258> A_IWL<41257> A_IWL<41256> A_IWL<41255> A_IWL<41254> A_IWL<41253> A_IWL<41252> A_IWL<41251> A_IWL<41250> A_IWL<41249> A_IWL<41248> A_IWL<41247> A_IWL<41246> A_IWL<41245> A_IWL<41244> A_IWL<41243> A_IWL<41242> A_IWL<41241> A_IWL<41240> A_IWL<41239> A_IWL<41238> A_IWL<41237> A_IWL<41236> A_IWL<41235> A_IWL<41234> A_IWL<41233> A_IWL<41232> A_IWL<41231> A_IWL<41230> A_IWL<41229> A_IWL<41228> A_IWL<41227> A_IWL<41226> A_IWL<41225> A_IWL<41224> A_IWL<41223> A_IWL<41222> A_IWL<41221> A_IWL<41220> A_IWL<41219> A_IWL<41218> A_IWL<41217> A_IWL<41216> A_IWL<41215> A_IWL<41214> A_IWL<41213> A_IWL<41212> A_IWL<41211> A_IWL<41210> A_IWL<41209> A_IWL<41208> A_IWL<41207> A_IWL<41206> A_IWL<41205> A_IWL<41204> A_IWL<41203> A_IWL<41202> A_IWL<41201> A_IWL<41200> A_IWL<41199> A_IWL<41198> A_IWL<41197> A_IWL<41196> A_IWL<41195> A_IWL<41194> A_IWL<41193> A_IWL<41192> A_IWL<41191> A_IWL<41190> A_IWL<41189> A_IWL<41188> A_IWL<41187> A_IWL<41186> A_IWL<41185> A_IWL<41184> A_IWL<41183> A_IWL<41182> A_IWL<41181> A_IWL<41180> A_IWL<41179> A_IWL<41178> A_IWL<41177> A_IWL<41176> A_IWL<41175> A_IWL<41174> A_IWL<41173> A_IWL<41172> A_IWL<41171> A_IWL<41170> A_IWL<41169> A_IWL<41168> A_IWL<41167> A_IWL<41166> A_IWL<41165> A_IWL<41164> A_IWL<41163> A_IWL<41162> A_IWL<41161> A_IWL<41160> A_IWL<41159> A_IWL<41158> A_IWL<41157> A_IWL<41156> A_IWL<41155> A_IWL<41154> A_IWL<41153> A_IWL<41152> A_IWL<41151> A_IWL<41150> A_IWL<41149> A_IWL<41148> A_IWL<41147> A_IWL<41146> A_IWL<41145> A_IWL<41144> A_IWL<41143> A_IWL<41142> A_IWL<41141> A_IWL<41140> A_IWL<41139> A_IWL<41138> A_IWL<41137> A_IWL<41136> A_IWL<41135> A_IWL<41134> A_IWL<41133> A_IWL<41132> A_IWL<41131> A_IWL<41130> A_IWL<41129> A_IWL<41128> A_IWL<41127> A_IWL<41126> A_IWL<41125> A_IWL<41124> A_IWL<41123> A_IWL<41122> A_IWL<41121> A_IWL<41120> A_IWL<41119> A_IWL<41118> A_IWL<41117> A_IWL<41116> A_IWL<41115> A_IWL<41114> A_IWL<41113> A_IWL<41112> A_IWL<41111> A_IWL<41110> A_IWL<41109> A_IWL<41108> A_IWL<41107> A_IWL<41106> A_IWL<41105> A_IWL<41104> A_IWL<41103> A_IWL<41102> A_IWL<41101> A_IWL<41100> A_IWL<41099> A_IWL<41098> A_IWL<41097> A_IWL<41096> A_IWL<41095> A_IWL<41094> A_IWL<41093> A_IWL<41092> A_IWL<41091> A_IWL<41090> A_IWL<41089> A_IWL<41088> A_IWL<41087> A_IWL<41086> A_IWL<41085> A_IWL<41084> A_IWL<41083> A_IWL<41082> A_IWL<41081> A_IWL<41080> A_IWL<41079> A_IWL<41078> A_IWL<41077> A_IWL<41076> A_IWL<41075> A_IWL<41074> A_IWL<41073> A_IWL<41072> A_IWL<41071> A_IWL<41070> A_IWL<41069> A_IWL<41068> A_IWL<41067> A_IWL<41066> A_IWL<41065> A_IWL<41064> A_IWL<41063> A_IWL<41062> A_IWL<41061> A_IWL<41060> A_IWL<41059> A_IWL<41058> A_IWL<41057> A_IWL<41056> A_IWL<41055> A_IWL<41054> A_IWL<41053> A_IWL<41052> A_IWL<41051> A_IWL<41050> A_IWL<41049> A_IWL<41048> A_IWL<41047> A_IWL<41046> A_IWL<41045> A_IWL<41044> A_IWL<41043> A_IWL<41042> A_IWL<41041> A_IWL<41040> A_IWL<41039> A_IWL<41038> A_IWL<41037> A_IWL<41036> A_IWL<41035> A_IWL<41034> A_IWL<41033> A_IWL<41032> A_IWL<41031> A_IWL<41030> A_IWL<41029> A_IWL<41028> A_IWL<41027> A_IWL<41026> A_IWL<41025> A_IWL<41024> A_IWL<41023> A_IWL<41022> A_IWL<41021> A_IWL<41020> A_IWL<41019> A_IWL<41018> A_IWL<41017> A_IWL<41016> A_IWL<41015> A_IWL<41014> A_IWL<41013> A_IWL<41012> A_IWL<41011> A_IWL<41010> A_IWL<41009> A_IWL<41008> A_IWL<41007> A_IWL<41006> A_IWL<41005> A_IWL<41004> A_IWL<41003> A_IWL<41002> A_IWL<41001> A_IWL<41000> A_IWL<40999> A_IWL<40998> A_IWL<40997> A_IWL<40996> A_IWL<40995> A_IWL<40994> A_IWL<40993> A_IWL<40992> A_IWL<40991> A_IWL<40990> A_IWL<40989> A_IWL<40988> A_IWL<40987> A_IWL<40986> A_IWL<40985> A_IWL<40984> A_IWL<40983> A_IWL<40982> A_IWL<40981> A_IWL<40980> A_IWL<40979> A_IWL<40978> A_IWL<40977> A_IWL<40976> A_IWL<40975> A_IWL<40974> A_IWL<40973> A_IWL<40972> A_IWL<40971> A_IWL<40970> A_IWL<40969> A_IWL<40968> A_IWL<40967> A_IWL<40966> A_IWL<40965> A_IWL<40964> A_IWL<40963> A_IWL<40962> A_IWL<40961> A_IWL<40960> A_IWL<41983> A_IWL<41982> A_IWL<41981> A_IWL<41980> A_IWL<41979> A_IWL<41978> A_IWL<41977> A_IWL<41976> A_IWL<41975> A_IWL<41974> A_IWL<41973> A_IWL<41972> A_IWL<41971> A_IWL<41970> A_IWL<41969> A_IWL<41968> A_IWL<41967> A_IWL<41966> A_IWL<41965> A_IWL<41964> A_IWL<41963> A_IWL<41962> A_IWL<41961> A_IWL<41960> A_IWL<41959> A_IWL<41958> A_IWL<41957> A_IWL<41956> A_IWL<41955> A_IWL<41954> A_IWL<41953> A_IWL<41952> A_IWL<41951> A_IWL<41950> A_IWL<41949> A_IWL<41948> A_IWL<41947> A_IWL<41946> A_IWL<41945> A_IWL<41944> A_IWL<41943> A_IWL<41942> A_IWL<41941> A_IWL<41940> A_IWL<41939> A_IWL<41938> A_IWL<41937> A_IWL<41936> A_IWL<41935> A_IWL<41934> A_IWL<41933> A_IWL<41932> A_IWL<41931> A_IWL<41930> A_IWL<41929> A_IWL<41928> A_IWL<41927> A_IWL<41926> A_IWL<41925> A_IWL<41924> A_IWL<41923> A_IWL<41922> A_IWL<41921> A_IWL<41920> A_IWL<41919> A_IWL<41918> A_IWL<41917> A_IWL<41916> A_IWL<41915> A_IWL<41914> A_IWL<41913> A_IWL<41912> A_IWL<41911> A_IWL<41910> A_IWL<41909> A_IWL<41908> A_IWL<41907> A_IWL<41906> A_IWL<41905> A_IWL<41904> A_IWL<41903> A_IWL<41902> A_IWL<41901> A_IWL<41900> A_IWL<41899> A_IWL<41898> A_IWL<41897> A_IWL<41896> A_IWL<41895> A_IWL<41894> A_IWL<41893> A_IWL<41892> A_IWL<41891> A_IWL<41890> A_IWL<41889> A_IWL<41888> A_IWL<41887> A_IWL<41886> A_IWL<41885> A_IWL<41884> A_IWL<41883> A_IWL<41882> A_IWL<41881> A_IWL<41880> A_IWL<41879> A_IWL<41878> A_IWL<41877> A_IWL<41876> A_IWL<41875> A_IWL<41874> A_IWL<41873> A_IWL<41872> A_IWL<41871> A_IWL<41870> A_IWL<41869> A_IWL<41868> A_IWL<41867> A_IWL<41866> A_IWL<41865> A_IWL<41864> A_IWL<41863> A_IWL<41862> A_IWL<41861> A_IWL<41860> A_IWL<41859> A_IWL<41858> A_IWL<41857> A_IWL<41856> A_IWL<41855> A_IWL<41854> A_IWL<41853> A_IWL<41852> A_IWL<41851> A_IWL<41850> A_IWL<41849> A_IWL<41848> A_IWL<41847> A_IWL<41846> A_IWL<41845> A_IWL<41844> A_IWL<41843> A_IWL<41842> A_IWL<41841> A_IWL<41840> A_IWL<41839> A_IWL<41838> A_IWL<41837> A_IWL<41836> A_IWL<41835> A_IWL<41834> A_IWL<41833> A_IWL<41832> A_IWL<41831> A_IWL<41830> A_IWL<41829> A_IWL<41828> A_IWL<41827> A_IWL<41826> A_IWL<41825> A_IWL<41824> A_IWL<41823> A_IWL<41822> A_IWL<41821> A_IWL<41820> A_IWL<41819> A_IWL<41818> A_IWL<41817> A_IWL<41816> A_IWL<41815> A_IWL<41814> A_IWL<41813> A_IWL<41812> A_IWL<41811> A_IWL<41810> A_IWL<41809> A_IWL<41808> A_IWL<41807> A_IWL<41806> A_IWL<41805> A_IWL<41804> A_IWL<41803> A_IWL<41802> A_IWL<41801> A_IWL<41800> A_IWL<41799> A_IWL<41798> A_IWL<41797> A_IWL<41796> A_IWL<41795> A_IWL<41794> A_IWL<41793> A_IWL<41792> A_IWL<41791> A_IWL<41790> A_IWL<41789> A_IWL<41788> A_IWL<41787> A_IWL<41786> A_IWL<41785> A_IWL<41784> A_IWL<41783> A_IWL<41782> A_IWL<41781> A_IWL<41780> A_IWL<41779> A_IWL<41778> A_IWL<41777> A_IWL<41776> A_IWL<41775> A_IWL<41774> A_IWL<41773> A_IWL<41772> A_IWL<41771> A_IWL<41770> A_IWL<41769> A_IWL<41768> A_IWL<41767> A_IWL<41766> A_IWL<41765> A_IWL<41764> A_IWL<41763> A_IWL<41762> A_IWL<41761> A_IWL<41760> A_IWL<41759> A_IWL<41758> A_IWL<41757> A_IWL<41756> A_IWL<41755> A_IWL<41754> A_IWL<41753> A_IWL<41752> A_IWL<41751> A_IWL<41750> A_IWL<41749> A_IWL<41748> A_IWL<41747> A_IWL<41746> A_IWL<41745> A_IWL<41744> A_IWL<41743> A_IWL<41742> A_IWL<41741> A_IWL<41740> A_IWL<41739> A_IWL<41738> A_IWL<41737> A_IWL<41736> A_IWL<41735> A_IWL<41734> A_IWL<41733> A_IWL<41732> A_IWL<41731> A_IWL<41730> A_IWL<41729> A_IWL<41728> A_IWL<41727> A_IWL<41726> A_IWL<41725> A_IWL<41724> A_IWL<41723> A_IWL<41722> A_IWL<41721> A_IWL<41720> A_IWL<41719> A_IWL<41718> A_IWL<41717> A_IWL<41716> A_IWL<41715> A_IWL<41714> A_IWL<41713> A_IWL<41712> A_IWL<41711> A_IWL<41710> A_IWL<41709> A_IWL<41708> A_IWL<41707> A_IWL<41706> A_IWL<41705> A_IWL<41704> A_IWL<41703> A_IWL<41702> A_IWL<41701> A_IWL<41700> A_IWL<41699> A_IWL<41698> A_IWL<41697> A_IWL<41696> A_IWL<41695> A_IWL<41694> A_IWL<41693> A_IWL<41692> A_IWL<41691> A_IWL<41690> A_IWL<41689> A_IWL<41688> A_IWL<41687> A_IWL<41686> A_IWL<41685> A_IWL<41684> A_IWL<41683> A_IWL<41682> A_IWL<41681> A_IWL<41680> A_IWL<41679> A_IWL<41678> A_IWL<41677> A_IWL<41676> A_IWL<41675> A_IWL<41674> A_IWL<41673> A_IWL<41672> A_IWL<41671> A_IWL<41670> A_IWL<41669> A_IWL<41668> A_IWL<41667> A_IWL<41666> A_IWL<41665> A_IWL<41664> A_IWL<41663> A_IWL<41662> A_IWL<41661> A_IWL<41660> A_IWL<41659> A_IWL<41658> A_IWL<41657> A_IWL<41656> A_IWL<41655> A_IWL<41654> A_IWL<41653> A_IWL<41652> A_IWL<41651> A_IWL<41650> A_IWL<41649> A_IWL<41648> A_IWL<41647> A_IWL<41646> A_IWL<41645> A_IWL<41644> A_IWL<41643> A_IWL<41642> A_IWL<41641> A_IWL<41640> A_IWL<41639> A_IWL<41638> A_IWL<41637> A_IWL<41636> A_IWL<41635> A_IWL<41634> A_IWL<41633> A_IWL<41632> A_IWL<41631> A_IWL<41630> A_IWL<41629> A_IWL<41628> A_IWL<41627> A_IWL<41626> A_IWL<41625> A_IWL<41624> A_IWL<41623> A_IWL<41622> A_IWL<41621> A_IWL<41620> A_IWL<41619> A_IWL<41618> A_IWL<41617> A_IWL<41616> A_IWL<41615> A_IWL<41614> A_IWL<41613> A_IWL<41612> A_IWL<41611> A_IWL<41610> A_IWL<41609> A_IWL<41608> A_IWL<41607> A_IWL<41606> A_IWL<41605> A_IWL<41604> A_IWL<41603> A_IWL<41602> A_IWL<41601> A_IWL<41600> A_IWL<41599> A_IWL<41598> A_IWL<41597> A_IWL<41596> A_IWL<41595> A_IWL<41594> A_IWL<41593> A_IWL<41592> A_IWL<41591> A_IWL<41590> A_IWL<41589> A_IWL<41588> A_IWL<41587> A_IWL<41586> A_IWL<41585> A_IWL<41584> A_IWL<41583> A_IWL<41582> A_IWL<41581> A_IWL<41580> A_IWL<41579> A_IWL<41578> A_IWL<41577> A_IWL<41576> A_IWL<41575> A_IWL<41574> A_IWL<41573> A_IWL<41572> A_IWL<41571> A_IWL<41570> A_IWL<41569> A_IWL<41568> A_IWL<41567> A_IWL<41566> A_IWL<41565> A_IWL<41564> A_IWL<41563> A_IWL<41562> A_IWL<41561> A_IWL<41560> A_IWL<41559> A_IWL<41558> A_IWL<41557> A_IWL<41556> A_IWL<41555> A_IWL<41554> A_IWL<41553> A_IWL<41552> A_IWL<41551> A_IWL<41550> A_IWL<41549> A_IWL<41548> A_IWL<41547> A_IWL<41546> A_IWL<41545> A_IWL<41544> A_IWL<41543> A_IWL<41542> A_IWL<41541> A_IWL<41540> A_IWL<41539> A_IWL<41538> A_IWL<41537> A_IWL<41536> A_IWL<41535> A_IWL<41534> A_IWL<41533> A_IWL<41532> A_IWL<41531> A_IWL<41530> A_IWL<41529> A_IWL<41528> A_IWL<41527> A_IWL<41526> A_IWL<41525> A_IWL<41524> A_IWL<41523> A_IWL<41522> A_IWL<41521> A_IWL<41520> A_IWL<41519> A_IWL<41518> A_IWL<41517> A_IWL<41516> A_IWL<41515> A_IWL<41514> A_IWL<41513> A_IWL<41512> A_IWL<41511> A_IWL<41510> A_IWL<41509> A_IWL<41508> A_IWL<41507> A_IWL<41506> A_IWL<41505> A_IWL<41504> A_IWL<41503> A_IWL<41502> A_IWL<41501> A_IWL<41500> A_IWL<41499> A_IWL<41498> A_IWL<41497> A_IWL<41496> A_IWL<41495> A_IWL<41494> A_IWL<41493> A_IWL<41492> A_IWL<41491> A_IWL<41490> A_IWL<41489> A_IWL<41488> A_IWL<41487> A_IWL<41486> A_IWL<41485> A_IWL<41484> A_IWL<41483> A_IWL<41482> A_IWL<41481> A_IWL<41480> A_IWL<41479> A_IWL<41478> A_IWL<41477> A_IWL<41476> A_IWL<41475> A_IWL<41474> A_IWL<41473> A_IWL<41472> VDD_CORE VSS / RM_IHPSG13_8192x32_c4_1P_COLUMN_pcell_0 +XCOL<80> A_BLC<161> A_BLC<160> A_BLC_TOP<161> A_BLC_TOP<160> A_BLT<161> A_BLT<160> A_BLT_TOP<161> A_BLT_TOP<160> A_IWL<40959> A_IWL<40958> A_IWL<40957> A_IWL<40956> A_IWL<40955> A_IWL<40954> A_IWL<40953> A_IWL<40952> A_IWL<40951> A_IWL<40950> A_IWL<40949> A_IWL<40948> A_IWL<40947> A_IWL<40946> A_IWL<40945> A_IWL<40944> A_IWL<40943> A_IWL<40942> A_IWL<40941> A_IWL<40940> A_IWL<40939> A_IWL<40938> A_IWL<40937> A_IWL<40936> A_IWL<40935> A_IWL<40934> A_IWL<40933> A_IWL<40932> A_IWL<40931> A_IWL<40930> A_IWL<40929> A_IWL<40928> A_IWL<40927> A_IWL<40926> A_IWL<40925> A_IWL<40924> A_IWL<40923> A_IWL<40922> A_IWL<40921> A_IWL<40920> A_IWL<40919> A_IWL<40918> A_IWL<40917> A_IWL<40916> A_IWL<40915> A_IWL<40914> A_IWL<40913> A_IWL<40912> A_IWL<40911> A_IWL<40910> A_IWL<40909> A_IWL<40908> A_IWL<40907> A_IWL<40906> A_IWL<40905> A_IWL<40904> A_IWL<40903> A_IWL<40902> A_IWL<40901> A_IWL<40900> A_IWL<40899> A_IWL<40898> A_IWL<40897> A_IWL<40896> A_IWL<40895> A_IWL<40894> A_IWL<40893> A_IWL<40892> A_IWL<40891> A_IWL<40890> A_IWL<40889> A_IWL<40888> A_IWL<40887> A_IWL<40886> A_IWL<40885> A_IWL<40884> A_IWL<40883> A_IWL<40882> A_IWL<40881> A_IWL<40880> A_IWL<40879> A_IWL<40878> A_IWL<40877> A_IWL<40876> A_IWL<40875> A_IWL<40874> A_IWL<40873> A_IWL<40872> A_IWL<40871> A_IWL<40870> A_IWL<40869> A_IWL<40868> A_IWL<40867> A_IWL<40866> A_IWL<40865> A_IWL<40864> A_IWL<40863> A_IWL<40862> A_IWL<40861> A_IWL<40860> A_IWL<40859> A_IWL<40858> A_IWL<40857> A_IWL<40856> A_IWL<40855> A_IWL<40854> A_IWL<40853> A_IWL<40852> A_IWL<40851> A_IWL<40850> A_IWL<40849> A_IWL<40848> A_IWL<40847> A_IWL<40846> A_IWL<40845> A_IWL<40844> A_IWL<40843> A_IWL<40842> A_IWL<40841> A_IWL<40840> A_IWL<40839> A_IWL<40838> A_IWL<40837> A_IWL<40836> A_IWL<40835> A_IWL<40834> A_IWL<40833> A_IWL<40832> A_IWL<40831> A_IWL<40830> A_IWL<40829> A_IWL<40828> A_IWL<40827> A_IWL<40826> A_IWL<40825> A_IWL<40824> A_IWL<40823> A_IWL<40822> A_IWL<40821> A_IWL<40820> A_IWL<40819> A_IWL<40818> A_IWL<40817> A_IWL<40816> A_IWL<40815> A_IWL<40814> A_IWL<40813> A_IWL<40812> A_IWL<40811> A_IWL<40810> A_IWL<40809> A_IWL<40808> A_IWL<40807> A_IWL<40806> A_IWL<40805> A_IWL<40804> A_IWL<40803> A_IWL<40802> A_IWL<40801> A_IWL<40800> A_IWL<40799> A_IWL<40798> A_IWL<40797> A_IWL<40796> A_IWL<40795> A_IWL<40794> A_IWL<40793> A_IWL<40792> A_IWL<40791> A_IWL<40790> A_IWL<40789> A_IWL<40788> A_IWL<40787> A_IWL<40786> A_IWL<40785> A_IWL<40784> A_IWL<40783> A_IWL<40782> A_IWL<40781> A_IWL<40780> A_IWL<40779> A_IWL<40778> A_IWL<40777> A_IWL<40776> A_IWL<40775> A_IWL<40774> A_IWL<40773> A_IWL<40772> A_IWL<40771> A_IWL<40770> A_IWL<40769> A_IWL<40768> A_IWL<40767> A_IWL<40766> A_IWL<40765> A_IWL<40764> A_IWL<40763> A_IWL<40762> A_IWL<40761> A_IWL<40760> A_IWL<40759> A_IWL<40758> A_IWL<40757> A_IWL<40756> A_IWL<40755> A_IWL<40754> A_IWL<40753> A_IWL<40752> A_IWL<40751> A_IWL<40750> A_IWL<40749> A_IWL<40748> A_IWL<40747> A_IWL<40746> A_IWL<40745> A_IWL<40744> A_IWL<40743> A_IWL<40742> A_IWL<40741> A_IWL<40740> A_IWL<40739> A_IWL<40738> A_IWL<40737> A_IWL<40736> A_IWL<40735> A_IWL<40734> A_IWL<40733> A_IWL<40732> A_IWL<40731> A_IWL<40730> A_IWL<40729> A_IWL<40728> A_IWL<40727> A_IWL<40726> A_IWL<40725> A_IWL<40724> A_IWL<40723> A_IWL<40722> A_IWL<40721> A_IWL<40720> A_IWL<40719> A_IWL<40718> A_IWL<40717> A_IWL<40716> A_IWL<40715> A_IWL<40714> A_IWL<40713> A_IWL<40712> A_IWL<40711> A_IWL<40710> A_IWL<40709> A_IWL<40708> A_IWL<40707> A_IWL<40706> A_IWL<40705> A_IWL<40704> A_IWL<40703> A_IWL<40702> A_IWL<40701> A_IWL<40700> A_IWL<40699> A_IWL<40698> A_IWL<40697> A_IWL<40696> A_IWL<40695> A_IWL<40694> A_IWL<40693> A_IWL<40692> A_IWL<40691> A_IWL<40690> A_IWL<40689> A_IWL<40688> A_IWL<40687> A_IWL<40686> A_IWL<40685> A_IWL<40684> A_IWL<40683> A_IWL<40682> A_IWL<40681> A_IWL<40680> A_IWL<40679> A_IWL<40678> A_IWL<40677> A_IWL<40676> A_IWL<40675> A_IWL<40674> A_IWL<40673> A_IWL<40672> A_IWL<40671> A_IWL<40670> A_IWL<40669> A_IWL<40668> A_IWL<40667> A_IWL<40666> A_IWL<40665> A_IWL<40664> A_IWL<40663> A_IWL<40662> A_IWL<40661> A_IWL<40660> A_IWL<40659> A_IWL<40658> A_IWL<40657> A_IWL<40656> A_IWL<40655> A_IWL<40654> A_IWL<40653> A_IWL<40652> A_IWL<40651> A_IWL<40650> A_IWL<40649> A_IWL<40648> A_IWL<40647> A_IWL<40646> A_IWL<40645> A_IWL<40644> A_IWL<40643> A_IWL<40642> A_IWL<40641> A_IWL<40640> A_IWL<40639> A_IWL<40638> A_IWL<40637> A_IWL<40636> A_IWL<40635> A_IWL<40634> A_IWL<40633> A_IWL<40632> A_IWL<40631> A_IWL<40630> A_IWL<40629> A_IWL<40628> A_IWL<40627> A_IWL<40626> A_IWL<40625> A_IWL<40624> A_IWL<40623> A_IWL<40622> A_IWL<40621> A_IWL<40620> A_IWL<40619> A_IWL<40618> A_IWL<40617> A_IWL<40616> A_IWL<40615> A_IWL<40614> A_IWL<40613> A_IWL<40612> A_IWL<40611> A_IWL<40610> A_IWL<40609> A_IWL<40608> A_IWL<40607> A_IWL<40606> A_IWL<40605> A_IWL<40604> A_IWL<40603> A_IWL<40602> A_IWL<40601> A_IWL<40600> A_IWL<40599> A_IWL<40598> A_IWL<40597> A_IWL<40596> A_IWL<40595> A_IWL<40594> A_IWL<40593> A_IWL<40592> A_IWL<40591> A_IWL<40590> A_IWL<40589> A_IWL<40588> A_IWL<40587> A_IWL<40586> A_IWL<40585> A_IWL<40584> A_IWL<40583> A_IWL<40582> A_IWL<40581> A_IWL<40580> A_IWL<40579> A_IWL<40578> A_IWL<40577> A_IWL<40576> A_IWL<40575> A_IWL<40574> A_IWL<40573> A_IWL<40572> A_IWL<40571> A_IWL<40570> A_IWL<40569> A_IWL<40568> A_IWL<40567> A_IWL<40566> A_IWL<40565> A_IWL<40564> A_IWL<40563> A_IWL<40562> A_IWL<40561> A_IWL<40560> A_IWL<40559> A_IWL<40558> A_IWL<40557> A_IWL<40556> A_IWL<40555> A_IWL<40554> A_IWL<40553> A_IWL<40552> A_IWL<40551> A_IWL<40550> A_IWL<40549> A_IWL<40548> A_IWL<40547> A_IWL<40546> A_IWL<40545> A_IWL<40544> A_IWL<40543> A_IWL<40542> A_IWL<40541> A_IWL<40540> A_IWL<40539> A_IWL<40538> A_IWL<40537> A_IWL<40536> A_IWL<40535> A_IWL<40534> A_IWL<40533> A_IWL<40532> A_IWL<40531> A_IWL<40530> A_IWL<40529> A_IWL<40528> A_IWL<40527> A_IWL<40526> A_IWL<40525> A_IWL<40524> A_IWL<40523> A_IWL<40522> A_IWL<40521> A_IWL<40520> A_IWL<40519> A_IWL<40518> A_IWL<40517> A_IWL<40516> A_IWL<40515> A_IWL<40514> A_IWL<40513> A_IWL<40512> A_IWL<40511> A_IWL<40510> A_IWL<40509> A_IWL<40508> A_IWL<40507> A_IWL<40506> A_IWL<40505> A_IWL<40504> A_IWL<40503> A_IWL<40502> A_IWL<40501> A_IWL<40500> A_IWL<40499> A_IWL<40498> A_IWL<40497> A_IWL<40496> A_IWL<40495> A_IWL<40494> A_IWL<40493> A_IWL<40492> A_IWL<40491> A_IWL<40490> A_IWL<40489> A_IWL<40488> A_IWL<40487> A_IWL<40486> A_IWL<40485> A_IWL<40484> A_IWL<40483> A_IWL<40482> A_IWL<40481> A_IWL<40480> A_IWL<40479> A_IWL<40478> A_IWL<40477> A_IWL<40476> A_IWL<40475> A_IWL<40474> A_IWL<40473> A_IWL<40472> A_IWL<40471> A_IWL<40470> A_IWL<40469> A_IWL<40468> A_IWL<40467> A_IWL<40466> A_IWL<40465> A_IWL<40464> A_IWL<40463> A_IWL<40462> A_IWL<40461> A_IWL<40460> A_IWL<40459> A_IWL<40458> A_IWL<40457> A_IWL<40456> A_IWL<40455> A_IWL<40454> A_IWL<40453> A_IWL<40452> A_IWL<40451> A_IWL<40450> A_IWL<40449> A_IWL<40448> A_IWL<41471> A_IWL<41470> A_IWL<41469> A_IWL<41468> A_IWL<41467> A_IWL<41466> A_IWL<41465> A_IWL<41464> A_IWL<41463> A_IWL<41462> A_IWL<41461> A_IWL<41460> A_IWL<41459> A_IWL<41458> A_IWL<41457> A_IWL<41456> A_IWL<41455> A_IWL<41454> A_IWL<41453> A_IWL<41452> A_IWL<41451> A_IWL<41450> A_IWL<41449> A_IWL<41448> A_IWL<41447> A_IWL<41446> A_IWL<41445> A_IWL<41444> A_IWL<41443> A_IWL<41442> A_IWL<41441> A_IWL<41440> A_IWL<41439> A_IWL<41438> A_IWL<41437> A_IWL<41436> A_IWL<41435> A_IWL<41434> A_IWL<41433> A_IWL<41432> A_IWL<41431> A_IWL<41430> A_IWL<41429> A_IWL<41428> A_IWL<41427> A_IWL<41426> A_IWL<41425> A_IWL<41424> A_IWL<41423> A_IWL<41422> A_IWL<41421> A_IWL<41420> A_IWL<41419> A_IWL<41418> A_IWL<41417> A_IWL<41416> A_IWL<41415> A_IWL<41414> A_IWL<41413> A_IWL<41412> A_IWL<41411> A_IWL<41410> A_IWL<41409> A_IWL<41408> A_IWL<41407> A_IWL<41406> A_IWL<41405> A_IWL<41404> A_IWL<41403> A_IWL<41402> A_IWL<41401> A_IWL<41400> A_IWL<41399> A_IWL<41398> A_IWL<41397> A_IWL<41396> A_IWL<41395> A_IWL<41394> A_IWL<41393> A_IWL<41392> A_IWL<41391> A_IWL<41390> A_IWL<41389> A_IWL<41388> A_IWL<41387> A_IWL<41386> A_IWL<41385> A_IWL<41384> A_IWL<41383> A_IWL<41382> A_IWL<41381> A_IWL<41380> A_IWL<41379> A_IWL<41378> A_IWL<41377> A_IWL<41376> A_IWL<41375> A_IWL<41374> A_IWL<41373> A_IWL<41372> A_IWL<41371> A_IWL<41370> A_IWL<41369> A_IWL<41368> A_IWL<41367> A_IWL<41366> A_IWL<41365> A_IWL<41364> A_IWL<41363> A_IWL<41362> A_IWL<41361> A_IWL<41360> A_IWL<41359> A_IWL<41358> A_IWL<41357> A_IWL<41356> A_IWL<41355> A_IWL<41354> A_IWL<41353> A_IWL<41352> A_IWL<41351> A_IWL<41350> A_IWL<41349> A_IWL<41348> A_IWL<41347> A_IWL<41346> A_IWL<41345> A_IWL<41344> A_IWL<41343> A_IWL<41342> A_IWL<41341> A_IWL<41340> A_IWL<41339> A_IWL<41338> A_IWL<41337> A_IWL<41336> A_IWL<41335> A_IWL<41334> A_IWL<41333> A_IWL<41332> A_IWL<41331> A_IWL<41330> A_IWL<41329> A_IWL<41328> A_IWL<41327> A_IWL<41326> A_IWL<41325> A_IWL<41324> A_IWL<41323> A_IWL<41322> A_IWL<41321> A_IWL<41320> A_IWL<41319> A_IWL<41318> A_IWL<41317> A_IWL<41316> A_IWL<41315> A_IWL<41314> A_IWL<41313> A_IWL<41312> A_IWL<41311> A_IWL<41310> A_IWL<41309> A_IWL<41308> A_IWL<41307> A_IWL<41306> A_IWL<41305> A_IWL<41304> A_IWL<41303> A_IWL<41302> A_IWL<41301> A_IWL<41300> A_IWL<41299> A_IWL<41298> A_IWL<41297> A_IWL<41296> A_IWL<41295> A_IWL<41294> A_IWL<41293> A_IWL<41292> A_IWL<41291> A_IWL<41290> A_IWL<41289> A_IWL<41288> A_IWL<41287> A_IWL<41286> A_IWL<41285> A_IWL<41284> A_IWL<41283> A_IWL<41282> A_IWL<41281> A_IWL<41280> A_IWL<41279> A_IWL<41278> A_IWL<41277> A_IWL<41276> A_IWL<41275> A_IWL<41274> A_IWL<41273> A_IWL<41272> A_IWL<41271> A_IWL<41270> A_IWL<41269> A_IWL<41268> A_IWL<41267> A_IWL<41266> A_IWL<41265> A_IWL<41264> A_IWL<41263> A_IWL<41262> A_IWL<41261> A_IWL<41260> A_IWL<41259> A_IWL<41258> A_IWL<41257> A_IWL<41256> A_IWL<41255> A_IWL<41254> A_IWL<41253> A_IWL<41252> A_IWL<41251> A_IWL<41250> A_IWL<41249> A_IWL<41248> A_IWL<41247> A_IWL<41246> A_IWL<41245> A_IWL<41244> A_IWL<41243> A_IWL<41242> A_IWL<41241> A_IWL<41240> A_IWL<41239> A_IWL<41238> A_IWL<41237> A_IWL<41236> A_IWL<41235> A_IWL<41234> A_IWL<41233> A_IWL<41232> A_IWL<41231> A_IWL<41230> A_IWL<41229> A_IWL<41228> A_IWL<41227> A_IWL<41226> A_IWL<41225> A_IWL<41224> A_IWL<41223> A_IWL<41222> A_IWL<41221> A_IWL<41220> A_IWL<41219> A_IWL<41218> A_IWL<41217> A_IWL<41216> A_IWL<41215> A_IWL<41214> A_IWL<41213> A_IWL<41212> A_IWL<41211> A_IWL<41210> A_IWL<41209> A_IWL<41208> A_IWL<41207> A_IWL<41206> A_IWL<41205> A_IWL<41204> A_IWL<41203> A_IWL<41202> A_IWL<41201> A_IWL<41200> A_IWL<41199> A_IWL<41198> A_IWL<41197> A_IWL<41196> A_IWL<41195> A_IWL<41194> A_IWL<41193> A_IWL<41192> A_IWL<41191> A_IWL<41190> A_IWL<41189> A_IWL<41188> A_IWL<41187> A_IWL<41186> A_IWL<41185> A_IWL<41184> A_IWL<41183> A_IWL<41182> A_IWL<41181> A_IWL<41180> A_IWL<41179> A_IWL<41178> A_IWL<41177> A_IWL<41176> A_IWL<41175> A_IWL<41174> A_IWL<41173> A_IWL<41172> A_IWL<41171> A_IWL<41170> A_IWL<41169> A_IWL<41168> A_IWL<41167> A_IWL<41166> A_IWL<41165> A_IWL<41164> A_IWL<41163> A_IWL<41162> A_IWL<41161> A_IWL<41160> A_IWL<41159> A_IWL<41158> A_IWL<41157> A_IWL<41156> A_IWL<41155> A_IWL<41154> A_IWL<41153> A_IWL<41152> A_IWL<41151> A_IWL<41150> A_IWL<41149> A_IWL<41148> A_IWL<41147> A_IWL<41146> A_IWL<41145> A_IWL<41144> A_IWL<41143> A_IWL<41142> A_IWL<41141> A_IWL<41140> A_IWL<41139> A_IWL<41138> A_IWL<41137> A_IWL<41136> A_IWL<41135> A_IWL<41134> A_IWL<41133> A_IWL<41132> A_IWL<41131> A_IWL<41130> A_IWL<41129> A_IWL<41128> A_IWL<41127> A_IWL<41126> A_IWL<41125> A_IWL<41124> A_IWL<41123> A_IWL<41122> A_IWL<41121> A_IWL<41120> A_IWL<41119> A_IWL<41118> A_IWL<41117> A_IWL<41116> A_IWL<41115> A_IWL<41114> A_IWL<41113> A_IWL<41112> A_IWL<41111> A_IWL<41110> A_IWL<41109> A_IWL<41108> A_IWL<41107> A_IWL<41106> A_IWL<41105> A_IWL<41104> A_IWL<41103> A_IWL<41102> A_IWL<41101> A_IWL<41100> A_IWL<41099> A_IWL<41098> A_IWL<41097> A_IWL<41096> A_IWL<41095> A_IWL<41094> A_IWL<41093> A_IWL<41092> A_IWL<41091> A_IWL<41090> A_IWL<41089> A_IWL<41088> A_IWL<41087> A_IWL<41086> A_IWL<41085> A_IWL<41084> A_IWL<41083> A_IWL<41082> A_IWL<41081> A_IWL<41080> A_IWL<41079> A_IWL<41078> A_IWL<41077> A_IWL<41076> A_IWL<41075> A_IWL<41074> A_IWL<41073> A_IWL<41072> A_IWL<41071> A_IWL<41070> A_IWL<41069> A_IWL<41068> A_IWL<41067> A_IWL<41066> A_IWL<41065> A_IWL<41064> A_IWL<41063> A_IWL<41062> A_IWL<41061> A_IWL<41060> A_IWL<41059> A_IWL<41058> A_IWL<41057> A_IWL<41056> A_IWL<41055> A_IWL<41054> A_IWL<41053> A_IWL<41052> A_IWL<41051> A_IWL<41050> A_IWL<41049> A_IWL<41048> A_IWL<41047> A_IWL<41046> A_IWL<41045> A_IWL<41044> A_IWL<41043> A_IWL<41042> A_IWL<41041> A_IWL<41040> A_IWL<41039> A_IWL<41038> A_IWL<41037> A_IWL<41036> A_IWL<41035> A_IWL<41034> A_IWL<41033> A_IWL<41032> A_IWL<41031> A_IWL<41030> A_IWL<41029> A_IWL<41028> A_IWL<41027> A_IWL<41026> A_IWL<41025> A_IWL<41024> A_IWL<41023> A_IWL<41022> A_IWL<41021> A_IWL<41020> A_IWL<41019> A_IWL<41018> A_IWL<41017> A_IWL<41016> A_IWL<41015> A_IWL<41014> A_IWL<41013> A_IWL<41012> A_IWL<41011> A_IWL<41010> A_IWL<41009> A_IWL<41008> A_IWL<41007> A_IWL<41006> A_IWL<41005> A_IWL<41004> A_IWL<41003> A_IWL<41002> A_IWL<41001> A_IWL<41000> A_IWL<40999> A_IWL<40998> A_IWL<40997> A_IWL<40996> A_IWL<40995> A_IWL<40994> A_IWL<40993> A_IWL<40992> A_IWL<40991> A_IWL<40990> A_IWL<40989> A_IWL<40988> A_IWL<40987> A_IWL<40986> A_IWL<40985> A_IWL<40984> A_IWL<40983> A_IWL<40982> A_IWL<40981> A_IWL<40980> A_IWL<40979> A_IWL<40978> A_IWL<40977> A_IWL<40976> A_IWL<40975> A_IWL<40974> A_IWL<40973> A_IWL<40972> A_IWL<40971> A_IWL<40970> A_IWL<40969> A_IWL<40968> A_IWL<40967> A_IWL<40966> A_IWL<40965> A_IWL<40964> A_IWL<40963> A_IWL<40962> A_IWL<40961> A_IWL<40960> VDD_CORE VSS / RM_IHPSG13_8192x32_c4_1P_COLUMN_pcell_0 +XCOL<79> A_BLC<159> A_BLC<158> A_BLC_TOP<159> A_BLC_TOP<158> A_BLT<159> A_BLT<158> A_BLT_TOP<159> A_BLT_TOP<158> A_IWL<40447> A_IWL<40446> A_IWL<40445> A_IWL<40444> A_IWL<40443> A_IWL<40442> A_IWL<40441> A_IWL<40440> A_IWL<40439> A_IWL<40438> A_IWL<40437> A_IWL<40436> A_IWL<40435> A_IWL<40434> A_IWL<40433> A_IWL<40432> A_IWL<40431> A_IWL<40430> A_IWL<40429> A_IWL<40428> A_IWL<40427> A_IWL<40426> A_IWL<40425> A_IWL<40424> A_IWL<40423> A_IWL<40422> A_IWL<40421> A_IWL<40420> A_IWL<40419> A_IWL<40418> A_IWL<40417> A_IWL<40416> A_IWL<40415> A_IWL<40414> A_IWL<40413> A_IWL<40412> A_IWL<40411> A_IWL<40410> A_IWL<40409> A_IWL<40408> A_IWL<40407> A_IWL<40406> A_IWL<40405> A_IWL<40404> A_IWL<40403> A_IWL<40402> A_IWL<40401> A_IWL<40400> A_IWL<40399> A_IWL<40398> A_IWL<40397> A_IWL<40396> A_IWL<40395> A_IWL<40394> A_IWL<40393> A_IWL<40392> A_IWL<40391> A_IWL<40390> A_IWL<40389> A_IWL<40388> A_IWL<40387> A_IWL<40386> A_IWL<40385> A_IWL<40384> A_IWL<40383> A_IWL<40382> A_IWL<40381> A_IWL<40380> A_IWL<40379> A_IWL<40378> A_IWL<40377> A_IWL<40376> A_IWL<40375> A_IWL<40374> A_IWL<40373> A_IWL<40372> A_IWL<40371> A_IWL<40370> A_IWL<40369> A_IWL<40368> A_IWL<40367> A_IWL<40366> A_IWL<40365> A_IWL<40364> A_IWL<40363> A_IWL<40362> A_IWL<40361> A_IWL<40360> A_IWL<40359> A_IWL<40358> A_IWL<40357> A_IWL<40356> A_IWL<40355> A_IWL<40354> A_IWL<40353> A_IWL<40352> A_IWL<40351> A_IWL<40350> A_IWL<40349> A_IWL<40348> A_IWL<40347> A_IWL<40346> A_IWL<40345> A_IWL<40344> A_IWL<40343> A_IWL<40342> A_IWL<40341> A_IWL<40340> A_IWL<40339> A_IWL<40338> A_IWL<40337> A_IWL<40336> A_IWL<40335> A_IWL<40334> A_IWL<40333> A_IWL<40332> A_IWL<40331> A_IWL<40330> A_IWL<40329> A_IWL<40328> A_IWL<40327> A_IWL<40326> A_IWL<40325> A_IWL<40324> A_IWL<40323> A_IWL<40322> A_IWL<40321> A_IWL<40320> A_IWL<40319> A_IWL<40318> A_IWL<40317> A_IWL<40316> A_IWL<40315> A_IWL<40314> A_IWL<40313> A_IWL<40312> A_IWL<40311> A_IWL<40310> A_IWL<40309> A_IWL<40308> A_IWL<40307> A_IWL<40306> A_IWL<40305> A_IWL<40304> A_IWL<40303> A_IWL<40302> A_IWL<40301> A_IWL<40300> A_IWL<40299> A_IWL<40298> A_IWL<40297> A_IWL<40296> A_IWL<40295> A_IWL<40294> A_IWL<40293> A_IWL<40292> A_IWL<40291> A_IWL<40290> A_IWL<40289> A_IWL<40288> A_IWL<40287> A_IWL<40286> A_IWL<40285> A_IWL<40284> A_IWL<40283> A_IWL<40282> A_IWL<40281> A_IWL<40280> A_IWL<40279> A_IWL<40278> A_IWL<40277> A_IWL<40276> A_IWL<40275> A_IWL<40274> A_IWL<40273> A_IWL<40272> A_IWL<40271> A_IWL<40270> A_IWL<40269> A_IWL<40268> A_IWL<40267> A_IWL<40266> A_IWL<40265> A_IWL<40264> A_IWL<40263> A_IWL<40262> A_IWL<40261> A_IWL<40260> A_IWL<40259> A_IWL<40258> A_IWL<40257> A_IWL<40256> A_IWL<40255> A_IWL<40254> A_IWL<40253> A_IWL<40252> A_IWL<40251> A_IWL<40250> A_IWL<40249> A_IWL<40248> A_IWL<40247> A_IWL<40246> A_IWL<40245> A_IWL<40244> A_IWL<40243> A_IWL<40242> A_IWL<40241> A_IWL<40240> A_IWL<40239> A_IWL<40238> A_IWL<40237> A_IWL<40236> A_IWL<40235> A_IWL<40234> A_IWL<40233> A_IWL<40232> A_IWL<40231> A_IWL<40230> A_IWL<40229> A_IWL<40228> A_IWL<40227> A_IWL<40226> A_IWL<40225> A_IWL<40224> A_IWL<40223> A_IWL<40222> A_IWL<40221> A_IWL<40220> A_IWL<40219> A_IWL<40218> A_IWL<40217> A_IWL<40216> A_IWL<40215> A_IWL<40214> A_IWL<40213> A_IWL<40212> A_IWL<40211> A_IWL<40210> A_IWL<40209> A_IWL<40208> A_IWL<40207> A_IWL<40206> A_IWL<40205> A_IWL<40204> A_IWL<40203> A_IWL<40202> A_IWL<40201> A_IWL<40200> A_IWL<40199> A_IWL<40198> A_IWL<40197> A_IWL<40196> A_IWL<40195> A_IWL<40194> A_IWL<40193> A_IWL<40192> A_IWL<40191> A_IWL<40190> A_IWL<40189> A_IWL<40188> A_IWL<40187> A_IWL<40186> A_IWL<40185> A_IWL<40184> A_IWL<40183> A_IWL<40182> A_IWL<40181> A_IWL<40180> A_IWL<40179> A_IWL<40178> A_IWL<40177> A_IWL<40176> A_IWL<40175> A_IWL<40174> A_IWL<40173> A_IWL<40172> A_IWL<40171> A_IWL<40170> A_IWL<40169> A_IWL<40168> A_IWL<40167> A_IWL<40166> A_IWL<40165> A_IWL<40164> A_IWL<40163> A_IWL<40162> A_IWL<40161> A_IWL<40160> A_IWL<40159> A_IWL<40158> A_IWL<40157> A_IWL<40156> A_IWL<40155> A_IWL<40154> A_IWL<40153> A_IWL<40152> A_IWL<40151> A_IWL<40150> A_IWL<40149> A_IWL<40148> A_IWL<40147> A_IWL<40146> A_IWL<40145> A_IWL<40144> A_IWL<40143> A_IWL<40142> A_IWL<40141> A_IWL<40140> A_IWL<40139> A_IWL<40138> A_IWL<40137> A_IWL<40136> A_IWL<40135> A_IWL<40134> A_IWL<40133> A_IWL<40132> A_IWL<40131> A_IWL<40130> A_IWL<40129> A_IWL<40128> A_IWL<40127> A_IWL<40126> A_IWL<40125> A_IWL<40124> A_IWL<40123> A_IWL<40122> A_IWL<40121> A_IWL<40120> A_IWL<40119> A_IWL<40118> A_IWL<40117> A_IWL<40116> A_IWL<40115> A_IWL<40114> A_IWL<40113> A_IWL<40112> A_IWL<40111> A_IWL<40110> A_IWL<40109> A_IWL<40108> A_IWL<40107> A_IWL<40106> A_IWL<40105> A_IWL<40104> A_IWL<40103> A_IWL<40102> A_IWL<40101> A_IWL<40100> A_IWL<40099> A_IWL<40098> A_IWL<40097> A_IWL<40096> A_IWL<40095> A_IWL<40094> A_IWL<40093> A_IWL<40092> A_IWL<40091> A_IWL<40090> A_IWL<40089> A_IWL<40088> A_IWL<40087> A_IWL<40086> A_IWL<40085> A_IWL<40084> A_IWL<40083> A_IWL<40082> A_IWL<40081> A_IWL<40080> A_IWL<40079> A_IWL<40078> A_IWL<40077> A_IWL<40076> A_IWL<40075> A_IWL<40074> A_IWL<40073> A_IWL<40072> A_IWL<40071> A_IWL<40070> A_IWL<40069> A_IWL<40068> A_IWL<40067> A_IWL<40066> A_IWL<40065> A_IWL<40064> A_IWL<40063> A_IWL<40062> A_IWL<40061> A_IWL<40060> A_IWL<40059> A_IWL<40058> A_IWL<40057> A_IWL<40056> A_IWL<40055> A_IWL<40054> A_IWL<40053> A_IWL<40052> A_IWL<40051> A_IWL<40050> A_IWL<40049> A_IWL<40048> A_IWL<40047> A_IWL<40046> A_IWL<40045> A_IWL<40044> A_IWL<40043> A_IWL<40042> A_IWL<40041> A_IWL<40040> A_IWL<40039> A_IWL<40038> A_IWL<40037> A_IWL<40036> A_IWL<40035> A_IWL<40034> A_IWL<40033> A_IWL<40032> A_IWL<40031> A_IWL<40030> A_IWL<40029> A_IWL<40028> A_IWL<40027> A_IWL<40026> A_IWL<40025> A_IWL<40024> A_IWL<40023> A_IWL<40022> A_IWL<40021> A_IWL<40020> A_IWL<40019> A_IWL<40018> A_IWL<40017> A_IWL<40016> A_IWL<40015> A_IWL<40014> A_IWL<40013> A_IWL<40012> A_IWL<40011> A_IWL<40010> A_IWL<40009> A_IWL<40008> A_IWL<40007> A_IWL<40006> A_IWL<40005> A_IWL<40004> A_IWL<40003> A_IWL<40002> A_IWL<40001> A_IWL<40000> A_IWL<39999> A_IWL<39998> A_IWL<39997> A_IWL<39996> A_IWL<39995> A_IWL<39994> A_IWL<39993> A_IWL<39992> A_IWL<39991> A_IWL<39990> A_IWL<39989> A_IWL<39988> A_IWL<39987> A_IWL<39986> A_IWL<39985> A_IWL<39984> A_IWL<39983> A_IWL<39982> A_IWL<39981> A_IWL<39980> A_IWL<39979> A_IWL<39978> A_IWL<39977> A_IWL<39976> A_IWL<39975> A_IWL<39974> A_IWL<39973> A_IWL<39972> A_IWL<39971> A_IWL<39970> A_IWL<39969> A_IWL<39968> A_IWL<39967> A_IWL<39966> A_IWL<39965> A_IWL<39964> A_IWL<39963> A_IWL<39962> A_IWL<39961> A_IWL<39960> A_IWL<39959> A_IWL<39958> A_IWL<39957> A_IWL<39956> A_IWL<39955> A_IWL<39954> A_IWL<39953> A_IWL<39952> A_IWL<39951> A_IWL<39950> A_IWL<39949> A_IWL<39948> A_IWL<39947> A_IWL<39946> A_IWL<39945> A_IWL<39944> A_IWL<39943> A_IWL<39942> A_IWL<39941> A_IWL<39940> A_IWL<39939> A_IWL<39938> A_IWL<39937> A_IWL<39936> A_IWL<40959> A_IWL<40958> A_IWL<40957> A_IWL<40956> A_IWL<40955> A_IWL<40954> A_IWL<40953> A_IWL<40952> A_IWL<40951> A_IWL<40950> A_IWL<40949> A_IWL<40948> A_IWL<40947> A_IWL<40946> A_IWL<40945> A_IWL<40944> A_IWL<40943> A_IWL<40942> A_IWL<40941> A_IWL<40940> A_IWL<40939> A_IWL<40938> A_IWL<40937> A_IWL<40936> A_IWL<40935> A_IWL<40934> A_IWL<40933> A_IWL<40932> A_IWL<40931> A_IWL<40930> A_IWL<40929> A_IWL<40928> A_IWL<40927> A_IWL<40926> A_IWL<40925> A_IWL<40924> A_IWL<40923> A_IWL<40922> A_IWL<40921> A_IWL<40920> A_IWL<40919> A_IWL<40918> A_IWL<40917> A_IWL<40916> A_IWL<40915> A_IWL<40914> A_IWL<40913> A_IWL<40912> A_IWL<40911> A_IWL<40910> A_IWL<40909> A_IWL<40908> A_IWL<40907> A_IWL<40906> A_IWL<40905> A_IWL<40904> A_IWL<40903> A_IWL<40902> A_IWL<40901> A_IWL<40900> A_IWL<40899> A_IWL<40898> A_IWL<40897> A_IWL<40896> A_IWL<40895> A_IWL<40894> A_IWL<40893> A_IWL<40892> A_IWL<40891> A_IWL<40890> A_IWL<40889> A_IWL<40888> A_IWL<40887> A_IWL<40886> A_IWL<40885> A_IWL<40884> A_IWL<40883> A_IWL<40882> A_IWL<40881> A_IWL<40880> A_IWL<40879> A_IWL<40878> A_IWL<40877> A_IWL<40876> A_IWL<40875> A_IWL<40874> A_IWL<40873> A_IWL<40872> A_IWL<40871> A_IWL<40870> A_IWL<40869> A_IWL<40868> A_IWL<40867> A_IWL<40866> A_IWL<40865> A_IWL<40864> A_IWL<40863> A_IWL<40862> A_IWL<40861> A_IWL<40860> A_IWL<40859> A_IWL<40858> A_IWL<40857> A_IWL<40856> A_IWL<40855> A_IWL<40854> A_IWL<40853> A_IWL<40852> A_IWL<40851> A_IWL<40850> A_IWL<40849> A_IWL<40848> A_IWL<40847> A_IWL<40846> A_IWL<40845> A_IWL<40844> A_IWL<40843> A_IWL<40842> A_IWL<40841> A_IWL<40840> A_IWL<40839> A_IWL<40838> A_IWL<40837> A_IWL<40836> A_IWL<40835> A_IWL<40834> A_IWL<40833> A_IWL<40832> A_IWL<40831> A_IWL<40830> A_IWL<40829> A_IWL<40828> A_IWL<40827> A_IWL<40826> A_IWL<40825> A_IWL<40824> A_IWL<40823> A_IWL<40822> A_IWL<40821> A_IWL<40820> A_IWL<40819> A_IWL<40818> A_IWL<40817> A_IWL<40816> A_IWL<40815> A_IWL<40814> A_IWL<40813> A_IWL<40812> A_IWL<40811> A_IWL<40810> A_IWL<40809> A_IWL<40808> A_IWL<40807> A_IWL<40806> A_IWL<40805> A_IWL<40804> A_IWL<40803> A_IWL<40802> A_IWL<40801> A_IWL<40800> A_IWL<40799> A_IWL<40798> A_IWL<40797> A_IWL<40796> A_IWL<40795> A_IWL<40794> A_IWL<40793> A_IWL<40792> A_IWL<40791> A_IWL<40790> A_IWL<40789> A_IWL<40788> A_IWL<40787> A_IWL<40786> A_IWL<40785> A_IWL<40784> A_IWL<40783> A_IWL<40782> A_IWL<40781> A_IWL<40780> A_IWL<40779> A_IWL<40778> A_IWL<40777> A_IWL<40776> A_IWL<40775> A_IWL<40774> A_IWL<40773> A_IWL<40772> A_IWL<40771> A_IWL<40770> A_IWL<40769> A_IWL<40768> A_IWL<40767> A_IWL<40766> A_IWL<40765> A_IWL<40764> A_IWL<40763> A_IWL<40762> A_IWL<40761> A_IWL<40760> A_IWL<40759> A_IWL<40758> A_IWL<40757> A_IWL<40756> A_IWL<40755> A_IWL<40754> A_IWL<40753> A_IWL<40752> A_IWL<40751> A_IWL<40750> A_IWL<40749> A_IWL<40748> A_IWL<40747> A_IWL<40746> A_IWL<40745> A_IWL<40744> A_IWL<40743> A_IWL<40742> A_IWL<40741> A_IWL<40740> A_IWL<40739> A_IWL<40738> A_IWL<40737> A_IWL<40736> A_IWL<40735> A_IWL<40734> A_IWL<40733> A_IWL<40732> A_IWL<40731> A_IWL<40730> A_IWL<40729> A_IWL<40728> A_IWL<40727> A_IWL<40726> A_IWL<40725> A_IWL<40724> A_IWL<40723> A_IWL<40722> A_IWL<40721> A_IWL<40720> A_IWL<40719> A_IWL<40718> A_IWL<40717> A_IWL<40716> A_IWL<40715> A_IWL<40714> A_IWL<40713> A_IWL<40712> A_IWL<40711> A_IWL<40710> A_IWL<40709> A_IWL<40708> A_IWL<40707> A_IWL<40706> A_IWL<40705> A_IWL<40704> A_IWL<40703> A_IWL<40702> A_IWL<40701> A_IWL<40700> A_IWL<40699> A_IWL<40698> A_IWL<40697> A_IWL<40696> A_IWL<40695> A_IWL<40694> A_IWL<40693> A_IWL<40692> A_IWL<40691> A_IWL<40690> A_IWL<40689> A_IWL<40688> A_IWL<40687> A_IWL<40686> A_IWL<40685> A_IWL<40684> A_IWL<40683> A_IWL<40682> A_IWL<40681> A_IWL<40680> A_IWL<40679> A_IWL<40678> A_IWL<40677> A_IWL<40676> A_IWL<40675> A_IWL<40674> A_IWL<40673> A_IWL<40672> A_IWL<40671> A_IWL<40670> A_IWL<40669> A_IWL<40668> A_IWL<40667> A_IWL<40666> A_IWL<40665> A_IWL<40664> A_IWL<40663> A_IWL<40662> A_IWL<40661> A_IWL<40660> A_IWL<40659> A_IWL<40658> A_IWL<40657> A_IWL<40656> A_IWL<40655> A_IWL<40654> A_IWL<40653> A_IWL<40652> A_IWL<40651> A_IWL<40650> A_IWL<40649> A_IWL<40648> A_IWL<40647> A_IWL<40646> A_IWL<40645> A_IWL<40644> A_IWL<40643> A_IWL<40642> A_IWL<40641> A_IWL<40640> A_IWL<40639> A_IWL<40638> A_IWL<40637> A_IWL<40636> A_IWL<40635> A_IWL<40634> A_IWL<40633> A_IWL<40632> A_IWL<40631> A_IWL<40630> A_IWL<40629> A_IWL<40628> A_IWL<40627> A_IWL<40626> A_IWL<40625> A_IWL<40624> A_IWL<40623> A_IWL<40622> A_IWL<40621> A_IWL<40620> A_IWL<40619> A_IWL<40618> A_IWL<40617> A_IWL<40616> A_IWL<40615> A_IWL<40614> A_IWL<40613> A_IWL<40612> A_IWL<40611> A_IWL<40610> A_IWL<40609> A_IWL<40608> A_IWL<40607> A_IWL<40606> A_IWL<40605> A_IWL<40604> A_IWL<40603> A_IWL<40602> A_IWL<40601> A_IWL<40600> A_IWL<40599> A_IWL<40598> A_IWL<40597> A_IWL<40596> A_IWL<40595> A_IWL<40594> A_IWL<40593> A_IWL<40592> A_IWL<40591> A_IWL<40590> A_IWL<40589> A_IWL<40588> A_IWL<40587> A_IWL<40586> A_IWL<40585> A_IWL<40584> A_IWL<40583> A_IWL<40582> A_IWL<40581> A_IWL<40580> A_IWL<40579> A_IWL<40578> A_IWL<40577> A_IWL<40576> A_IWL<40575> A_IWL<40574> A_IWL<40573> A_IWL<40572> A_IWL<40571> A_IWL<40570> A_IWL<40569> A_IWL<40568> A_IWL<40567> A_IWL<40566> A_IWL<40565> A_IWL<40564> A_IWL<40563> A_IWL<40562> A_IWL<40561> A_IWL<40560> A_IWL<40559> A_IWL<40558> A_IWL<40557> A_IWL<40556> A_IWL<40555> A_IWL<40554> A_IWL<40553> A_IWL<40552> A_IWL<40551> A_IWL<40550> A_IWL<40549> A_IWL<40548> A_IWL<40547> A_IWL<40546> A_IWL<40545> A_IWL<40544> A_IWL<40543> A_IWL<40542> A_IWL<40541> A_IWL<40540> A_IWL<40539> A_IWL<40538> A_IWL<40537> A_IWL<40536> A_IWL<40535> A_IWL<40534> A_IWL<40533> A_IWL<40532> A_IWL<40531> A_IWL<40530> A_IWL<40529> A_IWL<40528> A_IWL<40527> A_IWL<40526> A_IWL<40525> A_IWL<40524> A_IWL<40523> A_IWL<40522> A_IWL<40521> A_IWL<40520> A_IWL<40519> A_IWL<40518> A_IWL<40517> A_IWL<40516> A_IWL<40515> A_IWL<40514> A_IWL<40513> A_IWL<40512> A_IWL<40511> A_IWL<40510> A_IWL<40509> A_IWL<40508> A_IWL<40507> A_IWL<40506> A_IWL<40505> A_IWL<40504> A_IWL<40503> A_IWL<40502> A_IWL<40501> A_IWL<40500> A_IWL<40499> A_IWL<40498> A_IWL<40497> A_IWL<40496> A_IWL<40495> A_IWL<40494> A_IWL<40493> A_IWL<40492> A_IWL<40491> A_IWL<40490> A_IWL<40489> A_IWL<40488> A_IWL<40487> A_IWL<40486> A_IWL<40485> A_IWL<40484> A_IWL<40483> A_IWL<40482> A_IWL<40481> A_IWL<40480> A_IWL<40479> A_IWL<40478> A_IWL<40477> A_IWL<40476> A_IWL<40475> A_IWL<40474> A_IWL<40473> A_IWL<40472> A_IWL<40471> A_IWL<40470> A_IWL<40469> A_IWL<40468> A_IWL<40467> A_IWL<40466> A_IWL<40465> A_IWL<40464> A_IWL<40463> A_IWL<40462> A_IWL<40461> A_IWL<40460> A_IWL<40459> A_IWL<40458> A_IWL<40457> A_IWL<40456> A_IWL<40455> A_IWL<40454> A_IWL<40453> A_IWL<40452> A_IWL<40451> A_IWL<40450> A_IWL<40449> A_IWL<40448> VDD_CORE VSS / RM_IHPSG13_8192x32_c4_1P_COLUMN_pcell_0 +XCOL<78> A_BLC<157> A_BLC<156> A_BLC_TOP<157> A_BLC_TOP<156> A_BLT<157> A_BLT<156> A_BLT_TOP<157> A_BLT_TOP<156> A_IWL<39935> A_IWL<39934> A_IWL<39933> A_IWL<39932> A_IWL<39931> A_IWL<39930> A_IWL<39929> A_IWL<39928> A_IWL<39927> A_IWL<39926> A_IWL<39925> A_IWL<39924> A_IWL<39923> A_IWL<39922> A_IWL<39921> A_IWL<39920> A_IWL<39919> A_IWL<39918> A_IWL<39917> A_IWL<39916> A_IWL<39915> A_IWL<39914> A_IWL<39913> A_IWL<39912> A_IWL<39911> A_IWL<39910> A_IWL<39909> A_IWL<39908> A_IWL<39907> A_IWL<39906> A_IWL<39905> A_IWL<39904> A_IWL<39903> A_IWL<39902> A_IWL<39901> A_IWL<39900> A_IWL<39899> A_IWL<39898> A_IWL<39897> A_IWL<39896> A_IWL<39895> A_IWL<39894> A_IWL<39893> A_IWL<39892> A_IWL<39891> A_IWL<39890> A_IWL<39889> A_IWL<39888> A_IWL<39887> A_IWL<39886> A_IWL<39885> A_IWL<39884> A_IWL<39883> A_IWL<39882> A_IWL<39881> A_IWL<39880> A_IWL<39879> A_IWL<39878> A_IWL<39877> A_IWL<39876> A_IWL<39875> A_IWL<39874> A_IWL<39873> A_IWL<39872> A_IWL<39871> A_IWL<39870> A_IWL<39869> A_IWL<39868> A_IWL<39867> A_IWL<39866> A_IWL<39865> A_IWL<39864> A_IWL<39863> A_IWL<39862> A_IWL<39861> A_IWL<39860> A_IWL<39859> A_IWL<39858> A_IWL<39857> A_IWL<39856> A_IWL<39855> A_IWL<39854> A_IWL<39853> A_IWL<39852> A_IWL<39851> A_IWL<39850> A_IWL<39849> A_IWL<39848> A_IWL<39847> A_IWL<39846> A_IWL<39845> A_IWL<39844> A_IWL<39843> A_IWL<39842> A_IWL<39841> A_IWL<39840> A_IWL<39839> A_IWL<39838> A_IWL<39837> A_IWL<39836> A_IWL<39835> A_IWL<39834> A_IWL<39833> A_IWL<39832> A_IWL<39831> A_IWL<39830> A_IWL<39829> A_IWL<39828> A_IWL<39827> A_IWL<39826> A_IWL<39825> A_IWL<39824> A_IWL<39823> A_IWL<39822> A_IWL<39821> A_IWL<39820> A_IWL<39819> A_IWL<39818> A_IWL<39817> A_IWL<39816> A_IWL<39815> A_IWL<39814> A_IWL<39813> A_IWL<39812> A_IWL<39811> A_IWL<39810> A_IWL<39809> A_IWL<39808> A_IWL<39807> A_IWL<39806> A_IWL<39805> A_IWL<39804> A_IWL<39803> A_IWL<39802> A_IWL<39801> A_IWL<39800> A_IWL<39799> A_IWL<39798> A_IWL<39797> A_IWL<39796> A_IWL<39795> A_IWL<39794> A_IWL<39793> A_IWL<39792> A_IWL<39791> A_IWL<39790> A_IWL<39789> A_IWL<39788> A_IWL<39787> A_IWL<39786> A_IWL<39785> A_IWL<39784> A_IWL<39783> A_IWL<39782> A_IWL<39781> A_IWL<39780> A_IWL<39779> A_IWL<39778> A_IWL<39777> A_IWL<39776> A_IWL<39775> A_IWL<39774> A_IWL<39773> A_IWL<39772> A_IWL<39771> A_IWL<39770> A_IWL<39769> A_IWL<39768> A_IWL<39767> A_IWL<39766> A_IWL<39765> A_IWL<39764> A_IWL<39763> A_IWL<39762> A_IWL<39761> A_IWL<39760> A_IWL<39759> A_IWL<39758> A_IWL<39757> A_IWL<39756> A_IWL<39755> A_IWL<39754> A_IWL<39753> A_IWL<39752> A_IWL<39751> A_IWL<39750> A_IWL<39749> A_IWL<39748> A_IWL<39747> A_IWL<39746> A_IWL<39745> A_IWL<39744> A_IWL<39743> A_IWL<39742> A_IWL<39741> A_IWL<39740> A_IWL<39739> A_IWL<39738> A_IWL<39737> A_IWL<39736> A_IWL<39735> A_IWL<39734> A_IWL<39733> A_IWL<39732> A_IWL<39731> A_IWL<39730> A_IWL<39729> A_IWL<39728> A_IWL<39727> A_IWL<39726> A_IWL<39725> A_IWL<39724> A_IWL<39723> A_IWL<39722> A_IWL<39721> A_IWL<39720> A_IWL<39719> A_IWL<39718> A_IWL<39717> A_IWL<39716> A_IWL<39715> A_IWL<39714> A_IWL<39713> A_IWL<39712> A_IWL<39711> A_IWL<39710> A_IWL<39709> A_IWL<39708> A_IWL<39707> A_IWL<39706> A_IWL<39705> A_IWL<39704> A_IWL<39703> A_IWL<39702> A_IWL<39701> A_IWL<39700> A_IWL<39699> A_IWL<39698> A_IWL<39697> A_IWL<39696> A_IWL<39695> A_IWL<39694> A_IWL<39693> A_IWL<39692> A_IWL<39691> A_IWL<39690> A_IWL<39689> A_IWL<39688> A_IWL<39687> A_IWL<39686> A_IWL<39685> A_IWL<39684> A_IWL<39683> A_IWL<39682> A_IWL<39681> A_IWL<39680> A_IWL<39679> A_IWL<39678> A_IWL<39677> A_IWL<39676> A_IWL<39675> A_IWL<39674> A_IWL<39673> A_IWL<39672> A_IWL<39671> A_IWL<39670> A_IWL<39669> A_IWL<39668> A_IWL<39667> A_IWL<39666> A_IWL<39665> A_IWL<39664> A_IWL<39663> A_IWL<39662> A_IWL<39661> A_IWL<39660> A_IWL<39659> A_IWL<39658> A_IWL<39657> A_IWL<39656> A_IWL<39655> A_IWL<39654> A_IWL<39653> A_IWL<39652> A_IWL<39651> A_IWL<39650> A_IWL<39649> A_IWL<39648> A_IWL<39647> A_IWL<39646> A_IWL<39645> A_IWL<39644> A_IWL<39643> A_IWL<39642> A_IWL<39641> A_IWL<39640> A_IWL<39639> A_IWL<39638> A_IWL<39637> A_IWL<39636> A_IWL<39635> A_IWL<39634> A_IWL<39633> A_IWL<39632> A_IWL<39631> A_IWL<39630> A_IWL<39629> A_IWL<39628> A_IWL<39627> A_IWL<39626> A_IWL<39625> A_IWL<39624> A_IWL<39623> A_IWL<39622> A_IWL<39621> A_IWL<39620> A_IWL<39619> A_IWL<39618> A_IWL<39617> A_IWL<39616> A_IWL<39615> A_IWL<39614> A_IWL<39613> A_IWL<39612> A_IWL<39611> A_IWL<39610> A_IWL<39609> A_IWL<39608> A_IWL<39607> A_IWL<39606> A_IWL<39605> A_IWL<39604> A_IWL<39603> A_IWL<39602> A_IWL<39601> A_IWL<39600> A_IWL<39599> A_IWL<39598> A_IWL<39597> A_IWL<39596> A_IWL<39595> A_IWL<39594> A_IWL<39593> A_IWL<39592> A_IWL<39591> A_IWL<39590> A_IWL<39589> A_IWL<39588> A_IWL<39587> A_IWL<39586> A_IWL<39585> A_IWL<39584> A_IWL<39583> A_IWL<39582> A_IWL<39581> A_IWL<39580> A_IWL<39579> A_IWL<39578> A_IWL<39577> A_IWL<39576> A_IWL<39575> A_IWL<39574> A_IWL<39573> A_IWL<39572> A_IWL<39571> A_IWL<39570> A_IWL<39569> A_IWL<39568> A_IWL<39567> A_IWL<39566> A_IWL<39565> A_IWL<39564> A_IWL<39563> A_IWL<39562> A_IWL<39561> A_IWL<39560> A_IWL<39559> A_IWL<39558> A_IWL<39557> A_IWL<39556> A_IWL<39555> A_IWL<39554> A_IWL<39553> A_IWL<39552> A_IWL<39551> A_IWL<39550> A_IWL<39549> A_IWL<39548> A_IWL<39547> A_IWL<39546> A_IWL<39545> A_IWL<39544> A_IWL<39543> A_IWL<39542> A_IWL<39541> A_IWL<39540> A_IWL<39539> A_IWL<39538> A_IWL<39537> A_IWL<39536> A_IWL<39535> A_IWL<39534> A_IWL<39533> A_IWL<39532> A_IWL<39531> A_IWL<39530> A_IWL<39529> A_IWL<39528> A_IWL<39527> A_IWL<39526> A_IWL<39525> A_IWL<39524> A_IWL<39523> A_IWL<39522> A_IWL<39521> A_IWL<39520> A_IWL<39519> A_IWL<39518> A_IWL<39517> A_IWL<39516> A_IWL<39515> A_IWL<39514> A_IWL<39513> A_IWL<39512> A_IWL<39511> A_IWL<39510> A_IWL<39509> A_IWL<39508> A_IWL<39507> A_IWL<39506> A_IWL<39505> A_IWL<39504> A_IWL<39503> A_IWL<39502> A_IWL<39501> A_IWL<39500> A_IWL<39499> A_IWL<39498> A_IWL<39497> A_IWL<39496> A_IWL<39495> A_IWL<39494> A_IWL<39493> A_IWL<39492> A_IWL<39491> A_IWL<39490> A_IWL<39489> A_IWL<39488> A_IWL<39487> A_IWL<39486> A_IWL<39485> A_IWL<39484> A_IWL<39483> A_IWL<39482> A_IWL<39481> A_IWL<39480> A_IWL<39479> A_IWL<39478> A_IWL<39477> A_IWL<39476> A_IWL<39475> A_IWL<39474> A_IWL<39473> A_IWL<39472> A_IWL<39471> A_IWL<39470> A_IWL<39469> A_IWL<39468> A_IWL<39467> A_IWL<39466> A_IWL<39465> A_IWL<39464> A_IWL<39463> A_IWL<39462> A_IWL<39461> A_IWL<39460> A_IWL<39459> A_IWL<39458> A_IWL<39457> A_IWL<39456> A_IWL<39455> A_IWL<39454> A_IWL<39453> A_IWL<39452> A_IWL<39451> A_IWL<39450> A_IWL<39449> A_IWL<39448> A_IWL<39447> A_IWL<39446> A_IWL<39445> A_IWL<39444> A_IWL<39443> A_IWL<39442> A_IWL<39441> A_IWL<39440> A_IWL<39439> A_IWL<39438> A_IWL<39437> A_IWL<39436> A_IWL<39435> A_IWL<39434> A_IWL<39433> A_IWL<39432> A_IWL<39431> A_IWL<39430> A_IWL<39429> A_IWL<39428> A_IWL<39427> A_IWL<39426> A_IWL<39425> A_IWL<39424> A_IWL<40447> A_IWL<40446> A_IWL<40445> A_IWL<40444> A_IWL<40443> A_IWL<40442> A_IWL<40441> A_IWL<40440> A_IWL<40439> A_IWL<40438> A_IWL<40437> A_IWL<40436> A_IWL<40435> A_IWL<40434> A_IWL<40433> A_IWL<40432> A_IWL<40431> A_IWL<40430> A_IWL<40429> A_IWL<40428> A_IWL<40427> A_IWL<40426> A_IWL<40425> A_IWL<40424> A_IWL<40423> A_IWL<40422> A_IWL<40421> A_IWL<40420> A_IWL<40419> A_IWL<40418> A_IWL<40417> A_IWL<40416> A_IWL<40415> A_IWL<40414> A_IWL<40413> A_IWL<40412> A_IWL<40411> A_IWL<40410> A_IWL<40409> A_IWL<40408> A_IWL<40407> A_IWL<40406> A_IWL<40405> A_IWL<40404> A_IWL<40403> A_IWL<40402> A_IWL<40401> A_IWL<40400> A_IWL<40399> A_IWL<40398> A_IWL<40397> A_IWL<40396> A_IWL<40395> A_IWL<40394> A_IWL<40393> A_IWL<40392> A_IWL<40391> A_IWL<40390> A_IWL<40389> A_IWL<40388> A_IWL<40387> A_IWL<40386> A_IWL<40385> A_IWL<40384> A_IWL<40383> A_IWL<40382> A_IWL<40381> A_IWL<40380> A_IWL<40379> A_IWL<40378> A_IWL<40377> A_IWL<40376> A_IWL<40375> A_IWL<40374> A_IWL<40373> A_IWL<40372> A_IWL<40371> A_IWL<40370> A_IWL<40369> A_IWL<40368> A_IWL<40367> A_IWL<40366> A_IWL<40365> A_IWL<40364> A_IWL<40363> A_IWL<40362> A_IWL<40361> A_IWL<40360> A_IWL<40359> A_IWL<40358> A_IWL<40357> A_IWL<40356> A_IWL<40355> A_IWL<40354> A_IWL<40353> A_IWL<40352> A_IWL<40351> A_IWL<40350> A_IWL<40349> A_IWL<40348> A_IWL<40347> A_IWL<40346> A_IWL<40345> A_IWL<40344> A_IWL<40343> A_IWL<40342> A_IWL<40341> A_IWL<40340> A_IWL<40339> A_IWL<40338> A_IWL<40337> A_IWL<40336> A_IWL<40335> A_IWL<40334> A_IWL<40333> A_IWL<40332> A_IWL<40331> A_IWL<40330> A_IWL<40329> A_IWL<40328> A_IWL<40327> A_IWL<40326> A_IWL<40325> A_IWL<40324> A_IWL<40323> A_IWL<40322> A_IWL<40321> A_IWL<40320> A_IWL<40319> A_IWL<40318> A_IWL<40317> A_IWL<40316> A_IWL<40315> A_IWL<40314> A_IWL<40313> A_IWL<40312> A_IWL<40311> A_IWL<40310> A_IWL<40309> A_IWL<40308> A_IWL<40307> A_IWL<40306> A_IWL<40305> A_IWL<40304> A_IWL<40303> A_IWL<40302> A_IWL<40301> A_IWL<40300> A_IWL<40299> A_IWL<40298> A_IWL<40297> A_IWL<40296> A_IWL<40295> A_IWL<40294> A_IWL<40293> A_IWL<40292> A_IWL<40291> A_IWL<40290> A_IWL<40289> A_IWL<40288> A_IWL<40287> A_IWL<40286> A_IWL<40285> A_IWL<40284> A_IWL<40283> A_IWL<40282> A_IWL<40281> A_IWL<40280> A_IWL<40279> A_IWL<40278> A_IWL<40277> A_IWL<40276> A_IWL<40275> A_IWL<40274> A_IWL<40273> A_IWL<40272> A_IWL<40271> A_IWL<40270> A_IWL<40269> A_IWL<40268> A_IWL<40267> A_IWL<40266> A_IWL<40265> A_IWL<40264> A_IWL<40263> A_IWL<40262> A_IWL<40261> A_IWL<40260> A_IWL<40259> A_IWL<40258> A_IWL<40257> A_IWL<40256> A_IWL<40255> A_IWL<40254> A_IWL<40253> A_IWL<40252> A_IWL<40251> A_IWL<40250> A_IWL<40249> A_IWL<40248> A_IWL<40247> A_IWL<40246> A_IWL<40245> A_IWL<40244> A_IWL<40243> A_IWL<40242> A_IWL<40241> A_IWL<40240> A_IWL<40239> A_IWL<40238> A_IWL<40237> A_IWL<40236> A_IWL<40235> A_IWL<40234> A_IWL<40233> A_IWL<40232> A_IWL<40231> A_IWL<40230> A_IWL<40229> A_IWL<40228> A_IWL<40227> A_IWL<40226> A_IWL<40225> A_IWL<40224> A_IWL<40223> A_IWL<40222> A_IWL<40221> A_IWL<40220> A_IWL<40219> A_IWL<40218> A_IWL<40217> A_IWL<40216> A_IWL<40215> A_IWL<40214> A_IWL<40213> A_IWL<40212> A_IWL<40211> A_IWL<40210> A_IWL<40209> A_IWL<40208> A_IWL<40207> A_IWL<40206> A_IWL<40205> A_IWL<40204> A_IWL<40203> A_IWL<40202> A_IWL<40201> A_IWL<40200> A_IWL<40199> A_IWL<40198> A_IWL<40197> A_IWL<40196> A_IWL<40195> A_IWL<40194> A_IWL<40193> A_IWL<40192> A_IWL<40191> A_IWL<40190> A_IWL<40189> A_IWL<40188> A_IWL<40187> A_IWL<40186> A_IWL<40185> A_IWL<40184> A_IWL<40183> A_IWL<40182> A_IWL<40181> A_IWL<40180> A_IWL<40179> A_IWL<40178> A_IWL<40177> A_IWL<40176> A_IWL<40175> A_IWL<40174> A_IWL<40173> A_IWL<40172> A_IWL<40171> A_IWL<40170> A_IWL<40169> A_IWL<40168> A_IWL<40167> A_IWL<40166> A_IWL<40165> A_IWL<40164> A_IWL<40163> A_IWL<40162> A_IWL<40161> A_IWL<40160> A_IWL<40159> A_IWL<40158> A_IWL<40157> A_IWL<40156> A_IWL<40155> A_IWL<40154> A_IWL<40153> A_IWL<40152> A_IWL<40151> A_IWL<40150> A_IWL<40149> A_IWL<40148> A_IWL<40147> A_IWL<40146> A_IWL<40145> A_IWL<40144> A_IWL<40143> A_IWL<40142> A_IWL<40141> A_IWL<40140> A_IWL<40139> A_IWL<40138> A_IWL<40137> A_IWL<40136> A_IWL<40135> A_IWL<40134> A_IWL<40133> A_IWL<40132> A_IWL<40131> A_IWL<40130> A_IWL<40129> A_IWL<40128> A_IWL<40127> A_IWL<40126> A_IWL<40125> A_IWL<40124> A_IWL<40123> A_IWL<40122> A_IWL<40121> A_IWL<40120> A_IWL<40119> A_IWL<40118> A_IWL<40117> A_IWL<40116> A_IWL<40115> A_IWL<40114> A_IWL<40113> A_IWL<40112> A_IWL<40111> A_IWL<40110> A_IWL<40109> A_IWL<40108> A_IWL<40107> A_IWL<40106> A_IWL<40105> A_IWL<40104> A_IWL<40103> A_IWL<40102> A_IWL<40101> A_IWL<40100> A_IWL<40099> A_IWL<40098> A_IWL<40097> A_IWL<40096> A_IWL<40095> A_IWL<40094> A_IWL<40093> A_IWL<40092> A_IWL<40091> A_IWL<40090> A_IWL<40089> A_IWL<40088> A_IWL<40087> A_IWL<40086> A_IWL<40085> A_IWL<40084> A_IWL<40083> A_IWL<40082> A_IWL<40081> A_IWL<40080> A_IWL<40079> A_IWL<40078> A_IWL<40077> A_IWL<40076> A_IWL<40075> A_IWL<40074> A_IWL<40073> A_IWL<40072> A_IWL<40071> A_IWL<40070> A_IWL<40069> A_IWL<40068> A_IWL<40067> A_IWL<40066> A_IWL<40065> A_IWL<40064> A_IWL<40063> A_IWL<40062> A_IWL<40061> A_IWL<40060> A_IWL<40059> A_IWL<40058> A_IWL<40057> A_IWL<40056> A_IWL<40055> A_IWL<40054> A_IWL<40053> A_IWL<40052> A_IWL<40051> A_IWL<40050> A_IWL<40049> A_IWL<40048> A_IWL<40047> A_IWL<40046> A_IWL<40045> A_IWL<40044> A_IWL<40043> A_IWL<40042> A_IWL<40041> A_IWL<40040> A_IWL<40039> A_IWL<40038> A_IWL<40037> A_IWL<40036> A_IWL<40035> A_IWL<40034> A_IWL<40033> A_IWL<40032> A_IWL<40031> A_IWL<40030> A_IWL<40029> A_IWL<40028> A_IWL<40027> A_IWL<40026> A_IWL<40025> A_IWL<40024> A_IWL<40023> A_IWL<40022> A_IWL<40021> A_IWL<40020> A_IWL<40019> A_IWL<40018> A_IWL<40017> A_IWL<40016> A_IWL<40015> A_IWL<40014> A_IWL<40013> A_IWL<40012> A_IWL<40011> A_IWL<40010> A_IWL<40009> A_IWL<40008> A_IWL<40007> A_IWL<40006> A_IWL<40005> A_IWL<40004> A_IWL<40003> A_IWL<40002> A_IWL<40001> A_IWL<40000> A_IWL<39999> A_IWL<39998> A_IWL<39997> A_IWL<39996> A_IWL<39995> A_IWL<39994> A_IWL<39993> A_IWL<39992> A_IWL<39991> A_IWL<39990> A_IWL<39989> A_IWL<39988> A_IWL<39987> A_IWL<39986> A_IWL<39985> A_IWL<39984> A_IWL<39983> A_IWL<39982> A_IWL<39981> A_IWL<39980> A_IWL<39979> A_IWL<39978> A_IWL<39977> A_IWL<39976> A_IWL<39975> A_IWL<39974> A_IWL<39973> A_IWL<39972> A_IWL<39971> A_IWL<39970> A_IWL<39969> A_IWL<39968> A_IWL<39967> A_IWL<39966> A_IWL<39965> A_IWL<39964> A_IWL<39963> A_IWL<39962> A_IWL<39961> A_IWL<39960> A_IWL<39959> A_IWL<39958> A_IWL<39957> A_IWL<39956> A_IWL<39955> A_IWL<39954> A_IWL<39953> A_IWL<39952> A_IWL<39951> A_IWL<39950> A_IWL<39949> A_IWL<39948> A_IWL<39947> A_IWL<39946> A_IWL<39945> A_IWL<39944> A_IWL<39943> A_IWL<39942> A_IWL<39941> A_IWL<39940> A_IWL<39939> A_IWL<39938> A_IWL<39937> A_IWL<39936> VDD_CORE VSS / RM_IHPSG13_8192x32_c4_1P_COLUMN_pcell_0 +XCOL<77> A_BLC<155> A_BLC<154> A_BLC_TOP<155> A_BLC_TOP<154> A_BLT<155> A_BLT<154> A_BLT_TOP<155> A_BLT_TOP<154> A_IWL<39423> A_IWL<39422> A_IWL<39421> A_IWL<39420> A_IWL<39419> A_IWL<39418> A_IWL<39417> A_IWL<39416> A_IWL<39415> A_IWL<39414> A_IWL<39413> A_IWL<39412> A_IWL<39411> A_IWL<39410> A_IWL<39409> A_IWL<39408> A_IWL<39407> A_IWL<39406> A_IWL<39405> A_IWL<39404> A_IWL<39403> A_IWL<39402> A_IWL<39401> A_IWL<39400> A_IWL<39399> A_IWL<39398> A_IWL<39397> A_IWL<39396> A_IWL<39395> A_IWL<39394> A_IWL<39393> A_IWL<39392> A_IWL<39391> A_IWL<39390> A_IWL<39389> A_IWL<39388> A_IWL<39387> A_IWL<39386> A_IWL<39385> A_IWL<39384> A_IWL<39383> A_IWL<39382> A_IWL<39381> A_IWL<39380> A_IWL<39379> A_IWL<39378> A_IWL<39377> A_IWL<39376> A_IWL<39375> A_IWL<39374> A_IWL<39373> A_IWL<39372> A_IWL<39371> A_IWL<39370> A_IWL<39369> A_IWL<39368> A_IWL<39367> A_IWL<39366> A_IWL<39365> A_IWL<39364> A_IWL<39363> A_IWL<39362> A_IWL<39361> A_IWL<39360> A_IWL<39359> A_IWL<39358> A_IWL<39357> A_IWL<39356> A_IWL<39355> A_IWL<39354> A_IWL<39353> A_IWL<39352> A_IWL<39351> A_IWL<39350> A_IWL<39349> A_IWL<39348> A_IWL<39347> A_IWL<39346> A_IWL<39345> A_IWL<39344> A_IWL<39343> A_IWL<39342> A_IWL<39341> A_IWL<39340> A_IWL<39339> A_IWL<39338> A_IWL<39337> A_IWL<39336> A_IWL<39335> A_IWL<39334> A_IWL<39333> A_IWL<39332> A_IWL<39331> A_IWL<39330> A_IWL<39329> A_IWL<39328> A_IWL<39327> A_IWL<39326> A_IWL<39325> A_IWL<39324> A_IWL<39323> A_IWL<39322> A_IWL<39321> A_IWL<39320> A_IWL<39319> A_IWL<39318> A_IWL<39317> A_IWL<39316> A_IWL<39315> A_IWL<39314> A_IWL<39313> A_IWL<39312> A_IWL<39311> A_IWL<39310> A_IWL<39309> A_IWL<39308> A_IWL<39307> A_IWL<39306> A_IWL<39305> A_IWL<39304> A_IWL<39303> A_IWL<39302> A_IWL<39301> A_IWL<39300> A_IWL<39299> A_IWL<39298> A_IWL<39297> A_IWL<39296> A_IWL<39295> A_IWL<39294> A_IWL<39293> A_IWL<39292> A_IWL<39291> A_IWL<39290> A_IWL<39289> A_IWL<39288> A_IWL<39287> A_IWL<39286> A_IWL<39285> A_IWL<39284> A_IWL<39283> A_IWL<39282> A_IWL<39281> A_IWL<39280> A_IWL<39279> A_IWL<39278> A_IWL<39277> A_IWL<39276> A_IWL<39275> A_IWL<39274> A_IWL<39273> A_IWL<39272> A_IWL<39271> A_IWL<39270> A_IWL<39269> A_IWL<39268> A_IWL<39267> A_IWL<39266> A_IWL<39265> A_IWL<39264> A_IWL<39263> A_IWL<39262> A_IWL<39261> A_IWL<39260> A_IWL<39259> A_IWL<39258> A_IWL<39257> A_IWL<39256> A_IWL<39255> A_IWL<39254> A_IWL<39253> A_IWL<39252> A_IWL<39251> A_IWL<39250> A_IWL<39249> A_IWL<39248> A_IWL<39247> A_IWL<39246> A_IWL<39245> A_IWL<39244> A_IWL<39243> A_IWL<39242> A_IWL<39241> A_IWL<39240> A_IWL<39239> A_IWL<39238> A_IWL<39237> A_IWL<39236> A_IWL<39235> A_IWL<39234> A_IWL<39233> A_IWL<39232> A_IWL<39231> A_IWL<39230> A_IWL<39229> A_IWL<39228> A_IWL<39227> A_IWL<39226> A_IWL<39225> A_IWL<39224> A_IWL<39223> A_IWL<39222> A_IWL<39221> A_IWL<39220> A_IWL<39219> A_IWL<39218> A_IWL<39217> A_IWL<39216> A_IWL<39215> A_IWL<39214> A_IWL<39213> A_IWL<39212> A_IWL<39211> A_IWL<39210> A_IWL<39209> A_IWL<39208> A_IWL<39207> A_IWL<39206> A_IWL<39205> A_IWL<39204> A_IWL<39203> A_IWL<39202> A_IWL<39201> A_IWL<39200> A_IWL<39199> A_IWL<39198> A_IWL<39197> A_IWL<39196> A_IWL<39195> A_IWL<39194> A_IWL<39193> A_IWL<39192> A_IWL<39191> A_IWL<39190> A_IWL<39189> A_IWL<39188> A_IWL<39187> A_IWL<39186> A_IWL<39185> A_IWL<39184> A_IWL<39183> A_IWL<39182> A_IWL<39181> A_IWL<39180> A_IWL<39179> A_IWL<39178> A_IWL<39177> A_IWL<39176> A_IWL<39175> A_IWL<39174> A_IWL<39173> A_IWL<39172> A_IWL<39171> A_IWL<39170> A_IWL<39169> A_IWL<39168> A_IWL<39167> A_IWL<39166> A_IWL<39165> A_IWL<39164> A_IWL<39163> A_IWL<39162> A_IWL<39161> A_IWL<39160> A_IWL<39159> A_IWL<39158> A_IWL<39157> A_IWL<39156> A_IWL<39155> A_IWL<39154> A_IWL<39153> A_IWL<39152> A_IWL<39151> A_IWL<39150> A_IWL<39149> A_IWL<39148> A_IWL<39147> A_IWL<39146> A_IWL<39145> A_IWL<39144> A_IWL<39143> A_IWL<39142> A_IWL<39141> A_IWL<39140> A_IWL<39139> A_IWL<39138> A_IWL<39137> A_IWL<39136> A_IWL<39135> A_IWL<39134> A_IWL<39133> A_IWL<39132> A_IWL<39131> A_IWL<39130> A_IWL<39129> A_IWL<39128> A_IWL<39127> A_IWL<39126> A_IWL<39125> A_IWL<39124> A_IWL<39123> A_IWL<39122> A_IWL<39121> A_IWL<39120> A_IWL<39119> A_IWL<39118> A_IWL<39117> A_IWL<39116> A_IWL<39115> A_IWL<39114> A_IWL<39113> A_IWL<39112> A_IWL<39111> A_IWL<39110> A_IWL<39109> A_IWL<39108> A_IWL<39107> A_IWL<39106> A_IWL<39105> A_IWL<39104> A_IWL<39103> A_IWL<39102> A_IWL<39101> A_IWL<39100> A_IWL<39099> A_IWL<39098> A_IWL<39097> A_IWL<39096> A_IWL<39095> A_IWL<39094> A_IWL<39093> A_IWL<39092> A_IWL<39091> A_IWL<39090> A_IWL<39089> A_IWL<39088> A_IWL<39087> A_IWL<39086> A_IWL<39085> A_IWL<39084> A_IWL<39083> A_IWL<39082> A_IWL<39081> A_IWL<39080> A_IWL<39079> A_IWL<39078> A_IWL<39077> A_IWL<39076> A_IWL<39075> A_IWL<39074> A_IWL<39073> A_IWL<39072> A_IWL<39071> A_IWL<39070> A_IWL<39069> A_IWL<39068> A_IWL<39067> A_IWL<39066> A_IWL<39065> A_IWL<39064> A_IWL<39063> A_IWL<39062> A_IWL<39061> A_IWL<39060> A_IWL<39059> A_IWL<39058> A_IWL<39057> A_IWL<39056> A_IWL<39055> A_IWL<39054> A_IWL<39053> A_IWL<39052> A_IWL<39051> A_IWL<39050> A_IWL<39049> A_IWL<39048> A_IWL<39047> A_IWL<39046> A_IWL<39045> A_IWL<39044> A_IWL<39043> A_IWL<39042> A_IWL<39041> A_IWL<39040> A_IWL<39039> A_IWL<39038> A_IWL<39037> A_IWL<39036> A_IWL<39035> A_IWL<39034> A_IWL<39033> A_IWL<39032> A_IWL<39031> A_IWL<39030> A_IWL<39029> A_IWL<39028> A_IWL<39027> A_IWL<39026> A_IWL<39025> A_IWL<39024> A_IWL<39023> A_IWL<39022> A_IWL<39021> A_IWL<39020> A_IWL<39019> A_IWL<39018> A_IWL<39017> A_IWL<39016> A_IWL<39015> A_IWL<39014> A_IWL<39013> A_IWL<39012> A_IWL<39011> A_IWL<39010> A_IWL<39009> A_IWL<39008> A_IWL<39007> A_IWL<39006> A_IWL<39005> A_IWL<39004> A_IWL<39003> A_IWL<39002> A_IWL<39001> A_IWL<39000> A_IWL<38999> A_IWL<38998> A_IWL<38997> A_IWL<38996> A_IWL<38995> A_IWL<38994> A_IWL<38993> A_IWL<38992> A_IWL<38991> A_IWL<38990> A_IWL<38989> A_IWL<38988> A_IWL<38987> A_IWL<38986> A_IWL<38985> A_IWL<38984> A_IWL<38983> A_IWL<38982> A_IWL<38981> A_IWL<38980> A_IWL<38979> A_IWL<38978> A_IWL<38977> A_IWL<38976> A_IWL<38975> A_IWL<38974> A_IWL<38973> A_IWL<38972> A_IWL<38971> A_IWL<38970> A_IWL<38969> A_IWL<38968> A_IWL<38967> A_IWL<38966> A_IWL<38965> A_IWL<38964> A_IWL<38963> A_IWL<38962> A_IWL<38961> A_IWL<38960> A_IWL<38959> A_IWL<38958> A_IWL<38957> A_IWL<38956> A_IWL<38955> A_IWL<38954> A_IWL<38953> A_IWL<38952> A_IWL<38951> A_IWL<38950> A_IWL<38949> A_IWL<38948> A_IWL<38947> A_IWL<38946> A_IWL<38945> A_IWL<38944> A_IWL<38943> A_IWL<38942> A_IWL<38941> A_IWL<38940> A_IWL<38939> A_IWL<38938> A_IWL<38937> A_IWL<38936> A_IWL<38935> A_IWL<38934> A_IWL<38933> A_IWL<38932> A_IWL<38931> A_IWL<38930> A_IWL<38929> A_IWL<38928> A_IWL<38927> A_IWL<38926> A_IWL<38925> A_IWL<38924> A_IWL<38923> A_IWL<38922> A_IWL<38921> A_IWL<38920> A_IWL<38919> A_IWL<38918> A_IWL<38917> A_IWL<38916> A_IWL<38915> A_IWL<38914> A_IWL<38913> A_IWL<38912> A_IWL<39935> A_IWL<39934> A_IWL<39933> A_IWL<39932> A_IWL<39931> A_IWL<39930> A_IWL<39929> A_IWL<39928> A_IWL<39927> A_IWL<39926> A_IWL<39925> A_IWL<39924> A_IWL<39923> A_IWL<39922> A_IWL<39921> A_IWL<39920> A_IWL<39919> A_IWL<39918> A_IWL<39917> A_IWL<39916> A_IWL<39915> A_IWL<39914> A_IWL<39913> A_IWL<39912> A_IWL<39911> A_IWL<39910> A_IWL<39909> A_IWL<39908> A_IWL<39907> A_IWL<39906> A_IWL<39905> A_IWL<39904> A_IWL<39903> A_IWL<39902> A_IWL<39901> A_IWL<39900> A_IWL<39899> A_IWL<39898> A_IWL<39897> A_IWL<39896> A_IWL<39895> A_IWL<39894> A_IWL<39893> A_IWL<39892> A_IWL<39891> A_IWL<39890> A_IWL<39889> A_IWL<39888> A_IWL<39887> A_IWL<39886> A_IWL<39885> A_IWL<39884> A_IWL<39883> A_IWL<39882> A_IWL<39881> A_IWL<39880> A_IWL<39879> A_IWL<39878> A_IWL<39877> A_IWL<39876> A_IWL<39875> A_IWL<39874> A_IWL<39873> A_IWL<39872> A_IWL<39871> A_IWL<39870> A_IWL<39869> A_IWL<39868> A_IWL<39867> A_IWL<39866> A_IWL<39865> A_IWL<39864> A_IWL<39863> A_IWL<39862> A_IWL<39861> A_IWL<39860> A_IWL<39859> A_IWL<39858> A_IWL<39857> A_IWL<39856> A_IWL<39855> A_IWL<39854> A_IWL<39853> A_IWL<39852> A_IWL<39851> A_IWL<39850> A_IWL<39849> A_IWL<39848> A_IWL<39847> A_IWL<39846> A_IWL<39845> A_IWL<39844> A_IWL<39843> A_IWL<39842> A_IWL<39841> A_IWL<39840> A_IWL<39839> A_IWL<39838> A_IWL<39837> A_IWL<39836> A_IWL<39835> A_IWL<39834> A_IWL<39833> A_IWL<39832> A_IWL<39831> A_IWL<39830> A_IWL<39829> A_IWL<39828> A_IWL<39827> A_IWL<39826> A_IWL<39825> A_IWL<39824> A_IWL<39823> A_IWL<39822> A_IWL<39821> A_IWL<39820> A_IWL<39819> A_IWL<39818> A_IWL<39817> A_IWL<39816> A_IWL<39815> A_IWL<39814> A_IWL<39813> A_IWL<39812> A_IWL<39811> A_IWL<39810> A_IWL<39809> A_IWL<39808> A_IWL<39807> A_IWL<39806> A_IWL<39805> A_IWL<39804> A_IWL<39803> A_IWL<39802> A_IWL<39801> A_IWL<39800> A_IWL<39799> A_IWL<39798> A_IWL<39797> A_IWL<39796> A_IWL<39795> A_IWL<39794> A_IWL<39793> A_IWL<39792> A_IWL<39791> A_IWL<39790> A_IWL<39789> A_IWL<39788> A_IWL<39787> A_IWL<39786> A_IWL<39785> A_IWL<39784> A_IWL<39783> A_IWL<39782> A_IWL<39781> A_IWL<39780> A_IWL<39779> A_IWL<39778> A_IWL<39777> A_IWL<39776> A_IWL<39775> A_IWL<39774> A_IWL<39773> A_IWL<39772> A_IWL<39771> A_IWL<39770> A_IWL<39769> A_IWL<39768> A_IWL<39767> A_IWL<39766> A_IWL<39765> A_IWL<39764> A_IWL<39763> A_IWL<39762> A_IWL<39761> A_IWL<39760> A_IWL<39759> A_IWL<39758> A_IWL<39757> A_IWL<39756> A_IWL<39755> A_IWL<39754> A_IWL<39753> A_IWL<39752> A_IWL<39751> A_IWL<39750> A_IWL<39749> A_IWL<39748> A_IWL<39747> A_IWL<39746> A_IWL<39745> A_IWL<39744> A_IWL<39743> A_IWL<39742> A_IWL<39741> A_IWL<39740> A_IWL<39739> A_IWL<39738> A_IWL<39737> A_IWL<39736> A_IWL<39735> A_IWL<39734> A_IWL<39733> A_IWL<39732> A_IWL<39731> A_IWL<39730> A_IWL<39729> A_IWL<39728> A_IWL<39727> A_IWL<39726> A_IWL<39725> A_IWL<39724> A_IWL<39723> A_IWL<39722> A_IWL<39721> A_IWL<39720> A_IWL<39719> A_IWL<39718> A_IWL<39717> A_IWL<39716> A_IWL<39715> A_IWL<39714> A_IWL<39713> A_IWL<39712> A_IWL<39711> A_IWL<39710> A_IWL<39709> A_IWL<39708> A_IWL<39707> A_IWL<39706> A_IWL<39705> A_IWL<39704> A_IWL<39703> A_IWL<39702> A_IWL<39701> A_IWL<39700> A_IWL<39699> A_IWL<39698> A_IWL<39697> A_IWL<39696> A_IWL<39695> A_IWL<39694> A_IWL<39693> A_IWL<39692> A_IWL<39691> A_IWL<39690> A_IWL<39689> A_IWL<39688> A_IWL<39687> A_IWL<39686> A_IWL<39685> A_IWL<39684> A_IWL<39683> A_IWL<39682> A_IWL<39681> A_IWL<39680> A_IWL<39679> A_IWL<39678> A_IWL<39677> A_IWL<39676> A_IWL<39675> A_IWL<39674> A_IWL<39673> A_IWL<39672> A_IWL<39671> A_IWL<39670> A_IWL<39669> A_IWL<39668> A_IWL<39667> A_IWL<39666> A_IWL<39665> A_IWL<39664> A_IWL<39663> A_IWL<39662> A_IWL<39661> A_IWL<39660> A_IWL<39659> A_IWL<39658> A_IWL<39657> A_IWL<39656> A_IWL<39655> A_IWL<39654> A_IWL<39653> A_IWL<39652> A_IWL<39651> A_IWL<39650> A_IWL<39649> A_IWL<39648> A_IWL<39647> A_IWL<39646> A_IWL<39645> A_IWL<39644> A_IWL<39643> A_IWL<39642> A_IWL<39641> A_IWL<39640> A_IWL<39639> A_IWL<39638> A_IWL<39637> A_IWL<39636> A_IWL<39635> A_IWL<39634> A_IWL<39633> A_IWL<39632> A_IWL<39631> A_IWL<39630> A_IWL<39629> A_IWL<39628> A_IWL<39627> A_IWL<39626> A_IWL<39625> A_IWL<39624> A_IWL<39623> A_IWL<39622> A_IWL<39621> A_IWL<39620> A_IWL<39619> A_IWL<39618> A_IWL<39617> A_IWL<39616> A_IWL<39615> A_IWL<39614> A_IWL<39613> A_IWL<39612> A_IWL<39611> A_IWL<39610> A_IWL<39609> A_IWL<39608> A_IWL<39607> A_IWL<39606> A_IWL<39605> A_IWL<39604> A_IWL<39603> A_IWL<39602> A_IWL<39601> A_IWL<39600> A_IWL<39599> A_IWL<39598> A_IWL<39597> A_IWL<39596> A_IWL<39595> A_IWL<39594> A_IWL<39593> A_IWL<39592> A_IWL<39591> A_IWL<39590> A_IWL<39589> A_IWL<39588> A_IWL<39587> A_IWL<39586> A_IWL<39585> A_IWL<39584> A_IWL<39583> A_IWL<39582> A_IWL<39581> A_IWL<39580> A_IWL<39579> A_IWL<39578> A_IWL<39577> A_IWL<39576> A_IWL<39575> A_IWL<39574> A_IWL<39573> A_IWL<39572> A_IWL<39571> A_IWL<39570> A_IWL<39569> A_IWL<39568> A_IWL<39567> A_IWL<39566> A_IWL<39565> A_IWL<39564> A_IWL<39563> A_IWL<39562> A_IWL<39561> A_IWL<39560> A_IWL<39559> A_IWL<39558> A_IWL<39557> A_IWL<39556> A_IWL<39555> A_IWL<39554> A_IWL<39553> A_IWL<39552> A_IWL<39551> A_IWL<39550> A_IWL<39549> A_IWL<39548> A_IWL<39547> A_IWL<39546> A_IWL<39545> A_IWL<39544> A_IWL<39543> A_IWL<39542> A_IWL<39541> A_IWL<39540> A_IWL<39539> A_IWL<39538> A_IWL<39537> A_IWL<39536> A_IWL<39535> A_IWL<39534> A_IWL<39533> A_IWL<39532> A_IWL<39531> A_IWL<39530> A_IWL<39529> A_IWL<39528> A_IWL<39527> A_IWL<39526> A_IWL<39525> A_IWL<39524> A_IWL<39523> A_IWL<39522> A_IWL<39521> A_IWL<39520> A_IWL<39519> A_IWL<39518> A_IWL<39517> A_IWL<39516> A_IWL<39515> A_IWL<39514> A_IWL<39513> A_IWL<39512> A_IWL<39511> A_IWL<39510> A_IWL<39509> A_IWL<39508> A_IWL<39507> A_IWL<39506> A_IWL<39505> A_IWL<39504> A_IWL<39503> A_IWL<39502> A_IWL<39501> A_IWL<39500> A_IWL<39499> A_IWL<39498> A_IWL<39497> A_IWL<39496> A_IWL<39495> A_IWL<39494> A_IWL<39493> A_IWL<39492> A_IWL<39491> A_IWL<39490> A_IWL<39489> A_IWL<39488> A_IWL<39487> A_IWL<39486> A_IWL<39485> A_IWL<39484> A_IWL<39483> A_IWL<39482> A_IWL<39481> A_IWL<39480> A_IWL<39479> A_IWL<39478> A_IWL<39477> A_IWL<39476> A_IWL<39475> A_IWL<39474> A_IWL<39473> A_IWL<39472> A_IWL<39471> A_IWL<39470> A_IWL<39469> A_IWL<39468> A_IWL<39467> A_IWL<39466> A_IWL<39465> A_IWL<39464> A_IWL<39463> A_IWL<39462> A_IWL<39461> A_IWL<39460> A_IWL<39459> A_IWL<39458> A_IWL<39457> A_IWL<39456> A_IWL<39455> A_IWL<39454> A_IWL<39453> A_IWL<39452> A_IWL<39451> A_IWL<39450> A_IWL<39449> A_IWL<39448> A_IWL<39447> A_IWL<39446> A_IWL<39445> A_IWL<39444> A_IWL<39443> A_IWL<39442> A_IWL<39441> A_IWL<39440> A_IWL<39439> A_IWL<39438> A_IWL<39437> A_IWL<39436> A_IWL<39435> A_IWL<39434> A_IWL<39433> A_IWL<39432> A_IWL<39431> A_IWL<39430> A_IWL<39429> A_IWL<39428> A_IWL<39427> A_IWL<39426> A_IWL<39425> A_IWL<39424> VDD_CORE VSS / RM_IHPSG13_8192x32_c4_1P_COLUMN_pcell_0 +XCOL<76> A_BLC<153> A_BLC<152> A_BLC_TOP<153> A_BLC_TOP<152> A_BLT<153> A_BLT<152> A_BLT_TOP<153> A_BLT_TOP<152> A_IWL<38911> A_IWL<38910> A_IWL<38909> A_IWL<38908> A_IWL<38907> A_IWL<38906> A_IWL<38905> A_IWL<38904> A_IWL<38903> A_IWL<38902> A_IWL<38901> A_IWL<38900> A_IWL<38899> A_IWL<38898> A_IWL<38897> A_IWL<38896> A_IWL<38895> A_IWL<38894> A_IWL<38893> A_IWL<38892> A_IWL<38891> A_IWL<38890> A_IWL<38889> A_IWL<38888> A_IWL<38887> A_IWL<38886> A_IWL<38885> A_IWL<38884> A_IWL<38883> A_IWL<38882> A_IWL<38881> A_IWL<38880> A_IWL<38879> A_IWL<38878> A_IWL<38877> A_IWL<38876> A_IWL<38875> A_IWL<38874> A_IWL<38873> A_IWL<38872> A_IWL<38871> A_IWL<38870> A_IWL<38869> A_IWL<38868> A_IWL<38867> A_IWL<38866> A_IWL<38865> A_IWL<38864> A_IWL<38863> A_IWL<38862> A_IWL<38861> A_IWL<38860> A_IWL<38859> A_IWL<38858> A_IWL<38857> A_IWL<38856> A_IWL<38855> A_IWL<38854> A_IWL<38853> A_IWL<38852> A_IWL<38851> A_IWL<38850> A_IWL<38849> A_IWL<38848> A_IWL<38847> A_IWL<38846> A_IWL<38845> A_IWL<38844> A_IWL<38843> A_IWL<38842> A_IWL<38841> A_IWL<38840> A_IWL<38839> A_IWL<38838> A_IWL<38837> A_IWL<38836> A_IWL<38835> A_IWL<38834> A_IWL<38833> A_IWL<38832> A_IWL<38831> A_IWL<38830> A_IWL<38829> A_IWL<38828> A_IWL<38827> A_IWL<38826> A_IWL<38825> A_IWL<38824> A_IWL<38823> A_IWL<38822> A_IWL<38821> A_IWL<38820> A_IWL<38819> A_IWL<38818> A_IWL<38817> A_IWL<38816> A_IWL<38815> A_IWL<38814> A_IWL<38813> A_IWL<38812> A_IWL<38811> A_IWL<38810> A_IWL<38809> A_IWL<38808> A_IWL<38807> A_IWL<38806> A_IWL<38805> A_IWL<38804> A_IWL<38803> A_IWL<38802> A_IWL<38801> A_IWL<38800> A_IWL<38799> A_IWL<38798> A_IWL<38797> A_IWL<38796> A_IWL<38795> A_IWL<38794> A_IWL<38793> A_IWL<38792> A_IWL<38791> A_IWL<38790> A_IWL<38789> A_IWL<38788> A_IWL<38787> A_IWL<38786> A_IWL<38785> A_IWL<38784> A_IWL<38783> A_IWL<38782> A_IWL<38781> A_IWL<38780> A_IWL<38779> A_IWL<38778> A_IWL<38777> A_IWL<38776> A_IWL<38775> A_IWL<38774> A_IWL<38773> A_IWL<38772> A_IWL<38771> A_IWL<38770> A_IWL<38769> A_IWL<38768> A_IWL<38767> A_IWL<38766> A_IWL<38765> A_IWL<38764> A_IWL<38763> A_IWL<38762> A_IWL<38761> A_IWL<38760> A_IWL<38759> A_IWL<38758> A_IWL<38757> A_IWL<38756> A_IWL<38755> A_IWL<38754> A_IWL<38753> A_IWL<38752> A_IWL<38751> A_IWL<38750> A_IWL<38749> A_IWL<38748> A_IWL<38747> A_IWL<38746> A_IWL<38745> A_IWL<38744> A_IWL<38743> A_IWL<38742> A_IWL<38741> A_IWL<38740> A_IWL<38739> A_IWL<38738> A_IWL<38737> A_IWL<38736> A_IWL<38735> A_IWL<38734> A_IWL<38733> A_IWL<38732> A_IWL<38731> A_IWL<38730> A_IWL<38729> A_IWL<38728> A_IWL<38727> A_IWL<38726> A_IWL<38725> A_IWL<38724> A_IWL<38723> A_IWL<38722> A_IWL<38721> A_IWL<38720> A_IWL<38719> A_IWL<38718> A_IWL<38717> A_IWL<38716> A_IWL<38715> A_IWL<38714> A_IWL<38713> A_IWL<38712> A_IWL<38711> A_IWL<38710> A_IWL<38709> A_IWL<38708> A_IWL<38707> A_IWL<38706> A_IWL<38705> A_IWL<38704> A_IWL<38703> A_IWL<38702> A_IWL<38701> A_IWL<38700> A_IWL<38699> A_IWL<38698> A_IWL<38697> A_IWL<38696> A_IWL<38695> A_IWL<38694> A_IWL<38693> A_IWL<38692> A_IWL<38691> A_IWL<38690> A_IWL<38689> A_IWL<38688> A_IWL<38687> A_IWL<38686> A_IWL<38685> A_IWL<38684> A_IWL<38683> A_IWL<38682> A_IWL<38681> A_IWL<38680> A_IWL<38679> A_IWL<38678> A_IWL<38677> A_IWL<38676> A_IWL<38675> A_IWL<38674> A_IWL<38673> A_IWL<38672> A_IWL<38671> A_IWL<38670> A_IWL<38669> A_IWL<38668> A_IWL<38667> A_IWL<38666> A_IWL<38665> A_IWL<38664> A_IWL<38663> A_IWL<38662> A_IWL<38661> A_IWL<38660> A_IWL<38659> A_IWL<38658> A_IWL<38657> A_IWL<38656> A_IWL<38655> A_IWL<38654> A_IWL<38653> A_IWL<38652> A_IWL<38651> A_IWL<38650> A_IWL<38649> A_IWL<38648> A_IWL<38647> A_IWL<38646> A_IWL<38645> A_IWL<38644> A_IWL<38643> A_IWL<38642> A_IWL<38641> A_IWL<38640> A_IWL<38639> A_IWL<38638> A_IWL<38637> A_IWL<38636> A_IWL<38635> A_IWL<38634> A_IWL<38633> A_IWL<38632> A_IWL<38631> A_IWL<38630> A_IWL<38629> A_IWL<38628> A_IWL<38627> A_IWL<38626> A_IWL<38625> A_IWL<38624> A_IWL<38623> A_IWL<38622> A_IWL<38621> A_IWL<38620> A_IWL<38619> A_IWL<38618> A_IWL<38617> A_IWL<38616> A_IWL<38615> A_IWL<38614> A_IWL<38613> A_IWL<38612> A_IWL<38611> A_IWL<38610> A_IWL<38609> A_IWL<38608> A_IWL<38607> A_IWL<38606> A_IWL<38605> A_IWL<38604> A_IWL<38603> A_IWL<38602> A_IWL<38601> A_IWL<38600> A_IWL<38599> A_IWL<38598> A_IWL<38597> A_IWL<38596> A_IWL<38595> A_IWL<38594> A_IWL<38593> A_IWL<38592> A_IWL<38591> A_IWL<38590> A_IWL<38589> A_IWL<38588> A_IWL<38587> A_IWL<38586> A_IWL<38585> A_IWL<38584> A_IWL<38583> A_IWL<38582> A_IWL<38581> A_IWL<38580> A_IWL<38579> A_IWL<38578> A_IWL<38577> A_IWL<38576> A_IWL<38575> A_IWL<38574> A_IWL<38573> A_IWL<38572> A_IWL<38571> A_IWL<38570> A_IWL<38569> A_IWL<38568> A_IWL<38567> A_IWL<38566> A_IWL<38565> A_IWL<38564> A_IWL<38563> A_IWL<38562> A_IWL<38561> A_IWL<38560> A_IWL<38559> A_IWL<38558> A_IWL<38557> A_IWL<38556> A_IWL<38555> A_IWL<38554> A_IWL<38553> A_IWL<38552> A_IWL<38551> A_IWL<38550> A_IWL<38549> A_IWL<38548> A_IWL<38547> A_IWL<38546> A_IWL<38545> A_IWL<38544> A_IWL<38543> A_IWL<38542> A_IWL<38541> A_IWL<38540> A_IWL<38539> A_IWL<38538> A_IWL<38537> A_IWL<38536> A_IWL<38535> A_IWL<38534> A_IWL<38533> A_IWL<38532> A_IWL<38531> A_IWL<38530> A_IWL<38529> A_IWL<38528> A_IWL<38527> A_IWL<38526> A_IWL<38525> A_IWL<38524> A_IWL<38523> A_IWL<38522> A_IWL<38521> A_IWL<38520> A_IWL<38519> A_IWL<38518> A_IWL<38517> A_IWL<38516> A_IWL<38515> A_IWL<38514> A_IWL<38513> A_IWL<38512> A_IWL<38511> A_IWL<38510> A_IWL<38509> A_IWL<38508> A_IWL<38507> A_IWL<38506> A_IWL<38505> A_IWL<38504> A_IWL<38503> A_IWL<38502> A_IWL<38501> A_IWL<38500> A_IWL<38499> A_IWL<38498> A_IWL<38497> A_IWL<38496> A_IWL<38495> A_IWL<38494> A_IWL<38493> A_IWL<38492> A_IWL<38491> A_IWL<38490> A_IWL<38489> A_IWL<38488> A_IWL<38487> A_IWL<38486> A_IWL<38485> A_IWL<38484> A_IWL<38483> A_IWL<38482> A_IWL<38481> A_IWL<38480> A_IWL<38479> A_IWL<38478> A_IWL<38477> A_IWL<38476> A_IWL<38475> A_IWL<38474> A_IWL<38473> A_IWL<38472> A_IWL<38471> A_IWL<38470> A_IWL<38469> A_IWL<38468> A_IWL<38467> A_IWL<38466> A_IWL<38465> A_IWL<38464> A_IWL<38463> A_IWL<38462> A_IWL<38461> A_IWL<38460> A_IWL<38459> A_IWL<38458> A_IWL<38457> A_IWL<38456> A_IWL<38455> A_IWL<38454> A_IWL<38453> A_IWL<38452> A_IWL<38451> A_IWL<38450> A_IWL<38449> A_IWL<38448> A_IWL<38447> A_IWL<38446> A_IWL<38445> A_IWL<38444> A_IWL<38443> A_IWL<38442> A_IWL<38441> A_IWL<38440> A_IWL<38439> A_IWL<38438> A_IWL<38437> A_IWL<38436> A_IWL<38435> A_IWL<38434> A_IWL<38433> A_IWL<38432> A_IWL<38431> A_IWL<38430> A_IWL<38429> A_IWL<38428> A_IWL<38427> A_IWL<38426> A_IWL<38425> A_IWL<38424> A_IWL<38423> A_IWL<38422> A_IWL<38421> A_IWL<38420> A_IWL<38419> A_IWL<38418> A_IWL<38417> A_IWL<38416> A_IWL<38415> A_IWL<38414> A_IWL<38413> A_IWL<38412> A_IWL<38411> A_IWL<38410> A_IWL<38409> A_IWL<38408> A_IWL<38407> A_IWL<38406> A_IWL<38405> A_IWL<38404> A_IWL<38403> A_IWL<38402> A_IWL<38401> A_IWL<38400> A_IWL<39423> A_IWL<39422> A_IWL<39421> A_IWL<39420> A_IWL<39419> A_IWL<39418> A_IWL<39417> A_IWL<39416> A_IWL<39415> A_IWL<39414> A_IWL<39413> A_IWL<39412> A_IWL<39411> A_IWL<39410> A_IWL<39409> A_IWL<39408> A_IWL<39407> A_IWL<39406> A_IWL<39405> A_IWL<39404> A_IWL<39403> A_IWL<39402> A_IWL<39401> A_IWL<39400> A_IWL<39399> A_IWL<39398> A_IWL<39397> A_IWL<39396> A_IWL<39395> A_IWL<39394> A_IWL<39393> A_IWL<39392> A_IWL<39391> A_IWL<39390> A_IWL<39389> A_IWL<39388> A_IWL<39387> A_IWL<39386> A_IWL<39385> A_IWL<39384> A_IWL<39383> A_IWL<39382> A_IWL<39381> A_IWL<39380> A_IWL<39379> A_IWL<39378> A_IWL<39377> A_IWL<39376> A_IWL<39375> A_IWL<39374> A_IWL<39373> A_IWL<39372> A_IWL<39371> A_IWL<39370> A_IWL<39369> A_IWL<39368> A_IWL<39367> A_IWL<39366> A_IWL<39365> A_IWL<39364> A_IWL<39363> A_IWL<39362> A_IWL<39361> A_IWL<39360> A_IWL<39359> A_IWL<39358> A_IWL<39357> A_IWL<39356> A_IWL<39355> A_IWL<39354> A_IWL<39353> A_IWL<39352> A_IWL<39351> A_IWL<39350> A_IWL<39349> A_IWL<39348> A_IWL<39347> A_IWL<39346> A_IWL<39345> A_IWL<39344> A_IWL<39343> A_IWL<39342> A_IWL<39341> A_IWL<39340> A_IWL<39339> A_IWL<39338> A_IWL<39337> A_IWL<39336> A_IWL<39335> A_IWL<39334> A_IWL<39333> A_IWL<39332> A_IWL<39331> A_IWL<39330> A_IWL<39329> A_IWL<39328> A_IWL<39327> A_IWL<39326> A_IWL<39325> A_IWL<39324> A_IWL<39323> A_IWL<39322> A_IWL<39321> A_IWL<39320> A_IWL<39319> A_IWL<39318> A_IWL<39317> A_IWL<39316> A_IWL<39315> A_IWL<39314> A_IWL<39313> A_IWL<39312> A_IWL<39311> A_IWL<39310> A_IWL<39309> A_IWL<39308> A_IWL<39307> A_IWL<39306> A_IWL<39305> A_IWL<39304> A_IWL<39303> A_IWL<39302> A_IWL<39301> A_IWL<39300> A_IWL<39299> A_IWL<39298> A_IWL<39297> A_IWL<39296> A_IWL<39295> A_IWL<39294> A_IWL<39293> A_IWL<39292> A_IWL<39291> A_IWL<39290> A_IWL<39289> A_IWL<39288> A_IWL<39287> A_IWL<39286> A_IWL<39285> A_IWL<39284> A_IWL<39283> A_IWL<39282> A_IWL<39281> A_IWL<39280> A_IWL<39279> A_IWL<39278> A_IWL<39277> A_IWL<39276> A_IWL<39275> A_IWL<39274> A_IWL<39273> A_IWL<39272> A_IWL<39271> A_IWL<39270> A_IWL<39269> A_IWL<39268> A_IWL<39267> A_IWL<39266> A_IWL<39265> A_IWL<39264> A_IWL<39263> A_IWL<39262> A_IWL<39261> A_IWL<39260> A_IWL<39259> A_IWL<39258> A_IWL<39257> A_IWL<39256> A_IWL<39255> A_IWL<39254> A_IWL<39253> A_IWL<39252> A_IWL<39251> A_IWL<39250> A_IWL<39249> A_IWL<39248> A_IWL<39247> A_IWL<39246> A_IWL<39245> A_IWL<39244> A_IWL<39243> A_IWL<39242> A_IWL<39241> A_IWL<39240> A_IWL<39239> A_IWL<39238> A_IWL<39237> A_IWL<39236> A_IWL<39235> A_IWL<39234> A_IWL<39233> A_IWL<39232> A_IWL<39231> A_IWL<39230> A_IWL<39229> A_IWL<39228> A_IWL<39227> A_IWL<39226> A_IWL<39225> A_IWL<39224> A_IWL<39223> A_IWL<39222> A_IWL<39221> A_IWL<39220> A_IWL<39219> A_IWL<39218> A_IWL<39217> A_IWL<39216> A_IWL<39215> A_IWL<39214> A_IWL<39213> A_IWL<39212> A_IWL<39211> A_IWL<39210> A_IWL<39209> A_IWL<39208> A_IWL<39207> A_IWL<39206> A_IWL<39205> A_IWL<39204> A_IWL<39203> A_IWL<39202> A_IWL<39201> A_IWL<39200> A_IWL<39199> A_IWL<39198> A_IWL<39197> A_IWL<39196> A_IWL<39195> A_IWL<39194> A_IWL<39193> A_IWL<39192> A_IWL<39191> A_IWL<39190> A_IWL<39189> A_IWL<39188> A_IWL<39187> A_IWL<39186> A_IWL<39185> A_IWL<39184> A_IWL<39183> A_IWL<39182> A_IWL<39181> A_IWL<39180> A_IWL<39179> A_IWL<39178> A_IWL<39177> A_IWL<39176> A_IWL<39175> A_IWL<39174> A_IWL<39173> A_IWL<39172> A_IWL<39171> A_IWL<39170> A_IWL<39169> A_IWL<39168> A_IWL<39167> A_IWL<39166> A_IWL<39165> A_IWL<39164> A_IWL<39163> A_IWL<39162> A_IWL<39161> A_IWL<39160> A_IWL<39159> A_IWL<39158> A_IWL<39157> A_IWL<39156> A_IWL<39155> A_IWL<39154> A_IWL<39153> A_IWL<39152> A_IWL<39151> A_IWL<39150> A_IWL<39149> A_IWL<39148> A_IWL<39147> A_IWL<39146> A_IWL<39145> A_IWL<39144> A_IWL<39143> A_IWL<39142> A_IWL<39141> A_IWL<39140> A_IWL<39139> A_IWL<39138> A_IWL<39137> A_IWL<39136> A_IWL<39135> A_IWL<39134> A_IWL<39133> A_IWL<39132> A_IWL<39131> A_IWL<39130> A_IWL<39129> A_IWL<39128> A_IWL<39127> A_IWL<39126> A_IWL<39125> A_IWL<39124> A_IWL<39123> A_IWL<39122> A_IWL<39121> A_IWL<39120> A_IWL<39119> A_IWL<39118> A_IWL<39117> A_IWL<39116> A_IWL<39115> A_IWL<39114> A_IWL<39113> A_IWL<39112> A_IWL<39111> A_IWL<39110> A_IWL<39109> A_IWL<39108> A_IWL<39107> A_IWL<39106> A_IWL<39105> A_IWL<39104> A_IWL<39103> A_IWL<39102> A_IWL<39101> A_IWL<39100> A_IWL<39099> A_IWL<39098> A_IWL<39097> A_IWL<39096> A_IWL<39095> A_IWL<39094> A_IWL<39093> A_IWL<39092> A_IWL<39091> A_IWL<39090> A_IWL<39089> A_IWL<39088> A_IWL<39087> A_IWL<39086> A_IWL<39085> A_IWL<39084> A_IWL<39083> A_IWL<39082> A_IWL<39081> A_IWL<39080> A_IWL<39079> A_IWL<39078> A_IWL<39077> A_IWL<39076> A_IWL<39075> A_IWL<39074> A_IWL<39073> A_IWL<39072> A_IWL<39071> A_IWL<39070> A_IWL<39069> A_IWL<39068> A_IWL<39067> A_IWL<39066> A_IWL<39065> A_IWL<39064> A_IWL<39063> A_IWL<39062> A_IWL<39061> A_IWL<39060> A_IWL<39059> A_IWL<39058> A_IWL<39057> A_IWL<39056> A_IWL<39055> A_IWL<39054> A_IWL<39053> A_IWL<39052> A_IWL<39051> A_IWL<39050> A_IWL<39049> A_IWL<39048> A_IWL<39047> A_IWL<39046> A_IWL<39045> A_IWL<39044> A_IWL<39043> A_IWL<39042> A_IWL<39041> A_IWL<39040> A_IWL<39039> A_IWL<39038> A_IWL<39037> A_IWL<39036> A_IWL<39035> A_IWL<39034> A_IWL<39033> A_IWL<39032> A_IWL<39031> A_IWL<39030> A_IWL<39029> A_IWL<39028> A_IWL<39027> A_IWL<39026> A_IWL<39025> A_IWL<39024> A_IWL<39023> A_IWL<39022> A_IWL<39021> A_IWL<39020> A_IWL<39019> A_IWL<39018> A_IWL<39017> A_IWL<39016> A_IWL<39015> A_IWL<39014> A_IWL<39013> A_IWL<39012> A_IWL<39011> A_IWL<39010> A_IWL<39009> A_IWL<39008> A_IWL<39007> A_IWL<39006> A_IWL<39005> A_IWL<39004> A_IWL<39003> A_IWL<39002> A_IWL<39001> A_IWL<39000> A_IWL<38999> A_IWL<38998> A_IWL<38997> A_IWL<38996> A_IWL<38995> A_IWL<38994> A_IWL<38993> A_IWL<38992> A_IWL<38991> A_IWL<38990> A_IWL<38989> A_IWL<38988> A_IWL<38987> A_IWL<38986> A_IWL<38985> A_IWL<38984> A_IWL<38983> A_IWL<38982> A_IWL<38981> A_IWL<38980> A_IWL<38979> A_IWL<38978> A_IWL<38977> A_IWL<38976> A_IWL<38975> A_IWL<38974> A_IWL<38973> A_IWL<38972> A_IWL<38971> A_IWL<38970> A_IWL<38969> A_IWL<38968> A_IWL<38967> A_IWL<38966> A_IWL<38965> A_IWL<38964> A_IWL<38963> A_IWL<38962> A_IWL<38961> A_IWL<38960> A_IWL<38959> A_IWL<38958> A_IWL<38957> A_IWL<38956> A_IWL<38955> A_IWL<38954> A_IWL<38953> A_IWL<38952> A_IWL<38951> A_IWL<38950> A_IWL<38949> A_IWL<38948> A_IWL<38947> A_IWL<38946> A_IWL<38945> A_IWL<38944> A_IWL<38943> A_IWL<38942> A_IWL<38941> A_IWL<38940> A_IWL<38939> A_IWL<38938> A_IWL<38937> A_IWL<38936> A_IWL<38935> A_IWL<38934> A_IWL<38933> A_IWL<38932> A_IWL<38931> A_IWL<38930> A_IWL<38929> A_IWL<38928> A_IWL<38927> A_IWL<38926> A_IWL<38925> A_IWL<38924> A_IWL<38923> A_IWL<38922> A_IWL<38921> A_IWL<38920> A_IWL<38919> A_IWL<38918> A_IWL<38917> A_IWL<38916> A_IWL<38915> A_IWL<38914> A_IWL<38913> A_IWL<38912> VDD_CORE VSS / RM_IHPSG13_8192x32_c4_1P_COLUMN_pcell_0 +XCOL<75> A_BLC<151> A_BLC<150> A_BLC_TOP<151> A_BLC_TOP<150> A_BLT<151> A_BLT<150> A_BLT_TOP<151> A_BLT_TOP<150> A_IWL<38399> A_IWL<38398> A_IWL<38397> A_IWL<38396> A_IWL<38395> A_IWL<38394> A_IWL<38393> A_IWL<38392> A_IWL<38391> A_IWL<38390> A_IWL<38389> A_IWL<38388> A_IWL<38387> A_IWL<38386> A_IWL<38385> A_IWL<38384> A_IWL<38383> A_IWL<38382> A_IWL<38381> A_IWL<38380> A_IWL<38379> A_IWL<38378> A_IWL<38377> A_IWL<38376> A_IWL<38375> A_IWL<38374> A_IWL<38373> A_IWL<38372> A_IWL<38371> A_IWL<38370> A_IWL<38369> A_IWL<38368> A_IWL<38367> A_IWL<38366> A_IWL<38365> A_IWL<38364> A_IWL<38363> A_IWL<38362> A_IWL<38361> A_IWL<38360> A_IWL<38359> A_IWL<38358> A_IWL<38357> A_IWL<38356> A_IWL<38355> A_IWL<38354> A_IWL<38353> A_IWL<38352> A_IWL<38351> A_IWL<38350> A_IWL<38349> A_IWL<38348> A_IWL<38347> A_IWL<38346> A_IWL<38345> A_IWL<38344> A_IWL<38343> A_IWL<38342> A_IWL<38341> A_IWL<38340> A_IWL<38339> A_IWL<38338> A_IWL<38337> A_IWL<38336> A_IWL<38335> A_IWL<38334> A_IWL<38333> A_IWL<38332> A_IWL<38331> A_IWL<38330> A_IWL<38329> A_IWL<38328> A_IWL<38327> A_IWL<38326> A_IWL<38325> A_IWL<38324> A_IWL<38323> A_IWL<38322> A_IWL<38321> A_IWL<38320> A_IWL<38319> A_IWL<38318> A_IWL<38317> A_IWL<38316> A_IWL<38315> A_IWL<38314> A_IWL<38313> A_IWL<38312> A_IWL<38311> A_IWL<38310> A_IWL<38309> A_IWL<38308> A_IWL<38307> A_IWL<38306> A_IWL<38305> A_IWL<38304> A_IWL<38303> A_IWL<38302> A_IWL<38301> A_IWL<38300> A_IWL<38299> A_IWL<38298> A_IWL<38297> A_IWL<38296> A_IWL<38295> A_IWL<38294> A_IWL<38293> A_IWL<38292> A_IWL<38291> A_IWL<38290> A_IWL<38289> A_IWL<38288> A_IWL<38287> A_IWL<38286> A_IWL<38285> A_IWL<38284> A_IWL<38283> A_IWL<38282> A_IWL<38281> A_IWL<38280> A_IWL<38279> A_IWL<38278> A_IWL<38277> A_IWL<38276> A_IWL<38275> A_IWL<38274> A_IWL<38273> A_IWL<38272> A_IWL<38271> A_IWL<38270> A_IWL<38269> A_IWL<38268> A_IWL<38267> A_IWL<38266> A_IWL<38265> A_IWL<38264> A_IWL<38263> A_IWL<38262> A_IWL<38261> A_IWL<38260> A_IWL<38259> A_IWL<38258> A_IWL<38257> A_IWL<38256> A_IWL<38255> A_IWL<38254> A_IWL<38253> A_IWL<38252> A_IWL<38251> A_IWL<38250> A_IWL<38249> A_IWL<38248> A_IWL<38247> A_IWL<38246> A_IWL<38245> A_IWL<38244> A_IWL<38243> A_IWL<38242> A_IWL<38241> A_IWL<38240> A_IWL<38239> A_IWL<38238> A_IWL<38237> A_IWL<38236> A_IWL<38235> A_IWL<38234> A_IWL<38233> A_IWL<38232> A_IWL<38231> A_IWL<38230> A_IWL<38229> A_IWL<38228> A_IWL<38227> A_IWL<38226> A_IWL<38225> A_IWL<38224> A_IWL<38223> A_IWL<38222> A_IWL<38221> A_IWL<38220> A_IWL<38219> A_IWL<38218> A_IWL<38217> A_IWL<38216> A_IWL<38215> A_IWL<38214> A_IWL<38213> A_IWL<38212> A_IWL<38211> A_IWL<38210> A_IWL<38209> A_IWL<38208> A_IWL<38207> A_IWL<38206> A_IWL<38205> A_IWL<38204> A_IWL<38203> A_IWL<38202> A_IWL<38201> A_IWL<38200> A_IWL<38199> A_IWL<38198> A_IWL<38197> A_IWL<38196> A_IWL<38195> A_IWL<38194> A_IWL<38193> A_IWL<38192> A_IWL<38191> A_IWL<38190> A_IWL<38189> A_IWL<38188> A_IWL<38187> A_IWL<38186> A_IWL<38185> A_IWL<38184> A_IWL<38183> A_IWL<38182> A_IWL<38181> A_IWL<38180> A_IWL<38179> A_IWL<38178> A_IWL<38177> A_IWL<38176> A_IWL<38175> A_IWL<38174> A_IWL<38173> A_IWL<38172> A_IWL<38171> A_IWL<38170> A_IWL<38169> A_IWL<38168> A_IWL<38167> A_IWL<38166> A_IWL<38165> A_IWL<38164> A_IWL<38163> A_IWL<38162> A_IWL<38161> A_IWL<38160> A_IWL<38159> A_IWL<38158> A_IWL<38157> A_IWL<38156> A_IWL<38155> A_IWL<38154> A_IWL<38153> A_IWL<38152> A_IWL<38151> A_IWL<38150> A_IWL<38149> A_IWL<38148> A_IWL<38147> A_IWL<38146> A_IWL<38145> A_IWL<38144> A_IWL<38143> A_IWL<38142> A_IWL<38141> A_IWL<38140> A_IWL<38139> A_IWL<38138> A_IWL<38137> A_IWL<38136> A_IWL<38135> A_IWL<38134> A_IWL<38133> A_IWL<38132> A_IWL<38131> A_IWL<38130> A_IWL<38129> A_IWL<38128> A_IWL<38127> A_IWL<38126> A_IWL<38125> A_IWL<38124> A_IWL<38123> A_IWL<38122> A_IWL<38121> A_IWL<38120> A_IWL<38119> A_IWL<38118> A_IWL<38117> A_IWL<38116> A_IWL<38115> A_IWL<38114> A_IWL<38113> A_IWL<38112> A_IWL<38111> A_IWL<38110> A_IWL<38109> A_IWL<38108> A_IWL<38107> A_IWL<38106> A_IWL<38105> A_IWL<38104> A_IWL<38103> A_IWL<38102> A_IWL<38101> A_IWL<38100> A_IWL<38099> A_IWL<38098> A_IWL<38097> A_IWL<38096> A_IWL<38095> A_IWL<38094> A_IWL<38093> A_IWL<38092> A_IWL<38091> A_IWL<38090> A_IWL<38089> A_IWL<38088> A_IWL<38087> A_IWL<38086> A_IWL<38085> A_IWL<38084> A_IWL<38083> A_IWL<38082> A_IWL<38081> A_IWL<38080> A_IWL<38079> A_IWL<38078> A_IWL<38077> A_IWL<38076> A_IWL<38075> A_IWL<38074> A_IWL<38073> A_IWL<38072> A_IWL<38071> A_IWL<38070> A_IWL<38069> A_IWL<38068> A_IWL<38067> A_IWL<38066> A_IWL<38065> A_IWL<38064> A_IWL<38063> A_IWL<38062> A_IWL<38061> A_IWL<38060> A_IWL<38059> A_IWL<38058> A_IWL<38057> A_IWL<38056> A_IWL<38055> A_IWL<38054> A_IWL<38053> A_IWL<38052> A_IWL<38051> A_IWL<38050> A_IWL<38049> A_IWL<38048> A_IWL<38047> A_IWL<38046> A_IWL<38045> A_IWL<38044> A_IWL<38043> A_IWL<38042> A_IWL<38041> A_IWL<38040> A_IWL<38039> A_IWL<38038> A_IWL<38037> A_IWL<38036> A_IWL<38035> A_IWL<38034> A_IWL<38033> A_IWL<38032> A_IWL<38031> A_IWL<38030> A_IWL<38029> A_IWL<38028> A_IWL<38027> A_IWL<38026> A_IWL<38025> A_IWL<38024> A_IWL<38023> A_IWL<38022> A_IWL<38021> A_IWL<38020> A_IWL<38019> A_IWL<38018> A_IWL<38017> A_IWL<38016> A_IWL<38015> A_IWL<38014> A_IWL<38013> A_IWL<38012> A_IWL<38011> A_IWL<38010> A_IWL<38009> A_IWL<38008> A_IWL<38007> A_IWL<38006> A_IWL<38005> A_IWL<38004> A_IWL<38003> A_IWL<38002> A_IWL<38001> A_IWL<38000> A_IWL<37999> A_IWL<37998> A_IWL<37997> A_IWL<37996> A_IWL<37995> A_IWL<37994> A_IWL<37993> A_IWL<37992> A_IWL<37991> A_IWL<37990> A_IWL<37989> A_IWL<37988> A_IWL<37987> A_IWL<37986> A_IWL<37985> A_IWL<37984> A_IWL<37983> A_IWL<37982> A_IWL<37981> A_IWL<37980> A_IWL<37979> A_IWL<37978> A_IWL<37977> A_IWL<37976> A_IWL<37975> A_IWL<37974> A_IWL<37973> A_IWL<37972> A_IWL<37971> A_IWL<37970> A_IWL<37969> A_IWL<37968> A_IWL<37967> A_IWL<37966> A_IWL<37965> A_IWL<37964> A_IWL<37963> A_IWL<37962> A_IWL<37961> A_IWL<37960> A_IWL<37959> A_IWL<37958> A_IWL<37957> A_IWL<37956> A_IWL<37955> A_IWL<37954> A_IWL<37953> A_IWL<37952> A_IWL<37951> A_IWL<37950> A_IWL<37949> A_IWL<37948> A_IWL<37947> A_IWL<37946> A_IWL<37945> A_IWL<37944> A_IWL<37943> A_IWL<37942> A_IWL<37941> A_IWL<37940> A_IWL<37939> A_IWL<37938> A_IWL<37937> A_IWL<37936> A_IWL<37935> A_IWL<37934> A_IWL<37933> A_IWL<37932> A_IWL<37931> A_IWL<37930> A_IWL<37929> A_IWL<37928> A_IWL<37927> A_IWL<37926> A_IWL<37925> A_IWL<37924> A_IWL<37923> A_IWL<37922> A_IWL<37921> A_IWL<37920> A_IWL<37919> A_IWL<37918> A_IWL<37917> A_IWL<37916> A_IWL<37915> A_IWL<37914> A_IWL<37913> A_IWL<37912> A_IWL<37911> A_IWL<37910> A_IWL<37909> A_IWL<37908> A_IWL<37907> A_IWL<37906> A_IWL<37905> A_IWL<37904> A_IWL<37903> A_IWL<37902> A_IWL<37901> A_IWL<37900> A_IWL<37899> A_IWL<37898> A_IWL<37897> A_IWL<37896> A_IWL<37895> A_IWL<37894> A_IWL<37893> A_IWL<37892> A_IWL<37891> A_IWL<37890> A_IWL<37889> A_IWL<37888> A_IWL<38911> A_IWL<38910> A_IWL<38909> A_IWL<38908> A_IWL<38907> A_IWL<38906> A_IWL<38905> A_IWL<38904> A_IWL<38903> A_IWL<38902> A_IWL<38901> A_IWL<38900> A_IWL<38899> A_IWL<38898> A_IWL<38897> A_IWL<38896> A_IWL<38895> A_IWL<38894> A_IWL<38893> A_IWL<38892> A_IWL<38891> A_IWL<38890> A_IWL<38889> A_IWL<38888> A_IWL<38887> A_IWL<38886> A_IWL<38885> A_IWL<38884> A_IWL<38883> A_IWL<38882> A_IWL<38881> A_IWL<38880> A_IWL<38879> A_IWL<38878> A_IWL<38877> A_IWL<38876> A_IWL<38875> A_IWL<38874> A_IWL<38873> A_IWL<38872> A_IWL<38871> A_IWL<38870> A_IWL<38869> A_IWL<38868> A_IWL<38867> A_IWL<38866> A_IWL<38865> A_IWL<38864> A_IWL<38863> A_IWL<38862> A_IWL<38861> A_IWL<38860> A_IWL<38859> A_IWL<38858> A_IWL<38857> A_IWL<38856> A_IWL<38855> A_IWL<38854> A_IWL<38853> A_IWL<38852> A_IWL<38851> A_IWL<38850> A_IWL<38849> A_IWL<38848> A_IWL<38847> A_IWL<38846> A_IWL<38845> A_IWL<38844> A_IWL<38843> A_IWL<38842> A_IWL<38841> A_IWL<38840> A_IWL<38839> A_IWL<38838> A_IWL<38837> A_IWL<38836> A_IWL<38835> A_IWL<38834> A_IWL<38833> A_IWL<38832> A_IWL<38831> A_IWL<38830> A_IWL<38829> A_IWL<38828> A_IWL<38827> A_IWL<38826> A_IWL<38825> A_IWL<38824> A_IWL<38823> A_IWL<38822> A_IWL<38821> A_IWL<38820> A_IWL<38819> A_IWL<38818> A_IWL<38817> A_IWL<38816> A_IWL<38815> A_IWL<38814> A_IWL<38813> A_IWL<38812> A_IWL<38811> A_IWL<38810> A_IWL<38809> A_IWL<38808> A_IWL<38807> A_IWL<38806> A_IWL<38805> A_IWL<38804> A_IWL<38803> A_IWL<38802> A_IWL<38801> A_IWL<38800> A_IWL<38799> A_IWL<38798> A_IWL<38797> A_IWL<38796> A_IWL<38795> A_IWL<38794> A_IWL<38793> A_IWL<38792> A_IWL<38791> A_IWL<38790> A_IWL<38789> A_IWL<38788> A_IWL<38787> A_IWL<38786> A_IWL<38785> A_IWL<38784> A_IWL<38783> A_IWL<38782> A_IWL<38781> A_IWL<38780> A_IWL<38779> A_IWL<38778> A_IWL<38777> A_IWL<38776> A_IWL<38775> A_IWL<38774> A_IWL<38773> A_IWL<38772> A_IWL<38771> A_IWL<38770> A_IWL<38769> A_IWL<38768> A_IWL<38767> A_IWL<38766> A_IWL<38765> A_IWL<38764> A_IWL<38763> A_IWL<38762> A_IWL<38761> A_IWL<38760> A_IWL<38759> A_IWL<38758> A_IWL<38757> A_IWL<38756> A_IWL<38755> A_IWL<38754> A_IWL<38753> A_IWL<38752> A_IWL<38751> A_IWL<38750> A_IWL<38749> A_IWL<38748> A_IWL<38747> A_IWL<38746> A_IWL<38745> A_IWL<38744> A_IWL<38743> A_IWL<38742> A_IWL<38741> A_IWL<38740> A_IWL<38739> A_IWL<38738> A_IWL<38737> A_IWL<38736> A_IWL<38735> A_IWL<38734> A_IWL<38733> A_IWL<38732> A_IWL<38731> A_IWL<38730> A_IWL<38729> A_IWL<38728> A_IWL<38727> A_IWL<38726> A_IWL<38725> A_IWL<38724> A_IWL<38723> A_IWL<38722> A_IWL<38721> A_IWL<38720> A_IWL<38719> A_IWL<38718> A_IWL<38717> A_IWL<38716> A_IWL<38715> A_IWL<38714> A_IWL<38713> A_IWL<38712> A_IWL<38711> A_IWL<38710> A_IWL<38709> A_IWL<38708> A_IWL<38707> A_IWL<38706> A_IWL<38705> A_IWL<38704> A_IWL<38703> A_IWL<38702> A_IWL<38701> A_IWL<38700> A_IWL<38699> A_IWL<38698> A_IWL<38697> A_IWL<38696> A_IWL<38695> A_IWL<38694> A_IWL<38693> A_IWL<38692> A_IWL<38691> A_IWL<38690> A_IWL<38689> A_IWL<38688> A_IWL<38687> A_IWL<38686> A_IWL<38685> A_IWL<38684> A_IWL<38683> A_IWL<38682> A_IWL<38681> A_IWL<38680> A_IWL<38679> A_IWL<38678> A_IWL<38677> A_IWL<38676> A_IWL<38675> A_IWL<38674> A_IWL<38673> A_IWL<38672> A_IWL<38671> A_IWL<38670> A_IWL<38669> A_IWL<38668> A_IWL<38667> A_IWL<38666> A_IWL<38665> A_IWL<38664> A_IWL<38663> A_IWL<38662> A_IWL<38661> A_IWL<38660> A_IWL<38659> A_IWL<38658> A_IWL<38657> A_IWL<38656> A_IWL<38655> A_IWL<38654> A_IWL<38653> A_IWL<38652> A_IWL<38651> A_IWL<38650> A_IWL<38649> A_IWL<38648> A_IWL<38647> A_IWL<38646> A_IWL<38645> A_IWL<38644> A_IWL<38643> A_IWL<38642> A_IWL<38641> A_IWL<38640> A_IWL<38639> A_IWL<38638> A_IWL<38637> A_IWL<38636> A_IWL<38635> A_IWL<38634> A_IWL<38633> A_IWL<38632> A_IWL<38631> A_IWL<38630> A_IWL<38629> A_IWL<38628> A_IWL<38627> A_IWL<38626> A_IWL<38625> A_IWL<38624> A_IWL<38623> A_IWL<38622> A_IWL<38621> A_IWL<38620> A_IWL<38619> A_IWL<38618> A_IWL<38617> A_IWL<38616> A_IWL<38615> A_IWL<38614> A_IWL<38613> A_IWL<38612> A_IWL<38611> A_IWL<38610> A_IWL<38609> A_IWL<38608> A_IWL<38607> A_IWL<38606> A_IWL<38605> A_IWL<38604> A_IWL<38603> A_IWL<38602> A_IWL<38601> A_IWL<38600> A_IWL<38599> A_IWL<38598> A_IWL<38597> A_IWL<38596> A_IWL<38595> A_IWL<38594> A_IWL<38593> A_IWL<38592> A_IWL<38591> A_IWL<38590> A_IWL<38589> A_IWL<38588> A_IWL<38587> A_IWL<38586> A_IWL<38585> A_IWL<38584> A_IWL<38583> A_IWL<38582> A_IWL<38581> A_IWL<38580> A_IWL<38579> A_IWL<38578> A_IWL<38577> A_IWL<38576> A_IWL<38575> A_IWL<38574> A_IWL<38573> A_IWL<38572> A_IWL<38571> A_IWL<38570> A_IWL<38569> A_IWL<38568> A_IWL<38567> A_IWL<38566> A_IWL<38565> A_IWL<38564> A_IWL<38563> A_IWL<38562> A_IWL<38561> A_IWL<38560> A_IWL<38559> A_IWL<38558> A_IWL<38557> A_IWL<38556> A_IWL<38555> A_IWL<38554> A_IWL<38553> A_IWL<38552> A_IWL<38551> A_IWL<38550> A_IWL<38549> A_IWL<38548> A_IWL<38547> A_IWL<38546> A_IWL<38545> A_IWL<38544> A_IWL<38543> A_IWL<38542> A_IWL<38541> A_IWL<38540> A_IWL<38539> A_IWL<38538> A_IWL<38537> A_IWL<38536> A_IWL<38535> A_IWL<38534> A_IWL<38533> A_IWL<38532> A_IWL<38531> A_IWL<38530> A_IWL<38529> A_IWL<38528> A_IWL<38527> A_IWL<38526> A_IWL<38525> A_IWL<38524> A_IWL<38523> A_IWL<38522> A_IWL<38521> A_IWL<38520> A_IWL<38519> A_IWL<38518> A_IWL<38517> A_IWL<38516> A_IWL<38515> A_IWL<38514> A_IWL<38513> A_IWL<38512> A_IWL<38511> A_IWL<38510> A_IWL<38509> A_IWL<38508> A_IWL<38507> A_IWL<38506> A_IWL<38505> A_IWL<38504> A_IWL<38503> A_IWL<38502> A_IWL<38501> A_IWL<38500> A_IWL<38499> A_IWL<38498> A_IWL<38497> A_IWL<38496> A_IWL<38495> A_IWL<38494> A_IWL<38493> A_IWL<38492> A_IWL<38491> A_IWL<38490> A_IWL<38489> A_IWL<38488> A_IWL<38487> A_IWL<38486> A_IWL<38485> A_IWL<38484> A_IWL<38483> A_IWL<38482> A_IWL<38481> A_IWL<38480> A_IWL<38479> A_IWL<38478> A_IWL<38477> A_IWL<38476> A_IWL<38475> A_IWL<38474> A_IWL<38473> A_IWL<38472> A_IWL<38471> A_IWL<38470> A_IWL<38469> A_IWL<38468> A_IWL<38467> A_IWL<38466> A_IWL<38465> A_IWL<38464> A_IWL<38463> A_IWL<38462> A_IWL<38461> A_IWL<38460> A_IWL<38459> A_IWL<38458> A_IWL<38457> A_IWL<38456> A_IWL<38455> A_IWL<38454> A_IWL<38453> A_IWL<38452> A_IWL<38451> A_IWL<38450> A_IWL<38449> A_IWL<38448> A_IWL<38447> A_IWL<38446> A_IWL<38445> A_IWL<38444> A_IWL<38443> A_IWL<38442> A_IWL<38441> A_IWL<38440> A_IWL<38439> A_IWL<38438> A_IWL<38437> A_IWL<38436> A_IWL<38435> A_IWL<38434> A_IWL<38433> A_IWL<38432> A_IWL<38431> A_IWL<38430> A_IWL<38429> A_IWL<38428> A_IWL<38427> A_IWL<38426> A_IWL<38425> A_IWL<38424> A_IWL<38423> A_IWL<38422> A_IWL<38421> A_IWL<38420> A_IWL<38419> A_IWL<38418> A_IWL<38417> A_IWL<38416> A_IWL<38415> A_IWL<38414> A_IWL<38413> A_IWL<38412> A_IWL<38411> A_IWL<38410> A_IWL<38409> A_IWL<38408> A_IWL<38407> A_IWL<38406> A_IWL<38405> A_IWL<38404> A_IWL<38403> A_IWL<38402> A_IWL<38401> A_IWL<38400> VDD_CORE VSS / RM_IHPSG13_8192x32_c4_1P_COLUMN_pcell_0 +XCOL<74> A_BLC<149> A_BLC<148> A_BLC_TOP<149> A_BLC_TOP<148> A_BLT<149> A_BLT<148> A_BLT_TOP<149> A_BLT_TOP<148> A_IWL<37887> A_IWL<37886> A_IWL<37885> A_IWL<37884> A_IWL<37883> A_IWL<37882> A_IWL<37881> A_IWL<37880> A_IWL<37879> A_IWL<37878> A_IWL<37877> A_IWL<37876> A_IWL<37875> A_IWL<37874> A_IWL<37873> A_IWL<37872> A_IWL<37871> A_IWL<37870> A_IWL<37869> A_IWL<37868> A_IWL<37867> A_IWL<37866> A_IWL<37865> A_IWL<37864> A_IWL<37863> A_IWL<37862> A_IWL<37861> A_IWL<37860> A_IWL<37859> A_IWL<37858> A_IWL<37857> A_IWL<37856> A_IWL<37855> A_IWL<37854> A_IWL<37853> A_IWL<37852> A_IWL<37851> A_IWL<37850> A_IWL<37849> A_IWL<37848> A_IWL<37847> A_IWL<37846> A_IWL<37845> A_IWL<37844> A_IWL<37843> A_IWL<37842> A_IWL<37841> A_IWL<37840> A_IWL<37839> A_IWL<37838> A_IWL<37837> A_IWL<37836> A_IWL<37835> A_IWL<37834> A_IWL<37833> A_IWL<37832> A_IWL<37831> A_IWL<37830> A_IWL<37829> A_IWL<37828> A_IWL<37827> A_IWL<37826> A_IWL<37825> A_IWL<37824> A_IWL<37823> A_IWL<37822> A_IWL<37821> A_IWL<37820> A_IWL<37819> A_IWL<37818> A_IWL<37817> A_IWL<37816> A_IWL<37815> A_IWL<37814> A_IWL<37813> A_IWL<37812> A_IWL<37811> A_IWL<37810> A_IWL<37809> A_IWL<37808> A_IWL<37807> A_IWL<37806> A_IWL<37805> A_IWL<37804> A_IWL<37803> A_IWL<37802> A_IWL<37801> A_IWL<37800> A_IWL<37799> A_IWL<37798> A_IWL<37797> A_IWL<37796> A_IWL<37795> A_IWL<37794> A_IWL<37793> A_IWL<37792> A_IWL<37791> A_IWL<37790> A_IWL<37789> A_IWL<37788> A_IWL<37787> A_IWL<37786> A_IWL<37785> A_IWL<37784> A_IWL<37783> A_IWL<37782> A_IWL<37781> A_IWL<37780> A_IWL<37779> A_IWL<37778> A_IWL<37777> A_IWL<37776> A_IWL<37775> A_IWL<37774> A_IWL<37773> A_IWL<37772> A_IWL<37771> A_IWL<37770> A_IWL<37769> A_IWL<37768> A_IWL<37767> A_IWL<37766> A_IWL<37765> A_IWL<37764> A_IWL<37763> A_IWL<37762> A_IWL<37761> A_IWL<37760> A_IWL<37759> A_IWL<37758> A_IWL<37757> A_IWL<37756> A_IWL<37755> A_IWL<37754> A_IWL<37753> A_IWL<37752> A_IWL<37751> A_IWL<37750> A_IWL<37749> A_IWL<37748> A_IWL<37747> A_IWL<37746> A_IWL<37745> A_IWL<37744> A_IWL<37743> A_IWL<37742> A_IWL<37741> A_IWL<37740> A_IWL<37739> A_IWL<37738> A_IWL<37737> A_IWL<37736> A_IWL<37735> A_IWL<37734> A_IWL<37733> A_IWL<37732> A_IWL<37731> A_IWL<37730> A_IWL<37729> A_IWL<37728> A_IWL<37727> A_IWL<37726> A_IWL<37725> A_IWL<37724> A_IWL<37723> A_IWL<37722> A_IWL<37721> A_IWL<37720> A_IWL<37719> A_IWL<37718> A_IWL<37717> A_IWL<37716> A_IWL<37715> A_IWL<37714> A_IWL<37713> A_IWL<37712> A_IWL<37711> A_IWL<37710> A_IWL<37709> A_IWL<37708> A_IWL<37707> A_IWL<37706> A_IWL<37705> A_IWL<37704> A_IWL<37703> A_IWL<37702> A_IWL<37701> A_IWL<37700> A_IWL<37699> A_IWL<37698> A_IWL<37697> A_IWL<37696> A_IWL<37695> A_IWL<37694> A_IWL<37693> A_IWL<37692> A_IWL<37691> A_IWL<37690> A_IWL<37689> A_IWL<37688> A_IWL<37687> A_IWL<37686> A_IWL<37685> A_IWL<37684> A_IWL<37683> A_IWL<37682> A_IWL<37681> A_IWL<37680> A_IWL<37679> A_IWL<37678> A_IWL<37677> A_IWL<37676> A_IWL<37675> A_IWL<37674> A_IWL<37673> A_IWL<37672> A_IWL<37671> A_IWL<37670> A_IWL<37669> A_IWL<37668> A_IWL<37667> A_IWL<37666> A_IWL<37665> A_IWL<37664> A_IWL<37663> A_IWL<37662> A_IWL<37661> A_IWL<37660> A_IWL<37659> A_IWL<37658> A_IWL<37657> A_IWL<37656> A_IWL<37655> A_IWL<37654> A_IWL<37653> A_IWL<37652> A_IWL<37651> A_IWL<37650> A_IWL<37649> A_IWL<37648> A_IWL<37647> A_IWL<37646> A_IWL<37645> A_IWL<37644> A_IWL<37643> A_IWL<37642> A_IWL<37641> A_IWL<37640> A_IWL<37639> A_IWL<37638> A_IWL<37637> A_IWL<37636> A_IWL<37635> A_IWL<37634> A_IWL<37633> A_IWL<37632> A_IWL<37631> A_IWL<37630> A_IWL<37629> A_IWL<37628> A_IWL<37627> A_IWL<37626> A_IWL<37625> A_IWL<37624> A_IWL<37623> A_IWL<37622> A_IWL<37621> A_IWL<37620> A_IWL<37619> A_IWL<37618> A_IWL<37617> A_IWL<37616> A_IWL<37615> A_IWL<37614> A_IWL<37613> A_IWL<37612> A_IWL<37611> A_IWL<37610> A_IWL<37609> A_IWL<37608> A_IWL<37607> A_IWL<37606> A_IWL<37605> A_IWL<37604> A_IWL<37603> A_IWL<37602> A_IWL<37601> A_IWL<37600> A_IWL<37599> A_IWL<37598> A_IWL<37597> A_IWL<37596> A_IWL<37595> A_IWL<37594> A_IWL<37593> A_IWL<37592> A_IWL<37591> A_IWL<37590> A_IWL<37589> A_IWL<37588> A_IWL<37587> A_IWL<37586> A_IWL<37585> A_IWL<37584> A_IWL<37583> A_IWL<37582> A_IWL<37581> A_IWL<37580> A_IWL<37579> A_IWL<37578> A_IWL<37577> A_IWL<37576> A_IWL<37575> A_IWL<37574> A_IWL<37573> A_IWL<37572> A_IWL<37571> A_IWL<37570> A_IWL<37569> A_IWL<37568> A_IWL<37567> A_IWL<37566> A_IWL<37565> A_IWL<37564> A_IWL<37563> A_IWL<37562> A_IWL<37561> A_IWL<37560> A_IWL<37559> A_IWL<37558> A_IWL<37557> A_IWL<37556> A_IWL<37555> A_IWL<37554> A_IWL<37553> A_IWL<37552> A_IWL<37551> A_IWL<37550> A_IWL<37549> A_IWL<37548> A_IWL<37547> A_IWL<37546> A_IWL<37545> A_IWL<37544> A_IWL<37543> A_IWL<37542> A_IWL<37541> A_IWL<37540> A_IWL<37539> A_IWL<37538> A_IWL<37537> A_IWL<37536> A_IWL<37535> A_IWL<37534> A_IWL<37533> A_IWL<37532> A_IWL<37531> A_IWL<37530> A_IWL<37529> A_IWL<37528> A_IWL<37527> A_IWL<37526> A_IWL<37525> A_IWL<37524> A_IWL<37523> A_IWL<37522> A_IWL<37521> A_IWL<37520> A_IWL<37519> A_IWL<37518> A_IWL<37517> A_IWL<37516> A_IWL<37515> A_IWL<37514> A_IWL<37513> A_IWL<37512> A_IWL<37511> A_IWL<37510> A_IWL<37509> A_IWL<37508> A_IWL<37507> A_IWL<37506> A_IWL<37505> A_IWL<37504> A_IWL<37503> A_IWL<37502> A_IWL<37501> A_IWL<37500> A_IWL<37499> A_IWL<37498> A_IWL<37497> A_IWL<37496> A_IWL<37495> A_IWL<37494> A_IWL<37493> A_IWL<37492> A_IWL<37491> A_IWL<37490> A_IWL<37489> A_IWL<37488> A_IWL<37487> A_IWL<37486> A_IWL<37485> A_IWL<37484> A_IWL<37483> A_IWL<37482> A_IWL<37481> A_IWL<37480> A_IWL<37479> A_IWL<37478> A_IWL<37477> A_IWL<37476> A_IWL<37475> A_IWL<37474> A_IWL<37473> A_IWL<37472> A_IWL<37471> A_IWL<37470> A_IWL<37469> A_IWL<37468> A_IWL<37467> A_IWL<37466> A_IWL<37465> A_IWL<37464> A_IWL<37463> A_IWL<37462> A_IWL<37461> A_IWL<37460> A_IWL<37459> A_IWL<37458> A_IWL<37457> A_IWL<37456> A_IWL<37455> A_IWL<37454> A_IWL<37453> A_IWL<37452> A_IWL<37451> A_IWL<37450> A_IWL<37449> A_IWL<37448> A_IWL<37447> A_IWL<37446> A_IWL<37445> A_IWL<37444> A_IWL<37443> A_IWL<37442> A_IWL<37441> A_IWL<37440> A_IWL<37439> A_IWL<37438> A_IWL<37437> A_IWL<37436> A_IWL<37435> A_IWL<37434> A_IWL<37433> A_IWL<37432> A_IWL<37431> A_IWL<37430> A_IWL<37429> A_IWL<37428> A_IWL<37427> A_IWL<37426> A_IWL<37425> A_IWL<37424> A_IWL<37423> A_IWL<37422> A_IWL<37421> A_IWL<37420> A_IWL<37419> A_IWL<37418> A_IWL<37417> A_IWL<37416> A_IWL<37415> A_IWL<37414> A_IWL<37413> A_IWL<37412> A_IWL<37411> A_IWL<37410> A_IWL<37409> A_IWL<37408> A_IWL<37407> A_IWL<37406> A_IWL<37405> A_IWL<37404> A_IWL<37403> A_IWL<37402> A_IWL<37401> A_IWL<37400> A_IWL<37399> A_IWL<37398> A_IWL<37397> A_IWL<37396> A_IWL<37395> A_IWL<37394> A_IWL<37393> A_IWL<37392> A_IWL<37391> A_IWL<37390> A_IWL<37389> A_IWL<37388> A_IWL<37387> A_IWL<37386> A_IWL<37385> A_IWL<37384> A_IWL<37383> A_IWL<37382> A_IWL<37381> A_IWL<37380> A_IWL<37379> A_IWL<37378> A_IWL<37377> A_IWL<37376> A_IWL<38399> A_IWL<38398> A_IWL<38397> A_IWL<38396> A_IWL<38395> A_IWL<38394> A_IWL<38393> A_IWL<38392> A_IWL<38391> A_IWL<38390> A_IWL<38389> A_IWL<38388> A_IWL<38387> A_IWL<38386> A_IWL<38385> A_IWL<38384> A_IWL<38383> A_IWL<38382> A_IWL<38381> A_IWL<38380> A_IWL<38379> A_IWL<38378> A_IWL<38377> A_IWL<38376> A_IWL<38375> A_IWL<38374> A_IWL<38373> A_IWL<38372> A_IWL<38371> A_IWL<38370> A_IWL<38369> A_IWL<38368> A_IWL<38367> A_IWL<38366> A_IWL<38365> A_IWL<38364> A_IWL<38363> A_IWL<38362> A_IWL<38361> A_IWL<38360> A_IWL<38359> A_IWL<38358> A_IWL<38357> A_IWL<38356> A_IWL<38355> A_IWL<38354> A_IWL<38353> A_IWL<38352> A_IWL<38351> A_IWL<38350> A_IWL<38349> A_IWL<38348> A_IWL<38347> A_IWL<38346> A_IWL<38345> A_IWL<38344> A_IWL<38343> A_IWL<38342> A_IWL<38341> A_IWL<38340> A_IWL<38339> A_IWL<38338> A_IWL<38337> A_IWL<38336> A_IWL<38335> A_IWL<38334> A_IWL<38333> A_IWL<38332> A_IWL<38331> A_IWL<38330> A_IWL<38329> A_IWL<38328> A_IWL<38327> A_IWL<38326> A_IWL<38325> A_IWL<38324> A_IWL<38323> A_IWL<38322> A_IWL<38321> A_IWL<38320> A_IWL<38319> A_IWL<38318> A_IWL<38317> A_IWL<38316> A_IWL<38315> A_IWL<38314> A_IWL<38313> A_IWL<38312> A_IWL<38311> A_IWL<38310> A_IWL<38309> A_IWL<38308> A_IWL<38307> A_IWL<38306> A_IWL<38305> A_IWL<38304> A_IWL<38303> A_IWL<38302> A_IWL<38301> A_IWL<38300> A_IWL<38299> A_IWL<38298> A_IWL<38297> A_IWL<38296> A_IWL<38295> A_IWL<38294> A_IWL<38293> A_IWL<38292> A_IWL<38291> A_IWL<38290> A_IWL<38289> A_IWL<38288> A_IWL<38287> A_IWL<38286> A_IWL<38285> A_IWL<38284> A_IWL<38283> A_IWL<38282> A_IWL<38281> A_IWL<38280> A_IWL<38279> A_IWL<38278> A_IWL<38277> A_IWL<38276> A_IWL<38275> A_IWL<38274> A_IWL<38273> A_IWL<38272> A_IWL<38271> A_IWL<38270> A_IWL<38269> A_IWL<38268> A_IWL<38267> A_IWL<38266> A_IWL<38265> A_IWL<38264> A_IWL<38263> A_IWL<38262> A_IWL<38261> A_IWL<38260> A_IWL<38259> A_IWL<38258> A_IWL<38257> A_IWL<38256> A_IWL<38255> A_IWL<38254> A_IWL<38253> A_IWL<38252> A_IWL<38251> A_IWL<38250> A_IWL<38249> A_IWL<38248> A_IWL<38247> A_IWL<38246> A_IWL<38245> A_IWL<38244> A_IWL<38243> A_IWL<38242> A_IWL<38241> A_IWL<38240> A_IWL<38239> A_IWL<38238> A_IWL<38237> A_IWL<38236> A_IWL<38235> A_IWL<38234> A_IWL<38233> A_IWL<38232> A_IWL<38231> A_IWL<38230> A_IWL<38229> A_IWL<38228> A_IWL<38227> A_IWL<38226> A_IWL<38225> A_IWL<38224> A_IWL<38223> A_IWL<38222> A_IWL<38221> A_IWL<38220> A_IWL<38219> A_IWL<38218> A_IWL<38217> A_IWL<38216> A_IWL<38215> A_IWL<38214> A_IWL<38213> A_IWL<38212> A_IWL<38211> A_IWL<38210> A_IWL<38209> A_IWL<38208> A_IWL<38207> A_IWL<38206> A_IWL<38205> A_IWL<38204> A_IWL<38203> A_IWL<38202> A_IWL<38201> A_IWL<38200> A_IWL<38199> A_IWL<38198> A_IWL<38197> A_IWL<38196> A_IWL<38195> A_IWL<38194> A_IWL<38193> A_IWL<38192> A_IWL<38191> A_IWL<38190> A_IWL<38189> A_IWL<38188> A_IWL<38187> A_IWL<38186> A_IWL<38185> A_IWL<38184> A_IWL<38183> A_IWL<38182> A_IWL<38181> A_IWL<38180> A_IWL<38179> A_IWL<38178> A_IWL<38177> A_IWL<38176> A_IWL<38175> A_IWL<38174> A_IWL<38173> A_IWL<38172> A_IWL<38171> A_IWL<38170> A_IWL<38169> A_IWL<38168> A_IWL<38167> A_IWL<38166> A_IWL<38165> A_IWL<38164> A_IWL<38163> A_IWL<38162> A_IWL<38161> A_IWL<38160> A_IWL<38159> A_IWL<38158> A_IWL<38157> A_IWL<38156> A_IWL<38155> A_IWL<38154> A_IWL<38153> A_IWL<38152> A_IWL<38151> A_IWL<38150> A_IWL<38149> A_IWL<38148> A_IWL<38147> A_IWL<38146> A_IWL<38145> A_IWL<38144> A_IWL<38143> A_IWL<38142> A_IWL<38141> A_IWL<38140> A_IWL<38139> A_IWL<38138> A_IWL<38137> A_IWL<38136> A_IWL<38135> A_IWL<38134> A_IWL<38133> A_IWL<38132> A_IWL<38131> A_IWL<38130> A_IWL<38129> A_IWL<38128> A_IWL<38127> A_IWL<38126> A_IWL<38125> A_IWL<38124> A_IWL<38123> A_IWL<38122> A_IWL<38121> A_IWL<38120> A_IWL<38119> A_IWL<38118> A_IWL<38117> A_IWL<38116> A_IWL<38115> A_IWL<38114> A_IWL<38113> A_IWL<38112> A_IWL<38111> A_IWL<38110> A_IWL<38109> A_IWL<38108> A_IWL<38107> A_IWL<38106> A_IWL<38105> A_IWL<38104> A_IWL<38103> A_IWL<38102> A_IWL<38101> A_IWL<38100> A_IWL<38099> A_IWL<38098> A_IWL<38097> A_IWL<38096> A_IWL<38095> A_IWL<38094> A_IWL<38093> A_IWL<38092> A_IWL<38091> A_IWL<38090> A_IWL<38089> A_IWL<38088> A_IWL<38087> A_IWL<38086> A_IWL<38085> A_IWL<38084> A_IWL<38083> A_IWL<38082> A_IWL<38081> A_IWL<38080> A_IWL<38079> A_IWL<38078> A_IWL<38077> A_IWL<38076> A_IWL<38075> A_IWL<38074> A_IWL<38073> A_IWL<38072> A_IWL<38071> A_IWL<38070> A_IWL<38069> A_IWL<38068> A_IWL<38067> A_IWL<38066> A_IWL<38065> A_IWL<38064> A_IWL<38063> A_IWL<38062> A_IWL<38061> A_IWL<38060> A_IWL<38059> A_IWL<38058> A_IWL<38057> A_IWL<38056> A_IWL<38055> A_IWL<38054> A_IWL<38053> A_IWL<38052> A_IWL<38051> A_IWL<38050> A_IWL<38049> A_IWL<38048> A_IWL<38047> A_IWL<38046> A_IWL<38045> A_IWL<38044> A_IWL<38043> A_IWL<38042> A_IWL<38041> A_IWL<38040> A_IWL<38039> A_IWL<38038> A_IWL<38037> A_IWL<38036> A_IWL<38035> A_IWL<38034> A_IWL<38033> A_IWL<38032> A_IWL<38031> A_IWL<38030> A_IWL<38029> A_IWL<38028> A_IWL<38027> A_IWL<38026> A_IWL<38025> A_IWL<38024> A_IWL<38023> A_IWL<38022> A_IWL<38021> A_IWL<38020> A_IWL<38019> A_IWL<38018> A_IWL<38017> A_IWL<38016> A_IWL<38015> A_IWL<38014> A_IWL<38013> A_IWL<38012> A_IWL<38011> A_IWL<38010> A_IWL<38009> A_IWL<38008> A_IWL<38007> A_IWL<38006> A_IWL<38005> A_IWL<38004> A_IWL<38003> A_IWL<38002> A_IWL<38001> A_IWL<38000> A_IWL<37999> A_IWL<37998> A_IWL<37997> A_IWL<37996> A_IWL<37995> A_IWL<37994> A_IWL<37993> A_IWL<37992> A_IWL<37991> A_IWL<37990> A_IWL<37989> A_IWL<37988> A_IWL<37987> A_IWL<37986> A_IWL<37985> A_IWL<37984> A_IWL<37983> A_IWL<37982> A_IWL<37981> A_IWL<37980> A_IWL<37979> A_IWL<37978> A_IWL<37977> A_IWL<37976> A_IWL<37975> A_IWL<37974> A_IWL<37973> A_IWL<37972> A_IWL<37971> A_IWL<37970> A_IWL<37969> A_IWL<37968> A_IWL<37967> A_IWL<37966> A_IWL<37965> A_IWL<37964> A_IWL<37963> A_IWL<37962> A_IWL<37961> A_IWL<37960> A_IWL<37959> A_IWL<37958> A_IWL<37957> A_IWL<37956> A_IWL<37955> A_IWL<37954> A_IWL<37953> A_IWL<37952> A_IWL<37951> A_IWL<37950> A_IWL<37949> A_IWL<37948> A_IWL<37947> A_IWL<37946> A_IWL<37945> A_IWL<37944> A_IWL<37943> A_IWL<37942> A_IWL<37941> A_IWL<37940> A_IWL<37939> A_IWL<37938> A_IWL<37937> A_IWL<37936> A_IWL<37935> A_IWL<37934> A_IWL<37933> A_IWL<37932> A_IWL<37931> A_IWL<37930> A_IWL<37929> A_IWL<37928> A_IWL<37927> A_IWL<37926> A_IWL<37925> A_IWL<37924> A_IWL<37923> A_IWL<37922> A_IWL<37921> A_IWL<37920> A_IWL<37919> A_IWL<37918> A_IWL<37917> A_IWL<37916> A_IWL<37915> A_IWL<37914> A_IWL<37913> A_IWL<37912> A_IWL<37911> A_IWL<37910> A_IWL<37909> A_IWL<37908> A_IWL<37907> A_IWL<37906> A_IWL<37905> A_IWL<37904> A_IWL<37903> A_IWL<37902> A_IWL<37901> A_IWL<37900> A_IWL<37899> A_IWL<37898> A_IWL<37897> A_IWL<37896> A_IWL<37895> A_IWL<37894> A_IWL<37893> A_IWL<37892> A_IWL<37891> A_IWL<37890> A_IWL<37889> A_IWL<37888> VDD_CORE VSS / RM_IHPSG13_8192x32_c4_1P_COLUMN_pcell_0 +XCOL<73> A_BLC<147> A_BLC<146> A_BLC_TOP<147> A_BLC_TOP<146> A_BLT<147> A_BLT<146> A_BLT_TOP<147> A_BLT_TOP<146> A_IWL<37375> A_IWL<37374> A_IWL<37373> A_IWL<37372> A_IWL<37371> A_IWL<37370> A_IWL<37369> A_IWL<37368> A_IWL<37367> A_IWL<37366> A_IWL<37365> A_IWL<37364> A_IWL<37363> A_IWL<37362> A_IWL<37361> A_IWL<37360> A_IWL<37359> A_IWL<37358> A_IWL<37357> A_IWL<37356> A_IWL<37355> A_IWL<37354> A_IWL<37353> A_IWL<37352> A_IWL<37351> A_IWL<37350> A_IWL<37349> A_IWL<37348> A_IWL<37347> A_IWL<37346> A_IWL<37345> A_IWL<37344> A_IWL<37343> A_IWL<37342> A_IWL<37341> A_IWL<37340> A_IWL<37339> A_IWL<37338> A_IWL<37337> A_IWL<37336> A_IWL<37335> A_IWL<37334> A_IWL<37333> A_IWL<37332> A_IWL<37331> A_IWL<37330> A_IWL<37329> A_IWL<37328> A_IWL<37327> A_IWL<37326> A_IWL<37325> A_IWL<37324> A_IWL<37323> A_IWL<37322> A_IWL<37321> A_IWL<37320> A_IWL<37319> A_IWL<37318> A_IWL<37317> A_IWL<37316> A_IWL<37315> A_IWL<37314> A_IWL<37313> A_IWL<37312> A_IWL<37311> A_IWL<37310> A_IWL<37309> A_IWL<37308> A_IWL<37307> A_IWL<37306> A_IWL<37305> A_IWL<37304> A_IWL<37303> A_IWL<37302> A_IWL<37301> A_IWL<37300> A_IWL<37299> A_IWL<37298> A_IWL<37297> A_IWL<37296> A_IWL<37295> A_IWL<37294> A_IWL<37293> A_IWL<37292> A_IWL<37291> A_IWL<37290> A_IWL<37289> A_IWL<37288> A_IWL<37287> A_IWL<37286> A_IWL<37285> A_IWL<37284> A_IWL<37283> A_IWL<37282> A_IWL<37281> A_IWL<37280> A_IWL<37279> A_IWL<37278> A_IWL<37277> A_IWL<37276> A_IWL<37275> A_IWL<37274> A_IWL<37273> A_IWL<37272> A_IWL<37271> A_IWL<37270> A_IWL<37269> A_IWL<37268> A_IWL<37267> A_IWL<37266> A_IWL<37265> A_IWL<37264> A_IWL<37263> A_IWL<37262> A_IWL<37261> A_IWL<37260> A_IWL<37259> A_IWL<37258> A_IWL<37257> A_IWL<37256> A_IWL<37255> A_IWL<37254> A_IWL<37253> A_IWL<37252> A_IWL<37251> A_IWL<37250> A_IWL<37249> A_IWL<37248> A_IWL<37247> A_IWL<37246> A_IWL<37245> A_IWL<37244> A_IWL<37243> A_IWL<37242> A_IWL<37241> A_IWL<37240> A_IWL<37239> A_IWL<37238> A_IWL<37237> A_IWL<37236> A_IWL<37235> A_IWL<37234> A_IWL<37233> A_IWL<37232> A_IWL<37231> A_IWL<37230> A_IWL<37229> A_IWL<37228> A_IWL<37227> A_IWL<37226> A_IWL<37225> A_IWL<37224> A_IWL<37223> A_IWL<37222> A_IWL<37221> A_IWL<37220> A_IWL<37219> A_IWL<37218> A_IWL<37217> A_IWL<37216> A_IWL<37215> A_IWL<37214> A_IWL<37213> A_IWL<37212> A_IWL<37211> A_IWL<37210> A_IWL<37209> A_IWL<37208> A_IWL<37207> A_IWL<37206> A_IWL<37205> A_IWL<37204> A_IWL<37203> A_IWL<37202> A_IWL<37201> A_IWL<37200> A_IWL<37199> A_IWL<37198> A_IWL<37197> A_IWL<37196> A_IWL<37195> A_IWL<37194> A_IWL<37193> A_IWL<37192> A_IWL<37191> A_IWL<37190> A_IWL<37189> A_IWL<37188> A_IWL<37187> A_IWL<37186> A_IWL<37185> A_IWL<37184> A_IWL<37183> A_IWL<37182> A_IWL<37181> A_IWL<37180> A_IWL<37179> A_IWL<37178> A_IWL<37177> A_IWL<37176> A_IWL<37175> A_IWL<37174> A_IWL<37173> A_IWL<37172> A_IWL<37171> A_IWL<37170> A_IWL<37169> A_IWL<37168> A_IWL<37167> A_IWL<37166> A_IWL<37165> A_IWL<37164> A_IWL<37163> A_IWL<37162> A_IWL<37161> A_IWL<37160> A_IWL<37159> A_IWL<37158> A_IWL<37157> A_IWL<37156> A_IWL<37155> A_IWL<37154> A_IWL<37153> A_IWL<37152> A_IWL<37151> A_IWL<37150> A_IWL<37149> A_IWL<37148> A_IWL<37147> A_IWL<37146> A_IWL<37145> A_IWL<37144> A_IWL<37143> A_IWL<37142> A_IWL<37141> A_IWL<37140> A_IWL<37139> A_IWL<37138> A_IWL<37137> A_IWL<37136> A_IWL<37135> A_IWL<37134> A_IWL<37133> A_IWL<37132> A_IWL<37131> A_IWL<37130> A_IWL<37129> A_IWL<37128> A_IWL<37127> A_IWL<37126> A_IWL<37125> A_IWL<37124> A_IWL<37123> A_IWL<37122> A_IWL<37121> A_IWL<37120> A_IWL<37119> A_IWL<37118> A_IWL<37117> A_IWL<37116> A_IWL<37115> A_IWL<37114> A_IWL<37113> A_IWL<37112> A_IWL<37111> A_IWL<37110> A_IWL<37109> A_IWL<37108> A_IWL<37107> A_IWL<37106> A_IWL<37105> A_IWL<37104> A_IWL<37103> A_IWL<37102> A_IWL<37101> A_IWL<37100> A_IWL<37099> A_IWL<37098> A_IWL<37097> A_IWL<37096> A_IWL<37095> A_IWL<37094> A_IWL<37093> A_IWL<37092> A_IWL<37091> A_IWL<37090> A_IWL<37089> A_IWL<37088> A_IWL<37087> A_IWL<37086> A_IWL<37085> A_IWL<37084> A_IWL<37083> A_IWL<37082> A_IWL<37081> A_IWL<37080> A_IWL<37079> A_IWL<37078> A_IWL<37077> A_IWL<37076> A_IWL<37075> A_IWL<37074> A_IWL<37073> A_IWL<37072> A_IWL<37071> A_IWL<37070> A_IWL<37069> A_IWL<37068> A_IWL<37067> A_IWL<37066> A_IWL<37065> A_IWL<37064> A_IWL<37063> A_IWL<37062> A_IWL<37061> A_IWL<37060> A_IWL<37059> A_IWL<37058> A_IWL<37057> A_IWL<37056> A_IWL<37055> A_IWL<37054> A_IWL<37053> A_IWL<37052> A_IWL<37051> A_IWL<37050> A_IWL<37049> A_IWL<37048> A_IWL<37047> A_IWL<37046> A_IWL<37045> A_IWL<37044> A_IWL<37043> A_IWL<37042> A_IWL<37041> A_IWL<37040> A_IWL<37039> A_IWL<37038> A_IWL<37037> A_IWL<37036> A_IWL<37035> A_IWL<37034> A_IWL<37033> A_IWL<37032> A_IWL<37031> A_IWL<37030> A_IWL<37029> A_IWL<37028> A_IWL<37027> A_IWL<37026> A_IWL<37025> A_IWL<37024> A_IWL<37023> A_IWL<37022> A_IWL<37021> A_IWL<37020> A_IWL<37019> A_IWL<37018> A_IWL<37017> A_IWL<37016> A_IWL<37015> A_IWL<37014> A_IWL<37013> A_IWL<37012> A_IWL<37011> A_IWL<37010> A_IWL<37009> A_IWL<37008> A_IWL<37007> A_IWL<37006> A_IWL<37005> A_IWL<37004> A_IWL<37003> A_IWL<37002> A_IWL<37001> A_IWL<37000> A_IWL<36999> A_IWL<36998> A_IWL<36997> A_IWL<36996> A_IWL<36995> A_IWL<36994> A_IWL<36993> A_IWL<36992> A_IWL<36991> A_IWL<36990> A_IWL<36989> A_IWL<36988> A_IWL<36987> A_IWL<36986> A_IWL<36985> A_IWL<36984> A_IWL<36983> A_IWL<36982> A_IWL<36981> A_IWL<36980> A_IWL<36979> A_IWL<36978> A_IWL<36977> A_IWL<36976> A_IWL<36975> A_IWL<36974> A_IWL<36973> A_IWL<36972> A_IWL<36971> A_IWL<36970> A_IWL<36969> A_IWL<36968> A_IWL<36967> A_IWL<36966> A_IWL<36965> A_IWL<36964> A_IWL<36963> A_IWL<36962> A_IWL<36961> A_IWL<36960> A_IWL<36959> A_IWL<36958> A_IWL<36957> A_IWL<36956> A_IWL<36955> A_IWL<36954> A_IWL<36953> A_IWL<36952> A_IWL<36951> A_IWL<36950> A_IWL<36949> A_IWL<36948> A_IWL<36947> A_IWL<36946> A_IWL<36945> A_IWL<36944> A_IWL<36943> A_IWL<36942> A_IWL<36941> A_IWL<36940> A_IWL<36939> A_IWL<36938> A_IWL<36937> A_IWL<36936> A_IWL<36935> A_IWL<36934> A_IWL<36933> A_IWL<36932> A_IWL<36931> A_IWL<36930> A_IWL<36929> A_IWL<36928> A_IWL<36927> A_IWL<36926> A_IWL<36925> A_IWL<36924> A_IWL<36923> A_IWL<36922> A_IWL<36921> A_IWL<36920> A_IWL<36919> A_IWL<36918> A_IWL<36917> A_IWL<36916> A_IWL<36915> A_IWL<36914> A_IWL<36913> A_IWL<36912> A_IWL<36911> A_IWL<36910> A_IWL<36909> A_IWL<36908> A_IWL<36907> A_IWL<36906> A_IWL<36905> A_IWL<36904> A_IWL<36903> A_IWL<36902> A_IWL<36901> A_IWL<36900> A_IWL<36899> A_IWL<36898> A_IWL<36897> A_IWL<36896> A_IWL<36895> A_IWL<36894> A_IWL<36893> A_IWL<36892> A_IWL<36891> A_IWL<36890> A_IWL<36889> A_IWL<36888> A_IWL<36887> A_IWL<36886> A_IWL<36885> A_IWL<36884> A_IWL<36883> A_IWL<36882> A_IWL<36881> A_IWL<36880> A_IWL<36879> A_IWL<36878> A_IWL<36877> A_IWL<36876> A_IWL<36875> A_IWL<36874> A_IWL<36873> A_IWL<36872> A_IWL<36871> A_IWL<36870> A_IWL<36869> A_IWL<36868> A_IWL<36867> A_IWL<36866> A_IWL<36865> A_IWL<36864> A_IWL<37887> A_IWL<37886> A_IWL<37885> A_IWL<37884> A_IWL<37883> A_IWL<37882> A_IWL<37881> A_IWL<37880> A_IWL<37879> A_IWL<37878> A_IWL<37877> A_IWL<37876> A_IWL<37875> A_IWL<37874> A_IWL<37873> A_IWL<37872> A_IWL<37871> A_IWL<37870> A_IWL<37869> A_IWL<37868> A_IWL<37867> A_IWL<37866> A_IWL<37865> A_IWL<37864> A_IWL<37863> A_IWL<37862> A_IWL<37861> A_IWL<37860> A_IWL<37859> A_IWL<37858> A_IWL<37857> A_IWL<37856> A_IWL<37855> A_IWL<37854> A_IWL<37853> A_IWL<37852> A_IWL<37851> A_IWL<37850> A_IWL<37849> A_IWL<37848> A_IWL<37847> A_IWL<37846> A_IWL<37845> A_IWL<37844> A_IWL<37843> A_IWL<37842> A_IWL<37841> A_IWL<37840> A_IWL<37839> A_IWL<37838> A_IWL<37837> A_IWL<37836> A_IWL<37835> A_IWL<37834> A_IWL<37833> A_IWL<37832> A_IWL<37831> A_IWL<37830> A_IWL<37829> A_IWL<37828> A_IWL<37827> A_IWL<37826> A_IWL<37825> A_IWL<37824> A_IWL<37823> A_IWL<37822> A_IWL<37821> A_IWL<37820> A_IWL<37819> A_IWL<37818> A_IWL<37817> A_IWL<37816> A_IWL<37815> A_IWL<37814> A_IWL<37813> A_IWL<37812> A_IWL<37811> A_IWL<37810> A_IWL<37809> A_IWL<37808> A_IWL<37807> A_IWL<37806> A_IWL<37805> A_IWL<37804> A_IWL<37803> A_IWL<37802> A_IWL<37801> A_IWL<37800> A_IWL<37799> A_IWL<37798> A_IWL<37797> A_IWL<37796> A_IWL<37795> A_IWL<37794> A_IWL<37793> A_IWL<37792> A_IWL<37791> A_IWL<37790> A_IWL<37789> A_IWL<37788> A_IWL<37787> A_IWL<37786> A_IWL<37785> A_IWL<37784> A_IWL<37783> A_IWL<37782> A_IWL<37781> A_IWL<37780> A_IWL<37779> A_IWL<37778> A_IWL<37777> A_IWL<37776> A_IWL<37775> A_IWL<37774> A_IWL<37773> A_IWL<37772> A_IWL<37771> A_IWL<37770> A_IWL<37769> A_IWL<37768> A_IWL<37767> A_IWL<37766> A_IWL<37765> A_IWL<37764> A_IWL<37763> A_IWL<37762> A_IWL<37761> A_IWL<37760> A_IWL<37759> A_IWL<37758> A_IWL<37757> A_IWL<37756> A_IWL<37755> A_IWL<37754> A_IWL<37753> A_IWL<37752> A_IWL<37751> A_IWL<37750> A_IWL<37749> A_IWL<37748> A_IWL<37747> A_IWL<37746> A_IWL<37745> A_IWL<37744> A_IWL<37743> A_IWL<37742> A_IWL<37741> A_IWL<37740> A_IWL<37739> A_IWL<37738> A_IWL<37737> A_IWL<37736> A_IWL<37735> A_IWL<37734> A_IWL<37733> A_IWL<37732> A_IWL<37731> A_IWL<37730> A_IWL<37729> A_IWL<37728> A_IWL<37727> A_IWL<37726> A_IWL<37725> A_IWL<37724> A_IWL<37723> A_IWL<37722> A_IWL<37721> A_IWL<37720> A_IWL<37719> A_IWL<37718> A_IWL<37717> A_IWL<37716> A_IWL<37715> A_IWL<37714> A_IWL<37713> A_IWL<37712> A_IWL<37711> A_IWL<37710> A_IWL<37709> A_IWL<37708> A_IWL<37707> A_IWL<37706> A_IWL<37705> A_IWL<37704> A_IWL<37703> A_IWL<37702> A_IWL<37701> A_IWL<37700> A_IWL<37699> A_IWL<37698> A_IWL<37697> A_IWL<37696> A_IWL<37695> A_IWL<37694> A_IWL<37693> A_IWL<37692> A_IWL<37691> A_IWL<37690> A_IWL<37689> A_IWL<37688> A_IWL<37687> A_IWL<37686> A_IWL<37685> A_IWL<37684> A_IWL<37683> A_IWL<37682> A_IWL<37681> A_IWL<37680> A_IWL<37679> A_IWL<37678> A_IWL<37677> A_IWL<37676> A_IWL<37675> A_IWL<37674> A_IWL<37673> A_IWL<37672> A_IWL<37671> A_IWL<37670> A_IWL<37669> A_IWL<37668> A_IWL<37667> A_IWL<37666> A_IWL<37665> A_IWL<37664> A_IWL<37663> A_IWL<37662> A_IWL<37661> A_IWL<37660> A_IWL<37659> A_IWL<37658> A_IWL<37657> A_IWL<37656> A_IWL<37655> A_IWL<37654> A_IWL<37653> A_IWL<37652> A_IWL<37651> A_IWL<37650> A_IWL<37649> A_IWL<37648> A_IWL<37647> A_IWL<37646> A_IWL<37645> A_IWL<37644> A_IWL<37643> A_IWL<37642> A_IWL<37641> A_IWL<37640> A_IWL<37639> A_IWL<37638> A_IWL<37637> A_IWL<37636> A_IWL<37635> A_IWL<37634> A_IWL<37633> A_IWL<37632> A_IWL<37631> A_IWL<37630> A_IWL<37629> A_IWL<37628> A_IWL<37627> A_IWL<37626> A_IWL<37625> A_IWL<37624> A_IWL<37623> A_IWL<37622> A_IWL<37621> A_IWL<37620> A_IWL<37619> A_IWL<37618> A_IWL<37617> A_IWL<37616> A_IWL<37615> A_IWL<37614> A_IWL<37613> A_IWL<37612> A_IWL<37611> A_IWL<37610> A_IWL<37609> A_IWL<37608> A_IWL<37607> A_IWL<37606> A_IWL<37605> A_IWL<37604> A_IWL<37603> A_IWL<37602> A_IWL<37601> A_IWL<37600> A_IWL<37599> A_IWL<37598> A_IWL<37597> A_IWL<37596> A_IWL<37595> A_IWL<37594> A_IWL<37593> A_IWL<37592> A_IWL<37591> A_IWL<37590> A_IWL<37589> A_IWL<37588> A_IWL<37587> A_IWL<37586> A_IWL<37585> A_IWL<37584> A_IWL<37583> A_IWL<37582> A_IWL<37581> A_IWL<37580> A_IWL<37579> A_IWL<37578> A_IWL<37577> A_IWL<37576> A_IWL<37575> A_IWL<37574> A_IWL<37573> A_IWL<37572> A_IWL<37571> A_IWL<37570> A_IWL<37569> A_IWL<37568> A_IWL<37567> A_IWL<37566> A_IWL<37565> A_IWL<37564> A_IWL<37563> A_IWL<37562> A_IWL<37561> A_IWL<37560> A_IWL<37559> A_IWL<37558> A_IWL<37557> A_IWL<37556> A_IWL<37555> A_IWL<37554> A_IWL<37553> A_IWL<37552> A_IWL<37551> A_IWL<37550> A_IWL<37549> A_IWL<37548> A_IWL<37547> A_IWL<37546> A_IWL<37545> A_IWL<37544> A_IWL<37543> A_IWL<37542> A_IWL<37541> A_IWL<37540> A_IWL<37539> A_IWL<37538> A_IWL<37537> A_IWL<37536> A_IWL<37535> A_IWL<37534> A_IWL<37533> A_IWL<37532> A_IWL<37531> A_IWL<37530> A_IWL<37529> A_IWL<37528> A_IWL<37527> A_IWL<37526> A_IWL<37525> A_IWL<37524> A_IWL<37523> A_IWL<37522> A_IWL<37521> A_IWL<37520> A_IWL<37519> A_IWL<37518> A_IWL<37517> A_IWL<37516> A_IWL<37515> A_IWL<37514> A_IWL<37513> A_IWL<37512> A_IWL<37511> A_IWL<37510> A_IWL<37509> A_IWL<37508> A_IWL<37507> A_IWL<37506> A_IWL<37505> A_IWL<37504> A_IWL<37503> A_IWL<37502> A_IWL<37501> A_IWL<37500> A_IWL<37499> A_IWL<37498> A_IWL<37497> A_IWL<37496> A_IWL<37495> A_IWL<37494> A_IWL<37493> A_IWL<37492> A_IWL<37491> A_IWL<37490> A_IWL<37489> A_IWL<37488> A_IWL<37487> A_IWL<37486> A_IWL<37485> A_IWL<37484> A_IWL<37483> A_IWL<37482> A_IWL<37481> A_IWL<37480> A_IWL<37479> A_IWL<37478> A_IWL<37477> A_IWL<37476> A_IWL<37475> A_IWL<37474> A_IWL<37473> A_IWL<37472> A_IWL<37471> A_IWL<37470> A_IWL<37469> A_IWL<37468> A_IWL<37467> A_IWL<37466> A_IWL<37465> A_IWL<37464> A_IWL<37463> A_IWL<37462> A_IWL<37461> A_IWL<37460> A_IWL<37459> A_IWL<37458> A_IWL<37457> A_IWL<37456> A_IWL<37455> A_IWL<37454> A_IWL<37453> A_IWL<37452> A_IWL<37451> A_IWL<37450> A_IWL<37449> A_IWL<37448> A_IWL<37447> A_IWL<37446> A_IWL<37445> A_IWL<37444> A_IWL<37443> A_IWL<37442> A_IWL<37441> A_IWL<37440> A_IWL<37439> A_IWL<37438> A_IWL<37437> A_IWL<37436> A_IWL<37435> A_IWL<37434> A_IWL<37433> A_IWL<37432> A_IWL<37431> A_IWL<37430> A_IWL<37429> A_IWL<37428> A_IWL<37427> A_IWL<37426> A_IWL<37425> A_IWL<37424> A_IWL<37423> A_IWL<37422> A_IWL<37421> A_IWL<37420> A_IWL<37419> A_IWL<37418> A_IWL<37417> A_IWL<37416> A_IWL<37415> A_IWL<37414> A_IWL<37413> A_IWL<37412> A_IWL<37411> A_IWL<37410> A_IWL<37409> A_IWL<37408> A_IWL<37407> A_IWL<37406> A_IWL<37405> A_IWL<37404> A_IWL<37403> A_IWL<37402> A_IWL<37401> A_IWL<37400> A_IWL<37399> A_IWL<37398> A_IWL<37397> A_IWL<37396> A_IWL<37395> A_IWL<37394> A_IWL<37393> A_IWL<37392> A_IWL<37391> A_IWL<37390> A_IWL<37389> A_IWL<37388> A_IWL<37387> A_IWL<37386> A_IWL<37385> A_IWL<37384> A_IWL<37383> A_IWL<37382> A_IWL<37381> A_IWL<37380> A_IWL<37379> A_IWL<37378> A_IWL<37377> A_IWL<37376> VDD_CORE VSS / RM_IHPSG13_8192x32_c4_1P_COLUMN_pcell_0 +XCOL<72> A_BLC<145> A_BLC<144> A_BLC_TOP<145> A_BLC_TOP<144> A_BLT<145> A_BLT<144> A_BLT_TOP<145> A_BLT_TOP<144> A_IWL<36863> A_IWL<36862> A_IWL<36861> A_IWL<36860> A_IWL<36859> A_IWL<36858> A_IWL<36857> A_IWL<36856> A_IWL<36855> A_IWL<36854> A_IWL<36853> A_IWL<36852> A_IWL<36851> A_IWL<36850> A_IWL<36849> A_IWL<36848> A_IWL<36847> A_IWL<36846> A_IWL<36845> A_IWL<36844> A_IWL<36843> A_IWL<36842> A_IWL<36841> A_IWL<36840> A_IWL<36839> A_IWL<36838> A_IWL<36837> A_IWL<36836> A_IWL<36835> A_IWL<36834> A_IWL<36833> A_IWL<36832> A_IWL<36831> A_IWL<36830> A_IWL<36829> A_IWL<36828> A_IWL<36827> A_IWL<36826> A_IWL<36825> A_IWL<36824> A_IWL<36823> A_IWL<36822> A_IWL<36821> A_IWL<36820> A_IWL<36819> A_IWL<36818> A_IWL<36817> A_IWL<36816> A_IWL<36815> A_IWL<36814> A_IWL<36813> A_IWL<36812> A_IWL<36811> A_IWL<36810> A_IWL<36809> A_IWL<36808> A_IWL<36807> A_IWL<36806> A_IWL<36805> A_IWL<36804> A_IWL<36803> A_IWL<36802> A_IWL<36801> A_IWL<36800> A_IWL<36799> A_IWL<36798> A_IWL<36797> A_IWL<36796> A_IWL<36795> A_IWL<36794> A_IWL<36793> A_IWL<36792> A_IWL<36791> A_IWL<36790> A_IWL<36789> A_IWL<36788> A_IWL<36787> A_IWL<36786> A_IWL<36785> A_IWL<36784> A_IWL<36783> A_IWL<36782> A_IWL<36781> A_IWL<36780> A_IWL<36779> A_IWL<36778> A_IWL<36777> A_IWL<36776> A_IWL<36775> A_IWL<36774> A_IWL<36773> A_IWL<36772> A_IWL<36771> A_IWL<36770> A_IWL<36769> A_IWL<36768> A_IWL<36767> A_IWL<36766> A_IWL<36765> A_IWL<36764> A_IWL<36763> A_IWL<36762> A_IWL<36761> A_IWL<36760> A_IWL<36759> A_IWL<36758> A_IWL<36757> A_IWL<36756> A_IWL<36755> A_IWL<36754> A_IWL<36753> A_IWL<36752> A_IWL<36751> A_IWL<36750> A_IWL<36749> A_IWL<36748> A_IWL<36747> A_IWL<36746> A_IWL<36745> A_IWL<36744> A_IWL<36743> A_IWL<36742> A_IWL<36741> A_IWL<36740> A_IWL<36739> A_IWL<36738> A_IWL<36737> A_IWL<36736> A_IWL<36735> A_IWL<36734> A_IWL<36733> A_IWL<36732> A_IWL<36731> A_IWL<36730> A_IWL<36729> A_IWL<36728> A_IWL<36727> A_IWL<36726> A_IWL<36725> A_IWL<36724> A_IWL<36723> A_IWL<36722> A_IWL<36721> A_IWL<36720> A_IWL<36719> A_IWL<36718> A_IWL<36717> A_IWL<36716> A_IWL<36715> A_IWL<36714> A_IWL<36713> A_IWL<36712> A_IWL<36711> A_IWL<36710> A_IWL<36709> A_IWL<36708> A_IWL<36707> A_IWL<36706> A_IWL<36705> A_IWL<36704> A_IWL<36703> A_IWL<36702> A_IWL<36701> A_IWL<36700> A_IWL<36699> A_IWL<36698> A_IWL<36697> A_IWL<36696> A_IWL<36695> A_IWL<36694> A_IWL<36693> A_IWL<36692> A_IWL<36691> A_IWL<36690> A_IWL<36689> A_IWL<36688> A_IWL<36687> A_IWL<36686> A_IWL<36685> A_IWL<36684> A_IWL<36683> A_IWL<36682> A_IWL<36681> A_IWL<36680> A_IWL<36679> A_IWL<36678> A_IWL<36677> A_IWL<36676> A_IWL<36675> A_IWL<36674> A_IWL<36673> A_IWL<36672> A_IWL<36671> A_IWL<36670> A_IWL<36669> A_IWL<36668> A_IWL<36667> A_IWL<36666> A_IWL<36665> A_IWL<36664> A_IWL<36663> A_IWL<36662> A_IWL<36661> A_IWL<36660> A_IWL<36659> A_IWL<36658> A_IWL<36657> A_IWL<36656> A_IWL<36655> A_IWL<36654> A_IWL<36653> A_IWL<36652> A_IWL<36651> A_IWL<36650> A_IWL<36649> A_IWL<36648> A_IWL<36647> A_IWL<36646> A_IWL<36645> A_IWL<36644> A_IWL<36643> A_IWL<36642> A_IWL<36641> A_IWL<36640> A_IWL<36639> A_IWL<36638> A_IWL<36637> A_IWL<36636> A_IWL<36635> A_IWL<36634> A_IWL<36633> A_IWL<36632> A_IWL<36631> A_IWL<36630> A_IWL<36629> A_IWL<36628> A_IWL<36627> A_IWL<36626> A_IWL<36625> A_IWL<36624> A_IWL<36623> A_IWL<36622> A_IWL<36621> A_IWL<36620> A_IWL<36619> A_IWL<36618> A_IWL<36617> A_IWL<36616> A_IWL<36615> A_IWL<36614> A_IWL<36613> A_IWL<36612> A_IWL<36611> A_IWL<36610> A_IWL<36609> A_IWL<36608> A_IWL<36607> A_IWL<36606> A_IWL<36605> A_IWL<36604> A_IWL<36603> A_IWL<36602> A_IWL<36601> A_IWL<36600> A_IWL<36599> A_IWL<36598> A_IWL<36597> A_IWL<36596> A_IWL<36595> A_IWL<36594> A_IWL<36593> A_IWL<36592> A_IWL<36591> A_IWL<36590> A_IWL<36589> A_IWL<36588> A_IWL<36587> A_IWL<36586> A_IWL<36585> A_IWL<36584> A_IWL<36583> A_IWL<36582> A_IWL<36581> A_IWL<36580> A_IWL<36579> A_IWL<36578> A_IWL<36577> A_IWL<36576> A_IWL<36575> A_IWL<36574> A_IWL<36573> A_IWL<36572> A_IWL<36571> A_IWL<36570> A_IWL<36569> A_IWL<36568> A_IWL<36567> A_IWL<36566> A_IWL<36565> A_IWL<36564> A_IWL<36563> A_IWL<36562> A_IWL<36561> A_IWL<36560> A_IWL<36559> A_IWL<36558> A_IWL<36557> A_IWL<36556> A_IWL<36555> A_IWL<36554> A_IWL<36553> A_IWL<36552> A_IWL<36551> A_IWL<36550> A_IWL<36549> A_IWL<36548> A_IWL<36547> A_IWL<36546> A_IWL<36545> A_IWL<36544> A_IWL<36543> A_IWL<36542> A_IWL<36541> A_IWL<36540> A_IWL<36539> A_IWL<36538> A_IWL<36537> A_IWL<36536> A_IWL<36535> A_IWL<36534> A_IWL<36533> A_IWL<36532> A_IWL<36531> A_IWL<36530> A_IWL<36529> A_IWL<36528> A_IWL<36527> A_IWL<36526> A_IWL<36525> A_IWL<36524> A_IWL<36523> A_IWL<36522> A_IWL<36521> A_IWL<36520> A_IWL<36519> A_IWL<36518> A_IWL<36517> A_IWL<36516> A_IWL<36515> A_IWL<36514> A_IWL<36513> A_IWL<36512> A_IWL<36511> A_IWL<36510> A_IWL<36509> A_IWL<36508> A_IWL<36507> A_IWL<36506> A_IWL<36505> A_IWL<36504> A_IWL<36503> A_IWL<36502> A_IWL<36501> A_IWL<36500> A_IWL<36499> A_IWL<36498> A_IWL<36497> A_IWL<36496> A_IWL<36495> A_IWL<36494> A_IWL<36493> A_IWL<36492> A_IWL<36491> A_IWL<36490> A_IWL<36489> A_IWL<36488> A_IWL<36487> A_IWL<36486> A_IWL<36485> A_IWL<36484> A_IWL<36483> A_IWL<36482> A_IWL<36481> A_IWL<36480> A_IWL<36479> A_IWL<36478> A_IWL<36477> A_IWL<36476> A_IWL<36475> A_IWL<36474> A_IWL<36473> A_IWL<36472> A_IWL<36471> A_IWL<36470> A_IWL<36469> A_IWL<36468> A_IWL<36467> A_IWL<36466> A_IWL<36465> A_IWL<36464> A_IWL<36463> A_IWL<36462> A_IWL<36461> A_IWL<36460> A_IWL<36459> A_IWL<36458> A_IWL<36457> A_IWL<36456> A_IWL<36455> A_IWL<36454> A_IWL<36453> A_IWL<36452> A_IWL<36451> A_IWL<36450> A_IWL<36449> A_IWL<36448> A_IWL<36447> A_IWL<36446> A_IWL<36445> A_IWL<36444> A_IWL<36443> A_IWL<36442> A_IWL<36441> A_IWL<36440> A_IWL<36439> A_IWL<36438> A_IWL<36437> A_IWL<36436> A_IWL<36435> A_IWL<36434> A_IWL<36433> A_IWL<36432> A_IWL<36431> A_IWL<36430> A_IWL<36429> A_IWL<36428> A_IWL<36427> A_IWL<36426> A_IWL<36425> A_IWL<36424> A_IWL<36423> A_IWL<36422> A_IWL<36421> A_IWL<36420> A_IWL<36419> A_IWL<36418> A_IWL<36417> A_IWL<36416> A_IWL<36415> A_IWL<36414> A_IWL<36413> A_IWL<36412> A_IWL<36411> A_IWL<36410> A_IWL<36409> A_IWL<36408> A_IWL<36407> A_IWL<36406> A_IWL<36405> A_IWL<36404> A_IWL<36403> A_IWL<36402> A_IWL<36401> A_IWL<36400> A_IWL<36399> A_IWL<36398> A_IWL<36397> A_IWL<36396> A_IWL<36395> A_IWL<36394> A_IWL<36393> A_IWL<36392> A_IWL<36391> A_IWL<36390> A_IWL<36389> A_IWL<36388> A_IWL<36387> A_IWL<36386> A_IWL<36385> A_IWL<36384> A_IWL<36383> A_IWL<36382> A_IWL<36381> A_IWL<36380> A_IWL<36379> A_IWL<36378> A_IWL<36377> A_IWL<36376> A_IWL<36375> A_IWL<36374> A_IWL<36373> A_IWL<36372> A_IWL<36371> A_IWL<36370> A_IWL<36369> A_IWL<36368> A_IWL<36367> A_IWL<36366> A_IWL<36365> A_IWL<36364> A_IWL<36363> A_IWL<36362> A_IWL<36361> A_IWL<36360> A_IWL<36359> A_IWL<36358> A_IWL<36357> A_IWL<36356> A_IWL<36355> A_IWL<36354> A_IWL<36353> A_IWL<36352> A_IWL<37375> A_IWL<37374> A_IWL<37373> A_IWL<37372> A_IWL<37371> A_IWL<37370> A_IWL<37369> A_IWL<37368> A_IWL<37367> A_IWL<37366> A_IWL<37365> A_IWL<37364> A_IWL<37363> A_IWL<37362> A_IWL<37361> A_IWL<37360> A_IWL<37359> A_IWL<37358> A_IWL<37357> A_IWL<37356> A_IWL<37355> A_IWL<37354> A_IWL<37353> A_IWL<37352> A_IWL<37351> A_IWL<37350> A_IWL<37349> A_IWL<37348> A_IWL<37347> A_IWL<37346> A_IWL<37345> A_IWL<37344> A_IWL<37343> A_IWL<37342> A_IWL<37341> A_IWL<37340> A_IWL<37339> A_IWL<37338> A_IWL<37337> A_IWL<37336> A_IWL<37335> A_IWL<37334> A_IWL<37333> A_IWL<37332> A_IWL<37331> A_IWL<37330> A_IWL<37329> A_IWL<37328> A_IWL<37327> A_IWL<37326> A_IWL<37325> A_IWL<37324> A_IWL<37323> A_IWL<37322> A_IWL<37321> A_IWL<37320> A_IWL<37319> A_IWL<37318> A_IWL<37317> A_IWL<37316> A_IWL<37315> A_IWL<37314> A_IWL<37313> A_IWL<37312> A_IWL<37311> A_IWL<37310> A_IWL<37309> A_IWL<37308> A_IWL<37307> A_IWL<37306> A_IWL<37305> A_IWL<37304> A_IWL<37303> A_IWL<37302> A_IWL<37301> A_IWL<37300> A_IWL<37299> A_IWL<37298> A_IWL<37297> A_IWL<37296> A_IWL<37295> A_IWL<37294> A_IWL<37293> A_IWL<37292> A_IWL<37291> A_IWL<37290> A_IWL<37289> A_IWL<37288> A_IWL<37287> A_IWL<37286> A_IWL<37285> A_IWL<37284> A_IWL<37283> A_IWL<37282> A_IWL<37281> A_IWL<37280> A_IWL<37279> A_IWL<37278> A_IWL<37277> A_IWL<37276> A_IWL<37275> A_IWL<37274> A_IWL<37273> A_IWL<37272> A_IWL<37271> A_IWL<37270> A_IWL<37269> A_IWL<37268> A_IWL<37267> A_IWL<37266> A_IWL<37265> A_IWL<37264> A_IWL<37263> A_IWL<37262> A_IWL<37261> A_IWL<37260> A_IWL<37259> A_IWL<37258> A_IWL<37257> A_IWL<37256> A_IWL<37255> A_IWL<37254> A_IWL<37253> A_IWL<37252> A_IWL<37251> A_IWL<37250> A_IWL<37249> A_IWL<37248> A_IWL<37247> A_IWL<37246> A_IWL<37245> A_IWL<37244> A_IWL<37243> A_IWL<37242> A_IWL<37241> A_IWL<37240> A_IWL<37239> A_IWL<37238> A_IWL<37237> A_IWL<37236> A_IWL<37235> A_IWL<37234> A_IWL<37233> A_IWL<37232> A_IWL<37231> A_IWL<37230> A_IWL<37229> A_IWL<37228> A_IWL<37227> A_IWL<37226> A_IWL<37225> A_IWL<37224> A_IWL<37223> A_IWL<37222> A_IWL<37221> A_IWL<37220> A_IWL<37219> A_IWL<37218> A_IWL<37217> A_IWL<37216> A_IWL<37215> A_IWL<37214> A_IWL<37213> A_IWL<37212> A_IWL<37211> A_IWL<37210> A_IWL<37209> A_IWL<37208> A_IWL<37207> A_IWL<37206> A_IWL<37205> A_IWL<37204> A_IWL<37203> A_IWL<37202> A_IWL<37201> A_IWL<37200> A_IWL<37199> A_IWL<37198> A_IWL<37197> A_IWL<37196> A_IWL<37195> A_IWL<37194> A_IWL<37193> A_IWL<37192> A_IWL<37191> A_IWL<37190> A_IWL<37189> A_IWL<37188> A_IWL<37187> A_IWL<37186> A_IWL<37185> A_IWL<37184> A_IWL<37183> A_IWL<37182> A_IWL<37181> A_IWL<37180> A_IWL<37179> A_IWL<37178> A_IWL<37177> A_IWL<37176> A_IWL<37175> A_IWL<37174> A_IWL<37173> A_IWL<37172> A_IWL<37171> A_IWL<37170> A_IWL<37169> A_IWL<37168> A_IWL<37167> A_IWL<37166> A_IWL<37165> A_IWL<37164> A_IWL<37163> A_IWL<37162> A_IWL<37161> A_IWL<37160> A_IWL<37159> A_IWL<37158> A_IWL<37157> A_IWL<37156> A_IWL<37155> A_IWL<37154> A_IWL<37153> A_IWL<37152> A_IWL<37151> A_IWL<37150> A_IWL<37149> A_IWL<37148> A_IWL<37147> A_IWL<37146> A_IWL<37145> A_IWL<37144> A_IWL<37143> A_IWL<37142> A_IWL<37141> A_IWL<37140> A_IWL<37139> A_IWL<37138> A_IWL<37137> A_IWL<37136> A_IWL<37135> A_IWL<37134> A_IWL<37133> A_IWL<37132> A_IWL<37131> A_IWL<37130> A_IWL<37129> A_IWL<37128> A_IWL<37127> A_IWL<37126> A_IWL<37125> A_IWL<37124> A_IWL<37123> A_IWL<37122> A_IWL<37121> A_IWL<37120> A_IWL<37119> A_IWL<37118> A_IWL<37117> A_IWL<37116> A_IWL<37115> A_IWL<37114> A_IWL<37113> A_IWL<37112> A_IWL<37111> A_IWL<37110> A_IWL<37109> A_IWL<37108> A_IWL<37107> A_IWL<37106> A_IWL<37105> A_IWL<37104> A_IWL<37103> A_IWL<37102> A_IWL<37101> A_IWL<37100> A_IWL<37099> A_IWL<37098> A_IWL<37097> A_IWL<37096> A_IWL<37095> A_IWL<37094> A_IWL<37093> A_IWL<37092> A_IWL<37091> A_IWL<37090> A_IWL<37089> A_IWL<37088> A_IWL<37087> A_IWL<37086> A_IWL<37085> A_IWL<37084> A_IWL<37083> A_IWL<37082> A_IWL<37081> A_IWL<37080> A_IWL<37079> A_IWL<37078> A_IWL<37077> A_IWL<37076> A_IWL<37075> A_IWL<37074> A_IWL<37073> A_IWL<37072> A_IWL<37071> A_IWL<37070> A_IWL<37069> A_IWL<37068> A_IWL<37067> A_IWL<37066> A_IWL<37065> A_IWL<37064> A_IWL<37063> A_IWL<37062> A_IWL<37061> A_IWL<37060> A_IWL<37059> A_IWL<37058> A_IWL<37057> A_IWL<37056> A_IWL<37055> A_IWL<37054> A_IWL<37053> A_IWL<37052> A_IWL<37051> A_IWL<37050> A_IWL<37049> A_IWL<37048> A_IWL<37047> A_IWL<37046> A_IWL<37045> A_IWL<37044> A_IWL<37043> A_IWL<37042> A_IWL<37041> A_IWL<37040> A_IWL<37039> A_IWL<37038> A_IWL<37037> A_IWL<37036> A_IWL<37035> A_IWL<37034> A_IWL<37033> A_IWL<37032> A_IWL<37031> A_IWL<37030> A_IWL<37029> A_IWL<37028> A_IWL<37027> A_IWL<37026> A_IWL<37025> A_IWL<37024> A_IWL<37023> A_IWL<37022> A_IWL<37021> A_IWL<37020> A_IWL<37019> A_IWL<37018> A_IWL<37017> A_IWL<37016> A_IWL<37015> A_IWL<37014> A_IWL<37013> A_IWL<37012> A_IWL<37011> A_IWL<37010> A_IWL<37009> A_IWL<37008> A_IWL<37007> A_IWL<37006> A_IWL<37005> A_IWL<37004> A_IWL<37003> A_IWL<37002> A_IWL<37001> A_IWL<37000> A_IWL<36999> A_IWL<36998> A_IWL<36997> A_IWL<36996> A_IWL<36995> A_IWL<36994> A_IWL<36993> A_IWL<36992> A_IWL<36991> A_IWL<36990> A_IWL<36989> A_IWL<36988> A_IWL<36987> A_IWL<36986> A_IWL<36985> A_IWL<36984> A_IWL<36983> A_IWL<36982> A_IWL<36981> A_IWL<36980> A_IWL<36979> A_IWL<36978> A_IWL<36977> A_IWL<36976> A_IWL<36975> A_IWL<36974> A_IWL<36973> A_IWL<36972> A_IWL<36971> A_IWL<36970> A_IWL<36969> A_IWL<36968> A_IWL<36967> A_IWL<36966> A_IWL<36965> A_IWL<36964> A_IWL<36963> A_IWL<36962> A_IWL<36961> A_IWL<36960> A_IWL<36959> A_IWL<36958> A_IWL<36957> A_IWL<36956> A_IWL<36955> A_IWL<36954> A_IWL<36953> A_IWL<36952> A_IWL<36951> A_IWL<36950> A_IWL<36949> A_IWL<36948> A_IWL<36947> A_IWL<36946> A_IWL<36945> A_IWL<36944> A_IWL<36943> A_IWL<36942> A_IWL<36941> A_IWL<36940> A_IWL<36939> A_IWL<36938> A_IWL<36937> A_IWL<36936> A_IWL<36935> A_IWL<36934> A_IWL<36933> A_IWL<36932> A_IWL<36931> A_IWL<36930> A_IWL<36929> A_IWL<36928> A_IWL<36927> A_IWL<36926> A_IWL<36925> A_IWL<36924> A_IWL<36923> A_IWL<36922> A_IWL<36921> A_IWL<36920> A_IWL<36919> A_IWL<36918> A_IWL<36917> A_IWL<36916> A_IWL<36915> A_IWL<36914> A_IWL<36913> A_IWL<36912> A_IWL<36911> A_IWL<36910> A_IWL<36909> A_IWL<36908> A_IWL<36907> A_IWL<36906> A_IWL<36905> A_IWL<36904> A_IWL<36903> A_IWL<36902> A_IWL<36901> A_IWL<36900> A_IWL<36899> A_IWL<36898> A_IWL<36897> A_IWL<36896> A_IWL<36895> A_IWL<36894> A_IWL<36893> A_IWL<36892> A_IWL<36891> A_IWL<36890> A_IWL<36889> A_IWL<36888> A_IWL<36887> A_IWL<36886> A_IWL<36885> A_IWL<36884> A_IWL<36883> A_IWL<36882> A_IWL<36881> A_IWL<36880> A_IWL<36879> A_IWL<36878> A_IWL<36877> A_IWL<36876> A_IWL<36875> A_IWL<36874> A_IWL<36873> A_IWL<36872> A_IWL<36871> A_IWL<36870> A_IWL<36869> A_IWL<36868> A_IWL<36867> A_IWL<36866> A_IWL<36865> A_IWL<36864> VDD_CORE VSS / RM_IHPSG13_8192x32_c4_1P_COLUMN_pcell_0 +XCOL<71> A_BLC<143> A_BLC<142> A_BLC_TOP<143> A_BLC_TOP<142> A_BLT<143> A_BLT<142> A_BLT_TOP<143> A_BLT_TOP<142> A_IWL<36351> A_IWL<36350> A_IWL<36349> A_IWL<36348> A_IWL<36347> A_IWL<36346> A_IWL<36345> A_IWL<36344> A_IWL<36343> A_IWL<36342> A_IWL<36341> A_IWL<36340> A_IWL<36339> A_IWL<36338> A_IWL<36337> A_IWL<36336> A_IWL<36335> A_IWL<36334> A_IWL<36333> A_IWL<36332> A_IWL<36331> A_IWL<36330> A_IWL<36329> A_IWL<36328> A_IWL<36327> A_IWL<36326> A_IWL<36325> A_IWL<36324> A_IWL<36323> A_IWL<36322> A_IWL<36321> A_IWL<36320> A_IWL<36319> A_IWL<36318> A_IWL<36317> A_IWL<36316> A_IWL<36315> A_IWL<36314> A_IWL<36313> A_IWL<36312> A_IWL<36311> A_IWL<36310> A_IWL<36309> A_IWL<36308> A_IWL<36307> A_IWL<36306> A_IWL<36305> A_IWL<36304> A_IWL<36303> A_IWL<36302> A_IWL<36301> A_IWL<36300> A_IWL<36299> A_IWL<36298> A_IWL<36297> A_IWL<36296> A_IWL<36295> A_IWL<36294> A_IWL<36293> A_IWL<36292> A_IWL<36291> A_IWL<36290> A_IWL<36289> A_IWL<36288> A_IWL<36287> A_IWL<36286> A_IWL<36285> A_IWL<36284> A_IWL<36283> A_IWL<36282> A_IWL<36281> A_IWL<36280> A_IWL<36279> A_IWL<36278> A_IWL<36277> A_IWL<36276> A_IWL<36275> A_IWL<36274> A_IWL<36273> A_IWL<36272> A_IWL<36271> A_IWL<36270> A_IWL<36269> A_IWL<36268> A_IWL<36267> A_IWL<36266> A_IWL<36265> A_IWL<36264> A_IWL<36263> A_IWL<36262> A_IWL<36261> A_IWL<36260> A_IWL<36259> A_IWL<36258> A_IWL<36257> A_IWL<36256> A_IWL<36255> A_IWL<36254> A_IWL<36253> A_IWL<36252> A_IWL<36251> A_IWL<36250> A_IWL<36249> A_IWL<36248> A_IWL<36247> A_IWL<36246> A_IWL<36245> A_IWL<36244> A_IWL<36243> A_IWL<36242> A_IWL<36241> A_IWL<36240> A_IWL<36239> A_IWL<36238> A_IWL<36237> A_IWL<36236> A_IWL<36235> A_IWL<36234> A_IWL<36233> A_IWL<36232> A_IWL<36231> A_IWL<36230> A_IWL<36229> A_IWL<36228> A_IWL<36227> A_IWL<36226> A_IWL<36225> A_IWL<36224> A_IWL<36223> A_IWL<36222> A_IWL<36221> A_IWL<36220> A_IWL<36219> A_IWL<36218> A_IWL<36217> A_IWL<36216> A_IWL<36215> A_IWL<36214> A_IWL<36213> A_IWL<36212> A_IWL<36211> A_IWL<36210> A_IWL<36209> A_IWL<36208> A_IWL<36207> A_IWL<36206> A_IWL<36205> A_IWL<36204> A_IWL<36203> A_IWL<36202> A_IWL<36201> A_IWL<36200> A_IWL<36199> A_IWL<36198> A_IWL<36197> A_IWL<36196> A_IWL<36195> A_IWL<36194> A_IWL<36193> A_IWL<36192> A_IWL<36191> A_IWL<36190> A_IWL<36189> A_IWL<36188> A_IWL<36187> A_IWL<36186> A_IWL<36185> A_IWL<36184> A_IWL<36183> A_IWL<36182> A_IWL<36181> A_IWL<36180> A_IWL<36179> A_IWL<36178> A_IWL<36177> A_IWL<36176> A_IWL<36175> A_IWL<36174> A_IWL<36173> A_IWL<36172> A_IWL<36171> A_IWL<36170> A_IWL<36169> A_IWL<36168> A_IWL<36167> A_IWL<36166> A_IWL<36165> A_IWL<36164> A_IWL<36163> A_IWL<36162> A_IWL<36161> A_IWL<36160> A_IWL<36159> A_IWL<36158> A_IWL<36157> A_IWL<36156> A_IWL<36155> A_IWL<36154> A_IWL<36153> A_IWL<36152> A_IWL<36151> A_IWL<36150> A_IWL<36149> A_IWL<36148> A_IWL<36147> A_IWL<36146> A_IWL<36145> A_IWL<36144> A_IWL<36143> A_IWL<36142> A_IWL<36141> A_IWL<36140> A_IWL<36139> A_IWL<36138> A_IWL<36137> A_IWL<36136> A_IWL<36135> A_IWL<36134> A_IWL<36133> A_IWL<36132> A_IWL<36131> A_IWL<36130> A_IWL<36129> A_IWL<36128> A_IWL<36127> A_IWL<36126> A_IWL<36125> A_IWL<36124> A_IWL<36123> A_IWL<36122> A_IWL<36121> A_IWL<36120> A_IWL<36119> A_IWL<36118> A_IWL<36117> A_IWL<36116> A_IWL<36115> A_IWL<36114> A_IWL<36113> A_IWL<36112> A_IWL<36111> A_IWL<36110> A_IWL<36109> A_IWL<36108> A_IWL<36107> A_IWL<36106> A_IWL<36105> A_IWL<36104> A_IWL<36103> A_IWL<36102> A_IWL<36101> A_IWL<36100> A_IWL<36099> A_IWL<36098> A_IWL<36097> A_IWL<36096> A_IWL<36095> A_IWL<36094> A_IWL<36093> A_IWL<36092> A_IWL<36091> A_IWL<36090> A_IWL<36089> A_IWL<36088> A_IWL<36087> A_IWL<36086> A_IWL<36085> A_IWL<36084> A_IWL<36083> A_IWL<36082> A_IWL<36081> A_IWL<36080> A_IWL<36079> A_IWL<36078> A_IWL<36077> A_IWL<36076> A_IWL<36075> A_IWL<36074> A_IWL<36073> A_IWL<36072> A_IWL<36071> A_IWL<36070> A_IWL<36069> A_IWL<36068> A_IWL<36067> A_IWL<36066> A_IWL<36065> A_IWL<36064> A_IWL<36063> A_IWL<36062> A_IWL<36061> A_IWL<36060> A_IWL<36059> A_IWL<36058> A_IWL<36057> A_IWL<36056> A_IWL<36055> A_IWL<36054> A_IWL<36053> A_IWL<36052> A_IWL<36051> A_IWL<36050> A_IWL<36049> A_IWL<36048> A_IWL<36047> A_IWL<36046> A_IWL<36045> A_IWL<36044> A_IWL<36043> A_IWL<36042> A_IWL<36041> A_IWL<36040> A_IWL<36039> A_IWL<36038> A_IWL<36037> A_IWL<36036> A_IWL<36035> A_IWL<36034> A_IWL<36033> A_IWL<36032> A_IWL<36031> A_IWL<36030> A_IWL<36029> A_IWL<36028> A_IWL<36027> A_IWL<36026> A_IWL<36025> A_IWL<36024> A_IWL<36023> A_IWL<36022> A_IWL<36021> A_IWL<36020> A_IWL<36019> A_IWL<36018> A_IWL<36017> A_IWL<36016> A_IWL<36015> A_IWL<36014> A_IWL<36013> A_IWL<36012> A_IWL<36011> A_IWL<36010> A_IWL<36009> A_IWL<36008> A_IWL<36007> A_IWL<36006> A_IWL<36005> A_IWL<36004> A_IWL<36003> A_IWL<36002> A_IWL<36001> A_IWL<36000> A_IWL<35999> A_IWL<35998> A_IWL<35997> A_IWL<35996> A_IWL<35995> A_IWL<35994> A_IWL<35993> A_IWL<35992> A_IWL<35991> A_IWL<35990> A_IWL<35989> A_IWL<35988> A_IWL<35987> A_IWL<35986> A_IWL<35985> A_IWL<35984> A_IWL<35983> A_IWL<35982> A_IWL<35981> A_IWL<35980> A_IWL<35979> A_IWL<35978> A_IWL<35977> A_IWL<35976> A_IWL<35975> A_IWL<35974> A_IWL<35973> A_IWL<35972> A_IWL<35971> A_IWL<35970> A_IWL<35969> A_IWL<35968> A_IWL<35967> A_IWL<35966> A_IWL<35965> A_IWL<35964> A_IWL<35963> A_IWL<35962> A_IWL<35961> A_IWL<35960> A_IWL<35959> A_IWL<35958> A_IWL<35957> A_IWL<35956> A_IWL<35955> A_IWL<35954> A_IWL<35953> A_IWL<35952> A_IWL<35951> A_IWL<35950> A_IWL<35949> A_IWL<35948> A_IWL<35947> A_IWL<35946> A_IWL<35945> A_IWL<35944> A_IWL<35943> A_IWL<35942> A_IWL<35941> A_IWL<35940> A_IWL<35939> A_IWL<35938> A_IWL<35937> A_IWL<35936> A_IWL<35935> A_IWL<35934> A_IWL<35933> A_IWL<35932> A_IWL<35931> A_IWL<35930> A_IWL<35929> A_IWL<35928> A_IWL<35927> A_IWL<35926> A_IWL<35925> A_IWL<35924> A_IWL<35923> A_IWL<35922> A_IWL<35921> A_IWL<35920> A_IWL<35919> A_IWL<35918> A_IWL<35917> A_IWL<35916> A_IWL<35915> A_IWL<35914> A_IWL<35913> A_IWL<35912> A_IWL<35911> A_IWL<35910> A_IWL<35909> A_IWL<35908> A_IWL<35907> A_IWL<35906> A_IWL<35905> A_IWL<35904> A_IWL<35903> A_IWL<35902> A_IWL<35901> A_IWL<35900> A_IWL<35899> A_IWL<35898> A_IWL<35897> A_IWL<35896> A_IWL<35895> A_IWL<35894> A_IWL<35893> A_IWL<35892> A_IWL<35891> A_IWL<35890> A_IWL<35889> A_IWL<35888> A_IWL<35887> A_IWL<35886> A_IWL<35885> A_IWL<35884> A_IWL<35883> A_IWL<35882> A_IWL<35881> A_IWL<35880> A_IWL<35879> A_IWL<35878> A_IWL<35877> A_IWL<35876> A_IWL<35875> A_IWL<35874> A_IWL<35873> A_IWL<35872> A_IWL<35871> A_IWL<35870> A_IWL<35869> A_IWL<35868> A_IWL<35867> A_IWL<35866> A_IWL<35865> A_IWL<35864> A_IWL<35863> A_IWL<35862> A_IWL<35861> A_IWL<35860> A_IWL<35859> A_IWL<35858> A_IWL<35857> A_IWL<35856> A_IWL<35855> A_IWL<35854> A_IWL<35853> A_IWL<35852> A_IWL<35851> A_IWL<35850> A_IWL<35849> A_IWL<35848> A_IWL<35847> A_IWL<35846> A_IWL<35845> A_IWL<35844> A_IWL<35843> A_IWL<35842> A_IWL<35841> A_IWL<35840> A_IWL<36863> A_IWL<36862> A_IWL<36861> A_IWL<36860> A_IWL<36859> A_IWL<36858> A_IWL<36857> A_IWL<36856> A_IWL<36855> A_IWL<36854> A_IWL<36853> A_IWL<36852> A_IWL<36851> A_IWL<36850> A_IWL<36849> A_IWL<36848> A_IWL<36847> A_IWL<36846> A_IWL<36845> A_IWL<36844> A_IWL<36843> A_IWL<36842> A_IWL<36841> A_IWL<36840> A_IWL<36839> A_IWL<36838> A_IWL<36837> A_IWL<36836> A_IWL<36835> A_IWL<36834> A_IWL<36833> A_IWL<36832> A_IWL<36831> A_IWL<36830> A_IWL<36829> A_IWL<36828> A_IWL<36827> A_IWL<36826> A_IWL<36825> A_IWL<36824> A_IWL<36823> A_IWL<36822> A_IWL<36821> A_IWL<36820> A_IWL<36819> A_IWL<36818> A_IWL<36817> A_IWL<36816> A_IWL<36815> A_IWL<36814> A_IWL<36813> A_IWL<36812> A_IWL<36811> A_IWL<36810> A_IWL<36809> A_IWL<36808> A_IWL<36807> A_IWL<36806> A_IWL<36805> A_IWL<36804> A_IWL<36803> A_IWL<36802> A_IWL<36801> A_IWL<36800> A_IWL<36799> A_IWL<36798> A_IWL<36797> A_IWL<36796> A_IWL<36795> A_IWL<36794> A_IWL<36793> A_IWL<36792> A_IWL<36791> A_IWL<36790> A_IWL<36789> A_IWL<36788> A_IWL<36787> A_IWL<36786> A_IWL<36785> A_IWL<36784> A_IWL<36783> A_IWL<36782> A_IWL<36781> A_IWL<36780> A_IWL<36779> A_IWL<36778> A_IWL<36777> A_IWL<36776> A_IWL<36775> A_IWL<36774> A_IWL<36773> A_IWL<36772> A_IWL<36771> A_IWL<36770> A_IWL<36769> A_IWL<36768> A_IWL<36767> A_IWL<36766> A_IWL<36765> A_IWL<36764> A_IWL<36763> A_IWL<36762> A_IWL<36761> A_IWL<36760> A_IWL<36759> A_IWL<36758> A_IWL<36757> A_IWL<36756> A_IWL<36755> A_IWL<36754> A_IWL<36753> A_IWL<36752> A_IWL<36751> A_IWL<36750> A_IWL<36749> A_IWL<36748> A_IWL<36747> A_IWL<36746> A_IWL<36745> A_IWL<36744> A_IWL<36743> A_IWL<36742> A_IWL<36741> A_IWL<36740> A_IWL<36739> A_IWL<36738> A_IWL<36737> A_IWL<36736> A_IWL<36735> A_IWL<36734> A_IWL<36733> A_IWL<36732> A_IWL<36731> A_IWL<36730> A_IWL<36729> A_IWL<36728> A_IWL<36727> A_IWL<36726> A_IWL<36725> A_IWL<36724> A_IWL<36723> A_IWL<36722> A_IWL<36721> A_IWL<36720> A_IWL<36719> A_IWL<36718> A_IWL<36717> A_IWL<36716> A_IWL<36715> A_IWL<36714> A_IWL<36713> A_IWL<36712> A_IWL<36711> A_IWL<36710> A_IWL<36709> A_IWL<36708> A_IWL<36707> A_IWL<36706> A_IWL<36705> A_IWL<36704> A_IWL<36703> A_IWL<36702> A_IWL<36701> A_IWL<36700> A_IWL<36699> A_IWL<36698> A_IWL<36697> A_IWL<36696> A_IWL<36695> A_IWL<36694> A_IWL<36693> A_IWL<36692> A_IWL<36691> A_IWL<36690> A_IWL<36689> A_IWL<36688> A_IWL<36687> A_IWL<36686> A_IWL<36685> A_IWL<36684> A_IWL<36683> A_IWL<36682> A_IWL<36681> A_IWL<36680> A_IWL<36679> A_IWL<36678> A_IWL<36677> A_IWL<36676> A_IWL<36675> A_IWL<36674> A_IWL<36673> A_IWL<36672> A_IWL<36671> A_IWL<36670> A_IWL<36669> A_IWL<36668> A_IWL<36667> A_IWL<36666> A_IWL<36665> A_IWL<36664> A_IWL<36663> A_IWL<36662> A_IWL<36661> A_IWL<36660> A_IWL<36659> A_IWL<36658> A_IWL<36657> A_IWL<36656> A_IWL<36655> A_IWL<36654> A_IWL<36653> A_IWL<36652> A_IWL<36651> A_IWL<36650> A_IWL<36649> A_IWL<36648> A_IWL<36647> A_IWL<36646> A_IWL<36645> A_IWL<36644> A_IWL<36643> A_IWL<36642> A_IWL<36641> A_IWL<36640> A_IWL<36639> A_IWL<36638> A_IWL<36637> A_IWL<36636> A_IWL<36635> A_IWL<36634> A_IWL<36633> A_IWL<36632> A_IWL<36631> A_IWL<36630> A_IWL<36629> A_IWL<36628> A_IWL<36627> A_IWL<36626> A_IWL<36625> A_IWL<36624> A_IWL<36623> A_IWL<36622> A_IWL<36621> A_IWL<36620> A_IWL<36619> A_IWL<36618> A_IWL<36617> A_IWL<36616> A_IWL<36615> A_IWL<36614> A_IWL<36613> A_IWL<36612> A_IWL<36611> A_IWL<36610> A_IWL<36609> A_IWL<36608> A_IWL<36607> A_IWL<36606> A_IWL<36605> A_IWL<36604> A_IWL<36603> A_IWL<36602> A_IWL<36601> A_IWL<36600> A_IWL<36599> A_IWL<36598> A_IWL<36597> A_IWL<36596> A_IWL<36595> A_IWL<36594> A_IWL<36593> A_IWL<36592> A_IWL<36591> A_IWL<36590> A_IWL<36589> A_IWL<36588> A_IWL<36587> A_IWL<36586> A_IWL<36585> A_IWL<36584> A_IWL<36583> A_IWL<36582> A_IWL<36581> A_IWL<36580> A_IWL<36579> A_IWL<36578> A_IWL<36577> A_IWL<36576> A_IWL<36575> A_IWL<36574> A_IWL<36573> A_IWL<36572> A_IWL<36571> A_IWL<36570> A_IWL<36569> A_IWL<36568> A_IWL<36567> A_IWL<36566> A_IWL<36565> A_IWL<36564> A_IWL<36563> A_IWL<36562> A_IWL<36561> A_IWL<36560> A_IWL<36559> A_IWL<36558> A_IWL<36557> A_IWL<36556> A_IWL<36555> A_IWL<36554> A_IWL<36553> A_IWL<36552> A_IWL<36551> A_IWL<36550> A_IWL<36549> A_IWL<36548> A_IWL<36547> A_IWL<36546> A_IWL<36545> A_IWL<36544> A_IWL<36543> A_IWL<36542> A_IWL<36541> A_IWL<36540> A_IWL<36539> A_IWL<36538> A_IWL<36537> A_IWL<36536> A_IWL<36535> A_IWL<36534> A_IWL<36533> A_IWL<36532> A_IWL<36531> A_IWL<36530> A_IWL<36529> A_IWL<36528> A_IWL<36527> A_IWL<36526> A_IWL<36525> A_IWL<36524> A_IWL<36523> A_IWL<36522> A_IWL<36521> A_IWL<36520> A_IWL<36519> A_IWL<36518> A_IWL<36517> A_IWL<36516> A_IWL<36515> A_IWL<36514> A_IWL<36513> A_IWL<36512> A_IWL<36511> A_IWL<36510> A_IWL<36509> A_IWL<36508> A_IWL<36507> A_IWL<36506> A_IWL<36505> A_IWL<36504> A_IWL<36503> A_IWL<36502> A_IWL<36501> A_IWL<36500> A_IWL<36499> A_IWL<36498> A_IWL<36497> A_IWL<36496> A_IWL<36495> A_IWL<36494> A_IWL<36493> A_IWL<36492> A_IWL<36491> A_IWL<36490> A_IWL<36489> A_IWL<36488> A_IWL<36487> A_IWL<36486> A_IWL<36485> A_IWL<36484> A_IWL<36483> A_IWL<36482> A_IWL<36481> A_IWL<36480> A_IWL<36479> A_IWL<36478> A_IWL<36477> A_IWL<36476> A_IWL<36475> A_IWL<36474> A_IWL<36473> A_IWL<36472> A_IWL<36471> A_IWL<36470> A_IWL<36469> A_IWL<36468> A_IWL<36467> A_IWL<36466> A_IWL<36465> A_IWL<36464> A_IWL<36463> A_IWL<36462> A_IWL<36461> A_IWL<36460> A_IWL<36459> A_IWL<36458> A_IWL<36457> A_IWL<36456> A_IWL<36455> A_IWL<36454> A_IWL<36453> A_IWL<36452> A_IWL<36451> A_IWL<36450> A_IWL<36449> A_IWL<36448> A_IWL<36447> A_IWL<36446> A_IWL<36445> A_IWL<36444> A_IWL<36443> A_IWL<36442> A_IWL<36441> A_IWL<36440> A_IWL<36439> A_IWL<36438> A_IWL<36437> A_IWL<36436> A_IWL<36435> A_IWL<36434> A_IWL<36433> A_IWL<36432> A_IWL<36431> A_IWL<36430> A_IWL<36429> A_IWL<36428> A_IWL<36427> A_IWL<36426> A_IWL<36425> A_IWL<36424> A_IWL<36423> A_IWL<36422> A_IWL<36421> A_IWL<36420> A_IWL<36419> A_IWL<36418> A_IWL<36417> A_IWL<36416> A_IWL<36415> A_IWL<36414> A_IWL<36413> A_IWL<36412> A_IWL<36411> A_IWL<36410> A_IWL<36409> A_IWL<36408> A_IWL<36407> A_IWL<36406> A_IWL<36405> A_IWL<36404> A_IWL<36403> A_IWL<36402> A_IWL<36401> A_IWL<36400> A_IWL<36399> A_IWL<36398> A_IWL<36397> A_IWL<36396> A_IWL<36395> A_IWL<36394> A_IWL<36393> A_IWL<36392> A_IWL<36391> A_IWL<36390> A_IWL<36389> A_IWL<36388> A_IWL<36387> A_IWL<36386> A_IWL<36385> A_IWL<36384> A_IWL<36383> A_IWL<36382> A_IWL<36381> A_IWL<36380> A_IWL<36379> A_IWL<36378> A_IWL<36377> A_IWL<36376> A_IWL<36375> A_IWL<36374> A_IWL<36373> A_IWL<36372> A_IWL<36371> A_IWL<36370> A_IWL<36369> A_IWL<36368> A_IWL<36367> A_IWL<36366> A_IWL<36365> A_IWL<36364> A_IWL<36363> A_IWL<36362> A_IWL<36361> A_IWL<36360> A_IWL<36359> A_IWL<36358> A_IWL<36357> A_IWL<36356> A_IWL<36355> A_IWL<36354> A_IWL<36353> A_IWL<36352> VDD_CORE VSS / RM_IHPSG13_8192x32_c4_1P_COLUMN_pcell_0 +XCOL<70> A_BLC<141> A_BLC<140> A_BLC_TOP<141> A_BLC_TOP<140> A_BLT<141> A_BLT<140> A_BLT_TOP<141> A_BLT_TOP<140> A_IWL<35839> A_IWL<35838> A_IWL<35837> A_IWL<35836> A_IWL<35835> A_IWL<35834> A_IWL<35833> A_IWL<35832> A_IWL<35831> A_IWL<35830> A_IWL<35829> A_IWL<35828> A_IWL<35827> A_IWL<35826> A_IWL<35825> A_IWL<35824> A_IWL<35823> A_IWL<35822> A_IWL<35821> A_IWL<35820> A_IWL<35819> A_IWL<35818> A_IWL<35817> A_IWL<35816> A_IWL<35815> A_IWL<35814> A_IWL<35813> A_IWL<35812> A_IWL<35811> A_IWL<35810> A_IWL<35809> A_IWL<35808> A_IWL<35807> A_IWL<35806> A_IWL<35805> A_IWL<35804> A_IWL<35803> A_IWL<35802> A_IWL<35801> A_IWL<35800> A_IWL<35799> A_IWL<35798> A_IWL<35797> A_IWL<35796> A_IWL<35795> A_IWL<35794> A_IWL<35793> A_IWL<35792> A_IWL<35791> A_IWL<35790> A_IWL<35789> A_IWL<35788> A_IWL<35787> A_IWL<35786> A_IWL<35785> A_IWL<35784> A_IWL<35783> A_IWL<35782> A_IWL<35781> A_IWL<35780> A_IWL<35779> A_IWL<35778> A_IWL<35777> A_IWL<35776> A_IWL<35775> A_IWL<35774> A_IWL<35773> A_IWL<35772> A_IWL<35771> A_IWL<35770> A_IWL<35769> A_IWL<35768> A_IWL<35767> A_IWL<35766> A_IWL<35765> A_IWL<35764> A_IWL<35763> A_IWL<35762> A_IWL<35761> A_IWL<35760> A_IWL<35759> A_IWL<35758> A_IWL<35757> A_IWL<35756> A_IWL<35755> A_IWL<35754> A_IWL<35753> A_IWL<35752> A_IWL<35751> A_IWL<35750> A_IWL<35749> A_IWL<35748> A_IWL<35747> A_IWL<35746> A_IWL<35745> A_IWL<35744> A_IWL<35743> A_IWL<35742> A_IWL<35741> A_IWL<35740> A_IWL<35739> A_IWL<35738> A_IWL<35737> A_IWL<35736> A_IWL<35735> A_IWL<35734> A_IWL<35733> A_IWL<35732> A_IWL<35731> A_IWL<35730> A_IWL<35729> A_IWL<35728> A_IWL<35727> A_IWL<35726> A_IWL<35725> A_IWL<35724> A_IWL<35723> A_IWL<35722> A_IWL<35721> A_IWL<35720> A_IWL<35719> A_IWL<35718> A_IWL<35717> A_IWL<35716> A_IWL<35715> A_IWL<35714> A_IWL<35713> A_IWL<35712> A_IWL<35711> A_IWL<35710> A_IWL<35709> A_IWL<35708> A_IWL<35707> A_IWL<35706> A_IWL<35705> A_IWL<35704> A_IWL<35703> A_IWL<35702> A_IWL<35701> A_IWL<35700> A_IWL<35699> A_IWL<35698> A_IWL<35697> A_IWL<35696> A_IWL<35695> A_IWL<35694> A_IWL<35693> A_IWL<35692> A_IWL<35691> A_IWL<35690> A_IWL<35689> A_IWL<35688> A_IWL<35687> A_IWL<35686> A_IWL<35685> A_IWL<35684> A_IWL<35683> A_IWL<35682> A_IWL<35681> A_IWL<35680> A_IWL<35679> A_IWL<35678> A_IWL<35677> A_IWL<35676> A_IWL<35675> A_IWL<35674> A_IWL<35673> A_IWL<35672> A_IWL<35671> A_IWL<35670> A_IWL<35669> A_IWL<35668> A_IWL<35667> A_IWL<35666> A_IWL<35665> A_IWL<35664> A_IWL<35663> A_IWL<35662> A_IWL<35661> A_IWL<35660> A_IWL<35659> A_IWL<35658> A_IWL<35657> A_IWL<35656> A_IWL<35655> A_IWL<35654> A_IWL<35653> A_IWL<35652> A_IWL<35651> A_IWL<35650> A_IWL<35649> A_IWL<35648> A_IWL<35647> A_IWL<35646> A_IWL<35645> A_IWL<35644> A_IWL<35643> A_IWL<35642> A_IWL<35641> A_IWL<35640> A_IWL<35639> A_IWL<35638> A_IWL<35637> A_IWL<35636> A_IWL<35635> A_IWL<35634> A_IWL<35633> A_IWL<35632> A_IWL<35631> A_IWL<35630> A_IWL<35629> A_IWL<35628> A_IWL<35627> A_IWL<35626> A_IWL<35625> A_IWL<35624> A_IWL<35623> A_IWL<35622> A_IWL<35621> A_IWL<35620> A_IWL<35619> A_IWL<35618> A_IWL<35617> A_IWL<35616> A_IWL<35615> A_IWL<35614> A_IWL<35613> A_IWL<35612> A_IWL<35611> A_IWL<35610> A_IWL<35609> A_IWL<35608> A_IWL<35607> A_IWL<35606> A_IWL<35605> A_IWL<35604> A_IWL<35603> A_IWL<35602> A_IWL<35601> A_IWL<35600> A_IWL<35599> A_IWL<35598> A_IWL<35597> A_IWL<35596> A_IWL<35595> A_IWL<35594> A_IWL<35593> A_IWL<35592> A_IWL<35591> A_IWL<35590> A_IWL<35589> A_IWL<35588> A_IWL<35587> A_IWL<35586> A_IWL<35585> A_IWL<35584> A_IWL<35583> A_IWL<35582> A_IWL<35581> A_IWL<35580> A_IWL<35579> A_IWL<35578> A_IWL<35577> A_IWL<35576> A_IWL<35575> A_IWL<35574> A_IWL<35573> A_IWL<35572> A_IWL<35571> A_IWL<35570> A_IWL<35569> A_IWL<35568> A_IWL<35567> A_IWL<35566> A_IWL<35565> A_IWL<35564> A_IWL<35563> A_IWL<35562> A_IWL<35561> A_IWL<35560> A_IWL<35559> A_IWL<35558> A_IWL<35557> A_IWL<35556> A_IWL<35555> A_IWL<35554> A_IWL<35553> A_IWL<35552> A_IWL<35551> A_IWL<35550> A_IWL<35549> A_IWL<35548> A_IWL<35547> A_IWL<35546> A_IWL<35545> A_IWL<35544> A_IWL<35543> A_IWL<35542> A_IWL<35541> A_IWL<35540> A_IWL<35539> A_IWL<35538> A_IWL<35537> A_IWL<35536> A_IWL<35535> A_IWL<35534> A_IWL<35533> A_IWL<35532> A_IWL<35531> A_IWL<35530> A_IWL<35529> A_IWL<35528> A_IWL<35527> A_IWL<35526> A_IWL<35525> A_IWL<35524> A_IWL<35523> A_IWL<35522> A_IWL<35521> A_IWL<35520> A_IWL<35519> A_IWL<35518> A_IWL<35517> A_IWL<35516> A_IWL<35515> A_IWL<35514> A_IWL<35513> A_IWL<35512> A_IWL<35511> A_IWL<35510> A_IWL<35509> A_IWL<35508> A_IWL<35507> A_IWL<35506> A_IWL<35505> A_IWL<35504> A_IWL<35503> A_IWL<35502> A_IWL<35501> A_IWL<35500> A_IWL<35499> A_IWL<35498> A_IWL<35497> A_IWL<35496> A_IWL<35495> A_IWL<35494> A_IWL<35493> A_IWL<35492> A_IWL<35491> A_IWL<35490> A_IWL<35489> A_IWL<35488> A_IWL<35487> A_IWL<35486> A_IWL<35485> A_IWL<35484> A_IWL<35483> A_IWL<35482> A_IWL<35481> A_IWL<35480> A_IWL<35479> A_IWL<35478> A_IWL<35477> A_IWL<35476> A_IWL<35475> A_IWL<35474> A_IWL<35473> A_IWL<35472> A_IWL<35471> A_IWL<35470> A_IWL<35469> A_IWL<35468> A_IWL<35467> A_IWL<35466> A_IWL<35465> A_IWL<35464> A_IWL<35463> A_IWL<35462> A_IWL<35461> A_IWL<35460> A_IWL<35459> A_IWL<35458> A_IWL<35457> A_IWL<35456> A_IWL<35455> A_IWL<35454> A_IWL<35453> A_IWL<35452> A_IWL<35451> A_IWL<35450> A_IWL<35449> A_IWL<35448> A_IWL<35447> A_IWL<35446> A_IWL<35445> A_IWL<35444> A_IWL<35443> A_IWL<35442> A_IWL<35441> A_IWL<35440> A_IWL<35439> A_IWL<35438> A_IWL<35437> A_IWL<35436> A_IWL<35435> A_IWL<35434> A_IWL<35433> A_IWL<35432> A_IWL<35431> A_IWL<35430> A_IWL<35429> A_IWL<35428> A_IWL<35427> A_IWL<35426> A_IWL<35425> A_IWL<35424> A_IWL<35423> A_IWL<35422> A_IWL<35421> A_IWL<35420> A_IWL<35419> A_IWL<35418> A_IWL<35417> A_IWL<35416> A_IWL<35415> A_IWL<35414> A_IWL<35413> A_IWL<35412> A_IWL<35411> A_IWL<35410> A_IWL<35409> A_IWL<35408> A_IWL<35407> A_IWL<35406> A_IWL<35405> A_IWL<35404> A_IWL<35403> A_IWL<35402> A_IWL<35401> A_IWL<35400> A_IWL<35399> A_IWL<35398> A_IWL<35397> A_IWL<35396> A_IWL<35395> A_IWL<35394> A_IWL<35393> A_IWL<35392> A_IWL<35391> A_IWL<35390> A_IWL<35389> A_IWL<35388> A_IWL<35387> A_IWL<35386> A_IWL<35385> A_IWL<35384> A_IWL<35383> A_IWL<35382> A_IWL<35381> A_IWL<35380> A_IWL<35379> A_IWL<35378> A_IWL<35377> A_IWL<35376> A_IWL<35375> A_IWL<35374> A_IWL<35373> A_IWL<35372> A_IWL<35371> A_IWL<35370> A_IWL<35369> A_IWL<35368> A_IWL<35367> A_IWL<35366> A_IWL<35365> A_IWL<35364> A_IWL<35363> A_IWL<35362> A_IWL<35361> A_IWL<35360> A_IWL<35359> A_IWL<35358> A_IWL<35357> A_IWL<35356> A_IWL<35355> A_IWL<35354> A_IWL<35353> A_IWL<35352> A_IWL<35351> A_IWL<35350> A_IWL<35349> A_IWL<35348> A_IWL<35347> A_IWL<35346> A_IWL<35345> A_IWL<35344> A_IWL<35343> A_IWL<35342> A_IWL<35341> A_IWL<35340> A_IWL<35339> A_IWL<35338> A_IWL<35337> A_IWL<35336> A_IWL<35335> A_IWL<35334> A_IWL<35333> A_IWL<35332> A_IWL<35331> A_IWL<35330> A_IWL<35329> A_IWL<35328> A_IWL<36351> A_IWL<36350> A_IWL<36349> A_IWL<36348> A_IWL<36347> A_IWL<36346> A_IWL<36345> A_IWL<36344> A_IWL<36343> A_IWL<36342> A_IWL<36341> A_IWL<36340> A_IWL<36339> A_IWL<36338> A_IWL<36337> A_IWL<36336> A_IWL<36335> A_IWL<36334> A_IWL<36333> A_IWL<36332> A_IWL<36331> A_IWL<36330> A_IWL<36329> A_IWL<36328> A_IWL<36327> A_IWL<36326> A_IWL<36325> A_IWL<36324> A_IWL<36323> A_IWL<36322> A_IWL<36321> A_IWL<36320> A_IWL<36319> A_IWL<36318> A_IWL<36317> A_IWL<36316> A_IWL<36315> A_IWL<36314> A_IWL<36313> A_IWL<36312> A_IWL<36311> A_IWL<36310> A_IWL<36309> A_IWL<36308> A_IWL<36307> A_IWL<36306> A_IWL<36305> A_IWL<36304> A_IWL<36303> A_IWL<36302> A_IWL<36301> A_IWL<36300> A_IWL<36299> A_IWL<36298> A_IWL<36297> A_IWL<36296> A_IWL<36295> A_IWL<36294> A_IWL<36293> A_IWL<36292> A_IWL<36291> A_IWL<36290> A_IWL<36289> A_IWL<36288> A_IWL<36287> A_IWL<36286> A_IWL<36285> A_IWL<36284> A_IWL<36283> A_IWL<36282> A_IWL<36281> A_IWL<36280> A_IWL<36279> A_IWL<36278> A_IWL<36277> A_IWL<36276> A_IWL<36275> A_IWL<36274> A_IWL<36273> A_IWL<36272> A_IWL<36271> A_IWL<36270> A_IWL<36269> A_IWL<36268> A_IWL<36267> A_IWL<36266> A_IWL<36265> A_IWL<36264> A_IWL<36263> A_IWL<36262> A_IWL<36261> A_IWL<36260> A_IWL<36259> A_IWL<36258> A_IWL<36257> A_IWL<36256> A_IWL<36255> A_IWL<36254> A_IWL<36253> A_IWL<36252> A_IWL<36251> A_IWL<36250> A_IWL<36249> A_IWL<36248> A_IWL<36247> A_IWL<36246> A_IWL<36245> A_IWL<36244> A_IWL<36243> A_IWL<36242> A_IWL<36241> A_IWL<36240> A_IWL<36239> A_IWL<36238> A_IWL<36237> A_IWL<36236> A_IWL<36235> A_IWL<36234> A_IWL<36233> A_IWL<36232> A_IWL<36231> A_IWL<36230> A_IWL<36229> A_IWL<36228> A_IWL<36227> A_IWL<36226> A_IWL<36225> A_IWL<36224> A_IWL<36223> A_IWL<36222> A_IWL<36221> A_IWL<36220> A_IWL<36219> A_IWL<36218> A_IWL<36217> A_IWL<36216> A_IWL<36215> A_IWL<36214> A_IWL<36213> A_IWL<36212> A_IWL<36211> A_IWL<36210> A_IWL<36209> A_IWL<36208> A_IWL<36207> A_IWL<36206> A_IWL<36205> A_IWL<36204> A_IWL<36203> A_IWL<36202> A_IWL<36201> A_IWL<36200> A_IWL<36199> A_IWL<36198> A_IWL<36197> A_IWL<36196> A_IWL<36195> A_IWL<36194> A_IWL<36193> A_IWL<36192> A_IWL<36191> A_IWL<36190> A_IWL<36189> A_IWL<36188> A_IWL<36187> A_IWL<36186> A_IWL<36185> A_IWL<36184> A_IWL<36183> A_IWL<36182> A_IWL<36181> A_IWL<36180> A_IWL<36179> A_IWL<36178> A_IWL<36177> A_IWL<36176> A_IWL<36175> A_IWL<36174> A_IWL<36173> A_IWL<36172> A_IWL<36171> A_IWL<36170> A_IWL<36169> A_IWL<36168> A_IWL<36167> A_IWL<36166> A_IWL<36165> A_IWL<36164> A_IWL<36163> A_IWL<36162> A_IWL<36161> A_IWL<36160> A_IWL<36159> A_IWL<36158> A_IWL<36157> A_IWL<36156> A_IWL<36155> A_IWL<36154> A_IWL<36153> A_IWL<36152> A_IWL<36151> A_IWL<36150> A_IWL<36149> A_IWL<36148> A_IWL<36147> A_IWL<36146> A_IWL<36145> A_IWL<36144> A_IWL<36143> A_IWL<36142> A_IWL<36141> A_IWL<36140> A_IWL<36139> A_IWL<36138> A_IWL<36137> A_IWL<36136> A_IWL<36135> A_IWL<36134> A_IWL<36133> A_IWL<36132> A_IWL<36131> A_IWL<36130> A_IWL<36129> A_IWL<36128> A_IWL<36127> A_IWL<36126> A_IWL<36125> A_IWL<36124> A_IWL<36123> A_IWL<36122> A_IWL<36121> A_IWL<36120> A_IWL<36119> A_IWL<36118> A_IWL<36117> A_IWL<36116> A_IWL<36115> A_IWL<36114> A_IWL<36113> A_IWL<36112> A_IWL<36111> A_IWL<36110> A_IWL<36109> A_IWL<36108> A_IWL<36107> A_IWL<36106> A_IWL<36105> A_IWL<36104> A_IWL<36103> A_IWL<36102> A_IWL<36101> A_IWL<36100> A_IWL<36099> A_IWL<36098> A_IWL<36097> A_IWL<36096> A_IWL<36095> A_IWL<36094> A_IWL<36093> A_IWL<36092> A_IWL<36091> A_IWL<36090> A_IWL<36089> A_IWL<36088> A_IWL<36087> A_IWL<36086> A_IWL<36085> A_IWL<36084> A_IWL<36083> A_IWL<36082> A_IWL<36081> A_IWL<36080> A_IWL<36079> A_IWL<36078> A_IWL<36077> A_IWL<36076> A_IWL<36075> A_IWL<36074> A_IWL<36073> A_IWL<36072> A_IWL<36071> A_IWL<36070> A_IWL<36069> A_IWL<36068> A_IWL<36067> A_IWL<36066> A_IWL<36065> A_IWL<36064> A_IWL<36063> A_IWL<36062> A_IWL<36061> A_IWL<36060> A_IWL<36059> A_IWL<36058> A_IWL<36057> A_IWL<36056> A_IWL<36055> A_IWL<36054> A_IWL<36053> A_IWL<36052> A_IWL<36051> A_IWL<36050> A_IWL<36049> A_IWL<36048> A_IWL<36047> A_IWL<36046> A_IWL<36045> A_IWL<36044> A_IWL<36043> A_IWL<36042> A_IWL<36041> A_IWL<36040> A_IWL<36039> A_IWL<36038> A_IWL<36037> A_IWL<36036> A_IWL<36035> A_IWL<36034> A_IWL<36033> A_IWL<36032> A_IWL<36031> A_IWL<36030> A_IWL<36029> A_IWL<36028> A_IWL<36027> A_IWL<36026> A_IWL<36025> A_IWL<36024> A_IWL<36023> A_IWL<36022> A_IWL<36021> A_IWL<36020> A_IWL<36019> A_IWL<36018> A_IWL<36017> A_IWL<36016> A_IWL<36015> A_IWL<36014> A_IWL<36013> A_IWL<36012> A_IWL<36011> A_IWL<36010> A_IWL<36009> A_IWL<36008> A_IWL<36007> A_IWL<36006> A_IWL<36005> A_IWL<36004> A_IWL<36003> A_IWL<36002> A_IWL<36001> A_IWL<36000> A_IWL<35999> A_IWL<35998> A_IWL<35997> A_IWL<35996> A_IWL<35995> A_IWL<35994> A_IWL<35993> A_IWL<35992> A_IWL<35991> A_IWL<35990> A_IWL<35989> A_IWL<35988> A_IWL<35987> A_IWL<35986> A_IWL<35985> A_IWL<35984> A_IWL<35983> A_IWL<35982> A_IWL<35981> A_IWL<35980> A_IWL<35979> A_IWL<35978> A_IWL<35977> A_IWL<35976> A_IWL<35975> A_IWL<35974> A_IWL<35973> A_IWL<35972> A_IWL<35971> A_IWL<35970> A_IWL<35969> A_IWL<35968> A_IWL<35967> A_IWL<35966> A_IWL<35965> A_IWL<35964> A_IWL<35963> A_IWL<35962> A_IWL<35961> A_IWL<35960> A_IWL<35959> A_IWL<35958> A_IWL<35957> A_IWL<35956> A_IWL<35955> A_IWL<35954> A_IWL<35953> A_IWL<35952> A_IWL<35951> A_IWL<35950> A_IWL<35949> A_IWL<35948> A_IWL<35947> A_IWL<35946> A_IWL<35945> A_IWL<35944> A_IWL<35943> A_IWL<35942> A_IWL<35941> A_IWL<35940> A_IWL<35939> A_IWL<35938> A_IWL<35937> A_IWL<35936> A_IWL<35935> A_IWL<35934> A_IWL<35933> A_IWL<35932> A_IWL<35931> A_IWL<35930> A_IWL<35929> A_IWL<35928> A_IWL<35927> A_IWL<35926> A_IWL<35925> A_IWL<35924> A_IWL<35923> A_IWL<35922> A_IWL<35921> A_IWL<35920> A_IWL<35919> A_IWL<35918> A_IWL<35917> A_IWL<35916> A_IWL<35915> A_IWL<35914> A_IWL<35913> A_IWL<35912> A_IWL<35911> A_IWL<35910> A_IWL<35909> A_IWL<35908> A_IWL<35907> A_IWL<35906> A_IWL<35905> A_IWL<35904> A_IWL<35903> A_IWL<35902> A_IWL<35901> A_IWL<35900> A_IWL<35899> A_IWL<35898> A_IWL<35897> A_IWL<35896> A_IWL<35895> A_IWL<35894> A_IWL<35893> A_IWL<35892> A_IWL<35891> A_IWL<35890> A_IWL<35889> A_IWL<35888> A_IWL<35887> A_IWL<35886> A_IWL<35885> A_IWL<35884> A_IWL<35883> A_IWL<35882> A_IWL<35881> A_IWL<35880> A_IWL<35879> A_IWL<35878> A_IWL<35877> A_IWL<35876> A_IWL<35875> A_IWL<35874> A_IWL<35873> A_IWL<35872> A_IWL<35871> A_IWL<35870> A_IWL<35869> A_IWL<35868> A_IWL<35867> A_IWL<35866> A_IWL<35865> A_IWL<35864> A_IWL<35863> A_IWL<35862> A_IWL<35861> A_IWL<35860> A_IWL<35859> A_IWL<35858> A_IWL<35857> A_IWL<35856> A_IWL<35855> A_IWL<35854> A_IWL<35853> A_IWL<35852> A_IWL<35851> A_IWL<35850> A_IWL<35849> A_IWL<35848> A_IWL<35847> A_IWL<35846> A_IWL<35845> A_IWL<35844> A_IWL<35843> A_IWL<35842> A_IWL<35841> A_IWL<35840> VDD_CORE VSS / RM_IHPSG13_8192x32_c4_1P_COLUMN_pcell_0 +XCOL<69> A_BLC<139> A_BLC<138> A_BLC_TOP<139> A_BLC_TOP<138> A_BLT<139> A_BLT<138> A_BLT_TOP<139> A_BLT_TOP<138> A_IWL<35327> A_IWL<35326> A_IWL<35325> A_IWL<35324> A_IWL<35323> A_IWL<35322> A_IWL<35321> A_IWL<35320> A_IWL<35319> A_IWL<35318> A_IWL<35317> A_IWL<35316> A_IWL<35315> A_IWL<35314> A_IWL<35313> A_IWL<35312> A_IWL<35311> A_IWL<35310> A_IWL<35309> A_IWL<35308> A_IWL<35307> A_IWL<35306> A_IWL<35305> A_IWL<35304> A_IWL<35303> A_IWL<35302> A_IWL<35301> A_IWL<35300> A_IWL<35299> A_IWL<35298> A_IWL<35297> A_IWL<35296> A_IWL<35295> A_IWL<35294> A_IWL<35293> A_IWL<35292> A_IWL<35291> A_IWL<35290> A_IWL<35289> A_IWL<35288> A_IWL<35287> A_IWL<35286> A_IWL<35285> A_IWL<35284> A_IWL<35283> A_IWL<35282> A_IWL<35281> A_IWL<35280> A_IWL<35279> A_IWL<35278> A_IWL<35277> A_IWL<35276> A_IWL<35275> A_IWL<35274> A_IWL<35273> A_IWL<35272> A_IWL<35271> A_IWL<35270> A_IWL<35269> A_IWL<35268> A_IWL<35267> A_IWL<35266> A_IWL<35265> A_IWL<35264> A_IWL<35263> A_IWL<35262> A_IWL<35261> A_IWL<35260> A_IWL<35259> A_IWL<35258> A_IWL<35257> A_IWL<35256> A_IWL<35255> A_IWL<35254> A_IWL<35253> A_IWL<35252> A_IWL<35251> A_IWL<35250> A_IWL<35249> A_IWL<35248> A_IWL<35247> A_IWL<35246> A_IWL<35245> A_IWL<35244> A_IWL<35243> A_IWL<35242> A_IWL<35241> A_IWL<35240> A_IWL<35239> A_IWL<35238> A_IWL<35237> A_IWL<35236> A_IWL<35235> A_IWL<35234> A_IWL<35233> A_IWL<35232> A_IWL<35231> A_IWL<35230> A_IWL<35229> A_IWL<35228> A_IWL<35227> A_IWL<35226> A_IWL<35225> A_IWL<35224> A_IWL<35223> A_IWL<35222> A_IWL<35221> A_IWL<35220> A_IWL<35219> A_IWL<35218> A_IWL<35217> A_IWL<35216> A_IWL<35215> A_IWL<35214> A_IWL<35213> A_IWL<35212> A_IWL<35211> A_IWL<35210> A_IWL<35209> A_IWL<35208> A_IWL<35207> A_IWL<35206> A_IWL<35205> A_IWL<35204> A_IWL<35203> A_IWL<35202> A_IWL<35201> A_IWL<35200> A_IWL<35199> A_IWL<35198> A_IWL<35197> A_IWL<35196> A_IWL<35195> A_IWL<35194> A_IWL<35193> A_IWL<35192> A_IWL<35191> A_IWL<35190> A_IWL<35189> A_IWL<35188> A_IWL<35187> A_IWL<35186> A_IWL<35185> A_IWL<35184> A_IWL<35183> A_IWL<35182> A_IWL<35181> A_IWL<35180> A_IWL<35179> A_IWL<35178> A_IWL<35177> A_IWL<35176> A_IWL<35175> A_IWL<35174> A_IWL<35173> A_IWL<35172> A_IWL<35171> A_IWL<35170> A_IWL<35169> A_IWL<35168> A_IWL<35167> A_IWL<35166> A_IWL<35165> A_IWL<35164> A_IWL<35163> A_IWL<35162> A_IWL<35161> A_IWL<35160> A_IWL<35159> A_IWL<35158> A_IWL<35157> A_IWL<35156> A_IWL<35155> A_IWL<35154> A_IWL<35153> A_IWL<35152> A_IWL<35151> A_IWL<35150> A_IWL<35149> A_IWL<35148> A_IWL<35147> A_IWL<35146> A_IWL<35145> A_IWL<35144> A_IWL<35143> A_IWL<35142> A_IWL<35141> A_IWL<35140> A_IWL<35139> A_IWL<35138> A_IWL<35137> A_IWL<35136> A_IWL<35135> A_IWL<35134> A_IWL<35133> A_IWL<35132> A_IWL<35131> A_IWL<35130> A_IWL<35129> A_IWL<35128> A_IWL<35127> A_IWL<35126> A_IWL<35125> A_IWL<35124> A_IWL<35123> A_IWL<35122> A_IWL<35121> A_IWL<35120> A_IWL<35119> A_IWL<35118> A_IWL<35117> A_IWL<35116> A_IWL<35115> A_IWL<35114> A_IWL<35113> A_IWL<35112> A_IWL<35111> A_IWL<35110> A_IWL<35109> A_IWL<35108> A_IWL<35107> A_IWL<35106> A_IWL<35105> A_IWL<35104> A_IWL<35103> A_IWL<35102> A_IWL<35101> A_IWL<35100> A_IWL<35099> A_IWL<35098> A_IWL<35097> A_IWL<35096> A_IWL<35095> A_IWL<35094> A_IWL<35093> A_IWL<35092> A_IWL<35091> A_IWL<35090> A_IWL<35089> A_IWL<35088> A_IWL<35087> A_IWL<35086> A_IWL<35085> A_IWL<35084> A_IWL<35083> A_IWL<35082> A_IWL<35081> A_IWL<35080> A_IWL<35079> A_IWL<35078> A_IWL<35077> A_IWL<35076> A_IWL<35075> A_IWL<35074> A_IWL<35073> A_IWL<35072> A_IWL<35071> A_IWL<35070> A_IWL<35069> A_IWL<35068> A_IWL<35067> A_IWL<35066> A_IWL<35065> A_IWL<35064> A_IWL<35063> A_IWL<35062> A_IWL<35061> A_IWL<35060> A_IWL<35059> A_IWL<35058> A_IWL<35057> A_IWL<35056> A_IWL<35055> A_IWL<35054> A_IWL<35053> A_IWL<35052> A_IWL<35051> A_IWL<35050> A_IWL<35049> A_IWL<35048> A_IWL<35047> A_IWL<35046> A_IWL<35045> A_IWL<35044> A_IWL<35043> A_IWL<35042> A_IWL<35041> A_IWL<35040> A_IWL<35039> A_IWL<35038> A_IWL<35037> A_IWL<35036> A_IWL<35035> A_IWL<35034> A_IWL<35033> A_IWL<35032> A_IWL<35031> A_IWL<35030> A_IWL<35029> A_IWL<35028> A_IWL<35027> A_IWL<35026> A_IWL<35025> A_IWL<35024> A_IWL<35023> A_IWL<35022> A_IWL<35021> A_IWL<35020> A_IWL<35019> A_IWL<35018> A_IWL<35017> A_IWL<35016> A_IWL<35015> A_IWL<35014> A_IWL<35013> A_IWL<35012> A_IWL<35011> A_IWL<35010> A_IWL<35009> A_IWL<35008> A_IWL<35007> A_IWL<35006> A_IWL<35005> A_IWL<35004> A_IWL<35003> A_IWL<35002> A_IWL<35001> A_IWL<35000> A_IWL<34999> A_IWL<34998> A_IWL<34997> A_IWL<34996> A_IWL<34995> A_IWL<34994> A_IWL<34993> A_IWL<34992> A_IWL<34991> A_IWL<34990> A_IWL<34989> A_IWL<34988> A_IWL<34987> A_IWL<34986> A_IWL<34985> A_IWL<34984> A_IWL<34983> A_IWL<34982> A_IWL<34981> A_IWL<34980> A_IWL<34979> A_IWL<34978> A_IWL<34977> A_IWL<34976> A_IWL<34975> A_IWL<34974> A_IWL<34973> A_IWL<34972> A_IWL<34971> A_IWL<34970> A_IWL<34969> A_IWL<34968> A_IWL<34967> A_IWL<34966> A_IWL<34965> A_IWL<34964> A_IWL<34963> A_IWL<34962> A_IWL<34961> A_IWL<34960> A_IWL<34959> A_IWL<34958> A_IWL<34957> A_IWL<34956> A_IWL<34955> A_IWL<34954> A_IWL<34953> A_IWL<34952> A_IWL<34951> A_IWL<34950> A_IWL<34949> A_IWL<34948> A_IWL<34947> A_IWL<34946> A_IWL<34945> A_IWL<34944> A_IWL<34943> A_IWL<34942> A_IWL<34941> A_IWL<34940> A_IWL<34939> A_IWL<34938> A_IWL<34937> A_IWL<34936> A_IWL<34935> A_IWL<34934> A_IWL<34933> A_IWL<34932> A_IWL<34931> A_IWL<34930> A_IWL<34929> A_IWL<34928> A_IWL<34927> A_IWL<34926> A_IWL<34925> A_IWL<34924> A_IWL<34923> A_IWL<34922> A_IWL<34921> A_IWL<34920> A_IWL<34919> A_IWL<34918> A_IWL<34917> A_IWL<34916> A_IWL<34915> A_IWL<34914> A_IWL<34913> A_IWL<34912> A_IWL<34911> A_IWL<34910> A_IWL<34909> A_IWL<34908> A_IWL<34907> A_IWL<34906> A_IWL<34905> A_IWL<34904> A_IWL<34903> A_IWL<34902> A_IWL<34901> A_IWL<34900> A_IWL<34899> A_IWL<34898> A_IWL<34897> A_IWL<34896> A_IWL<34895> A_IWL<34894> A_IWL<34893> A_IWL<34892> A_IWL<34891> A_IWL<34890> A_IWL<34889> A_IWL<34888> A_IWL<34887> A_IWL<34886> A_IWL<34885> A_IWL<34884> A_IWL<34883> A_IWL<34882> A_IWL<34881> A_IWL<34880> A_IWL<34879> A_IWL<34878> A_IWL<34877> A_IWL<34876> A_IWL<34875> A_IWL<34874> A_IWL<34873> A_IWL<34872> A_IWL<34871> A_IWL<34870> A_IWL<34869> A_IWL<34868> A_IWL<34867> A_IWL<34866> A_IWL<34865> A_IWL<34864> A_IWL<34863> A_IWL<34862> A_IWL<34861> A_IWL<34860> A_IWL<34859> A_IWL<34858> A_IWL<34857> A_IWL<34856> A_IWL<34855> A_IWL<34854> A_IWL<34853> A_IWL<34852> A_IWL<34851> A_IWL<34850> A_IWL<34849> A_IWL<34848> A_IWL<34847> A_IWL<34846> A_IWL<34845> A_IWL<34844> A_IWL<34843> A_IWL<34842> A_IWL<34841> A_IWL<34840> A_IWL<34839> A_IWL<34838> A_IWL<34837> A_IWL<34836> A_IWL<34835> A_IWL<34834> A_IWL<34833> A_IWL<34832> A_IWL<34831> A_IWL<34830> A_IWL<34829> A_IWL<34828> A_IWL<34827> A_IWL<34826> A_IWL<34825> A_IWL<34824> A_IWL<34823> A_IWL<34822> A_IWL<34821> A_IWL<34820> A_IWL<34819> A_IWL<34818> A_IWL<34817> A_IWL<34816> A_IWL<35839> A_IWL<35838> A_IWL<35837> A_IWL<35836> A_IWL<35835> A_IWL<35834> A_IWL<35833> A_IWL<35832> A_IWL<35831> A_IWL<35830> A_IWL<35829> A_IWL<35828> A_IWL<35827> A_IWL<35826> A_IWL<35825> A_IWL<35824> A_IWL<35823> A_IWL<35822> A_IWL<35821> A_IWL<35820> A_IWL<35819> A_IWL<35818> A_IWL<35817> A_IWL<35816> A_IWL<35815> A_IWL<35814> A_IWL<35813> A_IWL<35812> A_IWL<35811> A_IWL<35810> A_IWL<35809> A_IWL<35808> A_IWL<35807> A_IWL<35806> A_IWL<35805> A_IWL<35804> A_IWL<35803> A_IWL<35802> A_IWL<35801> A_IWL<35800> A_IWL<35799> A_IWL<35798> A_IWL<35797> A_IWL<35796> A_IWL<35795> A_IWL<35794> A_IWL<35793> A_IWL<35792> A_IWL<35791> A_IWL<35790> A_IWL<35789> A_IWL<35788> A_IWL<35787> A_IWL<35786> A_IWL<35785> A_IWL<35784> A_IWL<35783> A_IWL<35782> A_IWL<35781> A_IWL<35780> A_IWL<35779> A_IWL<35778> A_IWL<35777> A_IWL<35776> A_IWL<35775> A_IWL<35774> A_IWL<35773> A_IWL<35772> A_IWL<35771> A_IWL<35770> A_IWL<35769> A_IWL<35768> A_IWL<35767> A_IWL<35766> A_IWL<35765> A_IWL<35764> A_IWL<35763> A_IWL<35762> A_IWL<35761> A_IWL<35760> A_IWL<35759> A_IWL<35758> A_IWL<35757> A_IWL<35756> A_IWL<35755> A_IWL<35754> A_IWL<35753> A_IWL<35752> A_IWL<35751> A_IWL<35750> A_IWL<35749> A_IWL<35748> A_IWL<35747> A_IWL<35746> A_IWL<35745> A_IWL<35744> A_IWL<35743> A_IWL<35742> A_IWL<35741> A_IWL<35740> A_IWL<35739> A_IWL<35738> A_IWL<35737> A_IWL<35736> A_IWL<35735> A_IWL<35734> A_IWL<35733> A_IWL<35732> A_IWL<35731> A_IWL<35730> A_IWL<35729> A_IWL<35728> A_IWL<35727> A_IWL<35726> A_IWL<35725> A_IWL<35724> A_IWL<35723> A_IWL<35722> A_IWL<35721> A_IWL<35720> A_IWL<35719> A_IWL<35718> A_IWL<35717> A_IWL<35716> A_IWL<35715> A_IWL<35714> A_IWL<35713> A_IWL<35712> A_IWL<35711> A_IWL<35710> A_IWL<35709> A_IWL<35708> A_IWL<35707> A_IWL<35706> A_IWL<35705> A_IWL<35704> A_IWL<35703> A_IWL<35702> A_IWL<35701> A_IWL<35700> A_IWL<35699> A_IWL<35698> A_IWL<35697> A_IWL<35696> A_IWL<35695> A_IWL<35694> A_IWL<35693> A_IWL<35692> A_IWL<35691> A_IWL<35690> A_IWL<35689> A_IWL<35688> A_IWL<35687> A_IWL<35686> A_IWL<35685> A_IWL<35684> A_IWL<35683> A_IWL<35682> A_IWL<35681> A_IWL<35680> A_IWL<35679> A_IWL<35678> A_IWL<35677> A_IWL<35676> A_IWL<35675> A_IWL<35674> A_IWL<35673> A_IWL<35672> A_IWL<35671> A_IWL<35670> A_IWL<35669> A_IWL<35668> A_IWL<35667> A_IWL<35666> A_IWL<35665> A_IWL<35664> A_IWL<35663> A_IWL<35662> A_IWL<35661> A_IWL<35660> A_IWL<35659> A_IWL<35658> A_IWL<35657> A_IWL<35656> A_IWL<35655> A_IWL<35654> A_IWL<35653> A_IWL<35652> A_IWL<35651> A_IWL<35650> A_IWL<35649> A_IWL<35648> A_IWL<35647> A_IWL<35646> A_IWL<35645> A_IWL<35644> A_IWL<35643> A_IWL<35642> A_IWL<35641> A_IWL<35640> A_IWL<35639> A_IWL<35638> A_IWL<35637> A_IWL<35636> A_IWL<35635> A_IWL<35634> A_IWL<35633> A_IWL<35632> A_IWL<35631> A_IWL<35630> A_IWL<35629> A_IWL<35628> A_IWL<35627> A_IWL<35626> A_IWL<35625> A_IWL<35624> A_IWL<35623> A_IWL<35622> A_IWL<35621> A_IWL<35620> A_IWL<35619> A_IWL<35618> A_IWL<35617> A_IWL<35616> A_IWL<35615> A_IWL<35614> A_IWL<35613> A_IWL<35612> A_IWL<35611> A_IWL<35610> A_IWL<35609> A_IWL<35608> A_IWL<35607> A_IWL<35606> A_IWL<35605> A_IWL<35604> A_IWL<35603> A_IWL<35602> A_IWL<35601> A_IWL<35600> A_IWL<35599> A_IWL<35598> A_IWL<35597> A_IWL<35596> A_IWL<35595> A_IWL<35594> A_IWL<35593> A_IWL<35592> A_IWL<35591> A_IWL<35590> A_IWL<35589> A_IWL<35588> A_IWL<35587> A_IWL<35586> A_IWL<35585> A_IWL<35584> A_IWL<35583> A_IWL<35582> A_IWL<35581> A_IWL<35580> A_IWL<35579> A_IWL<35578> A_IWL<35577> A_IWL<35576> A_IWL<35575> A_IWL<35574> A_IWL<35573> A_IWL<35572> A_IWL<35571> A_IWL<35570> A_IWL<35569> A_IWL<35568> A_IWL<35567> A_IWL<35566> A_IWL<35565> A_IWL<35564> A_IWL<35563> A_IWL<35562> A_IWL<35561> A_IWL<35560> A_IWL<35559> A_IWL<35558> A_IWL<35557> A_IWL<35556> A_IWL<35555> A_IWL<35554> A_IWL<35553> A_IWL<35552> A_IWL<35551> A_IWL<35550> A_IWL<35549> A_IWL<35548> A_IWL<35547> A_IWL<35546> A_IWL<35545> A_IWL<35544> A_IWL<35543> A_IWL<35542> A_IWL<35541> A_IWL<35540> A_IWL<35539> A_IWL<35538> A_IWL<35537> A_IWL<35536> A_IWL<35535> A_IWL<35534> A_IWL<35533> A_IWL<35532> A_IWL<35531> A_IWL<35530> A_IWL<35529> A_IWL<35528> A_IWL<35527> A_IWL<35526> A_IWL<35525> A_IWL<35524> A_IWL<35523> A_IWL<35522> A_IWL<35521> A_IWL<35520> A_IWL<35519> A_IWL<35518> A_IWL<35517> A_IWL<35516> A_IWL<35515> A_IWL<35514> A_IWL<35513> A_IWL<35512> A_IWL<35511> A_IWL<35510> A_IWL<35509> A_IWL<35508> A_IWL<35507> A_IWL<35506> A_IWL<35505> A_IWL<35504> A_IWL<35503> A_IWL<35502> A_IWL<35501> A_IWL<35500> A_IWL<35499> A_IWL<35498> A_IWL<35497> A_IWL<35496> A_IWL<35495> A_IWL<35494> A_IWL<35493> A_IWL<35492> A_IWL<35491> A_IWL<35490> A_IWL<35489> A_IWL<35488> A_IWL<35487> A_IWL<35486> A_IWL<35485> A_IWL<35484> A_IWL<35483> A_IWL<35482> A_IWL<35481> A_IWL<35480> A_IWL<35479> A_IWL<35478> A_IWL<35477> A_IWL<35476> A_IWL<35475> A_IWL<35474> A_IWL<35473> A_IWL<35472> A_IWL<35471> A_IWL<35470> A_IWL<35469> A_IWL<35468> A_IWL<35467> A_IWL<35466> A_IWL<35465> A_IWL<35464> A_IWL<35463> A_IWL<35462> A_IWL<35461> A_IWL<35460> A_IWL<35459> A_IWL<35458> A_IWL<35457> A_IWL<35456> A_IWL<35455> A_IWL<35454> A_IWL<35453> A_IWL<35452> A_IWL<35451> A_IWL<35450> A_IWL<35449> A_IWL<35448> A_IWL<35447> A_IWL<35446> A_IWL<35445> A_IWL<35444> A_IWL<35443> A_IWL<35442> A_IWL<35441> A_IWL<35440> A_IWL<35439> A_IWL<35438> A_IWL<35437> A_IWL<35436> A_IWL<35435> A_IWL<35434> A_IWL<35433> A_IWL<35432> A_IWL<35431> A_IWL<35430> A_IWL<35429> A_IWL<35428> A_IWL<35427> A_IWL<35426> A_IWL<35425> A_IWL<35424> A_IWL<35423> A_IWL<35422> A_IWL<35421> A_IWL<35420> A_IWL<35419> A_IWL<35418> A_IWL<35417> A_IWL<35416> A_IWL<35415> A_IWL<35414> A_IWL<35413> A_IWL<35412> A_IWL<35411> A_IWL<35410> A_IWL<35409> A_IWL<35408> A_IWL<35407> A_IWL<35406> A_IWL<35405> A_IWL<35404> A_IWL<35403> A_IWL<35402> A_IWL<35401> A_IWL<35400> A_IWL<35399> A_IWL<35398> A_IWL<35397> A_IWL<35396> A_IWL<35395> A_IWL<35394> A_IWL<35393> A_IWL<35392> A_IWL<35391> A_IWL<35390> A_IWL<35389> A_IWL<35388> A_IWL<35387> A_IWL<35386> A_IWL<35385> A_IWL<35384> A_IWL<35383> A_IWL<35382> A_IWL<35381> A_IWL<35380> A_IWL<35379> A_IWL<35378> A_IWL<35377> A_IWL<35376> A_IWL<35375> A_IWL<35374> A_IWL<35373> A_IWL<35372> A_IWL<35371> A_IWL<35370> A_IWL<35369> A_IWL<35368> A_IWL<35367> A_IWL<35366> A_IWL<35365> A_IWL<35364> A_IWL<35363> A_IWL<35362> A_IWL<35361> A_IWL<35360> A_IWL<35359> A_IWL<35358> A_IWL<35357> A_IWL<35356> A_IWL<35355> A_IWL<35354> A_IWL<35353> A_IWL<35352> A_IWL<35351> A_IWL<35350> A_IWL<35349> A_IWL<35348> A_IWL<35347> A_IWL<35346> A_IWL<35345> A_IWL<35344> A_IWL<35343> A_IWL<35342> A_IWL<35341> A_IWL<35340> A_IWL<35339> A_IWL<35338> A_IWL<35337> A_IWL<35336> A_IWL<35335> A_IWL<35334> A_IWL<35333> A_IWL<35332> A_IWL<35331> A_IWL<35330> A_IWL<35329> A_IWL<35328> VDD_CORE VSS / RM_IHPSG13_8192x32_c4_1P_COLUMN_pcell_0 +XCOL<68> A_BLC<137> A_BLC<136> A_BLC_TOP<137> A_BLC_TOP<136> A_BLT<137> A_BLT<136> A_BLT_TOP<137> A_BLT_TOP<136> A_IWL<34815> A_IWL<34814> A_IWL<34813> A_IWL<34812> A_IWL<34811> A_IWL<34810> A_IWL<34809> A_IWL<34808> A_IWL<34807> A_IWL<34806> A_IWL<34805> A_IWL<34804> A_IWL<34803> A_IWL<34802> A_IWL<34801> A_IWL<34800> A_IWL<34799> A_IWL<34798> A_IWL<34797> A_IWL<34796> A_IWL<34795> A_IWL<34794> A_IWL<34793> A_IWL<34792> A_IWL<34791> A_IWL<34790> A_IWL<34789> A_IWL<34788> A_IWL<34787> A_IWL<34786> A_IWL<34785> A_IWL<34784> A_IWL<34783> A_IWL<34782> A_IWL<34781> A_IWL<34780> A_IWL<34779> A_IWL<34778> A_IWL<34777> A_IWL<34776> A_IWL<34775> A_IWL<34774> A_IWL<34773> A_IWL<34772> A_IWL<34771> A_IWL<34770> A_IWL<34769> A_IWL<34768> A_IWL<34767> A_IWL<34766> A_IWL<34765> A_IWL<34764> A_IWL<34763> A_IWL<34762> A_IWL<34761> A_IWL<34760> A_IWL<34759> A_IWL<34758> A_IWL<34757> A_IWL<34756> A_IWL<34755> A_IWL<34754> A_IWL<34753> A_IWL<34752> A_IWL<34751> A_IWL<34750> A_IWL<34749> A_IWL<34748> A_IWL<34747> A_IWL<34746> A_IWL<34745> A_IWL<34744> A_IWL<34743> A_IWL<34742> A_IWL<34741> A_IWL<34740> A_IWL<34739> A_IWL<34738> A_IWL<34737> A_IWL<34736> A_IWL<34735> A_IWL<34734> A_IWL<34733> A_IWL<34732> A_IWL<34731> A_IWL<34730> A_IWL<34729> A_IWL<34728> A_IWL<34727> A_IWL<34726> A_IWL<34725> A_IWL<34724> A_IWL<34723> A_IWL<34722> A_IWL<34721> A_IWL<34720> A_IWL<34719> A_IWL<34718> A_IWL<34717> A_IWL<34716> A_IWL<34715> A_IWL<34714> A_IWL<34713> A_IWL<34712> A_IWL<34711> A_IWL<34710> A_IWL<34709> A_IWL<34708> A_IWL<34707> A_IWL<34706> A_IWL<34705> A_IWL<34704> A_IWL<34703> A_IWL<34702> A_IWL<34701> A_IWL<34700> A_IWL<34699> A_IWL<34698> A_IWL<34697> A_IWL<34696> A_IWL<34695> A_IWL<34694> A_IWL<34693> A_IWL<34692> A_IWL<34691> A_IWL<34690> A_IWL<34689> A_IWL<34688> A_IWL<34687> A_IWL<34686> A_IWL<34685> A_IWL<34684> A_IWL<34683> A_IWL<34682> A_IWL<34681> A_IWL<34680> A_IWL<34679> A_IWL<34678> A_IWL<34677> A_IWL<34676> A_IWL<34675> A_IWL<34674> A_IWL<34673> A_IWL<34672> A_IWL<34671> A_IWL<34670> A_IWL<34669> A_IWL<34668> A_IWL<34667> A_IWL<34666> A_IWL<34665> A_IWL<34664> A_IWL<34663> A_IWL<34662> A_IWL<34661> A_IWL<34660> A_IWL<34659> A_IWL<34658> A_IWL<34657> A_IWL<34656> A_IWL<34655> A_IWL<34654> A_IWL<34653> A_IWL<34652> A_IWL<34651> A_IWL<34650> A_IWL<34649> A_IWL<34648> A_IWL<34647> A_IWL<34646> A_IWL<34645> A_IWL<34644> A_IWL<34643> A_IWL<34642> A_IWL<34641> A_IWL<34640> A_IWL<34639> A_IWL<34638> A_IWL<34637> A_IWL<34636> A_IWL<34635> A_IWL<34634> A_IWL<34633> A_IWL<34632> A_IWL<34631> A_IWL<34630> A_IWL<34629> A_IWL<34628> A_IWL<34627> A_IWL<34626> A_IWL<34625> A_IWL<34624> A_IWL<34623> A_IWL<34622> A_IWL<34621> A_IWL<34620> A_IWL<34619> A_IWL<34618> A_IWL<34617> A_IWL<34616> A_IWL<34615> A_IWL<34614> A_IWL<34613> A_IWL<34612> A_IWL<34611> A_IWL<34610> A_IWL<34609> A_IWL<34608> A_IWL<34607> A_IWL<34606> A_IWL<34605> A_IWL<34604> A_IWL<34603> A_IWL<34602> A_IWL<34601> A_IWL<34600> A_IWL<34599> A_IWL<34598> A_IWL<34597> A_IWL<34596> A_IWL<34595> A_IWL<34594> A_IWL<34593> A_IWL<34592> A_IWL<34591> A_IWL<34590> A_IWL<34589> A_IWL<34588> A_IWL<34587> A_IWL<34586> A_IWL<34585> A_IWL<34584> A_IWL<34583> A_IWL<34582> A_IWL<34581> A_IWL<34580> A_IWL<34579> A_IWL<34578> A_IWL<34577> A_IWL<34576> A_IWL<34575> A_IWL<34574> A_IWL<34573> A_IWL<34572> A_IWL<34571> A_IWL<34570> A_IWL<34569> A_IWL<34568> A_IWL<34567> A_IWL<34566> A_IWL<34565> A_IWL<34564> A_IWL<34563> A_IWL<34562> A_IWL<34561> A_IWL<34560> A_IWL<34559> A_IWL<34558> A_IWL<34557> A_IWL<34556> A_IWL<34555> A_IWL<34554> A_IWL<34553> A_IWL<34552> A_IWL<34551> A_IWL<34550> A_IWL<34549> A_IWL<34548> A_IWL<34547> A_IWL<34546> A_IWL<34545> A_IWL<34544> A_IWL<34543> A_IWL<34542> A_IWL<34541> A_IWL<34540> A_IWL<34539> A_IWL<34538> A_IWL<34537> A_IWL<34536> A_IWL<34535> A_IWL<34534> A_IWL<34533> A_IWL<34532> A_IWL<34531> A_IWL<34530> A_IWL<34529> A_IWL<34528> A_IWL<34527> A_IWL<34526> A_IWL<34525> A_IWL<34524> A_IWL<34523> A_IWL<34522> A_IWL<34521> A_IWL<34520> A_IWL<34519> A_IWL<34518> A_IWL<34517> A_IWL<34516> A_IWL<34515> A_IWL<34514> A_IWL<34513> A_IWL<34512> A_IWL<34511> A_IWL<34510> A_IWL<34509> A_IWL<34508> A_IWL<34507> A_IWL<34506> A_IWL<34505> A_IWL<34504> A_IWL<34503> A_IWL<34502> A_IWL<34501> A_IWL<34500> A_IWL<34499> A_IWL<34498> A_IWL<34497> A_IWL<34496> A_IWL<34495> A_IWL<34494> A_IWL<34493> A_IWL<34492> A_IWL<34491> A_IWL<34490> A_IWL<34489> A_IWL<34488> A_IWL<34487> A_IWL<34486> A_IWL<34485> A_IWL<34484> A_IWL<34483> A_IWL<34482> A_IWL<34481> A_IWL<34480> A_IWL<34479> A_IWL<34478> A_IWL<34477> A_IWL<34476> A_IWL<34475> A_IWL<34474> A_IWL<34473> A_IWL<34472> A_IWL<34471> A_IWL<34470> A_IWL<34469> A_IWL<34468> A_IWL<34467> A_IWL<34466> A_IWL<34465> A_IWL<34464> A_IWL<34463> A_IWL<34462> A_IWL<34461> A_IWL<34460> A_IWL<34459> A_IWL<34458> A_IWL<34457> A_IWL<34456> A_IWL<34455> A_IWL<34454> A_IWL<34453> A_IWL<34452> A_IWL<34451> A_IWL<34450> A_IWL<34449> A_IWL<34448> A_IWL<34447> A_IWL<34446> A_IWL<34445> A_IWL<34444> A_IWL<34443> A_IWL<34442> A_IWL<34441> A_IWL<34440> A_IWL<34439> A_IWL<34438> A_IWL<34437> A_IWL<34436> A_IWL<34435> A_IWL<34434> A_IWL<34433> A_IWL<34432> A_IWL<34431> A_IWL<34430> A_IWL<34429> A_IWL<34428> A_IWL<34427> A_IWL<34426> A_IWL<34425> A_IWL<34424> A_IWL<34423> A_IWL<34422> A_IWL<34421> A_IWL<34420> A_IWL<34419> A_IWL<34418> A_IWL<34417> A_IWL<34416> A_IWL<34415> A_IWL<34414> A_IWL<34413> A_IWL<34412> A_IWL<34411> A_IWL<34410> A_IWL<34409> A_IWL<34408> A_IWL<34407> A_IWL<34406> A_IWL<34405> A_IWL<34404> A_IWL<34403> A_IWL<34402> A_IWL<34401> A_IWL<34400> A_IWL<34399> A_IWL<34398> A_IWL<34397> A_IWL<34396> A_IWL<34395> A_IWL<34394> A_IWL<34393> A_IWL<34392> A_IWL<34391> A_IWL<34390> A_IWL<34389> A_IWL<34388> A_IWL<34387> A_IWL<34386> A_IWL<34385> A_IWL<34384> A_IWL<34383> A_IWL<34382> A_IWL<34381> A_IWL<34380> A_IWL<34379> A_IWL<34378> A_IWL<34377> A_IWL<34376> A_IWL<34375> A_IWL<34374> A_IWL<34373> A_IWL<34372> A_IWL<34371> A_IWL<34370> A_IWL<34369> A_IWL<34368> A_IWL<34367> A_IWL<34366> A_IWL<34365> A_IWL<34364> A_IWL<34363> A_IWL<34362> A_IWL<34361> A_IWL<34360> A_IWL<34359> A_IWL<34358> A_IWL<34357> A_IWL<34356> A_IWL<34355> A_IWL<34354> A_IWL<34353> A_IWL<34352> A_IWL<34351> A_IWL<34350> A_IWL<34349> A_IWL<34348> A_IWL<34347> A_IWL<34346> A_IWL<34345> A_IWL<34344> A_IWL<34343> A_IWL<34342> A_IWL<34341> A_IWL<34340> A_IWL<34339> A_IWL<34338> A_IWL<34337> A_IWL<34336> A_IWL<34335> A_IWL<34334> A_IWL<34333> A_IWL<34332> A_IWL<34331> A_IWL<34330> A_IWL<34329> A_IWL<34328> A_IWL<34327> A_IWL<34326> A_IWL<34325> A_IWL<34324> A_IWL<34323> A_IWL<34322> A_IWL<34321> A_IWL<34320> A_IWL<34319> A_IWL<34318> A_IWL<34317> A_IWL<34316> A_IWL<34315> A_IWL<34314> A_IWL<34313> A_IWL<34312> A_IWL<34311> A_IWL<34310> A_IWL<34309> A_IWL<34308> A_IWL<34307> A_IWL<34306> A_IWL<34305> A_IWL<34304> A_IWL<35327> A_IWL<35326> A_IWL<35325> A_IWL<35324> A_IWL<35323> A_IWL<35322> A_IWL<35321> A_IWL<35320> A_IWL<35319> A_IWL<35318> A_IWL<35317> A_IWL<35316> A_IWL<35315> A_IWL<35314> A_IWL<35313> A_IWL<35312> A_IWL<35311> A_IWL<35310> A_IWL<35309> A_IWL<35308> A_IWL<35307> A_IWL<35306> A_IWL<35305> A_IWL<35304> A_IWL<35303> A_IWL<35302> A_IWL<35301> A_IWL<35300> A_IWL<35299> A_IWL<35298> A_IWL<35297> A_IWL<35296> A_IWL<35295> A_IWL<35294> A_IWL<35293> A_IWL<35292> A_IWL<35291> A_IWL<35290> A_IWL<35289> A_IWL<35288> A_IWL<35287> A_IWL<35286> A_IWL<35285> A_IWL<35284> A_IWL<35283> A_IWL<35282> A_IWL<35281> A_IWL<35280> A_IWL<35279> A_IWL<35278> A_IWL<35277> A_IWL<35276> A_IWL<35275> A_IWL<35274> A_IWL<35273> A_IWL<35272> A_IWL<35271> A_IWL<35270> A_IWL<35269> A_IWL<35268> A_IWL<35267> A_IWL<35266> A_IWL<35265> A_IWL<35264> A_IWL<35263> A_IWL<35262> A_IWL<35261> A_IWL<35260> A_IWL<35259> A_IWL<35258> A_IWL<35257> A_IWL<35256> A_IWL<35255> A_IWL<35254> A_IWL<35253> A_IWL<35252> A_IWL<35251> A_IWL<35250> A_IWL<35249> A_IWL<35248> A_IWL<35247> A_IWL<35246> A_IWL<35245> A_IWL<35244> A_IWL<35243> A_IWL<35242> A_IWL<35241> A_IWL<35240> A_IWL<35239> A_IWL<35238> A_IWL<35237> A_IWL<35236> A_IWL<35235> A_IWL<35234> A_IWL<35233> A_IWL<35232> A_IWL<35231> A_IWL<35230> A_IWL<35229> A_IWL<35228> A_IWL<35227> A_IWL<35226> A_IWL<35225> A_IWL<35224> A_IWL<35223> A_IWL<35222> A_IWL<35221> A_IWL<35220> A_IWL<35219> A_IWL<35218> A_IWL<35217> A_IWL<35216> A_IWL<35215> A_IWL<35214> A_IWL<35213> A_IWL<35212> A_IWL<35211> A_IWL<35210> A_IWL<35209> A_IWL<35208> A_IWL<35207> A_IWL<35206> A_IWL<35205> A_IWL<35204> A_IWL<35203> A_IWL<35202> A_IWL<35201> A_IWL<35200> A_IWL<35199> A_IWL<35198> A_IWL<35197> A_IWL<35196> A_IWL<35195> A_IWL<35194> A_IWL<35193> A_IWL<35192> A_IWL<35191> A_IWL<35190> A_IWL<35189> A_IWL<35188> A_IWL<35187> A_IWL<35186> A_IWL<35185> A_IWL<35184> A_IWL<35183> A_IWL<35182> A_IWL<35181> A_IWL<35180> A_IWL<35179> A_IWL<35178> A_IWL<35177> A_IWL<35176> A_IWL<35175> A_IWL<35174> A_IWL<35173> A_IWL<35172> A_IWL<35171> A_IWL<35170> A_IWL<35169> A_IWL<35168> A_IWL<35167> A_IWL<35166> A_IWL<35165> A_IWL<35164> A_IWL<35163> A_IWL<35162> A_IWL<35161> A_IWL<35160> A_IWL<35159> A_IWL<35158> A_IWL<35157> A_IWL<35156> A_IWL<35155> A_IWL<35154> A_IWL<35153> A_IWL<35152> A_IWL<35151> A_IWL<35150> A_IWL<35149> A_IWL<35148> A_IWL<35147> A_IWL<35146> A_IWL<35145> A_IWL<35144> A_IWL<35143> A_IWL<35142> A_IWL<35141> A_IWL<35140> A_IWL<35139> A_IWL<35138> A_IWL<35137> A_IWL<35136> A_IWL<35135> A_IWL<35134> A_IWL<35133> A_IWL<35132> A_IWL<35131> A_IWL<35130> A_IWL<35129> A_IWL<35128> A_IWL<35127> A_IWL<35126> A_IWL<35125> A_IWL<35124> A_IWL<35123> A_IWL<35122> A_IWL<35121> A_IWL<35120> A_IWL<35119> A_IWL<35118> A_IWL<35117> A_IWL<35116> A_IWL<35115> A_IWL<35114> A_IWL<35113> A_IWL<35112> A_IWL<35111> A_IWL<35110> A_IWL<35109> A_IWL<35108> A_IWL<35107> A_IWL<35106> A_IWL<35105> A_IWL<35104> A_IWL<35103> A_IWL<35102> A_IWL<35101> A_IWL<35100> A_IWL<35099> A_IWL<35098> A_IWL<35097> A_IWL<35096> A_IWL<35095> A_IWL<35094> A_IWL<35093> A_IWL<35092> A_IWL<35091> A_IWL<35090> A_IWL<35089> A_IWL<35088> A_IWL<35087> A_IWL<35086> A_IWL<35085> A_IWL<35084> A_IWL<35083> A_IWL<35082> A_IWL<35081> A_IWL<35080> A_IWL<35079> A_IWL<35078> A_IWL<35077> A_IWL<35076> A_IWL<35075> A_IWL<35074> A_IWL<35073> A_IWL<35072> A_IWL<35071> A_IWL<35070> A_IWL<35069> A_IWL<35068> A_IWL<35067> A_IWL<35066> A_IWL<35065> A_IWL<35064> A_IWL<35063> A_IWL<35062> A_IWL<35061> A_IWL<35060> A_IWL<35059> A_IWL<35058> A_IWL<35057> A_IWL<35056> A_IWL<35055> A_IWL<35054> A_IWL<35053> A_IWL<35052> A_IWL<35051> A_IWL<35050> A_IWL<35049> A_IWL<35048> A_IWL<35047> A_IWL<35046> A_IWL<35045> A_IWL<35044> A_IWL<35043> A_IWL<35042> A_IWL<35041> A_IWL<35040> A_IWL<35039> A_IWL<35038> A_IWL<35037> A_IWL<35036> A_IWL<35035> A_IWL<35034> A_IWL<35033> A_IWL<35032> A_IWL<35031> A_IWL<35030> A_IWL<35029> A_IWL<35028> A_IWL<35027> A_IWL<35026> A_IWL<35025> A_IWL<35024> A_IWL<35023> A_IWL<35022> A_IWL<35021> A_IWL<35020> A_IWL<35019> A_IWL<35018> A_IWL<35017> A_IWL<35016> A_IWL<35015> A_IWL<35014> A_IWL<35013> A_IWL<35012> A_IWL<35011> A_IWL<35010> A_IWL<35009> A_IWL<35008> A_IWL<35007> A_IWL<35006> A_IWL<35005> A_IWL<35004> A_IWL<35003> A_IWL<35002> A_IWL<35001> A_IWL<35000> A_IWL<34999> A_IWL<34998> A_IWL<34997> A_IWL<34996> A_IWL<34995> A_IWL<34994> A_IWL<34993> A_IWL<34992> A_IWL<34991> A_IWL<34990> A_IWL<34989> A_IWL<34988> A_IWL<34987> A_IWL<34986> A_IWL<34985> A_IWL<34984> A_IWL<34983> A_IWL<34982> A_IWL<34981> A_IWL<34980> A_IWL<34979> A_IWL<34978> A_IWL<34977> A_IWL<34976> A_IWL<34975> A_IWL<34974> A_IWL<34973> A_IWL<34972> A_IWL<34971> A_IWL<34970> A_IWL<34969> A_IWL<34968> A_IWL<34967> A_IWL<34966> A_IWL<34965> A_IWL<34964> A_IWL<34963> A_IWL<34962> A_IWL<34961> A_IWL<34960> A_IWL<34959> A_IWL<34958> A_IWL<34957> A_IWL<34956> A_IWL<34955> A_IWL<34954> A_IWL<34953> A_IWL<34952> A_IWL<34951> A_IWL<34950> A_IWL<34949> A_IWL<34948> A_IWL<34947> A_IWL<34946> A_IWL<34945> A_IWL<34944> A_IWL<34943> A_IWL<34942> A_IWL<34941> A_IWL<34940> A_IWL<34939> A_IWL<34938> A_IWL<34937> A_IWL<34936> A_IWL<34935> A_IWL<34934> A_IWL<34933> A_IWL<34932> A_IWL<34931> A_IWL<34930> A_IWL<34929> A_IWL<34928> A_IWL<34927> A_IWL<34926> A_IWL<34925> A_IWL<34924> A_IWL<34923> A_IWL<34922> A_IWL<34921> A_IWL<34920> A_IWL<34919> A_IWL<34918> A_IWL<34917> A_IWL<34916> A_IWL<34915> A_IWL<34914> A_IWL<34913> A_IWL<34912> A_IWL<34911> A_IWL<34910> A_IWL<34909> A_IWL<34908> A_IWL<34907> A_IWL<34906> A_IWL<34905> A_IWL<34904> A_IWL<34903> A_IWL<34902> A_IWL<34901> A_IWL<34900> A_IWL<34899> A_IWL<34898> A_IWL<34897> A_IWL<34896> A_IWL<34895> A_IWL<34894> A_IWL<34893> A_IWL<34892> A_IWL<34891> A_IWL<34890> A_IWL<34889> A_IWL<34888> A_IWL<34887> A_IWL<34886> A_IWL<34885> A_IWL<34884> A_IWL<34883> A_IWL<34882> A_IWL<34881> A_IWL<34880> A_IWL<34879> A_IWL<34878> A_IWL<34877> A_IWL<34876> A_IWL<34875> A_IWL<34874> A_IWL<34873> A_IWL<34872> A_IWL<34871> A_IWL<34870> A_IWL<34869> A_IWL<34868> A_IWL<34867> A_IWL<34866> A_IWL<34865> A_IWL<34864> A_IWL<34863> A_IWL<34862> A_IWL<34861> A_IWL<34860> A_IWL<34859> A_IWL<34858> A_IWL<34857> A_IWL<34856> A_IWL<34855> A_IWL<34854> A_IWL<34853> A_IWL<34852> A_IWL<34851> A_IWL<34850> A_IWL<34849> A_IWL<34848> A_IWL<34847> A_IWL<34846> A_IWL<34845> A_IWL<34844> A_IWL<34843> A_IWL<34842> A_IWL<34841> A_IWL<34840> A_IWL<34839> A_IWL<34838> A_IWL<34837> A_IWL<34836> A_IWL<34835> A_IWL<34834> A_IWL<34833> A_IWL<34832> A_IWL<34831> A_IWL<34830> A_IWL<34829> A_IWL<34828> A_IWL<34827> A_IWL<34826> A_IWL<34825> A_IWL<34824> A_IWL<34823> A_IWL<34822> A_IWL<34821> A_IWL<34820> A_IWL<34819> A_IWL<34818> A_IWL<34817> A_IWL<34816> VDD_CORE VSS / RM_IHPSG13_8192x32_c4_1P_COLUMN_pcell_0 +XCOL<67> A_BLC<135> A_BLC<134> A_BLC_TOP<135> A_BLC_TOP<134> A_BLT<135> A_BLT<134> A_BLT_TOP<135> A_BLT_TOP<134> A_IWL<34303> A_IWL<34302> A_IWL<34301> A_IWL<34300> A_IWL<34299> A_IWL<34298> A_IWL<34297> A_IWL<34296> A_IWL<34295> A_IWL<34294> A_IWL<34293> A_IWL<34292> A_IWL<34291> A_IWL<34290> A_IWL<34289> A_IWL<34288> A_IWL<34287> A_IWL<34286> A_IWL<34285> A_IWL<34284> A_IWL<34283> A_IWL<34282> A_IWL<34281> A_IWL<34280> A_IWL<34279> A_IWL<34278> A_IWL<34277> A_IWL<34276> A_IWL<34275> A_IWL<34274> A_IWL<34273> A_IWL<34272> A_IWL<34271> A_IWL<34270> A_IWL<34269> A_IWL<34268> A_IWL<34267> A_IWL<34266> A_IWL<34265> A_IWL<34264> A_IWL<34263> A_IWL<34262> A_IWL<34261> A_IWL<34260> A_IWL<34259> A_IWL<34258> A_IWL<34257> A_IWL<34256> A_IWL<34255> A_IWL<34254> A_IWL<34253> A_IWL<34252> A_IWL<34251> A_IWL<34250> A_IWL<34249> A_IWL<34248> A_IWL<34247> A_IWL<34246> A_IWL<34245> A_IWL<34244> A_IWL<34243> A_IWL<34242> A_IWL<34241> A_IWL<34240> A_IWL<34239> A_IWL<34238> A_IWL<34237> A_IWL<34236> A_IWL<34235> A_IWL<34234> A_IWL<34233> A_IWL<34232> A_IWL<34231> A_IWL<34230> A_IWL<34229> A_IWL<34228> A_IWL<34227> A_IWL<34226> A_IWL<34225> A_IWL<34224> A_IWL<34223> A_IWL<34222> A_IWL<34221> A_IWL<34220> A_IWL<34219> A_IWL<34218> A_IWL<34217> A_IWL<34216> A_IWL<34215> A_IWL<34214> A_IWL<34213> A_IWL<34212> A_IWL<34211> A_IWL<34210> A_IWL<34209> A_IWL<34208> A_IWL<34207> A_IWL<34206> A_IWL<34205> A_IWL<34204> A_IWL<34203> A_IWL<34202> A_IWL<34201> A_IWL<34200> A_IWL<34199> A_IWL<34198> A_IWL<34197> A_IWL<34196> A_IWL<34195> A_IWL<34194> A_IWL<34193> A_IWL<34192> A_IWL<34191> A_IWL<34190> A_IWL<34189> A_IWL<34188> A_IWL<34187> A_IWL<34186> A_IWL<34185> A_IWL<34184> A_IWL<34183> A_IWL<34182> A_IWL<34181> A_IWL<34180> A_IWL<34179> A_IWL<34178> A_IWL<34177> A_IWL<34176> A_IWL<34175> A_IWL<34174> A_IWL<34173> A_IWL<34172> A_IWL<34171> A_IWL<34170> A_IWL<34169> A_IWL<34168> A_IWL<34167> A_IWL<34166> A_IWL<34165> A_IWL<34164> A_IWL<34163> A_IWL<34162> A_IWL<34161> A_IWL<34160> A_IWL<34159> A_IWL<34158> A_IWL<34157> A_IWL<34156> A_IWL<34155> A_IWL<34154> A_IWL<34153> A_IWL<34152> A_IWL<34151> A_IWL<34150> A_IWL<34149> A_IWL<34148> A_IWL<34147> A_IWL<34146> A_IWL<34145> A_IWL<34144> A_IWL<34143> A_IWL<34142> A_IWL<34141> A_IWL<34140> A_IWL<34139> A_IWL<34138> A_IWL<34137> A_IWL<34136> A_IWL<34135> A_IWL<34134> A_IWL<34133> A_IWL<34132> A_IWL<34131> A_IWL<34130> A_IWL<34129> A_IWL<34128> A_IWL<34127> A_IWL<34126> A_IWL<34125> A_IWL<34124> A_IWL<34123> A_IWL<34122> A_IWL<34121> A_IWL<34120> A_IWL<34119> A_IWL<34118> A_IWL<34117> A_IWL<34116> A_IWL<34115> A_IWL<34114> A_IWL<34113> A_IWL<34112> A_IWL<34111> A_IWL<34110> A_IWL<34109> A_IWL<34108> A_IWL<34107> A_IWL<34106> A_IWL<34105> A_IWL<34104> A_IWL<34103> A_IWL<34102> A_IWL<34101> A_IWL<34100> A_IWL<34099> A_IWL<34098> A_IWL<34097> A_IWL<34096> A_IWL<34095> A_IWL<34094> A_IWL<34093> A_IWL<34092> A_IWL<34091> A_IWL<34090> A_IWL<34089> A_IWL<34088> A_IWL<34087> A_IWL<34086> A_IWL<34085> A_IWL<34084> A_IWL<34083> A_IWL<34082> A_IWL<34081> A_IWL<34080> A_IWL<34079> A_IWL<34078> A_IWL<34077> A_IWL<34076> A_IWL<34075> A_IWL<34074> A_IWL<34073> A_IWL<34072> A_IWL<34071> A_IWL<34070> A_IWL<34069> A_IWL<34068> A_IWL<34067> A_IWL<34066> A_IWL<34065> A_IWL<34064> A_IWL<34063> A_IWL<34062> A_IWL<34061> A_IWL<34060> A_IWL<34059> A_IWL<34058> A_IWL<34057> A_IWL<34056> A_IWL<34055> A_IWL<34054> A_IWL<34053> A_IWL<34052> A_IWL<34051> A_IWL<34050> A_IWL<34049> A_IWL<34048> A_IWL<34047> A_IWL<34046> A_IWL<34045> A_IWL<34044> A_IWL<34043> A_IWL<34042> A_IWL<34041> A_IWL<34040> A_IWL<34039> A_IWL<34038> A_IWL<34037> A_IWL<34036> A_IWL<34035> A_IWL<34034> A_IWL<34033> A_IWL<34032> A_IWL<34031> A_IWL<34030> A_IWL<34029> A_IWL<34028> A_IWL<34027> A_IWL<34026> A_IWL<34025> A_IWL<34024> A_IWL<34023> A_IWL<34022> A_IWL<34021> A_IWL<34020> A_IWL<34019> A_IWL<34018> A_IWL<34017> A_IWL<34016> A_IWL<34015> A_IWL<34014> A_IWL<34013> A_IWL<34012> A_IWL<34011> A_IWL<34010> A_IWL<34009> A_IWL<34008> A_IWL<34007> A_IWL<34006> A_IWL<34005> A_IWL<34004> A_IWL<34003> A_IWL<34002> A_IWL<34001> A_IWL<34000> A_IWL<33999> A_IWL<33998> A_IWL<33997> A_IWL<33996> A_IWL<33995> A_IWL<33994> A_IWL<33993> A_IWL<33992> A_IWL<33991> A_IWL<33990> A_IWL<33989> A_IWL<33988> A_IWL<33987> A_IWL<33986> A_IWL<33985> A_IWL<33984> A_IWL<33983> A_IWL<33982> A_IWL<33981> A_IWL<33980> A_IWL<33979> A_IWL<33978> A_IWL<33977> A_IWL<33976> A_IWL<33975> A_IWL<33974> A_IWL<33973> A_IWL<33972> A_IWL<33971> A_IWL<33970> A_IWL<33969> A_IWL<33968> A_IWL<33967> A_IWL<33966> A_IWL<33965> A_IWL<33964> A_IWL<33963> A_IWL<33962> A_IWL<33961> A_IWL<33960> A_IWL<33959> A_IWL<33958> A_IWL<33957> A_IWL<33956> A_IWL<33955> A_IWL<33954> A_IWL<33953> A_IWL<33952> A_IWL<33951> A_IWL<33950> A_IWL<33949> A_IWL<33948> A_IWL<33947> A_IWL<33946> A_IWL<33945> A_IWL<33944> A_IWL<33943> A_IWL<33942> A_IWL<33941> A_IWL<33940> A_IWL<33939> A_IWL<33938> A_IWL<33937> A_IWL<33936> A_IWL<33935> A_IWL<33934> A_IWL<33933> A_IWL<33932> A_IWL<33931> A_IWL<33930> A_IWL<33929> A_IWL<33928> A_IWL<33927> A_IWL<33926> A_IWL<33925> A_IWL<33924> A_IWL<33923> A_IWL<33922> A_IWL<33921> A_IWL<33920> A_IWL<33919> A_IWL<33918> A_IWL<33917> A_IWL<33916> A_IWL<33915> A_IWL<33914> A_IWL<33913> A_IWL<33912> A_IWL<33911> A_IWL<33910> A_IWL<33909> A_IWL<33908> A_IWL<33907> A_IWL<33906> A_IWL<33905> A_IWL<33904> A_IWL<33903> A_IWL<33902> A_IWL<33901> A_IWL<33900> A_IWL<33899> A_IWL<33898> A_IWL<33897> A_IWL<33896> A_IWL<33895> A_IWL<33894> A_IWL<33893> A_IWL<33892> A_IWL<33891> A_IWL<33890> A_IWL<33889> A_IWL<33888> A_IWL<33887> A_IWL<33886> A_IWL<33885> A_IWL<33884> A_IWL<33883> A_IWL<33882> A_IWL<33881> A_IWL<33880> A_IWL<33879> A_IWL<33878> A_IWL<33877> A_IWL<33876> A_IWL<33875> A_IWL<33874> A_IWL<33873> A_IWL<33872> A_IWL<33871> A_IWL<33870> A_IWL<33869> A_IWL<33868> A_IWL<33867> A_IWL<33866> A_IWL<33865> A_IWL<33864> A_IWL<33863> A_IWL<33862> A_IWL<33861> A_IWL<33860> A_IWL<33859> A_IWL<33858> A_IWL<33857> A_IWL<33856> A_IWL<33855> A_IWL<33854> A_IWL<33853> A_IWL<33852> A_IWL<33851> A_IWL<33850> A_IWL<33849> A_IWL<33848> A_IWL<33847> A_IWL<33846> A_IWL<33845> A_IWL<33844> A_IWL<33843> A_IWL<33842> A_IWL<33841> A_IWL<33840> A_IWL<33839> A_IWL<33838> A_IWL<33837> A_IWL<33836> A_IWL<33835> A_IWL<33834> A_IWL<33833> A_IWL<33832> A_IWL<33831> A_IWL<33830> A_IWL<33829> A_IWL<33828> A_IWL<33827> A_IWL<33826> A_IWL<33825> A_IWL<33824> A_IWL<33823> A_IWL<33822> A_IWL<33821> A_IWL<33820> A_IWL<33819> A_IWL<33818> A_IWL<33817> A_IWL<33816> A_IWL<33815> A_IWL<33814> A_IWL<33813> A_IWL<33812> A_IWL<33811> A_IWL<33810> A_IWL<33809> A_IWL<33808> A_IWL<33807> A_IWL<33806> A_IWL<33805> A_IWL<33804> A_IWL<33803> A_IWL<33802> A_IWL<33801> A_IWL<33800> A_IWL<33799> A_IWL<33798> A_IWL<33797> A_IWL<33796> A_IWL<33795> A_IWL<33794> A_IWL<33793> A_IWL<33792> A_IWL<34815> A_IWL<34814> A_IWL<34813> A_IWL<34812> A_IWL<34811> A_IWL<34810> A_IWL<34809> A_IWL<34808> A_IWL<34807> A_IWL<34806> A_IWL<34805> A_IWL<34804> A_IWL<34803> A_IWL<34802> A_IWL<34801> A_IWL<34800> A_IWL<34799> A_IWL<34798> A_IWL<34797> A_IWL<34796> A_IWL<34795> A_IWL<34794> A_IWL<34793> A_IWL<34792> A_IWL<34791> A_IWL<34790> A_IWL<34789> A_IWL<34788> A_IWL<34787> A_IWL<34786> A_IWL<34785> A_IWL<34784> A_IWL<34783> A_IWL<34782> A_IWL<34781> A_IWL<34780> A_IWL<34779> A_IWL<34778> A_IWL<34777> A_IWL<34776> A_IWL<34775> A_IWL<34774> A_IWL<34773> A_IWL<34772> A_IWL<34771> A_IWL<34770> A_IWL<34769> A_IWL<34768> A_IWL<34767> A_IWL<34766> A_IWL<34765> A_IWL<34764> A_IWL<34763> A_IWL<34762> A_IWL<34761> A_IWL<34760> A_IWL<34759> A_IWL<34758> A_IWL<34757> A_IWL<34756> A_IWL<34755> A_IWL<34754> A_IWL<34753> A_IWL<34752> A_IWL<34751> A_IWL<34750> A_IWL<34749> A_IWL<34748> A_IWL<34747> A_IWL<34746> A_IWL<34745> A_IWL<34744> A_IWL<34743> A_IWL<34742> A_IWL<34741> A_IWL<34740> A_IWL<34739> A_IWL<34738> A_IWL<34737> A_IWL<34736> A_IWL<34735> A_IWL<34734> A_IWL<34733> A_IWL<34732> A_IWL<34731> A_IWL<34730> A_IWL<34729> A_IWL<34728> A_IWL<34727> A_IWL<34726> A_IWL<34725> A_IWL<34724> A_IWL<34723> A_IWL<34722> A_IWL<34721> A_IWL<34720> A_IWL<34719> A_IWL<34718> A_IWL<34717> A_IWL<34716> A_IWL<34715> A_IWL<34714> A_IWL<34713> A_IWL<34712> A_IWL<34711> A_IWL<34710> A_IWL<34709> A_IWL<34708> A_IWL<34707> A_IWL<34706> A_IWL<34705> A_IWL<34704> A_IWL<34703> A_IWL<34702> A_IWL<34701> A_IWL<34700> A_IWL<34699> A_IWL<34698> A_IWL<34697> A_IWL<34696> A_IWL<34695> A_IWL<34694> A_IWL<34693> A_IWL<34692> A_IWL<34691> A_IWL<34690> A_IWL<34689> A_IWL<34688> A_IWL<34687> A_IWL<34686> A_IWL<34685> A_IWL<34684> A_IWL<34683> A_IWL<34682> A_IWL<34681> A_IWL<34680> A_IWL<34679> A_IWL<34678> A_IWL<34677> A_IWL<34676> A_IWL<34675> A_IWL<34674> A_IWL<34673> A_IWL<34672> A_IWL<34671> A_IWL<34670> A_IWL<34669> A_IWL<34668> A_IWL<34667> A_IWL<34666> A_IWL<34665> A_IWL<34664> A_IWL<34663> A_IWL<34662> A_IWL<34661> A_IWL<34660> A_IWL<34659> A_IWL<34658> A_IWL<34657> A_IWL<34656> A_IWL<34655> A_IWL<34654> A_IWL<34653> A_IWL<34652> A_IWL<34651> A_IWL<34650> A_IWL<34649> A_IWL<34648> A_IWL<34647> A_IWL<34646> A_IWL<34645> A_IWL<34644> A_IWL<34643> A_IWL<34642> A_IWL<34641> A_IWL<34640> A_IWL<34639> A_IWL<34638> A_IWL<34637> A_IWL<34636> A_IWL<34635> A_IWL<34634> A_IWL<34633> A_IWL<34632> A_IWL<34631> A_IWL<34630> A_IWL<34629> A_IWL<34628> A_IWL<34627> A_IWL<34626> A_IWL<34625> A_IWL<34624> A_IWL<34623> A_IWL<34622> A_IWL<34621> A_IWL<34620> A_IWL<34619> A_IWL<34618> A_IWL<34617> A_IWL<34616> A_IWL<34615> A_IWL<34614> A_IWL<34613> A_IWL<34612> A_IWL<34611> A_IWL<34610> A_IWL<34609> A_IWL<34608> A_IWL<34607> A_IWL<34606> A_IWL<34605> A_IWL<34604> A_IWL<34603> A_IWL<34602> A_IWL<34601> A_IWL<34600> A_IWL<34599> A_IWL<34598> A_IWL<34597> A_IWL<34596> A_IWL<34595> A_IWL<34594> A_IWL<34593> A_IWL<34592> A_IWL<34591> A_IWL<34590> A_IWL<34589> A_IWL<34588> A_IWL<34587> A_IWL<34586> A_IWL<34585> A_IWL<34584> A_IWL<34583> A_IWL<34582> A_IWL<34581> A_IWL<34580> A_IWL<34579> A_IWL<34578> A_IWL<34577> A_IWL<34576> A_IWL<34575> A_IWL<34574> A_IWL<34573> A_IWL<34572> A_IWL<34571> A_IWL<34570> A_IWL<34569> A_IWL<34568> A_IWL<34567> A_IWL<34566> A_IWL<34565> A_IWL<34564> A_IWL<34563> A_IWL<34562> A_IWL<34561> A_IWL<34560> A_IWL<34559> A_IWL<34558> A_IWL<34557> A_IWL<34556> A_IWL<34555> A_IWL<34554> A_IWL<34553> A_IWL<34552> A_IWL<34551> A_IWL<34550> A_IWL<34549> A_IWL<34548> A_IWL<34547> A_IWL<34546> A_IWL<34545> A_IWL<34544> A_IWL<34543> A_IWL<34542> A_IWL<34541> A_IWL<34540> A_IWL<34539> A_IWL<34538> A_IWL<34537> A_IWL<34536> A_IWL<34535> A_IWL<34534> A_IWL<34533> A_IWL<34532> A_IWL<34531> A_IWL<34530> A_IWL<34529> A_IWL<34528> A_IWL<34527> A_IWL<34526> A_IWL<34525> A_IWL<34524> A_IWL<34523> A_IWL<34522> A_IWL<34521> A_IWL<34520> A_IWL<34519> A_IWL<34518> A_IWL<34517> A_IWL<34516> A_IWL<34515> A_IWL<34514> A_IWL<34513> A_IWL<34512> A_IWL<34511> A_IWL<34510> A_IWL<34509> A_IWL<34508> A_IWL<34507> A_IWL<34506> A_IWL<34505> A_IWL<34504> A_IWL<34503> A_IWL<34502> A_IWL<34501> A_IWL<34500> A_IWL<34499> A_IWL<34498> A_IWL<34497> A_IWL<34496> A_IWL<34495> A_IWL<34494> A_IWL<34493> A_IWL<34492> A_IWL<34491> A_IWL<34490> A_IWL<34489> A_IWL<34488> A_IWL<34487> A_IWL<34486> A_IWL<34485> A_IWL<34484> A_IWL<34483> A_IWL<34482> A_IWL<34481> A_IWL<34480> A_IWL<34479> A_IWL<34478> A_IWL<34477> A_IWL<34476> A_IWL<34475> A_IWL<34474> A_IWL<34473> A_IWL<34472> A_IWL<34471> A_IWL<34470> A_IWL<34469> A_IWL<34468> A_IWL<34467> A_IWL<34466> A_IWL<34465> A_IWL<34464> A_IWL<34463> A_IWL<34462> A_IWL<34461> A_IWL<34460> A_IWL<34459> A_IWL<34458> A_IWL<34457> A_IWL<34456> A_IWL<34455> A_IWL<34454> A_IWL<34453> A_IWL<34452> A_IWL<34451> A_IWL<34450> A_IWL<34449> A_IWL<34448> A_IWL<34447> A_IWL<34446> A_IWL<34445> A_IWL<34444> A_IWL<34443> A_IWL<34442> A_IWL<34441> A_IWL<34440> A_IWL<34439> A_IWL<34438> A_IWL<34437> A_IWL<34436> A_IWL<34435> A_IWL<34434> A_IWL<34433> A_IWL<34432> A_IWL<34431> A_IWL<34430> A_IWL<34429> A_IWL<34428> A_IWL<34427> A_IWL<34426> A_IWL<34425> A_IWL<34424> A_IWL<34423> A_IWL<34422> A_IWL<34421> A_IWL<34420> A_IWL<34419> A_IWL<34418> A_IWL<34417> A_IWL<34416> A_IWL<34415> A_IWL<34414> A_IWL<34413> A_IWL<34412> A_IWL<34411> A_IWL<34410> A_IWL<34409> A_IWL<34408> A_IWL<34407> A_IWL<34406> A_IWL<34405> A_IWL<34404> A_IWL<34403> A_IWL<34402> A_IWL<34401> A_IWL<34400> A_IWL<34399> A_IWL<34398> A_IWL<34397> A_IWL<34396> A_IWL<34395> A_IWL<34394> A_IWL<34393> A_IWL<34392> A_IWL<34391> A_IWL<34390> A_IWL<34389> A_IWL<34388> A_IWL<34387> A_IWL<34386> A_IWL<34385> A_IWL<34384> A_IWL<34383> A_IWL<34382> A_IWL<34381> A_IWL<34380> A_IWL<34379> A_IWL<34378> A_IWL<34377> A_IWL<34376> A_IWL<34375> A_IWL<34374> A_IWL<34373> A_IWL<34372> A_IWL<34371> A_IWL<34370> A_IWL<34369> A_IWL<34368> A_IWL<34367> A_IWL<34366> A_IWL<34365> A_IWL<34364> A_IWL<34363> A_IWL<34362> A_IWL<34361> A_IWL<34360> A_IWL<34359> A_IWL<34358> A_IWL<34357> A_IWL<34356> A_IWL<34355> A_IWL<34354> A_IWL<34353> A_IWL<34352> A_IWL<34351> A_IWL<34350> A_IWL<34349> A_IWL<34348> A_IWL<34347> A_IWL<34346> A_IWL<34345> A_IWL<34344> A_IWL<34343> A_IWL<34342> A_IWL<34341> A_IWL<34340> A_IWL<34339> A_IWL<34338> A_IWL<34337> A_IWL<34336> A_IWL<34335> A_IWL<34334> A_IWL<34333> A_IWL<34332> A_IWL<34331> A_IWL<34330> A_IWL<34329> A_IWL<34328> A_IWL<34327> A_IWL<34326> A_IWL<34325> A_IWL<34324> A_IWL<34323> A_IWL<34322> A_IWL<34321> A_IWL<34320> A_IWL<34319> A_IWL<34318> A_IWL<34317> A_IWL<34316> A_IWL<34315> A_IWL<34314> A_IWL<34313> A_IWL<34312> A_IWL<34311> A_IWL<34310> A_IWL<34309> A_IWL<34308> A_IWL<34307> A_IWL<34306> A_IWL<34305> A_IWL<34304> VDD_CORE VSS / RM_IHPSG13_8192x32_c4_1P_COLUMN_pcell_0 +XCOL<66> A_BLC<133> A_BLC<132> A_BLC_TOP<133> A_BLC_TOP<132> A_BLT<133> A_BLT<132> A_BLT_TOP<133> A_BLT_TOP<132> A_IWL<33791> A_IWL<33790> A_IWL<33789> A_IWL<33788> A_IWL<33787> A_IWL<33786> A_IWL<33785> A_IWL<33784> A_IWL<33783> A_IWL<33782> A_IWL<33781> A_IWL<33780> A_IWL<33779> A_IWL<33778> A_IWL<33777> A_IWL<33776> A_IWL<33775> A_IWL<33774> A_IWL<33773> A_IWL<33772> A_IWL<33771> A_IWL<33770> A_IWL<33769> A_IWL<33768> A_IWL<33767> A_IWL<33766> A_IWL<33765> A_IWL<33764> A_IWL<33763> A_IWL<33762> A_IWL<33761> A_IWL<33760> A_IWL<33759> A_IWL<33758> A_IWL<33757> A_IWL<33756> A_IWL<33755> A_IWL<33754> A_IWL<33753> A_IWL<33752> A_IWL<33751> A_IWL<33750> A_IWL<33749> A_IWL<33748> A_IWL<33747> A_IWL<33746> A_IWL<33745> A_IWL<33744> A_IWL<33743> A_IWL<33742> A_IWL<33741> A_IWL<33740> A_IWL<33739> A_IWL<33738> A_IWL<33737> A_IWL<33736> A_IWL<33735> A_IWL<33734> A_IWL<33733> A_IWL<33732> A_IWL<33731> A_IWL<33730> A_IWL<33729> A_IWL<33728> A_IWL<33727> A_IWL<33726> A_IWL<33725> A_IWL<33724> A_IWL<33723> A_IWL<33722> A_IWL<33721> A_IWL<33720> A_IWL<33719> A_IWL<33718> A_IWL<33717> A_IWL<33716> A_IWL<33715> A_IWL<33714> A_IWL<33713> A_IWL<33712> A_IWL<33711> A_IWL<33710> A_IWL<33709> A_IWL<33708> A_IWL<33707> A_IWL<33706> A_IWL<33705> A_IWL<33704> A_IWL<33703> A_IWL<33702> A_IWL<33701> A_IWL<33700> A_IWL<33699> A_IWL<33698> A_IWL<33697> A_IWL<33696> A_IWL<33695> A_IWL<33694> A_IWL<33693> A_IWL<33692> A_IWL<33691> A_IWL<33690> A_IWL<33689> A_IWL<33688> A_IWL<33687> A_IWL<33686> A_IWL<33685> A_IWL<33684> A_IWL<33683> A_IWL<33682> A_IWL<33681> A_IWL<33680> A_IWL<33679> A_IWL<33678> A_IWL<33677> A_IWL<33676> A_IWL<33675> A_IWL<33674> A_IWL<33673> A_IWL<33672> A_IWL<33671> A_IWL<33670> A_IWL<33669> A_IWL<33668> A_IWL<33667> A_IWL<33666> A_IWL<33665> A_IWL<33664> A_IWL<33663> A_IWL<33662> A_IWL<33661> A_IWL<33660> A_IWL<33659> A_IWL<33658> A_IWL<33657> A_IWL<33656> A_IWL<33655> A_IWL<33654> A_IWL<33653> A_IWL<33652> A_IWL<33651> A_IWL<33650> A_IWL<33649> A_IWL<33648> A_IWL<33647> A_IWL<33646> A_IWL<33645> A_IWL<33644> A_IWL<33643> A_IWL<33642> A_IWL<33641> A_IWL<33640> A_IWL<33639> A_IWL<33638> A_IWL<33637> A_IWL<33636> A_IWL<33635> A_IWL<33634> A_IWL<33633> A_IWL<33632> A_IWL<33631> A_IWL<33630> A_IWL<33629> A_IWL<33628> A_IWL<33627> A_IWL<33626> A_IWL<33625> A_IWL<33624> A_IWL<33623> A_IWL<33622> A_IWL<33621> A_IWL<33620> A_IWL<33619> A_IWL<33618> A_IWL<33617> A_IWL<33616> A_IWL<33615> A_IWL<33614> A_IWL<33613> A_IWL<33612> A_IWL<33611> A_IWL<33610> A_IWL<33609> A_IWL<33608> A_IWL<33607> A_IWL<33606> A_IWL<33605> A_IWL<33604> A_IWL<33603> A_IWL<33602> A_IWL<33601> A_IWL<33600> A_IWL<33599> A_IWL<33598> A_IWL<33597> A_IWL<33596> A_IWL<33595> A_IWL<33594> A_IWL<33593> A_IWL<33592> A_IWL<33591> A_IWL<33590> A_IWL<33589> A_IWL<33588> A_IWL<33587> A_IWL<33586> A_IWL<33585> A_IWL<33584> A_IWL<33583> A_IWL<33582> A_IWL<33581> A_IWL<33580> A_IWL<33579> A_IWL<33578> A_IWL<33577> A_IWL<33576> A_IWL<33575> A_IWL<33574> A_IWL<33573> A_IWL<33572> A_IWL<33571> A_IWL<33570> A_IWL<33569> A_IWL<33568> A_IWL<33567> A_IWL<33566> A_IWL<33565> A_IWL<33564> A_IWL<33563> A_IWL<33562> A_IWL<33561> A_IWL<33560> A_IWL<33559> A_IWL<33558> A_IWL<33557> A_IWL<33556> A_IWL<33555> A_IWL<33554> A_IWL<33553> A_IWL<33552> A_IWL<33551> A_IWL<33550> A_IWL<33549> A_IWL<33548> A_IWL<33547> A_IWL<33546> A_IWL<33545> A_IWL<33544> A_IWL<33543> A_IWL<33542> A_IWL<33541> A_IWL<33540> A_IWL<33539> A_IWL<33538> A_IWL<33537> A_IWL<33536> A_IWL<33535> A_IWL<33534> A_IWL<33533> A_IWL<33532> A_IWL<33531> A_IWL<33530> A_IWL<33529> A_IWL<33528> A_IWL<33527> A_IWL<33526> A_IWL<33525> A_IWL<33524> A_IWL<33523> A_IWL<33522> A_IWL<33521> A_IWL<33520> A_IWL<33519> A_IWL<33518> A_IWL<33517> A_IWL<33516> A_IWL<33515> A_IWL<33514> A_IWL<33513> A_IWL<33512> A_IWL<33511> A_IWL<33510> A_IWL<33509> A_IWL<33508> A_IWL<33507> A_IWL<33506> A_IWL<33505> A_IWL<33504> A_IWL<33503> A_IWL<33502> A_IWL<33501> A_IWL<33500> A_IWL<33499> A_IWL<33498> A_IWL<33497> A_IWL<33496> A_IWL<33495> A_IWL<33494> A_IWL<33493> A_IWL<33492> A_IWL<33491> A_IWL<33490> A_IWL<33489> A_IWL<33488> A_IWL<33487> A_IWL<33486> A_IWL<33485> A_IWL<33484> A_IWL<33483> A_IWL<33482> A_IWL<33481> A_IWL<33480> A_IWL<33479> A_IWL<33478> A_IWL<33477> A_IWL<33476> A_IWL<33475> A_IWL<33474> A_IWL<33473> A_IWL<33472> A_IWL<33471> A_IWL<33470> A_IWL<33469> A_IWL<33468> A_IWL<33467> A_IWL<33466> A_IWL<33465> A_IWL<33464> A_IWL<33463> A_IWL<33462> A_IWL<33461> A_IWL<33460> A_IWL<33459> A_IWL<33458> A_IWL<33457> A_IWL<33456> A_IWL<33455> A_IWL<33454> A_IWL<33453> A_IWL<33452> A_IWL<33451> A_IWL<33450> A_IWL<33449> A_IWL<33448> A_IWL<33447> A_IWL<33446> A_IWL<33445> A_IWL<33444> A_IWL<33443> A_IWL<33442> A_IWL<33441> A_IWL<33440> A_IWL<33439> A_IWL<33438> A_IWL<33437> A_IWL<33436> A_IWL<33435> A_IWL<33434> A_IWL<33433> A_IWL<33432> A_IWL<33431> A_IWL<33430> A_IWL<33429> A_IWL<33428> A_IWL<33427> A_IWL<33426> A_IWL<33425> A_IWL<33424> A_IWL<33423> A_IWL<33422> A_IWL<33421> A_IWL<33420> A_IWL<33419> A_IWL<33418> A_IWL<33417> A_IWL<33416> A_IWL<33415> A_IWL<33414> A_IWL<33413> A_IWL<33412> A_IWL<33411> A_IWL<33410> A_IWL<33409> A_IWL<33408> A_IWL<33407> A_IWL<33406> A_IWL<33405> A_IWL<33404> A_IWL<33403> A_IWL<33402> A_IWL<33401> A_IWL<33400> A_IWL<33399> A_IWL<33398> A_IWL<33397> A_IWL<33396> A_IWL<33395> A_IWL<33394> A_IWL<33393> A_IWL<33392> A_IWL<33391> A_IWL<33390> A_IWL<33389> A_IWL<33388> A_IWL<33387> A_IWL<33386> A_IWL<33385> A_IWL<33384> A_IWL<33383> A_IWL<33382> A_IWL<33381> A_IWL<33380> A_IWL<33379> A_IWL<33378> A_IWL<33377> A_IWL<33376> A_IWL<33375> A_IWL<33374> A_IWL<33373> A_IWL<33372> A_IWL<33371> A_IWL<33370> A_IWL<33369> A_IWL<33368> A_IWL<33367> A_IWL<33366> A_IWL<33365> A_IWL<33364> A_IWL<33363> A_IWL<33362> A_IWL<33361> A_IWL<33360> A_IWL<33359> A_IWL<33358> A_IWL<33357> A_IWL<33356> A_IWL<33355> A_IWL<33354> A_IWL<33353> A_IWL<33352> A_IWL<33351> A_IWL<33350> A_IWL<33349> A_IWL<33348> A_IWL<33347> A_IWL<33346> A_IWL<33345> A_IWL<33344> A_IWL<33343> A_IWL<33342> A_IWL<33341> A_IWL<33340> A_IWL<33339> A_IWL<33338> A_IWL<33337> A_IWL<33336> A_IWL<33335> A_IWL<33334> A_IWL<33333> A_IWL<33332> A_IWL<33331> A_IWL<33330> A_IWL<33329> A_IWL<33328> A_IWL<33327> A_IWL<33326> A_IWL<33325> A_IWL<33324> A_IWL<33323> A_IWL<33322> A_IWL<33321> A_IWL<33320> A_IWL<33319> A_IWL<33318> A_IWL<33317> A_IWL<33316> A_IWL<33315> A_IWL<33314> A_IWL<33313> A_IWL<33312> A_IWL<33311> A_IWL<33310> A_IWL<33309> A_IWL<33308> A_IWL<33307> A_IWL<33306> A_IWL<33305> A_IWL<33304> A_IWL<33303> A_IWL<33302> A_IWL<33301> A_IWL<33300> A_IWL<33299> A_IWL<33298> A_IWL<33297> A_IWL<33296> A_IWL<33295> A_IWL<33294> A_IWL<33293> A_IWL<33292> A_IWL<33291> A_IWL<33290> A_IWL<33289> A_IWL<33288> A_IWL<33287> A_IWL<33286> A_IWL<33285> A_IWL<33284> A_IWL<33283> A_IWL<33282> A_IWL<33281> A_IWL<33280> A_IWL<34303> A_IWL<34302> A_IWL<34301> A_IWL<34300> A_IWL<34299> A_IWL<34298> A_IWL<34297> A_IWL<34296> A_IWL<34295> A_IWL<34294> A_IWL<34293> A_IWL<34292> A_IWL<34291> A_IWL<34290> A_IWL<34289> A_IWL<34288> A_IWL<34287> A_IWL<34286> A_IWL<34285> A_IWL<34284> A_IWL<34283> A_IWL<34282> A_IWL<34281> A_IWL<34280> A_IWL<34279> A_IWL<34278> A_IWL<34277> A_IWL<34276> A_IWL<34275> A_IWL<34274> A_IWL<34273> A_IWL<34272> A_IWL<34271> A_IWL<34270> A_IWL<34269> A_IWL<34268> A_IWL<34267> A_IWL<34266> A_IWL<34265> A_IWL<34264> A_IWL<34263> A_IWL<34262> A_IWL<34261> A_IWL<34260> A_IWL<34259> A_IWL<34258> A_IWL<34257> A_IWL<34256> A_IWL<34255> A_IWL<34254> A_IWL<34253> A_IWL<34252> A_IWL<34251> A_IWL<34250> A_IWL<34249> A_IWL<34248> A_IWL<34247> A_IWL<34246> A_IWL<34245> A_IWL<34244> A_IWL<34243> A_IWL<34242> A_IWL<34241> A_IWL<34240> A_IWL<34239> A_IWL<34238> A_IWL<34237> A_IWL<34236> A_IWL<34235> A_IWL<34234> A_IWL<34233> A_IWL<34232> A_IWL<34231> A_IWL<34230> A_IWL<34229> A_IWL<34228> A_IWL<34227> A_IWL<34226> A_IWL<34225> A_IWL<34224> A_IWL<34223> A_IWL<34222> A_IWL<34221> A_IWL<34220> A_IWL<34219> A_IWL<34218> A_IWL<34217> A_IWL<34216> A_IWL<34215> A_IWL<34214> A_IWL<34213> A_IWL<34212> A_IWL<34211> A_IWL<34210> A_IWL<34209> A_IWL<34208> A_IWL<34207> A_IWL<34206> A_IWL<34205> A_IWL<34204> A_IWL<34203> A_IWL<34202> A_IWL<34201> A_IWL<34200> A_IWL<34199> A_IWL<34198> A_IWL<34197> A_IWL<34196> A_IWL<34195> A_IWL<34194> A_IWL<34193> A_IWL<34192> A_IWL<34191> A_IWL<34190> A_IWL<34189> A_IWL<34188> A_IWL<34187> A_IWL<34186> A_IWL<34185> A_IWL<34184> A_IWL<34183> A_IWL<34182> A_IWL<34181> A_IWL<34180> A_IWL<34179> A_IWL<34178> A_IWL<34177> A_IWL<34176> A_IWL<34175> A_IWL<34174> A_IWL<34173> A_IWL<34172> A_IWL<34171> A_IWL<34170> A_IWL<34169> A_IWL<34168> A_IWL<34167> A_IWL<34166> A_IWL<34165> A_IWL<34164> A_IWL<34163> A_IWL<34162> A_IWL<34161> A_IWL<34160> A_IWL<34159> A_IWL<34158> A_IWL<34157> A_IWL<34156> A_IWL<34155> A_IWL<34154> A_IWL<34153> A_IWL<34152> A_IWL<34151> A_IWL<34150> A_IWL<34149> A_IWL<34148> A_IWL<34147> A_IWL<34146> A_IWL<34145> A_IWL<34144> A_IWL<34143> A_IWL<34142> A_IWL<34141> A_IWL<34140> A_IWL<34139> A_IWL<34138> A_IWL<34137> A_IWL<34136> A_IWL<34135> A_IWL<34134> A_IWL<34133> A_IWL<34132> A_IWL<34131> A_IWL<34130> A_IWL<34129> A_IWL<34128> A_IWL<34127> A_IWL<34126> A_IWL<34125> A_IWL<34124> A_IWL<34123> A_IWL<34122> A_IWL<34121> A_IWL<34120> A_IWL<34119> A_IWL<34118> A_IWL<34117> A_IWL<34116> A_IWL<34115> A_IWL<34114> A_IWL<34113> A_IWL<34112> A_IWL<34111> A_IWL<34110> A_IWL<34109> A_IWL<34108> A_IWL<34107> A_IWL<34106> A_IWL<34105> A_IWL<34104> A_IWL<34103> A_IWL<34102> A_IWL<34101> A_IWL<34100> A_IWL<34099> A_IWL<34098> A_IWL<34097> A_IWL<34096> A_IWL<34095> A_IWL<34094> A_IWL<34093> A_IWL<34092> A_IWL<34091> A_IWL<34090> A_IWL<34089> A_IWL<34088> A_IWL<34087> A_IWL<34086> A_IWL<34085> A_IWL<34084> A_IWL<34083> A_IWL<34082> A_IWL<34081> A_IWL<34080> A_IWL<34079> A_IWL<34078> A_IWL<34077> A_IWL<34076> A_IWL<34075> A_IWL<34074> A_IWL<34073> A_IWL<34072> A_IWL<34071> A_IWL<34070> A_IWL<34069> A_IWL<34068> A_IWL<34067> A_IWL<34066> A_IWL<34065> A_IWL<34064> A_IWL<34063> A_IWL<34062> A_IWL<34061> A_IWL<34060> A_IWL<34059> A_IWL<34058> A_IWL<34057> A_IWL<34056> A_IWL<34055> A_IWL<34054> A_IWL<34053> A_IWL<34052> A_IWL<34051> A_IWL<34050> A_IWL<34049> A_IWL<34048> A_IWL<34047> A_IWL<34046> A_IWL<34045> A_IWL<34044> A_IWL<34043> A_IWL<34042> A_IWL<34041> A_IWL<34040> A_IWL<34039> A_IWL<34038> A_IWL<34037> A_IWL<34036> A_IWL<34035> A_IWL<34034> A_IWL<34033> A_IWL<34032> A_IWL<34031> A_IWL<34030> A_IWL<34029> A_IWL<34028> A_IWL<34027> A_IWL<34026> A_IWL<34025> A_IWL<34024> A_IWL<34023> A_IWL<34022> A_IWL<34021> A_IWL<34020> A_IWL<34019> A_IWL<34018> A_IWL<34017> A_IWL<34016> A_IWL<34015> A_IWL<34014> A_IWL<34013> A_IWL<34012> A_IWL<34011> A_IWL<34010> A_IWL<34009> A_IWL<34008> A_IWL<34007> A_IWL<34006> A_IWL<34005> A_IWL<34004> A_IWL<34003> A_IWL<34002> A_IWL<34001> A_IWL<34000> A_IWL<33999> A_IWL<33998> A_IWL<33997> A_IWL<33996> A_IWL<33995> A_IWL<33994> A_IWL<33993> A_IWL<33992> A_IWL<33991> A_IWL<33990> A_IWL<33989> A_IWL<33988> A_IWL<33987> A_IWL<33986> A_IWL<33985> A_IWL<33984> A_IWL<33983> A_IWL<33982> A_IWL<33981> A_IWL<33980> A_IWL<33979> A_IWL<33978> A_IWL<33977> A_IWL<33976> A_IWL<33975> A_IWL<33974> A_IWL<33973> A_IWL<33972> A_IWL<33971> A_IWL<33970> A_IWL<33969> A_IWL<33968> A_IWL<33967> A_IWL<33966> A_IWL<33965> A_IWL<33964> A_IWL<33963> A_IWL<33962> A_IWL<33961> A_IWL<33960> A_IWL<33959> A_IWL<33958> A_IWL<33957> A_IWL<33956> A_IWL<33955> A_IWL<33954> A_IWL<33953> A_IWL<33952> A_IWL<33951> A_IWL<33950> A_IWL<33949> A_IWL<33948> A_IWL<33947> A_IWL<33946> A_IWL<33945> A_IWL<33944> A_IWL<33943> A_IWL<33942> A_IWL<33941> A_IWL<33940> A_IWL<33939> A_IWL<33938> A_IWL<33937> A_IWL<33936> A_IWL<33935> A_IWL<33934> A_IWL<33933> A_IWL<33932> A_IWL<33931> A_IWL<33930> A_IWL<33929> A_IWL<33928> A_IWL<33927> A_IWL<33926> A_IWL<33925> A_IWL<33924> A_IWL<33923> A_IWL<33922> A_IWL<33921> A_IWL<33920> A_IWL<33919> A_IWL<33918> A_IWL<33917> A_IWL<33916> A_IWL<33915> A_IWL<33914> A_IWL<33913> A_IWL<33912> A_IWL<33911> A_IWL<33910> A_IWL<33909> A_IWL<33908> A_IWL<33907> A_IWL<33906> A_IWL<33905> A_IWL<33904> A_IWL<33903> A_IWL<33902> A_IWL<33901> A_IWL<33900> A_IWL<33899> A_IWL<33898> A_IWL<33897> A_IWL<33896> A_IWL<33895> A_IWL<33894> A_IWL<33893> A_IWL<33892> A_IWL<33891> A_IWL<33890> A_IWL<33889> A_IWL<33888> A_IWL<33887> A_IWL<33886> A_IWL<33885> A_IWL<33884> A_IWL<33883> A_IWL<33882> A_IWL<33881> A_IWL<33880> A_IWL<33879> A_IWL<33878> A_IWL<33877> A_IWL<33876> A_IWL<33875> A_IWL<33874> A_IWL<33873> A_IWL<33872> A_IWL<33871> A_IWL<33870> A_IWL<33869> A_IWL<33868> A_IWL<33867> A_IWL<33866> A_IWL<33865> A_IWL<33864> A_IWL<33863> A_IWL<33862> A_IWL<33861> A_IWL<33860> A_IWL<33859> A_IWL<33858> A_IWL<33857> A_IWL<33856> A_IWL<33855> A_IWL<33854> A_IWL<33853> A_IWL<33852> A_IWL<33851> A_IWL<33850> A_IWL<33849> A_IWL<33848> A_IWL<33847> A_IWL<33846> A_IWL<33845> A_IWL<33844> A_IWL<33843> A_IWL<33842> A_IWL<33841> A_IWL<33840> A_IWL<33839> A_IWL<33838> A_IWL<33837> A_IWL<33836> A_IWL<33835> A_IWL<33834> A_IWL<33833> A_IWL<33832> A_IWL<33831> A_IWL<33830> A_IWL<33829> A_IWL<33828> A_IWL<33827> A_IWL<33826> A_IWL<33825> A_IWL<33824> A_IWL<33823> A_IWL<33822> A_IWL<33821> A_IWL<33820> A_IWL<33819> A_IWL<33818> A_IWL<33817> A_IWL<33816> A_IWL<33815> A_IWL<33814> A_IWL<33813> A_IWL<33812> A_IWL<33811> A_IWL<33810> A_IWL<33809> A_IWL<33808> A_IWL<33807> A_IWL<33806> A_IWL<33805> A_IWL<33804> A_IWL<33803> A_IWL<33802> A_IWL<33801> A_IWL<33800> A_IWL<33799> A_IWL<33798> A_IWL<33797> A_IWL<33796> A_IWL<33795> A_IWL<33794> A_IWL<33793> A_IWL<33792> VDD_CORE VSS / RM_IHPSG13_8192x32_c4_1P_COLUMN_pcell_0 +XCOL<65> A_BLC<131> A_BLC<130> A_BLC_TOP<131> A_BLC_TOP<130> A_BLT<131> A_BLT<130> A_BLT_TOP<131> A_BLT_TOP<130> A_IWL<33279> A_IWL<33278> A_IWL<33277> A_IWL<33276> A_IWL<33275> A_IWL<33274> A_IWL<33273> A_IWL<33272> A_IWL<33271> A_IWL<33270> A_IWL<33269> A_IWL<33268> A_IWL<33267> A_IWL<33266> A_IWL<33265> A_IWL<33264> A_IWL<33263> A_IWL<33262> A_IWL<33261> A_IWL<33260> A_IWL<33259> A_IWL<33258> A_IWL<33257> A_IWL<33256> A_IWL<33255> A_IWL<33254> A_IWL<33253> A_IWL<33252> A_IWL<33251> A_IWL<33250> A_IWL<33249> A_IWL<33248> A_IWL<33247> A_IWL<33246> A_IWL<33245> A_IWL<33244> A_IWL<33243> A_IWL<33242> A_IWL<33241> A_IWL<33240> A_IWL<33239> A_IWL<33238> A_IWL<33237> A_IWL<33236> A_IWL<33235> A_IWL<33234> A_IWL<33233> A_IWL<33232> A_IWL<33231> A_IWL<33230> A_IWL<33229> A_IWL<33228> A_IWL<33227> A_IWL<33226> A_IWL<33225> A_IWL<33224> A_IWL<33223> A_IWL<33222> A_IWL<33221> A_IWL<33220> A_IWL<33219> A_IWL<33218> A_IWL<33217> A_IWL<33216> A_IWL<33215> A_IWL<33214> A_IWL<33213> A_IWL<33212> A_IWL<33211> A_IWL<33210> A_IWL<33209> A_IWL<33208> A_IWL<33207> A_IWL<33206> A_IWL<33205> A_IWL<33204> A_IWL<33203> A_IWL<33202> A_IWL<33201> A_IWL<33200> A_IWL<33199> A_IWL<33198> A_IWL<33197> A_IWL<33196> A_IWL<33195> A_IWL<33194> A_IWL<33193> A_IWL<33192> A_IWL<33191> A_IWL<33190> A_IWL<33189> A_IWL<33188> A_IWL<33187> A_IWL<33186> A_IWL<33185> A_IWL<33184> A_IWL<33183> A_IWL<33182> A_IWL<33181> A_IWL<33180> A_IWL<33179> A_IWL<33178> A_IWL<33177> A_IWL<33176> A_IWL<33175> A_IWL<33174> A_IWL<33173> A_IWL<33172> A_IWL<33171> A_IWL<33170> A_IWL<33169> A_IWL<33168> A_IWL<33167> A_IWL<33166> A_IWL<33165> A_IWL<33164> A_IWL<33163> A_IWL<33162> A_IWL<33161> A_IWL<33160> A_IWL<33159> A_IWL<33158> A_IWL<33157> A_IWL<33156> A_IWL<33155> A_IWL<33154> A_IWL<33153> A_IWL<33152> A_IWL<33151> A_IWL<33150> A_IWL<33149> A_IWL<33148> A_IWL<33147> A_IWL<33146> A_IWL<33145> A_IWL<33144> A_IWL<33143> A_IWL<33142> A_IWL<33141> A_IWL<33140> A_IWL<33139> A_IWL<33138> A_IWL<33137> A_IWL<33136> A_IWL<33135> A_IWL<33134> A_IWL<33133> A_IWL<33132> A_IWL<33131> A_IWL<33130> A_IWL<33129> A_IWL<33128> A_IWL<33127> A_IWL<33126> A_IWL<33125> A_IWL<33124> A_IWL<33123> A_IWL<33122> A_IWL<33121> A_IWL<33120> A_IWL<33119> A_IWL<33118> A_IWL<33117> A_IWL<33116> A_IWL<33115> A_IWL<33114> A_IWL<33113> A_IWL<33112> A_IWL<33111> A_IWL<33110> A_IWL<33109> A_IWL<33108> A_IWL<33107> A_IWL<33106> A_IWL<33105> A_IWL<33104> A_IWL<33103> A_IWL<33102> A_IWL<33101> A_IWL<33100> A_IWL<33099> A_IWL<33098> A_IWL<33097> A_IWL<33096> A_IWL<33095> A_IWL<33094> A_IWL<33093> A_IWL<33092> A_IWL<33091> A_IWL<33090> A_IWL<33089> A_IWL<33088> A_IWL<33087> A_IWL<33086> A_IWL<33085> A_IWL<33084> A_IWL<33083> A_IWL<33082> A_IWL<33081> A_IWL<33080> A_IWL<33079> A_IWL<33078> A_IWL<33077> A_IWL<33076> A_IWL<33075> A_IWL<33074> A_IWL<33073> A_IWL<33072> A_IWL<33071> A_IWL<33070> A_IWL<33069> A_IWL<33068> A_IWL<33067> A_IWL<33066> A_IWL<33065> A_IWL<33064> A_IWL<33063> A_IWL<33062> A_IWL<33061> A_IWL<33060> A_IWL<33059> A_IWL<33058> A_IWL<33057> A_IWL<33056> A_IWL<33055> A_IWL<33054> A_IWL<33053> A_IWL<33052> A_IWL<33051> A_IWL<33050> A_IWL<33049> A_IWL<33048> A_IWL<33047> A_IWL<33046> A_IWL<33045> A_IWL<33044> A_IWL<33043> A_IWL<33042> A_IWL<33041> A_IWL<33040> A_IWL<33039> A_IWL<33038> A_IWL<33037> A_IWL<33036> A_IWL<33035> A_IWL<33034> A_IWL<33033> A_IWL<33032> A_IWL<33031> A_IWL<33030> A_IWL<33029> A_IWL<33028> A_IWL<33027> A_IWL<33026> A_IWL<33025> A_IWL<33024> A_IWL<33023> A_IWL<33022> A_IWL<33021> A_IWL<33020> A_IWL<33019> A_IWL<33018> A_IWL<33017> A_IWL<33016> A_IWL<33015> A_IWL<33014> A_IWL<33013> A_IWL<33012> A_IWL<33011> A_IWL<33010> A_IWL<33009> A_IWL<33008> A_IWL<33007> A_IWL<33006> A_IWL<33005> A_IWL<33004> A_IWL<33003> A_IWL<33002> A_IWL<33001> A_IWL<33000> A_IWL<32999> A_IWL<32998> A_IWL<32997> A_IWL<32996> A_IWL<32995> A_IWL<32994> A_IWL<32993> A_IWL<32992> A_IWL<32991> A_IWL<32990> A_IWL<32989> A_IWL<32988> A_IWL<32987> A_IWL<32986> A_IWL<32985> A_IWL<32984> A_IWL<32983> A_IWL<32982> A_IWL<32981> A_IWL<32980> A_IWL<32979> A_IWL<32978> A_IWL<32977> A_IWL<32976> A_IWL<32975> A_IWL<32974> A_IWL<32973> A_IWL<32972> A_IWL<32971> A_IWL<32970> A_IWL<32969> A_IWL<32968> A_IWL<32967> A_IWL<32966> A_IWL<32965> A_IWL<32964> A_IWL<32963> A_IWL<32962> A_IWL<32961> A_IWL<32960> A_IWL<32959> A_IWL<32958> A_IWL<32957> A_IWL<32956> A_IWL<32955> A_IWL<32954> A_IWL<32953> A_IWL<32952> A_IWL<32951> A_IWL<32950> A_IWL<32949> A_IWL<32948> A_IWL<32947> A_IWL<32946> A_IWL<32945> A_IWL<32944> A_IWL<32943> A_IWL<32942> A_IWL<32941> A_IWL<32940> A_IWL<32939> A_IWL<32938> A_IWL<32937> A_IWL<32936> A_IWL<32935> A_IWL<32934> A_IWL<32933> A_IWL<32932> A_IWL<32931> A_IWL<32930> A_IWL<32929> A_IWL<32928> A_IWL<32927> A_IWL<32926> A_IWL<32925> A_IWL<32924> A_IWL<32923> A_IWL<32922> A_IWL<32921> A_IWL<32920> A_IWL<32919> A_IWL<32918> A_IWL<32917> A_IWL<32916> A_IWL<32915> A_IWL<32914> A_IWL<32913> A_IWL<32912> A_IWL<32911> A_IWL<32910> A_IWL<32909> A_IWL<32908> A_IWL<32907> A_IWL<32906> A_IWL<32905> A_IWL<32904> A_IWL<32903> A_IWL<32902> A_IWL<32901> A_IWL<32900> A_IWL<32899> A_IWL<32898> A_IWL<32897> A_IWL<32896> A_IWL<32895> A_IWL<32894> A_IWL<32893> A_IWL<32892> A_IWL<32891> A_IWL<32890> A_IWL<32889> A_IWL<32888> A_IWL<32887> A_IWL<32886> A_IWL<32885> A_IWL<32884> A_IWL<32883> A_IWL<32882> A_IWL<32881> A_IWL<32880> A_IWL<32879> A_IWL<32878> A_IWL<32877> A_IWL<32876> A_IWL<32875> A_IWL<32874> A_IWL<32873> A_IWL<32872> A_IWL<32871> A_IWL<32870> A_IWL<32869> A_IWL<32868> A_IWL<32867> A_IWL<32866> A_IWL<32865> A_IWL<32864> A_IWL<32863> A_IWL<32862> A_IWL<32861> A_IWL<32860> A_IWL<32859> A_IWL<32858> A_IWL<32857> A_IWL<32856> A_IWL<32855> A_IWL<32854> A_IWL<32853> A_IWL<32852> A_IWL<32851> A_IWL<32850> A_IWL<32849> A_IWL<32848> A_IWL<32847> A_IWL<32846> A_IWL<32845> A_IWL<32844> A_IWL<32843> A_IWL<32842> A_IWL<32841> A_IWL<32840> A_IWL<32839> A_IWL<32838> A_IWL<32837> A_IWL<32836> A_IWL<32835> A_IWL<32834> A_IWL<32833> A_IWL<32832> A_IWL<32831> A_IWL<32830> A_IWL<32829> A_IWL<32828> A_IWL<32827> A_IWL<32826> A_IWL<32825> A_IWL<32824> A_IWL<32823> A_IWL<32822> A_IWL<32821> A_IWL<32820> A_IWL<32819> A_IWL<32818> A_IWL<32817> A_IWL<32816> A_IWL<32815> A_IWL<32814> A_IWL<32813> A_IWL<32812> A_IWL<32811> A_IWL<32810> A_IWL<32809> A_IWL<32808> A_IWL<32807> A_IWL<32806> A_IWL<32805> A_IWL<32804> A_IWL<32803> A_IWL<32802> A_IWL<32801> A_IWL<32800> A_IWL<32799> A_IWL<32798> A_IWL<32797> A_IWL<32796> A_IWL<32795> A_IWL<32794> A_IWL<32793> A_IWL<32792> A_IWL<32791> A_IWL<32790> A_IWL<32789> A_IWL<32788> A_IWL<32787> A_IWL<32786> A_IWL<32785> A_IWL<32784> A_IWL<32783> A_IWL<32782> A_IWL<32781> A_IWL<32780> A_IWL<32779> A_IWL<32778> A_IWL<32777> A_IWL<32776> A_IWL<32775> A_IWL<32774> A_IWL<32773> A_IWL<32772> A_IWL<32771> A_IWL<32770> A_IWL<32769> A_IWL<32768> A_IWL<33791> A_IWL<33790> A_IWL<33789> A_IWL<33788> A_IWL<33787> A_IWL<33786> A_IWL<33785> A_IWL<33784> A_IWL<33783> A_IWL<33782> A_IWL<33781> A_IWL<33780> A_IWL<33779> A_IWL<33778> A_IWL<33777> A_IWL<33776> A_IWL<33775> A_IWL<33774> A_IWL<33773> A_IWL<33772> A_IWL<33771> A_IWL<33770> A_IWL<33769> A_IWL<33768> A_IWL<33767> A_IWL<33766> A_IWL<33765> A_IWL<33764> A_IWL<33763> A_IWL<33762> A_IWL<33761> A_IWL<33760> A_IWL<33759> A_IWL<33758> A_IWL<33757> A_IWL<33756> A_IWL<33755> A_IWL<33754> A_IWL<33753> A_IWL<33752> A_IWL<33751> A_IWL<33750> A_IWL<33749> A_IWL<33748> A_IWL<33747> A_IWL<33746> A_IWL<33745> A_IWL<33744> A_IWL<33743> A_IWL<33742> A_IWL<33741> A_IWL<33740> A_IWL<33739> A_IWL<33738> A_IWL<33737> A_IWL<33736> A_IWL<33735> A_IWL<33734> A_IWL<33733> A_IWL<33732> A_IWL<33731> A_IWL<33730> A_IWL<33729> A_IWL<33728> A_IWL<33727> A_IWL<33726> A_IWL<33725> A_IWL<33724> A_IWL<33723> A_IWL<33722> A_IWL<33721> A_IWL<33720> A_IWL<33719> A_IWL<33718> A_IWL<33717> A_IWL<33716> A_IWL<33715> A_IWL<33714> A_IWL<33713> A_IWL<33712> A_IWL<33711> A_IWL<33710> A_IWL<33709> A_IWL<33708> A_IWL<33707> A_IWL<33706> A_IWL<33705> A_IWL<33704> A_IWL<33703> A_IWL<33702> A_IWL<33701> A_IWL<33700> A_IWL<33699> A_IWL<33698> A_IWL<33697> A_IWL<33696> A_IWL<33695> A_IWL<33694> A_IWL<33693> A_IWL<33692> A_IWL<33691> A_IWL<33690> A_IWL<33689> A_IWL<33688> A_IWL<33687> A_IWL<33686> A_IWL<33685> A_IWL<33684> A_IWL<33683> A_IWL<33682> A_IWL<33681> A_IWL<33680> A_IWL<33679> A_IWL<33678> A_IWL<33677> A_IWL<33676> A_IWL<33675> A_IWL<33674> A_IWL<33673> A_IWL<33672> A_IWL<33671> A_IWL<33670> A_IWL<33669> A_IWL<33668> A_IWL<33667> A_IWL<33666> A_IWL<33665> A_IWL<33664> A_IWL<33663> A_IWL<33662> A_IWL<33661> A_IWL<33660> A_IWL<33659> A_IWL<33658> A_IWL<33657> A_IWL<33656> A_IWL<33655> A_IWL<33654> A_IWL<33653> A_IWL<33652> A_IWL<33651> A_IWL<33650> A_IWL<33649> A_IWL<33648> A_IWL<33647> A_IWL<33646> A_IWL<33645> A_IWL<33644> A_IWL<33643> A_IWL<33642> A_IWL<33641> A_IWL<33640> A_IWL<33639> A_IWL<33638> A_IWL<33637> A_IWL<33636> A_IWL<33635> A_IWL<33634> A_IWL<33633> A_IWL<33632> A_IWL<33631> A_IWL<33630> A_IWL<33629> A_IWL<33628> A_IWL<33627> A_IWL<33626> A_IWL<33625> A_IWL<33624> A_IWL<33623> A_IWL<33622> A_IWL<33621> A_IWL<33620> A_IWL<33619> A_IWL<33618> A_IWL<33617> A_IWL<33616> A_IWL<33615> A_IWL<33614> A_IWL<33613> A_IWL<33612> A_IWL<33611> A_IWL<33610> A_IWL<33609> A_IWL<33608> A_IWL<33607> A_IWL<33606> A_IWL<33605> A_IWL<33604> A_IWL<33603> A_IWL<33602> A_IWL<33601> A_IWL<33600> A_IWL<33599> A_IWL<33598> A_IWL<33597> A_IWL<33596> A_IWL<33595> A_IWL<33594> A_IWL<33593> A_IWL<33592> A_IWL<33591> A_IWL<33590> A_IWL<33589> A_IWL<33588> A_IWL<33587> A_IWL<33586> A_IWL<33585> A_IWL<33584> A_IWL<33583> A_IWL<33582> A_IWL<33581> A_IWL<33580> A_IWL<33579> A_IWL<33578> A_IWL<33577> A_IWL<33576> A_IWL<33575> A_IWL<33574> A_IWL<33573> A_IWL<33572> A_IWL<33571> A_IWL<33570> A_IWL<33569> A_IWL<33568> A_IWL<33567> A_IWL<33566> A_IWL<33565> A_IWL<33564> A_IWL<33563> A_IWL<33562> A_IWL<33561> A_IWL<33560> A_IWL<33559> A_IWL<33558> A_IWL<33557> A_IWL<33556> A_IWL<33555> A_IWL<33554> A_IWL<33553> A_IWL<33552> A_IWL<33551> A_IWL<33550> A_IWL<33549> A_IWL<33548> A_IWL<33547> A_IWL<33546> A_IWL<33545> A_IWL<33544> A_IWL<33543> A_IWL<33542> A_IWL<33541> A_IWL<33540> A_IWL<33539> A_IWL<33538> A_IWL<33537> A_IWL<33536> A_IWL<33535> A_IWL<33534> A_IWL<33533> A_IWL<33532> A_IWL<33531> A_IWL<33530> A_IWL<33529> A_IWL<33528> A_IWL<33527> A_IWL<33526> A_IWL<33525> A_IWL<33524> A_IWL<33523> A_IWL<33522> A_IWL<33521> A_IWL<33520> A_IWL<33519> A_IWL<33518> A_IWL<33517> A_IWL<33516> A_IWL<33515> A_IWL<33514> A_IWL<33513> A_IWL<33512> A_IWL<33511> A_IWL<33510> A_IWL<33509> A_IWL<33508> A_IWL<33507> A_IWL<33506> A_IWL<33505> A_IWL<33504> A_IWL<33503> A_IWL<33502> A_IWL<33501> A_IWL<33500> A_IWL<33499> A_IWL<33498> A_IWL<33497> A_IWL<33496> A_IWL<33495> A_IWL<33494> A_IWL<33493> A_IWL<33492> A_IWL<33491> A_IWL<33490> A_IWL<33489> A_IWL<33488> A_IWL<33487> A_IWL<33486> A_IWL<33485> A_IWL<33484> A_IWL<33483> A_IWL<33482> A_IWL<33481> A_IWL<33480> A_IWL<33479> A_IWL<33478> A_IWL<33477> A_IWL<33476> A_IWL<33475> A_IWL<33474> A_IWL<33473> A_IWL<33472> A_IWL<33471> A_IWL<33470> A_IWL<33469> A_IWL<33468> A_IWL<33467> A_IWL<33466> A_IWL<33465> A_IWL<33464> A_IWL<33463> A_IWL<33462> A_IWL<33461> A_IWL<33460> A_IWL<33459> A_IWL<33458> A_IWL<33457> A_IWL<33456> A_IWL<33455> A_IWL<33454> A_IWL<33453> A_IWL<33452> A_IWL<33451> A_IWL<33450> A_IWL<33449> A_IWL<33448> A_IWL<33447> A_IWL<33446> A_IWL<33445> A_IWL<33444> A_IWL<33443> A_IWL<33442> A_IWL<33441> A_IWL<33440> A_IWL<33439> A_IWL<33438> A_IWL<33437> A_IWL<33436> A_IWL<33435> A_IWL<33434> A_IWL<33433> A_IWL<33432> A_IWL<33431> A_IWL<33430> A_IWL<33429> A_IWL<33428> A_IWL<33427> A_IWL<33426> A_IWL<33425> A_IWL<33424> A_IWL<33423> A_IWL<33422> A_IWL<33421> A_IWL<33420> A_IWL<33419> A_IWL<33418> A_IWL<33417> A_IWL<33416> A_IWL<33415> A_IWL<33414> A_IWL<33413> A_IWL<33412> A_IWL<33411> A_IWL<33410> A_IWL<33409> A_IWL<33408> A_IWL<33407> A_IWL<33406> A_IWL<33405> A_IWL<33404> A_IWL<33403> A_IWL<33402> A_IWL<33401> A_IWL<33400> A_IWL<33399> A_IWL<33398> A_IWL<33397> A_IWL<33396> A_IWL<33395> A_IWL<33394> A_IWL<33393> A_IWL<33392> A_IWL<33391> A_IWL<33390> A_IWL<33389> A_IWL<33388> A_IWL<33387> A_IWL<33386> A_IWL<33385> A_IWL<33384> A_IWL<33383> A_IWL<33382> A_IWL<33381> A_IWL<33380> A_IWL<33379> A_IWL<33378> A_IWL<33377> A_IWL<33376> A_IWL<33375> A_IWL<33374> A_IWL<33373> A_IWL<33372> A_IWL<33371> A_IWL<33370> A_IWL<33369> A_IWL<33368> A_IWL<33367> A_IWL<33366> A_IWL<33365> A_IWL<33364> A_IWL<33363> A_IWL<33362> A_IWL<33361> A_IWL<33360> A_IWL<33359> A_IWL<33358> A_IWL<33357> A_IWL<33356> A_IWL<33355> A_IWL<33354> A_IWL<33353> A_IWL<33352> A_IWL<33351> A_IWL<33350> A_IWL<33349> A_IWL<33348> A_IWL<33347> A_IWL<33346> A_IWL<33345> A_IWL<33344> A_IWL<33343> A_IWL<33342> A_IWL<33341> A_IWL<33340> A_IWL<33339> A_IWL<33338> A_IWL<33337> A_IWL<33336> A_IWL<33335> A_IWL<33334> A_IWL<33333> A_IWL<33332> A_IWL<33331> A_IWL<33330> A_IWL<33329> A_IWL<33328> A_IWL<33327> A_IWL<33326> A_IWL<33325> A_IWL<33324> A_IWL<33323> A_IWL<33322> A_IWL<33321> A_IWL<33320> A_IWL<33319> A_IWL<33318> A_IWL<33317> A_IWL<33316> A_IWL<33315> A_IWL<33314> A_IWL<33313> A_IWL<33312> A_IWL<33311> A_IWL<33310> A_IWL<33309> A_IWL<33308> A_IWL<33307> A_IWL<33306> A_IWL<33305> A_IWL<33304> A_IWL<33303> A_IWL<33302> A_IWL<33301> A_IWL<33300> A_IWL<33299> A_IWL<33298> A_IWL<33297> A_IWL<33296> A_IWL<33295> A_IWL<33294> A_IWL<33293> A_IWL<33292> A_IWL<33291> A_IWL<33290> A_IWL<33289> A_IWL<33288> A_IWL<33287> A_IWL<33286> A_IWL<33285> A_IWL<33284> A_IWL<33283> A_IWL<33282> A_IWL<33281> A_IWL<33280> VDD_CORE VSS / RM_IHPSG13_8192x32_c4_1P_COLUMN_pcell_0 +XCOL<64> A_BLC<129> A_BLC<128> A_BLC_TOP<129> A_BLC_TOP<128> A_BLT<129> A_BLT<128> A_BLT_TOP<129> A_BLT_TOP<128> A_IWL<32767> A_IWL<32766> A_IWL<32765> A_IWL<32764> A_IWL<32763> A_IWL<32762> A_IWL<32761> A_IWL<32760> A_IWL<32759> A_IWL<32758> A_IWL<32757> A_IWL<32756> A_IWL<32755> A_IWL<32754> A_IWL<32753> A_IWL<32752> A_IWL<32751> A_IWL<32750> A_IWL<32749> A_IWL<32748> A_IWL<32747> A_IWL<32746> A_IWL<32745> A_IWL<32744> A_IWL<32743> A_IWL<32742> A_IWL<32741> A_IWL<32740> A_IWL<32739> A_IWL<32738> A_IWL<32737> A_IWL<32736> A_IWL<32735> A_IWL<32734> A_IWL<32733> A_IWL<32732> A_IWL<32731> A_IWL<32730> A_IWL<32729> A_IWL<32728> A_IWL<32727> A_IWL<32726> A_IWL<32725> A_IWL<32724> A_IWL<32723> A_IWL<32722> A_IWL<32721> A_IWL<32720> A_IWL<32719> A_IWL<32718> A_IWL<32717> A_IWL<32716> A_IWL<32715> A_IWL<32714> A_IWL<32713> A_IWL<32712> A_IWL<32711> A_IWL<32710> A_IWL<32709> A_IWL<32708> A_IWL<32707> A_IWL<32706> A_IWL<32705> A_IWL<32704> A_IWL<32703> A_IWL<32702> A_IWL<32701> A_IWL<32700> A_IWL<32699> A_IWL<32698> A_IWL<32697> A_IWL<32696> A_IWL<32695> A_IWL<32694> A_IWL<32693> A_IWL<32692> A_IWL<32691> A_IWL<32690> A_IWL<32689> A_IWL<32688> A_IWL<32687> A_IWL<32686> A_IWL<32685> A_IWL<32684> A_IWL<32683> A_IWL<32682> A_IWL<32681> A_IWL<32680> A_IWL<32679> A_IWL<32678> A_IWL<32677> A_IWL<32676> A_IWL<32675> A_IWL<32674> A_IWL<32673> A_IWL<32672> A_IWL<32671> A_IWL<32670> A_IWL<32669> A_IWL<32668> A_IWL<32667> A_IWL<32666> A_IWL<32665> A_IWL<32664> A_IWL<32663> A_IWL<32662> A_IWL<32661> A_IWL<32660> A_IWL<32659> A_IWL<32658> A_IWL<32657> A_IWL<32656> A_IWL<32655> A_IWL<32654> A_IWL<32653> A_IWL<32652> A_IWL<32651> A_IWL<32650> A_IWL<32649> A_IWL<32648> A_IWL<32647> A_IWL<32646> A_IWL<32645> A_IWL<32644> A_IWL<32643> A_IWL<32642> A_IWL<32641> A_IWL<32640> A_IWL<32639> A_IWL<32638> A_IWL<32637> A_IWL<32636> A_IWL<32635> A_IWL<32634> A_IWL<32633> A_IWL<32632> A_IWL<32631> A_IWL<32630> A_IWL<32629> A_IWL<32628> A_IWL<32627> A_IWL<32626> A_IWL<32625> A_IWL<32624> A_IWL<32623> A_IWL<32622> A_IWL<32621> A_IWL<32620> A_IWL<32619> A_IWL<32618> A_IWL<32617> A_IWL<32616> A_IWL<32615> A_IWL<32614> A_IWL<32613> A_IWL<32612> A_IWL<32611> A_IWL<32610> A_IWL<32609> A_IWL<32608> A_IWL<32607> A_IWL<32606> A_IWL<32605> A_IWL<32604> A_IWL<32603> A_IWL<32602> A_IWL<32601> A_IWL<32600> A_IWL<32599> A_IWL<32598> A_IWL<32597> A_IWL<32596> A_IWL<32595> A_IWL<32594> A_IWL<32593> A_IWL<32592> A_IWL<32591> A_IWL<32590> A_IWL<32589> A_IWL<32588> A_IWL<32587> A_IWL<32586> A_IWL<32585> A_IWL<32584> A_IWL<32583> A_IWL<32582> A_IWL<32581> A_IWL<32580> A_IWL<32579> A_IWL<32578> A_IWL<32577> A_IWL<32576> A_IWL<32575> A_IWL<32574> A_IWL<32573> A_IWL<32572> A_IWL<32571> A_IWL<32570> A_IWL<32569> A_IWL<32568> A_IWL<32567> A_IWL<32566> A_IWL<32565> A_IWL<32564> A_IWL<32563> A_IWL<32562> A_IWL<32561> A_IWL<32560> A_IWL<32559> A_IWL<32558> A_IWL<32557> A_IWL<32556> A_IWL<32555> A_IWL<32554> A_IWL<32553> A_IWL<32552> A_IWL<32551> A_IWL<32550> A_IWL<32549> A_IWL<32548> A_IWL<32547> A_IWL<32546> A_IWL<32545> A_IWL<32544> A_IWL<32543> A_IWL<32542> A_IWL<32541> A_IWL<32540> A_IWL<32539> A_IWL<32538> A_IWL<32537> A_IWL<32536> A_IWL<32535> A_IWL<32534> A_IWL<32533> A_IWL<32532> A_IWL<32531> A_IWL<32530> A_IWL<32529> A_IWL<32528> A_IWL<32527> A_IWL<32526> A_IWL<32525> A_IWL<32524> A_IWL<32523> A_IWL<32522> A_IWL<32521> A_IWL<32520> A_IWL<32519> A_IWL<32518> A_IWL<32517> A_IWL<32516> A_IWL<32515> A_IWL<32514> A_IWL<32513> A_IWL<32512> A_IWL<32511> A_IWL<32510> A_IWL<32509> A_IWL<32508> A_IWL<32507> A_IWL<32506> A_IWL<32505> A_IWL<32504> A_IWL<32503> A_IWL<32502> A_IWL<32501> A_IWL<32500> A_IWL<32499> A_IWL<32498> A_IWL<32497> A_IWL<32496> A_IWL<32495> A_IWL<32494> A_IWL<32493> A_IWL<32492> A_IWL<32491> A_IWL<32490> A_IWL<32489> A_IWL<32488> A_IWL<32487> A_IWL<32486> A_IWL<32485> A_IWL<32484> A_IWL<32483> A_IWL<32482> A_IWL<32481> A_IWL<32480> A_IWL<32479> A_IWL<32478> A_IWL<32477> A_IWL<32476> A_IWL<32475> A_IWL<32474> A_IWL<32473> A_IWL<32472> A_IWL<32471> A_IWL<32470> A_IWL<32469> A_IWL<32468> A_IWL<32467> A_IWL<32466> A_IWL<32465> A_IWL<32464> A_IWL<32463> A_IWL<32462> A_IWL<32461> A_IWL<32460> A_IWL<32459> A_IWL<32458> A_IWL<32457> A_IWL<32456> A_IWL<32455> A_IWL<32454> A_IWL<32453> A_IWL<32452> A_IWL<32451> A_IWL<32450> A_IWL<32449> A_IWL<32448> A_IWL<32447> A_IWL<32446> A_IWL<32445> A_IWL<32444> A_IWL<32443> A_IWL<32442> A_IWL<32441> A_IWL<32440> A_IWL<32439> A_IWL<32438> A_IWL<32437> A_IWL<32436> A_IWL<32435> A_IWL<32434> A_IWL<32433> A_IWL<32432> A_IWL<32431> A_IWL<32430> A_IWL<32429> A_IWL<32428> A_IWL<32427> A_IWL<32426> A_IWL<32425> A_IWL<32424> A_IWL<32423> A_IWL<32422> A_IWL<32421> A_IWL<32420> A_IWL<32419> A_IWL<32418> A_IWL<32417> A_IWL<32416> A_IWL<32415> A_IWL<32414> A_IWL<32413> A_IWL<32412> A_IWL<32411> A_IWL<32410> A_IWL<32409> A_IWL<32408> A_IWL<32407> A_IWL<32406> A_IWL<32405> A_IWL<32404> A_IWL<32403> A_IWL<32402> A_IWL<32401> A_IWL<32400> A_IWL<32399> A_IWL<32398> A_IWL<32397> A_IWL<32396> A_IWL<32395> A_IWL<32394> A_IWL<32393> A_IWL<32392> A_IWL<32391> A_IWL<32390> A_IWL<32389> A_IWL<32388> A_IWL<32387> A_IWL<32386> A_IWL<32385> A_IWL<32384> A_IWL<32383> A_IWL<32382> A_IWL<32381> A_IWL<32380> A_IWL<32379> A_IWL<32378> A_IWL<32377> A_IWL<32376> A_IWL<32375> A_IWL<32374> A_IWL<32373> A_IWL<32372> A_IWL<32371> A_IWL<32370> A_IWL<32369> A_IWL<32368> A_IWL<32367> A_IWL<32366> A_IWL<32365> A_IWL<32364> A_IWL<32363> A_IWL<32362> A_IWL<32361> A_IWL<32360> A_IWL<32359> A_IWL<32358> A_IWL<32357> A_IWL<32356> A_IWL<32355> A_IWL<32354> A_IWL<32353> A_IWL<32352> A_IWL<32351> A_IWL<32350> A_IWL<32349> A_IWL<32348> A_IWL<32347> A_IWL<32346> A_IWL<32345> A_IWL<32344> A_IWL<32343> A_IWL<32342> A_IWL<32341> A_IWL<32340> A_IWL<32339> A_IWL<32338> A_IWL<32337> A_IWL<32336> A_IWL<32335> A_IWL<32334> A_IWL<32333> A_IWL<32332> A_IWL<32331> A_IWL<32330> A_IWL<32329> A_IWL<32328> A_IWL<32327> A_IWL<32326> A_IWL<32325> A_IWL<32324> A_IWL<32323> A_IWL<32322> A_IWL<32321> A_IWL<32320> A_IWL<32319> A_IWL<32318> A_IWL<32317> A_IWL<32316> A_IWL<32315> A_IWL<32314> A_IWL<32313> A_IWL<32312> A_IWL<32311> A_IWL<32310> A_IWL<32309> A_IWL<32308> A_IWL<32307> A_IWL<32306> A_IWL<32305> A_IWL<32304> A_IWL<32303> A_IWL<32302> A_IWL<32301> A_IWL<32300> A_IWL<32299> A_IWL<32298> A_IWL<32297> A_IWL<32296> A_IWL<32295> A_IWL<32294> A_IWL<32293> A_IWL<32292> A_IWL<32291> A_IWL<32290> A_IWL<32289> A_IWL<32288> A_IWL<32287> A_IWL<32286> A_IWL<32285> A_IWL<32284> A_IWL<32283> A_IWL<32282> A_IWL<32281> A_IWL<32280> A_IWL<32279> A_IWL<32278> A_IWL<32277> A_IWL<32276> A_IWL<32275> A_IWL<32274> A_IWL<32273> A_IWL<32272> A_IWL<32271> A_IWL<32270> A_IWL<32269> A_IWL<32268> A_IWL<32267> A_IWL<32266> A_IWL<32265> A_IWL<32264> A_IWL<32263> A_IWL<32262> A_IWL<32261> A_IWL<32260> A_IWL<32259> A_IWL<32258> A_IWL<32257> A_IWL<32256> A_IWL<33279> A_IWL<33278> A_IWL<33277> A_IWL<33276> A_IWL<33275> A_IWL<33274> A_IWL<33273> A_IWL<33272> A_IWL<33271> A_IWL<33270> A_IWL<33269> A_IWL<33268> A_IWL<33267> A_IWL<33266> A_IWL<33265> A_IWL<33264> A_IWL<33263> A_IWL<33262> A_IWL<33261> A_IWL<33260> A_IWL<33259> A_IWL<33258> A_IWL<33257> A_IWL<33256> A_IWL<33255> A_IWL<33254> A_IWL<33253> A_IWL<33252> A_IWL<33251> A_IWL<33250> A_IWL<33249> A_IWL<33248> A_IWL<33247> A_IWL<33246> A_IWL<33245> A_IWL<33244> A_IWL<33243> A_IWL<33242> A_IWL<33241> A_IWL<33240> A_IWL<33239> A_IWL<33238> A_IWL<33237> A_IWL<33236> A_IWL<33235> A_IWL<33234> A_IWL<33233> A_IWL<33232> A_IWL<33231> A_IWL<33230> A_IWL<33229> A_IWL<33228> A_IWL<33227> A_IWL<33226> A_IWL<33225> A_IWL<33224> A_IWL<33223> A_IWL<33222> A_IWL<33221> A_IWL<33220> A_IWL<33219> A_IWL<33218> A_IWL<33217> A_IWL<33216> A_IWL<33215> A_IWL<33214> A_IWL<33213> A_IWL<33212> A_IWL<33211> A_IWL<33210> A_IWL<33209> A_IWL<33208> A_IWL<33207> A_IWL<33206> A_IWL<33205> A_IWL<33204> A_IWL<33203> A_IWL<33202> A_IWL<33201> A_IWL<33200> A_IWL<33199> A_IWL<33198> A_IWL<33197> A_IWL<33196> A_IWL<33195> A_IWL<33194> A_IWL<33193> A_IWL<33192> A_IWL<33191> A_IWL<33190> A_IWL<33189> A_IWL<33188> A_IWL<33187> A_IWL<33186> A_IWL<33185> A_IWL<33184> A_IWL<33183> A_IWL<33182> A_IWL<33181> A_IWL<33180> A_IWL<33179> A_IWL<33178> A_IWL<33177> A_IWL<33176> A_IWL<33175> A_IWL<33174> A_IWL<33173> A_IWL<33172> A_IWL<33171> A_IWL<33170> A_IWL<33169> A_IWL<33168> A_IWL<33167> A_IWL<33166> A_IWL<33165> A_IWL<33164> A_IWL<33163> A_IWL<33162> A_IWL<33161> A_IWL<33160> A_IWL<33159> A_IWL<33158> A_IWL<33157> A_IWL<33156> A_IWL<33155> A_IWL<33154> A_IWL<33153> A_IWL<33152> A_IWL<33151> A_IWL<33150> A_IWL<33149> A_IWL<33148> A_IWL<33147> A_IWL<33146> A_IWL<33145> A_IWL<33144> A_IWL<33143> A_IWL<33142> A_IWL<33141> A_IWL<33140> A_IWL<33139> A_IWL<33138> A_IWL<33137> A_IWL<33136> A_IWL<33135> A_IWL<33134> A_IWL<33133> A_IWL<33132> A_IWL<33131> A_IWL<33130> A_IWL<33129> A_IWL<33128> A_IWL<33127> A_IWL<33126> A_IWL<33125> A_IWL<33124> A_IWL<33123> A_IWL<33122> A_IWL<33121> A_IWL<33120> A_IWL<33119> A_IWL<33118> A_IWL<33117> A_IWL<33116> A_IWL<33115> A_IWL<33114> A_IWL<33113> A_IWL<33112> A_IWL<33111> A_IWL<33110> A_IWL<33109> A_IWL<33108> A_IWL<33107> A_IWL<33106> A_IWL<33105> A_IWL<33104> A_IWL<33103> A_IWL<33102> A_IWL<33101> A_IWL<33100> A_IWL<33099> A_IWL<33098> A_IWL<33097> A_IWL<33096> A_IWL<33095> A_IWL<33094> A_IWL<33093> A_IWL<33092> A_IWL<33091> A_IWL<33090> A_IWL<33089> A_IWL<33088> A_IWL<33087> A_IWL<33086> A_IWL<33085> A_IWL<33084> A_IWL<33083> A_IWL<33082> A_IWL<33081> A_IWL<33080> A_IWL<33079> A_IWL<33078> A_IWL<33077> A_IWL<33076> A_IWL<33075> A_IWL<33074> A_IWL<33073> A_IWL<33072> A_IWL<33071> A_IWL<33070> A_IWL<33069> A_IWL<33068> A_IWL<33067> A_IWL<33066> A_IWL<33065> A_IWL<33064> A_IWL<33063> A_IWL<33062> A_IWL<33061> A_IWL<33060> A_IWL<33059> A_IWL<33058> A_IWL<33057> A_IWL<33056> A_IWL<33055> A_IWL<33054> A_IWL<33053> A_IWL<33052> A_IWL<33051> A_IWL<33050> A_IWL<33049> A_IWL<33048> A_IWL<33047> A_IWL<33046> A_IWL<33045> A_IWL<33044> A_IWL<33043> A_IWL<33042> A_IWL<33041> A_IWL<33040> A_IWL<33039> A_IWL<33038> A_IWL<33037> A_IWL<33036> A_IWL<33035> A_IWL<33034> A_IWL<33033> A_IWL<33032> A_IWL<33031> A_IWL<33030> A_IWL<33029> A_IWL<33028> A_IWL<33027> A_IWL<33026> A_IWL<33025> A_IWL<33024> A_IWL<33023> A_IWL<33022> A_IWL<33021> A_IWL<33020> A_IWL<33019> A_IWL<33018> A_IWL<33017> A_IWL<33016> A_IWL<33015> A_IWL<33014> A_IWL<33013> A_IWL<33012> A_IWL<33011> A_IWL<33010> A_IWL<33009> A_IWL<33008> A_IWL<33007> A_IWL<33006> A_IWL<33005> A_IWL<33004> A_IWL<33003> A_IWL<33002> A_IWL<33001> A_IWL<33000> A_IWL<32999> A_IWL<32998> A_IWL<32997> A_IWL<32996> A_IWL<32995> A_IWL<32994> A_IWL<32993> A_IWL<32992> A_IWL<32991> A_IWL<32990> A_IWL<32989> A_IWL<32988> A_IWL<32987> A_IWL<32986> A_IWL<32985> A_IWL<32984> A_IWL<32983> A_IWL<32982> A_IWL<32981> A_IWL<32980> A_IWL<32979> A_IWL<32978> A_IWL<32977> A_IWL<32976> A_IWL<32975> A_IWL<32974> A_IWL<32973> A_IWL<32972> A_IWL<32971> A_IWL<32970> A_IWL<32969> A_IWL<32968> A_IWL<32967> A_IWL<32966> A_IWL<32965> A_IWL<32964> A_IWL<32963> A_IWL<32962> A_IWL<32961> A_IWL<32960> A_IWL<32959> A_IWL<32958> A_IWL<32957> A_IWL<32956> A_IWL<32955> A_IWL<32954> A_IWL<32953> A_IWL<32952> A_IWL<32951> A_IWL<32950> A_IWL<32949> A_IWL<32948> A_IWL<32947> A_IWL<32946> A_IWL<32945> A_IWL<32944> A_IWL<32943> A_IWL<32942> A_IWL<32941> A_IWL<32940> A_IWL<32939> A_IWL<32938> A_IWL<32937> A_IWL<32936> A_IWL<32935> A_IWL<32934> A_IWL<32933> A_IWL<32932> A_IWL<32931> A_IWL<32930> A_IWL<32929> A_IWL<32928> A_IWL<32927> A_IWL<32926> A_IWL<32925> A_IWL<32924> A_IWL<32923> A_IWL<32922> A_IWL<32921> A_IWL<32920> A_IWL<32919> A_IWL<32918> A_IWL<32917> A_IWL<32916> A_IWL<32915> A_IWL<32914> A_IWL<32913> A_IWL<32912> A_IWL<32911> A_IWL<32910> A_IWL<32909> A_IWL<32908> A_IWL<32907> A_IWL<32906> A_IWL<32905> A_IWL<32904> A_IWL<32903> A_IWL<32902> A_IWL<32901> A_IWL<32900> A_IWL<32899> A_IWL<32898> A_IWL<32897> A_IWL<32896> A_IWL<32895> A_IWL<32894> A_IWL<32893> A_IWL<32892> A_IWL<32891> A_IWL<32890> A_IWL<32889> A_IWL<32888> A_IWL<32887> A_IWL<32886> A_IWL<32885> A_IWL<32884> A_IWL<32883> A_IWL<32882> A_IWL<32881> A_IWL<32880> A_IWL<32879> A_IWL<32878> A_IWL<32877> A_IWL<32876> A_IWL<32875> A_IWL<32874> A_IWL<32873> A_IWL<32872> A_IWL<32871> A_IWL<32870> A_IWL<32869> A_IWL<32868> A_IWL<32867> A_IWL<32866> A_IWL<32865> A_IWL<32864> A_IWL<32863> A_IWL<32862> A_IWL<32861> A_IWL<32860> A_IWL<32859> A_IWL<32858> A_IWL<32857> A_IWL<32856> A_IWL<32855> A_IWL<32854> A_IWL<32853> A_IWL<32852> A_IWL<32851> A_IWL<32850> A_IWL<32849> A_IWL<32848> A_IWL<32847> A_IWL<32846> A_IWL<32845> A_IWL<32844> A_IWL<32843> A_IWL<32842> A_IWL<32841> A_IWL<32840> A_IWL<32839> A_IWL<32838> A_IWL<32837> A_IWL<32836> A_IWL<32835> A_IWL<32834> A_IWL<32833> A_IWL<32832> A_IWL<32831> A_IWL<32830> A_IWL<32829> A_IWL<32828> A_IWL<32827> A_IWL<32826> A_IWL<32825> A_IWL<32824> A_IWL<32823> A_IWL<32822> A_IWL<32821> A_IWL<32820> A_IWL<32819> A_IWL<32818> A_IWL<32817> A_IWL<32816> A_IWL<32815> A_IWL<32814> A_IWL<32813> A_IWL<32812> A_IWL<32811> A_IWL<32810> A_IWL<32809> A_IWL<32808> A_IWL<32807> A_IWL<32806> A_IWL<32805> A_IWL<32804> A_IWL<32803> A_IWL<32802> A_IWL<32801> A_IWL<32800> A_IWL<32799> A_IWL<32798> A_IWL<32797> A_IWL<32796> A_IWL<32795> A_IWL<32794> A_IWL<32793> A_IWL<32792> A_IWL<32791> A_IWL<32790> A_IWL<32789> A_IWL<32788> A_IWL<32787> A_IWL<32786> A_IWL<32785> A_IWL<32784> A_IWL<32783> A_IWL<32782> A_IWL<32781> A_IWL<32780> A_IWL<32779> A_IWL<32778> A_IWL<32777> A_IWL<32776> A_IWL<32775> A_IWL<32774> A_IWL<32773> A_IWL<32772> A_IWL<32771> A_IWL<32770> A_IWL<32769> A_IWL<32768> VDD_CORE VSS / RM_IHPSG13_8192x32_c4_1P_COLUMN_pcell_0 +XCOL<63> A_BLC<127> A_BLC<126> A_BLC_TOP<127> A_BLC_TOP<126> A_BLT<127> A_BLT<126> A_BLT_TOP<127> A_BLT_TOP<126> A_IWL<32255> A_IWL<32254> A_IWL<32253> A_IWL<32252> A_IWL<32251> A_IWL<32250> A_IWL<32249> A_IWL<32248> A_IWL<32247> A_IWL<32246> A_IWL<32245> A_IWL<32244> A_IWL<32243> A_IWL<32242> A_IWL<32241> A_IWL<32240> A_IWL<32239> A_IWL<32238> A_IWL<32237> A_IWL<32236> A_IWL<32235> A_IWL<32234> A_IWL<32233> A_IWL<32232> A_IWL<32231> A_IWL<32230> A_IWL<32229> A_IWL<32228> A_IWL<32227> A_IWL<32226> A_IWL<32225> A_IWL<32224> A_IWL<32223> A_IWL<32222> A_IWL<32221> A_IWL<32220> A_IWL<32219> A_IWL<32218> A_IWL<32217> A_IWL<32216> A_IWL<32215> A_IWL<32214> A_IWL<32213> A_IWL<32212> A_IWL<32211> A_IWL<32210> A_IWL<32209> A_IWL<32208> A_IWL<32207> A_IWL<32206> A_IWL<32205> A_IWL<32204> A_IWL<32203> A_IWL<32202> A_IWL<32201> A_IWL<32200> A_IWL<32199> A_IWL<32198> A_IWL<32197> A_IWL<32196> A_IWL<32195> A_IWL<32194> A_IWL<32193> A_IWL<32192> A_IWL<32191> A_IWL<32190> A_IWL<32189> A_IWL<32188> A_IWL<32187> A_IWL<32186> A_IWL<32185> A_IWL<32184> A_IWL<32183> A_IWL<32182> A_IWL<32181> A_IWL<32180> A_IWL<32179> A_IWL<32178> A_IWL<32177> A_IWL<32176> A_IWL<32175> A_IWL<32174> A_IWL<32173> A_IWL<32172> A_IWL<32171> A_IWL<32170> A_IWL<32169> A_IWL<32168> A_IWL<32167> A_IWL<32166> A_IWL<32165> A_IWL<32164> A_IWL<32163> A_IWL<32162> A_IWL<32161> A_IWL<32160> A_IWL<32159> A_IWL<32158> A_IWL<32157> A_IWL<32156> A_IWL<32155> A_IWL<32154> A_IWL<32153> A_IWL<32152> A_IWL<32151> A_IWL<32150> A_IWL<32149> A_IWL<32148> A_IWL<32147> A_IWL<32146> A_IWL<32145> A_IWL<32144> A_IWL<32143> A_IWL<32142> A_IWL<32141> A_IWL<32140> A_IWL<32139> A_IWL<32138> A_IWL<32137> A_IWL<32136> A_IWL<32135> A_IWL<32134> A_IWL<32133> A_IWL<32132> A_IWL<32131> A_IWL<32130> A_IWL<32129> A_IWL<32128> A_IWL<32127> A_IWL<32126> A_IWL<32125> A_IWL<32124> A_IWL<32123> A_IWL<32122> A_IWL<32121> A_IWL<32120> A_IWL<32119> A_IWL<32118> A_IWL<32117> A_IWL<32116> A_IWL<32115> A_IWL<32114> A_IWL<32113> A_IWL<32112> A_IWL<32111> A_IWL<32110> A_IWL<32109> A_IWL<32108> A_IWL<32107> A_IWL<32106> A_IWL<32105> A_IWL<32104> A_IWL<32103> A_IWL<32102> A_IWL<32101> A_IWL<32100> A_IWL<32099> A_IWL<32098> A_IWL<32097> A_IWL<32096> A_IWL<32095> A_IWL<32094> A_IWL<32093> A_IWL<32092> A_IWL<32091> A_IWL<32090> A_IWL<32089> A_IWL<32088> A_IWL<32087> A_IWL<32086> A_IWL<32085> A_IWL<32084> A_IWL<32083> A_IWL<32082> A_IWL<32081> A_IWL<32080> A_IWL<32079> A_IWL<32078> A_IWL<32077> A_IWL<32076> A_IWL<32075> A_IWL<32074> A_IWL<32073> A_IWL<32072> A_IWL<32071> A_IWL<32070> A_IWL<32069> A_IWL<32068> A_IWL<32067> A_IWL<32066> A_IWL<32065> A_IWL<32064> A_IWL<32063> A_IWL<32062> A_IWL<32061> A_IWL<32060> A_IWL<32059> A_IWL<32058> A_IWL<32057> A_IWL<32056> A_IWL<32055> A_IWL<32054> A_IWL<32053> A_IWL<32052> A_IWL<32051> A_IWL<32050> A_IWL<32049> A_IWL<32048> A_IWL<32047> A_IWL<32046> A_IWL<32045> A_IWL<32044> A_IWL<32043> A_IWL<32042> A_IWL<32041> A_IWL<32040> A_IWL<32039> A_IWL<32038> A_IWL<32037> A_IWL<32036> A_IWL<32035> A_IWL<32034> A_IWL<32033> A_IWL<32032> A_IWL<32031> A_IWL<32030> A_IWL<32029> A_IWL<32028> A_IWL<32027> A_IWL<32026> A_IWL<32025> A_IWL<32024> A_IWL<32023> A_IWL<32022> A_IWL<32021> A_IWL<32020> A_IWL<32019> A_IWL<32018> A_IWL<32017> A_IWL<32016> A_IWL<32015> A_IWL<32014> A_IWL<32013> A_IWL<32012> A_IWL<32011> A_IWL<32010> A_IWL<32009> A_IWL<32008> A_IWL<32007> A_IWL<32006> A_IWL<32005> A_IWL<32004> A_IWL<32003> A_IWL<32002> A_IWL<32001> A_IWL<32000> A_IWL<31999> A_IWL<31998> A_IWL<31997> A_IWL<31996> A_IWL<31995> A_IWL<31994> A_IWL<31993> A_IWL<31992> A_IWL<31991> A_IWL<31990> A_IWL<31989> A_IWL<31988> A_IWL<31987> A_IWL<31986> A_IWL<31985> A_IWL<31984> A_IWL<31983> A_IWL<31982> A_IWL<31981> A_IWL<31980> A_IWL<31979> A_IWL<31978> A_IWL<31977> A_IWL<31976> A_IWL<31975> A_IWL<31974> A_IWL<31973> A_IWL<31972> A_IWL<31971> A_IWL<31970> A_IWL<31969> A_IWL<31968> A_IWL<31967> A_IWL<31966> A_IWL<31965> A_IWL<31964> A_IWL<31963> A_IWL<31962> A_IWL<31961> A_IWL<31960> A_IWL<31959> A_IWL<31958> A_IWL<31957> A_IWL<31956> A_IWL<31955> A_IWL<31954> A_IWL<31953> A_IWL<31952> A_IWL<31951> A_IWL<31950> A_IWL<31949> A_IWL<31948> A_IWL<31947> A_IWL<31946> A_IWL<31945> A_IWL<31944> A_IWL<31943> A_IWL<31942> A_IWL<31941> A_IWL<31940> A_IWL<31939> A_IWL<31938> A_IWL<31937> A_IWL<31936> A_IWL<31935> A_IWL<31934> A_IWL<31933> A_IWL<31932> A_IWL<31931> A_IWL<31930> A_IWL<31929> A_IWL<31928> A_IWL<31927> A_IWL<31926> A_IWL<31925> A_IWL<31924> A_IWL<31923> A_IWL<31922> A_IWL<31921> A_IWL<31920> A_IWL<31919> A_IWL<31918> A_IWL<31917> A_IWL<31916> A_IWL<31915> A_IWL<31914> A_IWL<31913> A_IWL<31912> A_IWL<31911> A_IWL<31910> A_IWL<31909> A_IWL<31908> A_IWL<31907> A_IWL<31906> A_IWL<31905> A_IWL<31904> A_IWL<31903> A_IWL<31902> A_IWL<31901> A_IWL<31900> A_IWL<31899> A_IWL<31898> A_IWL<31897> A_IWL<31896> A_IWL<31895> A_IWL<31894> A_IWL<31893> A_IWL<31892> A_IWL<31891> A_IWL<31890> A_IWL<31889> A_IWL<31888> A_IWL<31887> A_IWL<31886> A_IWL<31885> A_IWL<31884> A_IWL<31883> A_IWL<31882> A_IWL<31881> A_IWL<31880> A_IWL<31879> A_IWL<31878> A_IWL<31877> A_IWL<31876> A_IWL<31875> A_IWL<31874> A_IWL<31873> A_IWL<31872> A_IWL<31871> A_IWL<31870> A_IWL<31869> A_IWL<31868> A_IWL<31867> A_IWL<31866> A_IWL<31865> A_IWL<31864> A_IWL<31863> A_IWL<31862> A_IWL<31861> A_IWL<31860> A_IWL<31859> A_IWL<31858> A_IWL<31857> A_IWL<31856> A_IWL<31855> A_IWL<31854> A_IWL<31853> A_IWL<31852> A_IWL<31851> A_IWL<31850> A_IWL<31849> A_IWL<31848> A_IWL<31847> A_IWL<31846> A_IWL<31845> A_IWL<31844> A_IWL<31843> A_IWL<31842> A_IWL<31841> A_IWL<31840> A_IWL<31839> A_IWL<31838> A_IWL<31837> A_IWL<31836> A_IWL<31835> A_IWL<31834> A_IWL<31833> A_IWL<31832> A_IWL<31831> A_IWL<31830> A_IWL<31829> A_IWL<31828> A_IWL<31827> A_IWL<31826> A_IWL<31825> A_IWL<31824> A_IWL<31823> A_IWL<31822> A_IWL<31821> A_IWL<31820> A_IWL<31819> A_IWL<31818> A_IWL<31817> A_IWL<31816> A_IWL<31815> A_IWL<31814> A_IWL<31813> A_IWL<31812> A_IWL<31811> A_IWL<31810> A_IWL<31809> A_IWL<31808> A_IWL<31807> A_IWL<31806> A_IWL<31805> A_IWL<31804> A_IWL<31803> A_IWL<31802> A_IWL<31801> A_IWL<31800> A_IWL<31799> A_IWL<31798> A_IWL<31797> A_IWL<31796> A_IWL<31795> A_IWL<31794> A_IWL<31793> A_IWL<31792> A_IWL<31791> A_IWL<31790> A_IWL<31789> A_IWL<31788> A_IWL<31787> A_IWL<31786> A_IWL<31785> A_IWL<31784> A_IWL<31783> A_IWL<31782> A_IWL<31781> A_IWL<31780> A_IWL<31779> A_IWL<31778> A_IWL<31777> A_IWL<31776> A_IWL<31775> A_IWL<31774> A_IWL<31773> A_IWL<31772> A_IWL<31771> A_IWL<31770> A_IWL<31769> A_IWL<31768> A_IWL<31767> A_IWL<31766> A_IWL<31765> A_IWL<31764> A_IWL<31763> A_IWL<31762> A_IWL<31761> A_IWL<31760> A_IWL<31759> A_IWL<31758> A_IWL<31757> A_IWL<31756> A_IWL<31755> A_IWL<31754> A_IWL<31753> A_IWL<31752> A_IWL<31751> A_IWL<31750> A_IWL<31749> A_IWL<31748> A_IWL<31747> A_IWL<31746> A_IWL<31745> A_IWL<31744> A_IWL<32767> A_IWL<32766> A_IWL<32765> A_IWL<32764> A_IWL<32763> A_IWL<32762> A_IWL<32761> A_IWL<32760> A_IWL<32759> A_IWL<32758> A_IWL<32757> A_IWL<32756> A_IWL<32755> A_IWL<32754> A_IWL<32753> A_IWL<32752> A_IWL<32751> A_IWL<32750> A_IWL<32749> A_IWL<32748> A_IWL<32747> A_IWL<32746> A_IWL<32745> A_IWL<32744> A_IWL<32743> A_IWL<32742> A_IWL<32741> A_IWL<32740> A_IWL<32739> A_IWL<32738> A_IWL<32737> A_IWL<32736> A_IWL<32735> A_IWL<32734> A_IWL<32733> A_IWL<32732> A_IWL<32731> A_IWL<32730> A_IWL<32729> A_IWL<32728> A_IWL<32727> A_IWL<32726> A_IWL<32725> A_IWL<32724> A_IWL<32723> A_IWL<32722> A_IWL<32721> A_IWL<32720> A_IWL<32719> A_IWL<32718> A_IWL<32717> A_IWL<32716> A_IWL<32715> A_IWL<32714> A_IWL<32713> A_IWL<32712> A_IWL<32711> A_IWL<32710> A_IWL<32709> A_IWL<32708> A_IWL<32707> A_IWL<32706> A_IWL<32705> A_IWL<32704> A_IWL<32703> A_IWL<32702> A_IWL<32701> A_IWL<32700> A_IWL<32699> A_IWL<32698> A_IWL<32697> A_IWL<32696> A_IWL<32695> A_IWL<32694> A_IWL<32693> A_IWL<32692> A_IWL<32691> A_IWL<32690> A_IWL<32689> A_IWL<32688> A_IWL<32687> A_IWL<32686> A_IWL<32685> A_IWL<32684> A_IWL<32683> A_IWL<32682> A_IWL<32681> A_IWL<32680> A_IWL<32679> A_IWL<32678> A_IWL<32677> A_IWL<32676> A_IWL<32675> A_IWL<32674> A_IWL<32673> A_IWL<32672> A_IWL<32671> A_IWL<32670> A_IWL<32669> A_IWL<32668> A_IWL<32667> A_IWL<32666> A_IWL<32665> A_IWL<32664> A_IWL<32663> A_IWL<32662> A_IWL<32661> A_IWL<32660> A_IWL<32659> A_IWL<32658> A_IWL<32657> A_IWL<32656> A_IWL<32655> A_IWL<32654> A_IWL<32653> A_IWL<32652> A_IWL<32651> A_IWL<32650> A_IWL<32649> A_IWL<32648> A_IWL<32647> A_IWL<32646> A_IWL<32645> A_IWL<32644> A_IWL<32643> A_IWL<32642> A_IWL<32641> A_IWL<32640> A_IWL<32639> A_IWL<32638> A_IWL<32637> A_IWL<32636> A_IWL<32635> A_IWL<32634> A_IWL<32633> A_IWL<32632> A_IWL<32631> A_IWL<32630> A_IWL<32629> A_IWL<32628> A_IWL<32627> A_IWL<32626> A_IWL<32625> A_IWL<32624> A_IWL<32623> A_IWL<32622> A_IWL<32621> A_IWL<32620> A_IWL<32619> A_IWL<32618> A_IWL<32617> A_IWL<32616> A_IWL<32615> A_IWL<32614> A_IWL<32613> A_IWL<32612> A_IWL<32611> A_IWL<32610> A_IWL<32609> A_IWL<32608> A_IWL<32607> A_IWL<32606> A_IWL<32605> A_IWL<32604> A_IWL<32603> A_IWL<32602> A_IWL<32601> A_IWL<32600> A_IWL<32599> A_IWL<32598> A_IWL<32597> A_IWL<32596> A_IWL<32595> A_IWL<32594> A_IWL<32593> A_IWL<32592> A_IWL<32591> A_IWL<32590> A_IWL<32589> A_IWL<32588> A_IWL<32587> A_IWL<32586> A_IWL<32585> A_IWL<32584> A_IWL<32583> A_IWL<32582> A_IWL<32581> A_IWL<32580> A_IWL<32579> A_IWL<32578> A_IWL<32577> A_IWL<32576> A_IWL<32575> A_IWL<32574> A_IWL<32573> A_IWL<32572> A_IWL<32571> A_IWL<32570> A_IWL<32569> A_IWL<32568> A_IWL<32567> A_IWL<32566> A_IWL<32565> A_IWL<32564> A_IWL<32563> A_IWL<32562> A_IWL<32561> A_IWL<32560> A_IWL<32559> A_IWL<32558> A_IWL<32557> A_IWL<32556> A_IWL<32555> A_IWL<32554> A_IWL<32553> A_IWL<32552> A_IWL<32551> A_IWL<32550> A_IWL<32549> A_IWL<32548> A_IWL<32547> A_IWL<32546> A_IWL<32545> A_IWL<32544> A_IWL<32543> A_IWL<32542> A_IWL<32541> A_IWL<32540> A_IWL<32539> A_IWL<32538> A_IWL<32537> A_IWL<32536> A_IWL<32535> A_IWL<32534> A_IWL<32533> A_IWL<32532> A_IWL<32531> A_IWL<32530> A_IWL<32529> A_IWL<32528> A_IWL<32527> A_IWL<32526> A_IWL<32525> A_IWL<32524> A_IWL<32523> A_IWL<32522> A_IWL<32521> A_IWL<32520> A_IWL<32519> A_IWL<32518> A_IWL<32517> A_IWL<32516> A_IWL<32515> A_IWL<32514> A_IWL<32513> A_IWL<32512> A_IWL<32511> A_IWL<32510> A_IWL<32509> A_IWL<32508> A_IWL<32507> A_IWL<32506> A_IWL<32505> A_IWL<32504> A_IWL<32503> A_IWL<32502> A_IWL<32501> A_IWL<32500> A_IWL<32499> A_IWL<32498> A_IWL<32497> A_IWL<32496> A_IWL<32495> A_IWL<32494> A_IWL<32493> A_IWL<32492> A_IWL<32491> A_IWL<32490> A_IWL<32489> A_IWL<32488> A_IWL<32487> A_IWL<32486> A_IWL<32485> A_IWL<32484> A_IWL<32483> A_IWL<32482> A_IWL<32481> A_IWL<32480> A_IWL<32479> A_IWL<32478> A_IWL<32477> A_IWL<32476> A_IWL<32475> A_IWL<32474> A_IWL<32473> A_IWL<32472> A_IWL<32471> A_IWL<32470> A_IWL<32469> A_IWL<32468> A_IWL<32467> A_IWL<32466> A_IWL<32465> A_IWL<32464> A_IWL<32463> A_IWL<32462> A_IWL<32461> A_IWL<32460> A_IWL<32459> A_IWL<32458> A_IWL<32457> A_IWL<32456> A_IWL<32455> A_IWL<32454> A_IWL<32453> A_IWL<32452> A_IWL<32451> A_IWL<32450> A_IWL<32449> A_IWL<32448> A_IWL<32447> A_IWL<32446> A_IWL<32445> A_IWL<32444> A_IWL<32443> A_IWL<32442> A_IWL<32441> A_IWL<32440> A_IWL<32439> A_IWL<32438> A_IWL<32437> A_IWL<32436> A_IWL<32435> A_IWL<32434> A_IWL<32433> A_IWL<32432> A_IWL<32431> A_IWL<32430> A_IWL<32429> A_IWL<32428> A_IWL<32427> A_IWL<32426> A_IWL<32425> A_IWL<32424> A_IWL<32423> A_IWL<32422> A_IWL<32421> A_IWL<32420> A_IWL<32419> A_IWL<32418> A_IWL<32417> A_IWL<32416> A_IWL<32415> A_IWL<32414> A_IWL<32413> A_IWL<32412> A_IWL<32411> A_IWL<32410> A_IWL<32409> A_IWL<32408> A_IWL<32407> A_IWL<32406> A_IWL<32405> A_IWL<32404> A_IWL<32403> A_IWL<32402> A_IWL<32401> A_IWL<32400> A_IWL<32399> A_IWL<32398> A_IWL<32397> A_IWL<32396> A_IWL<32395> A_IWL<32394> A_IWL<32393> A_IWL<32392> A_IWL<32391> A_IWL<32390> A_IWL<32389> A_IWL<32388> A_IWL<32387> A_IWL<32386> A_IWL<32385> A_IWL<32384> A_IWL<32383> A_IWL<32382> A_IWL<32381> A_IWL<32380> A_IWL<32379> A_IWL<32378> A_IWL<32377> A_IWL<32376> A_IWL<32375> A_IWL<32374> A_IWL<32373> A_IWL<32372> A_IWL<32371> A_IWL<32370> A_IWL<32369> A_IWL<32368> A_IWL<32367> A_IWL<32366> A_IWL<32365> A_IWL<32364> A_IWL<32363> A_IWL<32362> A_IWL<32361> A_IWL<32360> A_IWL<32359> A_IWL<32358> A_IWL<32357> A_IWL<32356> A_IWL<32355> A_IWL<32354> A_IWL<32353> A_IWL<32352> A_IWL<32351> A_IWL<32350> A_IWL<32349> A_IWL<32348> A_IWL<32347> A_IWL<32346> A_IWL<32345> A_IWL<32344> A_IWL<32343> A_IWL<32342> A_IWL<32341> A_IWL<32340> A_IWL<32339> A_IWL<32338> A_IWL<32337> A_IWL<32336> A_IWL<32335> A_IWL<32334> A_IWL<32333> A_IWL<32332> A_IWL<32331> A_IWL<32330> A_IWL<32329> A_IWL<32328> A_IWL<32327> A_IWL<32326> A_IWL<32325> A_IWL<32324> A_IWL<32323> A_IWL<32322> A_IWL<32321> A_IWL<32320> A_IWL<32319> A_IWL<32318> A_IWL<32317> A_IWL<32316> A_IWL<32315> A_IWL<32314> A_IWL<32313> A_IWL<32312> A_IWL<32311> A_IWL<32310> A_IWL<32309> A_IWL<32308> A_IWL<32307> A_IWL<32306> A_IWL<32305> A_IWL<32304> A_IWL<32303> A_IWL<32302> A_IWL<32301> A_IWL<32300> A_IWL<32299> A_IWL<32298> A_IWL<32297> A_IWL<32296> A_IWL<32295> A_IWL<32294> A_IWL<32293> A_IWL<32292> A_IWL<32291> A_IWL<32290> A_IWL<32289> A_IWL<32288> A_IWL<32287> A_IWL<32286> A_IWL<32285> A_IWL<32284> A_IWL<32283> A_IWL<32282> A_IWL<32281> A_IWL<32280> A_IWL<32279> A_IWL<32278> A_IWL<32277> A_IWL<32276> A_IWL<32275> A_IWL<32274> A_IWL<32273> A_IWL<32272> A_IWL<32271> A_IWL<32270> A_IWL<32269> A_IWL<32268> A_IWL<32267> A_IWL<32266> A_IWL<32265> A_IWL<32264> A_IWL<32263> A_IWL<32262> A_IWL<32261> A_IWL<32260> A_IWL<32259> A_IWL<32258> A_IWL<32257> A_IWL<32256> VDD_CORE VSS / RM_IHPSG13_8192x32_c4_1P_COLUMN_pcell_0 +XCOL<62> A_BLC<125> A_BLC<124> A_BLC_TOP<125> A_BLC_TOP<124> A_BLT<125> A_BLT<124> A_BLT_TOP<125> A_BLT_TOP<124> A_IWL<31743> A_IWL<31742> A_IWL<31741> A_IWL<31740> A_IWL<31739> A_IWL<31738> A_IWL<31737> A_IWL<31736> A_IWL<31735> A_IWL<31734> A_IWL<31733> A_IWL<31732> A_IWL<31731> A_IWL<31730> A_IWL<31729> A_IWL<31728> A_IWL<31727> A_IWL<31726> A_IWL<31725> A_IWL<31724> A_IWL<31723> A_IWL<31722> A_IWL<31721> A_IWL<31720> A_IWL<31719> A_IWL<31718> A_IWL<31717> A_IWL<31716> A_IWL<31715> A_IWL<31714> A_IWL<31713> A_IWL<31712> A_IWL<31711> A_IWL<31710> A_IWL<31709> A_IWL<31708> A_IWL<31707> A_IWL<31706> A_IWL<31705> A_IWL<31704> A_IWL<31703> A_IWL<31702> A_IWL<31701> A_IWL<31700> A_IWL<31699> A_IWL<31698> A_IWL<31697> A_IWL<31696> A_IWL<31695> A_IWL<31694> A_IWL<31693> A_IWL<31692> A_IWL<31691> A_IWL<31690> A_IWL<31689> A_IWL<31688> A_IWL<31687> A_IWL<31686> A_IWL<31685> A_IWL<31684> A_IWL<31683> A_IWL<31682> A_IWL<31681> A_IWL<31680> A_IWL<31679> A_IWL<31678> A_IWL<31677> A_IWL<31676> A_IWL<31675> A_IWL<31674> A_IWL<31673> A_IWL<31672> A_IWL<31671> A_IWL<31670> A_IWL<31669> A_IWL<31668> A_IWL<31667> A_IWL<31666> A_IWL<31665> A_IWL<31664> A_IWL<31663> A_IWL<31662> A_IWL<31661> A_IWL<31660> A_IWL<31659> A_IWL<31658> A_IWL<31657> A_IWL<31656> A_IWL<31655> A_IWL<31654> A_IWL<31653> A_IWL<31652> A_IWL<31651> A_IWL<31650> A_IWL<31649> A_IWL<31648> A_IWL<31647> A_IWL<31646> A_IWL<31645> A_IWL<31644> A_IWL<31643> A_IWL<31642> A_IWL<31641> A_IWL<31640> A_IWL<31639> A_IWL<31638> A_IWL<31637> A_IWL<31636> A_IWL<31635> A_IWL<31634> A_IWL<31633> A_IWL<31632> A_IWL<31631> A_IWL<31630> A_IWL<31629> A_IWL<31628> A_IWL<31627> A_IWL<31626> A_IWL<31625> A_IWL<31624> A_IWL<31623> A_IWL<31622> A_IWL<31621> A_IWL<31620> A_IWL<31619> A_IWL<31618> A_IWL<31617> A_IWL<31616> A_IWL<31615> A_IWL<31614> A_IWL<31613> A_IWL<31612> A_IWL<31611> A_IWL<31610> A_IWL<31609> A_IWL<31608> A_IWL<31607> A_IWL<31606> A_IWL<31605> A_IWL<31604> A_IWL<31603> A_IWL<31602> A_IWL<31601> A_IWL<31600> A_IWL<31599> A_IWL<31598> A_IWL<31597> A_IWL<31596> A_IWL<31595> A_IWL<31594> A_IWL<31593> A_IWL<31592> A_IWL<31591> A_IWL<31590> A_IWL<31589> A_IWL<31588> A_IWL<31587> A_IWL<31586> A_IWL<31585> A_IWL<31584> A_IWL<31583> A_IWL<31582> A_IWL<31581> A_IWL<31580> A_IWL<31579> A_IWL<31578> A_IWL<31577> A_IWL<31576> A_IWL<31575> A_IWL<31574> A_IWL<31573> A_IWL<31572> A_IWL<31571> A_IWL<31570> A_IWL<31569> A_IWL<31568> A_IWL<31567> A_IWL<31566> A_IWL<31565> A_IWL<31564> A_IWL<31563> A_IWL<31562> A_IWL<31561> A_IWL<31560> A_IWL<31559> A_IWL<31558> A_IWL<31557> A_IWL<31556> A_IWL<31555> A_IWL<31554> A_IWL<31553> A_IWL<31552> A_IWL<31551> A_IWL<31550> A_IWL<31549> A_IWL<31548> A_IWL<31547> A_IWL<31546> A_IWL<31545> A_IWL<31544> A_IWL<31543> A_IWL<31542> A_IWL<31541> A_IWL<31540> A_IWL<31539> A_IWL<31538> A_IWL<31537> A_IWL<31536> A_IWL<31535> A_IWL<31534> A_IWL<31533> A_IWL<31532> A_IWL<31531> A_IWL<31530> A_IWL<31529> A_IWL<31528> A_IWL<31527> A_IWL<31526> A_IWL<31525> A_IWL<31524> A_IWL<31523> A_IWL<31522> A_IWL<31521> A_IWL<31520> A_IWL<31519> A_IWL<31518> A_IWL<31517> A_IWL<31516> A_IWL<31515> A_IWL<31514> A_IWL<31513> A_IWL<31512> A_IWL<31511> A_IWL<31510> A_IWL<31509> A_IWL<31508> A_IWL<31507> A_IWL<31506> A_IWL<31505> A_IWL<31504> A_IWL<31503> A_IWL<31502> A_IWL<31501> A_IWL<31500> A_IWL<31499> A_IWL<31498> A_IWL<31497> A_IWL<31496> A_IWL<31495> A_IWL<31494> A_IWL<31493> A_IWL<31492> A_IWL<31491> A_IWL<31490> A_IWL<31489> A_IWL<31488> A_IWL<31487> A_IWL<31486> A_IWL<31485> A_IWL<31484> A_IWL<31483> A_IWL<31482> A_IWL<31481> A_IWL<31480> A_IWL<31479> A_IWL<31478> A_IWL<31477> A_IWL<31476> A_IWL<31475> A_IWL<31474> A_IWL<31473> A_IWL<31472> A_IWL<31471> A_IWL<31470> A_IWL<31469> A_IWL<31468> A_IWL<31467> A_IWL<31466> A_IWL<31465> A_IWL<31464> A_IWL<31463> A_IWL<31462> A_IWL<31461> A_IWL<31460> A_IWL<31459> A_IWL<31458> A_IWL<31457> A_IWL<31456> A_IWL<31455> A_IWL<31454> A_IWL<31453> A_IWL<31452> A_IWL<31451> A_IWL<31450> A_IWL<31449> A_IWL<31448> A_IWL<31447> A_IWL<31446> A_IWL<31445> A_IWL<31444> A_IWL<31443> A_IWL<31442> A_IWL<31441> A_IWL<31440> A_IWL<31439> A_IWL<31438> A_IWL<31437> A_IWL<31436> A_IWL<31435> A_IWL<31434> A_IWL<31433> A_IWL<31432> A_IWL<31431> A_IWL<31430> A_IWL<31429> A_IWL<31428> A_IWL<31427> A_IWL<31426> A_IWL<31425> A_IWL<31424> A_IWL<31423> A_IWL<31422> A_IWL<31421> A_IWL<31420> A_IWL<31419> A_IWL<31418> A_IWL<31417> A_IWL<31416> A_IWL<31415> A_IWL<31414> A_IWL<31413> A_IWL<31412> A_IWL<31411> A_IWL<31410> A_IWL<31409> A_IWL<31408> A_IWL<31407> A_IWL<31406> A_IWL<31405> A_IWL<31404> A_IWL<31403> A_IWL<31402> A_IWL<31401> A_IWL<31400> A_IWL<31399> A_IWL<31398> A_IWL<31397> A_IWL<31396> A_IWL<31395> A_IWL<31394> A_IWL<31393> A_IWL<31392> A_IWL<31391> A_IWL<31390> A_IWL<31389> A_IWL<31388> A_IWL<31387> A_IWL<31386> A_IWL<31385> A_IWL<31384> A_IWL<31383> A_IWL<31382> A_IWL<31381> A_IWL<31380> A_IWL<31379> A_IWL<31378> A_IWL<31377> A_IWL<31376> A_IWL<31375> A_IWL<31374> A_IWL<31373> A_IWL<31372> A_IWL<31371> A_IWL<31370> A_IWL<31369> A_IWL<31368> A_IWL<31367> A_IWL<31366> A_IWL<31365> A_IWL<31364> A_IWL<31363> A_IWL<31362> A_IWL<31361> A_IWL<31360> A_IWL<31359> A_IWL<31358> A_IWL<31357> A_IWL<31356> A_IWL<31355> A_IWL<31354> A_IWL<31353> A_IWL<31352> A_IWL<31351> A_IWL<31350> A_IWL<31349> A_IWL<31348> A_IWL<31347> A_IWL<31346> A_IWL<31345> A_IWL<31344> A_IWL<31343> A_IWL<31342> A_IWL<31341> A_IWL<31340> A_IWL<31339> A_IWL<31338> A_IWL<31337> A_IWL<31336> A_IWL<31335> A_IWL<31334> A_IWL<31333> A_IWL<31332> A_IWL<31331> A_IWL<31330> A_IWL<31329> A_IWL<31328> A_IWL<31327> A_IWL<31326> A_IWL<31325> A_IWL<31324> A_IWL<31323> A_IWL<31322> A_IWL<31321> A_IWL<31320> A_IWL<31319> A_IWL<31318> A_IWL<31317> A_IWL<31316> A_IWL<31315> A_IWL<31314> A_IWL<31313> A_IWL<31312> A_IWL<31311> A_IWL<31310> A_IWL<31309> A_IWL<31308> A_IWL<31307> A_IWL<31306> A_IWL<31305> A_IWL<31304> A_IWL<31303> A_IWL<31302> A_IWL<31301> A_IWL<31300> A_IWL<31299> A_IWL<31298> A_IWL<31297> A_IWL<31296> A_IWL<31295> A_IWL<31294> A_IWL<31293> A_IWL<31292> A_IWL<31291> A_IWL<31290> A_IWL<31289> A_IWL<31288> A_IWL<31287> A_IWL<31286> A_IWL<31285> A_IWL<31284> A_IWL<31283> A_IWL<31282> A_IWL<31281> A_IWL<31280> A_IWL<31279> A_IWL<31278> A_IWL<31277> A_IWL<31276> A_IWL<31275> A_IWL<31274> A_IWL<31273> A_IWL<31272> A_IWL<31271> A_IWL<31270> A_IWL<31269> A_IWL<31268> A_IWL<31267> A_IWL<31266> A_IWL<31265> A_IWL<31264> A_IWL<31263> A_IWL<31262> A_IWL<31261> A_IWL<31260> A_IWL<31259> A_IWL<31258> A_IWL<31257> A_IWL<31256> A_IWL<31255> A_IWL<31254> A_IWL<31253> A_IWL<31252> A_IWL<31251> A_IWL<31250> A_IWL<31249> A_IWL<31248> A_IWL<31247> A_IWL<31246> A_IWL<31245> A_IWL<31244> A_IWL<31243> A_IWL<31242> A_IWL<31241> A_IWL<31240> A_IWL<31239> A_IWL<31238> A_IWL<31237> A_IWL<31236> A_IWL<31235> A_IWL<31234> A_IWL<31233> A_IWL<31232> A_IWL<32255> A_IWL<32254> A_IWL<32253> A_IWL<32252> A_IWL<32251> A_IWL<32250> A_IWL<32249> A_IWL<32248> A_IWL<32247> A_IWL<32246> A_IWL<32245> A_IWL<32244> A_IWL<32243> A_IWL<32242> A_IWL<32241> A_IWL<32240> A_IWL<32239> A_IWL<32238> A_IWL<32237> A_IWL<32236> A_IWL<32235> A_IWL<32234> A_IWL<32233> A_IWL<32232> A_IWL<32231> A_IWL<32230> A_IWL<32229> A_IWL<32228> A_IWL<32227> A_IWL<32226> A_IWL<32225> A_IWL<32224> A_IWL<32223> A_IWL<32222> A_IWL<32221> A_IWL<32220> A_IWL<32219> A_IWL<32218> A_IWL<32217> A_IWL<32216> A_IWL<32215> A_IWL<32214> A_IWL<32213> A_IWL<32212> A_IWL<32211> A_IWL<32210> A_IWL<32209> A_IWL<32208> A_IWL<32207> A_IWL<32206> A_IWL<32205> A_IWL<32204> A_IWL<32203> A_IWL<32202> A_IWL<32201> A_IWL<32200> A_IWL<32199> A_IWL<32198> A_IWL<32197> A_IWL<32196> A_IWL<32195> A_IWL<32194> A_IWL<32193> A_IWL<32192> A_IWL<32191> A_IWL<32190> A_IWL<32189> A_IWL<32188> A_IWL<32187> A_IWL<32186> A_IWL<32185> A_IWL<32184> A_IWL<32183> A_IWL<32182> A_IWL<32181> A_IWL<32180> A_IWL<32179> A_IWL<32178> A_IWL<32177> A_IWL<32176> A_IWL<32175> A_IWL<32174> A_IWL<32173> A_IWL<32172> A_IWL<32171> A_IWL<32170> A_IWL<32169> A_IWL<32168> A_IWL<32167> A_IWL<32166> A_IWL<32165> A_IWL<32164> A_IWL<32163> A_IWL<32162> A_IWL<32161> A_IWL<32160> A_IWL<32159> A_IWL<32158> A_IWL<32157> A_IWL<32156> A_IWL<32155> A_IWL<32154> A_IWL<32153> A_IWL<32152> A_IWL<32151> A_IWL<32150> A_IWL<32149> A_IWL<32148> A_IWL<32147> A_IWL<32146> A_IWL<32145> A_IWL<32144> A_IWL<32143> A_IWL<32142> A_IWL<32141> A_IWL<32140> A_IWL<32139> A_IWL<32138> A_IWL<32137> A_IWL<32136> A_IWL<32135> A_IWL<32134> A_IWL<32133> A_IWL<32132> A_IWL<32131> A_IWL<32130> A_IWL<32129> A_IWL<32128> A_IWL<32127> A_IWL<32126> A_IWL<32125> A_IWL<32124> A_IWL<32123> A_IWL<32122> A_IWL<32121> A_IWL<32120> A_IWL<32119> A_IWL<32118> A_IWL<32117> A_IWL<32116> A_IWL<32115> A_IWL<32114> A_IWL<32113> A_IWL<32112> A_IWL<32111> A_IWL<32110> A_IWL<32109> A_IWL<32108> A_IWL<32107> A_IWL<32106> A_IWL<32105> A_IWL<32104> A_IWL<32103> A_IWL<32102> A_IWL<32101> A_IWL<32100> A_IWL<32099> A_IWL<32098> A_IWL<32097> A_IWL<32096> A_IWL<32095> A_IWL<32094> A_IWL<32093> A_IWL<32092> A_IWL<32091> A_IWL<32090> A_IWL<32089> A_IWL<32088> A_IWL<32087> A_IWL<32086> A_IWL<32085> A_IWL<32084> A_IWL<32083> A_IWL<32082> A_IWL<32081> A_IWL<32080> A_IWL<32079> A_IWL<32078> A_IWL<32077> A_IWL<32076> A_IWL<32075> A_IWL<32074> A_IWL<32073> A_IWL<32072> A_IWL<32071> A_IWL<32070> A_IWL<32069> A_IWL<32068> A_IWL<32067> A_IWL<32066> A_IWL<32065> A_IWL<32064> A_IWL<32063> A_IWL<32062> A_IWL<32061> A_IWL<32060> A_IWL<32059> A_IWL<32058> A_IWL<32057> A_IWL<32056> A_IWL<32055> A_IWL<32054> A_IWL<32053> A_IWL<32052> A_IWL<32051> A_IWL<32050> A_IWL<32049> A_IWL<32048> A_IWL<32047> A_IWL<32046> A_IWL<32045> A_IWL<32044> A_IWL<32043> A_IWL<32042> A_IWL<32041> A_IWL<32040> A_IWL<32039> A_IWL<32038> A_IWL<32037> A_IWL<32036> A_IWL<32035> A_IWL<32034> A_IWL<32033> A_IWL<32032> A_IWL<32031> A_IWL<32030> A_IWL<32029> A_IWL<32028> A_IWL<32027> A_IWL<32026> A_IWL<32025> A_IWL<32024> A_IWL<32023> A_IWL<32022> A_IWL<32021> A_IWL<32020> A_IWL<32019> A_IWL<32018> A_IWL<32017> A_IWL<32016> A_IWL<32015> A_IWL<32014> A_IWL<32013> A_IWL<32012> A_IWL<32011> A_IWL<32010> A_IWL<32009> A_IWL<32008> A_IWL<32007> A_IWL<32006> A_IWL<32005> A_IWL<32004> A_IWL<32003> A_IWL<32002> A_IWL<32001> A_IWL<32000> A_IWL<31999> A_IWL<31998> A_IWL<31997> A_IWL<31996> A_IWL<31995> A_IWL<31994> A_IWL<31993> A_IWL<31992> A_IWL<31991> A_IWL<31990> A_IWL<31989> A_IWL<31988> A_IWL<31987> A_IWL<31986> A_IWL<31985> A_IWL<31984> A_IWL<31983> A_IWL<31982> A_IWL<31981> A_IWL<31980> A_IWL<31979> A_IWL<31978> A_IWL<31977> A_IWL<31976> A_IWL<31975> A_IWL<31974> A_IWL<31973> A_IWL<31972> A_IWL<31971> A_IWL<31970> A_IWL<31969> A_IWL<31968> A_IWL<31967> A_IWL<31966> A_IWL<31965> A_IWL<31964> A_IWL<31963> A_IWL<31962> A_IWL<31961> A_IWL<31960> A_IWL<31959> A_IWL<31958> A_IWL<31957> A_IWL<31956> A_IWL<31955> A_IWL<31954> A_IWL<31953> A_IWL<31952> A_IWL<31951> A_IWL<31950> A_IWL<31949> A_IWL<31948> A_IWL<31947> A_IWL<31946> A_IWL<31945> A_IWL<31944> A_IWL<31943> A_IWL<31942> A_IWL<31941> A_IWL<31940> A_IWL<31939> A_IWL<31938> A_IWL<31937> A_IWL<31936> A_IWL<31935> A_IWL<31934> A_IWL<31933> A_IWL<31932> A_IWL<31931> A_IWL<31930> A_IWL<31929> A_IWL<31928> A_IWL<31927> A_IWL<31926> A_IWL<31925> A_IWL<31924> A_IWL<31923> A_IWL<31922> A_IWL<31921> A_IWL<31920> A_IWL<31919> A_IWL<31918> A_IWL<31917> A_IWL<31916> A_IWL<31915> A_IWL<31914> A_IWL<31913> A_IWL<31912> A_IWL<31911> A_IWL<31910> A_IWL<31909> A_IWL<31908> A_IWL<31907> A_IWL<31906> A_IWL<31905> A_IWL<31904> A_IWL<31903> A_IWL<31902> A_IWL<31901> A_IWL<31900> A_IWL<31899> A_IWL<31898> A_IWL<31897> A_IWL<31896> A_IWL<31895> A_IWL<31894> A_IWL<31893> A_IWL<31892> A_IWL<31891> A_IWL<31890> A_IWL<31889> A_IWL<31888> A_IWL<31887> A_IWL<31886> A_IWL<31885> A_IWL<31884> A_IWL<31883> A_IWL<31882> A_IWL<31881> A_IWL<31880> A_IWL<31879> A_IWL<31878> A_IWL<31877> A_IWL<31876> A_IWL<31875> A_IWL<31874> A_IWL<31873> A_IWL<31872> A_IWL<31871> A_IWL<31870> A_IWL<31869> A_IWL<31868> A_IWL<31867> A_IWL<31866> A_IWL<31865> A_IWL<31864> A_IWL<31863> A_IWL<31862> A_IWL<31861> A_IWL<31860> A_IWL<31859> A_IWL<31858> A_IWL<31857> A_IWL<31856> A_IWL<31855> A_IWL<31854> A_IWL<31853> A_IWL<31852> A_IWL<31851> A_IWL<31850> A_IWL<31849> A_IWL<31848> A_IWL<31847> A_IWL<31846> A_IWL<31845> A_IWL<31844> A_IWL<31843> A_IWL<31842> A_IWL<31841> A_IWL<31840> A_IWL<31839> A_IWL<31838> A_IWL<31837> A_IWL<31836> A_IWL<31835> A_IWL<31834> A_IWL<31833> A_IWL<31832> A_IWL<31831> A_IWL<31830> A_IWL<31829> A_IWL<31828> A_IWL<31827> A_IWL<31826> A_IWL<31825> A_IWL<31824> A_IWL<31823> A_IWL<31822> A_IWL<31821> A_IWL<31820> A_IWL<31819> A_IWL<31818> A_IWL<31817> A_IWL<31816> A_IWL<31815> A_IWL<31814> A_IWL<31813> A_IWL<31812> A_IWL<31811> A_IWL<31810> A_IWL<31809> A_IWL<31808> A_IWL<31807> A_IWL<31806> A_IWL<31805> A_IWL<31804> A_IWL<31803> A_IWL<31802> A_IWL<31801> A_IWL<31800> A_IWL<31799> A_IWL<31798> A_IWL<31797> A_IWL<31796> A_IWL<31795> A_IWL<31794> A_IWL<31793> A_IWL<31792> A_IWL<31791> A_IWL<31790> A_IWL<31789> A_IWL<31788> A_IWL<31787> A_IWL<31786> A_IWL<31785> A_IWL<31784> A_IWL<31783> A_IWL<31782> A_IWL<31781> A_IWL<31780> A_IWL<31779> A_IWL<31778> A_IWL<31777> A_IWL<31776> A_IWL<31775> A_IWL<31774> A_IWL<31773> A_IWL<31772> A_IWL<31771> A_IWL<31770> A_IWL<31769> A_IWL<31768> A_IWL<31767> A_IWL<31766> A_IWL<31765> A_IWL<31764> A_IWL<31763> A_IWL<31762> A_IWL<31761> A_IWL<31760> A_IWL<31759> A_IWL<31758> A_IWL<31757> A_IWL<31756> A_IWL<31755> A_IWL<31754> A_IWL<31753> A_IWL<31752> A_IWL<31751> A_IWL<31750> A_IWL<31749> A_IWL<31748> A_IWL<31747> A_IWL<31746> A_IWL<31745> A_IWL<31744> VDD_CORE VSS / RM_IHPSG13_8192x32_c4_1P_COLUMN_pcell_0 +XCOL<61> A_BLC<123> A_BLC<122> A_BLC_TOP<123> A_BLC_TOP<122> A_BLT<123> A_BLT<122> A_BLT_TOP<123> A_BLT_TOP<122> A_IWL<31231> A_IWL<31230> A_IWL<31229> A_IWL<31228> A_IWL<31227> A_IWL<31226> A_IWL<31225> A_IWL<31224> A_IWL<31223> A_IWL<31222> A_IWL<31221> A_IWL<31220> A_IWL<31219> A_IWL<31218> A_IWL<31217> A_IWL<31216> A_IWL<31215> A_IWL<31214> A_IWL<31213> A_IWL<31212> A_IWL<31211> A_IWL<31210> A_IWL<31209> A_IWL<31208> A_IWL<31207> A_IWL<31206> A_IWL<31205> A_IWL<31204> A_IWL<31203> A_IWL<31202> A_IWL<31201> A_IWL<31200> A_IWL<31199> A_IWL<31198> A_IWL<31197> A_IWL<31196> A_IWL<31195> A_IWL<31194> A_IWL<31193> A_IWL<31192> A_IWL<31191> A_IWL<31190> A_IWL<31189> A_IWL<31188> A_IWL<31187> A_IWL<31186> A_IWL<31185> A_IWL<31184> A_IWL<31183> A_IWL<31182> A_IWL<31181> A_IWL<31180> A_IWL<31179> A_IWL<31178> A_IWL<31177> A_IWL<31176> A_IWL<31175> A_IWL<31174> A_IWL<31173> A_IWL<31172> A_IWL<31171> A_IWL<31170> A_IWL<31169> A_IWL<31168> A_IWL<31167> A_IWL<31166> A_IWL<31165> A_IWL<31164> A_IWL<31163> A_IWL<31162> A_IWL<31161> A_IWL<31160> A_IWL<31159> A_IWL<31158> A_IWL<31157> A_IWL<31156> A_IWL<31155> A_IWL<31154> A_IWL<31153> A_IWL<31152> A_IWL<31151> A_IWL<31150> A_IWL<31149> A_IWL<31148> A_IWL<31147> A_IWL<31146> A_IWL<31145> A_IWL<31144> A_IWL<31143> A_IWL<31142> A_IWL<31141> A_IWL<31140> A_IWL<31139> A_IWL<31138> A_IWL<31137> A_IWL<31136> A_IWL<31135> A_IWL<31134> A_IWL<31133> A_IWL<31132> A_IWL<31131> A_IWL<31130> A_IWL<31129> A_IWL<31128> A_IWL<31127> A_IWL<31126> A_IWL<31125> A_IWL<31124> A_IWL<31123> A_IWL<31122> A_IWL<31121> A_IWL<31120> A_IWL<31119> A_IWL<31118> A_IWL<31117> A_IWL<31116> A_IWL<31115> A_IWL<31114> A_IWL<31113> A_IWL<31112> A_IWL<31111> A_IWL<31110> A_IWL<31109> A_IWL<31108> A_IWL<31107> A_IWL<31106> A_IWL<31105> A_IWL<31104> A_IWL<31103> A_IWL<31102> A_IWL<31101> A_IWL<31100> A_IWL<31099> A_IWL<31098> A_IWL<31097> A_IWL<31096> A_IWL<31095> A_IWL<31094> A_IWL<31093> A_IWL<31092> A_IWL<31091> A_IWL<31090> A_IWL<31089> A_IWL<31088> A_IWL<31087> A_IWL<31086> A_IWL<31085> A_IWL<31084> A_IWL<31083> A_IWL<31082> A_IWL<31081> A_IWL<31080> A_IWL<31079> A_IWL<31078> A_IWL<31077> A_IWL<31076> A_IWL<31075> A_IWL<31074> A_IWL<31073> A_IWL<31072> A_IWL<31071> A_IWL<31070> A_IWL<31069> A_IWL<31068> A_IWL<31067> A_IWL<31066> A_IWL<31065> A_IWL<31064> A_IWL<31063> A_IWL<31062> A_IWL<31061> A_IWL<31060> A_IWL<31059> A_IWL<31058> A_IWL<31057> A_IWL<31056> A_IWL<31055> A_IWL<31054> A_IWL<31053> A_IWL<31052> A_IWL<31051> A_IWL<31050> A_IWL<31049> A_IWL<31048> A_IWL<31047> A_IWL<31046> A_IWL<31045> A_IWL<31044> A_IWL<31043> A_IWL<31042> A_IWL<31041> A_IWL<31040> A_IWL<31039> A_IWL<31038> A_IWL<31037> A_IWL<31036> A_IWL<31035> A_IWL<31034> A_IWL<31033> A_IWL<31032> A_IWL<31031> A_IWL<31030> A_IWL<31029> A_IWL<31028> A_IWL<31027> A_IWL<31026> A_IWL<31025> A_IWL<31024> A_IWL<31023> A_IWL<31022> A_IWL<31021> A_IWL<31020> A_IWL<31019> A_IWL<31018> A_IWL<31017> A_IWL<31016> A_IWL<31015> A_IWL<31014> A_IWL<31013> A_IWL<31012> A_IWL<31011> A_IWL<31010> A_IWL<31009> A_IWL<31008> A_IWL<31007> A_IWL<31006> A_IWL<31005> A_IWL<31004> A_IWL<31003> A_IWL<31002> A_IWL<31001> A_IWL<31000> A_IWL<30999> A_IWL<30998> A_IWL<30997> A_IWL<30996> A_IWL<30995> A_IWL<30994> A_IWL<30993> A_IWL<30992> A_IWL<30991> A_IWL<30990> A_IWL<30989> A_IWL<30988> A_IWL<30987> A_IWL<30986> A_IWL<30985> A_IWL<30984> A_IWL<30983> A_IWL<30982> A_IWL<30981> A_IWL<30980> A_IWL<30979> A_IWL<30978> A_IWL<30977> A_IWL<30976> A_IWL<30975> A_IWL<30974> A_IWL<30973> A_IWL<30972> A_IWL<30971> A_IWL<30970> A_IWL<30969> A_IWL<30968> A_IWL<30967> A_IWL<30966> A_IWL<30965> A_IWL<30964> A_IWL<30963> A_IWL<30962> A_IWL<30961> A_IWL<30960> A_IWL<30959> A_IWL<30958> A_IWL<30957> A_IWL<30956> A_IWL<30955> A_IWL<30954> A_IWL<30953> A_IWL<30952> A_IWL<30951> A_IWL<30950> A_IWL<30949> A_IWL<30948> A_IWL<30947> A_IWL<30946> A_IWL<30945> A_IWL<30944> A_IWL<30943> A_IWL<30942> A_IWL<30941> A_IWL<30940> A_IWL<30939> A_IWL<30938> A_IWL<30937> A_IWL<30936> A_IWL<30935> A_IWL<30934> A_IWL<30933> A_IWL<30932> A_IWL<30931> A_IWL<30930> A_IWL<30929> A_IWL<30928> A_IWL<30927> A_IWL<30926> A_IWL<30925> A_IWL<30924> A_IWL<30923> A_IWL<30922> A_IWL<30921> A_IWL<30920> A_IWL<30919> A_IWL<30918> A_IWL<30917> A_IWL<30916> A_IWL<30915> A_IWL<30914> A_IWL<30913> A_IWL<30912> A_IWL<30911> A_IWL<30910> A_IWL<30909> A_IWL<30908> A_IWL<30907> A_IWL<30906> A_IWL<30905> A_IWL<30904> A_IWL<30903> A_IWL<30902> A_IWL<30901> A_IWL<30900> A_IWL<30899> A_IWL<30898> A_IWL<30897> A_IWL<30896> A_IWL<30895> A_IWL<30894> A_IWL<30893> A_IWL<30892> A_IWL<30891> A_IWL<30890> A_IWL<30889> A_IWL<30888> A_IWL<30887> A_IWL<30886> A_IWL<30885> A_IWL<30884> A_IWL<30883> A_IWL<30882> A_IWL<30881> A_IWL<30880> A_IWL<30879> A_IWL<30878> A_IWL<30877> A_IWL<30876> A_IWL<30875> A_IWL<30874> A_IWL<30873> A_IWL<30872> A_IWL<30871> A_IWL<30870> A_IWL<30869> A_IWL<30868> A_IWL<30867> A_IWL<30866> A_IWL<30865> A_IWL<30864> A_IWL<30863> A_IWL<30862> A_IWL<30861> A_IWL<30860> A_IWL<30859> A_IWL<30858> A_IWL<30857> A_IWL<30856> A_IWL<30855> A_IWL<30854> A_IWL<30853> A_IWL<30852> A_IWL<30851> A_IWL<30850> A_IWL<30849> A_IWL<30848> A_IWL<30847> A_IWL<30846> A_IWL<30845> A_IWL<30844> A_IWL<30843> A_IWL<30842> A_IWL<30841> A_IWL<30840> A_IWL<30839> A_IWL<30838> A_IWL<30837> A_IWL<30836> A_IWL<30835> A_IWL<30834> A_IWL<30833> A_IWL<30832> A_IWL<30831> A_IWL<30830> A_IWL<30829> A_IWL<30828> A_IWL<30827> A_IWL<30826> A_IWL<30825> A_IWL<30824> A_IWL<30823> A_IWL<30822> A_IWL<30821> A_IWL<30820> A_IWL<30819> A_IWL<30818> A_IWL<30817> A_IWL<30816> A_IWL<30815> A_IWL<30814> A_IWL<30813> A_IWL<30812> A_IWL<30811> A_IWL<30810> A_IWL<30809> A_IWL<30808> A_IWL<30807> A_IWL<30806> A_IWL<30805> A_IWL<30804> A_IWL<30803> A_IWL<30802> A_IWL<30801> A_IWL<30800> A_IWL<30799> A_IWL<30798> A_IWL<30797> A_IWL<30796> A_IWL<30795> A_IWL<30794> A_IWL<30793> A_IWL<30792> A_IWL<30791> A_IWL<30790> A_IWL<30789> A_IWL<30788> A_IWL<30787> A_IWL<30786> A_IWL<30785> A_IWL<30784> A_IWL<30783> A_IWL<30782> A_IWL<30781> A_IWL<30780> A_IWL<30779> A_IWL<30778> A_IWL<30777> A_IWL<30776> A_IWL<30775> A_IWL<30774> A_IWL<30773> A_IWL<30772> A_IWL<30771> A_IWL<30770> A_IWL<30769> A_IWL<30768> A_IWL<30767> A_IWL<30766> A_IWL<30765> A_IWL<30764> A_IWL<30763> A_IWL<30762> A_IWL<30761> A_IWL<30760> A_IWL<30759> A_IWL<30758> A_IWL<30757> A_IWL<30756> A_IWL<30755> A_IWL<30754> A_IWL<30753> A_IWL<30752> A_IWL<30751> A_IWL<30750> A_IWL<30749> A_IWL<30748> A_IWL<30747> A_IWL<30746> A_IWL<30745> A_IWL<30744> A_IWL<30743> A_IWL<30742> A_IWL<30741> A_IWL<30740> A_IWL<30739> A_IWL<30738> A_IWL<30737> A_IWL<30736> A_IWL<30735> A_IWL<30734> A_IWL<30733> A_IWL<30732> A_IWL<30731> A_IWL<30730> A_IWL<30729> A_IWL<30728> A_IWL<30727> A_IWL<30726> A_IWL<30725> A_IWL<30724> A_IWL<30723> A_IWL<30722> A_IWL<30721> A_IWL<30720> A_IWL<31743> A_IWL<31742> A_IWL<31741> A_IWL<31740> A_IWL<31739> A_IWL<31738> A_IWL<31737> A_IWL<31736> A_IWL<31735> A_IWL<31734> A_IWL<31733> A_IWL<31732> A_IWL<31731> A_IWL<31730> A_IWL<31729> A_IWL<31728> A_IWL<31727> A_IWL<31726> A_IWL<31725> A_IWL<31724> A_IWL<31723> A_IWL<31722> A_IWL<31721> A_IWL<31720> A_IWL<31719> A_IWL<31718> A_IWL<31717> A_IWL<31716> A_IWL<31715> A_IWL<31714> A_IWL<31713> A_IWL<31712> A_IWL<31711> A_IWL<31710> A_IWL<31709> A_IWL<31708> A_IWL<31707> A_IWL<31706> A_IWL<31705> A_IWL<31704> A_IWL<31703> A_IWL<31702> A_IWL<31701> A_IWL<31700> A_IWL<31699> A_IWL<31698> A_IWL<31697> A_IWL<31696> A_IWL<31695> A_IWL<31694> A_IWL<31693> A_IWL<31692> A_IWL<31691> A_IWL<31690> A_IWL<31689> A_IWL<31688> A_IWL<31687> A_IWL<31686> A_IWL<31685> A_IWL<31684> A_IWL<31683> A_IWL<31682> A_IWL<31681> A_IWL<31680> A_IWL<31679> A_IWL<31678> A_IWL<31677> A_IWL<31676> A_IWL<31675> A_IWL<31674> A_IWL<31673> A_IWL<31672> A_IWL<31671> A_IWL<31670> A_IWL<31669> A_IWL<31668> A_IWL<31667> A_IWL<31666> A_IWL<31665> A_IWL<31664> A_IWL<31663> A_IWL<31662> A_IWL<31661> A_IWL<31660> A_IWL<31659> A_IWL<31658> A_IWL<31657> A_IWL<31656> A_IWL<31655> A_IWL<31654> A_IWL<31653> A_IWL<31652> A_IWL<31651> A_IWL<31650> A_IWL<31649> A_IWL<31648> A_IWL<31647> A_IWL<31646> A_IWL<31645> A_IWL<31644> A_IWL<31643> A_IWL<31642> A_IWL<31641> A_IWL<31640> A_IWL<31639> A_IWL<31638> A_IWL<31637> A_IWL<31636> A_IWL<31635> A_IWL<31634> A_IWL<31633> A_IWL<31632> A_IWL<31631> A_IWL<31630> A_IWL<31629> A_IWL<31628> A_IWL<31627> A_IWL<31626> A_IWL<31625> A_IWL<31624> A_IWL<31623> A_IWL<31622> A_IWL<31621> A_IWL<31620> A_IWL<31619> A_IWL<31618> A_IWL<31617> A_IWL<31616> A_IWL<31615> A_IWL<31614> A_IWL<31613> A_IWL<31612> A_IWL<31611> A_IWL<31610> A_IWL<31609> A_IWL<31608> A_IWL<31607> A_IWL<31606> A_IWL<31605> A_IWL<31604> A_IWL<31603> A_IWL<31602> A_IWL<31601> A_IWL<31600> A_IWL<31599> A_IWL<31598> A_IWL<31597> A_IWL<31596> A_IWL<31595> A_IWL<31594> A_IWL<31593> A_IWL<31592> A_IWL<31591> A_IWL<31590> A_IWL<31589> A_IWL<31588> A_IWL<31587> A_IWL<31586> A_IWL<31585> A_IWL<31584> A_IWL<31583> A_IWL<31582> A_IWL<31581> A_IWL<31580> A_IWL<31579> A_IWL<31578> A_IWL<31577> A_IWL<31576> A_IWL<31575> A_IWL<31574> A_IWL<31573> A_IWL<31572> A_IWL<31571> A_IWL<31570> A_IWL<31569> A_IWL<31568> A_IWL<31567> A_IWL<31566> A_IWL<31565> A_IWL<31564> A_IWL<31563> A_IWL<31562> A_IWL<31561> A_IWL<31560> A_IWL<31559> A_IWL<31558> A_IWL<31557> A_IWL<31556> A_IWL<31555> A_IWL<31554> A_IWL<31553> A_IWL<31552> A_IWL<31551> A_IWL<31550> A_IWL<31549> A_IWL<31548> A_IWL<31547> A_IWL<31546> A_IWL<31545> A_IWL<31544> A_IWL<31543> A_IWL<31542> A_IWL<31541> A_IWL<31540> A_IWL<31539> A_IWL<31538> A_IWL<31537> A_IWL<31536> A_IWL<31535> A_IWL<31534> A_IWL<31533> A_IWL<31532> A_IWL<31531> A_IWL<31530> A_IWL<31529> A_IWL<31528> A_IWL<31527> A_IWL<31526> A_IWL<31525> A_IWL<31524> A_IWL<31523> A_IWL<31522> A_IWL<31521> A_IWL<31520> A_IWL<31519> A_IWL<31518> A_IWL<31517> A_IWL<31516> A_IWL<31515> A_IWL<31514> A_IWL<31513> A_IWL<31512> A_IWL<31511> A_IWL<31510> A_IWL<31509> A_IWL<31508> A_IWL<31507> A_IWL<31506> A_IWL<31505> A_IWL<31504> A_IWL<31503> A_IWL<31502> A_IWL<31501> A_IWL<31500> A_IWL<31499> A_IWL<31498> A_IWL<31497> A_IWL<31496> A_IWL<31495> A_IWL<31494> A_IWL<31493> A_IWL<31492> A_IWL<31491> A_IWL<31490> A_IWL<31489> A_IWL<31488> A_IWL<31487> A_IWL<31486> A_IWL<31485> A_IWL<31484> A_IWL<31483> A_IWL<31482> A_IWL<31481> A_IWL<31480> A_IWL<31479> A_IWL<31478> A_IWL<31477> A_IWL<31476> A_IWL<31475> A_IWL<31474> A_IWL<31473> A_IWL<31472> A_IWL<31471> A_IWL<31470> A_IWL<31469> A_IWL<31468> A_IWL<31467> A_IWL<31466> A_IWL<31465> A_IWL<31464> A_IWL<31463> A_IWL<31462> A_IWL<31461> A_IWL<31460> A_IWL<31459> A_IWL<31458> A_IWL<31457> A_IWL<31456> A_IWL<31455> A_IWL<31454> A_IWL<31453> A_IWL<31452> A_IWL<31451> A_IWL<31450> A_IWL<31449> A_IWL<31448> A_IWL<31447> A_IWL<31446> A_IWL<31445> A_IWL<31444> A_IWL<31443> A_IWL<31442> A_IWL<31441> A_IWL<31440> A_IWL<31439> A_IWL<31438> A_IWL<31437> A_IWL<31436> A_IWL<31435> A_IWL<31434> A_IWL<31433> A_IWL<31432> A_IWL<31431> A_IWL<31430> A_IWL<31429> A_IWL<31428> A_IWL<31427> A_IWL<31426> A_IWL<31425> A_IWL<31424> A_IWL<31423> A_IWL<31422> A_IWL<31421> A_IWL<31420> A_IWL<31419> A_IWL<31418> A_IWL<31417> A_IWL<31416> A_IWL<31415> A_IWL<31414> A_IWL<31413> A_IWL<31412> A_IWL<31411> A_IWL<31410> A_IWL<31409> A_IWL<31408> A_IWL<31407> A_IWL<31406> A_IWL<31405> A_IWL<31404> A_IWL<31403> A_IWL<31402> A_IWL<31401> A_IWL<31400> A_IWL<31399> A_IWL<31398> A_IWL<31397> A_IWL<31396> A_IWL<31395> A_IWL<31394> A_IWL<31393> A_IWL<31392> A_IWL<31391> A_IWL<31390> A_IWL<31389> A_IWL<31388> A_IWL<31387> A_IWL<31386> A_IWL<31385> A_IWL<31384> A_IWL<31383> A_IWL<31382> A_IWL<31381> A_IWL<31380> A_IWL<31379> A_IWL<31378> A_IWL<31377> A_IWL<31376> A_IWL<31375> A_IWL<31374> A_IWL<31373> A_IWL<31372> A_IWL<31371> A_IWL<31370> A_IWL<31369> A_IWL<31368> A_IWL<31367> A_IWL<31366> A_IWL<31365> A_IWL<31364> A_IWL<31363> A_IWL<31362> A_IWL<31361> A_IWL<31360> A_IWL<31359> A_IWL<31358> A_IWL<31357> A_IWL<31356> A_IWL<31355> A_IWL<31354> A_IWL<31353> A_IWL<31352> A_IWL<31351> A_IWL<31350> A_IWL<31349> A_IWL<31348> A_IWL<31347> A_IWL<31346> A_IWL<31345> A_IWL<31344> A_IWL<31343> A_IWL<31342> A_IWL<31341> A_IWL<31340> A_IWL<31339> A_IWL<31338> A_IWL<31337> A_IWL<31336> A_IWL<31335> A_IWL<31334> A_IWL<31333> A_IWL<31332> A_IWL<31331> A_IWL<31330> A_IWL<31329> A_IWL<31328> A_IWL<31327> A_IWL<31326> A_IWL<31325> A_IWL<31324> A_IWL<31323> A_IWL<31322> A_IWL<31321> A_IWL<31320> A_IWL<31319> A_IWL<31318> A_IWL<31317> A_IWL<31316> A_IWL<31315> A_IWL<31314> A_IWL<31313> A_IWL<31312> A_IWL<31311> A_IWL<31310> A_IWL<31309> A_IWL<31308> A_IWL<31307> A_IWL<31306> A_IWL<31305> A_IWL<31304> A_IWL<31303> A_IWL<31302> A_IWL<31301> A_IWL<31300> A_IWL<31299> A_IWL<31298> A_IWL<31297> A_IWL<31296> A_IWL<31295> A_IWL<31294> A_IWL<31293> A_IWL<31292> A_IWL<31291> A_IWL<31290> A_IWL<31289> A_IWL<31288> A_IWL<31287> A_IWL<31286> A_IWL<31285> A_IWL<31284> A_IWL<31283> A_IWL<31282> A_IWL<31281> A_IWL<31280> A_IWL<31279> A_IWL<31278> A_IWL<31277> A_IWL<31276> A_IWL<31275> A_IWL<31274> A_IWL<31273> A_IWL<31272> A_IWL<31271> A_IWL<31270> A_IWL<31269> A_IWL<31268> A_IWL<31267> A_IWL<31266> A_IWL<31265> A_IWL<31264> A_IWL<31263> A_IWL<31262> A_IWL<31261> A_IWL<31260> A_IWL<31259> A_IWL<31258> A_IWL<31257> A_IWL<31256> A_IWL<31255> A_IWL<31254> A_IWL<31253> A_IWL<31252> A_IWL<31251> A_IWL<31250> A_IWL<31249> A_IWL<31248> A_IWL<31247> A_IWL<31246> A_IWL<31245> A_IWL<31244> A_IWL<31243> A_IWL<31242> A_IWL<31241> A_IWL<31240> A_IWL<31239> A_IWL<31238> A_IWL<31237> A_IWL<31236> A_IWL<31235> A_IWL<31234> A_IWL<31233> A_IWL<31232> VDD_CORE VSS / RM_IHPSG13_8192x32_c4_1P_COLUMN_pcell_0 +XCOL<60> A_BLC<121> A_BLC<120> A_BLC_TOP<121> A_BLC_TOP<120> A_BLT<121> A_BLT<120> A_BLT_TOP<121> A_BLT_TOP<120> A_IWL<30719> A_IWL<30718> A_IWL<30717> A_IWL<30716> A_IWL<30715> A_IWL<30714> A_IWL<30713> A_IWL<30712> A_IWL<30711> A_IWL<30710> A_IWL<30709> A_IWL<30708> A_IWL<30707> A_IWL<30706> A_IWL<30705> A_IWL<30704> A_IWL<30703> A_IWL<30702> A_IWL<30701> A_IWL<30700> A_IWL<30699> A_IWL<30698> A_IWL<30697> A_IWL<30696> A_IWL<30695> A_IWL<30694> A_IWL<30693> A_IWL<30692> A_IWL<30691> A_IWL<30690> A_IWL<30689> A_IWL<30688> A_IWL<30687> A_IWL<30686> A_IWL<30685> A_IWL<30684> A_IWL<30683> A_IWL<30682> A_IWL<30681> A_IWL<30680> A_IWL<30679> A_IWL<30678> A_IWL<30677> A_IWL<30676> A_IWL<30675> A_IWL<30674> A_IWL<30673> A_IWL<30672> A_IWL<30671> A_IWL<30670> A_IWL<30669> A_IWL<30668> A_IWL<30667> A_IWL<30666> A_IWL<30665> A_IWL<30664> A_IWL<30663> A_IWL<30662> A_IWL<30661> A_IWL<30660> A_IWL<30659> A_IWL<30658> A_IWL<30657> A_IWL<30656> A_IWL<30655> A_IWL<30654> A_IWL<30653> A_IWL<30652> A_IWL<30651> A_IWL<30650> A_IWL<30649> A_IWL<30648> A_IWL<30647> A_IWL<30646> A_IWL<30645> A_IWL<30644> A_IWL<30643> A_IWL<30642> A_IWL<30641> A_IWL<30640> A_IWL<30639> A_IWL<30638> A_IWL<30637> A_IWL<30636> A_IWL<30635> A_IWL<30634> A_IWL<30633> A_IWL<30632> A_IWL<30631> A_IWL<30630> A_IWL<30629> A_IWL<30628> A_IWL<30627> A_IWL<30626> A_IWL<30625> A_IWL<30624> A_IWL<30623> A_IWL<30622> A_IWL<30621> A_IWL<30620> A_IWL<30619> A_IWL<30618> A_IWL<30617> A_IWL<30616> A_IWL<30615> A_IWL<30614> A_IWL<30613> A_IWL<30612> A_IWL<30611> A_IWL<30610> A_IWL<30609> A_IWL<30608> A_IWL<30607> A_IWL<30606> A_IWL<30605> A_IWL<30604> A_IWL<30603> A_IWL<30602> A_IWL<30601> A_IWL<30600> A_IWL<30599> A_IWL<30598> A_IWL<30597> A_IWL<30596> A_IWL<30595> A_IWL<30594> A_IWL<30593> A_IWL<30592> A_IWL<30591> A_IWL<30590> A_IWL<30589> A_IWL<30588> A_IWL<30587> A_IWL<30586> A_IWL<30585> A_IWL<30584> A_IWL<30583> A_IWL<30582> A_IWL<30581> A_IWL<30580> A_IWL<30579> A_IWL<30578> A_IWL<30577> A_IWL<30576> A_IWL<30575> A_IWL<30574> A_IWL<30573> A_IWL<30572> A_IWL<30571> A_IWL<30570> A_IWL<30569> A_IWL<30568> A_IWL<30567> A_IWL<30566> A_IWL<30565> A_IWL<30564> A_IWL<30563> A_IWL<30562> A_IWL<30561> A_IWL<30560> A_IWL<30559> A_IWL<30558> A_IWL<30557> A_IWL<30556> A_IWL<30555> A_IWL<30554> A_IWL<30553> A_IWL<30552> A_IWL<30551> A_IWL<30550> A_IWL<30549> A_IWL<30548> A_IWL<30547> A_IWL<30546> A_IWL<30545> A_IWL<30544> A_IWL<30543> A_IWL<30542> A_IWL<30541> A_IWL<30540> A_IWL<30539> A_IWL<30538> A_IWL<30537> A_IWL<30536> A_IWL<30535> A_IWL<30534> A_IWL<30533> A_IWL<30532> A_IWL<30531> A_IWL<30530> A_IWL<30529> A_IWL<30528> A_IWL<30527> A_IWL<30526> A_IWL<30525> A_IWL<30524> A_IWL<30523> A_IWL<30522> A_IWL<30521> A_IWL<30520> A_IWL<30519> A_IWL<30518> A_IWL<30517> A_IWL<30516> A_IWL<30515> A_IWL<30514> A_IWL<30513> A_IWL<30512> A_IWL<30511> A_IWL<30510> A_IWL<30509> A_IWL<30508> A_IWL<30507> A_IWL<30506> A_IWL<30505> A_IWL<30504> A_IWL<30503> A_IWL<30502> A_IWL<30501> A_IWL<30500> A_IWL<30499> A_IWL<30498> A_IWL<30497> A_IWL<30496> A_IWL<30495> A_IWL<30494> A_IWL<30493> A_IWL<30492> A_IWL<30491> A_IWL<30490> A_IWL<30489> A_IWL<30488> A_IWL<30487> A_IWL<30486> A_IWL<30485> A_IWL<30484> A_IWL<30483> A_IWL<30482> A_IWL<30481> A_IWL<30480> A_IWL<30479> A_IWL<30478> A_IWL<30477> A_IWL<30476> A_IWL<30475> A_IWL<30474> A_IWL<30473> A_IWL<30472> A_IWL<30471> A_IWL<30470> A_IWL<30469> A_IWL<30468> A_IWL<30467> A_IWL<30466> A_IWL<30465> A_IWL<30464> A_IWL<30463> A_IWL<30462> A_IWL<30461> A_IWL<30460> A_IWL<30459> A_IWL<30458> A_IWL<30457> A_IWL<30456> A_IWL<30455> A_IWL<30454> A_IWL<30453> A_IWL<30452> A_IWL<30451> A_IWL<30450> A_IWL<30449> A_IWL<30448> A_IWL<30447> A_IWL<30446> A_IWL<30445> A_IWL<30444> A_IWL<30443> A_IWL<30442> A_IWL<30441> A_IWL<30440> A_IWL<30439> A_IWL<30438> A_IWL<30437> A_IWL<30436> A_IWL<30435> A_IWL<30434> A_IWL<30433> A_IWL<30432> A_IWL<30431> A_IWL<30430> A_IWL<30429> A_IWL<30428> A_IWL<30427> A_IWL<30426> A_IWL<30425> A_IWL<30424> A_IWL<30423> A_IWL<30422> A_IWL<30421> A_IWL<30420> A_IWL<30419> A_IWL<30418> A_IWL<30417> A_IWL<30416> A_IWL<30415> A_IWL<30414> A_IWL<30413> A_IWL<30412> A_IWL<30411> A_IWL<30410> A_IWL<30409> A_IWL<30408> A_IWL<30407> A_IWL<30406> A_IWL<30405> A_IWL<30404> A_IWL<30403> A_IWL<30402> A_IWL<30401> A_IWL<30400> A_IWL<30399> A_IWL<30398> A_IWL<30397> A_IWL<30396> A_IWL<30395> A_IWL<30394> A_IWL<30393> A_IWL<30392> A_IWL<30391> A_IWL<30390> A_IWL<30389> A_IWL<30388> A_IWL<30387> A_IWL<30386> A_IWL<30385> A_IWL<30384> A_IWL<30383> A_IWL<30382> A_IWL<30381> A_IWL<30380> A_IWL<30379> A_IWL<30378> A_IWL<30377> A_IWL<30376> A_IWL<30375> A_IWL<30374> A_IWL<30373> A_IWL<30372> A_IWL<30371> A_IWL<30370> A_IWL<30369> A_IWL<30368> A_IWL<30367> A_IWL<30366> A_IWL<30365> A_IWL<30364> A_IWL<30363> A_IWL<30362> A_IWL<30361> A_IWL<30360> A_IWL<30359> A_IWL<30358> A_IWL<30357> A_IWL<30356> A_IWL<30355> A_IWL<30354> A_IWL<30353> A_IWL<30352> A_IWL<30351> A_IWL<30350> A_IWL<30349> A_IWL<30348> A_IWL<30347> A_IWL<30346> A_IWL<30345> A_IWL<30344> A_IWL<30343> A_IWL<30342> A_IWL<30341> A_IWL<30340> A_IWL<30339> A_IWL<30338> A_IWL<30337> A_IWL<30336> A_IWL<30335> A_IWL<30334> A_IWL<30333> A_IWL<30332> A_IWL<30331> A_IWL<30330> A_IWL<30329> A_IWL<30328> A_IWL<30327> A_IWL<30326> A_IWL<30325> A_IWL<30324> A_IWL<30323> A_IWL<30322> A_IWL<30321> A_IWL<30320> A_IWL<30319> A_IWL<30318> A_IWL<30317> A_IWL<30316> A_IWL<30315> A_IWL<30314> A_IWL<30313> A_IWL<30312> A_IWL<30311> A_IWL<30310> A_IWL<30309> A_IWL<30308> A_IWL<30307> A_IWL<30306> A_IWL<30305> A_IWL<30304> A_IWL<30303> A_IWL<30302> A_IWL<30301> A_IWL<30300> A_IWL<30299> A_IWL<30298> A_IWL<30297> A_IWL<30296> A_IWL<30295> A_IWL<30294> A_IWL<30293> A_IWL<30292> A_IWL<30291> A_IWL<30290> A_IWL<30289> A_IWL<30288> A_IWL<30287> A_IWL<30286> A_IWL<30285> A_IWL<30284> A_IWL<30283> A_IWL<30282> A_IWL<30281> A_IWL<30280> A_IWL<30279> A_IWL<30278> A_IWL<30277> A_IWL<30276> A_IWL<30275> A_IWL<30274> A_IWL<30273> A_IWL<30272> A_IWL<30271> A_IWL<30270> A_IWL<30269> A_IWL<30268> A_IWL<30267> A_IWL<30266> A_IWL<30265> A_IWL<30264> A_IWL<30263> A_IWL<30262> A_IWL<30261> A_IWL<30260> A_IWL<30259> A_IWL<30258> A_IWL<30257> A_IWL<30256> A_IWL<30255> A_IWL<30254> A_IWL<30253> A_IWL<30252> A_IWL<30251> A_IWL<30250> A_IWL<30249> A_IWL<30248> A_IWL<30247> A_IWL<30246> A_IWL<30245> A_IWL<30244> A_IWL<30243> A_IWL<30242> A_IWL<30241> A_IWL<30240> A_IWL<30239> A_IWL<30238> A_IWL<30237> A_IWL<30236> A_IWL<30235> A_IWL<30234> A_IWL<30233> A_IWL<30232> A_IWL<30231> A_IWL<30230> A_IWL<30229> A_IWL<30228> A_IWL<30227> A_IWL<30226> A_IWL<30225> A_IWL<30224> A_IWL<30223> A_IWL<30222> A_IWL<30221> A_IWL<30220> A_IWL<30219> A_IWL<30218> A_IWL<30217> A_IWL<30216> A_IWL<30215> A_IWL<30214> A_IWL<30213> A_IWL<30212> A_IWL<30211> A_IWL<30210> A_IWL<30209> A_IWL<30208> A_IWL<31231> A_IWL<31230> A_IWL<31229> A_IWL<31228> A_IWL<31227> A_IWL<31226> A_IWL<31225> A_IWL<31224> A_IWL<31223> A_IWL<31222> A_IWL<31221> A_IWL<31220> A_IWL<31219> A_IWL<31218> A_IWL<31217> A_IWL<31216> A_IWL<31215> A_IWL<31214> A_IWL<31213> A_IWL<31212> A_IWL<31211> A_IWL<31210> A_IWL<31209> A_IWL<31208> A_IWL<31207> A_IWL<31206> A_IWL<31205> A_IWL<31204> A_IWL<31203> A_IWL<31202> A_IWL<31201> A_IWL<31200> A_IWL<31199> A_IWL<31198> A_IWL<31197> A_IWL<31196> A_IWL<31195> A_IWL<31194> A_IWL<31193> A_IWL<31192> A_IWL<31191> A_IWL<31190> A_IWL<31189> A_IWL<31188> A_IWL<31187> A_IWL<31186> A_IWL<31185> A_IWL<31184> A_IWL<31183> A_IWL<31182> A_IWL<31181> A_IWL<31180> A_IWL<31179> A_IWL<31178> A_IWL<31177> A_IWL<31176> A_IWL<31175> A_IWL<31174> A_IWL<31173> A_IWL<31172> A_IWL<31171> A_IWL<31170> A_IWL<31169> A_IWL<31168> A_IWL<31167> A_IWL<31166> A_IWL<31165> A_IWL<31164> A_IWL<31163> A_IWL<31162> A_IWL<31161> A_IWL<31160> A_IWL<31159> A_IWL<31158> A_IWL<31157> A_IWL<31156> A_IWL<31155> A_IWL<31154> A_IWL<31153> A_IWL<31152> A_IWL<31151> A_IWL<31150> A_IWL<31149> A_IWL<31148> A_IWL<31147> A_IWL<31146> A_IWL<31145> A_IWL<31144> A_IWL<31143> A_IWL<31142> A_IWL<31141> A_IWL<31140> A_IWL<31139> A_IWL<31138> A_IWL<31137> A_IWL<31136> A_IWL<31135> A_IWL<31134> A_IWL<31133> A_IWL<31132> A_IWL<31131> A_IWL<31130> A_IWL<31129> A_IWL<31128> A_IWL<31127> A_IWL<31126> A_IWL<31125> A_IWL<31124> A_IWL<31123> A_IWL<31122> A_IWL<31121> A_IWL<31120> A_IWL<31119> A_IWL<31118> A_IWL<31117> A_IWL<31116> A_IWL<31115> A_IWL<31114> A_IWL<31113> A_IWL<31112> A_IWL<31111> A_IWL<31110> A_IWL<31109> A_IWL<31108> A_IWL<31107> A_IWL<31106> A_IWL<31105> A_IWL<31104> A_IWL<31103> A_IWL<31102> A_IWL<31101> A_IWL<31100> A_IWL<31099> A_IWL<31098> A_IWL<31097> A_IWL<31096> A_IWL<31095> A_IWL<31094> A_IWL<31093> A_IWL<31092> A_IWL<31091> A_IWL<31090> A_IWL<31089> A_IWL<31088> A_IWL<31087> A_IWL<31086> A_IWL<31085> A_IWL<31084> A_IWL<31083> A_IWL<31082> A_IWL<31081> A_IWL<31080> A_IWL<31079> A_IWL<31078> A_IWL<31077> A_IWL<31076> A_IWL<31075> A_IWL<31074> A_IWL<31073> A_IWL<31072> A_IWL<31071> A_IWL<31070> A_IWL<31069> A_IWL<31068> A_IWL<31067> A_IWL<31066> A_IWL<31065> A_IWL<31064> A_IWL<31063> A_IWL<31062> A_IWL<31061> A_IWL<31060> A_IWL<31059> A_IWL<31058> A_IWL<31057> A_IWL<31056> A_IWL<31055> A_IWL<31054> A_IWL<31053> A_IWL<31052> A_IWL<31051> A_IWL<31050> A_IWL<31049> A_IWL<31048> A_IWL<31047> A_IWL<31046> A_IWL<31045> A_IWL<31044> A_IWL<31043> A_IWL<31042> A_IWL<31041> A_IWL<31040> A_IWL<31039> A_IWL<31038> A_IWL<31037> A_IWL<31036> A_IWL<31035> A_IWL<31034> A_IWL<31033> A_IWL<31032> A_IWL<31031> A_IWL<31030> A_IWL<31029> A_IWL<31028> A_IWL<31027> A_IWL<31026> A_IWL<31025> A_IWL<31024> A_IWL<31023> A_IWL<31022> A_IWL<31021> A_IWL<31020> A_IWL<31019> A_IWL<31018> A_IWL<31017> A_IWL<31016> A_IWL<31015> A_IWL<31014> A_IWL<31013> A_IWL<31012> A_IWL<31011> A_IWL<31010> A_IWL<31009> A_IWL<31008> A_IWL<31007> A_IWL<31006> A_IWL<31005> A_IWL<31004> A_IWL<31003> A_IWL<31002> A_IWL<31001> A_IWL<31000> A_IWL<30999> A_IWL<30998> A_IWL<30997> A_IWL<30996> A_IWL<30995> A_IWL<30994> A_IWL<30993> A_IWL<30992> A_IWL<30991> A_IWL<30990> A_IWL<30989> A_IWL<30988> A_IWL<30987> A_IWL<30986> A_IWL<30985> A_IWL<30984> A_IWL<30983> A_IWL<30982> A_IWL<30981> A_IWL<30980> A_IWL<30979> A_IWL<30978> A_IWL<30977> A_IWL<30976> A_IWL<30975> A_IWL<30974> A_IWL<30973> A_IWL<30972> A_IWL<30971> A_IWL<30970> A_IWL<30969> A_IWL<30968> A_IWL<30967> A_IWL<30966> A_IWL<30965> A_IWL<30964> A_IWL<30963> A_IWL<30962> A_IWL<30961> A_IWL<30960> A_IWL<30959> A_IWL<30958> A_IWL<30957> A_IWL<30956> A_IWL<30955> A_IWL<30954> A_IWL<30953> A_IWL<30952> A_IWL<30951> A_IWL<30950> A_IWL<30949> A_IWL<30948> A_IWL<30947> A_IWL<30946> A_IWL<30945> A_IWL<30944> A_IWL<30943> A_IWL<30942> A_IWL<30941> A_IWL<30940> A_IWL<30939> A_IWL<30938> A_IWL<30937> A_IWL<30936> A_IWL<30935> A_IWL<30934> A_IWL<30933> A_IWL<30932> A_IWL<30931> A_IWL<30930> A_IWL<30929> A_IWL<30928> A_IWL<30927> A_IWL<30926> A_IWL<30925> A_IWL<30924> A_IWL<30923> A_IWL<30922> A_IWL<30921> A_IWL<30920> A_IWL<30919> A_IWL<30918> A_IWL<30917> A_IWL<30916> A_IWL<30915> A_IWL<30914> A_IWL<30913> A_IWL<30912> A_IWL<30911> A_IWL<30910> A_IWL<30909> A_IWL<30908> A_IWL<30907> A_IWL<30906> A_IWL<30905> A_IWL<30904> A_IWL<30903> A_IWL<30902> A_IWL<30901> A_IWL<30900> A_IWL<30899> A_IWL<30898> A_IWL<30897> A_IWL<30896> A_IWL<30895> A_IWL<30894> A_IWL<30893> A_IWL<30892> A_IWL<30891> A_IWL<30890> A_IWL<30889> A_IWL<30888> A_IWL<30887> A_IWL<30886> A_IWL<30885> A_IWL<30884> A_IWL<30883> A_IWL<30882> A_IWL<30881> A_IWL<30880> A_IWL<30879> A_IWL<30878> A_IWL<30877> A_IWL<30876> A_IWL<30875> A_IWL<30874> A_IWL<30873> A_IWL<30872> A_IWL<30871> A_IWL<30870> A_IWL<30869> A_IWL<30868> A_IWL<30867> A_IWL<30866> A_IWL<30865> A_IWL<30864> A_IWL<30863> A_IWL<30862> A_IWL<30861> A_IWL<30860> A_IWL<30859> A_IWL<30858> A_IWL<30857> A_IWL<30856> A_IWL<30855> A_IWL<30854> A_IWL<30853> A_IWL<30852> A_IWL<30851> A_IWL<30850> A_IWL<30849> A_IWL<30848> A_IWL<30847> A_IWL<30846> A_IWL<30845> A_IWL<30844> A_IWL<30843> A_IWL<30842> A_IWL<30841> A_IWL<30840> A_IWL<30839> A_IWL<30838> A_IWL<30837> A_IWL<30836> A_IWL<30835> A_IWL<30834> A_IWL<30833> A_IWL<30832> A_IWL<30831> A_IWL<30830> A_IWL<30829> A_IWL<30828> A_IWL<30827> A_IWL<30826> A_IWL<30825> A_IWL<30824> A_IWL<30823> A_IWL<30822> A_IWL<30821> A_IWL<30820> A_IWL<30819> A_IWL<30818> A_IWL<30817> A_IWL<30816> A_IWL<30815> A_IWL<30814> A_IWL<30813> A_IWL<30812> A_IWL<30811> A_IWL<30810> A_IWL<30809> A_IWL<30808> A_IWL<30807> A_IWL<30806> A_IWL<30805> A_IWL<30804> A_IWL<30803> A_IWL<30802> A_IWL<30801> A_IWL<30800> A_IWL<30799> A_IWL<30798> A_IWL<30797> A_IWL<30796> A_IWL<30795> A_IWL<30794> A_IWL<30793> A_IWL<30792> A_IWL<30791> A_IWL<30790> A_IWL<30789> A_IWL<30788> A_IWL<30787> A_IWL<30786> A_IWL<30785> A_IWL<30784> A_IWL<30783> A_IWL<30782> A_IWL<30781> A_IWL<30780> A_IWL<30779> A_IWL<30778> A_IWL<30777> A_IWL<30776> A_IWL<30775> A_IWL<30774> A_IWL<30773> A_IWL<30772> A_IWL<30771> A_IWL<30770> A_IWL<30769> A_IWL<30768> A_IWL<30767> A_IWL<30766> A_IWL<30765> A_IWL<30764> A_IWL<30763> A_IWL<30762> A_IWL<30761> A_IWL<30760> A_IWL<30759> A_IWL<30758> A_IWL<30757> A_IWL<30756> A_IWL<30755> A_IWL<30754> A_IWL<30753> A_IWL<30752> A_IWL<30751> A_IWL<30750> A_IWL<30749> A_IWL<30748> A_IWL<30747> A_IWL<30746> A_IWL<30745> A_IWL<30744> A_IWL<30743> A_IWL<30742> A_IWL<30741> A_IWL<30740> A_IWL<30739> A_IWL<30738> A_IWL<30737> A_IWL<30736> A_IWL<30735> A_IWL<30734> A_IWL<30733> A_IWL<30732> A_IWL<30731> A_IWL<30730> A_IWL<30729> A_IWL<30728> A_IWL<30727> A_IWL<30726> A_IWL<30725> A_IWL<30724> A_IWL<30723> A_IWL<30722> A_IWL<30721> A_IWL<30720> VDD_CORE VSS / RM_IHPSG13_8192x32_c4_1P_COLUMN_pcell_0 +XCOL<59> A_BLC<119> A_BLC<118> A_BLC_TOP<119> A_BLC_TOP<118> A_BLT<119> A_BLT<118> A_BLT_TOP<119> A_BLT_TOP<118> A_IWL<30207> A_IWL<30206> A_IWL<30205> A_IWL<30204> A_IWL<30203> A_IWL<30202> A_IWL<30201> A_IWL<30200> A_IWL<30199> A_IWL<30198> A_IWL<30197> A_IWL<30196> A_IWL<30195> A_IWL<30194> A_IWL<30193> A_IWL<30192> A_IWL<30191> A_IWL<30190> A_IWL<30189> A_IWL<30188> A_IWL<30187> A_IWL<30186> A_IWL<30185> A_IWL<30184> A_IWL<30183> A_IWL<30182> A_IWL<30181> A_IWL<30180> A_IWL<30179> A_IWL<30178> A_IWL<30177> A_IWL<30176> A_IWL<30175> A_IWL<30174> A_IWL<30173> A_IWL<30172> A_IWL<30171> A_IWL<30170> A_IWL<30169> A_IWL<30168> A_IWL<30167> A_IWL<30166> A_IWL<30165> A_IWL<30164> A_IWL<30163> A_IWL<30162> A_IWL<30161> A_IWL<30160> A_IWL<30159> A_IWL<30158> A_IWL<30157> A_IWL<30156> A_IWL<30155> A_IWL<30154> A_IWL<30153> A_IWL<30152> A_IWL<30151> A_IWL<30150> A_IWL<30149> A_IWL<30148> A_IWL<30147> A_IWL<30146> A_IWL<30145> A_IWL<30144> A_IWL<30143> A_IWL<30142> A_IWL<30141> A_IWL<30140> A_IWL<30139> A_IWL<30138> A_IWL<30137> A_IWL<30136> A_IWL<30135> A_IWL<30134> A_IWL<30133> A_IWL<30132> A_IWL<30131> A_IWL<30130> A_IWL<30129> A_IWL<30128> A_IWL<30127> A_IWL<30126> A_IWL<30125> A_IWL<30124> A_IWL<30123> A_IWL<30122> A_IWL<30121> A_IWL<30120> A_IWL<30119> A_IWL<30118> A_IWL<30117> A_IWL<30116> A_IWL<30115> A_IWL<30114> A_IWL<30113> A_IWL<30112> A_IWL<30111> A_IWL<30110> A_IWL<30109> A_IWL<30108> A_IWL<30107> A_IWL<30106> A_IWL<30105> A_IWL<30104> A_IWL<30103> A_IWL<30102> A_IWL<30101> A_IWL<30100> A_IWL<30099> A_IWL<30098> A_IWL<30097> A_IWL<30096> A_IWL<30095> A_IWL<30094> A_IWL<30093> A_IWL<30092> A_IWL<30091> A_IWL<30090> A_IWL<30089> A_IWL<30088> A_IWL<30087> A_IWL<30086> A_IWL<30085> A_IWL<30084> A_IWL<30083> A_IWL<30082> A_IWL<30081> A_IWL<30080> A_IWL<30079> A_IWL<30078> A_IWL<30077> A_IWL<30076> A_IWL<30075> A_IWL<30074> A_IWL<30073> A_IWL<30072> A_IWL<30071> A_IWL<30070> A_IWL<30069> A_IWL<30068> A_IWL<30067> A_IWL<30066> A_IWL<30065> A_IWL<30064> A_IWL<30063> A_IWL<30062> A_IWL<30061> A_IWL<30060> A_IWL<30059> A_IWL<30058> A_IWL<30057> A_IWL<30056> A_IWL<30055> A_IWL<30054> A_IWL<30053> A_IWL<30052> A_IWL<30051> A_IWL<30050> A_IWL<30049> A_IWL<30048> A_IWL<30047> A_IWL<30046> A_IWL<30045> A_IWL<30044> A_IWL<30043> A_IWL<30042> A_IWL<30041> A_IWL<30040> A_IWL<30039> A_IWL<30038> A_IWL<30037> A_IWL<30036> A_IWL<30035> A_IWL<30034> A_IWL<30033> A_IWL<30032> A_IWL<30031> A_IWL<30030> A_IWL<30029> A_IWL<30028> A_IWL<30027> A_IWL<30026> A_IWL<30025> A_IWL<30024> A_IWL<30023> A_IWL<30022> A_IWL<30021> A_IWL<30020> A_IWL<30019> A_IWL<30018> A_IWL<30017> A_IWL<30016> A_IWL<30015> A_IWL<30014> A_IWL<30013> A_IWL<30012> A_IWL<30011> A_IWL<30010> A_IWL<30009> A_IWL<30008> A_IWL<30007> A_IWL<30006> A_IWL<30005> A_IWL<30004> A_IWL<30003> A_IWL<30002> A_IWL<30001> A_IWL<30000> A_IWL<29999> A_IWL<29998> A_IWL<29997> A_IWL<29996> A_IWL<29995> A_IWL<29994> A_IWL<29993> A_IWL<29992> A_IWL<29991> A_IWL<29990> A_IWL<29989> A_IWL<29988> A_IWL<29987> A_IWL<29986> A_IWL<29985> A_IWL<29984> A_IWL<29983> A_IWL<29982> A_IWL<29981> A_IWL<29980> A_IWL<29979> A_IWL<29978> A_IWL<29977> A_IWL<29976> A_IWL<29975> A_IWL<29974> A_IWL<29973> A_IWL<29972> A_IWL<29971> A_IWL<29970> A_IWL<29969> A_IWL<29968> A_IWL<29967> A_IWL<29966> A_IWL<29965> A_IWL<29964> A_IWL<29963> A_IWL<29962> A_IWL<29961> A_IWL<29960> A_IWL<29959> A_IWL<29958> A_IWL<29957> A_IWL<29956> A_IWL<29955> A_IWL<29954> A_IWL<29953> A_IWL<29952> A_IWL<29951> A_IWL<29950> A_IWL<29949> A_IWL<29948> A_IWL<29947> A_IWL<29946> A_IWL<29945> A_IWL<29944> A_IWL<29943> A_IWL<29942> A_IWL<29941> A_IWL<29940> A_IWL<29939> A_IWL<29938> A_IWL<29937> A_IWL<29936> A_IWL<29935> A_IWL<29934> A_IWL<29933> A_IWL<29932> A_IWL<29931> A_IWL<29930> A_IWL<29929> A_IWL<29928> A_IWL<29927> A_IWL<29926> A_IWL<29925> A_IWL<29924> A_IWL<29923> A_IWL<29922> A_IWL<29921> A_IWL<29920> A_IWL<29919> A_IWL<29918> A_IWL<29917> A_IWL<29916> A_IWL<29915> A_IWL<29914> A_IWL<29913> A_IWL<29912> A_IWL<29911> A_IWL<29910> A_IWL<29909> A_IWL<29908> A_IWL<29907> A_IWL<29906> A_IWL<29905> A_IWL<29904> A_IWL<29903> A_IWL<29902> A_IWL<29901> A_IWL<29900> A_IWL<29899> A_IWL<29898> A_IWL<29897> A_IWL<29896> A_IWL<29895> A_IWL<29894> A_IWL<29893> A_IWL<29892> A_IWL<29891> A_IWL<29890> A_IWL<29889> A_IWL<29888> A_IWL<29887> A_IWL<29886> A_IWL<29885> A_IWL<29884> A_IWL<29883> A_IWL<29882> A_IWL<29881> A_IWL<29880> A_IWL<29879> A_IWL<29878> A_IWL<29877> A_IWL<29876> A_IWL<29875> A_IWL<29874> A_IWL<29873> A_IWL<29872> A_IWL<29871> A_IWL<29870> A_IWL<29869> A_IWL<29868> A_IWL<29867> A_IWL<29866> A_IWL<29865> A_IWL<29864> A_IWL<29863> A_IWL<29862> A_IWL<29861> A_IWL<29860> A_IWL<29859> A_IWL<29858> A_IWL<29857> A_IWL<29856> A_IWL<29855> A_IWL<29854> A_IWL<29853> A_IWL<29852> A_IWL<29851> A_IWL<29850> A_IWL<29849> A_IWL<29848> A_IWL<29847> A_IWL<29846> A_IWL<29845> A_IWL<29844> A_IWL<29843> A_IWL<29842> A_IWL<29841> A_IWL<29840> A_IWL<29839> A_IWL<29838> A_IWL<29837> A_IWL<29836> A_IWL<29835> A_IWL<29834> A_IWL<29833> A_IWL<29832> A_IWL<29831> A_IWL<29830> A_IWL<29829> A_IWL<29828> A_IWL<29827> A_IWL<29826> A_IWL<29825> A_IWL<29824> A_IWL<29823> A_IWL<29822> A_IWL<29821> A_IWL<29820> A_IWL<29819> A_IWL<29818> A_IWL<29817> A_IWL<29816> A_IWL<29815> A_IWL<29814> A_IWL<29813> A_IWL<29812> A_IWL<29811> A_IWL<29810> A_IWL<29809> A_IWL<29808> A_IWL<29807> A_IWL<29806> A_IWL<29805> A_IWL<29804> A_IWL<29803> A_IWL<29802> A_IWL<29801> A_IWL<29800> A_IWL<29799> A_IWL<29798> A_IWL<29797> A_IWL<29796> A_IWL<29795> A_IWL<29794> A_IWL<29793> A_IWL<29792> A_IWL<29791> A_IWL<29790> A_IWL<29789> A_IWL<29788> A_IWL<29787> A_IWL<29786> A_IWL<29785> A_IWL<29784> A_IWL<29783> A_IWL<29782> A_IWL<29781> A_IWL<29780> A_IWL<29779> A_IWL<29778> A_IWL<29777> A_IWL<29776> A_IWL<29775> A_IWL<29774> A_IWL<29773> A_IWL<29772> A_IWL<29771> A_IWL<29770> A_IWL<29769> A_IWL<29768> A_IWL<29767> A_IWL<29766> A_IWL<29765> A_IWL<29764> A_IWL<29763> A_IWL<29762> A_IWL<29761> A_IWL<29760> A_IWL<29759> A_IWL<29758> A_IWL<29757> A_IWL<29756> A_IWL<29755> A_IWL<29754> A_IWL<29753> A_IWL<29752> A_IWL<29751> A_IWL<29750> A_IWL<29749> A_IWL<29748> A_IWL<29747> A_IWL<29746> A_IWL<29745> A_IWL<29744> A_IWL<29743> A_IWL<29742> A_IWL<29741> A_IWL<29740> A_IWL<29739> A_IWL<29738> A_IWL<29737> A_IWL<29736> A_IWL<29735> A_IWL<29734> A_IWL<29733> A_IWL<29732> A_IWL<29731> A_IWL<29730> A_IWL<29729> A_IWL<29728> A_IWL<29727> A_IWL<29726> A_IWL<29725> A_IWL<29724> A_IWL<29723> A_IWL<29722> A_IWL<29721> A_IWL<29720> A_IWL<29719> A_IWL<29718> A_IWL<29717> A_IWL<29716> A_IWL<29715> A_IWL<29714> A_IWL<29713> A_IWL<29712> A_IWL<29711> A_IWL<29710> A_IWL<29709> A_IWL<29708> A_IWL<29707> A_IWL<29706> A_IWL<29705> A_IWL<29704> A_IWL<29703> A_IWL<29702> A_IWL<29701> A_IWL<29700> A_IWL<29699> A_IWL<29698> A_IWL<29697> A_IWL<29696> A_IWL<30719> A_IWL<30718> A_IWL<30717> A_IWL<30716> A_IWL<30715> A_IWL<30714> A_IWL<30713> A_IWL<30712> A_IWL<30711> A_IWL<30710> A_IWL<30709> A_IWL<30708> A_IWL<30707> A_IWL<30706> A_IWL<30705> A_IWL<30704> A_IWL<30703> A_IWL<30702> A_IWL<30701> A_IWL<30700> A_IWL<30699> A_IWL<30698> A_IWL<30697> A_IWL<30696> A_IWL<30695> A_IWL<30694> A_IWL<30693> A_IWL<30692> A_IWL<30691> A_IWL<30690> A_IWL<30689> A_IWL<30688> A_IWL<30687> A_IWL<30686> A_IWL<30685> A_IWL<30684> A_IWL<30683> A_IWL<30682> A_IWL<30681> A_IWL<30680> A_IWL<30679> A_IWL<30678> A_IWL<30677> A_IWL<30676> A_IWL<30675> A_IWL<30674> A_IWL<30673> A_IWL<30672> A_IWL<30671> A_IWL<30670> A_IWL<30669> A_IWL<30668> A_IWL<30667> A_IWL<30666> A_IWL<30665> A_IWL<30664> A_IWL<30663> A_IWL<30662> A_IWL<30661> A_IWL<30660> A_IWL<30659> A_IWL<30658> A_IWL<30657> A_IWL<30656> A_IWL<30655> A_IWL<30654> A_IWL<30653> A_IWL<30652> A_IWL<30651> A_IWL<30650> A_IWL<30649> A_IWL<30648> A_IWL<30647> A_IWL<30646> A_IWL<30645> A_IWL<30644> A_IWL<30643> A_IWL<30642> A_IWL<30641> A_IWL<30640> A_IWL<30639> A_IWL<30638> A_IWL<30637> A_IWL<30636> A_IWL<30635> A_IWL<30634> A_IWL<30633> A_IWL<30632> A_IWL<30631> A_IWL<30630> A_IWL<30629> A_IWL<30628> A_IWL<30627> A_IWL<30626> A_IWL<30625> A_IWL<30624> A_IWL<30623> A_IWL<30622> A_IWL<30621> A_IWL<30620> A_IWL<30619> A_IWL<30618> A_IWL<30617> A_IWL<30616> A_IWL<30615> A_IWL<30614> A_IWL<30613> A_IWL<30612> A_IWL<30611> A_IWL<30610> A_IWL<30609> A_IWL<30608> A_IWL<30607> A_IWL<30606> A_IWL<30605> A_IWL<30604> A_IWL<30603> A_IWL<30602> A_IWL<30601> A_IWL<30600> A_IWL<30599> A_IWL<30598> A_IWL<30597> A_IWL<30596> A_IWL<30595> A_IWL<30594> A_IWL<30593> A_IWL<30592> A_IWL<30591> A_IWL<30590> A_IWL<30589> A_IWL<30588> A_IWL<30587> A_IWL<30586> A_IWL<30585> A_IWL<30584> A_IWL<30583> A_IWL<30582> A_IWL<30581> A_IWL<30580> A_IWL<30579> A_IWL<30578> A_IWL<30577> A_IWL<30576> A_IWL<30575> A_IWL<30574> A_IWL<30573> A_IWL<30572> A_IWL<30571> A_IWL<30570> A_IWL<30569> A_IWL<30568> A_IWL<30567> A_IWL<30566> A_IWL<30565> A_IWL<30564> A_IWL<30563> A_IWL<30562> A_IWL<30561> A_IWL<30560> A_IWL<30559> A_IWL<30558> A_IWL<30557> A_IWL<30556> A_IWL<30555> A_IWL<30554> A_IWL<30553> A_IWL<30552> A_IWL<30551> A_IWL<30550> A_IWL<30549> A_IWL<30548> A_IWL<30547> A_IWL<30546> A_IWL<30545> A_IWL<30544> A_IWL<30543> A_IWL<30542> A_IWL<30541> A_IWL<30540> A_IWL<30539> A_IWL<30538> A_IWL<30537> A_IWL<30536> A_IWL<30535> A_IWL<30534> A_IWL<30533> A_IWL<30532> A_IWL<30531> A_IWL<30530> A_IWL<30529> A_IWL<30528> A_IWL<30527> A_IWL<30526> A_IWL<30525> A_IWL<30524> A_IWL<30523> A_IWL<30522> A_IWL<30521> A_IWL<30520> A_IWL<30519> A_IWL<30518> A_IWL<30517> A_IWL<30516> A_IWL<30515> A_IWL<30514> A_IWL<30513> A_IWL<30512> A_IWL<30511> A_IWL<30510> A_IWL<30509> A_IWL<30508> A_IWL<30507> A_IWL<30506> A_IWL<30505> A_IWL<30504> A_IWL<30503> A_IWL<30502> A_IWL<30501> A_IWL<30500> A_IWL<30499> A_IWL<30498> A_IWL<30497> A_IWL<30496> A_IWL<30495> A_IWL<30494> A_IWL<30493> A_IWL<30492> A_IWL<30491> A_IWL<30490> A_IWL<30489> A_IWL<30488> A_IWL<30487> A_IWL<30486> A_IWL<30485> A_IWL<30484> A_IWL<30483> A_IWL<30482> A_IWL<30481> A_IWL<30480> A_IWL<30479> A_IWL<30478> A_IWL<30477> A_IWL<30476> A_IWL<30475> A_IWL<30474> A_IWL<30473> A_IWL<30472> A_IWL<30471> A_IWL<30470> A_IWL<30469> A_IWL<30468> A_IWL<30467> A_IWL<30466> A_IWL<30465> A_IWL<30464> A_IWL<30463> A_IWL<30462> A_IWL<30461> A_IWL<30460> A_IWL<30459> A_IWL<30458> A_IWL<30457> A_IWL<30456> A_IWL<30455> A_IWL<30454> A_IWL<30453> A_IWL<30452> A_IWL<30451> A_IWL<30450> A_IWL<30449> A_IWL<30448> A_IWL<30447> A_IWL<30446> A_IWL<30445> A_IWL<30444> A_IWL<30443> A_IWL<30442> A_IWL<30441> A_IWL<30440> A_IWL<30439> A_IWL<30438> A_IWL<30437> A_IWL<30436> A_IWL<30435> A_IWL<30434> A_IWL<30433> A_IWL<30432> A_IWL<30431> A_IWL<30430> A_IWL<30429> A_IWL<30428> A_IWL<30427> A_IWL<30426> A_IWL<30425> A_IWL<30424> A_IWL<30423> A_IWL<30422> A_IWL<30421> A_IWL<30420> A_IWL<30419> A_IWL<30418> A_IWL<30417> A_IWL<30416> A_IWL<30415> A_IWL<30414> A_IWL<30413> A_IWL<30412> A_IWL<30411> A_IWL<30410> A_IWL<30409> A_IWL<30408> A_IWL<30407> A_IWL<30406> A_IWL<30405> A_IWL<30404> A_IWL<30403> A_IWL<30402> A_IWL<30401> A_IWL<30400> A_IWL<30399> A_IWL<30398> A_IWL<30397> A_IWL<30396> A_IWL<30395> A_IWL<30394> A_IWL<30393> A_IWL<30392> A_IWL<30391> A_IWL<30390> A_IWL<30389> A_IWL<30388> A_IWL<30387> A_IWL<30386> A_IWL<30385> A_IWL<30384> A_IWL<30383> A_IWL<30382> A_IWL<30381> A_IWL<30380> A_IWL<30379> A_IWL<30378> A_IWL<30377> A_IWL<30376> A_IWL<30375> A_IWL<30374> A_IWL<30373> A_IWL<30372> A_IWL<30371> A_IWL<30370> A_IWL<30369> A_IWL<30368> A_IWL<30367> A_IWL<30366> A_IWL<30365> A_IWL<30364> A_IWL<30363> A_IWL<30362> A_IWL<30361> A_IWL<30360> A_IWL<30359> A_IWL<30358> A_IWL<30357> A_IWL<30356> A_IWL<30355> A_IWL<30354> A_IWL<30353> A_IWL<30352> A_IWL<30351> A_IWL<30350> A_IWL<30349> A_IWL<30348> A_IWL<30347> A_IWL<30346> A_IWL<30345> A_IWL<30344> A_IWL<30343> A_IWL<30342> A_IWL<30341> A_IWL<30340> A_IWL<30339> A_IWL<30338> A_IWL<30337> A_IWL<30336> A_IWL<30335> A_IWL<30334> A_IWL<30333> A_IWL<30332> A_IWL<30331> A_IWL<30330> A_IWL<30329> A_IWL<30328> A_IWL<30327> A_IWL<30326> A_IWL<30325> A_IWL<30324> A_IWL<30323> A_IWL<30322> A_IWL<30321> A_IWL<30320> A_IWL<30319> A_IWL<30318> A_IWL<30317> A_IWL<30316> A_IWL<30315> A_IWL<30314> A_IWL<30313> A_IWL<30312> A_IWL<30311> A_IWL<30310> A_IWL<30309> A_IWL<30308> A_IWL<30307> A_IWL<30306> A_IWL<30305> A_IWL<30304> A_IWL<30303> A_IWL<30302> A_IWL<30301> A_IWL<30300> A_IWL<30299> A_IWL<30298> A_IWL<30297> A_IWL<30296> A_IWL<30295> A_IWL<30294> A_IWL<30293> A_IWL<30292> A_IWL<30291> A_IWL<30290> A_IWL<30289> A_IWL<30288> A_IWL<30287> A_IWL<30286> A_IWL<30285> A_IWL<30284> A_IWL<30283> A_IWL<30282> A_IWL<30281> A_IWL<30280> A_IWL<30279> A_IWL<30278> A_IWL<30277> A_IWL<30276> A_IWL<30275> A_IWL<30274> A_IWL<30273> A_IWL<30272> A_IWL<30271> A_IWL<30270> A_IWL<30269> A_IWL<30268> A_IWL<30267> A_IWL<30266> A_IWL<30265> A_IWL<30264> A_IWL<30263> A_IWL<30262> A_IWL<30261> A_IWL<30260> A_IWL<30259> A_IWL<30258> A_IWL<30257> A_IWL<30256> A_IWL<30255> A_IWL<30254> A_IWL<30253> A_IWL<30252> A_IWL<30251> A_IWL<30250> A_IWL<30249> A_IWL<30248> A_IWL<30247> A_IWL<30246> A_IWL<30245> A_IWL<30244> A_IWL<30243> A_IWL<30242> A_IWL<30241> A_IWL<30240> A_IWL<30239> A_IWL<30238> A_IWL<30237> A_IWL<30236> A_IWL<30235> A_IWL<30234> A_IWL<30233> A_IWL<30232> A_IWL<30231> A_IWL<30230> A_IWL<30229> A_IWL<30228> A_IWL<30227> A_IWL<30226> A_IWL<30225> A_IWL<30224> A_IWL<30223> A_IWL<30222> A_IWL<30221> A_IWL<30220> A_IWL<30219> A_IWL<30218> A_IWL<30217> A_IWL<30216> A_IWL<30215> A_IWL<30214> A_IWL<30213> A_IWL<30212> A_IWL<30211> A_IWL<30210> A_IWL<30209> A_IWL<30208> VDD_CORE VSS / RM_IHPSG13_8192x32_c4_1P_COLUMN_pcell_0 +XCOL<58> A_BLC<117> A_BLC<116> A_BLC_TOP<117> A_BLC_TOP<116> A_BLT<117> A_BLT<116> A_BLT_TOP<117> A_BLT_TOP<116> A_IWL<29695> A_IWL<29694> A_IWL<29693> A_IWL<29692> A_IWL<29691> A_IWL<29690> A_IWL<29689> A_IWL<29688> A_IWL<29687> A_IWL<29686> A_IWL<29685> A_IWL<29684> A_IWL<29683> A_IWL<29682> A_IWL<29681> A_IWL<29680> A_IWL<29679> A_IWL<29678> A_IWL<29677> A_IWL<29676> A_IWL<29675> A_IWL<29674> A_IWL<29673> A_IWL<29672> A_IWL<29671> A_IWL<29670> A_IWL<29669> A_IWL<29668> A_IWL<29667> A_IWL<29666> A_IWL<29665> A_IWL<29664> A_IWL<29663> A_IWL<29662> A_IWL<29661> A_IWL<29660> A_IWL<29659> A_IWL<29658> A_IWL<29657> A_IWL<29656> A_IWL<29655> A_IWL<29654> A_IWL<29653> A_IWL<29652> A_IWL<29651> A_IWL<29650> A_IWL<29649> A_IWL<29648> A_IWL<29647> A_IWL<29646> A_IWL<29645> A_IWL<29644> A_IWL<29643> A_IWL<29642> A_IWL<29641> A_IWL<29640> A_IWL<29639> A_IWL<29638> A_IWL<29637> A_IWL<29636> A_IWL<29635> A_IWL<29634> A_IWL<29633> A_IWL<29632> A_IWL<29631> A_IWL<29630> A_IWL<29629> A_IWL<29628> A_IWL<29627> A_IWL<29626> A_IWL<29625> A_IWL<29624> A_IWL<29623> A_IWL<29622> A_IWL<29621> A_IWL<29620> A_IWL<29619> A_IWL<29618> A_IWL<29617> A_IWL<29616> A_IWL<29615> A_IWL<29614> A_IWL<29613> A_IWL<29612> A_IWL<29611> A_IWL<29610> A_IWL<29609> A_IWL<29608> A_IWL<29607> A_IWL<29606> A_IWL<29605> A_IWL<29604> A_IWL<29603> A_IWL<29602> A_IWL<29601> A_IWL<29600> A_IWL<29599> A_IWL<29598> A_IWL<29597> A_IWL<29596> A_IWL<29595> A_IWL<29594> A_IWL<29593> A_IWL<29592> A_IWL<29591> A_IWL<29590> A_IWL<29589> A_IWL<29588> A_IWL<29587> A_IWL<29586> A_IWL<29585> A_IWL<29584> A_IWL<29583> A_IWL<29582> A_IWL<29581> A_IWL<29580> A_IWL<29579> A_IWL<29578> A_IWL<29577> A_IWL<29576> A_IWL<29575> A_IWL<29574> A_IWL<29573> A_IWL<29572> A_IWL<29571> A_IWL<29570> A_IWL<29569> A_IWL<29568> A_IWL<29567> A_IWL<29566> A_IWL<29565> A_IWL<29564> A_IWL<29563> A_IWL<29562> A_IWL<29561> A_IWL<29560> A_IWL<29559> A_IWL<29558> A_IWL<29557> A_IWL<29556> A_IWL<29555> A_IWL<29554> A_IWL<29553> A_IWL<29552> A_IWL<29551> A_IWL<29550> A_IWL<29549> A_IWL<29548> A_IWL<29547> A_IWL<29546> A_IWL<29545> A_IWL<29544> A_IWL<29543> A_IWL<29542> A_IWL<29541> A_IWL<29540> A_IWL<29539> A_IWL<29538> A_IWL<29537> A_IWL<29536> A_IWL<29535> A_IWL<29534> A_IWL<29533> A_IWL<29532> A_IWL<29531> A_IWL<29530> A_IWL<29529> A_IWL<29528> A_IWL<29527> A_IWL<29526> A_IWL<29525> A_IWL<29524> A_IWL<29523> A_IWL<29522> A_IWL<29521> A_IWL<29520> A_IWL<29519> A_IWL<29518> A_IWL<29517> A_IWL<29516> A_IWL<29515> A_IWL<29514> A_IWL<29513> A_IWL<29512> A_IWL<29511> A_IWL<29510> A_IWL<29509> A_IWL<29508> A_IWL<29507> A_IWL<29506> A_IWL<29505> A_IWL<29504> A_IWL<29503> A_IWL<29502> A_IWL<29501> A_IWL<29500> A_IWL<29499> A_IWL<29498> A_IWL<29497> A_IWL<29496> A_IWL<29495> A_IWL<29494> A_IWL<29493> A_IWL<29492> A_IWL<29491> A_IWL<29490> A_IWL<29489> A_IWL<29488> A_IWL<29487> A_IWL<29486> A_IWL<29485> A_IWL<29484> A_IWL<29483> A_IWL<29482> A_IWL<29481> A_IWL<29480> A_IWL<29479> A_IWL<29478> A_IWL<29477> A_IWL<29476> A_IWL<29475> A_IWL<29474> A_IWL<29473> A_IWL<29472> A_IWL<29471> A_IWL<29470> A_IWL<29469> A_IWL<29468> A_IWL<29467> A_IWL<29466> A_IWL<29465> A_IWL<29464> A_IWL<29463> A_IWL<29462> A_IWL<29461> A_IWL<29460> A_IWL<29459> A_IWL<29458> A_IWL<29457> A_IWL<29456> A_IWL<29455> A_IWL<29454> A_IWL<29453> A_IWL<29452> A_IWL<29451> A_IWL<29450> A_IWL<29449> A_IWL<29448> A_IWL<29447> A_IWL<29446> A_IWL<29445> A_IWL<29444> A_IWL<29443> A_IWL<29442> A_IWL<29441> A_IWL<29440> A_IWL<29439> A_IWL<29438> A_IWL<29437> A_IWL<29436> A_IWL<29435> A_IWL<29434> A_IWL<29433> A_IWL<29432> A_IWL<29431> A_IWL<29430> A_IWL<29429> A_IWL<29428> A_IWL<29427> A_IWL<29426> A_IWL<29425> A_IWL<29424> A_IWL<29423> A_IWL<29422> A_IWL<29421> A_IWL<29420> A_IWL<29419> A_IWL<29418> A_IWL<29417> A_IWL<29416> A_IWL<29415> A_IWL<29414> A_IWL<29413> A_IWL<29412> A_IWL<29411> A_IWL<29410> A_IWL<29409> A_IWL<29408> A_IWL<29407> A_IWL<29406> A_IWL<29405> A_IWL<29404> A_IWL<29403> A_IWL<29402> A_IWL<29401> A_IWL<29400> A_IWL<29399> A_IWL<29398> A_IWL<29397> A_IWL<29396> A_IWL<29395> A_IWL<29394> A_IWL<29393> A_IWL<29392> A_IWL<29391> A_IWL<29390> A_IWL<29389> A_IWL<29388> A_IWL<29387> A_IWL<29386> A_IWL<29385> A_IWL<29384> A_IWL<29383> A_IWL<29382> A_IWL<29381> A_IWL<29380> A_IWL<29379> A_IWL<29378> A_IWL<29377> A_IWL<29376> A_IWL<29375> A_IWL<29374> A_IWL<29373> A_IWL<29372> A_IWL<29371> A_IWL<29370> A_IWL<29369> A_IWL<29368> A_IWL<29367> A_IWL<29366> A_IWL<29365> A_IWL<29364> A_IWL<29363> A_IWL<29362> A_IWL<29361> A_IWL<29360> A_IWL<29359> A_IWL<29358> A_IWL<29357> A_IWL<29356> A_IWL<29355> A_IWL<29354> A_IWL<29353> A_IWL<29352> A_IWL<29351> A_IWL<29350> A_IWL<29349> A_IWL<29348> A_IWL<29347> A_IWL<29346> A_IWL<29345> A_IWL<29344> A_IWL<29343> A_IWL<29342> A_IWL<29341> A_IWL<29340> A_IWL<29339> A_IWL<29338> A_IWL<29337> A_IWL<29336> A_IWL<29335> A_IWL<29334> A_IWL<29333> A_IWL<29332> A_IWL<29331> A_IWL<29330> A_IWL<29329> A_IWL<29328> A_IWL<29327> A_IWL<29326> A_IWL<29325> A_IWL<29324> A_IWL<29323> A_IWL<29322> A_IWL<29321> A_IWL<29320> A_IWL<29319> A_IWL<29318> A_IWL<29317> A_IWL<29316> A_IWL<29315> A_IWL<29314> A_IWL<29313> A_IWL<29312> A_IWL<29311> A_IWL<29310> A_IWL<29309> A_IWL<29308> A_IWL<29307> A_IWL<29306> A_IWL<29305> A_IWL<29304> A_IWL<29303> A_IWL<29302> A_IWL<29301> A_IWL<29300> A_IWL<29299> A_IWL<29298> A_IWL<29297> A_IWL<29296> A_IWL<29295> A_IWL<29294> A_IWL<29293> A_IWL<29292> A_IWL<29291> A_IWL<29290> A_IWL<29289> A_IWL<29288> A_IWL<29287> A_IWL<29286> A_IWL<29285> A_IWL<29284> A_IWL<29283> A_IWL<29282> A_IWL<29281> A_IWL<29280> A_IWL<29279> A_IWL<29278> A_IWL<29277> A_IWL<29276> A_IWL<29275> A_IWL<29274> A_IWL<29273> A_IWL<29272> A_IWL<29271> A_IWL<29270> A_IWL<29269> A_IWL<29268> A_IWL<29267> A_IWL<29266> A_IWL<29265> A_IWL<29264> A_IWL<29263> A_IWL<29262> A_IWL<29261> A_IWL<29260> A_IWL<29259> A_IWL<29258> A_IWL<29257> A_IWL<29256> A_IWL<29255> A_IWL<29254> A_IWL<29253> A_IWL<29252> A_IWL<29251> A_IWL<29250> A_IWL<29249> A_IWL<29248> A_IWL<29247> A_IWL<29246> A_IWL<29245> A_IWL<29244> A_IWL<29243> A_IWL<29242> A_IWL<29241> A_IWL<29240> A_IWL<29239> A_IWL<29238> A_IWL<29237> A_IWL<29236> A_IWL<29235> A_IWL<29234> A_IWL<29233> A_IWL<29232> A_IWL<29231> A_IWL<29230> A_IWL<29229> A_IWL<29228> A_IWL<29227> A_IWL<29226> A_IWL<29225> A_IWL<29224> A_IWL<29223> A_IWL<29222> A_IWL<29221> A_IWL<29220> A_IWL<29219> A_IWL<29218> A_IWL<29217> A_IWL<29216> A_IWL<29215> A_IWL<29214> A_IWL<29213> A_IWL<29212> A_IWL<29211> A_IWL<29210> A_IWL<29209> A_IWL<29208> A_IWL<29207> A_IWL<29206> A_IWL<29205> A_IWL<29204> A_IWL<29203> A_IWL<29202> A_IWL<29201> A_IWL<29200> A_IWL<29199> A_IWL<29198> A_IWL<29197> A_IWL<29196> A_IWL<29195> A_IWL<29194> A_IWL<29193> A_IWL<29192> A_IWL<29191> A_IWL<29190> A_IWL<29189> A_IWL<29188> A_IWL<29187> A_IWL<29186> A_IWL<29185> A_IWL<29184> A_IWL<30207> A_IWL<30206> A_IWL<30205> A_IWL<30204> A_IWL<30203> A_IWL<30202> A_IWL<30201> A_IWL<30200> A_IWL<30199> A_IWL<30198> A_IWL<30197> A_IWL<30196> A_IWL<30195> A_IWL<30194> A_IWL<30193> A_IWL<30192> A_IWL<30191> A_IWL<30190> A_IWL<30189> A_IWL<30188> A_IWL<30187> A_IWL<30186> A_IWL<30185> A_IWL<30184> A_IWL<30183> A_IWL<30182> A_IWL<30181> A_IWL<30180> A_IWL<30179> A_IWL<30178> A_IWL<30177> A_IWL<30176> A_IWL<30175> A_IWL<30174> A_IWL<30173> A_IWL<30172> A_IWL<30171> A_IWL<30170> A_IWL<30169> A_IWL<30168> A_IWL<30167> A_IWL<30166> A_IWL<30165> A_IWL<30164> A_IWL<30163> A_IWL<30162> A_IWL<30161> A_IWL<30160> A_IWL<30159> A_IWL<30158> A_IWL<30157> A_IWL<30156> A_IWL<30155> A_IWL<30154> A_IWL<30153> A_IWL<30152> A_IWL<30151> A_IWL<30150> A_IWL<30149> A_IWL<30148> A_IWL<30147> A_IWL<30146> A_IWL<30145> A_IWL<30144> A_IWL<30143> A_IWL<30142> A_IWL<30141> A_IWL<30140> A_IWL<30139> A_IWL<30138> A_IWL<30137> A_IWL<30136> A_IWL<30135> A_IWL<30134> A_IWL<30133> A_IWL<30132> A_IWL<30131> A_IWL<30130> A_IWL<30129> A_IWL<30128> A_IWL<30127> A_IWL<30126> A_IWL<30125> A_IWL<30124> A_IWL<30123> A_IWL<30122> A_IWL<30121> A_IWL<30120> A_IWL<30119> A_IWL<30118> A_IWL<30117> A_IWL<30116> A_IWL<30115> A_IWL<30114> A_IWL<30113> A_IWL<30112> A_IWL<30111> A_IWL<30110> A_IWL<30109> A_IWL<30108> A_IWL<30107> A_IWL<30106> A_IWL<30105> A_IWL<30104> A_IWL<30103> A_IWL<30102> A_IWL<30101> A_IWL<30100> A_IWL<30099> A_IWL<30098> A_IWL<30097> A_IWL<30096> A_IWL<30095> A_IWL<30094> A_IWL<30093> A_IWL<30092> A_IWL<30091> A_IWL<30090> A_IWL<30089> A_IWL<30088> A_IWL<30087> A_IWL<30086> A_IWL<30085> A_IWL<30084> A_IWL<30083> A_IWL<30082> A_IWL<30081> A_IWL<30080> A_IWL<30079> A_IWL<30078> A_IWL<30077> A_IWL<30076> A_IWL<30075> A_IWL<30074> A_IWL<30073> A_IWL<30072> A_IWL<30071> A_IWL<30070> A_IWL<30069> A_IWL<30068> A_IWL<30067> A_IWL<30066> A_IWL<30065> A_IWL<30064> A_IWL<30063> A_IWL<30062> A_IWL<30061> A_IWL<30060> A_IWL<30059> A_IWL<30058> A_IWL<30057> A_IWL<30056> A_IWL<30055> A_IWL<30054> A_IWL<30053> A_IWL<30052> A_IWL<30051> A_IWL<30050> A_IWL<30049> A_IWL<30048> A_IWL<30047> A_IWL<30046> A_IWL<30045> A_IWL<30044> A_IWL<30043> A_IWL<30042> A_IWL<30041> A_IWL<30040> A_IWL<30039> A_IWL<30038> A_IWL<30037> A_IWL<30036> A_IWL<30035> A_IWL<30034> A_IWL<30033> A_IWL<30032> A_IWL<30031> A_IWL<30030> A_IWL<30029> A_IWL<30028> A_IWL<30027> A_IWL<30026> A_IWL<30025> A_IWL<30024> A_IWL<30023> A_IWL<30022> A_IWL<30021> A_IWL<30020> A_IWL<30019> A_IWL<30018> A_IWL<30017> A_IWL<30016> A_IWL<30015> A_IWL<30014> A_IWL<30013> A_IWL<30012> A_IWL<30011> A_IWL<30010> A_IWL<30009> A_IWL<30008> A_IWL<30007> A_IWL<30006> A_IWL<30005> A_IWL<30004> A_IWL<30003> A_IWL<30002> A_IWL<30001> A_IWL<30000> A_IWL<29999> A_IWL<29998> A_IWL<29997> A_IWL<29996> A_IWL<29995> A_IWL<29994> A_IWL<29993> A_IWL<29992> A_IWL<29991> A_IWL<29990> A_IWL<29989> A_IWL<29988> A_IWL<29987> A_IWL<29986> A_IWL<29985> A_IWL<29984> A_IWL<29983> A_IWL<29982> A_IWL<29981> A_IWL<29980> A_IWL<29979> A_IWL<29978> A_IWL<29977> A_IWL<29976> A_IWL<29975> A_IWL<29974> A_IWL<29973> A_IWL<29972> A_IWL<29971> A_IWL<29970> A_IWL<29969> A_IWL<29968> A_IWL<29967> A_IWL<29966> A_IWL<29965> A_IWL<29964> A_IWL<29963> A_IWL<29962> A_IWL<29961> A_IWL<29960> A_IWL<29959> A_IWL<29958> A_IWL<29957> A_IWL<29956> A_IWL<29955> A_IWL<29954> A_IWL<29953> A_IWL<29952> A_IWL<29951> A_IWL<29950> A_IWL<29949> A_IWL<29948> A_IWL<29947> A_IWL<29946> A_IWL<29945> A_IWL<29944> A_IWL<29943> A_IWL<29942> A_IWL<29941> A_IWL<29940> A_IWL<29939> A_IWL<29938> A_IWL<29937> A_IWL<29936> A_IWL<29935> A_IWL<29934> A_IWL<29933> A_IWL<29932> A_IWL<29931> A_IWL<29930> A_IWL<29929> A_IWL<29928> A_IWL<29927> A_IWL<29926> A_IWL<29925> A_IWL<29924> A_IWL<29923> A_IWL<29922> A_IWL<29921> A_IWL<29920> A_IWL<29919> A_IWL<29918> A_IWL<29917> A_IWL<29916> A_IWL<29915> A_IWL<29914> A_IWL<29913> A_IWL<29912> A_IWL<29911> A_IWL<29910> A_IWL<29909> A_IWL<29908> A_IWL<29907> A_IWL<29906> A_IWL<29905> A_IWL<29904> A_IWL<29903> A_IWL<29902> A_IWL<29901> A_IWL<29900> A_IWL<29899> A_IWL<29898> A_IWL<29897> A_IWL<29896> A_IWL<29895> A_IWL<29894> A_IWL<29893> A_IWL<29892> A_IWL<29891> A_IWL<29890> A_IWL<29889> A_IWL<29888> A_IWL<29887> A_IWL<29886> A_IWL<29885> A_IWL<29884> A_IWL<29883> A_IWL<29882> A_IWL<29881> A_IWL<29880> A_IWL<29879> A_IWL<29878> A_IWL<29877> A_IWL<29876> A_IWL<29875> A_IWL<29874> A_IWL<29873> A_IWL<29872> A_IWL<29871> A_IWL<29870> A_IWL<29869> A_IWL<29868> A_IWL<29867> A_IWL<29866> A_IWL<29865> A_IWL<29864> A_IWL<29863> A_IWL<29862> A_IWL<29861> A_IWL<29860> A_IWL<29859> A_IWL<29858> A_IWL<29857> A_IWL<29856> A_IWL<29855> A_IWL<29854> A_IWL<29853> A_IWL<29852> A_IWL<29851> A_IWL<29850> A_IWL<29849> A_IWL<29848> A_IWL<29847> A_IWL<29846> A_IWL<29845> A_IWL<29844> A_IWL<29843> A_IWL<29842> A_IWL<29841> A_IWL<29840> A_IWL<29839> A_IWL<29838> A_IWL<29837> A_IWL<29836> A_IWL<29835> A_IWL<29834> A_IWL<29833> A_IWL<29832> A_IWL<29831> A_IWL<29830> A_IWL<29829> A_IWL<29828> A_IWL<29827> A_IWL<29826> A_IWL<29825> A_IWL<29824> A_IWL<29823> A_IWL<29822> A_IWL<29821> A_IWL<29820> A_IWL<29819> A_IWL<29818> A_IWL<29817> A_IWL<29816> A_IWL<29815> A_IWL<29814> A_IWL<29813> A_IWL<29812> A_IWL<29811> A_IWL<29810> A_IWL<29809> A_IWL<29808> A_IWL<29807> A_IWL<29806> A_IWL<29805> A_IWL<29804> A_IWL<29803> A_IWL<29802> A_IWL<29801> A_IWL<29800> A_IWL<29799> A_IWL<29798> A_IWL<29797> A_IWL<29796> A_IWL<29795> A_IWL<29794> A_IWL<29793> A_IWL<29792> A_IWL<29791> A_IWL<29790> A_IWL<29789> A_IWL<29788> A_IWL<29787> A_IWL<29786> A_IWL<29785> A_IWL<29784> A_IWL<29783> A_IWL<29782> A_IWL<29781> A_IWL<29780> A_IWL<29779> A_IWL<29778> A_IWL<29777> A_IWL<29776> A_IWL<29775> A_IWL<29774> A_IWL<29773> A_IWL<29772> A_IWL<29771> A_IWL<29770> A_IWL<29769> A_IWL<29768> A_IWL<29767> A_IWL<29766> A_IWL<29765> A_IWL<29764> A_IWL<29763> A_IWL<29762> A_IWL<29761> A_IWL<29760> A_IWL<29759> A_IWL<29758> A_IWL<29757> A_IWL<29756> A_IWL<29755> A_IWL<29754> A_IWL<29753> A_IWL<29752> A_IWL<29751> A_IWL<29750> A_IWL<29749> A_IWL<29748> A_IWL<29747> A_IWL<29746> A_IWL<29745> A_IWL<29744> A_IWL<29743> A_IWL<29742> A_IWL<29741> A_IWL<29740> A_IWL<29739> A_IWL<29738> A_IWL<29737> A_IWL<29736> A_IWL<29735> A_IWL<29734> A_IWL<29733> A_IWL<29732> A_IWL<29731> A_IWL<29730> A_IWL<29729> A_IWL<29728> A_IWL<29727> A_IWL<29726> A_IWL<29725> A_IWL<29724> A_IWL<29723> A_IWL<29722> A_IWL<29721> A_IWL<29720> A_IWL<29719> A_IWL<29718> A_IWL<29717> A_IWL<29716> A_IWL<29715> A_IWL<29714> A_IWL<29713> A_IWL<29712> A_IWL<29711> A_IWL<29710> A_IWL<29709> A_IWL<29708> A_IWL<29707> A_IWL<29706> A_IWL<29705> A_IWL<29704> A_IWL<29703> A_IWL<29702> A_IWL<29701> A_IWL<29700> A_IWL<29699> A_IWL<29698> A_IWL<29697> A_IWL<29696> VDD_CORE VSS / RM_IHPSG13_8192x32_c4_1P_COLUMN_pcell_0 +XCOL<57> A_BLC<115> A_BLC<114> A_BLC_TOP<115> A_BLC_TOP<114> A_BLT<115> A_BLT<114> A_BLT_TOP<115> A_BLT_TOP<114> A_IWL<29183> A_IWL<29182> A_IWL<29181> A_IWL<29180> A_IWL<29179> A_IWL<29178> A_IWL<29177> A_IWL<29176> A_IWL<29175> A_IWL<29174> A_IWL<29173> A_IWL<29172> A_IWL<29171> A_IWL<29170> A_IWL<29169> A_IWL<29168> A_IWL<29167> A_IWL<29166> A_IWL<29165> A_IWL<29164> A_IWL<29163> A_IWL<29162> A_IWL<29161> A_IWL<29160> A_IWL<29159> A_IWL<29158> A_IWL<29157> A_IWL<29156> A_IWL<29155> A_IWL<29154> A_IWL<29153> A_IWL<29152> A_IWL<29151> A_IWL<29150> A_IWL<29149> A_IWL<29148> A_IWL<29147> A_IWL<29146> A_IWL<29145> A_IWL<29144> A_IWL<29143> A_IWL<29142> A_IWL<29141> A_IWL<29140> A_IWL<29139> A_IWL<29138> A_IWL<29137> A_IWL<29136> A_IWL<29135> A_IWL<29134> A_IWL<29133> A_IWL<29132> A_IWL<29131> A_IWL<29130> A_IWL<29129> A_IWL<29128> A_IWL<29127> A_IWL<29126> A_IWL<29125> A_IWL<29124> A_IWL<29123> A_IWL<29122> A_IWL<29121> A_IWL<29120> A_IWL<29119> A_IWL<29118> A_IWL<29117> A_IWL<29116> A_IWL<29115> A_IWL<29114> A_IWL<29113> A_IWL<29112> A_IWL<29111> A_IWL<29110> A_IWL<29109> A_IWL<29108> A_IWL<29107> A_IWL<29106> A_IWL<29105> A_IWL<29104> A_IWL<29103> A_IWL<29102> A_IWL<29101> A_IWL<29100> A_IWL<29099> A_IWL<29098> A_IWL<29097> A_IWL<29096> A_IWL<29095> A_IWL<29094> A_IWL<29093> A_IWL<29092> A_IWL<29091> A_IWL<29090> A_IWL<29089> A_IWL<29088> A_IWL<29087> A_IWL<29086> A_IWL<29085> A_IWL<29084> A_IWL<29083> A_IWL<29082> A_IWL<29081> A_IWL<29080> A_IWL<29079> A_IWL<29078> A_IWL<29077> A_IWL<29076> A_IWL<29075> A_IWL<29074> A_IWL<29073> A_IWL<29072> A_IWL<29071> A_IWL<29070> A_IWL<29069> A_IWL<29068> A_IWL<29067> A_IWL<29066> A_IWL<29065> A_IWL<29064> A_IWL<29063> A_IWL<29062> A_IWL<29061> A_IWL<29060> A_IWL<29059> A_IWL<29058> A_IWL<29057> A_IWL<29056> A_IWL<29055> A_IWL<29054> A_IWL<29053> A_IWL<29052> A_IWL<29051> A_IWL<29050> A_IWL<29049> A_IWL<29048> A_IWL<29047> A_IWL<29046> A_IWL<29045> A_IWL<29044> A_IWL<29043> A_IWL<29042> A_IWL<29041> A_IWL<29040> A_IWL<29039> A_IWL<29038> A_IWL<29037> A_IWL<29036> A_IWL<29035> A_IWL<29034> A_IWL<29033> A_IWL<29032> A_IWL<29031> A_IWL<29030> A_IWL<29029> A_IWL<29028> A_IWL<29027> A_IWL<29026> A_IWL<29025> A_IWL<29024> A_IWL<29023> A_IWL<29022> A_IWL<29021> A_IWL<29020> A_IWL<29019> A_IWL<29018> A_IWL<29017> A_IWL<29016> A_IWL<29015> A_IWL<29014> A_IWL<29013> A_IWL<29012> A_IWL<29011> A_IWL<29010> A_IWL<29009> A_IWL<29008> A_IWL<29007> A_IWL<29006> A_IWL<29005> A_IWL<29004> A_IWL<29003> A_IWL<29002> A_IWL<29001> A_IWL<29000> A_IWL<28999> A_IWL<28998> A_IWL<28997> A_IWL<28996> A_IWL<28995> A_IWL<28994> A_IWL<28993> A_IWL<28992> A_IWL<28991> A_IWL<28990> A_IWL<28989> A_IWL<28988> A_IWL<28987> A_IWL<28986> A_IWL<28985> A_IWL<28984> A_IWL<28983> A_IWL<28982> A_IWL<28981> A_IWL<28980> A_IWL<28979> A_IWL<28978> A_IWL<28977> A_IWL<28976> A_IWL<28975> A_IWL<28974> A_IWL<28973> A_IWL<28972> A_IWL<28971> A_IWL<28970> A_IWL<28969> A_IWL<28968> A_IWL<28967> A_IWL<28966> A_IWL<28965> A_IWL<28964> A_IWL<28963> A_IWL<28962> A_IWL<28961> A_IWL<28960> A_IWL<28959> A_IWL<28958> A_IWL<28957> A_IWL<28956> A_IWL<28955> A_IWL<28954> A_IWL<28953> A_IWL<28952> A_IWL<28951> A_IWL<28950> A_IWL<28949> A_IWL<28948> A_IWL<28947> A_IWL<28946> A_IWL<28945> A_IWL<28944> A_IWL<28943> A_IWL<28942> A_IWL<28941> A_IWL<28940> A_IWL<28939> A_IWL<28938> A_IWL<28937> A_IWL<28936> A_IWL<28935> A_IWL<28934> A_IWL<28933> A_IWL<28932> A_IWL<28931> A_IWL<28930> A_IWL<28929> A_IWL<28928> A_IWL<28927> A_IWL<28926> A_IWL<28925> A_IWL<28924> A_IWL<28923> A_IWL<28922> A_IWL<28921> A_IWL<28920> A_IWL<28919> A_IWL<28918> A_IWL<28917> A_IWL<28916> A_IWL<28915> A_IWL<28914> A_IWL<28913> A_IWL<28912> A_IWL<28911> A_IWL<28910> A_IWL<28909> A_IWL<28908> A_IWL<28907> A_IWL<28906> A_IWL<28905> A_IWL<28904> A_IWL<28903> A_IWL<28902> A_IWL<28901> A_IWL<28900> A_IWL<28899> A_IWL<28898> A_IWL<28897> A_IWL<28896> A_IWL<28895> A_IWL<28894> A_IWL<28893> A_IWL<28892> A_IWL<28891> A_IWL<28890> A_IWL<28889> A_IWL<28888> A_IWL<28887> A_IWL<28886> A_IWL<28885> A_IWL<28884> A_IWL<28883> A_IWL<28882> A_IWL<28881> A_IWL<28880> A_IWL<28879> A_IWL<28878> A_IWL<28877> A_IWL<28876> A_IWL<28875> A_IWL<28874> A_IWL<28873> A_IWL<28872> A_IWL<28871> A_IWL<28870> A_IWL<28869> A_IWL<28868> A_IWL<28867> A_IWL<28866> A_IWL<28865> A_IWL<28864> A_IWL<28863> A_IWL<28862> A_IWL<28861> A_IWL<28860> A_IWL<28859> A_IWL<28858> A_IWL<28857> A_IWL<28856> A_IWL<28855> A_IWL<28854> A_IWL<28853> A_IWL<28852> A_IWL<28851> A_IWL<28850> A_IWL<28849> A_IWL<28848> A_IWL<28847> A_IWL<28846> A_IWL<28845> A_IWL<28844> A_IWL<28843> A_IWL<28842> A_IWL<28841> A_IWL<28840> A_IWL<28839> A_IWL<28838> A_IWL<28837> A_IWL<28836> A_IWL<28835> A_IWL<28834> A_IWL<28833> A_IWL<28832> A_IWL<28831> A_IWL<28830> A_IWL<28829> A_IWL<28828> A_IWL<28827> A_IWL<28826> A_IWL<28825> A_IWL<28824> A_IWL<28823> A_IWL<28822> A_IWL<28821> A_IWL<28820> A_IWL<28819> A_IWL<28818> A_IWL<28817> A_IWL<28816> A_IWL<28815> A_IWL<28814> A_IWL<28813> A_IWL<28812> A_IWL<28811> A_IWL<28810> A_IWL<28809> A_IWL<28808> A_IWL<28807> A_IWL<28806> A_IWL<28805> A_IWL<28804> A_IWL<28803> A_IWL<28802> A_IWL<28801> A_IWL<28800> A_IWL<28799> A_IWL<28798> A_IWL<28797> A_IWL<28796> A_IWL<28795> A_IWL<28794> A_IWL<28793> A_IWL<28792> A_IWL<28791> A_IWL<28790> A_IWL<28789> A_IWL<28788> A_IWL<28787> A_IWL<28786> A_IWL<28785> A_IWL<28784> A_IWL<28783> A_IWL<28782> A_IWL<28781> A_IWL<28780> A_IWL<28779> A_IWL<28778> A_IWL<28777> A_IWL<28776> A_IWL<28775> A_IWL<28774> A_IWL<28773> A_IWL<28772> A_IWL<28771> A_IWL<28770> A_IWL<28769> A_IWL<28768> A_IWL<28767> A_IWL<28766> A_IWL<28765> A_IWL<28764> A_IWL<28763> A_IWL<28762> A_IWL<28761> A_IWL<28760> A_IWL<28759> A_IWL<28758> A_IWL<28757> A_IWL<28756> A_IWL<28755> A_IWL<28754> A_IWL<28753> A_IWL<28752> A_IWL<28751> A_IWL<28750> A_IWL<28749> A_IWL<28748> A_IWL<28747> A_IWL<28746> A_IWL<28745> A_IWL<28744> A_IWL<28743> A_IWL<28742> A_IWL<28741> A_IWL<28740> A_IWL<28739> A_IWL<28738> A_IWL<28737> A_IWL<28736> A_IWL<28735> A_IWL<28734> A_IWL<28733> A_IWL<28732> A_IWL<28731> A_IWL<28730> A_IWL<28729> A_IWL<28728> A_IWL<28727> A_IWL<28726> A_IWL<28725> A_IWL<28724> A_IWL<28723> A_IWL<28722> A_IWL<28721> A_IWL<28720> A_IWL<28719> A_IWL<28718> A_IWL<28717> A_IWL<28716> A_IWL<28715> A_IWL<28714> A_IWL<28713> A_IWL<28712> A_IWL<28711> A_IWL<28710> A_IWL<28709> A_IWL<28708> A_IWL<28707> A_IWL<28706> A_IWL<28705> A_IWL<28704> A_IWL<28703> A_IWL<28702> A_IWL<28701> A_IWL<28700> A_IWL<28699> A_IWL<28698> A_IWL<28697> A_IWL<28696> A_IWL<28695> A_IWL<28694> A_IWL<28693> A_IWL<28692> A_IWL<28691> A_IWL<28690> A_IWL<28689> A_IWL<28688> A_IWL<28687> A_IWL<28686> A_IWL<28685> A_IWL<28684> A_IWL<28683> A_IWL<28682> A_IWL<28681> A_IWL<28680> A_IWL<28679> A_IWL<28678> A_IWL<28677> A_IWL<28676> A_IWL<28675> A_IWL<28674> A_IWL<28673> A_IWL<28672> A_IWL<29695> A_IWL<29694> A_IWL<29693> A_IWL<29692> A_IWL<29691> A_IWL<29690> A_IWL<29689> A_IWL<29688> A_IWL<29687> A_IWL<29686> A_IWL<29685> A_IWL<29684> A_IWL<29683> A_IWL<29682> A_IWL<29681> A_IWL<29680> A_IWL<29679> A_IWL<29678> A_IWL<29677> A_IWL<29676> A_IWL<29675> A_IWL<29674> A_IWL<29673> A_IWL<29672> A_IWL<29671> A_IWL<29670> A_IWL<29669> A_IWL<29668> A_IWL<29667> A_IWL<29666> A_IWL<29665> A_IWL<29664> A_IWL<29663> A_IWL<29662> A_IWL<29661> A_IWL<29660> A_IWL<29659> A_IWL<29658> A_IWL<29657> A_IWL<29656> A_IWL<29655> A_IWL<29654> A_IWL<29653> A_IWL<29652> A_IWL<29651> A_IWL<29650> A_IWL<29649> A_IWL<29648> A_IWL<29647> A_IWL<29646> A_IWL<29645> A_IWL<29644> A_IWL<29643> A_IWL<29642> A_IWL<29641> A_IWL<29640> A_IWL<29639> A_IWL<29638> A_IWL<29637> A_IWL<29636> A_IWL<29635> A_IWL<29634> A_IWL<29633> A_IWL<29632> A_IWL<29631> A_IWL<29630> A_IWL<29629> A_IWL<29628> A_IWL<29627> A_IWL<29626> A_IWL<29625> A_IWL<29624> A_IWL<29623> A_IWL<29622> A_IWL<29621> A_IWL<29620> A_IWL<29619> A_IWL<29618> A_IWL<29617> A_IWL<29616> A_IWL<29615> A_IWL<29614> A_IWL<29613> A_IWL<29612> A_IWL<29611> A_IWL<29610> A_IWL<29609> A_IWL<29608> A_IWL<29607> A_IWL<29606> A_IWL<29605> A_IWL<29604> A_IWL<29603> A_IWL<29602> A_IWL<29601> A_IWL<29600> A_IWL<29599> A_IWL<29598> A_IWL<29597> A_IWL<29596> A_IWL<29595> A_IWL<29594> A_IWL<29593> A_IWL<29592> A_IWL<29591> A_IWL<29590> A_IWL<29589> A_IWL<29588> A_IWL<29587> A_IWL<29586> A_IWL<29585> A_IWL<29584> A_IWL<29583> A_IWL<29582> A_IWL<29581> A_IWL<29580> A_IWL<29579> A_IWL<29578> A_IWL<29577> A_IWL<29576> A_IWL<29575> A_IWL<29574> A_IWL<29573> A_IWL<29572> A_IWL<29571> A_IWL<29570> A_IWL<29569> A_IWL<29568> A_IWL<29567> A_IWL<29566> A_IWL<29565> A_IWL<29564> A_IWL<29563> A_IWL<29562> A_IWL<29561> A_IWL<29560> A_IWL<29559> A_IWL<29558> A_IWL<29557> A_IWL<29556> A_IWL<29555> A_IWL<29554> A_IWL<29553> A_IWL<29552> A_IWL<29551> A_IWL<29550> A_IWL<29549> A_IWL<29548> A_IWL<29547> A_IWL<29546> A_IWL<29545> A_IWL<29544> A_IWL<29543> A_IWL<29542> A_IWL<29541> A_IWL<29540> A_IWL<29539> A_IWL<29538> A_IWL<29537> A_IWL<29536> A_IWL<29535> A_IWL<29534> A_IWL<29533> A_IWL<29532> A_IWL<29531> A_IWL<29530> A_IWL<29529> A_IWL<29528> A_IWL<29527> A_IWL<29526> A_IWL<29525> A_IWL<29524> A_IWL<29523> A_IWL<29522> A_IWL<29521> A_IWL<29520> A_IWL<29519> A_IWL<29518> A_IWL<29517> A_IWL<29516> A_IWL<29515> A_IWL<29514> A_IWL<29513> A_IWL<29512> A_IWL<29511> A_IWL<29510> A_IWL<29509> A_IWL<29508> A_IWL<29507> A_IWL<29506> A_IWL<29505> A_IWL<29504> A_IWL<29503> A_IWL<29502> A_IWL<29501> A_IWL<29500> A_IWL<29499> A_IWL<29498> A_IWL<29497> A_IWL<29496> A_IWL<29495> A_IWL<29494> A_IWL<29493> A_IWL<29492> A_IWL<29491> A_IWL<29490> A_IWL<29489> A_IWL<29488> A_IWL<29487> A_IWL<29486> A_IWL<29485> A_IWL<29484> A_IWL<29483> A_IWL<29482> A_IWL<29481> A_IWL<29480> A_IWL<29479> A_IWL<29478> A_IWL<29477> A_IWL<29476> A_IWL<29475> A_IWL<29474> A_IWL<29473> A_IWL<29472> A_IWL<29471> A_IWL<29470> A_IWL<29469> A_IWL<29468> A_IWL<29467> A_IWL<29466> A_IWL<29465> A_IWL<29464> A_IWL<29463> A_IWL<29462> A_IWL<29461> A_IWL<29460> A_IWL<29459> A_IWL<29458> A_IWL<29457> A_IWL<29456> A_IWL<29455> A_IWL<29454> A_IWL<29453> A_IWL<29452> A_IWL<29451> A_IWL<29450> A_IWL<29449> A_IWL<29448> A_IWL<29447> A_IWL<29446> A_IWL<29445> A_IWL<29444> A_IWL<29443> A_IWL<29442> A_IWL<29441> A_IWL<29440> A_IWL<29439> A_IWL<29438> A_IWL<29437> A_IWL<29436> A_IWL<29435> A_IWL<29434> A_IWL<29433> A_IWL<29432> A_IWL<29431> A_IWL<29430> A_IWL<29429> A_IWL<29428> A_IWL<29427> A_IWL<29426> A_IWL<29425> A_IWL<29424> A_IWL<29423> A_IWL<29422> A_IWL<29421> A_IWL<29420> A_IWL<29419> A_IWL<29418> A_IWL<29417> A_IWL<29416> A_IWL<29415> A_IWL<29414> A_IWL<29413> A_IWL<29412> A_IWL<29411> A_IWL<29410> A_IWL<29409> A_IWL<29408> A_IWL<29407> A_IWL<29406> A_IWL<29405> A_IWL<29404> A_IWL<29403> A_IWL<29402> A_IWL<29401> A_IWL<29400> A_IWL<29399> A_IWL<29398> A_IWL<29397> A_IWL<29396> A_IWL<29395> A_IWL<29394> A_IWL<29393> A_IWL<29392> A_IWL<29391> A_IWL<29390> A_IWL<29389> A_IWL<29388> A_IWL<29387> A_IWL<29386> A_IWL<29385> A_IWL<29384> A_IWL<29383> A_IWL<29382> A_IWL<29381> A_IWL<29380> A_IWL<29379> A_IWL<29378> A_IWL<29377> A_IWL<29376> A_IWL<29375> A_IWL<29374> A_IWL<29373> A_IWL<29372> A_IWL<29371> A_IWL<29370> A_IWL<29369> A_IWL<29368> A_IWL<29367> A_IWL<29366> A_IWL<29365> A_IWL<29364> A_IWL<29363> A_IWL<29362> A_IWL<29361> A_IWL<29360> A_IWL<29359> A_IWL<29358> A_IWL<29357> A_IWL<29356> A_IWL<29355> A_IWL<29354> A_IWL<29353> A_IWL<29352> A_IWL<29351> A_IWL<29350> A_IWL<29349> A_IWL<29348> A_IWL<29347> A_IWL<29346> A_IWL<29345> A_IWL<29344> A_IWL<29343> A_IWL<29342> A_IWL<29341> A_IWL<29340> A_IWL<29339> A_IWL<29338> A_IWL<29337> A_IWL<29336> A_IWL<29335> A_IWL<29334> A_IWL<29333> A_IWL<29332> A_IWL<29331> A_IWL<29330> A_IWL<29329> A_IWL<29328> A_IWL<29327> A_IWL<29326> A_IWL<29325> A_IWL<29324> A_IWL<29323> A_IWL<29322> A_IWL<29321> A_IWL<29320> A_IWL<29319> A_IWL<29318> A_IWL<29317> A_IWL<29316> A_IWL<29315> A_IWL<29314> A_IWL<29313> A_IWL<29312> A_IWL<29311> A_IWL<29310> A_IWL<29309> A_IWL<29308> A_IWL<29307> A_IWL<29306> A_IWL<29305> A_IWL<29304> A_IWL<29303> A_IWL<29302> A_IWL<29301> A_IWL<29300> A_IWL<29299> A_IWL<29298> A_IWL<29297> A_IWL<29296> A_IWL<29295> A_IWL<29294> A_IWL<29293> A_IWL<29292> A_IWL<29291> A_IWL<29290> A_IWL<29289> A_IWL<29288> A_IWL<29287> A_IWL<29286> A_IWL<29285> A_IWL<29284> A_IWL<29283> A_IWL<29282> A_IWL<29281> A_IWL<29280> A_IWL<29279> A_IWL<29278> A_IWL<29277> A_IWL<29276> A_IWL<29275> A_IWL<29274> A_IWL<29273> A_IWL<29272> A_IWL<29271> A_IWL<29270> A_IWL<29269> A_IWL<29268> A_IWL<29267> A_IWL<29266> A_IWL<29265> A_IWL<29264> A_IWL<29263> A_IWL<29262> A_IWL<29261> A_IWL<29260> A_IWL<29259> A_IWL<29258> A_IWL<29257> A_IWL<29256> A_IWL<29255> A_IWL<29254> A_IWL<29253> A_IWL<29252> A_IWL<29251> A_IWL<29250> A_IWL<29249> A_IWL<29248> A_IWL<29247> A_IWL<29246> A_IWL<29245> A_IWL<29244> A_IWL<29243> A_IWL<29242> A_IWL<29241> A_IWL<29240> A_IWL<29239> A_IWL<29238> A_IWL<29237> A_IWL<29236> A_IWL<29235> A_IWL<29234> A_IWL<29233> A_IWL<29232> A_IWL<29231> A_IWL<29230> A_IWL<29229> A_IWL<29228> A_IWL<29227> A_IWL<29226> A_IWL<29225> A_IWL<29224> A_IWL<29223> A_IWL<29222> A_IWL<29221> A_IWL<29220> A_IWL<29219> A_IWL<29218> A_IWL<29217> A_IWL<29216> A_IWL<29215> A_IWL<29214> A_IWL<29213> A_IWL<29212> A_IWL<29211> A_IWL<29210> A_IWL<29209> A_IWL<29208> A_IWL<29207> A_IWL<29206> A_IWL<29205> A_IWL<29204> A_IWL<29203> A_IWL<29202> A_IWL<29201> A_IWL<29200> A_IWL<29199> A_IWL<29198> A_IWL<29197> A_IWL<29196> A_IWL<29195> A_IWL<29194> A_IWL<29193> A_IWL<29192> A_IWL<29191> A_IWL<29190> A_IWL<29189> A_IWL<29188> A_IWL<29187> A_IWL<29186> A_IWL<29185> A_IWL<29184> VDD_CORE VSS / RM_IHPSG13_8192x32_c4_1P_COLUMN_pcell_0 +XCOL<56> A_BLC<113> A_BLC<112> A_BLC_TOP<113> A_BLC_TOP<112> A_BLT<113> A_BLT<112> A_BLT_TOP<113> A_BLT_TOP<112> A_IWL<28671> A_IWL<28670> A_IWL<28669> A_IWL<28668> A_IWL<28667> A_IWL<28666> A_IWL<28665> A_IWL<28664> A_IWL<28663> A_IWL<28662> A_IWL<28661> A_IWL<28660> A_IWL<28659> A_IWL<28658> A_IWL<28657> A_IWL<28656> A_IWL<28655> A_IWL<28654> A_IWL<28653> A_IWL<28652> A_IWL<28651> A_IWL<28650> A_IWL<28649> A_IWL<28648> A_IWL<28647> A_IWL<28646> A_IWL<28645> A_IWL<28644> A_IWL<28643> A_IWL<28642> A_IWL<28641> A_IWL<28640> A_IWL<28639> A_IWL<28638> A_IWL<28637> A_IWL<28636> A_IWL<28635> A_IWL<28634> A_IWL<28633> A_IWL<28632> A_IWL<28631> A_IWL<28630> A_IWL<28629> A_IWL<28628> A_IWL<28627> A_IWL<28626> A_IWL<28625> A_IWL<28624> A_IWL<28623> A_IWL<28622> A_IWL<28621> A_IWL<28620> A_IWL<28619> A_IWL<28618> A_IWL<28617> A_IWL<28616> A_IWL<28615> A_IWL<28614> A_IWL<28613> A_IWL<28612> A_IWL<28611> A_IWL<28610> A_IWL<28609> A_IWL<28608> A_IWL<28607> A_IWL<28606> A_IWL<28605> A_IWL<28604> A_IWL<28603> A_IWL<28602> A_IWL<28601> A_IWL<28600> A_IWL<28599> A_IWL<28598> A_IWL<28597> A_IWL<28596> A_IWL<28595> A_IWL<28594> A_IWL<28593> A_IWL<28592> A_IWL<28591> A_IWL<28590> A_IWL<28589> A_IWL<28588> A_IWL<28587> A_IWL<28586> A_IWL<28585> A_IWL<28584> A_IWL<28583> A_IWL<28582> A_IWL<28581> A_IWL<28580> A_IWL<28579> A_IWL<28578> A_IWL<28577> A_IWL<28576> A_IWL<28575> A_IWL<28574> A_IWL<28573> A_IWL<28572> A_IWL<28571> A_IWL<28570> A_IWL<28569> A_IWL<28568> A_IWL<28567> A_IWL<28566> A_IWL<28565> A_IWL<28564> A_IWL<28563> A_IWL<28562> A_IWL<28561> A_IWL<28560> A_IWL<28559> A_IWL<28558> A_IWL<28557> A_IWL<28556> A_IWL<28555> A_IWL<28554> A_IWL<28553> A_IWL<28552> A_IWL<28551> A_IWL<28550> A_IWL<28549> A_IWL<28548> A_IWL<28547> A_IWL<28546> A_IWL<28545> A_IWL<28544> A_IWL<28543> A_IWL<28542> A_IWL<28541> A_IWL<28540> A_IWL<28539> A_IWL<28538> A_IWL<28537> A_IWL<28536> A_IWL<28535> A_IWL<28534> A_IWL<28533> A_IWL<28532> A_IWL<28531> A_IWL<28530> A_IWL<28529> A_IWL<28528> A_IWL<28527> A_IWL<28526> A_IWL<28525> A_IWL<28524> A_IWL<28523> A_IWL<28522> A_IWL<28521> A_IWL<28520> A_IWL<28519> A_IWL<28518> A_IWL<28517> A_IWL<28516> A_IWL<28515> A_IWL<28514> A_IWL<28513> A_IWL<28512> A_IWL<28511> A_IWL<28510> A_IWL<28509> A_IWL<28508> A_IWL<28507> A_IWL<28506> A_IWL<28505> A_IWL<28504> A_IWL<28503> A_IWL<28502> A_IWL<28501> A_IWL<28500> A_IWL<28499> A_IWL<28498> A_IWL<28497> A_IWL<28496> A_IWL<28495> A_IWL<28494> A_IWL<28493> A_IWL<28492> A_IWL<28491> A_IWL<28490> A_IWL<28489> A_IWL<28488> A_IWL<28487> A_IWL<28486> A_IWL<28485> A_IWL<28484> A_IWL<28483> A_IWL<28482> A_IWL<28481> A_IWL<28480> A_IWL<28479> A_IWL<28478> A_IWL<28477> A_IWL<28476> A_IWL<28475> A_IWL<28474> A_IWL<28473> A_IWL<28472> A_IWL<28471> A_IWL<28470> A_IWL<28469> A_IWL<28468> A_IWL<28467> A_IWL<28466> A_IWL<28465> A_IWL<28464> A_IWL<28463> A_IWL<28462> A_IWL<28461> A_IWL<28460> A_IWL<28459> A_IWL<28458> A_IWL<28457> A_IWL<28456> A_IWL<28455> A_IWL<28454> A_IWL<28453> A_IWL<28452> A_IWL<28451> A_IWL<28450> A_IWL<28449> A_IWL<28448> A_IWL<28447> A_IWL<28446> A_IWL<28445> A_IWL<28444> A_IWL<28443> A_IWL<28442> A_IWL<28441> A_IWL<28440> A_IWL<28439> A_IWL<28438> A_IWL<28437> A_IWL<28436> A_IWL<28435> A_IWL<28434> A_IWL<28433> A_IWL<28432> A_IWL<28431> A_IWL<28430> A_IWL<28429> A_IWL<28428> A_IWL<28427> A_IWL<28426> A_IWL<28425> A_IWL<28424> A_IWL<28423> A_IWL<28422> A_IWL<28421> A_IWL<28420> A_IWL<28419> A_IWL<28418> A_IWL<28417> A_IWL<28416> A_IWL<28415> A_IWL<28414> A_IWL<28413> A_IWL<28412> A_IWL<28411> A_IWL<28410> A_IWL<28409> A_IWL<28408> A_IWL<28407> A_IWL<28406> A_IWL<28405> A_IWL<28404> A_IWL<28403> A_IWL<28402> A_IWL<28401> A_IWL<28400> A_IWL<28399> A_IWL<28398> A_IWL<28397> A_IWL<28396> A_IWL<28395> A_IWL<28394> A_IWL<28393> A_IWL<28392> A_IWL<28391> A_IWL<28390> A_IWL<28389> A_IWL<28388> A_IWL<28387> A_IWL<28386> A_IWL<28385> A_IWL<28384> A_IWL<28383> A_IWL<28382> A_IWL<28381> A_IWL<28380> A_IWL<28379> A_IWL<28378> A_IWL<28377> A_IWL<28376> A_IWL<28375> A_IWL<28374> A_IWL<28373> A_IWL<28372> A_IWL<28371> A_IWL<28370> A_IWL<28369> A_IWL<28368> A_IWL<28367> A_IWL<28366> A_IWL<28365> A_IWL<28364> A_IWL<28363> A_IWL<28362> A_IWL<28361> A_IWL<28360> A_IWL<28359> A_IWL<28358> A_IWL<28357> A_IWL<28356> A_IWL<28355> A_IWL<28354> A_IWL<28353> A_IWL<28352> A_IWL<28351> A_IWL<28350> A_IWL<28349> A_IWL<28348> A_IWL<28347> A_IWL<28346> A_IWL<28345> A_IWL<28344> A_IWL<28343> A_IWL<28342> A_IWL<28341> A_IWL<28340> A_IWL<28339> A_IWL<28338> A_IWL<28337> A_IWL<28336> A_IWL<28335> A_IWL<28334> A_IWL<28333> A_IWL<28332> A_IWL<28331> A_IWL<28330> A_IWL<28329> A_IWL<28328> A_IWL<28327> A_IWL<28326> A_IWL<28325> A_IWL<28324> A_IWL<28323> A_IWL<28322> A_IWL<28321> A_IWL<28320> A_IWL<28319> A_IWL<28318> A_IWL<28317> A_IWL<28316> A_IWL<28315> A_IWL<28314> A_IWL<28313> A_IWL<28312> A_IWL<28311> A_IWL<28310> A_IWL<28309> A_IWL<28308> A_IWL<28307> A_IWL<28306> A_IWL<28305> A_IWL<28304> A_IWL<28303> A_IWL<28302> A_IWL<28301> A_IWL<28300> A_IWL<28299> A_IWL<28298> A_IWL<28297> A_IWL<28296> A_IWL<28295> A_IWL<28294> A_IWL<28293> A_IWL<28292> A_IWL<28291> A_IWL<28290> A_IWL<28289> A_IWL<28288> A_IWL<28287> A_IWL<28286> A_IWL<28285> A_IWL<28284> A_IWL<28283> A_IWL<28282> A_IWL<28281> A_IWL<28280> A_IWL<28279> A_IWL<28278> A_IWL<28277> A_IWL<28276> A_IWL<28275> A_IWL<28274> A_IWL<28273> A_IWL<28272> A_IWL<28271> A_IWL<28270> A_IWL<28269> A_IWL<28268> A_IWL<28267> A_IWL<28266> A_IWL<28265> A_IWL<28264> A_IWL<28263> A_IWL<28262> A_IWL<28261> A_IWL<28260> A_IWL<28259> A_IWL<28258> A_IWL<28257> A_IWL<28256> A_IWL<28255> A_IWL<28254> A_IWL<28253> A_IWL<28252> A_IWL<28251> A_IWL<28250> A_IWL<28249> A_IWL<28248> A_IWL<28247> A_IWL<28246> A_IWL<28245> A_IWL<28244> A_IWL<28243> A_IWL<28242> A_IWL<28241> A_IWL<28240> A_IWL<28239> A_IWL<28238> A_IWL<28237> A_IWL<28236> A_IWL<28235> A_IWL<28234> A_IWL<28233> A_IWL<28232> A_IWL<28231> A_IWL<28230> A_IWL<28229> A_IWL<28228> A_IWL<28227> A_IWL<28226> A_IWL<28225> A_IWL<28224> A_IWL<28223> A_IWL<28222> A_IWL<28221> A_IWL<28220> A_IWL<28219> A_IWL<28218> A_IWL<28217> A_IWL<28216> A_IWL<28215> A_IWL<28214> A_IWL<28213> A_IWL<28212> A_IWL<28211> A_IWL<28210> A_IWL<28209> A_IWL<28208> A_IWL<28207> A_IWL<28206> A_IWL<28205> A_IWL<28204> A_IWL<28203> A_IWL<28202> A_IWL<28201> A_IWL<28200> A_IWL<28199> A_IWL<28198> A_IWL<28197> A_IWL<28196> A_IWL<28195> A_IWL<28194> A_IWL<28193> A_IWL<28192> A_IWL<28191> A_IWL<28190> A_IWL<28189> A_IWL<28188> A_IWL<28187> A_IWL<28186> A_IWL<28185> A_IWL<28184> A_IWL<28183> A_IWL<28182> A_IWL<28181> A_IWL<28180> A_IWL<28179> A_IWL<28178> A_IWL<28177> A_IWL<28176> A_IWL<28175> A_IWL<28174> A_IWL<28173> A_IWL<28172> A_IWL<28171> A_IWL<28170> A_IWL<28169> A_IWL<28168> A_IWL<28167> A_IWL<28166> A_IWL<28165> A_IWL<28164> A_IWL<28163> A_IWL<28162> A_IWL<28161> A_IWL<28160> A_IWL<29183> A_IWL<29182> A_IWL<29181> A_IWL<29180> A_IWL<29179> A_IWL<29178> A_IWL<29177> A_IWL<29176> A_IWL<29175> A_IWL<29174> A_IWL<29173> A_IWL<29172> A_IWL<29171> A_IWL<29170> A_IWL<29169> A_IWL<29168> A_IWL<29167> A_IWL<29166> A_IWL<29165> A_IWL<29164> A_IWL<29163> A_IWL<29162> A_IWL<29161> A_IWL<29160> A_IWL<29159> A_IWL<29158> A_IWL<29157> A_IWL<29156> A_IWL<29155> A_IWL<29154> A_IWL<29153> A_IWL<29152> A_IWL<29151> A_IWL<29150> A_IWL<29149> A_IWL<29148> A_IWL<29147> A_IWL<29146> A_IWL<29145> A_IWL<29144> A_IWL<29143> A_IWL<29142> A_IWL<29141> A_IWL<29140> A_IWL<29139> A_IWL<29138> A_IWL<29137> A_IWL<29136> A_IWL<29135> A_IWL<29134> A_IWL<29133> A_IWL<29132> A_IWL<29131> A_IWL<29130> A_IWL<29129> A_IWL<29128> A_IWL<29127> A_IWL<29126> A_IWL<29125> A_IWL<29124> A_IWL<29123> A_IWL<29122> A_IWL<29121> A_IWL<29120> A_IWL<29119> A_IWL<29118> A_IWL<29117> A_IWL<29116> A_IWL<29115> A_IWL<29114> A_IWL<29113> A_IWL<29112> A_IWL<29111> A_IWL<29110> A_IWL<29109> A_IWL<29108> A_IWL<29107> A_IWL<29106> A_IWL<29105> A_IWL<29104> A_IWL<29103> A_IWL<29102> A_IWL<29101> A_IWL<29100> A_IWL<29099> A_IWL<29098> A_IWL<29097> A_IWL<29096> A_IWL<29095> A_IWL<29094> A_IWL<29093> A_IWL<29092> A_IWL<29091> A_IWL<29090> A_IWL<29089> A_IWL<29088> A_IWL<29087> A_IWL<29086> A_IWL<29085> A_IWL<29084> A_IWL<29083> A_IWL<29082> A_IWL<29081> A_IWL<29080> A_IWL<29079> A_IWL<29078> A_IWL<29077> A_IWL<29076> A_IWL<29075> A_IWL<29074> A_IWL<29073> A_IWL<29072> A_IWL<29071> A_IWL<29070> A_IWL<29069> A_IWL<29068> A_IWL<29067> A_IWL<29066> A_IWL<29065> A_IWL<29064> A_IWL<29063> A_IWL<29062> A_IWL<29061> A_IWL<29060> A_IWL<29059> A_IWL<29058> A_IWL<29057> A_IWL<29056> A_IWL<29055> A_IWL<29054> A_IWL<29053> A_IWL<29052> A_IWL<29051> A_IWL<29050> A_IWL<29049> A_IWL<29048> A_IWL<29047> A_IWL<29046> A_IWL<29045> A_IWL<29044> A_IWL<29043> A_IWL<29042> A_IWL<29041> A_IWL<29040> A_IWL<29039> A_IWL<29038> A_IWL<29037> A_IWL<29036> A_IWL<29035> A_IWL<29034> A_IWL<29033> A_IWL<29032> A_IWL<29031> A_IWL<29030> A_IWL<29029> A_IWL<29028> A_IWL<29027> A_IWL<29026> A_IWL<29025> A_IWL<29024> A_IWL<29023> A_IWL<29022> A_IWL<29021> A_IWL<29020> A_IWL<29019> A_IWL<29018> A_IWL<29017> A_IWL<29016> A_IWL<29015> A_IWL<29014> A_IWL<29013> A_IWL<29012> A_IWL<29011> A_IWL<29010> A_IWL<29009> A_IWL<29008> A_IWL<29007> A_IWL<29006> A_IWL<29005> A_IWL<29004> A_IWL<29003> A_IWL<29002> A_IWL<29001> A_IWL<29000> A_IWL<28999> A_IWL<28998> A_IWL<28997> A_IWL<28996> A_IWL<28995> A_IWL<28994> A_IWL<28993> A_IWL<28992> A_IWL<28991> A_IWL<28990> A_IWL<28989> A_IWL<28988> A_IWL<28987> A_IWL<28986> A_IWL<28985> A_IWL<28984> A_IWL<28983> A_IWL<28982> A_IWL<28981> A_IWL<28980> A_IWL<28979> A_IWL<28978> A_IWL<28977> A_IWL<28976> A_IWL<28975> A_IWL<28974> A_IWL<28973> A_IWL<28972> A_IWL<28971> A_IWL<28970> A_IWL<28969> A_IWL<28968> A_IWL<28967> A_IWL<28966> A_IWL<28965> A_IWL<28964> A_IWL<28963> A_IWL<28962> A_IWL<28961> A_IWL<28960> A_IWL<28959> A_IWL<28958> A_IWL<28957> A_IWL<28956> A_IWL<28955> A_IWL<28954> A_IWL<28953> A_IWL<28952> A_IWL<28951> A_IWL<28950> A_IWL<28949> A_IWL<28948> A_IWL<28947> A_IWL<28946> A_IWL<28945> A_IWL<28944> A_IWL<28943> A_IWL<28942> A_IWL<28941> A_IWL<28940> A_IWL<28939> A_IWL<28938> A_IWL<28937> A_IWL<28936> A_IWL<28935> A_IWL<28934> A_IWL<28933> A_IWL<28932> A_IWL<28931> A_IWL<28930> A_IWL<28929> A_IWL<28928> A_IWL<28927> A_IWL<28926> A_IWL<28925> A_IWL<28924> A_IWL<28923> A_IWL<28922> A_IWL<28921> A_IWL<28920> A_IWL<28919> A_IWL<28918> A_IWL<28917> A_IWL<28916> A_IWL<28915> A_IWL<28914> A_IWL<28913> A_IWL<28912> A_IWL<28911> A_IWL<28910> A_IWL<28909> A_IWL<28908> A_IWL<28907> A_IWL<28906> A_IWL<28905> A_IWL<28904> A_IWL<28903> A_IWL<28902> A_IWL<28901> A_IWL<28900> A_IWL<28899> A_IWL<28898> A_IWL<28897> A_IWL<28896> A_IWL<28895> A_IWL<28894> A_IWL<28893> A_IWL<28892> A_IWL<28891> A_IWL<28890> A_IWL<28889> A_IWL<28888> A_IWL<28887> A_IWL<28886> A_IWL<28885> A_IWL<28884> A_IWL<28883> A_IWL<28882> A_IWL<28881> A_IWL<28880> A_IWL<28879> A_IWL<28878> A_IWL<28877> A_IWL<28876> A_IWL<28875> A_IWL<28874> A_IWL<28873> A_IWL<28872> A_IWL<28871> A_IWL<28870> A_IWL<28869> A_IWL<28868> A_IWL<28867> A_IWL<28866> A_IWL<28865> A_IWL<28864> A_IWL<28863> A_IWL<28862> A_IWL<28861> A_IWL<28860> A_IWL<28859> A_IWL<28858> A_IWL<28857> A_IWL<28856> A_IWL<28855> A_IWL<28854> A_IWL<28853> A_IWL<28852> A_IWL<28851> A_IWL<28850> A_IWL<28849> A_IWL<28848> A_IWL<28847> A_IWL<28846> A_IWL<28845> A_IWL<28844> A_IWL<28843> A_IWL<28842> A_IWL<28841> A_IWL<28840> A_IWL<28839> A_IWL<28838> A_IWL<28837> A_IWL<28836> A_IWL<28835> A_IWL<28834> A_IWL<28833> A_IWL<28832> A_IWL<28831> A_IWL<28830> A_IWL<28829> A_IWL<28828> A_IWL<28827> A_IWL<28826> A_IWL<28825> A_IWL<28824> A_IWL<28823> A_IWL<28822> A_IWL<28821> A_IWL<28820> A_IWL<28819> A_IWL<28818> A_IWL<28817> A_IWL<28816> A_IWL<28815> A_IWL<28814> A_IWL<28813> A_IWL<28812> A_IWL<28811> A_IWL<28810> A_IWL<28809> A_IWL<28808> A_IWL<28807> A_IWL<28806> A_IWL<28805> A_IWL<28804> A_IWL<28803> A_IWL<28802> A_IWL<28801> A_IWL<28800> A_IWL<28799> A_IWL<28798> A_IWL<28797> A_IWL<28796> A_IWL<28795> A_IWL<28794> A_IWL<28793> A_IWL<28792> A_IWL<28791> A_IWL<28790> A_IWL<28789> A_IWL<28788> A_IWL<28787> A_IWL<28786> A_IWL<28785> A_IWL<28784> A_IWL<28783> A_IWL<28782> A_IWL<28781> A_IWL<28780> A_IWL<28779> A_IWL<28778> A_IWL<28777> A_IWL<28776> A_IWL<28775> A_IWL<28774> A_IWL<28773> A_IWL<28772> A_IWL<28771> A_IWL<28770> A_IWL<28769> A_IWL<28768> A_IWL<28767> A_IWL<28766> A_IWL<28765> A_IWL<28764> A_IWL<28763> A_IWL<28762> A_IWL<28761> A_IWL<28760> A_IWL<28759> A_IWL<28758> A_IWL<28757> A_IWL<28756> A_IWL<28755> A_IWL<28754> A_IWL<28753> A_IWL<28752> A_IWL<28751> A_IWL<28750> A_IWL<28749> A_IWL<28748> A_IWL<28747> A_IWL<28746> A_IWL<28745> A_IWL<28744> A_IWL<28743> A_IWL<28742> A_IWL<28741> A_IWL<28740> A_IWL<28739> A_IWL<28738> A_IWL<28737> A_IWL<28736> A_IWL<28735> A_IWL<28734> A_IWL<28733> A_IWL<28732> A_IWL<28731> A_IWL<28730> A_IWL<28729> A_IWL<28728> A_IWL<28727> A_IWL<28726> A_IWL<28725> A_IWL<28724> A_IWL<28723> A_IWL<28722> A_IWL<28721> A_IWL<28720> A_IWL<28719> A_IWL<28718> A_IWL<28717> A_IWL<28716> A_IWL<28715> A_IWL<28714> A_IWL<28713> A_IWL<28712> A_IWL<28711> A_IWL<28710> A_IWL<28709> A_IWL<28708> A_IWL<28707> A_IWL<28706> A_IWL<28705> A_IWL<28704> A_IWL<28703> A_IWL<28702> A_IWL<28701> A_IWL<28700> A_IWL<28699> A_IWL<28698> A_IWL<28697> A_IWL<28696> A_IWL<28695> A_IWL<28694> A_IWL<28693> A_IWL<28692> A_IWL<28691> A_IWL<28690> A_IWL<28689> A_IWL<28688> A_IWL<28687> A_IWL<28686> A_IWL<28685> A_IWL<28684> A_IWL<28683> A_IWL<28682> A_IWL<28681> A_IWL<28680> A_IWL<28679> A_IWL<28678> A_IWL<28677> A_IWL<28676> A_IWL<28675> A_IWL<28674> A_IWL<28673> A_IWL<28672> VDD_CORE VSS / RM_IHPSG13_8192x32_c4_1P_COLUMN_pcell_0 +XCOL<55> A_BLC<111> A_BLC<110> A_BLC_TOP<111> A_BLC_TOP<110> A_BLT<111> A_BLT<110> A_BLT_TOP<111> A_BLT_TOP<110> A_IWL<28159> A_IWL<28158> A_IWL<28157> A_IWL<28156> A_IWL<28155> A_IWL<28154> A_IWL<28153> A_IWL<28152> A_IWL<28151> A_IWL<28150> A_IWL<28149> A_IWL<28148> A_IWL<28147> A_IWL<28146> A_IWL<28145> A_IWL<28144> A_IWL<28143> A_IWL<28142> A_IWL<28141> A_IWL<28140> A_IWL<28139> A_IWL<28138> A_IWL<28137> A_IWL<28136> A_IWL<28135> A_IWL<28134> A_IWL<28133> A_IWL<28132> A_IWL<28131> A_IWL<28130> A_IWL<28129> A_IWL<28128> A_IWL<28127> A_IWL<28126> A_IWL<28125> A_IWL<28124> A_IWL<28123> A_IWL<28122> A_IWL<28121> A_IWL<28120> A_IWL<28119> A_IWL<28118> A_IWL<28117> A_IWL<28116> A_IWL<28115> A_IWL<28114> A_IWL<28113> A_IWL<28112> A_IWL<28111> A_IWL<28110> A_IWL<28109> A_IWL<28108> A_IWL<28107> A_IWL<28106> A_IWL<28105> A_IWL<28104> A_IWL<28103> A_IWL<28102> A_IWL<28101> A_IWL<28100> A_IWL<28099> A_IWL<28098> A_IWL<28097> A_IWL<28096> A_IWL<28095> A_IWL<28094> A_IWL<28093> A_IWL<28092> A_IWL<28091> A_IWL<28090> A_IWL<28089> A_IWL<28088> A_IWL<28087> A_IWL<28086> A_IWL<28085> A_IWL<28084> A_IWL<28083> A_IWL<28082> A_IWL<28081> A_IWL<28080> A_IWL<28079> A_IWL<28078> A_IWL<28077> A_IWL<28076> A_IWL<28075> A_IWL<28074> A_IWL<28073> A_IWL<28072> A_IWL<28071> A_IWL<28070> A_IWL<28069> A_IWL<28068> A_IWL<28067> A_IWL<28066> A_IWL<28065> A_IWL<28064> A_IWL<28063> A_IWL<28062> A_IWL<28061> A_IWL<28060> A_IWL<28059> A_IWL<28058> A_IWL<28057> A_IWL<28056> A_IWL<28055> A_IWL<28054> A_IWL<28053> A_IWL<28052> A_IWL<28051> A_IWL<28050> A_IWL<28049> A_IWL<28048> A_IWL<28047> A_IWL<28046> A_IWL<28045> A_IWL<28044> A_IWL<28043> A_IWL<28042> A_IWL<28041> A_IWL<28040> A_IWL<28039> A_IWL<28038> A_IWL<28037> A_IWL<28036> A_IWL<28035> A_IWL<28034> A_IWL<28033> A_IWL<28032> A_IWL<28031> A_IWL<28030> A_IWL<28029> A_IWL<28028> A_IWL<28027> A_IWL<28026> A_IWL<28025> A_IWL<28024> A_IWL<28023> A_IWL<28022> A_IWL<28021> A_IWL<28020> A_IWL<28019> A_IWL<28018> A_IWL<28017> A_IWL<28016> A_IWL<28015> A_IWL<28014> A_IWL<28013> A_IWL<28012> A_IWL<28011> A_IWL<28010> A_IWL<28009> A_IWL<28008> A_IWL<28007> A_IWL<28006> A_IWL<28005> A_IWL<28004> A_IWL<28003> A_IWL<28002> A_IWL<28001> A_IWL<28000> A_IWL<27999> A_IWL<27998> A_IWL<27997> A_IWL<27996> A_IWL<27995> A_IWL<27994> A_IWL<27993> A_IWL<27992> A_IWL<27991> A_IWL<27990> A_IWL<27989> A_IWL<27988> A_IWL<27987> A_IWL<27986> A_IWL<27985> A_IWL<27984> A_IWL<27983> A_IWL<27982> A_IWL<27981> A_IWL<27980> A_IWL<27979> A_IWL<27978> A_IWL<27977> A_IWL<27976> A_IWL<27975> A_IWL<27974> A_IWL<27973> A_IWL<27972> A_IWL<27971> A_IWL<27970> A_IWL<27969> A_IWL<27968> A_IWL<27967> A_IWL<27966> A_IWL<27965> A_IWL<27964> A_IWL<27963> A_IWL<27962> A_IWL<27961> A_IWL<27960> A_IWL<27959> A_IWL<27958> A_IWL<27957> A_IWL<27956> A_IWL<27955> A_IWL<27954> A_IWL<27953> A_IWL<27952> A_IWL<27951> A_IWL<27950> A_IWL<27949> A_IWL<27948> A_IWL<27947> A_IWL<27946> A_IWL<27945> A_IWL<27944> A_IWL<27943> A_IWL<27942> A_IWL<27941> A_IWL<27940> A_IWL<27939> A_IWL<27938> A_IWL<27937> A_IWL<27936> A_IWL<27935> A_IWL<27934> A_IWL<27933> A_IWL<27932> A_IWL<27931> A_IWL<27930> A_IWL<27929> A_IWL<27928> A_IWL<27927> A_IWL<27926> A_IWL<27925> A_IWL<27924> A_IWL<27923> A_IWL<27922> A_IWL<27921> A_IWL<27920> A_IWL<27919> A_IWL<27918> A_IWL<27917> A_IWL<27916> A_IWL<27915> A_IWL<27914> A_IWL<27913> A_IWL<27912> A_IWL<27911> A_IWL<27910> A_IWL<27909> A_IWL<27908> A_IWL<27907> A_IWL<27906> A_IWL<27905> A_IWL<27904> A_IWL<27903> A_IWL<27902> A_IWL<27901> A_IWL<27900> A_IWL<27899> A_IWL<27898> A_IWL<27897> A_IWL<27896> A_IWL<27895> A_IWL<27894> A_IWL<27893> A_IWL<27892> A_IWL<27891> A_IWL<27890> A_IWL<27889> A_IWL<27888> A_IWL<27887> A_IWL<27886> A_IWL<27885> A_IWL<27884> A_IWL<27883> A_IWL<27882> A_IWL<27881> A_IWL<27880> A_IWL<27879> A_IWL<27878> A_IWL<27877> A_IWL<27876> A_IWL<27875> A_IWL<27874> A_IWL<27873> A_IWL<27872> A_IWL<27871> A_IWL<27870> A_IWL<27869> A_IWL<27868> A_IWL<27867> A_IWL<27866> A_IWL<27865> A_IWL<27864> A_IWL<27863> A_IWL<27862> A_IWL<27861> A_IWL<27860> A_IWL<27859> A_IWL<27858> A_IWL<27857> A_IWL<27856> A_IWL<27855> A_IWL<27854> A_IWL<27853> A_IWL<27852> A_IWL<27851> A_IWL<27850> A_IWL<27849> A_IWL<27848> A_IWL<27847> A_IWL<27846> A_IWL<27845> A_IWL<27844> A_IWL<27843> A_IWL<27842> A_IWL<27841> A_IWL<27840> A_IWL<27839> A_IWL<27838> A_IWL<27837> A_IWL<27836> A_IWL<27835> A_IWL<27834> A_IWL<27833> A_IWL<27832> A_IWL<27831> A_IWL<27830> A_IWL<27829> A_IWL<27828> A_IWL<27827> A_IWL<27826> A_IWL<27825> A_IWL<27824> A_IWL<27823> A_IWL<27822> A_IWL<27821> A_IWL<27820> A_IWL<27819> A_IWL<27818> A_IWL<27817> A_IWL<27816> A_IWL<27815> A_IWL<27814> A_IWL<27813> A_IWL<27812> A_IWL<27811> A_IWL<27810> A_IWL<27809> A_IWL<27808> A_IWL<27807> A_IWL<27806> A_IWL<27805> A_IWL<27804> A_IWL<27803> A_IWL<27802> A_IWL<27801> A_IWL<27800> A_IWL<27799> A_IWL<27798> A_IWL<27797> A_IWL<27796> A_IWL<27795> A_IWL<27794> A_IWL<27793> A_IWL<27792> A_IWL<27791> A_IWL<27790> A_IWL<27789> A_IWL<27788> A_IWL<27787> A_IWL<27786> A_IWL<27785> A_IWL<27784> A_IWL<27783> A_IWL<27782> A_IWL<27781> A_IWL<27780> A_IWL<27779> A_IWL<27778> A_IWL<27777> A_IWL<27776> A_IWL<27775> A_IWL<27774> A_IWL<27773> A_IWL<27772> A_IWL<27771> A_IWL<27770> A_IWL<27769> A_IWL<27768> A_IWL<27767> A_IWL<27766> A_IWL<27765> A_IWL<27764> A_IWL<27763> A_IWL<27762> A_IWL<27761> A_IWL<27760> A_IWL<27759> A_IWL<27758> A_IWL<27757> A_IWL<27756> A_IWL<27755> A_IWL<27754> A_IWL<27753> A_IWL<27752> A_IWL<27751> A_IWL<27750> A_IWL<27749> A_IWL<27748> A_IWL<27747> A_IWL<27746> A_IWL<27745> A_IWL<27744> A_IWL<27743> A_IWL<27742> A_IWL<27741> A_IWL<27740> A_IWL<27739> A_IWL<27738> A_IWL<27737> A_IWL<27736> A_IWL<27735> A_IWL<27734> A_IWL<27733> A_IWL<27732> A_IWL<27731> A_IWL<27730> A_IWL<27729> A_IWL<27728> A_IWL<27727> A_IWL<27726> A_IWL<27725> A_IWL<27724> A_IWL<27723> A_IWL<27722> A_IWL<27721> A_IWL<27720> A_IWL<27719> A_IWL<27718> A_IWL<27717> A_IWL<27716> A_IWL<27715> A_IWL<27714> A_IWL<27713> A_IWL<27712> A_IWL<27711> A_IWL<27710> A_IWL<27709> A_IWL<27708> A_IWL<27707> A_IWL<27706> A_IWL<27705> A_IWL<27704> A_IWL<27703> A_IWL<27702> A_IWL<27701> A_IWL<27700> A_IWL<27699> A_IWL<27698> A_IWL<27697> A_IWL<27696> A_IWL<27695> A_IWL<27694> A_IWL<27693> A_IWL<27692> A_IWL<27691> A_IWL<27690> A_IWL<27689> A_IWL<27688> A_IWL<27687> A_IWL<27686> A_IWL<27685> A_IWL<27684> A_IWL<27683> A_IWL<27682> A_IWL<27681> A_IWL<27680> A_IWL<27679> A_IWL<27678> A_IWL<27677> A_IWL<27676> A_IWL<27675> A_IWL<27674> A_IWL<27673> A_IWL<27672> A_IWL<27671> A_IWL<27670> A_IWL<27669> A_IWL<27668> A_IWL<27667> A_IWL<27666> A_IWL<27665> A_IWL<27664> A_IWL<27663> A_IWL<27662> A_IWL<27661> A_IWL<27660> A_IWL<27659> A_IWL<27658> A_IWL<27657> A_IWL<27656> A_IWL<27655> A_IWL<27654> A_IWL<27653> A_IWL<27652> A_IWL<27651> A_IWL<27650> A_IWL<27649> A_IWL<27648> A_IWL<28671> A_IWL<28670> A_IWL<28669> A_IWL<28668> A_IWL<28667> A_IWL<28666> A_IWL<28665> A_IWL<28664> A_IWL<28663> A_IWL<28662> A_IWL<28661> A_IWL<28660> A_IWL<28659> A_IWL<28658> A_IWL<28657> A_IWL<28656> A_IWL<28655> A_IWL<28654> A_IWL<28653> A_IWL<28652> A_IWL<28651> A_IWL<28650> A_IWL<28649> A_IWL<28648> A_IWL<28647> A_IWL<28646> A_IWL<28645> A_IWL<28644> A_IWL<28643> A_IWL<28642> A_IWL<28641> A_IWL<28640> A_IWL<28639> A_IWL<28638> A_IWL<28637> A_IWL<28636> A_IWL<28635> A_IWL<28634> A_IWL<28633> A_IWL<28632> A_IWL<28631> A_IWL<28630> A_IWL<28629> A_IWL<28628> A_IWL<28627> A_IWL<28626> A_IWL<28625> A_IWL<28624> A_IWL<28623> A_IWL<28622> A_IWL<28621> A_IWL<28620> A_IWL<28619> A_IWL<28618> A_IWL<28617> A_IWL<28616> A_IWL<28615> A_IWL<28614> A_IWL<28613> A_IWL<28612> A_IWL<28611> A_IWL<28610> A_IWL<28609> A_IWL<28608> A_IWL<28607> A_IWL<28606> A_IWL<28605> A_IWL<28604> A_IWL<28603> A_IWL<28602> A_IWL<28601> A_IWL<28600> A_IWL<28599> A_IWL<28598> A_IWL<28597> A_IWL<28596> A_IWL<28595> A_IWL<28594> A_IWL<28593> A_IWL<28592> A_IWL<28591> A_IWL<28590> A_IWL<28589> A_IWL<28588> A_IWL<28587> A_IWL<28586> A_IWL<28585> A_IWL<28584> A_IWL<28583> A_IWL<28582> A_IWL<28581> A_IWL<28580> A_IWL<28579> A_IWL<28578> A_IWL<28577> A_IWL<28576> A_IWL<28575> A_IWL<28574> A_IWL<28573> A_IWL<28572> A_IWL<28571> A_IWL<28570> A_IWL<28569> A_IWL<28568> A_IWL<28567> A_IWL<28566> A_IWL<28565> A_IWL<28564> A_IWL<28563> A_IWL<28562> A_IWL<28561> A_IWL<28560> A_IWL<28559> A_IWL<28558> A_IWL<28557> A_IWL<28556> A_IWL<28555> A_IWL<28554> A_IWL<28553> A_IWL<28552> A_IWL<28551> A_IWL<28550> A_IWL<28549> A_IWL<28548> A_IWL<28547> A_IWL<28546> A_IWL<28545> A_IWL<28544> A_IWL<28543> A_IWL<28542> A_IWL<28541> A_IWL<28540> A_IWL<28539> A_IWL<28538> A_IWL<28537> A_IWL<28536> A_IWL<28535> A_IWL<28534> A_IWL<28533> A_IWL<28532> A_IWL<28531> A_IWL<28530> A_IWL<28529> A_IWL<28528> A_IWL<28527> A_IWL<28526> A_IWL<28525> A_IWL<28524> A_IWL<28523> A_IWL<28522> A_IWL<28521> A_IWL<28520> A_IWL<28519> A_IWL<28518> A_IWL<28517> A_IWL<28516> A_IWL<28515> A_IWL<28514> A_IWL<28513> A_IWL<28512> A_IWL<28511> A_IWL<28510> A_IWL<28509> A_IWL<28508> A_IWL<28507> A_IWL<28506> A_IWL<28505> A_IWL<28504> A_IWL<28503> A_IWL<28502> A_IWL<28501> A_IWL<28500> A_IWL<28499> A_IWL<28498> A_IWL<28497> A_IWL<28496> A_IWL<28495> A_IWL<28494> A_IWL<28493> A_IWL<28492> A_IWL<28491> A_IWL<28490> A_IWL<28489> A_IWL<28488> A_IWL<28487> A_IWL<28486> A_IWL<28485> A_IWL<28484> A_IWL<28483> A_IWL<28482> A_IWL<28481> A_IWL<28480> A_IWL<28479> A_IWL<28478> A_IWL<28477> A_IWL<28476> A_IWL<28475> A_IWL<28474> A_IWL<28473> A_IWL<28472> A_IWL<28471> A_IWL<28470> A_IWL<28469> A_IWL<28468> A_IWL<28467> A_IWL<28466> A_IWL<28465> A_IWL<28464> A_IWL<28463> A_IWL<28462> A_IWL<28461> A_IWL<28460> A_IWL<28459> A_IWL<28458> A_IWL<28457> A_IWL<28456> A_IWL<28455> A_IWL<28454> A_IWL<28453> A_IWL<28452> A_IWL<28451> A_IWL<28450> A_IWL<28449> A_IWL<28448> A_IWL<28447> A_IWL<28446> A_IWL<28445> A_IWL<28444> A_IWL<28443> A_IWL<28442> A_IWL<28441> A_IWL<28440> A_IWL<28439> A_IWL<28438> A_IWL<28437> A_IWL<28436> A_IWL<28435> A_IWL<28434> A_IWL<28433> A_IWL<28432> A_IWL<28431> A_IWL<28430> A_IWL<28429> A_IWL<28428> A_IWL<28427> A_IWL<28426> A_IWL<28425> A_IWL<28424> A_IWL<28423> A_IWL<28422> A_IWL<28421> A_IWL<28420> A_IWL<28419> A_IWL<28418> A_IWL<28417> A_IWL<28416> A_IWL<28415> A_IWL<28414> A_IWL<28413> A_IWL<28412> A_IWL<28411> A_IWL<28410> A_IWL<28409> A_IWL<28408> A_IWL<28407> A_IWL<28406> A_IWL<28405> A_IWL<28404> A_IWL<28403> A_IWL<28402> A_IWL<28401> A_IWL<28400> A_IWL<28399> A_IWL<28398> A_IWL<28397> A_IWL<28396> A_IWL<28395> A_IWL<28394> A_IWL<28393> A_IWL<28392> A_IWL<28391> A_IWL<28390> A_IWL<28389> A_IWL<28388> A_IWL<28387> A_IWL<28386> A_IWL<28385> A_IWL<28384> A_IWL<28383> A_IWL<28382> A_IWL<28381> A_IWL<28380> A_IWL<28379> A_IWL<28378> A_IWL<28377> A_IWL<28376> A_IWL<28375> A_IWL<28374> A_IWL<28373> A_IWL<28372> A_IWL<28371> A_IWL<28370> A_IWL<28369> A_IWL<28368> A_IWL<28367> A_IWL<28366> A_IWL<28365> A_IWL<28364> A_IWL<28363> A_IWL<28362> A_IWL<28361> A_IWL<28360> A_IWL<28359> A_IWL<28358> A_IWL<28357> A_IWL<28356> A_IWL<28355> A_IWL<28354> A_IWL<28353> A_IWL<28352> A_IWL<28351> A_IWL<28350> A_IWL<28349> A_IWL<28348> A_IWL<28347> A_IWL<28346> A_IWL<28345> A_IWL<28344> A_IWL<28343> A_IWL<28342> A_IWL<28341> A_IWL<28340> A_IWL<28339> A_IWL<28338> A_IWL<28337> A_IWL<28336> A_IWL<28335> A_IWL<28334> A_IWL<28333> A_IWL<28332> A_IWL<28331> A_IWL<28330> A_IWL<28329> A_IWL<28328> A_IWL<28327> A_IWL<28326> A_IWL<28325> A_IWL<28324> A_IWL<28323> A_IWL<28322> A_IWL<28321> A_IWL<28320> A_IWL<28319> A_IWL<28318> A_IWL<28317> A_IWL<28316> A_IWL<28315> A_IWL<28314> A_IWL<28313> A_IWL<28312> A_IWL<28311> A_IWL<28310> A_IWL<28309> A_IWL<28308> A_IWL<28307> A_IWL<28306> A_IWL<28305> A_IWL<28304> A_IWL<28303> A_IWL<28302> A_IWL<28301> A_IWL<28300> A_IWL<28299> A_IWL<28298> A_IWL<28297> A_IWL<28296> A_IWL<28295> A_IWL<28294> A_IWL<28293> A_IWL<28292> A_IWL<28291> A_IWL<28290> A_IWL<28289> A_IWL<28288> A_IWL<28287> A_IWL<28286> A_IWL<28285> A_IWL<28284> A_IWL<28283> A_IWL<28282> A_IWL<28281> A_IWL<28280> A_IWL<28279> A_IWL<28278> A_IWL<28277> A_IWL<28276> A_IWL<28275> A_IWL<28274> A_IWL<28273> A_IWL<28272> A_IWL<28271> A_IWL<28270> A_IWL<28269> A_IWL<28268> A_IWL<28267> A_IWL<28266> A_IWL<28265> A_IWL<28264> A_IWL<28263> A_IWL<28262> A_IWL<28261> A_IWL<28260> A_IWL<28259> A_IWL<28258> A_IWL<28257> A_IWL<28256> A_IWL<28255> A_IWL<28254> A_IWL<28253> A_IWL<28252> A_IWL<28251> A_IWL<28250> A_IWL<28249> A_IWL<28248> A_IWL<28247> A_IWL<28246> A_IWL<28245> A_IWL<28244> A_IWL<28243> A_IWL<28242> A_IWL<28241> A_IWL<28240> A_IWL<28239> A_IWL<28238> A_IWL<28237> A_IWL<28236> A_IWL<28235> A_IWL<28234> A_IWL<28233> A_IWL<28232> A_IWL<28231> A_IWL<28230> A_IWL<28229> A_IWL<28228> A_IWL<28227> A_IWL<28226> A_IWL<28225> A_IWL<28224> A_IWL<28223> A_IWL<28222> A_IWL<28221> A_IWL<28220> A_IWL<28219> A_IWL<28218> A_IWL<28217> A_IWL<28216> A_IWL<28215> A_IWL<28214> A_IWL<28213> A_IWL<28212> A_IWL<28211> A_IWL<28210> A_IWL<28209> A_IWL<28208> A_IWL<28207> A_IWL<28206> A_IWL<28205> A_IWL<28204> A_IWL<28203> A_IWL<28202> A_IWL<28201> A_IWL<28200> A_IWL<28199> A_IWL<28198> A_IWL<28197> A_IWL<28196> A_IWL<28195> A_IWL<28194> A_IWL<28193> A_IWL<28192> A_IWL<28191> A_IWL<28190> A_IWL<28189> A_IWL<28188> A_IWL<28187> A_IWL<28186> A_IWL<28185> A_IWL<28184> A_IWL<28183> A_IWL<28182> A_IWL<28181> A_IWL<28180> A_IWL<28179> A_IWL<28178> A_IWL<28177> A_IWL<28176> A_IWL<28175> A_IWL<28174> A_IWL<28173> A_IWL<28172> A_IWL<28171> A_IWL<28170> A_IWL<28169> A_IWL<28168> A_IWL<28167> A_IWL<28166> A_IWL<28165> A_IWL<28164> A_IWL<28163> A_IWL<28162> A_IWL<28161> A_IWL<28160> VDD_CORE VSS / RM_IHPSG13_8192x32_c4_1P_COLUMN_pcell_0 +XCOL<54> A_BLC<109> A_BLC<108> A_BLC_TOP<109> A_BLC_TOP<108> A_BLT<109> A_BLT<108> A_BLT_TOP<109> A_BLT_TOP<108> A_IWL<27647> A_IWL<27646> A_IWL<27645> A_IWL<27644> A_IWL<27643> A_IWL<27642> A_IWL<27641> A_IWL<27640> A_IWL<27639> A_IWL<27638> A_IWL<27637> A_IWL<27636> A_IWL<27635> A_IWL<27634> A_IWL<27633> A_IWL<27632> A_IWL<27631> A_IWL<27630> A_IWL<27629> A_IWL<27628> A_IWL<27627> A_IWL<27626> A_IWL<27625> A_IWL<27624> A_IWL<27623> A_IWL<27622> A_IWL<27621> A_IWL<27620> A_IWL<27619> A_IWL<27618> A_IWL<27617> A_IWL<27616> A_IWL<27615> A_IWL<27614> A_IWL<27613> A_IWL<27612> A_IWL<27611> A_IWL<27610> A_IWL<27609> A_IWL<27608> A_IWL<27607> A_IWL<27606> A_IWL<27605> A_IWL<27604> A_IWL<27603> A_IWL<27602> A_IWL<27601> A_IWL<27600> A_IWL<27599> A_IWL<27598> A_IWL<27597> A_IWL<27596> A_IWL<27595> A_IWL<27594> A_IWL<27593> A_IWL<27592> A_IWL<27591> A_IWL<27590> A_IWL<27589> A_IWL<27588> A_IWL<27587> A_IWL<27586> A_IWL<27585> A_IWL<27584> A_IWL<27583> A_IWL<27582> A_IWL<27581> A_IWL<27580> A_IWL<27579> A_IWL<27578> A_IWL<27577> A_IWL<27576> A_IWL<27575> A_IWL<27574> A_IWL<27573> A_IWL<27572> A_IWL<27571> A_IWL<27570> A_IWL<27569> A_IWL<27568> A_IWL<27567> A_IWL<27566> A_IWL<27565> A_IWL<27564> A_IWL<27563> A_IWL<27562> A_IWL<27561> A_IWL<27560> A_IWL<27559> A_IWL<27558> A_IWL<27557> A_IWL<27556> A_IWL<27555> A_IWL<27554> A_IWL<27553> A_IWL<27552> A_IWL<27551> A_IWL<27550> A_IWL<27549> A_IWL<27548> A_IWL<27547> A_IWL<27546> A_IWL<27545> A_IWL<27544> A_IWL<27543> A_IWL<27542> A_IWL<27541> A_IWL<27540> A_IWL<27539> A_IWL<27538> A_IWL<27537> A_IWL<27536> A_IWL<27535> A_IWL<27534> A_IWL<27533> A_IWL<27532> A_IWL<27531> A_IWL<27530> A_IWL<27529> A_IWL<27528> A_IWL<27527> A_IWL<27526> A_IWL<27525> A_IWL<27524> A_IWL<27523> A_IWL<27522> A_IWL<27521> A_IWL<27520> A_IWL<27519> A_IWL<27518> A_IWL<27517> A_IWL<27516> A_IWL<27515> A_IWL<27514> A_IWL<27513> A_IWL<27512> A_IWL<27511> A_IWL<27510> A_IWL<27509> A_IWL<27508> A_IWL<27507> A_IWL<27506> A_IWL<27505> A_IWL<27504> A_IWL<27503> A_IWL<27502> A_IWL<27501> A_IWL<27500> A_IWL<27499> A_IWL<27498> A_IWL<27497> A_IWL<27496> A_IWL<27495> A_IWL<27494> A_IWL<27493> A_IWL<27492> A_IWL<27491> A_IWL<27490> A_IWL<27489> A_IWL<27488> A_IWL<27487> A_IWL<27486> A_IWL<27485> A_IWL<27484> A_IWL<27483> A_IWL<27482> A_IWL<27481> A_IWL<27480> A_IWL<27479> A_IWL<27478> A_IWL<27477> A_IWL<27476> A_IWL<27475> A_IWL<27474> A_IWL<27473> A_IWL<27472> A_IWL<27471> A_IWL<27470> A_IWL<27469> A_IWL<27468> A_IWL<27467> A_IWL<27466> A_IWL<27465> A_IWL<27464> A_IWL<27463> A_IWL<27462> A_IWL<27461> A_IWL<27460> A_IWL<27459> A_IWL<27458> A_IWL<27457> A_IWL<27456> A_IWL<27455> A_IWL<27454> A_IWL<27453> A_IWL<27452> A_IWL<27451> A_IWL<27450> A_IWL<27449> A_IWL<27448> A_IWL<27447> A_IWL<27446> A_IWL<27445> A_IWL<27444> A_IWL<27443> A_IWL<27442> A_IWL<27441> A_IWL<27440> A_IWL<27439> A_IWL<27438> A_IWL<27437> A_IWL<27436> A_IWL<27435> A_IWL<27434> A_IWL<27433> A_IWL<27432> A_IWL<27431> A_IWL<27430> A_IWL<27429> A_IWL<27428> A_IWL<27427> A_IWL<27426> A_IWL<27425> A_IWL<27424> A_IWL<27423> A_IWL<27422> A_IWL<27421> A_IWL<27420> A_IWL<27419> A_IWL<27418> A_IWL<27417> A_IWL<27416> A_IWL<27415> A_IWL<27414> A_IWL<27413> A_IWL<27412> A_IWL<27411> A_IWL<27410> A_IWL<27409> A_IWL<27408> A_IWL<27407> A_IWL<27406> A_IWL<27405> A_IWL<27404> A_IWL<27403> A_IWL<27402> A_IWL<27401> A_IWL<27400> A_IWL<27399> A_IWL<27398> A_IWL<27397> A_IWL<27396> A_IWL<27395> A_IWL<27394> A_IWL<27393> A_IWL<27392> A_IWL<27391> A_IWL<27390> A_IWL<27389> A_IWL<27388> A_IWL<27387> A_IWL<27386> A_IWL<27385> A_IWL<27384> A_IWL<27383> A_IWL<27382> A_IWL<27381> A_IWL<27380> A_IWL<27379> A_IWL<27378> A_IWL<27377> A_IWL<27376> A_IWL<27375> A_IWL<27374> A_IWL<27373> A_IWL<27372> A_IWL<27371> A_IWL<27370> A_IWL<27369> A_IWL<27368> A_IWL<27367> A_IWL<27366> A_IWL<27365> A_IWL<27364> A_IWL<27363> A_IWL<27362> A_IWL<27361> A_IWL<27360> A_IWL<27359> A_IWL<27358> A_IWL<27357> A_IWL<27356> A_IWL<27355> A_IWL<27354> A_IWL<27353> A_IWL<27352> A_IWL<27351> A_IWL<27350> A_IWL<27349> A_IWL<27348> A_IWL<27347> A_IWL<27346> A_IWL<27345> A_IWL<27344> A_IWL<27343> A_IWL<27342> A_IWL<27341> A_IWL<27340> A_IWL<27339> A_IWL<27338> A_IWL<27337> A_IWL<27336> A_IWL<27335> A_IWL<27334> A_IWL<27333> A_IWL<27332> A_IWL<27331> A_IWL<27330> A_IWL<27329> A_IWL<27328> A_IWL<27327> A_IWL<27326> A_IWL<27325> A_IWL<27324> A_IWL<27323> A_IWL<27322> A_IWL<27321> A_IWL<27320> A_IWL<27319> A_IWL<27318> A_IWL<27317> A_IWL<27316> A_IWL<27315> A_IWL<27314> A_IWL<27313> A_IWL<27312> A_IWL<27311> A_IWL<27310> A_IWL<27309> A_IWL<27308> A_IWL<27307> A_IWL<27306> A_IWL<27305> A_IWL<27304> A_IWL<27303> A_IWL<27302> A_IWL<27301> A_IWL<27300> A_IWL<27299> A_IWL<27298> A_IWL<27297> A_IWL<27296> A_IWL<27295> A_IWL<27294> A_IWL<27293> A_IWL<27292> A_IWL<27291> A_IWL<27290> A_IWL<27289> A_IWL<27288> A_IWL<27287> A_IWL<27286> A_IWL<27285> A_IWL<27284> A_IWL<27283> A_IWL<27282> A_IWL<27281> A_IWL<27280> A_IWL<27279> A_IWL<27278> A_IWL<27277> A_IWL<27276> A_IWL<27275> A_IWL<27274> A_IWL<27273> A_IWL<27272> A_IWL<27271> A_IWL<27270> A_IWL<27269> A_IWL<27268> A_IWL<27267> A_IWL<27266> A_IWL<27265> A_IWL<27264> A_IWL<27263> A_IWL<27262> A_IWL<27261> A_IWL<27260> A_IWL<27259> A_IWL<27258> A_IWL<27257> A_IWL<27256> A_IWL<27255> A_IWL<27254> A_IWL<27253> A_IWL<27252> A_IWL<27251> A_IWL<27250> A_IWL<27249> A_IWL<27248> A_IWL<27247> A_IWL<27246> A_IWL<27245> A_IWL<27244> A_IWL<27243> A_IWL<27242> A_IWL<27241> A_IWL<27240> A_IWL<27239> A_IWL<27238> A_IWL<27237> A_IWL<27236> A_IWL<27235> A_IWL<27234> A_IWL<27233> A_IWL<27232> A_IWL<27231> A_IWL<27230> A_IWL<27229> A_IWL<27228> A_IWL<27227> A_IWL<27226> A_IWL<27225> A_IWL<27224> A_IWL<27223> A_IWL<27222> A_IWL<27221> A_IWL<27220> A_IWL<27219> A_IWL<27218> A_IWL<27217> A_IWL<27216> A_IWL<27215> A_IWL<27214> A_IWL<27213> A_IWL<27212> A_IWL<27211> A_IWL<27210> A_IWL<27209> A_IWL<27208> A_IWL<27207> A_IWL<27206> A_IWL<27205> A_IWL<27204> A_IWL<27203> A_IWL<27202> A_IWL<27201> A_IWL<27200> A_IWL<27199> A_IWL<27198> A_IWL<27197> A_IWL<27196> A_IWL<27195> A_IWL<27194> A_IWL<27193> A_IWL<27192> A_IWL<27191> A_IWL<27190> A_IWL<27189> A_IWL<27188> A_IWL<27187> A_IWL<27186> A_IWL<27185> A_IWL<27184> A_IWL<27183> A_IWL<27182> A_IWL<27181> A_IWL<27180> A_IWL<27179> A_IWL<27178> A_IWL<27177> A_IWL<27176> A_IWL<27175> A_IWL<27174> A_IWL<27173> A_IWL<27172> A_IWL<27171> A_IWL<27170> A_IWL<27169> A_IWL<27168> A_IWL<27167> A_IWL<27166> A_IWL<27165> A_IWL<27164> A_IWL<27163> A_IWL<27162> A_IWL<27161> A_IWL<27160> A_IWL<27159> A_IWL<27158> A_IWL<27157> A_IWL<27156> A_IWL<27155> A_IWL<27154> A_IWL<27153> A_IWL<27152> A_IWL<27151> A_IWL<27150> A_IWL<27149> A_IWL<27148> A_IWL<27147> A_IWL<27146> A_IWL<27145> A_IWL<27144> A_IWL<27143> A_IWL<27142> A_IWL<27141> A_IWL<27140> A_IWL<27139> A_IWL<27138> A_IWL<27137> A_IWL<27136> A_IWL<28159> A_IWL<28158> A_IWL<28157> A_IWL<28156> A_IWL<28155> A_IWL<28154> A_IWL<28153> A_IWL<28152> A_IWL<28151> A_IWL<28150> A_IWL<28149> A_IWL<28148> A_IWL<28147> A_IWL<28146> A_IWL<28145> A_IWL<28144> A_IWL<28143> A_IWL<28142> A_IWL<28141> A_IWL<28140> A_IWL<28139> A_IWL<28138> A_IWL<28137> A_IWL<28136> A_IWL<28135> A_IWL<28134> A_IWL<28133> A_IWL<28132> A_IWL<28131> A_IWL<28130> A_IWL<28129> A_IWL<28128> A_IWL<28127> A_IWL<28126> A_IWL<28125> A_IWL<28124> A_IWL<28123> A_IWL<28122> A_IWL<28121> A_IWL<28120> A_IWL<28119> A_IWL<28118> A_IWL<28117> A_IWL<28116> A_IWL<28115> A_IWL<28114> A_IWL<28113> A_IWL<28112> A_IWL<28111> A_IWL<28110> A_IWL<28109> A_IWL<28108> A_IWL<28107> A_IWL<28106> A_IWL<28105> A_IWL<28104> A_IWL<28103> A_IWL<28102> A_IWL<28101> A_IWL<28100> A_IWL<28099> A_IWL<28098> A_IWL<28097> A_IWL<28096> A_IWL<28095> A_IWL<28094> A_IWL<28093> A_IWL<28092> A_IWL<28091> A_IWL<28090> A_IWL<28089> A_IWL<28088> A_IWL<28087> A_IWL<28086> A_IWL<28085> A_IWL<28084> A_IWL<28083> A_IWL<28082> A_IWL<28081> A_IWL<28080> A_IWL<28079> A_IWL<28078> A_IWL<28077> A_IWL<28076> A_IWL<28075> A_IWL<28074> A_IWL<28073> A_IWL<28072> A_IWL<28071> A_IWL<28070> A_IWL<28069> A_IWL<28068> A_IWL<28067> A_IWL<28066> A_IWL<28065> A_IWL<28064> A_IWL<28063> A_IWL<28062> A_IWL<28061> A_IWL<28060> A_IWL<28059> A_IWL<28058> A_IWL<28057> A_IWL<28056> A_IWL<28055> A_IWL<28054> A_IWL<28053> A_IWL<28052> A_IWL<28051> A_IWL<28050> A_IWL<28049> A_IWL<28048> A_IWL<28047> A_IWL<28046> A_IWL<28045> A_IWL<28044> A_IWL<28043> A_IWL<28042> A_IWL<28041> A_IWL<28040> A_IWL<28039> A_IWL<28038> A_IWL<28037> A_IWL<28036> A_IWL<28035> A_IWL<28034> A_IWL<28033> A_IWL<28032> A_IWL<28031> A_IWL<28030> A_IWL<28029> A_IWL<28028> A_IWL<28027> A_IWL<28026> A_IWL<28025> A_IWL<28024> A_IWL<28023> A_IWL<28022> A_IWL<28021> A_IWL<28020> A_IWL<28019> A_IWL<28018> A_IWL<28017> A_IWL<28016> A_IWL<28015> A_IWL<28014> A_IWL<28013> A_IWL<28012> A_IWL<28011> A_IWL<28010> A_IWL<28009> A_IWL<28008> A_IWL<28007> A_IWL<28006> A_IWL<28005> A_IWL<28004> A_IWL<28003> A_IWL<28002> A_IWL<28001> A_IWL<28000> A_IWL<27999> A_IWL<27998> A_IWL<27997> A_IWL<27996> A_IWL<27995> A_IWL<27994> A_IWL<27993> A_IWL<27992> A_IWL<27991> A_IWL<27990> A_IWL<27989> A_IWL<27988> A_IWL<27987> A_IWL<27986> A_IWL<27985> A_IWL<27984> A_IWL<27983> A_IWL<27982> A_IWL<27981> A_IWL<27980> A_IWL<27979> A_IWL<27978> A_IWL<27977> A_IWL<27976> A_IWL<27975> A_IWL<27974> A_IWL<27973> A_IWL<27972> A_IWL<27971> A_IWL<27970> A_IWL<27969> A_IWL<27968> A_IWL<27967> A_IWL<27966> A_IWL<27965> A_IWL<27964> A_IWL<27963> A_IWL<27962> A_IWL<27961> A_IWL<27960> A_IWL<27959> A_IWL<27958> A_IWL<27957> A_IWL<27956> A_IWL<27955> A_IWL<27954> A_IWL<27953> A_IWL<27952> A_IWL<27951> A_IWL<27950> A_IWL<27949> A_IWL<27948> A_IWL<27947> A_IWL<27946> A_IWL<27945> A_IWL<27944> A_IWL<27943> A_IWL<27942> A_IWL<27941> A_IWL<27940> A_IWL<27939> A_IWL<27938> A_IWL<27937> A_IWL<27936> A_IWL<27935> A_IWL<27934> A_IWL<27933> A_IWL<27932> A_IWL<27931> A_IWL<27930> A_IWL<27929> A_IWL<27928> A_IWL<27927> A_IWL<27926> A_IWL<27925> A_IWL<27924> A_IWL<27923> A_IWL<27922> A_IWL<27921> A_IWL<27920> A_IWL<27919> A_IWL<27918> A_IWL<27917> A_IWL<27916> A_IWL<27915> A_IWL<27914> A_IWL<27913> A_IWL<27912> A_IWL<27911> A_IWL<27910> A_IWL<27909> A_IWL<27908> A_IWL<27907> A_IWL<27906> A_IWL<27905> A_IWL<27904> A_IWL<27903> A_IWL<27902> A_IWL<27901> A_IWL<27900> A_IWL<27899> A_IWL<27898> A_IWL<27897> A_IWL<27896> A_IWL<27895> A_IWL<27894> A_IWL<27893> A_IWL<27892> A_IWL<27891> A_IWL<27890> A_IWL<27889> A_IWL<27888> A_IWL<27887> A_IWL<27886> A_IWL<27885> A_IWL<27884> A_IWL<27883> A_IWL<27882> A_IWL<27881> A_IWL<27880> A_IWL<27879> A_IWL<27878> A_IWL<27877> A_IWL<27876> A_IWL<27875> A_IWL<27874> A_IWL<27873> A_IWL<27872> A_IWL<27871> A_IWL<27870> A_IWL<27869> A_IWL<27868> A_IWL<27867> A_IWL<27866> A_IWL<27865> A_IWL<27864> A_IWL<27863> A_IWL<27862> A_IWL<27861> A_IWL<27860> A_IWL<27859> A_IWL<27858> A_IWL<27857> A_IWL<27856> A_IWL<27855> A_IWL<27854> A_IWL<27853> A_IWL<27852> A_IWL<27851> A_IWL<27850> A_IWL<27849> A_IWL<27848> A_IWL<27847> A_IWL<27846> A_IWL<27845> A_IWL<27844> A_IWL<27843> A_IWL<27842> A_IWL<27841> A_IWL<27840> A_IWL<27839> A_IWL<27838> A_IWL<27837> A_IWL<27836> A_IWL<27835> A_IWL<27834> A_IWL<27833> A_IWL<27832> A_IWL<27831> A_IWL<27830> A_IWL<27829> A_IWL<27828> A_IWL<27827> A_IWL<27826> A_IWL<27825> A_IWL<27824> A_IWL<27823> A_IWL<27822> A_IWL<27821> A_IWL<27820> A_IWL<27819> A_IWL<27818> A_IWL<27817> A_IWL<27816> A_IWL<27815> A_IWL<27814> A_IWL<27813> A_IWL<27812> A_IWL<27811> A_IWL<27810> A_IWL<27809> A_IWL<27808> A_IWL<27807> A_IWL<27806> A_IWL<27805> A_IWL<27804> A_IWL<27803> A_IWL<27802> A_IWL<27801> A_IWL<27800> A_IWL<27799> A_IWL<27798> A_IWL<27797> A_IWL<27796> A_IWL<27795> A_IWL<27794> A_IWL<27793> A_IWL<27792> A_IWL<27791> A_IWL<27790> A_IWL<27789> A_IWL<27788> A_IWL<27787> A_IWL<27786> A_IWL<27785> A_IWL<27784> A_IWL<27783> A_IWL<27782> A_IWL<27781> A_IWL<27780> A_IWL<27779> A_IWL<27778> A_IWL<27777> A_IWL<27776> A_IWL<27775> A_IWL<27774> A_IWL<27773> A_IWL<27772> A_IWL<27771> A_IWL<27770> A_IWL<27769> A_IWL<27768> A_IWL<27767> A_IWL<27766> A_IWL<27765> A_IWL<27764> A_IWL<27763> A_IWL<27762> A_IWL<27761> A_IWL<27760> A_IWL<27759> A_IWL<27758> A_IWL<27757> A_IWL<27756> A_IWL<27755> A_IWL<27754> A_IWL<27753> A_IWL<27752> A_IWL<27751> A_IWL<27750> A_IWL<27749> A_IWL<27748> A_IWL<27747> A_IWL<27746> A_IWL<27745> A_IWL<27744> A_IWL<27743> A_IWL<27742> A_IWL<27741> A_IWL<27740> A_IWL<27739> A_IWL<27738> A_IWL<27737> A_IWL<27736> A_IWL<27735> A_IWL<27734> A_IWL<27733> A_IWL<27732> A_IWL<27731> A_IWL<27730> A_IWL<27729> A_IWL<27728> A_IWL<27727> A_IWL<27726> A_IWL<27725> A_IWL<27724> A_IWL<27723> A_IWL<27722> A_IWL<27721> A_IWL<27720> A_IWL<27719> A_IWL<27718> A_IWL<27717> A_IWL<27716> A_IWL<27715> A_IWL<27714> A_IWL<27713> A_IWL<27712> A_IWL<27711> A_IWL<27710> A_IWL<27709> A_IWL<27708> A_IWL<27707> A_IWL<27706> A_IWL<27705> A_IWL<27704> A_IWL<27703> A_IWL<27702> A_IWL<27701> A_IWL<27700> A_IWL<27699> A_IWL<27698> A_IWL<27697> A_IWL<27696> A_IWL<27695> A_IWL<27694> A_IWL<27693> A_IWL<27692> A_IWL<27691> A_IWL<27690> A_IWL<27689> A_IWL<27688> A_IWL<27687> A_IWL<27686> A_IWL<27685> A_IWL<27684> A_IWL<27683> A_IWL<27682> A_IWL<27681> A_IWL<27680> A_IWL<27679> A_IWL<27678> A_IWL<27677> A_IWL<27676> A_IWL<27675> A_IWL<27674> A_IWL<27673> A_IWL<27672> A_IWL<27671> A_IWL<27670> A_IWL<27669> A_IWL<27668> A_IWL<27667> A_IWL<27666> A_IWL<27665> A_IWL<27664> A_IWL<27663> A_IWL<27662> A_IWL<27661> A_IWL<27660> A_IWL<27659> A_IWL<27658> A_IWL<27657> A_IWL<27656> A_IWL<27655> A_IWL<27654> A_IWL<27653> A_IWL<27652> A_IWL<27651> A_IWL<27650> A_IWL<27649> A_IWL<27648> VDD_CORE VSS / RM_IHPSG13_8192x32_c4_1P_COLUMN_pcell_0 +XCOL<53> A_BLC<107> A_BLC<106> A_BLC_TOP<107> A_BLC_TOP<106> A_BLT<107> A_BLT<106> A_BLT_TOP<107> A_BLT_TOP<106> A_IWL<27135> A_IWL<27134> A_IWL<27133> A_IWL<27132> A_IWL<27131> A_IWL<27130> A_IWL<27129> A_IWL<27128> A_IWL<27127> A_IWL<27126> A_IWL<27125> A_IWL<27124> A_IWL<27123> A_IWL<27122> A_IWL<27121> A_IWL<27120> A_IWL<27119> A_IWL<27118> A_IWL<27117> A_IWL<27116> A_IWL<27115> A_IWL<27114> A_IWL<27113> A_IWL<27112> A_IWL<27111> A_IWL<27110> A_IWL<27109> A_IWL<27108> A_IWL<27107> A_IWL<27106> A_IWL<27105> A_IWL<27104> A_IWL<27103> A_IWL<27102> A_IWL<27101> A_IWL<27100> A_IWL<27099> A_IWL<27098> A_IWL<27097> A_IWL<27096> A_IWL<27095> A_IWL<27094> A_IWL<27093> A_IWL<27092> A_IWL<27091> A_IWL<27090> A_IWL<27089> A_IWL<27088> A_IWL<27087> A_IWL<27086> A_IWL<27085> A_IWL<27084> A_IWL<27083> A_IWL<27082> A_IWL<27081> A_IWL<27080> A_IWL<27079> A_IWL<27078> A_IWL<27077> A_IWL<27076> A_IWL<27075> A_IWL<27074> A_IWL<27073> A_IWL<27072> A_IWL<27071> A_IWL<27070> A_IWL<27069> A_IWL<27068> A_IWL<27067> A_IWL<27066> A_IWL<27065> A_IWL<27064> A_IWL<27063> A_IWL<27062> A_IWL<27061> A_IWL<27060> A_IWL<27059> A_IWL<27058> A_IWL<27057> A_IWL<27056> A_IWL<27055> A_IWL<27054> A_IWL<27053> A_IWL<27052> A_IWL<27051> A_IWL<27050> A_IWL<27049> A_IWL<27048> A_IWL<27047> A_IWL<27046> A_IWL<27045> A_IWL<27044> A_IWL<27043> A_IWL<27042> A_IWL<27041> A_IWL<27040> A_IWL<27039> A_IWL<27038> A_IWL<27037> A_IWL<27036> A_IWL<27035> A_IWL<27034> A_IWL<27033> A_IWL<27032> A_IWL<27031> A_IWL<27030> A_IWL<27029> A_IWL<27028> A_IWL<27027> A_IWL<27026> A_IWL<27025> A_IWL<27024> A_IWL<27023> A_IWL<27022> A_IWL<27021> A_IWL<27020> A_IWL<27019> A_IWL<27018> A_IWL<27017> A_IWL<27016> A_IWL<27015> A_IWL<27014> A_IWL<27013> A_IWL<27012> A_IWL<27011> A_IWL<27010> A_IWL<27009> A_IWL<27008> A_IWL<27007> A_IWL<27006> A_IWL<27005> A_IWL<27004> A_IWL<27003> A_IWL<27002> A_IWL<27001> A_IWL<27000> A_IWL<26999> A_IWL<26998> A_IWL<26997> A_IWL<26996> A_IWL<26995> A_IWL<26994> A_IWL<26993> A_IWL<26992> A_IWL<26991> A_IWL<26990> A_IWL<26989> A_IWL<26988> A_IWL<26987> A_IWL<26986> A_IWL<26985> A_IWL<26984> A_IWL<26983> A_IWL<26982> A_IWL<26981> A_IWL<26980> A_IWL<26979> A_IWL<26978> A_IWL<26977> A_IWL<26976> A_IWL<26975> A_IWL<26974> A_IWL<26973> A_IWL<26972> A_IWL<26971> A_IWL<26970> A_IWL<26969> A_IWL<26968> A_IWL<26967> A_IWL<26966> A_IWL<26965> A_IWL<26964> A_IWL<26963> A_IWL<26962> A_IWL<26961> A_IWL<26960> A_IWL<26959> A_IWL<26958> A_IWL<26957> A_IWL<26956> A_IWL<26955> A_IWL<26954> A_IWL<26953> A_IWL<26952> A_IWL<26951> A_IWL<26950> A_IWL<26949> A_IWL<26948> A_IWL<26947> A_IWL<26946> A_IWL<26945> A_IWL<26944> A_IWL<26943> A_IWL<26942> A_IWL<26941> A_IWL<26940> A_IWL<26939> A_IWL<26938> A_IWL<26937> A_IWL<26936> A_IWL<26935> A_IWL<26934> A_IWL<26933> A_IWL<26932> A_IWL<26931> A_IWL<26930> A_IWL<26929> A_IWL<26928> A_IWL<26927> A_IWL<26926> A_IWL<26925> A_IWL<26924> A_IWL<26923> A_IWL<26922> A_IWL<26921> A_IWL<26920> A_IWL<26919> A_IWL<26918> A_IWL<26917> A_IWL<26916> A_IWL<26915> A_IWL<26914> A_IWL<26913> A_IWL<26912> A_IWL<26911> A_IWL<26910> A_IWL<26909> A_IWL<26908> A_IWL<26907> A_IWL<26906> A_IWL<26905> A_IWL<26904> A_IWL<26903> A_IWL<26902> A_IWL<26901> A_IWL<26900> A_IWL<26899> A_IWL<26898> A_IWL<26897> A_IWL<26896> A_IWL<26895> A_IWL<26894> A_IWL<26893> A_IWL<26892> A_IWL<26891> A_IWL<26890> A_IWL<26889> A_IWL<26888> A_IWL<26887> A_IWL<26886> A_IWL<26885> A_IWL<26884> A_IWL<26883> A_IWL<26882> A_IWL<26881> A_IWL<26880> A_IWL<26879> A_IWL<26878> A_IWL<26877> A_IWL<26876> A_IWL<26875> A_IWL<26874> A_IWL<26873> A_IWL<26872> A_IWL<26871> A_IWL<26870> A_IWL<26869> A_IWL<26868> A_IWL<26867> A_IWL<26866> A_IWL<26865> A_IWL<26864> A_IWL<26863> A_IWL<26862> A_IWL<26861> A_IWL<26860> A_IWL<26859> A_IWL<26858> A_IWL<26857> A_IWL<26856> A_IWL<26855> A_IWL<26854> A_IWL<26853> A_IWL<26852> A_IWL<26851> A_IWL<26850> A_IWL<26849> A_IWL<26848> A_IWL<26847> A_IWL<26846> A_IWL<26845> A_IWL<26844> A_IWL<26843> A_IWL<26842> A_IWL<26841> A_IWL<26840> A_IWL<26839> A_IWL<26838> A_IWL<26837> A_IWL<26836> A_IWL<26835> A_IWL<26834> A_IWL<26833> A_IWL<26832> A_IWL<26831> A_IWL<26830> A_IWL<26829> A_IWL<26828> A_IWL<26827> A_IWL<26826> A_IWL<26825> A_IWL<26824> A_IWL<26823> A_IWL<26822> A_IWL<26821> A_IWL<26820> A_IWL<26819> A_IWL<26818> A_IWL<26817> A_IWL<26816> A_IWL<26815> A_IWL<26814> A_IWL<26813> A_IWL<26812> A_IWL<26811> A_IWL<26810> A_IWL<26809> A_IWL<26808> A_IWL<26807> A_IWL<26806> A_IWL<26805> A_IWL<26804> A_IWL<26803> A_IWL<26802> A_IWL<26801> A_IWL<26800> A_IWL<26799> A_IWL<26798> A_IWL<26797> A_IWL<26796> A_IWL<26795> A_IWL<26794> A_IWL<26793> A_IWL<26792> A_IWL<26791> A_IWL<26790> A_IWL<26789> A_IWL<26788> A_IWL<26787> A_IWL<26786> A_IWL<26785> A_IWL<26784> A_IWL<26783> A_IWL<26782> A_IWL<26781> A_IWL<26780> A_IWL<26779> A_IWL<26778> A_IWL<26777> A_IWL<26776> A_IWL<26775> A_IWL<26774> A_IWL<26773> A_IWL<26772> A_IWL<26771> A_IWL<26770> A_IWL<26769> A_IWL<26768> A_IWL<26767> A_IWL<26766> A_IWL<26765> A_IWL<26764> A_IWL<26763> A_IWL<26762> A_IWL<26761> A_IWL<26760> A_IWL<26759> A_IWL<26758> A_IWL<26757> A_IWL<26756> A_IWL<26755> A_IWL<26754> A_IWL<26753> A_IWL<26752> A_IWL<26751> A_IWL<26750> A_IWL<26749> A_IWL<26748> A_IWL<26747> A_IWL<26746> A_IWL<26745> A_IWL<26744> A_IWL<26743> A_IWL<26742> A_IWL<26741> A_IWL<26740> A_IWL<26739> A_IWL<26738> A_IWL<26737> A_IWL<26736> A_IWL<26735> A_IWL<26734> A_IWL<26733> A_IWL<26732> A_IWL<26731> A_IWL<26730> A_IWL<26729> A_IWL<26728> A_IWL<26727> A_IWL<26726> A_IWL<26725> A_IWL<26724> A_IWL<26723> A_IWL<26722> A_IWL<26721> A_IWL<26720> A_IWL<26719> A_IWL<26718> A_IWL<26717> A_IWL<26716> A_IWL<26715> A_IWL<26714> A_IWL<26713> A_IWL<26712> A_IWL<26711> A_IWL<26710> A_IWL<26709> A_IWL<26708> A_IWL<26707> A_IWL<26706> A_IWL<26705> A_IWL<26704> A_IWL<26703> A_IWL<26702> A_IWL<26701> A_IWL<26700> A_IWL<26699> A_IWL<26698> A_IWL<26697> A_IWL<26696> A_IWL<26695> A_IWL<26694> A_IWL<26693> A_IWL<26692> A_IWL<26691> A_IWL<26690> A_IWL<26689> A_IWL<26688> A_IWL<26687> A_IWL<26686> A_IWL<26685> A_IWL<26684> A_IWL<26683> A_IWL<26682> A_IWL<26681> A_IWL<26680> A_IWL<26679> A_IWL<26678> A_IWL<26677> A_IWL<26676> A_IWL<26675> A_IWL<26674> A_IWL<26673> A_IWL<26672> A_IWL<26671> A_IWL<26670> A_IWL<26669> A_IWL<26668> A_IWL<26667> A_IWL<26666> A_IWL<26665> A_IWL<26664> A_IWL<26663> A_IWL<26662> A_IWL<26661> A_IWL<26660> A_IWL<26659> A_IWL<26658> A_IWL<26657> A_IWL<26656> A_IWL<26655> A_IWL<26654> A_IWL<26653> A_IWL<26652> A_IWL<26651> A_IWL<26650> A_IWL<26649> A_IWL<26648> A_IWL<26647> A_IWL<26646> A_IWL<26645> A_IWL<26644> A_IWL<26643> A_IWL<26642> A_IWL<26641> A_IWL<26640> A_IWL<26639> A_IWL<26638> A_IWL<26637> A_IWL<26636> A_IWL<26635> A_IWL<26634> A_IWL<26633> A_IWL<26632> A_IWL<26631> A_IWL<26630> A_IWL<26629> A_IWL<26628> A_IWL<26627> A_IWL<26626> A_IWL<26625> A_IWL<26624> A_IWL<27647> A_IWL<27646> A_IWL<27645> A_IWL<27644> A_IWL<27643> A_IWL<27642> A_IWL<27641> A_IWL<27640> A_IWL<27639> A_IWL<27638> A_IWL<27637> A_IWL<27636> A_IWL<27635> A_IWL<27634> A_IWL<27633> A_IWL<27632> A_IWL<27631> A_IWL<27630> A_IWL<27629> A_IWL<27628> A_IWL<27627> A_IWL<27626> A_IWL<27625> A_IWL<27624> A_IWL<27623> A_IWL<27622> A_IWL<27621> A_IWL<27620> A_IWL<27619> A_IWL<27618> A_IWL<27617> A_IWL<27616> A_IWL<27615> A_IWL<27614> A_IWL<27613> A_IWL<27612> A_IWL<27611> A_IWL<27610> A_IWL<27609> A_IWL<27608> A_IWL<27607> A_IWL<27606> A_IWL<27605> A_IWL<27604> A_IWL<27603> A_IWL<27602> A_IWL<27601> A_IWL<27600> A_IWL<27599> A_IWL<27598> A_IWL<27597> A_IWL<27596> A_IWL<27595> A_IWL<27594> A_IWL<27593> A_IWL<27592> A_IWL<27591> A_IWL<27590> A_IWL<27589> A_IWL<27588> A_IWL<27587> A_IWL<27586> A_IWL<27585> A_IWL<27584> A_IWL<27583> A_IWL<27582> A_IWL<27581> A_IWL<27580> A_IWL<27579> A_IWL<27578> A_IWL<27577> A_IWL<27576> A_IWL<27575> A_IWL<27574> A_IWL<27573> A_IWL<27572> A_IWL<27571> A_IWL<27570> A_IWL<27569> A_IWL<27568> A_IWL<27567> A_IWL<27566> A_IWL<27565> A_IWL<27564> A_IWL<27563> A_IWL<27562> A_IWL<27561> A_IWL<27560> A_IWL<27559> A_IWL<27558> A_IWL<27557> A_IWL<27556> A_IWL<27555> A_IWL<27554> A_IWL<27553> A_IWL<27552> A_IWL<27551> A_IWL<27550> A_IWL<27549> A_IWL<27548> A_IWL<27547> A_IWL<27546> A_IWL<27545> A_IWL<27544> A_IWL<27543> A_IWL<27542> A_IWL<27541> A_IWL<27540> A_IWL<27539> A_IWL<27538> A_IWL<27537> A_IWL<27536> A_IWL<27535> A_IWL<27534> A_IWL<27533> A_IWL<27532> A_IWL<27531> A_IWL<27530> A_IWL<27529> A_IWL<27528> A_IWL<27527> A_IWL<27526> A_IWL<27525> A_IWL<27524> A_IWL<27523> A_IWL<27522> A_IWL<27521> A_IWL<27520> A_IWL<27519> A_IWL<27518> A_IWL<27517> A_IWL<27516> A_IWL<27515> A_IWL<27514> A_IWL<27513> A_IWL<27512> A_IWL<27511> A_IWL<27510> A_IWL<27509> A_IWL<27508> A_IWL<27507> A_IWL<27506> A_IWL<27505> A_IWL<27504> A_IWL<27503> A_IWL<27502> A_IWL<27501> A_IWL<27500> A_IWL<27499> A_IWL<27498> A_IWL<27497> A_IWL<27496> A_IWL<27495> A_IWL<27494> A_IWL<27493> A_IWL<27492> A_IWL<27491> A_IWL<27490> A_IWL<27489> A_IWL<27488> A_IWL<27487> A_IWL<27486> A_IWL<27485> A_IWL<27484> A_IWL<27483> A_IWL<27482> A_IWL<27481> A_IWL<27480> A_IWL<27479> A_IWL<27478> A_IWL<27477> A_IWL<27476> A_IWL<27475> A_IWL<27474> A_IWL<27473> A_IWL<27472> A_IWL<27471> A_IWL<27470> A_IWL<27469> A_IWL<27468> A_IWL<27467> A_IWL<27466> A_IWL<27465> A_IWL<27464> A_IWL<27463> A_IWL<27462> A_IWL<27461> A_IWL<27460> A_IWL<27459> A_IWL<27458> A_IWL<27457> A_IWL<27456> A_IWL<27455> A_IWL<27454> A_IWL<27453> A_IWL<27452> A_IWL<27451> A_IWL<27450> A_IWL<27449> A_IWL<27448> A_IWL<27447> A_IWL<27446> A_IWL<27445> A_IWL<27444> A_IWL<27443> A_IWL<27442> A_IWL<27441> A_IWL<27440> A_IWL<27439> A_IWL<27438> A_IWL<27437> A_IWL<27436> A_IWL<27435> A_IWL<27434> A_IWL<27433> A_IWL<27432> A_IWL<27431> A_IWL<27430> A_IWL<27429> A_IWL<27428> A_IWL<27427> A_IWL<27426> A_IWL<27425> A_IWL<27424> A_IWL<27423> A_IWL<27422> A_IWL<27421> A_IWL<27420> A_IWL<27419> A_IWL<27418> A_IWL<27417> A_IWL<27416> A_IWL<27415> A_IWL<27414> A_IWL<27413> A_IWL<27412> A_IWL<27411> A_IWL<27410> A_IWL<27409> A_IWL<27408> A_IWL<27407> A_IWL<27406> A_IWL<27405> A_IWL<27404> A_IWL<27403> A_IWL<27402> A_IWL<27401> A_IWL<27400> A_IWL<27399> A_IWL<27398> A_IWL<27397> A_IWL<27396> A_IWL<27395> A_IWL<27394> A_IWL<27393> A_IWL<27392> A_IWL<27391> A_IWL<27390> A_IWL<27389> A_IWL<27388> A_IWL<27387> A_IWL<27386> A_IWL<27385> A_IWL<27384> A_IWL<27383> A_IWL<27382> A_IWL<27381> A_IWL<27380> A_IWL<27379> A_IWL<27378> A_IWL<27377> A_IWL<27376> A_IWL<27375> A_IWL<27374> A_IWL<27373> A_IWL<27372> A_IWL<27371> A_IWL<27370> A_IWL<27369> A_IWL<27368> A_IWL<27367> A_IWL<27366> A_IWL<27365> A_IWL<27364> A_IWL<27363> A_IWL<27362> A_IWL<27361> A_IWL<27360> A_IWL<27359> A_IWL<27358> A_IWL<27357> A_IWL<27356> A_IWL<27355> A_IWL<27354> A_IWL<27353> A_IWL<27352> A_IWL<27351> A_IWL<27350> A_IWL<27349> A_IWL<27348> A_IWL<27347> A_IWL<27346> A_IWL<27345> A_IWL<27344> A_IWL<27343> A_IWL<27342> A_IWL<27341> A_IWL<27340> A_IWL<27339> A_IWL<27338> A_IWL<27337> A_IWL<27336> A_IWL<27335> A_IWL<27334> A_IWL<27333> A_IWL<27332> A_IWL<27331> A_IWL<27330> A_IWL<27329> A_IWL<27328> A_IWL<27327> A_IWL<27326> A_IWL<27325> A_IWL<27324> A_IWL<27323> A_IWL<27322> A_IWL<27321> A_IWL<27320> A_IWL<27319> A_IWL<27318> A_IWL<27317> A_IWL<27316> A_IWL<27315> A_IWL<27314> A_IWL<27313> A_IWL<27312> A_IWL<27311> A_IWL<27310> A_IWL<27309> A_IWL<27308> A_IWL<27307> A_IWL<27306> A_IWL<27305> A_IWL<27304> A_IWL<27303> A_IWL<27302> A_IWL<27301> A_IWL<27300> A_IWL<27299> A_IWL<27298> A_IWL<27297> A_IWL<27296> A_IWL<27295> A_IWL<27294> A_IWL<27293> A_IWL<27292> A_IWL<27291> A_IWL<27290> A_IWL<27289> A_IWL<27288> A_IWL<27287> A_IWL<27286> A_IWL<27285> A_IWL<27284> A_IWL<27283> A_IWL<27282> A_IWL<27281> A_IWL<27280> A_IWL<27279> A_IWL<27278> A_IWL<27277> A_IWL<27276> A_IWL<27275> A_IWL<27274> A_IWL<27273> A_IWL<27272> A_IWL<27271> A_IWL<27270> A_IWL<27269> A_IWL<27268> A_IWL<27267> A_IWL<27266> A_IWL<27265> A_IWL<27264> A_IWL<27263> A_IWL<27262> A_IWL<27261> A_IWL<27260> A_IWL<27259> A_IWL<27258> A_IWL<27257> A_IWL<27256> A_IWL<27255> A_IWL<27254> A_IWL<27253> A_IWL<27252> A_IWL<27251> A_IWL<27250> A_IWL<27249> A_IWL<27248> A_IWL<27247> A_IWL<27246> A_IWL<27245> A_IWL<27244> A_IWL<27243> A_IWL<27242> A_IWL<27241> A_IWL<27240> A_IWL<27239> A_IWL<27238> A_IWL<27237> A_IWL<27236> A_IWL<27235> A_IWL<27234> A_IWL<27233> A_IWL<27232> A_IWL<27231> A_IWL<27230> A_IWL<27229> A_IWL<27228> A_IWL<27227> A_IWL<27226> A_IWL<27225> A_IWL<27224> A_IWL<27223> A_IWL<27222> A_IWL<27221> A_IWL<27220> A_IWL<27219> A_IWL<27218> A_IWL<27217> A_IWL<27216> A_IWL<27215> A_IWL<27214> A_IWL<27213> A_IWL<27212> A_IWL<27211> A_IWL<27210> A_IWL<27209> A_IWL<27208> A_IWL<27207> A_IWL<27206> A_IWL<27205> A_IWL<27204> A_IWL<27203> A_IWL<27202> A_IWL<27201> A_IWL<27200> A_IWL<27199> A_IWL<27198> A_IWL<27197> A_IWL<27196> A_IWL<27195> A_IWL<27194> A_IWL<27193> A_IWL<27192> A_IWL<27191> A_IWL<27190> A_IWL<27189> A_IWL<27188> A_IWL<27187> A_IWL<27186> A_IWL<27185> A_IWL<27184> A_IWL<27183> A_IWL<27182> A_IWL<27181> A_IWL<27180> A_IWL<27179> A_IWL<27178> A_IWL<27177> A_IWL<27176> A_IWL<27175> A_IWL<27174> A_IWL<27173> A_IWL<27172> A_IWL<27171> A_IWL<27170> A_IWL<27169> A_IWL<27168> A_IWL<27167> A_IWL<27166> A_IWL<27165> A_IWL<27164> A_IWL<27163> A_IWL<27162> A_IWL<27161> A_IWL<27160> A_IWL<27159> A_IWL<27158> A_IWL<27157> A_IWL<27156> A_IWL<27155> A_IWL<27154> A_IWL<27153> A_IWL<27152> A_IWL<27151> A_IWL<27150> A_IWL<27149> A_IWL<27148> A_IWL<27147> A_IWL<27146> A_IWL<27145> A_IWL<27144> A_IWL<27143> A_IWL<27142> A_IWL<27141> A_IWL<27140> A_IWL<27139> A_IWL<27138> A_IWL<27137> A_IWL<27136> VDD_CORE VSS / RM_IHPSG13_8192x32_c4_1P_COLUMN_pcell_0 +XCOL<52> A_BLC<105> A_BLC<104> A_BLC_TOP<105> A_BLC_TOP<104> A_BLT<105> A_BLT<104> A_BLT_TOP<105> A_BLT_TOP<104> A_IWL<26623> A_IWL<26622> A_IWL<26621> A_IWL<26620> A_IWL<26619> A_IWL<26618> A_IWL<26617> A_IWL<26616> A_IWL<26615> A_IWL<26614> A_IWL<26613> A_IWL<26612> A_IWL<26611> A_IWL<26610> A_IWL<26609> A_IWL<26608> A_IWL<26607> A_IWL<26606> A_IWL<26605> A_IWL<26604> A_IWL<26603> A_IWL<26602> A_IWL<26601> A_IWL<26600> A_IWL<26599> A_IWL<26598> A_IWL<26597> A_IWL<26596> A_IWL<26595> A_IWL<26594> A_IWL<26593> A_IWL<26592> A_IWL<26591> A_IWL<26590> A_IWL<26589> A_IWL<26588> A_IWL<26587> A_IWL<26586> A_IWL<26585> A_IWL<26584> A_IWL<26583> A_IWL<26582> A_IWL<26581> A_IWL<26580> A_IWL<26579> A_IWL<26578> A_IWL<26577> A_IWL<26576> A_IWL<26575> A_IWL<26574> A_IWL<26573> A_IWL<26572> A_IWL<26571> A_IWL<26570> A_IWL<26569> A_IWL<26568> A_IWL<26567> A_IWL<26566> A_IWL<26565> A_IWL<26564> A_IWL<26563> A_IWL<26562> A_IWL<26561> A_IWL<26560> A_IWL<26559> A_IWL<26558> A_IWL<26557> A_IWL<26556> A_IWL<26555> A_IWL<26554> A_IWL<26553> A_IWL<26552> A_IWL<26551> A_IWL<26550> A_IWL<26549> A_IWL<26548> A_IWL<26547> A_IWL<26546> A_IWL<26545> A_IWL<26544> A_IWL<26543> A_IWL<26542> A_IWL<26541> A_IWL<26540> A_IWL<26539> A_IWL<26538> A_IWL<26537> A_IWL<26536> A_IWL<26535> A_IWL<26534> A_IWL<26533> A_IWL<26532> A_IWL<26531> A_IWL<26530> A_IWL<26529> A_IWL<26528> A_IWL<26527> A_IWL<26526> A_IWL<26525> A_IWL<26524> A_IWL<26523> A_IWL<26522> A_IWL<26521> A_IWL<26520> A_IWL<26519> A_IWL<26518> A_IWL<26517> A_IWL<26516> A_IWL<26515> A_IWL<26514> A_IWL<26513> A_IWL<26512> A_IWL<26511> A_IWL<26510> A_IWL<26509> A_IWL<26508> A_IWL<26507> A_IWL<26506> A_IWL<26505> A_IWL<26504> A_IWL<26503> A_IWL<26502> A_IWL<26501> A_IWL<26500> A_IWL<26499> A_IWL<26498> A_IWL<26497> A_IWL<26496> A_IWL<26495> A_IWL<26494> A_IWL<26493> A_IWL<26492> A_IWL<26491> A_IWL<26490> A_IWL<26489> A_IWL<26488> A_IWL<26487> A_IWL<26486> A_IWL<26485> A_IWL<26484> A_IWL<26483> A_IWL<26482> A_IWL<26481> A_IWL<26480> A_IWL<26479> A_IWL<26478> A_IWL<26477> A_IWL<26476> A_IWL<26475> A_IWL<26474> A_IWL<26473> A_IWL<26472> A_IWL<26471> A_IWL<26470> A_IWL<26469> A_IWL<26468> A_IWL<26467> A_IWL<26466> A_IWL<26465> A_IWL<26464> A_IWL<26463> A_IWL<26462> A_IWL<26461> A_IWL<26460> A_IWL<26459> A_IWL<26458> A_IWL<26457> A_IWL<26456> A_IWL<26455> A_IWL<26454> A_IWL<26453> A_IWL<26452> A_IWL<26451> A_IWL<26450> A_IWL<26449> A_IWL<26448> A_IWL<26447> A_IWL<26446> A_IWL<26445> A_IWL<26444> A_IWL<26443> A_IWL<26442> A_IWL<26441> A_IWL<26440> A_IWL<26439> A_IWL<26438> A_IWL<26437> A_IWL<26436> A_IWL<26435> A_IWL<26434> A_IWL<26433> A_IWL<26432> A_IWL<26431> A_IWL<26430> A_IWL<26429> A_IWL<26428> A_IWL<26427> A_IWL<26426> A_IWL<26425> A_IWL<26424> A_IWL<26423> A_IWL<26422> A_IWL<26421> A_IWL<26420> A_IWL<26419> A_IWL<26418> A_IWL<26417> A_IWL<26416> A_IWL<26415> A_IWL<26414> A_IWL<26413> A_IWL<26412> A_IWL<26411> A_IWL<26410> A_IWL<26409> A_IWL<26408> A_IWL<26407> A_IWL<26406> A_IWL<26405> A_IWL<26404> A_IWL<26403> A_IWL<26402> A_IWL<26401> A_IWL<26400> A_IWL<26399> A_IWL<26398> A_IWL<26397> A_IWL<26396> A_IWL<26395> A_IWL<26394> A_IWL<26393> A_IWL<26392> A_IWL<26391> A_IWL<26390> A_IWL<26389> A_IWL<26388> A_IWL<26387> A_IWL<26386> A_IWL<26385> A_IWL<26384> A_IWL<26383> A_IWL<26382> A_IWL<26381> A_IWL<26380> A_IWL<26379> A_IWL<26378> A_IWL<26377> A_IWL<26376> A_IWL<26375> A_IWL<26374> A_IWL<26373> A_IWL<26372> A_IWL<26371> A_IWL<26370> A_IWL<26369> A_IWL<26368> A_IWL<26367> A_IWL<26366> A_IWL<26365> A_IWL<26364> A_IWL<26363> A_IWL<26362> A_IWL<26361> A_IWL<26360> A_IWL<26359> A_IWL<26358> A_IWL<26357> A_IWL<26356> A_IWL<26355> A_IWL<26354> A_IWL<26353> A_IWL<26352> A_IWL<26351> A_IWL<26350> A_IWL<26349> A_IWL<26348> A_IWL<26347> A_IWL<26346> A_IWL<26345> A_IWL<26344> A_IWL<26343> A_IWL<26342> A_IWL<26341> A_IWL<26340> A_IWL<26339> A_IWL<26338> A_IWL<26337> A_IWL<26336> A_IWL<26335> A_IWL<26334> A_IWL<26333> A_IWL<26332> A_IWL<26331> A_IWL<26330> A_IWL<26329> A_IWL<26328> A_IWL<26327> A_IWL<26326> A_IWL<26325> A_IWL<26324> A_IWL<26323> A_IWL<26322> A_IWL<26321> A_IWL<26320> A_IWL<26319> A_IWL<26318> A_IWL<26317> A_IWL<26316> A_IWL<26315> A_IWL<26314> A_IWL<26313> A_IWL<26312> A_IWL<26311> A_IWL<26310> A_IWL<26309> A_IWL<26308> A_IWL<26307> A_IWL<26306> A_IWL<26305> A_IWL<26304> A_IWL<26303> A_IWL<26302> A_IWL<26301> A_IWL<26300> A_IWL<26299> A_IWL<26298> A_IWL<26297> A_IWL<26296> A_IWL<26295> A_IWL<26294> A_IWL<26293> A_IWL<26292> A_IWL<26291> A_IWL<26290> A_IWL<26289> A_IWL<26288> A_IWL<26287> A_IWL<26286> A_IWL<26285> A_IWL<26284> A_IWL<26283> A_IWL<26282> A_IWL<26281> A_IWL<26280> A_IWL<26279> A_IWL<26278> A_IWL<26277> A_IWL<26276> A_IWL<26275> A_IWL<26274> A_IWL<26273> A_IWL<26272> A_IWL<26271> A_IWL<26270> A_IWL<26269> A_IWL<26268> A_IWL<26267> A_IWL<26266> A_IWL<26265> A_IWL<26264> A_IWL<26263> A_IWL<26262> A_IWL<26261> A_IWL<26260> A_IWL<26259> A_IWL<26258> A_IWL<26257> A_IWL<26256> A_IWL<26255> A_IWL<26254> A_IWL<26253> A_IWL<26252> A_IWL<26251> A_IWL<26250> A_IWL<26249> A_IWL<26248> A_IWL<26247> A_IWL<26246> A_IWL<26245> A_IWL<26244> A_IWL<26243> A_IWL<26242> A_IWL<26241> A_IWL<26240> A_IWL<26239> A_IWL<26238> A_IWL<26237> A_IWL<26236> A_IWL<26235> A_IWL<26234> A_IWL<26233> A_IWL<26232> A_IWL<26231> A_IWL<26230> A_IWL<26229> A_IWL<26228> A_IWL<26227> A_IWL<26226> A_IWL<26225> A_IWL<26224> A_IWL<26223> A_IWL<26222> A_IWL<26221> A_IWL<26220> A_IWL<26219> A_IWL<26218> A_IWL<26217> A_IWL<26216> A_IWL<26215> A_IWL<26214> A_IWL<26213> A_IWL<26212> A_IWL<26211> A_IWL<26210> A_IWL<26209> A_IWL<26208> A_IWL<26207> A_IWL<26206> A_IWL<26205> A_IWL<26204> A_IWL<26203> A_IWL<26202> A_IWL<26201> A_IWL<26200> A_IWL<26199> A_IWL<26198> A_IWL<26197> A_IWL<26196> A_IWL<26195> A_IWL<26194> A_IWL<26193> A_IWL<26192> A_IWL<26191> A_IWL<26190> A_IWL<26189> A_IWL<26188> A_IWL<26187> A_IWL<26186> A_IWL<26185> A_IWL<26184> A_IWL<26183> A_IWL<26182> A_IWL<26181> A_IWL<26180> A_IWL<26179> A_IWL<26178> A_IWL<26177> A_IWL<26176> A_IWL<26175> A_IWL<26174> A_IWL<26173> A_IWL<26172> A_IWL<26171> A_IWL<26170> A_IWL<26169> A_IWL<26168> A_IWL<26167> A_IWL<26166> A_IWL<26165> A_IWL<26164> A_IWL<26163> A_IWL<26162> A_IWL<26161> A_IWL<26160> A_IWL<26159> A_IWL<26158> A_IWL<26157> A_IWL<26156> A_IWL<26155> A_IWL<26154> A_IWL<26153> A_IWL<26152> A_IWL<26151> A_IWL<26150> A_IWL<26149> A_IWL<26148> A_IWL<26147> A_IWL<26146> A_IWL<26145> A_IWL<26144> A_IWL<26143> A_IWL<26142> A_IWL<26141> A_IWL<26140> A_IWL<26139> A_IWL<26138> A_IWL<26137> A_IWL<26136> A_IWL<26135> A_IWL<26134> A_IWL<26133> A_IWL<26132> A_IWL<26131> A_IWL<26130> A_IWL<26129> A_IWL<26128> A_IWL<26127> A_IWL<26126> A_IWL<26125> A_IWL<26124> A_IWL<26123> A_IWL<26122> A_IWL<26121> A_IWL<26120> A_IWL<26119> A_IWL<26118> A_IWL<26117> A_IWL<26116> A_IWL<26115> A_IWL<26114> A_IWL<26113> A_IWL<26112> A_IWL<27135> A_IWL<27134> A_IWL<27133> A_IWL<27132> A_IWL<27131> A_IWL<27130> A_IWL<27129> A_IWL<27128> A_IWL<27127> A_IWL<27126> A_IWL<27125> A_IWL<27124> A_IWL<27123> A_IWL<27122> A_IWL<27121> A_IWL<27120> A_IWL<27119> A_IWL<27118> A_IWL<27117> A_IWL<27116> A_IWL<27115> A_IWL<27114> A_IWL<27113> A_IWL<27112> A_IWL<27111> A_IWL<27110> A_IWL<27109> A_IWL<27108> A_IWL<27107> A_IWL<27106> A_IWL<27105> A_IWL<27104> A_IWL<27103> A_IWL<27102> A_IWL<27101> A_IWL<27100> A_IWL<27099> A_IWL<27098> A_IWL<27097> A_IWL<27096> A_IWL<27095> A_IWL<27094> A_IWL<27093> A_IWL<27092> A_IWL<27091> A_IWL<27090> A_IWL<27089> A_IWL<27088> A_IWL<27087> A_IWL<27086> A_IWL<27085> A_IWL<27084> A_IWL<27083> A_IWL<27082> A_IWL<27081> A_IWL<27080> A_IWL<27079> A_IWL<27078> A_IWL<27077> A_IWL<27076> A_IWL<27075> A_IWL<27074> A_IWL<27073> A_IWL<27072> A_IWL<27071> A_IWL<27070> A_IWL<27069> A_IWL<27068> A_IWL<27067> A_IWL<27066> A_IWL<27065> A_IWL<27064> A_IWL<27063> A_IWL<27062> A_IWL<27061> A_IWL<27060> A_IWL<27059> A_IWL<27058> A_IWL<27057> A_IWL<27056> A_IWL<27055> A_IWL<27054> A_IWL<27053> A_IWL<27052> A_IWL<27051> A_IWL<27050> A_IWL<27049> A_IWL<27048> A_IWL<27047> A_IWL<27046> A_IWL<27045> A_IWL<27044> A_IWL<27043> A_IWL<27042> A_IWL<27041> A_IWL<27040> A_IWL<27039> A_IWL<27038> A_IWL<27037> A_IWL<27036> A_IWL<27035> A_IWL<27034> A_IWL<27033> A_IWL<27032> A_IWL<27031> A_IWL<27030> A_IWL<27029> A_IWL<27028> A_IWL<27027> A_IWL<27026> A_IWL<27025> A_IWL<27024> A_IWL<27023> A_IWL<27022> A_IWL<27021> A_IWL<27020> A_IWL<27019> A_IWL<27018> A_IWL<27017> A_IWL<27016> A_IWL<27015> A_IWL<27014> A_IWL<27013> A_IWL<27012> A_IWL<27011> A_IWL<27010> A_IWL<27009> A_IWL<27008> A_IWL<27007> A_IWL<27006> A_IWL<27005> A_IWL<27004> A_IWL<27003> A_IWL<27002> A_IWL<27001> A_IWL<27000> A_IWL<26999> A_IWL<26998> A_IWL<26997> A_IWL<26996> A_IWL<26995> A_IWL<26994> A_IWL<26993> A_IWL<26992> A_IWL<26991> A_IWL<26990> A_IWL<26989> A_IWL<26988> A_IWL<26987> A_IWL<26986> A_IWL<26985> A_IWL<26984> A_IWL<26983> A_IWL<26982> A_IWL<26981> A_IWL<26980> A_IWL<26979> A_IWL<26978> A_IWL<26977> A_IWL<26976> A_IWL<26975> A_IWL<26974> A_IWL<26973> A_IWL<26972> A_IWL<26971> A_IWL<26970> A_IWL<26969> A_IWL<26968> A_IWL<26967> A_IWL<26966> A_IWL<26965> A_IWL<26964> A_IWL<26963> A_IWL<26962> A_IWL<26961> A_IWL<26960> A_IWL<26959> A_IWL<26958> A_IWL<26957> A_IWL<26956> A_IWL<26955> A_IWL<26954> A_IWL<26953> A_IWL<26952> A_IWL<26951> A_IWL<26950> A_IWL<26949> A_IWL<26948> A_IWL<26947> A_IWL<26946> A_IWL<26945> A_IWL<26944> A_IWL<26943> A_IWL<26942> A_IWL<26941> A_IWL<26940> A_IWL<26939> A_IWL<26938> A_IWL<26937> A_IWL<26936> A_IWL<26935> A_IWL<26934> A_IWL<26933> A_IWL<26932> A_IWL<26931> A_IWL<26930> A_IWL<26929> A_IWL<26928> A_IWL<26927> A_IWL<26926> A_IWL<26925> A_IWL<26924> A_IWL<26923> A_IWL<26922> A_IWL<26921> A_IWL<26920> A_IWL<26919> A_IWL<26918> A_IWL<26917> A_IWL<26916> A_IWL<26915> A_IWL<26914> A_IWL<26913> A_IWL<26912> A_IWL<26911> A_IWL<26910> A_IWL<26909> A_IWL<26908> A_IWL<26907> A_IWL<26906> A_IWL<26905> A_IWL<26904> A_IWL<26903> A_IWL<26902> A_IWL<26901> A_IWL<26900> A_IWL<26899> A_IWL<26898> A_IWL<26897> A_IWL<26896> A_IWL<26895> A_IWL<26894> A_IWL<26893> A_IWL<26892> A_IWL<26891> A_IWL<26890> A_IWL<26889> A_IWL<26888> A_IWL<26887> A_IWL<26886> A_IWL<26885> A_IWL<26884> A_IWL<26883> A_IWL<26882> A_IWL<26881> A_IWL<26880> A_IWL<26879> A_IWL<26878> A_IWL<26877> A_IWL<26876> A_IWL<26875> A_IWL<26874> A_IWL<26873> A_IWL<26872> A_IWL<26871> A_IWL<26870> A_IWL<26869> A_IWL<26868> A_IWL<26867> A_IWL<26866> A_IWL<26865> A_IWL<26864> A_IWL<26863> A_IWL<26862> A_IWL<26861> A_IWL<26860> A_IWL<26859> A_IWL<26858> A_IWL<26857> A_IWL<26856> A_IWL<26855> A_IWL<26854> A_IWL<26853> A_IWL<26852> A_IWL<26851> A_IWL<26850> A_IWL<26849> A_IWL<26848> A_IWL<26847> A_IWL<26846> A_IWL<26845> A_IWL<26844> A_IWL<26843> A_IWL<26842> A_IWL<26841> A_IWL<26840> A_IWL<26839> A_IWL<26838> A_IWL<26837> A_IWL<26836> A_IWL<26835> A_IWL<26834> A_IWL<26833> A_IWL<26832> A_IWL<26831> A_IWL<26830> A_IWL<26829> A_IWL<26828> A_IWL<26827> A_IWL<26826> A_IWL<26825> A_IWL<26824> A_IWL<26823> A_IWL<26822> A_IWL<26821> A_IWL<26820> A_IWL<26819> A_IWL<26818> A_IWL<26817> A_IWL<26816> A_IWL<26815> A_IWL<26814> A_IWL<26813> A_IWL<26812> A_IWL<26811> A_IWL<26810> A_IWL<26809> A_IWL<26808> A_IWL<26807> A_IWL<26806> A_IWL<26805> A_IWL<26804> A_IWL<26803> A_IWL<26802> A_IWL<26801> A_IWL<26800> A_IWL<26799> A_IWL<26798> A_IWL<26797> A_IWL<26796> A_IWL<26795> A_IWL<26794> A_IWL<26793> A_IWL<26792> A_IWL<26791> A_IWL<26790> A_IWL<26789> A_IWL<26788> A_IWL<26787> A_IWL<26786> A_IWL<26785> A_IWL<26784> A_IWL<26783> A_IWL<26782> A_IWL<26781> A_IWL<26780> A_IWL<26779> A_IWL<26778> A_IWL<26777> A_IWL<26776> A_IWL<26775> A_IWL<26774> A_IWL<26773> A_IWL<26772> A_IWL<26771> A_IWL<26770> A_IWL<26769> A_IWL<26768> A_IWL<26767> A_IWL<26766> A_IWL<26765> A_IWL<26764> A_IWL<26763> A_IWL<26762> A_IWL<26761> A_IWL<26760> A_IWL<26759> A_IWL<26758> A_IWL<26757> A_IWL<26756> A_IWL<26755> A_IWL<26754> A_IWL<26753> A_IWL<26752> A_IWL<26751> A_IWL<26750> A_IWL<26749> A_IWL<26748> A_IWL<26747> A_IWL<26746> A_IWL<26745> A_IWL<26744> A_IWL<26743> A_IWL<26742> A_IWL<26741> A_IWL<26740> A_IWL<26739> A_IWL<26738> A_IWL<26737> A_IWL<26736> A_IWL<26735> A_IWL<26734> A_IWL<26733> A_IWL<26732> A_IWL<26731> A_IWL<26730> A_IWL<26729> A_IWL<26728> A_IWL<26727> A_IWL<26726> A_IWL<26725> A_IWL<26724> A_IWL<26723> A_IWL<26722> A_IWL<26721> A_IWL<26720> A_IWL<26719> A_IWL<26718> A_IWL<26717> A_IWL<26716> A_IWL<26715> A_IWL<26714> A_IWL<26713> A_IWL<26712> A_IWL<26711> A_IWL<26710> A_IWL<26709> A_IWL<26708> A_IWL<26707> A_IWL<26706> A_IWL<26705> A_IWL<26704> A_IWL<26703> A_IWL<26702> A_IWL<26701> A_IWL<26700> A_IWL<26699> A_IWL<26698> A_IWL<26697> A_IWL<26696> A_IWL<26695> A_IWL<26694> A_IWL<26693> A_IWL<26692> A_IWL<26691> A_IWL<26690> A_IWL<26689> A_IWL<26688> A_IWL<26687> A_IWL<26686> A_IWL<26685> A_IWL<26684> A_IWL<26683> A_IWL<26682> A_IWL<26681> A_IWL<26680> A_IWL<26679> A_IWL<26678> A_IWL<26677> A_IWL<26676> A_IWL<26675> A_IWL<26674> A_IWL<26673> A_IWL<26672> A_IWL<26671> A_IWL<26670> A_IWL<26669> A_IWL<26668> A_IWL<26667> A_IWL<26666> A_IWL<26665> A_IWL<26664> A_IWL<26663> A_IWL<26662> A_IWL<26661> A_IWL<26660> A_IWL<26659> A_IWL<26658> A_IWL<26657> A_IWL<26656> A_IWL<26655> A_IWL<26654> A_IWL<26653> A_IWL<26652> A_IWL<26651> A_IWL<26650> A_IWL<26649> A_IWL<26648> A_IWL<26647> A_IWL<26646> A_IWL<26645> A_IWL<26644> A_IWL<26643> A_IWL<26642> A_IWL<26641> A_IWL<26640> A_IWL<26639> A_IWL<26638> A_IWL<26637> A_IWL<26636> A_IWL<26635> A_IWL<26634> A_IWL<26633> A_IWL<26632> A_IWL<26631> A_IWL<26630> A_IWL<26629> A_IWL<26628> A_IWL<26627> A_IWL<26626> A_IWL<26625> A_IWL<26624> VDD_CORE VSS / RM_IHPSG13_8192x32_c4_1P_COLUMN_pcell_0 +XCOL<51> A_BLC<103> A_BLC<102> A_BLC_TOP<103> A_BLC_TOP<102> A_BLT<103> A_BLT<102> A_BLT_TOP<103> A_BLT_TOP<102> A_IWL<26111> A_IWL<26110> A_IWL<26109> A_IWL<26108> A_IWL<26107> A_IWL<26106> A_IWL<26105> A_IWL<26104> A_IWL<26103> A_IWL<26102> A_IWL<26101> A_IWL<26100> A_IWL<26099> A_IWL<26098> A_IWL<26097> A_IWL<26096> A_IWL<26095> A_IWL<26094> A_IWL<26093> A_IWL<26092> A_IWL<26091> A_IWL<26090> A_IWL<26089> A_IWL<26088> A_IWL<26087> A_IWL<26086> A_IWL<26085> A_IWL<26084> A_IWL<26083> A_IWL<26082> A_IWL<26081> A_IWL<26080> A_IWL<26079> A_IWL<26078> A_IWL<26077> A_IWL<26076> A_IWL<26075> A_IWL<26074> A_IWL<26073> A_IWL<26072> A_IWL<26071> A_IWL<26070> A_IWL<26069> A_IWL<26068> A_IWL<26067> A_IWL<26066> A_IWL<26065> A_IWL<26064> A_IWL<26063> A_IWL<26062> A_IWL<26061> A_IWL<26060> A_IWL<26059> A_IWL<26058> A_IWL<26057> A_IWL<26056> A_IWL<26055> A_IWL<26054> A_IWL<26053> A_IWL<26052> A_IWL<26051> A_IWL<26050> A_IWL<26049> A_IWL<26048> A_IWL<26047> A_IWL<26046> A_IWL<26045> A_IWL<26044> A_IWL<26043> A_IWL<26042> A_IWL<26041> A_IWL<26040> A_IWL<26039> A_IWL<26038> A_IWL<26037> A_IWL<26036> A_IWL<26035> A_IWL<26034> A_IWL<26033> A_IWL<26032> A_IWL<26031> A_IWL<26030> A_IWL<26029> A_IWL<26028> A_IWL<26027> A_IWL<26026> A_IWL<26025> A_IWL<26024> A_IWL<26023> A_IWL<26022> A_IWL<26021> A_IWL<26020> A_IWL<26019> A_IWL<26018> A_IWL<26017> A_IWL<26016> A_IWL<26015> A_IWL<26014> A_IWL<26013> A_IWL<26012> A_IWL<26011> A_IWL<26010> A_IWL<26009> A_IWL<26008> A_IWL<26007> A_IWL<26006> A_IWL<26005> A_IWL<26004> A_IWL<26003> A_IWL<26002> A_IWL<26001> A_IWL<26000> A_IWL<25999> A_IWL<25998> A_IWL<25997> A_IWL<25996> A_IWL<25995> A_IWL<25994> A_IWL<25993> A_IWL<25992> A_IWL<25991> A_IWL<25990> A_IWL<25989> A_IWL<25988> A_IWL<25987> A_IWL<25986> A_IWL<25985> A_IWL<25984> A_IWL<25983> A_IWL<25982> A_IWL<25981> A_IWL<25980> A_IWL<25979> A_IWL<25978> A_IWL<25977> A_IWL<25976> A_IWL<25975> A_IWL<25974> A_IWL<25973> A_IWL<25972> A_IWL<25971> A_IWL<25970> A_IWL<25969> A_IWL<25968> A_IWL<25967> A_IWL<25966> A_IWL<25965> A_IWL<25964> A_IWL<25963> A_IWL<25962> A_IWL<25961> A_IWL<25960> A_IWL<25959> A_IWL<25958> A_IWL<25957> A_IWL<25956> A_IWL<25955> A_IWL<25954> A_IWL<25953> A_IWL<25952> A_IWL<25951> A_IWL<25950> A_IWL<25949> A_IWL<25948> A_IWL<25947> A_IWL<25946> A_IWL<25945> A_IWL<25944> A_IWL<25943> A_IWL<25942> A_IWL<25941> A_IWL<25940> A_IWL<25939> A_IWL<25938> A_IWL<25937> A_IWL<25936> A_IWL<25935> A_IWL<25934> A_IWL<25933> A_IWL<25932> A_IWL<25931> A_IWL<25930> A_IWL<25929> A_IWL<25928> A_IWL<25927> A_IWL<25926> A_IWL<25925> A_IWL<25924> A_IWL<25923> A_IWL<25922> A_IWL<25921> A_IWL<25920> A_IWL<25919> A_IWL<25918> A_IWL<25917> A_IWL<25916> A_IWL<25915> A_IWL<25914> A_IWL<25913> A_IWL<25912> A_IWL<25911> A_IWL<25910> A_IWL<25909> A_IWL<25908> A_IWL<25907> A_IWL<25906> A_IWL<25905> A_IWL<25904> A_IWL<25903> A_IWL<25902> A_IWL<25901> A_IWL<25900> A_IWL<25899> A_IWL<25898> A_IWL<25897> A_IWL<25896> A_IWL<25895> A_IWL<25894> A_IWL<25893> A_IWL<25892> A_IWL<25891> A_IWL<25890> A_IWL<25889> A_IWL<25888> A_IWL<25887> A_IWL<25886> A_IWL<25885> A_IWL<25884> A_IWL<25883> A_IWL<25882> A_IWL<25881> A_IWL<25880> A_IWL<25879> A_IWL<25878> A_IWL<25877> A_IWL<25876> A_IWL<25875> A_IWL<25874> A_IWL<25873> A_IWL<25872> A_IWL<25871> A_IWL<25870> A_IWL<25869> A_IWL<25868> A_IWL<25867> A_IWL<25866> A_IWL<25865> A_IWL<25864> A_IWL<25863> A_IWL<25862> A_IWL<25861> A_IWL<25860> A_IWL<25859> A_IWL<25858> A_IWL<25857> A_IWL<25856> A_IWL<25855> A_IWL<25854> A_IWL<25853> A_IWL<25852> A_IWL<25851> A_IWL<25850> A_IWL<25849> A_IWL<25848> A_IWL<25847> A_IWL<25846> A_IWL<25845> A_IWL<25844> A_IWL<25843> A_IWL<25842> A_IWL<25841> A_IWL<25840> A_IWL<25839> A_IWL<25838> A_IWL<25837> A_IWL<25836> A_IWL<25835> A_IWL<25834> A_IWL<25833> A_IWL<25832> A_IWL<25831> A_IWL<25830> A_IWL<25829> A_IWL<25828> A_IWL<25827> A_IWL<25826> A_IWL<25825> A_IWL<25824> A_IWL<25823> A_IWL<25822> A_IWL<25821> A_IWL<25820> A_IWL<25819> A_IWL<25818> A_IWL<25817> A_IWL<25816> A_IWL<25815> A_IWL<25814> A_IWL<25813> A_IWL<25812> A_IWL<25811> A_IWL<25810> A_IWL<25809> A_IWL<25808> A_IWL<25807> A_IWL<25806> A_IWL<25805> A_IWL<25804> A_IWL<25803> A_IWL<25802> A_IWL<25801> A_IWL<25800> A_IWL<25799> A_IWL<25798> A_IWL<25797> A_IWL<25796> A_IWL<25795> A_IWL<25794> A_IWL<25793> A_IWL<25792> A_IWL<25791> A_IWL<25790> A_IWL<25789> A_IWL<25788> A_IWL<25787> A_IWL<25786> A_IWL<25785> A_IWL<25784> A_IWL<25783> A_IWL<25782> A_IWL<25781> A_IWL<25780> A_IWL<25779> A_IWL<25778> A_IWL<25777> A_IWL<25776> A_IWL<25775> A_IWL<25774> A_IWL<25773> A_IWL<25772> A_IWL<25771> A_IWL<25770> A_IWL<25769> A_IWL<25768> A_IWL<25767> A_IWL<25766> A_IWL<25765> A_IWL<25764> A_IWL<25763> A_IWL<25762> A_IWL<25761> A_IWL<25760> A_IWL<25759> A_IWL<25758> A_IWL<25757> A_IWL<25756> A_IWL<25755> A_IWL<25754> A_IWL<25753> A_IWL<25752> A_IWL<25751> A_IWL<25750> A_IWL<25749> A_IWL<25748> A_IWL<25747> A_IWL<25746> A_IWL<25745> A_IWL<25744> A_IWL<25743> A_IWL<25742> A_IWL<25741> A_IWL<25740> A_IWL<25739> A_IWL<25738> A_IWL<25737> A_IWL<25736> A_IWL<25735> A_IWL<25734> A_IWL<25733> A_IWL<25732> A_IWL<25731> A_IWL<25730> A_IWL<25729> A_IWL<25728> A_IWL<25727> A_IWL<25726> A_IWL<25725> A_IWL<25724> A_IWL<25723> A_IWL<25722> A_IWL<25721> A_IWL<25720> A_IWL<25719> A_IWL<25718> A_IWL<25717> A_IWL<25716> A_IWL<25715> A_IWL<25714> A_IWL<25713> A_IWL<25712> A_IWL<25711> A_IWL<25710> A_IWL<25709> A_IWL<25708> A_IWL<25707> A_IWL<25706> A_IWL<25705> A_IWL<25704> A_IWL<25703> A_IWL<25702> A_IWL<25701> A_IWL<25700> A_IWL<25699> A_IWL<25698> A_IWL<25697> A_IWL<25696> A_IWL<25695> A_IWL<25694> A_IWL<25693> A_IWL<25692> A_IWL<25691> A_IWL<25690> A_IWL<25689> A_IWL<25688> A_IWL<25687> A_IWL<25686> A_IWL<25685> A_IWL<25684> A_IWL<25683> A_IWL<25682> A_IWL<25681> A_IWL<25680> A_IWL<25679> A_IWL<25678> A_IWL<25677> A_IWL<25676> A_IWL<25675> A_IWL<25674> A_IWL<25673> A_IWL<25672> A_IWL<25671> A_IWL<25670> A_IWL<25669> A_IWL<25668> A_IWL<25667> A_IWL<25666> A_IWL<25665> A_IWL<25664> A_IWL<25663> A_IWL<25662> A_IWL<25661> A_IWL<25660> A_IWL<25659> A_IWL<25658> A_IWL<25657> A_IWL<25656> A_IWL<25655> A_IWL<25654> A_IWL<25653> A_IWL<25652> A_IWL<25651> A_IWL<25650> A_IWL<25649> A_IWL<25648> A_IWL<25647> A_IWL<25646> A_IWL<25645> A_IWL<25644> A_IWL<25643> A_IWL<25642> A_IWL<25641> A_IWL<25640> A_IWL<25639> A_IWL<25638> A_IWL<25637> A_IWL<25636> A_IWL<25635> A_IWL<25634> A_IWL<25633> A_IWL<25632> A_IWL<25631> A_IWL<25630> A_IWL<25629> A_IWL<25628> A_IWL<25627> A_IWL<25626> A_IWL<25625> A_IWL<25624> A_IWL<25623> A_IWL<25622> A_IWL<25621> A_IWL<25620> A_IWL<25619> A_IWL<25618> A_IWL<25617> A_IWL<25616> A_IWL<25615> A_IWL<25614> A_IWL<25613> A_IWL<25612> A_IWL<25611> A_IWL<25610> A_IWL<25609> A_IWL<25608> A_IWL<25607> A_IWL<25606> A_IWL<25605> A_IWL<25604> A_IWL<25603> A_IWL<25602> A_IWL<25601> A_IWL<25600> A_IWL<26623> A_IWL<26622> A_IWL<26621> A_IWL<26620> A_IWL<26619> A_IWL<26618> A_IWL<26617> A_IWL<26616> A_IWL<26615> A_IWL<26614> A_IWL<26613> A_IWL<26612> A_IWL<26611> A_IWL<26610> A_IWL<26609> A_IWL<26608> A_IWL<26607> A_IWL<26606> A_IWL<26605> A_IWL<26604> A_IWL<26603> A_IWL<26602> A_IWL<26601> A_IWL<26600> A_IWL<26599> A_IWL<26598> A_IWL<26597> A_IWL<26596> A_IWL<26595> A_IWL<26594> A_IWL<26593> A_IWL<26592> A_IWL<26591> A_IWL<26590> A_IWL<26589> A_IWL<26588> A_IWL<26587> A_IWL<26586> A_IWL<26585> A_IWL<26584> A_IWL<26583> A_IWL<26582> A_IWL<26581> A_IWL<26580> A_IWL<26579> A_IWL<26578> A_IWL<26577> A_IWL<26576> A_IWL<26575> A_IWL<26574> A_IWL<26573> A_IWL<26572> A_IWL<26571> A_IWL<26570> A_IWL<26569> A_IWL<26568> A_IWL<26567> A_IWL<26566> A_IWL<26565> A_IWL<26564> A_IWL<26563> A_IWL<26562> A_IWL<26561> A_IWL<26560> A_IWL<26559> A_IWL<26558> A_IWL<26557> A_IWL<26556> A_IWL<26555> A_IWL<26554> A_IWL<26553> A_IWL<26552> A_IWL<26551> A_IWL<26550> A_IWL<26549> A_IWL<26548> A_IWL<26547> A_IWL<26546> A_IWL<26545> A_IWL<26544> A_IWL<26543> A_IWL<26542> A_IWL<26541> A_IWL<26540> A_IWL<26539> A_IWL<26538> A_IWL<26537> A_IWL<26536> A_IWL<26535> A_IWL<26534> A_IWL<26533> A_IWL<26532> A_IWL<26531> A_IWL<26530> A_IWL<26529> A_IWL<26528> A_IWL<26527> A_IWL<26526> A_IWL<26525> A_IWL<26524> A_IWL<26523> A_IWL<26522> A_IWL<26521> A_IWL<26520> A_IWL<26519> A_IWL<26518> A_IWL<26517> A_IWL<26516> A_IWL<26515> A_IWL<26514> A_IWL<26513> A_IWL<26512> A_IWL<26511> A_IWL<26510> A_IWL<26509> A_IWL<26508> A_IWL<26507> A_IWL<26506> A_IWL<26505> A_IWL<26504> A_IWL<26503> A_IWL<26502> A_IWL<26501> A_IWL<26500> A_IWL<26499> A_IWL<26498> A_IWL<26497> A_IWL<26496> A_IWL<26495> A_IWL<26494> A_IWL<26493> A_IWL<26492> A_IWL<26491> A_IWL<26490> A_IWL<26489> A_IWL<26488> A_IWL<26487> A_IWL<26486> A_IWL<26485> A_IWL<26484> A_IWL<26483> A_IWL<26482> A_IWL<26481> A_IWL<26480> A_IWL<26479> A_IWL<26478> A_IWL<26477> A_IWL<26476> A_IWL<26475> A_IWL<26474> A_IWL<26473> A_IWL<26472> A_IWL<26471> A_IWL<26470> A_IWL<26469> A_IWL<26468> A_IWL<26467> A_IWL<26466> A_IWL<26465> A_IWL<26464> A_IWL<26463> A_IWL<26462> A_IWL<26461> A_IWL<26460> A_IWL<26459> A_IWL<26458> A_IWL<26457> A_IWL<26456> A_IWL<26455> A_IWL<26454> A_IWL<26453> A_IWL<26452> A_IWL<26451> A_IWL<26450> A_IWL<26449> A_IWL<26448> A_IWL<26447> A_IWL<26446> A_IWL<26445> A_IWL<26444> A_IWL<26443> A_IWL<26442> A_IWL<26441> A_IWL<26440> A_IWL<26439> A_IWL<26438> A_IWL<26437> A_IWL<26436> A_IWL<26435> A_IWL<26434> A_IWL<26433> A_IWL<26432> A_IWL<26431> A_IWL<26430> A_IWL<26429> A_IWL<26428> A_IWL<26427> A_IWL<26426> A_IWL<26425> A_IWL<26424> A_IWL<26423> A_IWL<26422> A_IWL<26421> A_IWL<26420> A_IWL<26419> A_IWL<26418> A_IWL<26417> A_IWL<26416> A_IWL<26415> A_IWL<26414> A_IWL<26413> A_IWL<26412> A_IWL<26411> A_IWL<26410> A_IWL<26409> A_IWL<26408> A_IWL<26407> A_IWL<26406> A_IWL<26405> A_IWL<26404> A_IWL<26403> A_IWL<26402> A_IWL<26401> A_IWL<26400> A_IWL<26399> A_IWL<26398> A_IWL<26397> A_IWL<26396> A_IWL<26395> A_IWL<26394> A_IWL<26393> A_IWL<26392> A_IWL<26391> A_IWL<26390> A_IWL<26389> A_IWL<26388> A_IWL<26387> A_IWL<26386> A_IWL<26385> A_IWL<26384> A_IWL<26383> A_IWL<26382> A_IWL<26381> A_IWL<26380> A_IWL<26379> A_IWL<26378> A_IWL<26377> A_IWL<26376> A_IWL<26375> A_IWL<26374> A_IWL<26373> A_IWL<26372> A_IWL<26371> A_IWL<26370> A_IWL<26369> A_IWL<26368> A_IWL<26367> A_IWL<26366> A_IWL<26365> A_IWL<26364> A_IWL<26363> A_IWL<26362> A_IWL<26361> A_IWL<26360> A_IWL<26359> A_IWL<26358> A_IWL<26357> A_IWL<26356> A_IWL<26355> A_IWL<26354> A_IWL<26353> A_IWL<26352> A_IWL<26351> A_IWL<26350> A_IWL<26349> A_IWL<26348> A_IWL<26347> A_IWL<26346> A_IWL<26345> A_IWL<26344> A_IWL<26343> A_IWL<26342> A_IWL<26341> A_IWL<26340> A_IWL<26339> A_IWL<26338> A_IWL<26337> A_IWL<26336> A_IWL<26335> A_IWL<26334> A_IWL<26333> A_IWL<26332> A_IWL<26331> A_IWL<26330> A_IWL<26329> A_IWL<26328> A_IWL<26327> A_IWL<26326> A_IWL<26325> A_IWL<26324> A_IWL<26323> A_IWL<26322> A_IWL<26321> A_IWL<26320> A_IWL<26319> A_IWL<26318> A_IWL<26317> A_IWL<26316> A_IWL<26315> A_IWL<26314> A_IWL<26313> A_IWL<26312> A_IWL<26311> A_IWL<26310> A_IWL<26309> A_IWL<26308> A_IWL<26307> A_IWL<26306> A_IWL<26305> A_IWL<26304> A_IWL<26303> A_IWL<26302> A_IWL<26301> A_IWL<26300> A_IWL<26299> A_IWL<26298> A_IWL<26297> A_IWL<26296> A_IWL<26295> A_IWL<26294> A_IWL<26293> A_IWL<26292> A_IWL<26291> A_IWL<26290> A_IWL<26289> A_IWL<26288> A_IWL<26287> A_IWL<26286> A_IWL<26285> A_IWL<26284> A_IWL<26283> A_IWL<26282> A_IWL<26281> A_IWL<26280> A_IWL<26279> A_IWL<26278> A_IWL<26277> A_IWL<26276> A_IWL<26275> A_IWL<26274> A_IWL<26273> A_IWL<26272> A_IWL<26271> A_IWL<26270> A_IWL<26269> A_IWL<26268> A_IWL<26267> A_IWL<26266> A_IWL<26265> A_IWL<26264> A_IWL<26263> A_IWL<26262> A_IWL<26261> A_IWL<26260> A_IWL<26259> A_IWL<26258> A_IWL<26257> A_IWL<26256> A_IWL<26255> A_IWL<26254> A_IWL<26253> A_IWL<26252> A_IWL<26251> A_IWL<26250> A_IWL<26249> A_IWL<26248> A_IWL<26247> A_IWL<26246> A_IWL<26245> A_IWL<26244> A_IWL<26243> A_IWL<26242> A_IWL<26241> A_IWL<26240> A_IWL<26239> A_IWL<26238> A_IWL<26237> A_IWL<26236> A_IWL<26235> A_IWL<26234> A_IWL<26233> A_IWL<26232> A_IWL<26231> A_IWL<26230> A_IWL<26229> A_IWL<26228> A_IWL<26227> A_IWL<26226> A_IWL<26225> A_IWL<26224> A_IWL<26223> A_IWL<26222> A_IWL<26221> A_IWL<26220> A_IWL<26219> A_IWL<26218> A_IWL<26217> A_IWL<26216> A_IWL<26215> A_IWL<26214> A_IWL<26213> A_IWL<26212> A_IWL<26211> A_IWL<26210> A_IWL<26209> A_IWL<26208> A_IWL<26207> A_IWL<26206> A_IWL<26205> A_IWL<26204> A_IWL<26203> A_IWL<26202> A_IWL<26201> A_IWL<26200> A_IWL<26199> A_IWL<26198> A_IWL<26197> A_IWL<26196> A_IWL<26195> A_IWL<26194> A_IWL<26193> A_IWL<26192> A_IWL<26191> A_IWL<26190> A_IWL<26189> A_IWL<26188> A_IWL<26187> A_IWL<26186> A_IWL<26185> A_IWL<26184> A_IWL<26183> A_IWL<26182> A_IWL<26181> A_IWL<26180> A_IWL<26179> A_IWL<26178> A_IWL<26177> A_IWL<26176> A_IWL<26175> A_IWL<26174> A_IWL<26173> A_IWL<26172> A_IWL<26171> A_IWL<26170> A_IWL<26169> A_IWL<26168> A_IWL<26167> A_IWL<26166> A_IWL<26165> A_IWL<26164> A_IWL<26163> A_IWL<26162> A_IWL<26161> A_IWL<26160> A_IWL<26159> A_IWL<26158> A_IWL<26157> A_IWL<26156> A_IWL<26155> A_IWL<26154> A_IWL<26153> A_IWL<26152> A_IWL<26151> A_IWL<26150> A_IWL<26149> A_IWL<26148> A_IWL<26147> A_IWL<26146> A_IWL<26145> A_IWL<26144> A_IWL<26143> A_IWL<26142> A_IWL<26141> A_IWL<26140> A_IWL<26139> A_IWL<26138> A_IWL<26137> A_IWL<26136> A_IWL<26135> A_IWL<26134> A_IWL<26133> A_IWL<26132> A_IWL<26131> A_IWL<26130> A_IWL<26129> A_IWL<26128> A_IWL<26127> A_IWL<26126> A_IWL<26125> A_IWL<26124> A_IWL<26123> A_IWL<26122> A_IWL<26121> A_IWL<26120> A_IWL<26119> A_IWL<26118> A_IWL<26117> A_IWL<26116> A_IWL<26115> A_IWL<26114> A_IWL<26113> A_IWL<26112> VDD_CORE VSS / RM_IHPSG13_8192x32_c4_1P_COLUMN_pcell_0 +XCOL<50> A_BLC<101> A_BLC<100> A_BLC_TOP<101> A_BLC_TOP<100> A_BLT<101> A_BLT<100> A_BLT_TOP<101> A_BLT_TOP<100> A_IWL<25599> A_IWL<25598> A_IWL<25597> A_IWL<25596> A_IWL<25595> A_IWL<25594> A_IWL<25593> A_IWL<25592> A_IWL<25591> A_IWL<25590> A_IWL<25589> A_IWL<25588> A_IWL<25587> A_IWL<25586> A_IWL<25585> A_IWL<25584> A_IWL<25583> A_IWL<25582> A_IWL<25581> A_IWL<25580> A_IWL<25579> A_IWL<25578> A_IWL<25577> A_IWL<25576> A_IWL<25575> A_IWL<25574> A_IWL<25573> A_IWL<25572> A_IWL<25571> A_IWL<25570> A_IWL<25569> A_IWL<25568> A_IWL<25567> A_IWL<25566> A_IWL<25565> A_IWL<25564> A_IWL<25563> A_IWL<25562> A_IWL<25561> A_IWL<25560> A_IWL<25559> A_IWL<25558> A_IWL<25557> A_IWL<25556> A_IWL<25555> A_IWL<25554> A_IWL<25553> A_IWL<25552> A_IWL<25551> A_IWL<25550> A_IWL<25549> A_IWL<25548> A_IWL<25547> A_IWL<25546> A_IWL<25545> A_IWL<25544> A_IWL<25543> A_IWL<25542> A_IWL<25541> A_IWL<25540> A_IWL<25539> A_IWL<25538> A_IWL<25537> A_IWL<25536> A_IWL<25535> A_IWL<25534> A_IWL<25533> A_IWL<25532> A_IWL<25531> A_IWL<25530> A_IWL<25529> A_IWL<25528> A_IWL<25527> A_IWL<25526> A_IWL<25525> A_IWL<25524> A_IWL<25523> A_IWL<25522> A_IWL<25521> A_IWL<25520> A_IWL<25519> A_IWL<25518> A_IWL<25517> A_IWL<25516> A_IWL<25515> A_IWL<25514> A_IWL<25513> A_IWL<25512> A_IWL<25511> A_IWL<25510> A_IWL<25509> A_IWL<25508> A_IWL<25507> A_IWL<25506> A_IWL<25505> A_IWL<25504> A_IWL<25503> A_IWL<25502> A_IWL<25501> A_IWL<25500> A_IWL<25499> A_IWL<25498> A_IWL<25497> A_IWL<25496> A_IWL<25495> A_IWL<25494> A_IWL<25493> A_IWL<25492> A_IWL<25491> A_IWL<25490> A_IWL<25489> A_IWL<25488> A_IWL<25487> A_IWL<25486> A_IWL<25485> A_IWL<25484> A_IWL<25483> A_IWL<25482> A_IWL<25481> A_IWL<25480> A_IWL<25479> A_IWL<25478> A_IWL<25477> A_IWL<25476> A_IWL<25475> A_IWL<25474> A_IWL<25473> A_IWL<25472> A_IWL<25471> A_IWL<25470> A_IWL<25469> A_IWL<25468> A_IWL<25467> A_IWL<25466> A_IWL<25465> A_IWL<25464> A_IWL<25463> A_IWL<25462> A_IWL<25461> A_IWL<25460> A_IWL<25459> A_IWL<25458> A_IWL<25457> A_IWL<25456> A_IWL<25455> A_IWL<25454> A_IWL<25453> A_IWL<25452> A_IWL<25451> A_IWL<25450> A_IWL<25449> A_IWL<25448> A_IWL<25447> A_IWL<25446> A_IWL<25445> A_IWL<25444> A_IWL<25443> A_IWL<25442> A_IWL<25441> A_IWL<25440> A_IWL<25439> A_IWL<25438> A_IWL<25437> A_IWL<25436> A_IWL<25435> A_IWL<25434> A_IWL<25433> A_IWL<25432> A_IWL<25431> A_IWL<25430> A_IWL<25429> A_IWL<25428> A_IWL<25427> A_IWL<25426> A_IWL<25425> A_IWL<25424> A_IWL<25423> A_IWL<25422> A_IWL<25421> A_IWL<25420> A_IWL<25419> A_IWL<25418> A_IWL<25417> A_IWL<25416> A_IWL<25415> A_IWL<25414> A_IWL<25413> A_IWL<25412> A_IWL<25411> A_IWL<25410> A_IWL<25409> A_IWL<25408> A_IWL<25407> A_IWL<25406> A_IWL<25405> A_IWL<25404> A_IWL<25403> A_IWL<25402> A_IWL<25401> A_IWL<25400> A_IWL<25399> A_IWL<25398> A_IWL<25397> A_IWL<25396> A_IWL<25395> A_IWL<25394> A_IWL<25393> A_IWL<25392> A_IWL<25391> A_IWL<25390> A_IWL<25389> A_IWL<25388> A_IWL<25387> A_IWL<25386> A_IWL<25385> A_IWL<25384> A_IWL<25383> A_IWL<25382> A_IWL<25381> A_IWL<25380> A_IWL<25379> A_IWL<25378> A_IWL<25377> A_IWL<25376> A_IWL<25375> A_IWL<25374> A_IWL<25373> A_IWL<25372> A_IWL<25371> A_IWL<25370> A_IWL<25369> A_IWL<25368> A_IWL<25367> A_IWL<25366> A_IWL<25365> A_IWL<25364> A_IWL<25363> A_IWL<25362> A_IWL<25361> A_IWL<25360> A_IWL<25359> A_IWL<25358> A_IWL<25357> A_IWL<25356> A_IWL<25355> A_IWL<25354> A_IWL<25353> A_IWL<25352> A_IWL<25351> A_IWL<25350> A_IWL<25349> A_IWL<25348> A_IWL<25347> A_IWL<25346> A_IWL<25345> A_IWL<25344> A_IWL<25343> A_IWL<25342> A_IWL<25341> A_IWL<25340> A_IWL<25339> A_IWL<25338> A_IWL<25337> A_IWL<25336> A_IWL<25335> A_IWL<25334> A_IWL<25333> A_IWL<25332> A_IWL<25331> A_IWL<25330> A_IWL<25329> A_IWL<25328> A_IWL<25327> A_IWL<25326> A_IWL<25325> A_IWL<25324> A_IWL<25323> A_IWL<25322> A_IWL<25321> A_IWL<25320> A_IWL<25319> A_IWL<25318> A_IWL<25317> A_IWL<25316> A_IWL<25315> A_IWL<25314> A_IWL<25313> A_IWL<25312> A_IWL<25311> A_IWL<25310> A_IWL<25309> A_IWL<25308> A_IWL<25307> A_IWL<25306> A_IWL<25305> A_IWL<25304> A_IWL<25303> A_IWL<25302> A_IWL<25301> A_IWL<25300> A_IWL<25299> A_IWL<25298> A_IWL<25297> A_IWL<25296> A_IWL<25295> A_IWL<25294> A_IWL<25293> A_IWL<25292> A_IWL<25291> A_IWL<25290> A_IWL<25289> A_IWL<25288> A_IWL<25287> A_IWL<25286> A_IWL<25285> A_IWL<25284> A_IWL<25283> A_IWL<25282> A_IWL<25281> A_IWL<25280> A_IWL<25279> A_IWL<25278> A_IWL<25277> A_IWL<25276> A_IWL<25275> A_IWL<25274> A_IWL<25273> A_IWL<25272> A_IWL<25271> A_IWL<25270> A_IWL<25269> A_IWL<25268> A_IWL<25267> A_IWL<25266> A_IWL<25265> A_IWL<25264> A_IWL<25263> A_IWL<25262> A_IWL<25261> A_IWL<25260> A_IWL<25259> A_IWL<25258> A_IWL<25257> A_IWL<25256> A_IWL<25255> A_IWL<25254> A_IWL<25253> A_IWL<25252> A_IWL<25251> A_IWL<25250> A_IWL<25249> A_IWL<25248> A_IWL<25247> A_IWL<25246> A_IWL<25245> A_IWL<25244> A_IWL<25243> A_IWL<25242> A_IWL<25241> A_IWL<25240> A_IWL<25239> A_IWL<25238> A_IWL<25237> A_IWL<25236> A_IWL<25235> A_IWL<25234> A_IWL<25233> A_IWL<25232> A_IWL<25231> A_IWL<25230> A_IWL<25229> A_IWL<25228> A_IWL<25227> A_IWL<25226> A_IWL<25225> A_IWL<25224> A_IWL<25223> A_IWL<25222> A_IWL<25221> A_IWL<25220> A_IWL<25219> A_IWL<25218> A_IWL<25217> A_IWL<25216> A_IWL<25215> A_IWL<25214> A_IWL<25213> A_IWL<25212> A_IWL<25211> A_IWL<25210> A_IWL<25209> A_IWL<25208> A_IWL<25207> A_IWL<25206> A_IWL<25205> A_IWL<25204> A_IWL<25203> A_IWL<25202> A_IWL<25201> A_IWL<25200> A_IWL<25199> A_IWL<25198> A_IWL<25197> A_IWL<25196> A_IWL<25195> A_IWL<25194> A_IWL<25193> A_IWL<25192> A_IWL<25191> A_IWL<25190> A_IWL<25189> A_IWL<25188> A_IWL<25187> A_IWL<25186> A_IWL<25185> A_IWL<25184> A_IWL<25183> A_IWL<25182> A_IWL<25181> A_IWL<25180> A_IWL<25179> A_IWL<25178> A_IWL<25177> A_IWL<25176> A_IWL<25175> A_IWL<25174> A_IWL<25173> A_IWL<25172> A_IWL<25171> A_IWL<25170> A_IWL<25169> A_IWL<25168> A_IWL<25167> A_IWL<25166> A_IWL<25165> A_IWL<25164> A_IWL<25163> A_IWL<25162> A_IWL<25161> A_IWL<25160> A_IWL<25159> A_IWL<25158> A_IWL<25157> A_IWL<25156> A_IWL<25155> A_IWL<25154> A_IWL<25153> A_IWL<25152> A_IWL<25151> A_IWL<25150> A_IWL<25149> A_IWL<25148> A_IWL<25147> A_IWL<25146> A_IWL<25145> A_IWL<25144> A_IWL<25143> A_IWL<25142> A_IWL<25141> A_IWL<25140> A_IWL<25139> A_IWL<25138> A_IWL<25137> A_IWL<25136> A_IWL<25135> A_IWL<25134> A_IWL<25133> A_IWL<25132> A_IWL<25131> A_IWL<25130> A_IWL<25129> A_IWL<25128> A_IWL<25127> A_IWL<25126> A_IWL<25125> A_IWL<25124> A_IWL<25123> A_IWL<25122> A_IWL<25121> A_IWL<25120> A_IWL<25119> A_IWL<25118> A_IWL<25117> A_IWL<25116> A_IWL<25115> A_IWL<25114> A_IWL<25113> A_IWL<25112> A_IWL<25111> A_IWL<25110> A_IWL<25109> A_IWL<25108> A_IWL<25107> A_IWL<25106> A_IWL<25105> A_IWL<25104> A_IWL<25103> A_IWL<25102> A_IWL<25101> A_IWL<25100> A_IWL<25099> A_IWL<25098> A_IWL<25097> A_IWL<25096> A_IWL<25095> A_IWL<25094> A_IWL<25093> A_IWL<25092> A_IWL<25091> A_IWL<25090> A_IWL<25089> A_IWL<25088> A_IWL<26111> A_IWL<26110> A_IWL<26109> A_IWL<26108> A_IWL<26107> A_IWL<26106> A_IWL<26105> A_IWL<26104> A_IWL<26103> A_IWL<26102> A_IWL<26101> A_IWL<26100> A_IWL<26099> A_IWL<26098> A_IWL<26097> A_IWL<26096> A_IWL<26095> A_IWL<26094> A_IWL<26093> A_IWL<26092> A_IWL<26091> A_IWL<26090> A_IWL<26089> A_IWL<26088> A_IWL<26087> A_IWL<26086> A_IWL<26085> A_IWL<26084> A_IWL<26083> A_IWL<26082> A_IWL<26081> A_IWL<26080> A_IWL<26079> A_IWL<26078> A_IWL<26077> A_IWL<26076> A_IWL<26075> A_IWL<26074> A_IWL<26073> A_IWL<26072> A_IWL<26071> A_IWL<26070> A_IWL<26069> A_IWL<26068> A_IWL<26067> A_IWL<26066> A_IWL<26065> A_IWL<26064> A_IWL<26063> A_IWL<26062> A_IWL<26061> A_IWL<26060> A_IWL<26059> A_IWL<26058> A_IWL<26057> A_IWL<26056> A_IWL<26055> A_IWL<26054> A_IWL<26053> A_IWL<26052> A_IWL<26051> A_IWL<26050> A_IWL<26049> A_IWL<26048> A_IWL<26047> A_IWL<26046> A_IWL<26045> A_IWL<26044> A_IWL<26043> A_IWL<26042> A_IWL<26041> A_IWL<26040> A_IWL<26039> A_IWL<26038> A_IWL<26037> A_IWL<26036> A_IWL<26035> A_IWL<26034> A_IWL<26033> A_IWL<26032> A_IWL<26031> A_IWL<26030> A_IWL<26029> A_IWL<26028> A_IWL<26027> A_IWL<26026> A_IWL<26025> A_IWL<26024> A_IWL<26023> A_IWL<26022> A_IWL<26021> A_IWL<26020> A_IWL<26019> A_IWL<26018> A_IWL<26017> A_IWL<26016> A_IWL<26015> A_IWL<26014> A_IWL<26013> A_IWL<26012> A_IWL<26011> A_IWL<26010> A_IWL<26009> A_IWL<26008> A_IWL<26007> A_IWL<26006> A_IWL<26005> A_IWL<26004> A_IWL<26003> A_IWL<26002> A_IWL<26001> A_IWL<26000> A_IWL<25999> A_IWL<25998> A_IWL<25997> A_IWL<25996> A_IWL<25995> A_IWL<25994> A_IWL<25993> A_IWL<25992> A_IWL<25991> A_IWL<25990> A_IWL<25989> A_IWL<25988> A_IWL<25987> A_IWL<25986> A_IWL<25985> A_IWL<25984> A_IWL<25983> A_IWL<25982> A_IWL<25981> A_IWL<25980> A_IWL<25979> A_IWL<25978> A_IWL<25977> A_IWL<25976> A_IWL<25975> A_IWL<25974> A_IWL<25973> A_IWL<25972> A_IWL<25971> A_IWL<25970> A_IWL<25969> A_IWL<25968> A_IWL<25967> A_IWL<25966> A_IWL<25965> A_IWL<25964> A_IWL<25963> A_IWL<25962> A_IWL<25961> A_IWL<25960> A_IWL<25959> A_IWL<25958> A_IWL<25957> A_IWL<25956> A_IWL<25955> A_IWL<25954> A_IWL<25953> A_IWL<25952> A_IWL<25951> A_IWL<25950> A_IWL<25949> A_IWL<25948> A_IWL<25947> A_IWL<25946> A_IWL<25945> A_IWL<25944> A_IWL<25943> A_IWL<25942> A_IWL<25941> A_IWL<25940> A_IWL<25939> A_IWL<25938> A_IWL<25937> A_IWL<25936> A_IWL<25935> A_IWL<25934> A_IWL<25933> A_IWL<25932> A_IWL<25931> A_IWL<25930> A_IWL<25929> A_IWL<25928> A_IWL<25927> A_IWL<25926> A_IWL<25925> A_IWL<25924> A_IWL<25923> A_IWL<25922> A_IWL<25921> A_IWL<25920> A_IWL<25919> A_IWL<25918> A_IWL<25917> A_IWL<25916> A_IWL<25915> A_IWL<25914> A_IWL<25913> A_IWL<25912> A_IWL<25911> A_IWL<25910> A_IWL<25909> A_IWL<25908> A_IWL<25907> A_IWL<25906> A_IWL<25905> A_IWL<25904> A_IWL<25903> A_IWL<25902> A_IWL<25901> A_IWL<25900> A_IWL<25899> A_IWL<25898> A_IWL<25897> A_IWL<25896> A_IWL<25895> A_IWL<25894> A_IWL<25893> A_IWL<25892> A_IWL<25891> A_IWL<25890> A_IWL<25889> A_IWL<25888> A_IWL<25887> A_IWL<25886> A_IWL<25885> A_IWL<25884> A_IWL<25883> A_IWL<25882> A_IWL<25881> A_IWL<25880> A_IWL<25879> A_IWL<25878> A_IWL<25877> A_IWL<25876> A_IWL<25875> A_IWL<25874> A_IWL<25873> A_IWL<25872> A_IWL<25871> A_IWL<25870> A_IWL<25869> A_IWL<25868> A_IWL<25867> A_IWL<25866> A_IWL<25865> A_IWL<25864> A_IWL<25863> A_IWL<25862> A_IWL<25861> A_IWL<25860> A_IWL<25859> A_IWL<25858> A_IWL<25857> A_IWL<25856> A_IWL<25855> A_IWL<25854> A_IWL<25853> A_IWL<25852> A_IWL<25851> A_IWL<25850> A_IWL<25849> A_IWL<25848> A_IWL<25847> A_IWL<25846> A_IWL<25845> A_IWL<25844> A_IWL<25843> A_IWL<25842> A_IWL<25841> A_IWL<25840> A_IWL<25839> A_IWL<25838> A_IWL<25837> A_IWL<25836> A_IWL<25835> A_IWL<25834> A_IWL<25833> A_IWL<25832> A_IWL<25831> A_IWL<25830> A_IWL<25829> A_IWL<25828> A_IWL<25827> A_IWL<25826> A_IWL<25825> A_IWL<25824> A_IWL<25823> A_IWL<25822> A_IWL<25821> A_IWL<25820> A_IWL<25819> A_IWL<25818> A_IWL<25817> A_IWL<25816> A_IWL<25815> A_IWL<25814> A_IWL<25813> A_IWL<25812> A_IWL<25811> A_IWL<25810> A_IWL<25809> A_IWL<25808> A_IWL<25807> A_IWL<25806> A_IWL<25805> A_IWL<25804> A_IWL<25803> A_IWL<25802> A_IWL<25801> A_IWL<25800> A_IWL<25799> A_IWL<25798> A_IWL<25797> A_IWL<25796> A_IWL<25795> A_IWL<25794> A_IWL<25793> A_IWL<25792> A_IWL<25791> A_IWL<25790> A_IWL<25789> A_IWL<25788> A_IWL<25787> A_IWL<25786> A_IWL<25785> A_IWL<25784> A_IWL<25783> A_IWL<25782> A_IWL<25781> A_IWL<25780> A_IWL<25779> A_IWL<25778> A_IWL<25777> A_IWL<25776> A_IWL<25775> A_IWL<25774> A_IWL<25773> A_IWL<25772> A_IWL<25771> A_IWL<25770> A_IWL<25769> A_IWL<25768> A_IWL<25767> A_IWL<25766> A_IWL<25765> A_IWL<25764> A_IWL<25763> A_IWL<25762> A_IWL<25761> A_IWL<25760> A_IWL<25759> A_IWL<25758> A_IWL<25757> A_IWL<25756> A_IWL<25755> A_IWL<25754> A_IWL<25753> A_IWL<25752> A_IWL<25751> A_IWL<25750> A_IWL<25749> A_IWL<25748> A_IWL<25747> A_IWL<25746> A_IWL<25745> A_IWL<25744> A_IWL<25743> A_IWL<25742> A_IWL<25741> A_IWL<25740> A_IWL<25739> A_IWL<25738> A_IWL<25737> A_IWL<25736> A_IWL<25735> A_IWL<25734> A_IWL<25733> A_IWL<25732> A_IWL<25731> A_IWL<25730> A_IWL<25729> A_IWL<25728> A_IWL<25727> A_IWL<25726> A_IWL<25725> A_IWL<25724> A_IWL<25723> A_IWL<25722> A_IWL<25721> A_IWL<25720> A_IWL<25719> A_IWL<25718> A_IWL<25717> A_IWL<25716> A_IWL<25715> A_IWL<25714> A_IWL<25713> A_IWL<25712> A_IWL<25711> A_IWL<25710> A_IWL<25709> A_IWL<25708> A_IWL<25707> A_IWL<25706> A_IWL<25705> A_IWL<25704> A_IWL<25703> A_IWL<25702> A_IWL<25701> A_IWL<25700> A_IWL<25699> A_IWL<25698> A_IWL<25697> A_IWL<25696> A_IWL<25695> A_IWL<25694> A_IWL<25693> A_IWL<25692> A_IWL<25691> A_IWL<25690> A_IWL<25689> A_IWL<25688> A_IWL<25687> A_IWL<25686> A_IWL<25685> A_IWL<25684> A_IWL<25683> A_IWL<25682> A_IWL<25681> A_IWL<25680> A_IWL<25679> A_IWL<25678> A_IWL<25677> A_IWL<25676> A_IWL<25675> A_IWL<25674> A_IWL<25673> A_IWL<25672> A_IWL<25671> A_IWL<25670> A_IWL<25669> A_IWL<25668> A_IWL<25667> A_IWL<25666> A_IWL<25665> A_IWL<25664> A_IWL<25663> A_IWL<25662> A_IWL<25661> A_IWL<25660> A_IWL<25659> A_IWL<25658> A_IWL<25657> A_IWL<25656> A_IWL<25655> A_IWL<25654> A_IWL<25653> A_IWL<25652> A_IWL<25651> A_IWL<25650> A_IWL<25649> A_IWL<25648> A_IWL<25647> A_IWL<25646> A_IWL<25645> A_IWL<25644> A_IWL<25643> A_IWL<25642> A_IWL<25641> A_IWL<25640> A_IWL<25639> A_IWL<25638> A_IWL<25637> A_IWL<25636> A_IWL<25635> A_IWL<25634> A_IWL<25633> A_IWL<25632> A_IWL<25631> A_IWL<25630> A_IWL<25629> A_IWL<25628> A_IWL<25627> A_IWL<25626> A_IWL<25625> A_IWL<25624> A_IWL<25623> A_IWL<25622> A_IWL<25621> A_IWL<25620> A_IWL<25619> A_IWL<25618> A_IWL<25617> A_IWL<25616> A_IWL<25615> A_IWL<25614> A_IWL<25613> A_IWL<25612> A_IWL<25611> A_IWL<25610> A_IWL<25609> A_IWL<25608> A_IWL<25607> A_IWL<25606> A_IWL<25605> A_IWL<25604> A_IWL<25603> A_IWL<25602> A_IWL<25601> A_IWL<25600> VDD_CORE VSS / RM_IHPSG13_8192x32_c4_1P_COLUMN_pcell_0 +XCOL<49> A_BLC<99> A_BLC<98> A_BLC_TOP<99> A_BLC_TOP<98> A_BLT<99> A_BLT<98> A_BLT_TOP<99> A_BLT_TOP<98> A_IWL<25087> A_IWL<25086> A_IWL<25085> A_IWL<25084> A_IWL<25083> A_IWL<25082> A_IWL<25081> A_IWL<25080> A_IWL<25079> A_IWL<25078> A_IWL<25077> A_IWL<25076> A_IWL<25075> A_IWL<25074> A_IWL<25073> A_IWL<25072> A_IWL<25071> A_IWL<25070> A_IWL<25069> A_IWL<25068> A_IWL<25067> A_IWL<25066> A_IWL<25065> A_IWL<25064> A_IWL<25063> A_IWL<25062> A_IWL<25061> A_IWL<25060> A_IWL<25059> A_IWL<25058> A_IWL<25057> A_IWL<25056> A_IWL<25055> A_IWL<25054> A_IWL<25053> A_IWL<25052> A_IWL<25051> A_IWL<25050> A_IWL<25049> A_IWL<25048> A_IWL<25047> A_IWL<25046> A_IWL<25045> A_IWL<25044> A_IWL<25043> A_IWL<25042> A_IWL<25041> A_IWL<25040> A_IWL<25039> A_IWL<25038> A_IWL<25037> A_IWL<25036> A_IWL<25035> A_IWL<25034> A_IWL<25033> A_IWL<25032> A_IWL<25031> A_IWL<25030> A_IWL<25029> A_IWL<25028> A_IWL<25027> A_IWL<25026> A_IWL<25025> A_IWL<25024> A_IWL<25023> A_IWL<25022> A_IWL<25021> A_IWL<25020> A_IWL<25019> A_IWL<25018> A_IWL<25017> A_IWL<25016> A_IWL<25015> A_IWL<25014> A_IWL<25013> A_IWL<25012> A_IWL<25011> A_IWL<25010> A_IWL<25009> A_IWL<25008> A_IWL<25007> A_IWL<25006> A_IWL<25005> A_IWL<25004> A_IWL<25003> A_IWL<25002> A_IWL<25001> A_IWL<25000> A_IWL<24999> A_IWL<24998> A_IWL<24997> A_IWL<24996> A_IWL<24995> A_IWL<24994> A_IWL<24993> A_IWL<24992> A_IWL<24991> A_IWL<24990> A_IWL<24989> A_IWL<24988> A_IWL<24987> A_IWL<24986> A_IWL<24985> A_IWL<24984> A_IWL<24983> A_IWL<24982> A_IWL<24981> A_IWL<24980> A_IWL<24979> A_IWL<24978> A_IWL<24977> A_IWL<24976> A_IWL<24975> A_IWL<24974> A_IWL<24973> A_IWL<24972> A_IWL<24971> A_IWL<24970> A_IWL<24969> A_IWL<24968> A_IWL<24967> A_IWL<24966> A_IWL<24965> A_IWL<24964> A_IWL<24963> A_IWL<24962> A_IWL<24961> A_IWL<24960> A_IWL<24959> A_IWL<24958> A_IWL<24957> A_IWL<24956> A_IWL<24955> A_IWL<24954> A_IWL<24953> A_IWL<24952> A_IWL<24951> A_IWL<24950> A_IWL<24949> A_IWL<24948> A_IWL<24947> A_IWL<24946> A_IWL<24945> A_IWL<24944> A_IWL<24943> A_IWL<24942> A_IWL<24941> A_IWL<24940> A_IWL<24939> A_IWL<24938> A_IWL<24937> A_IWL<24936> A_IWL<24935> A_IWL<24934> A_IWL<24933> A_IWL<24932> A_IWL<24931> A_IWL<24930> A_IWL<24929> A_IWL<24928> A_IWL<24927> A_IWL<24926> A_IWL<24925> A_IWL<24924> A_IWL<24923> A_IWL<24922> A_IWL<24921> A_IWL<24920> A_IWL<24919> A_IWL<24918> A_IWL<24917> A_IWL<24916> A_IWL<24915> A_IWL<24914> A_IWL<24913> A_IWL<24912> A_IWL<24911> A_IWL<24910> A_IWL<24909> A_IWL<24908> A_IWL<24907> A_IWL<24906> A_IWL<24905> A_IWL<24904> A_IWL<24903> A_IWL<24902> A_IWL<24901> A_IWL<24900> A_IWL<24899> A_IWL<24898> A_IWL<24897> A_IWL<24896> A_IWL<24895> A_IWL<24894> A_IWL<24893> A_IWL<24892> A_IWL<24891> A_IWL<24890> A_IWL<24889> A_IWL<24888> A_IWL<24887> A_IWL<24886> A_IWL<24885> A_IWL<24884> A_IWL<24883> A_IWL<24882> A_IWL<24881> A_IWL<24880> A_IWL<24879> A_IWL<24878> A_IWL<24877> A_IWL<24876> A_IWL<24875> A_IWL<24874> A_IWL<24873> A_IWL<24872> A_IWL<24871> A_IWL<24870> A_IWL<24869> A_IWL<24868> A_IWL<24867> A_IWL<24866> A_IWL<24865> A_IWL<24864> A_IWL<24863> A_IWL<24862> A_IWL<24861> A_IWL<24860> A_IWL<24859> A_IWL<24858> A_IWL<24857> A_IWL<24856> A_IWL<24855> A_IWL<24854> A_IWL<24853> A_IWL<24852> A_IWL<24851> A_IWL<24850> A_IWL<24849> A_IWL<24848> A_IWL<24847> A_IWL<24846> A_IWL<24845> A_IWL<24844> A_IWL<24843> A_IWL<24842> A_IWL<24841> A_IWL<24840> A_IWL<24839> A_IWL<24838> A_IWL<24837> A_IWL<24836> A_IWL<24835> A_IWL<24834> A_IWL<24833> A_IWL<24832> A_IWL<24831> A_IWL<24830> A_IWL<24829> A_IWL<24828> A_IWL<24827> A_IWL<24826> A_IWL<24825> A_IWL<24824> A_IWL<24823> A_IWL<24822> A_IWL<24821> A_IWL<24820> A_IWL<24819> A_IWL<24818> A_IWL<24817> A_IWL<24816> A_IWL<24815> A_IWL<24814> A_IWL<24813> A_IWL<24812> A_IWL<24811> A_IWL<24810> A_IWL<24809> A_IWL<24808> A_IWL<24807> A_IWL<24806> A_IWL<24805> A_IWL<24804> A_IWL<24803> A_IWL<24802> A_IWL<24801> A_IWL<24800> A_IWL<24799> A_IWL<24798> A_IWL<24797> A_IWL<24796> A_IWL<24795> A_IWL<24794> A_IWL<24793> A_IWL<24792> A_IWL<24791> A_IWL<24790> A_IWL<24789> A_IWL<24788> A_IWL<24787> A_IWL<24786> A_IWL<24785> A_IWL<24784> A_IWL<24783> A_IWL<24782> A_IWL<24781> A_IWL<24780> A_IWL<24779> A_IWL<24778> A_IWL<24777> A_IWL<24776> A_IWL<24775> A_IWL<24774> A_IWL<24773> A_IWL<24772> A_IWL<24771> A_IWL<24770> A_IWL<24769> A_IWL<24768> A_IWL<24767> A_IWL<24766> A_IWL<24765> A_IWL<24764> A_IWL<24763> A_IWL<24762> A_IWL<24761> A_IWL<24760> A_IWL<24759> A_IWL<24758> A_IWL<24757> A_IWL<24756> A_IWL<24755> A_IWL<24754> A_IWL<24753> A_IWL<24752> A_IWL<24751> A_IWL<24750> A_IWL<24749> A_IWL<24748> A_IWL<24747> A_IWL<24746> A_IWL<24745> A_IWL<24744> A_IWL<24743> A_IWL<24742> A_IWL<24741> A_IWL<24740> A_IWL<24739> A_IWL<24738> A_IWL<24737> A_IWL<24736> A_IWL<24735> A_IWL<24734> A_IWL<24733> A_IWL<24732> A_IWL<24731> A_IWL<24730> A_IWL<24729> A_IWL<24728> A_IWL<24727> A_IWL<24726> A_IWL<24725> A_IWL<24724> A_IWL<24723> A_IWL<24722> A_IWL<24721> A_IWL<24720> A_IWL<24719> A_IWL<24718> A_IWL<24717> A_IWL<24716> A_IWL<24715> A_IWL<24714> A_IWL<24713> A_IWL<24712> A_IWL<24711> A_IWL<24710> A_IWL<24709> A_IWL<24708> A_IWL<24707> A_IWL<24706> A_IWL<24705> A_IWL<24704> A_IWL<24703> A_IWL<24702> A_IWL<24701> A_IWL<24700> A_IWL<24699> A_IWL<24698> A_IWL<24697> A_IWL<24696> A_IWL<24695> A_IWL<24694> A_IWL<24693> A_IWL<24692> A_IWL<24691> A_IWL<24690> A_IWL<24689> A_IWL<24688> A_IWL<24687> A_IWL<24686> A_IWL<24685> A_IWL<24684> A_IWL<24683> A_IWL<24682> A_IWL<24681> A_IWL<24680> A_IWL<24679> A_IWL<24678> A_IWL<24677> A_IWL<24676> A_IWL<24675> A_IWL<24674> A_IWL<24673> A_IWL<24672> A_IWL<24671> A_IWL<24670> A_IWL<24669> A_IWL<24668> A_IWL<24667> A_IWL<24666> A_IWL<24665> A_IWL<24664> A_IWL<24663> A_IWL<24662> A_IWL<24661> A_IWL<24660> A_IWL<24659> A_IWL<24658> A_IWL<24657> A_IWL<24656> A_IWL<24655> A_IWL<24654> A_IWL<24653> A_IWL<24652> A_IWL<24651> A_IWL<24650> A_IWL<24649> A_IWL<24648> A_IWL<24647> A_IWL<24646> A_IWL<24645> A_IWL<24644> A_IWL<24643> A_IWL<24642> A_IWL<24641> A_IWL<24640> A_IWL<24639> A_IWL<24638> A_IWL<24637> A_IWL<24636> A_IWL<24635> A_IWL<24634> A_IWL<24633> A_IWL<24632> A_IWL<24631> A_IWL<24630> A_IWL<24629> A_IWL<24628> A_IWL<24627> A_IWL<24626> A_IWL<24625> A_IWL<24624> A_IWL<24623> A_IWL<24622> A_IWL<24621> A_IWL<24620> A_IWL<24619> A_IWL<24618> A_IWL<24617> A_IWL<24616> A_IWL<24615> A_IWL<24614> A_IWL<24613> A_IWL<24612> A_IWL<24611> A_IWL<24610> A_IWL<24609> A_IWL<24608> A_IWL<24607> A_IWL<24606> A_IWL<24605> A_IWL<24604> A_IWL<24603> A_IWL<24602> A_IWL<24601> A_IWL<24600> A_IWL<24599> A_IWL<24598> A_IWL<24597> A_IWL<24596> A_IWL<24595> A_IWL<24594> A_IWL<24593> A_IWL<24592> A_IWL<24591> A_IWL<24590> A_IWL<24589> A_IWL<24588> A_IWL<24587> A_IWL<24586> A_IWL<24585> A_IWL<24584> A_IWL<24583> A_IWL<24582> A_IWL<24581> A_IWL<24580> A_IWL<24579> A_IWL<24578> A_IWL<24577> A_IWL<24576> A_IWL<25599> A_IWL<25598> A_IWL<25597> A_IWL<25596> A_IWL<25595> A_IWL<25594> A_IWL<25593> A_IWL<25592> A_IWL<25591> A_IWL<25590> A_IWL<25589> A_IWL<25588> A_IWL<25587> A_IWL<25586> A_IWL<25585> A_IWL<25584> A_IWL<25583> A_IWL<25582> A_IWL<25581> A_IWL<25580> A_IWL<25579> A_IWL<25578> A_IWL<25577> A_IWL<25576> A_IWL<25575> A_IWL<25574> A_IWL<25573> A_IWL<25572> A_IWL<25571> A_IWL<25570> A_IWL<25569> A_IWL<25568> A_IWL<25567> A_IWL<25566> A_IWL<25565> A_IWL<25564> A_IWL<25563> A_IWL<25562> A_IWL<25561> A_IWL<25560> A_IWL<25559> A_IWL<25558> A_IWL<25557> A_IWL<25556> A_IWL<25555> A_IWL<25554> A_IWL<25553> A_IWL<25552> A_IWL<25551> A_IWL<25550> A_IWL<25549> A_IWL<25548> A_IWL<25547> A_IWL<25546> A_IWL<25545> A_IWL<25544> A_IWL<25543> A_IWL<25542> A_IWL<25541> A_IWL<25540> A_IWL<25539> A_IWL<25538> A_IWL<25537> A_IWL<25536> A_IWL<25535> A_IWL<25534> A_IWL<25533> A_IWL<25532> A_IWL<25531> A_IWL<25530> A_IWL<25529> A_IWL<25528> A_IWL<25527> A_IWL<25526> A_IWL<25525> A_IWL<25524> A_IWL<25523> A_IWL<25522> A_IWL<25521> A_IWL<25520> A_IWL<25519> A_IWL<25518> A_IWL<25517> A_IWL<25516> A_IWL<25515> A_IWL<25514> A_IWL<25513> A_IWL<25512> A_IWL<25511> A_IWL<25510> A_IWL<25509> A_IWL<25508> A_IWL<25507> A_IWL<25506> A_IWL<25505> A_IWL<25504> A_IWL<25503> A_IWL<25502> A_IWL<25501> A_IWL<25500> A_IWL<25499> A_IWL<25498> A_IWL<25497> A_IWL<25496> A_IWL<25495> A_IWL<25494> A_IWL<25493> A_IWL<25492> A_IWL<25491> A_IWL<25490> A_IWL<25489> A_IWL<25488> A_IWL<25487> A_IWL<25486> A_IWL<25485> A_IWL<25484> A_IWL<25483> A_IWL<25482> A_IWL<25481> A_IWL<25480> A_IWL<25479> A_IWL<25478> A_IWL<25477> A_IWL<25476> A_IWL<25475> A_IWL<25474> A_IWL<25473> A_IWL<25472> A_IWL<25471> A_IWL<25470> A_IWL<25469> A_IWL<25468> A_IWL<25467> A_IWL<25466> A_IWL<25465> A_IWL<25464> A_IWL<25463> A_IWL<25462> A_IWL<25461> A_IWL<25460> A_IWL<25459> A_IWL<25458> A_IWL<25457> A_IWL<25456> A_IWL<25455> A_IWL<25454> A_IWL<25453> A_IWL<25452> A_IWL<25451> A_IWL<25450> A_IWL<25449> A_IWL<25448> A_IWL<25447> A_IWL<25446> A_IWL<25445> A_IWL<25444> A_IWL<25443> A_IWL<25442> A_IWL<25441> A_IWL<25440> A_IWL<25439> A_IWL<25438> A_IWL<25437> A_IWL<25436> A_IWL<25435> A_IWL<25434> A_IWL<25433> A_IWL<25432> A_IWL<25431> A_IWL<25430> A_IWL<25429> A_IWL<25428> A_IWL<25427> A_IWL<25426> A_IWL<25425> A_IWL<25424> A_IWL<25423> A_IWL<25422> A_IWL<25421> A_IWL<25420> A_IWL<25419> A_IWL<25418> A_IWL<25417> A_IWL<25416> A_IWL<25415> A_IWL<25414> A_IWL<25413> A_IWL<25412> A_IWL<25411> A_IWL<25410> A_IWL<25409> A_IWL<25408> A_IWL<25407> A_IWL<25406> A_IWL<25405> A_IWL<25404> A_IWL<25403> A_IWL<25402> A_IWL<25401> A_IWL<25400> A_IWL<25399> A_IWL<25398> A_IWL<25397> A_IWL<25396> A_IWL<25395> A_IWL<25394> A_IWL<25393> A_IWL<25392> A_IWL<25391> A_IWL<25390> A_IWL<25389> A_IWL<25388> A_IWL<25387> A_IWL<25386> A_IWL<25385> A_IWL<25384> A_IWL<25383> A_IWL<25382> A_IWL<25381> A_IWL<25380> A_IWL<25379> A_IWL<25378> A_IWL<25377> A_IWL<25376> A_IWL<25375> A_IWL<25374> A_IWL<25373> A_IWL<25372> A_IWL<25371> A_IWL<25370> A_IWL<25369> A_IWL<25368> A_IWL<25367> A_IWL<25366> A_IWL<25365> A_IWL<25364> A_IWL<25363> A_IWL<25362> A_IWL<25361> A_IWL<25360> A_IWL<25359> A_IWL<25358> A_IWL<25357> A_IWL<25356> A_IWL<25355> A_IWL<25354> A_IWL<25353> A_IWL<25352> A_IWL<25351> A_IWL<25350> A_IWL<25349> A_IWL<25348> A_IWL<25347> A_IWL<25346> A_IWL<25345> A_IWL<25344> A_IWL<25343> A_IWL<25342> A_IWL<25341> A_IWL<25340> A_IWL<25339> A_IWL<25338> A_IWL<25337> A_IWL<25336> A_IWL<25335> A_IWL<25334> A_IWL<25333> A_IWL<25332> A_IWL<25331> A_IWL<25330> A_IWL<25329> A_IWL<25328> A_IWL<25327> A_IWL<25326> A_IWL<25325> A_IWL<25324> A_IWL<25323> A_IWL<25322> A_IWL<25321> A_IWL<25320> A_IWL<25319> A_IWL<25318> A_IWL<25317> A_IWL<25316> A_IWL<25315> A_IWL<25314> A_IWL<25313> A_IWL<25312> A_IWL<25311> A_IWL<25310> A_IWL<25309> A_IWL<25308> A_IWL<25307> A_IWL<25306> A_IWL<25305> A_IWL<25304> A_IWL<25303> A_IWL<25302> A_IWL<25301> A_IWL<25300> A_IWL<25299> A_IWL<25298> A_IWL<25297> A_IWL<25296> A_IWL<25295> A_IWL<25294> A_IWL<25293> A_IWL<25292> A_IWL<25291> A_IWL<25290> A_IWL<25289> A_IWL<25288> A_IWL<25287> A_IWL<25286> A_IWL<25285> A_IWL<25284> A_IWL<25283> A_IWL<25282> A_IWL<25281> A_IWL<25280> A_IWL<25279> A_IWL<25278> A_IWL<25277> A_IWL<25276> A_IWL<25275> A_IWL<25274> A_IWL<25273> A_IWL<25272> A_IWL<25271> A_IWL<25270> A_IWL<25269> A_IWL<25268> A_IWL<25267> A_IWL<25266> A_IWL<25265> A_IWL<25264> A_IWL<25263> A_IWL<25262> A_IWL<25261> A_IWL<25260> A_IWL<25259> A_IWL<25258> A_IWL<25257> A_IWL<25256> A_IWL<25255> A_IWL<25254> A_IWL<25253> A_IWL<25252> A_IWL<25251> A_IWL<25250> A_IWL<25249> A_IWL<25248> A_IWL<25247> A_IWL<25246> A_IWL<25245> A_IWL<25244> A_IWL<25243> A_IWL<25242> A_IWL<25241> A_IWL<25240> A_IWL<25239> A_IWL<25238> A_IWL<25237> A_IWL<25236> A_IWL<25235> A_IWL<25234> A_IWL<25233> A_IWL<25232> A_IWL<25231> A_IWL<25230> A_IWL<25229> A_IWL<25228> A_IWL<25227> A_IWL<25226> A_IWL<25225> A_IWL<25224> A_IWL<25223> A_IWL<25222> A_IWL<25221> A_IWL<25220> A_IWL<25219> A_IWL<25218> A_IWL<25217> A_IWL<25216> A_IWL<25215> A_IWL<25214> A_IWL<25213> A_IWL<25212> A_IWL<25211> A_IWL<25210> A_IWL<25209> A_IWL<25208> A_IWL<25207> A_IWL<25206> A_IWL<25205> A_IWL<25204> A_IWL<25203> A_IWL<25202> A_IWL<25201> A_IWL<25200> A_IWL<25199> A_IWL<25198> A_IWL<25197> A_IWL<25196> A_IWL<25195> A_IWL<25194> A_IWL<25193> A_IWL<25192> A_IWL<25191> A_IWL<25190> A_IWL<25189> A_IWL<25188> A_IWL<25187> A_IWL<25186> A_IWL<25185> A_IWL<25184> A_IWL<25183> A_IWL<25182> A_IWL<25181> A_IWL<25180> A_IWL<25179> A_IWL<25178> A_IWL<25177> A_IWL<25176> A_IWL<25175> A_IWL<25174> A_IWL<25173> A_IWL<25172> A_IWL<25171> A_IWL<25170> A_IWL<25169> A_IWL<25168> A_IWL<25167> A_IWL<25166> A_IWL<25165> A_IWL<25164> A_IWL<25163> A_IWL<25162> A_IWL<25161> A_IWL<25160> A_IWL<25159> A_IWL<25158> A_IWL<25157> A_IWL<25156> A_IWL<25155> A_IWL<25154> A_IWL<25153> A_IWL<25152> A_IWL<25151> A_IWL<25150> A_IWL<25149> A_IWL<25148> A_IWL<25147> A_IWL<25146> A_IWL<25145> A_IWL<25144> A_IWL<25143> A_IWL<25142> A_IWL<25141> A_IWL<25140> A_IWL<25139> A_IWL<25138> A_IWL<25137> A_IWL<25136> A_IWL<25135> A_IWL<25134> A_IWL<25133> A_IWL<25132> A_IWL<25131> A_IWL<25130> A_IWL<25129> A_IWL<25128> A_IWL<25127> A_IWL<25126> A_IWL<25125> A_IWL<25124> A_IWL<25123> A_IWL<25122> A_IWL<25121> A_IWL<25120> A_IWL<25119> A_IWL<25118> A_IWL<25117> A_IWL<25116> A_IWL<25115> A_IWL<25114> A_IWL<25113> A_IWL<25112> A_IWL<25111> A_IWL<25110> A_IWL<25109> A_IWL<25108> A_IWL<25107> A_IWL<25106> A_IWL<25105> A_IWL<25104> A_IWL<25103> A_IWL<25102> A_IWL<25101> A_IWL<25100> A_IWL<25099> A_IWL<25098> A_IWL<25097> A_IWL<25096> A_IWL<25095> A_IWL<25094> A_IWL<25093> A_IWL<25092> A_IWL<25091> A_IWL<25090> A_IWL<25089> A_IWL<25088> VDD_CORE VSS / RM_IHPSG13_8192x32_c4_1P_COLUMN_pcell_0 +XCOL<48> A_BLC<97> A_BLC<96> A_BLC_TOP<97> A_BLC_TOP<96> A_BLT<97> A_BLT<96> A_BLT_TOP<97> A_BLT_TOP<96> A_IWL<24575> A_IWL<24574> A_IWL<24573> A_IWL<24572> A_IWL<24571> A_IWL<24570> A_IWL<24569> A_IWL<24568> A_IWL<24567> A_IWL<24566> A_IWL<24565> A_IWL<24564> A_IWL<24563> A_IWL<24562> A_IWL<24561> A_IWL<24560> A_IWL<24559> A_IWL<24558> A_IWL<24557> A_IWL<24556> A_IWL<24555> A_IWL<24554> A_IWL<24553> A_IWL<24552> A_IWL<24551> A_IWL<24550> A_IWL<24549> A_IWL<24548> A_IWL<24547> A_IWL<24546> A_IWL<24545> A_IWL<24544> A_IWL<24543> A_IWL<24542> A_IWL<24541> A_IWL<24540> A_IWL<24539> A_IWL<24538> A_IWL<24537> A_IWL<24536> A_IWL<24535> A_IWL<24534> A_IWL<24533> A_IWL<24532> A_IWL<24531> A_IWL<24530> A_IWL<24529> A_IWL<24528> A_IWL<24527> A_IWL<24526> A_IWL<24525> A_IWL<24524> A_IWL<24523> A_IWL<24522> A_IWL<24521> A_IWL<24520> A_IWL<24519> A_IWL<24518> A_IWL<24517> A_IWL<24516> A_IWL<24515> A_IWL<24514> A_IWL<24513> A_IWL<24512> A_IWL<24511> A_IWL<24510> A_IWL<24509> A_IWL<24508> A_IWL<24507> A_IWL<24506> A_IWL<24505> A_IWL<24504> A_IWL<24503> A_IWL<24502> A_IWL<24501> A_IWL<24500> A_IWL<24499> A_IWL<24498> A_IWL<24497> A_IWL<24496> A_IWL<24495> A_IWL<24494> A_IWL<24493> A_IWL<24492> A_IWL<24491> A_IWL<24490> A_IWL<24489> A_IWL<24488> A_IWL<24487> A_IWL<24486> A_IWL<24485> A_IWL<24484> A_IWL<24483> A_IWL<24482> A_IWL<24481> A_IWL<24480> A_IWL<24479> A_IWL<24478> A_IWL<24477> A_IWL<24476> A_IWL<24475> A_IWL<24474> A_IWL<24473> A_IWL<24472> A_IWL<24471> A_IWL<24470> A_IWL<24469> A_IWL<24468> A_IWL<24467> A_IWL<24466> A_IWL<24465> A_IWL<24464> A_IWL<24463> A_IWL<24462> A_IWL<24461> A_IWL<24460> A_IWL<24459> A_IWL<24458> A_IWL<24457> A_IWL<24456> A_IWL<24455> A_IWL<24454> A_IWL<24453> A_IWL<24452> A_IWL<24451> A_IWL<24450> A_IWL<24449> A_IWL<24448> A_IWL<24447> A_IWL<24446> A_IWL<24445> A_IWL<24444> A_IWL<24443> A_IWL<24442> A_IWL<24441> A_IWL<24440> A_IWL<24439> A_IWL<24438> A_IWL<24437> A_IWL<24436> A_IWL<24435> A_IWL<24434> A_IWL<24433> A_IWL<24432> A_IWL<24431> A_IWL<24430> A_IWL<24429> A_IWL<24428> A_IWL<24427> A_IWL<24426> A_IWL<24425> A_IWL<24424> A_IWL<24423> A_IWL<24422> A_IWL<24421> A_IWL<24420> A_IWL<24419> A_IWL<24418> A_IWL<24417> A_IWL<24416> A_IWL<24415> A_IWL<24414> A_IWL<24413> A_IWL<24412> A_IWL<24411> A_IWL<24410> A_IWL<24409> A_IWL<24408> A_IWL<24407> A_IWL<24406> A_IWL<24405> A_IWL<24404> A_IWL<24403> A_IWL<24402> A_IWL<24401> A_IWL<24400> A_IWL<24399> A_IWL<24398> A_IWL<24397> A_IWL<24396> A_IWL<24395> A_IWL<24394> A_IWL<24393> A_IWL<24392> A_IWL<24391> A_IWL<24390> A_IWL<24389> A_IWL<24388> A_IWL<24387> A_IWL<24386> A_IWL<24385> A_IWL<24384> A_IWL<24383> A_IWL<24382> A_IWL<24381> A_IWL<24380> A_IWL<24379> A_IWL<24378> A_IWL<24377> A_IWL<24376> A_IWL<24375> A_IWL<24374> A_IWL<24373> A_IWL<24372> A_IWL<24371> A_IWL<24370> A_IWL<24369> A_IWL<24368> A_IWL<24367> A_IWL<24366> A_IWL<24365> A_IWL<24364> A_IWL<24363> A_IWL<24362> A_IWL<24361> A_IWL<24360> A_IWL<24359> A_IWL<24358> A_IWL<24357> A_IWL<24356> A_IWL<24355> A_IWL<24354> A_IWL<24353> A_IWL<24352> A_IWL<24351> A_IWL<24350> A_IWL<24349> A_IWL<24348> A_IWL<24347> A_IWL<24346> A_IWL<24345> A_IWL<24344> A_IWL<24343> A_IWL<24342> A_IWL<24341> A_IWL<24340> A_IWL<24339> A_IWL<24338> A_IWL<24337> A_IWL<24336> A_IWL<24335> A_IWL<24334> A_IWL<24333> A_IWL<24332> A_IWL<24331> A_IWL<24330> A_IWL<24329> A_IWL<24328> A_IWL<24327> A_IWL<24326> A_IWL<24325> A_IWL<24324> A_IWL<24323> A_IWL<24322> A_IWL<24321> A_IWL<24320> A_IWL<24319> A_IWL<24318> A_IWL<24317> A_IWL<24316> A_IWL<24315> A_IWL<24314> A_IWL<24313> A_IWL<24312> A_IWL<24311> A_IWL<24310> A_IWL<24309> A_IWL<24308> A_IWL<24307> A_IWL<24306> A_IWL<24305> A_IWL<24304> A_IWL<24303> A_IWL<24302> A_IWL<24301> A_IWL<24300> A_IWL<24299> A_IWL<24298> A_IWL<24297> A_IWL<24296> A_IWL<24295> A_IWL<24294> A_IWL<24293> A_IWL<24292> A_IWL<24291> A_IWL<24290> A_IWL<24289> A_IWL<24288> A_IWL<24287> A_IWL<24286> A_IWL<24285> A_IWL<24284> A_IWL<24283> A_IWL<24282> A_IWL<24281> A_IWL<24280> A_IWL<24279> A_IWL<24278> A_IWL<24277> A_IWL<24276> A_IWL<24275> A_IWL<24274> A_IWL<24273> A_IWL<24272> A_IWL<24271> A_IWL<24270> A_IWL<24269> A_IWL<24268> A_IWL<24267> A_IWL<24266> A_IWL<24265> A_IWL<24264> A_IWL<24263> A_IWL<24262> A_IWL<24261> A_IWL<24260> A_IWL<24259> A_IWL<24258> A_IWL<24257> A_IWL<24256> A_IWL<24255> A_IWL<24254> A_IWL<24253> A_IWL<24252> A_IWL<24251> A_IWL<24250> A_IWL<24249> A_IWL<24248> A_IWL<24247> A_IWL<24246> A_IWL<24245> A_IWL<24244> A_IWL<24243> A_IWL<24242> A_IWL<24241> A_IWL<24240> A_IWL<24239> A_IWL<24238> A_IWL<24237> A_IWL<24236> A_IWL<24235> A_IWL<24234> A_IWL<24233> A_IWL<24232> A_IWL<24231> A_IWL<24230> A_IWL<24229> A_IWL<24228> A_IWL<24227> A_IWL<24226> A_IWL<24225> A_IWL<24224> A_IWL<24223> A_IWL<24222> A_IWL<24221> A_IWL<24220> A_IWL<24219> A_IWL<24218> A_IWL<24217> A_IWL<24216> A_IWL<24215> A_IWL<24214> A_IWL<24213> A_IWL<24212> A_IWL<24211> A_IWL<24210> A_IWL<24209> A_IWL<24208> A_IWL<24207> A_IWL<24206> A_IWL<24205> A_IWL<24204> A_IWL<24203> A_IWL<24202> A_IWL<24201> A_IWL<24200> A_IWL<24199> A_IWL<24198> A_IWL<24197> A_IWL<24196> A_IWL<24195> A_IWL<24194> A_IWL<24193> A_IWL<24192> A_IWL<24191> A_IWL<24190> A_IWL<24189> A_IWL<24188> A_IWL<24187> A_IWL<24186> A_IWL<24185> A_IWL<24184> A_IWL<24183> A_IWL<24182> A_IWL<24181> A_IWL<24180> A_IWL<24179> A_IWL<24178> A_IWL<24177> A_IWL<24176> A_IWL<24175> A_IWL<24174> A_IWL<24173> A_IWL<24172> A_IWL<24171> A_IWL<24170> A_IWL<24169> A_IWL<24168> A_IWL<24167> A_IWL<24166> A_IWL<24165> A_IWL<24164> A_IWL<24163> A_IWL<24162> A_IWL<24161> A_IWL<24160> A_IWL<24159> A_IWL<24158> A_IWL<24157> A_IWL<24156> A_IWL<24155> A_IWL<24154> A_IWL<24153> A_IWL<24152> A_IWL<24151> A_IWL<24150> A_IWL<24149> A_IWL<24148> A_IWL<24147> A_IWL<24146> A_IWL<24145> A_IWL<24144> A_IWL<24143> A_IWL<24142> A_IWL<24141> A_IWL<24140> A_IWL<24139> A_IWL<24138> A_IWL<24137> A_IWL<24136> A_IWL<24135> A_IWL<24134> A_IWL<24133> A_IWL<24132> A_IWL<24131> A_IWL<24130> A_IWL<24129> A_IWL<24128> A_IWL<24127> A_IWL<24126> A_IWL<24125> A_IWL<24124> A_IWL<24123> A_IWL<24122> A_IWL<24121> A_IWL<24120> A_IWL<24119> A_IWL<24118> A_IWL<24117> A_IWL<24116> A_IWL<24115> A_IWL<24114> A_IWL<24113> A_IWL<24112> A_IWL<24111> A_IWL<24110> A_IWL<24109> A_IWL<24108> A_IWL<24107> A_IWL<24106> A_IWL<24105> A_IWL<24104> A_IWL<24103> A_IWL<24102> A_IWL<24101> A_IWL<24100> A_IWL<24099> A_IWL<24098> A_IWL<24097> A_IWL<24096> A_IWL<24095> A_IWL<24094> A_IWL<24093> A_IWL<24092> A_IWL<24091> A_IWL<24090> A_IWL<24089> A_IWL<24088> A_IWL<24087> A_IWL<24086> A_IWL<24085> A_IWL<24084> A_IWL<24083> A_IWL<24082> A_IWL<24081> A_IWL<24080> A_IWL<24079> A_IWL<24078> A_IWL<24077> A_IWL<24076> A_IWL<24075> A_IWL<24074> A_IWL<24073> A_IWL<24072> A_IWL<24071> A_IWL<24070> A_IWL<24069> A_IWL<24068> A_IWL<24067> A_IWL<24066> A_IWL<24065> A_IWL<24064> A_IWL<25087> A_IWL<25086> A_IWL<25085> A_IWL<25084> A_IWL<25083> A_IWL<25082> A_IWL<25081> A_IWL<25080> A_IWL<25079> A_IWL<25078> A_IWL<25077> A_IWL<25076> A_IWL<25075> A_IWL<25074> A_IWL<25073> A_IWL<25072> A_IWL<25071> A_IWL<25070> A_IWL<25069> A_IWL<25068> A_IWL<25067> A_IWL<25066> A_IWL<25065> A_IWL<25064> A_IWL<25063> A_IWL<25062> A_IWL<25061> A_IWL<25060> A_IWL<25059> A_IWL<25058> A_IWL<25057> A_IWL<25056> A_IWL<25055> A_IWL<25054> A_IWL<25053> A_IWL<25052> A_IWL<25051> A_IWL<25050> A_IWL<25049> A_IWL<25048> A_IWL<25047> A_IWL<25046> A_IWL<25045> A_IWL<25044> A_IWL<25043> A_IWL<25042> A_IWL<25041> A_IWL<25040> A_IWL<25039> A_IWL<25038> A_IWL<25037> A_IWL<25036> A_IWL<25035> A_IWL<25034> A_IWL<25033> A_IWL<25032> A_IWL<25031> A_IWL<25030> A_IWL<25029> A_IWL<25028> A_IWL<25027> A_IWL<25026> A_IWL<25025> A_IWL<25024> A_IWL<25023> A_IWL<25022> A_IWL<25021> A_IWL<25020> A_IWL<25019> A_IWL<25018> A_IWL<25017> A_IWL<25016> A_IWL<25015> A_IWL<25014> A_IWL<25013> A_IWL<25012> A_IWL<25011> A_IWL<25010> A_IWL<25009> A_IWL<25008> A_IWL<25007> A_IWL<25006> A_IWL<25005> A_IWL<25004> A_IWL<25003> A_IWL<25002> A_IWL<25001> A_IWL<25000> A_IWL<24999> A_IWL<24998> A_IWL<24997> A_IWL<24996> A_IWL<24995> A_IWL<24994> A_IWL<24993> A_IWL<24992> A_IWL<24991> A_IWL<24990> A_IWL<24989> A_IWL<24988> A_IWL<24987> A_IWL<24986> A_IWL<24985> A_IWL<24984> A_IWL<24983> A_IWL<24982> A_IWL<24981> A_IWL<24980> A_IWL<24979> A_IWL<24978> A_IWL<24977> A_IWL<24976> A_IWL<24975> A_IWL<24974> A_IWL<24973> A_IWL<24972> A_IWL<24971> A_IWL<24970> A_IWL<24969> A_IWL<24968> A_IWL<24967> A_IWL<24966> A_IWL<24965> A_IWL<24964> A_IWL<24963> A_IWL<24962> A_IWL<24961> A_IWL<24960> A_IWL<24959> A_IWL<24958> A_IWL<24957> A_IWL<24956> A_IWL<24955> A_IWL<24954> A_IWL<24953> A_IWL<24952> A_IWL<24951> A_IWL<24950> A_IWL<24949> A_IWL<24948> A_IWL<24947> A_IWL<24946> A_IWL<24945> A_IWL<24944> A_IWL<24943> A_IWL<24942> A_IWL<24941> A_IWL<24940> A_IWL<24939> A_IWL<24938> A_IWL<24937> A_IWL<24936> A_IWL<24935> A_IWL<24934> A_IWL<24933> A_IWL<24932> A_IWL<24931> A_IWL<24930> A_IWL<24929> A_IWL<24928> A_IWL<24927> A_IWL<24926> A_IWL<24925> A_IWL<24924> A_IWL<24923> A_IWL<24922> A_IWL<24921> A_IWL<24920> A_IWL<24919> A_IWL<24918> A_IWL<24917> A_IWL<24916> A_IWL<24915> A_IWL<24914> A_IWL<24913> A_IWL<24912> A_IWL<24911> A_IWL<24910> A_IWL<24909> A_IWL<24908> A_IWL<24907> A_IWL<24906> A_IWL<24905> A_IWL<24904> A_IWL<24903> A_IWL<24902> A_IWL<24901> A_IWL<24900> A_IWL<24899> A_IWL<24898> A_IWL<24897> A_IWL<24896> A_IWL<24895> A_IWL<24894> A_IWL<24893> A_IWL<24892> A_IWL<24891> A_IWL<24890> A_IWL<24889> A_IWL<24888> A_IWL<24887> A_IWL<24886> A_IWL<24885> A_IWL<24884> A_IWL<24883> A_IWL<24882> A_IWL<24881> A_IWL<24880> A_IWL<24879> A_IWL<24878> A_IWL<24877> A_IWL<24876> A_IWL<24875> A_IWL<24874> A_IWL<24873> A_IWL<24872> A_IWL<24871> A_IWL<24870> A_IWL<24869> A_IWL<24868> A_IWL<24867> A_IWL<24866> A_IWL<24865> A_IWL<24864> A_IWL<24863> A_IWL<24862> A_IWL<24861> A_IWL<24860> A_IWL<24859> A_IWL<24858> A_IWL<24857> A_IWL<24856> A_IWL<24855> A_IWL<24854> A_IWL<24853> A_IWL<24852> A_IWL<24851> A_IWL<24850> A_IWL<24849> A_IWL<24848> A_IWL<24847> A_IWL<24846> A_IWL<24845> A_IWL<24844> A_IWL<24843> A_IWL<24842> A_IWL<24841> A_IWL<24840> A_IWL<24839> A_IWL<24838> A_IWL<24837> A_IWL<24836> A_IWL<24835> A_IWL<24834> A_IWL<24833> A_IWL<24832> A_IWL<24831> A_IWL<24830> A_IWL<24829> A_IWL<24828> A_IWL<24827> A_IWL<24826> A_IWL<24825> A_IWL<24824> A_IWL<24823> A_IWL<24822> A_IWL<24821> A_IWL<24820> A_IWL<24819> A_IWL<24818> A_IWL<24817> A_IWL<24816> A_IWL<24815> A_IWL<24814> A_IWL<24813> A_IWL<24812> A_IWL<24811> A_IWL<24810> A_IWL<24809> A_IWL<24808> A_IWL<24807> A_IWL<24806> A_IWL<24805> A_IWL<24804> A_IWL<24803> A_IWL<24802> A_IWL<24801> A_IWL<24800> A_IWL<24799> A_IWL<24798> A_IWL<24797> A_IWL<24796> A_IWL<24795> A_IWL<24794> A_IWL<24793> A_IWL<24792> A_IWL<24791> A_IWL<24790> A_IWL<24789> A_IWL<24788> A_IWL<24787> A_IWL<24786> A_IWL<24785> A_IWL<24784> A_IWL<24783> A_IWL<24782> A_IWL<24781> A_IWL<24780> A_IWL<24779> A_IWL<24778> A_IWL<24777> A_IWL<24776> A_IWL<24775> A_IWL<24774> A_IWL<24773> A_IWL<24772> A_IWL<24771> A_IWL<24770> A_IWL<24769> A_IWL<24768> A_IWL<24767> A_IWL<24766> A_IWL<24765> A_IWL<24764> A_IWL<24763> A_IWL<24762> A_IWL<24761> A_IWL<24760> A_IWL<24759> A_IWL<24758> A_IWL<24757> A_IWL<24756> A_IWL<24755> A_IWL<24754> A_IWL<24753> A_IWL<24752> A_IWL<24751> A_IWL<24750> A_IWL<24749> A_IWL<24748> A_IWL<24747> A_IWL<24746> A_IWL<24745> A_IWL<24744> A_IWL<24743> A_IWL<24742> A_IWL<24741> A_IWL<24740> A_IWL<24739> A_IWL<24738> A_IWL<24737> A_IWL<24736> A_IWL<24735> A_IWL<24734> A_IWL<24733> A_IWL<24732> A_IWL<24731> A_IWL<24730> A_IWL<24729> A_IWL<24728> A_IWL<24727> A_IWL<24726> A_IWL<24725> A_IWL<24724> A_IWL<24723> A_IWL<24722> A_IWL<24721> A_IWL<24720> A_IWL<24719> A_IWL<24718> A_IWL<24717> A_IWL<24716> A_IWL<24715> A_IWL<24714> A_IWL<24713> A_IWL<24712> A_IWL<24711> A_IWL<24710> A_IWL<24709> A_IWL<24708> A_IWL<24707> A_IWL<24706> A_IWL<24705> A_IWL<24704> A_IWL<24703> A_IWL<24702> A_IWL<24701> A_IWL<24700> A_IWL<24699> A_IWL<24698> A_IWL<24697> A_IWL<24696> A_IWL<24695> A_IWL<24694> A_IWL<24693> A_IWL<24692> A_IWL<24691> A_IWL<24690> A_IWL<24689> A_IWL<24688> A_IWL<24687> A_IWL<24686> A_IWL<24685> A_IWL<24684> A_IWL<24683> A_IWL<24682> A_IWL<24681> A_IWL<24680> A_IWL<24679> A_IWL<24678> A_IWL<24677> A_IWL<24676> A_IWL<24675> A_IWL<24674> A_IWL<24673> A_IWL<24672> A_IWL<24671> A_IWL<24670> A_IWL<24669> A_IWL<24668> A_IWL<24667> A_IWL<24666> A_IWL<24665> A_IWL<24664> A_IWL<24663> A_IWL<24662> A_IWL<24661> A_IWL<24660> A_IWL<24659> A_IWL<24658> A_IWL<24657> A_IWL<24656> A_IWL<24655> A_IWL<24654> A_IWL<24653> A_IWL<24652> A_IWL<24651> A_IWL<24650> A_IWL<24649> A_IWL<24648> A_IWL<24647> A_IWL<24646> A_IWL<24645> A_IWL<24644> A_IWL<24643> A_IWL<24642> A_IWL<24641> A_IWL<24640> A_IWL<24639> A_IWL<24638> A_IWL<24637> A_IWL<24636> A_IWL<24635> A_IWL<24634> A_IWL<24633> A_IWL<24632> A_IWL<24631> A_IWL<24630> A_IWL<24629> A_IWL<24628> A_IWL<24627> A_IWL<24626> A_IWL<24625> A_IWL<24624> A_IWL<24623> A_IWL<24622> A_IWL<24621> A_IWL<24620> A_IWL<24619> A_IWL<24618> A_IWL<24617> A_IWL<24616> A_IWL<24615> A_IWL<24614> A_IWL<24613> A_IWL<24612> A_IWL<24611> A_IWL<24610> A_IWL<24609> A_IWL<24608> A_IWL<24607> A_IWL<24606> A_IWL<24605> A_IWL<24604> A_IWL<24603> A_IWL<24602> A_IWL<24601> A_IWL<24600> A_IWL<24599> A_IWL<24598> A_IWL<24597> A_IWL<24596> A_IWL<24595> A_IWL<24594> A_IWL<24593> A_IWL<24592> A_IWL<24591> A_IWL<24590> A_IWL<24589> A_IWL<24588> A_IWL<24587> A_IWL<24586> A_IWL<24585> A_IWL<24584> A_IWL<24583> A_IWL<24582> A_IWL<24581> A_IWL<24580> A_IWL<24579> A_IWL<24578> A_IWL<24577> A_IWL<24576> VDD_CORE VSS / RM_IHPSG13_8192x32_c4_1P_COLUMN_pcell_0 +XCOL<47> A_BLC<95> A_BLC<94> A_BLC_TOP<95> A_BLC_TOP<94> A_BLT<95> A_BLT<94> A_BLT_TOP<95> A_BLT_TOP<94> A_IWL<24063> A_IWL<24062> A_IWL<24061> A_IWL<24060> A_IWL<24059> A_IWL<24058> A_IWL<24057> A_IWL<24056> A_IWL<24055> A_IWL<24054> A_IWL<24053> A_IWL<24052> A_IWL<24051> A_IWL<24050> A_IWL<24049> A_IWL<24048> A_IWL<24047> A_IWL<24046> A_IWL<24045> A_IWL<24044> A_IWL<24043> A_IWL<24042> A_IWL<24041> A_IWL<24040> A_IWL<24039> A_IWL<24038> A_IWL<24037> A_IWL<24036> A_IWL<24035> A_IWL<24034> A_IWL<24033> A_IWL<24032> A_IWL<24031> A_IWL<24030> A_IWL<24029> A_IWL<24028> A_IWL<24027> A_IWL<24026> A_IWL<24025> A_IWL<24024> A_IWL<24023> A_IWL<24022> A_IWL<24021> A_IWL<24020> A_IWL<24019> A_IWL<24018> A_IWL<24017> A_IWL<24016> A_IWL<24015> A_IWL<24014> A_IWL<24013> A_IWL<24012> A_IWL<24011> A_IWL<24010> A_IWL<24009> A_IWL<24008> A_IWL<24007> A_IWL<24006> A_IWL<24005> A_IWL<24004> A_IWL<24003> A_IWL<24002> A_IWL<24001> A_IWL<24000> A_IWL<23999> A_IWL<23998> A_IWL<23997> A_IWL<23996> A_IWL<23995> A_IWL<23994> A_IWL<23993> A_IWL<23992> A_IWL<23991> A_IWL<23990> A_IWL<23989> A_IWL<23988> A_IWL<23987> A_IWL<23986> A_IWL<23985> A_IWL<23984> A_IWL<23983> A_IWL<23982> A_IWL<23981> A_IWL<23980> A_IWL<23979> A_IWL<23978> A_IWL<23977> A_IWL<23976> A_IWL<23975> A_IWL<23974> A_IWL<23973> A_IWL<23972> A_IWL<23971> A_IWL<23970> A_IWL<23969> A_IWL<23968> A_IWL<23967> A_IWL<23966> A_IWL<23965> A_IWL<23964> A_IWL<23963> A_IWL<23962> A_IWL<23961> A_IWL<23960> A_IWL<23959> A_IWL<23958> A_IWL<23957> A_IWL<23956> A_IWL<23955> A_IWL<23954> A_IWL<23953> A_IWL<23952> A_IWL<23951> A_IWL<23950> A_IWL<23949> A_IWL<23948> A_IWL<23947> A_IWL<23946> A_IWL<23945> A_IWL<23944> A_IWL<23943> A_IWL<23942> A_IWL<23941> A_IWL<23940> A_IWL<23939> A_IWL<23938> A_IWL<23937> A_IWL<23936> A_IWL<23935> A_IWL<23934> A_IWL<23933> A_IWL<23932> A_IWL<23931> A_IWL<23930> A_IWL<23929> A_IWL<23928> A_IWL<23927> A_IWL<23926> A_IWL<23925> A_IWL<23924> A_IWL<23923> A_IWL<23922> A_IWL<23921> A_IWL<23920> A_IWL<23919> A_IWL<23918> A_IWL<23917> A_IWL<23916> A_IWL<23915> A_IWL<23914> A_IWL<23913> A_IWL<23912> A_IWL<23911> A_IWL<23910> A_IWL<23909> A_IWL<23908> A_IWL<23907> A_IWL<23906> A_IWL<23905> A_IWL<23904> A_IWL<23903> A_IWL<23902> A_IWL<23901> A_IWL<23900> A_IWL<23899> A_IWL<23898> A_IWL<23897> A_IWL<23896> A_IWL<23895> A_IWL<23894> A_IWL<23893> A_IWL<23892> A_IWL<23891> A_IWL<23890> A_IWL<23889> A_IWL<23888> A_IWL<23887> A_IWL<23886> A_IWL<23885> A_IWL<23884> A_IWL<23883> A_IWL<23882> A_IWL<23881> A_IWL<23880> A_IWL<23879> A_IWL<23878> A_IWL<23877> A_IWL<23876> A_IWL<23875> A_IWL<23874> A_IWL<23873> A_IWL<23872> A_IWL<23871> A_IWL<23870> A_IWL<23869> A_IWL<23868> A_IWL<23867> A_IWL<23866> A_IWL<23865> A_IWL<23864> A_IWL<23863> A_IWL<23862> A_IWL<23861> A_IWL<23860> A_IWL<23859> A_IWL<23858> A_IWL<23857> A_IWL<23856> A_IWL<23855> A_IWL<23854> A_IWL<23853> A_IWL<23852> A_IWL<23851> A_IWL<23850> A_IWL<23849> A_IWL<23848> A_IWL<23847> A_IWL<23846> A_IWL<23845> A_IWL<23844> A_IWL<23843> A_IWL<23842> A_IWL<23841> A_IWL<23840> A_IWL<23839> A_IWL<23838> A_IWL<23837> A_IWL<23836> A_IWL<23835> A_IWL<23834> A_IWL<23833> A_IWL<23832> A_IWL<23831> A_IWL<23830> A_IWL<23829> A_IWL<23828> A_IWL<23827> A_IWL<23826> A_IWL<23825> A_IWL<23824> A_IWL<23823> A_IWL<23822> A_IWL<23821> A_IWL<23820> A_IWL<23819> A_IWL<23818> A_IWL<23817> A_IWL<23816> A_IWL<23815> A_IWL<23814> A_IWL<23813> A_IWL<23812> A_IWL<23811> A_IWL<23810> A_IWL<23809> A_IWL<23808> A_IWL<23807> A_IWL<23806> A_IWL<23805> A_IWL<23804> A_IWL<23803> A_IWL<23802> A_IWL<23801> A_IWL<23800> A_IWL<23799> A_IWL<23798> A_IWL<23797> A_IWL<23796> A_IWL<23795> A_IWL<23794> A_IWL<23793> A_IWL<23792> A_IWL<23791> A_IWL<23790> A_IWL<23789> A_IWL<23788> A_IWL<23787> A_IWL<23786> A_IWL<23785> A_IWL<23784> A_IWL<23783> A_IWL<23782> A_IWL<23781> A_IWL<23780> A_IWL<23779> A_IWL<23778> A_IWL<23777> A_IWL<23776> A_IWL<23775> A_IWL<23774> A_IWL<23773> A_IWL<23772> A_IWL<23771> A_IWL<23770> A_IWL<23769> A_IWL<23768> A_IWL<23767> A_IWL<23766> A_IWL<23765> A_IWL<23764> A_IWL<23763> A_IWL<23762> A_IWL<23761> A_IWL<23760> A_IWL<23759> A_IWL<23758> A_IWL<23757> A_IWL<23756> A_IWL<23755> A_IWL<23754> A_IWL<23753> A_IWL<23752> A_IWL<23751> A_IWL<23750> A_IWL<23749> A_IWL<23748> A_IWL<23747> A_IWL<23746> A_IWL<23745> A_IWL<23744> A_IWL<23743> A_IWL<23742> A_IWL<23741> A_IWL<23740> A_IWL<23739> A_IWL<23738> A_IWL<23737> A_IWL<23736> A_IWL<23735> A_IWL<23734> A_IWL<23733> A_IWL<23732> A_IWL<23731> A_IWL<23730> A_IWL<23729> A_IWL<23728> A_IWL<23727> A_IWL<23726> A_IWL<23725> A_IWL<23724> A_IWL<23723> A_IWL<23722> A_IWL<23721> A_IWL<23720> A_IWL<23719> A_IWL<23718> A_IWL<23717> A_IWL<23716> A_IWL<23715> A_IWL<23714> A_IWL<23713> A_IWL<23712> A_IWL<23711> A_IWL<23710> A_IWL<23709> A_IWL<23708> A_IWL<23707> A_IWL<23706> A_IWL<23705> A_IWL<23704> A_IWL<23703> A_IWL<23702> A_IWL<23701> A_IWL<23700> A_IWL<23699> A_IWL<23698> A_IWL<23697> A_IWL<23696> A_IWL<23695> A_IWL<23694> A_IWL<23693> A_IWL<23692> A_IWL<23691> A_IWL<23690> A_IWL<23689> A_IWL<23688> A_IWL<23687> A_IWL<23686> A_IWL<23685> A_IWL<23684> A_IWL<23683> A_IWL<23682> A_IWL<23681> A_IWL<23680> A_IWL<23679> A_IWL<23678> A_IWL<23677> A_IWL<23676> A_IWL<23675> A_IWL<23674> A_IWL<23673> A_IWL<23672> A_IWL<23671> A_IWL<23670> A_IWL<23669> A_IWL<23668> A_IWL<23667> A_IWL<23666> A_IWL<23665> A_IWL<23664> A_IWL<23663> A_IWL<23662> A_IWL<23661> A_IWL<23660> A_IWL<23659> A_IWL<23658> A_IWL<23657> A_IWL<23656> A_IWL<23655> A_IWL<23654> A_IWL<23653> A_IWL<23652> A_IWL<23651> A_IWL<23650> A_IWL<23649> A_IWL<23648> A_IWL<23647> A_IWL<23646> A_IWL<23645> A_IWL<23644> A_IWL<23643> A_IWL<23642> A_IWL<23641> A_IWL<23640> A_IWL<23639> A_IWL<23638> A_IWL<23637> A_IWL<23636> A_IWL<23635> A_IWL<23634> A_IWL<23633> A_IWL<23632> A_IWL<23631> A_IWL<23630> A_IWL<23629> A_IWL<23628> A_IWL<23627> A_IWL<23626> A_IWL<23625> A_IWL<23624> A_IWL<23623> A_IWL<23622> A_IWL<23621> A_IWL<23620> A_IWL<23619> A_IWL<23618> A_IWL<23617> A_IWL<23616> A_IWL<23615> A_IWL<23614> A_IWL<23613> A_IWL<23612> A_IWL<23611> A_IWL<23610> A_IWL<23609> A_IWL<23608> A_IWL<23607> A_IWL<23606> A_IWL<23605> A_IWL<23604> A_IWL<23603> A_IWL<23602> A_IWL<23601> A_IWL<23600> A_IWL<23599> A_IWL<23598> A_IWL<23597> A_IWL<23596> A_IWL<23595> A_IWL<23594> A_IWL<23593> A_IWL<23592> A_IWL<23591> A_IWL<23590> A_IWL<23589> A_IWL<23588> A_IWL<23587> A_IWL<23586> A_IWL<23585> A_IWL<23584> A_IWL<23583> A_IWL<23582> A_IWL<23581> A_IWL<23580> A_IWL<23579> A_IWL<23578> A_IWL<23577> A_IWL<23576> A_IWL<23575> A_IWL<23574> A_IWL<23573> A_IWL<23572> A_IWL<23571> A_IWL<23570> A_IWL<23569> A_IWL<23568> A_IWL<23567> A_IWL<23566> A_IWL<23565> A_IWL<23564> A_IWL<23563> A_IWL<23562> A_IWL<23561> A_IWL<23560> A_IWL<23559> A_IWL<23558> A_IWL<23557> A_IWL<23556> A_IWL<23555> A_IWL<23554> A_IWL<23553> A_IWL<23552> A_IWL<24575> A_IWL<24574> A_IWL<24573> A_IWL<24572> A_IWL<24571> A_IWL<24570> A_IWL<24569> A_IWL<24568> A_IWL<24567> A_IWL<24566> A_IWL<24565> A_IWL<24564> A_IWL<24563> A_IWL<24562> A_IWL<24561> A_IWL<24560> A_IWL<24559> A_IWL<24558> A_IWL<24557> A_IWL<24556> A_IWL<24555> A_IWL<24554> A_IWL<24553> A_IWL<24552> A_IWL<24551> A_IWL<24550> A_IWL<24549> A_IWL<24548> A_IWL<24547> A_IWL<24546> A_IWL<24545> A_IWL<24544> A_IWL<24543> A_IWL<24542> A_IWL<24541> A_IWL<24540> A_IWL<24539> A_IWL<24538> A_IWL<24537> A_IWL<24536> A_IWL<24535> A_IWL<24534> A_IWL<24533> A_IWL<24532> A_IWL<24531> A_IWL<24530> A_IWL<24529> A_IWL<24528> A_IWL<24527> A_IWL<24526> A_IWL<24525> A_IWL<24524> A_IWL<24523> A_IWL<24522> A_IWL<24521> A_IWL<24520> A_IWL<24519> A_IWL<24518> A_IWL<24517> A_IWL<24516> A_IWL<24515> A_IWL<24514> A_IWL<24513> A_IWL<24512> A_IWL<24511> A_IWL<24510> A_IWL<24509> A_IWL<24508> A_IWL<24507> A_IWL<24506> A_IWL<24505> A_IWL<24504> A_IWL<24503> A_IWL<24502> A_IWL<24501> A_IWL<24500> A_IWL<24499> A_IWL<24498> A_IWL<24497> A_IWL<24496> A_IWL<24495> A_IWL<24494> A_IWL<24493> A_IWL<24492> A_IWL<24491> A_IWL<24490> A_IWL<24489> A_IWL<24488> A_IWL<24487> A_IWL<24486> A_IWL<24485> A_IWL<24484> A_IWL<24483> A_IWL<24482> A_IWL<24481> A_IWL<24480> A_IWL<24479> A_IWL<24478> A_IWL<24477> A_IWL<24476> A_IWL<24475> A_IWL<24474> A_IWL<24473> A_IWL<24472> A_IWL<24471> A_IWL<24470> A_IWL<24469> A_IWL<24468> A_IWL<24467> A_IWL<24466> A_IWL<24465> A_IWL<24464> A_IWL<24463> A_IWL<24462> A_IWL<24461> A_IWL<24460> A_IWL<24459> A_IWL<24458> A_IWL<24457> A_IWL<24456> A_IWL<24455> A_IWL<24454> A_IWL<24453> A_IWL<24452> A_IWL<24451> A_IWL<24450> A_IWL<24449> A_IWL<24448> A_IWL<24447> A_IWL<24446> A_IWL<24445> A_IWL<24444> A_IWL<24443> A_IWL<24442> A_IWL<24441> A_IWL<24440> A_IWL<24439> A_IWL<24438> A_IWL<24437> A_IWL<24436> A_IWL<24435> A_IWL<24434> A_IWL<24433> A_IWL<24432> A_IWL<24431> A_IWL<24430> A_IWL<24429> A_IWL<24428> A_IWL<24427> A_IWL<24426> A_IWL<24425> A_IWL<24424> A_IWL<24423> A_IWL<24422> A_IWL<24421> A_IWL<24420> A_IWL<24419> A_IWL<24418> A_IWL<24417> A_IWL<24416> A_IWL<24415> A_IWL<24414> A_IWL<24413> A_IWL<24412> A_IWL<24411> A_IWL<24410> A_IWL<24409> A_IWL<24408> A_IWL<24407> A_IWL<24406> A_IWL<24405> A_IWL<24404> A_IWL<24403> A_IWL<24402> A_IWL<24401> A_IWL<24400> A_IWL<24399> A_IWL<24398> A_IWL<24397> A_IWL<24396> A_IWL<24395> A_IWL<24394> A_IWL<24393> A_IWL<24392> A_IWL<24391> A_IWL<24390> A_IWL<24389> A_IWL<24388> A_IWL<24387> A_IWL<24386> A_IWL<24385> A_IWL<24384> A_IWL<24383> A_IWL<24382> A_IWL<24381> A_IWL<24380> A_IWL<24379> A_IWL<24378> A_IWL<24377> A_IWL<24376> A_IWL<24375> A_IWL<24374> A_IWL<24373> A_IWL<24372> A_IWL<24371> A_IWL<24370> A_IWL<24369> A_IWL<24368> A_IWL<24367> A_IWL<24366> A_IWL<24365> A_IWL<24364> A_IWL<24363> A_IWL<24362> A_IWL<24361> A_IWL<24360> A_IWL<24359> A_IWL<24358> A_IWL<24357> A_IWL<24356> A_IWL<24355> A_IWL<24354> A_IWL<24353> A_IWL<24352> A_IWL<24351> A_IWL<24350> A_IWL<24349> A_IWL<24348> A_IWL<24347> A_IWL<24346> A_IWL<24345> A_IWL<24344> A_IWL<24343> A_IWL<24342> A_IWL<24341> A_IWL<24340> A_IWL<24339> A_IWL<24338> A_IWL<24337> A_IWL<24336> A_IWL<24335> A_IWL<24334> A_IWL<24333> A_IWL<24332> A_IWL<24331> A_IWL<24330> A_IWL<24329> A_IWL<24328> A_IWL<24327> A_IWL<24326> A_IWL<24325> A_IWL<24324> A_IWL<24323> A_IWL<24322> A_IWL<24321> A_IWL<24320> A_IWL<24319> A_IWL<24318> A_IWL<24317> A_IWL<24316> A_IWL<24315> A_IWL<24314> A_IWL<24313> A_IWL<24312> A_IWL<24311> A_IWL<24310> A_IWL<24309> A_IWL<24308> A_IWL<24307> A_IWL<24306> A_IWL<24305> A_IWL<24304> A_IWL<24303> A_IWL<24302> A_IWL<24301> A_IWL<24300> A_IWL<24299> A_IWL<24298> A_IWL<24297> A_IWL<24296> A_IWL<24295> A_IWL<24294> A_IWL<24293> A_IWL<24292> A_IWL<24291> A_IWL<24290> A_IWL<24289> A_IWL<24288> A_IWL<24287> A_IWL<24286> A_IWL<24285> A_IWL<24284> A_IWL<24283> A_IWL<24282> A_IWL<24281> A_IWL<24280> A_IWL<24279> A_IWL<24278> A_IWL<24277> A_IWL<24276> A_IWL<24275> A_IWL<24274> A_IWL<24273> A_IWL<24272> A_IWL<24271> A_IWL<24270> A_IWL<24269> A_IWL<24268> A_IWL<24267> A_IWL<24266> A_IWL<24265> A_IWL<24264> A_IWL<24263> A_IWL<24262> A_IWL<24261> A_IWL<24260> A_IWL<24259> A_IWL<24258> A_IWL<24257> A_IWL<24256> A_IWL<24255> A_IWL<24254> A_IWL<24253> A_IWL<24252> A_IWL<24251> A_IWL<24250> A_IWL<24249> A_IWL<24248> A_IWL<24247> A_IWL<24246> A_IWL<24245> A_IWL<24244> A_IWL<24243> A_IWL<24242> A_IWL<24241> A_IWL<24240> A_IWL<24239> A_IWL<24238> A_IWL<24237> A_IWL<24236> A_IWL<24235> A_IWL<24234> A_IWL<24233> A_IWL<24232> A_IWL<24231> A_IWL<24230> A_IWL<24229> A_IWL<24228> A_IWL<24227> A_IWL<24226> A_IWL<24225> A_IWL<24224> A_IWL<24223> A_IWL<24222> A_IWL<24221> A_IWL<24220> A_IWL<24219> A_IWL<24218> A_IWL<24217> A_IWL<24216> A_IWL<24215> A_IWL<24214> A_IWL<24213> A_IWL<24212> A_IWL<24211> A_IWL<24210> A_IWL<24209> A_IWL<24208> A_IWL<24207> A_IWL<24206> A_IWL<24205> A_IWL<24204> A_IWL<24203> A_IWL<24202> A_IWL<24201> A_IWL<24200> A_IWL<24199> A_IWL<24198> A_IWL<24197> A_IWL<24196> A_IWL<24195> A_IWL<24194> A_IWL<24193> A_IWL<24192> A_IWL<24191> A_IWL<24190> A_IWL<24189> A_IWL<24188> A_IWL<24187> A_IWL<24186> A_IWL<24185> A_IWL<24184> A_IWL<24183> A_IWL<24182> A_IWL<24181> A_IWL<24180> A_IWL<24179> A_IWL<24178> A_IWL<24177> A_IWL<24176> A_IWL<24175> A_IWL<24174> A_IWL<24173> A_IWL<24172> A_IWL<24171> A_IWL<24170> A_IWL<24169> A_IWL<24168> A_IWL<24167> A_IWL<24166> A_IWL<24165> A_IWL<24164> A_IWL<24163> A_IWL<24162> A_IWL<24161> A_IWL<24160> A_IWL<24159> A_IWL<24158> A_IWL<24157> A_IWL<24156> A_IWL<24155> A_IWL<24154> A_IWL<24153> A_IWL<24152> A_IWL<24151> A_IWL<24150> A_IWL<24149> A_IWL<24148> A_IWL<24147> A_IWL<24146> A_IWL<24145> A_IWL<24144> A_IWL<24143> A_IWL<24142> A_IWL<24141> A_IWL<24140> A_IWL<24139> A_IWL<24138> A_IWL<24137> A_IWL<24136> A_IWL<24135> A_IWL<24134> A_IWL<24133> A_IWL<24132> A_IWL<24131> A_IWL<24130> A_IWL<24129> A_IWL<24128> A_IWL<24127> A_IWL<24126> A_IWL<24125> A_IWL<24124> A_IWL<24123> A_IWL<24122> A_IWL<24121> A_IWL<24120> A_IWL<24119> A_IWL<24118> A_IWL<24117> A_IWL<24116> A_IWL<24115> A_IWL<24114> A_IWL<24113> A_IWL<24112> A_IWL<24111> A_IWL<24110> A_IWL<24109> A_IWL<24108> A_IWL<24107> A_IWL<24106> A_IWL<24105> A_IWL<24104> A_IWL<24103> A_IWL<24102> A_IWL<24101> A_IWL<24100> A_IWL<24099> A_IWL<24098> A_IWL<24097> A_IWL<24096> A_IWL<24095> A_IWL<24094> A_IWL<24093> A_IWL<24092> A_IWL<24091> A_IWL<24090> A_IWL<24089> A_IWL<24088> A_IWL<24087> A_IWL<24086> A_IWL<24085> A_IWL<24084> A_IWL<24083> A_IWL<24082> A_IWL<24081> A_IWL<24080> A_IWL<24079> A_IWL<24078> A_IWL<24077> A_IWL<24076> A_IWL<24075> A_IWL<24074> A_IWL<24073> A_IWL<24072> A_IWL<24071> A_IWL<24070> A_IWL<24069> A_IWL<24068> A_IWL<24067> A_IWL<24066> A_IWL<24065> A_IWL<24064> VDD_CORE VSS / RM_IHPSG13_8192x32_c4_1P_COLUMN_pcell_0 +XCOL<46> A_BLC<93> A_BLC<92> A_BLC_TOP<93> A_BLC_TOP<92> A_BLT<93> A_BLT<92> A_BLT_TOP<93> A_BLT_TOP<92> A_IWL<23551> A_IWL<23550> A_IWL<23549> A_IWL<23548> A_IWL<23547> A_IWL<23546> A_IWL<23545> A_IWL<23544> A_IWL<23543> A_IWL<23542> A_IWL<23541> A_IWL<23540> A_IWL<23539> A_IWL<23538> A_IWL<23537> A_IWL<23536> A_IWL<23535> A_IWL<23534> A_IWL<23533> A_IWL<23532> A_IWL<23531> A_IWL<23530> A_IWL<23529> A_IWL<23528> A_IWL<23527> A_IWL<23526> A_IWL<23525> A_IWL<23524> A_IWL<23523> A_IWL<23522> A_IWL<23521> A_IWL<23520> A_IWL<23519> A_IWL<23518> A_IWL<23517> A_IWL<23516> A_IWL<23515> A_IWL<23514> A_IWL<23513> A_IWL<23512> A_IWL<23511> A_IWL<23510> A_IWL<23509> A_IWL<23508> A_IWL<23507> A_IWL<23506> A_IWL<23505> A_IWL<23504> A_IWL<23503> A_IWL<23502> A_IWL<23501> A_IWL<23500> A_IWL<23499> A_IWL<23498> A_IWL<23497> A_IWL<23496> A_IWL<23495> A_IWL<23494> A_IWL<23493> A_IWL<23492> A_IWL<23491> A_IWL<23490> A_IWL<23489> A_IWL<23488> A_IWL<23487> A_IWL<23486> A_IWL<23485> A_IWL<23484> A_IWL<23483> A_IWL<23482> A_IWL<23481> A_IWL<23480> A_IWL<23479> A_IWL<23478> A_IWL<23477> A_IWL<23476> A_IWL<23475> A_IWL<23474> A_IWL<23473> A_IWL<23472> A_IWL<23471> A_IWL<23470> A_IWL<23469> A_IWL<23468> A_IWL<23467> A_IWL<23466> A_IWL<23465> A_IWL<23464> A_IWL<23463> A_IWL<23462> A_IWL<23461> A_IWL<23460> A_IWL<23459> A_IWL<23458> A_IWL<23457> A_IWL<23456> A_IWL<23455> A_IWL<23454> A_IWL<23453> A_IWL<23452> A_IWL<23451> A_IWL<23450> A_IWL<23449> A_IWL<23448> A_IWL<23447> A_IWL<23446> A_IWL<23445> A_IWL<23444> A_IWL<23443> A_IWL<23442> A_IWL<23441> A_IWL<23440> A_IWL<23439> A_IWL<23438> A_IWL<23437> A_IWL<23436> A_IWL<23435> A_IWL<23434> A_IWL<23433> A_IWL<23432> A_IWL<23431> A_IWL<23430> A_IWL<23429> A_IWL<23428> A_IWL<23427> A_IWL<23426> A_IWL<23425> A_IWL<23424> A_IWL<23423> A_IWL<23422> A_IWL<23421> A_IWL<23420> A_IWL<23419> A_IWL<23418> A_IWL<23417> A_IWL<23416> A_IWL<23415> A_IWL<23414> A_IWL<23413> A_IWL<23412> A_IWL<23411> A_IWL<23410> A_IWL<23409> A_IWL<23408> A_IWL<23407> A_IWL<23406> A_IWL<23405> A_IWL<23404> A_IWL<23403> A_IWL<23402> A_IWL<23401> A_IWL<23400> A_IWL<23399> A_IWL<23398> A_IWL<23397> A_IWL<23396> A_IWL<23395> A_IWL<23394> A_IWL<23393> A_IWL<23392> A_IWL<23391> A_IWL<23390> A_IWL<23389> A_IWL<23388> A_IWL<23387> A_IWL<23386> A_IWL<23385> A_IWL<23384> A_IWL<23383> A_IWL<23382> A_IWL<23381> A_IWL<23380> A_IWL<23379> A_IWL<23378> A_IWL<23377> A_IWL<23376> A_IWL<23375> A_IWL<23374> A_IWL<23373> A_IWL<23372> A_IWL<23371> A_IWL<23370> A_IWL<23369> A_IWL<23368> A_IWL<23367> A_IWL<23366> A_IWL<23365> A_IWL<23364> A_IWL<23363> A_IWL<23362> A_IWL<23361> A_IWL<23360> A_IWL<23359> A_IWL<23358> A_IWL<23357> A_IWL<23356> A_IWL<23355> A_IWL<23354> A_IWL<23353> A_IWL<23352> A_IWL<23351> A_IWL<23350> A_IWL<23349> A_IWL<23348> A_IWL<23347> A_IWL<23346> A_IWL<23345> A_IWL<23344> A_IWL<23343> A_IWL<23342> A_IWL<23341> A_IWL<23340> A_IWL<23339> A_IWL<23338> A_IWL<23337> A_IWL<23336> A_IWL<23335> A_IWL<23334> A_IWL<23333> A_IWL<23332> A_IWL<23331> A_IWL<23330> A_IWL<23329> A_IWL<23328> A_IWL<23327> A_IWL<23326> A_IWL<23325> A_IWL<23324> A_IWL<23323> A_IWL<23322> A_IWL<23321> A_IWL<23320> A_IWL<23319> A_IWL<23318> A_IWL<23317> A_IWL<23316> A_IWL<23315> A_IWL<23314> A_IWL<23313> A_IWL<23312> A_IWL<23311> A_IWL<23310> A_IWL<23309> A_IWL<23308> A_IWL<23307> A_IWL<23306> A_IWL<23305> A_IWL<23304> A_IWL<23303> A_IWL<23302> A_IWL<23301> A_IWL<23300> A_IWL<23299> A_IWL<23298> A_IWL<23297> A_IWL<23296> A_IWL<23295> A_IWL<23294> A_IWL<23293> A_IWL<23292> A_IWL<23291> A_IWL<23290> A_IWL<23289> A_IWL<23288> A_IWL<23287> A_IWL<23286> A_IWL<23285> A_IWL<23284> A_IWL<23283> A_IWL<23282> A_IWL<23281> A_IWL<23280> A_IWL<23279> A_IWL<23278> A_IWL<23277> A_IWL<23276> A_IWL<23275> A_IWL<23274> A_IWL<23273> A_IWL<23272> A_IWL<23271> A_IWL<23270> A_IWL<23269> A_IWL<23268> A_IWL<23267> A_IWL<23266> A_IWL<23265> A_IWL<23264> A_IWL<23263> A_IWL<23262> A_IWL<23261> A_IWL<23260> A_IWL<23259> A_IWL<23258> A_IWL<23257> A_IWL<23256> A_IWL<23255> A_IWL<23254> A_IWL<23253> A_IWL<23252> A_IWL<23251> A_IWL<23250> A_IWL<23249> A_IWL<23248> A_IWL<23247> A_IWL<23246> A_IWL<23245> A_IWL<23244> A_IWL<23243> A_IWL<23242> A_IWL<23241> A_IWL<23240> A_IWL<23239> A_IWL<23238> A_IWL<23237> A_IWL<23236> A_IWL<23235> A_IWL<23234> A_IWL<23233> A_IWL<23232> A_IWL<23231> A_IWL<23230> A_IWL<23229> A_IWL<23228> A_IWL<23227> A_IWL<23226> A_IWL<23225> A_IWL<23224> A_IWL<23223> A_IWL<23222> A_IWL<23221> A_IWL<23220> A_IWL<23219> A_IWL<23218> A_IWL<23217> A_IWL<23216> A_IWL<23215> A_IWL<23214> A_IWL<23213> A_IWL<23212> A_IWL<23211> A_IWL<23210> A_IWL<23209> A_IWL<23208> A_IWL<23207> A_IWL<23206> A_IWL<23205> A_IWL<23204> A_IWL<23203> A_IWL<23202> A_IWL<23201> A_IWL<23200> A_IWL<23199> A_IWL<23198> A_IWL<23197> A_IWL<23196> A_IWL<23195> A_IWL<23194> A_IWL<23193> A_IWL<23192> A_IWL<23191> A_IWL<23190> A_IWL<23189> A_IWL<23188> A_IWL<23187> A_IWL<23186> A_IWL<23185> A_IWL<23184> A_IWL<23183> A_IWL<23182> A_IWL<23181> A_IWL<23180> A_IWL<23179> A_IWL<23178> A_IWL<23177> A_IWL<23176> A_IWL<23175> A_IWL<23174> A_IWL<23173> A_IWL<23172> A_IWL<23171> A_IWL<23170> A_IWL<23169> A_IWL<23168> A_IWL<23167> A_IWL<23166> A_IWL<23165> A_IWL<23164> A_IWL<23163> A_IWL<23162> A_IWL<23161> A_IWL<23160> A_IWL<23159> A_IWL<23158> A_IWL<23157> A_IWL<23156> A_IWL<23155> A_IWL<23154> A_IWL<23153> A_IWL<23152> A_IWL<23151> A_IWL<23150> A_IWL<23149> A_IWL<23148> A_IWL<23147> A_IWL<23146> A_IWL<23145> A_IWL<23144> A_IWL<23143> A_IWL<23142> A_IWL<23141> A_IWL<23140> A_IWL<23139> A_IWL<23138> A_IWL<23137> A_IWL<23136> A_IWL<23135> A_IWL<23134> A_IWL<23133> A_IWL<23132> A_IWL<23131> A_IWL<23130> A_IWL<23129> A_IWL<23128> A_IWL<23127> A_IWL<23126> A_IWL<23125> A_IWL<23124> A_IWL<23123> A_IWL<23122> A_IWL<23121> A_IWL<23120> A_IWL<23119> A_IWL<23118> A_IWL<23117> A_IWL<23116> A_IWL<23115> A_IWL<23114> A_IWL<23113> A_IWL<23112> A_IWL<23111> A_IWL<23110> A_IWL<23109> A_IWL<23108> A_IWL<23107> A_IWL<23106> A_IWL<23105> A_IWL<23104> A_IWL<23103> A_IWL<23102> A_IWL<23101> A_IWL<23100> A_IWL<23099> A_IWL<23098> A_IWL<23097> A_IWL<23096> A_IWL<23095> A_IWL<23094> A_IWL<23093> A_IWL<23092> A_IWL<23091> A_IWL<23090> A_IWL<23089> A_IWL<23088> A_IWL<23087> A_IWL<23086> A_IWL<23085> A_IWL<23084> A_IWL<23083> A_IWL<23082> A_IWL<23081> A_IWL<23080> A_IWL<23079> A_IWL<23078> A_IWL<23077> A_IWL<23076> A_IWL<23075> A_IWL<23074> A_IWL<23073> A_IWL<23072> A_IWL<23071> A_IWL<23070> A_IWL<23069> A_IWL<23068> A_IWL<23067> A_IWL<23066> A_IWL<23065> A_IWL<23064> A_IWL<23063> A_IWL<23062> A_IWL<23061> A_IWL<23060> A_IWL<23059> A_IWL<23058> A_IWL<23057> A_IWL<23056> A_IWL<23055> A_IWL<23054> A_IWL<23053> A_IWL<23052> A_IWL<23051> A_IWL<23050> A_IWL<23049> A_IWL<23048> A_IWL<23047> A_IWL<23046> A_IWL<23045> A_IWL<23044> A_IWL<23043> A_IWL<23042> A_IWL<23041> A_IWL<23040> A_IWL<24063> A_IWL<24062> A_IWL<24061> A_IWL<24060> A_IWL<24059> A_IWL<24058> A_IWL<24057> A_IWL<24056> A_IWL<24055> A_IWL<24054> A_IWL<24053> A_IWL<24052> A_IWL<24051> A_IWL<24050> A_IWL<24049> A_IWL<24048> A_IWL<24047> A_IWL<24046> A_IWL<24045> A_IWL<24044> A_IWL<24043> A_IWL<24042> A_IWL<24041> A_IWL<24040> A_IWL<24039> A_IWL<24038> A_IWL<24037> A_IWL<24036> A_IWL<24035> A_IWL<24034> A_IWL<24033> A_IWL<24032> A_IWL<24031> A_IWL<24030> A_IWL<24029> A_IWL<24028> A_IWL<24027> A_IWL<24026> A_IWL<24025> A_IWL<24024> A_IWL<24023> A_IWL<24022> A_IWL<24021> A_IWL<24020> A_IWL<24019> A_IWL<24018> A_IWL<24017> A_IWL<24016> A_IWL<24015> A_IWL<24014> A_IWL<24013> A_IWL<24012> A_IWL<24011> A_IWL<24010> A_IWL<24009> A_IWL<24008> A_IWL<24007> A_IWL<24006> A_IWL<24005> A_IWL<24004> A_IWL<24003> A_IWL<24002> A_IWL<24001> A_IWL<24000> A_IWL<23999> A_IWL<23998> A_IWL<23997> A_IWL<23996> A_IWL<23995> A_IWL<23994> A_IWL<23993> A_IWL<23992> A_IWL<23991> A_IWL<23990> A_IWL<23989> A_IWL<23988> A_IWL<23987> A_IWL<23986> A_IWL<23985> A_IWL<23984> A_IWL<23983> A_IWL<23982> A_IWL<23981> A_IWL<23980> A_IWL<23979> A_IWL<23978> A_IWL<23977> A_IWL<23976> A_IWL<23975> A_IWL<23974> A_IWL<23973> A_IWL<23972> A_IWL<23971> A_IWL<23970> A_IWL<23969> A_IWL<23968> A_IWL<23967> A_IWL<23966> A_IWL<23965> A_IWL<23964> A_IWL<23963> A_IWL<23962> A_IWL<23961> A_IWL<23960> A_IWL<23959> A_IWL<23958> A_IWL<23957> A_IWL<23956> A_IWL<23955> A_IWL<23954> A_IWL<23953> A_IWL<23952> A_IWL<23951> A_IWL<23950> A_IWL<23949> A_IWL<23948> A_IWL<23947> A_IWL<23946> A_IWL<23945> A_IWL<23944> A_IWL<23943> A_IWL<23942> A_IWL<23941> A_IWL<23940> A_IWL<23939> A_IWL<23938> A_IWL<23937> A_IWL<23936> A_IWL<23935> A_IWL<23934> A_IWL<23933> A_IWL<23932> A_IWL<23931> A_IWL<23930> A_IWL<23929> A_IWL<23928> A_IWL<23927> A_IWL<23926> A_IWL<23925> A_IWL<23924> A_IWL<23923> A_IWL<23922> A_IWL<23921> A_IWL<23920> A_IWL<23919> A_IWL<23918> A_IWL<23917> A_IWL<23916> A_IWL<23915> A_IWL<23914> A_IWL<23913> A_IWL<23912> A_IWL<23911> A_IWL<23910> A_IWL<23909> A_IWL<23908> A_IWL<23907> A_IWL<23906> A_IWL<23905> A_IWL<23904> A_IWL<23903> A_IWL<23902> A_IWL<23901> A_IWL<23900> A_IWL<23899> A_IWL<23898> A_IWL<23897> A_IWL<23896> A_IWL<23895> A_IWL<23894> A_IWL<23893> A_IWL<23892> A_IWL<23891> A_IWL<23890> A_IWL<23889> A_IWL<23888> A_IWL<23887> A_IWL<23886> A_IWL<23885> A_IWL<23884> A_IWL<23883> A_IWL<23882> A_IWL<23881> A_IWL<23880> A_IWL<23879> A_IWL<23878> A_IWL<23877> A_IWL<23876> A_IWL<23875> A_IWL<23874> A_IWL<23873> A_IWL<23872> A_IWL<23871> A_IWL<23870> A_IWL<23869> A_IWL<23868> A_IWL<23867> A_IWL<23866> A_IWL<23865> A_IWL<23864> A_IWL<23863> A_IWL<23862> A_IWL<23861> A_IWL<23860> A_IWL<23859> A_IWL<23858> A_IWL<23857> A_IWL<23856> A_IWL<23855> A_IWL<23854> A_IWL<23853> A_IWL<23852> A_IWL<23851> A_IWL<23850> A_IWL<23849> A_IWL<23848> A_IWL<23847> A_IWL<23846> A_IWL<23845> A_IWL<23844> A_IWL<23843> A_IWL<23842> A_IWL<23841> A_IWL<23840> A_IWL<23839> A_IWL<23838> A_IWL<23837> A_IWL<23836> A_IWL<23835> A_IWL<23834> A_IWL<23833> A_IWL<23832> A_IWL<23831> A_IWL<23830> A_IWL<23829> A_IWL<23828> A_IWL<23827> A_IWL<23826> A_IWL<23825> A_IWL<23824> A_IWL<23823> A_IWL<23822> A_IWL<23821> A_IWL<23820> A_IWL<23819> A_IWL<23818> A_IWL<23817> A_IWL<23816> A_IWL<23815> A_IWL<23814> A_IWL<23813> A_IWL<23812> A_IWL<23811> A_IWL<23810> A_IWL<23809> A_IWL<23808> A_IWL<23807> A_IWL<23806> A_IWL<23805> A_IWL<23804> A_IWL<23803> A_IWL<23802> A_IWL<23801> A_IWL<23800> A_IWL<23799> A_IWL<23798> A_IWL<23797> A_IWL<23796> A_IWL<23795> A_IWL<23794> A_IWL<23793> A_IWL<23792> A_IWL<23791> A_IWL<23790> A_IWL<23789> A_IWL<23788> A_IWL<23787> A_IWL<23786> A_IWL<23785> A_IWL<23784> A_IWL<23783> A_IWL<23782> A_IWL<23781> A_IWL<23780> A_IWL<23779> A_IWL<23778> A_IWL<23777> A_IWL<23776> A_IWL<23775> A_IWL<23774> A_IWL<23773> A_IWL<23772> A_IWL<23771> A_IWL<23770> A_IWL<23769> A_IWL<23768> A_IWL<23767> A_IWL<23766> A_IWL<23765> A_IWL<23764> A_IWL<23763> A_IWL<23762> A_IWL<23761> A_IWL<23760> A_IWL<23759> A_IWL<23758> A_IWL<23757> A_IWL<23756> A_IWL<23755> A_IWL<23754> A_IWL<23753> A_IWL<23752> A_IWL<23751> A_IWL<23750> A_IWL<23749> A_IWL<23748> A_IWL<23747> A_IWL<23746> A_IWL<23745> A_IWL<23744> A_IWL<23743> A_IWL<23742> A_IWL<23741> A_IWL<23740> A_IWL<23739> A_IWL<23738> A_IWL<23737> A_IWL<23736> A_IWL<23735> A_IWL<23734> A_IWL<23733> A_IWL<23732> A_IWL<23731> A_IWL<23730> A_IWL<23729> A_IWL<23728> A_IWL<23727> A_IWL<23726> A_IWL<23725> A_IWL<23724> A_IWL<23723> A_IWL<23722> A_IWL<23721> A_IWL<23720> A_IWL<23719> A_IWL<23718> A_IWL<23717> A_IWL<23716> A_IWL<23715> A_IWL<23714> A_IWL<23713> A_IWL<23712> A_IWL<23711> A_IWL<23710> A_IWL<23709> A_IWL<23708> A_IWL<23707> A_IWL<23706> A_IWL<23705> A_IWL<23704> A_IWL<23703> A_IWL<23702> A_IWL<23701> A_IWL<23700> A_IWL<23699> A_IWL<23698> A_IWL<23697> A_IWL<23696> A_IWL<23695> A_IWL<23694> A_IWL<23693> A_IWL<23692> A_IWL<23691> A_IWL<23690> A_IWL<23689> A_IWL<23688> A_IWL<23687> A_IWL<23686> A_IWL<23685> A_IWL<23684> A_IWL<23683> A_IWL<23682> A_IWL<23681> A_IWL<23680> A_IWL<23679> A_IWL<23678> A_IWL<23677> A_IWL<23676> A_IWL<23675> A_IWL<23674> A_IWL<23673> A_IWL<23672> A_IWL<23671> A_IWL<23670> A_IWL<23669> A_IWL<23668> A_IWL<23667> A_IWL<23666> A_IWL<23665> A_IWL<23664> A_IWL<23663> A_IWL<23662> A_IWL<23661> A_IWL<23660> A_IWL<23659> A_IWL<23658> A_IWL<23657> A_IWL<23656> A_IWL<23655> A_IWL<23654> A_IWL<23653> A_IWL<23652> A_IWL<23651> A_IWL<23650> A_IWL<23649> A_IWL<23648> A_IWL<23647> A_IWL<23646> A_IWL<23645> A_IWL<23644> A_IWL<23643> A_IWL<23642> A_IWL<23641> A_IWL<23640> A_IWL<23639> A_IWL<23638> A_IWL<23637> A_IWL<23636> A_IWL<23635> A_IWL<23634> A_IWL<23633> A_IWL<23632> A_IWL<23631> A_IWL<23630> A_IWL<23629> A_IWL<23628> A_IWL<23627> A_IWL<23626> A_IWL<23625> A_IWL<23624> A_IWL<23623> A_IWL<23622> A_IWL<23621> A_IWL<23620> A_IWL<23619> A_IWL<23618> A_IWL<23617> A_IWL<23616> A_IWL<23615> A_IWL<23614> A_IWL<23613> A_IWL<23612> A_IWL<23611> A_IWL<23610> A_IWL<23609> A_IWL<23608> A_IWL<23607> A_IWL<23606> A_IWL<23605> A_IWL<23604> A_IWL<23603> A_IWL<23602> A_IWL<23601> A_IWL<23600> A_IWL<23599> A_IWL<23598> A_IWL<23597> A_IWL<23596> A_IWL<23595> A_IWL<23594> A_IWL<23593> A_IWL<23592> A_IWL<23591> A_IWL<23590> A_IWL<23589> A_IWL<23588> A_IWL<23587> A_IWL<23586> A_IWL<23585> A_IWL<23584> A_IWL<23583> A_IWL<23582> A_IWL<23581> A_IWL<23580> A_IWL<23579> A_IWL<23578> A_IWL<23577> A_IWL<23576> A_IWL<23575> A_IWL<23574> A_IWL<23573> A_IWL<23572> A_IWL<23571> A_IWL<23570> A_IWL<23569> A_IWL<23568> A_IWL<23567> A_IWL<23566> A_IWL<23565> A_IWL<23564> A_IWL<23563> A_IWL<23562> A_IWL<23561> A_IWL<23560> A_IWL<23559> A_IWL<23558> A_IWL<23557> A_IWL<23556> A_IWL<23555> A_IWL<23554> A_IWL<23553> A_IWL<23552> VDD_CORE VSS / RM_IHPSG13_8192x32_c4_1P_COLUMN_pcell_0 +XCOL<45> A_BLC<91> A_BLC<90> A_BLC_TOP<91> A_BLC_TOP<90> A_BLT<91> A_BLT<90> A_BLT_TOP<91> A_BLT_TOP<90> A_IWL<23039> A_IWL<23038> A_IWL<23037> A_IWL<23036> A_IWL<23035> A_IWL<23034> A_IWL<23033> A_IWL<23032> A_IWL<23031> A_IWL<23030> A_IWL<23029> A_IWL<23028> A_IWL<23027> A_IWL<23026> A_IWL<23025> A_IWL<23024> A_IWL<23023> A_IWL<23022> A_IWL<23021> A_IWL<23020> A_IWL<23019> A_IWL<23018> A_IWL<23017> A_IWL<23016> A_IWL<23015> A_IWL<23014> A_IWL<23013> A_IWL<23012> A_IWL<23011> A_IWL<23010> A_IWL<23009> A_IWL<23008> A_IWL<23007> A_IWL<23006> A_IWL<23005> A_IWL<23004> A_IWL<23003> A_IWL<23002> A_IWL<23001> A_IWL<23000> A_IWL<22999> A_IWL<22998> A_IWL<22997> A_IWL<22996> A_IWL<22995> A_IWL<22994> A_IWL<22993> A_IWL<22992> A_IWL<22991> A_IWL<22990> A_IWL<22989> A_IWL<22988> A_IWL<22987> A_IWL<22986> A_IWL<22985> A_IWL<22984> A_IWL<22983> A_IWL<22982> A_IWL<22981> A_IWL<22980> A_IWL<22979> A_IWL<22978> A_IWL<22977> A_IWL<22976> A_IWL<22975> A_IWL<22974> A_IWL<22973> A_IWL<22972> A_IWL<22971> A_IWL<22970> A_IWL<22969> A_IWL<22968> A_IWL<22967> A_IWL<22966> A_IWL<22965> A_IWL<22964> A_IWL<22963> A_IWL<22962> A_IWL<22961> A_IWL<22960> A_IWL<22959> A_IWL<22958> A_IWL<22957> A_IWL<22956> A_IWL<22955> A_IWL<22954> A_IWL<22953> A_IWL<22952> A_IWL<22951> A_IWL<22950> A_IWL<22949> A_IWL<22948> A_IWL<22947> A_IWL<22946> A_IWL<22945> A_IWL<22944> A_IWL<22943> A_IWL<22942> A_IWL<22941> A_IWL<22940> A_IWL<22939> A_IWL<22938> A_IWL<22937> A_IWL<22936> A_IWL<22935> A_IWL<22934> A_IWL<22933> A_IWL<22932> A_IWL<22931> A_IWL<22930> A_IWL<22929> A_IWL<22928> A_IWL<22927> A_IWL<22926> A_IWL<22925> A_IWL<22924> A_IWL<22923> A_IWL<22922> A_IWL<22921> A_IWL<22920> A_IWL<22919> A_IWL<22918> A_IWL<22917> A_IWL<22916> A_IWL<22915> A_IWL<22914> A_IWL<22913> A_IWL<22912> A_IWL<22911> A_IWL<22910> A_IWL<22909> A_IWL<22908> A_IWL<22907> A_IWL<22906> A_IWL<22905> A_IWL<22904> A_IWL<22903> A_IWL<22902> A_IWL<22901> A_IWL<22900> A_IWL<22899> A_IWL<22898> A_IWL<22897> A_IWL<22896> A_IWL<22895> A_IWL<22894> A_IWL<22893> A_IWL<22892> A_IWL<22891> A_IWL<22890> A_IWL<22889> A_IWL<22888> A_IWL<22887> A_IWL<22886> A_IWL<22885> A_IWL<22884> A_IWL<22883> A_IWL<22882> A_IWL<22881> A_IWL<22880> A_IWL<22879> A_IWL<22878> A_IWL<22877> A_IWL<22876> A_IWL<22875> A_IWL<22874> A_IWL<22873> A_IWL<22872> A_IWL<22871> A_IWL<22870> A_IWL<22869> A_IWL<22868> A_IWL<22867> A_IWL<22866> A_IWL<22865> A_IWL<22864> A_IWL<22863> A_IWL<22862> A_IWL<22861> A_IWL<22860> A_IWL<22859> A_IWL<22858> A_IWL<22857> A_IWL<22856> A_IWL<22855> A_IWL<22854> A_IWL<22853> A_IWL<22852> A_IWL<22851> A_IWL<22850> A_IWL<22849> A_IWL<22848> A_IWL<22847> A_IWL<22846> A_IWL<22845> A_IWL<22844> A_IWL<22843> A_IWL<22842> A_IWL<22841> A_IWL<22840> A_IWL<22839> A_IWL<22838> A_IWL<22837> A_IWL<22836> A_IWL<22835> A_IWL<22834> A_IWL<22833> A_IWL<22832> A_IWL<22831> A_IWL<22830> A_IWL<22829> A_IWL<22828> A_IWL<22827> A_IWL<22826> A_IWL<22825> A_IWL<22824> A_IWL<22823> A_IWL<22822> A_IWL<22821> A_IWL<22820> A_IWL<22819> A_IWL<22818> A_IWL<22817> A_IWL<22816> A_IWL<22815> A_IWL<22814> A_IWL<22813> A_IWL<22812> A_IWL<22811> A_IWL<22810> A_IWL<22809> A_IWL<22808> A_IWL<22807> A_IWL<22806> A_IWL<22805> A_IWL<22804> A_IWL<22803> A_IWL<22802> A_IWL<22801> A_IWL<22800> A_IWL<22799> A_IWL<22798> A_IWL<22797> A_IWL<22796> A_IWL<22795> A_IWL<22794> A_IWL<22793> A_IWL<22792> A_IWL<22791> A_IWL<22790> A_IWL<22789> A_IWL<22788> A_IWL<22787> A_IWL<22786> A_IWL<22785> A_IWL<22784> A_IWL<22783> A_IWL<22782> A_IWL<22781> A_IWL<22780> A_IWL<22779> A_IWL<22778> A_IWL<22777> A_IWL<22776> A_IWL<22775> A_IWL<22774> A_IWL<22773> A_IWL<22772> A_IWL<22771> A_IWL<22770> A_IWL<22769> A_IWL<22768> A_IWL<22767> A_IWL<22766> A_IWL<22765> A_IWL<22764> A_IWL<22763> A_IWL<22762> A_IWL<22761> A_IWL<22760> A_IWL<22759> A_IWL<22758> A_IWL<22757> A_IWL<22756> A_IWL<22755> A_IWL<22754> A_IWL<22753> A_IWL<22752> A_IWL<22751> A_IWL<22750> A_IWL<22749> A_IWL<22748> A_IWL<22747> A_IWL<22746> A_IWL<22745> A_IWL<22744> A_IWL<22743> A_IWL<22742> A_IWL<22741> A_IWL<22740> A_IWL<22739> A_IWL<22738> A_IWL<22737> A_IWL<22736> A_IWL<22735> A_IWL<22734> A_IWL<22733> A_IWL<22732> A_IWL<22731> A_IWL<22730> A_IWL<22729> A_IWL<22728> A_IWL<22727> A_IWL<22726> A_IWL<22725> A_IWL<22724> A_IWL<22723> A_IWL<22722> A_IWL<22721> A_IWL<22720> A_IWL<22719> A_IWL<22718> A_IWL<22717> A_IWL<22716> A_IWL<22715> A_IWL<22714> A_IWL<22713> A_IWL<22712> A_IWL<22711> A_IWL<22710> A_IWL<22709> A_IWL<22708> A_IWL<22707> A_IWL<22706> A_IWL<22705> A_IWL<22704> A_IWL<22703> A_IWL<22702> A_IWL<22701> A_IWL<22700> A_IWL<22699> A_IWL<22698> A_IWL<22697> A_IWL<22696> A_IWL<22695> A_IWL<22694> A_IWL<22693> A_IWL<22692> A_IWL<22691> A_IWL<22690> A_IWL<22689> A_IWL<22688> A_IWL<22687> A_IWL<22686> A_IWL<22685> A_IWL<22684> A_IWL<22683> A_IWL<22682> A_IWL<22681> A_IWL<22680> A_IWL<22679> A_IWL<22678> A_IWL<22677> A_IWL<22676> A_IWL<22675> A_IWL<22674> A_IWL<22673> A_IWL<22672> A_IWL<22671> A_IWL<22670> A_IWL<22669> A_IWL<22668> A_IWL<22667> A_IWL<22666> A_IWL<22665> A_IWL<22664> A_IWL<22663> A_IWL<22662> A_IWL<22661> A_IWL<22660> A_IWL<22659> A_IWL<22658> A_IWL<22657> A_IWL<22656> A_IWL<22655> A_IWL<22654> A_IWL<22653> A_IWL<22652> A_IWL<22651> A_IWL<22650> A_IWL<22649> A_IWL<22648> A_IWL<22647> A_IWL<22646> A_IWL<22645> A_IWL<22644> A_IWL<22643> A_IWL<22642> A_IWL<22641> A_IWL<22640> A_IWL<22639> A_IWL<22638> A_IWL<22637> A_IWL<22636> A_IWL<22635> A_IWL<22634> A_IWL<22633> A_IWL<22632> A_IWL<22631> A_IWL<22630> A_IWL<22629> A_IWL<22628> A_IWL<22627> A_IWL<22626> A_IWL<22625> A_IWL<22624> A_IWL<22623> A_IWL<22622> A_IWL<22621> A_IWL<22620> A_IWL<22619> A_IWL<22618> A_IWL<22617> A_IWL<22616> A_IWL<22615> A_IWL<22614> A_IWL<22613> A_IWL<22612> A_IWL<22611> A_IWL<22610> A_IWL<22609> A_IWL<22608> A_IWL<22607> A_IWL<22606> A_IWL<22605> A_IWL<22604> A_IWL<22603> A_IWL<22602> A_IWL<22601> A_IWL<22600> A_IWL<22599> A_IWL<22598> A_IWL<22597> A_IWL<22596> A_IWL<22595> A_IWL<22594> A_IWL<22593> A_IWL<22592> A_IWL<22591> A_IWL<22590> A_IWL<22589> A_IWL<22588> A_IWL<22587> A_IWL<22586> A_IWL<22585> A_IWL<22584> A_IWL<22583> A_IWL<22582> A_IWL<22581> A_IWL<22580> A_IWL<22579> A_IWL<22578> A_IWL<22577> A_IWL<22576> A_IWL<22575> A_IWL<22574> A_IWL<22573> A_IWL<22572> A_IWL<22571> A_IWL<22570> A_IWL<22569> A_IWL<22568> A_IWL<22567> A_IWL<22566> A_IWL<22565> A_IWL<22564> A_IWL<22563> A_IWL<22562> A_IWL<22561> A_IWL<22560> A_IWL<22559> A_IWL<22558> A_IWL<22557> A_IWL<22556> A_IWL<22555> A_IWL<22554> A_IWL<22553> A_IWL<22552> A_IWL<22551> A_IWL<22550> A_IWL<22549> A_IWL<22548> A_IWL<22547> A_IWL<22546> A_IWL<22545> A_IWL<22544> A_IWL<22543> A_IWL<22542> A_IWL<22541> A_IWL<22540> A_IWL<22539> A_IWL<22538> A_IWL<22537> A_IWL<22536> A_IWL<22535> A_IWL<22534> A_IWL<22533> A_IWL<22532> A_IWL<22531> A_IWL<22530> A_IWL<22529> A_IWL<22528> A_IWL<23551> A_IWL<23550> A_IWL<23549> A_IWL<23548> A_IWL<23547> A_IWL<23546> A_IWL<23545> A_IWL<23544> A_IWL<23543> A_IWL<23542> A_IWL<23541> A_IWL<23540> A_IWL<23539> A_IWL<23538> A_IWL<23537> A_IWL<23536> A_IWL<23535> A_IWL<23534> A_IWL<23533> A_IWL<23532> A_IWL<23531> A_IWL<23530> A_IWL<23529> A_IWL<23528> A_IWL<23527> A_IWL<23526> A_IWL<23525> A_IWL<23524> A_IWL<23523> A_IWL<23522> A_IWL<23521> A_IWL<23520> A_IWL<23519> A_IWL<23518> A_IWL<23517> A_IWL<23516> A_IWL<23515> A_IWL<23514> A_IWL<23513> A_IWL<23512> A_IWL<23511> A_IWL<23510> A_IWL<23509> A_IWL<23508> A_IWL<23507> A_IWL<23506> A_IWL<23505> A_IWL<23504> A_IWL<23503> A_IWL<23502> A_IWL<23501> A_IWL<23500> A_IWL<23499> A_IWL<23498> A_IWL<23497> A_IWL<23496> A_IWL<23495> A_IWL<23494> A_IWL<23493> A_IWL<23492> A_IWL<23491> A_IWL<23490> A_IWL<23489> A_IWL<23488> A_IWL<23487> A_IWL<23486> A_IWL<23485> A_IWL<23484> A_IWL<23483> A_IWL<23482> A_IWL<23481> A_IWL<23480> A_IWL<23479> A_IWL<23478> A_IWL<23477> A_IWL<23476> A_IWL<23475> A_IWL<23474> A_IWL<23473> A_IWL<23472> A_IWL<23471> A_IWL<23470> A_IWL<23469> A_IWL<23468> A_IWL<23467> A_IWL<23466> A_IWL<23465> A_IWL<23464> A_IWL<23463> A_IWL<23462> A_IWL<23461> A_IWL<23460> A_IWL<23459> A_IWL<23458> A_IWL<23457> A_IWL<23456> A_IWL<23455> A_IWL<23454> A_IWL<23453> A_IWL<23452> A_IWL<23451> A_IWL<23450> A_IWL<23449> A_IWL<23448> A_IWL<23447> A_IWL<23446> A_IWL<23445> A_IWL<23444> A_IWL<23443> A_IWL<23442> A_IWL<23441> A_IWL<23440> A_IWL<23439> A_IWL<23438> A_IWL<23437> A_IWL<23436> A_IWL<23435> A_IWL<23434> A_IWL<23433> A_IWL<23432> A_IWL<23431> A_IWL<23430> A_IWL<23429> A_IWL<23428> A_IWL<23427> A_IWL<23426> A_IWL<23425> A_IWL<23424> A_IWL<23423> A_IWL<23422> A_IWL<23421> A_IWL<23420> A_IWL<23419> A_IWL<23418> A_IWL<23417> A_IWL<23416> A_IWL<23415> A_IWL<23414> A_IWL<23413> A_IWL<23412> A_IWL<23411> A_IWL<23410> A_IWL<23409> A_IWL<23408> A_IWL<23407> A_IWL<23406> A_IWL<23405> A_IWL<23404> A_IWL<23403> A_IWL<23402> A_IWL<23401> A_IWL<23400> A_IWL<23399> A_IWL<23398> A_IWL<23397> A_IWL<23396> A_IWL<23395> A_IWL<23394> A_IWL<23393> A_IWL<23392> A_IWL<23391> A_IWL<23390> A_IWL<23389> A_IWL<23388> A_IWL<23387> A_IWL<23386> A_IWL<23385> A_IWL<23384> A_IWL<23383> A_IWL<23382> A_IWL<23381> A_IWL<23380> A_IWL<23379> A_IWL<23378> A_IWL<23377> A_IWL<23376> A_IWL<23375> A_IWL<23374> A_IWL<23373> A_IWL<23372> A_IWL<23371> A_IWL<23370> A_IWL<23369> A_IWL<23368> A_IWL<23367> A_IWL<23366> A_IWL<23365> A_IWL<23364> A_IWL<23363> A_IWL<23362> A_IWL<23361> A_IWL<23360> A_IWL<23359> A_IWL<23358> A_IWL<23357> A_IWL<23356> A_IWL<23355> A_IWL<23354> A_IWL<23353> A_IWL<23352> A_IWL<23351> A_IWL<23350> A_IWL<23349> A_IWL<23348> A_IWL<23347> A_IWL<23346> A_IWL<23345> A_IWL<23344> A_IWL<23343> A_IWL<23342> A_IWL<23341> A_IWL<23340> A_IWL<23339> A_IWL<23338> A_IWL<23337> A_IWL<23336> A_IWL<23335> A_IWL<23334> A_IWL<23333> A_IWL<23332> A_IWL<23331> A_IWL<23330> A_IWL<23329> A_IWL<23328> A_IWL<23327> A_IWL<23326> A_IWL<23325> A_IWL<23324> A_IWL<23323> A_IWL<23322> A_IWL<23321> A_IWL<23320> A_IWL<23319> A_IWL<23318> A_IWL<23317> A_IWL<23316> A_IWL<23315> A_IWL<23314> A_IWL<23313> A_IWL<23312> A_IWL<23311> A_IWL<23310> A_IWL<23309> A_IWL<23308> A_IWL<23307> A_IWL<23306> A_IWL<23305> A_IWL<23304> A_IWL<23303> A_IWL<23302> A_IWL<23301> A_IWL<23300> A_IWL<23299> A_IWL<23298> A_IWL<23297> A_IWL<23296> A_IWL<23295> A_IWL<23294> A_IWL<23293> A_IWL<23292> A_IWL<23291> A_IWL<23290> A_IWL<23289> A_IWL<23288> A_IWL<23287> A_IWL<23286> A_IWL<23285> A_IWL<23284> A_IWL<23283> A_IWL<23282> A_IWL<23281> A_IWL<23280> A_IWL<23279> A_IWL<23278> A_IWL<23277> A_IWL<23276> A_IWL<23275> A_IWL<23274> A_IWL<23273> A_IWL<23272> A_IWL<23271> A_IWL<23270> A_IWL<23269> A_IWL<23268> A_IWL<23267> A_IWL<23266> A_IWL<23265> A_IWL<23264> A_IWL<23263> A_IWL<23262> A_IWL<23261> A_IWL<23260> A_IWL<23259> A_IWL<23258> A_IWL<23257> A_IWL<23256> A_IWL<23255> A_IWL<23254> A_IWL<23253> A_IWL<23252> A_IWL<23251> A_IWL<23250> A_IWL<23249> A_IWL<23248> A_IWL<23247> A_IWL<23246> A_IWL<23245> A_IWL<23244> A_IWL<23243> A_IWL<23242> A_IWL<23241> A_IWL<23240> A_IWL<23239> A_IWL<23238> A_IWL<23237> A_IWL<23236> A_IWL<23235> A_IWL<23234> A_IWL<23233> A_IWL<23232> A_IWL<23231> A_IWL<23230> A_IWL<23229> A_IWL<23228> A_IWL<23227> A_IWL<23226> A_IWL<23225> A_IWL<23224> A_IWL<23223> A_IWL<23222> A_IWL<23221> A_IWL<23220> A_IWL<23219> A_IWL<23218> A_IWL<23217> A_IWL<23216> A_IWL<23215> A_IWL<23214> A_IWL<23213> A_IWL<23212> A_IWL<23211> A_IWL<23210> A_IWL<23209> A_IWL<23208> A_IWL<23207> A_IWL<23206> A_IWL<23205> A_IWL<23204> A_IWL<23203> A_IWL<23202> A_IWL<23201> A_IWL<23200> A_IWL<23199> A_IWL<23198> A_IWL<23197> A_IWL<23196> A_IWL<23195> A_IWL<23194> A_IWL<23193> A_IWL<23192> A_IWL<23191> A_IWL<23190> A_IWL<23189> A_IWL<23188> A_IWL<23187> A_IWL<23186> A_IWL<23185> A_IWL<23184> A_IWL<23183> A_IWL<23182> A_IWL<23181> A_IWL<23180> A_IWL<23179> A_IWL<23178> A_IWL<23177> A_IWL<23176> A_IWL<23175> A_IWL<23174> A_IWL<23173> A_IWL<23172> A_IWL<23171> A_IWL<23170> A_IWL<23169> A_IWL<23168> A_IWL<23167> A_IWL<23166> A_IWL<23165> A_IWL<23164> A_IWL<23163> A_IWL<23162> A_IWL<23161> A_IWL<23160> A_IWL<23159> A_IWL<23158> A_IWL<23157> A_IWL<23156> A_IWL<23155> A_IWL<23154> A_IWL<23153> A_IWL<23152> A_IWL<23151> A_IWL<23150> A_IWL<23149> A_IWL<23148> A_IWL<23147> A_IWL<23146> A_IWL<23145> A_IWL<23144> A_IWL<23143> A_IWL<23142> A_IWL<23141> A_IWL<23140> A_IWL<23139> A_IWL<23138> A_IWL<23137> A_IWL<23136> A_IWL<23135> A_IWL<23134> A_IWL<23133> A_IWL<23132> A_IWL<23131> A_IWL<23130> A_IWL<23129> A_IWL<23128> A_IWL<23127> A_IWL<23126> A_IWL<23125> A_IWL<23124> A_IWL<23123> A_IWL<23122> A_IWL<23121> A_IWL<23120> A_IWL<23119> A_IWL<23118> A_IWL<23117> A_IWL<23116> A_IWL<23115> A_IWL<23114> A_IWL<23113> A_IWL<23112> A_IWL<23111> A_IWL<23110> A_IWL<23109> A_IWL<23108> A_IWL<23107> A_IWL<23106> A_IWL<23105> A_IWL<23104> A_IWL<23103> A_IWL<23102> A_IWL<23101> A_IWL<23100> A_IWL<23099> A_IWL<23098> A_IWL<23097> A_IWL<23096> A_IWL<23095> A_IWL<23094> A_IWL<23093> A_IWL<23092> A_IWL<23091> A_IWL<23090> A_IWL<23089> A_IWL<23088> A_IWL<23087> A_IWL<23086> A_IWL<23085> A_IWL<23084> A_IWL<23083> A_IWL<23082> A_IWL<23081> A_IWL<23080> A_IWL<23079> A_IWL<23078> A_IWL<23077> A_IWL<23076> A_IWL<23075> A_IWL<23074> A_IWL<23073> A_IWL<23072> A_IWL<23071> A_IWL<23070> A_IWL<23069> A_IWL<23068> A_IWL<23067> A_IWL<23066> A_IWL<23065> A_IWL<23064> A_IWL<23063> A_IWL<23062> A_IWL<23061> A_IWL<23060> A_IWL<23059> A_IWL<23058> A_IWL<23057> A_IWL<23056> A_IWL<23055> A_IWL<23054> A_IWL<23053> A_IWL<23052> A_IWL<23051> A_IWL<23050> A_IWL<23049> A_IWL<23048> A_IWL<23047> A_IWL<23046> A_IWL<23045> A_IWL<23044> A_IWL<23043> A_IWL<23042> A_IWL<23041> A_IWL<23040> VDD_CORE VSS / RM_IHPSG13_8192x32_c4_1P_COLUMN_pcell_0 +XCOL<44> A_BLC<89> A_BLC<88> A_BLC_TOP<89> A_BLC_TOP<88> A_BLT<89> A_BLT<88> A_BLT_TOP<89> A_BLT_TOP<88> A_IWL<22527> A_IWL<22526> A_IWL<22525> A_IWL<22524> A_IWL<22523> A_IWL<22522> A_IWL<22521> A_IWL<22520> A_IWL<22519> A_IWL<22518> A_IWL<22517> A_IWL<22516> A_IWL<22515> A_IWL<22514> A_IWL<22513> A_IWL<22512> A_IWL<22511> A_IWL<22510> A_IWL<22509> A_IWL<22508> A_IWL<22507> A_IWL<22506> A_IWL<22505> A_IWL<22504> A_IWL<22503> A_IWL<22502> A_IWL<22501> A_IWL<22500> A_IWL<22499> A_IWL<22498> A_IWL<22497> A_IWL<22496> A_IWL<22495> A_IWL<22494> A_IWL<22493> A_IWL<22492> A_IWL<22491> A_IWL<22490> A_IWL<22489> A_IWL<22488> A_IWL<22487> A_IWL<22486> A_IWL<22485> A_IWL<22484> A_IWL<22483> A_IWL<22482> A_IWL<22481> A_IWL<22480> A_IWL<22479> A_IWL<22478> A_IWL<22477> A_IWL<22476> A_IWL<22475> A_IWL<22474> A_IWL<22473> A_IWL<22472> A_IWL<22471> A_IWL<22470> A_IWL<22469> A_IWL<22468> A_IWL<22467> A_IWL<22466> A_IWL<22465> A_IWL<22464> A_IWL<22463> A_IWL<22462> A_IWL<22461> A_IWL<22460> A_IWL<22459> A_IWL<22458> A_IWL<22457> A_IWL<22456> A_IWL<22455> A_IWL<22454> A_IWL<22453> A_IWL<22452> A_IWL<22451> A_IWL<22450> A_IWL<22449> A_IWL<22448> A_IWL<22447> A_IWL<22446> A_IWL<22445> A_IWL<22444> A_IWL<22443> A_IWL<22442> A_IWL<22441> A_IWL<22440> A_IWL<22439> A_IWL<22438> A_IWL<22437> A_IWL<22436> A_IWL<22435> A_IWL<22434> A_IWL<22433> A_IWL<22432> A_IWL<22431> A_IWL<22430> A_IWL<22429> A_IWL<22428> A_IWL<22427> A_IWL<22426> A_IWL<22425> A_IWL<22424> A_IWL<22423> A_IWL<22422> A_IWL<22421> A_IWL<22420> A_IWL<22419> A_IWL<22418> A_IWL<22417> A_IWL<22416> A_IWL<22415> A_IWL<22414> A_IWL<22413> A_IWL<22412> A_IWL<22411> A_IWL<22410> A_IWL<22409> A_IWL<22408> A_IWL<22407> A_IWL<22406> A_IWL<22405> A_IWL<22404> A_IWL<22403> A_IWL<22402> A_IWL<22401> A_IWL<22400> A_IWL<22399> A_IWL<22398> A_IWL<22397> A_IWL<22396> A_IWL<22395> A_IWL<22394> A_IWL<22393> A_IWL<22392> A_IWL<22391> A_IWL<22390> A_IWL<22389> A_IWL<22388> A_IWL<22387> A_IWL<22386> A_IWL<22385> A_IWL<22384> A_IWL<22383> A_IWL<22382> A_IWL<22381> A_IWL<22380> A_IWL<22379> A_IWL<22378> A_IWL<22377> A_IWL<22376> A_IWL<22375> A_IWL<22374> A_IWL<22373> A_IWL<22372> A_IWL<22371> A_IWL<22370> A_IWL<22369> A_IWL<22368> A_IWL<22367> A_IWL<22366> A_IWL<22365> A_IWL<22364> A_IWL<22363> A_IWL<22362> A_IWL<22361> A_IWL<22360> A_IWL<22359> A_IWL<22358> A_IWL<22357> A_IWL<22356> A_IWL<22355> A_IWL<22354> A_IWL<22353> A_IWL<22352> A_IWL<22351> A_IWL<22350> A_IWL<22349> A_IWL<22348> A_IWL<22347> A_IWL<22346> A_IWL<22345> A_IWL<22344> A_IWL<22343> A_IWL<22342> A_IWL<22341> A_IWL<22340> A_IWL<22339> A_IWL<22338> A_IWL<22337> A_IWL<22336> A_IWL<22335> A_IWL<22334> A_IWL<22333> A_IWL<22332> A_IWL<22331> A_IWL<22330> A_IWL<22329> A_IWL<22328> A_IWL<22327> A_IWL<22326> A_IWL<22325> A_IWL<22324> A_IWL<22323> A_IWL<22322> A_IWL<22321> A_IWL<22320> A_IWL<22319> A_IWL<22318> A_IWL<22317> A_IWL<22316> A_IWL<22315> A_IWL<22314> A_IWL<22313> A_IWL<22312> A_IWL<22311> A_IWL<22310> A_IWL<22309> A_IWL<22308> A_IWL<22307> A_IWL<22306> A_IWL<22305> A_IWL<22304> A_IWL<22303> A_IWL<22302> A_IWL<22301> A_IWL<22300> A_IWL<22299> A_IWL<22298> A_IWL<22297> A_IWL<22296> A_IWL<22295> A_IWL<22294> A_IWL<22293> A_IWL<22292> A_IWL<22291> A_IWL<22290> A_IWL<22289> A_IWL<22288> A_IWL<22287> A_IWL<22286> A_IWL<22285> A_IWL<22284> A_IWL<22283> A_IWL<22282> A_IWL<22281> A_IWL<22280> A_IWL<22279> A_IWL<22278> A_IWL<22277> A_IWL<22276> A_IWL<22275> A_IWL<22274> A_IWL<22273> A_IWL<22272> A_IWL<22271> A_IWL<22270> A_IWL<22269> A_IWL<22268> A_IWL<22267> A_IWL<22266> A_IWL<22265> A_IWL<22264> A_IWL<22263> A_IWL<22262> A_IWL<22261> A_IWL<22260> A_IWL<22259> A_IWL<22258> A_IWL<22257> A_IWL<22256> A_IWL<22255> A_IWL<22254> A_IWL<22253> A_IWL<22252> A_IWL<22251> A_IWL<22250> A_IWL<22249> A_IWL<22248> A_IWL<22247> A_IWL<22246> A_IWL<22245> A_IWL<22244> A_IWL<22243> A_IWL<22242> A_IWL<22241> A_IWL<22240> A_IWL<22239> A_IWL<22238> A_IWL<22237> A_IWL<22236> A_IWL<22235> A_IWL<22234> A_IWL<22233> A_IWL<22232> A_IWL<22231> A_IWL<22230> A_IWL<22229> A_IWL<22228> A_IWL<22227> A_IWL<22226> A_IWL<22225> A_IWL<22224> A_IWL<22223> A_IWL<22222> A_IWL<22221> A_IWL<22220> A_IWL<22219> A_IWL<22218> A_IWL<22217> A_IWL<22216> A_IWL<22215> A_IWL<22214> A_IWL<22213> A_IWL<22212> A_IWL<22211> A_IWL<22210> A_IWL<22209> A_IWL<22208> A_IWL<22207> A_IWL<22206> A_IWL<22205> A_IWL<22204> A_IWL<22203> A_IWL<22202> A_IWL<22201> A_IWL<22200> A_IWL<22199> A_IWL<22198> A_IWL<22197> A_IWL<22196> A_IWL<22195> A_IWL<22194> A_IWL<22193> A_IWL<22192> A_IWL<22191> A_IWL<22190> A_IWL<22189> A_IWL<22188> A_IWL<22187> A_IWL<22186> A_IWL<22185> A_IWL<22184> A_IWL<22183> A_IWL<22182> A_IWL<22181> A_IWL<22180> A_IWL<22179> A_IWL<22178> A_IWL<22177> A_IWL<22176> A_IWL<22175> A_IWL<22174> A_IWL<22173> A_IWL<22172> A_IWL<22171> A_IWL<22170> A_IWL<22169> A_IWL<22168> A_IWL<22167> A_IWL<22166> A_IWL<22165> A_IWL<22164> A_IWL<22163> A_IWL<22162> A_IWL<22161> A_IWL<22160> A_IWL<22159> A_IWL<22158> A_IWL<22157> A_IWL<22156> A_IWL<22155> A_IWL<22154> A_IWL<22153> A_IWL<22152> A_IWL<22151> A_IWL<22150> A_IWL<22149> A_IWL<22148> A_IWL<22147> A_IWL<22146> A_IWL<22145> A_IWL<22144> A_IWL<22143> A_IWL<22142> A_IWL<22141> A_IWL<22140> A_IWL<22139> A_IWL<22138> A_IWL<22137> A_IWL<22136> A_IWL<22135> A_IWL<22134> A_IWL<22133> A_IWL<22132> A_IWL<22131> A_IWL<22130> A_IWL<22129> A_IWL<22128> A_IWL<22127> A_IWL<22126> A_IWL<22125> A_IWL<22124> A_IWL<22123> A_IWL<22122> A_IWL<22121> A_IWL<22120> A_IWL<22119> A_IWL<22118> A_IWL<22117> A_IWL<22116> A_IWL<22115> A_IWL<22114> A_IWL<22113> A_IWL<22112> A_IWL<22111> A_IWL<22110> A_IWL<22109> A_IWL<22108> A_IWL<22107> A_IWL<22106> A_IWL<22105> A_IWL<22104> A_IWL<22103> A_IWL<22102> A_IWL<22101> A_IWL<22100> A_IWL<22099> A_IWL<22098> A_IWL<22097> A_IWL<22096> A_IWL<22095> A_IWL<22094> A_IWL<22093> A_IWL<22092> A_IWL<22091> A_IWL<22090> A_IWL<22089> A_IWL<22088> A_IWL<22087> A_IWL<22086> A_IWL<22085> A_IWL<22084> A_IWL<22083> A_IWL<22082> A_IWL<22081> A_IWL<22080> A_IWL<22079> A_IWL<22078> A_IWL<22077> A_IWL<22076> A_IWL<22075> A_IWL<22074> A_IWL<22073> A_IWL<22072> A_IWL<22071> A_IWL<22070> A_IWL<22069> A_IWL<22068> A_IWL<22067> A_IWL<22066> A_IWL<22065> A_IWL<22064> A_IWL<22063> A_IWL<22062> A_IWL<22061> A_IWL<22060> A_IWL<22059> A_IWL<22058> A_IWL<22057> A_IWL<22056> A_IWL<22055> A_IWL<22054> A_IWL<22053> A_IWL<22052> A_IWL<22051> A_IWL<22050> A_IWL<22049> A_IWL<22048> A_IWL<22047> A_IWL<22046> A_IWL<22045> A_IWL<22044> A_IWL<22043> A_IWL<22042> A_IWL<22041> A_IWL<22040> A_IWL<22039> A_IWL<22038> A_IWL<22037> A_IWL<22036> A_IWL<22035> A_IWL<22034> A_IWL<22033> A_IWL<22032> A_IWL<22031> A_IWL<22030> A_IWL<22029> A_IWL<22028> A_IWL<22027> A_IWL<22026> A_IWL<22025> A_IWL<22024> A_IWL<22023> A_IWL<22022> A_IWL<22021> A_IWL<22020> A_IWL<22019> A_IWL<22018> A_IWL<22017> A_IWL<22016> A_IWL<23039> A_IWL<23038> A_IWL<23037> A_IWL<23036> A_IWL<23035> A_IWL<23034> A_IWL<23033> A_IWL<23032> A_IWL<23031> A_IWL<23030> A_IWL<23029> A_IWL<23028> A_IWL<23027> A_IWL<23026> A_IWL<23025> A_IWL<23024> A_IWL<23023> A_IWL<23022> A_IWL<23021> A_IWL<23020> A_IWL<23019> A_IWL<23018> A_IWL<23017> A_IWL<23016> A_IWL<23015> A_IWL<23014> A_IWL<23013> A_IWL<23012> A_IWL<23011> A_IWL<23010> A_IWL<23009> A_IWL<23008> A_IWL<23007> A_IWL<23006> A_IWL<23005> A_IWL<23004> A_IWL<23003> A_IWL<23002> A_IWL<23001> A_IWL<23000> A_IWL<22999> A_IWL<22998> A_IWL<22997> A_IWL<22996> A_IWL<22995> A_IWL<22994> A_IWL<22993> A_IWL<22992> A_IWL<22991> A_IWL<22990> A_IWL<22989> A_IWL<22988> A_IWL<22987> A_IWL<22986> A_IWL<22985> A_IWL<22984> A_IWL<22983> A_IWL<22982> A_IWL<22981> A_IWL<22980> A_IWL<22979> A_IWL<22978> A_IWL<22977> A_IWL<22976> A_IWL<22975> A_IWL<22974> A_IWL<22973> A_IWL<22972> A_IWL<22971> A_IWL<22970> A_IWL<22969> A_IWL<22968> A_IWL<22967> A_IWL<22966> A_IWL<22965> A_IWL<22964> A_IWL<22963> A_IWL<22962> A_IWL<22961> A_IWL<22960> A_IWL<22959> A_IWL<22958> A_IWL<22957> A_IWL<22956> A_IWL<22955> A_IWL<22954> A_IWL<22953> A_IWL<22952> A_IWL<22951> A_IWL<22950> A_IWL<22949> A_IWL<22948> A_IWL<22947> A_IWL<22946> A_IWL<22945> A_IWL<22944> A_IWL<22943> A_IWL<22942> A_IWL<22941> A_IWL<22940> A_IWL<22939> A_IWL<22938> A_IWL<22937> A_IWL<22936> A_IWL<22935> A_IWL<22934> A_IWL<22933> A_IWL<22932> A_IWL<22931> A_IWL<22930> A_IWL<22929> A_IWL<22928> A_IWL<22927> A_IWL<22926> A_IWL<22925> A_IWL<22924> A_IWL<22923> A_IWL<22922> A_IWL<22921> A_IWL<22920> A_IWL<22919> A_IWL<22918> A_IWL<22917> A_IWL<22916> A_IWL<22915> A_IWL<22914> A_IWL<22913> A_IWL<22912> A_IWL<22911> A_IWL<22910> A_IWL<22909> A_IWL<22908> A_IWL<22907> A_IWL<22906> A_IWL<22905> A_IWL<22904> A_IWL<22903> A_IWL<22902> A_IWL<22901> A_IWL<22900> A_IWL<22899> A_IWL<22898> A_IWL<22897> A_IWL<22896> A_IWL<22895> A_IWL<22894> A_IWL<22893> A_IWL<22892> A_IWL<22891> A_IWL<22890> A_IWL<22889> A_IWL<22888> A_IWL<22887> A_IWL<22886> A_IWL<22885> A_IWL<22884> A_IWL<22883> A_IWL<22882> A_IWL<22881> A_IWL<22880> A_IWL<22879> A_IWL<22878> A_IWL<22877> A_IWL<22876> A_IWL<22875> A_IWL<22874> A_IWL<22873> A_IWL<22872> A_IWL<22871> A_IWL<22870> A_IWL<22869> A_IWL<22868> A_IWL<22867> A_IWL<22866> A_IWL<22865> A_IWL<22864> A_IWL<22863> A_IWL<22862> A_IWL<22861> A_IWL<22860> A_IWL<22859> A_IWL<22858> A_IWL<22857> A_IWL<22856> A_IWL<22855> A_IWL<22854> A_IWL<22853> A_IWL<22852> A_IWL<22851> A_IWL<22850> A_IWL<22849> A_IWL<22848> A_IWL<22847> A_IWL<22846> A_IWL<22845> A_IWL<22844> A_IWL<22843> A_IWL<22842> A_IWL<22841> A_IWL<22840> A_IWL<22839> A_IWL<22838> A_IWL<22837> A_IWL<22836> A_IWL<22835> A_IWL<22834> A_IWL<22833> A_IWL<22832> A_IWL<22831> A_IWL<22830> A_IWL<22829> A_IWL<22828> A_IWL<22827> A_IWL<22826> A_IWL<22825> A_IWL<22824> A_IWL<22823> A_IWL<22822> A_IWL<22821> A_IWL<22820> A_IWL<22819> A_IWL<22818> A_IWL<22817> A_IWL<22816> A_IWL<22815> A_IWL<22814> A_IWL<22813> A_IWL<22812> A_IWL<22811> A_IWL<22810> A_IWL<22809> A_IWL<22808> A_IWL<22807> A_IWL<22806> A_IWL<22805> A_IWL<22804> A_IWL<22803> A_IWL<22802> A_IWL<22801> A_IWL<22800> A_IWL<22799> A_IWL<22798> A_IWL<22797> A_IWL<22796> A_IWL<22795> A_IWL<22794> A_IWL<22793> A_IWL<22792> A_IWL<22791> A_IWL<22790> A_IWL<22789> A_IWL<22788> A_IWL<22787> A_IWL<22786> A_IWL<22785> A_IWL<22784> A_IWL<22783> A_IWL<22782> A_IWL<22781> A_IWL<22780> A_IWL<22779> A_IWL<22778> A_IWL<22777> A_IWL<22776> A_IWL<22775> A_IWL<22774> A_IWL<22773> A_IWL<22772> A_IWL<22771> A_IWL<22770> A_IWL<22769> A_IWL<22768> A_IWL<22767> A_IWL<22766> A_IWL<22765> A_IWL<22764> A_IWL<22763> A_IWL<22762> A_IWL<22761> A_IWL<22760> A_IWL<22759> A_IWL<22758> A_IWL<22757> A_IWL<22756> A_IWL<22755> A_IWL<22754> A_IWL<22753> A_IWL<22752> A_IWL<22751> A_IWL<22750> A_IWL<22749> A_IWL<22748> A_IWL<22747> A_IWL<22746> A_IWL<22745> A_IWL<22744> A_IWL<22743> A_IWL<22742> A_IWL<22741> A_IWL<22740> A_IWL<22739> A_IWL<22738> A_IWL<22737> A_IWL<22736> A_IWL<22735> A_IWL<22734> A_IWL<22733> A_IWL<22732> A_IWL<22731> A_IWL<22730> A_IWL<22729> A_IWL<22728> A_IWL<22727> A_IWL<22726> A_IWL<22725> A_IWL<22724> A_IWL<22723> A_IWL<22722> A_IWL<22721> A_IWL<22720> A_IWL<22719> A_IWL<22718> A_IWL<22717> A_IWL<22716> A_IWL<22715> A_IWL<22714> A_IWL<22713> A_IWL<22712> A_IWL<22711> A_IWL<22710> A_IWL<22709> A_IWL<22708> A_IWL<22707> A_IWL<22706> A_IWL<22705> A_IWL<22704> A_IWL<22703> A_IWL<22702> A_IWL<22701> A_IWL<22700> A_IWL<22699> A_IWL<22698> A_IWL<22697> A_IWL<22696> A_IWL<22695> A_IWL<22694> A_IWL<22693> A_IWL<22692> A_IWL<22691> A_IWL<22690> A_IWL<22689> A_IWL<22688> A_IWL<22687> A_IWL<22686> A_IWL<22685> A_IWL<22684> A_IWL<22683> A_IWL<22682> A_IWL<22681> A_IWL<22680> A_IWL<22679> A_IWL<22678> A_IWL<22677> A_IWL<22676> A_IWL<22675> A_IWL<22674> A_IWL<22673> A_IWL<22672> A_IWL<22671> A_IWL<22670> A_IWL<22669> A_IWL<22668> A_IWL<22667> A_IWL<22666> A_IWL<22665> A_IWL<22664> A_IWL<22663> A_IWL<22662> A_IWL<22661> A_IWL<22660> A_IWL<22659> A_IWL<22658> A_IWL<22657> A_IWL<22656> A_IWL<22655> A_IWL<22654> A_IWL<22653> A_IWL<22652> A_IWL<22651> A_IWL<22650> A_IWL<22649> A_IWL<22648> A_IWL<22647> A_IWL<22646> A_IWL<22645> A_IWL<22644> A_IWL<22643> A_IWL<22642> A_IWL<22641> A_IWL<22640> A_IWL<22639> A_IWL<22638> A_IWL<22637> A_IWL<22636> A_IWL<22635> A_IWL<22634> A_IWL<22633> A_IWL<22632> A_IWL<22631> A_IWL<22630> A_IWL<22629> A_IWL<22628> A_IWL<22627> A_IWL<22626> A_IWL<22625> A_IWL<22624> A_IWL<22623> A_IWL<22622> A_IWL<22621> A_IWL<22620> A_IWL<22619> A_IWL<22618> A_IWL<22617> A_IWL<22616> A_IWL<22615> A_IWL<22614> A_IWL<22613> A_IWL<22612> A_IWL<22611> A_IWL<22610> A_IWL<22609> A_IWL<22608> A_IWL<22607> A_IWL<22606> A_IWL<22605> A_IWL<22604> A_IWL<22603> A_IWL<22602> A_IWL<22601> A_IWL<22600> A_IWL<22599> A_IWL<22598> A_IWL<22597> A_IWL<22596> A_IWL<22595> A_IWL<22594> A_IWL<22593> A_IWL<22592> A_IWL<22591> A_IWL<22590> A_IWL<22589> A_IWL<22588> A_IWL<22587> A_IWL<22586> A_IWL<22585> A_IWL<22584> A_IWL<22583> A_IWL<22582> A_IWL<22581> A_IWL<22580> A_IWL<22579> A_IWL<22578> A_IWL<22577> A_IWL<22576> A_IWL<22575> A_IWL<22574> A_IWL<22573> A_IWL<22572> A_IWL<22571> A_IWL<22570> A_IWL<22569> A_IWL<22568> A_IWL<22567> A_IWL<22566> A_IWL<22565> A_IWL<22564> A_IWL<22563> A_IWL<22562> A_IWL<22561> A_IWL<22560> A_IWL<22559> A_IWL<22558> A_IWL<22557> A_IWL<22556> A_IWL<22555> A_IWL<22554> A_IWL<22553> A_IWL<22552> A_IWL<22551> A_IWL<22550> A_IWL<22549> A_IWL<22548> A_IWL<22547> A_IWL<22546> A_IWL<22545> A_IWL<22544> A_IWL<22543> A_IWL<22542> A_IWL<22541> A_IWL<22540> A_IWL<22539> A_IWL<22538> A_IWL<22537> A_IWL<22536> A_IWL<22535> A_IWL<22534> A_IWL<22533> A_IWL<22532> A_IWL<22531> A_IWL<22530> A_IWL<22529> A_IWL<22528> VDD_CORE VSS / RM_IHPSG13_8192x32_c4_1P_COLUMN_pcell_0 +XCOL<43> A_BLC<87> A_BLC<86> A_BLC_TOP<87> A_BLC_TOP<86> A_BLT<87> A_BLT<86> A_BLT_TOP<87> A_BLT_TOP<86> A_IWL<22015> A_IWL<22014> A_IWL<22013> A_IWL<22012> A_IWL<22011> A_IWL<22010> A_IWL<22009> A_IWL<22008> A_IWL<22007> A_IWL<22006> A_IWL<22005> A_IWL<22004> A_IWL<22003> A_IWL<22002> A_IWL<22001> A_IWL<22000> A_IWL<21999> A_IWL<21998> A_IWL<21997> A_IWL<21996> A_IWL<21995> A_IWL<21994> A_IWL<21993> A_IWL<21992> A_IWL<21991> A_IWL<21990> A_IWL<21989> A_IWL<21988> A_IWL<21987> A_IWL<21986> A_IWL<21985> A_IWL<21984> A_IWL<21983> A_IWL<21982> A_IWL<21981> A_IWL<21980> A_IWL<21979> A_IWL<21978> A_IWL<21977> A_IWL<21976> A_IWL<21975> A_IWL<21974> A_IWL<21973> A_IWL<21972> A_IWL<21971> A_IWL<21970> A_IWL<21969> A_IWL<21968> A_IWL<21967> A_IWL<21966> A_IWL<21965> A_IWL<21964> A_IWL<21963> A_IWL<21962> A_IWL<21961> A_IWL<21960> A_IWL<21959> A_IWL<21958> A_IWL<21957> A_IWL<21956> A_IWL<21955> A_IWL<21954> A_IWL<21953> A_IWL<21952> A_IWL<21951> A_IWL<21950> A_IWL<21949> A_IWL<21948> A_IWL<21947> A_IWL<21946> A_IWL<21945> A_IWL<21944> A_IWL<21943> A_IWL<21942> A_IWL<21941> A_IWL<21940> A_IWL<21939> A_IWL<21938> A_IWL<21937> A_IWL<21936> A_IWL<21935> A_IWL<21934> A_IWL<21933> A_IWL<21932> A_IWL<21931> A_IWL<21930> A_IWL<21929> A_IWL<21928> A_IWL<21927> A_IWL<21926> A_IWL<21925> A_IWL<21924> A_IWL<21923> A_IWL<21922> A_IWL<21921> A_IWL<21920> A_IWL<21919> A_IWL<21918> A_IWL<21917> A_IWL<21916> A_IWL<21915> A_IWL<21914> A_IWL<21913> A_IWL<21912> A_IWL<21911> A_IWL<21910> A_IWL<21909> A_IWL<21908> A_IWL<21907> A_IWL<21906> A_IWL<21905> A_IWL<21904> A_IWL<21903> A_IWL<21902> A_IWL<21901> A_IWL<21900> A_IWL<21899> A_IWL<21898> A_IWL<21897> A_IWL<21896> A_IWL<21895> A_IWL<21894> A_IWL<21893> A_IWL<21892> A_IWL<21891> A_IWL<21890> A_IWL<21889> A_IWL<21888> A_IWL<21887> A_IWL<21886> A_IWL<21885> A_IWL<21884> A_IWL<21883> A_IWL<21882> A_IWL<21881> A_IWL<21880> A_IWL<21879> A_IWL<21878> A_IWL<21877> A_IWL<21876> A_IWL<21875> A_IWL<21874> A_IWL<21873> A_IWL<21872> A_IWL<21871> A_IWL<21870> A_IWL<21869> A_IWL<21868> A_IWL<21867> A_IWL<21866> A_IWL<21865> A_IWL<21864> A_IWL<21863> A_IWL<21862> A_IWL<21861> A_IWL<21860> A_IWL<21859> A_IWL<21858> A_IWL<21857> A_IWL<21856> A_IWL<21855> A_IWL<21854> A_IWL<21853> A_IWL<21852> A_IWL<21851> A_IWL<21850> A_IWL<21849> A_IWL<21848> A_IWL<21847> A_IWL<21846> A_IWL<21845> A_IWL<21844> A_IWL<21843> A_IWL<21842> A_IWL<21841> A_IWL<21840> A_IWL<21839> A_IWL<21838> A_IWL<21837> A_IWL<21836> A_IWL<21835> A_IWL<21834> A_IWL<21833> A_IWL<21832> A_IWL<21831> A_IWL<21830> A_IWL<21829> A_IWL<21828> A_IWL<21827> A_IWL<21826> A_IWL<21825> A_IWL<21824> A_IWL<21823> A_IWL<21822> A_IWL<21821> A_IWL<21820> A_IWL<21819> A_IWL<21818> A_IWL<21817> A_IWL<21816> A_IWL<21815> A_IWL<21814> A_IWL<21813> A_IWL<21812> A_IWL<21811> A_IWL<21810> A_IWL<21809> A_IWL<21808> A_IWL<21807> A_IWL<21806> A_IWL<21805> A_IWL<21804> A_IWL<21803> A_IWL<21802> A_IWL<21801> A_IWL<21800> A_IWL<21799> A_IWL<21798> A_IWL<21797> A_IWL<21796> A_IWL<21795> A_IWL<21794> A_IWL<21793> A_IWL<21792> A_IWL<21791> A_IWL<21790> A_IWL<21789> A_IWL<21788> A_IWL<21787> A_IWL<21786> A_IWL<21785> A_IWL<21784> A_IWL<21783> A_IWL<21782> A_IWL<21781> A_IWL<21780> A_IWL<21779> A_IWL<21778> A_IWL<21777> A_IWL<21776> A_IWL<21775> A_IWL<21774> A_IWL<21773> A_IWL<21772> A_IWL<21771> A_IWL<21770> A_IWL<21769> A_IWL<21768> A_IWL<21767> A_IWL<21766> A_IWL<21765> A_IWL<21764> A_IWL<21763> A_IWL<21762> A_IWL<21761> A_IWL<21760> A_IWL<21759> A_IWL<21758> A_IWL<21757> A_IWL<21756> A_IWL<21755> A_IWL<21754> A_IWL<21753> A_IWL<21752> A_IWL<21751> A_IWL<21750> A_IWL<21749> A_IWL<21748> A_IWL<21747> A_IWL<21746> A_IWL<21745> A_IWL<21744> A_IWL<21743> A_IWL<21742> A_IWL<21741> A_IWL<21740> A_IWL<21739> A_IWL<21738> A_IWL<21737> A_IWL<21736> A_IWL<21735> A_IWL<21734> A_IWL<21733> A_IWL<21732> A_IWL<21731> A_IWL<21730> A_IWL<21729> A_IWL<21728> A_IWL<21727> A_IWL<21726> A_IWL<21725> A_IWL<21724> A_IWL<21723> A_IWL<21722> A_IWL<21721> A_IWL<21720> A_IWL<21719> A_IWL<21718> A_IWL<21717> A_IWL<21716> A_IWL<21715> A_IWL<21714> A_IWL<21713> A_IWL<21712> A_IWL<21711> A_IWL<21710> A_IWL<21709> A_IWL<21708> A_IWL<21707> A_IWL<21706> A_IWL<21705> A_IWL<21704> A_IWL<21703> A_IWL<21702> A_IWL<21701> A_IWL<21700> A_IWL<21699> A_IWL<21698> A_IWL<21697> A_IWL<21696> A_IWL<21695> A_IWL<21694> A_IWL<21693> A_IWL<21692> A_IWL<21691> A_IWL<21690> A_IWL<21689> A_IWL<21688> A_IWL<21687> A_IWL<21686> A_IWL<21685> A_IWL<21684> A_IWL<21683> A_IWL<21682> A_IWL<21681> A_IWL<21680> A_IWL<21679> A_IWL<21678> A_IWL<21677> A_IWL<21676> A_IWL<21675> A_IWL<21674> A_IWL<21673> A_IWL<21672> A_IWL<21671> A_IWL<21670> A_IWL<21669> A_IWL<21668> A_IWL<21667> A_IWL<21666> A_IWL<21665> A_IWL<21664> A_IWL<21663> A_IWL<21662> A_IWL<21661> A_IWL<21660> A_IWL<21659> A_IWL<21658> A_IWL<21657> A_IWL<21656> A_IWL<21655> A_IWL<21654> A_IWL<21653> A_IWL<21652> A_IWL<21651> A_IWL<21650> A_IWL<21649> A_IWL<21648> A_IWL<21647> A_IWL<21646> A_IWL<21645> A_IWL<21644> A_IWL<21643> A_IWL<21642> A_IWL<21641> A_IWL<21640> A_IWL<21639> A_IWL<21638> A_IWL<21637> A_IWL<21636> A_IWL<21635> A_IWL<21634> A_IWL<21633> A_IWL<21632> A_IWL<21631> A_IWL<21630> A_IWL<21629> A_IWL<21628> A_IWL<21627> A_IWL<21626> A_IWL<21625> A_IWL<21624> A_IWL<21623> A_IWL<21622> A_IWL<21621> A_IWL<21620> A_IWL<21619> A_IWL<21618> A_IWL<21617> A_IWL<21616> A_IWL<21615> A_IWL<21614> A_IWL<21613> A_IWL<21612> A_IWL<21611> A_IWL<21610> A_IWL<21609> A_IWL<21608> A_IWL<21607> A_IWL<21606> A_IWL<21605> A_IWL<21604> A_IWL<21603> A_IWL<21602> A_IWL<21601> A_IWL<21600> A_IWL<21599> A_IWL<21598> A_IWL<21597> A_IWL<21596> A_IWL<21595> A_IWL<21594> A_IWL<21593> A_IWL<21592> A_IWL<21591> A_IWL<21590> A_IWL<21589> A_IWL<21588> A_IWL<21587> A_IWL<21586> A_IWL<21585> A_IWL<21584> A_IWL<21583> A_IWL<21582> A_IWL<21581> A_IWL<21580> A_IWL<21579> A_IWL<21578> A_IWL<21577> A_IWL<21576> A_IWL<21575> A_IWL<21574> A_IWL<21573> A_IWL<21572> A_IWL<21571> A_IWL<21570> A_IWL<21569> A_IWL<21568> A_IWL<21567> A_IWL<21566> A_IWL<21565> A_IWL<21564> A_IWL<21563> A_IWL<21562> A_IWL<21561> A_IWL<21560> A_IWL<21559> A_IWL<21558> A_IWL<21557> A_IWL<21556> A_IWL<21555> A_IWL<21554> A_IWL<21553> A_IWL<21552> A_IWL<21551> A_IWL<21550> A_IWL<21549> A_IWL<21548> A_IWL<21547> A_IWL<21546> A_IWL<21545> A_IWL<21544> A_IWL<21543> A_IWL<21542> A_IWL<21541> A_IWL<21540> A_IWL<21539> A_IWL<21538> A_IWL<21537> A_IWL<21536> A_IWL<21535> A_IWL<21534> A_IWL<21533> A_IWL<21532> A_IWL<21531> A_IWL<21530> A_IWL<21529> A_IWL<21528> A_IWL<21527> A_IWL<21526> A_IWL<21525> A_IWL<21524> A_IWL<21523> A_IWL<21522> A_IWL<21521> A_IWL<21520> A_IWL<21519> A_IWL<21518> A_IWL<21517> A_IWL<21516> A_IWL<21515> A_IWL<21514> A_IWL<21513> A_IWL<21512> A_IWL<21511> A_IWL<21510> A_IWL<21509> A_IWL<21508> A_IWL<21507> A_IWL<21506> A_IWL<21505> A_IWL<21504> A_IWL<22527> A_IWL<22526> A_IWL<22525> A_IWL<22524> A_IWL<22523> A_IWL<22522> A_IWL<22521> A_IWL<22520> A_IWL<22519> A_IWL<22518> A_IWL<22517> A_IWL<22516> A_IWL<22515> A_IWL<22514> A_IWL<22513> A_IWL<22512> A_IWL<22511> A_IWL<22510> A_IWL<22509> A_IWL<22508> A_IWL<22507> A_IWL<22506> A_IWL<22505> A_IWL<22504> A_IWL<22503> A_IWL<22502> A_IWL<22501> A_IWL<22500> A_IWL<22499> A_IWL<22498> A_IWL<22497> A_IWL<22496> A_IWL<22495> A_IWL<22494> A_IWL<22493> A_IWL<22492> A_IWL<22491> A_IWL<22490> A_IWL<22489> A_IWL<22488> A_IWL<22487> A_IWL<22486> A_IWL<22485> A_IWL<22484> A_IWL<22483> A_IWL<22482> A_IWL<22481> A_IWL<22480> A_IWL<22479> A_IWL<22478> A_IWL<22477> A_IWL<22476> A_IWL<22475> A_IWL<22474> A_IWL<22473> A_IWL<22472> A_IWL<22471> A_IWL<22470> A_IWL<22469> A_IWL<22468> A_IWL<22467> A_IWL<22466> A_IWL<22465> A_IWL<22464> A_IWL<22463> A_IWL<22462> A_IWL<22461> A_IWL<22460> A_IWL<22459> A_IWL<22458> A_IWL<22457> A_IWL<22456> A_IWL<22455> A_IWL<22454> A_IWL<22453> A_IWL<22452> A_IWL<22451> A_IWL<22450> A_IWL<22449> A_IWL<22448> A_IWL<22447> A_IWL<22446> A_IWL<22445> A_IWL<22444> A_IWL<22443> A_IWL<22442> A_IWL<22441> A_IWL<22440> A_IWL<22439> A_IWL<22438> A_IWL<22437> A_IWL<22436> A_IWL<22435> A_IWL<22434> A_IWL<22433> A_IWL<22432> A_IWL<22431> A_IWL<22430> A_IWL<22429> A_IWL<22428> A_IWL<22427> A_IWL<22426> A_IWL<22425> A_IWL<22424> A_IWL<22423> A_IWL<22422> A_IWL<22421> A_IWL<22420> A_IWL<22419> A_IWL<22418> A_IWL<22417> A_IWL<22416> A_IWL<22415> A_IWL<22414> A_IWL<22413> A_IWL<22412> A_IWL<22411> A_IWL<22410> A_IWL<22409> A_IWL<22408> A_IWL<22407> A_IWL<22406> A_IWL<22405> A_IWL<22404> A_IWL<22403> A_IWL<22402> A_IWL<22401> A_IWL<22400> A_IWL<22399> A_IWL<22398> A_IWL<22397> A_IWL<22396> A_IWL<22395> A_IWL<22394> A_IWL<22393> A_IWL<22392> A_IWL<22391> A_IWL<22390> A_IWL<22389> A_IWL<22388> A_IWL<22387> A_IWL<22386> A_IWL<22385> A_IWL<22384> A_IWL<22383> A_IWL<22382> A_IWL<22381> A_IWL<22380> A_IWL<22379> A_IWL<22378> A_IWL<22377> A_IWL<22376> A_IWL<22375> A_IWL<22374> A_IWL<22373> A_IWL<22372> A_IWL<22371> A_IWL<22370> A_IWL<22369> A_IWL<22368> A_IWL<22367> A_IWL<22366> A_IWL<22365> A_IWL<22364> A_IWL<22363> A_IWL<22362> A_IWL<22361> A_IWL<22360> A_IWL<22359> A_IWL<22358> A_IWL<22357> A_IWL<22356> A_IWL<22355> A_IWL<22354> A_IWL<22353> A_IWL<22352> A_IWL<22351> A_IWL<22350> A_IWL<22349> A_IWL<22348> A_IWL<22347> A_IWL<22346> A_IWL<22345> A_IWL<22344> A_IWL<22343> A_IWL<22342> A_IWL<22341> A_IWL<22340> A_IWL<22339> A_IWL<22338> A_IWL<22337> A_IWL<22336> A_IWL<22335> A_IWL<22334> A_IWL<22333> A_IWL<22332> A_IWL<22331> A_IWL<22330> A_IWL<22329> A_IWL<22328> A_IWL<22327> A_IWL<22326> A_IWL<22325> A_IWL<22324> A_IWL<22323> A_IWL<22322> A_IWL<22321> A_IWL<22320> A_IWL<22319> A_IWL<22318> A_IWL<22317> A_IWL<22316> A_IWL<22315> A_IWL<22314> A_IWL<22313> A_IWL<22312> A_IWL<22311> A_IWL<22310> A_IWL<22309> A_IWL<22308> A_IWL<22307> A_IWL<22306> A_IWL<22305> A_IWL<22304> A_IWL<22303> A_IWL<22302> A_IWL<22301> A_IWL<22300> A_IWL<22299> A_IWL<22298> A_IWL<22297> A_IWL<22296> A_IWL<22295> A_IWL<22294> A_IWL<22293> A_IWL<22292> A_IWL<22291> A_IWL<22290> A_IWL<22289> A_IWL<22288> A_IWL<22287> A_IWL<22286> A_IWL<22285> A_IWL<22284> A_IWL<22283> A_IWL<22282> A_IWL<22281> A_IWL<22280> A_IWL<22279> A_IWL<22278> A_IWL<22277> A_IWL<22276> A_IWL<22275> A_IWL<22274> A_IWL<22273> A_IWL<22272> A_IWL<22271> A_IWL<22270> A_IWL<22269> A_IWL<22268> A_IWL<22267> A_IWL<22266> A_IWL<22265> A_IWL<22264> A_IWL<22263> A_IWL<22262> A_IWL<22261> A_IWL<22260> A_IWL<22259> A_IWL<22258> A_IWL<22257> A_IWL<22256> A_IWL<22255> A_IWL<22254> A_IWL<22253> A_IWL<22252> A_IWL<22251> A_IWL<22250> A_IWL<22249> A_IWL<22248> A_IWL<22247> A_IWL<22246> A_IWL<22245> A_IWL<22244> A_IWL<22243> A_IWL<22242> A_IWL<22241> A_IWL<22240> A_IWL<22239> A_IWL<22238> A_IWL<22237> A_IWL<22236> A_IWL<22235> A_IWL<22234> A_IWL<22233> A_IWL<22232> A_IWL<22231> A_IWL<22230> A_IWL<22229> A_IWL<22228> A_IWL<22227> A_IWL<22226> A_IWL<22225> A_IWL<22224> A_IWL<22223> A_IWL<22222> A_IWL<22221> A_IWL<22220> A_IWL<22219> A_IWL<22218> A_IWL<22217> A_IWL<22216> A_IWL<22215> A_IWL<22214> A_IWL<22213> A_IWL<22212> A_IWL<22211> A_IWL<22210> A_IWL<22209> A_IWL<22208> A_IWL<22207> A_IWL<22206> A_IWL<22205> A_IWL<22204> A_IWL<22203> A_IWL<22202> A_IWL<22201> A_IWL<22200> A_IWL<22199> A_IWL<22198> A_IWL<22197> A_IWL<22196> A_IWL<22195> A_IWL<22194> A_IWL<22193> A_IWL<22192> A_IWL<22191> A_IWL<22190> A_IWL<22189> A_IWL<22188> A_IWL<22187> A_IWL<22186> A_IWL<22185> A_IWL<22184> A_IWL<22183> A_IWL<22182> A_IWL<22181> A_IWL<22180> A_IWL<22179> A_IWL<22178> A_IWL<22177> A_IWL<22176> A_IWL<22175> A_IWL<22174> A_IWL<22173> A_IWL<22172> A_IWL<22171> A_IWL<22170> A_IWL<22169> A_IWL<22168> A_IWL<22167> A_IWL<22166> A_IWL<22165> A_IWL<22164> A_IWL<22163> A_IWL<22162> A_IWL<22161> A_IWL<22160> A_IWL<22159> A_IWL<22158> A_IWL<22157> A_IWL<22156> A_IWL<22155> A_IWL<22154> A_IWL<22153> A_IWL<22152> A_IWL<22151> A_IWL<22150> A_IWL<22149> A_IWL<22148> A_IWL<22147> A_IWL<22146> A_IWL<22145> A_IWL<22144> A_IWL<22143> A_IWL<22142> A_IWL<22141> A_IWL<22140> A_IWL<22139> A_IWL<22138> A_IWL<22137> A_IWL<22136> A_IWL<22135> A_IWL<22134> A_IWL<22133> A_IWL<22132> A_IWL<22131> A_IWL<22130> A_IWL<22129> A_IWL<22128> A_IWL<22127> A_IWL<22126> A_IWL<22125> A_IWL<22124> A_IWL<22123> A_IWL<22122> A_IWL<22121> A_IWL<22120> A_IWL<22119> A_IWL<22118> A_IWL<22117> A_IWL<22116> A_IWL<22115> A_IWL<22114> A_IWL<22113> A_IWL<22112> A_IWL<22111> A_IWL<22110> A_IWL<22109> A_IWL<22108> A_IWL<22107> A_IWL<22106> A_IWL<22105> A_IWL<22104> A_IWL<22103> A_IWL<22102> A_IWL<22101> A_IWL<22100> A_IWL<22099> A_IWL<22098> A_IWL<22097> A_IWL<22096> A_IWL<22095> A_IWL<22094> A_IWL<22093> A_IWL<22092> A_IWL<22091> A_IWL<22090> A_IWL<22089> A_IWL<22088> A_IWL<22087> A_IWL<22086> A_IWL<22085> A_IWL<22084> A_IWL<22083> A_IWL<22082> A_IWL<22081> A_IWL<22080> A_IWL<22079> A_IWL<22078> A_IWL<22077> A_IWL<22076> A_IWL<22075> A_IWL<22074> A_IWL<22073> A_IWL<22072> A_IWL<22071> A_IWL<22070> A_IWL<22069> A_IWL<22068> A_IWL<22067> A_IWL<22066> A_IWL<22065> A_IWL<22064> A_IWL<22063> A_IWL<22062> A_IWL<22061> A_IWL<22060> A_IWL<22059> A_IWL<22058> A_IWL<22057> A_IWL<22056> A_IWL<22055> A_IWL<22054> A_IWL<22053> A_IWL<22052> A_IWL<22051> A_IWL<22050> A_IWL<22049> A_IWL<22048> A_IWL<22047> A_IWL<22046> A_IWL<22045> A_IWL<22044> A_IWL<22043> A_IWL<22042> A_IWL<22041> A_IWL<22040> A_IWL<22039> A_IWL<22038> A_IWL<22037> A_IWL<22036> A_IWL<22035> A_IWL<22034> A_IWL<22033> A_IWL<22032> A_IWL<22031> A_IWL<22030> A_IWL<22029> A_IWL<22028> A_IWL<22027> A_IWL<22026> A_IWL<22025> A_IWL<22024> A_IWL<22023> A_IWL<22022> A_IWL<22021> A_IWL<22020> A_IWL<22019> A_IWL<22018> A_IWL<22017> A_IWL<22016> VDD_CORE VSS / RM_IHPSG13_8192x32_c4_1P_COLUMN_pcell_0 +XCOL<42> A_BLC<85> A_BLC<84> A_BLC_TOP<85> A_BLC_TOP<84> A_BLT<85> A_BLT<84> A_BLT_TOP<85> A_BLT_TOP<84> A_IWL<21503> A_IWL<21502> A_IWL<21501> A_IWL<21500> A_IWL<21499> A_IWL<21498> A_IWL<21497> A_IWL<21496> A_IWL<21495> A_IWL<21494> A_IWL<21493> A_IWL<21492> A_IWL<21491> A_IWL<21490> A_IWL<21489> A_IWL<21488> A_IWL<21487> A_IWL<21486> A_IWL<21485> A_IWL<21484> A_IWL<21483> A_IWL<21482> A_IWL<21481> A_IWL<21480> A_IWL<21479> A_IWL<21478> A_IWL<21477> A_IWL<21476> A_IWL<21475> A_IWL<21474> A_IWL<21473> A_IWL<21472> A_IWL<21471> A_IWL<21470> A_IWL<21469> A_IWL<21468> A_IWL<21467> A_IWL<21466> A_IWL<21465> A_IWL<21464> A_IWL<21463> A_IWL<21462> A_IWL<21461> A_IWL<21460> A_IWL<21459> A_IWL<21458> A_IWL<21457> A_IWL<21456> A_IWL<21455> A_IWL<21454> A_IWL<21453> A_IWL<21452> A_IWL<21451> A_IWL<21450> A_IWL<21449> A_IWL<21448> A_IWL<21447> A_IWL<21446> A_IWL<21445> A_IWL<21444> A_IWL<21443> A_IWL<21442> A_IWL<21441> A_IWL<21440> A_IWL<21439> A_IWL<21438> A_IWL<21437> A_IWL<21436> A_IWL<21435> A_IWL<21434> A_IWL<21433> A_IWL<21432> A_IWL<21431> A_IWL<21430> A_IWL<21429> A_IWL<21428> A_IWL<21427> A_IWL<21426> A_IWL<21425> A_IWL<21424> A_IWL<21423> A_IWL<21422> A_IWL<21421> A_IWL<21420> A_IWL<21419> A_IWL<21418> A_IWL<21417> A_IWL<21416> A_IWL<21415> A_IWL<21414> A_IWL<21413> A_IWL<21412> A_IWL<21411> A_IWL<21410> A_IWL<21409> A_IWL<21408> A_IWL<21407> A_IWL<21406> A_IWL<21405> A_IWL<21404> A_IWL<21403> A_IWL<21402> A_IWL<21401> A_IWL<21400> A_IWL<21399> A_IWL<21398> A_IWL<21397> A_IWL<21396> A_IWL<21395> A_IWL<21394> A_IWL<21393> A_IWL<21392> A_IWL<21391> A_IWL<21390> A_IWL<21389> A_IWL<21388> A_IWL<21387> A_IWL<21386> A_IWL<21385> A_IWL<21384> A_IWL<21383> A_IWL<21382> A_IWL<21381> A_IWL<21380> A_IWL<21379> A_IWL<21378> A_IWL<21377> A_IWL<21376> A_IWL<21375> A_IWL<21374> A_IWL<21373> A_IWL<21372> A_IWL<21371> A_IWL<21370> A_IWL<21369> A_IWL<21368> A_IWL<21367> A_IWL<21366> A_IWL<21365> A_IWL<21364> A_IWL<21363> A_IWL<21362> A_IWL<21361> A_IWL<21360> A_IWL<21359> A_IWL<21358> A_IWL<21357> A_IWL<21356> A_IWL<21355> A_IWL<21354> A_IWL<21353> A_IWL<21352> A_IWL<21351> A_IWL<21350> A_IWL<21349> A_IWL<21348> A_IWL<21347> A_IWL<21346> A_IWL<21345> A_IWL<21344> A_IWL<21343> A_IWL<21342> A_IWL<21341> A_IWL<21340> A_IWL<21339> A_IWL<21338> A_IWL<21337> A_IWL<21336> A_IWL<21335> A_IWL<21334> A_IWL<21333> A_IWL<21332> A_IWL<21331> A_IWL<21330> A_IWL<21329> A_IWL<21328> A_IWL<21327> A_IWL<21326> A_IWL<21325> A_IWL<21324> A_IWL<21323> A_IWL<21322> A_IWL<21321> A_IWL<21320> A_IWL<21319> A_IWL<21318> A_IWL<21317> A_IWL<21316> A_IWL<21315> A_IWL<21314> A_IWL<21313> A_IWL<21312> A_IWL<21311> A_IWL<21310> A_IWL<21309> A_IWL<21308> A_IWL<21307> A_IWL<21306> A_IWL<21305> A_IWL<21304> A_IWL<21303> A_IWL<21302> A_IWL<21301> A_IWL<21300> A_IWL<21299> A_IWL<21298> A_IWL<21297> A_IWL<21296> A_IWL<21295> A_IWL<21294> A_IWL<21293> A_IWL<21292> A_IWL<21291> A_IWL<21290> A_IWL<21289> A_IWL<21288> A_IWL<21287> A_IWL<21286> A_IWL<21285> A_IWL<21284> A_IWL<21283> A_IWL<21282> A_IWL<21281> A_IWL<21280> A_IWL<21279> A_IWL<21278> A_IWL<21277> A_IWL<21276> A_IWL<21275> A_IWL<21274> A_IWL<21273> A_IWL<21272> A_IWL<21271> A_IWL<21270> A_IWL<21269> A_IWL<21268> A_IWL<21267> A_IWL<21266> A_IWL<21265> A_IWL<21264> A_IWL<21263> A_IWL<21262> A_IWL<21261> A_IWL<21260> A_IWL<21259> A_IWL<21258> A_IWL<21257> A_IWL<21256> A_IWL<21255> A_IWL<21254> A_IWL<21253> A_IWL<21252> A_IWL<21251> A_IWL<21250> A_IWL<21249> A_IWL<21248> A_IWL<21247> A_IWL<21246> A_IWL<21245> A_IWL<21244> A_IWL<21243> A_IWL<21242> A_IWL<21241> A_IWL<21240> A_IWL<21239> A_IWL<21238> A_IWL<21237> A_IWL<21236> A_IWL<21235> A_IWL<21234> A_IWL<21233> A_IWL<21232> A_IWL<21231> A_IWL<21230> A_IWL<21229> A_IWL<21228> A_IWL<21227> A_IWL<21226> A_IWL<21225> A_IWL<21224> A_IWL<21223> A_IWL<21222> A_IWL<21221> A_IWL<21220> A_IWL<21219> A_IWL<21218> A_IWL<21217> A_IWL<21216> A_IWL<21215> A_IWL<21214> A_IWL<21213> A_IWL<21212> A_IWL<21211> A_IWL<21210> A_IWL<21209> A_IWL<21208> A_IWL<21207> A_IWL<21206> A_IWL<21205> A_IWL<21204> A_IWL<21203> A_IWL<21202> A_IWL<21201> A_IWL<21200> A_IWL<21199> A_IWL<21198> A_IWL<21197> A_IWL<21196> A_IWL<21195> A_IWL<21194> A_IWL<21193> A_IWL<21192> A_IWL<21191> A_IWL<21190> A_IWL<21189> A_IWL<21188> A_IWL<21187> A_IWL<21186> A_IWL<21185> A_IWL<21184> A_IWL<21183> A_IWL<21182> A_IWL<21181> A_IWL<21180> A_IWL<21179> A_IWL<21178> A_IWL<21177> A_IWL<21176> A_IWL<21175> A_IWL<21174> A_IWL<21173> A_IWL<21172> A_IWL<21171> A_IWL<21170> A_IWL<21169> A_IWL<21168> A_IWL<21167> A_IWL<21166> A_IWL<21165> A_IWL<21164> A_IWL<21163> A_IWL<21162> A_IWL<21161> A_IWL<21160> A_IWL<21159> A_IWL<21158> A_IWL<21157> A_IWL<21156> A_IWL<21155> A_IWL<21154> A_IWL<21153> A_IWL<21152> A_IWL<21151> A_IWL<21150> A_IWL<21149> A_IWL<21148> A_IWL<21147> A_IWL<21146> A_IWL<21145> A_IWL<21144> A_IWL<21143> A_IWL<21142> A_IWL<21141> A_IWL<21140> A_IWL<21139> A_IWL<21138> A_IWL<21137> A_IWL<21136> A_IWL<21135> A_IWL<21134> A_IWL<21133> A_IWL<21132> A_IWL<21131> A_IWL<21130> A_IWL<21129> A_IWL<21128> A_IWL<21127> A_IWL<21126> A_IWL<21125> A_IWL<21124> A_IWL<21123> A_IWL<21122> A_IWL<21121> A_IWL<21120> A_IWL<21119> A_IWL<21118> A_IWL<21117> A_IWL<21116> A_IWL<21115> A_IWL<21114> A_IWL<21113> A_IWL<21112> A_IWL<21111> A_IWL<21110> A_IWL<21109> A_IWL<21108> A_IWL<21107> A_IWL<21106> A_IWL<21105> A_IWL<21104> A_IWL<21103> A_IWL<21102> A_IWL<21101> A_IWL<21100> A_IWL<21099> A_IWL<21098> A_IWL<21097> A_IWL<21096> A_IWL<21095> A_IWL<21094> A_IWL<21093> A_IWL<21092> A_IWL<21091> A_IWL<21090> A_IWL<21089> A_IWL<21088> A_IWL<21087> A_IWL<21086> A_IWL<21085> A_IWL<21084> A_IWL<21083> A_IWL<21082> A_IWL<21081> A_IWL<21080> A_IWL<21079> A_IWL<21078> A_IWL<21077> A_IWL<21076> A_IWL<21075> A_IWL<21074> A_IWL<21073> A_IWL<21072> A_IWL<21071> A_IWL<21070> A_IWL<21069> A_IWL<21068> A_IWL<21067> A_IWL<21066> A_IWL<21065> A_IWL<21064> A_IWL<21063> A_IWL<21062> A_IWL<21061> A_IWL<21060> A_IWL<21059> A_IWL<21058> A_IWL<21057> A_IWL<21056> A_IWL<21055> A_IWL<21054> A_IWL<21053> A_IWL<21052> A_IWL<21051> A_IWL<21050> A_IWL<21049> A_IWL<21048> A_IWL<21047> A_IWL<21046> A_IWL<21045> A_IWL<21044> A_IWL<21043> A_IWL<21042> A_IWL<21041> A_IWL<21040> A_IWL<21039> A_IWL<21038> A_IWL<21037> A_IWL<21036> A_IWL<21035> A_IWL<21034> A_IWL<21033> A_IWL<21032> A_IWL<21031> A_IWL<21030> A_IWL<21029> A_IWL<21028> A_IWL<21027> A_IWL<21026> A_IWL<21025> A_IWL<21024> A_IWL<21023> A_IWL<21022> A_IWL<21021> A_IWL<21020> A_IWL<21019> A_IWL<21018> A_IWL<21017> A_IWL<21016> A_IWL<21015> A_IWL<21014> A_IWL<21013> A_IWL<21012> A_IWL<21011> A_IWL<21010> A_IWL<21009> A_IWL<21008> A_IWL<21007> A_IWL<21006> A_IWL<21005> A_IWL<21004> A_IWL<21003> A_IWL<21002> A_IWL<21001> A_IWL<21000> A_IWL<20999> A_IWL<20998> A_IWL<20997> A_IWL<20996> A_IWL<20995> A_IWL<20994> A_IWL<20993> A_IWL<20992> A_IWL<22015> A_IWL<22014> A_IWL<22013> A_IWL<22012> A_IWL<22011> A_IWL<22010> A_IWL<22009> A_IWL<22008> A_IWL<22007> A_IWL<22006> A_IWL<22005> A_IWL<22004> A_IWL<22003> A_IWL<22002> A_IWL<22001> A_IWL<22000> A_IWL<21999> A_IWL<21998> A_IWL<21997> A_IWL<21996> A_IWL<21995> A_IWL<21994> A_IWL<21993> A_IWL<21992> A_IWL<21991> A_IWL<21990> A_IWL<21989> A_IWL<21988> A_IWL<21987> A_IWL<21986> A_IWL<21985> A_IWL<21984> A_IWL<21983> A_IWL<21982> A_IWL<21981> A_IWL<21980> A_IWL<21979> A_IWL<21978> A_IWL<21977> A_IWL<21976> A_IWL<21975> A_IWL<21974> A_IWL<21973> A_IWL<21972> A_IWL<21971> A_IWL<21970> A_IWL<21969> A_IWL<21968> A_IWL<21967> A_IWL<21966> A_IWL<21965> A_IWL<21964> A_IWL<21963> A_IWL<21962> A_IWL<21961> A_IWL<21960> A_IWL<21959> A_IWL<21958> A_IWL<21957> A_IWL<21956> A_IWL<21955> A_IWL<21954> A_IWL<21953> A_IWL<21952> A_IWL<21951> A_IWL<21950> A_IWL<21949> A_IWL<21948> A_IWL<21947> A_IWL<21946> A_IWL<21945> A_IWL<21944> A_IWL<21943> A_IWL<21942> A_IWL<21941> A_IWL<21940> A_IWL<21939> A_IWL<21938> A_IWL<21937> A_IWL<21936> A_IWL<21935> A_IWL<21934> A_IWL<21933> A_IWL<21932> A_IWL<21931> A_IWL<21930> A_IWL<21929> A_IWL<21928> A_IWL<21927> A_IWL<21926> A_IWL<21925> A_IWL<21924> A_IWL<21923> A_IWL<21922> A_IWL<21921> A_IWL<21920> A_IWL<21919> A_IWL<21918> A_IWL<21917> A_IWL<21916> A_IWL<21915> A_IWL<21914> A_IWL<21913> A_IWL<21912> A_IWL<21911> A_IWL<21910> A_IWL<21909> A_IWL<21908> A_IWL<21907> A_IWL<21906> A_IWL<21905> A_IWL<21904> A_IWL<21903> A_IWL<21902> A_IWL<21901> A_IWL<21900> A_IWL<21899> A_IWL<21898> A_IWL<21897> A_IWL<21896> A_IWL<21895> A_IWL<21894> A_IWL<21893> A_IWL<21892> A_IWL<21891> A_IWL<21890> A_IWL<21889> A_IWL<21888> A_IWL<21887> A_IWL<21886> A_IWL<21885> A_IWL<21884> A_IWL<21883> A_IWL<21882> A_IWL<21881> A_IWL<21880> A_IWL<21879> A_IWL<21878> A_IWL<21877> A_IWL<21876> A_IWL<21875> A_IWL<21874> A_IWL<21873> A_IWL<21872> A_IWL<21871> A_IWL<21870> A_IWL<21869> A_IWL<21868> A_IWL<21867> A_IWL<21866> A_IWL<21865> A_IWL<21864> A_IWL<21863> A_IWL<21862> A_IWL<21861> A_IWL<21860> A_IWL<21859> A_IWL<21858> A_IWL<21857> A_IWL<21856> A_IWL<21855> A_IWL<21854> A_IWL<21853> A_IWL<21852> A_IWL<21851> A_IWL<21850> A_IWL<21849> A_IWL<21848> A_IWL<21847> A_IWL<21846> A_IWL<21845> A_IWL<21844> A_IWL<21843> A_IWL<21842> A_IWL<21841> A_IWL<21840> A_IWL<21839> A_IWL<21838> A_IWL<21837> A_IWL<21836> A_IWL<21835> A_IWL<21834> A_IWL<21833> A_IWL<21832> A_IWL<21831> A_IWL<21830> A_IWL<21829> A_IWL<21828> A_IWL<21827> A_IWL<21826> A_IWL<21825> A_IWL<21824> A_IWL<21823> A_IWL<21822> A_IWL<21821> A_IWL<21820> A_IWL<21819> A_IWL<21818> A_IWL<21817> A_IWL<21816> A_IWL<21815> A_IWL<21814> A_IWL<21813> A_IWL<21812> A_IWL<21811> A_IWL<21810> A_IWL<21809> A_IWL<21808> A_IWL<21807> A_IWL<21806> A_IWL<21805> A_IWL<21804> A_IWL<21803> A_IWL<21802> A_IWL<21801> A_IWL<21800> A_IWL<21799> A_IWL<21798> A_IWL<21797> A_IWL<21796> A_IWL<21795> A_IWL<21794> A_IWL<21793> A_IWL<21792> A_IWL<21791> A_IWL<21790> A_IWL<21789> A_IWL<21788> A_IWL<21787> A_IWL<21786> A_IWL<21785> A_IWL<21784> A_IWL<21783> A_IWL<21782> A_IWL<21781> A_IWL<21780> A_IWL<21779> A_IWL<21778> A_IWL<21777> A_IWL<21776> A_IWL<21775> A_IWL<21774> A_IWL<21773> A_IWL<21772> A_IWL<21771> A_IWL<21770> A_IWL<21769> A_IWL<21768> A_IWL<21767> A_IWL<21766> A_IWL<21765> A_IWL<21764> A_IWL<21763> A_IWL<21762> A_IWL<21761> A_IWL<21760> A_IWL<21759> A_IWL<21758> A_IWL<21757> A_IWL<21756> A_IWL<21755> A_IWL<21754> A_IWL<21753> A_IWL<21752> A_IWL<21751> A_IWL<21750> A_IWL<21749> A_IWL<21748> A_IWL<21747> A_IWL<21746> A_IWL<21745> A_IWL<21744> A_IWL<21743> A_IWL<21742> A_IWL<21741> A_IWL<21740> A_IWL<21739> A_IWL<21738> A_IWL<21737> A_IWL<21736> A_IWL<21735> A_IWL<21734> A_IWL<21733> A_IWL<21732> A_IWL<21731> A_IWL<21730> A_IWL<21729> A_IWL<21728> A_IWL<21727> A_IWL<21726> A_IWL<21725> A_IWL<21724> A_IWL<21723> A_IWL<21722> A_IWL<21721> A_IWL<21720> A_IWL<21719> A_IWL<21718> A_IWL<21717> A_IWL<21716> A_IWL<21715> A_IWL<21714> A_IWL<21713> A_IWL<21712> A_IWL<21711> A_IWL<21710> A_IWL<21709> A_IWL<21708> A_IWL<21707> A_IWL<21706> A_IWL<21705> A_IWL<21704> A_IWL<21703> A_IWL<21702> A_IWL<21701> A_IWL<21700> A_IWL<21699> A_IWL<21698> A_IWL<21697> A_IWL<21696> A_IWL<21695> A_IWL<21694> A_IWL<21693> A_IWL<21692> A_IWL<21691> A_IWL<21690> A_IWL<21689> A_IWL<21688> A_IWL<21687> A_IWL<21686> A_IWL<21685> A_IWL<21684> A_IWL<21683> A_IWL<21682> A_IWL<21681> A_IWL<21680> A_IWL<21679> A_IWL<21678> A_IWL<21677> A_IWL<21676> A_IWL<21675> A_IWL<21674> A_IWL<21673> A_IWL<21672> A_IWL<21671> A_IWL<21670> A_IWL<21669> A_IWL<21668> A_IWL<21667> A_IWL<21666> A_IWL<21665> A_IWL<21664> A_IWL<21663> A_IWL<21662> A_IWL<21661> A_IWL<21660> A_IWL<21659> A_IWL<21658> A_IWL<21657> A_IWL<21656> A_IWL<21655> A_IWL<21654> A_IWL<21653> A_IWL<21652> A_IWL<21651> A_IWL<21650> A_IWL<21649> A_IWL<21648> A_IWL<21647> A_IWL<21646> A_IWL<21645> A_IWL<21644> A_IWL<21643> A_IWL<21642> A_IWL<21641> A_IWL<21640> A_IWL<21639> A_IWL<21638> A_IWL<21637> A_IWL<21636> A_IWL<21635> A_IWL<21634> A_IWL<21633> A_IWL<21632> A_IWL<21631> A_IWL<21630> A_IWL<21629> A_IWL<21628> A_IWL<21627> A_IWL<21626> A_IWL<21625> A_IWL<21624> A_IWL<21623> A_IWL<21622> A_IWL<21621> A_IWL<21620> A_IWL<21619> A_IWL<21618> A_IWL<21617> A_IWL<21616> A_IWL<21615> A_IWL<21614> A_IWL<21613> A_IWL<21612> A_IWL<21611> A_IWL<21610> A_IWL<21609> A_IWL<21608> A_IWL<21607> A_IWL<21606> A_IWL<21605> A_IWL<21604> A_IWL<21603> A_IWL<21602> A_IWL<21601> A_IWL<21600> A_IWL<21599> A_IWL<21598> A_IWL<21597> A_IWL<21596> A_IWL<21595> A_IWL<21594> A_IWL<21593> A_IWL<21592> A_IWL<21591> A_IWL<21590> A_IWL<21589> A_IWL<21588> A_IWL<21587> A_IWL<21586> A_IWL<21585> A_IWL<21584> A_IWL<21583> A_IWL<21582> A_IWL<21581> A_IWL<21580> A_IWL<21579> A_IWL<21578> A_IWL<21577> A_IWL<21576> A_IWL<21575> A_IWL<21574> A_IWL<21573> A_IWL<21572> A_IWL<21571> A_IWL<21570> A_IWL<21569> A_IWL<21568> A_IWL<21567> A_IWL<21566> A_IWL<21565> A_IWL<21564> A_IWL<21563> A_IWL<21562> A_IWL<21561> A_IWL<21560> A_IWL<21559> A_IWL<21558> A_IWL<21557> A_IWL<21556> A_IWL<21555> A_IWL<21554> A_IWL<21553> A_IWL<21552> A_IWL<21551> A_IWL<21550> A_IWL<21549> A_IWL<21548> A_IWL<21547> A_IWL<21546> A_IWL<21545> A_IWL<21544> A_IWL<21543> A_IWL<21542> A_IWL<21541> A_IWL<21540> A_IWL<21539> A_IWL<21538> A_IWL<21537> A_IWL<21536> A_IWL<21535> A_IWL<21534> A_IWL<21533> A_IWL<21532> A_IWL<21531> A_IWL<21530> A_IWL<21529> A_IWL<21528> A_IWL<21527> A_IWL<21526> A_IWL<21525> A_IWL<21524> A_IWL<21523> A_IWL<21522> A_IWL<21521> A_IWL<21520> A_IWL<21519> A_IWL<21518> A_IWL<21517> A_IWL<21516> A_IWL<21515> A_IWL<21514> A_IWL<21513> A_IWL<21512> A_IWL<21511> A_IWL<21510> A_IWL<21509> A_IWL<21508> A_IWL<21507> A_IWL<21506> A_IWL<21505> A_IWL<21504> VDD_CORE VSS / RM_IHPSG13_8192x32_c4_1P_COLUMN_pcell_0 +XCOL<41> A_BLC<83> A_BLC<82> A_BLC_TOP<83> A_BLC_TOP<82> A_BLT<83> A_BLT<82> A_BLT_TOP<83> A_BLT_TOP<82> A_IWL<20991> A_IWL<20990> A_IWL<20989> A_IWL<20988> A_IWL<20987> A_IWL<20986> A_IWL<20985> A_IWL<20984> A_IWL<20983> A_IWL<20982> A_IWL<20981> A_IWL<20980> A_IWL<20979> A_IWL<20978> A_IWL<20977> A_IWL<20976> A_IWL<20975> A_IWL<20974> A_IWL<20973> A_IWL<20972> A_IWL<20971> A_IWL<20970> A_IWL<20969> A_IWL<20968> A_IWL<20967> A_IWL<20966> A_IWL<20965> A_IWL<20964> A_IWL<20963> A_IWL<20962> A_IWL<20961> A_IWL<20960> A_IWL<20959> A_IWL<20958> A_IWL<20957> A_IWL<20956> A_IWL<20955> A_IWL<20954> A_IWL<20953> A_IWL<20952> A_IWL<20951> A_IWL<20950> A_IWL<20949> A_IWL<20948> A_IWL<20947> A_IWL<20946> A_IWL<20945> A_IWL<20944> A_IWL<20943> A_IWL<20942> A_IWL<20941> A_IWL<20940> A_IWL<20939> A_IWL<20938> A_IWL<20937> A_IWL<20936> A_IWL<20935> A_IWL<20934> A_IWL<20933> A_IWL<20932> A_IWL<20931> A_IWL<20930> A_IWL<20929> A_IWL<20928> A_IWL<20927> A_IWL<20926> A_IWL<20925> A_IWL<20924> A_IWL<20923> A_IWL<20922> A_IWL<20921> A_IWL<20920> A_IWL<20919> A_IWL<20918> A_IWL<20917> A_IWL<20916> A_IWL<20915> A_IWL<20914> A_IWL<20913> A_IWL<20912> A_IWL<20911> A_IWL<20910> A_IWL<20909> A_IWL<20908> A_IWL<20907> A_IWL<20906> A_IWL<20905> A_IWL<20904> A_IWL<20903> A_IWL<20902> A_IWL<20901> A_IWL<20900> A_IWL<20899> A_IWL<20898> A_IWL<20897> A_IWL<20896> A_IWL<20895> A_IWL<20894> A_IWL<20893> A_IWL<20892> A_IWL<20891> A_IWL<20890> A_IWL<20889> A_IWL<20888> A_IWL<20887> A_IWL<20886> A_IWL<20885> A_IWL<20884> A_IWL<20883> A_IWL<20882> A_IWL<20881> A_IWL<20880> A_IWL<20879> A_IWL<20878> A_IWL<20877> A_IWL<20876> A_IWL<20875> A_IWL<20874> A_IWL<20873> A_IWL<20872> A_IWL<20871> A_IWL<20870> A_IWL<20869> A_IWL<20868> A_IWL<20867> A_IWL<20866> A_IWL<20865> A_IWL<20864> A_IWL<20863> A_IWL<20862> A_IWL<20861> A_IWL<20860> A_IWL<20859> A_IWL<20858> A_IWL<20857> A_IWL<20856> A_IWL<20855> A_IWL<20854> A_IWL<20853> A_IWL<20852> A_IWL<20851> A_IWL<20850> A_IWL<20849> A_IWL<20848> A_IWL<20847> A_IWL<20846> A_IWL<20845> A_IWL<20844> A_IWL<20843> A_IWL<20842> A_IWL<20841> A_IWL<20840> A_IWL<20839> A_IWL<20838> A_IWL<20837> A_IWL<20836> A_IWL<20835> A_IWL<20834> A_IWL<20833> A_IWL<20832> A_IWL<20831> A_IWL<20830> A_IWL<20829> A_IWL<20828> A_IWL<20827> A_IWL<20826> A_IWL<20825> A_IWL<20824> A_IWL<20823> A_IWL<20822> A_IWL<20821> A_IWL<20820> A_IWL<20819> A_IWL<20818> A_IWL<20817> A_IWL<20816> A_IWL<20815> A_IWL<20814> A_IWL<20813> A_IWL<20812> A_IWL<20811> A_IWL<20810> A_IWL<20809> A_IWL<20808> A_IWL<20807> A_IWL<20806> A_IWL<20805> A_IWL<20804> A_IWL<20803> A_IWL<20802> A_IWL<20801> A_IWL<20800> A_IWL<20799> A_IWL<20798> A_IWL<20797> A_IWL<20796> A_IWL<20795> A_IWL<20794> A_IWL<20793> A_IWL<20792> A_IWL<20791> A_IWL<20790> A_IWL<20789> A_IWL<20788> A_IWL<20787> A_IWL<20786> A_IWL<20785> A_IWL<20784> A_IWL<20783> A_IWL<20782> A_IWL<20781> A_IWL<20780> A_IWL<20779> A_IWL<20778> A_IWL<20777> A_IWL<20776> A_IWL<20775> A_IWL<20774> A_IWL<20773> A_IWL<20772> A_IWL<20771> A_IWL<20770> A_IWL<20769> A_IWL<20768> A_IWL<20767> A_IWL<20766> A_IWL<20765> A_IWL<20764> A_IWL<20763> A_IWL<20762> A_IWL<20761> A_IWL<20760> A_IWL<20759> A_IWL<20758> A_IWL<20757> A_IWL<20756> A_IWL<20755> A_IWL<20754> A_IWL<20753> A_IWL<20752> A_IWL<20751> A_IWL<20750> A_IWL<20749> A_IWL<20748> A_IWL<20747> A_IWL<20746> A_IWL<20745> A_IWL<20744> A_IWL<20743> A_IWL<20742> A_IWL<20741> A_IWL<20740> A_IWL<20739> A_IWL<20738> A_IWL<20737> A_IWL<20736> A_IWL<20735> A_IWL<20734> A_IWL<20733> A_IWL<20732> A_IWL<20731> A_IWL<20730> A_IWL<20729> A_IWL<20728> A_IWL<20727> A_IWL<20726> A_IWL<20725> A_IWL<20724> A_IWL<20723> A_IWL<20722> A_IWL<20721> A_IWL<20720> A_IWL<20719> A_IWL<20718> A_IWL<20717> A_IWL<20716> A_IWL<20715> A_IWL<20714> A_IWL<20713> A_IWL<20712> A_IWL<20711> A_IWL<20710> A_IWL<20709> A_IWL<20708> A_IWL<20707> A_IWL<20706> A_IWL<20705> A_IWL<20704> A_IWL<20703> A_IWL<20702> A_IWL<20701> A_IWL<20700> A_IWL<20699> A_IWL<20698> A_IWL<20697> A_IWL<20696> A_IWL<20695> A_IWL<20694> A_IWL<20693> A_IWL<20692> A_IWL<20691> A_IWL<20690> A_IWL<20689> A_IWL<20688> A_IWL<20687> A_IWL<20686> A_IWL<20685> A_IWL<20684> A_IWL<20683> A_IWL<20682> A_IWL<20681> A_IWL<20680> A_IWL<20679> A_IWL<20678> A_IWL<20677> A_IWL<20676> A_IWL<20675> A_IWL<20674> A_IWL<20673> A_IWL<20672> A_IWL<20671> A_IWL<20670> A_IWL<20669> A_IWL<20668> A_IWL<20667> A_IWL<20666> A_IWL<20665> A_IWL<20664> A_IWL<20663> A_IWL<20662> A_IWL<20661> A_IWL<20660> A_IWL<20659> A_IWL<20658> A_IWL<20657> A_IWL<20656> A_IWL<20655> A_IWL<20654> A_IWL<20653> A_IWL<20652> A_IWL<20651> A_IWL<20650> A_IWL<20649> A_IWL<20648> A_IWL<20647> A_IWL<20646> A_IWL<20645> A_IWL<20644> A_IWL<20643> A_IWL<20642> A_IWL<20641> A_IWL<20640> A_IWL<20639> A_IWL<20638> A_IWL<20637> A_IWL<20636> A_IWL<20635> A_IWL<20634> A_IWL<20633> A_IWL<20632> A_IWL<20631> A_IWL<20630> A_IWL<20629> A_IWL<20628> A_IWL<20627> A_IWL<20626> A_IWL<20625> A_IWL<20624> A_IWL<20623> A_IWL<20622> A_IWL<20621> A_IWL<20620> A_IWL<20619> A_IWL<20618> A_IWL<20617> A_IWL<20616> A_IWL<20615> A_IWL<20614> A_IWL<20613> A_IWL<20612> A_IWL<20611> A_IWL<20610> A_IWL<20609> A_IWL<20608> A_IWL<20607> A_IWL<20606> A_IWL<20605> A_IWL<20604> A_IWL<20603> A_IWL<20602> A_IWL<20601> A_IWL<20600> A_IWL<20599> A_IWL<20598> A_IWL<20597> A_IWL<20596> A_IWL<20595> A_IWL<20594> A_IWL<20593> A_IWL<20592> A_IWL<20591> A_IWL<20590> A_IWL<20589> A_IWL<20588> A_IWL<20587> A_IWL<20586> A_IWL<20585> A_IWL<20584> A_IWL<20583> A_IWL<20582> A_IWL<20581> A_IWL<20580> A_IWL<20579> A_IWL<20578> A_IWL<20577> A_IWL<20576> A_IWL<20575> A_IWL<20574> A_IWL<20573> A_IWL<20572> A_IWL<20571> A_IWL<20570> A_IWL<20569> A_IWL<20568> A_IWL<20567> A_IWL<20566> A_IWL<20565> A_IWL<20564> A_IWL<20563> A_IWL<20562> A_IWL<20561> A_IWL<20560> A_IWL<20559> A_IWL<20558> A_IWL<20557> A_IWL<20556> A_IWL<20555> A_IWL<20554> A_IWL<20553> A_IWL<20552> A_IWL<20551> A_IWL<20550> A_IWL<20549> A_IWL<20548> A_IWL<20547> A_IWL<20546> A_IWL<20545> A_IWL<20544> A_IWL<20543> A_IWL<20542> A_IWL<20541> A_IWL<20540> A_IWL<20539> A_IWL<20538> A_IWL<20537> A_IWL<20536> A_IWL<20535> A_IWL<20534> A_IWL<20533> A_IWL<20532> A_IWL<20531> A_IWL<20530> A_IWL<20529> A_IWL<20528> A_IWL<20527> A_IWL<20526> A_IWL<20525> A_IWL<20524> A_IWL<20523> A_IWL<20522> A_IWL<20521> A_IWL<20520> A_IWL<20519> A_IWL<20518> A_IWL<20517> A_IWL<20516> A_IWL<20515> A_IWL<20514> A_IWL<20513> A_IWL<20512> A_IWL<20511> A_IWL<20510> A_IWL<20509> A_IWL<20508> A_IWL<20507> A_IWL<20506> A_IWL<20505> A_IWL<20504> A_IWL<20503> A_IWL<20502> A_IWL<20501> A_IWL<20500> A_IWL<20499> A_IWL<20498> A_IWL<20497> A_IWL<20496> A_IWL<20495> A_IWL<20494> A_IWL<20493> A_IWL<20492> A_IWL<20491> A_IWL<20490> A_IWL<20489> A_IWL<20488> A_IWL<20487> A_IWL<20486> A_IWL<20485> A_IWL<20484> A_IWL<20483> A_IWL<20482> A_IWL<20481> A_IWL<20480> A_IWL<21503> A_IWL<21502> A_IWL<21501> A_IWL<21500> A_IWL<21499> A_IWL<21498> A_IWL<21497> A_IWL<21496> A_IWL<21495> A_IWL<21494> A_IWL<21493> A_IWL<21492> A_IWL<21491> A_IWL<21490> A_IWL<21489> A_IWL<21488> A_IWL<21487> A_IWL<21486> A_IWL<21485> A_IWL<21484> A_IWL<21483> A_IWL<21482> A_IWL<21481> A_IWL<21480> A_IWL<21479> A_IWL<21478> A_IWL<21477> A_IWL<21476> A_IWL<21475> A_IWL<21474> A_IWL<21473> A_IWL<21472> A_IWL<21471> A_IWL<21470> A_IWL<21469> A_IWL<21468> A_IWL<21467> A_IWL<21466> A_IWL<21465> A_IWL<21464> A_IWL<21463> A_IWL<21462> A_IWL<21461> A_IWL<21460> A_IWL<21459> A_IWL<21458> A_IWL<21457> A_IWL<21456> A_IWL<21455> A_IWL<21454> A_IWL<21453> A_IWL<21452> A_IWL<21451> A_IWL<21450> A_IWL<21449> A_IWL<21448> A_IWL<21447> A_IWL<21446> A_IWL<21445> A_IWL<21444> A_IWL<21443> A_IWL<21442> A_IWL<21441> A_IWL<21440> A_IWL<21439> A_IWL<21438> A_IWL<21437> A_IWL<21436> A_IWL<21435> A_IWL<21434> A_IWL<21433> A_IWL<21432> A_IWL<21431> A_IWL<21430> A_IWL<21429> A_IWL<21428> A_IWL<21427> A_IWL<21426> A_IWL<21425> A_IWL<21424> A_IWL<21423> A_IWL<21422> A_IWL<21421> A_IWL<21420> A_IWL<21419> A_IWL<21418> A_IWL<21417> A_IWL<21416> A_IWL<21415> A_IWL<21414> A_IWL<21413> A_IWL<21412> A_IWL<21411> A_IWL<21410> A_IWL<21409> A_IWL<21408> A_IWL<21407> A_IWL<21406> A_IWL<21405> A_IWL<21404> A_IWL<21403> A_IWL<21402> A_IWL<21401> A_IWL<21400> A_IWL<21399> A_IWL<21398> A_IWL<21397> A_IWL<21396> A_IWL<21395> A_IWL<21394> A_IWL<21393> A_IWL<21392> A_IWL<21391> A_IWL<21390> A_IWL<21389> A_IWL<21388> A_IWL<21387> A_IWL<21386> A_IWL<21385> A_IWL<21384> A_IWL<21383> A_IWL<21382> A_IWL<21381> A_IWL<21380> A_IWL<21379> A_IWL<21378> A_IWL<21377> A_IWL<21376> A_IWL<21375> A_IWL<21374> A_IWL<21373> A_IWL<21372> A_IWL<21371> A_IWL<21370> A_IWL<21369> A_IWL<21368> A_IWL<21367> A_IWL<21366> A_IWL<21365> A_IWL<21364> A_IWL<21363> A_IWL<21362> A_IWL<21361> A_IWL<21360> A_IWL<21359> A_IWL<21358> A_IWL<21357> A_IWL<21356> A_IWL<21355> A_IWL<21354> A_IWL<21353> A_IWL<21352> A_IWL<21351> A_IWL<21350> A_IWL<21349> A_IWL<21348> A_IWL<21347> A_IWL<21346> A_IWL<21345> A_IWL<21344> A_IWL<21343> A_IWL<21342> A_IWL<21341> A_IWL<21340> A_IWL<21339> A_IWL<21338> A_IWL<21337> A_IWL<21336> A_IWL<21335> A_IWL<21334> A_IWL<21333> A_IWL<21332> A_IWL<21331> A_IWL<21330> A_IWL<21329> A_IWL<21328> A_IWL<21327> A_IWL<21326> A_IWL<21325> A_IWL<21324> A_IWL<21323> A_IWL<21322> A_IWL<21321> A_IWL<21320> A_IWL<21319> A_IWL<21318> A_IWL<21317> A_IWL<21316> A_IWL<21315> A_IWL<21314> A_IWL<21313> A_IWL<21312> A_IWL<21311> A_IWL<21310> A_IWL<21309> A_IWL<21308> A_IWL<21307> A_IWL<21306> A_IWL<21305> A_IWL<21304> A_IWL<21303> A_IWL<21302> A_IWL<21301> A_IWL<21300> A_IWL<21299> A_IWL<21298> A_IWL<21297> A_IWL<21296> A_IWL<21295> A_IWL<21294> A_IWL<21293> A_IWL<21292> A_IWL<21291> A_IWL<21290> A_IWL<21289> A_IWL<21288> A_IWL<21287> A_IWL<21286> A_IWL<21285> A_IWL<21284> A_IWL<21283> A_IWL<21282> A_IWL<21281> A_IWL<21280> A_IWL<21279> A_IWL<21278> A_IWL<21277> A_IWL<21276> A_IWL<21275> A_IWL<21274> A_IWL<21273> A_IWL<21272> A_IWL<21271> A_IWL<21270> A_IWL<21269> A_IWL<21268> A_IWL<21267> A_IWL<21266> A_IWL<21265> A_IWL<21264> A_IWL<21263> A_IWL<21262> A_IWL<21261> A_IWL<21260> A_IWL<21259> A_IWL<21258> A_IWL<21257> A_IWL<21256> A_IWL<21255> A_IWL<21254> A_IWL<21253> A_IWL<21252> A_IWL<21251> A_IWL<21250> A_IWL<21249> A_IWL<21248> A_IWL<21247> A_IWL<21246> A_IWL<21245> A_IWL<21244> A_IWL<21243> A_IWL<21242> A_IWL<21241> A_IWL<21240> A_IWL<21239> A_IWL<21238> A_IWL<21237> A_IWL<21236> A_IWL<21235> A_IWL<21234> A_IWL<21233> A_IWL<21232> A_IWL<21231> A_IWL<21230> A_IWL<21229> A_IWL<21228> A_IWL<21227> A_IWL<21226> A_IWL<21225> A_IWL<21224> A_IWL<21223> A_IWL<21222> A_IWL<21221> A_IWL<21220> A_IWL<21219> A_IWL<21218> A_IWL<21217> A_IWL<21216> A_IWL<21215> A_IWL<21214> A_IWL<21213> A_IWL<21212> A_IWL<21211> A_IWL<21210> A_IWL<21209> A_IWL<21208> A_IWL<21207> A_IWL<21206> A_IWL<21205> A_IWL<21204> A_IWL<21203> A_IWL<21202> A_IWL<21201> A_IWL<21200> A_IWL<21199> A_IWL<21198> A_IWL<21197> A_IWL<21196> A_IWL<21195> A_IWL<21194> A_IWL<21193> A_IWL<21192> A_IWL<21191> A_IWL<21190> A_IWL<21189> A_IWL<21188> A_IWL<21187> A_IWL<21186> A_IWL<21185> A_IWL<21184> A_IWL<21183> A_IWL<21182> A_IWL<21181> A_IWL<21180> A_IWL<21179> A_IWL<21178> A_IWL<21177> A_IWL<21176> A_IWL<21175> A_IWL<21174> A_IWL<21173> A_IWL<21172> A_IWL<21171> A_IWL<21170> A_IWL<21169> A_IWL<21168> A_IWL<21167> A_IWL<21166> A_IWL<21165> A_IWL<21164> A_IWL<21163> A_IWL<21162> A_IWL<21161> A_IWL<21160> A_IWL<21159> A_IWL<21158> A_IWL<21157> A_IWL<21156> A_IWL<21155> A_IWL<21154> A_IWL<21153> A_IWL<21152> A_IWL<21151> A_IWL<21150> A_IWL<21149> A_IWL<21148> A_IWL<21147> A_IWL<21146> A_IWL<21145> A_IWL<21144> A_IWL<21143> A_IWL<21142> A_IWL<21141> A_IWL<21140> A_IWL<21139> A_IWL<21138> A_IWL<21137> A_IWL<21136> A_IWL<21135> A_IWL<21134> A_IWL<21133> A_IWL<21132> A_IWL<21131> A_IWL<21130> A_IWL<21129> A_IWL<21128> A_IWL<21127> A_IWL<21126> A_IWL<21125> A_IWL<21124> A_IWL<21123> A_IWL<21122> A_IWL<21121> A_IWL<21120> A_IWL<21119> A_IWL<21118> A_IWL<21117> A_IWL<21116> A_IWL<21115> A_IWL<21114> A_IWL<21113> A_IWL<21112> A_IWL<21111> A_IWL<21110> A_IWL<21109> A_IWL<21108> A_IWL<21107> A_IWL<21106> A_IWL<21105> A_IWL<21104> A_IWL<21103> A_IWL<21102> A_IWL<21101> A_IWL<21100> A_IWL<21099> A_IWL<21098> A_IWL<21097> A_IWL<21096> A_IWL<21095> A_IWL<21094> A_IWL<21093> A_IWL<21092> A_IWL<21091> A_IWL<21090> A_IWL<21089> A_IWL<21088> A_IWL<21087> A_IWL<21086> A_IWL<21085> A_IWL<21084> A_IWL<21083> A_IWL<21082> A_IWL<21081> A_IWL<21080> A_IWL<21079> A_IWL<21078> A_IWL<21077> A_IWL<21076> A_IWL<21075> A_IWL<21074> A_IWL<21073> A_IWL<21072> A_IWL<21071> A_IWL<21070> A_IWL<21069> A_IWL<21068> A_IWL<21067> A_IWL<21066> A_IWL<21065> A_IWL<21064> A_IWL<21063> A_IWL<21062> A_IWL<21061> A_IWL<21060> A_IWL<21059> A_IWL<21058> A_IWL<21057> A_IWL<21056> A_IWL<21055> A_IWL<21054> A_IWL<21053> A_IWL<21052> A_IWL<21051> A_IWL<21050> A_IWL<21049> A_IWL<21048> A_IWL<21047> A_IWL<21046> A_IWL<21045> A_IWL<21044> A_IWL<21043> A_IWL<21042> A_IWL<21041> A_IWL<21040> A_IWL<21039> A_IWL<21038> A_IWL<21037> A_IWL<21036> A_IWL<21035> A_IWL<21034> A_IWL<21033> A_IWL<21032> A_IWL<21031> A_IWL<21030> A_IWL<21029> A_IWL<21028> A_IWL<21027> A_IWL<21026> A_IWL<21025> A_IWL<21024> A_IWL<21023> A_IWL<21022> A_IWL<21021> A_IWL<21020> A_IWL<21019> A_IWL<21018> A_IWL<21017> A_IWL<21016> A_IWL<21015> A_IWL<21014> A_IWL<21013> A_IWL<21012> A_IWL<21011> A_IWL<21010> A_IWL<21009> A_IWL<21008> A_IWL<21007> A_IWL<21006> A_IWL<21005> A_IWL<21004> A_IWL<21003> A_IWL<21002> A_IWL<21001> A_IWL<21000> A_IWL<20999> A_IWL<20998> A_IWL<20997> A_IWL<20996> A_IWL<20995> A_IWL<20994> A_IWL<20993> A_IWL<20992> VDD_CORE VSS / RM_IHPSG13_8192x32_c4_1P_COLUMN_pcell_0 +XCOL<40> A_BLC<81> A_BLC<80> A_BLC_TOP<81> A_BLC_TOP<80> A_BLT<81> A_BLT<80> A_BLT_TOP<81> A_BLT_TOP<80> A_IWL<20479> A_IWL<20478> A_IWL<20477> A_IWL<20476> A_IWL<20475> A_IWL<20474> A_IWL<20473> A_IWL<20472> A_IWL<20471> A_IWL<20470> A_IWL<20469> A_IWL<20468> A_IWL<20467> A_IWL<20466> A_IWL<20465> A_IWL<20464> A_IWL<20463> A_IWL<20462> A_IWL<20461> A_IWL<20460> A_IWL<20459> A_IWL<20458> A_IWL<20457> A_IWL<20456> A_IWL<20455> A_IWL<20454> A_IWL<20453> A_IWL<20452> A_IWL<20451> A_IWL<20450> A_IWL<20449> A_IWL<20448> A_IWL<20447> A_IWL<20446> A_IWL<20445> A_IWL<20444> A_IWL<20443> A_IWL<20442> A_IWL<20441> A_IWL<20440> A_IWL<20439> A_IWL<20438> A_IWL<20437> A_IWL<20436> A_IWL<20435> A_IWL<20434> A_IWL<20433> A_IWL<20432> A_IWL<20431> A_IWL<20430> A_IWL<20429> A_IWL<20428> A_IWL<20427> A_IWL<20426> A_IWL<20425> A_IWL<20424> A_IWL<20423> A_IWL<20422> A_IWL<20421> A_IWL<20420> A_IWL<20419> A_IWL<20418> A_IWL<20417> A_IWL<20416> A_IWL<20415> A_IWL<20414> A_IWL<20413> A_IWL<20412> A_IWL<20411> A_IWL<20410> A_IWL<20409> A_IWL<20408> A_IWL<20407> A_IWL<20406> A_IWL<20405> A_IWL<20404> A_IWL<20403> A_IWL<20402> A_IWL<20401> A_IWL<20400> A_IWL<20399> A_IWL<20398> A_IWL<20397> A_IWL<20396> A_IWL<20395> A_IWL<20394> A_IWL<20393> A_IWL<20392> A_IWL<20391> A_IWL<20390> A_IWL<20389> A_IWL<20388> A_IWL<20387> A_IWL<20386> A_IWL<20385> A_IWL<20384> A_IWL<20383> A_IWL<20382> A_IWL<20381> A_IWL<20380> A_IWL<20379> A_IWL<20378> A_IWL<20377> A_IWL<20376> A_IWL<20375> A_IWL<20374> A_IWL<20373> A_IWL<20372> A_IWL<20371> A_IWL<20370> A_IWL<20369> A_IWL<20368> A_IWL<20367> A_IWL<20366> A_IWL<20365> A_IWL<20364> A_IWL<20363> A_IWL<20362> A_IWL<20361> A_IWL<20360> A_IWL<20359> A_IWL<20358> A_IWL<20357> A_IWL<20356> A_IWL<20355> A_IWL<20354> A_IWL<20353> A_IWL<20352> A_IWL<20351> A_IWL<20350> A_IWL<20349> A_IWL<20348> A_IWL<20347> A_IWL<20346> A_IWL<20345> A_IWL<20344> A_IWL<20343> A_IWL<20342> A_IWL<20341> A_IWL<20340> A_IWL<20339> A_IWL<20338> A_IWL<20337> A_IWL<20336> A_IWL<20335> A_IWL<20334> A_IWL<20333> A_IWL<20332> A_IWL<20331> A_IWL<20330> A_IWL<20329> A_IWL<20328> A_IWL<20327> A_IWL<20326> A_IWL<20325> A_IWL<20324> A_IWL<20323> A_IWL<20322> A_IWL<20321> A_IWL<20320> A_IWL<20319> A_IWL<20318> A_IWL<20317> A_IWL<20316> A_IWL<20315> A_IWL<20314> A_IWL<20313> A_IWL<20312> A_IWL<20311> A_IWL<20310> A_IWL<20309> A_IWL<20308> A_IWL<20307> A_IWL<20306> A_IWL<20305> A_IWL<20304> A_IWL<20303> A_IWL<20302> A_IWL<20301> A_IWL<20300> A_IWL<20299> A_IWL<20298> A_IWL<20297> A_IWL<20296> A_IWL<20295> A_IWL<20294> A_IWL<20293> A_IWL<20292> A_IWL<20291> A_IWL<20290> A_IWL<20289> A_IWL<20288> A_IWL<20287> A_IWL<20286> A_IWL<20285> A_IWL<20284> A_IWL<20283> A_IWL<20282> A_IWL<20281> A_IWL<20280> A_IWL<20279> A_IWL<20278> A_IWL<20277> A_IWL<20276> A_IWL<20275> A_IWL<20274> A_IWL<20273> A_IWL<20272> A_IWL<20271> A_IWL<20270> A_IWL<20269> A_IWL<20268> A_IWL<20267> A_IWL<20266> A_IWL<20265> A_IWL<20264> A_IWL<20263> A_IWL<20262> A_IWL<20261> A_IWL<20260> A_IWL<20259> A_IWL<20258> A_IWL<20257> A_IWL<20256> A_IWL<20255> A_IWL<20254> A_IWL<20253> A_IWL<20252> A_IWL<20251> A_IWL<20250> A_IWL<20249> A_IWL<20248> A_IWL<20247> A_IWL<20246> A_IWL<20245> A_IWL<20244> A_IWL<20243> A_IWL<20242> A_IWL<20241> A_IWL<20240> A_IWL<20239> A_IWL<20238> A_IWL<20237> A_IWL<20236> A_IWL<20235> A_IWL<20234> A_IWL<20233> A_IWL<20232> A_IWL<20231> A_IWL<20230> A_IWL<20229> A_IWL<20228> A_IWL<20227> A_IWL<20226> A_IWL<20225> A_IWL<20224> A_IWL<20223> A_IWL<20222> A_IWL<20221> A_IWL<20220> A_IWL<20219> A_IWL<20218> A_IWL<20217> A_IWL<20216> A_IWL<20215> A_IWL<20214> A_IWL<20213> A_IWL<20212> A_IWL<20211> A_IWL<20210> A_IWL<20209> A_IWL<20208> A_IWL<20207> A_IWL<20206> A_IWL<20205> A_IWL<20204> A_IWL<20203> A_IWL<20202> A_IWL<20201> A_IWL<20200> A_IWL<20199> A_IWL<20198> A_IWL<20197> A_IWL<20196> A_IWL<20195> A_IWL<20194> A_IWL<20193> A_IWL<20192> A_IWL<20191> A_IWL<20190> A_IWL<20189> A_IWL<20188> A_IWL<20187> A_IWL<20186> A_IWL<20185> A_IWL<20184> A_IWL<20183> A_IWL<20182> A_IWL<20181> A_IWL<20180> A_IWL<20179> A_IWL<20178> A_IWL<20177> A_IWL<20176> A_IWL<20175> A_IWL<20174> A_IWL<20173> A_IWL<20172> A_IWL<20171> A_IWL<20170> A_IWL<20169> A_IWL<20168> A_IWL<20167> A_IWL<20166> A_IWL<20165> A_IWL<20164> A_IWL<20163> A_IWL<20162> A_IWL<20161> A_IWL<20160> A_IWL<20159> A_IWL<20158> A_IWL<20157> A_IWL<20156> A_IWL<20155> A_IWL<20154> A_IWL<20153> A_IWL<20152> A_IWL<20151> A_IWL<20150> A_IWL<20149> A_IWL<20148> A_IWL<20147> A_IWL<20146> A_IWL<20145> A_IWL<20144> A_IWL<20143> A_IWL<20142> A_IWL<20141> A_IWL<20140> A_IWL<20139> A_IWL<20138> A_IWL<20137> A_IWL<20136> A_IWL<20135> A_IWL<20134> A_IWL<20133> A_IWL<20132> A_IWL<20131> A_IWL<20130> A_IWL<20129> A_IWL<20128> A_IWL<20127> A_IWL<20126> A_IWL<20125> A_IWL<20124> A_IWL<20123> A_IWL<20122> A_IWL<20121> A_IWL<20120> A_IWL<20119> A_IWL<20118> A_IWL<20117> A_IWL<20116> A_IWL<20115> A_IWL<20114> A_IWL<20113> A_IWL<20112> A_IWL<20111> A_IWL<20110> A_IWL<20109> A_IWL<20108> A_IWL<20107> A_IWL<20106> A_IWL<20105> A_IWL<20104> A_IWL<20103> A_IWL<20102> A_IWL<20101> A_IWL<20100> A_IWL<20099> A_IWL<20098> A_IWL<20097> A_IWL<20096> A_IWL<20095> A_IWL<20094> A_IWL<20093> A_IWL<20092> A_IWL<20091> A_IWL<20090> A_IWL<20089> A_IWL<20088> A_IWL<20087> A_IWL<20086> A_IWL<20085> A_IWL<20084> A_IWL<20083> A_IWL<20082> A_IWL<20081> A_IWL<20080> A_IWL<20079> A_IWL<20078> A_IWL<20077> A_IWL<20076> A_IWL<20075> A_IWL<20074> A_IWL<20073> A_IWL<20072> A_IWL<20071> A_IWL<20070> A_IWL<20069> A_IWL<20068> A_IWL<20067> A_IWL<20066> A_IWL<20065> A_IWL<20064> A_IWL<20063> A_IWL<20062> A_IWL<20061> A_IWL<20060> A_IWL<20059> A_IWL<20058> A_IWL<20057> A_IWL<20056> A_IWL<20055> A_IWL<20054> A_IWL<20053> A_IWL<20052> A_IWL<20051> A_IWL<20050> A_IWL<20049> A_IWL<20048> A_IWL<20047> A_IWL<20046> A_IWL<20045> A_IWL<20044> A_IWL<20043> A_IWL<20042> A_IWL<20041> A_IWL<20040> A_IWL<20039> A_IWL<20038> A_IWL<20037> A_IWL<20036> A_IWL<20035> A_IWL<20034> A_IWL<20033> A_IWL<20032> A_IWL<20031> A_IWL<20030> A_IWL<20029> A_IWL<20028> A_IWL<20027> A_IWL<20026> A_IWL<20025> A_IWL<20024> A_IWL<20023> A_IWL<20022> A_IWL<20021> A_IWL<20020> A_IWL<20019> A_IWL<20018> A_IWL<20017> A_IWL<20016> A_IWL<20015> A_IWL<20014> A_IWL<20013> A_IWL<20012> A_IWL<20011> A_IWL<20010> A_IWL<20009> A_IWL<20008> A_IWL<20007> A_IWL<20006> A_IWL<20005> A_IWL<20004> A_IWL<20003> A_IWL<20002> A_IWL<20001> A_IWL<20000> A_IWL<19999> A_IWL<19998> A_IWL<19997> A_IWL<19996> A_IWL<19995> A_IWL<19994> A_IWL<19993> A_IWL<19992> A_IWL<19991> A_IWL<19990> A_IWL<19989> A_IWL<19988> A_IWL<19987> A_IWL<19986> A_IWL<19985> A_IWL<19984> A_IWL<19983> A_IWL<19982> A_IWL<19981> A_IWL<19980> A_IWL<19979> A_IWL<19978> A_IWL<19977> A_IWL<19976> A_IWL<19975> A_IWL<19974> A_IWL<19973> A_IWL<19972> A_IWL<19971> A_IWL<19970> A_IWL<19969> A_IWL<19968> A_IWL<20991> A_IWL<20990> A_IWL<20989> A_IWL<20988> A_IWL<20987> A_IWL<20986> A_IWL<20985> A_IWL<20984> A_IWL<20983> A_IWL<20982> A_IWL<20981> A_IWL<20980> A_IWL<20979> A_IWL<20978> A_IWL<20977> A_IWL<20976> A_IWL<20975> A_IWL<20974> A_IWL<20973> A_IWL<20972> A_IWL<20971> A_IWL<20970> A_IWL<20969> A_IWL<20968> A_IWL<20967> A_IWL<20966> A_IWL<20965> A_IWL<20964> A_IWL<20963> A_IWL<20962> A_IWL<20961> A_IWL<20960> A_IWL<20959> A_IWL<20958> A_IWL<20957> A_IWL<20956> A_IWL<20955> A_IWL<20954> A_IWL<20953> A_IWL<20952> A_IWL<20951> A_IWL<20950> A_IWL<20949> A_IWL<20948> A_IWL<20947> A_IWL<20946> A_IWL<20945> A_IWL<20944> A_IWL<20943> A_IWL<20942> A_IWL<20941> A_IWL<20940> A_IWL<20939> A_IWL<20938> A_IWL<20937> A_IWL<20936> A_IWL<20935> A_IWL<20934> A_IWL<20933> A_IWL<20932> A_IWL<20931> A_IWL<20930> A_IWL<20929> A_IWL<20928> A_IWL<20927> A_IWL<20926> A_IWL<20925> A_IWL<20924> A_IWL<20923> A_IWL<20922> A_IWL<20921> A_IWL<20920> A_IWL<20919> A_IWL<20918> A_IWL<20917> A_IWL<20916> A_IWL<20915> A_IWL<20914> A_IWL<20913> A_IWL<20912> A_IWL<20911> A_IWL<20910> A_IWL<20909> A_IWL<20908> A_IWL<20907> A_IWL<20906> A_IWL<20905> A_IWL<20904> A_IWL<20903> A_IWL<20902> A_IWL<20901> A_IWL<20900> A_IWL<20899> A_IWL<20898> A_IWL<20897> A_IWL<20896> A_IWL<20895> A_IWL<20894> A_IWL<20893> A_IWL<20892> A_IWL<20891> A_IWL<20890> A_IWL<20889> A_IWL<20888> A_IWL<20887> A_IWL<20886> A_IWL<20885> A_IWL<20884> A_IWL<20883> A_IWL<20882> A_IWL<20881> A_IWL<20880> A_IWL<20879> A_IWL<20878> A_IWL<20877> A_IWL<20876> A_IWL<20875> A_IWL<20874> A_IWL<20873> A_IWL<20872> A_IWL<20871> A_IWL<20870> A_IWL<20869> A_IWL<20868> A_IWL<20867> A_IWL<20866> A_IWL<20865> A_IWL<20864> A_IWL<20863> A_IWL<20862> A_IWL<20861> A_IWL<20860> A_IWL<20859> A_IWL<20858> A_IWL<20857> A_IWL<20856> A_IWL<20855> A_IWL<20854> A_IWL<20853> A_IWL<20852> A_IWL<20851> A_IWL<20850> A_IWL<20849> A_IWL<20848> A_IWL<20847> A_IWL<20846> A_IWL<20845> A_IWL<20844> A_IWL<20843> A_IWL<20842> A_IWL<20841> A_IWL<20840> A_IWL<20839> A_IWL<20838> A_IWL<20837> A_IWL<20836> A_IWL<20835> A_IWL<20834> A_IWL<20833> A_IWL<20832> A_IWL<20831> A_IWL<20830> A_IWL<20829> A_IWL<20828> A_IWL<20827> A_IWL<20826> A_IWL<20825> A_IWL<20824> A_IWL<20823> A_IWL<20822> A_IWL<20821> A_IWL<20820> A_IWL<20819> A_IWL<20818> A_IWL<20817> A_IWL<20816> A_IWL<20815> A_IWL<20814> A_IWL<20813> A_IWL<20812> A_IWL<20811> A_IWL<20810> A_IWL<20809> A_IWL<20808> A_IWL<20807> A_IWL<20806> A_IWL<20805> A_IWL<20804> A_IWL<20803> A_IWL<20802> A_IWL<20801> A_IWL<20800> A_IWL<20799> A_IWL<20798> A_IWL<20797> A_IWL<20796> A_IWL<20795> A_IWL<20794> A_IWL<20793> A_IWL<20792> A_IWL<20791> A_IWL<20790> A_IWL<20789> A_IWL<20788> A_IWL<20787> A_IWL<20786> A_IWL<20785> A_IWL<20784> A_IWL<20783> A_IWL<20782> A_IWL<20781> A_IWL<20780> A_IWL<20779> A_IWL<20778> A_IWL<20777> A_IWL<20776> A_IWL<20775> A_IWL<20774> A_IWL<20773> A_IWL<20772> A_IWL<20771> A_IWL<20770> A_IWL<20769> A_IWL<20768> A_IWL<20767> A_IWL<20766> A_IWL<20765> A_IWL<20764> A_IWL<20763> A_IWL<20762> A_IWL<20761> A_IWL<20760> A_IWL<20759> A_IWL<20758> A_IWL<20757> A_IWL<20756> A_IWL<20755> A_IWL<20754> A_IWL<20753> A_IWL<20752> A_IWL<20751> A_IWL<20750> A_IWL<20749> A_IWL<20748> A_IWL<20747> A_IWL<20746> A_IWL<20745> A_IWL<20744> A_IWL<20743> A_IWL<20742> A_IWL<20741> A_IWL<20740> A_IWL<20739> A_IWL<20738> A_IWL<20737> A_IWL<20736> A_IWL<20735> A_IWL<20734> A_IWL<20733> A_IWL<20732> A_IWL<20731> A_IWL<20730> A_IWL<20729> A_IWL<20728> A_IWL<20727> A_IWL<20726> A_IWL<20725> A_IWL<20724> A_IWL<20723> A_IWL<20722> A_IWL<20721> A_IWL<20720> A_IWL<20719> A_IWL<20718> A_IWL<20717> A_IWL<20716> A_IWL<20715> A_IWL<20714> A_IWL<20713> A_IWL<20712> A_IWL<20711> A_IWL<20710> A_IWL<20709> A_IWL<20708> A_IWL<20707> A_IWL<20706> A_IWL<20705> A_IWL<20704> A_IWL<20703> A_IWL<20702> A_IWL<20701> A_IWL<20700> A_IWL<20699> A_IWL<20698> A_IWL<20697> A_IWL<20696> A_IWL<20695> A_IWL<20694> A_IWL<20693> A_IWL<20692> A_IWL<20691> A_IWL<20690> A_IWL<20689> A_IWL<20688> A_IWL<20687> A_IWL<20686> A_IWL<20685> A_IWL<20684> A_IWL<20683> A_IWL<20682> A_IWL<20681> A_IWL<20680> A_IWL<20679> A_IWL<20678> A_IWL<20677> A_IWL<20676> A_IWL<20675> A_IWL<20674> A_IWL<20673> A_IWL<20672> A_IWL<20671> A_IWL<20670> A_IWL<20669> A_IWL<20668> A_IWL<20667> A_IWL<20666> A_IWL<20665> A_IWL<20664> A_IWL<20663> A_IWL<20662> A_IWL<20661> A_IWL<20660> A_IWL<20659> A_IWL<20658> A_IWL<20657> A_IWL<20656> A_IWL<20655> A_IWL<20654> A_IWL<20653> A_IWL<20652> A_IWL<20651> A_IWL<20650> A_IWL<20649> A_IWL<20648> A_IWL<20647> A_IWL<20646> A_IWL<20645> A_IWL<20644> A_IWL<20643> A_IWL<20642> A_IWL<20641> A_IWL<20640> A_IWL<20639> A_IWL<20638> A_IWL<20637> A_IWL<20636> A_IWL<20635> A_IWL<20634> A_IWL<20633> A_IWL<20632> A_IWL<20631> A_IWL<20630> A_IWL<20629> A_IWL<20628> A_IWL<20627> A_IWL<20626> A_IWL<20625> A_IWL<20624> A_IWL<20623> A_IWL<20622> A_IWL<20621> A_IWL<20620> A_IWL<20619> A_IWL<20618> A_IWL<20617> A_IWL<20616> A_IWL<20615> A_IWL<20614> A_IWL<20613> A_IWL<20612> A_IWL<20611> A_IWL<20610> A_IWL<20609> A_IWL<20608> A_IWL<20607> A_IWL<20606> A_IWL<20605> A_IWL<20604> A_IWL<20603> A_IWL<20602> A_IWL<20601> A_IWL<20600> A_IWL<20599> A_IWL<20598> A_IWL<20597> A_IWL<20596> A_IWL<20595> A_IWL<20594> A_IWL<20593> A_IWL<20592> A_IWL<20591> A_IWL<20590> A_IWL<20589> A_IWL<20588> A_IWL<20587> A_IWL<20586> A_IWL<20585> A_IWL<20584> A_IWL<20583> A_IWL<20582> A_IWL<20581> A_IWL<20580> A_IWL<20579> A_IWL<20578> A_IWL<20577> A_IWL<20576> A_IWL<20575> A_IWL<20574> A_IWL<20573> A_IWL<20572> A_IWL<20571> A_IWL<20570> A_IWL<20569> A_IWL<20568> A_IWL<20567> A_IWL<20566> A_IWL<20565> A_IWL<20564> A_IWL<20563> A_IWL<20562> A_IWL<20561> A_IWL<20560> A_IWL<20559> A_IWL<20558> A_IWL<20557> A_IWL<20556> A_IWL<20555> A_IWL<20554> A_IWL<20553> A_IWL<20552> A_IWL<20551> A_IWL<20550> A_IWL<20549> A_IWL<20548> A_IWL<20547> A_IWL<20546> A_IWL<20545> A_IWL<20544> A_IWL<20543> A_IWL<20542> A_IWL<20541> A_IWL<20540> A_IWL<20539> A_IWL<20538> A_IWL<20537> A_IWL<20536> A_IWL<20535> A_IWL<20534> A_IWL<20533> A_IWL<20532> A_IWL<20531> A_IWL<20530> A_IWL<20529> A_IWL<20528> A_IWL<20527> A_IWL<20526> A_IWL<20525> A_IWL<20524> A_IWL<20523> A_IWL<20522> A_IWL<20521> A_IWL<20520> A_IWL<20519> A_IWL<20518> A_IWL<20517> A_IWL<20516> A_IWL<20515> A_IWL<20514> A_IWL<20513> A_IWL<20512> A_IWL<20511> A_IWL<20510> A_IWL<20509> A_IWL<20508> A_IWL<20507> A_IWL<20506> A_IWL<20505> A_IWL<20504> A_IWL<20503> A_IWL<20502> A_IWL<20501> A_IWL<20500> A_IWL<20499> A_IWL<20498> A_IWL<20497> A_IWL<20496> A_IWL<20495> A_IWL<20494> A_IWL<20493> A_IWL<20492> A_IWL<20491> A_IWL<20490> A_IWL<20489> A_IWL<20488> A_IWL<20487> A_IWL<20486> A_IWL<20485> A_IWL<20484> A_IWL<20483> A_IWL<20482> A_IWL<20481> A_IWL<20480> VDD_CORE VSS / RM_IHPSG13_8192x32_c4_1P_COLUMN_pcell_0 +XCOL<39> A_BLC<79> A_BLC<78> A_BLC_TOP<79> A_BLC_TOP<78> A_BLT<79> A_BLT<78> A_BLT_TOP<79> A_BLT_TOP<78> A_IWL<19967> A_IWL<19966> A_IWL<19965> A_IWL<19964> A_IWL<19963> A_IWL<19962> A_IWL<19961> A_IWL<19960> A_IWL<19959> A_IWL<19958> A_IWL<19957> A_IWL<19956> A_IWL<19955> A_IWL<19954> A_IWL<19953> A_IWL<19952> A_IWL<19951> A_IWL<19950> A_IWL<19949> A_IWL<19948> A_IWL<19947> A_IWL<19946> A_IWL<19945> A_IWL<19944> A_IWL<19943> A_IWL<19942> A_IWL<19941> A_IWL<19940> A_IWL<19939> A_IWL<19938> A_IWL<19937> A_IWL<19936> A_IWL<19935> A_IWL<19934> A_IWL<19933> A_IWL<19932> A_IWL<19931> A_IWL<19930> A_IWL<19929> A_IWL<19928> A_IWL<19927> A_IWL<19926> A_IWL<19925> A_IWL<19924> A_IWL<19923> A_IWL<19922> A_IWL<19921> A_IWL<19920> A_IWL<19919> A_IWL<19918> A_IWL<19917> A_IWL<19916> A_IWL<19915> A_IWL<19914> A_IWL<19913> A_IWL<19912> A_IWL<19911> A_IWL<19910> A_IWL<19909> A_IWL<19908> A_IWL<19907> A_IWL<19906> A_IWL<19905> A_IWL<19904> A_IWL<19903> A_IWL<19902> A_IWL<19901> A_IWL<19900> A_IWL<19899> A_IWL<19898> A_IWL<19897> A_IWL<19896> A_IWL<19895> A_IWL<19894> A_IWL<19893> A_IWL<19892> A_IWL<19891> A_IWL<19890> A_IWL<19889> A_IWL<19888> A_IWL<19887> A_IWL<19886> A_IWL<19885> A_IWL<19884> A_IWL<19883> A_IWL<19882> A_IWL<19881> A_IWL<19880> A_IWL<19879> A_IWL<19878> A_IWL<19877> A_IWL<19876> A_IWL<19875> A_IWL<19874> A_IWL<19873> A_IWL<19872> A_IWL<19871> A_IWL<19870> A_IWL<19869> A_IWL<19868> A_IWL<19867> A_IWL<19866> A_IWL<19865> A_IWL<19864> A_IWL<19863> A_IWL<19862> A_IWL<19861> A_IWL<19860> A_IWL<19859> A_IWL<19858> A_IWL<19857> A_IWL<19856> A_IWL<19855> A_IWL<19854> A_IWL<19853> A_IWL<19852> A_IWL<19851> A_IWL<19850> A_IWL<19849> A_IWL<19848> A_IWL<19847> A_IWL<19846> A_IWL<19845> A_IWL<19844> A_IWL<19843> A_IWL<19842> A_IWL<19841> A_IWL<19840> A_IWL<19839> A_IWL<19838> A_IWL<19837> A_IWL<19836> A_IWL<19835> A_IWL<19834> A_IWL<19833> A_IWL<19832> A_IWL<19831> A_IWL<19830> A_IWL<19829> A_IWL<19828> A_IWL<19827> A_IWL<19826> A_IWL<19825> A_IWL<19824> A_IWL<19823> A_IWL<19822> A_IWL<19821> A_IWL<19820> A_IWL<19819> A_IWL<19818> A_IWL<19817> A_IWL<19816> A_IWL<19815> A_IWL<19814> A_IWL<19813> A_IWL<19812> A_IWL<19811> A_IWL<19810> A_IWL<19809> A_IWL<19808> A_IWL<19807> A_IWL<19806> A_IWL<19805> A_IWL<19804> A_IWL<19803> A_IWL<19802> A_IWL<19801> A_IWL<19800> A_IWL<19799> A_IWL<19798> A_IWL<19797> A_IWL<19796> A_IWL<19795> A_IWL<19794> A_IWL<19793> A_IWL<19792> A_IWL<19791> A_IWL<19790> A_IWL<19789> A_IWL<19788> A_IWL<19787> A_IWL<19786> A_IWL<19785> A_IWL<19784> A_IWL<19783> A_IWL<19782> A_IWL<19781> A_IWL<19780> A_IWL<19779> A_IWL<19778> A_IWL<19777> A_IWL<19776> A_IWL<19775> A_IWL<19774> A_IWL<19773> A_IWL<19772> A_IWL<19771> A_IWL<19770> A_IWL<19769> A_IWL<19768> A_IWL<19767> A_IWL<19766> A_IWL<19765> A_IWL<19764> A_IWL<19763> A_IWL<19762> A_IWL<19761> A_IWL<19760> A_IWL<19759> A_IWL<19758> A_IWL<19757> A_IWL<19756> A_IWL<19755> A_IWL<19754> A_IWL<19753> A_IWL<19752> A_IWL<19751> A_IWL<19750> A_IWL<19749> A_IWL<19748> A_IWL<19747> A_IWL<19746> A_IWL<19745> A_IWL<19744> A_IWL<19743> A_IWL<19742> A_IWL<19741> A_IWL<19740> A_IWL<19739> A_IWL<19738> A_IWL<19737> A_IWL<19736> A_IWL<19735> A_IWL<19734> A_IWL<19733> A_IWL<19732> A_IWL<19731> A_IWL<19730> A_IWL<19729> A_IWL<19728> A_IWL<19727> A_IWL<19726> A_IWL<19725> A_IWL<19724> A_IWL<19723> A_IWL<19722> A_IWL<19721> A_IWL<19720> A_IWL<19719> A_IWL<19718> A_IWL<19717> A_IWL<19716> A_IWL<19715> A_IWL<19714> A_IWL<19713> A_IWL<19712> A_IWL<19711> A_IWL<19710> A_IWL<19709> A_IWL<19708> A_IWL<19707> A_IWL<19706> A_IWL<19705> A_IWL<19704> A_IWL<19703> A_IWL<19702> A_IWL<19701> A_IWL<19700> A_IWL<19699> A_IWL<19698> A_IWL<19697> A_IWL<19696> A_IWL<19695> A_IWL<19694> A_IWL<19693> A_IWL<19692> A_IWL<19691> A_IWL<19690> A_IWL<19689> A_IWL<19688> A_IWL<19687> A_IWL<19686> A_IWL<19685> A_IWL<19684> A_IWL<19683> A_IWL<19682> A_IWL<19681> A_IWL<19680> A_IWL<19679> A_IWL<19678> A_IWL<19677> A_IWL<19676> A_IWL<19675> A_IWL<19674> A_IWL<19673> A_IWL<19672> A_IWL<19671> A_IWL<19670> A_IWL<19669> A_IWL<19668> A_IWL<19667> A_IWL<19666> A_IWL<19665> A_IWL<19664> A_IWL<19663> A_IWL<19662> A_IWL<19661> A_IWL<19660> A_IWL<19659> A_IWL<19658> A_IWL<19657> A_IWL<19656> A_IWL<19655> A_IWL<19654> A_IWL<19653> A_IWL<19652> A_IWL<19651> A_IWL<19650> A_IWL<19649> A_IWL<19648> A_IWL<19647> A_IWL<19646> A_IWL<19645> A_IWL<19644> A_IWL<19643> A_IWL<19642> A_IWL<19641> A_IWL<19640> A_IWL<19639> A_IWL<19638> A_IWL<19637> A_IWL<19636> A_IWL<19635> A_IWL<19634> A_IWL<19633> A_IWL<19632> A_IWL<19631> A_IWL<19630> A_IWL<19629> A_IWL<19628> A_IWL<19627> A_IWL<19626> A_IWL<19625> A_IWL<19624> A_IWL<19623> A_IWL<19622> A_IWL<19621> A_IWL<19620> A_IWL<19619> A_IWL<19618> A_IWL<19617> A_IWL<19616> A_IWL<19615> A_IWL<19614> A_IWL<19613> A_IWL<19612> A_IWL<19611> A_IWL<19610> A_IWL<19609> A_IWL<19608> A_IWL<19607> A_IWL<19606> A_IWL<19605> A_IWL<19604> A_IWL<19603> A_IWL<19602> A_IWL<19601> A_IWL<19600> A_IWL<19599> A_IWL<19598> A_IWL<19597> A_IWL<19596> A_IWL<19595> A_IWL<19594> A_IWL<19593> A_IWL<19592> A_IWL<19591> A_IWL<19590> A_IWL<19589> A_IWL<19588> A_IWL<19587> A_IWL<19586> A_IWL<19585> A_IWL<19584> A_IWL<19583> A_IWL<19582> A_IWL<19581> A_IWL<19580> A_IWL<19579> A_IWL<19578> A_IWL<19577> A_IWL<19576> A_IWL<19575> A_IWL<19574> A_IWL<19573> A_IWL<19572> A_IWL<19571> A_IWL<19570> A_IWL<19569> A_IWL<19568> A_IWL<19567> A_IWL<19566> A_IWL<19565> A_IWL<19564> A_IWL<19563> A_IWL<19562> A_IWL<19561> A_IWL<19560> A_IWL<19559> A_IWL<19558> A_IWL<19557> A_IWL<19556> A_IWL<19555> A_IWL<19554> A_IWL<19553> A_IWL<19552> A_IWL<19551> A_IWL<19550> A_IWL<19549> A_IWL<19548> A_IWL<19547> A_IWL<19546> A_IWL<19545> A_IWL<19544> A_IWL<19543> A_IWL<19542> A_IWL<19541> A_IWL<19540> A_IWL<19539> A_IWL<19538> A_IWL<19537> A_IWL<19536> A_IWL<19535> A_IWL<19534> A_IWL<19533> A_IWL<19532> A_IWL<19531> A_IWL<19530> A_IWL<19529> A_IWL<19528> A_IWL<19527> A_IWL<19526> A_IWL<19525> A_IWL<19524> A_IWL<19523> A_IWL<19522> A_IWL<19521> A_IWL<19520> A_IWL<19519> A_IWL<19518> A_IWL<19517> A_IWL<19516> A_IWL<19515> A_IWL<19514> A_IWL<19513> A_IWL<19512> A_IWL<19511> A_IWL<19510> A_IWL<19509> A_IWL<19508> A_IWL<19507> A_IWL<19506> A_IWL<19505> A_IWL<19504> A_IWL<19503> A_IWL<19502> A_IWL<19501> A_IWL<19500> A_IWL<19499> A_IWL<19498> A_IWL<19497> A_IWL<19496> A_IWL<19495> A_IWL<19494> A_IWL<19493> A_IWL<19492> A_IWL<19491> A_IWL<19490> A_IWL<19489> A_IWL<19488> A_IWL<19487> A_IWL<19486> A_IWL<19485> A_IWL<19484> A_IWL<19483> A_IWL<19482> A_IWL<19481> A_IWL<19480> A_IWL<19479> A_IWL<19478> A_IWL<19477> A_IWL<19476> A_IWL<19475> A_IWL<19474> A_IWL<19473> A_IWL<19472> A_IWL<19471> A_IWL<19470> A_IWL<19469> A_IWL<19468> A_IWL<19467> A_IWL<19466> A_IWL<19465> A_IWL<19464> A_IWL<19463> A_IWL<19462> A_IWL<19461> A_IWL<19460> A_IWL<19459> A_IWL<19458> A_IWL<19457> A_IWL<19456> A_IWL<20479> A_IWL<20478> A_IWL<20477> A_IWL<20476> A_IWL<20475> A_IWL<20474> A_IWL<20473> A_IWL<20472> A_IWL<20471> A_IWL<20470> A_IWL<20469> A_IWL<20468> A_IWL<20467> A_IWL<20466> A_IWL<20465> A_IWL<20464> A_IWL<20463> A_IWL<20462> A_IWL<20461> A_IWL<20460> A_IWL<20459> A_IWL<20458> A_IWL<20457> A_IWL<20456> A_IWL<20455> A_IWL<20454> A_IWL<20453> A_IWL<20452> A_IWL<20451> A_IWL<20450> A_IWL<20449> A_IWL<20448> A_IWL<20447> A_IWL<20446> A_IWL<20445> A_IWL<20444> A_IWL<20443> A_IWL<20442> A_IWL<20441> A_IWL<20440> A_IWL<20439> A_IWL<20438> A_IWL<20437> A_IWL<20436> A_IWL<20435> A_IWL<20434> A_IWL<20433> A_IWL<20432> A_IWL<20431> A_IWL<20430> A_IWL<20429> A_IWL<20428> A_IWL<20427> A_IWL<20426> A_IWL<20425> A_IWL<20424> A_IWL<20423> A_IWL<20422> A_IWL<20421> A_IWL<20420> A_IWL<20419> A_IWL<20418> A_IWL<20417> A_IWL<20416> A_IWL<20415> A_IWL<20414> A_IWL<20413> A_IWL<20412> A_IWL<20411> A_IWL<20410> A_IWL<20409> A_IWL<20408> A_IWL<20407> A_IWL<20406> A_IWL<20405> A_IWL<20404> A_IWL<20403> A_IWL<20402> A_IWL<20401> A_IWL<20400> A_IWL<20399> A_IWL<20398> A_IWL<20397> A_IWL<20396> A_IWL<20395> A_IWL<20394> A_IWL<20393> A_IWL<20392> A_IWL<20391> A_IWL<20390> A_IWL<20389> A_IWL<20388> A_IWL<20387> A_IWL<20386> A_IWL<20385> A_IWL<20384> A_IWL<20383> A_IWL<20382> A_IWL<20381> A_IWL<20380> A_IWL<20379> A_IWL<20378> A_IWL<20377> A_IWL<20376> A_IWL<20375> A_IWL<20374> A_IWL<20373> A_IWL<20372> A_IWL<20371> A_IWL<20370> A_IWL<20369> A_IWL<20368> A_IWL<20367> A_IWL<20366> A_IWL<20365> A_IWL<20364> A_IWL<20363> A_IWL<20362> A_IWL<20361> A_IWL<20360> A_IWL<20359> A_IWL<20358> A_IWL<20357> A_IWL<20356> A_IWL<20355> A_IWL<20354> A_IWL<20353> A_IWL<20352> A_IWL<20351> A_IWL<20350> A_IWL<20349> A_IWL<20348> A_IWL<20347> A_IWL<20346> A_IWL<20345> A_IWL<20344> A_IWL<20343> A_IWL<20342> A_IWL<20341> A_IWL<20340> A_IWL<20339> A_IWL<20338> A_IWL<20337> A_IWL<20336> A_IWL<20335> A_IWL<20334> A_IWL<20333> A_IWL<20332> A_IWL<20331> A_IWL<20330> A_IWL<20329> A_IWL<20328> A_IWL<20327> A_IWL<20326> A_IWL<20325> A_IWL<20324> A_IWL<20323> A_IWL<20322> A_IWL<20321> A_IWL<20320> A_IWL<20319> A_IWL<20318> A_IWL<20317> A_IWL<20316> A_IWL<20315> A_IWL<20314> A_IWL<20313> A_IWL<20312> A_IWL<20311> A_IWL<20310> A_IWL<20309> A_IWL<20308> A_IWL<20307> A_IWL<20306> A_IWL<20305> A_IWL<20304> A_IWL<20303> A_IWL<20302> A_IWL<20301> A_IWL<20300> A_IWL<20299> A_IWL<20298> A_IWL<20297> A_IWL<20296> A_IWL<20295> A_IWL<20294> A_IWL<20293> A_IWL<20292> A_IWL<20291> A_IWL<20290> A_IWL<20289> A_IWL<20288> A_IWL<20287> A_IWL<20286> A_IWL<20285> A_IWL<20284> A_IWL<20283> A_IWL<20282> A_IWL<20281> A_IWL<20280> A_IWL<20279> A_IWL<20278> A_IWL<20277> A_IWL<20276> A_IWL<20275> A_IWL<20274> A_IWL<20273> A_IWL<20272> A_IWL<20271> A_IWL<20270> A_IWL<20269> A_IWL<20268> A_IWL<20267> A_IWL<20266> A_IWL<20265> A_IWL<20264> A_IWL<20263> A_IWL<20262> A_IWL<20261> A_IWL<20260> A_IWL<20259> A_IWL<20258> A_IWL<20257> A_IWL<20256> A_IWL<20255> A_IWL<20254> A_IWL<20253> A_IWL<20252> A_IWL<20251> A_IWL<20250> A_IWL<20249> A_IWL<20248> A_IWL<20247> A_IWL<20246> A_IWL<20245> A_IWL<20244> A_IWL<20243> A_IWL<20242> A_IWL<20241> A_IWL<20240> A_IWL<20239> A_IWL<20238> A_IWL<20237> A_IWL<20236> A_IWL<20235> A_IWL<20234> A_IWL<20233> A_IWL<20232> A_IWL<20231> A_IWL<20230> A_IWL<20229> A_IWL<20228> A_IWL<20227> A_IWL<20226> A_IWL<20225> A_IWL<20224> A_IWL<20223> A_IWL<20222> A_IWL<20221> A_IWL<20220> A_IWL<20219> A_IWL<20218> A_IWL<20217> A_IWL<20216> A_IWL<20215> A_IWL<20214> A_IWL<20213> A_IWL<20212> A_IWL<20211> A_IWL<20210> A_IWL<20209> A_IWL<20208> A_IWL<20207> A_IWL<20206> A_IWL<20205> A_IWL<20204> A_IWL<20203> A_IWL<20202> A_IWL<20201> A_IWL<20200> A_IWL<20199> A_IWL<20198> A_IWL<20197> A_IWL<20196> A_IWL<20195> A_IWL<20194> A_IWL<20193> A_IWL<20192> A_IWL<20191> A_IWL<20190> A_IWL<20189> A_IWL<20188> A_IWL<20187> A_IWL<20186> A_IWL<20185> A_IWL<20184> A_IWL<20183> A_IWL<20182> A_IWL<20181> A_IWL<20180> A_IWL<20179> A_IWL<20178> A_IWL<20177> A_IWL<20176> A_IWL<20175> A_IWL<20174> A_IWL<20173> A_IWL<20172> A_IWL<20171> A_IWL<20170> A_IWL<20169> A_IWL<20168> A_IWL<20167> A_IWL<20166> A_IWL<20165> A_IWL<20164> A_IWL<20163> A_IWL<20162> A_IWL<20161> A_IWL<20160> A_IWL<20159> A_IWL<20158> A_IWL<20157> A_IWL<20156> A_IWL<20155> A_IWL<20154> A_IWL<20153> A_IWL<20152> A_IWL<20151> A_IWL<20150> A_IWL<20149> A_IWL<20148> A_IWL<20147> A_IWL<20146> A_IWL<20145> A_IWL<20144> A_IWL<20143> A_IWL<20142> A_IWL<20141> A_IWL<20140> A_IWL<20139> A_IWL<20138> A_IWL<20137> A_IWL<20136> A_IWL<20135> A_IWL<20134> A_IWL<20133> A_IWL<20132> A_IWL<20131> A_IWL<20130> A_IWL<20129> A_IWL<20128> A_IWL<20127> A_IWL<20126> A_IWL<20125> A_IWL<20124> A_IWL<20123> A_IWL<20122> A_IWL<20121> A_IWL<20120> A_IWL<20119> A_IWL<20118> A_IWL<20117> A_IWL<20116> A_IWL<20115> A_IWL<20114> A_IWL<20113> A_IWL<20112> A_IWL<20111> A_IWL<20110> A_IWL<20109> A_IWL<20108> A_IWL<20107> A_IWL<20106> A_IWL<20105> A_IWL<20104> A_IWL<20103> A_IWL<20102> A_IWL<20101> A_IWL<20100> A_IWL<20099> A_IWL<20098> A_IWL<20097> A_IWL<20096> A_IWL<20095> A_IWL<20094> A_IWL<20093> A_IWL<20092> A_IWL<20091> A_IWL<20090> A_IWL<20089> A_IWL<20088> A_IWL<20087> A_IWL<20086> A_IWL<20085> A_IWL<20084> A_IWL<20083> A_IWL<20082> A_IWL<20081> A_IWL<20080> A_IWL<20079> A_IWL<20078> A_IWL<20077> A_IWL<20076> A_IWL<20075> A_IWL<20074> A_IWL<20073> A_IWL<20072> A_IWL<20071> A_IWL<20070> A_IWL<20069> A_IWL<20068> A_IWL<20067> A_IWL<20066> A_IWL<20065> A_IWL<20064> A_IWL<20063> A_IWL<20062> A_IWL<20061> A_IWL<20060> A_IWL<20059> A_IWL<20058> A_IWL<20057> A_IWL<20056> A_IWL<20055> A_IWL<20054> A_IWL<20053> A_IWL<20052> A_IWL<20051> A_IWL<20050> A_IWL<20049> A_IWL<20048> A_IWL<20047> A_IWL<20046> A_IWL<20045> A_IWL<20044> A_IWL<20043> A_IWL<20042> A_IWL<20041> A_IWL<20040> A_IWL<20039> A_IWL<20038> A_IWL<20037> A_IWL<20036> A_IWL<20035> A_IWL<20034> A_IWL<20033> A_IWL<20032> A_IWL<20031> A_IWL<20030> A_IWL<20029> A_IWL<20028> A_IWL<20027> A_IWL<20026> A_IWL<20025> A_IWL<20024> A_IWL<20023> A_IWL<20022> A_IWL<20021> A_IWL<20020> A_IWL<20019> A_IWL<20018> A_IWL<20017> A_IWL<20016> A_IWL<20015> A_IWL<20014> A_IWL<20013> A_IWL<20012> A_IWL<20011> A_IWL<20010> A_IWL<20009> A_IWL<20008> A_IWL<20007> A_IWL<20006> A_IWL<20005> A_IWL<20004> A_IWL<20003> A_IWL<20002> A_IWL<20001> A_IWL<20000> A_IWL<19999> A_IWL<19998> A_IWL<19997> A_IWL<19996> A_IWL<19995> A_IWL<19994> A_IWL<19993> A_IWL<19992> A_IWL<19991> A_IWL<19990> A_IWL<19989> A_IWL<19988> A_IWL<19987> A_IWL<19986> A_IWL<19985> A_IWL<19984> A_IWL<19983> A_IWL<19982> A_IWL<19981> A_IWL<19980> A_IWL<19979> A_IWL<19978> A_IWL<19977> A_IWL<19976> A_IWL<19975> A_IWL<19974> A_IWL<19973> A_IWL<19972> A_IWL<19971> A_IWL<19970> A_IWL<19969> A_IWL<19968> VDD_CORE VSS / RM_IHPSG13_8192x32_c4_1P_COLUMN_pcell_0 +XCOL<38> A_BLC<77> A_BLC<76> A_BLC_TOP<77> A_BLC_TOP<76> A_BLT<77> A_BLT<76> A_BLT_TOP<77> A_BLT_TOP<76> A_IWL<19455> A_IWL<19454> A_IWL<19453> A_IWL<19452> A_IWL<19451> A_IWL<19450> A_IWL<19449> A_IWL<19448> A_IWL<19447> A_IWL<19446> A_IWL<19445> A_IWL<19444> A_IWL<19443> A_IWL<19442> A_IWL<19441> A_IWL<19440> A_IWL<19439> A_IWL<19438> A_IWL<19437> A_IWL<19436> A_IWL<19435> A_IWL<19434> A_IWL<19433> A_IWL<19432> A_IWL<19431> A_IWL<19430> A_IWL<19429> A_IWL<19428> A_IWL<19427> A_IWL<19426> A_IWL<19425> A_IWL<19424> A_IWL<19423> A_IWL<19422> A_IWL<19421> A_IWL<19420> A_IWL<19419> A_IWL<19418> A_IWL<19417> A_IWL<19416> A_IWL<19415> A_IWL<19414> A_IWL<19413> A_IWL<19412> A_IWL<19411> A_IWL<19410> A_IWL<19409> A_IWL<19408> A_IWL<19407> A_IWL<19406> A_IWL<19405> A_IWL<19404> A_IWL<19403> A_IWL<19402> A_IWL<19401> A_IWL<19400> A_IWL<19399> A_IWL<19398> A_IWL<19397> A_IWL<19396> A_IWL<19395> A_IWL<19394> A_IWL<19393> A_IWL<19392> A_IWL<19391> A_IWL<19390> A_IWL<19389> A_IWL<19388> A_IWL<19387> A_IWL<19386> A_IWL<19385> A_IWL<19384> A_IWL<19383> A_IWL<19382> A_IWL<19381> A_IWL<19380> A_IWL<19379> A_IWL<19378> A_IWL<19377> A_IWL<19376> A_IWL<19375> A_IWL<19374> A_IWL<19373> A_IWL<19372> A_IWL<19371> A_IWL<19370> A_IWL<19369> A_IWL<19368> A_IWL<19367> A_IWL<19366> A_IWL<19365> A_IWL<19364> A_IWL<19363> A_IWL<19362> A_IWL<19361> A_IWL<19360> A_IWL<19359> A_IWL<19358> A_IWL<19357> A_IWL<19356> A_IWL<19355> A_IWL<19354> A_IWL<19353> A_IWL<19352> A_IWL<19351> A_IWL<19350> A_IWL<19349> A_IWL<19348> A_IWL<19347> A_IWL<19346> A_IWL<19345> A_IWL<19344> A_IWL<19343> A_IWL<19342> A_IWL<19341> A_IWL<19340> A_IWL<19339> A_IWL<19338> A_IWL<19337> A_IWL<19336> A_IWL<19335> A_IWL<19334> A_IWL<19333> A_IWL<19332> A_IWL<19331> A_IWL<19330> A_IWL<19329> A_IWL<19328> A_IWL<19327> A_IWL<19326> A_IWL<19325> A_IWL<19324> A_IWL<19323> A_IWL<19322> A_IWL<19321> A_IWL<19320> A_IWL<19319> A_IWL<19318> A_IWL<19317> A_IWL<19316> A_IWL<19315> A_IWL<19314> A_IWL<19313> A_IWL<19312> A_IWL<19311> A_IWL<19310> A_IWL<19309> A_IWL<19308> A_IWL<19307> A_IWL<19306> A_IWL<19305> A_IWL<19304> A_IWL<19303> A_IWL<19302> A_IWL<19301> A_IWL<19300> A_IWL<19299> A_IWL<19298> A_IWL<19297> A_IWL<19296> A_IWL<19295> A_IWL<19294> A_IWL<19293> A_IWL<19292> A_IWL<19291> A_IWL<19290> A_IWL<19289> A_IWL<19288> A_IWL<19287> A_IWL<19286> A_IWL<19285> A_IWL<19284> A_IWL<19283> A_IWL<19282> A_IWL<19281> A_IWL<19280> A_IWL<19279> A_IWL<19278> A_IWL<19277> A_IWL<19276> A_IWL<19275> A_IWL<19274> A_IWL<19273> A_IWL<19272> A_IWL<19271> A_IWL<19270> A_IWL<19269> A_IWL<19268> A_IWL<19267> A_IWL<19266> A_IWL<19265> A_IWL<19264> A_IWL<19263> A_IWL<19262> A_IWL<19261> A_IWL<19260> A_IWL<19259> A_IWL<19258> A_IWL<19257> A_IWL<19256> A_IWL<19255> A_IWL<19254> A_IWL<19253> A_IWL<19252> A_IWL<19251> A_IWL<19250> A_IWL<19249> A_IWL<19248> A_IWL<19247> A_IWL<19246> A_IWL<19245> A_IWL<19244> A_IWL<19243> A_IWL<19242> A_IWL<19241> A_IWL<19240> A_IWL<19239> A_IWL<19238> A_IWL<19237> A_IWL<19236> A_IWL<19235> A_IWL<19234> A_IWL<19233> A_IWL<19232> A_IWL<19231> A_IWL<19230> A_IWL<19229> A_IWL<19228> A_IWL<19227> A_IWL<19226> A_IWL<19225> A_IWL<19224> A_IWL<19223> A_IWL<19222> A_IWL<19221> A_IWL<19220> A_IWL<19219> A_IWL<19218> A_IWL<19217> A_IWL<19216> A_IWL<19215> A_IWL<19214> A_IWL<19213> A_IWL<19212> A_IWL<19211> A_IWL<19210> A_IWL<19209> A_IWL<19208> A_IWL<19207> A_IWL<19206> A_IWL<19205> A_IWL<19204> A_IWL<19203> A_IWL<19202> A_IWL<19201> A_IWL<19200> A_IWL<19199> A_IWL<19198> A_IWL<19197> A_IWL<19196> A_IWL<19195> A_IWL<19194> A_IWL<19193> A_IWL<19192> A_IWL<19191> A_IWL<19190> A_IWL<19189> A_IWL<19188> A_IWL<19187> A_IWL<19186> A_IWL<19185> A_IWL<19184> A_IWL<19183> A_IWL<19182> A_IWL<19181> A_IWL<19180> A_IWL<19179> A_IWL<19178> A_IWL<19177> A_IWL<19176> A_IWL<19175> A_IWL<19174> A_IWL<19173> A_IWL<19172> A_IWL<19171> A_IWL<19170> A_IWL<19169> A_IWL<19168> A_IWL<19167> A_IWL<19166> A_IWL<19165> A_IWL<19164> A_IWL<19163> A_IWL<19162> A_IWL<19161> A_IWL<19160> A_IWL<19159> A_IWL<19158> A_IWL<19157> A_IWL<19156> A_IWL<19155> A_IWL<19154> A_IWL<19153> A_IWL<19152> A_IWL<19151> A_IWL<19150> A_IWL<19149> A_IWL<19148> A_IWL<19147> A_IWL<19146> A_IWL<19145> A_IWL<19144> A_IWL<19143> A_IWL<19142> A_IWL<19141> A_IWL<19140> A_IWL<19139> A_IWL<19138> A_IWL<19137> A_IWL<19136> A_IWL<19135> A_IWL<19134> A_IWL<19133> A_IWL<19132> A_IWL<19131> A_IWL<19130> A_IWL<19129> A_IWL<19128> A_IWL<19127> A_IWL<19126> A_IWL<19125> A_IWL<19124> A_IWL<19123> A_IWL<19122> A_IWL<19121> A_IWL<19120> A_IWL<19119> A_IWL<19118> A_IWL<19117> A_IWL<19116> A_IWL<19115> A_IWL<19114> A_IWL<19113> A_IWL<19112> A_IWL<19111> A_IWL<19110> A_IWL<19109> A_IWL<19108> A_IWL<19107> A_IWL<19106> A_IWL<19105> A_IWL<19104> A_IWL<19103> A_IWL<19102> A_IWL<19101> A_IWL<19100> A_IWL<19099> A_IWL<19098> A_IWL<19097> A_IWL<19096> A_IWL<19095> A_IWL<19094> A_IWL<19093> A_IWL<19092> A_IWL<19091> A_IWL<19090> A_IWL<19089> A_IWL<19088> A_IWL<19087> A_IWL<19086> A_IWL<19085> A_IWL<19084> A_IWL<19083> A_IWL<19082> A_IWL<19081> A_IWL<19080> A_IWL<19079> A_IWL<19078> A_IWL<19077> A_IWL<19076> A_IWL<19075> A_IWL<19074> A_IWL<19073> A_IWL<19072> A_IWL<19071> A_IWL<19070> A_IWL<19069> A_IWL<19068> A_IWL<19067> A_IWL<19066> A_IWL<19065> A_IWL<19064> A_IWL<19063> A_IWL<19062> A_IWL<19061> A_IWL<19060> A_IWL<19059> A_IWL<19058> A_IWL<19057> A_IWL<19056> A_IWL<19055> A_IWL<19054> A_IWL<19053> A_IWL<19052> A_IWL<19051> A_IWL<19050> A_IWL<19049> A_IWL<19048> A_IWL<19047> A_IWL<19046> A_IWL<19045> A_IWL<19044> A_IWL<19043> A_IWL<19042> A_IWL<19041> A_IWL<19040> A_IWL<19039> A_IWL<19038> A_IWL<19037> A_IWL<19036> A_IWL<19035> A_IWL<19034> A_IWL<19033> A_IWL<19032> A_IWL<19031> A_IWL<19030> A_IWL<19029> A_IWL<19028> A_IWL<19027> A_IWL<19026> A_IWL<19025> A_IWL<19024> A_IWL<19023> A_IWL<19022> A_IWL<19021> A_IWL<19020> A_IWL<19019> A_IWL<19018> A_IWL<19017> A_IWL<19016> A_IWL<19015> A_IWL<19014> A_IWL<19013> A_IWL<19012> A_IWL<19011> A_IWL<19010> A_IWL<19009> A_IWL<19008> A_IWL<19007> A_IWL<19006> A_IWL<19005> A_IWL<19004> A_IWL<19003> A_IWL<19002> A_IWL<19001> A_IWL<19000> A_IWL<18999> A_IWL<18998> A_IWL<18997> A_IWL<18996> A_IWL<18995> A_IWL<18994> A_IWL<18993> A_IWL<18992> A_IWL<18991> A_IWL<18990> A_IWL<18989> A_IWL<18988> A_IWL<18987> A_IWL<18986> A_IWL<18985> A_IWL<18984> A_IWL<18983> A_IWL<18982> A_IWL<18981> A_IWL<18980> A_IWL<18979> A_IWL<18978> A_IWL<18977> A_IWL<18976> A_IWL<18975> A_IWL<18974> A_IWL<18973> A_IWL<18972> A_IWL<18971> A_IWL<18970> A_IWL<18969> A_IWL<18968> A_IWL<18967> A_IWL<18966> A_IWL<18965> A_IWL<18964> A_IWL<18963> A_IWL<18962> A_IWL<18961> A_IWL<18960> A_IWL<18959> A_IWL<18958> A_IWL<18957> A_IWL<18956> A_IWL<18955> A_IWL<18954> A_IWL<18953> A_IWL<18952> A_IWL<18951> A_IWL<18950> A_IWL<18949> A_IWL<18948> A_IWL<18947> A_IWL<18946> A_IWL<18945> A_IWL<18944> A_IWL<19967> A_IWL<19966> A_IWL<19965> A_IWL<19964> A_IWL<19963> A_IWL<19962> A_IWL<19961> A_IWL<19960> A_IWL<19959> A_IWL<19958> A_IWL<19957> A_IWL<19956> A_IWL<19955> A_IWL<19954> A_IWL<19953> A_IWL<19952> A_IWL<19951> A_IWL<19950> A_IWL<19949> A_IWL<19948> A_IWL<19947> A_IWL<19946> A_IWL<19945> A_IWL<19944> A_IWL<19943> A_IWL<19942> A_IWL<19941> A_IWL<19940> A_IWL<19939> A_IWL<19938> A_IWL<19937> A_IWL<19936> A_IWL<19935> A_IWL<19934> A_IWL<19933> A_IWL<19932> A_IWL<19931> A_IWL<19930> A_IWL<19929> A_IWL<19928> A_IWL<19927> A_IWL<19926> A_IWL<19925> A_IWL<19924> A_IWL<19923> A_IWL<19922> A_IWL<19921> A_IWL<19920> A_IWL<19919> A_IWL<19918> A_IWL<19917> A_IWL<19916> A_IWL<19915> A_IWL<19914> A_IWL<19913> A_IWL<19912> A_IWL<19911> A_IWL<19910> A_IWL<19909> A_IWL<19908> A_IWL<19907> A_IWL<19906> A_IWL<19905> A_IWL<19904> A_IWL<19903> A_IWL<19902> A_IWL<19901> A_IWL<19900> A_IWL<19899> A_IWL<19898> A_IWL<19897> A_IWL<19896> A_IWL<19895> A_IWL<19894> A_IWL<19893> A_IWL<19892> A_IWL<19891> A_IWL<19890> A_IWL<19889> A_IWL<19888> A_IWL<19887> A_IWL<19886> A_IWL<19885> A_IWL<19884> A_IWL<19883> A_IWL<19882> A_IWL<19881> A_IWL<19880> A_IWL<19879> A_IWL<19878> A_IWL<19877> A_IWL<19876> A_IWL<19875> A_IWL<19874> A_IWL<19873> A_IWL<19872> A_IWL<19871> A_IWL<19870> A_IWL<19869> A_IWL<19868> A_IWL<19867> A_IWL<19866> A_IWL<19865> A_IWL<19864> A_IWL<19863> A_IWL<19862> A_IWL<19861> A_IWL<19860> A_IWL<19859> A_IWL<19858> A_IWL<19857> A_IWL<19856> A_IWL<19855> A_IWL<19854> A_IWL<19853> A_IWL<19852> A_IWL<19851> A_IWL<19850> A_IWL<19849> A_IWL<19848> A_IWL<19847> A_IWL<19846> A_IWL<19845> A_IWL<19844> A_IWL<19843> A_IWL<19842> A_IWL<19841> A_IWL<19840> A_IWL<19839> A_IWL<19838> A_IWL<19837> A_IWL<19836> A_IWL<19835> A_IWL<19834> A_IWL<19833> A_IWL<19832> A_IWL<19831> A_IWL<19830> A_IWL<19829> A_IWL<19828> A_IWL<19827> A_IWL<19826> A_IWL<19825> A_IWL<19824> A_IWL<19823> A_IWL<19822> A_IWL<19821> A_IWL<19820> A_IWL<19819> A_IWL<19818> A_IWL<19817> A_IWL<19816> A_IWL<19815> A_IWL<19814> A_IWL<19813> A_IWL<19812> A_IWL<19811> A_IWL<19810> A_IWL<19809> A_IWL<19808> A_IWL<19807> A_IWL<19806> A_IWL<19805> A_IWL<19804> A_IWL<19803> A_IWL<19802> A_IWL<19801> A_IWL<19800> A_IWL<19799> A_IWL<19798> A_IWL<19797> A_IWL<19796> A_IWL<19795> A_IWL<19794> A_IWL<19793> A_IWL<19792> A_IWL<19791> A_IWL<19790> A_IWL<19789> A_IWL<19788> A_IWL<19787> A_IWL<19786> A_IWL<19785> A_IWL<19784> A_IWL<19783> A_IWL<19782> A_IWL<19781> A_IWL<19780> A_IWL<19779> A_IWL<19778> A_IWL<19777> A_IWL<19776> A_IWL<19775> A_IWL<19774> A_IWL<19773> A_IWL<19772> A_IWL<19771> A_IWL<19770> A_IWL<19769> A_IWL<19768> A_IWL<19767> A_IWL<19766> A_IWL<19765> A_IWL<19764> A_IWL<19763> A_IWL<19762> A_IWL<19761> A_IWL<19760> A_IWL<19759> A_IWL<19758> A_IWL<19757> A_IWL<19756> A_IWL<19755> A_IWL<19754> A_IWL<19753> A_IWL<19752> A_IWL<19751> A_IWL<19750> A_IWL<19749> A_IWL<19748> A_IWL<19747> A_IWL<19746> A_IWL<19745> A_IWL<19744> A_IWL<19743> A_IWL<19742> A_IWL<19741> A_IWL<19740> A_IWL<19739> A_IWL<19738> A_IWL<19737> A_IWL<19736> A_IWL<19735> A_IWL<19734> A_IWL<19733> A_IWL<19732> A_IWL<19731> A_IWL<19730> A_IWL<19729> A_IWL<19728> A_IWL<19727> A_IWL<19726> A_IWL<19725> A_IWL<19724> A_IWL<19723> A_IWL<19722> A_IWL<19721> A_IWL<19720> A_IWL<19719> A_IWL<19718> A_IWL<19717> A_IWL<19716> A_IWL<19715> A_IWL<19714> A_IWL<19713> A_IWL<19712> A_IWL<19711> A_IWL<19710> A_IWL<19709> A_IWL<19708> A_IWL<19707> A_IWL<19706> A_IWL<19705> A_IWL<19704> A_IWL<19703> A_IWL<19702> A_IWL<19701> A_IWL<19700> A_IWL<19699> A_IWL<19698> A_IWL<19697> A_IWL<19696> A_IWL<19695> A_IWL<19694> A_IWL<19693> A_IWL<19692> A_IWL<19691> A_IWL<19690> A_IWL<19689> A_IWL<19688> A_IWL<19687> A_IWL<19686> A_IWL<19685> A_IWL<19684> A_IWL<19683> A_IWL<19682> A_IWL<19681> A_IWL<19680> A_IWL<19679> A_IWL<19678> A_IWL<19677> A_IWL<19676> A_IWL<19675> A_IWL<19674> A_IWL<19673> A_IWL<19672> A_IWL<19671> A_IWL<19670> A_IWL<19669> A_IWL<19668> A_IWL<19667> A_IWL<19666> A_IWL<19665> A_IWL<19664> A_IWL<19663> A_IWL<19662> A_IWL<19661> A_IWL<19660> A_IWL<19659> A_IWL<19658> A_IWL<19657> A_IWL<19656> A_IWL<19655> A_IWL<19654> A_IWL<19653> A_IWL<19652> A_IWL<19651> A_IWL<19650> A_IWL<19649> A_IWL<19648> A_IWL<19647> A_IWL<19646> A_IWL<19645> A_IWL<19644> A_IWL<19643> A_IWL<19642> A_IWL<19641> A_IWL<19640> A_IWL<19639> A_IWL<19638> A_IWL<19637> A_IWL<19636> A_IWL<19635> A_IWL<19634> A_IWL<19633> A_IWL<19632> A_IWL<19631> A_IWL<19630> A_IWL<19629> A_IWL<19628> A_IWL<19627> A_IWL<19626> A_IWL<19625> A_IWL<19624> A_IWL<19623> A_IWL<19622> A_IWL<19621> A_IWL<19620> A_IWL<19619> A_IWL<19618> A_IWL<19617> A_IWL<19616> A_IWL<19615> A_IWL<19614> A_IWL<19613> A_IWL<19612> A_IWL<19611> A_IWL<19610> A_IWL<19609> A_IWL<19608> A_IWL<19607> A_IWL<19606> A_IWL<19605> A_IWL<19604> A_IWL<19603> A_IWL<19602> A_IWL<19601> A_IWL<19600> A_IWL<19599> A_IWL<19598> A_IWL<19597> A_IWL<19596> A_IWL<19595> A_IWL<19594> A_IWL<19593> A_IWL<19592> A_IWL<19591> A_IWL<19590> A_IWL<19589> A_IWL<19588> A_IWL<19587> A_IWL<19586> A_IWL<19585> A_IWL<19584> A_IWL<19583> A_IWL<19582> A_IWL<19581> A_IWL<19580> A_IWL<19579> A_IWL<19578> A_IWL<19577> A_IWL<19576> A_IWL<19575> A_IWL<19574> A_IWL<19573> A_IWL<19572> A_IWL<19571> A_IWL<19570> A_IWL<19569> A_IWL<19568> A_IWL<19567> A_IWL<19566> A_IWL<19565> A_IWL<19564> A_IWL<19563> A_IWL<19562> A_IWL<19561> A_IWL<19560> A_IWL<19559> A_IWL<19558> A_IWL<19557> A_IWL<19556> A_IWL<19555> A_IWL<19554> A_IWL<19553> A_IWL<19552> A_IWL<19551> A_IWL<19550> A_IWL<19549> A_IWL<19548> A_IWL<19547> A_IWL<19546> A_IWL<19545> A_IWL<19544> A_IWL<19543> A_IWL<19542> A_IWL<19541> A_IWL<19540> A_IWL<19539> A_IWL<19538> A_IWL<19537> A_IWL<19536> A_IWL<19535> A_IWL<19534> A_IWL<19533> A_IWL<19532> A_IWL<19531> A_IWL<19530> A_IWL<19529> A_IWL<19528> A_IWL<19527> A_IWL<19526> A_IWL<19525> A_IWL<19524> A_IWL<19523> A_IWL<19522> A_IWL<19521> A_IWL<19520> A_IWL<19519> A_IWL<19518> A_IWL<19517> A_IWL<19516> A_IWL<19515> A_IWL<19514> A_IWL<19513> A_IWL<19512> A_IWL<19511> A_IWL<19510> A_IWL<19509> A_IWL<19508> A_IWL<19507> A_IWL<19506> A_IWL<19505> A_IWL<19504> A_IWL<19503> A_IWL<19502> A_IWL<19501> A_IWL<19500> A_IWL<19499> A_IWL<19498> A_IWL<19497> A_IWL<19496> A_IWL<19495> A_IWL<19494> A_IWL<19493> A_IWL<19492> A_IWL<19491> A_IWL<19490> A_IWL<19489> A_IWL<19488> A_IWL<19487> A_IWL<19486> A_IWL<19485> A_IWL<19484> A_IWL<19483> A_IWL<19482> A_IWL<19481> A_IWL<19480> A_IWL<19479> A_IWL<19478> A_IWL<19477> A_IWL<19476> A_IWL<19475> A_IWL<19474> A_IWL<19473> A_IWL<19472> A_IWL<19471> A_IWL<19470> A_IWL<19469> A_IWL<19468> A_IWL<19467> A_IWL<19466> A_IWL<19465> A_IWL<19464> A_IWL<19463> A_IWL<19462> A_IWL<19461> A_IWL<19460> A_IWL<19459> A_IWL<19458> A_IWL<19457> A_IWL<19456> VDD_CORE VSS / RM_IHPSG13_8192x32_c4_1P_COLUMN_pcell_0 +XCOL<37> A_BLC<75> A_BLC<74> A_BLC_TOP<75> A_BLC_TOP<74> A_BLT<75> A_BLT<74> A_BLT_TOP<75> A_BLT_TOP<74> A_IWL<18943> A_IWL<18942> A_IWL<18941> A_IWL<18940> A_IWL<18939> A_IWL<18938> A_IWL<18937> A_IWL<18936> A_IWL<18935> A_IWL<18934> A_IWL<18933> A_IWL<18932> A_IWL<18931> A_IWL<18930> A_IWL<18929> A_IWL<18928> A_IWL<18927> A_IWL<18926> A_IWL<18925> A_IWL<18924> A_IWL<18923> A_IWL<18922> A_IWL<18921> A_IWL<18920> A_IWL<18919> A_IWL<18918> A_IWL<18917> A_IWL<18916> A_IWL<18915> A_IWL<18914> A_IWL<18913> A_IWL<18912> A_IWL<18911> A_IWL<18910> A_IWL<18909> A_IWL<18908> A_IWL<18907> A_IWL<18906> A_IWL<18905> A_IWL<18904> A_IWL<18903> A_IWL<18902> A_IWL<18901> A_IWL<18900> A_IWL<18899> A_IWL<18898> A_IWL<18897> A_IWL<18896> A_IWL<18895> A_IWL<18894> A_IWL<18893> A_IWL<18892> A_IWL<18891> A_IWL<18890> A_IWL<18889> A_IWL<18888> A_IWL<18887> A_IWL<18886> A_IWL<18885> A_IWL<18884> A_IWL<18883> A_IWL<18882> A_IWL<18881> A_IWL<18880> A_IWL<18879> A_IWL<18878> A_IWL<18877> A_IWL<18876> A_IWL<18875> A_IWL<18874> A_IWL<18873> A_IWL<18872> A_IWL<18871> A_IWL<18870> A_IWL<18869> A_IWL<18868> A_IWL<18867> A_IWL<18866> A_IWL<18865> A_IWL<18864> A_IWL<18863> A_IWL<18862> A_IWL<18861> A_IWL<18860> A_IWL<18859> A_IWL<18858> A_IWL<18857> A_IWL<18856> A_IWL<18855> A_IWL<18854> A_IWL<18853> A_IWL<18852> A_IWL<18851> A_IWL<18850> A_IWL<18849> A_IWL<18848> A_IWL<18847> A_IWL<18846> A_IWL<18845> A_IWL<18844> A_IWL<18843> A_IWL<18842> A_IWL<18841> A_IWL<18840> A_IWL<18839> A_IWL<18838> A_IWL<18837> A_IWL<18836> A_IWL<18835> A_IWL<18834> A_IWL<18833> A_IWL<18832> A_IWL<18831> A_IWL<18830> A_IWL<18829> A_IWL<18828> A_IWL<18827> A_IWL<18826> A_IWL<18825> A_IWL<18824> A_IWL<18823> A_IWL<18822> A_IWL<18821> A_IWL<18820> A_IWL<18819> A_IWL<18818> A_IWL<18817> A_IWL<18816> A_IWL<18815> A_IWL<18814> A_IWL<18813> A_IWL<18812> A_IWL<18811> A_IWL<18810> A_IWL<18809> A_IWL<18808> A_IWL<18807> A_IWL<18806> A_IWL<18805> A_IWL<18804> A_IWL<18803> A_IWL<18802> A_IWL<18801> A_IWL<18800> A_IWL<18799> A_IWL<18798> A_IWL<18797> A_IWL<18796> A_IWL<18795> A_IWL<18794> A_IWL<18793> A_IWL<18792> A_IWL<18791> A_IWL<18790> A_IWL<18789> A_IWL<18788> A_IWL<18787> A_IWL<18786> A_IWL<18785> A_IWL<18784> A_IWL<18783> A_IWL<18782> A_IWL<18781> A_IWL<18780> A_IWL<18779> A_IWL<18778> A_IWL<18777> A_IWL<18776> A_IWL<18775> A_IWL<18774> A_IWL<18773> A_IWL<18772> A_IWL<18771> A_IWL<18770> A_IWL<18769> A_IWL<18768> A_IWL<18767> A_IWL<18766> A_IWL<18765> A_IWL<18764> A_IWL<18763> A_IWL<18762> A_IWL<18761> A_IWL<18760> A_IWL<18759> A_IWL<18758> A_IWL<18757> A_IWL<18756> A_IWL<18755> A_IWL<18754> A_IWL<18753> A_IWL<18752> A_IWL<18751> A_IWL<18750> A_IWL<18749> A_IWL<18748> A_IWL<18747> A_IWL<18746> A_IWL<18745> A_IWL<18744> A_IWL<18743> A_IWL<18742> A_IWL<18741> A_IWL<18740> A_IWL<18739> A_IWL<18738> A_IWL<18737> A_IWL<18736> A_IWL<18735> A_IWL<18734> A_IWL<18733> A_IWL<18732> A_IWL<18731> A_IWL<18730> A_IWL<18729> A_IWL<18728> A_IWL<18727> A_IWL<18726> A_IWL<18725> A_IWL<18724> A_IWL<18723> A_IWL<18722> A_IWL<18721> A_IWL<18720> A_IWL<18719> A_IWL<18718> A_IWL<18717> A_IWL<18716> A_IWL<18715> A_IWL<18714> A_IWL<18713> A_IWL<18712> A_IWL<18711> A_IWL<18710> A_IWL<18709> A_IWL<18708> A_IWL<18707> A_IWL<18706> A_IWL<18705> A_IWL<18704> A_IWL<18703> A_IWL<18702> A_IWL<18701> A_IWL<18700> A_IWL<18699> A_IWL<18698> A_IWL<18697> A_IWL<18696> A_IWL<18695> A_IWL<18694> A_IWL<18693> A_IWL<18692> A_IWL<18691> A_IWL<18690> A_IWL<18689> A_IWL<18688> A_IWL<18687> A_IWL<18686> A_IWL<18685> A_IWL<18684> A_IWL<18683> A_IWL<18682> A_IWL<18681> A_IWL<18680> A_IWL<18679> A_IWL<18678> A_IWL<18677> A_IWL<18676> A_IWL<18675> A_IWL<18674> A_IWL<18673> A_IWL<18672> A_IWL<18671> A_IWL<18670> A_IWL<18669> A_IWL<18668> A_IWL<18667> A_IWL<18666> A_IWL<18665> A_IWL<18664> A_IWL<18663> A_IWL<18662> A_IWL<18661> A_IWL<18660> A_IWL<18659> A_IWL<18658> A_IWL<18657> A_IWL<18656> A_IWL<18655> A_IWL<18654> A_IWL<18653> A_IWL<18652> A_IWL<18651> A_IWL<18650> A_IWL<18649> A_IWL<18648> A_IWL<18647> A_IWL<18646> A_IWL<18645> A_IWL<18644> A_IWL<18643> A_IWL<18642> A_IWL<18641> A_IWL<18640> A_IWL<18639> A_IWL<18638> A_IWL<18637> A_IWL<18636> A_IWL<18635> A_IWL<18634> A_IWL<18633> A_IWL<18632> A_IWL<18631> A_IWL<18630> A_IWL<18629> A_IWL<18628> A_IWL<18627> A_IWL<18626> A_IWL<18625> A_IWL<18624> A_IWL<18623> A_IWL<18622> A_IWL<18621> A_IWL<18620> A_IWL<18619> A_IWL<18618> A_IWL<18617> A_IWL<18616> A_IWL<18615> A_IWL<18614> A_IWL<18613> A_IWL<18612> A_IWL<18611> A_IWL<18610> A_IWL<18609> A_IWL<18608> A_IWL<18607> A_IWL<18606> A_IWL<18605> A_IWL<18604> A_IWL<18603> A_IWL<18602> A_IWL<18601> A_IWL<18600> A_IWL<18599> A_IWL<18598> A_IWL<18597> A_IWL<18596> A_IWL<18595> A_IWL<18594> A_IWL<18593> A_IWL<18592> A_IWL<18591> A_IWL<18590> A_IWL<18589> A_IWL<18588> A_IWL<18587> A_IWL<18586> A_IWL<18585> A_IWL<18584> A_IWL<18583> A_IWL<18582> A_IWL<18581> A_IWL<18580> A_IWL<18579> A_IWL<18578> A_IWL<18577> A_IWL<18576> A_IWL<18575> A_IWL<18574> A_IWL<18573> A_IWL<18572> A_IWL<18571> A_IWL<18570> A_IWL<18569> A_IWL<18568> A_IWL<18567> A_IWL<18566> A_IWL<18565> A_IWL<18564> A_IWL<18563> A_IWL<18562> A_IWL<18561> A_IWL<18560> A_IWL<18559> A_IWL<18558> A_IWL<18557> A_IWL<18556> A_IWL<18555> A_IWL<18554> A_IWL<18553> A_IWL<18552> A_IWL<18551> A_IWL<18550> A_IWL<18549> A_IWL<18548> A_IWL<18547> A_IWL<18546> A_IWL<18545> A_IWL<18544> A_IWL<18543> A_IWL<18542> A_IWL<18541> A_IWL<18540> A_IWL<18539> A_IWL<18538> A_IWL<18537> A_IWL<18536> A_IWL<18535> A_IWL<18534> A_IWL<18533> A_IWL<18532> A_IWL<18531> A_IWL<18530> A_IWL<18529> A_IWL<18528> A_IWL<18527> A_IWL<18526> A_IWL<18525> A_IWL<18524> A_IWL<18523> A_IWL<18522> A_IWL<18521> A_IWL<18520> A_IWL<18519> A_IWL<18518> A_IWL<18517> A_IWL<18516> A_IWL<18515> A_IWL<18514> A_IWL<18513> A_IWL<18512> A_IWL<18511> A_IWL<18510> A_IWL<18509> A_IWL<18508> A_IWL<18507> A_IWL<18506> A_IWL<18505> A_IWL<18504> A_IWL<18503> A_IWL<18502> A_IWL<18501> A_IWL<18500> A_IWL<18499> A_IWL<18498> A_IWL<18497> A_IWL<18496> A_IWL<18495> A_IWL<18494> A_IWL<18493> A_IWL<18492> A_IWL<18491> A_IWL<18490> A_IWL<18489> A_IWL<18488> A_IWL<18487> A_IWL<18486> A_IWL<18485> A_IWL<18484> A_IWL<18483> A_IWL<18482> A_IWL<18481> A_IWL<18480> A_IWL<18479> A_IWL<18478> A_IWL<18477> A_IWL<18476> A_IWL<18475> A_IWL<18474> A_IWL<18473> A_IWL<18472> A_IWL<18471> A_IWL<18470> A_IWL<18469> A_IWL<18468> A_IWL<18467> A_IWL<18466> A_IWL<18465> A_IWL<18464> A_IWL<18463> A_IWL<18462> A_IWL<18461> A_IWL<18460> A_IWL<18459> A_IWL<18458> A_IWL<18457> A_IWL<18456> A_IWL<18455> A_IWL<18454> A_IWL<18453> A_IWL<18452> A_IWL<18451> A_IWL<18450> A_IWL<18449> A_IWL<18448> A_IWL<18447> A_IWL<18446> A_IWL<18445> A_IWL<18444> A_IWL<18443> A_IWL<18442> A_IWL<18441> A_IWL<18440> A_IWL<18439> A_IWL<18438> A_IWL<18437> A_IWL<18436> A_IWL<18435> A_IWL<18434> A_IWL<18433> A_IWL<18432> A_IWL<19455> A_IWL<19454> A_IWL<19453> A_IWL<19452> A_IWL<19451> A_IWL<19450> A_IWL<19449> A_IWL<19448> A_IWL<19447> A_IWL<19446> A_IWL<19445> A_IWL<19444> A_IWL<19443> A_IWL<19442> A_IWL<19441> A_IWL<19440> A_IWL<19439> A_IWL<19438> A_IWL<19437> A_IWL<19436> A_IWL<19435> A_IWL<19434> A_IWL<19433> A_IWL<19432> A_IWL<19431> A_IWL<19430> A_IWL<19429> A_IWL<19428> A_IWL<19427> A_IWL<19426> A_IWL<19425> A_IWL<19424> A_IWL<19423> A_IWL<19422> A_IWL<19421> A_IWL<19420> A_IWL<19419> A_IWL<19418> A_IWL<19417> A_IWL<19416> A_IWL<19415> A_IWL<19414> A_IWL<19413> A_IWL<19412> A_IWL<19411> A_IWL<19410> A_IWL<19409> A_IWL<19408> A_IWL<19407> A_IWL<19406> A_IWL<19405> A_IWL<19404> A_IWL<19403> A_IWL<19402> A_IWL<19401> A_IWL<19400> A_IWL<19399> A_IWL<19398> A_IWL<19397> A_IWL<19396> A_IWL<19395> A_IWL<19394> A_IWL<19393> A_IWL<19392> A_IWL<19391> A_IWL<19390> A_IWL<19389> A_IWL<19388> A_IWL<19387> A_IWL<19386> A_IWL<19385> A_IWL<19384> A_IWL<19383> A_IWL<19382> A_IWL<19381> A_IWL<19380> A_IWL<19379> A_IWL<19378> A_IWL<19377> A_IWL<19376> A_IWL<19375> A_IWL<19374> A_IWL<19373> A_IWL<19372> A_IWL<19371> A_IWL<19370> A_IWL<19369> A_IWL<19368> A_IWL<19367> A_IWL<19366> A_IWL<19365> A_IWL<19364> A_IWL<19363> A_IWL<19362> A_IWL<19361> A_IWL<19360> A_IWL<19359> A_IWL<19358> A_IWL<19357> A_IWL<19356> A_IWL<19355> A_IWL<19354> A_IWL<19353> A_IWL<19352> A_IWL<19351> A_IWL<19350> A_IWL<19349> A_IWL<19348> A_IWL<19347> A_IWL<19346> A_IWL<19345> A_IWL<19344> A_IWL<19343> A_IWL<19342> A_IWL<19341> A_IWL<19340> A_IWL<19339> A_IWL<19338> A_IWL<19337> A_IWL<19336> A_IWL<19335> A_IWL<19334> A_IWL<19333> A_IWL<19332> A_IWL<19331> A_IWL<19330> A_IWL<19329> A_IWL<19328> A_IWL<19327> A_IWL<19326> A_IWL<19325> A_IWL<19324> A_IWL<19323> A_IWL<19322> A_IWL<19321> A_IWL<19320> A_IWL<19319> A_IWL<19318> A_IWL<19317> A_IWL<19316> A_IWL<19315> A_IWL<19314> A_IWL<19313> A_IWL<19312> A_IWL<19311> A_IWL<19310> A_IWL<19309> A_IWL<19308> A_IWL<19307> A_IWL<19306> A_IWL<19305> A_IWL<19304> A_IWL<19303> A_IWL<19302> A_IWL<19301> A_IWL<19300> A_IWL<19299> A_IWL<19298> A_IWL<19297> A_IWL<19296> A_IWL<19295> A_IWL<19294> A_IWL<19293> A_IWL<19292> A_IWL<19291> A_IWL<19290> A_IWL<19289> A_IWL<19288> A_IWL<19287> A_IWL<19286> A_IWL<19285> A_IWL<19284> A_IWL<19283> A_IWL<19282> A_IWL<19281> A_IWL<19280> A_IWL<19279> A_IWL<19278> A_IWL<19277> A_IWL<19276> A_IWL<19275> A_IWL<19274> A_IWL<19273> A_IWL<19272> A_IWL<19271> A_IWL<19270> A_IWL<19269> A_IWL<19268> A_IWL<19267> A_IWL<19266> A_IWL<19265> A_IWL<19264> A_IWL<19263> A_IWL<19262> A_IWL<19261> A_IWL<19260> A_IWL<19259> A_IWL<19258> A_IWL<19257> A_IWL<19256> A_IWL<19255> A_IWL<19254> A_IWL<19253> A_IWL<19252> A_IWL<19251> A_IWL<19250> A_IWL<19249> A_IWL<19248> A_IWL<19247> A_IWL<19246> A_IWL<19245> A_IWL<19244> A_IWL<19243> A_IWL<19242> A_IWL<19241> A_IWL<19240> A_IWL<19239> A_IWL<19238> A_IWL<19237> A_IWL<19236> A_IWL<19235> A_IWL<19234> A_IWL<19233> A_IWL<19232> A_IWL<19231> A_IWL<19230> A_IWL<19229> A_IWL<19228> A_IWL<19227> A_IWL<19226> A_IWL<19225> A_IWL<19224> A_IWL<19223> A_IWL<19222> A_IWL<19221> A_IWL<19220> A_IWL<19219> A_IWL<19218> A_IWL<19217> A_IWL<19216> A_IWL<19215> A_IWL<19214> A_IWL<19213> A_IWL<19212> A_IWL<19211> A_IWL<19210> A_IWL<19209> A_IWL<19208> A_IWL<19207> A_IWL<19206> A_IWL<19205> A_IWL<19204> A_IWL<19203> A_IWL<19202> A_IWL<19201> A_IWL<19200> A_IWL<19199> A_IWL<19198> A_IWL<19197> A_IWL<19196> A_IWL<19195> A_IWL<19194> A_IWL<19193> A_IWL<19192> A_IWL<19191> A_IWL<19190> A_IWL<19189> A_IWL<19188> A_IWL<19187> A_IWL<19186> A_IWL<19185> A_IWL<19184> A_IWL<19183> A_IWL<19182> A_IWL<19181> A_IWL<19180> A_IWL<19179> A_IWL<19178> A_IWL<19177> A_IWL<19176> A_IWL<19175> A_IWL<19174> A_IWL<19173> A_IWL<19172> A_IWL<19171> A_IWL<19170> A_IWL<19169> A_IWL<19168> A_IWL<19167> A_IWL<19166> A_IWL<19165> A_IWL<19164> A_IWL<19163> A_IWL<19162> A_IWL<19161> A_IWL<19160> A_IWL<19159> A_IWL<19158> A_IWL<19157> A_IWL<19156> A_IWL<19155> A_IWL<19154> A_IWL<19153> A_IWL<19152> A_IWL<19151> A_IWL<19150> A_IWL<19149> A_IWL<19148> A_IWL<19147> A_IWL<19146> A_IWL<19145> A_IWL<19144> A_IWL<19143> A_IWL<19142> A_IWL<19141> A_IWL<19140> A_IWL<19139> A_IWL<19138> A_IWL<19137> A_IWL<19136> A_IWL<19135> A_IWL<19134> A_IWL<19133> A_IWL<19132> A_IWL<19131> A_IWL<19130> A_IWL<19129> A_IWL<19128> A_IWL<19127> A_IWL<19126> A_IWL<19125> A_IWL<19124> A_IWL<19123> A_IWL<19122> A_IWL<19121> A_IWL<19120> A_IWL<19119> A_IWL<19118> A_IWL<19117> A_IWL<19116> A_IWL<19115> A_IWL<19114> A_IWL<19113> A_IWL<19112> A_IWL<19111> A_IWL<19110> A_IWL<19109> A_IWL<19108> A_IWL<19107> A_IWL<19106> A_IWL<19105> A_IWL<19104> A_IWL<19103> A_IWL<19102> A_IWL<19101> A_IWL<19100> A_IWL<19099> A_IWL<19098> A_IWL<19097> A_IWL<19096> A_IWL<19095> A_IWL<19094> A_IWL<19093> A_IWL<19092> A_IWL<19091> A_IWL<19090> A_IWL<19089> A_IWL<19088> A_IWL<19087> A_IWL<19086> A_IWL<19085> A_IWL<19084> A_IWL<19083> A_IWL<19082> A_IWL<19081> A_IWL<19080> A_IWL<19079> A_IWL<19078> A_IWL<19077> A_IWL<19076> A_IWL<19075> A_IWL<19074> A_IWL<19073> A_IWL<19072> A_IWL<19071> A_IWL<19070> A_IWL<19069> A_IWL<19068> A_IWL<19067> A_IWL<19066> A_IWL<19065> A_IWL<19064> A_IWL<19063> A_IWL<19062> A_IWL<19061> A_IWL<19060> A_IWL<19059> A_IWL<19058> A_IWL<19057> A_IWL<19056> A_IWL<19055> A_IWL<19054> A_IWL<19053> A_IWL<19052> A_IWL<19051> A_IWL<19050> A_IWL<19049> A_IWL<19048> A_IWL<19047> A_IWL<19046> A_IWL<19045> A_IWL<19044> A_IWL<19043> A_IWL<19042> A_IWL<19041> A_IWL<19040> A_IWL<19039> A_IWL<19038> A_IWL<19037> A_IWL<19036> A_IWL<19035> A_IWL<19034> A_IWL<19033> A_IWL<19032> A_IWL<19031> A_IWL<19030> A_IWL<19029> A_IWL<19028> A_IWL<19027> A_IWL<19026> A_IWL<19025> A_IWL<19024> A_IWL<19023> A_IWL<19022> A_IWL<19021> A_IWL<19020> A_IWL<19019> A_IWL<19018> A_IWL<19017> A_IWL<19016> A_IWL<19015> A_IWL<19014> A_IWL<19013> A_IWL<19012> A_IWL<19011> A_IWL<19010> A_IWL<19009> A_IWL<19008> A_IWL<19007> A_IWL<19006> A_IWL<19005> A_IWL<19004> A_IWL<19003> A_IWL<19002> A_IWL<19001> A_IWL<19000> A_IWL<18999> A_IWL<18998> A_IWL<18997> A_IWL<18996> A_IWL<18995> A_IWL<18994> A_IWL<18993> A_IWL<18992> A_IWL<18991> A_IWL<18990> A_IWL<18989> A_IWL<18988> A_IWL<18987> A_IWL<18986> A_IWL<18985> A_IWL<18984> A_IWL<18983> A_IWL<18982> A_IWL<18981> A_IWL<18980> A_IWL<18979> A_IWL<18978> A_IWL<18977> A_IWL<18976> A_IWL<18975> A_IWL<18974> A_IWL<18973> A_IWL<18972> A_IWL<18971> A_IWL<18970> A_IWL<18969> A_IWL<18968> A_IWL<18967> A_IWL<18966> A_IWL<18965> A_IWL<18964> A_IWL<18963> A_IWL<18962> A_IWL<18961> A_IWL<18960> A_IWL<18959> A_IWL<18958> A_IWL<18957> A_IWL<18956> A_IWL<18955> A_IWL<18954> A_IWL<18953> A_IWL<18952> A_IWL<18951> A_IWL<18950> A_IWL<18949> A_IWL<18948> A_IWL<18947> A_IWL<18946> A_IWL<18945> A_IWL<18944> VDD_CORE VSS / RM_IHPSG13_8192x32_c4_1P_COLUMN_pcell_0 +XCOL<36> A_BLC<73> A_BLC<72> A_BLC_TOP<73> A_BLC_TOP<72> A_BLT<73> A_BLT<72> A_BLT_TOP<73> A_BLT_TOP<72> A_IWL<18431> A_IWL<18430> A_IWL<18429> A_IWL<18428> A_IWL<18427> A_IWL<18426> A_IWL<18425> A_IWL<18424> A_IWL<18423> A_IWL<18422> A_IWL<18421> A_IWL<18420> A_IWL<18419> A_IWL<18418> A_IWL<18417> A_IWL<18416> A_IWL<18415> A_IWL<18414> A_IWL<18413> A_IWL<18412> A_IWL<18411> A_IWL<18410> A_IWL<18409> A_IWL<18408> A_IWL<18407> A_IWL<18406> A_IWL<18405> A_IWL<18404> A_IWL<18403> A_IWL<18402> A_IWL<18401> A_IWL<18400> A_IWL<18399> A_IWL<18398> A_IWL<18397> A_IWL<18396> A_IWL<18395> A_IWL<18394> A_IWL<18393> A_IWL<18392> A_IWL<18391> A_IWL<18390> A_IWL<18389> A_IWL<18388> A_IWL<18387> A_IWL<18386> A_IWL<18385> A_IWL<18384> A_IWL<18383> A_IWL<18382> A_IWL<18381> A_IWL<18380> A_IWL<18379> A_IWL<18378> A_IWL<18377> A_IWL<18376> A_IWL<18375> A_IWL<18374> A_IWL<18373> A_IWL<18372> A_IWL<18371> A_IWL<18370> A_IWL<18369> A_IWL<18368> A_IWL<18367> A_IWL<18366> A_IWL<18365> A_IWL<18364> A_IWL<18363> A_IWL<18362> A_IWL<18361> A_IWL<18360> A_IWL<18359> A_IWL<18358> A_IWL<18357> A_IWL<18356> A_IWL<18355> A_IWL<18354> A_IWL<18353> A_IWL<18352> A_IWL<18351> A_IWL<18350> A_IWL<18349> A_IWL<18348> A_IWL<18347> A_IWL<18346> A_IWL<18345> A_IWL<18344> A_IWL<18343> A_IWL<18342> A_IWL<18341> A_IWL<18340> A_IWL<18339> A_IWL<18338> A_IWL<18337> A_IWL<18336> A_IWL<18335> A_IWL<18334> A_IWL<18333> A_IWL<18332> A_IWL<18331> A_IWL<18330> A_IWL<18329> A_IWL<18328> A_IWL<18327> A_IWL<18326> A_IWL<18325> A_IWL<18324> A_IWL<18323> A_IWL<18322> A_IWL<18321> A_IWL<18320> A_IWL<18319> A_IWL<18318> A_IWL<18317> A_IWL<18316> A_IWL<18315> A_IWL<18314> A_IWL<18313> A_IWL<18312> A_IWL<18311> A_IWL<18310> A_IWL<18309> A_IWL<18308> A_IWL<18307> A_IWL<18306> A_IWL<18305> A_IWL<18304> A_IWL<18303> A_IWL<18302> A_IWL<18301> A_IWL<18300> A_IWL<18299> A_IWL<18298> A_IWL<18297> A_IWL<18296> A_IWL<18295> A_IWL<18294> A_IWL<18293> A_IWL<18292> A_IWL<18291> A_IWL<18290> A_IWL<18289> A_IWL<18288> A_IWL<18287> A_IWL<18286> A_IWL<18285> A_IWL<18284> A_IWL<18283> A_IWL<18282> A_IWL<18281> A_IWL<18280> A_IWL<18279> A_IWL<18278> A_IWL<18277> A_IWL<18276> A_IWL<18275> A_IWL<18274> A_IWL<18273> A_IWL<18272> A_IWL<18271> A_IWL<18270> A_IWL<18269> A_IWL<18268> A_IWL<18267> A_IWL<18266> A_IWL<18265> A_IWL<18264> A_IWL<18263> A_IWL<18262> A_IWL<18261> A_IWL<18260> A_IWL<18259> A_IWL<18258> A_IWL<18257> A_IWL<18256> A_IWL<18255> A_IWL<18254> A_IWL<18253> A_IWL<18252> A_IWL<18251> A_IWL<18250> A_IWL<18249> A_IWL<18248> A_IWL<18247> A_IWL<18246> A_IWL<18245> A_IWL<18244> A_IWL<18243> A_IWL<18242> A_IWL<18241> A_IWL<18240> A_IWL<18239> A_IWL<18238> A_IWL<18237> A_IWL<18236> A_IWL<18235> A_IWL<18234> A_IWL<18233> A_IWL<18232> A_IWL<18231> A_IWL<18230> A_IWL<18229> A_IWL<18228> A_IWL<18227> A_IWL<18226> A_IWL<18225> A_IWL<18224> A_IWL<18223> A_IWL<18222> A_IWL<18221> A_IWL<18220> A_IWL<18219> A_IWL<18218> A_IWL<18217> A_IWL<18216> A_IWL<18215> A_IWL<18214> A_IWL<18213> A_IWL<18212> A_IWL<18211> A_IWL<18210> A_IWL<18209> A_IWL<18208> A_IWL<18207> A_IWL<18206> A_IWL<18205> A_IWL<18204> A_IWL<18203> A_IWL<18202> A_IWL<18201> A_IWL<18200> A_IWL<18199> A_IWL<18198> A_IWL<18197> A_IWL<18196> A_IWL<18195> A_IWL<18194> A_IWL<18193> A_IWL<18192> A_IWL<18191> A_IWL<18190> A_IWL<18189> A_IWL<18188> A_IWL<18187> A_IWL<18186> A_IWL<18185> A_IWL<18184> A_IWL<18183> A_IWL<18182> A_IWL<18181> A_IWL<18180> A_IWL<18179> A_IWL<18178> A_IWL<18177> A_IWL<18176> A_IWL<18175> A_IWL<18174> A_IWL<18173> A_IWL<18172> A_IWL<18171> A_IWL<18170> A_IWL<18169> A_IWL<18168> A_IWL<18167> A_IWL<18166> A_IWL<18165> A_IWL<18164> A_IWL<18163> A_IWL<18162> A_IWL<18161> A_IWL<18160> A_IWL<18159> A_IWL<18158> A_IWL<18157> A_IWL<18156> A_IWL<18155> A_IWL<18154> A_IWL<18153> A_IWL<18152> A_IWL<18151> A_IWL<18150> A_IWL<18149> A_IWL<18148> A_IWL<18147> A_IWL<18146> A_IWL<18145> A_IWL<18144> A_IWL<18143> A_IWL<18142> A_IWL<18141> A_IWL<18140> A_IWL<18139> A_IWL<18138> A_IWL<18137> A_IWL<18136> A_IWL<18135> A_IWL<18134> A_IWL<18133> A_IWL<18132> A_IWL<18131> A_IWL<18130> A_IWL<18129> A_IWL<18128> A_IWL<18127> A_IWL<18126> A_IWL<18125> A_IWL<18124> A_IWL<18123> A_IWL<18122> A_IWL<18121> A_IWL<18120> A_IWL<18119> A_IWL<18118> A_IWL<18117> A_IWL<18116> A_IWL<18115> A_IWL<18114> A_IWL<18113> A_IWL<18112> A_IWL<18111> A_IWL<18110> A_IWL<18109> A_IWL<18108> A_IWL<18107> A_IWL<18106> A_IWL<18105> A_IWL<18104> A_IWL<18103> A_IWL<18102> A_IWL<18101> A_IWL<18100> A_IWL<18099> A_IWL<18098> A_IWL<18097> A_IWL<18096> A_IWL<18095> A_IWL<18094> A_IWL<18093> A_IWL<18092> A_IWL<18091> A_IWL<18090> A_IWL<18089> A_IWL<18088> A_IWL<18087> A_IWL<18086> A_IWL<18085> A_IWL<18084> A_IWL<18083> A_IWL<18082> A_IWL<18081> A_IWL<18080> A_IWL<18079> A_IWL<18078> A_IWL<18077> A_IWL<18076> A_IWL<18075> A_IWL<18074> A_IWL<18073> A_IWL<18072> A_IWL<18071> A_IWL<18070> A_IWL<18069> A_IWL<18068> A_IWL<18067> A_IWL<18066> A_IWL<18065> A_IWL<18064> A_IWL<18063> A_IWL<18062> A_IWL<18061> A_IWL<18060> A_IWL<18059> A_IWL<18058> A_IWL<18057> A_IWL<18056> A_IWL<18055> A_IWL<18054> A_IWL<18053> A_IWL<18052> A_IWL<18051> A_IWL<18050> A_IWL<18049> A_IWL<18048> A_IWL<18047> A_IWL<18046> A_IWL<18045> A_IWL<18044> A_IWL<18043> A_IWL<18042> A_IWL<18041> A_IWL<18040> A_IWL<18039> A_IWL<18038> A_IWL<18037> A_IWL<18036> A_IWL<18035> A_IWL<18034> A_IWL<18033> A_IWL<18032> A_IWL<18031> A_IWL<18030> A_IWL<18029> A_IWL<18028> A_IWL<18027> A_IWL<18026> A_IWL<18025> A_IWL<18024> A_IWL<18023> A_IWL<18022> A_IWL<18021> A_IWL<18020> A_IWL<18019> A_IWL<18018> A_IWL<18017> A_IWL<18016> A_IWL<18015> A_IWL<18014> A_IWL<18013> A_IWL<18012> A_IWL<18011> A_IWL<18010> A_IWL<18009> A_IWL<18008> A_IWL<18007> A_IWL<18006> A_IWL<18005> A_IWL<18004> A_IWL<18003> A_IWL<18002> A_IWL<18001> A_IWL<18000> A_IWL<17999> A_IWL<17998> A_IWL<17997> A_IWL<17996> A_IWL<17995> A_IWL<17994> A_IWL<17993> A_IWL<17992> A_IWL<17991> A_IWL<17990> A_IWL<17989> A_IWL<17988> A_IWL<17987> A_IWL<17986> A_IWL<17985> A_IWL<17984> A_IWL<17983> A_IWL<17982> A_IWL<17981> A_IWL<17980> A_IWL<17979> A_IWL<17978> A_IWL<17977> A_IWL<17976> A_IWL<17975> A_IWL<17974> A_IWL<17973> A_IWL<17972> A_IWL<17971> A_IWL<17970> A_IWL<17969> A_IWL<17968> A_IWL<17967> A_IWL<17966> A_IWL<17965> A_IWL<17964> A_IWL<17963> A_IWL<17962> A_IWL<17961> A_IWL<17960> A_IWL<17959> A_IWL<17958> A_IWL<17957> A_IWL<17956> A_IWL<17955> A_IWL<17954> A_IWL<17953> A_IWL<17952> A_IWL<17951> A_IWL<17950> A_IWL<17949> A_IWL<17948> A_IWL<17947> A_IWL<17946> A_IWL<17945> A_IWL<17944> A_IWL<17943> A_IWL<17942> A_IWL<17941> A_IWL<17940> A_IWL<17939> A_IWL<17938> A_IWL<17937> A_IWL<17936> A_IWL<17935> A_IWL<17934> A_IWL<17933> A_IWL<17932> A_IWL<17931> A_IWL<17930> A_IWL<17929> A_IWL<17928> A_IWL<17927> A_IWL<17926> A_IWL<17925> A_IWL<17924> A_IWL<17923> A_IWL<17922> A_IWL<17921> A_IWL<17920> A_IWL<18943> A_IWL<18942> A_IWL<18941> A_IWL<18940> A_IWL<18939> A_IWL<18938> A_IWL<18937> A_IWL<18936> A_IWL<18935> A_IWL<18934> A_IWL<18933> A_IWL<18932> A_IWL<18931> A_IWL<18930> A_IWL<18929> A_IWL<18928> A_IWL<18927> A_IWL<18926> A_IWL<18925> A_IWL<18924> A_IWL<18923> A_IWL<18922> A_IWL<18921> A_IWL<18920> A_IWL<18919> A_IWL<18918> A_IWL<18917> A_IWL<18916> A_IWL<18915> A_IWL<18914> A_IWL<18913> A_IWL<18912> A_IWL<18911> A_IWL<18910> A_IWL<18909> A_IWL<18908> A_IWL<18907> A_IWL<18906> A_IWL<18905> A_IWL<18904> A_IWL<18903> A_IWL<18902> A_IWL<18901> A_IWL<18900> A_IWL<18899> A_IWL<18898> A_IWL<18897> A_IWL<18896> A_IWL<18895> A_IWL<18894> A_IWL<18893> A_IWL<18892> A_IWL<18891> A_IWL<18890> A_IWL<18889> A_IWL<18888> A_IWL<18887> A_IWL<18886> A_IWL<18885> A_IWL<18884> A_IWL<18883> A_IWL<18882> A_IWL<18881> A_IWL<18880> A_IWL<18879> A_IWL<18878> A_IWL<18877> A_IWL<18876> A_IWL<18875> A_IWL<18874> A_IWL<18873> A_IWL<18872> A_IWL<18871> A_IWL<18870> A_IWL<18869> A_IWL<18868> A_IWL<18867> A_IWL<18866> A_IWL<18865> A_IWL<18864> A_IWL<18863> A_IWL<18862> A_IWL<18861> A_IWL<18860> A_IWL<18859> A_IWL<18858> A_IWL<18857> A_IWL<18856> A_IWL<18855> A_IWL<18854> A_IWL<18853> A_IWL<18852> A_IWL<18851> A_IWL<18850> A_IWL<18849> A_IWL<18848> A_IWL<18847> A_IWL<18846> A_IWL<18845> A_IWL<18844> A_IWL<18843> A_IWL<18842> A_IWL<18841> A_IWL<18840> A_IWL<18839> A_IWL<18838> A_IWL<18837> A_IWL<18836> A_IWL<18835> A_IWL<18834> A_IWL<18833> A_IWL<18832> A_IWL<18831> A_IWL<18830> A_IWL<18829> A_IWL<18828> A_IWL<18827> A_IWL<18826> A_IWL<18825> A_IWL<18824> A_IWL<18823> A_IWL<18822> A_IWL<18821> A_IWL<18820> A_IWL<18819> A_IWL<18818> A_IWL<18817> A_IWL<18816> A_IWL<18815> A_IWL<18814> A_IWL<18813> A_IWL<18812> A_IWL<18811> A_IWL<18810> A_IWL<18809> A_IWL<18808> A_IWL<18807> A_IWL<18806> A_IWL<18805> A_IWL<18804> A_IWL<18803> A_IWL<18802> A_IWL<18801> A_IWL<18800> A_IWL<18799> A_IWL<18798> A_IWL<18797> A_IWL<18796> A_IWL<18795> A_IWL<18794> A_IWL<18793> A_IWL<18792> A_IWL<18791> A_IWL<18790> A_IWL<18789> A_IWL<18788> A_IWL<18787> A_IWL<18786> A_IWL<18785> A_IWL<18784> A_IWL<18783> A_IWL<18782> A_IWL<18781> A_IWL<18780> A_IWL<18779> A_IWL<18778> A_IWL<18777> A_IWL<18776> A_IWL<18775> A_IWL<18774> A_IWL<18773> A_IWL<18772> A_IWL<18771> A_IWL<18770> A_IWL<18769> A_IWL<18768> A_IWL<18767> A_IWL<18766> A_IWL<18765> A_IWL<18764> A_IWL<18763> A_IWL<18762> A_IWL<18761> A_IWL<18760> A_IWL<18759> A_IWL<18758> A_IWL<18757> A_IWL<18756> A_IWL<18755> A_IWL<18754> A_IWL<18753> A_IWL<18752> A_IWL<18751> A_IWL<18750> A_IWL<18749> A_IWL<18748> A_IWL<18747> A_IWL<18746> A_IWL<18745> A_IWL<18744> A_IWL<18743> A_IWL<18742> A_IWL<18741> A_IWL<18740> A_IWL<18739> A_IWL<18738> A_IWL<18737> A_IWL<18736> A_IWL<18735> A_IWL<18734> A_IWL<18733> A_IWL<18732> A_IWL<18731> A_IWL<18730> A_IWL<18729> A_IWL<18728> A_IWL<18727> A_IWL<18726> A_IWL<18725> A_IWL<18724> A_IWL<18723> A_IWL<18722> A_IWL<18721> A_IWL<18720> A_IWL<18719> A_IWL<18718> A_IWL<18717> A_IWL<18716> A_IWL<18715> A_IWL<18714> A_IWL<18713> A_IWL<18712> A_IWL<18711> A_IWL<18710> A_IWL<18709> A_IWL<18708> A_IWL<18707> A_IWL<18706> A_IWL<18705> A_IWL<18704> A_IWL<18703> A_IWL<18702> A_IWL<18701> A_IWL<18700> A_IWL<18699> A_IWL<18698> A_IWL<18697> A_IWL<18696> A_IWL<18695> A_IWL<18694> A_IWL<18693> A_IWL<18692> A_IWL<18691> A_IWL<18690> A_IWL<18689> A_IWL<18688> A_IWL<18687> A_IWL<18686> A_IWL<18685> A_IWL<18684> A_IWL<18683> A_IWL<18682> A_IWL<18681> A_IWL<18680> A_IWL<18679> A_IWL<18678> A_IWL<18677> A_IWL<18676> A_IWL<18675> A_IWL<18674> A_IWL<18673> A_IWL<18672> A_IWL<18671> A_IWL<18670> A_IWL<18669> A_IWL<18668> A_IWL<18667> A_IWL<18666> A_IWL<18665> A_IWL<18664> A_IWL<18663> A_IWL<18662> A_IWL<18661> A_IWL<18660> A_IWL<18659> A_IWL<18658> A_IWL<18657> A_IWL<18656> A_IWL<18655> A_IWL<18654> A_IWL<18653> A_IWL<18652> A_IWL<18651> A_IWL<18650> A_IWL<18649> A_IWL<18648> A_IWL<18647> A_IWL<18646> A_IWL<18645> A_IWL<18644> A_IWL<18643> A_IWL<18642> A_IWL<18641> A_IWL<18640> A_IWL<18639> A_IWL<18638> A_IWL<18637> A_IWL<18636> A_IWL<18635> A_IWL<18634> A_IWL<18633> A_IWL<18632> A_IWL<18631> A_IWL<18630> A_IWL<18629> A_IWL<18628> A_IWL<18627> A_IWL<18626> A_IWL<18625> A_IWL<18624> A_IWL<18623> A_IWL<18622> A_IWL<18621> A_IWL<18620> A_IWL<18619> A_IWL<18618> A_IWL<18617> A_IWL<18616> A_IWL<18615> A_IWL<18614> A_IWL<18613> A_IWL<18612> A_IWL<18611> A_IWL<18610> A_IWL<18609> A_IWL<18608> A_IWL<18607> A_IWL<18606> A_IWL<18605> A_IWL<18604> A_IWL<18603> A_IWL<18602> A_IWL<18601> A_IWL<18600> A_IWL<18599> A_IWL<18598> A_IWL<18597> A_IWL<18596> A_IWL<18595> A_IWL<18594> A_IWL<18593> A_IWL<18592> A_IWL<18591> A_IWL<18590> A_IWL<18589> A_IWL<18588> A_IWL<18587> A_IWL<18586> A_IWL<18585> A_IWL<18584> A_IWL<18583> A_IWL<18582> A_IWL<18581> A_IWL<18580> A_IWL<18579> A_IWL<18578> A_IWL<18577> A_IWL<18576> A_IWL<18575> A_IWL<18574> A_IWL<18573> A_IWL<18572> A_IWL<18571> A_IWL<18570> A_IWL<18569> A_IWL<18568> A_IWL<18567> A_IWL<18566> A_IWL<18565> A_IWL<18564> A_IWL<18563> A_IWL<18562> A_IWL<18561> A_IWL<18560> A_IWL<18559> A_IWL<18558> A_IWL<18557> A_IWL<18556> A_IWL<18555> A_IWL<18554> A_IWL<18553> A_IWL<18552> A_IWL<18551> A_IWL<18550> A_IWL<18549> A_IWL<18548> A_IWL<18547> A_IWL<18546> A_IWL<18545> A_IWL<18544> A_IWL<18543> A_IWL<18542> A_IWL<18541> A_IWL<18540> A_IWL<18539> A_IWL<18538> A_IWL<18537> A_IWL<18536> A_IWL<18535> A_IWL<18534> A_IWL<18533> A_IWL<18532> A_IWL<18531> A_IWL<18530> A_IWL<18529> A_IWL<18528> A_IWL<18527> A_IWL<18526> A_IWL<18525> A_IWL<18524> A_IWL<18523> A_IWL<18522> A_IWL<18521> A_IWL<18520> A_IWL<18519> A_IWL<18518> A_IWL<18517> A_IWL<18516> A_IWL<18515> A_IWL<18514> A_IWL<18513> A_IWL<18512> A_IWL<18511> A_IWL<18510> A_IWL<18509> A_IWL<18508> A_IWL<18507> A_IWL<18506> A_IWL<18505> A_IWL<18504> A_IWL<18503> A_IWL<18502> A_IWL<18501> A_IWL<18500> A_IWL<18499> A_IWL<18498> A_IWL<18497> A_IWL<18496> A_IWL<18495> A_IWL<18494> A_IWL<18493> A_IWL<18492> A_IWL<18491> A_IWL<18490> A_IWL<18489> A_IWL<18488> A_IWL<18487> A_IWL<18486> A_IWL<18485> A_IWL<18484> A_IWL<18483> A_IWL<18482> A_IWL<18481> A_IWL<18480> A_IWL<18479> A_IWL<18478> A_IWL<18477> A_IWL<18476> A_IWL<18475> A_IWL<18474> A_IWL<18473> A_IWL<18472> A_IWL<18471> A_IWL<18470> A_IWL<18469> A_IWL<18468> A_IWL<18467> A_IWL<18466> A_IWL<18465> A_IWL<18464> A_IWL<18463> A_IWL<18462> A_IWL<18461> A_IWL<18460> A_IWL<18459> A_IWL<18458> A_IWL<18457> A_IWL<18456> A_IWL<18455> A_IWL<18454> A_IWL<18453> A_IWL<18452> A_IWL<18451> A_IWL<18450> A_IWL<18449> A_IWL<18448> A_IWL<18447> A_IWL<18446> A_IWL<18445> A_IWL<18444> A_IWL<18443> A_IWL<18442> A_IWL<18441> A_IWL<18440> A_IWL<18439> A_IWL<18438> A_IWL<18437> A_IWL<18436> A_IWL<18435> A_IWL<18434> A_IWL<18433> A_IWL<18432> VDD_CORE VSS / RM_IHPSG13_8192x32_c4_1P_COLUMN_pcell_0 +XCOL<35> A_BLC<71> A_BLC<70> A_BLC_TOP<71> A_BLC_TOP<70> A_BLT<71> A_BLT<70> A_BLT_TOP<71> A_BLT_TOP<70> A_IWL<17919> A_IWL<17918> A_IWL<17917> A_IWL<17916> A_IWL<17915> A_IWL<17914> A_IWL<17913> A_IWL<17912> A_IWL<17911> A_IWL<17910> A_IWL<17909> A_IWL<17908> A_IWL<17907> A_IWL<17906> A_IWL<17905> A_IWL<17904> A_IWL<17903> A_IWL<17902> A_IWL<17901> A_IWL<17900> A_IWL<17899> A_IWL<17898> A_IWL<17897> A_IWL<17896> A_IWL<17895> A_IWL<17894> A_IWL<17893> A_IWL<17892> A_IWL<17891> A_IWL<17890> A_IWL<17889> A_IWL<17888> A_IWL<17887> A_IWL<17886> A_IWL<17885> A_IWL<17884> A_IWL<17883> A_IWL<17882> A_IWL<17881> A_IWL<17880> A_IWL<17879> A_IWL<17878> A_IWL<17877> A_IWL<17876> A_IWL<17875> A_IWL<17874> A_IWL<17873> A_IWL<17872> A_IWL<17871> A_IWL<17870> A_IWL<17869> A_IWL<17868> A_IWL<17867> A_IWL<17866> A_IWL<17865> A_IWL<17864> A_IWL<17863> A_IWL<17862> A_IWL<17861> A_IWL<17860> A_IWL<17859> A_IWL<17858> A_IWL<17857> A_IWL<17856> A_IWL<17855> A_IWL<17854> A_IWL<17853> A_IWL<17852> A_IWL<17851> A_IWL<17850> A_IWL<17849> A_IWL<17848> A_IWL<17847> A_IWL<17846> A_IWL<17845> A_IWL<17844> A_IWL<17843> A_IWL<17842> A_IWL<17841> A_IWL<17840> A_IWL<17839> A_IWL<17838> A_IWL<17837> A_IWL<17836> A_IWL<17835> A_IWL<17834> A_IWL<17833> A_IWL<17832> A_IWL<17831> A_IWL<17830> A_IWL<17829> A_IWL<17828> A_IWL<17827> A_IWL<17826> A_IWL<17825> A_IWL<17824> A_IWL<17823> A_IWL<17822> A_IWL<17821> A_IWL<17820> A_IWL<17819> A_IWL<17818> A_IWL<17817> A_IWL<17816> A_IWL<17815> A_IWL<17814> A_IWL<17813> A_IWL<17812> A_IWL<17811> A_IWL<17810> A_IWL<17809> A_IWL<17808> A_IWL<17807> A_IWL<17806> A_IWL<17805> A_IWL<17804> A_IWL<17803> A_IWL<17802> A_IWL<17801> A_IWL<17800> A_IWL<17799> A_IWL<17798> A_IWL<17797> A_IWL<17796> A_IWL<17795> A_IWL<17794> A_IWL<17793> A_IWL<17792> A_IWL<17791> A_IWL<17790> A_IWL<17789> A_IWL<17788> A_IWL<17787> A_IWL<17786> A_IWL<17785> A_IWL<17784> A_IWL<17783> A_IWL<17782> A_IWL<17781> A_IWL<17780> A_IWL<17779> A_IWL<17778> A_IWL<17777> A_IWL<17776> A_IWL<17775> A_IWL<17774> A_IWL<17773> A_IWL<17772> A_IWL<17771> A_IWL<17770> A_IWL<17769> A_IWL<17768> A_IWL<17767> A_IWL<17766> A_IWL<17765> A_IWL<17764> A_IWL<17763> A_IWL<17762> A_IWL<17761> A_IWL<17760> A_IWL<17759> A_IWL<17758> A_IWL<17757> A_IWL<17756> A_IWL<17755> A_IWL<17754> A_IWL<17753> A_IWL<17752> A_IWL<17751> A_IWL<17750> A_IWL<17749> A_IWL<17748> A_IWL<17747> A_IWL<17746> A_IWL<17745> A_IWL<17744> A_IWL<17743> A_IWL<17742> A_IWL<17741> A_IWL<17740> A_IWL<17739> A_IWL<17738> A_IWL<17737> A_IWL<17736> A_IWL<17735> A_IWL<17734> A_IWL<17733> A_IWL<17732> A_IWL<17731> A_IWL<17730> A_IWL<17729> A_IWL<17728> A_IWL<17727> A_IWL<17726> A_IWL<17725> A_IWL<17724> A_IWL<17723> A_IWL<17722> A_IWL<17721> A_IWL<17720> A_IWL<17719> A_IWL<17718> A_IWL<17717> A_IWL<17716> A_IWL<17715> A_IWL<17714> A_IWL<17713> A_IWL<17712> A_IWL<17711> A_IWL<17710> A_IWL<17709> A_IWL<17708> A_IWL<17707> A_IWL<17706> A_IWL<17705> A_IWL<17704> A_IWL<17703> A_IWL<17702> A_IWL<17701> A_IWL<17700> A_IWL<17699> A_IWL<17698> A_IWL<17697> A_IWL<17696> A_IWL<17695> A_IWL<17694> A_IWL<17693> A_IWL<17692> A_IWL<17691> A_IWL<17690> A_IWL<17689> A_IWL<17688> A_IWL<17687> A_IWL<17686> A_IWL<17685> A_IWL<17684> A_IWL<17683> A_IWL<17682> A_IWL<17681> A_IWL<17680> A_IWL<17679> A_IWL<17678> A_IWL<17677> A_IWL<17676> A_IWL<17675> A_IWL<17674> A_IWL<17673> A_IWL<17672> A_IWL<17671> A_IWL<17670> A_IWL<17669> A_IWL<17668> A_IWL<17667> A_IWL<17666> A_IWL<17665> A_IWL<17664> A_IWL<17663> A_IWL<17662> A_IWL<17661> A_IWL<17660> A_IWL<17659> A_IWL<17658> A_IWL<17657> A_IWL<17656> A_IWL<17655> A_IWL<17654> A_IWL<17653> A_IWL<17652> A_IWL<17651> A_IWL<17650> A_IWL<17649> A_IWL<17648> A_IWL<17647> A_IWL<17646> A_IWL<17645> A_IWL<17644> A_IWL<17643> A_IWL<17642> A_IWL<17641> A_IWL<17640> A_IWL<17639> A_IWL<17638> A_IWL<17637> A_IWL<17636> A_IWL<17635> A_IWL<17634> A_IWL<17633> A_IWL<17632> A_IWL<17631> A_IWL<17630> A_IWL<17629> A_IWL<17628> A_IWL<17627> A_IWL<17626> A_IWL<17625> A_IWL<17624> A_IWL<17623> A_IWL<17622> A_IWL<17621> A_IWL<17620> A_IWL<17619> A_IWL<17618> A_IWL<17617> A_IWL<17616> A_IWL<17615> A_IWL<17614> A_IWL<17613> A_IWL<17612> A_IWL<17611> A_IWL<17610> A_IWL<17609> A_IWL<17608> A_IWL<17607> A_IWL<17606> A_IWL<17605> A_IWL<17604> A_IWL<17603> A_IWL<17602> A_IWL<17601> A_IWL<17600> A_IWL<17599> A_IWL<17598> A_IWL<17597> A_IWL<17596> A_IWL<17595> A_IWL<17594> A_IWL<17593> A_IWL<17592> A_IWL<17591> A_IWL<17590> A_IWL<17589> A_IWL<17588> A_IWL<17587> A_IWL<17586> A_IWL<17585> A_IWL<17584> A_IWL<17583> A_IWL<17582> A_IWL<17581> A_IWL<17580> A_IWL<17579> A_IWL<17578> A_IWL<17577> A_IWL<17576> A_IWL<17575> A_IWL<17574> A_IWL<17573> A_IWL<17572> A_IWL<17571> A_IWL<17570> A_IWL<17569> A_IWL<17568> A_IWL<17567> A_IWL<17566> A_IWL<17565> A_IWL<17564> A_IWL<17563> A_IWL<17562> A_IWL<17561> A_IWL<17560> A_IWL<17559> A_IWL<17558> A_IWL<17557> A_IWL<17556> A_IWL<17555> A_IWL<17554> A_IWL<17553> A_IWL<17552> A_IWL<17551> A_IWL<17550> A_IWL<17549> A_IWL<17548> A_IWL<17547> A_IWL<17546> A_IWL<17545> A_IWL<17544> A_IWL<17543> A_IWL<17542> A_IWL<17541> A_IWL<17540> A_IWL<17539> A_IWL<17538> A_IWL<17537> A_IWL<17536> A_IWL<17535> A_IWL<17534> A_IWL<17533> A_IWL<17532> A_IWL<17531> A_IWL<17530> A_IWL<17529> A_IWL<17528> A_IWL<17527> A_IWL<17526> A_IWL<17525> A_IWL<17524> A_IWL<17523> A_IWL<17522> A_IWL<17521> A_IWL<17520> A_IWL<17519> A_IWL<17518> A_IWL<17517> A_IWL<17516> A_IWL<17515> A_IWL<17514> A_IWL<17513> A_IWL<17512> A_IWL<17511> A_IWL<17510> A_IWL<17509> A_IWL<17508> A_IWL<17507> A_IWL<17506> A_IWL<17505> A_IWL<17504> A_IWL<17503> A_IWL<17502> A_IWL<17501> A_IWL<17500> A_IWL<17499> A_IWL<17498> A_IWL<17497> A_IWL<17496> A_IWL<17495> A_IWL<17494> A_IWL<17493> A_IWL<17492> A_IWL<17491> A_IWL<17490> A_IWL<17489> A_IWL<17488> A_IWL<17487> A_IWL<17486> A_IWL<17485> A_IWL<17484> A_IWL<17483> A_IWL<17482> A_IWL<17481> A_IWL<17480> A_IWL<17479> A_IWL<17478> A_IWL<17477> A_IWL<17476> A_IWL<17475> A_IWL<17474> A_IWL<17473> A_IWL<17472> A_IWL<17471> A_IWL<17470> A_IWL<17469> A_IWL<17468> A_IWL<17467> A_IWL<17466> A_IWL<17465> A_IWL<17464> A_IWL<17463> A_IWL<17462> A_IWL<17461> A_IWL<17460> A_IWL<17459> A_IWL<17458> A_IWL<17457> A_IWL<17456> A_IWL<17455> A_IWL<17454> A_IWL<17453> A_IWL<17452> A_IWL<17451> A_IWL<17450> A_IWL<17449> A_IWL<17448> A_IWL<17447> A_IWL<17446> A_IWL<17445> A_IWL<17444> A_IWL<17443> A_IWL<17442> A_IWL<17441> A_IWL<17440> A_IWL<17439> A_IWL<17438> A_IWL<17437> A_IWL<17436> A_IWL<17435> A_IWL<17434> A_IWL<17433> A_IWL<17432> A_IWL<17431> A_IWL<17430> A_IWL<17429> A_IWL<17428> A_IWL<17427> A_IWL<17426> A_IWL<17425> A_IWL<17424> A_IWL<17423> A_IWL<17422> A_IWL<17421> A_IWL<17420> A_IWL<17419> A_IWL<17418> A_IWL<17417> A_IWL<17416> A_IWL<17415> A_IWL<17414> A_IWL<17413> A_IWL<17412> A_IWL<17411> A_IWL<17410> A_IWL<17409> A_IWL<17408> A_IWL<18431> A_IWL<18430> A_IWL<18429> A_IWL<18428> A_IWL<18427> A_IWL<18426> A_IWL<18425> A_IWL<18424> A_IWL<18423> A_IWL<18422> A_IWL<18421> A_IWL<18420> A_IWL<18419> A_IWL<18418> A_IWL<18417> A_IWL<18416> A_IWL<18415> A_IWL<18414> A_IWL<18413> A_IWL<18412> A_IWL<18411> A_IWL<18410> A_IWL<18409> A_IWL<18408> A_IWL<18407> A_IWL<18406> A_IWL<18405> A_IWL<18404> A_IWL<18403> A_IWL<18402> A_IWL<18401> A_IWL<18400> A_IWL<18399> A_IWL<18398> A_IWL<18397> A_IWL<18396> A_IWL<18395> A_IWL<18394> A_IWL<18393> A_IWL<18392> A_IWL<18391> A_IWL<18390> A_IWL<18389> A_IWL<18388> A_IWL<18387> A_IWL<18386> A_IWL<18385> A_IWL<18384> A_IWL<18383> A_IWL<18382> A_IWL<18381> A_IWL<18380> A_IWL<18379> A_IWL<18378> A_IWL<18377> A_IWL<18376> A_IWL<18375> A_IWL<18374> A_IWL<18373> A_IWL<18372> A_IWL<18371> A_IWL<18370> A_IWL<18369> A_IWL<18368> A_IWL<18367> A_IWL<18366> A_IWL<18365> A_IWL<18364> A_IWL<18363> A_IWL<18362> A_IWL<18361> A_IWL<18360> A_IWL<18359> A_IWL<18358> A_IWL<18357> A_IWL<18356> A_IWL<18355> A_IWL<18354> A_IWL<18353> A_IWL<18352> A_IWL<18351> A_IWL<18350> A_IWL<18349> A_IWL<18348> A_IWL<18347> A_IWL<18346> A_IWL<18345> A_IWL<18344> A_IWL<18343> A_IWL<18342> A_IWL<18341> A_IWL<18340> A_IWL<18339> A_IWL<18338> A_IWL<18337> A_IWL<18336> A_IWL<18335> A_IWL<18334> A_IWL<18333> A_IWL<18332> A_IWL<18331> A_IWL<18330> A_IWL<18329> A_IWL<18328> A_IWL<18327> A_IWL<18326> A_IWL<18325> A_IWL<18324> A_IWL<18323> A_IWL<18322> A_IWL<18321> A_IWL<18320> A_IWL<18319> A_IWL<18318> A_IWL<18317> A_IWL<18316> A_IWL<18315> A_IWL<18314> A_IWL<18313> A_IWL<18312> A_IWL<18311> A_IWL<18310> A_IWL<18309> A_IWL<18308> A_IWL<18307> A_IWL<18306> A_IWL<18305> A_IWL<18304> A_IWL<18303> A_IWL<18302> A_IWL<18301> A_IWL<18300> A_IWL<18299> A_IWL<18298> A_IWL<18297> A_IWL<18296> A_IWL<18295> A_IWL<18294> A_IWL<18293> A_IWL<18292> A_IWL<18291> A_IWL<18290> A_IWL<18289> A_IWL<18288> A_IWL<18287> A_IWL<18286> A_IWL<18285> A_IWL<18284> A_IWL<18283> A_IWL<18282> A_IWL<18281> A_IWL<18280> A_IWL<18279> A_IWL<18278> A_IWL<18277> A_IWL<18276> A_IWL<18275> A_IWL<18274> A_IWL<18273> A_IWL<18272> A_IWL<18271> A_IWL<18270> A_IWL<18269> A_IWL<18268> A_IWL<18267> A_IWL<18266> A_IWL<18265> A_IWL<18264> A_IWL<18263> A_IWL<18262> A_IWL<18261> A_IWL<18260> A_IWL<18259> A_IWL<18258> A_IWL<18257> A_IWL<18256> A_IWL<18255> A_IWL<18254> A_IWL<18253> A_IWL<18252> A_IWL<18251> A_IWL<18250> A_IWL<18249> A_IWL<18248> A_IWL<18247> A_IWL<18246> A_IWL<18245> A_IWL<18244> A_IWL<18243> A_IWL<18242> A_IWL<18241> A_IWL<18240> A_IWL<18239> A_IWL<18238> A_IWL<18237> A_IWL<18236> A_IWL<18235> A_IWL<18234> A_IWL<18233> A_IWL<18232> A_IWL<18231> A_IWL<18230> A_IWL<18229> A_IWL<18228> A_IWL<18227> A_IWL<18226> A_IWL<18225> A_IWL<18224> A_IWL<18223> A_IWL<18222> A_IWL<18221> A_IWL<18220> A_IWL<18219> A_IWL<18218> A_IWL<18217> A_IWL<18216> A_IWL<18215> A_IWL<18214> A_IWL<18213> A_IWL<18212> A_IWL<18211> A_IWL<18210> A_IWL<18209> A_IWL<18208> A_IWL<18207> A_IWL<18206> A_IWL<18205> A_IWL<18204> A_IWL<18203> A_IWL<18202> A_IWL<18201> A_IWL<18200> A_IWL<18199> A_IWL<18198> A_IWL<18197> A_IWL<18196> A_IWL<18195> A_IWL<18194> A_IWL<18193> A_IWL<18192> A_IWL<18191> A_IWL<18190> A_IWL<18189> A_IWL<18188> A_IWL<18187> A_IWL<18186> A_IWL<18185> A_IWL<18184> A_IWL<18183> A_IWL<18182> A_IWL<18181> A_IWL<18180> A_IWL<18179> A_IWL<18178> A_IWL<18177> A_IWL<18176> A_IWL<18175> A_IWL<18174> A_IWL<18173> A_IWL<18172> A_IWL<18171> A_IWL<18170> A_IWL<18169> A_IWL<18168> A_IWL<18167> A_IWL<18166> A_IWL<18165> A_IWL<18164> A_IWL<18163> A_IWL<18162> A_IWL<18161> A_IWL<18160> A_IWL<18159> A_IWL<18158> A_IWL<18157> A_IWL<18156> A_IWL<18155> A_IWL<18154> A_IWL<18153> A_IWL<18152> A_IWL<18151> A_IWL<18150> A_IWL<18149> A_IWL<18148> A_IWL<18147> A_IWL<18146> A_IWL<18145> A_IWL<18144> A_IWL<18143> A_IWL<18142> A_IWL<18141> A_IWL<18140> A_IWL<18139> A_IWL<18138> A_IWL<18137> A_IWL<18136> A_IWL<18135> A_IWL<18134> A_IWL<18133> A_IWL<18132> A_IWL<18131> A_IWL<18130> A_IWL<18129> A_IWL<18128> A_IWL<18127> A_IWL<18126> A_IWL<18125> A_IWL<18124> A_IWL<18123> A_IWL<18122> A_IWL<18121> A_IWL<18120> A_IWL<18119> A_IWL<18118> A_IWL<18117> A_IWL<18116> A_IWL<18115> A_IWL<18114> A_IWL<18113> A_IWL<18112> A_IWL<18111> A_IWL<18110> A_IWL<18109> A_IWL<18108> A_IWL<18107> A_IWL<18106> A_IWL<18105> A_IWL<18104> A_IWL<18103> A_IWL<18102> A_IWL<18101> A_IWL<18100> A_IWL<18099> A_IWL<18098> A_IWL<18097> A_IWL<18096> A_IWL<18095> A_IWL<18094> A_IWL<18093> A_IWL<18092> A_IWL<18091> A_IWL<18090> A_IWL<18089> A_IWL<18088> A_IWL<18087> A_IWL<18086> A_IWL<18085> A_IWL<18084> A_IWL<18083> A_IWL<18082> A_IWL<18081> A_IWL<18080> A_IWL<18079> A_IWL<18078> A_IWL<18077> A_IWL<18076> A_IWL<18075> A_IWL<18074> A_IWL<18073> A_IWL<18072> A_IWL<18071> A_IWL<18070> A_IWL<18069> A_IWL<18068> A_IWL<18067> A_IWL<18066> A_IWL<18065> A_IWL<18064> A_IWL<18063> A_IWL<18062> A_IWL<18061> A_IWL<18060> A_IWL<18059> A_IWL<18058> A_IWL<18057> A_IWL<18056> A_IWL<18055> A_IWL<18054> A_IWL<18053> A_IWL<18052> A_IWL<18051> A_IWL<18050> A_IWL<18049> A_IWL<18048> A_IWL<18047> A_IWL<18046> A_IWL<18045> A_IWL<18044> A_IWL<18043> A_IWL<18042> A_IWL<18041> A_IWL<18040> A_IWL<18039> A_IWL<18038> A_IWL<18037> A_IWL<18036> A_IWL<18035> A_IWL<18034> A_IWL<18033> A_IWL<18032> A_IWL<18031> A_IWL<18030> A_IWL<18029> A_IWL<18028> A_IWL<18027> A_IWL<18026> A_IWL<18025> A_IWL<18024> A_IWL<18023> A_IWL<18022> A_IWL<18021> A_IWL<18020> A_IWL<18019> A_IWL<18018> A_IWL<18017> A_IWL<18016> A_IWL<18015> A_IWL<18014> A_IWL<18013> A_IWL<18012> A_IWL<18011> A_IWL<18010> A_IWL<18009> A_IWL<18008> A_IWL<18007> A_IWL<18006> A_IWL<18005> A_IWL<18004> A_IWL<18003> A_IWL<18002> A_IWL<18001> A_IWL<18000> A_IWL<17999> A_IWL<17998> A_IWL<17997> A_IWL<17996> A_IWL<17995> A_IWL<17994> A_IWL<17993> A_IWL<17992> A_IWL<17991> A_IWL<17990> A_IWL<17989> A_IWL<17988> A_IWL<17987> A_IWL<17986> A_IWL<17985> A_IWL<17984> A_IWL<17983> A_IWL<17982> A_IWL<17981> A_IWL<17980> A_IWL<17979> A_IWL<17978> A_IWL<17977> A_IWL<17976> A_IWL<17975> A_IWL<17974> A_IWL<17973> A_IWL<17972> A_IWL<17971> A_IWL<17970> A_IWL<17969> A_IWL<17968> A_IWL<17967> A_IWL<17966> A_IWL<17965> A_IWL<17964> A_IWL<17963> A_IWL<17962> A_IWL<17961> A_IWL<17960> A_IWL<17959> A_IWL<17958> A_IWL<17957> A_IWL<17956> A_IWL<17955> A_IWL<17954> A_IWL<17953> A_IWL<17952> A_IWL<17951> A_IWL<17950> A_IWL<17949> A_IWL<17948> A_IWL<17947> A_IWL<17946> A_IWL<17945> A_IWL<17944> A_IWL<17943> A_IWL<17942> A_IWL<17941> A_IWL<17940> A_IWL<17939> A_IWL<17938> A_IWL<17937> A_IWL<17936> A_IWL<17935> A_IWL<17934> A_IWL<17933> A_IWL<17932> A_IWL<17931> A_IWL<17930> A_IWL<17929> A_IWL<17928> A_IWL<17927> A_IWL<17926> A_IWL<17925> A_IWL<17924> A_IWL<17923> A_IWL<17922> A_IWL<17921> A_IWL<17920> VDD_CORE VSS / RM_IHPSG13_8192x32_c4_1P_COLUMN_pcell_0 +XCOL<34> A_BLC<69> A_BLC<68> A_BLC_TOP<69> A_BLC_TOP<68> A_BLT<69> A_BLT<68> A_BLT_TOP<69> A_BLT_TOP<68> A_IWL<17407> A_IWL<17406> A_IWL<17405> A_IWL<17404> A_IWL<17403> A_IWL<17402> A_IWL<17401> A_IWL<17400> A_IWL<17399> A_IWL<17398> A_IWL<17397> A_IWL<17396> A_IWL<17395> A_IWL<17394> A_IWL<17393> A_IWL<17392> A_IWL<17391> A_IWL<17390> A_IWL<17389> A_IWL<17388> A_IWL<17387> A_IWL<17386> A_IWL<17385> A_IWL<17384> A_IWL<17383> A_IWL<17382> A_IWL<17381> A_IWL<17380> A_IWL<17379> A_IWL<17378> A_IWL<17377> A_IWL<17376> A_IWL<17375> A_IWL<17374> A_IWL<17373> A_IWL<17372> A_IWL<17371> A_IWL<17370> A_IWL<17369> A_IWL<17368> A_IWL<17367> A_IWL<17366> A_IWL<17365> A_IWL<17364> A_IWL<17363> A_IWL<17362> A_IWL<17361> A_IWL<17360> A_IWL<17359> A_IWL<17358> A_IWL<17357> A_IWL<17356> A_IWL<17355> A_IWL<17354> A_IWL<17353> A_IWL<17352> A_IWL<17351> A_IWL<17350> A_IWL<17349> A_IWL<17348> A_IWL<17347> A_IWL<17346> A_IWL<17345> A_IWL<17344> A_IWL<17343> A_IWL<17342> A_IWL<17341> A_IWL<17340> A_IWL<17339> A_IWL<17338> A_IWL<17337> A_IWL<17336> A_IWL<17335> A_IWL<17334> A_IWL<17333> A_IWL<17332> A_IWL<17331> A_IWL<17330> A_IWL<17329> A_IWL<17328> A_IWL<17327> A_IWL<17326> A_IWL<17325> A_IWL<17324> A_IWL<17323> A_IWL<17322> A_IWL<17321> A_IWL<17320> A_IWL<17319> A_IWL<17318> A_IWL<17317> A_IWL<17316> A_IWL<17315> A_IWL<17314> A_IWL<17313> A_IWL<17312> A_IWL<17311> A_IWL<17310> A_IWL<17309> A_IWL<17308> A_IWL<17307> A_IWL<17306> A_IWL<17305> A_IWL<17304> A_IWL<17303> A_IWL<17302> A_IWL<17301> A_IWL<17300> A_IWL<17299> A_IWL<17298> A_IWL<17297> A_IWL<17296> A_IWL<17295> A_IWL<17294> A_IWL<17293> A_IWL<17292> A_IWL<17291> A_IWL<17290> A_IWL<17289> A_IWL<17288> A_IWL<17287> A_IWL<17286> A_IWL<17285> A_IWL<17284> A_IWL<17283> A_IWL<17282> A_IWL<17281> A_IWL<17280> A_IWL<17279> A_IWL<17278> A_IWL<17277> A_IWL<17276> A_IWL<17275> A_IWL<17274> A_IWL<17273> A_IWL<17272> A_IWL<17271> A_IWL<17270> A_IWL<17269> A_IWL<17268> A_IWL<17267> A_IWL<17266> A_IWL<17265> A_IWL<17264> A_IWL<17263> A_IWL<17262> A_IWL<17261> A_IWL<17260> A_IWL<17259> A_IWL<17258> A_IWL<17257> A_IWL<17256> A_IWL<17255> A_IWL<17254> A_IWL<17253> A_IWL<17252> A_IWL<17251> A_IWL<17250> A_IWL<17249> A_IWL<17248> A_IWL<17247> A_IWL<17246> A_IWL<17245> A_IWL<17244> A_IWL<17243> A_IWL<17242> A_IWL<17241> A_IWL<17240> A_IWL<17239> A_IWL<17238> A_IWL<17237> A_IWL<17236> A_IWL<17235> A_IWL<17234> A_IWL<17233> A_IWL<17232> A_IWL<17231> A_IWL<17230> A_IWL<17229> A_IWL<17228> A_IWL<17227> A_IWL<17226> A_IWL<17225> A_IWL<17224> A_IWL<17223> A_IWL<17222> A_IWL<17221> A_IWL<17220> A_IWL<17219> A_IWL<17218> A_IWL<17217> A_IWL<17216> A_IWL<17215> A_IWL<17214> A_IWL<17213> A_IWL<17212> A_IWL<17211> A_IWL<17210> A_IWL<17209> A_IWL<17208> A_IWL<17207> A_IWL<17206> A_IWL<17205> A_IWL<17204> A_IWL<17203> A_IWL<17202> A_IWL<17201> A_IWL<17200> A_IWL<17199> A_IWL<17198> A_IWL<17197> A_IWL<17196> A_IWL<17195> A_IWL<17194> A_IWL<17193> A_IWL<17192> A_IWL<17191> A_IWL<17190> A_IWL<17189> A_IWL<17188> A_IWL<17187> A_IWL<17186> A_IWL<17185> A_IWL<17184> A_IWL<17183> A_IWL<17182> A_IWL<17181> A_IWL<17180> A_IWL<17179> A_IWL<17178> A_IWL<17177> A_IWL<17176> A_IWL<17175> A_IWL<17174> A_IWL<17173> A_IWL<17172> A_IWL<17171> A_IWL<17170> A_IWL<17169> A_IWL<17168> A_IWL<17167> A_IWL<17166> A_IWL<17165> A_IWL<17164> A_IWL<17163> A_IWL<17162> A_IWL<17161> A_IWL<17160> A_IWL<17159> A_IWL<17158> A_IWL<17157> A_IWL<17156> A_IWL<17155> A_IWL<17154> A_IWL<17153> A_IWL<17152> A_IWL<17151> A_IWL<17150> A_IWL<17149> A_IWL<17148> A_IWL<17147> A_IWL<17146> A_IWL<17145> A_IWL<17144> A_IWL<17143> A_IWL<17142> A_IWL<17141> A_IWL<17140> A_IWL<17139> A_IWL<17138> A_IWL<17137> A_IWL<17136> A_IWL<17135> A_IWL<17134> A_IWL<17133> A_IWL<17132> A_IWL<17131> A_IWL<17130> A_IWL<17129> A_IWL<17128> A_IWL<17127> A_IWL<17126> A_IWL<17125> A_IWL<17124> A_IWL<17123> A_IWL<17122> A_IWL<17121> A_IWL<17120> A_IWL<17119> A_IWL<17118> A_IWL<17117> A_IWL<17116> A_IWL<17115> A_IWL<17114> A_IWL<17113> A_IWL<17112> A_IWL<17111> A_IWL<17110> A_IWL<17109> A_IWL<17108> A_IWL<17107> A_IWL<17106> A_IWL<17105> A_IWL<17104> A_IWL<17103> A_IWL<17102> A_IWL<17101> A_IWL<17100> A_IWL<17099> A_IWL<17098> A_IWL<17097> A_IWL<17096> A_IWL<17095> A_IWL<17094> A_IWL<17093> A_IWL<17092> A_IWL<17091> A_IWL<17090> A_IWL<17089> A_IWL<17088> A_IWL<17087> A_IWL<17086> A_IWL<17085> A_IWL<17084> A_IWL<17083> A_IWL<17082> A_IWL<17081> A_IWL<17080> A_IWL<17079> A_IWL<17078> A_IWL<17077> A_IWL<17076> A_IWL<17075> A_IWL<17074> A_IWL<17073> A_IWL<17072> A_IWL<17071> A_IWL<17070> A_IWL<17069> A_IWL<17068> A_IWL<17067> A_IWL<17066> A_IWL<17065> A_IWL<17064> A_IWL<17063> A_IWL<17062> A_IWL<17061> A_IWL<17060> A_IWL<17059> A_IWL<17058> A_IWL<17057> A_IWL<17056> A_IWL<17055> A_IWL<17054> A_IWL<17053> A_IWL<17052> A_IWL<17051> A_IWL<17050> A_IWL<17049> A_IWL<17048> A_IWL<17047> A_IWL<17046> A_IWL<17045> A_IWL<17044> A_IWL<17043> A_IWL<17042> A_IWL<17041> A_IWL<17040> A_IWL<17039> A_IWL<17038> A_IWL<17037> A_IWL<17036> A_IWL<17035> A_IWL<17034> A_IWL<17033> A_IWL<17032> A_IWL<17031> A_IWL<17030> A_IWL<17029> A_IWL<17028> A_IWL<17027> A_IWL<17026> A_IWL<17025> A_IWL<17024> A_IWL<17023> A_IWL<17022> A_IWL<17021> A_IWL<17020> A_IWL<17019> A_IWL<17018> A_IWL<17017> A_IWL<17016> A_IWL<17015> A_IWL<17014> A_IWL<17013> A_IWL<17012> A_IWL<17011> A_IWL<17010> A_IWL<17009> A_IWL<17008> A_IWL<17007> A_IWL<17006> A_IWL<17005> A_IWL<17004> A_IWL<17003> A_IWL<17002> A_IWL<17001> A_IWL<17000> A_IWL<16999> A_IWL<16998> A_IWL<16997> A_IWL<16996> A_IWL<16995> A_IWL<16994> A_IWL<16993> A_IWL<16992> A_IWL<16991> A_IWL<16990> A_IWL<16989> A_IWL<16988> A_IWL<16987> A_IWL<16986> A_IWL<16985> A_IWL<16984> A_IWL<16983> A_IWL<16982> A_IWL<16981> A_IWL<16980> A_IWL<16979> A_IWL<16978> A_IWL<16977> A_IWL<16976> A_IWL<16975> A_IWL<16974> A_IWL<16973> A_IWL<16972> A_IWL<16971> A_IWL<16970> A_IWL<16969> A_IWL<16968> A_IWL<16967> A_IWL<16966> A_IWL<16965> A_IWL<16964> A_IWL<16963> A_IWL<16962> A_IWL<16961> A_IWL<16960> A_IWL<16959> A_IWL<16958> A_IWL<16957> A_IWL<16956> A_IWL<16955> A_IWL<16954> A_IWL<16953> A_IWL<16952> A_IWL<16951> A_IWL<16950> A_IWL<16949> A_IWL<16948> A_IWL<16947> A_IWL<16946> A_IWL<16945> A_IWL<16944> A_IWL<16943> A_IWL<16942> A_IWL<16941> A_IWL<16940> A_IWL<16939> A_IWL<16938> A_IWL<16937> A_IWL<16936> A_IWL<16935> A_IWL<16934> A_IWL<16933> A_IWL<16932> A_IWL<16931> A_IWL<16930> A_IWL<16929> A_IWL<16928> A_IWL<16927> A_IWL<16926> A_IWL<16925> A_IWL<16924> A_IWL<16923> A_IWL<16922> A_IWL<16921> A_IWL<16920> A_IWL<16919> A_IWL<16918> A_IWL<16917> A_IWL<16916> A_IWL<16915> A_IWL<16914> A_IWL<16913> A_IWL<16912> A_IWL<16911> A_IWL<16910> A_IWL<16909> A_IWL<16908> A_IWL<16907> A_IWL<16906> A_IWL<16905> A_IWL<16904> A_IWL<16903> A_IWL<16902> A_IWL<16901> A_IWL<16900> A_IWL<16899> A_IWL<16898> A_IWL<16897> A_IWL<16896> A_IWL<17919> A_IWL<17918> A_IWL<17917> A_IWL<17916> A_IWL<17915> A_IWL<17914> A_IWL<17913> A_IWL<17912> A_IWL<17911> A_IWL<17910> A_IWL<17909> A_IWL<17908> A_IWL<17907> A_IWL<17906> A_IWL<17905> A_IWL<17904> A_IWL<17903> A_IWL<17902> A_IWL<17901> A_IWL<17900> A_IWL<17899> A_IWL<17898> A_IWL<17897> A_IWL<17896> A_IWL<17895> A_IWL<17894> A_IWL<17893> A_IWL<17892> A_IWL<17891> A_IWL<17890> A_IWL<17889> A_IWL<17888> A_IWL<17887> A_IWL<17886> A_IWL<17885> A_IWL<17884> A_IWL<17883> A_IWL<17882> A_IWL<17881> A_IWL<17880> A_IWL<17879> A_IWL<17878> A_IWL<17877> A_IWL<17876> A_IWL<17875> A_IWL<17874> A_IWL<17873> A_IWL<17872> A_IWL<17871> A_IWL<17870> A_IWL<17869> A_IWL<17868> A_IWL<17867> A_IWL<17866> A_IWL<17865> A_IWL<17864> A_IWL<17863> A_IWL<17862> A_IWL<17861> A_IWL<17860> A_IWL<17859> A_IWL<17858> A_IWL<17857> A_IWL<17856> A_IWL<17855> A_IWL<17854> A_IWL<17853> A_IWL<17852> A_IWL<17851> A_IWL<17850> A_IWL<17849> A_IWL<17848> A_IWL<17847> A_IWL<17846> A_IWL<17845> A_IWL<17844> A_IWL<17843> A_IWL<17842> A_IWL<17841> A_IWL<17840> A_IWL<17839> A_IWL<17838> A_IWL<17837> A_IWL<17836> A_IWL<17835> A_IWL<17834> A_IWL<17833> A_IWL<17832> A_IWL<17831> A_IWL<17830> A_IWL<17829> A_IWL<17828> A_IWL<17827> A_IWL<17826> A_IWL<17825> A_IWL<17824> A_IWL<17823> A_IWL<17822> A_IWL<17821> A_IWL<17820> A_IWL<17819> A_IWL<17818> A_IWL<17817> A_IWL<17816> A_IWL<17815> A_IWL<17814> A_IWL<17813> A_IWL<17812> A_IWL<17811> A_IWL<17810> A_IWL<17809> A_IWL<17808> A_IWL<17807> A_IWL<17806> A_IWL<17805> A_IWL<17804> A_IWL<17803> A_IWL<17802> A_IWL<17801> A_IWL<17800> A_IWL<17799> A_IWL<17798> A_IWL<17797> A_IWL<17796> A_IWL<17795> A_IWL<17794> A_IWL<17793> A_IWL<17792> A_IWL<17791> A_IWL<17790> A_IWL<17789> A_IWL<17788> A_IWL<17787> A_IWL<17786> A_IWL<17785> A_IWL<17784> A_IWL<17783> A_IWL<17782> A_IWL<17781> A_IWL<17780> A_IWL<17779> A_IWL<17778> A_IWL<17777> A_IWL<17776> A_IWL<17775> A_IWL<17774> A_IWL<17773> A_IWL<17772> A_IWL<17771> A_IWL<17770> A_IWL<17769> A_IWL<17768> A_IWL<17767> A_IWL<17766> A_IWL<17765> A_IWL<17764> A_IWL<17763> A_IWL<17762> A_IWL<17761> A_IWL<17760> A_IWL<17759> A_IWL<17758> A_IWL<17757> A_IWL<17756> A_IWL<17755> A_IWL<17754> A_IWL<17753> A_IWL<17752> A_IWL<17751> A_IWL<17750> A_IWL<17749> A_IWL<17748> A_IWL<17747> A_IWL<17746> A_IWL<17745> A_IWL<17744> A_IWL<17743> A_IWL<17742> A_IWL<17741> A_IWL<17740> A_IWL<17739> A_IWL<17738> A_IWL<17737> A_IWL<17736> A_IWL<17735> A_IWL<17734> A_IWL<17733> A_IWL<17732> A_IWL<17731> A_IWL<17730> A_IWL<17729> A_IWL<17728> A_IWL<17727> A_IWL<17726> A_IWL<17725> A_IWL<17724> A_IWL<17723> A_IWL<17722> A_IWL<17721> A_IWL<17720> A_IWL<17719> A_IWL<17718> A_IWL<17717> A_IWL<17716> A_IWL<17715> A_IWL<17714> A_IWL<17713> A_IWL<17712> A_IWL<17711> A_IWL<17710> A_IWL<17709> A_IWL<17708> A_IWL<17707> A_IWL<17706> A_IWL<17705> A_IWL<17704> A_IWL<17703> A_IWL<17702> A_IWL<17701> A_IWL<17700> A_IWL<17699> A_IWL<17698> A_IWL<17697> A_IWL<17696> A_IWL<17695> A_IWL<17694> A_IWL<17693> A_IWL<17692> A_IWL<17691> A_IWL<17690> A_IWL<17689> A_IWL<17688> A_IWL<17687> A_IWL<17686> A_IWL<17685> A_IWL<17684> A_IWL<17683> A_IWL<17682> A_IWL<17681> A_IWL<17680> A_IWL<17679> A_IWL<17678> A_IWL<17677> A_IWL<17676> A_IWL<17675> A_IWL<17674> A_IWL<17673> A_IWL<17672> A_IWL<17671> A_IWL<17670> A_IWL<17669> A_IWL<17668> A_IWL<17667> A_IWL<17666> A_IWL<17665> A_IWL<17664> A_IWL<17663> A_IWL<17662> A_IWL<17661> A_IWL<17660> A_IWL<17659> A_IWL<17658> A_IWL<17657> A_IWL<17656> A_IWL<17655> A_IWL<17654> A_IWL<17653> A_IWL<17652> A_IWL<17651> A_IWL<17650> A_IWL<17649> A_IWL<17648> A_IWL<17647> A_IWL<17646> A_IWL<17645> A_IWL<17644> A_IWL<17643> A_IWL<17642> A_IWL<17641> A_IWL<17640> A_IWL<17639> A_IWL<17638> A_IWL<17637> A_IWL<17636> A_IWL<17635> A_IWL<17634> A_IWL<17633> A_IWL<17632> A_IWL<17631> A_IWL<17630> A_IWL<17629> A_IWL<17628> A_IWL<17627> A_IWL<17626> A_IWL<17625> A_IWL<17624> A_IWL<17623> A_IWL<17622> A_IWL<17621> A_IWL<17620> A_IWL<17619> A_IWL<17618> A_IWL<17617> A_IWL<17616> A_IWL<17615> A_IWL<17614> A_IWL<17613> A_IWL<17612> A_IWL<17611> A_IWL<17610> A_IWL<17609> A_IWL<17608> A_IWL<17607> A_IWL<17606> A_IWL<17605> A_IWL<17604> A_IWL<17603> A_IWL<17602> A_IWL<17601> A_IWL<17600> A_IWL<17599> A_IWL<17598> A_IWL<17597> A_IWL<17596> A_IWL<17595> A_IWL<17594> A_IWL<17593> A_IWL<17592> A_IWL<17591> A_IWL<17590> A_IWL<17589> A_IWL<17588> A_IWL<17587> A_IWL<17586> A_IWL<17585> A_IWL<17584> A_IWL<17583> A_IWL<17582> A_IWL<17581> A_IWL<17580> A_IWL<17579> A_IWL<17578> A_IWL<17577> A_IWL<17576> A_IWL<17575> A_IWL<17574> A_IWL<17573> A_IWL<17572> A_IWL<17571> A_IWL<17570> A_IWL<17569> A_IWL<17568> A_IWL<17567> A_IWL<17566> A_IWL<17565> A_IWL<17564> A_IWL<17563> A_IWL<17562> A_IWL<17561> A_IWL<17560> A_IWL<17559> A_IWL<17558> A_IWL<17557> A_IWL<17556> A_IWL<17555> A_IWL<17554> A_IWL<17553> A_IWL<17552> A_IWL<17551> A_IWL<17550> A_IWL<17549> A_IWL<17548> A_IWL<17547> A_IWL<17546> A_IWL<17545> A_IWL<17544> A_IWL<17543> A_IWL<17542> A_IWL<17541> A_IWL<17540> A_IWL<17539> A_IWL<17538> A_IWL<17537> A_IWL<17536> A_IWL<17535> A_IWL<17534> A_IWL<17533> A_IWL<17532> A_IWL<17531> A_IWL<17530> A_IWL<17529> A_IWL<17528> A_IWL<17527> A_IWL<17526> A_IWL<17525> A_IWL<17524> A_IWL<17523> A_IWL<17522> A_IWL<17521> A_IWL<17520> A_IWL<17519> A_IWL<17518> A_IWL<17517> A_IWL<17516> A_IWL<17515> A_IWL<17514> A_IWL<17513> A_IWL<17512> A_IWL<17511> A_IWL<17510> A_IWL<17509> A_IWL<17508> A_IWL<17507> A_IWL<17506> A_IWL<17505> A_IWL<17504> A_IWL<17503> A_IWL<17502> A_IWL<17501> A_IWL<17500> A_IWL<17499> A_IWL<17498> A_IWL<17497> A_IWL<17496> A_IWL<17495> A_IWL<17494> A_IWL<17493> A_IWL<17492> A_IWL<17491> A_IWL<17490> A_IWL<17489> A_IWL<17488> A_IWL<17487> A_IWL<17486> A_IWL<17485> A_IWL<17484> A_IWL<17483> A_IWL<17482> A_IWL<17481> A_IWL<17480> A_IWL<17479> A_IWL<17478> A_IWL<17477> A_IWL<17476> A_IWL<17475> A_IWL<17474> A_IWL<17473> A_IWL<17472> A_IWL<17471> A_IWL<17470> A_IWL<17469> A_IWL<17468> A_IWL<17467> A_IWL<17466> A_IWL<17465> A_IWL<17464> A_IWL<17463> A_IWL<17462> A_IWL<17461> A_IWL<17460> A_IWL<17459> A_IWL<17458> A_IWL<17457> A_IWL<17456> A_IWL<17455> A_IWL<17454> A_IWL<17453> A_IWL<17452> A_IWL<17451> A_IWL<17450> A_IWL<17449> A_IWL<17448> A_IWL<17447> A_IWL<17446> A_IWL<17445> A_IWL<17444> A_IWL<17443> A_IWL<17442> A_IWL<17441> A_IWL<17440> A_IWL<17439> A_IWL<17438> A_IWL<17437> A_IWL<17436> A_IWL<17435> A_IWL<17434> A_IWL<17433> A_IWL<17432> A_IWL<17431> A_IWL<17430> A_IWL<17429> A_IWL<17428> A_IWL<17427> A_IWL<17426> A_IWL<17425> A_IWL<17424> A_IWL<17423> A_IWL<17422> A_IWL<17421> A_IWL<17420> A_IWL<17419> A_IWL<17418> A_IWL<17417> A_IWL<17416> A_IWL<17415> A_IWL<17414> A_IWL<17413> A_IWL<17412> A_IWL<17411> A_IWL<17410> A_IWL<17409> A_IWL<17408> VDD_CORE VSS / RM_IHPSG13_8192x32_c4_1P_COLUMN_pcell_0 +XCOL<33> A_BLC<67> A_BLC<66> A_BLC_TOP<67> A_BLC_TOP<66> A_BLT<67> A_BLT<66> A_BLT_TOP<67> A_BLT_TOP<66> A_IWL<16895> A_IWL<16894> A_IWL<16893> A_IWL<16892> A_IWL<16891> A_IWL<16890> A_IWL<16889> A_IWL<16888> A_IWL<16887> A_IWL<16886> A_IWL<16885> A_IWL<16884> A_IWL<16883> A_IWL<16882> A_IWL<16881> A_IWL<16880> A_IWL<16879> A_IWL<16878> A_IWL<16877> A_IWL<16876> A_IWL<16875> A_IWL<16874> A_IWL<16873> A_IWL<16872> A_IWL<16871> A_IWL<16870> A_IWL<16869> A_IWL<16868> A_IWL<16867> A_IWL<16866> A_IWL<16865> A_IWL<16864> A_IWL<16863> A_IWL<16862> A_IWL<16861> A_IWL<16860> A_IWL<16859> A_IWL<16858> A_IWL<16857> A_IWL<16856> A_IWL<16855> A_IWL<16854> A_IWL<16853> A_IWL<16852> A_IWL<16851> A_IWL<16850> A_IWL<16849> A_IWL<16848> A_IWL<16847> A_IWL<16846> A_IWL<16845> A_IWL<16844> A_IWL<16843> A_IWL<16842> A_IWL<16841> A_IWL<16840> A_IWL<16839> A_IWL<16838> A_IWL<16837> A_IWL<16836> A_IWL<16835> A_IWL<16834> A_IWL<16833> A_IWL<16832> A_IWL<16831> A_IWL<16830> A_IWL<16829> A_IWL<16828> A_IWL<16827> A_IWL<16826> A_IWL<16825> A_IWL<16824> A_IWL<16823> A_IWL<16822> A_IWL<16821> A_IWL<16820> A_IWL<16819> A_IWL<16818> A_IWL<16817> A_IWL<16816> A_IWL<16815> A_IWL<16814> A_IWL<16813> A_IWL<16812> A_IWL<16811> A_IWL<16810> A_IWL<16809> A_IWL<16808> A_IWL<16807> A_IWL<16806> A_IWL<16805> A_IWL<16804> A_IWL<16803> A_IWL<16802> A_IWL<16801> A_IWL<16800> A_IWL<16799> A_IWL<16798> A_IWL<16797> A_IWL<16796> A_IWL<16795> A_IWL<16794> A_IWL<16793> A_IWL<16792> A_IWL<16791> A_IWL<16790> A_IWL<16789> A_IWL<16788> A_IWL<16787> A_IWL<16786> A_IWL<16785> A_IWL<16784> A_IWL<16783> A_IWL<16782> A_IWL<16781> A_IWL<16780> A_IWL<16779> A_IWL<16778> A_IWL<16777> A_IWL<16776> A_IWL<16775> A_IWL<16774> A_IWL<16773> A_IWL<16772> A_IWL<16771> A_IWL<16770> A_IWL<16769> A_IWL<16768> A_IWL<16767> A_IWL<16766> A_IWL<16765> A_IWL<16764> A_IWL<16763> A_IWL<16762> A_IWL<16761> A_IWL<16760> A_IWL<16759> A_IWL<16758> A_IWL<16757> A_IWL<16756> A_IWL<16755> A_IWL<16754> A_IWL<16753> A_IWL<16752> A_IWL<16751> A_IWL<16750> A_IWL<16749> A_IWL<16748> A_IWL<16747> A_IWL<16746> A_IWL<16745> A_IWL<16744> A_IWL<16743> A_IWL<16742> A_IWL<16741> A_IWL<16740> A_IWL<16739> A_IWL<16738> A_IWL<16737> A_IWL<16736> A_IWL<16735> A_IWL<16734> A_IWL<16733> A_IWL<16732> A_IWL<16731> A_IWL<16730> A_IWL<16729> A_IWL<16728> A_IWL<16727> A_IWL<16726> A_IWL<16725> A_IWL<16724> A_IWL<16723> A_IWL<16722> A_IWL<16721> A_IWL<16720> A_IWL<16719> A_IWL<16718> A_IWL<16717> A_IWL<16716> A_IWL<16715> A_IWL<16714> A_IWL<16713> A_IWL<16712> A_IWL<16711> A_IWL<16710> A_IWL<16709> A_IWL<16708> A_IWL<16707> A_IWL<16706> A_IWL<16705> A_IWL<16704> A_IWL<16703> A_IWL<16702> A_IWL<16701> A_IWL<16700> A_IWL<16699> A_IWL<16698> A_IWL<16697> A_IWL<16696> A_IWL<16695> A_IWL<16694> A_IWL<16693> A_IWL<16692> A_IWL<16691> A_IWL<16690> A_IWL<16689> A_IWL<16688> A_IWL<16687> A_IWL<16686> A_IWL<16685> A_IWL<16684> A_IWL<16683> A_IWL<16682> A_IWL<16681> A_IWL<16680> A_IWL<16679> A_IWL<16678> A_IWL<16677> A_IWL<16676> A_IWL<16675> A_IWL<16674> A_IWL<16673> A_IWL<16672> A_IWL<16671> A_IWL<16670> A_IWL<16669> A_IWL<16668> A_IWL<16667> A_IWL<16666> A_IWL<16665> A_IWL<16664> A_IWL<16663> A_IWL<16662> A_IWL<16661> A_IWL<16660> A_IWL<16659> A_IWL<16658> A_IWL<16657> A_IWL<16656> A_IWL<16655> A_IWL<16654> A_IWL<16653> A_IWL<16652> A_IWL<16651> A_IWL<16650> A_IWL<16649> A_IWL<16648> A_IWL<16647> A_IWL<16646> A_IWL<16645> A_IWL<16644> A_IWL<16643> A_IWL<16642> A_IWL<16641> A_IWL<16640> A_IWL<16639> A_IWL<16638> A_IWL<16637> A_IWL<16636> A_IWL<16635> A_IWL<16634> A_IWL<16633> A_IWL<16632> A_IWL<16631> A_IWL<16630> A_IWL<16629> A_IWL<16628> A_IWL<16627> A_IWL<16626> A_IWL<16625> A_IWL<16624> A_IWL<16623> A_IWL<16622> A_IWL<16621> A_IWL<16620> A_IWL<16619> A_IWL<16618> A_IWL<16617> A_IWL<16616> A_IWL<16615> A_IWL<16614> A_IWL<16613> A_IWL<16612> A_IWL<16611> A_IWL<16610> A_IWL<16609> A_IWL<16608> A_IWL<16607> A_IWL<16606> A_IWL<16605> A_IWL<16604> A_IWL<16603> A_IWL<16602> A_IWL<16601> A_IWL<16600> A_IWL<16599> A_IWL<16598> A_IWL<16597> A_IWL<16596> A_IWL<16595> A_IWL<16594> A_IWL<16593> A_IWL<16592> A_IWL<16591> A_IWL<16590> A_IWL<16589> A_IWL<16588> A_IWL<16587> A_IWL<16586> A_IWL<16585> A_IWL<16584> A_IWL<16583> A_IWL<16582> A_IWL<16581> A_IWL<16580> A_IWL<16579> A_IWL<16578> A_IWL<16577> A_IWL<16576> A_IWL<16575> A_IWL<16574> A_IWL<16573> A_IWL<16572> A_IWL<16571> A_IWL<16570> A_IWL<16569> A_IWL<16568> A_IWL<16567> A_IWL<16566> A_IWL<16565> A_IWL<16564> A_IWL<16563> A_IWL<16562> A_IWL<16561> A_IWL<16560> A_IWL<16559> A_IWL<16558> A_IWL<16557> A_IWL<16556> A_IWL<16555> A_IWL<16554> A_IWL<16553> A_IWL<16552> A_IWL<16551> A_IWL<16550> A_IWL<16549> A_IWL<16548> A_IWL<16547> A_IWL<16546> A_IWL<16545> A_IWL<16544> A_IWL<16543> A_IWL<16542> A_IWL<16541> A_IWL<16540> A_IWL<16539> A_IWL<16538> A_IWL<16537> A_IWL<16536> A_IWL<16535> A_IWL<16534> A_IWL<16533> A_IWL<16532> A_IWL<16531> A_IWL<16530> A_IWL<16529> A_IWL<16528> A_IWL<16527> A_IWL<16526> A_IWL<16525> A_IWL<16524> A_IWL<16523> A_IWL<16522> A_IWL<16521> A_IWL<16520> A_IWL<16519> A_IWL<16518> A_IWL<16517> A_IWL<16516> A_IWL<16515> A_IWL<16514> A_IWL<16513> A_IWL<16512> A_IWL<16511> A_IWL<16510> A_IWL<16509> A_IWL<16508> A_IWL<16507> A_IWL<16506> A_IWL<16505> A_IWL<16504> A_IWL<16503> A_IWL<16502> A_IWL<16501> A_IWL<16500> A_IWL<16499> A_IWL<16498> A_IWL<16497> A_IWL<16496> A_IWL<16495> A_IWL<16494> A_IWL<16493> A_IWL<16492> A_IWL<16491> A_IWL<16490> A_IWL<16489> A_IWL<16488> A_IWL<16487> A_IWL<16486> A_IWL<16485> A_IWL<16484> A_IWL<16483> A_IWL<16482> A_IWL<16481> A_IWL<16480> A_IWL<16479> A_IWL<16478> A_IWL<16477> A_IWL<16476> A_IWL<16475> A_IWL<16474> A_IWL<16473> A_IWL<16472> A_IWL<16471> A_IWL<16470> A_IWL<16469> A_IWL<16468> A_IWL<16467> A_IWL<16466> A_IWL<16465> A_IWL<16464> A_IWL<16463> A_IWL<16462> A_IWL<16461> A_IWL<16460> A_IWL<16459> A_IWL<16458> A_IWL<16457> A_IWL<16456> A_IWL<16455> A_IWL<16454> A_IWL<16453> A_IWL<16452> A_IWL<16451> A_IWL<16450> A_IWL<16449> A_IWL<16448> A_IWL<16447> A_IWL<16446> A_IWL<16445> A_IWL<16444> A_IWL<16443> A_IWL<16442> A_IWL<16441> A_IWL<16440> A_IWL<16439> A_IWL<16438> A_IWL<16437> A_IWL<16436> A_IWL<16435> A_IWL<16434> A_IWL<16433> A_IWL<16432> A_IWL<16431> A_IWL<16430> A_IWL<16429> A_IWL<16428> A_IWL<16427> A_IWL<16426> A_IWL<16425> A_IWL<16424> A_IWL<16423> A_IWL<16422> A_IWL<16421> A_IWL<16420> A_IWL<16419> A_IWL<16418> A_IWL<16417> A_IWL<16416> A_IWL<16415> A_IWL<16414> A_IWL<16413> A_IWL<16412> A_IWL<16411> A_IWL<16410> A_IWL<16409> A_IWL<16408> A_IWL<16407> A_IWL<16406> A_IWL<16405> A_IWL<16404> A_IWL<16403> A_IWL<16402> A_IWL<16401> A_IWL<16400> A_IWL<16399> A_IWL<16398> A_IWL<16397> A_IWL<16396> A_IWL<16395> A_IWL<16394> A_IWL<16393> A_IWL<16392> A_IWL<16391> A_IWL<16390> A_IWL<16389> A_IWL<16388> A_IWL<16387> A_IWL<16386> A_IWL<16385> A_IWL<16384> A_IWL<17407> A_IWL<17406> A_IWL<17405> A_IWL<17404> A_IWL<17403> A_IWL<17402> A_IWL<17401> A_IWL<17400> A_IWL<17399> A_IWL<17398> A_IWL<17397> A_IWL<17396> A_IWL<17395> A_IWL<17394> A_IWL<17393> A_IWL<17392> A_IWL<17391> A_IWL<17390> A_IWL<17389> A_IWL<17388> A_IWL<17387> A_IWL<17386> A_IWL<17385> A_IWL<17384> A_IWL<17383> A_IWL<17382> A_IWL<17381> A_IWL<17380> A_IWL<17379> A_IWL<17378> A_IWL<17377> A_IWL<17376> A_IWL<17375> A_IWL<17374> A_IWL<17373> A_IWL<17372> A_IWL<17371> A_IWL<17370> A_IWL<17369> A_IWL<17368> A_IWL<17367> A_IWL<17366> A_IWL<17365> A_IWL<17364> A_IWL<17363> A_IWL<17362> A_IWL<17361> A_IWL<17360> A_IWL<17359> A_IWL<17358> A_IWL<17357> A_IWL<17356> A_IWL<17355> A_IWL<17354> A_IWL<17353> A_IWL<17352> A_IWL<17351> A_IWL<17350> A_IWL<17349> A_IWL<17348> A_IWL<17347> A_IWL<17346> A_IWL<17345> A_IWL<17344> A_IWL<17343> A_IWL<17342> A_IWL<17341> A_IWL<17340> A_IWL<17339> A_IWL<17338> A_IWL<17337> A_IWL<17336> A_IWL<17335> A_IWL<17334> A_IWL<17333> A_IWL<17332> A_IWL<17331> A_IWL<17330> A_IWL<17329> A_IWL<17328> A_IWL<17327> A_IWL<17326> A_IWL<17325> A_IWL<17324> A_IWL<17323> A_IWL<17322> A_IWL<17321> A_IWL<17320> A_IWL<17319> A_IWL<17318> A_IWL<17317> A_IWL<17316> A_IWL<17315> A_IWL<17314> A_IWL<17313> A_IWL<17312> A_IWL<17311> A_IWL<17310> A_IWL<17309> A_IWL<17308> A_IWL<17307> A_IWL<17306> A_IWL<17305> A_IWL<17304> A_IWL<17303> A_IWL<17302> A_IWL<17301> A_IWL<17300> A_IWL<17299> A_IWL<17298> A_IWL<17297> A_IWL<17296> A_IWL<17295> A_IWL<17294> A_IWL<17293> A_IWL<17292> A_IWL<17291> A_IWL<17290> A_IWL<17289> A_IWL<17288> A_IWL<17287> A_IWL<17286> A_IWL<17285> A_IWL<17284> A_IWL<17283> A_IWL<17282> A_IWL<17281> A_IWL<17280> A_IWL<17279> A_IWL<17278> A_IWL<17277> A_IWL<17276> A_IWL<17275> A_IWL<17274> A_IWL<17273> A_IWL<17272> A_IWL<17271> A_IWL<17270> A_IWL<17269> A_IWL<17268> A_IWL<17267> A_IWL<17266> A_IWL<17265> A_IWL<17264> A_IWL<17263> A_IWL<17262> A_IWL<17261> A_IWL<17260> A_IWL<17259> A_IWL<17258> A_IWL<17257> A_IWL<17256> A_IWL<17255> A_IWL<17254> A_IWL<17253> A_IWL<17252> A_IWL<17251> A_IWL<17250> A_IWL<17249> A_IWL<17248> A_IWL<17247> A_IWL<17246> A_IWL<17245> A_IWL<17244> A_IWL<17243> A_IWL<17242> A_IWL<17241> A_IWL<17240> A_IWL<17239> A_IWL<17238> A_IWL<17237> A_IWL<17236> A_IWL<17235> A_IWL<17234> A_IWL<17233> A_IWL<17232> A_IWL<17231> A_IWL<17230> A_IWL<17229> A_IWL<17228> A_IWL<17227> A_IWL<17226> A_IWL<17225> A_IWL<17224> A_IWL<17223> A_IWL<17222> A_IWL<17221> A_IWL<17220> A_IWL<17219> A_IWL<17218> A_IWL<17217> A_IWL<17216> A_IWL<17215> A_IWL<17214> A_IWL<17213> A_IWL<17212> A_IWL<17211> A_IWL<17210> A_IWL<17209> A_IWL<17208> A_IWL<17207> A_IWL<17206> A_IWL<17205> A_IWL<17204> A_IWL<17203> A_IWL<17202> A_IWL<17201> A_IWL<17200> A_IWL<17199> A_IWL<17198> A_IWL<17197> A_IWL<17196> A_IWL<17195> A_IWL<17194> A_IWL<17193> A_IWL<17192> A_IWL<17191> A_IWL<17190> A_IWL<17189> A_IWL<17188> A_IWL<17187> A_IWL<17186> A_IWL<17185> A_IWL<17184> A_IWL<17183> A_IWL<17182> A_IWL<17181> A_IWL<17180> A_IWL<17179> A_IWL<17178> A_IWL<17177> A_IWL<17176> A_IWL<17175> A_IWL<17174> A_IWL<17173> A_IWL<17172> A_IWL<17171> A_IWL<17170> A_IWL<17169> A_IWL<17168> A_IWL<17167> A_IWL<17166> A_IWL<17165> A_IWL<17164> A_IWL<17163> A_IWL<17162> A_IWL<17161> A_IWL<17160> A_IWL<17159> A_IWL<17158> A_IWL<17157> A_IWL<17156> A_IWL<17155> A_IWL<17154> A_IWL<17153> A_IWL<17152> A_IWL<17151> A_IWL<17150> A_IWL<17149> A_IWL<17148> A_IWL<17147> A_IWL<17146> A_IWL<17145> A_IWL<17144> A_IWL<17143> A_IWL<17142> A_IWL<17141> A_IWL<17140> A_IWL<17139> A_IWL<17138> A_IWL<17137> A_IWL<17136> A_IWL<17135> A_IWL<17134> A_IWL<17133> A_IWL<17132> A_IWL<17131> A_IWL<17130> A_IWL<17129> A_IWL<17128> A_IWL<17127> A_IWL<17126> A_IWL<17125> A_IWL<17124> A_IWL<17123> A_IWL<17122> A_IWL<17121> A_IWL<17120> A_IWL<17119> A_IWL<17118> A_IWL<17117> A_IWL<17116> A_IWL<17115> A_IWL<17114> A_IWL<17113> A_IWL<17112> A_IWL<17111> A_IWL<17110> A_IWL<17109> A_IWL<17108> A_IWL<17107> A_IWL<17106> A_IWL<17105> A_IWL<17104> A_IWL<17103> A_IWL<17102> A_IWL<17101> A_IWL<17100> A_IWL<17099> A_IWL<17098> A_IWL<17097> A_IWL<17096> A_IWL<17095> A_IWL<17094> A_IWL<17093> A_IWL<17092> A_IWL<17091> A_IWL<17090> A_IWL<17089> A_IWL<17088> A_IWL<17087> A_IWL<17086> A_IWL<17085> A_IWL<17084> A_IWL<17083> A_IWL<17082> A_IWL<17081> A_IWL<17080> A_IWL<17079> A_IWL<17078> A_IWL<17077> A_IWL<17076> A_IWL<17075> A_IWL<17074> A_IWL<17073> A_IWL<17072> A_IWL<17071> A_IWL<17070> A_IWL<17069> A_IWL<17068> A_IWL<17067> A_IWL<17066> A_IWL<17065> A_IWL<17064> A_IWL<17063> A_IWL<17062> A_IWL<17061> A_IWL<17060> A_IWL<17059> A_IWL<17058> A_IWL<17057> A_IWL<17056> A_IWL<17055> A_IWL<17054> A_IWL<17053> A_IWL<17052> A_IWL<17051> A_IWL<17050> A_IWL<17049> A_IWL<17048> A_IWL<17047> A_IWL<17046> A_IWL<17045> A_IWL<17044> A_IWL<17043> A_IWL<17042> A_IWL<17041> A_IWL<17040> A_IWL<17039> A_IWL<17038> A_IWL<17037> A_IWL<17036> A_IWL<17035> A_IWL<17034> A_IWL<17033> A_IWL<17032> A_IWL<17031> A_IWL<17030> A_IWL<17029> A_IWL<17028> A_IWL<17027> A_IWL<17026> A_IWL<17025> A_IWL<17024> A_IWL<17023> A_IWL<17022> A_IWL<17021> A_IWL<17020> A_IWL<17019> A_IWL<17018> A_IWL<17017> A_IWL<17016> A_IWL<17015> A_IWL<17014> A_IWL<17013> A_IWL<17012> A_IWL<17011> A_IWL<17010> A_IWL<17009> A_IWL<17008> A_IWL<17007> A_IWL<17006> A_IWL<17005> A_IWL<17004> A_IWL<17003> A_IWL<17002> A_IWL<17001> A_IWL<17000> A_IWL<16999> A_IWL<16998> A_IWL<16997> A_IWL<16996> A_IWL<16995> A_IWL<16994> A_IWL<16993> A_IWL<16992> A_IWL<16991> A_IWL<16990> A_IWL<16989> A_IWL<16988> A_IWL<16987> A_IWL<16986> A_IWL<16985> A_IWL<16984> A_IWL<16983> A_IWL<16982> A_IWL<16981> A_IWL<16980> A_IWL<16979> A_IWL<16978> A_IWL<16977> A_IWL<16976> A_IWL<16975> A_IWL<16974> A_IWL<16973> A_IWL<16972> A_IWL<16971> A_IWL<16970> A_IWL<16969> A_IWL<16968> A_IWL<16967> A_IWL<16966> A_IWL<16965> A_IWL<16964> A_IWL<16963> A_IWL<16962> A_IWL<16961> A_IWL<16960> A_IWL<16959> A_IWL<16958> A_IWL<16957> A_IWL<16956> A_IWL<16955> A_IWL<16954> A_IWL<16953> A_IWL<16952> A_IWL<16951> A_IWL<16950> A_IWL<16949> A_IWL<16948> A_IWL<16947> A_IWL<16946> A_IWL<16945> A_IWL<16944> A_IWL<16943> A_IWL<16942> A_IWL<16941> A_IWL<16940> A_IWL<16939> A_IWL<16938> A_IWL<16937> A_IWL<16936> A_IWL<16935> A_IWL<16934> A_IWL<16933> A_IWL<16932> A_IWL<16931> A_IWL<16930> A_IWL<16929> A_IWL<16928> A_IWL<16927> A_IWL<16926> A_IWL<16925> A_IWL<16924> A_IWL<16923> A_IWL<16922> A_IWL<16921> A_IWL<16920> A_IWL<16919> A_IWL<16918> A_IWL<16917> A_IWL<16916> A_IWL<16915> A_IWL<16914> A_IWL<16913> A_IWL<16912> A_IWL<16911> A_IWL<16910> A_IWL<16909> A_IWL<16908> A_IWL<16907> A_IWL<16906> A_IWL<16905> A_IWL<16904> A_IWL<16903> A_IWL<16902> A_IWL<16901> A_IWL<16900> A_IWL<16899> A_IWL<16898> A_IWL<16897> A_IWL<16896> VDD_CORE VSS / RM_IHPSG13_8192x32_c4_1P_COLUMN_pcell_0 +XCOL<32> A_BLC<65> A_BLC<64> A_BLC_TOP<65> A_BLC_TOP<64> A_BLT<65> A_BLT<64> A_BLT_TOP<65> A_BLT_TOP<64> A_IWL<16383> A_IWL<16382> A_IWL<16381> A_IWL<16380> A_IWL<16379> A_IWL<16378> A_IWL<16377> A_IWL<16376> A_IWL<16375> A_IWL<16374> A_IWL<16373> A_IWL<16372> A_IWL<16371> A_IWL<16370> A_IWL<16369> A_IWL<16368> A_IWL<16367> A_IWL<16366> A_IWL<16365> A_IWL<16364> A_IWL<16363> A_IWL<16362> A_IWL<16361> A_IWL<16360> A_IWL<16359> A_IWL<16358> A_IWL<16357> A_IWL<16356> A_IWL<16355> A_IWL<16354> A_IWL<16353> A_IWL<16352> A_IWL<16351> A_IWL<16350> A_IWL<16349> A_IWL<16348> A_IWL<16347> A_IWL<16346> A_IWL<16345> A_IWL<16344> A_IWL<16343> A_IWL<16342> A_IWL<16341> A_IWL<16340> A_IWL<16339> A_IWL<16338> A_IWL<16337> A_IWL<16336> A_IWL<16335> A_IWL<16334> A_IWL<16333> A_IWL<16332> A_IWL<16331> A_IWL<16330> A_IWL<16329> A_IWL<16328> A_IWL<16327> A_IWL<16326> A_IWL<16325> A_IWL<16324> A_IWL<16323> A_IWL<16322> A_IWL<16321> A_IWL<16320> A_IWL<16319> A_IWL<16318> A_IWL<16317> A_IWL<16316> A_IWL<16315> A_IWL<16314> A_IWL<16313> A_IWL<16312> A_IWL<16311> A_IWL<16310> A_IWL<16309> A_IWL<16308> A_IWL<16307> A_IWL<16306> A_IWL<16305> A_IWL<16304> A_IWL<16303> A_IWL<16302> A_IWL<16301> A_IWL<16300> A_IWL<16299> A_IWL<16298> A_IWL<16297> A_IWL<16296> A_IWL<16295> A_IWL<16294> A_IWL<16293> A_IWL<16292> A_IWL<16291> A_IWL<16290> A_IWL<16289> A_IWL<16288> A_IWL<16287> A_IWL<16286> A_IWL<16285> A_IWL<16284> A_IWL<16283> A_IWL<16282> A_IWL<16281> A_IWL<16280> A_IWL<16279> A_IWL<16278> A_IWL<16277> A_IWL<16276> A_IWL<16275> A_IWL<16274> A_IWL<16273> A_IWL<16272> A_IWL<16271> A_IWL<16270> A_IWL<16269> A_IWL<16268> A_IWL<16267> A_IWL<16266> A_IWL<16265> A_IWL<16264> A_IWL<16263> A_IWL<16262> A_IWL<16261> A_IWL<16260> A_IWL<16259> A_IWL<16258> A_IWL<16257> A_IWL<16256> A_IWL<16255> A_IWL<16254> A_IWL<16253> A_IWL<16252> A_IWL<16251> A_IWL<16250> A_IWL<16249> A_IWL<16248> A_IWL<16247> A_IWL<16246> A_IWL<16245> A_IWL<16244> A_IWL<16243> A_IWL<16242> A_IWL<16241> A_IWL<16240> A_IWL<16239> A_IWL<16238> A_IWL<16237> A_IWL<16236> A_IWL<16235> A_IWL<16234> A_IWL<16233> A_IWL<16232> A_IWL<16231> A_IWL<16230> A_IWL<16229> A_IWL<16228> A_IWL<16227> A_IWL<16226> A_IWL<16225> A_IWL<16224> A_IWL<16223> A_IWL<16222> A_IWL<16221> A_IWL<16220> A_IWL<16219> A_IWL<16218> A_IWL<16217> A_IWL<16216> A_IWL<16215> A_IWL<16214> A_IWL<16213> A_IWL<16212> A_IWL<16211> A_IWL<16210> A_IWL<16209> A_IWL<16208> A_IWL<16207> A_IWL<16206> A_IWL<16205> A_IWL<16204> A_IWL<16203> A_IWL<16202> A_IWL<16201> A_IWL<16200> A_IWL<16199> A_IWL<16198> A_IWL<16197> A_IWL<16196> A_IWL<16195> A_IWL<16194> A_IWL<16193> A_IWL<16192> A_IWL<16191> A_IWL<16190> A_IWL<16189> A_IWL<16188> A_IWL<16187> A_IWL<16186> A_IWL<16185> A_IWL<16184> A_IWL<16183> A_IWL<16182> A_IWL<16181> A_IWL<16180> A_IWL<16179> A_IWL<16178> A_IWL<16177> A_IWL<16176> A_IWL<16175> A_IWL<16174> A_IWL<16173> A_IWL<16172> A_IWL<16171> A_IWL<16170> A_IWL<16169> A_IWL<16168> A_IWL<16167> A_IWL<16166> A_IWL<16165> A_IWL<16164> A_IWL<16163> A_IWL<16162> A_IWL<16161> A_IWL<16160> A_IWL<16159> A_IWL<16158> A_IWL<16157> A_IWL<16156> A_IWL<16155> A_IWL<16154> A_IWL<16153> A_IWL<16152> A_IWL<16151> A_IWL<16150> A_IWL<16149> A_IWL<16148> A_IWL<16147> A_IWL<16146> A_IWL<16145> A_IWL<16144> A_IWL<16143> A_IWL<16142> A_IWL<16141> A_IWL<16140> A_IWL<16139> A_IWL<16138> A_IWL<16137> A_IWL<16136> A_IWL<16135> A_IWL<16134> A_IWL<16133> A_IWL<16132> A_IWL<16131> A_IWL<16130> A_IWL<16129> A_IWL<16128> A_IWL<16127> A_IWL<16126> A_IWL<16125> A_IWL<16124> A_IWL<16123> A_IWL<16122> A_IWL<16121> A_IWL<16120> A_IWL<16119> A_IWL<16118> A_IWL<16117> A_IWL<16116> A_IWL<16115> A_IWL<16114> A_IWL<16113> A_IWL<16112> A_IWL<16111> A_IWL<16110> A_IWL<16109> A_IWL<16108> A_IWL<16107> A_IWL<16106> A_IWL<16105> A_IWL<16104> A_IWL<16103> A_IWL<16102> A_IWL<16101> A_IWL<16100> A_IWL<16099> A_IWL<16098> A_IWL<16097> A_IWL<16096> A_IWL<16095> A_IWL<16094> A_IWL<16093> A_IWL<16092> A_IWL<16091> A_IWL<16090> A_IWL<16089> A_IWL<16088> A_IWL<16087> A_IWL<16086> A_IWL<16085> A_IWL<16084> A_IWL<16083> A_IWL<16082> A_IWL<16081> A_IWL<16080> A_IWL<16079> A_IWL<16078> A_IWL<16077> A_IWL<16076> A_IWL<16075> A_IWL<16074> A_IWL<16073> A_IWL<16072> A_IWL<16071> A_IWL<16070> A_IWL<16069> A_IWL<16068> A_IWL<16067> A_IWL<16066> A_IWL<16065> A_IWL<16064> A_IWL<16063> A_IWL<16062> A_IWL<16061> A_IWL<16060> A_IWL<16059> A_IWL<16058> A_IWL<16057> A_IWL<16056> A_IWL<16055> A_IWL<16054> A_IWL<16053> A_IWL<16052> A_IWL<16051> A_IWL<16050> A_IWL<16049> A_IWL<16048> A_IWL<16047> A_IWL<16046> A_IWL<16045> A_IWL<16044> A_IWL<16043> A_IWL<16042> A_IWL<16041> A_IWL<16040> A_IWL<16039> A_IWL<16038> A_IWL<16037> A_IWL<16036> A_IWL<16035> A_IWL<16034> A_IWL<16033> A_IWL<16032> A_IWL<16031> A_IWL<16030> A_IWL<16029> A_IWL<16028> A_IWL<16027> A_IWL<16026> A_IWL<16025> A_IWL<16024> A_IWL<16023> A_IWL<16022> A_IWL<16021> A_IWL<16020> A_IWL<16019> A_IWL<16018> A_IWL<16017> A_IWL<16016> A_IWL<16015> A_IWL<16014> A_IWL<16013> A_IWL<16012> A_IWL<16011> A_IWL<16010> A_IWL<16009> A_IWL<16008> A_IWL<16007> A_IWL<16006> A_IWL<16005> A_IWL<16004> A_IWL<16003> A_IWL<16002> A_IWL<16001> A_IWL<16000> A_IWL<15999> A_IWL<15998> A_IWL<15997> A_IWL<15996> A_IWL<15995> A_IWL<15994> A_IWL<15993> A_IWL<15992> A_IWL<15991> A_IWL<15990> A_IWL<15989> A_IWL<15988> A_IWL<15987> A_IWL<15986> A_IWL<15985> A_IWL<15984> A_IWL<15983> A_IWL<15982> A_IWL<15981> A_IWL<15980> A_IWL<15979> A_IWL<15978> A_IWL<15977> A_IWL<15976> A_IWL<15975> A_IWL<15974> A_IWL<15973> A_IWL<15972> A_IWL<15971> A_IWL<15970> A_IWL<15969> A_IWL<15968> A_IWL<15967> A_IWL<15966> A_IWL<15965> A_IWL<15964> A_IWL<15963> A_IWL<15962> A_IWL<15961> A_IWL<15960> A_IWL<15959> A_IWL<15958> A_IWL<15957> A_IWL<15956> A_IWL<15955> A_IWL<15954> A_IWL<15953> A_IWL<15952> A_IWL<15951> A_IWL<15950> A_IWL<15949> A_IWL<15948> A_IWL<15947> A_IWL<15946> A_IWL<15945> A_IWL<15944> A_IWL<15943> A_IWL<15942> A_IWL<15941> A_IWL<15940> A_IWL<15939> A_IWL<15938> A_IWL<15937> A_IWL<15936> A_IWL<15935> A_IWL<15934> A_IWL<15933> A_IWL<15932> A_IWL<15931> A_IWL<15930> A_IWL<15929> A_IWL<15928> A_IWL<15927> A_IWL<15926> A_IWL<15925> A_IWL<15924> A_IWL<15923> A_IWL<15922> A_IWL<15921> A_IWL<15920> A_IWL<15919> A_IWL<15918> A_IWL<15917> A_IWL<15916> A_IWL<15915> A_IWL<15914> A_IWL<15913> A_IWL<15912> A_IWL<15911> A_IWL<15910> A_IWL<15909> A_IWL<15908> A_IWL<15907> A_IWL<15906> A_IWL<15905> A_IWL<15904> A_IWL<15903> A_IWL<15902> A_IWL<15901> A_IWL<15900> A_IWL<15899> A_IWL<15898> A_IWL<15897> A_IWL<15896> A_IWL<15895> A_IWL<15894> A_IWL<15893> A_IWL<15892> A_IWL<15891> A_IWL<15890> A_IWL<15889> A_IWL<15888> A_IWL<15887> A_IWL<15886> A_IWL<15885> A_IWL<15884> A_IWL<15883> A_IWL<15882> A_IWL<15881> A_IWL<15880> A_IWL<15879> A_IWL<15878> A_IWL<15877> A_IWL<15876> A_IWL<15875> A_IWL<15874> A_IWL<15873> A_IWL<15872> A_IWL<16895> A_IWL<16894> A_IWL<16893> A_IWL<16892> A_IWL<16891> A_IWL<16890> A_IWL<16889> A_IWL<16888> A_IWL<16887> A_IWL<16886> A_IWL<16885> A_IWL<16884> A_IWL<16883> A_IWL<16882> A_IWL<16881> A_IWL<16880> A_IWL<16879> A_IWL<16878> A_IWL<16877> A_IWL<16876> A_IWL<16875> A_IWL<16874> A_IWL<16873> A_IWL<16872> A_IWL<16871> A_IWL<16870> A_IWL<16869> A_IWL<16868> A_IWL<16867> A_IWL<16866> A_IWL<16865> A_IWL<16864> A_IWL<16863> A_IWL<16862> A_IWL<16861> A_IWL<16860> A_IWL<16859> A_IWL<16858> A_IWL<16857> A_IWL<16856> A_IWL<16855> A_IWL<16854> A_IWL<16853> A_IWL<16852> A_IWL<16851> A_IWL<16850> A_IWL<16849> A_IWL<16848> A_IWL<16847> A_IWL<16846> A_IWL<16845> A_IWL<16844> A_IWL<16843> A_IWL<16842> A_IWL<16841> A_IWL<16840> A_IWL<16839> A_IWL<16838> A_IWL<16837> A_IWL<16836> A_IWL<16835> A_IWL<16834> A_IWL<16833> A_IWL<16832> A_IWL<16831> A_IWL<16830> A_IWL<16829> A_IWL<16828> A_IWL<16827> A_IWL<16826> A_IWL<16825> A_IWL<16824> A_IWL<16823> A_IWL<16822> A_IWL<16821> A_IWL<16820> A_IWL<16819> A_IWL<16818> A_IWL<16817> A_IWL<16816> A_IWL<16815> A_IWL<16814> A_IWL<16813> A_IWL<16812> A_IWL<16811> A_IWL<16810> A_IWL<16809> A_IWL<16808> A_IWL<16807> A_IWL<16806> A_IWL<16805> A_IWL<16804> A_IWL<16803> A_IWL<16802> A_IWL<16801> A_IWL<16800> A_IWL<16799> A_IWL<16798> A_IWL<16797> A_IWL<16796> A_IWL<16795> A_IWL<16794> A_IWL<16793> A_IWL<16792> A_IWL<16791> A_IWL<16790> A_IWL<16789> A_IWL<16788> A_IWL<16787> A_IWL<16786> A_IWL<16785> A_IWL<16784> A_IWL<16783> A_IWL<16782> A_IWL<16781> A_IWL<16780> A_IWL<16779> A_IWL<16778> A_IWL<16777> A_IWL<16776> A_IWL<16775> A_IWL<16774> A_IWL<16773> A_IWL<16772> A_IWL<16771> A_IWL<16770> A_IWL<16769> A_IWL<16768> A_IWL<16767> A_IWL<16766> A_IWL<16765> A_IWL<16764> A_IWL<16763> A_IWL<16762> A_IWL<16761> A_IWL<16760> A_IWL<16759> A_IWL<16758> A_IWL<16757> A_IWL<16756> A_IWL<16755> A_IWL<16754> A_IWL<16753> A_IWL<16752> A_IWL<16751> A_IWL<16750> A_IWL<16749> A_IWL<16748> A_IWL<16747> A_IWL<16746> A_IWL<16745> A_IWL<16744> A_IWL<16743> A_IWL<16742> A_IWL<16741> A_IWL<16740> A_IWL<16739> A_IWL<16738> A_IWL<16737> A_IWL<16736> A_IWL<16735> A_IWL<16734> A_IWL<16733> A_IWL<16732> A_IWL<16731> A_IWL<16730> A_IWL<16729> A_IWL<16728> A_IWL<16727> A_IWL<16726> A_IWL<16725> A_IWL<16724> A_IWL<16723> A_IWL<16722> A_IWL<16721> A_IWL<16720> A_IWL<16719> A_IWL<16718> A_IWL<16717> A_IWL<16716> A_IWL<16715> A_IWL<16714> A_IWL<16713> A_IWL<16712> A_IWL<16711> A_IWL<16710> A_IWL<16709> A_IWL<16708> A_IWL<16707> A_IWL<16706> A_IWL<16705> A_IWL<16704> A_IWL<16703> A_IWL<16702> A_IWL<16701> A_IWL<16700> A_IWL<16699> A_IWL<16698> A_IWL<16697> A_IWL<16696> A_IWL<16695> A_IWL<16694> A_IWL<16693> A_IWL<16692> A_IWL<16691> A_IWL<16690> A_IWL<16689> A_IWL<16688> A_IWL<16687> A_IWL<16686> A_IWL<16685> A_IWL<16684> A_IWL<16683> A_IWL<16682> A_IWL<16681> A_IWL<16680> A_IWL<16679> A_IWL<16678> A_IWL<16677> A_IWL<16676> A_IWL<16675> A_IWL<16674> A_IWL<16673> A_IWL<16672> A_IWL<16671> A_IWL<16670> A_IWL<16669> A_IWL<16668> A_IWL<16667> A_IWL<16666> A_IWL<16665> A_IWL<16664> A_IWL<16663> A_IWL<16662> A_IWL<16661> A_IWL<16660> A_IWL<16659> A_IWL<16658> A_IWL<16657> A_IWL<16656> A_IWL<16655> A_IWL<16654> A_IWL<16653> A_IWL<16652> A_IWL<16651> A_IWL<16650> A_IWL<16649> A_IWL<16648> A_IWL<16647> A_IWL<16646> A_IWL<16645> A_IWL<16644> A_IWL<16643> A_IWL<16642> A_IWL<16641> A_IWL<16640> A_IWL<16639> A_IWL<16638> A_IWL<16637> A_IWL<16636> A_IWL<16635> A_IWL<16634> A_IWL<16633> A_IWL<16632> A_IWL<16631> A_IWL<16630> A_IWL<16629> A_IWL<16628> A_IWL<16627> A_IWL<16626> A_IWL<16625> A_IWL<16624> A_IWL<16623> A_IWL<16622> A_IWL<16621> A_IWL<16620> A_IWL<16619> A_IWL<16618> A_IWL<16617> A_IWL<16616> A_IWL<16615> A_IWL<16614> A_IWL<16613> A_IWL<16612> A_IWL<16611> A_IWL<16610> A_IWL<16609> A_IWL<16608> A_IWL<16607> A_IWL<16606> A_IWL<16605> A_IWL<16604> A_IWL<16603> A_IWL<16602> A_IWL<16601> A_IWL<16600> A_IWL<16599> A_IWL<16598> A_IWL<16597> A_IWL<16596> A_IWL<16595> A_IWL<16594> A_IWL<16593> A_IWL<16592> A_IWL<16591> A_IWL<16590> A_IWL<16589> A_IWL<16588> A_IWL<16587> A_IWL<16586> A_IWL<16585> A_IWL<16584> A_IWL<16583> A_IWL<16582> A_IWL<16581> A_IWL<16580> A_IWL<16579> A_IWL<16578> A_IWL<16577> A_IWL<16576> A_IWL<16575> A_IWL<16574> A_IWL<16573> A_IWL<16572> A_IWL<16571> A_IWL<16570> A_IWL<16569> A_IWL<16568> A_IWL<16567> A_IWL<16566> A_IWL<16565> A_IWL<16564> A_IWL<16563> A_IWL<16562> A_IWL<16561> A_IWL<16560> A_IWL<16559> A_IWL<16558> A_IWL<16557> A_IWL<16556> A_IWL<16555> A_IWL<16554> A_IWL<16553> A_IWL<16552> A_IWL<16551> A_IWL<16550> A_IWL<16549> A_IWL<16548> A_IWL<16547> A_IWL<16546> A_IWL<16545> A_IWL<16544> A_IWL<16543> A_IWL<16542> A_IWL<16541> A_IWL<16540> A_IWL<16539> A_IWL<16538> A_IWL<16537> A_IWL<16536> A_IWL<16535> A_IWL<16534> A_IWL<16533> A_IWL<16532> A_IWL<16531> A_IWL<16530> A_IWL<16529> A_IWL<16528> A_IWL<16527> A_IWL<16526> A_IWL<16525> A_IWL<16524> A_IWL<16523> A_IWL<16522> A_IWL<16521> A_IWL<16520> A_IWL<16519> A_IWL<16518> A_IWL<16517> A_IWL<16516> A_IWL<16515> A_IWL<16514> A_IWL<16513> A_IWL<16512> A_IWL<16511> A_IWL<16510> A_IWL<16509> A_IWL<16508> A_IWL<16507> A_IWL<16506> A_IWL<16505> A_IWL<16504> A_IWL<16503> A_IWL<16502> A_IWL<16501> A_IWL<16500> A_IWL<16499> A_IWL<16498> A_IWL<16497> A_IWL<16496> A_IWL<16495> A_IWL<16494> A_IWL<16493> A_IWL<16492> A_IWL<16491> A_IWL<16490> A_IWL<16489> A_IWL<16488> A_IWL<16487> A_IWL<16486> A_IWL<16485> A_IWL<16484> A_IWL<16483> A_IWL<16482> A_IWL<16481> A_IWL<16480> A_IWL<16479> A_IWL<16478> A_IWL<16477> A_IWL<16476> A_IWL<16475> A_IWL<16474> A_IWL<16473> A_IWL<16472> A_IWL<16471> A_IWL<16470> A_IWL<16469> A_IWL<16468> A_IWL<16467> A_IWL<16466> A_IWL<16465> A_IWL<16464> A_IWL<16463> A_IWL<16462> A_IWL<16461> A_IWL<16460> A_IWL<16459> A_IWL<16458> A_IWL<16457> A_IWL<16456> A_IWL<16455> A_IWL<16454> A_IWL<16453> A_IWL<16452> A_IWL<16451> A_IWL<16450> A_IWL<16449> A_IWL<16448> A_IWL<16447> A_IWL<16446> A_IWL<16445> A_IWL<16444> A_IWL<16443> A_IWL<16442> A_IWL<16441> A_IWL<16440> A_IWL<16439> A_IWL<16438> A_IWL<16437> A_IWL<16436> A_IWL<16435> A_IWL<16434> A_IWL<16433> A_IWL<16432> A_IWL<16431> A_IWL<16430> A_IWL<16429> A_IWL<16428> A_IWL<16427> A_IWL<16426> A_IWL<16425> A_IWL<16424> A_IWL<16423> A_IWL<16422> A_IWL<16421> A_IWL<16420> A_IWL<16419> A_IWL<16418> A_IWL<16417> A_IWL<16416> A_IWL<16415> A_IWL<16414> A_IWL<16413> A_IWL<16412> A_IWL<16411> A_IWL<16410> A_IWL<16409> A_IWL<16408> A_IWL<16407> A_IWL<16406> A_IWL<16405> A_IWL<16404> A_IWL<16403> A_IWL<16402> A_IWL<16401> A_IWL<16400> A_IWL<16399> A_IWL<16398> A_IWL<16397> A_IWL<16396> A_IWL<16395> A_IWL<16394> A_IWL<16393> A_IWL<16392> A_IWL<16391> A_IWL<16390> A_IWL<16389> A_IWL<16388> A_IWL<16387> A_IWL<16386> A_IWL<16385> A_IWL<16384> VDD_CORE VSS / RM_IHPSG13_8192x32_c4_1P_COLUMN_pcell_0 +XCOL<31> A_BLC<63> A_BLC<62> A_BLC_TOP<63> A_BLC_TOP<62> A_BLT<63> A_BLT<62> A_BLT_TOP<63> A_BLT_TOP<62> A_IWL<15871> A_IWL<15870> A_IWL<15869> A_IWL<15868> A_IWL<15867> A_IWL<15866> A_IWL<15865> A_IWL<15864> A_IWL<15863> A_IWL<15862> A_IWL<15861> A_IWL<15860> A_IWL<15859> A_IWL<15858> A_IWL<15857> A_IWL<15856> A_IWL<15855> A_IWL<15854> A_IWL<15853> A_IWL<15852> A_IWL<15851> A_IWL<15850> A_IWL<15849> A_IWL<15848> A_IWL<15847> A_IWL<15846> A_IWL<15845> A_IWL<15844> A_IWL<15843> A_IWL<15842> A_IWL<15841> A_IWL<15840> A_IWL<15839> A_IWL<15838> A_IWL<15837> A_IWL<15836> A_IWL<15835> A_IWL<15834> A_IWL<15833> A_IWL<15832> A_IWL<15831> A_IWL<15830> A_IWL<15829> A_IWL<15828> A_IWL<15827> A_IWL<15826> A_IWL<15825> A_IWL<15824> A_IWL<15823> A_IWL<15822> A_IWL<15821> A_IWL<15820> A_IWL<15819> A_IWL<15818> A_IWL<15817> A_IWL<15816> A_IWL<15815> A_IWL<15814> A_IWL<15813> A_IWL<15812> A_IWL<15811> A_IWL<15810> A_IWL<15809> A_IWL<15808> A_IWL<15807> A_IWL<15806> A_IWL<15805> A_IWL<15804> A_IWL<15803> A_IWL<15802> A_IWL<15801> A_IWL<15800> A_IWL<15799> A_IWL<15798> A_IWL<15797> A_IWL<15796> A_IWL<15795> A_IWL<15794> A_IWL<15793> A_IWL<15792> A_IWL<15791> A_IWL<15790> A_IWL<15789> A_IWL<15788> A_IWL<15787> A_IWL<15786> A_IWL<15785> A_IWL<15784> A_IWL<15783> A_IWL<15782> A_IWL<15781> A_IWL<15780> A_IWL<15779> A_IWL<15778> A_IWL<15777> A_IWL<15776> A_IWL<15775> A_IWL<15774> A_IWL<15773> A_IWL<15772> A_IWL<15771> A_IWL<15770> A_IWL<15769> A_IWL<15768> A_IWL<15767> A_IWL<15766> A_IWL<15765> A_IWL<15764> A_IWL<15763> A_IWL<15762> A_IWL<15761> A_IWL<15760> A_IWL<15759> A_IWL<15758> A_IWL<15757> A_IWL<15756> A_IWL<15755> A_IWL<15754> A_IWL<15753> A_IWL<15752> A_IWL<15751> A_IWL<15750> A_IWL<15749> A_IWL<15748> A_IWL<15747> A_IWL<15746> A_IWL<15745> A_IWL<15744> A_IWL<15743> A_IWL<15742> A_IWL<15741> A_IWL<15740> A_IWL<15739> A_IWL<15738> A_IWL<15737> A_IWL<15736> A_IWL<15735> A_IWL<15734> A_IWL<15733> A_IWL<15732> A_IWL<15731> A_IWL<15730> A_IWL<15729> A_IWL<15728> A_IWL<15727> A_IWL<15726> A_IWL<15725> A_IWL<15724> A_IWL<15723> A_IWL<15722> A_IWL<15721> A_IWL<15720> A_IWL<15719> A_IWL<15718> A_IWL<15717> A_IWL<15716> A_IWL<15715> A_IWL<15714> A_IWL<15713> A_IWL<15712> A_IWL<15711> A_IWL<15710> A_IWL<15709> A_IWL<15708> A_IWL<15707> A_IWL<15706> A_IWL<15705> A_IWL<15704> A_IWL<15703> A_IWL<15702> A_IWL<15701> A_IWL<15700> A_IWL<15699> A_IWL<15698> A_IWL<15697> A_IWL<15696> A_IWL<15695> A_IWL<15694> A_IWL<15693> A_IWL<15692> A_IWL<15691> A_IWL<15690> A_IWL<15689> A_IWL<15688> A_IWL<15687> A_IWL<15686> A_IWL<15685> A_IWL<15684> A_IWL<15683> A_IWL<15682> A_IWL<15681> A_IWL<15680> A_IWL<15679> A_IWL<15678> A_IWL<15677> A_IWL<15676> A_IWL<15675> A_IWL<15674> A_IWL<15673> A_IWL<15672> A_IWL<15671> A_IWL<15670> A_IWL<15669> A_IWL<15668> A_IWL<15667> A_IWL<15666> A_IWL<15665> A_IWL<15664> A_IWL<15663> A_IWL<15662> A_IWL<15661> A_IWL<15660> A_IWL<15659> A_IWL<15658> A_IWL<15657> A_IWL<15656> A_IWL<15655> A_IWL<15654> A_IWL<15653> A_IWL<15652> A_IWL<15651> A_IWL<15650> A_IWL<15649> A_IWL<15648> A_IWL<15647> A_IWL<15646> A_IWL<15645> A_IWL<15644> A_IWL<15643> A_IWL<15642> A_IWL<15641> A_IWL<15640> A_IWL<15639> A_IWL<15638> A_IWL<15637> A_IWL<15636> A_IWL<15635> A_IWL<15634> A_IWL<15633> A_IWL<15632> A_IWL<15631> A_IWL<15630> A_IWL<15629> A_IWL<15628> A_IWL<15627> A_IWL<15626> A_IWL<15625> A_IWL<15624> A_IWL<15623> A_IWL<15622> A_IWL<15621> A_IWL<15620> A_IWL<15619> A_IWL<15618> A_IWL<15617> A_IWL<15616> A_IWL<15615> A_IWL<15614> A_IWL<15613> A_IWL<15612> A_IWL<15611> A_IWL<15610> A_IWL<15609> A_IWL<15608> A_IWL<15607> A_IWL<15606> A_IWL<15605> A_IWL<15604> A_IWL<15603> A_IWL<15602> A_IWL<15601> A_IWL<15600> A_IWL<15599> A_IWL<15598> A_IWL<15597> A_IWL<15596> A_IWL<15595> A_IWL<15594> A_IWL<15593> A_IWL<15592> A_IWL<15591> A_IWL<15590> A_IWL<15589> A_IWL<15588> A_IWL<15587> A_IWL<15586> A_IWL<15585> A_IWL<15584> A_IWL<15583> A_IWL<15582> A_IWL<15581> A_IWL<15580> A_IWL<15579> A_IWL<15578> A_IWL<15577> A_IWL<15576> A_IWL<15575> A_IWL<15574> A_IWL<15573> A_IWL<15572> A_IWL<15571> A_IWL<15570> A_IWL<15569> A_IWL<15568> A_IWL<15567> A_IWL<15566> A_IWL<15565> A_IWL<15564> A_IWL<15563> A_IWL<15562> A_IWL<15561> A_IWL<15560> A_IWL<15559> A_IWL<15558> A_IWL<15557> A_IWL<15556> A_IWL<15555> A_IWL<15554> A_IWL<15553> A_IWL<15552> A_IWL<15551> A_IWL<15550> A_IWL<15549> A_IWL<15548> A_IWL<15547> A_IWL<15546> A_IWL<15545> A_IWL<15544> A_IWL<15543> A_IWL<15542> A_IWL<15541> A_IWL<15540> A_IWL<15539> A_IWL<15538> A_IWL<15537> A_IWL<15536> A_IWL<15535> A_IWL<15534> A_IWL<15533> A_IWL<15532> A_IWL<15531> A_IWL<15530> A_IWL<15529> A_IWL<15528> A_IWL<15527> A_IWL<15526> A_IWL<15525> A_IWL<15524> A_IWL<15523> A_IWL<15522> A_IWL<15521> A_IWL<15520> A_IWL<15519> A_IWL<15518> A_IWL<15517> A_IWL<15516> A_IWL<15515> A_IWL<15514> A_IWL<15513> A_IWL<15512> A_IWL<15511> A_IWL<15510> A_IWL<15509> A_IWL<15508> A_IWL<15507> A_IWL<15506> A_IWL<15505> A_IWL<15504> A_IWL<15503> A_IWL<15502> A_IWL<15501> A_IWL<15500> A_IWL<15499> A_IWL<15498> A_IWL<15497> A_IWL<15496> A_IWL<15495> A_IWL<15494> A_IWL<15493> A_IWL<15492> A_IWL<15491> A_IWL<15490> A_IWL<15489> A_IWL<15488> A_IWL<15487> A_IWL<15486> A_IWL<15485> A_IWL<15484> A_IWL<15483> A_IWL<15482> A_IWL<15481> A_IWL<15480> A_IWL<15479> A_IWL<15478> A_IWL<15477> A_IWL<15476> A_IWL<15475> A_IWL<15474> A_IWL<15473> A_IWL<15472> A_IWL<15471> A_IWL<15470> A_IWL<15469> A_IWL<15468> A_IWL<15467> A_IWL<15466> A_IWL<15465> A_IWL<15464> A_IWL<15463> A_IWL<15462> A_IWL<15461> A_IWL<15460> A_IWL<15459> A_IWL<15458> A_IWL<15457> A_IWL<15456> A_IWL<15455> A_IWL<15454> A_IWL<15453> A_IWL<15452> A_IWL<15451> A_IWL<15450> A_IWL<15449> A_IWL<15448> A_IWL<15447> A_IWL<15446> A_IWL<15445> A_IWL<15444> A_IWL<15443> A_IWL<15442> A_IWL<15441> A_IWL<15440> A_IWL<15439> A_IWL<15438> A_IWL<15437> A_IWL<15436> A_IWL<15435> A_IWL<15434> A_IWL<15433> A_IWL<15432> A_IWL<15431> A_IWL<15430> A_IWL<15429> A_IWL<15428> A_IWL<15427> A_IWL<15426> A_IWL<15425> A_IWL<15424> A_IWL<15423> A_IWL<15422> A_IWL<15421> A_IWL<15420> A_IWL<15419> A_IWL<15418> A_IWL<15417> A_IWL<15416> A_IWL<15415> A_IWL<15414> A_IWL<15413> A_IWL<15412> A_IWL<15411> A_IWL<15410> A_IWL<15409> A_IWL<15408> A_IWL<15407> A_IWL<15406> A_IWL<15405> A_IWL<15404> A_IWL<15403> A_IWL<15402> A_IWL<15401> A_IWL<15400> A_IWL<15399> A_IWL<15398> A_IWL<15397> A_IWL<15396> A_IWL<15395> A_IWL<15394> A_IWL<15393> A_IWL<15392> A_IWL<15391> A_IWL<15390> A_IWL<15389> A_IWL<15388> A_IWL<15387> A_IWL<15386> A_IWL<15385> A_IWL<15384> A_IWL<15383> A_IWL<15382> A_IWL<15381> A_IWL<15380> A_IWL<15379> A_IWL<15378> A_IWL<15377> A_IWL<15376> A_IWL<15375> A_IWL<15374> A_IWL<15373> A_IWL<15372> A_IWL<15371> A_IWL<15370> A_IWL<15369> A_IWL<15368> A_IWL<15367> A_IWL<15366> A_IWL<15365> A_IWL<15364> A_IWL<15363> A_IWL<15362> A_IWL<15361> A_IWL<15360> A_IWL<16383> A_IWL<16382> A_IWL<16381> A_IWL<16380> A_IWL<16379> A_IWL<16378> A_IWL<16377> A_IWL<16376> A_IWL<16375> A_IWL<16374> A_IWL<16373> A_IWL<16372> A_IWL<16371> A_IWL<16370> A_IWL<16369> A_IWL<16368> A_IWL<16367> A_IWL<16366> A_IWL<16365> A_IWL<16364> A_IWL<16363> A_IWL<16362> A_IWL<16361> A_IWL<16360> A_IWL<16359> A_IWL<16358> A_IWL<16357> A_IWL<16356> A_IWL<16355> A_IWL<16354> A_IWL<16353> A_IWL<16352> A_IWL<16351> A_IWL<16350> A_IWL<16349> A_IWL<16348> A_IWL<16347> A_IWL<16346> A_IWL<16345> A_IWL<16344> A_IWL<16343> A_IWL<16342> A_IWL<16341> A_IWL<16340> A_IWL<16339> A_IWL<16338> A_IWL<16337> A_IWL<16336> A_IWL<16335> A_IWL<16334> A_IWL<16333> A_IWL<16332> A_IWL<16331> A_IWL<16330> A_IWL<16329> A_IWL<16328> A_IWL<16327> A_IWL<16326> A_IWL<16325> A_IWL<16324> A_IWL<16323> A_IWL<16322> A_IWL<16321> A_IWL<16320> A_IWL<16319> A_IWL<16318> A_IWL<16317> A_IWL<16316> A_IWL<16315> A_IWL<16314> A_IWL<16313> A_IWL<16312> A_IWL<16311> A_IWL<16310> A_IWL<16309> A_IWL<16308> A_IWL<16307> A_IWL<16306> A_IWL<16305> A_IWL<16304> A_IWL<16303> A_IWL<16302> A_IWL<16301> A_IWL<16300> A_IWL<16299> A_IWL<16298> A_IWL<16297> A_IWL<16296> A_IWL<16295> A_IWL<16294> A_IWL<16293> A_IWL<16292> A_IWL<16291> A_IWL<16290> A_IWL<16289> A_IWL<16288> A_IWL<16287> A_IWL<16286> A_IWL<16285> A_IWL<16284> A_IWL<16283> A_IWL<16282> A_IWL<16281> A_IWL<16280> A_IWL<16279> A_IWL<16278> A_IWL<16277> A_IWL<16276> A_IWL<16275> A_IWL<16274> A_IWL<16273> A_IWL<16272> A_IWL<16271> A_IWL<16270> A_IWL<16269> A_IWL<16268> A_IWL<16267> A_IWL<16266> A_IWL<16265> A_IWL<16264> A_IWL<16263> A_IWL<16262> A_IWL<16261> A_IWL<16260> A_IWL<16259> A_IWL<16258> A_IWL<16257> A_IWL<16256> A_IWL<16255> A_IWL<16254> A_IWL<16253> A_IWL<16252> A_IWL<16251> A_IWL<16250> A_IWL<16249> A_IWL<16248> A_IWL<16247> A_IWL<16246> A_IWL<16245> A_IWL<16244> A_IWL<16243> A_IWL<16242> A_IWL<16241> A_IWL<16240> A_IWL<16239> A_IWL<16238> A_IWL<16237> A_IWL<16236> A_IWL<16235> A_IWL<16234> A_IWL<16233> A_IWL<16232> A_IWL<16231> A_IWL<16230> A_IWL<16229> A_IWL<16228> A_IWL<16227> A_IWL<16226> A_IWL<16225> A_IWL<16224> A_IWL<16223> A_IWL<16222> A_IWL<16221> A_IWL<16220> A_IWL<16219> A_IWL<16218> A_IWL<16217> A_IWL<16216> A_IWL<16215> A_IWL<16214> A_IWL<16213> A_IWL<16212> A_IWL<16211> A_IWL<16210> A_IWL<16209> A_IWL<16208> A_IWL<16207> A_IWL<16206> A_IWL<16205> A_IWL<16204> A_IWL<16203> A_IWL<16202> A_IWL<16201> A_IWL<16200> A_IWL<16199> A_IWL<16198> A_IWL<16197> A_IWL<16196> A_IWL<16195> A_IWL<16194> A_IWL<16193> A_IWL<16192> A_IWL<16191> A_IWL<16190> A_IWL<16189> A_IWL<16188> A_IWL<16187> A_IWL<16186> A_IWL<16185> A_IWL<16184> A_IWL<16183> A_IWL<16182> A_IWL<16181> A_IWL<16180> A_IWL<16179> A_IWL<16178> A_IWL<16177> A_IWL<16176> A_IWL<16175> A_IWL<16174> A_IWL<16173> A_IWL<16172> A_IWL<16171> A_IWL<16170> A_IWL<16169> A_IWL<16168> A_IWL<16167> A_IWL<16166> A_IWL<16165> A_IWL<16164> A_IWL<16163> A_IWL<16162> A_IWL<16161> A_IWL<16160> A_IWL<16159> A_IWL<16158> A_IWL<16157> A_IWL<16156> A_IWL<16155> A_IWL<16154> A_IWL<16153> A_IWL<16152> A_IWL<16151> A_IWL<16150> A_IWL<16149> A_IWL<16148> A_IWL<16147> A_IWL<16146> A_IWL<16145> A_IWL<16144> A_IWL<16143> A_IWL<16142> A_IWL<16141> A_IWL<16140> A_IWL<16139> A_IWL<16138> A_IWL<16137> A_IWL<16136> A_IWL<16135> A_IWL<16134> A_IWL<16133> A_IWL<16132> A_IWL<16131> A_IWL<16130> A_IWL<16129> A_IWL<16128> A_IWL<16127> A_IWL<16126> A_IWL<16125> A_IWL<16124> A_IWL<16123> A_IWL<16122> A_IWL<16121> A_IWL<16120> A_IWL<16119> A_IWL<16118> A_IWL<16117> A_IWL<16116> A_IWL<16115> A_IWL<16114> A_IWL<16113> A_IWL<16112> A_IWL<16111> A_IWL<16110> A_IWL<16109> A_IWL<16108> A_IWL<16107> A_IWL<16106> A_IWL<16105> A_IWL<16104> A_IWL<16103> A_IWL<16102> A_IWL<16101> A_IWL<16100> A_IWL<16099> A_IWL<16098> A_IWL<16097> A_IWL<16096> A_IWL<16095> A_IWL<16094> A_IWL<16093> A_IWL<16092> A_IWL<16091> A_IWL<16090> A_IWL<16089> A_IWL<16088> A_IWL<16087> A_IWL<16086> A_IWL<16085> A_IWL<16084> A_IWL<16083> A_IWL<16082> A_IWL<16081> A_IWL<16080> A_IWL<16079> A_IWL<16078> A_IWL<16077> A_IWL<16076> A_IWL<16075> A_IWL<16074> A_IWL<16073> A_IWL<16072> A_IWL<16071> A_IWL<16070> A_IWL<16069> A_IWL<16068> A_IWL<16067> A_IWL<16066> A_IWL<16065> A_IWL<16064> A_IWL<16063> A_IWL<16062> A_IWL<16061> A_IWL<16060> A_IWL<16059> A_IWL<16058> A_IWL<16057> A_IWL<16056> A_IWL<16055> A_IWL<16054> A_IWL<16053> A_IWL<16052> A_IWL<16051> A_IWL<16050> A_IWL<16049> A_IWL<16048> A_IWL<16047> A_IWL<16046> A_IWL<16045> A_IWL<16044> A_IWL<16043> A_IWL<16042> A_IWL<16041> A_IWL<16040> A_IWL<16039> A_IWL<16038> A_IWL<16037> A_IWL<16036> A_IWL<16035> A_IWL<16034> A_IWL<16033> A_IWL<16032> A_IWL<16031> A_IWL<16030> A_IWL<16029> A_IWL<16028> A_IWL<16027> A_IWL<16026> A_IWL<16025> A_IWL<16024> A_IWL<16023> A_IWL<16022> A_IWL<16021> A_IWL<16020> A_IWL<16019> A_IWL<16018> A_IWL<16017> A_IWL<16016> A_IWL<16015> A_IWL<16014> A_IWL<16013> A_IWL<16012> A_IWL<16011> A_IWL<16010> A_IWL<16009> A_IWL<16008> A_IWL<16007> A_IWL<16006> A_IWL<16005> A_IWL<16004> A_IWL<16003> A_IWL<16002> A_IWL<16001> A_IWL<16000> A_IWL<15999> A_IWL<15998> A_IWL<15997> A_IWL<15996> A_IWL<15995> A_IWL<15994> A_IWL<15993> A_IWL<15992> A_IWL<15991> A_IWL<15990> A_IWL<15989> A_IWL<15988> A_IWL<15987> A_IWL<15986> A_IWL<15985> A_IWL<15984> A_IWL<15983> A_IWL<15982> A_IWL<15981> A_IWL<15980> A_IWL<15979> A_IWL<15978> A_IWL<15977> A_IWL<15976> A_IWL<15975> A_IWL<15974> A_IWL<15973> A_IWL<15972> A_IWL<15971> A_IWL<15970> A_IWL<15969> A_IWL<15968> A_IWL<15967> A_IWL<15966> A_IWL<15965> A_IWL<15964> A_IWL<15963> A_IWL<15962> A_IWL<15961> A_IWL<15960> A_IWL<15959> A_IWL<15958> A_IWL<15957> A_IWL<15956> A_IWL<15955> A_IWL<15954> A_IWL<15953> A_IWL<15952> A_IWL<15951> A_IWL<15950> A_IWL<15949> A_IWL<15948> A_IWL<15947> A_IWL<15946> A_IWL<15945> A_IWL<15944> A_IWL<15943> A_IWL<15942> A_IWL<15941> A_IWL<15940> A_IWL<15939> A_IWL<15938> A_IWL<15937> A_IWL<15936> A_IWL<15935> A_IWL<15934> A_IWL<15933> A_IWL<15932> A_IWL<15931> A_IWL<15930> A_IWL<15929> A_IWL<15928> A_IWL<15927> A_IWL<15926> A_IWL<15925> A_IWL<15924> A_IWL<15923> A_IWL<15922> A_IWL<15921> A_IWL<15920> A_IWL<15919> A_IWL<15918> A_IWL<15917> A_IWL<15916> A_IWL<15915> A_IWL<15914> A_IWL<15913> A_IWL<15912> A_IWL<15911> A_IWL<15910> A_IWL<15909> A_IWL<15908> A_IWL<15907> A_IWL<15906> A_IWL<15905> A_IWL<15904> A_IWL<15903> A_IWL<15902> A_IWL<15901> A_IWL<15900> A_IWL<15899> A_IWL<15898> A_IWL<15897> A_IWL<15896> A_IWL<15895> A_IWL<15894> A_IWL<15893> A_IWL<15892> A_IWL<15891> A_IWL<15890> A_IWL<15889> A_IWL<15888> A_IWL<15887> A_IWL<15886> A_IWL<15885> A_IWL<15884> A_IWL<15883> A_IWL<15882> A_IWL<15881> A_IWL<15880> A_IWL<15879> A_IWL<15878> A_IWL<15877> A_IWL<15876> A_IWL<15875> A_IWL<15874> A_IWL<15873> A_IWL<15872> VDD_CORE VSS / RM_IHPSG13_8192x32_c4_1P_COLUMN_pcell_0 +XCOL<30> A_BLC<61> A_BLC<60> A_BLC_TOP<61> A_BLC_TOP<60> A_BLT<61> A_BLT<60> A_BLT_TOP<61> A_BLT_TOP<60> A_IWL<15359> A_IWL<15358> A_IWL<15357> A_IWL<15356> A_IWL<15355> A_IWL<15354> A_IWL<15353> A_IWL<15352> A_IWL<15351> A_IWL<15350> A_IWL<15349> A_IWL<15348> A_IWL<15347> A_IWL<15346> A_IWL<15345> A_IWL<15344> A_IWL<15343> A_IWL<15342> A_IWL<15341> A_IWL<15340> A_IWL<15339> A_IWL<15338> A_IWL<15337> A_IWL<15336> A_IWL<15335> A_IWL<15334> A_IWL<15333> A_IWL<15332> A_IWL<15331> A_IWL<15330> A_IWL<15329> A_IWL<15328> A_IWL<15327> A_IWL<15326> A_IWL<15325> A_IWL<15324> A_IWL<15323> A_IWL<15322> A_IWL<15321> A_IWL<15320> A_IWL<15319> A_IWL<15318> A_IWL<15317> A_IWL<15316> A_IWL<15315> A_IWL<15314> A_IWL<15313> A_IWL<15312> A_IWL<15311> A_IWL<15310> A_IWL<15309> A_IWL<15308> A_IWL<15307> A_IWL<15306> A_IWL<15305> A_IWL<15304> A_IWL<15303> A_IWL<15302> A_IWL<15301> A_IWL<15300> A_IWL<15299> A_IWL<15298> A_IWL<15297> A_IWL<15296> A_IWL<15295> A_IWL<15294> A_IWL<15293> A_IWL<15292> A_IWL<15291> A_IWL<15290> A_IWL<15289> A_IWL<15288> A_IWL<15287> A_IWL<15286> A_IWL<15285> A_IWL<15284> A_IWL<15283> A_IWL<15282> A_IWL<15281> A_IWL<15280> A_IWL<15279> A_IWL<15278> A_IWL<15277> A_IWL<15276> A_IWL<15275> A_IWL<15274> A_IWL<15273> A_IWL<15272> A_IWL<15271> A_IWL<15270> A_IWL<15269> A_IWL<15268> A_IWL<15267> A_IWL<15266> A_IWL<15265> A_IWL<15264> A_IWL<15263> A_IWL<15262> A_IWL<15261> A_IWL<15260> A_IWL<15259> A_IWL<15258> A_IWL<15257> A_IWL<15256> A_IWL<15255> A_IWL<15254> A_IWL<15253> A_IWL<15252> A_IWL<15251> A_IWL<15250> A_IWL<15249> A_IWL<15248> A_IWL<15247> A_IWL<15246> A_IWL<15245> A_IWL<15244> A_IWL<15243> A_IWL<15242> A_IWL<15241> A_IWL<15240> A_IWL<15239> A_IWL<15238> A_IWL<15237> A_IWL<15236> A_IWL<15235> A_IWL<15234> A_IWL<15233> A_IWL<15232> A_IWL<15231> A_IWL<15230> A_IWL<15229> A_IWL<15228> A_IWL<15227> A_IWL<15226> A_IWL<15225> A_IWL<15224> A_IWL<15223> A_IWL<15222> A_IWL<15221> A_IWL<15220> A_IWL<15219> A_IWL<15218> A_IWL<15217> A_IWL<15216> A_IWL<15215> A_IWL<15214> A_IWL<15213> A_IWL<15212> A_IWL<15211> A_IWL<15210> A_IWL<15209> A_IWL<15208> A_IWL<15207> A_IWL<15206> A_IWL<15205> A_IWL<15204> A_IWL<15203> A_IWL<15202> A_IWL<15201> A_IWL<15200> A_IWL<15199> A_IWL<15198> A_IWL<15197> A_IWL<15196> A_IWL<15195> A_IWL<15194> A_IWL<15193> A_IWL<15192> A_IWL<15191> A_IWL<15190> A_IWL<15189> A_IWL<15188> A_IWL<15187> A_IWL<15186> A_IWL<15185> A_IWL<15184> A_IWL<15183> A_IWL<15182> A_IWL<15181> A_IWL<15180> A_IWL<15179> A_IWL<15178> A_IWL<15177> A_IWL<15176> A_IWL<15175> A_IWL<15174> A_IWL<15173> A_IWL<15172> A_IWL<15171> A_IWL<15170> A_IWL<15169> A_IWL<15168> A_IWL<15167> A_IWL<15166> A_IWL<15165> A_IWL<15164> A_IWL<15163> A_IWL<15162> A_IWL<15161> A_IWL<15160> A_IWL<15159> A_IWL<15158> A_IWL<15157> A_IWL<15156> A_IWL<15155> A_IWL<15154> A_IWL<15153> A_IWL<15152> A_IWL<15151> A_IWL<15150> A_IWL<15149> A_IWL<15148> A_IWL<15147> A_IWL<15146> A_IWL<15145> A_IWL<15144> A_IWL<15143> A_IWL<15142> A_IWL<15141> A_IWL<15140> A_IWL<15139> A_IWL<15138> A_IWL<15137> A_IWL<15136> A_IWL<15135> A_IWL<15134> A_IWL<15133> A_IWL<15132> A_IWL<15131> A_IWL<15130> A_IWL<15129> A_IWL<15128> A_IWL<15127> A_IWL<15126> A_IWL<15125> A_IWL<15124> A_IWL<15123> A_IWL<15122> A_IWL<15121> A_IWL<15120> A_IWL<15119> A_IWL<15118> A_IWL<15117> A_IWL<15116> A_IWL<15115> A_IWL<15114> A_IWL<15113> A_IWL<15112> A_IWL<15111> A_IWL<15110> A_IWL<15109> A_IWL<15108> A_IWL<15107> A_IWL<15106> A_IWL<15105> A_IWL<15104> A_IWL<15103> A_IWL<15102> A_IWL<15101> A_IWL<15100> A_IWL<15099> A_IWL<15098> A_IWL<15097> A_IWL<15096> A_IWL<15095> A_IWL<15094> A_IWL<15093> A_IWL<15092> A_IWL<15091> A_IWL<15090> A_IWL<15089> A_IWL<15088> A_IWL<15087> A_IWL<15086> A_IWL<15085> A_IWL<15084> A_IWL<15083> A_IWL<15082> A_IWL<15081> A_IWL<15080> A_IWL<15079> A_IWL<15078> A_IWL<15077> A_IWL<15076> A_IWL<15075> A_IWL<15074> A_IWL<15073> A_IWL<15072> A_IWL<15071> A_IWL<15070> A_IWL<15069> A_IWL<15068> A_IWL<15067> A_IWL<15066> A_IWL<15065> A_IWL<15064> A_IWL<15063> A_IWL<15062> A_IWL<15061> A_IWL<15060> A_IWL<15059> A_IWL<15058> A_IWL<15057> A_IWL<15056> A_IWL<15055> A_IWL<15054> A_IWL<15053> A_IWL<15052> A_IWL<15051> A_IWL<15050> A_IWL<15049> A_IWL<15048> A_IWL<15047> A_IWL<15046> A_IWL<15045> A_IWL<15044> A_IWL<15043> A_IWL<15042> A_IWL<15041> A_IWL<15040> A_IWL<15039> A_IWL<15038> A_IWL<15037> A_IWL<15036> A_IWL<15035> A_IWL<15034> A_IWL<15033> A_IWL<15032> A_IWL<15031> A_IWL<15030> A_IWL<15029> A_IWL<15028> A_IWL<15027> A_IWL<15026> A_IWL<15025> A_IWL<15024> A_IWL<15023> A_IWL<15022> A_IWL<15021> A_IWL<15020> A_IWL<15019> A_IWL<15018> A_IWL<15017> A_IWL<15016> A_IWL<15015> A_IWL<15014> A_IWL<15013> A_IWL<15012> A_IWL<15011> A_IWL<15010> A_IWL<15009> A_IWL<15008> A_IWL<15007> A_IWL<15006> A_IWL<15005> A_IWL<15004> A_IWL<15003> A_IWL<15002> A_IWL<15001> A_IWL<15000> A_IWL<14999> A_IWL<14998> A_IWL<14997> A_IWL<14996> A_IWL<14995> A_IWL<14994> A_IWL<14993> A_IWL<14992> A_IWL<14991> A_IWL<14990> A_IWL<14989> A_IWL<14988> A_IWL<14987> A_IWL<14986> A_IWL<14985> A_IWL<14984> A_IWL<14983> A_IWL<14982> A_IWL<14981> A_IWL<14980> A_IWL<14979> A_IWL<14978> A_IWL<14977> A_IWL<14976> A_IWL<14975> A_IWL<14974> A_IWL<14973> A_IWL<14972> A_IWL<14971> A_IWL<14970> A_IWL<14969> A_IWL<14968> A_IWL<14967> A_IWL<14966> A_IWL<14965> A_IWL<14964> A_IWL<14963> A_IWL<14962> A_IWL<14961> A_IWL<14960> A_IWL<14959> A_IWL<14958> A_IWL<14957> A_IWL<14956> A_IWL<14955> A_IWL<14954> A_IWL<14953> A_IWL<14952> A_IWL<14951> A_IWL<14950> A_IWL<14949> A_IWL<14948> A_IWL<14947> A_IWL<14946> A_IWL<14945> A_IWL<14944> A_IWL<14943> A_IWL<14942> A_IWL<14941> A_IWL<14940> A_IWL<14939> A_IWL<14938> A_IWL<14937> A_IWL<14936> A_IWL<14935> A_IWL<14934> A_IWL<14933> A_IWL<14932> A_IWL<14931> A_IWL<14930> A_IWL<14929> A_IWL<14928> A_IWL<14927> A_IWL<14926> A_IWL<14925> A_IWL<14924> A_IWL<14923> A_IWL<14922> A_IWL<14921> A_IWL<14920> A_IWL<14919> A_IWL<14918> A_IWL<14917> A_IWL<14916> A_IWL<14915> A_IWL<14914> A_IWL<14913> A_IWL<14912> A_IWL<14911> A_IWL<14910> A_IWL<14909> A_IWL<14908> A_IWL<14907> A_IWL<14906> A_IWL<14905> A_IWL<14904> A_IWL<14903> A_IWL<14902> A_IWL<14901> A_IWL<14900> A_IWL<14899> A_IWL<14898> A_IWL<14897> A_IWL<14896> A_IWL<14895> A_IWL<14894> A_IWL<14893> A_IWL<14892> A_IWL<14891> A_IWL<14890> A_IWL<14889> A_IWL<14888> A_IWL<14887> A_IWL<14886> A_IWL<14885> A_IWL<14884> A_IWL<14883> A_IWL<14882> A_IWL<14881> A_IWL<14880> A_IWL<14879> A_IWL<14878> A_IWL<14877> A_IWL<14876> A_IWL<14875> A_IWL<14874> A_IWL<14873> A_IWL<14872> A_IWL<14871> A_IWL<14870> A_IWL<14869> A_IWL<14868> A_IWL<14867> A_IWL<14866> A_IWL<14865> A_IWL<14864> A_IWL<14863> A_IWL<14862> A_IWL<14861> A_IWL<14860> A_IWL<14859> A_IWL<14858> A_IWL<14857> A_IWL<14856> A_IWL<14855> A_IWL<14854> A_IWL<14853> A_IWL<14852> A_IWL<14851> A_IWL<14850> A_IWL<14849> A_IWL<14848> A_IWL<15871> A_IWL<15870> A_IWL<15869> A_IWL<15868> A_IWL<15867> A_IWL<15866> A_IWL<15865> A_IWL<15864> A_IWL<15863> A_IWL<15862> A_IWL<15861> A_IWL<15860> A_IWL<15859> A_IWL<15858> A_IWL<15857> A_IWL<15856> A_IWL<15855> A_IWL<15854> A_IWL<15853> A_IWL<15852> A_IWL<15851> A_IWL<15850> A_IWL<15849> A_IWL<15848> A_IWL<15847> A_IWL<15846> A_IWL<15845> A_IWL<15844> A_IWL<15843> A_IWL<15842> A_IWL<15841> A_IWL<15840> A_IWL<15839> A_IWL<15838> A_IWL<15837> A_IWL<15836> A_IWL<15835> A_IWL<15834> A_IWL<15833> A_IWL<15832> A_IWL<15831> A_IWL<15830> A_IWL<15829> A_IWL<15828> A_IWL<15827> A_IWL<15826> A_IWL<15825> A_IWL<15824> A_IWL<15823> A_IWL<15822> A_IWL<15821> A_IWL<15820> A_IWL<15819> A_IWL<15818> A_IWL<15817> A_IWL<15816> A_IWL<15815> A_IWL<15814> A_IWL<15813> A_IWL<15812> A_IWL<15811> A_IWL<15810> A_IWL<15809> A_IWL<15808> A_IWL<15807> A_IWL<15806> A_IWL<15805> A_IWL<15804> A_IWL<15803> A_IWL<15802> A_IWL<15801> A_IWL<15800> A_IWL<15799> A_IWL<15798> A_IWL<15797> A_IWL<15796> A_IWL<15795> A_IWL<15794> A_IWL<15793> A_IWL<15792> A_IWL<15791> A_IWL<15790> A_IWL<15789> A_IWL<15788> A_IWL<15787> A_IWL<15786> A_IWL<15785> A_IWL<15784> A_IWL<15783> A_IWL<15782> A_IWL<15781> A_IWL<15780> A_IWL<15779> A_IWL<15778> A_IWL<15777> A_IWL<15776> A_IWL<15775> A_IWL<15774> A_IWL<15773> A_IWL<15772> A_IWL<15771> A_IWL<15770> A_IWL<15769> A_IWL<15768> A_IWL<15767> A_IWL<15766> A_IWL<15765> A_IWL<15764> A_IWL<15763> A_IWL<15762> A_IWL<15761> A_IWL<15760> A_IWL<15759> A_IWL<15758> A_IWL<15757> A_IWL<15756> A_IWL<15755> A_IWL<15754> A_IWL<15753> A_IWL<15752> A_IWL<15751> A_IWL<15750> A_IWL<15749> A_IWL<15748> A_IWL<15747> A_IWL<15746> A_IWL<15745> A_IWL<15744> A_IWL<15743> A_IWL<15742> A_IWL<15741> A_IWL<15740> A_IWL<15739> A_IWL<15738> A_IWL<15737> A_IWL<15736> A_IWL<15735> A_IWL<15734> A_IWL<15733> A_IWL<15732> A_IWL<15731> A_IWL<15730> A_IWL<15729> A_IWL<15728> A_IWL<15727> A_IWL<15726> A_IWL<15725> A_IWL<15724> A_IWL<15723> A_IWL<15722> A_IWL<15721> A_IWL<15720> A_IWL<15719> A_IWL<15718> A_IWL<15717> A_IWL<15716> A_IWL<15715> A_IWL<15714> A_IWL<15713> A_IWL<15712> A_IWL<15711> A_IWL<15710> A_IWL<15709> A_IWL<15708> A_IWL<15707> A_IWL<15706> A_IWL<15705> A_IWL<15704> A_IWL<15703> A_IWL<15702> A_IWL<15701> A_IWL<15700> A_IWL<15699> A_IWL<15698> A_IWL<15697> A_IWL<15696> A_IWL<15695> A_IWL<15694> A_IWL<15693> A_IWL<15692> A_IWL<15691> A_IWL<15690> A_IWL<15689> A_IWL<15688> A_IWL<15687> A_IWL<15686> A_IWL<15685> A_IWL<15684> A_IWL<15683> A_IWL<15682> A_IWL<15681> A_IWL<15680> A_IWL<15679> A_IWL<15678> A_IWL<15677> A_IWL<15676> A_IWL<15675> A_IWL<15674> A_IWL<15673> A_IWL<15672> A_IWL<15671> A_IWL<15670> A_IWL<15669> A_IWL<15668> A_IWL<15667> A_IWL<15666> A_IWL<15665> A_IWL<15664> A_IWL<15663> A_IWL<15662> A_IWL<15661> A_IWL<15660> A_IWL<15659> A_IWL<15658> A_IWL<15657> A_IWL<15656> A_IWL<15655> A_IWL<15654> A_IWL<15653> A_IWL<15652> A_IWL<15651> A_IWL<15650> A_IWL<15649> A_IWL<15648> A_IWL<15647> A_IWL<15646> A_IWL<15645> A_IWL<15644> A_IWL<15643> A_IWL<15642> A_IWL<15641> A_IWL<15640> A_IWL<15639> A_IWL<15638> A_IWL<15637> A_IWL<15636> A_IWL<15635> A_IWL<15634> A_IWL<15633> A_IWL<15632> A_IWL<15631> A_IWL<15630> A_IWL<15629> A_IWL<15628> A_IWL<15627> A_IWL<15626> A_IWL<15625> A_IWL<15624> A_IWL<15623> A_IWL<15622> A_IWL<15621> A_IWL<15620> A_IWL<15619> A_IWL<15618> A_IWL<15617> A_IWL<15616> A_IWL<15615> A_IWL<15614> A_IWL<15613> A_IWL<15612> A_IWL<15611> A_IWL<15610> A_IWL<15609> A_IWL<15608> A_IWL<15607> A_IWL<15606> A_IWL<15605> A_IWL<15604> A_IWL<15603> A_IWL<15602> A_IWL<15601> A_IWL<15600> A_IWL<15599> A_IWL<15598> A_IWL<15597> A_IWL<15596> A_IWL<15595> A_IWL<15594> A_IWL<15593> A_IWL<15592> A_IWL<15591> A_IWL<15590> A_IWL<15589> A_IWL<15588> A_IWL<15587> A_IWL<15586> A_IWL<15585> A_IWL<15584> A_IWL<15583> A_IWL<15582> A_IWL<15581> A_IWL<15580> A_IWL<15579> A_IWL<15578> A_IWL<15577> A_IWL<15576> A_IWL<15575> A_IWL<15574> A_IWL<15573> A_IWL<15572> A_IWL<15571> A_IWL<15570> A_IWL<15569> A_IWL<15568> A_IWL<15567> A_IWL<15566> A_IWL<15565> A_IWL<15564> A_IWL<15563> A_IWL<15562> A_IWL<15561> A_IWL<15560> A_IWL<15559> A_IWL<15558> A_IWL<15557> A_IWL<15556> A_IWL<15555> A_IWL<15554> A_IWL<15553> A_IWL<15552> A_IWL<15551> A_IWL<15550> A_IWL<15549> A_IWL<15548> A_IWL<15547> A_IWL<15546> A_IWL<15545> A_IWL<15544> A_IWL<15543> A_IWL<15542> A_IWL<15541> A_IWL<15540> A_IWL<15539> A_IWL<15538> A_IWL<15537> A_IWL<15536> A_IWL<15535> A_IWL<15534> A_IWL<15533> A_IWL<15532> A_IWL<15531> A_IWL<15530> A_IWL<15529> A_IWL<15528> A_IWL<15527> A_IWL<15526> A_IWL<15525> A_IWL<15524> A_IWL<15523> A_IWL<15522> A_IWL<15521> A_IWL<15520> A_IWL<15519> A_IWL<15518> A_IWL<15517> A_IWL<15516> A_IWL<15515> A_IWL<15514> A_IWL<15513> A_IWL<15512> A_IWL<15511> A_IWL<15510> A_IWL<15509> A_IWL<15508> A_IWL<15507> A_IWL<15506> A_IWL<15505> A_IWL<15504> A_IWL<15503> A_IWL<15502> A_IWL<15501> A_IWL<15500> A_IWL<15499> A_IWL<15498> A_IWL<15497> A_IWL<15496> A_IWL<15495> A_IWL<15494> A_IWL<15493> A_IWL<15492> A_IWL<15491> A_IWL<15490> A_IWL<15489> A_IWL<15488> A_IWL<15487> A_IWL<15486> A_IWL<15485> A_IWL<15484> A_IWL<15483> A_IWL<15482> A_IWL<15481> A_IWL<15480> A_IWL<15479> A_IWL<15478> A_IWL<15477> A_IWL<15476> A_IWL<15475> A_IWL<15474> A_IWL<15473> A_IWL<15472> A_IWL<15471> A_IWL<15470> A_IWL<15469> A_IWL<15468> A_IWL<15467> A_IWL<15466> A_IWL<15465> A_IWL<15464> A_IWL<15463> A_IWL<15462> A_IWL<15461> A_IWL<15460> A_IWL<15459> A_IWL<15458> A_IWL<15457> A_IWL<15456> A_IWL<15455> A_IWL<15454> A_IWL<15453> A_IWL<15452> A_IWL<15451> A_IWL<15450> A_IWL<15449> A_IWL<15448> A_IWL<15447> A_IWL<15446> A_IWL<15445> A_IWL<15444> A_IWL<15443> A_IWL<15442> A_IWL<15441> A_IWL<15440> A_IWL<15439> A_IWL<15438> A_IWL<15437> A_IWL<15436> A_IWL<15435> A_IWL<15434> A_IWL<15433> A_IWL<15432> A_IWL<15431> A_IWL<15430> A_IWL<15429> A_IWL<15428> A_IWL<15427> A_IWL<15426> A_IWL<15425> A_IWL<15424> A_IWL<15423> A_IWL<15422> A_IWL<15421> A_IWL<15420> A_IWL<15419> A_IWL<15418> A_IWL<15417> A_IWL<15416> A_IWL<15415> A_IWL<15414> A_IWL<15413> A_IWL<15412> A_IWL<15411> A_IWL<15410> A_IWL<15409> A_IWL<15408> A_IWL<15407> A_IWL<15406> A_IWL<15405> A_IWL<15404> A_IWL<15403> A_IWL<15402> A_IWL<15401> A_IWL<15400> A_IWL<15399> A_IWL<15398> A_IWL<15397> A_IWL<15396> A_IWL<15395> A_IWL<15394> A_IWL<15393> A_IWL<15392> A_IWL<15391> A_IWL<15390> A_IWL<15389> A_IWL<15388> A_IWL<15387> A_IWL<15386> A_IWL<15385> A_IWL<15384> A_IWL<15383> A_IWL<15382> A_IWL<15381> A_IWL<15380> A_IWL<15379> A_IWL<15378> A_IWL<15377> A_IWL<15376> A_IWL<15375> A_IWL<15374> A_IWL<15373> A_IWL<15372> A_IWL<15371> A_IWL<15370> A_IWL<15369> A_IWL<15368> A_IWL<15367> A_IWL<15366> A_IWL<15365> A_IWL<15364> A_IWL<15363> A_IWL<15362> A_IWL<15361> A_IWL<15360> VDD_CORE VSS / RM_IHPSG13_8192x32_c4_1P_COLUMN_pcell_0 +XCOL<29> A_BLC<59> A_BLC<58> A_BLC_TOP<59> A_BLC_TOP<58> A_BLT<59> A_BLT<58> A_BLT_TOP<59> A_BLT_TOP<58> A_IWL<14847> A_IWL<14846> A_IWL<14845> A_IWL<14844> A_IWL<14843> A_IWL<14842> A_IWL<14841> A_IWL<14840> A_IWL<14839> A_IWL<14838> A_IWL<14837> A_IWL<14836> A_IWL<14835> A_IWL<14834> A_IWL<14833> A_IWL<14832> A_IWL<14831> A_IWL<14830> A_IWL<14829> A_IWL<14828> A_IWL<14827> A_IWL<14826> A_IWL<14825> A_IWL<14824> A_IWL<14823> A_IWL<14822> A_IWL<14821> A_IWL<14820> A_IWL<14819> A_IWL<14818> A_IWL<14817> A_IWL<14816> A_IWL<14815> A_IWL<14814> A_IWL<14813> A_IWL<14812> A_IWL<14811> A_IWL<14810> A_IWL<14809> A_IWL<14808> A_IWL<14807> A_IWL<14806> A_IWL<14805> A_IWL<14804> A_IWL<14803> A_IWL<14802> A_IWL<14801> A_IWL<14800> A_IWL<14799> A_IWL<14798> A_IWL<14797> A_IWL<14796> A_IWL<14795> A_IWL<14794> A_IWL<14793> A_IWL<14792> A_IWL<14791> A_IWL<14790> A_IWL<14789> A_IWL<14788> A_IWL<14787> A_IWL<14786> A_IWL<14785> A_IWL<14784> A_IWL<14783> A_IWL<14782> A_IWL<14781> A_IWL<14780> A_IWL<14779> A_IWL<14778> A_IWL<14777> A_IWL<14776> A_IWL<14775> A_IWL<14774> A_IWL<14773> A_IWL<14772> A_IWL<14771> A_IWL<14770> A_IWL<14769> A_IWL<14768> A_IWL<14767> A_IWL<14766> A_IWL<14765> A_IWL<14764> A_IWL<14763> A_IWL<14762> A_IWL<14761> A_IWL<14760> A_IWL<14759> A_IWL<14758> A_IWL<14757> A_IWL<14756> A_IWL<14755> A_IWL<14754> A_IWL<14753> A_IWL<14752> A_IWL<14751> A_IWL<14750> A_IWL<14749> A_IWL<14748> A_IWL<14747> A_IWL<14746> A_IWL<14745> A_IWL<14744> A_IWL<14743> A_IWL<14742> A_IWL<14741> A_IWL<14740> A_IWL<14739> A_IWL<14738> A_IWL<14737> A_IWL<14736> A_IWL<14735> A_IWL<14734> A_IWL<14733> A_IWL<14732> A_IWL<14731> A_IWL<14730> A_IWL<14729> A_IWL<14728> A_IWL<14727> A_IWL<14726> A_IWL<14725> A_IWL<14724> A_IWL<14723> A_IWL<14722> A_IWL<14721> A_IWL<14720> A_IWL<14719> A_IWL<14718> A_IWL<14717> A_IWL<14716> A_IWL<14715> A_IWL<14714> A_IWL<14713> A_IWL<14712> A_IWL<14711> A_IWL<14710> A_IWL<14709> A_IWL<14708> A_IWL<14707> A_IWL<14706> A_IWL<14705> A_IWL<14704> A_IWL<14703> A_IWL<14702> A_IWL<14701> A_IWL<14700> A_IWL<14699> A_IWL<14698> A_IWL<14697> A_IWL<14696> A_IWL<14695> A_IWL<14694> A_IWL<14693> A_IWL<14692> A_IWL<14691> A_IWL<14690> A_IWL<14689> A_IWL<14688> A_IWL<14687> A_IWL<14686> A_IWL<14685> A_IWL<14684> A_IWL<14683> A_IWL<14682> A_IWL<14681> A_IWL<14680> A_IWL<14679> A_IWL<14678> A_IWL<14677> A_IWL<14676> A_IWL<14675> A_IWL<14674> A_IWL<14673> A_IWL<14672> A_IWL<14671> A_IWL<14670> A_IWL<14669> A_IWL<14668> A_IWL<14667> A_IWL<14666> A_IWL<14665> A_IWL<14664> A_IWL<14663> A_IWL<14662> A_IWL<14661> A_IWL<14660> A_IWL<14659> A_IWL<14658> A_IWL<14657> A_IWL<14656> A_IWL<14655> A_IWL<14654> A_IWL<14653> A_IWL<14652> A_IWL<14651> A_IWL<14650> A_IWL<14649> A_IWL<14648> A_IWL<14647> A_IWL<14646> A_IWL<14645> A_IWL<14644> A_IWL<14643> A_IWL<14642> A_IWL<14641> A_IWL<14640> A_IWL<14639> A_IWL<14638> A_IWL<14637> A_IWL<14636> A_IWL<14635> A_IWL<14634> A_IWL<14633> A_IWL<14632> A_IWL<14631> A_IWL<14630> A_IWL<14629> A_IWL<14628> A_IWL<14627> A_IWL<14626> A_IWL<14625> A_IWL<14624> A_IWL<14623> A_IWL<14622> A_IWL<14621> A_IWL<14620> A_IWL<14619> A_IWL<14618> A_IWL<14617> A_IWL<14616> A_IWL<14615> A_IWL<14614> A_IWL<14613> A_IWL<14612> A_IWL<14611> A_IWL<14610> A_IWL<14609> A_IWL<14608> A_IWL<14607> A_IWL<14606> A_IWL<14605> A_IWL<14604> A_IWL<14603> A_IWL<14602> A_IWL<14601> A_IWL<14600> A_IWL<14599> A_IWL<14598> A_IWL<14597> A_IWL<14596> A_IWL<14595> A_IWL<14594> A_IWL<14593> A_IWL<14592> A_IWL<14591> A_IWL<14590> A_IWL<14589> A_IWL<14588> A_IWL<14587> A_IWL<14586> A_IWL<14585> A_IWL<14584> A_IWL<14583> A_IWL<14582> A_IWL<14581> A_IWL<14580> A_IWL<14579> A_IWL<14578> A_IWL<14577> A_IWL<14576> A_IWL<14575> A_IWL<14574> A_IWL<14573> A_IWL<14572> A_IWL<14571> A_IWL<14570> A_IWL<14569> A_IWL<14568> A_IWL<14567> A_IWL<14566> A_IWL<14565> A_IWL<14564> A_IWL<14563> A_IWL<14562> A_IWL<14561> A_IWL<14560> A_IWL<14559> A_IWL<14558> A_IWL<14557> A_IWL<14556> A_IWL<14555> A_IWL<14554> A_IWL<14553> A_IWL<14552> A_IWL<14551> A_IWL<14550> A_IWL<14549> A_IWL<14548> A_IWL<14547> A_IWL<14546> A_IWL<14545> A_IWL<14544> A_IWL<14543> A_IWL<14542> A_IWL<14541> A_IWL<14540> A_IWL<14539> A_IWL<14538> A_IWL<14537> A_IWL<14536> A_IWL<14535> A_IWL<14534> A_IWL<14533> A_IWL<14532> A_IWL<14531> A_IWL<14530> A_IWL<14529> A_IWL<14528> A_IWL<14527> A_IWL<14526> A_IWL<14525> A_IWL<14524> A_IWL<14523> A_IWL<14522> A_IWL<14521> A_IWL<14520> A_IWL<14519> A_IWL<14518> A_IWL<14517> A_IWL<14516> A_IWL<14515> A_IWL<14514> A_IWL<14513> A_IWL<14512> A_IWL<14511> A_IWL<14510> A_IWL<14509> A_IWL<14508> A_IWL<14507> A_IWL<14506> A_IWL<14505> A_IWL<14504> A_IWL<14503> A_IWL<14502> A_IWL<14501> A_IWL<14500> A_IWL<14499> A_IWL<14498> A_IWL<14497> A_IWL<14496> A_IWL<14495> A_IWL<14494> A_IWL<14493> A_IWL<14492> A_IWL<14491> A_IWL<14490> A_IWL<14489> A_IWL<14488> A_IWL<14487> A_IWL<14486> A_IWL<14485> A_IWL<14484> A_IWL<14483> A_IWL<14482> A_IWL<14481> A_IWL<14480> A_IWL<14479> A_IWL<14478> A_IWL<14477> A_IWL<14476> A_IWL<14475> A_IWL<14474> A_IWL<14473> A_IWL<14472> A_IWL<14471> A_IWL<14470> A_IWL<14469> A_IWL<14468> A_IWL<14467> A_IWL<14466> A_IWL<14465> A_IWL<14464> A_IWL<14463> A_IWL<14462> A_IWL<14461> A_IWL<14460> A_IWL<14459> A_IWL<14458> A_IWL<14457> A_IWL<14456> A_IWL<14455> A_IWL<14454> A_IWL<14453> A_IWL<14452> A_IWL<14451> A_IWL<14450> A_IWL<14449> A_IWL<14448> A_IWL<14447> A_IWL<14446> A_IWL<14445> A_IWL<14444> A_IWL<14443> A_IWL<14442> A_IWL<14441> A_IWL<14440> A_IWL<14439> A_IWL<14438> A_IWL<14437> A_IWL<14436> A_IWL<14435> A_IWL<14434> A_IWL<14433> A_IWL<14432> A_IWL<14431> A_IWL<14430> A_IWL<14429> A_IWL<14428> A_IWL<14427> A_IWL<14426> A_IWL<14425> A_IWL<14424> A_IWL<14423> A_IWL<14422> A_IWL<14421> A_IWL<14420> A_IWL<14419> A_IWL<14418> A_IWL<14417> A_IWL<14416> A_IWL<14415> A_IWL<14414> A_IWL<14413> A_IWL<14412> A_IWL<14411> A_IWL<14410> A_IWL<14409> A_IWL<14408> A_IWL<14407> A_IWL<14406> A_IWL<14405> A_IWL<14404> A_IWL<14403> A_IWL<14402> A_IWL<14401> A_IWL<14400> A_IWL<14399> A_IWL<14398> A_IWL<14397> A_IWL<14396> A_IWL<14395> A_IWL<14394> A_IWL<14393> A_IWL<14392> A_IWL<14391> A_IWL<14390> A_IWL<14389> A_IWL<14388> A_IWL<14387> A_IWL<14386> A_IWL<14385> A_IWL<14384> A_IWL<14383> A_IWL<14382> A_IWL<14381> A_IWL<14380> A_IWL<14379> A_IWL<14378> A_IWL<14377> A_IWL<14376> A_IWL<14375> A_IWL<14374> A_IWL<14373> A_IWL<14372> A_IWL<14371> A_IWL<14370> A_IWL<14369> A_IWL<14368> A_IWL<14367> A_IWL<14366> A_IWL<14365> A_IWL<14364> A_IWL<14363> A_IWL<14362> A_IWL<14361> A_IWL<14360> A_IWL<14359> A_IWL<14358> A_IWL<14357> A_IWL<14356> A_IWL<14355> A_IWL<14354> A_IWL<14353> A_IWL<14352> A_IWL<14351> A_IWL<14350> A_IWL<14349> A_IWL<14348> A_IWL<14347> A_IWL<14346> A_IWL<14345> A_IWL<14344> A_IWL<14343> A_IWL<14342> A_IWL<14341> A_IWL<14340> A_IWL<14339> A_IWL<14338> A_IWL<14337> A_IWL<14336> A_IWL<15359> A_IWL<15358> A_IWL<15357> A_IWL<15356> A_IWL<15355> A_IWL<15354> A_IWL<15353> A_IWL<15352> A_IWL<15351> A_IWL<15350> A_IWL<15349> A_IWL<15348> A_IWL<15347> A_IWL<15346> A_IWL<15345> A_IWL<15344> A_IWL<15343> A_IWL<15342> A_IWL<15341> A_IWL<15340> A_IWL<15339> A_IWL<15338> A_IWL<15337> A_IWL<15336> A_IWL<15335> A_IWL<15334> A_IWL<15333> A_IWL<15332> A_IWL<15331> A_IWL<15330> A_IWL<15329> A_IWL<15328> A_IWL<15327> A_IWL<15326> A_IWL<15325> A_IWL<15324> A_IWL<15323> A_IWL<15322> A_IWL<15321> A_IWL<15320> A_IWL<15319> A_IWL<15318> A_IWL<15317> A_IWL<15316> A_IWL<15315> A_IWL<15314> A_IWL<15313> A_IWL<15312> A_IWL<15311> A_IWL<15310> A_IWL<15309> A_IWL<15308> A_IWL<15307> A_IWL<15306> A_IWL<15305> A_IWL<15304> A_IWL<15303> A_IWL<15302> A_IWL<15301> A_IWL<15300> A_IWL<15299> A_IWL<15298> A_IWL<15297> A_IWL<15296> A_IWL<15295> A_IWL<15294> A_IWL<15293> A_IWL<15292> A_IWL<15291> A_IWL<15290> A_IWL<15289> A_IWL<15288> A_IWL<15287> A_IWL<15286> A_IWL<15285> A_IWL<15284> A_IWL<15283> A_IWL<15282> A_IWL<15281> A_IWL<15280> A_IWL<15279> A_IWL<15278> A_IWL<15277> A_IWL<15276> A_IWL<15275> A_IWL<15274> A_IWL<15273> A_IWL<15272> A_IWL<15271> A_IWL<15270> A_IWL<15269> A_IWL<15268> A_IWL<15267> A_IWL<15266> A_IWL<15265> A_IWL<15264> A_IWL<15263> A_IWL<15262> A_IWL<15261> A_IWL<15260> A_IWL<15259> A_IWL<15258> A_IWL<15257> A_IWL<15256> A_IWL<15255> A_IWL<15254> A_IWL<15253> A_IWL<15252> A_IWL<15251> A_IWL<15250> A_IWL<15249> A_IWL<15248> A_IWL<15247> A_IWL<15246> A_IWL<15245> A_IWL<15244> A_IWL<15243> A_IWL<15242> A_IWL<15241> A_IWL<15240> A_IWL<15239> A_IWL<15238> A_IWL<15237> A_IWL<15236> A_IWL<15235> A_IWL<15234> A_IWL<15233> A_IWL<15232> A_IWL<15231> A_IWL<15230> A_IWL<15229> A_IWL<15228> A_IWL<15227> A_IWL<15226> A_IWL<15225> A_IWL<15224> A_IWL<15223> A_IWL<15222> A_IWL<15221> A_IWL<15220> A_IWL<15219> A_IWL<15218> A_IWL<15217> A_IWL<15216> A_IWL<15215> A_IWL<15214> A_IWL<15213> A_IWL<15212> A_IWL<15211> A_IWL<15210> A_IWL<15209> A_IWL<15208> A_IWL<15207> A_IWL<15206> A_IWL<15205> A_IWL<15204> A_IWL<15203> A_IWL<15202> A_IWL<15201> A_IWL<15200> A_IWL<15199> A_IWL<15198> A_IWL<15197> A_IWL<15196> A_IWL<15195> A_IWL<15194> A_IWL<15193> A_IWL<15192> A_IWL<15191> A_IWL<15190> A_IWL<15189> A_IWL<15188> A_IWL<15187> A_IWL<15186> A_IWL<15185> A_IWL<15184> A_IWL<15183> A_IWL<15182> A_IWL<15181> A_IWL<15180> A_IWL<15179> A_IWL<15178> A_IWL<15177> A_IWL<15176> A_IWL<15175> A_IWL<15174> A_IWL<15173> A_IWL<15172> A_IWL<15171> A_IWL<15170> A_IWL<15169> A_IWL<15168> A_IWL<15167> A_IWL<15166> A_IWL<15165> A_IWL<15164> A_IWL<15163> A_IWL<15162> A_IWL<15161> A_IWL<15160> A_IWL<15159> A_IWL<15158> A_IWL<15157> A_IWL<15156> A_IWL<15155> A_IWL<15154> A_IWL<15153> A_IWL<15152> A_IWL<15151> A_IWL<15150> A_IWL<15149> A_IWL<15148> A_IWL<15147> A_IWL<15146> A_IWL<15145> A_IWL<15144> A_IWL<15143> A_IWL<15142> A_IWL<15141> A_IWL<15140> A_IWL<15139> A_IWL<15138> A_IWL<15137> A_IWL<15136> A_IWL<15135> A_IWL<15134> A_IWL<15133> A_IWL<15132> A_IWL<15131> A_IWL<15130> A_IWL<15129> A_IWL<15128> A_IWL<15127> A_IWL<15126> A_IWL<15125> A_IWL<15124> A_IWL<15123> A_IWL<15122> A_IWL<15121> A_IWL<15120> A_IWL<15119> A_IWL<15118> A_IWL<15117> A_IWL<15116> A_IWL<15115> A_IWL<15114> A_IWL<15113> A_IWL<15112> A_IWL<15111> A_IWL<15110> A_IWL<15109> A_IWL<15108> A_IWL<15107> A_IWL<15106> A_IWL<15105> A_IWL<15104> A_IWL<15103> A_IWL<15102> A_IWL<15101> A_IWL<15100> A_IWL<15099> A_IWL<15098> A_IWL<15097> A_IWL<15096> A_IWL<15095> A_IWL<15094> A_IWL<15093> A_IWL<15092> A_IWL<15091> A_IWL<15090> A_IWL<15089> A_IWL<15088> A_IWL<15087> A_IWL<15086> A_IWL<15085> A_IWL<15084> A_IWL<15083> A_IWL<15082> A_IWL<15081> A_IWL<15080> A_IWL<15079> A_IWL<15078> A_IWL<15077> A_IWL<15076> A_IWL<15075> A_IWL<15074> A_IWL<15073> A_IWL<15072> A_IWL<15071> A_IWL<15070> A_IWL<15069> A_IWL<15068> A_IWL<15067> A_IWL<15066> A_IWL<15065> A_IWL<15064> A_IWL<15063> A_IWL<15062> A_IWL<15061> A_IWL<15060> A_IWL<15059> A_IWL<15058> A_IWL<15057> A_IWL<15056> A_IWL<15055> A_IWL<15054> A_IWL<15053> A_IWL<15052> A_IWL<15051> A_IWL<15050> A_IWL<15049> A_IWL<15048> A_IWL<15047> A_IWL<15046> A_IWL<15045> A_IWL<15044> A_IWL<15043> A_IWL<15042> A_IWL<15041> A_IWL<15040> A_IWL<15039> A_IWL<15038> A_IWL<15037> A_IWL<15036> A_IWL<15035> A_IWL<15034> A_IWL<15033> A_IWL<15032> A_IWL<15031> A_IWL<15030> A_IWL<15029> A_IWL<15028> A_IWL<15027> A_IWL<15026> A_IWL<15025> A_IWL<15024> A_IWL<15023> A_IWL<15022> A_IWL<15021> A_IWL<15020> A_IWL<15019> A_IWL<15018> A_IWL<15017> A_IWL<15016> A_IWL<15015> A_IWL<15014> A_IWL<15013> A_IWL<15012> A_IWL<15011> A_IWL<15010> A_IWL<15009> A_IWL<15008> A_IWL<15007> A_IWL<15006> A_IWL<15005> A_IWL<15004> A_IWL<15003> A_IWL<15002> A_IWL<15001> A_IWL<15000> A_IWL<14999> A_IWL<14998> A_IWL<14997> A_IWL<14996> A_IWL<14995> A_IWL<14994> A_IWL<14993> A_IWL<14992> A_IWL<14991> A_IWL<14990> A_IWL<14989> A_IWL<14988> A_IWL<14987> A_IWL<14986> A_IWL<14985> A_IWL<14984> A_IWL<14983> A_IWL<14982> A_IWL<14981> A_IWL<14980> A_IWL<14979> A_IWL<14978> A_IWL<14977> A_IWL<14976> A_IWL<14975> A_IWL<14974> A_IWL<14973> A_IWL<14972> A_IWL<14971> A_IWL<14970> A_IWL<14969> A_IWL<14968> A_IWL<14967> A_IWL<14966> A_IWL<14965> A_IWL<14964> A_IWL<14963> A_IWL<14962> A_IWL<14961> A_IWL<14960> A_IWL<14959> A_IWL<14958> A_IWL<14957> A_IWL<14956> A_IWL<14955> A_IWL<14954> A_IWL<14953> A_IWL<14952> A_IWL<14951> A_IWL<14950> A_IWL<14949> A_IWL<14948> A_IWL<14947> A_IWL<14946> A_IWL<14945> A_IWL<14944> A_IWL<14943> A_IWL<14942> A_IWL<14941> A_IWL<14940> A_IWL<14939> A_IWL<14938> A_IWL<14937> A_IWL<14936> A_IWL<14935> A_IWL<14934> A_IWL<14933> A_IWL<14932> A_IWL<14931> A_IWL<14930> A_IWL<14929> A_IWL<14928> A_IWL<14927> A_IWL<14926> A_IWL<14925> A_IWL<14924> A_IWL<14923> A_IWL<14922> A_IWL<14921> A_IWL<14920> A_IWL<14919> A_IWL<14918> A_IWL<14917> A_IWL<14916> A_IWL<14915> A_IWL<14914> A_IWL<14913> A_IWL<14912> A_IWL<14911> A_IWL<14910> A_IWL<14909> A_IWL<14908> A_IWL<14907> A_IWL<14906> A_IWL<14905> A_IWL<14904> A_IWL<14903> A_IWL<14902> A_IWL<14901> A_IWL<14900> A_IWL<14899> A_IWL<14898> A_IWL<14897> A_IWL<14896> A_IWL<14895> A_IWL<14894> A_IWL<14893> A_IWL<14892> A_IWL<14891> A_IWL<14890> A_IWL<14889> A_IWL<14888> A_IWL<14887> A_IWL<14886> A_IWL<14885> A_IWL<14884> A_IWL<14883> A_IWL<14882> A_IWL<14881> A_IWL<14880> A_IWL<14879> A_IWL<14878> A_IWL<14877> A_IWL<14876> A_IWL<14875> A_IWL<14874> A_IWL<14873> A_IWL<14872> A_IWL<14871> A_IWL<14870> A_IWL<14869> A_IWL<14868> A_IWL<14867> A_IWL<14866> A_IWL<14865> A_IWL<14864> A_IWL<14863> A_IWL<14862> A_IWL<14861> A_IWL<14860> A_IWL<14859> A_IWL<14858> A_IWL<14857> A_IWL<14856> A_IWL<14855> A_IWL<14854> A_IWL<14853> A_IWL<14852> A_IWL<14851> A_IWL<14850> A_IWL<14849> A_IWL<14848> VDD_CORE VSS / RM_IHPSG13_8192x32_c4_1P_COLUMN_pcell_0 +XCOL<28> A_BLC<57> A_BLC<56> A_BLC_TOP<57> A_BLC_TOP<56> A_BLT<57> A_BLT<56> A_BLT_TOP<57> A_BLT_TOP<56> A_IWL<14335> A_IWL<14334> A_IWL<14333> A_IWL<14332> A_IWL<14331> A_IWL<14330> A_IWL<14329> A_IWL<14328> A_IWL<14327> A_IWL<14326> A_IWL<14325> A_IWL<14324> A_IWL<14323> A_IWL<14322> A_IWL<14321> A_IWL<14320> A_IWL<14319> A_IWL<14318> A_IWL<14317> A_IWL<14316> A_IWL<14315> A_IWL<14314> A_IWL<14313> A_IWL<14312> A_IWL<14311> A_IWL<14310> A_IWL<14309> A_IWL<14308> A_IWL<14307> A_IWL<14306> A_IWL<14305> A_IWL<14304> A_IWL<14303> A_IWL<14302> A_IWL<14301> A_IWL<14300> A_IWL<14299> A_IWL<14298> A_IWL<14297> A_IWL<14296> A_IWL<14295> A_IWL<14294> A_IWL<14293> A_IWL<14292> A_IWL<14291> A_IWL<14290> A_IWL<14289> A_IWL<14288> A_IWL<14287> A_IWL<14286> A_IWL<14285> A_IWL<14284> A_IWL<14283> A_IWL<14282> A_IWL<14281> A_IWL<14280> A_IWL<14279> A_IWL<14278> A_IWL<14277> A_IWL<14276> A_IWL<14275> A_IWL<14274> A_IWL<14273> A_IWL<14272> A_IWL<14271> A_IWL<14270> A_IWL<14269> A_IWL<14268> A_IWL<14267> A_IWL<14266> A_IWL<14265> A_IWL<14264> A_IWL<14263> A_IWL<14262> A_IWL<14261> A_IWL<14260> A_IWL<14259> A_IWL<14258> A_IWL<14257> A_IWL<14256> A_IWL<14255> A_IWL<14254> A_IWL<14253> A_IWL<14252> A_IWL<14251> A_IWL<14250> A_IWL<14249> A_IWL<14248> A_IWL<14247> A_IWL<14246> A_IWL<14245> A_IWL<14244> A_IWL<14243> A_IWL<14242> A_IWL<14241> A_IWL<14240> A_IWL<14239> A_IWL<14238> A_IWL<14237> A_IWL<14236> A_IWL<14235> A_IWL<14234> A_IWL<14233> A_IWL<14232> A_IWL<14231> A_IWL<14230> A_IWL<14229> A_IWL<14228> A_IWL<14227> A_IWL<14226> A_IWL<14225> A_IWL<14224> A_IWL<14223> A_IWL<14222> A_IWL<14221> A_IWL<14220> A_IWL<14219> A_IWL<14218> A_IWL<14217> A_IWL<14216> A_IWL<14215> A_IWL<14214> A_IWL<14213> A_IWL<14212> A_IWL<14211> A_IWL<14210> A_IWL<14209> A_IWL<14208> A_IWL<14207> A_IWL<14206> A_IWL<14205> A_IWL<14204> A_IWL<14203> A_IWL<14202> A_IWL<14201> A_IWL<14200> A_IWL<14199> A_IWL<14198> A_IWL<14197> A_IWL<14196> A_IWL<14195> A_IWL<14194> A_IWL<14193> A_IWL<14192> A_IWL<14191> A_IWL<14190> A_IWL<14189> A_IWL<14188> A_IWL<14187> A_IWL<14186> A_IWL<14185> A_IWL<14184> A_IWL<14183> A_IWL<14182> A_IWL<14181> A_IWL<14180> A_IWL<14179> A_IWL<14178> A_IWL<14177> A_IWL<14176> A_IWL<14175> A_IWL<14174> A_IWL<14173> A_IWL<14172> A_IWL<14171> A_IWL<14170> A_IWL<14169> A_IWL<14168> A_IWL<14167> A_IWL<14166> A_IWL<14165> A_IWL<14164> A_IWL<14163> A_IWL<14162> A_IWL<14161> A_IWL<14160> A_IWL<14159> A_IWL<14158> A_IWL<14157> A_IWL<14156> A_IWL<14155> A_IWL<14154> A_IWL<14153> A_IWL<14152> A_IWL<14151> A_IWL<14150> A_IWL<14149> A_IWL<14148> A_IWL<14147> A_IWL<14146> A_IWL<14145> A_IWL<14144> A_IWL<14143> A_IWL<14142> A_IWL<14141> A_IWL<14140> A_IWL<14139> A_IWL<14138> A_IWL<14137> A_IWL<14136> A_IWL<14135> A_IWL<14134> A_IWL<14133> A_IWL<14132> A_IWL<14131> A_IWL<14130> A_IWL<14129> A_IWL<14128> A_IWL<14127> A_IWL<14126> A_IWL<14125> A_IWL<14124> A_IWL<14123> A_IWL<14122> A_IWL<14121> A_IWL<14120> A_IWL<14119> A_IWL<14118> A_IWL<14117> A_IWL<14116> A_IWL<14115> A_IWL<14114> A_IWL<14113> A_IWL<14112> A_IWL<14111> A_IWL<14110> A_IWL<14109> A_IWL<14108> A_IWL<14107> A_IWL<14106> A_IWL<14105> A_IWL<14104> A_IWL<14103> A_IWL<14102> A_IWL<14101> A_IWL<14100> A_IWL<14099> A_IWL<14098> A_IWL<14097> A_IWL<14096> A_IWL<14095> A_IWL<14094> A_IWL<14093> A_IWL<14092> A_IWL<14091> A_IWL<14090> A_IWL<14089> A_IWL<14088> A_IWL<14087> A_IWL<14086> A_IWL<14085> A_IWL<14084> A_IWL<14083> A_IWL<14082> A_IWL<14081> A_IWL<14080> A_IWL<14079> A_IWL<14078> A_IWL<14077> A_IWL<14076> A_IWL<14075> A_IWL<14074> A_IWL<14073> A_IWL<14072> A_IWL<14071> A_IWL<14070> A_IWL<14069> A_IWL<14068> A_IWL<14067> A_IWL<14066> A_IWL<14065> A_IWL<14064> A_IWL<14063> A_IWL<14062> A_IWL<14061> A_IWL<14060> A_IWL<14059> A_IWL<14058> A_IWL<14057> A_IWL<14056> A_IWL<14055> A_IWL<14054> A_IWL<14053> A_IWL<14052> A_IWL<14051> A_IWL<14050> A_IWL<14049> A_IWL<14048> A_IWL<14047> A_IWL<14046> A_IWL<14045> A_IWL<14044> A_IWL<14043> A_IWL<14042> A_IWL<14041> A_IWL<14040> A_IWL<14039> A_IWL<14038> A_IWL<14037> A_IWL<14036> A_IWL<14035> A_IWL<14034> A_IWL<14033> A_IWL<14032> A_IWL<14031> A_IWL<14030> A_IWL<14029> A_IWL<14028> A_IWL<14027> A_IWL<14026> A_IWL<14025> A_IWL<14024> A_IWL<14023> A_IWL<14022> A_IWL<14021> A_IWL<14020> A_IWL<14019> A_IWL<14018> A_IWL<14017> A_IWL<14016> A_IWL<14015> A_IWL<14014> A_IWL<14013> A_IWL<14012> A_IWL<14011> A_IWL<14010> A_IWL<14009> A_IWL<14008> A_IWL<14007> A_IWL<14006> A_IWL<14005> A_IWL<14004> A_IWL<14003> A_IWL<14002> A_IWL<14001> A_IWL<14000> A_IWL<13999> A_IWL<13998> A_IWL<13997> A_IWL<13996> A_IWL<13995> A_IWL<13994> A_IWL<13993> A_IWL<13992> A_IWL<13991> A_IWL<13990> A_IWL<13989> A_IWL<13988> A_IWL<13987> A_IWL<13986> A_IWL<13985> A_IWL<13984> A_IWL<13983> A_IWL<13982> A_IWL<13981> A_IWL<13980> A_IWL<13979> A_IWL<13978> A_IWL<13977> A_IWL<13976> A_IWL<13975> A_IWL<13974> A_IWL<13973> A_IWL<13972> A_IWL<13971> A_IWL<13970> A_IWL<13969> A_IWL<13968> A_IWL<13967> A_IWL<13966> A_IWL<13965> A_IWL<13964> A_IWL<13963> A_IWL<13962> A_IWL<13961> A_IWL<13960> A_IWL<13959> A_IWL<13958> A_IWL<13957> A_IWL<13956> A_IWL<13955> A_IWL<13954> A_IWL<13953> A_IWL<13952> A_IWL<13951> A_IWL<13950> A_IWL<13949> A_IWL<13948> A_IWL<13947> A_IWL<13946> A_IWL<13945> A_IWL<13944> A_IWL<13943> A_IWL<13942> A_IWL<13941> A_IWL<13940> A_IWL<13939> A_IWL<13938> A_IWL<13937> A_IWL<13936> A_IWL<13935> A_IWL<13934> A_IWL<13933> A_IWL<13932> A_IWL<13931> A_IWL<13930> A_IWL<13929> A_IWL<13928> A_IWL<13927> A_IWL<13926> A_IWL<13925> A_IWL<13924> A_IWL<13923> A_IWL<13922> A_IWL<13921> A_IWL<13920> A_IWL<13919> A_IWL<13918> A_IWL<13917> A_IWL<13916> A_IWL<13915> A_IWL<13914> A_IWL<13913> A_IWL<13912> A_IWL<13911> A_IWL<13910> A_IWL<13909> A_IWL<13908> A_IWL<13907> A_IWL<13906> A_IWL<13905> A_IWL<13904> A_IWL<13903> A_IWL<13902> A_IWL<13901> A_IWL<13900> A_IWL<13899> A_IWL<13898> A_IWL<13897> A_IWL<13896> A_IWL<13895> A_IWL<13894> A_IWL<13893> A_IWL<13892> A_IWL<13891> A_IWL<13890> A_IWL<13889> A_IWL<13888> A_IWL<13887> A_IWL<13886> A_IWL<13885> A_IWL<13884> A_IWL<13883> A_IWL<13882> A_IWL<13881> A_IWL<13880> A_IWL<13879> A_IWL<13878> A_IWL<13877> A_IWL<13876> A_IWL<13875> A_IWL<13874> A_IWL<13873> A_IWL<13872> A_IWL<13871> A_IWL<13870> A_IWL<13869> A_IWL<13868> A_IWL<13867> A_IWL<13866> A_IWL<13865> A_IWL<13864> A_IWL<13863> A_IWL<13862> A_IWL<13861> A_IWL<13860> A_IWL<13859> A_IWL<13858> A_IWL<13857> A_IWL<13856> A_IWL<13855> A_IWL<13854> A_IWL<13853> A_IWL<13852> A_IWL<13851> A_IWL<13850> A_IWL<13849> A_IWL<13848> A_IWL<13847> A_IWL<13846> A_IWL<13845> A_IWL<13844> A_IWL<13843> A_IWL<13842> A_IWL<13841> A_IWL<13840> A_IWL<13839> A_IWL<13838> A_IWL<13837> A_IWL<13836> A_IWL<13835> A_IWL<13834> A_IWL<13833> A_IWL<13832> A_IWL<13831> A_IWL<13830> A_IWL<13829> A_IWL<13828> A_IWL<13827> A_IWL<13826> A_IWL<13825> A_IWL<13824> A_IWL<14847> A_IWL<14846> A_IWL<14845> A_IWL<14844> A_IWL<14843> A_IWL<14842> A_IWL<14841> A_IWL<14840> A_IWL<14839> A_IWL<14838> A_IWL<14837> A_IWL<14836> A_IWL<14835> A_IWL<14834> A_IWL<14833> A_IWL<14832> A_IWL<14831> A_IWL<14830> A_IWL<14829> A_IWL<14828> A_IWL<14827> A_IWL<14826> A_IWL<14825> A_IWL<14824> A_IWL<14823> A_IWL<14822> A_IWL<14821> A_IWL<14820> A_IWL<14819> A_IWL<14818> A_IWL<14817> A_IWL<14816> A_IWL<14815> A_IWL<14814> A_IWL<14813> A_IWL<14812> A_IWL<14811> A_IWL<14810> A_IWL<14809> A_IWL<14808> A_IWL<14807> A_IWL<14806> A_IWL<14805> A_IWL<14804> A_IWL<14803> A_IWL<14802> A_IWL<14801> A_IWL<14800> A_IWL<14799> A_IWL<14798> A_IWL<14797> A_IWL<14796> A_IWL<14795> A_IWL<14794> A_IWL<14793> A_IWL<14792> A_IWL<14791> A_IWL<14790> A_IWL<14789> A_IWL<14788> A_IWL<14787> A_IWL<14786> A_IWL<14785> A_IWL<14784> A_IWL<14783> A_IWL<14782> A_IWL<14781> A_IWL<14780> A_IWL<14779> A_IWL<14778> A_IWL<14777> A_IWL<14776> A_IWL<14775> A_IWL<14774> A_IWL<14773> A_IWL<14772> A_IWL<14771> A_IWL<14770> A_IWL<14769> A_IWL<14768> A_IWL<14767> A_IWL<14766> A_IWL<14765> A_IWL<14764> A_IWL<14763> A_IWL<14762> A_IWL<14761> A_IWL<14760> A_IWL<14759> A_IWL<14758> A_IWL<14757> A_IWL<14756> A_IWL<14755> A_IWL<14754> A_IWL<14753> A_IWL<14752> A_IWL<14751> A_IWL<14750> A_IWL<14749> A_IWL<14748> A_IWL<14747> A_IWL<14746> A_IWL<14745> A_IWL<14744> A_IWL<14743> A_IWL<14742> A_IWL<14741> A_IWL<14740> A_IWL<14739> A_IWL<14738> A_IWL<14737> A_IWL<14736> A_IWL<14735> A_IWL<14734> A_IWL<14733> A_IWL<14732> A_IWL<14731> A_IWL<14730> A_IWL<14729> A_IWL<14728> A_IWL<14727> A_IWL<14726> A_IWL<14725> A_IWL<14724> A_IWL<14723> A_IWL<14722> A_IWL<14721> A_IWL<14720> A_IWL<14719> A_IWL<14718> A_IWL<14717> A_IWL<14716> A_IWL<14715> A_IWL<14714> A_IWL<14713> A_IWL<14712> A_IWL<14711> A_IWL<14710> A_IWL<14709> A_IWL<14708> A_IWL<14707> A_IWL<14706> A_IWL<14705> A_IWL<14704> A_IWL<14703> A_IWL<14702> A_IWL<14701> A_IWL<14700> A_IWL<14699> A_IWL<14698> A_IWL<14697> A_IWL<14696> A_IWL<14695> A_IWL<14694> A_IWL<14693> A_IWL<14692> A_IWL<14691> A_IWL<14690> A_IWL<14689> A_IWL<14688> A_IWL<14687> A_IWL<14686> A_IWL<14685> A_IWL<14684> A_IWL<14683> A_IWL<14682> A_IWL<14681> A_IWL<14680> A_IWL<14679> A_IWL<14678> A_IWL<14677> A_IWL<14676> A_IWL<14675> A_IWL<14674> A_IWL<14673> A_IWL<14672> A_IWL<14671> A_IWL<14670> A_IWL<14669> A_IWL<14668> A_IWL<14667> A_IWL<14666> A_IWL<14665> A_IWL<14664> A_IWL<14663> A_IWL<14662> A_IWL<14661> A_IWL<14660> A_IWL<14659> A_IWL<14658> A_IWL<14657> A_IWL<14656> A_IWL<14655> A_IWL<14654> A_IWL<14653> A_IWL<14652> A_IWL<14651> A_IWL<14650> A_IWL<14649> A_IWL<14648> A_IWL<14647> A_IWL<14646> A_IWL<14645> A_IWL<14644> A_IWL<14643> A_IWL<14642> A_IWL<14641> A_IWL<14640> A_IWL<14639> A_IWL<14638> A_IWL<14637> A_IWL<14636> A_IWL<14635> A_IWL<14634> A_IWL<14633> A_IWL<14632> A_IWL<14631> A_IWL<14630> A_IWL<14629> A_IWL<14628> A_IWL<14627> A_IWL<14626> A_IWL<14625> A_IWL<14624> A_IWL<14623> A_IWL<14622> A_IWL<14621> A_IWL<14620> A_IWL<14619> A_IWL<14618> A_IWL<14617> A_IWL<14616> A_IWL<14615> A_IWL<14614> A_IWL<14613> A_IWL<14612> A_IWL<14611> A_IWL<14610> A_IWL<14609> A_IWL<14608> A_IWL<14607> A_IWL<14606> A_IWL<14605> A_IWL<14604> A_IWL<14603> A_IWL<14602> A_IWL<14601> A_IWL<14600> A_IWL<14599> A_IWL<14598> A_IWL<14597> A_IWL<14596> A_IWL<14595> A_IWL<14594> A_IWL<14593> A_IWL<14592> A_IWL<14591> A_IWL<14590> A_IWL<14589> A_IWL<14588> A_IWL<14587> A_IWL<14586> A_IWL<14585> A_IWL<14584> A_IWL<14583> A_IWL<14582> A_IWL<14581> A_IWL<14580> A_IWL<14579> A_IWL<14578> A_IWL<14577> A_IWL<14576> A_IWL<14575> A_IWL<14574> A_IWL<14573> A_IWL<14572> A_IWL<14571> A_IWL<14570> A_IWL<14569> A_IWL<14568> A_IWL<14567> A_IWL<14566> A_IWL<14565> A_IWL<14564> A_IWL<14563> A_IWL<14562> A_IWL<14561> A_IWL<14560> A_IWL<14559> A_IWL<14558> A_IWL<14557> A_IWL<14556> A_IWL<14555> A_IWL<14554> A_IWL<14553> A_IWL<14552> A_IWL<14551> A_IWL<14550> A_IWL<14549> A_IWL<14548> A_IWL<14547> A_IWL<14546> A_IWL<14545> A_IWL<14544> A_IWL<14543> A_IWL<14542> A_IWL<14541> A_IWL<14540> A_IWL<14539> A_IWL<14538> A_IWL<14537> A_IWL<14536> A_IWL<14535> A_IWL<14534> A_IWL<14533> A_IWL<14532> A_IWL<14531> A_IWL<14530> A_IWL<14529> A_IWL<14528> A_IWL<14527> A_IWL<14526> A_IWL<14525> A_IWL<14524> A_IWL<14523> A_IWL<14522> A_IWL<14521> A_IWL<14520> A_IWL<14519> A_IWL<14518> A_IWL<14517> A_IWL<14516> A_IWL<14515> A_IWL<14514> A_IWL<14513> A_IWL<14512> A_IWL<14511> A_IWL<14510> A_IWL<14509> A_IWL<14508> A_IWL<14507> A_IWL<14506> A_IWL<14505> A_IWL<14504> A_IWL<14503> A_IWL<14502> A_IWL<14501> A_IWL<14500> A_IWL<14499> A_IWL<14498> A_IWL<14497> A_IWL<14496> A_IWL<14495> A_IWL<14494> A_IWL<14493> A_IWL<14492> A_IWL<14491> A_IWL<14490> A_IWL<14489> A_IWL<14488> A_IWL<14487> A_IWL<14486> A_IWL<14485> A_IWL<14484> A_IWL<14483> A_IWL<14482> A_IWL<14481> A_IWL<14480> A_IWL<14479> A_IWL<14478> A_IWL<14477> A_IWL<14476> A_IWL<14475> A_IWL<14474> A_IWL<14473> A_IWL<14472> A_IWL<14471> A_IWL<14470> A_IWL<14469> A_IWL<14468> A_IWL<14467> A_IWL<14466> A_IWL<14465> A_IWL<14464> A_IWL<14463> A_IWL<14462> A_IWL<14461> A_IWL<14460> A_IWL<14459> A_IWL<14458> A_IWL<14457> A_IWL<14456> A_IWL<14455> A_IWL<14454> A_IWL<14453> A_IWL<14452> A_IWL<14451> A_IWL<14450> A_IWL<14449> A_IWL<14448> A_IWL<14447> A_IWL<14446> A_IWL<14445> A_IWL<14444> A_IWL<14443> A_IWL<14442> A_IWL<14441> A_IWL<14440> A_IWL<14439> A_IWL<14438> A_IWL<14437> A_IWL<14436> A_IWL<14435> A_IWL<14434> A_IWL<14433> A_IWL<14432> A_IWL<14431> A_IWL<14430> A_IWL<14429> A_IWL<14428> A_IWL<14427> A_IWL<14426> A_IWL<14425> A_IWL<14424> A_IWL<14423> A_IWL<14422> A_IWL<14421> A_IWL<14420> A_IWL<14419> A_IWL<14418> A_IWL<14417> A_IWL<14416> A_IWL<14415> A_IWL<14414> A_IWL<14413> A_IWL<14412> A_IWL<14411> A_IWL<14410> A_IWL<14409> A_IWL<14408> A_IWL<14407> A_IWL<14406> A_IWL<14405> A_IWL<14404> A_IWL<14403> A_IWL<14402> A_IWL<14401> A_IWL<14400> A_IWL<14399> A_IWL<14398> A_IWL<14397> A_IWL<14396> A_IWL<14395> A_IWL<14394> A_IWL<14393> A_IWL<14392> A_IWL<14391> A_IWL<14390> A_IWL<14389> A_IWL<14388> A_IWL<14387> A_IWL<14386> A_IWL<14385> A_IWL<14384> A_IWL<14383> A_IWL<14382> A_IWL<14381> A_IWL<14380> A_IWL<14379> A_IWL<14378> A_IWL<14377> A_IWL<14376> A_IWL<14375> A_IWL<14374> A_IWL<14373> A_IWL<14372> A_IWL<14371> A_IWL<14370> A_IWL<14369> A_IWL<14368> A_IWL<14367> A_IWL<14366> A_IWL<14365> A_IWL<14364> A_IWL<14363> A_IWL<14362> A_IWL<14361> A_IWL<14360> A_IWL<14359> A_IWL<14358> A_IWL<14357> A_IWL<14356> A_IWL<14355> A_IWL<14354> A_IWL<14353> A_IWL<14352> A_IWL<14351> A_IWL<14350> A_IWL<14349> A_IWL<14348> A_IWL<14347> A_IWL<14346> A_IWL<14345> A_IWL<14344> A_IWL<14343> A_IWL<14342> A_IWL<14341> A_IWL<14340> A_IWL<14339> A_IWL<14338> A_IWL<14337> A_IWL<14336> VDD_CORE VSS / RM_IHPSG13_8192x32_c4_1P_COLUMN_pcell_0 +XCOL<27> A_BLC<55> A_BLC<54> A_BLC_TOP<55> A_BLC_TOP<54> A_BLT<55> A_BLT<54> A_BLT_TOP<55> A_BLT_TOP<54> A_IWL<13823> A_IWL<13822> A_IWL<13821> A_IWL<13820> A_IWL<13819> A_IWL<13818> A_IWL<13817> A_IWL<13816> A_IWL<13815> A_IWL<13814> A_IWL<13813> A_IWL<13812> A_IWL<13811> A_IWL<13810> A_IWL<13809> A_IWL<13808> A_IWL<13807> A_IWL<13806> A_IWL<13805> A_IWL<13804> A_IWL<13803> A_IWL<13802> A_IWL<13801> A_IWL<13800> A_IWL<13799> A_IWL<13798> A_IWL<13797> A_IWL<13796> A_IWL<13795> A_IWL<13794> A_IWL<13793> A_IWL<13792> A_IWL<13791> A_IWL<13790> A_IWL<13789> A_IWL<13788> A_IWL<13787> A_IWL<13786> A_IWL<13785> A_IWL<13784> A_IWL<13783> A_IWL<13782> A_IWL<13781> A_IWL<13780> A_IWL<13779> A_IWL<13778> A_IWL<13777> A_IWL<13776> A_IWL<13775> A_IWL<13774> A_IWL<13773> A_IWL<13772> A_IWL<13771> A_IWL<13770> A_IWL<13769> A_IWL<13768> A_IWL<13767> A_IWL<13766> A_IWL<13765> A_IWL<13764> A_IWL<13763> A_IWL<13762> A_IWL<13761> A_IWL<13760> A_IWL<13759> A_IWL<13758> A_IWL<13757> A_IWL<13756> A_IWL<13755> A_IWL<13754> A_IWL<13753> A_IWL<13752> A_IWL<13751> A_IWL<13750> A_IWL<13749> A_IWL<13748> A_IWL<13747> A_IWL<13746> A_IWL<13745> A_IWL<13744> A_IWL<13743> A_IWL<13742> A_IWL<13741> A_IWL<13740> A_IWL<13739> A_IWL<13738> A_IWL<13737> A_IWL<13736> A_IWL<13735> A_IWL<13734> A_IWL<13733> A_IWL<13732> A_IWL<13731> A_IWL<13730> A_IWL<13729> A_IWL<13728> A_IWL<13727> A_IWL<13726> A_IWL<13725> A_IWL<13724> A_IWL<13723> A_IWL<13722> A_IWL<13721> A_IWL<13720> A_IWL<13719> A_IWL<13718> A_IWL<13717> A_IWL<13716> A_IWL<13715> A_IWL<13714> A_IWL<13713> A_IWL<13712> A_IWL<13711> A_IWL<13710> A_IWL<13709> A_IWL<13708> A_IWL<13707> A_IWL<13706> A_IWL<13705> A_IWL<13704> A_IWL<13703> A_IWL<13702> A_IWL<13701> A_IWL<13700> A_IWL<13699> A_IWL<13698> A_IWL<13697> A_IWL<13696> A_IWL<13695> A_IWL<13694> A_IWL<13693> A_IWL<13692> A_IWL<13691> A_IWL<13690> A_IWL<13689> A_IWL<13688> A_IWL<13687> A_IWL<13686> A_IWL<13685> A_IWL<13684> A_IWL<13683> A_IWL<13682> A_IWL<13681> A_IWL<13680> A_IWL<13679> A_IWL<13678> A_IWL<13677> A_IWL<13676> A_IWL<13675> A_IWL<13674> A_IWL<13673> A_IWL<13672> A_IWL<13671> A_IWL<13670> A_IWL<13669> A_IWL<13668> A_IWL<13667> A_IWL<13666> A_IWL<13665> A_IWL<13664> A_IWL<13663> A_IWL<13662> A_IWL<13661> A_IWL<13660> A_IWL<13659> A_IWL<13658> A_IWL<13657> A_IWL<13656> A_IWL<13655> A_IWL<13654> A_IWL<13653> A_IWL<13652> A_IWL<13651> A_IWL<13650> A_IWL<13649> A_IWL<13648> A_IWL<13647> A_IWL<13646> A_IWL<13645> A_IWL<13644> A_IWL<13643> A_IWL<13642> A_IWL<13641> A_IWL<13640> A_IWL<13639> A_IWL<13638> A_IWL<13637> A_IWL<13636> A_IWL<13635> A_IWL<13634> A_IWL<13633> A_IWL<13632> A_IWL<13631> A_IWL<13630> A_IWL<13629> A_IWL<13628> A_IWL<13627> A_IWL<13626> A_IWL<13625> A_IWL<13624> A_IWL<13623> A_IWL<13622> A_IWL<13621> A_IWL<13620> A_IWL<13619> A_IWL<13618> A_IWL<13617> A_IWL<13616> A_IWL<13615> A_IWL<13614> A_IWL<13613> A_IWL<13612> A_IWL<13611> A_IWL<13610> A_IWL<13609> A_IWL<13608> A_IWL<13607> A_IWL<13606> A_IWL<13605> A_IWL<13604> A_IWL<13603> A_IWL<13602> A_IWL<13601> A_IWL<13600> A_IWL<13599> A_IWL<13598> A_IWL<13597> A_IWL<13596> A_IWL<13595> A_IWL<13594> A_IWL<13593> A_IWL<13592> A_IWL<13591> A_IWL<13590> A_IWL<13589> A_IWL<13588> A_IWL<13587> A_IWL<13586> A_IWL<13585> A_IWL<13584> A_IWL<13583> A_IWL<13582> A_IWL<13581> A_IWL<13580> A_IWL<13579> A_IWL<13578> A_IWL<13577> A_IWL<13576> A_IWL<13575> A_IWL<13574> A_IWL<13573> A_IWL<13572> A_IWL<13571> A_IWL<13570> A_IWL<13569> A_IWL<13568> A_IWL<13567> A_IWL<13566> A_IWL<13565> A_IWL<13564> A_IWL<13563> A_IWL<13562> A_IWL<13561> A_IWL<13560> A_IWL<13559> A_IWL<13558> A_IWL<13557> A_IWL<13556> A_IWL<13555> A_IWL<13554> A_IWL<13553> A_IWL<13552> A_IWL<13551> A_IWL<13550> A_IWL<13549> A_IWL<13548> A_IWL<13547> A_IWL<13546> A_IWL<13545> A_IWL<13544> A_IWL<13543> A_IWL<13542> A_IWL<13541> A_IWL<13540> A_IWL<13539> A_IWL<13538> A_IWL<13537> A_IWL<13536> A_IWL<13535> A_IWL<13534> A_IWL<13533> A_IWL<13532> A_IWL<13531> A_IWL<13530> A_IWL<13529> A_IWL<13528> A_IWL<13527> A_IWL<13526> A_IWL<13525> A_IWL<13524> A_IWL<13523> A_IWL<13522> A_IWL<13521> A_IWL<13520> A_IWL<13519> A_IWL<13518> A_IWL<13517> A_IWL<13516> A_IWL<13515> A_IWL<13514> A_IWL<13513> A_IWL<13512> A_IWL<13511> A_IWL<13510> A_IWL<13509> A_IWL<13508> A_IWL<13507> A_IWL<13506> A_IWL<13505> A_IWL<13504> A_IWL<13503> A_IWL<13502> A_IWL<13501> A_IWL<13500> A_IWL<13499> A_IWL<13498> A_IWL<13497> A_IWL<13496> A_IWL<13495> A_IWL<13494> A_IWL<13493> A_IWL<13492> A_IWL<13491> A_IWL<13490> A_IWL<13489> A_IWL<13488> A_IWL<13487> A_IWL<13486> A_IWL<13485> A_IWL<13484> A_IWL<13483> A_IWL<13482> A_IWL<13481> A_IWL<13480> A_IWL<13479> A_IWL<13478> A_IWL<13477> A_IWL<13476> A_IWL<13475> A_IWL<13474> A_IWL<13473> A_IWL<13472> A_IWL<13471> A_IWL<13470> A_IWL<13469> A_IWL<13468> A_IWL<13467> A_IWL<13466> A_IWL<13465> A_IWL<13464> A_IWL<13463> A_IWL<13462> A_IWL<13461> A_IWL<13460> A_IWL<13459> A_IWL<13458> A_IWL<13457> A_IWL<13456> A_IWL<13455> A_IWL<13454> A_IWL<13453> A_IWL<13452> A_IWL<13451> A_IWL<13450> A_IWL<13449> A_IWL<13448> A_IWL<13447> A_IWL<13446> A_IWL<13445> A_IWL<13444> A_IWL<13443> A_IWL<13442> A_IWL<13441> A_IWL<13440> A_IWL<13439> A_IWL<13438> A_IWL<13437> A_IWL<13436> A_IWL<13435> A_IWL<13434> A_IWL<13433> A_IWL<13432> A_IWL<13431> A_IWL<13430> A_IWL<13429> A_IWL<13428> A_IWL<13427> A_IWL<13426> A_IWL<13425> A_IWL<13424> A_IWL<13423> A_IWL<13422> A_IWL<13421> A_IWL<13420> A_IWL<13419> A_IWL<13418> A_IWL<13417> A_IWL<13416> A_IWL<13415> A_IWL<13414> A_IWL<13413> A_IWL<13412> A_IWL<13411> A_IWL<13410> A_IWL<13409> A_IWL<13408> A_IWL<13407> A_IWL<13406> A_IWL<13405> A_IWL<13404> A_IWL<13403> A_IWL<13402> A_IWL<13401> A_IWL<13400> A_IWL<13399> A_IWL<13398> A_IWL<13397> A_IWL<13396> A_IWL<13395> A_IWL<13394> A_IWL<13393> A_IWL<13392> A_IWL<13391> A_IWL<13390> A_IWL<13389> A_IWL<13388> A_IWL<13387> A_IWL<13386> A_IWL<13385> A_IWL<13384> A_IWL<13383> A_IWL<13382> A_IWL<13381> A_IWL<13380> A_IWL<13379> A_IWL<13378> A_IWL<13377> A_IWL<13376> A_IWL<13375> A_IWL<13374> A_IWL<13373> A_IWL<13372> A_IWL<13371> A_IWL<13370> A_IWL<13369> A_IWL<13368> A_IWL<13367> A_IWL<13366> A_IWL<13365> A_IWL<13364> A_IWL<13363> A_IWL<13362> A_IWL<13361> A_IWL<13360> A_IWL<13359> A_IWL<13358> A_IWL<13357> A_IWL<13356> A_IWL<13355> A_IWL<13354> A_IWL<13353> A_IWL<13352> A_IWL<13351> A_IWL<13350> A_IWL<13349> A_IWL<13348> A_IWL<13347> A_IWL<13346> A_IWL<13345> A_IWL<13344> A_IWL<13343> A_IWL<13342> A_IWL<13341> A_IWL<13340> A_IWL<13339> A_IWL<13338> A_IWL<13337> A_IWL<13336> A_IWL<13335> A_IWL<13334> A_IWL<13333> A_IWL<13332> A_IWL<13331> A_IWL<13330> A_IWL<13329> A_IWL<13328> A_IWL<13327> A_IWL<13326> A_IWL<13325> A_IWL<13324> A_IWL<13323> A_IWL<13322> A_IWL<13321> A_IWL<13320> A_IWL<13319> A_IWL<13318> A_IWL<13317> A_IWL<13316> A_IWL<13315> A_IWL<13314> A_IWL<13313> A_IWL<13312> A_IWL<14335> A_IWL<14334> A_IWL<14333> A_IWL<14332> A_IWL<14331> A_IWL<14330> A_IWL<14329> A_IWL<14328> A_IWL<14327> A_IWL<14326> A_IWL<14325> A_IWL<14324> A_IWL<14323> A_IWL<14322> A_IWL<14321> A_IWL<14320> A_IWL<14319> A_IWL<14318> A_IWL<14317> A_IWL<14316> A_IWL<14315> A_IWL<14314> A_IWL<14313> A_IWL<14312> A_IWL<14311> A_IWL<14310> A_IWL<14309> A_IWL<14308> A_IWL<14307> A_IWL<14306> A_IWL<14305> A_IWL<14304> A_IWL<14303> A_IWL<14302> A_IWL<14301> A_IWL<14300> A_IWL<14299> A_IWL<14298> A_IWL<14297> A_IWL<14296> A_IWL<14295> A_IWL<14294> A_IWL<14293> A_IWL<14292> A_IWL<14291> A_IWL<14290> A_IWL<14289> A_IWL<14288> A_IWL<14287> A_IWL<14286> A_IWL<14285> A_IWL<14284> A_IWL<14283> A_IWL<14282> A_IWL<14281> A_IWL<14280> A_IWL<14279> A_IWL<14278> A_IWL<14277> A_IWL<14276> A_IWL<14275> A_IWL<14274> A_IWL<14273> A_IWL<14272> A_IWL<14271> A_IWL<14270> A_IWL<14269> A_IWL<14268> A_IWL<14267> A_IWL<14266> A_IWL<14265> A_IWL<14264> A_IWL<14263> A_IWL<14262> A_IWL<14261> A_IWL<14260> A_IWL<14259> A_IWL<14258> A_IWL<14257> A_IWL<14256> A_IWL<14255> A_IWL<14254> A_IWL<14253> A_IWL<14252> A_IWL<14251> A_IWL<14250> A_IWL<14249> A_IWL<14248> A_IWL<14247> A_IWL<14246> A_IWL<14245> A_IWL<14244> A_IWL<14243> A_IWL<14242> A_IWL<14241> A_IWL<14240> A_IWL<14239> A_IWL<14238> A_IWL<14237> A_IWL<14236> A_IWL<14235> A_IWL<14234> A_IWL<14233> A_IWL<14232> A_IWL<14231> A_IWL<14230> A_IWL<14229> A_IWL<14228> A_IWL<14227> A_IWL<14226> A_IWL<14225> A_IWL<14224> A_IWL<14223> A_IWL<14222> A_IWL<14221> A_IWL<14220> A_IWL<14219> A_IWL<14218> A_IWL<14217> A_IWL<14216> A_IWL<14215> A_IWL<14214> A_IWL<14213> A_IWL<14212> A_IWL<14211> A_IWL<14210> A_IWL<14209> A_IWL<14208> A_IWL<14207> A_IWL<14206> A_IWL<14205> A_IWL<14204> A_IWL<14203> A_IWL<14202> A_IWL<14201> A_IWL<14200> A_IWL<14199> A_IWL<14198> A_IWL<14197> A_IWL<14196> A_IWL<14195> A_IWL<14194> A_IWL<14193> A_IWL<14192> A_IWL<14191> A_IWL<14190> A_IWL<14189> A_IWL<14188> A_IWL<14187> A_IWL<14186> A_IWL<14185> A_IWL<14184> A_IWL<14183> A_IWL<14182> A_IWL<14181> A_IWL<14180> A_IWL<14179> A_IWL<14178> A_IWL<14177> A_IWL<14176> A_IWL<14175> A_IWL<14174> A_IWL<14173> A_IWL<14172> A_IWL<14171> A_IWL<14170> A_IWL<14169> A_IWL<14168> A_IWL<14167> A_IWL<14166> A_IWL<14165> A_IWL<14164> A_IWL<14163> A_IWL<14162> A_IWL<14161> A_IWL<14160> A_IWL<14159> A_IWL<14158> A_IWL<14157> A_IWL<14156> A_IWL<14155> A_IWL<14154> A_IWL<14153> A_IWL<14152> A_IWL<14151> A_IWL<14150> A_IWL<14149> A_IWL<14148> A_IWL<14147> A_IWL<14146> A_IWL<14145> A_IWL<14144> A_IWL<14143> A_IWL<14142> A_IWL<14141> A_IWL<14140> A_IWL<14139> A_IWL<14138> A_IWL<14137> A_IWL<14136> A_IWL<14135> A_IWL<14134> A_IWL<14133> A_IWL<14132> A_IWL<14131> A_IWL<14130> A_IWL<14129> A_IWL<14128> A_IWL<14127> A_IWL<14126> A_IWL<14125> A_IWL<14124> A_IWL<14123> A_IWL<14122> A_IWL<14121> A_IWL<14120> A_IWL<14119> A_IWL<14118> A_IWL<14117> A_IWL<14116> A_IWL<14115> A_IWL<14114> A_IWL<14113> A_IWL<14112> A_IWL<14111> A_IWL<14110> A_IWL<14109> A_IWL<14108> A_IWL<14107> A_IWL<14106> A_IWL<14105> A_IWL<14104> A_IWL<14103> A_IWL<14102> A_IWL<14101> A_IWL<14100> A_IWL<14099> A_IWL<14098> A_IWL<14097> A_IWL<14096> A_IWL<14095> A_IWL<14094> A_IWL<14093> A_IWL<14092> A_IWL<14091> A_IWL<14090> A_IWL<14089> A_IWL<14088> A_IWL<14087> A_IWL<14086> A_IWL<14085> A_IWL<14084> A_IWL<14083> A_IWL<14082> A_IWL<14081> A_IWL<14080> A_IWL<14079> A_IWL<14078> A_IWL<14077> A_IWL<14076> A_IWL<14075> A_IWL<14074> A_IWL<14073> A_IWL<14072> A_IWL<14071> A_IWL<14070> A_IWL<14069> A_IWL<14068> A_IWL<14067> A_IWL<14066> A_IWL<14065> A_IWL<14064> A_IWL<14063> A_IWL<14062> A_IWL<14061> A_IWL<14060> A_IWL<14059> A_IWL<14058> A_IWL<14057> A_IWL<14056> A_IWL<14055> A_IWL<14054> A_IWL<14053> A_IWL<14052> A_IWL<14051> A_IWL<14050> A_IWL<14049> A_IWL<14048> A_IWL<14047> A_IWL<14046> A_IWL<14045> A_IWL<14044> A_IWL<14043> A_IWL<14042> A_IWL<14041> A_IWL<14040> A_IWL<14039> A_IWL<14038> A_IWL<14037> A_IWL<14036> A_IWL<14035> A_IWL<14034> A_IWL<14033> A_IWL<14032> A_IWL<14031> A_IWL<14030> A_IWL<14029> A_IWL<14028> A_IWL<14027> A_IWL<14026> A_IWL<14025> A_IWL<14024> A_IWL<14023> A_IWL<14022> A_IWL<14021> A_IWL<14020> A_IWL<14019> A_IWL<14018> A_IWL<14017> A_IWL<14016> A_IWL<14015> A_IWL<14014> A_IWL<14013> A_IWL<14012> A_IWL<14011> A_IWL<14010> A_IWL<14009> A_IWL<14008> A_IWL<14007> A_IWL<14006> A_IWL<14005> A_IWL<14004> A_IWL<14003> A_IWL<14002> A_IWL<14001> A_IWL<14000> A_IWL<13999> A_IWL<13998> A_IWL<13997> A_IWL<13996> A_IWL<13995> A_IWL<13994> A_IWL<13993> A_IWL<13992> A_IWL<13991> A_IWL<13990> A_IWL<13989> A_IWL<13988> A_IWL<13987> A_IWL<13986> A_IWL<13985> A_IWL<13984> A_IWL<13983> A_IWL<13982> A_IWL<13981> A_IWL<13980> A_IWL<13979> A_IWL<13978> A_IWL<13977> A_IWL<13976> A_IWL<13975> A_IWL<13974> A_IWL<13973> A_IWL<13972> A_IWL<13971> A_IWL<13970> A_IWL<13969> A_IWL<13968> A_IWL<13967> A_IWL<13966> A_IWL<13965> A_IWL<13964> A_IWL<13963> A_IWL<13962> A_IWL<13961> A_IWL<13960> A_IWL<13959> A_IWL<13958> A_IWL<13957> A_IWL<13956> A_IWL<13955> A_IWL<13954> A_IWL<13953> A_IWL<13952> A_IWL<13951> A_IWL<13950> A_IWL<13949> A_IWL<13948> A_IWL<13947> A_IWL<13946> A_IWL<13945> A_IWL<13944> A_IWL<13943> A_IWL<13942> A_IWL<13941> A_IWL<13940> A_IWL<13939> A_IWL<13938> A_IWL<13937> A_IWL<13936> A_IWL<13935> A_IWL<13934> A_IWL<13933> A_IWL<13932> A_IWL<13931> A_IWL<13930> A_IWL<13929> A_IWL<13928> A_IWL<13927> A_IWL<13926> A_IWL<13925> A_IWL<13924> A_IWL<13923> A_IWL<13922> A_IWL<13921> A_IWL<13920> A_IWL<13919> A_IWL<13918> A_IWL<13917> A_IWL<13916> A_IWL<13915> A_IWL<13914> A_IWL<13913> A_IWL<13912> A_IWL<13911> A_IWL<13910> A_IWL<13909> A_IWL<13908> A_IWL<13907> A_IWL<13906> A_IWL<13905> A_IWL<13904> A_IWL<13903> A_IWL<13902> A_IWL<13901> A_IWL<13900> A_IWL<13899> A_IWL<13898> A_IWL<13897> A_IWL<13896> A_IWL<13895> A_IWL<13894> A_IWL<13893> A_IWL<13892> A_IWL<13891> A_IWL<13890> A_IWL<13889> A_IWL<13888> A_IWL<13887> A_IWL<13886> A_IWL<13885> A_IWL<13884> A_IWL<13883> A_IWL<13882> A_IWL<13881> A_IWL<13880> A_IWL<13879> A_IWL<13878> A_IWL<13877> A_IWL<13876> A_IWL<13875> A_IWL<13874> A_IWL<13873> A_IWL<13872> A_IWL<13871> A_IWL<13870> A_IWL<13869> A_IWL<13868> A_IWL<13867> A_IWL<13866> A_IWL<13865> A_IWL<13864> A_IWL<13863> A_IWL<13862> A_IWL<13861> A_IWL<13860> A_IWL<13859> A_IWL<13858> A_IWL<13857> A_IWL<13856> A_IWL<13855> A_IWL<13854> A_IWL<13853> A_IWL<13852> A_IWL<13851> A_IWL<13850> A_IWL<13849> A_IWL<13848> A_IWL<13847> A_IWL<13846> A_IWL<13845> A_IWL<13844> A_IWL<13843> A_IWL<13842> A_IWL<13841> A_IWL<13840> A_IWL<13839> A_IWL<13838> A_IWL<13837> A_IWL<13836> A_IWL<13835> A_IWL<13834> A_IWL<13833> A_IWL<13832> A_IWL<13831> A_IWL<13830> A_IWL<13829> A_IWL<13828> A_IWL<13827> A_IWL<13826> A_IWL<13825> A_IWL<13824> VDD_CORE VSS / RM_IHPSG13_8192x32_c4_1P_COLUMN_pcell_0 +XCOL<26> A_BLC<53> A_BLC<52> A_BLC_TOP<53> A_BLC_TOP<52> A_BLT<53> A_BLT<52> A_BLT_TOP<53> A_BLT_TOP<52> A_IWL<13311> A_IWL<13310> A_IWL<13309> A_IWL<13308> A_IWL<13307> A_IWL<13306> A_IWL<13305> A_IWL<13304> A_IWL<13303> A_IWL<13302> A_IWL<13301> A_IWL<13300> A_IWL<13299> A_IWL<13298> A_IWL<13297> A_IWL<13296> A_IWL<13295> A_IWL<13294> A_IWL<13293> A_IWL<13292> A_IWL<13291> A_IWL<13290> A_IWL<13289> A_IWL<13288> A_IWL<13287> A_IWL<13286> A_IWL<13285> A_IWL<13284> A_IWL<13283> A_IWL<13282> A_IWL<13281> A_IWL<13280> A_IWL<13279> A_IWL<13278> A_IWL<13277> A_IWL<13276> A_IWL<13275> A_IWL<13274> A_IWL<13273> A_IWL<13272> A_IWL<13271> A_IWL<13270> A_IWL<13269> A_IWL<13268> A_IWL<13267> A_IWL<13266> A_IWL<13265> A_IWL<13264> A_IWL<13263> A_IWL<13262> A_IWL<13261> A_IWL<13260> A_IWL<13259> A_IWL<13258> A_IWL<13257> A_IWL<13256> A_IWL<13255> A_IWL<13254> A_IWL<13253> A_IWL<13252> A_IWL<13251> A_IWL<13250> A_IWL<13249> A_IWL<13248> A_IWL<13247> A_IWL<13246> A_IWL<13245> A_IWL<13244> A_IWL<13243> A_IWL<13242> A_IWL<13241> A_IWL<13240> A_IWL<13239> A_IWL<13238> A_IWL<13237> A_IWL<13236> A_IWL<13235> A_IWL<13234> A_IWL<13233> A_IWL<13232> A_IWL<13231> A_IWL<13230> A_IWL<13229> A_IWL<13228> A_IWL<13227> A_IWL<13226> A_IWL<13225> A_IWL<13224> A_IWL<13223> A_IWL<13222> A_IWL<13221> A_IWL<13220> A_IWL<13219> A_IWL<13218> A_IWL<13217> A_IWL<13216> A_IWL<13215> A_IWL<13214> A_IWL<13213> A_IWL<13212> A_IWL<13211> A_IWL<13210> A_IWL<13209> A_IWL<13208> A_IWL<13207> A_IWL<13206> A_IWL<13205> A_IWL<13204> A_IWL<13203> A_IWL<13202> A_IWL<13201> A_IWL<13200> A_IWL<13199> A_IWL<13198> A_IWL<13197> A_IWL<13196> A_IWL<13195> A_IWL<13194> A_IWL<13193> A_IWL<13192> A_IWL<13191> A_IWL<13190> A_IWL<13189> A_IWL<13188> A_IWL<13187> A_IWL<13186> A_IWL<13185> A_IWL<13184> A_IWL<13183> A_IWL<13182> A_IWL<13181> A_IWL<13180> A_IWL<13179> A_IWL<13178> A_IWL<13177> A_IWL<13176> A_IWL<13175> A_IWL<13174> A_IWL<13173> A_IWL<13172> A_IWL<13171> A_IWL<13170> A_IWL<13169> A_IWL<13168> A_IWL<13167> A_IWL<13166> A_IWL<13165> A_IWL<13164> A_IWL<13163> A_IWL<13162> A_IWL<13161> A_IWL<13160> A_IWL<13159> A_IWL<13158> A_IWL<13157> A_IWL<13156> A_IWL<13155> A_IWL<13154> A_IWL<13153> A_IWL<13152> A_IWL<13151> A_IWL<13150> A_IWL<13149> A_IWL<13148> A_IWL<13147> A_IWL<13146> A_IWL<13145> A_IWL<13144> A_IWL<13143> A_IWL<13142> A_IWL<13141> A_IWL<13140> A_IWL<13139> A_IWL<13138> A_IWL<13137> A_IWL<13136> A_IWL<13135> A_IWL<13134> A_IWL<13133> A_IWL<13132> A_IWL<13131> A_IWL<13130> A_IWL<13129> A_IWL<13128> A_IWL<13127> A_IWL<13126> A_IWL<13125> A_IWL<13124> A_IWL<13123> A_IWL<13122> A_IWL<13121> A_IWL<13120> A_IWL<13119> A_IWL<13118> A_IWL<13117> A_IWL<13116> A_IWL<13115> A_IWL<13114> A_IWL<13113> A_IWL<13112> A_IWL<13111> A_IWL<13110> A_IWL<13109> A_IWL<13108> A_IWL<13107> A_IWL<13106> A_IWL<13105> A_IWL<13104> A_IWL<13103> A_IWL<13102> A_IWL<13101> A_IWL<13100> A_IWL<13099> A_IWL<13098> A_IWL<13097> A_IWL<13096> A_IWL<13095> A_IWL<13094> A_IWL<13093> A_IWL<13092> A_IWL<13091> A_IWL<13090> A_IWL<13089> A_IWL<13088> A_IWL<13087> A_IWL<13086> A_IWL<13085> A_IWL<13084> A_IWL<13083> A_IWL<13082> A_IWL<13081> A_IWL<13080> A_IWL<13079> A_IWL<13078> A_IWL<13077> A_IWL<13076> A_IWL<13075> A_IWL<13074> A_IWL<13073> A_IWL<13072> A_IWL<13071> A_IWL<13070> A_IWL<13069> A_IWL<13068> A_IWL<13067> A_IWL<13066> A_IWL<13065> A_IWL<13064> A_IWL<13063> A_IWL<13062> A_IWL<13061> A_IWL<13060> A_IWL<13059> A_IWL<13058> A_IWL<13057> A_IWL<13056> A_IWL<13055> A_IWL<13054> A_IWL<13053> A_IWL<13052> A_IWL<13051> A_IWL<13050> A_IWL<13049> A_IWL<13048> A_IWL<13047> A_IWL<13046> A_IWL<13045> A_IWL<13044> A_IWL<13043> A_IWL<13042> A_IWL<13041> A_IWL<13040> A_IWL<13039> A_IWL<13038> A_IWL<13037> A_IWL<13036> A_IWL<13035> A_IWL<13034> A_IWL<13033> A_IWL<13032> A_IWL<13031> A_IWL<13030> A_IWL<13029> A_IWL<13028> A_IWL<13027> A_IWL<13026> A_IWL<13025> A_IWL<13024> A_IWL<13023> A_IWL<13022> A_IWL<13021> A_IWL<13020> A_IWL<13019> A_IWL<13018> A_IWL<13017> A_IWL<13016> A_IWL<13015> A_IWL<13014> A_IWL<13013> A_IWL<13012> A_IWL<13011> A_IWL<13010> A_IWL<13009> A_IWL<13008> A_IWL<13007> A_IWL<13006> A_IWL<13005> A_IWL<13004> A_IWL<13003> A_IWL<13002> A_IWL<13001> A_IWL<13000> A_IWL<12999> A_IWL<12998> A_IWL<12997> A_IWL<12996> A_IWL<12995> A_IWL<12994> A_IWL<12993> A_IWL<12992> A_IWL<12991> A_IWL<12990> A_IWL<12989> A_IWL<12988> A_IWL<12987> A_IWL<12986> A_IWL<12985> A_IWL<12984> A_IWL<12983> A_IWL<12982> A_IWL<12981> A_IWL<12980> A_IWL<12979> A_IWL<12978> A_IWL<12977> A_IWL<12976> A_IWL<12975> A_IWL<12974> A_IWL<12973> A_IWL<12972> A_IWL<12971> A_IWL<12970> A_IWL<12969> A_IWL<12968> A_IWL<12967> A_IWL<12966> A_IWL<12965> A_IWL<12964> A_IWL<12963> A_IWL<12962> A_IWL<12961> A_IWL<12960> A_IWL<12959> A_IWL<12958> A_IWL<12957> A_IWL<12956> A_IWL<12955> A_IWL<12954> A_IWL<12953> A_IWL<12952> A_IWL<12951> A_IWL<12950> A_IWL<12949> A_IWL<12948> A_IWL<12947> A_IWL<12946> A_IWL<12945> A_IWL<12944> A_IWL<12943> A_IWL<12942> A_IWL<12941> A_IWL<12940> A_IWL<12939> A_IWL<12938> A_IWL<12937> A_IWL<12936> A_IWL<12935> A_IWL<12934> A_IWL<12933> A_IWL<12932> A_IWL<12931> A_IWL<12930> A_IWL<12929> A_IWL<12928> A_IWL<12927> A_IWL<12926> A_IWL<12925> A_IWL<12924> A_IWL<12923> A_IWL<12922> A_IWL<12921> A_IWL<12920> A_IWL<12919> A_IWL<12918> A_IWL<12917> A_IWL<12916> A_IWL<12915> A_IWL<12914> A_IWL<12913> A_IWL<12912> A_IWL<12911> A_IWL<12910> A_IWL<12909> A_IWL<12908> A_IWL<12907> A_IWL<12906> A_IWL<12905> A_IWL<12904> A_IWL<12903> A_IWL<12902> A_IWL<12901> A_IWL<12900> A_IWL<12899> A_IWL<12898> A_IWL<12897> A_IWL<12896> A_IWL<12895> A_IWL<12894> A_IWL<12893> A_IWL<12892> A_IWL<12891> A_IWL<12890> A_IWL<12889> A_IWL<12888> A_IWL<12887> A_IWL<12886> A_IWL<12885> A_IWL<12884> A_IWL<12883> A_IWL<12882> A_IWL<12881> A_IWL<12880> A_IWL<12879> A_IWL<12878> A_IWL<12877> A_IWL<12876> A_IWL<12875> A_IWL<12874> A_IWL<12873> A_IWL<12872> A_IWL<12871> A_IWL<12870> A_IWL<12869> A_IWL<12868> A_IWL<12867> A_IWL<12866> A_IWL<12865> A_IWL<12864> A_IWL<12863> A_IWL<12862> A_IWL<12861> A_IWL<12860> A_IWL<12859> A_IWL<12858> A_IWL<12857> A_IWL<12856> A_IWL<12855> A_IWL<12854> A_IWL<12853> A_IWL<12852> A_IWL<12851> A_IWL<12850> A_IWL<12849> A_IWL<12848> A_IWL<12847> A_IWL<12846> A_IWL<12845> A_IWL<12844> A_IWL<12843> A_IWL<12842> A_IWL<12841> A_IWL<12840> A_IWL<12839> A_IWL<12838> A_IWL<12837> A_IWL<12836> A_IWL<12835> A_IWL<12834> A_IWL<12833> A_IWL<12832> A_IWL<12831> A_IWL<12830> A_IWL<12829> A_IWL<12828> A_IWL<12827> A_IWL<12826> A_IWL<12825> A_IWL<12824> A_IWL<12823> A_IWL<12822> A_IWL<12821> A_IWL<12820> A_IWL<12819> A_IWL<12818> A_IWL<12817> A_IWL<12816> A_IWL<12815> A_IWL<12814> A_IWL<12813> A_IWL<12812> A_IWL<12811> A_IWL<12810> A_IWL<12809> A_IWL<12808> A_IWL<12807> A_IWL<12806> A_IWL<12805> A_IWL<12804> A_IWL<12803> A_IWL<12802> A_IWL<12801> A_IWL<12800> A_IWL<13823> A_IWL<13822> A_IWL<13821> A_IWL<13820> A_IWL<13819> A_IWL<13818> A_IWL<13817> A_IWL<13816> A_IWL<13815> A_IWL<13814> A_IWL<13813> A_IWL<13812> A_IWL<13811> A_IWL<13810> A_IWL<13809> A_IWL<13808> A_IWL<13807> A_IWL<13806> A_IWL<13805> A_IWL<13804> A_IWL<13803> A_IWL<13802> A_IWL<13801> A_IWL<13800> A_IWL<13799> A_IWL<13798> A_IWL<13797> A_IWL<13796> A_IWL<13795> A_IWL<13794> A_IWL<13793> A_IWL<13792> A_IWL<13791> A_IWL<13790> A_IWL<13789> A_IWL<13788> A_IWL<13787> A_IWL<13786> A_IWL<13785> A_IWL<13784> A_IWL<13783> A_IWL<13782> A_IWL<13781> A_IWL<13780> A_IWL<13779> A_IWL<13778> A_IWL<13777> A_IWL<13776> A_IWL<13775> A_IWL<13774> A_IWL<13773> A_IWL<13772> A_IWL<13771> A_IWL<13770> A_IWL<13769> A_IWL<13768> A_IWL<13767> A_IWL<13766> A_IWL<13765> A_IWL<13764> A_IWL<13763> A_IWL<13762> A_IWL<13761> A_IWL<13760> A_IWL<13759> A_IWL<13758> A_IWL<13757> A_IWL<13756> A_IWL<13755> A_IWL<13754> A_IWL<13753> A_IWL<13752> A_IWL<13751> A_IWL<13750> A_IWL<13749> A_IWL<13748> A_IWL<13747> A_IWL<13746> A_IWL<13745> A_IWL<13744> A_IWL<13743> A_IWL<13742> A_IWL<13741> A_IWL<13740> A_IWL<13739> A_IWL<13738> A_IWL<13737> A_IWL<13736> A_IWL<13735> A_IWL<13734> A_IWL<13733> A_IWL<13732> A_IWL<13731> A_IWL<13730> A_IWL<13729> A_IWL<13728> A_IWL<13727> A_IWL<13726> A_IWL<13725> A_IWL<13724> A_IWL<13723> A_IWL<13722> A_IWL<13721> A_IWL<13720> A_IWL<13719> A_IWL<13718> A_IWL<13717> A_IWL<13716> A_IWL<13715> A_IWL<13714> A_IWL<13713> A_IWL<13712> A_IWL<13711> A_IWL<13710> A_IWL<13709> A_IWL<13708> A_IWL<13707> A_IWL<13706> A_IWL<13705> A_IWL<13704> A_IWL<13703> A_IWL<13702> A_IWL<13701> A_IWL<13700> A_IWL<13699> A_IWL<13698> A_IWL<13697> A_IWL<13696> A_IWL<13695> A_IWL<13694> A_IWL<13693> A_IWL<13692> A_IWL<13691> A_IWL<13690> A_IWL<13689> A_IWL<13688> A_IWL<13687> A_IWL<13686> A_IWL<13685> A_IWL<13684> A_IWL<13683> A_IWL<13682> A_IWL<13681> A_IWL<13680> A_IWL<13679> A_IWL<13678> A_IWL<13677> A_IWL<13676> A_IWL<13675> A_IWL<13674> A_IWL<13673> A_IWL<13672> A_IWL<13671> A_IWL<13670> A_IWL<13669> A_IWL<13668> A_IWL<13667> A_IWL<13666> A_IWL<13665> A_IWL<13664> A_IWL<13663> A_IWL<13662> A_IWL<13661> A_IWL<13660> A_IWL<13659> A_IWL<13658> A_IWL<13657> A_IWL<13656> A_IWL<13655> A_IWL<13654> A_IWL<13653> A_IWL<13652> A_IWL<13651> A_IWL<13650> A_IWL<13649> A_IWL<13648> A_IWL<13647> A_IWL<13646> A_IWL<13645> A_IWL<13644> A_IWL<13643> A_IWL<13642> A_IWL<13641> A_IWL<13640> A_IWL<13639> A_IWL<13638> A_IWL<13637> A_IWL<13636> A_IWL<13635> A_IWL<13634> A_IWL<13633> A_IWL<13632> A_IWL<13631> A_IWL<13630> A_IWL<13629> A_IWL<13628> A_IWL<13627> A_IWL<13626> A_IWL<13625> A_IWL<13624> A_IWL<13623> A_IWL<13622> A_IWL<13621> A_IWL<13620> A_IWL<13619> A_IWL<13618> A_IWL<13617> A_IWL<13616> A_IWL<13615> A_IWL<13614> A_IWL<13613> A_IWL<13612> A_IWL<13611> A_IWL<13610> A_IWL<13609> A_IWL<13608> A_IWL<13607> A_IWL<13606> A_IWL<13605> A_IWL<13604> A_IWL<13603> A_IWL<13602> A_IWL<13601> A_IWL<13600> A_IWL<13599> A_IWL<13598> A_IWL<13597> A_IWL<13596> A_IWL<13595> A_IWL<13594> A_IWL<13593> A_IWL<13592> A_IWL<13591> A_IWL<13590> A_IWL<13589> A_IWL<13588> A_IWL<13587> A_IWL<13586> A_IWL<13585> A_IWL<13584> A_IWL<13583> A_IWL<13582> A_IWL<13581> A_IWL<13580> A_IWL<13579> A_IWL<13578> A_IWL<13577> A_IWL<13576> A_IWL<13575> A_IWL<13574> A_IWL<13573> A_IWL<13572> A_IWL<13571> A_IWL<13570> A_IWL<13569> A_IWL<13568> A_IWL<13567> A_IWL<13566> A_IWL<13565> A_IWL<13564> A_IWL<13563> A_IWL<13562> A_IWL<13561> A_IWL<13560> A_IWL<13559> A_IWL<13558> A_IWL<13557> A_IWL<13556> A_IWL<13555> A_IWL<13554> A_IWL<13553> A_IWL<13552> A_IWL<13551> A_IWL<13550> A_IWL<13549> A_IWL<13548> A_IWL<13547> A_IWL<13546> A_IWL<13545> A_IWL<13544> A_IWL<13543> A_IWL<13542> A_IWL<13541> A_IWL<13540> A_IWL<13539> A_IWL<13538> A_IWL<13537> A_IWL<13536> A_IWL<13535> A_IWL<13534> A_IWL<13533> A_IWL<13532> A_IWL<13531> A_IWL<13530> A_IWL<13529> A_IWL<13528> A_IWL<13527> A_IWL<13526> A_IWL<13525> A_IWL<13524> A_IWL<13523> A_IWL<13522> A_IWL<13521> A_IWL<13520> A_IWL<13519> A_IWL<13518> A_IWL<13517> A_IWL<13516> A_IWL<13515> A_IWL<13514> A_IWL<13513> A_IWL<13512> A_IWL<13511> A_IWL<13510> A_IWL<13509> A_IWL<13508> A_IWL<13507> A_IWL<13506> A_IWL<13505> A_IWL<13504> A_IWL<13503> A_IWL<13502> A_IWL<13501> A_IWL<13500> A_IWL<13499> A_IWL<13498> A_IWL<13497> A_IWL<13496> A_IWL<13495> A_IWL<13494> A_IWL<13493> A_IWL<13492> A_IWL<13491> A_IWL<13490> A_IWL<13489> A_IWL<13488> A_IWL<13487> A_IWL<13486> A_IWL<13485> A_IWL<13484> A_IWL<13483> A_IWL<13482> A_IWL<13481> A_IWL<13480> A_IWL<13479> A_IWL<13478> A_IWL<13477> A_IWL<13476> A_IWL<13475> A_IWL<13474> A_IWL<13473> A_IWL<13472> A_IWL<13471> A_IWL<13470> A_IWL<13469> A_IWL<13468> A_IWL<13467> A_IWL<13466> A_IWL<13465> A_IWL<13464> A_IWL<13463> A_IWL<13462> A_IWL<13461> A_IWL<13460> A_IWL<13459> A_IWL<13458> A_IWL<13457> A_IWL<13456> A_IWL<13455> A_IWL<13454> A_IWL<13453> A_IWL<13452> A_IWL<13451> A_IWL<13450> A_IWL<13449> A_IWL<13448> A_IWL<13447> A_IWL<13446> A_IWL<13445> A_IWL<13444> A_IWL<13443> A_IWL<13442> A_IWL<13441> A_IWL<13440> A_IWL<13439> A_IWL<13438> A_IWL<13437> A_IWL<13436> A_IWL<13435> A_IWL<13434> A_IWL<13433> A_IWL<13432> A_IWL<13431> A_IWL<13430> A_IWL<13429> A_IWL<13428> A_IWL<13427> A_IWL<13426> A_IWL<13425> A_IWL<13424> A_IWL<13423> A_IWL<13422> A_IWL<13421> A_IWL<13420> A_IWL<13419> A_IWL<13418> A_IWL<13417> A_IWL<13416> A_IWL<13415> A_IWL<13414> A_IWL<13413> A_IWL<13412> A_IWL<13411> A_IWL<13410> A_IWL<13409> A_IWL<13408> A_IWL<13407> A_IWL<13406> A_IWL<13405> A_IWL<13404> A_IWL<13403> A_IWL<13402> A_IWL<13401> A_IWL<13400> A_IWL<13399> A_IWL<13398> A_IWL<13397> A_IWL<13396> A_IWL<13395> A_IWL<13394> A_IWL<13393> A_IWL<13392> A_IWL<13391> A_IWL<13390> A_IWL<13389> A_IWL<13388> A_IWL<13387> A_IWL<13386> A_IWL<13385> A_IWL<13384> A_IWL<13383> A_IWL<13382> A_IWL<13381> A_IWL<13380> A_IWL<13379> A_IWL<13378> A_IWL<13377> A_IWL<13376> A_IWL<13375> A_IWL<13374> A_IWL<13373> A_IWL<13372> A_IWL<13371> A_IWL<13370> A_IWL<13369> A_IWL<13368> A_IWL<13367> A_IWL<13366> A_IWL<13365> A_IWL<13364> A_IWL<13363> A_IWL<13362> A_IWL<13361> A_IWL<13360> A_IWL<13359> A_IWL<13358> A_IWL<13357> A_IWL<13356> A_IWL<13355> A_IWL<13354> A_IWL<13353> A_IWL<13352> A_IWL<13351> A_IWL<13350> A_IWL<13349> A_IWL<13348> A_IWL<13347> A_IWL<13346> A_IWL<13345> A_IWL<13344> A_IWL<13343> A_IWL<13342> A_IWL<13341> A_IWL<13340> A_IWL<13339> A_IWL<13338> A_IWL<13337> A_IWL<13336> A_IWL<13335> A_IWL<13334> A_IWL<13333> A_IWL<13332> A_IWL<13331> A_IWL<13330> A_IWL<13329> A_IWL<13328> A_IWL<13327> A_IWL<13326> A_IWL<13325> A_IWL<13324> A_IWL<13323> A_IWL<13322> A_IWL<13321> A_IWL<13320> A_IWL<13319> A_IWL<13318> A_IWL<13317> A_IWL<13316> A_IWL<13315> A_IWL<13314> A_IWL<13313> A_IWL<13312> VDD_CORE VSS / RM_IHPSG13_8192x32_c4_1P_COLUMN_pcell_0 +XCOL<25> A_BLC<51> A_BLC<50> A_BLC_TOP<51> A_BLC_TOP<50> A_BLT<51> A_BLT<50> A_BLT_TOP<51> A_BLT_TOP<50> A_IWL<12799> A_IWL<12798> A_IWL<12797> A_IWL<12796> A_IWL<12795> A_IWL<12794> A_IWL<12793> A_IWL<12792> A_IWL<12791> A_IWL<12790> A_IWL<12789> A_IWL<12788> A_IWL<12787> A_IWL<12786> A_IWL<12785> A_IWL<12784> A_IWL<12783> A_IWL<12782> A_IWL<12781> A_IWL<12780> A_IWL<12779> A_IWL<12778> A_IWL<12777> A_IWL<12776> A_IWL<12775> A_IWL<12774> A_IWL<12773> A_IWL<12772> A_IWL<12771> A_IWL<12770> A_IWL<12769> A_IWL<12768> A_IWL<12767> A_IWL<12766> A_IWL<12765> A_IWL<12764> A_IWL<12763> A_IWL<12762> A_IWL<12761> A_IWL<12760> A_IWL<12759> A_IWL<12758> A_IWL<12757> A_IWL<12756> A_IWL<12755> A_IWL<12754> A_IWL<12753> A_IWL<12752> A_IWL<12751> A_IWL<12750> A_IWL<12749> A_IWL<12748> A_IWL<12747> A_IWL<12746> A_IWL<12745> A_IWL<12744> A_IWL<12743> A_IWL<12742> A_IWL<12741> A_IWL<12740> A_IWL<12739> A_IWL<12738> A_IWL<12737> A_IWL<12736> A_IWL<12735> A_IWL<12734> A_IWL<12733> A_IWL<12732> A_IWL<12731> A_IWL<12730> A_IWL<12729> A_IWL<12728> A_IWL<12727> A_IWL<12726> A_IWL<12725> A_IWL<12724> A_IWL<12723> A_IWL<12722> A_IWL<12721> A_IWL<12720> A_IWL<12719> A_IWL<12718> A_IWL<12717> A_IWL<12716> A_IWL<12715> A_IWL<12714> A_IWL<12713> A_IWL<12712> A_IWL<12711> A_IWL<12710> A_IWL<12709> A_IWL<12708> A_IWL<12707> A_IWL<12706> A_IWL<12705> A_IWL<12704> A_IWL<12703> A_IWL<12702> A_IWL<12701> A_IWL<12700> A_IWL<12699> A_IWL<12698> A_IWL<12697> A_IWL<12696> A_IWL<12695> A_IWL<12694> A_IWL<12693> A_IWL<12692> A_IWL<12691> A_IWL<12690> A_IWL<12689> A_IWL<12688> A_IWL<12687> A_IWL<12686> A_IWL<12685> A_IWL<12684> A_IWL<12683> A_IWL<12682> A_IWL<12681> A_IWL<12680> A_IWL<12679> A_IWL<12678> A_IWL<12677> A_IWL<12676> A_IWL<12675> A_IWL<12674> A_IWL<12673> A_IWL<12672> A_IWL<12671> A_IWL<12670> A_IWL<12669> A_IWL<12668> A_IWL<12667> A_IWL<12666> A_IWL<12665> A_IWL<12664> A_IWL<12663> A_IWL<12662> A_IWL<12661> A_IWL<12660> A_IWL<12659> A_IWL<12658> A_IWL<12657> A_IWL<12656> A_IWL<12655> A_IWL<12654> A_IWL<12653> A_IWL<12652> A_IWL<12651> A_IWL<12650> A_IWL<12649> A_IWL<12648> A_IWL<12647> A_IWL<12646> A_IWL<12645> A_IWL<12644> A_IWL<12643> A_IWL<12642> A_IWL<12641> A_IWL<12640> A_IWL<12639> A_IWL<12638> A_IWL<12637> A_IWL<12636> A_IWL<12635> A_IWL<12634> A_IWL<12633> A_IWL<12632> A_IWL<12631> A_IWL<12630> A_IWL<12629> A_IWL<12628> A_IWL<12627> A_IWL<12626> A_IWL<12625> A_IWL<12624> A_IWL<12623> A_IWL<12622> A_IWL<12621> A_IWL<12620> A_IWL<12619> A_IWL<12618> A_IWL<12617> A_IWL<12616> A_IWL<12615> A_IWL<12614> A_IWL<12613> A_IWL<12612> A_IWL<12611> A_IWL<12610> A_IWL<12609> A_IWL<12608> A_IWL<12607> A_IWL<12606> A_IWL<12605> A_IWL<12604> A_IWL<12603> A_IWL<12602> A_IWL<12601> A_IWL<12600> A_IWL<12599> A_IWL<12598> A_IWL<12597> A_IWL<12596> A_IWL<12595> A_IWL<12594> A_IWL<12593> A_IWL<12592> A_IWL<12591> A_IWL<12590> A_IWL<12589> A_IWL<12588> A_IWL<12587> A_IWL<12586> A_IWL<12585> A_IWL<12584> A_IWL<12583> A_IWL<12582> A_IWL<12581> A_IWL<12580> A_IWL<12579> A_IWL<12578> A_IWL<12577> A_IWL<12576> A_IWL<12575> A_IWL<12574> A_IWL<12573> A_IWL<12572> A_IWL<12571> A_IWL<12570> A_IWL<12569> A_IWL<12568> A_IWL<12567> A_IWL<12566> A_IWL<12565> A_IWL<12564> A_IWL<12563> A_IWL<12562> A_IWL<12561> A_IWL<12560> A_IWL<12559> A_IWL<12558> A_IWL<12557> A_IWL<12556> A_IWL<12555> A_IWL<12554> A_IWL<12553> A_IWL<12552> A_IWL<12551> A_IWL<12550> A_IWL<12549> A_IWL<12548> A_IWL<12547> A_IWL<12546> A_IWL<12545> A_IWL<12544> A_IWL<12543> A_IWL<12542> A_IWL<12541> A_IWL<12540> A_IWL<12539> A_IWL<12538> A_IWL<12537> A_IWL<12536> A_IWL<12535> A_IWL<12534> A_IWL<12533> A_IWL<12532> A_IWL<12531> A_IWL<12530> A_IWL<12529> A_IWL<12528> A_IWL<12527> A_IWL<12526> A_IWL<12525> A_IWL<12524> A_IWL<12523> A_IWL<12522> A_IWL<12521> A_IWL<12520> A_IWL<12519> A_IWL<12518> A_IWL<12517> A_IWL<12516> A_IWL<12515> A_IWL<12514> A_IWL<12513> A_IWL<12512> A_IWL<12511> A_IWL<12510> A_IWL<12509> A_IWL<12508> A_IWL<12507> A_IWL<12506> A_IWL<12505> A_IWL<12504> A_IWL<12503> A_IWL<12502> A_IWL<12501> A_IWL<12500> A_IWL<12499> A_IWL<12498> A_IWL<12497> A_IWL<12496> A_IWL<12495> A_IWL<12494> A_IWL<12493> A_IWL<12492> A_IWL<12491> A_IWL<12490> A_IWL<12489> A_IWL<12488> A_IWL<12487> A_IWL<12486> A_IWL<12485> A_IWL<12484> A_IWL<12483> A_IWL<12482> A_IWL<12481> A_IWL<12480> A_IWL<12479> A_IWL<12478> A_IWL<12477> A_IWL<12476> A_IWL<12475> A_IWL<12474> A_IWL<12473> A_IWL<12472> A_IWL<12471> A_IWL<12470> A_IWL<12469> A_IWL<12468> A_IWL<12467> A_IWL<12466> A_IWL<12465> A_IWL<12464> A_IWL<12463> A_IWL<12462> A_IWL<12461> A_IWL<12460> A_IWL<12459> A_IWL<12458> A_IWL<12457> A_IWL<12456> A_IWL<12455> A_IWL<12454> A_IWL<12453> A_IWL<12452> A_IWL<12451> A_IWL<12450> A_IWL<12449> A_IWL<12448> A_IWL<12447> A_IWL<12446> A_IWL<12445> A_IWL<12444> A_IWL<12443> A_IWL<12442> A_IWL<12441> A_IWL<12440> A_IWL<12439> A_IWL<12438> A_IWL<12437> A_IWL<12436> A_IWL<12435> A_IWL<12434> A_IWL<12433> A_IWL<12432> A_IWL<12431> A_IWL<12430> A_IWL<12429> A_IWL<12428> A_IWL<12427> A_IWL<12426> A_IWL<12425> A_IWL<12424> A_IWL<12423> A_IWL<12422> A_IWL<12421> A_IWL<12420> A_IWL<12419> A_IWL<12418> A_IWL<12417> A_IWL<12416> A_IWL<12415> A_IWL<12414> A_IWL<12413> A_IWL<12412> A_IWL<12411> A_IWL<12410> A_IWL<12409> A_IWL<12408> A_IWL<12407> A_IWL<12406> A_IWL<12405> A_IWL<12404> A_IWL<12403> A_IWL<12402> A_IWL<12401> A_IWL<12400> A_IWL<12399> A_IWL<12398> A_IWL<12397> A_IWL<12396> A_IWL<12395> A_IWL<12394> A_IWL<12393> A_IWL<12392> A_IWL<12391> A_IWL<12390> A_IWL<12389> A_IWL<12388> A_IWL<12387> A_IWL<12386> A_IWL<12385> A_IWL<12384> A_IWL<12383> A_IWL<12382> A_IWL<12381> A_IWL<12380> A_IWL<12379> A_IWL<12378> A_IWL<12377> A_IWL<12376> A_IWL<12375> A_IWL<12374> A_IWL<12373> A_IWL<12372> A_IWL<12371> A_IWL<12370> A_IWL<12369> A_IWL<12368> A_IWL<12367> A_IWL<12366> A_IWL<12365> A_IWL<12364> A_IWL<12363> A_IWL<12362> A_IWL<12361> A_IWL<12360> A_IWL<12359> A_IWL<12358> A_IWL<12357> A_IWL<12356> A_IWL<12355> A_IWL<12354> A_IWL<12353> A_IWL<12352> A_IWL<12351> A_IWL<12350> A_IWL<12349> A_IWL<12348> A_IWL<12347> A_IWL<12346> A_IWL<12345> A_IWL<12344> A_IWL<12343> A_IWL<12342> A_IWL<12341> A_IWL<12340> A_IWL<12339> A_IWL<12338> A_IWL<12337> A_IWL<12336> A_IWL<12335> A_IWL<12334> A_IWL<12333> A_IWL<12332> A_IWL<12331> A_IWL<12330> A_IWL<12329> A_IWL<12328> A_IWL<12327> A_IWL<12326> A_IWL<12325> A_IWL<12324> A_IWL<12323> A_IWL<12322> A_IWL<12321> A_IWL<12320> A_IWL<12319> A_IWL<12318> A_IWL<12317> A_IWL<12316> A_IWL<12315> A_IWL<12314> A_IWL<12313> A_IWL<12312> A_IWL<12311> A_IWL<12310> A_IWL<12309> A_IWL<12308> A_IWL<12307> A_IWL<12306> A_IWL<12305> A_IWL<12304> A_IWL<12303> A_IWL<12302> A_IWL<12301> A_IWL<12300> A_IWL<12299> A_IWL<12298> A_IWL<12297> A_IWL<12296> A_IWL<12295> A_IWL<12294> A_IWL<12293> A_IWL<12292> A_IWL<12291> A_IWL<12290> A_IWL<12289> A_IWL<12288> A_IWL<13311> A_IWL<13310> A_IWL<13309> A_IWL<13308> A_IWL<13307> A_IWL<13306> A_IWL<13305> A_IWL<13304> A_IWL<13303> A_IWL<13302> A_IWL<13301> A_IWL<13300> A_IWL<13299> A_IWL<13298> A_IWL<13297> A_IWL<13296> A_IWL<13295> A_IWL<13294> A_IWL<13293> A_IWL<13292> A_IWL<13291> A_IWL<13290> A_IWL<13289> A_IWL<13288> A_IWL<13287> A_IWL<13286> A_IWL<13285> A_IWL<13284> A_IWL<13283> A_IWL<13282> A_IWL<13281> A_IWL<13280> A_IWL<13279> A_IWL<13278> A_IWL<13277> A_IWL<13276> A_IWL<13275> A_IWL<13274> A_IWL<13273> A_IWL<13272> A_IWL<13271> A_IWL<13270> A_IWL<13269> A_IWL<13268> A_IWL<13267> A_IWL<13266> A_IWL<13265> A_IWL<13264> A_IWL<13263> A_IWL<13262> A_IWL<13261> A_IWL<13260> A_IWL<13259> A_IWL<13258> A_IWL<13257> A_IWL<13256> A_IWL<13255> A_IWL<13254> A_IWL<13253> A_IWL<13252> A_IWL<13251> A_IWL<13250> A_IWL<13249> A_IWL<13248> A_IWL<13247> A_IWL<13246> A_IWL<13245> A_IWL<13244> A_IWL<13243> A_IWL<13242> A_IWL<13241> A_IWL<13240> A_IWL<13239> A_IWL<13238> A_IWL<13237> A_IWL<13236> A_IWL<13235> A_IWL<13234> A_IWL<13233> A_IWL<13232> A_IWL<13231> A_IWL<13230> A_IWL<13229> A_IWL<13228> A_IWL<13227> A_IWL<13226> A_IWL<13225> A_IWL<13224> A_IWL<13223> A_IWL<13222> A_IWL<13221> A_IWL<13220> A_IWL<13219> A_IWL<13218> A_IWL<13217> A_IWL<13216> A_IWL<13215> A_IWL<13214> A_IWL<13213> A_IWL<13212> A_IWL<13211> A_IWL<13210> A_IWL<13209> A_IWL<13208> A_IWL<13207> A_IWL<13206> A_IWL<13205> A_IWL<13204> A_IWL<13203> A_IWL<13202> A_IWL<13201> A_IWL<13200> A_IWL<13199> A_IWL<13198> A_IWL<13197> A_IWL<13196> A_IWL<13195> A_IWL<13194> A_IWL<13193> A_IWL<13192> A_IWL<13191> A_IWL<13190> A_IWL<13189> A_IWL<13188> A_IWL<13187> A_IWL<13186> A_IWL<13185> A_IWL<13184> A_IWL<13183> A_IWL<13182> A_IWL<13181> A_IWL<13180> A_IWL<13179> A_IWL<13178> A_IWL<13177> A_IWL<13176> A_IWL<13175> A_IWL<13174> A_IWL<13173> A_IWL<13172> A_IWL<13171> A_IWL<13170> A_IWL<13169> A_IWL<13168> A_IWL<13167> A_IWL<13166> A_IWL<13165> A_IWL<13164> A_IWL<13163> A_IWL<13162> A_IWL<13161> A_IWL<13160> A_IWL<13159> A_IWL<13158> A_IWL<13157> A_IWL<13156> A_IWL<13155> A_IWL<13154> A_IWL<13153> A_IWL<13152> A_IWL<13151> A_IWL<13150> A_IWL<13149> A_IWL<13148> A_IWL<13147> A_IWL<13146> A_IWL<13145> A_IWL<13144> A_IWL<13143> A_IWL<13142> A_IWL<13141> A_IWL<13140> A_IWL<13139> A_IWL<13138> A_IWL<13137> A_IWL<13136> A_IWL<13135> A_IWL<13134> A_IWL<13133> A_IWL<13132> A_IWL<13131> A_IWL<13130> A_IWL<13129> A_IWL<13128> A_IWL<13127> A_IWL<13126> A_IWL<13125> A_IWL<13124> A_IWL<13123> A_IWL<13122> A_IWL<13121> A_IWL<13120> A_IWL<13119> A_IWL<13118> A_IWL<13117> A_IWL<13116> A_IWL<13115> A_IWL<13114> A_IWL<13113> A_IWL<13112> A_IWL<13111> A_IWL<13110> A_IWL<13109> A_IWL<13108> A_IWL<13107> A_IWL<13106> A_IWL<13105> A_IWL<13104> A_IWL<13103> A_IWL<13102> A_IWL<13101> A_IWL<13100> A_IWL<13099> A_IWL<13098> A_IWL<13097> A_IWL<13096> A_IWL<13095> A_IWL<13094> A_IWL<13093> A_IWL<13092> A_IWL<13091> A_IWL<13090> A_IWL<13089> A_IWL<13088> A_IWL<13087> A_IWL<13086> A_IWL<13085> A_IWL<13084> A_IWL<13083> A_IWL<13082> A_IWL<13081> A_IWL<13080> A_IWL<13079> A_IWL<13078> A_IWL<13077> A_IWL<13076> A_IWL<13075> A_IWL<13074> A_IWL<13073> A_IWL<13072> A_IWL<13071> A_IWL<13070> A_IWL<13069> A_IWL<13068> A_IWL<13067> A_IWL<13066> A_IWL<13065> A_IWL<13064> A_IWL<13063> A_IWL<13062> A_IWL<13061> A_IWL<13060> A_IWL<13059> A_IWL<13058> A_IWL<13057> A_IWL<13056> A_IWL<13055> A_IWL<13054> A_IWL<13053> A_IWL<13052> A_IWL<13051> A_IWL<13050> A_IWL<13049> A_IWL<13048> A_IWL<13047> A_IWL<13046> A_IWL<13045> A_IWL<13044> A_IWL<13043> A_IWL<13042> A_IWL<13041> A_IWL<13040> A_IWL<13039> A_IWL<13038> A_IWL<13037> A_IWL<13036> A_IWL<13035> A_IWL<13034> A_IWL<13033> A_IWL<13032> A_IWL<13031> A_IWL<13030> A_IWL<13029> A_IWL<13028> A_IWL<13027> A_IWL<13026> A_IWL<13025> A_IWL<13024> A_IWL<13023> A_IWL<13022> A_IWL<13021> A_IWL<13020> A_IWL<13019> A_IWL<13018> A_IWL<13017> A_IWL<13016> A_IWL<13015> A_IWL<13014> A_IWL<13013> A_IWL<13012> A_IWL<13011> A_IWL<13010> A_IWL<13009> A_IWL<13008> A_IWL<13007> A_IWL<13006> A_IWL<13005> A_IWL<13004> A_IWL<13003> A_IWL<13002> A_IWL<13001> A_IWL<13000> A_IWL<12999> A_IWL<12998> A_IWL<12997> A_IWL<12996> A_IWL<12995> A_IWL<12994> A_IWL<12993> A_IWL<12992> A_IWL<12991> A_IWL<12990> A_IWL<12989> A_IWL<12988> A_IWL<12987> A_IWL<12986> A_IWL<12985> A_IWL<12984> A_IWL<12983> A_IWL<12982> A_IWL<12981> A_IWL<12980> A_IWL<12979> A_IWL<12978> A_IWL<12977> A_IWL<12976> A_IWL<12975> A_IWL<12974> A_IWL<12973> A_IWL<12972> A_IWL<12971> A_IWL<12970> A_IWL<12969> A_IWL<12968> A_IWL<12967> A_IWL<12966> A_IWL<12965> A_IWL<12964> A_IWL<12963> A_IWL<12962> A_IWL<12961> A_IWL<12960> A_IWL<12959> A_IWL<12958> A_IWL<12957> A_IWL<12956> A_IWL<12955> A_IWL<12954> A_IWL<12953> A_IWL<12952> A_IWL<12951> A_IWL<12950> A_IWL<12949> A_IWL<12948> A_IWL<12947> A_IWL<12946> A_IWL<12945> A_IWL<12944> A_IWL<12943> A_IWL<12942> A_IWL<12941> A_IWL<12940> A_IWL<12939> A_IWL<12938> A_IWL<12937> A_IWL<12936> A_IWL<12935> A_IWL<12934> A_IWL<12933> A_IWL<12932> A_IWL<12931> A_IWL<12930> A_IWL<12929> A_IWL<12928> A_IWL<12927> A_IWL<12926> A_IWL<12925> A_IWL<12924> A_IWL<12923> A_IWL<12922> A_IWL<12921> A_IWL<12920> A_IWL<12919> A_IWL<12918> A_IWL<12917> A_IWL<12916> A_IWL<12915> A_IWL<12914> A_IWL<12913> A_IWL<12912> A_IWL<12911> A_IWL<12910> A_IWL<12909> A_IWL<12908> A_IWL<12907> A_IWL<12906> A_IWL<12905> A_IWL<12904> A_IWL<12903> A_IWL<12902> A_IWL<12901> A_IWL<12900> A_IWL<12899> A_IWL<12898> A_IWL<12897> A_IWL<12896> A_IWL<12895> A_IWL<12894> A_IWL<12893> A_IWL<12892> A_IWL<12891> A_IWL<12890> A_IWL<12889> A_IWL<12888> A_IWL<12887> A_IWL<12886> A_IWL<12885> A_IWL<12884> A_IWL<12883> A_IWL<12882> A_IWL<12881> A_IWL<12880> A_IWL<12879> A_IWL<12878> A_IWL<12877> A_IWL<12876> A_IWL<12875> A_IWL<12874> A_IWL<12873> A_IWL<12872> A_IWL<12871> A_IWL<12870> A_IWL<12869> A_IWL<12868> A_IWL<12867> A_IWL<12866> A_IWL<12865> A_IWL<12864> A_IWL<12863> A_IWL<12862> A_IWL<12861> A_IWL<12860> A_IWL<12859> A_IWL<12858> A_IWL<12857> A_IWL<12856> A_IWL<12855> A_IWL<12854> A_IWL<12853> A_IWL<12852> A_IWL<12851> A_IWL<12850> A_IWL<12849> A_IWL<12848> A_IWL<12847> A_IWL<12846> A_IWL<12845> A_IWL<12844> A_IWL<12843> A_IWL<12842> A_IWL<12841> A_IWL<12840> A_IWL<12839> A_IWL<12838> A_IWL<12837> A_IWL<12836> A_IWL<12835> A_IWL<12834> A_IWL<12833> A_IWL<12832> A_IWL<12831> A_IWL<12830> A_IWL<12829> A_IWL<12828> A_IWL<12827> A_IWL<12826> A_IWL<12825> A_IWL<12824> A_IWL<12823> A_IWL<12822> A_IWL<12821> A_IWL<12820> A_IWL<12819> A_IWL<12818> A_IWL<12817> A_IWL<12816> A_IWL<12815> A_IWL<12814> A_IWL<12813> A_IWL<12812> A_IWL<12811> A_IWL<12810> A_IWL<12809> A_IWL<12808> A_IWL<12807> A_IWL<12806> A_IWL<12805> A_IWL<12804> A_IWL<12803> A_IWL<12802> A_IWL<12801> A_IWL<12800> VDD_CORE VSS / RM_IHPSG13_8192x32_c4_1P_COLUMN_pcell_0 +XCOL<24> A_BLC<49> A_BLC<48> A_BLC_TOP<49> A_BLC_TOP<48> A_BLT<49> A_BLT<48> A_BLT_TOP<49> A_BLT_TOP<48> A_IWL<12287> A_IWL<12286> A_IWL<12285> A_IWL<12284> A_IWL<12283> A_IWL<12282> A_IWL<12281> A_IWL<12280> A_IWL<12279> A_IWL<12278> A_IWL<12277> A_IWL<12276> A_IWL<12275> A_IWL<12274> A_IWL<12273> A_IWL<12272> A_IWL<12271> A_IWL<12270> A_IWL<12269> A_IWL<12268> A_IWL<12267> A_IWL<12266> A_IWL<12265> A_IWL<12264> A_IWL<12263> A_IWL<12262> A_IWL<12261> A_IWL<12260> A_IWL<12259> A_IWL<12258> A_IWL<12257> A_IWL<12256> A_IWL<12255> A_IWL<12254> A_IWL<12253> A_IWL<12252> A_IWL<12251> A_IWL<12250> A_IWL<12249> A_IWL<12248> A_IWL<12247> A_IWL<12246> A_IWL<12245> A_IWL<12244> A_IWL<12243> A_IWL<12242> A_IWL<12241> A_IWL<12240> A_IWL<12239> A_IWL<12238> A_IWL<12237> A_IWL<12236> A_IWL<12235> A_IWL<12234> A_IWL<12233> A_IWL<12232> A_IWL<12231> A_IWL<12230> A_IWL<12229> A_IWL<12228> A_IWL<12227> A_IWL<12226> A_IWL<12225> A_IWL<12224> A_IWL<12223> A_IWL<12222> A_IWL<12221> A_IWL<12220> A_IWL<12219> A_IWL<12218> A_IWL<12217> A_IWL<12216> A_IWL<12215> A_IWL<12214> A_IWL<12213> A_IWL<12212> A_IWL<12211> A_IWL<12210> A_IWL<12209> A_IWL<12208> A_IWL<12207> A_IWL<12206> A_IWL<12205> A_IWL<12204> A_IWL<12203> A_IWL<12202> A_IWL<12201> A_IWL<12200> A_IWL<12199> A_IWL<12198> A_IWL<12197> A_IWL<12196> A_IWL<12195> A_IWL<12194> A_IWL<12193> A_IWL<12192> A_IWL<12191> A_IWL<12190> A_IWL<12189> A_IWL<12188> A_IWL<12187> A_IWL<12186> A_IWL<12185> A_IWL<12184> A_IWL<12183> A_IWL<12182> A_IWL<12181> A_IWL<12180> A_IWL<12179> A_IWL<12178> A_IWL<12177> A_IWL<12176> A_IWL<12175> A_IWL<12174> A_IWL<12173> A_IWL<12172> A_IWL<12171> A_IWL<12170> A_IWL<12169> A_IWL<12168> A_IWL<12167> A_IWL<12166> A_IWL<12165> A_IWL<12164> A_IWL<12163> A_IWL<12162> A_IWL<12161> A_IWL<12160> A_IWL<12159> A_IWL<12158> A_IWL<12157> A_IWL<12156> A_IWL<12155> A_IWL<12154> A_IWL<12153> A_IWL<12152> A_IWL<12151> A_IWL<12150> A_IWL<12149> A_IWL<12148> A_IWL<12147> A_IWL<12146> A_IWL<12145> A_IWL<12144> A_IWL<12143> A_IWL<12142> A_IWL<12141> A_IWL<12140> A_IWL<12139> A_IWL<12138> A_IWL<12137> A_IWL<12136> A_IWL<12135> A_IWL<12134> A_IWL<12133> A_IWL<12132> A_IWL<12131> A_IWL<12130> A_IWL<12129> A_IWL<12128> A_IWL<12127> A_IWL<12126> A_IWL<12125> A_IWL<12124> A_IWL<12123> A_IWL<12122> A_IWL<12121> A_IWL<12120> A_IWL<12119> A_IWL<12118> A_IWL<12117> A_IWL<12116> A_IWL<12115> A_IWL<12114> A_IWL<12113> A_IWL<12112> A_IWL<12111> A_IWL<12110> A_IWL<12109> A_IWL<12108> A_IWL<12107> A_IWL<12106> A_IWL<12105> A_IWL<12104> A_IWL<12103> A_IWL<12102> A_IWL<12101> A_IWL<12100> A_IWL<12099> A_IWL<12098> A_IWL<12097> A_IWL<12096> A_IWL<12095> A_IWL<12094> A_IWL<12093> A_IWL<12092> A_IWL<12091> A_IWL<12090> A_IWL<12089> A_IWL<12088> A_IWL<12087> A_IWL<12086> A_IWL<12085> A_IWL<12084> A_IWL<12083> A_IWL<12082> A_IWL<12081> A_IWL<12080> A_IWL<12079> A_IWL<12078> A_IWL<12077> A_IWL<12076> A_IWL<12075> A_IWL<12074> A_IWL<12073> A_IWL<12072> A_IWL<12071> A_IWL<12070> A_IWL<12069> A_IWL<12068> A_IWL<12067> A_IWL<12066> A_IWL<12065> A_IWL<12064> A_IWL<12063> A_IWL<12062> A_IWL<12061> A_IWL<12060> A_IWL<12059> A_IWL<12058> A_IWL<12057> A_IWL<12056> A_IWL<12055> A_IWL<12054> A_IWL<12053> A_IWL<12052> A_IWL<12051> A_IWL<12050> A_IWL<12049> A_IWL<12048> A_IWL<12047> A_IWL<12046> A_IWL<12045> A_IWL<12044> A_IWL<12043> A_IWL<12042> A_IWL<12041> A_IWL<12040> A_IWL<12039> A_IWL<12038> A_IWL<12037> A_IWL<12036> A_IWL<12035> A_IWL<12034> A_IWL<12033> A_IWL<12032> A_IWL<12031> A_IWL<12030> A_IWL<12029> A_IWL<12028> A_IWL<12027> A_IWL<12026> A_IWL<12025> A_IWL<12024> A_IWL<12023> A_IWL<12022> A_IWL<12021> A_IWL<12020> A_IWL<12019> A_IWL<12018> A_IWL<12017> A_IWL<12016> A_IWL<12015> A_IWL<12014> A_IWL<12013> A_IWL<12012> A_IWL<12011> A_IWL<12010> A_IWL<12009> A_IWL<12008> A_IWL<12007> A_IWL<12006> A_IWL<12005> A_IWL<12004> A_IWL<12003> A_IWL<12002> A_IWL<12001> A_IWL<12000> A_IWL<11999> A_IWL<11998> A_IWL<11997> A_IWL<11996> A_IWL<11995> A_IWL<11994> A_IWL<11993> A_IWL<11992> A_IWL<11991> A_IWL<11990> A_IWL<11989> A_IWL<11988> A_IWL<11987> A_IWL<11986> A_IWL<11985> A_IWL<11984> A_IWL<11983> A_IWL<11982> A_IWL<11981> A_IWL<11980> A_IWL<11979> A_IWL<11978> A_IWL<11977> A_IWL<11976> A_IWL<11975> A_IWL<11974> A_IWL<11973> A_IWL<11972> A_IWL<11971> A_IWL<11970> A_IWL<11969> A_IWL<11968> A_IWL<11967> A_IWL<11966> A_IWL<11965> A_IWL<11964> A_IWL<11963> A_IWL<11962> A_IWL<11961> A_IWL<11960> A_IWL<11959> A_IWL<11958> A_IWL<11957> A_IWL<11956> A_IWL<11955> A_IWL<11954> A_IWL<11953> A_IWL<11952> A_IWL<11951> A_IWL<11950> A_IWL<11949> A_IWL<11948> A_IWL<11947> A_IWL<11946> A_IWL<11945> A_IWL<11944> A_IWL<11943> A_IWL<11942> A_IWL<11941> A_IWL<11940> A_IWL<11939> A_IWL<11938> A_IWL<11937> A_IWL<11936> A_IWL<11935> A_IWL<11934> A_IWL<11933> A_IWL<11932> A_IWL<11931> A_IWL<11930> A_IWL<11929> A_IWL<11928> A_IWL<11927> A_IWL<11926> A_IWL<11925> A_IWL<11924> A_IWL<11923> A_IWL<11922> A_IWL<11921> A_IWL<11920> A_IWL<11919> A_IWL<11918> A_IWL<11917> A_IWL<11916> A_IWL<11915> A_IWL<11914> A_IWL<11913> A_IWL<11912> A_IWL<11911> A_IWL<11910> A_IWL<11909> A_IWL<11908> A_IWL<11907> A_IWL<11906> A_IWL<11905> A_IWL<11904> A_IWL<11903> A_IWL<11902> A_IWL<11901> A_IWL<11900> A_IWL<11899> A_IWL<11898> A_IWL<11897> A_IWL<11896> A_IWL<11895> A_IWL<11894> A_IWL<11893> A_IWL<11892> A_IWL<11891> A_IWL<11890> A_IWL<11889> A_IWL<11888> A_IWL<11887> A_IWL<11886> A_IWL<11885> A_IWL<11884> A_IWL<11883> A_IWL<11882> A_IWL<11881> A_IWL<11880> A_IWL<11879> A_IWL<11878> A_IWL<11877> A_IWL<11876> A_IWL<11875> A_IWL<11874> A_IWL<11873> A_IWL<11872> A_IWL<11871> A_IWL<11870> A_IWL<11869> A_IWL<11868> A_IWL<11867> A_IWL<11866> A_IWL<11865> A_IWL<11864> A_IWL<11863> A_IWL<11862> A_IWL<11861> A_IWL<11860> A_IWL<11859> A_IWL<11858> A_IWL<11857> A_IWL<11856> A_IWL<11855> A_IWL<11854> A_IWL<11853> A_IWL<11852> A_IWL<11851> A_IWL<11850> A_IWL<11849> A_IWL<11848> A_IWL<11847> A_IWL<11846> A_IWL<11845> A_IWL<11844> A_IWL<11843> A_IWL<11842> A_IWL<11841> A_IWL<11840> A_IWL<11839> A_IWL<11838> A_IWL<11837> A_IWL<11836> A_IWL<11835> A_IWL<11834> A_IWL<11833> A_IWL<11832> A_IWL<11831> A_IWL<11830> A_IWL<11829> A_IWL<11828> A_IWL<11827> A_IWL<11826> A_IWL<11825> A_IWL<11824> A_IWL<11823> A_IWL<11822> A_IWL<11821> A_IWL<11820> A_IWL<11819> A_IWL<11818> A_IWL<11817> A_IWL<11816> A_IWL<11815> A_IWL<11814> A_IWL<11813> A_IWL<11812> A_IWL<11811> A_IWL<11810> A_IWL<11809> A_IWL<11808> A_IWL<11807> A_IWL<11806> A_IWL<11805> A_IWL<11804> A_IWL<11803> A_IWL<11802> A_IWL<11801> A_IWL<11800> A_IWL<11799> A_IWL<11798> A_IWL<11797> A_IWL<11796> A_IWL<11795> A_IWL<11794> A_IWL<11793> A_IWL<11792> A_IWL<11791> A_IWL<11790> A_IWL<11789> A_IWL<11788> A_IWL<11787> A_IWL<11786> A_IWL<11785> A_IWL<11784> A_IWL<11783> A_IWL<11782> A_IWL<11781> A_IWL<11780> A_IWL<11779> A_IWL<11778> A_IWL<11777> A_IWL<11776> A_IWL<12799> A_IWL<12798> A_IWL<12797> A_IWL<12796> A_IWL<12795> A_IWL<12794> A_IWL<12793> A_IWL<12792> A_IWL<12791> A_IWL<12790> A_IWL<12789> A_IWL<12788> A_IWL<12787> A_IWL<12786> A_IWL<12785> A_IWL<12784> A_IWL<12783> A_IWL<12782> A_IWL<12781> A_IWL<12780> A_IWL<12779> A_IWL<12778> A_IWL<12777> A_IWL<12776> A_IWL<12775> A_IWL<12774> A_IWL<12773> A_IWL<12772> A_IWL<12771> A_IWL<12770> A_IWL<12769> A_IWL<12768> A_IWL<12767> A_IWL<12766> A_IWL<12765> A_IWL<12764> A_IWL<12763> A_IWL<12762> A_IWL<12761> A_IWL<12760> A_IWL<12759> A_IWL<12758> A_IWL<12757> A_IWL<12756> A_IWL<12755> A_IWL<12754> A_IWL<12753> A_IWL<12752> A_IWL<12751> A_IWL<12750> A_IWL<12749> A_IWL<12748> A_IWL<12747> A_IWL<12746> A_IWL<12745> A_IWL<12744> A_IWL<12743> A_IWL<12742> A_IWL<12741> A_IWL<12740> A_IWL<12739> A_IWL<12738> A_IWL<12737> A_IWL<12736> A_IWL<12735> A_IWL<12734> A_IWL<12733> A_IWL<12732> A_IWL<12731> A_IWL<12730> A_IWL<12729> A_IWL<12728> A_IWL<12727> A_IWL<12726> A_IWL<12725> A_IWL<12724> A_IWL<12723> A_IWL<12722> A_IWL<12721> A_IWL<12720> A_IWL<12719> A_IWL<12718> A_IWL<12717> A_IWL<12716> A_IWL<12715> A_IWL<12714> A_IWL<12713> A_IWL<12712> A_IWL<12711> A_IWL<12710> A_IWL<12709> A_IWL<12708> A_IWL<12707> A_IWL<12706> A_IWL<12705> A_IWL<12704> A_IWL<12703> A_IWL<12702> A_IWL<12701> A_IWL<12700> A_IWL<12699> A_IWL<12698> A_IWL<12697> A_IWL<12696> A_IWL<12695> A_IWL<12694> A_IWL<12693> A_IWL<12692> A_IWL<12691> A_IWL<12690> A_IWL<12689> A_IWL<12688> A_IWL<12687> A_IWL<12686> A_IWL<12685> A_IWL<12684> A_IWL<12683> A_IWL<12682> A_IWL<12681> A_IWL<12680> A_IWL<12679> A_IWL<12678> A_IWL<12677> A_IWL<12676> A_IWL<12675> A_IWL<12674> A_IWL<12673> A_IWL<12672> A_IWL<12671> A_IWL<12670> A_IWL<12669> A_IWL<12668> A_IWL<12667> A_IWL<12666> A_IWL<12665> A_IWL<12664> A_IWL<12663> A_IWL<12662> A_IWL<12661> A_IWL<12660> A_IWL<12659> A_IWL<12658> A_IWL<12657> A_IWL<12656> A_IWL<12655> A_IWL<12654> A_IWL<12653> A_IWL<12652> A_IWL<12651> A_IWL<12650> A_IWL<12649> A_IWL<12648> A_IWL<12647> A_IWL<12646> A_IWL<12645> A_IWL<12644> A_IWL<12643> A_IWL<12642> A_IWL<12641> A_IWL<12640> A_IWL<12639> A_IWL<12638> A_IWL<12637> A_IWL<12636> A_IWL<12635> A_IWL<12634> A_IWL<12633> A_IWL<12632> A_IWL<12631> A_IWL<12630> A_IWL<12629> A_IWL<12628> A_IWL<12627> A_IWL<12626> A_IWL<12625> A_IWL<12624> A_IWL<12623> A_IWL<12622> A_IWL<12621> A_IWL<12620> A_IWL<12619> A_IWL<12618> A_IWL<12617> A_IWL<12616> A_IWL<12615> A_IWL<12614> A_IWL<12613> A_IWL<12612> A_IWL<12611> A_IWL<12610> A_IWL<12609> A_IWL<12608> A_IWL<12607> A_IWL<12606> A_IWL<12605> A_IWL<12604> A_IWL<12603> A_IWL<12602> A_IWL<12601> A_IWL<12600> A_IWL<12599> A_IWL<12598> A_IWL<12597> A_IWL<12596> A_IWL<12595> A_IWL<12594> A_IWL<12593> A_IWL<12592> A_IWL<12591> A_IWL<12590> A_IWL<12589> A_IWL<12588> A_IWL<12587> A_IWL<12586> A_IWL<12585> A_IWL<12584> A_IWL<12583> A_IWL<12582> A_IWL<12581> A_IWL<12580> A_IWL<12579> A_IWL<12578> A_IWL<12577> A_IWL<12576> A_IWL<12575> A_IWL<12574> A_IWL<12573> A_IWL<12572> A_IWL<12571> A_IWL<12570> A_IWL<12569> A_IWL<12568> A_IWL<12567> A_IWL<12566> A_IWL<12565> A_IWL<12564> A_IWL<12563> A_IWL<12562> A_IWL<12561> A_IWL<12560> A_IWL<12559> A_IWL<12558> A_IWL<12557> A_IWL<12556> A_IWL<12555> A_IWL<12554> A_IWL<12553> A_IWL<12552> A_IWL<12551> A_IWL<12550> A_IWL<12549> A_IWL<12548> A_IWL<12547> A_IWL<12546> A_IWL<12545> A_IWL<12544> A_IWL<12543> A_IWL<12542> A_IWL<12541> A_IWL<12540> A_IWL<12539> A_IWL<12538> A_IWL<12537> A_IWL<12536> A_IWL<12535> A_IWL<12534> A_IWL<12533> A_IWL<12532> A_IWL<12531> A_IWL<12530> A_IWL<12529> A_IWL<12528> A_IWL<12527> A_IWL<12526> A_IWL<12525> A_IWL<12524> A_IWL<12523> A_IWL<12522> A_IWL<12521> A_IWL<12520> A_IWL<12519> A_IWL<12518> A_IWL<12517> A_IWL<12516> A_IWL<12515> A_IWL<12514> A_IWL<12513> A_IWL<12512> A_IWL<12511> A_IWL<12510> A_IWL<12509> A_IWL<12508> A_IWL<12507> A_IWL<12506> A_IWL<12505> A_IWL<12504> A_IWL<12503> A_IWL<12502> A_IWL<12501> A_IWL<12500> A_IWL<12499> A_IWL<12498> A_IWL<12497> A_IWL<12496> A_IWL<12495> A_IWL<12494> A_IWL<12493> A_IWL<12492> A_IWL<12491> A_IWL<12490> A_IWL<12489> A_IWL<12488> A_IWL<12487> A_IWL<12486> A_IWL<12485> A_IWL<12484> A_IWL<12483> A_IWL<12482> A_IWL<12481> A_IWL<12480> A_IWL<12479> A_IWL<12478> A_IWL<12477> A_IWL<12476> A_IWL<12475> A_IWL<12474> A_IWL<12473> A_IWL<12472> A_IWL<12471> A_IWL<12470> A_IWL<12469> A_IWL<12468> A_IWL<12467> A_IWL<12466> A_IWL<12465> A_IWL<12464> A_IWL<12463> A_IWL<12462> A_IWL<12461> A_IWL<12460> A_IWL<12459> A_IWL<12458> A_IWL<12457> A_IWL<12456> A_IWL<12455> A_IWL<12454> A_IWL<12453> A_IWL<12452> A_IWL<12451> A_IWL<12450> A_IWL<12449> A_IWL<12448> A_IWL<12447> A_IWL<12446> A_IWL<12445> A_IWL<12444> A_IWL<12443> A_IWL<12442> A_IWL<12441> A_IWL<12440> A_IWL<12439> A_IWL<12438> A_IWL<12437> A_IWL<12436> A_IWL<12435> A_IWL<12434> A_IWL<12433> A_IWL<12432> A_IWL<12431> A_IWL<12430> A_IWL<12429> A_IWL<12428> A_IWL<12427> A_IWL<12426> A_IWL<12425> A_IWL<12424> A_IWL<12423> A_IWL<12422> A_IWL<12421> A_IWL<12420> A_IWL<12419> A_IWL<12418> A_IWL<12417> A_IWL<12416> A_IWL<12415> A_IWL<12414> A_IWL<12413> A_IWL<12412> A_IWL<12411> A_IWL<12410> A_IWL<12409> A_IWL<12408> A_IWL<12407> A_IWL<12406> A_IWL<12405> A_IWL<12404> A_IWL<12403> A_IWL<12402> A_IWL<12401> A_IWL<12400> A_IWL<12399> A_IWL<12398> A_IWL<12397> A_IWL<12396> A_IWL<12395> A_IWL<12394> A_IWL<12393> A_IWL<12392> A_IWL<12391> A_IWL<12390> A_IWL<12389> A_IWL<12388> A_IWL<12387> A_IWL<12386> A_IWL<12385> A_IWL<12384> A_IWL<12383> A_IWL<12382> A_IWL<12381> A_IWL<12380> A_IWL<12379> A_IWL<12378> A_IWL<12377> A_IWL<12376> A_IWL<12375> A_IWL<12374> A_IWL<12373> A_IWL<12372> A_IWL<12371> A_IWL<12370> A_IWL<12369> A_IWL<12368> A_IWL<12367> A_IWL<12366> A_IWL<12365> A_IWL<12364> A_IWL<12363> A_IWL<12362> A_IWL<12361> A_IWL<12360> A_IWL<12359> A_IWL<12358> A_IWL<12357> A_IWL<12356> A_IWL<12355> A_IWL<12354> A_IWL<12353> A_IWL<12352> A_IWL<12351> A_IWL<12350> A_IWL<12349> A_IWL<12348> A_IWL<12347> A_IWL<12346> A_IWL<12345> A_IWL<12344> A_IWL<12343> A_IWL<12342> A_IWL<12341> A_IWL<12340> A_IWL<12339> A_IWL<12338> A_IWL<12337> A_IWL<12336> A_IWL<12335> A_IWL<12334> A_IWL<12333> A_IWL<12332> A_IWL<12331> A_IWL<12330> A_IWL<12329> A_IWL<12328> A_IWL<12327> A_IWL<12326> A_IWL<12325> A_IWL<12324> A_IWL<12323> A_IWL<12322> A_IWL<12321> A_IWL<12320> A_IWL<12319> A_IWL<12318> A_IWL<12317> A_IWL<12316> A_IWL<12315> A_IWL<12314> A_IWL<12313> A_IWL<12312> A_IWL<12311> A_IWL<12310> A_IWL<12309> A_IWL<12308> A_IWL<12307> A_IWL<12306> A_IWL<12305> A_IWL<12304> A_IWL<12303> A_IWL<12302> A_IWL<12301> A_IWL<12300> A_IWL<12299> A_IWL<12298> A_IWL<12297> A_IWL<12296> A_IWL<12295> A_IWL<12294> A_IWL<12293> A_IWL<12292> A_IWL<12291> A_IWL<12290> A_IWL<12289> A_IWL<12288> VDD_CORE VSS / RM_IHPSG13_8192x32_c4_1P_COLUMN_pcell_0 +XCOL<23> A_BLC<47> A_BLC<46> A_BLC_TOP<47> A_BLC_TOP<46> A_BLT<47> A_BLT<46> A_BLT_TOP<47> A_BLT_TOP<46> A_IWL<11775> A_IWL<11774> A_IWL<11773> A_IWL<11772> A_IWL<11771> A_IWL<11770> A_IWL<11769> A_IWL<11768> A_IWL<11767> A_IWL<11766> A_IWL<11765> A_IWL<11764> A_IWL<11763> A_IWL<11762> A_IWL<11761> A_IWL<11760> A_IWL<11759> A_IWL<11758> A_IWL<11757> A_IWL<11756> A_IWL<11755> A_IWL<11754> A_IWL<11753> A_IWL<11752> A_IWL<11751> A_IWL<11750> A_IWL<11749> A_IWL<11748> A_IWL<11747> A_IWL<11746> A_IWL<11745> A_IWL<11744> A_IWL<11743> A_IWL<11742> A_IWL<11741> A_IWL<11740> A_IWL<11739> A_IWL<11738> A_IWL<11737> A_IWL<11736> A_IWL<11735> A_IWL<11734> A_IWL<11733> A_IWL<11732> A_IWL<11731> A_IWL<11730> A_IWL<11729> A_IWL<11728> A_IWL<11727> A_IWL<11726> A_IWL<11725> A_IWL<11724> A_IWL<11723> A_IWL<11722> A_IWL<11721> A_IWL<11720> A_IWL<11719> A_IWL<11718> A_IWL<11717> A_IWL<11716> A_IWL<11715> A_IWL<11714> A_IWL<11713> A_IWL<11712> A_IWL<11711> A_IWL<11710> A_IWL<11709> A_IWL<11708> A_IWL<11707> A_IWL<11706> A_IWL<11705> A_IWL<11704> A_IWL<11703> A_IWL<11702> A_IWL<11701> A_IWL<11700> A_IWL<11699> A_IWL<11698> A_IWL<11697> A_IWL<11696> A_IWL<11695> A_IWL<11694> A_IWL<11693> A_IWL<11692> A_IWL<11691> A_IWL<11690> A_IWL<11689> A_IWL<11688> A_IWL<11687> A_IWL<11686> A_IWL<11685> A_IWL<11684> A_IWL<11683> A_IWL<11682> A_IWL<11681> A_IWL<11680> A_IWL<11679> A_IWL<11678> A_IWL<11677> A_IWL<11676> A_IWL<11675> A_IWL<11674> A_IWL<11673> A_IWL<11672> A_IWL<11671> A_IWL<11670> A_IWL<11669> A_IWL<11668> A_IWL<11667> A_IWL<11666> A_IWL<11665> A_IWL<11664> A_IWL<11663> A_IWL<11662> A_IWL<11661> A_IWL<11660> A_IWL<11659> A_IWL<11658> A_IWL<11657> A_IWL<11656> A_IWL<11655> A_IWL<11654> A_IWL<11653> A_IWL<11652> A_IWL<11651> A_IWL<11650> A_IWL<11649> A_IWL<11648> A_IWL<11647> A_IWL<11646> A_IWL<11645> A_IWL<11644> A_IWL<11643> A_IWL<11642> A_IWL<11641> A_IWL<11640> A_IWL<11639> A_IWL<11638> A_IWL<11637> A_IWL<11636> A_IWL<11635> A_IWL<11634> A_IWL<11633> A_IWL<11632> A_IWL<11631> A_IWL<11630> A_IWL<11629> A_IWL<11628> A_IWL<11627> A_IWL<11626> A_IWL<11625> A_IWL<11624> A_IWL<11623> A_IWL<11622> A_IWL<11621> A_IWL<11620> A_IWL<11619> A_IWL<11618> A_IWL<11617> A_IWL<11616> A_IWL<11615> A_IWL<11614> A_IWL<11613> A_IWL<11612> A_IWL<11611> A_IWL<11610> A_IWL<11609> A_IWL<11608> A_IWL<11607> A_IWL<11606> A_IWL<11605> A_IWL<11604> A_IWL<11603> A_IWL<11602> A_IWL<11601> A_IWL<11600> A_IWL<11599> A_IWL<11598> A_IWL<11597> A_IWL<11596> A_IWL<11595> A_IWL<11594> A_IWL<11593> A_IWL<11592> A_IWL<11591> A_IWL<11590> A_IWL<11589> A_IWL<11588> A_IWL<11587> A_IWL<11586> A_IWL<11585> A_IWL<11584> A_IWL<11583> A_IWL<11582> A_IWL<11581> A_IWL<11580> A_IWL<11579> A_IWL<11578> A_IWL<11577> A_IWL<11576> A_IWL<11575> A_IWL<11574> A_IWL<11573> A_IWL<11572> A_IWL<11571> A_IWL<11570> A_IWL<11569> A_IWL<11568> A_IWL<11567> A_IWL<11566> A_IWL<11565> A_IWL<11564> A_IWL<11563> A_IWL<11562> A_IWL<11561> A_IWL<11560> A_IWL<11559> A_IWL<11558> A_IWL<11557> A_IWL<11556> A_IWL<11555> A_IWL<11554> A_IWL<11553> A_IWL<11552> A_IWL<11551> A_IWL<11550> A_IWL<11549> A_IWL<11548> A_IWL<11547> A_IWL<11546> A_IWL<11545> A_IWL<11544> A_IWL<11543> A_IWL<11542> A_IWL<11541> A_IWL<11540> A_IWL<11539> A_IWL<11538> A_IWL<11537> A_IWL<11536> A_IWL<11535> A_IWL<11534> A_IWL<11533> A_IWL<11532> A_IWL<11531> A_IWL<11530> A_IWL<11529> A_IWL<11528> A_IWL<11527> A_IWL<11526> A_IWL<11525> A_IWL<11524> A_IWL<11523> A_IWL<11522> A_IWL<11521> A_IWL<11520> A_IWL<11519> A_IWL<11518> A_IWL<11517> A_IWL<11516> A_IWL<11515> A_IWL<11514> A_IWL<11513> A_IWL<11512> A_IWL<11511> A_IWL<11510> A_IWL<11509> A_IWL<11508> A_IWL<11507> A_IWL<11506> A_IWL<11505> A_IWL<11504> A_IWL<11503> A_IWL<11502> A_IWL<11501> A_IWL<11500> A_IWL<11499> A_IWL<11498> A_IWL<11497> A_IWL<11496> A_IWL<11495> A_IWL<11494> A_IWL<11493> A_IWL<11492> A_IWL<11491> A_IWL<11490> A_IWL<11489> A_IWL<11488> A_IWL<11487> A_IWL<11486> A_IWL<11485> A_IWL<11484> A_IWL<11483> A_IWL<11482> A_IWL<11481> A_IWL<11480> A_IWL<11479> A_IWL<11478> A_IWL<11477> A_IWL<11476> A_IWL<11475> A_IWL<11474> A_IWL<11473> A_IWL<11472> A_IWL<11471> A_IWL<11470> A_IWL<11469> A_IWL<11468> A_IWL<11467> A_IWL<11466> A_IWL<11465> A_IWL<11464> A_IWL<11463> A_IWL<11462> A_IWL<11461> A_IWL<11460> A_IWL<11459> A_IWL<11458> A_IWL<11457> A_IWL<11456> A_IWL<11455> A_IWL<11454> A_IWL<11453> A_IWL<11452> A_IWL<11451> A_IWL<11450> A_IWL<11449> A_IWL<11448> A_IWL<11447> A_IWL<11446> A_IWL<11445> A_IWL<11444> A_IWL<11443> A_IWL<11442> A_IWL<11441> A_IWL<11440> A_IWL<11439> A_IWL<11438> A_IWL<11437> A_IWL<11436> A_IWL<11435> A_IWL<11434> A_IWL<11433> A_IWL<11432> A_IWL<11431> A_IWL<11430> A_IWL<11429> A_IWL<11428> A_IWL<11427> A_IWL<11426> A_IWL<11425> A_IWL<11424> A_IWL<11423> A_IWL<11422> A_IWL<11421> A_IWL<11420> A_IWL<11419> A_IWL<11418> A_IWL<11417> A_IWL<11416> A_IWL<11415> A_IWL<11414> A_IWL<11413> A_IWL<11412> A_IWL<11411> A_IWL<11410> A_IWL<11409> A_IWL<11408> A_IWL<11407> A_IWL<11406> A_IWL<11405> A_IWL<11404> A_IWL<11403> A_IWL<11402> A_IWL<11401> A_IWL<11400> A_IWL<11399> A_IWL<11398> A_IWL<11397> A_IWL<11396> A_IWL<11395> A_IWL<11394> A_IWL<11393> A_IWL<11392> A_IWL<11391> A_IWL<11390> A_IWL<11389> A_IWL<11388> A_IWL<11387> A_IWL<11386> A_IWL<11385> A_IWL<11384> A_IWL<11383> A_IWL<11382> A_IWL<11381> A_IWL<11380> A_IWL<11379> A_IWL<11378> A_IWL<11377> A_IWL<11376> A_IWL<11375> A_IWL<11374> A_IWL<11373> A_IWL<11372> A_IWL<11371> A_IWL<11370> A_IWL<11369> A_IWL<11368> A_IWL<11367> A_IWL<11366> A_IWL<11365> A_IWL<11364> A_IWL<11363> A_IWL<11362> A_IWL<11361> A_IWL<11360> A_IWL<11359> A_IWL<11358> A_IWL<11357> A_IWL<11356> A_IWL<11355> A_IWL<11354> A_IWL<11353> A_IWL<11352> A_IWL<11351> A_IWL<11350> A_IWL<11349> A_IWL<11348> A_IWL<11347> A_IWL<11346> A_IWL<11345> A_IWL<11344> A_IWL<11343> A_IWL<11342> A_IWL<11341> A_IWL<11340> A_IWL<11339> A_IWL<11338> A_IWL<11337> A_IWL<11336> A_IWL<11335> A_IWL<11334> A_IWL<11333> A_IWL<11332> A_IWL<11331> A_IWL<11330> A_IWL<11329> A_IWL<11328> A_IWL<11327> A_IWL<11326> A_IWL<11325> A_IWL<11324> A_IWL<11323> A_IWL<11322> A_IWL<11321> A_IWL<11320> A_IWL<11319> A_IWL<11318> A_IWL<11317> A_IWL<11316> A_IWL<11315> A_IWL<11314> A_IWL<11313> A_IWL<11312> A_IWL<11311> A_IWL<11310> A_IWL<11309> A_IWL<11308> A_IWL<11307> A_IWL<11306> A_IWL<11305> A_IWL<11304> A_IWL<11303> A_IWL<11302> A_IWL<11301> A_IWL<11300> A_IWL<11299> A_IWL<11298> A_IWL<11297> A_IWL<11296> A_IWL<11295> A_IWL<11294> A_IWL<11293> A_IWL<11292> A_IWL<11291> A_IWL<11290> A_IWL<11289> A_IWL<11288> A_IWL<11287> A_IWL<11286> A_IWL<11285> A_IWL<11284> A_IWL<11283> A_IWL<11282> A_IWL<11281> A_IWL<11280> A_IWL<11279> A_IWL<11278> A_IWL<11277> A_IWL<11276> A_IWL<11275> A_IWL<11274> A_IWL<11273> A_IWL<11272> A_IWL<11271> A_IWL<11270> A_IWL<11269> A_IWL<11268> A_IWL<11267> A_IWL<11266> A_IWL<11265> A_IWL<11264> A_IWL<12287> A_IWL<12286> A_IWL<12285> A_IWL<12284> A_IWL<12283> A_IWL<12282> A_IWL<12281> A_IWL<12280> A_IWL<12279> A_IWL<12278> A_IWL<12277> A_IWL<12276> A_IWL<12275> A_IWL<12274> A_IWL<12273> A_IWL<12272> A_IWL<12271> A_IWL<12270> A_IWL<12269> A_IWL<12268> A_IWL<12267> A_IWL<12266> A_IWL<12265> A_IWL<12264> A_IWL<12263> A_IWL<12262> A_IWL<12261> A_IWL<12260> A_IWL<12259> A_IWL<12258> A_IWL<12257> A_IWL<12256> A_IWL<12255> A_IWL<12254> A_IWL<12253> A_IWL<12252> A_IWL<12251> A_IWL<12250> A_IWL<12249> A_IWL<12248> A_IWL<12247> A_IWL<12246> A_IWL<12245> A_IWL<12244> A_IWL<12243> A_IWL<12242> A_IWL<12241> A_IWL<12240> A_IWL<12239> A_IWL<12238> A_IWL<12237> A_IWL<12236> A_IWL<12235> A_IWL<12234> A_IWL<12233> A_IWL<12232> A_IWL<12231> A_IWL<12230> A_IWL<12229> A_IWL<12228> A_IWL<12227> A_IWL<12226> A_IWL<12225> A_IWL<12224> A_IWL<12223> A_IWL<12222> A_IWL<12221> A_IWL<12220> A_IWL<12219> A_IWL<12218> A_IWL<12217> A_IWL<12216> A_IWL<12215> A_IWL<12214> A_IWL<12213> A_IWL<12212> A_IWL<12211> A_IWL<12210> A_IWL<12209> A_IWL<12208> A_IWL<12207> A_IWL<12206> A_IWL<12205> A_IWL<12204> A_IWL<12203> A_IWL<12202> A_IWL<12201> A_IWL<12200> A_IWL<12199> A_IWL<12198> A_IWL<12197> A_IWL<12196> A_IWL<12195> A_IWL<12194> A_IWL<12193> A_IWL<12192> A_IWL<12191> A_IWL<12190> A_IWL<12189> A_IWL<12188> A_IWL<12187> A_IWL<12186> A_IWL<12185> A_IWL<12184> A_IWL<12183> A_IWL<12182> A_IWL<12181> A_IWL<12180> A_IWL<12179> A_IWL<12178> A_IWL<12177> A_IWL<12176> A_IWL<12175> A_IWL<12174> A_IWL<12173> A_IWL<12172> A_IWL<12171> A_IWL<12170> A_IWL<12169> A_IWL<12168> A_IWL<12167> A_IWL<12166> A_IWL<12165> A_IWL<12164> A_IWL<12163> A_IWL<12162> A_IWL<12161> A_IWL<12160> A_IWL<12159> A_IWL<12158> A_IWL<12157> A_IWL<12156> A_IWL<12155> A_IWL<12154> A_IWL<12153> A_IWL<12152> A_IWL<12151> A_IWL<12150> A_IWL<12149> A_IWL<12148> A_IWL<12147> A_IWL<12146> A_IWL<12145> A_IWL<12144> A_IWL<12143> A_IWL<12142> A_IWL<12141> A_IWL<12140> A_IWL<12139> A_IWL<12138> A_IWL<12137> A_IWL<12136> A_IWL<12135> A_IWL<12134> A_IWL<12133> A_IWL<12132> A_IWL<12131> A_IWL<12130> A_IWL<12129> A_IWL<12128> A_IWL<12127> A_IWL<12126> A_IWL<12125> A_IWL<12124> A_IWL<12123> A_IWL<12122> A_IWL<12121> A_IWL<12120> A_IWL<12119> A_IWL<12118> A_IWL<12117> A_IWL<12116> A_IWL<12115> A_IWL<12114> A_IWL<12113> A_IWL<12112> A_IWL<12111> A_IWL<12110> A_IWL<12109> A_IWL<12108> A_IWL<12107> A_IWL<12106> A_IWL<12105> A_IWL<12104> A_IWL<12103> A_IWL<12102> A_IWL<12101> A_IWL<12100> A_IWL<12099> A_IWL<12098> A_IWL<12097> A_IWL<12096> A_IWL<12095> A_IWL<12094> A_IWL<12093> A_IWL<12092> A_IWL<12091> A_IWL<12090> A_IWL<12089> A_IWL<12088> A_IWL<12087> A_IWL<12086> A_IWL<12085> A_IWL<12084> A_IWL<12083> A_IWL<12082> A_IWL<12081> A_IWL<12080> A_IWL<12079> A_IWL<12078> A_IWL<12077> A_IWL<12076> A_IWL<12075> A_IWL<12074> A_IWL<12073> A_IWL<12072> A_IWL<12071> A_IWL<12070> A_IWL<12069> A_IWL<12068> A_IWL<12067> A_IWL<12066> A_IWL<12065> A_IWL<12064> A_IWL<12063> A_IWL<12062> A_IWL<12061> A_IWL<12060> A_IWL<12059> A_IWL<12058> A_IWL<12057> A_IWL<12056> A_IWL<12055> A_IWL<12054> A_IWL<12053> A_IWL<12052> A_IWL<12051> A_IWL<12050> A_IWL<12049> A_IWL<12048> A_IWL<12047> A_IWL<12046> A_IWL<12045> A_IWL<12044> A_IWL<12043> A_IWL<12042> A_IWL<12041> A_IWL<12040> A_IWL<12039> A_IWL<12038> A_IWL<12037> A_IWL<12036> A_IWL<12035> A_IWL<12034> A_IWL<12033> A_IWL<12032> A_IWL<12031> A_IWL<12030> A_IWL<12029> A_IWL<12028> A_IWL<12027> A_IWL<12026> A_IWL<12025> A_IWL<12024> A_IWL<12023> A_IWL<12022> A_IWL<12021> A_IWL<12020> A_IWL<12019> A_IWL<12018> A_IWL<12017> A_IWL<12016> A_IWL<12015> A_IWL<12014> A_IWL<12013> A_IWL<12012> A_IWL<12011> A_IWL<12010> A_IWL<12009> A_IWL<12008> A_IWL<12007> A_IWL<12006> A_IWL<12005> A_IWL<12004> A_IWL<12003> A_IWL<12002> A_IWL<12001> A_IWL<12000> A_IWL<11999> A_IWL<11998> A_IWL<11997> A_IWL<11996> A_IWL<11995> A_IWL<11994> A_IWL<11993> A_IWL<11992> A_IWL<11991> A_IWL<11990> A_IWL<11989> A_IWL<11988> A_IWL<11987> A_IWL<11986> A_IWL<11985> A_IWL<11984> A_IWL<11983> A_IWL<11982> A_IWL<11981> A_IWL<11980> A_IWL<11979> A_IWL<11978> A_IWL<11977> A_IWL<11976> A_IWL<11975> A_IWL<11974> A_IWL<11973> A_IWL<11972> A_IWL<11971> A_IWL<11970> A_IWL<11969> A_IWL<11968> A_IWL<11967> A_IWL<11966> A_IWL<11965> A_IWL<11964> A_IWL<11963> A_IWL<11962> A_IWL<11961> A_IWL<11960> A_IWL<11959> A_IWL<11958> A_IWL<11957> A_IWL<11956> A_IWL<11955> A_IWL<11954> A_IWL<11953> A_IWL<11952> A_IWL<11951> A_IWL<11950> A_IWL<11949> A_IWL<11948> A_IWL<11947> A_IWL<11946> A_IWL<11945> A_IWL<11944> A_IWL<11943> A_IWL<11942> A_IWL<11941> A_IWL<11940> A_IWL<11939> A_IWL<11938> A_IWL<11937> A_IWL<11936> A_IWL<11935> A_IWL<11934> A_IWL<11933> A_IWL<11932> A_IWL<11931> A_IWL<11930> A_IWL<11929> A_IWL<11928> A_IWL<11927> A_IWL<11926> A_IWL<11925> A_IWL<11924> A_IWL<11923> A_IWL<11922> A_IWL<11921> A_IWL<11920> A_IWL<11919> A_IWL<11918> A_IWL<11917> A_IWL<11916> A_IWL<11915> A_IWL<11914> A_IWL<11913> A_IWL<11912> A_IWL<11911> A_IWL<11910> A_IWL<11909> A_IWL<11908> A_IWL<11907> A_IWL<11906> A_IWL<11905> A_IWL<11904> A_IWL<11903> A_IWL<11902> A_IWL<11901> A_IWL<11900> A_IWL<11899> A_IWL<11898> A_IWL<11897> A_IWL<11896> A_IWL<11895> A_IWL<11894> A_IWL<11893> A_IWL<11892> A_IWL<11891> A_IWL<11890> A_IWL<11889> A_IWL<11888> A_IWL<11887> A_IWL<11886> A_IWL<11885> A_IWL<11884> A_IWL<11883> A_IWL<11882> A_IWL<11881> A_IWL<11880> A_IWL<11879> A_IWL<11878> A_IWL<11877> A_IWL<11876> A_IWL<11875> A_IWL<11874> A_IWL<11873> A_IWL<11872> A_IWL<11871> A_IWL<11870> A_IWL<11869> A_IWL<11868> A_IWL<11867> A_IWL<11866> A_IWL<11865> A_IWL<11864> A_IWL<11863> A_IWL<11862> A_IWL<11861> A_IWL<11860> A_IWL<11859> A_IWL<11858> A_IWL<11857> A_IWL<11856> A_IWL<11855> A_IWL<11854> A_IWL<11853> A_IWL<11852> A_IWL<11851> A_IWL<11850> A_IWL<11849> A_IWL<11848> A_IWL<11847> A_IWL<11846> A_IWL<11845> A_IWL<11844> A_IWL<11843> A_IWL<11842> A_IWL<11841> A_IWL<11840> A_IWL<11839> A_IWL<11838> A_IWL<11837> A_IWL<11836> A_IWL<11835> A_IWL<11834> A_IWL<11833> A_IWL<11832> A_IWL<11831> A_IWL<11830> A_IWL<11829> A_IWL<11828> A_IWL<11827> A_IWL<11826> A_IWL<11825> A_IWL<11824> A_IWL<11823> A_IWL<11822> A_IWL<11821> A_IWL<11820> A_IWL<11819> A_IWL<11818> A_IWL<11817> A_IWL<11816> A_IWL<11815> A_IWL<11814> A_IWL<11813> A_IWL<11812> A_IWL<11811> A_IWL<11810> A_IWL<11809> A_IWL<11808> A_IWL<11807> A_IWL<11806> A_IWL<11805> A_IWL<11804> A_IWL<11803> A_IWL<11802> A_IWL<11801> A_IWL<11800> A_IWL<11799> A_IWL<11798> A_IWL<11797> A_IWL<11796> A_IWL<11795> A_IWL<11794> A_IWL<11793> A_IWL<11792> A_IWL<11791> A_IWL<11790> A_IWL<11789> A_IWL<11788> A_IWL<11787> A_IWL<11786> A_IWL<11785> A_IWL<11784> A_IWL<11783> A_IWL<11782> A_IWL<11781> A_IWL<11780> A_IWL<11779> A_IWL<11778> A_IWL<11777> A_IWL<11776> VDD_CORE VSS / RM_IHPSG13_8192x32_c4_1P_COLUMN_pcell_0 +XCOL<22> A_BLC<45> A_BLC<44> A_BLC_TOP<45> A_BLC_TOP<44> A_BLT<45> A_BLT<44> A_BLT_TOP<45> A_BLT_TOP<44> A_IWL<11263> A_IWL<11262> A_IWL<11261> A_IWL<11260> A_IWL<11259> A_IWL<11258> A_IWL<11257> A_IWL<11256> A_IWL<11255> A_IWL<11254> A_IWL<11253> A_IWL<11252> A_IWL<11251> A_IWL<11250> A_IWL<11249> A_IWL<11248> A_IWL<11247> A_IWL<11246> A_IWL<11245> A_IWL<11244> A_IWL<11243> A_IWL<11242> A_IWL<11241> A_IWL<11240> A_IWL<11239> A_IWL<11238> A_IWL<11237> A_IWL<11236> A_IWL<11235> A_IWL<11234> A_IWL<11233> A_IWL<11232> A_IWL<11231> A_IWL<11230> A_IWL<11229> A_IWL<11228> A_IWL<11227> A_IWL<11226> A_IWL<11225> A_IWL<11224> A_IWL<11223> A_IWL<11222> A_IWL<11221> A_IWL<11220> A_IWL<11219> A_IWL<11218> A_IWL<11217> A_IWL<11216> A_IWL<11215> A_IWL<11214> A_IWL<11213> A_IWL<11212> A_IWL<11211> A_IWL<11210> A_IWL<11209> A_IWL<11208> A_IWL<11207> A_IWL<11206> A_IWL<11205> A_IWL<11204> A_IWL<11203> A_IWL<11202> A_IWL<11201> A_IWL<11200> A_IWL<11199> A_IWL<11198> A_IWL<11197> A_IWL<11196> A_IWL<11195> A_IWL<11194> A_IWL<11193> A_IWL<11192> A_IWL<11191> A_IWL<11190> A_IWL<11189> A_IWL<11188> A_IWL<11187> A_IWL<11186> A_IWL<11185> A_IWL<11184> A_IWL<11183> A_IWL<11182> A_IWL<11181> A_IWL<11180> A_IWL<11179> A_IWL<11178> A_IWL<11177> A_IWL<11176> A_IWL<11175> A_IWL<11174> A_IWL<11173> A_IWL<11172> A_IWL<11171> A_IWL<11170> A_IWL<11169> A_IWL<11168> A_IWL<11167> A_IWL<11166> A_IWL<11165> A_IWL<11164> A_IWL<11163> A_IWL<11162> A_IWL<11161> A_IWL<11160> A_IWL<11159> A_IWL<11158> A_IWL<11157> A_IWL<11156> A_IWL<11155> A_IWL<11154> A_IWL<11153> A_IWL<11152> A_IWL<11151> A_IWL<11150> A_IWL<11149> A_IWL<11148> A_IWL<11147> A_IWL<11146> A_IWL<11145> A_IWL<11144> A_IWL<11143> A_IWL<11142> A_IWL<11141> A_IWL<11140> A_IWL<11139> A_IWL<11138> A_IWL<11137> A_IWL<11136> A_IWL<11135> A_IWL<11134> A_IWL<11133> A_IWL<11132> A_IWL<11131> A_IWL<11130> A_IWL<11129> A_IWL<11128> A_IWL<11127> A_IWL<11126> A_IWL<11125> A_IWL<11124> A_IWL<11123> A_IWL<11122> A_IWL<11121> A_IWL<11120> A_IWL<11119> A_IWL<11118> A_IWL<11117> A_IWL<11116> A_IWL<11115> A_IWL<11114> A_IWL<11113> A_IWL<11112> A_IWL<11111> A_IWL<11110> A_IWL<11109> A_IWL<11108> A_IWL<11107> A_IWL<11106> A_IWL<11105> A_IWL<11104> A_IWL<11103> A_IWL<11102> A_IWL<11101> A_IWL<11100> A_IWL<11099> A_IWL<11098> A_IWL<11097> A_IWL<11096> A_IWL<11095> A_IWL<11094> A_IWL<11093> A_IWL<11092> A_IWL<11091> A_IWL<11090> A_IWL<11089> A_IWL<11088> A_IWL<11087> A_IWL<11086> A_IWL<11085> A_IWL<11084> A_IWL<11083> A_IWL<11082> A_IWL<11081> A_IWL<11080> A_IWL<11079> A_IWL<11078> A_IWL<11077> A_IWL<11076> A_IWL<11075> A_IWL<11074> A_IWL<11073> A_IWL<11072> A_IWL<11071> A_IWL<11070> A_IWL<11069> A_IWL<11068> A_IWL<11067> A_IWL<11066> A_IWL<11065> A_IWL<11064> A_IWL<11063> A_IWL<11062> A_IWL<11061> A_IWL<11060> A_IWL<11059> A_IWL<11058> A_IWL<11057> A_IWL<11056> A_IWL<11055> A_IWL<11054> A_IWL<11053> A_IWL<11052> A_IWL<11051> A_IWL<11050> A_IWL<11049> A_IWL<11048> A_IWL<11047> A_IWL<11046> A_IWL<11045> A_IWL<11044> A_IWL<11043> A_IWL<11042> A_IWL<11041> A_IWL<11040> A_IWL<11039> A_IWL<11038> A_IWL<11037> A_IWL<11036> A_IWL<11035> A_IWL<11034> A_IWL<11033> A_IWL<11032> A_IWL<11031> A_IWL<11030> A_IWL<11029> A_IWL<11028> A_IWL<11027> A_IWL<11026> A_IWL<11025> A_IWL<11024> A_IWL<11023> A_IWL<11022> A_IWL<11021> A_IWL<11020> A_IWL<11019> A_IWL<11018> A_IWL<11017> A_IWL<11016> A_IWL<11015> A_IWL<11014> A_IWL<11013> A_IWL<11012> A_IWL<11011> A_IWL<11010> A_IWL<11009> A_IWL<11008> A_IWL<11007> A_IWL<11006> A_IWL<11005> A_IWL<11004> A_IWL<11003> A_IWL<11002> A_IWL<11001> A_IWL<11000> A_IWL<10999> A_IWL<10998> A_IWL<10997> A_IWL<10996> A_IWL<10995> A_IWL<10994> A_IWL<10993> A_IWL<10992> A_IWL<10991> A_IWL<10990> A_IWL<10989> A_IWL<10988> A_IWL<10987> A_IWL<10986> A_IWL<10985> A_IWL<10984> A_IWL<10983> A_IWL<10982> A_IWL<10981> A_IWL<10980> A_IWL<10979> A_IWL<10978> A_IWL<10977> A_IWL<10976> A_IWL<10975> A_IWL<10974> A_IWL<10973> A_IWL<10972> A_IWL<10971> A_IWL<10970> A_IWL<10969> A_IWL<10968> A_IWL<10967> A_IWL<10966> A_IWL<10965> A_IWL<10964> A_IWL<10963> A_IWL<10962> A_IWL<10961> A_IWL<10960> A_IWL<10959> A_IWL<10958> A_IWL<10957> A_IWL<10956> A_IWL<10955> A_IWL<10954> A_IWL<10953> A_IWL<10952> A_IWL<10951> A_IWL<10950> A_IWL<10949> A_IWL<10948> A_IWL<10947> A_IWL<10946> A_IWL<10945> A_IWL<10944> A_IWL<10943> A_IWL<10942> A_IWL<10941> A_IWL<10940> A_IWL<10939> A_IWL<10938> A_IWL<10937> A_IWL<10936> A_IWL<10935> A_IWL<10934> A_IWL<10933> A_IWL<10932> A_IWL<10931> A_IWL<10930> A_IWL<10929> A_IWL<10928> A_IWL<10927> A_IWL<10926> A_IWL<10925> A_IWL<10924> A_IWL<10923> A_IWL<10922> A_IWL<10921> A_IWL<10920> A_IWL<10919> A_IWL<10918> A_IWL<10917> A_IWL<10916> A_IWL<10915> A_IWL<10914> A_IWL<10913> A_IWL<10912> A_IWL<10911> A_IWL<10910> A_IWL<10909> A_IWL<10908> A_IWL<10907> A_IWL<10906> A_IWL<10905> A_IWL<10904> A_IWL<10903> A_IWL<10902> A_IWL<10901> A_IWL<10900> A_IWL<10899> A_IWL<10898> A_IWL<10897> A_IWL<10896> A_IWL<10895> A_IWL<10894> A_IWL<10893> A_IWL<10892> A_IWL<10891> A_IWL<10890> A_IWL<10889> A_IWL<10888> A_IWL<10887> A_IWL<10886> A_IWL<10885> A_IWL<10884> A_IWL<10883> A_IWL<10882> A_IWL<10881> A_IWL<10880> A_IWL<10879> A_IWL<10878> A_IWL<10877> A_IWL<10876> A_IWL<10875> A_IWL<10874> A_IWL<10873> A_IWL<10872> A_IWL<10871> A_IWL<10870> A_IWL<10869> A_IWL<10868> A_IWL<10867> A_IWL<10866> A_IWL<10865> A_IWL<10864> A_IWL<10863> A_IWL<10862> A_IWL<10861> A_IWL<10860> A_IWL<10859> A_IWL<10858> A_IWL<10857> A_IWL<10856> A_IWL<10855> A_IWL<10854> A_IWL<10853> A_IWL<10852> A_IWL<10851> A_IWL<10850> A_IWL<10849> A_IWL<10848> A_IWL<10847> A_IWL<10846> A_IWL<10845> A_IWL<10844> A_IWL<10843> A_IWL<10842> A_IWL<10841> A_IWL<10840> A_IWL<10839> A_IWL<10838> A_IWL<10837> A_IWL<10836> A_IWL<10835> A_IWL<10834> A_IWL<10833> A_IWL<10832> A_IWL<10831> A_IWL<10830> A_IWL<10829> A_IWL<10828> A_IWL<10827> A_IWL<10826> A_IWL<10825> A_IWL<10824> A_IWL<10823> A_IWL<10822> A_IWL<10821> A_IWL<10820> A_IWL<10819> A_IWL<10818> A_IWL<10817> A_IWL<10816> A_IWL<10815> A_IWL<10814> A_IWL<10813> A_IWL<10812> A_IWL<10811> A_IWL<10810> A_IWL<10809> A_IWL<10808> A_IWL<10807> A_IWL<10806> A_IWL<10805> A_IWL<10804> A_IWL<10803> A_IWL<10802> A_IWL<10801> A_IWL<10800> A_IWL<10799> A_IWL<10798> A_IWL<10797> A_IWL<10796> A_IWL<10795> A_IWL<10794> A_IWL<10793> A_IWL<10792> A_IWL<10791> A_IWL<10790> A_IWL<10789> A_IWL<10788> A_IWL<10787> A_IWL<10786> A_IWL<10785> A_IWL<10784> A_IWL<10783> A_IWL<10782> A_IWL<10781> A_IWL<10780> A_IWL<10779> A_IWL<10778> A_IWL<10777> A_IWL<10776> A_IWL<10775> A_IWL<10774> A_IWL<10773> A_IWL<10772> A_IWL<10771> A_IWL<10770> A_IWL<10769> A_IWL<10768> A_IWL<10767> A_IWL<10766> A_IWL<10765> A_IWL<10764> A_IWL<10763> A_IWL<10762> A_IWL<10761> A_IWL<10760> A_IWL<10759> A_IWL<10758> A_IWL<10757> A_IWL<10756> A_IWL<10755> A_IWL<10754> A_IWL<10753> A_IWL<10752> A_IWL<11775> A_IWL<11774> A_IWL<11773> A_IWL<11772> A_IWL<11771> A_IWL<11770> A_IWL<11769> A_IWL<11768> A_IWL<11767> A_IWL<11766> A_IWL<11765> A_IWL<11764> A_IWL<11763> A_IWL<11762> A_IWL<11761> A_IWL<11760> A_IWL<11759> A_IWL<11758> A_IWL<11757> A_IWL<11756> A_IWL<11755> A_IWL<11754> A_IWL<11753> A_IWL<11752> A_IWL<11751> A_IWL<11750> A_IWL<11749> A_IWL<11748> A_IWL<11747> A_IWL<11746> A_IWL<11745> A_IWL<11744> A_IWL<11743> A_IWL<11742> A_IWL<11741> A_IWL<11740> A_IWL<11739> A_IWL<11738> A_IWL<11737> A_IWL<11736> A_IWL<11735> A_IWL<11734> A_IWL<11733> A_IWL<11732> A_IWL<11731> A_IWL<11730> A_IWL<11729> A_IWL<11728> A_IWL<11727> A_IWL<11726> A_IWL<11725> A_IWL<11724> A_IWL<11723> A_IWL<11722> A_IWL<11721> A_IWL<11720> A_IWL<11719> A_IWL<11718> A_IWL<11717> A_IWL<11716> A_IWL<11715> A_IWL<11714> A_IWL<11713> A_IWL<11712> A_IWL<11711> A_IWL<11710> A_IWL<11709> A_IWL<11708> A_IWL<11707> A_IWL<11706> A_IWL<11705> A_IWL<11704> A_IWL<11703> A_IWL<11702> A_IWL<11701> A_IWL<11700> A_IWL<11699> A_IWL<11698> A_IWL<11697> A_IWL<11696> A_IWL<11695> A_IWL<11694> A_IWL<11693> A_IWL<11692> A_IWL<11691> A_IWL<11690> A_IWL<11689> A_IWL<11688> A_IWL<11687> A_IWL<11686> A_IWL<11685> A_IWL<11684> A_IWL<11683> A_IWL<11682> A_IWL<11681> A_IWL<11680> A_IWL<11679> A_IWL<11678> A_IWL<11677> A_IWL<11676> A_IWL<11675> A_IWL<11674> A_IWL<11673> A_IWL<11672> A_IWL<11671> A_IWL<11670> A_IWL<11669> A_IWL<11668> A_IWL<11667> A_IWL<11666> A_IWL<11665> A_IWL<11664> A_IWL<11663> A_IWL<11662> A_IWL<11661> A_IWL<11660> A_IWL<11659> A_IWL<11658> A_IWL<11657> A_IWL<11656> A_IWL<11655> A_IWL<11654> A_IWL<11653> A_IWL<11652> A_IWL<11651> A_IWL<11650> A_IWL<11649> A_IWL<11648> A_IWL<11647> A_IWL<11646> A_IWL<11645> A_IWL<11644> A_IWL<11643> A_IWL<11642> A_IWL<11641> A_IWL<11640> A_IWL<11639> A_IWL<11638> A_IWL<11637> A_IWL<11636> A_IWL<11635> A_IWL<11634> A_IWL<11633> A_IWL<11632> A_IWL<11631> A_IWL<11630> A_IWL<11629> A_IWL<11628> A_IWL<11627> A_IWL<11626> A_IWL<11625> A_IWL<11624> A_IWL<11623> A_IWL<11622> A_IWL<11621> A_IWL<11620> A_IWL<11619> A_IWL<11618> A_IWL<11617> A_IWL<11616> A_IWL<11615> A_IWL<11614> A_IWL<11613> A_IWL<11612> A_IWL<11611> A_IWL<11610> A_IWL<11609> A_IWL<11608> A_IWL<11607> A_IWL<11606> A_IWL<11605> A_IWL<11604> A_IWL<11603> A_IWL<11602> A_IWL<11601> A_IWL<11600> A_IWL<11599> A_IWL<11598> A_IWL<11597> A_IWL<11596> A_IWL<11595> A_IWL<11594> A_IWL<11593> A_IWL<11592> A_IWL<11591> A_IWL<11590> A_IWL<11589> A_IWL<11588> A_IWL<11587> A_IWL<11586> A_IWL<11585> A_IWL<11584> A_IWL<11583> A_IWL<11582> A_IWL<11581> A_IWL<11580> A_IWL<11579> A_IWL<11578> A_IWL<11577> A_IWL<11576> A_IWL<11575> A_IWL<11574> A_IWL<11573> A_IWL<11572> A_IWL<11571> A_IWL<11570> A_IWL<11569> A_IWL<11568> A_IWL<11567> A_IWL<11566> A_IWL<11565> A_IWL<11564> A_IWL<11563> A_IWL<11562> A_IWL<11561> A_IWL<11560> A_IWL<11559> A_IWL<11558> A_IWL<11557> A_IWL<11556> A_IWL<11555> A_IWL<11554> A_IWL<11553> A_IWL<11552> A_IWL<11551> A_IWL<11550> A_IWL<11549> A_IWL<11548> A_IWL<11547> A_IWL<11546> A_IWL<11545> A_IWL<11544> A_IWL<11543> A_IWL<11542> A_IWL<11541> A_IWL<11540> A_IWL<11539> A_IWL<11538> A_IWL<11537> A_IWL<11536> A_IWL<11535> A_IWL<11534> A_IWL<11533> A_IWL<11532> A_IWL<11531> A_IWL<11530> A_IWL<11529> A_IWL<11528> A_IWL<11527> A_IWL<11526> A_IWL<11525> A_IWL<11524> A_IWL<11523> A_IWL<11522> A_IWL<11521> A_IWL<11520> A_IWL<11519> A_IWL<11518> A_IWL<11517> A_IWL<11516> A_IWL<11515> A_IWL<11514> A_IWL<11513> A_IWL<11512> A_IWL<11511> A_IWL<11510> A_IWL<11509> A_IWL<11508> A_IWL<11507> A_IWL<11506> A_IWL<11505> A_IWL<11504> A_IWL<11503> A_IWL<11502> A_IWL<11501> A_IWL<11500> A_IWL<11499> A_IWL<11498> A_IWL<11497> A_IWL<11496> A_IWL<11495> A_IWL<11494> A_IWL<11493> A_IWL<11492> A_IWL<11491> A_IWL<11490> A_IWL<11489> A_IWL<11488> A_IWL<11487> A_IWL<11486> A_IWL<11485> A_IWL<11484> A_IWL<11483> A_IWL<11482> A_IWL<11481> A_IWL<11480> A_IWL<11479> A_IWL<11478> A_IWL<11477> A_IWL<11476> A_IWL<11475> A_IWL<11474> A_IWL<11473> A_IWL<11472> A_IWL<11471> A_IWL<11470> A_IWL<11469> A_IWL<11468> A_IWL<11467> A_IWL<11466> A_IWL<11465> A_IWL<11464> A_IWL<11463> A_IWL<11462> A_IWL<11461> A_IWL<11460> A_IWL<11459> A_IWL<11458> A_IWL<11457> A_IWL<11456> A_IWL<11455> A_IWL<11454> A_IWL<11453> A_IWL<11452> A_IWL<11451> A_IWL<11450> A_IWL<11449> A_IWL<11448> A_IWL<11447> A_IWL<11446> A_IWL<11445> A_IWL<11444> A_IWL<11443> A_IWL<11442> A_IWL<11441> A_IWL<11440> A_IWL<11439> A_IWL<11438> A_IWL<11437> A_IWL<11436> A_IWL<11435> A_IWL<11434> A_IWL<11433> A_IWL<11432> A_IWL<11431> A_IWL<11430> A_IWL<11429> A_IWL<11428> A_IWL<11427> A_IWL<11426> A_IWL<11425> A_IWL<11424> A_IWL<11423> A_IWL<11422> A_IWL<11421> A_IWL<11420> A_IWL<11419> A_IWL<11418> A_IWL<11417> A_IWL<11416> A_IWL<11415> A_IWL<11414> A_IWL<11413> A_IWL<11412> A_IWL<11411> A_IWL<11410> A_IWL<11409> A_IWL<11408> A_IWL<11407> A_IWL<11406> A_IWL<11405> A_IWL<11404> A_IWL<11403> A_IWL<11402> A_IWL<11401> A_IWL<11400> A_IWL<11399> A_IWL<11398> A_IWL<11397> A_IWL<11396> A_IWL<11395> A_IWL<11394> A_IWL<11393> A_IWL<11392> A_IWL<11391> A_IWL<11390> A_IWL<11389> A_IWL<11388> A_IWL<11387> A_IWL<11386> A_IWL<11385> A_IWL<11384> A_IWL<11383> A_IWL<11382> A_IWL<11381> A_IWL<11380> A_IWL<11379> A_IWL<11378> A_IWL<11377> A_IWL<11376> A_IWL<11375> A_IWL<11374> A_IWL<11373> A_IWL<11372> A_IWL<11371> A_IWL<11370> A_IWL<11369> A_IWL<11368> A_IWL<11367> A_IWL<11366> A_IWL<11365> A_IWL<11364> A_IWL<11363> A_IWL<11362> A_IWL<11361> A_IWL<11360> A_IWL<11359> A_IWL<11358> A_IWL<11357> A_IWL<11356> A_IWL<11355> A_IWL<11354> A_IWL<11353> A_IWL<11352> A_IWL<11351> A_IWL<11350> A_IWL<11349> A_IWL<11348> A_IWL<11347> A_IWL<11346> A_IWL<11345> A_IWL<11344> A_IWL<11343> A_IWL<11342> A_IWL<11341> A_IWL<11340> A_IWL<11339> A_IWL<11338> A_IWL<11337> A_IWL<11336> A_IWL<11335> A_IWL<11334> A_IWL<11333> A_IWL<11332> A_IWL<11331> A_IWL<11330> A_IWL<11329> A_IWL<11328> A_IWL<11327> A_IWL<11326> A_IWL<11325> A_IWL<11324> A_IWL<11323> A_IWL<11322> A_IWL<11321> A_IWL<11320> A_IWL<11319> A_IWL<11318> A_IWL<11317> A_IWL<11316> A_IWL<11315> A_IWL<11314> A_IWL<11313> A_IWL<11312> A_IWL<11311> A_IWL<11310> A_IWL<11309> A_IWL<11308> A_IWL<11307> A_IWL<11306> A_IWL<11305> A_IWL<11304> A_IWL<11303> A_IWL<11302> A_IWL<11301> A_IWL<11300> A_IWL<11299> A_IWL<11298> A_IWL<11297> A_IWL<11296> A_IWL<11295> A_IWL<11294> A_IWL<11293> A_IWL<11292> A_IWL<11291> A_IWL<11290> A_IWL<11289> A_IWL<11288> A_IWL<11287> A_IWL<11286> A_IWL<11285> A_IWL<11284> A_IWL<11283> A_IWL<11282> A_IWL<11281> A_IWL<11280> A_IWL<11279> A_IWL<11278> A_IWL<11277> A_IWL<11276> A_IWL<11275> A_IWL<11274> A_IWL<11273> A_IWL<11272> A_IWL<11271> A_IWL<11270> A_IWL<11269> A_IWL<11268> A_IWL<11267> A_IWL<11266> A_IWL<11265> A_IWL<11264> VDD_CORE VSS / RM_IHPSG13_8192x32_c4_1P_COLUMN_pcell_0 +XCOL<21> A_BLC<43> A_BLC<42> A_BLC_TOP<43> A_BLC_TOP<42> A_BLT<43> A_BLT<42> A_BLT_TOP<43> A_BLT_TOP<42> A_IWL<10751> A_IWL<10750> A_IWL<10749> A_IWL<10748> A_IWL<10747> A_IWL<10746> A_IWL<10745> A_IWL<10744> A_IWL<10743> A_IWL<10742> A_IWL<10741> A_IWL<10740> A_IWL<10739> A_IWL<10738> A_IWL<10737> A_IWL<10736> A_IWL<10735> A_IWL<10734> A_IWL<10733> A_IWL<10732> A_IWL<10731> A_IWL<10730> A_IWL<10729> A_IWL<10728> A_IWL<10727> A_IWL<10726> A_IWL<10725> A_IWL<10724> A_IWL<10723> A_IWL<10722> A_IWL<10721> A_IWL<10720> A_IWL<10719> A_IWL<10718> A_IWL<10717> A_IWL<10716> A_IWL<10715> A_IWL<10714> A_IWL<10713> A_IWL<10712> A_IWL<10711> A_IWL<10710> A_IWL<10709> A_IWL<10708> A_IWL<10707> A_IWL<10706> A_IWL<10705> A_IWL<10704> A_IWL<10703> A_IWL<10702> A_IWL<10701> A_IWL<10700> A_IWL<10699> A_IWL<10698> A_IWL<10697> A_IWL<10696> A_IWL<10695> A_IWL<10694> A_IWL<10693> A_IWL<10692> A_IWL<10691> A_IWL<10690> A_IWL<10689> A_IWL<10688> A_IWL<10687> A_IWL<10686> A_IWL<10685> A_IWL<10684> A_IWL<10683> A_IWL<10682> A_IWL<10681> A_IWL<10680> A_IWL<10679> A_IWL<10678> A_IWL<10677> A_IWL<10676> A_IWL<10675> A_IWL<10674> A_IWL<10673> A_IWL<10672> A_IWL<10671> A_IWL<10670> A_IWL<10669> A_IWL<10668> A_IWL<10667> A_IWL<10666> A_IWL<10665> A_IWL<10664> A_IWL<10663> A_IWL<10662> A_IWL<10661> A_IWL<10660> A_IWL<10659> A_IWL<10658> A_IWL<10657> A_IWL<10656> A_IWL<10655> A_IWL<10654> A_IWL<10653> A_IWL<10652> A_IWL<10651> A_IWL<10650> A_IWL<10649> A_IWL<10648> A_IWL<10647> A_IWL<10646> A_IWL<10645> A_IWL<10644> A_IWL<10643> A_IWL<10642> A_IWL<10641> A_IWL<10640> A_IWL<10639> A_IWL<10638> A_IWL<10637> A_IWL<10636> A_IWL<10635> A_IWL<10634> A_IWL<10633> A_IWL<10632> A_IWL<10631> A_IWL<10630> A_IWL<10629> A_IWL<10628> A_IWL<10627> A_IWL<10626> A_IWL<10625> A_IWL<10624> A_IWL<10623> A_IWL<10622> A_IWL<10621> A_IWL<10620> A_IWL<10619> A_IWL<10618> A_IWL<10617> A_IWL<10616> A_IWL<10615> A_IWL<10614> A_IWL<10613> A_IWL<10612> A_IWL<10611> A_IWL<10610> A_IWL<10609> A_IWL<10608> A_IWL<10607> A_IWL<10606> A_IWL<10605> A_IWL<10604> A_IWL<10603> A_IWL<10602> A_IWL<10601> A_IWL<10600> A_IWL<10599> A_IWL<10598> A_IWL<10597> A_IWL<10596> A_IWL<10595> A_IWL<10594> A_IWL<10593> A_IWL<10592> A_IWL<10591> A_IWL<10590> A_IWL<10589> A_IWL<10588> A_IWL<10587> A_IWL<10586> A_IWL<10585> A_IWL<10584> A_IWL<10583> A_IWL<10582> A_IWL<10581> A_IWL<10580> A_IWL<10579> A_IWL<10578> A_IWL<10577> A_IWL<10576> A_IWL<10575> A_IWL<10574> A_IWL<10573> A_IWL<10572> A_IWL<10571> A_IWL<10570> A_IWL<10569> A_IWL<10568> A_IWL<10567> A_IWL<10566> A_IWL<10565> A_IWL<10564> A_IWL<10563> A_IWL<10562> A_IWL<10561> A_IWL<10560> A_IWL<10559> A_IWL<10558> A_IWL<10557> A_IWL<10556> A_IWL<10555> A_IWL<10554> A_IWL<10553> A_IWL<10552> A_IWL<10551> A_IWL<10550> A_IWL<10549> A_IWL<10548> A_IWL<10547> A_IWL<10546> A_IWL<10545> A_IWL<10544> A_IWL<10543> A_IWL<10542> A_IWL<10541> A_IWL<10540> A_IWL<10539> A_IWL<10538> A_IWL<10537> A_IWL<10536> A_IWL<10535> A_IWL<10534> A_IWL<10533> A_IWL<10532> A_IWL<10531> A_IWL<10530> A_IWL<10529> A_IWL<10528> A_IWL<10527> A_IWL<10526> A_IWL<10525> A_IWL<10524> A_IWL<10523> A_IWL<10522> A_IWL<10521> A_IWL<10520> A_IWL<10519> A_IWL<10518> A_IWL<10517> A_IWL<10516> A_IWL<10515> A_IWL<10514> A_IWL<10513> A_IWL<10512> A_IWL<10511> A_IWL<10510> A_IWL<10509> A_IWL<10508> A_IWL<10507> A_IWL<10506> A_IWL<10505> A_IWL<10504> A_IWL<10503> A_IWL<10502> A_IWL<10501> A_IWL<10500> A_IWL<10499> A_IWL<10498> A_IWL<10497> A_IWL<10496> A_IWL<10495> A_IWL<10494> A_IWL<10493> A_IWL<10492> A_IWL<10491> A_IWL<10490> A_IWL<10489> A_IWL<10488> A_IWL<10487> A_IWL<10486> A_IWL<10485> A_IWL<10484> A_IWL<10483> A_IWL<10482> A_IWL<10481> A_IWL<10480> A_IWL<10479> A_IWL<10478> A_IWL<10477> A_IWL<10476> A_IWL<10475> A_IWL<10474> A_IWL<10473> A_IWL<10472> A_IWL<10471> A_IWL<10470> A_IWL<10469> A_IWL<10468> A_IWL<10467> A_IWL<10466> A_IWL<10465> A_IWL<10464> A_IWL<10463> A_IWL<10462> A_IWL<10461> A_IWL<10460> A_IWL<10459> A_IWL<10458> A_IWL<10457> A_IWL<10456> A_IWL<10455> A_IWL<10454> A_IWL<10453> A_IWL<10452> A_IWL<10451> A_IWL<10450> A_IWL<10449> A_IWL<10448> A_IWL<10447> A_IWL<10446> A_IWL<10445> A_IWL<10444> A_IWL<10443> A_IWL<10442> A_IWL<10441> A_IWL<10440> A_IWL<10439> A_IWL<10438> A_IWL<10437> A_IWL<10436> A_IWL<10435> A_IWL<10434> A_IWL<10433> A_IWL<10432> A_IWL<10431> A_IWL<10430> A_IWL<10429> A_IWL<10428> A_IWL<10427> A_IWL<10426> A_IWL<10425> A_IWL<10424> A_IWL<10423> A_IWL<10422> A_IWL<10421> A_IWL<10420> A_IWL<10419> A_IWL<10418> A_IWL<10417> A_IWL<10416> A_IWL<10415> A_IWL<10414> A_IWL<10413> A_IWL<10412> A_IWL<10411> A_IWL<10410> A_IWL<10409> A_IWL<10408> A_IWL<10407> A_IWL<10406> A_IWL<10405> A_IWL<10404> A_IWL<10403> A_IWL<10402> A_IWL<10401> A_IWL<10400> A_IWL<10399> A_IWL<10398> A_IWL<10397> A_IWL<10396> A_IWL<10395> A_IWL<10394> A_IWL<10393> A_IWL<10392> A_IWL<10391> A_IWL<10390> A_IWL<10389> A_IWL<10388> A_IWL<10387> A_IWL<10386> A_IWL<10385> A_IWL<10384> A_IWL<10383> A_IWL<10382> A_IWL<10381> A_IWL<10380> A_IWL<10379> A_IWL<10378> A_IWL<10377> A_IWL<10376> A_IWL<10375> A_IWL<10374> A_IWL<10373> A_IWL<10372> A_IWL<10371> A_IWL<10370> A_IWL<10369> A_IWL<10368> A_IWL<10367> A_IWL<10366> A_IWL<10365> A_IWL<10364> A_IWL<10363> A_IWL<10362> A_IWL<10361> A_IWL<10360> A_IWL<10359> A_IWL<10358> A_IWL<10357> A_IWL<10356> A_IWL<10355> A_IWL<10354> A_IWL<10353> A_IWL<10352> A_IWL<10351> A_IWL<10350> A_IWL<10349> A_IWL<10348> A_IWL<10347> A_IWL<10346> A_IWL<10345> A_IWL<10344> A_IWL<10343> A_IWL<10342> A_IWL<10341> A_IWL<10340> A_IWL<10339> A_IWL<10338> A_IWL<10337> A_IWL<10336> A_IWL<10335> A_IWL<10334> A_IWL<10333> A_IWL<10332> A_IWL<10331> A_IWL<10330> A_IWL<10329> A_IWL<10328> A_IWL<10327> A_IWL<10326> A_IWL<10325> A_IWL<10324> A_IWL<10323> A_IWL<10322> A_IWL<10321> A_IWL<10320> A_IWL<10319> A_IWL<10318> A_IWL<10317> A_IWL<10316> A_IWL<10315> A_IWL<10314> A_IWL<10313> A_IWL<10312> A_IWL<10311> A_IWL<10310> A_IWL<10309> A_IWL<10308> A_IWL<10307> A_IWL<10306> A_IWL<10305> A_IWL<10304> A_IWL<10303> A_IWL<10302> A_IWL<10301> A_IWL<10300> A_IWL<10299> A_IWL<10298> A_IWL<10297> A_IWL<10296> A_IWL<10295> A_IWL<10294> A_IWL<10293> A_IWL<10292> A_IWL<10291> A_IWL<10290> A_IWL<10289> A_IWL<10288> A_IWL<10287> A_IWL<10286> A_IWL<10285> A_IWL<10284> A_IWL<10283> A_IWL<10282> A_IWL<10281> A_IWL<10280> A_IWL<10279> A_IWL<10278> A_IWL<10277> A_IWL<10276> A_IWL<10275> A_IWL<10274> A_IWL<10273> A_IWL<10272> A_IWL<10271> A_IWL<10270> A_IWL<10269> A_IWL<10268> A_IWL<10267> A_IWL<10266> A_IWL<10265> A_IWL<10264> A_IWL<10263> A_IWL<10262> A_IWL<10261> A_IWL<10260> A_IWL<10259> A_IWL<10258> A_IWL<10257> A_IWL<10256> A_IWL<10255> A_IWL<10254> A_IWL<10253> A_IWL<10252> A_IWL<10251> A_IWL<10250> A_IWL<10249> A_IWL<10248> A_IWL<10247> A_IWL<10246> A_IWL<10245> A_IWL<10244> A_IWL<10243> A_IWL<10242> A_IWL<10241> A_IWL<10240> A_IWL<11263> A_IWL<11262> A_IWL<11261> A_IWL<11260> A_IWL<11259> A_IWL<11258> A_IWL<11257> A_IWL<11256> A_IWL<11255> A_IWL<11254> A_IWL<11253> A_IWL<11252> A_IWL<11251> A_IWL<11250> A_IWL<11249> A_IWL<11248> A_IWL<11247> A_IWL<11246> A_IWL<11245> A_IWL<11244> A_IWL<11243> A_IWL<11242> A_IWL<11241> A_IWL<11240> A_IWL<11239> A_IWL<11238> A_IWL<11237> A_IWL<11236> A_IWL<11235> A_IWL<11234> A_IWL<11233> A_IWL<11232> A_IWL<11231> A_IWL<11230> A_IWL<11229> A_IWL<11228> A_IWL<11227> A_IWL<11226> A_IWL<11225> A_IWL<11224> A_IWL<11223> A_IWL<11222> A_IWL<11221> A_IWL<11220> A_IWL<11219> A_IWL<11218> A_IWL<11217> A_IWL<11216> A_IWL<11215> A_IWL<11214> A_IWL<11213> A_IWL<11212> A_IWL<11211> A_IWL<11210> A_IWL<11209> A_IWL<11208> A_IWL<11207> A_IWL<11206> A_IWL<11205> A_IWL<11204> A_IWL<11203> A_IWL<11202> A_IWL<11201> A_IWL<11200> A_IWL<11199> A_IWL<11198> A_IWL<11197> A_IWL<11196> A_IWL<11195> A_IWL<11194> A_IWL<11193> A_IWL<11192> A_IWL<11191> A_IWL<11190> A_IWL<11189> A_IWL<11188> A_IWL<11187> A_IWL<11186> A_IWL<11185> A_IWL<11184> A_IWL<11183> A_IWL<11182> A_IWL<11181> A_IWL<11180> A_IWL<11179> A_IWL<11178> A_IWL<11177> A_IWL<11176> A_IWL<11175> A_IWL<11174> A_IWL<11173> A_IWL<11172> A_IWL<11171> A_IWL<11170> A_IWL<11169> A_IWL<11168> A_IWL<11167> A_IWL<11166> A_IWL<11165> A_IWL<11164> A_IWL<11163> A_IWL<11162> A_IWL<11161> A_IWL<11160> A_IWL<11159> A_IWL<11158> A_IWL<11157> A_IWL<11156> A_IWL<11155> A_IWL<11154> A_IWL<11153> A_IWL<11152> A_IWL<11151> A_IWL<11150> A_IWL<11149> A_IWL<11148> A_IWL<11147> A_IWL<11146> A_IWL<11145> A_IWL<11144> A_IWL<11143> A_IWL<11142> A_IWL<11141> A_IWL<11140> A_IWL<11139> A_IWL<11138> A_IWL<11137> A_IWL<11136> A_IWL<11135> A_IWL<11134> A_IWL<11133> A_IWL<11132> A_IWL<11131> A_IWL<11130> A_IWL<11129> A_IWL<11128> A_IWL<11127> A_IWL<11126> A_IWL<11125> A_IWL<11124> A_IWL<11123> A_IWL<11122> A_IWL<11121> A_IWL<11120> A_IWL<11119> A_IWL<11118> A_IWL<11117> A_IWL<11116> A_IWL<11115> A_IWL<11114> A_IWL<11113> A_IWL<11112> A_IWL<11111> A_IWL<11110> A_IWL<11109> A_IWL<11108> A_IWL<11107> A_IWL<11106> A_IWL<11105> A_IWL<11104> A_IWL<11103> A_IWL<11102> A_IWL<11101> A_IWL<11100> A_IWL<11099> A_IWL<11098> A_IWL<11097> A_IWL<11096> A_IWL<11095> A_IWL<11094> A_IWL<11093> A_IWL<11092> A_IWL<11091> A_IWL<11090> A_IWL<11089> A_IWL<11088> A_IWL<11087> A_IWL<11086> A_IWL<11085> A_IWL<11084> A_IWL<11083> A_IWL<11082> A_IWL<11081> A_IWL<11080> A_IWL<11079> A_IWL<11078> A_IWL<11077> A_IWL<11076> A_IWL<11075> A_IWL<11074> A_IWL<11073> A_IWL<11072> A_IWL<11071> A_IWL<11070> A_IWL<11069> A_IWL<11068> A_IWL<11067> A_IWL<11066> A_IWL<11065> A_IWL<11064> A_IWL<11063> A_IWL<11062> A_IWL<11061> A_IWL<11060> A_IWL<11059> A_IWL<11058> A_IWL<11057> A_IWL<11056> A_IWL<11055> A_IWL<11054> A_IWL<11053> A_IWL<11052> A_IWL<11051> A_IWL<11050> A_IWL<11049> A_IWL<11048> A_IWL<11047> A_IWL<11046> A_IWL<11045> A_IWL<11044> A_IWL<11043> A_IWL<11042> A_IWL<11041> A_IWL<11040> A_IWL<11039> A_IWL<11038> A_IWL<11037> A_IWL<11036> A_IWL<11035> A_IWL<11034> A_IWL<11033> A_IWL<11032> A_IWL<11031> A_IWL<11030> A_IWL<11029> A_IWL<11028> A_IWL<11027> A_IWL<11026> A_IWL<11025> A_IWL<11024> A_IWL<11023> A_IWL<11022> A_IWL<11021> A_IWL<11020> A_IWL<11019> A_IWL<11018> A_IWL<11017> A_IWL<11016> A_IWL<11015> A_IWL<11014> A_IWL<11013> A_IWL<11012> A_IWL<11011> A_IWL<11010> A_IWL<11009> A_IWL<11008> A_IWL<11007> A_IWL<11006> A_IWL<11005> A_IWL<11004> A_IWL<11003> A_IWL<11002> A_IWL<11001> A_IWL<11000> A_IWL<10999> A_IWL<10998> A_IWL<10997> A_IWL<10996> A_IWL<10995> A_IWL<10994> A_IWL<10993> A_IWL<10992> A_IWL<10991> A_IWL<10990> A_IWL<10989> A_IWL<10988> A_IWL<10987> A_IWL<10986> A_IWL<10985> A_IWL<10984> A_IWL<10983> A_IWL<10982> A_IWL<10981> A_IWL<10980> A_IWL<10979> A_IWL<10978> A_IWL<10977> A_IWL<10976> A_IWL<10975> A_IWL<10974> A_IWL<10973> A_IWL<10972> A_IWL<10971> A_IWL<10970> A_IWL<10969> A_IWL<10968> A_IWL<10967> A_IWL<10966> A_IWL<10965> A_IWL<10964> A_IWL<10963> A_IWL<10962> A_IWL<10961> A_IWL<10960> A_IWL<10959> A_IWL<10958> A_IWL<10957> A_IWL<10956> A_IWL<10955> A_IWL<10954> A_IWL<10953> A_IWL<10952> A_IWL<10951> A_IWL<10950> A_IWL<10949> A_IWL<10948> A_IWL<10947> A_IWL<10946> A_IWL<10945> A_IWL<10944> A_IWL<10943> A_IWL<10942> A_IWL<10941> A_IWL<10940> A_IWL<10939> A_IWL<10938> A_IWL<10937> A_IWL<10936> A_IWL<10935> A_IWL<10934> A_IWL<10933> A_IWL<10932> A_IWL<10931> A_IWL<10930> A_IWL<10929> A_IWL<10928> A_IWL<10927> A_IWL<10926> A_IWL<10925> A_IWL<10924> A_IWL<10923> A_IWL<10922> A_IWL<10921> A_IWL<10920> A_IWL<10919> A_IWL<10918> A_IWL<10917> A_IWL<10916> A_IWL<10915> A_IWL<10914> A_IWL<10913> A_IWL<10912> A_IWL<10911> A_IWL<10910> A_IWL<10909> A_IWL<10908> A_IWL<10907> A_IWL<10906> A_IWL<10905> A_IWL<10904> A_IWL<10903> A_IWL<10902> A_IWL<10901> A_IWL<10900> A_IWL<10899> A_IWL<10898> A_IWL<10897> A_IWL<10896> A_IWL<10895> A_IWL<10894> A_IWL<10893> A_IWL<10892> A_IWL<10891> A_IWL<10890> A_IWL<10889> A_IWL<10888> A_IWL<10887> A_IWL<10886> A_IWL<10885> A_IWL<10884> A_IWL<10883> A_IWL<10882> A_IWL<10881> A_IWL<10880> A_IWL<10879> A_IWL<10878> A_IWL<10877> A_IWL<10876> A_IWL<10875> A_IWL<10874> A_IWL<10873> A_IWL<10872> A_IWL<10871> A_IWL<10870> A_IWL<10869> A_IWL<10868> A_IWL<10867> A_IWL<10866> A_IWL<10865> A_IWL<10864> A_IWL<10863> A_IWL<10862> A_IWL<10861> A_IWL<10860> A_IWL<10859> A_IWL<10858> A_IWL<10857> A_IWL<10856> A_IWL<10855> A_IWL<10854> A_IWL<10853> A_IWL<10852> A_IWL<10851> A_IWL<10850> A_IWL<10849> A_IWL<10848> A_IWL<10847> A_IWL<10846> A_IWL<10845> A_IWL<10844> A_IWL<10843> A_IWL<10842> A_IWL<10841> A_IWL<10840> A_IWL<10839> A_IWL<10838> A_IWL<10837> A_IWL<10836> A_IWL<10835> A_IWL<10834> A_IWL<10833> A_IWL<10832> A_IWL<10831> A_IWL<10830> A_IWL<10829> A_IWL<10828> A_IWL<10827> A_IWL<10826> A_IWL<10825> A_IWL<10824> A_IWL<10823> A_IWL<10822> A_IWL<10821> A_IWL<10820> A_IWL<10819> A_IWL<10818> A_IWL<10817> A_IWL<10816> A_IWL<10815> A_IWL<10814> A_IWL<10813> A_IWL<10812> A_IWL<10811> A_IWL<10810> A_IWL<10809> A_IWL<10808> A_IWL<10807> A_IWL<10806> A_IWL<10805> A_IWL<10804> A_IWL<10803> A_IWL<10802> A_IWL<10801> A_IWL<10800> A_IWL<10799> A_IWL<10798> A_IWL<10797> A_IWL<10796> A_IWL<10795> A_IWL<10794> A_IWL<10793> A_IWL<10792> A_IWL<10791> A_IWL<10790> A_IWL<10789> A_IWL<10788> A_IWL<10787> A_IWL<10786> A_IWL<10785> A_IWL<10784> A_IWL<10783> A_IWL<10782> A_IWL<10781> A_IWL<10780> A_IWL<10779> A_IWL<10778> A_IWL<10777> A_IWL<10776> A_IWL<10775> A_IWL<10774> A_IWL<10773> A_IWL<10772> A_IWL<10771> A_IWL<10770> A_IWL<10769> A_IWL<10768> A_IWL<10767> A_IWL<10766> A_IWL<10765> A_IWL<10764> A_IWL<10763> A_IWL<10762> A_IWL<10761> A_IWL<10760> A_IWL<10759> A_IWL<10758> A_IWL<10757> A_IWL<10756> A_IWL<10755> A_IWL<10754> A_IWL<10753> A_IWL<10752> VDD_CORE VSS / RM_IHPSG13_8192x32_c4_1P_COLUMN_pcell_0 +XCOL<20> A_BLC<41> A_BLC<40> A_BLC_TOP<41> A_BLC_TOP<40> A_BLT<41> A_BLT<40> A_BLT_TOP<41> A_BLT_TOP<40> A_IWL<10239> A_IWL<10238> A_IWL<10237> A_IWL<10236> A_IWL<10235> A_IWL<10234> A_IWL<10233> A_IWL<10232> A_IWL<10231> A_IWL<10230> A_IWL<10229> A_IWL<10228> A_IWL<10227> A_IWL<10226> A_IWL<10225> A_IWL<10224> A_IWL<10223> A_IWL<10222> A_IWL<10221> A_IWL<10220> A_IWL<10219> A_IWL<10218> A_IWL<10217> A_IWL<10216> A_IWL<10215> A_IWL<10214> A_IWL<10213> A_IWL<10212> A_IWL<10211> A_IWL<10210> A_IWL<10209> A_IWL<10208> A_IWL<10207> A_IWL<10206> A_IWL<10205> A_IWL<10204> A_IWL<10203> A_IWL<10202> A_IWL<10201> A_IWL<10200> A_IWL<10199> A_IWL<10198> A_IWL<10197> A_IWL<10196> A_IWL<10195> A_IWL<10194> A_IWL<10193> A_IWL<10192> A_IWL<10191> A_IWL<10190> A_IWL<10189> A_IWL<10188> A_IWL<10187> A_IWL<10186> A_IWL<10185> A_IWL<10184> A_IWL<10183> A_IWL<10182> A_IWL<10181> A_IWL<10180> A_IWL<10179> A_IWL<10178> A_IWL<10177> A_IWL<10176> A_IWL<10175> A_IWL<10174> A_IWL<10173> A_IWL<10172> A_IWL<10171> A_IWL<10170> A_IWL<10169> A_IWL<10168> A_IWL<10167> A_IWL<10166> A_IWL<10165> A_IWL<10164> A_IWL<10163> A_IWL<10162> A_IWL<10161> A_IWL<10160> A_IWL<10159> A_IWL<10158> A_IWL<10157> A_IWL<10156> A_IWL<10155> A_IWL<10154> A_IWL<10153> A_IWL<10152> A_IWL<10151> A_IWL<10150> A_IWL<10149> A_IWL<10148> A_IWL<10147> A_IWL<10146> A_IWL<10145> A_IWL<10144> A_IWL<10143> A_IWL<10142> A_IWL<10141> A_IWL<10140> A_IWL<10139> A_IWL<10138> A_IWL<10137> A_IWL<10136> A_IWL<10135> A_IWL<10134> A_IWL<10133> A_IWL<10132> A_IWL<10131> A_IWL<10130> A_IWL<10129> A_IWL<10128> A_IWL<10127> A_IWL<10126> A_IWL<10125> A_IWL<10124> A_IWL<10123> A_IWL<10122> A_IWL<10121> A_IWL<10120> A_IWL<10119> A_IWL<10118> A_IWL<10117> A_IWL<10116> A_IWL<10115> A_IWL<10114> A_IWL<10113> A_IWL<10112> A_IWL<10111> A_IWL<10110> A_IWL<10109> A_IWL<10108> A_IWL<10107> A_IWL<10106> A_IWL<10105> A_IWL<10104> A_IWL<10103> A_IWL<10102> A_IWL<10101> A_IWL<10100> A_IWL<10099> A_IWL<10098> A_IWL<10097> A_IWL<10096> A_IWL<10095> A_IWL<10094> A_IWL<10093> A_IWL<10092> A_IWL<10091> A_IWL<10090> A_IWL<10089> A_IWL<10088> A_IWL<10087> A_IWL<10086> A_IWL<10085> A_IWL<10084> A_IWL<10083> A_IWL<10082> A_IWL<10081> A_IWL<10080> A_IWL<10079> A_IWL<10078> A_IWL<10077> A_IWL<10076> A_IWL<10075> A_IWL<10074> A_IWL<10073> A_IWL<10072> A_IWL<10071> A_IWL<10070> A_IWL<10069> A_IWL<10068> A_IWL<10067> A_IWL<10066> A_IWL<10065> A_IWL<10064> A_IWL<10063> A_IWL<10062> A_IWL<10061> A_IWL<10060> A_IWL<10059> A_IWL<10058> A_IWL<10057> A_IWL<10056> A_IWL<10055> A_IWL<10054> A_IWL<10053> A_IWL<10052> A_IWL<10051> A_IWL<10050> A_IWL<10049> A_IWL<10048> A_IWL<10047> A_IWL<10046> A_IWL<10045> A_IWL<10044> A_IWL<10043> A_IWL<10042> A_IWL<10041> A_IWL<10040> A_IWL<10039> A_IWL<10038> A_IWL<10037> A_IWL<10036> A_IWL<10035> A_IWL<10034> A_IWL<10033> A_IWL<10032> A_IWL<10031> A_IWL<10030> A_IWL<10029> A_IWL<10028> A_IWL<10027> A_IWL<10026> A_IWL<10025> A_IWL<10024> A_IWL<10023> A_IWL<10022> A_IWL<10021> A_IWL<10020> A_IWL<10019> A_IWL<10018> A_IWL<10017> A_IWL<10016> A_IWL<10015> A_IWL<10014> A_IWL<10013> A_IWL<10012> A_IWL<10011> A_IWL<10010> A_IWL<10009> A_IWL<10008> A_IWL<10007> A_IWL<10006> A_IWL<10005> A_IWL<10004> A_IWL<10003> A_IWL<10002> A_IWL<10001> A_IWL<10000> A_IWL<9999> A_IWL<9998> A_IWL<9997> A_IWL<9996> A_IWL<9995> A_IWL<9994> A_IWL<9993> A_IWL<9992> A_IWL<9991> A_IWL<9990> A_IWL<9989> A_IWL<9988> A_IWL<9987> A_IWL<9986> A_IWL<9985> A_IWL<9984> A_IWL<9983> A_IWL<9982> A_IWL<9981> A_IWL<9980> A_IWL<9979> A_IWL<9978> A_IWL<9977> A_IWL<9976> A_IWL<9975> A_IWL<9974> A_IWL<9973> A_IWL<9972> A_IWL<9971> A_IWL<9970> A_IWL<9969> A_IWL<9968> A_IWL<9967> A_IWL<9966> A_IWL<9965> A_IWL<9964> A_IWL<9963> A_IWL<9962> A_IWL<9961> A_IWL<9960> A_IWL<9959> A_IWL<9958> A_IWL<9957> A_IWL<9956> A_IWL<9955> A_IWL<9954> A_IWL<9953> A_IWL<9952> A_IWL<9951> A_IWL<9950> A_IWL<9949> A_IWL<9948> A_IWL<9947> A_IWL<9946> A_IWL<9945> A_IWL<9944> A_IWL<9943> A_IWL<9942> A_IWL<9941> A_IWL<9940> A_IWL<9939> A_IWL<9938> A_IWL<9937> A_IWL<9936> A_IWL<9935> A_IWL<9934> A_IWL<9933> A_IWL<9932> A_IWL<9931> A_IWL<9930> A_IWL<9929> A_IWL<9928> A_IWL<9927> A_IWL<9926> A_IWL<9925> A_IWL<9924> A_IWL<9923> A_IWL<9922> A_IWL<9921> A_IWL<9920> A_IWL<9919> A_IWL<9918> A_IWL<9917> A_IWL<9916> A_IWL<9915> A_IWL<9914> A_IWL<9913> A_IWL<9912> A_IWL<9911> A_IWL<9910> A_IWL<9909> A_IWL<9908> A_IWL<9907> A_IWL<9906> A_IWL<9905> A_IWL<9904> A_IWL<9903> A_IWL<9902> A_IWL<9901> A_IWL<9900> A_IWL<9899> A_IWL<9898> A_IWL<9897> A_IWL<9896> A_IWL<9895> A_IWL<9894> A_IWL<9893> A_IWL<9892> A_IWL<9891> A_IWL<9890> A_IWL<9889> A_IWL<9888> A_IWL<9887> A_IWL<9886> A_IWL<9885> A_IWL<9884> A_IWL<9883> A_IWL<9882> A_IWL<9881> A_IWL<9880> A_IWL<9879> A_IWL<9878> A_IWL<9877> A_IWL<9876> A_IWL<9875> A_IWL<9874> A_IWL<9873> A_IWL<9872> A_IWL<9871> A_IWL<9870> A_IWL<9869> A_IWL<9868> A_IWL<9867> A_IWL<9866> A_IWL<9865> A_IWL<9864> A_IWL<9863> A_IWL<9862> A_IWL<9861> A_IWL<9860> A_IWL<9859> A_IWL<9858> A_IWL<9857> A_IWL<9856> A_IWL<9855> A_IWL<9854> A_IWL<9853> A_IWL<9852> A_IWL<9851> A_IWL<9850> A_IWL<9849> A_IWL<9848> A_IWL<9847> A_IWL<9846> A_IWL<9845> A_IWL<9844> A_IWL<9843> A_IWL<9842> A_IWL<9841> A_IWL<9840> A_IWL<9839> A_IWL<9838> A_IWL<9837> A_IWL<9836> A_IWL<9835> A_IWL<9834> A_IWL<9833> A_IWL<9832> A_IWL<9831> A_IWL<9830> A_IWL<9829> A_IWL<9828> A_IWL<9827> A_IWL<9826> A_IWL<9825> A_IWL<9824> A_IWL<9823> A_IWL<9822> A_IWL<9821> A_IWL<9820> A_IWL<9819> A_IWL<9818> A_IWL<9817> A_IWL<9816> A_IWL<9815> A_IWL<9814> A_IWL<9813> A_IWL<9812> A_IWL<9811> A_IWL<9810> A_IWL<9809> A_IWL<9808> A_IWL<9807> A_IWL<9806> A_IWL<9805> A_IWL<9804> A_IWL<9803> A_IWL<9802> A_IWL<9801> A_IWL<9800> A_IWL<9799> A_IWL<9798> A_IWL<9797> A_IWL<9796> A_IWL<9795> A_IWL<9794> A_IWL<9793> A_IWL<9792> A_IWL<9791> A_IWL<9790> A_IWL<9789> A_IWL<9788> A_IWL<9787> A_IWL<9786> A_IWL<9785> A_IWL<9784> A_IWL<9783> A_IWL<9782> A_IWL<9781> A_IWL<9780> A_IWL<9779> A_IWL<9778> A_IWL<9777> A_IWL<9776> A_IWL<9775> A_IWL<9774> A_IWL<9773> A_IWL<9772> A_IWL<9771> A_IWL<9770> A_IWL<9769> A_IWL<9768> A_IWL<9767> A_IWL<9766> A_IWL<9765> A_IWL<9764> A_IWL<9763> A_IWL<9762> A_IWL<9761> A_IWL<9760> A_IWL<9759> A_IWL<9758> A_IWL<9757> A_IWL<9756> A_IWL<9755> A_IWL<9754> A_IWL<9753> A_IWL<9752> A_IWL<9751> A_IWL<9750> A_IWL<9749> A_IWL<9748> A_IWL<9747> A_IWL<9746> A_IWL<9745> A_IWL<9744> A_IWL<9743> A_IWL<9742> A_IWL<9741> A_IWL<9740> A_IWL<9739> A_IWL<9738> A_IWL<9737> A_IWL<9736> A_IWL<9735> A_IWL<9734> A_IWL<9733> A_IWL<9732> A_IWL<9731> A_IWL<9730> A_IWL<9729> A_IWL<9728> A_IWL<10751> A_IWL<10750> A_IWL<10749> A_IWL<10748> A_IWL<10747> A_IWL<10746> A_IWL<10745> A_IWL<10744> A_IWL<10743> A_IWL<10742> A_IWL<10741> A_IWL<10740> A_IWL<10739> A_IWL<10738> A_IWL<10737> A_IWL<10736> A_IWL<10735> A_IWL<10734> A_IWL<10733> A_IWL<10732> A_IWL<10731> A_IWL<10730> A_IWL<10729> A_IWL<10728> A_IWL<10727> A_IWL<10726> A_IWL<10725> A_IWL<10724> A_IWL<10723> A_IWL<10722> A_IWL<10721> A_IWL<10720> A_IWL<10719> A_IWL<10718> A_IWL<10717> A_IWL<10716> A_IWL<10715> A_IWL<10714> A_IWL<10713> A_IWL<10712> A_IWL<10711> A_IWL<10710> A_IWL<10709> A_IWL<10708> A_IWL<10707> A_IWL<10706> A_IWL<10705> A_IWL<10704> A_IWL<10703> A_IWL<10702> A_IWL<10701> A_IWL<10700> A_IWL<10699> A_IWL<10698> A_IWL<10697> A_IWL<10696> A_IWL<10695> A_IWL<10694> A_IWL<10693> A_IWL<10692> A_IWL<10691> A_IWL<10690> A_IWL<10689> A_IWL<10688> A_IWL<10687> A_IWL<10686> A_IWL<10685> A_IWL<10684> A_IWL<10683> A_IWL<10682> A_IWL<10681> A_IWL<10680> A_IWL<10679> A_IWL<10678> A_IWL<10677> A_IWL<10676> A_IWL<10675> A_IWL<10674> A_IWL<10673> A_IWL<10672> A_IWL<10671> A_IWL<10670> A_IWL<10669> A_IWL<10668> A_IWL<10667> A_IWL<10666> A_IWL<10665> A_IWL<10664> A_IWL<10663> A_IWL<10662> A_IWL<10661> A_IWL<10660> A_IWL<10659> A_IWL<10658> A_IWL<10657> A_IWL<10656> A_IWL<10655> A_IWL<10654> A_IWL<10653> A_IWL<10652> A_IWL<10651> A_IWL<10650> A_IWL<10649> A_IWL<10648> A_IWL<10647> A_IWL<10646> A_IWL<10645> A_IWL<10644> A_IWL<10643> A_IWL<10642> A_IWL<10641> A_IWL<10640> A_IWL<10639> A_IWL<10638> A_IWL<10637> A_IWL<10636> A_IWL<10635> A_IWL<10634> A_IWL<10633> A_IWL<10632> A_IWL<10631> A_IWL<10630> A_IWL<10629> A_IWL<10628> A_IWL<10627> A_IWL<10626> A_IWL<10625> A_IWL<10624> A_IWL<10623> A_IWL<10622> A_IWL<10621> A_IWL<10620> A_IWL<10619> A_IWL<10618> A_IWL<10617> A_IWL<10616> A_IWL<10615> A_IWL<10614> A_IWL<10613> A_IWL<10612> A_IWL<10611> A_IWL<10610> A_IWL<10609> A_IWL<10608> A_IWL<10607> A_IWL<10606> A_IWL<10605> A_IWL<10604> A_IWL<10603> A_IWL<10602> A_IWL<10601> A_IWL<10600> A_IWL<10599> A_IWL<10598> A_IWL<10597> A_IWL<10596> A_IWL<10595> A_IWL<10594> A_IWL<10593> A_IWL<10592> A_IWL<10591> A_IWL<10590> A_IWL<10589> A_IWL<10588> A_IWL<10587> A_IWL<10586> A_IWL<10585> A_IWL<10584> A_IWL<10583> A_IWL<10582> A_IWL<10581> A_IWL<10580> A_IWL<10579> A_IWL<10578> A_IWL<10577> A_IWL<10576> A_IWL<10575> A_IWL<10574> A_IWL<10573> A_IWL<10572> A_IWL<10571> A_IWL<10570> A_IWL<10569> A_IWL<10568> A_IWL<10567> A_IWL<10566> A_IWL<10565> A_IWL<10564> A_IWL<10563> A_IWL<10562> A_IWL<10561> A_IWL<10560> A_IWL<10559> A_IWL<10558> A_IWL<10557> A_IWL<10556> A_IWL<10555> A_IWL<10554> A_IWL<10553> A_IWL<10552> A_IWL<10551> A_IWL<10550> A_IWL<10549> A_IWL<10548> A_IWL<10547> A_IWL<10546> A_IWL<10545> A_IWL<10544> A_IWL<10543> A_IWL<10542> A_IWL<10541> A_IWL<10540> A_IWL<10539> A_IWL<10538> A_IWL<10537> A_IWL<10536> A_IWL<10535> A_IWL<10534> A_IWL<10533> A_IWL<10532> A_IWL<10531> A_IWL<10530> A_IWL<10529> A_IWL<10528> A_IWL<10527> A_IWL<10526> A_IWL<10525> A_IWL<10524> A_IWL<10523> A_IWL<10522> A_IWL<10521> A_IWL<10520> A_IWL<10519> A_IWL<10518> A_IWL<10517> A_IWL<10516> A_IWL<10515> A_IWL<10514> A_IWL<10513> A_IWL<10512> A_IWL<10511> A_IWL<10510> A_IWL<10509> A_IWL<10508> A_IWL<10507> A_IWL<10506> A_IWL<10505> A_IWL<10504> A_IWL<10503> A_IWL<10502> A_IWL<10501> A_IWL<10500> A_IWL<10499> A_IWL<10498> A_IWL<10497> A_IWL<10496> A_IWL<10495> A_IWL<10494> A_IWL<10493> A_IWL<10492> A_IWL<10491> A_IWL<10490> A_IWL<10489> A_IWL<10488> A_IWL<10487> A_IWL<10486> A_IWL<10485> A_IWL<10484> A_IWL<10483> A_IWL<10482> A_IWL<10481> A_IWL<10480> A_IWL<10479> A_IWL<10478> A_IWL<10477> A_IWL<10476> A_IWL<10475> A_IWL<10474> A_IWL<10473> A_IWL<10472> A_IWL<10471> A_IWL<10470> A_IWL<10469> A_IWL<10468> A_IWL<10467> A_IWL<10466> A_IWL<10465> A_IWL<10464> A_IWL<10463> A_IWL<10462> A_IWL<10461> A_IWL<10460> A_IWL<10459> A_IWL<10458> A_IWL<10457> A_IWL<10456> A_IWL<10455> A_IWL<10454> A_IWL<10453> A_IWL<10452> A_IWL<10451> A_IWL<10450> A_IWL<10449> A_IWL<10448> A_IWL<10447> A_IWL<10446> A_IWL<10445> A_IWL<10444> A_IWL<10443> A_IWL<10442> A_IWL<10441> A_IWL<10440> A_IWL<10439> A_IWL<10438> A_IWL<10437> A_IWL<10436> A_IWL<10435> A_IWL<10434> A_IWL<10433> A_IWL<10432> A_IWL<10431> A_IWL<10430> A_IWL<10429> A_IWL<10428> A_IWL<10427> A_IWL<10426> A_IWL<10425> A_IWL<10424> A_IWL<10423> A_IWL<10422> A_IWL<10421> A_IWL<10420> A_IWL<10419> A_IWL<10418> A_IWL<10417> A_IWL<10416> A_IWL<10415> A_IWL<10414> A_IWL<10413> A_IWL<10412> A_IWL<10411> A_IWL<10410> A_IWL<10409> A_IWL<10408> A_IWL<10407> A_IWL<10406> A_IWL<10405> A_IWL<10404> A_IWL<10403> A_IWL<10402> A_IWL<10401> A_IWL<10400> A_IWL<10399> A_IWL<10398> A_IWL<10397> A_IWL<10396> A_IWL<10395> A_IWL<10394> A_IWL<10393> A_IWL<10392> A_IWL<10391> A_IWL<10390> A_IWL<10389> A_IWL<10388> A_IWL<10387> A_IWL<10386> A_IWL<10385> A_IWL<10384> A_IWL<10383> A_IWL<10382> A_IWL<10381> A_IWL<10380> A_IWL<10379> A_IWL<10378> A_IWL<10377> A_IWL<10376> A_IWL<10375> A_IWL<10374> A_IWL<10373> A_IWL<10372> A_IWL<10371> A_IWL<10370> A_IWL<10369> A_IWL<10368> A_IWL<10367> A_IWL<10366> A_IWL<10365> A_IWL<10364> A_IWL<10363> A_IWL<10362> A_IWL<10361> A_IWL<10360> A_IWL<10359> A_IWL<10358> A_IWL<10357> A_IWL<10356> A_IWL<10355> A_IWL<10354> A_IWL<10353> A_IWL<10352> A_IWL<10351> A_IWL<10350> A_IWL<10349> A_IWL<10348> A_IWL<10347> A_IWL<10346> A_IWL<10345> A_IWL<10344> A_IWL<10343> A_IWL<10342> A_IWL<10341> A_IWL<10340> A_IWL<10339> A_IWL<10338> A_IWL<10337> A_IWL<10336> A_IWL<10335> A_IWL<10334> A_IWL<10333> A_IWL<10332> A_IWL<10331> A_IWL<10330> A_IWL<10329> A_IWL<10328> A_IWL<10327> A_IWL<10326> A_IWL<10325> A_IWL<10324> A_IWL<10323> A_IWL<10322> A_IWL<10321> A_IWL<10320> A_IWL<10319> A_IWL<10318> A_IWL<10317> A_IWL<10316> A_IWL<10315> A_IWL<10314> A_IWL<10313> A_IWL<10312> A_IWL<10311> A_IWL<10310> A_IWL<10309> A_IWL<10308> A_IWL<10307> A_IWL<10306> A_IWL<10305> A_IWL<10304> A_IWL<10303> A_IWL<10302> A_IWL<10301> A_IWL<10300> A_IWL<10299> A_IWL<10298> A_IWL<10297> A_IWL<10296> A_IWL<10295> A_IWL<10294> A_IWL<10293> A_IWL<10292> A_IWL<10291> A_IWL<10290> A_IWL<10289> A_IWL<10288> A_IWL<10287> A_IWL<10286> A_IWL<10285> A_IWL<10284> A_IWL<10283> A_IWL<10282> A_IWL<10281> A_IWL<10280> A_IWL<10279> A_IWL<10278> A_IWL<10277> A_IWL<10276> A_IWL<10275> A_IWL<10274> A_IWL<10273> A_IWL<10272> A_IWL<10271> A_IWL<10270> A_IWL<10269> A_IWL<10268> A_IWL<10267> A_IWL<10266> A_IWL<10265> A_IWL<10264> A_IWL<10263> A_IWL<10262> A_IWL<10261> A_IWL<10260> A_IWL<10259> A_IWL<10258> A_IWL<10257> A_IWL<10256> A_IWL<10255> A_IWL<10254> A_IWL<10253> A_IWL<10252> A_IWL<10251> A_IWL<10250> A_IWL<10249> A_IWL<10248> A_IWL<10247> A_IWL<10246> A_IWL<10245> A_IWL<10244> A_IWL<10243> A_IWL<10242> A_IWL<10241> A_IWL<10240> VDD_CORE VSS / RM_IHPSG13_8192x32_c4_1P_COLUMN_pcell_0 +XCOL<19> A_BLC<39> A_BLC<38> A_BLC_TOP<39> A_BLC_TOP<38> A_BLT<39> A_BLT<38> A_BLT_TOP<39> A_BLT_TOP<38> A_IWL<9727> A_IWL<9726> A_IWL<9725> A_IWL<9724> A_IWL<9723> A_IWL<9722> A_IWL<9721> A_IWL<9720> A_IWL<9719> A_IWL<9718> A_IWL<9717> A_IWL<9716> A_IWL<9715> A_IWL<9714> A_IWL<9713> A_IWL<9712> A_IWL<9711> A_IWL<9710> A_IWL<9709> A_IWL<9708> A_IWL<9707> A_IWL<9706> A_IWL<9705> A_IWL<9704> A_IWL<9703> A_IWL<9702> A_IWL<9701> A_IWL<9700> A_IWL<9699> A_IWL<9698> A_IWL<9697> A_IWL<9696> A_IWL<9695> A_IWL<9694> A_IWL<9693> A_IWL<9692> A_IWL<9691> A_IWL<9690> A_IWL<9689> A_IWL<9688> A_IWL<9687> A_IWL<9686> A_IWL<9685> A_IWL<9684> A_IWL<9683> A_IWL<9682> A_IWL<9681> A_IWL<9680> A_IWL<9679> A_IWL<9678> A_IWL<9677> A_IWL<9676> A_IWL<9675> A_IWL<9674> A_IWL<9673> A_IWL<9672> A_IWL<9671> A_IWL<9670> A_IWL<9669> A_IWL<9668> A_IWL<9667> A_IWL<9666> A_IWL<9665> A_IWL<9664> A_IWL<9663> A_IWL<9662> A_IWL<9661> A_IWL<9660> A_IWL<9659> A_IWL<9658> A_IWL<9657> A_IWL<9656> A_IWL<9655> A_IWL<9654> A_IWL<9653> A_IWL<9652> A_IWL<9651> A_IWL<9650> A_IWL<9649> A_IWL<9648> A_IWL<9647> A_IWL<9646> A_IWL<9645> A_IWL<9644> A_IWL<9643> A_IWL<9642> A_IWL<9641> A_IWL<9640> A_IWL<9639> A_IWL<9638> A_IWL<9637> A_IWL<9636> A_IWL<9635> A_IWL<9634> A_IWL<9633> A_IWL<9632> A_IWL<9631> A_IWL<9630> A_IWL<9629> A_IWL<9628> A_IWL<9627> A_IWL<9626> A_IWL<9625> A_IWL<9624> A_IWL<9623> A_IWL<9622> A_IWL<9621> A_IWL<9620> A_IWL<9619> A_IWL<9618> A_IWL<9617> A_IWL<9616> A_IWL<9615> A_IWL<9614> A_IWL<9613> A_IWL<9612> A_IWL<9611> A_IWL<9610> A_IWL<9609> A_IWL<9608> A_IWL<9607> A_IWL<9606> A_IWL<9605> A_IWL<9604> A_IWL<9603> A_IWL<9602> A_IWL<9601> A_IWL<9600> A_IWL<9599> A_IWL<9598> A_IWL<9597> A_IWL<9596> A_IWL<9595> A_IWL<9594> A_IWL<9593> A_IWL<9592> A_IWL<9591> A_IWL<9590> A_IWL<9589> A_IWL<9588> A_IWL<9587> A_IWL<9586> A_IWL<9585> A_IWL<9584> A_IWL<9583> A_IWL<9582> A_IWL<9581> A_IWL<9580> A_IWL<9579> A_IWL<9578> A_IWL<9577> A_IWL<9576> A_IWL<9575> A_IWL<9574> A_IWL<9573> A_IWL<9572> A_IWL<9571> A_IWL<9570> A_IWL<9569> A_IWL<9568> A_IWL<9567> A_IWL<9566> A_IWL<9565> A_IWL<9564> A_IWL<9563> A_IWL<9562> A_IWL<9561> A_IWL<9560> A_IWL<9559> A_IWL<9558> A_IWL<9557> A_IWL<9556> A_IWL<9555> A_IWL<9554> A_IWL<9553> A_IWL<9552> A_IWL<9551> A_IWL<9550> A_IWL<9549> A_IWL<9548> A_IWL<9547> A_IWL<9546> A_IWL<9545> A_IWL<9544> A_IWL<9543> A_IWL<9542> A_IWL<9541> A_IWL<9540> A_IWL<9539> A_IWL<9538> A_IWL<9537> A_IWL<9536> A_IWL<9535> A_IWL<9534> A_IWL<9533> A_IWL<9532> A_IWL<9531> A_IWL<9530> A_IWL<9529> A_IWL<9528> A_IWL<9527> A_IWL<9526> A_IWL<9525> A_IWL<9524> A_IWL<9523> A_IWL<9522> A_IWL<9521> A_IWL<9520> A_IWL<9519> A_IWL<9518> A_IWL<9517> A_IWL<9516> A_IWL<9515> A_IWL<9514> A_IWL<9513> A_IWL<9512> A_IWL<9511> A_IWL<9510> A_IWL<9509> A_IWL<9508> A_IWL<9507> A_IWL<9506> A_IWL<9505> A_IWL<9504> A_IWL<9503> A_IWL<9502> A_IWL<9501> A_IWL<9500> A_IWL<9499> A_IWL<9498> A_IWL<9497> A_IWL<9496> A_IWL<9495> A_IWL<9494> A_IWL<9493> A_IWL<9492> A_IWL<9491> A_IWL<9490> A_IWL<9489> A_IWL<9488> A_IWL<9487> A_IWL<9486> A_IWL<9485> A_IWL<9484> A_IWL<9483> A_IWL<9482> A_IWL<9481> A_IWL<9480> A_IWL<9479> A_IWL<9478> A_IWL<9477> A_IWL<9476> A_IWL<9475> A_IWL<9474> A_IWL<9473> A_IWL<9472> A_IWL<9471> A_IWL<9470> A_IWL<9469> A_IWL<9468> A_IWL<9467> A_IWL<9466> A_IWL<9465> A_IWL<9464> A_IWL<9463> A_IWL<9462> A_IWL<9461> A_IWL<9460> A_IWL<9459> A_IWL<9458> A_IWL<9457> A_IWL<9456> A_IWL<9455> A_IWL<9454> A_IWL<9453> A_IWL<9452> A_IWL<9451> A_IWL<9450> A_IWL<9449> A_IWL<9448> A_IWL<9447> A_IWL<9446> A_IWL<9445> A_IWL<9444> A_IWL<9443> A_IWL<9442> A_IWL<9441> A_IWL<9440> A_IWL<9439> A_IWL<9438> A_IWL<9437> A_IWL<9436> A_IWL<9435> A_IWL<9434> A_IWL<9433> A_IWL<9432> A_IWL<9431> A_IWL<9430> A_IWL<9429> A_IWL<9428> A_IWL<9427> A_IWL<9426> A_IWL<9425> A_IWL<9424> A_IWL<9423> A_IWL<9422> A_IWL<9421> A_IWL<9420> A_IWL<9419> A_IWL<9418> A_IWL<9417> A_IWL<9416> A_IWL<9415> A_IWL<9414> A_IWL<9413> A_IWL<9412> A_IWL<9411> A_IWL<9410> A_IWL<9409> A_IWL<9408> A_IWL<9407> A_IWL<9406> A_IWL<9405> A_IWL<9404> A_IWL<9403> A_IWL<9402> A_IWL<9401> A_IWL<9400> A_IWL<9399> A_IWL<9398> A_IWL<9397> A_IWL<9396> A_IWL<9395> A_IWL<9394> A_IWL<9393> A_IWL<9392> A_IWL<9391> A_IWL<9390> A_IWL<9389> A_IWL<9388> A_IWL<9387> A_IWL<9386> A_IWL<9385> A_IWL<9384> A_IWL<9383> A_IWL<9382> A_IWL<9381> A_IWL<9380> A_IWL<9379> A_IWL<9378> A_IWL<9377> A_IWL<9376> A_IWL<9375> A_IWL<9374> A_IWL<9373> A_IWL<9372> A_IWL<9371> A_IWL<9370> A_IWL<9369> A_IWL<9368> A_IWL<9367> A_IWL<9366> A_IWL<9365> A_IWL<9364> A_IWL<9363> A_IWL<9362> A_IWL<9361> A_IWL<9360> A_IWL<9359> A_IWL<9358> A_IWL<9357> A_IWL<9356> A_IWL<9355> A_IWL<9354> A_IWL<9353> A_IWL<9352> A_IWL<9351> A_IWL<9350> A_IWL<9349> A_IWL<9348> A_IWL<9347> A_IWL<9346> A_IWL<9345> A_IWL<9344> A_IWL<9343> A_IWL<9342> A_IWL<9341> A_IWL<9340> A_IWL<9339> A_IWL<9338> A_IWL<9337> A_IWL<9336> A_IWL<9335> A_IWL<9334> A_IWL<9333> A_IWL<9332> A_IWL<9331> A_IWL<9330> A_IWL<9329> A_IWL<9328> A_IWL<9327> A_IWL<9326> A_IWL<9325> A_IWL<9324> A_IWL<9323> A_IWL<9322> A_IWL<9321> A_IWL<9320> A_IWL<9319> A_IWL<9318> A_IWL<9317> A_IWL<9316> A_IWL<9315> A_IWL<9314> A_IWL<9313> A_IWL<9312> A_IWL<9311> A_IWL<9310> A_IWL<9309> A_IWL<9308> A_IWL<9307> A_IWL<9306> A_IWL<9305> A_IWL<9304> A_IWL<9303> A_IWL<9302> A_IWL<9301> A_IWL<9300> A_IWL<9299> A_IWL<9298> A_IWL<9297> A_IWL<9296> A_IWL<9295> A_IWL<9294> A_IWL<9293> A_IWL<9292> A_IWL<9291> A_IWL<9290> A_IWL<9289> A_IWL<9288> A_IWL<9287> A_IWL<9286> A_IWL<9285> A_IWL<9284> A_IWL<9283> A_IWL<9282> A_IWL<9281> A_IWL<9280> A_IWL<9279> A_IWL<9278> A_IWL<9277> A_IWL<9276> A_IWL<9275> A_IWL<9274> A_IWL<9273> A_IWL<9272> A_IWL<9271> A_IWL<9270> A_IWL<9269> A_IWL<9268> A_IWL<9267> A_IWL<9266> A_IWL<9265> A_IWL<9264> A_IWL<9263> A_IWL<9262> A_IWL<9261> A_IWL<9260> A_IWL<9259> A_IWL<9258> A_IWL<9257> A_IWL<9256> A_IWL<9255> A_IWL<9254> A_IWL<9253> A_IWL<9252> A_IWL<9251> A_IWL<9250> A_IWL<9249> A_IWL<9248> A_IWL<9247> A_IWL<9246> A_IWL<9245> A_IWL<9244> A_IWL<9243> A_IWL<9242> A_IWL<9241> A_IWL<9240> A_IWL<9239> A_IWL<9238> A_IWL<9237> A_IWL<9236> A_IWL<9235> A_IWL<9234> A_IWL<9233> A_IWL<9232> A_IWL<9231> A_IWL<9230> A_IWL<9229> A_IWL<9228> A_IWL<9227> A_IWL<9226> A_IWL<9225> A_IWL<9224> A_IWL<9223> A_IWL<9222> A_IWL<9221> A_IWL<9220> A_IWL<9219> A_IWL<9218> A_IWL<9217> A_IWL<9216> A_IWL<10239> A_IWL<10238> A_IWL<10237> A_IWL<10236> A_IWL<10235> A_IWL<10234> A_IWL<10233> A_IWL<10232> A_IWL<10231> A_IWL<10230> A_IWL<10229> A_IWL<10228> A_IWL<10227> A_IWL<10226> A_IWL<10225> A_IWL<10224> A_IWL<10223> A_IWL<10222> A_IWL<10221> A_IWL<10220> A_IWL<10219> A_IWL<10218> A_IWL<10217> A_IWL<10216> A_IWL<10215> A_IWL<10214> A_IWL<10213> A_IWL<10212> A_IWL<10211> A_IWL<10210> A_IWL<10209> A_IWL<10208> A_IWL<10207> A_IWL<10206> A_IWL<10205> A_IWL<10204> A_IWL<10203> A_IWL<10202> A_IWL<10201> A_IWL<10200> A_IWL<10199> A_IWL<10198> A_IWL<10197> A_IWL<10196> A_IWL<10195> A_IWL<10194> A_IWL<10193> A_IWL<10192> A_IWL<10191> A_IWL<10190> A_IWL<10189> A_IWL<10188> A_IWL<10187> A_IWL<10186> A_IWL<10185> A_IWL<10184> A_IWL<10183> A_IWL<10182> A_IWL<10181> A_IWL<10180> A_IWL<10179> A_IWL<10178> A_IWL<10177> A_IWL<10176> A_IWL<10175> A_IWL<10174> A_IWL<10173> A_IWL<10172> A_IWL<10171> A_IWL<10170> A_IWL<10169> A_IWL<10168> A_IWL<10167> A_IWL<10166> A_IWL<10165> A_IWL<10164> A_IWL<10163> A_IWL<10162> A_IWL<10161> A_IWL<10160> A_IWL<10159> A_IWL<10158> A_IWL<10157> A_IWL<10156> A_IWL<10155> A_IWL<10154> A_IWL<10153> A_IWL<10152> A_IWL<10151> A_IWL<10150> A_IWL<10149> A_IWL<10148> A_IWL<10147> A_IWL<10146> A_IWL<10145> A_IWL<10144> A_IWL<10143> A_IWL<10142> A_IWL<10141> A_IWL<10140> A_IWL<10139> A_IWL<10138> A_IWL<10137> A_IWL<10136> A_IWL<10135> A_IWL<10134> A_IWL<10133> A_IWL<10132> A_IWL<10131> A_IWL<10130> A_IWL<10129> A_IWL<10128> A_IWL<10127> A_IWL<10126> A_IWL<10125> A_IWL<10124> A_IWL<10123> A_IWL<10122> A_IWL<10121> A_IWL<10120> A_IWL<10119> A_IWL<10118> A_IWL<10117> A_IWL<10116> A_IWL<10115> A_IWL<10114> A_IWL<10113> A_IWL<10112> A_IWL<10111> A_IWL<10110> A_IWL<10109> A_IWL<10108> A_IWL<10107> A_IWL<10106> A_IWL<10105> A_IWL<10104> A_IWL<10103> A_IWL<10102> A_IWL<10101> A_IWL<10100> A_IWL<10099> A_IWL<10098> A_IWL<10097> A_IWL<10096> A_IWL<10095> A_IWL<10094> A_IWL<10093> A_IWL<10092> A_IWL<10091> A_IWL<10090> A_IWL<10089> A_IWL<10088> A_IWL<10087> A_IWL<10086> A_IWL<10085> A_IWL<10084> A_IWL<10083> A_IWL<10082> A_IWL<10081> A_IWL<10080> A_IWL<10079> A_IWL<10078> A_IWL<10077> A_IWL<10076> A_IWL<10075> A_IWL<10074> A_IWL<10073> A_IWL<10072> A_IWL<10071> A_IWL<10070> A_IWL<10069> A_IWL<10068> A_IWL<10067> A_IWL<10066> A_IWL<10065> A_IWL<10064> A_IWL<10063> A_IWL<10062> A_IWL<10061> A_IWL<10060> A_IWL<10059> A_IWL<10058> A_IWL<10057> A_IWL<10056> A_IWL<10055> A_IWL<10054> A_IWL<10053> A_IWL<10052> A_IWL<10051> A_IWL<10050> A_IWL<10049> A_IWL<10048> A_IWL<10047> A_IWL<10046> A_IWL<10045> A_IWL<10044> A_IWL<10043> A_IWL<10042> A_IWL<10041> A_IWL<10040> A_IWL<10039> A_IWL<10038> A_IWL<10037> A_IWL<10036> A_IWL<10035> A_IWL<10034> A_IWL<10033> A_IWL<10032> A_IWL<10031> A_IWL<10030> A_IWL<10029> A_IWL<10028> A_IWL<10027> A_IWL<10026> A_IWL<10025> A_IWL<10024> A_IWL<10023> A_IWL<10022> A_IWL<10021> A_IWL<10020> A_IWL<10019> A_IWL<10018> A_IWL<10017> A_IWL<10016> A_IWL<10015> A_IWL<10014> A_IWL<10013> A_IWL<10012> A_IWL<10011> A_IWL<10010> A_IWL<10009> A_IWL<10008> A_IWL<10007> A_IWL<10006> A_IWL<10005> A_IWL<10004> A_IWL<10003> A_IWL<10002> A_IWL<10001> A_IWL<10000> A_IWL<9999> A_IWL<9998> A_IWL<9997> A_IWL<9996> A_IWL<9995> A_IWL<9994> A_IWL<9993> A_IWL<9992> A_IWL<9991> A_IWL<9990> A_IWL<9989> A_IWL<9988> A_IWL<9987> A_IWL<9986> A_IWL<9985> A_IWL<9984> A_IWL<9983> A_IWL<9982> A_IWL<9981> A_IWL<9980> A_IWL<9979> A_IWL<9978> A_IWL<9977> A_IWL<9976> A_IWL<9975> A_IWL<9974> A_IWL<9973> A_IWL<9972> A_IWL<9971> A_IWL<9970> A_IWL<9969> A_IWL<9968> A_IWL<9967> A_IWL<9966> A_IWL<9965> A_IWL<9964> A_IWL<9963> A_IWL<9962> A_IWL<9961> A_IWL<9960> A_IWL<9959> A_IWL<9958> A_IWL<9957> A_IWL<9956> A_IWL<9955> A_IWL<9954> A_IWL<9953> A_IWL<9952> A_IWL<9951> A_IWL<9950> A_IWL<9949> A_IWL<9948> A_IWL<9947> A_IWL<9946> A_IWL<9945> A_IWL<9944> A_IWL<9943> A_IWL<9942> A_IWL<9941> A_IWL<9940> A_IWL<9939> A_IWL<9938> A_IWL<9937> A_IWL<9936> A_IWL<9935> A_IWL<9934> A_IWL<9933> A_IWL<9932> A_IWL<9931> A_IWL<9930> A_IWL<9929> A_IWL<9928> A_IWL<9927> A_IWL<9926> A_IWL<9925> A_IWL<9924> A_IWL<9923> A_IWL<9922> A_IWL<9921> A_IWL<9920> A_IWL<9919> A_IWL<9918> A_IWL<9917> A_IWL<9916> A_IWL<9915> A_IWL<9914> A_IWL<9913> A_IWL<9912> A_IWL<9911> A_IWL<9910> A_IWL<9909> A_IWL<9908> A_IWL<9907> A_IWL<9906> A_IWL<9905> A_IWL<9904> A_IWL<9903> A_IWL<9902> A_IWL<9901> A_IWL<9900> A_IWL<9899> A_IWL<9898> A_IWL<9897> A_IWL<9896> A_IWL<9895> A_IWL<9894> A_IWL<9893> A_IWL<9892> A_IWL<9891> A_IWL<9890> A_IWL<9889> A_IWL<9888> A_IWL<9887> A_IWL<9886> A_IWL<9885> A_IWL<9884> A_IWL<9883> A_IWL<9882> A_IWL<9881> A_IWL<9880> A_IWL<9879> A_IWL<9878> A_IWL<9877> A_IWL<9876> A_IWL<9875> A_IWL<9874> A_IWL<9873> A_IWL<9872> A_IWL<9871> A_IWL<9870> A_IWL<9869> A_IWL<9868> A_IWL<9867> A_IWL<9866> A_IWL<9865> A_IWL<9864> A_IWL<9863> A_IWL<9862> A_IWL<9861> A_IWL<9860> A_IWL<9859> A_IWL<9858> A_IWL<9857> A_IWL<9856> A_IWL<9855> A_IWL<9854> A_IWL<9853> A_IWL<9852> A_IWL<9851> A_IWL<9850> A_IWL<9849> A_IWL<9848> A_IWL<9847> A_IWL<9846> A_IWL<9845> A_IWL<9844> A_IWL<9843> A_IWL<9842> A_IWL<9841> A_IWL<9840> A_IWL<9839> A_IWL<9838> A_IWL<9837> A_IWL<9836> A_IWL<9835> A_IWL<9834> A_IWL<9833> A_IWL<9832> A_IWL<9831> A_IWL<9830> A_IWL<9829> A_IWL<9828> A_IWL<9827> A_IWL<9826> A_IWL<9825> A_IWL<9824> A_IWL<9823> A_IWL<9822> A_IWL<9821> A_IWL<9820> A_IWL<9819> A_IWL<9818> A_IWL<9817> A_IWL<9816> A_IWL<9815> A_IWL<9814> A_IWL<9813> A_IWL<9812> A_IWL<9811> A_IWL<9810> A_IWL<9809> A_IWL<9808> A_IWL<9807> A_IWL<9806> A_IWL<9805> A_IWL<9804> A_IWL<9803> A_IWL<9802> A_IWL<9801> A_IWL<9800> A_IWL<9799> A_IWL<9798> A_IWL<9797> A_IWL<9796> A_IWL<9795> A_IWL<9794> A_IWL<9793> A_IWL<9792> A_IWL<9791> A_IWL<9790> A_IWL<9789> A_IWL<9788> A_IWL<9787> A_IWL<9786> A_IWL<9785> A_IWL<9784> A_IWL<9783> A_IWL<9782> A_IWL<9781> A_IWL<9780> A_IWL<9779> A_IWL<9778> A_IWL<9777> A_IWL<9776> A_IWL<9775> A_IWL<9774> A_IWL<9773> A_IWL<9772> A_IWL<9771> A_IWL<9770> A_IWL<9769> A_IWL<9768> A_IWL<9767> A_IWL<9766> A_IWL<9765> A_IWL<9764> A_IWL<9763> A_IWL<9762> A_IWL<9761> A_IWL<9760> A_IWL<9759> A_IWL<9758> A_IWL<9757> A_IWL<9756> A_IWL<9755> A_IWL<9754> A_IWL<9753> A_IWL<9752> A_IWL<9751> A_IWL<9750> A_IWL<9749> A_IWL<9748> A_IWL<9747> A_IWL<9746> A_IWL<9745> A_IWL<9744> A_IWL<9743> A_IWL<9742> A_IWL<9741> A_IWL<9740> A_IWL<9739> A_IWL<9738> A_IWL<9737> A_IWL<9736> A_IWL<9735> A_IWL<9734> A_IWL<9733> A_IWL<9732> A_IWL<9731> A_IWL<9730> A_IWL<9729> A_IWL<9728> VDD_CORE VSS / RM_IHPSG13_8192x32_c4_1P_COLUMN_pcell_0 +XCOL<18> A_BLC<37> A_BLC<36> A_BLC_TOP<37> A_BLC_TOP<36> A_BLT<37> A_BLT<36> A_BLT_TOP<37> A_BLT_TOP<36> A_IWL<9215> A_IWL<9214> A_IWL<9213> A_IWL<9212> A_IWL<9211> A_IWL<9210> A_IWL<9209> A_IWL<9208> A_IWL<9207> A_IWL<9206> A_IWL<9205> A_IWL<9204> A_IWL<9203> A_IWL<9202> A_IWL<9201> A_IWL<9200> A_IWL<9199> A_IWL<9198> A_IWL<9197> A_IWL<9196> A_IWL<9195> A_IWL<9194> A_IWL<9193> A_IWL<9192> A_IWL<9191> A_IWL<9190> A_IWL<9189> A_IWL<9188> A_IWL<9187> A_IWL<9186> A_IWL<9185> A_IWL<9184> A_IWL<9183> A_IWL<9182> A_IWL<9181> A_IWL<9180> A_IWL<9179> A_IWL<9178> A_IWL<9177> A_IWL<9176> A_IWL<9175> A_IWL<9174> A_IWL<9173> A_IWL<9172> A_IWL<9171> A_IWL<9170> A_IWL<9169> A_IWL<9168> A_IWL<9167> A_IWL<9166> A_IWL<9165> A_IWL<9164> A_IWL<9163> A_IWL<9162> A_IWL<9161> A_IWL<9160> A_IWL<9159> A_IWL<9158> A_IWL<9157> A_IWL<9156> A_IWL<9155> A_IWL<9154> A_IWL<9153> A_IWL<9152> A_IWL<9151> A_IWL<9150> A_IWL<9149> A_IWL<9148> A_IWL<9147> A_IWL<9146> A_IWL<9145> A_IWL<9144> A_IWL<9143> A_IWL<9142> A_IWL<9141> A_IWL<9140> A_IWL<9139> A_IWL<9138> A_IWL<9137> A_IWL<9136> A_IWL<9135> A_IWL<9134> A_IWL<9133> A_IWL<9132> A_IWL<9131> A_IWL<9130> A_IWL<9129> A_IWL<9128> A_IWL<9127> A_IWL<9126> A_IWL<9125> A_IWL<9124> A_IWL<9123> A_IWL<9122> A_IWL<9121> A_IWL<9120> A_IWL<9119> A_IWL<9118> A_IWL<9117> A_IWL<9116> A_IWL<9115> A_IWL<9114> A_IWL<9113> A_IWL<9112> A_IWL<9111> A_IWL<9110> A_IWL<9109> A_IWL<9108> A_IWL<9107> A_IWL<9106> A_IWL<9105> A_IWL<9104> A_IWL<9103> A_IWL<9102> A_IWL<9101> A_IWL<9100> A_IWL<9099> A_IWL<9098> A_IWL<9097> A_IWL<9096> A_IWL<9095> A_IWL<9094> A_IWL<9093> A_IWL<9092> A_IWL<9091> A_IWL<9090> A_IWL<9089> A_IWL<9088> A_IWL<9087> A_IWL<9086> A_IWL<9085> A_IWL<9084> A_IWL<9083> A_IWL<9082> A_IWL<9081> A_IWL<9080> A_IWL<9079> A_IWL<9078> A_IWL<9077> A_IWL<9076> A_IWL<9075> A_IWL<9074> A_IWL<9073> A_IWL<9072> A_IWL<9071> A_IWL<9070> A_IWL<9069> A_IWL<9068> A_IWL<9067> A_IWL<9066> A_IWL<9065> A_IWL<9064> A_IWL<9063> A_IWL<9062> A_IWL<9061> A_IWL<9060> A_IWL<9059> A_IWL<9058> A_IWL<9057> A_IWL<9056> A_IWL<9055> A_IWL<9054> A_IWL<9053> A_IWL<9052> A_IWL<9051> A_IWL<9050> A_IWL<9049> A_IWL<9048> A_IWL<9047> A_IWL<9046> A_IWL<9045> A_IWL<9044> A_IWL<9043> A_IWL<9042> A_IWL<9041> A_IWL<9040> A_IWL<9039> A_IWL<9038> A_IWL<9037> A_IWL<9036> A_IWL<9035> A_IWL<9034> A_IWL<9033> A_IWL<9032> A_IWL<9031> A_IWL<9030> A_IWL<9029> A_IWL<9028> A_IWL<9027> A_IWL<9026> A_IWL<9025> A_IWL<9024> A_IWL<9023> A_IWL<9022> A_IWL<9021> A_IWL<9020> A_IWL<9019> A_IWL<9018> A_IWL<9017> A_IWL<9016> A_IWL<9015> A_IWL<9014> A_IWL<9013> A_IWL<9012> A_IWL<9011> A_IWL<9010> A_IWL<9009> A_IWL<9008> A_IWL<9007> A_IWL<9006> A_IWL<9005> A_IWL<9004> A_IWL<9003> A_IWL<9002> A_IWL<9001> A_IWL<9000> A_IWL<8999> A_IWL<8998> A_IWL<8997> A_IWL<8996> A_IWL<8995> A_IWL<8994> A_IWL<8993> A_IWL<8992> A_IWL<8991> A_IWL<8990> A_IWL<8989> A_IWL<8988> A_IWL<8987> A_IWL<8986> A_IWL<8985> A_IWL<8984> A_IWL<8983> A_IWL<8982> A_IWL<8981> A_IWL<8980> A_IWL<8979> A_IWL<8978> A_IWL<8977> A_IWL<8976> A_IWL<8975> A_IWL<8974> A_IWL<8973> A_IWL<8972> A_IWL<8971> A_IWL<8970> A_IWL<8969> A_IWL<8968> A_IWL<8967> A_IWL<8966> A_IWL<8965> A_IWL<8964> A_IWL<8963> A_IWL<8962> A_IWL<8961> A_IWL<8960> A_IWL<8959> A_IWL<8958> A_IWL<8957> A_IWL<8956> A_IWL<8955> A_IWL<8954> A_IWL<8953> A_IWL<8952> A_IWL<8951> A_IWL<8950> A_IWL<8949> A_IWL<8948> A_IWL<8947> A_IWL<8946> A_IWL<8945> A_IWL<8944> A_IWL<8943> A_IWL<8942> A_IWL<8941> A_IWL<8940> A_IWL<8939> A_IWL<8938> A_IWL<8937> A_IWL<8936> A_IWL<8935> A_IWL<8934> A_IWL<8933> A_IWL<8932> A_IWL<8931> A_IWL<8930> A_IWL<8929> A_IWL<8928> A_IWL<8927> A_IWL<8926> A_IWL<8925> A_IWL<8924> A_IWL<8923> A_IWL<8922> A_IWL<8921> A_IWL<8920> A_IWL<8919> A_IWL<8918> A_IWL<8917> A_IWL<8916> A_IWL<8915> A_IWL<8914> A_IWL<8913> A_IWL<8912> A_IWL<8911> A_IWL<8910> A_IWL<8909> A_IWL<8908> A_IWL<8907> A_IWL<8906> A_IWL<8905> A_IWL<8904> A_IWL<8903> A_IWL<8902> A_IWL<8901> A_IWL<8900> A_IWL<8899> A_IWL<8898> A_IWL<8897> A_IWL<8896> A_IWL<8895> A_IWL<8894> A_IWL<8893> A_IWL<8892> A_IWL<8891> A_IWL<8890> A_IWL<8889> A_IWL<8888> A_IWL<8887> A_IWL<8886> A_IWL<8885> A_IWL<8884> A_IWL<8883> A_IWL<8882> A_IWL<8881> A_IWL<8880> A_IWL<8879> A_IWL<8878> A_IWL<8877> A_IWL<8876> A_IWL<8875> A_IWL<8874> A_IWL<8873> A_IWL<8872> A_IWL<8871> A_IWL<8870> A_IWL<8869> A_IWL<8868> A_IWL<8867> A_IWL<8866> A_IWL<8865> A_IWL<8864> A_IWL<8863> A_IWL<8862> A_IWL<8861> A_IWL<8860> A_IWL<8859> A_IWL<8858> A_IWL<8857> A_IWL<8856> A_IWL<8855> A_IWL<8854> A_IWL<8853> A_IWL<8852> A_IWL<8851> A_IWL<8850> A_IWL<8849> A_IWL<8848> A_IWL<8847> A_IWL<8846> A_IWL<8845> A_IWL<8844> A_IWL<8843> A_IWL<8842> A_IWL<8841> A_IWL<8840> A_IWL<8839> A_IWL<8838> A_IWL<8837> A_IWL<8836> A_IWL<8835> A_IWL<8834> A_IWL<8833> A_IWL<8832> A_IWL<8831> A_IWL<8830> A_IWL<8829> A_IWL<8828> A_IWL<8827> A_IWL<8826> A_IWL<8825> A_IWL<8824> A_IWL<8823> A_IWL<8822> A_IWL<8821> A_IWL<8820> A_IWL<8819> A_IWL<8818> A_IWL<8817> A_IWL<8816> A_IWL<8815> A_IWL<8814> A_IWL<8813> A_IWL<8812> A_IWL<8811> A_IWL<8810> A_IWL<8809> A_IWL<8808> A_IWL<8807> A_IWL<8806> A_IWL<8805> A_IWL<8804> A_IWL<8803> A_IWL<8802> A_IWL<8801> A_IWL<8800> A_IWL<8799> A_IWL<8798> A_IWL<8797> A_IWL<8796> A_IWL<8795> A_IWL<8794> A_IWL<8793> A_IWL<8792> A_IWL<8791> A_IWL<8790> A_IWL<8789> A_IWL<8788> A_IWL<8787> A_IWL<8786> A_IWL<8785> A_IWL<8784> A_IWL<8783> A_IWL<8782> A_IWL<8781> A_IWL<8780> A_IWL<8779> A_IWL<8778> A_IWL<8777> A_IWL<8776> A_IWL<8775> A_IWL<8774> A_IWL<8773> A_IWL<8772> A_IWL<8771> A_IWL<8770> A_IWL<8769> A_IWL<8768> A_IWL<8767> A_IWL<8766> A_IWL<8765> A_IWL<8764> A_IWL<8763> A_IWL<8762> A_IWL<8761> A_IWL<8760> A_IWL<8759> A_IWL<8758> A_IWL<8757> A_IWL<8756> A_IWL<8755> A_IWL<8754> A_IWL<8753> A_IWL<8752> A_IWL<8751> A_IWL<8750> A_IWL<8749> A_IWL<8748> A_IWL<8747> A_IWL<8746> A_IWL<8745> A_IWL<8744> A_IWL<8743> A_IWL<8742> A_IWL<8741> A_IWL<8740> A_IWL<8739> A_IWL<8738> A_IWL<8737> A_IWL<8736> A_IWL<8735> A_IWL<8734> A_IWL<8733> A_IWL<8732> A_IWL<8731> A_IWL<8730> A_IWL<8729> A_IWL<8728> A_IWL<8727> A_IWL<8726> A_IWL<8725> A_IWL<8724> A_IWL<8723> A_IWL<8722> A_IWL<8721> A_IWL<8720> A_IWL<8719> A_IWL<8718> A_IWL<8717> A_IWL<8716> A_IWL<8715> A_IWL<8714> A_IWL<8713> A_IWL<8712> A_IWL<8711> A_IWL<8710> A_IWL<8709> A_IWL<8708> A_IWL<8707> A_IWL<8706> A_IWL<8705> A_IWL<8704> A_IWL<9727> A_IWL<9726> A_IWL<9725> A_IWL<9724> A_IWL<9723> A_IWL<9722> A_IWL<9721> A_IWL<9720> A_IWL<9719> A_IWL<9718> A_IWL<9717> A_IWL<9716> A_IWL<9715> A_IWL<9714> A_IWL<9713> A_IWL<9712> A_IWL<9711> A_IWL<9710> A_IWL<9709> A_IWL<9708> A_IWL<9707> A_IWL<9706> A_IWL<9705> A_IWL<9704> A_IWL<9703> A_IWL<9702> A_IWL<9701> A_IWL<9700> A_IWL<9699> A_IWL<9698> A_IWL<9697> A_IWL<9696> A_IWL<9695> A_IWL<9694> A_IWL<9693> A_IWL<9692> A_IWL<9691> A_IWL<9690> A_IWL<9689> A_IWL<9688> A_IWL<9687> A_IWL<9686> A_IWL<9685> A_IWL<9684> A_IWL<9683> A_IWL<9682> A_IWL<9681> A_IWL<9680> A_IWL<9679> A_IWL<9678> A_IWL<9677> A_IWL<9676> A_IWL<9675> A_IWL<9674> A_IWL<9673> A_IWL<9672> A_IWL<9671> A_IWL<9670> A_IWL<9669> A_IWL<9668> A_IWL<9667> A_IWL<9666> A_IWL<9665> A_IWL<9664> A_IWL<9663> A_IWL<9662> A_IWL<9661> A_IWL<9660> A_IWL<9659> A_IWL<9658> A_IWL<9657> A_IWL<9656> A_IWL<9655> A_IWL<9654> A_IWL<9653> A_IWL<9652> A_IWL<9651> A_IWL<9650> A_IWL<9649> A_IWL<9648> A_IWL<9647> A_IWL<9646> A_IWL<9645> A_IWL<9644> A_IWL<9643> A_IWL<9642> A_IWL<9641> A_IWL<9640> A_IWL<9639> A_IWL<9638> A_IWL<9637> A_IWL<9636> A_IWL<9635> A_IWL<9634> A_IWL<9633> A_IWL<9632> A_IWL<9631> A_IWL<9630> A_IWL<9629> A_IWL<9628> A_IWL<9627> A_IWL<9626> A_IWL<9625> A_IWL<9624> A_IWL<9623> A_IWL<9622> A_IWL<9621> A_IWL<9620> A_IWL<9619> A_IWL<9618> A_IWL<9617> A_IWL<9616> A_IWL<9615> A_IWL<9614> A_IWL<9613> A_IWL<9612> A_IWL<9611> A_IWL<9610> A_IWL<9609> A_IWL<9608> A_IWL<9607> A_IWL<9606> A_IWL<9605> A_IWL<9604> A_IWL<9603> A_IWL<9602> A_IWL<9601> A_IWL<9600> A_IWL<9599> A_IWL<9598> A_IWL<9597> A_IWL<9596> A_IWL<9595> A_IWL<9594> A_IWL<9593> A_IWL<9592> A_IWL<9591> A_IWL<9590> A_IWL<9589> A_IWL<9588> A_IWL<9587> A_IWL<9586> A_IWL<9585> A_IWL<9584> A_IWL<9583> A_IWL<9582> A_IWL<9581> A_IWL<9580> A_IWL<9579> A_IWL<9578> A_IWL<9577> A_IWL<9576> A_IWL<9575> A_IWL<9574> A_IWL<9573> A_IWL<9572> A_IWL<9571> A_IWL<9570> A_IWL<9569> A_IWL<9568> A_IWL<9567> A_IWL<9566> A_IWL<9565> A_IWL<9564> A_IWL<9563> A_IWL<9562> A_IWL<9561> A_IWL<9560> A_IWL<9559> A_IWL<9558> A_IWL<9557> A_IWL<9556> A_IWL<9555> A_IWL<9554> A_IWL<9553> A_IWL<9552> A_IWL<9551> A_IWL<9550> A_IWL<9549> A_IWL<9548> A_IWL<9547> A_IWL<9546> A_IWL<9545> A_IWL<9544> A_IWL<9543> A_IWL<9542> A_IWL<9541> A_IWL<9540> A_IWL<9539> A_IWL<9538> A_IWL<9537> A_IWL<9536> A_IWL<9535> A_IWL<9534> A_IWL<9533> A_IWL<9532> A_IWL<9531> A_IWL<9530> A_IWL<9529> A_IWL<9528> A_IWL<9527> A_IWL<9526> A_IWL<9525> A_IWL<9524> A_IWL<9523> A_IWL<9522> A_IWL<9521> A_IWL<9520> A_IWL<9519> A_IWL<9518> A_IWL<9517> A_IWL<9516> A_IWL<9515> A_IWL<9514> A_IWL<9513> A_IWL<9512> A_IWL<9511> A_IWL<9510> A_IWL<9509> A_IWL<9508> A_IWL<9507> A_IWL<9506> A_IWL<9505> A_IWL<9504> A_IWL<9503> A_IWL<9502> A_IWL<9501> A_IWL<9500> A_IWL<9499> A_IWL<9498> A_IWL<9497> A_IWL<9496> A_IWL<9495> A_IWL<9494> A_IWL<9493> A_IWL<9492> A_IWL<9491> A_IWL<9490> A_IWL<9489> A_IWL<9488> A_IWL<9487> A_IWL<9486> A_IWL<9485> A_IWL<9484> A_IWL<9483> A_IWL<9482> A_IWL<9481> A_IWL<9480> A_IWL<9479> A_IWL<9478> A_IWL<9477> A_IWL<9476> A_IWL<9475> A_IWL<9474> A_IWL<9473> A_IWL<9472> A_IWL<9471> A_IWL<9470> A_IWL<9469> A_IWL<9468> A_IWL<9467> A_IWL<9466> A_IWL<9465> A_IWL<9464> A_IWL<9463> A_IWL<9462> A_IWL<9461> A_IWL<9460> A_IWL<9459> A_IWL<9458> A_IWL<9457> A_IWL<9456> A_IWL<9455> A_IWL<9454> A_IWL<9453> A_IWL<9452> A_IWL<9451> A_IWL<9450> A_IWL<9449> A_IWL<9448> A_IWL<9447> A_IWL<9446> A_IWL<9445> A_IWL<9444> A_IWL<9443> A_IWL<9442> A_IWL<9441> A_IWL<9440> A_IWL<9439> A_IWL<9438> A_IWL<9437> A_IWL<9436> A_IWL<9435> A_IWL<9434> A_IWL<9433> A_IWL<9432> A_IWL<9431> A_IWL<9430> A_IWL<9429> A_IWL<9428> A_IWL<9427> A_IWL<9426> A_IWL<9425> A_IWL<9424> A_IWL<9423> A_IWL<9422> A_IWL<9421> A_IWL<9420> A_IWL<9419> A_IWL<9418> A_IWL<9417> A_IWL<9416> A_IWL<9415> A_IWL<9414> A_IWL<9413> A_IWL<9412> A_IWL<9411> A_IWL<9410> A_IWL<9409> A_IWL<9408> A_IWL<9407> A_IWL<9406> A_IWL<9405> A_IWL<9404> A_IWL<9403> A_IWL<9402> A_IWL<9401> A_IWL<9400> A_IWL<9399> A_IWL<9398> A_IWL<9397> A_IWL<9396> A_IWL<9395> A_IWL<9394> A_IWL<9393> A_IWL<9392> A_IWL<9391> A_IWL<9390> A_IWL<9389> A_IWL<9388> A_IWL<9387> A_IWL<9386> A_IWL<9385> A_IWL<9384> A_IWL<9383> A_IWL<9382> A_IWL<9381> A_IWL<9380> A_IWL<9379> A_IWL<9378> A_IWL<9377> A_IWL<9376> A_IWL<9375> A_IWL<9374> A_IWL<9373> A_IWL<9372> A_IWL<9371> A_IWL<9370> A_IWL<9369> A_IWL<9368> A_IWL<9367> A_IWL<9366> A_IWL<9365> A_IWL<9364> A_IWL<9363> A_IWL<9362> A_IWL<9361> A_IWL<9360> A_IWL<9359> A_IWL<9358> A_IWL<9357> A_IWL<9356> A_IWL<9355> A_IWL<9354> A_IWL<9353> A_IWL<9352> A_IWL<9351> A_IWL<9350> A_IWL<9349> A_IWL<9348> A_IWL<9347> A_IWL<9346> A_IWL<9345> A_IWL<9344> A_IWL<9343> A_IWL<9342> A_IWL<9341> A_IWL<9340> A_IWL<9339> A_IWL<9338> A_IWL<9337> A_IWL<9336> A_IWL<9335> A_IWL<9334> A_IWL<9333> A_IWL<9332> A_IWL<9331> A_IWL<9330> A_IWL<9329> A_IWL<9328> A_IWL<9327> A_IWL<9326> A_IWL<9325> A_IWL<9324> A_IWL<9323> A_IWL<9322> A_IWL<9321> A_IWL<9320> A_IWL<9319> A_IWL<9318> A_IWL<9317> A_IWL<9316> A_IWL<9315> A_IWL<9314> A_IWL<9313> A_IWL<9312> A_IWL<9311> A_IWL<9310> A_IWL<9309> A_IWL<9308> A_IWL<9307> A_IWL<9306> A_IWL<9305> A_IWL<9304> A_IWL<9303> A_IWL<9302> A_IWL<9301> A_IWL<9300> A_IWL<9299> A_IWL<9298> A_IWL<9297> A_IWL<9296> A_IWL<9295> A_IWL<9294> A_IWL<9293> A_IWL<9292> A_IWL<9291> A_IWL<9290> A_IWL<9289> A_IWL<9288> A_IWL<9287> A_IWL<9286> A_IWL<9285> A_IWL<9284> A_IWL<9283> A_IWL<9282> A_IWL<9281> A_IWL<9280> A_IWL<9279> A_IWL<9278> A_IWL<9277> A_IWL<9276> A_IWL<9275> A_IWL<9274> A_IWL<9273> A_IWL<9272> A_IWL<9271> A_IWL<9270> A_IWL<9269> A_IWL<9268> A_IWL<9267> A_IWL<9266> A_IWL<9265> A_IWL<9264> A_IWL<9263> A_IWL<9262> A_IWL<9261> A_IWL<9260> A_IWL<9259> A_IWL<9258> A_IWL<9257> A_IWL<9256> A_IWL<9255> A_IWL<9254> A_IWL<9253> A_IWL<9252> A_IWL<9251> A_IWL<9250> A_IWL<9249> A_IWL<9248> A_IWL<9247> A_IWL<9246> A_IWL<9245> A_IWL<9244> A_IWL<9243> A_IWL<9242> A_IWL<9241> A_IWL<9240> A_IWL<9239> A_IWL<9238> A_IWL<9237> A_IWL<9236> A_IWL<9235> A_IWL<9234> A_IWL<9233> A_IWL<9232> A_IWL<9231> A_IWL<9230> A_IWL<9229> A_IWL<9228> A_IWL<9227> A_IWL<9226> A_IWL<9225> A_IWL<9224> A_IWL<9223> A_IWL<9222> A_IWL<9221> A_IWL<9220> A_IWL<9219> A_IWL<9218> A_IWL<9217> A_IWL<9216> VDD_CORE VSS / RM_IHPSG13_8192x32_c4_1P_COLUMN_pcell_0 +XCOL<17> A_BLC<35> A_BLC<34> A_BLC_TOP<35> A_BLC_TOP<34> A_BLT<35> A_BLT<34> A_BLT_TOP<35> A_BLT_TOP<34> A_IWL<8703> A_IWL<8702> A_IWL<8701> A_IWL<8700> A_IWL<8699> A_IWL<8698> A_IWL<8697> A_IWL<8696> A_IWL<8695> A_IWL<8694> A_IWL<8693> A_IWL<8692> A_IWL<8691> A_IWL<8690> A_IWL<8689> A_IWL<8688> A_IWL<8687> A_IWL<8686> A_IWL<8685> A_IWL<8684> A_IWL<8683> A_IWL<8682> A_IWL<8681> A_IWL<8680> A_IWL<8679> A_IWL<8678> A_IWL<8677> A_IWL<8676> A_IWL<8675> A_IWL<8674> A_IWL<8673> A_IWL<8672> A_IWL<8671> A_IWL<8670> A_IWL<8669> A_IWL<8668> A_IWL<8667> A_IWL<8666> A_IWL<8665> A_IWL<8664> A_IWL<8663> A_IWL<8662> A_IWL<8661> A_IWL<8660> A_IWL<8659> A_IWL<8658> A_IWL<8657> A_IWL<8656> A_IWL<8655> A_IWL<8654> A_IWL<8653> A_IWL<8652> A_IWL<8651> A_IWL<8650> A_IWL<8649> A_IWL<8648> A_IWL<8647> A_IWL<8646> A_IWL<8645> A_IWL<8644> A_IWL<8643> A_IWL<8642> A_IWL<8641> A_IWL<8640> A_IWL<8639> A_IWL<8638> A_IWL<8637> A_IWL<8636> A_IWL<8635> A_IWL<8634> A_IWL<8633> A_IWL<8632> A_IWL<8631> A_IWL<8630> A_IWL<8629> A_IWL<8628> A_IWL<8627> A_IWL<8626> A_IWL<8625> A_IWL<8624> A_IWL<8623> A_IWL<8622> A_IWL<8621> A_IWL<8620> A_IWL<8619> A_IWL<8618> A_IWL<8617> A_IWL<8616> A_IWL<8615> A_IWL<8614> A_IWL<8613> A_IWL<8612> A_IWL<8611> A_IWL<8610> A_IWL<8609> A_IWL<8608> A_IWL<8607> A_IWL<8606> A_IWL<8605> A_IWL<8604> A_IWL<8603> A_IWL<8602> A_IWL<8601> A_IWL<8600> A_IWL<8599> A_IWL<8598> A_IWL<8597> A_IWL<8596> A_IWL<8595> A_IWL<8594> A_IWL<8593> A_IWL<8592> A_IWL<8591> A_IWL<8590> A_IWL<8589> A_IWL<8588> A_IWL<8587> A_IWL<8586> A_IWL<8585> A_IWL<8584> A_IWL<8583> A_IWL<8582> A_IWL<8581> A_IWL<8580> A_IWL<8579> A_IWL<8578> A_IWL<8577> A_IWL<8576> A_IWL<8575> A_IWL<8574> A_IWL<8573> A_IWL<8572> A_IWL<8571> A_IWL<8570> A_IWL<8569> A_IWL<8568> A_IWL<8567> A_IWL<8566> A_IWL<8565> A_IWL<8564> A_IWL<8563> A_IWL<8562> A_IWL<8561> A_IWL<8560> A_IWL<8559> A_IWL<8558> A_IWL<8557> A_IWL<8556> A_IWL<8555> A_IWL<8554> A_IWL<8553> A_IWL<8552> A_IWL<8551> A_IWL<8550> A_IWL<8549> A_IWL<8548> A_IWL<8547> A_IWL<8546> A_IWL<8545> A_IWL<8544> A_IWL<8543> A_IWL<8542> A_IWL<8541> A_IWL<8540> A_IWL<8539> A_IWL<8538> A_IWL<8537> A_IWL<8536> A_IWL<8535> A_IWL<8534> A_IWL<8533> A_IWL<8532> A_IWL<8531> A_IWL<8530> A_IWL<8529> A_IWL<8528> A_IWL<8527> A_IWL<8526> A_IWL<8525> A_IWL<8524> A_IWL<8523> A_IWL<8522> A_IWL<8521> A_IWL<8520> A_IWL<8519> A_IWL<8518> A_IWL<8517> A_IWL<8516> A_IWL<8515> A_IWL<8514> A_IWL<8513> A_IWL<8512> A_IWL<8511> A_IWL<8510> A_IWL<8509> A_IWL<8508> A_IWL<8507> A_IWL<8506> A_IWL<8505> A_IWL<8504> A_IWL<8503> A_IWL<8502> A_IWL<8501> A_IWL<8500> A_IWL<8499> A_IWL<8498> A_IWL<8497> A_IWL<8496> A_IWL<8495> A_IWL<8494> A_IWL<8493> A_IWL<8492> A_IWL<8491> A_IWL<8490> A_IWL<8489> A_IWL<8488> A_IWL<8487> A_IWL<8486> A_IWL<8485> A_IWL<8484> A_IWL<8483> A_IWL<8482> A_IWL<8481> A_IWL<8480> A_IWL<8479> A_IWL<8478> A_IWL<8477> A_IWL<8476> A_IWL<8475> A_IWL<8474> A_IWL<8473> A_IWL<8472> A_IWL<8471> A_IWL<8470> A_IWL<8469> A_IWL<8468> A_IWL<8467> A_IWL<8466> A_IWL<8465> A_IWL<8464> A_IWL<8463> A_IWL<8462> A_IWL<8461> A_IWL<8460> A_IWL<8459> A_IWL<8458> A_IWL<8457> A_IWL<8456> A_IWL<8455> A_IWL<8454> A_IWL<8453> A_IWL<8452> A_IWL<8451> A_IWL<8450> A_IWL<8449> A_IWL<8448> A_IWL<8447> A_IWL<8446> A_IWL<8445> A_IWL<8444> A_IWL<8443> A_IWL<8442> A_IWL<8441> A_IWL<8440> A_IWL<8439> A_IWL<8438> A_IWL<8437> A_IWL<8436> A_IWL<8435> A_IWL<8434> A_IWL<8433> A_IWL<8432> A_IWL<8431> A_IWL<8430> A_IWL<8429> A_IWL<8428> A_IWL<8427> A_IWL<8426> A_IWL<8425> A_IWL<8424> A_IWL<8423> A_IWL<8422> A_IWL<8421> A_IWL<8420> A_IWL<8419> A_IWL<8418> A_IWL<8417> A_IWL<8416> A_IWL<8415> A_IWL<8414> A_IWL<8413> A_IWL<8412> A_IWL<8411> A_IWL<8410> A_IWL<8409> A_IWL<8408> A_IWL<8407> A_IWL<8406> A_IWL<8405> A_IWL<8404> A_IWL<8403> A_IWL<8402> A_IWL<8401> A_IWL<8400> A_IWL<8399> A_IWL<8398> A_IWL<8397> A_IWL<8396> A_IWL<8395> A_IWL<8394> A_IWL<8393> A_IWL<8392> A_IWL<8391> A_IWL<8390> A_IWL<8389> A_IWL<8388> A_IWL<8387> A_IWL<8386> A_IWL<8385> A_IWL<8384> A_IWL<8383> A_IWL<8382> A_IWL<8381> A_IWL<8380> A_IWL<8379> A_IWL<8378> A_IWL<8377> A_IWL<8376> A_IWL<8375> A_IWL<8374> A_IWL<8373> A_IWL<8372> A_IWL<8371> A_IWL<8370> A_IWL<8369> A_IWL<8368> A_IWL<8367> A_IWL<8366> A_IWL<8365> A_IWL<8364> A_IWL<8363> A_IWL<8362> A_IWL<8361> A_IWL<8360> A_IWL<8359> A_IWL<8358> A_IWL<8357> A_IWL<8356> A_IWL<8355> A_IWL<8354> A_IWL<8353> A_IWL<8352> A_IWL<8351> A_IWL<8350> A_IWL<8349> A_IWL<8348> A_IWL<8347> A_IWL<8346> A_IWL<8345> A_IWL<8344> A_IWL<8343> A_IWL<8342> A_IWL<8341> A_IWL<8340> A_IWL<8339> A_IWL<8338> A_IWL<8337> A_IWL<8336> A_IWL<8335> A_IWL<8334> A_IWL<8333> A_IWL<8332> A_IWL<8331> A_IWL<8330> A_IWL<8329> A_IWL<8328> A_IWL<8327> A_IWL<8326> A_IWL<8325> A_IWL<8324> A_IWL<8323> A_IWL<8322> A_IWL<8321> A_IWL<8320> A_IWL<8319> A_IWL<8318> A_IWL<8317> A_IWL<8316> A_IWL<8315> A_IWL<8314> A_IWL<8313> A_IWL<8312> A_IWL<8311> A_IWL<8310> A_IWL<8309> A_IWL<8308> A_IWL<8307> A_IWL<8306> A_IWL<8305> A_IWL<8304> A_IWL<8303> A_IWL<8302> A_IWL<8301> A_IWL<8300> A_IWL<8299> A_IWL<8298> A_IWL<8297> A_IWL<8296> A_IWL<8295> A_IWL<8294> A_IWL<8293> A_IWL<8292> A_IWL<8291> A_IWL<8290> A_IWL<8289> A_IWL<8288> A_IWL<8287> A_IWL<8286> A_IWL<8285> A_IWL<8284> A_IWL<8283> A_IWL<8282> A_IWL<8281> A_IWL<8280> A_IWL<8279> A_IWL<8278> A_IWL<8277> A_IWL<8276> A_IWL<8275> A_IWL<8274> A_IWL<8273> A_IWL<8272> A_IWL<8271> A_IWL<8270> A_IWL<8269> A_IWL<8268> A_IWL<8267> A_IWL<8266> A_IWL<8265> A_IWL<8264> A_IWL<8263> A_IWL<8262> A_IWL<8261> A_IWL<8260> A_IWL<8259> A_IWL<8258> A_IWL<8257> A_IWL<8256> A_IWL<8255> A_IWL<8254> A_IWL<8253> A_IWL<8252> A_IWL<8251> A_IWL<8250> A_IWL<8249> A_IWL<8248> A_IWL<8247> A_IWL<8246> A_IWL<8245> A_IWL<8244> A_IWL<8243> A_IWL<8242> A_IWL<8241> A_IWL<8240> A_IWL<8239> A_IWL<8238> A_IWL<8237> A_IWL<8236> A_IWL<8235> A_IWL<8234> A_IWL<8233> A_IWL<8232> A_IWL<8231> A_IWL<8230> A_IWL<8229> A_IWL<8228> A_IWL<8227> A_IWL<8226> A_IWL<8225> A_IWL<8224> A_IWL<8223> A_IWL<8222> A_IWL<8221> A_IWL<8220> A_IWL<8219> A_IWL<8218> A_IWL<8217> A_IWL<8216> A_IWL<8215> A_IWL<8214> A_IWL<8213> A_IWL<8212> A_IWL<8211> A_IWL<8210> A_IWL<8209> A_IWL<8208> A_IWL<8207> A_IWL<8206> A_IWL<8205> A_IWL<8204> A_IWL<8203> A_IWL<8202> A_IWL<8201> A_IWL<8200> A_IWL<8199> A_IWL<8198> A_IWL<8197> A_IWL<8196> A_IWL<8195> A_IWL<8194> A_IWL<8193> A_IWL<8192> A_IWL<9215> A_IWL<9214> A_IWL<9213> A_IWL<9212> A_IWL<9211> A_IWL<9210> A_IWL<9209> A_IWL<9208> A_IWL<9207> A_IWL<9206> A_IWL<9205> A_IWL<9204> A_IWL<9203> A_IWL<9202> A_IWL<9201> A_IWL<9200> A_IWL<9199> A_IWL<9198> A_IWL<9197> A_IWL<9196> A_IWL<9195> A_IWL<9194> A_IWL<9193> A_IWL<9192> A_IWL<9191> A_IWL<9190> A_IWL<9189> A_IWL<9188> A_IWL<9187> A_IWL<9186> A_IWL<9185> A_IWL<9184> A_IWL<9183> A_IWL<9182> A_IWL<9181> A_IWL<9180> A_IWL<9179> A_IWL<9178> A_IWL<9177> A_IWL<9176> A_IWL<9175> A_IWL<9174> A_IWL<9173> A_IWL<9172> A_IWL<9171> A_IWL<9170> A_IWL<9169> A_IWL<9168> A_IWL<9167> A_IWL<9166> A_IWL<9165> A_IWL<9164> A_IWL<9163> A_IWL<9162> A_IWL<9161> A_IWL<9160> A_IWL<9159> A_IWL<9158> A_IWL<9157> A_IWL<9156> A_IWL<9155> A_IWL<9154> A_IWL<9153> A_IWL<9152> A_IWL<9151> A_IWL<9150> A_IWL<9149> A_IWL<9148> A_IWL<9147> A_IWL<9146> A_IWL<9145> A_IWL<9144> A_IWL<9143> A_IWL<9142> A_IWL<9141> A_IWL<9140> A_IWL<9139> A_IWL<9138> A_IWL<9137> A_IWL<9136> A_IWL<9135> A_IWL<9134> A_IWL<9133> A_IWL<9132> A_IWL<9131> A_IWL<9130> A_IWL<9129> A_IWL<9128> A_IWL<9127> A_IWL<9126> A_IWL<9125> A_IWL<9124> A_IWL<9123> A_IWL<9122> A_IWL<9121> A_IWL<9120> A_IWL<9119> A_IWL<9118> A_IWL<9117> A_IWL<9116> A_IWL<9115> A_IWL<9114> A_IWL<9113> A_IWL<9112> A_IWL<9111> A_IWL<9110> A_IWL<9109> A_IWL<9108> A_IWL<9107> A_IWL<9106> A_IWL<9105> A_IWL<9104> A_IWL<9103> A_IWL<9102> A_IWL<9101> A_IWL<9100> A_IWL<9099> A_IWL<9098> A_IWL<9097> A_IWL<9096> A_IWL<9095> A_IWL<9094> A_IWL<9093> A_IWL<9092> A_IWL<9091> A_IWL<9090> A_IWL<9089> A_IWL<9088> A_IWL<9087> A_IWL<9086> A_IWL<9085> A_IWL<9084> A_IWL<9083> A_IWL<9082> A_IWL<9081> A_IWL<9080> A_IWL<9079> A_IWL<9078> A_IWL<9077> A_IWL<9076> A_IWL<9075> A_IWL<9074> A_IWL<9073> A_IWL<9072> A_IWL<9071> A_IWL<9070> A_IWL<9069> A_IWL<9068> A_IWL<9067> A_IWL<9066> A_IWL<9065> A_IWL<9064> A_IWL<9063> A_IWL<9062> A_IWL<9061> A_IWL<9060> A_IWL<9059> A_IWL<9058> A_IWL<9057> A_IWL<9056> A_IWL<9055> A_IWL<9054> A_IWL<9053> A_IWL<9052> A_IWL<9051> A_IWL<9050> A_IWL<9049> A_IWL<9048> A_IWL<9047> A_IWL<9046> A_IWL<9045> A_IWL<9044> A_IWL<9043> A_IWL<9042> A_IWL<9041> A_IWL<9040> A_IWL<9039> A_IWL<9038> A_IWL<9037> A_IWL<9036> A_IWL<9035> A_IWL<9034> A_IWL<9033> A_IWL<9032> A_IWL<9031> A_IWL<9030> A_IWL<9029> A_IWL<9028> A_IWL<9027> A_IWL<9026> A_IWL<9025> A_IWL<9024> A_IWL<9023> A_IWL<9022> A_IWL<9021> A_IWL<9020> A_IWL<9019> A_IWL<9018> A_IWL<9017> A_IWL<9016> A_IWL<9015> A_IWL<9014> A_IWL<9013> A_IWL<9012> A_IWL<9011> A_IWL<9010> A_IWL<9009> A_IWL<9008> A_IWL<9007> A_IWL<9006> A_IWL<9005> A_IWL<9004> A_IWL<9003> A_IWL<9002> A_IWL<9001> A_IWL<9000> A_IWL<8999> A_IWL<8998> A_IWL<8997> A_IWL<8996> A_IWL<8995> A_IWL<8994> A_IWL<8993> A_IWL<8992> A_IWL<8991> A_IWL<8990> A_IWL<8989> A_IWL<8988> A_IWL<8987> A_IWL<8986> A_IWL<8985> A_IWL<8984> A_IWL<8983> A_IWL<8982> A_IWL<8981> A_IWL<8980> A_IWL<8979> A_IWL<8978> A_IWL<8977> A_IWL<8976> A_IWL<8975> A_IWL<8974> A_IWL<8973> A_IWL<8972> A_IWL<8971> A_IWL<8970> A_IWL<8969> A_IWL<8968> A_IWL<8967> A_IWL<8966> A_IWL<8965> A_IWL<8964> A_IWL<8963> A_IWL<8962> A_IWL<8961> A_IWL<8960> A_IWL<8959> A_IWL<8958> A_IWL<8957> A_IWL<8956> A_IWL<8955> A_IWL<8954> A_IWL<8953> A_IWL<8952> A_IWL<8951> A_IWL<8950> A_IWL<8949> A_IWL<8948> A_IWL<8947> A_IWL<8946> A_IWL<8945> A_IWL<8944> A_IWL<8943> A_IWL<8942> A_IWL<8941> A_IWL<8940> A_IWL<8939> A_IWL<8938> A_IWL<8937> A_IWL<8936> A_IWL<8935> A_IWL<8934> A_IWL<8933> A_IWL<8932> A_IWL<8931> A_IWL<8930> A_IWL<8929> A_IWL<8928> A_IWL<8927> A_IWL<8926> A_IWL<8925> A_IWL<8924> A_IWL<8923> A_IWL<8922> A_IWL<8921> A_IWL<8920> A_IWL<8919> A_IWL<8918> A_IWL<8917> A_IWL<8916> A_IWL<8915> A_IWL<8914> A_IWL<8913> A_IWL<8912> A_IWL<8911> A_IWL<8910> A_IWL<8909> A_IWL<8908> A_IWL<8907> A_IWL<8906> A_IWL<8905> A_IWL<8904> A_IWL<8903> A_IWL<8902> A_IWL<8901> A_IWL<8900> A_IWL<8899> A_IWL<8898> A_IWL<8897> A_IWL<8896> A_IWL<8895> A_IWL<8894> A_IWL<8893> A_IWL<8892> A_IWL<8891> A_IWL<8890> A_IWL<8889> A_IWL<8888> A_IWL<8887> A_IWL<8886> A_IWL<8885> A_IWL<8884> A_IWL<8883> A_IWL<8882> A_IWL<8881> A_IWL<8880> A_IWL<8879> A_IWL<8878> A_IWL<8877> A_IWL<8876> A_IWL<8875> A_IWL<8874> A_IWL<8873> A_IWL<8872> A_IWL<8871> A_IWL<8870> A_IWL<8869> A_IWL<8868> A_IWL<8867> A_IWL<8866> A_IWL<8865> A_IWL<8864> A_IWL<8863> A_IWL<8862> A_IWL<8861> A_IWL<8860> A_IWL<8859> A_IWL<8858> A_IWL<8857> A_IWL<8856> A_IWL<8855> A_IWL<8854> A_IWL<8853> A_IWL<8852> A_IWL<8851> A_IWL<8850> A_IWL<8849> A_IWL<8848> A_IWL<8847> A_IWL<8846> A_IWL<8845> A_IWL<8844> A_IWL<8843> A_IWL<8842> A_IWL<8841> A_IWL<8840> A_IWL<8839> A_IWL<8838> A_IWL<8837> A_IWL<8836> A_IWL<8835> A_IWL<8834> A_IWL<8833> A_IWL<8832> A_IWL<8831> A_IWL<8830> A_IWL<8829> A_IWL<8828> A_IWL<8827> A_IWL<8826> A_IWL<8825> A_IWL<8824> A_IWL<8823> A_IWL<8822> A_IWL<8821> A_IWL<8820> A_IWL<8819> A_IWL<8818> A_IWL<8817> A_IWL<8816> A_IWL<8815> A_IWL<8814> A_IWL<8813> A_IWL<8812> A_IWL<8811> A_IWL<8810> A_IWL<8809> A_IWL<8808> A_IWL<8807> A_IWL<8806> A_IWL<8805> A_IWL<8804> A_IWL<8803> A_IWL<8802> A_IWL<8801> A_IWL<8800> A_IWL<8799> A_IWL<8798> A_IWL<8797> A_IWL<8796> A_IWL<8795> A_IWL<8794> A_IWL<8793> A_IWL<8792> A_IWL<8791> A_IWL<8790> A_IWL<8789> A_IWL<8788> A_IWL<8787> A_IWL<8786> A_IWL<8785> A_IWL<8784> A_IWL<8783> A_IWL<8782> A_IWL<8781> A_IWL<8780> A_IWL<8779> A_IWL<8778> A_IWL<8777> A_IWL<8776> A_IWL<8775> A_IWL<8774> A_IWL<8773> A_IWL<8772> A_IWL<8771> A_IWL<8770> A_IWL<8769> A_IWL<8768> A_IWL<8767> A_IWL<8766> A_IWL<8765> A_IWL<8764> A_IWL<8763> A_IWL<8762> A_IWL<8761> A_IWL<8760> A_IWL<8759> A_IWL<8758> A_IWL<8757> A_IWL<8756> A_IWL<8755> A_IWL<8754> A_IWL<8753> A_IWL<8752> A_IWL<8751> A_IWL<8750> A_IWL<8749> A_IWL<8748> A_IWL<8747> A_IWL<8746> A_IWL<8745> A_IWL<8744> A_IWL<8743> A_IWL<8742> A_IWL<8741> A_IWL<8740> A_IWL<8739> A_IWL<8738> A_IWL<8737> A_IWL<8736> A_IWL<8735> A_IWL<8734> A_IWL<8733> A_IWL<8732> A_IWL<8731> A_IWL<8730> A_IWL<8729> A_IWL<8728> A_IWL<8727> A_IWL<8726> A_IWL<8725> A_IWL<8724> A_IWL<8723> A_IWL<8722> A_IWL<8721> A_IWL<8720> A_IWL<8719> A_IWL<8718> A_IWL<8717> A_IWL<8716> A_IWL<8715> A_IWL<8714> A_IWL<8713> A_IWL<8712> A_IWL<8711> A_IWL<8710> A_IWL<8709> A_IWL<8708> A_IWL<8707> A_IWL<8706> A_IWL<8705> A_IWL<8704> VDD_CORE VSS / RM_IHPSG13_8192x32_c4_1P_COLUMN_pcell_0 +XCOL<16> A_BLC<33> A_BLC<32> A_BLC_TOP<33> A_BLC_TOP<32> A_BLT<33> A_BLT<32> A_BLT_TOP<33> A_BLT_TOP<32> A_IWL<8191> A_IWL<8190> A_IWL<8189> A_IWL<8188> A_IWL<8187> A_IWL<8186> A_IWL<8185> A_IWL<8184> A_IWL<8183> A_IWL<8182> A_IWL<8181> A_IWL<8180> A_IWL<8179> A_IWL<8178> A_IWL<8177> A_IWL<8176> A_IWL<8175> A_IWL<8174> A_IWL<8173> A_IWL<8172> A_IWL<8171> A_IWL<8170> A_IWL<8169> A_IWL<8168> A_IWL<8167> A_IWL<8166> A_IWL<8165> A_IWL<8164> A_IWL<8163> A_IWL<8162> A_IWL<8161> A_IWL<8160> A_IWL<8159> A_IWL<8158> A_IWL<8157> A_IWL<8156> A_IWL<8155> A_IWL<8154> A_IWL<8153> A_IWL<8152> A_IWL<8151> A_IWL<8150> A_IWL<8149> A_IWL<8148> A_IWL<8147> A_IWL<8146> A_IWL<8145> A_IWL<8144> A_IWL<8143> A_IWL<8142> A_IWL<8141> A_IWL<8140> A_IWL<8139> A_IWL<8138> A_IWL<8137> A_IWL<8136> A_IWL<8135> A_IWL<8134> A_IWL<8133> A_IWL<8132> A_IWL<8131> A_IWL<8130> A_IWL<8129> A_IWL<8128> A_IWL<8127> A_IWL<8126> A_IWL<8125> A_IWL<8124> A_IWL<8123> A_IWL<8122> A_IWL<8121> A_IWL<8120> A_IWL<8119> A_IWL<8118> A_IWL<8117> A_IWL<8116> A_IWL<8115> A_IWL<8114> A_IWL<8113> A_IWL<8112> A_IWL<8111> A_IWL<8110> A_IWL<8109> A_IWL<8108> A_IWL<8107> A_IWL<8106> A_IWL<8105> A_IWL<8104> A_IWL<8103> A_IWL<8102> A_IWL<8101> A_IWL<8100> A_IWL<8099> A_IWL<8098> A_IWL<8097> A_IWL<8096> A_IWL<8095> A_IWL<8094> A_IWL<8093> A_IWL<8092> A_IWL<8091> A_IWL<8090> A_IWL<8089> A_IWL<8088> A_IWL<8087> A_IWL<8086> A_IWL<8085> A_IWL<8084> A_IWL<8083> A_IWL<8082> A_IWL<8081> A_IWL<8080> A_IWL<8079> A_IWL<8078> A_IWL<8077> A_IWL<8076> A_IWL<8075> A_IWL<8074> A_IWL<8073> A_IWL<8072> A_IWL<8071> A_IWL<8070> A_IWL<8069> A_IWL<8068> A_IWL<8067> A_IWL<8066> A_IWL<8065> A_IWL<8064> A_IWL<8063> A_IWL<8062> A_IWL<8061> A_IWL<8060> A_IWL<8059> A_IWL<8058> A_IWL<8057> A_IWL<8056> A_IWL<8055> A_IWL<8054> A_IWL<8053> A_IWL<8052> A_IWL<8051> A_IWL<8050> A_IWL<8049> A_IWL<8048> A_IWL<8047> A_IWL<8046> A_IWL<8045> A_IWL<8044> A_IWL<8043> A_IWL<8042> A_IWL<8041> A_IWL<8040> A_IWL<8039> A_IWL<8038> A_IWL<8037> A_IWL<8036> A_IWL<8035> A_IWL<8034> A_IWL<8033> A_IWL<8032> A_IWL<8031> A_IWL<8030> A_IWL<8029> A_IWL<8028> A_IWL<8027> A_IWL<8026> A_IWL<8025> A_IWL<8024> A_IWL<8023> A_IWL<8022> A_IWL<8021> A_IWL<8020> A_IWL<8019> A_IWL<8018> A_IWL<8017> A_IWL<8016> A_IWL<8015> A_IWL<8014> A_IWL<8013> A_IWL<8012> A_IWL<8011> A_IWL<8010> A_IWL<8009> A_IWL<8008> A_IWL<8007> A_IWL<8006> A_IWL<8005> A_IWL<8004> A_IWL<8003> A_IWL<8002> A_IWL<8001> A_IWL<8000> A_IWL<7999> A_IWL<7998> A_IWL<7997> A_IWL<7996> A_IWL<7995> A_IWL<7994> A_IWL<7993> A_IWL<7992> A_IWL<7991> A_IWL<7990> A_IWL<7989> A_IWL<7988> A_IWL<7987> A_IWL<7986> A_IWL<7985> A_IWL<7984> A_IWL<7983> A_IWL<7982> A_IWL<7981> A_IWL<7980> A_IWL<7979> A_IWL<7978> A_IWL<7977> A_IWL<7976> A_IWL<7975> A_IWL<7974> A_IWL<7973> A_IWL<7972> A_IWL<7971> A_IWL<7970> A_IWL<7969> A_IWL<7968> A_IWL<7967> A_IWL<7966> A_IWL<7965> A_IWL<7964> A_IWL<7963> A_IWL<7962> A_IWL<7961> A_IWL<7960> A_IWL<7959> A_IWL<7958> A_IWL<7957> A_IWL<7956> A_IWL<7955> A_IWL<7954> A_IWL<7953> A_IWL<7952> A_IWL<7951> A_IWL<7950> A_IWL<7949> A_IWL<7948> A_IWL<7947> A_IWL<7946> A_IWL<7945> A_IWL<7944> A_IWL<7943> A_IWL<7942> A_IWL<7941> A_IWL<7940> A_IWL<7939> A_IWL<7938> A_IWL<7937> A_IWL<7936> A_IWL<7935> A_IWL<7934> A_IWL<7933> A_IWL<7932> A_IWL<7931> A_IWL<7930> A_IWL<7929> A_IWL<7928> A_IWL<7927> A_IWL<7926> A_IWL<7925> A_IWL<7924> A_IWL<7923> A_IWL<7922> A_IWL<7921> A_IWL<7920> A_IWL<7919> A_IWL<7918> A_IWL<7917> A_IWL<7916> A_IWL<7915> A_IWL<7914> A_IWL<7913> A_IWL<7912> A_IWL<7911> A_IWL<7910> A_IWL<7909> A_IWL<7908> A_IWL<7907> A_IWL<7906> A_IWL<7905> A_IWL<7904> A_IWL<7903> A_IWL<7902> A_IWL<7901> A_IWL<7900> A_IWL<7899> A_IWL<7898> A_IWL<7897> A_IWL<7896> A_IWL<7895> A_IWL<7894> A_IWL<7893> A_IWL<7892> A_IWL<7891> A_IWL<7890> A_IWL<7889> A_IWL<7888> A_IWL<7887> A_IWL<7886> A_IWL<7885> A_IWL<7884> A_IWL<7883> A_IWL<7882> A_IWL<7881> A_IWL<7880> A_IWL<7879> A_IWL<7878> A_IWL<7877> A_IWL<7876> A_IWL<7875> A_IWL<7874> A_IWL<7873> A_IWL<7872> A_IWL<7871> A_IWL<7870> A_IWL<7869> A_IWL<7868> A_IWL<7867> A_IWL<7866> A_IWL<7865> A_IWL<7864> A_IWL<7863> A_IWL<7862> A_IWL<7861> A_IWL<7860> A_IWL<7859> A_IWL<7858> A_IWL<7857> A_IWL<7856> A_IWL<7855> A_IWL<7854> A_IWL<7853> A_IWL<7852> A_IWL<7851> A_IWL<7850> A_IWL<7849> A_IWL<7848> A_IWL<7847> A_IWL<7846> A_IWL<7845> A_IWL<7844> A_IWL<7843> A_IWL<7842> A_IWL<7841> A_IWL<7840> A_IWL<7839> A_IWL<7838> A_IWL<7837> A_IWL<7836> A_IWL<7835> A_IWL<7834> A_IWL<7833> A_IWL<7832> A_IWL<7831> A_IWL<7830> A_IWL<7829> A_IWL<7828> A_IWL<7827> A_IWL<7826> A_IWL<7825> A_IWL<7824> A_IWL<7823> A_IWL<7822> A_IWL<7821> A_IWL<7820> A_IWL<7819> A_IWL<7818> A_IWL<7817> A_IWL<7816> A_IWL<7815> A_IWL<7814> A_IWL<7813> A_IWL<7812> A_IWL<7811> A_IWL<7810> A_IWL<7809> A_IWL<7808> A_IWL<7807> A_IWL<7806> A_IWL<7805> A_IWL<7804> A_IWL<7803> A_IWL<7802> A_IWL<7801> A_IWL<7800> A_IWL<7799> A_IWL<7798> A_IWL<7797> A_IWL<7796> A_IWL<7795> A_IWL<7794> A_IWL<7793> A_IWL<7792> A_IWL<7791> A_IWL<7790> A_IWL<7789> A_IWL<7788> A_IWL<7787> A_IWL<7786> A_IWL<7785> A_IWL<7784> A_IWL<7783> A_IWL<7782> A_IWL<7781> A_IWL<7780> A_IWL<7779> A_IWL<7778> A_IWL<7777> A_IWL<7776> A_IWL<7775> A_IWL<7774> A_IWL<7773> A_IWL<7772> A_IWL<7771> A_IWL<7770> A_IWL<7769> A_IWL<7768> A_IWL<7767> A_IWL<7766> A_IWL<7765> A_IWL<7764> A_IWL<7763> A_IWL<7762> A_IWL<7761> A_IWL<7760> A_IWL<7759> A_IWL<7758> A_IWL<7757> A_IWL<7756> A_IWL<7755> A_IWL<7754> A_IWL<7753> A_IWL<7752> A_IWL<7751> A_IWL<7750> A_IWL<7749> A_IWL<7748> A_IWL<7747> A_IWL<7746> A_IWL<7745> A_IWL<7744> A_IWL<7743> A_IWL<7742> A_IWL<7741> A_IWL<7740> A_IWL<7739> A_IWL<7738> A_IWL<7737> A_IWL<7736> A_IWL<7735> A_IWL<7734> A_IWL<7733> A_IWL<7732> A_IWL<7731> A_IWL<7730> A_IWL<7729> A_IWL<7728> A_IWL<7727> A_IWL<7726> A_IWL<7725> A_IWL<7724> A_IWL<7723> A_IWL<7722> A_IWL<7721> A_IWL<7720> A_IWL<7719> A_IWL<7718> A_IWL<7717> A_IWL<7716> A_IWL<7715> A_IWL<7714> A_IWL<7713> A_IWL<7712> A_IWL<7711> A_IWL<7710> A_IWL<7709> A_IWL<7708> A_IWL<7707> A_IWL<7706> A_IWL<7705> A_IWL<7704> A_IWL<7703> A_IWL<7702> A_IWL<7701> A_IWL<7700> A_IWL<7699> A_IWL<7698> A_IWL<7697> A_IWL<7696> A_IWL<7695> A_IWL<7694> A_IWL<7693> A_IWL<7692> A_IWL<7691> A_IWL<7690> A_IWL<7689> A_IWL<7688> A_IWL<7687> A_IWL<7686> A_IWL<7685> A_IWL<7684> A_IWL<7683> A_IWL<7682> A_IWL<7681> A_IWL<7680> A_IWL<8703> A_IWL<8702> A_IWL<8701> A_IWL<8700> A_IWL<8699> A_IWL<8698> A_IWL<8697> A_IWL<8696> A_IWL<8695> A_IWL<8694> A_IWL<8693> A_IWL<8692> A_IWL<8691> A_IWL<8690> A_IWL<8689> A_IWL<8688> A_IWL<8687> A_IWL<8686> A_IWL<8685> A_IWL<8684> A_IWL<8683> A_IWL<8682> A_IWL<8681> A_IWL<8680> A_IWL<8679> A_IWL<8678> A_IWL<8677> A_IWL<8676> A_IWL<8675> A_IWL<8674> A_IWL<8673> A_IWL<8672> A_IWL<8671> A_IWL<8670> A_IWL<8669> A_IWL<8668> A_IWL<8667> A_IWL<8666> A_IWL<8665> A_IWL<8664> A_IWL<8663> A_IWL<8662> A_IWL<8661> A_IWL<8660> A_IWL<8659> A_IWL<8658> A_IWL<8657> A_IWL<8656> A_IWL<8655> A_IWL<8654> A_IWL<8653> A_IWL<8652> A_IWL<8651> A_IWL<8650> A_IWL<8649> A_IWL<8648> A_IWL<8647> A_IWL<8646> A_IWL<8645> A_IWL<8644> A_IWL<8643> A_IWL<8642> A_IWL<8641> A_IWL<8640> A_IWL<8639> A_IWL<8638> A_IWL<8637> A_IWL<8636> A_IWL<8635> A_IWL<8634> A_IWL<8633> A_IWL<8632> A_IWL<8631> A_IWL<8630> A_IWL<8629> A_IWL<8628> A_IWL<8627> A_IWL<8626> A_IWL<8625> A_IWL<8624> A_IWL<8623> A_IWL<8622> A_IWL<8621> A_IWL<8620> A_IWL<8619> A_IWL<8618> A_IWL<8617> A_IWL<8616> A_IWL<8615> A_IWL<8614> A_IWL<8613> A_IWL<8612> A_IWL<8611> A_IWL<8610> A_IWL<8609> A_IWL<8608> A_IWL<8607> A_IWL<8606> A_IWL<8605> A_IWL<8604> A_IWL<8603> A_IWL<8602> A_IWL<8601> A_IWL<8600> A_IWL<8599> A_IWL<8598> A_IWL<8597> A_IWL<8596> A_IWL<8595> A_IWL<8594> A_IWL<8593> A_IWL<8592> A_IWL<8591> A_IWL<8590> A_IWL<8589> A_IWL<8588> A_IWL<8587> A_IWL<8586> A_IWL<8585> A_IWL<8584> A_IWL<8583> A_IWL<8582> A_IWL<8581> A_IWL<8580> A_IWL<8579> A_IWL<8578> A_IWL<8577> A_IWL<8576> A_IWL<8575> A_IWL<8574> A_IWL<8573> A_IWL<8572> A_IWL<8571> A_IWL<8570> A_IWL<8569> A_IWL<8568> A_IWL<8567> A_IWL<8566> A_IWL<8565> A_IWL<8564> A_IWL<8563> A_IWL<8562> A_IWL<8561> A_IWL<8560> A_IWL<8559> A_IWL<8558> A_IWL<8557> A_IWL<8556> A_IWL<8555> A_IWL<8554> A_IWL<8553> A_IWL<8552> A_IWL<8551> A_IWL<8550> A_IWL<8549> A_IWL<8548> A_IWL<8547> A_IWL<8546> A_IWL<8545> A_IWL<8544> A_IWL<8543> A_IWL<8542> A_IWL<8541> A_IWL<8540> A_IWL<8539> A_IWL<8538> A_IWL<8537> A_IWL<8536> A_IWL<8535> A_IWL<8534> A_IWL<8533> A_IWL<8532> A_IWL<8531> A_IWL<8530> A_IWL<8529> A_IWL<8528> A_IWL<8527> A_IWL<8526> A_IWL<8525> A_IWL<8524> A_IWL<8523> A_IWL<8522> A_IWL<8521> A_IWL<8520> A_IWL<8519> A_IWL<8518> A_IWL<8517> A_IWL<8516> A_IWL<8515> A_IWL<8514> A_IWL<8513> A_IWL<8512> A_IWL<8511> A_IWL<8510> A_IWL<8509> A_IWL<8508> A_IWL<8507> A_IWL<8506> A_IWL<8505> A_IWL<8504> A_IWL<8503> A_IWL<8502> A_IWL<8501> A_IWL<8500> A_IWL<8499> A_IWL<8498> A_IWL<8497> A_IWL<8496> A_IWL<8495> A_IWL<8494> A_IWL<8493> A_IWL<8492> A_IWL<8491> A_IWL<8490> A_IWL<8489> A_IWL<8488> A_IWL<8487> A_IWL<8486> A_IWL<8485> A_IWL<8484> A_IWL<8483> A_IWL<8482> A_IWL<8481> A_IWL<8480> A_IWL<8479> A_IWL<8478> A_IWL<8477> A_IWL<8476> A_IWL<8475> A_IWL<8474> A_IWL<8473> A_IWL<8472> A_IWL<8471> A_IWL<8470> A_IWL<8469> A_IWL<8468> A_IWL<8467> A_IWL<8466> A_IWL<8465> A_IWL<8464> A_IWL<8463> A_IWL<8462> A_IWL<8461> A_IWL<8460> A_IWL<8459> A_IWL<8458> A_IWL<8457> A_IWL<8456> A_IWL<8455> A_IWL<8454> A_IWL<8453> A_IWL<8452> A_IWL<8451> A_IWL<8450> A_IWL<8449> A_IWL<8448> A_IWL<8447> A_IWL<8446> A_IWL<8445> A_IWL<8444> A_IWL<8443> A_IWL<8442> A_IWL<8441> A_IWL<8440> A_IWL<8439> A_IWL<8438> A_IWL<8437> A_IWL<8436> A_IWL<8435> A_IWL<8434> A_IWL<8433> A_IWL<8432> A_IWL<8431> A_IWL<8430> A_IWL<8429> A_IWL<8428> A_IWL<8427> A_IWL<8426> A_IWL<8425> A_IWL<8424> A_IWL<8423> A_IWL<8422> A_IWL<8421> A_IWL<8420> A_IWL<8419> A_IWL<8418> A_IWL<8417> A_IWL<8416> A_IWL<8415> A_IWL<8414> A_IWL<8413> A_IWL<8412> A_IWL<8411> A_IWL<8410> A_IWL<8409> A_IWL<8408> A_IWL<8407> A_IWL<8406> A_IWL<8405> A_IWL<8404> A_IWL<8403> A_IWL<8402> A_IWL<8401> A_IWL<8400> A_IWL<8399> A_IWL<8398> A_IWL<8397> A_IWL<8396> A_IWL<8395> A_IWL<8394> A_IWL<8393> A_IWL<8392> A_IWL<8391> A_IWL<8390> A_IWL<8389> A_IWL<8388> A_IWL<8387> A_IWL<8386> A_IWL<8385> A_IWL<8384> A_IWL<8383> A_IWL<8382> A_IWL<8381> A_IWL<8380> A_IWL<8379> A_IWL<8378> A_IWL<8377> A_IWL<8376> A_IWL<8375> A_IWL<8374> A_IWL<8373> A_IWL<8372> A_IWL<8371> A_IWL<8370> A_IWL<8369> A_IWL<8368> A_IWL<8367> A_IWL<8366> A_IWL<8365> A_IWL<8364> A_IWL<8363> A_IWL<8362> A_IWL<8361> A_IWL<8360> A_IWL<8359> A_IWL<8358> A_IWL<8357> A_IWL<8356> A_IWL<8355> A_IWL<8354> A_IWL<8353> A_IWL<8352> A_IWL<8351> A_IWL<8350> A_IWL<8349> A_IWL<8348> A_IWL<8347> A_IWL<8346> A_IWL<8345> A_IWL<8344> A_IWL<8343> A_IWL<8342> A_IWL<8341> A_IWL<8340> A_IWL<8339> A_IWL<8338> A_IWL<8337> A_IWL<8336> A_IWL<8335> A_IWL<8334> A_IWL<8333> A_IWL<8332> A_IWL<8331> A_IWL<8330> A_IWL<8329> A_IWL<8328> A_IWL<8327> A_IWL<8326> A_IWL<8325> A_IWL<8324> A_IWL<8323> A_IWL<8322> A_IWL<8321> A_IWL<8320> A_IWL<8319> A_IWL<8318> A_IWL<8317> A_IWL<8316> A_IWL<8315> A_IWL<8314> A_IWL<8313> A_IWL<8312> A_IWL<8311> A_IWL<8310> A_IWL<8309> A_IWL<8308> A_IWL<8307> A_IWL<8306> A_IWL<8305> A_IWL<8304> A_IWL<8303> A_IWL<8302> A_IWL<8301> A_IWL<8300> A_IWL<8299> A_IWL<8298> A_IWL<8297> A_IWL<8296> A_IWL<8295> A_IWL<8294> A_IWL<8293> A_IWL<8292> A_IWL<8291> A_IWL<8290> A_IWL<8289> A_IWL<8288> A_IWL<8287> A_IWL<8286> A_IWL<8285> A_IWL<8284> A_IWL<8283> A_IWL<8282> A_IWL<8281> A_IWL<8280> A_IWL<8279> A_IWL<8278> A_IWL<8277> A_IWL<8276> A_IWL<8275> A_IWL<8274> A_IWL<8273> A_IWL<8272> A_IWL<8271> A_IWL<8270> A_IWL<8269> A_IWL<8268> A_IWL<8267> A_IWL<8266> A_IWL<8265> A_IWL<8264> A_IWL<8263> A_IWL<8262> A_IWL<8261> A_IWL<8260> A_IWL<8259> A_IWL<8258> A_IWL<8257> A_IWL<8256> A_IWL<8255> A_IWL<8254> A_IWL<8253> A_IWL<8252> A_IWL<8251> A_IWL<8250> A_IWL<8249> A_IWL<8248> A_IWL<8247> A_IWL<8246> A_IWL<8245> A_IWL<8244> A_IWL<8243> A_IWL<8242> A_IWL<8241> A_IWL<8240> A_IWL<8239> A_IWL<8238> A_IWL<8237> A_IWL<8236> A_IWL<8235> A_IWL<8234> A_IWL<8233> A_IWL<8232> A_IWL<8231> A_IWL<8230> A_IWL<8229> A_IWL<8228> A_IWL<8227> A_IWL<8226> A_IWL<8225> A_IWL<8224> A_IWL<8223> A_IWL<8222> A_IWL<8221> A_IWL<8220> A_IWL<8219> A_IWL<8218> A_IWL<8217> A_IWL<8216> A_IWL<8215> A_IWL<8214> A_IWL<8213> A_IWL<8212> A_IWL<8211> A_IWL<8210> A_IWL<8209> A_IWL<8208> A_IWL<8207> A_IWL<8206> A_IWL<8205> A_IWL<8204> A_IWL<8203> A_IWL<8202> A_IWL<8201> A_IWL<8200> A_IWL<8199> A_IWL<8198> A_IWL<8197> A_IWL<8196> A_IWL<8195> A_IWL<8194> A_IWL<8193> A_IWL<8192> VDD_CORE VSS / RM_IHPSG13_8192x32_c4_1P_COLUMN_pcell_0 +XCOL<15> A_BLC<31> A_BLC<30> A_BLC_TOP<31> A_BLC_TOP<30> A_BLT<31> A_BLT<30> A_BLT_TOP<31> A_BLT_TOP<30> A_IWL<7679> A_IWL<7678> A_IWL<7677> A_IWL<7676> A_IWL<7675> A_IWL<7674> A_IWL<7673> A_IWL<7672> A_IWL<7671> A_IWL<7670> A_IWL<7669> A_IWL<7668> A_IWL<7667> A_IWL<7666> A_IWL<7665> A_IWL<7664> A_IWL<7663> A_IWL<7662> A_IWL<7661> A_IWL<7660> A_IWL<7659> A_IWL<7658> A_IWL<7657> A_IWL<7656> A_IWL<7655> A_IWL<7654> A_IWL<7653> A_IWL<7652> A_IWL<7651> A_IWL<7650> A_IWL<7649> A_IWL<7648> A_IWL<7647> A_IWL<7646> A_IWL<7645> A_IWL<7644> A_IWL<7643> A_IWL<7642> A_IWL<7641> A_IWL<7640> A_IWL<7639> A_IWL<7638> A_IWL<7637> A_IWL<7636> A_IWL<7635> A_IWL<7634> A_IWL<7633> A_IWL<7632> A_IWL<7631> A_IWL<7630> A_IWL<7629> A_IWL<7628> A_IWL<7627> A_IWL<7626> A_IWL<7625> A_IWL<7624> A_IWL<7623> A_IWL<7622> A_IWL<7621> A_IWL<7620> A_IWL<7619> A_IWL<7618> A_IWL<7617> A_IWL<7616> A_IWL<7615> A_IWL<7614> A_IWL<7613> A_IWL<7612> A_IWL<7611> A_IWL<7610> A_IWL<7609> A_IWL<7608> A_IWL<7607> A_IWL<7606> A_IWL<7605> A_IWL<7604> A_IWL<7603> A_IWL<7602> A_IWL<7601> A_IWL<7600> A_IWL<7599> A_IWL<7598> A_IWL<7597> A_IWL<7596> A_IWL<7595> A_IWL<7594> A_IWL<7593> A_IWL<7592> A_IWL<7591> A_IWL<7590> A_IWL<7589> A_IWL<7588> A_IWL<7587> A_IWL<7586> A_IWL<7585> A_IWL<7584> A_IWL<7583> A_IWL<7582> A_IWL<7581> A_IWL<7580> A_IWL<7579> A_IWL<7578> A_IWL<7577> A_IWL<7576> A_IWL<7575> A_IWL<7574> A_IWL<7573> A_IWL<7572> A_IWL<7571> A_IWL<7570> A_IWL<7569> A_IWL<7568> A_IWL<7567> A_IWL<7566> A_IWL<7565> A_IWL<7564> A_IWL<7563> A_IWL<7562> A_IWL<7561> A_IWL<7560> A_IWL<7559> A_IWL<7558> A_IWL<7557> A_IWL<7556> A_IWL<7555> A_IWL<7554> A_IWL<7553> A_IWL<7552> A_IWL<7551> A_IWL<7550> A_IWL<7549> A_IWL<7548> A_IWL<7547> A_IWL<7546> A_IWL<7545> A_IWL<7544> A_IWL<7543> A_IWL<7542> A_IWL<7541> A_IWL<7540> A_IWL<7539> A_IWL<7538> A_IWL<7537> A_IWL<7536> A_IWL<7535> A_IWL<7534> A_IWL<7533> A_IWL<7532> A_IWL<7531> A_IWL<7530> A_IWL<7529> A_IWL<7528> A_IWL<7527> A_IWL<7526> A_IWL<7525> A_IWL<7524> A_IWL<7523> A_IWL<7522> A_IWL<7521> A_IWL<7520> A_IWL<7519> A_IWL<7518> A_IWL<7517> A_IWL<7516> A_IWL<7515> A_IWL<7514> A_IWL<7513> A_IWL<7512> A_IWL<7511> A_IWL<7510> A_IWL<7509> A_IWL<7508> A_IWL<7507> A_IWL<7506> A_IWL<7505> A_IWL<7504> A_IWL<7503> A_IWL<7502> A_IWL<7501> A_IWL<7500> A_IWL<7499> A_IWL<7498> A_IWL<7497> A_IWL<7496> A_IWL<7495> A_IWL<7494> A_IWL<7493> A_IWL<7492> A_IWL<7491> A_IWL<7490> A_IWL<7489> A_IWL<7488> A_IWL<7487> A_IWL<7486> A_IWL<7485> A_IWL<7484> A_IWL<7483> A_IWL<7482> A_IWL<7481> A_IWL<7480> A_IWL<7479> A_IWL<7478> A_IWL<7477> A_IWL<7476> A_IWL<7475> A_IWL<7474> A_IWL<7473> A_IWL<7472> A_IWL<7471> A_IWL<7470> A_IWL<7469> A_IWL<7468> A_IWL<7467> A_IWL<7466> A_IWL<7465> A_IWL<7464> A_IWL<7463> A_IWL<7462> A_IWL<7461> A_IWL<7460> A_IWL<7459> A_IWL<7458> A_IWL<7457> A_IWL<7456> A_IWL<7455> A_IWL<7454> A_IWL<7453> A_IWL<7452> A_IWL<7451> A_IWL<7450> A_IWL<7449> A_IWL<7448> A_IWL<7447> A_IWL<7446> A_IWL<7445> A_IWL<7444> A_IWL<7443> A_IWL<7442> A_IWL<7441> A_IWL<7440> A_IWL<7439> A_IWL<7438> A_IWL<7437> A_IWL<7436> A_IWL<7435> A_IWL<7434> A_IWL<7433> A_IWL<7432> A_IWL<7431> A_IWL<7430> A_IWL<7429> A_IWL<7428> A_IWL<7427> A_IWL<7426> A_IWL<7425> A_IWL<7424> A_IWL<7423> A_IWL<7422> A_IWL<7421> A_IWL<7420> A_IWL<7419> A_IWL<7418> A_IWL<7417> A_IWL<7416> A_IWL<7415> A_IWL<7414> A_IWL<7413> A_IWL<7412> A_IWL<7411> A_IWL<7410> A_IWL<7409> A_IWL<7408> A_IWL<7407> A_IWL<7406> A_IWL<7405> A_IWL<7404> A_IWL<7403> A_IWL<7402> A_IWL<7401> A_IWL<7400> A_IWL<7399> A_IWL<7398> A_IWL<7397> A_IWL<7396> A_IWL<7395> A_IWL<7394> A_IWL<7393> A_IWL<7392> A_IWL<7391> A_IWL<7390> A_IWL<7389> A_IWL<7388> A_IWL<7387> A_IWL<7386> A_IWL<7385> A_IWL<7384> A_IWL<7383> A_IWL<7382> A_IWL<7381> A_IWL<7380> A_IWL<7379> A_IWL<7378> A_IWL<7377> A_IWL<7376> A_IWL<7375> A_IWL<7374> A_IWL<7373> A_IWL<7372> A_IWL<7371> A_IWL<7370> A_IWL<7369> A_IWL<7368> A_IWL<7367> A_IWL<7366> A_IWL<7365> A_IWL<7364> A_IWL<7363> A_IWL<7362> A_IWL<7361> A_IWL<7360> A_IWL<7359> A_IWL<7358> A_IWL<7357> A_IWL<7356> A_IWL<7355> A_IWL<7354> A_IWL<7353> A_IWL<7352> A_IWL<7351> A_IWL<7350> A_IWL<7349> A_IWL<7348> A_IWL<7347> A_IWL<7346> A_IWL<7345> A_IWL<7344> A_IWL<7343> A_IWL<7342> A_IWL<7341> A_IWL<7340> A_IWL<7339> A_IWL<7338> A_IWL<7337> A_IWL<7336> A_IWL<7335> A_IWL<7334> A_IWL<7333> A_IWL<7332> A_IWL<7331> A_IWL<7330> A_IWL<7329> A_IWL<7328> A_IWL<7327> A_IWL<7326> A_IWL<7325> A_IWL<7324> A_IWL<7323> A_IWL<7322> A_IWL<7321> A_IWL<7320> A_IWL<7319> A_IWL<7318> A_IWL<7317> A_IWL<7316> A_IWL<7315> A_IWL<7314> A_IWL<7313> A_IWL<7312> A_IWL<7311> A_IWL<7310> A_IWL<7309> A_IWL<7308> A_IWL<7307> A_IWL<7306> A_IWL<7305> A_IWL<7304> A_IWL<7303> A_IWL<7302> A_IWL<7301> A_IWL<7300> A_IWL<7299> A_IWL<7298> A_IWL<7297> A_IWL<7296> A_IWL<7295> A_IWL<7294> A_IWL<7293> A_IWL<7292> A_IWL<7291> A_IWL<7290> A_IWL<7289> A_IWL<7288> A_IWL<7287> A_IWL<7286> A_IWL<7285> A_IWL<7284> A_IWL<7283> A_IWL<7282> A_IWL<7281> A_IWL<7280> A_IWL<7279> A_IWL<7278> A_IWL<7277> A_IWL<7276> A_IWL<7275> A_IWL<7274> A_IWL<7273> A_IWL<7272> A_IWL<7271> A_IWL<7270> A_IWL<7269> A_IWL<7268> A_IWL<7267> A_IWL<7266> A_IWL<7265> A_IWL<7264> A_IWL<7263> A_IWL<7262> A_IWL<7261> A_IWL<7260> A_IWL<7259> A_IWL<7258> A_IWL<7257> A_IWL<7256> A_IWL<7255> A_IWL<7254> A_IWL<7253> A_IWL<7252> A_IWL<7251> A_IWL<7250> A_IWL<7249> A_IWL<7248> A_IWL<7247> A_IWL<7246> A_IWL<7245> A_IWL<7244> A_IWL<7243> A_IWL<7242> A_IWL<7241> A_IWL<7240> A_IWL<7239> A_IWL<7238> A_IWL<7237> A_IWL<7236> A_IWL<7235> A_IWL<7234> A_IWL<7233> A_IWL<7232> A_IWL<7231> A_IWL<7230> A_IWL<7229> A_IWL<7228> A_IWL<7227> A_IWL<7226> A_IWL<7225> A_IWL<7224> A_IWL<7223> A_IWL<7222> A_IWL<7221> A_IWL<7220> A_IWL<7219> A_IWL<7218> A_IWL<7217> A_IWL<7216> A_IWL<7215> A_IWL<7214> A_IWL<7213> A_IWL<7212> A_IWL<7211> A_IWL<7210> A_IWL<7209> A_IWL<7208> A_IWL<7207> A_IWL<7206> A_IWL<7205> A_IWL<7204> A_IWL<7203> A_IWL<7202> A_IWL<7201> A_IWL<7200> A_IWL<7199> A_IWL<7198> A_IWL<7197> A_IWL<7196> A_IWL<7195> A_IWL<7194> A_IWL<7193> A_IWL<7192> A_IWL<7191> A_IWL<7190> A_IWL<7189> A_IWL<7188> A_IWL<7187> A_IWL<7186> A_IWL<7185> A_IWL<7184> A_IWL<7183> A_IWL<7182> A_IWL<7181> A_IWL<7180> A_IWL<7179> A_IWL<7178> A_IWL<7177> A_IWL<7176> A_IWL<7175> A_IWL<7174> A_IWL<7173> A_IWL<7172> A_IWL<7171> A_IWL<7170> A_IWL<7169> A_IWL<7168> A_IWL<8191> A_IWL<8190> A_IWL<8189> A_IWL<8188> A_IWL<8187> A_IWL<8186> A_IWL<8185> A_IWL<8184> A_IWL<8183> A_IWL<8182> A_IWL<8181> A_IWL<8180> A_IWL<8179> A_IWL<8178> A_IWL<8177> A_IWL<8176> A_IWL<8175> A_IWL<8174> A_IWL<8173> A_IWL<8172> A_IWL<8171> A_IWL<8170> A_IWL<8169> A_IWL<8168> A_IWL<8167> A_IWL<8166> A_IWL<8165> A_IWL<8164> A_IWL<8163> A_IWL<8162> A_IWL<8161> A_IWL<8160> A_IWL<8159> A_IWL<8158> A_IWL<8157> A_IWL<8156> A_IWL<8155> A_IWL<8154> A_IWL<8153> A_IWL<8152> A_IWL<8151> A_IWL<8150> A_IWL<8149> A_IWL<8148> A_IWL<8147> A_IWL<8146> A_IWL<8145> A_IWL<8144> A_IWL<8143> A_IWL<8142> A_IWL<8141> A_IWL<8140> A_IWL<8139> A_IWL<8138> A_IWL<8137> A_IWL<8136> A_IWL<8135> A_IWL<8134> A_IWL<8133> A_IWL<8132> A_IWL<8131> A_IWL<8130> A_IWL<8129> A_IWL<8128> A_IWL<8127> A_IWL<8126> A_IWL<8125> A_IWL<8124> A_IWL<8123> A_IWL<8122> A_IWL<8121> A_IWL<8120> A_IWL<8119> A_IWL<8118> A_IWL<8117> A_IWL<8116> A_IWL<8115> A_IWL<8114> A_IWL<8113> A_IWL<8112> A_IWL<8111> A_IWL<8110> A_IWL<8109> A_IWL<8108> A_IWL<8107> A_IWL<8106> A_IWL<8105> A_IWL<8104> A_IWL<8103> A_IWL<8102> A_IWL<8101> A_IWL<8100> A_IWL<8099> A_IWL<8098> A_IWL<8097> A_IWL<8096> A_IWL<8095> A_IWL<8094> A_IWL<8093> A_IWL<8092> A_IWL<8091> A_IWL<8090> A_IWL<8089> A_IWL<8088> A_IWL<8087> A_IWL<8086> A_IWL<8085> A_IWL<8084> A_IWL<8083> A_IWL<8082> A_IWL<8081> A_IWL<8080> A_IWL<8079> A_IWL<8078> A_IWL<8077> A_IWL<8076> A_IWL<8075> A_IWL<8074> A_IWL<8073> A_IWL<8072> A_IWL<8071> A_IWL<8070> A_IWL<8069> A_IWL<8068> A_IWL<8067> A_IWL<8066> A_IWL<8065> A_IWL<8064> A_IWL<8063> A_IWL<8062> A_IWL<8061> A_IWL<8060> A_IWL<8059> A_IWL<8058> A_IWL<8057> A_IWL<8056> A_IWL<8055> A_IWL<8054> A_IWL<8053> A_IWL<8052> A_IWL<8051> A_IWL<8050> A_IWL<8049> A_IWL<8048> A_IWL<8047> A_IWL<8046> A_IWL<8045> A_IWL<8044> A_IWL<8043> A_IWL<8042> A_IWL<8041> A_IWL<8040> A_IWL<8039> A_IWL<8038> A_IWL<8037> A_IWL<8036> A_IWL<8035> A_IWL<8034> A_IWL<8033> A_IWL<8032> A_IWL<8031> A_IWL<8030> A_IWL<8029> A_IWL<8028> A_IWL<8027> A_IWL<8026> A_IWL<8025> A_IWL<8024> A_IWL<8023> A_IWL<8022> A_IWL<8021> A_IWL<8020> A_IWL<8019> A_IWL<8018> A_IWL<8017> A_IWL<8016> A_IWL<8015> A_IWL<8014> A_IWL<8013> A_IWL<8012> A_IWL<8011> A_IWL<8010> A_IWL<8009> A_IWL<8008> A_IWL<8007> A_IWL<8006> A_IWL<8005> A_IWL<8004> A_IWL<8003> A_IWL<8002> A_IWL<8001> A_IWL<8000> A_IWL<7999> A_IWL<7998> A_IWL<7997> A_IWL<7996> A_IWL<7995> A_IWL<7994> A_IWL<7993> A_IWL<7992> A_IWL<7991> A_IWL<7990> A_IWL<7989> A_IWL<7988> A_IWL<7987> A_IWL<7986> A_IWL<7985> A_IWL<7984> A_IWL<7983> A_IWL<7982> A_IWL<7981> A_IWL<7980> A_IWL<7979> A_IWL<7978> A_IWL<7977> A_IWL<7976> A_IWL<7975> A_IWL<7974> A_IWL<7973> A_IWL<7972> A_IWL<7971> A_IWL<7970> A_IWL<7969> A_IWL<7968> A_IWL<7967> A_IWL<7966> A_IWL<7965> A_IWL<7964> A_IWL<7963> A_IWL<7962> A_IWL<7961> A_IWL<7960> A_IWL<7959> A_IWL<7958> A_IWL<7957> A_IWL<7956> A_IWL<7955> A_IWL<7954> A_IWL<7953> A_IWL<7952> A_IWL<7951> A_IWL<7950> A_IWL<7949> A_IWL<7948> A_IWL<7947> A_IWL<7946> A_IWL<7945> A_IWL<7944> A_IWL<7943> A_IWL<7942> A_IWL<7941> A_IWL<7940> A_IWL<7939> A_IWL<7938> A_IWL<7937> A_IWL<7936> A_IWL<7935> A_IWL<7934> A_IWL<7933> A_IWL<7932> A_IWL<7931> A_IWL<7930> A_IWL<7929> A_IWL<7928> A_IWL<7927> A_IWL<7926> A_IWL<7925> A_IWL<7924> A_IWL<7923> A_IWL<7922> A_IWL<7921> A_IWL<7920> A_IWL<7919> A_IWL<7918> A_IWL<7917> A_IWL<7916> A_IWL<7915> A_IWL<7914> A_IWL<7913> A_IWL<7912> A_IWL<7911> A_IWL<7910> A_IWL<7909> A_IWL<7908> A_IWL<7907> A_IWL<7906> A_IWL<7905> A_IWL<7904> A_IWL<7903> A_IWL<7902> A_IWL<7901> A_IWL<7900> A_IWL<7899> A_IWL<7898> A_IWL<7897> A_IWL<7896> A_IWL<7895> A_IWL<7894> A_IWL<7893> A_IWL<7892> A_IWL<7891> A_IWL<7890> A_IWL<7889> A_IWL<7888> A_IWL<7887> A_IWL<7886> A_IWL<7885> A_IWL<7884> A_IWL<7883> A_IWL<7882> A_IWL<7881> A_IWL<7880> A_IWL<7879> A_IWL<7878> A_IWL<7877> A_IWL<7876> A_IWL<7875> A_IWL<7874> A_IWL<7873> A_IWL<7872> A_IWL<7871> A_IWL<7870> A_IWL<7869> A_IWL<7868> A_IWL<7867> A_IWL<7866> A_IWL<7865> A_IWL<7864> A_IWL<7863> A_IWL<7862> A_IWL<7861> A_IWL<7860> A_IWL<7859> A_IWL<7858> A_IWL<7857> A_IWL<7856> A_IWL<7855> A_IWL<7854> A_IWL<7853> A_IWL<7852> A_IWL<7851> A_IWL<7850> A_IWL<7849> A_IWL<7848> A_IWL<7847> A_IWL<7846> A_IWL<7845> A_IWL<7844> A_IWL<7843> A_IWL<7842> A_IWL<7841> A_IWL<7840> A_IWL<7839> A_IWL<7838> A_IWL<7837> A_IWL<7836> A_IWL<7835> A_IWL<7834> A_IWL<7833> A_IWL<7832> A_IWL<7831> A_IWL<7830> A_IWL<7829> A_IWL<7828> A_IWL<7827> A_IWL<7826> A_IWL<7825> A_IWL<7824> A_IWL<7823> A_IWL<7822> A_IWL<7821> A_IWL<7820> A_IWL<7819> A_IWL<7818> A_IWL<7817> A_IWL<7816> A_IWL<7815> A_IWL<7814> A_IWL<7813> A_IWL<7812> A_IWL<7811> A_IWL<7810> A_IWL<7809> A_IWL<7808> A_IWL<7807> A_IWL<7806> A_IWL<7805> A_IWL<7804> A_IWL<7803> A_IWL<7802> A_IWL<7801> A_IWL<7800> A_IWL<7799> A_IWL<7798> A_IWL<7797> A_IWL<7796> A_IWL<7795> A_IWL<7794> A_IWL<7793> A_IWL<7792> A_IWL<7791> A_IWL<7790> A_IWL<7789> A_IWL<7788> A_IWL<7787> A_IWL<7786> A_IWL<7785> A_IWL<7784> A_IWL<7783> A_IWL<7782> A_IWL<7781> A_IWL<7780> A_IWL<7779> A_IWL<7778> A_IWL<7777> A_IWL<7776> A_IWL<7775> A_IWL<7774> A_IWL<7773> A_IWL<7772> A_IWL<7771> A_IWL<7770> A_IWL<7769> A_IWL<7768> A_IWL<7767> A_IWL<7766> A_IWL<7765> A_IWL<7764> A_IWL<7763> A_IWL<7762> A_IWL<7761> A_IWL<7760> A_IWL<7759> A_IWL<7758> A_IWL<7757> A_IWL<7756> A_IWL<7755> A_IWL<7754> A_IWL<7753> A_IWL<7752> A_IWL<7751> A_IWL<7750> A_IWL<7749> A_IWL<7748> A_IWL<7747> A_IWL<7746> A_IWL<7745> A_IWL<7744> A_IWL<7743> A_IWL<7742> A_IWL<7741> A_IWL<7740> A_IWL<7739> A_IWL<7738> A_IWL<7737> A_IWL<7736> A_IWL<7735> A_IWL<7734> A_IWL<7733> A_IWL<7732> A_IWL<7731> A_IWL<7730> A_IWL<7729> A_IWL<7728> A_IWL<7727> A_IWL<7726> A_IWL<7725> A_IWL<7724> A_IWL<7723> A_IWL<7722> A_IWL<7721> A_IWL<7720> A_IWL<7719> A_IWL<7718> A_IWL<7717> A_IWL<7716> A_IWL<7715> A_IWL<7714> A_IWL<7713> A_IWL<7712> A_IWL<7711> A_IWL<7710> A_IWL<7709> A_IWL<7708> A_IWL<7707> A_IWL<7706> A_IWL<7705> A_IWL<7704> A_IWL<7703> A_IWL<7702> A_IWL<7701> A_IWL<7700> A_IWL<7699> A_IWL<7698> A_IWL<7697> A_IWL<7696> A_IWL<7695> A_IWL<7694> A_IWL<7693> A_IWL<7692> A_IWL<7691> A_IWL<7690> A_IWL<7689> A_IWL<7688> A_IWL<7687> A_IWL<7686> A_IWL<7685> A_IWL<7684> A_IWL<7683> A_IWL<7682> A_IWL<7681> A_IWL<7680> VDD_CORE VSS / RM_IHPSG13_8192x32_c4_1P_COLUMN_pcell_0 +XCOL<14> A_BLC<29> A_BLC<28> A_BLC_TOP<29> A_BLC_TOP<28> A_BLT<29> A_BLT<28> A_BLT_TOP<29> A_BLT_TOP<28> A_IWL<7167> A_IWL<7166> A_IWL<7165> A_IWL<7164> A_IWL<7163> A_IWL<7162> A_IWL<7161> A_IWL<7160> A_IWL<7159> A_IWL<7158> A_IWL<7157> A_IWL<7156> A_IWL<7155> A_IWL<7154> A_IWL<7153> A_IWL<7152> A_IWL<7151> A_IWL<7150> A_IWL<7149> A_IWL<7148> A_IWL<7147> A_IWL<7146> A_IWL<7145> A_IWL<7144> A_IWL<7143> A_IWL<7142> A_IWL<7141> A_IWL<7140> A_IWL<7139> A_IWL<7138> A_IWL<7137> A_IWL<7136> A_IWL<7135> A_IWL<7134> A_IWL<7133> A_IWL<7132> A_IWL<7131> A_IWL<7130> A_IWL<7129> A_IWL<7128> A_IWL<7127> A_IWL<7126> A_IWL<7125> A_IWL<7124> A_IWL<7123> A_IWL<7122> A_IWL<7121> A_IWL<7120> A_IWL<7119> A_IWL<7118> A_IWL<7117> A_IWL<7116> A_IWL<7115> A_IWL<7114> A_IWL<7113> A_IWL<7112> A_IWL<7111> A_IWL<7110> A_IWL<7109> A_IWL<7108> A_IWL<7107> A_IWL<7106> A_IWL<7105> A_IWL<7104> A_IWL<7103> A_IWL<7102> A_IWL<7101> A_IWL<7100> A_IWL<7099> A_IWL<7098> A_IWL<7097> A_IWL<7096> A_IWL<7095> A_IWL<7094> A_IWL<7093> A_IWL<7092> A_IWL<7091> A_IWL<7090> A_IWL<7089> A_IWL<7088> A_IWL<7087> A_IWL<7086> A_IWL<7085> A_IWL<7084> A_IWL<7083> A_IWL<7082> A_IWL<7081> A_IWL<7080> A_IWL<7079> A_IWL<7078> A_IWL<7077> A_IWL<7076> A_IWL<7075> A_IWL<7074> A_IWL<7073> A_IWL<7072> A_IWL<7071> A_IWL<7070> A_IWL<7069> A_IWL<7068> A_IWL<7067> A_IWL<7066> A_IWL<7065> A_IWL<7064> A_IWL<7063> A_IWL<7062> A_IWL<7061> A_IWL<7060> A_IWL<7059> A_IWL<7058> A_IWL<7057> A_IWL<7056> A_IWL<7055> A_IWL<7054> A_IWL<7053> A_IWL<7052> A_IWL<7051> A_IWL<7050> A_IWL<7049> A_IWL<7048> A_IWL<7047> A_IWL<7046> A_IWL<7045> A_IWL<7044> A_IWL<7043> A_IWL<7042> A_IWL<7041> A_IWL<7040> A_IWL<7039> A_IWL<7038> A_IWL<7037> A_IWL<7036> A_IWL<7035> A_IWL<7034> A_IWL<7033> A_IWL<7032> A_IWL<7031> A_IWL<7030> A_IWL<7029> A_IWL<7028> A_IWL<7027> A_IWL<7026> A_IWL<7025> A_IWL<7024> A_IWL<7023> A_IWL<7022> A_IWL<7021> A_IWL<7020> A_IWL<7019> A_IWL<7018> A_IWL<7017> A_IWL<7016> A_IWL<7015> A_IWL<7014> A_IWL<7013> A_IWL<7012> A_IWL<7011> A_IWL<7010> A_IWL<7009> A_IWL<7008> A_IWL<7007> A_IWL<7006> A_IWL<7005> A_IWL<7004> A_IWL<7003> A_IWL<7002> A_IWL<7001> A_IWL<7000> A_IWL<6999> A_IWL<6998> A_IWL<6997> A_IWL<6996> A_IWL<6995> A_IWL<6994> A_IWL<6993> A_IWL<6992> A_IWL<6991> A_IWL<6990> A_IWL<6989> A_IWL<6988> A_IWL<6987> A_IWL<6986> A_IWL<6985> A_IWL<6984> A_IWL<6983> A_IWL<6982> A_IWL<6981> A_IWL<6980> A_IWL<6979> A_IWL<6978> A_IWL<6977> A_IWL<6976> A_IWL<6975> A_IWL<6974> A_IWL<6973> A_IWL<6972> A_IWL<6971> A_IWL<6970> A_IWL<6969> A_IWL<6968> A_IWL<6967> A_IWL<6966> A_IWL<6965> A_IWL<6964> A_IWL<6963> A_IWL<6962> A_IWL<6961> A_IWL<6960> A_IWL<6959> A_IWL<6958> A_IWL<6957> A_IWL<6956> A_IWL<6955> A_IWL<6954> A_IWL<6953> A_IWL<6952> A_IWL<6951> A_IWL<6950> A_IWL<6949> A_IWL<6948> A_IWL<6947> A_IWL<6946> A_IWL<6945> A_IWL<6944> A_IWL<6943> A_IWL<6942> A_IWL<6941> A_IWL<6940> A_IWL<6939> A_IWL<6938> A_IWL<6937> A_IWL<6936> A_IWL<6935> A_IWL<6934> A_IWL<6933> A_IWL<6932> A_IWL<6931> A_IWL<6930> A_IWL<6929> A_IWL<6928> A_IWL<6927> A_IWL<6926> A_IWL<6925> A_IWL<6924> A_IWL<6923> A_IWL<6922> A_IWL<6921> A_IWL<6920> A_IWL<6919> A_IWL<6918> A_IWL<6917> A_IWL<6916> A_IWL<6915> A_IWL<6914> A_IWL<6913> A_IWL<6912> A_IWL<6911> A_IWL<6910> A_IWL<6909> A_IWL<6908> A_IWL<6907> A_IWL<6906> A_IWL<6905> A_IWL<6904> A_IWL<6903> A_IWL<6902> A_IWL<6901> A_IWL<6900> A_IWL<6899> A_IWL<6898> A_IWL<6897> A_IWL<6896> A_IWL<6895> A_IWL<6894> A_IWL<6893> A_IWL<6892> A_IWL<6891> A_IWL<6890> A_IWL<6889> A_IWL<6888> A_IWL<6887> A_IWL<6886> A_IWL<6885> A_IWL<6884> A_IWL<6883> A_IWL<6882> A_IWL<6881> A_IWL<6880> A_IWL<6879> A_IWL<6878> A_IWL<6877> A_IWL<6876> A_IWL<6875> A_IWL<6874> A_IWL<6873> A_IWL<6872> A_IWL<6871> A_IWL<6870> A_IWL<6869> A_IWL<6868> A_IWL<6867> A_IWL<6866> A_IWL<6865> A_IWL<6864> A_IWL<6863> A_IWL<6862> A_IWL<6861> A_IWL<6860> A_IWL<6859> A_IWL<6858> A_IWL<6857> A_IWL<6856> A_IWL<6855> A_IWL<6854> A_IWL<6853> A_IWL<6852> A_IWL<6851> A_IWL<6850> A_IWL<6849> A_IWL<6848> A_IWL<6847> A_IWL<6846> A_IWL<6845> A_IWL<6844> A_IWL<6843> A_IWL<6842> A_IWL<6841> A_IWL<6840> A_IWL<6839> A_IWL<6838> A_IWL<6837> A_IWL<6836> A_IWL<6835> A_IWL<6834> A_IWL<6833> A_IWL<6832> A_IWL<6831> A_IWL<6830> A_IWL<6829> A_IWL<6828> A_IWL<6827> A_IWL<6826> A_IWL<6825> A_IWL<6824> A_IWL<6823> A_IWL<6822> A_IWL<6821> A_IWL<6820> A_IWL<6819> A_IWL<6818> A_IWL<6817> A_IWL<6816> A_IWL<6815> A_IWL<6814> A_IWL<6813> A_IWL<6812> A_IWL<6811> A_IWL<6810> A_IWL<6809> A_IWL<6808> A_IWL<6807> A_IWL<6806> A_IWL<6805> A_IWL<6804> A_IWL<6803> A_IWL<6802> A_IWL<6801> A_IWL<6800> A_IWL<6799> A_IWL<6798> A_IWL<6797> A_IWL<6796> A_IWL<6795> A_IWL<6794> A_IWL<6793> A_IWL<6792> A_IWL<6791> A_IWL<6790> A_IWL<6789> A_IWL<6788> A_IWL<6787> A_IWL<6786> A_IWL<6785> A_IWL<6784> A_IWL<6783> A_IWL<6782> A_IWL<6781> A_IWL<6780> A_IWL<6779> A_IWL<6778> A_IWL<6777> A_IWL<6776> A_IWL<6775> A_IWL<6774> A_IWL<6773> A_IWL<6772> A_IWL<6771> A_IWL<6770> A_IWL<6769> A_IWL<6768> A_IWL<6767> A_IWL<6766> A_IWL<6765> A_IWL<6764> A_IWL<6763> A_IWL<6762> A_IWL<6761> A_IWL<6760> A_IWL<6759> A_IWL<6758> A_IWL<6757> A_IWL<6756> A_IWL<6755> A_IWL<6754> A_IWL<6753> A_IWL<6752> A_IWL<6751> A_IWL<6750> A_IWL<6749> A_IWL<6748> A_IWL<6747> A_IWL<6746> A_IWL<6745> A_IWL<6744> A_IWL<6743> A_IWL<6742> A_IWL<6741> A_IWL<6740> A_IWL<6739> A_IWL<6738> A_IWL<6737> A_IWL<6736> A_IWL<6735> A_IWL<6734> A_IWL<6733> A_IWL<6732> A_IWL<6731> A_IWL<6730> A_IWL<6729> A_IWL<6728> A_IWL<6727> A_IWL<6726> A_IWL<6725> A_IWL<6724> A_IWL<6723> A_IWL<6722> A_IWL<6721> A_IWL<6720> A_IWL<6719> A_IWL<6718> A_IWL<6717> A_IWL<6716> A_IWL<6715> A_IWL<6714> A_IWL<6713> A_IWL<6712> A_IWL<6711> A_IWL<6710> A_IWL<6709> A_IWL<6708> A_IWL<6707> A_IWL<6706> A_IWL<6705> A_IWL<6704> A_IWL<6703> A_IWL<6702> A_IWL<6701> A_IWL<6700> A_IWL<6699> A_IWL<6698> A_IWL<6697> A_IWL<6696> A_IWL<6695> A_IWL<6694> A_IWL<6693> A_IWL<6692> A_IWL<6691> A_IWL<6690> A_IWL<6689> A_IWL<6688> A_IWL<6687> A_IWL<6686> A_IWL<6685> A_IWL<6684> A_IWL<6683> A_IWL<6682> A_IWL<6681> A_IWL<6680> A_IWL<6679> A_IWL<6678> A_IWL<6677> A_IWL<6676> A_IWL<6675> A_IWL<6674> A_IWL<6673> A_IWL<6672> A_IWL<6671> A_IWL<6670> A_IWL<6669> A_IWL<6668> A_IWL<6667> A_IWL<6666> A_IWL<6665> A_IWL<6664> A_IWL<6663> A_IWL<6662> A_IWL<6661> A_IWL<6660> A_IWL<6659> A_IWL<6658> A_IWL<6657> A_IWL<6656> A_IWL<7679> A_IWL<7678> A_IWL<7677> A_IWL<7676> A_IWL<7675> A_IWL<7674> A_IWL<7673> A_IWL<7672> A_IWL<7671> A_IWL<7670> A_IWL<7669> A_IWL<7668> A_IWL<7667> A_IWL<7666> A_IWL<7665> A_IWL<7664> A_IWL<7663> A_IWL<7662> A_IWL<7661> A_IWL<7660> A_IWL<7659> A_IWL<7658> A_IWL<7657> A_IWL<7656> A_IWL<7655> A_IWL<7654> A_IWL<7653> A_IWL<7652> A_IWL<7651> A_IWL<7650> A_IWL<7649> A_IWL<7648> A_IWL<7647> A_IWL<7646> A_IWL<7645> A_IWL<7644> A_IWL<7643> A_IWL<7642> A_IWL<7641> A_IWL<7640> A_IWL<7639> A_IWL<7638> A_IWL<7637> A_IWL<7636> A_IWL<7635> A_IWL<7634> A_IWL<7633> A_IWL<7632> A_IWL<7631> A_IWL<7630> A_IWL<7629> A_IWL<7628> A_IWL<7627> A_IWL<7626> A_IWL<7625> A_IWL<7624> A_IWL<7623> A_IWL<7622> A_IWL<7621> A_IWL<7620> A_IWL<7619> A_IWL<7618> A_IWL<7617> A_IWL<7616> A_IWL<7615> A_IWL<7614> A_IWL<7613> A_IWL<7612> A_IWL<7611> A_IWL<7610> A_IWL<7609> A_IWL<7608> A_IWL<7607> A_IWL<7606> A_IWL<7605> A_IWL<7604> A_IWL<7603> A_IWL<7602> A_IWL<7601> A_IWL<7600> A_IWL<7599> A_IWL<7598> A_IWL<7597> A_IWL<7596> A_IWL<7595> A_IWL<7594> A_IWL<7593> A_IWL<7592> A_IWL<7591> A_IWL<7590> A_IWL<7589> A_IWL<7588> A_IWL<7587> A_IWL<7586> A_IWL<7585> A_IWL<7584> A_IWL<7583> A_IWL<7582> A_IWL<7581> A_IWL<7580> A_IWL<7579> A_IWL<7578> A_IWL<7577> A_IWL<7576> A_IWL<7575> A_IWL<7574> A_IWL<7573> A_IWL<7572> A_IWL<7571> A_IWL<7570> A_IWL<7569> A_IWL<7568> A_IWL<7567> A_IWL<7566> A_IWL<7565> A_IWL<7564> A_IWL<7563> A_IWL<7562> A_IWL<7561> A_IWL<7560> A_IWL<7559> A_IWL<7558> A_IWL<7557> A_IWL<7556> A_IWL<7555> A_IWL<7554> A_IWL<7553> A_IWL<7552> A_IWL<7551> A_IWL<7550> A_IWL<7549> A_IWL<7548> A_IWL<7547> A_IWL<7546> A_IWL<7545> A_IWL<7544> A_IWL<7543> A_IWL<7542> A_IWL<7541> A_IWL<7540> A_IWL<7539> A_IWL<7538> A_IWL<7537> A_IWL<7536> A_IWL<7535> A_IWL<7534> A_IWL<7533> A_IWL<7532> A_IWL<7531> A_IWL<7530> A_IWL<7529> A_IWL<7528> A_IWL<7527> A_IWL<7526> A_IWL<7525> A_IWL<7524> A_IWL<7523> A_IWL<7522> A_IWL<7521> A_IWL<7520> A_IWL<7519> A_IWL<7518> A_IWL<7517> A_IWL<7516> A_IWL<7515> A_IWL<7514> A_IWL<7513> A_IWL<7512> A_IWL<7511> A_IWL<7510> A_IWL<7509> A_IWL<7508> A_IWL<7507> A_IWL<7506> A_IWL<7505> A_IWL<7504> A_IWL<7503> A_IWL<7502> A_IWL<7501> A_IWL<7500> A_IWL<7499> A_IWL<7498> A_IWL<7497> A_IWL<7496> A_IWL<7495> A_IWL<7494> A_IWL<7493> A_IWL<7492> A_IWL<7491> A_IWL<7490> A_IWL<7489> A_IWL<7488> A_IWL<7487> A_IWL<7486> A_IWL<7485> A_IWL<7484> A_IWL<7483> A_IWL<7482> A_IWL<7481> A_IWL<7480> A_IWL<7479> A_IWL<7478> A_IWL<7477> A_IWL<7476> A_IWL<7475> A_IWL<7474> A_IWL<7473> A_IWL<7472> A_IWL<7471> A_IWL<7470> A_IWL<7469> A_IWL<7468> A_IWL<7467> A_IWL<7466> A_IWL<7465> A_IWL<7464> A_IWL<7463> A_IWL<7462> A_IWL<7461> A_IWL<7460> A_IWL<7459> A_IWL<7458> A_IWL<7457> A_IWL<7456> A_IWL<7455> A_IWL<7454> A_IWL<7453> A_IWL<7452> A_IWL<7451> A_IWL<7450> A_IWL<7449> A_IWL<7448> A_IWL<7447> A_IWL<7446> A_IWL<7445> A_IWL<7444> A_IWL<7443> A_IWL<7442> A_IWL<7441> A_IWL<7440> A_IWL<7439> A_IWL<7438> A_IWL<7437> A_IWL<7436> A_IWL<7435> A_IWL<7434> A_IWL<7433> A_IWL<7432> A_IWL<7431> A_IWL<7430> A_IWL<7429> A_IWL<7428> A_IWL<7427> A_IWL<7426> A_IWL<7425> A_IWL<7424> A_IWL<7423> A_IWL<7422> A_IWL<7421> A_IWL<7420> A_IWL<7419> A_IWL<7418> A_IWL<7417> A_IWL<7416> A_IWL<7415> A_IWL<7414> A_IWL<7413> A_IWL<7412> A_IWL<7411> A_IWL<7410> A_IWL<7409> A_IWL<7408> A_IWL<7407> A_IWL<7406> A_IWL<7405> A_IWL<7404> A_IWL<7403> A_IWL<7402> A_IWL<7401> A_IWL<7400> A_IWL<7399> A_IWL<7398> A_IWL<7397> A_IWL<7396> A_IWL<7395> A_IWL<7394> A_IWL<7393> A_IWL<7392> A_IWL<7391> A_IWL<7390> A_IWL<7389> A_IWL<7388> A_IWL<7387> A_IWL<7386> A_IWL<7385> A_IWL<7384> A_IWL<7383> A_IWL<7382> A_IWL<7381> A_IWL<7380> A_IWL<7379> A_IWL<7378> A_IWL<7377> A_IWL<7376> A_IWL<7375> A_IWL<7374> A_IWL<7373> A_IWL<7372> A_IWL<7371> A_IWL<7370> A_IWL<7369> A_IWL<7368> A_IWL<7367> A_IWL<7366> A_IWL<7365> A_IWL<7364> A_IWL<7363> A_IWL<7362> A_IWL<7361> A_IWL<7360> A_IWL<7359> A_IWL<7358> A_IWL<7357> A_IWL<7356> A_IWL<7355> A_IWL<7354> A_IWL<7353> A_IWL<7352> A_IWL<7351> A_IWL<7350> A_IWL<7349> A_IWL<7348> A_IWL<7347> A_IWL<7346> A_IWL<7345> A_IWL<7344> A_IWL<7343> A_IWL<7342> A_IWL<7341> A_IWL<7340> A_IWL<7339> A_IWL<7338> A_IWL<7337> A_IWL<7336> A_IWL<7335> A_IWL<7334> A_IWL<7333> A_IWL<7332> A_IWL<7331> A_IWL<7330> A_IWL<7329> A_IWL<7328> A_IWL<7327> A_IWL<7326> A_IWL<7325> A_IWL<7324> A_IWL<7323> A_IWL<7322> A_IWL<7321> A_IWL<7320> A_IWL<7319> A_IWL<7318> A_IWL<7317> A_IWL<7316> A_IWL<7315> A_IWL<7314> A_IWL<7313> A_IWL<7312> A_IWL<7311> A_IWL<7310> A_IWL<7309> A_IWL<7308> A_IWL<7307> A_IWL<7306> A_IWL<7305> A_IWL<7304> A_IWL<7303> A_IWL<7302> A_IWL<7301> A_IWL<7300> A_IWL<7299> A_IWL<7298> A_IWL<7297> A_IWL<7296> A_IWL<7295> A_IWL<7294> A_IWL<7293> A_IWL<7292> A_IWL<7291> A_IWL<7290> A_IWL<7289> A_IWL<7288> A_IWL<7287> A_IWL<7286> A_IWL<7285> A_IWL<7284> A_IWL<7283> A_IWL<7282> A_IWL<7281> A_IWL<7280> A_IWL<7279> A_IWL<7278> A_IWL<7277> A_IWL<7276> A_IWL<7275> A_IWL<7274> A_IWL<7273> A_IWL<7272> A_IWL<7271> A_IWL<7270> A_IWL<7269> A_IWL<7268> A_IWL<7267> A_IWL<7266> A_IWL<7265> A_IWL<7264> A_IWL<7263> A_IWL<7262> A_IWL<7261> A_IWL<7260> A_IWL<7259> A_IWL<7258> A_IWL<7257> A_IWL<7256> A_IWL<7255> A_IWL<7254> A_IWL<7253> A_IWL<7252> A_IWL<7251> A_IWL<7250> A_IWL<7249> A_IWL<7248> A_IWL<7247> A_IWL<7246> A_IWL<7245> A_IWL<7244> A_IWL<7243> A_IWL<7242> A_IWL<7241> A_IWL<7240> A_IWL<7239> A_IWL<7238> A_IWL<7237> A_IWL<7236> A_IWL<7235> A_IWL<7234> A_IWL<7233> A_IWL<7232> A_IWL<7231> A_IWL<7230> A_IWL<7229> A_IWL<7228> A_IWL<7227> A_IWL<7226> A_IWL<7225> A_IWL<7224> A_IWL<7223> A_IWL<7222> A_IWL<7221> A_IWL<7220> A_IWL<7219> A_IWL<7218> A_IWL<7217> A_IWL<7216> A_IWL<7215> A_IWL<7214> A_IWL<7213> A_IWL<7212> A_IWL<7211> A_IWL<7210> A_IWL<7209> A_IWL<7208> A_IWL<7207> A_IWL<7206> A_IWL<7205> A_IWL<7204> A_IWL<7203> A_IWL<7202> A_IWL<7201> A_IWL<7200> A_IWL<7199> A_IWL<7198> A_IWL<7197> A_IWL<7196> A_IWL<7195> A_IWL<7194> A_IWL<7193> A_IWL<7192> A_IWL<7191> A_IWL<7190> A_IWL<7189> A_IWL<7188> A_IWL<7187> A_IWL<7186> A_IWL<7185> A_IWL<7184> A_IWL<7183> A_IWL<7182> A_IWL<7181> A_IWL<7180> A_IWL<7179> A_IWL<7178> A_IWL<7177> A_IWL<7176> A_IWL<7175> A_IWL<7174> A_IWL<7173> A_IWL<7172> A_IWL<7171> A_IWL<7170> A_IWL<7169> A_IWL<7168> VDD_CORE VSS / RM_IHPSG13_8192x32_c4_1P_COLUMN_pcell_0 +XCOL<13> A_BLC<27> A_BLC<26> A_BLC_TOP<27> A_BLC_TOP<26> A_BLT<27> A_BLT<26> A_BLT_TOP<27> A_BLT_TOP<26> A_IWL<6655> A_IWL<6654> A_IWL<6653> A_IWL<6652> A_IWL<6651> A_IWL<6650> A_IWL<6649> A_IWL<6648> A_IWL<6647> A_IWL<6646> A_IWL<6645> A_IWL<6644> A_IWL<6643> A_IWL<6642> A_IWL<6641> A_IWL<6640> A_IWL<6639> A_IWL<6638> A_IWL<6637> A_IWL<6636> A_IWL<6635> A_IWL<6634> A_IWL<6633> A_IWL<6632> A_IWL<6631> A_IWL<6630> A_IWL<6629> A_IWL<6628> A_IWL<6627> A_IWL<6626> A_IWL<6625> A_IWL<6624> A_IWL<6623> A_IWL<6622> A_IWL<6621> A_IWL<6620> A_IWL<6619> A_IWL<6618> A_IWL<6617> A_IWL<6616> A_IWL<6615> A_IWL<6614> A_IWL<6613> A_IWL<6612> A_IWL<6611> A_IWL<6610> A_IWL<6609> A_IWL<6608> A_IWL<6607> A_IWL<6606> A_IWL<6605> A_IWL<6604> A_IWL<6603> A_IWL<6602> A_IWL<6601> A_IWL<6600> A_IWL<6599> A_IWL<6598> A_IWL<6597> A_IWL<6596> A_IWL<6595> A_IWL<6594> A_IWL<6593> A_IWL<6592> A_IWL<6591> A_IWL<6590> A_IWL<6589> A_IWL<6588> A_IWL<6587> A_IWL<6586> A_IWL<6585> A_IWL<6584> A_IWL<6583> A_IWL<6582> A_IWL<6581> A_IWL<6580> A_IWL<6579> A_IWL<6578> A_IWL<6577> A_IWL<6576> A_IWL<6575> A_IWL<6574> A_IWL<6573> A_IWL<6572> A_IWL<6571> A_IWL<6570> A_IWL<6569> A_IWL<6568> A_IWL<6567> A_IWL<6566> A_IWL<6565> A_IWL<6564> A_IWL<6563> A_IWL<6562> A_IWL<6561> A_IWL<6560> A_IWL<6559> A_IWL<6558> A_IWL<6557> A_IWL<6556> A_IWL<6555> A_IWL<6554> A_IWL<6553> A_IWL<6552> A_IWL<6551> A_IWL<6550> A_IWL<6549> A_IWL<6548> A_IWL<6547> A_IWL<6546> A_IWL<6545> A_IWL<6544> A_IWL<6543> A_IWL<6542> A_IWL<6541> A_IWL<6540> A_IWL<6539> A_IWL<6538> A_IWL<6537> A_IWL<6536> A_IWL<6535> A_IWL<6534> A_IWL<6533> A_IWL<6532> A_IWL<6531> A_IWL<6530> A_IWL<6529> A_IWL<6528> A_IWL<6527> A_IWL<6526> A_IWL<6525> A_IWL<6524> A_IWL<6523> A_IWL<6522> A_IWL<6521> A_IWL<6520> A_IWL<6519> A_IWL<6518> A_IWL<6517> A_IWL<6516> A_IWL<6515> A_IWL<6514> A_IWL<6513> A_IWL<6512> A_IWL<6511> A_IWL<6510> A_IWL<6509> A_IWL<6508> A_IWL<6507> A_IWL<6506> A_IWL<6505> A_IWL<6504> A_IWL<6503> A_IWL<6502> A_IWL<6501> A_IWL<6500> A_IWL<6499> A_IWL<6498> A_IWL<6497> A_IWL<6496> A_IWL<6495> A_IWL<6494> A_IWL<6493> A_IWL<6492> A_IWL<6491> A_IWL<6490> A_IWL<6489> A_IWL<6488> A_IWL<6487> A_IWL<6486> A_IWL<6485> A_IWL<6484> A_IWL<6483> A_IWL<6482> A_IWL<6481> A_IWL<6480> A_IWL<6479> A_IWL<6478> A_IWL<6477> A_IWL<6476> A_IWL<6475> A_IWL<6474> A_IWL<6473> A_IWL<6472> A_IWL<6471> A_IWL<6470> A_IWL<6469> A_IWL<6468> A_IWL<6467> A_IWL<6466> A_IWL<6465> A_IWL<6464> A_IWL<6463> A_IWL<6462> A_IWL<6461> A_IWL<6460> A_IWL<6459> A_IWL<6458> A_IWL<6457> A_IWL<6456> A_IWL<6455> A_IWL<6454> A_IWL<6453> A_IWL<6452> A_IWL<6451> A_IWL<6450> A_IWL<6449> A_IWL<6448> A_IWL<6447> A_IWL<6446> A_IWL<6445> A_IWL<6444> A_IWL<6443> A_IWL<6442> A_IWL<6441> A_IWL<6440> A_IWL<6439> A_IWL<6438> A_IWL<6437> A_IWL<6436> A_IWL<6435> A_IWL<6434> A_IWL<6433> A_IWL<6432> A_IWL<6431> A_IWL<6430> A_IWL<6429> A_IWL<6428> A_IWL<6427> A_IWL<6426> A_IWL<6425> A_IWL<6424> A_IWL<6423> A_IWL<6422> A_IWL<6421> A_IWL<6420> A_IWL<6419> A_IWL<6418> A_IWL<6417> A_IWL<6416> A_IWL<6415> A_IWL<6414> A_IWL<6413> A_IWL<6412> A_IWL<6411> A_IWL<6410> A_IWL<6409> A_IWL<6408> A_IWL<6407> A_IWL<6406> A_IWL<6405> A_IWL<6404> A_IWL<6403> A_IWL<6402> A_IWL<6401> A_IWL<6400> A_IWL<6399> A_IWL<6398> A_IWL<6397> A_IWL<6396> A_IWL<6395> A_IWL<6394> A_IWL<6393> A_IWL<6392> A_IWL<6391> A_IWL<6390> A_IWL<6389> A_IWL<6388> A_IWL<6387> A_IWL<6386> A_IWL<6385> A_IWL<6384> A_IWL<6383> A_IWL<6382> A_IWL<6381> A_IWL<6380> A_IWL<6379> A_IWL<6378> A_IWL<6377> A_IWL<6376> A_IWL<6375> A_IWL<6374> A_IWL<6373> A_IWL<6372> A_IWL<6371> A_IWL<6370> A_IWL<6369> A_IWL<6368> A_IWL<6367> A_IWL<6366> A_IWL<6365> A_IWL<6364> A_IWL<6363> A_IWL<6362> A_IWL<6361> A_IWL<6360> A_IWL<6359> A_IWL<6358> A_IWL<6357> A_IWL<6356> A_IWL<6355> A_IWL<6354> A_IWL<6353> A_IWL<6352> A_IWL<6351> A_IWL<6350> A_IWL<6349> A_IWL<6348> A_IWL<6347> A_IWL<6346> A_IWL<6345> A_IWL<6344> A_IWL<6343> A_IWL<6342> A_IWL<6341> A_IWL<6340> A_IWL<6339> A_IWL<6338> A_IWL<6337> A_IWL<6336> A_IWL<6335> A_IWL<6334> A_IWL<6333> A_IWL<6332> A_IWL<6331> A_IWL<6330> A_IWL<6329> A_IWL<6328> A_IWL<6327> A_IWL<6326> A_IWL<6325> A_IWL<6324> A_IWL<6323> A_IWL<6322> A_IWL<6321> A_IWL<6320> A_IWL<6319> A_IWL<6318> A_IWL<6317> A_IWL<6316> A_IWL<6315> A_IWL<6314> A_IWL<6313> A_IWL<6312> A_IWL<6311> A_IWL<6310> A_IWL<6309> A_IWL<6308> A_IWL<6307> A_IWL<6306> A_IWL<6305> A_IWL<6304> A_IWL<6303> A_IWL<6302> A_IWL<6301> A_IWL<6300> A_IWL<6299> A_IWL<6298> A_IWL<6297> A_IWL<6296> A_IWL<6295> A_IWL<6294> A_IWL<6293> A_IWL<6292> A_IWL<6291> A_IWL<6290> A_IWL<6289> A_IWL<6288> A_IWL<6287> A_IWL<6286> A_IWL<6285> A_IWL<6284> A_IWL<6283> A_IWL<6282> A_IWL<6281> A_IWL<6280> A_IWL<6279> A_IWL<6278> A_IWL<6277> A_IWL<6276> A_IWL<6275> A_IWL<6274> A_IWL<6273> A_IWL<6272> A_IWL<6271> A_IWL<6270> A_IWL<6269> A_IWL<6268> A_IWL<6267> A_IWL<6266> A_IWL<6265> A_IWL<6264> A_IWL<6263> A_IWL<6262> A_IWL<6261> A_IWL<6260> A_IWL<6259> A_IWL<6258> A_IWL<6257> A_IWL<6256> A_IWL<6255> A_IWL<6254> A_IWL<6253> A_IWL<6252> A_IWL<6251> A_IWL<6250> A_IWL<6249> A_IWL<6248> A_IWL<6247> A_IWL<6246> A_IWL<6245> A_IWL<6244> A_IWL<6243> A_IWL<6242> A_IWL<6241> A_IWL<6240> A_IWL<6239> A_IWL<6238> A_IWL<6237> A_IWL<6236> A_IWL<6235> A_IWL<6234> A_IWL<6233> A_IWL<6232> A_IWL<6231> A_IWL<6230> A_IWL<6229> A_IWL<6228> A_IWL<6227> A_IWL<6226> A_IWL<6225> A_IWL<6224> A_IWL<6223> A_IWL<6222> A_IWL<6221> A_IWL<6220> A_IWL<6219> A_IWL<6218> A_IWL<6217> A_IWL<6216> A_IWL<6215> A_IWL<6214> A_IWL<6213> A_IWL<6212> A_IWL<6211> A_IWL<6210> A_IWL<6209> A_IWL<6208> A_IWL<6207> A_IWL<6206> A_IWL<6205> A_IWL<6204> A_IWL<6203> A_IWL<6202> A_IWL<6201> A_IWL<6200> A_IWL<6199> A_IWL<6198> A_IWL<6197> A_IWL<6196> A_IWL<6195> A_IWL<6194> A_IWL<6193> A_IWL<6192> A_IWL<6191> A_IWL<6190> A_IWL<6189> A_IWL<6188> A_IWL<6187> A_IWL<6186> A_IWL<6185> A_IWL<6184> A_IWL<6183> A_IWL<6182> A_IWL<6181> A_IWL<6180> A_IWL<6179> A_IWL<6178> A_IWL<6177> A_IWL<6176> A_IWL<6175> A_IWL<6174> A_IWL<6173> A_IWL<6172> A_IWL<6171> A_IWL<6170> A_IWL<6169> A_IWL<6168> A_IWL<6167> A_IWL<6166> A_IWL<6165> A_IWL<6164> A_IWL<6163> A_IWL<6162> A_IWL<6161> A_IWL<6160> A_IWL<6159> A_IWL<6158> A_IWL<6157> A_IWL<6156> A_IWL<6155> A_IWL<6154> A_IWL<6153> A_IWL<6152> A_IWL<6151> A_IWL<6150> A_IWL<6149> A_IWL<6148> A_IWL<6147> A_IWL<6146> A_IWL<6145> A_IWL<6144> A_IWL<7167> A_IWL<7166> A_IWL<7165> A_IWL<7164> A_IWL<7163> A_IWL<7162> A_IWL<7161> A_IWL<7160> A_IWL<7159> A_IWL<7158> A_IWL<7157> A_IWL<7156> A_IWL<7155> A_IWL<7154> A_IWL<7153> A_IWL<7152> A_IWL<7151> A_IWL<7150> A_IWL<7149> A_IWL<7148> A_IWL<7147> A_IWL<7146> A_IWL<7145> A_IWL<7144> A_IWL<7143> A_IWL<7142> A_IWL<7141> A_IWL<7140> A_IWL<7139> A_IWL<7138> A_IWL<7137> A_IWL<7136> A_IWL<7135> A_IWL<7134> A_IWL<7133> A_IWL<7132> A_IWL<7131> A_IWL<7130> A_IWL<7129> A_IWL<7128> A_IWL<7127> A_IWL<7126> A_IWL<7125> A_IWL<7124> A_IWL<7123> A_IWL<7122> A_IWL<7121> A_IWL<7120> A_IWL<7119> A_IWL<7118> A_IWL<7117> A_IWL<7116> A_IWL<7115> A_IWL<7114> A_IWL<7113> A_IWL<7112> A_IWL<7111> A_IWL<7110> A_IWL<7109> A_IWL<7108> A_IWL<7107> A_IWL<7106> A_IWL<7105> A_IWL<7104> A_IWL<7103> A_IWL<7102> A_IWL<7101> A_IWL<7100> A_IWL<7099> A_IWL<7098> A_IWL<7097> A_IWL<7096> A_IWL<7095> A_IWL<7094> A_IWL<7093> A_IWL<7092> A_IWL<7091> A_IWL<7090> A_IWL<7089> A_IWL<7088> A_IWL<7087> A_IWL<7086> A_IWL<7085> A_IWL<7084> A_IWL<7083> A_IWL<7082> A_IWL<7081> A_IWL<7080> A_IWL<7079> A_IWL<7078> A_IWL<7077> A_IWL<7076> A_IWL<7075> A_IWL<7074> A_IWL<7073> A_IWL<7072> A_IWL<7071> A_IWL<7070> A_IWL<7069> A_IWL<7068> A_IWL<7067> A_IWL<7066> A_IWL<7065> A_IWL<7064> A_IWL<7063> A_IWL<7062> A_IWL<7061> A_IWL<7060> A_IWL<7059> A_IWL<7058> A_IWL<7057> A_IWL<7056> A_IWL<7055> A_IWL<7054> A_IWL<7053> A_IWL<7052> A_IWL<7051> A_IWL<7050> A_IWL<7049> A_IWL<7048> A_IWL<7047> A_IWL<7046> A_IWL<7045> A_IWL<7044> A_IWL<7043> A_IWL<7042> A_IWL<7041> A_IWL<7040> A_IWL<7039> A_IWL<7038> A_IWL<7037> A_IWL<7036> A_IWL<7035> A_IWL<7034> A_IWL<7033> A_IWL<7032> A_IWL<7031> A_IWL<7030> A_IWL<7029> A_IWL<7028> A_IWL<7027> A_IWL<7026> A_IWL<7025> A_IWL<7024> A_IWL<7023> A_IWL<7022> A_IWL<7021> A_IWL<7020> A_IWL<7019> A_IWL<7018> A_IWL<7017> A_IWL<7016> A_IWL<7015> A_IWL<7014> A_IWL<7013> A_IWL<7012> A_IWL<7011> A_IWL<7010> A_IWL<7009> A_IWL<7008> A_IWL<7007> A_IWL<7006> A_IWL<7005> A_IWL<7004> A_IWL<7003> A_IWL<7002> A_IWL<7001> A_IWL<7000> A_IWL<6999> A_IWL<6998> A_IWL<6997> A_IWL<6996> A_IWL<6995> A_IWL<6994> A_IWL<6993> A_IWL<6992> A_IWL<6991> A_IWL<6990> A_IWL<6989> A_IWL<6988> A_IWL<6987> A_IWL<6986> A_IWL<6985> A_IWL<6984> A_IWL<6983> A_IWL<6982> A_IWL<6981> A_IWL<6980> A_IWL<6979> A_IWL<6978> A_IWL<6977> A_IWL<6976> A_IWL<6975> A_IWL<6974> A_IWL<6973> A_IWL<6972> A_IWL<6971> A_IWL<6970> A_IWL<6969> A_IWL<6968> A_IWL<6967> A_IWL<6966> A_IWL<6965> A_IWL<6964> A_IWL<6963> A_IWL<6962> A_IWL<6961> A_IWL<6960> A_IWL<6959> A_IWL<6958> A_IWL<6957> A_IWL<6956> A_IWL<6955> A_IWL<6954> A_IWL<6953> A_IWL<6952> A_IWL<6951> A_IWL<6950> A_IWL<6949> A_IWL<6948> A_IWL<6947> A_IWL<6946> A_IWL<6945> A_IWL<6944> A_IWL<6943> A_IWL<6942> A_IWL<6941> A_IWL<6940> A_IWL<6939> A_IWL<6938> A_IWL<6937> A_IWL<6936> A_IWL<6935> A_IWL<6934> A_IWL<6933> A_IWL<6932> A_IWL<6931> A_IWL<6930> A_IWL<6929> A_IWL<6928> A_IWL<6927> A_IWL<6926> A_IWL<6925> A_IWL<6924> A_IWL<6923> A_IWL<6922> A_IWL<6921> A_IWL<6920> A_IWL<6919> A_IWL<6918> A_IWL<6917> A_IWL<6916> A_IWL<6915> A_IWL<6914> A_IWL<6913> A_IWL<6912> A_IWL<6911> A_IWL<6910> A_IWL<6909> A_IWL<6908> A_IWL<6907> A_IWL<6906> A_IWL<6905> A_IWL<6904> A_IWL<6903> A_IWL<6902> A_IWL<6901> A_IWL<6900> A_IWL<6899> A_IWL<6898> A_IWL<6897> A_IWL<6896> A_IWL<6895> A_IWL<6894> A_IWL<6893> A_IWL<6892> A_IWL<6891> A_IWL<6890> A_IWL<6889> A_IWL<6888> A_IWL<6887> A_IWL<6886> A_IWL<6885> A_IWL<6884> A_IWL<6883> A_IWL<6882> A_IWL<6881> A_IWL<6880> A_IWL<6879> A_IWL<6878> A_IWL<6877> A_IWL<6876> A_IWL<6875> A_IWL<6874> A_IWL<6873> A_IWL<6872> A_IWL<6871> A_IWL<6870> A_IWL<6869> A_IWL<6868> A_IWL<6867> A_IWL<6866> A_IWL<6865> A_IWL<6864> A_IWL<6863> A_IWL<6862> A_IWL<6861> A_IWL<6860> A_IWL<6859> A_IWL<6858> A_IWL<6857> A_IWL<6856> A_IWL<6855> A_IWL<6854> A_IWL<6853> A_IWL<6852> A_IWL<6851> A_IWL<6850> A_IWL<6849> A_IWL<6848> A_IWL<6847> A_IWL<6846> A_IWL<6845> A_IWL<6844> A_IWL<6843> A_IWL<6842> A_IWL<6841> A_IWL<6840> A_IWL<6839> A_IWL<6838> A_IWL<6837> A_IWL<6836> A_IWL<6835> A_IWL<6834> A_IWL<6833> A_IWL<6832> A_IWL<6831> A_IWL<6830> A_IWL<6829> A_IWL<6828> A_IWL<6827> A_IWL<6826> A_IWL<6825> A_IWL<6824> A_IWL<6823> A_IWL<6822> A_IWL<6821> A_IWL<6820> A_IWL<6819> A_IWL<6818> A_IWL<6817> A_IWL<6816> A_IWL<6815> A_IWL<6814> A_IWL<6813> A_IWL<6812> A_IWL<6811> A_IWL<6810> A_IWL<6809> A_IWL<6808> A_IWL<6807> A_IWL<6806> A_IWL<6805> A_IWL<6804> A_IWL<6803> A_IWL<6802> A_IWL<6801> A_IWL<6800> A_IWL<6799> A_IWL<6798> A_IWL<6797> A_IWL<6796> A_IWL<6795> A_IWL<6794> A_IWL<6793> A_IWL<6792> A_IWL<6791> A_IWL<6790> A_IWL<6789> A_IWL<6788> A_IWL<6787> A_IWL<6786> A_IWL<6785> A_IWL<6784> A_IWL<6783> A_IWL<6782> A_IWL<6781> A_IWL<6780> A_IWL<6779> A_IWL<6778> A_IWL<6777> A_IWL<6776> A_IWL<6775> A_IWL<6774> A_IWL<6773> A_IWL<6772> A_IWL<6771> A_IWL<6770> A_IWL<6769> A_IWL<6768> A_IWL<6767> A_IWL<6766> A_IWL<6765> A_IWL<6764> A_IWL<6763> A_IWL<6762> A_IWL<6761> A_IWL<6760> A_IWL<6759> A_IWL<6758> A_IWL<6757> A_IWL<6756> A_IWL<6755> A_IWL<6754> A_IWL<6753> A_IWL<6752> A_IWL<6751> A_IWL<6750> A_IWL<6749> A_IWL<6748> A_IWL<6747> A_IWL<6746> A_IWL<6745> A_IWL<6744> A_IWL<6743> A_IWL<6742> A_IWL<6741> A_IWL<6740> A_IWL<6739> A_IWL<6738> A_IWL<6737> A_IWL<6736> A_IWL<6735> A_IWL<6734> A_IWL<6733> A_IWL<6732> A_IWL<6731> A_IWL<6730> A_IWL<6729> A_IWL<6728> A_IWL<6727> A_IWL<6726> A_IWL<6725> A_IWL<6724> A_IWL<6723> A_IWL<6722> A_IWL<6721> A_IWL<6720> A_IWL<6719> A_IWL<6718> A_IWL<6717> A_IWL<6716> A_IWL<6715> A_IWL<6714> A_IWL<6713> A_IWL<6712> A_IWL<6711> A_IWL<6710> A_IWL<6709> A_IWL<6708> A_IWL<6707> A_IWL<6706> A_IWL<6705> A_IWL<6704> A_IWL<6703> A_IWL<6702> A_IWL<6701> A_IWL<6700> A_IWL<6699> A_IWL<6698> A_IWL<6697> A_IWL<6696> A_IWL<6695> A_IWL<6694> A_IWL<6693> A_IWL<6692> A_IWL<6691> A_IWL<6690> A_IWL<6689> A_IWL<6688> A_IWL<6687> A_IWL<6686> A_IWL<6685> A_IWL<6684> A_IWL<6683> A_IWL<6682> A_IWL<6681> A_IWL<6680> A_IWL<6679> A_IWL<6678> A_IWL<6677> A_IWL<6676> A_IWL<6675> A_IWL<6674> A_IWL<6673> A_IWL<6672> A_IWL<6671> A_IWL<6670> A_IWL<6669> A_IWL<6668> A_IWL<6667> A_IWL<6666> A_IWL<6665> A_IWL<6664> A_IWL<6663> A_IWL<6662> A_IWL<6661> A_IWL<6660> A_IWL<6659> A_IWL<6658> A_IWL<6657> A_IWL<6656> VDD_CORE VSS / RM_IHPSG13_8192x32_c4_1P_COLUMN_pcell_0 +XCOL<12> A_BLC<25> A_BLC<24> A_BLC_TOP<25> A_BLC_TOP<24> A_BLT<25> A_BLT<24> A_BLT_TOP<25> A_BLT_TOP<24> A_IWL<6143> A_IWL<6142> A_IWL<6141> A_IWL<6140> A_IWL<6139> A_IWL<6138> A_IWL<6137> A_IWL<6136> A_IWL<6135> A_IWL<6134> A_IWL<6133> A_IWL<6132> A_IWL<6131> A_IWL<6130> A_IWL<6129> A_IWL<6128> A_IWL<6127> A_IWL<6126> A_IWL<6125> A_IWL<6124> A_IWL<6123> A_IWL<6122> A_IWL<6121> A_IWL<6120> A_IWL<6119> A_IWL<6118> A_IWL<6117> A_IWL<6116> A_IWL<6115> A_IWL<6114> A_IWL<6113> A_IWL<6112> A_IWL<6111> A_IWL<6110> A_IWL<6109> A_IWL<6108> A_IWL<6107> A_IWL<6106> A_IWL<6105> A_IWL<6104> A_IWL<6103> A_IWL<6102> A_IWL<6101> A_IWL<6100> A_IWL<6099> A_IWL<6098> A_IWL<6097> A_IWL<6096> A_IWL<6095> A_IWL<6094> A_IWL<6093> A_IWL<6092> A_IWL<6091> A_IWL<6090> A_IWL<6089> A_IWL<6088> A_IWL<6087> A_IWL<6086> A_IWL<6085> A_IWL<6084> A_IWL<6083> A_IWL<6082> A_IWL<6081> A_IWL<6080> A_IWL<6079> A_IWL<6078> A_IWL<6077> A_IWL<6076> A_IWL<6075> A_IWL<6074> A_IWL<6073> A_IWL<6072> A_IWL<6071> A_IWL<6070> A_IWL<6069> A_IWL<6068> A_IWL<6067> A_IWL<6066> A_IWL<6065> A_IWL<6064> A_IWL<6063> A_IWL<6062> A_IWL<6061> A_IWL<6060> A_IWL<6059> A_IWL<6058> A_IWL<6057> A_IWL<6056> A_IWL<6055> A_IWL<6054> A_IWL<6053> A_IWL<6052> A_IWL<6051> A_IWL<6050> A_IWL<6049> A_IWL<6048> A_IWL<6047> A_IWL<6046> A_IWL<6045> A_IWL<6044> A_IWL<6043> A_IWL<6042> A_IWL<6041> A_IWL<6040> A_IWL<6039> A_IWL<6038> A_IWL<6037> A_IWL<6036> A_IWL<6035> A_IWL<6034> A_IWL<6033> A_IWL<6032> A_IWL<6031> A_IWL<6030> A_IWL<6029> A_IWL<6028> A_IWL<6027> A_IWL<6026> A_IWL<6025> A_IWL<6024> A_IWL<6023> A_IWL<6022> A_IWL<6021> A_IWL<6020> A_IWL<6019> A_IWL<6018> A_IWL<6017> A_IWL<6016> A_IWL<6015> A_IWL<6014> A_IWL<6013> A_IWL<6012> A_IWL<6011> A_IWL<6010> A_IWL<6009> A_IWL<6008> A_IWL<6007> A_IWL<6006> A_IWL<6005> A_IWL<6004> A_IWL<6003> A_IWL<6002> A_IWL<6001> A_IWL<6000> A_IWL<5999> A_IWL<5998> A_IWL<5997> A_IWL<5996> A_IWL<5995> A_IWL<5994> A_IWL<5993> A_IWL<5992> A_IWL<5991> A_IWL<5990> A_IWL<5989> A_IWL<5988> A_IWL<5987> A_IWL<5986> A_IWL<5985> A_IWL<5984> A_IWL<5983> A_IWL<5982> A_IWL<5981> A_IWL<5980> A_IWL<5979> A_IWL<5978> A_IWL<5977> A_IWL<5976> A_IWL<5975> A_IWL<5974> A_IWL<5973> A_IWL<5972> A_IWL<5971> A_IWL<5970> A_IWL<5969> A_IWL<5968> A_IWL<5967> A_IWL<5966> A_IWL<5965> A_IWL<5964> A_IWL<5963> A_IWL<5962> A_IWL<5961> A_IWL<5960> A_IWL<5959> A_IWL<5958> A_IWL<5957> A_IWL<5956> A_IWL<5955> A_IWL<5954> A_IWL<5953> A_IWL<5952> A_IWL<5951> A_IWL<5950> A_IWL<5949> A_IWL<5948> A_IWL<5947> A_IWL<5946> A_IWL<5945> A_IWL<5944> A_IWL<5943> A_IWL<5942> A_IWL<5941> A_IWL<5940> A_IWL<5939> A_IWL<5938> A_IWL<5937> A_IWL<5936> A_IWL<5935> A_IWL<5934> A_IWL<5933> A_IWL<5932> A_IWL<5931> A_IWL<5930> A_IWL<5929> A_IWL<5928> A_IWL<5927> A_IWL<5926> A_IWL<5925> A_IWL<5924> A_IWL<5923> A_IWL<5922> A_IWL<5921> A_IWL<5920> A_IWL<5919> A_IWL<5918> A_IWL<5917> A_IWL<5916> A_IWL<5915> A_IWL<5914> A_IWL<5913> A_IWL<5912> A_IWL<5911> A_IWL<5910> A_IWL<5909> A_IWL<5908> A_IWL<5907> A_IWL<5906> A_IWL<5905> A_IWL<5904> A_IWL<5903> A_IWL<5902> A_IWL<5901> A_IWL<5900> A_IWL<5899> A_IWL<5898> A_IWL<5897> A_IWL<5896> A_IWL<5895> A_IWL<5894> A_IWL<5893> A_IWL<5892> A_IWL<5891> A_IWL<5890> A_IWL<5889> A_IWL<5888> A_IWL<5887> A_IWL<5886> A_IWL<5885> A_IWL<5884> A_IWL<5883> A_IWL<5882> A_IWL<5881> A_IWL<5880> A_IWL<5879> A_IWL<5878> A_IWL<5877> A_IWL<5876> A_IWL<5875> A_IWL<5874> A_IWL<5873> A_IWL<5872> A_IWL<5871> A_IWL<5870> A_IWL<5869> A_IWL<5868> A_IWL<5867> A_IWL<5866> A_IWL<5865> A_IWL<5864> A_IWL<5863> A_IWL<5862> A_IWL<5861> A_IWL<5860> A_IWL<5859> A_IWL<5858> A_IWL<5857> A_IWL<5856> A_IWL<5855> A_IWL<5854> A_IWL<5853> A_IWL<5852> A_IWL<5851> A_IWL<5850> A_IWL<5849> A_IWL<5848> A_IWL<5847> A_IWL<5846> A_IWL<5845> A_IWL<5844> A_IWL<5843> A_IWL<5842> A_IWL<5841> A_IWL<5840> A_IWL<5839> A_IWL<5838> A_IWL<5837> A_IWL<5836> A_IWL<5835> A_IWL<5834> A_IWL<5833> A_IWL<5832> A_IWL<5831> A_IWL<5830> A_IWL<5829> A_IWL<5828> A_IWL<5827> A_IWL<5826> A_IWL<5825> A_IWL<5824> A_IWL<5823> A_IWL<5822> A_IWL<5821> A_IWL<5820> A_IWL<5819> A_IWL<5818> A_IWL<5817> A_IWL<5816> A_IWL<5815> A_IWL<5814> A_IWL<5813> A_IWL<5812> A_IWL<5811> A_IWL<5810> A_IWL<5809> A_IWL<5808> A_IWL<5807> A_IWL<5806> A_IWL<5805> A_IWL<5804> A_IWL<5803> A_IWL<5802> A_IWL<5801> A_IWL<5800> A_IWL<5799> A_IWL<5798> A_IWL<5797> A_IWL<5796> A_IWL<5795> A_IWL<5794> A_IWL<5793> A_IWL<5792> A_IWL<5791> A_IWL<5790> A_IWL<5789> A_IWL<5788> A_IWL<5787> A_IWL<5786> A_IWL<5785> A_IWL<5784> A_IWL<5783> A_IWL<5782> A_IWL<5781> A_IWL<5780> A_IWL<5779> A_IWL<5778> A_IWL<5777> A_IWL<5776> A_IWL<5775> A_IWL<5774> A_IWL<5773> A_IWL<5772> A_IWL<5771> A_IWL<5770> A_IWL<5769> A_IWL<5768> A_IWL<5767> A_IWL<5766> A_IWL<5765> A_IWL<5764> A_IWL<5763> A_IWL<5762> A_IWL<5761> A_IWL<5760> A_IWL<5759> A_IWL<5758> A_IWL<5757> A_IWL<5756> A_IWL<5755> A_IWL<5754> A_IWL<5753> A_IWL<5752> A_IWL<5751> A_IWL<5750> A_IWL<5749> A_IWL<5748> A_IWL<5747> A_IWL<5746> A_IWL<5745> A_IWL<5744> A_IWL<5743> A_IWL<5742> A_IWL<5741> A_IWL<5740> A_IWL<5739> A_IWL<5738> A_IWL<5737> A_IWL<5736> A_IWL<5735> A_IWL<5734> A_IWL<5733> A_IWL<5732> A_IWL<5731> A_IWL<5730> A_IWL<5729> A_IWL<5728> A_IWL<5727> A_IWL<5726> A_IWL<5725> A_IWL<5724> A_IWL<5723> A_IWL<5722> A_IWL<5721> A_IWL<5720> A_IWL<5719> A_IWL<5718> A_IWL<5717> A_IWL<5716> A_IWL<5715> A_IWL<5714> A_IWL<5713> A_IWL<5712> A_IWL<5711> A_IWL<5710> A_IWL<5709> A_IWL<5708> A_IWL<5707> A_IWL<5706> A_IWL<5705> A_IWL<5704> A_IWL<5703> A_IWL<5702> A_IWL<5701> A_IWL<5700> A_IWL<5699> A_IWL<5698> A_IWL<5697> A_IWL<5696> A_IWL<5695> A_IWL<5694> A_IWL<5693> A_IWL<5692> A_IWL<5691> A_IWL<5690> A_IWL<5689> A_IWL<5688> A_IWL<5687> A_IWL<5686> A_IWL<5685> A_IWL<5684> A_IWL<5683> A_IWL<5682> A_IWL<5681> A_IWL<5680> A_IWL<5679> A_IWL<5678> A_IWL<5677> A_IWL<5676> A_IWL<5675> A_IWL<5674> A_IWL<5673> A_IWL<5672> A_IWL<5671> A_IWL<5670> A_IWL<5669> A_IWL<5668> A_IWL<5667> A_IWL<5666> A_IWL<5665> A_IWL<5664> A_IWL<5663> A_IWL<5662> A_IWL<5661> A_IWL<5660> A_IWL<5659> A_IWL<5658> A_IWL<5657> A_IWL<5656> A_IWL<5655> A_IWL<5654> A_IWL<5653> A_IWL<5652> A_IWL<5651> A_IWL<5650> A_IWL<5649> A_IWL<5648> A_IWL<5647> A_IWL<5646> A_IWL<5645> A_IWL<5644> A_IWL<5643> A_IWL<5642> A_IWL<5641> A_IWL<5640> A_IWL<5639> A_IWL<5638> A_IWL<5637> A_IWL<5636> A_IWL<5635> A_IWL<5634> A_IWL<5633> A_IWL<5632> A_IWL<6655> A_IWL<6654> A_IWL<6653> A_IWL<6652> A_IWL<6651> A_IWL<6650> A_IWL<6649> A_IWL<6648> A_IWL<6647> A_IWL<6646> A_IWL<6645> A_IWL<6644> A_IWL<6643> A_IWL<6642> A_IWL<6641> A_IWL<6640> A_IWL<6639> A_IWL<6638> A_IWL<6637> A_IWL<6636> A_IWL<6635> A_IWL<6634> A_IWL<6633> A_IWL<6632> A_IWL<6631> A_IWL<6630> A_IWL<6629> A_IWL<6628> A_IWL<6627> A_IWL<6626> A_IWL<6625> A_IWL<6624> A_IWL<6623> A_IWL<6622> A_IWL<6621> A_IWL<6620> A_IWL<6619> A_IWL<6618> A_IWL<6617> A_IWL<6616> A_IWL<6615> A_IWL<6614> A_IWL<6613> A_IWL<6612> A_IWL<6611> A_IWL<6610> A_IWL<6609> A_IWL<6608> A_IWL<6607> A_IWL<6606> A_IWL<6605> A_IWL<6604> A_IWL<6603> A_IWL<6602> A_IWL<6601> A_IWL<6600> A_IWL<6599> A_IWL<6598> A_IWL<6597> A_IWL<6596> A_IWL<6595> A_IWL<6594> A_IWL<6593> A_IWL<6592> A_IWL<6591> A_IWL<6590> A_IWL<6589> A_IWL<6588> A_IWL<6587> A_IWL<6586> A_IWL<6585> A_IWL<6584> A_IWL<6583> A_IWL<6582> A_IWL<6581> A_IWL<6580> A_IWL<6579> A_IWL<6578> A_IWL<6577> A_IWL<6576> A_IWL<6575> A_IWL<6574> A_IWL<6573> A_IWL<6572> A_IWL<6571> A_IWL<6570> A_IWL<6569> A_IWL<6568> A_IWL<6567> A_IWL<6566> A_IWL<6565> A_IWL<6564> A_IWL<6563> A_IWL<6562> A_IWL<6561> A_IWL<6560> A_IWL<6559> A_IWL<6558> A_IWL<6557> A_IWL<6556> A_IWL<6555> A_IWL<6554> A_IWL<6553> A_IWL<6552> A_IWL<6551> A_IWL<6550> A_IWL<6549> A_IWL<6548> A_IWL<6547> A_IWL<6546> A_IWL<6545> A_IWL<6544> A_IWL<6543> A_IWL<6542> A_IWL<6541> A_IWL<6540> A_IWL<6539> A_IWL<6538> A_IWL<6537> A_IWL<6536> A_IWL<6535> A_IWL<6534> A_IWL<6533> A_IWL<6532> A_IWL<6531> A_IWL<6530> A_IWL<6529> A_IWL<6528> A_IWL<6527> A_IWL<6526> A_IWL<6525> A_IWL<6524> A_IWL<6523> A_IWL<6522> A_IWL<6521> A_IWL<6520> A_IWL<6519> A_IWL<6518> A_IWL<6517> A_IWL<6516> A_IWL<6515> A_IWL<6514> A_IWL<6513> A_IWL<6512> A_IWL<6511> A_IWL<6510> A_IWL<6509> A_IWL<6508> A_IWL<6507> A_IWL<6506> A_IWL<6505> A_IWL<6504> A_IWL<6503> A_IWL<6502> A_IWL<6501> A_IWL<6500> A_IWL<6499> A_IWL<6498> A_IWL<6497> A_IWL<6496> A_IWL<6495> A_IWL<6494> A_IWL<6493> A_IWL<6492> A_IWL<6491> A_IWL<6490> A_IWL<6489> A_IWL<6488> A_IWL<6487> A_IWL<6486> A_IWL<6485> A_IWL<6484> A_IWL<6483> A_IWL<6482> A_IWL<6481> A_IWL<6480> A_IWL<6479> A_IWL<6478> A_IWL<6477> A_IWL<6476> A_IWL<6475> A_IWL<6474> A_IWL<6473> A_IWL<6472> A_IWL<6471> A_IWL<6470> A_IWL<6469> A_IWL<6468> A_IWL<6467> A_IWL<6466> A_IWL<6465> A_IWL<6464> A_IWL<6463> A_IWL<6462> A_IWL<6461> A_IWL<6460> A_IWL<6459> A_IWL<6458> A_IWL<6457> A_IWL<6456> A_IWL<6455> A_IWL<6454> A_IWL<6453> A_IWL<6452> A_IWL<6451> A_IWL<6450> A_IWL<6449> A_IWL<6448> A_IWL<6447> A_IWL<6446> A_IWL<6445> A_IWL<6444> A_IWL<6443> A_IWL<6442> A_IWL<6441> A_IWL<6440> A_IWL<6439> A_IWL<6438> A_IWL<6437> A_IWL<6436> A_IWL<6435> A_IWL<6434> A_IWL<6433> A_IWL<6432> A_IWL<6431> A_IWL<6430> A_IWL<6429> A_IWL<6428> A_IWL<6427> A_IWL<6426> A_IWL<6425> A_IWL<6424> A_IWL<6423> A_IWL<6422> A_IWL<6421> A_IWL<6420> A_IWL<6419> A_IWL<6418> A_IWL<6417> A_IWL<6416> A_IWL<6415> A_IWL<6414> A_IWL<6413> A_IWL<6412> A_IWL<6411> A_IWL<6410> A_IWL<6409> A_IWL<6408> A_IWL<6407> A_IWL<6406> A_IWL<6405> A_IWL<6404> A_IWL<6403> A_IWL<6402> A_IWL<6401> A_IWL<6400> A_IWL<6399> A_IWL<6398> A_IWL<6397> A_IWL<6396> A_IWL<6395> A_IWL<6394> A_IWL<6393> A_IWL<6392> A_IWL<6391> A_IWL<6390> A_IWL<6389> A_IWL<6388> A_IWL<6387> A_IWL<6386> A_IWL<6385> A_IWL<6384> A_IWL<6383> A_IWL<6382> A_IWL<6381> A_IWL<6380> A_IWL<6379> A_IWL<6378> A_IWL<6377> A_IWL<6376> A_IWL<6375> A_IWL<6374> A_IWL<6373> A_IWL<6372> A_IWL<6371> A_IWL<6370> A_IWL<6369> A_IWL<6368> A_IWL<6367> A_IWL<6366> A_IWL<6365> A_IWL<6364> A_IWL<6363> A_IWL<6362> A_IWL<6361> A_IWL<6360> A_IWL<6359> A_IWL<6358> A_IWL<6357> A_IWL<6356> A_IWL<6355> A_IWL<6354> A_IWL<6353> A_IWL<6352> A_IWL<6351> A_IWL<6350> A_IWL<6349> A_IWL<6348> A_IWL<6347> A_IWL<6346> A_IWL<6345> A_IWL<6344> A_IWL<6343> A_IWL<6342> A_IWL<6341> A_IWL<6340> A_IWL<6339> A_IWL<6338> A_IWL<6337> A_IWL<6336> A_IWL<6335> A_IWL<6334> A_IWL<6333> A_IWL<6332> A_IWL<6331> A_IWL<6330> A_IWL<6329> A_IWL<6328> A_IWL<6327> A_IWL<6326> A_IWL<6325> A_IWL<6324> A_IWL<6323> A_IWL<6322> A_IWL<6321> A_IWL<6320> A_IWL<6319> A_IWL<6318> A_IWL<6317> A_IWL<6316> A_IWL<6315> A_IWL<6314> A_IWL<6313> A_IWL<6312> A_IWL<6311> A_IWL<6310> A_IWL<6309> A_IWL<6308> A_IWL<6307> A_IWL<6306> A_IWL<6305> A_IWL<6304> A_IWL<6303> A_IWL<6302> A_IWL<6301> A_IWL<6300> A_IWL<6299> A_IWL<6298> A_IWL<6297> A_IWL<6296> A_IWL<6295> A_IWL<6294> A_IWL<6293> A_IWL<6292> A_IWL<6291> A_IWL<6290> A_IWL<6289> A_IWL<6288> A_IWL<6287> A_IWL<6286> A_IWL<6285> A_IWL<6284> A_IWL<6283> A_IWL<6282> A_IWL<6281> A_IWL<6280> A_IWL<6279> A_IWL<6278> A_IWL<6277> A_IWL<6276> A_IWL<6275> A_IWL<6274> A_IWL<6273> A_IWL<6272> A_IWL<6271> A_IWL<6270> A_IWL<6269> A_IWL<6268> A_IWL<6267> A_IWL<6266> A_IWL<6265> A_IWL<6264> A_IWL<6263> A_IWL<6262> A_IWL<6261> A_IWL<6260> A_IWL<6259> A_IWL<6258> A_IWL<6257> A_IWL<6256> A_IWL<6255> A_IWL<6254> A_IWL<6253> A_IWL<6252> A_IWL<6251> A_IWL<6250> A_IWL<6249> A_IWL<6248> A_IWL<6247> A_IWL<6246> A_IWL<6245> A_IWL<6244> A_IWL<6243> A_IWL<6242> A_IWL<6241> A_IWL<6240> A_IWL<6239> A_IWL<6238> A_IWL<6237> A_IWL<6236> A_IWL<6235> A_IWL<6234> A_IWL<6233> A_IWL<6232> A_IWL<6231> A_IWL<6230> A_IWL<6229> A_IWL<6228> A_IWL<6227> A_IWL<6226> A_IWL<6225> A_IWL<6224> A_IWL<6223> A_IWL<6222> A_IWL<6221> A_IWL<6220> A_IWL<6219> A_IWL<6218> A_IWL<6217> A_IWL<6216> A_IWL<6215> A_IWL<6214> A_IWL<6213> A_IWL<6212> A_IWL<6211> A_IWL<6210> A_IWL<6209> A_IWL<6208> A_IWL<6207> A_IWL<6206> A_IWL<6205> A_IWL<6204> A_IWL<6203> A_IWL<6202> A_IWL<6201> A_IWL<6200> A_IWL<6199> A_IWL<6198> A_IWL<6197> A_IWL<6196> A_IWL<6195> A_IWL<6194> A_IWL<6193> A_IWL<6192> A_IWL<6191> A_IWL<6190> A_IWL<6189> A_IWL<6188> A_IWL<6187> A_IWL<6186> A_IWL<6185> A_IWL<6184> A_IWL<6183> A_IWL<6182> A_IWL<6181> A_IWL<6180> A_IWL<6179> A_IWL<6178> A_IWL<6177> A_IWL<6176> A_IWL<6175> A_IWL<6174> A_IWL<6173> A_IWL<6172> A_IWL<6171> A_IWL<6170> A_IWL<6169> A_IWL<6168> A_IWL<6167> A_IWL<6166> A_IWL<6165> A_IWL<6164> A_IWL<6163> A_IWL<6162> A_IWL<6161> A_IWL<6160> A_IWL<6159> A_IWL<6158> A_IWL<6157> A_IWL<6156> A_IWL<6155> A_IWL<6154> A_IWL<6153> A_IWL<6152> A_IWL<6151> A_IWL<6150> A_IWL<6149> A_IWL<6148> A_IWL<6147> A_IWL<6146> A_IWL<6145> A_IWL<6144> VDD_CORE VSS / RM_IHPSG13_8192x32_c4_1P_COLUMN_pcell_0 +XCOL<11> A_BLC<23> A_BLC<22> A_BLC_TOP<23> A_BLC_TOP<22> A_BLT<23> A_BLT<22> A_BLT_TOP<23> A_BLT_TOP<22> A_IWL<5631> A_IWL<5630> A_IWL<5629> A_IWL<5628> A_IWL<5627> A_IWL<5626> A_IWL<5625> A_IWL<5624> A_IWL<5623> A_IWL<5622> A_IWL<5621> A_IWL<5620> A_IWL<5619> A_IWL<5618> A_IWL<5617> A_IWL<5616> A_IWL<5615> A_IWL<5614> A_IWL<5613> A_IWL<5612> A_IWL<5611> A_IWL<5610> A_IWL<5609> A_IWL<5608> A_IWL<5607> A_IWL<5606> A_IWL<5605> A_IWL<5604> A_IWL<5603> A_IWL<5602> A_IWL<5601> A_IWL<5600> A_IWL<5599> A_IWL<5598> A_IWL<5597> A_IWL<5596> A_IWL<5595> A_IWL<5594> A_IWL<5593> A_IWL<5592> A_IWL<5591> A_IWL<5590> A_IWL<5589> A_IWL<5588> A_IWL<5587> A_IWL<5586> A_IWL<5585> A_IWL<5584> A_IWL<5583> A_IWL<5582> A_IWL<5581> A_IWL<5580> A_IWL<5579> A_IWL<5578> A_IWL<5577> A_IWL<5576> A_IWL<5575> A_IWL<5574> A_IWL<5573> A_IWL<5572> A_IWL<5571> A_IWL<5570> A_IWL<5569> A_IWL<5568> A_IWL<5567> A_IWL<5566> A_IWL<5565> A_IWL<5564> A_IWL<5563> A_IWL<5562> A_IWL<5561> A_IWL<5560> A_IWL<5559> A_IWL<5558> A_IWL<5557> A_IWL<5556> A_IWL<5555> A_IWL<5554> A_IWL<5553> A_IWL<5552> A_IWL<5551> A_IWL<5550> A_IWL<5549> A_IWL<5548> A_IWL<5547> A_IWL<5546> A_IWL<5545> A_IWL<5544> A_IWL<5543> A_IWL<5542> A_IWL<5541> A_IWL<5540> A_IWL<5539> A_IWL<5538> A_IWL<5537> A_IWL<5536> A_IWL<5535> A_IWL<5534> A_IWL<5533> A_IWL<5532> A_IWL<5531> A_IWL<5530> A_IWL<5529> A_IWL<5528> A_IWL<5527> A_IWL<5526> A_IWL<5525> A_IWL<5524> A_IWL<5523> A_IWL<5522> A_IWL<5521> A_IWL<5520> A_IWL<5519> A_IWL<5518> A_IWL<5517> A_IWL<5516> A_IWL<5515> A_IWL<5514> A_IWL<5513> A_IWL<5512> A_IWL<5511> A_IWL<5510> A_IWL<5509> A_IWL<5508> A_IWL<5507> A_IWL<5506> A_IWL<5505> A_IWL<5504> A_IWL<5503> A_IWL<5502> A_IWL<5501> A_IWL<5500> A_IWL<5499> A_IWL<5498> A_IWL<5497> A_IWL<5496> A_IWL<5495> A_IWL<5494> A_IWL<5493> A_IWL<5492> A_IWL<5491> A_IWL<5490> A_IWL<5489> A_IWL<5488> A_IWL<5487> A_IWL<5486> A_IWL<5485> A_IWL<5484> A_IWL<5483> A_IWL<5482> A_IWL<5481> A_IWL<5480> A_IWL<5479> A_IWL<5478> A_IWL<5477> A_IWL<5476> A_IWL<5475> A_IWL<5474> A_IWL<5473> A_IWL<5472> A_IWL<5471> A_IWL<5470> A_IWL<5469> A_IWL<5468> A_IWL<5467> A_IWL<5466> A_IWL<5465> A_IWL<5464> A_IWL<5463> A_IWL<5462> A_IWL<5461> A_IWL<5460> A_IWL<5459> A_IWL<5458> A_IWL<5457> A_IWL<5456> A_IWL<5455> A_IWL<5454> A_IWL<5453> A_IWL<5452> A_IWL<5451> A_IWL<5450> A_IWL<5449> A_IWL<5448> A_IWL<5447> A_IWL<5446> A_IWL<5445> A_IWL<5444> A_IWL<5443> A_IWL<5442> A_IWL<5441> A_IWL<5440> A_IWL<5439> A_IWL<5438> A_IWL<5437> A_IWL<5436> A_IWL<5435> A_IWL<5434> A_IWL<5433> A_IWL<5432> A_IWL<5431> A_IWL<5430> A_IWL<5429> A_IWL<5428> A_IWL<5427> A_IWL<5426> A_IWL<5425> A_IWL<5424> A_IWL<5423> A_IWL<5422> A_IWL<5421> A_IWL<5420> A_IWL<5419> A_IWL<5418> A_IWL<5417> A_IWL<5416> A_IWL<5415> A_IWL<5414> A_IWL<5413> A_IWL<5412> A_IWL<5411> A_IWL<5410> A_IWL<5409> A_IWL<5408> A_IWL<5407> A_IWL<5406> A_IWL<5405> A_IWL<5404> A_IWL<5403> A_IWL<5402> A_IWL<5401> A_IWL<5400> A_IWL<5399> A_IWL<5398> A_IWL<5397> A_IWL<5396> A_IWL<5395> A_IWL<5394> A_IWL<5393> A_IWL<5392> A_IWL<5391> A_IWL<5390> A_IWL<5389> A_IWL<5388> A_IWL<5387> A_IWL<5386> A_IWL<5385> A_IWL<5384> A_IWL<5383> A_IWL<5382> A_IWL<5381> A_IWL<5380> A_IWL<5379> A_IWL<5378> A_IWL<5377> A_IWL<5376> A_IWL<5375> A_IWL<5374> A_IWL<5373> A_IWL<5372> A_IWL<5371> A_IWL<5370> A_IWL<5369> A_IWL<5368> A_IWL<5367> A_IWL<5366> A_IWL<5365> A_IWL<5364> A_IWL<5363> A_IWL<5362> A_IWL<5361> A_IWL<5360> A_IWL<5359> A_IWL<5358> A_IWL<5357> A_IWL<5356> A_IWL<5355> A_IWL<5354> A_IWL<5353> A_IWL<5352> A_IWL<5351> A_IWL<5350> A_IWL<5349> A_IWL<5348> A_IWL<5347> A_IWL<5346> A_IWL<5345> A_IWL<5344> A_IWL<5343> A_IWL<5342> A_IWL<5341> A_IWL<5340> A_IWL<5339> A_IWL<5338> A_IWL<5337> A_IWL<5336> A_IWL<5335> A_IWL<5334> A_IWL<5333> A_IWL<5332> A_IWL<5331> A_IWL<5330> A_IWL<5329> A_IWL<5328> A_IWL<5327> A_IWL<5326> A_IWL<5325> A_IWL<5324> A_IWL<5323> A_IWL<5322> A_IWL<5321> A_IWL<5320> A_IWL<5319> A_IWL<5318> A_IWL<5317> A_IWL<5316> A_IWL<5315> A_IWL<5314> A_IWL<5313> A_IWL<5312> A_IWL<5311> A_IWL<5310> A_IWL<5309> A_IWL<5308> A_IWL<5307> A_IWL<5306> A_IWL<5305> A_IWL<5304> A_IWL<5303> A_IWL<5302> A_IWL<5301> A_IWL<5300> A_IWL<5299> A_IWL<5298> A_IWL<5297> A_IWL<5296> A_IWL<5295> A_IWL<5294> A_IWL<5293> A_IWL<5292> A_IWL<5291> A_IWL<5290> A_IWL<5289> A_IWL<5288> A_IWL<5287> A_IWL<5286> A_IWL<5285> A_IWL<5284> A_IWL<5283> A_IWL<5282> A_IWL<5281> A_IWL<5280> A_IWL<5279> A_IWL<5278> A_IWL<5277> A_IWL<5276> A_IWL<5275> A_IWL<5274> A_IWL<5273> A_IWL<5272> A_IWL<5271> A_IWL<5270> A_IWL<5269> A_IWL<5268> A_IWL<5267> A_IWL<5266> A_IWL<5265> A_IWL<5264> A_IWL<5263> A_IWL<5262> A_IWL<5261> A_IWL<5260> A_IWL<5259> A_IWL<5258> A_IWL<5257> A_IWL<5256> A_IWL<5255> A_IWL<5254> A_IWL<5253> A_IWL<5252> A_IWL<5251> A_IWL<5250> A_IWL<5249> A_IWL<5248> A_IWL<5247> A_IWL<5246> A_IWL<5245> A_IWL<5244> A_IWL<5243> A_IWL<5242> A_IWL<5241> A_IWL<5240> A_IWL<5239> A_IWL<5238> A_IWL<5237> A_IWL<5236> A_IWL<5235> A_IWL<5234> A_IWL<5233> A_IWL<5232> A_IWL<5231> A_IWL<5230> A_IWL<5229> A_IWL<5228> A_IWL<5227> A_IWL<5226> A_IWL<5225> A_IWL<5224> A_IWL<5223> A_IWL<5222> A_IWL<5221> A_IWL<5220> A_IWL<5219> A_IWL<5218> A_IWL<5217> A_IWL<5216> A_IWL<5215> A_IWL<5214> A_IWL<5213> A_IWL<5212> A_IWL<5211> A_IWL<5210> A_IWL<5209> A_IWL<5208> A_IWL<5207> A_IWL<5206> A_IWL<5205> A_IWL<5204> A_IWL<5203> A_IWL<5202> A_IWL<5201> A_IWL<5200> A_IWL<5199> A_IWL<5198> A_IWL<5197> A_IWL<5196> A_IWL<5195> A_IWL<5194> A_IWL<5193> A_IWL<5192> A_IWL<5191> A_IWL<5190> A_IWL<5189> A_IWL<5188> A_IWL<5187> A_IWL<5186> A_IWL<5185> A_IWL<5184> A_IWL<5183> A_IWL<5182> A_IWL<5181> A_IWL<5180> A_IWL<5179> A_IWL<5178> A_IWL<5177> A_IWL<5176> A_IWL<5175> A_IWL<5174> A_IWL<5173> A_IWL<5172> A_IWL<5171> A_IWL<5170> A_IWL<5169> A_IWL<5168> A_IWL<5167> A_IWL<5166> A_IWL<5165> A_IWL<5164> A_IWL<5163> A_IWL<5162> A_IWL<5161> A_IWL<5160> A_IWL<5159> A_IWL<5158> A_IWL<5157> A_IWL<5156> A_IWL<5155> A_IWL<5154> A_IWL<5153> A_IWL<5152> A_IWL<5151> A_IWL<5150> A_IWL<5149> A_IWL<5148> A_IWL<5147> A_IWL<5146> A_IWL<5145> A_IWL<5144> A_IWL<5143> A_IWL<5142> A_IWL<5141> A_IWL<5140> A_IWL<5139> A_IWL<5138> A_IWL<5137> A_IWL<5136> A_IWL<5135> A_IWL<5134> A_IWL<5133> A_IWL<5132> A_IWL<5131> A_IWL<5130> A_IWL<5129> A_IWL<5128> A_IWL<5127> A_IWL<5126> A_IWL<5125> A_IWL<5124> A_IWL<5123> A_IWL<5122> A_IWL<5121> A_IWL<5120> A_IWL<6143> A_IWL<6142> A_IWL<6141> A_IWL<6140> A_IWL<6139> A_IWL<6138> A_IWL<6137> A_IWL<6136> A_IWL<6135> A_IWL<6134> A_IWL<6133> A_IWL<6132> A_IWL<6131> A_IWL<6130> A_IWL<6129> A_IWL<6128> A_IWL<6127> A_IWL<6126> A_IWL<6125> A_IWL<6124> A_IWL<6123> A_IWL<6122> A_IWL<6121> A_IWL<6120> A_IWL<6119> A_IWL<6118> A_IWL<6117> A_IWL<6116> A_IWL<6115> A_IWL<6114> A_IWL<6113> A_IWL<6112> A_IWL<6111> A_IWL<6110> A_IWL<6109> A_IWL<6108> A_IWL<6107> A_IWL<6106> A_IWL<6105> A_IWL<6104> A_IWL<6103> A_IWL<6102> A_IWL<6101> A_IWL<6100> A_IWL<6099> A_IWL<6098> A_IWL<6097> A_IWL<6096> A_IWL<6095> A_IWL<6094> A_IWL<6093> A_IWL<6092> A_IWL<6091> A_IWL<6090> A_IWL<6089> A_IWL<6088> A_IWL<6087> A_IWL<6086> A_IWL<6085> A_IWL<6084> A_IWL<6083> A_IWL<6082> A_IWL<6081> A_IWL<6080> A_IWL<6079> A_IWL<6078> A_IWL<6077> A_IWL<6076> A_IWL<6075> A_IWL<6074> A_IWL<6073> A_IWL<6072> A_IWL<6071> A_IWL<6070> A_IWL<6069> A_IWL<6068> A_IWL<6067> A_IWL<6066> A_IWL<6065> A_IWL<6064> A_IWL<6063> A_IWL<6062> A_IWL<6061> A_IWL<6060> A_IWL<6059> A_IWL<6058> A_IWL<6057> A_IWL<6056> A_IWL<6055> A_IWL<6054> A_IWL<6053> A_IWL<6052> A_IWL<6051> A_IWL<6050> A_IWL<6049> A_IWL<6048> A_IWL<6047> A_IWL<6046> A_IWL<6045> A_IWL<6044> A_IWL<6043> A_IWL<6042> A_IWL<6041> A_IWL<6040> A_IWL<6039> A_IWL<6038> A_IWL<6037> A_IWL<6036> A_IWL<6035> A_IWL<6034> A_IWL<6033> A_IWL<6032> A_IWL<6031> A_IWL<6030> A_IWL<6029> A_IWL<6028> A_IWL<6027> A_IWL<6026> A_IWL<6025> A_IWL<6024> A_IWL<6023> A_IWL<6022> A_IWL<6021> A_IWL<6020> A_IWL<6019> A_IWL<6018> A_IWL<6017> A_IWL<6016> A_IWL<6015> A_IWL<6014> A_IWL<6013> A_IWL<6012> A_IWL<6011> A_IWL<6010> A_IWL<6009> A_IWL<6008> A_IWL<6007> A_IWL<6006> A_IWL<6005> A_IWL<6004> A_IWL<6003> A_IWL<6002> A_IWL<6001> A_IWL<6000> A_IWL<5999> A_IWL<5998> A_IWL<5997> A_IWL<5996> A_IWL<5995> A_IWL<5994> A_IWL<5993> A_IWL<5992> A_IWL<5991> A_IWL<5990> A_IWL<5989> A_IWL<5988> A_IWL<5987> A_IWL<5986> A_IWL<5985> A_IWL<5984> A_IWL<5983> A_IWL<5982> A_IWL<5981> A_IWL<5980> A_IWL<5979> A_IWL<5978> A_IWL<5977> A_IWL<5976> A_IWL<5975> A_IWL<5974> A_IWL<5973> A_IWL<5972> A_IWL<5971> A_IWL<5970> A_IWL<5969> A_IWL<5968> A_IWL<5967> A_IWL<5966> A_IWL<5965> A_IWL<5964> A_IWL<5963> A_IWL<5962> A_IWL<5961> A_IWL<5960> A_IWL<5959> A_IWL<5958> A_IWL<5957> A_IWL<5956> A_IWL<5955> A_IWL<5954> A_IWL<5953> A_IWL<5952> A_IWL<5951> A_IWL<5950> A_IWL<5949> A_IWL<5948> A_IWL<5947> A_IWL<5946> A_IWL<5945> A_IWL<5944> A_IWL<5943> A_IWL<5942> A_IWL<5941> A_IWL<5940> A_IWL<5939> A_IWL<5938> A_IWL<5937> A_IWL<5936> A_IWL<5935> A_IWL<5934> A_IWL<5933> A_IWL<5932> A_IWL<5931> A_IWL<5930> A_IWL<5929> A_IWL<5928> A_IWL<5927> A_IWL<5926> A_IWL<5925> A_IWL<5924> A_IWL<5923> A_IWL<5922> A_IWL<5921> A_IWL<5920> A_IWL<5919> A_IWL<5918> A_IWL<5917> A_IWL<5916> A_IWL<5915> A_IWL<5914> A_IWL<5913> A_IWL<5912> A_IWL<5911> A_IWL<5910> A_IWL<5909> A_IWL<5908> A_IWL<5907> A_IWL<5906> A_IWL<5905> A_IWL<5904> A_IWL<5903> A_IWL<5902> A_IWL<5901> A_IWL<5900> A_IWL<5899> A_IWL<5898> A_IWL<5897> A_IWL<5896> A_IWL<5895> A_IWL<5894> A_IWL<5893> A_IWL<5892> A_IWL<5891> A_IWL<5890> A_IWL<5889> A_IWL<5888> A_IWL<5887> A_IWL<5886> A_IWL<5885> A_IWL<5884> A_IWL<5883> A_IWL<5882> A_IWL<5881> A_IWL<5880> A_IWL<5879> A_IWL<5878> A_IWL<5877> A_IWL<5876> A_IWL<5875> A_IWL<5874> A_IWL<5873> A_IWL<5872> A_IWL<5871> A_IWL<5870> A_IWL<5869> A_IWL<5868> A_IWL<5867> A_IWL<5866> A_IWL<5865> A_IWL<5864> A_IWL<5863> A_IWL<5862> A_IWL<5861> A_IWL<5860> A_IWL<5859> A_IWL<5858> A_IWL<5857> A_IWL<5856> A_IWL<5855> A_IWL<5854> A_IWL<5853> A_IWL<5852> A_IWL<5851> A_IWL<5850> A_IWL<5849> A_IWL<5848> A_IWL<5847> A_IWL<5846> A_IWL<5845> A_IWL<5844> A_IWL<5843> A_IWL<5842> A_IWL<5841> A_IWL<5840> A_IWL<5839> A_IWL<5838> A_IWL<5837> A_IWL<5836> A_IWL<5835> A_IWL<5834> A_IWL<5833> A_IWL<5832> A_IWL<5831> A_IWL<5830> A_IWL<5829> A_IWL<5828> A_IWL<5827> A_IWL<5826> A_IWL<5825> A_IWL<5824> A_IWL<5823> A_IWL<5822> A_IWL<5821> A_IWL<5820> A_IWL<5819> A_IWL<5818> A_IWL<5817> A_IWL<5816> A_IWL<5815> A_IWL<5814> A_IWL<5813> A_IWL<5812> A_IWL<5811> A_IWL<5810> A_IWL<5809> A_IWL<5808> A_IWL<5807> A_IWL<5806> A_IWL<5805> A_IWL<5804> A_IWL<5803> A_IWL<5802> A_IWL<5801> A_IWL<5800> A_IWL<5799> A_IWL<5798> A_IWL<5797> A_IWL<5796> A_IWL<5795> A_IWL<5794> A_IWL<5793> A_IWL<5792> A_IWL<5791> A_IWL<5790> A_IWL<5789> A_IWL<5788> A_IWL<5787> A_IWL<5786> A_IWL<5785> A_IWL<5784> A_IWL<5783> A_IWL<5782> A_IWL<5781> A_IWL<5780> A_IWL<5779> A_IWL<5778> A_IWL<5777> A_IWL<5776> A_IWL<5775> A_IWL<5774> A_IWL<5773> A_IWL<5772> A_IWL<5771> A_IWL<5770> A_IWL<5769> A_IWL<5768> A_IWL<5767> A_IWL<5766> A_IWL<5765> A_IWL<5764> A_IWL<5763> A_IWL<5762> A_IWL<5761> A_IWL<5760> A_IWL<5759> A_IWL<5758> A_IWL<5757> A_IWL<5756> A_IWL<5755> A_IWL<5754> A_IWL<5753> A_IWL<5752> A_IWL<5751> A_IWL<5750> A_IWL<5749> A_IWL<5748> A_IWL<5747> A_IWL<5746> A_IWL<5745> A_IWL<5744> A_IWL<5743> A_IWL<5742> A_IWL<5741> A_IWL<5740> A_IWL<5739> A_IWL<5738> A_IWL<5737> A_IWL<5736> A_IWL<5735> A_IWL<5734> A_IWL<5733> A_IWL<5732> A_IWL<5731> A_IWL<5730> A_IWL<5729> A_IWL<5728> A_IWL<5727> A_IWL<5726> A_IWL<5725> A_IWL<5724> A_IWL<5723> A_IWL<5722> A_IWL<5721> A_IWL<5720> A_IWL<5719> A_IWL<5718> A_IWL<5717> A_IWL<5716> A_IWL<5715> A_IWL<5714> A_IWL<5713> A_IWL<5712> A_IWL<5711> A_IWL<5710> A_IWL<5709> A_IWL<5708> A_IWL<5707> A_IWL<5706> A_IWL<5705> A_IWL<5704> A_IWL<5703> A_IWL<5702> A_IWL<5701> A_IWL<5700> A_IWL<5699> A_IWL<5698> A_IWL<5697> A_IWL<5696> A_IWL<5695> A_IWL<5694> A_IWL<5693> A_IWL<5692> A_IWL<5691> A_IWL<5690> A_IWL<5689> A_IWL<5688> A_IWL<5687> A_IWL<5686> A_IWL<5685> A_IWL<5684> A_IWL<5683> A_IWL<5682> A_IWL<5681> A_IWL<5680> A_IWL<5679> A_IWL<5678> A_IWL<5677> A_IWL<5676> A_IWL<5675> A_IWL<5674> A_IWL<5673> A_IWL<5672> A_IWL<5671> A_IWL<5670> A_IWL<5669> A_IWL<5668> A_IWL<5667> A_IWL<5666> A_IWL<5665> A_IWL<5664> A_IWL<5663> A_IWL<5662> A_IWL<5661> A_IWL<5660> A_IWL<5659> A_IWL<5658> A_IWL<5657> A_IWL<5656> A_IWL<5655> A_IWL<5654> A_IWL<5653> A_IWL<5652> A_IWL<5651> A_IWL<5650> A_IWL<5649> A_IWL<5648> A_IWL<5647> A_IWL<5646> A_IWL<5645> A_IWL<5644> A_IWL<5643> A_IWL<5642> A_IWL<5641> A_IWL<5640> A_IWL<5639> A_IWL<5638> A_IWL<5637> A_IWL<5636> A_IWL<5635> A_IWL<5634> A_IWL<5633> A_IWL<5632> VDD_CORE VSS / RM_IHPSG13_8192x32_c4_1P_COLUMN_pcell_0 +XCOL<10> A_BLC<21> A_BLC<20> A_BLC_TOP<21> A_BLC_TOP<20> A_BLT<21> A_BLT<20> A_BLT_TOP<21> A_BLT_TOP<20> A_IWL<5119> A_IWL<5118> A_IWL<5117> A_IWL<5116> A_IWL<5115> A_IWL<5114> A_IWL<5113> A_IWL<5112> A_IWL<5111> A_IWL<5110> A_IWL<5109> A_IWL<5108> A_IWL<5107> A_IWL<5106> A_IWL<5105> A_IWL<5104> A_IWL<5103> A_IWL<5102> A_IWL<5101> A_IWL<5100> A_IWL<5099> A_IWL<5098> A_IWL<5097> A_IWL<5096> A_IWL<5095> A_IWL<5094> A_IWL<5093> A_IWL<5092> A_IWL<5091> A_IWL<5090> A_IWL<5089> A_IWL<5088> A_IWL<5087> A_IWL<5086> A_IWL<5085> A_IWL<5084> A_IWL<5083> A_IWL<5082> A_IWL<5081> A_IWL<5080> A_IWL<5079> A_IWL<5078> A_IWL<5077> A_IWL<5076> A_IWL<5075> A_IWL<5074> A_IWL<5073> A_IWL<5072> A_IWL<5071> A_IWL<5070> A_IWL<5069> A_IWL<5068> A_IWL<5067> A_IWL<5066> A_IWL<5065> A_IWL<5064> A_IWL<5063> A_IWL<5062> A_IWL<5061> A_IWL<5060> A_IWL<5059> A_IWL<5058> A_IWL<5057> A_IWL<5056> A_IWL<5055> A_IWL<5054> A_IWL<5053> A_IWL<5052> A_IWL<5051> A_IWL<5050> A_IWL<5049> A_IWL<5048> A_IWL<5047> A_IWL<5046> A_IWL<5045> A_IWL<5044> A_IWL<5043> A_IWL<5042> A_IWL<5041> A_IWL<5040> A_IWL<5039> A_IWL<5038> A_IWL<5037> A_IWL<5036> A_IWL<5035> A_IWL<5034> A_IWL<5033> A_IWL<5032> A_IWL<5031> A_IWL<5030> A_IWL<5029> A_IWL<5028> A_IWL<5027> A_IWL<5026> A_IWL<5025> A_IWL<5024> A_IWL<5023> A_IWL<5022> A_IWL<5021> A_IWL<5020> A_IWL<5019> A_IWL<5018> A_IWL<5017> A_IWL<5016> A_IWL<5015> A_IWL<5014> A_IWL<5013> A_IWL<5012> A_IWL<5011> A_IWL<5010> A_IWL<5009> A_IWL<5008> A_IWL<5007> A_IWL<5006> A_IWL<5005> A_IWL<5004> A_IWL<5003> A_IWL<5002> A_IWL<5001> A_IWL<5000> A_IWL<4999> A_IWL<4998> A_IWL<4997> A_IWL<4996> A_IWL<4995> A_IWL<4994> A_IWL<4993> A_IWL<4992> A_IWL<4991> A_IWL<4990> A_IWL<4989> A_IWL<4988> A_IWL<4987> A_IWL<4986> A_IWL<4985> A_IWL<4984> A_IWL<4983> A_IWL<4982> A_IWL<4981> A_IWL<4980> A_IWL<4979> A_IWL<4978> A_IWL<4977> A_IWL<4976> A_IWL<4975> A_IWL<4974> A_IWL<4973> A_IWL<4972> A_IWL<4971> A_IWL<4970> A_IWL<4969> A_IWL<4968> A_IWL<4967> A_IWL<4966> A_IWL<4965> A_IWL<4964> A_IWL<4963> A_IWL<4962> A_IWL<4961> A_IWL<4960> A_IWL<4959> A_IWL<4958> A_IWL<4957> A_IWL<4956> A_IWL<4955> A_IWL<4954> A_IWL<4953> A_IWL<4952> A_IWL<4951> A_IWL<4950> A_IWL<4949> A_IWL<4948> A_IWL<4947> A_IWL<4946> A_IWL<4945> A_IWL<4944> A_IWL<4943> A_IWL<4942> A_IWL<4941> A_IWL<4940> A_IWL<4939> A_IWL<4938> A_IWL<4937> A_IWL<4936> A_IWL<4935> A_IWL<4934> A_IWL<4933> A_IWL<4932> A_IWL<4931> A_IWL<4930> A_IWL<4929> A_IWL<4928> A_IWL<4927> A_IWL<4926> A_IWL<4925> A_IWL<4924> A_IWL<4923> A_IWL<4922> A_IWL<4921> A_IWL<4920> A_IWL<4919> A_IWL<4918> A_IWL<4917> A_IWL<4916> A_IWL<4915> A_IWL<4914> A_IWL<4913> A_IWL<4912> A_IWL<4911> A_IWL<4910> A_IWL<4909> A_IWL<4908> A_IWL<4907> A_IWL<4906> A_IWL<4905> A_IWL<4904> A_IWL<4903> A_IWL<4902> A_IWL<4901> A_IWL<4900> A_IWL<4899> A_IWL<4898> A_IWL<4897> A_IWL<4896> A_IWL<4895> A_IWL<4894> A_IWL<4893> A_IWL<4892> A_IWL<4891> A_IWL<4890> A_IWL<4889> A_IWL<4888> A_IWL<4887> A_IWL<4886> A_IWL<4885> A_IWL<4884> A_IWL<4883> A_IWL<4882> A_IWL<4881> A_IWL<4880> A_IWL<4879> A_IWL<4878> A_IWL<4877> A_IWL<4876> A_IWL<4875> A_IWL<4874> A_IWL<4873> A_IWL<4872> A_IWL<4871> A_IWL<4870> A_IWL<4869> A_IWL<4868> A_IWL<4867> A_IWL<4866> A_IWL<4865> A_IWL<4864> A_IWL<4863> A_IWL<4862> A_IWL<4861> A_IWL<4860> A_IWL<4859> A_IWL<4858> A_IWL<4857> A_IWL<4856> A_IWL<4855> A_IWL<4854> A_IWL<4853> A_IWL<4852> A_IWL<4851> A_IWL<4850> A_IWL<4849> A_IWL<4848> A_IWL<4847> A_IWL<4846> A_IWL<4845> A_IWL<4844> A_IWL<4843> A_IWL<4842> A_IWL<4841> A_IWL<4840> A_IWL<4839> A_IWL<4838> A_IWL<4837> A_IWL<4836> A_IWL<4835> A_IWL<4834> A_IWL<4833> A_IWL<4832> A_IWL<4831> A_IWL<4830> A_IWL<4829> A_IWL<4828> A_IWL<4827> A_IWL<4826> A_IWL<4825> A_IWL<4824> A_IWL<4823> A_IWL<4822> A_IWL<4821> A_IWL<4820> A_IWL<4819> A_IWL<4818> A_IWL<4817> A_IWL<4816> A_IWL<4815> A_IWL<4814> A_IWL<4813> A_IWL<4812> A_IWL<4811> A_IWL<4810> A_IWL<4809> A_IWL<4808> A_IWL<4807> A_IWL<4806> A_IWL<4805> A_IWL<4804> A_IWL<4803> A_IWL<4802> A_IWL<4801> A_IWL<4800> A_IWL<4799> A_IWL<4798> A_IWL<4797> A_IWL<4796> A_IWL<4795> A_IWL<4794> A_IWL<4793> A_IWL<4792> A_IWL<4791> A_IWL<4790> A_IWL<4789> A_IWL<4788> A_IWL<4787> A_IWL<4786> A_IWL<4785> A_IWL<4784> A_IWL<4783> A_IWL<4782> A_IWL<4781> A_IWL<4780> A_IWL<4779> A_IWL<4778> A_IWL<4777> A_IWL<4776> A_IWL<4775> A_IWL<4774> A_IWL<4773> A_IWL<4772> A_IWL<4771> A_IWL<4770> A_IWL<4769> A_IWL<4768> A_IWL<4767> A_IWL<4766> A_IWL<4765> A_IWL<4764> A_IWL<4763> A_IWL<4762> A_IWL<4761> A_IWL<4760> A_IWL<4759> A_IWL<4758> A_IWL<4757> A_IWL<4756> A_IWL<4755> A_IWL<4754> A_IWL<4753> A_IWL<4752> A_IWL<4751> A_IWL<4750> A_IWL<4749> A_IWL<4748> A_IWL<4747> A_IWL<4746> A_IWL<4745> A_IWL<4744> A_IWL<4743> A_IWL<4742> A_IWL<4741> A_IWL<4740> A_IWL<4739> A_IWL<4738> A_IWL<4737> A_IWL<4736> A_IWL<4735> A_IWL<4734> A_IWL<4733> A_IWL<4732> A_IWL<4731> A_IWL<4730> A_IWL<4729> A_IWL<4728> A_IWL<4727> A_IWL<4726> A_IWL<4725> A_IWL<4724> A_IWL<4723> A_IWL<4722> A_IWL<4721> A_IWL<4720> A_IWL<4719> A_IWL<4718> A_IWL<4717> A_IWL<4716> A_IWL<4715> A_IWL<4714> A_IWL<4713> A_IWL<4712> A_IWL<4711> A_IWL<4710> A_IWL<4709> A_IWL<4708> A_IWL<4707> A_IWL<4706> A_IWL<4705> A_IWL<4704> A_IWL<4703> A_IWL<4702> A_IWL<4701> A_IWL<4700> A_IWL<4699> A_IWL<4698> A_IWL<4697> A_IWL<4696> A_IWL<4695> A_IWL<4694> A_IWL<4693> A_IWL<4692> A_IWL<4691> A_IWL<4690> A_IWL<4689> A_IWL<4688> A_IWL<4687> A_IWL<4686> A_IWL<4685> A_IWL<4684> A_IWL<4683> A_IWL<4682> A_IWL<4681> A_IWL<4680> A_IWL<4679> A_IWL<4678> A_IWL<4677> A_IWL<4676> A_IWL<4675> A_IWL<4674> A_IWL<4673> A_IWL<4672> A_IWL<4671> A_IWL<4670> A_IWL<4669> A_IWL<4668> A_IWL<4667> A_IWL<4666> A_IWL<4665> A_IWL<4664> A_IWL<4663> A_IWL<4662> A_IWL<4661> A_IWL<4660> A_IWL<4659> A_IWL<4658> A_IWL<4657> A_IWL<4656> A_IWL<4655> A_IWL<4654> A_IWL<4653> A_IWL<4652> A_IWL<4651> A_IWL<4650> A_IWL<4649> A_IWL<4648> A_IWL<4647> A_IWL<4646> A_IWL<4645> A_IWL<4644> A_IWL<4643> A_IWL<4642> A_IWL<4641> A_IWL<4640> A_IWL<4639> A_IWL<4638> A_IWL<4637> A_IWL<4636> A_IWL<4635> A_IWL<4634> A_IWL<4633> A_IWL<4632> A_IWL<4631> A_IWL<4630> A_IWL<4629> A_IWL<4628> A_IWL<4627> A_IWL<4626> A_IWL<4625> A_IWL<4624> A_IWL<4623> A_IWL<4622> A_IWL<4621> A_IWL<4620> A_IWL<4619> A_IWL<4618> A_IWL<4617> A_IWL<4616> A_IWL<4615> A_IWL<4614> A_IWL<4613> A_IWL<4612> A_IWL<4611> A_IWL<4610> A_IWL<4609> A_IWL<4608> A_IWL<5631> A_IWL<5630> A_IWL<5629> A_IWL<5628> A_IWL<5627> A_IWL<5626> A_IWL<5625> A_IWL<5624> A_IWL<5623> A_IWL<5622> A_IWL<5621> A_IWL<5620> A_IWL<5619> A_IWL<5618> A_IWL<5617> A_IWL<5616> A_IWL<5615> A_IWL<5614> A_IWL<5613> A_IWL<5612> A_IWL<5611> A_IWL<5610> A_IWL<5609> A_IWL<5608> A_IWL<5607> A_IWL<5606> A_IWL<5605> A_IWL<5604> A_IWL<5603> A_IWL<5602> A_IWL<5601> A_IWL<5600> A_IWL<5599> A_IWL<5598> A_IWL<5597> A_IWL<5596> A_IWL<5595> A_IWL<5594> A_IWL<5593> A_IWL<5592> A_IWL<5591> A_IWL<5590> A_IWL<5589> A_IWL<5588> A_IWL<5587> A_IWL<5586> A_IWL<5585> A_IWL<5584> A_IWL<5583> A_IWL<5582> A_IWL<5581> A_IWL<5580> A_IWL<5579> A_IWL<5578> A_IWL<5577> A_IWL<5576> A_IWL<5575> A_IWL<5574> A_IWL<5573> A_IWL<5572> A_IWL<5571> A_IWL<5570> A_IWL<5569> A_IWL<5568> A_IWL<5567> A_IWL<5566> A_IWL<5565> A_IWL<5564> A_IWL<5563> A_IWL<5562> A_IWL<5561> A_IWL<5560> A_IWL<5559> A_IWL<5558> A_IWL<5557> A_IWL<5556> A_IWL<5555> A_IWL<5554> A_IWL<5553> A_IWL<5552> A_IWL<5551> A_IWL<5550> A_IWL<5549> A_IWL<5548> A_IWL<5547> A_IWL<5546> A_IWL<5545> A_IWL<5544> A_IWL<5543> A_IWL<5542> A_IWL<5541> A_IWL<5540> A_IWL<5539> A_IWL<5538> A_IWL<5537> A_IWL<5536> A_IWL<5535> A_IWL<5534> A_IWL<5533> A_IWL<5532> A_IWL<5531> A_IWL<5530> A_IWL<5529> A_IWL<5528> A_IWL<5527> A_IWL<5526> A_IWL<5525> A_IWL<5524> A_IWL<5523> A_IWL<5522> A_IWL<5521> A_IWL<5520> A_IWL<5519> A_IWL<5518> A_IWL<5517> A_IWL<5516> A_IWL<5515> A_IWL<5514> A_IWL<5513> A_IWL<5512> A_IWL<5511> A_IWL<5510> A_IWL<5509> A_IWL<5508> A_IWL<5507> A_IWL<5506> A_IWL<5505> A_IWL<5504> A_IWL<5503> A_IWL<5502> A_IWL<5501> A_IWL<5500> A_IWL<5499> A_IWL<5498> A_IWL<5497> A_IWL<5496> A_IWL<5495> A_IWL<5494> A_IWL<5493> A_IWL<5492> A_IWL<5491> A_IWL<5490> A_IWL<5489> A_IWL<5488> A_IWL<5487> A_IWL<5486> A_IWL<5485> A_IWL<5484> A_IWL<5483> A_IWL<5482> A_IWL<5481> A_IWL<5480> A_IWL<5479> A_IWL<5478> A_IWL<5477> A_IWL<5476> A_IWL<5475> A_IWL<5474> A_IWL<5473> A_IWL<5472> A_IWL<5471> A_IWL<5470> A_IWL<5469> A_IWL<5468> A_IWL<5467> A_IWL<5466> A_IWL<5465> A_IWL<5464> A_IWL<5463> A_IWL<5462> A_IWL<5461> A_IWL<5460> A_IWL<5459> A_IWL<5458> A_IWL<5457> A_IWL<5456> A_IWL<5455> A_IWL<5454> A_IWL<5453> A_IWL<5452> A_IWL<5451> A_IWL<5450> A_IWL<5449> A_IWL<5448> A_IWL<5447> A_IWL<5446> A_IWL<5445> A_IWL<5444> A_IWL<5443> A_IWL<5442> A_IWL<5441> A_IWL<5440> A_IWL<5439> A_IWL<5438> A_IWL<5437> A_IWL<5436> A_IWL<5435> A_IWL<5434> A_IWL<5433> A_IWL<5432> A_IWL<5431> A_IWL<5430> A_IWL<5429> A_IWL<5428> A_IWL<5427> A_IWL<5426> A_IWL<5425> A_IWL<5424> A_IWL<5423> A_IWL<5422> A_IWL<5421> A_IWL<5420> A_IWL<5419> A_IWL<5418> A_IWL<5417> A_IWL<5416> A_IWL<5415> A_IWL<5414> A_IWL<5413> A_IWL<5412> A_IWL<5411> A_IWL<5410> A_IWL<5409> A_IWL<5408> A_IWL<5407> A_IWL<5406> A_IWL<5405> A_IWL<5404> A_IWL<5403> A_IWL<5402> A_IWL<5401> A_IWL<5400> A_IWL<5399> A_IWL<5398> A_IWL<5397> A_IWL<5396> A_IWL<5395> A_IWL<5394> A_IWL<5393> A_IWL<5392> A_IWL<5391> A_IWL<5390> A_IWL<5389> A_IWL<5388> A_IWL<5387> A_IWL<5386> A_IWL<5385> A_IWL<5384> A_IWL<5383> A_IWL<5382> A_IWL<5381> A_IWL<5380> A_IWL<5379> A_IWL<5378> A_IWL<5377> A_IWL<5376> A_IWL<5375> A_IWL<5374> A_IWL<5373> A_IWL<5372> A_IWL<5371> A_IWL<5370> A_IWL<5369> A_IWL<5368> A_IWL<5367> A_IWL<5366> A_IWL<5365> A_IWL<5364> A_IWL<5363> A_IWL<5362> A_IWL<5361> A_IWL<5360> A_IWL<5359> A_IWL<5358> A_IWL<5357> A_IWL<5356> A_IWL<5355> A_IWL<5354> A_IWL<5353> A_IWL<5352> A_IWL<5351> A_IWL<5350> A_IWL<5349> A_IWL<5348> A_IWL<5347> A_IWL<5346> A_IWL<5345> A_IWL<5344> A_IWL<5343> A_IWL<5342> A_IWL<5341> A_IWL<5340> A_IWL<5339> A_IWL<5338> A_IWL<5337> A_IWL<5336> A_IWL<5335> A_IWL<5334> A_IWL<5333> A_IWL<5332> A_IWL<5331> A_IWL<5330> A_IWL<5329> A_IWL<5328> A_IWL<5327> A_IWL<5326> A_IWL<5325> A_IWL<5324> A_IWL<5323> A_IWL<5322> A_IWL<5321> A_IWL<5320> A_IWL<5319> A_IWL<5318> A_IWL<5317> A_IWL<5316> A_IWL<5315> A_IWL<5314> A_IWL<5313> A_IWL<5312> A_IWL<5311> A_IWL<5310> A_IWL<5309> A_IWL<5308> A_IWL<5307> A_IWL<5306> A_IWL<5305> A_IWL<5304> A_IWL<5303> A_IWL<5302> A_IWL<5301> A_IWL<5300> A_IWL<5299> A_IWL<5298> A_IWL<5297> A_IWL<5296> A_IWL<5295> A_IWL<5294> A_IWL<5293> A_IWL<5292> A_IWL<5291> A_IWL<5290> A_IWL<5289> A_IWL<5288> A_IWL<5287> A_IWL<5286> A_IWL<5285> A_IWL<5284> A_IWL<5283> A_IWL<5282> A_IWL<5281> A_IWL<5280> A_IWL<5279> A_IWL<5278> A_IWL<5277> A_IWL<5276> A_IWL<5275> A_IWL<5274> A_IWL<5273> A_IWL<5272> A_IWL<5271> A_IWL<5270> A_IWL<5269> A_IWL<5268> A_IWL<5267> A_IWL<5266> A_IWL<5265> A_IWL<5264> A_IWL<5263> A_IWL<5262> A_IWL<5261> A_IWL<5260> A_IWL<5259> A_IWL<5258> A_IWL<5257> A_IWL<5256> A_IWL<5255> A_IWL<5254> A_IWL<5253> A_IWL<5252> A_IWL<5251> A_IWL<5250> A_IWL<5249> A_IWL<5248> A_IWL<5247> A_IWL<5246> A_IWL<5245> A_IWL<5244> A_IWL<5243> A_IWL<5242> A_IWL<5241> A_IWL<5240> A_IWL<5239> A_IWL<5238> A_IWL<5237> A_IWL<5236> A_IWL<5235> A_IWL<5234> A_IWL<5233> A_IWL<5232> A_IWL<5231> A_IWL<5230> A_IWL<5229> A_IWL<5228> A_IWL<5227> A_IWL<5226> A_IWL<5225> A_IWL<5224> A_IWL<5223> A_IWL<5222> A_IWL<5221> A_IWL<5220> A_IWL<5219> A_IWL<5218> A_IWL<5217> A_IWL<5216> A_IWL<5215> A_IWL<5214> A_IWL<5213> A_IWL<5212> A_IWL<5211> A_IWL<5210> A_IWL<5209> A_IWL<5208> A_IWL<5207> A_IWL<5206> A_IWL<5205> A_IWL<5204> A_IWL<5203> A_IWL<5202> A_IWL<5201> A_IWL<5200> A_IWL<5199> A_IWL<5198> A_IWL<5197> A_IWL<5196> A_IWL<5195> A_IWL<5194> A_IWL<5193> A_IWL<5192> A_IWL<5191> A_IWL<5190> A_IWL<5189> A_IWL<5188> A_IWL<5187> A_IWL<5186> A_IWL<5185> A_IWL<5184> A_IWL<5183> A_IWL<5182> A_IWL<5181> A_IWL<5180> A_IWL<5179> A_IWL<5178> A_IWL<5177> A_IWL<5176> A_IWL<5175> A_IWL<5174> A_IWL<5173> A_IWL<5172> A_IWL<5171> A_IWL<5170> A_IWL<5169> A_IWL<5168> A_IWL<5167> A_IWL<5166> A_IWL<5165> A_IWL<5164> A_IWL<5163> A_IWL<5162> A_IWL<5161> A_IWL<5160> A_IWL<5159> A_IWL<5158> A_IWL<5157> A_IWL<5156> A_IWL<5155> A_IWL<5154> A_IWL<5153> A_IWL<5152> A_IWL<5151> A_IWL<5150> A_IWL<5149> A_IWL<5148> A_IWL<5147> A_IWL<5146> A_IWL<5145> A_IWL<5144> A_IWL<5143> A_IWL<5142> A_IWL<5141> A_IWL<5140> A_IWL<5139> A_IWL<5138> A_IWL<5137> A_IWL<5136> A_IWL<5135> A_IWL<5134> A_IWL<5133> A_IWL<5132> A_IWL<5131> A_IWL<5130> A_IWL<5129> A_IWL<5128> A_IWL<5127> A_IWL<5126> A_IWL<5125> A_IWL<5124> A_IWL<5123> A_IWL<5122> A_IWL<5121> A_IWL<5120> VDD_CORE VSS / RM_IHPSG13_8192x32_c4_1P_COLUMN_pcell_0 +XCOL<9> A_BLC<19> A_BLC<18> A_BLC_TOP<19> A_BLC_TOP<18> A_BLT<19> A_BLT<18> A_BLT_TOP<19> A_BLT_TOP<18> A_IWL<4607> A_IWL<4606> A_IWL<4605> A_IWL<4604> A_IWL<4603> A_IWL<4602> A_IWL<4601> A_IWL<4600> A_IWL<4599> A_IWL<4598> A_IWL<4597> A_IWL<4596> A_IWL<4595> A_IWL<4594> A_IWL<4593> A_IWL<4592> A_IWL<4591> A_IWL<4590> A_IWL<4589> A_IWL<4588> A_IWL<4587> A_IWL<4586> A_IWL<4585> A_IWL<4584> A_IWL<4583> A_IWL<4582> A_IWL<4581> A_IWL<4580> A_IWL<4579> A_IWL<4578> A_IWL<4577> A_IWL<4576> A_IWL<4575> A_IWL<4574> A_IWL<4573> A_IWL<4572> A_IWL<4571> A_IWL<4570> A_IWL<4569> A_IWL<4568> A_IWL<4567> A_IWL<4566> A_IWL<4565> A_IWL<4564> A_IWL<4563> A_IWL<4562> A_IWL<4561> A_IWL<4560> A_IWL<4559> A_IWL<4558> A_IWL<4557> A_IWL<4556> A_IWL<4555> A_IWL<4554> A_IWL<4553> A_IWL<4552> A_IWL<4551> A_IWL<4550> A_IWL<4549> A_IWL<4548> A_IWL<4547> A_IWL<4546> A_IWL<4545> A_IWL<4544> A_IWL<4543> A_IWL<4542> A_IWL<4541> A_IWL<4540> A_IWL<4539> A_IWL<4538> A_IWL<4537> A_IWL<4536> A_IWL<4535> A_IWL<4534> A_IWL<4533> A_IWL<4532> A_IWL<4531> A_IWL<4530> A_IWL<4529> A_IWL<4528> A_IWL<4527> A_IWL<4526> A_IWL<4525> A_IWL<4524> A_IWL<4523> A_IWL<4522> A_IWL<4521> A_IWL<4520> A_IWL<4519> A_IWL<4518> A_IWL<4517> A_IWL<4516> A_IWL<4515> A_IWL<4514> A_IWL<4513> A_IWL<4512> A_IWL<4511> A_IWL<4510> A_IWL<4509> A_IWL<4508> A_IWL<4507> A_IWL<4506> A_IWL<4505> A_IWL<4504> A_IWL<4503> A_IWL<4502> A_IWL<4501> A_IWL<4500> A_IWL<4499> A_IWL<4498> A_IWL<4497> A_IWL<4496> A_IWL<4495> A_IWL<4494> A_IWL<4493> A_IWL<4492> A_IWL<4491> A_IWL<4490> A_IWL<4489> A_IWL<4488> A_IWL<4487> A_IWL<4486> A_IWL<4485> A_IWL<4484> A_IWL<4483> A_IWL<4482> A_IWL<4481> A_IWL<4480> A_IWL<4479> A_IWL<4478> A_IWL<4477> A_IWL<4476> A_IWL<4475> A_IWL<4474> A_IWL<4473> A_IWL<4472> A_IWL<4471> A_IWL<4470> A_IWL<4469> A_IWL<4468> A_IWL<4467> A_IWL<4466> A_IWL<4465> A_IWL<4464> A_IWL<4463> A_IWL<4462> A_IWL<4461> A_IWL<4460> A_IWL<4459> A_IWL<4458> A_IWL<4457> A_IWL<4456> A_IWL<4455> A_IWL<4454> A_IWL<4453> A_IWL<4452> A_IWL<4451> A_IWL<4450> A_IWL<4449> A_IWL<4448> A_IWL<4447> A_IWL<4446> A_IWL<4445> A_IWL<4444> A_IWL<4443> A_IWL<4442> A_IWL<4441> A_IWL<4440> A_IWL<4439> A_IWL<4438> A_IWL<4437> A_IWL<4436> A_IWL<4435> A_IWL<4434> A_IWL<4433> A_IWL<4432> A_IWL<4431> A_IWL<4430> A_IWL<4429> A_IWL<4428> A_IWL<4427> A_IWL<4426> A_IWL<4425> A_IWL<4424> A_IWL<4423> A_IWL<4422> A_IWL<4421> A_IWL<4420> A_IWL<4419> A_IWL<4418> A_IWL<4417> A_IWL<4416> A_IWL<4415> A_IWL<4414> A_IWL<4413> A_IWL<4412> A_IWL<4411> A_IWL<4410> A_IWL<4409> A_IWL<4408> A_IWL<4407> A_IWL<4406> A_IWL<4405> A_IWL<4404> A_IWL<4403> A_IWL<4402> A_IWL<4401> A_IWL<4400> A_IWL<4399> A_IWL<4398> A_IWL<4397> A_IWL<4396> A_IWL<4395> A_IWL<4394> A_IWL<4393> A_IWL<4392> A_IWL<4391> A_IWL<4390> A_IWL<4389> A_IWL<4388> A_IWL<4387> A_IWL<4386> A_IWL<4385> A_IWL<4384> A_IWL<4383> A_IWL<4382> A_IWL<4381> A_IWL<4380> A_IWL<4379> A_IWL<4378> A_IWL<4377> A_IWL<4376> A_IWL<4375> A_IWL<4374> A_IWL<4373> A_IWL<4372> A_IWL<4371> A_IWL<4370> A_IWL<4369> A_IWL<4368> A_IWL<4367> A_IWL<4366> A_IWL<4365> A_IWL<4364> A_IWL<4363> A_IWL<4362> A_IWL<4361> A_IWL<4360> A_IWL<4359> A_IWL<4358> A_IWL<4357> A_IWL<4356> A_IWL<4355> A_IWL<4354> A_IWL<4353> A_IWL<4352> A_IWL<4351> A_IWL<4350> A_IWL<4349> A_IWL<4348> A_IWL<4347> A_IWL<4346> A_IWL<4345> A_IWL<4344> A_IWL<4343> A_IWL<4342> A_IWL<4341> A_IWL<4340> A_IWL<4339> A_IWL<4338> A_IWL<4337> A_IWL<4336> A_IWL<4335> A_IWL<4334> A_IWL<4333> A_IWL<4332> A_IWL<4331> A_IWL<4330> A_IWL<4329> A_IWL<4328> A_IWL<4327> A_IWL<4326> A_IWL<4325> A_IWL<4324> A_IWL<4323> A_IWL<4322> A_IWL<4321> A_IWL<4320> A_IWL<4319> A_IWL<4318> A_IWL<4317> A_IWL<4316> A_IWL<4315> A_IWL<4314> A_IWL<4313> A_IWL<4312> A_IWL<4311> A_IWL<4310> A_IWL<4309> A_IWL<4308> A_IWL<4307> A_IWL<4306> A_IWL<4305> A_IWL<4304> A_IWL<4303> A_IWL<4302> A_IWL<4301> A_IWL<4300> A_IWL<4299> A_IWL<4298> A_IWL<4297> A_IWL<4296> A_IWL<4295> A_IWL<4294> A_IWL<4293> A_IWL<4292> A_IWL<4291> A_IWL<4290> A_IWL<4289> A_IWL<4288> A_IWL<4287> A_IWL<4286> A_IWL<4285> A_IWL<4284> A_IWL<4283> A_IWL<4282> A_IWL<4281> A_IWL<4280> A_IWL<4279> A_IWL<4278> A_IWL<4277> A_IWL<4276> A_IWL<4275> A_IWL<4274> A_IWL<4273> A_IWL<4272> A_IWL<4271> A_IWL<4270> A_IWL<4269> A_IWL<4268> A_IWL<4267> A_IWL<4266> A_IWL<4265> A_IWL<4264> A_IWL<4263> A_IWL<4262> A_IWL<4261> A_IWL<4260> A_IWL<4259> A_IWL<4258> A_IWL<4257> A_IWL<4256> A_IWL<4255> A_IWL<4254> A_IWL<4253> A_IWL<4252> A_IWL<4251> A_IWL<4250> A_IWL<4249> A_IWL<4248> A_IWL<4247> A_IWL<4246> A_IWL<4245> A_IWL<4244> A_IWL<4243> A_IWL<4242> A_IWL<4241> A_IWL<4240> A_IWL<4239> A_IWL<4238> A_IWL<4237> A_IWL<4236> A_IWL<4235> A_IWL<4234> A_IWL<4233> A_IWL<4232> A_IWL<4231> A_IWL<4230> A_IWL<4229> A_IWL<4228> A_IWL<4227> A_IWL<4226> A_IWL<4225> A_IWL<4224> A_IWL<4223> A_IWL<4222> A_IWL<4221> A_IWL<4220> A_IWL<4219> A_IWL<4218> A_IWL<4217> A_IWL<4216> A_IWL<4215> A_IWL<4214> A_IWL<4213> A_IWL<4212> A_IWL<4211> A_IWL<4210> A_IWL<4209> A_IWL<4208> A_IWL<4207> A_IWL<4206> A_IWL<4205> A_IWL<4204> A_IWL<4203> A_IWL<4202> A_IWL<4201> A_IWL<4200> A_IWL<4199> A_IWL<4198> A_IWL<4197> A_IWL<4196> A_IWL<4195> A_IWL<4194> A_IWL<4193> A_IWL<4192> A_IWL<4191> A_IWL<4190> A_IWL<4189> A_IWL<4188> A_IWL<4187> A_IWL<4186> A_IWL<4185> A_IWL<4184> A_IWL<4183> A_IWL<4182> A_IWL<4181> A_IWL<4180> A_IWL<4179> A_IWL<4178> A_IWL<4177> A_IWL<4176> A_IWL<4175> A_IWL<4174> A_IWL<4173> A_IWL<4172> A_IWL<4171> A_IWL<4170> A_IWL<4169> A_IWL<4168> A_IWL<4167> A_IWL<4166> A_IWL<4165> A_IWL<4164> A_IWL<4163> A_IWL<4162> A_IWL<4161> A_IWL<4160> A_IWL<4159> A_IWL<4158> A_IWL<4157> A_IWL<4156> A_IWL<4155> A_IWL<4154> A_IWL<4153> A_IWL<4152> A_IWL<4151> A_IWL<4150> A_IWL<4149> A_IWL<4148> A_IWL<4147> A_IWL<4146> A_IWL<4145> A_IWL<4144> A_IWL<4143> A_IWL<4142> A_IWL<4141> A_IWL<4140> A_IWL<4139> A_IWL<4138> A_IWL<4137> A_IWL<4136> A_IWL<4135> A_IWL<4134> A_IWL<4133> A_IWL<4132> A_IWL<4131> A_IWL<4130> A_IWL<4129> A_IWL<4128> A_IWL<4127> A_IWL<4126> A_IWL<4125> A_IWL<4124> A_IWL<4123> A_IWL<4122> A_IWL<4121> A_IWL<4120> A_IWL<4119> A_IWL<4118> A_IWL<4117> A_IWL<4116> A_IWL<4115> A_IWL<4114> A_IWL<4113> A_IWL<4112> A_IWL<4111> A_IWL<4110> A_IWL<4109> A_IWL<4108> A_IWL<4107> A_IWL<4106> A_IWL<4105> A_IWL<4104> A_IWL<4103> A_IWL<4102> A_IWL<4101> A_IWL<4100> A_IWL<4099> A_IWL<4098> A_IWL<4097> A_IWL<4096> A_IWL<5119> A_IWL<5118> A_IWL<5117> A_IWL<5116> A_IWL<5115> A_IWL<5114> A_IWL<5113> A_IWL<5112> A_IWL<5111> A_IWL<5110> A_IWL<5109> A_IWL<5108> A_IWL<5107> A_IWL<5106> A_IWL<5105> A_IWL<5104> A_IWL<5103> A_IWL<5102> A_IWL<5101> A_IWL<5100> A_IWL<5099> A_IWL<5098> A_IWL<5097> A_IWL<5096> A_IWL<5095> A_IWL<5094> A_IWL<5093> A_IWL<5092> A_IWL<5091> A_IWL<5090> A_IWL<5089> A_IWL<5088> A_IWL<5087> A_IWL<5086> A_IWL<5085> A_IWL<5084> A_IWL<5083> A_IWL<5082> A_IWL<5081> A_IWL<5080> A_IWL<5079> A_IWL<5078> A_IWL<5077> A_IWL<5076> A_IWL<5075> A_IWL<5074> A_IWL<5073> A_IWL<5072> A_IWL<5071> A_IWL<5070> A_IWL<5069> A_IWL<5068> A_IWL<5067> A_IWL<5066> A_IWL<5065> A_IWL<5064> A_IWL<5063> A_IWL<5062> A_IWL<5061> A_IWL<5060> A_IWL<5059> A_IWL<5058> A_IWL<5057> A_IWL<5056> A_IWL<5055> A_IWL<5054> A_IWL<5053> A_IWL<5052> A_IWL<5051> A_IWL<5050> A_IWL<5049> A_IWL<5048> A_IWL<5047> A_IWL<5046> A_IWL<5045> A_IWL<5044> A_IWL<5043> A_IWL<5042> A_IWL<5041> A_IWL<5040> A_IWL<5039> A_IWL<5038> A_IWL<5037> A_IWL<5036> A_IWL<5035> A_IWL<5034> A_IWL<5033> A_IWL<5032> A_IWL<5031> A_IWL<5030> A_IWL<5029> A_IWL<5028> A_IWL<5027> A_IWL<5026> A_IWL<5025> A_IWL<5024> A_IWL<5023> A_IWL<5022> A_IWL<5021> A_IWL<5020> A_IWL<5019> A_IWL<5018> A_IWL<5017> A_IWL<5016> A_IWL<5015> A_IWL<5014> A_IWL<5013> A_IWL<5012> A_IWL<5011> A_IWL<5010> A_IWL<5009> A_IWL<5008> A_IWL<5007> A_IWL<5006> A_IWL<5005> A_IWL<5004> A_IWL<5003> A_IWL<5002> A_IWL<5001> A_IWL<5000> A_IWL<4999> A_IWL<4998> A_IWL<4997> A_IWL<4996> A_IWL<4995> A_IWL<4994> A_IWL<4993> A_IWL<4992> A_IWL<4991> A_IWL<4990> A_IWL<4989> A_IWL<4988> A_IWL<4987> A_IWL<4986> A_IWL<4985> A_IWL<4984> A_IWL<4983> A_IWL<4982> A_IWL<4981> A_IWL<4980> A_IWL<4979> A_IWL<4978> A_IWL<4977> A_IWL<4976> A_IWL<4975> A_IWL<4974> A_IWL<4973> A_IWL<4972> A_IWL<4971> A_IWL<4970> A_IWL<4969> A_IWL<4968> A_IWL<4967> A_IWL<4966> A_IWL<4965> A_IWL<4964> A_IWL<4963> A_IWL<4962> A_IWL<4961> A_IWL<4960> A_IWL<4959> A_IWL<4958> A_IWL<4957> A_IWL<4956> A_IWL<4955> A_IWL<4954> A_IWL<4953> A_IWL<4952> A_IWL<4951> A_IWL<4950> A_IWL<4949> A_IWL<4948> A_IWL<4947> A_IWL<4946> A_IWL<4945> A_IWL<4944> A_IWL<4943> A_IWL<4942> A_IWL<4941> A_IWL<4940> A_IWL<4939> A_IWL<4938> A_IWL<4937> A_IWL<4936> A_IWL<4935> A_IWL<4934> A_IWL<4933> A_IWL<4932> A_IWL<4931> A_IWL<4930> A_IWL<4929> A_IWL<4928> A_IWL<4927> A_IWL<4926> A_IWL<4925> A_IWL<4924> A_IWL<4923> A_IWL<4922> A_IWL<4921> A_IWL<4920> A_IWL<4919> A_IWL<4918> A_IWL<4917> A_IWL<4916> A_IWL<4915> A_IWL<4914> A_IWL<4913> A_IWL<4912> A_IWL<4911> A_IWL<4910> A_IWL<4909> A_IWL<4908> A_IWL<4907> A_IWL<4906> A_IWL<4905> A_IWL<4904> A_IWL<4903> A_IWL<4902> A_IWL<4901> A_IWL<4900> A_IWL<4899> A_IWL<4898> A_IWL<4897> A_IWL<4896> A_IWL<4895> A_IWL<4894> A_IWL<4893> A_IWL<4892> A_IWL<4891> A_IWL<4890> A_IWL<4889> A_IWL<4888> A_IWL<4887> A_IWL<4886> A_IWL<4885> A_IWL<4884> A_IWL<4883> A_IWL<4882> A_IWL<4881> A_IWL<4880> A_IWL<4879> A_IWL<4878> A_IWL<4877> A_IWL<4876> A_IWL<4875> A_IWL<4874> A_IWL<4873> A_IWL<4872> A_IWL<4871> A_IWL<4870> A_IWL<4869> A_IWL<4868> A_IWL<4867> A_IWL<4866> A_IWL<4865> A_IWL<4864> A_IWL<4863> A_IWL<4862> A_IWL<4861> A_IWL<4860> A_IWL<4859> A_IWL<4858> A_IWL<4857> A_IWL<4856> A_IWL<4855> A_IWL<4854> A_IWL<4853> A_IWL<4852> A_IWL<4851> A_IWL<4850> A_IWL<4849> A_IWL<4848> A_IWL<4847> A_IWL<4846> A_IWL<4845> A_IWL<4844> A_IWL<4843> A_IWL<4842> A_IWL<4841> A_IWL<4840> A_IWL<4839> A_IWL<4838> A_IWL<4837> A_IWL<4836> A_IWL<4835> A_IWL<4834> A_IWL<4833> A_IWL<4832> A_IWL<4831> A_IWL<4830> A_IWL<4829> A_IWL<4828> A_IWL<4827> A_IWL<4826> A_IWL<4825> A_IWL<4824> A_IWL<4823> A_IWL<4822> A_IWL<4821> A_IWL<4820> A_IWL<4819> A_IWL<4818> A_IWL<4817> A_IWL<4816> A_IWL<4815> A_IWL<4814> A_IWL<4813> A_IWL<4812> A_IWL<4811> A_IWL<4810> A_IWL<4809> A_IWL<4808> A_IWL<4807> A_IWL<4806> A_IWL<4805> A_IWL<4804> A_IWL<4803> A_IWL<4802> A_IWL<4801> A_IWL<4800> A_IWL<4799> A_IWL<4798> A_IWL<4797> A_IWL<4796> A_IWL<4795> A_IWL<4794> A_IWL<4793> A_IWL<4792> A_IWL<4791> A_IWL<4790> A_IWL<4789> A_IWL<4788> A_IWL<4787> A_IWL<4786> A_IWL<4785> A_IWL<4784> A_IWL<4783> A_IWL<4782> A_IWL<4781> A_IWL<4780> A_IWL<4779> A_IWL<4778> A_IWL<4777> A_IWL<4776> A_IWL<4775> A_IWL<4774> A_IWL<4773> A_IWL<4772> A_IWL<4771> A_IWL<4770> A_IWL<4769> A_IWL<4768> A_IWL<4767> A_IWL<4766> A_IWL<4765> A_IWL<4764> A_IWL<4763> A_IWL<4762> A_IWL<4761> A_IWL<4760> A_IWL<4759> A_IWL<4758> A_IWL<4757> A_IWL<4756> A_IWL<4755> A_IWL<4754> A_IWL<4753> A_IWL<4752> A_IWL<4751> A_IWL<4750> A_IWL<4749> A_IWL<4748> A_IWL<4747> A_IWL<4746> A_IWL<4745> A_IWL<4744> A_IWL<4743> A_IWL<4742> A_IWL<4741> A_IWL<4740> A_IWL<4739> A_IWL<4738> A_IWL<4737> A_IWL<4736> A_IWL<4735> A_IWL<4734> A_IWL<4733> A_IWL<4732> A_IWL<4731> A_IWL<4730> A_IWL<4729> A_IWL<4728> A_IWL<4727> A_IWL<4726> A_IWL<4725> A_IWL<4724> A_IWL<4723> A_IWL<4722> A_IWL<4721> A_IWL<4720> A_IWL<4719> A_IWL<4718> A_IWL<4717> A_IWL<4716> A_IWL<4715> A_IWL<4714> A_IWL<4713> A_IWL<4712> A_IWL<4711> A_IWL<4710> A_IWL<4709> A_IWL<4708> A_IWL<4707> A_IWL<4706> A_IWL<4705> A_IWL<4704> A_IWL<4703> A_IWL<4702> A_IWL<4701> A_IWL<4700> A_IWL<4699> A_IWL<4698> A_IWL<4697> A_IWL<4696> A_IWL<4695> A_IWL<4694> A_IWL<4693> A_IWL<4692> A_IWL<4691> A_IWL<4690> A_IWL<4689> A_IWL<4688> A_IWL<4687> A_IWL<4686> A_IWL<4685> A_IWL<4684> A_IWL<4683> A_IWL<4682> A_IWL<4681> A_IWL<4680> A_IWL<4679> A_IWL<4678> A_IWL<4677> A_IWL<4676> A_IWL<4675> A_IWL<4674> A_IWL<4673> A_IWL<4672> A_IWL<4671> A_IWL<4670> A_IWL<4669> A_IWL<4668> A_IWL<4667> A_IWL<4666> A_IWL<4665> A_IWL<4664> A_IWL<4663> A_IWL<4662> A_IWL<4661> A_IWL<4660> A_IWL<4659> A_IWL<4658> A_IWL<4657> A_IWL<4656> A_IWL<4655> A_IWL<4654> A_IWL<4653> A_IWL<4652> A_IWL<4651> A_IWL<4650> A_IWL<4649> A_IWL<4648> A_IWL<4647> A_IWL<4646> A_IWL<4645> A_IWL<4644> A_IWL<4643> A_IWL<4642> A_IWL<4641> A_IWL<4640> A_IWL<4639> A_IWL<4638> A_IWL<4637> A_IWL<4636> A_IWL<4635> A_IWL<4634> A_IWL<4633> A_IWL<4632> A_IWL<4631> A_IWL<4630> A_IWL<4629> A_IWL<4628> A_IWL<4627> A_IWL<4626> A_IWL<4625> A_IWL<4624> A_IWL<4623> A_IWL<4622> A_IWL<4621> A_IWL<4620> A_IWL<4619> A_IWL<4618> A_IWL<4617> A_IWL<4616> A_IWL<4615> A_IWL<4614> A_IWL<4613> A_IWL<4612> A_IWL<4611> A_IWL<4610> A_IWL<4609> A_IWL<4608> VDD_CORE VSS / RM_IHPSG13_8192x32_c4_1P_COLUMN_pcell_0 +XCOL<8> A_BLC<17> A_BLC<16> A_BLC_TOP<17> A_BLC_TOP<16> A_BLT<17> A_BLT<16> A_BLT_TOP<17> A_BLT_TOP<16> A_IWL<4095> A_IWL<4094> A_IWL<4093> A_IWL<4092> A_IWL<4091> A_IWL<4090> A_IWL<4089> A_IWL<4088> A_IWL<4087> A_IWL<4086> A_IWL<4085> A_IWL<4084> A_IWL<4083> A_IWL<4082> A_IWL<4081> A_IWL<4080> A_IWL<4079> A_IWL<4078> A_IWL<4077> A_IWL<4076> A_IWL<4075> A_IWL<4074> A_IWL<4073> A_IWL<4072> A_IWL<4071> A_IWL<4070> A_IWL<4069> A_IWL<4068> A_IWL<4067> A_IWL<4066> A_IWL<4065> A_IWL<4064> A_IWL<4063> A_IWL<4062> A_IWL<4061> A_IWL<4060> A_IWL<4059> A_IWL<4058> A_IWL<4057> A_IWL<4056> A_IWL<4055> A_IWL<4054> A_IWL<4053> A_IWL<4052> A_IWL<4051> A_IWL<4050> A_IWL<4049> A_IWL<4048> A_IWL<4047> A_IWL<4046> A_IWL<4045> A_IWL<4044> A_IWL<4043> A_IWL<4042> A_IWL<4041> A_IWL<4040> A_IWL<4039> A_IWL<4038> A_IWL<4037> A_IWL<4036> A_IWL<4035> A_IWL<4034> A_IWL<4033> A_IWL<4032> A_IWL<4031> A_IWL<4030> A_IWL<4029> A_IWL<4028> A_IWL<4027> A_IWL<4026> A_IWL<4025> A_IWL<4024> A_IWL<4023> A_IWL<4022> A_IWL<4021> A_IWL<4020> A_IWL<4019> A_IWL<4018> A_IWL<4017> A_IWL<4016> A_IWL<4015> A_IWL<4014> A_IWL<4013> A_IWL<4012> A_IWL<4011> A_IWL<4010> A_IWL<4009> A_IWL<4008> A_IWL<4007> A_IWL<4006> A_IWL<4005> A_IWL<4004> A_IWL<4003> A_IWL<4002> A_IWL<4001> A_IWL<4000> A_IWL<3999> A_IWL<3998> A_IWL<3997> A_IWL<3996> A_IWL<3995> A_IWL<3994> A_IWL<3993> A_IWL<3992> A_IWL<3991> A_IWL<3990> A_IWL<3989> A_IWL<3988> A_IWL<3987> A_IWL<3986> A_IWL<3985> A_IWL<3984> A_IWL<3983> A_IWL<3982> A_IWL<3981> A_IWL<3980> A_IWL<3979> A_IWL<3978> A_IWL<3977> A_IWL<3976> A_IWL<3975> A_IWL<3974> A_IWL<3973> A_IWL<3972> A_IWL<3971> A_IWL<3970> A_IWL<3969> A_IWL<3968> A_IWL<3967> A_IWL<3966> A_IWL<3965> A_IWL<3964> A_IWL<3963> A_IWL<3962> A_IWL<3961> A_IWL<3960> A_IWL<3959> A_IWL<3958> A_IWL<3957> A_IWL<3956> A_IWL<3955> A_IWL<3954> A_IWL<3953> A_IWL<3952> A_IWL<3951> A_IWL<3950> A_IWL<3949> A_IWL<3948> A_IWL<3947> A_IWL<3946> A_IWL<3945> A_IWL<3944> A_IWL<3943> A_IWL<3942> A_IWL<3941> A_IWL<3940> A_IWL<3939> A_IWL<3938> A_IWL<3937> A_IWL<3936> A_IWL<3935> A_IWL<3934> A_IWL<3933> A_IWL<3932> A_IWL<3931> A_IWL<3930> A_IWL<3929> A_IWL<3928> A_IWL<3927> A_IWL<3926> A_IWL<3925> A_IWL<3924> A_IWL<3923> A_IWL<3922> A_IWL<3921> A_IWL<3920> A_IWL<3919> A_IWL<3918> A_IWL<3917> A_IWL<3916> A_IWL<3915> A_IWL<3914> A_IWL<3913> A_IWL<3912> A_IWL<3911> A_IWL<3910> A_IWL<3909> A_IWL<3908> A_IWL<3907> A_IWL<3906> A_IWL<3905> A_IWL<3904> A_IWL<3903> A_IWL<3902> A_IWL<3901> A_IWL<3900> A_IWL<3899> A_IWL<3898> A_IWL<3897> A_IWL<3896> A_IWL<3895> A_IWL<3894> A_IWL<3893> A_IWL<3892> A_IWL<3891> A_IWL<3890> A_IWL<3889> A_IWL<3888> A_IWL<3887> A_IWL<3886> A_IWL<3885> A_IWL<3884> A_IWL<3883> A_IWL<3882> A_IWL<3881> A_IWL<3880> A_IWL<3879> A_IWL<3878> A_IWL<3877> A_IWL<3876> A_IWL<3875> A_IWL<3874> A_IWL<3873> A_IWL<3872> A_IWL<3871> A_IWL<3870> A_IWL<3869> A_IWL<3868> A_IWL<3867> A_IWL<3866> A_IWL<3865> A_IWL<3864> A_IWL<3863> A_IWL<3862> A_IWL<3861> A_IWL<3860> A_IWL<3859> A_IWL<3858> A_IWL<3857> A_IWL<3856> A_IWL<3855> A_IWL<3854> A_IWL<3853> A_IWL<3852> A_IWL<3851> A_IWL<3850> A_IWL<3849> A_IWL<3848> A_IWL<3847> A_IWL<3846> A_IWL<3845> A_IWL<3844> A_IWL<3843> A_IWL<3842> A_IWL<3841> A_IWL<3840> A_IWL<3839> A_IWL<3838> A_IWL<3837> A_IWL<3836> A_IWL<3835> A_IWL<3834> A_IWL<3833> A_IWL<3832> A_IWL<3831> A_IWL<3830> A_IWL<3829> A_IWL<3828> A_IWL<3827> A_IWL<3826> A_IWL<3825> A_IWL<3824> A_IWL<3823> A_IWL<3822> A_IWL<3821> A_IWL<3820> A_IWL<3819> A_IWL<3818> A_IWL<3817> A_IWL<3816> A_IWL<3815> A_IWL<3814> A_IWL<3813> A_IWL<3812> A_IWL<3811> A_IWL<3810> A_IWL<3809> A_IWL<3808> A_IWL<3807> A_IWL<3806> A_IWL<3805> A_IWL<3804> A_IWL<3803> A_IWL<3802> A_IWL<3801> A_IWL<3800> A_IWL<3799> A_IWL<3798> A_IWL<3797> A_IWL<3796> A_IWL<3795> A_IWL<3794> A_IWL<3793> A_IWL<3792> A_IWL<3791> A_IWL<3790> A_IWL<3789> A_IWL<3788> A_IWL<3787> A_IWL<3786> A_IWL<3785> A_IWL<3784> A_IWL<3783> A_IWL<3782> A_IWL<3781> A_IWL<3780> A_IWL<3779> A_IWL<3778> A_IWL<3777> A_IWL<3776> A_IWL<3775> A_IWL<3774> A_IWL<3773> A_IWL<3772> A_IWL<3771> A_IWL<3770> A_IWL<3769> A_IWL<3768> A_IWL<3767> A_IWL<3766> A_IWL<3765> A_IWL<3764> A_IWL<3763> A_IWL<3762> A_IWL<3761> A_IWL<3760> A_IWL<3759> A_IWL<3758> A_IWL<3757> A_IWL<3756> A_IWL<3755> A_IWL<3754> A_IWL<3753> A_IWL<3752> A_IWL<3751> A_IWL<3750> A_IWL<3749> A_IWL<3748> A_IWL<3747> A_IWL<3746> A_IWL<3745> A_IWL<3744> A_IWL<3743> A_IWL<3742> A_IWL<3741> A_IWL<3740> A_IWL<3739> A_IWL<3738> A_IWL<3737> A_IWL<3736> A_IWL<3735> A_IWL<3734> A_IWL<3733> A_IWL<3732> A_IWL<3731> A_IWL<3730> A_IWL<3729> A_IWL<3728> A_IWL<3727> A_IWL<3726> A_IWL<3725> A_IWL<3724> A_IWL<3723> A_IWL<3722> A_IWL<3721> A_IWL<3720> A_IWL<3719> A_IWL<3718> A_IWL<3717> A_IWL<3716> A_IWL<3715> A_IWL<3714> A_IWL<3713> A_IWL<3712> A_IWL<3711> A_IWL<3710> A_IWL<3709> A_IWL<3708> A_IWL<3707> A_IWL<3706> A_IWL<3705> A_IWL<3704> A_IWL<3703> A_IWL<3702> A_IWL<3701> A_IWL<3700> A_IWL<3699> A_IWL<3698> A_IWL<3697> A_IWL<3696> A_IWL<3695> A_IWL<3694> A_IWL<3693> A_IWL<3692> A_IWL<3691> A_IWL<3690> A_IWL<3689> A_IWL<3688> A_IWL<3687> A_IWL<3686> A_IWL<3685> A_IWL<3684> A_IWL<3683> A_IWL<3682> A_IWL<3681> A_IWL<3680> A_IWL<3679> A_IWL<3678> A_IWL<3677> A_IWL<3676> A_IWL<3675> A_IWL<3674> A_IWL<3673> A_IWL<3672> A_IWL<3671> A_IWL<3670> A_IWL<3669> A_IWL<3668> A_IWL<3667> A_IWL<3666> A_IWL<3665> A_IWL<3664> A_IWL<3663> A_IWL<3662> A_IWL<3661> A_IWL<3660> A_IWL<3659> A_IWL<3658> A_IWL<3657> A_IWL<3656> A_IWL<3655> A_IWL<3654> A_IWL<3653> A_IWL<3652> A_IWL<3651> A_IWL<3650> A_IWL<3649> A_IWL<3648> A_IWL<3647> A_IWL<3646> A_IWL<3645> A_IWL<3644> A_IWL<3643> A_IWL<3642> A_IWL<3641> A_IWL<3640> A_IWL<3639> A_IWL<3638> A_IWL<3637> A_IWL<3636> A_IWL<3635> A_IWL<3634> A_IWL<3633> A_IWL<3632> A_IWL<3631> A_IWL<3630> A_IWL<3629> A_IWL<3628> A_IWL<3627> A_IWL<3626> A_IWL<3625> A_IWL<3624> A_IWL<3623> A_IWL<3622> A_IWL<3621> A_IWL<3620> A_IWL<3619> A_IWL<3618> A_IWL<3617> A_IWL<3616> A_IWL<3615> A_IWL<3614> A_IWL<3613> A_IWL<3612> A_IWL<3611> A_IWL<3610> A_IWL<3609> A_IWL<3608> A_IWL<3607> A_IWL<3606> A_IWL<3605> A_IWL<3604> A_IWL<3603> A_IWL<3602> A_IWL<3601> A_IWL<3600> A_IWL<3599> A_IWL<3598> A_IWL<3597> A_IWL<3596> A_IWL<3595> A_IWL<3594> A_IWL<3593> A_IWL<3592> A_IWL<3591> A_IWL<3590> A_IWL<3589> A_IWL<3588> A_IWL<3587> A_IWL<3586> A_IWL<3585> A_IWL<3584> A_IWL<4607> A_IWL<4606> A_IWL<4605> A_IWL<4604> A_IWL<4603> A_IWL<4602> A_IWL<4601> A_IWL<4600> A_IWL<4599> A_IWL<4598> A_IWL<4597> A_IWL<4596> A_IWL<4595> A_IWL<4594> A_IWL<4593> A_IWL<4592> A_IWL<4591> A_IWL<4590> A_IWL<4589> A_IWL<4588> A_IWL<4587> A_IWL<4586> A_IWL<4585> A_IWL<4584> A_IWL<4583> A_IWL<4582> A_IWL<4581> A_IWL<4580> A_IWL<4579> A_IWL<4578> A_IWL<4577> A_IWL<4576> A_IWL<4575> A_IWL<4574> A_IWL<4573> A_IWL<4572> A_IWL<4571> A_IWL<4570> A_IWL<4569> A_IWL<4568> A_IWL<4567> A_IWL<4566> A_IWL<4565> A_IWL<4564> A_IWL<4563> A_IWL<4562> A_IWL<4561> A_IWL<4560> A_IWL<4559> A_IWL<4558> A_IWL<4557> A_IWL<4556> A_IWL<4555> A_IWL<4554> A_IWL<4553> A_IWL<4552> A_IWL<4551> A_IWL<4550> A_IWL<4549> A_IWL<4548> A_IWL<4547> A_IWL<4546> A_IWL<4545> A_IWL<4544> A_IWL<4543> A_IWL<4542> A_IWL<4541> A_IWL<4540> A_IWL<4539> A_IWL<4538> A_IWL<4537> A_IWL<4536> A_IWL<4535> A_IWL<4534> A_IWL<4533> A_IWL<4532> A_IWL<4531> A_IWL<4530> A_IWL<4529> A_IWL<4528> A_IWL<4527> A_IWL<4526> A_IWL<4525> A_IWL<4524> A_IWL<4523> A_IWL<4522> A_IWL<4521> A_IWL<4520> A_IWL<4519> A_IWL<4518> A_IWL<4517> A_IWL<4516> A_IWL<4515> A_IWL<4514> A_IWL<4513> A_IWL<4512> A_IWL<4511> A_IWL<4510> A_IWL<4509> A_IWL<4508> A_IWL<4507> A_IWL<4506> A_IWL<4505> A_IWL<4504> A_IWL<4503> A_IWL<4502> A_IWL<4501> A_IWL<4500> A_IWL<4499> A_IWL<4498> A_IWL<4497> A_IWL<4496> A_IWL<4495> A_IWL<4494> A_IWL<4493> A_IWL<4492> A_IWL<4491> A_IWL<4490> A_IWL<4489> A_IWL<4488> A_IWL<4487> A_IWL<4486> A_IWL<4485> A_IWL<4484> A_IWL<4483> A_IWL<4482> A_IWL<4481> A_IWL<4480> A_IWL<4479> A_IWL<4478> A_IWL<4477> A_IWL<4476> A_IWL<4475> A_IWL<4474> A_IWL<4473> A_IWL<4472> A_IWL<4471> A_IWL<4470> A_IWL<4469> A_IWL<4468> A_IWL<4467> A_IWL<4466> A_IWL<4465> A_IWL<4464> A_IWL<4463> A_IWL<4462> A_IWL<4461> A_IWL<4460> A_IWL<4459> A_IWL<4458> A_IWL<4457> A_IWL<4456> A_IWL<4455> A_IWL<4454> A_IWL<4453> A_IWL<4452> A_IWL<4451> A_IWL<4450> A_IWL<4449> A_IWL<4448> A_IWL<4447> A_IWL<4446> A_IWL<4445> A_IWL<4444> A_IWL<4443> A_IWL<4442> A_IWL<4441> A_IWL<4440> A_IWL<4439> A_IWL<4438> A_IWL<4437> A_IWL<4436> A_IWL<4435> A_IWL<4434> A_IWL<4433> A_IWL<4432> A_IWL<4431> A_IWL<4430> A_IWL<4429> A_IWL<4428> A_IWL<4427> A_IWL<4426> A_IWL<4425> A_IWL<4424> A_IWL<4423> A_IWL<4422> A_IWL<4421> A_IWL<4420> A_IWL<4419> A_IWL<4418> A_IWL<4417> A_IWL<4416> A_IWL<4415> A_IWL<4414> A_IWL<4413> A_IWL<4412> A_IWL<4411> A_IWL<4410> A_IWL<4409> A_IWL<4408> A_IWL<4407> A_IWL<4406> A_IWL<4405> A_IWL<4404> A_IWL<4403> A_IWL<4402> A_IWL<4401> A_IWL<4400> A_IWL<4399> A_IWL<4398> A_IWL<4397> A_IWL<4396> A_IWL<4395> A_IWL<4394> A_IWL<4393> A_IWL<4392> A_IWL<4391> A_IWL<4390> A_IWL<4389> A_IWL<4388> A_IWL<4387> A_IWL<4386> A_IWL<4385> A_IWL<4384> A_IWL<4383> A_IWL<4382> A_IWL<4381> A_IWL<4380> A_IWL<4379> A_IWL<4378> A_IWL<4377> A_IWL<4376> A_IWL<4375> A_IWL<4374> A_IWL<4373> A_IWL<4372> A_IWL<4371> A_IWL<4370> A_IWL<4369> A_IWL<4368> A_IWL<4367> A_IWL<4366> A_IWL<4365> A_IWL<4364> A_IWL<4363> A_IWL<4362> A_IWL<4361> A_IWL<4360> A_IWL<4359> A_IWL<4358> A_IWL<4357> A_IWL<4356> A_IWL<4355> A_IWL<4354> A_IWL<4353> A_IWL<4352> A_IWL<4351> A_IWL<4350> A_IWL<4349> A_IWL<4348> A_IWL<4347> A_IWL<4346> A_IWL<4345> A_IWL<4344> A_IWL<4343> A_IWL<4342> A_IWL<4341> A_IWL<4340> A_IWL<4339> A_IWL<4338> A_IWL<4337> A_IWL<4336> A_IWL<4335> A_IWL<4334> A_IWL<4333> A_IWL<4332> A_IWL<4331> A_IWL<4330> A_IWL<4329> A_IWL<4328> A_IWL<4327> A_IWL<4326> A_IWL<4325> A_IWL<4324> A_IWL<4323> A_IWL<4322> A_IWL<4321> A_IWL<4320> A_IWL<4319> A_IWL<4318> A_IWL<4317> A_IWL<4316> A_IWL<4315> A_IWL<4314> A_IWL<4313> A_IWL<4312> A_IWL<4311> A_IWL<4310> A_IWL<4309> A_IWL<4308> A_IWL<4307> A_IWL<4306> A_IWL<4305> A_IWL<4304> A_IWL<4303> A_IWL<4302> A_IWL<4301> A_IWL<4300> A_IWL<4299> A_IWL<4298> A_IWL<4297> A_IWL<4296> A_IWL<4295> A_IWL<4294> A_IWL<4293> A_IWL<4292> A_IWL<4291> A_IWL<4290> A_IWL<4289> A_IWL<4288> A_IWL<4287> A_IWL<4286> A_IWL<4285> A_IWL<4284> A_IWL<4283> A_IWL<4282> A_IWL<4281> A_IWL<4280> A_IWL<4279> A_IWL<4278> A_IWL<4277> A_IWL<4276> A_IWL<4275> A_IWL<4274> A_IWL<4273> A_IWL<4272> A_IWL<4271> A_IWL<4270> A_IWL<4269> A_IWL<4268> A_IWL<4267> A_IWL<4266> A_IWL<4265> A_IWL<4264> A_IWL<4263> A_IWL<4262> A_IWL<4261> A_IWL<4260> A_IWL<4259> A_IWL<4258> A_IWL<4257> A_IWL<4256> A_IWL<4255> A_IWL<4254> A_IWL<4253> A_IWL<4252> A_IWL<4251> A_IWL<4250> A_IWL<4249> A_IWL<4248> A_IWL<4247> A_IWL<4246> A_IWL<4245> A_IWL<4244> A_IWL<4243> A_IWL<4242> A_IWL<4241> A_IWL<4240> A_IWL<4239> A_IWL<4238> A_IWL<4237> A_IWL<4236> A_IWL<4235> A_IWL<4234> A_IWL<4233> A_IWL<4232> A_IWL<4231> A_IWL<4230> A_IWL<4229> A_IWL<4228> A_IWL<4227> A_IWL<4226> A_IWL<4225> A_IWL<4224> A_IWL<4223> A_IWL<4222> A_IWL<4221> A_IWL<4220> A_IWL<4219> A_IWL<4218> A_IWL<4217> A_IWL<4216> A_IWL<4215> A_IWL<4214> A_IWL<4213> A_IWL<4212> A_IWL<4211> A_IWL<4210> A_IWL<4209> A_IWL<4208> A_IWL<4207> A_IWL<4206> A_IWL<4205> A_IWL<4204> A_IWL<4203> A_IWL<4202> A_IWL<4201> A_IWL<4200> A_IWL<4199> A_IWL<4198> A_IWL<4197> A_IWL<4196> A_IWL<4195> A_IWL<4194> A_IWL<4193> A_IWL<4192> A_IWL<4191> A_IWL<4190> A_IWL<4189> A_IWL<4188> A_IWL<4187> A_IWL<4186> A_IWL<4185> A_IWL<4184> A_IWL<4183> A_IWL<4182> A_IWL<4181> A_IWL<4180> A_IWL<4179> A_IWL<4178> A_IWL<4177> A_IWL<4176> A_IWL<4175> A_IWL<4174> A_IWL<4173> A_IWL<4172> A_IWL<4171> A_IWL<4170> A_IWL<4169> A_IWL<4168> A_IWL<4167> A_IWL<4166> A_IWL<4165> A_IWL<4164> A_IWL<4163> A_IWL<4162> A_IWL<4161> A_IWL<4160> A_IWL<4159> A_IWL<4158> A_IWL<4157> A_IWL<4156> A_IWL<4155> A_IWL<4154> A_IWL<4153> A_IWL<4152> A_IWL<4151> A_IWL<4150> A_IWL<4149> A_IWL<4148> A_IWL<4147> A_IWL<4146> A_IWL<4145> A_IWL<4144> A_IWL<4143> A_IWL<4142> A_IWL<4141> A_IWL<4140> A_IWL<4139> A_IWL<4138> A_IWL<4137> A_IWL<4136> A_IWL<4135> A_IWL<4134> A_IWL<4133> A_IWL<4132> A_IWL<4131> A_IWL<4130> A_IWL<4129> A_IWL<4128> A_IWL<4127> A_IWL<4126> A_IWL<4125> A_IWL<4124> A_IWL<4123> A_IWL<4122> A_IWL<4121> A_IWL<4120> A_IWL<4119> A_IWL<4118> A_IWL<4117> A_IWL<4116> A_IWL<4115> A_IWL<4114> A_IWL<4113> A_IWL<4112> A_IWL<4111> A_IWL<4110> A_IWL<4109> A_IWL<4108> A_IWL<4107> A_IWL<4106> A_IWL<4105> A_IWL<4104> A_IWL<4103> A_IWL<4102> A_IWL<4101> A_IWL<4100> A_IWL<4099> A_IWL<4098> A_IWL<4097> A_IWL<4096> VDD_CORE VSS / RM_IHPSG13_8192x32_c4_1P_COLUMN_pcell_0 +XCOL<7> A_BLC<15> A_BLC<14> A_BLC_TOP<15> A_BLC_TOP<14> A_BLT<15> A_BLT<14> A_BLT_TOP<15> A_BLT_TOP<14> A_IWL<3583> A_IWL<3582> A_IWL<3581> A_IWL<3580> A_IWL<3579> A_IWL<3578> A_IWL<3577> A_IWL<3576> A_IWL<3575> A_IWL<3574> A_IWL<3573> A_IWL<3572> A_IWL<3571> A_IWL<3570> A_IWL<3569> A_IWL<3568> A_IWL<3567> A_IWL<3566> A_IWL<3565> A_IWL<3564> A_IWL<3563> A_IWL<3562> A_IWL<3561> A_IWL<3560> A_IWL<3559> A_IWL<3558> A_IWL<3557> A_IWL<3556> A_IWL<3555> A_IWL<3554> A_IWL<3553> A_IWL<3552> A_IWL<3551> A_IWL<3550> A_IWL<3549> A_IWL<3548> A_IWL<3547> A_IWL<3546> A_IWL<3545> A_IWL<3544> A_IWL<3543> A_IWL<3542> A_IWL<3541> A_IWL<3540> A_IWL<3539> A_IWL<3538> A_IWL<3537> A_IWL<3536> A_IWL<3535> A_IWL<3534> A_IWL<3533> A_IWL<3532> A_IWL<3531> A_IWL<3530> A_IWL<3529> A_IWL<3528> A_IWL<3527> A_IWL<3526> A_IWL<3525> A_IWL<3524> A_IWL<3523> A_IWL<3522> A_IWL<3521> A_IWL<3520> A_IWL<3519> A_IWL<3518> A_IWL<3517> A_IWL<3516> A_IWL<3515> A_IWL<3514> A_IWL<3513> A_IWL<3512> A_IWL<3511> A_IWL<3510> A_IWL<3509> A_IWL<3508> A_IWL<3507> A_IWL<3506> A_IWL<3505> A_IWL<3504> A_IWL<3503> A_IWL<3502> A_IWL<3501> A_IWL<3500> A_IWL<3499> A_IWL<3498> A_IWL<3497> A_IWL<3496> A_IWL<3495> A_IWL<3494> A_IWL<3493> A_IWL<3492> A_IWL<3491> A_IWL<3490> A_IWL<3489> A_IWL<3488> A_IWL<3487> A_IWL<3486> A_IWL<3485> A_IWL<3484> A_IWL<3483> A_IWL<3482> A_IWL<3481> A_IWL<3480> A_IWL<3479> A_IWL<3478> A_IWL<3477> A_IWL<3476> A_IWL<3475> A_IWL<3474> A_IWL<3473> A_IWL<3472> A_IWL<3471> A_IWL<3470> A_IWL<3469> A_IWL<3468> A_IWL<3467> A_IWL<3466> A_IWL<3465> A_IWL<3464> A_IWL<3463> A_IWL<3462> A_IWL<3461> A_IWL<3460> A_IWL<3459> A_IWL<3458> A_IWL<3457> A_IWL<3456> A_IWL<3455> A_IWL<3454> A_IWL<3453> A_IWL<3452> A_IWL<3451> A_IWL<3450> A_IWL<3449> A_IWL<3448> A_IWL<3447> A_IWL<3446> A_IWL<3445> A_IWL<3444> A_IWL<3443> A_IWL<3442> A_IWL<3441> A_IWL<3440> A_IWL<3439> A_IWL<3438> A_IWL<3437> A_IWL<3436> A_IWL<3435> A_IWL<3434> A_IWL<3433> A_IWL<3432> A_IWL<3431> A_IWL<3430> A_IWL<3429> A_IWL<3428> A_IWL<3427> A_IWL<3426> A_IWL<3425> A_IWL<3424> A_IWL<3423> A_IWL<3422> A_IWL<3421> A_IWL<3420> A_IWL<3419> A_IWL<3418> A_IWL<3417> A_IWL<3416> A_IWL<3415> A_IWL<3414> A_IWL<3413> A_IWL<3412> A_IWL<3411> A_IWL<3410> A_IWL<3409> A_IWL<3408> A_IWL<3407> A_IWL<3406> A_IWL<3405> A_IWL<3404> A_IWL<3403> A_IWL<3402> A_IWL<3401> A_IWL<3400> A_IWL<3399> A_IWL<3398> A_IWL<3397> A_IWL<3396> A_IWL<3395> A_IWL<3394> A_IWL<3393> A_IWL<3392> A_IWL<3391> A_IWL<3390> A_IWL<3389> A_IWL<3388> A_IWL<3387> A_IWL<3386> A_IWL<3385> A_IWL<3384> A_IWL<3383> A_IWL<3382> A_IWL<3381> A_IWL<3380> A_IWL<3379> A_IWL<3378> A_IWL<3377> A_IWL<3376> A_IWL<3375> A_IWL<3374> A_IWL<3373> A_IWL<3372> A_IWL<3371> A_IWL<3370> A_IWL<3369> A_IWL<3368> A_IWL<3367> A_IWL<3366> A_IWL<3365> A_IWL<3364> A_IWL<3363> A_IWL<3362> A_IWL<3361> A_IWL<3360> A_IWL<3359> A_IWL<3358> A_IWL<3357> A_IWL<3356> A_IWL<3355> A_IWL<3354> A_IWL<3353> A_IWL<3352> A_IWL<3351> A_IWL<3350> A_IWL<3349> A_IWL<3348> A_IWL<3347> A_IWL<3346> A_IWL<3345> A_IWL<3344> A_IWL<3343> A_IWL<3342> A_IWL<3341> A_IWL<3340> A_IWL<3339> A_IWL<3338> A_IWL<3337> A_IWL<3336> A_IWL<3335> A_IWL<3334> A_IWL<3333> A_IWL<3332> A_IWL<3331> A_IWL<3330> A_IWL<3329> A_IWL<3328> A_IWL<3327> A_IWL<3326> A_IWL<3325> A_IWL<3324> A_IWL<3323> A_IWL<3322> A_IWL<3321> A_IWL<3320> A_IWL<3319> A_IWL<3318> A_IWL<3317> A_IWL<3316> A_IWL<3315> A_IWL<3314> A_IWL<3313> A_IWL<3312> A_IWL<3311> A_IWL<3310> A_IWL<3309> A_IWL<3308> A_IWL<3307> A_IWL<3306> A_IWL<3305> A_IWL<3304> A_IWL<3303> A_IWL<3302> A_IWL<3301> A_IWL<3300> A_IWL<3299> A_IWL<3298> A_IWL<3297> A_IWL<3296> A_IWL<3295> A_IWL<3294> A_IWL<3293> A_IWL<3292> A_IWL<3291> A_IWL<3290> A_IWL<3289> A_IWL<3288> A_IWL<3287> A_IWL<3286> A_IWL<3285> A_IWL<3284> A_IWL<3283> A_IWL<3282> A_IWL<3281> A_IWL<3280> A_IWL<3279> A_IWL<3278> A_IWL<3277> A_IWL<3276> A_IWL<3275> A_IWL<3274> A_IWL<3273> A_IWL<3272> A_IWL<3271> A_IWL<3270> A_IWL<3269> A_IWL<3268> A_IWL<3267> A_IWL<3266> A_IWL<3265> A_IWL<3264> A_IWL<3263> A_IWL<3262> A_IWL<3261> A_IWL<3260> A_IWL<3259> A_IWL<3258> A_IWL<3257> A_IWL<3256> A_IWL<3255> A_IWL<3254> A_IWL<3253> A_IWL<3252> A_IWL<3251> A_IWL<3250> A_IWL<3249> A_IWL<3248> A_IWL<3247> A_IWL<3246> A_IWL<3245> A_IWL<3244> A_IWL<3243> A_IWL<3242> A_IWL<3241> A_IWL<3240> A_IWL<3239> A_IWL<3238> A_IWL<3237> A_IWL<3236> A_IWL<3235> A_IWL<3234> A_IWL<3233> A_IWL<3232> A_IWL<3231> A_IWL<3230> A_IWL<3229> A_IWL<3228> A_IWL<3227> A_IWL<3226> A_IWL<3225> A_IWL<3224> A_IWL<3223> A_IWL<3222> A_IWL<3221> A_IWL<3220> A_IWL<3219> A_IWL<3218> A_IWL<3217> A_IWL<3216> A_IWL<3215> A_IWL<3214> A_IWL<3213> A_IWL<3212> A_IWL<3211> A_IWL<3210> A_IWL<3209> A_IWL<3208> A_IWL<3207> A_IWL<3206> A_IWL<3205> A_IWL<3204> A_IWL<3203> A_IWL<3202> A_IWL<3201> A_IWL<3200> A_IWL<3199> A_IWL<3198> A_IWL<3197> A_IWL<3196> A_IWL<3195> A_IWL<3194> A_IWL<3193> A_IWL<3192> A_IWL<3191> A_IWL<3190> A_IWL<3189> A_IWL<3188> A_IWL<3187> A_IWL<3186> A_IWL<3185> A_IWL<3184> A_IWL<3183> A_IWL<3182> A_IWL<3181> A_IWL<3180> A_IWL<3179> A_IWL<3178> A_IWL<3177> A_IWL<3176> A_IWL<3175> A_IWL<3174> A_IWL<3173> A_IWL<3172> A_IWL<3171> A_IWL<3170> A_IWL<3169> A_IWL<3168> A_IWL<3167> A_IWL<3166> A_IWL<3165> A_IWL<3164> A_IWL<3163> A_IWL<3162> A_IWL<3161> A_IWL<3160> A_IWL<3159> A_IWL<3158> A_IWL<3157> A_IWL<3156> A_IWL<3155> A_IWL<3154> A_IWL<3153> A_IWL<3152> A_IWL<3151> A_IWL<3150> A_IWL<3149> A_IWL<3148> A_IWL<3147> A_IWL<3146> A_IWL<3145> A_IWL<3144> A_IWL<3143> A_IWL<3142> A_IWL<3141> A_IWL<3140> A_IWL<3139> A_IWL<3138> A_IWL<3137> A_IWL<3136> A_IWL<3135> A_IWL<3134> A_IWL<3133> A_IWL<3132> A_IWL<3131> A_IWL<3130> A_IWL<3129> A_IWL<3128> A_IWL<3127> A_IWL<3126> A_IWL<3125> A_IWL<3124> A_IWL<3123> A_IWL<3122> A_IWL<3121> A_IWL<3120> A_IWL<3119> A_IWL<3118> A_IWL<3117> A_IWL<3116> A_IWL<3115> A_IWL<3114> A_IWL<3113> A_IWL<3112> A_IWL<3111> A_IWL<3110> A_IWL<3109> A_IWL<3108> A_IWL<3107> A_IWL<3106> A_IWL<3105> A_IWL<3104> A_IWL<3103> A_IWL<3102> A_IWL<3101> A_IWL<3100> A_IWL<3099> A_IWL<3098> A_IWL<3097> A_IWL<3096> A_IWL<3095> A_IWL<3094> A_IWL<3093> A_IWL<3092> A_IWL<3091> A_IWL<3090> A_IWL<3089> A_IWL<3088> A_IWL<3087> A_IWL<3086> A_IWL<3085> A_IWL<3084> A_IWL<3083> A_IWL<3082> A_IWL<3081> A_IWL<3080> A_IWL<3079> A_IWL<3078> A_IWL<3077> A_IWL<3076> A_IWL<3075> A_IWL<3074> A_IWL<3073> A_IWL<3072> A_IWL<4095> A_IWL<4094> A_IWL<4093> A_IWL<4092> A_IWL<4091> A_IWL<4090> A_IWL<4089> A_IWL<4088> A_IWL<4087> A_IWL<4086> A_IWL<4085> A_IWL<4084> A_IWL<4083> A_IWL<4082> A_IWL<4081> A_IWL<4080> A_IWL<4079> A_IWL<4078> A_IWL<4077> A_IWL<4076> A_IWL<4075> A_IWL<4074> A_IWL<4073> A_IWL<4072> A_IWL<4071> A_IWL<4070> A_IWL<4069> A_IWL<4068> A_IWL<4067> A_IWL<4066> A_IWL<4065> A_IWL<4064> A_IWL<4063> A_IWL<4062> A_IWL<4061> A_IWL<4060> A_IWL<4059> A_IWL<4058> A_IWL<4057> A_IWL<4056> A_IWL<4055> A_IWL<4054> A_IWL<4053> A_IWL<4052> A_IWL<4051> A_IWL<4050> A_IWL<4049> A_IWL<4048> A_IWL<4047> A_IWL<4046> A_IWL<4045> A_IWL<4044> A_IWL<4043> A_IWL<4042> A_IWL<4041> A_IWL<4040> A_IWL<4039> A_IWL<4038> A_IWL<4037> A_IWL<4036> A_IWL<4035> A_IWL<4034> A_IWL<4033> A_IWL<4032> A_IWL<4031> A_IWL<4030> A_IWL<4029> A_IWL<4028> A_IWL<4027> A_IWL<4026> A_IWL<4025> A_IWL<4024> A_IWL<4023> A_IWL<4022> A_IWL<4021> A_IWL<4020> A_IWL<4019> A_IWL<4018> A_IWL<4017> A_IWL<4016> A_IWL<4015> A_IWL<4014> A_IWL<4013> A_IWL<4012> A_IWL<4011> A_IWL<4010> A_IWL<4009> A_IWL<4008> A_IWL<4007> A_IWL<4006> A_IWL<4005> A_IWL<4004> A_IWL<4003> A_IWL<4002> A_IWL<4001> A_IWL<4000> A_IWL<3999> A_IWL<3998> A_IWL<3997> A_IWL<3996> A_IWL<3995> A_IWL<3994> A_IWL<3993> A_IWL<3992> A_IWL<3991> A_IWL<3990> A_IWL<3989> A_IWL<3988> A_IWL<3987> A_IWL<3986> A_IWL<3985> A_IWL<3984> A_IWL<3983> A_IWL<3982> A_IWL<3981> A_IWL<3980> A_IWL<3979> A_IWL<3978> A_IWL<3977> A_IWL<3976> A_IWL<3975> A_IWL<3974> A_IWL<3973> A_IWL<3972> A_IWL<3971> A_IWL<3970> A_IWL<3969> A_IWL<3968> A_IWL<3967> A_IWL<3966> A_IWL<3965> A_IWL<3964> A_IWL<3963> A_IWL<3962> A_IWL<3961> A_IWL<3960> A_IWL<3959> A_IWL<3958> A_IWL<3957> A_IWL<3956> A_IWL<3955> A_IWL<3954> A_IWL<3953> A_IWL<3952> A_IWL<3951> A_IWL<3950> A_IWL<3949> A_IWL<3948> A_IWL<3947> A_IWL<3946> A_IWL<3945> A_IWL<3944> A_IWL<3943> A_IWL<3942> A_IWL<3941> A_IWL<3940> A_IWL<3939> A_IWL<3938> A_IWL<3937> A_IWL<3936> A_IWL<3935> A_IWL<3934> A_IWL<3933> A_IWL<3932> A_IWL<3931> A_IWL<3930> A_IWL<3929> A_IWL<3928> A_IWL<3927> A_IWL<3926> A_IWL<3925> A_IWL<3924> A_IWL<3923> A_IWL<3922> A_IWL<3921> A_IWL<3920> A_IWL<3919> A_IWL<3918> A_IWL<3917> A_IWL<3916> A_IWL<3915> A_IWL<3914> A_IWL<3913> A_IWL<3912> A_IWL<3911> A_IWL<3910> A_IWL<3909> A_IWL<3908> A_IWL<3907> A_IWL<3906> A_IWL<3905> A_IWL<3904> A_IWL<3903> A_IWL<3902> A_IWL<3901> A_IWL<3900> A_IWL<3899> A_IWL<3898> A_IWL<3897> A_IWL<3896> A_IWL<3895> A_IWL<3894> A_IWL<3893> A_IWL<3892> A_IWL<3891> A_IWL<3890> A_IWL<3889> A_IWL<3888> A_IWL<3887> A_IWL<3886> A_IWL<3885> A_IWL<3884> A_IWL<3883> A_IWL<3882> A_IWL<3881> A_IWL<3880> A_IWL<3879> A_IWL<3878> A_IWL<3877> A_IWL<3876> A_IWL<3875> A_IWL<3874> A_IWL<3873> A_IWL<3872> A_IWL<3871> A_IWL<3870> A_IWL<3869> A_IWL<3868> A_IWL<3867> A_IWL<3866> A_IWL<3865> A_IWL<3864> A_IWL<3863> A_IWL<3862> A_IWL<3861> A_IWL<3860> A_IWL<3859> A_IWL<3858> A_IWL<3857> A_IWL<3856> A_IWL<3855> A_IWL<3854> A_IWL<3853> A_IWL<3852> A_IWL<3851> A_IWL<3850> A_IWL<3849> A_IWL<3848> A_IWL<3847> A_IWL<3846> A_IWL<3845> A_IWL<3844> A_IWL<3843> A_IWL<3842> A_IWL<3841> A_IWL<3840> A_IWL<3839> A_IWL<3838> A_IWL<3837> A_IWL<3836> A_IWL<3835> A_IWL<3834> A_IWL<3833> A_IWL<3832> A_IWL<3831> A_IWL<3830> A_IWL<3829> A_IWL<3828> A_IWL<3827> A_IWL<3826> A_IWL<3825> A_IWL<3824> A_IWL<3823> A_IWL<3822> A_IWL<3821> A_IWL<3820> A_IWL<3819> A_IWL<3818> A_IWL<3817> A_IWL<3816> A_IWL<3815> A_IWL<3814> A_IWL<3813> A_IWL<3812> A_IWL<3811> A_IWL<3810> A_IWL<3809> A_IWL<3808> A_IWL<3807> A_IWL<3806> A_IWL<3805> A_IWL<3804> A_IWL<3803> A_IWL<3802> A_IWL<3801> A_IWL<3800> A_IWL<3799> A_IWL<3798> A_IWL<3797> A_IWL<3796> A_IWL<3795> A_IWL<3794> A_IWL<3793> A_IWL<3792> A_IWL<3791> A_IWL<3790> A_IWL<3789> A_IWL<3788> A_IWL<3787> A_IWL<3786> A_IWL<3785> A_IWL<3784> A_IWL<3783> A_IWL<3782> A_IWL<3781> A_IWL<3780> A_IWL<3779> A_IWL<3778> A_IWL<3777> A_IWL<3776> A_IWL<3775> A_IWL<3774> A_IWL<3773> A_IWL<3772> A_IWL<3771> A_IWL<3770> A_IWL<3769> A_IWL<3768> A_IWL<3767> A_IWL<3766> A_IWL<3765> A_IWL<3764> A_IWL<3763> A_IWL<3762> A_IWL<3761> A_IWL<3760> A_IWL<3759> A_IWL<3758> A_IWL<3757> A_IWL<3756> A_IWL<3755> A_IWL<3754> A_IWL<3753> A_IWL<3752> A_IWL<3751> A_IWL<3750> A_IWL<3749> A_IWL<3748> A_IWL<3747> A_IWL<3746> A_IWL<3745> A_IWL<3744> A_IWL<3743> A_IWL<3742> A_IWL<3741> A_IWL<3740> A_IWL<3739> A_IWL<3738> A_IWL<3737> A_IWL<3736> A_IWL<3735> A_IWL<3734> A_IWL<3733> A_IWL<3732> A_IWL<3731> A_IWL<3730> A_IWL<3729> A_IWL<3728> A_IWL<3727> A_IWL<3726> A_IWL<3725> A_IWL<3724> A_IWL<3723> A_IWL<3722> A_IWL<3721> A_IWL<3720> A_IWL<3719> A_IWL<3718> A_IWL<3717> A_IWL<3716> A_IWL<3715> A_IWL<3714> A_IWL<3713> A_IWL<3712> A_IWL<3711> A_IWL<3710> A_IWL<3709> A_IWL<3708> A_IWL<3707> A_IWL<3706> A_IWL<3705> A_IWL<3704> A_IWL<3703> A_IWL<3702> A_IWL<3701> A_IWL<3700> A_IWL<3699> A_IWL<3698> A_IWL<3697> A_IWL<3696> A_IWL<3695> A_IWL<3694> A_IWL<3693> A_IWL<3692> A_IWL<3691> A_IWL<3690> A_IWL<3689> A_IWL<3688> A_IWL<3687> A_IWL<3686> A_IWL<3685> A_IWL<3684> A_IWL<3683> A_IWL<3682> A_IWL<3681> A_IWL<3680> A_IWL<3679> A_IWL<3678> A_IWL<3677> A_IWL<3676> A_IWL<3675> A_IWL<3674> A_IWL<3673> A_IWL<3672> A_IWL<3671> A_IWL<3670> A_IWL<3669> A_IWL<3668> A_IWL<3667> A_IWL<3666> A_IWL<3665> A_IWL<3664> A_IWL<3663> A_IWL<3662> A_IWL<3661> A_IWL<3660> A_IWL<3659> A_IWL<3658> A_IWL<3657> A_IWL<3656> A_IWL<3655> A_IWL<3654> A_IWL<3653> A_IWL<3652> A_IWL<3651> A_IWL<3650> A_IWL<3649> A_IWL<3648> A_IWL<3647> A_IWL<3646> A_IWL<3645> A_IWL<3644> A_IWL<3643> A_IWL<3642> A_IWL<3641> A_IWL<3640> A_IWL<3639> A_IWL<3638> A_IWL<3637> A_IWL<3636> A_IWL<3635> A_IWL<3634> A_IWL<3633> A_IWL<3632> A_IWL<3631> A_IWL<3630> A_IWL<3629> A_IWL<3628> A_IWL<3627> A_IWL<3626> A_IWL<3625> A_IWL<3624> A_IWL<3623> A_IWL<3622> A_IWL<3621> A_IWL<3620> A_IWL<3619> A_IWL<3618> A_IWL<3617> A_IWL<3616> A_IWL<3615> A_IWL<3614> A_IWL<3613> A_IWL<3612> A_IWL<3611> A_IWL<3610> A_IWL<3609> A_IWL<3608> A_IWL<3607> A_IWL<3606> A_IWL<3605> A_IWL<3604> A_IWL<3603> A_IWL<3602> A_IWL<3601> A_IWL<3600> A_IWL<3599> A_IWL<3598> A_IWL<3597> A_IWL<3596> A_IWL<3595> A_IWL<3594> A_IWL<3593> A_IWL<3592> A_IWL<3591> A_IWL<3590> A_IWL<3589> A_IWL<3588> A_IWL<3587> A_IWL<3586> A_IWL<3585> A_IWL<3584> VDD_CORE VSS / RM_IHPSG13_8192x32_c4_1P_COLUMN_pcell_0 +XCOL<6> A_BLC<13> A_BLC<12> A_BLC_TOP<13> A_BLC_TOP<12> A_BLT<13> A_BLT<12> A_BLT_TOP<13> A_BLT_TOP<12> A_IWL<3071> A_IWL<3070> A_IWL<3069> A_IWL<3068> A_IWL<3067> A_IWL<3066> A_IWL<3065> A_IWL<3064> A_IWL<3063> A_IWL<3062> A_IWL<3061> A_IWL<3060> A_IWL<3059> A_IWL<3058> A_IWL<3057> A_IWL<3056> A_IWL<3055> A_IWL<3054> A_IWL<3053> A_IWL<3052> A_IWL<3051> A_IWL<3050> A_IWL<3049> A_IWL<3048> A_IWL<3047> A_IWL<3046> A_IWL<3045> A_IWL<3044> A_IWL<3043> A_IWL<3042> A_IWL<3041> A_IWL<3040> A_IWL<3039> A_IWL<3038> A_IWL<3037> A_IWL<3036> A_IWL<3035> A_IWL<3034> A_IWL<3033> A_IWL<3032> A_IWL<3031> A_IWL<3030> A_IWL<3029> A_IWL<3028> A_IWL<3027> A_IWL<3026> A_IWL<3025> A_IWL<3024> A_IWL<3023> A_IWL<3022> A_IWL<3021> A_IWL<3020> A_IWL<3019> A_IWL<3018> A_IWL<3017> A_IWL<3016> A_IWL<3015> A_IWL<3014> A_IWL<3013> A_IWL<3012> A_IWL<3011> A_IWL<3010> A_IWL<3009> A_IWL<3008> A_IWL<3007> A_IWL<3006> A_IWL<3005> A_IWL<3004> A_IWL<3003> A_IWL<3002> A_IWL<3001> A_IWL<3000> A_IWL<2999> A_IWL<2998> A_IWL<2997> A_IWL<2996> A_IWL<2995> A_IWL<2994> A_IWL<2993> A_IWL<2992> A_IWL<2991> A_IWL<2990> A_IWL<2989> A_IWL<2988> A_IWL<2987> A_IWL<2986> A_IWL<2985> A_IWL<2984> A_IWL<2983> A_IWL<2982> A_IWL<2981> A_IWL<2980> A_IWL<2979> A_IWL<2978> A_IWL<2977> A_IWL<2976> A_IWL<2975> A_IWL<2974> A_IWL<2973> A_IWL<2972> A_IWL<2971> A_IWL<2970> A_IWL<2969> A_IWL<2968> A_IWL<2967> A_IWL<2966> A_IWL<2965> A_IWL<2964> A_IWL<2963> A_IWL<2962> A_IWL<2961> A_IWL<2960> A_IWL<2959> A_IWL<2958> A_IWL<2957> A_IWL<2956> A_IWL<2955> A_IWL<2954> A_IWL<2953> A_IWL<2952> A_IWL<2951> A_IWL<2950> A_IWL<2949> A_IWL<2948> A_IWL<2947> A_IWL<2946> A_IWL<2945> A_IWL<2944> A_IWL<2943> A_IWL<2942> A_IWL<2941> A_IWL<2940> A_IWL<2939> A_IWL<2938> A_IWL<2937> A_IWL<2936> A_IWL<2935> A_IWL<2934> A_IWL<2933> A_IWL<2932> A_IWL<2931> A_IWL<2930> A_IWL<2929> A_IWL<2928> A_IWL<2927> A_IWL<2926> A_IWL<2925> A_IWL<2924> A_IWL<2923> A_IWL<2922> A_IWL<2921> A_IWL<2920> A_IWL<2919> A_IWL<2918> A_IWL<2917> A_IWL<2916> A_IWL<2915> A_IWL<2914> A_IWL<2913> A_IWL<2912> A_IWL<2911> A_IWL<2910> A_IWL<2909> A_IWL<2908> A_IWL<2907> A_IWL<2906> A_IWL<2905> A_IWL<2904> A_IWL<2903> A_IWL<2902> A_IWL<2901> A_IWL<2900> A_IWL<2899> A_IWL<2898> A_IWL<2897> A_IWL<2896> A_IWL<2895> A_IWL<2894> A_IWL<2893> A_IWL<2892> A_IWL<2891> A_IWL<2890> A_IWL<2889> A_IWL<2888> A_IWL<2887> A_IWL<2886> A_IWL<2885> A_IWL<2884> A_IWL<2883> A_IWL<2882> A_IWL<2881> A_IWL<2880> A_IWL<2879> A_IWL<2878> A_IWL<2877> A_IWL<2876> A_IWL<2875> A_IWL<2874> A_IWL<2873> A_IWL<2872> A_IWL<2871> A_IWL<2870> A_IWL<2869> A_IWL<2868> A_IWL<2867> A_IWL<2866> A_IWL<2865> A_IWL<2864> A_IWL<2863> A_IWL<2862> A_IWL<2861> A_IWL<2860> A_IWL<2859> A_IWL<2858> A_IWL<2857> A_IWL<2856> A_IWL<2855> A_IWL<2854> A_IWL<2853> A_IWL<2852> A_IWL<2851> A_IWL<2850> A_IWL<2849> A_IWL<2848> A_IWL<2847> A_IWL<2846> A_IWL<2845> A_IWL<2844> A_IWL<2843> A_IWL<2842> A_IWL<2841> A_IWL<2840> A_IWL<2839> A_IWL<2838> A_IWL<2837> A_IWL<2836> A_IWL<2835> A_IWL<2834> A_IWL<2833> A_IWL<2832> A_IWL<2831> A_IWL<2830> A_IWL<2829> A_IWL<2828> A_IWL<2827> A_IWL<2826> A_IWL<2825> A_IWL<2824> A_IWL<2823> A_IWL<2822> A_IWL<2821> A_IWL<2820> A_IWL<2819> A_IWL<2818> A_IWL<2817> A_IWL<2816> A_IWL<2815> A_IWL<2814> A_IWL<2813> A_IWL<2812> A_IWL<2811> A_IWL<2810> A_IWL<2809> A_IWL<2808> A_IWL<2807> A_IWL<2806> A_IWL<2805> A_IWL<2804> A_IWL<2803> A_IWL<2802> A_IWL<2801> A_IWL<2800> A_IWL<2799> A_IWL<2798> A_IWL<2797> A_IWL<2796> A_IWL<2795> A_IWL<2794> A_IWL<2793> A_IWL<2792> A_IWL<2791> A_IWL<2790> A_IWL<2789> A_IWL<2788> A_IWL<2787> A_IWL<2786> A_IWL<2785> A_IWL<2784> A_IWL<2783> A_IWL<2782> A_IWL<2781> A_IWL<2780> A_IWL<2779> A_IWL<2778> A_IWL<2777> A_IWL<2776> A_IWL<2775> A_IWL<2774> A_IWL<2773> A_IWL<2772> A_IWL<2771> A_IWL<2770> A_IWL<2769> A_IWL<2768> A_IWL<2767> A_IWL<2766> A_IWL<2765> A_IWL<2764> A_IWL<2763> A_IWL<2762> A_IWL<2761> A_IWL<2760> A_IWL<2759> A_IWL<2758> A_IWL<2757> A_IWL<2756> A_IWL<2755> A_IWL<2754> A_IWL<2753> A_IWL<2752> A_IWL<2751> A_IWL<2750> A_IWL<2749> A_IWL<2748> A_IWL<2747> A_IWL<2746> A_IWL<2745> A_IWL<2744> A_IWL<2743> A_IWL<2742> A_IWL<2741> A_IWL<2740> A_IWL<2739> A_IWL<2738> A_IWL<2737> A_IWL<2736> A_IWL<2735> A_IWL<2734> A_IWL<2733> A_IWL<2732> A_IWL<2731> A_IWL<2730> A_IWL<2729> A_IWL<2728> A_IWL<2727> A_IWL<2726> A_IWL<2725> A_IWL<2724> A_IWL<2723> A_IWL<2722> A_IWL<2721> A_IWL<2720> A_IWL<2719> A_IWL<2718> A_IWL<2717> A_IWL<2716> A_IWL<2715> A_IWL<2714> A_IWL<2713> A_IWL<2712> A_IWL<2711> A_IWL<2710> A_IWL<2709> A_IWL<2708> A_IWL<2707> A_IWL<2706> A_IWL<2705> A_IWL<2704> A_IWL<2703> A_IWL<2702> A_IWL<2701> A_IWL<2700> A_IWL<2699> A_IWL<2698> A_IWL<2697> A_IWL<2696> A_IWL<2695> A_IWL<2694> A_IWL<2693> A_IWL<2692> A_IWL<2691> A_IWL<2690> A_IWL<2689> A_IWL<2688> A_IWL<2687> A_IWL<2686> A_IWL<2685> A_IWL<2684> A_IWL<2683> A_IWL<2682> A_IWL<2681> A_IWL<2680> A_IWL<2679> A_IWL<2678> A_IWL<2677> A_IWL<2676> A_IWL<2675> A_IWL<2674> A_IWL<2673> A_IWL<2672> A_IWL<2671> A_IWL<2670> A_IWL<2669> A_IWL<2668> A_IWL<2667> A_IWL<2666> A_IWL<2665> A_IWL<2664> A_IWL<2663> A_IWL<2662> A_IWL<2661> A_IWL<2660> A_IWL<2659> A_IWL<2658> A_IWL<2657> A_IWL<2656> A_IWL<2655> A_IWL<2654> A_IWL<2653> A_IWL<2652> A_IWL<2651> A_IWL<2650> A_IWL<2649> A_IWL<2648> A_IWL<2647> A_IWL<2646> A_IWL<2645> A_IWL<2644> A_IWL<2643> A_IWL<2642> A_IWL<2641> A_IWL<2640> A_IWL<2639> A_IWL<2638> A_IWL<2637> A_IWL<2636> A_IWL<2635> A_IWL<2634> A_IWL<2633> A_IWL<2632> A_IWL<2631> A_IWL<2630> A_IWL<2629> A_IWL<2628> A_IWL<2627> A_IWL<2626> A_IWL<2625> A_IWL<2624> A_IWL<2623> A_IWL<2622> A_IWL<2621> A_IWL<2620> A_IWL<2619> A_IWL<2618> A_IWL<2617> A_IWL<2616> A_IWL<2615> A_IWL<2614> A_IWL<2613> A_IWL<2612> A_IWL<2611> A_IWL<2610> A_IWL<2609> A_IWL<2608> A_IWL<2607> A_IWL<2606> A_IWL<2605> A_IWL<2604> A_IWL<2603> A_IWL<2602> A_IWL<2601> A_IWL<2600> A_IWL<2599> A_IWL<2598> A_IWL<2597> A_IWL<2596> A_IWL<2595> A_IWL<2594> A_IWL<2593> A_IWL<2592> A_IWL<2591> A_IWL<2590> A_IWL<2589> A_IWL<2588> A_IWL<2587> A_IWL<2586> A_IWL<2585> A_IWL<2584> A_IWL<2583> A_IWL<2582> A_IWL<2581> A_IWL<2580> A_IWL<2579> A_IWL<2578> A_IWL<2577> A_IWL<2576> A_IWL<2575> A_IWL<2574> A_IWL<2573> A_IWL<2572> A_IWL<2571> A_IWL<2570> A_IWL<2569> A_IWL<2568> A_IWL<2567> A_IWL<2566> A_IWL<2565> A_IWL<2564> A_IWL<2563> A_IWL<2562> A_IWL<2561> A_IWL<2560> A_IWL<3583> A_IWL<3582> A_IWL<3581> A_IWL<3580> A_IWL<3579> A_IWL<3578> A_IWL<3577> A_IWL<3576> A_IWL<3575> A_IWL<3574> A_IWL<3573> A_IWL<3572> A_IWL<3571> A_IWL<3570> A_IWL<3569> A_IWL<3568> A_IWL<3567> A_IWL<3566> A_IWL<3565> A_IWL<3564> A_IWL<3563> A_IWL<3562> A_IWL<3561> A_IWL<3560> A_IWL<3559> A_IWL<3558> A_IWL<3557> A_IWL<3556> A_IWL<3555> A_IWL<3554> A_IWL<3553> A_IWL<3552> A_IWL<3551> A_IWL<3550> A_IWL<3549> A_IWL<3548> A_IWL<3547> A_IWL<3546> A_IWL<3545> A_IWL<3544> A_IWL<3543> A_IWL<3542> A_IWL<3541> A_IWL<3540> A_IWL<3539> A_IWL<3538> A_IWL<3537> A_IWL<3536> A_IWL<3535> A_IWL<3534> A_IWL<3533> A_IWL<3532> A_IWL<3531> A_IWL<3530> A_IWL<3529> A_IWL<3528> A_IWL<3527> A_IWL<3526> A_IWL<3525> A_IWL<3524> A_IWL<3523> A_IWL<3522> A_IWL<3521> A_IWL<3520> A_IWL<3519> A_IWL<3518> A_IWL<3517> A_IWL<3516> A_IWL<3515> A_IWL<3514> A_IWL<3513> A_IWL<3512> A_IWL<3511> A_IWL<3510> A_IWL<3509> A_IWL<3508> A_IWL<3507> A_IWL<3506> A_IWL<3505> A_IWL<3504> A_IWL<3503> A_IWL<3502> A_IWL<3501> A_IWL<3500> A_IWL<3499> A_IWL<3498> A_IWL<3497> A_IWL<3496> A_IWL<3495> A_IWL<3494> A_IWL<3493> A_IWL<3492> A_IWL<3491> A_IWL<3490> A_IWL<3489> A_IWL<3488> A_IWL<3487> A_IWL<3486> A_IWL<3485> A_IWL<3484> A_IWL<3483> A_IWL<3482> A_IWL<3481> A_IWL<3480> A_IWL<3479> A_IWL<3478> A_IWL<3477> A_IWL<3476> A_IWL<3475> A_IWL<3474> A_IWL<3473> A_IWL<3472> A_IWL<3471> A_IWL<3470> A_IWL<3469> A_IWL<3468> A_IWL<3467> A_IWL<3466> A_IWL<3465> A_IWL<3464> A_IWL<3463> A_IWL<3462> A_IWL<3461> A_IWL<3460> A_IWL<3459> A_IWL<3458> A_IWL<3457> A_IWL<3456> A_IWL<3455> A_IWL<3454> A_IWL<3453> A_IWL<3452> A_IWL<3451> A_IWL<3450> A_IWL<3449> A_IWL<3448> A_IWL<3447> A_IWL<3446> A_IWL<3445> A_IWL<3444> A_IWL<3443> A_IWL<3442> A_IWL<3441> A_IWL<3440> A_IWL<3439> A_IWL<3438> A_IWL<3437> A_IWL<3436> A_IWL<3435> A_IWL<3434> A_IWL<3433> A_IWL<3432> A_IWL<3431> A_IWL<3430> A_IWL<3429> A_IWL<3428> A_IWL<3427> A_IWL<3426> A_IWL<3425> A_IWL<3424> A_IWL<3423> A_IWL<3422> A_IWL<3421> A_IWL<3420> A_IWL<3419> A_IWL<3418> A_IWL<3417> A_IWL<3416> A_IWL<3415> A_IWL<3414> A_IWL<3413> A_IWL<3412> A_IWL<3411> A_IWL<3410> A_IWL<3409> A_IWL<3408> A_IWL<3407> A_IWL<3406> A_IWL<3405> A_IWL<3404> A_IWL<3403> A_IWL<3402> A_IWL<3401> A_IWL<3400> A_IWL<3399> A_IWL<3398> A_IWL<3397> A_IWL<3396> A_IWL<3395> A_IWL<3394> A_IWL<3393> A_IWL<3392> A_IWL<3391> A_IWL<3390> A_IWL<3389> A_IWL<3388> A_IWL<3387> A_IWL<3386> A_IWL<3385> A_IWL<3384> A_IWL<3383> A_IWL<3382> A_IWL<3381> A_IWL<3380> A_IWL<3379> A_IWL<3378> A_IWL<3377> A_IWL<3376> A_IWL<3375> A_IWL<3374> A_IWL<3373> A_IWL<3372> A_IWL<3371> A_IWL<3370> A_IWL<3369> A_IWL<3368> A_IWL<3367> A_IWL<3366> A_IWL<3365> A_IWL<3364> A_IWL<3363> A_IWL<3362> A_IWL<3361> A_IWL<3360> A_IWL<3359> A_IWL<3358> A_IWL<3357> A_IWL<3356> A_IWL<3355> A_IWL<3354> A_IWL<3353> A_IWL<3352> A_IWL<3351> A_IWL<3350> A_IWL<3349> A_IWL<3348> A_IWL<3347> A_IWL<3346> A_IWL<3345> A_IWL<3344> A_IWL<3343> A_IWL<3342> A_IWL<3341> A_IWL<3340> A_IWL<3339> A_IWL<3338> A_IWL<3337> A_IWL<3336> A_IWL<3335> A_IWL<3334> A_IWL<3333> A_IWL<3332> A_IWL<3331> A_IWL<3330> A_IWL<3329> A_IWL<3328> A_IWL<3327> A_IWL<3326> A_IWL<3325> A_IWL<3324> A_IWL<3323> A_IWL<3322> A_IWL<3321> A_IWL<3320> A_IWL<3319> A_IWL<3318> A_IWL<3317> A_IWL<3316> A_IWL<3315> A_IWL<3314> A_IWL<3313> A_IWL<3312> A_IWL<3311> A_IWL<3310> A_IWL<3309> A_IWL<3308> A_IWL<3307> A_IWL<3306> A_IWL<3305> A_IWL<3304> A_IWL<3303> A_IWL<3302> A_IWL<3301> A_IWL<3300> A_IWL<3299> A_IWL<3298> A_IWL<3297> A_IWL<3296> A_IWL<3295> A_IWL<3294> A_IWL<3293> A_IWL<3292> A_IWL<3291> A_IWL<3290> A_IWL<3289> A_IWL<3288> A_IWL<3287> A_IWL<3286> A_IWL<3285> A_IWL<3284> A_IWL<3283> A_IWL<3282> A_IWL<3281> A_IWL<3280> A_IWL<3279> A_IWL<3278> A_IWL<3277> A_IWL<3276> A_IWL<3275> A_IWL<3274> A_IWL<3273> A_IWL<3272> A_IWL<3271> A_IWL<3270> A_IWL<3269> A_IWL<3268> A_IWL<3267> A_IWL<3266> A_IWL<3265> A_IWL<3264> A_IWL<3263> A_IWL<3262> A_IWL<3261> A_IWL<3260> A_IWL<3259> A_IWL<3258> A_IWL<3257> A_IWL<3256> A_IWL<3255> A_IWL<3254> A_IWL<3253> A_IWL<3252> A_IWL<3251> A_IWL<3250> A_IWL<3249> A_IWL<3248> A_IWL<3247> A_IWL<3246> A_IWL<3245> A_IWL<3244> A_IWL<3243> A_IWL<3242> A_IWL<3241> A_IWL<3240> A_IWL<3239> A_IWL<3238> A_IWL<3237> A_IWL<3236> A_IWL<3235> A_IWL<3234> A_IWL<3233> A_IWL<3232> A_IWL<3231> A_IWL<3230> A_IWL<3229> A_IWL<3228> A_IWL<3227> A_IWL<3226> A_IWL<3225> A_IWL<3224> A_IWL<3223> A_IWL<3222> A_IWL<3221> A_IWL<3220> A_IWL<3219> A_IWL<3218> A_IWL<3217> A_IWL<3216> A_IWL<3215> A_IWL<3214> A_IWL<3213> A_IWL<3212> A_IWL<3211> A_IWL<3210> A_IWL<3209> A_IWL<3208> A_IWL<3207> A_IWL<3206> A_IWL<3205> A_IWL<3204> A_IWL<3203> A_IWL<3202> A_IWL<3201> A_IWL<3200> A_IWL<3199> A_IWL<3198> A_IWL<3197> A_IWL<3196> A_IWL<3195> A_IWL<3194> A_IWL<3193> A_IWL<3192> A_IWL<3191> A_IWL<3190> A_IWL<3189> A_IWL<3188> A_IWL<3187> A_IWL<3186> A_IWL<3185> A_IWL<3184> A_IWL<3183> A_IWL<3182> A_IWL<3181> A_IWL<3180> A_IWL<3179> A_IWL<3178> A_IWL<3177> A_IWL<3176> A_IWL<3175> A_IWL<3174> A_IWL<3173> A_IWL<3172> A_IWL<3171> A_IWL<3170> A_IWL<3169> A_IWL<3168> A_IWL<3167> A_IWL<3166> A_IWL<3165> A_IWL<3164> A_IWL<3163> A_IWL<3162> A_IWL<3161> A_IWL<3160> A_IWL<3159> A_IWL<3158> A_IWL<3157> A_IWL<3156> A_IWL<3155> A_IWL<3154> A_IWL<3153> A_IWL<3152> A_IWL<3151> A_IWL<3150> A_IWL<3149> A_IWL<3148> A_IWL<3147> A_IWL<3146> A_IWL<3145> A_IWL<3144> A_IWL<3143> A_IWL<3142> A_IWL<3141> A_IWL<3140> A_IWL<3139> A_IWL<3138> A_IWL<3137> A_IWL<3136> A_IWL<3135> A_IWL<3134> A_IWL<3133> A_IWL<3132> A_IWL<3131> A_IWL<3130> A_IWL<3129> A_IWL<3128> A_IWL<3127> A_IWL<3126> A_IWL<3125> A_IWL<3124> A_IWL<3123> A_IWL<3122> A_IWL<3121> A_IWL<3120> A_IWL<3119> A_IWL<3118> A_IWL<3117> A_IWL<3116> A_IWL<3115> A_IWL<3114> A_IWL<3113> A_IWL<3112> A_IWL<3111> A_IWL<3110> A_IWL<3109> A_IWL<3108> A_IWL<3107> A_IWL<3106> A_IWL<3105> A_IWL<3104> A_IWL<3103> A_IWL<3102> A_IWL<3101> A_IWL<3100> A_IWL<3099> A_IWL<3098> A_IWL<3097> A_IWL<3096> A_IWL<3095> A_IWL<3094> A_IWL<3093> A_IWL<3092> A_IWL<3091> A_IWL<3090> A_IWL<3089> A_IWL<3088> A_IWL<3087> A_IWL<3086> A_IWL<3085> A_IWL<3084> A_IWL<3083> A_IWL<3082> A_IWL<3081> A_IWL<3080> A_IWL<3079> A_IWL<3078> A_IWL<3077> A_IWL<3076> A_IWL<3075> A_IWL<3074> A_IWL<3073> A_IWL<3072> VDD_CORE VSS / RM_IHPSG13_8192x32_c4_1P_COLUMN_pcell_0 +XCOL<5> A_BLC<11> A_BLC<10> A_BLC_TOP<11> A_BLC_TOP<10> A_BLT<11> A_BLT<10> A_BLT_TOP<11> A_BLT_TOP<10> A_IWL<2559> A_IWL<2558> A_IWL<2557> A_IWL<2556> A_IWL<2555> A_IWL<2554> A_IWL<2553> A_IWL<2552> A_IWL<2551> A_IWL<2550> A_IWL<2549> A_IWL<2548> A_IWL<2547> A_IWL<2546> A_IWL<2545> A_IWL<2544> A_IWL<2543> A_IWL<2542> A_IWL<2541> A_IWL<2540> A_IWL<2539> A_IWL<2538> A_IWL<2537> A_IWL<2536> A_IWL<2535> A_IWL<2534> A_IWL<2533> A_IWL<2532> A_IWL<2531> A_IWL<2530> A_IWL<2529> A_IWL<2528> A_IWL<2527> A_IWL<2526> A_IWL<2525> A_IWL<2524> A_IWL<2523> A_IWL<2522> A_IWL<2521> A_IWL<2520> A_IWL<2519> A_IWL<2518> A_IWL<2517> A_IWL<2516> A_IWL<2515> A_IWL<2514> A_IWL<2513> A_IWL<2512> A_IWL<2511> A_IWL<2510> A_IWL<2509> A_IWL<2508> A_IWL<2507> A_IWL<2506> A_IWL<2505> A_IWL<2504> A_IWL<2503> A_IWL<2502> A_IWL<2501> A_IWL<2500> A_IWL<2499> A_IWL<2498> A_IWL<2497> A_IWL<2496> A_IWL<2495> A_IWL<2494> A_IWL<2493> A_IWL<2492> A_IWL<2491> A_IWL<2490> A_IWL<2489> A_IWL<2488> A_IWL<2487> A_IWL<2486> A_IWL<2485> A_IWL<2484> A_IWL<2483> A_IWL<2482> A_IWL<2481> A_IWL<2480> A_IWL<2479> A_IWL<2478> A_IWL<2477> A_IWL<2476> A_IWL<2475> A_IWL<2474> A_IWL<2473> A_IWL<2472> A_IWL<2471> A_IWL<2470> A_IWL<2469> A_IWL<2468> A_IWL<2467> A_IWL<2466> A_IWL<2465> A_IWL<2464> A_IWL<2463> A_IWL<2462> A_IWL<2461> A_IWL<2460> A_IWL<2459> A_IWL<2458> A_IWL<2457> A_IWL<2456> A_IWL<2455> A_IWL<2454> A_IWL<2453> A_IWL<2452> A_IWL<2451> A_IWL<2450> A_IWL<2449> A_IWL<2448> A_IWL<2447> A_IWL<2446> A_IWL<2445> A_IWL<2444> A_IWL<2443> A_IWL<2442> A_IWL<2441> A_IWL<2440> A_IWL<2439> A_IWL<2438> A_IWL<2437> A_IWL<2436> A_IWL<2435> A_IWL<2434> A_IWL<2433> A_IWL<2432> A_IWL<2431> A_IWL<2430> A_IWL<2429> A_IWL<2428> A_IWL<2427> A_IWL<2426> A_IWL<2425> A_IWL<2424> A_IWL<2423> A_IWL<2422> A_IWL<2421> A_IWL<2420> A_IWL<2419> A_IWL<2418> A_IWL<2417> A_IWL<2416> A_IWL<2415> A_IWL<2414> A_IWL<2413> A_IWL<2412> A_IWL<2411> A_IWL<2410> A_IWL<2409> A_IWL<2408> A_IWL<2407> A_IWL<2406> A_IWL<2405> A_IWL<2404> A_IWL<2403> A_IWL<2402> A_IWL<2401> A_IWL<2400> A_IWL<2399> A_IWL<2398> A_IWL<2397> A_IWL<2396> A_IWL<2395> A_IWL<2394> A_IWL<2393> A_IWL<2392> A_IWL<2391> A_IWL<2390> A_IWL<2389> A_IWL<2388> A_IWL<2387> A_IWL<2386> A_IWL<2385> A_IWL<2384> A_IWL<2383> A_IWL<2382> A_IWL<2381> A_IWL<2380> A_IWL<2379> A_IWL<2378> A_IWL<2377> A_IWL<2376> A_IWL<2375> A_IWL<2374> A_IWL<2373> A_IWL<2372> A_IWL<2371> A_IWL<2370> A_IWL<2369> A_IWL<2368> A_IWL<2367> A_IWL<2366> A_IWL<2365> A_IWL<2364> A_IWL<2363> A_IWL<2362> A_IWL<2361> A_IWL<2360> A_IWL<2359> A_IWL<2358> A_IWL<2357> A_IWL<2356> A_IWL<2355> A_IWL<2354> A_IWL<2353> A_IWL<2352> A_IWL<2351> A_IWL<2350> A_IWL<2349> A_IWL<2348> A_IWL<2347> A_IWL<2346> A_IWL<2345> A_IWL<2344> A_IWL<2343> A_IWL<2342> A_IWL<2341> A_IWL<2340> A_IWL<2339> A_IWL<2338> A_IWL<2337> A_IWL<2336> A_IWL<2335> A_IWL<2334> A_IWL<2333> A_IWL<2332> A_IWL<2331> A_IWL<2330> A_IWL<2329> A_IWL<2328> A_IWL<2327> A_IWL<2326> A_IWL<2325> A_IWL<2324> A_IWL<2323> A_IWL<2322> A_IWL<2321> A_IWL<2320> A_IWL<2319> A_IWL<2318> A_IWL<2317> A_IWL<2316> A_IWL<2315> A_IWL<2314> A_IWL<2313> A_IWL<2312> A_IWL<2311> A_IWL<2310> A_IWL<2309> A_IWL<2308> A_IWL<2307> A_IWL<2306> A_IWL<2305> A_IWL<2304> A_IWL<2303> A_IWL<2302> A_IWL<2301> A_IWL<2300> A_IWL<2299> A_IWL<2298> A_IWL<2297> A_IWL<2296> A_IWL<2295> A_IWL<2294> A_IWL<2293> A_IWL<2292> A_IWL<2291> A_IWL<2290> A_IWL<2289> A_IWL<2288> A_IWL<2287> A_IWL<2286> A_IWL<2285> A_IWL<2284> A_IWL<2283> A_IWL<2282> A_IWL<2281> A_IWL<2280> A_IWL<2279> A_IWL<2278> A_IWL<2277> A_IWL<2276> A_IWL<2275> A_IWL<2274> A_IWL<2273> A_IWL<2272> A_IWL<2271> A_IWL<2270> A_IWL<2269> A_IWL<2268> A_IWL<2267> A_IWL<2266> A_IWL<2265> A_IWL<2264> A_IWL<2263> A_IWL<2262> A_IWL<2261> A_IWL<2260> A_IWL<2259> A_IWL<2258> A_IWL<2257> A_IWL<2256> A_IWL<2255> A_IWL<2254> A_IWL<2253> A_IWL<2252> A_IWL<2251> A_IWL<2250> A_IWL<2249> A_IWL<2248> A_IWL<2247> A_IWL<2246> A_IWL<2245> A_IWL<2244> A_IWL<2243> A_IWL<2242> A_IWL<2241> A_IWL<2240> A_IWL<2239> A_IWL<2238> A_IWL<2237> A_IWL<2236> A_IWL<2235> A_IWL<2234> A_IWL<2233> A_IWL<2232> A_IWL<2231> A_IWL<2230> A_IWL<2229> A_IWL<2228> A_IWL<2227> A_IWL<2226> A_IWL<2225> A_IWL<2224> A_IWL<2223> A_IWL<2222> A_IWL<2221> A_IWL<2220> A_IWL<2219> A_IWL<2218> A_IWL<2217> A_IWL<2216> A_IWL<2215> A_IWL<2214> A_IWL<2213> A_IWL<2212> A_IWL<2211> A_IWL<2210> A_IWL<2209> A_IWL<2208> A_IWL<2207> A_IWL<2206> A_IWL<2205> A_IWL<2204> A_IWL<2203> A_IWL<2202> A_IWL<2201> A_IWL<2200> A_IWL<2199> A_IWL<2198> A_IWL<2197> A_IWL<2196> A_IWL<2195> A_IWL<2194> A_IWL<2193> A_IWL<2192> A_IWL<2191> A_IWL<2190> A_IWL<2189> A_IWL<2188> A_IWL<2187> A_IWL<2186> A_IWL<2185> A_IWL<2184> A_IWL<2183> A_IWL<2182> A_IWL<2181> A_IWL<2180> A_IWL<2179> A_IWL<2178> A_IWL<2177> A_IWL<2176> A_IWL<2175> A_IWL<2174> A_IWL<2173> A_IWL<2172> A_IWL<2171> A_IWL<2170> A_IWL<2169> A_IWL<2168> A_IWL<2167> A_IWL<2166> A_IWL<2165> A_IWL<2164> A_IWL<2163> A_IWL<2162> A_IWL<2161> A_IWL<2160> A_IWL<2159> A_IWL<2158> A_IWL<2157> A_IWL<2156> A_IWL<2155> A_IWL<2154> A_IWL<2153> A_IWL<2152> A_IWL<2151> A_IWL<2150> A_IWL<2149> A_IWL<2148> A_IWL<2147> A_IWL<2146> A_IWL<2145> A_IWL<2144> A_IWL<2143> A_IWL<2142> A_IWL<2141> A_IWL<2140> A_IWL<2139> A_IWL<2138> A_IWL<2137> A_IWL<2136> A_IWL<2135> A_IWL<2134> A_IWL<2133> A_IWL<2132> A_IWL<2131> A_IWL<2130> A_IWL<2129> A_IWL<2128> A_IWL<2127> A_IWL<2126> A_IWL<2125> A_IWL<2124> A_IWL<2123> A_IWL<2122> A_IWL<2121> A_IWL<2120> A_IWL<2119> A_IWL<2118> A_IWL<2117> A_IWL<2116> A_IWL<2115> A_IWL<2114> A_IWL<2113> A_IWL<2112> A_IWL<2111> A_IWL<2110> A_IWL<2109> A_IWL<2108> A_IWL<2107> A_IWL<2106> A_IWL<2105> A_IWL<2104> A_IWL<2103> A_IWL<2102> A_IWL<2101> A_IWL<2100> A_IWL<2099> A_IWL<2098> A_IWL<2097> A_IWL<2096> A_IWL<2095> A_IWL<2094> A_IWL<2093> A_IWL<2092> A_IWL<2091> A_IWL<2090> A_IWL<2089> A_IWL<2088> A_IWL<2087> A_IWL<2086> A_IWL<2085> A_IWL<2084> A_IWL<2083> A_IWL<2082> A_IWL<2081> A_IWL<2080> A_IWL<2079> A_IWL<2078> A_IWL<2077> A_IWL<2076> A_IWL<2075> A_IWL<2074> A_IWL<2073> A_IWL<2072> A_IWL<2071> A_IWL<2070> A_IWL<2069> A_IWL<2068> A_IWL<2067> A_IWL<2066> A_IWL<2065> A_IWL<2064> A_IWL<2063> A_IWL<2062> A_IWL<2061> A_IWL<2060> A_IWL<2059> A_IWL<2058> A_IWL<2057> A_IWL<2056> A_IWL<2055> A_IWL<2054> A_IWL<2053> A_IWL<2052> A_IWL<2051> A_IWL<2050> A_IWL<2049> A_IWL<2048> A_IWL<3071> A_IWL<3070> A_IWL<3069> A_IWL<3068> A_IWL<3067> A_IWL<3066> A_IWL<3065> A_IWL<3064> A_IWL<3063> A_IWL<3062> A_IWL<3061> A_IWL<3060> A_IWL<3059> A_IWL<3058> A_IWL<3057> A_IWL<3056> A_IWL<3055> A_IWL<3054> A_IWL<3053> A_IWL<3052> A_IWL<3051> A_IWL<3050> A_IWL<3049> A_IWL<3048> A_IWL<3047> A_IWL<3046> A_IWL<3045> A_IWL<3044> A_IWL<3043> A_IWL<3042> A_IWL<3041> A_IWL<3040> A_IWL<3039> A_IWL<3038> A_IWL<3037> A_IWL<3036> A_IWL<3035> A_IWL<3034> A_IWL<3033> A_IWL<3032> A_IWL<3031> A_IWL<3030> A_IWL<3029> A_IWL<3028> A_IWL<3027> A_IWL<3026> A_IWL<3025> A_IWL<3024> A_IWL<3023> A_IWL<3022> A_IWL<3021> A_IWL<3020> A_IWL<3019> A_IWL<3018> A_IWL<3017> A_IWL<3016> A_IWL<3015> A_IWL<3014> A_IWL<3013> A_IWL<3012> A_IWL<3011> A_IWL<3010> A_IWL<3009> A_IWL<3008> A_IWL<3007> A_IWL<3006> A_IWL<3005> A_IWL<3004> A_IWL<3003> A_IWL<3002> A_IWL<3001> A_IWL<3000> A_IWL<2999> A_IWL<2998> A_IWL<2997> A_IWL<2996> A_IWL<2995> A_IWL<2994> A_IWL<2993> A_IWL<2992> A_IWL<2991> A_IWL<2990> A_IWL<2989> A_IWL<2988> A_IWL<2987> A_IWL<2986> A_IWL<2985> A_IWL<2984> A_IWL<2983> A_IWL<2982> A_IWL<2981> A_IWL<2980> A_IWL<2979> A_IWL<2978> A_IWL<2977> A_IWL<2976> A_IWL<2975> A_IWL<2974> A_IWL<2973> A_IWL<2972> A_IWL<2971> A_IWL<2970> A_IWL<2969> A_IWL<2968> A_IWL<2967> A_IWL<2966> A_IWL<2965> A_IWL<2964> A_IWL<2963> A_IWL<2962> A_IWL<2961> A_IWL<2960> A_IWL<2959> A_IWL<2958> A_IWL<2957> A_IWL<2956> A_IWL<2955> A_IWL<2954> A_IWL<2953> A_IWL<2952> A_IWL<2951> A_IWL<2950> A_IWL<2949> A_IWL<2948> A_IWL<2947> A_IWL<2946> A_IWL<2945> A_IWL<2944> A_IWL<2943> A_IWL<2942> A_IWL<2941> A_IWL<2940> A_IWL<2939> A_IWL<2938> A_IWL<2937> A_IWL<2936> A_IWL<2935> A_IWL<2934> A_IWL<2933> A_IWL<2932> A_IWL<2931> A_IWL<2930> A_IWL<2929> A_IWL<2928> A_IWL<2927> A_IWL<2926> A_IWL<2925> A_IWL<2924> A_IWL<2923> A_IWL<2922> A_IWL<2921> A_IWL<2920> A_IWL<2919> A_IWL<2918> A_IWL<2917> A_IWL<2916> A_IWL<2915> A_IWL<2914> A_IWL<2913> A_IWL<2912> A_IWL<2911> A_IWL<2910> A_IWL<2909> A_IWL<2908> A_IWL<2907> A_IWL<2906> A_IWL<2905> A_IWL<2904> A_IWL<2903> A_IWL<2902> A_IWL<2901> A_IWL<2900> A_IWL<2899> A_IWL<2898> A_IWL<2897> A_IWL<2896> A_IWL<2895> A_IWL<2894> A_IWL<2893> A_IWL<2892> A_IWL<2891> A_IWL<2890> A_IWL<2889> A_IWL<2888> A_IWL<2887> A_IWL<2886> A_IWL<2885> A_IWL<2884> A_IWL<2883> A_IWL<2882> A_IWL<2881> A_IWL<2880> A_IWL<2879> A_IWL<2878> A_IWL<2877> A_IWL<2876> A_IWL<2875> A_IWL<2874> A_IWL<2873> A_IWL<2872> A_IWL<2871> A_IWL<2870> A_IWL<2869> A_IWL<2868> A_IWL<2867> A_IWL<2866> A_IWL<2865> A_IWL<2864> A_IWL<2863> A_IWL<2862> A_IWL<2861> A_IWL<2860> A_IWL<2859> A_IWL<2858> A_IWL<2857> A_IWL<2856> A_IWL<2855> A_IWL<2854> A_IWL<2853> A_IWL<2852> A_IWL<2851> A_IWL<2850> A_IWL<2849> A_IWL<2848> A_IWL<2847> A_IWL<2846> A_IWL<2845> A_IWL<2844> A_IWL<2843> A_IWL<2842> A_IWL<2841> A_IWL<2840> A_IWL<2839> A_IWL<2838> A_IWL<2837> A_IWL<2836> A_IWL<2835> A_IWL<2834> A_IWL<2833> A_IWL<2832> A_IWL<2831> A_IWL<2830> A_IWL<2829> A_IWL<2828> A_IWL<2827> A_IWL<2826> A_IWL<2825> A_IWL<2824> A_IWL<2823> A_IWL<2822> A_IWL<2821> A_IWL<2820> A_IWL<2819> A_IWL<2818> A_IWL<2817> A_IWL<2816> A_IWL<2815> A_IWL<2814> A_IWL<2813> A_IWL<2812> A_IWL<2811> A_IWL<2810> A_IWL<2809> A_IWL<2808> A_IWL<2807> A_IWL<2806> A_IWL<2805> A_IWL<2804> A_IWL<2803> A_IWL<2802> A_IWL<2801> A_IWL<2800> A_IWL<2799> A_IWL<2798> A_IWL<2797> A_IWL<2796> A_IWL<2795> A_IWL<2794> A_IWL<2793> A_IWL<2792> A_IWL<2791> A_IWL<2790> A_IWL<2789> A_IWL<2788> A_IWL<2787> A_IWL<2786> A_IWL<2785> A_IWL<2784> A_IWL<2783> A_IWL<2782> A_IWL<2781> A_IWL<2780> A_IWL<2779> A_IWL<2778> A_IWL<2777> A_IWL<2776> A_IWL<2775> A_IWL<2774> A_IWL<2773> A_IWL<2772> A_IWL<2771> A_IWL<2770> A_IWL<2769> A_IWL<2768> A_IWL<2767> A_IWL<2766> A_IWL<2765> A_IWL<2764> A_IWL<2763> A_IWL<2762> A_IWL<2761> A_IWL<2760> A_IWL<2759> A_IWL<2758> A_IWL<2757> A_IWL<2756> A_IWL<2755> A_IWL<2754> A_IWL<2753> A_IWL<2752> A_IWL<2751> A_IWL<2750> A_IWL<2749> A_IWL<2748> A_IWL<2747> A_IWL<2746> A_IWL<2745> A_IWL<2744> A_IWL<2743> A_IWL<2742> A_IWL<2741> A_IWL<2740> A_IWL<2739> A_IWL<2738> A_IWL<2737> A_IWL<2736> A_IWL<2735> A_IWL<2734> A_IWL<2733> A_IWL<2732> A_IWL<2731> A_IWL<2730> A_IWL<2729> A_IWL<2728> A_IWL<2727> A_IWL<2726> A_IWL<2725> A_IWL<2724> A_IWL<2723> A_IWL<2722> A_IWL<2721> A_IWL<2720> A_IWL<2719> A_IWL<2718> A_IWL<2717> A_IWL<2716> A_IWL<2715> A_IWL<2714> A_IWL<2713> A_IWL<2712> A_IWL<2711> A_IWL<2710> A_IWL<2709> A_IWL<2708> A_IWL<2707> A_IWL<2706> A_IWL<2705> A_IWL<2704> A_IWL<2703> A_IWL<2702> A_IWL<2701> A_IWL<2700> A_IWL<2699> A_IWL<2698> A_IWL<2697> A_IWL<2696> A_IWL<2695> A_IWL<2694> A_IWL<2693> A_IWL<2692> A_IWL<2691> A_IWL<2690> A_IWL<2689> A_IWL<2688> A_IWL<2687> A_IWL<2686> A_IWL<2685> A_IWL<2684> A_IWL<2683> A_IWL<2682> A_IWL<2681> A_IWL<2680> A_IWL<2679> A_IWL<2678> A_IWL<2677> A_IWL<2676> A_IWL<2675> A_IWL<2674> A_IWL<2673> A_IWL<2672> A_IWL<2671> A_IWL<2670> A_IWL<2669> A_IWL<2668> A_IWL<2667> A_IWL<2666> A_IWL<2665> A_IWL<2664> A_IWL<2663> A_IWL<2662> A_IWL<2661> A_IWL<2660> A_IWL<2659> A_IWL<2658> A_IWL<2657> A_IWL<2656> A_IWL<2655> A_IWL<2654> A_IWL<2653> A_IWL<2652> A_IWL<2651> A_IWL<2650> A_IWL<2649> A_IWL<2648> A_IWL<2647> A_IWL<2646> A_IWL<2645> A_IWL<2644> A_IWL<2643> A_IWL<2642> A_IWL<2641> A_IWL<2640> A_IWL<2639> A_IWL<2638> A_IWL<2637> A_IWL<2636> A_IWL<2635> A_IWL<2634> A_IWL<2633> A_IWL<2632> A_IWL<2631> A_IWL<2630> A_IWL<2629> A_IWL<2628> A_IWL<2627> A_IWL<2626> A_IWL<2625> A_IWL<2624> A_IWL<2623> A_IWL<2622> A_IWL<2621> A_IWL<2620> A_IWL<2619> A_IWL<2618> A_IWL<2617> A_IWL<2616> A_IWL<2615> A_IWL<2614> A_IWL<2613> A_IWL<2612> A_IWL<2611> A_IWL<2610> A_IWL<2609> A_IWL<2608> A_IWL<2607> A_IWL<2606> A_IWL<2605> A_IWL<2604> A_IWL<2603> A_IWL<2602> A_IWL<2601> A_IWL<2600> A_IWL<2599> A_IWL<2598> A_IWL<2597> A_IWL<2596> A_IWL<2595> A_IWL<2594> A_IWL<2593> A_IWL<2592> A_IWL<2591> A_IWL<2590> A_IWL<2589> A_IWL<2588> A_IWL<2587> A_IWL<2586> A_IWL<2585> A_IWL<2584> A_IWL<2583> A_IWL<2582> A_IWL<2581> A_IWL<2580> A_IWL<2579> A_IWL<2578> A_IWL<2577> A_IWL<2576> A_IWL<2575> A_IWL<2574> A_IWL<2573> A_IWL<2572> A_IWL<2571> A_IWL<2570> A_IWL<2569> A_IWL<2568> A_IWL<2567> A_IWL<2566> A_IWL<2565> A_IWL<2564> A_IWL<2563> A_IWL<2562> A_IWL<2561> A_IWL<2560> VDD_CORE VSS / RM_IHPSG13_8192x32_c4_1P_COLUMN_pcell_0 +XCOL<4> A_BLC<9> A_BLC<8> A_BLC_TOP<9> A_BLC_TOP<8> A_BLT<9> A_BLT<8> A_BLT_TOP<9> A_BLT_TOP<8> A_IWL<2047> A_IWL<2046> A_IWL<2045> A_IWL<2044> A_IWL<2043> A_IWL<2042> A_IWL<2041> A_IWL<2040> A_IWL<2039> A_IWL<2038> A_IWL<2037> A_IWL<2036> A_IWL<2035> A_IWL<2034> A_IWL<2033> A_IWL<2032> A_IWL<2031> A_IWL<2030> A_IWL<2029> A_IWL<2028> A_IWL<2027> A_IWL<2026> A_IWL<2025> A_IWL<2024> A_IWL<2023> A_IWL<2022> A_IWL<2021> A_IWL<2020> A_IWL<2019> A_IWL<2018> A_IWL<2017> A_IWL<2016> A_IWL<2015> A_IWL<2014> A_IWL<2013> A_IWL<2012> A_IWL<2011> A_IWL<2010> A_IWL<2009> A_IWL<2008> A_IWL<2007> A_IWL<2006> A_IWL<2005> A_IWL<2004> A_IWL<2003> A_IWL<2002> A_IWL<2001> A_IWL<2000> A_IWL<1999> A_IWL<1998> A_IWL<1997> A_IWL<1996> A_IWL<1995> A_IWL<1994> A_IWL<1993> A_IWL<1992> A_IWL<1991> A_IWL<1990> A_IWL<1989> A_IWL<1988> A_IWL<1987> A_IWL<1986> A_IWL<1985> A_IWL<1984> A_IWL<1983> A_IWL<1982> A_IWL<1981> A_IWL<1980> A_IWL<1979> A_IWL<1978> A_IWL<1977> A_IWL<1976> A_IWL<1975> A_IWL<1974> A_IWL<1973> A_IWL<1972> A_IWL<1971> A_IWL<1970> A_IWL<1969> A_IWL<1968> A_IWL<1967> A_IWL<1966> A_IWL<1965> A_IWL<1964> A_IWL<1963> A_IWL<1962> A_IWL<1961> A_IWL<1960> A_IWL<1959> A_IWL<1958> A_IWL<1957> A_IWL<1956> A_IWL<1955> A_IWL<1954> A_IWL<1953> A_IWL<1952> A_IWL<1951> A_IWL<1950> A_IWL<1949> A_IWL<1948> A_IWL<1947> A_IWL<1946> A_IWL<1945> A_IWL<1944> A_IWL<1943> A_IWL<1942> A_IWL<1941> A_IWL<1940> A_IWL<1939> A_IWL<1938> A_IWL<1937> A_IWL<1936> A_IWL<1935> A_IWL<1934> A_IWL<1933> A_IWL<1932> A_IWL<1931> A_IWL<1930> A_IWL<1929> A_IWL<1928> A_IWL<1927> A_IWL<1926> A_IWL<1925> A_IWL<1924> A_IWL<1923> A_IWL<1922> A_IWL<1921> A_IWL<1920> A_IWL<1919> A_IWL<1918> A_IWL<1917> A_IWL<1916> A_IWL<1915> A_IWL<1914> A_IWL<1913> A_IWL<1912> A_IWL<1911> A_IWL<1910> A_IWL<1909> A_IWL<1908> A_IWL<1907> A_IWL<1906> A_IWL<1905> A_IWL<1904> A_IWL<1903> A_IWL<1902> A_IWL<1901> A_IWL<1900> A_IWL<1899> A_IWL<1898> A_IWL<1897> A_IWL<1896> A_IWL<1895> A_IWL<1894> A_IWL<1893> A_IWL<1892> A_IWL<1891> A_IWL<1890> A_IWL<1889> A_IWL<1888> A_IWL<1887> A_IWL<1886> A_IWL<1885> A_IWL<1884> A_IWL<1883> A_IWL<1882> A_IWL<1881> A_IWL<1880> A_IWL<1879> A_IWL<1878> A_IWL<1877> A_IWL<1876> A_IWL<1875> A_IWL<1874> A_IWL<1873> A_IWL<1872> A_IWL<1871> A_IWL<1870> A_IWL<1869> A_IWL<1868> A_IWL<1867> A_IWL<1866> A_IWL<1865> A_IWL<1864> A_IWL<1863> A_IWL<1862> A_IWL<1861> A_IWL<1860> A_IWL<1859> A_IWL<1858> A_IWL<1857> A_IWL<1856> A_IWL<1855> A_IWL<1854> A_IWL<1853> A_IWL<1852> A_IWL<1851> A_IWL<1850> A_IWL<1849> A_IWL<1848> A_IWL<1847> A_IWL<1846> A_IWL<1845> A_IWL<1844> A_IWL<1843> A_IWL<1842> A_IWL<1841> A_IWL<1840> A_IWL<1839> A_IWL<1838> A_IWL<1837> A_IWL<1836> A_IWL<1835> A_IWL<1834> A_IWL<1833> A_IWL<1832> A_IWL<1831> A_IWL<1830> A_IWL<1829> A_IWL<1828> A_IWL<1827> A_IWL<1826> A_IWL<1825> A_IWL<1824> A_IWL<1823> A_IWL<1822> A_IWL<1821> A_IWL<1820> A_IWL<1819> A_IWL<1818> A_IWL<1817> A_IWL<1816> A_IWL<1815> A_IWL<1814> A_IWL<1813> A_IWL<1812> A_IWL<1811> A_IWL<1810> A_IWL<1809> A_IWL<1808> A_IWL<1807> A_IWL<1806> A_IWL<1805> A_IWL<1804> A_IWL<1803> A_IWL<1802> A_IWL<1801> A_IWL<1800> A_IWL<1799> A_IWL<1798> A_IWL<1797> A_IWL<1796> A_IWL<1795> A_IWL<1794> A_IWL<1793> A_IWL<1792> A_IWL<1791> A_IWL<1790> A_IWL<1789> A_IWL<1788> A_IWL<1787> A_IWL<1786> A_IWL<1785> A_IWL<1784> A_IWL<1783> A_IWL<1782> A_IWL<1781> A_IWL<1780> A_IWL<1779> A_IWL<1778> A_IWL<1777> A_IWL<1776> A_IWL<1775> A_IWL<1774> A_IWL<1773> A_IWL<1772> A_IWL<1771> A_IWL<1770> A_IWL<1769> A_IWL<1768> A_IWL<1767> A_IWL<1766> A_IWL<1765> A_IWL<1764> A_IWL<1763> A_IWL<1762> A_IWL<1761> A_IWL<1760> A_IWL<1759> A_IWL<1758> A_IWL<1757> A_IWL<1756> A_IWL<1755> A_IWL<1754> A_IWL<1753> A_IWL<1752> A_IWL<1751> A_IWL<1750> A_IWL<1749> A_IWL<1748> A_IWL<1747> A_IWL<1746> A_IWL<1745> A_IWL<1744> A_IWL<1743> A_IWL<1742> A_IWL<1741> A_IWL<1740> A_IWL<1739> A_IWL<1738> A_IWL<1737> A_IWL<1736> A_IWL<1735> A_IWL<1734> A_IWL<1733> A_IWL<1732> A_IWL<1731> A_IWL<1730> A_IWL<1729> A_IWL<1728> A_IWL<1727> A_IWL<1726> A_IWL<1725> A_IWL<1724> A_IWL<1723> A_IWL<1722> A_IWL<1721> A_IWL<1720> A_IWL<1719> A_IWL<1718> A_IWL<1717> A_IWL<1716> A_IWL<1715> A_IWL<1714> A_IWL<1713> A_IWL<1712> A_IWL<1711> A_IWL<1710> A_IWL<1709> A_IWL<1708> A_IWL<1707> A_IWL<1706> A_IWL<1705> A_IWL<1704> A_IWL<1703> A_IWL<1702> A_IWL<1701> A_IWL<1700> A_IWL<1699> A_IWL<1698> A_IWL<1697> A_IWL<1696> A_IWL<1695> A_IWL<1694> A_IWL<1693> A_IWL<1692> A_IWL<1691> A_IWL<1690> A_IWL<1689> A_IWL<1688> A_IWL<1687> A_IWL<1686> A_IWL<1685> A_IWL<1684> A_IWL<1683> A_IWL<1682> A_IWL<1681> A_IWL<1680> A_IWL<1679> A_IWL<1678> A_IWL<1677> A_IWL<1676> A_IWL<1675> A_IWL<1674> A_IWL<1673> A_IWL<1672> A_IWL<1671> A_IWL<1670> A_IWL<1669> A_IWL<1668> A_IWL<1667> A_IWL<1666> A_IWL<1665> A_IWL<1664> A_IWL<1663> A_IWL<1662> A_IWL<1661> A_IWL<1660> A_IWL<1659> A_IWL<1658> A_IWL<1657> A_IWL<1656> A_IWL<1655> A_IWL<1654> A_IWL<1653> A_IWL<1652> A_IWL<1651> A_IWL<1650> A_IWL<1649> A_IWL<1648> A_IWL<1647> A_IWL<1646> A_IWL<1645> A_IWL<1644> A_IWL<1643> A_IWL<1642> A_IWL<1641> A_IWL<1640> A_IWL<1639> A_IWL<1638> A_IWL<1637> A_IWL<1636> A_IWL<1635> A_IWL<1634> A_IWL<1633> A_IWL<1632> A_IWL<1631> A_IWL<1630> A_IWL<1629> A_IWL<1628> A_IWL<1627> A_IWL<1626> A_IWL<1625> A_IWL<1624> A_IWL<1623> A_IWL<1622> A_IWL<1621> A_IWL<1620> A_IWL<1619> A_IWL<1618> A_IWL<1617> A_IWL<1616> A_IWL<1615> A_IWL<1614> A_IWL<1613> A_IWL<1612> A_IWL<1611> A_IWL<1610> A_IWL<1609> A_IWL<1608> A_IWL<1607> A_IWL<1606> A_IWL<1605> A_IWL<1604> A_IWL<1603> A_IWL<1602> A_IWL<1601> A_IWL<1600> A_IWL<1599> A_IWL<1598> A_IWL<1597> A_IWL<1596> A_IWL<1595> A_IWL<1594> A_IWL<1593> A_IWL<1592> A_IWL<1591> A_IWL<1590> A_IWL<1589> A_IWL<1588> A_IWL<1587> A_IWL<1586> A_IWL<1585> A_IWL<1584> A_IWL<1583> A_IWL<1582> A_IWL<1581> A_IWL<1580> A_IWL<1579> A_IWL<1578> A_IWL<1577> A_IWL<1576> A_IWL<1575> A_IWL<1574> A_IWL<1573> A_IWL<1572> A_IWL<1571> A_IWL<1570> A_IWL<1569> A_IWL<1568> A_IWL<1567> A_IWL<1566> A_IWL<1565> A_IWL<1564> A_IWL<1563> A_IWL<1562> A_IWL<1561> A_IWL<1560> A_IWL<1559> A_IWL<1558> A_IWL<1557> A_IWL<1556> A_IWL<1555> A_IWL<1554> A_IWL<1553> A_IWL<1552> A_IWL<1551> A_IWL<1550> A_IWL<1549> A_IWL<1548> A_IWL<1547> A_IWL<1546> A_IWL<1545> A_IWL<1544> A_IWL<1543> A_IWL<1542> A_IWL<1541> A_IWL<1540> A_IWL<1539> A_IWL<1538> A_IWL<1537> A_IWL<1536> A_IWL<2559> A_IWL<2558> A_IWL<2557> A_IWL<2556> A_IWL<2555> A_IWL<2554> A_IWL<2553> A_IWL<2552> A_IWL<2551> A_IWL<2550> A_IWL<2549> A_IWL<2548> A_IWL<2547> A_IWL<2546> A_IWL<2545> A_IWL<2544> A_IWL<2543> A_IWL<2542> A_IWL<2541> A_IWL<2540> A_IWL<2539> A_IWL<2538> A_IWL<2537> A_IWL<2536> A_IWL<2535> A_IWL<2534> A_IWL<2533> A_IWL<2532> A_IWL<2531> A_IWL<2530> A_IWL<2529> A_IWL<2528> A_IWL<2527> A_IWL<2526> A_IWL<2525> A_IWL<2524> A_IWL<2523> A_IWL<2522> A_IWL<2521> A_IWL<2520> A_IWL<2519> A_IWL<2518> A_IWL<2517> A_IWL<2516> A_IWL<2515> A_IWL<2514> A_IWL<2513> A_IWL<2512> A_IWL<2511> A_IWL<2510> A_IWL<2509> A_IWL<2508> A_IWL<2507> A_IWL<2506> A_IWL<2505> A_IWL<2504> A_IWL<2503> A_IWL<2502> A_IWL<2501> A_IWL<2500> A_IWL<2499> A_IWL<2498> A_IWL<2497> A_IWL<2496> A_IWL<2495> A_IWL<2494> A_IWL<2493> A_IWL<2492> A_IWL<2491> A_IWL<2490> A_IWL<2489> A_IWL<2488> A_IWL<2487> A_IWL<2486> A_IWL<2485> A_IWL<2484> A_IWL<2483> A_IWL<2482> A_IWL<2481> A_IWL<2480> A_IWL<2479> A_IWL<2478> A_IWL<2477> A_IWL<2476> A_IWL<2475> A_IWL<2474> A_IWL<2473> A_IWL<2472> A_IWL<2471> A_IWL<2470> A_IWL<2469> A_IWL<2468> A_IWL<2467> A_IWL<2466> A_IWL<2465> A_IWL<2464> A_IWL<2463> A_IWL<2462> A_IWL<2461> A_IWL<2460> A_IWL<2459> A_IWL<2458> A_IWL<2457> A_IWL<2456> A_IWL<2455> A_IWL<2454> A_IWL<2453> A_IWL<2452> A_IWL<2451> A_IWL<2450> A_IWL<2449> A_IWL<2448> A_IWL<2447> A_IWL<2446> A_IWL<2445> A_IWL<2444> A_IWL<2443> A_IWL<2442> A_IWL<2441> A_IWL<2440> A_IWL<2439> A_IWL<2438> A_IWL<2437> A_IWL<2436> A_IWL<2435> A_IWL<2434> A_IWL<2433> A_IWL<2432> A_IWL<2431> A_IWL<2430> A_IWL<2429> A_IWL<2428> A_IWL<2427> A_IWL<2426> A_IWL<2425> A_IWL<2424> A_IWL<2423> A_IWL<2422> A_IWL<2421> A_IWL<2420> A_IWL<2419> A_IWL<2418> A_IWL<2417> A_IWL<2416> A_IWL<2415> A_IWL<2414> A_IWL<2413> A_IWL<2412> A_IWL<2411> A_IWL<2410> A_IWL<2409> A_IWL<2408> A_IWL<2407> A_IWL<2406> A_IWL<2405> A_IWL<2404> A_IWL<2403> A_IWL<2402> A_IWL<2401> A_IWL<2400> A_IWL<2399> A_IWL<2398> A_IWL<2397> A_IWL<2396> A_IWL<2395> A_IWL<2394> A_IWL<2393> A_IWL<2392> A_IWL<2391> A_IWL<2390> A_IWL<2389> A_IWL<2388> A_IWL<2387> A_IWL<2386> A_IWL<2385> A_IWL<2384> A_IWL<2383> A_IWL<2382> A_IWL<2381> A_IWL<2380> A_IWL<2379> A_IWL<2378> A_IWL<2377> A_IWL<2376> A_IWL<2375> A_IWL<2374> A_IWL<2373> A_IWL<2372> A_IWL<2371> A_IWL<2370> A_IWL<2369> A_IWL<2368> A_IWL<2367> A_IWL<2366> A_IWL<2365> A_IWL<2364> A_IWL<2363> A_IWL<2362> A_IWL<2361> A_IWL<2360> A_IWL<2359> A_IWL<2358> A_IWL<2357> A_IWL<2356> A_IWL<2355> A_IWL<2354> A_IWL<2353> A_IWL<2352> A_IWL<2351> A_IWL<2350> A_IWL<2349> A_IWL<2348> A_IWL<2347> A_IWL<2346> A_IWL<2345> A_IWL<2344> A_IWL<2343> A_IWL<2342> A_IWL<2341> A_IWL<2340> A_IWL<2339> A_IWL<2338> A_IWL<2337> A_IWL<2336> A_IWL<2335> A_IWL<2334> A_IWL<2333> A_IWL<2332> A_IWL<2331> A_IWL<2330> A_IWL<2329> A_IWL<2328> A_IWL<2327> A_IWL<2326> A_IWL<2325> A_IWL<2324> A_IWL<2323> A_IWL<2322> A_IWL<2321> A_IWL<2320> A_IWL<2319> A_IWL<2318> A_IWL<2317> A_IWL<2316> A_IWL<2315> A_IWL<2314> A_IWL<2313> A_IWL<2312> A_IWL<2311> A_IWL<2310> A_IWL<2309> A_IWL<2308> A_IWL<2307> A_IWL<2306> A_IWL<2305> A_IWL<2304> A_IWL<2303> A_IWL<2302> A_IWL<2301> A_IWL<2300> A_IWL<2299> A_IWL<2298> A_IWL<2297> A_IWL<2296> A_IWL<2295> A_IWL<2294> A_IWL<2293> A_IWL<2292> A_IWL<2291> A_IWL<2290> A_IWL<2289> A_IWL<2288> A_IWL<2287> A_IWL<2286> A_IWL<2285> A_IWL<2284> A_IWL<2283> A_IWL<2282> A_IWL<2281> A_IWL<2280> A_IWL<2279> A_IWL<2278> A_IWL<2277> A_IWL<2276> A_IWL<2275> A_IWL<2274> A_IWL<2273> A_IWL<2272> A_IWL<2271> A_IWL<2270> A_IWL<2269> A_IWL<2268> A_IWL<2267> A_IWL<2266> A_IWL<2265> A_IWL<2264> A_IWL<2263> A_IWL<2262> A_IWL<2261> A_IWL<2260> A_IWL<2259> A_IWL<2258> A_IWL<2257> A_IWL<2256> A_IWL<2255> A_IWL<2254> A_IWL<2253> A_IWL<2252> A_IWL<2251> A_IWL<2250> A_IWL<2249> A_IWL<2248> A_IWL<2247> A_IWL<2246> A_IWL<2245> A_IWL<2244> A_IWL<2243> A_IWL<2242> A_IWL<2241> A_IWL<2240> A_IWL<2239> A_IWL<2238> A_IWL<2237> A_IWL<2236> A_IWL<2235> A_IWL<2234> A_IWL<2233> A_IWL<2232> A_IWL<2231> A_IWL<2230> A_IWL<2229> A_IWL<2228> A_IWL<2227> A_IWL<2226> A_IWL<2225> A_IWL<2224> A_IWL<2223> A_IWL<2222> A_IWL<2221> A_IWL<2220> A_IWL<2219> A_IWL<2218> A_IWL<2217> A_IWL<2216> A_IWL<2215> A_IWL<2214> A_IWL<2213> A_IWL<2212> A_IWL<2211> A_IWL<2210> A_IWL<2209> A_IWL<2208> A_IWL<2207> A_IWL<2206> A_IWL<2205> A_IWL<2204> A_IWL<2203> A_IWL<2202> A_IWL<2201> A_IWL<2200> A_IWL<2199> A_IWL<2198> A_IWL<2197> A_IWL<2196> A_IWL<2195> A_IWL<2194> A_IWL<2193> A_IWL<2192> A_IWL<2191> A_IWL<2190> A_IWL<2189> A_IWL<2188> A_IWL<2187> A_IWL<2186> A_IWL<2185> A_IWL<2184> A_IWL<2183> A_IWL<2182> A_IWL<2181> A_IWL<2180> A_IWL<2179> A_IWL<2178> A_IWL<2177> A_IWL<2176> A_IWL<2175> A_IWL<2174> A_IWL<2173> A_IWL<2172> A_IWL<2171> A_IWL<2170> A_IWL<2169> A_IWL<2168> A_IWL<2167> A_IWL<2166> A_IWL<2165> A_IWL<2164> A_IWL<2163> A_IWL<2162> A_IWL<2161> A_IWL<2160> A_IWL<2159> A_IWL<2158> A_IWL<2157> A_IWL<2156> A_IWL<2155> A_IWL<2154> A_IWL<2153> A_IWL<2152> A_IWL<2151> A_IWL<2150> A_IWL<2149> A_IWL<2148> A_IWL<2147> A_IWL<2146> A_IWL<2145> A_IWL<2144> A_IWL<2143> A_IWL<2142> A_IWL<2141> A_IWL<2140> A_IWL<2139> A_IWL<2138> A_IWL<2137> A_IWL<2136> A_IWL<2135> A_IWL<2134> A_IWL<2133> A_IWL<2132> A_IWL<2131> A_IWL<2130> A_IWL<2129> A_IWL<2128> A_IWL<2127> A_IWL<2126> A_IWL<2125> A_IWL<2124> A_IWL<2123> A_IWL<2122> A_IWL<2121> A_IWL<2120> A_IWL<2119> A_IWL<2118> A_IWL<2117> A_IWL<2116> A_IWL<2115> A_IWL<2114> A_IWL<2113> A_IWL<2112> A_IWL<2111> A_IWL<2110> A_IWL<2109> A_IWL<2108> A_IWL<2107> A_IWL<2106> A_IWL<2105> A_IWL<2104> A_IWL<2103> A_IWL<2102> A_IWL<2101> A_IWL<2100> A_IWL<2099> A_IWL<2098> A_IWL<2097> A_IWL<2096> A_IWL<2095> A_IWL<2094> A_IWL<2093> A_IWL<2092> A_IWL<2091> A_IWL<2090> A_IWL<2089> A_IWL<2088> A_IWL<2087> A_IWL<2086> A_IWL<2085> A_IWL<2084> A_IWL<2083> A_IWL<2082> A_IWL<2081> A_IWL<2080> A_IWL<2079> A_IWL<2078> A_IWL<2077> A_IWL<2076> A_IWL<2075> A_IWL<2074> A_IWL<2073> A_IWL<2072> A_IWL<2071> A_IWL<2070> A_IWL<2069> A_IWL<2068> A_IWL<2067> A_IWL<2066> A_IWL<2065> A_IWL<2064> A_IWL<2063> A_IWL<2062> A_IWL<2061> A_IWL<2060> A_IWL<2059> A_IWL<2058> A_IWL<2057> A_IWL<2056> A_IWL<2055> A_IWL<2054> A_IWL<2053> A_IWL<2052> A_IWL<2051> A_IWL<2050> A_IWL<2049> A_IWL<2048> VDD_CORE VSS / RM_IHPSG13_8192x32_c4_1P_COLUMN_pcell_0 +XCOL<3> A_BLC<7> A_BLC<6> A_BLC_TOP<7> A_BLC_TOP<6> A_BLT<7> A_BLT<6> A_BLT_TOP<7> A_BLT_TOP<6> A_IWL<1535> A_IWL<1534> A_IWL<1533> A_IWL<1532> A_IWL<1531> A_IWL<1530> A_IWL<1529> A_IWL<1528> A_IWL<1527> A_IWL<1526> A_IWL<1525> A_IWL<1524> A_IWL<1523> A_IWL<1522> A_IWL<1521> A_IWL<1520> A_IWL<1519> A_IWL<1518> A_IWL<1517> A_IWL<1516> A_IWL<1515> A_IWL<1514> A_IWL<1513> A_IWL<1512> A_IWL<1511> A_IWL<1510> A_IWL<1509> A_IWL<1508> A_IWL<1507> A_IWL<1506> A_IWL<1505> A_IWL<1504> A_IWL<1503> A_IWL<1502> A_IWL<1501> A_IWL<1500> A_IWL<1499> A_IWL<1498> A_IWL<1497> A_IWL<1496> A_IWL<1495> A_IWL<1494> A_IWL<1493> A_IWL<1492> A_IWL<1491> A_IWL<1490> A_IWL<1489> A_IWL<1488> A_IWL<1487> A_IWL<1486> A_IWL<1485> A_IWL<1484> A_IWL<1483> A_IWL<1482> A_IWL<1481> A_IWL<1480> A_IWL<1479> A_IWL<1478> A_IWL<1477> A_IWL<1476> A_IWL<1475> A_IWL<1474> A_IWL<1473> A_IWL<1472> A_IWL<1471> A_IWL<1470> A_IWL<1469> A_IWL<1468> A_IWL<1467> A_IWL<1466> A_IWL<1465> A_IWL<1464> A_IWL<1463> A_IWL<1462> A_IWL<1461> A_IWL<1460> A_IWL<1459> A_IWL<1458> A_IWL<1457> A_IWL<1456> A_IWL<1455> A_IWL<1454> A_IWL<1453> A_IWL<1452> A_IWL<1451> A_IWL<1450> A_IWL<1449> A_IWL<1448> A_IWL<1447> A_IWL<1446> A_IWL<1445> A_IWL<1444> A_IWL<1443> A_IWL<1442> A_IWL<1441> A_IWL<1440> A_IWL<1439> A_IWL<1438> A_IWL<1437> A_IWL<1436> A_IWL<1435> A_IWL<1434> A_IWL<1433> A_IWL<1432> A_IWL<1431> A_IWL<1430> A_IWL<1429> A_IWL<1428> A_IWL<1427> A_IWL<1426> A_IWL<1425> A_IWL<1424> A_IWL<1423> A_IWL<1422> A_IWL<1421> A_IWL<1420> A_IWL<1419> A_IWL<1418> A_IWL<1417> A_IWL<1416> A_IWL<1415> A_IWL<1414> A_IWL<1413> A_IWL<1412> A_IWL<1411> A_IWL<1410> A_IWL<1409> A_IWL<1408> A_IWL<1407> A_IWL<1406> A_IWL<1405> A_IWL<1404> A_IWL<1403> A_IWL<1402> A_IWL<1401> A_IWL<1400> A_IWL<1399> A_IWL<1398> A_IWL<1397> A_IWL<1396> A_IWL<1395> A_IWL<1394> A_IWL<1393> A_IWL<1392> A_IWL<1391> A_IWL<1390> A_IWL<1389> A_IWL<1388> A_IWL<1387> A_IWL<1386> A_IWL<1385> A_IWL<1384> A_IWL<1383> A_IWL<1382> A_IWL<1381> A_IWL<1380> A_IWL<1379> A_IWL<1378> A_IWL<1377> A_IWL<1376> A_IWL<1375> A_IWL<1374> A_IWL<1373> A_IWL<1372> A_IWL<1371> A_IWL<1370> A_IWL<1369> A_IWL<1368> A_IWL<1367> A_IWL<1366> A_IWL<1365> A_IWL<1364> A_IWL<1363> A_IWL<1362> A_IWL<1361> A_IWL<1360> A_IWL<1359> A_IWL<1358> A_IWL<1357> A_IWL<1356> A_IWL<1355> A_IWL<1354> A_IWL<1353> A_IWL<1352> A_IWL<1351> A_IWL<1350> A_IWL<1349> A_IWL<1348> A_IWL<1347> A_IWL<1346> A_IWL<1345> A_IWL<1344> A_IWL<1343> A_IWL<1342> A_IWL<1341> A_IWL<1340> A_IWL<1339> A_IWL<1338> A_IWL<1337> A_IWL<1336> A_IWL<1335> A_IWL<1334> A_IWL<1333> A_IWL<1332> A_IWL<1331> A_IWL<1330> A_IWL<1329> A_IWL<1328> A_IWL<1327> A_IWL<1326> A_IWL<1325> A_IWL<1324> A_IWL<1323> A_IWL<1322> A_IWL<1321> A_IWL<1320> A_IWL<1319> A_IWL<1318> A_IWL<1317> A_IWL<1316> A_IWL<1315> A_IWL<1314> A_IWL<1313> A_IWL<1312> A_IWL<1311> A_IWL<1310> A_IWL<1309> A_IWL<1308> A_IWL<1307> A_IWL<1306> A_IWL<1305> A_IWL<1304> A_IWL<1303> A_IWL<1302> A_IWL<1301> A_IWL<1300> A_IWL<1299> A_IWL<1298> A_IWL<1297> A_IWL<1296> A_IWL<1295> A_IWL<1294> A_IWL<1293> A_IWL<1292> A_IWL<1291> A_IWL<1290> A_IWL<1289> A_IWL<1288> A_IWL<1287> A_IWL<1286> A_IWL<1285> A_IWL<1284> A_IWL<1283> A_IWL<1282> A_IWL<1281> A_IWL<1280> A_IWL<1279> A_IWL<1278> A_IWL<1277> A_IWL<1276> A_IWL<1275> A_IWL<1274> A_IWL<1273> A_IWL<1272> A_IWL<1271> A_IWL<1270> A_IWL<1269> A_IWL<1268> A_IWL<1267> A_IWL<1266> A_IWL<1265> A_IWL<1264> A_IWL<1263> A_IWL<1262> A_IWL<1261> A_IWL<1260> A_IWL<1259> A_IWL<1258> A_IWL<1257> A_IWL<1256> A_IWL<1255> A_IWL<1254> A_IWL<1253> A_IWL<1252> A_IWL<1251> A_IWL<1250> A_IWL<1249> A_IWL<1248> A_IWL<1247> A_IWL<1246> A_IWL<1245> A_IWL<1244> A_IWL<1243> A_IWL<1242> A_IWL<1241> A_IWL<1240> A_IWL<1239> A_IWL<1238> A_IWL<1237> A_IWL<1236> A_IWL<1235> A_IWL<1234> A_IWL<1233> A_IWL<1232> A_IWL<1231> A_IWL<1230> A_IWL<1229> A_IWL<1228> A_IWL<1227> A_IWL<1226> A_IWL<1225> A_IWL<1224> A_IWL<1223> A_IWL<1222> A_IWL<1221> A_IWL<1220> A_IWL<1219> A_IWL<1218> A_IWL<1217> A_IWL<1216> A_IWL<1215> A_IWL<1214> A_IWL<1213> A_IWL<1212> A_IWL<1211> A_IWL<1210> A_IWL<1209> A_IWL<1208> A_IWL<1207> A_IWL<1206> A_IWL<1205> A_IWL<1204> A_IWL<1203> A_IWL<1202> A_IWL<1201> A_IWL<1200> A_IWL<1199> A_IWL<1198> A_IWL<1197> A_IWL<1196> A_IWL<1195> A_IWL<1194> A_IWL<1193> A_IWL<1192> A_IWL<1191> A_IWL<1190> A_IWL<1189> A_IWL<1188> A_IWL<1187> A_IWL<1186> A_IWL<1185> A_IWL<1184> A_IWL<1183> A_IWL<1182> A_IWL<1181> A_IWL<1180> A_IWL<1179> A_IWL<1178> A_IWL<1177> A_IWL<1176> A_IWL<1175> A_IWL<1174> A_IWL<1173> A_IWL<1172> A_IWL<1171> A_IWL<1170> A_IWL<1169> A_IWL<1168> A_IWL<1167> A_IWL<1166> A_IWL<1165> A_IWL<1164> A_IWL<1163> A_IWL<1162> A_IWL<1161> A_IWL<1160> A_IWL<1159> A_IWL<1158> A_IWL<1157> A_IWL<1156> A_IWL<1155> A_IWL<1154> A_IWL<1153> A_IWL<1152> A_IWL<1151> A_IWL<1150> A_IWL<1149> A_IWL<1148> A_IWL<1147> A_IWL<1146> A_IWL<1145> A_IWL<1144> A_IWL<1143> A_IWL<1142> A_IWL<1141> A_IWL<1140> A_IWL<1139> A_IWL<1138> A_IWL<1137> A_IWL<1136> A_IWL<1135> A_IWL<1134> A_IWL<1133> A_IWL<1132> A_IWL<1131> A_IWL<1130> A_IWL<1129> A_IWL<1128> A_IWL<1127> A_IWL<1126> A_IWL<1125> A_IWL<1124> A_IWL<1123> A_IWL<1122> A_IWL<1121> A_IWL<1120> A_IWL<1119> A_IWL<1118> A_IWL<1117> A_IWL<1116> A_IWL<1115> A_IWL<1114> A_IWL<1113> A_IWL<1112> A_IWL<1111> A_IWL<1110> A_IWL<1109> A_IWL<1108> A_IWL<1107> A_IWL<1106> A_IWL<1105> A_IWL<1104> A_IWL<1103> A_IWL<1102> A_IWL<1101> A_IWL<1100> A_IWL<1099> A_IWL<1098> A_IWL<1097> A_IWL<1096> A_IWL<1095> A_IWL<1094> A_IWL<1093> A_IWL<1092> A_IWL<1091> A_IWL<1090> A_IWL<1089> A_IWL<1088> A_IWL<1087> A_IWL<1086> A_IWL<1085> A_IWL<1084> A_IWL<1083> A_IWL<1082> A_IWL<1081> A_IWL<1080> A_IWL<1079> A_IWL<1078> A_IWL<1077> A_IWL<1076> A_IWL<1075> A_IWL<1074> A_IWL<1073> A_IWL<1072> A_IWL<1071> A_IWL<1070> A_IWL<1069> A_IWL<1068> A_IWL<1067> A_IWL<1066> A_IWL<1065> A_IWL<1064> A_IWL<1063> A_IWL<1062> A_IWL<1061> A_IWL<1060> A_IWL<1059> A_IWL<1058> A_IWL<1057> A_IWL<1056> A_IWL<1055> A_IWL<1054> A_IWL<1053> A_IWL<1052> A_IWL<1051> A_IWL<1050> A_IWL<1049> A_IWL<1048> A_IWL<1047> A_IWL<1046> A_IWL<1045> A_IWL<1044> A_IWL<1043> A_IWL<1042> A_IWL<1041> A_IWL<1040> A_IWL<1039> A_IWL<1038> A_IWL<1037> A_IWL<1036> A_IWL<1035> A_IWL<1034> A_IWL<1033> A_IWL<1032> A_IWL<1031> A_IWL<1030> A_IWL<1029> A_IWL<1028> A_IWL<1027> A_IWL<1026> A_IWL<1025> A_IWL<1024> A_IWL<2047> A_IWL<2046> A_IWL<2045> A_IWL<2044> A_IWL<2043> A_IWL<2042> A_IWL<2041> A_IWL<2040> A_IWL<2039> A_IWL<2038> A_IWL<2037> A_IWL<2036> A_IWL<2035> A_IWL<2034> A_IWL<2033> A_IWL<2032> A_IWL<2031> A_IWL<2030> A_IWL<2029> A_IWL<2028> A_IWL<2027> A_IWL<2026> A_IWL<2025> A_IWL<2024> A_IWL<2023> A_IWL<2022> A_IWL<2021> A_IWL<2020> A_IWL<2019> A_IWL<2018> A_IWL<2017> A_IWL<2016> A_IWL<2015> A_IWL<2014> A_IWL<2013> A_IWL<2012> A_IWL<2011> A_IWL<2010> A_IWL<2009> A_IWL<2008> A_IWL<2007> A_IWL<2006> A_IWL<2005> A_IWL<2004> A_IWL<2003> A_IWL<2002> A_IWL<2001> A_IWL<2000> A_IWL<1999> A_IWL<1998> A_IWL<1997> A_IWL<1996> A_IWL<1995> A_IWL<1994> A_IWL<1993> A_IWL<1992> A_IWL<1991> A_IWL<1990> A_IWL<1989> A_IWL<1988> A_IWL<1987> A_IWL<1986> A_IWL<1985> A_IWL<1984> A_IWL<1983> A_IWL<1982> A_IWL<1981> A_IWL<1980> A_IWL<1979> A_IWL<1978> A_IWL<1977> A_IWL<1976> A_IWL<1975> A_IWL<1974> A_IWL<1973> A_IWL<1972> A_IWL<1971> A_IWL<1970> A_IWL<1969> A_IWL<1968> A_IWL<1967> A_IWL<1966> A_IWL<1965> A_IWL<1964> A_IWL<1963> A_IWL<1962> A_IWL<1961> A_IWL<1960> A_IWL<1959> A_IWL<1958> A_IWL<1957> A_IWL<1956> A_IWL<1955> A_IWL<1954> A_IWL<1953> A_IWL<1952> A_IWL<1951> A_IWL<1950> A_IWL<1949> A_IWL<1948> A_IWL<1947> A_IWL<1946> A_IWL<1945> A_IWL<1944> A_IWL<1943> A_IWL<1942> A_IWL<1941> A_IWL<1940> A_IWL<1939> A_IWL<1938> A_IWL<1937> A_IWL<1936> A_IWL<1935> A_IWL<1934> A_IWL<1933> A_IWL<1932> A_IWL<1931> A_IWL<1930> A_IWL<1929> A_IWL<1928> A_IWL<1927> A_IWL<1926> A_IWL<1925> A_IWL<1924> A_IWL<1923> A_IWL<1922> A_IWL<1921> A_IWL<1920> A_IWL<1919> A_IWL<1918> A_IWL<1917> A_IWL<1916> A_IWL<1915> A_IWL<1914> A_IWL<1913> A_IWL<1912> A_IWL<1911> A_IWL<1910> A_IWL<1909> A_IWL<1908> A_IWL<1907> A_IWL<1906> A_IWL<1905> A_IWL<1904> A_IWL<1903> A_IWL<1902> A_IWL<1901> A_IWL<1900> A_IWL<1899> A_IWL<1898> A_IWL<1897> A_IWL<1896> A_IWL<1895> A_IWL<1894> A_IWL<1893> A_IWL<1892> A_IWL<1891> A_IWL<1890> A_IWL<1889> A_IWL<1888> A_IWL<1887> A_IWL<1886> A_IWL<1885> A_IWL<1884> A_IWL<1883> A_IWL<1882> A_IWL<1881> A_IWL<1880> A_IWL<1879> A_IWL<1878> A_IWL<1877> A_IWL<1876> A_IWL<1875> A_IWL<1874> A_IWL<1873> A_IWL<1872> A_IWL<1871> A_IWL<1870> A_IWL<1869> A_IWL<1868> A_IWL<1867> A_IWL<1866> A_IWL<1865> A_IWL<1864> A_IWL<1863> A_IWL<1862> A_IWL<1861> A_IWL<1860> A_IWL<1859> A_IWL<1858> A_IWL<1857> A_IWL<1856> A_IWL<1855> A_IWL<1854> A_IWL<1853> A_IWL<1852> A_IWL<1851> A_IWL<1850> A_IWL<1849> A_IWL<1848> A_IWL<1847> A_IWL<1846> A_IWL<1845> A_IWL<1844> A_IWL<1843> A_IWL<1842> A_IWL<1841> A_IWL<1840> A_IWL<1839> A_IWL<1838> A_IWL<1837> A_IWL<1836> A_IWL<1835> A_IWL<1834> A_IWL<1833> A_IWL<1832> A_IWL<1831> A_IWL<1830> A_IWL<1829> A_IWL<1828> A_IWL<1827> A_IWL<1826> A_IWL<1825> A_IWL<1824> A_IWL<1823> A_IWL<1822> A_IWL<1821> A_IWL<1820> A_IWL<1819> A_IWL<1818> A_IWL<1817> A_IWL<1816> A_IWL<1815> A_IWL<1814> A_IWL<1813> A_IWL<1812> A_IWL<1811> A_IWL<1810> A_IWL<1809> A_IWL<1808> A_IWL<1807> A_IWL<1806> A_IWL<1805> A_IWL<1804> A_IWL<1803> A_IWL<1802> A_IWL<1801> A_IWL<1800> A_IWL<1799> A_IWL<1798> A_IWL<1797> A_IWL<1796> A_IWL<1795> A_IWL<1794> A_IWL<1793> A_IWL<1792> A_IWL<1791> A_IWL<1790> A_IWL<1789> A_IWL<1788> A_IWL<1787> A_IWL<1786> A_IWL<1785> A_IWL<1784> A_IWL<1783> A_IWL<1782> A_IWL<1781> A_IWL<1780> A_IWL<1779> A_IWL<1778> A_IWL<1777> A_IWL<1776> A_IWL<1775> A_IWL<1774> A_IWL<1773> A_IWL<1772> A_IWL<1771> A_IWL<1770> A_IWL<1769> A_IWL<1768> A_IWL<1767> A_IWL<1766> A_IWL<1765> A_IWL<1764> A_IWL<1763> A_IWL<1762> A_IWL<1761> A_IWL<1760> A_IWL<1759> A_IWL<1758> A_IWL<1757> A_IWL<1756> A_IWL<1755> A_IWL<1754> A_IWL<1753> A_IWL<1752> A_IWL<1751> A_IWL<1750> A_IWL<1749> A_IWL<1748> A_IWL<1747> A_IWL<1746> A_IWL<1745> A_IWL<1744> A_IWL<1743> A_IWL<1742> A_IWL<1741> A_IWL<1740> A_IWL<1739> A_IWL<1738> A_IWL<1737> A_IWL<1736> A_IWL<1735> A_IWL<1734> A_IWL<1733> A_IWL<1732> A_IWL<1731> A_IWL<1730> A_IWL<1729> A_IWL<1728> A_IWL<1727> A_IWL<1726> A_IWL<1725> A_IWL<1724> A_IWL<1723> A_IWL<1722> A_IWL<1721> A_IWL<1720> A_IWL<1719> A_IWL<1718> A_IWL<1717> A_IWL<1716> A_IWL<1715> A_IWL<1714> A_IWL<1713> A_IWL<1712> A_IWL<1711> A_IWL<1710> A_IWL<1709> A_IWL<1708> A_IWL<1707> A_IWL<1706> A_IWL<1705> A_IWL<1704> A_IWL<1703> A_IWL<1702> A_IWL<1701> A_IWL<1700> A_IWL<1699> A_IWL<1698> A_IWL<1697> A_IWL<1696> A_IWL<1695> A_IWL<1694> A_IWL<1693> A_IWL<1692> A_IWL<1691> A_IWL<1690> A_IWL<1689> A_IWL<1688> A_IWL<1687> A_IWL<1686> A_IWL<1685> A_IWL<1684> A_IWL<1683> A_IWL<1682> A_IWL<1681> A_IWL<1680> A_IWL<1679> A_IWL<1678> A_IWL<1677> A_IWL<1676> A_IWL<1675> A_IWL<1674> A_IWL<1673> A_IWL<1672> A_IWL<1671> A_IWL<1670> A_IWL<1669> A_IWL<1668> A_IWL<1667> A_IWL<1666> A_IWL<1665> A_IWL<1664> A_IWL<1663> A_IWL<1662> A_IWL<1661> A_IWL<1660> A_IWL<1659> A_IWL<1658> A_IWL<1657> A_IWL<1656> A_IWL<1655> A_IWL<1654> A_IWL<1653> A_IWL<1652> A_IWL<1651> A_IWL<1650> A_IWL<1649> A_IWL<1648> A_IWL<1647> A_IWL<1646> A_IWL<1645> A_IWL<1644> A_IWL<1643> A_IWL<1642> A_IWL<1641> A_IWL<1640> A_IWL<1639> A_IWL<1638> A_IWL<1637> A_IWL<1636> A_IWL<1635> A_IWL<1634> A_IWL<1633> A_IWL<1632> A_IWL<1631> A_IWL<1630> A_IWL<1629> A_IWL<1628> A_IWL<1627> A_IWL<1626> A_IWL<1625> A_IWL<1624> A_IWL<1623> A_IWL<1622> A_IWL<1621> A_IWL<1620> A_IWL<1619> A_IWL<1618> A_IWL<1617> A_IWL<1616> A_IWL<1615> A_IWL<1614> A_IWL<1613> A_IWL<1612> A_IWL<1611> A_IWL<1610> A_IWL<1609> A_IWL<1608> A_IWL<1607> A_IWL<1606> A_IWL<1605> A_IWL<1604> A_IWL<1603> A_IWL<1602> A_IWL<1601> A_IWL<1600> A_IWL<1599> A_IWL<1598> A_IWL<1597> A_IWL<1596> A_IWL<1595> A_IWL<1594> A_IWL<1593> A_IWL<1592> A_IWL<1591> A_IWL<1590> A_IWL<1589> A_IWL<1588> A_IWL<1587> A_IWL<1586> A_IWL<1585> A_IWL<1584> A_IWL<1583> A_IWL<1582> A_IWL<1581> A_IWL<1580> A_IWL<1579> A_IWL<1578> A_IWL<1577> A_IWL<1576> A_IWL<1575> A_IWL<1574> A_IWL<1573> A_IWL<1572> A_IWL<1571> A_IWL<1570> A_IWL<1569> A_IWL<1568> A_IWL<1567> A_IWL<1566> A_IWL<1565> A_IWL<1564> A_IWL<1563> A_IWL<1562> A_IWL<1561> A_IWL<1560> A_IWL<1559> A_IWL<1558> A_IWL<1557> A_IWL<1556> A_IWL<1555> A_IWL<1554> A_IWL<1553> A_IWL<1552> A_IWL<1551> A_IWL<1550> A_IWL<1549> A_IWL<1548> A_IWL<1547> A_IWL<1546> A_IWL<1545> A_IWL<1544> A_IWL<1543> A_IWL<1542> A_IWL<1541> A_IWL<1540> A_IWL<1539> A_IWL<1538> A_IWL<1537> A_IWL<1536> VDD_CORE VSS / RM_IHPSG13_8192x32_c4_1P_COLUMN_pcell_0 +XCOL<2> A_BLC<5> A_BLC<4> A_BLC_TOP<5> A_BLC_TOP<4> A_BLT<5> A_BLT<4> A_BLT_TOP<5> A_BLT_TOP<4> A_IWL<1023> A_IWL<1022> A_IWL<1021> A_IWL<1020> A_IWL<1019> A_IWL<1018> A_IWL<1017> A_IWL<1016> A_IWL<1015> A_IWL<1014> A_IWL<1013> A_IWL<1012> A_IWL<1011> A_IWL<1010> A_IWL<1009> A_IWL<1008> A_IWL<1007> A_IWL<1006> A_IWL<1005> A_IWL<1004> A_IWL<1003> A_IWL<1002> A_IWL<1001> A_IWL<1000> A_IWL<999> A_IWL<998> A_IWL<997> A_IWL<996> A_IWL<995> A_IWL<994> A_IWL<993> A_IWL<992> A_IWL<991> A_IWL<990> A_IWL<989> A_IWL<988> A_IWL<987> A_IWL<986> A_IWL<985> A_IWL<984> A_IWL<983> A_IWL<982> A_IWL<981> A_IWL<980> A_IWL<979> A_IWL<978> A_IWL<977> A_IWL<976> A_IWL<975> A_IWL<974> A_IWL<973> A_IWL<972> A_IWL<971> A_IWL<970> A_IWL<969> A_IWL<968> A_IWL<967> A_IWL<966> A_IWL<965> A_IWL<964> A_IWL<963> A_IWL<962> A_IWL<961> A_IWL<960> A_IWL<959> A_IWL<958> A_IWL<957> A_IWL<956> A_IWL<955> A_IWL<954> A_IWL<953> A_IWL<952> A_IWL<951> A_IWL<950> A_IWL<949> A_IWL<948> A_IWL<947> A_IWL<946> A_IWL<945> A_IWL<944> A_IWL<943> A_IWL<942> A_IWL<941> A_IWL<940> A_IWL<939> A_IWL<938> A_IWL<937> A_IWL<936> A_IWL<935> A_IWL<934> A_IWL<933> A_IWL<932> A_IWL<931> A_IWL<930> A_IWL<929> A_IWL<928> A_IWL<927> A_IWL<926> A_IWL<925> A_IWL<924> A_IWL<923> A_IWL<922> A_IWL<921> A_IWL<920> A_IWL<919> A_IWL<918> A_IWL<917> A_IWL<916> A_IWL<915> A_IWL<914> A_IWL<913> A_IWL<912> A_IWL<911> A_IWL<910> A_IWL<909> A_IWL<908> A_IWL<907> A_IWL<906> A_IWL<905> A_IWL<904> A_IWL<903> A_IWL<902> A_IWL<901> A_IWL<900> A_IWL<899> A_IWL<898> A_IWL<897> A_IWL<896> A_IWL<895> A_IWL<894> A_IWL<893> A_IWL<892> A_IWL<891> A_IWL<890> A_IWL<889> A_IWL<888> A_IWL<887> A_IWL<886> A_IWL<885> A_IWL<884> A_IWL<883> A_IWL<882> A_IWL<881> A_IWL<880> A_IWL<879> A_IWL<878> A_IWL<877> A_IWL<876> A_IWL<875> A_IWL<874> A_IWL<873> A_IWL<872> A_IWL<871> A_IWL<870> A_IWL<869> A_IWL<868> A_IWL<867> A_IWL<866> A_IWL<865> A_IWL<864> A_IWL<863> A_IWL<862> A_IWL<861> A_IWL<860> A_IWL<859> A_IWL<858> A_IWL<857> A_IWL<856> A_IWL<855> A_IWL<854> A_IWL<853> A_IWL<852> A_IWL<851> A_IWL<850> A_IWL<849> A_IWL<848> A_IWL<847> A_IWL<846> A_IWL<845> A_IWL<844> A_IWL<843> A_IWL<842> A_IWL<841> A_IWL<840> A_IWL<839> A_IWL<838> A_IWL<837> A_IWL<836> A_IWL<835> A_IWL<834> A_IWL<833> A_IWL<832> A_IWL<831> A_IWL<830> A_IWL<829> A_IWL<828> A_IWL<827> A_IWL<826> A_IWL<825> A_IWL<824> A_IWL<823> A_IWL<822> A_IWL<821> A_IWL<820> A_IWL<819> A_IWL<818> A_IWL<817> A_IWL<816> A_IWL<815> A_IWL<814> A_IWL<813> A_IWL<812> A_IWL<811> A_IWL<810> A_IWL<809> A_IWL<808> A_IWL<807> A_IWL<806> A_IWL<805> A_IWL<804> A_IWL<803> A_IWL<802> A_IWL<801> A_IWL<800> A_IWL<799> A_IWL<798> A_IWL<797> A_IWL<796> A_IWL<795> A_IWL<794> A_IWL<793> A_IWL<792> A_IWL<791> A_IWL<790> A_IWL<789> A_IWL<788> A_IWL<787> A_IWL<786> A_IWL<785> A_IWL<784> A_IWL<783> A_IWL<782> A_IWL<781> A_IWL<780> A_IWL<779> A_IWL<778> A_IWL<777> A_IWL<776> A_IWL<775> A_IWL<774> A_IWL<773> A_IWL<772> A_IWL<771> A_IWL<770> A_IWL<769> A_IWL<768> A_IWL<767> A_IWL<766> A_IWL<765> A_IWL<764> A_IWL<763> A_IWL<762> A_IWL<761> A_IWL<760> A_IWL<759> A_IWL<758> A_IWL<757> A_IWL<756> A_IWL<755> A_IWL<754> A_IWL<753> A_IWL<752> A_IWL<751> A_IWL<750> A_IWL<749> A_IWL<748> A_IWL<747> A_IWL<746> A_IWL<745> A_IWL<744> A_IWL<743> A_IWL<742> A_IWL<741> A_IWL<740> A_IWL<739> A_IWL<738> A_IWL<737> A_IWL<736> A_IWL<735> A_IWL<734> A_IWL<733> A_IWL<732> A_IWL<731> A_IWL<730> A_IWL<729> A_IWL<728> A_IWL<727> A_IWL<726> A_IWL<725> A_IWL<724> A_IWL<723> A_IWL<722> A_IWL<721> A_IWL<720> A_IWL<719> A_IWL<718> A_IWL<717> A_IWL<716> A_IWL<715> A_IWL<714> A_IWL<713> A_IWL<712> A_IWL<711> A_IWL<710> A_IWL<709> A_IWL<708> A_IWL<707> A_IWL<706> A_IWL<705> A_IWL<704> A_IWL<703> A_IWL<702> A_IWL<701> A_IWL<700> A_IWL<699> A_IWL<698> A_IWL<697> A_IWL<696> A_IWL<695> A_IWL<694> A_IWL<693> A_IWL<692> A_IWL<691> A_IWL<690> A_IWL<689> A_IWL<688> A_IWL<687> A_IWL<686> A_IWL<685> A_IWL<684> A_IWL<683> A_IWL<682> A_IWL<681> A_IWL<680> A_IWL<679> A_IWL<678> A_IWL<677> A_IWL<676> A_IWL<675> A_IWL<674> A_IWL<673> A_IWL<672> A_IWL<671> A_IWL<670> A_IWL<669> A_IWL<668> A_IWL<667> A_IWL<666> A_IWL<665> A_IWL<664> A_IWL<663> A_IWL<662> A_IWL<661> A_IWL<660> A_IWL<659> A_IWL<658> A_IWL<657> A_IWL<656> A_IWL<655> A_IWL<654> A_IWL<653> A_IWL<652> A_IWL<651> A_IWL<650> A_IWL<649> A_IWL<648> A_IWL<647> A_IWL<646> A_IWL<645> A_IWL<644> A_IWL<643> A_IWL<642> A_IWL<641> A_IWL<640> A_IWL<639> A_IWL<638> A_IWL<637> A_IWL<636> A_IWL<635> A_IWL<634> A_IWL<633> A_IWL<632> A_IWL<631> A_IWL<630> A_IWL<629> A_IWL<628> A_IWL<627> A_IWL<626> A_IWL<625> A_IWL<624> A_IWL<623> A_IWL<622> A_IWL<621> A_IWL<620> A_IWL<619> A_IWL<618> A_IWL<617> A_IWL<616> A_IWL<615> A_IWL<614> A_IWL<613> A_IWL<612> A_IWL<611> A_IWL<610> A_IWL<609> A_IWL<608> A_IWL<607> A_IWL<606> A_IWL<605> A_IWL<604> A_IWL<603> A_IWL<602> A_IWL<601> A_IWL<600> A_IWL<599> A_IWL<598> A_IWL<597> A_IWL<596> A_IWL<595> A_IWL<594> A_IWL<593> A_IWL<592> A_IWL<591> A_IWL<590> A_IWL<589> A_IWL<588> A_IWL<587> A_IWL<586> A_IWL<585> A_IWL<584> A_IWL<583> A_IWL<582> A_IWL<581> A_IWL<580> A_IWL<579> A_IWL<578> A_IWL<577> A_IWL<576> A_IWL<575> A_IWL<574> A_IWL<573> A_IWL<572> A_IWL<571> A_IWL<570> A_IWL<569> A_IWL<568> A_IWL<567> A_IWL<566> A_IWL<565> A_IWL<564> A_IWL<563> A_IWL<562> A_IWL<561> A_IWL<560> A_IWL<559> A_IWL<558> A_IWL<557> A_IWL<556> A_IWL<555> A_IWL<554> A_IWL<553> A_IWL<552> A_IWL<551> A_IWL<550> A_IWL<549> A_IWL<548> A_IWL<547> A_IWL<546> A_IWL<545> A_IWL<544> A_IWL<543> A_IWL<542> A_IWL<541> A_IWL<540> A_IWL<539> A_IWL<538> A_IWL<537> A_IWL<536> A_IWL<535> A_IWL<534> A_IWL<533> A_IWL<532> A_IWL<531> A_IWL<530> A_IWL<529> A_IWL<528> A_IWL<527> A_IWL<526> A_IWL<525> A_IWL<524> A_IWL<523> A_IWL<522> A_IWL<521> A_IWL<520> A_IWL<519> A_IWL<518> A_IWL<517> A_IWL<516> A_IWL<515> A_IWL<514> A_IWL<513> A_IWL<512> A_IWL<1535> A_IWL<1534> A_IWL<1533> A_IWL<1532> A_IWL<1531> A_IWL<1530> A_IWL<1529> A_IWL<1528> A_IWL<1527> A_IWL<1526> A_IWL<1525> A_IWL<1524> A_IWL<1523> A_IWL<1522> A_IWL<1521> A_IWL<1520> A_IWL<1519> A_IWL<1518> A_IWL<1517> A_IWL<1516> A_IWL<1515> A_IWL<1514> A_IWL<1513> A_IWL<1512> A_IWL<1511> A_IWL<1510> A_IWL<1509> A_IWL<1508> A_IWL<1507> A_IWL<1506> A_IWL<1505> A_IWL<1504> A_IWL<1503> A_IWL<1502> A_IWL<1501> A_IWL<1500> A_IWL<1499> A_IWL<1498> A_IWL<1497> A_IWL<1496> A_IWL<1495> A_IWL<1494> A_IWL<1493> A_IWL<1492> A_IWL<1491> A_IWL<1490> A_IWL<1489> A_IWL<1488> A_IWL<1487> A_IWL<1486> A_IWL<1485> A_IWL<1484> A_IWL<1483> A_IWL<1482> A_IWL<1481> A_IWL<1480> A_IWL<1479> A_IWL<1478> A_IWL<1477> A_IWL<1476> A_IWL<1475> A_IWL<1474> A_IWL<1473> A_IWL<1472> A_IWL<1471> A_IWL<1470> A_IWL<1469> A_IWL<1468> A_IWL<1467> A_IWL<1466> A_IWL<1465> A_IWL<1464> A_IWL<1463> A_IWL<1462> A_IWL<1461> A_IWL<1460> A_IWL<1459> A_IWL<1458> A_IWL<1457> A_IWL<1456> A_IWL<1455> A_IWL<1454> A_IWL<1453> A_IWL<1452> A_IWL<1451> A_IWL<1450> A_IWL<1449> A_IWL<1448> A_IWL<1447> A_IWL<1446> A_IWL<1445> A_IWL<1444> A_IWL<1443> A_IWL<1442> A_IWL<1441> A_IWL<1440> A_IWL<1439> A_IWL<1438> A_IWL<1437> A_IWL<1436> A_IWL<1435> A_IWL<1434> A_IWL<1433> A_IWL<1432> A_IWL<1431> A_IWL<1430> A_IWL<1429> A_IWL<1428> A_IWL<1427> A_IWL<1426> A_IWL<1425> A_IWL<1424> A_IWL<1423> A_IWL<1422> A_IWL<1421> A_IWL<1420> A_IWL<1419> A_IWL<1418> A_IWL<1417> A_IWL<1416> A_IWL<1415> A_IWL<1414> A_IWL<1413> A_IWL<1412> A_IWL<1411> A_IWL<1410> A_IWL<1409> A_IWL<1408> A_IWL<1407> A_IWL<1406> A_IWL<1405> A_IWL<1404> A_IWL<1403> A_IWL<1402> A_IWL<1401> A_IWL<1400> A_IWL<1399> A_IWL<1398> A_IWL<1397> A_IWL<1396> A_IWL<1395> A_IWL<1394> A_IWL<1393> A_IWL<1392> A_IWL<1391> A_IWL<1390> A_IWL<1389> A_IWL<1388> A_IWL<1387> A_IWL<1386> A_IWL<1385> A_IWL<1384> A_IWL<1383> A_IWL<1382> A_IWL<1381> A_IWL<1380> A_IWL<1379> A_IWL<1378> A_IWL<1377> A_IWL<1376> A_IWL<1375> A_IWL<1374> A_IWL<1373> A_IWL<1372> A_IWL<1371> A_IWL<1370> A_IWL<1369> A_IWL<1368> A_IWL<1367> A_IWL<1366> A_IWL<1365> A_IWL<1364> A_IWL<1363> A_IWL<1362> A_IWL<1361> A_IWL<1360> A_IWL<1359> A_IWL<1358> A_IWL<1357> A_IWL<1356> A_IWL<1355> A_IWL<1354> A_IWL<1353> A_IWL<1352> A_IWL<1351> A_IWL<1350> A_IWL<1349> A_IWL<1348> A_IWL<1347> A_IWL<1346> A_IWL<1345> A_IWL<1344> A_IWL<1343> A_IWL<1342> A_IWL<1341> A_IWL<1340> A_IWL<1339> A_IWL<1338> A_IWL<1337> A_IWL<1336> A_IWL<1335> A_IWL<1334> A_IWL<1333> A_IWL<1332> A_IWL<1331> A_IWL<1330> A_IWL<1329> A_IWL<1328> A_IWL<1327> A_IWL<1326> A_IWL<1325> A_IWL<1324> A_IWL<1323> A_IWL<1322> A_IWL<1321> A_IWL<1320> A_IWL<1319> A_IWL<1318> A_IWL<1317> A_IWL<1316> A_IWL<1315> A_IWL<1314> A_IWL<1313> A_IWL<1312> A_IWL<1311> A_IWL<1310> A_IWL<1309> A_IWL<1308> A_IWL<1307> A_IWL<1306> A_IWL<1305> A_IWL<1304> A_IWL<1303> A_IWL<1302> A_IWL<1301> A_IWL<1300> A_IWL<1299> A_IWL<1298> A_IWL<1297> A_IWL<1296> A_IWL<1295> A_IWL<1294> A_IWL<1293> A_IWL<1292> A_IWL<1291> A_IWL<1290> A_IWL<1289> A_IWL<1288> A_IWL<1287> A_IWL<1286> A_IWL<1285> A_IWL<1284> A_IWL<1283> A_IWL<1282> A_IWL<1281> A_IWL<1280> A_IWL<1279> A_IWL<1278> A_IWL<1277> A_IWL<1276> A_IWL<1275> A_IWL<1274> A_IWL<1273> A_IWL<1272> A_IWL<1271> A_IWL<1270> A_IWL<1269> A_IWL<1268> A_IWL<1267> A_IWL<1266> A_IWL<1265> A_IWL<1264> A_IWL<1263> A_IWL<1262> A_IWL<1261> A_IWL<1260> A_IWL<1259> A_IWL<1258> A_IWL<1257> A_IWL<1256> A_IWL<1255> A_IWL<1254> A_IWL<1253> A_IWL<1252> A_IWL<1251> A_IWL<1250> A_IWL<1249> A_IWL<1248> A_IWL<1247> A_IWL<1246> A_IWL<1245> A_IWL<1244> A_IWL<1243> A_IWL<1242> A_IWL<1241> A_IWL<1240> A_IWL<1239> A_IWL<1238> A_IWL<1237> A_IWL<1236> A_IWL<1235> A_IWL<1234> A_IWL<1233> A_IWL<1232> A_IWL<1231> A_IWL<1230> A_IWL<1229> A_IWL<1228> A_IWL<1227> A_IWL<1226> A_IWL<1225> A_IWL<1224> A_IWL<1223> A_IWL<1222> A_IWL<1221> A_IWL<1220> A_IWL<1219> A_IWL<1218> A_IWL<1217> A_IWL<1216> A_IWL<1215> A_IWL<1214> A_IWL<1213> A_IWL<1212> A_IWL<1211> A_IWL<1210> A_IWL<1209> A_IWL<1208> A_IWL<1207> A_IWL<1206> A_IWL<1205> A_IWL<1204> A_IWL<1203> A_IWL<1202> A_IWL<1201> A_IWL<1200> A_IWL<1199> A_IWL<1198> A_IWL<1197> A_IWL<1196> A_IWL<1195> A_IWL<1194> A_IWL<1193> A_IWL<1192> A_IWL<1191> A_IWL<1190> A_IWL<1189> A_IWL<1188> A_IWL<1187> A_IWL<1186> A_IWL<1185> A_IWL<1184> A_IWL<1183> A_IWL<1182> A_IWL<1181> A_IWL<1180> A_IWL<1179> A_IWL<1178> A_IWL<1177> A_IWL<1176> A_IWL<1175> A_IWL<1174> A_IWL<1173> A_IWL<1172> A_IWL<1171> A_IWL<1170> A_IWL<1169> A_IWL<1168> A_IWL<1167> A_IWL<1166> A_IWL<1165> A_IWL<1164> A_IWL<1163> A_IWL<1162> A_IWL<1161> A_IWL<1160> A_IWL<1159> A_IWL<1158> A_IWL<1157> A_IWL<1156> A_IWL<1155> A_IWL<1154> A_IWL<1153> A_IWL<1152> A_IWL<1151> A_IWL<1150> A_IWL<1149> A_IWL<1148> A_IWL<1147> A_IWL<1146> A_IWL<1145> A_IWL<1144> A_IWL<1143> A_IWL<1142> A_IWL<1141> A_IWL<1140> A_IWL<1139> A_IWL<1138> A_IWL<1137> A_IWL<1136> A_IWL<1135> A_IWL<1134> A_IWL<1133> A_IWL<1132> A_IWL<1131> A_IWL<1130> A_IWL<1129> A_IWL<1128> A_IWL<1127> A_IWL<1126> A_IWL<1125> A_IWL<1124> A_IWL<1123> A_IWL<1122> A_IWL<1121> A_IWL<1120> A_IWL<1119> A_IWL<1118> A_IWL<1117> A_IWL<1116> A_IWL<1115> A_IWL<1114> A_IWL<1113> A_IWL<1112> A_IWL<1111> A_IWL<1110> A_IWL<1109> A_IWL<1108> A_IWL<1107> A_IWL<1106> A_IWL<1105> A_IWL<1104> A_IWL<1103> A_IWL<1102> A_IWL<1101> A_IWL<1100> A_IWL<1099> A_IWL<1098> A_IWL<1097> A_IWL<1096> A_IWL<1095> A_IWL<1094> A_IWL<1093> A_IWL<1092> A_IWL<1091> A_IWL<1090> A_IWL<1089> A_IWL<1088> A_IWL<1087> A_IWL<1086> A_IWL<1085> A_IWL<1084> A_IWL<1083> A_IWL<1082> A_IWL<1081> A_IWL<1080> A_IWL<1079> A_IWL<1078> A_IWL<1077> A_IWL<1076> A_IWL<1075> A_IWL<1074> A_IWL<1073> A_IWL<1072> A_IWL<1071> A_IWL<1070> A_IWL<1069> A_IWL<1068> A_IWL<1067> A_IWL<1066> A_IWL<1065> A_IWL<1064> A_IWL<1063> A_IWL<1062> A_IWL<1061> A_IWL<1060> A_IWL<1059> A_IWL<1058> A_IWL<1057> A_IWL<1056> A_IWL<1055> A_IWL<1054> A_IWL<1053> A_IWL<1052> A_IWL<1051> A_IWL<1050> A_IWL<1049> A_IWL<1048> A_IWL<1047> A_IWL<1046> A_IWL<1045> A_IWL<1044> A_IWL<1043> A_IWL<1042> A_IWL<1041> A_IWL<1040> A_IWL<1039> A_IWL<1038> A_IWL<1037> A_IWL<1036> A_IWL<1035> A_IWL<1034> A_IWL<1033> A_IWL<1032> A_IWL<1031> A_IWL<1030> A_IWL<1029> A_IWL<1028> A_IWL<1027> A_IWL<1026> A_IWL<1025> A_IWL<1024> VDD_CORE VSS / RM_IHPSG13_8192x32_c4_1P_COLUMN_pcell_0 +XCOL<1> A_BLC<3> A_BLC<2> A_BLC_TOP<3> A_BLC_TOP<2> A_BLT<3> A_BLT<2> A_BLT_TOP<3> A_BLT_TOP<2> A_IWL<511> A_IWL<510> A_IWL<509> A_IWL<508> A_IWL<507> A_IWL<506> A_IWL<505> A_IWL<504> A_IWL<503> A_IWL<502> A_IWL<501> A_IWL<500> A_IWL<499> A_IWL<498> A_IWL<497> A_IWL<496> A_IWL<495> A_IWL<494> A_IWL<493> A_IWL<492> A_IWL<491> A_IWL<490> A_IWL<489> A_IWL<488> A_IWL<487> A_IWL<486> A_IWL<485> A_IWL<484> A_IWL<483> A_IWL<482> A_IWL<481> A_IWL<480> A_IWL<479> A_IWL<478> A_IWL<477> A_IWL<476> A_IWL<475> A_IWL<474> A_IWL<473> A_IWL<472> A_IWL<471> A_IWL<470> A_IWL<469> A_IWL<468> A_IWL<467> A_IWL<466> A_IWL<465> A_IWL<464> A_IWL<463> A_IWL<462> A_IWL<461> A_IWL<460> A_IWL<459> A_IWL<458> A_IWL<457> A_IWL<456> A_IWL<455> A_IWL<454> A_IWL<453> A_IWL<452> A_IWL<451> A_IWL<450> A_IWL<449> A_IWL<448> A_IWL<447> A_IWL<446> A_IWL<445> A_IWL<444> A_IWL<443> A_IWL<442> A_IWL<441> A_IWL<440> A_IWL<439> A_IWL<438> A_IWL<437> A_IWL<436> A_IWL<435> A_IWL<434> A_IWL<433> A_IWL<432> A_IWL<431> A_IWL<430> A_IWL<429> A_IWL<428> A_IWL<427> A_IWL<426> A_IWL<425> A_IWL<424> A_IWL<423> A_IWL<422> A_IWL<421> A_IWL<420> A_IWL<419> A_IWL<418> A_IWL<417> A_IWL<416> A_IWL<415> A_IWL<414> A_IWL<413> A_IWL<412> A_IWL<411> A_IWL<410> A_IWL<409> A_IWL<408> A_IWL<407> A_IWL<406> A_IWL<405> A_IWL<404> A_IWL<403> A_IWL<402> A_IWL<401> A_IWL<400> A_IWL<399> A_IWL<398> A_IWL<397> A_IWL<396> A_IWL<395> A_IWL<394> A_IWL<393> A_IWL<392> A_IWL<391> A_IWL<390> A_IWL<389> A_IWL<388> A_IWL<387> A_IWL<386> A_IWL<385> A_IWL<384> A_IWL<383> A_IWL<382> A_IWL<381> A_IWL<380> A_IWL<379> A_IWL<378> A_IWL<377> A_IWL<376> A_IWL<375> A_IWL<374> A_IWL<373> A_IWL<372> A_IWL<371> A_IWL<370> A_IWL<369> A_IWL<368> A_IWL<367> A_IWL<366> A_IWL<365> A_IWL<364> A_IWL<363> A_IWL<362> A_IWL<361> A_IWL<360> A_IWL<359> A_IWL<358> A_IWL<357> A_IWL<356> A_IWL<355> A_IWL<354> A_IWL<353> A_IWL<352> A_IWL<351> A_IWL<350> A_IWL<349> A_IWL<348> A_IWL<347> A_IWL<346> A_IWL<345> A_IWL<344> A_IWL<343> A_IWL<342> A_IWL<341> A_IWL<340> A_IWL<339> A_IWL<338> A_IWL<337> A_IWL<336> A_IWL<335> A_IWL<334> A_IWL<333> A_IWL<332> A_IWL<331> A_IWL<330> A_IWL<329> A_IWL<328> A_IWL<327> A_IWL<326> A_IWL<325> A_IWL<324> A_IWL<323> A_IWL<322> A_IWL<321> A_IWL<320> A_IWL<319> A_IWL<318> A_IWL<317> A_IWL<316> A_IWL<315> A_IWL<314> A_IWL<313> A_IWL<312> A_IWL<311> A_IWL<310> A_IWL<309> A_IWL<308> A_IWL<307> A_IWL<306> A_IWL<305> A_IWL<304> A_IWL<303> A_IWL<302> A_IWL<301> A_IWL<300> A_IWL<299> A_IWL<298> A_IWL<297> A_IWL<296> A_IWL<295> A_IWL<294> A_IWL<293> A_IWL<292> A_IWL<291> A_IWL<290> A_IWL<289> A_IWL<288> A_IWL<287> A_IWL<286> A_IWL<285> A_IWL<284> A_IWL<283> A_IWL<282> A_IWL<281> A_IWL<280> A_IWL<279> A_IWL<278> A_IWL<277> A_IWL<276> A_IWL<275> A_IWL<274> A_IWL<273> A_IWL<272> A_IWL<271> A_IWL<270> A_IWL<269> A_IWL<268> A_IWL<267> A_IWL<266> A_IWL<265> A_IWL<264> A_IWL<263> A_IWL<262> A_IWL<261> A_IWL<260> A_IWL<259> A_IWL<258> A_IWL<257> A_IWL<256> A_IWL<255> A_IWL<254> A_IWL<253> A_IWL<252> A_IWL<251> A_IWL<250> A_IWL<249> A_IWL<248> A_IWL<247> A_IWL<246> A_IWL<245> A_IWL<244> A_IWL<243> A_IWL<242> A_IWL<241> A_IWL<240> A_IWL<239> A_IWL<238> A_IWL<237> A_IWL<236> A_IWL<235> A_IWL<234> A_IWL<233> A_IWL<232> A_IWL<231> A_IWL<230> A_IWL<229> A_IWL<228> A_IWL<227> A_IWL<226> A_IWL<225> A_IWL<224> A_IWL<223> A_IWL<222> A_IWL<221> A_IWL<220> A_IWL<219> A_IWL<218> A_IWL<217> A_IWL<216> A_IWL<215> A_IWL<214> A_IWL<213> A_IWL<212> A_IWL<211> A_IWL<210> A_IWL<209> A_IWL<208> A_IWL<207> A_IWL<206> A_IWL<205> A_IWL<204> A_IWL<203> A_IWL<202> A_IWL<201> A_IWL<200> A_IWL<199> A_IWL<198> A_IWL<197> A_IWL<196> A_IWL<195> A_IWL<194> A_IWL<193> A_IWL<192> A_IWL<191> A_IWL<190> A_IWL<189> A_IWL<188> A_IWL<187> A_IWL<186> A_IWL<185> A_IWL<184> A_IWL<183> A_IWL<182> A_IWL<181> A_IWL<180> A_IWL<179> A_IWL<178> A_IWL<177> A_IWL<176> A_IWL<175> A_IWL<174> A_IWL<173> A_IWL<172> A_IWL<171> A_IWL<170> A_IWL<169> A_IWL<168> A_IWL<167> A_IWL<166> A_IWL<165> A_IWL<164> A_IWL<163> A_IWL<162> A_IWL<161> A_IWL<160> A_IWL<159> A_IWL<158> A_IWL<157> A_IWL<156> A_IWL<155> A_IWL<154> A_IWL<153> A_IWL<152> A_IWL<151> A_IWL<150> A_IWL<149> A_IWL<148> A_IWL<147> A_IWL<146> A_IWL<145> A_IWL<144> A_IWL<143> A_IWL<142> A_IWL<141> A_IWL<140> A_IWL<139> A_IWL<138> A_IWL<137> A_IWL<136> A_IWL<135> A_IWL<134> A_IWL<133> A_IWL<132> A_IWL<131> A_IWL<130> A_IWL<129> A_IWL<128> A_IWL<127> A_IWL<126> A_IWL<125> A_IWL<124> A_IWL<123> A_IWL<122> A_IWL<121> A_IWL<120> A_IWL<119> A_IWL<118> A_IWL<117> A_IWL<116> A_IWL<115> A_IWL<114> A_IWL<113> A_IWL<112> A_IWL<111> A_IWL<110> A_IWL<109> A_IWL<108> A_IWL<107> A_IWL<106> A_IWL<105> A_IWL<104> A_IWL<103> A_IWL<102> A_IWL<101> A_IWL<100> A_IWL<99> A_IWL<98> A_IWL<97> A_IWL<96> A_IWL<95> A_IWL<94> A_IWL<93> A_IWL<92> A_IWL<91> A_IWL<90> A_IWL<89> A_IWL<88> A_IWL<87> A_IWL<86> A_IWL<85> A_IWL<84> A_IWL<83> A_IWL<82> A_IWL<81> A_IWL<80> A_IWL<79> A_IWL<78> A_IWL<77> A_IWL<76> A_IWL<75> A_IWL<74> A_IWL<73> A_IWL<72> A_IWL<71> A_IWL<70> A_IWL<69> A_IWL<68> A_IWL<67> A_IWL<66> A_IWL<65> A_IWL<64> A_IWL<63> A_IWL<62> A_IWL<61> A_IWL<60> A_IWL<59> A_IWL<58> A_IWL<57> A_IWL<56> A_IWL<55> A_IWL<54> A_IWL<53> A_IWL<52> A_IWL<51> A_IWL<50> A_IWL<49> A_IWL<48> A_IWL<47> A_IWL<46> A_IWL<45> A_IWL<44> A_IWL<43> A_IWL<42> A_IWL<41> A_IWL<40> A_IWL<39> A_IWL<38> A_IWL<37> A_IWL<36> A_IWL<35> A_IWL<34> A_IWL<33> A_IWL<32> A_IWL<31> A_IWL<30> A_IWL<29> A_IWL<28> A_IWL<27> A_IWL<26> A_IWL<25> A_IWL<24> A_IWL<23> A_IWL<22> A_IWL<21> A_IWL<20> A_IWL<19> A_IWL<18> A_IWL<17> A_IWL<16> A_IWL<15> A_IWL<14> A_IWL<13> A_IWL<12> A_IWL<11> A_IWL<10> A_IWL<9> A_IWL<8> A_IWL<7> A_IWL<6> A_IWL<5> A_IWL<4> A_IWL<3> A_IWL<2> A_IWL<1> A_IWL<0> A_IWL<1023> A_IWL<1022> A_IWL<1021> A_IWL<1020> A_IWL<1019> A_IWL<1018> A_IWL<1017> A_IWL<1016> A_IWL<1015> A_IWL<1014> A_IWL<1013> A_IWL<1012> A_IWL<1011> A_IWL<1010> A_IWL<1009> A_IWL<1008> A_IWL<1007> A_IWL<1006> A_IWL<1005> A_IWL<1004> A_IWL<1003> A_IWL<1002> A_IWL<1001> A_IWL<1000> A_IWL<999> A_IWL<998> A_IWL<997> A_IWL<996> A_IWL<995> A_IWL<994> A_IWL<993> A_IWL<992> A_IWL<991> A_IWL<990> A_IWL<989> A_IWL<988> A_IWL<987> A_IWL<986> A_IWL<985> A_IWL<984> A_IWL<983> A_IWL<982> A_IWL<981> A_IWL<980> A_IWL<979> A_IWL<978> A_IWL<977> A_IWL<976> A_IWL<975> A_IWL<974> A_IWL<973> A_IWL<972> A_IWL<971> A_IWL<970> A_IWL<969> A_IWL<968> A_IWL<967> A_IWL<966> A_IWL<965> A_IWL<964> A_IWL<963> A_IWL<962> A_IWL<961> A_IWL<960> A_IWL<959> A_IWL<958> A_IWL<957> A_IWL<956> A_IWL<955> A_IWL<954> A_IWL<953> A_IWL<952> A_IWL<951> A_IWL<950> A_IWL<949> A_IWL<948> A_IWL<947> A_IWL<946> A_IWL<945> A_IWL<944> A_IWL<943> A_IWL<942> A_IWL<941> A_IWL<940> A_IWL<939> A_IWL<938> A_IWL<937> A_IWL<936> A_IWL<935> A_IWL<934> A_IWL<933> A_IWL<932> A_IWL<931> A_IWL<930> A_IWL<929> A_IWL<928> A_IWL<927> A_IWL<926> A_IWL<925> A_IWL<924> A_IWL<923> A_IWL<922> A_IWL<921> A_IWL<920> A_IWL<919> A_IWL<918> A_IWL<917> A_IWL<916> A_IWL<915> A_IWL<914> A_IWL<913> A_IWL<912> A_IWL<911> A_IWL<910> A_IWL<909> A_IWL<908> A_IWL<907> A_IWL<906> A_IWL<905> A_IWL<904> A_IWL<903> A_IWL<902> A_IWL<901> A_IWL<900> A_IWL<899> A_IWL<898> A_IWL<897> A_IWL<896> A_IWL<895> A_IWL<894> A_IWL<893> A_IWL<892> A_IWL<891> A_IWL<890> A_IWL<889> A_IWL<888> A_IWL<887> A_IWL<886> A_IWL<885> A_IWL<884> A_IWL<883> A_IWL<882> A_IWL<881> A_IWL<880> A_IWL<879> A_IWL<878> A_IWL<877> A_IWL<876> A_IWL<875> A_IWL<874> A_IWL<873> A_IWL<872> A_IWL<871> A_IWL<870> A_IWL<869> A_IWL<868> A_IWL<867> A_IWL<866> A_IWL<865> A_IWL<864> A_IWL<863> A_IWL<862> A_IWL<861> A_IWL<860> A_IWL<859> A_IWL<858> A_IWL<857> A_IWL<856> A_IWL<855> A_IWL<854> A_IWL<853> A_IWL<852> A_IWL<851> A_IWL<850> A_IWL<849> A_IWL<848> A_IWL<847> A_IWL<846> A_IWL<845> A_IWL<844> A_IWL<843> A_IWL<842> A_IWL<841> A_IWL<840> A_IWL<839> A_IWL<838> A_IWL<837> A_IWL<836> A_IWL<835> A_IWL<834> A_IWL<833> A_IWL<832> A_IWL<831> A_IWL<830> A_IWL<829> A_IWL<828> A_IWL<827> A_IWL<826> A_IWL<825> A_IWL<824> A_IWL<823> A_IWL<822> A_IWL<821> A_IWL<820> A_IWL<819> A_IWL<818> A_IWL<817> A_IWL<816> A_IWL<815> A_IWL<814> A_IWL<813> A_IWL<812> A_IWL<811> A_IWL<810> A_IWL<809> A_IWL<808> A_IWL<807> A_IWL<806> A_IWL<805> A_IWL<804> A_IWL<803> A_IWL<802> A_IWL<801> A_IWL<800> A_IWL<799> A_IWL<798> A_IWL<797> A_IWL<796> A_IWL<795> A_IWL<794> A_IWL<793> A_IWL<792> A_IWL<791> A_IWL<790> A_IWL<789> A_IWL<788> A_IWL<787> A_IWL<786> A_IWL<785> A_IWL<784> A_IWL<783> A_IWL<782> A_IWL<781> A_IWL<780> A_IWL<779> A_IWL<778> A_IWL<777> A_IWL<776> A_IWL<775> A_IWL<774> A_IWL<773> A_IWL<772> A_IWL<771> A_IWL<770> A_IWL<769> A_IWL<768> A_IWL<767> A_IWL<766> A_IWL<765> A_IWL<764> A_IWL<763> A_IWL<762> A_IWL<761> A_IWL<760> A_IWL<759> A_IWL<758> A_IWL<757> A_IWL<756> A_IWL<755> A_IWL<754> A_IWL<753> A_IWL<752> A_IWL<751> A_IWL<750> A_IWL<749> A_IWL<748> A_IWL<747> A_IWL<746> A_IWL<745> A_IWL<744> A_IWL<743> A_IWL<742> A_IWL<741> A_IWL<740> A_IWL<739> A_IWL<738> A_IWL<737> A_IWL<736> A_IWL<735> A_IWL<734> A_IWL<733> A_IWL<732> A_IWL<731> A_IWL<730> A_IWL<729> A_IWL<728> A_IWL<727> A_IWL<726> A_IWL<725> A_IWL<724> A_IWL<723> A_IWL<722> A_IWL<721> A_IWL<720> A_IWL<719> A_IWL<718> A_IWL<717> A_IWL<716> A_IWL<715> A_IWL<714> A_IWL<713> A_IWL<712> A_IWL<711> A_IWL<710> A_IWL<709> A_IWL<708> A_IWL<707> A_IWL<706> A_IWL<705> A_IWL<704> A_IWL<703> A_IWL<702> A_IWL<701> A_IWL<700> A_IWL<699> A_IWL<698> A_IWL<697> A_IWL<696> A_IWL<695> A_IWL<694> A_IWL<693> A_IWL<692> A_IWL<691> A_IWL<690> A_IWL<689> A_IWL<688> A_IWL<687> A_IWL<686> A_IWL<685> A_IWL<684> A_IWL<683> A_IWL<682> A_IWL<681> A_IWL<680> A_IWL<679> A_IWL<678> A_IWL<677> A_IWL<676> A_IWL<675> A_IWL<674> A_IWL<673> A_IWL<672> A_IWL<671> A_IWL<670> A_IWL<669> A_IWL<668> A_IWL<667> A_IWL<666> A_IWL<665> A_IWL<664> A_IWL<663> A_IWL<662> A_IWL<661> A_IWL<660> A_IWL<659> A_IWL<658> A_IWL<657> A_IWL<656> A_IWL<655> A_IWL<654> A_IWL<653> A_IWL<652> A_IWL<651> A_IWL<650> A_IWL<649> A_IWL<648> A_IWL<647> A_IWL<646> A_IWL<645> A_IWL<644> A_IWL<643> A_IWL<642> A_IWL<641> A_IWL<640> A_IWL<639> A_IWL<638> A_IWL<637> A_IWL<636> A_IWL<635> A_IWL<634> A_IWL<633> A_IWL<632> A_IWL<631> A_IWL<630> A_IWL<629> A_IWL<628> A_IWL<627> A_IWL<626> A_IWL<625> A_IWL<624> A_IWL<623> A_IWL<622> A_IWL<621> A_IWL<620> A_IWL<619> A_IWL<618> A_IWL<617> A_IWL<616> A_IWL<615> A_IWL<614> A_IWL<613> A_IWL<612> A_IWL<611> A_IWL<610> A_IWL<609> A_IWL<608> A_IWL<607> A_IWL<606> A_IWL<605> A_IWL<604> A_IWL<603> A_IWL<602> A_IWL<601> A_IWL<600> A_IWL<599> A_IWL<598> A_IWL<597> A_IWL<596> A_IWL<595> A_IWL<594> A_IWL<593> A_IWL<592> A_IWL<591> A_IWL<590> A_IWL<589> A_IWL<588> A_IWL<587> A_IWL<586> A_IWL<585> A_IWL<584> A_IWL<583> A_IWL<582> A_IWL<581> A_IWL<580> A_IWL<579> A_IWL<578> A_IWL<577> A_IWL<576> A_IWL<575> A_IWL<574> A_IWL<573> A_IWL<572> A_IWL<571> A_IWL<570> A_IWL<569> A_IWL<568> A_IWL<567> A_IWL<566> A_IWL<565> A_IWL<564> A_IWL<563> A_IWL<562> A_IWL<561> A_IWL<560> A_IWL<559> A_IWL<558> A_IWL<557> A_IWL<556> A_IWL<555> A_IWL<554> A_IWL<553> A_IWL<552> A_IWL<551> A_IWL<550> A_IWL<549> A_IWL<548> A_IWL<547> A_IWL<546> A_IWL<545> A_IWL<544> A_IWL<543> A_IWL<542> A_IWL<541> A_IWL<540> A_IWL<539> A_IWL<538> A_IWL<537> A_IWL<536> A_IWL<535> A_IWL<534> A_IWL<533> A_IWL<532> A_IWL<531> A_IWL<530> A_IWL<529> A_IWL<528> A_IWL<527> A_IWL<526> A_IWL<525> A_IWL<524> A_IWL<523> A_IWL<522> A_IWL<521> A_IWL<520> A_IWL<519> A_IWL<518> A_IWL<517> A_IWL<516> A_IWL<515> A_IWL<514> A_IWL<513> A_IWL<512> VDD_CORE VSS / RM_IHPSG13_8192x32_c4_1P_COLUMN_pcell_0 +XCOL<0> A_BLC<1> A_BLC<0> A_BLC_TOP<1> A_BLC_TOP<0> A_BLT<1> A_BLT<0> A_BLT_TOP<1> A_BLT_TOP<0> A_WL<511> A_WL<510> A_WL<509> A_WL<508> A_WL<507> A_WL<506> A_WL<505> A_WL<504> A_WL<503> A_WL<502> A_WL<501> A_WL<500> A_WL<499> A_WL<498> A_WL<497> A_WL<496> A_WL<495> A_WL<494> A_WL<493> A_WL<492> A_WL<491> A_WL<490> A_WL<489> A_WL<488> A_WL<487> A_WL<486> A_WL<485> A_WL<484> A_WL<483> A_WL<482> A_WL<481> A_WL<480> A_WL<479> A_WL<478> A_WL<477> A_WL<476> A_WL<475> A_WL<474> A_WL<473> A_WL<472> A_WL<471> A_WL<470> A_WL<469> A_WL<468> A_WL<467> A_WL<466> A_WL<465> A_WL<464> A_WL<463> A_WL<462> A_WL<461> A_WL<460> A_WL<459> A_WL<458> A_WL<457> A_WL<456> A_WL<455> A_WL<454> A_WL<453> A_WL<452> A_WL<451> A_WL<450> A_WL<449> A_WL<448> A_WL<447> A_WL<446> A_WL<445> A_WL<444> A_WL<443> A_WL<442> A_WL<441> A_WL<440> A_WL<439> A_WL<438> A_WL<437> A_WL<436> A_WL<435> A_WL<434> A_WL<433> A_WL<432> A_WL<431> A_WL<430> A_WL<429> A_WL<428> A_WL<427> A_WL<426> A_WL<425> A_WL<424> A_WL<423> A_WL<422> A_WL<421> A_WL<420> A_WL<419> A_WL<418> A_WL<417> A_WL<416> A_WL<415> A_WL<414> A_WL<413> A_WL<412> A_WL<411> A_WL<410> A_WL<409> A_WL<408> A_WL<407> A_WL<406> A_WL<405> A_WL<404> A_WL<403> A_WL<402> A_WL<401> A_WL<400> A_WL<399> A_WL<398> A_WL<397> A_WL<396> A_WL<395> A_WL<394> A_WL<393> A_WL<392> A_WL<391> A_WL<390> A_WL<389> A_WL<388> A_WL<387> A_WL<386> A_WL<385> A_WL<384> A_WL<383> A_WL<382> A_WL<381> A_WL<380> A_WL<379> A_WL<378> A_WL<377> A_WL<376> A_WL<375> A_WL<374> A_WL<373> A_WL<372> A_WL<371> A_WL<370> A_WL<369> A_WL<368> A_WL<367> A_WL<366> A_WL<365> A_WL<364> A_WL<363> A_WL<362> A_WL<361> A_WL<360> A_WL<359> A_WL<358> A_WL<357> A_WL<356> A_WL<355> A_WL<354> A_WL<353> A_WL<352> A_WL<351> A_WL<350> A_WL<349> A_WL<348> A_WL<347> A_WL<346> A_WL<345> A_WL<344> A_WL<343> A_WL<342> A_WL<341> A_WL<340> A_WL<339> A_WL<338> A_WL<337> A_WL<336> A_WL<335> A_WL<334> A_WL<333> A_WL<332> A_WL<331> A_WL<330> A_WL<329> A_WL<328> A_WL<327> A_WL<326> A_WL<325> A_WL<324> A_WL<323> A_WL<322> A_WL<321> A_WL<320> A_WL<319> A_WL<318> A_WL<317> A_WL<316> A_WL<315> A_WL<314> A_WL<313> A_WL<312> A_WL<311> A_WL<310> A_WL<309> A_WL<308> A_WL<307> A_WL<306> A_WL<305> A_WL<304> A_WL<303> A_WL<302> A_WL<301> A_WL<300> A_WL<299> A_WL<298> A_WL<297> A_WL<296> A_WL<295> A_WL<294> A_WL<293> A_WL<292> A_WL<291> A_WL<290> A_WL<289> A_WL<288> A_WL<287> A_WL<286> A_WL<285> A_WL<284> A_WL<283> A_WL<282> A_WL<281> A_WL<280> A_WL<279> A_WL<278> A_WL<277> A_WL<276> A_WL<275> A_WL<274> A_WL<273> A_WL<272> A_WL<271> A_WL<270> A_WL<269> A_WL<268> A_WL<267> A_WL<266> A_WL<265> A_WL<264> A_WL<263> A_WL<262> A_WL<261> A_WL<260> A_WL<259> A_WL<258> A_WL<257> A_WL<256> A_WL<255> A_WL<254> A_WL<253> A_WL<252> A_WL<251> A_WL<250> A_WL<249> A_WL<248> A_WL<247> A_WL<246> A_WL<245> A_WL<244> A_WL<243> A_WL<242> A_WL<241> A_WL<240> A_WL<239> A_WL<238> A_WL<237> A_WL<236> A_WL<235> A_WL<234> A_WL<233> A_WL<232> A_WL<231> A_WL<230> A_WL<229> A_WL<228> A_WL<227> A_WL<226> A_WL<225> A_WL<224> A_WL<223> A_WL<222> A_WL<221> A_WL<220> A_WL<219> A_WL<218> A_WL<217> A_WL<216> A_WL<215> A_WL<214> A_WL<213> A_WL<212> A_WL<211> A_WL<210> A_WL<209> A_WL<208> A_WL<207> A_WL<206> A_WL<205> A_WL<204> A_WL<203> A_WL<202> A_WL<201> A_WL<200> A_WL<199> A_WL<198> A_WL<197> A_WL<196> A_WL<195> A_WL<194> A_WL<193> A_WL<192> A_WL<191> A_WL<190> A_WL<189> A_WL<188> A_WL<187> A_WL<186> A_WL<185> A_WL<184> A_WL<183> A_WL<182> A_WL<181> A_WL<180> A_WL<179> A_WL<178> A_WL<177> A_WL<176> A_WL<175> A_WL<174> A_WL<173> A_WL<172> A_WL<171> A_WL<170> A_WL<169> A_WL<168> A_WL<167> A_WL<166> A_WL<165> A_WL<164> A_WL<163> A_WL<162> A_WL<161> A_WL<160> A_WL<159> A_WL<158> A_WL<157> A_WL<156> A_WL<155> A_WL<154> A_WL<153> A_WL<152> A_WL<151> A_WL<150> A_WL<149> A_WL<148> A_WL<147> A_WL<146> A_WL<145> A_WL<144> A_WL<143> A_WL<142> A_WL<141> A_WL<140> A_WL<139> A_WL<138> A_WL<137> A_WL<136> A_WL<135> A_WL<134> A_WL<133> A_WL<132> A_WL<131> A_WL<130> A_WL<129> A_WL<128> A_WL<127> A_WL<126> A_WL<125> A_WL<124> A_WL<123> A_WL<122> A_WL<121> A_WL<120> A_WL<119> A_WL<118> A_WL<117> A_WL<116> A_WL<115> A_WL<114> A_WL<113> A_WL<112> A_WL<111> A_WL<110> A_WL<109> A_WL<108> A_WL<107> A_WL<106> A_WL<105> A_WL<104> A_WL<103> A_WL<102> A_WL<101> A_WL<100> A_WL<99> A_WL<98> A_WL<97> A_WL<96> A_WL<95> A_WL<94> A_WL<93> A_WL<92> A_WL<91> A_WL<90> A_WL<89> A_WL<88> A_WL<87> A_WL<86> A_WL<85> A_WL<84> A_WL<83> A_WL<82> A_WL<81> A_WL<80> A_WL<79> A_WL<78> A_WL<77> A_WL<76> A_WL<75> A_WL<74> A_WL<73> A_WL<72> A_WL<71> A_WL<70> A_WL<69> A_WL<68> A_WL<67> A_WL<66> A_WL<65> A_WL<64> A_WL<63> A_WL<62> A_WL<61> A_WL<60> A_WL<59> A_WL<58> A_WL<57> A_WL<56> A_WL<55> A_WL<54> A_WL<53> A_WL<52> A_WL<51> A_WL<50> A_WL<49> A_WL<48> A_WL<47> A_WL<46> A_WL<45> A_WL<44> A_WL<43> A_WL<42> A_WL<41> A_WL<40> A_WL<39> A_WL<38> A_WL<37> A_WL<36> A_WL<35> A_WL<34> A_WL<33> A_WL<32> A_WL<31> A_WL<30> A_WL<29> A_WL<28> A_WL<27> A_WL<26> A_WL<25> A_WL<24> A_WL<23> A_WL<22> A_WL<21> A_WL<20> A_WL<19> A_WL<18> A_WL<17> A_WL<16> A_WL<15> A_WL<14> A_WL<13> A_WL<12> A_WL<11> A_WL<10> A_WL<9> A_WL<8> A_WL<7> A_WL<6> A_WL<5> A_WL<4> A_WL<3> A_WL<2> A_WL<1> A_WL<0> A_IWL<511> A_IWL<510> A_IWL<509> A_IWL<508> A_IWL<507> A_IWL<506> A_IWL<505> A_IWL<504> A_IWL<503> A_IWL<502> A_IWL<501> A_IWL<500> A_IWL<499> A_IWL<498> A_IWL<497> A_IWL<496> A_IWL<495> A_IWL<494> A_IWL<493> A_IWL<492> A_IWL<491> A_IWL<490> A_IWL<489> A_IWL<488> A_IWL<487> A_IWL<486> A_IWL<485> A_IWL<484> A_IWL<483> A_IWL<482> A_IWL<481> A_IWL<480> A_IWL<479> A_IWL<478> A_IWL<477> A_IWL<476> A_IWL<475> A_IWL<474> A_IWL<473> A_IWL<472> A_IWL<471> A_IWL<470> A_IWL<469> A_IWL<468> A_IWL<467> A_IWL<466> A_IWL<465> A_IWL<464> A_IWL<463> A_IWL<462> A_IWL<461> A_IWL<460> A_IWL<459> A_IWL<458> A_IWL<457> A_IWL<456> A_IWL<455> A_IWL<454> A_IWL<453> A_IWL<452> A_IWL<451> A_IWL<450> A_IWL<449> A_IWL<448> A_IWL<447> A_IWL<446> A_IWL<445> A_IWL<444> A_IWL<443> A_IWL<442> A_IWL<441> A_IWL<440> A_IWL<439> A_IWL<438> A_IWL<437> A_IWL<436> A_IWL<435> A_IWL<434> A_IWL<433> A_IWL<432> A_IWL<431> A_IWL<430> A_IWL<429> A_IWL<428> A_IWL<427> A_IWL<426> A_IWL<425> A_IWL<424> A_IWL<423> A_IWL<422> A_IWL<421> A_IWL<420> A_IWL<419> A_IWL<418> A_IWL<417> A_IWL<416> A_IWL<415> A_IWL<414> A_IWL<413> A_IWL<412> A_IWL<411> A_IWL<410> A_IWL<409> A_IWL<408> A_IWL<407> A_IWL<406> A_IWL<405> A_IWL<404> A_IWL<403> A_IWL<402> A_IWL<401> A_IWL<400> A_IWL<399> A_IWL<398> A_IWL<397> A_IWL<396> A_IWL<395> A_IWL<394> A_IWL<393> A_IWL<392> A_IWL<391> A_IWL<390> A_IWL<389> A_IWL<388> A_IWL<387> A_IWL<386> A_IWL<385> A_IWL<384> A_IWL<383> A_IWL<382> A_IWL<381> A_IWL<380> A_IWL<379> A_IWL<378> A_IWL<377> A_IWL<376> A_IWL<375> A_IWL<374> A_IWL<373> A_IWL<372> A_IWL<371> A_IWL<370> A_IWL<369> A_IWL<368> A_IWL<367> A_IWL<366> A_IWL<365> A_IWL<364> A_IWL<363> A_IWL<362> A_IWL<361> A_IWL<360> A_IWL<359> A_IWL<358> A_IWL<357> A_IWL<356> A_IWL<355> A_IWL<354> A_IWL<353> A_IWL<352> A_IWL<351> A_IWL<350> A_IWL<349> A_IWL<348> A_IWL<347> A_IWL<346> A_IWL<345> A_IWL<344> A_IWL<343> A_IWL<342> A_IWL<341> A_IWL<340> A_IWL<339> A_IWL<338> A_IWL<337> A_IWL<336> A_IWL<335> A_IWL<334> A_IWL<333> A_IWL<332> A_IWL<331> A_IWL<330> A_IWL<329> A_IWL<328> A_IWL<327> A_IWL<326> A_IWL<325> A_IWL<324> A_IWL<323> A_IWL<322> A_IWL<321> A_IWL<320> A_IWL<319> A_IWL<318> A_IWL<317> A_IWL<316> A_IWL<315> A_IWL<314> A_IWL<313> A_IWL<312> A_IWL<311> A_IWL<310> A_IWL<309> A_IWL<308> A_IWL<307> A_IWL<306> A_IWL<305> A_IWL<304> A_IWL<303> A_IWL<302> A_IWL<301> A_IWL<300> A_IWL<299> A_IWL<298> A_IWL<297> A_IWL<296> A_IWL<295> A_IWL<294> A_IWL<293> A_IWL<292> A_IWL<291> A_IWL<290> A_IWL<289> A_IWL<288> A_IWL<287> A_IWL<286> A_IWL<285> A_IWL<284> A_IWL<283> A_IWL<282> A_IWL<281> A_IWL<280> A_IWL<279> A_IWL<278> A_IWL<277> A_IWL<276> A_IWL<275> A_IWL<274> A_IWL<273> A_IWL<272> A_IWL<271> A_IWL<270> A_IWL<269> A_IWL<268> A_IWL<267> A_IWL<266> A_IWL<265> A_IWL<264> A_IWL<263> A_IWL<262> A_IWL<261> A_IWL<260> A_IWL<259> A_IWL<258> A_IWL<257> A_IWL<256> A_IWL<255> A_IWL<254> A_IWL<253> A_IWL<252> A_IWL<251> A_IWL<250> A_IWL<249> A_IWL<248> A_IWL<247> A_IWL<246> A_IWL<245> A_IWL<244> A_IWL<243> A_IWL<242> A_IWL<241> A_IWL<240> A_IWL<239> A_IWL<238> A_IWL<237> A_IWL<236> A_IWL<235> A_IWL<234> A_IWL<233> A_IWL<232> A_IWL<231> A_IWL<230> A_IWL<229> A_IWL<228> A_IWL<227> A_IWL<226> A_IWL<225> A_IWL<224> A_IWL<223> A_IWL<222> A_IWL<221> A_IWL<220> A_IWL<219> A_IWL<218> A_IWL<217> A_IWL<216> A_IWL<215> A_IWL<214> A_IWL<213> A_IWL<212> A_IWL<211> A_IWL<210> A_IWL<209> A_IWL<208> A_IWL<207> A_IWL<206> A_IWL<205> A_IWL<204> A_IWL<203> A_IWL<202> A_IWL<201> A_IWL<200> A_IWL<199> A_IWL<198> A_IWL<197> A_IWL<196> A_IWL<195> A_IWL<194> A_IWL<193> A_IWL<192> A_IWL<191> A_IWL<190> A_IWL<189> A_IWL<188> A_IWL<187> A_IWL<186> A_IWL<185> A_IWL<184> A_IWL<183> A_IWL<182> A_IWL<181> A_IWL<180> A_IWL<179> A_IWL<178> A_IWL<177> A_IWL<176> A_IWL<175> A_IWL<174> A_IWL<173> A_IWL<172> A_IWL<171> A_IWL<170> A_IWL<169> A_IWL<168> A_IWL<167> A_IWL<166> A_IWL<165> A_IWL<164> A_IWL<163> A_IWL<162> A_IWL<161> A_IWL<160> A_IWL<159> A_IWL<158> A_IWL<157> A_IWL<156> A_IWL<155> A_IWL<154> A_IWL<153> A_IWL<152> A_IWL<151> A_IWL<150> A_IWL<149> A_IWL<148> A_IWL<147> A_IWL<146> A_IWL<145> A_IWL<144> A_IWL<143> A_IWL<142> A_IWL<141> A_IWL<140> A_IWL<139> A_IWL<138> A_IWL<137> A_IWL<136> A_IWL<135> A_IWL<134> A_IWL<133> A_IWL<132> A_IWL<131> A_IWL<130> A_IWL<129> A_IWL<128> A_IWL<127> A_IWL<126> A_IWL<125> A_IWL<124> A_IWL<123> A_IWL<122> A_IWL<121> A_IWL<120> A_IWL<119> A_IWL<118> A_IWL<117> A_IWL<116> A_IWL<115> A_IWL<114> A_IWL<113> A_IWL<112> A_IWL<111> A_IWL<110> A_IWL<109> A_IWL<108> A_IWL<107> A_IWL<106> A_IWL<105> A_IWL<104> A_IWL<103> A_IWL<102> A_IWL<101> A_IWL<100> A_IWL<99> A_IWL<98> A_IWL<97> A_IWL<96> A_IWL<95> A_IWL<94> A_IWL<93> A_IWL<92> A_IWL<91> A_IWL<90> A_IWL<89> A_IWL<88> A_IWL<87> A_IWL<86> A_IWL<85> A_IWL<84> A_IWL<83> A_IWL<82> A_IWL<81> A_IWL<80> A_IWL<79> A_IWL<78> A_IWL<77> A_IWL<76> A_IWL<75> A_IWL<74> A_IWL<73> A_IWL<72> A_IWL<71> A_IWL<70> A_IWL<69> A_IWL<68> A_IWL<67> A_IWL<66> A_IWL<65> A_IWL<64> A_IWL<63> A_IWL<62> A_IWL<61> A_IWL<60> A_IWL<59> A_IWL<58> A_IWL<57> A_IWL<56> A_IWL<55> A_IWL<54> A_IWL<53> A_IWL<52> A_IWL<51> A_IWL<50> A_IWL<49> A_IWL<48> A_IWL<47> A_IWL<46> A_IWL<45> A_IWL<44> A_IWL<43> A_IWL<42> A_IWL<41> A_IWL<40> A_IWL<39> A_IWL<38> A_IWL<37> A_IWL<36> A_IWL<35> A_IWL<34> A_IWL<33> A_IWL<32> A_IWL<31> A_IWL<30> A_IWL<29> A_IWL<28> A_IWL<27> A_IWL<26> A_IWL<25> A_IWL<24> A_IWL<23> A_IWL<22> A_IWL<21> A_IWL<20> A_IWL<19> A_IWL<18> A_IWL<17> A_IWL<16> A_IWL<15> A_IWL<14> A_IWL<13> A_IWL<12> A_IWL<11> A_IWL<10> A_IWL<9> A_IWL<8> A_IWL<7> A_IWL<6> A_IWL<5> A_IWL<4> A_IWL<3> A_IWL<2> A_IWL<1> A_IWL<0> VDD_CORE VSS / RM_IHPSG13_8192x32_c4_1P_COLUMN_pcell_0 +.ENDS + + + + +.SUBCKT RM_IHPSG13_8192x32_c4_1P_DLY_pcell_2 A Z VDD VSS + XIDL<3> D<7> Z VDD VSS / RSC_IHPSG13_CDLYX1 + XIDL<2> D<6> D<7> VDD VSS / RSC_IHPSG13_CDLYX1 + XIDL<1> D<5> D<6> VDD VSS / RSC_IHPSG13_CDLYX1 + XIDM<5> D<4> D<5> VDD VSS / RSC_IHPSG13_CDLYX1_DUMMY + XIDM<4> D<3> D<4> VDD VSS / RSC_IHPSG13_CDLYX1_DUMMY + XIDM<3> D<2> D<3> VDD VSS / RSC_IHPSG13_CDLYX1_DUMMY + XIDM<2> D<1> D<2> VDD VSS / RSC_IHPSG13_CDLYX1_DUMMY + XIDM<1> A D<1> VDD VSS / RSC_IHPSG13_CDLYX1_DUMMY +.ENDS + + +.SUBCKT RM_IHPSG13_8192x32_c4_1P_DLY_pcell_3 A Z VDD VSS + XIDL<8> D<7> Z VDD VSS / RSC_IHPSG13_CDLYX1 + XIDL<7> D<6> D<7> VDD VSS / RSC_IHPSG13_CDLYX1 + XIDL<6> D<5> D<6> VDD VSS / RSC_IHPSG13_CDLYX1 + XIDL<5> D<4> D<5> VDD VSS / RSC_IHPSG13_CDLYX1 + XIDL<4> D<3> D<4> VDD VSS / RSC_IHPSG13_CDLYX1 + XIDL<3> D<2> D<3> VDD VSS / RSC_IHPSG13_CDLYX1 + XIDL<2> D<1> D<2> VDD VSS / RSC_IHPSG13_CDLYX1 + XIDL<1> A D<1> VDD VSS / RSC_IHPSG13_CDLYX1 +.ENDS + + + +.SUBCKT RM_IHPSG13_1P_8192x32_c4 A_ADDR<12> A_ADDR<11> A_ADDR<10> A_ADDR<9> A_ADDR<8> A_ADDR<7> A_ADDR<6> A_ADDR<5> A_ADDR<4> A_ADDR<3> A_ADDR<2> A_ADDR<1> A_ADDR<0> A_CLK A_DIN<31> A_DIN<30> A_DIN<29> A_DIN<28> A_DIN<27> A_DIN<26> A_DIN<25> A_DIN<24> A_DIN<23> A_DIN<22> A_DIN<21> A_DIN<20> A_DIN<19> A_DIN<18> A_DIN<17> A_DIN<16> A_DIN<15> A_DIN<14> A_DIN<13> A_DIN<12> A_DIN<11> A_DIN<10> A_DIN<9> A_DIN<8> A_DIN<7> A_DIN<6> A_DIN<5> A_DIN<4> A_DIN<3> A_DIN<2> A_DIN<1> A_DIN<0> A_DLY A_DOUT<31> A_DOUT<30> A_DOUT<29> A_DOUT<28> A_DOUT<27> A_DOUT<26> A_DOUT<25> A_DOUT<24> A_DOUT<23> A_DOUT<22> A_DOUT<21> A_DOUT<20> A_DOUT<19> A_DOUT<18> A_DOUT<17> A_DOUT<16> A_DOUT<15> A_DOUT<14> A_DOUT<13> A_DOUT<12> A_DOUT<11> A_DOUT<10> A_DOUT<9> A_DOUT<8> A_DOUT<7> A_DOUT<6> A_DOUT<5> A_DOUT<4> A_DOUT<3> A_DOUT<2> A_DOUT<1> A_DOUT<0> A_MEN A_REN A_WEN VDD! VDDARRAY! VSS! + + +XRAM<1> a_blc_r<255> a_blc_r<254> a_blc_r<253> a_blc_r<252> a_blc_r<251> a_blc_r<250> a_blc_r<249> a_blc_r<248> a_blc_r<247> a_blc_r<246> a_blc_r<245> a_blc_r<244> a_blc_r<243> a_blc_r<242> a_blc_r<241> a_blc_r<240> a_blc_r<239> a_blc_r<238> a_blc_r<237> a_blc_r<236> a_blc_r<235> a_blc_r<234> a_blc_r<233> a_blc_r<232> a_blc_r<231> a_blc_r<230> a_blc_r<229> a_blc_r<228> a_blc_r<227> a_blc_r<226> a_blc_r<225> a_blc_r<224> a_blc_r<223> a_blc_r<222> a_blc_r<221> a_blc_r<220> a_blc_r<219> a_blc_r<218> a_blc_r<217> a_blc_r<216> a_blc_r<215> a_blc_r<214> a_blc_r<213> a_blc_r<212> a_blc_r<211> a_blc_r<210> a_blc_r<209> a_blc_r<208> a_blc_r<207> a_blc_r<206> a_blc_r<205> a_blc_r<204> a_blc_r<203> a_blc_r<202> a_blc_r<201> a_blc_r<200> a_blc_r<199> a_blc_r<198> a_blc_r<197> a_blc_r<196> a_blc_r<195> a_blc_r<194> a_blc_r<193> a_blc_r<192> a_blc_r<191> a_blc_r<190> a_blc_r<189> a_blc_r<188> a_blc_r<187> a_blc_r<186> a_blc_r<185> a_blc_r<184> a_blc_r<183> a_blc_r<182> a_blc_r<181> a_blc_r<180> a_blc_r<179> a_blc_r<178> a_blc_r<177> a_blc_r<176> a_blc_r<175> a_blc_r<174> a_blc_r<173> a_blc_r<172> a_blc_r<171> a_blc_r<170> a_blc_r<169> a_blc_r<168> a_blc_r<167> a_blc_r<166> a_blc_r<165> a_blc_r<164> a_blc_r<163> a_blc_r<162> a_blc_r<161> a_blc_r<160> a_blc_r<159> a_blc_r<158> a_blc_r<157> a_blc_r<156> a_blc_r<155> a_blc_r<154> a_blc_r<153> a_blc_r<152> a_blc_r<151> a_blc_r<150> a_blc_r<149> a_blc_r<148> a_blc_r<147> a_blc_r<146> a_blc_r<145> a_blc_r<144> a_blc_r<143> a_blc_r<142> a_blc_r<141> a_blc_r<140> a_blc_r<139> a_blc_r<138> a_blc_r<137> a_blc_r<136> a_blc_r<135> a_blc_r<134> a_blc_r<133> a_blc_r<132> a_blc_r<131> a_blc_r<130> a_blc_r<129> a_blc_r<128> a_blc_r<127> a_blc_r<126> a_blc_r<125> a_blc_r<124> a_blc_r<123> a_blc_r<122> a_blc_r<121> a_blc_r<120> a_blc_r<119> a_blc_r<118> a_blc_r<117> a_blc_r<116> a_blc_r<115> a_blc_r<114> a_blc_r<113> a_blc_r<112> a_blc_r<111> a_blc_r<110> a_blc_r<109> a_blc_r<108> a_blc_r<107> a_blc_r<106> a_blc_r<105> a_blc_r<104> a_blc_r<103> a_blc_r<102> a_blc_r<101> a_blc_r<100> a_blc_r<99> a_blc_r<98> a_blc_r<97> a_blc_r<96> a_blc_r<95> a_blc_r<94> a_blc_r<93> a_blc_r<92> a_blc_r<91> a_blc_r<90> a_blc_r<89> a_blc_r<88> a_blc_r<87> a_blc_r<86> a_blc_r<85> a_blc_r<84> a_blc_r<83> a_blc_r<82> a_blc_r<81> a_blc_r<80> a_blc_r<79> a_blc_r<78> a_blc_r<77> a_blc_r<76> a_blc_r<75> a_blc_r<74> a_blc_r<73> a_blc_r<72> a_blc_r<71> a_blc_r<70> a_blc_r<69> a_blc_r<68> a_blc_r<67> a_blc_r<66> a_blc_r<65> a_blc_r<64> a_blc_r<63> a_blc_r<62> a_blc_r<61> a_blc_r<60> a_blc_r<59> a_blc_r<58> a_blc_r<57> a_blc_r<56> a_blc_r<55> a_blc_r<54> a_blc_r<53> a_blc_r<52> a_blc_r<51> a_blc_r<50> a_blc_r<49> a_blc_r<48> a_blc_r<47> a_blc_r<46> a_blc_r<45> a_blc_r<44> a_blc_r<43> a_blc_r<42> a_blc_r<41> a_blc_r<40> a_blc_r<39> a_blc_r<38> a_blc_r<37> a_blc_r<36> a_blc_r<35> a_blc_r<34> a_blc_r<33> a_blc_r<32> a_blc_r<31> a_blc_r<30> a_blc_r<29> a_blc_r<28> a_blc_r<27> a_blc_r<26> a_blc_r<25> a_blc_r<24> a_blc_r<23> a_blc_r<22> a_blc_r<21> a_blc_r<20> a_blc_r<19> a_blc_r<18> a_blc_r<17> a_blc_r<16> a_blc_r<15> a_blc_r<14> a_blc_r<13> a_blc_r<12> a_blc_r<11> a_blc_r<10> a_blc_r<9> a_blc_r<8> a_blc_r<7> a_blc_r<6> a_blc_r<5> a_blc_r<4> a_blc_r<3> a_blc_r<2> a_blc_r<1> a_blc_r<0> a_blt_r<255> a_blt_r<254> a_blt_r<253> a_blt_r<252> a_blt_r<251> a_blt_r<250> a_blt_r<249> a_blt_r<248> a_blt_r<247> a_blt_r<246> a_blt_r<245> a_blt_r<244> a_blt_r<243> a_blt_r<242> a_blt_r<241> a_blt_r<240> a_blt_r<239> a_blt_r<238> a_blt_r<237> a_blt_r<236> a_blt_r<235> a_blt_r<234> a_blt_r<233> a_blt_r<232> a_blt_r<231> a_blt_r<230> a_blt_r<229> a_blt_r<228> a_blt_r<227> a_blt_r<226> a_blt_r<225> a_blt_r<224> a_blt_r<223> a_blt_r<222> a_blt_r<221> a_blt_r<220> a_blt_r<219> a_blt_r<218> a_blt_r<217> a_blt_r<216> a_blt_r<215> a_blt_r<214> a_blt_r<213> a_blt_r<212> a_blt_r<211> a_blt_r<210> a_blt_r<209> a_blt_r<208> a_blt_r<207> a_blt_r<206> a_blt_r<205> a_blt_r<204> a_blt_r<203> a_blt_r<202> a_blt_r<201> a_blt_r<200> a_blt_r<199> a_blt_r<198> a_blt_r<197> a_blt_r<196> a_blt_r<195> a_blt_r<194> a_blt_r<193> a_blt_r<192> a_blt_r<191> a_blt_r<190> a_blt_r<189> a_blt_r<188> a_blt_r<187> a_blt_r<186> a_blt_r<185> a_blt_r<184> a_blt_r<183> a_blt_r<182> a_blt_r<181> a_blt_r<180> a_blt_r<179> a_blt_r<178> a_blt_r<177> a_blt_r<176> a_blt_r<175> a_blt_r<174> a_blt_r<173> a_blt_r<172> a_blt_r<171> a_blt_r<170> a_blt_r<169> a_blt_r<168> a_blt_r<167> a_blt_r<166> a_blt_r<165> a_blt_r<164> a_blt_r<163> a_blt_r<162> a_blt_r<161> a_blt_r<160> a_blt_r<159> a_blt_r<158> a_blt_r<157> a_blt_r<156> a_blt_r<155> a_blt_r<154> a_blt_r<153> a_blt_r<152> a_blt_r<151> a_blt_r<150> a_blt_r<149> a_blt_r<148> a_blt_r<147> a_blt_r<146> a_blt_r<145> a_blt_r<144> a_blt_r<143> a_blt_r<142> a_blt_r<141> a_blt_r<140> a_blt_r<139> a_blt_r<138> a_blt_r<137> a_blt_r<136> a_blt_r<135> a_blt_r<134> a_blt_r<133> a_blt_r<132> a_blt_r<131> a_blt_r<130> a_blt_r<129> a_blt_r<128> a_blt_r<127> a_blt_r<126> a_blt_r<125> a_blt_r<124> a_blt_r<123> a_blt_r<122> a_blt_r<121> a_blt_r<120> a_blt_r<119> a_blt_r<118> a_blt_r<117> a_blt_r<116> a_blt_r<115> a_blt_r<114> a_blt_r<113> a_blt_r<112> a_blt_r<111> a_blt_r<110> a_blt_r<109> a_blt_r<108> a_blt_r<107> a_blt_r<106> a_blt_r<105> a_blt_r<104> a_blt_r<103> a_blt_r<102> a_blt_r<101> a_blt_r<100> a_blt_r<99> a_blt_r<98> a_blt_r<97> a_blt_r<96> a_blt_r<95> a_blt_r<94> a_blt_r<93> a_blt_r<92> a_blt_r<91> a_blt_r<90> a_blt_r<89> a_blt_r<88> a_blt_r<87> a_blt_r<86> a_blt_r<85> a_blt_r<84> a_blt_r<83> a_blt_r<82> a_blt_r<81> a_blt_r<80> a_blt_r<79> a_blt_r<78> a_blt_r<77> a_blt_r<76> a_blt_r<75> a_blt_r<74> a_blt_r<73> a_blt_r<72> a_blt_r<71> a_blt_r<70> a_blt_r<69> a_blt_r<68> a_blt_r<67> a_blt_r<66> a_blt_r<65> a_blt_r<64> a_blt_r<63> a_blt_r<62> a_blt_r<61> a_blt_r<60> a_blt_r<59> a_blt_r<58> a_blt_r<57> a_blt_r<56> a_blt_r<55> a_blt_r<54> a_blt_r<53> a_blt_r<52> a_blt_r<51> a_blt_r<50> a_blt_r<49> a_blt_r<48> a_blt_r<47> a_blt_r<46> a_blt_r<45> a_blt_r<44> a_blt_r<43> a_blt_r<42> a_blt_r<41> a_blt_r<40> a_blt_r<39> a_blt_r<38> a_blt_r<37> a_blt_r<36> a_blt_r<35> a_blt_r<34> a_blt_r<33> a_blt_r<32> a_blt_r<31> a_blt_r<30> a_blt_r<29> a_blt_r<28> a_blt_r<27> a_blt_r<26> a_blt_r<25> a_blt_r<24> a_blt_r<23> a_blt_r<22> a_blt_r<21> a_blt_r<20> a_blt_r<19> a_blt_r<18> a_blt_r<17> a_blt_r<16> a_blt_r<15> a_blt_r<14> a_blt_r<13> a_blt_r<12> a_blt_r<11> a_blt_r<10> a_blt_r<9> a_blt_r<8> a_blt_r<7> a_blt_r<6> a_blt_r<5> a_blt_r<4> a_blt_r<3> a_blt_r<2> a_blt_r<1> a_blt_r<0> a_wl_r<511> a_wl_r<510> a_wl_r<509> a_wl_r<508> a_wl_r<507> a_wl_r<506> a_wl_r<505> a_wl_r<504> a_wl_r<503> a_wl_r<502> a_wl_r<501> a_wl_r<500> a_wl_r<499> a_wl_r<498> a_wl_r<497> a_wl_r<496> a_wl_r<495> a_wl_r<494> a_wl_r<493> a_wl_r<492> a_wl_r<491> a_wl_r<490> a_wl_r<489> a_wl_r<488> a_wl_r<487> a_wl_r<486> a_wl_r<485> a_wl_r<484> a_wl_r<483> a_wl_r<482> a_wl_r<481> a_wl_r<480> a_wl_r<479> a_wl_r<478> a_wl_r<477> a_wl_r<476> a_wl_r<475> a_wl_r<474> a_wl_r<473> a_wl_r<472> a_wl_r<471> a_wl_r<470> a_wl_r<469> a_wl_r<468> a_wl_r<467> a_wl_r<466> a_wl_r<465> a_wl_r<464> a_wl_r<463> a_wl_r<462> a_wl_r<461> a_wl_r<460> a_wl_r<459> a_wl_r<458> a_wl_r<457> a_wl_r<456> a_wl_r<455> a_wl_r<454> a_wl_r<453> a_wl_r<452> a_wl_r<451> a_wl_r<450> a_wl_r<449> a_wl_r<448> a_wl_r<447> a_wl_r<446> a_wl_r<445> a_wl_r<444> a_wl_r<443> a_wl_r<442> a_wl_r<441> a_wl_r<440> a_wl_r<439> a_wl_r<438> a_wl_r<437> a_wl_r<436> a_wl_r<435> a_wl_r<434> a_wl_r<433> a_wl_r<432> a_wl_r<431> a_wl_r<430> a_wl_r<429> a_wl_r<428> a_wl_r<427> a_wl_r<426> a_wl_r<425> a_wl_r<424> a_wl_r<423> a_wl_r<422> a_wl_r<421> a_wl_r<420> a_wl_r<419> a_wl_r<418> a_wl_r<417> a_wl_r<416> a_wl_r<415> a_wl_r<414> a_wl_r<413> a_wl_r<412> a_wl_r<411> a_wl_r<410> a_wl_r<409> a_wl_r<408> a_wl_r<407> a_wl_r<406> a_wl_r<405> a_wl_r<404> a_wl_r<403> a_wl_r<402> a_wl_r<401> a_wl_r<400> a_wl_r<399> a_wl_r<398> a_wl_r<397> a_wl_r<396> a_wl_r<395> a_wl_r<394> a_wl_r<393> a_wl_r<392> a_wl_r<391> a_wl_r<390> a_wl_r<389> a_wl_r<388> a_wl_r<387> a_wl_r<386> a_wl_r<385> a_wl_r<384> a_wl_r<383> a_wl_r<382> a_wl_r<381> a_wl_r<380> a_wl_r<379> a_wl_r<378> a_wl_r<377> a_wl_r<376> a_wl_r<375> a_wl_r<374> a_wl_r<373> a_wl_r<372> a_wl_r<371> a_wl_r<370> a_wl_r<369> a_wl_r<368> a_wl_r<367> a_wl_r<366> a_wl_r<365> a_wl_r<364> a_wl_r<363> a_wl_r<362> a_wl_r<361> a_wl_r<360> a_wl_r<359> a_wl_r<358> a_wl_r<357> a_wl_r<356> a_wl_r<355> a_wl_r<354> a_wl_r<353> a_wl_r<352> a_wl_r<351> a_wl_r<350> a_wl_r<349> a_wl_r<348> a_wl_r<347> a_wl_r<346> a_wl_r<345> a_wl_r<344> a_wl_r<343> a_wl_r<342> a_wl_r<341> a_wl_r<340> a_wl_r<339> a_wl_r<338> a_wl_r<337> a_wl_r<336> a_wl_r<335> a_wl_r<334> a_wl_r<333> a_wl_r<332> a_wl_r<331> a_wl_r<330> a_wl_r<329> a_wl_r<328> a_wl_r<327> a_wl_r<326> a_wl_r<325> a_wl_r<324> a_wl_r<323> a_wl_r<322> a_wl_r<321> a_wl_r<320> a_wl_r<319> a_wl_r<318> a_wl_r<317> a_wl_r<316> a_wl_r<315> a_wl_r<314> a_wl_r<313> a_wl_r<312> a_wl_r<311> a_wl_r<310> a_wl_r<309> a_wl_r<308> a_wl_r<307> a_wl_r<306> a_wl_r<305> a_wl_r<304> a_wl_r<303> a_wl_r<302> a_wl_r<301> a_wl_r<300> a_wl_r<299> a_wl_r<298> a_wl_r<297> a_wl_r<296> a_wl_r<295> a_wl_r<294> a_wl_r<293> a_wl_r<292> a_wl_r<291> a_wl_r<290> a_wl_r<289> a_wl_r<288> a_wl_r<287> a_wl_r<286> a_wl_r<285> a_wl_r<284> a_wl_r<283> a_wl_r<282> a_wl_r<281> a_wl_r<280> a_wl_r<279> a_wl_r<278> a_wl_r<277> a_wl_r<276> a_wl_r<275> a_wl_r<274> a_wl_r<273> a_wl_r<272> a_wl_r<271> a_wl_r<270> a_wl_r<269> a_wl_r<268> a_wl_r<267> a_wl_r<266> a_wl_r<265> a_wl_r<264> a_wl_r<263> a_wl_r<262> a_wl_r<261> a_wl_r<260> a_wl_r<259> a_wl_r<258> a_wl_r<257> a_wl_r<256> a_wl_r<255> a_wl_r<254> a_wl_r<253> a_wl_r<252> a_wl_r<251> a_wl_r<250> a_wl_r<249> a_wl_r<248> a_wl_r<247> a_wl_r<246> a_wl_r<245> a_wl_r<244> a_wl_r<243> a_wl_r<242> a_wl_r<241> a_wl_r<240> a_wl_r<239> a_wl_r<238> a_wl_r<237> a_wl_r<236> a_wl_r<235> a_wl_r<234> a_wl_r<233> a_wl_r<232> a_wl_r<231> a_wl_r<230> a_wl_r<229> a_wl_r<228> a_wl_r<227> a_wl_r<226> a_wl_r<225> a_wl_r<224> a_wl_r<223> a_wl_r<222> a_wl_r<221> a_wl_r<220> a_wl_r<219> a_wl_r<218> a_wl_r<217> a_wl_r<216> a_wl_r<215> a_wl_r<214> a_wl_r<213> a_wl_r<212> a_wl_r<211> a_wl_r<210> a_wl_r<209> a_wl_r<208> a_wl_r<207> a_wl_r<206> a_wl_r<205> a_wl_r<204> a_wl_r<203> a_wl_r<202> a_wl_r<201> a_wl_r<200> a_wl_r<199> a_wl_r<198> a_wl_r<197> a_wl_r<196> a_wl_r<195> a_wl_r<194> a_wl_r<193> a_wl_r<192> a_wl_r<191> a_wl_r<190> a_wl_r<189> a_wl_r<188> a_wl_r<187> a_wl_r<186> a_wl_r<185> a_wl_r<184> a_wl_r<183> a_wl_r<182> a_wl_r<181> a_wl_r<180> a_wl_r<179> a_wl_r<178> a_wl_r<177> a_wl_r<176> a_wl_r<175> a_wl_r<174> a_wl_r<173> a_wl_r<172> a_wl_r<171> a_wl_r<170> a_wl_r<169> a_wl_r<168> a_wl_r<167> a_wl_r<166> a_wl_r<165> a_wl_r<164> a_wl_r<163> a_wl_r<162> a_wl_r<161> a_wl_r<160> a_wl_r<159> a_wl_r<158> a_wl_r<157> a_wl_r<156> a_wl_r<155> a_wl_r<154> a_wl_r<153> a_wl_r<152> a_wl_r<151> a_wl_r<150> a_wl_r<149> a_wl_r<148> a_wl_r<147> a_wl_r<146> a_wl_r<145> a_wl_r<144> a_wl_r<143> a_wl_r<142> a_wl_r<141> a_wl_r<140> a_wl_r<139> a_wl_r<138> a_wl_r<137> a_wl_r<136> a_wl_r<135> a_wl_r<134> a_wl_r<133> a_wl_r<132> a_wl_r<131> a_wl_r<130> a_wl_r<129> a_wl_r<128> a_wl_r<127> a_wl_r<126> a_wl_r<125> a_wl_r<124> a_wl_r<123> a_wl_r<122> a_wl_r<121> a_wl_r<120> a_wl_r<119> a_wl_r<118> a_wl_r<117> a_wl_r<116> a_wl_r<115> a_wl_r<114> a_wl_r<113> a_wl_r<112> a_wl_r<111> a_wl_r<110> a_wl_r<109> a_wl_r<108> a_wl_r<107> a_wl_r<106> a_wl_r<105> a_wl_r<104> a_wl_r<103> a_wl_r<102> a_wl_r<101> a_wl_r<100> a_wl_r<99> a_wl_r<98> a_wl_r<97> a_wl_r<96> a_wl_r<95> a_wl_r<94> a_wl_r<93> a_wl_r<92> a_wl_r<91> a_wl_r<90> a_wl_r<89> a_wl_r<88> a_wl_r<87> a_wl_r<86> a_wl_r<85> a_wl_r<84> a_wl_r<83> a_wl_r<82> a_wl_r<81> a_wl_r<80> a_wl_r<79> a_wl_r<78> a_wl_r<77> a_wl_r<76> a_wl_r<75> a_wl_r<74> a_wl_r<73> a_wl_r<72> a_wl_r<71> a_wl_r<70> a_wl_r<69> a_wl_r<68> a_wl_r<67> a_wl_r<66> a_wl_r<65> a_wl_r<64> a_wl_r<63> a_wl_r<62> a_wl_r<61> a_wl_r<60> a_wl_r<59> a_wl_r<58> a_wl_r<57> a_wl_r<56> a_wl_r<55> a_wl_r<54> a_wl_r<53> a_wl_r<52> a_wl_r<51> a_wl_r<50> a_wl_r<49> a_wl_r<48> a_wl_r<47> a_wl_r<46> a_wl_r<45> a_wl_r<44> a_wl_r<43> a_wl_r<42> a_wl_r<41> a_wl_r<40> a_wl_r<39> a_wl_r<38> a_wl_r<37> a_wl_r<36> a_wl_r<35> a_wl_r<34> a_wl_r<33> a_wl_r<32> a_wl_r<31> a_wl_r<30> a_wl_r<29> a_wl_r<28> a_wl_r<27> a_wl_r<26> a_wl_r<25> a_wl_r<24> a_wl_r<23> a_wl_r<22> a_wl_r<21> a_wl_r<20> a_wl_r<19> a_wl_r<18> a_wl_r<17> a_wl_r<16> a_wl_r<15> a_wl_r<14> a_wl_r<13> a_wl_r<12> a_wl_r<11> a_wl_r<10> a_wl_r<9> a_wl_r<8> a_wl_r<7> a_wl_r<6> a_wl_r<5> a_wl_r<4> a_wl_r<3> a_wl_r<2> a_wl_r<1> a_wl_r<0> VDDARRAY! VSS! / RM_IHPSG13_8192x32_c4_1P_MATRIX_pcell_1 +XRAM<0> a_blc_l<255> a_blc_l<254> a_blc_l<253> a_blc_l<252> a_blc_l<251> a_blc_l<250> a_blc_l<249> a_blc_l<248> a_blc_l<247> a_blc_l<246> a_blc_l<245> a_blc_l<244> a_blc_l<243> a_blc_l<242> a_blc_l<241> a_blc_l<240> a_blc_l<239> a_blc_l<238> a_blc_l<237> a_blc_l<236> a_blc_l<235> a_blc_l<234> a_blc_l<233> a_blc_l<232> a_blc_l<231> a_blc_l<230> a_blc_l<229> a_blc_l<228> a_blc_l<227> a_blc_l<226> a_blc_l<225> a_blc_l<224> a_blc_l<223> a_blc_l<222> a_blc_l<221> a_blc_l<220> a_blc_l<219> a_blc_l<218> a_blc_l<217> a_blc_l<216> a_blc_l<215> a_blc_l<214> a_blc_l<213> a_blc_l<212> a_blc_l<211> a_blc_l<210> a_blc_l<209> a_blc_l<208> a_blc_l<207> a_blc_l<206> a_blc_l<205> a_blc_l<204> a_blc_l<203> a_blc_l<202> a_blc_l<201> a_blc_l<200> a_blc_l<199> a_blc_l<198> a_blc_l<197> a_blc_l<196> a_blc_l<195> a_blc_l<194> a_blc_l<193> a_blc_l<192> a_blc_l<191> a_blc_l<190> a_blc_l<189> a_blc_l<188> a_blc_l<187> a_blc_l<186> a_blc_l<185> a_blc_l<184> a_blc_l<183> a_blc_l<182> a_blc_l<181> a_blc_l<180> a_blc_l<179> a_blc_l<178> a_blc_l<177> a_blc_l<176> a_blc_l<175> a_blc_l<174> a_blc_l<173> a_blc_l<172> a_blc_l<171> a_blc_l<170> a_blc_l<169> a_blc_l<168> a_blc_l<167> a_blc_l<166> a_blc_l<165> a_blc_l<164> a_blc_l<163> a_blc_l<162> a_blc_l<161> a_blc_l<160> a_blc_l<159> a_blc_l<158> a_blc_l<157> a_blc_l<156> a_blc_l<155> a_blc_l<154> a_blc_l<153> a_blc_l<152> a_blc_l<151> a_blc_l<150> a_blc_l<149> a_blc_l<148> a_blc_l<147> a_blc_l<146> a_blc_l<145> a_blc_l<144> a_blc_l<143> a_blc_l<142> a_blc_l<141> a_blc_l<140> a_blc_l<139> a_blc_l<138> a_blc_l<137> a_blc_l<136> a_blc_l<135> a_blc_l<134> a_blc_l<133> a_blc_l<132> a_blc_l<131> a_blc_l<130> a_blc_l<129> a_blc_l<128> a_blc_l<127> a_blc_l<126> a_blc_l<125> a_blc_l<124> a_blc_l<123> a_blc_l<122> a_blc_l<121> a_blc_l<120> a_blc_l<119> a_blc_l<118> a_blc_l<117> a_blc_l<116> a_blc_l<115> a_blc_l<114> a_blc_l<113> a_blc_l<112> a_blc_l<111> a_blc_l<110> a_blc_l<109> a_blc_l<108> a_blc_l<107> a_blc_l<106> a_blc_l<105> a_blc_l<104> a_blc_l<103> a_blc_l<102> a_blc_l<101> a_blc_l<100> a_blc_l<99> a_blc_l<98> a_blc_l<97> a_blc_l<96> a_blc_l<95> a_blc_l<94> a_blc_l<93> a_blc_l<92> a_blc_l<91> a_blc_l<90> a_blc_l<89> a_blc_l<88> a_blc_l<87> a_blc_l<86> a_blc_l<85> a_blc_l<84> a_blc_l<83> a_blc_l<82> a_blc_l<81> a_blc_l<80> a_blc_l<79> a_blc_l<78> a_blc_l<77> a_blc_l<76> a_blc_l<75> a_blc_l<74> a_blc_l<73> a_blc_l<72> a_blc_l<71> a_blc_l<70> a_blc_l<69> a_blc_l<68> a_blc_l<67> a_blc_l<66> a_blc_l<65> a_blc_l<64> a_blc_l<63> a_blc_l<62> a_blc_l<61> a_blc_l<60> a_blc_l<59> a_blc_l<58> a_blc_l<57> a_blc_l<56> a_blc_l<55> a_blc_l<54> a_blc_l<53> a_blc_l<52> a_blc_l<51> a_blc_l<50> a_blc_l<49> a_blc_l<48> a_blc_l<47> a_blc_l<46> a_blc_l<45> a_blc_l<44> a_blc_l<43> a_blc_l<42> a_blc_l<41> a_blc_l<40> a_blc_l<39> a_blc_l<38> a_blc_l<37> a_blc_l<36> a_blc_l<35> a_blc_l<34> a_blc_l<33> a_blc_l<32> a_blc_l<31> a_blc_l<30> a_blc_l<29> a_blc_l<28> a_blc_l<27> a_blc_l<26> a_blc_l<25> a_blc_l<24> a_blc_l<23> a_blc_l<22> a_blc_l<21> a_blc_l<20> a_blc_l<19> a_blc_l<18> a_blc_l<17> a_blc_l<16> a_blc_l<15> a_blc_l<14> a_blc_l<13> a_blc_l<12> a_blc_l<11> a_blc_l<10> a_blc_l<9> a_blc_l<8> a_blc_l<7> a_blc_l<6> a_blc_l<5> a_blc_l<4> a_blc_l<3> a_blc_l<2> a_blc_l<1> a_blc_l<0> a_blt_l<255> a_blt_l<254> a_blt_l<253> a_blt_l<252> a_blt_l<251> a_blt_l<250> a_blt_l<249> a_blt_l<248> a_blt_l<247> a_blt_l<246> a_blt_l<245> a_blt_l<244> a_blt_l<243> a_blt_l<242> a_blt_l<241> a_blt_l<240> a_blt_l<239> a_blt_l<238> a_blt_l<237> a_blt_l<236> a_blt_l<235> a_blt_l<234> a_blt_l<233> a_blt_l<232> a_blt_l<231> a_blt_l<230> a_blt_l<229> a_blt_l<228> a_blt_l<227> a_blt_l<226> a_blt_l<225> a_blt_l<224> a_blt_l<223> a_blt_l<222> a_blt_l<221> a_blt_l<220> a_blt_l<219> a_blt_l<218> a_blt_l<217> a_blt_l<216> a_blt_l<215> a_blt_l<214> a_blt_l<213> a_blt_l<212> a_blt_l<211> a_blt_l<210> a_blt_l<209> a_blt_l<208> a_blt_l<207> a_blt_l<206> a_blt_l<205> a_blt_l<204> a_blt_l<203> a_blt_l<202> a_blt_l<201> a_blt_l<200> a_blt_l<199> a_blt_l<198> a_blt_l<197> a_blt_l<196> a_blt_l<195> a_blt_l<194> a_blt_l<193> a_blt_l<192> a_blt_l<191> a_blt_l<190> a_blt_l<189> a_blt_l<188> a_blt_l<187> a_blt_l<186> a_blt_l<185> a_blt_l<184> a_blt_l<183> a_blt_l<182> a_blt_l<181> a_blt_l<180> a_blt_l<179> a_blt_l<178> a_blt_l<177> a_blt_l<176> a_blt_l<175> a_blt_l<174> a_blt_l<173> a_blt_l<172> a_blt_l<171> a_blt_l<170> a_blt_l<169> a_blt_l<168> a_blt_l<167> a_blt_l<166> a_blt_l<165> a_blt_l<164> a_blt_l<163> a_blt_l<162> a_blt_l<161> a_blt_l<160> a_blt_l<159> a_blt_l<158> a_blt_l<157> a_blt_l<156> a_blt_l<155> a_blt_l<154> a_blt_l<153> a_blt_l<152> a_blt_l<151> a_blt_l<150> a_blt_l<149> a_blt_l<148> a_blt_l<147> a_blt_l<146> a_blt_l<145> a_blt_l<144> a_blt_l<143> a_blt_l<142> a_blt_l<141> a_blt_l<140> a_blt_l<139> a_blt_l<138> a_blt_l<137> a_blt_l<136> a_blt_l<135> a_blt_l<134> a_blt_l<133> a_blt_l<132> a_blt_l<131> a_blt_l<130> a_blt_l<129> a_blt_l<128> a_blt_l<127> a_blt_l<126> a_blt_l<125> a_blt_l<124> a_blt_l<123> a_blt_l<122> a_blt_l<121> a_blt_l<120> a_blt_l<119> a_blt_l<118> a_blt_l<117> a_blt_l<116> a_blt_l<115> a_blt_l<114> a_blt_l<113> a_blt_l<112> a_blt_l<111> a_blt_l<110> a_blt_l<109> a_blt_l<108> a_blt_l<107> a_blt_l<106> a_blt_l<105> a_blt_l<104> a_blt_l<103> a_blt_l<102> a_blt_l<101> a_blt_l<100> a_blt_l<99> a_blt_l<98> a_blt_l<97> a_blt_l<96> a_blt_l<95> a_blt_l<94> a_blt_l<93> a_blt_l<92> a_blt_l<91> a_blt_l<90> a_blt_l<89> a_blt_l<88> a_blt_l<87> a_blt_l<86> a_blt_l<85> a_blt_l<84> a_blt_l<83> a_blt_l<82> a_blt_l<81> a_blt_l<80> a_blt_l<79> a_blt_l<78> a_blt_l<77> a_blt_l<76> a_blt_l<75> a_blt_l<74> a_blt_l<73> a_blt_l<72> a_blt_l<71> a_blt_l<70> a_blt_l<69> a_blt_l<68> a_blt_l<67> a_blt_l<66> a_blt_l<65> a_blt_l<64> a_blt_l<63> a_blt_l<62> a_blt_l<61> a_blt_l<60> a_blt_l<59> a_blt_l<58> a_blt_l<57> a_blt_l<56> a_blt_l<55> a_blt_l<54> a_blt_l<53> a_blt_l<52> a_blt_l<51> a_blt_l<50> a_blt_l<49> a_blt_l<48> a_blt_l<47> a_blt_l<46> a_blt_l<45> a_blt_l<44> a_blt_l<43> a_blt_l<42> a_blt_l<41> a_blt_l<40> a_blt_l<39> a_blt_l<38> a_blt_l<37> a_blt_l<36> a_blt_l<35> a_blt_l<34> a_blt_l<33> a_blt_l<32> a_blt_l<31> a_blt_l<30> a_blt_l<29> a_blt_l<28> a_blt_l<27> a_blt_l<26> a_blt_l<25> a_blt_l<24> a_blt_l<23> a_blt_l<22> a_blt_l<21> a_blt_l<20> a_blt_l<19> a_blt_l<18> a_blt_l<17> a_blt_l<16> a_blt_l<15> a_blt_l<14> a_blt_l<13> a_blt_l<12> a_blt_l<11> a_blt_l<10> a_blt_l<9> a_blt_l<8> a_blt_l<7> a_blt_l<6> a_blt_l<5> a_blt_l<4> a_blt_l<3> a_blt_l<2> a_blt_l<1> a_blt_l<0> a_wl_l<511> a_wl_l<510> a_wl_l<509> a_wl_l<508> a_wl_l<507> a_wl_l<506> a_wl_l<505> a_wl_l<504> a_wl_l<503> a_wl_l<502> a_wl_l<501> a_wl_l<500> a_wl_l<499> a_wl_l<498> a_wl_l<497> a_wl_l<496> a_wl_l<495> a_wl_l<494> a_wl_l<493> a_wl_l<492> a_wl_l<491> a_wl_l<490> a_wl_l<489> a_wl_l<488> a_wl_l<487> a_wl_l<486> a_wl_l<485> a_wl_l<484> a_wl_l<483> a_wl_l<482> a_wl_l<481> a_wl_l<480> a_wl_l<479> a_wl_l<478> a_wl_l<477> a_wl_l<476> a_wl_l<475> a_wl_l<474> a_wl_l<473> a_wl_l<472> a_wl_l<471> a_wl_l<470> a_wl_l<469> a_wl_l<468> a_wl_l<467> a_wl_l<466> a_wl_l<465> a_wl_l<464> a_wl_l<463> a_wl_l<462> a_wl_l<461> a_wl_l<460> a_wl_l<459> a_wl_l<458> a_wl_l<457> a_wl_l<456> a_wl_l<455> a_wl_l<454> a_wl_l<453> a_wl_l<452> a_wl_l<451> a_wl_l<450> a_wl_l<449> a_wl_l<448> a_wl_l<447> a_wl_l<446> a_wl_l<445> a_wl_l<444> a_wl_l<443> a_wl_l<442> a_wl_l<441> a_wl_l<440> a_wl_l<439> a_wl_l<438> a_wl_l<437> a_wl_l<436> a_wl_l<435> a_wl_l<434> a_wl_l<433> a_wl_l<432> a_wl_l<431> a_wl_l<430> a_wl_l<429> a_wl_l<428> a_wl_l<427> a_wl_l<426> a_wl_l<425> a_wl_l<424> a_wl_l<423> a_wl_l<422> a_wl_l<421> a_wl_l<420> a_wl_l<419> a_wl_l<418> a_wl_l<417> a_wl_l<416> a_wl_l<415> a_wl_l<414> a_wl_l<413> a_wl_l<412> a_wl_l<411> a_wl_l<410> a_wl_l<409> a_wl_l<408> a_wl_l<407> a_wl_l<406> a_wl_l<405> a_wl_l<404> a_wl_l<403> a_wl_l<402> a_wl_l<401> a_wl_l<400> a_wl_l<399> a_wl_l<398> a_wl_l<397> a_wl_l<396> a_wl_l<395> a_wl_l<394> a_wl_l<393> a_wl_l<392> a_wl_l<391> a_wl_l<390> a_wl_l<389> a_wl_l<388> a_wl_l<387> a_wl_l<386> a_wl_l<385> a_wl_l<384> a_wl_l<383> a_wl_l<382> a_wl_l<381> a_wl_l<380> a_wl_l<379> a_wl_l<378> a_wl_l<377> a_wl_l<376> a_wl_l<375> a_wl_l<374> a_wl_l<373> a_wl_l<372> a_wl_l<371> a_wl_l<370> a_wl_l<369> a_wl_l<368> a_wl_l<367> a_wl_l<366> a_wl_l<365> a_wl_l<364> a_wl_l<363> a_wl_l<362> a_wl_l<361> a_wl_l<360> a_wl_l<359> a_wl_l<358> a_wl_l<357> a_wl_l<356> a_wl_l<355> a_wl_l<354> a_wl_l<353> a_wl_l<352> a_wl_l<351> a_wl_l<350> a_wl_l<349> a_wl_l<348> a_wl_l<347> a_wl_l<346> a_wl_l<345> a_wl_l<344> a_wl_l<343> a_wl_l<342> a_wl_l<341> a_wl_l<340> a_wl_l<339> a_wl_l<338> a_wl_l<337> a_wl_l<336> a_wl_l<335> a_wl_l<334> a_wl_l<333> a_wl_l<332> a_wl_l<331> a_wl_l<330> a_wl_l<329> a_wl_l<328> a_wl_l<327> a_wl_l<326> a_wl_l<325> a_wl_l<324> a_wl_l<323> a_wl_l<322> a_wl_l<321> a_wl_l<320> a_wl_l<319> a_wl_l<318> a_wl_l<317> a_wl_l<316> a_wl_l<315> a_wl_l<314> a_wl_l<313> a_wl_l<312> a_wl_l<311> a_wl_l<310> a_wl_l<309> a_wl_l<308> a_wl_l<307> a_wl_l<306> a_wl_l<305> a_wl_l<304> a_wl_l<303> a_wl_l<302> a_wl_l<301> a_wl_l<300> a_wl_l<299> a_wl_l<298> a_wl_l<297> a_wl_l<296> a_wl_l<295> a_wl_l<294> a_wl_l<293> a_wl_l<292> a_wl_l<291> a_wl_l<290> a_wl_l<289> a_wl_l<288> a_wl_l<287> a_wl_l<286> a_wl_l<285> a_wl_l<284> a_wl_l<283> a_wl_l<282> a_wl_l<281> a_wl_l<280> a_wl_l<279> a_wl_l<278> a_wl_l<277> a_wl_l<276> a_wl_l<275> a_wl_l<274> a_wl_l<273> a_wl_l<272> a_wl_l<271> a_wl_l<270> a_wl_l<269> a_wl_l<268> a_wl_l<267> a_wl_l<266> a_wl_l<265> a_wl_l<264> a_wl_l<263> a_wl_l<262> a_wl_l<261> a_wl_l<260> a_wl_l<259> a_wl_l<258> a_wl_l<257> a_wl_l<256> a_wl_l<255> a_wl_l<254> a_wl_l<253> a_wl_l<252> a_wl_l<251> a_wl_l<250> a_wl_l<249> a_wl_l<248> a_wl_l<247> a_wl_l<246> a_wl_l<245> a_wl_l<244> a_wl_l<243> a_wl_l<242> a_wl_l<241> a_wl_l<240> a_wl_l<239> a_wl_l<238> a_wl_l<237> a_wl_l<236> a_wl_l<235> a_wl_l<234> a_wl_l<233> a_wl_l<232> a_wl_l<231> a_wl_l<230> a_wl_l<229> a_wl_l<228> a_wl_l<227> a_wl_l<226> a_wl_l<225> a_wl_l<224> a_wl_l<223> a_wl_l<222> a_wl_l<221> a_wl_l<220> a_wl_l<219> a_wl_l<218> a_wl_l<217> a_wl_l<216> a_wl_l<215> a_wl_l<214> a_wl_l<213> a_wl_l<212> a_wl_l<211> a_wl_l<210> a_wl_l<209> a_wl_l<208> a_wl_l<207> a_wl_l<206> a_wl_l<205> a_wl_l<204> a_wl_l<203> a_wl_l<202> a_wl_l<201> a_wl_l<200> a_wl_l<199> a_wl_l<198> a_wl_l<197> a_wl_l<196> a_wl_l<195> a_wl_l<194> a_wl_l<193> a_wl_l<192> a_wl_l<191> a_wl_l<190> a_wl_l<189> a_wl_l<188> a_wl_l<187> a_wl_l<186> a_wl_l<185> a_wl_l<184> a_wl_l<183> a_wl_l<182> a_wl_l<181> a_wl_l<180> a_wl_l<179> a_wl_l<178> a_wl_l<177> a_wl_l<176> a_wl_l<175> a_wl_l<174> a_wl_l<173> a_wl_l<172> a_wl_l<171> a_wl_l<170> a_wl_l<169> a_wl_l<168> a_wl_l<167> a_wl_l<166> a_wl_l<165> a_wl_l<164> a_wl_l<163> a_wl_l<162> a_wl_l<161> a_wl_l<160> a_wl_l<159> a_wl_l<158> a_wl_l<157> a_wl_l<156> a_wl_l<155> a_wl_l<154> a_wl_l<153> a_wl_l<152> a_wl_l<151> a_wl_l<150> a_wl_l<149> a_wl_l<148> a_wl_l<147> a_wl_l<146> a_wl_l<145> a_wl_l<144> a_wl_l<143> a_wl_l<142> a_wl_l<141> a_wl_l<140> a_wl_l<139> a_wl_l<138> a_wl_l<137> a_wl_l<136> a_wl_l<135> a_wl_l<134> a_wl_l<133> a_wl_l<132> a_wl_l<131> a_wl_l<130> a_wl_l<129> a_wl_l<128> a_wl_l<127> a_wl_l<126> a_wl_l<125> a_wl_l<124> a_wl_l<123> a_wl_l<122> a_wl_l<121> a_wl_l<120> a_wl_l<119> a_wl_l<118> a_wl_l<117> a_wl_l<116> a_wl_l<115> a_wl_l<114> a_wl_l<113> a_wl_l<112> a_wl_l<111> a_wl_l<110> a_wl_l<109> a_wl_l<108> a_wl_l<107> a_wl_l<106> a_wl_l<105> a_wl_l<104> a_wl_l<103> a_wl_l<102> a_wl_l<101> a_wl_l<100> a_wl_l<99> a_wl_l<98> a_wl_l<97> a_wl_l<96> a_wl_l<95> a_wl_l<94> a_wl_l<93> a_wl_l<92> a_wl_l<91> a_wl_l<90> a_wl_l<89> a_wl_l<88> a_wl_l<87> a_wl_l<86> a_wl_l<85> a_wl_l<84> a_wl_l<83> a_wl_l<82> a_wl_l<81> a_wl_l<80> a_wl_l<79> a_wl_l<78> a_wl_l<77> a_wl_l<76> a_wl_l<75> a_wl_l<74> a_wl_l<73> a_wl_l<72> a_wl_l<71> a_wl_l<70> a_wl_l<69> a_wl_l<68> a_wl_l<67> a_wl_l<66> a_wl_l<65> a_wl_l<64> a_wl_l<63> a_wl_l<62> a_wl_l<61> a_wl_l<60> a_wl_l<59> a_wl_l<58> a_wl_l<57> a_wl_l<56> a_wl_l<55> a_wl_l<54> a_wl_l<53> a_wl_l<52> a_wl_l<51> a_wl_l<50> a_wl_l<49> a_wl_l<48> a_wl_l<47> a_wl_l<46> a_wl_l<45> a_wl_l<44> a_wl_l<43> a_wl_l<42> a_wl_l<41> a_wl_l<40> a_wl_l<39> a_wl_l<38> a_wl_l<37> a_wl_l<36> a_wl_l<35> a_wl_l<34> a_wl_l<33> a_wl_l<32> a_wl_l<31> a_wl_l<30> a_wl_l<29> a_wl_l<28> a_wl_l<27> a_wl_l<26> a_wl_l<25> a_wl_l<24> a_wl_l<23> a_wl_l<22> a_wl_l<21> a_wl_l<20> a_wl_l<19> a_wl_l<18> a_wl_l<17> a_wl_l<16> a_wl_l<15> a_wl_l<14> a_wl_l<13> a_wl_l<12> a_wl_l<11> a_wl_l<10> a_wl_l<9> a_wl_l<8> a_wl_l<7> a_wl_l<6> a_wl_l<5> a_wl_l<4> a_wl_l<3> a_wl_l<2> a_wl_l<1> a_wl_l<0> VDDARRAY! VSS! / RM_IHPSG13_8192x32_c4_1P_MATRIX_pcell_1 + + +XA_COLDRV<1> a_addr_col<1> a_addr_col<0> a_addr_col_r<1> a_addr_col_r<0> a_addr_dec<7> a_addr_dec<6> a_addr_dec<5> a_addr_dec<4> a_addr_dec<3> a_addr_dec<2> a_addr_dec<1> a_addr_dec<0> a_addr_dec_r<7> a_addr_dec_r<6> a_addr_dec_r<5> a_addr_dec_r<4> a_addr_dec_r<3> a_addr_dec_r<2> a_addr_dec_r<1> a_addr_dec_r<0> a_dclk a_dclk_p_r<0> a_rclk a_rclk_p_r<0> a_wclk a_wclk_p_r<0> VDD! VSS! / RM_IHPSG13_8192x32_c4_1P_COLDRV13X16 +XA_COLDRV<0> a_addr_col<1> a_addr_col<0> a_addr_col_l<1> a_addr_col_l<0> a_addr_dec<7> a_addr_dec<6> a_addr_dec<5> a_addr_dec<4> a_addr_dec<3> a_addr_dec<2> a_addr_dec<1> a_addr_dec<0> a_addr_dec_l<7> a_addr_dec_l<6> a_addr_dec_l<5> a_addr_dec_l<4> a_addr_dec_l<3> a_addr_dec_l<2> a_addr_dec_l<1> a_addr_dec_l<0> a_dclk a_dclk_p_l<0> a_rclk a_rclk_p_l<0> a_wclk a_wclk_p_l<0> VDD! VSS! / RM_IHPSG13_8192x32_c4_1P_COLDRV13X16 + + +XA_WLDRV<63> a_wi<511> a_wi<510> a_wi<509> a_wi<508> a_wi<507> a_wi<506> a_wi<505> a_wi<504> a_wi<503> a_wi<502> a_wi<501> a_wi<500> a_wi<499> a_wi<498> a_wi<497> a_wi<496> a_wl_r<511> a_wl_r<510> a_wl_r<509> a_wl_r<508> a_wl_r<507> a_wl_r<506> a_wl_r<505> a_wl_r<504> a_wl_r<503> a_wl_r<502> a_wl_r<501> a_wl_r<500> a_wl_r<499> a_wl_r<498> a_wl_r<497> a_wl_r<496> VDD! VSS! / RM_IHPSG13_8192x32_c4_1P_WLDRV16X16 +XA_WLDRV<62> a_wi<495> a_wi<494> a_wi<493> a_wi<492> a_wi<491> a_wi<490> a_wi<489> a_wi<488> a_wi<487> a_wi<486> a_wi<485> a_wi<484> a_wi<483> a_wi<482> a_wi<481> a_wi<480> a_wl_r<495> a_wl_r<494> a_wl_r<493> a_wl_r<492> a_wl_r<491> a_wl_r<490> a_wl_r<489> a_wl_r<488> a_wl_r<487> a_wl_r<486> a_wl_r<485> a_wl_r<484> a_wl_r<483> a_wl_r<482> a_wl_r<481> a_wl_r<480> VDD! VSS! / RM_IHPSG13_8192x32_c4_1P_WLDRV16X16 +XA_WLDRV<61> a_wi<479> a_wi<478> a_wi<477> a_wi<476> a_wi<475> a_wi<474> a_wi<473> a_wi<472> a_wi<471> a_wi<470> a_wi<469> a_wi<468> a_wi<467> a_wi<466> a_wi<465> a_wi<464> a_wl_r<479> a_wl_r<478> a_wl_r<477> a_wl_r<476> a_wl_r<475> a_wl_r<474> a_wl_r<473> a_wl_r<472> a_wl_r<471> a_wl_r<470> a_wl_r<469> a_wl_r<468> a_wl_r<467> a_wl_r<466> a_wl_r<465> a_wl_r<464> VDD! VSS! / RM_IHPSG13_8192x32_c4_1P_WLDRV16X16 +XA_WLDRV<60> a_wi<463> a_wi<462> a_wi<461> a_wi<460> a_wi<459> a_wi<458> a_wi<457> a_wi<456> a_wi<455> a_wi<454> a_wi<453> a_wi<452> a_wi<451> a_wi<450> a_wi<449> a_wi<448> a_wl_r<463> a_wl_r<462> a_wl_r<461> a_wl_r<460> a_wl_r<459> a_wl_r<458> a_wl_r<457> a_wl_r<456> a_wl_r<455> a_wl_r<454> a_wl_r<453> a_wl_r<452> a_wl_r<451> a_wl_r<450> a_wl_r<449> a_wl_r<448> VDD! VSS! / RM_IHPSG13_8192x32_c4_1P_WLDRV16X16 +XA_WLDRV<59> a_wi<447> a_wi<446> a_wi<445> a_wi<444> a_wi<443> a_wi<442> a_wi<441> a_wi<440> a_wi<439> a_wi<438> a_wi<437> a_wi<436> a_wi<435> a_wi<434> a_wi<433> a_wi<432> a_wl_r<447> a_wl_r<446> a_wl_r<445> a_wl_r<444> a_wl_r<443> a_wl_r<442> a_wl_r<441> a_wl_r<440> a_wl_r<439> a_wl_r<438> a_wl_r<437> a_wl_r<436> a_wl_r<435> a_wl_r<434> a_wl_r<433> a_wl_r<432> VDD! VSS! / RM_IHPSG13_8192x32_c4_1P_WLDRV16X16 +XA_WLDRV<58> a_wi<431> a_wi<430> a_wi<429> a_wi<428> a_wi<427> a_wi<426> a_wi<425> a_wi<424> a_wi<423> a_wi<422> a_wi<421> a_wi<420> a_wi<419> a_wi<418> a_wi<417> a_wi<416> a_wl_r<431> a_wl_r<430> a_wl_r<429> a_wl_r<428> a_wl_r<427> a_wl_r<426> a_wl_r<425> a_wl_r<424> a_wl_r<423> a_wl_r<422> a_wl_r<421> a_wl_r<420> a_wl_r<419> a_wl_r<418> a_wl_r<417> a_wl_r<416> VDD! VSS! / RM_IHPSG13_8192x32_c4_1P_WLDRV16X16 +XA_WLDRV<57> a_wi<415> a_wi<414> a_wi<413> a_wi<412> a_wi<411> a_wi<410> a_wi<409> a_wi<408> a_wi<407> a_wi<406> a_wi<405> a_wi<404> a_wi<403> a_wi<402> a_wi<401> a_wi<400> a_wl_r<415> a_wl_r<414> a_wl_r<413> a_wl_r<412> a_wl_r<411> a_wl_r<410> a_wl_r<409> a_wl_r<408> a_wl_r<407> a_wl_r<406> a_wl_r<405> a_wl_r<404> a_wl_r<403> a_wl_r<402> a_wl_r<401> a_wl_r<400> VDD! VSS! / RM_IHPSG13_8192x32_c4_1P_WLDRV16X16 +XA_WLDRV<56> a_wi<399> a_wi<398> a_wi<397> a_wi<396> a_wi<395> a_wi<394> a_wi<393> a_wi<392> a_wi<391> a_wi<390> a_wi<389> a_wi<388> a_wi<387> a_wi<386> a_wi<385> a_wi<384> a_wl_r<399> a_wl_r<398> a_wl_r<397> a_wl_r<396> a_wl_r<395> a_wl_r<394> a_wl_r<393> a_wl_r<392> a_wl_r<391> a_wl_r<390> a_wl_r<389> a_wl_r<388> a_wl_r<387> a_wl_r<386> a_wl_r<385> a_wl_r<384> VDD! VSS! / RM_IHPSG13_8192x32_c4_1P_WLDRV16X16 +XA_WLDRV<55> a_wi<383> a_wi<382> a_wi<381> a_wi<380> a_wi<379> a_wi<378> a_wi<377> a_wi<376> a_wi<375> a_wi<374> a_wi<373> a_wi<372> a_wi<371> a_wi<370> a_wi<369> a_wi<368> a_wl_r<383> a_wl_r<382> a_wl_r<381> a_wl_r<380> a_wl_r<379> a_wl_r<378> a_wl_r<377> a_wl_r<376> a_wl_r<375> a_wl_r<374> a_wl_r<373> a_wl_r<372> a_wl_r<371> a_wl_r<370> a_wl_r<369> a_wl_r<368> VDD! VSS! / RM_IHPSG13_8192x32_c4_1P_WLDRV16X16 +XA_WLDRV<54> a_wi<367> a_wi<366> a_wi<365> a_wi<364> a_wi<363> a_wi<362> a_wi<361> a_wi<360> a_wi<359> a_wi<358> a_wi<357> a_wi<356> a_wi<355> a_wi<354> a_wi<353> a_wi<352> a_wl_r<367> a_wl_r<366> a_wl_r<365> a_wl_r<364> a_wl_r<363> a_wl_r<362> a_wl_r<361> a_wl_r<360> a_wl_r<359> a_wl_r<358> a_wl_r<357> a_wl_r<356> a_wl_r<355> a_wl_r<354> a_wl_r<353> a_wl_r<352> VDD! VSS! / RM_IHPSG13_8192x32_c4_1P_WLDRV16X16 +XA_WLDRV<53> a_wi<351> a_wi<350> a_wi<349> a_wi<348> a_wi<347> a_wi<346> a_wi<345> a_wi<344> a_wi<343> a_wi<342> a_wi<341> a_wi<340> a_wi<339> a_wi<338> a_wi<337> a_wi<336> a_wl_r<351> a_wl_r<350> a_wl_r<349> a_wl_r<348> a_wl_r<347> a_wl_r<346> a_wl_r<345> a_wl_r<344> a_wl_r<343> a_wl_r<342> a_wl_r<341> a_wl_r<340> a_wl_r<339> a_wl_r<338> a_wl_r<337> a_wl_r<336> VDD! VSS! / RM_IHPSG13_8192x32_c4_1P_WLDRV16X16 +XA_WLDRV<52> a_wi<335> a_wi<334> a_wi<333> a_wi<332> a_wi<331> a_wi<330> a_wi<329> a_wi<328> a_wi<327> a_wi<326> a_wi<325> a_wi<324> a_wi<323> a_wi<322> a_wi<321> a_wi<320> a_wl_r<335> a_wl_r<334> a_wl_r<333> a_wl_r<332> a_wl_r<331> a_wl_r<330> a_wl_r<329> a_wl_r<328> a_wl_r<327> a_wl_r<326> a_wl_r<325> a_wl_r<324> a_wl_r<323> a_wl_r<322> a_wl_r<321> a_wl_r<320> VDD! VSS! / RM_IHPSG13_8192x32_c4_1P_WLDRV16X16 +XA_WLDRV<51> a_wi<319> a_wi<318> a_wi<317> a_wi<316> a_wi<315> a_wi<314> a_wi<313> a_wi<312> a_wi<311> a_wi<310> a_wi<309> a_wi<308> a_wi<307> a_wi<306> a_wi<305> a_wi<304> a_wl_r<319> a_wl_r<318> a_wl_r<317> a_wl_r<316> a_wl_r<315> a_wl_r<314> a_wl_r<313> a_wl_r<312> a_wl_r<311> a_wl_r<310> a_wl_r<309> a_wl_r<308> a_wl_r<307> a_wl_r<306> a_wl_r<305> a_wl_r<304> VDD! VSS! / RM_IHPSG13_8192x32_c4_1P_WLDRV16X16 +XA_WLDRV<50> a_wi<303> a_wi<302> a_wi<301> a_wi<300> a_wi<299> a_wi<298> a_wi<297> a_wi<296> a_wi<295> a_wi<294> a_wi<293> a_wi<292> a_wi<291> a_wi<290> a_wi<289> a_wi<288> a_wl_r<303> a_wl_r<302> a_wl_r<301> a_wl_r<300> a_wl_r<299> a_wl_r<298> a_wl_r<297> a_wl_r<296> a_wl_r<295> a_wl_r<294> a_wl_r<293> a_wl_r<292> a_wl_r<291> a_wl_r<290> a_wl_r<289> a_wl_r<288> VDD! VSS! / RM_IHPSG13_8192x32_c4_1P_WLDRV16X16 +XA_WLDRV<49> a_wi<287> a_wi<286> a_wi<285> a_wi<284> a_wi<283> a_wi<282> a_wi<281> a_wi<280> a_wi<279> a_wi<278> a_wi<277> a_wi<276> a_wi<275> a_wi<274> a_wi<273> a_wi<272> a_wl_r<287> a_wl_r<286> a_wl_r<285> a_wl_r<284> a_wl_r<283> a_wl_r<282> a_wl_r<281> a_wl_r<280> a_wl_r<279> a_wl_r<278> a_wl_r<277> a_wl_r<276> a_wl_r<275> a_wl_r<274> a_wl_r<273> a_wl_r<272> VDD! VSS! / RM_IHPSG13_8192x32_c4_1P_WLDRV16X16 +XA_WLDRV<48> a_wi<271> a_wi<270> a_wi<269> a_wi<268> a_wi<267> a_wi<266> a_wi<265> a_wi<264> a_wi<263> a_wi<262> a_wi<261> a_wi<260> a_wi<259> a_wi<258> a_wi<257> a_wi<256> a_wl_r<271> a_wl_r<270> a_wl_r<269> a_wl_r<268> a_wl_r<267> a_wl_r<266> a_wl_r<265> a_wl_r<264> a_wl_r<263> a_wl_r<262> a_wl_r<261> a_wl_r<260> a_wl_r<259> a_wl_r<258> a_wl_r<257> a_wl_r<256> VDD! VSS! / RM_IHPSG13_8192x32_c4_1P_WLDRV16X16 +XA_WLDRV<47> a_wi<255> a_wi<254> a_wi<253> a_wi<252> a_wi<251> a_wi<250> a_wi<249> a_wi<248> a_wi<247> a_wi<246> a_wi<245> a_wi<244> a_wi<243> a_wi<242> a_wi<241> a_wi<240> a_wl_r<255> a_wl_r<254> a_wl_r<253> a_wl_r<252> a_wl_r<251> a_wl_r<250> a_wl_r<249> a_wl_r<248> a_wl_r<247> a_wl_r<246> a_wl_r<245> a_wl_r<244> a_wl_r<243> a_wl_r<242> a_wl_r<241> a_wl_r<240> VDD! VSS! / RM_IHPSG13_8192x32_c4_1P_WLDRV16X16 +XA_WLDRV<46> a_wi<239> a_wi<238> a_wi<237> a_wi<236> a_wi<235> a_wi<234> a_wi<233> a_wi<232> a_wi<231> a_wi<230> a_wi<229> a_wi<228> a_wi<227> a_wi<226> a_wi<225> a_wi<224> a_wl_r<239> a_wl_r<238> a_wl_r<237> a_wl_r<236> a_wl_r<235> a_wl_r<234> a_wl_r<233> a_wl_r<232> a_wl_r<231> a_wl_r<230> a_wl_r<229> a_wl_r<228> a_wl_r<227> a_wl_r<226> a_wl_r<225> a_wl_r<224> VDD! VSS! / RM_IHPSG13_8192x32_c4_1P_WLDRV16X16 +XA_WLDRV<45> a_wi<223> a_wi<222> a_wi<221> a_wi<220> a_wi<219> a_wi<218> a_wi<217> a_wi<216> a_wi<215> a_wi<214> a_wi<213> a_wi<212> a_wi<211> a_wi<210> a_wi<209> a_wi<208> a_wl_r<223> a_wl_r<222> a_wl_r<221> a_wl_r<220> a_wl_r<219> a_wl_r<218> a_wl_r<217> a_wl_r<216> a_wl_r<215> a_wl_r<214> a_wl_r<213> a_wl_r<212> a_wl_r<211> a_wl_r<210> a_wl_r<209> a_wl_r<208> VDD! VSS! / RM_IHPSG13_8192x32_c4_1P_WLDRV16X16 +XA_WLDRV<44> a_wi<207> a_wi<206> a_wi<205> a_wi<204> a_wi<203> a_wi<202> a_wi<201> a_wi<200> a_wi<199> a_wi<198> a_wi<197> a_wi<196> a_wi<195> a_wi<194> a_wi<193> a_wi<192> a_wl_r<207> a_wl_r<206> a_wl_r<205> a_wl_r<204> a_wl_r<203> a_wl_r<202> a_wl_r<201> a_wl_r<200> a_wl_r<199> a_wl_r<198> a_wl_r<197> a_wl_r<196> a_wl_r<195> a_wl_r<194> a_wl_r<193> a_wl_r<192> VDD! VSS! / RM_IHPSG13_8192x32_c4_1P_WLDRV16X16 +XA_WLDRV<43> a_wi<191> a_wi<190> a_wi<189> a_wi<188> a_wi<187> a_wi<186> a_wi<185> a_wi<184> a_wi<183> a_wi<182> a_wi<181> a_wi<180> a_wi<179> a_wi<178> a_wi<177> a_wi<176> a_wl_r<191> a_wl_r<190> a_wl_r<189> a_wl_r<188> a_wl_r<187> a_wl_r<186> a_wl_r<185> a_wl_r<184> a_wl_r<183> a_wl_r<182> a_wl_r<181> a_wl_r<180> a_wl_r<179> a_wl_r<178> a_wl_r<177> a_wl_r<176> VDD! VSS! / RM_IHPSG13_8192x32_c4_1P_WLDRV16X16 +XA_WLDRV<42> a_wi<175> a_wi<174> a_wi<173> a_wi<172> a_wi<171> a_wi<170> a_wi<169> a_wi<168> a_wi<167> a_wi<166> a_wi<165> a_wi<164> a_wi<163> a_wi<162> a_wi<161> a_wi<160> a_wl_r<175> a_wl_r<174> a_wl_r<173> a_wl_r<172> a_wl_r<171> a_wl_r<170> a_wl_r<169> a_wl_r<168> a_wl_r<167> a_wl_r<166> a_wl_r<165> a_wl_r<164> a_wl_r<163> a_wl_r<162> a_wl_r<161> a_wl_r<160> VDD! VSS! / RM_IHPSG13_8192x32_c4_1P_WLDRV16X16 +XA_WLDRV<41> a_wi<159> a_wi<158> a_wi<157> a_wi<156> a_wi<155> a_wi<154> a_wi<153> a_wi<152> a_wi<151> a_wi<150> a_wi<149> a_wi<148> a_wi<147> a_wi<146> a_wi<145> a_wi<144> a_wl_r<159> a_wl_r<158> a_wl_r<157> a_wl_r<156> a_wl_r<155> a_wl_r<154> a_wl_r<153> a_wl_r<152> a_wl_r<151> a_wl_r<150> a_wl_r<149> a_wl_r<148> a_wl_r<147> a_wl_r<146> a_wl_r<145> a_wl_r<144> VDD! VSS! / RM_IHPSG13_8192x32_c4_1P_WLDRV16X16 +XA_WLDRV<40> a_wi<143> a_wi<142> a_wi<141> a_wi<140> a_wi<139> a_wi<138> a_wi<137> a_wi<136> a_wi<135> a_wi<134> a_wi<133> a_wi<132> a_wi<131> a_wi<130> a_wi<129> a_wi<128> a_wl_r<143> a_wl_r<142> a_wl_r<141> a_wl_r<140> a_wl_r<139> a_wl_r<138> a_wl_r<137> a_wl_r<136> a_wl_r<135> a_wl_r<134> a_wl_r<133> a_wl_r<132> a_wl_r<131> a_wl_r<130> a_wl_r<129> a_wl_r<128> VDD! VSS! / RM_IHPSG13_8192x32_c4_1P_WLDRV16X16 +XA_WLDRV<39> a_wi<127> a_wi<126> a_wi<125> a_wi<124> a_wi<123> a_wi<122> a_wi<121> a_wi<120> a_wi<119> a_wi<118> a_wi<117> a_wi<116> a_wi<115> a_wi<114> a_wi<113> a_wi<112> a_wl_r<127> a_wl_r<126> a_wl_r<125> a_wl_r<124> a_wl_r<123> a_wl_r<122> a_wl_r<121> a_wl_r<120> a_wl_r<119> a_wl_r<118> a_wl_r<117> a_wl_r<116> a_wl_r<115> a_wl_r<114> a_wl_r<113> a_wl_r<112> VDD! VSS! / RM_IHPSG13_8192x32_c4_1P_WLDRV16X16 +XA_WLDRV<38> a_wi<111> a_wi<110> a_wi<109> a_wi<108> a_wi<107> a_wi<106> a_wi<105> a_wi<104> a_wi<103> a_wi<102> a_wi<101> a_wi<100> a_wi<99> a_wi<98> a_wi<97> a_wi<96> a_wl_r<111> a_wl_r<110> a_wl_r<109> a_wl_r<108> a_wl_r<107> a_wl_r<106> a_wl_r<105> a_wl_r<104> a_wl_r<103> a_wl_r<102> a_wl_r<101> a_wl_r<100> a_wl_r<99> a_wl_r<98> a_wl_r<97> a_wl_r<96> VDD! VSS! / RM_IHPSG13_8192x32_c4_1P_WLDRV16X16 +XA_WLDRV<37> a_wi<95> a_wi<94> a_wi<93> a_wi<92> a_wi<91> a_wi<90> a_wi<89> a_wi<88> a_wi<87> a_wi<86> a_wi<85> a_wi<84> a_wi<83> a_wi<82> a_wi<81> a_wi<80> a_wl_r<95> a_wl_r<94> a_wl_r<93> a_wl_r<92> a_wl_r<91> a_wl_r<90> a_wl_r<89> a_wl_r<88> a_wl_r<87> a_wl_r<86> a_wl_r<85> a_wl_r<84> a_wl_r<83> a_wl_r<82> a_wl_r<81> a_wl_r<80> VDD! VSS! / RM_IHPSG13_8192x32_c4_1P_WLDRV16X16 +XA_WLDRV<36> a_wi<79> a_wi<78> a_wi<77> a_wi<76> a_wi<75> a_wi<74> a_wi<73> a_wi<72> a_wi<71> a_wi<70> a_wi<69> a_wi<68> a_wi<67> a_wi<66> a_wi<65> a_wi<64> a_wl_r<79> a_wl_r<78> a_wl_r<77> a_wl_r<76> a_wl_r<75> a_wl_r<74> a_wl_r<73> a_wl_r<72> a_wl_r<71> a_wl_r<70> a_wl_r<69> a_wl_r<68> a_wl_r<67> a_wl_r<66> a_wl_r<65> a_wl_r<64> VDD! VSS! / RM_IHPSG13_8192x32_c4_1P_WLDRV16X16 +XA_WLDRV<35> a_wi<63> a_wi<62> a_wi<61> a_wi<60> a_wi<59> a_wi<58> a_wi<57> a_wi<56> a_wi<55> a_wi<54> a_wi<53> a_wi<52> a_wi<51> a_wi<50> a_wi<49> a_wi<48> a_wl_r<63> a_wl_r<62> a_wl_r<61> a_wl_r<60> a_wl_r<59> a_wl_r<58> a_wl_r<57> a_wl_r<56> a_wl_r<55> a_wl_r<54> a_wl_r<53> a_wl_r<52> a_wl_r<51> a_wl_r<50> a_wl_r<49> a_wl_r<48> VDD! VSS! / RM_IHPSG13_8192x32_c4_1P_WLDRV16X16 +XA_WLDRV<34> a_wi<47> a_wi<46> a_wi<45> a_wi<44> a_wi<43> a_wi<42> a_wi<41> a_wi<40> a_wi<39> a_wi<38> a_wi<37> a_wi<36> a_wi<35> a_wi<34> a_wi<33> a_wi<32> a_wl_r<47> a_wl_r<46> a_wl_r<45> a_wl_r<44> a_wl_r<43> a_wl_r<42> a_wl_r<41> a_wl_r<40> a_wl_r<39> a_wl_r<38> a_wl_r<37> a_wl_r<36> a_wl_r<35> a_wl_r<34> a_wl_r<33> a_wl_r<32> VDD! VSS! / RM_IHPSG13_8192x32_c4_1P_WLDRV16X16 +XA_WLDRV<33> a_wi<31> a_wi<30> a_wi<29> a_wi<28> a_wi<27> a_wi<26> a_wi<25> a_wi<24> a_wi<23> a_wi<22> a_wi<21> a_wi<20> a_wi<19> a_wi<18> a_wi<17> a_wi<16> a_wl_r<31> a_wl_r<30> a_wl_r<29> a_wl_r<28> a_wl_r<27> a_wl_r<26> a_wl_r<25> a_wl_r<24> a_wl_r<23> a_wl_r<22> a_wl_r<21> a_wl_r<20> a_wl_r<19> a_wl_r<18> a_wl_r<17> a_wl_r<16> VDD! VSS! / RM_IHPSG13_8192x32_c4_1P_WLDRV16X16 +XA_WLDRV<32> a_wi<15> a_wi<14> a_wi<13> a_wi<12> a_wi<11> a_wi<10> a_wi<9> a_wi<8> a_wi<7> a_wi<6> a_wi<5> a_wi<4> a_wi<3> a_wi<2> a_wi<1> a_wi<0> a_wl_r<15> a_wl_r<14> a_wl_r<13> a_wl_r<12> a_wl_r<11> a_wl_r<10> a_wl_r<9> a_wl_r<8> a_wl_r<7> a_wl_r<6> a_wl_r<5> a_wl_r<4> a_wl_r<3> a_wl_r<2> a_wl_r<1> a_wl_r<0> VDD! VSS! / RM_IHPSG13_8192x32_c4_1P_WLDRV16X16 +XA_WLDRV<31> a_wi<511> a_wi<510> a_wi<509> a_wi<508> a_wi<507> a_wi<506> a_wi<505> a_wi<504> a_wi<503> a_wi<502> a_wi<501> a_wi<500> a_wi<499> a_wi<498> a_wi<497> a_wi<496> a_wl_l<511> a_wl_l<510> a_wl_l<509> a_wl_l<508> a_wl_l<507> a_wl_l<506> a_wl_l<505> a_wl_l<504> a_wl_l<503> a_wl_l<502> a_wl_l<501> a_wl_l<500> a_wl_l<499> a_wl_l<498> a_wl_l<497> a_wl_l<496> VDD! VSS! / RM_IHPSG13_8192x32_c4_1P_WLDRV16X16 +XA_WLDRV<30> a_wi<495> a_wi<494> a_wi<493> a_wi<492> a_wi<491> a_wi<490> a_wi<489> a_wi<488> a_wi<487> a_wi<486> a_wi<485> a_wi<484> a_wi<483> a_wi<482> a_wi<481> a_wi<480> a_wl_l<495> a_wl_l<494> a_wl_l<493> a_wl_l<492> a_wl_l<491> a_wl_l<490> a_wl_l<489> a_wl_l<488> a_wl_l<487> a_wl_l<486> a_wl_l<485> a_wl_l<484> a_wl_l<483> a_wl_l<482> a_wl_l<481> a_wl_l<480> VDD! VSS! / RM_IHPSG13_8192x32_c4_1P_WLDRV16X16 +XA_WLDRV<29> a_wi<479> a_wi<478> a_wi<477> a_wi<476> a_wi<475> a_wi<474> a_wi<473> a_wi<472> a_wi<471> a_wi<470> a_wi<469> a_wi<468> a_wi<467> a_wi<466> a_wi<465> a_wi<464> a_wl_l<479> a_wl_l<478> a_wl_l<477> a_wl_l<476> a_wl_l<475> a_wl_l<474> a_wl_l<473> a_wl_l<472> a_wl_l<471> a_wl_l<470> a_wl_l<469> a_wl_l<468> a_wl_l<467> a_wl_l<466> a_wl_l<465> a_wl_l<464> VDD! VSS! / RM_IHPSG13_8192x32_c4_1P_WLDRV16X16 +XA_WLDRV<28> a_wi<463> a_wi<462> a_wi<461> a_wi<460> a_wi<459> a_wi<458> a_wi<457> a_wi<456> a_wi<455> a_wi<454> a_wi<453> a_wi<452> a_wi<451> a_wi<450> a_wi<449> a_wi<448> a_wl_l<463> a_wl_l<462> a_wl_l<461> a_wl_l<460> a_wl_l<459> a_wl_l<458> a_wl_l<457> a_wl_l<456> a_wl_l<455> a_wl_l<454> a_wl_l<453> a_wl_l<452> a_wl_l<451> a_wl_l<450> a_wl_l<449> a_wl_l<448> VDD! VSS! / RM_IHPSG13_8192x32_c4_1P_WLDRV16X16 +XA_WLDRV<27> a_wi<447> a_wi<446> a_wi<445> a_wi<444> a_wi<443> a_wi<442> a_wi<441> a_wi<440> a_wi<439> a_wi<438> a_wi<437> a_wi<436> a_wi<435> a_wi<434> a_wi<433> a_wi<432> a_wl_l<447> a_wl_l<446> a_wl_l<445> a_wl_l<444> a_wl_l<443> a_wl_l<442> a_wl_l<441> a_wl_l<440> a_wl_l<439> a_wl_l<438> a_wl_l<437> a_wl_l<436> a_wl_l<435> a_wl_l<434> a_wl_l<433> a_wl_l<432> VDD! VSS! / RM_IHPSG13_8192x32_c4_1P_WLDRV16X16 +XA_WLDRV<26> a_wi<431> a_wi<430> a_wi<429> a_wi<428> a_wi<427> a_wi<426> a_wi<425> a_wi<424> a_wi<423> a_wi<422> a_wi<421> a_wi<420> a_wi<419> a_wi<418> a_wi<417> a_wi<416> a_wl_l<431> a_wl_l<430> a_wl_l<429> a_wl_l<428> a_wl_l<427> a_wl_l<426> a_wl_l<425> a_wl_l<424> a_wl_l<423> a_wl_l<422> a_wl_l<421> a_wl_l<420> a_wl_l<419> a_wl_l<418> a_wl_l<417> a_wl_l<416> VDD! VSS! / RM_IHPSG13_8192x32_c4_1P_WLDRV16X16 +XA_WLDRV<25> a_wi<415> a_wi<414> a_wi<413> a_wi<412> a_wi<411> a_wi<410> a_wi<409> a_wi<408> a_wi<407> a_wi<406> a_wi<405> a_wi<404> a_wi<403> a_wi<402> a_wi<401> a_wi<400> a_wl_l<415> a_wl_l<414> a_wl_l<413> a_wl_l<412> a_wl_l<411> a_wl_l<410> a_wl_l<409> a_wl_l<408> a_wl_l<407> a_wl_l<406> a_wl_l<405> a_wl_l<404> a_wl_l<403> a_wl_l<402> a_wl_l<401> a_wl_l<400> VDD! VSS! / RM_IHPSG13_8192x32_c4_1P_WLDRV16X16 +XA_WLDRV<24> a_wi<399> a_wi<398> a_wi<397> a_wi<396> a_wi<395> a_wi<394> a_wi<393> a_wi<392> a_wi<391> a_wi<390> a_wi<389> a_wi<388> a_wi<387> a_wi<386> a_wi<385> a_wi<384> a_wl_l<399> a_wl_l<398> a_wl_l<397> a_wl_l<396> a_wl_l<395> a_wl_l<394> a_wl_l<393> a_wl_l<392> a_wl_l<391> a_wl_l<390> a_wl_l<389> a_wl_l<388> a_wl_l<387> a_wl_l<386> a_wl_l<385> a_wl_l<384> VDD! VSS! / RM_IHPSG13_8192x32_c4_1P_WLDRV16X16 +XA_WLDRV<23> a_wi<383> a_wi<382> a_wi<381> a_wi<380> a_wi<379> a_wi<378> a_wi<377> a_wi<376> a_wi<375> a_wi<374> a_wi<373> a_wi<372> a_wi<371> a_wi<370> a_wi<369> a_wi<368> a_wl_l<383> a_wl_l<382> a_wl_l<381> a_wl_l<380> a_wl_l<379> a_wl_l<378> a_wl_l<377> a_wl_l<376> a_wl_l<375> a_wl_l<374> a_wl_l<373> a_wl_l<372> a_wl_l<371> a_wl_l<370> a_wl_l<369> a_wl_l<368> VDD! VSS! / RM_IHPSG13_8192x32_c4_1P_WLDRV16X16 +XA_WLDRV<22> a_wi<367> a_wi<366> a_wi<365> a_wi<364> a_wi<363> a_wi<362> a_wi<361> a_wi<360> a_wi<359> a_wi<358> a_wi<357> a_wi<356> a_wi<355> a_wi<354> a_wi<353> a_wi<352> a_wl_l<367> a_wl_l<366> a_wl_l<365> a_wl_l<364> a_wl_l<363> a_wl_l<362> a_wl_l<361> a_wl_l<360> a_wl_l<359> a_wl_l<358> a_wl_l<357> a_wl_l<356> a_wl_l<355> a_wl_l<354> a_wl_l<353> a_wl_l<352> VDD! VSS! / RM_IHPSG13_8192x32_c4_1P_WLDRV16X16 +XA_WLDRV<21> a_wi<351> a_wi<350> a_wi<349> a_wi<348> a_wi<347> a_wi<346> a_wi<345> a_wi<344> a_wi<343> a_wi<342> a_wi<341> a_wi<340> a_wi<339> a_wi<338> a_wi<337> a_wi<336> a_wl_l<351> a_wl_l<350> a_wl_l<349> a_wl_l<348> a_wl_l<347> a_wl_l<346> a_wl_l<345> a_wl_l<344> a_wl_l<343> a_wl_l<342> a_wl_l<341> a_wl_l<340> a_wl_l<339> a_wl_l<338> a_wl_l<337> a_wl_l<336> VDD! VSS! / RM_IHPSG13_8192x32_c4_1P_WLDRV16X16 +XA_WLDRV<20> a_wi<335> a_wi<334> a_wi<333> a_wi<332> a_wi<331> a_wi<330> a_wi<329> a_wi<328> a_wi<327> a_wi<326> a_wi<325> a_wi<324> a_wi<323> a_wi<322> a_wi<321> a_wi<320> a_wl_l<335> a_wl_l<334> a_wl_l<333> a_wl_l<332> a_wl_l<331> a_wl_l<330> a_wl_l<329> a_wl_l<328> a_wl_l<327> a_wl_l<326> a_wl_l<325> a_wl_l<324> a_wl_l<323> a_wl_l<322> a_wl_l<321> a_wl_l<320> VDD! VSS! / RM_IHPSG13_8192x32_c4_1P_WLDRV16X16 +XA_WLDRV<19> a_wi<319> a_wi<318> a_wi<317> a_wi<316> a_wi<315> a_wi<314> a_wi<313> a_wi<312> a_wi<311> a_wi<310> a_wi<309> a_wi<308> a_wi<307> a_wi<306> a_wi<305> a_wi<304> a_wl_l<319> a_wl_l<318> a_wl_l<317> a_wl_l<316> a_wl_l<315> a_wl_l<314> a_wl_l<313> a_wl_l<312> a_wl_l<311> a_wl_l<310> a_wl_l<309> a_wl_l<308> a_wl_l<307> a_wl_l<306> a_wl_l<305> a_wl_l<304> VDD! VSS! / RM_IHPSG13_8192x32_c4_1P_WLDRV16X16 +XA_WLDRV<18> a_wi<303> a_wi<302> a_wi<301> a_wi<300> a_wi<299> a_wi<298> a_wi<297> a_wi<296> a_wi<295> a_wi<294> a_wi<293> a_wi<292> a_wi<291> a_wi<290> a_wi<289> a_wi<288> a_wl_l<303> a_wl_l<302> a_wl_l<301> a_wl_l<300> a_wl_l<299> a_wl_l<298> a_wl_l<297> a_wl_l<296> a_wl_l<295> a_wl_l<294> a_wl_l<293> a_wl_l<292> a_wl_l<291> a_wl_l<290> a_wl_l<289> a_wl_l<288> VDD! VSS! / RM_IHPSG13_8192x32_c4_1P_WLDRV16X16 +XA_WLDRV<17> a_wi<287> a_wi<286> a_wi<285> a_wi<284> a_wi<283> a_wi<282> a_wi<281> a_wi<280> a_wi<279> a_wi<278> a_wi<277> a_wi<276> a_wi<275> a_wi<274> a_wi<273> a_wi<272> a_wl_l<287> a_wl_l<286> a_wl_l<285> a_wl_l<284> a_wl_l<283> a_wl_l<282> a_wl_l<281> a_wl_l<280> a_wl_l<279> a_wl_l<278> a_wl_l<277> a_wl_l<276> a_wl_l<275> a_wl_l<274> a_wl_l<273> a_wl_l<272> VDD! VSS! / RM_IHPSG13_8192x32_c4_1P_WLDRV16X16 +XA_WLDRV<16> a_wi<271> a_wi<270> a_wi<269> a_wi<268> a_wi<267> a_wi<266> a_wi<265> a_wi<264> a_wi<263> a_wi<262> a_wi<261> a_wi<260> a_wi<259> a_wi<258> a_wi<257> a_wi<256> a_wl_l<271> a_wl_l<270> a_wl_l<269> a_wl_l<268> a_wl_l<267> a_wl_l<266> a_wl_l<265> a_wl_l<264> a_wl_l<263> a_wl_l<262> a_wl_l<261> a_wl_l<260> a_wl_l<259> a_wl_l<258> a_wl_l<257> a_wl_l<256> VDD! VSS! / RM_IHPSG13_8192x32_c4_1P_WLDRV16X16 +XA_WLDRV<15> a_wi<255> a_wi<254> a_wi<253> a_wi<252> a_wi<251> a_wi<250> a_wi<249> a_wi<248> a_wi<247> a_wi<246> a_wi<245> a_wi<244> a_wi<243> a_wi<242> a_wi<241> a_wi<240> a_wl_l<255> a_wl_l<254> a_wl_l<253> a_wl_l<252> a_wl_l<251> a_wl_l<250> a_wl_l<249> a_wl_l<248> a_wl_l<247> a_wl_l<246> a_wl_l<245> a_wl_l<244> a_wl_l<243> a_wl_l<242> a_wl_l<241> a_wl_l<240> VDD! VSS! / RM_IHPSG13_8192x32_c4_1P_WLDRV16X16 +XA_WLDRV<14> a_wi<239> a_wi<238> a_wi<237> a_wi<236> a_wi<235> a_wi<234> a_wi<233> a_wi<232> a_wi<231> a_wi<230> a_wi<229> a_wi<228> a_wi<227> a_wi<226> a_wi<225> a_wi<224> a_wl_l<239> a_wl_l<238> a_wl_l<237> a_wl_l<236> a_wl_l<235> a_wl_l<234> a_wl_l<233> a_wl_l<232> a_wl_l<231> a_wl_l<230> a_wl_l<229> a_wl_l<228> a_wl_l<227> a_wl_l<226> a_wl_l<225> a_wl_l<224> VDD! VSS! / RM_IHPSG13_8192x32_c4_1P_WLDRV16X16 +XA_WLDRV<13> a_wi<223> a_wi<222> a_wi<221> a_wi<220> a_wi<219> a_wi<218> a_wi<217> a_wi<216> a_wi<215> a_wi<214> a_wi<213> a_wi<212> a_wi<211> a_wi<210> a_wi<209> a_wi<208> a_wl_l<223> a_wl_l<222> a_wl_l<221> a_wl_l<220> a_wl_l<219> a_wl_l<218> a_wl_l<217> a_wl_l<216> a_wl_l<215> a_wl_l<214> a_wl_l<213> a_wl_l<212> a_wl_l<211> a_wl_l<210> a_wl_l<209> a_wl_l<208> VDD! VSS! / RM_IHPSG13_8192x32_c4_1P_WLDRV16X16 +XA_WLDRV<12> a_wi<207> a_wi<206> a_wi<205> a_wi<204> a_wi<203> a_wi<202> a_wi<201> a_wi<200> a_wi<199> a_wi<198> a_wi<197> a_wi<196> a_wi<195> a_wi<194> a_wi<193> a_wi<192> a_wl_l<207> a_wl_l<206> a_wl_l<205> a_wl_l<204> a_wl_l<203> a_wl_l<202> a_wl_l<201> a_wl_l<200> a_wl_l<199> a_wl_l<198> a_wl_l<197> a_wl_l<196> a_wl_l<195> a_wl_l<194> a_wl_l<193> a_wl_l<192> VDD! VSS! / RM_IHPSG13_8192x32_c4_1P_WLDRV16X16 +XA_WLDRV<11> a_wi<191> a_wi<190> a_wi<189> a_wi<188> a_wi<187> a_wi<186> a_wi<185> a_wi<184> a_wi<183> a_wi<182> a_wi<181> a_wi<180> a_wi<179> a_wi<178> a_wi<177> a_wi<176> a_wl_l<191> a_wl_l<190> a_wl_l<189> a_wl_l<188> a_wl_l<187> a_wl_l<186> a_wl_l<185> a_wl_l<184> a_wl_l<183> a_wl_l<182> a_wl_l<181> a_wl_l<180> a_wl_l<179> a_wl_l<178> a_wl_l<177> a_wl_l<176> VDD! VSS! / RM_IHPSG13_8192x32_c4_1P_WLDRV16X16 +XA_WLDRV<10> a_wi<175> a_wi<174> a_wi<173> a_wi<172> a_wi<171> a_wi<170> a_wi<169> a_wi<168> a_wi<167> a_wi<166> a_wi<165> a_wi<164> a_wi<163> a_wi<162> a_wi<161> a_wi<160> a_wl_l<175> a_wl_l<174> a_wl_l<173> a_wl_l<172> a_wl_l<171> a_wl_l<170> a_wl_l<169> a_wl_l<168> a_wl_l<167> a_wl_l<166> a_wl_l<165> a_wl_l<164> a_wl_l<163> a_wl_l<162> a_wl_l<161> a_wl_l<160> VDD! VSS! / RM_IHPSG13_8192x32_c4_1P_WLDRV16X16 +XA_WLDRV<9> a_wi<159> a_wi<158> a_wi<157> a_wi<156> a_wi<155> a_wi<154> a_wi<153> a_wi<152> a_wi<151> a_wi<150> a_wi<149> a_wi<148> a_wi<147> a_wi<146> a_wi<145> a_wi<144> a_wl_l<159> a_wl_l<158> a_wl_l<157> a_wl_l<156> a_wl_l<155> a_wl_l<154> a_wl_l<153> a_wl_l<152> a_wl_l<151> a_wl_l<150> a_wl_l<149> a_wl_l<148> a_wl_l<147> a_wl_l<146> a_wl_l<145> a_wl_l<144> VDD! VSS! / RM_IHPSG13_8192x32_c4_1P_WLDRV16X16 +XA_WLDRV<8> a_wi<143> a_wi<142> a_wi<141> a_wi<140> a_wi<139> a_wi<138> a_wi<137> a_wi<136> a_wi<135> a_wi<134> a_wi<133> a_wi<132> a_wi<131> a_wi<130> a_wi<129> a_wi<128> a_wl_l<143> a_wl_l<142> a_wl_l<141> a_wl_l<140> a_wl_l<139> a_wl_l<138> a_wl_l<137> a_wl_l<136> a_wl_l<135> a_wl_l<134> a_wl_l<133> a_wl_l<132> a_wl_l<131> a_wl_l<130> a_wl_l<129> a_wl_l<128> VDD! VSS! / RM_IHPSG13_8192x32_c4_1P_WLDRV16X16 +XA_WLDRV<7> a_wi<127> a_wi<126> a_wi<125> a_wi<124> a_wi<123> a_wi<122> a_wi<121> a_wi<120> a_wi<119> a_wi<118> a_wi<117> a_wi<116> a_wi<115> a_wi<114> a_wi<113> a_wi<112> a_wl_l<127> a_wl_l<126> a_wl_l<125> a_wl_l<124> a_wl_l<123> a_wl_l<122> a_wl_l<121> a_wl_l<120> a_wl_l<119> a_wl_l<118> a_wl_l<117> a_wl_l<116> a_wl_l<115> a_wl_l<114> a_wl_l<113> a_wl_l<112> VDD! VSS! / RM_IHPSG13_8192x32_c4_1P_WLDRV16X16 +XA_WLDRV<6> a_wi<111> a_wi<110> a_wi<109> a_wi<108> a_wi<107> a_wi<106> a_wi<105> a_wi<104> a_wi<103> a_wi<102> a_wi<101> a_wi<100> a_wi<99> a_wi<98> a_wi<97> a_wi<96> a_wl_l<111> a_wl_l<110> a_wl_l<109> a_wl_l<108> a_wl_l<107> a_wl_l<106> a_wl_l<105> a_wl_l<104> a_wl_l<103> a_wl_l<102> a_wl_l<101> a_wl_l<100> a_wl_l<99> a_wl_l<98> a_wl_l<97> a_wl_l<96> VDD! VSS! / RM_IHPSG13_8192x32_c4_1P_WLDRV16X16 +XA_WLDRV<5> a_wi<95> a_wi<94> a_wi<93> a_wi<92> a_wi<91> a_wi<90> a_wi<89> a_wi<88> a_wi<87> a_wi<86> a_wi<85> a_wi<84> a_wi<83> a_wi<82> a_wi<81> a_wi<80> a_wl_l<95> a_wl_l<94> a_wl_l<93> a_wl_l<92> a_wl_l<91> a_wl_l<90> a_wl_l<89> a_wl_l<88> a_wl_l<87> a_wl_l<86> a_wl_l<85> a_wl_l<84> a_wl_l<83> a_wl_l<82> a_wl_l<81> a_wl_l<80> VDD! VSS! / RM_IHPSG13_8192x32_c4_1P_WLDRV16X16 +XA_WLDRV<4> a_wi<79> a_wi<78> a_wi<77> a_wi<76> a_wi<75> a_wi<74> a_wi<73> a_wi<72> a_wi<71> a_wi<70> a_wi<69> a_wi<68> a_wi<67> a_wi<66> a_wi<65> a_wi<64> a_wl_l<79> a_wl_l<78> a_wl_l<77> a_wl_l<76> a_wl_l<75> a_wl_l<74> a_wl_l<73> a_wl_l<72> a_wl_l<71> a_wl_l<70> a_wl_l<69> a_wl_l<68> a_wl_l<67> a_wl_l<66> a_wl_l<65> a_wl_l<64> VDD! VSS! / RM_IHPSG13_8192x32_c4_1P_WLDRV16X16 +XA_WLDRV<3> a_wi<63> a_wi<62> a_wi<61> a_wi<60> a_wi<59> a_wi<58> a_wi<57> a_wi<56> a_wi<55> a_wi<54> a_wi<53> a_wi<52> a_wi<51> a_wi<50> a_wi<49> a_wi<48> a_wl_l<63> a_wl_l<62> a_wl_l<61> a_wl_l<60> a_wl_l<59> a_wl_l<58> a_wl_l<57> a_wl_l<56> a_wl_l<55> a_wl_l<54> a_wl_l<53> a_wl_l<52> a_wl_l<51> a_wl_l<50> a_wl_l<49> a_wl_l<48> VDD! VSS! / RM_IHPSG13_8192x32_c4_1P_WLDRV16X16 +XA_WLDRV<2> a_wi<47> a_wi<46> a_wi<45> a_wi<44> a_wi<43> a_wi<42> a_wi<41> a_wi<40> a_wi<39> a_wi<38> a_wi<37> a_wi<36> a_wi<35> a_wi<34> a_wi<33> a_wi<32> a_wl_l<47> a_wl_l<46> a_wl_l<45> a_wl_l<44> a_wl_l<43> a_wl_l<42> a_wl_l<41> a_wl_l<40> a_wl_l<39> a_wl_l<38> a_wl_l<37> a_wl_l<36> a_wl_l<35> a_wl_l<34> a_wl_l<33> a_wl_l<32> VDD! VSS! / RM_IHPSG13_8192x32_c4_1P_WLDRV16X16 +XA_WLDRV<1> a_wi<31> a_wi<30> a_wi<29> a_wi<28> a_wi<27> a_wi<26> a_wi<25> a_wi<24> a_wi<23> a_wi<22> a_wi<21> a_wi<20> a_wi<19> a_wi<18> a_wi<17> a_wi<16> a_wl_l<31> a_wl_l<30> a_wl_l<29> a_wl_l<28> a_wl_l<27> a_wl_l<26> a_wl_l<25> a_wl_l<24> a_wl_l<23> a_wl_l<22> a_wl_l<21> a_wl_l<20> a_wl_l<19> a_wl_l<18> a_wl_l<17> a_wl_l<16> VDD! VSS! / RM_IHPSG13_8192x32_c4_1P_WLDRV16X16 +XA_WLDRV<0> a_wi<15> a_wi<14> a_wi<13> a_wi<12> a_wi<11> a_wi<10> a_wi<9> a_wi<8> a_wi<7> a_wi<6> a_wi<5> a_wi<4> a_wi<3> a_wi<2> a_wi<1> a_wi<0> a_wl_l<15> a_wl_l<14> a_wl_l<13> a_wl_l<12> a_wl_l<11> a_wl_l<10> a_wl_l<9> a_wl_l<8> a_wl_l<7> a_wl_l<6> a_wl_l<5> a_wl_l<4> a_wl_l<3> a_wl_l<2> a_wl_l<1> a_wl_l<0> VDD! VSS! / RM_IHPSG13_8192x32_c4_1P_WLDRV16X16 + + +XA_CTRL a_aclk_n a_tiel a_tiel a_tiel a_tiel a_tiel a_tiel A_CLK A_MEN a_dclk a_eclk a_pulse_h a_pulse_l a_pulse a_rclk A_REN a_cs a_wclk A_WEN VDD! VSS! / RM_IHPSG13_8192x32_c4_1P_CTRL + + +XA_ROWDEC a_addr_row<8> a_addr_row<7> a_addr_row<6> a_addr_row<5> a_addr_row<4> a_addr_row<3> a_addr_row<2> a_addr_row<1> a_addr_row<0> a_cs a_eclk a_wi<511> a_wi<510> a_wi<509> a_wi<508> a_wi<507> a_wi<506> a_wi<505> a_wi<504> a_wi<503> a_wi<502> a_wi<501> a_wi<500> a_wi<499> a_wi<498> a_wi<497> a_wi<496> a_wi<495> a_wi<494> a_wi<493> a_wi<492> a_wi<491> a_wi<490> a_wi<489> a_wi<488> a_wi<487> a_wi<486> a_wi<485> a_wi<484> a_wi<483> a_wi<482> a_wi<481> a_wi<480> a_wi<479> a_wi<478> a_wi<477> a_wi<476> a_wi<475> a_wi<474> a_wi<473> a_wi<472> a_wi<471> a_wi<470> a_wi<469> a_wi<468> a_wi<467> a_wi<466> a_wi<465> a_wi<464> a_wi<463> a_wi<462> a_wi<461> a_wi<460> a_wi<459> a_wi<458> a_wi<457> a_wi<456> a_wi<455> a_wi<454> a_wi<453> a_wi<452> a_wi<451> a_wi<450> a_wi<449> a_wi<448> a_wi<447> a_wi<446> a_wi<445> a_wi<444> a_wi<443> a_wi<442> a_wi<441> a_wi<440> a_wi<439> a_wi<438> a_wi<437> a_wi<436> a_wi<435> a_wi<434> a_wi<433> a_wi<432> a_wi<431> a_wi<430> a_wi<429> a_wi<428> a_wi<427> a_wi<426> a_wi<425> a_wi<424> a_wi<423> a_wi<422> a_wi<421> a_wi<420> a_wi<419> a_wi<418> a_wi<417> a_wi<416> a_wi<415> a_wi<414> a_wi<413> a_wi<412> a_wi<411> a_wi<410> a_wi<409> a_wi<408> a_wi<407> a_wi<406> a_wi<405> a_wi<404> a_wi<403> a_wi<402> a_wi<401> a_wi<400> a_wi<399> a_wi<398> a_wi<397> a_wi<396> a_wi<395> a_wi<394> a_wi<393> a_wi<392> a_wi<391> a_wi<390> a_wi<389> a_wi<388> a_wi<387> a_wi<386> a_wi<385> a_wi<384> a_wi<383> a_wi<382> a_wi<381> a_wi<380> a_wi<379> a_wi<378> a_wi<377> a_wi<376> a_wi<375> a_wi<374> a_wi<373> a_wi<372> a_wi<371> a_wi<370> a_wi<369> a_wi<368> a_wi<367> a_wi<366> a_wi<365> a_wi<364> a_wi<363> a_wi<362> a_wi<361> a_wi<360> a_wi<359> a_wi<358> a_wi<357> a_wi<356> a_wi<355> a_wi<354> a_wi<353> a_wi<352> a_wi<351> a_wi<350> a_wi<349> a_wi<348> a_wi<347> a_wi<346> a_wi<345> a_wi<344> a_wi<343> a_wi<342> a_wi<341> a_wi<340> a_wi<339> a_wi<338> a_wi<337> a_wi<336> a_wi<335> a_wi<334> a_wi<333> a_wi<332> a_wi<331> a_wi<330> a_wi<329> a_wi<328> a_wi<327> a_wi<326> a_wi<325> a_wi<324> a_wi<323> a_wi<322> a_wi<321> a_wi<320> a_wi<319> a_wi<318> a_wi<317> a_wi<316> a_wi<315> a_wi<314> a_wi<313> a_wi<312> a_wi<311> a_wi<310> a_wi<309> a_wi<308> a_wi<307> a_wi<306> a_wi<305> a_wi<304> a_wi<303> a_wi<302> a_wi<301> a_wi<300> a_wi<299> a_wi<298> a_wi<297> a_wi<296> a_wi<295> a_wi<294> a_wi<293> a_wi<292> a_wi<291> a_wi<290> a_wi<289> a_wi<288> a_wi<287> a_wi<286> a_wi<285> a_wi<284> a_wi<283> a_wi<282> a_wi<281> a_wi<280> a_wi<279> a_wi<278> a_wi<277> a_wi<276> a_wi<275> a_wi<274> a_wi<273> a_wi<272> a_wi<271> a_wi<270> a_wi<269> a_wi<268> a_wi<267> a_wi<266> a_wi<265> a_wi<264> a_wi<263> a_wi<262> a_wi<261> a_wi<260> a_wi<259> a_wi<258> a_wi<257> a_wi<256> a_wi<255> a_wi<254> a_wi<253> a_wi<252> a_wi<251> a_wi<250> a_wi<249> a_wi<248> a_wi<247> a_wi<246> a_wi<245> a_wi<244> a_wi<243> a_wi<242> a_wi<241> a_wi<240> a_wi<239> a_wi<238> a_wi<237> a_wi<236> a_wi<235> a_wi<234> a_wi<233> a_wi<232> a_wi<231> a_wi<230> a_wi<229> a_wi<228> a_wi<227> a_wi<226> a_wi<225> a_wi<224> a_wi<223> a_wi<222> a_wi<221> a_wi<220> a_wi<219> a_wi<218> a_wi<217> a_wi<216> a_wi<215> a_wi<214> a_wi<213> a_wi<212> a_wi<211> a_wi<210> a_wi<209> a_wi<208> a_wi<207> a_wi<206> a_wi<205> a_wi<204> a_wi<203> a_wi<202> a_wi<201> a_wi<200> a_wi<199> a_wi<198> a_wi<197> a_wi<196> a_wi<195> a_wi<194> a_wi<193> a_wi<192> a_wi<191> a_wi<190> a_wi<189> a_wi<188> a_wi<187> a_wi<186> a_wi<185> a_wi<184> a_wi<183> a_wi<182> a_wi<181> a_wi<180> a_wi<179> a_wi<178> a_wi<177> a_wi<176> a_wi<175> a_wi<174> a_wi<173> a_wi<172> a_wi<171> a_wi<170> a_wi<169> a_wi<168> a_wi<167> a_wi<166> a_wi<165> a_wi<164> a_wi<163> a_wi<162> a_wi<161> a_wi<160> a_wi<159> a_wi<158> a_wi<157> a_wi<156> a_wi<155> a_wi<154> a_wi<153> a_wi<152> a_wi<151> a_wi<150> a_wi<149> a_wi<148> a_wi<147> a_wi<146> a_wi<145> a_wi<144> a_wi<143> a_wi<142> a_wi<141> a_wi<140> a_wi<139> a_wi<138> a_wi<137> a_wi<136> a_wi<135> a_wi<134> a_wi<133> a_wi<132> a_wi<131> a_wi<130> a_wi<129> a_wi<128> a_wi<127> a_wi<126> a_wi<125> a_wi<124> a_wi<123> a_wi<122> a_wi<121> a_wi<120> a_wi<119> a_wi<118> a_wi<117> a_wi<116> a_wi<115> a_wi<114> a_wi<113> a_wi<112> a_wi<111> a_wi<110> a_wi<109> a_wi<108> a_wi<107> a_wi<106> a_wi<105> a_wi<104> a_wi<103> a_wi<102> a_wi<101> a_wi<100> a_wi<99> a_wi<98> a_wi<97> a_wi<96> a_wi<95> a_wi<94> a_wi<93> a_wi<92> a_wi<91> a_wi<90> a_wi<89> a_wi<88> a_wi<87> a_wi<86> a_wi<85> a_wi<84> a_wi<83> a_wi<82> a_wi<81> a_wi<80> a_wi<79> a_wi<78> a_wi<77> a_wi<76> a_wi<75> a_wi<74> a_wi<73> a_wi<72> a_wi<71> a_wi<70> a_wi<69> a_wi<68> a_wi<67> a_wi<66> a_wi<65> a_wi<64> a_wi<63> a_wi<62> a_wi<61> a_wi<60> a_wi<59> a_wi<58> a_wi<57> a_wi<56> a_wi<55> a_wi<54> a_wi<53> a_wi<52> a_wi<51> a_wi<50> a_wi<49> a_wi<48> a_wi<47> a_wi<46> a_wi<45> a_wi<44> a_wi<43> a_wi<42> a_wi<41> a_wi<40> a_wi<39> a_wi<38> a_wi<37> a_wi<36> a_wi<35> a_wi<34> a_wi<33> a_wi<32> a_wi<31> a_wi<30> a_wi<29> a_wi<28> a_wi<27> a_wi<26> a_wi<25> a_wi<24> a_wi<23> a_wi<22> a_wi<21> a_wi<20> a_wi<19> a_wi<18> a_wi<17> a_wi<16> a_wi<15> a_wi<14> a_wi<13> a_wi<12> a_wi<11> a_wi<10> a_wi<9> a_wi<8> a_wi<7> a_wi<6> a_wi<5> a_wi<4> a_wi<3> a_wi<2> a_wi<1> a_wi<0> VDD! VSS! / RM_IHPSG13_8192x32_c4_1P_ROWDEC9 +XA_ROWREG a_aclk_n A_ADDR<12> A_ADDR<11> A_ADDR<10> A_ADDR<9> A_ADDR<8> A_ADDR<7> A_ADDR<6> A_ADDR<5> A_ADDR<4> a_addr_row<8> a_addr_row<7> a_addr_row<6> a_addr_row<5> a_addr_row<4> a_addr_row<3> a_addr_row<2> a_addr_row<1> a_addr_row<0> a_tiel a_tiel a_tiel a_tiel a_tiel a_tiel a_tiel a_tiel a_tiel a_tiel VDD! VSS! / RM_IHPSG13_8192x32_c4_1P_ROWREG9 +XA_COLDEC a_aclk_n A_ADDR<3> A_ADDR<2> A_ADDR<1> A_ADDR<0> a_addr_col<1> a_addr_col<0> a_addr_dec<7> a_addr_dec<6> a_addr_dec<5> a_addr_dec<4> a_addr_dec<3> a_addr_dec<2> a_addr_dec<1> a_addr_dec<0> a_tiel a_tiel a_tiel a_tiel a_tiel VDD! VSS! / RM_IHPSG13_8192x32_c4_1P_COLDEC4 + + +XA_DLYH a_pulse a_pulse_h VDD! VSS! / RM_IHPSG13_8192x32_c4_1P_DLY_pcell_2 +XA_DLYL a_pulse_x a_pulse_l VDD! VSS! / RM_IHPSG13_8192x32_c4_1P_DLY_pcell_3 +XA_DLYMUX a_pulse_h A_DLY a_pulse_x VDD! VSS! / RM_IHPSG13_8192x32_c4_1P_DLY_MUX + +XCOLCTRL<31> a_addr_col_r<0> a_addr_dec_r<7> a_addr_dec_r<6> a_addr_dec_r<5> a_addr_dec_r<4> a_addr_dec_r<3> a_addr_dec_r<2> a_addr_dec_r<1> a_addr_dec_r<0> a_tiel a_tiel a_tiel a_blc_r<255> a_blc_r<254> a_blc_r<253> a_blc_r<252> a_blc_r<251> a_blc_r<250> a_blc_r<249> a_blc_r<248> a_blc_r<247> a_blc_r<246> a_blc_r<245> a_blc_r<244> a_blc_r<243> a_blc_r<242> a_blc_r<241> a_blc_r<240> a_blt_r<255> a_blt_r<254> a_blt_r<253> a_blt_r<252> a_blt_r<251> a_blt_r<250> a_blt_r<249> a_blt_r<248> a_blt_r<247> a_blt_r<246> a_blt_r<245> a_blt_r<244> a_blt_r<243> a_blt_r<242> a_blt_r<241> a_blt_r<240> a_tieh<31> a_dclk_n_r<15> a_dclk_n_r<16> a_dclk_p_r<15> a_dclk_p_r<16> A_DOUT<31> A_DIN<31> a_rclk_n_r<15> a_rclk_n_r<16> a_rclk_p_r<15> a_rclk_p_r<16> a_tieh<31> a_wclk_n_r<15> a_wclk_n_r<16> a_wclk_p_r<15> a_wclk_p_r<16> VDD! VSS! / RM_IHPSG13_8192x32_c4_1P_COLCTRL4 +XCOLCTRL<30> a_addr_col_r<0> a_addr_dec_r<7> a_addr_dec_r<6> a_addr_dec_r<5> a_addr_dec_r<4> a_addr_dec_r<3> a_addr_dec_r<2> a_addr_dec_r<1> a_addr_dec_r<0> a_tiel a_tiel a_tiel a_blc_r<239> a_blc_r<238> a_blc_r<237> a_blc_r<236> a_blc_r<235> a_blc_r<234> a_blc_r<233> a_blc_r<232> a_blc_r<231> a_blc_r<230> a_blc_r<229> a_blc_r<228> a_blc_r<227> a_blc_r<226> a_blc_r<225> a_blc_r<224> a_blt_r<239> a_blt_r<238> a_blt_r<237> a_blt_r<236> a_blt_r<235> a_blt_r<234> a_blt_r<233> a_blt_r<232> a_blt_r<231> a_blt_r<230> a_blt_r<229> a_blt_r<228> a_blt_r<227> a_blt_r<226> a_blt_r<225> a_blt_r<224> a_tieh<30> a_dclk_n_r<14> a_dclk_n_r<15> a_dclk_p_r<14> a_dclk_p_r<15> A_DOUT<30> A_DIN<30> a_rclk_n_r<14> a_rclk_n_r<15> a_rclk_p_r<14> a_rclk_p_r<15> a_tieh<30> a_wclk_n_r<14> a_wclk_n_r<15> a_wclk_p_r<14> a_wclk_p_r<15> VDD! VSS! / RM_IHPSG13_8192x32_c4_1P_COLCTRL4 +XCOLCTRL<29> a_addr_col_r<0> a_addr_dec_r<7> a_addr_dec_r<6> a_addr_dec_r<5> a_addr_dec_r<4> a_addr_dec_r<3> a_addr_dec_r<2> a_addr_dec_r<1> a_addr_dec_r<0> a_tiel a_tiel a_tiel a_blc_r<223> a_blc_r<222> a_blc_r<221> a_blc_r<220> a_blc_r<219> a_blc_r<218> a_blc_r<217> a_blc_r<216> a_blc_r<215> a_blc_r<214> a_blc_r<213> a_blc_r<212> a_blc_r<211> a_blc_r<210> a_blc_r<209> a_blc_r<208> a_blt_r<223> a_blt_r<222> a_blt_r<221> a_blt_r<220> a_blt_r<219> a_blt_r<218> a_blt_r<217> a_blt_r<216> a_blt_r<215> a_blt_r<214> a_blt_r<213> a_blt_r<212> a_blt_r<211> a_blt_r<210> a_blt_r<209> a_blt_r<208> a_tieh<29> a_dclk_n_r<13> a_dclk_n_r<14> a_dclk_p_r<13> a_dclk_p_r<14> A_DOUT<29> A_DIN<29> a_rclk_n_r<13> a_rclk_n_r<14> a_rclk_p_r<13> a_rclk_p_r<14> a_tieh<29> a_wclk_n_r<13> a_wclk_n_r<14> a_wclk_p_r<13> a_wclk_p_r<14> VDD! VSS! / RM_IHPSG13_8192x32_c4_1P_COLCTRL4 +XCOLCTRL<28> a_addr_col_r<0> a_addr_dec_r<7> a_addr_dec_r<6> a_addr_dec_r<5> a_addr_dec_r<4> a_addr_dec_r<3> a_addr_dec_r<2> a_addr_dec_r<1> a_addr_dec_r<0> a_tiel a_tiel a_tiel a_blc_r<207> a_blc_r<206> a_blc_r<205> a_blc_r<204> a_blc_r<203> a_blc_r<202> a_blc_r<201> a_blc_r<200> a_blc_r<199> a_blc_r<198> a_blc_r<197> a_blc_r<196> a_blc_r<195> a_blc_r<194> a_blc_r<193> a_blc_r<192> a_blt_r<207> a_blt_r<206> a_blt_r<205> a_blt_r<204> a_blt_r<203> a_blt_r<202> a_blt_r<201> a_blt_r<200> a_blt_r<199> a_blt_r<198> a_blt_r<197> a_blt_r<196> a_blt_r<195> a_blt_r<194> a_blt_r<193> a_blt_r<192> a_tieh<28> a_dclk_n_r<12> a_dclk_n_r<13> a_dclk_p_r<12> a_dclk_p_r<13> A_DOUT<28> A_DIN<28> a_rclk_n_r<12> a_rclk_n_r<13> a_rclk_p_r<12> a_rclk_p_r<13> a_tieh<28> a_wclk_n_r<12> a_wclk_n_r<13> a_wclk_p_r<12> a_wclk_p_r<13> VDD! VSS! / RM_IHPSG13_8192x32_c4_1P_COLCTRL4 +XCOLCTRL<27> a_addr_col_r<0> a_addr_dec_r<7> a_addr_dec_r<6> a_addr_dec_r<5> a_addr_dec_r<4> a_addr_dec_r<3> a_addr_dec_r<2> a_addr_dec_r<1> a_addr_dec_r<0> a_tiel a_tiel a_tiel a_blc_r<191> a_blc_r<190> a_blc_r<189> a_blc_r<188> a_blc_r<187> a_blc_r<186> a_blc_r<185> a_blc_r<184> a_blc_r<183> a_blc_r<182> a_blc_r<181> a_blc_r<180> a_blc_r<179> a_blc_r<178> a_blc_r<177> a_blc_r<176> a_blt_r<191> a_blt_r<190> a_blt_r<189> a_blt_r<188> a_blt_r<187> a_blt_r<186> a_blt_r<185> a_blt_r<184> a_blt_r<183> a_blt_r<182> a_blt_r<181> a_blt_r<180> a_blt_r<179> a_blt_r<178> a_blt_r<177> a_blt_r<176> a_tieh<27> a_dclk_n_r<11> a_dclk_n_r<12> a_dclk_p_r<11> a_dclk_p_r<12> A_DOUT<27> A_DIN<27> a_rclk_n_r<11> a_rclk_n_r<12> a_rclk_p_r<11> a_rclk_p_r<12> a_tieh<27> a_wclk_n_r<11> a_wclk_n_r<12> a_wclk_p_r<11> a_wclk_p_r<12> VDD! VSS! / RM_IHPSG13_8192x32_c4_1P_COLCTRL4 +XCOLCTRL<26> a_addr_col_r<0> a_addr_dec_r<7> a_addr_dec_r<6> a_addr_dec_r<5> a_addr_dec_r<4> a_addr_dec_r<3> a_addr_dec_r<2> a_addr_dec_r<1> a_addr_dec_r<0> a_tiel a_tiel a_tiel a_blc_r<175> a_blc_r<174> a_blc_r<173> a_blc_r<172> a_blc_r<171> a_blc_r<170> a_blc_r<169> a_blc_r<168> a_blc_r<167> a_blc_r<166> a_blc_r<165> a_blc_r<164> a_blc_r<163> a_blc_r<162> a_blc_r<161> a_blc_r<160> a_blt_r<175> a_blt_r<174> a_blt_r<173> a_blt_r<172> a_blt_r<171> a_blt_r<170> a_blt_r<169> a_blt_r<168> a_blt_r<167> a_blt_r<166> a_blt_r<165> a_blt_r<164> a_blt_r<163> a_blt_r<162> a_blt_r<161> a_blt_r<160> a_tieh<26> a_dclk_n_r<10> a_dclk_n_r<11> a_dclk_p_r<10> a_dclk_p_r<11> A_DOUT<26> A_DIN<26> a_rclk_n_r<10> a_rclk_n_r<11> a_rclk_p_r<10> a_rclk_p_r<11> a_tieh<26> a_wclk_n_r<10> a_wclk_n_r<11> a_wclk_p_r<10> a_wclk_p_r<11> VDD! VSS! / RM_IHPSG13_8192x32_c4_1P_COLCTRL4 +XCOLCTRL<25> a_addr_col_r<0> a_addr_dec_r<7> a_addr_dec_r<6> a_addr_dec_r<5> a_addr_dec_r<4> a_addr_dec_r<3> a_addr_dec_r<2> a_addr_dec_r<1> a_addr_dec_r<0> a_tiel a_tiel a_tiel a_blc_r<159> a_blc_r<158> a_blc_r<157> a_blc_r<156> a_blc_r<155> a_blc_r<154> a_blc_r<153> a_blc_r<152> a_blc_r<151> a_blc_r<150> a_blc_r<149> a_blc_r<148> a_blc_r<147> a_blc_r<146> a_blc_r<145> a_blc_r<144> a_blt_r<159> a_blt_r<158> a_blt_r<157> a_blt_r<156> a_blt_r<155> a_blt_r<154> a_blt_r<153> a_blt_r<152> a_blt_r<151> a_blt_r<150> a_blt_r<149> a_blt_r<148> a_blt_r<147> a_blt_r<146> a_blt_r<145> a_blt_r<144> a_tieh<25> a_dclk_n_r<9> a_dclk_n_r<10> a_dclk_p_r<9> a_dclk_p_r<10> A_DOUT<25> A_DIN<25> a_rclk_n_r<9> a_rclk_n_r<10> a_rclk_p_r<9> a_rclk_p_r<10> a_tieh<25> a_wclk_n_r<9> a_wclk_n_r<10> a_wclk_p_r<9> a_wclk_p_r<10> VDD! VSS! / RM_IHPSG13_8192x32_c4_1P_COLCTRL4 +XCOLCTRL<24> a_addr_col_r<0> a_addr_dec_r<7> a_addr_dec_r<6> a_addr_dec_r<5> a_addr_dec_r<4> a_addr_dec_r<3> a_addr_dec_r<2> a_addr_dec_r<1> a_addr_dec_r<0> a_tiel a_tiel a_tiel a_blc_r<143> a_blc_r<142> a_blc_r<141> a_blc_r<140> a_blc_r<139> a_blc_r<138> a_blc_r<137> a_blc_r<136> a_blc_r<135> a_blc_r<134> a_blc_r<133> a_blc_r<132> a_blc_r<131> a_blc_r<130> a_blc_r<129> a_blc_r<128> a_blt_r<143> a_blt_r<142> a_blt_r<141> a_blt_r<140> a_blt_r<139> a_blt_r<138> a_blt_r<137> a_blt_r<136> a_blt_r<135> a_blt_r<134> a_blt_r<133> a_blt_r<132> a_blt_r<131> a_blt_r<130> a_blt_r<129> a_blt_r<128> a_tieh<24> a_dclk_n_r<8> a_dclk_n_r<9> a_dclk_p_r<8> a_dclk_p_r<9> A_DOUT<24> A_DIN<24> a_rclk_n_r<8> a_rclk_n_r<9> a_rclk_p_r<8> a_rclk_p_r<9> a_tieh<24> a_wclk_n_r<8> a_wclk_n_r<9> a_wclk_p_r<8> a_wclk_p_r<9> VDD! VSS! / RM_IHPSG13_8192x32_c4_1P_COLCTRL4 +XCOLCTRL<23> a_addr_col_r<0> a_addr_dec_r<7> a_addr_dec_r<6> a_addr_dec_r<5> a_addr_dec_r<4> a_addr_dec_r<3> a_addr_dec_r<2> a_addr_dec_r<1> a_addr_dec_r<0> a_tiel a_tiel a_tiel a_blc_r<127> a_blc_r<126> a_blc_r<125> a_blc_r<124> a_blc_r<123> a_blc_r<122> a_blc_r<121> a_blc_r<120> a_blc_r<119> a_blc_r<118> a_blc_r<117> a_blc_r<116> a_blc_r<115> a_blc_r<114> a_blc_r<113> a_blc_r<112> a_blt_r<127> a_blt_r<126> a_blt_r<125> a_blt_r<124> a_blt_r<123> a_blt_r<122> a_blt_r<121> a_blt_r<120> a_blt_r<119> a_blt_r<118> a_blt_r<117> a_blt_r<116> a_blt_r<115> a_blt_r<114> a_blt_r<113> a_blt_r<112> a_tieh<23> a_dclk_n_r<7> a_dclk_n_r<8> a_dclk_p_r<7> a_dclk_p_r<8> A_DOUT<23> A_DIN<23> a_rclk_n_r<7> a_rclk_n_r<8> a_rclk_p_r<7> a_rclk_p_r<8> a_tieh<23> a_wclk_n_r<7> a_wclk_n_r<8> a_wclk_p_r<7> a_wclk_p_r<8> VDD! VSS! / RM_IHPSG13_8192x32_c4_1P_COLCTRL4 +XCOLCTRL<22> a_addr_col_r<0> a_addr_dec_r<7> a_addr_dec_r<6> a_addr_dec_r<5> a_addr_dec_r<4> a_addr_dec_r<3> a_addr_dec_r<2> a_addr_dec_r<1> a_addr_dec_r<0> a_tiel a_tiel a_tiel a_blc_r<111> a_blc_r<110> a_blc_r<109> a_blc_r<108> a_blc_r<107> a_blc_r<106> a_blc_r<105> a_blc_r<104> a_blc_r<103> a_blc_r<102> a_blc_r<101> a_blc_r<100> a_blc_r<99> a_blc_r<98> a_blc_r<97> a_blc_r<96> a_blt_r<111> a_blt_r<110> a_blt_r<109> a_blt_r<108> a_blt_r<107> a_blt_r<106> a_blt_r<105> a_blt_r<104> a_blt_r<103> a_blt_r<102> a_blt_r<101> a_blt_r<100> a_blt_r<99> a_blt_r<98> a_blt_r<97> a_blt_r<96> a_tieh<22> a_dclk_n_r<6> a_dclk_n_r<7> a_dclk_p_r<6> a_dclk_p_r<7> A_DOUT<22> A_DIN<22> a_rclk_n_r<6> a_rclk_n_r<7> a_rclk_p_r<6> a_rclk_p_r<7> a_tieh<22> a_wclk_n_r<6> a_wclk_n_r<7> a_wclk_p_r<6> a_wclk_p_r<7> VDD! VSS! / RM_IHPSG13_8192x32_c4_1P_COLCTRL4 +XCOLCTRL<21> a_addr_col_r<0> a_addr_dec_r<7> a_addr_dec_r<6> a_addr_dec_r<5> a_addr_dec_r<4> a_addr_dec_r<3> a_addr_dec_r<2> a_addr_dec_r<1> a_addr_dec_r<0> a_tiel a_tiel a_tiel a_blc_r<95> a_blc_r<94> a_blc_r<93> a_blc_r<92> a_blc_r<91> a_blc_r<90> a_blc_r<89> a_blc_r<88> a_blc_r<87> a_blc_r<86> a_blc_r<85> a_blc_r<84> a_blc_r<83> a_blc_r<82> a_blc_r<81> a_blc_r<80> a_blt_r<95> a_blt_r<94> a_blt_r<93> a_blt_r<92> a_blt_r<91> a_blt_r<90> a_blt_r<89> a_blt_r<88> a_blt_r<87> a_blt_r<86> a_blt_r<85> a_blt_r<84> a_blt_r<83> a_blt_r<82> a_blt_r<81> a_blt_r<80> a_tieh<21> a_dclk_n_r<5> a_dclk_n_r<6> a_dclk_p_r<5> a_dclk_p_r<6> A_DOUT<21> A_DIN<21> a_rclk_n_r<5> a_rclk_n_r<6> a_rclk_p_r<5> a_rclk_p_r<6> a_tieh<21> a_wclk_n_r<5> a_wclk_n_r<6> a_wclk_p_r<5> a_wclk_p_r<6> VDD! VSS! / RM_IHPSG13_8192x32_c4_1P_COLCTRL4 +XCOLCTRL<20> a_addr_col_r<0> a_addr_dec_r<7> a_addr_dec_r<6> a_addr_dec_r<5> a_addr_dec_r<4> a_addr_dec_r<3> a_addr_dec_r<2> a_addr_dec_r<1> a_addr_dec_r<0> a_tiel a_tiel a_tiel a_blc_r<79> a_blc_r<78> a_blc_r<77> a_blc_r<76> a_blc_r<75> a_blc_r<74> a_blc_r<73> a_blc_r<72> a_blc_r<71> a_blc_r<70> a_blc_r<69> a_blc_r<68> a_blc_r<67> a_blc_r<66> a_blc_r<65> a_blc_r<64> a_blt_r<79> a_blt_r<78> a_blt_r<77> a_blt_r<76> a_blt_r<75> a_blt_r<74> a_blt_r<73> a_blt_r<72> a_blt_r<71> a_blt_r<70> a_blt_r<69> a_blt_r<68> a_blt_r<67> a_blt_r<66> a_blt_r<65> a_blt_r<64> a_tieh<20> a_dclk_n_r<4> a_dclk_n_r<5> a_dclk_p_r<4> a_dclk_p_r<5> A_DOUT<20> A_DIN<20> a_rclk_n_r<4> a_rclk_n_r<5> a_rclk_p_r<4> a_rclk_p_r<5> a_tieh<20> a_wclk_n_r<4> a_wclk_n_r<5> a_wclk_p_r<4> a_wclk_p_r<5> VDD! VSS! / RM_IHPSG13_8192x32_c4_1P_COLCTRL4 +XCOLCTRL<19> a_addr_col_r<0> a_addr_dec_r<7> a_addr_dec_r<6> a_addr_dec_r<5> a_addr_dec_r<4> a_addr_dec_r<3> a_addr_dec_r<2> a_addr_dec_r<1> a_addr_dec_r<0> a_tiel a_tiel a_tiel a_blc_r<63> a_blc_r<62> a_blc_r<61> a_blc_r<60> a_blc_r<59> a_blc_r<58> a_blc_r<57> a_blc_r<56> a_blc_r<55> a_blc_r<54> a_blc_r<53> a_blc_r<52> a_blc_r<51> a_blc_r<50> a_blc_r<49> a_blc_r<48> a_blt_r<63> a_blt_r<62> a_blt_r<61> a_blt_r<60> a_blt_r<59> a_blt_r<58> a_blt_r<57> a_blt_r<56> a_blt_r<55> a_blt_r<54> a_blt_r<53> a_blt_r<52> a_blt_r<51> a_blt_r<50> a_blt_r<49> a_blt_r<48> a_tieh<19> a_dclk_n_r<3> a_dclk_n_r<4> a_dclk_p_r<3> a_dclk_p_r<4> A_DOUT<19> A_DIN<19> a_rclk_n_r<3> a_rclk_n_r<4> a_rclk_p_r<3> a_rclk_p_r<4> a_tieh<19> a_wclk_n_r<3> a_wclk_n_r<4> a_wclk_p_r<3> a_wclk_p_r<4> VDD! VSS! / RM_IHPSG13_8192x32_c4_1P_COLCTRL4 +XCOLCTRL<18> a_addr_col_r<0> a_addr_dec_r<7> a_addr_dec_r<6> a_addr_dec_r<5> a_addr_dec_r<4> a_addr_dec_r<3> a_addr_dec_r<2> a_addr_dec_r<1> a_addr_dec_r<0> a_tiel a_tiel a_tiel a_blc_r<47> a_blc_r<46> a_blc_r<45> a_blc_r<44> a_blc_r<43> a_blc_r<42> a_blc_r<41> a_blc_r<40> a_blc_r<39> a_blc_r<38> a_blc_r<37> a_blc_r<36> a_blc_r<35> a_blc_r<34> a_blc_r<33> a_blc_r<32> a_blt_r<47> a_blt_r<46> a_blt_r<45> a_blt_r<44> a_blt_r<43> a_blt_r<42> a_blt_r<41> a_blt_r<40> a_blt_r<39> a_blt_r<38> a_blt_r<37> a_blt_r<36> a_blt_r<35> a_blt_r<34> a_blt_r<33> a_blt_r<32> a_tieh<18> a_dclk_n_r<2> a_dclk_n_r<3> a_dclk_p_r<2> a_dclk_p_r<3> A_DOUT<18> A_DIN<18> a_rclk_n_r<2> a_rclk_n_r<3> a_rclk_p_r<2> a_rclk_p_r<3> a_tieh<18> a_wclk_n_r<2> a_wclk_n_r<3> a_wclk_p_r<2> a_wclk_p_r<3> VDD! VSS! / RM_IHPSG13_8192x32_c4_1P_COLCTRL4 +XCOLCTRL<17> a_addr_col_r<0> a_addr_dec_r<7> a_addr_dec_r<6> a_addr_dec_r<5> a_addr_dec_r<4> a_addr_dec_r<3> a_addr_dec_r<2> a_addr_dec_r<1> a_addr_dec_r<0> a_tiel a_tiel a_tiel a_blc_r<31> a_blc_r<30> a_blc_r<29> a_blc_r<28> a_blc_r<27> a_blc_r<26> a_blc_r<25> a_blc_r<24> a_blc_r<23> a_blc_r<22> a_blc_r<21> a_blc_r<20> a_blc_r<19> a_blc_r<18> a_blc_r<17> a_blc_r<16> a_blt_r<31> a_blt_r<30> a_blt_r<29> a_blt_r<28> a_blt_r<27> a_blt_r<26> a_blt_r<25> a_blt_r<24> a_blt_r<23> a_blt_r<22> a_blt_r<21> a_blt_r<20> a_blt_r<19> a_blt_r<18> a_blt_r<17> a_blt_r<16> a_tieh<17> a_dclk_n_r<1> a_dclk_n_r<2> a_dclk_p_r<1> a_dclk_p_r<2> A_DOUT<17> A_DIN<17> a_rclk_n_r<1> a_rclk_n_r<2> a_rclk_p_r<1> a_rclk_p_r<2> a_tieh<17> a_wclk_n_r<1> a_wclk_n_r<2> a_wclk_p_r<1> a_wclk_p_r<2> VDD! VSS! / RM_IHPSG13_8192x32_c4_1P_COLCTRL4 +XCOLCTRL<16> a_addr_col_r<0> a_addr_dec_r<7> a_addr_dec_r<6> a_addr_dec_r<5> a_addr_dec_r<4> a_addr_dec_r<3> a_addr_dec_r<2> a_addr_dec_r<1> a_addr_dec_r<0> a_tiel a_tiel a_tiel a_blc_r<15> a_blc_r<14> a_blc_r<13> a_blc_r<12> a_blc_r<11> a_blc_r<10> a_blc_r<9> a_blc_r<8> a_blc_r<7> a_blc_r<6> a_blc_r<5> a_blc_r<4> a_blc_r<3> a_blc_r<2> a_blc_r<1> a_blc_r<0> a_blt_r<15> a_blt_r<14> a_blt_r<13> a_blt_r<12> a_blt_r<11> a_blt_r<10> a_blt_r<9> a_blt_r<8> a_blt_r<7> a_blt_r<6> a_blt_r<5> a_blt_r<4> a_blt_r<3> a_blt_r<2> a_blt_r<1> a_blt_r<0> a_tieh<16> a_dclk_n_r<0> a_dclk_n_r<1> a_dclk_p_r<0> a_dclk_p_r<1> A_DOUT<16> A_DIN<16> a_rclk_n_r<0> a_rclk_n_r<1> a_rclk_p_r<0> a_rclk_p_r<1> a_tieh<16> a_wclk_n_r<0> a_wclk_n_r<1> a_wclk_p_r<0> a_wclk_p_r<1> VDD! VSS! / RM_IHPSG13_8192x32_c4_1P_COLCTRL4 +XCOLCTRL<15> a_addr_col_l<0> a_addr_dec_l<7> a_addr_dec_l<6> a_addr_dec_l<5> a_addr_dec_l<4> a_addr_dec_l<3> a_addr_dec_l<2> a_addr_dec_l<1> a_addr_dec_l<0> a_tiel a_tiel a_tiel a_blc_l<255> a_blc_l<254> a_blc_l<253> a_blc_l<252> a_blc_l<251> a_blc_l<250> a_blc_l<249> a_blc_l<248> a_blc_l<247> a_blc_l<246> a_blc_l<245> a_blc_l<244> a_blc_l<243> a_blc_l<242> a_blc_l<241> a_blc_l<240> a_blt_l<255> a_blt_l<254> a_blt_l<253> a_blt_l<252> a_blt_l<251> a_blt_l<250> a_blt_l<249> a_blt_l<248> a_blt_l<247> a_blt_l<246> a_blt_l<245> a_blt_l<244> a_blt_l<243> a_blt_l<242> a_blt_l<241> a_blt_l<240> a_tieh<0> a_dclk_n_l<15> a_dclk_n_l<16> a_dclk_p_l<15> a_dclk_p_l<16> A_DOUT<0> A_DIN<0> a_rclk_n_l<15> a_rclk_n_l<16> a_rclk_p_l<15> a_rclk_p_l<16> a_tieh<0> a_wclk_n_l<15> a_wclk_n_l<16> a_wclk_p_l<15> a_wclk_p_l<16> VDD! VSS! / RM_IHPSG13_8192x32_c4_1P_COLCTRL4 +XCOLCTRL<14> a_addr_col_l<0> a_addr_dec_l<7> a_addr_dec_l<6> a_addr_dec_l<5> a_addr_dec_l<4> a_addr_dec_l<3> a_addr_dec_l<2> a_addr_dec_l<1> a_addr_dec_l<0> a_tiel a_tiel a_tiel a_blc_l<239> a_blc_l<238> a_blc_l<237> a_blc_l<236> a_blc_l<235> a_blc_l<234> a_blc_l<233> a_blc_l<232> a_blc_l<231> a_blc_l<230> a_blc_l<229> a_blc_l<228> a_blc_l<227> a_blc_l<226> a_blc_l<225> a_blc_l<224> a_blt_l<239> a_blt_l<238> a_blt_l<237> a_blt_l<236> a_blt_l<235> a_blt_l<234> a_blt_l<233> a_blt_l<232> a_blt_l<231> a_blt_l<230> a_blt_l<229> a_blt_l<228> a_blt_l<227> a_blt_l<226> a_blt_l<225> a_blt_l<224> a_tieh<1> a_dclk_n_l<14> a_dclk_n_l<15> a_dclk_p_l<14> a_dclk_p_l<15> A_DOUT<1> A_DIN<1> a_rclk_n_l<14> a_rclk_n_l<15> a_rclk_p_l<14> a_rclk_p_l<15> a_tieh<1> a_wclk_n_l<14> a_wclk_n_l<15> a_wclk_p_l<14> a_wclk_p_l<15> VDD! VSS! / RM_IHPSG13_8192x32_c4_1P_COLCTRL4 +XCOLCTRL<13> a_addr_col_l<0> a_addr_dec_l<7> a_addr_dec_l<6> a_addr_dec_l<5> a_addr_dec_l<4> a_addr_dec_l<3> a_addr_dec_l<2> a_addr_dec_l<1> a_addr_dec_l<0> a_tiel a_tiel a_tiel a_blc_l<223> a_blc_l<222> a_blc_l<221> a_blc_l<220> a_blc_l<219> a_blc_l<218> a_blc_l<217> a_blc_l<216> a_blc_l<215> a_blc_l<214> a_blc_l<213> a_blc_l<212> a_blc_l<211> a_blc_l<210> a_blc_l<209> a_blc_l<208> a_blt_l<223> a_blt_l<222> a_blt_l<221> a_blt_l<220> a_blt_l<219> a_blt_l<218> a_blt_l<217> a_blt_l<216> a_blt_l<215> a_blt_l<214> a_blt_l<213> a_blt_l<212> a_blt_l<211> a_blt_l<210> a_blt_l<209> a_blt_l<208> a_tieh<2> a_dclk_n_l<13> a_dclk_n_l<14> a_dclk_p_l<13> a_dclk_p_l<14> A_DOUT<2> A_DIN<2> a_rclk_n_l<13> a_rclk_n_l<14> a_rclk_p_l<13> a_rclk_p_l<14> a_tieh<2> a_wclk_n_l<13> a_wclk_n_l<14> a_wclk_p_l<13> a_wclk_p_l<14> VDD! VSS! / RM_IHPSG13_8192x32_c4_1P_COLCTRL4 +XCOLCTRL<12> a_addr_col_l<0> a_addr_dec_l<7> a_addr_dec_l<6> a_addr_dec_l<5> a_addr_dec_l<4> a_addr_dec_l<3> a_addr_dec_l<2> a_addr_dec_l<1> a_addr_dec_l<0> a_tiel a_tiel a_tiel a_blc_l<207> a_blc_l<206> a_blc_l<205> a_blc_l<204> a_blc_l<203> a_blc_l<202> a_blc_l<201> a_blc_l<200> a_blc_l<199> a_blc_l<198> a_blc_l<197> a_blc_l<196> a_blc_l<195> a_blc_l<194> a_blc_l<193> a_blc_l<192> a_blt_l<207> a_blt_l<206> a_blt_l<205> a_blt_l<204> a_blt_l<203> a_blt_l<202> a_blt_l<201> a_blt_l<200> a_blt_l<199> a_blt_l<198> a_blt_l<197> a_blt_l<196> a_blt_l<195> a_blt_l<194> a_blt_l<193> a_blt_l<192> a_tieh<3> a_dclk_n_l<12> a_dclk_n_l<13> a_dclk_p_l<12> a_dclk_p_l<13> A_DOUT<3> A_DIN<3> a_rclk_n_l<12> a_rclk_n_l<13> a_rclk_p_l<12> a_rclk_p_l<13> a_tieh<3> a_wclk_n_l<12> a_wclk_n_l<13> a_wclk_p_l<12> a_wclk_p_l<13> VDD! VSS! / RM_IHPSG13_8192x32_c4_1P_COLCTRL4 +XCOLCTRL<11> a_addr_col_l<0> a_addr_dec_l<7> a_addr_dec_l<6> a_addr_dec_l<5> a_addr_dec_l<4> a_addr_dec_l<3> a_addr_dec_l<2> a_addr_dec_l<1> a_addr_dec_l<0> a_tiel a_tiel a_tiel a_blc_l<191> a_blc_l<190> a_blc_l<189> a_blc_l<188> a_blc_l<187> a_blc_l<186> a_blc_l<185> a_blc_l<184> a_blc_l<183> a_blc_l<182> a_blc_l<181> a_blc_l<180> a_blc_l<179> a_blc_l<178> a_blc_l<177> a_blc_l<176> a_blt_l<191> a_blt_l<190> a_blt_l<189> a_blt_l<188> a_blt_l<187> a_blt_l<186> a_blt_l<185> a_blt_l<184> a_blt_l<183> a_blt_l<182> a_blt_l<181> a_blt_l<180> a_blt_l<179> a_blt_l<178> a_blt_l<177> a_blt_l<176> a_tieh<4> a_dclk_n_l<11> a_dclk_n_l<12> a_dclk_p_l<11> a_dclk_p_l<12> A_DOUT<4> A_DIN<4> a_rclk_n_l<11> a_rclk_n_l<12> a_rclk_p_l<11> a_rclk_p_l<12> a_tieh<4> a_wclk_n_l<11> a_wclk_n_l<12> a_wclk_p_l<11> a_wclk_p_l<12> VDD! VSS! / RM_IHPSG13_8192x32_c4_1P_COLCTRL4 +XCOLCTRL<10> a_addr_col_l<0> a_addr_dec_l<7> a_addr_dec_l<6> a_addr_dec_l<5> a_addr_dec_l<4> a_addr_dec_l<3> a_addr_dec_l<2> a_addr_dec_l<1> a_addr_dec_l<0> a_tiel a_tiel a_tiel a_blc_l<175> a_blc_l<174> a_blc_l<173> a_blc_l<172> a_blc_l<171> a_blc_l<170> a_blc_l<169> a_blc_l<168> a_blc_l<167> a_blc_l<166> a_blc_l<165> a_blc_l<164> a_blc_l<163> a_blc_l<162> a_blc_l<161> a_blc_l<160> a_blt_l<175> a_blt_l<174> a_blt_l<173> a_blt_l<172> a_blt_l<171> a_blt_l<170> a_blt_l<169> a_blt_l<168> a_blt_l<167> a_blt_l<166> a_blt_l<165> a_blt_l<164> a_blt_l<163> a_blt_l<162> a_blt_l<161> a_blt_l<160> a_tieh<5> a_dclk_n_l<10> a_dclk_n_l<11> a_dclk_p_l<10> a_dclk_p_l<11> A_DOUT<5> A_DIN<5> a_rclk_n_l<10> a_rclk_n_l<11> a_rclk_p_l<10> a_rclk_p_l<11> a_tieh<5> a_wclk_n_l<10> a_wclk_n_l<11> a_wclk_p_l<10> a_wclk_p_l<11> VDD! VSS! / RM_IHPSG13_8192x32_c4_1P_COLCTRL4 +XCOLCTRL<9> a_addr_col_l<0> a_addr_dec_l<7> a_addr_dec_l<6> a_addr_dec_l<5> a_addr_dec_l<4> a_addr_dec_l<3> a_addr_dec_l<2> a_addr_dec_l<1> a_addr_dec_l<0> a_tiel a_tiel a_tiel a_blc_l<159> a_blc_l<158> a_blc_l<157> a_blc_l<156> a_blc_l<155> a_blc_l<154> a_blc_l<153> a_blc_l<152> a_blc_l<151> a_blc_l<150> a_blc_l<149> a_blc_l<148> a_blc_l<147> a_blc_l<146> a_blc_l<145> a_blc_l<144> a_blt_l<159> a_blt_l<158> a_blt_l<157> a_blt_l<156> a_blt_l<155> a_blt_l<154> a_blt_l<153> a_blt_l<152> a_blt_l<151> a_blt_l<150> a_blt_l<149> a_blt_l<148> a_blt_l<147> a_blt_l<146> a_blt_l<145> a_blt_l<144> a_tieh<6> a_dclk_n_l<9> a_dclk_n_l<10> a_dclk_p_l<9> a_dclk_p_l<10> A_DOUT<6> A_DIN<6> a_rclk_n_l<9> a_rclk_n_l<10> a_rclk_p_l<9> a_rclk_p_l<10> a_tieh<6> a_wclk_n_l<9> a_wclk_n_l<10> a_wclk_p_l<9> a_wclk_p_l<10> VDD! VSS! / RM_IHPSG13_8192x32_c4_1P_COLCTRL4 +XCOLCTRL<8> a_addr_col_l<0> a_addr_dec_l<7> a_addr_dec_l<6> a_addr_dec_l<5> a_addr_dec_l<4> a_addr_dec_l<3> a_addr_dec_l<2> a_addr_dec_l<1> a_addr_dec_l<0> a_tiel a_tiel a_tiel a_blc_l<143> a_blc_l<142> a_blc_l<141> a_blc_l<140> a_blc_l<139> a_blc_l<138> a_blc_l<137> a_blc_l<136> a_blc_l<135> a_blc_l<134> a_blc_l<133> a_blc_l<132> a_blc_l<131> a_blc_l<130> a_blc_l<129> a_blc_l<128> a_blt_l<143> a_blt_l<142> a_blt_l<141> a_blt_l<140> a_blt_l<139> a_blt_l<138> a_blt_l<137> a_blt_l<136> a_blt_l<135> a_blt_l<134> a_blt_l<133> a_blt_l<132> a_blt_l<131> a_blt_l<130> a_blt_l<129> a_blt_l<128> a_tieh<7> a_dclk_n_l<8> a_dclk_n_l<9> a_dclk_p_l<8> a_dclk_p_l<9> A_DOUT<7> A_DIN<7> a_rclk_n_l<8> a_rclk_n_l<9> a_rclk_p_l<8> a_rclk_p_l<9> a_tieh<7> a_wclk_n_l<8> a_wclk_n_l<9> a_wclk_p_l<8> a_wclk_p_l<9> VDD! VSS! / RM_IHPSG13_8192x32_c4_1P_COLCTRL4 +XCOLCTRL<7> a_addr_col_l<0> a_addr_dec_l<7> a_addr_dec_l<6> a_addr_dec_l<5> a_addr_dec_l<4> a_addr_dec_l<3> a_addr_dec_l<2> a_addr_dec_l<1> a_addr_dec_l<0> a_tiel a_tiel a_tiel a_blc_l<127> a_blc_l<126> a_blc_l<125> a_blc_l<124> a_blc_l<123> a_blc_l<122> a_blc_l<121> a_blc_l<120> a_blc_l<119> a_blc_l<118> a_blc_l<117> a_blc_l<116> a_blc_l<115> a_blc_l<114> a_blc_l<113> a_blc_l<112> a_blt_l<127> a_blt_l<126> a_blt_l<125> a_blt_l<124> a_blt_l<123> a_blt_l<122> a_blt_l<121> a_blt_l<120> a_blt_l<119> a_blt_l<118> a_blt_l<117> a_blt_l<116> a_blt_l<115> a_blt_l<114> a_blt_l<113> a_blt_l<112> a_tieh<8> a_dclk_n_l<7> a_dclk_n_l<8> a_dclk_p_l<7> a_dclk_p_l<8> A_DOUT<8> A_DIN<8> a_rclk_n_l<7> a_rclk_n_l<8> a_rclk_p_l<7> a_rclk_p_l<8> a_tieh<8> a_wclk_n_l<7> a_wclk_n_l<8> a_wclk_p_l<7> a_wclk_p_l<8> VDD! VSS! / RM_IHPSG13_8192x32_c4_1P_COLCTRL4 +XCOLCTRL<6> a_addr_col_l<0> a_addr_dec_l<7> a_addr_dec_l<6> a_addr_dec_l<5> a_addr_dec_l<4> a_addr_dec_l<3> a_addr_dec_l<2> a_addr_dec_l<1> a_addr_dec_l<0> a_tiel a_tiel a_tiel a_blc_l<111> a_blc_l<110> a_blc_l<109> a_blc_l<108> a_blc_l<107> a_blc_l<106> a_blc_l<105> a_blc_l<104> a_blc_l<103> a_blc_l<102> a_blc_l<101> a_blc_l<100> a_blc_l<99> a_blc_l<98> a_blc_l<97> a_blc_l<96> a_blt_l<111> a_blt_l<110> a_blt_l<109> a_blt_l<108> a_blt_l<107> a_blt_l<106> a_blt_l<105> a_blt_l<104> a_blt_l<103> a_blt_l<102> a_blt_l<101> a_blt_l<100> a_blt_l<99> a_blt_l<98> a_blt_l<97> a_blt_l<96> a_tieh<9> a_dclk_n_l<6> a_dclk_n_l<7> a_dclk_p_l<6> a_dclk_p_l<7> A_DOUT<9> A_DIN<9> a_rclk_n_l<6> a_rclk_n_l<7> a_rclk_p_l<6> a_rclk_p_l<7> a_tieh<9> a_wclk_n_l<6> a_wclk_n_l<7> a_wclk_p_l<6> a_wclk_p_l<7> VDD! VSS! / RM_IHPSG13_8192x32_c4_1P_COLCTRL4 +XCOLCTRL<5> a_addr_col_l<0> a_addr_dec_l<7> a_addr_dec_l<6> a_addr_dec_l<5> a_addr_dec_l<4> a_addr_dec_l<3> a_addr_dec_l<2> a_addr_dec_l<1> a_addr_dec_l<0> a_tiel a_tiel a_tiel a_blc_l<95> a_blc_l<94> a_blc_l<93> a_blc_l<92> a_blc_l<91> a_blc_l<90> a_blc_l<89> a_blc_l<88> a_blc_l<87> a_blc_l<86> a_blc_l<85> a_blc_l<84> a_blc_l<83> a_blc_l<82> a_blc_l<81> a_blc_l<80> a_blt_l<95> a_blt_l<94> a_blt_l<93> a_blt_l<92> a_blt_l<91> a_blt_l<90> a_blt_l<89> a_blt_l<88> a_blt_l<87> a_blt_l<86> a_blt_l<85> a_blt_l<84> a_blt_l<83> a_blt_l<82> a_blt_l<81> a_blt_l<80> a_tieh<10> a_dclk_n_l<5> a_dclk_n_l<6> a_dclk_p_l<5> a_dclk_p_l<6> A_DOUT<10> A_DIN<10> a_rclk_n_l<5> a_rclk_n_l<6> a_rclk_p_l<5> a_rclk_p_l<6> a_tieh<10> a_wclk_n_l<5> a_wclk_n_l<6> a_wclk_p_l<5> a_wclk_p_l<6> VDD! VSS! / RM_IHPSG13_8192x32_c4_1P_COLCTRL4 +XCOLCTRL<4> a_addr_col_l<0> a_addr_dec_l<7> a_addr_dec_l<6> a_addr_dec_l<5> a_addr_dec_l<4> a_addr_dec_l<3> a_addr_dec_l<2> a_addr_dec_l<1> a_addr_dec_l<0> a_tiel a_tiel a_tiel a_blc_l<79> a_blc_l<78> a_blc_l<77> a_blc_l<76> a_blc_l<75> a_blc_l<74> a_blc_l<73> a_blc_l<72> a_blc_l<71> a_blc_l<70> a_blc_l<69> a_blc_l<68> a_blc_l<67> a_blc_l<66> a_blc_l<65> a_blc_l<64> a_blt_l<79> a_blt_l<78> a_blt_l<77> a_blt_l<76> a_blt_l<75> a_blt_l<74> a_blt_l<73> a_blt_l<72> a_blt_l<71> a_blt_l<70> a_blt_l<69> a_blt_l<68> a_blt_l<67> a_blt_l<66> a_blt_l<65> a_blt_l<64> a_tieh<11> a_dclk_n_l<4> a_dclk_n_l<5> a_dclk_p_l<4> a_dclk_p_l<5> A_DOUT<11> A_DIN<11> a_rclk_n_l<4> a_rclk_n_l<5> a_rclk_p_l<4> a_rclk_p_l<5> a_tieh<11> a_wclk_n_l<4> a_wclk_n_l<5> a_wclk_p_l<4> a_wclk_p_l<5> VDD! VSS! / RM_IHPSG13_8192x32_c4_1P_COLCTRL4 +XCOLCTRL<3> a_addr_col_l<0> a_addr_dec_l<7> a_addr_dec_l<6> a_addr_dec_l<5> a_addr_dec_l<4> a_addr_dec_l<3> a_addr_dec_l<2> a_addr_dec_l<1> a_addr_dec_l<0> a_tiel a_tiel a_tiel a_blc_l<63> a_blc_l<62> a_blc_l<61> a_blc_l<60> a_blc_l<59> a_blc_l<58> a_blc_l<57> a_blc_l<56> a_blc_l<55> a_blc_l<54> a_blc_l<53> a_blc_l<52> a_blc_l<51> a_blc_l<50> a_blc_l<49> a_blc_l<48> a_blt_l<63> a_blt_l<62> a_blt_l<61> a_blt_l<60> a_blt_l<59> a_blt_l<58> a_blt_l<57> a_blt_l<56> a_blt_l<55> a_blt_l<54> a_blt_l<53> a_blt_l<52> a_blt_l<51> a_blt_l<50> a_blt_l<49> a_blt_l<48> a_tieh<12> a_dclk_n_l<3> a_dclk_n_l<4> a_dclk_p_l<3> a_dclk_p_l<4> A_DOUT<12> A_DIN<12> a_rclk_n_l<3> a_rclk_n_l<4> a_rclk_p_l<3> a_rclk_p_l<4> a_tieh<12> a_wclk_n_l<3> a_wclk_n_l<4> a_wclk_p_l<3> a_wclk_p_l<4> VDD! VSS! / RM_IHPSG13_8192x32_c4_1P_COLCTRL4 +XCOLCTRL<2> a_addr_col_l<0> a_addr_dec_l<7> a_addr_dec_l<6> a_addr_dec_l<5> a_addr_dec_l<4> a_addr_dec_l<3> a_addr_dec_l<2> a_addr_dec_l<1> a_addr_dec_l<0> a_tiel a_tiel a_tiel a_blc_l<47> a_blc_l<46> a_blc_l<45> a_blc_l<44> a_blc_l<43> a_blc_l<42> a_blc_l<41> a_blc_l<40> a_blc_l<39> a_blc_l<38> a_blc_l<37> a_blc_l<36> a_blc_l<35> a_blc_l<34> a_blc_l<33> a_blc_l<32> a_blt_l<47> a_blt_l<46> a_blt_l<45> a_blt_l<44> a_blt_l<43> a_blt_l<42> a_blt_l<41> a_blt_l<40> a_blt_l<39> a_blt_l<38> a_blt_l<37> a_blt_l<36> a_blt_l<35> a_blt_l<34> a_blt_l<33> a_blt_l<32> a_tieh<13> a_dclk_n_l<2> a_dclk_n_l<3> a_dclk_p_l<2> a_dclk_p_l<3> A_DOUT<13> A_DIN<13> a_rclk_n_l<2> a_rclk_n_l<3> a_rclk_p_l<2> a_rclk_p_l<3> a_tieh<13> a_wclk_n_l<2> a_wclk_n_l<3> a_wclk_p_l<2> a_wclk_p_l<3> VDD! VSS! / RM_IHPSG13_8192x32_c4_1P_COLCTRL4 +XCOLCTRL<1> a_addr_col_l<0> a_addr_dec_l<7> a_addr_dec_l<6> a_addr_dec_l<5> a_addr_dec_l<4> a_addr_dec_l<3> a_addr_dec_l<2> a_addr_dec_l<1> a_addr_dec_l<0> a_tiel a_tiel a_tiel a_blc_l<31> a_blc_l<30> a_blc_l<29> a_blc_l<28> a_blc_l<27> a_blc_l<26> a_blc_l<25> a_blc_l<24> a_blc_l<23> a_blc_l<22> a_blc_l<21> a_blc_l<20> a_blc_l<19> a_blc_l<18> a_blc_l<17> a_blc_l<16> a_blt_l<31> a_blt_l<30> a_blt_l<29> a_blt_l<28> a_blt_l<27> a_blt_l<26> a_blt_l<25> a_blt_l<24> a_blt_l<23> a_blt_l<22> a_blt_l<21> a_blt_l<20> a_blt_l<19> a_blt_l<18> a_blt_l<17> a_blt_l<16> a_tieh<14> a_dclk_n_l<1> a_dclk_n_l<2> a_dclk_p_l<1> a_dclk_p_l<2> A_DOUT<14> A_DIN<14> a_rclk_n_l<1> a_rclk_n_l<2> a_rclk_p_l<1> a_rclk_p_l<2> a_tieh<14> a_wclk_n_l<1> a_wclk_n_l<2> a_wclk_p_l<1> a_wclk_p_l<2> VDD! VSS! / RM_IHPSG13_8192x32_c4_1P_COLCTRL4 +XCOLCTRL<0> a_addr_col_l<0> a_addr_dec_l<7> a_addr_dec_l<6> a_addr_dec_l<5> a_addr_dec_l<4> a_addr_dec_l<3> a_addr_dec_l<2> a_addr_dec_l<1> a_addr_dec_l<0> a_tiel a_tiel a_tiel a_blc_l<15> a_blc_l<14> a_blc_l<13> a_blc_l<12> a_blc_l<11> a_blc_l<10> a_blc_l<9> a_blc_l<8> a_blc_l<7> a_blc_l<6> a_blc_l<5> a_blc_l<4> a_blc_l<3> a_blc_l<2> a_blc_l<1> a_blc_l<0> a_blt_l<15> a_blt_l<14> a_blt_l<13> a_blt_l<12> a_blt_l<11> a_blt_l<10> a_blt_l<9> a_blt_l<8> a_blt_l<7> a_blt_l<6> a_blt_l<5> a_blt_l<4> a_blt_l<3> a_blt_l<2> a_blt_l<1> a_blt_l<0> a_tieh<15> a_dclk_n_l<0> a_dclk_n_l<1> a_dclk_p_l<0> a_dclk_p_l<1> A_DOUT<15> A_DIN<15> a_rclk_n_l<0> a_rclk_n_l<1> a_rclk_p_l<0> a_rclk_p_l<1> a_tieh<15> a_wclk_n_l<0> a_wclk_n_l<1> a_wclk_p_l<0> a_wclk_p_l<1> VDD! VSS! / RM_IHPSG13_8192x32_c4_1P_COLCTRL4 + + +XDRVFILL4<1> VDD! VSS! / RM_IHPSG13_8192x32_c4_1P_COLDRV13_FILL4 +XDRVFILL4<2> VDD! VSS! / RM_IHPSG13_8192x32_c4_1P_COLDRV13_FILL4 +XDRVFILL4<3> VDD! VSS! / RM_IHPSG13_8192x32_c4_1P_COLDRV13_FILL4 +XDRVFILL4<4> VDD! VSS! / RM_IHPSG13_8192x32_c4_1P_COLDRV13_FILL4 +XDRVFILL4<5> VDD! VSS! / RM_IHPSG13_8192x32_c4_1P_COLDRV13_FILL4 +XDRVFILL4<6> VDD! VSS! / RM_IHPSG13_8192x32_c4_1P_COLDRV13_FILL4 +.ENDS diff --git a/flow/platforms/ihp-sg13g2/cdl/RM_IHPSG13_2P_1024x16_c2_bm_bist.cdl b/flow/platforms/ihp-sg13g2/cdl/RM_IHPSG13_2P_1024x16_c2_bm_bist.cdl new file mode 100644 index 0000000000..71a04173e4 --- /dev/null +++ b/flow/platforms/ihp-sg13g2/cdl/RM_IHPSG13_2P_1024x16_c2_bm_bist.cdl @@ -0,0 +1,6450 @@ +* ------------------------------------------------------ +* +* Copyright 2025 IHP PDK Authors +* +* Licensed under the Apache License, Version 2.0 (the "License"); +* you may not use this file except in compliance with the License. +* You may obtain a copy of the License at +* +* https://www.apache.org/licenses/LICENSE-2.0 +* +* Unless required by applicable law or agreed to in writing, software +* distributed under the License is distributed on an "AS IS" BASIS, +* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +* See the License for the specific language governing permissions and +* limitations under the License. +* +* Generated on Tue Sep 9 10:49:23 2025 +* +* ------------------------------------------------------ + +.SUBCKT RM_IHPSG13_1024x16_c2_1P_BITKIT_CORNER NW PW VDD VSS +.ENDS +.SUBCKT RM_IHPSG13_1024x16_c2_1P_BITKIT_16x2_CORNER VDD_CORE VSS +XI16 VDD_CORE VSS VDD_CORE VSS / ++ RM_IHPSG13_1024x16_c2_1P_BITKIT_CORNER +.ENDS +.SUBCKT RM_IHPSG13_1024x16_c2_1P_BITKIT_EDGE_LR LWL NW PW VDD VSS +MN1 VSS LWL VSS VSS sg13_lv_nmos m=1 w=300.0n l=130.00n ng=1 nrd=0 nrs=0 +MN0 VSS net9 VSS VSS sg13_lv_nmos m=1 w=300.0n l=130.00n ng=1 nrd=0 nrs=0 +.ENDS +.SUBCKT RM_IHPSG13_1024x16_c2_1P_BITKIT_16x2_EDGE_LR A_WL<15> A_WL<14> A_WL<13> A_WL<12> ++ A_WL<11> A_WL<10> A_WL<9> A_WL<8> A_WL<7> A_WL<6> A_WL<5> A_WL<4> A_WL<3> ++ A_WL<2> A_WL<1> A_WL<0> VDD_CORE VSS +XI0<15> A_WL<15> VDD_CORE VSS VDD_CORE VSS / ++ RM_IHPSG13_1024x16_c2_1P_BITKIT_EDGE_LR +XI0<14> A_WL<14> VDD_CORE VSS VDD_CORE VSS / ++ RM_IHPSG13_1024x16_c2_1P_BITKIT_EDGE_LR +XI0<13> A_WL<13> VDD_CORE VSS VDD_CORE VSS / ++ RM_IHPSG13_1024x16_c2_1P_BITKIT_EDGE_LR +XI0<12> A_WL<12> VDD_CORE VSS VDD_CORE VSS / ++ RM_IHPSG13_1024x16_c2_1P_BITKIT_EDGE_LR +XI0<11> A_WL<11> VDD_CORE VSS VDD_CORE VSS / ++ RM_IHPSG13_1024x16_c2_1P_BITKIT_EDGE_LR +XI0<10> A_WL<10> VDD_CORE VSS VDD_CORE VSS / ++ RM_IHPSG13_1024x16_c2_1P_BITKIT_EDGE_LR +XI0<9> A_WL<9> VDD_CORE VSS VDD_CORE VSS / ++ RM_IHPSG13_1024x16_c2_1P_BITKIT_EDGE_LR +XI0<8> A_WL<8> VDD_CORE VSS VDD_CORE VSS / ++ RM_IHPSG13_1024x16_c2_1P_BITKIT_EDGE_LR +XI0<7> A_WL<7> VDD_CORE VSS VDD_CORE VSS / ++ RM_IHPSG13_1024x16_c2_1P_BITKIT_EDGE_LR +XI0<6> A_WL<6> VDD_CORE VSS VDD_CORE VSS / ++ RM_IHPSG13_1024x16_c2_1P_BITKIT_EDGE_LR +XI0<5> A_WL<5> VDD_CORE VSS VDD_CORE VSS / ++ RM_IHPSG13_1024x16_c2_1P_BITKIT_EDGE_LR +XI0<4> A_WL<4> VDD_CORE VSS VDD_CORE VSS / ++ RM_IHPSG13_1024x16_c2_1P_BITKIT_EDGE_LR +XI0<3> A_WL<3> VDD_CORE VSS VDD_CORE VSS / ++ RM_IHPSG13_1024x16_c2_1P_BITKIT_EDGE_LR +XI0<2> A_WL<2> VDD_CORE VSS VDD_CORE VSS / ++ RM_IHPSG13_1024x16_c2_1P_BITKIT_EDGE_LR +XI0<1> A_WL<1> VDD_CORE VSS VDD_CORE VSS / ++ RM_IHPSG13_1024x16_c2_1P_BITKIT_EDGE_LR +XI0<0> A_WL<0> VDD_CORE VSS VDD_CORE VSS / ++ RM_IHPSG13_1024x16_c2_1P_BITKIT_EDGE_LR +.ENDS +.SUBCKT RM_IHPSG13_1024x16_c2_1P_BITKIT_CELL BLC_BOT BLC_TOP BLT_BOT BLT_TOP LWL NW PW ++ RWL VDD VSS +MN0 NC NT VSS PW sg13_lv_nmos m=1 w=300.0n l=130.00n ng=1 nrd=0 nrs=0 +MN1 NT NC VSS PW sg13_lv_nmos m=1 w=300.0n l=130.00n ng=1 nrd=0 nrs=0 +MN3 NC RWL BLC_TOP PW sg13_lv_nmos m=1 w=300.0n l=130.00n ng=1 nrd=0 nrs=0 +MN2 BLT_BOT LWL NT PW sg13_lv_nmos m=1 w=300.0n l=130.00n ng=1 nrd=0 nrs=0 +MP1 NT NC VDD NW sg13_lv_pmos m=1 w=150.00n l=130.00n ng=1 nrd=0 nrs=0 +MP0 NC NT VDD NW sg13_lv_pmos m=1 w=150.00n l=130.00n ng=1 nrd=0 nrs=0 +R1 BLC_BOT BLC_TOP lvsres w=2.6e-07 l=6e-07 +R0 BLT_BOT BLT_TOP lvsres w=2.6e-07 l=6e-07 +R2 RWL LWL lvsres w=2.6e-07 l=6e-07 +.ENDS +.SUBCKT RM_IHPSG13_1024x16_c2_1P_BITKIT_16x2_SRAM A_BLC_BOT<1> A_BLC_BOT<0> A_BLC_TOP<1> ++ A_BLC_TOP<0> A_BLT_BOT<1> A_BLT_BOT<0> A_BLT_TOP<1> A_BLT_TOP<0> A_LWL<15> ++ A_LWL<14> A_LWL<13> A_LWL<12> A_LWL<11> A_LWL<10> A_LWL<9> A_LWL<8> A_LWL<7> ++ A_LWL<6> A_LWL<5> A_LWL<4> A_LWL<3> A_LWL<2> A_LWL<1> A_LWL<0> A_RWL<15> ++ A_RWL<14> A_RWL<13> A_RWL<12> A_RWL<11> A_RWL<10> A_RWL<9> A_RWL<8> A_RWL<7> ++ A_RWL<6> A_RWL<5> A_RWL<4> A_RWL<3> A_RWL<2> A_RWL<1> A_RWL<0> VDD_CORE ++ VSS +XCELL<31> A_BLC_TOP<1> A_RBLC<15> A_BLT_TOP<1> A_RBLT<15> A_RWL<15> ++ VDD_CORE VSS A_XWL<15> VDD_CORE VSS / ++ RM_IHPSG13_1024x16_c2_1P_BITKIT_CELL +XCELL<30> A_RBLC<14> A_RBLC<15> A_RBLT<14> A_RBLT<15> A_RWL<14> VDD_CORE ++ VSS A_XWL<14> VDD_CORE VSS / RM_IHPSG13_1024x16_c2_1P_BITKIT_CELL +XCELL<29> A_RBLC<14> A_RBLC<13> A_RBLT<14> A_RBLT<13> A_RWL<13> VDD_CORE ++ VSS A_XWL<13> VDD_CORE VSS / RM_IHPSG13_1024x16_c2_1P_BITKIT_CELL +XCELL<28> A_RBLC<12> A_RBLC<13> A_RBLT<12> A_RBLT<13> A_RWL<12> VDD_CORE ++ VSS A_XWL<12> VDD_CORE VSS / RM_IHPSG13_1024x16_c2_1P_BITKIT_CELL +XCELL<27> A_RBLC<12> A_RBLC<11> A_RBLT<12> A_RBLT<11> A_RWL<11> VDD_CORE ++ VSS A_XWL<11> VDD_CORE VSS / RM_IHPSG13_1024x16_c2_1P_BITKIT_CELL +XCELL<26> A_RBLC<10> A_RBLC<11> A_RBLT<10> A_RBLT<11> A_RWL<10> VDD_CORE ++ VSS A_XWL<10> VDD_CORE VSS / RM_IHPSG13_1024x16_c2_1P_BITKIT_CELL +XCELL<25> A_RBLC<10> A_RBLC<9> A_RBLT<10> A_RBLT<9> A_RWL<9> VDD_CORE ++ VSS A_XWL<9> VDD_CORE VSS / RM_IHPSG13_1024x16_c2_1P_BITKIT_CELL +XCELL<24> A_RBLC<8> A_RBLC<9> A_RBLT<8> A_RBLT<9> A_RWL<8> VDD_CORE ++ VSS A_XWL<8> VDD_CORE VSS / RM_IHPSG13_1024x16_c2_1P_BITKIT_CELL +XCELL<23> A_RBLC<8> A_RBLC<7> A_RBLT<8> A_RBLT<7> A_RWL<7> VDD_CORE ++ VSS A_XWL<7> VDD_CORE VSS / RM_IHPSG13_1024x16_c2_1P_BITKIT_CELL +XCELL<22> A_RBLC<6> A_RBLC<7> A_RBLT<6> A_RBLT<7> A_RWL<6> VDD_CORE ++ VSS A_XWL<6> VDD_CORE VSS / RM_IHPSG13_1024x16_c2_1P_BITKIT_CELL +XCELL<21> A_RBLC<6> A_RBLC<5> A_RBLT<6> A_RBLT<5> A_RWL<5> VDD_CORE ++ VSS A_XWL<5> VDD_CORE VSS / RM_IHPSG13_1024x16_c2_1P_BITKIT_CELL +XCELL<20> A_RBLC<4> A_RBLC<5> A_RBLT<4> A_RBLT<5> A_RWL<4> VDD_CORE ++ VSS A_XWL<4> VDD_CORE VSS / RM_IHPSG13_1024x16_c2_1P_BITKIT_CELL +XCELL<19> A_RBLC<4> A_RBLC<3> A_RBLT<4> A_RBLT<3> A_RWL<3> VDD_CORE ++ VSS A_XWL<3> VDD_CORE VSS / RM_IHPSG13_1024x16_c2_1P_BITKIT_CELL +XCELL<18> A_RBLC<2> A_RBLC<3> A_RBLT<2> A_RBLT<3> A_RWL<2> VDD_CORE ++ VSS A_XWL<2> VDD_CORE VSS / RM_IHPSG13_1024x16_c2_1P_BITKIT_CELL +XCELL<17> A_RBLC<2> A_RBLC<1> A_RBLT<2> A_RBLT<1> A_RWL<1> VDD_CORE ++ VSS A_XWL<1> VDD_CORE VSS / RM_IHPSG13_1024x16_c2_1P_BITKIT_CELL +XCELL<16> A_BLC_BOT<1> A_RBLC<1> A_BLT_BOT<1> A_RBLT<1> A_RWL<0> VDD_CORE ++ VSS A_XWL<0> VDD_CORE VSS / RM_IHPSG13_1024x16_c2_1P_BITKIT_CELL +XCELL<15> A_BLC_TOP<0> A_LBLC<15> A_BLT_TOP<0> A_LBLT<15> A_LWL<15> ++ VDD_CORE VSS A_XWL<15> VDD_CORE VSS / ++ RM_IHPSG13_1024x16_c2_1P_BITKIT_CELL +XCELL<14> A_LBLC<14> A_LBLC<15> A_LBLT<14> A_LBLT<15> A_LWL<14> VDD_CORE ++ VSS A_XWL<14> VDD_CORE VSS / RM_IHPSG13_1024x16_c2_1P_BITKIT_CELL +XCELL<13> A_LBLC<14> A_LBLC<13> A_LBLT<14> A_LBLT<13> A_LWL<13> VDD_CORE ++ VSS A_XWL<13> VDD_CORE VSS / RM_IHPSG13_1024x16_c2_1P_BITKIT_CELL +XCELL<12> A_LBLC<12> A_LBLC<13> A_LBLT<12> A_LBLT<13> A_LWL<12> VDD_CORE ++ VSS A_XWL<12> VDD_CORE VSS / RM_IHPSG13_1024x16_c2_1P_BITKIT_CELL +XCELL<11> A_LBLC<12> A_LBLC<11> A_LBLT<12> A_LBLT<11> A_LWL<11> VDD_CORE ++ VSS A_XWL<11> VDD_CORE VSS / RM_IHPSG13_1024x16_c2_1P_BITKIT_CELL +XCELL<10> A_LBLC<10> A_LBLC<11> A_LBLT<10> A_LBLT<11> A_LWL<10> VDD_CORE ++ VSS A_XWL<10> VDD_CORE VSS / RM_IHPSG13_1024x16_c2_1P_BITKIT_CELL +XCELL<9> A_LBLC<10> A_LBLC<9> A_LBLT<10> A_LBLT<9> A_LWL<9> VDD_CORE ++ VSS A_XWL<9> VDD_CORE VSS / RM_IHPSG13_1024x16_c2_1P_BITKIT_CELL +XCELL<8> A_LBLC<8> A_LBLC<9> A_LBLT<8> A_LBLT<9> A_LWL<8> VDD_CORE ++ VSS A_XWL<8> VDD_CORE VSS / RM_IHPSG13_1024x16_c2_1P_BITKIT_CELL +XCELL<7> A_LBLC<8> A_LBLC<7> A_LBLT<8> A_LBLT<7> A_LWL<7> VDD_CORE ++ VSS A_XWL<7> VDD_CORE VSS / RM_IHPSG13_1024x16_c2_1P_BITKIT_CELL +XCELL<6> A_LBLC<6> A_LBLC<7> A_LBLT<6> A_LBLT<7> A_LWL<6> VDD_CORE ++ VSS A_XWL<6> VDD_CORE VSS / RM_IHPSG13_1024x16_c2_1P_BITKIT_CELL +XCELL<5> A_LBLC<6> A_LBLC<5> A_LBLT<6> A_LBLT<5> A_LWL<5> VDD_CORE ++ VSS A_XWL<5> VDD_CORE VSS / RM_IHPSG13_1024x16_c2_1P_BITKIT_CELL +XCELL<4> A_LBLC<4> A_LBLC<5> A_LBLT<4> A_LBLT<5> A_LWL<4> VDD_CORE ++ VSS A_XWL<4> VDD_CORE VSS / RM_IHPSG13_1024x16_c2_1P_BITKIT_CELL +XCELL<3> A_LBLC<4> A_LBLC<3> A_LBLT<4> A_LBLT<3> A_LWL<3> VDD_CORE ++ VSS A_XWL<3> VDD_CORE VSS / RM_IHPSG13_1024x16_c2_1P_BITKIT_CELL +XCELL<2> A_LBLC<2> A_LBLC<3> A_LBLT<2> A_LBLT<3> A_LWL<2> VDD_CORE ++ VSS A_XWL<2> VDD_CORE VSS / RM_IHPSG13_1024x16_c2_1P_BITKIT_CELL +XCELL<1> A_LBLC<2> A_LBLC<1> A_LBLT<2> A_LBLT<1> A_LWL<1> VDD_CORE ++ VSS A_XWL<1> VDD_CORE VSS / RM_IHPSG13_1024x16_c2_1P_BITKIT_CELL +XCELL<0> A_BLC_BOT<0> A_LBLC<1> A_BLT_BOT<0> A_LBLT<1> A_LWL<0> VDD_CORE ++ VSS A_XWL<0> VDD_CORE VSS / RM_IHPSG13_1024x16_c2_1P_BITKIT_CELL +.ENDS +.SUBCKT RM_IHPSG13_1024x16_c2_1P_BITKIT_EDGE_TB BLC BLT NW PW VDD VSS +.ENDS +.SUBCKT RM_IHPSG13_1024x16_c2_1P_BITKIT_16x2_EDGE_TB A_BLC<1> A_BLC<0> A_BLT<1> A_BLT<0> ++ VDD_CORE VSS +XEDGE<1> A_BLC<1> A_BLT<1> VDD_CORE VSS VDD_CORE VSS ++ / RM_IHPSG13_1024x16_c2_1P_BITKIT_EDGE_TB +XEDGE<0> A_BLC<0> A_BLT<0> VDD_CORE VSS VDD_CORE VSS ++ / RM_IHPSG13_1024x16_c2_1P_BITKIT_EDGE_TB +.ENDS + +.SUBCKT RSC_IHPSG13_CBUFX4 A Z VDD VSS +MN0 net9 A VSS VSS sg13_lv_nmos m=1 w=705.000n l=130.00n ng=1 nrd=0 ++ nrs=0 +MN1 Z net9 VSS VSS sg13_lv_nmos m=1 w=1.41u l=130.00n ng=2 nrd=0 nrs=0 +MP0 net9 A VDD VDD sg13_lv_pmos m=1 w=1.62u l=130.00n ng=1 nrd=0 nrs=0 +MP1 Z net9 VDD VDD sg13_lv_pmos m=1 w=3.24u l=130.00n ng=2 nrd=0 nrs=0 +.ENDS +.SUBCKT RM_IHPSG13_1024x16_c2_1P_COLDRV13X4 ADDR_COL_I<1> ADDR_COL_I<0> ADDR_COL_O<1> ++ ADDR_COL_O<0> ADDR_DEC_I<7> ADDR_DEC_I<6> ADDR_DEC_I<5> ADDR_DEC_I<4> ++ ADDR_DEC_I<3> ADDR_DEC_I<2> ADDR_DEC_I<1> ADDR_DEC_I<0> ADDR_DEC_O<7> ++ ADDR_DEC_O<6> ADDR_DEC_O<5> ADDR_DEC_O<4> ADDR_DEC_O<3> ADDR_DEC_O<2> ++ ADDR_DEC_O<1> ADDR_DEC_O<0> DCLK_I DCLK_O RCLK_I RCLK_O WCLK_I WCLK_O ++ VDD VSS +XADDR_COL_DRV<1> ADDR_COL_I<1> ADDR_COL_O<1> VDD VSS / ++ RSC_IHPSG13_CBUFX4 +XADDR_COL_DRV<0> ADDR_COL_I<0> ADDR_COL_O<0> VDD VSS / ++ RSC_IHPSG13_CBUFX4 +XADDR_DEC_DRV<7> ADDR_DEC_I<7> ADDR_DEC_O<7> VDD VSS / ++ RSC_IHPSG13_CBUFX4 +XADDR_DEC_DRV<6> ADDR_DEC_I<6> ADDR_DEC_O<6> VDD VSS / ++ RSC_IHPSG13_CBUFX4 +XADDR_DEC_DRV<5> ADDR_DEC_I<5> ADDR_DEC_O<5> VDD VSS / ++ RSC_IHPSG13_CBUFX4 +XADDR_DEC_DRV<4> ADDR_DEC_I<4> ADDR_DEC_O<4> VDD VSS / ++ RSC_IHPSG13_CBUFX4 +XADDR_DEC_DRV<3> ADDR_DEC_I<3> ADDR_DEC_O<3> VDD VSS / ++ RSC_IHPSG13_CBUFX4 +XADDR_DEC_DRV<2> ADDR_DEC_I<2> ADDR_DEC_O<2> VDD VSS / ++ RSC_IHPSG13_CBUFX4 +XADDR_DEC_DRV<1> ADDR_DEC_I<1> ADDR_DEC_O<1> VDD VSS / ++ RSC_IHPSG13_CBUFX4 +XADDR_DEC_DRV<0> ADDR_DEC_I<0> ADDR_DEC_O<0> VDD VSS / ++ RSC_IHPSG13_CBUFX4 +XDCLK_DRV DCLK_I DCLK_O VDD VSS / RSC_IHPSG13_CBUFX4 +XRCLK_DRV RCLK_I RCLK_O VDD VSS / RSC_IHPSG13_CBUFX4 +XWCLK_DRV WCLK_I WCLK_O VDD VSS / RSC_IHPSG13_CBUFX4 +.ENDS +.SUBCKT RSC_IHPSG13_WLDRVX4 A Z VDD VSS +MN1 Z net6 VSS VSS sg13_lv_nmos m=1 w=705.000n l=130.00n ng=1 nrd=0 ++ nrs=0 +MN0 net6 A VSS VSS sg13_lv_nmos m=1 w=900.0n l=130.00n ng=1 nrd=0 nrs=0 +MP1 Z net6 VDD VDD sg13_lv_pmos m=1 w=3.24u l=130.00n ng=2 nrd=0 nrs=0 +MP0 net6 A VDD VDD sg13_lv_pmos m=1 w=900.0n l=130.00n ng=1 nrd=0 nrs=0 +.ENDS +.SUBCKT RM_IHPSG13_1024x16_c2_1P_WLDRV16X4 A<15> A<14> A<13> A<12> A<11> A<10> A<9> A<8> ++ A<7> A<6> A<5> A<4> A<3> A<2> A<1> A<0> Z<15> Z<14> Z<13> Z<12> Z<11> Z<10> ++ Z<9> Z<8> Z<7> Z<6> Z<5> Z<4> Z<3> Z<2> Z<1> Z<0> VDD VSS +XBUF<15> A<15> Z<15> VDD VSS / RSC_IHPSG13_WLDRVX4 +XBUF<14> A<14> Z<14> VDD VSS / RSC_IHPSG13_WLDRVX4 +XBUF<13> A<13> Z<13> VDD VSS / RSC_IHPSG13_WLDRVX4 +XBUF<12> A<12> Z<12> VDD VSS / RSC_IHPSG13_WLDRVX4 +XBUF<11> A<11> Z<11> VDD VSS / RSC_IHPSG13_WLDRVX4 +XBUF<10> A<10> Z<10> VDD VSS / RSC_IHPSG13_WLDRVX4 +XBUF<9> A<9> Z<9> VDD VSS / RSC_IHPSG13_WLDRVX4 +XBUF<8> A<8> Z<8> VDD VSS / RSC_IHPSG13_WLDRVX4 +XBUF<7> A<7> Z<7> VDD VSS / RSC_IHPSG13_WLDRVX4 +XBUF<6> A<6> Z<6> VDD VSS / RSC_IHPSG13_WLDRVX4 +XBUF<5> A<5> Z<5> VDD VSS / RSC_IHPSG13_WLDRVX4 +XBUF<4> A<4> Z<4> VDD VSS / RSC_IHPSG13_WLDRVX4 +XBUF<3> A<3> Z<3> VDD VSS / RSC_IHPSG13_WLDRVX4 +XBUF<2> A<2> Z<2> VDD VSS / RSC_IHPSG13_WLDRVX4 +XBUF<1> A<1> Z<1> VDD VSS / RSC_IHPSG13_WLDRVX4 +XBUF<0> A<0> Z<0> VDD VSS / RSC_IHPSG13_WLDRVX4 +.ENDS +.SUBCKT RSC_IHPSG13_FILLCAP8 VDD VSS +MN0 vss_r vdd_r VSS VSS sg13_lv_nmos m=1 w=4.98u l=130.00n ng=6 nrd=0 ++ nrs=0 +MP0 vdd_r vss_r VDD VDD sg13_lv_pmos m=1 w=6.48u l=385.000n ng=4 nrd=0 ++ nrs=0 +.ENDS +.SUBCKT RSC_IHPSG13_LHPQX2 CP D Q VDD VSS +MN3 QIN CPN net14 VSS sg13_lv_nmos m=1 w=480.00n l=130.00n ng=1 nrd=0 nrs=0 +MN2 net14 net10 VSS VSS sg13_lv_nmos m=1 w=480.00n l=130.00n ng=1 ++ nrd=0 nrs=0 +MN5 net21 D VSS VSS sg13_lv_nmos m=1 w=870.00n l=130.00n ng=1 nrd=0 ++ nrs=0 +MN6 QIN CP net21 VSS sg13_lv_nmos m=1 w=870.00n l=130.00n ng=1 nrd=0 nrs=0 +MN1 net10 QIN VSS VSS sg13_lv_nmos m=1 w=480.00n l=130.00n ng=1 nrd=0 ++ nrs=0 +MN0 CPN CP VSS VSS sg13_lv_nmos m=1 w=480.00n l=130.00n ng=1 nrd=0 ++ nrs=0 +MN4 Q QIN VSS VSS sg13_lv_nmos m=1 w=980.00n l=130.00n ng=1 nrd=0 nrs=0 +MP2 QIN CP net16 VDD sg13_lv_pmos m=1 w=480.00n l=130.00n ng=1 nrd=0 nrs=0 +MP0 CPN CP VDD VDD sg13_lv_pmos m=1 w=480.00n l=130.00n ng=1 nrd=0 ++ nrs=0 +MP4 Q QIN VDD VDD sg13_lv_pmos m=1 w=1.62u l=130.00n ng=1 nrd=0 nrs=0 +MP3 net10 QIN VDD VDD sg13_lv_pmos m=1 w=480.00n l=130.00n ng=1 nrd=0 ++ nrs=0 +MP1 net16 net10 VDD VDD sg13_lv_pmos m=1 w=480.00n l=130.00n ng=1 ++ nrd=0 nrs=0 +MP6 QIN CPN net20 VDD sg13_lv_pmos m=1 w=975.000n l=130.00n ng=1 nrd=0 ++ nrs=0 +MP5 net20 D VDD VDD sg13_lv_pmos m=1 w=975.000n l=130.00n ng=1 nrd=0 ++ nrs=0 +.ENDS +.SUBCKT RSC_IHPSG13_NAND2X2 A B Z VDD VSS +MP1 Z B VDD VDD sg13_lv_pmos m=1 w=1.62u l=130.00n ng=1 nrd=0 nrs=0 +MP0 Z A VDD VDD sg13_lv_pmos m=1 w=1.62u l=130.00n ng=1 nrd=0 nrs=0 +MN0 Z B net7 VSS sg13_lv_nmos m=1 w=980.00n l=130.00n ng=1 nrd=0 nrs=0 +MN1 net7 A VSS VSS sg13_lv_nmos m=1 w=980.00n l=130.00n ng=1 nrd=0 ++ nrs=0 +.ENDS +.SUBCKT RSC_IHPSG13_CINVX4 A Z VDD VSS +MN0 Z A VSS VSS sg13_lv_nmos m=1 w=1.41u l=130.00n ng=2 nrd=0 nrs=0 +MP0 Z A VDD VDD sg13_lv_pmos m=1 w=3.24u l=130.00n ng=2 nrd=0 nrs=0 +.ENDS +.SUBCKT RSC_IHPSG13_CINVX2 A Z VDD VSS +MN0 Z A VSS VSS sg13_lv_nmos m=1 w=705.000n l=130.00n ng=1 nrd=0 nrs=0 +MP0 Z A VDD VDD sg13_lv_pmos m=1 w=1.62u l=130.00n ng=1 nrd=0 nrs=0 +.ENDS +.SUBCKT RSC_IHPSG13_INVX2 A Z VDD VSS +MN0 Z A VSS VSS sg13_lv_nmos m=1 w=980.00n l=130.00n ng=1 nrd=0 nrs=0 +MP0 Z A VDD VDD sg13_lv_pmos m=1 w=1.62u l=130.00n ng=1 nrd=0 nrs=0 +.ENDS +.SUBCKT RSC_IHPSG13_NAND3X2 A B C Z VDD VSS +MP2 Z A VDD VDD sg13_lv_pmos m=1 w=1.62u l=130.00n ng=1 nrd=0 nrs=0 +MP1 Z B VDD VDD sg13_lv_pmos m=1 w=1.62u l=130.00n ng=1 nrd=0 nrs=0 +MP0 Z C VDD VDD sg13_lv_pmos m=1 w=1.62u l=130.00n ng=1 nrd=0 nrs=0 +MN1 net12 B net16 VSS sg13_lv_nmos m=1 w=980.00n l=130.00n ng=1 nrd=0 nrs=0 +MN0 Z C net12 VSS sg13_lv_nmos m=1 w=980.00n l=130.00n ng=1 nrd=0 nrs=0 +MN2 net16 A VSS VSS sg13_lv_nmos m=1 w=980.00n l=130.00n ng=1 nrd=0 ++ nrs=0 +.ENDS +.SUBCKT RSC_IHPSG13_NOR3X2 A B C Z VDD VSS +MP0 net13 A VDD VDD sg13_lv_pmos m=1 w=1.62u l=130.00n ng=1 nrd=0 nrs=0 +MP2 Z C net10 VDD sg13_lv_pmos m=1 w=1.62u l=130.00n ng=1 nrd=0 nrs=0 +MP1 net10 B net13 VDD sg13_lv_pmos m=1 w=1.62u l=130.00n ng=1 nrd=0 nrs=0 +MN1 Z B VSS VSS sg13_lv_nmos m=1 w=875.000n l=130.00n ng=1 nrd=0 nrs=0 +MN0 Z C VSS VSS sg13_lv_nmos m=1 w=875.000n l=130.00n ng=1 nrd=0 nrs=0 +MN2 Z A VSS VSS sg13_lv_nmos m=1 w=875.000n l=130.00n ng=1 nrd=0 nrs=0 +.ENDS +.SUBCKT RSC_IHPSG13_FILLCAP4 VDD VSS +MN0 vss_r vdd_r VSS VSS sg13_lv_nmos m=1 w=2.49u l=130.00n ng=3 nrd=0 ++ nrs=0 +MP0 vdd_r vss_r VDD VDD sg13_lv_pmos m=1 w=3.24u l=385.000n ng=2 nrd=0 ++ nrs=0 +.ENDS +.SUBCKT RSC_IHPSG13_MET2RES A B +R0 B A lvsres w=2.6e-07 l=6e-07 +.ENDS +.SUBCKT RM_IHPSG13_1024x16_c2_1P_DEC04 ADDR<3> ADDR<2> ADDR<1> ADDR<0> CS ECLK_H_BOT ++ ECLK_H_TOP ECLK_L_BOT ECLK_L_TOP WL<15> WL<14> WL<13> WL<12> WL<11> WL<10> ++ WL<9> WL<8> WL<7> WL<6> WL<5> WL<4> WL<3> WL<2> WL<1> WL<0> VDD VSS +XLATCH<3> CS ADDR<3> PADR<3> VDD VSS / RSC_IHPSG13_LHPQX2 +XLATCH<2> CS ADDR<2> PADR<2> VDD VSS / RSC_IHPSG13_LHPQX2 +XLATCH<1> CS ADDR<1> PADR<1> VDD VSS / RSC_IHPSG13_LHPQX2 +XLATCH<0> CS ADDR<0> PADR<0> VDD VSS / RSC_IHPSG13_LHPQX2 +XI0<3> PADR<1> PADR<0> sel01<3> VDD VSS / RSC_IHPSG13_NAND2X2 +XI0<2> PADR<1> NADR<0> sel01<2> VDD VSS / RSC_IHPSG13_NAND2X2 +XI0<1> NADR<1> PADR<0> sel01<1> VDD VSS / RSC_IHPSG13_NAND2X2 +XI0<0> NADR<1> NADR<0> sel01<0> VDD VSS / RSC_IHPSG13_NAND2X2 +XI4 ECLK_L_BOT EN VDD VSS / RSC_IHPSG13_CINVX4 +XI5 ECLK_H_BOT ECLK_L_BOT VDD VSS / RSC_IHPSG13_CINVX2 +XI3<3> PADR<3> NADR<3> VDD VSS / RSC_IHPSG13_INVX2 +XI3<2> PADR<2> NADR<2> VDD VSS / RSC_IHPSG13_INVX2 +XI3<1> PADR<1> NADR<1> VDD VSS / RSC_IHPSG13_INVX2 +XI3<0> PADR<0> NADR<0> VDD VSS / RSC_IHPSG13_INVX2 +XI1<3> PADR<2> PADR<3> CS sel23<3> VDD VSS / RSC_IHPSG13_NAND3X2 +XI1<2> NADR<2> PADR<3> CS sel23<2> VDD VSS / RSC_IHPSG13_NAND3X2 +XI1<1> PADR<2> NADR<3> CS sel23<1> VDD VSS / RSC_IHPSG13_NAND3X2 +XI1<0> NADR<2> NADR<3> CS sel23<0> VDD VSS / RSC_IHPSG13_NAND3X2 +XI2<15> sel23<3> sel01<3> EN WL<15> VDD VSS / RSC_IHPSG13_NOR3X2 +XI2<14> sel23<3> sel01<2> EN WL<14> VDD VSS / RSC_IHPSG13_NOR3X2 +XI2<13> sel23<3> sel01<1> EN WL<13> VDD VSS / RSC_IHPSG13_NOR3X2 +XI2<12> sel23<3> sel01<0> EN WL<12> VDD VSS / RSC_IHPSG13_NOR3X2 +XI2<11> sel23<2> sel01<3> EN WL<11> VDD VSS / RSC_IHPSG13_NOR3X2 +XI2<10> sel23<2> sel01<2> EN WL<10> VDD VSS / RSC_IHPSG13_NOR3X2 +XI2<9> sel23<2> sel01<1> EN WL<9> VDD VSS / RSC_IHPSG13_NOR3X2 +XI2<8> sel23<2> sel01<0> EN WL<8> VDD VSS / RSC_IHPSG13_NOR3X2 +XI2<7> sel23<1> sel01<3> EN WL<7> VDD VSS / RSC_IHPSG13_NOR3X2 +XI2<6> sel23<1> sel01<2> EN WL<6> VDD VSS / RSC_IHPSG13_NOR3X2 +XI2<5> sel23<1> sel01<1> EN WL<5> VDD VSS / RSC_IHPSG13_NOR3X2 +XI2<4> sel23<1> sel01<0> EN WL<4> VDD VSS / RSC_IHPSG13_NOR3X2 +XI2<3> sel23<0> sel01<3> EN WL<3> VDD VSS / RSC_IHPSG13_NOR3X2 +XI2<2> sel23<0> sel01<2> EN WL<2> VDD VSS / RSC_IHPSG13_NOR3X2 +XI2<1> sel23<0> sel01<1> EN WL<1> VDD VSS / RSC_IHPSG13_NOR3X2 +XI2<0> sel23<0> sel01<0> EN WL<0> VDD VSS / RSC_IHPSG13_NOR3X2 +XCAPS4 VDD VSS / RSC_IHPSG13_FILLCAP4 +XI11 ECLK_L_BOT ECLK_L_TOP / RSC_IHPSG13_MET2RES +XR0 ECLK_H_BOT ECLK_H_TOP / RSC_IHPSG13_MET2RES +.ENDS +.SUBCKT RM_IHPSG13_1024x16_c2_1P_ROWDEC4 ADDR_N_I<3> ADDR_N_I<2> ADDR_N_I<1> ADDR_N_I<0> ++ CS_I ECLK_I WL_O<15> WL_O<14> WL_O<13> WL_O<12> WL_O<11> WL_O<10> WL_O<9> ++ WL_O<8> WL_O<7> WL_O<6> WL_O<5> WL_O<4> WL_O<3> WL_O<2> WL_O<1> WL_O<0> ++ VDD VSS +XL2<8> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<7> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<6> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<5> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<4> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<3> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<2> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<1> VDD VSS / RSC_IHPSG13_FILLCAP8 +XSEL ADDR_N_I<3> ADDR_N_I<2> ADDR_N_I<1> ADDR_N_I<0> CS_I ECLK_I ECLK_H<1> ++ ECLK_B<0> ECLK_B<1> WL_O<15> WL_O<14> WL_O<13> WL_O<12> WL_O<11> WL_O<10> ++ WL_O<9> WL_O<8> WL_O<7> WL_O<6> WL_O<5> WL_O<4> WL_O<3> WL_O<2> WL_O<1> ++ WL_O<0> VDD VSS / RM_IHPSG13_1024x16_c2_1P_DEC04 +.ENDS +.SUBCKT RSC_IHPSG13_CINVX8 A Z VDD VSS +MN0 Z A VSS VSS sg13_lv_nmos m=1 w=2.82u l=130.00n ng=4 nrd=0 nrs=0 +MP0 Z A VDD VDD sg13_lv_pmos m=1 w=6.48u l=130.00n ng=4 nrd=0 nrs=0 +.ENDS +.SUBCKT RSC_IHPSG13_DFNQMX2IX1 BE BI CN D QI QIN VDD VSS +MN15 net026 BI VSS VSS sg13_lv_nmos m=1 w=560.00n l=130.00n ng=1 nrd=0 ++ nrs=0 +MN14 MXI_OUT BE net026 VSS sg13_lv_nmos m=1 w=560.00n l=130.00n ng=1 nrd=0 ++ nrs=0 +MN1 net025 D VSS VSS sg13_lv_nmos m=1 w=560.00n l=130.00n ng=1 nrd=0 ++ nrs=0 +MN0 MXI_OUT BEN net025 VSS sg13_lv_nmos m=1 w=560.00n l=130.00n ng=1 nrd=0 ++ nrs=0 +MN10 QI CNN net21 VSS sg13_lv_nmos m=1 w=850.00n l=130.00n ng=1 nrd=0 nrs=0 +MN11 net21 QI_MS VSS VSS sg13_lv_nmos m=1 w=850.00n l=130.00n ng=1 ++ nrd=0 nrs=0 +MN7 net30 QI_MS VSS VSS sg13_lv_nmos m=1 w=480.00n l=130.00n ng=1 ++ nrd=0 nrs=0 +MN6 QIN_MS CNN net30 VSS sg13_lv_nmos m=1 w=480.00n l=130.00n ng=1 nrd=0 ++ nrs=0 +MN3 QI_MS QIN_MS VSS VSS sg13_lv_nmos m=1 w=480.00n l=130.00n ng=1 ++ nrd=0 nrs=0 +MN12 CNN CN VSS VSS sg13_lv_nmos m=1 w=495.000n l=130.00n ng=1 nrd=0 ++ nrs=0 +MN9 net37 MXI_OUT VSS VSS sg13_lv_nmos m=1 w=870.00n l=130.00n ng=1 ++ nrd=0 nrs=0 +MN8 QIN_MS CN net37 VSS sg13_lv_nmos m=1 w=870.00n l=130.00n ng=1 nrd=0 ++ nrs=0 +MN5 QI CN net25 VSS sg13_lv_nmos m=1 w=480.00n l=130.00n ng=1 nrd=0 nrs=0 +MN4 net25 QIN VSS VSS sg13_lv_nmos m=1 w=480.00n l=130.00n ng=1 nrd=0 ++ nrs=0 +MN2 QIN QI VSS VSS sg13_lv_nmos m=1 w=480.00n l=130.00n ng=1 nrd=0 ++ nrs=0 +MN13 BEN BE VSS VSS sg13_lv_nmos m=1 w=560.00n l=130.00n ng=1 nrd=0 ++ nrs=0 +MP15 MXI_OUT BEN net027 VDD sg13_lv_pmos m=1 w=985.000n l=130.00n ng=1 ++ nrd=0 nrs=0 +MP14 net027 BI VDD VDD sg13_lv_pmos m=1 w=985.000n l=130.00n ng=1 ++ nrd=0 nrs=0 +MP1 MXI_OUT BE net024 VDD sg13_lv_pmos m=1 w=985.000n l=130.00n ng=1 nrd=0 ++ nrs=0 +MP0 net024 D VDD VDD sg13_lv_pmos m=1 w=985.000n l=130.00n ng=1 nrd=0 ++ nrs=0 +MP13 BEN BE VDD VDD sg13_lv_pmos m=1 w=645.000n l=130.00n ng=1 nrd=0 ++ nrs=0 +MP6 QI_MS QIN_MS VDD VDD sg13_lv_pmos m=1 w=480.00n l=130.00n ng=1 ++ nrd=0 nrs=0 +MP3 QI CNN net27 VDD sg13_lv_pmos m=1 w=480.00n l=130.00n ng=1 nrd=0 nrs=0 +MP2 net27 QIN VDD VDD sg13_lv_pmos m=1 w=480.00n l=130.00n ng=1 nrd=0 ++ nrs=0 +MP10 net36 MXI_OUT VDD VDD sg13_lv_pmos m=1 w=975.000n l=130.00n ng=1 ++ nrd=0 nrs=0 +MP11 QIN_MS CNN net36 VDD sg13_lv_pmos m=1 w=975.000n l=130.00n ng=1 nrd=0 ++ nrs=0 +MP4 net32 QI_MS VDD VDD sg13_lv_pmos m=1 w=480.00n l=130.00n ng=1 ++ nrd=0 nrs=0 +MP5 QIN_MS CN net32 VDD sg13_lv_pmos m=1 w=480.00n l=130.00n ng=1 nrd=0 ++ nrs=0 +MP7 QIN QI VDD VDD sg13_lv_pmos m=1 w=480.00n l=130.00n ng=1 nrd=0 ++ nrs=0 +MP12 CNN CN VDD VDD sg13_lv_pmos m=1 w=480.00n l=130.00n ng=1 nrd=0 ++ nrs=0 +MP9 QI CN net19 VDD sg13_lv_pmos m=1 w=990.00n l=130.00n ng=1 nrd=0 nrs=0 +MP8 net19 QI_MS VDD VDD sg13_lv_pmos m=1 w=990.00n l=130.00n ng=1 ++ nrd=0 nrs=0 +.ENDS +.SUBCKT RM_IHPSG13_1024x16_c2_1P_ROWREG4 ACLK_N_I ADDR_I<3> ADDR_I<2> ADDR_I<1> ADDR_I<0> ++ ADDR_N_O<3> ADDR_N_O<2> ADDR_N_O<1> ADDR_N_O<0> BIST_ADDR_I<3> ++ BIST_ADDR_I<2> BIST_ADDR_I<1> BIST_ADDR_I<0> BIST_EN_I VDD VSS +XINV<3> q_int<3> qn_int<3> VDD VSS / RSC_IHPSG13_CINVX2 +XINV<2> q_int<2> qn_int<2> VDD VSS / RSC_IHPSG13_CINVX2 +XINV<1> q_int<1> qn_int<1> VDD VSS / RSC_IHPSG13_CINVX2 +XINV<0> q_int<0> qn_int<0> VDD VSS / RSC_IHPSG13_CINVX2 +XDRV<3> qn_int<3> ADDR_N_O<3> VDD VSS / RSC_IHPSG13_CINVX8 +XDRV<2> qn_int<2> ADDR_N_O<2> VDD VSS / RSC_IHPSG13_CINVX8 +XDRV<1> qn_int<1> ADDR_N_O<1> VDD VSS / RSC_IHPSG13_CINVX8 +XDRV<0> qn_int<0> ADDR_N_O<0> VDD VSS / RSC_IHPSG13_CINVX8 +XDFF<3> BIST_EN_I BIST_ADDR_I<3> ACLK_N_I ADDR_I<3> q_int<3> net2<0> VDD ++ VSS / RSC_IHPSG13_DFNQMX2IX1 +XDFF<2> BIST_EN_I BIST_ADDR_I<2> ACLK_N_I ADDR_I<2> q_int<2> net2<1> VDD ++ VSS / RSC_IHPSG13_DFNQMX2IX1 +XDFF<1> BIST_EN_I BIST_ADDR_I<1> ACLK_N_I ADDR_I<1> q_int<1> net2<2> VDD ++ VSS / RSC_IHPSG13_DFNQMX2IX1 +XDFF<0> BIST_EN_I BIST_ADDR_I<0> ACLK_N_I ADDR_I<0> q_int<0> net2<3> VDD ++ VSS / RSC_IHPSG13_DFNQMX2IX1 +XI11<20> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI11<19> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI11<18> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI11<17> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI11<16> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI11<15> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI11<14> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI11<13> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI11<12> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI11<11> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI11<10> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI11<9> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI11<8> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI11<7> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI11<6> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI11<5> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI11<4> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI11<3> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI11<2> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI11<1> VDD VSS / RSC_IHPSG13_FILLCAP8 +.ENDS +.SUBCKT RSC_IHPSG13_CDLYX1 A Z VDD VSS +MN1 net010 net032 VSS VSS sg13_lv_nmos m=1 w=300.0n l=160.00n ng=1 ++ nrd=0 nrs=0 +MN2 net032 A net014 VSS sg13_lv_nmos m=1 w=300.0n l=160.00n ng=1 nrd=0 ++ nrs=0 +MN0 Z net032 net010 VSS sg13_lv_nmos m=1 w=300.0n l=160.00n ng=1 nrd=0 ++ nrs=0 +MN3 net014 A VSS VSS sg13_lv_nmos m=1 w=300.0n l=160.00n ng=1 nrd=0 ++ nrs=0 +MP1 Z net032 net07 VDD sg13_lv_pmos m=1 w=720.00n l=160.00n ng=1 nrd=0 ++ nrs=0 +MP3 net011 A VDD VDD sg13_lv_pmos m=1 w=720.00n l=160.00n ng=1 nrd=0 ++ nrs=0 +MP0 net07 net032 VDD VDD sg13_lv_pmos m=1 w=720.00n l=160.00n ng=1 ++ nrd=0 nrs=0 +MP2 net032 A net011 VDD sg13_lv_pmos m=1 w=720.00n l=160.00n ng=1 nrd=0 ++ nrs=0 +.ENDS +.SUBCKT RSC_IHPSG13_CDLYX1_DUMMY A Z VDD VSS +MN0 vss_r vdd_r VSS VSS sg13_lv_nmos m=1 w=2.49u l=300.0n ng=3 nrd=0 ++ nrs=0 +MP0 vdd_r vss_r VDD VDD sg13_lv_pmos m=1 w=3.24u l=640.00n ng=2 nrd=0 ++ nrs=0 +R0 Z A lvsres w=2.6e-07 l=6e-07 +.ENDS + +.SUBCKT RSC_IHPSG13_MX2IX1 A0 A1 S ZN VDD VSS +MP4 SN S VDD VDD sg13_lv_pmos m=1 w=645.000n l=130.00n ng=1 nrd=0 nrs=0 +MP3 ZN SN net12 VDD sg13_lv_pmos m=1 w=985.000n l=130.00n ng=1 nrd=0 nrs=0 +MP2 net12 A1 VDD VDD sg13_lv_pmos m=1 w=985.000n l=130.00n ng=1 nrd=0 ++ nrs=0 +MP1 ZN S net17 VDD sg13_lv_pmos m=1 w=985.000n l=130.00n ng=1 nrd=0 nrs=0 +MP0 net17 A0 VDD VDD sg13_lv_pmos m=1 w=985.000n l=130.00n ng=1 nrd=0 ++ nrs=0 +MN5 SN S VSS VSS sg13_lv_nmos m=1 w=480.00n l=130.00n ng=1 nrd=0 nrs=0 +MN3 net13 A1 VSS VSS sg13_lv_nmos m=1 w=480.00n l=130.00n ng=1 nrd=0 ++ nrs=0 +MN2 ZN S net13 VSS sg13_lv_nmos m=1 w=480.00n l=130.00n ng=1 nrd=0 nrs=0 +MN1 net15 A0 VSS VSS sg13_lv_nmos m=1 w=480.00n l=130.00n ng=1 nrd=0 ++ nrs=0 +MN0 ZN SN net15 VSS sg13_lv_nmos m=1 w=480.00n l=130.00n ng=1 nrd=0 nrs=0 +.ENDS +.SUBCKT RM_IHPSG13_1024x16_c2_1P_DLY_MUX A SEL Z VDD VSS +XI11 net4 Z VDD VSS / RSC_IHPSG13_CINVX2 +XI8 A D<3> SEL net4 VDD VSS / RSC_IHPSG13_MX2IX1 +XI20<3> D<2> D<3> VDD VSS / RSC_IHPSG13_CDLYX1 +XI20<2> D<1> D<2> VDD VSS / RSC_IHPSG13_CDLYX1 +XI20<1> A D<1> VDD VSS / RSC_IHPSG13_CDLYX1 +.ENDS +.SUBCKT RSC_IHPSG13_DFNQX2 CN D Q VDD VSS +MN0 Q QIN_SL VSS VSS sg13_lv_nmos m=1 w=980.00n l=130.00n ng=1 nrd=0 ++ nrs=0 +MN10 QIN_SL CNN net21 VSS sg13_lv_nmos m=1 w=850.00n l=130.00n ng=1 nrd=0 ++ nrs=0 +MN11 net21 QI_MS VSS VSS sg13_lv_nmos m=1 w=850.00n l=130.00n ng=1 ++ nrd=0 nrs=0 +MN7 net30 QI_MS VSS VSS sg13_lv_nmos m=1 w=480.00n l=130.00n ng=1 ++ nrd=0 nrs=0 +MN6 QIN_MS CNN net30 VSS sg13_lv_nmos m=1 w=480.00n l=130.00n ng=1 nrd=0 ++ nrs=0 +MN3 QI_MS QIN_MS VSS VSS sg13_lv_nmos m=1 w=480.00n l=130.00n ng=1 ++ nrd=0 nrs=0 +MN12 CNN CN VSS VSS sg13_lv_nmos m=1 w=495.000n l=130.00n ng=1 nrd=0 ++ nrs=0 +MN9 net37 D VSS VSS sg13_lv_nmos m=1 w=870.00n l=130.00n ng=1 nrd=0 ++ nrs=0 +MN8 QIN_MS CN net37 VSS sg13_lv_nmos m=1 w=870.00n l=130.00n ng=1 nrd=0 ++ nrs=0 +MN5 QIN_SL CN net25 VSS sg13_lv_nmos m=1 w=480.00n l=130.00n ng=1 nrd=0 ++ nrs=0 +MN4 net25 QI_SL VSS VSS sg13_lv_nmos m=1 w=480.00n l=130.00n ng=1 ++ nrd=0 nrs=0 +MN2 QI_SL QIN_SL VSS VSS sg13_lv_nmos m=1 w=480.00n l=130.00n ng=1 ++ nrd=0 nrs=0 +MP0 Q QIN_SL VDD VDD sg13_lv_pmos m=1 w=1.62u l=130.00n ng=1 nrd=0 ++ nrs=0 +MP6 QI_MS QIN_MS VDD VDD sg13_lv_pmos m=1 w=480.00n l=130.00n ng=1 ++ nrd=0 nrs=0 +MP3 QIN_SL CNN net27 VDD sg13_lv_pmos m=1 w=480.00n l=130.00n ng=1 nrd=0 ++ nrs=0 +MP2 net27 QI_SL VDD VDD sg13_lv_pmos m=1 w=480.00n l=130.00n ng=1 ++ nrd=0 nrs=0 +MP10 net36 D VDD VDD sg13_lv_pmos m=1 w=975.000n l=130.00n ng=1 nrd=0 ++ nrs=0 +MP11 QIN_MS CNN net36 VDD sg13_lv_pmos m=1 w=975.000n l=130.00n ng=1 nrd=0 ++ nrs=0 +MP4 net32 QI_MS VDD VDD sg13_lv_pmos m=1 w=480.00n l=130.00n ng=1 ++ nrd=0 nrs=0 +MP5 QIN_MS CN net32 VDD sg13_lv_pmos m=1 w=480.00n l=130.00n ng=1 nrd=0 ++ nrs=0 +MP7 QI_SL QIN_SL VDD VDD sg13_lv_pmos m=1 w=480.00n l=130.00n ng=1 ++ nrd=0 nrs=0 +MP12 CNN CN VDD VDD sg13_lv_pmos m=1 w=480.00n l=130.00n ng=1 nrd=0 ++ nrs=0 +MP9 QIN_SL CN net19 VDD sg13_lv_pmos m=1 w=990.00n l=130.00n ng=1 nrd=0 ++ nrs=0 +MP8 net19 QI_MS VDD VDD sg13_lv_pmos m=1 w=990.00n l=130.00n ng=1 ++ nrd=0 nrs=0 +.ENDS +.SUBCKT RSC_IHPSG13_CNAND2X2 A B Z VDD VSS +MN0 Z B net6 VSS sg13_lv_nmos m=1 w=980.00n l=130.00n ng=1 nrd=0 nrs=0 +MN1 net6 A VSS VSS sg13_lv_nmos m=1 w=980.00n l=130.00n ng=1 nrd=0 ++ nrs=0 +MP1 Z B VDD VDD sg13_lv_pmos m=1 w=1.62u l=130.00n ng=1 nrd=0 nrs=0 +MP0 Z A VDD VDD sg13_lv_pmos m=1 w=1.62u l=130.00n ng=1 nrd=0 nrs=0 +.ENDS +.SUBCKT RSC_IHPSG13_CGATEPX4 CP E Q VDD VSS +MN1 net08 QIN VSS VSS sg13_lv_nmos m=1 w=480.00n l=130.00n ng=1 nrd=0 ++ nrs=0 +MN2 net019 net08 VSS VSS sg13_lv_nmos m=1 w=480.00n l=130.00n ng=1 ++ nrd=0 nrs=0 +MN3 QIN CP net019 VSS sg13_lv_nmos m=1 w=480.00n l=130.00n ng=1 nrd=0 nrs=0 +MN6 Q net015 VSS VSS sg13_lv_nmos m=1 w=1.41u l=130.00n ng=2 nrd=0 ++ nrs=0 +MN5 net015 net08 net018 VSS sg13_lv_nmos m=1 w=980.00n l=130.00n ng=1 ++ nrd=0 nrs=0 +MN8 QIN CPN net023 VSS sg13_lv_nmos m=1 w=870.00n l=130.00n ng=1 nrd=0 ++ nrs=0 +MN7 net023 E VSS VSS sg13_lv_nmos m=1 w=870.00n l=130.00n ng=1 nrd=0 ++ nrs=0 +MN4 net018 CP VSS VSS sg13_lv_nmos m=1 w=980.00n l=130.00n ng=1 nrd=0 ++ nrs=0 +MN0 CPN CP VSS VSS sg13_lv_nmos m=1 w=500.0n l=130.00n ng=1 nrd=0 nrs=0 +MP3 net08 QIN VDD VDD sg13_lv_pmos m=1 w=480.00n l=130.00n ng=1 nrd=0 ++ nrs=0 +MP2 QIN CPN net017 VDD sg13_lv_pmos m=1 w=480.00n l=130.00n ng=1 nrd=0 ++ nrs=0 +MP1 net017 net08 VDD VDD sg13_lv_pmos m=1 w=480.00n l=130.00n ng=1 ++ nrd=0 nrs=0 +MP0 CPN CP VDD VDD sg13_lv_pmos m=1 w=500.0n l=130.00n ng=1 nrd=0 nrs=0 +MP8 QIN CP net024 VDD sg13_lv_pmos m=1 w=975.000n l=130.00n ng=1 nrd=0 ++ nrs=0 +MP7 net024 E VDD VDD sg13_lv_pmos m=1 w=975.000n l=130.00n ng=1 nrd=0 ++ nrs=0 +MP4 net015 CP VDD VDD sg13_lv_pmos m=1 w=1.27u l=130.00n ng=1 nrd=0 ++ nrs=0 +MP6 Q net015 VDD VDD sg13_lv_pmos m=1 w=3.24u l=130.00n ng=2 nrd=0 ++ nrs=0 +MP5 net015 net08 VDD VDD sg13_lv_pmos m=1 w=1.27u l=130.00n ng=1 nrd=0 ++ nrs=0 +.ENDS +.SUBCKT RSC_IHPSG13_CBUFX8 A Z VDD VSS +MP0 net4 A VDD VDD sg13_lv_pmos m=1 w=3.24u l=130.00n ng=2 nrd=0 nrs=0 +MP1 Z net4 VDD VDD sg13_lv_pmos m=1 w=6.48u l=130.00n ng=4 nrd=0 nrs=0 +MN1 Z net4 VSS VSS sg13_lv_nmos m=1 w=2.82u l=130.00n ng=4 nrd=0 nrs=0 +MN0 net4 A VSS VSS sg13_lv_nmos m=1 w=1.41u l=130.00n ng=2 nrd=0 nrs=0 +.ENDS +.SUBCKT RSC_IHPSG13_CDLYX2 A Z VDD VSS +MN2 net4 A net9 VSS sg13_lv_nmos m=1 w=320.00n l=200.0n ng=1 nrd=0 nrs=0 +MN0 Z net4 VSS VSS sg13_lv_nmos m=1 w=705.000n l=130.00n ng=1 nrd=0 ++ nrs=0 +MN1 net9 A VSS VSS sg13_lv_nmos m=1 w=320.00n l=200.0n ng=1 nrd=0 nrs=0 +MP2 net4 A net10 VDD sg13_lv_pmos m=1 w=1.2u l=200.0n ng=1 nrd=0 nrs=0 +MP1 net10 A VDD VDD sg13_lv_pmos m=1 w=1.2u l=200.0n ng=1 nrd=0 nrs=0 +MP0 Z net4 VDD VDD sg13_lv_pmos m=1 w=1.62u l=130.00n ng=1 nrd=0 nrs=0 +.ENDS +.SUBCKT RSC_IHPSG13_MX2X2 A0 A1 S Z VDD VSS +MP6 Z net010 VDD VDD sg13_lv_pmos m=1 w=1.62u l=130.00n ng=1 nrd=0 ++ nrs=0 +MP4 SN S VDD VDD sg13_lv_pmos m=1 w=645.000n l=130.00n ng=1 nrd=0 nrs=0 +MP3 net010 SN net12 VDD sg13_lv_pmos m=1 w=985.000n l=130.00n ng=1 nrd=0 ++ nrs=0 +MP2 net12 A1 VDD VDD sg13_lv_pmos m=1 w=985.000n l=130.00n ng=1 nrd=0 ++ nrs=0 +MP1 net010 S net17 VDD sg13_lv_pmos m=1 w=985.000n l=130.00n ng=1 nrd=0 ++ nrs=0 +MP0 net17 A0 VDD VDD sg13_lv_pmos m=1 w=985.000n l=130.00n ng=1 nrd=0 ++ nrs=0 +MN6 Z net010 VSS VSS sg13_lv_nmos m=1 w=705.000n l=130.00n ng=1 nrd=0 ++ nrs=0 +MN5 SN S VSS VSS sg13_lv_nmos m=1 w=560.00n l=130.00n ng=1 nrd=0 nrs=0 +MN3 net13 A1 VSS VSS sg13_lv_nmos m=1 w=560.00n l=130.00n ng=1 nrd=0 ++ nrs=0 +MN2 net010 S net13 VSS sg13_lv_nmos m=1 w=560.00n l=130.00n ng=1 nrd=0 ++ nrs=0 +MN1 net15 A0 VSS VSS sg13_lv_nmos m=1 w=560.00n l=130.00n ng=1 nrd=0 ++ nrs=0 +MN0 net010 SN net15 VSS sg13_lv_nmos m=1 w=560.00n l=130.00n ng=1 nrd=0 ++ nrs=0 +.ENDS +.SUBCKT RSC_IHPSG13_AND2X2 A B Z VDD VSS +MN3 Z net6 VSS VSS sg13_lv_nmos m=1 w=980.00n l=130.00n ng=1 nrd=0 ++ nrs=0 +MN4 net9 B VSS VSS sg13_lv_nmos m=1 w=500.0n l=130.00n ng=1 nrd=0 nrs=0 +MN6 net6 A net9 VSS sg13_lv_nmos m=1 w=500.0n l=130.00n ng=1 nrd=0 nrs=0 +MP2 Z net6 VDD VDD sg13_lv_pmos m=1 w=1.62u l=130.00n ng=1 nrd=0 nrs=0 +MP0 net6 B VDD VDD sg13_lv_pmos m=1 w=860.00n l=130.00n ng=1 nrd=0 ++ nrs=0 +MP1 net6 A VDD VDD sg13_lv_pmos m=1 w=860.00n l=130.00n ng=1 nrd=0 ++ nrs=0 +.ENDS +.SUBCKT RSC_IHPSG13_TIEL Z VDD VSS +MN0 Z net2 VSS VSS sg13_lv_nmos m=1 w=480.00n l=130.00n ng=1 nrd=0 ++ nrs=0 +MP0 net2 net2 VDD VDD sg13_lv_pmos m=1 w=480.00n l=130.00n ng=1 nrd=0 ++ nrs=0 +.ENDS +.SUBCKT RSC_IHPSG13_XOR2X2 A B Z VDD VSS +MP8 net012 B net7 VDD sg13_lv_pmos m=1 w=825.000n l=130.00n ng=1 nrd=0 ++ nrs=0 +MP7 net011 net3 net012 VDD sg13_lv_pmos m=1 w=825.000n l=130.00n ng=1 ++ nrd=0 nrs=0 +MP6 Z net012 VDD VDD sg13_lv_pmos m=1 w=1.535u l=130.00n ng=1 nrd=0 ++ nrs=0 +MP2 net7 A VDD VDD sg13_lv_pmos m=1 w=825.000n l=130.00n ng=1 nrd=0 ++ nrs=0 +MP4 net011 net7 VDD VDD sg13_lv_pmos m=1 w=825.000n l=130.00n ng=1 ++ nrd=0 nrs=0 +MP5 net3 B VDD VDD sg13_lv_pmos m=1 w=580.00n l=130.00n ng=1 nrd=0 ++ nrs=0 +MN7 net012 B net011 VSS sg13_lv_nmos m=1 w=555.000n l=130.00n ng=1 nrd=0 ++ nrs=0 +MN6 net7 net3 net012 VSS sg13_lv_nmos m=1 w=555.000n l=130.00n ng=1 nrd=0 ++ nrs=0 +MN5 Z net012 VSS VSS sg13_lv_nmos m=1 w=775.000n l=130.00n ng=1 nrd=0 ++ nrs=0 +MN2 net7 A VSS VSS sg13_lv_nmos m=1 w=555.000n l=130.00n ng=1 nrd=0 ++ nrs=0 +MN4 net3 B VSS VSS sg13_lv_nmos m=1 w=480.00n l=130.00n ng=1 nrd=0 ++ nrs=0 +MN3 net011 net7 VSS VSS sg13_lv_nmos m=1 w=555.000n l=130.00n ng=1 ++ nrd=0 nrs=0 +.ENDS +.SUBCKT RSC_IHPSG13_OA12X1 A B C Z VDD VSS +MN2 net7 C VSS VSS sg13_lv_nmos m=1 w=980.00n l=130.00n ng=1 nrd=0 ++ nrs=0 +MN3 Z net17 VSS VSS sg13_lv_nmos m=1 w=500.0n l=130.00n ng=1 nrd=0 ++ nrs=0 +MN1 net17 B net7 VSS sg13_lv_nmos m=1 w=980.00n l=130.00n ng=1 nrd=0 nrs=0 +MN0 net17 A net7 VSS sg13_lv_nmos m=1 w=980.00n l=130.00n ng=1 nrd=0 nrs=0 +MP0 net24 A VDD VDD sg13_lv_pmos m=1 w=1.62u l=130.00n ng=1 nrd=0 nrs=0 +MP3 Z net17 VDD VDD sg13_lv_pmos m=1 w=905.000n l=130.00n ng=1 nrd=0 ++ nrs=0 +MP1 net17 B net24 VDD sg13_lv_pmos m=1 w=1.62u l=130.00n ng=1 nrd=0 nrs=0 +MP2 net17 C VDD VDD sg13_lv_pmos m=1 w=905.000n l=130.00n ng=1 nrd=0 ++ nrs=0 +.ENDS +.SUBCKT RM_IHPSG13_1024x16_c2_1P_CTRL ACLK_N BIST_CK_I BIST_CS_I BIST_EN BIST_RE_I ++ BIST_WE_I B_TIEL_O CK_I CS_I DCLK ECLK PULSE_H PULSE_L PULSE_O RCLK RE_I ++ ROW_CS WCLK WE_I VDD VSS +XI17 ck_regs we col_we VDD VSS / RSC_IHPSG13_DFNQX2 +XI16 ck_regs re col_re VDD VSS / RSC_IHPSG13_DFNQX2 +XI18 ck_regs cs net7 VDD VSS / RSC_IHPSG13_DFNQX2 +XI71 ACLK_N net012 PULSE_O VDD VSS / RSC_IHPSG13_DFNQX2 +XI77 col_we net9 net016 VDD VSS / RSC_IHPSG13_CNAND2X2 +XI76 col_re net9 net018 VDD VSS / RSC_IHPSG13_CNAND2X2 +XI15 ck_dly WEorREandCS aclk VDD VSS / RSC_IHPSG13_CGATEPX4 +XI14 ck WEandCS DCLK VDD VSS / RSC_IHPSG13_CGATEPX4 +XI60 net7 ROW_CS VDD VSS / RSC_IHPSG13_CBUFX8 +XI73 PULSE_O net012 VDD VSS / RSC_IHPSG13_CINVX2 +XI8 net9 net8 VDD VSS / RSC_IHPSG13_CINVX2 +XI64 ck ck_dly VDD VSS / RSC_IHPSG13_CDLYX2 +XI86 CS_I BIST_CS_I BIST_EN cs VDD VSS / RSC_IHPSG13_MX2X2 +XI87 CK_I BIST_CK_I BIST_EN ck VDD VSS / RSC_IHPSG13_MX2X2 +XI85 WE_I BIST_WE_I BIST_EN we VDD VSS / RSC_IHPSG13_MX2X2 +XI84 RE_I BIST_RE_I BIST_EN re VDD VSS / RSC_IHPSG13_MX2X2 +XI22 we cs WEandCS VDD VSS / RSC_IHPSG13_AND2X2 +XBM_TIEL B_TIEL_O VDD VSS / RSC_IHPSG13_TIEL +XI48 ck_dly ck_regs VDD VSS / RSC_IHPSG13_CINVX4 +XI81 net016 WCLK VDD VSS / RSC_IHPSG13_CINVX4 +XI80 net018 RCLK VDD VSS / RSC_IHPSG13_CINVX4 +XI78 net8 net020 VDD VSS / RSC_IHPSG13_CINVX4 +XI6 PULSE_L PULSE_H net9 VDD VSS / RSC_IHPSG13_XOR2X2 +XI79 net020 ECLK VDD VSS / RSC_IHPSG13_CINVX8 +XI63 aclk ACLK_N VDD VSS / RSC_IHPSG13_CINVX8 +XI21 re we cs WEorREandCS VDD VSS / RSC_IHPSG13_OA12X1 +.ENDS +.SUBCKT RM_IHPSG13_1024x16_c2_1P_COLDEC2 ACLK_N ADDR<1> ADDR<0> ADDR_COL<1> ADDR_COL<0> ++ ADDR_DEC<7> ADDR_DEC<6> ADDR_DEC<5> ADDR_DEC<4> ADDR_DEC<3> ADDR_DEC<2> ++ ADDR_DEC<1> ADDR_DEC<0> BIST_ADDR<1> BIST_ADDR<0> BIST_EN_I VDD VSS +XI14<5> VDD VSS / RSC_IHPSG13_FILLCAP4 +XI14<4> VDD VSS / RSC_IHPSG13_FILLCAP4 +XI14<3> VDD VSS / RSC_IHPSG13_FILLCAP4 +XI14<2> VDD VSS / RSC_IHPSG13_FILLCAP4 +XI14<1> VDD VSS / RSC_IHPSG13_FILLCAP4 +XDFF<1> BIST_EN_I BIST_ADDR<1> ACLK_N ADDR<1> padr_int<1> net6<0> VDD ++ VSS / RSC_IHPSG13_DFNQMX2IX1 +XDFF<0> BIST_EN_I BIST_ADDR<0> ACLK_N ADDR<0> padr_int<0> net6<1> VDD ++ VSS / RSC_IHPSG13_DFNQMX2IX1 +XI1<3> PADR<1> PADR<0> addr_n<3> VDD VSS / RSC_IHPSG13_NAND2X2 +XI1<2> PADR<1> NADR<0> addr_n<2> VDD VSS / RSC_IHPSG13_NAND2X2 +XI1<1> NADR<1> PADR<0> addr_n<1> VDD VSS / RSC_IHPSG13_NAND2X2 +XI1<0> NADR<1> NADR<0> addr_n<0> VDD VSS / RSC_IHPSG13_NAND2X2 +XI16<37> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI16<36> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI16<35> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI16<34> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI16<33> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI16<32> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI16<31> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI16<30> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI16<29> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI16<28> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI16<27> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI16<26> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI16<25> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI16<24> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI16<23> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI16<22> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI16<21> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI16<20> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI16<19> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI16<18> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI16<17> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI16<16> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI16<15> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI16<14> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI16<13> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI16<12> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI16<11> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI16<10> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI16<9> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI16<8> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI16<7> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI16<6> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI16<5> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI16<4> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI16<3> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI16<2> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI16<1> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI3<1> padr_int<1> NADR<1> VDD VSS / RSC_IHPSG13_INVX2 +XI3<0> padr_int<0> NADR<0> VDD VSS / RSC_IHPSG13_INVX2 +XI13<1> NADR<1> PADR<1> VDD VSS / RSC_IHPSG13_INVX2 +XI13<0> NADR<0> PADR<0> VDD VSS / RSC_IHPSG13_INVX2 +XI2<3> addr_n<3> ADDR_DEC<3> VDD VSS / RSC_IHPSG13_INVX2 +XI2<2> addr_n<2> ADDR_DEC<2> VDD VSS / RSC_IHPSG13_INVX2 +XI2<1> addr_n<1> ADDR_DEC<1> VDD VSS / RSC_IHPSG13_INVX2 +XI2<0> addr_n<0> ADDR_DEC<0> VDD VSS / RSC_IHPSG13_INVX2 +XI15<1> ADDR_COL<1> VDD VSS / RSC_IHPSG13_TIEL +XI15<0> ADDR_COL<0> VDD VSS / RSC_IHPSG13_TIEL +XI17<3> ADDR_DEC<7> VDD VSS / RSC_IHPSG13_TIEL +XI17<2> ADDR_DEC<6> VDD VSS / RSC_IHPSG13_TIEL +XI17<1> ADDR_DEC<5> VDD VSS / RSC_IHPSG13_TIEL +XI17<0> ADDR_DEC<4> VDD VSS / RSC_IHPSG13_TIEL +.ENDS +.SUBCKT RSC_IHPSG13_NOR2X2 A B Z VDD VSS +MP1 Z B net9 VDD sg13_lv_pmos m=1 w=1.62u l=130.00n ng=1 nrd=0 nrs=0 +MP0 net9 A VDD VDD sg13_lv_pmos m=1 w=1.62u l=130.00n ng=1 nrd=0 nrs=0 +MN0 Z B VSS VSS sg13_lv_nmos m=1 w=980.00n l=130.00n ng=1 nrd=0 nrs=0 +MN1 Z A VSS VSS sg13_lv_nmos m=1 w=980.00n l=130.00n ng=1 nrd=0 nrs=0 +.ENDS +.SUBCKT RSC_IHPSG13_CINVX4_WN A Z VDD VSS +MN0 Z A VSS VSS sg13_lv_nmos m=1 w=705.000n l=130.00n ng=1 nrd=0 nrs=0 +MP0 Z A VDD VDD sg13_lv_pmos m=1 w=3.24u l=130.00n ng=2 nrd=0 nrs=0 +.ENDS +.SUBCKT RM_IHPSG13_1024x16_c2_1P_BLDRV BLC BLC_SEL BLT BLT_SEL PRE_N SEL_P WR_ONE WR_ZERO ++ VDD VSS +XCDEC SEL_P WR_ZERO BLC_PMOS_DRIVE VDD VSS / RSC_IHPSG13_NAND2X2 +XTDEC SEL_P WR_ONE BLT_PMOS_DRIVE VDD VSS / RSC_IHPSG13_NAND2X2 +MTWN BLT BLT_NMOS_DRIVE VSS VSS sg13_lv_nmos m=1 w=4.82u l=130.00n ++ ng=2 nrd=0 nrs=0 +MCWN BLC BLC_NMOS_DRIVE VSS VSS sg13_lv_nmos m=1 w=4.82u l=130.00n ++ ng=2 nrd=0 nrs=0 +MCWP BLC BLC_PMOS_DRIVE VDD VDD sg13_lv_pmos m=1 w=1.5u l=130.00n ng=1 ++ nrd=0 nrs=0 +MTWP BLT BLT_PMOS_DRIVE VDD VDD sg13_lv_pmos m=1 w=1.5u l=130.00n ng=1 ++ nrd=0 nrs=0 +MTSP BLT_SEL SEL_N BLT VDD sg13_lv_pmos m=1 w=1.5u l=130.00n ng=1 nrd=0 ++ nrs=0 +MTPR BLT PRE_N VDD VDD sg13_lv_pmos m=1 w=3.000u l=130.00n ng=2 nrd=0 ++ nrs=0 +MCSP BLC_SEL SEL_N BLC VDD sg13_lv_pmos m=1 w=1.5u l=130.00n ng=1 nrd=0 ++ nrs=0 +MCPR BLC PRE_N VDD VDD sg13_lv_pmos m=1 w=3.000u l=130.00n ng=2 nrd=0 ++ nrs=0 +XI86 SEL_P SEL_N VDD VSS / RSC_IHPSG13_INVX2 +XTINV BLC_PMOS_DRIVE BLT_NMOS_DRIVE VDD VSS / RSC_IHPSG13_INVX2 +XCINV BLT_PMOS_DRIVE BLC_NMOS_DRIVE VDD VSS / RSC_IHPSG13_INVX2 +.ENDS +.SUBCKT RSC_IHPSG13_TIEH Z VDD VSS +MN0 net2 net2 VSS VSS sg13_lv_nmos m=1 w=480.00n l=130.00n ng=1 nrd=0 ++ nrs=0 +MP0 Z net2 VDD VDD sg13_lv_pmos m=1 w=480.00n l=130.00n ng=1 nrd=0 ++ nrs=0 +.ENDS +.SUBCKT RSC_IHPSG13_MET3RES A B +R0 B A lvsres w=2.6e-07 l=6e-07 +.ENDS +.SUBCKT RSC_IHPSG13_DFPQD_MSAFFX2 CP DN DP QN QP VDD VSS +MN12 SN RN DIFFP VSS sg13_lv_nmos m=1 w=2.4u l=200.0n ng=2 nrd=0 nrs=0 +MN13 TAIL CP VSS VSS sg13_lv_nmos m=1 w=2.4u l=130.00n ng=2 nrd=0 nrs=0 +MN9 DIFFP DP TAIL VSS sg13_lv_nmos m=1 w=2.4u l=200.0n ng=2 nrd=0 nrs=0 +MN10 DIFFN DN TAIL VSS sg13_lv_nmos m=1 w=2.4u l=200.0n ng=2 nrd=0 nrs=0 +MN11 RN SN DIFFN VSS sg13_lv_nmos m=1 w=2.4u l=200.0n ng=2 nrd=0 nrs=0 +MN19 net33 SN VSS VSS sg13_lv_nmos m=1 w=980.00n l=130.00n ng=1 nrd=0 ++ nrs=0 +MN20 QN QP net37 VSS sg13_lv_nmos m=1 w=980.00n l=130.00n ng=1 nrd=0 nrs=0 +MN18 net37 RN VSS VSS sg13_lv_nmos m=1 w=980.00n l=130.00n ng=1 nrd=0 ++ nrs=0 +MN17 QP QN net33 VSS sg13_lv_nmos m=1 w=980.00n l=130.00n ng=1 nrd=0 nrs=0 +MP15 SN RN VDD VDD sg13_lv_pmos m=1 w=800.0n l=130.00n ng=1 nrd=0 nrs=0 +MP16 RN CP VDD VDD sg13_lv_pmos m=1 w=800.0n l=130.00n ng=1 nrd=0 nrs=0 +MP14 DIFFP CP VDD VDD sg13_lv_pmos m=1 w=800.0n l=130.00n ng=1 nrd=0 ++ nrs=0 +MP12 RN SN VDD VDD sg13_lv_pmos m=1 w=800.0n l=130.00n ng=1 nrd=0 nrs=0 +MP13 DIFFN CP VDD VDD sg13_lv_pmos m=1 w=800.0n l=130.00n ng=1 nrd=0 ++ nrs=0 +MP11 SN CP VDD VDD sg13_lv_pmos m=1 w=800.0n l=130.00n ng=1 nrd=0 nrs=0 +MP19 QN QP VDD VDD sg13_lv_pmos m=1 w=900.0n l=130.00n ng=1 nrd=0 nrs=0 +MP20 QP SN VDD VDD sg13_lv_pmos m=1 w=1.8u l=130.00n ng=2 nrd=0 nrs=0 +MP18 QN RN VDD VDD sg13_lv_pmos m=1 w=1.8u l=130.00n ng=2 nrd=0 nrs=0 +MP17 QP QN VDD VDD sg13_lv_pmos m=1 w=900.0n l=130.00n ng=1 nrd=0 nrs=0 +.ENDS +.SUBCKT RSC_IHPSG13_CBUFX2 A Z VDD VSS +MN1 Z net4 VSS VSS sg13_lv_nmos m=1 w=705.000n l=130.00n ng=1 nrd=0 ++ nrs=0 +MN0 net4 A VSS VSS sg13_lv_nmos m=1 w=540.00n l=130.00n ng=1 nrd=0 ++ nrs=0 +MP1 Z net4 VDD VDD sg13_lv_pmos m=1 w=1.62u l=130.00n ng=1 nrd=0 nrs=0 +MP0 net4 A VDD VDD sg13_lv_pmos m=1 w=1.1u l=130.00n ng=1 nrd=0 nrs=0 +.ENDS +.SUBCKT RSC_IHPSG13_INVX4 A Z VDD VSS +MN0 Z A VSS VSS sg13_lv_nmos m=1 w=1.96u l=130.00n ng=2 nrd=0 nrs=0 +MP0 Z A VDD VDD sg13_lv_pmos m=1 w=3.24u l=130.00n ng=2 nrd=0 nrs=0 +.ENDS +.SUBCKT RM_IHPSG13_1024x16_c2_1P_COLCTRL2 A_ADDR_DEC<3> A_ADDR_DEC<2> A_ADDR_DEC<1> ++ A_ADDR_DEC<0> A_BIST_BM_I A_BIST_DW_I A_BIST_EN_I A_BLC<3> A_BLC<2> A_BLC<1> ++ A_BLC<0> A_BLT<3> A_BLT<2> A_BLT<1> A_BLT<0> A_BM_I A_DCLK_B_L A_DCLK_B_R ++ A_DCLK_L A_DCLK_R A_DR_O A_DW_I A_RCLK_B_L A_RCLK_B_R A_RCLK_L A_RCLK_R ++ A_TIEH_O A_WCLK_B_L A_WCLK_B_R A_WCLK_L A_WCLK_R VDD VSS +XA_DREG A_BIST_EN_I A_BIST_DW_I A_DCLK_B_L A_DW_I A_DI_R net22 VDD VSS ++ / RSC_IHPSG13_DFNQMX2IX1 +XA_BREG A_BIST_EN_I A_BIST_BM_I A_DCLK_B_L A_BM_I A_BM_R net23 VDD VSS ++ / RSC_IHPSG13_DFNQMX2IX1 +XA_CAPS<5> VDD VSS / RSC_IHPSG13_FILLCAP4 +XA_CAPS<4> VDD VSS / RSC_IHPSG13_FILLCAP4 +XA_CAPS<3> VDD VSS / RSC_IHPSG13_FILLCAP4 +XA_CAPS<2> VDD VSS / RSC_IHPSG13_FILLCAP4 +XA_CAPS<1> VDD VSS / RSC_IHPSG13_FILLCAP4 +XA_I80 A_WCLK_B_R A_RCLK_B_R net21 VDD VSS / RSC_IHPSG13_AND2X2 +XA_I75 A_DI_R A_DO_WRITE_P A_WR_ONE VDD VSS / RSC_IHPSG13_AND2X2 +XA_I76 A_DI_N A_DO_WRITE_P A_WR_ZERO VDD VSS / RSC_IHPSG13_AND2X2 +XA_I44 A_WCLK_B_R A_BM_N A_DO_WRITE_P VDD VSS / RSC_IHPSG13_NOR2X2 +XA_I81 net21 A_PRE_N VDD VSS / RSC_IHPSG13_CINVX4_WN +XA_BLTMUX<3> A_BLC<3> A_BLC_SEL A_BLT<3> A_BLT_SEL A_PRE_N A_ADDR_DEC<3> ++ A_WR_ONE A_WR_ZERO VDD VSS / RM_IHPSG13_1024x16_c2_1P_BLDRV +XA_BLTMUX<2> A_BLC<2> A_BLC_SEL A_BLT<2> A_BLT_SEL A_PRE_N A_ADDR_DEC<2> ++ A_WR_ONE A_WR_ZERO VDD VSS / RM_IHPSG13_1024x16_c2_1P_BLDRV +XA_BLTMUX<1> A_BLC<1> A_BLC_SEL A_BLT<1> A_BLT_SEL A_PRE_N A_ADDR_DEC<1> ++ A_WR_ONE A_WR_ZERO VDD VSS / RM_IHPSG13_1024x16_c2_1P_BLDRV +XA_BLTMUX<0> A_BLC<0> A_BLC_SEL A_BLT<0> A_BLT_SEL A_PRE_N A_ADDR_DEC<0> ++ A_WR_ONE A_WR_ZERO VDD VSS / RM_IHPSG13_1024x16_c2_1P_BLDRV +XA_BM_TIEH A_TIEH_O VDD VSS / RSC_IHPSG13_TIEH +XA_I89 A_DCLK_B_L A_DCLK_B_R / RSC_IHPSG13_MET3RES +XA_I88 A_DCLK_L A_DCLK_R / RSC_IHPSG13_MET3RES +XA_I87 A_WCLK_L A_WCLK_R / RSC_IHPSG13_MET3RES +XA_I91 A_RCLK_B_R A_RCLK_B_L / RSC_IHPSG13_MET3RES +XA_R2 A_RCLK_R A_RCLK_L / RSC_IHPSG13_MET3RES +XA_I90 A_WCLK_B_R A_WCLK_B_L / RSC_IHPSG13_MET3RES +XA_ISENSE A_SAE A_BLC_SEL A_BLT_SEL net19 net20 VDD VSS / ++ RSC_IHPSG13_DFPQD_MSAFFX2 +XA_I78 A_RCLK_B_R A_SAE VDD VSS / RSC_IHPSG13_CBUFX2 +XA_I83 A_BM_R A_BM_N VDD VSS / RSC_IHPSG13_INVX2 +XA_I49 A_DI_R A_DI_N VDD VSS / RSC_IHPSG13_INVX2 +XA_I51 net19 A_DR_O VDD VSS / RSC_IHPSG13_INVX4 +XA_I69 A_DCLK_L A_DCLK_B_L VDD VSS / RSC_IHPSG13_CINVX2 +XA_I50 A_WCLK_L A_WCLK_B_R VDD VSS / RSC_IHPSG13_CINVX2 +XA_EBUF A_RCLK_R A_RCLK_B_R VDD VSS / RSC_IHPSG13_CINVX2 +.ENDS +.SUBCKT RM_IHPSG13_1024x16_c2_1P_COLDRV13_FILL4 VDD VSS +XI0<9> VDD VSS / RSC_IHPSG13_FILLCAP4 +XI0<8> VDD VSS / RSC_IHPSG13_FILLCAP4 +XI0<7> VDD VSS / RSC_IHPSG13_FILLCAP4 +XI0<6> VDD VSS / RSC_IHPSG13_FILLCAP4 +XI0<5> VDD VSS / RSC_IHPSG13_FILLCAP4 +XI0<4> VDD VSS / RSC_IHPSG13_FILLCAP4 +XI0<3> VDD VSS / RSC_IHPSG13_FILLCAP4 +XI0<2> VDD VSS / RSC_IHPSG13_FILLCAP4 +XI0<1> VDD VSS / RSC_IHPSG13_FILLCAP4 +.ENDS +.SUBCKT RM_IHPSG13_1024x16_c2_1P_COLDRV13_FILL4C2 VDD VSS +XI0<2> VDD VSS / RSC_IHPSG13_FILLCAP4 +XI0<1> VDD VSS / RSC_IHPSG13_FILLCAP4 +.ENDS + + +.SUBCKT RM_IHPSG13_1024x16_c2_1P_COLDEC4 ACLK_N ADDR<3> ADDR<2> ADDR<1> ADDR<0> ++ ADDR_COL<1> ADDR_COL<0> ADDR_DEC<7> ADDR_DEC<6> ADDR_DEC<5> ADDR_DEC<4> ++ ADDR_DEC<3> ADDR_DEC<2> ADDR_DEC<1> ADDR_DEC<0> BIST_ADDR<3> BIST_ADDR<2> ++ BIST_ADDR<1> BIST_ADDR<0> BIST_EN_I VDD VSS +XI15 ADDR_COL<1> VDD VSS / RSC_IHPSG13_TIEL +XI14 addr_int ADDR_COL<0> VDD VSS / RSC_IHPSG13_CBUFX2 +XDFF<3> BIST_EN_I BIST_ADDR<3> ACLK_N ADDR<3> addr_int net7<0> VDD VSS ++ / RSC_IHPSG13_DFNQMX2IX1 +XDFF<2> BIST_EN_I BIST_ADDR<2> ACLK_N ADDR<2> padr_int<2> net7<1> VDD ++ VSS / RSC_IHPSG13_DFNQMX2IX1 +XDFF<1> BIST_EN_I BIST_ADDR<1> ACLK_N ADDR<1> padr_int<1> net7<2> VDD ++ VSS / RSC_IHPSG13_DFNQMX2IX1 +XDFF<0> BIST_EN_I BIST_ADDR<0> ACLK_N ADDR<0> padr_int<0> net7<3> VDD ++ VSS / RSC_IHPSG13_DFNQMX2IX1 +XI1<7> PADR<0> PADR<1> PADR<2> addr_n<7> VDD VSS / RSC_IHPSG13_NAND3X2 +XI1<6> NADR<0> PADR<1> PADR<2> addr_n<6> VDD VSS / RSC_IHPSG13_NAND3X2 +XI1<5> PADR<0> NADR<1> PADR<2> addr_n<5> VDD VSS / RSC_IHPSG13_NAND3X2 +XI1<4> NADR<0> NADR<1> PADR<2> addr_n<4> VDD VSS / RSC_IHPSG13_NAND3X2 +XI1<3> PADR<0> PADR<1> NADR<2> addr_n<3> VDD VSS / RSC_IHPSG13_NAND3X2 +XI1<2> NADR<0> PADR<1> NADR<2> addr_n<2> VDD VSS / RSC_IHPSG13_NAND3X2 +XI1<1> PADR<0> NADR<1> NADR<2> addr_n<1> VDD VSS / RSC_IHPSG13_NAND3X2 +XI1<0> NADR<0> NADR<1> NADR<2> addr_n<0> VDD VSS / RSC_IHPSG13_NAND3X2 +XI13<2> NADR<2> PADR<2> VDD VSS / RSC_IHPSG13_INVX2 +XI13<1> NADR<1> PADR<1> VDD VSS / RSC_IHPSG13_INVX2 +XI13<0> NADR<0> PADR<0> VDD VSS / RSC_IHPSG13_INVX2 +XI3<2> padr_int<2> NADR<2> VDD VSS / RSC_IHPSG13_INVX2 +XI3<1> padr_int<1> NADR<1> VDD VSS / RSC_IHPSG13_INVX2 +XI3<0> padr_int<0> NADR<0> VDD VSS / RSC_IHPSG13_INVX2 +XI2<7> addr_n<7> ADDR_DEC<7> VDD VSS / RSC_IHPSG13_INVX2 +XI2<6> addr_n<6> ADDR_DEC<6> VDD VSS / RSC_IHPSG13_INVX2 +XI2<5> addr_n<5> ADDR_DEC<5> VDD VSS / RSC_IHPSG13_INVX2 +XI2<4> addr_n<4> ADDR_DEC<4> VDD VSS / RSC_IHPSG13_INVX2 +XI2<3> addr_n<3> ADDR_DEC<3> VDD VSS / RSC_IHPSG13_INVX2 +XI2<2> addr_n<2> ADDR_DEC<2> VDD VSS / RSC_IHPSG13_INVX2 +XI2<1> addr_n<1> ADDR_DEC<1> VDD VSS / RSC_IHPSG13_INVX2 +XI2<0> addr_n<0> ADDR_DEC<0> VDD VSS / RSC_IHPSG13_INVX2 +XI16<3> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI16<2> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI16<1> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI17<2> VDD VSS / RSC_IHPSG13_FILLCAP4 +XI17<1> VDD VSS / RSC_IHPSG13_FILLCAP4 +.ENDS +.SUBCKT RSC_IHPSG13_AND2X4 A B Z VDD VSS +MN3 Z net6 VSS VSS sg13_lv_nmos m=1 w=1.96u l=130.00n ng=2 nrd=0 nrs=0 +MN4 net9 B VSS VSS sg13_lv_nmos m=1 w=500.0n l=130.00n ng=1 nrd=0 nrs=0 +MN6 net6 A net9 VSS sg13_lv_nmos m=1 w=500.0n l=130.00n ng=1 nrd=0 nrs=0 +MP2 Z net6 VDD VDD sg13_lv_pmos m=1 w=3.24u l=130.00n ng=2 nrd=0 nrs=0 +MP0 net6 B VDD VDD sg13_lv_pmos m=1 w=860.00n l=130.00n ng=1 nrd=0 ++ nrs=0 +MP1 net6 A VDD VDD sg13_lv_pmos m=1 w=860.00n l=130.00n ng=1 nrd=0 ++ nrs=0 +.ENDS +.SUBCKT RM_IHPSG13_1024x16_c2_1P_COLCTRL4 A_ADDR_COL A_ADDR_DEC<7> A_ADDR_DEC<6> ++ A_ADDR_DEC<5> A_ADDR_DEC<4> A_ADDR_DEC<3> A_ADDR_DEC<2> A_ADDR_DEC<1> ++ A_ADDR_DEC<0> A_BIST_BM_I A_BIST_DW_I A_BIST_EN_I A_BLC<15> A_BLC<14> ++ A_BLC<13> A_BLC<12> A_BLC<11> A_BLC<10> A_BLC<9> A_BLC<8> A_BLC<7> A_BLC<6> ++ A_BLC<5> A_BLC<4> A_BLC<3> A_BLC<2> A_BLC<1> A_BLC<0> A_BLT<15> A_BLT<14> ++ A_BLT<13> A_BLT<12> A_BLT<11> A_BLT<10> A_BLT<9> A_BLT<8> A_BLT<7> A_BLT<6> ++ A_BLT<5> A_BLT<4> A_BLT<3> A_BLT<2> A_BLT<1> A_BLT<0> A_BM_I A_DCLK_B_L ++ A_DCLK_B_R A_DCLK_L A_DCLK_R A_DR_O A_DW_I A_RCLK_B_L A_RCLK_B_R A_RCLK_L ++ A_RCLK_R A_TIEH_O A_WCLK_B_L A_WCLK_B_R A_WCLK_L A_WCLK_R VDD VSS +XA_I80 A_WCLK_B_L A_RCLK_B_L net21 VDD VSS / RSC_IHPSG13_AND2X2 +XA_I76 A_DO_WRITE_P A_DI_N A_WR_ZERO VDD VSS / RSC_IHPSG13_AND2X4 +XA_I75 A_DI_R A_DO_WRITE_P A_WR_ONE VDD VSS / RSC_IHPSG13_AND2X4 +XA_CAPS<8> VDD VSS / RSC_IHPSG13_FILLCAP4 +XA_CAPS<7> VDD VSS / RSC_IHPSG13_FILLCAP4 +XA_CAPS<6> VDD VSS / RSC_IHPSG13_FILLCAP4 +XA_CAPS<5> VDD VSS / RSC_IHPSG13_FILLCAP4 +XA_CAPS<4> VDD VSS / RSC_IHPSG13_FILLCAP4 +XA_CAPS<3> VDD VSS / RSC_IHPSG13_FILLCAP4 +XA_CAPS<2> VDD VSS / RSC_IHPSG13_FILLCAP4 +XA_CAPS<1> VDD VSS / RSC_IHPSG13_FILLCAP4 +XA_I69 A_DCLK_L A_DCLK_B_L VDD VSS / RSC_IHPSG13_CINVX4 +XA_I50 A_WCLK_L A_WCLK_B_L VDD VSS / RSC_IHPSG13_CINVX4 +XA_EBUF A_RCLK_L A_RCLK_B_L VDD VSS / RSC_IHPSG13_CINVX4 +XA_INV<1> A_N0 A_P0 VDD VSS / RSC_IHPSG13_CINVX4 +XA_INV<0> A_ADDR_COL A_N0 VDD VSS / RSC_IHPSG13_CINVX4 +XA_I81<1> net21 A_PRE_N VDD VSS / RSC_IHPSG13_CINVX4_WN +XA_I81<0> net21 A_PRE_N VDD VSS / RSC_IHPSG13_CINVX4_WN +XA_BLTMUX<15> A_BLC<15> A_BLC_SEL A_BLT<15> A_BLT_SEL A_PRE_N A_SEL_P<15> ++ A_WR_ONE A_WR_ZERO VDD VSS / RM_IHPSG13_1024x16_c2_1P_BLDRV +XA_BLTMUX<14> A_BLC<14> A_BLC_SEL A_BLT<14> A_BLT_SEL A_PRE_N A_SEL_P<14> ++ A_WR_ONE A_WR_ZERO VDD VSS / RM_IHPSG13_1024x16_c2_1P_BLDRV +XA_BLTMUX<13> A_BLC<13> A_BLC_SEL A_BLT<13> A_BLT_SEL A_PRE_N A_SEL_P<13> ++ A_WR_ONE A_WR_ZERO VDD VSS / RM_IHPSG13_1024x16_c2_1P_BLDRV +XA_BLTMUX<12> A_BLC<12> A_BLC_SEL A_BLT<12> A_BLT_SEL A_PRE_N A_SEL_P<12> ++ A_WR_ONE A_WR_ZERO VDD VSS / RM_IHPSG13_1024x16_c2_1P_BLDRV +XA_BLTMUX<11> A_BLC<11> A_BLC_SEL A_BLT<11> A_BLT_SEL A_PRE_N A_SEL_P<11> ++ A_WR_ONE A_WR_ZERO VDD VSS / RM_IHPSG13_1024x16_c2_1P_BLDRV +XA_BLTMUX<10> A_BLC<10> A_BLC_SEL A_BLT<10> A_BLT_SEL A_PRE_N A_SEL_P<10> ++ A_WR_ONE A_WR_ZERO VDD VSS / RM_IHPSG13_1024x16_c2_1P_BLDRV +XA_BLTMUX<9> A_BLC<9> A_BLC_SEL A_BLT<9> A_BLT_SEL A_PRE_N A_SEL_P<9> A_WR_ONE ++ A_WR_ZERO VDD VSS / RM_IHPSG13_1024x16_c2_1P_BLDRV +XA_BLTMUX<8> A_BLC<8> A_BLC_SEL A_BLT<8> A_BLT_SEL A_PRE_N A_SEL_P<8> A_WR_ONE ++ A_WR_ZERO VDD VSS / RM_IHPSG13_1024x16_c2_1P_BLDRV +XA_BLTMUX<7> A_BLC<7> A_BLC_SEL A_BLT<7> A_BLT_SEL A_PRE_N A_SEL_P<7> A_WR_ONE ++ A_WR_ZERO VDD VSS / RM_IHPSG13_1024x16_c2_1P_BLDRV +XA_BLTMUX<6> A_BLC<6> A_BLC_SEL A_BLT<6> A_BLT_SEL A_PRE_N A_SEL_P<6> A_WR_ONE ++ A_WR_ZERO VDD VSS / RM_IHPSG13_1024x16_c2_1P_BLDRV +XA_BLTMUX<5> A_BLC<5> A_BLC_SEL A_BLT<5> A_BLT_SEL A_PRE_N A_SEL_P<5> A_WR_ONE ++ A_WR_ZERO VDD VSS / RM_IHPSG13_1024x16_c2_1P_BLDRV +XA_BLTMUX<4> A_BLC<4> A_BLC_SEL A_BLT<4> A_BLT_SEL A_PRE_N A_SEL_P<4> A_WR_ONE ++ A_WR_ZERO VDD VSS / RM_IHPSG13_1024x16_c2_1P_BLDRV +XA_BLTMUX<3> A_BLC<3> A_BLC_SEL A_BLT<3> A_BLT_SEL A_PRE_N A_SEL_P<3> A_WR_ONE ++ A_WR_ZERO VDD VSS / RM_IHPSG13_1024x16_c2_1P_BLDRV +XA_BLTMUX<2> A_BLC<2> A_BLC_SEL A_BLT<2> A_BLT_SEL A_PRE_N A_SEL_P<2> A_WR_ONE ++ A_WR_ZERO VDD VSS / RM_IHPSG13_1024x16_c2_1P_BLDRV +XA_BLTMUX<1> A_BLC<1> A_BLC_SEL A_BLT<1> A_BLT_SEL A_PRE_N A_SEL_P<1> A_WR_ONE ++ A_WR_ZERO VDD VSS / RM_IHPSG13_1024x16_c2_1P_BLDRV +XA_BLTMUX<0> A_BLC<0> A_BLC_SEL A_BLT<0> A_BLT_SEL A_PRE_N A_SEL_P<0> A_WR_ONE ++ A_WR_ZERO VDD VSS / RM_IHPSG13_1024x16_c2_1P_BLDRV +XA_R2 A_RCLK_L A_RCLK_R / RSC_IHPSG13_MET3RES +XA_I87 A_WCLK_L A_WCLK_R / RSC_IHPSG13_MET3RES +XA_I88 A_DCLK_L A_DCLK_R / RSC_IHPSG13_MET3RES +XA_I89 A_DCLK_B_L A_DCLK_B_R / RSC_IHPSG13_MET3RES +XA_I90 A_WCLK_B_L A_WCLK_B_R / RSC_IHPSG13_MET3RES +XA_I91 A_RCLK_B_L A_RCLK_B_R / RSC_IHPSG13_MET3RES +XA_ISENSE A_SAE A_BLC_SEL A_BLT_SEL net19 net20 VDD VSS / ++ RSC_IHPSG13_DFPQD_MSAFFX2 +XA_I51 net19 A_DR_O VDD VSS / RSC_IHPSG13_INVX4 +XA_I78 A_RCLK_B_L A_SAE VDD VSS / RSC_IHPSG13_CBUFX2 +XA_DREG A_BIST_EN_I A_BIST_DW_I A_DCLK_B_L A_DW_I A_DI_R net22 VDD VSS ++ / RSC_IHPSG13_DFNQMX2IX1 +XA_BREG A_BIST_EN_I A_BIST_BM_I A_DCLK_B_L A_BM_I A_BM_R net24 VDD VSS ++ / RSC_IHPSG13_DFNQMX2IX1 +XA_DEC3INV<15> net23<0> A_SEL_P<15> VDD VSS / RSC_IHPSG13_INVX2 +XA_DEC3INV<14> net23<1> A_SEL_P<14> VDD VSS / RSC_IHPSG13_INVX2 +XA_DEC3INV<13> net23<2> A_SEL_P<13> VDD VSS / RSC_IHPSG13_INVX2 +XA_DEC3INV<12> net23<3> A_SEL_P<12> VDD VSS / RSC_IHPSG13_INVX2 +XA_DEC3INV<11> net23<4> A_SEL_P<11> VDD VSS / RSC_IHPSG13_INVX2 +XA_DEC3INV<10> net23<5> A_SEL_P<10> VDD VSS / RSC_IHPSG13_INVX2 +XA_DEC3INV<9> net23<6> A_SEL_P<9> VDD VSS / RSC_IHPSG13_INVX2 +XA_DEC3INV<8> net23<7> A_SEL_P<8> VDD VSS / RSC_IHPSG13_INVX2 +XA_DEC3INV<7> net23<8> A_SEL_P<7> VDD VSS / RSC_IHPSG13_INVX2 +XA_DEC3INV<6> net23<9> A_SEL_P<6> VDD VSS / RSC_IHPSG13_INVX2 +XA_DEC3INV<5> net23<10> A_SEL_P<5> VDD VSS / RSC_IHPSG13_INVX2 +XA_DEC3INV<4> net23<11> A_SEL_P<4> VDD VSS / RSC_IHPSG13_INVX2 +XA_DEC3INV<3> net23<12> A_SEL_P<3> VDD VSS / RSC_IHPSG13_INVX2 +XA_DEC3INV<2> net23<13> A_SEL_P<2> VDD VSS / RSC_IHPSG13_INVX2 +XA_DEC3INV<1> net23<14> A_SEL_P<1> VDD VSS / RSC_IHPSG13_INVX2 +XA_DEC3INV<0> net23<15> A_SEL_P<0> VDD VSS / RSC_IHPSG13_INVX2 +XA_I83 A_BM_R A_BM_N VDD VSS / RSC_IHPSG13_INVX2 +XA_I49 A_DI_R A_DI_N VDD VSS / RSC_IHPSG13_INVX2 +XA_I70<4> VDD VSS / RSC_IHPSG13_FILLCAP8 +XA_I70<3> VDD VSS / RSC_IHPSG13_FILLCAP8 +XA_I70<2> VDD VSS / RSC_IHPSG13_FILLCAP8 +XA_I70<1> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI73<14> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI73<13> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI73<12> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI73<11> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI73<10> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI73<9> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI73<8> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI73<7> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI73<6> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI73<5> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI73<4> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI73<3> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI73<2> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI73<1> VDD VSS / RSC_IHPSG13_FILLCAP8 +XA_I44 A_BM_N A_WCLK_B_L A_DO_WRITE_P VDD VSS / RSC_IHPSG13_NOR2X2 +XA_DEC3<15> A_P0 A_ADDR_DEC<7> net23<0> VDD VSS / RSC_IHPSG13_NAND2X2 +XA_DEC3<14> A_P0 A_ADDR_DEC<6> net23<1> VDD VSS / RSC_IHPSG13_NAND2X2 +XA_DEC3<13> A_P0 A_ADDR_DEC<5> net23<2> VDD VSS / RSC_IHPSG13_NAND2X2 +XA_DEC3<12> A_P0 A_ADDR_DEC<4> net23<3> VDD VSS / RSC_IHPSG13_NAND2X2 +XA_DEC3<11> A_P0 A_ADDR_DEC<3> net23<4> VDD VSS / RSC_IHPSG13_NAND2X2 +XA_DEC3<10> A_P0 A_ADDR_DEC<2> net23<5> VDD VSS / RSC_IHPSG13_NAND2X2 +XA_DEC3<9> A_P0 A_ADDR_DEC<1> net23<6> VDD VSS / RSC_IHPSG13_NAND2X2 +XA_DEC3<8> A_P0 A_ADDR_DEC<0> net23<7> VDD VSS / RSC_IHPSG13_NAND2X2 +XA_DEC3<7> A_N0 A_ADDR_DEC<7> net23<8> VDD VSS / RSC_IHPSG13_NAND2X2 +XA_DEC3<6> A_N0 A_ADDR_DEC<6> net23<9> VDD VSS / RSC_IHPSG13_NAND2X2 +XA_DEC3<5> A_N0 A_ADDR_DEC<5> net23<10> VDD VSS / RSC_IHPSG13_NAND2X2 +XA_DEC3<4> A_N0 A_ADDR_DEC<4> net23<11> VDD VSS / RSC_IHPSG13_NAND2X2 +XA_DEC3<3> A_N0 A_ADDR_DEC<3> net23<12> VDD VSS / RSC_IHPSG13_NAND2X2 +XA_DEC3<2> A_N0 A_ADDR_DEC<2> net23<13> VDD VSS / RSC_IHPSG13_NAND2X2 +XA_DEC3<1> A_N0 A_ADDR_DEC<1> net23<14> VDD VSS / RSC_IHPSG13_NAND2X2 +XA_DEC3<0> A_N0 A_ADDR_DEC<0> net23<15> VDD VSS / RSC_IHPSG13_NAND2X2 +XA_BM_TIEH A_TIEH_O VDD VSS / RSC_IHPSG13_TIEH +.ENDS + + +.SUBCKT RM_IHPSG13_1024x16_c2_1P_COLDEC3 ACLK_N ADDR<2> ADDR<1> ADDR<0> ADDR_COL<1> ++ ADDR_COL<0> ADDR_DEC<7> ADDR_DEC<6> ADDR_DEC<5> ADDR_DEC<4> ADDR_DEC<3> ++ ADDR_DEC<2> ADDR_DEC<1> ADDR_DEC<0> BIST_ADDR<2> BIST_ADDR<1> BIST_ADDR<0> ++ BIST_EN_I VDD VSS +XI15<1> ADDR_COL<1> VDD VSS / RSC_IHPSG13_TIEL +XI15<0> ADDR_COL<0> VDD VSS / RSC_IHPSG13_TIEL +XI1<7> PADR<0> PADR<1> PADR<2> addr_n<7> VDD VSS / RSC_IHPSG13_NAND3X2 +XI1<6> NADR<0> PADR<1> PADR<2> addr_n<6> VDD VSS / RSC_IHPSG13_NAND3X2 +XI1<5> PADR<0> NADR<1> PADR<2> addr_n<5> VDD VSS / RSC_IHPSG13_NAND3X2 +XI1<4> NADR<0> NADR<1> PADR<2> addr_n<4> VDD VSS / RSC_IHPSG13_NAND3X2 +XI1<3> PADR<0> PADR<1> NADR<2> addr_n<3> VDD VSS / RSC_IHPSG13_NAND3X2 +XI1<2> NADR<0> PADR<1> NADR<2> addr_n<2> VDD VSS / RSC_IHPSG13_NAND3X2 +XI1<1> PADR<0> NADR<1> NADR<2> addr_n<1> VDD VSS / RSC_IHPSG13_NAND3X2 +XI1<0> NADR<0> NADR<1> NADR<2> addr_n<0> VDD VSS / RSC_IHPSG13_NAND3X2 +XDFF<2> BIST_EN_I BIST_ADDR<2> ACLK_N ADDR<2> padr_int<2> net6<0> VDD ++ VSS / RSC_IHPSG13_DFNQMX2IX1 +XDFF<1> BIST_EN_I BIST_ADDR<1> ACLK_N ADDR<1> padr_int<1> net6<1> VDD ++ VSS / RSC_IHPSG13_DFNQMX2IX1 +XDFF<0> BIST_EN_I BIST_ADDR<0> ACLK_N ADDR<0> padr_int<0> net6<2> VDD ++ VSS / RSC_IHPSG13_DFNQMX2IX1 +XI17<2> VDD VSS / RSC_IHPSG13_FILLCAP4 +XI17<1> VDD VSS / RSC_IHPSG13_FILLCAP4 +XI13<2> NADR<2> PADR<2> VDD VSS / RSC_IHPSG13_INVX2 +XI13<1> NADR<1> PADR<1> VDD VSS / RSC_IHPSG13_INVX2 +XI13<0> NADR<0> PADR<0> VDD VSS / RSC_IHPSG13_INVX2 +XI3<2> padr_int<2> NADR<2> VDD VSS / RSC_IHPSG13_INVX2 +XI3<1> padr_int<1> NADR<1> VDD VSS / RSC_IHPSG13_INVX2 +XI3<0> padr_int<0> NADR<0> VDD VSS / RSC_IHPSG13_INVX2 +XI2<7> addr_n<7> ADDR_DEC<7> VDD VSS / RSC_IHPSG13_INVX2 +XI2<6> addr_n<6> ADDR_DEC<6> VDD VSS / RSC_IHPSG13_INVX2 +XI2<5> addr_n<5> ADDR_DEC<5> VDD VSS / RSC_IHPSG13_INVX2 +XI2<4> addr_n<4> ADDR_DEC<4> VDD VSS / RSC_IHPSG13_INVX2 +XI2<3> addr_n<3> ADDR_DEC<3> VDD VSS / RSC_IHPSG13_INVX2 +XI2<2> addr_n<2> ADDR_DEC<2> VDD VSS / RSC_IHPSG13_INVX2 +XI2<1> addr_n<1> ADDR_DEC<1> VDD VSS / RSC_IHPSG13_INVX2 +XI2<0> addr_n<0> ADDR_DEC<0> VDD VSS / RSC_IHPSG13_INVX2 +XI16<6> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI16<5> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI16<4> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI16<3> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI16<2> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI16<1> VDD VSS / RSC_IHPSG13_FILLCAP8 +.ENDS +.SUBCKT RM_IHPSG13_1024x16_c2_1P_COLCTRL3 A_ADDR_DEC<7> A_ADDR_DEC<6> A_ADDR_DEC<5> ++ A_ADDR_DEC<4> A_ADDR_DEC<3> A_ADDR_DEC<2> A_ADDR_DEC<1> A_ADDR_DEC<0> ++ A_BIST_BM_I A_BIST_DW_I A_BIST_EN_I A_BLC<7> A_BLC<6> A_BLC<5> A_BLC<4> ++ A_BLC<3> A_BLC<2> A_BLC<1> A_BLC<0> A_BLT<7> A_BLT<6> A_BLT<5> A_BLT<4> ++ A_BLT<3> A_BLT<2> A_BLT<1> A_BLT<0> A_BM_I A_DCLK_B_L A_DCLK_B_R A_DCLK_L ++ A_DCLK_R A_DR_O A_DW_I A_RCLK_B_L A_RCLK_B_R A_RCLK_L A_RCLK_R A_TIEH_O ++ A_WCLK_B_L A_WCLK_B_R A_WCLK_L A_WCLK_R VDD VSS +XA_DREG A_BIST_EN_I A_BIST_DW_I A_DCLK_B_L A_DW_I A_DI_R net22 VDD VSS ++ / RSC_IHPSG13_DFNQMX2IX1 +XA_BREG A_BIST_EN_I A_BIST_BM_I A_DCLK_B_R A_BM_I A_BM_R net23 VDD VSS ++ / RSC_IHPSG13_DFNQMX2IX1 +XA_I70<8> VDD VSS / RSC_IHPSG13_FILLCAP8 +XA_I70<7> VDD VSS / RSC_IHPSG13_FILLCAP8 +XA_I70<6> VDD VSS / RSC_IHPSG13_FILLCAP8 +XA_I70<5> VDD VSS / RSC_IHPSG13_FILLCAP8 +XA_I70<4> VDD VSS / RSC_IHPSG13_FILLCAP8 +XA_I70<3> VDD VSS / RSC_IHPSG13_FILLCAP8 +XA_I70<2> VDD VSS / RSC_IHPSG13_FILLCAP8 +XA_I70<1> VDD VSS / RSC_IHPSG13_FILLCAP8 +XA_I51 net19 A_DR_O VDD VSS / RSC_IHPSG13_INVX4 +XA_I44 A_BM_N A_WCLK_B_R A_DO_WRITE_P VDD VSS / RSC_IHPSG13_NOR2X2 +XA_BM_TIEH A_TIEH_O VDD VSS / RSC_IHPSG13_TIEH +XA_BLTMUX<7> A_BLC<7> A_BLC_SEL A_BLT<7> A_BLT_SEL A_PRE_N A_ADDR_DEC<7> ++ A_WR_ONE A_WR_ZERO VDD VSS / RM_IHPSG13_1024x16_c2_1P_BLDRV +XA_BLTMUX<6> A_BLC<6> A_BLC_SEL A_BLT<6> A_BLT_SEL A_PRE_N A_ADDR_DEC<6> ++ A_WR_ONE A_WR_ZERO VDD VSS / RM_IHPSG13_1024x16_c2_1P_BLDRV +XA_BLTMUX<5> A_BLC<5> A_BLC_SEL A_BLT<5> A_BLT_SEL A_PRE_N A_ADDR_DEC<5> ++ A_WR_ONE A_WR_ZERO VDD VSS / RM_IHPSG13_1024x16_c2_1P_BLDRV +XA_BLTMUX<4> A_BLC<4> A_BLC_SEL A_BLT<4> A_BLT_SEL A_PRE_N A_ADDR_DEC<4> ++ A_WR_ONE A_WR_ZERO VDD VSS / RM_IHPSG13_1024x16_c2_1P_BLDRV +XA_BLTMUX<3> A_BLC<3> A_BLC_SEL A_BLT<3> A_BLT_SEL A_PRE_N A_ADDR_DEC<3> ++ A_WR_ONE A_WR_ZERO VDD VSS / RM_IHPSG13_1024x16_c2_1P_BLDRV +XA_BLTMUX<2> A_BLC<2> A_BLC_SEL A_BLT<2> A_BLT_SEL A_PRE_N A_ADDR_DEC<2> ++ A_WR_ONE A_WR_ZERO VDD VSS / RM_IHPSG13_1024x16_c2_1P_BLDRV +XA_BLTMUX<1> A_BLC<1> A_BLC_SEL A_BLT<1> A_BLT_SEL A_PRE_N A_ADDR_DEC<1> ++ A_WR_ONE A_WR_ZERO VDD VSS / RM_IHPSG13_1024x16_c2_1P_BLDRV +XA_BLTMUX<0> A_BLC<0> A_BLC_SEL A_BLT<0> A_BLT_SEL A_PRE_N A_ADDR_DEC<0> ++ A_WR_ONE A_WR_ZERO VDD VSS / RM_IHPSG13_1024x16_c2_1P_BLDRV +XA_I49 A_DI_R A_DI_N VDD VSS / RSC_IHPSG13_INVX2 +XA_I83 A_BM_R A_BM_N VDD VSS / RSC_IHPSG13_INVX2 +XA_I69 A_DCLK_L A_DCLK_B_L VDD VSS / RSC_IHPSG13_CINVX2 +XA_I50 A_WCLK_L A_WCLK_B_L VDD VSS / RSC_IHPSG13_CINVX2 +XA_EBUF A_RCLK_L A_RCLK_B_L VDD VSS / RSC_IHPSG13_CINVX2 +XA_I78 A_RCLK_B_L A_SAE VDD VSS / RSC_IHPSG13_CBUFX2 +XA_I88 A_DCLK_L A_DCLK_R / RSC_IHPSG13_MET3RES +XA_I87 A_WCLK_L A_WCLK_R / RSC_IHPSG13_MET3RES +XA_R2 A_RCLK_L A_RCLK_R / RSC_IHPSG13_MET3RES +XA_I91 A_RCLK_B_L A_RCLK_B_R / RSC_IHPSG13_MET3RES +XA_I90 A_WCLK_B_L A_WCLK_B_R / RSC_IHPSG13_MET3RES +XA_I89 A_DCLK_B_L A_DCLK_B_R / RSC_IHPSG13_MET3RES +XA_I80 A_WCLK_B_R A_RCLK_B_R net21 VDD VSS / RSC_IHPSG13_AND2X2 +XA_I76 A_DI_N A_DO_WRITE_P A_WR_ZERO VDD VSS / RSC_IHPSG13_AND2X2 +XA_I75 A_DI_R A_DO_WRITE_P A_WR_ONE VDD VSS / RSC_IHPSG13_AND2X2 +XA_ISENSE A_SAE A_BLC_SEL A_BLT_SEL net19 net20 VDD VSS / ++ RSC_IHPSG13_DFPQD_MSAFFX2 +XA_I81 net21 A_PRE_N VDD VSS / RSC_IHPSG13_CINVX4_WN +XA_CAPS<5> VDD VSS / RSC_IHPSG13_FILLCAP4 +XA_CAPS<4> VDD VSS / RSC_IHPSG13_FILLCAP4 +XA_CAPS<3> VDD VSS / RSC_IHPSG13_FILLCAP4 +XA_CAPS<2> VDD VSS / RSC_IHPSG13_FILLCAP4 +XA_CAPS<1> VDD VSS / RSC_IHPSG13_FILLCAP4 +.ENDS + +.SUBCKT RM_IHPSG13_1024x16_c2_2P_BITKIT_16x2_CORNER VDD_CORE VSS +XI16 VDD_CORE VSS VDD_CORE VSS / ++ RM_IHPSG13_1024x16_c2_1P_BITKIT_CORNER +.ENDS +.SUBCKT RM_IHPSG13_1024x16_c2_2P_BITKIT_EDGE_LR A_WL B_WL NW PW VDD VSS +MN1 VSS A_WL VSS VSS sg13_lv_nmos m=1 w=300.0n l=130.00n ng=1 nrd=0 nrs=0 +MN0 VSS B_WL VSS VSS sg13_lv_nmos m=1 w=300.0n l=130.00n ng=1 nrd=0 nrs=0 +.ENDS +.SUBCKT RM_IHPSG13_1024x16_c2_2P_BITKIT_16x2_EDGE_LR A_WL<15> A_WL<14> A_WL<13> A_WL<12> ++ A_WL<11> A_WL<10> A_WL<9> A_WL<8> A_WL<7> A_WL<6> A_WL<5> A_WL<4> A_WL<3> ++ A_WL<2> A_WL<1> A_WL<0> B_WL<15> B_WL<14> B_WL<13> B_WL<12> B_WL<11> ++ B_WL<10> B_WL<9> B_WL<8> B_WL<7> B_WL<6> B_WL<5> B_WL<4> B_WL<3> B_WL<2> ++ B_WL<1> B_WL<0> VDD_CORE VSS +XI0<15> A_WL<15> B_WL<15> VDD_CORE VSS VDD_CORE VSS ++ / RM_IHPSG13_1024x16_c2_2P_BITKIT_EDGE_LR +XI0<14> A_WL<14> B_WL<14> VDD_CORE VSS VDD_CORE VSS ++ / RM_IHPSG13_1024x16_c2_2P_BITKIT_EDGE_LR +XI0<13> A_WL<13> B_WL<13> VDD_CORE VSS VDD_CORE VSS ++ / RM_IHPSG13_1024x16_c2_2P_BITKIT_EDGE_LR +XI0<12> A_WL<12> B_WL<12> VDD_CORE VSS VDD_CORE VSS ++ / RM_IHPSG13_1024x16_c2_2P_BITKIT_EDGE_LR +XI0<11> A_WL<11> B_WL<11> VDD_CORE VSS VDD_CORE VSS ++ / RM_IHPSG13_1024x16_c2_2P_BITKIT_EDGE_LR +XI0<10> A_WL<10> B_WL<10> VDD_CORE VSS VDD_CORE VSS ++ / RM_IHPSG13_1024x16_c2_2P_BITKIT_EDGE_LR +XI0<9> A_WL<9> B_WL<9> VDD_CORE VSS VDD_CORE VSS / ++ RM_IHPSG13_1024x16_c2_2P_BITKIT_EDGE_LR +XI0<8> A_WL<8> B_WL<8> VDD_CORE VSS VDD_CORE VSS / ++ RM_IHPSG13_1024x16_c2_2P_BITKIT_EDGE_LR +XI0<7> A_WL<7> B_WL<7> VDD_CORE VSS VDD_CORE VSS / ++ RM_IHPSG13_1024x16_c2_2P_BITKIT_EDGE_LR +XI0<6> A_WL<6> B_WL<6> VDD_CORE VSS VDD_CORE VSS / ++ RM_IHPSG13_1024x16_c2_2P_BITKIT_EDGE_LR +XI0<5> A_WL<5> B_WL<5> VDD_CORE VSS VDD_CORE VSS / ++ RM_IHPSG13_1024x16_c2_2P_BITKIT_EDGE_LR +XI0<4> A_WL<4> B_WL<4> VDD_CORE VSS VDD_CORE VSS / ++ RM_IHPSG13_1024x16_c2_2P_BITKIT_EDGE_LR +XI0<3> A_WL<3> B_WL<3> VDD_CORE VSS VDD_CORE VSS / ++ RM_IHPSG13_1024x16_c2_2P_BITKIT_EDGE_LR +XI0<2> A_WL<2> B_WL<2> VDD_CORE VSS VDD_CORE VSS / ++ RM_IHPSG13_1024x16_c2_2P_BITKIT_EDGE_LR +XI0<1> A_WL<1> B_WL<1> VDD_CORE VSS VDD_CORE VSS / ++ RM_IHPSG13_1024x16_c2_2P_BITKIT_EDGE_LR +XI0<0> A_WL<0> B_WL<0> VDD_CORE VSS VDD_CORE VSS / ++ RM_IHPSG13_1024x16_c2_2P_BITKIT_EDGE_LR +.ENDS +.SUBCKT RM_IHPSG13_1024x16_c2_2P_BITKIT_CELL A_BLC_BOT A_BLC_TOP A_BLT_BOT A_BLT_TOP ++ A_LWL A_RWL B_BLC_BOT B_BLC_TOP B_BLT_BOT B_BLT_TOP B_LWL B_RWL NW PW VDD VSS +MN5 NC B_RWL B_BLC_BOT PW sg13_lv_nmos m=1 w=300.0n l=130.00n ng=1 nrd=0 nrs=0 +MN4 B_BLT_BOT B_LWL NT PW sg13_lv_nmos m=1 w=300.0n l=130.00n ng=1 nrd=0 nrs=0 +MN0 NC NT VSS PW sg13_lv_nmos m=1 w=600.0n l=130.00n ng=2 nrd=0 nrs=0 +MN1 NT NC VSS PW sg13_lv_nmos m=1 w=600.0n l=130.00n ng=2 nrd=0 nrs=0 +MN3 NC A_RWL A_BLC_TOP PW sg13_lv_nmos m=1 w=300.0n l=130.00n ng=1 nrd=0 nrs=0 +MN2 A_BLT_TOP A_LWL NT PW sg13_lv_nmos m=1 w=300.0n l=130.00n ng=1 nrd=0 nrs=0 +MP1 NT NC VDD NW sg13_lv_pmos m=1 w=150.00n l=130.00n ng=1 nrd=0 nrs=0 +MP0 NC NT VDD NW sg13_lv_pmos m=1 w=150.00n l=130.00n ng=1 nrd=0 nrs=0 +R5 B_RWL B_LWL lvsres w=2.6e-07 l=6e-07 +R4 B_BLC_BOT B_BLC_TOP lvsres w=2.6e-07 l=6e-07 +R3 B_BLT_BOT B_BLT_TOP lvsres w=2.6e-07 l=6e-07 +R1 A_BLC_BOT A_BLC_TOP lvsres w=2.6e-07 l=6e-07 +R0 A_BLT_BOT A_BLT_TOP lvsres w=2.6e-07 l=6e-07 +R2 A_RWL A_LWL lvsres w=2.6e-07 l=6e-07 +.ENDS +.SUBCKT RM_IHPSG13_1024x16_c2_2P_BITKIT_16x2_SRAM A_BLC_BOT<1> A_BLC_BOT<0> A_BLC_TOP<1> ++ A_BLC_TOP<0> A_BLT_BOT<1> A_BLT_BOT<0> A_BLT_TOP<1> A_BLT_TOP<0> A_LWL<15> ++ A_LWL<14> A_LWL<13> A_LWL<12> A_LWL<11> A_LWL<10> A_LWL<9> A_LWL<8> A_LWL<7> ++ A_LWL<6> A_LWL<5> A_LWL<4> A_LWL<3> A_LWL<2> A_LWL<1> A_LWL<0> A_RWL<15> ++ A_RWL<14> A_RWL<13> A_RWL<12> A_RWL<11> A_RWL<10> A_RWL<9> A_RWL<8> A_RWL<7> ++ A_RWL<6> A_RWL<5> A_RWL<4> A_RWL<3> A_RWL<2> A_RWL<1> A_RWL<0> B_BLC_BOT<1> ++ B_BLC_BOT<0> B_BLC_TOP<1> B_BLC_TOP<0> B_BLT_BOT<1> B_BLT_BOT<0> ++ B_BLT_TOP<1> B_BLT_TOP<0> B_LWL<15> B_LWL<14> B_LWL<13> B_LWL<12> B_LWL<11> ++ B_LWL<10> B_LWL<9> B_LWL<8> B_LWL<7> B_LWL<6> B_LWL<5> B_LWL<4> B_LWL<3> ++ B_LWL<2> B_LWL<1> B_LWL<0> B_RWL<15> B_RWL<14> B_RWL<13> B_RWL<12> B_RWL<11> ++ B_RWL<10> B_RWL<9> B_RWL<8> B_RWL<7> B_RWL<6> B_RWL<5> B_RWL<4> B_RWL<3> ++ B_RWL<2> B_RWL<1> B_RWL<0> VDD_CORE VSS +XCELL<31> A_BLC_TOP<1> A_RBLC<15> A_BLT_TOP<1> A_RBLT<15> A_XWL<15> A_RWL<15> ++ B_BLC_TOP<1> B_RBLC<15> B_BLT_TOP<1> B_RBLT<15> B_XWL<15> B_RWL<15> ++ VDD_CORE VSS VDD_CORE VSS / ++ RM_IHPSG13_1024x16_c2_2P_BITKIT_CELL +XCELL<30> A_RBLC<14> A_RBLC<15> A_RBLT<14> A_RBLT<15> A_XWL<14> A_RWL<14> ++ B_RBLC<14> B_RBLC<15> B_RBLT<14> B_RBLT<15> B_XWL<14> B_RWL<14> VDD_CORE ++ VSS VDD_CORE VSS / RM_IHPSG13_1024x16_c2_2P_BITKIT_CELL +XCELL<29> A_RBLC<14> A_RBLC<13> A_RBLT<14> A_RBLT<13> A_XWL<13> A_RWL<13> ++ B_RBLC<14> B_RBLC<13> B_RBLT<14> B_RBLT<13> B_XWL<13> B_RWL<13> VDD_CORE ++ VSS VDD_CORE VSS / RM_IHPSG13_1024x16_c2_2P_BITKIT_CELL +XCELL<28> A_RBLC<12> A_RBLC<13> A_RBLT<12> A_RBLT<13> A_XWL<12> A_RWL<12> ++ B_RBLC<12> B_RBLC<13> B_RBLT<12> B_RBLT<13> B_XWL<12> B_RWL<12> VDD_CORE ++ VSS VDD_CORE VSS / RM_IHPSG13_1024x16_c2_2P_BITKIT_CELL +XCELL<27> A_RBLC<12> A_RBLC<11> A_RBLT<12> A_RBLT<11> A_XWL<11> A_RWL<11> ++ B_RBLC<12> B_RBLC<11> B_RBLT<12> B_RBLT<11> B_XWL<11> B_RWL<11> VDD_CORE ++ VSS VDD_CORE VSS / RM_IHPSG13_1024x16_c2_2P_BITKIT_CELL +XCELL<26> A_RBLC<10> A_RBLC<11> A_RBLT<10> A_RBLT<11> A_XWL<10> A_RWL<10> ++ B_RBLC<10> B_RBLC<11> B_RBLT<10> B_RBLT<11> B_XWL<10> B_RWL<10> VDD_CORE ++ VSS VDD_CORE VSS / RM_IHPSG13_1024x16_c2_2P_BITKIT_CELL +XCELL<25> A_RBLC<10> A_RBLC<9> A_RBLT<10> A_RBLT<9> A_XWL<9> A_RWL<9> ++ B_RBLC<10> B_RBLC<9> B_RBLT<10> B_RBLT<9> B_XWL<9> B_RWL<9> VDD_CORE ++ VSS VDD_CORE VSS / RM_IHPSG13_1024x16_c2_2P_BITKIT_CELL +XCELL<24> A_RBLC<8> A_RBLC<9> A_RBLT<8> A_RBLT<9> A_XWL<8> A_RWL<8> B_RBLC<8> ++ B_RBLC<9> B_RBLT<8> B_RBLT<9> B_XWL<8> B_RWL<8> VDD_CORE VSS ++ VDD_CORE VSS / RM_IHPSG13_1024x16_c2_2P_BITKIT_CELL +XCELL<23> A_RBLC<8> A_RBLC<7> A_RBLT<8> A_RBLT<7> A_XWL<7> A_RWL<7> B_RBLC<8> ++ B_RBLC<7> B_RBLT<8> B_RBLT<7> B_XWL<7> B_RWL<7> VDD_CORE VSS ++ VDD_CORE VSS / RM_IHPSG13_1024x16_c2_2P_BITKIT_CELL +XCELL<22> A_RBLC<6> A_RBLC<7> A_RBLT<6> A_RBLT<7> A_XWL<6> A_RWL<6> B_RBLC<6> ++ B_RBLC<7> B_RBLT<6> B_RBLT<7> B_XWL<6> B_RWL<6> VDD_CORE VSS ++ VDD_CORE VSS / RM_IHPSG13_1024x16_c2_2P_BITKIT_CELL +XCELL<21> A_RBLC<6> A_RBLC<5> A_RBLT<6> A_RBLT<5> A_XWL<5> A_RWL<5> B_RBLC<6> ++ B_RBLC<5> B_RBLT<6> B_RBLT<5> B_XWL<5> B_RWL<5> VDD_CORE VSS ++ VDD_CORE VSS / RM_IHPSG13_1024x16_c2_2P_BITKIT_CELL +XCELL<20> A_RBLC<4> A_RBLC<5> A_RBLT<4> A_RBLT<5> A_XWL<4> A_RWL<4> B_RBLC<4> ++ B_RBLC<5> B_RBLT<4> B_RBLT<5> B_XWL<4> B_RWL<4> VDD_CORE VSS ++ VDD_CORE VSS / RM_IHPSG13_1024x16_c2_2P_BITKIT_CELL +XCELL<19> A_RBLC<4> A_RBLC<3> A_RBLT<4> A_RBLT<3> A_XWL<3> A_RWL<3> B_RBLC<4> ++ B_RBLC<3> B_RBLT<4> B_RBLT<3> B_XWL<3> B_RWL<3> VDD_CORE VSS ++ VDD_CORE VSS / RM_IHPSG13_1024x16_c2_2P_BITKIT_CELL +XCELL<18> A_RBLC<2> A_RBLC<3> A_RBLT<2> A_RBLT<3> A_XWL<2> A_RWL<2> B_RBLC<2> ++ B_RBLC<3> B_RBLT<2> B_RBLT<3> B_XWL<2> B_RWL<2> VDD_CORE VSS ++ VDD_CORE VSS / RM_IHPSG13_1024x16_c2_2P_BITKIT_CELL +XCELL<17> A_RBLC<2> A_RBLC<1> A_RBLT<2> A_RBLT<1> A_XWL<1> A_RWL<1> B_RBLC<2> ++ B_RBLC<1> B_RBLT<2> B_RBLT<1> B_XWL<1> B_RWL<1> VDD_CORE VSS ++ VDD_CORE VSS / RM_IHPSG13_1024x16_c2_2P_BITKIT_CELL +XCELL<16> A_BLC_BOT<1> A_RBLC<1> A_BLT_BOT<1> A_RBLT<1> A_XWL<0> A_RWL<0> ++ B_BLC_BOT<1> B_RBLC<1> B_BLT_BOT<1> B_RBLT<1> B_XWL<0> B_RWL<0> VDD_CORE ++ VSS VDD_CORE VSS / RM_IHPSG13_1024x16_c2_2P_BITKIT_CELL +XCELL<15> A_BLC_TOP<0> A_LBLC<15> A_BLT_TOP<0> A_LBLT<15> A_LWL<15> A_XWL<15> ++ B_BLC_TOP<0> B_LBLC<15> B_BLT_TOP<0> B_LBLT<15> B_LWL<15> B_XWL<15> ++ VDD_CORE VSS VDD_CORE VSS / ++ RM_IHPSG13_1024x16_c2_2P_BITKIT_CELL +XCELL<14> A_LBLC<14> A_LBLC<15> A_LBLT<14> A_LBLT<15> A_LWL<14> A_XWL<14> ++ B_LBLC<14> B_LBLC<15> B_LBLT<14> B_LBLT<15> B_LWL<14> B_XWL<14> VDD_CORE ++ VSS VDD_CORE VSS / RM_IHPSG13_1024x16_c2_2P_BITKIT_CELL +XCELL<13> A_LBLC<14> A_LBLC<13> A_LBLT<14> A_LBLT<13> A_LWL<13> A_XWL<13> ++ B_LBLC<14> B_LBLC<13> B_LBLT<14> B_LBLT<13> B_LWL<13> B_XWL<13> VDD_CORE ++ VSS VDD_CORE VSS / RM_IHPSG13_1024x16_c2_2P_BITKIT_CELL +XCELL<12> A_LBLC<12> A_LBLC<13> A_LBLT<12> A_LBLT<13> A_LWL<12> A_XWL<12> ++ B_LBLC<12> B_LBLC<13> B_LBLT<12> B_LBLT<13> B_LWL<12> B_XWL<12> VDD_CORE ++ VSS VDD_CORE VSS / RM_IHPSG13_1024x16_c2_2P_BITKIT_CELL +XCELL<11> A_LBLC<12> A_LBLC<11> A_LBLT<12> A_LBLT<11> A_LWL<11> A_XWL<11> ++ B_LBLC<12> B_LBLC<11> B_LBLT<12> B_LBLT<11> B_LWL<11> B_XWL<11> VDD_CORE ++ VSS VDD_CORE VSS / RM_IHPSG13_1024x16_c2_2P_BITKIT_CELL +XCELL<10> A_LBLC<10> A_LBLC<11> A_LBLT<10> A_LBLT<11> A_LWL<10> A_XWL<10> ++ B_LBLC<10> B_LBLC<11> B_LBLT<10> B_LBLT<11> B_LWL<10> B_XWL<10> VDD_CORE ++ VSS VDD_CORE VSS / RM_IHPSG13_1024x16_c2_2P_BITKIT_CELL +XCELL<9> A_LBLC<10> A_LBLC<9> A_LBLT<10> A_LBLT<9> A_LWL<9> A_XWL<9> ++ B_LBLC<10> B_LBLC<9> B_LBLT<10> B_LBLT<9> B_LWL<9> B_XWL<9> VDD_CORE ++ VSS VDD_CORE VSS / RM_IHPSG13_1024x16_c2_2P_BITKIT_CELL +XCELL<8> A_LBLC<8> A_LBLC<9> A_LBLT<8> A_LBLT<9> A_LWL<8> A_XWL<8> B_LBLC<8> ++ B_LBLC<9> B_LBLT<8> B_LBLT<9> B_LWL<8> B_XWL<8> VDD_CORE VSS ++ VDD_CORE VSS / RM_IHPSG13_1024x16_c2_2P_BITKIT_CELL +XCELL<7> A_LBLC<8> A_LBLC<7> A_LBLT<8> A_LBLT<7> A_LWL<7> A_XWL<7> B_LBLC<8> ++ B_LBLC<7> B_LBLT<8> B_LBLT<7> B_LWL<7> B_XWL<7> VDD_CORE VSS ++ VDD_CORE VSS / RM_IHPSG13_1024x16_c2_2P_BITKIT_CELL +XCELL<6> A_LBLC<6> A_LBLC<7> A_LBLT<6> A_LBLT<7> A_LWL<6> A_XWL<6> B_LBLC<6> ++ B_LBLC<7> B_LBLT<6> B_LBLT<7> B_LWL<6> B_XWL<6> VDD_CORE VSS ++ VDD_CORE VSS / RM_IHPSG13_1024x16_c2_2P_BITKIT_CELL +XCELL<5> A_LBLC<6> A_LBLC<5> A_LBLT<6> A_LBLT<5> A_LWL<5> A_XWL<5> B_LBLC<6> ++ B_LBLC<5> B_LBLT<6> B_LBLT<5> B_LWL<5> B_XWL<5> VDD_CORE VSS ++ VDD_CORE VSS / RM_IHPSG13_1024x16_c2_2P_BITKIT_CELL +XCELL<4> A_LBLC<4> A_LBLC<5> A_LBLT<4> A_LBLT<5> A_LWL<4> A_XWL<4> B_LBLC<4> ++ B_LBLC<5> B_LBLT<4> B_LBLT<5> B_LWL<4> B_XWL<4> VDD_CORE VSS ++ VDD_CORE VSS / RM_IHPSG13_1024x16_c2_2P_BITKIT_CELL +XCELL<3> A_LBLC<4> A_LBLC<3> A_LBLT<4> A_LBLT<3> A_LWL<3> A_XWL<3> B_LBLC<4> ++ B_LBLC<3> B_LBLT<4> B_LBLT<3> B_LWL<3> B_XWL<3> VDD_CORE VSS ++ VDD_CORE VSS / RM_IHPSG13_1024x16_c2_2P_BITKIT_CELL +XCELL<2> A_LBLC<2> A_LBLC<3> A_LBLT<2> A_LBLT<3> A_LWL<2> A_XWL<2> B_LBLC<2> ++ B_LBLC<3> B_LBLT<2> B_LBLT<3> B_LWL<2> B_XWL<2> VDD_CORE VSS ++ VDD_CORE VSS / RM_IHPSG13_1024x16_c2_2P_BITKIT_CELL +XCELL<1> A_LBLC<2> A_LBLC<1> A_LBLT<2> A_LBLT<1> A_LWL<1> A_XWL<1> B_LBLC<2> ++ B_LBLC<1> B_LBLT<2> B_LBLT<1> B_LWL<1> B_XWL<1> VDD_CORE VSS ++ VDD_CORE VSS / RM_IHPSG13_1024x16_c2_2P_BITKIT_CELL +XCELL<0> A_BLC_BOT<0> A_LBLC<1> A_BLT_BOT<0> A_LBLT<1> A_LWL<0> A_XWL<0> ++ B_BLC_BOT<0> B_LBLC<1> B_BLT_BOT<0> B_LBLT<1> B_LWL<0> B_XWL<0> VDD_CORE ++ VSS VDD_CORE VSS / RM_IHPSG13_1024x16_c2_2P_BITKIT_CELL +.ENDS +.SUBCKT RM_IHPSG13_1024x16_c2_2P_BITKIT_EDGE_TB A_BLC A_BLT B_BLC B_BLT NW PW VDD VSS +.ENDS +.SUBCKT RM_IHPSG13_1024x16_c2_2P_BITKIT_16x2_EDGE_TB A_BLC<1> A_BLC<0> A_BLT<1> A_BLT<0> ++ B_BLC<1> B_BLC<0> B_BLT<1> B_BLT<0> VDD_CORE VSS +XEDGE<1> A_BLC<1> A_BLT<1> B_BLC<1> B_BLT<1> VDD_CORE VSS ++ VDD_CORE VSS / RM_IHPSG13_1024x16_c2_2P_BITKIT_EDGE_TB +XEDGE<0> A_BLC<0> A_BLT<0> B_BLC<0> B_BLT<0> VDD_CORE VSS ++ VDD_CORE VSS / RM_IHPSG13_1024x16_c2_2P_BITKIT_EDGE_TB +.ENDS +.SUBCKT RM_IHPSG13_1024x16_c2_2P_BITKIT_TAP A_BLC A_BLT B_BLC B_BLT NW PW VDD VSS +.ENDS +.SUBCKT RM_IHPSG13_1024x16_c2_2P_BITKIT_16x2_TAP A_BLC<1> A_BLC<0> A_BLT<1> A_BLT<0> ++ B_BLC<1> B_BLC<0> B_BLT<1> B_BLT<0> VDD_CORE VSS +XIEDGEBP_COL1<1> A_BLC<1> A_BLT<1> B_BLC<1> B_BLT<1> VDD_CORE VSS ++ VDD_CORE VSS / RM_IHPSG13_1024x16_c2_2P_BITKIT_EDGE_TB +XIEDGEBP_COL1<0> A_BLC<1> A_BLT<1> B_BLC<1> B_BLT<1> VDD_CORE VSS ++ VDD_CORE VSS / RM_IHPSG13_1024x16_c2_2P_BITKIT_EDGE_TB +XIEDGEBP_COL2<1> A_BLC<0> A_BLT<0> B_BLC<0> B_BLT<0> VDD_CORE VSS ++ VDD_CORE VSS / RM_IHPSG13_1024x16_c2_2P_BITKIT_EDGE_TB +XIEDGEBP_COL2<0> A_BLC<0> A_BLT<0> B_BLC<0> B_BLT<0> VDD_CORE VSS ++ VDD_CORE VSS / RM_IHPSG13_1024x16_c2_2P_BITKIT_EDGE_TB +XITAP<1> A_BLC<1> A_BLT<1> B_BLC<1> B_BLT<1> VDD_CORE VSS ++ VDD_CORE VSS / RM_IHPSG13_1024x16_c2_2P_BITKIT_TAP +XITAP<0> A_BLC<0> A_BLT<0> B_BLC<0> B_BLT<0> VDD_CORE VSS ++ VDD_CORE VSS / RM_IHPSG13_1024x16_c2_2P_BITKIT_TAP +.ENDS + + +.SUBCKT RM_IHPSG13_1024x16_c2_1P_BITKIT_TAP_LR NW PW VDD VSS +.ENDS +.SUBCKT RM_IHPSG13_1024x16_c2_2P_BITKIT_16x2_TAP_LR VDD_CORE VSS +XCORNER<1> VDD_CORE VSS VDD_CORE VSS / ++ RM_IHPSG13_1024x16_c2_1P_BITKIT_CORNER +XCORNER<0> VDD_CORE VSS VDD_CORE VSS / ++ RM_IHPSG13_1024x16_c2_1P_BITKIT_CORNER +XTAP_BORDER VDD_CORE VSS VDD_CORE VSS / ++ RM_IHPSG13_1024x16_c2_1P_BITKIT_TAP_LR +.ENDS + +.SUBCKT RSC_IHPSG13_CBUFX12 A Z VDD VSS +MN1 Z net6 VSS VSS sg13_lv_nmos m=1 w=4.23u l=130.00n ng=6 nrd=0 nrs=0 +MN0 net6 A VSS VSS sg13_lv_nmos m=1 w=1.41u l=130.00n ng=2 nrd=0 nrs=0 +MP1 Z net6 VDD VDD sg13_lv_pmos m=1 w=9.72u l=130.00n ng=6 nrd=0 nrs=0 +MP0 net6 A VDD VDD sg13_lv_pmos m=1 w=3.24u l=130.00n ng=2 nrd=0 nrs=0 +.ENDS +.SUBCKT RM_IHPSG13_1024x16_c2_2P_COLDRV13X12 ADDR_COL_I<1> ADDR_COL_I<0> ADDR_COL_O<1> ++ ADDR_COL_O<0> ADDR_DEC_I<7> ADDR_DEC_I<6> ADDR_DEC_I<5> ADDR_DEC_I<4> ++ ADDR_DEC_I<3> ADDR_DEC_I<2> ADDR_DEC_I<1> ADDR_DEC_I<0> ADDR_DEC_O<7> ++ ADDR_DEC_O<6> ADDR_DEC_O<5> ADDR_DEC_O<4> ADDR_DEC_O<3> ADDR_DEC_O<2> ++ ADDR_DEC_O<1> ADDR_DEC_O<0> DCLK_I DCLK_O RCLK_I RCLK_O WCLK_I WCLK_O ++ VDD VSS +XI1<3> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI1<2> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI1<1> VDD VSS / RSC_IHPSG13_FILLCAP8 +XWCLK_DRV WCLK_I WCLK_O VDD VSS / RSC_IHPSG13_CBUFX12 +XRCLK_DRV RCLK_I RCLK_O VDD VSS / RSC_IHPSG13_CBUFX12 +XDCLK_DRV DCLK_I DCLK_O VDD VSS / RSC_IHPSG13_CBUFX12 +XADDR_COL_DRV<1> ADDR_COL_I<1> ADDR_COL_O<1> VDD VSS / ++ RSC_IHPSG13_CBUFX12 +XADDR_COL_DRV<0> ADDR_COL_I<0> ADDR_COL_O<0> VDD VSS / ++ RSC_IHPSG13_CBUFX12 +XADDR_DEC_DRV<7> ADDR_DEC_I<7> ADDR_DEC_O<7> VDD VSS / ++ RSC_IHPSG13_CBUFX12 +XADDR_DEC_DRV<6> ADDR_DEC_I<6> ADDR_DEC_O<6> VDD VSS / ++ RSC_IHPSG13_CBUFX12 +XADDR_DEC_DRV<5> ADDR_DEC_I<5> ADDR_DEC_O<5> VDD VSS / ++ RSC_IHPSG13_CBUFX12 +XADDR_DEC_DRV<4> ADDR_DEC_I<4> ADDR_DEC_O<4> VDD VSS / ++ RSC_IHPSG13_CBUFX12 +XADDR_DEC_DRV<3> ADDR_DEC_I<3> ADDR_DEC_O<3> VDD VSS / ++ RSC_IHPSG13_CBUFX12 +XADDR_DEC_DRV<2> ADDR_DEC_I<2> ADDR_DEC_O<2> VDD VSS / ++ RSC_IHPSG13_CBUFX12 +XADDR_DEC_DRV<1> ADDR_DEC_I<1> ADDR_DEC_O<1> VDD VSS / ++ RSC_IHPSG13_CBUFX12 +XADDR_DEC_DRV<0> ADDR_DEC_I<0> ADDR_DEC_O<0> VDD VSS / ++ RSC_IHPSG13_CBUFX12 +XI0<6> VDD VSS / RSC_IHPSG13_FILLCAP4 +XI0<5> VDD VSS / RSC_IHPSG13_FILLCAP4 +XI0<4> VDD VSS / RSC_IHPSG13_FILLCAP4 +XI0<3> VDD VSS / RSC_IHPSG13_FILLCAP4 +XI0<2> VDD VSS / RSC_IHPSG13_FILLCAP4 +XI0<1> VDD VSS / RSC_IHPSG13_FILLCAP4 +.ENDS +.SUBCKT RSC_IHPSG13_WLDRVX12 A Z VDD VSS +MN1 Z net6 VSS VSS sg13_lv_nmos m=1 w=1.41u l=130.00n ng=2 nrd=0 nrs=0 +MN0 net6 A VSS VSS sg13_lv_nmos m=1 w=1.8u l=130.00n ng=2 nrd=0 nrs=0 +MP1 Z net6 VDD VDD sg13_lv_pmos m=1 w=9.72u l=130.00n ng=6 nrd=0 nrs=0 +MP0 net6 A VDD VDD sg13_lv_pmos m=1 w=900.0n l=130.00n ng=1 nrd=0 nrs=0 +.ENDS +.SUBCKT RM_IHPSG13_1024x16_c2_2P_WLDRV16X12 A<15> A<14> A<13> A<12> A<11> A<10> A<9> A<8> ++ A<7> A<6> A<5> A<4> A<3> A<2> A<1> A<0> Z<15> Z<14> Z<13> Z<12> Z<11> Z<10> ++ Z<9> Z<8> Z<7> Z<6> Z<5> Z<4> Z<3> Z<2> Z<1> Z<0> VDD VSS +XBUF<15> A<15> Z<15> VDD VSS / RSC_IHPSG13_WLDRVX12 +XBUF<14> A<14> Z<14> VDD VSS / RSC_IHPSG13_WLDRVX12 +XBUF<13> A<13> Z<13> VDD VSS / RSC_IHPSG13_WLDRVX12 +XBUF<12> A<12> Z<12> VDD VSS / RSC_IHPSG13_WLDRVX12 +XBUF<11> A<11> Z<11> VDD VSS / RSC_IHPSG13_WLDRVX12 +XBUF<10> A<10> Z<10> VDD VSS / RSC_IHPSG13_WLDRVX12 +XBUF<9> A<9> Z<9> VDD VSS / RSC_IHPSG13_WLDRVX12 +XBUF<8> A<8> Z<8> VDD VSS / RSC_IHPSG13_WLDRVX12 +XBUF<7> A<7> Z<7> VDD VSS / RSC_IHPSG13_WLDRVX12 +XBUF<6> A<6> Z<6> VDD VSS / RSC_IHPSG13_WLDRVX12 +XBUF<5> A<5> Z<5> VDD VSS / RSC_IHPSG13_WLDRVX12 +XBUF<4> A<4> Z<4> VDD VSS / RSC_IHPSG13_WLDRVX12 +XBUF<3> A<3> Z<3> VDD VSS / RSC_IHPSG13_WLDRVX12 +XBUF<2> A<2> Z<2> VDD VSS / RSC_IHPSG13_WLDRVX12 +XBUF<1> A<1> Z<1> VDD VSS / RSC_IHPSG13_WLDRVX12 +XBUF<0> A<0> Z<0> VDD VSS / RSC_IHPSG13_WLDRVX12 +.ENDS +.SUBCKT RM_IHPSG13_1024x16_c2_2P_DEC04 ADDR<3> ADDR<2> ADDR<1> ADDR<0> CS ECLK_H_BOT ++ ECLK_H_TOP ECLK_L_BOT ECLK_L_TOP WL<15> WL<14> WL<13> WL<12> WL<11> WL<10> ++ WL<9> WL<8> WL<7> WL<6> WL<5> WL<4> WL<3> WL<2> WL<1> WL<0> VDD VSS +XI0<3> PADR<1> PADR<0> sel01<3> VDD VSS / RSC_IHPSG13_NAND2X2 +XI0<2> PADR<1> NADR<0> sel01<2> VDD VSS / RSC_IHPSG13_NAND2X2 +XI0<1> NADR<1> PADR<0> sel01<1> VDD VSS / RSC_IHPSG13_NAND2X2 +XI0<0> NADR<1> NADR<0> sel01<0> VDD VSS / RSC_IHPSG13_NAND2X2 +XI4 ECLK_L_BOT EN VDD VSS / RSC_IHPSG13_CINVX4 +XI5 ECLK_H_BOT ECLK_L_BOT VDD VSS / RSC_IHPSG13_CINVX2 +XI3<3> PADR<3> NADR<3> VDD VSS / RSC_IHPSG13_INVX2 +XI3<2> PADR<2> NADR<2> VDD VSS / RSC_IHPSG13_INVX2 +XI3<1> PADR<1> NADR<1> VDD VSS / RSC_IHPSG13_INVX2 +XI3<0> PADR<0> NADR<0> VDD VSS / RSC_IHPSG13_INVX2 +XR0 ECLK_H_BOT ECLK_H_TOP / RSC_IHPSG13_MET2RES +XI11 ECLK_L_BOT ECLK_L_TOP / RSC_IHPSG13_MET2RES +XI1<3> PADR<2> PADR<3> CS sel23<3> VDD VSS / RSC_IHPSG13_NAND3X2 +XI1<2> NADR<2> PADR<3> CS sel23<2> VDD VSS / RSC_IHPSG13_NAND3X2 +XI1<1> PADR<2> NADR<3> CS sel23<1> VDD VSS / RSC_IHPSG13_NAND3X2 +XI1<0> NADR<2> NADR<3> CS sel23<0> VDD VSS / RSC_IHPSG13_NAND3X2 +XI2<15> sel23<3> sel01<3> EN WL<15> VDD VSS / RSC_IHPSG13_NOR3X2 +XI2<14> sel23<3> sel01<2> EN WL<14> VDD VSS / RSC_IHPSG13_NOR3X2 +XI2<13> sel23<3> sel01<1> EN WL<13> VDD VSS / RSC_IHPSG13_NOR3X2 +XI2<12> sel23<3> sel01<0> EN WL<12> VDD VSS / RSC_IHPSG13_NOR3X2 +XI2<11> sel23<2> sel01<3> EN WL<11> VDD VSS / RSC_IHPSG13_NOR3X2 +XI2<10> sel23<2> sel01<2> EN WL<10> VDD VSS / RSC_IHPSG13_NOR3X2 +XI2<9> sel23<2> sel01<1> EN WL<9> VDD VSS / RSC_IHPSG13_NOR3X2 +XI2<8> sel23<2> sel01<0> EN WL<8> VDD VSS / RSC_IHPSG13_NOR3X2 +XI2<7> sel23<1> sel01<3> EN WL<7> VDD VSS / RSC_IHPSG13_NOR3X2 +XI2<6> sel23<1> sel01<2> EN WL<6> VDD VSS / RSC_IHPSG13_NOR3X2 +XI2<5> sel23<1> sel01<1> EN WL<5> VDD VSS / RSC_IHPSG13_NOR3X2 +XI2<4> sel23<1> sel01<0> EN WL<4> VDD VSS / RSC_IHPSG13_NOR3X2 +XI2<3> sel23<0> sel01<3> EN WL<3> VDD VSS / RSC_IHPSG13_NOR3X2 +XI2<2> sel23<0> sel01<2> EN WL<2> VDD VSS / RSC_IHPSG13_NOR3X2 +XI2<1> sel23<0> sel01<1> EN WL<1> VDD VSS / RSC_IHPSG13_NOR3X2 +XI2<0> sel23<0> sel01<0> EN WL<0> VDD VSS / RSC_IHPSG13_NOR3X2 +XCAPS4 VDD VSS / RSC_IHPSG13_FILLCAP4 +XLATCH<3> CS ADDR<3> PADR<3> VDD VSS / RSC_IHPSG13_LHPQX2 +XLATCH<2> CS ADDR<2> PADR<2> VDD VSS / RSC_IHPSG13_LHPQX2 +XLATCH<1> CS ADDR<1> PADR<1> VDD VSS / RSC_IHPSG13_LHPQX2 +XLATCH<0> CS ADDR<0> PADR<0> VDD VSS / RSC_IHPSG13_LHPQX2 +.ENDS +.SUBCKT RM_IHPSG13_1024x16_c2_2P_DEC02 ADDR<1> ADDR<0> CS CS_OUT VDD VSS +XDEC ADDR<1> NADDR<0> CS net1 VDD VSS / RSC_IHPSG13_NAND3X2 +XADDRINV ADDR<0> NADDR<0> VDD VSS / RSC_IHPSG13_INVX2 +XDECINV net1 CS_OUT VDD VSS / RSC_IHPSG13_INVX4 +XI2<1> VDD VSS / RSC_IHPSG13_FILLCAP4 +XI2<0> VDD VSS / RSC_IHPSG13_FILLCAP4 +.ENDS +.SUBCKT RM_IHPSG13_1024x16_c2_2P_DEC01 ADDR<1> ADDR<0> CS CS_OUT VDD VSS +XDEC NADDR<1> ADDR<0> CS net1 VDD VSS / RSC_IHPSG13_NAND3X2 +XADDRINV ADDR<1> NADDR<1> VDD VSS / RSC_IHPSG13_INVX2 +XDECINV net1 CS_OUT VDD VSS / RSC_IHPSG13_INVX4 +XI2<1> VDD VSS / RSC_IHPSG13_FILLCAP4 +XI2<0> VDD VSS / RSC_IHPSG13_FILLCAP4 +.ENDS +.SUBCKT RM_IHPSG13_1024x16_c2_2P_DEC00 ADDR<1> ADDR<0> CS CS_OUT VDD VSS +XDEC NADDR<1> NADDR<0> CS net1 VDD VSS / RSC_IHPSG13_NAND3X2 +XADDRINV<1> ADDR<1> NADDR<1> VDD VSS / RSC_IHPSG13_INVX2 +XADDRINV<0> ADDR<0> NADDR<0> VDD VSS / RSC_IHPSG13_INVX2 +XI1<1> VDD VSS / RSC_IHPSG13_FILLCAP4 +XI1<0> VDD VSS / RSC_IHPSG13_FILLCAP4 +XDECINV net1 CS_OUT VDD VSS / RSC_IHPSG13_INVX4 +.ENDS +.SUBCKT RM_IHPSG13_1024x16_c2_2P_DEC03 ADDR<1> ADDR<0> CS CS_OUT VDD VSS +XDEC ADDR<1> ADDR<0> CS net1 VDD VSS / RSC_IHPSG13_NAND3X2 +XDECINV net1 CS_OUT VDD VSS / RSC_IHPSG13_INVX4 +XI0<1> VDD VSS / RSC_IHPSG13_FILLCAP4 +XI0<0> VDD VSS / RSC_IHPSG13_FILLCAP4 +.ENDS +.SUBCKT RM_IHPSG13_1024x16_c2_2P_ROWDEC9 ADDR_N_I<8> ADDR_N_I<7> ADDR_N_I<6> ADDR_N_I<5> ++ ADDR_N_I<4> ADDR_N_I<3> ADDR_N_I<2> ADDR_N_I<1> ADDR_N_I<0> CS_I ECLK_I ++ WL_O<511> WL_O<510> WL_O<509> WL_O<508> WL_O<507> WL_O<506> WL_O<505> ++ WL_O<504> WL_O<503> WL_O<502> WL_O<501> WL_O<500> WL_O<499> WL_O<498> ++ WL_O<497> WL_O<496> WL_O<495> WL_O<494> WL_O<493> WL_O<492> WL_O<491> ++ WL_O<490> WL_O<489> WL_O<488> WL_O<487> WL_O<486> WL_O<485> WL_O<484> ++ WL_O<483> WL_O<482> WL_O<481> WL_O<480> WL_O<479> WL_O<478> WL_O<477> ++ WL_O<476> WL_O<475> WL_O<474> WL_O<473> WL_O<472> WL_O<471> WL_O<470> ++ WL_O<469> WL_O<468> WL_O<467> WL_O<466> WL_O<465> WL_O<464> WL_O<463> ++ WL_O<462> WL_O<461> WL_O<460> WL_O<459> WL_O<458> WL_O<457> WL_O<456> ++ WL_O<455> WL_O<454> WL_O<453> WL_O<452> WL_O<451> WL_O<450> WL_O<449> ++ WL_O<448> WL_O<447> WL_O<446> WL_O<445> WL_O<444> WL_O<443> WL_O<442> ++ WL_O<441> WL_O<440> WL_O<439> WL_O<438> WL_O<437> WL_O<436> WL_O<435> ++ WL_O<434> WL_O<433> WL_O<432> WL_O<431> WL_O<430> WL_O<429> WL_O<428> ++ WL_O<427> WL_O<426> WL_O<425> WL_O<424> WL_O<423> WL_O<422> WL_O<421> ++ WL_O<420> WL_O<419> WL_O<418> WL_O<417> WL_O<416> WL_O<415> WL_O<414> ++ WL_O<413> WL_O<412> WL_O<411> WL_O<410> WL_O<409> WL_O<408> WL_O<407> ++ WL_O<406> WL_O<405> WL_O<404> WL_O<403> WL_O<402> WL_O<401> WL_O<400> ++ WL_O<399> WL_O<398> WL_O<397> WL_O<396> WL_O<395> WL_O<394> WL_O<393> ++ WL_O<392> WL_O<391> WL_O<390> WL_O<389> WL_O<388> WL_O<387> WL_O<386> ++ WL_O<385> WL_O<384> WL_O<383> WL_O<382> WL_O<381> WL_O<380> WL_O<379> ++ WL_O<378> WL_O<377> WL_O<376> WL_O<375> WL_O<374> WL_O<373> WL_O<372> ++ WL_O<371> WL_O<370> WL_O<369> WL_O<368> WL_O<367> WL_O<366> WL_O<365> ++ WL_O<364> WL_O<363> WL_O<362> WL_O<361> WL_O<360> WL_O<359> WL_O<358> ++ WL_O<357> WL_O<356> WL_O<355> WL_O<354> WL_O<353> WL_O<352> WL_O<351> ++ WL_O<350> WL_O<349> WL_O<348> WL_O<347> WL_O<346> WL_O<345> WL_O<344> ++ WL_O<343> WL_O<342> WL_O<341> WL_O<340> WL_O<339> WL_O<338> WL_O<337> ++ WL_O<336> WL_O<335> WL_O<334> WL_O<333> WL_O<332> WL_O<331> WL_O<330> ++ WL_O<329> WL_O<328> WL_O<327> WL_O<326> WL_O<325> WL_O<324> WL_O<323> ++ WL_O<322> WL_O<321> WL_O<320> WL_O<319> WL_O<318> WL_O<317> WL_O<316> ++ WL_O<315> WL_O<314> WL_O<313> WL_O<312> WL_O<311> WL_O<310> WL_O<309> ++ WL_O<308> WL_O<307> WL_O<306> WL_O<305> WL_O<304> WL_O<303> WL_O<302> ++ WL_O<301> WL_O<300> WL_O<299> WL_O<298> WL_O<297> WL_O<296> WL_O<295> ++ WL_O<294> WL_O<293> WL_O<292> WL_O<291> WL_O<290> WL_O<289> WL_O<288> ++ WL_O<287> WL_O<286> WL_O<285> WL_O<284> WL_O<283> WL_O<282> WL_O<281> ++ WL_O<280> WL_O<279> WL_O<278> WL_O<277> WL_O<276> WL_O<275> WL_O<274> ++ WL_O<273> WL_O<272> WL_O<271> WL_O<270> WL_O<269> WL_O<268> WL_O<267> ++ WL_O<266> WL_O<265> WL_O<264> WL_O<263> WL_O<262> WL_O<261> WL_O<260> ++ WL_O<259> WL_O<258> WL_O<257> WL_O<256> WL_O<255> WL_O<254> WL_O<253> ++ WL_O<252> WL_O<251> WL_O<250> WL_O<249> WL_O<248> WL_O<247> WL_O<246> ++ WL_O<245> WL_O<244> WL_O<243> WL_O<242> WL_O<241> WL_O<240> WL_O<239> ++ WL_O<238> WL_O<237> WL_O<236> WL_O<235> WL_O<234> WL_O<233> WL_O<232> ++ WL_O<231> WL_O<230> WL_O<229> WL_O<228> WL_O<227> WL_O<226> WL_O<225> ++ WL_O<224> WL_O<223> WL_O<222> WL_O<221> WL_O<220> WL_O<219> WL_O<218> ++ WL_O<217> WL_O<216> WL_O<215> WL_O<214> WL_O<213> WL_O<212> WL_O<211> ++ WL_O<210> WL_O<209> WL_O<208> WL_O<207> WL_O<206> WL_O<205> WL_O<204> ++ WL_O<203> WL_O<202> WL_O<201> WL_O<200> WL_O<199> WL_O<198> WL_O<197> ++ WL_O<196> WL_O<195> WL_O<194> WL_O<193> WL_O<192> WL_O<191> WL_O<190> ++ WL_O<189> WL_O<188> WL_O<187> WL_O<186> WL_O<185> WL_O<184> WL_O<183> ++ WL_O<182> WL_O<181> WL_O<180> WL_O<179> WL_O<178> WL_O<177> WL_O<176> ++ WL_O<175> WL_O<174> WL_O<173> WL_O<172> WL_O<171> WL_O<170> WL_O<169> ++ WL_O<168> WL_O<167> WL_O<166> WL_O<165> WL_O<164> WL_O<163> WL_O<162> ++ WL_O<161> WL_O<160> WL_O<159> WL_O<158> WL_O<157> WL_O<156> WL_O<155> ++ WL_O<154> WL_O<153> WL_O<152> WL_O<151> WL_O<150> WL_O<149> WL_O<148> ++ WL_O<147> WL_O<146> WL_O<145> WL_O<144> WL_O<143> WL_O<142> WL_O<141> ++ WL_O<140> WL_O<139> WL_O<138> WL_O<137> WL_O<136> WL_O<135> WL_O<134> ++ WL_O<133> WL_O<132> WL_O<131> WL_O<130> WL_O<129> WL_O<128> WL_O<127> ++ WL_O<126> WL_O<125> WL_O<124> WL_O<123> WL_O<122> WL_O<121> WL_O<120> ++ WL_O<119> WL_O<118> WL_O<117> WL_O<116> WL_O<115> WL_O<114> WL_O<113> ++ WL_O<112> WL_O<111> WL_O<110> WL_O<109> WL_O<108> WL_O<107> WL_O<106> ++ WL_O<105> WL_O<104> WL_O<103> WL_O<102> WL_O<101> WL_O<100> WL_O<99> ++ WL_O<98> WL_O<97> WL_O<96> WL_O<95> WL_O<94> WL_O<93> WL_O<92> WL_O<91> ++ WL_O<90> WL_O<89> WL_O<88> WL_O<87> WL_O<86> WL_O<85> WL_O<84> WL_O<83> ++ WL_O<82> WL_O<81> WL_O<80> WL_O<79> WL_O<78> WL_O<77> WL_O<76> WL_O<75> ++ WL_O<74> WL_O<73> WL_O<72> WL_O<71> WL_O<70> WL_O<69> WL_O<68> WL_O<67> ++ WL_O<66> WL_O<65> WL_O<64> WL_O<63> WL_O<62> WL_O<61> WL_O<60> WL_O<59> ++ WL_O<58> WL_O<57> WL_O<56> WL_O<55> WL_O<54> WL_O<53> WL_O<52> WL_O<51> ++ WL_O<50> WL_O<49> WL_O<48> WL_O<47> WL_O<46> WL_O<45> WL_O<44> WL_O<43> ++ WL_O<42> WL_O<41> WL_O<40> WL_O<39> WL_O<38> WL_O<37> WL_O<36> WL_O<35> ++ WL_O<34> WL_O<33> WL_O<32> WL_O<31> WL_O<30> WL_O<29> WL_O<28> WL_O<27> ++ WL_O<26> WL_O<25> WL_O<24> WL_O<23> WL_O<22> WL_O<21> WL_O<20> WL_O<19> ++ WL_O<18> WL_O<17> WL_O<16> WL_O<15> WL_O<14> WL_O<13> WL_O<12> WL_O<11> ++ WL_O<10> WL_O<9> WL_O<8> WL_O<7> WL_O<6> WL_O<5> WL_O<4> WL_O<3> WL_O<2> ++ WL_O<1> WL_O<0> VDD VSS +XSEL<31> ADDR_N_I<3> ADDR_N_I<2> ADDR_N_I<1> ADDR_N_I<0> CS00<31> ECLK_H<31> ++ ECLK_H<32> ECLK_B<31> ECLK_B<32> WL_O<511> WL_O<510> WL_O<509> WL_O<508> ++ WL_O<507> WL_O<506> WL_O<505> WL_O<504> WL_O<503> WL_O<502> WL_O<501> ++ WL_O<500> WL_O<499> WL_O<498> WL_O<497> WL_O<496> VDD VSS / ++ RM_IHPSG13_1024x16_c2_2P_DEC04 +XSEL<30> ADDR_N_I<3> ADDR_N_I<2> ADDR_N_I<1> ADDR_N_I<0> CS00<30> ECLK_H<30> ++ ECLK_H<31> ECLK_B<30> ECLK_B<31> WL_O<495> WL_O<494> WL_O<493> WL_O<492> ++ WL_O<491> WL_O<490> WL_O<489> WL_O<488> WL_O<487> WL_O<486> WL_O<485> ++ WL_O<484> WL_O<483> WL_O<482> WL_O<481> WL_O<480> VDD VSS / ++ RM_IHPSG13_1024x16_c2_2P_DEC04 +XSEL<29> ADDR_N_I<3> ADDR_N_I<2> ADDR_N_I<1> ADDR_N_I<0> CS00<29> ECLK_H<29> ++ ECLK_H<30> ECLK_B<29> ECLK_B<30> WL_O<479> WL_O<478> WL_O<477> WL_O<476> ++ WL_O<475> WL_O<474> WL_O<473> WL_O<472> WL_O<471> WL_O<470> WL_O<469> ++ WL_O<468> WL_O<467> WL_O<466> WL_O<465> WL_O<464> VDD VSS / ++ RM_IHPSG13_1024x16_c2_2P_DEC04 +XSEL<28> ADDR_N_I<3> ADDR_N_I<2> ADDR_N_I<1> ADDR_N_I<0> CS00<28> ECLK_H<28> ++ ECLK_H<29> ECLK_B<28> ECLK_B<29> WL_O<463> WL_O<462> WL_O<461> WL_O<460> ++ WL_O<459> WL_O<458> WL_O<457> WL_O<456> WL_O<455> WL_O<454> WL_O<453> ++ WL_O<452> WL_O<451> WL_O<450> WL_O<449> WL_O<448> VDD VSS / ++ RM_IHPSG13_1024x16_c2_2P_DEC04 +XSEL<27> ADDR_N_I<3> ADDR_N_I<2> ADDR_N_I<1> ADDR_N_I<0> CS00<27> ECLK_H<27> ++ ECLK_H<28> ECLK_B<27> ECLK_B<28> WL_O<447> WL_O<446> WL_O<445> WL_O<444> ++ WL_O<443> WL_O<442> WL_O<441> WL_O<440> WL_O<439> WL_O<438> WL_O<437> ++ WL_O<436> WL_O<435> WL_O<434> WL_O<433> WL_O<432> VDD VSS / ++ RM_IHPSG13_1024x16_c2_2P_DEC04 +XSEL<26> ADDR_N_I<3> ADDR_N_I<2> ADDR_N_I<1> ADDR_N_I<0> CS00<26> ECLK_H<26> ++ ECLK_H<27> ECLK_B<26> ECLK_B<27> WL_O<431> WL_O<430> WL_O<429> WL_O<428> ++ WL_O<427> WL_O<426> WL_O<425> WL_O<424> WL_O<423> WL_O<422> WL_O<421> ++ WL_O<420> WL_O<419> WL_O<418> WL_O<417> WL_O<416> VDD VSS / ++ RM_IHPSG13_1024x16_c2_2P_DEC04 +XSEL<25> ADDR_N_I<3> ADDR_N_I<2> ADDR_N_I<1> ADDR_N_I<0> CS00<25> ECLK_H<25> ++ ECLK_H<26> ECLK_B<25> ECLK_B<26> WL_O<415> WL_O<414> WL_O<413> WL_O<412> ++ WL_O<411> WL_O<410> WL_O<409> WL_O<408> WL_O<407> WL_O<406> WL_O<405> ++ WL_O<404> WL_O<403> WL_O<402> WL_O<401> WL_O<400> VDD VSS / ++ RM_IHPSG13_1024x16_c2_2P_DEC04 +XSEL<24> ADDR_N_I<3> ADDR_N_I<2> ADDR_N_I<1> ADDR_N_I<0> CS00<24> ECLK_H<24> ++ ECLK_H<25> ECLK_B<24> ECLK_B<25> WL_O<399> WL_O<398> WL_O<397> WL_O<396> ++ WL_O<395> WL_O<394> WL_O<393> WL_O<392> WL_O<391> WL_O<390> WL_O<389> ++ WL_O<388> WL_O<387> WL_O<386> WL_O<385> WL_O<384> VDD VSS / ++ RM_IHPSG13_1024x16_c2_2P_DEC04 +XSEL<23> ADDR_N_I<3> ADDR_N_I<2> ADDR_N_I<1> ADDR_N_I<0> CS00<23> ECLK_H<23> ++ ECLK_H<24> ECLK_B<23> ECLK_B<24> WL_O<383> WL_O<382> WL_O<381> WL_O<380> ++ WL_O<379> WL_O<378> WL_O<377> WL_O<376> WL_O<375> WL_O<374> WL_O<373> ++ WL_O<372> WL_O<371> WL_O<370> WL_O<369> WL_O<368> VDD VSS / ++ RM_IHPSG13_1024x16_c2_2P_DEC04 +XSEL<22> ADDR_N_I<3> ADDR_N_I<2> ADDR_N_I<1> ADDR_N_I<0> CS00<22> ECLK_H<22> ++ ECLK_H<23> ECLK_B<22> ECLK_B<23> WL_O<367> WL_O<366> WL_O<365> WL_O<364> ++ WL_O<363> WL_O<362> WL_O<361> WL_O<360> WL_O<359> WL_O<358> WL_O<357> ++ WL_O<356> WL_O<355> WL_O<354> WL_O<353> WL_O<352> VDD VSS / ++ RM_IHPSG13_1024x16_c2_2P_DEC04 +XSEL<21> ADDR_N_I<3> ADDR_N_I<2> ADDR_N_I<1> ADDR_N_I<0> CS00<21> ECLK_H<21> ++ ECLK_H<22> ECLK_B<21> ECLK_B<22> WL_O<351> WL_O<350> WL_O<349> WL_O<348> ++ WL_O<347> WL_O<346> WL_O<345> WL_O<344> WL_O<343> WL_O<342> WL_O<341> ++ WL_O<340> WL_O<339> WL_O<338> WL_O<337> WL_O<336> VDD VSS / ++ RM_IHPSG13_1024x16_c2_2P_DEC04 +XSEL<20> ADDR_N_I<3> ADDR_N_I<2> ADDR_N_I<1> ADDR_N_I<0> CS00<20> ECLK_H<20> ++ ECLK_H<21> ECLK_B<20> ECLK_B<21> WL_O<335> WL_O<334> WL_O<333> WL_O<332> ++ WL_O<331> WL_O<330> WL_O<329> WL_O<328> WL_O<327> WL_O<326> WL_O<325> ++ WL_O<324> WL_O<323> WL_O<322> WL_O<321> WL_O<320> VDD VSS / ++ RM_IHPSG13_1024x16_c2_2P_DEC04 +XSEL<19> ADDR_N_I<3> ADDR_N_I<2> ADDR_N_I<1> ADDR_N_I<0> CS00<19> ECLK_H<19> ++ ECLK_H<20> ECLK_B<19> ECLK_B<20> WL_O<319> WL_O<318> WL_O<317> WL_O<316> ++ WL_O<315> WL_O<314> WL_O<313> WL_O<312> WL_O<311> WL_O<310> WL_O<309> ++ WL_O<308> WL_O<307> WL_O<306> WL_O<305> WL_O<304> VDD VSS / ++ RM_IHPSG13_1024x16_c2_2P_DEC04 +XSEL<18> ADDR_N_I<3> ADDR_N_I<2> ADDR_N_I<1> ADDR_N_I<0> CS00<18> ECLK_H<18> ++ ECLK_H<19> ECLK_B<18> ECLK_B<19> WL_O<303> WL_O<302> WL_O<301> WL_O<300> ++ WL_O<299> WL_O<298> WL_O<297> WL_O<296> WL_O<295> WL_O<294> WL_O<293> ++ WL_O<292> WL_O<291> WL_O<290> WL_O<289> WL_O<288> VDD VSS / ++ RM_IHPSG13_1024x16_c2_2P_DEC04 +XSEL<17> ADDR_N_I<3> ADDR_N_I<2> ADDR_N_I<1> ADDR_N_I<0> CS00<17> ECLK_H<17> ++ ECLK_H<18> ECLK_B<17> ECLK_B<18> WL_O<287> WL_O<286> WL_O<285> WL_O<284> ++ WL_O<283> WL_O<282> WL_O<281> WL_O<280> WL_O<279> WL_O<278> WL_O<277> ++ WL_O<276> WL_O<275> WL_O<274> WL_O<273> WL_O<272> VDD VSS / ++ RM_IHPSG13_1024x16_c2_2P_DEC04 +XSEL<16> ADDR_N_I<3> ADDR_N_I<2> ADDR_N_I<1> ADDR_N_I<0> CS00<16> ECLK_H<16> ++ ECLK_H<17> ECLK_B<16> ECLK_B<17> WL_O<271> WL_O<270> WL_O<269> WL_O<268> ++ WL_O<267> WL_O<266> WL_O<265> WL_O<264> WL_O<263> WL_O<262> WL_O<261> ++ WL_O<260> WL_O<259> WL_O<258> WL_O<257> WL_O<256> VDD VSS / ++ RM_IHPSG13_1024x16_c2_2P_DEC04 +XSEL<15> ADDR_N_I<3> ADDR_N_I<2> ADDR_N_I<1> ADDR_N_I<0> CS00<15> ECLK_H<15> ++ ECLK_H<16> ECLK_B<15> ECLK_B<16> WL_O<255> WL_O<254> WL_O<253> WL_O<252> ++ WL_O<251> WL_O<250> WL_O<249> WL_O<248> WL_O<247> WL_O<246> WL_O<245> ++ WL_O<244> WL_O<243> WL_O<242> WL_O<241> WL_O<240> VDD VSS / ++ RM_IHPSG13_1024x16_c2_2P_DEC04 +XSEL<14> ADDR_N_I<3> ADDR_N_I<2> ADDR_N_I<1> ADDR_N_I<0> CS00<14> ECLK_H<14> ++ ECLK_H<15> ECLK_B<14> ECLK_B<15> WL_O<239> WL_O<238> WL_O<237> WL_O<236> ++ WL_O<235> WL_O<234> WL_O<233> WL_O<232> WL_O<231> WL_O<230> WL_O<229> ++ WL_O<228> WL_O<227> WL_O<226> WL_O<225> WL_O<224> VDD VSS / ++ RM_IHPSG13_1024x16_c2_2P_DEC04 +XSEL<13> ADDR_N_I<3> ADDR_N_I<2> ADDR_N_I<1> ADDR_N_I<0> CS00<13> ECLK_H<13> ++ ECLK_H<14> ECLK_B<13> ECLK_B<14> WL_O<223> WL_O<222> WL_O<221> WL_O<220> ++ WL_O<219> WL_O<218> WL_O<217> WL_O<216> WL_O<215> WL_O<214> WL_O<213> ++ WL_O<212> WL_O<211> WL_O<210> WL_O<209> WL_O<208> VDD VSS / ++ RM_IHPSG13_1024x16_c2_2P_DEC04 +XSEL<12> ADDR_N_I<3> ADDR_N_I<2> ADDR_N_I<1> ADDR_N_I<0> CS00<12> ECLK_H<12> ++ ECLK_H<13> ECLK_B<12> ECLK_B<13> WL_O<207> WL_O<206> WL_O<205> WL_O<204> ++ WL_O<203> WL_O<202> WL_O<201> WL_O<200> WL_O<199> WL_O<198> WL_O<197> ++ WL_O<196> WL_O<195> WL_O<194> WL_O<193> WL_O<192> VDD VSS / ++ RM_IHPSG13_1024x16_c2_2P_DEC04 +XSEL<11> ADDR_N_I<3> ADDR_N_I<2> ADDR_N_I<1> ADDR_N_I<0> CS00<11> ECLK_H<11> ++ ECLK_H<12> ECLK_B<11> ECLK_B<12> WL_O<191> WL_O<190> WL_O<189> WL_O<188> ++ WL_O<187> WL_O<186> WL_O<185> WL_O<184> WL_O<183> WL_O<182> WL_O<181> ++ WL_O<180> WL_O<179> WL_O<178> WL_O<177> WL_O<176> VDD VSS / ++ RM_IHPSG13_1024x16_c2_2P_DEC04 +XSEL<10> ADDR_N_I<3> ADDR_N_I<2> ADDR_N_I<1> ADDR_N_I<0> CS00<10> ECLK_H<10> ++ ECLK_H<11> ECLK_B<10> ECLK_B<11> WL_O<175> WL_O<174> WL_O<173> WL_O<172> ++ WL_O<171> WL_O<170> WL_O<169> WL_O<168> WL_O<167> WL_O<166> WL_O<165> ++ WL_O<164> WL_O<163> WL_O<162> WL_O<161> WL_O<160> VDD VSS / ++ RM_IHPSG13_1024x16_c2_2P_DEC04 +XSEL<9> ADDR_N_I<3> ADDR_N_I<2> ADDR_N_I<1> ADDR_N_I<0> CS00<9> ECLK_H<9> ++ ECLK_H<10> ECLK_B<9> ECLK_B<10> WL_O<159> WL_O<158> WL_O<157> WL_O<156> ++ WL_O<155> WL_O<154> WL_O<153> WL_O<152> WL_O<151> WL_O<150> WL_O<149> ++ WL_O<148> WL_O<147> WL_O<146> WL_O<145> WL_O<144> VDD VSS / ++ RM_IHPSG13_1024x16_c2_2P_DEC04 +XSEL<8> ADDR_N_I<3> ADDR_N_I<2> ADDR_N_I<1> ADDR_N_I<0> CS00<8> ECLK_H<8> ++ ECLK_H<9> ECLK_B<8> ECLK_B<9> WL_O<143> WL_O<142> WL_O<141> WL_O<140> ++ WL_O<139> WL_O<138> WL_O<137> WL_O<136> WL_O<135> WL_O<134> WL_O<133> ++ WL_O<132> WL_O<131> WL_O<130> WL_O<129> WL_O<128> VDD VSS / ++ RM_IHPSG13_1024x16_c2_2P_DEC04 +XSEL<7> ADDR_N_I<3> ADDR_N_I<2> ADDR_N_I<1> ADDR_N_I<0> CS00<7> ECLK_H<7> ++ ECLK_H<8> ECLK_B<7> ECLK_B<8> WL_O<127> WL_O<126> WL_O<125> WL_O<124> ++ WL_O<123> WL_O<122> WL_O<121> WL_O<120> WL_O<119> WL_O<118> WL_O<117> ++ WL_O<116> WL_O<115> WL_O<114> WL_O<113> WL_O<112> VDD VSS / ++ RM_IHPSG13_1024x16_c2_2P_DEC04 +XSEL<6> ADDR_N_I<3> ADDR_N_I<2> ADDR_N_I<1> ADDR_N_I<0> CS00<6> ECLK_H<6> ++ ECLK_H<7> ECLK_B<6> ECLK_B<7> WL_O<111> WL_O<110> WL_O<109> WL_O<108> ++ WL_O<107> WL_O<106> WL_O<105> WL_O<104> WL_O<103> WL_O<102> WL_O<101> ++ WL_O<100> WL_O<99> WL_O<98> WL_O<97> WL_O<96> VDD VSS / ++ RM_IHPSG13_1024x16_c2_2P_DEC04 +XSEL<5> ADDR_N_I<3> ADDR_N_I<2> ADDR_N_I<1> ADDR_N_I<0> CS00<5> ECLK_H<5> ++ ECLK_H<6> ECLK_B<5> ECLK_B<6> WL_O<95> WL_O<94> WL_O<93> WL_O<92> WL_O<91> ++ WL_O<90> WL_O<89> WL_O<88> WL_O<87> WL_O<86> WL_O<85> WL_O<84> WL_O<83> ++ WL_O<82> WL_O<81> WL_O<80> VDD VSS / RM_IHPSG13_1024x16_c2_2P_DEC04 +XSEL<4> ADDR_N_I<3> ADDR_N_I<2> ADDR_N_I<1> ADDR_N_I<0> CS00<4> ECLK_H<4> ++ ECLK_H<5> ECLK_B<4> ECLK_B<5> WL_O<79> WL_O<78> WL_O<77> WL_O<76> WL_O<75> ++ WL_O<74> WL_O<73> WL_O<72> WL_O<71> WL_O<70> WL_O<69> WL_O<68> WL_O<67> ++ WL_O<66> WL_O<65> WL_O<64> VDD VSS / RM_IHPSG13_1024x16_c2_2P_DEC04 +XSEL<3> ADDR_N_I<3> ADDR_N_I<2> ADDR_N_I<1> ADDR_N_I<0> CS00<3> ECLK_H<3> ++ ECLK_H<4> ECLK_B<3> ECLK_B<4> WL_O<63> WL_O<62> WL_O<61> WL_O<60> WL_O<59> ++ WL_O<58> WL_O<57> WL_O<56> WL_O<55> WL_O<54> WL_O<53> WL_O<52> WL_O<51> ++ WL_O<50> WL_O<49> WL_O<48> VDD VSS / RM_IHPSG13_1024x16_c2_2P_DEC04 +XSEL<2> ADDR_N_I<3> ADDR_N_I<2> ADDR_N_I<1> ADDR_N_I<0> CS00<2> ECLK_H<2> ++ ECLK_H<3> ECLK_B<2> ECLK_B<3> WL_O<47> WL_O<46> WL_O<45> WL_O<44> WL_O<43> ++ WL_O<42> WL_O<41> WL_O<40> WL_O<39> WL_O<38> WL_O<37> WL_O<36> WL_O<35> ++ WL_O<34> WL_O<33> WL_O<32> VDD VSS / RM_IHPSG13_1024x16_c2_2P_DEC04 +XSEL<1> ADDR_N_I<3> ADDR_N_I<2> ADDR_N_I<1> ADDR_N_I<0> CS00<1> ECLK_H<1> ++ ECLK_H<2> ECLK_B<1> ECLK_B<2> WL_O<31> WL_O<30> WL_O<29> WL_O<28> WL_O<27> ++ WL_O<26> WL_O<25> WL_O<24> WL_O<23> WL_O<22> WL_O<21> WL_O<20> WL_O<19> ++ WL_O<18> WL_O<17> WL_O<16> VDD VSS / RM_IHPSG13_1024x16_c2_2P_DEC04 +XSEL<0> ADDR_N_I<3> ADDR_N_I<2> ADDR_N_I<1> ADDR_N_I<0> CS00<0> ECLK_I ++ ECLK_H<1> ECLK_B<0> ECLK_B<1> WL_O<15> WL_O<14> WL_O<13> WL_O<12> WL_O<11> ++ WL_O<10> WL_O<9> WL_O<8> WL_O<7> WL_O<6> WL_O<5> WL_O<4> WL_O<3> WL_O<2> ++ WL_O<1> WL_O<0> VDD VSS / RM_IHPSG13_1024x16_c2_2P_DEC04 +XDEC10<9> ADDR_N_I<7> ADDR_N_I<6> CS04<1> CS02<6> VDD VSS / ++ RM_IHPSG13_1024x16_c2_2P_DEC02 +XDEC10<8> ADDR_N_I<7> ADDR_N_I<6> CS04<0> CS02<2> VDD VSS / ++ RM_IHPSG13_1024x16_c2_2P_DEC02 +XDEC10<7> ADDR_N_I<5> ADDR_N_I<4> CS02<7> CS00<30> VDD VSS / ++ RM_IHPSG13_1024x16_c2_2P_DEC02 +XDEC10<6> ADDR_N_I<5> ADDR_N_I<4> CS02<6> CS00<26> VDD VSS / ++ RM_IHPSG13_1024x16_c2_2P_DEC02 +XDEC10<5> ADDR_N_I<5> ADDR_N_I<4> CS02<5> CS00<22> VDD VSS / ++ RM_IHPSG13_1024x16_c2_2P_DEC02 +XDEC10<4> ADDR_N_I<5> ADDR_N_I<4> CS02<4> CS00<18> VDD VSS / ++ RM_IHPSG13_1024x16_c2_2P_DEC02 +XDEC10<3> ADDR_N_I<5> ADDR_N_I<4> CS02<3> CS00<14> VDD VSS / ++ RM_IHPSG13_1024x16_c2_2P_DEC02 +XDEC10<2> ADDR_N_I<5> ADDR_N_I<4> CS02<2> CS00<10> VDD VSS / ++ RM_IHPSG13_1024x16_c2_2P_DEC02 +XDEC10<1> ADDR_N_I<5> ADDR_N_I<4> CS02<1> CS00<6> VDD VSS / ++ RM_IHPSG13_1024x16_c2_2P_DEC02 +XDEC10<0> ADDR_N_I<5> ADDR_N_I<4> CS02<0> CS00<2> VDD VSS / ++ RM_IHPSG13_1024x16_c2_2P_DEC02 +XDEC01<10> ADDR_N_I<9> ADDR_N_I<8> CS_I CS04<1> VDD VSS / ++ RM_IHPSG13_1024x16_c2_2P_DEC01 +XDEC01<9> ADDR_N_I<7> ADDR_N_I<6> CS04<1> CS02<5> VDD VSS / ++ RM_IHPSG13_1024x16_c2_2P_DEC01 +XDEC01<8> ADDR_N_I<7> ADDR_N_I<6> CS04<0> CS02<1> VDD VSS / ++ RM_IHPSG13_1024x16_c2_2P_DEC01 +XDEC01<7> ADDR_N_I<5> ADDR_N_I<4> CS02<7> CS00<29> VDD VSS / ++ RM_IHPSG13_1024x16_c2_2P_DEC01 +XDEC01<6> ADDR_N_I<5> ADDR_N_I<4> CS02<6> CS00<25> VDD VSS / ++ RM_IHPSG13_1024x16_c2_2P_DEC01 +XDEC01<5> ADDR_N_I<5> ADDR_N_I<4> CS02<5> CS00<21> VDD VSS / ++ RM_IHPSG13_1024x16_c2_2P_DEC01 +XDEC01<4> ADDR_N_I<5> ADDR_N_I<4> CS02<4> CS00<17> VDD VSS / ++ RM_IHPSG13_1024x16_c2_2P_DEC01 +XDEC01<3> ADDR_N_I<5> ADDR_N_I<4> CS02<3> CS00<13> VDD VSS / ++ RM_IHPSG13_1024x16_c2_2P_DEC01 +XDEC01<2> ADDR_N_I<5> ADDR_N_I<4> CS02<2> CS00<9> VDD VSS / ++ RM_IHPSG13_1024x16_c2_2P_DEC01 +XDEC01<1> ADDR_N_I<5> ADDR_N_I<4> CS02<1> CS00<5> VDD VSS / ++ RM_IHPSG13_1024x16_c2_2P_DEC01 +XDEC01<0> ADDR_N_I<5> ADDR_N_I<4> CS02<0> CS00<1> VDD VSS / ++ RM_IHPSG13_1024x16_c2_2P_DEC01 +XL2<258> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<257> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<256> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<255> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<254> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<253> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<252> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<251> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<250> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<249> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<248> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<247> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<246> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<245> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<244> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<243> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<242> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<241> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<240> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<239> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<238> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<237> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<236> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<235> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<234> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<233> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<232> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<231> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<230> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<229> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<228> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<227> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<226> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<225> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<224> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<223> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<222> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<221> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<220> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<219> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<218> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<217> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<216> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<215> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<214> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<213> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<212> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<211> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<210> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<209> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<208> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<207> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<206> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<205> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<204> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<203> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<202> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<201> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<200> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<199> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<198> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<197> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<196> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<195> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<194> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<193> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<192> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<191> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<190> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<189> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<188> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<187> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<186> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<185> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<184> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<183> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<182> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<181> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<180> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<179> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<178> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<177> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<176> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<175> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<174> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<173> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<172> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<171> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<170> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<169> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<168> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<167> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<166> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<165> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<164> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<163> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<162> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<161> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<160> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<159> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<158> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<157> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<156> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<155> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<154> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<153> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<152> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<151> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<150> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<149> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<148> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<147> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<146> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<145> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<144> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<143> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<142> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<141> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<140> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<139> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<138> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<137> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<136> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<135> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<134> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<133> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<132> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<131> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<130> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<129> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<128> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<127> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<126> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<125> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<124> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<123> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<122> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<121> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<120> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<119> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<118> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<117> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<116> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<115> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<114> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<113> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<112> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<111> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<110> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<109> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<108> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<107> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<106> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<105> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<104> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<103> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<102> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<101> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<100> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<99> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<98> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<97> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<96> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<95> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<94> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<93> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<92> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<91> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<90> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<89> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<88> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<87> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<86> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<85> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<84> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<83> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<82> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<81> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<80> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<79> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<78> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<77> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<76> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<75> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<74> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<73> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<72> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<71> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<70> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<69> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<68> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<67> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<66> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<65> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<64> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<63> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<62> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<61> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<60> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<59> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<58> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<57> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<56> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<55> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<54> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<53> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<52> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<51> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<50> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<49> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<48> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<47> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<46> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<45> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<44> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<43> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<42> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<41> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<40> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<39> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<38> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<37> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<36> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<35> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<34> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<33> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<32> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<31> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<30> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<29> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<28> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<27> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<26> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<25> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<24> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<23> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<22> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<21> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<20> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<19> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<18> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<17> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<16> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<15> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<14> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<13> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<12> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<11> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<10> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<9> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<8> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<7> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<6> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<5> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<4> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<3> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<2> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<1> VDD VSS / RSC_IHPSG13_FILLCAP8 +XDEC00<10> ADDR_N_I<9> ADDR_N_I<8> CS_I CS04<0> VDD VSS / ++ RM_IHPSG13_1024x16_c2_2P_DEC00 +XDEC00<9> ADDR_N_I<7> ADDR_N_I<6> CS04<1> CS02<4> VDD VSS / ++ RM_IHPSG13_1024x16_c2_2P_DEC00 +XDEC00<8> ADDR_N_I<7> ADDR_N_I<6> CS04<0> CS02<0> VDD VSS / ++ RM_IHPSG13_1024x16_c2_2P_DEC00 +XDEC00<7> ADDR_N_I<5> ADDR_N_I<4> CS02<7> CS00<28> VDD VSS / ++ RM_IHPSG13_1024x16_c2_2P_DEC00 +XDEC00<6> ADDR_N_I<5> ADDR_N_I<4> CS02<6> CS00<24> VDD VSS / ++ RM_IHPSG13_1024x16_c2_2P_DEC00 +XDEC00<5> ADDR_N_I<5> ADDR_N_I<4> CS02<5> CS00<20> VDD VSS / ++ RM_IHPSG13_1024x16_c2_2P_DEC00 +XDEC00<4> ADDR_N_I<5> ADDR_N_I<4> CS02<4> CS00<16> VDD VSS / ++ RM_IHPSG13_1024x16_c2_2P_DEC00 +XDEC00<3> ADDR_N_I<5> ADDR_N_I<4> CS02<3> CS00<12> VDD VSS / ++ RM_IHPSG13_1024x16_c2_2P_DEC00 +XDEC00<2> ADDR_N_I<5> ADDR_N_I<4> CS02<2> CS00<8> VDD VSS / ++ RM_IHPSG13_1024x16_c2_2P_DEC00 +XDEC00<1> ADDR_N_I<5> ADDR_N_I<4> CS02<1> CS00<4> VDD VSS / ++ RM_IHPSG13_1024x16_c2_2P_DEC00 +XDEC00<0> ADDR_N_I<5> ADDR_N_I<4> CS02<0> CS00<0> VDD VSS / ++ RM_IHPSG13_1024x16_c2_2P_DEC00 +XDEC11<9> ADDR_N_I<7> ADDR_N_I<6> CS04<1> CS02<7> VDD VSS / ++ RM_IHPSG13_1024x16_c2_2P_DEC03 +XDEC11<8> ADDR_N_I<7> ADDR_N_I<6> CS04<0> CS02<3> VDD VSS / ++ RM_IHPSG13_1024x16_c2_2P_DEC03 +XDEC11<7> ADDR_N_I<5> ADDR_N_I<4> CS02<7> CS00<31> VDD VSS / ++ RM_IHPSG13_1024x16_c2_2P_DEC03 +XDEC11<6> ADDR_N_I<5> ADDR_N_I<4> CS02<6> CS00<27> VDD VSS / ++ RM_IHPSG13_1024x16_c2_2P_DEC03 +XDEC11<5> ADDR_N_I<5> ADDR_N_I<4> CS02<5> CS00<23> VDD VSS / ++ RM_IHPSG13_1024x16_c2_2P_DEC03 +XDEC11<4> ADDR_N_I<5> ADDR_N_I<4> CS02<4> CS00<19> VDD VSS / ++ RM_IHPSG13_1024x16_c2_2P_DEC03 +XDEC11<3> ADDR_N_I<5> ADDR_N_I<4> CS02<3> CS00<15> VDD VSS / ++ RM_IHPSG13_1024x16_c2_2P_DEC03 +XDEC11<2> ADDR_N_I<5> ADDR_N_I<4> CS02<2> CS00<11> VDD VSS / ++ RM_IHPSG13_1024x16_c2_2P_DEC03 +XDEC11<1> ADDR_N_I<5> ADDR_N_I<4> CS02<1> CS00<7> VDD VSS / ++ RM_IHPSG13_1024x16_c2_2P_DEC03 +XDEC11<0> ADDR_N_I<5> ADDR_N_I<4> CS02<0> CS00<3> VDD VSS / ++ RM_IHPSG13_1024x16_c2_2P_DEC03 +XI0 ADDR_N_I<9> VDD VSS / RSC_IHPSG13_TIEL +.ENDS +.SUBCKT RM_IHPSG13_1024x16_c2_2P_ROWREG9 ACLK_N_I ADDR_I<8> ADDR_I<7> ADDR_I<6> ADDR_I<5> ++ ADDR_I<4> ADDR_I<3> ADDR_I<2> ADDR_I<1> ADDR_I<0> ADDR_N_O<8> ADDR_N_O<7> ++ ADDR_N_O<6> ADDR_N_O<5> ADDR_N_O<4> ADDR_N_O<3> ADDR_N_O<2> ADDR_N_O<1> ++ ADDR_N_O<0> BIST_ADDR_I<8> BIST_ADDR_I<7> BIST_ADDR_I<6> BIST_ADDR_I<5> ++ BIST_ADDR_I<4> BIST_ADDR_I<3> BIST_ADDR_I<2> BIST_ADDR_I<1> BIST_ADDR_I<0> ++ BIST_EN_I VDD VSS +XDFF<8> BIST_EN_I BIST_ADDR_I<8> ACLK_N_I ADDR_I<8> q_int<8> net04<0> VDD ++ VSS / RSC_IHPSG13_DFNQMX2IX1 +XDFF<7> BIST_EN_I BIST_ADDR_I<7> ACLK_N_I ADDR_I<7> q_int<7> net04<1> VDD ++ VSS / RSC_IHPSG13_DFNQMX2IX1 +XDFF<6> BIST_EN_I BIST_ADDR_I<6> ACLK_N_I ADDR_I<6> q_int<6> net04<2> VDD ++ VSS / RSC_IHPSG13_DFNQMX2IX1 +XDFF<5> BIST_EN_I BIST_ADDR_I<5> ACLK_N_I ADDR_I<5> q_int<5> net04<3> VDD ++ VSS / RSC_IHPSG13_DFNQMX2IX1 +XDFF<4> BIST_EN_I BIST_ADDR_I<4> ACLK_N_I ADDR_I<4> q_int<4> net04<4> VDD ++ VSS / RSC_IHPSG13_DFNQMX2IX1 +XDFF<3> BIST_EN_I BIST_ADDR_I<3> ACLK_N_I ADDR_I<3> q_int<3> net04<5> VDD ++ VSS / RSC_IHPSG13_DFNQMX2IX1 +XDFF<2> BIST_EN_I BIST_ADDR_I<2> ACLK_N_I ADDR_I<2> q_int<2> net04<6> VDD ++ VSS / RSC_IHPSG13_DFNQMX2IX1 +XDFF<1> BIST_EN_I BIST_ADDR_I<1> ACLK_N_I ADDR_I<1> q_int<1> net04<7> VDD ++ VSS / RSC_IHPSG13_DFNQMX2IX1 +XDFF<0> BIST_EN_I BIST_ADDR_I<0> ACLK_N_I ADDR_I<0> q_int<0> net04<8> VDD ++ VSS / RSC_IHPSG13_DFNQMX2IX1 +XDRV<8> qn_int<8> ADDR_N_O<8> VDD VSS / RSC_IHPSG13_CINVX8 +XDRV<7> qn_int<7> ADDR_N_O<7> VDD VSS / RSC_IHPSG13_CINVX8 +XDRV<6> qn_int<6> ADDR_N_O<6> VDD VSS / RSC_IHPSG13_CINVX8 +XDRV<5> qn_int<5> ADDR_N_O<5> VDD VSS / RSC_IHPSG13_CINVX8 +XDRV<4> qn_int<4> ADDR_N_O<4> VDD VSS / RSC_IHPSG13_CINVX8 +XDRV<3> qn_int<3> ADDR_N_O<3> VDD VSS / RSC_IHPSG13_CINVX8 +XDRV<2> qn_int<2> ADDR_N_O<2> VDD VSS / RSC_IHPSG13_CINVX8 +XDRV<1> qn_int<1> ADDR_N_O<1> VDD VSS / RSC_IHPSG13_CINVX8 +XDRV<0> qn_int<0> ADDR_N_O<0> VDD VSS / RSC_IHPSG13_CINVX8 +XINV<8> q_int<8> qn_int<8> VDD VSS / RSC_IHPSG13_CINVX2 +XINV<7> q_int<7> qn_int<7> VDD VSS / RSC_IHPSG13_CINVX2 +XINV<6> q_int<6> qn_int<6> VDD VSS / RSC_IHPSG13_CINVX2 +XINV<5> q_int<5> qn_int<5> VDD VSS / RSC_IHPSG13_CINVX2 +XINV<4> q_int<4> qn_int<4> VDD VSS / RSC_IHPSG13_CINVX2 +XINV<3> q_int<3> qn_int<3> VDD VSS / RSC_IHPSG13_CINVX2 +XINV<2> q_int<2> qn_int<2> VDD VSS / RSC_IHPSG13_CINVX2 +XINV<1> q_int<1> qn_int<1> VDD VSS / RSC_IHPSG13_CINVX2 +XINV<0> q_int<0> qn_int<0> VDD VSS / RSC_IHPSG13_CINVX2 +.ENDS + +.SUBCKT RM_IHPSG13_1024x16_c2_2P_DLY_MUX A SEL Z VDD VSS +XI11 net4 Z VDD VSS / RSC_IHPSG13_CINVX2 +XI8 A D<3> SEL net4 VDD VSS / RSC_IHPSG13_MX2IX1 +XI20<3> D<2> D<3> VDD VSS / RSC_IHPSG13_CDLYX1 +XI20<2> D<1> D<2> VDD VSS / RSC_IHPSG13_CDLYX1 +XI20<1> A D<1> VDD VSS / RSC_IHPSG13_CDLYX1 +.ENDS +.SUBCKT RM_IHPSG13_1024x16_c2_2P_CTRL ACLK_N BIST_CK_I BIST_CS_I BIST_EN BIST_RE_I ++ BIST_WE_I B_TIEL_O CK_I CS_I DCLK ECLK PULSE_H PULSE_L PULSE_O RCLK RE_I ++ ROW_CS WCLK WE_I VDD VSS +XI17 ck_regs we col_we VDD VSS / RSC_IHPSG13_DFNQX2 +XI16 ck_regs re col_re VDD VSS / RSC_IHPSG13_DFNQX2 +XI18 ck_regs cs net7 VDD VSS / RSC_IHPSG13_DFNQX2 +XI71 ACLK_N net012 PULSE_O VDD VSS / RSC_IHPSG13_DFNQX2 +XI77 col_we net017 net016 VDD VSS / RSC_IHPSG13_CNAND2X2 +XI76 col_re net017 net018 VDD VSS / RSC_IHPSG13_CNAND2X2 +XI15 ck_dly WEorREandCS aclk VDD VSS / RSC_IHPSG13_CGATEPX4 +XI14 ck WEandCS DCLK VDD VSS / RSC_IHPSG13_CGATEPX4 +XI60 net7 ROW_CS VDD VSS / RSC_IHPSG13_CBUFX8 +XI73 PULSE_O net012 VDD VSS / RSC_IHPSG13_CINVX2 +XI8 net017 net8 VDD VSS / RSC_IHPSG13_CINVX2 +XCAPS4<7> VDD VSS / RSC_IHPSG13_FILLCAP4 +XCAPS4<6> VDD VSS / RSC_IHPSG13_FILLCAP4 +XCAPS4<5> VDD VSS / RSC_IHPSG13_FILLCAP4 +XCAPS4<4> VDD VSS / RSC_IHPSG13_FILLCAP4 +XCAPS4<3> VDD VSS / RSC_IHPSG13_FILLCAP4 +XCAPS4<2> VDD VSS / RSC_IHPSG13_FILLCAP4 +XCAPS4<1> VDD VSS / RSC_IHPSG13_FILLCAP4 +XBM_TIEL B_TIEL_O VDD VSS / RSC_IHPSG13_TIEL +XI64 ck ck_dly VDD VSS / RSC_IHPSG13_CDLYX2 +XI86 CS_I BIST_CS_I BIST_EN cs VDD VSS / RSC_IHPSG13_MX2X2 +XI87 CK_I BIST_CK_I BIST_EN ck VDD VSS / RSC_IHPSG13_MX2X2 +XI85 WE_I BIST_WE_I BIST_EN we VDD VSS / RSC_IHPSG13_MX2X2 +XI84 RE_I BIST_RE_I BIST_EN re VDD VSS / RSC_IHPSG13_MX2X2 +XI48 ck_dly ck_regs VDD VSS / RSC_IHPSG13_CINVX4 +XI81 net016 WCLK VDD VSS / RSC_IHPSG13_CINVX4 +XI80 net018 RCLK VDD VSS / RSC_IHPSG13_CINVX4 +XI78 net8 net020 VDD VSS / RSC_IHPSG13_CINVX4 +XCAPS8<7> VDD VSS / RSC_IHPSG13_FILLCAP8 +XCAPS8<6> VDD VSS / RSC_IHPSG13_FILLCAP8 +XCAPS8<5> VDD VSS / RSC_IHPSG13_FILLCAP8 +XCAPS8<4> VDD VSS / RSC_IHPSG13_FILLCAP8 +XCAPS8<3> VDD VSS / RSC_IHPSG13_FILLCAP8 +XCAPS8<2> VDD VSS / RSC_IHPSG13_FILLCAP8 +XCAPS8<1> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI6 PULSE_L PULSE_H net017 VDD VSS / RSC_IHPSG13_XOR2X2 +XI22 we cs WEandCS VDD VSS / RSC_IHPSG13_AND2X2 +XI79 net020 ECLK VDD VSS / RSC_IHPSG13_CINVX8 +XI63 aclk ACLK_N VDD VSS / RSC_IHPSG13_CINVX8 +XI21 re we cs WEorREandCS VDD VSS / RSC_IHPSG13_OA12X1 +.ENDS +.SUBCKT RM_IHPSG13_1024x16_c2_2P_COLDEC5 ACLK_N ADDR<4> ADDR<3> ADDR<2> ADDR<1> ADDR<0> ++ ADDR_COL<1> ADDR_COL<0> ADDR_DEC<7> ADDR_DEC<6> ADDR_DEC<5> ADDR_DEC<4> ++ ADDR_DEC<3> ADDR_DEC<2> ADDR_DEC<1> ADDR_DEC<0> BIST_ADDR<4> BIST_ADDR<3> ++ BIST_ADDR<2> BIST_ADDR<1> BIST_ADDR<0> BIST_EN_I VDD VSS +XI17<4> VDD VSS / RSC_IHPSG13_FILLCAP4 +XI17<3> VDD VSS / RSC_IHPSG13_FILLCAP4 +XI17<2> VDD VSS / RSC_IHPSG13_FILLCAP4 +XI17<1> VDD VSS / RSC_IHPSG13_FILLCAP4 +XI1<7> PADR<0> PADR<1> PADR<2> addr_n<7> VDD VSS / RSC_IHPSG13_NAND3X2 +XI1<6> NADR<0> PADR<1> PADR<2> addr_n<6> VDD VSS / RSC_IHPSG13_NAND3X2 +XI1<5> PADR<0> NADR<1> PADR<2> addr_n<5> VDD VSS / RSC_IHPSG13_NAND3X2 +XI1<4> NADR<0> NADR<1> PADR<2> addr_n<4> VDD VSS / RSC_IHPSG13_NAND3X2 +XI1<3> PADR<0> PADR<1> NADR<2> addr_n<3> VDD VSS / RSC_IHPSG13_NAND3X2 +XI1<2> NADR<0> PADR<1> NADR<2> addr_n<2> VDD VSS / RSC_IHPSG13_NAND3X2 +XI1<1> PADR<0> NADR<1> NADR<2> addr_n<1> VDD VSS / RSC_IHPSG13_NAND3X2 +XI1<0> NADR<0> NADR<1> NADR<2> addr_n<0> VDD VSS / RSC_IHPSG13_NAND3X2 +XDFF<4> BIST_EN_I BIST_ADDR<4> ACLK_N ADDR<4> addr_int<1> net13<0> VDD ++ VSS / RSC_IHPSG13_DFNQMX2IX1 +XDFF<3> BIST_EN_I BIST_ADDR<3> ACLK_N ADDR<3> addr_int<0> net13<1> VDD ++ VSS / RSC_IHPSG13_DFNQMX2IX1 +XDFF<2> BIST_EN_I BIST_ADDR<2> ACLK_N ADDR<2> padr_int<2> net13<2> VDD ++ VSS / RSC_IHPSG13_DFNQMX2IX1 +XDFF<1> BIST_EN_I BIST_ADDR<1> ACLK_N ADDR<1> padr_int<1> net13<3> VDD ++ VSS / RSC_IHPSG13_DFNQMX2IX1 +XDFF<0> BIST_EN_I BIST_ADDR<0> ACLK_N ADDR<0> padr_int<0> net13<4> VDD ++ VSS / RSC_IHPSG13_DFNQMX2IX1 +XI3<2> padr_int<2> NADR<2> VDD VSS / RSC_IHPSG13_INVX2 +XI3<1> padr_int<1> NADR<1> VDD VSS / RSC_IHPSG13_INVX2 +XI3<0> padr_int<0> NADR<0> VDD VSS / RSC_IHPSG13_INVX2 +XI2<7> addr_n<7> ADDR_DEC<7> VDD VSS / RSC_IHPSG13_INVX2 +XI2<6> addr_n<6> ADDR_DEC<6> VDD VSS / RSC_IHPSG13_INVX2 +XI2<5> addr_n<5> ADDR_DEC<5> VDD VSS / RSC_IHPSG13_INVX2 +XI2<4> addr_n<4> ADDR_DEC<4> VDD VSS / RSC_IHPSG13_INVX2 +XI2<3> addr_n<3> ADDR_DEC<3> VDD VSS / RSC_IHPSG13_INVX2 +XI2<2> addr_n<2> ADDR_DEC<2> VDD VSS / RSC_IHPSG13_INVX2 +XI2<1> addr_n<1> ADDR_DEC<1> VDD VSS / RSC_IHPSG13_INVX2 +XI2<0> addr_n<0> ADDR_DEC<0> VDD VSS / RSC_IHPSG13_INVX2 +XI15<2> NADR<2> PADR<2> VDD VSS / RSC_IHPSG13_INVX2 +XI15<1> NADR<1> PADR<1> VDD VSS / RSC_IHPSG13_INVX2 +XI15<0> NADR<0> PADR<0> VDD VSS / RSC_IHPSG13_INVX2 +XI13<1> addr_int<1> ADDR_COL<1> VDD VSS / RSC_IHPSG13_CBUFX2 +XI13<0> addr_int<0> ADDR_COL<0> VDD VSS / RSC_IHPSG13_CBUFX2 +XI14<5> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI14<4> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI14<3> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI14<2> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI14<1> VDD VSS / RSC_IHPSG13_FILLCAP8 +.ENDS +.SUBCKT RM_IHPSG13_1024x16_c2_2P_BLDRV A_BLC<3> A_BLC<2> A_BLC<1> A_BLC<0> A_BLC_SEL ++ A_BLT<3> A_BLT<2> A_BLT<1> A_BLT<0> A_BLT_SEL A_PRE_N A_SEL_P<3> A_SEL_P<2> ++ A_SEL_P<1> A_SEL_P<0> A_WR_ONE A_WR_ZERO B_BLC<3> B_BLC<2> B_BLC<1> B_BLC<0> ++ B_BLC_SEL B_BLT<3> B_BLT<2> B_BLT<1> B_BLT<0> B_BLT_SEL B_PRE_N B_SEL_P<3> ++ B_SEL_P<2> B_SEL_P<1> B_SEL_P<0> B_WR_ONE B_WR_ZERO VDD VSS +MA_CWN<3> A_BLC<3> A_BLC_NMOS_DRIVE<3> VSS VSS sg13_lv_nmos m=1 ++ w=4.82u l=130.00n ng=2 nrd=0 nrs=0 +MA_CWN<2> A_BLC<2> A_BLC_NMOS_DRIVE<2> VSS VSS sg13_lv_nmos m=1 ++ w=4.82u l=130.00n ng=2 nrd=0 nrs=0 +MA_CWN<1> A_BLC<1> A_BLC_NMOS_DRIVE<1> VSS VSS sg13_lv_nmos m=1 ++ w=4.82u l=130.00n ng=2 nrd=0 nrs=0 +MA_CWN<0> A_BLC<0> A_BLC_NMOS_DRIVE<0> VSS VSS sg13_lv_nmos m=1 ++ w=4.82u l=130.00n ng=2 nrd=0 nrs=0 +MA_TWN<3> A_BLT<3> A_BLT_NMOS_DRIVE<3> VSS VSS sg13_lv_nmos m=1 ++ w=4.82u l=130.00n ng=2 nrd=0 nrs=0 +MA_TWN<2> A_BLT<2> A_BLT_NMOS_DRIVE<2> VSS VSS sg13_lv_nmos m=1 ++ w=4.82u l=130.00n ng=2 nrd=0 nrs=0 +MA_TWN<1> A_BLT<1> A_BLT_NMOS_DRIVE<1> VSS VSS sg13_lv_nmos m=1 ++ w=4.82u l=130.00n ng=2 nrd=0 nrs=0 +MA_TWN<0> A_BLT<0> A_BLT_NMOS_DRIVE<0> VSS VSS sg13_lv_nmos m=1 ++ w=4.82u l=130.00n ng=2 nrd=0 nrs=0 +MB_TWN<3> B_BLT<3> B_BLT_NMOS_DRIVE<3> VSS VSS sg13_lv_nmos m=1 ++ w=4.82u l=130.00n ng=2 nrd=0 nrs=0 +MB_TWN<2> B_BLT<2> B_BLT_NMOS_DRIVE<2> VSS VSS sg13_lv_nmos m=1 ++ w=4.82u l=130.00n ng=2 nrd=0 nrs=0 +MB_TWN<1> B_BLT<1> B_BLT_NMOS_DRIVE<1> VSS VSS sg13_lv_nmos m=1 ++ w=4.82u l=130.00n ng=2 nrd=0 nrs=0 +MB_TWN<0> B_BLT<0> B_BLT_NMOS_DRIVE<0> VSS VSS sg13_lv_nmos m=1 ++ w=4.82u l=130.00n ng=2 nrd=0 nrs=0 +MB_CWN<3> B_BLC<3> B_BLC_NMOS_DRIVE<3> VSS VSS sg13_lv_nmos m=1 ++ w=4.82u l=130.00n ng=2 nrd=0 nrs=0 +MB_CWN<2> B_BLC<2> B_BLC_NMOS_DRIVE<2> VSS VSS sg13_lv_nmos m=1 ++ w=4.82u l=130.00n ng=2 nrd=0 nrs=0 +MB_CWN<1> B_BLC<1> B_BLC_NMOS_DRIVE<1> VSS VSS sg13_lv_nmos m=1 ++ w=4.82u l=130.00n ng=2 nrd=0 nrs=0 +MB_CWN<0> B_BLC<0> B_BLC_NMOS_DRIVE<0> VSS VSS sg13_lv_nmos m=1 ++ w=4.82u l=130.00n ng=2 nrd=0 nrs=0 +MA_CPR<3> A_BLC<3> A_PRE_N VDD VDD sg13_lv_pmos m=1 w=3.000u l=130.00n ++ ng=2 nrd=0 nrs=0 +MA_CPR<2> A_BLC<2> A_PRE_N VDD VDD sg13_lv_pmos m=1 w=3.000u l=130.00n ++ ng=2 nrd=0 nrs=0 +MA_CPR<1> A_BLC<1> A_PRE_N VDD VDD sg13_lv_pmos m=1 w=3.000u l=130.00n ++ ng=2 nrd=0 nrs=0 +MA_CPR<0> A_BLC<0> A_PRE_N VDD VDD sg13_lv_pmos m=1 w=3.000u l=130.00n ++ ng=2 nrd=0 nrs=0 +MA_TWP<3> A_BLT<3> A_BLT_PMOS_DRIVE<3> VDD VDD sg13_lv_pmos m=1 w=1.5u ++ l=130.00n ng=1 nrd=0 nrs=0 +MA_TWP<2> A_BLT<2> A_BLT_PMOS_DRIVE<2> VDD VDD sg13_lv_pmos m=1 w=1.5u ++ l=130.00n ng=1 nrd=0 nrs=0 +MA_TWP<1> A_BLT<1> A_BLT_PMOS_DRIVE<1> VDD VDD sg13_lv_pmos m=1 w=1.5u ++ l=130.00n ng=1 nrd=0 nrs=0 +MA_TWP<0> A_BLT<0> A_BLT_PMOS_DRIVE<0> VDD VDD sg13_lv_pmos m=1 w=1.5u ++ l=130.00n ng=1 nrd=0 nrs=0 +MA_CWP<3> A_BLC<3> A_BLC_PMOS_DRIVE<3> VDD VDD sg13_lv_pmos m=1 w=1.5u ++ l=130.00n ng=1 nrd=0 nrs=0 +MA_CWP<2> A_BLC<2> A_BLC_PMOS_DRIVE<2> VDD VDD sg13_lv_pmos m=1 w=1.5u ++ l=130.00n ng=1 nrd=0 nrs=0 +MA_CWP<1> A_BLC<1> A_BLC_PMOS_DRIVE<1> VDD VDD sg13_lv_pmos m=1 w=1.5u ++ l=130.00n ng=1 nrd=0 nrs=0 +MA_CWP<0> A_BLC<0> A_BLC_PMOS_DRIVE<0> VDD VDD sg13_lv_pmos m=1 w=1.5u ++ l=130.00n ng=1 nrd=0 nrs=0 +MA_TPR<3> A_BLT<3> A_PRE_N VDD VDD sg13_lv_pmos m=1 w=3.000u l=130.00n ++ ng=2 nrd=0 nrs=0 +MA_TPR<2> A_BLT<2> A_PRE_N VDD VDD sg13_lv_pmos m=1 w=3.000u l=130.00n ++ ng=2 nrd=0 nrs=0 +MA_TPR<1> A_BLT<1> A_PRE_N VDD VDD sg13_lv_pmos m=1 w=3.000u l=130.00n ++ ng=2 nrd=0 nrs=0 +MA_TPR<0> A_BLT<0> A_PRE_N VDD VDD sg13_lv_pmos m=1 w=3.000u l=130.00n ++ ng=2 nrd=0 nrs=0 +MA_TSP<3> A_BLT_SEL A_SEL_N<3> A_BLT<3> VDD sg13_lv_pmos m=1 w=1.5u ++ l=130.00n ng=1 nrd=0 nrs=0 +MA_TSP<2> A_BLT_SEL A_SEL_N<2> A_BLT<2> VDD sg13_lv_pmos m=1 w=1.5u ++ l=130.00n ng=1 nrd=0 nrs=0 +MA_TSP<1> A_BLT_SEL A_SEL_N<1> A_BLT<1> VDD sg13_lv_pmos m=1 w=1.5u ++ l=130.00n ng=1 nrd=0 nrs=0 +MA_TSP<0> A_BLT_SEL A_SEL_N<0> A_BLT<0> VDD sg13_lv_pmos m=1 w=1.5u ++ l=130.00n ng=1 nrd=0 nrs=0 +MA_CSP<3> A_BLC_SEL A_SEL_N<3> A_BLC<3> VDD sg13_lv_pmos m=1 w=1.5u ++ l=130.00n ng=1 nrd=0 nrs=0 +MA_CSP<2> A_BLC_SEL A_SEL_N<2> A_BLC<2> VDD sg13_lv_pmos m=1 w=1.5u ++ l=130.00n ng=1 nrd=0 nrs=0 +MA_CSP<1> A_BLC_SEL A_SEL_N<1> A_BLC<1> VDD sg13_lv_pmos m=1 w=1.5u ++ l=130.00n ng=1 nrd=0 nrs=0 +MA_CSP<0> A_BLC_SEL A_SEL_N<0> A_BLC<0> VDD sg13_lv_pmos m=1 w=1.5u ++ l=130.00n ng=1 nrd=0 nrs=0 +MB_CWP<3> B_BLC<3> B_BLC_PMOS_DRIVE<3> VDD VDD sg13_lv_pmos m=1 w=1.5u ++ l=130.00n ng=1 nrd=0 nrs=0 +MB_CWP<2> B_BLC<2> B_BLC_PMOS_DRIVE<2> VDD VDD sg13_lv_pmos m=1 w=1.5u ++ l=130.00n ng=1 nrd=0 nrs=0 +MB_CWP<1> B_BLC<1> B_BLC_PMOS_DRIVE<1> VDD VDD sg13_lv_pmos m=1 w=1.5u ++ l=130.00n ng=1 nrd=0 nrs=0 +MB_CWP<0> B_BLC<0> B_BLC_PMOS_DRIVE<0> VDD VDD sg13_lv_pmos m=1 w=1.5u ++ l=130.00n ng=1 nrd=0 nrs=0 +MB_TWP<3> B_BLT<3> B_BLT_PMOS_DRIVE<3> VDD VDD sg13_lv_pmos m=1 w=1.5u ++ l=130.00n ng=1 nrd=0 nrs=0 +MB_TWP<2> B_BLT<2> B_BLT_PMOS_DRIVE<2> VDD VDD sg13_lv_pmos m=1 w=1.5u ++ l=130.00n ng=1 nrd=0 nrs=0 +MB_TWP<1> B_BLT<1> B_BLT_PMOS_DRIVE<1> VDD VDD sg13_lv_pmos m=1 w=1.5u ++ l=130.00n ng=1 nrd=0 nrs=0 +MB_TWP<0> B_BLT<0> B_BLT_PMOS_DRIVE<0> VDD VDD sg13_lv_pmos m=1 w=1.5u ++ l=130.00n ng=1 nrd=0 nrs=0 +MB_TSP<3> B_BLT_SEL B_SEL_N<3> B_BLT<3> VDD sg13_lv_pmos m=1 w=1.5u ++ l=130.00n ng=1 nrd=0 nrs=0 +MB_TSP<2> B_BLT_SEL B_SEL_N<2> B_BLT<2> VDD sg13_lv_pmos m=1 w=1.5u ++ l=130.00n ng=1 nrd=0 nrs=0 +MB_TSP<1> B_BLT_SEL B_SEL_N<1> B_BLT<1> VDD sg13_lv_pmos m=1 w=1.5u ++ l=130.00n ng=1 nrd=0 nrs=0 +MB_TSP<0> B_BLT_SEL B_SEL_N<0> B_BLT<0> VDD sg13_lv_pmos m=1 w=1.5u ++ l=130.00n ng=1 nrd=0 nrs=0 +MB_TPR<3> B_BLT<3> B_PRE_N VDD VDD sg13_lv_pmos m=1 w=3.000u l=130.00n ++ ng=2 nrd=0 nrs=0 +MB_TPR<2> B_BLT<2> B_PRE_N VDD VDD sg13_lv_pmos m=1 w=3.000u l=130.00n ++ ng=2 nrd=0 nrs=0 +MB_TPR<1> B_BLT<1> B_PRE_N VDD VDD sg13_lv_pmos m=1 w=3.000u l=130.00n ++ ng=2 nrd=0 nrs=0 +MB_TPR<0> B_BLT<0> B_PRE_N VDD VDD sg13_lv_pmos m=1 w=3.000u l=130.00n ++ ng=2 nrd=0 nrs=0 +MB_CSP<3> B_BLC_SEL B_SEL_N<3> B_BLC<3> VDD sg13_lv_pmos m=1 w=1.5u ++ l=130.00n ng=1 nrd=0 nrs=0 +MB_CSP<2> B_BLC_SEL B_SEL_N<2> B_BLC<2> VDD sg13_lv_pmos m=1 w=1.5u ++ l=130.00n ng=1 nrd=0 nrs=0 +MB_CSP<1> B_BLC_SEL B_SEL_N<1> B_BLC<1> VDD sg13_lv_pmos m=1 w=1.5u ++ l=130.00n ng=1 nrd=0 nrs=0 +MB_CSP<0> B_BLC_SEL B_SEL_N<0> B_BLC<0> VDD sg13_lv_pmos m=1 w=1.5u ++ l=130.00n ng=1 nrd=0 nrs=0 +MB_CPR<3> B_BLC<3> B_PRE_N VDD VDD sg13_lv_pmos m=1 w=3.000u l=130.00n ++ ng=2 nrd=0 nrs=0 +MB_CPR<2> B_BLC<2> B_PRE_N VDD VDD sg13_lv_pmos m=1 w=3.000u l=130.00n ++ ng=2 nrd=0 nrs=0 +MB_CPR<1> B_BLC<1> B_PRE_N VDD VDD sg13_lv_pmos m=1 w=3.000u l=130.00n ++ ng=2 nrd=0 nrs=0 +MB_CPR<0> B_BLC<0> B_PRE_N VDD VDD sg13_lv_pmos m=1 w=3.000u l=130.00n ++ ng=2 nrd=0 nrs=0 +XA_SEL<3> A_SEL_P<3> A_SEL_N<3> VDD VSS / RSC_IHPSG13_INVX2 +XA_SEL<2> A_SEL_P<2> A_SEL_N<2> VDD VSS / RSC_IHPSG13_INVX2 +XA_SEL<1> A_SEL_P<1> A_SEL_N<1> VDD VSS / RSC_IHPSG13_INVX2 +XA_SEL<0> A_SEL_P<0> A_SEL_N<0> VDD VSS / RSC_IHPSG13_INVX2 +XA_CINV<3> A_BLT_PMOS_DRIVE<3> A_BLC_NMOS_DRIVE<3> VDD VSS / ++ RSC_IHPSG13_INVX2 +XA_CINV<2> A_BLT_PMOS_DRIVE<2> A_BLC_NMOS_DRIVE<2> VDD VSS / ++ RSC_IHPSG13_INVX2 +XA_CINV<1> A_BLT_PMOS_DRIVE<1> A_BLC_NMOS_DRIVE<1> VDD VSS / ++ RSC_IHPSG13_INVX2 +XA_CINV<0> A_BLT_PMOS_DRIVE<0> A_BLC_NMOS_DRIVE<0> VDD VSS / ++ RSC_IHPSG13_INVX2 +XA_TINV<3> A_BLC_PMOS_DRIVE<3> A_BLT_NMOS_DRIVE<3> VDD VSS / ++ RSC_IHPSG13_INVX2 +XA_TINV<2> A_BLC_PMOS_DRIVE<2> A_BLT_NMOS_DRIVE<2> VDD VSS / ++ RSC_IHPSG13_INVX2 +XA_TINV<1> A_BLC_PMOS_DRIVE<1> A_BLT_NMOS_DRIVE<1> VDD VSS / ++ RSC_IHPSG13_INVX2 +XA_TINV<0> A_BLC_PMOS_DRIVE<0> A_BLT_NMOS_DRIVE<0> VDD VSS / ++ RSC_IHPSG13_INVX2 +XB_SEL<3> B_SEL_P<3> B_SEL_N<3> VDD VSS / RSC_IHPSG13_INVX2 +XB_SEL<2> B_SEL_P<2> B_SEL_N<2> VDD VSS / RSC_IHPSG13_INVX2 +XB_SEL<1> B_SEL_P<1> B_SEL_N<1> VDD VSS / RSC_IHPSG13_INVX2 +XB_SEL<0> B_SEL_P<0> B_SEL_N<0> VDD VSS / RSC_IHPSG13_INVX2 +XB_TINV<3> B_BLC_PMOS_DRIVE<3> B_BLT_NMOS_DRIVE<3> VDD VSS / ++ RSC_IHPSG13_INVX2 +XB_TINV<2> B_BLC_PMOS_DRIVE<2> B_BLT_NMOS_DRIVE<2> VDD VSS / ++ RSC_IHPSG13_INVX2 +XB_TINV<1> B_BLC_PMOS_DRIVE<1> B_BLT_NMOS_DRIVE<1> VDD VSS / ++ RSC_IHPSG13_INVX2 +XB_TINV<0> B_BLC_PMOS_DRIVE<0> B_BLT_NMOS_DRIVE<0> VDD VSS / ++ RSC_IHPSG13_INVX2 +XB_CINV<3> B_BLT_PMOS_DRIVE<3> B_BLC_NMOS_DRIVE<3> VDD VSS / ++ RSC_IHPSG13_INVX2 +XB_CINV<2> B_BLT_PMOS_DRIVE<2> B_BLC_NMOS_DRIVE<2> VDD VSS / ++ RSC_IHPSG13_INVX2 +XB_CINV<1> B_BLT_PMOS_DRIVE<1> B_BLC_NMOS_DRIVE<1> VDD VSS / ++ RSC_IHPSG13_INVX2 +XB_CINV<0> B_BLT_PMOS_DRIVE<0> B_BLC_NMOS_DRIVE<0> VDD VSS / ++ RSC_IHPSG13_INVX2 +XA_TDEC<3> A_SEL_P<3> A_WR_ONE A_BLT_PMOS_DRIVE<3> VDD VSS / ++ RSC_IHPSG13_NAND2X2 +XA_TDEC<2> A_SEL_P<2> A_WR_ONE A_BLT_PMOS_DRIVE<2> VDD VSS / ++ RSC_IHPSG13_NAND2X2 +XA_TDEC<1> A_SEL_P<1> A_WR_ONE A_BLT_PMOS_DRIVE<1> VDD VSS / ++ RSC_IHPSG13_NAND2X2 +XA_TDEC<0> A_SEL_P<0> A_WR_ONE A_BLT_PMOS_DRIVE<0> VDD VSS / ++ RSC_IHPSG13_NAND2X2 +XA_CDEC<3> A_SEL_P<3> A_WR_ZERO A_BLC_PMOS_DRIVE<3> VDD VSS / ++ RSC_IHPSG13_NAND2X2 +XA_CDEC<2> A_SEL_P<2> A_WR_ZERO A_BLC_PMOS_DRIVE<2> VDD VSS / ++ RSC_IHPSG13_NAND2X2 +XA_CDEC<1> A_SEL_P<1> A_WR_ZERO A_BLC_PMOS_DRIVE<1> VDD VSS / ++ RSC_IHPSG13_NAND2X2 +XA_CDEC<0> A_SEL_P<0> A_WR_ZERO A_BLC_PMOS_DRIVE<0> VDD VSS / ++ RSC_IHPSG13_NAND2X2 +XB_CDEC<3> B_SEL_P<3> B_WR_ZERO B_BLC_PMOS_DRIVE<3> VDD VSS / ++ RSC_IHPSG13_NAND2X2 +XB_CDEC<2> B_SEL_P<2> B_WR_ZERO B_BLC_PMOS_DRIVE<2> VDD VSS / ++ RSC_IHPSG13_NAND2X2 +XB_CDEC<1> B_SEL_P<1> B_WR_ZERO B_BLC_PMOS_DRIVE<1> VDD VSS / ++ RSC_IHPSG13_NAND2X2 +XB_CDEC<0> B_SEL_P<0> B_WR_ZERO B_BLC_PMOS_DRIVE<0> VDD VSS / ++ RSC_IHPSG13_NAND2X2 +XB_TDEC<3> B_SEL_P<3> B_WR_ONE B_BLT_PMOS_DRIVE<3> VDD VSS / ++ RSC_IHPSG13_NAND2X2 +XB_TDEC<2> B_SEL_P<2> B_WR_ONE B_BLT_PMOS_DRIVE<2> VDD VSS / ++ RSC_IHPSG13_NAND2X2 +XB_TDEC<1> B_SEL_P<1> B_WR_ONE B_BLT_PMOS_DRIVE<1> VDD VSS / ++ RSC_IHPSG13_NAND2X2 +XB_TDEC<0> B_SEL_P<0> B_WR_ONE B_BLT_PMOS_DRIVE<0> VDD VSS / ++ RSC_IHPSG13_NAND2X2 +.ENDS +.SUBCKT RSC_IHPSG13_AND2X6 A B Z VDD VSS +MN3 Z net6 VSS VSS sg13_lv_nmos m=1 w=2.94u l=130.00n ng=3 nrd=0 nrs=0 +MN4 net9 B VSS VSS sg13_lv_nmos m=1 w=500.0n l=130.00n ng=1 nrd=0 nrs=0 +MN6 net6 A net9 VSS sg13_lv_nmos m=1 w=500.0n l=130.00n ng=1 nrd=0 nrs=0 +MP2 Z net6 VDD VDD sg13_lv_pmos m=1 w=4.86u l=130.00n ng=3 nrd=0 nrs=0 +MP0 net6 B VDD VDD sg13_lv_pmos m=1 w=860.00n l=130.00n ng=1 nrd=0 ++ nrs=0 +MP1 net6 A VDD VDD sg13_lv_pmos m=1 w=860.00n l=130.00n ng=1 nrd=0 ++ nrs=0 +.ENDS +.SUBCKT RM_IHPSG13_1024x16_c2_2P_COLCTRL5 A_ADDR_COL<1> A_ADDR_COL<0> A_ADDR_DEC<7> ++ A_ADDR_DEC<6> A_ADDR_DEC<5> A_ADDR_DEC<4> A_ADDR_DEC<3> A_ADDR_DEC<2> ++ A_ADDR_DEC<1> A_ADDR_DEC<0> A_BIST_BM_I A_BIST_DW_I A_BIST_EN_I A_BLC<31> ++ A_BLC<30> A_BLC<29> A_BLC<28> A_BLC<27> A_BLC<26> A_BLC<25> A_BLC<24> ++ A_BLC<23> A_BLC<22> A_BLC<21> A_BLC<20> A_BLC<19> A_BLC<18> A_BLC<17> ++ A_BLC<16> A_BLC<15> A_BLC<14> A_BLC<13> A_BLC<12> A_BLC<11> A_BLC<10> ++ A_BLC<9> A_BLC<8> A_BLC<7> A_BLC<6> A_BLC<5> A_BLC<4> A_BLC<3> A_BLC<2> ++ A_BLC<1> A_BLC<0> A_BLT<31> A_BLT<30> A_BLT<29> A_BLT<28> A_BLT<27> ++ A_BLT<26> A_BLT<25> A_BLT<24> A_BLT<23> A_BLT<22> A_BLT<21> A_BLT<20> ++ A_BLT<19> A_BLT<18> A_BLT<17> A_BLT<16> A_BLT<15> A_BLT<14> A_BLT<13> ++ A_BLT<12> A_BLT<11> A_BLT<10> A_BLT<9> A_BLT<8> A_BLT<7> A_BLT<6> A_BLT<5> ++ A_BLT<4> A_BLT<3> A_BLT<2> A_BLT<1> A_BLT<0> A_BM_I A_DCLK_B_L A_DCLK_B_R ++ A_DCLK_L A_DCLK_R A_DR_O A_DW_I A_RCLK_B_L A_RCLK_B_R A_RCLK_L A_RCLK_R ++ A_TIEH_O A_WCLK_B_L A_WCLK_B_R A_WCLK_L A_WCLK_R B_ADDR_COL<1> B_ADDR_COL<0> ++ B_ADDR_DEC<7> B_ADDR_DEC<6> B_ADDR_DEC<5> B_ADDR_DEC<4> B_ADDR_DEC<3> ++ B_ADDR_DEC<2> B_ADDR_DEC<1> B_ADDR_DEC<0> B_BIST_BM_I B_BIST_DW_I ++ B_BIST_EN_I B_BLC<31> B_BLC<30> B_BLC<29> B_BLC<28> B_BLC<27> B_BLC<26> ++ B_BLC<25> B_BLC<24> B_BLC<23> B_BLC<22> B_BLC<21> B_BLC<20> B_BLC<19> ++ B_BLC<18> B_BLC<17> B_BLC<16> B_BLC<15> B_BLC<14> B_BLC<13> B_BLC<12> ++ B_BLC<11> B_BLC<10> B_BLC<9> B_BLC<8> B_BLC<7> B_BLC<6> B_BLC<5> B_BLC<4> ++ B_BLC<3> B_BLC<2> B_BLC<1> B_BLC<0> B_BLT<31> B_BLT<30> B_BLT<29> B_BLT<28> ++ B_BLT<27> B_BLT<26> B_BLT<25> B_BLT<24> B_BLT<23> B_BLT<22> B_BLT<21> ++ B_BLT<20> B_BLT<19> B_BLT<18> B_BLT<17> B_BLT<16> B_BLT<15> B_BLT<14> ++ B_BLT<13> B_BLT<12> B_BLT<11> B_BLT<10> B_BLT<9> B_BLT<8> B_BLT<7> B_BLT<6> ++ B_BLT<5> B_BLT<4> B_BLT<3> B_BLT<2> B_BLT<1> B_BLT<0> B_BM_I B_DCLK_B_L ++ B_DCLK_B_R B_DCLK_L B_DCLK_R B_DR_O B_DW_I B_RCLK_B_L B_RCLK_B_R B_RCLK_L ++ B_RCLK_R B_TIEH_O B_WCLK_B_L B_WCLK_B_R B_WCLK_L B_WCLK_R VDD VSS +XB_I80<1> B_WCLK_B_L B_RCLK_B_L B_W_nor_R<1> VDD VSS / ++ RSC_IHPSG13_AND2X2 +XB_I80<0> B_WCLK_B_L B_RCLK_B_L B_W_nor_R<0> VDD VSS / ++ RSC_IHPSG13_AND2X2 +XA_I80<1> A_WCLK_B_L A_RCLK_B_L A_W_nor_R<1> VDD VSS / ++ RSC_IHPSG13_AND2X2 +XA_I80<0> A_WCLK_B_L A_RCLK_B_L A_W_nor_R<0> VDD VSS / ++ RSC_IHPSG13_AND2X2 +XB_I44 B_BM_N B_WCLK_B_L B_DO_WRITE_P VDD VSS / RSC_IHPSG13_NOR2X2 +XA_I44 A_BM_N A_WCLK_B_L A_DO_WRITE_P VDD VSS / RSC_IHPSG13_NOR2X2 +XI_FILL4<16> VDD VSS / RSC_IHPSG13_FILLCAP4 +XI_FILL4<15> VDD VSS / RSC_IHPSG13_FILLCAP4 +XI_FILL4<14> VDD VSS / RSC_IHPSG13_FILLCAP4 +XI_FILL4<13> VDD VSS / RSC_IHPSG13_FILLCAP4 +XI_FILL4<12> VDD VSS / RSC_IHPSG13_FILLCAP4 +XI_FILL4<11> VDD VSS / RSC_IHPSG13_FILLCAP4 +XI_FILL4<10> VDD VSS / RSC_IHPSG13_FILLCAP4 +XI_FILL4<9> VDD VSS / RSC_IHPSG13_FILLCAP4 +XI_FILL4<8> VDD VSS / RSC_IHPSG13_FILLCAP4 +XI_FILL4<7> VDD VSS / RSC_IHPSG13_FILLCAP4 +XI_FILL4<6> VDD VSS / RSC_IHPSG13_FILLCAP4 +XI_FILL4<5> VDD VSS / RSC_IHPSG13_FILLCAP4 +XI_FILL4<4> VDD VSS / RSC_IHPSG13_FILLCAP4 +XI_FILL4<3> VDD VSS / RSC_IHPSG13_FILLCAP4 +XI_FILL4<2> VDD VSS / RSC_IHPSG13_FILLCAP4 +XI_FILL4<1> VDD VSS / RSC_IHPSG13_FILLCAP4 +XB_INV<6> B_N1<1> B_P1<1> VDD VSS / RSC_IHPSG13_CINVX4 +XB_INV<5> B_N0<1> B_P0<1> VDD VSS / RSC_IHPSG13_CINVX4 +XB_INV<4> B_N0<0> B_P0<0> VDD VSS / RSC_IHPSG13_CINVX4 +XB_INV<3> B_ADDR_COL<1> B_N1<1> VDD VSS / RSC_IHPSG13_CINVX4 +XB_INV<2> B_ADDR_COL<1> B_N1<0> VDD VSS / RSC_IHPSG13_CINVX4 +XB_INV<1> B_ADDR_COL<0> B_N0<1> VDD VSS / RSC_IHPSG13_CINVX4 +XB_INV<0> B_ADDR_COL<0> B_N0<0> VDD VSS / RSC_IHPSG13_CINVX4 +XA_INV<6> A_N1<1> A_P1<1> VDD VSS / RSC_IHPSG13_CINVX4 +XA_INV<5> A_N0<1> A_P0<1> VDD VSS / RSC_IHPSG13_CINVX4 +XA_INV<4> A_N0<0> A_P0<0> VDD VSS / RSC_IHPSG13_CINVX4 +XA_INV<3> A_ADDR_COL<1> A_N1<1> VDD VSS / RSC_IHPSG13_CINVX4 +XA_INV<2> A_ADDR_COL<1> A_N1<0> VDD VSS / RSC_IHPSG13_CINVX4 +XA_INV<1> A_ADDR_COL<0> A_N0<1> VDD VSS / RSC_IHPSG13_CINVX4 +XA_INV<0> A_ADDR_COL<0> A_N0<0> VDD VSS / RSC_IHPSG13_CINVX4 +XB_I81<3> B_W_nor_R<1> B_PRE_N VDD VSS / RSC_IHPSG13_CINVX4_WN +XB_I81<2> B_W_nor_R<1> B_PRE_N VDD VSS / RSC_IHPSG13_CINVX4_WN +XB_I81<1> B_W_nor_R<0> B_PRE_N VDD VSS / RSC_IHPSG13_CINVX4_WN +XB_I81<0> B_W_nor_R<0> B_PRE_N VDD VSS / RSC_IHPSG13_CINVX4_WN +XA_I81<3> A_W_nor_R<1> A_PRE_N VDD VSS / RSC_IHPSG13_CINVX4_WN +XA_I81<2> A_W_nor_R<1> A_PRE_N VDD VSS / RSC_IHPSG13_CINVX4_WN +XA_I81<1> A_W_nor_R<0> A_PRE_N VDD VSS / RSC_IHPSG13_CINVX4_WN +XA_I81<0> A_W_nor_R<0> A_PRE_N VDD VSS / RSC_IHPSG13_CINVX4_WN +XI_FILL8<78> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI_FILL8<77> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI_FILL8<76> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI_FILL8<75> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI_FILL8<74> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI_FILL8<73> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI_FILL8<72> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI_FILL8<71> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI_FILL8<70> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI_FILL8<69> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI_FILL8<68> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI_FILL8<67> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI_FILL8<66> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI_FILL8<65> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI_FILL8<64> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI_FILL8<63> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI_FILL8<62> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI_FILL8<61> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI_FILL8<60> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI_FILL8<59> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI_FILL8<58> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI_FILL8<57> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI_FILL8<56> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI_FILL8<55> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI_FILL8<54> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI_FILL8<53> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI_FILL8<52> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI_FILL8<51> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI_FILL8<50> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI_FILL8<49> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI_FILL8<48> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI_FILL8<47> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI_FILL8<46> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI_FILL8<45> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI_FILL8<44> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI_FILL8<43> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI_FILL8<42> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI_FILL8<41> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI_FILL8<40> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI_FILL8<39> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI_FILL8<38> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI_FILL8<37> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI_FILL8<36> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI_FILL8<35> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI_FILL8<34> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI_FILL8<33> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI_FILL8<32> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI_FILL8<31> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI_FILL8<30> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI_FILL8<29> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI_FILL8<28> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI_FILL8<27> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI_FILL8<26> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI_FILL8<25> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI_FILL8<24> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI_FILL8<23> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI_FILL8<22> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI_FILL8<21> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI_FILL8<20> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI_FILL8<19> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI_FILL8<18> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI_FILL8<17> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI_FILL8<16> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI_FILL8<15> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI_FILL8<14> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI_FILL8<13> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI_FILL8<12> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI_FILL8<11> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI_FILL8<10> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI_FILL8<9> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI_FILL8<8> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI_FILL8<7> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI_FILL8<6> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI_FILL8<5> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI_FILL8<4> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI_FILL8<3> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI_FILL8<2> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI_FILL8<1> VDD VSS / RSC_IHPSG13_FILLCAP8 +XAB_BLMUX<7> A_BLC<31> A_BLC<30> A_BLC<29> A_BLC<28> A_BLC_SEL A_BLT<31> ++ A_BLT<30> A_BLT<29> A_BLT<28> A_BLT_SEL A_PRE_N A_SEL_P<31> A_SEL_P<30> ++ A_SEL_P<29> A_SEL_P<28> A_WR_ONE A_WR_ZERO B_BLC<31> B_BLC<30> B_BLC<29> ++ B_BLC<28> B_BLC_SEL B_BLT<31> B_BLT<30> B_BLT<29> B_BLT<28> B_BLT_SEL ++ B_PRE_N B_SEL_P<31> B_SEL_P<30> B_SEL_P<29> B_SEL_P<28> B_WR_ONE B_WR_ZERO ++ VDD VSS / RM_IHPSG13_1024x16_c2_2P_BLDRV +XAB_BLMUX<6> A_BLC<27> A_BLC<26> A_BLC<25> A_BLC<24> A_BLC_SEL A_BLT<27> ++ A_BLT<26> A_BLT<25> A_BLT<24> A_BLT_SEL A_PRE_N A_SEL_P<27> A_SEL_P<26> ++ A_SEL_P<25> A_SEL_P<24> A_WR_ONE A_WR_ZERO B_BLC<27> B_BLC<26> B_BLC<25> ++ B_BLC<24> B_BLC_SEL B_BLT<27> B_BLT<26> B_BLT<25> B_BLT<24> B_BLT_SEL ++ B_PRE_N B_SEL_P<27> B_SEL_P<26> B_SEL_P<25> B_SEL_P<24> B_WR_ONE B_WR_ZERO ++ VDD VSS / RM_IHPSG13_1024x16_c2_2P_BLDRV +XAB_BLMUX<5> A_BLC<23> A_BLC<22> A_BLC<21> A_BLC<20> A_BLC_SEL A_BLT<23> ++ A_BLT<22> A_BLT<21> A_BLT<20> A_BLT_SEL A_PRE_N A_SEL_P<23> A_SEL_P<22> ++ A_SEL_P<21> A_SEL_P<20> A_WR_ONE A_WR_ZERO B_BLC<23> B_BLC<22> B_BLC<21> ++ B_BLC<20> B_BLC_SEL B_BLT<23> B_BLT<22> B_BLT<21> B_BLT<20> B_BLT_SEL ++ B_PRE_N B_SEL_P<23> B_SEL_P<22> B_SEL_P<21> B_SEL_P<20> B_WR_ONE B_WR_ZERO ++ VDD VSS / RM_IHPSG13_1024x16_c2_2P_BLDRV +XAB_BLMUX<4> A_BLC<19> A_BLC<18> A_BLC<17> A_BLC<16> A_BLC_SEL A_BLT<19> ++ A_BLT<18> A_BLT<17> A_BLT<16> A_BLT_SEL A_PRE_N A_SEL_P<19> A_SEL_P<18> ++ A_SEL_P<17> A_SEL_P<16> A_WR_ONE A_WR_ZERO B_BLC<19> B_BLC<18> B_BLC<17> ++ B_BLC<16> B_BLC_SEL B_BLT<19> B_BLT<18> B_BLT<17> B_BLT<16> B_BLT_SEL ++ B_PRE_N B_SEL_P<19> B_SEL_P<18> B_SEL_P<17> B_SEL_P<16> B_WR_ONE B_WR_ZERO ++ VDD VSS / RM_IHPSG13_1024x16_c2_2P_BLDRV +XAB_BLMUX<3> A_BLC<15> A_BLC<14> A_BLC<13> A_BLC<12> A_BLC_SEL A_BLT<15> ++ A_BLT<14> A_BLT<13> A_BLT<12> A_BLT_SEL A_PRE_N A_SEL_P<15> A_SEL_P<14> ++ A_SEL_P<13> A_SEL_P<12> A_WR_ONE A_WR_ZERO B_BLC<15> B_BLC<14> B_BLC<13> ++ B_BLC<12> B_BLC_SEL B_BLT<15> B_BLT<14> B_BLT<13> B_BLT<12> B_BLT_SEL ++ B_PRE_N B_SEL_P<15> B_SEL_P<14> B_SEL_P<13> B_SEL_P<12> B_WR_ONE B_WR_ZERO ++ VDD VSS / RM_IHPSG13_1024x16_c2_2P_BLDRV +XAB_BLMUX<2> A_BLC<11> A_BLC<10> A_BLC<9> A_BLC<8> A_BLC_SEL A_BLT<11> ++ A_BLT<10> A_BLT<9> A_BLT<8> A_BLT_SEL A_PRE_N A_SEL_P<11> A_SEL_P<10> ++ A_SEL_P<9> A_SEL_P<8> A_WR_ONE A_WR_ZERO B_BLC<11> B_BLC<10> B_BLC<9> ++ B_BLC<8> B_BLC_SEL B_BLT<11> B_BLT<10> B_BLT<9> B_BLT<8> B_BLT_SEL B_PRE_N ++ B_SEL_P<11> B_SEL_P<10> B_SEL_P<9> B_SEL_P<8> B_WR_ONE B_WR_ZERO VDD ++ VSS / RM_IHPSG13_1024x16_c2_2P_BLDRV +XAB_BLMUX<1> A_BLC<7> A_BLC<6> A_BLC<5> A_BLC<4> A_BLC_SEL A_BLT<7> A_BLT<6> ++ A_BLT<5> A_BLT<4> A_BLT_SEL A_PRE_N A_SEL_P<7> A_SEL_P<6> A_SEL_P<5> ++ A_SEL_P<4> A_WR_ONE A_WR_ZERO B_BLC<7> B_BLC<6> B_BLC<5> B_BLC<4> B_BLC_SEL ++ B_BLT<7> B_BLT<6> B_BLT<5> B_BLT<4> B_BLT_SEL B_PRE_N B_SEL_P<7> B_SEL_P<6> ++ B_SEL_P<5> B_SEL_P<4> B_WR_ONE B_WR_ZERO VDD VSS / ++ RM_IHPSG13_1024x16_c2_2P_BLDRV +XAB_BLMUX<0> A_BLC<3> A_BLC<2> A_BLC<1> A_BLC<0> A_BLC_SEL A_BLT<3> A_BLT<2> ++ A_BLT<1> A_BLT<0> A_BLT_SEL A_PRE_N A_SEL_P<3> A_SEL_P<2> A_SEL_P<1> ++ A_SEL_P<0> A_WR_ONE A_WR_ZERO B_BLC<3> B_BLC<2> B_BLC<1> B_BLC<0> B_BLC_SEL ++ B_BLT<3> B_BLT<2> B_BLT<1> B_BLT<0> B_BLT_SEL B_PRE_N B_SEL_P<3> B_SEL_P<2> ++ B_SEL_P<1> B_SEL_P<0> B_WR_ONE B_WR_ZERO VDD VSS / ++ RM_IHPSG13_1024x16_c2_2P_BLDRV +XB_I51 net037 B_DR_O VDD VSS / RSC_IHPSG13_INVX4 +XA_I51 net19 A_DR_O VDD VSS / RSC_IHPSG13_INVX4 +XB_I78 B_RCLK_B_L B_SAE VDD VSS / RSC_IHPSG13_CBUFX2 +XA_I78 A_RCLK_B_L A_SAE VDD VSS / RSC_IHPSG13_CBUFX2 +XB_I69 B_DCLK_L B_DCLK_B_L VDD VSS / RSC_IHPSG13_CINVX8 +XB_I50 B_WCLK_L B_WCLK_B_L VDD VSS / RSC_IHPSG13_CINVX8 +XB_EBUF B_RCLK_L B_RCLK_B_L VDD VSS / RSC_IHPSG13_CINVX8 +XA_I69 A_DCLK_L A_DCLK_B_L VDD VSS / RSC_IHPSG13_CINVX8 +XA_I50 A_WCLK_L A_WCLK_B_L VDD VSS / RSC_IHPSG13_CINVX8 +XA_EBUF A_RCLK_L A_RCLK_B_L VDD VSS / RSC_IHPSG13_CINVX8 +XB_I76 B_DI_N B_DO_WRITE_P B_WR_ZERO VDD VSS / RSC_IHPSG13_AND2X6 +XB_I75 B_DI_R B_DO_WRITE_P B_WR_ONE VDD VSS / RSC_IHPSG13_AND2X6 +XA_I76 A_DI_N A_DO_WRITE_P A_WR_ZERO VDD VSS / RSC_IHPSG13_AND2X6 +XA_I75 A_DI_R A_DO_WRITE_P A_WR_ONE VDD VSS / RSC_IHPSG13_AND2X6 +XB_I83 B_BM_R B_BM_N VDD VSS / RSC_IHPSG13_INVX2 +XB_DEC3INV<31> net041<0> B_SEL_P<31> VDD VSS / RSC_IHPSG13_INVX2 +XB_DEC3INV<30> net041<1> B_SEL_P<30> VDD VSS / RSC_IHPSG13_INVX2 +XB_DEC3INV<29> net041<2> B_SEL_P<29> VDD VSS / RSC_IHPSG13_INVX2 +XB_DEC3INV<28> net041<3> B_SEL_P<28> VDD VSS / RSC_IHPSG13_INVX2 +XB_DEC3INV<27> net041<4> B_SEL_P<27> VDD VSS / RSC_IHPSG13_INVX2 +XB_DEC3INV<26> net041<5> B_SEL_P<26> VDD VSS / RSC_IHPSG13_INVX2 +XB_DEC3INV<25> net041<6> B_SEL_P<25> VDD VSS / RSC_IHPSG13_INVX2 +XB_DEC3INV<24> net041<7> B_SEL_P<24> VDD VSS / RSC_IHPSG13_INVX2 +XB_DEC3INV<23> net041<8> B_SEL_P<23> VDD VSS / RSC_IHPSG13_INVX2 +XB_DEC3INV<22> net041<9> B_SEL_P<22> VDD VSS / RSC_IHPSG13_INVX2 +XB_DEC3INV<21> net041<10> B_SEL_P<21> VDD VSS / RSC_IHPSG13_INVX2 +XB_DEC3INV<20> net041<11> B_SEL_P<20> VDD VSS / RSC_IHPSG13_INVX2 +XB_DEC3INV<19> net041<12> B_SEL_P<19> VDD VSS / RSC_IHPSG13_INVX2 +XB_DEC3INV<18> net041<13> B_SEL_P<18> VDD VSS / RSC_IHPSG13_INVX2 +XB_DEC3INV<17> net041<14> B_SEL_P<17> VDD VSS / RSC_IHPSG13_INVX2 +XB_DEC3INV<16> net041<15> B_SEL_P<16> VDD VSS / RSC_IHPSG13_INVX2 +XB_DEC3INV<15> net041<16> B_SEL_P<15> VDD VSS / RSC_IHPSG13_INVX2 +XB_DEC3INV<14> net041<17> B_SEL_P<14> VDD VSS / RSC_IHPSG13_INVX2 +XB_DEC3INV<13> net041<18> B_SEL_P<13> VDD VSS / RSC_IHPSG13_INVX2 +XB_DEC3INV<12> net041<19> B_SEL_P<12> VDD VSS / RSC_IHPSG13_INVX2 +XB_DEC3INV<11> net041<20> B_SEL_P<11> VDD VSS / RSC_IHPSG13_INVX2 +XB_DEC3INV<10> net041<21> B_SEL_P<10> VDD VSS / RSC_IHPSG13_INVX2 +XB_DEC3INV<9> net041<22> B_SEL_P<9> VDD VSS / RSC_IHPSG13_INVX2 +XB_DEC3INV<8> net041<23> B_SEL_P<8> VDD VSS / RSC_IHPSG13_INVX2 +XB_DEC3INV<7> net041<24> B_SEL_P<7> VDD VSS / RSC_IHPSG13_INVX2 +XB_DEC3INV<6> net041<25> B_SEL_P<6> VDD VSS / RSC_IHPSG13_INVX2 +XB_DEC3INV<5> net041<26> B_SEL_P<5> VDD VSS / RSC_IHPSG13_INVX2 +XB_DEC3INV<4> net041<27> B_SEL_P<4> VDD VSS / RSC_IHPSG13_INVX2 +XB_DEC3INV<3> net041<28> B_SEL_P<3> VDD VSS / RSC_IHPSG13_INVX2 +XB_DEC3INV<2> net041<29> B_SEL_P<2> VDD VSS / RSC_IHPSG13_INVX2 +XB_DEC3INV<1> net041<30> B_SEL_P<1> VDD VSS / RSC_IHPSG13_INVX2 +XB_DEC3INV<0> net041<31> B_SEL_P<0> VDD VSS / RSC_IHPSG13_INVX2 +XB_I49 B_DI_R B_DI_N VDD VSS / RSC_IHPSG13_INVX2 +XA_I83 A_BM_R A_BM_N VDD VSS / RSC_IHPSG13_INVX2 +XA_DEC3INV<31> net23<0> A_SEL_P<31> VDD VSS / RSC_IHPSG13_INVX2 +XA_DEC3INV<30> net23<1> A_SEL_P<30> VDD VSS / RSC_IHPSG13_INVX2 +XA_DEC3INV<29> net23<2> A_SEL_P<29> VDD VSS / RSC_IHPSG13_INVX2 +XA_DEC3INV<28> net23<3> A_SEL_P<28> VDD VSS / RSC_IHPSG13_INVX2 +XA_DEC3INV<27> net23<4> A_SEL_P<27> VDD VSS / RSC_IHPSG13_INVX2 +XA_DEC3INV<26> net23<5> A_SEL_P<26> VDD VSS / RSC_IHPSG13_INVX2 +XA_DEC3INV<25> net23<6> A_SEL_P<25> VDD VSS / RSC_IHPSG13_INVX2 +XA_DEC3INV<24> net23<7> A_SEL_P<24> VDD VSS / RSC_IHPSG13_INVX2 +XA_DEC3INV<23> net23<8> A_SEL_P<23> VDD VSS / RSC_IHPSG13_INVX2 +XA_DEC3INV<22> net23<9> A_SEL_P<22> VDD VSS / RSC_IHPSG13_INVX2 +XA_DEC3INV<21> net23<10> A_SEL_P<21> VDD VSS / RSC_IHPSG13_INVX2 +XA_DEC3INV<20> net23<11> A_SEL_P<20> VDD VSS / RSC_IHPSG13_INVX2 +XA_DEC3INV<19> net23<12> A_SEL_P<19> VDD VSS / RSC_IHPSG13_INVX2 +XA_DEC3INV<18> net23<13> A_SEL_P<18> VDD VSS / RSC_IHPSG13_INVX2 +XA_DEC3INV<17> net23<14> A_SEL_P<17> VDD VSS / RSC_IHPSG13_INVX2 +XA_DEC3INV<16> net23<15> A_SEL_P<16> VDD VSS / RSC_IHPSG13_INVX2 +XA_DEC3INV<15> net23<16> A_SEL_P<15> VDD VSS / RSC_IHPSG13_INVX2 +XA_DEC3INV<14> net23<17> A_SEL_P<14> VDD VSS / RSC_IHPSG13_INVX2 +XA_DEC3INV<13> net23<18> A_SEL_P<13> VDD VSS / RSC_IHPSG13_INVX2 +XA_DEC3INV<12> net23<19> A_SEL_P<12> VDD VSS / RSC_IHPSG13_INVX2 +XA_DEC3INV<11> net23<20> A_SEL_P<11> VDD VSS / RSC_IHPSG13_INVX2 +XA_DEC3INV<10> net23<21> A_SEL_P<10> VDD VSS / RSC_IHPSG13_INVX2 +XA_DEC3INV<9> net23<22> A_SEL_P<9> VDD VSS / RSC_IHPSG13_INVX2 +XA_DEC3INV<8> net23<23> A_SEL_P<8> VDD VSS / RSC_IHPSG13_INVX2 +XA_DEC3INV<7> net23<24> A_SEL_P<7> VDD VSS / RSC_IHPSG13_INVX2 +XA_DEC3INV<6> net23<25> A_SEL_P<6> VDD VSS / RSC_IHPSG13_INVX2 +XA_DEC3INV<5> net23<26> A_SEL_P<5> VDD VSS / RSC_IHPSG13_INVX2 +XA_DEC3INV<4> net23<27> A_SEL_P<4> VDD VSS / RSC_IHPSG13_INVX2 +XA_DEC3INV<3> net23<28> A_SEL_P<3> VDD VSS / RSC_IHPSG13_INVX2 +XA_DEC3INV<2> net23<29> A_SEL_P<2> VDD VSS / RSC_IHPSG13_INVX2 +XA_DEC3INV<1> net23<30> A_SEL_P<1> VDD VSS / RSC_IHPSG13_INVX2 +XA_DEC3INV<0> net23<31> A_SEL_P<0> VDD VSS / RSC_IHPSG13_INVX2 +XA_I49 A_DI_R A_DI_N VDD VSS / RSC_IHPSG13_INVX2 +XB_ISENSE B_SAE B_BLC_SEL B_BLT_SEL net037 net038 VDD VSS / ++ RSC_IHPSG13_DFPQD_MSAFFX2 +XA_ISENSE A_SAE A_BLC_SEL A_BLT_SEL net19 net20 VDD VSS / ++ RSC_IHPSG13_DFPQD_MSAFFX2 +XB_DREG B_BIST_EN_I B_BIST_DW_I B_DCLK_B_L B_DW_I B_DI_R net042 VDD ++ VSS / RSC_IHPSG13_DFNQMX2IX1 +XB_BREG B_BIST_EN_I B_BIST_BM_I B_DCLK_B_L B_BM_I B_BM_R net043 VDD ++ VSS / RSC_IHPSG13_DFNQMX2IX1 +XA_DREG A_BIST_EN_I A_BIST_DW_I A_DCLK_B_L A_DW_I A_DI_R net22 VDD VSS ++ / RSC_IHPSG13_DFNQMX2IX1 +XA_BREG A_BIST_EN_I A_BIST_BM_I A_DCLK_B_L A_BM_I A_BM_R net21 VDD VSS ++ / RSC_IHPSG13_DFNQMX2IX1 +XB_DEC3<31> B_P1<1> B_P0<1> B_ADDR_DEC<7> net041<0> VDD VSS / ++ RSC_IHPSG13_NAND3X2 +XB_DEC3<30> B_P1<1> B_P0<1> B_ADDR_DEC<6> net041<1> VDD VSS / ++ RSC_IHPSG13_NAND3X2 +XB_DEC3<29> B_P1<1> B_P0<1> B_ADDR_DEC<5> net041<2> VDD VSS / ++ RSC_IHPSG13_NAND3X2 +XB_DEC3<28> B_P1<1> B_P0<1> B_ADDR_DEC<4> net041<3> VDD VSS / ++ RSC_IHPSG13_NAND3X2 +XB_DEC3<27> B_P1<1> B_P0<1> B_ADDR_DEC<3> net041<4> VDD VSS / ++ RSC_IHPSG13_NAND3X2 +XB_DEC3<26> B_P1<1> B_P0<1> B_ADDR_DEC<2> net041<5> VDD VSS / ++ RSC_IHPSG13_NAND3X2 +XB_DEC3<25> B_P1<1> B_P0<1> B_ADDR_DEC<1> net041<6> VDD VSS / ++ RSC_IHPSG13_NAND3X2 +XB_DEC3<24> B_P1<1> B_P0<1> B_ADDR_DEC<0> net041<7> VDD VSS / ++ RSC_IHPSG13_NAND3X2 +XB_DEC3<23> B_P1<1> B_N0<1> B_ADDR_DEC<7> net041<8> VDD VSS / ++ RSC_IHPSG13_NAND3X2 +XB_DEC3<22> B_P1<1> B_N0<1> B_ADDR_DEC<6> net041<9> VDD VSS / ++ RSC_IHPSG13_NAND3X2 +XB_DEC3<21> B_P1<1> B_N0<1> B_ADDR_DEC<5> net041<10> VDD VSS / ++ RSC_IHPSG13_NAND3X2 +XB_DEC3<20> B_P1<1> B_N0<1> B_ADDR_DEC<4> net041<11> VDD VSS / ++ RSC_IHPSG13_NAND3X2 +XB_DEC3<19> B_P1<1> B_N0<1> B_ADDR_DEC<3> net041<12> VDD VSS / ++ RSC_IHPSG13_NAND3X2 +XB_DEC3<18> B_P1<1> B_N0<1> B_ADDR_DEC<2> net041<13> VDD VSS / ++ RSC_IHPSG13_NAND3X2 +XB_DEC3<17> B_P1<1> B_N0<1> B_ADDR_DEC<1> net041<14> VDD VSS / ++ RSC_IHPSG13_NAND3X2 +XB_DEC3<16> B_P1<1> B_N0<1> B_ADDR_DEC<0> net041<15> VDD VSS / ++ RSC_IHPSG13_NAND3X2 +XB_DEC3<15> B_N1<0> B_P0<0> B_ADDR_DEC<7> net041<16> VDD VSS / ++ RSC_IHPSG13_NAND3X2 +XB_DEC3<14> B_N1<0> B_P0<0> B_ADDR_DEC<6> net041<17> VDD VSS / ++ RSC_IHPSG13_NAND3X2 +XB_DEC3<13> B_N1<0> B_P0<0> B_ADDR_DEC<5> net041<18> VDD VSS / ++ RSC_IHPSG13_NAND3X2 +XB_DEC3<12> B_N1<0> B_P0<0> B_ADDR_DEC<4> net041<19> VDD VSS / ++ RSC_IHPSG13_NAND3X2 +XB_DEC3<11> B_N1<0> B_P0<0> B_ADDR_DEC<3> net041<20> VDD VSS / ++ RSC_IHPSG13_NAND3X2 +XB_DEC3<10> B_N1<0> B_P0<0> B_ADDR_DEC<2> net041<21> VDD VSS / ++ RSC_IHPSG13_NAND3X2 +XB_DEC3<9> B_N1<0> B_P0<0> B_ADDR_DEC<1> net041<22> VDD VSS / ++ RSC_IHPSG13_NAND3X2 +XB_DEC3<8> B_N1<0> B_P0<0> B_ADDR_DEC<0> net041<23> VDD VSS / ++ RSC_IHPSG13_NAND3X2 +XB_DEC3<7> B_N1<0> B_N0<0> B_ADDR_DEC<7> net041<24> VDD VSS / ++ RSC_IHPSG13_NAND3X2 +XB_DEC3<6> B_N1<0> B_N0<0> B_ADDR_DEC<6> net041<25> VDD VSS / ++ RSC_IHPSG13_NAND3X2 +XB_DEC3<5> B_N1<0> B_N0<0> B_ADDR_DEC<5> net041<26> VDD VSS / ++ RSC_IHPSG13_NAND3X2 +XB_DEC3<4> B_N1<0> B_N0<0> B_ADDR_DEC<4> net041<27> VDD VSS / ++ RSC_IHPSG13_NAND3X2 +XB_DEC3<3> B_N1<0> B_N0<0> B_ADDR_DEC<3> net041<28> VDD VSS / ++ RSC_IHPSG13_NAND3X2 +XB_DEC3<2> B_N1<0> B_N0<0> B_ADDR_DEC<2> net041<29> VDD VSS / ++ RSC_IHPSG13_NAND3X2 +XB_DEC3<1> B_N1<0> B_N0<0> B_ADDR_DEC<1> net041<30> VDD VSS / ++ RSC_IHPSG13_NAND3X2 +XB_DEC3<0> B_N1<0> B_N0<0> B_ADDR_DEC<0> net041<31> VDD VSS / ++ RSC_IHPSG13_NAND3X2 +XA_DEC3<31> A_P1<1> A_P0<1> A_ADDR_DEC<7> net23<0> VDD VSS / ++ RSC_IHPSG13_NAND3X2 +XA_DEC3<30> A_P1<1> A_P0<1> A_ADDR_DEC<6> net23<1> VDD VSS / ++ RSC_IHPSG13_NAND3X2 +XA_DEC3<29> A_P1<1> A_P0<1> A_ADDR_DEC<5> net23<2> VDD VSS / ++ RSC_IHPSG13_NAND3X2 +XA_DEC3<28> A_P1<1> A_P0<1> A_ADDR_DEC<4> net23<3> VDD VSS / ++ RSC_IHPSG13_NAND3X2 +XA_DEC3<27> A_P1<1> A_P0<1> A_ADDR_DEC<3> net23<4> VDD VSS / ++ RSC_IHPSG13_NAND3X2 +XA_DEC3<26> A_P1<1> A_P0<1> A_ADDR_DEC<2> net23<5> VDD VSS / ++ RSC_IHPSG13_NAND3X2 +XA_DEC3<25> A_P1<1> A_P0<1> A_ADDR_DEC<1> net23<6> VDD VSS / ++ RSC_IHPSG13_NAND3X2 +XA_DEC3<24> A_P1<1> A_P0<1> A_ADDR_DEC<0> net23<7> VDD VSS / ++ RSC_IHPSG13_NAND3X2 +XA_DEC3<23> A_P1<1> A_N0<1> A_ADDR_DEC<7> net23<8> VDD VSS / ++ RSC_IHPSG13_NAND3X2 +XA_DEC3<22> A_P1<1> A_N0<1> A_ADDR_DEC<6> net23<9> VDD VSS / ++ RSC_IHPSG13_NAND3X2 +XA_DEC3<21> A_P1<1> A_N0<1> A_ADDR_DEC<5> net23<10> VDD VSS / ++ RSC_IHPSG13_NAND3X2 +XA_DEC3<20> A_P1<1> A_N0<1> A_ADDR_DEC<4> net23<11> VDD VSS / ++ RSC_IHPSG13_NAND3X2 +XA_DEC3<19> A_P1<1> A_N0<1> A_ADDR_DEC<3> net23<12> VDD VSS / ++ RSC_IHPSG13_NAND3X2 +XA_DEC3<18> A_P1<1> A_N0<1> A_ADDR_DEC<2> net23<13> VDD VSS / ++ RSC_IHPSG13_NAND3X2 +XA_DEC3<17> A_P1<1> A_N0<1> A_ADDR_DEC<1> net23<14> VDD VSS / ++ RSC_IHPSG13_NAND3X2 +XA_DEC3<16> A_P1<1> A_N0<1> A_ADDR_DEC<0> net23<15> VDD VSS / ++ RSC_IHPSG13_NAND3X2 +XA_DEC3<15> A_N1<0> A_P0<0> A_ADDR_DEC<7> net23<16> VDD VSS / ++ RSC_IHPSG13_NAND3X2 +XA_DEC3<14> A_N1<0> A_P0<0> A_ADDR_DEC<6> net23<17> VDD VSS / ++ RSC_IHPSG13_NAND3X2 +XA_DEC3<13> A_N1<0> A_P0<0> A_ADDR_DEC<5> net23<18> VDD VSS / ++ RSC_IHPSG13_NAND3X2 +XA_DEC3<12> A_N1<0> A_P0<0> A_ADDR_DEC<4> net23<19> VDD VSS / ++ RSC_IHPSG13_NAND3X2 +XA_DEC3<11> A_N1<0> A_P0<0> A_ADDR_DEC<3> net23<20> VDD VSS / ++ RSC_IHPSG13_NAND3X2 +XA_DEC3<10> A_N1<0> A_P0<0> A_ADDR_DEC<2> net23<21> VDD VSS / ++ RSC_IHPSG13_NAND3X2 +XA_DEC3<9> A_N1<0> A_P0<0> A_ADDR_DEC<1> net23<22> VDD VSS / ++ RSC_IHPSG13_NAND3X2 +XA_DEC3<8> A_N1<0> A_P0<0> A_ADDR_DEC<0> net23<23> VDD VSS / ++ RSC_IHPSG13_NAND3X2 +XA_DEC3<7> A_N1<0> A_N0<0> A_ADDR_DEC<7> net23<24> VDD VSS / ++ RSC_IHPSG13_NAND3X2 +XA_DEC3<6> A_N1<0> A_N0<0> A_ADDR_DEC<6> net23<25> VDD VSS / ++ RSC_IHPSG13_NAND3X2 +XA_DEC3<5> A_N1<0> A_N0<0> A_ADDR_DEC<5> net23<26> VDD VSS / ++ RSC_IHPSG13_NAND3X2 +XA_DEC3<4> A_N1<0> A_N0<0> A_ADDR_DEC<4> net23<27> VDD VSS / ++ RSC_IHPSG13_NAND3X2 +XA_DEC3<3> A_N1<0> A_N0<0> A_ADDR_DEC<3> net23<28> VDD VSS / ++ RSC_IHPSG13_NAND3X2 +XA_DEC3<2> A_N1<0> A_N0<0> A_ADDR_DEC<2> net23<29> VDD VSS / ++ RSC_IHPSG13_NAND3X2 +XA_DEC3<1> A_N1<0> A_N0<0> A_ADDR_DEC<1> net23<30> VDD VSS / ++ RSC_IHPSG13_NAND3X2 +XA_DEC3<0> A_N1<0> A_N0<0> A_ADDR_DEC<0> net23<31> VDD VSS / ++ RSC_IHPSG13_NAND3X2 +XB_I89 B_DCLK_B_L B_DCLK_B_R / RSC_IHPSG13_MET3RES +XB_I91 B_RCLK_B_L B_RCLK_B_R / RSC_IHPSG13_MET3RES +XB_I90 B_WCLK_B_L B_WCLK_B_R / RSC_IHPSG13_MET3RES +XB_I88 B_DCLK_L B_DCLK_R / RSC_IHPSG13_MET3RES +XB_I87 B_WCLK_L B_WCLK_R / RSC_IHPSG13_MET3RES +XB_R2 B_RCLK_L B_RCLK_R / RSC_IHPSG13_MET3RES +XA_I89 A_DCLK_B_L A_DCLK_B_R / RSC_IHPSG13_MET3RES +XA_I91 A_RCLK_B_L A_RCLK_B_R / RSC_IHPSG13_MET3RES +XA_I90 A_WCLK_B_L A_WCLK_B_R / RSC_IHPSG13_MET3RES +XA_I88 A_DCLK_L A_DCLK_R / RSC_IHPSG13_MET3RES +XA_I87 A_WCLK_L A_WCLK_R / RSC_IHPSG13_MET3RES +XA_R2 A_RCLK_L A_RCLK_R / RSC_IHPSG13_MET3RES +XB_BM_TIEH B_TIEH_O VDD VSS / RSC_IHPSG13_TIEH +XA_BM_TIEH A_TIEH_O VDD VSS / RSC_IHPSG13_TIEH +.ENDS +.SUBCKT RM_IHPSG13_1024x16_c2_2P_COLDRV13_FILL4 VDD VSS +XI0<11> VDD VSS / RSC_IHPSG13_FILLCAP4 +XI0<10> VDD VSS / RSC_IHPSG13_FILLCAP4 +XI0<9> VDD VSS / RSC_IHPSG13_FILLCAP4 +XI0<8> VDD VSS / RSC_IHPSG13_FILLCAP4 +XI0<7> VDD VSS / RSC_IHPSG13_FILLCAP4 +XI0<6> VDD VSS / RSC_IHPSG13_FILLCAP4 +XI0<5> VDD VSS / RSC_IHPSG13_FILLCAP4 +XI0<4> VDD VSS / RSC_IHPSG13_FILLCAP4 +XI0<3> VDD VSS / RSC_IHPSG13_FILLCAP4 +XI0<2> VDD VSS / RSC_IHPSG13_FILLCAP4 +XI0<1> VDD VSS / RSC_IHPSG13_FILLCAP4 +.ENDS + + +.SUBCKT RSC_IHPSG13_CBUFX16 A Z VDD VSS +MN0 net4 A VSS VSS sg13_lv_nmos m=1 w=2.115u l=130.00n ng=3 nrd=0 nrs=0 +MN1 Z net4 VSS VSS sg13_lv_nmos m=1 w=5.64u l=130.00n ng=8 nrd=0 nrs=0 +MP1 Z net4 VDD VDD sg13_lv_pmos m=1 w=13.000u l=130.00n ng=8 nrd=0 ++ nrs=0 +MP0 net4 A VDD VDD sg13_lv_pmos m=1 w=4.89u l=130.00n ng=3 nrd=0 nrs=0 +.ENDS +.SUBCKT RM_IHPSG13_1024x16_c2_1P_COLDRV13X16 ADDR_COL_I<1> ADDR_COL_I<0> ADDR_COL_O<1> ++ ADDR_COL_O<0> ADDR_DEC_I<7> ADDR_DEC_I<6> ADDR_DEC_I<5> ADDR_DEC_I<4> ++ ADDR_DEC_I<3> ADDR_DEC_I<2> ADDR_DEC_I<1> ADDR_DEC_I<0> ADDR_DEC_O<7> ++ ADDR_DEC_O<6> ADDR_DEC_O<5> ADDR_DEC_O<4> ADDR_DEC_O<3> ADDR_DEC_O<2> ++ ADDR_DEC_O<1> ADDR_DEC_O<0> DCLK_I DCLK_O RCLK_I RCLK_O WCLK_I WCLK_O ++ VDD VSS +XI1<1> VDD VSS / RSC_IHPSG13_FILLCAP4 +XI1<0> VDD VSS / RSC_IHPSG13_FILLCAP4 +XI0<3> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI0<2> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI0<1> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI0<0> VDD VSS / RSC_IHPSG13_FILLCAP8 +XADDR_COL_DRV<1> ADDR_COL_I<1> ADDR_COL_O<1> VDD VSS / ++ RSC_IHPSG13_CBUFX16 +XADDR_COL_DRV<0> ADDR_COL_I<0> ADDR_COL_O<0> VDD VSS / ++ RSC_IHPSG13_CBUFX16 +XADDR_DEC_DRV<7> ADDR_DEC_I<7> ADDR_DEC_O<7> VDD VSS / ++ RSC_IHPSG13_CBUFX16 +XADDR_DEC_DRV<6> ADDR_DEC_I<6> ADDR_DEC_O<6> VDD VSS / ++ RSC_IHPSG13_CBUFX16 +XADDR_DEC_DRV<5> ADDR_DEC_I<5> ADDR_DEC_O<5> VDD VSS / ++ RSC_IHPSG13_CBUFX16 +XADDR_DEC_DRV<4> ADDR_DEC_I<4> ADDR_DEC_O<4> VDD VSS / ++ RSC_IHPSG13_CBUFX16 +XADDR_DEC_DRV<3> ADDR_DEC_I<3> ADDR_DEC_O<3> VDD VSS / ++ RSC_IHPSG13_CBUFX16 +XADDR_DEC_DRV<2> ADDR_DEC_I<2> ADDR_DEC_O<2> VDD VSS / ++ RSC_IHPSG13_CBUFX16 +XADDR_DEC_DRV<1> ADDR_DEC_I<1> ADDR_DEC_O<1> VDD VSS / ++ RSC_IHPSG13_CBUFX16 +XADDR_DEC_DRV<0> ADDR_DEC_I<0> ADDR_DEC_O<0> VDD VSS / ++ RSC_IHPSG13_CBUFX16 +XDCLK_DRV DCLK_I DCLK_O VDD VSS / RSC_IHPSG13_CBUFX16 +XRCLK_DRV RCLK_I RCLK_O VDD VSS / RSC_IHPSG13_CBUFX16 +XWCLK_DRV WCLK_I WCLK_O VDD VSS / RSC_IHPSG13_CBUFX16 +.ENDS +.SUBCKT RSC_IHPSG13_WLDRVX16 A Z VDD VSS +MN1 Z net6 VSS VSS sg13_lv_nmos m=1 w=1.41u l=130.00n ng=2 nrd=0 nrs=0 +MN0 net6 A VSS VSS sg13_lv_nmos m=1 w=1.8u l=130.00n ng=2 nrd=0 nrs=0 +MP1 Z net6 VDD VDD sg13_lv_pmos m=1 w=12.96u l=130.00n ng=8 nrd=0 nrs=0 +MP0 net6 A VDD VDD sg13_lv_pmos m=1 w=900.0n l=130.00n ng=1 nrd=0 nrs=0 +.ENDS +.SUBCKT RM_IHPSG13_1024x16_c2_1P_WLDRV16X16 A<15> A<14> A<13> A<12> A<11> A<10> A<9> A<8> ++ A<7> A<6> A<5> A<4> A<3> A<2> A<1> A<0> Z<15> Z<14> Z<13> Z<12> Z<11> Z<10> ++ Z<9> Z<8> Z<7> Z<6> Z<5> Z<4> Z<3> Z<2> Z<1> Z<0> VDD VSS +XBUF<15> A<15> Z<15> VDD VSS / RSC_IHPSG13_WLDRVX16 +XBUF<14> A<14> Z<14> VDD VSS / RSC_IHPSG13_WLDRVX16 +XBUF<13> A<13> Z<13> VDD VSS / RSC_IHPSG13_WLDRVX16 +XBUF<12> A<12> Z<12> VDD VSS / RSC_IHPSG13_WLDRVX16 +XBUF<11> A<11> Z<11> VDD VSS / RSC_IHPSG13_WLDRVX16 +XBUF<10> A<10> Z<10> VDD VSS / RSC_IHPSG13_WLDRVX16 +XBUF<9> A<9> Z<9> VDD VSS / RSC_IHPSG13_WLDRVX16 +XBUF<8> A<8> Z<8> VDD VSS / RSC_IHPSG13_WLDRVX16 +XBUF<7> A<7> Z<7> VDD VSS / RSC_IHPSG13_WLDRVX16 +XBUF<6> A<6> Z<6> VDD VSS / RSC_IHPSG13_WLDRVX16 +XBUF<5> A<5> Z<5> VDD VSS / RSC_IHPSG13_WLDRVX16 +XBUF<4> A<4> Z<4> VDD VSS / RSC_IHPSG13_WLDRVX16 +XBUF<3> A<3> Z<3> VDD VSS / RSC_IHPSG13_WLDRVX16 +XBUF<2> A<2> Z<2> VDD VSS / RSC_IHPSG13_WLDRVX16 +XBUF<1> A<1> Z<1> VDD VSS / RSC_IHPSG13_WLDRVX16 +XBUF<0> A<0> Z<0> VDD VSS / RSC_IHPSG13_WLDRVX16 +.ENDS + + +.SUBCKT RM_IHPSG13_1024x16_c2_2P_COLDRV13X4 ADDR_COL_I<1> ADDR_COL_I<0> ADDR_COL_O<1> ++ ADDR_COL_O<0> ADDR_DEC_I<7> ADDR_DEC_I<6> ADDR_DEC_I<5> ADDR_DEC_I<4> ++ ADDR_DEC_I<3> ADDR_DEC_I<2> ADDR_DEC_I<1> ADDR_DEC_I<0> ADDR_DEC_O<7> ++ ADDR_DEC_O<6> ADDR_DEC_O<5> ADDR_DEC_O<4> ADDR_DEC_O<3> ADDR_DEC_O<2> ++ ADDR_DEC_O<1> ADDR_DEC_O<0> DCLK_I DCLK_O RCLK_I RCLK_O WCLK_I WCLK_O ++ VDD VSS +XWCLK_DRV WCLK_I WCLK_O VDD VSS / RSC_IHPSG13_CBUFX4 +XRCLK_DRV RCLK_I RCLK_O VDD VSS / RSC_IHPSG13_CBUFX4 +XDCLK_DRV DCLK_I DCLK_O VDD VSS / RSC_IHPSG13_CBUFX4 +XADDR_COL_DRV<1> ADDR_COL_I<1> ADDR_COL_O<1> VDD VSS / ++ RSC_IHPSG13_CBUFX4 +XADDR_COL_DRV<0> ADDR_COL_I<0> ADDR_COL_O<0> VDD VSS / ++ RSC_IHPSG13_CBUFX4 +XADDR_DEC_DRV<7> ADDR_DEC_I<7> ADDR_DEC_O<7> VDD VSS / ++ RSC_IHPSG13_CBUFX4 +XADDR_DEC_DRV<6> ADDR_DEC_I<6> ADDR_DEC_O<6> VDD VSS / ++ RSC_IHPSG13_CBUFX4 +XADDR_DEC_DRV<5> ADDR_DEC_I<5> ADDR_DEC_O<5> VDD VSS / ++ RSC_IHPSG13_CBUFX4 +XADDR_DEC_DRV<4> ADDR_DEC_I<4> ADDR_DEC_O<4> VDD VSS / ++ RSC_IHPSG13_CBUFX4 +XADDR_DEC_DRV<3> ADDR_DEC_I<3> ADDR_DEC_O<3> VDD VSS / ++ RSC_IHPSG13_CBUFX4 +XADDR_DEC_DRV<2> ADDR_DEC_I<2> ADDR_DEC_O<2> VDD VSS / ++ RSC_IHPSG13_CBUFX4 +XADDR_DEC_DRV<1> ADDR_DEC_I<1> ADDR_DEC_O<1> VDD VSS / ++ RSC_IHPSG13_CBUFX4 +XADDR_DEC_DRV<0> ADDR_DEC_I<0> ADDR_DEC_O<0> VDD VSS / ++ RSC_IHPSG13_CBUFX4 +XI0<6> VDD VSS / RSC_IHPSG13_FILLCAP4 +XI0<5> VDD VSS / RSC_IHPSG13_FILLCAP4 +XI0<4> VDD VSS / RSC_IHPSG13_FILLCAP4 +XI0<3> VDD VSS / RSC_IHPSG13_FILLCAP4 +XI0<2> VDD VSS / RSC_IHPSG13_FILLCAP4 +XI0<1> VDD VSS / RSC_IHPSG13_FILLCAP4 +XI1 VDD VSS / RSC_IHPSG13_FILLCAP8 +.ENDS +.SUBCKT RM_IHPSG13_1024x16_c2_2P_WLDRV16X4 A<15> A<14> A<13> A<12> A<11> A<10> A<9> A<8> ++ A<7> A<6> A<5> A<4> A<3> A<2> A<1> A<0> Z<15> Z<14> Z<13> Z<12> Z<11> Z<10> ++ Z<9> Z<8> Z<7> Z<6> Z<5> Z<4> Z<3> Z<2> Z<1> Z<0> VDD VSS +XBUF<15> A<15> Z<15> VDD VSS / RSC_IHPSG13_WLDRVX4 +XBUF<14> A<14> Z<14> VDD VSS / RSC_IHPSG13_WLDRVX4 +XBUF<13> A<13> Z<13> VDD VSS / RSC_IHPSG13_WLDRVX4 +XBUF<12> A<12> Z<12> VDD VSS / RSC_IHPSG13_WLDRVX4 +XBUF<11> A<11> Z<11> VDD VSS / RSC_IHPSG13_WLDRVX4 +XBUF<10> A<10> Z<10> VDD VSS / RSC_IHPSG13_WLDRVX4 +XBUF<9> A<9> Z<9> VDD VSS / RSC_IHPSG13_WLDRVX4 +XBUF<8> A<8> Z<8> VDD VSS / RSC_IHPSG13_WLDRVX4 +XBUF<7> A<7> Z<7> VDD VSS / RSC_IHPSG13_WLDRVX4 +XBUF<6> A<6> Z<6> VDD VSS / RSC_IHPSG13_WLDRVX4 +XBUF<5> A<5> Z<5> VDD VSS / RSC_IHPSG13_WLDRVX4 +XBUF<4> A<4> Z<4> VDD VSS / RSC_IHPSG13_WLDRVX4 +XBUF<3> A<3> Z<3> VDD VSS / RSC_IHPSG13_WLDRVX4 +XBUF<2> A<2> Z<2> VDD VSS / RSC_IHPSG13_WLDRVX4 +XBUF<1> A<1> Z<1> VDD VSS / RSC_IHPSG13_WLDRVX4 +XBUF<0> A<0> Z<0> VDD VSS / RSC_IHPSG13_WLDRVX4 +.ENDS +.SUBCKT RM_IHPSG13_1024x16_c2_2P_ROWDEC8 ADDR_N_I<7> ADDR_N_I<6> ADDR_N_I<5> ADDR_N_I<4> ++ ADDR_N_I<3> ADDR_N_I<2> ADDR_N_I<1> ADDR_N_I<0> CS_I ECLK_I WL_O<255> ++ WL_O<254> WL_O<253> WL_O<252> WL_O<251> WL_O<250> WL_O<249> WL_O<248> ++ WL_O<247> WL_O<246> WL_O<245> WL_O<244> WL_O<243> WL_O<242> WL_O<241> ++ WL_O<240> WL_O<239> WL_O<238> WL_O<237> WL_O<236> WL_O<235> WL_O<234> ++ WL_O<233> WL_O<232> WL_O<231> WL_O<230> WL_O<229> WL_O<228> WL_O<227> ++ WL_O<226> WL_O<225> WL_O<224> WL_O<223> WL_O<222> WL_O<221> WL_O<220> ++ WL_O<219> WL_O<218> WL_O<217> WL_O<216> WL_O<215> WL_O<214> WL_O<213> ++ WL_O<212> WL_O<211> WL_O<210> WL_O<209> WL_O<208> WL_O<207> WL_O<206> ++ WL_O<205> WL_O<204> WL_O<203> WL_O<202> WL_O<201> WL_O<200> WL_O<199> ++ WL_O<198> WL_O<197> WL_O<196> WL_O<195> WL_O<194> WL_O<193> WL_O<192> ++ WL_O<191> WL_O<190> WL_O<189> WL_O<188> WL_O<187> WL_O<186> WL_O<185> ++ WL_O<184> WL_O<183> WL_O<182> WL_O<181> WL_O<180> WL_O<179> WL_O<178> ++ WL_O<177> WL_O<176> WL_O<175> WL_O<174> WL_O<173> WL_O<172> WL_O<171> ++ WL_O<170> WL_O<169> WL_O<168> WL_O<167> WL_O<166> WL_O<165> WL_O<164> ++ WL_O<163> WL_O<162> WL_O<161> WL_O<160> WL_O<159> WL_O<158> WL_O<157> ++ WL_O<156> WL_O<155> WL_O<154> WL_O<153> WL_O<152> WL_O<151> WL_O<150> ++ WL_O<149> WL_O<148> WL_O<147> WL_O<146> WL_O<145> WL_O<144> WL_O<143> ++ WL_O<142> WL_O<141> WL_O<140> WL_O<139> WL_O<138> WL_O<137> WL_O<136> ++ WL_O<135> WL_O<134> WL_O<133> WL_O<132> WL_O<131> WL_O<130> WL_O<129> ++ WL_O<128> WL_O<127> WL_O<126> WL_O<125> WL_O<124> WL_O<123> WL_O<122> ++ WL_O<121> WL_O<120> WL_O<119> WL_O<118> WL_O<117> WL_O<116> WL_O<115> ++ WL_O<114> WL_O<113> WL_O<112> WL_O<111> WL_O<110> WL_O<109> WL_O<108> ++ WL_O<107> WL_O<106> WL_O<105> WL_O<104> WL_O<103> WL_O<102> WL_O<101> ++ WL_O<100> WL_O<99> WL_O<98> WL_O<97> WL_O<96> WL_O<95> WL_O<94> WL_O<93> ++ WL_O<92> WL_O<91> WL_O<90> WL_O<89> WL_O<88> WL_O<87> WL_O<86> WL_O<85> ++ WL_O<84> WL_O<83> WL_O<82> WL_O<81> WL_O<80> WL_O<79> WL_O<78> WL_O<77> ++ WL_O<76> WL_O<75> WL_O<74> WL_O<73> WL_O<72> WL_O<71> WL_O<70> WL_O<69> ++ WL_O<68> WL_O<67> WL_O<66> WL_O<65> WL_O<64> WL_O<63> WL_O<62> WL_O<61> ++ WL_O<60> WL_O<59> WL_O<58> WL_O<57> WL_O<56> WL_O<55> WL_O<54> WL_O<53> ++ WL_O<52> WL_O<51> WL_O<50> WL_O<49> WL_O<48> WL_O<47> WL_O<46> WL_O<45> ++ WL_O<44> WL_O<43> WL_O<42> WL_O<41> WL_O<40> WL_O<39> WL_O<38> WL_O<37> ++ WL_O<36> WL_O<35> WL_O<34> WL_O<33> WL_O<32> WL_O<31> WL_O<30> WL_O<29> ++ WL_O<28> WL_O<27> WL_O<26> WL_O<25> WL_O<24> WL_O<23> WL_O<22> WL_O<21> ++ WL_O<20> WL_O<19> WL_O<18> WL_O<17> WL_O<16> WL_O<15> WL_O<14> WL_O<13> ++ WL_O<12> WL_O<11> WL_O<10> WL_O<9> WL_O<8> WL_O<7> WL_O<6> WL_O<5> WL_O<4> ++ WL_O<3> WL_O<2> WL_O<1> WL_O<0> VDD VSS +XDEC11<4> ADDR_N_I<7> ADDR_N_I<6> CS_I CS04<3> VDD VSS / ++ RM_IHPSG13_1024x16_c2_2P_DEC03 +XDEC11<3> ADDR_N_I<5> ADDR_N_I<4> CS04<3> CS00<15> VDD VSS / ++ RM_IHPSG13_1024x16_c2_2P_DEC03 +XDEC11<2> ADDR_N_I<5> ADDR_N_I<4> CS04<2> CS00<11> VDD VSS / ++ RM_IHPSG13_1024x16_c2_2P_DEC03 +XDEC11<1> ADDR_N_I<5> ADDR_N_I<4> CS04<1> CS00<7> VDD VSS / ++ RM_IHPSG13_1024x16_c2_2P_DEC03 +XDEC11<0> ADDR_N_I<5> ADDR_N_I<4> CS04<0> CS00<3> VDD VSS / ++ RM_IHPSG13_1024x16_c2_2P_DEC03 +XSEL<15> ADDR_N_I<3> ADDR_N_I<2> ADDR_N_I<1> ADDR_N_I<0> CS00<15> ECLK_H<15> ++ ECLK_H<16> ECLK_B<15> ECLK_B<16> WL_O<255> WL_O<254> WL_O<253> WL_O<252> ++ WL_O<251> WL_O<250> WL_O<249> WL_O<248> WL_O<247> WL_O<246> WL_O<245> ++ WL_O<244> WL_O<243> WL_O<242> WL_O<241> WL_O<240> VDD VSS / ++ RM_IHPSG13_1024x16_c2_2P_DEC04 +XSEL<14> ADDR_N_I<3> ADDR_N_I<2> ADDR_N_I<1> ADDR_N_I<0> CS00<14> ECLK_H<14> ++ ECLK_H<15> ECLK_B<14> ECLK_B<15> WL_O<239> WL_O<238> WL_O<237> WL_O<236> ++ WL_O<235> WL_O<234> WL_O<233> WL_O<232> WL_O<231> WL_O<230> WL_O<229> ++ WL_O<228> WL_O<227> WL_O<226> WL_O<225> WL_O<224> VDD VSS / ++ RM_IHPSG13_1024x16_c2_2P_DEC04 +XSEL<13> ADDR_N_I<3> ADDR_N_I<2> ADDR_N_I<1> ADDR_N_I<0> CS00<13> ECLK_H<13> ++ ECLK_H<14> ECLK_B<13> ECLK_B<14> WL_O<223> WL_O<222> WL_O<221> WL_O<220> ++ WL_O<219> WL_O<218> WL_O<217> WL_O<216> WL_O<215> WL_O<214> WL_O<213> ++ WL_O<212> WL_O<211> WL_O<210> WL_O<209> WL_O<208> VDD VSS / ++ RM_IHPSG13_1024x16_c2_2P_DEC04 +XSEL<12> ADDR_N_I<3> ADDR_N_I<2> ADDR_N_I<1> ADDR_N_I<0> CS00<12> ECLK_H<12> ++ ECLK_H<13> ECLK_B<12> ECLK_B<13> WL_O<207> WL_O<206> WL_O<205> WL_O<204> ++ WL_O<203> WL_O<202> WL_O<201> WL_O<200> WL_O<199> WL_O<198> WL_O<197> ++ WL_O<196> WL_O<195> WL_O<194> WL_O<193> WL_O<192> VDD VSS / ++ RM_IHPSG13_1024x16_c2_2P_DEC04 +XSEL<11> ADDR_N_I<3> ADDR_N_I<2> ADDR_N_I<1> ADDR_N_I<0> CS00<11> ECLK_H<11> ++ ECLK_H<12> ECLK_B<11> ECLK_B<12> WL_O<191> WL_O<190> WL_O<189> WL_O<188> ++ WL_O<187> WL_O<186> WL_O<185> WL_O<184> WL_O<183> WL_O<182> WL_O<181> ++ WL_O<180> WL_O<179> WL_O<178> WL_O<177> WL_O<176> VDD VSS / ++ RM_IHPSG13_1024x16_c2_2P_DEC04 +XSEL<10> ADDR_N_I<3> ADDR_N_I<2> ADDR_N_I<1> ADDR_N_I<0> CS00<10> ECLK_H<10> ++ ECLK_H<11> ECLK_B<10> ECLK_B<11> WL_O<175> WL_O<174> WL_O<173> WL_O<172> ++ WL_O<171> WL_O<170> WL_O<169> WL_O<168> WL_O<167> WL_O<166> WL_O<165> ++ WL_O<164> WL_O<163> WL_O<162> WL_O<161> WL_O<160> VDD VSS / ++ RM_IHPSG13_1024x16_c2_2P_DEC04 +XSEL<9> ADDR_N_I<3> ADDR_N_I<2> ADDR_N_I<1> ADDR_N_I<0> CS00<9> ECLK_H<9> ++ ECLK_H<10> ECLK_B<9> ECLK_B<10> WL_O<159> WL_O<158> WL_O<157> WL_O<156> ++ WL_O<155> WL_O<154> WL_O<153> WL_O<152> WL_O<151> WL_O<150> WL_O<149> ++ WL_O<148> WL_O<147> WL_O<146> WL_O<145> WL_O<144> VDD VSS / ++ RM_IHPSG13_1024x16_c2_2P_DEC04 +XSEL<8> ADDR_N_I<3> ADDR_N_I<2> ADDR_N_I<1> ADDR_N_I<0> CS00<8> ECLK_H<8> ++ ECLK_H<9> ECLK_B<8> ECLK_B<9> WL_O<143> WL_O<142> WL_O<141> WL_O<140> ++ WL_O<139> WL_O<138> WL_O<137> WL_O<136> WL_O<135> WL_O<134> WL_O<133> ++ WL_O<132> WL_O<131> WL_O<130> WL_O<129> WL_O<128> VDD VSS / ++ RM_IHPSG13_1024x16_c2_2P_DEC04 +XSEL<7> ADDR_N_I<3> ADDR_N_I<2> ADDR_N_I<1> ADDR_N_I<0> CS00<7> ECLK_H<7> ++ ECLK_H<8> ECLK_B<7> ECLK_B<8> WL_O<127> WL_O<126> WL_O<125> WL_O<124> ++ WL_O<123> WL_O<122> WL_O<121> WL_O<120> WL_O<119> WL_O<118> WL_O<117> ++ WL_O<116> WL_O<115> WL_O<114> WL_O<113> WL_O<112> VDD VSS / ++ RM_IHPSG13_1024x16_c2_2P_DEC04 +XSEL<6> ADDR_N_I<3> ADDR_N_I<2> ADDR_N_I<1> ADDR_N_I<0> CS00<6> ECLK_H<6> ++ ECLK_H<7> ECLK_B<6> ECLK_B<7> WL_O<111> WL_O<110> WL_O<109> WL_O<108> ++ WL_O<107> WL_O<106> WL_O<105> WL_O<104> WL_O<103> WL_O<102> WL_O<101> ++ WL_O<100> WL_O<99> WL_O<98> WL_O<97> WL_O<96> VDD VSS / ++ RM_IHPSG13_1024x16_c2_2P_DEC04 +XSEL<5> ADDR_N_I<3> ADDR_N_I<2> ADDR_N_I<1> ADDR_N_I<0> CS00<5> ECLK_H<5> ++ ECLK_H<6> ECLK_B<5> ECLK_B<6> WL_O<95> WL_O<94> WL_O<93> WL_O<92> WL_O<91> ++ WL_O<90> WL_O<89> WL_O<88> WL_O<87> WL_O<86> WL_O<85> WL_O<84> WL_O<83> ++ WL_O<82> WL_O<81> WL_O<80> VDD VSS / RM_IHPSG13_1024x16_c2_2P_DEC04 +XSEL<4> ADDR_N_I<3> ADDR_N_I<2> ADDR_N_I<1> ADDR_N_I<0> CS00<4> ECLK_H<4> ++ ECLK_H<5> ECLK_B<4> ECLK_B<5> WL_O<79> WL_O<78> WL_O<77> WL_O<76> WL_O<75> ++ WL_O<74> WL_O<73> WL_O<72> WL_O<71> WL_O<70> WL_O<69> WL_O<68> WL_O<67> ++ WL_O<66> WL_O<65> WL_O<64> VDD VSS / RM_IHPSG13_1024x16_c2_2P_DEC04 +XSEL<3> ADDR_N_I<3> ADDR_N_I<2> ADDR_N_I<1> ADDR_N_I<0> CS00<3> ECLK_H<3> ++ ECLK_H<4> ECLK_B<3> ECLK_B<4> WL_O<63> WL_O<62> WL_O<61> WL_O<60> WL_O<59> ++ WL_O<58> WL_O<57> WL_O<56> WL_O<55> WL_O<54> WL_O<53> WL_O<52> WL_O<51> ++ WL_O<50> WL_O<49> WL_O<48> VDD VSS / RM_IHPSG13_1024x16_c2_2P_DEC04 +XSEL<2> ADDR_N_I<3> ADDR_N_I<2> ADDR_N_I<1> ADDR_N_I<0> CS00<2> ECLK_H<2> ++ ECLK_H<3> ECLK_B<2> ECLK_B<3> WL_O<47> WL_O<46> WL_O<45> WL_O<44> WL_O<43> ++ WL_O<42> WL_O<41> WL_O<40> WL_O<39> WL_O<38> WL_O<37> WL_O<36> WL_O<35> ++ WL_O<34> WL_O<33> WL_O<32> VDD VSS / RM_IHPSG13_1024x16_c2_2P_DEC04 +XSEL<1> ADDR_N_I<3> ADDR_N_I<2> ADDR_N_I<1> ADDR_N_I<0> CS00<1> ECLK_H<1> ++ ECLK_H<2> ECLK_B<1> ECLK_B<2> WL_O<31> WL_O<30> WL_O<29> WL_O<28> WL_O<27> ++ WL_O<26> WL_O<25> WL_O<24> WL_O<23> WL_O<22> WL_O<21> WL_O<20> WL_O<19> ++ WL_O<18> WL_O<17> WL_O<16> VDD VSS / RM_IHPSG13_1024x16_c2_2P_DEC04 +XSEL<0> ADDR_N_I<3> ADDR_N_I<2> ADDR_N_I<1> ADDR_N_I<0> CS00<0> ECLK_I ++ ECLK_H<1> ECLK_B<0> ECLK_B<1> WL_O<15> WL_O<14> WL_O<13> WL_O<12> WL_O<11> ++ WL_O<10> WL_O<9> WL_O<8> WL_O<7> WL_O<6> WL_O<5> WL_O<4> WL_O<3> WL_O<2> ++ WL_O<1> WL_O<0> VDD VSS / RM_IHPSG13_1024x16_c2_2P_DEC04 +XDEC10<4> ADDR_N_I<7> ADDR_N_I<6> CS_I CS04<2> VDD VSS / ++ RM_IHPSG13_1024x16_c2_2P_DEC02 +XDEC10<3> ADDR_N_I<5> ADDR_N_I<4> CS04<3> CS00<14> VDD VSS / ++ RM_IHPSG13_1024x16_c2_2P_DEC02 +XDEC10<2> ADDR_N_I<5> ADDR_N_I<4> CS04<2> CS00<10> VDD VSS / ++ RM_IHPSG13_1024x16_c2_2P_DEC02 +XDEC10<1> ADDR_N_I<5> ADDR_N_I<4> CS04<1> CS00<6> VDD VSS / ++ RM_IHPSG13_1024x16_c2_2P_DEC02 +XDEC10<0> ADDR_N_I<5> ADDR_N_I<4> CS04<0> CS00<2> VDD VSS / ++ RM_IHPSG13_1024x16_c2_2P_DEC02 +XL2<132> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<131> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<130> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<129> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<128> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<127> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<126> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<125> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<124> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<123> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<122> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<121> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<120> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<119> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<118> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<117> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<116> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<115> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<114> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<113> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<112> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<111> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<110> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<109> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<108> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<107> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<106> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<105> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<104> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<103> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<102> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<101> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<100> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<99> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<98> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<97> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<96> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<95> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<94> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<93> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<92> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<91> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<90> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<89> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<88> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<87> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<86> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<85> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<84> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<83> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<82> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<81> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<80> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<79> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<78> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<77> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<76> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<75> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<74> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<73> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<72> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<71> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<70> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<69> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<68> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<67> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<66> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<65> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<64> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<63> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<62> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<61> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<60> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<59> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<58> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<57> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<56> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<55> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<54> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<53> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<52> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<51> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<50> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<49> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<48> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<47> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<46> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<45> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<44> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<43> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<42> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<41> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<40> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<39> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<38> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<37> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<36> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<35> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<34> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<33> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<32> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<31> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<30> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<29> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<28> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<27> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<26> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<25> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<24> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<23> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<22> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<21> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<20> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<19> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<18> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<17> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<16> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<15> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<14> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<13> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<12> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<11> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<10> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<9> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<8> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<7> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<6> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<5> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<4> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<3> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<2> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<1> VDD VSS / RSC_IHPSG13_FILLCAP8 +XDEC00<4> ADDR_N_I<7> ADDR_N_I<6> CS_I CS04<0> VDD VSS / ++ RM_IHPSG13_1024x16_c2_2P_DEC00 +XDEC00<3> ADDR_N_I<5> ADDR_N_I<4> CS04<3> CS00<12> VDD VSS / ++ RM_IHPSG13_1024x16_c2_2P_DEC00 +XDEC00<2> ADDR_N_I<5> ADDR_N_I<4> CS04<2> CS00<8> VDD VSS / ++ RM_IHPSG13_1024x16_c2_2P_DEC00 +XDEC00<1> ADDR_N_I<5> ADDR_N_I<4> CS04<1> CS00<4> VDD VSS / ++ RM_IHPSG13_1024x16_c2_2P_DEC00 +XDEC00<0> ADDR_N_I<5> ADDR_N_I<4> CS04<0> CS00<0> VDD VSS / ++ RM_IHPSG13_1024x16_c2_2P_DEC00 +XDEC01<4> ADDR_N_I<7> ADDR_N_I<6> CS_I CS04<1> VDD VSS / ++ RM_IHPSG13_1024x16_c2_2P_DEC01 +XDEC01<3> ADDR_N_I<5> ADDR_N_I<4> CS04<3> CS00<13> VDD VSS / ++ RM_IHPSG13_1024x16_c2_2P_DEC01 +XDEC01<2> ADDR_N_I<5> ADDR_N_I<4> CS04<2> CS00<9> VDD VSS / ++ RM_IHPSG13_1024x16_c2_2P_DEC01 +XDEC01<1> ADDR_N_I<5> ADDR_N_I<4> CS04<1> CS00<5> VDD VSS / ++ RM_IHPSG13_1024x16_c2_2P_DEC01 +XDEC01<0> ADDR_N_I<5> ADDR_N_I<4> CS04<0> CS00<1> VDD VSS / ++ RM_IHPSG13_1024x16_c2_2P_DEC01 +.ENDS +.SUBCKT RM_IHPSG13_1024x16_c2_2P_ROWREG8 ACLK_N_I ADDR_I<7> ADDR_I<6> ADDR_I<5> ADDR_I<4> ++ ADDR_I<3> ADDR_I<2> ADDR_I<1> ADDR_I<0> ADDR_N_O<7> ADDR_N_O<6> ADDR_N_O<5> ++ ADDR_N_O<4> ADDR_N_O<3> ADDR_N_O<2> ADDR_N_O<1> ADDR_N_O<0> BIST_ADDR_I<7> ++ BIST_ADDR_I<6> BIST_ADDR_I<5> BIST_ADDR_I<4> BIST_ADDR_I<3> BIST_ADDR_I<2> ++ BIST_ADDR_I<1> BIST_ADDR_I<0> BIST_EN_I VDD VSS +XINV<7> q_int<7> qn_int<7> VDD VSS / RSC_IHPSG13_CINVX2 +XINV<6> q_int<6> qn_int<6> VDD VSS / RSC_IHPSG13_CINVX2 +XINV<5> q_int<5> qn_int<5> VDD VSS / RSC_IHPSG13_CINVX2 +XINV<4> q_int<4> qn_int<4> VDD VSS / RSC_IHPSG13_CINVX2 +XINV<3> q_int<3> qn_int<3> VDD VSS / RSC_IHPSG13_CINVX2 +XINV<2> q_int<2> qn_int<2> VDD VSS / RSC_IHPSG13_CINVX2 +XINV<1> q_int<1> qn_int<1> VDD VSS / RSC_IHPSG13_CINVX2 +XINV<0> q_int<0> qn_int<0> VDD VSS / RSC_IHPSG13_CINVX2 +XDRV<7> qn_int<7> ADDR_N_O<7> VDD VSS / RSC_IHPSG13_CINVX8 +XDRV<6> qn_int<6> ADDR_N_O<6> VDD VSS / RSC_IHPSG13_CINVX8 +XDRV<5> qn_int<5> ADDR_N_O<5> VDD VSS / RSC_IHPSG13_CINVX8 +XDRV<4> qn_int<4> ADDR_N_O<4> VDD VSS / RSC_IHPSG13_CINVX8 +XDRV<3> qn_int<3> ADDR_N_O<3> VDD VSS / RSC_IHPSG13_CINVX8 +XDRV<2> qn_int<2> ADDR_N_O<2> VDD VSS / RSC_IHPSG13_CINVX8 +XDRV<1> qn_int<1> ADDR_N_O<1> VDD VSS / RSC_IHPSG13_CINVX8 +XDRV<0> qn_int<0> ADDR_N_O<0> VDD VSS / RSC_IHPSG13_CINVX8 +XDFF<7> BIST_EN_I BIST_ADDR_I<7> ACLK_N_I ADDR_I<7> q_int<7> net2<0> VDD ++ VSS / RSC_IHPSG13_DFNQMX2IX1 +XDFF<6> BIST_EN_I BIST_ADDR_I<6> ACLK_N_I ADDR_I<6> q_int<6> net2<1> VDD ++ VSS / RSC_IHPSG13_DFNQMX2IX1 +XDFF<5> BIST_EN_I BIST_ADDR_I<5> ACLK_N_I ADDR_I<5> q_int<5> net2<2> VDD ++ VSS / RSC_IHPSG13_DFNQMX2IX1 +XDFF<4> BIST_EN_I BIST_ADDR_I<4> ACLK_N_I ADDR_I<4> q_int<4> net2<3> VDD ++ VSS / RSC_IHPSG13_DFNQMX2IX1 +XDFF<3> BIST_EN_I BIST_ADDR_I<3> ACLK_N_I ADDR_I<3> q_int<3> net2<4> VDD ++ VSS / RSC_IHPSG13_DFNQMX2IX1 +XDFF<2> BIST_EN_I BIST_ADDR_I<2> ACLK_N_I ADDR_I<2> q_int<2> net2<5> VDD ++ VSS / RSC_IHPSG13_DFNQMX2IX1 +XDFF<1> BIST_EN_I BIST_ADDR_I<1> ACLK_N_I ADDR_I<1> q_int<1> net2<6> VDD ++ VSS / RSC_IHPSG13_DFNQMX2IX1 +XDFF<0> BIST_EN_I BIST_ADDR_I<0> ACLK_N_I ADDR_I<0> q_int<0> net2<7> VDD ++ VSS / RSC_IHPSG13_DFNQMX2IX1 +XI11<4> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI11<3> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI11<2> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI11<1> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI10 VDD VSS / RSC_IHPSG13_FILLCAP4 +.ENDS +.SUBCKT RM_IHPSG13_1024x16_c2_2P_COLDEC4 ACLK_N ADDR<3> ADDR<2> ADDR<1> ADDR<0> ++ ADDR_COL<1> ADDR_COL<0> ADDR_DEC<7> ADDR_DEC<6> ADDR_DEC<5> ADDR_DEC<4> ++ ADDR_DEC<3> ADDR_DEC<2> ADDR_DEC<1> ADDR_DEC<0> BIST_ADDR<3> BIST_ADDR<2> ++ BIST_ADDR<1> BIST_ADDR<0> BIST_EN_I VDD VSS +XI1<7> PADR<0> PADR<1> PADR<2> addr_n<7> VDD VSS / RSC_IHPSG13_NAND3X2 +XI1<6> NADR<0> PADR<1> PADR<2> addr_n<6> VDD VSS / RSC_IHPSG13_NAND3X2 +XI1<5> PADR<0> NADR<1> PADR<2> addr_n<5> VDD VSS / RSC_IHPSG13_NAND3X2 +XI1<4> NADR<0> NADR<1> PADR<2> addr_n<4> VDD VSS / RSC_IHPSG13_NAND3X2 +XI1<3> PADR<0> PADR<1> NADR<2> addr_n<3> VDD VSS / RSC_IHPSG13_NAND3X2 +XI1<2> NADR<0> PADR<1> NADR<2> addr_n<2> VDD VSS / RSC_IHPSG13_NAND3X2 +XI1<1> PADR<0> NADR<1> NADR<2> addr_n<1> VDD VSS / RSC_IHPSG13_NAND3X2 +XI1<0> NADR<0> NADR<1> NADR<2> addr_n<0> VDD VSS / RSC_IHPSG13_NAND3X2 +XDFF<3> BIST_EN_I BIST_ADDR<3> ACLK_N ADDR<3> addr_int net12<0> VDD ++ VSS / RSC_IHPSG13_DFNQMX2IX1 +XDFF<2> BIST_EN_I BIST_ADDR<2> ACLK_N ADDR<2> padr_int<2> net12<1> VDD ++ VSS / RSC_IHPSG13_DFNQMX2IX1 +XDFF<1> BIST_EN_I BIST_ADDR<1> ACLK_N ADDR<1> padr_int<1> net12<2> VDD ++ VSS / RSC_IHPSG13_DFNQMX2IX1 +XDFF<0> BIST_EN_I BIST_ADDR<0> ACLK_N ADDR<0> padr_int<0> net12<3> VDD ++ VSS / RSC_IHPSG13_DFNQMX2IX1 +XI17<4> VDD VSS / RSC_IHPSG13_FILLCAP4 +XI17<3> VDD VSS / RSC_IHPSG13_FILLCAP4 +XI17<2> VDD VSS / RSC_IHPSG13_FILLCAP4 +XI17<1> VDD VSS / RSC_IHPSG13_FILLCAP4 +XI13<2> NADR<2> PADR<2> VDD VSS / RSC_IHPSG13_INVX2 +XI13<1> NADR<1> PADR<1> VDD VSS / RSC_IHPSG13_INVX2 +XI13<0> NADR<0> PADR<0> VDD VSS / RSC_IHPSG13_INVX2 +XI2<7> addr_n<7> ADDR_DEC<7> VDD VSS / RSC_IHPSG13_INVX2 +XI2<6> addr_n<6> ADDR_DEC<6> VDD VSS / RSC_IHPSG13_INVX2 +XI2<5> addr_n<5> ADDR_DEC<5> VDD VSS / RSC_IHPSG13_INVX2 +XI2<4> addr_n<4> ADDR_DEC<4> VDD VSS / RSC_IHPSG13_INVX2 +XI2<3> addr_n<3> ADDR_DEC<3> VDD VSS / RSC_IHPSG13_INVX2 +XI2<2> addr_n<2> ADDR_DEC<2> VDD VSS / RSC_IHPSG13_INVX2 +XI2<1> addr_n<1> ADDR_DEC<1> VDD VSS / RSC_IHPSG13_INVX2 +XI2<0> addr_n<0> ADDR_DEC<0> VDD VSS / RSC_IHPSG13_INVX2 +XI3<2> padr_int<2> NADR<2> VDD VSS / RSC_IHPSG13_INVX2 +XI3<1> padr_int<1> NADR<1> VDD VSS / RSC_IHPSG13_INVX2 +XI3<0> padr_int<0> NADR<0> VDD VSS / RSC_IHPSG13_INVX2 +XI14 addr_int ADDR_COL<0> VDD VSS / RSC_IHPSG13_CBUFX2 +XI16<8> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI16<7> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI16<6> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI16<5> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI16<4> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI16<3> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI16<2> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI16<1> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI15 ADDR_COL<1> VDD VSS / RSC_IHPSG13_TIEL +.ENDS +.SUBCKT RM_IHPSG13_1024x16_c2_2P_COLCTRL4 A_ADDR_COL A_ADDR_DEC<7> A_ADDR_DEC<6> ++ A_ADDR_DEC<5> A_ADDR_DEC<4> A_ADDR_DEC<3> A_ADDR_DEC<2> A_ADDR_DEC<1> ++ A_ADDR_DEC<0> A_BIST_BM_I A_BIST_DW_I A_BIST_EN_I A_BLC<15> A_BLC<14> ++ A_BLC<13> A_BLC<12> A_BLC<11> A_BLC<10> A_BLC<9> A_BLC<8> A_BLC<7> A_BLC<6> ++ A_BLC<5> A_BLC<4> A_BLC<3> A_BLC<2> A_BLC<1> A_BLC<0> A_BLT<15> A_BLT<14> ++ A_BLT<13> A_BLT<12> A_BLT<11> A_BLT<10> A_BLT<9> A_BLT<8> A_BLT<7> A_BLT<6> ++ A_BLT<5> A_BLT<4> A_BLT<3> A_BLT<2> A_BLT<1> A_BLT<0> A_BM_I A_DCLK_B_L ++ A_DCLK_B_R A_DCLK_L A_DCLK_R A_DR_O A_DW_I A_RCLK_B_L A_RCLK_B_R A_RCLK_L ++ A_RCLK_R A_TIEH_O A_WCLK_B_L A_WCLK_B_R A_WCLK_L A_WCLK_R B_ADDR_COL ++ B_ADDR_DEC<7> B_ADDR_DEC<6> B_ADDR_DEC<5> B_ADDR_DEC<4> B_ADDR_DEC<3> ++ B_ADDR_DEC<2> B_ADDR_DEC<1> B_ADDR_DEC<0> B_BIST_BM_I B_BIST_DW_I ++ B_BIST_EN_I B_BLC<15> B_BLC<14> B_BLC<13> B_BLC<12> B_BLC<11> B_BLC<10> ++ B_BLC<9> B_BLC<8> B_BLC<7> B_BLC<6> B_BLC<5> B_BLC<4> B_BLC<3> B_BLC<2> ++ B_BLC<1> B_BLC<0> B_BLT<15> B_BLT<14> B_BLT<13> B_BLT<12> B_BLT<11> ++ B_BLT<10> B_BLT<9> B_BLT<8> B_BLT<7> B_BLT<6> B_BLT<5> B_BLT<4> B_BLT<3> ++ B_BLT<2> B_BLT<1> B_BLT<0> B_BM_I B_DCLK_B_L B_DCLK_B_R B_DCLK_L B_DCLK_R ++ B_DR_O B_DW_I B_RCLK_B_L B_RCLK_B_R B_RCLK_L B_RCLK_R B_TIEH_O B_WCLK_B_L ++ B_WCLK_B_R B_WCLK_L B_WCLK_R VDD VSS +XB_I80 B_RCLK_B_L B_WCLK_B_L net041 VDD VSS / RSC_IHPSG13_AND2X2 +XA_I80 A_RCLK_B_L A_WCLK_B_L net21 VDD VSS / RSC_IHPSG13_AND2X2 +XB_I76 B_DI_N B_DO_WRITE_P B_WR_ZERO VDD VSS / RSC_IHPSG13_AND2X4 +XB_I75 B_DI_R B_DO_WRITE_P B_WR_ONE VDD VSS / RSC_IHPSG13_AND2X4 +XA_I76 A_DI_N A_DO_WRITE_P A_WR_ZERO VDD VSS / RSC_IHPSG13_AND2X4 +XA_I75 A_DI_R A_DO_WRITE_P A_WR_ONE VDD VSS / RSC_IHPSG13_AND2X4 +XI_FILL4<26> VDD VSS / RSC_IHPSG13_FILLCAP4 +XI_FILL4<25> VDD VSS / RSC_IHPSG13_FILLCAP4 +XI_FILL4<24> VDD VSS / RSC_IHPSG13_FILLCAP4 +XI_FILL4<23> VDD VSS / RSC_IHPSG13_FILLCAP4 +XI_FILL4<22> VDD VSS / RSC_IHPSG13_FILLCAP4 +XI_FILL4<21> VDD VSS / RSC_IHPSG13_FILLCAP4 +XI_FILL4<20> VDD VSS / RSC_IHPSG13_FILLCAP4 +XI_FILL4<19> VDD VSS / RSC_IHPSG13_FILLCAP4 +XI_FILL4<18> VDD VSS / RSC_IHPSG13_FILLCAP4 +XI_FILL4<17> VDD VSS / RSC_IHPSG13_FILLCAP4 +XI_FILL4<16> VDD VSS / RSC_IHPSG13_FILLCAP4 +XI_FILL4<15> VDD VSS / RSC_IHPSG13_FILLCAP4 +XI_FILL4<14> VDD VSS / RSC_IHPSG13_FILLCAP4 +XI_FILL4<13> VDD VSS / RSC_IHPSG13_FILLCAP4 +XI_FILL4<12> VDD VSS / RSC_IHPSG13_FILLCAP4 +XI_FILL4<11> VDD VSS / RSC_IHPSG13_FILLCAP4 +XI_FILL4<10> VDD VSS / RSC_IHPSG13_FILLCAP4 +XI_FILL4<9> VDD VSS / RSC_IHPSG13_FILLCAP4 +XI_FILL4<8> VDD VSS / RSC_IHPSG13_FILLCAP4 +XI_FILL4<7> VDD VSS / RSC_IHPSG13_FILLCAP4 +XI_FILL4<6> VDD VSS / RSC_IHPSG13_FILLCAP4 +XI_FILL4<5> VDD VSS / RSC_IHPSG13_FILLCAP4 +XI_FILL4<4> VDD VSS / RSC_IHPSG13_FILLCAP4 +XI_FILL4<3> VDD VSS / RSC_IHPSG13_FILLCAP4 +XI_FILL4<2> VDD VSS / RSC_IHPSG13_FILLCAP4 +XI_FILL4<1> VDD VSS / RSC_IHPSG13_FILLCAP4 +XB_I69 B_DCLK_L B_DCLK_B_L VDD VSS / RSC_IHPSG13_CINVX4 +XB_I50 B_WCLK_L B_WCLK_B_L VDD VSS / RSC_IHPSG13_CINVX4 +XB_EBUF B_RCLK_L B_RCLK_B_L VDD VSS / RSC_IHPSG13_CINVX4 +XB_INV<1> B_N0 B_P0 VDD VSS / RSC_IHPSG13_CINVX4 +XB_INV<0> B_ADDR_COL B_N0 VDD VSS / RSC_IHPSG13_CINVX4 +XA_I69 A_DCLK_L A_DCLK_B_L VDD VSS / RSC_IHPSG13_CINVX4 +XA_I50 A_WCLK_L A_WCLK_B_L VDD VSS / RSC_IHPSG13_CINVX4 +XA_EBUF A_RCLK_L A_RCLK_B_L VDD VSS / RSC_IHPSG13_CINVX4 +XA_INV<1> A_N0 A_P0 VDD VSS / RSC_IHPSG13_CINVX4 +XA_INV<0> A_ADDR_COL A_N0 VDD VSS / RSC_IHPSG13_CINVX4 +XB_I81<1> net041 B_PRE_N VDD VSS / RSC_IHPSG13_CINVX4_WN +XB_I81<0> net041 B_PRE_N VDD VSS / RSC_IHPSG13_CINVX4_WN +XA_I81<1> net21 A_PRE_N VDD VSS / RSC_IHPSG13_CINVX4_WN +XA_I81<0> net21 A_PRE_N VDD VSS / RSC_IHPSG13_CINVX4_WN +XA_R2 A_RCLK_L A_RCLK_R / RSC_IHPSG13_MET3RES +XA_I87 A_WCLK_L A_WCLK_R / RSC_IHPSG13_MET3RES +XA_I88 A_DCLK_L A_DCLK_R / RSC_IHPSG13_MET3RES +XA_I89 A_DCLK_B_L A_DCLK_B_R / RSC_IHPSG13_MET3RES +XA_I90 A_WCLK_B_L A_WCLK_B_R / RSC_IHPSG13_MET3RES +XA_I91 A_RCLK_B_L A_RCLK_B_R / RSC_IHPSG13_MET3RES +XB_R2 B_RCLK_L B_RCLK_R / RSC_IHPSG13_MET3RES +XB_I87 B_WCLK_L B_WCLK_R / RSC_IHPSG13_MET3RES +XB_I88 B_DCLK_L B_DCLK_R / RSC_IHPSG13_MET3RES +XB_I89 B_DCLK_B_L B_DCLK_B_R / RSC_IHPSG13_MET3RES +XB_I90 B_WCLK_B_L B_WCLK_B_R / RSC_IHPSG13_MET3RES +XB_I91 B_RCLK_B_L B_RCLK_B_R / RSC_IHPSG13_MET3RES +XA_ISENSE A_SAE A_BLC_SEL A_BLT_SEL net19 net20 VDD VSS / ++ RSC_IHPSG13_DFPQD_MSAFFX2 +XB_ISENSE B_SAE B_BLC_SEL B_BLT_SEL net037 net038 VDD VSS / ++ RSC_IHPSG13_DFPQD_MSAFFX2 +XAB_BLMUX<3> A_BLC<15> A_BLC<14> A_BLC<13> A_BLC<12> A_BLC_SEL A_BLT<15> ++ A_BLT<14> A_BLT<13> A_BLT<12> A_BLT_SEL A_PRE_N A_SEL_P<15> A_SEL_P<14> ++ A_SEL_P<13> A_SEL_P<12> A_WR_ONE A_WR_ZERO B_BLC<15> B_BLC<14> B_BLC<13> ++ B_BLC<12> B_BLC_SEL B_BLT<15> B_BLT<14> B_BLT<13> B_BLT<12> B_BLT_SEL ++ B_PRE_N B_SEL_P<15> B_SEL_P<14> B_SEL_P<13> B_SEL_P<12> B_WR_ONE B_WR_ZERO ++ VDD VSS / RM_IHPSG13_1024x16_c2_2P_BLDRV +XAB_BLMUX<2> A_BLC<11> A_BLC<10> A_BLC<9> A_BLC<8> A_BLC_SEL A_BLT<11> ++ A_BLT<10> A_BLT<9> A_BLT<8> A_BLT_SEL A_PRE_N A_SEL_P<11> A_SEL_P<10> ++ A_SEL_P<9> A_SEL_P<8> A_WR_ONE A_WR_ZERO B_BLC<11> B_BLC<10> B_BLC<9> ++ B_BLC<8> B_BLC_SEL B_BLT<11> B_BLT<10> B_BLT<9> B_BLT<8> B_BLT_SEL B_PRE_N ++ B_SEL_P<11> B_SEL_P<10> B_SEL_P<9> B_SEL_P<8> B_WR_ONE B_WR_ZERO VDD ++ VSS / RM_IHPSG13_1024x16_c2_2P_BLDRV +XAB_BLMUX<1> A_BLC<7> A_BLC<6> A_BLC<5> A_BLC<4> A_BLC_SEL A_BLT<7> A_BLT<6> ++ A_BLT<5> A_BLT<4> A_BLT_SEL A_PRE_N A_SEL_P<7> A_SEL_P<6> A_SEL_P<5> ++ A_SEL_P<4> A_WR_ONE A_WR_ZERO B_BLC<7> B_BLC<6> B_BLC<5> B_BLC<4> B_BLC_SEL ++ B_BLT<7> B_BLT<6> B_BLT<5> B_BLT<4> B_BLT_SEL B_PRE_N B_SEL_P<7> B_SEL_P<6> ++ B_SEL_P<5> B_SEL_P<4> B_WR_ONE B_WR_ZERO VDD VSS / ++ RM_IHPSG13_1024x16_c2_2P_BLDRV +XAB_BLMUX<0> A_BLC<3> A_BLC<2> A_BLC<1> A_BLC<0> A_BLC_SEL A_BLT<3> A_BLT<2> ++ A_BLT<1> A_BLT<0> A_BLT_SEL A_PRE_N A_SEL_P<3> A_SEL_P<2> A_SEL_P<1> ++ A_SEL_P<0> A_WR_ONE A_WR_ZERO B_BLC<3> B_BLC<2> B_BLC<1> B_BLC<0> B_BLC_SEL ++ B_BLT<3> B_BLT<2> B_BLT<1> B_BLT<0> B_BLT_SEL B_PRE_N B_SEL_P<3> B_SEL_P<2> ++ B_SEL_P<1> B_SEL_P<0> B_WR_ONE B_WR_ZERO VDD VSS / ++ RM_IHPSG13_1024x16_c2_2P_BLDRV +XA_I51 net19 A_DR_O VDD VSS / RSC_IHPSG13_INVX4 +XB_I51 net037 B_DR_O VDD VSS / RSC_IHPSG13_INVX4 +XA_I78 A_RCLK_B_L A_SAE VDD VSS / RSC_IHPSG13_CBUFX2 +XB_I78 B_RCLK_B_L B_SAE VDD VSS / RSC_IHPSG13_CBUFX2 +XA_DREG A_BIST_EN_I A_BIST_DW_I A_DCLK_B_L A_DW_I A_DI_R net22 VDD VSS ++ / RSC_IHPSG13_DFNQMX2IX1 +XB_DREG B_BIST_EN_I B_BIST_DW_I B_DCLK_B_L B_DW_I B_DI_R net046 VDD ++ VSS / RSC_IHPSG13_DFNQMX2IX1 +XB_BREG B_BIST_EN_I B_BIST_BM_I B_DCLK_B_L B_BM_I B_BM_R net045 VDD ++ VSS / RSC_IHPSG13_DFNQMX2IX1 +XA_BREG A_BIST_EN_I A_BIST_BM_I A_DCLK_B_L A_BM_I A_BM_R net24 VDD VSS ++ / RSC_IHPSG13_DFNQMX2IX1 +XA_DEC3INV<15> net23<0> A_SEL_P<15> VDD VSS / RSC_IHPSG13_INVX2 +XA_DEC3INV<14> net23<1> A_SEL_P<14> VDD VSS / RSC_IHPSG13_INVX2 +XA_DEC3INV<13> net23<2> A_SEL_P<13> VDD VSS / RSC_IHPSG13_INVX2 +XA_DEC3INV<12> net23<3> A_SEL_P<12> VDD VSS / RSC_IHPSG13_INVX2 +XA_DEC3INV<11> net23<4> A_SEL_P<11> VDD VSS / RSC_IHPSG13_INVX2 +XA_DEC3INV<10> net23<5> A_SEL_P<10> VDD VSS / RSC_IHPSG13_INVX2 +XA_DEC3INV<9> net23<6> A_SEL_P<9> VDD VSS / RSC_IHPSG13_INVX2 +XA_DEC3INV<8> net23<7> A_SEL_P<8> VDD VSS / RSC_IHPSG13_INVX2 +XA_DEC3INV<7> net23<8> A_SEL_P<7> VDD VSS / RSC_IHPSG13_INVX2 +XA_DEC3INV<6> net23<9> A_SEL_P<6> VDD VSS / RSC_IHPSG13_INVX2 +XA_DEC3INV<5> net23<10> A_SEL_P<5> VDD VSS / RSC_IHPSG13_INVX2 +XA_DEC3INV<4> net23<11> A_SEL_P<4> VDD VSS / RSC_IHPSG13_INVX2 +XA_DEC3INV<3> net23<12> A_SEL_P<3> VDD VSS / RSC_IHPSG13_INVX2 +XA_DEC3INV<2> net23<13> A_SEL_P<2> VDD VSS / RSC_IHPSG13_INVX2 +XA_DEC3INV<1> net23<14> A_SEL_P<1> VDD VSS / RSC_IHPSG13_INVX2 +XA_DEC3INV<0> net23<15> A_SEL_P<0> VDD VSS / RSC_IHPSG13_INVX2 +XA_I83 A_BM_R A_BM_N VDD VSS / RSC_IHPSG13_INVX2 +XA_I49 A_DI_R A_DI_N VDD VSS / RSC_IHPSG13_INVX2 +XB_DEC3INV<15> net044<0> B_SEL_P<15> VDD VSS / RSC_IHPSG13_INVX2 +XB_DEC3INV<14> net044<1> B_SEL_P<14> VDD VSS / RSC_IHPSG13_INVX2 +XB_DEC3INV<13> net044<2> B_SEL_P<13> VDD VSS / RSC_IHPSG13_INVX2 +XB_DEC3INV<12> net044<3> B_SEL_P<12> VDD VSS / RSC_IHPSG13_INVX2 +XB_DEC3INV<11> net044<4> B_SEL_P<11> VDD VSS / RSC_IHPSG13_INVX2 +XB_DEC3INV<10> net044<5> B_SEL_P<10> VDD VSS / RSC_IHPSG13_INVX2 +XB_DEC3INV<9> net044<6> B_SEL_P<9> VDD VSS / RSC_IHPSG13_INVX2 +XB_DEC3INV<8> net044<7> B_SEL_P<8> VDD VSS / RSC_IHPSG13_INVX2 +XB_DEC3INV<7> net044<8> B_SEL_P<7> VDD VSS / RSC_IHPSG13_INVX2 +XB_DEC3INV<6> net044<9> B_SEL_P<6> VDD VSS / RSC_IHPSG13_INVX2 +XB_DEC3INV<5> net044<10> B_SEL_P<5> VDD VSS / RSC_IHPSG13_INVX2 +XB_DEC3INV<4> net044<11> B_SEL_P<4> VDD VSS / RSC_IHPSG13_INVX2 +XB_DEC3INV<3> net044<12> B_SEL_P<3> VDD VSS / RSC_IHPSG13_INVX2 +XB_DEC3INV<2> net044<13> B_SEL_P<2> VDD VSS / RSC_IHPSG13_INVX2 +XB_DEC3INV<1> net044<14> B_SEL_P<1> VDD VSS / RSC_IHPSG13_INVX2 +XB_DEC3INV<0> net044<15> B_SEL_P<0> VDD VSS / RSC_IHPSG13_INVX2 +XB_I83 B_BM_R B_BM_N VDD VSS / RSC_IHPSG13_INVX2 +XB_I49 B_DI_R B_DI_N VDD VSS / RSC_IHPSG13_INVX2 +XI_FILL8<20> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI_FILL8<19> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI_FILL8<18> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI_FILL8<17> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI_FILL8<16> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI_FILL8<15> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI_FILL8<14> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI_FILL8<13> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI_FILL8<12> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI_FILL8<11> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI_FILL8<10> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI_FILL8<9> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI_FILL8<8> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI_FILL8<7> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI_FILL8<6> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI_FILL8<5> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI_FILL8<4> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI_FILL8<3> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI_FILL8<2> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI_FILL8<1> VDD VSS / RSC_IHPSG13_FILLCAP8 +XA_I44 A_BM_N A_WCLK_B_L A_DO_WRITE_P VDD VSS / RSC_IHPSG13_NOR2X2 +XB_I44 B_BM_N B_WCLK_B_L B_DO_WRITE_P VDD VSS / RSC_IHPSG13_NOR2X2 +XA_DEC3<15> A_P0 A_ADDR_DEC<7> net23<0> VDD VSS / RSC_IHPSG13_NAND2X2 +XA_DEC3<14> A_P0 A_ADDR_DEC<6> net23<1> VDD VSS / RSC_IHPSG13_NAND2X2 +XA_DEC3<13> A_P0 A_ADDR_DEC<5> net23<2> VDD VSS / RSC_IHPSG13_NAND2X2 +XA_DEC3<12> A_P0 A_ADDR_DEC<4> net23<3> VDD VSS / RSC_IHPSG13_NAND2X2 +XA_DEC3<11> A_P0 A_ADDR_DEC<3> net23<4> VDD VSS / RSC_IHPSG13_NAND2X2 +XA_DEC3<10> A_P0 A_ADDR_DEC<2> net23<5> VDD VSS / RSC_IHPSG13_NAND2X2 +XA_DEC3<9> A_P0 A_ADDR_DEC<1> net23<6> VDD VSS / RSC_IHPSG13_NAND2X2 +XA_DEC3<8> A_P0 A_ADDR_DEC<0> net23<7> VDD VSS / RSC_IHPSG13_NAND2X2 +XA_DEC3<7> A_N0 A_ADDR_DEC<7> net23<8> VDD VSS / RSC_IHPSG13_NAND2X2 +XA_DEC3<6> A_N0 A_ADDR_DEC<6> net23<9> VDD VSS / RSC_IHPSG13_NAND2X2 +XA_DEC3<5> A_N0 A_ADDR_DEC<5> net23<10> VDD VSS / RSC_IHPSG13_NAND2X2 +XA_DEC3<4> A_N0 A_ADDR_DEC<4> net23<11> VDD VSS / RSC_IHPSG13_NAND2X2 +XA_DEC3<3> A_N0 A_ADDR_DEC<3> net23<12> VDD VSS / RSC_IHPSG13_NAND2X2 +XA_DEC3<2> A_N0 A_ADDR_DEC<2> net23<13> VDD VSS / RSC_IHPSG13_NAND2X2 +XA_DEC3<1> A_N0 A_ADDR_DEC<1> net23<14> VDD VSS / RSC_IHPSG13_NAND2X2 +XA_DEC3<0> A_N0 A_ADDR_DEC<0> net23<15> VDD VSS / RSC_IHPSG13_NAND2X2 +XB_DEC3<15> B_P0 B_ADDR_DEC<7> net044<0> VDD VSS / RSC_IHPSG13_NAND2X2 +XB_DEC3<14> B_P0 B_ADDR_DEC<6> net044<1> VDD VSS / RSC_IHPSG13_NAND2X2 +XB_DEC3<13> B_P0 B_ADDR_DEC<5> net044<2> VDD VSS / RSC_IHPSG13_NAND2X2 +XB_DEC3<12> B_P0 B_ADDR_DEC<4> net044<3> VDD VSS / RSC_IHPSG13_NAND2X2 +XB_DEC3<11> B_P0 B_ADDR_DEC<3> net044<4> VDD VSS / RSC_IHPSG13_NAND2X2 +XB_DEC3<10> B_P0 B_ADDR_DEC<2> net044<5> VDD VSS / RSC_IHPSG13_NAND2X2 +XB_DEC3<9> B_P0 B_ADDR_DEC<1> net044<6> VDD VSS / RSC_IHPSG13_NAND2X2 +XB_DEC3<8> B_P0 B_ADDR_DEC<0> net044<7> VDD VSS / RSC_IHPSG13_NAND2X2 +XB_DEC3<7> B_N0 B_ADDR_DEC<7> net044<8> VDD VSS / RSC_IHPSG13_NAND2X2 +XB_DEC3<6> B_N0 B_ADDR_DEC<6> net044<9> VDD VSS / RSC_IHPSG13_NAND2X2 +XB_DEC3<5> B_N0 B_ADDR_DEC<5> net044<10> VDD VSS / RSC_IHPSG13_NAND2X2 +XB_DEC3<4> B_N0 B_ADDR_DEC<4> net044<11> VDD VSS / RSC_IHPSG13_NAND2X2 +XB_DEC3<3> B_N0 B_ADDR_DEC<3> net044<12> VDD VSS / RSC_IHPSG13_NAND2X2 +XB_DEC3<2> B_N0 B_ADDR_DEC<2> net044<13> VDD VSS / RSC_IHPSG13_NAND2X2 +XB_DEC3<1> B_N0 B_ADDR_DEC<1> net044<14> VDD VSS / RSC_IHPSG13_NAND2X2 +XB_DEC3<0> B_N0 B_ADDR_DEC<0> net044<15> VDD VSS / RSC_IHPSG13_NAND2X2 +XB_BM_TIEH B_TIEH_O VDD VSS / RSC_IHPSG13_TIEH +XA_BM_TIEH A_TIEH_O VDD VSS / RSC_IHPSG13_TIEH +.ENDS + + +.SUBCKT RM_IHPSG13_1024x16_c2_2P_ROWDEC5 ADDR_N_I<4> ADDR_N_I<3> ADDR_N_I<2> ADDR_N_I<1> ++ ADDR_N_I<0> CS_I ECLK_I WL_O<31> WL_O<30> WL_O<29> WL_O<28> WL_O<27> ++ WL_O<26> WL_O<25> WL_O<24> WL_O<23> WL_O<22> WL_O<21> WL_O<20> WL_O<19> ++ WL_O<18> WL_O<17> WL_O<16> WL_O<15> WL_O<14> WL_O<13> WL_O<12> WL_O<11> ++ WL_O<10> WL_O<9> WL_O<8> WL_O<7> WL_O<6> WL_O<5> WL_O<4> WL_O<3> WL_O<2> ++ WL_O<1> WL_O<0> VDD VSS +XDEC00 ADDR_N_I<5> ADDR_N_I<4> CS_I CS00<0> VDD VSS / ++ RM_IHPSG13_1024x16_c2_2P_DEC00 +XSEL<1> ADDR_N_I<3> ADDR_N_I<2> ADDR_N_I<1> ADDR_N_I<0> CS00<1> ECLK_H<1> ++ ECLK_H<2> ECLK_B<1> ECLK_B<2> WL_O<31> WL_O<30> WL_O<29> WL_O<28> WL_O<27> ++ WL_O<26> WL_O<25> WL_O<24> WL_O<23> WL_O<22> WL_O<21> WL_O<20> WL_O<19> ++ WL_O<18> WL_O<17> WL_O<16> VDD VSS / RM_IHPSG13_1024x16_c2_2P_DEC04 +XSEL<0> ADDR_N_I<3> ADDR_N_I<2> ADDR_N_I<1> ADDR_N_I<0> CS00<0> ECLK_I ++ ECLK_H<1> ECLK_B<0> ECLK_B<1> WL_O<15> WL_O<14> WL_O<13> WL_O<12> WL_O<11> ++ WL_O<10> WL_O<9> WL_O<8> WL_O<7> WL_O<6> WL_O<5> WL_O<4> WL_O<3> WL_O<2> ++ WL_O<1> WL_O<0> VDD VSS / RM_IHPSG13_1024x16_c2_2P_DEC04 +XDEC01 ADDR_N_I<5> ADDR_N_I<4> CS_I CS00<1> VDD VSS / ++ RM_IHPSG13_1024x16_c2_2P_DEC01 +XL2<18> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<17> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<16> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<15> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<14> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<13> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<12> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<11> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<10> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<9> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<8> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<7> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<6> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<5> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<4> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<3> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<2> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<1> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI0 ADDR_N_I<5> VDD VSS / RSC_IHPSG13_TIEL +.ENDS +.SUBCKT RM_IHPSG13_1024x16_c2_2P_ROWREG5 ACLK_N_I ADDR_I<4> ADDR_I<3> ADDR_I<2> ADDR_I<1> ++ ADDR_I<0> ADDR_N_O<4> ADDR_N_O<3> ADDR_N_O<2> ADDR_N_O<1> ADDR_N_O<0> ++ BIST_ADDR_I<4> BIST_ADDR_I<3> BIST_ADDR_I<2> BIST_ADDR_I<1> BIST_ADDR_I<0> ++ BIST_EN_I VDD VSS +XINV<4> q_int<4> qn_int<4> VDD VSS / RSC_IHPSG13_CINVX2 +XINV<3> q_int<3> qn_int<3> VDD VSS / RSC_IHPSG13_CINVX2 +XINV<2> q_int<2> qn_int<2> VDD VSS / RSC_IHPSG13_CINVX2 +XINV<1> q_int<1> qn_int<1> VDD VSS / RSC_IHPSG13_CINVX2 +XINV<0> q_int<0> qn_int<0> VDD VSS / RSC_IHPSG13_CINVX2 +XDRV<4> qn_int<4> ADDR_N_O<4> VDD VSS / RSC_IHPSG13_CINVX8 +XDRV<3> qn_int<3> ADDR_N_O<3> VDD VSS / RSC_IHPSG13_CINVX8 +XDRV<2> qn_int<2> ADDR_N_O<2> VDD VSS / RSC_IHPSG13_CINVX8 +XDRV<1> qn_int<1> ADDR_N_O<1> VDD VSS / RSC_IHPSG13_CINVX8 +XDRV<0> qn_int<0> ADDR_N_O<0> VDD VSS / RSC_IHPSG13_CINVX8 +XDFF<4> BIST_EN_I BIST_ADDR_I<4> ACLK_N_I ADDR_I<4> q_int<4> net2<0> VDD ++ VSS / RSC_IHPSG13_DFNQMX2IX1 +XDFF<3> BIST_EN_I BIST_ADDR_I<3> ACLK_N_I ADDR_I<3> q_int<3> net2<1> VDD ++ VSS / RSC_IHPSG13_DFNQMX2IX1 +XDFF<2> BIST_EN_I BIST_ADDR_I<2> ACLK_N_I ADDR_I<2> q_int<2> net2<2> VDD ++ VSS / RSC_IHPSG13_DFNQMX2IX1 +XDFF<1> BIST_EN_I BIST_ADDR_I<1> ACLK_N_I ADDR_I<1> q_int<1> net2<3> VDD ++ VSS / RSC_IHPSG13_DFNQMX2IX1 +XDFF<0> BIST_EN_I BIST_ADDR_I<0> ACLK_N_I ADDR_I<0> q_int<0> net2<4> VDD ++ VSS / RSC_IHPSG13_DFNQMX2IX1 +XI11<16> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI11<15> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI11<14> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI11<13> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI11<12> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI11<11> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI11<10> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI11<9> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI11<8> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI11<7> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI11<6> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI11<5> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI11<4> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI11<3> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI11<2> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI11<1> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI12<3> VDD VSS / RSC_IHPSG13_FILLCAP4 +XI12<2> VDD VSS / RSC_IHPSG13_FILLCAP4 +XI12<1> VDD VSS / RSC_IHPSG13_FILLCAP4 +XI12<0> VDD VSS / RSC_IHPSG13_FILLCAP4 +.ENDS + + +.SUBCKT RM_IHPSG13_1024x16_c2_2P_COLDEC3 ACLK_N ADDR<2> ADDR<1> ADDR<0> ADDR_COL<1> ++ ADDR_COL<0> ADDR_DEC<7> ADDR_DEC<6> ADDR_DEC<5> ADDR_DEC<4> ADDR_DEC<3> ++ ADDR_DEC<2> ADDR_DEC<1> ADDR_DEC<0> BIST_ADDR<2> BIST_ADDR<1> BIST_ADDR<0> ++ BIST_EN_I VDD VSS +XI1<7> PADR<0> PADR<1> PADR<2> addr_n<7> VDD VSS / RSC_IHPSG13_NAND3X2 +XI1<6> NADR<0> PADR<1> PADR<2> addr_n<6> VDD VSS / RSC_IHPSG13_NAND3X2 +XI1<5> PADR<0> NADR<1> PADR<2> addr_n<5> VDD VSS / RSC_IHPSG13_NAND3X2 +XI1<4> NADR<0> NADR<1> PADR<2> addr_n<4> VDD VSS / RSC_IHPSG13_NAND3X2 +XI1<3> PADR<0> PADR<1> NADR<2> addr_n<3> VDD VSS / RSC_IHPSG13_NAND3X2 +XI1<2> NADR<0> PADR<1> NADR<2> addr_n<2> VDD VSS / RSC_IHPSG13_NAND3X2 +XI1<1> PADR<0> NADR<1> NADR<2> addr_n<1> VDD VSS / RSC_IHPSG13_NAND3X2 +XI1<0> NADR<0> NADR<1> NADR<2> addr_n<0> VDD VSS / RSC_IHPSG13_NAND3X2 +XDFF<2> BIST_EN_I BIST_ADDR<2> ACLK_N ADDR<2> padr_int<2> net13<0> VDD ++ VSS / RSC_IHPSG13_DFNQMX2IX1 +XDFF<1> BIST_EN_I BIST_ADDR<1> ACLK_N ADDR<1> padr_int<1> net13<1> VDD ++ VSS / RSC_IHPSG13_DFNQMX2IX1 +XDFF<0> BIST_EN_I BIST_ADDR<0> ACLK_N ADDR<0> padr_int<0> net13<2> VDD ++ VSS / RSC_IHPSG13_DFNQMX2IX1 +XI15<1> ADDR_COL<1> VDD VSS / RSC_IHPSG13_TIEL +XI15<0> ADDR_COL<0> VDD VSS / RSC_IHPSG13_TIEL +XI13<2> NADR<2> PADR<2> VDD VSS / RSC_IHPSG13_INVX2 +XI13<1> NADR<1> PADR<1> VDD VSS / RSC_IHPSG13_INVX2 +XI13<0> NADR<0> PADR<0> VDD VSS / RSC_IHPSG13_INVX2 +XI3<2> padr_int<2> NADR<2> VDD VSS / RSC_IHPSG13_INVX2 +XI3<1> padr_int<1> NADR<1> VDD VSS / RSC_IHPSG13_INVX2 +XI3<0> padr_int<0> NADR<0> VDD VSS / RSC_IHPSG13_INVX2 +XI2<7> addr_n<7> ADDR_DEC<7> VDD VSS / RSC_IHPSG13_INVX2 +XI2<6> addr_n<6> ADDR_DEC<6> VDD VSS / RSC_IHPSG13_INVX2 +XI2<5> addr_n<5> ADDR_DEC<5> VDD VSS / RSC_IHPSG13_INVX2 +XI2<4> addr_n<4> ADDR_DEC<4> VDD VSS / RSC_IHPSG13_INVX2 +XI2<3> addr_n<3> ADDR_DEC<3> VDD VSS / RSC_IHPSG13_INVX2 +XI2<2> addr_n<2> ADDR_DEC<2> VDD VSS / RSC_IHPSG13_INVX2 +XI2<1> addr_n<1> ADDR_DEC<1> VDD VSS / RSC_IHPSG13_INVX2 +XI2<0> addr_n<0> ADDR_DEC<0> VDD VSS / RSC_IHPSG13_INVX2 +XI17<4> VDD VSS / RSC_IHPSG13_FILLCAP4 +XI17<3> VDD VSS / RSC_IHPSG13_FILLCAP4 +XI17<2> VDD VSS / RSC_IHPSG13_FILLCAP4 +XI17<1> VDD VSS / RSC_IHPSG13_FILLCAP4 +XI16<11> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI16<10> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI16<9> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI16<8> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI16<7> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI16<6> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI16<5> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI16<4> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI16<3> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI16<2> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI16<1> VDD VSS / RSC_IHPSG13_FILLCAP8 +.ENDS +.SUBCKT RSC_IHPSG13_DFPQD_MSAFFX2P CP DN DP QN QP VDD VSS +XI_AMP CP DN DP QN QP VDD VSS / RSC_IHPSG13_DFPQD_MSAFFX2 +.ENDS +.SUBCKT RM_IHPSG13_1024x16_c2_2P_COLCTRL3 A_ADDR_DEC<7> A_ADDR_DEC<6> A_ADDR_DEC<5> ++ A_ADDR_DEC<4> A_ADDR_DEC<3> A_ADDR_DEC<2> A_ADDR_DEC<1> A_ADDR_DEC<0> ++ A_BIST_BM_I A_BIST_DW_I A_BIST_EN_I A_BLC<7> A_BLC<6> A_BLC<5> A_BLC<4> ++ A_BLC<3> A_BLC<2> A_BLC<1> A_BLC<0> A_BLT<7> A_BLT<6> A_BLT<5> A_BLT<4> ++ A_BLT<3> A_BLT<2> A_BLT<1> A_BLT<0> A_BM_I A_DCLK_B_L A_DCLK_B_R A_DCLK_L ++ A_DCLK_R A_DR_O A_DW_I A_RCLK_B_L A_RCLK_B_R A_RCLK_L A_RCLK_R A_TIEH_O ++ A_WCLK_B_L A_WCLK_B_R A_WCLK_L A_WCLK_R B_ADDR_DEC<7> B_ADDR_DEC<6> ++ B_ADDR_DEC<5> B_ADDR_DEC<4> B_ADDR_DEC<3> B_ADDR_DEC<2> B_ADDR_DEC<1> ++ B_ADDR_DEC<0> B_BIST_BM_I B_BIST_DW_I B_BIST_EN_I B_BLC<7> B_BLC<6> B_BLC<5> ++ B_BLC<4> B_BLC<3> B_BLC<2> B_BLC<1> B_BLC<0> B_BLT<7> B_BLT<6> B_BLT<5> ++ B_BLT<4> B_BLT<3> B_BLT<2> B_BLT<1> B_BLT<0> B_BM_I B_DCLK_B_L B_DCLK_B_R ++ B_DCLK_L B_DCLK_R B_DR_O B_DW_I B_RCLK_B_L B_RCLK_B_R B_RCLK_L B_RCLK_R ++ B_TIEH_O B_WCLK_B_L B_WCLK_B_R B_WCLK_L B_WCLK_R VDD VSS +XB_DREG B_BIST_EN_I B_BIST_DW_I B_DCLK_B_L B_DW_I B_DI_R net044 VDD ++ VSS / RSC_IHPSG13_DFNQMX2IX1 +XB_BREG B_BIST_EN_I B_BIST_BM_I B_DCLK_B_L B_BM_I B_BM_R net043 VDD ++ VSS / RSC_IHPSG13_DFNQMX2IX1 +XA_DREG A_BIST_EN_I A_BIST_DW_I A_DCLK_B_L A_DW_I A_DI_R net22 VDD VSS ++ / RSC_IHPSG13_DFNQMX2IX1 +XA_BREG A_BIST_EN_I A_BIST_BM_I A_DCLK_B_L A_BM_I A_BM_R net23 VDD VSS ++ / RSC_IHPSG13_DFNQMX2IX1 +XI_FILL8<11> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI_FILL8<10> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI_FILL8<9> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI_FILL8<8> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI_FILL8<7> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI_FILL8<6> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI_FILL8<5> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI_FILL8<4> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI_FILL8<3> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI_FILL8<2> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI_FILL8<1> VDD VSS / RSC_IHPSG13_FILLCAP8 +XB_I51 net037 B_DR_O VDD VSS / RSC_IHPSG13_INVX4 +XA_I51 net19 A_DR_O VDD VSS / RSC_IHPSG13_INVX4 +XB_I44 B_BM_N B_WCLK_B_L B_DO_WRITE_P VDD VSS / RSC_IHPSG13_NOR2X2 +XA_I44 A_BM_N A_WCLK_B_L A_DO_WRITE_P VDD VSS / RSC_IHPSG13_NOR2X2 +XB_BM_TIEH B_TIEH_O VDD VSS / RSC_IHPSG13_TIEH +XA_BM_TIEH A_TIEH_O VDD VSS / RSC_IHPSG13_TIEH +XB_ISENSE B_SAE B_BLC_SEL B_BLT_SEL net037 net038 VDD VSS / ++ RSC_IHPSG13_DFPQD_MSAFFX2P +XA_ISENSE A_SAE A_BLC_SEL A_BLT_SEL net19 net20 VDD VSS / ++ RSC_IHPSG13_DFPQD_MSAFFX2P +XB_I49 B_DI_R B_DI_N VDD VSS / RSC_IHPSG13_INVX2 +XB_I83 B_BM_R B_BM_N VDD VSS / RSC_IHPSG13_INVX2 +XA_I49 A_DI_R A_DI_N VDD VSS / RSC_IHPSG13_INVX2 +XA_I83 A_BM_R A_BM_N VDD VSS / RSC_IHPSG13_INVX2 +XB_I69 B_DCLK_L B_DCLK_B_L VDD VSS / RSC_IHPSG13_CINVX2 +XB_I50 B_WCLK_L B_WCLK_B_L VDD VSS / RSC_IHPSG13_CINVX2 +XB_EBUF B_RCLK_L B_RCLK_B_L VDD VSS / RSC_IHPSG13_CINVX2 +XA_I69 A_DCLK_L A_DCLK_B_L VDD VSS / RSC_IHPSG13_CINVX2 +XA_I50 A_WCLK_L A_WCLK_B_L VDD VSS / RSC_IHPSG13_CINVX2 +XA_EBUF A_RCLK_L A_RCLK_B_L VDD VSS / RSC_IHPSG13_CINVX2 +XAB_BLMUX<1> A_BLC<7> A_BLC<6> A_BLC<5> A_BLC<4> A_BLC_SEL A_BLT<7> A_BLT<6> ++ A_BLT<5> A_BLT<4> A_BLT_SEL A_PRE_N A_ADDR_DEC<7> A_ADDR_DEC<6> ++ A_ADDR_DEC<5> A_ADDR_DEC<4> A_WR_ONE A_WR_ZERO B_BLC<7> B_BLC<6> B_BLC<5> ++ B_BLC<4> B_BLC_SEL B_BLT<7> B_BLT<6> B_BLT<5> B_BLT<4> B_BLT_SEL B_PRE_N ++ B_ADDR_DEC<7> B_ADDR_DEC<6> B_ADDR_DEC<5> B_ADDR_DEC<4> B_WR_ONE B_WR_ZERO ++ VDD VSS / RM_IHPSG13_1024x16_c2_2P_BLDRV +XAB_BLMUX<0> A_BLC<3> A_BLC<2> A_BLC<1> A_BLC<0> A_BLC_SEL A_BLT<3> A_BLT<2> ++ A_BLT<1> A_BLT<0> A_BLT_SEL A_PRE_N A_ADDR_DEC<3> A_ADDR_DEC<2> ++ A_ADDR_DEC<1> A_ADDR_DEC<0> A_WR_ONE A_WR_ZERO B_BLC<3> B_BLC<2> B_BLC<1> ++ B_BLC<0> B_BLC_SEL B_BLT<3> B_BLT<2> B_BLT<1> B_BLT<0> B_BLT_SEL B_PRE_N ++ B_ADDR_DEC<3> B_ADDR_DEC<2> B_ADDR_DEC<1> B_ADDR_DEC<0> B_WR_ONE B_WR_ZERO ++ VDD VSS / RM_IHPSG13_1024x16_c2_2P_BLDRV +XB_I78 B_RCLK_B_L B_SAE VDD VSS / RSC_IHPSG13_CBUFX2 +XA_I78 A_RCLK_B_L A_SAE VDD VSS / RSC_IHPSG13_CBUFX2 +XB_I88 B_DCLK_L B_DCLK_R / RSC_IHPSG13_MET3RES +XB_I87 B_WCLK_L B_WCLK_R / RSC_IHPSG13_MET3RES +XB_R2 B_RCLK_L B_RCLK_R / RSC_IHPSG13_MET3RES +XB_I91 B_RCLK_B_L B_RCLK_B_R / RSC_IHPSG13_MET3RES +XB_I90 B_WCLK_B_L B_WCLK_B_R / RSC_IHPSG13_MET3RES +XB_I89 B_DCLK_B_L B_DCLK_B_R / RSC_IHPSG13_MET3RES +XA_I88 A_DCLK_L A_DCLK_R / RSC_IHPSG13_MET3RES +XA_I87 A_WCLK_L A_WCLK_R / RSC_IHPSG13_MET3RES +XA_R2 A_RCLK_L A_RCLK_R / RSC_IHPSG13_MET3RES +XA_I91 A_RCLK_B_L A_RCLK_B_R / RSC_IHPSG13_MET3RES +XA_I90 A_WCLK_B_L A_WCLK_B_R / RSC_IHPSG13_MET3RES +XA_I89 A_DCLK_B_L A_DCLK_B_R / RSC_IHPSG13_MET3RES +XB_I80 B_WCLK_B_L B_RCLK_B_L net041 VDD VSS / RSC_IHPSG13_AND2X2 +XB_I76 B_DO_WRITE_P B_DI_N B_WR_ZERO VDD VSS / RSC_IHPSG13_AND2X2 +XB_I75 B_DO_WRITE_P B_DI_R B_WR_ONE VDD VSS / RSC_IHPSG13_AND2X2 +XA_I80 A_WCLK_B_L A_RCLK_B_L net21 VDD VSS / RSC_IHPSG13_AND2X2 +XA_I76 A_DI_N A_DO_WRITE_P A_WR_ZERO VDD VSS / RSC_IHPSG13_AND2X2 +XA_I75 A_DI_R A_DO_WRITE_P A_WR_ONE VDD VSS / RSC_IHPSG13_AND2X2 +XB_I81 net041 B_PRE_N VDD VSS / RSC_IHPSG13_CINVX4_WN +XA_I81 net21 A_PRE_N VDD VSS / RSC_IHPSG13_CINVX4_WN +XI_FILL4<10> VDD VSS / RSC_IHPSG13_FILLCAP4 +XI_FILL4<9> VDD VSS / RSC_IHPSG13_FILLCAP4 +XI_FILL4<8> VDD VSS / RSC_IHPSG13_FILLCAP4 +XI_FILL4<7> VDD VSS / RSC_IHPSG13_FILLCAP4 +XI_FILL4<6> VDD VSS / RSC_IHPSG13_FILLCAP4 +XI_FILL4<5> VDD VSS / RSC_IHPSG13_FILLCAP4 +XI_FILL4<4> VDD VSS / RSC_IHPSG13_FILLCAP4 +XI_FILL4<3> VDD VSS / RSC_IHPSG13_FILLCAP4 +XI_FILL4<2> VDD VSS / RSC_IHPSG13_FILLCAP4 +XI_FILL4<1> VDD VSS / RSC_IHPSG13_FILLCAP4 +.ENDS + +.SUBCKT RM_IHPSG13_1024x16_c2_2P_ROWDEC6 ADDR_N_I<5> ADDR_N_I<4> ADDR_N_I<3> ADDR_N_I<2> ++ ADDR_N_I<1> ADDR_N_I<0> CS_I ECLK_I WL_O<63> WL_O<62> WL_O<61> WL_O<60> ++ WL_O<59> WL_O<58> WL_O<57> WL_O<56> WL_O<55> WL_O<54> WL_O<53> WL_O<52> ++ WL_O<51> WL_O<50> WL_O<49> WL_O<48> WL_O<47> WL_O<46> WL_O<45> WL_O<44> ++ WL_O<43> WL_O<42> WL_O<41> WL_O<40> WL_O<39> WL_O<38> WL_O<37> WL_O<36> ++ WL_O<35> WL_O<34> WL_O<33> WL_O<32> WL_O<31> WL_O<30> WL_O<29> WL_O<28> ++ WL_O<27> WL_O<26> WL_O<25> WL_O<24> WL_O<23> WL_O<22> WL_O<21> WL_O<20> ++ WL_O<19> WL_O<18> WL_O<17> WL_O<16> WL_O<15> WL_O<14> WL_O<13> WL_O<12> ++ WL_O<11> WL_O<10> WL_O<9> WL_O<8> WL_O<7> WL_O<6> WL_O<5> WL_O<4> WL_O<3> ++ WL_O<2> WL_O<1> WL_O<0> VDD VSS +XDEC10 ADDR_N_I<5> ADDR_N_I<4> CS_I CS00<2> VDD VSS / ++ RM_IHPSG13_1024x16_c2_2P_DEC02 +XDEC00 ADDR_N_I<5> ADDR_N_I<4> CS_I CS00<0> VDD VSS / ++ RM_IHPSG13_1024x16_c2_2P_DEC00 +XSEL<3> ADDR_N_I<3> ADDR_N_I<2> ADDR_N_I<1> ADDR_N_I<0> CS00<3> ECLK_H<3> ++ ECLK_H<4> ECLK_B<3> ECLK_B<4> WL_O<63> WL_O<62> WL_O<61> WL_O<60> WL_O<59> ++ WL_O<58> WL_O<57> WL_O<56> WL_O<55> WL_O<54> WL_O<53> WL_O<52> WL_O<51> ++ WL_O<50> WL_O<49> WL_O<48> VDD VSS / RM_IHPSG13_1024x16_c2_2P_DEC04 +XSEL<2> ADDR_N_I<3> ADDR_N_I<2> ADDR_N_I<1> ADDR_N_I<0> CS00<2> ECLK_H<2> ++ ECLK_H<3> ECLK_B<2> ECLK_B<3> WL_O<47> WL_O<46> WL_O<45> WL_O<44> WL_O<43> ++ WL_O<42> WL_O<41> WL_O<40> WL_O<39> WL_O<38> WL_O<37> WL_O<36> WL_O<35> ++ WL_O<34> WL_O<33> WL_O<32> VDD VSS / RM_IHPSG13_1024x16_c2_2P_DEC04 +XSEL<1> ADDR_N_I<3> ADDR_N_I<2> ADDR_N_I<1> ADDR_N_I<0> CS00<1> ECLK_H<1> ++ ECLK_H<2> ECLK_B<1> ECLK_B<2> WL_O<31> WL_O<30> WL_O<29> WL_O<28> WL_O<27> ++ WL_O<26> WL_O<25> WL_O<24> WL_O<23> WL_O<22> WL_O<21> WL_O<20> WL_O<19> ++ WL_O<18> WL_O<17> WL_O<16> VDD VSS / RM_IHPSG13_1024x16_c2_2P_DEC04 +XSEL<0> ADDR_N_I<3> ADDR_N_I<2> ADDR_N_I<1> ADDR_N_I<0> CS00<0> ECLK_I ++ ECLK_H<1> ECLK_B<0> ECLK_B<1> WL_O<15> WL_O<14> WL_O<13> WL_O<12> WL_O<11> ++ WL_O<10> WL_O<9> WL_O<8> WL_O<7> WL_O<6> WL_O<5> WL_O<4> WL_O<3> WL_O<2> ++ WL_O<1> WL_O<0> VDD VSS / RM_IHPSG13_1024x16_c2_2P_DEC04 +XDEC11 ADDR_N_I<5> ADDR_N_I<4> CS_I CS00<3> VDD VSS / ++ RM_IHPSG13_1024x16_c2_2P_DEC03 +XL2<36> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<35> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<34> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<33> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<32> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<31> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<30> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<29> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<28> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<27> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<26> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<25> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<24> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<23> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<22> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<21> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<20> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<19> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<18> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<17> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<16> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<15> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<14> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<13> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<12> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<11> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<10> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<9> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<8> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<7> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<6> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<5> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<4> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<3> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<2> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<1> VDD VSS / RSC_IHPSG13_FILLCAP8 +XDEC01 ADDR_N_I<5> ADDR_N_I<4> CS_I CS00<1> VDD VSS / ++ RM_IHPSG13_1024x16_c2_2P_DEC01 +.ENDS +.SUBCKT RM_IHPSG13_1024x16_c2_2P_ROWREG6 ACLK_N_I ADDR_I<5> ADDR_I<4> ADDR_I<3> ADDR_I<2> ++ ADDR_I<1> ADDR_I<0> ADDR_N_O<5> ADDR_N_O<4> ADDR_N_O<3> ADDR_N_O<2> ++ ADDR_N_O<1> ADDR_N_O<0> BIST_ADDR_I<5> BIST_ADDR_I<4> BIST_ADDR_I<3> ++ BIST_ADDR_I<2> BIST_ADDR_I<1> BIST_ADDR_I<0> BIST_EN_I VDD VSS +XINV<5> q_int<5> qn_int<5> VDD VSS / RSC_IHPSG13_CINVX2 +XINV<4> q_int<4> qn_int<4> VDD VSS / RSC_IHPSG13_CINVX2 +XINV<3> q_int<3> qn_int<3> VDD VSS / RSC_IHPSG13_CINVX2 +XINV<2> q_int<2> qn_int<2> VDD VSS / RSC_IHPSG13_CINVX2 +XINV<1> q_int<1> qn_int<1> VDD VSS / RSC_IHPSG13_CINVX2 +XINV<0> q_int<0> qn_int<0> VDD VSS / RSC_IHPSG13_CINVX2 +XDRV<5> qn_int<5> ADDR_N_O<5> VDD VSS / RSC_IHPSG13_CINVX8 +XDRV<4> qn_int<4> ADDR_N_O<4> VDD VSS / RSC_IHPSG13_CINVX8 +XDRV<3> qn_int<3> ADDR_N_O<3> VDD VSS / RSC_IHPSG13_CINVX8 +XDRV<2> qn_int<2> ADDR_N_O<2> VDD VSS / RSC_IHPSG13_CINVX8 +XDRV<1> qn_int<1> ADDR_N_O<1> VDD VSS / RSC_IHPSG13_CINVX8 +XDRV<0> qn_int<0> ADDR_N_O<0> VDD VSS / RSC_IHPSG13_CINVX8 +XDFF<5> BIST_EN_I BIST_ADDR_I<5> ACLK_N_I ADDR_I<5> q_int<5> net2<0> VDD ++ VSS / RSC_IHPSG13_DFNQMX2IX1 +XDFF<4> BIST_EN_I BIST_ADDR_I<4> ACLK_N_I ADDR_I<4> q_int<4> net2<1> VDD ++ VSS / RSC_IHPSG13_DFNQMX2IX1 +XDFF<3> BIST_EN_I BIST_ADDR_I<3> ACLK_N_I ADDR_I<3> q_int<3> net2<2> VDD ++ VSS / RSC_IHPSG13_DFNQMX2IX1 +XDFF<2> BIST_EN_I BIST_ADDR_I<2> ACLK_N_I ADDR_I<2> q_int<2> net2<3> VDD ++ VSS / RSC_IHPSG13_DFNQMX2IX1 +XDFF<1> BIST_EN_I BIST_ADDR_I<1> ACLK_N_I ADDR_I<1> q_int<1> net2<4> VDD ++ VSS / RSC_IHPSG13_DFNQMX2IX1 +XDFF<0> BIST_EN_I BIST_ADDR_I<0> ACLK_N_I ADDR_I<0> q_int<0> net2<5> VDD ++ VSS / RSC_IHPSG13_DFNQMX2IX1 +XI11<12> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI11<11> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI11<10> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI11<9> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI11<8> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI11<7> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI11<6> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI11<5> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI11<4> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI11<3> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI11<2> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI11<1> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI12<2> VDD VSS / RSC_IHPSG13_FILLCAP4 +XI12<1> VDD VSS / RSC_IHPSG13_FILLCAP4 +XI12<0> VDD VSS / RSC_IHPSG13_FILLCAP4 +.ENDS + +.SUBCKT RM_IHPSG13_1024x16_c2_2P_COLDRV13X16 ADDR_COL_I<1> ADDR_COL_I<0> ADDR_COL_O<1> ++ ADDR_COL_O<0> ADDR_DEC_I<7> ADDR_DEC_I<6> ADDR_DEC_I<5> ADDR_DEC_I<4> ++ ADDR_DEC_I<3> ADDR_DEC_I<2> ADDR_DEC_I<1> ADDR_DEC_I<0> ADDR_DEC_O<7> ++ ADDR_DEC_O<6> ADDR_DEC_O<5> ADDR_DEC_O<4> ADDR_DEC_O<3> ADDR_DEC_O<2> ++ ADDR_DEC_O<1> ADDR_DEC_O<0> DCLK_I DCLK_O RCLK_I RCLK_O WCLK_I WCLK_O ++ VDD VSS +XI0<7> VDD VSS / RSC_IHPSG13_FILLCAP4 +XI0<6> VDD VSS / RSC_IHPSG13_FILLCAP4 +XI0<5> VDD VSS / RSC_IHPSG13_FILLCAP4 +XI0<4> VDD VSS / RSC_IHPSG13_FILLCAP4 +XI0<3> VDD VSS / RSC_IHPSG13_FILLCAP4 +XI0<2> VDD VSS / RSC_IHPSG13_FILLCAP4 +XI0<1> VDD VSS / RSC_IHPSG13_FILLCAP4 +XWCLK_DRV WCLK_I WCLK_O VDD VSS / RSC_IHPSG13_CBUFX16 +XRCLK_DRV RCLK_I RCLK_O VDD VSS / RSC_IHPSG13_CBUFX16 +XDCLK_DRV DCLK_I DCLK_O VDD VSS / RSC_IHPSG13_CBUFX16 +XADDR_COL_DRV<1> ADDR_COL_I<1> ADDR_COL_O<1> VDD VSS / ++ RSC_IHPSG13_CBUFX16 +XADDR_COL_DRV<0> ADDR_COL_I<0> ADDR_COL_O<0> VDD VSS / ++ RSC_IHPSG13_CBUFX16 +XADDR_DEC_DRV<7> ADDR_DEC_I<7> ADDR_DEC_O<7> VDD VSS / ++ RSC_IHPSG13_CBUFX16 +XADDR_DEC_DRV<6> ADDR_DEC_I<6> ADDR_DEC_O<6> VDD VSS / ++ RSC_IHPSG13_CBUFX16 +XADDR_DEC_DRV<5> ADDR_DEC_I<5> ADDR_DEC_O<5> VDD VSS / ++ RSC_IHPSG13_CBUFX16 +XADDR_DEC_DRV<4> ADDR_DEC_I<4> ADDR_DEC_O<4> VDD VSS / ++ RSC_IHPSG13_CBUFX16 +XADDR_DEC_DRV<3> ADDR_DEC_I<3> ADDR_DEC_O<3> VDD VSS / ++ RSC_IHPSG13_CBUFX16 +XADDR_DEC_DRV<2> ADDR_DEC_I<2> ADDR_DEC_O<2> VDD VSS / ++ RSC_IHPSG13_CBUFX16 +XADDR_DEC_DRV<1> ADDR_DEC_I<1> ADDR_DEC_O<1> VDD VSS / ++ RSC_IHPSG13_CBUFX16 +XADDR_DEC_DRV<0> ADDR_DEC_I<0> ADDR_DEC_O<0> VDD VSS / ++ RSC_IHPSG13_CBUFX16 +XI1<5> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI1<4> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI1<3> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI1<2> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI1<1> VDD VSS / RSC_IHPSG13_FILLCAP8 +.ENDS +.SUBCKT RM_IHPSG13_1024x16_c2_2P_WLDRV16X16 A<15> A<14> A<13> A<12> A<11> A<10> A<9> A<8> ++ A<7> A<6> A<5> A<4> A<3> A<2> A<1> A<0> Z<15> Z<14> Z<13> Z<12> Z<11> Z<10> ++ Z<9> Z<8> Z<7> Z<6> Z<5> Z<4> Z<3> Z<2> Z<1> Z<0> VDD VSS +XBUF<15> A<15> Z<15> VDD VSS / RSC_IHPSG13_WLDRVX16 +XBUF<14> A<14> Z<14> VDD VSS / RSC_IHPSG13_WLDRVX16 +XBUF<13> A<13> Z<13> VDD VSS / RSC_IHPSG13_WLDRVX16 +XBUF<12> A<12> Z<12> VDD VSS / RSC_IHPSG13_WLDRVX16 +XBUF<11> A<11> Z<11> VDD VSS / RSC_IHPSG13_WLDRVX16 +XBUF<10> A<10> Z<10> VDD VSS / RSC_IHPSG13_WLDRVX16 +XBUF<9> A<9> Z<9> VDD VSS / RSC_IHPSG13_WLDRVX16 +XBUF<8> A<8> Z<8> VDD VSS / RSC_IHPSG13_WLDRVX16 +XBUF<7> A<7> Z<7> VDD VSS / RSC_IHPSG13_WLDRVX16 +XBUF<6> A<6> Z<6> VDD VSS / RSC_IHPSG13_WLDRVX16 +XBUF<5> A<5> Z<5> VDD VSS / RSC_IHPSG13_WLDRVX16 +XBUF<4> A<4> Z<4> VDD VSS / RSC_IHPSG13_WLDRVX16 +XBUF<3> A<3> Z<3> VDD VSS / RSC_IHPSG13_WLDRVX16 +XBUF<2> A<2> Z<2> VDD VSS / RSC_IHPSG13_WLDRVX16 +XBUF<1> A<1> Z<1> VDD VSS / RSC_IHPSG13_WLDRVX16 +XBUF<0> A<0> Z<0> VDD VSS / RSC_IHPSG13_WLDRVX16 +.ENDS + + +.SUBCKT RM_IHPSG13_1024x16_c2_1P_DEC01 ADDR<1> ADDR<0> CS CS_OUT VDD VSS +XDECINV net1 CS_OUT VDD VSS / RSC_IHPSG13_INVX4 +XDEC NADDR<1> ADDR<0> CS net1 VDD VSS / RSC_IHPSG13_NAND3X2 +XI2 VDD VSS / RSC_IHPSG13_FILLCAP4 +XADDRINV ADDR<1> NADDR<1> VDD VSS / RSC_IHPSG13_INVX2 +.ENDS +.SUBCKT RM_IHPSG13_1024x16_c2_1P_DEC00 ADDR<1> ADDR<0> CS CS_OUT VDD VSS +XDECINV net1 CS_OUT VDD VSS / RSC_IHPSG13_INVX4 +XDEC NADDR<1> NADDR<0> CS net1 VDD VSS / RSC_IHPSG13_NAND3X2 +XADDRINV<1> ADDR<1> NADDR<1> VDD VSS / RSC_IHPSG13_INVX2 +XADDRINV<0> ADDR<0> NADDR<0> VDD VSS / RSC_IHPSG13_INVX2 +XI1 VDD VSS / RSC_IHPSG13_FILLCAP4 +.ENDS +.SUBCKT RM_IHPSG13_1024x16_c2_1P_ROWDEC5 ADDR_N_I<4> ADDR_N_I<3> ADDR_N_I<2> ADDR_N_I<1> ++ ADDR_N_I<0> CS_I ECLK_I WL_O<31> WL_O<30> WL_O<29> WL_O<28> WL_O<27> ++ WL_O<26> WL_O<25> WL_O<24> WL_O<23> WL_O<22> WL_O<21> WL_O<20> WL_O<19> ++ WL_O<18> WL_O<17> WL_O<16> WL_O<15> WL_O<14> WL_O<13> WL_O<12> WL_O<11> ++ WL_O<10> WL_O<9> WL_O<8> WL_O<7> WL_O<6> WL_O<5> WL_O<4> WL_O<3> WL_O<2> ++ WL_O<1> WL_O<0> VDD VSS +XL2<12> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<11> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<10> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<9> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<8> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<7> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<6> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<5> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<4> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<3> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<2> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<1> VDD VSS / RSC_IHPSG13_FILLCAP8 +XDEC01 ADDR_N_I<5> ADDR_N_I<4> CS_I CS00<1> VDD VSS / ++ RM_IHPSG13_1024x16_c2_1P_DEC01 +XDEC00 ADDR_N_I<5> ADDR_N_I<4> CS_I CS00<0> VDD VSS / ++ RM_IHPSG13_1024x16_c2_1P_DEC00 +XSEL<1> ADDR_N_I<3> ADDR_N_I<2> ADDR_N_I<1> ADDR_N_I<0> CS00<1> ECLK_H<1> ++ ECLK_H<2> ECLK_B<1> ECLK_B<2> WL_O<31> WL_O<30> WL_O<29> WL_O<28> WL_O<27> ++ WL_O<26> WL_O<25> WL_O<24> WL_O<23> WL_O<22> WL_O<21> WL_O<20> WL_O<19> ++ WL_O<18> WL_O<17> WL_O<16> VDD VSS / RM_IHPSG13_1024x16_c2_1P_DEC04 +XSEL<0> ADDR_N_I<3> ADDR_N_I<2> ADDR_N_I<1> ADDR_N_I<0> CS00<0> ECLK_I ++ ECLK_H<1> ECLK_B<0> ECLK_B<1> WL_O<15> WL_O<14> WL_O<13> WL_O<12> WL_O<11> ++ WL_O<10> WL_O<9> WL_O<8> WL_O<7> WL_O<6> WL_O<5> WL_O<4> WL_O<3> WL_O<2> ++ WL_O<1> WL_O<0> VDD VSS / RM_IHPSG13_1024x16_c2_1P_DEC04 +XI0 ADDR_N_I<5> VDD VSS / RSC_IHPSG13_TIEL +.ENDS +.SUBCKT RM_IHPSG13_1024x16_c2_1P_ROWREG5 ACLK_N_I ADDR_I<4> ADDR_I<3> ADDR_I<2> ADDR_I<1> ++ ADDR_I<0> ADDR_N_O<4> ADDR_N_O<3> ADDR_N_O<2> ADDR_N_O<1> ADDR_N_O<0> ++ BIST_ADDR_I<4> BIST_ADDR_I<3> BIST_ADDR_I<2> BIST_ADDR_I<1> BIST_ADDR_I<0> ++ BIST_EN_I VDD VSS +XINV<4> q_int<4> qn_int<4> VDD VSS / RSC_IHPSG13_CINVX2 +XINV<3> q_int<3> qn_int<3> VDD VSS / RSC_IHPSG13_CINVX2 +XINV<2> q_int<2> qn_int<2> VDD VSS / RSC_IHPSG13_CINVX2 +XINV<1> q_int<1> qn_int<1> VDD VSS / RSC_IHPSG13_CINVX2 +XINV<0> q_int<0> qn_int<0> VDD VSS / RSC_IHPSG13_CINVX2 +XDRV<4> qn_int<4> ADDR_N_O<4> VDD VSS / RSC_IHPSG13_CINVX8 +XDRV<3> qn_int<3> ADDR_N_O<3> VDD VSS / RSC_IHPSG13_CINVX8 +XDRV<2> qn_int<2> ADDR_N_O<2> VDD VSS / RSC_IHPSG13_CINVX8 +XDRV<1> qn_int<1> ADDR_N_O<1> VDD VSS / RSC_IHPSG13_CINVX8 +XDRV<0> qn_int<0> ADDR_N_O<0> VDD VSS / RSC_IHPSG13_CINVX8 +XDFF<4> BIST_EN_I BIST_ADDR_I<4> ACLK_N_I ADDR_I<4> q_int<4> net2<0> VDD ++ VSS / RSC_IHPSG13_DFNQMX2IX1 +XDFF<3> BIST_EN_I BIST_ADDR_I<3> ACLK_N_I ADDR_I<3> q_int<3> net2<1> VDD ++ VSS / RSC_IHPSG13_DFNQMX2IX1 +XDFF<2> BIST_EN_I BIST_ADDR_I<2> ACLK_N_I ADDR_I<2> q_int<2> net2<2> VDD ++ VSS / RSC_IHPSG13_DFNQMX2IX1 +XDFF<1> BIST_EN_I BIST_ADDR_I<1> ACLK_N_I ADDR_I<1> q_int<1> net2<3> VDD ++ VSS / RSC_IHPSG13_DFNQMX2IX1 +XDFF<0> BIST_EN_I BIST_ADDR_I<0> ACLK_N_I ADDR_I<0> q_int<0> net2<4> VDD ++ VSS / RSC_IHPSG13_DFNQMX2IX1 +XI11<16> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI11<15> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI11<14> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI11<13> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI11<12> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI11<11> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI11<10> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI11<9> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI11<8> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI11<7> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI11<6> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI11<5> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI11<4> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI11<3> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI11<2> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI11<1> VDD VSS / RSC_IHPSG13_FILLCAP8 +.ENDS + + +.SUBCKT RM_IHPSG13_1024x16_c2_1P_COLDEC5 ACLK_N ADDR<4> ADDR<3> ADDR<2> ADDR<1> ADDR<0> ++ ADDR_COL<1> ADDR_COL<0> ADDR_DEC<7> ADDR_DEC<6> ADDR_DEC<5> ADDR_DEC<4> ++ ADDR_DEC<3> ADDR_DEC<2> ADDR_DEC<1> ADDR_DEC<0> BIST_ADDR<4> BIST_ADDR<3> ++ BIST_ADDR<2> BIST_ADDR<1> BIST_ADDR<0> BIST_EN_I VDD VSS +XI17<2> VDD VSS / RSC_IHPSG13_FILLCAP4 +XI17<1> VDD VSS / RSC_IHPSG13_FILLCAP4 +XI13<1> addr_int<1> ADDR_COL<1> VDD VSS / RSC_IHPSG13_CBUFX2 +XI13<0> addr_int<0> ADDR_COL<0> VDD VSS / RSC_IHPSG13_CBUFX2 +XDFF<4> BIST_EN_I BIST_ADDR<4> ACLK_N ADDR<4> addr_int<1> net7<0> VDD ++ VSS / RSC_IHPSG13_DFNQMX2IX1 +XDFF<3> BIST_EN_I BIST_ADDR<3> ACLK_N ADDR<3> addr_int<0> net7<1> VDD ++ VSS / RSC_IHPSG13_DFNQMX2IX1 +XDFF<2> BIST_EN_I BIST_ADDR<2> ACLK_N ADDR<2> padr_int<2> net7<2> VDD ++ VSS / RSC_IHPSG13_DFNQMX2IX1 +XDFF<1> BIST_EN_I BIST_ADDR<1> ACLK_N ADDR<1> padr_int<1> net7<3> VDD ++ VSS / RSC_IHPSG13_DFNQMX2IX1 +XDFF<0> BIST_EN_I BIST_ADDR<0> ACLK_N ADDR<0> padr_int<0> net7<4> VDD ++ VSS / RSC_IHPSG13_DFNQMX2IX1 +XI1<7> PADR<0> PADR<1> PADR<2> addr_n<7> VDD VSS / RSC_IHPSG13_NAND3X2 +XI1<6> NADR<0> PADR<1> PADR<2> addr_n<6> VDD VSS / RSC_IHPSG13_NAND3X2 +XI1<5> PADR<0> NADR<1> PADR<2> addr_n<5> VDD VSS / RSC_IHPSG13_NAND3X2 +XI1<4> NADR<0> NADR<1> PADR<2> addr_n<4> VDD VSS / RSC_IHPSG13_NAND3X2 +XI1<3> PADR<0> PADR<1> NADR<2> addr_n<3> VDD VSS / RSC_IHPSG13_NAND3X2 +XI1<2> NADR<0> PADR<1> NADR<2> addr_n<2> VDD VSS / RSC_IHPSG13_NAND3X2 +XI1<1> PADR<0> NADR<1> NADR<2> addr_n<1> VDD VSS / RSC_IHPSG13_NAND3X2 +XI1<0> NADR<0> NADR<1> NADR<2> addr_n<0> VDD VSS / RSC_IHPSG13_NAND3X2 +XI15<2> NADR<2> PADR<2> VDD VSS / RSC_IHPSG13_INVX2 +XI15<1> NADR<1> PADR<1> VDD VSS / RSC_IHPSG13_INVX2 +XI15<0> NADR<0> PADR<0> VDD VSS / RSC_IHPSG13_INVX2 +XI3<2> padr_int<2> NADR<2> VDD VSS / RSC_IHPSG13_INVX2 +XI3<1> padr_int<1> NADR<1> VDD VSS / RSC_IHPSG13_INVX2 +XI3<0> padr_int<0> NADR<0> VDD VSS / RSC_IHPSG13_INVX2 +XI2<7> addr_n<7> ADDR_DEC<7> VDD VSS / RSC_IHPSG13_INVX2 +XI2<6> addr_n<6> ADDR_DEC<6> VDD VSS / RSC_IHPSG13_INVX2 +XI2<5> addr_n<5> ADDR_DEC<5> VDD VSS / RSC_IHPSG13_INVX2 +XI2<4> addr_n<4> ADDR_DEC<4> VDD VSS / RSC_IHPSG13_INVX2 +XI2<3> addr_n<3> ADDR_DEC<3> VDD VSS / RSC_IHPSG13_INVX2 +XI2<2> addr_n<2> ADDR_DEC<2> VDD VSS / RSC_IHPSG13_INVX2 +XI2<1> addr_n<1> ADDR_DEC<1> VDD VSS / RSC_IHPSG13_INVX2 +XI2<0> addr_n<0> ADDR_DEC<0> VDD VSS / RSC_IHPSG13_INVX2 +.ENDS +.SUBCKT RM_IHPSG13_1024x16_c2_1P_COLCTRL5 A_ADDR_COL<1> A_ADDR_COL<0> A_ADDR_DEC<7> ++ A_ADDR_DEC<6> A_ADDR_DEC<5> A_ADDR_DEC<4> A_ADDR_DEC<3> A_ADDR_DEC<2> ++ A_ADDR_DEC<1> A_ADDR_DEC<0> A_BIST_BM_I A_BIST_DW_I A_BIST_EN_I A_BLC<31> ++ A_BLC<30> A_BLC<29> A_BLC<28> A_BLC<27> A_BLC<26> A_BLC<25> A_BLC<24> ++ A_BLC<23> A_BLC<22> A_BLC<21> A_BLC<20> A_BLC<19> A_BLC<18> A_BLC<17> ++ A_BLC<16> A_BLC<15> A_BLC<14> A_BLC<13> A_BLC<12> A_BLC<11> A_BLC<10> ++ A_BLC<9> A_BLC<8> A_BLC<7> A_BLC<6> A_BLC<5> A_BLC<4> A_BLC<3> A_BLC<2> ++ A_BLC<1> A_BLC<0> A_BLT<31> A_BLT<30> A_BLT<29> A_BLT<28> A_BLT<27> ++ A_BLT<26> A_BLT<25> A_BLT<24> A_BLT<23> A_BLT<22> A_BLT<21> A_BLT<20> ++ A_BLT<19> A_BLT<18> A_BLT<17> A_BLT<16> A_BLT<15> A_BLT<14> A_BLT<13> ++ A_BLT<12> A_BLT<11> A_BLT<10> A_BLT<9> A_BLT<8> A_BLT<7> A_BLT<6> A_BLT<5> ++ A_BLT<4> A_BLT<3> A_BLT<2> A_BLT<1> A_BLT<0> A_BM_I A_DCLK_B_L A_DCLK_B_R ++ A_DCLK_L A_DCLK_R A_DR_O A_DW_I A_RCLK_B_L A_RCLK_B_R A_RCLK_L A_RCLK_R ++ A_TIEH_O A_WCLK_B_L A_WCLK_B_R A_WCLK_L A_WCLK_R VDD VSS +XA_I80<1> A_WCLK_B_L A_RCLK_B_L A_W_nor_R<1> VDD VSS / ++ RSC_IHPSG13_AND2X2 +XA_I80<0> A_WCLK_B_L A_RCLK_B_L A_W_nor_R<0> VDD VSS / ++ RSC_IHPSG13_AND2X2 +XA_I44 A_BM_N A_WCLK_B_L A_DO_WRITE_P VDD VSS / RSC_IHPSG13_NOR2X2 +XI80<29> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI80<28> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI80<27> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI80<26> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI80<25> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI80<24> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI80<23> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI80<22> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI80<21> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI80<20> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI80<19> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI80<18> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI80<17> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI80<16> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI80<15> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI80<14> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI80<13> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI80<12> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI80<11> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI80<10> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI80<9> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI80<8> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI80<7> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI80<6> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI80<5> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI80<4> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI80<3> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI80<2> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI80<1> VDD VSS / RSC_IHPSG13_FILLCAP8 +XA_I74<16> VDD VSS / RSC_IHPSG13_FILLCAP8 +XA_I74<15> VDD VSS / RSC_IHPSG13_FILLCAP8 +XA_I74<14> VDD VSS / RSC_IHPSG13_FILLCAP8 +XA_I74<13> VDD VSS / RSC_IHPSG13_FILLCAP8 +XA_I74<12> VDD VSS / RSC_IHPSG13_FILLCAP8 +XA_I74<11> VDD VSS / RSC_IHPSG13_FILLCAP8 +XA_I74<10> VDD VSS / RSC_IHPSG13_FILLCAP8 +XA_I74<9> VDD VSS / RSC_IHPSG13_FILLCAP8 +XA_I74<8> VDD VSS / RSC_IHPSG13_FILLCAP8 +XA_I74<7> VDD VSS / RSC_IHPSG13_FILLCAP8 +XA_I74<6> VDD VSS / RSC_IHPSG13_FILLCAP8 +XA_I74<5> VDD VSS / RSC_IHPSG13_FILLCAP8 +XA_I74<4> VDD VSS / RSC_IHPSG13_FILLCAP8 +XA_I74<3> VDD VSS / RSC_IHPSG13_FILLCAP8 +XA_I74<2> VDD VSS / RSC_IHPSG13_FILLCAP8 +XA_I74<1> VDD VSS / RSC_IHPSG13_FILLCAP8 +XA_INV<6> A_N1<1> A_P1<1> VDD VSS / RSC_IHPSG13_CINVX4 +XA_INV<5> A_N0<1> A_P0<1> VDD VSS / RSC_IHPSG13_CINVX4 +XA_INV<4> A_N0<0> A_P0<0> VDD VSS / RSC_IHPSG13_CINVX4 +XA_INV<3> A_ADDR_COL<1> A_N1<1> VDD VSS / RSC_IHPSG13_CINVX4 +XA_INV<2> A_ADDR_COL<1> A_N1<0> VDD VSS / RSC_IHPSG13_CINVX4 +XA_INV<1> A_ADDR_COL<0> A_N0<1> VDD VSS / RSC_IHPSG13_CINVX4 +XA_INV<0> A_ADDR_COL<0> A_N0<0> VDD VSS / RSC_IHPSG13_CINVX4 +XA_I81<3> A_W_nor_R<1> A_PRE_N VDD VSS / RSC_IHPSG13_CINVX4_WN +XA_I81<2> A_W_nor_R<1> A_PRE_N VDD VSS / RSC_IHPSG13_CINVX4_WN +XA_I81<1> A_W_nor_R<0> A_PRE_N VDD VSS / RSC_IHPSG13_CINVX4_WN +XA_I81<0> A_W_nor_R<0> A_PRE_N VDD VSS / RSC_IHPSG13_CINVX4_WN +XA_BLTMUX<31> A_BLC<31> A_BLC_SEL A_BLT<31> A_BLT_SEL A_PRE_N A_SEL_P<31> ++ A_WR_ONE A_WR_ZERO VDD VSS / RM_IHPSG13_1024x16_c2_1P_BLDRV +XA_BLTMUX<30> A_BLC<30> A_BLC_SEL A_BLT<30> A_BLT_SEL A_PRE_N A_SEL_P<30> ++ A_WR_ONE A_WR_ZERO VDD VSS / RM_IHPSG13_1024x16_c2_1P_BLDRV +XA_BLTMUX<29> A_BLC<29> A_BLC_SEL A_BLT<29> A_BLT_SEL A_PRE_N A_SEL_P<29> ++ A_WR_ONE A_WR_ZERO VDD VSS / RM_IHPSG13_1024x16_c2_1P_BLDRV +XA_BLTMUX<28> A_BLC<28> A_BLC_SEL A_BLT<28> A_BLT_SEL A_PRE_N A_SEL_P<28> ++ A_WR_ONE A_WR_ZERO VDD VSS / RM_IHPSG13_1024x16_c2_1P_BLDRV +XA_BLTMUX<27> A_BLC<27> A_BLC_SEL A_BLT<27> A_BLT_SEL A_PRE_N A_SEL_P<27> ++ A_WR_ONE A_WR_ZERO VDD VSS / RM_IHPSG13_1024x16_c2_1P_BLDRV +XA_BLTMUX<26> A_BLC<26> A_BLC_SEL A_BLT<26> A_BLT_SEL A_PRE_N A_SEL_P<26> ++ A_WR_ONE A_WR_ZERO VDD VSS / RM_IHPSG13_1024x16_c2_1P_BLDRV +XA_BLTMUX<25> A_BLC<25> A_BLC_SEL A_BLT<25> A_BLT_SEL A_PRE_N A_SEL_P<25> ++ A_WR_ONE A_WR_ZERO VDD VSS / RM_IHPSG13_1024x16_c2_1P_BLDRV +XA_BLTMUX<24> A_BLC<24> A_BLC_SEL A_BLT<24> A_BLT_SEL A_PRE_N A_SEL_P<24> ++ A_WR_ONE A_WR_ZERO VDD VSS / RM_IHPSG13_1024x16_c2_1P_BLDRV +XA_BLTMUX<23> A_BLC<23> A_BLC_SEL A_BLT<23> A_BLT_SEL A_PRE_N A_SEL_P<23> ++ A_WR_ONE A_WR_ZERO VDD VSS / RM_IHPSG13_1024x16_c2_1P_BLDRV +XA_BLTMUX<22> A_BLC<22> A_BLC_SEL A_BLT<22> A_BLT_SEL A_PRE_N A_SEL_P<22> ++ A_WR_ONE A_WR_ZERO VDD VSS / RM_IHPSG13_1024x16_c2_1P_BLDRV +XA_BLTMUX<21> A_BLC<21> A_BLC_SEL A_BLT<21> A_BLT_SEL A_PRE_N A_SEL_P<21> ++ A_WR_ONE A_WR_ZERO VDD VSS / RM_IHPSG13_1024x16_c2_1P_BLDRV +XA_BLTMUX<20> A_BLC<20> A_BLC_SEL A_BLT<20> A_BLT_SEL A_PRE_N A_SEL_P<20> ++ A_WR_ONE A_WR_ZERO VDD VSS / RM_IHPSG13_1024x16_c2_1P_BLDRV +XA_BLTMUX<19> A_BLC<19> A_BLC_SEL A_BLT<19> A_BLT_SEL A_PRE_N A_SEL_P<19> ++ A_WR_ONE A_WR_ZERO VDD VSS / RM_IHPSG13_1024x16_c2_1P_BLDRV +XA_BLTMUX<18> A_BLC<18> A_BLC_SEL A_BLT<18> A_BLT_SEL A_PRE_N A_SEL_P<18> ++ A_WR_ONE A_WR_ZERO VDD VSS / RM_IHPSG13_1024x16_c2_1P_BLDRV +XA_BLTMUX<17> A_BLC<17> A_BLC_SEL A_BLT<17> A_BLT_SEL A_PRE_N A_SEL_P<17> ++ A_WR_ONE A_WR_ZERO VDD VSS / RM_IHPSG13_1024x16_c2_1P_BLDRV +XA_BLTMUX<16> A_BLC<16> A_BLC_SEL A_BLT<16> A_BLT_SEL A_PRE_N A_SEL_P<16> ++ A_WR_ONE A_WR_ZERO VDD VSS / RM_IHPSG13_1024x16_c2_1P_BLDRV +XA_BLTMUX<15> A_BLC<15> A_BLC_SEL A_BLT<15> A_BLT_SEL A_PRE_N A_SEL_P<15> ++ A_WR_ONE A_WR_ZERO VDD VSS / RM_IHPSG13_1024x16_c2_1P_BLDRV +XA_BLTMUX<14> A_BLC<14> A_BLC_SEL A_BLT<14> A_BLT_SEL A_PRE_N A_SEL_P<14> ++ A_WR_ONE A_WR_ZERO VDD VSS / RM_IHPSG13_1024x16_c2_1P_BLDRV +XA_BLTMUX<13> A_BLC<13> A_BLC_SEL A_BLT<13> A_BLT_SEL A_PRE_N A_SEL_P<13> ++ A_WR_ONE A_WR_ZERO VDD VSS / RM_IHPSG13_1024x16_c2_1P_BLDRV +XA_BLTMUX<12> A_BLC<12> A_BLC_SEL A_BLT<12> A_BLT_SEL A_PRE_N A_SEL_P<12> ++ A_WR_ONE A_WR_ZERO VDD VSS / RM_IHPSG13_1024x16_c2_1P_BLDRV +XA_BLTMUX<11> A_BLC<11> A_BLC_SEL A_BLT<11> A_BLT_SEL A_PRE_N A_SEL_P<11> ++ A_WR_ONE A_WR_ZERO VDD VSS / RM_IHPSG13_1024x16_c2_1P_BLDRV +XA_BLTMUX<10> A_BLC<10> A_BLC_SEL A_BLT<10> A_BLT_SEL A_PRE_N A_SEL_P<10> ++ A_WR_ONE A_WR_ZERO VDD VSS / RM_IHPSG13_1024x16_c2_1P_BLDRV +XA_BLTMUX<9> A_BLC<9> A_BLC_SEL A_BLT<9> A_BLT_SEL A_PRE_N A_SEL_P<9> A_WR_ONE ++ A_WR_ZERO VDD VSS / RM_IHPSG13_1024x16_c2_1P_BLDRV +XA_BLTMUX<8> A_BLC<8> A_BLC_SEL A_BLT<8> A_BLT_SEL A_PRE_N A_SEL_P<8> A_WR_ONE ++ A_WR_ZERO VDD VSS / RM_IHPSG13_1024x16_c2_1P_BLDRV +XA_BLTMUX<7> A_BLC<7> A_BLC_SEL A_BLT<7> A_BLT_SEL A_PRE_N A_SEL_P<7> A_WR_ONE ++ A_WR_ZERO VDD VSS / RM_IHPSG13_1024x16_c2_1P_BLDRV +XA_BLTMUX<6> A_BLC<6> A_BLC_SEL A_BLT<6> A_BLT_SEL A_PRE_N A_SEL_P<6> A_WR_ONE ++ A_WR_ZERO VDD VSS / RM_IHPSG13_1024x16_c2_1P_BLDRV +XA_BLTMUX<5> A_BLC<5> A_BLC_SEL A_BLT<5> A_BLT_SEL A_PRE_N A_SEL_P<5> A_WR_ONE ++ A_WR_ZERO VDD VSS / RM_IHPSG13_1024x16_c2_1P_BLDRV +XA_BLTMUX<4> A_BLC<4> A_BLC_SEL A_BLT<4> A_BLT_SEL A_PRE_N A_SEL_P<4> A_WR_ONE ++ A_WR_ZERO VDD VSS / RM_IHPSG13_1024x16_c2_1P_BLDRV +XA_BLTMUX<3> A_BLC<3> A_BLC_SEL A_BLT<3> A_BLT_SEL A_PRE_N A_SEL_P<3> A_WR_ONE ++ A_WR_ZERO VDD VSS / RM_IHPSG13_1024x16_c2_1P_BLDRV +XA_BLTMUX<2> A_BLC<2> A_BLC_SEL A_BLT<2> A_BLT_SEL A_PRE_N A_SEL_P<2> A_WR_ONE ++ A_WR_ZERO VDD VSS / RM_IHPSG13_1024x16_c2_1P_BLDRV +XA_BLTMUX<1> A_BLC<1> A_BLC_SEL A_BLT<1> A_BLT_SEL A_PRE_N A_SEL_P<1> A_WR_ONE ++ A_WR_ZERO VDD VSS / RM_IHPSG13_1024x16_c2_1P_BLDRV +XA_BLTMUX<0> A_BLC<0> A_BLC_SEL A_BLT<0> A_BLT_SEL A_PRE_N A_SEL_P<0> A_WR_ONE ++ A_WR_ZERO VDD VSS / RM_IHPSG13_1024x16_c2_1P_BLDRV +XA_CAPS<17> VDD VSS / RSC_IHPSG13_FILLCAP4 +XA_CAPS<16> VDD VSS / RSC_IHPSG13_FILLCAP4 +XA_CAPS<15> VDD VSS / RSC_IHPSG13_FILLCAP4 +XA_CAPS<14> VDD VSS / RSC_IHPSG13_FILLCAP4 +XA_CAPS<13> VDD VSS / RSC_IHPSG13_FILLCAP4 +XA_CAPS<12> VDD VSS / RSC_IHPSG13_FILLCAP4 +XA_CAPS<11> VDD VSS / RSC_IHPSG13_FILLCAP4 +XA_CAPS<10> VDD VSS / RSC_IHPSG13_FILLCAP4 +XA_CAPS<9> VDD VSS / RSC_IHPSG13_FILLCAP4 +XA_CAPS<8> VDD VSS / RSC_IHPSG13_FILLCAP4 +XA_CAPS<7> VDD VSS / RSC_IHPSG13_FILLCAP4 +XA_CAPS<6> VDD VSS / RSC_IHPSG13_FILLCAP4 +XA_CAPS<5> VDD VSS / RSC_IHPSG13_FILLCAP4 +XA_CAPS<4> VDD VSS / RSC_IHPSG13_FILLCAP4 +XA_CAPS<3> VDD VSS / RSC_IHPSG13_FILLCAP4 +XA_CAPS<2> VDD VSS / RSC_IHPSG13_FILLCAP4 +XA_CAPS<1> VDD VSS / RSC_IHPSG13_FILLCAP4 +XA_I51 net19 A_DR_O VDD VSS / RSC_IHPSG13_INVX4 +XA_I78 A_RCLK_B_L A_SAE VDD VSS / RSC_IHPSG13_CBUFX2 +XA_I69 A_DCLK_L A_DCLK_B_L VDD VSS / RSC_IHPSG13_CINVX8 +XA_I50 A_WCLK_L A_WCLK_B_L VDD VSS / RSC_IHPSG13_CINVX8 +XA_EBUF A_RCLK_L A_RCLK_B_L VDD VSS / RSC_IHPSG13_CINVX8 +XA_I76 A_DI_N A_DO_WRITE_P A_WR_ZERO VDD VSS / RSC_IHPSG13_AND2X6 +XA_I75 A_DI_R A_DO_WRITE_P A_WR_ONE VDD VSS / RSC_IHPSG13_AND2X6 +XA_I83 A_BM_R A_BM_N VDD VSS / RSC_IHPSG13_INVX2 +XA_DEC3INV<31> net23<0> A_SEL_P<31> VDD VSS / RSC_IHPSG13_INVX2 +XA_DEC3INV<30> net23<1> A_SEL_P<30> VDD VSS / RSC_IHPSG13_INVX2 +XA_DEC3INV<29> net23<2> A_SEL_P<29> VDD VSS / RSC_IHPSG13_INVX2 +XA_DEC3INV<28> net23<3> A_SEL_P<28> VDD VSS / RSC_IHPSG13_INVX2 +XA_DEC3INV<27> net23<4> A_SEL_P<27> VDD VSS / RSC_IHPSG13_INVX2 +XA_DEC3INV<26> net23<5> A_SEL_P<26> VDD VSS / RSC_IHPSG13_INVX2 +XA_DEC3INV<25> net23<6> A_SEL_P<25> VDD VSS / RSC_IHPSG13_INVX2 +XA_DEC3INV<24> net23<7> A_SEL_P<24> VDD VSS / RSC_IHPSG13_INVX2 +XA_DEC3INV<23> net23<8> A_SEL_P<23> VDD VSS / RSC_IHPSG13_INVX2 +XA_DEC3INV<22> net23<9> A_SEL_P<22> VDD VSS / RSC_IHPSG13_INVX2 +XA_DEC3INV<21> net23<10> A_SEL_P<21> VDD VSS / RSC_IHPSG13_INVX2 +XA_DEC3INV<20> net23<11> A_SEL_P<20> VDD VSS / RSC_IHPSG13_INVX2 +XA_DEC3INV<19> net23<12> A_SEL_P<19> VDD VSS / RSC_IHPSG13_INVX2 +XA_DEC3INV<18> net23<13> A_SEL_P<18> VDD VSS / RSC_IHPSG13_INVX2 +XA_DEC3INV<17> net23<14> A_SEL_P<17> VDD VSS / RSC_IHPSG13_INVX2 +XA_DEC3INV<16> net23<15> A_SEL_P<16> VDD VSS / RSC_IHPSG13_INVX2 +XA_DEC3INV<15> net23<16> A_SEL_P<15> VDD VSS / RSC_IHPSG13_INVX2 +XA_DEC3INV<14> net23<17> A_SEL_P<14> VDD VSS / RSC_IHPSG13_INVX2 +XA_DEC3INV<13> net23<18> A_SEL_P<13> VDD VSS / RSC_IHPSG13_INVX2 +XA_DEC3INV<12> net23<19> A_SEL_P<12> VDD VSS / RSC_IHPSG13_INVX2 +XA_DEC3INV<11> net23<20> A_SEL_P<11> VDD VSS / RSC_IHPSG13_INVX2 +XA_DEC3INV<10> net23<21> A_SEL_P<10> VDD VSS / RSC_IHPSG13_INVX2 +XA_DEC3INV<9> net23<22> A_SEL_P<9> VDD VSS / RSC_IHPSG13_INVX2 +XA_DEC3INV<8> net23<23> A_SEL_P<8> VDD VSS / RSC_IHPSG13_INVX2 +XA_DEC3INV<7> net23<24> A_SEL_P<7> VDD VSS / RSC_IHPSG13_INVX2 +XA_DEC3INV<6> net23<25> A_SEL_P<6> VDD VSS / RSC_IHPSG13_INVX2 +XA_DEC3INV<5> net23<26> A_SEL_P<5> VDD VSS / RSC_IHPSG13_INVX2 +XA_DEC3INV<4> net23<27> A_SEL_P<4> VDD VSS / RSC_IHPSG13_INVX2 +XA_DEC3INV<3> net23<28> A_SEL_P<3> VDD VSS / RSC_IHPSG13_INVX2 +XA_DEC3INV<2> net23<29> A_SEL_P<2> VDD VSS / RSC_IHPSG13_INVX2 +XA_DEC3INV<1> net23<30> A_SEL_P<1> VDD VSS / RSC_IHPSG13_INVX2 +XA_DEC3INV<0> net23<31> A_SEL_P<0> VDD VSS / RSC_IHPSG13_INVX2 +XA_I49 A_DI_R A_DI_N VDD VSS / RSC_IHPSG13_INVX2 +XA_ISENSE A_SAE A_BLC_SEL A_BLT_SEL net19 net20 VDD VSS / ++ RSC_IHPSG13_DFPQD_MSAFFX2 +XA_DREG A_BIST_EN_I A_BIST_DW_I A_DCLK_B_L A_DW_I A_DI_R net22 VDD VSS ++ / RSC_IHPSG13_DFNQMX2IX1 +XA_BREG A_BIST_EN_I A_BIST_BM_I A_DCLK_B_L A_BM_I A_BM_R net21 VDD VSS ++ / RSC_IHPSG13_DFNQMX2IX1 +XA_DEC3<31> A_P1<1> A_P0<1> A_ADDR_DEC<7> net23<0> VDD VSS / ++ RSC_IHPSG13_NAND3X2 +XA_DEC3<30> A_P1<1> A_P0<1> A_ADDR_DEC<6> net23<1> VDD VSS / ++ RSC_IHPSG13_NAND3X2 +XA_DEC3<29> A_P1<1> A_P0<1> A_ADDR_DEC<5> net23<2> VDD VSS / ++ RSC_IHPSG13_NAND3X2 +XA_DEC3<28> A_P1<1> A_P0<1> A_ADDR_DEC<4> net23<3> VDD VSS / ++ RSC_IHPSG13_NAND3X2 +XA_DEC3<27> A_P1<1> A_P0<1> A_ADDR_DEC<3> net23<4> VDD VSS / ++ RSC_IHPSG13_NAND3X2 +XA_DEC3<26> A_P1<1> A_P0<1> A_ADDR_DEC<2> net23<5> VDD VSS / ++ RSC_IHPSG13_NAND3X2 +XA_DEC3<25> A_P1<1> A_P0<1> A_ADDR_DEC<1> net23<6> VDD VSS / ++ RSC_IHPSG13_NAND3X2 +XA_DEC3<24> A_P1<1> A_P0<1> A_ADDR_DEC<0> net23<7> VDD VSS / ++ RSC_IHPSG13_NAND3X2 +XA_DEC3<23> A_P1<1> A_N0<1> A_ADDR_DEC<7> net23<8> VDD VSS / ++ RSC_IHPSG13_NAND3X2 +XA_DEC3<22> A_P1<1> A_N0<1> A_ADDR_DEC<6> net23<9> VDD VSS / ++ RSC_IHPSG13_NAND3X2 +XA_DEC3<21> A_P1<1> A_N0<1> A_ADDR_DEC<5> net23<10> VDD VSS / ++ RSC_IHPSG13_NAND3X2 +XA_DEC3<20> A_P1<1> A_N0<1> A_ADDR_DEC<4> net23<11> VDD VSS / ++ RSC_IHPSG13_NAND3X2 +XA_DEC3<19> A_P1<1> A_N0<1> A_ADDR_DEC<3> net23<12> VDD VSS / ++ RSC_IHPSG13_NAND3X2 +XA_DEC3<18> A_P1<1> A_N0<1> A_ADDR_DEC<2> net23<13> VDD VSS / ++ RSC_IHPSG13_NAND3X2 +XA_DEC3<17> A_P1<1> A_N0<1> A_ADDR_DEC<1> net23<14> VDD VSS / ++ RSC_IHPSG13_NAND3X2 +XA_DEC3<16> A_P1<1> A_N0<1> A_ADDR_DEC<0> net23<15> VDD VSS / ++ RSC_IHPSG13_NAND3X2 +XA_DEC3<15> A_N1<0> A_P0<0> A_ADDR_DEC<7> net23<16> VDD VSS / ++ RSC_IHPSG13_NAND3X2 +XA_DEC3<14> A_N1<0> A_P0<0> A_ADDR_DEC<6> net23<17> VDD VSS / ++ RSC_IHPSG13_NAND3X2 +XA_DEC3<13> A_N1<0> A_P0<0> A_ADDR_DEC<5> net23<18> VDD VSS / ++ RSC_IHPSG13_NAND3X2 +XA_DEC3<12> A_N1<0> A_P0<0> A_ADDR_DEC<4> net23<19> VDD VSS / ++ RSC_IHPSG13_NAND3X2 +XA_DEC3<11> A_N1<0> A_P0<0> A_ADDR_DEC<3> net23<20> VDD VSS / ++ RSC_IHPSG13_NAND3X2 +XA_DEC3<10> A_N1<0> A_P0<0> A_ADDR_DEC<2> net23<21> VDD VSS / ++ RSC_IHPSG13_NAND3X2 +XA_DEC3<9> A_N1<0> A_P0<0> A_ADDR_DEC<1> net23<22> VDD VSS / ++ RSC_IHPSG13_NAND3X2 +XA_DEC3<8> A_N1<0> A_P0<0> A_ADDR_DEC<0> net23<23> VDD VSS / ++ RSC_IHPSG13_NAND3X2 +XA_DEC3<7> A_N1<0> A_N0<0> A_ADDR_DEC<7> net23<24> VDD VSS / ++ RSC_IHPSG13_NAND3X2 +XA_DEC3<6> A_N1<0> A_N0<0> A_ADDR_DEC<6> net23<25> VDD VSS / ++ RSC_IHPSG13_NAND3X2 +XA_DEC3<5> A_N1<0> A_N0<0> A_ADDR_DEC<5> net23<26> VDD VSS / ++ RSC_IHPSG13_NAND3X2 +XA_DEC3<4> A_N1<0> A_N0<0> A_ADDR_DEC<4> net23<27> VDD VSS / ++ RSC_IHPSG13_NAND3X2 +XA_DEC3<3> A_N1<0> A_N0<0> A_ADDR_DEC<3> net23<28> VDD VSS / ++ RSC_IHPSG13_NAND3X2 +XA_DEC3<2> A_N1<0> A_N0<0> A_ADDR_DEC<2> net23<29> VDD VSS / ++ RSC_IHPSG13_NAND3X2 +XA_DEC3<1> A_N1<0> A_N0<0> A_ADDR_DEC<1> net23<30> VDD VSS / ++ RSC_IHPSG13_NAND3X2 +XA_DEC3<0> A_N1<0> A_N0<0> A_ADDR_DEC<0> net23<31> VDD VSS / ++ RSC_IHPSG13_NAND3X2 +XA_I89 A_DCLK_B_L A_DCLK_B_R / RSC_IHPSG13_MET3RES +XA_I91 A_RCLK_B_L A_RCLK_B_R / RSC_IHPSG13_MET3RES +XA_I90 A_WCLK_B_L A_WCLK_B_R / RSC_IHPSG13_MET3RES +XA_I88 A_DCLK_L A_DCLK_R / RSC_IHPSG13_MET3RES +XA_I87 A_WCLK_L A_WCLK_R / RSC_IHPSG13_MET3RES +XA_R2 A_RCLK_L A_RCLK_R / RSC_IHPSG13_MET3RES +XA_BM_TIEH A_TIEH_O VDD VSS / RSC_IHPSG13_TIEH +.ENDS + +.SUBCKT RM_IHPSG13_1024x16_c2_1P_COLDRV13X12 ADDR_COL_I<1> ADDR_COL_I<0> ADDR_COL_O<1> ++ ADDR_COL_O<0> ADDR_DEC_I<7> ADDR_DEC_I<6> ADDR_DEC_I<5> ADDR_DEC_I<4> ++ ADDR_DEC_I<3> ADDR_DEC_I<2> ADDR_DEC_I<1> ADDR_DEC_I<0> ADDR_DEC_O<7> ++ ADDR_DEC_O<6> ADDR_DEC_O<5> ADDR_DEC_O<4> ADDR_DEC_O<3> ADDR_DEC_O<2> ++ ADDR_DEC_O<1> ADDR_DEC_O<0> DCLK_I DCLK_O RCLK_I RCLK_O WCLK_I WCLK_O ++ VDD VSS +XI1<1> VDD VSS / RSC_IHPSG13_FILLCAP4 +XI1<0> VDD VSS / RSC_IHPSG13_FILLCAP4 +XI0<1> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI0<0> VDD VSS / RSC_IHPSG13_FILLCAP8 +XADDR_COL_DRV<1> ADDR_COL_I<1> ADDR_COL_O<1> VDD VSS / ++ RSC_IHPSG13_CBUFX12 +XADDR_COL_DRV<0> ADDR_COL_I<0> ADDR_COL_O<0> VDD VSS / ++ RSC_IHPSG13_CBUFX12 +XADDR_DEC_DRV<7> ADDR_DEC_I<7> ADDR_DEC_O<7> VDD VSS / ++ RSC_IHPSG13_CBUFX12 +XADDR_DEC_DRV<6> ADDR_DEC_I<6> ADDR_DEC_O<6> VDD VSS / ++ RSC_IHPSG13_CBUFX12 +XADDR_DEC_DRV<5> ADDR_DEC_I<5> ADDR_DEC_O<5> VDD VSS / ++ RSC_IHPSG13_CBUFX12 +XADDR_DEC_DRV<4> ADDR_DEC_I<4> ADDR_DEC_O<4> VDD VSS / ++ RSC_IHPSG13_CBUFX12 +XADDR_DEC_DRV<3> ADDR_DEC_I<3> ADDR_DEC_O<3> VDD VSS / ++ RSC_IHPSG13_CBUFX12 +XADDR_DEC_DRV<2> ADDR_DEC_I<2> ADDR_DEC_O<2> VDD VSS / ++ RSC_IHPSG13_CBUFX12 +XADDR_DEC_DRV<1> ADDR_DEC_I<1> ADDR_DEC_O<1> VDD VSS / ++ RSC_IHPSG13_CBUFX12 +XADDR_DEC_DRV<0> ADDR_DEC_I<0> ADDR_DEC_O<0> VDD VSS / ++ RSC_IHPSG13_CBUFX12 +XDCLK_DRV DCLK_I DCLK_O VDD VSS / RSC_IHPSG13_CBUFX12 +XRCLK_DRV RCLK_I RCLK_O VDD VSS / RSC_IHPSG13_CBUFX12 +XWCLK_DRV WCLK_I WCLK_O VDD VSS / RSC_IHPSG13_CBUFX12 +.ENDS +.SUBCKT RM_IHPSG13_1024x16_c2_1P_WLDRV16X12 A<15> A<14> A<13> A<12> A<11> A<10> A<9> A<8> ++ A<7> A<6> A<5> A<4> A<3> A<2> A<1> A<0> Z<15> Z<14> Z<13> Z<12> Z<11> Z<10> ++ Z<9> Z<8> Z<7> Z<6> Z<5> Z<4> Z<3> Z<2> Z<1> Z<0> VDD VSS +XBUF<15> A<15> Z<15> VDD VSS / RSC_IHPSG13_WLDRVX12 +XBUF<14> A<14> Z<14> VDD VSS / RSC_IHPSG13_WLDRVX12 +XBUF<13> A<13> Z<13> VDD VSS / RSC_IHPSG13_WLDRVX12 +XBUF<12> A<12> Z<12> VDD VSS / RSC_IHPSG13_WLDRVX12 +XBUF<11> A<11> Z<11> VDD VSS / RSC_IHPSG13_WLDRVX12 +XBUF<10> A<10> Z<10> VDD VSS / RSC_IHPSG13_WLDRVX12 +XBUF<9> A<9> Z<9> VDD VSS / RSC_IHPSG13_WLDRVX12 +XBUF<8> A<8> Z<8> VDD VSS / RSC_IHPSG13_WLDRVX12 +XBUF<7> A<7> Z<7> VDD VSS / RSC_IHPSG13_WLDRVX12 +XBUF<6> A<6> Z<6> VDD VSS / RSC_IHPSG13_WLDRVX12 +XBUF<5> A<5> Z<5> VDD VSS / RSC_IHPSG13_WLDRVX12 +XBUF<4> A<4> Z<4> VDD VSS / RSC_IHPSG13_WLDRVX12 +XBUF<3> A<3> Z<3> VDD VSS / RSC_IHPSG13_WLDRVX12 +XBUF<2> A<2> Z<2> VDD VSS / RSC_IHPSG13_WLDRVX12 +XBUF<1> A<1> Z<1> VDD VSS / RSC_IHPSG13_WLDRVX12 +XBUF<0> A<0> Z<0> VDD VSS / RSC_IHPSG13_WLDRVX12 +.ENDS + + + +.SUBCKT RM_IHPSG13_1024x16_c2_2P_COLDRV13X8 ADDR_COL_I<1> ADDR_COL_I<0> ADDR_COL_O<1> ++ ADDR_COL_O<0> ADDR_DEC_I<7> ADDR_DEC_I<6> ADDR_DEC_I<5> ADDR_DEC_I<4> ++ ADDR_DEC_I<3> ADDR_DEC_I<2> ADDR_DEC_I<1> ADDR_DEC_I<0> ADDR_DEC_O<7> ++ ADDR_DEC_O<6> ADDR_DEC_O<5> ADDR_DEC_O<4> ADDR_DEC_O<3> ADDR_DEC_O<2> ++ ADDR_DEC_O<1> ADDR_DEC_O<0> DCLK_I DCLK_O RCLK_I RCLK_O WCLK_I WCLK_O ++ VDD VSS +XI0<5> VDD VSS / RSC_IHPSG13_FILLCAP4 +XI0<4> VDD VSS / RSC_IHPSG13_FILLCAP4 +XI0<3> VDD VSS / RSC_IHPSG13_FILLCAP4 +XI0<2> VDD VSS / RSC_IHPSG13_FILLCAP4 +XI0<1> VDD VSS / RSC_IHPSG13_FILLCAP4 +XWCLK_DRV WCLK_I WCLK_O VDD VSS / RSC_IHPSG13_CBUFX8 +XRCLK_DRV RCLK_I RCLK_O VDD VSS / RSC_IHPSG13_CBUFX8 +XDCLK_DRV DCLK_I DCLK_O VDD VSS / RSC_IHPSG13_CBUFX8 +XADDR_COL_DRV<1> ADDR_COL_I<1> ADDR_COL_O<1> VDD VSS / ++ RSC_IHPSG13_CBUFX8 +XADDR_COL_DRV<0> ADDR_COL_I<0> ADDR_COL_O<0> VDD VSS / ++ RSC_IHPSG13_CBUFX8 +XADDR_DEC_DRV<7> ADDR_DEC_I<7> ADDR_DEC_O<7> VDD VSS / ++ RSC_IHPSG13_CBUFX8 +XADDR_DEC_DRV<6> ADDR_DEC_I<6> ADDR_DEC_O<6> VDD VSS / ++ RSC_IHPSG13_CBUFX8 +XADDR_DEC_DRV<5> ADDR_DEC_I<5> ADDR_DEC_O<5> VDD VSS / ++ RSC_IHPSG13_CBUFX8 +XADDR_DEC_DRV<4> ADDR_DEC_I<4> ADDR_DEC_O<4> VDD VSS / ++ RSC_IHPSG13_CBUFX8 +XADDR_DEC_DRV<3> ADDR_DEC_I<3> ADDR_DEC_O<3> VDD VSS / ++ RSC_IHPSG13_CBUFX8 +XADDR_DEC_DRV<2> ADDR_DEC_I<2> ADDR_DEC_O<2> VDD VSS / ++ RSC_IHPSG13_CBUFX8 +XADDR_DEC_DRV<1> ADDR_DEC_I<1> ADDR_DEC_O<1> VDD VSS / ++ RSC_IHPSG13_CBUFX8 +XADDR_DEC_DRV<0> ADDR_DEC_I<0> ADDR_DEC_O<0> VDD VSS / ++ RSC_IHPSG13_CBUFX8 +XI1<3> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI1<2> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI1<1> VDD VSS / RSC_IHPSG13_FILLCAP8 +.ENDS +.SUBCKT RSC_IHPSG13_WLDRVX8 A Z VDD VSS +MN1 Z net6 VSS VSS sg13_lv_nmos m=1 w=1.41u l=130.00n ng=2 nrd=0 nrs=0 +MN0 net6 A VSS VSS sg13_lv_nmos m=1 w=1.8u l=130.00n ng=2 nrd=0 nrs=0 +MP1 Z net6 VDD VDD sg13_lv_pmos m=1 w=6.48u l=130.00n ng=4 nrd=0 nrs=0 +MP0 net6 A VDD VDD sg13_lv_pmos m=1 w=900.0n l=130.00n ng=1 nrd=0 nrs=0 +.ENDS +.SUBCKT RM_IHPSG13_1024x16_c2_2P_WLDRV16X8 A<15> A<14> A<13> A<12> A<11> A<10> A<9> A<8> ++ A<7> A<6> A<5> A<4> A<3> A<2> A<1> A<0> Z<15> Z<14> Z<13> Z<12> Z<11> Z<10> ++ Z<9> Z<8> Z<7> Z<6> Z<5> Z<4> Z<3> Z<2> Z<1> Z<0> VDD VSS +XBUF<15> A<15> Z<15> VDD VSS / RSC_IHPSG13_WLDRVX8 +XBUF<14> A<14> Z<14> VDD VSS / RSC_IHPSG13_WLDRVX8 +XBUF<13> A<13> Z<13> VDD VSS / RSC_IHPSG13_WLDRVX8 +XBUF<12> A<12> Z<12> VDD VSS / RSC_IHPSG13_WLDRVX8 +XBUF<11> A<11> Z<11> VDD VSS / RSC_IHPSG13_WLDRVX8 +XBUF<10> A<10> Z<10> VDD VSS / RSC_IHPSG13_WLDRVX8 +XBUF<9> A<9> Z<9> VDD VSS / RSC_IHPSG13_WLDRVX8 +XBUF<8> A<8> Z<8> VDD VSS / RSC_IHPSG13_WLDRVX8 +XBUF<7> A<7> Z<7> VDD VSS / RSC_IHPSG13_WLDRVX8 +XBUF<6> A<6> Z<6> VDD VSS / RSC_IHPSG13_WLDRVX8 +XBUF<5> A<5> Z<5> VDD VSS / RSC_IHPSG13_WLDRVX8 +XBUF<4> A<4> Z<4> VDD VSS / RSC_IHPSG13_WLDRVX8 +XBUF<3> A<3> Z<3> VDD VSS / RSC_IHPSG13_WLDRVX8 +XBUF<2> A<2> Z<2> VDD VSS / RSC_IHPSG13_WLDRVX8 +XBUF<1> A<1> Z<1> VDD VSS / RSC_IHPSG13_WLDRVX8 +XBUF<0> A<0> Z<0> VDD VSS / RSC_IHPSG13_WLDRVX8 +.ENDS + + + +.SUBCKT RM_IHPSG13_1024x16_c2_2P_COLDEC2 ACLK_N ADDR<1> ADDR<0> ADDR_COL<1> ADDR_COL<0> ++ ADDR_DEC<7> ADDR_DEC<6> ADDR_DEC<5> ADDR_DEC<4> ADDR_DEC<3> ADDR_DEC<2> ++ ADDR_DEC<1> ADDR_DEC<0> BIST_ADDR<1> BIST_ADDR<0> BIST_EN_I VDD VSS +XI16<17> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI16<16> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI16<15> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI16<14> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI16<13> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI16<12> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI16<11> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI16<10> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI16<9> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI16<8> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI16<7> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI16<6> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI16<5> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI16<4> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI16<3> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI16<2> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI16<1> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI18<24> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI18<23> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI18<22> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI18<21> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI18<20> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI18<19> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI18<18> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI18<17> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI18<16> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI18<15> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI18<14> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI18<13> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI18<12> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI18<11> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI18<10> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI18<9> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI18<8> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI18<7> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI18<6> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI18<5> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI18<4> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI18<3> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI18<2> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI18<1> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI1<3> PADR<0> PADR<1> addr_n<3> VDD VSS / RSC_IHPSG13_NAND2X2 +XI1<2> NADR<0> PADR<1> addr_n<2> VDD VSS / RSC_IHPSG13_NAND2X2 +XI1<1> PADR<0> NADR<1> addr_n<1> VDD VSS / RSC_IHPSG13_NAND2X2 +XI1<0> NADR<0> NADR<1> addr_n<0> VDD VSS / RSC_IHPSG13_NAND2X2 +XI17<1> ADDR_COL<1> VDD VSS / RSC_IHPSG13_TIEL +XI17<0> ADDR_COL<0> VDD VSS / RSC_IHPSG13_TIEL +XI14<3> ADDR_DEC<7> VDD VSS / RSC_IHPSG13_TIEL +XI14<2> ADDR_DEC<6> VDD VSS / RSC_IHPSG13_TIEL +XI14<1> ADDR_DEC<5> VDD VSS / RSC_IHPSG13_TIEL +XI14<0> ADDR_DEC<4> VDD VSS / RSC_IHPSG13_TIEL +XI13<1> NADR<1> PADR<1> VDD VSS / RSC_IHPSG13_INVX2 +XI13<0> NADR<0> PADR<0> VDD VSS / RSC_IHPSG13_INVX2 +XI3<1> padr_int<1> NADR<1> VDD VSS / RSC_IHPSG13_INVX2 +XI3<0> padr_int<0> NADR<0> VDD VSS / RSC_IHPSG13_INVX2 +XI2<3> addr_n<3> ADDR_DEC<3> VDD VSS / RSC_IHPSG13_INVX2 +XI2<2> addr_n<2> ADDR_DEC<2> VDD VSS / RSC_IHPSG13_INVX2 +XI2<1> addr_n<1> ADDR_DEC<1> VDD VSS / RSC_IHPSG13_INVX2 +XI2<0> addr_n<0> ADDR_DEC<0> VDD VSS / RSC_IHPSG13_INVX2 +XDFF<1> BIST_EN_I BIST_ADDR<1> ACLK_N ADDR<1> padr_int<1> net12<0> VDD ++ VSS / RSC_IHPSG13_DFNQMX2IX1 +XDFF<0> BIST_EN_I BIST_ADDR<0> ACLK_N ADDR<0> padr_int<0> net12<1> VDD ++ VSS / RSC_IHPSG13_DFNQMX2IX1 +XI15<5> VDD VSS / RSC_IHPSG13_FILLCAP4 +XI15<4> VDD VSS / RSC_IHPSG13_FILLCAP4 +XI15<3> VDD VSS / RSC_IHPSG13_FILLCAP4 +XI15<2> VDD VSS / RSC_IHPSG13_FILLCAP4 +XI15<1> VDD VSS / RSC_IHPSG13_FILLCAP4 +XI19<4> VDD VSS / RSC_IHPSG13_FILLCAP4 +XI19<3> VDD VSS / RSC_IHPSG13_FILLCAP4 +XI19<2> VDD VSS / RSC_IHPSG13_FILLCAP4 +XI19<1> VDD VSS / RSC_IHPSG13_FILLCAP4 +.ENDS +.SUBCKT RM_IHPSG13_1024x16_c2_2P_COLCTRL2 A_ADDR_DEC<3> A_ADDR_DEC<2> A_ADDR_DEC<1> ++ A_ADDR_DEC<0> A_BIST_BM_I A_BIST_DW_I A_BIST_EN_I A_BLC<3> A_BLC<2> A_BLC<1> ++ A_BLC<0> A_BLT<3> A_BLT<2> A_BLT<1> A_BLT<0> A_BM_I A_DCLK_B_L A_DCLK_B_R ++ A_DCLK_L A_DCLK_R A_DR_O A_DW_I A_RCLK_B_L A_RCLK_B_R A_RCLK_L A_RCLK_R ++ A_TIEH_O A_WCLK_B_L A_WCLK_B_R A_WCLK_L A_WCLK_R B_ADDR_DEC<3> B_ADDR_DEC<2> ++ B_ADDR_DEC<1> B_ADDR_DEC<0> B_BIST_BM_I B_BIST_DW_I B_BIST_EN_I B_BLC<3> ++ B_BLC<2> B_BLC<1> B_BLC<0> B_BLT<3> B_BLT<2> B_BLT<1> B_BLT<0> B_BM_I ++ B_DCLK_B_L B_DCLK_B_R B_DCLK_L B_DCLK_R B_DR_O B_DW_I B_RCLK_B_L B_RCLK_B_R ++ B_RCLK_L B_RCLK_R B_TIEH_O B_WCLK_B_L B_WCLK_B_R B_WCLK_L B_WCLK_R VDD ++ VSS +XB_DREG B_BIST_EN_I B_BIST_DW_I B_DCLK_B_L B_DW_I B_DI_R net046 VDD ++ VSS / RSC_IHPSG13_DFNQMX2IX1 +XB_BREG B_BIST_EN_I B_BIST_BM_I B_DCLK_B_L B_BM_I B_BM_R net045 VDD ++ VSS / RSC_IHPSG13_DFNQMX2IX1 +XA_DREG A_BIST_EN_I A_BIST_DW_I A_DCLK_B_L A_DW_I A_DI_R net22 VDD VSS ++ / RSC_IHPSG13_DFNQMX2IX1 +XA_BREG A_BIST_EN_I A_BIST_BM_I A_DCLK_B_L A_BM_I A_BM_R net23 VDD VSS ++ / RSC_IHPSG13_DFNQMX2IX1 +XB_CAPS VDD VSS / RSC_IHPSG13_FILLCAP4 +XA_CAPS VDD VSS / RSC_IHPSG13_FILLCAP4 +XB_I75 B_DI_R B_DO_WRITE_P B_WR_ONE VDD VSS / RSC_IHPSG13_AND2X2 +XB_I80 B_RCLK_B_L B_WCLK_B_L net041 VDD VSS / RSC_IHPSG13_AND2X2 +XB_I76 B_DI_N B_DO_WRITE_P B_WR_ZERO VDD VSS / RSC_IHPSG13_AND2X2 +XA_I80 A_RCLK_B_L A_WCLK_B_L net21 VDD VSS / RSC_IHPSG13_AND2X2 +XA_I75 A_DI_R A_DO_WRITE_P A_WR_ONE VDD VSS / RSC_IHPSG13_AND2X2 +XA_I76 A_DI_N A_DO_WRITE_P A_WR_ZERO VDD VSS / RSC_IHPSG13_AND2X2 +XB_I44 B_WCLK_B_L B_BM_N B_DO_WRITE_P VDD VSS / RSC_IHPSG13_NOR2X2 +XA_I44 A_WCLK_B_L A_BM_N A_DO_WRITE_P VDD VSS / RSC_IHPSG13_NOR2X2 +XB_I81 net041 B_PRE_N VDD VSS / RSC_IHPSG13_CINVX4_WN +XA_I81 net21 A_PRE_N VDD VSS / RSC_IHPSG13_CINVX4_WN +XB_BM_TIEH B_TIEH_O VDD VSS / RSC_IHPSG13_TIEH +XA_BM_TIEH A_TIEH_O VDD VSS / RSC_IHPSG13_TIEH +XA_I89 A_DCLK_B_L A_DCLK_B_R / RSC_IHPSG13_MET3RES +XA_I88 A_DCLK_L A_DCLK_R / RSC_IHPSG13_MET3RES +XA_I87 A_WCLK_L A_WCLK_R / RSC_IHPSG13_MET3RES +XA_I91 A_RCLK_B_L A_RCLK_B_R / RSC_IHPSG13_MET3RES +XB_I87 B_WCLK_L B_WCLK_R / RSC_IHPSG13_MET3RES +XB_I88 B_DCLK_L B_DCLK_R / RSC_IHPSG13_MET3RES +XB_I89 B_DCLK_B_L B_DCLK_B_R / RSC_IHPSG13_MET3RES +XB_I90 B_WCLK_B_L B_WCLK_B_R / RSC_IHPSG13_MET3RES +XB_R2 B_RCLK_L B_RCLK_R / RSC_IHPSG13_MET3RES +XB_I91 B_RCLK_B_L B_RCLK_B_R / RSC_IHPSG13_MET3RES +XA_R2 A_RCLK_L A_RCLK_R / RSC_IHPSG13_MET3RES +XA_I90 A_WCLK_B_L A_WCLK_B_R / RSC_IHPSG13_MET3RES +XAB_BLMUX A_BLC<3> A_BLC<2> A_BLC<1> A_BLC<0> A_BLC_SEL A_BLT<3> A_BLT<2> ++ A_BLT<1> A_BLT<0> A_BLT_SEL A_PRE_N A_ADDR_DEC<3> A_ADDR_DEC<2> ++ A_ADDR_DEC<1> A_ADDR_DEC<0> A_WR_ONE A_WR_ZERO B_BLC<3> B_BLC<2> B_BLC<1> ++ B_BLC<0> B_BLC_SEL B_BLT<3> B_BLT<2> B_BLT<1> B_BLT<0> B_BLT_SEL B_PRE_N ++ B_ADDR_DEC<3> B_ADDR_DEC<2> B_ADDR_DEC<1> B_ADDR_DEC<0> B_WR_ONE B_WR_ZERO ++ VDD VSS / RM_IHPSG13_1024x16_c2_2P_BLDRV +XB_ISENSE B_SAE B_BLC_SEL B_BLT_SEL net039 net040 VDD VSS / ++ RSC_IHPSG13_DFPQD_MSAFFX2 +XA_ISENSE A_SAE A_BLC_SEL A_BLT_SEL net19 net20 VDD VSS / ++ RSC_IHPSG13_DFPQD_MSAFFX2 +XB_I78 B_RCLK_B_L B_SAE VDD VSS / RSC_IHPSG13_CBUFX2 +XA_I78 A_RCLK_B_L A_SAE VDD VSS / RSC_IHPSG13_CBUFX2 +XB_I83 B_BM_R B_BM_N VDD VSS / RSC_IHPSG13_INVX2 +XB_I49 B_DI_R B_DI_N VDD VSS / RSC_IHPSG13_INVX2 +XA_I83 A_BM_R A_BM_N VDD VSS / RSC_IHPSG13_INVX2 +XA_I49 A_DI_R A_DI_N VDD VSS / RSC_IHPSG13_INVX2 +XB_I51 net039 B_DR_O VDD VSS / RSC_IHPSG13_INVX4 +XA_I51 net19 A_DR_O VDD VSS / RSC_IHPSG13_INVX4 +XA_I69 A_DCLK_L A_DCLK_B_L VDD VSS / RSC_IHPSG13_CINVX2 +XA_I50 A_WCLK_L A_WCLK_B_L VDD VSS / RSC_IHPSG13_CINVX2 +XA_EBUF A_RCLK_L A_RCLK_B_L VDD VSS / RSC_IHPSG13_CINVX2 +XB_EBUF B_RCLK_L B_RCLK_B_L VDD VSS / RSC_IHPSG13_CINVX2 +XB_I50 B_WCLK_L B_WCLK_B_L VDD VSS / RSC_IHPSG13_CINVX2 +XB_I69 B_DCLK_L B_DCLK_B_L VDD VSS / RSC_IHPSG13_CINVX2 +.ENDS +.SUBCKT RM_IHPSG13_1024x16_c2_2P_COLDRV13_FILL4C2 VDD VSS +XI0<2> VDD VSS / RSC_IHPSG13_FILLCAP4 +XI0<1> VDD VSS / RSC_IHPSG13_FILLCAP4 +.ENDS + + +.SUBCKT RM_IHPSG13_1024x16_c2_2P_ROWDEC7 ADDR_N_I<6> ADDR_N_I<5> ADDR_N_I<4> ADDR_N_I<3> ++ ADDR_N_I<2> ADDR_N_I<1> ADDR_N_I<0> CS_I ECLK_I WL_O<127> WL_O<126> ++ WL_O<125> WL_O<124> WL_O<123> WL_O<122> WL_O<121> WL_O<120> WL_O<119> ++ WL_O<118> WL_O<117> WL_O<116> WL_O<115> WL_O<114> WL_O<113> WL_O<112> ++ WL_O<111> WL_O<110> WL_O<109> WL_O<108> WL_O<107> WL_O<106> WL_O<105> ++ WL_O<104> WL_O<103> WL_O<102> WL_O<101> WL_O<100> WL_O<99> WL_O<98> WL_O<97> ++ WL_O<96> WL_O<95> WL_O<94> WL_O<93> WL_O<92> WL_O<91> WL_O<90> WL_O<89> ++ WL_O<88> WL_O<87> WL_O<86> WL_O<85> WL_O<84> WL_O<83> WL_O<82> WL_O<81> ++ WL_O<80> WL_O<79> WL_O<78> WL_O<77> WL_O<76> WL_O<75> WL_O<74> WL_O<73> ++ WL_O<72> WL_O<71> WL_O<70> WL_O<69> WL_O<68> WL_O<67> WL_O<66> WL_O<65> ++ WL_O<64> WL_O<63> WL_O<62> WL_O<61> WL_O<60> WL_O<59> WL_O<58> WL_O<57> ++ WL_O<56> WL_O<55> WL_O<54> WL_O<53> WL_O<52> WL_O<51> WL_O<50> WL_O<49> ++ WL_O<48> WL_O<47> WL_O<46> WL_O<45> WL_O<44> WL_O<43> WL_O<42> WL_O<41> ++ WL_O<40> WL_O<39> WL_O<38> WL_O<37> WL_O<36> WL_O<35> WL_O<34> WL_O<33> ++ WL_O<32> WL_O<31> WL_O<30> WL_O<29> WL_O<28> WL_O<27> WL_O<26> WL_O<25> ++ WL_O<24> WL_O<23> WL_O<22> WL_O<21> WL_O<20> WL_O<19> WL_O<18> WL_O<17> ++ WL_O<16> WL_O<15> WL_O<14> WL_O<13> WL_O<12> WL_O<11> WL_O<10> WL_O<9> ++ WL_O<8> WL_O<7> WL_O<6> WL_O<5> WL_O<4> WL_O<3> WL_O<2> WL_O<1> WL_O<0> ++ VDD VSS +XSEL<7> ADDR_N_I<3> ADDR_N_I<2> ADDR_N_I<1> ADDR_N_I<0> CS00<7> ECLK_H<7> ++ ECLK_H<8> ECLK_B<7> ECLK_B<8> WL_O<127> WL_O<126> WL_O<125> WL_O<124> ++ WL_O<123> WL_O<122> WL_O<121> WL_O<120> WL_O<119> WL_O<118> WL_O<117> ++ WL_O<116> WL_O<115> WL_O<114> WL_O<113> WL_O<112> VDD VSS / ++ RM_IHPSG13_1024x16_c2_2P_DEC04 +XSEL<6> ADDR_N_I<3> ADDR_N_I<2> ADDR_N_I<1> ADDR_N_I<0> CS00<6> ECLK_H<6> ++ ECLK_H<7> ECLK_B<6> ECLK_B<7> WL_O<111> WL_O<110> WL_O<109> WL_O<108> ++ WL_O<107> WL_O<106> WL_O<105> WL_O<104> WL_O<103> WL_O<102> WL_O<101> ++ WL_O<100> WL_O<99> WL_O<98> WL_O<97> WL_O<96> VDD VSS / ++ RM_IHPSG13_1024x16_c2_2P_DEC04 +XSEL<5> ADDR_N_I<3> ADDR_N_I<2> ADDR_N_I<1> ADDR_N_I<0> CS00<5> ECLK_H<5> ++ ECLK_H<6> ECLK_B<5> ECLK_B<6> WL_O<95> WL_O<94> WL_O<93> WL_O<92> WL_O<91> ++ WL_O<90> WL_O<89> WL_O<88> WL_O<87> WL_O<86> WL_O<85> WL_O<84> WL_O<83> ++ WL_O<82> WL_O<81> WL_O<80> VDD VSS / RM_IHPSG13_1024x16_c2_2P_DEC04 +XSEL<4> ADDR_N_I<3> ADDR_N_I<2> ADDR_N_I<1> ADDR_N_I<0> CS00<4> ECLK_H<4> ++ ECLK_H<5> ECLK_B<4> ECLK_B<5> WL_O<79> WL_O<78> WL_O<77> WL_O<76> WL_O<75> ++ WL_O<74> WL_O<73> WL_O<72> WL_O<71> WL_O<70> WL_O<69> WL_O<68> WL_O<67> ++ WL_O<66> WL_O<65> WL_O<64> VDD VSS / RM_IHPSG13_1024x16_c2_2P_DEC04 +XSEL<3> ADDR_N_I<3> ADDR_N_I<2> ADDR_N_I<1> ADDR_N_I<0> CS00<3> ECLK_H<3> ++ ECLK_H<4> ECLK_B<3> ECLK_B<4> WL_O<63> WL_O<62> WL_O<61> WL_O<60> WL_O<59> ++ WL_O<58> WL_O<57> WL_O<56> WL_O<55> WL_O<54> WL_O<53> WL_O<52> WL_O<51> ++ WL_O<50> WL_O<49> WL_O<48> VDD VSS / RM_IHPSG13_1024x16_c2_2P_DEC04 +XSEL<2> ADDR_N_I<3> ADDR_N_I<2> ADDR_N_I<1> ADDR_N_I<0> CS00<2> ECLK_H<2> ++ ECLK_H<3> ECLK_B<2> ECLK_B<3> WL_O<47> WL_O<46> WL_O<45> WL_O<44> WL_O<43> ++ WL_O<42> WL_O<41> WL_O<40> WL_O<39> WL_O<38> WL_O<37> WL_O<36> WL_O<35> ++ WL_O<34> WL_O<33> WL_O<32> VDD VSS / RM_IHPSG13_1024x16_c2_2P_DEC04 +XSEL<1> ADDR_N_I<3> ADDR_N_I<2> ADDR_N_I<1> ADDR_N_I<0> CS00<1> ECLK_H<1> ++ ECLK_H<2> ECLK_B<1> ECLK_B<2> WL_O<31> WL_O<30> WL_O<29> WL_O<28> WL_O<27> ++ WL_O<26> WL_O<25> WL_O<24> WL_O<23> WL_O<22> WL_O<21> WL_O<20> WL_O<19> ++ WL_O<18> WL_O<17> WL_O<16> VDD VSS / RM_IHPSG13_1024x16_c2_2P_DEC04 +XSEL<0> ADDR_N_I<3> ADDR_N_I<2> ADDR_N_I<1> ADDR_N_I<0> CS00<0> ECLK_I ++ ECLK_H<1> ECLK_B<0> ECLK_B<1> WL_O<15> WL_O<14> WL_O<13> WL_O<12> WL_O<11> ++ WL_O<10> WL_O<9> WL_O<8> WL_O<7> WL_O<6> WL_O<5> WL_O<4> WL_O<3> WL_O<2> ++ WL_O<1> WL_O<0> VDD VSS / RM_IHPSG13_1024x16_c2_2P_DEC04 +XDEC11<1> ADDR_N_I<5> ADDR_N_I<4> CS04<1> CS00<7> VDD VSS / ++ RM_IHPSG13_1024x16_c2_2P_DEC03 +XDEC11<0> ADDR_N_I<5> ADDR_N_I<4> CS04<0> CS00<3> VDD VSS / ++ RM_IHPSG13_1024x16_c2_2P_DEC03 +XDEC01<2> ADDR_N_I<7> ADDR_N_I<6> CS_I CS04<1> VDD VSS / ++ RM_IHPSG13_1024x16_c2_2P_DEC01 +XDEC01<1> ADDR_N_I<5> ADDR_N_I<4> CS04<1> CS00<5> VDD VSS / ++ RM_IHPSG13_1024x16_c2_2P_DEC01 +XDEC01<0> ADDR_N_I<5> ADDR_N_I<4> CS04<0> CS00<1> VDD VSS / ++ RM_IHPSG13_1024x16_c2_2P_DEC01 +XL2<66> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<65> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<64> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<63> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<62> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<61> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<60> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<59> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<58> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<57> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<56> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<55> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<54> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<53> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<52> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<51> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<50> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<49> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<48> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<47> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<46> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<45> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<44> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<43> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<42> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<41> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<40> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<39> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<38> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<37> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<36> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<35> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<34> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<33> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<32> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<31> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<30> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<29> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<28> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<27> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<26> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<25> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<24> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<23> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<22> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<21> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<20> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<19> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<18> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<17> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<16> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<15> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<14> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<13> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<12> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<11> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<10> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<9> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<8> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<7> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<6> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<5> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<4> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<3> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<2> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<1> VDD VSS / RSC_IHPSG13_FILLCAP8 +XDEC10<1> ADDR_N_I<5> ADDR_N_I<4> CS04<1> CS00<6> VDD VSS / ++ RM_IHPSG13_1024x16_c2_2P_DEC02 +XDEC10<0> ADDR_N_I<5> ADDR_N_I<4> CS04<0> CS00<2> VDD VSS / ++ RM_IHPSG13_1024x16_c2_2P_DEC02 +XDEC00<2> ADDR_N_I<7> ADDR_N_I<6> CS_I CS04<0> VDD VSS / ++ RM_IHPSG13_1024x16_c2_2P_DEC00 +XDEC00<1> ADDR_N_I<5> ADDR_N_I<4> CS04<1> CS00<4> VDD VSS / ++ RM_IHPSG13_1024x16_c2_2P_DEC00 +XDEC00<0> ADDR_N_I<5> ADDR_N_I<4> CS04<0> CS00<0> VDD VSS / ++ RM_IHPSG13_1024x16_c2_2P_DEC00 +XI0 ADDR_N_I<7> VDD VSS / RSC_IHPSG13_TIEL +.ENDS +.SUBCKT RM_IHPSG13_1024x16_c2_2P_ROWREG7 ACLK_N_I ADDR_I<6> ADDR_I<5> ADDR_I<4> ADDR_I<3> ++ ADDR_I<2> ADDR_I<1> ADDR_I<0> ADDR_N_O<6> ADDR_N_O<5> ADDR_N_O<4> ++ ADDR_N_O<3> ADDR_N_O<2> ADDR_N_O<1> ADDR_N_O<0> BIST_ADDR_I<6> ++ BIST_ADDR_I<5> BIST_ADDR_I<4> BIST_ADDR_I<3> BIST_ADDR_I<2> BIST_ADDR_I<1> ++ BIST_ADDR_I<0> BIST_EN_I VDD VSS +XINV<6> q_int<6> qn_int<6> VDD VSS / RSC_IHPSG13_CINVX2 +XINV<5> q_int<5> qn_int<5> VDD VSS / RSC_IHPSG13_CINVX2 +XINV<4> q_int<4> qn_int<4> VDD VSS / RSC_IHPSG13_CINVX2 +XINV<3> q_int<3> qn_int<3> VDD VSS / RSC_IHPSG13_CINVX2 +XINV<2> q_int<2> qn_int<2> VDD VSS / RSC_IHPSG13_CINVX2 +XINV<1> q_int<1> qn_int<1> VDD VSS / RSC_IHPSG13_CINVX2 +XINV<0> q_int<0> qn_int<0> VDD VSS / RSC_IHPSG13_CINVX2 +XDRV<6> qn_int<6> ADDR_N_O<6> VDD VSS / RSC_IHPSG13_CINVX8 +XDRV<5> qn_int<5> ADDR_N_O<5> VDD VSS / RSC_IHPSG13_CINVX8 +XDRV<4> qn_int<4> ADDR_N_O<4> VDD VSS / RSC_IHPSG13_CINVX8 +XDRV<3> qn_int<3> ADDR_N_O<3> VDD VSS / RSC_IHPSG13_CINVX8 +XDRV<2> qn_int<2> ADDR_N_O<2> VDD VSS / RSC_IHPSG13_CINVX8 +XDRV<1> qn_int<1> ADDR_N_O<1> VDD VSS / RSC_IHPSG13_CINVX8 +XDRV<0> qn_int<0> ADDR_N_O<0> VDD VSS / RSC_IHPSG13_CINVX8 +XDFF<6> BIST_EN_I BIST_ADDR_I<6> ACLK_N_I ADDR_I<6> q_int<6> net2<0> VDD ++ VSS / RSC_IHPSG13_DFNQMX2IX1 +XDFF<5> BIST_EN_I BIST_ADDR_I<5> ACLK_N_I ADDR_I<5> q_int<5> net2<1> VDD ++ VSS / RSC_IHPSG13_DFNQMX2IX1 +XDFF<4> BIST_EN_I BIST_ADDR_I<4> ACLK_N_I ADDR_I<4> q_int<4> net2<2> VDD ++ VSS / RSC_IHPSG13_DFNQMX2IX1 +XDFF<3> BIST_EN_I BIST_ADDR_I<3> ACLK_N_I ADDR_I<3> q_int<3> net2<3> VDD ++ VSS / RSC_IHPSG13_DFNQMX2IX1 +XDFF<2> BIST_EN_I BIST_ADDR_I<2> ACLK_N_I ADDR_I<2> q_int<2> net2<4> VDD ++ VSS / RSC_IHPSG13_DFNQMX2IX1 +XDFF<1> BIST_EN_I BIST_ADDR_I<1> ACLK_N_I ADDR_I<1> q_int<1> net2<5> VDD ++ VSS / RSC_IHPSG13_DFNQMX2IX1 +XDFF<0> BIST_EN_I BIST_ADDR_I<0> ACLK_N_I ADDR_I<0> q_int<0> net2<6> VDD ++ VSS / RSC_IHPSG13_DFNQMX2IX1 +XI11<7> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI11<6> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI11<5> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI11<4> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI11<3> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI11<2> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI11<1> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI11<0> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI12<1> VDD VSS / RSC_IHPSG13_FILLCAP4 +XI12<0> VDD VSS / RSC_IHPSG13_FILLCAP4 +.ENDS + +.SUBCKT RM_IHPSG13_1024x16_c2_2P_ROWDEC4 ADDR_N_I<3> ADDR_N_I<2> ADDR_N_I<1> ADDR_N_I<0> ++ CS_I ECLK_I WL_O<15> WL_O<14> WL_O<13> WL_O<12> WL_O<11> WL_O<10> WL_O<9> ++ WL_O<8> WL_O<7> WL_O<6> WL_O<5> WL_O<4> WL_O<3> WL_O<2> WL_O<1> WL_O<0> ++ VDD VSS +XL2<12> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<11> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<10> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<9> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<8> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<7> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<6> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<5> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<4> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<3> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<2> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<1> VDD VSS / RSC_IHPSG13_FILLCAP8 +XSEL ADDR_N_I<3> ADDR_N_I<2> ADDR_N_I<1> ADDR_N_I<0> CS_I ECLK_I ECLK_H<1> ++ ECLK_B<0> ECLK_B<1> WL_O<15> WL_O<14> WL_O<13> WL_O<12> WL_O<11> WL_O<10> ++ WL_O<9> WL_O<8> WL_O<7> WL_O<6> WL_O<5> WL_O<4> WL_O<3> WL_O<2> WL_O<1> ++ WL_O<0> VDD VSS / RM_IHPSG13_1024x16_c2_2P_DEC04 +.ENDS +.SUBCKT RM_IHPSG13_1024x16_c2_2P_ROWREG4 ACLK_N_I ADDR_I<3> ADDR_I<2> ADDR_I<1> ADDR_I<0> ++ ADDR_N_O<3> ADDR_N_O<2> ADDR_N_O<1> ADDR_N_O<0> BIST_ADDR_I<3> ++ BIST_ADDR_I<2> BIST_ADDR_I<1> BIST_ADDR_I<0> BIST_EN_I VDD VSS +XINV<3> q_int<3> qn_int<3> VDD VSS / RSC_IHPSG13_CINVX2 +XINV<2> q_int<2> qn_int<2> VDD VSS / RSC_IHPSG13_CINVX2 +XINV<1> q_int<1> qn_int<1> VDD VSS / RSC_IHPSG13_CINVX2 +XINV<0> q_int<0> qn_int<0> VDD VSS / RSC_IHPSG13_CINVX2 +XDRV<3> qn_int<3> ADDR_N_O<3> VDD VSS / RSC_IHPSG13_CINVX8 +XDRV<2> qn_int<2> ADDR_N_O<2> VDD VSS / RSC_IHPSG13_CINVX8 +XDRV<1> qn_int<1> ADDR_N_O<1> VDD VSS / RSC_IHPSG13_CINVX8 +XDRV<0> qn_int<0> ADDR_N_O<0> VDD VSS / RSC_IHPSG13_CINVX8 +XDFF<3> BIST_EN_I BIST_ADDR_I<3> ACLK_N_I ADDR_I<3> q_int<3> net7<0> VDD ++ VSS / RSC_IHPSG13_DFNQMX2IX1 +XDFF<2> BIST_EN_I BIST_ADDR_I<2> ACLK_N_I ADDR_I<2> q_int<2> net7<1> VDD ++ VSS / RSC_IHPSG13_DFNQMX2IX1 +XDFF<1> BIST_EN_I BIST_ADDR_I<1> ACLK_N_I ADDR_I<1> q_int<1> net7<2> VDD ++ VSS / RSC_IHPSG13_DFNQMX2IX1 +XDFF<0> BIST_EN_I BIST_ADDR_I<0> ACLK_N_I ADDR_I<0> q_int<0> net7<3> VDD ++ VSS / RSC_IHPSG13_DFNQMX2IX1 +XI11<20> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI11<19> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI11<18> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI11<17> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI11<16> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI11<15> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI11<14> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI11<13> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI11<12> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI11<11> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI11<10> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI11<9> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI11<8> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI11<7> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI11<6> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI11<5> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI11<4> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI11<3> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI11<2> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI11<1> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI12<4> VDD VSS / RSC_IHPSG13_FILLCAP4 +XI12<3> VDD VSS / RSC_IHPSG13_FILLCAP4 +XI12<2> VDD VSS / RSC_IHPSG13_FILLCAP4 +XI12<1> VDD VSS / RSC_IHPSG13_FILLCAP4 +XI12<0> VDD VSS / RSC_IHPSG13_FILLCAP4 +.ENDS + + +.SUBCKT RM_IHPSG13_1024x16_c2_1P_BITKIT_TAP BLC BLT NW PW VDD VSS +.ENDS +.SUBCKT RM_IHPSG13_1024x16_c2_1P_BITKIT_16x2_TAP A_BLC<1> A_BLC<0> A_BLT<1> A_BLT<0> ++ VDD_CORE VSS +XITAP<1> A_BLC<1> A_BLT<1> VDD_CORE VSS VDD_CORE VSS ++ / RM_IHPSG13_1024x16_c2_1P_BITKIT_TAP +XITAP<0> A_BLC<0> A_BLT<0> VDD_CORE VSS VDD_CORE VSS ++ / RM_IHPSG13_1024x16_c2_1P_BITKIT_TAP +XIEDGEBP_COL1<1> BLC<1> BLT<1> VDD_CORE VSS VDD_CORE ++ VSS / RM_IHPSG13_1024x16_c2_1P_BITKIT_EDGE_TB +XIEDGEBP_COL1<0> BLC<1> BLT<1> VDD_CORE VSS VDD_CORE ++ VSS / RM_IHPSG13_1024x16_c2_1P_BITKIT_EDGE_TB +XIEDGEBP_COL2<1> BLC<0> BLT<0> VDD_CORE VSS VDD_CORE ++ VSS / RM_IHPSG13_1024x16_c2_1P_BITKIT_EDGE_TB +XIEDGEBP_COL2<0> BLC<0> BLT<0> VDD_CORE VSS VDD_CORE ++ VSS / RM_IHPSG13_1024x16_c2_1P_BITKIT_EDGE_TB +.ENDS +.SUBCKT RM_IHPSG13_1024x16_c2_1P_BITKIT_16x2_TAP_LR VDD_CORE VSS +XCORNER<1> VDD_CORE VSS VDD_CORE VSS / ++ RM_IHPSG13_1024x16_c2_1P_BITKIT_CORNER +XCORNER<0> VDD_CORE VSS VDD_CORE VSS / ++ RM_IHPSG13_1024x16_c2_1P_BITKIT_CORNER +XTAP_BORDER VDD_CORE VSS VDD_CORE VSS / ++ RM_IHPSG13_1024x16_c2_1P_BITKIT_TAP_LR +.ENDS +.SUBCKT RM_IHPSG13_1024x16_c2_1P_DEC03 ADDR<1> ADDR<0> CS CS_OUT VDD VSS +XDECINV net1 CS_OUT VDD VSS / RSC_IHPSG13_INVX4 +XI0 VDD VSS / RSC_IHPSG13_FILLCAP4 +XDEC ADDR<1> ADDR<0> CS net1 VDD VSS / RSC_IHPSG13_NAND3X2 +.ENDS +.SUBCKT RM_IHPSG13_1024x16_c2_1P_DEC02 ADDR<1> ADDR<0> CS CS_OUT VDD VSS +XDECINV net1 CS_OUT VDD VSS / RSC_IHPSG13_INVX4 +XDEC ADDR<1> NADDR<0> CS net1 VDD VSS / RSC_IHPSG13_NAND3X2 +XI2 VDD VSS / RSC_IHPSG13_FILLCAP4 +XADDRINV ADDR<0> NADDR<0> VDD VSS / RSC_IHPSG13_INVX2 +.ENDS +.SUBCKT RM_IHPSG13_1024x16_c2_1P_ROWDEC8 ADDR_N_I<7> ADDR_N_I<6> ADDR_N_I<5> ADDR_N_I<4> ++ ADDR_N_I<3> ADDR_N_I<2> ADDR_N_I<1> ADDR_N_I<0> CS_I ECLK_I WL_O<255> ++ WL_O<254> WL_O<253> WL_O<252> WL_O<251> WL_O<250> WL_O<249> WL_O<248> ++ WL_O<247> WL_O<246> WL_O<245> WL_O<244> WL_O<243> WL_O<242> WL_O<241> ++ WL_O<240> WL_O<239> WL_O<238> WL_O<237> WL_O<236> WL_O<235> WL_O<234> ++ WL_O<233> WL_O<232> WL_O<231> WL_O<230> WL_O<229> WL_O<228> WL_O<227> ++ WL_O<226> WL_O<225> WL_O<224> WL_O<223> WL_O<222> WL_O<221> WL_O<220> ++ WL_O<219> WL_O<218> WL_O<217> WL_O<216> WL_O<215> WL_O<214> WL_O<213> ++ WL_O<212> WL_O<211> WL_O<210> WL_O<209> WL_O<208> WL_O<207> WL_O<206> ++ WL_O<205> WL_O<204> WL_O<203> WL_O<202> WL_O<201> WL_O<200> WL_O<199> ++ WL_O<198> WL_O<197> WL_O<196> WL_O<195> WL_O<194> WL_O<193> WL_O<192> ++ WL_O<191> WL_O<190> WL_O<189> WL_O<188> WL_O<187> WL_O<186> WL_O<185> ++ WL_O<184> WL_O<183> WL_O<182> WL_O<181> WL_O<180> WL_O<179> WL_O<178> ++ WL_O<177> WL_O<176> WL_O<175> WL_O<174> WL_O<173> WL_O<172> WL_O<171> ++ WL_O<170> WL_O<169> WL_O<168> WL_O<167> WL_O<166> WL_O<165> WL_O<164> ++ WL_O<163> WL_O<162> WL_O<161> WL_O<160> WL_O<159> WL_O<158> WL_O<157> ++ WL_O<156> WL_O<155> WL_O<154> WL_O<153> WL_O<152> WL_O<151> WL_O<150> ++ WL_O<149> WL_O<148> WL_O<147> WL_O<146> WL_O<145> WL_O<144> WL_O<143> ++ WL_O<142> WL_O<141> WL_O<140> WL_O<139> WL_O<138> WL_O<137> WL_O<136> ++ WL_O<135> WL_O<134> WL_O<133> WL_O<132> WL_O<131> WL_O<130> WL_O<129> ++ WL_O<128> WL_O<127> WL_O<126> WL_O<125> WL_O<124> WL_O<123> WL_O<122> ++ WL_O<121> WL_O<120> WL_O<119> WL_O<118> WL_O<117> WL_O<116> WL_O<115> ++ WL_O<114> WL_O<113> WL_O<112> WL_O<111> WL_O<110> WL_O<109> WL_O<108> ++ WL_O<107> WL_O<106> WL_O<105> WL_O<104> WL_O<103> WL_O<102> WL_O<101> ++ WL_O<100> WL_O<99> WL_O<98> WL_O<97> WL_O<96> WL_O<95> WL_O<94> WL_O<93> ++ WL_O<92> WL_O<91> WL_O<90> WL_O<89> WL_O<88> WL_O<87> WL_O<86> WL_O<85> ++ WL_O<84> WL_O<83> WL_O<82> WL_O<81> WL_O<80> WL_O<79> WL_O<78> WL_O<77> ++ WL_O<76> WL_O<75> WL_O<74> WL_O<73> WL_O<72> WL_O<71> WL_O<70> WL_O<69> ++ WL_O<68> WL_O<67> WL_O<66> WL_O<65> WL_O<64> WL_O<63> WL_O<62> WL_O<61> ++ WL_O<60> WL_O<59> WL_O<58> WL_O<57> WL_O<56> WL_O<55> WL_O<54> WL_O<53> ++ WL_O<52> WL_O<51> WL_O<50> WL_O<49> WL_O<48> WL_O<47> WL_O<46> WL_O<45> ++ WL_O<44> WL_O<43> WL_O<42> WL_O<41> WL_O<40> WL_O<39> WL_O<38> WL_O<37> ++ WL_O<36> WL_O<35> WL_O<34> WL_O<33> WL_O<32> WL_O<31> WL_O<30> WL_O<29> ++ WL_O<28> WL_O<27> WL_O<26> WL_O<25> WL_O<24> WL_O<23> WL_O<22> WL_O<21> ++ WL_O<20> WL_O<19> WL_O<18> WL_O<17> WL_O<16> WL_O<15> WL_O<14> WL_O<13> ++ WL_O<12> WL_O<11> WL_O<10> WL_O<9> WL_O<8> WL_O<7> WL_O<6> WL_O<5> WL_O<4> ++ WL_O<3> WL_O<2> WL_O<1> WL_O<0> VDD VSS +XDEC11<4> ADDR_N_I<7> ADDR_N_I<6> CS_I CS04<3> VDD VSS / ++ RM_IHPSG13_1024x16_c2_1P_DEC03 +XDEC11<3> ADDR_N_I<5> ADDR_N_I<4> CS04<3> CS00<15> VDD VSS / ++ RM_IHPSG13_1024x16_c2_1P_DEC03 +XDEC11<2> ADDR_N_I<5> ADDR_N_I<4> CS04<2> CS00<11> VDD VSS / ++ RM_IHPSG13_1024x16_c2_1P_DEC03 +XDEC11<1> ADDR_N_I<5> ADDR_N_I<4> CS04<1> CS00<7> VDD VSS / ++ RM_IHPSG13_1024x16_c2_1P_DEC03 +XDEC11<0> ADDR_N_I<5> ADDR_N_I<4> CS04<0> CS00<3> VDD VSS / ++ RM_IHPSG13_1024x16_c2_1P_DEC03 +XL2<88> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<87> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<86> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<85> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<84> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<83> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<82> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<81> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<80> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<79> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<78> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<77> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<76> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<75> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<74> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<73> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<72> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<71> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<70> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<69> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<68> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<67> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<66> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<65> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<64> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<63> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<62> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<61> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<60> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<59> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<58> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<57> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<56> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<55> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<54> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<53> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<52> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<51> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<50> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<49> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<48> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<47> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<46> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<45> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<44> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<43> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<42> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<41> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<40> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<39> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<38> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<37> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<36> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<35> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<34> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<33> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<32> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<31> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<30> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<29> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<28> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<27> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<26> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<25> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<24> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<23> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<22> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<21> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<20> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<19> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<18> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<17> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<16> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<15> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<14> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<13> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<12> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<11> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<10> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<9> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<8> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<7> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<6> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<5> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<4> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<3> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<2> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<1> VDD VSS / RSC_IHPSG13_FILLCAP8 +XDEC10<4> ADDR_N_I<7> ADDR_N_I<6> CS_I CS04<2> VDD VSS / ++ RM_IHPSG13_1024x16_c2_1P_DEC02 +XDEC10<3> ADDR_N_I<5> ADDR_N_I<4> CS04<3> CS00<14> VDD VSS / ++ RM_IHPSG13_1024x16_c2_1P_DEC02 +XDEC10<2> ADDR_N_I<5> ADDR_N_I<4> CS04<2> CS00<10> VDD VSS / ++ RM_IHPSG13_1024x16_c2_1P_DEC02 +XDEC10<1> ADDR_N_I<5> ADDR_N_I<4> CS04<1> CS00<6> VDD VSS / ++ RM_IHPSG13_1024x16_c2_1P_DEC02 +XDEC10<0> ADDR_N_I<5> ADDR_N_I<4> CS04<0> CS00<2> VDD VSS / ++ RM_IHPSG13_1024x16_c2_1P_DEC02 +XDEC00<4> ADDR_N_I<7> ADDR_N_I<6> CS_I CS04<0> VDD VSS / ++ RM_IHPSG13_1024x16_c2_1P_DEC00 +XDEC00<3> ADDR_N_I<5> ADDR_N_I<4> CS04<3> CS00<12> VDD VSS / ++ RM_IHPSG13_1024x16_c2_1P_DEC00 +XDEC00<2> ADDR_N_I<5> ADDR_N_I<4> CS04<2> CS00<8> VDD VSS / ++ RM_IHPSG13_1024x16_c2_1P_DEC00 +XDEC00<1> ADDR_N_I<5> ADDR_N_I<4> CS04<1> CS00<4> VDD VSS / ++ RM_IHPSG13_1024x16_c2_1P_DEC00 +XDEC00<0> ADDR_N_I<5> ADDR_N_I<4> CS04<0> CS00<0> VDD VSS / ++ RM_IHPSG13_1024x16_c2_1P_DEC00 +XSEL<15> ADDR_N_I<3> ADDR_N_I<2> ADDR_N_I<1> ADDR_N_I<0> CS00<15> ECLK_H<15> ++ ECLK_H<16> ECLK_B<15> ECLK_B<16> WL_O<255> WL_O<254> WL_O<253> WL_O<252> ++ WL_O<251> WL_O<250> WL_O<249> WL_O<248> WL_O<247> WL_O<246> WL_O<245> ++ WL_O<244> WL_O<243> WL_O<242> WL_O<241> WL_O<240> VDD VSS / ++ RM_IHPSG13_1024x16_c2_1P_DEC04 +XSEL<14> ADDR_N_I<3> ADDR_N_I<2> ADDR_N_I<1> ADDR_N_I<0> CS00<14> ECLK_H<14> ++ ECLK_H<15> ECLK_B<14> ECLK_B<15> WL_O<239> WL_O<238> WL_O<237> WL_O<236> ++ WL_O<235> WL_O<234> WL_O<233> WL_O<232> WL_O<231> WL_O<230> WL_O<229> ++ WL_O<228> WL_O<227> WL_O<226> WL_O<225> WL_O<224> VDD VSS / ++ RM_IHPSG13_1024x16_c2_1P_DEC04 +XSEL<13> ADDR_N_I<3> ADDR_N_I<2> ADDR_N_I<1> ADDR_N_I<0> CS00<13> ECLK_H<13> ++ ECLK_H<14> ECLK_B<13> ECLK_B<14> WL_O<223> WL_O<222> WL_O<221> WL_O<220> ++ WL_O<219> WL_O<218> WL_O<217> WL_O<216> WL_O<215> WL_O<214> WL_O<213> ++ WL_O<212> WL_O<211> WL_O<210> WL_O<209> WL_O<208> VDD VSS / ++ RM_IHPSG13_1024x16_c2_1P_DEC04 +XSEL<12> ADDR_N_I<3> ADDR_N_I<2> ADDR_N_I<1> ADDR_N_I<0> CS00<12> ECLK_H<12> ++ ECLK_H<13> ECLK_B<12> ECLK_B<13> WL_O<207> WL_O<206> WL_O<205> WL_O<204> ++ WL_O<203> WL_O<202> WL_O<201> WL_O<200> WL_O<199> WL_O<198> WL_O<197> ++ WL_O<196> WL_O<195> WL_O<194> WL_O<193> WL_O<192> VDD VSS / ++ RM_IHPSG13_1024x16_c2_1P_DEC04 +XSEL<11> ADDR_N_I<3> ADDR_N_I<2> ADDR_N_I<1> ADDR_N_I<0> CS00<11> ECLK_H<11> ++ ECLK_H<12> ECLK_B<11> ECLK_B<12> WL_O<191> WL_O<190> WL_O<189> WL_O<188> ++ WL_O<187> WL_O<186> WL_O<185> WL_O<184> WL_O<183> WL_O<182> WL_O<181> ++ WL_O<180> WL_O<179> WL_O<178> WL_O<177> WL_O<176> VDD VSS / ++ RM_IHPSG13_1024x16_c2_1P_DEC04 +XSEL<10> ADDR_N_I<3> ADDR_N_I<2> ADDR_N_I<1> ADDR_N_I<0> CS00<10> ECLK_H<10> ++ ECLK_H<11> ECLK_B<10> ECLK_B<11> WL_O<175> WL_O<174> WL_O<173> WL_O<172> ++ WL_O<171> WL_O<170> WL_O<169> WL_O<168> WL_O<167> WL_O<166> WL_O<165> ++ WL_O<164> WL_O<163> WL_O<162> WL_O<161> WL_O<160> VDD VSS / ++ RM_IHPSG13_1024x16_c2_1P_DEC04 +XSEL<9> ADDR_N_I<3> ADDR_N_I<2> ADDR_N_I<1> ADDR_N_I<0> CS00<9> ECLK_H<9> ++ ECLK_H<10> ECLK_B<9> ECLK_B<10> WL_O<159> WL_O<158> WL_O<157> WL_O<156> ++ WL_O<155> WL_O<154> WL_O<153> WL_O<152> WL_O<151> WL_O<150> WL_O<149> ++ WL_O<148> WL_O<147> WL_O<146> WL_O<145> WL_O<144> VDD VSS / ++ RM_IHPSG13_1024x16_c2_1P_DEC04 +XSEL<8> ADDR_N_I<3> ADDR_N_I<2> ADDR_N_I<1> ADDR_N_I<0> CS00<8> ECLK_H<8> ++ ECLK_H<9> ECLK_B<8> ECLK_B<9> WL_O<143> WL_O<142> WL_O<141> WL_O<140> ++ WL_O<139> WL_O<138> WL_O<137> WL_O<136> WL_O<135> WL_O<134> WL_O<133> ++ WL_O<132> WL_O<131> WL_O<130> WL_O<129> WL_O<128> VDD VSS / ++ RM_IHPSG13_1024x16_c2_1P_DEC04 +XSEL<7> ADDR_N_I<3> ADDR_N_I<2> ADDR_N_I<1> ADDR_N_I<0> CS00<7> ECLK_H<7> ++ ECLK_H<8> ECLK_B<7> ECLK_B<8> WL_O<127> WL_O<126> WL_O<125> WL_O<124> ++ WL_O<123> WL_O<122> WL_O<121> WL_O<120> WL_O<119> WL_O<118> WL_O<117> ++ WL_O<116> WL_O<115> WL_O<114> WL_O<113> WL_O<112> VDD VSS / ++ RM_IHPSG13_1024x16_c2_1P_DEC04 +XSEL<6> ADDR_N_I<3> ADDR_N_I<2> ADDR_N_I<1> ADDR_N_I<0> CS00<6> ECLK_H<6> ++ ECLK_H<7> ECLK_B<6> ECLK_B<7> WL_O<111> WL_O<110> WL_O<109> WL_O<108> ++ WL_O<107> WL_O<106> WL_O<105> WL_O<104> WL_O<103> WL_O<102> WL_O<101> ++ WL_O<100> WL_O<99> WL_O<98> WL_O<97> WL_O<96> VDD VSS / ++ RM_IHPSG13_1024x16_c2_1P_DEC04 +XSEL<5> ADDR_N_I<3> ADDR_N_I<2> ADDR_N_I<1> ADDR_N_I<0> CS00<5> ECLK_H<5> ++ ECLK_H<6> ECLK_B<5> ECLK_B<6> WL_O<95> WL_O<94> WL_O<93> WL_O<92> WL_O<91> ++ WL_O<90> WL_O<89> WL_O<88> WL_O<87> WL_O<86> WL_O<85> WL_O<84> WL_O<83> ++ WL_O<82> WL_O<81> WL_O<80> VDD VSS / RM_IHPSG13_1024x16_c2_1P_DEC04 +XSEL<4> ADDR_N_I<3> ADDR_N_I<2> ADDR_N_I<1> ADDR_N_I<0> CS00<4> ECLK_H<4> ++ ECLK_H<5> ECLK_B<4> ECLK_B<5> WL_O<79> WL_O<78> WL_O<77> WL_O<76> WL_O<75> ++ WL_O<74> WL_O<73> WL_O<72> WL_O<71> WL_O<70> WL_O<69> WL_O<68> WL_O<67> ++ WL_O<66> WL_O<65> WL_O<64> VDD VSS / RM_IHPSG13_1024x16_c2_1P_DEC04 +XSEL<3> ADDR_N_I<3> ADDR_N_I<2> ADDR_N_I<1> ADDR_N_I<0> CS00<3> ECLK_H<3> ++ ECLK_H<4> ECLK_B<3> ECLK_B<4> WL_O<63> WL_O<62> WL_O<61> WL_O<60> WL_O<59> ++ WL_O<58> WL_O<57> WL_O<56> WL_O<55> WL_O<54> WL_O<53> WL_O<52> WL_O<51> ++ WL_O<50> WL_O<49> WL_O<48> VDD VSS / RM_IHPSG13_1024x16_c2_1P_DEC04 +XSEL<2> ADDR_N_I<3> ADDR_N_I<2> ADDR_N_I<1> ADDR_N_I<0> CS00<2> ECLK_H<2> ++ ECLK_H<3> ECLK_B<2> ECLK_B<3> WL_O<47> WL_O<46> WL_O<45> WL_O<44> WL_O<43> ++ WL_O<42> WL_O<41> WL_O<40> WL_O<39> WL_O<38> WL_O<37> WL_O<36> WL_O<35> ++ WL_O<34> WL_O<33> WL_O<32> VDD VSS / RM_IHPSG13_1024x16_c2_1P_DEC04 +XSEL<1> ADDR_N_I<3> ADDR_N_I<2> ADDR_N_I<1> ADDR_N_I<0> CS00<1> ECLK_H<1> ++ ECLK_H<2> ECLK_B<1> ECLK_B<2> WL_O<31> WL_O<30> WL_O<29> WL_O<28> WL_O<27> ++ WL_O<26> WL_O<25> WL_O<24> WL_O<23> WL_O<22> WL_O<21> WL_O<20> WL_O<19> ++ WL_O<18> WL_O<17> WL_O<16> VDD VSS / RM_IHPSG13_1024x16_c2_1P_DEC04 +XSEL<0> ADDR_N_I<3> ADDR_N_I<2> ADDR_N_I<1> ADDR_N_I<0> CS00<0> ECLK_I ++ ECLK_H<1> ECLK_B<0> ECLK_B<1> WL_O<15> WL_O<14> WL_O<13> WL_O<12> WL_O<11> ++ WL_O<10> WL_O<9> WL_O<8> WL_O<7> WL_O<6> WL_O<5> WL_O<4> WL_O<3> WL_O<2> ++ WL_O<1> WL_O<0> VDD VSS / RM_IHPSG13_1024x16_c2_1P_DEC04 +XDEC01<4> ADDR_N_I<7> ADDR_N_I<6> CS_I CS04<1> VDD VSS / ++ RM_IHPSG13_1024x16_c2_1P_DEC01 +XDEC01<3> ADDR_N_I<5> ADDR_N_I<4> CS04<3> CS00<13> VDD VSS / ++ RM_IHPSG13_1024x16_c2_1P_DEC01 +XDEC01<2> ADDR_N_I<5> ADDR_N_I<4> CS04<2> CS00<9> VDD VSS / ++ RM_IHPSG13_1024x16_c2_1P_DEC01 +XDEC01<1> ADDR_N_I<5> ADDR_N_I<4> CS04<1> CS00<5> VDD VSS / ++ RM_IHPSG13_1024x16_c2_1P_DEC01 +XDEC01<0> ADDR_N_I<5> ADDR_N_I<4> CS04<0> CS00<1> VDD VSS / ++ RM_IHPSG13_1024x16_c2_1P_DEC01 +.ENDS +.SUBCKT RM_IHPSG13_1024x16_c2_1P_ROWREG8 ACLK_N_I ADDR_I<7> ADDR_I<6> ADDR_I<5> ADDR_I<4> ++ ADDR_I<3> ADDR_I<2> ADDR_I<1> ADDR_I<0> ADDR_N_O<7> ADDR_N_O<6> ADDR_N_O<5> ++ ADDR_N_O<4> ADDR_N_O<3> ADDR_N_O<2> ADDR_N_O<1> ADDR_N_O<0> BIST_ADDR_I<7> ++ BIST_ADDR_I<6> BIST_ADDR_I<5> BIST_ADDR_I<4> BIST_ADDR_I<3> BIST_ADDR_I<2> ++ BIST_ADDR_I<1> BIST_ADDR_I<0> BIST_EN_I VDD VSS +XINV<7> q_int<7> qn_int<7> VDD VSS / RSC_IHPSG13_CINVX2 +XINV<6> q_int<6> qn_int<6> VDD VSS / RSC_IHPSG13_CINVX2 +XINV<5> q_int<5> qn_int<5> VDD VSS / RSC_IHPSG13_CINVX2 +XINV<4> q_int<4> qn_int<4> VDD VSS / RSC_IHPSG13_CINVX2 +XINV<3> q_int<3> qn_int<3> VDD VSS / RSC_IHPSG13_CINVX2 +XINV<2> q_int<2> qn_int<2> VDD VSS / RSC_IHPSG13_CINVX2 +XINV<1> q_int<1> qn_int<1> VDD VSS / RSC_IHPSG13_CINVX2 +XINV<0> q_int<0> qn_int<0> VDD VSS / RSC_IHPSG13_CINVX2 +XDRV<7> qn_int<7> ADDR_N_O<7> VDD VSS / RSC_IHPSG13_CINVX8 +XDRV<6> qn_int<6> ADDR_N_O<6> VDD VSS / RSC_IHPSG13_CINVX8 +XDRV<5> qn_int<5> ADDR_N_O<5> VDD VSS / RSC_IHPSG13_CINVX8 +XDRV<4> qn_int<4> ADDR_N_O<4> VDD VSS / RSC_IHPSG13_CINVX8 +XDRV<3> qn_int<3> ADDR_N_O<3> VDD VSS / RSC_IHPSG13_CINVX8 +XDRV<2> qn_int<2> ADDR_N_O<2> VDD VSS / RSC_IHPSG13_CINVX8 +XDRV<1> qn_int<1> ADDR_N_O<1> VDD VSS / RSC_IHPSG13_CINVX8 +XDRV<0> qn_int<0> ADDR_N_O<0> VDD VSS / RSC_IHPSG13_CINVX8 +XDFF<7> BIST_EN_I BIST_ADDR_I<7> ACLK_N_I ADDR_I<7> q_int<7> net2<0> VDD ++ VSS / RSC_IHPSG13_DFNQMX2IX1 +XDFF<6> BIST_EN_I BIST_ADDR_I<6> ACLK_N_I ADDR_I<6> q_int<6> net2<1> VDD ++ VSS / RSC_IHPSG13_DFNQMX2IX1 +XDFF<5> BIST_EN_I BIST_ADDR_I<5> ACLK_N_I ADDR_I<5> q_int<5> net2<2> VDD ++ VSS / RSC_IHPSG13_DFNQMX2IX1 +XDFF<4> BIST_EN_I BIST_ADDR_I<4> ACLK_N_I ADDR_I<4> q_int<4> net2<3> VDD ++ VSS / RSC_IHPSG13_DFNQMX2IX1 +XDFF<3> BIST_EN_I BIST_ADDR_I<3> ACLK_N_I ADDR_I<3> q_int<3> net2<4> VDD ++ VSS / RSC_IHPSG13_DFNQMX2IX1 +XDFF<2> BIST_EN_I BIST_ADDR_I<2> ACLK_N_I ADDR_I<2> q_int<2> net2<5> VDD ++ VSS / RSC_IHPSG13_DFNQMX2IX1 +XDFF<1> BIST_EN_I BIST_ADDR_I<1> ACLK_N_I ADDR_I<1> q_int<1> net2<6> VDD ++ VSS / RSC_IHPSG13_DFNQMX2IX1 +XDFF<0> BIST_EN_I BIST_ADDR_I<0> ACLK_N_I ADDR_I<0> q_int<0> net2<7> VDD ++ VSS / RSC_IHPSG13_DFNQMX2IX1 +XI11<4> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI11<3> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI11<2> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI11<1> VDD VSS / RSC_IHPSG13_FILLCAP8 +.ENDS + +.SUBCKT RM_IHPSG13_1024x16_c2_1P_ROWDEC9 ADDR_N_I<8> ADDR_N_I<7> ADDR_N_I<6> ADDR_N_I<5> ++ ADDR_N_I<4> ADDR_N_I<3> ADDR_N_I<2> ADDR_N_I<1> ADDR_N_I<0> CS_I ECLK_I ++ WL_O<511> WL_O<510> WL_O<509> WL_O<508> WL_O<507> WL_O<506> WL_O<505> ++ WL_O<504> WL_O<503> WL_O<502> WL_O<501> WL_O<500> WL_O<499> WL_O<498> ++ WL_O<497> WL_O<496> WL_O<495> WL_O<494> WL_O<493> WL_O<492> WL_O<491> ++ WL_O<490> WL_O<489> WL_O<488> WL_O<487> WL_O<486> WL_O<485> WL_O<484> ++ WL_O<483> WL_O<482> WL_O<481> WL_O<480> WL_O<479> WL_O<478> WL_O<477> ++ WL_O<476> WL_O<475> WL_O<474> WL_O<473> WL_O<472> WL_O<471> WL_O<470> ++ WL_O<469> WL_O<468> WL_O<467> WL_O<466> WL_O<465> WL_O<464> WL_O<463> ++ WL_O<462> WL_O<461> WL_O<460> WL_O<459> WL_O<458> WL_O<457> WL_O<456> ++ WL_O<455> WL_O<454> WL_O<453> WL_O<452> WL_O<451> WL_O<450> WL_O<449> ++ WL_O<448> WL_O<447> WL_O<446> WL_O<445> WL_O<444> WL_O<443> WL_O<442> ++ WL_O<441> WL_O<440> WL_O<439> WL_O<438> WL_O<437> WL_O<436> WL_O<435> ++ WL_O<434> WL_O<433> WL_O<432> WL_O<431> WL_O<430> WL_O<429> WL_O<428> ++ WL_O<427> WL_O<426> WL_O<425> WL_O<424> WL_O<423> WL_O<422> WL_O<421> ++ WL_O<420> WL_O<419> WL_O<418> WL_O<417> WL_O<416> WL_O<415> WL_O<414> ++ WL_O<413> WL_O<412> WL_O<411> WL_O<410> WL_O<409> WL_O<408> WL_O<407> ++ WL_O<406> WL_O<405> WL_O<404> WL_O<403> WL_O<402> WL_O<401> WL_O<400> ++ WL_O<399> WL_O<398> WL_O<397> WL_O<396> WL_O<395> WL_O<394> WL_O<393> ++ WL_O<392> WL_O<391> WL_O<390> WL_O<389> WL_O<388> WL_O<387> WL_O<386> ++ WL_O<385> WL_O<384> WL_O<383> WL_O<382> WL_O<381> WL_O<380> WL_O<379> ++ WL_O<378> WL_O<377> WL_O<376> WL_O<375> WL_O<374> WL_O<373> WL_O<372> ++ WL_O<371> WL_O<370> WL_O<369> WL_O<368> WL_O<367> WL_O<366> WL_O<365> ++ WL_O<364> WL_O<363> WL_O<362> WL_O<361> WL_O<360> WL_O<359> WL_O<358> ++ WL_O<357> WL_O<356> WL_O<355> WL_O<354> WL_O<353> WL_O<352> WL_O<351> ++ WL_O<350> WL_O<349> WL_O<348> WL_O<347> WL_O<346> WL_O<345> WL_O<344> ++ WL_O<343> WL_O<342> WL_O<341> WL_O<340> WL_O<339> WL_O<338> WL_O<337> ++ WL_O<336> WL_O<335> WL_O<334> WL_O<333> WL_O<332> WL_O<331> WL_O<330> ++ WL_O<329> WL_O<328> WL_O<327> WL_O<326> WL_O<325> WL_O<324> WL_O<323> ++ WL_O<322> WL_O<321> WL_O<320> WL_O<319> WL_O<318> WL_O<317> WL_O<316> ++ WL_O<315> WL_O<314> WL_O<313> WL_O<312> WL_O<311> WL_O<310> WL_O<309> ++ WL_O<308> WL_O<307> WL_O<306> WL_O<305> WL_O<304> WL_O<303> WL_O<302> ++ WL_O<301> WL_O<300> WL_O<299> WL_O<298> WL_O<297> WL_O<296> WL_O<295> ++ WL_O<294> WL_O<293> WL_O<292> WL_O<291> WL_O<290> WL_O<289> WL_O<288> ++ WL_O<287> WL_O<286> WL_O<285> WL_O<284> WL_O<283> WL_O<282> WL_O<281> ++ WL_O<280> WL_O<279> WL_O<278> WL_O<277> WL_O<276> WL_O<275> WL_O<274> ++ WL_O<273> WL_O<272> WL_O<271> WL_O<270> WL_O<269> WL_O<268> WL_O<267> ++ WL_O<266> WL_O<265> WL_O<264> WL_O<263> WL_O<262> WL_O<261> WL_O<260> ++ WL_O<259> WL_O<258> WL_O<257> WL_O<256> WL_O<255> WL_O<254> WL_O<253> ++ WL_O<252> WL_O<251> WL_O<250> WL_O<249> WL_O<248> WL_O<247> WL_O<246> ++ WL_O<245> WL_O<244> WL_O<243> WL_O<242> WL_O<241> WL_O<240> WL_O<239> ++ WL_O<238> WL_O<237> WL_O<236> WL_O<235> WL_O<234> WL_O<233> WL_O<232> ++ WL_O<231> WL_O<230> WL_O<229> WL_O<228> WL_O<227> WL_O<226> WL_O<225> ++ WL_O<224> WL_O<223> WL_O<222> WL_O<221> WL_O<220> WL_O<219> WL_O<218> ++ WL_O<217> WL_O<216> WL_O<215> WL_O<214> WL_O<213> WL_O<212> WL_O<211> ++ WL_O<210> WL_O<209> WL_O<208> WL_O<207> WL_O<206> WL_O<205> WL_O<204> ++ WL_O<203> WL_O<202> WL_O<201> WL_O<200> WL_O<199> WL_O<198> WL_O<197> ++ WL_O<196> WL_O<195> WL_O<194> WL_O<193> WL_O<192> WL_O<191> WL_O<190> ++ WL_O<189> WL_O<188> WL_O<187> WL_O<186> WL_O<185> WL_O<184> WL_O<183> ++ WL_O<182> WL_O<181> WL_O<180> WL_O<179> WL_O<178> WL_O<177> WL_O<176> ++ WL_O<175> WL_O<174> WL_O<173> WL_O<172> WL_O<171> WL_O<170> WL_O<169> ++ WL_O<168> WL_O<167> WL_O<166> WL_O<165> WL_O<164> WL_O<163> WL_O<162> ++ WL_O<161> WL_O<160> WL_O<159> WL_O<158> WL_O<157> WL_O<156> WL_O<155> ++ WL_O<154> WL_O<153> WL_O<152> WL_O<151> WL_O<150> WL_O<149> WL_O<148> ++ WL_O<147> WL_O<146> WL_O<145> WL_O<144> WL_O<143> WL_O<142> WL_O<141> ++ WL_O<140> WL_O<139> WL_O<138> WL_O<137> WL_O<136> WL_O<135> WL_O<134> ++ WL_O<133> WL_O<132> WL_O<131> WL_O<130> WL_O<129> WL_O<128> WL_O<127> ++ WL_O<126> WL_O<125> WL_O<124> WL_O<123> WL_O<122> WL_O<121> WL_O<120> ++ WL_O<119> WL_O<118> WL_O<117> WL_O<116> WL_O<115> WL_O<114> WL_O<113> ++ WL_O<112> WL_O<111> WL_O<110> WL_O<109> WL_O<108> WL_O<107> WL_O<106> ++ WL_O<105> WL_O<104> WL_O<103> WL_O<102> WL_O<101> WL_O<100> WL_O<99> ++ WL_O<98> WL_O<97> WL_O<96> WL_O<95> WL_O<94> WL_O<93> WL_O<92> WL_O<91> ++ WL_O<90> WL_O<89> WL_O<88> WL_O<87> WL_O<86> WL_O<85> WL_O<84> WL_O<83> ++ WL_O<82> WL_O<81> WL_O<80> WL_O<79> WL_O<78> WL_O<77> WL_O<76> WL_O<75> ++ WL_O<74> WL_O<73> WL_O<72> WL_O<71> WL_O<70> WL_O<69> WL_O<68> WL_O<67> ++ WL_O<66> WL_O<65> WL_O<64> WL_O<63> WL_O<62> WL_O<61> WL_O<60> WL_O<59> ++ WL_O<58> WL_O<57> WL_O<56> WL_O<55> WL_O<54> WL_O<53> WL_O<52> WL_O<51> ++ WL_O<50> WL_O<49> WL_O<48> WL_O<47> WL_O<46> WL_O<45> WL_O<44> WL_O<43> ++ WL_O<42> WL_O<41> WL_O<40> WL_O<39> WL_O<38> WL_O<37> WL_O<36> WL_O<35> ++ WL_O<34> WL_O<33> WL_O<32> WL_O<31> WL_O<30> WL_O<29> WL_O<28> WL_O<27> ++ WL_O<26> WL_O<25> WL_O<24> WL_O<23> WL_O<22> WL_O<21> WL_O<20> WL_O<19> ++ WL_O<18> WL_O<17> WL_O<16> WL_O<15> WL_O<14> WL_O<13> WL_O<12> WL_O<11> ++ WL_O<10> WL_O<9> WL_O<8> WL_O<7> WL_O<6> WL_O<5> WL_O<4> WL_O<3> WL_O<2> ++ WL_O<1> WL_O<0> VDD VSS +XL2<172> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<171> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<170> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<169> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<168> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<167> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<166> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<165> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<164> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<163> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<162> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<161> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<160> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<159> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<158> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<157> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<156> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<155> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<154> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<153> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<152> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<151> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<150> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<149> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<148> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<147> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<146> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<145> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<144> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<143> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<142> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<141> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<140> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<139> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<138> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<137> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<136> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<135> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<134> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<133> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<132> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<131> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<130> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<129> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<128> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<127> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<126> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<125> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<124> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<123> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<122> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<121> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<120> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<119> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<118> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<117> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<116> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<115> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<114> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<113> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<112> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<111> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<110> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<109> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<108> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<107> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<106> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<105> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<104> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<103> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<102> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<101> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<100> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<99> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<98> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<97> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<96> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<95> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<94> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<93> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<92> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<91> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<90> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<89> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<88> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<87> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<86> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<85> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<84> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<83> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<82> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<81> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<80> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<79> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<78> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<77> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<76> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<75> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<74> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<73> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<72> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<71> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<70> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<69> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<68> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<67> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<66> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<65> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<64> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<63> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<62> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<61> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<60> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<59> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<58> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<57> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<56> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<55> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<54> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<53> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<52> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<51> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<50> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<49> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<48> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<47> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<46> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<45> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<44> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<43> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<42> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<41> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<40> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<39> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<38> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<37> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<36> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<35> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<34> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<33> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<32> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<31> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<30> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<29> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<28> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<27> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<26> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<25> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<24> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<23> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<22> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<21> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<20> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<19> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<18> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<17> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<16> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<15> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<14> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<13> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<12> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<11> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<10> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<9> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<8> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<7> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<6> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<5> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<4> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<3> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<2> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<1> VDD VSS / RSC_IHPSG13_FILLCAP8 +XDEC11<9> ADDR_N_I<7> ADDR_N_I<6> CS04<1> CS02<7> VDD VSS / ++ RM_IHPSG13_1024x16_c2_1P_DEC03 +XDEC11<8> ADDR_N_I<7> ADDR_N_I<6> CS04<0> CS02<3> VDD VSS / ++ RM_IHPSG13_1024x16_c2_1P_DEC03 +XDEC11<7> ADDR_N_I<5> ADDR_N_I<4> CS02<7> CS00<31> VDD VSS / ++ RM_IHPSG13_1024x16_c2_1P_DEC03 +XDEC11<6> ADDR_N_I<5> ADDR_N_I<4> CS02<6> CS00<27> VDD VSS / ++ RM_IHPSG13_1024x16_c2_1P_DEC03 +XDEC11<5> ADDR_N_I<5> ADDR_N_I<4> CS02<5> CS00<23> VDD VSS / ++ RM_IHPSG13_1024x16_c2_1P_DEC03 +XDEC11<4> ADDR_N_I<5> ADDR_N_I<4> CS02<4> CS00<19> VDD VSS / ++ RM_IHPSG13_1024x16_c2_1P_DEC03 +XDEC11<3> ADDR_N_I<5> ADDR_N_I<4> CS02<3> CS00<15> VDD VSS / ++ RM_IHPSG13_1024x16_c2_1P_DEC03 +XDEC11<2> ADDR_N_I<5> ADDR_N_I<4> CS02<2> CS00<11> VDD VSS / ++ RM_IHPSG13_1024x16_c2_1P_DEC03 +XDEC11<1> ADDR_N_I<5> ADDR_N_I<4> CS02<1> CS00<7> VDD VSS / ++ RM_IHPSG13_1024x16_c2_1P_DEC03 +XDEC11<0> ADDR_N_I<5> ADDR_N_I<4> CS02<0> CS00<3> VDD VSS / ++ RM_IHPSG13_1024x16_c2_1P_DEC03 +XDEC00<10> ADDR_N_I<9> ADDR_N_I<8> CS_I CS04<0> VDD VSS / ++ RM_IHPSG13_1024x16_c2_1P_DEC00 +XDEC00<9> ADDR_N_I<7> ADDR_N_I<6> CS04<1> CS02<4> VDD VSS / ++ RM_IHPSG13_1024x16_c2_1P_DEC00 +XDEC00<8> ADDR_N_I<7> ADDR_N_I<6> CS04<0> CS02<0> VDD VSS / ++ RM_IHPSG13_1024x16_c2_1P_DEC00 +XDEC00<7> ADDR_N_I<5> ADDR_N_I<4> CS02<7> CS00<28> VDD VSS / ++ RM_IHPSG13_1024x16_c2_1P_DEC00 +XDEC00<6> ADDR_N_I<5> ADDR_N_I<4> CS02<6> CS00<24> VDD VSS / ++ RM_IHPSG13_1024x16_c2_1P_DEC00 +XDEC00<5> ADDR_N_I<5> ADDR_N_I<4> CS02<5> CS00<20> VDD VSS / ++ RM_IHPSG13_1024x16_c2_1P_DEC00 +XDEC00<4> ADDR_N_I<5> ADDR_N_I<4> CS02<4> CS00<16> VDD VSS / ++ RM_IHPSG13_1024x16_c2_1P_DEC00 +XDEC00<3> ADDR_N_I<5> ADDR_N_I<4> CS02<3> CS00<12> VDD VSS / ++ RM_IHPSG13_1024x16_c2_1P_DEC00 +XDEC00<2> ADDR_N_I<5> ADDR_N_I<4> CS02<2> CS00<8> VDD VSS / ++ RM_IHPSG13_1024x16_c2_1P_DEC00 +XDEC00<1> ADDR_N_I<5> ADDR_N_I<4> CS02<1> CS00<4> VDD VSS / ++ RM_IHPSG13_1024x16_c2_1P_DEC00 +XDEC00<0> ADDR_N_I<5> ADDR_N_I<4> CS02<0> CS00<0> VDD VSS / ++ RM_IHPSG13_1024x16_c2_1P_DEC00 +XSEL<31> ADDR_N_I<3> ADDR_N_I<2> ADDR_N_I<1> ADDR_N_I<0> CS00<31> ECLK_H<31> ++ ECLK_H<32> ECLK_B<31> ECLK_B<32> WL_O<511> WL_O<510> WL_O<509> WL_O<508> ++ WL_O<507> WL_O<506> WL_O<505> WL_O<504> WL_O<503> WL_O<502> WL_O<501> ++ WL_O<500> WL_O<499> WL_O<498> WL_O<497> WL_O<496> VDD VSS / ++ RM_IHPSG13_1024x16_c2_1P_DEC04 +XSEL<30> ADDR_N_I<3> ADDR_N_I<2> ADDR_N_I<1> ADDR_N_I<0> CS00<30> ECLK_H<30> ++ ECLK_H<31> ECLK_B<30> ECLK_B<31> WL_O<495> WL_O<494> WL_O<493> WL_O<492> ++ WL_O<491> WL_O<490> WL_O<489> WL_O<488> WL_O<487> WL_O<486> WL_O<485> ++ WL_O<484> WL_O<483> WL_O<482> WL_O<481> WL_O<480> VDD VSS / ++ RM_IHPSG13_1024x16_c2_1P_DEC04 +XSEL<29> ADDR_N_I<3> ADDR_N_I<2> ADDR_N_I<1> ADDR_N_I<0> CS00<29> ECLK_H<29> ++ ECLK_H<30> ECLK_B<29> ECLK_B<30> WL_O<479> WL_O<478> WL_O<477> WL_O<476> ++ WL_O<475> WL_O<474> WL_O<473> WL_O<472> WL_O<471> WL_O<470> WL_O<469> ++ WL_O<468> WL_O<467> WL_O<466> WL_O<465> WL_O<464> VDD VSS / ++ RM_IHPSG13_1024x16_c2_1P_DEC04 +XSEL<28> ADDR_N_I<3> ADDR_N_I<2> ADDR_N_I<1> ADDR_N_I<0> CS00<28> ECLK_H<28> ++ ECLK_H<29> ECLK_B<28> ECLK_B<29> WL_O<463> WL_O<462> WL_O<461> WL_O<460> ++ WL_O<459> WL_O<458> WL_O<457> WL_O<456> WL_O<455> WL_O<454> WL_O<453> ++ WL_O<452> WL_O<451> WL_O<450> WL_O<449> WL_O<448> VDD VSS / ++ RM_IHPSG13_1024x16_c2_1P_DEC04 +XSEL<27> ADDR_N_I<3> ADDR_N_I<2> ADDR_N_I<1> ADDR_N_I<0> CS00<27> ECLK_H<27> ++ ECLK_H<28> ECLK_B<27> ECLK_B<28> WL_O<447> WL_O<446> WL_O<445> WL_O<444> ++ WL_O<443> WL_O<442> WL_O<441> WL_O<440> WL_O<439> WL_O<438> WL_O<437> ++ WL_O<436> WL_O<435> WL_O<434> WL_O<433> WL_O<432> VDD VSS / ++ RM_IHPSG13_1024x16_c2_1P_DEC04 +XSEL<26> ADDR_N_I<3> ADDR_N_I<2> ADDR_N_I<1> ADDR_N_I<0> CS00<26> ECLK_H<26> ++ ECLK_H<27> ECLK_B<26> ECLK_B<27> WL_O<431> WL_O<430> WL_O<429> WL_O<428> ++ WL_O<427> WL_O<426> WL_O<425> WL_O<424> WL_O<423> WL_O<422> WL_O<421> ++ WL_O<420> WL_O<419> WL_O<418> WL_O<417> WL_O<416> VDD VSS / ++ RM_IHPSG13_1024x16_c2_1P_DEC04 +XSEL<25> ADDR_N_I<3> ADDR_N_I<2> ADDR_N_I<1> ADDR_N_I<0> CS00<25> ECLK_H<25> ++ ECLK_H<26> ECLK_B<25> ECLK_B<26> WL_O<415> WL_O<414> WL_O<413> WL_O<412> ++ WL_O<411> WL_O<410> WL_O<409> WL_O<408> WL_O<407> WL_O<406> WL_O<405> ++ WL_O<404> WL_O<403> WL_O<402> WL_O<401> WL_O<400> VDD VSS / ++ RM_IHPSG13_1024x16_c2_1P_DEC04 +XSEL<24> ADDR_N_I<3> ADDR_N_I<2> ADDR_N_I<1> ADDR_N_I<0> CS00<24> ECLK_H<24> ++ ECLK_H<25> ECLK_B<24> ECLK_B<25> WL_O<399> WL_O<398> WL_O<397> WL_O<396> ++ WL_O<395> WL_O<394> WL_O<393> WL_O<392> WL_O<391> WL_O<390> WL_O<389> ++ WL_O<388> WL_O<387> WL_O<386> WL_O<385> WL_O<384> VDD VSS / ++ RM_IHPSG13_1024x16_c2_1P_DEC04 +XSEL<23> ADDR_N_I<3> ADDR_N_I<2> ADDR_N_I<1> ADDR_N_I<0> CS00<23> ECLK_H<23> ++ ECLK_H<24> ECLK_B<23> ECLK_B<24> WL_O<383> WL_O<382> WL_O<381> WL_O<380> ++ WL_O<379> WL_O<378> WL_O<377> WL_O<376> WL_O<375> WL_O<374> WL_O<373> ++ WL_O<372> WL_O<371> WL_O<370> WL_O<369> WL_O<368> VDD VSS / ++ RM_IHPSG13_1024x16_c2_1P_DEC04 +XSEL<22> ADDR_N_I<3> ADDR_N_I<2> ADDR_N_I<1> ADDR_N_I<0> CS00<22> ECLK_H<22> ++ ECLK_H<23> ECLK_B<22> ECLK_B<23> WL_O<367> WL_O<366> WL_O<365> WL_O<364> ++ WL_O<363> WL_O<362> WL_O<361> WL_O<360> WL_O<359> WL_O<358> WL_O<357> ++ WL_O<356> WL_O<355> WL_O<354> WL_O<353> WL_O<352> VDD VSS / ++ RM_IHPSG13_1024x16_c2_1P_DEC04 +XSEL<21> ADDR_N_I<3> ADDR_N_I<2> ADDR_N_I<1> ADDR_N_I<0> CS00<21> ECLK_H<21> ++ ECLK_H<22> ECLK_B<21> ECLK_B<22> WL_O<351> WL_O<350> WL_O<349> WL_O<348> ++ WL_O<347> WL_O<346> WL_O<345> WL_O<344> WL_O<343> WL_O<342> WL_O<341> ++ WL_O<340> WL_O<339> WL_O<338> WL_O<337> WL_O<336> VDD VSS / ++ RM_IHPSG13_1024x16_c2_1P_DEC04 +XSEL<20> ADDR_N_I<3> ADDR_N_I<2> ADDR_N_I<1> ADDR_N_I<0> CS00<20> ECLK_H<20> ++ ECLK_H<21> ECLK_B<20> ECLK_B<21> WL_O<335> WL_O<334> WL_O<333> WL_O<332> ++ WL_O<331> WL_O<330> WL_O<329> WL_O<328> WL_O<327> WL_O<326> WL_O<325> ++ WL_O<324> WL_O<323> WL_O<322> WL_O<321> WL_O<320> VDD VSS / ++ RM_IHPSG13_1024x16_c2_1P_DEC04 +XSEL<19> ADDR_N_I<3> ADDR_N_I<2> ADDR_N_I<1> ADDR_N_I<0> CS00<19> ECLK_H<19> ++ ECLK_H<20> ECLK_B<19> ECLK_B<20> WL_O<319> WL_O<318> WL_O<317> WL_O<316> ++ WL_O<315> WL_O<314> WL_O<313> WL_O<312> WL_O<311> WL_O<310> WL_O<309> ++ WL_O<308> WL_O<307> WL_O<306> WL_O<305> WL_O<304> VDD VSS / ++ RM_IHPSG13_1024x16_c2_1P_DEC04 +XSEL<18> ADDR_N_I<3> ADDR_N_I<2> ADDR_N_I<1> ADDR_N_I<0> CS00<18> ECLK_H<18> ++ ECLK_H<19> ECLK_B<18> ECLK_B<19> WL_O<303> WL_O<302> WL_O<301> WL_O<300> ++ WL_O<299> WL_O<298> WL_O<297> WL_O<296> WL_O<295> WL_O<294> WL_O<293> ++ WL_O<292> WL_O<291> WL_O<290> WL_O<289> WL_O<288> VDD VSS / ++ RM_IHPSG13_1024x16_c2_1P_DEC04 +XSEL<17> ADDR_N_I<3> ADDR_N_I<2> ADDR_N_I<1> ADDR_N_I<0> CS00<17> ECLK_H<17> ++ ECLK_H<18> ECLK_B<17> ECLK_B<18> WL_O<287> WL_O<286> WL_O<285> WL_O<284> ++ WL_O<283> WL_O<282> WL_O<281> WL_O<280> WL_O<279> WL_O<278> WL_O<277> ++ WL_O<276> WL_O<275> WL_O<274> WL_O<273> WL_O<272> VDD VSS / ++ RM_IHPSG13_1024x16_c2_1P_DEC04 +XSEL<16> ADDR_N_I<3> ADDR_N_I<2> ADDR_N_I<1> ADDR_N_I<0> CS00<16> ECLK_H<16> ++ ECLK_H<17> ECLK_B<16> ECLK_B<17> WL_O<271> WL_O<270> WL_O<269> WL_O<268> ++ WL_O<267> WL_O<266> WL_O<265> WL_O<264> WL_O<263> WL_O<262> WL_O<261> ++ WL_O<260> WL_O<259> WL_O<258> WL_O<257> WL_O<256> VDD VSS / ++ RM_IHPSG13_1024x16_c2_1P_DEC04 +XSEL<15> ADDR_N_I<3> ADDR_N_I<2> ADDR_N_I<1> ADDR_N_I<0> CS00<15> ECLK_H<15> ++ ECLK_H<16> ECLK_B<15> ECLK_B<16> WL_O<255> WL_O<254> WL_O<253> WL_O<252> ++ WL_O<251> WL_O<250> WL_O<249> WL_O<248> WL_O<247> WL_O<246> WL_O<245> ++ WL_O<244> WL_O<243> WL_O<242> WL_O<241> WL_O<240> VDD VSS / ++ RM_IHPSG13_1024x16_c2_1P_DEC04 +XSEL<14> ADDR_N_I<3> ADDR_N_I<2> ADDR_N_I<1> ADDR_N_I<0> CS00<14> ECLK_H<14> ++ ECLK_H<15> ECLK_B<14> ECLK_B<15> WL_O<239> WL_O<238> WL_O<237> WL_O<236> ++ WL_O<235> WL_O<234> WL_O<233> WL_O<232> WL_O<231> WL_O<230> WL_O<229> ++ WL_O<228> WL_O<227> WL_O<226> WL_O<225> WL_O<224> VDD VSS / ++ RM_IHPSG13_1024x16_c2_1P_DEC04 +XSEL<13> ADDR_N_I<3> ADDR_N_I<2> ADDR_N_I<1> ADDR_N_I<0> CS00<13> ECLK_H<13> ++ ECLK_H<14> ECLK_B<13> ECLK_B<14> WL_O<223> WL_O<222> WL_O<221> WL_O<220> ++ WL_O<219> WL_O<218> WL_O<217> WL_O<216> WL_O<215> WL_O<214> WL_O<213> ++ WL_O<212> WL_O<211> WL_O<210> WL_O<209> WL_O<208> VDD VSS / ++ RM_IHPSG13_1024x16_c2_1P_DEC04 +XSEL<12> ADDR_N_I<3> ADDR_N_I<2> ADDR_N_I<1> ADDR_N_I<0> CS00<12> ECLK_H<12> ++ ECLK_H<13> ECLK_B<12> ECLK_B<13> WL_O<207> WL_O<206> WL_O<205> WL_O<204> ++ WL_O<203> WL_O<202> WL_O<201> WL_O<200> WL_O<199> WL_O<198> WL_O<197> ++ WL_O<196> WL_O<195> WL_O<194> WL_O<193> WL_O<192> VDD VSS / ++ RM_IHPSG13_1024x16_c2_1P_DEC04 +XSEL<11> ADDR_N_I<3> ADDR_N_I<2> ADDR_N_I<1> ADDR_N_I<0> CS00<11> ECLK_H<11> ++ ECLK_H<12> ECLK_B<11> ECLK_B<12> WL_O<191> WL_O<190> WL_O<189> WL_O<188> ++ WL_O<187> WL_O<186> WL_O<185> WL_O<184> WL_O<183> WL_O<182> WL_O<181> ++ WL_O<180> WL_O<179> WL_O<178> WL_O<177> WL_O<176> VDD VSS / ++ RM_IHPSG13_1024x16_c2_1P_DEC04 +XSEL<10> ADDR_N_I<3> ADDR_N_I<2> ADDR_N_I<1> ADDR_N_I<0> CS00<10> ECLK_H<10> ++ ECLK_H<11> ECLK_B<10> ECLK_B<11> WL_O<175> WL_O<174> WL_O<173> WL_O<172> ++ WL_O<171> WL_O<170> WL_O<169> WL_O<168> WL_O<167> WL_O<166> WL_O<165> ++ WL_O<164> WL_O<163> WL_O<162> WL_O<161> WL_O<160> VDD VSS / ++ RM_IHPSG13_1024x16_c2_1P_DEC04 +XSEL<9> ADDR_N_I<3> ADDR_N_I<2> ADDR_N_I<1> ADDR_N_I<0> CS00<9> ECLK_H<9> ++ ECLK_H<10> ECLK_B<9> ECLK_B<10> WL_O<159> WL_O<158> WL_O<157> WL_O<156> ++ WL_O<155> WL_O<154> WL_O<153> WL_O<152> WL_O<151> WL_O<150> WL_O<149> ++ WL_O<148> WL_O<147> WL_O<146> WL_O<145> WL_O<144> VDD VSS / ++ RM_IHPSG13_1024x16_c2_1P_DEC04 +XSEL<8> ADDR_N_I<3> ADDR_N_I<2> ADDR_N_I<1> ADDR_N_I<0> CS00<8> ECLK_H<8> ++ ECLK_H<9> ECLK_B<8> ECLK_B<9> WL_O<143> WL_O<142> WL_O<141> WL_O<140> ++ WL_O<139> WL_O<138> WL_O<137> WL_O<136> WL_O<135> WL_O<134> WL_O<133> ++ WL_O<132> WL_O<131> WL_O<130> WL_O<129> WL_O<128> VDD VSS / ++ RM_IHPSG13_1024x16_c2_1P_DEC04 +XSEL<7> ADDR_N_I<3> ADDR_N_I<2> ADDR_N_I<1> ADDR_N_I<0> CS00<7> ECLK_H<7> ++ ECLK_H<8> ECLK_B<7> ECLK_B<8> WL_O<127> WL_O<126> WL_O<125> WL_O<124> ++ WL_O<123> WL_O<122> WL_O<121> WL_O<120> WL_O<119> WL_O<118> WL_O<117> ++ WL_O<116> WL_O<115> WL_O<114> WL_O<113> WL_O<112> VDD VSS / ++ RM_IHPSG13_1024x16_c2_1P_DEC04 +XSEL<6> ADDR_N_I<3> ADDR_N_I<2> ADDR_N_I<1> ADDR_N_I<0> CS00<6> ECLK_H<6> ++ ECLK_H<7> ECLK_B<6> ECLK_B<7> WL_O<111> WL_O<110> WL_O<109> WL_O<108> ++ WL_O<107> WL_O<106> WL_O<105> WL_O<104> WL_O<103> WL_O<102> WL_O<101> ++ WL_O<100> WL_O<99> WL_O<98> WL_O<97> WL_O<96> VDD VSS / ++ RM_IHPSG13_1024x16_c2_1P_DEC04 +XSEL<5> ADDR_N_I<3> ADDR_N_I<2> ADDR_N_I<1> ADDR_N_I<0> CS00<5> ECLK_H<5> ++ ECLK_H<6> ECLK_B<5> ECLK_B<6> WL_O<95> WL_O<94> WL_O<93> WL_O<92> WL_O<91> ++ WL_O<90> WL_O<89> WL_O<88> WL_O<87> WL_O<86> WL_O<85> WL_O<84> WL_O<83> ++ WL_O<82> WL_O<81> WL_O<80> VDD VSS / RM_IHPSG13_1024x16_c2_1P_DEC04 +XSEL<4> ADDR_N_I<3> ADDR_N_I<2> ADDR_N_I<1> ADDR_N_I<0> CS00<4> ECLK_H<4> ++ ECLK_H<5> ECLK_B<4> ECLK_B<5> WL_O<79> WL_O<78> WL_O<77> WL_O<76> WL_O<75> ++ WL_O<74> WL_O<73> WL_O<72> WL_O<71> WL_O<70> WL_O<69> WL_O<68> WL_O<67> ++ WL_O<66> WL_O<65> WL_O<64> VDD VSS / RM_IHPSG13_1024x16_c2_1P_DEC04 +XSEL<3> ADDR_N_I<3> ADDR_N_I<2> ADDR_N_I<1> ADDR_N_I<0> CS00<3> ECLK_H<3> ++ ECLK_H<4> ECLK_B<3> ECLK_B<4> WL_O<63> WL_O<62> WL_O<61> WL_O<60> WL_O<59> ++ WL_O<58> WL_O<57> WL_O<56> WL_O<55> WL_O<54> WL_O<53> WL_O<52> WL_O<51> ++ WL_O<50> WL_O<49> WL_O<48> VDD VSS / RM_IHPSG13_1024x16_c2_1P_DEC04 +XSEL<2> ADDR_N_I<3> ADDR_N_I<2> ADDR_N_I<1> ADDR_N_I<0> CS00<2> ECLK_H<2> ++ ECLK_H<3> ECLK_B<2> ECLK_B<3> WL_O<47> WL_O<46> WL_O<45> WL_O<44> WL_O<43> ++ WL_O<42> WL_O<41> WL_O<40> WL_O<39> WL_O<38> WL_O<37> WL_O<36> WL_O<35> ++ WL_O<34> WL_O<33> WL_O<32> VDD VSS / RM_IHPSG13_1024x16_c2_1P_DEC04 +XSEL<1> ADDR_N_I<3> ADDR_N_I<2> ADDR_N_I<1> ADDR_N_I<0> CS00<1> ECLK_H<1> ++ ECLK_H<2> ECLK_B<1> ECLK_B<2> WL_O<31> WL_O<30> WL_O<29> WL_O<28> WL_O<27> ++ WL_O<26> WL_O<25> WL_O<24> WL_O<23> WL_O<22> WL_O<21> WL_O<20> WL_O<19> ++ WL_O<18> WL_O<17> WL_O<16> VDD VSS / RM_IHPSG13_1024x16_c2_1P_DEC04 +XSEL<0> ADDR_N_I<3> ADDR_N_I<2> ADDR_N_I<1> ADDR_N_I<0> CS00<0> ECLK_I ++ ECLK_H<1> ECLK_B<0> ECLK_B<1> WL_O<15> WL_O<14> WL_O<13> WL_O<12> WL_O<11> ++ WL_O<10> WL_O<9> WL_O<8> WL_O<7> WL_O<6> WL_O<5> WL_O<4> WL_O<3> WL_O<2> ++ WL_O<1> WL_O<0> VDD VSS / RM_IHPSG13_1024x16_c2_1P_DEC04 +XDEC01<10> ADDR_N_I<9> ADDR_N_I<8> CS_I CS04<1> VDD VSS / ++ RM_IHPSG13_1024x16_c2_1P_DEC01 +XDEC01<9> ADDR_N_I<7> ADDR_N_I<6> CS04<1> CS02<5> VDD VSS / ++ RM_IHPSG13_1024x16_c2_1P_DEC01 +XDEC01<8> ADDR_N_I<7> ADDR_N_I<6> CS04<0> CS02<1> VDD VSS / ++ RM_IHPSG13_1024x16_c2_1P_DEC01 +XDEC01<7> ADDR_N_I<5> ADDR_N_I<4> CS02<7> CS00<29> VDD VSS / ++ RM_IHPSG13_1024x16_c2_1P_DEC01 +XDEC01<6> ADDR_N_I<5> ADDR_N_I<4> CS02<6> CS00<25> VDD VSS / ++ RM_IHPSG13_1024x16_c2_1P_DEC01 +XDEC01<5> ADDR_N_I<5> ADDR_N_I<4> CS02<5> CS00<21> VDD VSS / ++ RM_IHPSG13_1024x16_c2_1P_DEC01 +XDEC01<4> ADDR_N_I<5> ADDR_N_I<4> CS02<4> CS00<17> VDD VSS / ++ RM_IHPSG13_1024x16_c2_1P_DEC01 +XDEC01<3> ADDR_N_I<5> ADDR_N_I<4> CS02<3> CS00<13> VDD VSS / ++ RM_IHPSG13_1024x16_c2_1P_DEC01 +XDEC01<2> ADDR_N_I<5> ADDR_N_I<4> CS02<2> CS00<9> VDD VSS / ++ RM_IHPSG13_1024x16_c2_1P_DEC01 +XDEC01<1> ADDR_N_I<5> ADDR_N_I<4> CS02<1> CS00<5> VDD VSS / ++ RM_IHPSG13_1024x16_c2_1P_DEC01 +XDEC01<0> ADDR_N_I<5> ADDR_N_I<4> CS02<0> CS00<1> VDD VSS / ++ RM_IHPSG13_1024x16_c2_1P_DEC01 +XDEC10<9> ADDR_N_I<7> ADDR_N_I<6> CS04<1> CS02<6> VDD VSS / ++ RM_IHPSG13_1024x16_c2_1P_DEC02 +XDEC10<8> ADDR_N_I<7> ADDR_N_I<6> CS04<0> CS02<2> VDD VSS / ++ RM_IHPSG13_1024x16_c2_1P_DEC02 +XDEC10<7> ADDR_N_I<5> ADDR_N_I<4> CS02<7> CS00<30> VDD VSS / ++ RM_IHPSG13_1024x16_c2_1P_DEC02 +XDEC10<6> ADDR_N_I<5> ADDR_N_I<4> CS02<6> CS00<26> VDD VSS / ++ RM_IHPSG13_1024x16_c2_1P_DEC02 +XDEC10<5> ADDR_N_I<5> ADDR_N_I<4> CS02<5> CS00<22> VDD VSS / ++ RM_IHPSG13_1024x16_c2_1P_DEC02 +XDEC10<4> ADDR_N_I<5> ADDR_N_I<4> CS02<4> CS00<18> VDD VSS / ++ RM_IHPSG13_1024x16_c2_1P_DEC02 +XDEC10<3> ADDR_N_I<5> ADDR_N_I<4> CS02<3> CS00<14> VDD VSS / ++ RM_IHPSG13_1024x16_c2_1P_DEC02 +XDEC10<2> ADDR_N_I<5> ADDR_N_I<4> CS02<2> CS00<10> VDD VSS / ++ RM_IHPSG13_1024x16_c2_1P_DEC02 +XDEC10<1> ADDR_N_I<5> ADDR_N_I<4> CS02<1> CS00<6> VDD VSS / ++ RM_IHPSG13_1024x16_c2_1P_DEC02 +XDEC10<0> ADDR_N_I<5> ADDR_N_I<4> CS02<0> CS00<2> VDD VSS / ++ RM_IHPSG13_1024x16_c2_1P_DEC02 +XI0 ADDR_N_I<9> VDD VSS / RSC_IHPSG13_TIEL +.ENDS +.SUBCKT RM_IHPSG13_1024x16_c2_1P_ROWREG9 ACLK_N_I ADDR_I<8> ADDR_I<7> ADDR_I<6> ADDR_I<5> ++ ADDR_I<4> ADDR_I<3> ADDR_I<2> ADDR_I<1> ADDR_I<0> ADDR_N_O<8> ADDR_N_O<7> ++ ADDR_N_O<6> ADDR_N_O<5> ADDR_N_O<4> ADDR_N_O<3> ADDR_N_O<2> ADDR_N_O<1> ++ ADDR_N_O<0> BIST_ADDR_I<8> BIST_ADDR_I<7> BIST_ADDR_I<6> BIST_ADDR_I<5> ++ BIST_ADDR_I<4> BIST_ADDR_I<3> BIST_ADDR_I<2> BIST_ADDR_I<1> BIST_ADDR_I<0> ++ BIST_EN_I VDD VSS +XINV<8> q_int<8> qn_int<8> VDD VSS / RSC_IHPSG13_CINVX2 +XINV<7> q_int<7> qn_int<7> VDD VSS / RSC_IHPSG13_CINVX2 +XINV<6> q_int<6> qn_int<6> VDD VSS / RSC_IHPSG13_CINVX2 +XINV<5> q_int<5> qn_int<5> VDD VSS / RSC_IHPSG13_CINVX2 +XINV<4> q_int<4> qn_int<4> VDD VSS / RSC_IHPSG13_CINVX2 +XINV<3> q_int<3> qn_int<3> VDD VSS / RSC_IHPSG13_CINVX2 +XINV<2> q_int<2> qn_int<2> VDD VSS / RSC_IHPSG13_CINVX2 +XINV<1> q_int<1> qn_int<1> VDD VSS / RSC_IHPSG13_CINVX2 +XINV<0> q_int<0> qn_int<0> VDD VSS / RSC_IHPSG13_CINVX2 +XDRV<8> qn_int<8> ADDR_N_O<8> VDD VSS / RSC_IHPSG13_CINVX8 +XDRV<7> qn_int<7> ADDR_N_O<7> VDD VSS / RSC_IHPSG13_CINVX8 +XDRV<6> qn_int<6> ADDR_N_O<6> VDD VSS / RSC_IHPSG13_CINVX8 +XDRV<5> qn_int<5> ADDR_N_O<5> VDD VSS / RSC_IHPSG13_CINVX8 +XDRV<4> qn_int<4> ADDR_N_O<4> VDD VSS / RSC_IHPSG13_CINVX8 +XDRV<3> qn_int<3> ADDR_N_O<3> VDD VSS / RSC_IHPSG13_CINVX8 +XDRV<2> qn_int<2> ADDR_N_O<2> VDD VSS / RSC_IHPSG13_CINVX8 +XDRV<1> qn_int<1> ADDR_N_O<1> VDD VSS / RSC_IHPSG13_CINVX8 +XDRV<0> qn_int<0> ADDR_N_O<0> VDD VSS / RSC_IHPSG13_CINVX8 +XDFF<8> BIST_EN_I BIST_ADDR_I<8> ACLK_N_I ADDR_I<8> q_int<8> net04<0> VDD ++ VSS / RSC_IHPSG13_DFNQMX2IX1 +XDFF<7> BIST_EN_I BIST_ADDR_I<7> ACLK_N_I ADDR_I<7> q_int<7> net04<1> VDD ++ VSS / RSC_IHPSG13_DFNQMX2IX1 +XDFF<6> BIST_EN_I BIST_ADDR_I<6> ACLK_N_I ADDR_I<6> q_int<6> net04<2> VDD ++ VSS / RSC_IHPSG13_DFNQMX2IX1 +XDFF<5> BIST_EN_I BIST_ADDR_I<5> ACLK_N_I ADDR_I<5> q_int<5> net04<3> VDD ++ VSS / RSC_IHPSG13_DFNQMX2IX1 +XDFF<4> BIST_EN_I BIST_ADDR_I<4> ACLK_N_I ADDR_I<4> q_int<4> net04<4> VDD ++ VSS / RSC_IHPSG13_DFNQMX2IX1 +XDFF<3> BIST_EN_I BIST_ADDR_I<3> ACLK_N_I ADDR_I<3> q_int<3> net04<5> VDD ++ VSS / RSC_IHPSG13_DFNQMX2IX1 +XDFF<2> BIST_EN_I BIST_ADDR_I<2> ACLK_N_I ADDR_I<2> q_int<2> net04<6> VDD ++ VSS / RSC_IHPSG13_DFNQMX2IX1 +XDFF<1> BIST_EN_I BIST_ADDR_I<1> ACLK_N_I ADDR_I<1> q_int<1> net04<7> VDD ++ VSS / RSC_IHPSG13_DFNQMX2IX1 +XDFF<0> BIST_EN_I BIST_ADDR_I<0> ACLK_N_I ADDR_I<0> q_int<0> net04<8> VDD ++ VSS / RSC_IHPSG13_DFNQMX2IX1 +.ENDS + +.SUBCKT RM_IHPSG13_1024x16_c2_1P_ROWDEC7 ADDR_N_I<6> ADDR_N_I<5> ADDR_N_I<4> ADDR_N_I<3> ++ ADDR_N_I<2> ADDR_N_I<1> ADDR_N_I<0> CS_I ECLK_I WL_O<127> WL_O<126> ++ WL_O<125> WL_O<124> WL_O<123> WL_O<122> WL_O<121> WL_O<120> WL_O<119> ++ WL_O<118> WL_O<117> WL_O<116> WL_O<115> WL_O<114> WL_O<113> WL_O<112> ++ WL_O<111> WL_O<110> WL_O<109> WL_O<108> WL_O<107> WL_O<106> WL_O<105> ++ WL_O<104> WL_O<103> WL_O<102> WL_O<101> WL_O<100> WL_O<99> WL_O<98> WL_O<97> ++ WL_O<96> WL_O<95> WL_O<94> WL_O<93> WL_O<92> WL_O<91> WL_O<90> WL_O<89> ++ WL_O<88> WL_O<87> WL_O<86> WL_O<85> WL_O<84> WL_O<83> WL_O<82> WL_O<81> ++ WL_O<80> WL_O<79> WL_O<78> WL_O<77> WL_O<76> WL_O<75> WL_O<74> WL_O<73> ++ WL_O<72> WL_O<71> WL_O<70> WL_O<69> WL_O<68> WL_O<67> WL_O<66> WL_O<65> ++ WL_O<64> WL_O<63> WL_O<62> WL_O<61> WL_O<60> WL_O<59> WL_O<58> WL_O<57> ++ WL_O<56> WL_O<55> WL_O<54> WL_O<53> WL_O<52> WL_O<51> WL_O<50> WL_O<49> ++ WL_O<48> WL_O<47> WL_O<46> WL_O<45> WL_O<44> WL_O<43> WL_O<42> WL_O<41> ++ WL_O<40> WL_O<39> WL_O<38> WL_O<37> WL_O<36> WL_O<35> WL_O<34> WL_O<33> ++ WL_O<32> WL_O<31> WL_O<30> WL_O<29> WL_O<28> WL_O<27> WL_O<26> WL_O<25> ++ WL_O<24> WL_O<23> WL_O<22> WL_O<21> WL_O<20> WL_O<19> WL_O<18> WL_O<17> ++ WL_O<16> WL_O<15> WL_O<14> WL_O<13> WL_O<12> WL_O<11> WL_O<10> WL_O<9> ++ WL_O<8> WL_O<7> WL_O<6> WL_O<5> WL_O<4> WL_O<3> WL_O<2> WL_O<1> WL_O<0> ++ VDD VSS +XDEC11<1> ADDR_N_I<5> ADDR_N_I<4> CS04<1> CS00<7> VDD VSS / ++ RM_IHPSG13_1024x16_c2_1P_DEC03 +XDEC11<0> ADDR_N_I<5> ADDR_N_I<4> CS04<0> CS00<3> VDD VSS / ++ RM_IHPSG13_1024x16_c2_1P_DEC03 +XDEC10<1> ADDR_N_I<5> ADDR_N_I<4> CS04<1> CS00<6> VDD VSS / ++ RM_IHPSG13_1024x16_c2_1P_DEC02 +XDEC10<0> ADDR_N_I<5> ADDR_N_I<4> CS04<0> CS00<2> VDD VSS / ++ RM_IHPSG13_1024x16_c2_1P_DEC02 +XSEL<7> ADDR_N_I<3> ADDR_N_I<2> ADDR_N_I<1> ADDR_N_I<0> CS00<7> ECLK_H<7> ++ ECLK_H<8> ECLK_B<7> ECLK_B<8> WL_O<127> WL_O<126> WL_O<125> WL_O<124> ++ WL_O<123> WL_O<122> WL_O<121> WL_O<120> WL_O<119> WL_O<118> WL_O<117> ++ WL_O<116> WL_O<115> WL_O<114> WL_O<113> WL_O<112> VDD VSS / ++ RM_IHPSG13_1024x16_c2_1P_DEC04 +XSEL<6> ADDR_N_I<3> ADDR_N_I<2> ADDR_N_I<1> ADDR_N_I<0> CS00<6> ECLK_H<6> ++ ECLK_H<7> ECLK_B<6> ECLK_B<7> WL_O<111> WL_O<110> WL_O<109> WL_O<108> ++ WL_O<107> WL_O<106> WL_O<105> WL_O<104> WL_O<103> WL_O<102> WL_O<101> ++ WL_O<100> WL_O<99> WL_O<98> WL_O<97> WL_O<96> VDD VSS / ++ RM_IHPSG13_1024x16_c2_1P_DEC04 +XSEL<5> ADDR_N_I<3> ADDR_N_I<2> ADDR_N_I<1> ADDR_N_I<0> CS00<5> ECLK_H<5> ++ ECLK_H<6> ECLK_B<5> ECLK_B<6> WL_O<95> WL_O<94> WL_O<93> WL_O<92> WL_O<91> ++ WL_O<90> WL_O<89> WL_O<88> WL_O<87> WL_O<86> WL_O<85> WL_O<84> WL_O<83> ++ WL_O<82> WL_O<81> WL_O<80> VDD VSS / RM_IHPSG13_1024x16_c2_1P_DEC04 +XSEL<4> ADDR_N_I<3> ADDR_N_I<2> ADDR_N_I<1> ADDR_N_I<0> CS00<4> ECLK_H<4> ++ ECLK_H<5> ECLK_B<4> ECLK_B<5> WL_O<79> WL_O<78> WL_O<77> WL_O<76> WL_O<75> ++ WL_O<74> WL_O<73> WL_O<72> WL_O<71> WL_O<70> WL_O<69> WL_O<68> WL_O<67> ++ WL_O<66> WL_O<65> WL_O<64> VDD VSS / RM_IHPSG13_1024x16_c2_1P_DEC04 +XSEL<3> ADDR_N_I<3> ADDR_N_I<2> ADDR_N_I<1> ADDR_N_I<0> CS00<3> ECLK_H<3> ++ ECLK_H<4> ECLK_B<3> ECLK_B<4> WL_O<63> WL_O<62> WL_O<61> WL_O<60> WL_O<59> ++ WL_O<58> WL_O<57> WL_O<56> WL_O<55> WL_O<54> WL_O<53> WL_O<52> WL_O<51> ++ WL_O<50> WL_O<49> WL_O<48> VDD VSS / RM_IHPSG13_1024x16_c2_1P_DEC04 +XSEL<2> ADDR_N_I<3> ADDR_N_I<2> ADDR_N_I<1> ADDR_N_I<0> CS00<2> ECLK_H<2> ++ ECLK_H<3> ECLK_B<2> ECLK_B<3> WL_O<47> WL_O<46> WL_O<45> WL_O<44> WL_O<43> ++ WL_O<42> WL_O<41> WL_O<40> WL_O<39> WL_O<38> WL_O<37> WL_O<36> WL_O<35> ++ WL_O<34> WL_O<33> WL_O<32> VDD VSS / RM_IHPSG13_1024x16_c2_1P_DEC04 +XSEL<1> ADDR_N_I<3> ADDR_N_I<2> ADDR_N_I<1> ADDR_N_I<0> CS00<1> ECLK_H<1> ++ ECLK_H<2> ECLK_B<1> ECLK_B<2> WL_O<31> WL_O<30> WL_O<29> WL_O<28> WL_O<27> ++ WL_O<26> WL_O<25> WL_O<24> WL_O<23> WL_O<22> WL_O<21> WL_O<20> WL_O<19> ++ WL_O<18> WL_O<17> WL_O<16> VDD VSS / RM_IHPSG13_1024x16_c2_1P_DEC04 +XSEL<0> ADDR_N_I<3> ADDR_N_I<2> ADDR_N_I<1> ADDR_N_I<0> CS00<0> ECLK_I ++ ECLK_H<1> ECLK_B<0> ECLK_B<1> WL_O<15> WL_O<14> WL_O<13> WL_O<12> WL_O<11> ++ WL_O<10> WL_O<9> WL_O<8> WL_O<7> WL_O<6> WL_O<5> WL_O<4> WL_O<3> WL_O<2> ++ WL_O<1> WL_O<0> VDD VSS / RM_IHPSG13_1024x16_c2_1P_DEC04 +XDEC00<2> ADDR_N_I<7> ADDR_N_I<6> CS_I CS04<0> VDD VSS / ++ RM_IHPSG13_1024x16_c2_1P_DEC00 +XDEC00<1> ADDR_N_I<5> ADDR_N_I<4> CS04<1> CS00<4> VDD VSS / ++ RM_IHPSG13_1024x16_c2_1P_DEC00 +XDEC00<0> ADDR_N_I<5> ADDR_N_I<4> CS04<0> CS00<0> VDD VSS / ++ RM_IHPSG13_1024x16_c2_1P_DEC00 +XDEC01<2> ADDR_N_I<7> ADDR_N_I<6> CS_I CS04<1> VDD VSS / ++ RM_IHPSG13_1024x16_c2_1P_DEC01 +XDEC01<1> ADDR_N_I<5> ADDR_N_I<4> CS04<1> CS00<5> VDD VSS / ++ RM_IHPSG13_1024x16_c2_1P_DEC01 +XDEC01<0> ADDR_N_I<5> ADDR_N_I<4> CS04<0> CS00<1> VDD VSS / ++ RM_IHPSG13_1024x16_c2_1P_DEC01 +XL2<44> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<43> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<42> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<41> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<40> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<39> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<38> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<37> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<36> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<35> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<34> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<33> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<32> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<31> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<30> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<29> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<28> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<27> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<26> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<25> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<24> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<23> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<22> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<21> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<20> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<19> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<18> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<17> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<16> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<15> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<14> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<13> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<12> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<11> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<10> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<9> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<8> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<7> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<6> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<5> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<4> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<3> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<2> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<1> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI0 ADDR_N_I<7> VDD VSS / RSC_IHPSG13_TIEL +.ENDS +.SUBCKT RM_IHPSG13_1024x16_c2_1P_ROWREG7 ACLK_N_I ADDR_I<6> ADDR_I<5> ADDR_I<4> ADDR_I<3> ++ ADDR_I<2> ADDR_I<1> ADDR_I<0> ADDR_N_O<6> ADDR_N_O<5> ADDR_N_O<4> ++ ADDR_N_O<3> ADDR_N_O<2> ADDR_N_O<1> ADDR_N_O<0> BIST_ADDR_I<6> ++ BIST_ADDR_I<5> BIST_ADDR_I<4> BIST_ADDR_I<3> BIST_ADDR_I<2> BIST_ADDR_I<1> ++ BIST_ADDR_I<0> BIST_EN_I VDD VSS +XINV<6> q_int<6> qn_int<6> VDD VSS / RSC_IHPSG13_CINVX2 +XINV<5> q_int<5> qn_int<5> VDD VSS / RSC_IHPSG13_CINVX2 +XINV<4> q_int<4> qn_int<4> VDD VSS / RSC_IHPSG13_CINVX2 +XINV<3> q_int<3> qn_int<3> VDD VSS / RSC_IHPSG13_CINVX2 +XINV<2> q_int<2> qn_int<2> VDD VSS / RSC_IHPSG13_CINVX2 +XINV<1> q_int<1> qn_int<1> VDD VSS / RSC_IHPSG13_CINVX2 +XINV<0> q_int<0> qn_int<0> VDD VSS / RSC_IHPSG13_CINVX2 +XDRV<6> qn_int<6> ADDR_N_O<6> VDD VSS / RSC_IHPSG13_CINVX8 +XDRV<5> qn_int<5> ADDR_N_O<5> VDD VSS / RSC_IHPSG13_CINVX8 +XDRV<4> qn_int<4> ADDR_N_O<4> VDD VSS / RSC_IHPSG13_CINVX8 +XDRV<3> qn_int<3> ADDR_N_O<3> VDD VSS / RSC_IHPSG13_CINVX8 +XDRV<2> qn_int<2> ADDR_N_O<2> VDD VSS / RSC_IHPSG13_CINVX8 +XDRV<1> qn_int<1> ADDR_N_O<1> VDD VSS / RSC_IHPSG13_CINVX8 +XDRV<0> qn_int<0> ADDR_N_O<0> VDD VSS / RSC_IHPSG13_CINVX8 +XDFF<6> BIST_EN_I BIST_ADDR_I<6> ACLK_N_I ADDR_I<6> q_int<6> net2<0> VDD ++ VSS / RSC_IHPSG13_DFNQMX2IX1 +XDFF<5> BIST_EN_I BIST_ADDR_I<5> ACLK_N_I ADDR_I<5> q_int<5> net2<1> VDD ++ VSS / RSC_IHPSG13_DFNQMX2IX1 +XDFF<4> BIST_EN_I BIST_ADDR_I<4> ACLK_N_I ADDR_I<4> q_int<4> net2<2> VDD ++ VSS / RSC_IHPSG13_DFNQMX2IX1 +XDFF<3> BIST_EN_I BIST_ADDR_I<3> ACLK_N_I ADDR_I<3> q_int<3> net2<3> VDD ++ VSS / RSC_IHPSG13_DFNQMX2IX1 +XDFF<2> BIST_EN_I BIST_ADDR_I<2> ACLK_N_I ADDR_I<2> q_int<2> net2<4> VDD ++ VSS / RSC_IHPSG13_DFNQMX2IX1 +XDFF<1> BIST_EN_I BIST_ADDR_I<1> ACLK_N_I ADDR_I<1> q_int<1> net2<5> VDD ++ VSS / RSC_IHPSG13_DFNQMX2IX1 +XDFF<0> BIST_EN_I BIST_ADDR_I<0> ACLK_N_I ADDR_I<0> q_int<0> net2<6> VDD ++ VSS / RSC_IHPSG13_DFNQMX2IX1 +XI11<8> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI11<7> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI11<6> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI11<5> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI11<4> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI11<3> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI11<2> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI11<1> VDD VSS / RSC_IHPSG13_FILLCAP8 +.ENDS + +.SUBCKT RM_IHPSG13_1024x16_c2_1P_COLDRV13X8 ADDR_COL_I<1> ADDR_COL_I<0> ADDR_COL_O<1> ++ ADDR_COL_O<0> ADDR_DEC_I<7> ADDR_DEC_I<6> ADDR_DEC_I<5> ADDR_DEC_I<4> ++ ADDR_DEC_I<3> ADDR_DEC_I<2> ADDR_DEC_I<1> ADDR_DEC_I<0> ADDR_DEC_O<7> ++ ADDR_DEC_O<6> ADDR_DEC_O<5> ADDR_DEC_O<4> ADDR_DEC_O<3> ADDR_DEC_O<2> ++ ADDR_DEC_O<1> ADDR_DEC_O<0> DCLK_I DCLK_O RCLK_I RCLK_O WCLK_I WCLK_O ++ VDD VSS +XI0<1> VDD VSS / RSC_IHPSG13_FILLCAP4 +XI0<0> VDD VSS / RSC_IHPSG13_FILLCAP4 +XADDR_COL_DRV<1> ADDR_COL_I<1> ADDR_COL_O<1> VDD VSS / ++ RSC_IHPSG13_CBUFX8 +XADDR_COL_DRV<0> ADDR_COL_I<0> ADDR_COL_O<0> VDD VSS / ++ RSC_IHPSG13_CBUFX8 +XADDR_DEC_DRV<7> ADDR_DEC_I<7> ADDR_DEC_O<7> VDD VSS / ++ RSC_IHPSG13_CBUFX8 +XADDR_DEC_DRV<6> ADDR_DEC_I<6> ADDR_DEC_O<6> VDD VSS / ++ RSC_IHPSG13_CBUFX8 +XADDR_DEC_DRV<5> ADDR_DEC_I<5> ADDR_DEC_O<5> VDD VSS / ++ RSC_IHPSG13_CBUFX8 +XADDR_DEC_DRV<4> ADDR_DEC_I<4> ADDR_DEC_O<4> VDD VSS / ++ RSC_IHPSG13_CBUFX8 +XADDR_DEC_DRV<3> ADDR_DEC_I<3> ADDR_DEC_O<3> VDD VSS / ++ RSC_IHPSG13_CBUFX8 +XADDR_DEC_DRV<2> ADDR_DEC_I<2> ADDR_DEC_O<2> VDD VSS / ++ RSC_IHPSG13_CBUFX8 +XADDR_DEC_DRV<1> ADDR_DEC_I<1> ADDR_DEC_O<1> VDD VSS / ++ RSC_IHPSG13_CBUFX8 +XADDR_DEC_DRV<0> ADDR_DEC_I<0> ADDR_DEC_O<0> VDD VSS / ++ RSC_IHPSG13_CBUFX8 +XDCLK_DRV DCLK_I DCLK_O VDD VSS / RSC_IHPSG13_CBUFX8 +XRCLK_DRV RCLK_I RCLK_O VDD VSS / RSC_IHPSG13_CBUFX8 +XWCLK_DRV WCLK_I WCLK_O VDD VSS / RSC_IHPSG13_CBUFX8 +.ENDS +.SUBCKT RM_IHPSG13_1024x16_c2_1P_WLDRV16X8 A<15> A<14> A<13> A<12> A<11> A<10> A<9> A<8> ++ A<7> A<6> A<5> A<4> A<3> A<2> A<1> A<0> Z<15> Z<14> Z<13> Z<12> Z<11> Z<10> ++ Z<9> Z<8> Z<7> Z<6> Z<5> Z<4> Z<3> Z<2> Z<1> Z<0> VDD VSS +XBUF<15> A<15> Z<15> VDD VSS / RSC_IHPSG13_WLDRVX8 +XBUF<14> A<14> Z<14> VDD VSS / RSC_IHPSG13_WLDRVX8 +XBUF<13> A<13> Z<13> VDD VSS / RSC_IHPSG13_WLDRVX8 +XBUF<12> A<12> Z<12> VDD VSS / RSC_IHPSG13_WLDRVX8 +XBUF<11> A<11> Z<11> VDD VSS / RSC_IHPSG13_WLDRVX8 +XBUF<10> A<10> Z<10> VDD VSS / RSC_IHPSG13_WLDRVX8 +XBUF<9> A<9> Z<9> VDD VSS / RSC_IHPSG13_WLDRVX8 +XBUF<8> A<8> Z<8> VDD VSS / RSC_IHPSG13_WLDRVX8 +XBUF<7> A<7> Z<7> VDD VSS / RSC_IHPSG13_WLDRVX8 +XBUF<6> A<6> Z<6> VDD VSS / RSC_IHPSG13_WLDRVX8 +XBUF<5> A<5> Z<5> VDD VSS / RSC_IHPSG13_WLDRVX8 +XBUF<4> A<4> Z<4> VDD VSS / RSC_IHPSG13_WLDRVX8 +XBUF<3> A<3> Z<3> VDD VSS / RSC_IHPSG13_WLDRVX8 +XBUF<2> A<2> Z<2> VDD VSS / RSC_IHPSG13_WLDRVX8 +XBUF<1> A<1> Z<1> VDD VSS / RSC_IHPSG13_WLDRVX8 +XBUF<0> A<0> Z<0> VDD VSS / RSC_IHPSG13_WLDRVX8 +.ENDS + + + +.SUBCKT RM_IHPSG13_1024x16_c2_1P_ROWDEC6 ADDR_N_I<5> ADDR_N_I<4> ADDR_N_I<3> ADDR_N_I<2> ++ ADDR_N_I<1> ADDR_N_I<0> CS_I ECLK_I WL_O<63> WL_O<62> WL_O<61> WL_O<60> ++ WL_O<59> WL_O<58> WL_O<57> WL_O<56> WL_O<55> WL_O<54> WL_O<53> WL_O<52> ++ WL_O<51> WL_O<50> WL_O<49> WL_O<48> WL_O<47> WL_O<46> WL_O<45> WL_O<44> ++ WL_O<43> WL_O<42> WL_O<41> WL_O<40> WL_O<39> WL_O<38> WL_O<37> WL_O<36> ++ WL_O<35> WL_O<34> WL_O<33> WL_O<32> WL_O<31> WL_O<30> WL_O<29> WL_O<28> ++ WL_O<27> WL_O<26> WL_O<25> WL_O<24> WL_O<23> WL_O<22> WL_O<21> WL_O<20> ++ WL_O<19> WL_O<18> WL_O<17> WL_O<16> WL_O<15> WL_O<14> WL_O<13> WL_O<12> ++ WL_O<11> WL_O<10> WL_O<9> WL_O<8> WL_O<7> WL_O<6> WL_O<5> WL_O<4> WL_O<3> ++ WL_O<2> WL_O<1> WL_O<0> VDD VSS +XDEC11 ADDR_N_I<5> ADDR_N_I<4> CS_I CS00<3> VDD VSS / ++ RM_IHPSG13_1024x16_c2_1P_DEC03 +XDEC00 ADDR_N_I<5> ADDR_N_I<4> CS_I CS00<0> VDD VSS / ++ RM_IHPSG13_1024x16_c2_1P_DEC00 +XDEC01 ADDR_N_I<5> ADDR_N_I<4> CS_I CS00<1> VDD VSS / ++ RM_IHPSG13_1024x16_c2_1P_DEC01 +XDEC10 ADDR_N_I<5> ADDR_N_I<4> CS_I CS00<2> VDD VSS / ++ RM_IHPSG13_1024x16_c2_1P_DEC02 +XSEL<3> ADDR_N_I<3> ADDR_N_I<2> ADDR_N_I<1> ADDR_N_I<0> CS00<3> ECLK_H<3> ++ ECLK_H<4> ECLK_B<3> ECLK_B<4> WL_O<63> WL_O<62> WL_O<61> WL_O<60> WL_O<59> ++ WL_O<58> WL_O<57> WL_O<56> WL_O<55> WL_O<54> WL_O<53> WL_O<52> WL_O<51> ++ WL_O<50> WL_O<49> WL_O<48> VDD VSS / RM_IHPSG13_1024x16_c2_1P_DEC04 +XSEL<2> ADDR_N_I<3> ADDR_N_I<2> ADDR_N_I<1> ADDR_N_I<0> CS00<2> ECLK_H<2> ++ ECLK_H<3> ECLK_B<2> ECLK_B<3> WL_O<47> WL_O<46> WL_O<45> WL_O<44> WL_O<43> ++ WL_O<42> WL_O<41> WL_O<40> WL_O<39> WL_O<38> WL_O<37> WL_O<36> WL_O<35> ++ WL_O<34> WL_O<33> WL_O<32> VDD VSS / RM_IHPSG13_1024x16_c2_1P_DEC04 +XSEL<1> ADDR_N_I<3> ADDR_N_I<2> ADDR_N_I<1> ADDR_N_I<0> CS00<1> ECLK_H<1> ++ ECLK_H<2> ECLK_B<1> ECLK_B<2> WL_O<31> WL_O<30> WL_O<29> WL_O<28> WL_O<27> ++ WL_O<26> WL_O<25> WL_O<24> WL_O<23> WL_O<22> WL_O<21> WL_O<20> WL_O<19> ++ WL_O<18> WL_O<17> WL_O<16> VDD VSS / RM_IHPSG13_1024x16_c2_1P_DEC04 +XSEL<0> ADDR_N_I<3> ADDR_N_I<2> ADDR_N_I<1> ADDR_N_I<0> CS00<0> ECLK_I ++ ECLK_H<1> ECLK_B<0> ECLK_B<1> WL_O<15> WL_O<14> WL_O<13> WL_O<12> WL_O<11> ++ WL_O<10> WL_O<9> WL_O<8> WL_O<7> WL_O<6> WL_O<5> WL_O<4> WL_O<3> WL_O<2> ++ WL_O<1> WL_O<0> VDD VSS / RM_IHPSG13_1024x16_c2_1P_DEC04 +XL2<24> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<23> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<22> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<21> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<20> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<19> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<18> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<17> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<16> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<15> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<14> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<13> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<12> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<11> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<10> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<9> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<8> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<7> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<6> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<5> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<4> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<3> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<2> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<1> VDD VSS / RSC_IHPSG13_FILLCAP8 +.ENDS +.SUBCKT RM_IHPSG13_1024x16_c2_1P_ROWREG6 ACLK_N_I ADDR_I<5> ADDR_I<4> ADDR_I<3> ADDR_I<2> ++ ADDR_I<1> ADDR_I<0> ADDR_N_O<5> ADDR_N_O<4> ADDR_N_O<3> ADDR_N_O<2> ++ ADDR_N_O<1> ADDR_N_O<0> BIST_ADDR_I<5> BIST_ADDR_I<4> BIST_ADDR_I<3> ++ BIST_ADDR_I<2> BIST_ADDR_I<1> BIST_ADDR_I<0> BIST_EN_I VDD VSS +XINV<5> q_int<5> qn_int<5> VDD VSS / RSC_IHPSG13_CINVX2 +XINV<4> q_int<4> qn_int<4> VDD VSS / RSC_IHPSG13_CINVX2 +XINV<3> q_int<3> qn_int<3> VDD VSS / RSC_IHPSG13_CINVX2 +XINV<2> q_int<2> qn_int<2> VDD VSS / RSC_IHPSG13_CINVX2 +XINV<1> q_int<1> qn_int<1> VDD VSS / RSC_IHPSG13_CINVX2 +XINV<0> q_int<0> qn_int<0> VDD VSS / RSC_IHPSG13_CINVX2 +XDRV<5> qn_int<5> ADDR_N_O<5> VDD VSS / RSC_IHPSG13_CINVX8 +XDRV<4> qn_int<4> ADDR_N_O<4> VDD VSS / RSC_IHPSG13_CINVX8 +XDRV<3> qn_int<3> ADDR_N_O<3> VDD VSS / RSC_IHPSG13_CINVX8 +XDRV<2> qn_int<2> ADDR_N_O<2> VDD VSS / RSC_IHPSG13_CINVX8 +XDRV<1> qn_int<1> ADDR_N_O<1> VDD VSS / RSC_IHPSG13_CINVX8 +XDRV<0> qn_int<0> ADDR_N_O<0> VDD VSS / RSC_IHPSG13_CINVX8 +XDFF<5> BIST_EN_I BIST_ADDR_I<5> ACLK_N_I ADDR_I<5> q_int<5> net2<0> VDD ++ VSS / RSC_IHPSG13_DFNQMX2IX1 +XDFF<4> BIST_EN_I BIST_ADDR_I<4> ACLK_N_I ADDR_I<4> q_int<4> net2<1> VDD ++ VSS / RSC_IHPSG13_DFNQMX2IX1 +XDFF<3> BIST_EN_I BIST_ADDR_I<3> ACLK_N_I ADDR_I<3> q_int<3> net2<2> VDD ++ VSS / RSC_IHPSG13_DFNQMX2IX1 +XDFF<2> BIST_EN_I BIST_ADDR_I<2> ACLK_N_I ADDR_I<2> q_int<2> net2<3> VDD ++ VSS / RSC_IHPSG13_DFNQMX2IX1 +XDFF<1> BIST_EN_I BIST_ADDR_I<1> ACLK_N_I ADDR_I<1> q_int<1> net2<4> VDD ++ VSS / RSC_IHPSG13_DFNQMX2IX1 +XDFF<0> BIST_EN_I BIST_ADDR_I<0> ACLK_N_I ADDR_I<0> q_int<0> net2<5> VDD ++ VSS / RSC_IHPSG13_DFNQMX2IX1 +XI11<12> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI11<11> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI11<10> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI11<9> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI11<8> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI11<7> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI11<6> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI11<5> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI11<4> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI11<3> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI11<2> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI11<1> VDD VSS / RSC_IHPSG13_FILLCAP8 +.ENDS + + +.SUBCKT RM_IHPSG13_1024x16_c2_2P_COLUMN_pcell_0 A_BLC_BOT<1> A_BLC_BOT<0> A_BLC_TOP<1> A_BLC_TOP<0> A_BLT_BOT<1> A_BLT_BOT<0> A_BLT_TOP<1> A_BLT_TOP<0> A_LWL<255> A_LWL<254> A_LWL<253> A_LWL<252> A_LWL<251> A_LWL<250> A_LWL<249> A_LWL<248> A_LWL<247> A_LWL<246> A_LWL<245> A_LWL<244> A_LWL<243> A_LWL<242> A_LWL<241> A_LWL<240> A_LWL<239> A_LWL<238> A_LWL<237> A_LWL<236> A_LWL<235> A_LWL<234> A_LWL<233> A_LWL<232> A_LWL<231> A_LWL<230> A_LWL<229> A_LWL<228> A_LWL<227> A_LWL<226> A_LWL<225> A_LWL<224> A_LWL<223> A_LWL<222> A_LWL<221> A_LWL<220> A_LWL<219> A_LWL<218> A_LWL<217> A_LWL<216> A_LWL<215> A_LWL<214> A_LWL<213> A_LWL<212> A_LWL<211> A_LWL<210> A_LWL<209> A_LWL<208> A_LWL<207> A_LWL<206> A_LWL<205> A_LWL<204> A_LWL<203> A_LWL<202> A_LWL<201> A_LWL<200> A_LWL<199> A_LWL<198> A_LWL<197> A_LWL<196> A_LWL<195> A_LWL<194> A_LWL<193> A_LWL<192> A_LWL<191> A_LWL<190> A_LWL<189> A_LWL<188> A_LWL<187> A_LWL<186> A_LWL<185> A_LWL<184> A_LWL<183> A_LWL<182> A_LWL<181> A_LWL<180> A_LWL<179> A_LWL<178> A_LWL<177> A_LWL<176> A_LWL<175> A_LWL<174> A_LWL<173> A_LWL<172> A_LWL<171> A_LWL<170> A_LWL<169> A_LWL<168> A_LWL<167> A_LWL<166> A_LWL<165> A_LWL<164> A_LWL<163> A_LWL<162> A_LWL<161> A_LWL<160> A_LWL<159> A_LWL<158> A_LWL<157> A_LWL<156> A_LWL<155> A_LWL<154> A_LWL<153> A_LWL<152> A_LWL<151> A_LWL<150> A_LWL<149> A_LWL<148> A_LWL<147> A_LWL<146> A_LWL<145> A_LWL<144> A_LWL<143> A_LWL<142> A_LWL<141> A_LWL<140> A_LWL<139> A_LWL<138> A_LWL<137> A_LWL<136> A_LWL<135> A_LWL<134> A_LWL<133> A_LWL<132> A_LWL<131> A_LWL<130> A_LWL<129> A_LWL<128> A_LWL<127> A_LWL<126> A_LWL<125> A_LWL<124> A_LWL<123> A_LWL<122> A_LWL<121> A_LWL<120> A_LWL<119> A_LWL<118> A_LWL<117> A_LWL<116> A_LWL<115> A_LWL<114> A_LWL<113> A_LWL<112> A_LWL<111> A_LWL<110> A_LWL<109> A_LWL<108> A_LWL<107> A_LWL<106> A_LWL<105> A_LWL<104> A_LWL<103> A_LWL<102> A_LWL<101> A_LWL<100> A_LWL<99> A_LWL<98> A_LWL<97> A_LWL<96> A_LWL<95> A_LWL<94> A_LWL<93> A_LWL<92> A_LWL<91> A_LWL<90> A_LWL<89> A_LWL<88> A_LWL<87> A_LWL<86> A_LWL<85> A_LWL<84> A_LWL<83> A_LWL<82> A_LWL<81> A_LWL<80> A_LWL<79> A_LWL<78> A_LWL<77> A_LWL<76> A_LWL<75> A_LWL<74> A_LWL<73> A_LWL<72> A_LWL<71> A_LWL<70> A_LWL<69> A_LWL<68> A_LWL<67> A_LWL<66> A_LWL<65> A_LWL<64> A_LWL<63> A_LWL<62> A_LWL<61> A_LWL<60> A_LWL<59> A_LWL<58> A_LWL<57> A_LWL<56> A_LWL<55> A_LWL<54> A_LWL<53> A_LWL<52> A_LWL<51> A_LWL<50> A_LWL<49> A_LWL<48> A_LWL<47> A_LWL<46> A_LWL<45> A_LWL<44> A_LWL<43> A_LWL<42> A_LWL<41> A_LWL<40> A_LWL<39> A_LWL<38> A_LWL<37> A_LWL<36> A_LWL<35> A_LWL<34> A_LWL<33> A_LWL<32> A_LWL<31> A_LWL<30> A_LWL<29> A_LWL<28> A_LWL<27> A_LWL<26> A_LWL<25> A_LWL<24> A_LWL<23> A_LWL<22> A_LWL<21> A_LWL<20> A_LWL<19> A_LWL<18> A_LWL<17> A_LWL<16> A_LWL<15> A_LWL<14> A_LWL<13> A_LWL<12> A_LWL<11> A_LWL<10> A_LWL<9> A_LWL<8> A_LWL<7> A_LWL<6> A_LWL<5> A_LWL<4> A_LWL<3> A_LWL<2> A_LWL<1> A_LWL<0> A_RWL<255> A_RWL<254> A_RWL<253> A_RWL<252> A_RWL<251> A_RWL<250> A_RWL<249> A_RWL<248> A_RWL<247> A_RWL<246> A_RWL<245> A_RWL<244> A_RWL<243> A_RWL<242> A_RWL<241> A_RWL<240> A_RWL<239> A_RWL<238> A_RWL<237> A_RWL<236> A_RWL<235> A_RWL<234> A_RWL<233> A_RWL<232> A_RWL<231> A_RWL<230> A_RWL<229> A_RWL<228> A_RWL<227> A_RWL<226> A_RWL<225> A_RWL<224> A_RWL<223> A_RWL<222> A_RWL<221> A_RWL<220> A_RWL<219> A_RWL<218> A_RWL<217> A_RWL<216> A_RWL<215> A_RWL<214> A_RWL<213> A_RWL<212> A_RWL<211> A_RWL<210> A_RWL<209> A_RWL<208> A_RWL<207> A_RWL<206> A_RWL<205> A_RWL<204> A_RWL<203> A_RWL<202> A_RWL<201> A_RWL<200> A_RWL<199> A_RWL<198> A_RWL<197> A_RWL<196> A_RWL<195> A_RWL<194> A_RWL<193> A_RWL<192> A_RWL<191> A_RWL<190> A_RWL<189> A_RWL<188> A_RWL<187> A_RWL<186> A_RWL<185> A_RWL<184> A_RWL<183> A_RWL<182> A_RWL<181> A_RWL<180> A_RWL<179> A_RWL<178> A_RWL<177> A_RWL<176> A_RWL<175> A_RWL<174> A_RWL<173> A_RWL<172> A_RWL<171> A_RWL<170> A_RWL<169> A_RWL<168> A_RWL<167> A_RWL<166> A_RWL<165> A_RWL<164> A_RWL<163> A_RWL<162> A_RWL<161> A_RWL<160> A_RWL<159> A_RWL<158> A_RWL<157> A_RWL<156> A_RWL<155> A_RWL<154> A_RWL<153> A_RWL<152> A_RWL<151> A_RWL<150> A_RWL<149> A_RWL<148> A_RWL<147> A_RWL<146> A_RWL<145> A_RWL<144> A_RWL<143> A_RWL<142> A_RWL<141> A_RWL<140> A_RWL<139> A_RWL<138> A_RWL<137> A_RWL<136> A_RWL<135> A_RWL<134> A_RWL<133> A_RWL<132> A_RWL<131> A_RWL<130> A_RWL<129> A_RWL<128> A_RWL<127> A_RWL<126> A_RWL<125> A_RWL<124> A_RWL<123> A_RWL<122> A_RWL<121> A_RWL<120> A_RWL<119> A_RWL<118> A_RWL<117> A_RWL<116> A_RWL<115> A_RWL<114> A_RWL<113> A_RWL<112> A_RWL<111> A_RWL<110> A_RWL<109> A_RWL<108> A_RWL<107> A_RWL<106> A_RWL<105> A_RWL<104> A_RWL<103> A_RWL<102> A_RWL<101> A_RWL<100> A_RWL<99> A_RWL<98> A_RWL<97> A_RWL<96> A_RWL<95> A_RWL<94> A_RWL<93> A_RWL<92> A_RWL<91> A_RWL<90> A_RWL<89> A_RWL<88> A_RWL<87> A_RWL<86> A_RWL<85> A_RWL<84> A_RWL<83> A_RWL<82> A_RWL<81> A_RWL<80> A_RWL<79> A_RWL<78> A_RWL<77> A_RWL<76> A_RWL<75> A_RWL<74> A_RWL<73> A_RWL<72> A_RWL<71> A_RWL<70> A_RWL<69> A_RWL<68> A_RWL<67> A_RWL<66> A_RWL<65> A_RWL<64> A_RWL<63> A_RWL<62> A_RWL<61> A_RWL<60> A_RWL<59> A_RWL<58> A_RWL<57> A_RWL<56> A_RWL<55> A_RWL<54> A_RWL<53> A_RWL<52> A_RWL<51> A_RWL<50> A_RWL<49> A_RWL<48> A_RWL<47> A_RWL<46> A_RWL<45> A_RWL<44> A_RWL<43> A_RWL<42> A_RWL<41> A_RWL<40> A_RWL<39> A_RWL<38> A_RWL<37> A_RWL<36> A_RWL<35> A_RWL<34> A_RWL<33> A_RWL<32> A_RWL<31> A_RWL<30> A_RWL<29> A_RWL<28> A_RWL<27> A_RWL<26> A_RWL<25> A_RWL<24> A_RWL<23> A_RWL<22> A_RWL<21> A_RWL<20> A_RWL<19> A_RWL<18> A_RWL<17> A_RWL<16> A_RWL<15> A_RWL<14> A_RWL<13> A_RWL<12> A_RWL<11> A_RWL<10> A_RWL<9> A_RWL<8> A_RWL<7> A_RWL<6> A_RWL<5> A_RWL<4> A_RWL<3> A_RWL<2> A_RWL<1> A_RWL<0> B_BLC_BOT<1> B_BLC_BOT<0> B_BLC_TOP<1> B_BLC_TOP<0> B_BLT_BOT<1> B_BLT_BOT<0> B_BLT_TOP<1> B_BLT_TOP<0> B_LWL<255> B_LWL<254> B_LWL<253> B_LWL<252> B_LWL<251> B_LWL<250> B_LWL<249> B_LWL<248> B_LWL<247> B_LWL<246> B_LWL<245> B_LWL<244> B_LWL<243> B_LWL<242> B_LWL<241> B_LWL<240> B_LWL<239> B_LWL<238> B_LWL<237> B_LWL<236> B_LWL<235> B_LWL<234> B_LWL<233> B_LWL<232> B_LWL<231> B_LWL<230> B_LWL<229> B_LWL<228> B_LWL<227> B_LWL<226> B_LWL<225> B_LWL<224> B_LWL<223> B_LWL<222> B_LWL<221> B_LWL<220> B_LWL<219> B_LWL<218> B_LWL<217> B_LWL<216> B_LWL<215> B_LWL<214> B_LWL<213> B_LWL<212> B_LWL<211> B_LWL<210> B_LWL<209> B_LWL<208> B_LWL<207> B_LWL<206> B_LWL<205> B_LWL<204> B_LWL<203> B_LWL<202> B_LWL<201> B_LWL<200> B_LWL<199> B_LWL<198> B_LWL<197> B_LWL<196> B_LWL<195> B_LWL<194> B_LWL<193> B_LWL<192> B_LWL<191> B_LWL<190> B_LWL<189> B_LWL<188> B_LWL<187> B_LWL<186> B_LWL<185> B_LWL<184> B_LWL<183> B_LWL<182> B_LWL<181> B_LWL<180> B_LWL<179> B_LWL<178> B_LWL<177> B_LWL<176> B_LWL<175> B_LWL<174> B_LWL<173> B_LWL<172> B_LWL<171> B_LWL<170> B_LWL<169> B_LWL<168> B_LWL<167> B_LWL<166> B_LWL<165> B_LWL<164> B_LWL<163> B_LWL<162> B_LWL<161> B_LWL<160> B_LWL<159> B_LWL<158> B_LWL<157> B_LWL<156> B_LWL<155> B_LWL<154> B_LWL<153> B_LWL<152> B_LWL<151> B_LWL<150> B_LWL<149> B_LWL<148> B_LWL<147> B_LWL<146> B_LWL<145> B_LWL<144> B_LWL<143> B_LWL<142> B_LWL<141> B_LWL<140> B_LWL<139> B_LWL<138> B_LWL<137> B_LWL<136> B_LWL<135> B_LWL<134> B_LWL<133> B_LWL<132> B_LWL<131> B_LWL<130> B_LWL<129> B_LWL<128> B_LWL<127> B_LWL<126> B_LWL<125> B_LWL<124> B_LWL<123> B_LWL<122> B_LWL<121> B_LWL<120> B_LWL<119> B_LWL<118> B_LWL<117> B_LWL<116> B_LWL<115> B_LWL<114> B_LWL<113> B_LWL<112> B_LWL<111> B_LWL<110> B_LWL<109> B_LWL<108> B_LWL<107> B_LWL<106> B_LWL<105> B_LWL<104> B_LWL<103> B_LWL<102> B_LWL<101> B_LWL<100> B_LWL<99> B_LWL<98> B_LWL<97> B_LWL<96> B_LWL<95> B_LWL<94> B_LWL<93> B_LWL<92> B_LWL<91> B_LWL<90> B_LWL<89> B_LWL<88> B_LWL<87> B_LWL<86> B_LWL<85> B_LWL<84> B_LWL<83> B_LWL<82> B_LWL<81> B_LWL<80> B_LWL<79> B_LWL<78> B_LWL<77> B_LWL<76> B_LWL<75> B_LWL<74> B_LWL<73> B_LWL<72> B_LWL<71> B_LWL<70> B_LWL<69> B_LWL<68> B_LWL<67> B_LWL<66> B_LWL<65> B_LWL<64> B_LWL<63> B_LWL<62> B_LWL<61> B_LWL<60> B_LWL<59> B_LWL<58> B_LWL<57> B_LWL<56> B_LWL<55> B_LWL<54> B_LWL<53> B_LWL<52> B_LWL<51> B_LWL<50> B_LWL<49> B_LWL<48> B_LWL<47> B_LWL<46> B_LWL<45> B_LWL<44> B_LWL<43> B_LWL<42> B_LWL<41> B_LWL<40> B_LWL<39> B_LWL<38> B_LWL<37> B_LWL<36> B_LWL<35> B_LWL<34> B_LWL<33> B_LWL<32> B_LWL<31> B_LWL<30> B_LWL<29> B_LWL<28> B_LWL<27> B_LWL<26> B_LWL<25> B_LWL<24> B_LWL<23> B_LWL<22> B_LWL<21> B_LWL<20> B_LWL<19> B_LWL<18> B_LWL<17> B_LWL<16> B_LWL<15> B_LWL<14> B_LWL<13> B_LWL<12> B_LWL<11> B_LWL<10> B_LWL<9> B_LWL<8> B_LWL<7> B_LWL<6> B_LWL<5> B_LWL<4> B_LWL<3> B_LWL<2> B_LWL<1> B_LWL<0> B_RWL<255> B_RWL<254> B_RWL<253> B_RWL<252> B_RWL<251> B_RWL<250> B_RWL<249> B_RWL<248> B_RWL<247> B_RWL<246> B_RWL<245> B_RWL<244> B_RWL<243> B_RWL<242> B_RWL<241> B_RWL<240> B_RWL<239> B_RWL<238> B_RWL<237> B_RWL<236> B_RWL<235> B_RWL<234> B_RWL<233> B_RWL<232> B_RWL<231> B_RWL<230> B_RWL<229> B_RWL<228> B_RWL<227> B_RWL<226> B_RWL<225> B_RWL<224> B_RWL<223> B_RWL<222> B_RWL<221> B_RWL<220> B_RWL<219> B_RWL<218> B_RWL<217> B_RWL<216> B_RWL<215> B_RWL<214> B_RWL<213> B_RWL<212> B_RWL<211> B_RWL<210> B_RWL<209> B_RWL<208> B_RWL<207> B_RWL<206> B_RWL<205> B_RWL<204> B_RWL<203> B_RWL<202> B_RWL<201> B_RWL<200> B_RWL<199> B_RWL<198> B_RWL<197> B_RWL<196> B_RWL<195> B_RWL<194> B_RWL<193> B_RWL<192> B_RWL<191> B_RWL<190> B_RWL<189> B_RWL<188> B_RWL<187> B_RWL<186> B_RWL<185> B_RWL<184> B_RWL<183> B_RWL<182> B_RWL<181> B_RWL<180> B_RWL<179> B_RWL<178> B_RWL<177> B_RWL<176> B_RWL<175> B_RWL<174> B_RWL<173> B_RWL<172> B_RWL<171> B_RWL<170> B_RWL<169> B_RWL<168> B_RWL<167> B_RWL<166> B_RWL<165> B_RWL<164> B_RWL<163> B_RWL<162> B_RWL<161> B_RWL<160> B_RWL<159> B_RWL<158> B_RWL<157> B_RWL<156> B_RWL<155> B_RWL<154> B_RWL<153> B_RWL<152> B_RWL<151> B_RWL<150> B_RWL<149> B_RWL<148> B_RWL<147> B_RWL<146> B_RWL<145> B_RWL<144> B_RWL<143> B_RWL<142> B_RWL<141> B_RWL<140> B_RWL<139> B_RWL<138> B_RWL<137> B_RWL<136> B_RWL<135> B_RWL<134> B_RWL<133> B_RWL<132> B_RWL<131> B_RWL<130> B_RWL<129> B_RWL<128> B_RWL<127> B_RWL<126> B_RWL<125> B_RWL<124> B_RWL<123> B_RWL<122> B_RWL<121> B_RWL<120> B_RWL<119> B_RWL<118> B_RWL<117> B_RWL<116> B_RWL<115> B_RWL<114> B_RWL<113> B_RWL<112> B_RWL<111> B_RWL<110> B_RWL<109> B_RWL<108> B_RWL<107> B_RWL<106> B_RWL<105> B_RWL<104> B_RWL<103> B_RWL<102> B_RWL<101> B_RWL<100> B_RWL<99> B_RWL<98> B_RWL<97> B_RWL<96> B_RWL<95> B_RWL<94> B_RWL<93> B_RWL<92> B_RWL<91> B_RWL<90> B_RWL<89> B_RWL<88> B_RWL<87> B_RWL<86> B_RWL<85> B_RWL<84> B_RWL<83> B_RWL<82> B_RWL<81> B_RWL<80> B_RWL<79> B_RWL<78> B_RWL<77> B_RWL<76> B_RWL<75> B_RWL<74> B_RWL<73> B_RWL<72> B_RWL<71> B_RWL<70> B_RWL<69> B_RWL<68> B_RWL<67> B_RWL<66> B_RWL<65> B_RWL<64> B_RWL<63> B_RWL<62> B_RWL<61> B_RWL<60> B_RWL<59> B_RWL<58> B_RWL<57> B_RWL<56> B_RWL<55> B_RWL<54> B_RWL<53> B_RWL<52> B_RWL<51> B_RWL<50> B_RWL<49> B_RWL<48> B_RWL<47> B_RWL<46> B_RWL<45> B_RWL<44> B_RWL<43> B_RWL<42> B_RWL<41> B_RWL<40> B_RWL<39> B_RWL<38> B_RWL<37> B_RWL<36> B_RWL<35> B_RWL<34> B_RWL<33> B_RWL<32> B_RWL<31> B_RWL<30> B_RWL<29> B_RWL<28> B_RWL<27> B_RWL<26> B_RWL<25> B_RWL<24> B_RWL<23> B_RWL<22> B_RWL<21> B_RWL<20> B_RWL<19> B_RWL<18> B_RWL<17> B_RWL<16> B_RWL<15> B_RWL<14> B_RWL<13> B_RWL<12> B_RWL<11> B_RWL<10> B_RWL<9> B_RWL<8> B_RWL<7> B_RWL<6> B_RWL<5> B_RWL<4> B_RWL<3> B_RWL<2> B_RWL<1> B_RWL<0> VDD_CORE VSS +XRAM<16> A_BLC<29> A_BLC<28> A_BLC_TOP<1> A_BLC_TOP<0> A_BLT<29> A_BLT<28> A_BLT_TOP<1> A_BLT_TOP<0> A_LWL<255> A_LWL<254> A_LWL<253> A_LWL<252> A_LWL<251> A_LWL<250> A_LWL<249> A_LWL<248> A_LWL<247> A_LWL<246> A_LWL<245> A_LWL<244> A_LWL<243> A_LWL<242> A_LWL<241> A_LWL<240> A_RWL<255> A_RWL<254> A_RWL<253> A_RWL<252> A_RWL<251> A_RWL<250> A_RWL<249> A_RWL<248> A_RWL<247> A_RWL<246> A_RWL<245> A_RWL<244> A_RWL<243> A_RWL<242> A_RWL<241> A_RWL<240> B_BLC<29> B_BLC<28> B_BLC_TOP<1> B_BLC_TOP<0> B_BLT<29> B_BLT<28> B_BLT_TOP<1> B_BLT_TOP<0> B_LWL<255> B_LWL<254> B_LWL<253> B_LWL<252> B_LWL<251> B_LWL<250> B_LWL<249> B_LWL<248> B_LWL<247> B_LWL<246> B_LWL<245> B_LWL<244> B_LWL<243> B_LWL<242> B_LWL<241> B_LWL<240> B_RWL<255> B_RWL<254> B_RWL<253> B_RWL<252> B_RWL<251> B_RWL<250> B_RWL<249> B_RWL<248> B_RWL<247> B_RWL<246> B_RWL<245> B_RWL<244> B_RWL<243> B_RWL<242> B_RWL<241> B_RWL<240> VDD_CORE VSS / RM_IHPSG13_1024x16_c2_2P_BITKIT_16x2_SRAM +XRAM<15> A_BLC<27> A_BLC<26> A_BLC<29> A_BLC<28> A_BLT<27> A_BLT<26> A_BLT<29> A_BLT<28> A_LWL<239> A_LWL<238> A_LWL<237> A_LWL<236> A_LWL<235> A_LWL<234> A_LWL<233> A_LWL<232> A_LWL<231> A_LWL<230> A_LWL<229> A_LWL<228> A_LWL<227> A_LWL<226> A_LWL<225> A_LWL<224> A_RWL<239> A_RWL<238> A_RWL<237> A_RWL<236> A_RWL<235> A_RWL<234> A_RWL<233> A_RWL<232> A_RWL<231> A_RWL<230> A_RWL<229> A_RWL<228> A_RWL<227> A_RWL<226> A_RWL<225> A_RWL<224> B_BLC<27> B_BLC<26> B_BLC<29> B_BLC<28> B_BLT<27> B_BLT<26> B_BLT<29> B_BLT<28> B_LWL<239> B_LWL<238> B_LWL<237> B_LWL<236> B_LWL<235> B_LWL<234> B_LWL<233> B_LWL<232> B_LWL<231> B_LWL<230> B_LWL<229> B_LWL<228> B_LWL<227> B_LWL<226> B_LWL<225> B_LWL<224> B_RWL<239> B_RWL<238> B_RWL<237> B_RWL<236> B_RWL<235> B_RWL<234> B_RWL<233> B_RWL<232> B_RWL<231> B_RWL<230> B_RWL<229> B_RWL<228> B_RWL<227> B_RWL<226> B_RWL<225> B_RWL<224> VDD_CORE VSS / RM_IHPSG13_1024x16_c2_2P_BITKIT_16x2_SRAM +XRAM<14> A_BLC<25> A_BLC<24> A_BLC<27> A_BLC<26> A_BLT<25> A_BLT<24> A_BLT<27> A_BLT<26> A_LWL<223> A_LWL<222> A_LWL<221> A_LWL<220> A_LWL<219> A_LWL<218> A_LWL<217> A_LWL<216> A_LWL<215> A_LWL<214> A_LWL<213> A_LWL<212> A_LWL<211> A_LWL<210> A_LWL<209> A_LWL<208> A_RWL<223> A_RWL<222> A_RWL<221> A_RWL<220> A_RWL<219> A_RWL<218> A_RWL<217> A_RWL<216> A_RWL<215> A_RWL<214> A_RWL<213> A_RWL<212> A_RWL<211> A_RWL<210> A_RWL<209> A_RWL<208> B_BLC<25> B_BLC<24> B_BLC<27> B_BLC<26> B_BLT<25> B_BLT<24> B_BLT<27> B_BLT<26> B_LWL<223> B_LWL<222> B_LWL<221> B_LWL<220> B_LWL<219> B_LWL<218> B_LWL<217> B_LWL<216> B_LWL<215> B_LWL<214> B_LWL<213> B_LWL<212> B_LWL<211> B_LWL<210> B_LWL<209> B_LWL<208> B_RWL<223> B_RWL<222> B_RWL<221> B_RWL<220> B_RWL<219> B_RWL<218> B_RWL<217> B_RWL<216> B_RWL<215> B_RWL<214> B_RWL<213> B_RWL<212> B_RWL<211> B_RWL<210> B_RWL<209> B_RWL<208> VDD_CORE VSS / RM_IHPSG13_1024x16_c2_2P_BITKIT_16x2_SRAM +XRAM<13> A_BLC<23> A_BLC<22> A_BLC<25> A_BLC<24> A_BLT<23> A_BLT<22> A_BLT<25> A_BLT<24> A_LWL<207> A_LWL<206> A_LWL<205> A_LWL<204> A_LWL<203> A_LWL<202> A_LWL<201> A_LWL<200> A_LWL<199> A_LWL<198> A_LWL<197> A_LWL<196> A_LWL<195> A_LWL<194> A_LWL<193> A_LWL<192> A_RWL<207> A_RWL<206> A_RWL<205> A_RWL<204> A_RWL<203> A_RWL<202> A_RWL<201> A_RWL<200> A_RWL<199> A_RWL<198> A_RWL<197> A_RWL<196> A_RWL<195> A_RWL<194> A_RWL<193> A_RWL<192> B_BLC<23> B_BLC<22> B_BLC<25> B_BLC<24> B_BLT<23> B_BLT<22> B_BLT<25> B_BLT<24> B_LWL<207> B_LWL<206> B_LWL<205> B_LWL<204> B_LWL<203> B_LWL<202> B_LWL<201> B_LWL<200> B_LWL<199> B_LWL<198> B_LWL<197> B_LWL<196> B_LWL<195> B_LWL<194> B_LWL<193> B_LWL<192> B_RWL<207> B_RWL<206> B_RWL<205> B_RWL<204> B_RWL<203> B_RWL<202> B_RWL<201> B_RWL<200> B_RWL<199> B_RWL<198> B_RWL<197> B_RWL<196> B_RWL<195> B_RWL<194> B_RWL<193> B_RWL<192> VDD_CORE VSS / RM_IHPSG13_1024x16_c2_2P_BITKIT_16x2_SRAM +XRAM<12> A_BLC<21> A_BLC<20> A_BLC<23> A_BLC<22> A_BLT<21> A_BLT<20> A_BLT<23> A_BLT<22> A_LWL<191> A_LWL<190> A_LWL<189> A_LWL<188> A_LWL<187> A_LWL<186> A_LWL<185> A_LWL<184> A_LWL<183> A_LWL<182> A_LWL<181> A_LWL<180> A_LWL<179> A_LWL<178> A_LWL<177> A_LWL<176> A_RWL<191> A_RWL<190> A_RWL<189> A_RWL<188> A_RWL<187> A_RWL<186> A_RWL<185> A_RWL<184> A_RWL<183> A_RWL<182> A_RWL<181> A_RWL<180> A_RWL<179> A_RWL<178> A_RWL<177> A_RWL<176> B_BLC<21> B_BLC<20> B_BLC<23> B_BLC<22> B_BLT<21> B_BLT<20> B_BLT<23> B_BLT<22> B_LWL<191> B_LWL<190> B_LWL<189> B_LWL<188> B_LWL<187> B_LWL<186> B_LWL<185> B_LWL<184> B_LWL<183> B_LWL<182> B_LWL<181> B_LWL<180> B_LWL<179> B_LWL<178> B_LWL<177> B_LWL<176> B_RWL<191> B_RWL<190> B_RWL<189> B_RWL<188> B_RWL<187> B_RWL<186> B_RWL<185> B_RWL<184> B_RWL<183> B_RWL<182> B_RWL<181> B_RWL<180> B_RWL<179> B_RWL<178> B_RWL<177> B_RWL<176> VDD_CORE VSS / RM_IHPSG13_1024x16_c2_2P_BITKIT_16x2_SRAM +XRAM<11> A_BLC<19> A_BLC<18> A_BLC<21> A_BLC<20> A_BLT<19> A_BLT<18> A_BLT<21> A_BLT<20> A_LWL<175> A_LWL<174> A_LWL<173> A_LWL<172> A_LWL<171> A_LWL<170> A_LWL<169> A_LWL<168> A_LWL<167> A_LWL<166> A_LWL<165> A_LWL<164> A_LWL<163> A_LWL<162> A_LWL<161> A_LWL<160> A_RWL<175> A_RWL<174> A_RWL<173> A_RWL<172> A_RWL<171> A_RWL<170> A_RWL<169> A_RWL<168> A_RWL<167> A_RWL<166> A_RWL<165> A_RWL<164> A_RWL<163> A_RWL<162> A_RWL<161> A_RWL<160> B_BLC<19> B_BLC<18> B_BLC<21> B_BLC<20> B_BLT<19> B_BLT<18> B_BLT<21> B_BLT<20> B_LWL<175> B_LWL<174> B_LWL<173> B_LWL<172> B_LWL<171> B_LWL<170> B_LWL<169> B_LWL<168> B_LWL<167> B_LWL<166> B_LWL<165> B_LWL<164> B_LWL<163> B_LWL<162> B_LWL<161> B_LWL<160> B_RWL<175> B_RWL<174> B_RWL<173> B_RWL<172> B_RWL<171> B_RWL<170> B_RWL<169> B_RWL<168> B_RWL<167> B_RWL<166> B_RWL<165> B_RWL<164> B_RWL<163> B_RWL<162> B_RWL<161> B_RWL<160> VDD_CORE VSS / RM_IHPSG13_1024x16_c2_2P_BITKIT_16x2_SRAM +XRAM<10> A_BLC<17> A_BLC<16> A_BLC<19> A_BLC<18> A_BLT<17> A_BLT<16> A_BLT<19> A_BLT<18> A_LWL<159> A_LWL<158> A_LWL<157> A_LWL<156> A_LWL<155> A_LWL<154> A_LWL<153> A_LWL<152> A_LWL<151> A_LWL<150> A_LWL<149> A_LWL<148> A_LWL<147> A_LWL<146> A_LWL<145> A_LWL<144> A_RWL<159> A_RWL<158> A_RWL<157> A_RWL<156> A_RWL<155> A_RWL<154> A_RWL<153> A_RWL<152> A_RWL<151> A_RWL<150> A_RWL<149> A_RWL<148> A_RWL<147> A_RWL<146> A_RWL<145> A_RWL<144> B_BLC<17> B_BLC<16> B_BLC<19> B_BLC<18> B_BLT<17> B_BLT<16> B_BLT<19> B_BLT<18> B_LWL<159> B_LWL<158> B_LWL<157> B_LWL<156> B_LWL<155> B_LWL<154> B_LWL<153> B_LWL<152> B_LWL<151> B_LWL<150> B_LWL<149> B_LWL<148> B_LWL<147> B_LWL<146> B_LWL<145> B_LWL<144> B_RWL<159> B_RWL<158> B_RWL<157> B_RWL<156> B_RWL<155> B_RWL<154> B_RWL<153> B_RWL<152> B_RWL<151> B_RWL<150> B_RWL<149> B_RWL<148> B_RWL<147> B_RWL<146> B_RWL<145> B_RWL<144> VDD_CORE VSS / RM_IHPSG13_1024x16_c2_2P_BITKIT_16x2_SRAM +XRAM<9> A_BLC<15> A_BLC<14> A_BLC<17> A_BLC<16> A_BLT<15> A_BLT<14> A_BLT<17> A_BLT<16> A_LWL<143> A_LWL<142> A_LWL<141> A_LWL<140> A_LWL<139> A_LWL<138> A_LWL<137> A_LWL<136> A_LWL<135> A_LWL<134> A_LWL<133> A_LWL<132> A_LWL<131> A_LWL<130> A_LWL<129> A_LWL<128> A_RWL<143> A_RWL<142> A_RWL<141> A_RWL<140> A_RWL<139> A_RWL<138> A_RWL<137> A_RWL<136> A_RWL<135> A_RWL<134> A_RWL<133> A_RWL<132> A_RWL<131> A_RWL<130> A_RWL<129> A_RWL<128> B_BLC<15> B_BLC<14> B_BLC<17> B_BLC<16> B_BLT<15> B_BLT<14> B_BLT<17> B_BLT<16> B_LWL<143> B_LWL<142> B_LWL<141> B_LWL<140> B_LWL<139> B_LWL<138> B_LWL<137> B_LWL<136> B_LWL<135> B_LWL<134> B_LWL<133> B_LWL<132> B_LWL<131> B_LWL<130> B_LWL<129> B_LWL<128> B_RWL<143> B_RWL<142> B_RWL<141> B_RWL<140> B_RWL<139> B_RWL<138> B_RWL<137> B_RWL<136> B_RWL<135> B_RWL<134> B_RWL<133> B_RWL<132> B_RWL<131> B_RWL<130> B_RWL<129> B_RWL<128> VDD_CORE VSS / RM_IHPSG13_1024x16_c2_2P_BITKIT_16x2_SRAM +XRAM<8> A_BLC<13> A_BLC<12> A_BLC<15> A_BLC<14> A_BLT<13> A_BLT<12> A_BLT<15> A_BLT<14> A_LWL<127> A_LWL<126> A_LWL<125> A_LWL<124> A_LWL<123> A_LWL<122> A_LWL<121> A_LWL<120> A_LWL<119> A_LWL<118> A_LWL<117> A_LWL<116> A_LWL<115> A_LWL<114> A_LWL<113> A_LWL<112> A_RWL<127> A_RWL<126> A_RWL<125> A_RWL<124> A_RWL<123> A_RWL<122> A_RWL<121> A_RWL<120> A_RWL<119> A_RWL<118> A_RWL<117> A_RWL<116> A_RWL<115> A_RWL<114> A_RWL<113> A_RWL<112> B_BLC<13> B_BLC<12> B_BLC<15> B_BLC<14> B_BLT<13> B_BLT<12> B_BLT<15> B_BLT<14> B_LWL<127> B_LWL<126> B_LWL<125> B_LWL<124> B_LWL<123> B_LWL<122> B_LWL<121> B_LWL<120> B_LWL<119> B_LWL<118> B_LWL<117> B_LWL<116> B_LWL<115> B_LWL<114> B_LWL<113> B_LWL<112> B_RWL<127> B_RWL<126> B_RWL<125> B_RWL<124> B_RWL<123> B_RWL<122> B_RWL<121> B_RWL<120> B_RWL<119> B_RWL<118> B_RWL<117> B_RWL<116> B_RWL<115> B_RWL<114> B_RWL<113> B_RWL<112> VDD_CORE VSS / RM_IHPSG13_1024x16_c2_2P_BITKIT_16x2_SRAM +XRAM<7> A_BLC<11> A_BLC<10> A_BLC<13> A_BLC<12> A_BLT<11> A_BLT<10> A_BLT<13> A_BLT<12> A_LWL<111> A_LWL<110> A_LWL<109> A_LWL<108> A_LWL<107> A_LWL<106> A_LWL<105> A_LWL<104> A_LWL<103> A_LWL<102> A_LWL<101> A_LWL<100> A_LWL<99> A_LWL<98> A_LWL<97> A_LWL<96> A_RWL<111> A_RWL<110> A_RWL<109> A_RWL<108> A_RWL<107> A_RWL<106> A_RWL<105> A_RWL<104> A_RWL<103> A_RWL<102> A_RWL<101> A_RWL<100> A_RWL<99> A_RWL<98> A_RWL<97> A_RWL<96> B_BLC<11> B_BLC<10> B_BLC<13> B_BLC<12> B_BLT<11> B_BLT<10> B_BLT<13> B_BLT<12> B_LWL<111> B_LWL<110> B_LWL<109> B_LWL<108> B_LWL<107> B_LWL<106> B_LWL<105> B_LWL<104> B_LWL<103> B_LWL<102> B_LWL<101> B_LWL<100> B_LWL<99> B_LWL<98> B_LWL<97> B_LWL<96> B_RWL<111> B_RWL<110> B_RWL<109> B_RWL<108> B_RWL<107> B_RWL<106> B_RWL<105> B_RWL<104> B_RWL<103> B_RWL<102> B_RWL<101> B_RWL<100> B_RWL<99> B_RWL<98> B_RWL<97> B_RWL<96> VDD_CORE VSS / RM_IHPSG13_1024x16_c2_2P_BITKIT_16x2_SRAM +XRAM<6> A_BLC<9> A_BLC<8> A_BLC<11> A_BLC<10> A_BLT<9> A_BLT<8> A_BLT<11> A_BLT<10> A_LWL<95> A_LWL<94> A_LWL<93> A_LWL<92> A_LWL<91> A_LWL<90> A_LWL<89> A_LWL<88> A_LWL<87> A_LWL<86> A_LWL<85> A_LWL<84> A_LWL<83> A_LWL<82> A_LWL<81> A_LWL<80> A_RWL<95> A_RWL<94> A_RWL<93> A_RWL<92> A_RWL<91> A_RWL<90> A_RWL<89> A_RWL<88> A_RWL<87> A_RWL<86> A_RWL<85> A_RWL<84> A_RWL<83> A_RWL<82> A_RWL<81> A_RWL<80> B_BLC<9> B_BLC<8> B_BLC<11> B_BLC<10> B_BLT<9> B_BLT<8> B_BLT<11> B_BLT<10> B_LWL<95> B_LWL<94> B_LWL<93> B_LWL<92> B_LWL<91> B_LWL<90> B_LWL<89> B_LWL<88> B_LWL<87> B_LWL<86> B_LWL<85> B_LWL<84> B_LWL<83> B_LWL<82> B_LWL<81> B_LWL<80> B_RWL<95> B_RWL<94> B_RWL<93> B_RWL<92> B_RWL<91> B_RWL<90> B_RWL<89> B_RWL<88> B_RWL<87> B_RWL<86> B_RWL<85> B_RWL<84> B_RWL<83> B_RWL<82> B_RWL<81> B_RWL<80> VDD_CORE VSS / RM_IHPSG13_1024x16_c2_2P_BITKIT_16x2_SRAM +XRAM<5> A_BLC<7> A_BLC<6> A_BLC<9> A_BLC<8> A_BLT<7> A_BLT<6> A_BLT<9> A_BLT<8> A_LWL<79> A_LWL<78> A_LWL<77> A_LWL<76> A_LWL<75> A_LWL<74> A_LWL<73> A_LWL<72> A_LWL<71> A_LWL<70> A_LWL<69> A_LWL<68> A_LWL<67> A_LWL<66> A_LWL<65> A_LWL<64> A_RWL<79> A_RWL<78> A_RWL<77> A_RWL<76> A_RWL<75> A_RWL<74> A_RWL<73> A_RWL<72> A_RWL<71> A_RWL<70> A_RWL<69> A_RWL<68> A_RWL<67> A_RWL<66> A_RWL<65> A_RWL<64> B_BLC<7> B_BLC<6> B_BLC<9> B_BLC<8> B_BLT<7> B_BLT<6> B_BLT<9> B_BLT<8> B_LWL<79> B_LWL<78> B_LWL<77> B_LWL<76> B_LWL<75> B_LWL<74> B_LWL<73> B_LWL<72> B_LWL<71> B_LWL<70> B_LWL<69> B_LWL<68> B_LWL<67> B_LWL<66> B_LWL<65> B_LWL<64> B_RWL<79> B_RWL<78> B_RWL<77> B_RWL<76> B_RWL<75> B_RWL<74> B_RWL<73> B_RWL<72> B_RWL<71> B_RWL<70> B_RWL<69> B_RWL<68> B_RWL<67> B_RWL<66> B_RWL<65> B_RWL<64> VDD_CORE VSS / RM_IHPSG13_1024x16_c2_2P_BITKIT_16x2_SRAM +XRAM<4> A_BLC<5> A_BLC<4> A_BLC<7> A_BLC<6> A_BLT<5> A_BLT<4> A_BLT<7> A_BLT<6> A_LWL<63> A_LWL<62> A_LWL<61> A_LWL<60> A_LWL<59> A_LWL<58> A_LWL<57> A_LWL<56> A_LWL<55> A_LWL<54> A_LWL<53> A_LWL<52> A_LWL<51> A_LWL<50> A_LWL<49> A_LWL<48> A_RWL<63> A_RWL<62> A_RWL<61> A_RWL<60> A_RWL<59> A_RWL<58> A_RWL<57> A_RWL<56> A_RWL<55> A_RWL<54> A_RWL<53> A_RWL<52> A_RWL<51> A_RWL<50> A_RWL<49> A_RWL<48> B_BLC<5> B_BLC<4> B_BLC<7> B_BLC<6> B_BLT<5> B_BLT<4> B_BLT<7> B_BLT<6> B_LWL<63> B_LWL<62> B_LWL<61> B_LWL<60> B_LWL<59> B_LWL<58> B_LWL<57> B_LWL<56> B_LWL<55> B_LWL<54> B_LWL<53> B_LWL<52> B_LWL<51> B_LWL<50> B_LWL<49> B_LWL<48> B_RWL<63> B_RWL<62> B_RWL<61> B_RWL<60> B_RWL<59> B_RWL<58> B_RWL<57> B_RWL<56> B_RWL<55> B_RWL<54> B_RWL<53> B_RWL<52> B_RWL<51> B_RWL<50> B_RWL<49> B_RWL<48> VDD_CORE VSS / RM_IHPSG13_1024x16_c2_2P_BITKIT_16x2_SRAM +XRAM<3> A_BLC<3> A_BLC<2> A_BLC<5> A_BLC<4> A_BLT<3> A_BLT<2> A_BLT<5> A_BLT<4> A_LWL<47> A_LWL<46> A_LWL<45> A_LWL<44> A_LWL<43> A_LWL<42> A_LWL<41> A_LWL<40> A_LWL<39> A_LWL<38> A_LWL<37> A_LWL<36> A_LWL<35> A_LWL<34> A_LWL<33> A_LWL<32> A_RWL<47> A_RWL<46> A_RWL<45> A_RWL<44> A_RWL<43> A_RWL<42> A_RWL<41> A_RWL<40> A_RWL<39> A_RWL<38> A_RWL<37> A_RWL<36> A_RWL<35> A_RWL<34> A_RWL<33> A_RWL<32> B_BLC<3> B_BLC<2> B_BLC<5> B_BLC<4> B_BLT<3> B_BLT<2> B_BLT<5> B_BLT<4> B_LWL<47> B_LWL<46> B_LWL<45> B_LWL<44> B_LWL<43> B_LWL<42> B_LWL<41> B_LWL<40> B_LWL<39> B_LWL<38> B_LWL<37> B_LWL<36> B_LWL<35> B_LWL<34> B_LWL<33> B_LWL<32> B_RWL<47> B_RWL<46> B_RWL<45> B_RWL<44> B_RWL<43> B_RWL<42> B_RWL<41> B_RWL<40> B_RWL<39> B_RWL<38> B_RWL<37> B_RWL<36> B_RWL<35> B_RWL<34> B_RWL<33> B_RWL<32> VDD_CORE VSS / RM_IHPSG13_1024x16_c2_2P_BITKIT_16x2_SRAM +XRAM<2> A_BLC<1> A_BLC<0> A_BLC<3> A_BLC<2> A_BLT<1> A_BLT<0> A_BLT<3> A_BLT<2> A_LWL<31> A_LWL<30> A_LWL<29> A_LWL<28> A_LWL<27> A_LWL<26> A_LWL<25> A_LWL<24> A_LWL<23> A_LWL<22> A_LWL<21> A_LWL<20> A_LWL<19> A_LWL<18> A_LWL<17> A_LWL<16> A_RWL<31> A_RWL<30> A_RWL<29> A_RWL<28> A_RWL<27> A_RWL<26> A_RWL<25> A_RWL<24> A_RWL<23> A_RWL<22> A_RWL<21> A_RWL<20> A_RWL<19> A_RWL<18> A_RWL<17> A_RWL<16> B_BLC<1> B_BLC<0> B_BLC<3> B_BLC<2> B_BLT<1> B_BLT<0> B_BLT<3> B_BLT<2> B_LWL<31> B_LWL<30> B_LWL<29> B_LWL<28> B_LWL<27> B_LWL<26> B_LWL<25> B_LWL<24> B_LWL<23> B_LWL<22> B_LWL<21> B_LWL<20> B_LWL<19> B_LWL<18> B_LWL<17> B_LWL<16> B_RWL<31> B_RWL<30> B_RWL<29> B_RWL<28> B_RWL<27> B_RWL<26> B_RWL<25> B_RWL<24> B_RWL<23> B_RWL<22> B_RWL<21> B_RWL<20> B_RWL<19> B_RWL<18> B_RWL<17> B_RWL<16> VDD_CORE VSS / RM_IHPSG13_1024x16_c2_2P_BITKIT_16x2_SRAM +XRAM<1> A_BLC_BOT<1> A_BLC_BOT<0> A_BLC<1> A_BLC<0> A_BLT_BOT<1> A_BLT_BOT<0> A_BLT<1> A_BLT<0> A_LWL<15> A_LWL<14> A_LWL<13> A_LWL<12> A_LWL<11> A_LWL<10> A_LWL<9> A_LWL<8> A_LWL<7> A_LWL<6> A_LWL<5> A_LWL<4> A_LWL<3> A_LWL<2> A_LWL<1> A_LWL<0> A_RWL<15> A_RWL<14> A_RWL<13> A_RWL<12> A_RWL<11> A_RWL<10> A_RWL<9> A_RWL<8> A_RWL<7> A_RWL<6> A_RWL<5> A_RWL<4> A_RWL<3> A_RWL<2> A_RWL<1> A_RWL<0> B_BLC_BOT<1> B_BLC_BOT<0> B_BLC<1> B_BLC<0> B_BLT_BOT<1> B_BLT_BOT<0> B_BLT<1> B_BLT<0> B_LWL<15> B_LWL<14> B_LWL<13> B_LWL<12> B_LWL<11> B_LWL<10> B_LWL<9> B_LWL<8> B_LWL<7> B_LWL<6> B_LWL<5> B_LWL<4> B_LWL<3> B_LWL<2> B_LWL<1> B_LWL<0> B_RWL<15> B_RWL<14> B_RWL<13> B_RWL<12> B_RWL<11> B_RWL<10> B_RWL<9> B_RWL<8> B_RWL<7> B_RWL<6> B_RWL<5> B_RWL<4> B_RWL<3> B_RWL<2> B_RWL<1> B_RWL<0> VDD_CORE VSS / RM_IHPSG13_1024x16_c2_2P_BITKIT_16x2_SRAM +XEDGE<1> A_BLC_TOP<1> A_BLC_TOP<0> A_BLT_TOP<1> A_BLT_TOP<0> B_BLC_TOP<1> B_BLC_TOP<0> B_BLT_TOP<1> B_BLT_TOP<0> VDD_CORE VSS / RM_IHPSG13_1024x16_c2_2P_BITKIT_16x2_EDGE_TB +XEDGE<0> A_BLC_BOT<1> A_BLC_BOT<0> A_BLT_BOT<1> A_BLT_BOT<0> B_BLC_BOT<1> B_BLC_BOT<0> B_BLT_BOT<1> B_BLT_BOT<0> VDD_CORE VSS / RM_IHPSG13_1024x16_c2_2P_BITKIT_16x2_EDGE_TB +.ENDS + + + + +.SUBCKT RM_IHPSG13_1024x16_c2_2P_MATRIX_pcell_1 A_BLC<31> A_BLC<30> A_BLC<29> A_BLC<28> A_BLC<27> A_BLC<26> A_BLC<25> A_BLC<24> A_BLC<23> A_BLC<22> A_BLC<21> A_BLC<20> A_BLC<19> A_BLC<18> A_BLC<17> A_BLC<16> A_BLC<15> A_BLC<14> A_BLC<13> A_BLC<12> A_BLC<11> A_BLC<10> A_BLC<9> A_BLC<8> A_BLC<7> A_BLC<6> A_BLC<5> A_BLC<4> A_BLC<3> A_BLC<2> A_BLC<1> A_BLC<0> A_BLT<31> A_BLT<30> A_BLT<29> A_BLT<28> A_BLT<27> A_BLT<26> A_BLT<25> A_BLT<24> A_BLT<23> A_BLT<22> A_BLT<21> A_BLT<20> A_BLT<19> A_BLT<18> A_BLT<17> A_BLT<16> A_BLT<15> A_BLT<14> A_BLT<13> A_BLT<12> A_BLT<11> A_BLT<10> A_BLT<9> A_BLT<8> A_BLT<7> A_BLT<6> A_BLT<5> A_BLT<4> A_BLT<3> A_BLT<2> A_BLT<1> A_BLT<0> A_WL<255> A_WL<254> A_WL<253> A_WL<252> A_WL<251> A_WL<250> A_WL<249> A_WL<248> A_WL<247> A_WL<246> A_WL<245> A_WL<244> A_WL<243> A_WL<242> A_WL<241> A_WL<240> A_WL<239> A_WL<238> A_WL<237> A_WL<236> A_WL<235> A_WL<234> A_WL<233> A_WL<232> A_WL<231> A_WL<230> A_WL<229> A_WL<228> A_WL<227> A_WL<226> A_WL<225> A_WL<224> A_WL<223> A_WL<222> A_WL<221> A_WL<220> A_WL<219> A_WL<218> A_WL<217> A_WL<216> A_WL<215> A_WL<214> A_WL<213> A_WL<212> A_WL<211> A_WL<210> A_WL<209> A_WL<208> A_WL<207> A_WL<206> A_WL<205> A_WL<204> A_WL<203> A_WL<202> A_WL<201> A_WL<200> A_WL<199> A_WL<198> A_WL<197> A_WL<196> A_WL<195> A_WL<194> A_WL<193> A_WL<192> A_WL<191> A_WL<190> A_WL<189> A_WL<188> A_WL<187> A_WL<186> A_WL<185> A_WL<184> A_WL<183> A_WL<182> A_WL<181> A_WL<180> A_WL<179> A_WL<178> A_WL<177> A_WL<176> A_WL<175> A_WL<174> A_WL<173> A_WL<172> A_WL<171> A_WL<170> A_WL<169> A_WL<168> A_WL<167> A_WL<166> A_WL<165> A_WL<164> A_WL<163> A_WL<162> A_WL<161> A_WL<160> A_WL<159> A_WL<158> A_WL<157> A_WL<156> A_WL<155> A_WL<154> A_WL<153> A_WL<152> A_WL<151> A_WL<150> A_WL<149> A_WL<148> A_WL<147> A_WL<146> A_WL<145> A_WL<144> A_WL<143> A_WL<142> A_WL<141> A_WL<140> A_WL<139> A_WL<138> A_WL<137> A_WL<136> A_WL<135> A_WL<134> A_WL<133> A_WL<132> A_WL<131> A_WL<130> A_WL<129> A_WL<128> A_WL<127> A_WL<126> A_WL<125> A_WL<124> A_WL<123> A_WL<122> A_WL<121> A_WL<120> A_WL<119> A_WL<118> A_WL<117> A_WL<116> A_WL<115> A_WL<114> A_WL<113> A_WL<112> A_WL<111> A_WL<110> A_WL<109> A_WL<108> A_WL<107> A_WL<106> A_WL<105> A_WL<104> A_WL<103> A_WL<102> A_WL<101> A_WL<100> A_WL<99> A_WL<98> A_WL<97> A_WL<96> A_WL<95> A_WL<94> A_WL<93> A_WL<92> A_WL<91> A_WL<90> A_WL<89> A_WL<88> A_WL<87> A_WL<86> A_WL<85> A_WL<84> A_WL<83> A_WL<82> A_WL<81> A_WL<80> A_WL<79> A_WL<78> A_WL<77> A_WL<76> A_WL<75> A_WL<74> A_WL<73> A_WL<72> A_WL<71> A_WL<70> A_WL<69> A_WL<68> A_WL<67> A_WL<66> A_WL<65> A_WL<64> A_WL<63> A_WL<62> A_WL<61> A_WL<60> A_WL<59> A_WL<58> A_WL<57> A_WL<56> A_WL<55> A_WL<54> A_WL<53> A_WL<52> A_WL<51> A_WL<50> A_WL<49> A_WL<48> A_WL<47> A_WL<46> A_WL<45> A_WL<44> A_WL<43> A_WL<42> A_WL<41> A_WL<40> A_WL<39> A_WL<38> A_WL<37> A_WL<36> A_WL<35> A_WL<34> A_WL<33> A_WL<32> A_WL<31> A_WL<30> A_WL<29> A_WL<28> A_WL<27> A_WL<26> A_WL<25> A_WL<24> A_WL<23> A_WL<22> A_WL<21> A_WL<20> A_WL<19> A_WL<18> A_WL<17> A_WL<16> A_WL<15> A_WL<14> A_WL<13> A_WL<12> A_WL<11> A_WL<10> A_WL<9> A_WL<8> A_WL<7> A_WL<6> A_WL<5> A_WL<4> A_WL<3> A_WL<2> A_WL<1> A_WL<0> B_BLC<31> B_BLC<30> B_BLC<29> B_BLC<28> B_BLC<27> B_BLC<26> B_BLC<25> B_BLC<24> B_BLC<23> B_BLC<22> B_BLC<21> B_BLC<20> B_BLC<19> B_BLC<18> B_BLC<17> B_BLC<16> B_BLC<15> B_BLC<14> B_BLC<13> B_BLC<12> B_BLC<11> B_BLC<10> B_BLC<9> B_BLC<8> B_BLC<7> B_BLC<6> B_BLC<5> B_BLC<4> B_BLC<3> B_BLC<2> B_BLC<1> B_BLC<0> B_BLT<31> B_BLT<30> B_BLT<29> B_BLT<28> B_BLT<27> B_BLT<26> B_BLT<25> B_BLT<24> B_BLT<23> B_BLT<22> B_BLT<21> B_BLT<20> B_BLT<19> B_BLT<18> B_BLT<17> B_BLT<16> B_BLT<15> B_BLT<14> B_BLT<13> B_BLT<12> B_BLT<11> B_BLT<10> B_BLT<9> B_BLT<8> B_BLT<7> B_BLT<6> B_BLT<5> B_BLT<4> B_BLT<3> B_BLT<2> B_BLT<1> B_BLT<0> B_WL<255> B_WL<254> B_WL<253> B_WL<252> B_WL<251> B_WL<250> B_WL<249> B_WL<248> B_WL<247> B_WL<246> B_WL<245> B_WL<244> B_WL<243> B_WL<242> B_WL<241> B_WL<240> B_WL<239> B_WL<238> B_WL<237> B_WL<236> B_WL<235> B_WL<234> B_WL<233> B_WL<232> B_WL<231> B_WL<230> B_WL<229> B_WL<228> B_WL<227> B_WL<226> B_WL<225> B_WL<224> B_WL<223> B_WL<222> B_WL<221> B_WL<220> B_WL<219> B_WL<218> B_WL<217> B_WL<216> B_WL<215> B_WL<214> B_WL<213> B_WL<212> B_WL<211> B_WL<210> B_WL<209> B_WL<208> B_WL<207> B_WL<206> B_WL<205> B_WL<204> B_WL<203> B_WL<202> B_WL<201> B_WL<200> B_WL<199> B_WL<198> B_WL<197> B_WL<196> B_WL<195> B_WL<194> B_WL<193> B_WL<192> B_WL<191> B_WL<190> B_WL<189> B_WL<188> B_WL<187> B_WL<186> B_WL<185> B_WL<184> B_WL<183> B_WL<182> B_WL<181> B_WL<180> B_WL<179> B_WL<178> B_WL<177> B_WL<176> B_WL<175> B_WL<174> B_WL<173> B_WL<172> B_WL<171> B_WL<170> B_WL<169> B_WL<168> B_WL<167> B_WL<166> B_WL<165> B_WL<164> B_WL<163> B_WL<162> B_WL<161> B_WL<160> B_WL<159> B_WL<158> B_WL<157> B_WL<156> B_WL<155> B_WL<154> B_WL<153> B_WL<152> B_WL<151> B_WL<150> B_WL<149> B_WL<148> B_WL<147> B_WL<146> B_WL<145> B_WL<144> B_WL<143> B_WL<142> B_WL<141> B_WL<140> B_WL<139> B_WL<138> B_WL<137> B_WL<136> B_WL<135> B_WL<134> B_WL<133> B_WL<132> B_WL<131> B_WL<130> B_WL<129> B_WL<128> B_WL<127> B_WL<126> B_WL<125> B_WL<124> B_WL<123> B_WL<122> B_WL<121> B_WL<120> B_WL<119> B_WL<118> B_WL<117> B_WL<116> B_WL<115> B_WL<114> B_WL<113> B_WL<112> B_WL<111> B_WL<110> B_WL<109> B_WL<108> B_WL<107> B_WL<106> B_WL<105> B_WL<104> B_WL<103> B_WL<102> B_WL<101> B_WL<100> B_WL<99> B_WL<98> B_WL<97> B_WL<96> B_WL<95> B_WL<94> B_WL<93> B_WL<92> B_WL<91> B_WL<90> B_WL<89> B_WL<88> B_WL<87> B_WL<86> B_WL<85> B_WL<84> B_WL<83> B_WL<82> B_WL<81> B_WL<80> B_WL<79> B_WL<78> B_WL<77> B_WL<76> B_WL<75> B_WL<74> B_WL<73> B_WL<72> B_WL<71> B_WL<70> B_WL<69> B_WL<68> B_WL<67> B_WL<66> B_WL<65> B_WL<64> B_WL<63> B_WL<62> B_WL<61> B_WL<60> B_WL<59> B_WL<58> B_WL<57> B_WL<56> B_WL<55> B_WL<54> B_WL<53> B_WL<52> B_WL<51> B_WL<50> B_WL<49> B_WL<48> B_WL<47> B_WL<46> B_WL<45> B_WL<44> B_WL<43> B_WL<42> B_WL<41> B_WL<40> B_WL<39> B_WL<38> B_WL<37> B_WL<36> B_WL<35> B_WL<34> B_WL<33> B_WL<32> B_WL<31> B_WL<30> B_WL<29> B_WL<28> B_WL<27> B_WL<26> B_WL<25> B_WL<24> B_WL<23> B_WL<22> B_WL<21> B_WL<20> B_WL<19> B_WL<18> B_WL<17> B_WL<16> B_WL<15> B_WL<14> B_WL<13> B_WL<12> B_WL<11> B_WL<10> B_WL<9> B_WL<8> B_WL<7> B_WL<6> B_WL<5> B_WL<4> B_WL<3> B_WL<2> B_WL<1> B_WL<0> VDD_CORE VSS +XCORNER<3> VDD_CORE VSS / RM_IHPSG13_1024x16_c2_2P_BITKIT_16x2_CORNER +XCORNER<2> VDD_CORE VSS / RM_IHPSG13_1024x16_c2_2P_BITKIT_16x2_CORNER +XCORNER<1> VDD_CORE VSS / RM_IHPSG13_1024x16_c2_2P_BITKIT_16x2_CORNER +XCORNER<0> VDD_CORE VSS / RM_IHPSG13_1024x16_c2_2P_BITKIT_16x2_CORNER +XRAMEDGE_L<15> A_WL<255> A_WL<254> A_WL<253> A_WL<252> A_WL<251> A_WL<250> A_WL<249> A_WL<248> A_WL<247> A_WL<246> A_WL<245> A_WL<244> A_WL<243> A_WL<242> A_WL<241> A_WL<240> B_WL<255> B_WL<254> B_WL<253> B_WL<252> B_WL<251> B_WL<250> B_WL<249> B_WL<248> B_WL<247> B_WL<246> B_WL<245> B_WL<244> B_WL<243> B_WL<242> B_WL<241> B_WL<240> VDD_CORE VSS / RM_IHPSG13_1024x16_c2_2P_BITKIT_16x2_EDGE_LR +XRAMEDGE_L<14> A_WL<239> A_WL<238> A_WL<237> A_WL<236> A_WL<235> A_WL<234> A_WL<233> A_WL<232> A_WL<231> A_WL<230> A_WL<229> A_WL<228> A_WL<227> A_WL<226> A_WL<225> A_WL<224> B_WL<239> B_WL<238> B_WL<237> B_WL<236> B_WL<235> B_WL<234> B_WL<233> B_WL<232> B_WL<231> B_WL<230> B_WL<229> B_WL<228> B_WL<227> B_WL<226> B_WL<225> B_WL<224> VDD_CORE VSS / RM_IHPSG13_1024x16_c2_2P_BITKIT_16x2_EDGE_LR +XRAMEDGE_L<13> A_WL<223> A_WL<222> A_WL<221> A_WL<220> A_WL<219> A_WL<218> A_WL<217> A_WL<216> A_WL<215> A_WL<214> A_WL<213> A_WL<212> A_WL<211> A_WL<210> A_WL<209> A_WL<208> B_WL<223> B_WL<222> B_WL<221> B_WL<220> B_WL<219> B_WL<218> B_WL<217> B_WL<216> B_WL<215> B_WL<214> B_WL<213> B_WL<212> B_WL<211> B_WL<210> B_WL<209> B_WL<208> VDD_CORE VSS / RM_IHPSG13_1024x16_c2_2P_BITKIT_16x2_EDGE_LR +XRAMEDGE_L<12> A_WL<207> A_WL<206> A_WL<205> A_WL<204> A_WL<203> A_WL<202> A_WL<201> A_WL<200> A_WL<199> A_WL<198> A_WL<197> A_WL<196> A_WL<195> A_WL<194> A_WL<193> A_WL<192> B_WL<207> B_WL<206> B_WL<205> B_WL<204> B_WL<203> B_WL<202> B_WL<201> B_WL<200> B_WL<199> B_WL<198> B_WL<197> B_WL<196> B_WL<195> B_WL<194> B_WL<193> B_WL<192> VDD_CORE VSS / RM_IHPSG13_1024x16_c2_2P_BITKIT_16x2_EDGE_LR +XRAMEDGE_L<11> A_WL<191> A_WL<190> A_WL<189> A_WL<188> A_WL<187> A_WL<186> A_WL<185> A_WL<184> A_WL<183> A_WL<182> A_WL<181> A_WL<180> A_WL<179> A_WL<178> A_WL<177> A_WL<176> B_WL<191> B_WL<190> B_WL<189> B_WL<188> B_WL<187> B_WL<186> B_WL<185> B_WL<184> B_WL<183> B_WL<182> B_WL<181> B_WL<180> B_WL<179> B_WL<178> B_WL<177> B_WL<176> VDD_CORE VSS / RM_IHPSG13_1024x16_c2_2P_BITKIT_16x2_EDGE_LR +XRAMEDGE_L<10> A_WL<175> A_WL<174> A_WL<173> A_WL<172> A_WL<171> A_WL<170> A_WL<169> A_WL<168> A_WL<167> A_WL<166> A_WL<165> A_WL<164> A_WL<163> A_WL<162> A_WL<161> A_WL<160> B_WL<175> B_WL<174> B_WL<173> B_WL<172> B_WL<171> B_WL<170> B_WL<169> B_WL<168> B_WL<167> B_WL<166> B_WL<165> B_WL<164> B_WL<163> B_WL<162> B_WL<161> B_WL<160> VDD_CORE VSS / RM_IHPSG13_1024x16_c2_2P_BITKIT_16x2_EDGE_LR +XRAMEDGE_L<9> A_WL<159> A_WL<158> A_WL<157> A_WL<156> A_WL<155> A_WL<154> A_WL<153> A_WL<152> A_WL<151> A_WL<150> A_WL<149> A_WL<148> A_WL<147> A_WL<146> A_WL<145> A_WL<144> B_WL<159> B_WL<158> B_WL<157> B_WL<156> B_WL<155> B_WL<154> B_WL<153> B_WL<152> B_WL<151> B_WL<150> B_WL<149> B_WL<148> B_WL<147> B_WL<146> B_WL<145> B_WL<144> VDD_CORE VSS / RM_IHPSG13_1024x16_c2_2P_BITKIT_16x2_EDGE_LR +XRAMEDGE_L<8> A_WL<143> A_WL<142> A_WL<141> A_WL<140> A_WL<139> A_WL<138> A_WL<137> A_WL<136> A_WL<135> A_WL<134> A_WL<133> A_WL<132> A_WL<131> A_WL<130> A_WL<129> A_WL<128> B_WL<143> B_WL<142> B_WL<141> B_WL<140> B_WL<139> B_WL<138> B_WL<137> B_WL<136> B_WL<135> B_WL<134> B_WL<133> B_WL<132> B_WL<131> B_WL<130> B_WL<129> B_WL<128> VDD_CORE VSS / RM_IHPSG13_1024x16_c2_2P_BITKIT_16x2_EDGE_LR +XRAMEDGE_L<7> A_WL<127> A_WL<126> A_WL<125> A_WL<124> A_WL<123> A_WL<122> A_WL<121> A_WL<120> A_WL<119> A_WL<118> A_WL<117> A_WL<116> A_WL<115> A_WL<114> A_WL<113> A_WL<112> B_WL<127> B_WL<126> B_WL<125> B_WL<124> B_WL<123> B_WL<122> B_WL<121> B_WL<120> B_WL<119> B_WL<118> B_WL<117> B_WL<116> B_WL<115> B_WL<114> B_WL<113> B_WL<112> VDD_CORE VSS / RM_IHPSG13_1024x16_c2_2P_BITKIT_16x2_EDGE_LR +XRAMEDGE_L<6> A_WL<111> A_WL<110> A_WL<109> A_WL<108> A_WL<107> A_WL<106> A_WL<105> A_WL<104> A_WL<103> A_WL<102> A_WL<101> A_WL<100> A_WL<99> A_WL<98> A_WL<97> A_WL<96> B_WL<111> B_WL<110> B_WL<109> B_WL<108> B_WL<107> B_WL<106> B_WL<105> B_WL<104> B_WL<103> B_WL<102> B_WL<101> B_WL<100> B_WL<99> B_WL<98> B_WL<97> B_WL<96> VDD_CORE VSS / RM_IHPSG13_1024x16_c2_2P_BITKIT_16x2_EDGE_LR +XRAMEDGE_L<5> A_WL<95> A_WL<94> A_WL<93> A_WL<92> A_WL<91> A_WL<90> A_WL<89> A_WL<88> A_WL<87> A_WL<86> A_WL<85> A_WL<84> A_WL<83> A_WL<82> A_WL<81> A_WL<80> B_WL<95> B_WL<94> B_WL<93> B_WL<92> B_WL<91> B_WL<90> B_WL<89> B_WL<88> B_WL<87> B_WL<86> B_WL<85> B_WL<84> B_WL<83> B_WL<82> B_WL<81> B_WL<80> VDD_CORE VSS / RM_IHPSG13_1024x16_c2_2P_BITKIT_16x2_EDGE_LR +XRAMEDGE_L<4> A_WL<79> A_WL<78> A_WL<77> A_WL<76> A_WL<75> A_WL<74> A_WL<73> A_WL<72> A_WL<71> A_WL<70> A_WL<69> A_WL<68> A_WL<67> A_WL<66> A_WL<65> A_WL<64> B_WL<79> B_WL<78> B_WL<77> B_WL<76> B_WL<75> B_WL<74> B_WL<73> B_WL<72> B_WL<71> B_WL<70> B_WL<69> B_WL<68> B_WL<67> B_WL<66> B_WL<65> B_WL<64> VDD_CORE VSS / RM_IHPSG13_1024x16_c2_2P_BITKIT_16x2_EDGE_LR +XRAMEDGE_L<3> A_WL<63> A_WL<62> A_WL<61> A_WL<60> A_WL<59> A_WL<58> A_WL<57> A_WL<56> A_WL<55> A_WL<54> A_WL<53> A_WL<52> A_WL<51> A_WL<50> A_WL<49> A_WL<48> B_WL<63> B_WL<62> B_WL<61> B_WL<60> B_WL<59> B_WL<58> B_WL<57> B_WL<56> B_WL<55> B_WL<54> B_WL<53> B_WL<52> B_WL<51> B_WL<50> B_WL<49> B_WL<48> VDD_CORE VSS / RM_IHPSG13_1024x16_c2_2P_BITKIT_16x2_EDGE_LR +XRAMEDGE_L<2> A_WL<47> A_WL<46> A_WL<45> A_WL<44> A_WL<43> A_WL<42> A_WL<41> A_WL<40> A_WL<39> A_WL<38> A_WL<37> A_WL<36> A_WL<35> A_WL<34> A_WL<33> A_WL<32> B_WL<47> B_WL<46> B_WL<45> B_WL<44> B_WL<43> B_WL<42> B_WL<41> B_WL<40> B_WL<39> B_WL<38> B_WL<37> B_WL<36> B_WL<35> B_WL<34> B_WL<33> B_WL<32> VDD_CORE VSS / RM_IHPSG13_1024x16_c2_2P_BITKIT_16x2_EDGE_LR +XRAMEDGE_L<1> A_WL<31> A_WL<30> A_WL<29> A_WL<28> A_WL<27> A_WL<26> A_WL<25> A_WL<24> A_WL<23> A_WL<22> A_WL<21> A_WL<20> A_WL<19> A_WL<18> A_WL<17> A_WL<16> B_WL<31> B_WL<30> B_WL<29> B_WL<28> B_WL<27> B_WL<26> B_WL<25> B_WL<24> B_WL<23> B_WL<22> B_WL<21> B_WL<20> B_WL<19> B_WL<18> B_WL<17> B_WL<16> VDD_CORE VSS / RM_IHPSG13_1024x16_c2_2P_BITKIT_16x2_EDGE_LR +XRAMEDGE_L<0> A_WL<15> A_WL<14> A_WL<13> A_WL<12> A_WL<11> A_WL<10> A_WL<9> A_WL<8> A_WL<7> A_WL<6> A_WL<5> A_WL<4> A_WL<3> A_WL<2> A_WL<1> A_WL<0> B_WL<15> B_WL<14> B_WL<13> B_WL<12> B_WL<11> B_WL<10> B_WL<9> B_WL<8> B_WL<7> B_WL<6> B_WL<5> B_WL<4> B_WL<3> B_WL<2> B_WL<1> B_WL<0> VDD_CORE VSS / RM_IHPSG13_1024x16_c2_2P_BITKIT_16x2_EDGE_LR +XRAMEDGE_R<15> A_IWL<4095> A_IWL<4094> A_IWL<4093> A_IWL<4092> A_IWL<4091> A_IWL<4090> A_IWL<4089> A_IWL<4088> A_IWL<4087> A_IWL<4086> A_IWL<4085> A_IWL<4084> A_IWL<4083> A_IWL<4082> A_IWL<4081> A_IWL<4080> B_IWL<4095> B_IWL<4094> B_IWL<4093> B_IWL<4092> B_IWL<4091> B_IWL<4090> B_IWL<4089> B_IWL<4088> B_IWL<4087> B_IWL<4086> B_IWL<4085> B_IWL<4084> B_IWL<4083> B_IWL<4082> B_IWL<4081> B_IWL<4080> VDD_CORE VSS / RM_IHPSG13_1024x16_c2_2P_BITKIT_16x2_EDGE_LR +XRAMEDGE_R<14> A_IWL<4079> A_IWL<4078> A_IWL<4077> A_IWL<4076> A_IWL<4075> A_IWL<4074> A_IWL<4073> A_IWL<4072> A_IWL<4071> A_IWL<4070> A_IWL<4069> A_IWL<4068> A_IWL<4067> A_IWL<4066> A_IWL<4065> A_IWL<4064> B_IWL<4079> B_IWL<4078> B_IWL<4077> B_IWL<4076> B_IWL<4075> B_IWL<4074> B_IWL<4073> B_IWL<4072> B_IWL<4071> B_IWL<4070> B_IWL<4069> B_IWL<4068> B_IWL<4067> B_IWL<4066> B_IWL<4065> B_IWL<4064> VDD_CORE VSS / RM_IHPSG13_1024x16_c2_2P_BITKIT_16x2_EDGE_LR +XRAMEDGE_R<13> A_IWL<4063> A_IWL<4062> A_IWL<4061> A_IWL<4060> A_IWL<4059> A_IWL<4058> A_IWL<4057> A_IWL<4056> A_IWL<4055> A_IWL<4054> A_IWL<4053> A_IWL<4052> A_IWL<4051> A_IWL<4050> A_IWL<4049> A_IWL<4048> B_IWL<4063> B_IWL<4062> B_IWL<4061> B_IWL<4060> B_IWL<4059> B_IWL<4058> B_IWL<4057> B_IWL<4056> B_IWL<4055> B_IWL<4054> B_IWL<4053> B_IWL<4052> B_IWL<4051> B_IWL<4050> B_IWL<4049> B_IWL<4048> VDD_CORE VSS / RM_IHPSG13_1024x16_c2_2P_BITKIT_16x2_EDGE_LR +XRAMEDGE_R<12> A_IWL<4047> A_IWL<4046> A_IWL<4045> A_IWL<4044> A_IWL<4043> A_IWL<4042> A_IWL<4041> A_IWL<4040> A_IWL<4039> A_IWL<4038> A_IWL<4037> A_IWL<4036> A_IWL<4035> A_IWL<4034> A_IWL<4033> A_IWL<4032> B_IWL<4047> B_IWL<4046> B_IWL<4045> B_IWL<4044> B_IWL<4043> B_IWL<4042> B_IWL<4041> B_IWL<4040> B_IWL<4039> B_IWL<4038> B_IWL<4037> B_IWL<4036> B_IWL<4035> B_IWL<4034> B_IWL<4033> B_IWL<4032> VDD_CORE VSS / RM_IHPSG13_1024x16_c2_2P_BITKIT_16x2_EDGE_LR +XRAMEDGE_R<11> A_IWL<4031> A_IWL<4030> A_IWL<4029> A_IWL<4028> A_IWL<4027> A_IWL<4026> A_IWL<4025> A_IWL<4024> A_IWL<4023> A_IWL<4022> A_IWL<4021> A_IWL<4020> A_IWL<4019> A_IWL<4018> A_IWL<4017> A_IWL<4016> B_IWL<4031> B_IWL<4030> B_IWL<4029> B_IWL<4028> B_IWL<4027> B_IWL<4026> B_IWL<4025> B_IWL<4024> B_IWL<4023> B_IWL<4022> B_IWL<4021> B_IWL<4020> B_IWL<4019> B_IWL<4018> B_IWL<4017> B_IWL<4016> VDD_CORE VSS / RM_IHPSG13_1024x16_c2_2P_BITKIT_16x2_EDGE_LR +XRAMEDGE_R<10> A_IWL<4015> A_IWL<4014> A_IWL<4013> A_IWL<4012> A_IWL<4011> A_IWL<4010> A_IWL<4009> A_IWL<4008> A_IWL<4007> A_IWL<4006> A_IWL<4005> A_IWL<4004> A_IWL<4003> A_IWL<4002> A_IWL<4001> A_IWL<4000> B_IWL<4015> B_IWL<4014> B_IWL<4013> B_IWL<4012> B_IWL<4011> B_IWL<4010> B_IWL<4009> B_IWL<4008> B_IWL<4007> B_IWL<4006> B_IWL<4005> B_IWL<4004> B_IWL<4003> B_IWL<4002> B_IWL<4001> B_IWL<4000> VDD_CORE VSS / RM_IHPSG13_1024x16_c2_2P_BITKIT_16x2_EDGE_LR +XRAMEDGE_R<9> A_IWL<3999> A_IWL<3998> A_IWL<3997> A_IWL<3996> A_IWL<3995> A_IWL<3994> A_IWL<3993> A_IWL<3992> A_IWL<3991> A_IWL<3990> A_IWL<3989> A_IWL<3988> A_IWL<3987> A_IWL<3986> A_IWL<3985> A_IWL<3984> B_IWL<3999> B_IWL<3998> B_IWL<3997> B_IWL<3996> B_IWL<3995> B_IWL<3994> B_IWL<3993> B_IWL<3992> B_IWL<3991> B_IWL<3990> B_IWL<3989> B_IWL<3988> B_IWL<3987> B_IWL<3986> B_IWL<3985> B_IWL<3984> VDD_CORE VSS / RM_IHPSG13_1024x16_c2_2P_BITKIT_16x2_EDGE_LR +XRAMEDGE_R<8> A_IWL<3983> A_IWL<3982> A_IWL<3981> A_IWL<3980> A_IWL<3979> A_IWL<3978> A_IWL<3977> A_IWL<3976> A_IWL<3975> A_IWL<3974> A_IWL<3973> A_IWL<3972> A_IWL<3971> A_IWL<3970> A_IWL<3969> A_IWL<3968> B_IWL<3983> B_IWL<3982> B_IWL<3981> B_IWL<3980> B_IWL<3979> B_IWL<3978> B_IWL<3977> B_IWL<3976> B_IWL<3975> B_IWL<3974> B_IWL<3973> B_IWL<3972> B_IWL<3971> B_IWL<3970> B_IWL<3969> B_IWL<3968> VDD_CORE VSS / RM_IHPSG13_1024x16_c2_2P_BITKIT_16x2_EDGE_LR +XRAMEDGE_R<7> A_IWL<3967> A_IWL<3966> A_IWL<3965> A_IWL<3964> A_IWL<3963> A_IWL<3962> A_IWL<3961> A_IWL<3960> A_IWL<3959> A_IWL<3958> A_IWL<3957> A_IWL<3956> A_IWL<3955> A_IWL<3954> A_IWL<3953> A_IWL<3952> B_IWL<3967> B_IWL<3966> B_IWL<3965> B_IWL<3964> B_IWL<3963> B_IWL<3962> B_IWL<3961> B_IWL<3960> B_IWL<3959> B_IWL<3958> B_IWL<3957> B_IWL<3956> B_IWL<3955> B_IWL<3954> B_IWL<3953> B_IWL<3952> VDD_CORE VSS / RM_IHPSG13_1024x16_c2_2P_BITKIT_16x2_EDGE_LR +XRAMEDGE_R<6> A_IWL<3951> A_IWL<3950> A_IWL<3949> A_IWL<3948> A_IWL<3947> A_IWL<3946> A_IWL<3945> A_IWL<3944> A_IWL<3943> A_IWL<3942> A_IWL<3941> A_IWL<3940> A_IWL<3939> A_IWL<3938> A_IWL<3937> A_IWL<3936> B_IWL<3951> B_IWL<3950> B_IWL<3949> B_IWL<3948> B_IWL<3947> B_IWL<3946> B_IWL<3945> B_IWL<3944> B_IWL<3943> B_IWL<3942> B_IWL<3941> B_IWL<3940> B_IWL<3939> B_IWL<3938> B_IWL<3937> B_IWL<3936> VDD_CORE VSS / RM_IHPSG13_1024x16_c2_2P_BITKIT_16x2_EDGE_LR +XRAMEDGE_R<5> A_IWL<3935> A_IWL<3934> A_IWL<3933> A_IWL<3932> A_IWL<3931> A_IWL<3930> A_IWL<3929> A_IWL<3928> A_IWL<3927> A_IWL<3926> A_IWL<3925> A_IWL<3924> A_IWL<3923> A_IWL<3922> A_IWL<3921> A_IWL<3920> B_IWL<3935> B_IWL<3934> B_IWL<3933> B_IWL<3932> B_IWL<3931> B_IWL<3930> B_IWL<3929> B_IWL<3928> B_IWL<3927> B_IWL<3926> B_IWL<3925> B_IWL<3924> B_IWL<3923> B_IWL<3922> B_IWL<3921> B_IWL<3920> VDD_CORE VSS / RM_IHPSG13_1024x16_c2_2P_BITKIT_16x2_EDGE_LR +XRAMEDGE_R<4> A_IWL<3919> A_IWL<3918> A_IWL<3917> A_IWL<3916> A_IWL<3915> A_IWL<3914> A_IWL<3913> A_IWL<3912> A_IWL<3911> A_IWL<3910> A_IWL<3909> A_IWL<3908> A_IWL<3907> A_IWL<3906> A_IWL<3905> A_IWL<3904> B_IWL<3919> B_IWL<3918> B_IWL<3917> B_IWL<3916> B_IWL<3915> B_IWL<3914> B_IWL<3913> B_IWL<3912> B_IWL<3911> B_IWL<3910> B_IWL<3909> B_IWL<3908> B_IWL<3907> B_IWL<3906> B_IWL<3905> B_IWL<3904> VDD_CORE VSS / RM_IHPSG13_1024x16_c2_2P_BITKIT_16x2_EDGE_LR +XRAMEDGE_R<3> A_IWL<3903> A_IWL<3902> A_IWL<3901> A_IWL<3900> A_IWL<3899> A_IWL<3898> A_IWL<3897> A_IWL<3896> A_IWL<3895> A_IWL<3894> A_IWL<3893> A_IWL<3892> A_IWL<3891> A_IWL<3890> A_IWL<3889> A_IWL<3888> B_IWL<3903> B_IWL<3902> B_IWL<3901> B_IWL<3900> B_IWL<3899> B_IWL<3898> B_IWL<3897> B_IWL<3896> B_IWL<3895> B_IWL<3894> B_IWL<3893> B_IWL<3892> B_IWL<3891> B_IWL<3890> B_IWL<3889> B_IWL<3888> VDD_CORE VSS / RM_IHPSG13_1024x16_c2_2P_BITKIT_16x2_EDGE_LR +XRAMEDGE_R<2> A_IWL<3887> A_IWL<3886> A_IWL<3885> A_IWL<3884> A_IWL<3883> A_IWL<3882> A_IWL<3881> A_IWL<3880> A_IWL<3879> A_IWL<3878> A_IWL<3877> A_IWL<3876> A_IWL<3875> A_IWL<3874> A_IWL<3873> A_IWL<3872> B_IWL<3887> B_IWL<3886> B_IWL<3885> B_IWL<3884> B_IWL<3883> B_IWL<3882> B_IWL<3881> B_IWL<3880> B_IWL<3879> B_IWL<3878> B_IWL<3877> B_IWL<3876> B_IWL<3875> B_IWL<3874> B_IWL<3873> B_IWL<3872> VDD_CORE VSS / RM_IHPSG13_1024x16_c2_2P_BITKIT_16x2_EDGE_LR +XRAMEDGE_R<1> A_IWL<3871> A_IWL<3870> A_IWL<3869> A_IWL<3868> A_IWL<3867> A_IWL<3866> A_IWL<3865> A_IWL<3864> A_IWL<3863> A_IWL<3862> A_IWL<3861> A_IWL<3860> A_IWL<3859> A_IWL<3858> A_IWL<3857> A_IWL<3856> B_IWL<3871> B_IWL<3870> B_IWL<3869> B_IWL<3868> B_IWL<3867> B_IWL<3866> B_IWL<3865> B_IWL<3864> B_IWL<3863> B_IWL<3862> B_IWL<3861> B_IWL<3860> B_IWL<3859> B_IWL<3858> B_IWL<3857> B_IWL<3856> VDD_CORE VSS / RM_IHPSG13_1024x16_c2_2P_BITKIT_16x2_EDGE_LR +XRAMEDGE_R<0> A_IWL<3855> A_IWL<3854> A_IWL<3853> A_IWL<3852> A_IWL<3851> A_IWL<3850> A_IWL<3849> A_IWL<3848> A_IWL<3847> A_IWL<3846> A_IWL<3845> A_IWL<3844> A_IWL<3843> A_IWL<3842> A_IWL<3841> A_IWL<3840> B_IWL<3855> B_IWL<3854> B_IWL<3853> B_IWL<3852> B_IWL<3851> B_IWL<3850> B_IWL<3849> B_IWL<3848> B_IWL<3847> B_IWL<3846> B_IWL<3845> B_IWL<3844> B_IWL<3843> B_IWL<3842> B_IWL<3841> B_IWL<3840> VDD_CORE VSS / RM_IHPSG13_1024x16_c2_2P_BITKIT_16x2_EDGE_LR +XCOL<15> A_BLC<31> A_BLC<30> A_BLC_TOP<31> A_BLC_TOP<30> A_BLT<31> A_BLT<30> A_BLT_TOP<31> A_BLT_TOP<30> A_IWL<3839> A_IWL<3838> A_IWL<3837> A_IWL<3836> A_IWL<3835> A_IWL<3834> A_IWL<3833> A_IWL<3832> A_IWL<3831> A_IWL<3830> A_IWL<3829> A_IWL<3828> A_IWL<3827> A_IWL<3826> A_IWL<3825> A_IWL<3824> A_IWL<3823> A_IWL<3822> A_IWL<3821> A_IWL<3820> A_IWL<3819> A_IWL<3818> A_IWL<3817> A_IWL<3816> A_IWL<3815> A_IWL<3814> A_IWL<3813> A_IWL<3812> A_IWL<3811> A_IWL<3810> A_IWL<3809> A_IWL<3808> A_IWL<3807> A_IWL<3806> A_IWL<3805> A_IWL<3804> A_IWL<3803> A_IWL<3802> A_IWL<3801> A_IWL<3800> A_IWL<3799> A_IWL<3798> A_IWL<3797> A_IWL<3796> A_IWL<3795> A_IWL<3794> A_IWL<3793> A_IWL<3792> A_IWL<3791> A_IWL<3790> A_IWL<3789> A_IWL<3788> A_IWL<3787> A_IWL<3786> A_IWL<3785> A_IWL<3784> A_IWL<3783> A_IWL<3782> A_IWL<3781> A_IWL<3780> A_IWL<3779> A_IWL<3778> A_IWL<3777> A_IWL<3776> A_IWL<3775> A_IWL<3774> A_IWL<3773> A_IWL<3772> A_IWL<3771> A_IWL<3770> A_IWL<3769> A_IWL<3768> A_IWL<3767> A_IWL<3766> A_IWL<3765> A_IWL<3764> A_IWL<3763> A_IWL<3762> A_IWL<3761> A_IWL<3760> A_IWL<3759> A_IWL<3758> A_IWL<3757> A_IWL<3756> A_IWL<3755> A_IWL<3754> A_IWL<3753> A_IWL<3752> A_IWL<3751> A_IWL<3750> A_IWL<3749> A_IWL<3748> A_IWL<3747> A_IWL<3746> A_IWL<3745> A_IWL<3744> A_IWL<3743> A_IWL<3742> A_IWL<3741> A_IWL<3740> A_IWL<3739> A_IWL<3738> A_IWL<3737> A_IWL<3736> A_IWL<3735> A_IWL<3734> A_IWL<3733> A_IWL<3732> A_IWL<3731> A_IWL<3730> A_IWL<3729> A_IWL<3728> A_IWL<3727> A_IWL<3726> A_IWL<3725> A_IWL<3724> A_IWL<3723> A_IWL<3722> A_IWL<3721> A_IWL<3720> A_IWL<3719> A_IWL<3718> A_IWL<3717> A_IWL<3716> A_IWL<3715> A_IWL<3714> A_IWL<3713> A_IWL<3712> A_IWL<3711> A_IWL<3710> A_IWL<3709> A_IWL<3708> A_IWL<3707> A_IWL<3706> A_IWL<3705> A_IWL<3704> A_IWL<3703> A_IWL<3702> A_IWL<3701> A_IWL<3700> A_IWL<3699> A_IWL<3698> A_IWL<3697> A_IWL<3696> A_IWL<3695> A_IWL<3694> A_IWL<3693> A_IWL<3692> A_IWL<3691> A_IWL<3690> A_IWL<3689> A_IWL<3688> A_IWL<3687> A_IWL<3686> A_IWL<3685> A_IWL<3684> A_IWL<3683> A_IWL<3682> A_IWL<3681> A_IWL<3680> A_IWL<3679> A_IWL<3678> A_IWL<3677> A_IWL<3676> A_IWL<3675> A_IWL<3674> A_IWL<3673> A_IWL<3672> A_IWL<3671> A_IWL<3670> A_IWL<3669> A_IWL<3668> A_IWL<3667> A_IWL<3666> A_IWL<3665> A_IWL<3664> A_IWL<3663> A_IWL<3662> A_IWL<3661> A_IWL<3660> A_IWL<3659> A_IWL<3658> A_IWL<3657> A_IWL<3656> A_IWL<3655> A_IWL<3654> A_IWL<3653> A_IWL<3652> A_IWL<3651> A_IWL<3650> A_IWL<3649> A_IWL<3648> A_IWL<3647> A_IWL<3646> A_IWL<3645> A_IWL<3644> A_IWL<3643> A_IWL<3642> A_IWL<3641> A_IWL<3640> A_IWL<3639> A_IWL<3638> A_IWL<3637> A_IWL<3636> A_IWL<3635> A_IWL<3634> A_IWL<3633> A_IWL<3632> A_IWL<3631> A_IWL<3630> A_IWL<3629> A_IWL<3628> A_IWL<3627> A_IWL<3626> A_IWL<3625> A_IWL<3624> A_IWL<3623> A_IWL<3622> A_IWL<3621> A_IWL<3620> A_IWL<3619> A_IWL<3618> A_IWL<3617> A_IWL<3616> A_IWL<3615> A_IWL<3614> A_IWL<3613> A_IWL<3612> A_IWL<3611> A_IWL<3610> A_IWL<3609> A_IWL<3608> A_IWL<3607> A_IWL<3606> A_IWL<3605> A_IWL<3604> A_IWL<3603> A_IWL<3602> A_IWL<3601> A_IWL<3600> A_IWL<3599> A_IWL<3598> A_IWL<3597> A_IWL<3596> A_IWL<3595> A_IWL<3594> A_IWL<3593> A_IWL<3592> A_IWL<3591> A_IWL<3590> A_IWL<3589> A_IWL<3588> A_IWL<3587> A_IWL<3586> A_IWL<3585> A_IWL<3584> A_IWL<4095> A_IWL<4094> A_IWL<4093> A_IWL<4092> A_IWL<4091> A_IWL<4090> A_IWL<4089> A_IWL<4088> A_IWL<4087> A_IWL<4086> A_IWL<4085> A_IWL<4084> A_IWL<4083> A_IWL<4082> A_IWL<4081> A_IWL<4080> A_IWL<4079> A_IWL<4078> A_IWL<4077> A_IWL<4076> A_IWL<4075> A_IWL<4074> A_IWL<4073> A_IWL<4072> A_IWL<4071> A_IWL<4070> A_IWL<4069> A_IWL<4068> A_IWL<4067> A_IWL<4066> A_IWL<4065> A_IWL<4064> A_IWL<4063> A_IWL<4062> A_IWL<4061> A_IWL<4060> A_IWL<4059> A_IWL<4058> A_IWL<4057> A_IWL<4056> A_IWL<4055> A_IWL<4054> A_IWL<4053> A_IWL<4052> A_IWL<4051> A_IWL<4050> A_IWL<4049> A_IWL<4048> A_IWL<4047> A_IWL<4046> A_IWL<4045> A_IWL<4044> A_IWL<4043> A_IWL<4042> A_IWL<4041> A_IWL<4040> A_IWL<4039> A_IWL<4038> A_IWL<4037> A_IWL<4036> A_IWL<4035> A_IWL<4034> A_IWL<4033> A_IWL<4032> A_IWL<4031> A_IWL<4030> A_IWL<4029> A_IWL<4028> A_IWL<4027> A_IWL<4026> A_IWL<4025> A_IWL<4024> A_IWL<4023> A_IWL<4022> A_IWL<4021> A_IWL<4020> A_IWL<4019> A_IWL<4018> A_IWL<4017> A_IWL<4016> A_IWL<4015> A_IWL<4014> A_IWL<4013> A_IWL<4012> A_IWL<4011> A_IWL<4010> A_IWL<4009> A_IWL<4008> A_IWL<4007> A_IWL<4006> A_IWL<4005> A_IWL<4004> A_IWL<4003> A_IWL<4002> A_IWL<4001> A_IWL<4000> A_IWL<3999> A_IWL<3998> A_IWL<3997> A_IWL<3996> A_IWL<3995> A_IWL<3994> A_IWL<3993> A_IWL<3992> A_IWL<3991> A_IWL<3990> A_IWL<3989> A_IWL<3988> A_IWL<3987> A_IWL<3986> A_IWL<3985> A_IWL<3984> A_IWL<3983> A_IWL<3982> A_IWL<3981> A_IWL<3980> A_IWL<3979> A_IWL<3978> A_IWL<3977> A_IWL<3976> A_IWL<3975> A_IWL<3974> A_IWL<3973> A_IWL<3972> A_IWL<3971> A_IWL<3970> A_IWL<3969> A_IWL<3968> A_IWL<3967> A_IWL<3966> A_IWL<3965> A_IWL<3964> A_IWL<3963> A_IWL<3962> A_IWL<3961> A_IWL<3960> A_IWL<3959> A_IWL<3958> A_IWL<3957> A_IWL<3956> A_IWL<3955> A_IWL<3954> A_IWL<3953> A_IWL<3952> A_IWL<3951> A_IWL<3950> A_IWL<3949> A_IWL<3948> A_IWL<3947> A_IWL<3946> A_IWL<3945> A_IWL<3944> A_IWL<3943> A_IWL<3942> A_IWL<3941> A_IWL<3940> A_IWL<3939> A_IWL<3938> A_IWL<3937> A_IWL<3936> A_IWL<3935> A_IWL<3934> A_IWL<3933> A_IWL<3932> A_IWL<3931> A_IWL<3930> A_IWL<3929> A_IWL<3928> A_IWL<3927> A_IWL<3926> A_IWL<3925> A_IWL<3924> A_IWL<3923> A_IWL<3922> A_IWL<3921> A_IWL<3920> A_IWL<3919> A_IWL<3918> A_IWL<3917> A_IWL<3916> A_IWL<3915> A_IWL<3914> A_IWL<3913> A_IWL<3912> A_IWL<3911> A_IWL<3910> A_IWL<3909> A_IWL<3908> A_IWL<3907> A_IWL<3906> A_IWL<3905> A_IWL<3904> A_IWL<3903> A_IWL<3902> A_IWL<3901> A_IWL<3900> A_IWL<3899> A_IWL<3898> A_IWL<3897> A_IWL<3896> A_IWL<3895> A_IWL<3894> A_IWL<3893> A_IWL<3892> A_IWL<3891> A_IWL<3890> A_IWL<3889> A_IWL<3888> A_IWL<3887> A_IWL<3886> A_IWL<3885> A_IWL<3884> A_IWL<3883> A_IWL<3882> A_IWL<3881> A_IWL<3880> A_IWL<3879> A_IWL<3878> A_IWL<3877> A_IWL<3876> A_IWL<3875> A_IWL<3874> A_IWL<3873> A_IWL<3872> A_IWL<3871> A_IWL<3870> A_IWL<3869> A_IWL<3868> A_IWL<3867> A_IWL<3866> A_IWL<3865> A_IWL<3864> A_IWL<3863> A_IWL<3862> A_IWL<3861> A_IWL<3860> A_IWL<3859> A_IWL<3858> A_IWL<3857> A_IWL<3856> A_IWL<3855> A_IWL<3854> A_IWL<3853> A_IWL<3852> A_IWL<3851> A_IWL<3850> A_IWL<3849> A_IWL<3848> A_IWL<3847> A_IWL<3846> A_IWL<3845> A_IWL<3844> A_IWL<3843> A_IWL<3842> A_IWL<3841> A_IWL<3840> B_BLC<31> B_BLC<30> B_BLC_TOP<31> B_BLC_TOP<30> B_BLT<31> B_BLT<30> B_BLT_TOP<31> B_BLT_TOP<30> B_IWL<3839> B_IWL<3838> B_IWL<3837> B_IWL<3836> B_IWL<3835> B_IWL<3834> B_IWL<3833> B_IWL<3832> B_IWL<3831> B_IWL<3830> B_IWL<3829> B_IWL<3828> B_IWL<3827> B_IWL<3826> B_IWL<3825> B_IWL<3824> B_IWL<3823> B_IWL<3822> B_IWL<3821> B_IWL<3820> B_IWL<3819> B_IWL<3818> B_IWL<3817> B_IWL<3816> B_IWL<3815> B_IWL<3814> B_IWL<3813> B_IWL<3812> B_IWL<3811> B_IWL<3810> B_IWL<3809> B_IWL<3808> B_IWL<3807> B_IWL<3806> B_IWL<3805> B_IWL<3804> B_IWL<3803> B_IWL<3802> B_IWL<3801> B_IWL<3800> B_IWL<3799> B_IWL<3798> B_IWL<3797> B_IWL<3796> B_IWL<3795> B_IWL<3794> B_IWL<3793> B_IWL<3792> B_IWL<3791> B_IWL<3790> B_IWL<3789> B_IWL<3788> B_IWL<3787> B_IWL<3786> B_IWL<3785> B_IWL<3784> B_IWL<3783> B_IWL<3782> B_IWL<3781> B_IWL<3780> B_IWL<3779> B_IWL<3778> B_IWL<3777> B_IWL<3776> B_IWL<3775> B_IWL<3774> B_IWL<3773> B_IWL<3772> B_IWL<3771> B_IWL<3770> B_IWL<3769> B_IWL<3768> B_IWL<3767> B_IWL<3766> B_IWL<3765> B_IWL<3764> B_IWL<3763> B_IWL<3762> B_IWL<3761> B_IWL<3760> B_IWL<3759> B_IWL<3758> B_IWL<3757> B_IWL<3756> B_IWL<3755> B_IWL<3754> B_IWL<3753> B_IWL<3752> B_IWL<3751> B_IWL<3750> B_IWL<3749> B_IWL<3748> B_IWL<3747> B_IWL<3746> B_IWL<3745> B_IWL<3744> B_IWL<3743> B_IWL<3742> B_IWL<3741> B_IWL<3740> B_IWL<3739> B_IWL<3738> B_IWL<3737> B_IWL<3736> B_IWL<3735> B_IWL<3734> B_IWL<3733> B_IWL<3732> B_IWL<3731> B_IWL<3730> B_IWL<3729> B_IWL<3728> B_IWL<3727> B_IWL<3726> B_IWL<3725> B_IWL<3724> B_IWL<3723> B_IWL<3722> B_IWL<3721> B_IWL<3720> B_IWL<3719> B_IWL<3718> B_IWL<3717> B_IWL<3716> B_IWL<3715> B_IWL<3714> B_IWL<3713> B_IWL<3712> B_IWL<3711> B_IWL<3710> B_IWL<3709> B_IWL<3708> B_IWL<3707> B_IWL<3706> B_IWL<3705> B_IWL<3704> B_IWL<3703> B_IWL<3702> B_IWL<3701> B_IWL<3700> B_IWL<3699> B_IWL<3698> B_IWL<3697> B_IWL<3696> B_IWL<3695> B_IWL<3694> B_IWL<3693> B_IWL<3692> B_IWL<3691> B_IWL<3690> B_IWL<3689> B_IWL<3688> B_IWL<3687> B_IWL<3686> B_IWL<3685> B_IWL<3684> B_IWL<3683> B_IWL<3682> B_IWL<3681> B_IWL<3680> B_IWL<3679> B_IWL<3678> B_IWL<3677> B_IWL<3676> B_IWL<3675> B_IWL<3674> B_IWL<3673> B_IWL<3672> B_IWL<3671> B_IWL<3670> B_IWL<3669> B_IWL<3668> B_IWL<3667> B_IWL<3666> B_IWL<3665> B_IWL<3664> B_IWL<3663> B_IWL<3662> B_IWL<3661> B_IWL<3660> B_IWL<3659> B_IWL<3658> B_IWL<3657> B_IWL<3656> B_IWL<3655> B_IWL<3654> B_IWL<3653> B_IWL<3652> B_IWL<3651> B_IWL<3650> B_IWL<3649> B_IWL<3648> B_IWL<3647> B_IWL<3646> B_IWL<3645> B_IWL<3644> B_IWL<3643> B_IWL<3642> B_IWL<3641> B_IWL<3640> B_IWL<3639> B_IWL<3638> B_IWL<3637> B_IWL<3636> B_IWL<3635> B_IWL<3634> B_IWL<3633> B_IWL<3632> B_IWL<3631> B_IWL<3630> B_IWL<3629> B_IWL<3628> B_IWL<3627> B_IWL<3626> B_IWL<3625> B_IWL<3624> B_IWL<3623> B_IWL<3622> B_IWL<3621> B_IWL<3620> B_IWL<3619> B_IWL<3618> B_IWL<3617> B_IWL<3616> B_IWL<3615> B_IWL<3614> B_IWL<3613> B_IWL<3612> B_IWL<3611> B_IWL<3610> B_IWL<3609> B_IWL<3608> B_IWL<3607> B_IWL<3606> B_IWL<3605> B_IWL<3604> B_IWL<3603> B_IWL<3602> B_IWL<3601> B_IWL<3600> B_IWL<3599> B_IWL<3598> B_IWL<3597> B_IWL<3596> B_IWL<3595> B_IWL<3594> B_IWL<3593> B_IWL<3592> B_IWL<3591> B_IWL<3590> B_IWL<3589> B_IWL<3588> B_IWL<3587> B_IWL<3586> B_IWL<3585> B_IWL<3584> B_IWL<4095> B_IWL<4094> B_IWL<4093> B_IWL<4092> B_IWL<4091> B_IWL<4090> B_IWL<4089> B_IWL<4088> B_IWL<4087> B_IWL<4086> B_IWL<4085> B_IWL<4084> B_IWL<4083> B_IWL<4082> B_IWL<4081> B_IWL<4080> B_IWL<4079> B_IWL<4078> B_IWL<4077> B_IWL<4076> B_IWL<4075> B_IWL<4074> B_IWL<4073> B_IWL<4072> B_IWL<4071> B_IWL<4070> B_IWL<4069> B_IWL<4068> B_IWL<4067> B_IWL<4066> B_IWL<4065> B_IWL<4064> B_IWL<4063> B_IWL<4062> B_IWL<4061> B_IWL<4060> B_IWL<4059> B_IWL<4058> B_IWL<4057> B_IWL<4056> B_IWL<4055> B_IWL<4054> B_IWL<4053> B_IWL<4052> B_IWL<4051> B_IWL<4050> B_IWL<4049> B_IWL<4048> B_IWL<4047> B_IWL<4046> B_IWL<4045> B_IWL<4044> B_IWL<4043> B_IWL<4042> B_IWL<4041> B_IWL<4040> B_IWL<4039> B_IWL<4038> B_IWL<4037> B_IWL<4036> B_IWL<4035> B_IWL<4034> B_IWL<4033> B_IWL<4032> B_IWL<4031> B_IWL<4030> B_IWL<4029> B_IWL<4028> B_IWL<4027> B_IWL<4026> B_IWL<4025> B_IWL<4024> B_IWL<4023> B_IWL<4022> B_IWL<4021> B_IWL<4020> B_IWL<4019> B_IWL<4018> B_IWL<4017> B_IWL<4016> B_IWL<4015> B_IWL<4014> B_IWL<4013> B_IWL<4012> B_IWL<4011> B_IWL<4010> B_IWL<4009> B_IWL<4008> B_IWL<4007> B_IWL<4006> B_IWL<4005> B_IWL<4004> B_IWL<4003> B_IWL<4002> B_IWL<4001> B_IWL<4000> B_IWL<3999> B_IWL<3998> B_IWL<3997> B_IWL<3996> B_IWL<3995> B_IWL<3994> B_IWL<3993> B_IWL<3992> B_IWL<3991> B_IWL<3990> B_IWL<3989> B_IWL<3988> B_IWL<3987> B_IWL<3986> B_IWL<3985> B_IWL<3984> B_IWL<3983> B_IWL<3982> B_IWL<3981> B_IWL<3980> B_IWL<3979> B_IWL<3978> B_IWL<3977> B_IWL<3976> B_IWL<3975> B_IWL<3974> B_IWL<3973> B_IWL<3972> B_IWL<3971> B_IWL<3970> B_IWL<3969> B_IWL<3968> B_IWL<3967> B_IWL<3966> B_IWL<3965> B_IWL<3964> B_IWL<3963> B_IWL<3962> B_IWL<3961> B_IWL<3960> B_IWL<3959> B_IWL<3958> B_IWL<3957> B_IWL<3956> B_IWL<3955> B_IWL<3954> B_IWL<3953> B_IWL<3952> B_IWL<3951> B_IWL<3950> B_IWL<3949> B_IWL<3948> B_IWL<3947> B_IWL<3946> B_IWL<3945> B_IWL<3944> B_IWL<3943> B_IWL<3942> B_IWL<3941> B_IWL<3940> B_IWL<3939> B_IWL<3938> B_IWL<3937> B_IWL<3936> B_IWL<3935> B_IWL<3934> B_IWL<3933> B_IWL<3932> B_IWL<3931> B_IWL<3930> B_IWL<3929> B_IWL<3928> B_IWL<3927> B_IWL<3926> B_IWL<3925> B_IWL<3924> B_IWL<3923> B_IWL<3922> B_IWL<3921> B_IWL<3920> B_IWL<3919> B_IWL<3918> B_IWL<3917> B_IWL<3916> B_IWL<3915> B_IWL<3914> B_IWL<3913> B_IWL<3912> B_IWL<3911> B_IWL<3910> B_IWL<3909> B_IWL<3908> B_IWL<3907> B_IWL<3906> B_IWL<3905> B_IWL<3904> B_IWL<3903> B_IWL<3902> B_IWL<3901> B_IWL<3900> B_IWL<3899> B_IWL<3898> B_IWL<3897> B_IWL<3896> B_IWL<3895> B_IWL<3894> B_IWL<3893> B_IWL<3892> B_IWL<3891> B_IWL<3890> B_IWL<3889> B_IWL<3888> B_IWL<3887> B_IWL<3886> B_IWL<3885> B_IWL<3884> B_IWL<3883> B_IWL<3882> B_IWL<3881> B_IWL<3880> B_IWL<3879> B_IWL<3878> B_IWL<3877> B_IWL<3876> B_IWL<3875> B_IWL<3874> B_IWL<3873> B_IWL<3872> B_IWL<3871> B_IWL<3870> B_IWL<3869> B_IWL<3868> B_IWL<3867> B_IWL<3866> B_IWL<3865> B_IWL<3864> B_IWL<3863> B_IWL<3862> B_IWL<3861> B_IWL<3860> B_IWL<3859> B_IWL<3858> B_IWL<3857> B_IWL<3856> B_IWL<3855> B_IWL<3854> B_IWL<3853> B_IWL<3852> B_IWL<3851> B_IWL<3850> B_IWL<3849> B_IWL<3848> B_IWL<3847> B_IWL<3846> B_IWL<3845> B_IWL<3844> B_IWL<3843> B_IWL<3842> B_IWL<3841> B_IWL<3840> VDD_CORE VSS / RM_IHPSG13_1024x16_c2_2P_COLUMN_pcell_0 +XCOL<14> A_BLC<29> A_BLC<28> A_BLC_TOP<29> A_BLC_TOP<28> A_BLT<29> A_BLT<28> A_BLT_TOP<29> A_BLT_TOP<28> A_IWL<3583> A_IWL<3582> A_IWL<3581> A_IWL<3580> A_IWL<3579> A_IWL<3578> A_IWL<3577> A_IWL<3576> A_IWL<3575> A_IWL<3574> A_IWL<3573> A_IWL<3572> A_IWL<3571> A_IWL<3570> A_IWL<3569> A_IWL<3568> A_IWL<3567> A_IWL<3566> A_IWL<3565> A_IWL<3564> A_IWL<3563> A_IWL<3562> A_IWL<3561> A_IWL<3560> A_IWL<3559> A_IWL<3558> A_IWL<3557> A_IWL<3556> A_IWL<3555> A_IWL<3554> A_IWL<3553> A_IWL<3552> A_IWL<3551> A_IWL<3550> A_IWL<3549> A_IWL<3548> A_IWL<3547> A_IWL<3546> A_IWL<3545> A_IWL<3544> A_IWL<3543> A_IWL<3542> A_IWL<3541> A_IWL<3540> A_IWL<3539> A_IWL<3538> A_IWL<3537> A_IWL<3536> A_IWL<3535> A_IWL<3534> A_IWL<3533> A_IWL<3532> A_IWL<3531> A_IWL<3530> A_IWL<3529> A_IWL<3528> A_IWL<3527> A_IWL<3526> A_IWL<3525> A_IWL<3524> A_IWL<3523> A_IWL<3522> A_IWL<3521> A_IWL<3520> A_IWL<3519> A_IWL<3518> A_IWL<3517> A_IWL<3516> A_IWL<3515> A_IWL<3514> A_IWL<3513> A_IWL<3512> A_IWL<3511> A_IWL<3510> A_IWL<3509> A_IWL<3508> A_IWL<3507> A_IWL<3506> A_IWL<3505> A_IWL<3504> A_IWL<3503> A_IWL<3502> A_IWL<3501> A_IWL<3500> A_IWL<3499> A_IWL<3498> A_IWL<3497> A_IWL<3496> A_IWL<3495> A_IWL<3494> A_IWL<3493> A_IWL<3492> A_IWL<3491> A_IWL<3490> A_IWL<3489> A_IWL<3488> A_IWL<3487> A_IWL<3486> A_IWL<3485> A_IWL<3484> A_IWL<3483> A_IWL<3482> A_IWL<3481> A_IWL<3480> A_IWL<3479> A_IWL<3478> A_IWL<3477> A_IWL<3476> A_IWL<3475> A_IWL<3474> A_IWL<3473> A_IWL<3472> A_IWL<3471> A_IWL<3470> A_IWL<3469> A_IWL<3468> A_IWL<3467> A_IWL<3466> A_IWL<3465> A_IWL<3464> A_IWL<3463> A_IWL<3462> A_IWL<3461> A_IWL<3460> A_IWL<3459> A_IWL<3458> A_IWL<3457> A_IWL<3456> A_IWL<3455> A_IWL<3454> A_IWL<3453> A_IWL<3452> A_IWL<3451> A_IWL<3450> A_IWL<3449> A_IWL<3448> A_IWL<3447> A_IWL<3446> A_IWL<3445> A_IWL<3444> A_IWL<3443> A_IWL<3442> A_IWL<3441> A_IWL<3440> A_IWL<3439> A_IWL<3438> A_IWL<3437> A_IWL<3436> A_IWL<3435> A_IWL<3434> A_IWL<3433> A_IWL<3432> A_IWL<3431> A_IWL<3430> A_IWL<3429> A_IWL<3428> A_IWL<3427> A_IWL<3426> A_IWL<3425> A_IWL<3424> A_IWL<3423> A_IWL<3422> A_IWL<3421> A_IWL<3420> A_IWL<3419> A_IWL<3418> A_IWL<3417> A_IWL<3416> A_IWL<3415> A_IWL<3414> A_IWL<3413> A_IWL<3412> A_IWL<3411> A_IWL<3410> A_IWL<3409> A_IWL<3408> A_IWL<3407> A_IWL<3406> A_IWL<3405> A_IWL<3404> A_IWL<3403> A_IWL<3402> A_IWL<3401> A_IWL<3400> A_IWL<3399> A_IWL<3398> A_IWL<3397> A_IWL<3396> A_IWL<3395> A_IWL<3394> A_IWL<3393> A_IWL<3392> A_IWL<3391> A_IWL<3390> A_IWL<3389> A_IWL<3388> A_IWL<3387> A_IWL<3386> A_IWL<3385> A_IWL<3384> A_IWL<3383> A_IWL<3382> A_IWL<3381> A_IWL<3380> A_IWL<3379> A_IWL<3378> A_IWL<3377> A_IWL<3376> A_IWL<3375> A_IWL<3374> A_IWL<3373> A_IWL<3372> A_IWL<3371> A_IWL<3370> A_IWL<3369> A_IWL<3368> A_IWL<3367> A_IWL<3366> A_IWL<3365> A_IWL<3364> A_IWL<3363> A_IWL<3362> A_IWL<3361> A_IWL<3360> A_IWL<3359> A_IWL<3358> A_IWL<3357> A_IWL<3356> A_IWL<3355> A_IWL<3354> A_IWL<3353> A_IWL<3352> A_IWL<3351> A_IWL<3350> A_IWL<3349> A_IWL<3348> A_IWL<3347> A_IWL<3346> A_IWL<3345> A_IWL<3344> A_IWL<3343> A_IWL<3342> A_IWL<3341> A_IWL<3340> A_IWL<3339> A_IWL<3338> A_IWL<3337> A_IWL<3336> A_IWL<3335> A_IWL<3334> A_IWL<3333> A_IWL<3332> A_IWL<3331> A_IWL<3330> A_IWL<3329> A_IWL<3328> A_IWL<3839> A_IWL<3838> A_IWL<3837> A_IWL<3836> A_IWL<3835> A_IWL<3834> A_IWL<3833> A_IWL<3832> A_IWL<3831> A_IWL<3830> A_IWL<3829> A_IWL<3828> A_IWL<3827> A_IWL<3826> A_IWL<3825> A_IWL<3824> A_IWL<3823> A_IWL<3822> A_IWL<3821> A_IWL<3820> A_IWL<3819> A_IWL<3818> A_IWL<3817> A_IWL<3816> A_IWL<3815> A_IWL<3814> A_IWL<3813> A_IWL<3812> A_IWL<3811> A_IWL<3810> A_IWL<3809> A_IWL<3808> A_IWL<3807> A_IWL<3806> A_IWL<3805> A_IWL<3804> A_IWL<3803> A_IWL<3802> A_IWL<3801> A_IWL<3800> A_IWL<3799> A_IWL<3798> A_IWL<3797> A_IWL<3796> A_IWL<3795> A_IWL<3794> A_IWL<3793> A_IWL<3792> A_IWL<3791> A_IWL<3790> A_IWL<3789> A_IWL<3788> A_IWL<3787> A_IWL<3786> A_IWL<3785> A_IWL<3784> A_IWL<3783> A_IWL<3782> A_IWL<3781> A_IWL<3780> A_IWL<3779> A_IWL<3778> A_IWL<3777> A_IWL<3776> A_IWL<3775> A_IWL<3774> A_IWL<3773> A_IWL<3772> A_IWL<3771> A_IWL<3770> A_IWL<3769> A_IWL<3768> A_IWL<3767> A_IWL<3766> A_IWL<3765> A_IWL<3764> A_IWL<3763> A_IWL<3762> A_IWL<3761> A_IWL<3760> A_IWL<3759> A_IWL<3758> A_IWL<3757> A_IWL<3756> A_IWL<3755> A_IWL<3754> A_IWL<3753> A_IWL<3752> A_IWL<3751> A_IWL<3750> A_IWL<3749> A_IWL<3748> A_IWL<3747> A_IWL<3746> A_IWL<3745> A_IWL<3744> A_IWL<3743> A_IWL<3742> A_IWL<3741> A_IWL<3740> A_IWL<3739> A_IWL<3738> A_IWL<3737> A_IWL<3736> A_IWL<3735> A_IWL<3734> A_IWL<3733> A_IWL<3732> A_IWL<3731> A_IWL<3730> A_IWL<3729> A_IWL<3728> A_IWL<3727> A_IWL<3726> A_IWL<3725> A_IWL<3724> A_IWL<3723> A_IWL<3722> A_IWL<3721> A_IWL<3720> A_IWL<3719> A_IWL<3718> A_IWL<3717> A_IWL<3716> A_IWL<3715> A_IWL<3714> A_IWL<3713> A_IWL<3712> A_IWL<3711> A_IWL<3710> A_IWL<3709> A_IWL<3708> A_IWL<3707> A_IWL<3706> A_IWL<3705> A_IWL<3704> A_IWL<3703> A_IWL<3702> A_IWL<3701> A_IWL<3700> A_IWL<3699> A_IWL<3698> A_IWL<3697> A_IWL<3696> A_IWL<3695> A_IWL<3694> A_IWL<3693> A_IWL<3692> A_IWL<3691> A_IWL<3690> A_IWL<3689> A_IWL<3688> A_IWL<3687> A_IWL<3686> A_IWL<3685> A_IWL<3684> A_IWL<3683> A_IWL<3682> A_IWL<3681> A_IWL<3680> A_IWL<3679> A_IWL<3678> A_IWL<3677> A_IWL<3676> A_IWL<3675> A_IWL<3674> A_IWL<3673> A_IWL<3672> A_IWL<3671> A_IWL<3670> A_IWL<3669> A_IWL<3668> A_IWL<3667> A_IWL<3666> A_IWL<3665> A_IWL<3664> A_IWL<3663> A_IWL<3662> A_IWL<3661> A_IWL<3660> A_IWL<3659> A_IWL<3658> A_IWL<3657> A_IWL<3656> A_IWL<3655> A_IWL<3654> A_IWL<3653> A_IWL<3652> A_IWL<3651> A_IWL<3650> A_IWL<3649> A_IWL<3648> A_IWL<3647> A_IWL<3646> A_IWL<3645> A_IWL<3644> A_IWL<3643> A_IWL<3642> A_IWL<3641> A_IWL<3640> A_IWL<3639> A_IWL<3638> A_IWL<3637> A_IWL<3636> A_IWL<3635> A_IWL<3634> A_IWL<3633> A_IWL<3632> A_IWL<3631> A_IWL<3630> A_IWL<3629> A_IWL<3628> A_IWL<3627> A_IWL<3626> A_IWL<3625> A_IWL<3624> A_IWL<3623> A_IWL<3622> A_IWL<3621> A_IWL<3620> A_IWL<3619> A_IWL<3618> A_IWL<3617> A_IWL<3616> A_IWL<3615> A_IWL<3614> A_IWL<3613> A_IWL<3612> A_IWL<3611> A_IWL<3610> A_IWL<3609> A_IWL<3608> A_IWL<3607> A_IWL<3606> A_IWL<3605> A_IWL<3604> A_IWL<3603> A_IWL<3602> A_IWL<3601> A_IWL<3600> A_IWL<3599> A_IWL<3598> A_IWL<3597> A_IWL<3596> A_IWL<3595> A_IWL<3594> A_IWL<3593> A_IWL<3592> A_IWL<3591> A_IWL<3590> A_IWL<3589> A_IWL<3588> A_IWL<3587> A_IWL<3586> A_IWL<3585> A_IWL<3584> B_BLC<29> B_BLC<28> B_BLC_TOP<29> B_BLC_TOP<28> B_BLT<29> B_BLT<28> B_BLT_TOP<29> B_BLT_TOP<28> B_IWL<3583> B_IWL<3582> B_IWL<3581> B_IWL<3580> B_IWL<3579> B_IWL<3578> B_IWL<3577> B_IWL<3576> B_IWL<3575> B_IWL<3574> B_IWL<3573> B_IWL<3572> B_IWL<3571> B_IWL<3570> B_IWL<3569> B_IWL<3568> B_IWL<3567> B_IWL<3566> B_IWL<3565> B_IWL<3564> B_IWL<3563> B_IWL<3562> B_IWL<3561> B_IWL<3560> B_IWL<3559> B_IWL<3558> B_IWL<3557> B_IWL<3556> B_IWL<3555> B_IWL<3554> B_IWL<3553> B_IWL<3552> B_IWL<3551> B_IWL<3550> B_IWL<3549> B_IWL<3548> B_IWL<3547> B_IWL<3546> B_IWL<3545> B_IWL<3544> B_IWL<3543> B_IWL<3542> B_IWL<3541> B_IWL<3540> B_IWL<3539> B_IWL<3538> B_IWL<3537> B_IWL<3536> B_IWL<3535> B_IWL<3534> B_IWL<3533> B_IWL<3532> B_IWL<3531> B_IWL<3530> B_IWL<3529> B_IWL<3528> B_IWL<3527> B_IWL<3526> B_IWL<3525> B_IWL<3524> B_IWL<3523> B_IWL<3522> B_IWL<3521> B_IWL<3520> B_IWL<3519> B_IWL<3518> B_IWL<3517> B_IWL<3516> B_IWL<3515> B_IWL<3514> B_IWL<3513> B_IWL<3512> B_IWL<3511> B_IWL<3510> B_IWL<3509> B_IWL<3508> B_IWL<3507> B_IWL<3506> B_IWL<3505> B_IWL<3504> B_IWL<3503> B_IWL<3502> B_IWL<3501> B_IWL<3500> B_IWL<3499> B_IWL<3498> B_IWL<3497> B_IWL<3496> B_IWL<3495> B_IWL<3494> B_IWL<3493> B_IWL<3492> B_IWL<3491> B_IWL<3490> B_IWL<3489> B_IWL<3488> B_IWL<3487> B_IWL<3486> B_IWL<3485> B_IWL<3484> B_IWL<3483> B_IWL<3482> B_IWL<3481> B_IWL<3480> B_IWL<3479> B_IWL<3478> B_IWL<3477> B_IWL<3476> B_IWL<3475> B_IWL<3474> B_IWL<3473> B_IWL<3472> B_IWL<3471> B_IWL<3470> B_IWL<3469> B_IWL<3468> B_IWL<3467> B_IWL<3466> B_IWL<3465> B_IWL<3464> B_IWL<3463> B_IWL<3462> B_IWL<3461> B_IWL<3460> B_IWL<3459> B_IWL<3458> B_IWL<3457> B_IWL<3456> B_IWL<3455> B_IWL<3454> B_IWL<3453> B_IWL<3452> B_IWL<3451> B_IWL<3450> B_IWL<3449> B_IWL<3448> B_IWL<3447> B_IWL<3446> B_IWL<3445> B_IWL<3444> B_IWL<3443> B_IWL<3442> B_IWL<3441> B_IWL<3440> B_IWL<3439> B_IWL<3438> B_IWL<3437> B_IWL<3436> B_IWL<3435> B_IWL<3434> B_IWL<3433> B_IWL<3432> B_IWL<3431> B_IWL<3430> B_IWL<3429> B_IWL<3428> B_IWL<3427> B_IWL<3426> B_IWL<3425> B_IWL<3424> B_IWL<3423> B_IWL<3422> B_IWL<3421> B_IWL<3420> B_IWL<3419> B_IWL<3418> B_IWL<3417> B_IWL<3416> B_IWL<3415> B_IWL<3414> B_IWL<3413> B_IWL<3412> B_IWL<3411> B_IWL<3410> B_IWL<3409> B_IWL<3408> B_IWL<3407> B_IWL<3406> B_IWL<3405> B_IWL<3404> B_IWL<3403> B_IWL<3402> B_IWL<3401> B_IWL<3400> B_IWL<3399> B_IWL<3398> B_IWL<3397> B_IWL<3396> B_IWL<3395> B_IWL<3394> B_IWL<3393> B_IWL<3392> B_IWL<3391> B_IWL<3390> B_IWL<3389> B_IWL<3388> B_IWL<3387> B_IWL<3386> B_IWL<3385> B_IWL<3384> B_IWL<3383> B_IWL<3382> B_IWL<3381> B_IWL<3380> B_IWL<3379> B_IWL<3378> B_IWL<3377> B_IWL<3376> B_IWL<3375> B_IWL<3374> B_IWL<3373> B_IWL<3372> B_IWL<3371> B_IWL<3370> B_IWL<3369> B_IWL<3368> B_IWL<3367> B_IWL<3366> B_IWL<3365> B_IWL<3364> B_IWL<3363> B_IWL<3362> B_IWL<3361> B_IWL<3360> B_IWL<3359> B_IWL<3358> B_IWL<3357> B_IWL<3356> B_IWL<3355> B_IWL<3354> B_IWL<3353> B_IWL<3352> B_IWL<3351> B_IWL<3350> B_IWL<3349> B_IWL<3348> B_IWL<3347> B_IWL<3346> B_IWL<3345> B_IWL<3344> B_IWL<3343> B_IWL<3342> B_IWL<3341> B_IWL<3340> B_IWL<3339> B_IWL<3338> B_IWL<3337> B_IWL<3336> B_IWL<3335> B_IWL<3334> B_IWL<3333> B_IWL<3332> B_IWL<3331> B_IWL<3330> B_IWL<3329> B_IWL<3328> B_IWL<3839> B_IWL<3838> B_IWL<3837> B_IWL<3836> B_IWL<3835> B_IWL<3834> B_IWL<3833> B_IWL<3832> B_IWL<3831> B_IWL<3830> B_IWL<3829> B_IWL<3828> B_IWL<3827> B_IWL<3826> B_IWL<3825> B_IWL<3824> B_IWL<3823> B_IWL<3822> B_IWL<3821> B_IWL<3820> B_IWL<3819> B_IWL<3818> B_IWL<3817> B_IWL<3816> B_IWL<3815> B_IWL<3814> B_IWL<3813> B_IWL<3812> B_IWL<3811> B_IWL<3810> B_IWL<3809> B_IWL<3808> B_IWL<3807> B_IWL<3806> B_IWL<3805> B_IWL<3804> B_IWL<3803> B_IWL<3802> B_IWL<3801> B_IWL<3800> B_IWL<3799> B_IWL<3798> B_IWL<3797> B_IWL<3796> B_IWL<3795> B_IWL<3794> B_IWL<3793> B_IWL<3792> B_IWL<3791> B_IWL<3790> B_IWL<3789> B_IWL<3788> B_IWL<3787> B_IWL<3786> B_IWL<3785> B_IWL<3784> B_IWL<3783> B_IWL<3782> B_IWL<3781> B_IWL<3780> B_IWL<3779> B_IWL<3778> B_IWL<3777> B_IWL<3776> B_IWL<3775> B_IWL<3774> B_IWL<3773> B_IWL<3772> B_IWL<3771> B_IWL<3770> B_IWL<3769> B_IWL<3768> B_IWL<3767> B_IWL<3766> B_IWL<3765> B_IWL<3764> B_IWL<3763> B_IWL<3762> B_IWL<3761> B_IWL<3760> B_IWL<3759> B_IWL<3758> B_IWL<3757> B_IWL<3756> B_IWL<3755> B_IWL<3754> B_IWL<3753> B_IWL<3752> B_IWL<3751> B_IWL<3750> B_IWL<3749> B_IWL<3748> B_IWL<3747> B_IWL<3746> B_IWL<3745> B_IWL<3744> B_IWL<3743> B_IWL<3742> B_IWL<3741> B_IWL<3740> B_IWL<3739> B_IWL<3738> B_IWL<3737> B_IWL<3736> B_IWL<3735> B_IWL<3734> B_IWL<3733> B_IWL<3732> B_IWL<3731> B_IWL<3730> B_IWL<3729> B_IWL<3728> B_IWL<3727> B_IWL<3726> B_IWL<3725> B_IWL<3724> B_IWL<3723> B_IWL<3722> B_IWL<3721> B_IWL<3720> B_IWL<3719> B_IWL<3718> B_IWL<3717> B_IWL<3716> B_IWL<3715> B_IWL<3714> B_IWL<3713> B_IWL<3712> B_IWL<3711> B_IWL<3710> B_IWL<3709> B_IWL<3708> B_IWL<3707> B_IWL<3706> B_IWL<3705> B_IWL<3704> B_IWL<3703> B_IWL<3702> B_IWL<3701> B_IWL<3700> B_IWL<3699> B_IWL<3698> B_IWL<3697> B_IWL<3696> B_IWL<3695> B_IWL<3694> B_IWL<3693> B_IWL<3692> B_IWL<3691> B_IWL<3690> B_IWL<3689> B_IWL<3688> B_IWL<3687> B_IWL<3686> B_IWL<3685> B_IWL<3684> B_IWL<3683> B_IWL<3682> B_IWL<3681> B_IWL<3680> B_IWL<3679> B_IWL<3678> B_IWL<3677> B_IWL<3676> B_IWL<3675> B_IWL<3674> B_IWL<3673> B_IWL<3672> B_IWL<3671> B_IWL<3670> B_IWL<3669> B_IWL<3668> B_IWL<3667> B_IWL<3666> B_IWL<3665> B_IWL<3664> B_IWL<3663> B_IWL<3662> B_IWL<3661> B_IWL<3660> B_IWL<3659> B_IWL<3658> B_IWL<3657> B_IWL<3656> B_IWL<3655> B_IWL<3654> B_IWL<3653> B_IWL<3652> B_IWL<3651> B_IWL<3650> B_IWL<3649> B_IWL<3648> B_IWL<3647> B_IWL<3646> B_IWL<3645> B_IWL<3644> B_IWL<3643> B_IWL<3642> B_IWL<3641> B_IWL<3640> B_IWL<3639> B_IWL<3638> B_IWL<3637> B_IWL<3636> B_IWL<3635> B_IWL<3634> B_IWL<3633> B_IWL<3632> B_IWL<3631> B_IWL<3630> B_IWL<3629> B_IWL<3628> B_IWL<3627> B_IWL<3626> B_IWL<3625> B_IWL<3624> B_IWL<3623> B_IWL<3622> B_IWL<3621> B_IWL<3620> B_IWL<3619> B_IWL<3618> B_IWL<3617> B_IWL<3616> B_IWL<3615> B_IWL<3614> B_IWL<3613> B_IWL<3612> B_IWL<3611> B_IWL<3610> B_IWL<3609> B_IWL<3608> B_IWL<3607> B_IWL<3606> B_IWL<3605> B_IWL<3604> B_IWL<3603> B_IWL<3602> B_IWL<3601> B_IWL<3600> B_IWL<3599> B_IWL<3598> B_IWL<3597> B_IWL<3596> B_IWL<3595> B_IWL<3594> B_IWL<3593> B_IWL<3592> B_IWL<3591> B_IWL<3590> B_IWL<3589> B_IWL<3588> B_IWL<3587> B_IWL<3586> B_IWL<3585> B_IWL<3584> VDD_CORE VSS / RM_IHPSG13_1024x16_c2_2P_COLUMN_pcell_0 +XCOL<13> A_BLC<27> A_BLC<26> A_BLC_TOP<27> A_BLC_TOP<26> A_BLT<27> A_BLT<26> A_BLT_TOP<27> A_BLT_TOP<26> A_IWL<3327> A_IWL<3326> A_IWL<3325> A_IWL<3324> A_IWL<3323> A_IWL<3322> A_IWL<3321> A_IWL<3320> A_IWL<3319> A_IWL<3318> A_IWL<3317> A_IWL<3316> A_IWL<3315> A_IWL<3314> A_IWL<3313> A_IWL<3312> A_IWL<3311> A_IWL<3310> A_IWL<3309> A_IWL<3308> A_IWL<3307> A_IWL<3306> A_IWL<3305> A_IWL<3304> A_IWL<3303> A_IWL<3302> A_IWL<3301> A_IWL<3300> A_IWL<3299> A_IWL<3298> A_IWL<3297> A_IWL<3296> A_IWL<3295> A_IWL<3294> A_IWL<3293> A_IWL<3292> A_IWL<3291> A_IWL<3290> A_IWL<3289> A_IWL<3288> A_IWL<3287> A_IWL<3286> A_IWL<3285> A_IWL<3284> A_IWL<3283> A_IWL<3282> A_IWL<3281> A_IWL<3280> A_IWL<3279> A_IWL<3278> A_IWL<3277> A_IWL<3276> A_IWL<3275> A_IWL<3274> A_IWL<3273> A_IWL<3272> A_IWL<3271> A_IWL<3270> A_IWL<3269> A_IWL<3268> A_IWL<3267> A_IWL<3266> A_IWL<3265> A_IWL<3264> A_IWL<3263> A_IWL<3262> A_IWL<3261> A_IWL<3260> A_IWL<3259> A_IWL<3258> A_IWL<3257> A_IWL<3256> A_IWL<3255> A_IWL<3254> A_IWL<3253> A_IWL<3252> A_IWL<3251> A_IWL<3250> A_IWL<3249> A_IWL<3248> A_IWL<3247> A_IWL<3246> A_IWL<3245> A_IWL<3244> A_IWL<3243> A_IWL<3242> A_IWL<3241> A_IWL<3240> A_IWL<3239> A_IWL<3238> A_IWL<3237> A_IWL<3236> A_IWL<3235> A_IWL<3234> A_IWL<3233> A_IWL<3232> A_IWL<3231> A_IWL<3230> A_IWL<3229> A_IWL<3228> A_IWL<3227> A_IWL<3226> A_IWL<3225> A_IWL<3224> A_IWL<3223> A_IWL<3222> A_IWL<3221> A_IWL<3220> A_IWL<3219> A_IWL<3218> A_IWL<3217> A_IWL<3216> A_IWL<3215> A_IWL<3214> A_IWL<3213> A_IWL<3212> A_IWL<3211> A_IWL<3210> A_IWL<3209> A_IWL<3208> A_IWL<3207> A_IWL<3206> A_IWL<3205> A_IWL<3204> A_IWL<3203> A_IWL<3202> A_IWL<3201> A_IWL<3200> A_IWL<3199> A_IWL<3198> A_IWL<3197> A_IWL<3196> A_IWL<3195> A_IWL<3194> A_IWL<3193> A_IWL<3192> A_IWL<3191> A_IWL<3190> A_IWL<3189> A_IWL<3188> A_IWL<3187> A_IWL<3186> A_IWL<3185> A_IWL<3184> A_IWL<3183> A_IWL<3182> A_IWL<3181> A_IWL<3180> A_IWL<3179> A_IWL<3178> A_IWL<3177> A_IWL<3176> A_IWL<3175> A_IWL<3174> A_IWL<3173> A_IWL<3172> A_IWL<3171> A_IWL<3170> A_IWL<3169> A_IWL<3168> A_IWL<3167> A_IWL<3166> A_IWL<3165> A_IWL<3164> A_IWL<3163> A_IWL<3162> A_IWL<3161> A_IWL<3160> A_IWL<3159> A_IWL<3158> A_IWL<3157> A_IWL<3156> A_IWL<3155> A_IWL<3154> A_IWL<3153> A_IWL<3152> A_IWL<3151> A_IWL<3150> A_IWL<3149> A_IWL<3148> A_IWL<3147> A_IWL<3146> A_IWL<3145> A_IWL<3144> A_IWL<3143> A_IWL<3142> A_IWL<3141> A_IWL<3140> A_IWL<3139> A_IWL<3138> A_IWL<3137> A_IWL<3136> A_IWL<3135> A_IWL<3134> A_IWL<3133> A_IWL<3132> A_IWL<3131> A_IWL<3130> A_IWL<3129> A_IWL<3128> A_IWL<3127> A_IWL<3126> A_IWL<3125> A_IWL<3124> A_IWL<3123> A_IWL<3122> A_IWL<3121> A_IWL<3120> A_IWL<3119> A_IWL<3118> A_IWL<3117> A_IWL<3116> A_IWL<3115> A_IWL<3114> A_IWL<3113> A_IWL<3112> A_IWL<3111> A_IWL<3110> A_IWL<3109> A_IWL<3108> A_IWL<3107> A_IWL<3106> A_IWL<3105> A_IWL<3104> A_IWL<3103> A_IWL<3102> A_IWL<3101> A_IWL<3100> A_IWL<3099> A_IWL<3098> A_IWL<3097> A_IWL<3096> A_IWL<3095> A_IWL<3094> A_IWL<3093> A_IWL<3092> A_IWL<3091> A_IWL<3090> A_IWL<3089> A_IWL<3088> A_IWL<3087> A_IWL<3086> A_IWL<3085> A_IWL<3084> A_IWL<3083> A_IWL<3082> A_IWL<3081> A_IWL<3080> A_IWL<3079> A_IWL<3078> A_IWL<3077> A_IWL<3076> A_IWL<3075> A_IWL<3074> A_IWL<3073> A_IWL<3072> A_IWL<3583> A_IWL<3582> A_IWL<3581> A_IWL<3580> A_IWL<3579> A_IWL<3578> A_IWL<3577> A_IWL<3576> A_IWL<3575> A_IWL<3574> A_IWL<3573> A_IWL<3572> A_IWL<3571> A_IWL<3570> A_IWL<3569> A_IWL<3568> A_IWL<3567> A_IWL<3566> A_IWL<3565> A_IWL<3564> A_IWL<3563> A_IWL<3562> A_IWL<3561> A_IWL<3560> A_IWL<3559> A_IWL<3558> A_IWL<3557> A_IWL<3556> A_IWL<3555> A_IWL<3554> A_IWL<3553> A_IWL<3552> A_IWL<3551> A_IWL<3550> A_IWL<3549> A_IWL<3548> A_IWL<3547> A_IWL<3546> A_IWL<3545> A_IWL<3544> A_IWL<3543> A_IWL<3542> A_IWL<3541> A_IWL<3540> A_IWL<3539> A_IWL<3538> A_IWL<3537> A_IWL<3536> A_IWL<3535> A_IWL<3534> A_IWL<3533> A_IWL<3532> A_IWL<3531> A_IWL<3530> A_IWL<3529> A_IWL<3528> A_IWL<3527> A_IWL<3526> A_IWL<3525> A_IWL<3524> A_IWL<3523> A_IWL<3522> A_IWL<3521> A_IWL<3520> A_IWL<3519> A_IWL<3518> A_IWL<3517> A_IWL<3516> A_IWL<3515> A_IWL<3514> A_IWL<3513> A_IWL<3512> A_IWL<3511> A_IWL<3510> A_IWL<3509> A_IWL<3508> A_IWL<3507> A_IWL<3506> A_IWL<3505> A_IWL<3504> A_IWL<3503> A_IWL<3502> A_IWL<3501> A_IWL<3500> A_IWL<3499> A_IWL<3498> A_IWL<3497> A_IWL<3496> A_IWL<3495> A_IWL<3494> A_IWL<3493> A_IWL<3492> A_IWL<3491> A_IWL<3490> A_IWL<3489> A_IWL<3488> A_IWL<3487> A_IWL<3486> A_IWL<3485> A_IWL<3484> A_IWL<3483> A_IWL<3482> A_IWL<3481> A_IWL<3480> A_IWL<3479> A_IWL<3478> A_IWL<3477> A_IWL<3476> A_IWL<3475> A_IWL<3474> A_IWL<3473> A_IWL<3472> A_IWL<3471> A_IWL<3470> A_IWL<3469> A_IWL<3468> A_IWL<3467> A_IWL<3466> A_IWL<3465> A_IWL<3464> A_IWL<3463> A_IWL<3462> A_IWL<3461> A_IWL<3460> A_IWL<3459> A_IWL<3458> A_IWL<3457> A_IWL<3456> A_IWL<3455> A_IWL<3454> A_IWL<3453> A_IWL<3452> A_IWL<3451> A_IWL<3450> A_IWL<3449> A_IWL<3448> A_IWL<3447> A_IWL<3446> A_IWL<3445> A_IWL<3444> A_IWL<3443> A_IWL<3442> A_IWL<3441> A_IWL<3440> A_IWL<3439> A_IWL<3438> A_IWL<3437> A_IWL<3436> A_IWL<3435> A_IWL<3434> A_IWL<3433> A_IWL<3432> A_IWL<3431> A_IWL<3430> A_IWL<3429> A_IWL<3428> A_IWL<3427> A_IWL<3426> A_IWL<3425> A_IWL<3424> A_IWL<3423> A_IWL<3422> A_IWL<3421> A_IWL<3420> A_IWL<3419> A_IWL<3418> A_IWL<3417> A_IWL<3416> A_IWL<3415> A_IWL<3414> A_IWL<3413> A_IWL<3412> A_IWL<3411> A_IWL<3410> A_IWL<3409> A_IWL<3408> A_IWL<3407> A_IWL<3406> A_IWL<3405> A_IWL<3404> A_IWL<3403> A_IWL<3402> A_IWL<3401> A_IWL<3400> A_IWL<3399> A_IWL<3398> A_IWL<3397> A_IWL<3396> A_IWL<3395> A_IWL<3394> A_IWL<3393> A_IWL<3392> A_IWL<3391> A_IWL<3390> A_IWL<3389> A_IWL<3388> A_IWL<3387> A_IWL<3386> A_IWL<3385> A_IWL<3384> A_IWL<3383> A_IWL<3382> A_IWL<3381> A_IWL<3380> A_IWL<3379> A_IWL<3378> A_IWL<3377> A_IWL<3376> A_IWL<3375> A_IWL<3374> A_IWL<3373> A_IWL<3372> A_IWL<3371> A_IWL<3370> A_IWL<3369> A_IWL<3368> A_IWL<3367> A_IWL<3366> A_IWL<3365> A_IWL<3364> A_IWL<3363> A_IWL<3362> A_IWL<3361> A_IWL<3360> A_IWL<3359> A_IWL<3358> A_IWL<3357> A_IWL<3356> A_IWL<3355> A_IWL<3354> A_IWL<3353> A_IWL<3352> A_IWL<3351> A_IWL<3350> A_IWL<3349> A_IWL<3348> A_IWL<3347> A_IWL<3346> A_IWL<3345> A_IWL<3344> A_IWL<3343> A_IWL<3342> A_IWL<3341> A_IWL<3340> A_IWL<3339> A_IWL<3338> A_IWL<3337> A_IWL<3336> A_IWL<3335> A_IWL<3334> A_IWL<3333> A_IWL<3332> A_IWL<3331> A_IWL<3330> A_IWL<3329> A_IWL<3328> B_BLC<27> B_BLC<26> B_BLC_TOP<27> B_BLC_TOP<26> B_BLT<27> B_BLT<26> B_BLT_TOP<27> B_BLT_TOP<26> B_IWL<3327> B_IWL<3326> B_IWL<3325> B_IWL<3324> B_IWL<3323> B_IWL<3322> B_IWL<3321> B_IWL<3320> B_IWL<3319> B_IWL<3318> B_IWL<3317> B_IWL<3316> B_IWL<3315> B_IWL<3314> B_IWL<3313> B_IWL<3312> B_IWL<3311> B_IWL<3310> B_IWL<3309> B_IWL<3308> B_IWL<3307> B_IWL<3306> B_IWL<3305> B_IWL<3304> B_IWL<3303> B_IWL<3302> B_IWL<3301> B_IWL<3300> B_IWL<3299> B_IWL<3298> B_IWL<3297> B_IWL<3296> B_IWL<3295> B_IWL<3294> B_IWL<3293> B_IWL<3292> B_IWL<3291> B_IWL<3290> B_IWL<3289> B_IWL<3288> B_IWL<3287> B_IWL<3286> B_IWL<3285> B_IWL<3284> B_IWL<3283> B_IWL<3282> B_IWL<3281> B_IWL<3280> B_IWL<3279> B_IWL<3278> B_IWL<3277> B_IWL<3276> B_IWL<3275> B_IWL<3274> B_IWL<3273> B_IWL<3272> B_IWL<3271> B_IWL<3270> B_IWL<3269> B_IWL<3268> B_IWL<3267> B_IWL<3266> B_IWL<3265> B_IWL<3264> B_IWL<3263> B_IWL<3262> B_IWL<3261> B_IWL<3260> B_IWL<3259> B_IWL<3258> B_IWL<3257> B_IWL<3256> B_IWL<3255> B_IWL<3254> B_IWL<3253> B_IWL<3252> B_IWL<3251> B_IWL<3250> B_IWL<3249> B_IWL<3248> B_IWL<3247> B_IWL<3246> B_IWL<3245> B_IWL<3244> B_IWL<3243> B_IWL<3242> B_IWL<3241> B_IWL<3240> B_IWL<3239> B_IWL<3238> B_IWL<3237> B_IWL<3236> B_IWL<3235> B_IWL<3234> B_IWL<3233> B_IWL<3232> B_IWL<3231> B_IWL<3230> B_IWL<3229> B_IWL<3228> B_IWL<3227> B_IWL<3226> B_IWL<3225> B_IWL<3224> B_IWL<3223> B_IWL<3222> B_IWL<3221> B_IWL<3220> B_IWL<3219> B_IWL<3218> B_IWL<3217> B_IWL<3216> B_IWL<3215> B_IWL<3214> B_IWL<3213> B_IWL<3212> B_IWL<3211> B_IWL<3210> B_IWL<3209> B_IWL<3208> B_IWL<3207> B_IWL<3206> B_IWL<3205> B_IWL<3204> B_IWL<3203> B_IWL<3202> B_IWL<3201> B_IWL<3200> B_IWL<3199> B_IWL<3198> B_IWL<3197> B_IWL<3196> B_IWL<3195> B_IWL<3194> B_IWL<3193> B_IWL<3192> B_IWL<3191> B_IWL<3190> B_IWL<3189> B_IWL<3188> B_IWL<3187> B_IWL<3186> B_IWL<3185> B_IWL<3184> B_IWL<3183> B_IWL<3182> B_IWL<3181> B_IWL<3180> B_IWL<3179> B_IWL<3178> B_IWL<3177> B_IWL<3176> B_IWL<3175> B_IWL<3174> B_IWL<3173> B_IWL<3172> B_IWL<3171> B_IWL<3170> B_IWL<3169> B_IWL<3168> B_IWL<3167> B_IWL<3166> B_IWL<3165> B_IWL<3164> B_IWL<3163> B_IWL<3162> B_IWL<3161> B_IWL<3160> B_IWL<3159> B_IWL<3158> B_IWL<3157> B_IWL<3156> B_IWL<3155> B_IWL<3154> B_IWL<3153> B_IWL<3152> B_IWL<3151> B_IWL<3150> B_IWL<3149> B_IWL<3148> B_IWL<3147> B_IWL<3146> B_IWL<3145> B_IWL<3144> B_IWL<3143> B_IWL<3142> B_IWL<3141> B_IWL<3140> B_IWL<3139> B_IWL<3138> B_IWL<3137> B_IWL<3136> B_IWL<3135> B_IWL<3134> B_IWL<3133> B_IWL<3132> B_IWL<3131> B_IWL<3130> B_IWL<3129> B_IWL<3128> B_IWL<3127> B_IWL<3126> B_IWL<3125> B_IWL<3124> B_IWL<3123> B_IWL<3122> B_IWL<3121> B_IWL<3120> B_IWL<3119> B_IWL<3118> B_IWL<3117> B_IWL<3116> B_IWL<3115> B_IWL<3114> B_IWL<3113> B_IWL<3112> B_IWL<3111> B_IWL<3110> B_IWL<3109> B_IWL<3108> B_IWL<3107> B_IWL<3106> B_IWL<3105> B_IWL<3104> B_IWL<3103> B_IWL<3102> B_IWL<3101> B_IWL<3100> B_IWL<3099> B_IWL<3098> B_IWL<3097> B_IWL<3096> B_IWL<3095> B_IWL<3094> B_IWL<3093> B_IWL<3092> B_IWL<3091> B_IWL<3090> B_IWL<3089> B_IWL<3088> B_IWL<3087> B_IWL<3086> B_IWL<3085> B_IWL<3084> B_IWL<3083> B_IWL<3082> B_IWL<3081> B_IWL<3080> B_IWL<3079> B_IWL<3078> B_IWL<3077> B_IWL<3076> B_IWL<3075> B_IWL<3074> B_IWL<3073> B_IWL<3072> B_IWL<3583> B_IWL<3582> B_IWL<3581> B_IWL<3580> B_IWL<3579> B_IWL<3578> B_IWL<3577> B_IWL<3576> B_IWL<3575> B_IWL<3574> B_IWL<3573> B_IWL<3572> B_IWL<3571> B_IWL<3570> B_IWL<3569> B_IWL<3568> B_IWL<3567> B_IWL<3566> B_IWL<3565> B_IWL<3564> B_IWL<3563> B_IWL<3562> B_IWL<3561> B_IWL<3560> B_IWL<3559> B_IWL<3558> B_IWL<3557> B_IWL<3556> B_IWL<3555> B_IWL<3554> B_IWL<3553> B_IWL<3552> B_IWL<3551> B_IWL<3550> B_IWL<3549> B_IWL<3548> B_IWL<3547> B_IWL<3546> B_IWL<3545> B_IWL<3544> B_IWL<3543> B_IWL<3542> B_IWL<3541> B_IWL<3540> B_IWL<3539> B_IWL<3538> B_IWL<3537> B_IWL<3536> B_IWL<3535> B_IWL<3534> B_IWL<3533> B_IWL<3532> B_IWL<3531> B_IWL<3530> B_IWL<3529> B_IWL<3528> B_IWL<3527> B_IWL<3526> B_IWL<3525> B_IWL<3524> B_IWL<3523> B_IWL<3522> B_IWL<3521> B_IWL<3520> B_IWL<3519> B_IWL<3518> B_IWL<3517> B_IWL<3516> B_IWL<3515> B_IWL<3514> B_IWL<3513> B_IWL<3512> B_IWL<3511> B_IWL<3510> B_IWL<3509> B_IWL<3508> B_IWL<3507> B_IWL<3506> B_IWL<3505> B_IWL<3504> B_IWL<3503> B_IWL<3502> B_IWL<3501> B_IWL<3500> B_IWL<3499> B_IWL<3498> B_IWL<3497> B_IWL<3496> B_IWL<3495> B_IWL<3494> B_IWL<3493> B_IWL<3492> B_IWL<3491> B_IWL<3490> B_IWL<3489> B_IWL<3488> B_IWL<3487> B_IWL<3486> B_IWL<3485> B_IWL<3484> B_IWL<3483> B_IWL<3482> B_IWL<3481> B_IWL<3480> B_IWL<3479> B_IWL<3478> B_IWL<3477> B_IWL<3476> B_IWL<3475> B_IWL<3474> B_IWL<3473> B_IWL<3472> B_IWL<3471> B_IWL<3470> B_IWL<3469> B_IWL<3468> B_IWL<3467> B_IWL<3466> B_IWL<3465> B_IWL<3464> B_IWL<3463> B_IWL<3462> B_IWL<3461> B_IWL<3460> B_IWL<3459> B_IWL<3458> B_IWL<3457> B_IWL<3456> B_IWL<3455> B_IWL<3454> B_IWL<3453> B_IWL<3452> B_IWL<3451> B_IWL<3450> B_IWL<3449> B_IWL<3448> B_IWL<3447> B_IWL<3446> B_IWL<3445> B_IWL<3444> B_IWL<3443> B_IWL<3442> B_IWL<3441> B_IWL<3440> B_IWL<3439> B_IWL<3438> B_IWL<3437> B_IWL<3436> B_IWL<3435> B_IWL<3434> B_IWL<3433> B_IWL<3432> B_IWL<3431> B_IWL<3430> B_IWL<3429> B_IWL<3428> B_IWL<3427> B_IWL<3426> B_IWL<3425> B_IWL<3424> B_IWL<3423> B_IWL<3422> B_IWL<3421> B_IWL<3420> B_IWL<3419> B_IWL<3418> B_IWL<3417> B_IWL<3416> B_IWL<3415> B_IWL<3414> B_IWL<3413> B_IWL<3412> B_IWL<3411> B_IWL<3410> B_IWL<3409> B_IWL<3408> B_IWL<3407> B_IWL<3406> B_IWL<3405> B_IWL<3404> B_IWL<3403> B_IWL<3402> B_IWL<3401> B_IWL<3400> B_IWL<3399> B_IWL<3398> B_IWL<3397> B_IWL<3396> B_IWL<3395> B_IWL<3394> B_IWL<3393> B_IWL<3392> B_IWL<3391> B_IWL<3390> B_IWL<3389> B_IWL<3388> B_IWL<3387> B_IWL<3386> B_IWL<3385> B_IWL<3384> B_IWL<3383> B_IWL<3382> B_IWL<3381> B_IWL<3380> B_IWL<3379> B_IWL<3378> B_IWL<3377> B_IWL<3376> B_IWL<3375> B_IWL<3374> B_IWL<3373> B_IWL<3372> B_IWL<3371> B_IWL<3370> B_IWL<3369> B_IWL<3368> B_IWL<3367> B_IWL<3366> B_IWL<3365> B_IWL<3364> B_IWL<3363> B_IWL<3362> B_IWL<3361> B_IWL<3360> B_IWL<3359> B_IWL<3358> B_IWL<3357> B_IWL<3356> B_IWL<3355> B_IWL<3354> B_IWL<3353> B_IWL<3352> B_IWL<3351> B_IWL<3350> B_IWL<3349> B_IWL<3348> B_IWL<3347> B_IWL<3346> B_IWL<3345> B_IWL<3344> B_IWL<3343> B_IWL<3342> B_IWL<3341> B_IWL<3340> B_IWL<3339> B_IWL<3338> B_IWL<3337> B_IWL<3336> B_IWL<3335> B_IWL<3334> B_IWL<3333> B_IWL<3332> B_IWL<3331> B_IWL<3330> B_IWL<3329> B_IWL<3328> VDD_CORE VSS / RM_IHPSG13_1024x16_c2_2P_COLUMN_pcell_0 +XCOL<12> A_BLC<25> A_BLC<24> A_BLC_TOP<25> A_BLC_TOP<24> A_BLT<25> A_BLT<24> A_BLT_TOP<25> A_BLT_TOP<24> A_IWL<3071> A_IWL<3070> A_IWL<3069> A_IWL<3068> A_IWL<3067> A_IWL<3066> A_IWL<3065> A_IWL<3064> A_IWL<3063> A_IWL<3062> A_IWL<3061> A_IWL<3060> A_IWL<3059> A_IWL<3058> A_IWL<3057> A_IWL<3056> A_IWL<3055> A_IWL<3054> A_IWL<3053> A_IWL<3052> A_IWL<3051> A_IWL<3050> A_IWL<3049> A_IWL<3048> A_IWL<3047> A_IWL<3046> A_IWL<3045> A_IWL<3044> A_IWL<3043> A_IWL<3042> A_IWL<3041> A_IWL<3040> A_IWL<3039> A_IWL<3038> A_IWL<3037> A_IWL<3036> A_IWL<3035> A_IWL<3034> A_IWL<3033> A_IWL<3032> A_IWL<3031> A_IWL<3030> A_IWL<3029> A_IWL<3028> A_IWL<3027> A_IWL<3026> A_IWL<3025> A_IWL<3024> A_IWL<3023> A_IWL<3022> A_IWL<3021> A_IWL<3020> A_IWL<3019> A_IWL<3018> A_IWL<3017> A_IWL<3016> A_IWL<3015> A_IWL<3014> A_IWL<3013> A_IWL<3012> A_IWL<3011> A_IWL<3010> A_IWL<3009> A_IWL<3008> A_IWL<3007> A_IWL<3006> A_IWL<3005> A_IWL<3004> A_IWL<3003> A_IWL<3002> A_IWL<3001> A_IWL<3000> A_IWL<2999> A_IWL<2998> A_IWL<2997> A_IWL<2996> A_IWL<2995> A_IWL<2994> A_IWL<2993> A_IWL<2992> A_IWL<2991> A_IWL<2990> A_IWL<2989> A_IWL<2988> A_IWL<2987> A_IWL<2986> A_IWL<2985> A_IWL<2984> A_IWL<2983> A_IWL<2982> A_IWL<2981> A_IWL<2980> A_IWL<2979> A_IWL<2978> A_IWL<2977> A_IWL<2976> A_IWL<2975> A_IWL<2974> A_IWL<2973> A_IWL<2972> A_IWL<2971> A_IWL<2970> A_IWL<2969> A_IWL<2968> A_IWL<2967> A_IWL<2966> A_IWL<2965> A_IWL<2964> A_IWL<2963> A_IWL<2962> A_IWL<2961> A_IWL<2960> A_IWL<2959> A_IWL<2958> A_IWL<2957> A_IWL<2956> A_IWL<2955> A_IWL<2954> A_IWL<2953> A_IWL<2952> A_IWL<2951> A_IWL<2950> A_IWL<2949> A_IWL<2948> A_IWL<2947> A_IWL<2946> A_IWL<2945> A_IWL<2944> A_IWL<2943> A_IWL<2942> A_IWL<2941> A_IWL<2940> A_IWL<2939> A_IWL<2938> A_IWL<2937> A_IWL<2936> A_IWL<2935> A_IWL<2934> A_IWL<2933> A_IWL<2932> A_IWL<2931> A_IWL<2930> A_IWL<2929> A_IWL<2928> A_IWL<2927> A_IWL<2926> A_IWL<2925> A_IWL<2924> A_IWL<2923> A_IWL<2922> A_IWL<2921> A_IWL<2920> A_IWL<2919> A_IWL<2918> A_IWL<2917> A_IWL<2916> A_IWL<2915> A_IWL<2914> A_IWL<2913> A_IWL<2912> A_IWL<2911> A_IWL<2910> A_IWL<2909> A_IWL<2908> A_IWL<2907> A_IWL<2906> A_IWL<2905> A_IWL<2904> A_IWL<2903> A_IWL<2902> A_IWL<2901> A_IWL<2900> A_IWL<2899> A_IWL<2898> A_IWL<2897> A_IWL<2896> A_IWL<2895> A_IWL<2894> A_IWL<2893> A_IWL<2892> A_IWL<2891> A_IWL<2890> A_IWL<2889> A_IWL<2888> A_IWL<2887> A_IWL<2886> A_IWL<2885> A_IWL<2884> A_IWL<2883> A_IWL<2882> A_IWL<2881> A_IWL<2880> A_IWL<2879> A_IWL<2878> A_IWL<2877> A_IWL<2876> A_IWL<2875> A_IWL<2874> A_IWL<2873> A_IWL<2872> A_IWL<2871> A_IWL<2870> A_IWL<2869> A_IWL<2868> A_IWL<2867> A_IWL<2866> A_IWL<2865> A_IWL<2864> A_IWL<2863> A_IWL<2862> A_IWL<2861> A_IWL<2860> A_IWL<2859> A_IWL<2858> A_IWL<2857> A_IWL<2856> A_IWL<2855> A_IWL<2854> A_IWL<2853> A_IWL<2852> A_IWL<2851> A_IWL<2850> A_IWL<2849> A_IWL<2848> A_IWL<2847> A_IWL<2846> A_IWL<2845> A_IWL<2844> A_IWL<2843> A_IWL<2842> A_IWL<2841> A_IWL<2840> A_IWL<2839> A_IWL<2838> A_IWL<2837> A_IWL<2836> A_IWL<2835> A_IWL<2834> A_IWL<2833> A_IWL<2832> A_IWL<2831> A_IWL<2830> A_IWL<2829> A_IWL<2828> A_IWL<2827> A_IWL<2826> A_IWL<2825> A_IWL<2824> A_IWL<2823> A_IWL<2822> A_IWL<2821> A_IWL<2820> A_IWL<2819> A_IWL<2818> A_IWL<2817> A_IWL<2816> A_IWL<3327> A_IWL<3326> A_IWL<3325> A_IWL<3324> A_IWL<3323> A_IWL<3322> A_IWL<3321> A_IWL<3320> A_IWL<3319> A_IWL<3318> A_IWL<3317> A_IWL<3316> A_IWL<3315> A_IWL<3314> A_IWL<3313> A_IWL<3312> A_IWL<3311> A_IWL<3310> A_IWL<3309> A_IWL<3308> A_IWL<3307> A_IWL<3306> A_IWL<3305> A_IWL<3304> A_IWL<3303> A_IWL<3302> A_IWL<3301> A_IWL<3300> A_IWL<3299> A_IWL<3298> A_IWL<3297> A_IWL<3296> A_IWL<3295> A_IWL<3294> A_IWL<3293> A_IWL<3292> A_IWL<3291> A_IWL<3290> A_IWL<3289> A_IWL<3288> A_IWL<3287> A_IWL<3286> A_IWL<3285> A_IWL<3284> A_IWL<3283> A_IWL<3282> A_IWL<3281> A_IWL<3280> A_IWL<3279> A_IWL<3278> A_IWL<3277> A_IWL<3276> A_IWL<3275> A_IWL<3274> A_IWL<3273> A_IWL<3272> A_IWL<3271> A_IWL<3270> A_IWL<3269> A_IWL<3268> A_IWL<3267> A_IWL<3266> A_IWL<3265> A_IWL<3264> A_IWL<3263> A_IWL<3262> A_IWL<3261> A_IWL<3260> A_IWL<3259> A_IWL<3258> A_IWL<3257> A_IWL<3256> A_IWL<3255> A_IWL<3254> A_IWL<3253> A_IWL<3252> A_IWL<3251> A_IWL<3250> A_IWL<3249> A_IWL<3248> A_IWL<3247> A_IWL<3246> A_IWL<3245> A_IWL<3244> A_IWL<3243> A_IWL<3242> A_IWL<3241> A_IWL<3240> A_IWL<3239> A_IWL<3238> A_IWL<3237> A_IWL<3236> A_IWL<3235> A_IWL<3234> A_IWL<3233> A_IWL<3232> A_IWL<3231> A_IWL<3230> A_IWL<3229> A_IWL<3228> A_IWL<3227> A_IWL<3226> A_IWL<3225> A_IWL<3224> A_IWL<3223> A_IWL<3222> A_IWL<3221> A_IWL<3220> A_IWL<3219> A_IWL<3218> A_IWL<3217> A_IWL<3216> A_IWL<3215> A_IWL<3214> A_IWL<3213> A_IWL<3212> A_IWL<3211> A_IWL<3210> A_IWL<3209> A_IWL<3208> A_IWL<3207> A_IWL<3206> A_IWL<3205> A_IWL<3204> A_IWL<3203> A_IWL<3202> A_IWL<3201> A_IWL<3200> A_IWL<3199> A_IWL<3198> A_IWL<3197> A_IWL<3196> A_IWL<3195> A_IWL<3194> A_IWL<3193> A_IWL<3192> A_IWL<3191> A_IWL<3190> A_IWL<3189> A_IWL<3188> A_IWL<3187> A_IWL<3186> A_IWL<3185> A_IWL<3184> A_IWL<3183> A_IWL<3182> A_IWL<3181> A_IWL<3180> A_IWL<3179> A_IWL<3178> A_IWL<3177> A_IWL<3176> A_IWL<3175> A_IWL<3174> A_IWL<3173> A_IWL<3172> A_IWL<3171> A_IWL<3170> A_IWL<3169> A_IWL<3168> A_IWL<3167> A_IWL<3166> A_IWL<3165> A_IWL<3164> A_IWL<3163> A_IWL<3162> A_IWL<3161> A_IWL<3160> A_IWL<3159> A_IWL<3158> A_IWL<3157> A_IWL<3156> A_IWL<3155> A_IWL<3154> A_IWL<3153> A_IWL<3152> A_IWL<3151> A_IWL<3150> A_IWL<3149> A_IWL<3148> A_IWL<3147> A_IWL<3146> A_IWL<3145> A_IWL<3144> A_IWL<3143> A_IWL<3142> A_IWL<3141> A_IWL<3140> A_IWL<3139> A_IWL<3138> A_IWL<3137> A_IWL<3136> A_IWL<3135> A_IWL<3134> A_IWL<3133> A_IWL<3132> A_IWL<3131> A_IWL<3130> A_IWL<3129> A_IWL<3128> A_IWL<3127> A_IWL<3126> A_IWL<3125> A_IWL<3124> A_IWL<3123> A_IWL<3122> A_IWL<3121> A_IWL<3120> A_IWL<3119> A_IWL<3118> A_IWL<3117> A_IWL<3116> A_IWL<3115> A_IWL<3114> A_IWL<3113> A_IWL<3112> A_IWL<3111> A_IWL<3110> A_IWL<3109> A_IWL<3108> A_IWL<3107> A_IWL<3106> A_IWL<3105> A_IWL<3104> A_IWL<3103> A_IWL<3102> A_IWL<3101> A_IWL<3100> A_IWL<3099> A_IWL<3098> A_IWL<3097> A_IWL<3096> A_IWL<3095> A_IWL<3094> A_IWL<3093> A_IWL<3092> A_IWL<3091> A_IWL<3090> A_IWL<3089> A_IWL<3088> A_IWL<3087> A_IWL<3086> A_IWL<3085> A_IWL<3084> A_IWL<3083> A_IWL<3082> A_IWL<3081> A_IWL<3080> A_IWL<3079> A_IWL<3078> A_IWL<3077> A_IWL<3076> A_IWL<3075> A_IWL<3074> A_IWL<3073> A_IWL<3072> B_BLC<25> B_BLC<24> B_BLC_TOP<25> B_BLC_TOP<24> B_BLT<25> B_BLT<24> B_BLT_TOP<25> B_BLT_TOP<24> B_IWL<3071> B_IWL<3070> B_IWL<3069> B_IWL<3068> B_IWL<3067> B_IWL<3066> B_IWL<3065> B_IWL<3064> B_IWL<3063> B_IWL<3062> B_IWL<3061> B_IWL<3060> B_IWL<3059> B_IWL<3058> B_IWL<3057> B_IWL<3056> B_IWL<3055> B_IWL<3054> B_IWL<3053> B_IWL<3052> B_IWL<3051> B_IWL<3050> B_IWL<3049> B_IWL<3048> B_IWL<3047> B_IWL<3046> B_IWL<3045> B_IWL<3044> B_IWL<3043> B_IWL<3042> B_IWL<3041> B_IWL<3040> B_IWL<3039> B_IWL<3038> B_IWL<3037> B_IWL<3036> B_IWL<3035> B_IWL<3034> B_IWL<3033> B_IWL<3032> B_IWL<3031> B_IWL<3030> B_IWL<3029> B_IWL<3028> B_IWL<3027> B_IWL<3026> B_IWL<3025> B_IWL<3024> B_IWL<3023> B_IWL<3022> B_IWL<3021> B_IWL<3020> B_IWL<3019> B_IWL<3018> B_IWL<3017> B_IWL<3016> B_IWL<3015> B_IWL<3014> B_IWL<3013> B_IWL<3012> B_IWL<3011> B_IWL<3010> B_IWL<3009> B_IWL<3008> B_IWL<3007> B_IWL<3006> B_IWL<3005> B_IWL<3004> B_IWL<3003> B_IWL<3002> B_IWL<3001> B_IWL<3000> B_IWL<2999> B_IWL<2998> B_IWL<2997> B_IWL<2996> B_IWL<2995> B_IWL<2994> B_IWL<2993> B_IWL<2992> B_IWL<2991> B_IWL<2990> B_IWL<2989> B_IWL<2988> B_IWL<2987> B_IWL<2986> B_IWL<2985> B_IWL<2984> B_IWL<2983> B_IWL<2982> B_IWL<2981> B_IWL<2980> B_IWL<2979> B_IWL<2978> B_IWL<2977> B_IWL<2976> B_IWL<2975> B_IWL<2974> B_IWL<2973> B_IWL<2972> B_IWL<2971> B_IWL<2970> B_IWL<2969> B_IWL<2968> B_IWL<2967> B_IWL<2966> B_IWL<2965> B_IWL<2964> B_IWL<2963> B_IWL<2962> B_IWL<2961> B_IWL<2960> B_IWL<2959> B_IWL<2958> B_IWL<2957> B_IWL<2956> B_IWL<2955> B_IWL<2954> B_IWL<2953> B_IWL<2952> B_IWL<2951> B_IWL<2950> B_IWL<2949> B_IWL<2948> B_IWL<2947> B_IWL<2946> B_IWL<2945> B_IWL<2944> B_IWL<2943> B_IWL<2942> B_IWL<2941> B_IWL<2940> B_IWL<2939> B_IWL<2938> B_IWL<2937> B_IWL<2936> B_IWL<2935> B_IWL<2934> B_IWL<2933> B_IWL<2932> B_IWL<2931> B_IWL<2930> B_IWL<2929> B_IWL<2928> B_IWL<2927> B_IWL<2926> B_IWL<2925> B_IWL<2924> B_IWL<2923> B_IWL<2922> B_IWL<2921> B_IWL<2920> B_IWL<2919> B_IWL<2918> B_IWL<2917> B_IWL<2916> B_IWL<2915> B_IWL<2914> B_IWL<2913> B_IWL<2912> B_IWL<2911> B_IWL<2910> B_IWL<2909> B_IWL<2908> B_IWL<2907> B_IWL<2906> B_IWL<2905> B_IWL<2904> B_IWL<2903> B_IWL<2902> B_IWL<2901> B_IWL<2900> B_IWL<2899> B_IWL<2898> B_IWL<2897> B_IWL<2896> B_IWL<2895> B_IWL<2894> B_IWL<2893> B_IWL<2892> B_IWL<2891> B_IWL<2890> B_IWL<2889> B_IWL<2888> B_IWL<2887> B_IWL<2886> B_IWL<2885> B_IWL<2884> B_IWL<2883> B_IWL<2882> B_IWL<2881> B_IWL<2880> B_IWL<2879> B_IWL<2878> B_IWL<2877> B_IWL<2876> B_IWL<2875> B_IWL<2874> B_IWL<2873> B_IWL<2872> B_IWL<2871> B_IWL<2870> B_IWL<2869> B_IWL<2868> B_IWL<2867> B_IWL<2866> B_IWL<2865> B_IWL<2864> B_IWL<2863> B_IWL<2862> B_IWL<2861> B_IWL<2860> B_IWL<2859> B_IWL<2858> B_IWL<2857> B_IWL<2856> B_IWL<2855> B_IWL<2854> B_IWL<2853> B_IWL<2852> B_IWL<2851> B_IWL<2850> B_IWL<2849> B_IWL<2848> B_IWL<2847> B_IWL<2846> B_IWL<2845> B_IWL<2844> B_IWL<2843> B_IWL<2842> B_IWL<2841> B_IWL<2840> B_IWL<2839> B_IWL<2838> B_IWL<2837> B_IWL<2836> B_IWL<2835> B_IWL<2834> B_IWL<2833> B_IWL<2832> B_IWL<2831> B_IWL<2830> B_IWL<2829> B_IWL<2828> B_IWL<2827> B_IWL<2826> B_IWL<2825> B_IWL<2824> B_IWL<2823> B_IWL<2822> B_IWL<2821> B_IWL<2820> B_IWL<2819> B_IWL<2818> B_IWL<2817> B_IWL<2816> B_IWL<3327> B_IWL<3326> B_IWL<3325> B_IWL<3324> B_IWL<3323> B_IWL<3322> B_IWL<3321> B_IWL<3320> B_IWL<3319> B_IWL<3318> B_IWL<3317> B_IWL<3316> B_IWL<3315> B_IWL<3314> B_IWL<3313> B_IWL<3312> B_IWL<3311> B_IWL<3310> B_IWL<3309> B_IWL<3308> B_IWL<3307> B_IWL<3306> B_IWL<3305> B_IWL<3304> B_IWL<3303> B_IWL<3302> B_IWL<3301> B_IWL<3300> B_IWL<3299> B_IWL<3298> B_IWL<3297> B_IWL<3296> B_IWL<3295> B_IWL<3294> B_IWL<3293> B_IWL<3292> B_IWL<3291> B_IWL<3290> B_IWL<3289> B_IWL<3288> B_IWL<3287> B_IWL<3286> B_IWL<3285> B_IWL<3284> B_IWL<3283> B_IWL<3282> B_IWL<3281> B_IWL<3280> B_IWL<3279> B_IWL<3278> B_IWL<3277> B_IWL<3276> B_IWL<3275> B_IWL<3274> B_IWL<3273> B_IWL<3272> B_IWL<3271> B_IWL<3270> B_IWL<3269> B_IWL<3268> B_IWL<3267> B_IWL<3266> B_IWL<3265> B_IWL<3264> B_IWL<3263> B_IWL<3262> B_IWL<3261> B_IWL<3260> B_IWL<3259> B_IWL<3258> B_IWL<3257> B_IWL<3256> B_IWL<3255> B_IWL<3254> B_IWL<3253> B_IWL<3252> B_IWL<3251> B_IWL<3250> B_IWL<3249> B_IWL<3248> B_IWL<3247> B_IWL<3246> B_IWL<3245> B_IWL<3244> B_IWL<3243> B_IWL<3242> B_IWL<3241> B_IWL<3240> B_IWL<3239> B_IWL<3238> B_IWL<3237> B_IWL<3236> B_IWL<3235> B_IWL<3234> B_IWL<3233> B_IWL<3232> B_IWL<3231> B_IWL<3230> B_IWL<3229> B_IWL<3228> B_IWL<3227> B_IWL<3226> B_IWL<3225> B_IWL<3224> B_IWL<3223> B_IWL<3222> B_IWL<3221> B_IWL<3220> B_IWL<3219> B_IWL<3218> B_IWL<3217> B_IWL<3216> B_IWL<3215> B_IWL<3214> B_IWL<3213> B_IWL<3212> B_IWL<3211> B_IWL<3210> B_IWL<3209> B_IWL<3208> B_IWL<3207> B_IWL<3206> B_IWL<3205> B_IWL<3204> B_IWL<3203> B_IWL<3202> B_IWL<3201> B_IWL<3200> B_IWL<3199> B_IWL<3198> B_IWL<3197> B_IWL<3196> B_IWL<3195> B_IWL<3194> B_IWL<3193> B_IWL<3192> B_IWL<3191> B_IWL<3190> B_IWL<3189> B_IWL<3188> B_IWL<3187> B_IWL<3186> B_IWL<3185> B_IWL<3184> B_IWL<3183> B_IWL<3182> B_IWL<3181> B_IWL<3180> B_IWL<3179> B_IWL<3178> B_IWL<3177> B_IWL<3176> B_IWL<3175> B_IWL<3174> B_IWL<3173> B_IWL<3172> B_IWL<3171> B_IWL<3170> B_IWL<3169> B_IWL<3168> B_IWL<3167> B_IWL<3166> B_IWL<3165> B_IWL<3164> B_IWL<3163> B_IWL<3162> B_IWL<3161> B_IWL<3160> B_IWL<3159> B_IWL<3158> B_IWL<3157> B_IWL<3156> B_IWL<3155> B_IWL<3154> B_IWL<3153> B_IWL<3152> B_IWL<3151> B_IWL<3150> B_IWL<3149> B_IWL<3148> B_IWL<3147> B_IWL<3146> B_IWL<3145> B_IWL<3144> B_IWL<3143> B_IWL<3142> B_IWL<3141> B_IWL<3140> B_IWL<3139> B_IWL<3138> B_IWL<3137> B_IWL<3136> B_IWL<3135> B_IWL<3134> B_IWL<3133> B_IWL<3132> B_IWL<3131> B_IWL<3130> B_IWL<3129> B_IWL<3128> B_IWL<3127> B_IWL<3126> B_IWL<3125> B_IWL<3124> B_IWL<3123> B_IWL<3122> B_IWL<3121> B_IWL<3120> B_IWL<3119> B_IWL<3118> B_IWL<3117> B_IWL<3116> B_IWL<3115> B_IWL<3114> B_IWL<3113> B_IWL<3112> B_IWL<3111> B_IWL<3110> B_IWL<3109> B_IWL<3108> B_IWL<3107> B_IWL<3106> B_IWL<3105> B_IWL<3104> B_IWL<3103> B_IWL<3102> B_IWL<3101> B_IWL<3100> B_IWL<3099> B_IWL<3098> B_IWL<3097> B_IWL<3096> B_IWL<3095> B_IWL<3094> B_IWL<3093> B_IWL<3092> B_IWL<3091> B_IWL<3090> B_IWL<3089> B_IWL<3088> B_IWL<3087> B_IWL<3086> B_IWL<3085> B_IWL<3084> B_IWL<3083> B_IWL<3082> B_IWL<3081> B_IWL<3080> B_IWL<3079> B_IWL<3078> B_IWL<3077> B_IWL<3076> B_IWL<3075> B_IWL<3074> B_IWL<3073> B_IWL<3072> VDD_CORE VSS / RM_IHPSG13_1024x16_c2_2P_COLUMN_pcell_0 +XCOL<11> A_BLC<23> A_BLC<22> A_BLC_TOP<23> A_BLC_TOP<22> A_BLT<23> A_BLT<22> A_BLT_TOP<23> A_BLT_TOP<22> A_IWL<2815> A_IWL<2814> A_IWL<2813> A_IWL<2812> A_IWL<2811> A_IWL<2810> A_IWL<2809> A_IWL<2808> A_IWL<2807> A_IWL<2806> A_IWL<2805> A_IWL<2804> A_IWL<2803> A_IWL<2802> A_IWL<2801> A_IWL<2800> A_IWL<2799> A_IWL<2798> A_IWL<2797> A_IWL<2796> A_IWL<2795> A_IWL<2794> A_IWL<2793> A_IWL<2792> A_IWL<2791> A_IWL<2790> A_IWL<2789> A_IWL<2788> A_IWL<2787> A_IWL<2786> A_IWL<2785> A_IWL<2784> A_IWL<2783> A_IWL<2782> A_IWL<2781> A_IWL<2780> A_IWL<2779> A_IWL<2778> A_IWL<2777> A_IWL<2776> A_IWL<2775> A_IWL<2774> A_IWL<2773> A_IWL<2772> A_IWL<2771> A_IWL<2770> A_IWL<2769> A_IWL<2768> A_IWL<2767> A_IWL<2766> A_IWL<2765> A_IWL<2764> A_IWL<2763> A_IWL<2762> A_IWL<2761> A_IWL<2760> A_IWL<2759> A_IWL<2758> A_IWL<2757> A_IWL<2756> A_IWL<2755> A_IWL<2754> A_IWL<2753> A_IWL<2752> A_IWL<2751> A_IWL<2750> A_IWL<2749> A_IWL<2748> A_IWL<2747> A_IWL<2746> A_IWL<2745> A_IWL<2744> A_IWL<2743> A_IWL<2742> A_IWL<2741> A_IWL<2740> A_IWL<2739> A_IWL<2738> A_IWL<2737> A_IWL<2736> A_IWL<2735> A_IWL<2734> A_IWL<2733> A_IWL<2732> A_IWL<2731> A_IWL<2730> A_IWL<2729> A_IWL<2728> A_IWL<2727> A_IWL<2726> A_IWL<2725> A_IWL<2724> A_IWL<2723> A_IWL<2722> A_IWL<2721> A_IWL<2720> A_IWL<2719> A_IWL<2718> A_IWL<2717> A_IWL<2716> A_IWL<2715> A_IWL<2714> A_IWL<2713> A_IWL<2712> A_IWL<2711> A_IWL<2710> A_IWL<2709> A_IWL<2708> A_IWL<2707> A_IWL<2706> A_IWL<2705> A_IWL<2704> A_IWL<2703> A_IWL<2702> A_IWL<2701> A_IWL<2700> A_IWL<2699> A_IWL<2698> A_IWL<2697> A_IWL<2696> A_IWL<2695> A_IWL<2694> A_IWL<2693> A_IWL<2692> A_IWL<2691> A_IWL<2690> A_IWL<2689> A_IWL<2688> A_IWL<2687> A_IWL<2686> A_IWL<2685> A_IWL<2684> A_IWL<2683> A_IWL<2682> A_IWL<2681> A_IWL<2680> A_IWL<2679> A_IWL<2678> A_IWL<2677> A_IWL<2676> A_IWL<2675> A_IWL<2674> A_IWL<2673> A_IWL<2672> A_IWL<2671> A_IWL<2670> A_IWL<2669> A_IWL<2668> A_IWL<2667> A_IWL<2666> A_IWL<2665> A_IWL<2664> A_IWL<2663> A_IWL<2662> A_IWL<2661> A_IWL<2660> A_IWL<2659> A_IWL<2658> A_IWL<2657> A_IWL<2656> A_IWL<2655> A_IWL<2654> A_IWL<2653> A_IWL<2652> A_IWL<2651> A_IWL<2650> A_IWL<2649> A_IWL<2648> A_IWL<2647> A_IWL<2646> A_IWL<2645> A_IWL<2644> A_IWL<2643> A_IWL<2642> A_IWL<2641> A_IWL<2640> A_IWL<2639> A_IWL<2638> A_IWL<2637> A_IWL<2636> A_IWL<2635> A_IWL<2634> A_IWL<2633> A_IWL<2632> A_IWL<2631> A_IWL<2630> A_IWL<2629> A_IWL<2628> A_IWL<2627> A_IWL<2626> A_IWL<2625> A_IWL<2624> A_IWL<2623> A_IWL<2622> A_IWL<2621> A_IWL<2620> A_IWL<2619> A_IWL<2618> A_IWL<2617> A_IWL<2616> A_IWL<2615> A_IWL<2614> A_IWL<2613> A_IWL<2612> A_IWL<2611> A_IWL<2610> A_IWL<2609> A_IWL<2608> A_IWL<2607> A_IWL<2606> A_IWL<2605> A_IWL<2604> A_IWL<2603> A_IWL<2602> A_IWL<2601> A_IWL<2600> A_IWL<2599> A_IWL<2598> A_IWL<2597> A_IWL<2596> A_IWL<2595> A_IWL<2594> A_IWL<2593> A_IWL<2592> A_IWL<2591> A_IWL<2590> A_IWL<2589> A_IWL<2588> A_IWL<2587> A_IWL<2586> A_IWL<2585> A_IWL<2584> A_IWL<2583> A_IWL<2582> A_IWL<2581> A_IWL<2580> A_IWL<2579> A_IWL<2578> A_IWL<2577> A_IWL<2576> A_IWL<2575> A_IWL<2574> A_IWL<2573> A_IWL<2572> A_IWL<2571> A_IWL<2570> A_IWL<2569> A_IWL<2568> A_IWL<2567> A_IWL<2566> A_IWL<2565> A_IWL<2564> A_IWL<2563> A_IWL<2562> A_IWL<2561> A_IWL<2560> A_IWL<3071> A_IWL<3070> A_IWL<3069> A_IWL<3068> A_IWL<3067> A_IWL<3066> A_IWL<3065> A_IWL<3064> A_IWL<3063> A_IWL<3062> A_IWL<3061> A_IWL<3060> A_IWL<3059> A_IWL<3058> A_IWL<3057> A_IWL<3056> A_IWL<3055> A_IWL<3054> A_IWL<3053> A_IWL<3052> A_IWL<3051> A_IWL<3050> A_IWL<3049> A_IWL<3048> A_IWL<3047> A_IWL<3046> A_IWL<3045> A_IWL<3044> A_IWL<3043> A_IWL<3042> A_IWL<3041> A_IWL<3040> A_IWL<3039> A_IWL<3038> A_IWL<3037> A_IWL<3036> A_IWL<3035> A_IWL<3034> A_IWL<3033> A_IWL<3032> A_IWL<3031> A_IWL<3030> A_IWL<3029> A_IWL<3028> A_IWL<3027> A_IWL<3026> A_IWL<3025> A_IWL<3024> A_IWL<3023> A_IWL<3022> A_IWL<3021> A_IWL<3020> A_IWL<3019> A_IWL<3018> A_IWL<3017> A_IWL<3016> A_IWL<3015> A_IWL<3014> A_IWL<3013> A_IWL<3012> A_IWL<3011> A_IWL<3010> A_IWL<3009> A_IWL<3008> A_IWL<3007> A_IWL<3006> A_IWL<3005> A_IWL<3004> A_IWL<3003> A_IWL<3002> A_IWL<3001> A_IWL<3000> A_IWL<2999> A_IWL<2998> A_IWL<2997> A_IWL<2996> A_IWL<2995> A_IWL<2994> A_IWL<2993> A_IWL<2992> A_IWL<2991> A_IWL<2990> A_IWL<2989> A_IWL<2988> A_IWL<2987> A_IWL<2986> A_IWL<2985> A_IWL<2984> A_IWL<2983> A_IWL<2982> A_IWL<2981> A_IWL<2980> A_IWL<2979> A_IWL<2978> A_IWL<2977> A_IWL<2976> A_IWL<2975> A_IWL<2974> A_IWL<2973> A_IWL<2972> A_IWL<2971> A_IWL<2970> A_IWL<2969> A_IWL<2968> A_IWL<2967> A_IWL<2966> A_IWL<2965> A_IWL<2964> A_IWL<2963> A_IWL<2962> A_IWL<2961> A_IWL<2960> A_IWL<2959> A_IWL<2958> A_IWL<2957> A_IWL<2956> A_IWL<2955> A_IWL<2954> A_IWL<2953> A_IWL<2952> A_IWL<2951> A_IWL<2950> A_IWL<2949> A_IWL<2948> A_IWL<2947> A_IWL<2946> A_IWL<2945> A_IWL<2944> A_IWL<2943> A_IWL<2942> A_IWL<2941> A_IWL<2940> A_IWL<2939> A_IWL<2938> A_IWL<2937> A_IWL<2936> A_IWL<2935> A_IWL<2934> A_IWL<2933> A_IWL<2932> A_IWL<2931> A_IWL<2930> A_IWL<2929> A_IWL<2928> A_IWL<2927> A_IWL<2926> A_IWL<2925> A_IWL<2924> A_IWL<2923> A_IWL<2922> A_IWL<2921> A_IWL<2920> A_IWL<2919> A_IWL<2918> A_IWL<2917> A_IWL<2916> A_IWL<2915> A_IWL<2914> A_IWL<2913> A_IWL<2912> A_IWL<2911> A_IWL<2910> A_IWL<2909> A_IWL<2908> A_IWL<2907> A_IWL<2906> A_IWL<2905> A_IWL<2904> A_IWL<2903> A_IWL<2902> A_IWL<2901> A_IWL<2900> A_IWL<2899> A_IWL<2898> A_IWL<2897> A_IWL<2896> A_IWL<2895> A_IWL<2894> A_IWL<2893> A_IWL<2892> A_IWL<2891> A_IWL<2890> A_IWL<2889> A_IWL<2888> A_IWL<2887> A_IWL<2886> A_IWL<2885> A_IWL<2884> A_IWL<2883> A_IWL<2882> A_IWL<2881> A_IWL<2880> A_IWL<2879> A_IWL<2878> A_IWL<2877> A_IWL<2876> A_IWL<2875> A_IWL<2874> A_IWL<2873> A_IWL<2872> A_IWL<2871> A_IWL<2870> A_IWL<2869> A_IWL<2868> A_IWL<2867> A_IWL<2866> A_IWL<2865> A_IWL<2864> A_IWL<2863> A_IWL<2862> A_IWL<2861> A_IWL<2860> A_IWL<2859> A_IWL<2858> A_IWL<2857> A_IWL<2856> A_IWL<2855> A_IWL<2854> A_IWL<2853> A_IWL<2852> A_IWL<2851> A_IWL<2850> A_IWL<2849> A_IWL<2848> A_IWL<2847> A_IWL<2846> A_IWL<2845> A_IWL<2844> A_IWL<2843> A_IWL<2842> A_IWL<2841> A_IWL<2840> A_IWL<2839> A_IWL<2838> A_IWL<2837> A_IWL<2836> A_IWL<2835> A_IWL<2834> A_IWL<2833> A_IWL<2832> A_IWL<2831> A_IWL<2830> A_IWL<2829> A_IWL<2828> A_IWL<2827> A_IWL<2826> A_IWL<2825> A_IWL<2824> A_IWL<2823> A_IWL<2822> A_IWL<2821> A_IWL<2820> A_IWL<2819> A_IWL<2818> A_IWL<2817> A_IWL<2816> B_BLC<23> B_BLC<22> B_BLC_TOP<23> B_BLC_TOP<22> B_BLT<23> B_BLT<22> B_BLT_TOP<23> B_BLT_TOP<22> B_IWL<2815> B_IWL<2814> B_IWL<2813> B_IWL<2812> B_IWL<2811> B_IWL<2810> B_IWL<2809> B_IWL<2808> B_IWL<2807> B_IWL<2806> B_IWL<2805> B_IWL<2804> B_IWL<2803> B_IWL<2802> B_IWL<2801> B_IWL<2800> B_IWL<2799> B_IWL<2798> B_IWL<2797> B_IWL<2796> B_IWL<2795> B_IWL<2794> B_IWL<2793> B_IWL<2792> B_IWL<2791> B_IWL<2790> B_IWL<2789> B_IWL<2788> B_IWL<2787> B_IWL<2786> B_IWL<2785> B_IWL<2784> B_IWL<2783> B_IWL<2782> B_IWL<2781> B_IWL<2780> B_IWL<2779> B_IWL<2778> B_IWL<2777> B_IWL<2776> B_IWL<2775> B_IWL<2774> B_IWL<2773> B_IWL<2772> B_IWL<2771> B_IWL<2770> B_IWL<2769> B_IWL<2768> B_IWL<2767> B_IWL<2766> B_IWL<2765> B_IWL<2764> B_IWL<2763> B_IWL<2762> B_IWL<2761> B_IWL<2760> B_IWL<2759> B_IWL<2758> B_IWL<2757> B_IWL<2756> B_IWL<2755> B_IWL<2754> B_IWL<2753> B_IWL<2752> B_IWL<2751> B_IWL<2750> B_IWL<2749> B_IWL<2748> B_IWL<2747> B_IWL<2746> B_IWL<2745> B_IWL<2744> B_IWL<2743> B_IWL<2742> B_IWL<2741> B_IWL<2740> B_IWL<2739> B_IWL<2738> B_IWL<2737> B_IWL<2736> B_IWL<2735> B_IWL<2734> B_IWL<2733> B_IWL<2732> B_IWL<2731> B_IWL<2730> B_IWL<2729> B_IWL<2728> B_IWL<2727> B_IWL<2726> B_IWL<2725> B_IWL<2724> B_IWL<2723> B_IWL<2722> B_IWL<2721> B_IWL<2720> B_IWL<2719> B_IWL<2718> B_IWL<2717> B_IWL<2716> B_IWL<2715> B_IWL<2714> B_IWL<2713> B_IWL<2712> B_IWL<2711> B_IWL<2710> B_IWL<2709> B_IWL<2708> B_IWL<2707> B_IWL<2706> B_IWL<2705> B_IWL<2704> B_IWL<2703> B_IWL<2702> B_IWL<2701> B_IWL<2700> B_IWL<2699> B_IWL<2698> B_IWL<2697> B_IWL<2696> B_IWL<2695> B_IWL<2694> B_IWL<2693> B_IWL<2692> B_IWL<2691> B_IWL<2690> B_IWL<2689> B_IWL<2688> B_IWL<2687> B_IWL<2686> B_IWL<2685> B_IWL<2684> B_IWL<2683> B_IWL<2682> B_IWL<2681> B_IWL<2680> B_IWL<2679> B_IWL<2678> B_IWL<2677> B_IWL<2676> B_IWL<2675> B_IWL<2674> B_IWL<2673> B_IWL<2672> B_IWL<2671> B_IWL<2670> B_IWL<2669> B_IWL<2668> B_IWL<2667> B_IWL<2666> B_IWL<2665> B_IWL<2664> B_IWL<2663> B_IWL<2662> B_IWL<2661> B_IWL<2660> B_IWL<2659> B_IWL<2658> B_IWL<2657> B_IWL<2656> B_IWL<2655> B_IWL<2654> B_IWL<2653> B_IWL<2652> B_IWL<2651> B_IWL<2650> B_IWL<2649> B_IWL<2648> B_IWL<2647> B_IWL<2646> B_IWL<2645> B_IWL<2644> B_IWL<2643> B_IWL<2642> B_IWL<2641> B_IWL<2640> B_IWL<2639> B_IWL<2638> B_IWL<2637> B_IWL<2636> B_IWL<2635> B_IWL<2634> B_IWL<2633> B_IWL<2632> B_IWL<2631> B_IWL<2630> B_IWL<2629> B_IWL<2628> B_IWL<2627> B_IWL<2626> B_IWL<2625> B_IWL<2624> B_IWL<2623> B_IWL<2622> B_IWL<2621> B_IWL<2620> B_IWL<2619> B_IWL<2618> B_IWL<2617> B_IWL<2616> B_IWL<2615> B_IWL<2614> B_IWL<2613> B_IWL<2612> B_IWL<2611> B_IWL<2610> B_IWL<2609> B_IWL<2608> B_IWL<2607> B_IWL<2606> B_IWL<2605> B_IWL<2604> B_IWL<2603> B_IWL<2602> B_IWL<2601> B_IWL<2600> B_IWL<2599> B_IWL<2598> B_IWL<2597> B_IWL<2596> B_IWL<2595> B_IWL<2594> B_IWL<2593> B_IWL<2592> B_IWL<2591> B_IWL<2590> B_IWL<2589> B_IWL<2588> B_IWL<2587> B_IWL<2586> B_IWL<2585> B_IWL<2584> B_IWL<2583> B_IWL<2582> B_IWL<2581> B_IWL<2580> B_IWL<2579> B_IWL<2578> B_IWL<2577> B_IWL<2576> B_IWL<2575> B_IWL<2574> B_IWL<2573> B_IWL<2572> B_IWL<2571> B_IWL<2570> B_IWL<2569> B_IWL<2568> B_IWL<2567> B_IWL<2566> B_IWL<2565> B_IWL<2564> B_IWL<2563> B_IWL<2562> B_IWL<2561> B_IWL<2560> B_IWL<3071> B_IWL<3070> B_IWL<3069> B_IWL<3068> B_IWL<3067> B_IWL<3066> B_IWL<3065> B_IWL<3064> B_IWL<3063> B_IWL<3062> B_IWL<3061> B_IWL<3060> B_IWL<3059> B_IWL<3058> B_IWL<3057> B_IWL<3056> B_IWL<3055> B_IWL<3054> B_IWL<3053> B_IWL<3052> B_IWL<3051> B_IWL<3050> B_IWL<3049> B_IWL<3048> B_IWL<3047> B_IWL<3046> B_IWL<3045> B_IWL<3044> B_IWL<3043> B_IWL<3042> B_IWL<3041> B_IWL<3040> B_IWL<3039> B_IWL<3038> B_IWL<3037> B_IWL<3036> B_IWL<3035> B_IWL<3034> B_IWL<3033> B_IWL<3032> B_IWL<3031> B_IWL<3030> B_IWL<3029> B_IWL<3028> B_IWL<3027> B_IWL<3026> B_IWL<3025> B_IWL<3024> B_IWL<3023> B_IWL<3022> B_IWL<3021> B_IWL<3020> B_IWL<3019> B_IWL<3018> B_IWL<3017> B_IWL<3016> B_IWL<3015> B_IWL<3014> B_IWL<3013> B_IWL<3012> B_IWL<3011> B_IWL<3010> B_IWL<3009> B_IWL<3008> B_IWL<3007> B_IWL<3006> B_IWL<3005> B_IWL<3004> B_IWL<3003> B_IWL<3002> B_IWL<3001> B_IWL<3000> B_IWL<2999> B_IWL<2998> B_IWL<2997> B_IWL<2996> B_IWL<2995> B_IWL<2994> B_IWL<2993> B_IWL<2992> B_IWL<2991> B_IWL<2990> B_IWL<2989> B_IWL<2988> B_IWL<2987> B_IWL<2986> B_IWL<2985> B_IWL<2984> B_IWL<2983> B_IWL<2982> B_IWL<2981> B_IWL<2980> B_IWL<2979> B_IWL<2978> B_IWL<2977> B_IWL<2976> B_IWL<2975> B_IWL<2974> B_IWL<2973> B_IWL<2972> B_IWL<2971> B_IWL<2970> B_IWL<2969> B_IWL<2968> B_IWL<2967> B_IWL<2966> B_IWL<2965> B_IWL<2964> B_IWL<2963> B_IWL<2962> B_IWL<2961> B_IWL<2960> B_IWL<2959> B_IWL<2958> B_IWL<2957> B_IWL<2956> B_IWL<2955> B_IWL<2954> B_IWL<2953> B_IWL<2952> B_IWL<2951> B_IWL<2950> B_IWL<2949> B_IWL<2948> B_IWL<2947> B_IWL<2946> B_IWL<2945> B_IWL<2944> B_IWL<2943> B_IWL<2942> B_IWL<2941> B_IWL<2940> B_IWL<2939> B_IWL<2938> B_IWL<2937> B_IWL<2936> B_IWL<2935> B_IWL<2934> B_IWL<2933> B_IWL<2932> B_IWL<2931> B_IWL<2930> B_IWL<2929> B_IWL<2928> B_IWL<2927> B_IWL<2926> B_IWL<2925> B_IWL<2924> B_IWL<2923> B_IWL<2922> B_IWL<2921> B_IWL<2920> B_IWL<2919> B_IWL<2918> B_IWL<2917> B_IWL<2916> B_IWL<2915> B_IWL<2914> B_IWL<2913> B_IWL<2912> B_IWL<2911> B_IWL<2910> B_IWL<2909> B_IWL<2908> B_IWL<2907> B_IWL<2906> B_IWL<2905> B_IWL<2904> B_IWL<2903> B_IWL<2902> B_IWL<2901> B_IWL<2900> B_IWL<2899> B_IWL<2898> B_IWL<2897> B_IWL<2896> B_IWL<2895> B_IWL<2894> B_IWL<2893> B_IWL<2892> B_IWL<2891> B_IWL<2890> B_IWL<2889> B_IWL<2888> B_IWL<2887> B_IWL<2886> B_IWL<2885> B_IWL<2884> B_IWL<2883> B_IWL<2882> B_IWL<2881> B_IWL<2880> B_IWL<2879> B_IWL<2878> B_IWL<2877> B_IWL<2876> B_IWL<2875> B_IWL<2874> B_IWL<2873> B_IWL<2872> B_IWL<2871> B_IWL<2870> B_IWL<2869> B_IWL<2868> B_IWL<2867> B_IWL<2866> B_IWL<2865> B_IWL<2864> B_IWL<2863> B_IWL<2862> B_IWL<2861> B_IWL<2860> B_IWL<2859> B_IWL<2858> B_IWL<2857> B_IWL<2856> B_IWL<2855> B_IWL<2854> B_IWL<2853> B_IWL<2852> B_IWL<2851> B_IWL<2850> B_IWL<2849> B_IWL<2848> B_IWL<2847> B_IWL<2846> B_IWL<2845> B_IWL<2844> B_IWL<2843> B_IWL<2842> B_IWL<2841> B_IWL<2840> B_IWL<2839> B_IWL<2838> B_IWL<2837> B_IWL<2836> B_IWL<2835> B_IWL<2834> B_IWL<2833> B_IWL<2832> B_IWL<2831> B_IWL<2830> B_IWL<2829> B_IWL<2828> B_IWL<2827> B_IWL<2826> B_IWL<2825> B_IWL<2824> B_IWL<2823> B_IWL<2822> B_IWL<2821> B_IWL<2820> B_IWL<2819> B_IWL<2818> B_IWL<2817> B_IWL<2816> VDD_CORE VSS / RM_IHPSG13_1024x16_c2_2P_COLUMN_pcell_0 +XCOL<10> A_BLC<21> A_BLC<20> A_BLC_TOP<21> A_BLC_TOP<20> A_BLT<21> A_BLT<20> A_BLT_TOP<21> A_BLT_TOP<20> A_IWL<2559> A_IWL<2558> A_IWL<2557> A_IWL<2556> A_IWL<2555> A_IWL<2554> A_IWL<2553> A_IWL<2552> A_IWL<2551> A_IWL<2550> A_IWL<2549> A_IWL<2548> A_IWL<2547> A_IWL<2546> A_IWL<2545> A_IWL<2544> A_IWL<2543> A_IWL<2542> A_IWL<2541> A_IWL<2540> A_IWL<2539> A_IWL<2538> A_IWL<2537> A_IWL<2536> A_IWL<2535> A_IWL<2534> A_IWL<2533> A_IWL<2532> A_IWL<2531> A_IWL<2530> A_IWL<2529> A_IWL<2528> A_IWL<2527> A_IWL<2526> A_IWL<2525> A_IWL<2524> A_IWL<2523> A_IWL<2522> A_IWL<2521> A_IWL<2520> A_IWL<2519> A_IWL<2518> A_IWL<2517> A_IWL<2516> A_IWL<2515> A_IWL<2514> A_IWL<2513> A_IWL<2512> A_IWL<2511> A_IWL<2510> A_IWL<2509> A_IWL<2508> A_IWL<2507> A_IWL<2506> A_IWL<2505> A_IWL<2504> A_IWL<2503> A_IWL<2502> A_IWL<2501> A_IWL<2500> A_IWL<2499> A_IWL<2498> A_IWL<2497> A_IWL<2496> A_IWL<2495> A_IWL<2494> A_IWL<2493> A_IWL<2492> A_IWL<2491> A_IWL<2490> A_IWL<2489> A_IWL<2488> A_IWL<2487> A_IWL<2486> A_IWL<2485> A_IWL<2484> A_IWL<2483> A_IWL<2482> A_IWL<2481> A_IWL<2480> A_IWL<2479> A_IWL<2478> A_IWL<2477> A_IWL<2476> A_IWL<2475> A_IWL<2474> A_IWL<2473> A_IWL<2472> A_IWL<2471> A_IWL<2470> A_IWL<2469> A_IWL<2468> A_IWL<2467> A_IWL<2466> A_IWL<2465> A_IWL<2464> A_IWL<2463> A_IWL<2462> A_IWL<2461> A_IWL<2460> A_IWL<2459> A_IWL<2458> A_IWL<2457> A_IWL<2456> A_IWL<2455> A_IWL<2454> A_IWL<2453> A_IWL<2452> A_IWL<2451> A_IWL<2450> A_IWL<2449> A_IWL<2448> A_IWL<2447> A_IWL<2446> A_IWL<2445> A_IWL<2444> A_IWL<2443> A_IWL<2442> A_IWL<2441> A_IWL<2440> A_IWL<2439> A_IWL<2438> A_IWL<2437> A_IWL<2436> A_IWL<2435> A_IWL<2434> A_IWL<2433> A_IWL<2432> A_IWL<2431> A_IWL<2430> A_IWL<2429> A_IWL<2428> A_IWL<2427> A_IWL<2426> A_IWL<2425> A_IWL<2424> A_IWL<2423> A_IWL<2422> A_IWL<2421> A_IWL<2420> A_IWL<2419> A_IWL<2418> A_IWL<2417> A_IWL<2416> A_IWL<2415> A_IWL<2414> A_IWL<2413> A_IWL<2412> A_IWL<2411> A_IWL<2410> A_IWL<2409> A_IWL<2408> A_IWL<2407> A_IWL<2406> A_IWL<2405> A_IWL<2404> A_IWL<2403> A_IWL<2402> A_IWL<2401> A_IWL<2400> A_IWL<2399> A_IWL<2398> A_IWL<2397> A_IWL<2396> A_IWL<2395> A_IWL<2394> A_IWL<2393> A_IWL<2392> A_IWL<2391> A_IWL<2390> A_IWL<2389> A_IWL<2388> A_IWL<2387> A_IWL<2386> A_IWL<2385> A_IWL<2384> A_IWL<2383> A_IWL<2382> A_IWL<2381> A_IWL<2380> A_IWL<2379> A_IWL<2378> A_IWL<2377> A_IWL<2376> A_IWL<2375> A_IWL<2374> A_IWL<2373> A_IWL<2372> A_IWL<2371> A_IWL<2370> A_IWL<2369> A_IWL<2368> A_IWL<2367> A_IWL<2366> A_IWL<2365> A_IWL<2364> A_IWL<2363> A_IWL<2362> A_IWL<2361> A_IWL<2360> A_IWL<2359> A_IWL<2358> A_IWL<2357> A_IWL<2356> A_IWL<2355> A_IWL<2354> A_IWL<2353> A_IWL<2352> A_IWL<2351> A_IWL<2350> A_IWL<2349> A_IWL<2348> A_IWL<2347> A_IWL<2346> A_IWL<2345> A_IWL<2344> A_IWL<2343> A_IWL<2342> A_IWL<2341> A_IWL<2340> A_IWL<2339> A_IWL<2338> A_IWL<2337> A_IWL<2336> A_IWL<2335> A_IWL<2334> A_IWL<2333> A_IWL<2332> A_IWL<2331> A_IWL<2330> A_IWL<2329> A_IWL<2328> A_IWL<2327> A_IWL<2326> A_IWL<2325> A_IWL<2324> A_IWL<2323> A_IWL<2322> A_IWL<2321> A_IWL<2320> A_IWL<2319> A_IWL<2318> A_IWL<2317> A_IWL<2316> A_IWL<2315> A_IWL<2314> A_IWL<2313> A_IWL<2312> A_IWL<2311> A_IWL<2310> A_IWL<2309> A_IWL<2308> A_IWL<2307> A_IWL<2306> A_IWL<2305> A_IWL<2304> A_IWL<2815> A_IWL<2814> A_IWL<2813> A_IWL<2812> A_IWL<2811> A_IWL<2810> A_IWL<2809> A_IWL<2808> A_IWL<2807> A_IWL<2806> A_IWL<2805> A_IWL<2804> A_IWL<2803> A_IWL<2802> A_IWL<2801> A_IWL<2800> A_IWL<2799> A_IWL<2798> A_IWL<2797> A_IWL<2796> A_IWL<2795> A_IWL<2794> A_IWL<2793> A_IWL<2792> A_IWL<2791> A_IWL<2790> A_IWL<2789> A_IWL<2788> A_IWL<2787> A_IWL<2786> A_IWL<2785> A_IWL<2784> A_IWL<2783> A_IWL<2782> A_IWL<2781> A_IWL<2780> A_IWL<2779> A_IWL<2778> A_IWL<2777> A_IWL<2776> A_IWL<2775> A_IWL<2774> A_IWL<2773> A_IWL<2772> A_IWL<2771> A_IWL<2770> A_IWL<2769> A_IWL<2768> A_IWL<2767> A_IWL<2766> A_IWL<2765> A_IWL<2764> A_IWL<2763> A_IWL<2762> A_IWL<2761> A_IWL<2760> A_IWL<2759> A_IWL<2758> A_IWL<2757> A_IWL<2756> A_IWL<2755> A_IWL<2754> A_IWL<2753> A_IWL<2752> A_IWL<2751> A_IWL<2750> A_IWL<2749> A_IWL<2748> A_IWL<2747> A_IWL<2746> A_IWL<2745> A_IWL<2744> A_IWL<2743> A_IWL<2742> A_IWL<2741> A_IWL<2740> A_IWL<2739> A_IWL<2738> A_IWL<2737> A_IWL<2736> A_IWL<2735> A_IWL<2734> A_IWL<2733> A_IWL<2732> A_IWL<2731> A_IWL<2730> A_IWL<2729> A_IWL<2728> A_IWL<2727> A_IWL<2726> A_IWL<2725> A_IWL<2724> A_IWL<2723> A_IWL<2722> A_IWL<2721> A_IWL<2720> A_IWL<2719> A_IWL<2718> A_IWL<2717> A_IWL<2716> A_IWL<2715> A_IWL<2714> A_IWL<2713> A_IWL<2712> A_IWL<2711> A_IWL<2710> A_IWL<2709> A_IWL<2708> A_IWL<2707> A_IWL<2706> A_IWL<2705> A_IWL<2704> A_IWL<2703> A_IWL<2702> A_IWL<2701> A_IWL<2700> A_IWL<2699> A_IWL<2698> A_IWL<2697> A_IWL<2696> A_IWL<2695> A_IWL<2694> A_IWL<2693> A_IWL<2692> A_IWL<2691> A_IWL<2690> A_IWL<2689> A_IWL<2688> A_IWL<2687> A_IWL<2686> A_IWL<2685> A_IWL<2684> A_IWL<2683> A_IWL<2682> A_IWL<2681> A_IWL<2680> A_IWL<2679> A_IWL<2678> A_IWL<2677> A_IWL<2676> A_IWL<2675> A_IWL<2674> A_IWL<2673> A_IWL<2672> A_IWL<2671> A_IWL<2670> A_IWL<2669> A_IWL<2668> A_IWL<2667> A_IWL<2666> A_IWL<2665> A_IWL<2664> A_IWL<2663> A_IWL<2662> A_IWL<2661> A_IWL<2660> A_IWL<2659> A_IWL<2658> A_IWL<2657> A_IWL<2656> A_IWL<2655> A_IWL<2654> A_IWL<2653> A_IWL<2652> A_IWL<2651> A_IWL<2650> A_IWL<2649> A_IWL<2648> A_IWL<2647> A_IWL<2646> A_IWL<2645> A_IWL<2644> A_IWL<2643> A_IWL<2642> A_IWL<2641> A_IWL<2640> A_IWL<2639> A_IWL<2638> A_IWL<2637> A_IWL<2636> A_IWL<2635> A_IWL<2634> A_IWL<2633> A_IWL<2632> A_IWL<2631> A_IWL<2630> A_IWL<2629> A_IWL<2628> A_IWL<2627> A_IWL<2626> A_IWL<2625> A_IWL<2624> A_IWL<2623> A_IWL<2622> A_IWL<2621> A_IWL<2620> A_IWL<2619> A_IWL<2618> A_IWL<2617> A_IWL<2616> A_IWL<2615> A_IWL<2614> A_IWL<2613> A_IWL<2612> A_IWL<2611> A_IWL<2610> A_IWL<2609> A_IWL<2608> A_IWL<2607> A_IWL<2606> A_IWL<2605> A_IWL<2604> A_IWL<2603> A_IWL<2602> A_IWL<2601> A_IWL<2600> A_IWL<2599> A_IWL<2598> A_IWL<2597> A_IWL<2596> A_IWL<2595> A_IWL<2594> A_IWL<2593> A_IWL<2592> A_IWL<2591> A_IWL<2590> A_IWL<2589> A_IWL<2588> A_IWL<2587> A_IWL<2586> A_IWL<2585> A_IWL<2584> A_IWL<2583> A_IWL<2582> A_IWL<2581> A_IWL<2580> A_IWL<2579> A_IWL<2578> A_IWL<2577> A_IWL<2576> A_IWL<2575> A_IWL<2574> A_IWL<2573> A_IWL<2572> A_IWL<2571> A_IWL<2570> A_IWL<2569> A_IWL<2568> A_IWL<2567> A_IWL<2566> A_IWL<2565> A_IWL<2564> A_IWL<2563> A_IWL<2562> A_IWL<2561> A_IWL<2560> B_BLC<21> B_BLC<20> B_BLC_TOP<21> B_BLC_TOP<20> B_BLT<21> B_BLT<20> B_BLT_TOP<21> B_BLT_TOP<20> B_IWL<2559> B_IWL<2558> B_IWL<2557> B_IWL<2556> B_IWL<2555> B_IWL<2554> B_IWL<2553> B_IWL<2552> B_IWL<2551> B_IWL<2550> B_IWL<2549> B_IWL<2548> B_IWL<2547> B_IWL<2546> B_IWL<2545> B_IWL<2544> B_IWL<2543> B_IWL<2542> B_IWL<2541> B_IWL<2540> B_IWL<2539> B_IWL<2538> B_IWL<2537> B_IWL<2536> B_IWL<2535> B_IWL<2534> B_IWL<2533> B_IWL<2532> B_IWL<2531> B_IWL<2530> B_IWL<2529> B_IWL<2528> B_IWL<2527> B_IWL<2526> B_IWL<2525> B_IWL<2524> B_IWL<2523> B_IWL<2522> B_IWL<2521> B_IWL<2520> B_IWL<2519> B_IWL<2518> B_IWL<2517> B_IWL<2516> B_IWL<2515> B_IWL<2514> B_IWL<2513> B_IWL<2512> B_IWL<2511> B_IWL<2510> B_IWL<2509> B_IWL<2508> B_IWL<2507> B_IWL<2506> B_IWL<2505> B_IWL<2504> B_IWL<2503> B_IWL<2502> B_IWL<2501> B_IWL<2500> B_IWL<2499> B_IWL<2498> B_IWL<2497> B_IWL<2496> B_IWL<2495> B_IWL<2494> B_IWL<2493> B_IWL<2492> B_IWL<2491> B_IWL<2490> B_IWL<2489> B_IWL<2488> B_IWL<2487> B_IWL<2486> B_IWL<2485> B_IWL<2484> B_IWL<2483> B_IWL<2482> B_IWL<2481> B_IWL<2480> B_IWL<2479> B_IWL<2478> B_IWL<2477> B_IWL<2476> B_IWL<2475> B_IWL<2474> B_IWL<2473> B_IWL<2472> B_IWL<2471> B_IWL<2470> B_IWL<2469> B_IWL<2468> B_IWL<2467> B_IWL<2466> B_IWL<2465> B_IWL<2464> B_IWL<2463> B_IWL<2462> B_IWL<2461> B_IWL<2460> B_IWL<2459> B_IWL<2458> B_IWL<2457> B_IWL<2456> B_IWL<2455> B_IWL<2454> B_IWL<2453> B_IWL<2452> B_IWL<2451> B_IWL<2450> B_IWL<2449> B_IWL<2448> B_IWL<2447> B_IWL<2446> B_IWL<2445> B_IWL<2444> B_IWL<2443> B_IWL<2442> B_IWL<2441> B_IWL<2440> B_IWL<2439> B_IWL<2438> B_IWL<2437> B_IWL<2436> B_IWL<2435> B_IWL<2434> B_IWL<2433> B_IWL<2432> B_IWL<2431> B_IWL<2430> B_IWL<2429> B_IWL<2428> B_IWL<2427> B_IWL<2426> B_IWL<2425> B_IWL<2424> B_IWL<2423> B_IWL<2422> B_IWL<2421> B_IWL<2420> B_IWL<2419> B_IWL<2418> B_IWL<2417> B_IWL<2416> B_IWL<2415> B_IWL<2414> B_IWL<2413> B_IWL<2412> B_IWL<2411> B_IWL<2410> B_IWL<2409> B_IWL<2408> B_IWL<2407> B_IWL<2406> B_IWL<2405> B_IWL<2404> B_IWL<2403> B_IWL<2402> B_IWL<2401> B_IWL<2400> B_IWL<2399> B_IWL<2398> B_IWL<2397> B_IWL<2396> B_IWL<2395> B_IWL<2394> B_IWL<2393> B_IWL<2392> B_IWL<2391> B_IWL<2390> B_IWL<2389> B_IWL<2388> B_IWL<2387> B_IWL<2386> B_IWL<2385> B_IWL<2384> B_IWL<2383> B_IWL<2382> B_IWL<2381> B_IWL<2380> B_IWL<2379> B_IWL<2378> B_IWL<2377> B_IWL<2376> B_IWL<2375> B_IWL<2374> B_IWL<2373> B_IWL<2372> B_IWL<2371> B_IWL<2370> B_IWL<2369> B_IWL<2368> B_IWL<2367> B_IWL<2366> B_IWL<2365> B_IWL<2364> B_IWL<2363> B_IWL<2362> B_IWL<2361> B_IWL<2360> B_IWL<2359> B_IWL<2358> B_IWL<2357> B_IWL<2356> B_IWL<2355> B_IWL<2354> B_IWL<2353> B_IWL<2352> B_IWL<2351> B_IWL<2350> B_IWL<2349> B_IWL<2348> B_IWL<2347> B_IWL<2346> B_IWL<2345> B_IWL<2344> B_IWL<2343> B_IWL<2342> B_IWL<2341> B_IWL<2340> B_IWL<2339> B_IWL<2338> B_IWL<2337> B_IWL<2336> B_IWL<2335> B_IWL<2334> B_IWL<2333> B_IWL<2332> B_IWL<2331> B_IWL<2330> B_IWL<2329> B_IWL<2328> B_IWL<2327> B_IWL<2326> B_IWL<2325> B_IWL<2324> B_IWL<2323> B_IWL<2322> B_IWL<2321> B_IWL<2320> B_IWL<2319> B_IWL<2318> B_IWL<2317> B_IWL<2316> B_IWL<2315> B_IWL<2314> B_IWL<2313> B_IWL<2312> B_IWL<2311> B_IWL<2310> B_IWL<2309> B_IWL<2308> B_IWL<2307> B_IWL<2306> B_IWL<2305> B_IWL<2304> B_IWL<2815> B_IWL<2814> B_IWL<2813> B_IWL<2812> B_IWL<2811> B_IWL<2810> B_IWL<2809> B_IWL<2808> B_IWL<2807> B_IWL<2806> B_IWL<2805> B_IWL<2804> B_IWL<2803> B_IWL<2802> B_IWL<2801> B_IWL<2800> B_IWL<2799> B_IWL<2798> B_IWL<2797> B_IWL<2796> B_IWL<2795> B_IWL<2794> B_IWL<2793> B_IWL<2792> B_IWL<2791> B_IWL<2790> B_IWL<2789> B_IWL<2788> B_IWL<2787> B_IWL<2786> B_IWL<2785> B_IWL<2784> B_IWL<2783> B_IWL<2782> B_IWL<2781> B_IWL<2780> B_IWL<2779> B_IWL<2778> B_IWL<2777> B_IWL<2776> B_IWL<2775> B_IWL<2774> B_IWL<2773> B_IWL<2772> B_IWL<2771> B_IWL<2770> B_IWL<2769> B_IWL<2768> B_IWL<2767> B_IWL<2766> B_IWL<2765> B_IWL<2764> B_IWL<2763> B_IWL<2762> B_IWL<2761> B_IWL<2760> B_IWL<2759> B_IWL<2758> B_IWL<2757> B_IWL<2756> B_IWL<2755> B_IWL<2754> B_IWL<2753> B_IWL<2752> B_IWL<2751> B_IWL<2750> B_IWL<2749> B_IWL<2748> B_IWL<2747> B_IWL<2746> B_IWL<2745> B_IWL<2744> B_IWL<2743> B_IWL<2742> B_IWL<2741> B_IWL<2740> B_IWL<2739> B_IWL<2738> B_IWL<2737> B_IWL<2736> B_IWL<2735> B_IWL<2734> B_IWL<2733> B_IWL<2732> B_IWL<2731> B_IWL<2730> B_IWL<2729> B_IWL<2728> B_IWL<2727> B_IWL<2726> B_IWL<2725> B_IWL<2724> B_IWL<2723> B_IWL<2722> B_IWL<2721> B_IWL<2720> B_IWL<2719> B_IWL<2718> B_IWL<2717> B_IWL<2716> B_IWL<2715> B_IWL<2714> B_IWL<2713> B_IWL<2712> B_IWL<2711> B_IWL<2710> B_IWL<2709> B_IWL<2708> B_IWL<2707> B_IWL<2706> B_IWL<2705> B_IWL<2704> B_IWL<2703> B_IWL<2702> B_IWL<2701> B_IWL<2700> B_IWL<2699> B_IWL<2698> B_IWL<2697> B_IWL<2696> B_IWL<2695> B_IWL<2694> B_IWL<2693> B_IWL<2692> B_IWL<2691> B_IWL<2690> B_IWL<2689> B_IWL<2688> B_IWL<2687> B_IWL<2686> B_IWL<2685> B_IWL<2684> B_IWL<2683> B_IWL<2682> B_IWL<2681> B_IWL<2680> B_IWL<2679> B_IWL<2678> B_IWL<2677> B_IWL<2676> B_IWL<2675> B_IWL<2674> B_IWL<2673> B_IWL<2672> B_IWL<2671> B_IWL<2670> B_IWL<2669> B_IWL<2668> B_IWL<2667> B_IWL<2666> B_IWL<2665> B_IWL<2664> B_IWL<2663> B_IWL<2662> B_IWL<2661> B_IWL<2660> B_IWL<2659> B_IWL<2658> B_IWL<2657> B_IWL<2656> B_IWL<2655> B_IWL<2654> B_IWL<2653> B_IWL<2652> B_IWL<2651> B_IWL<2650> B_IWL<2649> B_IWL<2648> B_IWL<2647> B_IWL<2646> B_IWL<2645> B_IWL<2644> B_IWL<2643> B_IWL<2642> B_IWL<2641> B_IWL<2640> B_IWL<2639> B_IWL<2638> B_IWL<2637> B_IWL<2636> B_IWL<2635> B_IWL<2634> B_IWL<2633> B_IWL<2632> B_IWL<2631> B_IWL<2630> B_IWL<2629> B_IWL<2628> B_IWL<2627> B_IWL<2626> B_IWL<2625> B_IWL<2624> B_IWL<2623> B_IWL<2622> B_IWL<2621> B_IWL<2620> B_IWL<2619> B_IWL<2618> B_IWL<2617> B_IWL<2616> B_IWL<2615> B_IWL<2614> B_IWL<2613> B_IWL<2612> B_IWL<2611> B_IWL<2610> B_IWL<2609> B_IWL<2608> B_IWL<2607> B_IWL<2606> B_IWL<2605> B_IWL<2604> B_IWL<2603> B_IWL<2602> B_IWL<2601> B_IWL<2600> B_IWL<2599> B_IWL<2598> B_IWL<2597> B_IWL<2596> B_IWL<2595> B_IWL<2594> B_IWL<2593> B_IWL<2592> B_IWL<2591> B_IWL<2590> B_IWL<2589> B_IWL<2588> B_IWL<2587> B_IWL<2586> B_IWL<2585> B_IWL<2584> B_IWL<2583> B_IWL<2582> B_IWL<2581> B_IWL<2580> B_IWL<2579> B_IWL<2578> B_IWL<2577> B_IWL<2576> B_IWL<2575> B_IWL<2574> B_IWL<2573> B_IWL<2572> B_IWL<2571> B_IWL<2570> B_IWL<2569> B_IWL<2568> B_IWL<2567> B_IWL<2566> B_IWL<2565> B_IWL<2564> B_IWL<2563> B_IWL<2562> B_IWL<2561> B_IWL<2560> VDD_CORE VSS / RM_IHPSG13_1024x16_c2_2P_COLUMN_pcell_0 +XCOL<9> A_BLC<19> A_BLC<18> A_BLC_TOP<19> A_BLC_TOP<18> A_BLT<19> A_BLT<18> A_BLT_TOP<19> A_BLT_TOP<18> A_IWL<2303> A_IWL<2302> A_IWL<2301> A_IWL<2300> A_IWL<2299> A_IWL<2298> A_IWL<2297> A_IWL<2296> A_IWL<2295> A_IWL<2294> A_IWL<2293> A_IWL<2292> A_IWL<2291> A_IWL<2290> A_IWL<2289> A_IWL<2288> A_IWL<2287> A_IWL<2286> A_IWL<2285> A_IWL<2284> A_IWL<2283> A_IWL<2282> A_IWL<2281> A_IWL<2280> A_IWL<2279> A_IWL<2278> A_IWL<2277> A_IWL<2276> A_IWL<2275> A_IWL<2274> A_IWL<2273> A_IWL<2272> A_IWL<2271> A_IWL<2270> A_IWL<2269> A_IWL<2268> A_IWL<2267> A_IWL<2266> A_IWL<2265> A_IWL<2264> A_IWL<2263> A_IWL<2262> A_IWL<2261> A_IWL<2260> A_IWL<2259> A_IWL<2258> A_IWL<2257> A_IWL<2256> A_IWL<2255> A_IWL<2254> A_IWL<2253> A_IWL<2252> A_IWL<2251> A_IWL<2250> A_IWL<2249> A_IWL<2248> A_IWL<2247> A_IWL<2246> A_IWL<2245> A_IWL<2244> A_IWL<2243> A_IWL<2242> A_IWL<2241> A_IWL<2240> A_IWL<2239> A_IWL<2238> A_IWL<2237> A_IWL<2236> A_IWL<2235> A_IWL<2234> A_IWL<2233> A_IWL<2232> A_IWL<2231> A_IWL<2230> A_IWL<2229> A_IWL<2228> A_IWL<2227> A_IWL<2226> A_IWL<2225> A_IWL<2224> A_IWL<2223> A_IWL<2222> A_IWL<2221> A_IWL<2220> A_IWL<2219> A_IWL<2218> A_IWL<2217> A_IWL<2216> A_IWL<2215> A_IWL<2214> A_IWL<2213> A_IWL<2212> A_IWL<2211> A_IWL<2210> A_IWL<2209> A_IWL<2208> A_IWL<2207> A_IWL<2206> A_IWL<2205> A_IWL<2204> A_IWL<2203> A_IWL<2202> A_IWL<2201> A_IWL<2200> A_IWL<2199> A_IWL<2198> A_IWL<2197> A_IWL<2196> A_IWL<2195> A_IWL<2194> A_IWL<2193> A_IWL<2192> A_IWL<2191> A_IWL<2190> A_IWL<2189> A_IWL<2188> A_IWL<2187> A_IWL<2186> A_IWL<2185> A_IWL<2184> A_IWL<2183> A_IWL<2182> A_IWL<2181> A_IWL<2180> A_IWL<2179> A_IWL<2178> A_IWL<2177> A_IWL<2176> A_IWL<2175> A_IWL<2174> A_IWL<2173> A_IWL<2172> A_IWL<2171> A_IWL<2170> A_IWL<2169> A_IWL<2168> A_IWL<2167> A_IWL<2166> A_IWL<2165> A_IWL<2164> A_IWL<2163> A_IWL<2162> A_IWL<2161> A_IWL<2160> A_IWL<2159> A_IWL<2158> A_IWL<2157> A_IWL<2156> A_IWL<2155> A_IWL<2154> A_IWL<2153> A_IWL<2152> A_IWL<2151> A_IWL<2150> A_IWL<2149> A_IWL<2148> A_IWL<2147> A_IWL<2146> A_IWL<2145> A_IWL<2144> A_IWL<2143> A_IWL<2142> A_IWL<2141> A_IWL<2140> A_IWL<2139> A_IWL<2138> A_IWL<2137> A_IWL<2136> A_IWL<2135> A_IWL<2134> A_IWL<2133> A_IWL<2132> A_IWL<2131> A_IWL<2130> A_IWL<2129> A_IWL<2128> A_IWL<2127> A_IWL<2126> A_IWL<2125> A_IWL<2124> A_IWL<2123> A_IWL<2122> A_IWL<2121> A_IWL<2120> A_IWL<2119> A_IWL<2118> A_IWL<2117> A_IWL<2116> A_IWL<2115> A_IWL<2114> A_IWL<2113> A_IWL<2112> A_IWL<2111> A_IWL<2110> A_IWL<2109> A_IWL<2108> A_IWL<2107> A_IWL<2106> A_IWL<2105> A_IWL<2104> A_IWL<2103> A_IWL<2102> A_IWL<2101> A_IWL<2100> A_IWL<2099> A_IWL<2098> A_IWL<2097> A_IWL<2096> A_IWL<2095> A_IWL<2094> A_IWL<2093> A_IWL<2092> A_IWL<2091> A_IWL<2090> A_IWL<2089> A_IWL<2088> A_IWL<2087> A_IWL<2086> A_IWL<2085> A_IWL<2084> A_IWL<2083> A_IWL<2082> A_IWL<2081> A_IWL<2080> A_IWL<2079> A_IWL<2078> A_IWL<2077> A_IWL<2076> A_IWL<2075> A_IWL<2074> A_IWL<2073> A_IWL<2072> A_IWL<2071> A_IWL<2070> A_IWL<2069> A_IWL<2068> A_IWL<2067> A_IWL<2066> A_IWL<2065> A_IWL<2064> A_IWL<2063> A_IWL<2062> A_IWL<2061> A_IWL<2060> A_IWL<2059> A_IWL<2058> A_IWL<2057> A_IWL<2056> A_IWL<2055> A_IWL<2054> A_IWL<2053> A_IWL<2052> A_IWL<2051> A_IWL<2050> A_IWL<2049> A_IWL<2048> A_IWL<2559> A_IWL<2558> A_IWL<2557> A_IWL<2556> A_IWL<2555> A_IWL<2554> A_IWL<2553> A_IWL<2552> A_IWL<2551> A_IWL<2550> A_IWL<2549> A_IWL<2548> A_IWL<2547> A_IWL<2546> A_IWL<2545> A_IWL<2544> A_IWL<2543> A_IWL<2542> A_IWL<2541> A_IWL<2540> A_IWL<2539> A_IWL<2538> A_IWL<2537> A_IWL<2536> A_IWL<2535> A_IWL<2534> A_IWL<2533> A_IWL<2532> A_IWL<2531> A_IWL<2530> A_IWL<2529> A_IWL<2528> A_IWL<2527> A_IWL<2526> A_IWL<2525> A_IWL<2524> A_IWL<2523> A_IWL<2522> A_IWL<2521> A_IWL<2520> A_IWL<2519> A_IWL<2518> A_IWL<2517> A_IWL<2516> A_IWL<2515> A_IWL<2514> A_IWL<2513> A_IWL<2512> A_IWL<2511> A_IWL<2510> A_IWL<2509> A_IWL<2508> A_IWL<2507> A_IWL<2506> A_IWL<2505> A_IWL<2504> A_IWL<2503> A_IWL<2502> A_IWL<2501> A_IWL<2500> A_IWL<2499> A_IWL<2498> A_IWL<2497> A_IWL<2496> A_IWL<2495> A_IWL<2494> A_IWL<2493> A_IWL<2492> A_IWL<2491> A_IWL<2490> A_IWL<2489> A_IWL<2488> A_IWL<2487> A_IWL<2486> A_IWL<2485> A_IWL<2484> A_IWL<2483> A_IWL<2482> A_IWL<2481> A_IWL<2480> A_IWL<2479> A_IWL<2478> A_IWL<2477> A_IWL<2476> A_IWL<2475> A_IWL<2474> A_IWL<2473> A_IWL<2472> A_IWL<2471> A_IWL<2470> A_IWL<2469> A_IWL<2468> A_IWL<2467> A_IWL<2466> A_IWL<2465> A_IWL<2464> A_IWL<2463> A_IWL<2462> A_IWL<2461> A_IWL<2460> A_IWL<2459> A_IWL<2458> A_IWL<2457> A_IWL<2456> A_IWL<2455> A_IWL<2454> A_IWL<2453> A_IWL<2452> A_IWL<2451> A_IWL<2450> A_IWL<2449> A_IWL<2448> A_IWL<2447> A_IWL<2446> A_IWL<2445> A_IWL<2444> A_IWL<2443> A_IWL<2442> A_IWL<2441> A_IWL<2440> A_IWL<2439> A_IWL<2438> A_IWL<2437> A_IWL<2436> A_IWL<2435> A_IWL<2434> A_IWL<2433> A_IWL<2432> A_IWL<2431> A_IWL<2430> A_IWL<2429> A_IWL<2428> A_IWL<2427> A_IWL<2426> A_IWL<2425> A_IWL<2424> A_IWL<2423> A_IWL<2422> A_IWL<2421> A_IWL<2420> A_IWL<2419> A_IWL<2418> A_IWL<2417> A_IWL<2416> A_IWL<2415> A_IWL<2414> A_IWL<2413> A_IWL<2412> A_IWL<2411> A_IWL<2410> A_IWL<2409> A_IWL<2408> A_IWL<2407> A_IWL<2406> A_IWL<2405> A_IWL<2404> A_IWL<2403> A_IWL<2402> A_IWL<2401> A_IWL<2400> A_IWL<2399> A_IWL<2398> A_IWL<2397> A_IWL<2396> A_IWL<2395> A_IWL<2394> A_IWL<2393> A_IWL<2392> A_IWL<2391> A_IWL<2390> A_IWL<2389> A_IWL<2388> A_IWL<2387> A_IWL<2386> A_IWL<2385> A_IWL<2384> A_IWL<2383> A_IWL<2382> A_IWL<2381> A_IWL<2380> A_IWL<2379> A_IWL<2378> A_IWL<2377> A_IWL<2376> A_IWL<2375> A_IWL<2374> A_IWL<2373> A_IWL<2372> A_IWL<2371> A_IWL<2370> A_IWL<2369> A_IWL<2368> A_IWL<2367> A_IWL<2366> A_IWL<2365> A_IWL<2364> A_IWL<2363> A_IWL<2362> A_IWL<2361> A_IWL<2360> A_IWL<2359> A_IWL<2358> A_IWL<2357> A_IWL<2356> A_IWL<2355> A_IWL<2354> A_IWL<2353> A_IWL<2352> A_IWL<2351> A_IWL<2350> A_IWL<2349> A_IWL<2348> A_IWL<2347> A_IWL<2346> A_IWL<2345> A_IWL<2344> A_IWL<2343> A_IWL<2342> A_IWL<2341> A_IWL<2340> A_IWL<2339> A_IWL<2338> A_IWL<2337> A_IWL<2336> A_IWL<2335> A_IWL<2334> A_IWL<2333> A_IWL<2332> A_IWL<2331> A_IWL<2330> A_IWL<2329> A_IWL<2328> A_IWL<2327> A_IWL<2326> A_IWL<2325> A_IWL<2324> A_IWL<2323> A_IWL<2322> A_IWL<2321> A_IWL<2320> A_IWL<2319> A_IWL<2318> A_IWL<2317> A_IWL<2316> A_IWL<2315> A_IWL<2314> A_IWL<2313> A_IWL<2312> A_IWL<2311> A_IWL<2310> A_IWL<2309> A_IWL<2308> A_IWL<2307> A_IWL<2306> A_IWL<2305> A_IWL<2304> B_BLC<19> B_BLC<18> B_BLC_TOP<19> B_BLC_TOP<18> B_BLT<19> B_BLT<18> B_BLT_TOP<19> B_BLT_TOP<18> B_IWL<2303> B_IWL<2302> B_IWL<2301> B_IWL<2300> B_IWL<2299> B_IWL<2298> B_IWL<2297> B_IWL<2296> B_IWL<2295> B_IWL<2294> B_IWL<2293> B_IWL<2292> B_IWL<2291> B_IWL<2290> B_IWL<2289> B_IWL<2288> B_IWL<2287> B_IWL<2286> B_IWL<2285> B_IWL<2284> B_IWL<2283> B_IWL<2282> B_IWL<2281> B_IWL<2280> B_IWL<2279> B_IWL<2278> B_IWL<2277> B_IWL<2276> B_IWL<2275> B_IWL<2274> B_IWL<2273> B_IWL<2272> B_IWL<2271> B_IWL<2270> B_IWL<2269> B_IWL<2268> B_IWL<2267> B_IWL<2266> B_IWL<2265> B_IWL<2264> B_IWL<2263> B_IWL<2262> B_IWL<2261> B_IWL<2260> B_IWL<2259> B_IWL<2258> B_IWL<2257> B_IWL<2256> B_IWL<2255> B_IWL<2254> B_IWL<2253> B_IWL<2252> B_IWL<2251> B_IWL<2250> B_IWL<2249> B_IWL<2248> B_IWL<2247> B_IWL<2246> B_IWL<2245> B_IWL<2244> B_IWL<2243> B_IWL<2242> B_IWL<2241> B_IWL<2240> B_IWL<2239> B_IWL<2238> B_IWL<2237> B_IWL<2236> B_IWL<2235> B_IWL<2234> B_IWL<2233> B_IWL<2232> B_IWL<2231> B_IWL<2230> B_IWL<2229> B_IWL<2228> B_IWL<2227> B_IWL<2226> B_IWL<2225> B_IWL<2224> B_IWL<2223> B_IWL<2222> B_IWL<2221> B_IWL<2220> B_IWL<2219> B_IWL<2218> B_IWL<2217> B_IWL<2216> B_IWL<2215> B_IWL<2214> B_IWL<2213> B_IWL<2212> B_IWL<2211> B_IWL<2210> B_IWL<2209> B_IWL<2208> B_IWL<2207> B_IWL<2206> B_IWL<2205> B_IWL<2204> B_IWL<2203> B_IWL<2202> B_IWL<2201> B_IWL<2200> B_IWL<2199> B_IWL<2198> B_IWL<2197> B_IWL<2196> B_IWL<2195> B_IWL<2194> B_IWL<2193> B_IWL<2192> B_IWL<2191> B_IWL<2190> B_IWL<2189> B_IWL<2188> B_IWL<2187> B_IWL<2186> B_IWL<2185> B_IWL<2184> B_IWL<2183> B_IWL<2182> B_IWL<2181> B_IWL<2180> B_IWL<2179> B_IWL<2178> B_IWL<2177> B_IWL<2176> B_IWL<2175> B_IWL<2174> B_IWL<2173> B_IWL<2172> B_IWL<2171> B_IWL<2170> B_IWL<2169> B_IWL<2168> B_IWL<2167> B_IWL<2166> B_IWL<2165> B_IWL<2164> B_IWL<2163> B_IWL<2162> B_IWL<2161> B_IWL<2160> B_IWL<2159> B_IWL<2158> B_IWL<2157> B_IWL<2156> B_IWL<2155> B_IWL<2154> B_IWL<2153> B_IWL<2152> B_IWL<2151> B_IWL<2150> B_IWL<2149> B_IWL<2148> B_IWL<2147> B_IWL<2146> B_IWL<2145> B_IWL<2144> B_IWL<2143> B_IWL<2142> B_IWL<2141> B_IWL<2140> B_IWL<2139> B_IWL<2138> B_IWL<2137> B_IWL<2136> B_IWL<2135> B_IWL<2134> B_IWL<2133> B_IWL<2132> B_IWL<2131> B_IWL<2130> B_IWL<2129> B_IWL<2128> B_IWL<2127> B_IWL<2126> B_IWL<2125> B_IWL<2124> B_IWL<2123> B_IWL<2122> B_IWL<2121> B_IWL<2120> B_IWL<2119> B_IWL<2118> B_IWL<2117> B_IWL<2116> B_IWL<2115> B_IWL<2114> B_IWL<2113> B_IWL<2112> B_IWL<2111> B_IWL<2110> B_IWL<2109> B_IWL<2108> B_IWL<2107> B_IWL<2106> B_IWL<2105> B_IWL<2104> B_IWL<2103> B_IWL<2102> B_IWL<2101> B_IWL<2100> B_IWL<2099> B_IWL<2098> B_IWL<2097> B_IWL<2096> B_IWL<2095> B_IWL<2094> B_IWL<2093> B_IWL<2092> B_IWL<2091> B_IWL<2090> B_IWL<2089> B_IWL<2088> B_IWL<2087> B_IWL<2086> B_IWL<2085> B_IWL<2084> B_IWL<2083> B_IWL<2082> B_IWL<2081> B_IWL<2080> B_IWL<2079> B_IWL<2078> B_IWL<2077> B_IWL<2076> B_IWL<2075> B_IWL<2074> B_IWL<2073> B_IWL<2072> B_IWL<2071> B_IWL<2070> B_IWL<2069> B_IWL<2068> B_IWL<2067> B_IWL<2066> B_IWL<2065> B_IWL<2064> B_IWL<2063> B_IWL<2062> B_IWL<2061> B_IWL<2060> B_IWL<2059> B_IWL<2058> B_IWL<2057> B_IWL<2056> B_IWL<2055> B_IWL<2054> B_IWL<2053> B_IWL<2052> B_IWL<2051> B_IWL<2050> B_IWL<2049> B_IWL<2048> B_IWL<2559> B_IWL<2558> B_IWL<2557> B_IWL<2556> B_IWL<2555> B_IWL<2554> B_IWL<2553> B_IWL<2552> B_IWL<2551> B_IWL<2550> B_IWL<2549> B_IWL<2548> B_IWL<2547> B_IWL<2546> B_IWL<2545> B_IWL<2544> B_IWL<2543> B_IWL<2542> B_IWL<2541> B_IWL<2540> B_IWL<2539> B_IWL<2538> B_IWL<2537> B_IWL<2536> B_IWL<2535> B_IWL<2534> B_IWL<2533> B_IWL<2532> B_IWL<2531> B_IWL<2530> B_IWL<2529> B_IWL<2528> B_IWL<2527> B_IWL<2526> B_IWL<2525> B_IWL<2524> B_IWL<2523> B_IWL<2522> B_IWL<2521> B_IWL<2520> B_IWL<2519> B_IWL<2518> B_IWL<2517> B_IWL<2516> B_IWL<2515> B_IWL<2514> B_IWL<2513> B_IWL<2512> B_IWL<2511> B_IWL<2510> B_IWL<2509> B_IWL<2508> B_IWL<2507> B_IWL<2506> B_IWL<2505> B_IWL<2504> B_IWL<2503> B_IWL<2502> B_IWL<2501> B_IWL<2500> B_IWL<2499> B_IWL<2498> B_IWL<2497> B_IWL<2496> B_IWL<2495> B_IWL<2494> B_IWL<2493> B_IWL<2492> B_IWL<2491> B_IWL<2490> B_IWL<2489> B_IWL<2488> B_IWL<2487> B_IWL<2486> B_IWL<2485> B_IWL<2484> B_IWL<2483> B_IWL<2482> B_IWL<2481> B_IWL<2480> B_IWL<2479> B_IWL<2478> B_IWL<2477> B_IWL<2476> B_IWL<2475> B_IWL<2474> B_IWL<2473> B_IWL<2472> B_IWL<2471> B_IWL<2470> B_IWL<2469> B_IWL<2468> B_IWL<2467> B_IWL<2466> B_IWL<2465> B_IWL<2464> B_IWL<2463> B_IWL<2462> B_IWL<2461> B_IWL<2460> B_IWL<2459> B_IWL<2458> B_IWL<2457> B_IWL<2456> B_IWL<2455> B_IWL<2454> B_IWL<2453> B_IWL<2452> B_IWL<2451> B_IWL<2450> B_IWL<2449> B_IWL<2448> B_IWL<2447> B_IWL<2446> B_IWL<2445> B_IWL<2444> B_IWL<2443> B_IWL<2442> B_IWL<2441> B_IWL<2440> B_IWL<2439> B_IWL<2438> B_IWL<2437> B_IWL<2436> B_IWL<2435> B_IWL<2434> B_IWL<2433> B_IWL<2432> B_IWL<2431> B_IWL<2430> B_IWL<2429> B_IWL<2428> B_IWL<2427> B_IWL<2426> B_IWL<2425> B_IWL<2424> B_IWL<2423> B_IWL<2422> B_IWL<2421> B_IWL<2420> B_IWL<2419> B_IWL<2418> B_IWL<2417> B_IWL<2416> B_IWL<2415> B_IWL<2414> B_IWL<2413> B_IWL<2412> B_IWL<2411> B_IWL<2410> B_IWL<2409> B_IWL<2408> B_IWL<2407> B_IWL<2406> B_IWL<2405> B_IWL<2404> B_IWL<2403> B_IWL<2402> B_IWL<2401> B_IWL<2400> B_IWL<2399> B_IWL<2398> B_IWL<2397> B_IWL<2396> B_IWL<2395> B_IWL<2394> B_IWL<2393> B_IWL<2392> B_IWL<2391> B_IWL<2390> B_IWL<2389> B_IWL<2388> B_IWL<2387> B_IWL<2386> B_IWL<2385> B_IWL<2384> B_IWL<2383> B_IWL<2382> B_IWL<2381> B_IWL<2380> B_IWL<2379> B_IWL<2378> B_IWL<2377> B_IWL<2376> B_IWL<2375> B_IWL<2374> B_IWL<2373> B_IWL<2372> B_IWL<2371> B_IWL<2370> B_IWL<2369> B_IWL<2368> B_IWL<2367> B_IWL<2366> B_IWL<2365> B_IWL<2364> B_IWL<2363> B_IWL<2362> B_IWL<2361> B_IWL<2360> B_IWL<2359> B_IWL<2358> B_IWL<2357> B_IWL<2356> B_IWL<2355> B_IWL<2354> B_IWL<2353> B_IWL<2352> B_IWL<2351> B_IWL<2350> B_IWL<2349> B_IWL<2348> B_IWL<2347> B_IWL<2346> B_IWL<2345> B_IWL<2344> B_IWL<2343> B_IWL<2342> B_IWL<2341> B_IWL<2340> B_IWL<2339> B_IWL<2338> B_IWL<2337> B_IWL<2336> B_IWL<2335> B_IWL<2334> B_IWL<2333> B_IWL<2332> B_IWL<2331> B_IWL<2330> B_IWL<2329> B_IWL<2328> B_IWL<2327> B_IWL<2326> B_IWL<2325> B_IWL<2324> B_IWL<2323> B_IWL<2322> B_IWL<2321> B_IWL<2320> B_IWL<2319> B_IWL<2318> B_IWL<2317> B_IWL<2316> B_IWL<2315> B_IWL<2314> B_IWL<2313> B_IWL<2312> B_IWL<2311> B_IWL<2310> B_IWL<2309> B_IWL<2308> B_IWL<2307> B_IWL<2306> B_IWL<2305> B_IWL<2304> VDD_CORE VSS / RM_IHPSG13_1024x16_c2_2P_COLUMN_pcell_0 +XCOL<8> A_BLC<17> A_BLC<16> A_BLC_TOP<17> A_BLC_TOP<16> A_BLT<17> A_BLT<16> A_BLT_TOP<17> A_BLT_TOP<16> A_IWL<2047> A_IWL<2046> A_IWL<2045> A_IWL<2044> A_IWL<2043> A_IWL<2042> A_IWL<2041> A_IWL<2040> A_IWL<2039> A_IWL<2038> A_IWL<2037> A_IWL<2036> A_IWL<2035> A_IWL<2034> A_IWL<2033> A_IWL<2032> A_IWL<2031> A_IWL<2030> A_IWL<2029> A_IWL<2028> A_IWL<2027> A_IWL<2026> A_IWL<2025> A_IWL<2024> A_IWL<2023> A_IWL<2022> A_IWL<2021> A_IWL<2020> A_IWL<2019> A_IWL<2018> A_IWL<2017> A_IWL<2016> A_IWL<2015> A_IWL<2014> A_IWL<2013> A_IWL<2012> A_IWL<2011> A_IWL<2010> A_IWL<2009> A_IWL<2008> A_IWL<2007> A_IWL<2006> A_IWL<2005> A_IWL<2004> A_IWL<2003> A_IWL<2002> A_IWL<2001> A_IWL<2000> A_IWL<1999> A_IWL<1998> A_IWL<1997> A_IWL<1996> A_IWL<1995> A_IWL<1994> A_IWL<1993> A_IWL<1992> A_IWL<1991> A_IWL<1990> A_IWL<1989> A_IWL<1988> A_IWL<1987> A_IWL<1986> A_IWL<1985> A_IWL<1984> A_IWL<1983> A_IWL<1982> A_IWL<1981> A_IWL<1980> A_IWL<1979> A_IWL<1978> A_IWL<1977> A_IWL<1976> A_IWL<1975> A_IWL<1974> A_IWL<1973> A_IWL<1972> A_IWL<1971> A_IWL<1970> A_IWL<1969> A_IWL<1968> A_IWL<1967> A_IWL<1966> A_IWL<1965> A_IWL<1964> A_IWL<1963> A_IWL<1962> A_IWL<1961> A_IWL<1960> A_IWL<1959> A_IWL<1958> A_IWL<1957> A_IWL<1956> A_IWL<1955> A_IWL<1954> A_IWL<1953> A_IWL<1952> A_IWL<1951> A_IWL<1950> A_IWL<1949> A_IWL<1948> A_IWL<1947> A_IWL<1946> A_IWL<1945> A_IWL<1944> A_IWL<1943> A_IWL<1942> A_IWL<1941> A_IWL<1940> A_IWL<1939> A_IWL<1938> A_IWL<1937> A_IWL<1936> A_IWL<1935> A_IWL<1934> A_IWL<1933> A_IWL<1932> A_IWL<1931> A_IWL<1930> A_IWL<1929> A_IWL<1928> A_IWL<1927> A_IWL<1926> A_IWL<1925> A_IWL<1924> A_IWL<1923> A_IWL<1922> A_IWL<1921> A_IWL<1920> A_IWL<1919> A_IWL<1918> A_IWL<1917> A_IWL<1916> A_IWL<1915> A_IWL<1914> A_IWL<1913> A_IWL<1912> A_IWL<1911> A_IWL<1910> A_IWL<1909> A_IWL<1908> A_IWL<1907> A_IWL<1906> A_IWL<1905> A_IWL<1904> A_IWL<1903> A_IWL<1902> A_IWL<1901> A_IWL<1900> A_IWL<1899> A_IWL<1898> A_IWL<1897> A_IWL<1896> A_IWL<1895> A_IWL<1894> A_IWL<1893> A_IWL<1892> A_IWL<1891> A_IWL<1890> A_IWL<1889> A_IWL<1888> A_IWL<1887> A_IWL<1886> A_IWL<1885> A_IWL<1884> A_IWL<1883> A_IWL<1882> A_IWL<1881> A_IWL<1880> A_IWL<1879> A_IWL<1878> A_IWL<1877> A_IWL<1876> A_IWL<1875> A_IWL<1874> A_IWL<1873> A_IWL<1872> A_IWL<1871> A_IWL<1870> A_IWL<1869> A_IWL<1868> A_IWL<1867> A_IWL<1866> A_IWL<1865> A_IWL<1864> A_IWL<1863> A_IWL<1862> A_IWL<1861> A_IWL<1860> A_IWL<1859> A_IWL<1858> A_IWL<1857> A_IWL<1856> A_IWL<1855> A_IWL<1854> A_IWL<1853> A_IWL<1852> A_IWL<1851> A_IWL<1850> A_IWL<1849> A_IWL<1848> A_IWL<1847> A_IWL<1846> A_IWL<1845> A_IWL<1844> A_IWL<1843> A_IWL<1842> A_IWL<1841> A_IWL<1840> A_IWL<1839> A_IWL<1838> A_IWL<1837> A_IWL<1836> A_IWL<1835> A_IWL<1834> A_IWL<1833> A_IWL<1832> A_IWL<1831> A_IWL<1830> A_IWL<1829> A_IWL<1828> A_IWL<1827> A_IWL<1826> A_IWL<1825> A_IWL<1824> A_IWL<1823> A_IWL<1822> A_IWL<1821> A_IWL<1820> A_IWL<1819> A_IWL<1818> A_IWL<1817> A_IWL<1816> A_IWL<1815> A_IWL<1814> A_IWL<1813> A_IWL<1812> A_IWL<1811> A_IWL<1810> A_IWL<1809> A_IWL<1808> A_IWL<1807> A_IWL<1806> A_IWL<1805> A_IWL<1804> A_IWL<1803> A_IWL<1802> A_IWL<1801> A_IWL<1800> A_IWL<1799> A_IWL<1798> A_IWL<1797> A_IWL<1796> A_IWL<1795> A_IWL<1794> A_IWL<1793> A_IWL<1792> A_IWL<2303> A_IWL<2302> A_IWL<2301> A_IWL<2300> A_IWL<2299> A_IWL<2298> A_IWL<2297> A_IWL<2296> A_IWL<2295> A_IWL<2294> A_IWL<2293> A_IWL<2292> A_IWL<2291> A_IWL<2290> A_IWL<2289> A_IWL<2288> A_IWL<2287> A_IWL<2286> A_IWL<2285> A_IWL<2284> A_IWL<2283> A_IWL<2282> A_IWL<2281> A_IWL<2280> A_IWL<2279> A_IWL<2278> A_IWL<2277> A_IWL<2276> A_IWL<2275> A_IWL<2274> A_IWL<2273> A_IWL<2272> A_IWL<2271> A_IWL<2270> A_IWL<2269> A_IWL<2268> A_IWL<2267> A_IWL<2266> A_IWL<2265> A_IWL<2264> A_IWL<2263> A_IWL<2262> A_IWL<2261> A_IWL<2260> A_IWL<2259> A_IWL<2258> A_IWL<2257> A_IWL<2256> A_IWL<2255> A_IWL<2254> A_IWL<2253> A_IWL<2252> A_IWL<2251> A_IWL<2250> A_IWL<2249> A_IWL<2248> A_IWL<2247> A_IWL<2246> A_IWL<2245> A_IWL<2244> A_IWL<2243> A_IWL<2242> A_IWL<2241> A_IWL<2240> A_IWL<2239> A_IWL<2238> A_IWL<2237> A_IWL<2236> A_IWL<2235> A_IWL<2234> A_IWL<2233> A_IWL<2232> A_IWL<2231> A_IWL<2230> A_IWL<2229> A_IWL<2228> A_IWL<2227> A_IWL<2226> A_IWL<2225> A_IWL<2224> A_IWL<2223> A_IWL<2222> A_IWL<2221> A_IWL<2220> A_IWL<2219> A_IWL<2218> A_IWL<2217> A_IWL<2216> A_IWL<2215> A_IWL<2214> A_IWL<2213> A_IWL<2212> A_IWL<2211> A_IWL<2210> A_IWL<2209> A_IWL<2208> A_IWL<2207> A_IWL<2206> A_IWL<2205> A_IWL<2204> A_IWL<2203> A_IWL<2202> A_IWL<2201> A_IWL<2200> A_IWL<2199> A_IWL<2198> A_IWL<2197> A_IWL<2196> A_IWL<2195> A_IWL<2194> A_IWL<2193> A_IWL<2192> A_IWL<2191> A_IWL<2190> A_IWL<2189> A_IWL<2188> A_IWL<2187> A_IWL<2186> A_IWL<2185> A_IWL<2184> A_IWL<2183> A_IWL<2182> A_IWL<2181> A_IWL<2180> A_IWL<2179> A_IWL<2178> A_IWL<2177> A_IWL<2176> A_IWL<2175> A_IWL<2174> A_IWL<2173> A_IWL<2172> A_IWL<2171> A_IWL<2170> A_IWL<2169> A_IWL<2168> A_IWL<2167> A_IWL<2166> A_IWL<2165> A_IWL<2164> A_IWL<2163> A_IWL<2162> A_IWL<2161> A_IWL<2160> A_IWL<2159> A_IWL<2158> A_IWL<2157> A_IWL<2156> A_IWL<2155> A_IWL<2154> A_IWL<2153> A_IWL<2152> A_IWL<2151> A_IWL<2150> A_IWL<2149> A_IWL<2148> A_IWL<2147> A_IWL<2146> A_IWL<2145> A_IWL<2144> A_IWL<2143> A_IWL<2142> A_IWL<2141> A_IWL<2140> A_IWL<2139> A_IWL<2138> A_IWL<2137> A_IWL<2136> A_IWL<2135> A_IWL<2134> A_IWL<2133> A_IWL<2132> A_IWL<2131> A_IWL<2130> A_IWL<2129> A_IWL<2128> A_IWL<2127> A_IWL<2126> A_IWL<2125> A_IWL<2124> A_IWL<2123> A_IWL<2122> A_IWL<2121> A_IWL<2120> A_IWL<2119> A_IWL<2118> A_IWL<2117> A_IWL<2116> A_IWL<2115> A_IWL<2114> A_IWL<2113> A_IWL<2112> A_IWL<2111> A_IWL<2110> A_IWL<2109> A_IWL<2108> A_IWL<2107> A_IWL<2106> A_IWL<2105> A_IWL<2104> A_IWL<2103> A_IWL<2102> A_IWL<2101> A_IWL<2100> A_IWL<2099> A_IWL<2098> A_IWL<2097> A_IWL<2096> A_IWL<2095> A_IWL<2094> A_IWL<2093> A_IWL<2092> A_IWL<2091> A_IWL<2090> A_IWL<2089> A_IWL<2088> A_IWL<2087> A_IWL<2086> A_IWL<2085> A_IWL<2084> A_IWL<2083> A_IWL<2082> A_IWL<2081> A_IWL<2080> A_IWL<2079> A_IWL<2078> A_IWL<2077> A_IWL<2076> A_IWL<2075> A_IWL<2074> A_IWL<2073> A_IWL<2072> A_IWL<2071> A_IWL<2070> A_IWL<2069> A_IWL<2068> A_IWL<2067> A_IWL<2066> A_IWL<2065> A_IWL<2064> A_IWL<2063> A_IWL<2062> A_IWL<2061> A_IWL<2060> A_IWL<2059> A_IWL<2058> A_IWL<2057> A_IWL<2056> A_IWL<2055> A_IWL<2054> A_IWL<2053> A_IWL<2052> A_IWL<2051> A_IWL<2050> A_IWL<2049> A_IWL<2048> B_BLC<17> B_BLC<16> B_BLC_TOP<17> B_BLC_TOP<16> B_BLT<17> B_BLT<16> B_BLT_TOP<17> B_BLT_TOP<16> B_IWL<2047> B_IWL<2046> B_IWL<2045> B_IWL<2044> B_IWL<2043> B_IWL<2042> B_IWL<2041> B_IWL<2040> B_IWL<2039> B_IWL<2038> B_IWL<2037> B_IWL<2036> B_IWL<2035> B_IWL<2034> B_IWL<2033> B_IWL<2032> B_IWL<2031> B_IWL<2030> B_IWL<2029> B_IWL<2028> B_IWL<2027> B_IWL<2026> B_IWL<2025> B_IWL<2024> B_IWL<2023> B_IWL<2022> B_IWL<2021> B_IWL<2020> B_IWL<2019> B_IWL<2018> B_IWL<2017> B_IWL<2016> B_IWL<2015> B_IWL<2014> B_IWL<2013> B_IWL<2012> B_IWL<2011> B_IWL<2010> B_IWL<2009> B_IWL<2008> B_IWL<2007> B_IWL<2006> B_IWL<2005> B_IWL<2004> B_IWL<2003> B_IWL<2002> B_IWL<2001> B_IWL<2000> B_IWL<1999> B_IWL<1998> B_IWL<1997> B_IWL<1996> B_IWL<1995> B_IWL<1994> B_IWL<1993> B_IWL<1992> B_IWL<1991> B_IWL<1990> B_IWL<1989> B_IWL<1988> B_IWL<1987> B_IWL<1986> B_IWL<1985> B_IWL<1984> B_IWL<1983> B_IWL<1982> B_IWL<1981> B_IWL<1980> B_IWL<1979> B_IWL<1978> B_IWL<1977> B_IWL<1976> B_IWL<1975> B_IWL<1974> B_IWL<1973> B_IWL<1972> B_IWL<1971> B_IWL<1970> B_IWL<1969> B_IWL<1968> B_IWL<1967> B_IWL<1966> B_IWL<1965> B_IWL<1964> B_IWL<1963> B_IWL<1962> B_IWL<1961> B_IWL<1960> B_IWL<1959> B_IWL<1958> B_IWL<1957> B_IWL<1956> B_IWL<1955> B_IWL<1954> B_IWL<1953> B_IWL<1952> B_IWL<1951> B_IWL<1950> B_IWL<1949> B_IWL<1948> B_IWL<1947> B_IWL<1946> B_IWL<1945> B_IWL<1944> B_IWL<1943> B_IWL<1942> B_IWL<1941> B_IWL<1940> B_IWL<1939> B_IWL<1938> B_IWL<1937> B_IWL<1936> B_IWL<1935> B_IWL<1934> B_IWL<1933> B_IWL<1932> B_IWL<1931> B_IWL<1930> B_IWL<1929> B_IWL<1928> B_IWL<1927> B_IWL<1926> B_IWL<1925> B_IWL<1924> B_IWL<1923> B_IWL<1922> B_IWL<1921> B_IWL<1920> B_IWL<1919> B_IWL<1918> B_IWL<1917> B_IWL<1916> B_IWL<1915> B_IWL<1914> B_IWL<1913> B_IWL<1912> B_IWL<1911> B_IWL<1910> B_IWL<1909> B_IWL<1908> B_IWL<1907> B_IWL<1906> B_IWL<1905> B_IWL<1904> B_IWL<1903> B_IWL<1902> B_IWL<1901> B_IWL<1900> B_IWL<1899> B_IWL<1898> B_IWL<1897> B_IWL<1896> B_IWL<1895> B_IWL<1894> B_IWL<1893> B_IWL<1892> B_IWL<1891> B_IWL<1890> B_IWL<1889> B_IWL<1888> B_IWL<1887> B_IWL<1886> B_IWL<1885> B_IWL<1884> B_IWL<1883> B_IWL<1882> B_IWL<1881> B_IWL<1880> B_IWL<1879> B_IWL<1878> B_IWL<1877> B_IWL<1876> B_IWL<1875> B_IWL<1874> B_IWL<1873> B_IWL<1872> B_IWL<1871> B_IWL<1870> B_IWL<1869> B_IWL<1868> B_IWL<1867> B_IWL<1866> B_IWL<1865> B_IWL<1864> B_IWL<1863> B_IWL<1862> B_IWL<1861> B_IWL<1860> B_IWL<1859> B_IWL<1858> B_IWL<1857> B_IWL<1856> B_IWL<1855> B_IWL<1854> B_IWL<1853> B_IWL<1852> B_IWL<1851> B_IWL<1850> B_IWL<1849> B_IWL<1848> B_IWL<1847> B_IWL<1846> B_IWL<1845> B_IWL<1844> B_IWL<1843> B_IWL<1842> B_IWL<1841> B_IWL<1840> B_IWL<1839> B_IWL<1838> B_IWL<1837> B_IWL<1836> B_IWL<1835> B_IWL<1834> B_IWL<1833> B_IWL<1832> B_IWL<1831> B_IWL<1830> B_IWL<1829> B_IWL<1828> B_IWL<1827> B_IWL<1826> B_IWL<1825> B_IWL<1824> B_IWL<1823> B_IWL<1822> B_IWL<1821> B_IWL<1820> B_IWL<1819> B_IWL<1818> B_IWL<1817> B_IWL<1816> B_IWL<1815> B_IWL<1814> B_IWL<1813> B_IWL<1812> B_IWL<1811> B_IWL<1810> B_IWL<1809> B_IWL<1808> B_IWL<1807> B_IWL<1806> B_IWL<1805> B_IWL<1804> B_IWL<1803> B_IWL<1802> B_IWL<1801> B_IWL<1800> B_IWL<1799> B_IWL<1798> B_IWL<1797> B_IWL<1796> B_IWL<1795> B_IWL<1794> B_IWL<1793> B_IWL<1792> B_IWL<2303> B_IWL<2302> B_IWL<2301> B_IWL<2300> B_IWL<2299> B_IWL<2298> B_IWL<2297> B_IWL<2296> B_IWL<2295> B_IWL<2294> B_IWL<2293> B_IWL<2292> B_IWL<2291> B_IWL<2290> B_IWL<2289> B_IWL<2288> B_IWL<2287> B_IWL<2286> B_IWL<2285> B_IWL<2284> B_IWL<2283> B_IWL<2282> B_IWL<2281> B_IWL<2280> B_IWL<2279> B_IWL<2278> B_IWL<2277> B_IWL<2276> B_IWL<2275> B_IWL<2274> B_IWL<2273> B_IWL<2272> B_IWL<2271> B_IWL<2270> B_IWL<2269> B_IWL<2268> B_IWL<2267> B_IWL<2266> B_IWL<2265> B_IWL<2264> B_IWL<2263> B_IWL<2262> B_IWL<2261> B_IWL<2260> B_IWL<2259> B_IWL<2258> B_IWL<2257> B_IWL<2256> B_IWL<2255> B_IWL<2254> B_IWL<2253> B_IWL<2252> B_IWL<2251> B_IWL<2250> B_IWL<2249> B_IWL<2248> B_IWL<2247> B_IWL<2246> B_IWL<2245> B_IWL<2244> B_IWL<2243> B_IWL<2242> B_IWL<2241> B_IWL<2240> B_IWL<2239> B_IWL<2238> B_IWL<2237> B_IWL<2236> B_IWL<2235> B_IWL<2234> B_IWL<2233> B_IWL<2232> B_IWL<2231> B_IWL<2230> B_IWL<2229> B_IWL<2228> B_IWL<2227> B_IWL<2226> B_IWL<2225> B_IWL<2224> B_IWL<2223> B_IWL<2222> B_IWL<2221> B_IWL<2220> B_IWL<2219> B_IWL<2218> B_IWL<2217> B_IWL<2216> B_IWL<2215> B_IWL<2214> B_IWL<2213> B_IWL<2212> B_IWL<2211> B_IWL<2210> B_IWL<2209> B_IWL<2208> B_IWL<2207> B_IWL<2206> B_IWL<2205> B_IWL<2204> B_IWL<2203> B_IWL<2202> B_IWL<2201> B_IWL<2200> B_IWL<2199> B_IWL<2198> B_IWL<2197> B_IWL<2196> B_IWL<2195> B_IWL<2194> B_IWL<2193> B_IWL<2192> B_IWL<2191> B_IWL<2190> B_IWL<2189> B_IWL<2188> B_IWL<2187> B_IWL<2186> B_IWL<2185> B_IWL<2184> B_IWL<2183> B_IWL<2182> B_IWL<2181> B_IWL<2180> B_IWL<2179> B_IWL<2178> B_IWL<2177> B_IWL<2176> B_IWL<2175> B_IWL<2174> B_IWL<2173> B_IWL<2172> B_IWL<2171> B_IWL<2170> B_IWL<2169> B_IWL<2168> B_IWL<2167> B_IWL<2166> B_IWL<2165> B_IWL<2164> B_IWL<2163> B_IWL<2162> B_IWL<2161> B_IWL<2160> B_IWL<2159> B_IWL<2158> B_IWL<2157> B_IWL<2156> B_IWL<2155> B_IWL<2154> B_IWL<2153> B_IWL<2152> B_IWL<2151> B_IWL<2150> B_IWL<2149> B_IWL<2148> B_IWL<2147> B_IWL<2146> B_IWL<2145> B_IWL<2144> B_IWL<2143> B_IWL<2142> B_IWL<2141> B_IWL<2140> B_IWL<2139> B_IWL<2138> B_IWL<2137> B_IWL<2136> B_IWL<2135> B_IWL<2134> B_IWL<2133> B_IWL<2132> B_IWL<2131> B_IWL<2130> B_IWL<2129> B_IWL<2128> B_IWL<2127> B_IWL<2126> B_IWL<2125> B_IWL<2124> B_IWL<2123> B_IWL<2122> B_IWL<2121> B_IWL<2120> B_IWL<2119> B_IWL<2118> B_IWL<2117> B_IWL<2116> B_IWL<2115> B_IWL<2114> B_IWL<2113> B_IWL<2112> B_IWL<2111> B_IWL<2110> B_IWL<2109> B_IWL<2108> B_IWL<2107> B_IWL<2106> B_IWL<2105> B_IWL<2104> B_IWL<2103> B_IWL<2102> B_IWL<2101> B_IWL<2100> B_IWL<2099> B_IWL<2098> B_IWL<2097> B_IWL<2096> B_IWL<2095> B_IWL<2094> B_IWL<2093> B_IWL<2092> B_IWL<2091> B_IWL<2090> B_IWL<2089> B_IWL<2088> B_IWL<2087> B_IWL<2086> B_IWL<2085> B_IWL<2084> B_IWL<2083> B_IWL<2082> B_IWL<2081> B_IWL<2080> B_IWL<2079> B_IWL<2078> B_IWL<2077> B_IWL<2076> B_IWL<2075> B_IWL<2074> B_IWL<2073> B_IWL<2072> B_IWL<2071> B_IWL<2070> B_IWL<2069> B_IWL<2068> B_IWL<2067> B_IWL<2066> B_IWL<2065> B_IWL<2064> B_IWL<2063> B_IWL<2062> B_IWL<2061> B_IWL<2060> B_IWL<2059> B_IWL<2058> B_IWL<2057> B_IWL<2056> B_IWL<2055> B_IWL<2054> B_IWL<2053> B_IWL<2052> B_IWL<2051> B_IWL<2050> B_IWL<2049> B_IWL<2048> VDD_CORE VSS / RM_IHPSG13_1024x16_c2_2P_COLUMN_pcell_0 +XCOL<7> A_BLC<15> A_BLC<14> A_BLC_TOP<15> A_BLC_TOP<14> A_BLT<15> A_BLT<14> A_BLT_TOP<15> A_BLT_TOP<14> A_IWL<1791> A_IWL<1790> A_IWL<1789> A_IWL<1788> A_IWL<1787> A_IWL<1786> A_IWL<1785> A_IWL<1784> A_IWL<1783> A_IWL<1782> A_IWL<1781> A_IWL<1780> A_IWL<1779> A_IWL<1778> A_IWL<1777> A_IWL<1776> A_IWL<1775> A_IWL<1774> A_IWL<1773> A_IWL<1772> A_IWL<1771> A_IWL<1770> A_IWL<1769> A_IWL<1768> A_IWL<1767> A_IWL<1766> A_IWL<1765> A_IWL<1764> A_IWL<1763> A_IWL<1762> A_IWL<1761> A_IWL<1760> A_IWL<1759> A_IWL<1758> A_IWL<1757> A_IWL<1756> A_IWL<1755> A_IWL<1754> A_IWL<1753> A_IWL<1752> A_IWL<1751> A_IWL<1750> A_IWL<1749> A_IWL<1748> A_IWL<1747> A_IWL<1746> A_IWL<1745> A_IWL<1744> A_IWL<1743> A_IWL<1742> A_IWL<1741> A_IWL<1740> A_IWL<1739> A_IWL<1738> A_IWL<1737> A_IWL<1736> A_IWL<1735> A_IWL<1734> A_IWL<1733> A_IWL<1732> A_IWL<1731> A_IWL<1730> A_IWL<1729> A_IWL<1728> A_IWL<1727> A_IWL<1726> A_IWL<1725> A_IWL<1724> A_IWL<1723> A_IWL<1722> A_IWL<1721> A_IWL<1720> A_IWL<1719> A_IWL<1718> A_IWL<1717> A_IWL<1716> A_IWL<1715> A_IWL<1714> A_IWL<1713> A_IWL<1712> A_IWL<1711> A_IWL<1710> A_IWL<1709> A_IWL<1708> A_IWL<1707> A_IWL<1706> A_IWL<1705> A_IWL<1704> A_IWL<1703> A_IWL<1702> A_IWL<1701> A_IWL<1700> A_IWL<1699> A_IWL<1698> A_IWL<1697> A_IWL<1696> A_IWL<1695> A_IWL<1694> A_IWL<1693> A_IWL<1692> A_IWL<1691> A_IWL<1690> A_IWL<1689> A_IWL<1688> A_IWL<1687> A_IWL<1686> A_IWL<1685> A_IWL<1684> A_IWL<1683> A_IWL<1682> A_IWL<1681> A_IWL<1680> A_IWL<1679> A_IWL<1678> A_IWL<1677> A_IWL<1676> A_IWL<1675> A_IWL<1674> A_IWL<1673> A_IWL<1672> A_IWL<1671> A_IWL<1670> A_IWL<1669> A_IWL<1668> A_IWL<1667> A_IWL<1666> A_IWL<1665> A_IWL<1664> A_IWL<1663> A_IWL<1662> A_IWL<1661> A_IWL<1660> A_IWL<1659> A_IWL<1658> A_IWL<1657> A_IWL<1656> A_IWL<1655> A_IWL<1654> A_IWL<1653> A_IWL<1652> A_IWL<1651> A_IWL<1650> A_IWL<1649> A_IWL<1648> A_IWL<1647> A_IWL<1646> A_IWL<1645> A_IWL<1644> A_IWL<1643> A_IWL<1642> A_IWL<1641> A_IWL<1640> A_IWL<1639> A_IWL<1638> A_IWL<1637> A_IWL<1636> A_IWL<1635> A_IWL<1634> A_IWL<1633> A_IWL<1632> A_IWL<1631> A_IWL<1630> A_IWL<1629> A_IWL<1628> A_IWL<1627> A_IWL<1626> A_IWL<1625> A_IWL<1624> A_IWL<1623> A_IWL<1622> A_IWL<1621> A_IWL<1620> A_IWL<1619> A_IWL<1618> A_IWL<1617> A_IWL<1616> A_IWL<1615> A_IWL<1614> A_IWL<1613> A_IWL<1612> A_IWL<1611> A_IWL<1610> A_IWL<1609> A_IWL<1608> A_IWL<1607> A_IWL<1606> A_IWL<1605> A_IWL<1604> A_IWL<1603> A_IWL<1602> A_IWL<1601> A_IWL<1600> A_IWL<1599> A_IWL<1598> A_IWL<1597> A_IWL<1596> A_IWL<1595> A_IWL<1594> A_IWL<1593> A_IWL<1592> A_IWL<1591> A_IWL<1590> A_IWL<1589> A_IWL<1588> A_IWL<1587> A_IWL<1586> A_IWL<1585> A_IWL<1584> A_IWL<1583> A_IWL<1582> A_IWL<1581> A_IWL<1580> A_IWL<1579> A_IWL<1578> A_IWL<1577> A_IWL<1576> A_IWL<1575> A_IWL<1574> A_IWL<1573> A_IWL<1572> A_IWL<1571> A_IWL<1570> A_IWL<1569> A_IWL<1568> A_IWL<1567> A_IWL<1566> A_IWL<1565> A_IWL<1564> A_IWL<1563> A_IWL<1562> A_IWL<1561> A_IWL<1560> A_IWL<1559> A_IWL<1558> A_IWL<1557> A_IWL<1556> A_IWL<1555> A_IWL<1554> A_IWL<1553> A_IWL<1552> A_IWL<1551> A_IWL<1550> A_IWL<1549> A_IWL<1548> A_IWL<1547> A_IWL<1546> A_IWL<1545> A_IWL<1544> A_IWL<1543> A_IWL<1542> A_IWL<1541> A_IWL<1540> A_IWL<1539> A_IWL<1538> A_IWL<1537> A_IWL<1536> A_IWL<2047> A_IWL<2046> A_IWL<2045> A_IWL<2044> A_IWL<2043> A_IWL<2042> A_IWL<2041> A_IWL<2040> A_IWL<2039> A_IWL<2038> A_IWL<2037> A_IWL<2036> A_IWL<2035> A_IWL<2034> A_IWL<2033> A_IWL<2032> A_IWL<2031> A_IWL<2030> A_IWL<2029> A_IWL<2028> A_IWL<2027> A_IWL<2026> A_IWL<2025> A_IWL<2024> A_IWL<2023> A_IWL<2022> A_IWL<2021> A_IWL<2020> A_IWL<2019> A_IWL<2018> A_IWL<2017> A_IWL<2016> A_IWL<2015> A_IWL<2014> A_IWL<2013> A_IWL<2012> A_IWL<2011> A_IWL<2010> A_IWL<2009> A_IWL<2008> A_IWL<2007> A_IWL<2006> A_IWL<2005> A_IWL<2004> A_IWL<2003> A_IWL<2002> A_IWL<2001> A_IWL<2000> A_IWL<1999> A_IWL<1998> A_IWL<1997> A_IWL<1996> A_IWL<1995> A_IWL<1994> A_IWL<1993> A_IWL<1992> A_IWL<1991> A_IWL<1990> A_IWL<1989> A_IWL<1988> A_IWL<1987> A_IWL<1986> A_IWL<1985> A_IWL<1984> A_IWL<1983> A_IWL<1982> A_IWL<1981> A_IWL<1980> A_IWL<1979> A_IWL<1978> A_IWL<1977> A_IWL<1976> A_IWL<1975> A_IWL<1974> A_IWL<1973> A_IWL<1972> A_IWL<1971> A_IWL<1970> A_IWL<1969> A_IWL<1968> A_IWL<1967> A_IWL<1966> A_IWL<1965> A_IWL<1964> A_IWL<1963> A_IWL<1962> A_IWL<1961> A_IWL<1960> A_IWL<1959> A_IWL<1958> A_IWL<1957> A_IWL<1956> A_IWL<1955> A_IWL<1954> A_IWL<1953> A_IWL<1952> A_IWL<1951> A_IWL<1950> A_IWL<1949> A_IWL<1948> A_IWL<1947> A_IWL<1946> A_IWL<1945> A_IWL<1944> A_IWL<1943> A_IWL<1942> A_IWL<1941> A_IWL<1940> A_IWL<1939> A_IWL<1938> A_IWL<1937> A_IWL<1936> A_IWL<1935> A_IWL<1934> A_IWL<1933> A_IWL<1932> A_IWL<1931> A_IWL<1930> A_IWL<1929> A_IWL<1928> A_IWL<1927> A_IWL<1926> A_IWL<1925> A_IWL<1924> A_IWL<1923> A_IWL<1922> A_IWL<1921> A_IWL<1920> A_IWL<1919> A_IWL<1918> A_IWL<1917> A_IWL<1916> A_IWL<1915> A_IWL<1914> A_IWL<1913> A_IWL<1912> A_IWL<1911> A_IWL<1910> A_IWL<1909> A_IWL<1908> A_IWL<1907> A_IWL<1906> A_IWL<1905> A_IWL<1904> A_IWL<1903> A_IWL<1902> A_IWL<1901> A_IWL<1900> A_IWL<1899> A_IWL<1898> A_IWL<1897> A_IWL<1896> A_IWL<1895> A_IWL<1894> A_IWL<1893> A_IWL<1892> A_IWL<1891> A_IWL<1890> A_IWL<1889> A_IWL<1888> A_IWL<1887> A_IWL<1886> A_IWL<1885> A_IWL<1884> A_IWL<1883> A_IWL<1882> A_IWL<1881> A_IWL<1880> A_IWL<1879> A_IWL<1878> A_IWL<1877> A_IWL<1876> A_IWL<1875> A_IWL<1874> A_IWL<1873> A_IWL<1872> A_IWL<1871> A_IWL<1870> A_IWL<1869> A_IWL<1868> A_IWL<1867> A_IWL<1866> A_IWL<1865> A_IWL<1864> A_IWL<1863> A_IWL<1862> A_IWL<1861> A_IWL<1860> A_IWL<1859> A_IWL<1858> A_IWL<1857> A_IWL<1856> A_IWL<1855> A_IWL<1854> A_IWL<1853> A_IWL<1852> A_IWL<1851> A_IWL<1850> A_IWL<1849> A_IWL<1848> A_IWL<1847> A_IWL<1846> A_IWL<1845> A_IWL<1844> A_IWL<1843> A_IWL<1842> A_IWL<1841> A_IWL<1840> A_IWL<1839> A_IWL<1838> A_IWL<1837> A_IWL<1836> A_IWL<1835> A_IWL<1834> A_IWL<1833> A_IWL<1832> A_IWL<1831> A_IWL<1830> A_IWL<1829> A_IWL<1828> A_IWL<1827> A_IWL<1826> A_IWL<1825> A_IWL<1824> A_IWL<1823> A_IWL<1822> A_IWL<1821> A_IWL<1820> A_IWL<1819> A_IWL<1818> A_IWL<1817> A_IWL<1816> A_IWL<1815> A_IWL<1814> A_IWL<1813> A_IWL<1812> A_IWL<1811> A_IWL<1810> A_IWL<1809> A_IWL<1808> A_IWL<1807> A_IWL<1806> A_IWL<1805> A_IWL<1804> A_IWL<1803> A_IWL<1802> A_IWL<1801> A_IWL<1800> A_IWL<1799> A_IWL<1798> A_IWL<1797> A_IWL<1796> A_IWL<1795> A_IWL<1794> A_IWL<1793> A_IWL<1792> B_BLC<15> B_BLC<14> B_BLC_TOP<15> B_BLC_TOP<14> B_BLT<15> B_BLT<14> B_BLT_TOP<15> B_BLT_TOP<14> B_IWL<1791> B_IWL<1790> B_IWL<1789> B_IWL<1788> B_IWL<1787> B_IWL<1786> B_IWL<1785> B_IWL<1784> B_IWL<1783> B_IWL<1782> B_IWL<1781> B_IWL<1780> B_IWL<1779> B_IWL<1778> B_IWL<1777> B_IWL<1776> B_IWL<1775> B_IWL<1774> B_IWL<1773> B_IWL<1772> B_IWL<1771> B_IWL<1770> B_IWL<1769> B_IWL<1768> B_IWL<1767> B_IWL<1766> B_IWL<1765> B_IWL<1764> B_IWL<1763> B_IWL<1762> B_IWL<1761> B_IWL<1760> B_IWL<1759> B_IWL<1758> B_IWL<1757> B_IWL<1756> B_IWL<1755> B_IWL<1754> B_IWL<1753> B_IWL<1752> B_IWL<1751> B_IWL<1750> B_IWL<1749> B_IWL<1748> B_IWL<1747> B_IWL<1746> B_IWL<1745> B_IWL<1744> B_IWL<1743> B_IWL<1742> B_IWL<1741> B_IWL<1740> B_IWL<1739> B_IWL<1738> B_IWL<1737> B_IWL<1736> B_IWL<1735> B_IWL<1734> B_IWL<1733> B_IWL<1732> B_IWL<1731> B_IWL<1730> B_IWL<1729> B_IWL<1728> B_IWL<1727> B_IWL<1726> B_IWL<1725> B_IWL<1724> B_IWL<1723> B_IWL<1722> B_IWL<1721> B_IWL<1720> B_IWL<1719> B_IWL<1718> B_IWL<1717> B_IWL<1716> B_IWL<1715> B_IWL<1714> B_IWL<1713> B_IWL<1712> B_IWL<1711> B_IWL<1710> B_IWL<1709> B_IWL<1708> B_IWL<1707> B_IWL<1706> B_IWL<1705> B_IWL<1704> B_IWL<1703> B_IWL<1702> B_IWL<1701> B_IWL<1700> B_IWL<1699> B_IWL<1698> B_IWL<1697> B_IWL<1696> B_IWL<1695> B_IWL<1694> B_IWL<1693> B_IWL<1692> B_IWL<1691> B_IWL<1690> B_IWL<1689> B_IWL<1688> B_IWL<1687> B_IWL<1686> B_IWL<1685> B_IWL<1684> B_IWL<1683> B_IWL<1682> B_IWL<1681> B_IWL<1680> B_IWL<1679> B_IWL<1678> B_IWL<1677> B_IWL<1676> B_IWL<1675> B_IWL<1674> B_IWL<1673> B_IWL<1672> B_IWL<1671> B_IWL<1670> B_IWL<1669> B_IWL<1668> B_IWL<1667> B_IWL<1666> B_IWL<1665> B_IWL<1664> B_IWL<1663> B_IWL<1662> B_IWL<1661> B_IWL<1660> B_IWL<1659> B_IWL<1658> B_IWL<1657> B_IWL<1656> B_IWL<1655> B_IWL<1654> B_IWL<1653> B_IWL<1652> B_IWL<1651> B_IWL<1650> B_IWL<1649> B_IWL<1648> B_IWL<1647> B_IWL<1646> B_IWL<1645> B_IWL<1644> B_IWL<1643> B_IWL<1642> B_IWL<1641> B_IWL<1640> B_IWL<1639> B_IWL<1638> B_IWL<1637> B_IWL<1636> B_IWL<1635> B_IWL<1634> B_IWL<1633> B_IWL<1632> B_IWL<1631> B_IWL<1630> B_IWL<1629> B_IWL<1628> B_IWL<1627> B_IWL<1626> B_IWL<1625> B_IWL<1624> B_IWL<1623> B_IWL<1622> B_IWL<1621> B_IWL<1620> B_IWL<1619> B_IWL<1618> B_IWL<1617> B_IWL<1616> B_IWL<1615> B_IWL<1614> B_IWL<1613> B_IWL<1612> B_IWL<1611> B_IWL<1610> B_IWL<1609> B_IWL<1608> B_IWL<1607> B_IWL<1606> B_IWL<1605> B_IWL<1604> B_IWL<1603> B_IWL<1602> B_IWL<1601> B_IWL<1600> B_IWL<1599> B_IWL<1598> B_IWL<1597> B_IWL<1596> B_IWL<1595> B_IWL<1594> B_IWL<1593> B_IWL<1592> B_IWL<1591> B_IWL<1590> B_IWL<1589> B_IWL<1588> B_IWL<1587> B_IWL<1586> B_IWL<1585> B_IWL<1584> B_IWL<1583> B_IWL<1582> B_IWL<1581> B_IWL<1580> B_IWL<1579> B_IWL<1578> B_IWL<1577> B_IWL<1576> B_IWL<1575> B_IWL<1574> B_IWL<1573> B_IWL<1572> B_IWL<1571> B_IWL<1570> B_IWL<1569> B_IWL<1568> B_IWL<1567> B_IWL<1566> B_IWL<1565> B_IWL<1564> B_IWL<1563> B_IWL<1562> B_IWL<1561> B_IWL<1560> B_IWL<1559> B_IWL<1558> B_IWL<1557> B_IWL<1556> B_IWL<1555> B_IWL<1554> B_IWL<1553> B_IWL<1552> B_IWL<1551> B_IWL<1550> B_IWL<1549> B_IWL<1548> B_IWL<1547> B_IWL<1546> B_IWL<1545> B_IWL<1544> B_IWL<1543> B_IWL<1542> B_IWL<1541> B_IWL<1540> B_IWL<1539> B_IWL<1538> B_IWL<1537> B_IWL<1536> B_IWL<2047> B_IWL<2046> B_IWL<2045> B_IWL<2044> B_IWL<2043> B_IWL<2042> B_IWL<2041> B_IWL<2040> B_IWL<2039> B_IWL<2038> B_IWL<2037> B_IWL<2036> B_IWL<2035> B_IWL<2034> B_IWL<2033> B_IWL<2032> B_IWL<2031> B_IWL<2030> B_IWL<2029> B_IWL<2028> B_IWL<2027> B_IWL<2026> B_IWL<2025> B_IWL<2024> B_IWL<2023> B_IWL<2022> B_IWL<2021> B_IWL<2020> B_IWL<2019> B_IWL<2018> B_IWL<2017> B_IWL<2016> B_IWL<2015> B_IWL<2014> B_IWL<2013> B_IWL<2012> B_IWL<2011> B_IWL<2010> B_IWL<2009> B_IWL<2008> B_IWL<2007> B_IWL<2006> B_IWL<2005> B_IWL<2004> B_IWL<2003> B_IWL<2002> B_IWL<2001> B_IWL<2000> B_IWL<1999> B_IWL<1998> B_IWL<1997> B_IWL<1996> B_IWL<1995> B_IWL<1994> B_IWL<1993> B_IWL<1992> B_IWL<1991> B_IWL<1990> B_IWL<1989> B_IWL<1988> B_IWL<1987> B_IWL<1986> B_IWL<1985> B_IWL<1984> B_IWL<1983> B_IWL<1982> B_IWL<1981> B_IWL<1980> B_IWL<1979> B_IWL<1978> B_IWL<1977> B_IWL<1976> B_IWL<1975> B_IWL<1974> B_IWL<1973> B_IWL<1972> B_IWL<1971> B_IWL<1970> B_IWL<1969> B_IWL<1968> B_IWL<1967> B_IWL<1966> B_IWL<1965> B_IWL<1964> B_IWL<1963> B_IWL<1962> B_IWL<1961> B_IWL<1960> B_IWL<1959> B_IWL<1958> B_IWL<1957> B_IWL<1956> B_IWL<1955> B_IWL<1954> B_IWL<1953> B_IWL<1952> B_IWL<1951> B_IWL<1950> B_IWL<1949> B_IWL<1948> B_IWL<1947> B_IWL<1946> B_IWL<1945> B_IWL<1944> B_IWL<1943> B_IWL<1942> B_IWL<1941> B_IWL<1940> B_IWL<1939> B_IWL<1938> B_IWL<1937> B_IWL<1936> B_IWL<1935> B_IWL<1934> B_IWL<1933> B_IWL<1932> B_IWL<1931> B_IWL<1930> B_IWL<1929> B_IWL<1928> B_IWL<1927> B_IWL<1926> B_IWL<1925> B_IWL<1924> B_IWL<1923> B_IWL<1922> B_IWL<1921> B_IWL<1920> B_IWL<1919> B_IWL<1918> B_IWL<1917> B_IWL<1916> B_IWL<1915> B_IWL<1914> B_IWL<1913> B_IWL<1912> B_IWL<1911> B_IWL<1910> B_IWL<1909> B_IWL<1908> B_IWL<1907> B_IWL<1906> B_IWL<1905> B_IWL<1904> B_IWL<1903> B_IWL<1902> B_IWL<1901> B_IWL<1900> B_IWL<1899> B_IWL<1898> B_IWL<1897> B_IWL<1896> B_IWL<1895> B_IWL<1894> B_IWL<1893> B_IWL<1892> B_IWL<1891> B_IWL<1890> B_IWL<1889> B_IWL<1888> B_IWL<1887> B_IWL<1886> B_IWL<1885> B_IWL<1884> B_IWL<1883> B_IWL<1882> B_IWL<1881> B_IWL<1880> B_IWL<1879> B_IWL<1878> B_IWL<1877> B_IWL<1876> B_IWL<1875> B_IWL<1874> B_IWL<1873> B_IWL<1872> B_IWL<1871> B_IWL<1870> B_IWL<1869> B_IWL<1868> B_IWL<1867> B_IWL<1866> B_IWL<1865> B_IWL<1864> B_IWL<1863> B_IWL<1862> B_IWL<1861> B_IWL<1860> B_IWL<1859> B_IWL<1858> B_IWL<1857> B_IWL<1856> B_IWL<1855> B_IWL<1854> B_IWL<1853> B_IWL<1852> B_IWL<1851> B_IWL<1850> B_IWL<1849> B_IWL<1848> B_IWL<1847> B_IWL<1846> B_IWL<1845> B_IWL<1844> B_IWL<1843> B_IWL<1842> B_IWL<1841> B_IWL<1840> B_IWL<1839> B_IWL<1838> B_IWL<1837> B_IWL<1836> B_IWL<1835> B_IWL<1834> B_IWL<1833> B_IWL<1832> B_IWL<1831> B_IWL<1830> B_IWL<1829> B_IWL<1828> B_IWL<1827> B_IWL<1826> B_IWL<1825> B_IWL<1824> B_IWL<1823> B_IWL<1822> B_IWL<1821> B_IWL<1820> B_IWL<1819> B_IWL<1818> B_IWL<1817> B_IWL<1816> B_IWL<1815> B_IWL<1814> B_IWL<1813> B_IWL<1812> B_IWL<1811> B_IWL<1810> B_IWL<1809> B_IWL<1808> B_IWL<1807> B_IWL<1806> B_IWL<1805> B_IWL<1804> B_IWL<1803> B_IWL<1802> B_IWL<1801> B_IWL<1800> B_IWL<1799> B_IWL<1798> B_IWL<1797> B_IWL<1796> B_IWL<1795> B_IWL<1794> B_IWL<1793> B_IWL<1792> VDD_CORE VSS / RM_IHPSG13_1024x16_c2_2P_COLUMN_pcell_0 +XCOL<6> A_BLC<13> A_BLC<12> A_BLC_TOP<13> A_BLC_TOP<12> A_BLT<13> A_BLT<12> A_BLT_TOP<13> A_BLT_TOP<12> A_IWL<1535> A_IWL<1534> A_IWL<1533> A_IWL<1532> A_IWL<1531> A_IWL<1530> A_IWL<1529> A_IWL<1528> A_IWL<1527> A_IWL<1526> A_IWL<1525> A_IWL<1524> A_IWL<1523> A_IWL<1522> A_IWL<1521> A_IWL<1520> A_IWL<1519> A_IWL<1518> A_IWL<1517> A_IWL<1516> A_IWL<1515> A_IWL<1514> A_IWL<1513> A_IWL<1512> A_IWL<1511> A_IWL<1510> A_IWL<1509> A_IWL<1508> A_IWL<1507> A_IWL<1506> A_IWL<1505> A_IWL<1504> A_IWL<1503> A_IWL<1502> A_IWL<1501> A_IWL<1500> A_IWL<1499> A_IWL<1498> A_IWL<1497> A_IWL<1496> A_IWL<1495> A_IWL<1494> A_IWL<1493> A_IWL<1492> A_IWL<1491> A_IWL<1490> A_IWL<1489> A_IWL<1488> A_IWL<1487> A_IWL<1486> A_IWL<1485> A_IWL<1484> A_IWL<1483> A_IWL<1482> A_IWL<1481> A_IWL<1480> A_IWL<1479> A_IWL<1478> A_IWL<1477> A_IWL<1476> A_IWL<1475> A_IWL<1474> A_IWL<1473> A_IWL<1472> A_IWL<1471> A_IWL<1470> A_IWL<1469> A_IWL<1468> A_IWL<1467> A_IWL<1466> A_IWL<1465> A_IWL<1464> A_IWL<1463> A_IWL<1462> A_IWL<1461> A_IWL<1460> A_IWL<1459> A_IWL<1458> A_IWL<1457> A_IWL<1456> A_IWL<1455> A_IWL<1454> A_IWL<1453> A_IWL<1452> A_IWL<1451> A_IWL<1450> A_IWL<1449> A_IWL<1448> A_IWL<1447> A_IWL<1446> A_IWL<1445> A_IWL<1444> A_IWL<1443> A_IWL<1442> A_IWL<1441> A_IWL<1440> A_IWL<1439> A_IWL<1438> A_IWL<1437> A_IWL<1436> A_IWL<1435> A_IWL<1434> A_IWL<1433> A_IWL<1432> A_IWL<1431> A_IWL<1430> A_IWL<1429> A_IWL<1428> A_IWL<1427> A_IWL<1426> A_IWL<1425> A_IWL<1424> A_IWL<1423> A_IWL<1422> A_IWL<1421> A_IWL<1420> A_IWL<1419> A_IWL<1418> A_IWL<1417> A_IWL<1416> A_IWL<1415> A_IWL<1414> A_IWL<1413> A_IWL<1412> A_IWL<1411> A_IWL<1410> A_IWL<1409> A_IWL<1408> A_IWL<1407> A_IWL<1406> A_IWL<1405> A_IWL<1404> A_IWL<1403> A_IWL<1402> A_IWL<1401> A_IWL<1400> A_IWL<1399> A_IWL<1398> A_IWL<1397> A_IWL<1396> A_IWL<1395> A_IWL<1394> A_IWL<1393> A_IWL<1392> A_IWL<1391> A_IWL<1390> A_IWL<1389> A_IWL<1388> A_IWL<1387> A_IWL<1386> A_IWL<1385> A_IWL<1384> A_IWL<1383> A_IWL<1382> A_IWL<1381> A_IWL<1380> A_IWL<1379> A_IWL<1378> A_IWL<1377> A_IWL<1376> A_IWL<1375> A_IWL<1374> A_IWL<1373> A_IWL<1372> A_IWL<1371> A_IWL<1370> A_IWL<1369> A_IWL<1368> A_IWL<1367> A_IWL<1366> A_IWL<1365> A_IWL<1364> A_IWL<1363> A_IWL<1362> A_IWL<1361> A_IWL<1360> A_IWL<1359> A_IWL<1358> A_IWL<1357> A_IWL<1356> A_IWL<1355> A_IWL<1354> A_IWL<1353> A_IWL<1352> A_IWL<1351> A_IWL<1350> A_IWL<1349> A_IWL<1348> A_IWL<1347> A_IWL<1346> A_IWL<1345> A_IWL<1344> A_IWL<1343> A_IWL<1342> A_IWL<1341> A_IWL<1340> A_IWL<1339> A_IWL<1338> A_IWL<1337> A_IWL<1336> A_IWL<1335> A_IWL<1334> A_IWL<1333> A_IWL<1332> A_IWL<1331> A_IWL<1330> A_IWL<1329> A_IWL<1328> A_IWL<1327> A_IWL<1326> A_IWL<1325> A_IWL<1324> A_IWL<1323> A_IWL<1322> A_IWL<1321> A_IWL<1320> A_IWL<1319> A_IWL<1318> A_IWL<1317> A_IWL<1316> A_IWL<1315> A_IWL<1314> A_IWL<1313> A_IWL<1312> A_IWL<1311> A_IWL<1310> A_IWL<1309> A_IWL<1308> A_IWL<1307> A_IWL<1306> A_IWL<1305> A_IWL<1304> A_IWL<1303> A_IWL<1302> A_IWL<1301> A_IWL<1300> A_IWL<1299> A_IWL<1298> A_IWL<1297> A_IWL<1296> A_IWL<1295> A_IWL<1294> A_IWL<1293> A_IWL<1292> A_IWL<1291> A_IWL<1290> A_IWL<1289> A_IWL<1288> A_IWL<1287> A_IWL<1286> A_IWL<1285> A_IWL<1284> A_IWL<1283> A_IWL<1282> A_IWL<1281> A_IWL<1280> A_IWL<1791> A_IWL<1790> A_IWL<1789> A_IWL<1788> A_IWL<1787> A_IWL<1786> A_IWL<1785> A_IWL<1784> A_IWL<1783> A_IWL<1782> A_IWL<1781> A_IWL<1780> A_IWL<1779> A_IWL<1778> A_IWL<1777> A_IWL<1776> A_IWL<1775> A_IWL<1774> A_IWL<1773> A_IWL<1772> A_IWL<1771> A_IWL<1770> A_IWL<1769> A_IWL<1768> A_IWL<1767> A_IWL<1766> A_IWL<1765> A_IWL<1764> A_IWL<1763> A_IWL<1762> A_IWL<1761> A_IWL<1760> A_IWL<1759> A_IWL<1758> A_IWL<1757> A_IWL<1756> A_IWL<1755> A_IWL<1754> A_IWL<1753> A_IWL<1752> A_IWL<1751> A_IWL<1750> A_IWL<1749> A_IWL<1748> A_IWL<1747> A_IWL<1746> A_IWL<1745> A_IWL<1744> A_IWL<1743> A_IWL<1742> A_IWL<1741> A_IWL<1740> A_IWL<1739> A_IWL<1738> A_IWL<1737> A_IWL<1736> A_IWL<1735> A_IWL<1734> A_IWL<1733> A_IWL<1732> A_IWL<1731> A_IWL<1730> A_IWL<1729> A_IWL<1728> A_IWL<1727> A_IWL<1726> A_IWL<1725> A_IWL<1724> A_IWL<1723> A_IWL<1722> A_IWL<1721> A_IWL<1720> A_IWL<1719> A_IWL<1718> A_IWL<1717> A_IWL<1716> A_IWL<1715> A_IWL<1714> A_IWL<1713> A_IWL<1712> A_IWL<1711> A_IWL<1710> A_IWL<1709> A_IWL<1708> A_IWL<1707> A_IWL<1706> A_IWL<1705> A_IWL<1704> A_IWL<1703> A_IWL<1702> A_IWL<1701> A_IWL<1700> A_IWL<1699> A_IWL<1698> A_IWL<1697> A_IWL<1696> A_IWL<1695> A_IWL<1694> A_IWL<1693> A_IWL<1692> A_IWL<1691> A_IWL<1690> A_IWL<1689> A_IWL<1688> A_IWL<1687> A_IWL<1686> A_IWL<1685> A_IWL<1684> A_IWL<1683> A_IWL<1682> A_IWL<1681> A_IWL<1680> A_IWL<1679> A_IWL<1678> A_IWL<1677> A_IWL<1676> A_IWL<1675> A_IWL<1674> A_IWL<1673> A_IWL<1672> A_IWL<1671> A_IWL<1670> A_IWL<1669> A_IWL<1668> A_IWL<1667> A_IWL<1666> A_IWL<1665> A_IWL<1664> A_IWL<1663> A_IWL<1662> A_IWL<1661> A_IWL<1660> A_IWL<1659> A_IWL<1658> A_IWL<1657> A_IWL<1656> A_IWL<1655> A_IWL<1654> A_IWL<1653> A_IWL<1652> A_IWL<1651> A_IWL<1650> A_IWL<1649> A_IWL<1648> A_IWL<1647> A_IWL<1646> A_IWL<1645> A_IWL<1644> A_IWL<1643> A_IWL<1642> A_IWL<1641> A_IWL<1640> A_IWL<1639> A_IWL<1638> A_IWL<1637> A_IWL<1636> A_IWL<1635> A_IWL<1634> A_IWL<1633> A_IWL<1632> A_IWL<1631> A_IWL<1630> A_IWL<1629> A_IWL<1628> A_IWL<1627> A_IWL<1626> A_IWL<1625> A_IWL<1624> A_IWL<1623> A_IWL<1622> A_IWL<1621> A_IWL<1620> A_IWL<1619> A_IWL<1618> A_IWL<1617> A_IWL<1616> A_IWL<1615> A_IWL<1614> A_IWL<1613> A_IWL<1612> A_IWL<1611> A_IWL<1610> A_IWL<1609> A_IWL<1608> A_IWL<1607> A_IWL<1606> A_IWL<1605> A_IWL<1604> A_IWL<1603> A_IWL<1602> A_IWL<1601> A_IWL<1600> A_IWL<1599> A_IWL<1598> A_IWL<1597> A_IWL<1596> A_IWL<1595> A_IWL<1594> A_IWL<1593> A_IWL<1592> A_IWL<1591> A_IWL<1590> A_IWL<1589> A_IWL<1588> A_IWL<1587> A_IWL<1586> A_IWL<1585> A_IWL<1584> A_IWL<1583> A_IWL<1582> A_IWL<1581> A_IWL<1580> A_IWL<1579> A_IWL<1578> A_IWL<1577> A_IWL<1576> A_IWL<1575> A_IWL<1574> A_IWL<1573> A_IWL<1572> A_IWL<1571> A_IWL<1570> A_IWL<1569> A_IWL<1568> A_IWL<1567> A_IWL<1566> A_IWL<1565> A_IWL<1564> A_IWL<1563> A_IWL<1562> A_IWL<1561> A_IWL<1560> A_IWL<1559> A_IWL<1558> A_IWL<1557> A_IWL<1556> A_IWL<1555> A_IWL<1554> A_IWL<1553> A_IWL<1552> A_IWL<1551> A_IWL<1550> A_IWL<1549> A_IWL<1548> A_IWL<1547> A_IWL<1546> A_IWL<1545> A_IWL<1544> A_IWL<1543> A_IWL<1542> A_IWL<1541> A_IWL<1540> A_IWL<1539> A_IWL<1538> A_IWL<1537> A_IWL<1536> B_BLC<13> B_BLC<12> B_BLC_TOP<13> B_BLC_TOP<12> B_BLT<13> B_BLT<12> B_BLT_TOP<13> B_BLT_TOP<12> B_IWL<1535> B_IWL<1534> B_IWL<1533> B_IWL<1532> B_IWL<1531> B_IWL<1530> B_IWL<1529> B_IWL<1528> B_IWL<1527> B_IWL<1526> B_IWL<1525> B_IWL<1524> B_IWL<1523> B_IWL<1522> B_IWL<1521> B_IWL<1520> B_IWL<1519> B_IWL<1518> B_IWL<1517> B_IWL<1516> B_IWL<1515> B_IWL<1514> B_IWL<1513> B_IWL<1512> B_IWL<1511> B_IWL<1510> B_IWL<1509> B_IWL<1508> B_IWL<1507> B_IWL<1506> B_IWL<1505> B_IWL<1504> B_IWL<1503> B_IWL<1502> B_IWL<1501> B_IWL<1500> B_IWL<1499> B_IWL<1498> B_IWL<1497> B_IWL<1496> B_IWL<1495> B_IWL<1494> B_IWL<1493> B_IWL<1492> B_IWL<1491> B_IWL<1490> B_IWL<1489> B_IWL<1488> B_IWL<1487> B_IWL<1486> B_IWL<1485> B_IWL<1484> B_IWL<1483> B_IWL<1482> B_IWL<1481> B_IWL<1480> B_IWL<1479> B_IWL<1478> B_IWL<1477> B_IWL<1476> B_IWL<1475> B_IWL<1474> B_IWL<1473> B_IWL<1472> B_IWL<1471> B_IWL<1470> B_IWL<1469> B_IWL<1468> B_IWL<1467> B_IWL<1466> B_IWL<1465> B_IWL<1464> B_IWL<1463> B_IWL<1462> B_IWL<1461> B_IWL<1460> B_IWL<1459> B_IWL<1458> B_IWL<1457> B_IWL<1456> B_IWL<1455> B_IWL<1454> B_IWL<1453> B_IWL<1452> B_IWL<1451> B_IWL<1450> B_IWL<1449> B_IWL<1448> B_IWL<1447> B_IWL<1446> B_IWL<1445> B_IWL<1444> B_IWL<1443> B_IWL<1442> B_IWL<1441> B_IWL<1440> B_IWL<1439> B_IWL<1438> B_IWL<1437> B_IWL<1436> B_IWL<1435> B_IWL<1434> B_IWL<1433> B_IWL<1432> B_IWL<1431> B_IWL<1430> B_IWL<1429> B_IWL<1428> B_IWL<1427> B_IWL<1426> B_IWL<1425> B_IWL<1424> B_IWL<1423> B_IWL<1422> B_IWL<1421> B_IWL<1420> B_IWL<1419> B_IWL<1418> B_IWL<1417> B_IWL<1416> B_IWL<1415> B_IWL<1414> B_IWL<1413> B_IWL<1412> B_IWL<1411> B_IWL<1410> B_IWL<1409> B_IWL<1408> B_IWL<1407> B_IWL<1406> B_IWL<1405> B_IWL<1404> B_IWL<1403> B_IWL<1402> B_IWL<1401> B_IWL<1400> B_IWL<1399> B_IWL<1398> B_IWL<1397> B_IWL<1396> B_IWL<1395> B_IWL<1394> B_IWL<1393> B_IWL<1392> B_IWL<1391> B_IWL<1390> B_IWL<1389> B_IWL<1388> B_IWL<1387> B_IWL<1386> B_IWL<1385> B_IWL<1384> B_IWL<1383> B_IWL<1382> B_IWL<1381> B_IWL<1380> B_IWL<1379> B_IWL<1378> B_IWL<1377> B_IWL<1376> B_IWL<1375> B_IWL<1374> B_IWL<1373> B_IWL<1372> B_IWL<1371> B_IWL<1370> B_IWL<1369> B_IWL<1368> B_IWL<1367> B_IWL<1366> B_IWL<1365> B_IWL<1364> B_IWL<1363> B_IWL<1362> B_IWL<1361> B_IWL<1360> B_IWL<1359> B_IWL<1358> B_IWL<1357> B_IWL<1356> B_IWL<1355> B_IWL<1354> B_IWL<1353> B_IWL<1352> B_IWL<1351> B_IWL<1350> B_IWL<1349> B_IWL<1348> B_IWL<1347> B_IWL<1346> B_IWL<1345> B_IWL<1344> B_IWL<1343> B_IWL<1342> B_IWL<1341> B_IWL<1340> B_IWL<1339> B_IWL<1338> B_IWL<1337> B_IWL<1336> B_IWL<1335> B_IWL<1334> B_IWL<1333> B_IWL<1332> B_IWL<1331> B_IWL<1330> B_IWL<1329> B_IWL<1328> B_IWL<1327> B_IWL<1326> B_IWL<1325> B_IWL<1324> B_IWL<1323> B_IWL<1322> B_IWL<1321> B_IWL<1320> B_IWL<1319> B_IWL<1318> B_IWL<1317> B_IWL<1316> B_IWL<1315> B_IWL<1314> B_IWL<1313> B_IWL<1312> B_IWL<1311> B_IWL<1310> B_IWL<1309> B_IWL<1308> B_IWL<1307> B_IWL<1306> B_IWL<1305> B_IWL<1304> B_IWL<1303> B_IWL<1302> B_IWL<1301> B_IWL<1300> B_IWL<1299> B_IWL<1298> B_IWL<1297> B_IWL<1296> B_IWL<1295> B_IWL<1294> B_IWL<1293> B_IWL<1292> B_IWL<1291> B_IWL<1290> B_IWL<1289> B_IWL<1288> B_IWL<1287> B_IWL<1286> B_IWL<1285> B_IWL<1284> B_IWL<1283> B_IWL<1282> B_IWL<1281> B_IWL<1280> B_IWL<1791> B_IWL<1790> B_IWL<1789> B_IWL<1788> B_IWL<1787> B_IWL<1786> B_IWL<1785> B_IWL<1784> B_IWL<1783> B_IWL<1782> B_IWL<1781> B_IWL<1780> B_IWL<1779> B_IWL<1778> B_IWL<1777> B_IWL<1776> B_IWL<1775> B_IWL<1774> B_IWL<1773> B_IWL<1772> B_IWL<1771> B_IWL<1770> B_IWL<1769> B_IWL<1768> B_IWL<1767> B_IWL<1766> B_IWL<1765> B_IWL<1764> B_IWL<1763> B_IWL<1762> B_IWL<1761> B_IWL<1760> B_IWL<1759> B_IWL<1758> B_IWL<1757> B_IWL<1756> B_IWL<1755> B_IWL<1754> B_IWL<1753> B_IWL<1752> B_IWL<1751> B_IWL<1750> B_IWL<1749> B_IWL<1748> B_IWL<1747> B_IWL<1746> B_IWL<1745> B_IWL<1744> B_IWL<1743> B_IWL<1742> B_IWL<1741> B_IWL<1740> B_IWL<1739> B_IWL<1738> B_IWL<1737> B_IWL<1736> B_IWL<1735> B_IWL<1734> B_IWL<1733> B_IWL<1732> B_IWL<1731> B_IWL<1730> B_IWL<1729> B_IWL<1728> B_IWL<1727> B_IWL<1726> B_IWL<1725> B_IWL<1724> B_IWL<1723> B_IWL<1722> B_IWL<1721> B_IWL<1720> B_IWL<1719> B_IWL<1718> B_IWL<1717> B_IWL<1716> B_IWL<1715> B_IWL<1714> B_IWL<1713> B_IWL<1712> B_IWL<1711> B_IWL<1710> B_IWL<1709> B_IWL<1708> B_IWL<1707> B_IWL<1706> B_IWL<1705> B_IWL<1704> B_IWL<1703> B_IWL<1702> B_IWL<1701> B_IWL<1700> B_IWL<1699> B_IWL<1698> B_IWL<1697> B_IWL<1696> B_IWL<1695> B_IWL<1694> B_IWL<1693> B_IWL<1692> B_IWL<1691> B_IWL<1690> B_IWL<1689> B_IWL<1688> B_IWL<1687> B_IWL<1686> B_IWL<1685> B_IWL<1684> B_IWL<1683> B_IWL<1682> B_IWL<1681> B_IWL<1680> B_IWL<1679> B_IWL<1678> B_IWL<1677> B_IWL<1676> B_IWL<1675> B_IWL<1674> B_IWL<1673> B_IWL<1672> B_IWL<1671> B_IWL<1670> B_IWL<1669> B_IWL<1668> B_IWL<1667> B_IWL<1666> B_IWL<1665> B_IWL<1664> B_IWL<1663> B_IWL<1662> B_IWL<1661> B_IWL<1660> B_IWL<1659> B_IWL<1658> B_IWL<1657> B_IWL<1656> B_IWL<1655> B_IWL<1654> B_IWL<1653> B_IWL<1652> B_IWL<1651> B_IWL<1650> B_IWL<1649> B_IWL<1648> B_IWL<1647> B_IWL<1646> B_IWL<1645> B_IWL<1644> B_IWL<1643> B_IWL<1642> B_IWL<1641> B_IWL<1640> B_IWL<1639> B_IWL<1638> B_IWL<1637> B_IWL<1636> B_IWL<1635> B_IWL<1634> B_IWL<1633> B_IWL<1632> B_IWL<1631> B_IWL<1630> B_IWL<1629> B_IWL<1628> B_IWL<1627> B_IWL<1626> B_IWL<1625> B_IWL<1624> B_IWL<1623> B_IWL<1622> B_IWL<1621> B_IWL<1620> B_IWL<1619> B_IWL<1618> B_IWL<1617> B_IWL<1616> B_IWL<1615> B_IWL<1614> B_IWL<1613> B_IWL<1612> B_IWL<1611> B_IWL<1610> B_IWL<1609> B_IWL<1608> B_IWL<1607> B_IWL<1606> B_IWL<1605> B_IWL<1604> B_IWL<1603> B_IWL<1602> B_IWL<1601> B_IWL<1600> B_IWL<1599> B_IWL<1598> B_IWL<1597> B_IWL<1596> B_IWL<1595> B_IWL<1594> B_IWL<1593> B_IWL<1592> B_IWL<1591> B_IWL<1590> B_IWL<1589> B_IWL<1588> B_IWL<1587> B_IWL<1586> B_IWL<1585> B_IWL<1584> B_IWL<1583> B_IWL<1582> B_IWL<1581> B_IWL<1580> B_IWL<1579> B_IWL<1578> B_IWL<1577> B_IWL<1576> B_IWL<1575> B_IWL<1574> B_IWL<1573> B_IWL<1572> B_IWL<1571> B_IWL<1570> B_IWL<1569> B_IWL<1568> B_IWL<1567> B_IWL<1566> B_IWL<1565> B_IWL<1564> B_IWL<1563> B_IWL<1562> B_IWL<1561> B_IWL<1560> B_IWL<1559> B_IWL<1558> B_IWL<1557> B_IWL<1556> B_IWL<1555> B_IWL<1554> B_IWL<1553> B_IWL<1552> B_IWL<1551> B_IWL<1550> B_IWL<1549> B_IWL<1548> B_IWL<1547> B_IWL<1546> B_IWL<1545> B_IWL<1544> B_IWL<1543> B_IWL<1542> B_IWL<1541> B_IWL<1540> B_IWL<1539> B_IWL<1538> B_IWL<1537> B_IWL<1536> VDD_CORE VSS / RM_IHPSG13_1024x16_c2_2P_COLUMN_pcell_0 +XCOL<5> A_BLC<11> A_BLC<10> A_BLC_TOP<11> A_BLC_TOP<10> A_BLT<11> A_BLT<10> A_BLT_TOP<11> A_BLT_TOP<10> A_IWL<1279> A_IWL<1278> A_IWL<1277> A_IWL<1276> A_IWL<1275> A_IWL<1274> A_IWL<1273> A_IWL<1272> A_IWL<1271> A_IWL<1270> A_IWL<1269> A_IWL<1268> A_IWL<1267> A_IWL<1266> A_IWL<1265> A_IWL<1264> A_IWL<1263> A_IWL<1262> A_IWL<1261> A_IWL<1260> A_IWL<1259> A_IWL<1258> A_IWL<1257> A_IWL<1256> A_IWL<1255> A_IWL<1254> A_IWL<1253> A_IWL<1252> A_IWL<1251> A_IWL<1250> A_IWL<1249> A_IWL<1248> A_IWL<1247> A_IWL<1246> A_IWL<1245> A_IWL<1244> A_IWL<1243> A_IWL<1242> A_IWL<1241> A_IWL<1240> A_IWL<1239> A_IWL<1238> A_IWL<1237> A_IWL<1236> A_IWL<1235> A_IWL<1234> A_IWL<1233> A_IWL<1232> A_IWL<1231> A_IWL<1230> A_IWL<1229> A_IWL<1228> A_IWL<1227> A_IWL<1226> A_IWL<1225> A_IWL<1224> A_IWL<1223> A_IWL<1222> A_IWL<1221> A_IWL<1220> A_IWL<1219> A_IWL<1218> A_IWL<1217> A_IWL<1216> A_IWL<1215> A_IWL<1214> A_IWL<1213> A_IWL<1212> A_IWL<1211> A_IWL<1210> A_IWL<1209> A_IWL<1208> A_IWL<1207> A_IWL<1206> A_IWL<1205> A_IWL<1204> A_IWL<1203> A_IWL<1202> A_IWL<1201> A_IWL<1200> A_IWL<1199> A_IWL<1198> A_IWL<1197> A_IWL<1196> A_IWL<1195> A_IWL<1194> A_IWL<1193> A_IWL<1192> A_IWL<1191> A_IWL<1190> A_IWL<1189> A_IWL<1188> A_IWL<1187> A_IWL<1186> A_IWL<1185> A_IWL<1184> A_IWL<1183> A_IWL<1182> A_IWL<1181> A_IWL<1180> A_IWL<1179> A_IWL<1178> A_IWL<1177> A_IWL<1176> A_IWL<1175> A_IWL<1174> A_IWL<1173> A_IWL<1172> A_IWL<1171> A_IWL<1170> A_IWL<1169> A_IWL<1168> A_IWL<1167> A_IWL<1166> A_IWL<1165> A_IWL<1164> A_IWL<1163> A_IWL<1162> A_IWL<1161> A_IWL<1160> A_IWL<1159> A_IWL<1158> A_IWL<1157> A_IWL<1156> A_IWL<1155> A_IWL<1154> A_IWL<1153> A_IWL<1152> A_IWL<1151> A_IWL<1150> A_IWL<1149> A_IWL<1148> A_IWL<1147> A_IWL<1146> A_IWL<1145> A_IWL<1144> A_IWL<1143> A_IWL<1142> A_IWL<1141> A_IWL<1140> A_IWL<1139> A_IWL<1138> A_IWL<1137> A_IWL<1136> A_IWL<1135> A_IWL<1134> A_IWL<1133> A_IWL<1132> A_IWL<1131> A_IWL<1130> A_IWL<1129> A_IWL<1128> A_IWL<1127> A_IWL<1126> A_IWL<1125> A_IWL<1124> A_IWL<1123> A_IWL<1122> A_IWL<1121> A_IWL<1120> A_IWL<1119> A_IWL<1118> A_IWL<1117> A_IWL<1116> A_IWL<1115> A_IWL<1114> A_IWL<1113> A_IWL<1112> A_IWL<1111> A_IWL<1110> A_IWL<1109> A_IWL<1108> A_IWL<1107> A_IWL<1106> A_IWL<1105> A_IWL<1104> A_IWL<1103> A_IWL<1102> A_IWL<1101> A_IWL<1100> A_IWL<1099> A_IWL<1098> A_IWL<1097> A_IWL<1096> A_IWL<1095> A_IWL<1094> A_IWL<1093> A_IWL<1092> A_IWL<1091> A_IWL<1090> A_IWL<1089> A_IWL<1088> A_IWL<1087> A_IWL<1086> A_IWL<1085> A_IWL<1084> A_IWL<1083> A_IWL<1082> A_IWL<1081> A_IWL<1080> A_IWL<1079> A_IWL<1078> A_IWL<1077> A_IWL<1076> A_IWL<1075> A_IWL<1074> A_IWL<1073> A_IWL<1072> A_IWL<1071> A_IWL<1070> A_IWL<1069> A_IWL<1068> A_IWL<1067> A_IWL<1066> A_IWL<1065> A_IWL<1064> A_IWL<1063> A_IWL<1062> A_IWL<1061> A_IWL<1060> A_IWL<1059> A_IWL<1058> A_IWL<1057> A_IWL<1056> A_IWL<1055> A_IWL<1054> A_IWL<1053> A_IWL<1052> A_IWL<1051> A_IWL<1050> A_IWL<1049> A_IWL<1048> A_IWL<1047> A_IWL<1046> A_IWL<1045> A_IWL<1044> A_IWL<1043> A_IWL<1042> A_IWL<1041> A_IWL<1040> A_IWL<1039> A_IWL<1038> A_IWL<1037> A_IWL<1036> A_IWL<1035> A_IWL<1034> A_IWL<1033> A_IWL<1032> A_IWL<1031> A_IWL<1030> A_IWL<1029> A_IWL<1028> A_IWL<1027> A_IWL<1026> A_IWL<1025> A_IWL<1024> A_IWL<1535> A_IWL<1534> A_IWL<1533> A_IWL<1532> A_IWL<1531> A_IWL<1530> A_IWL<1529> A_IWL<1528> A_IWL<1527> A_IWL<1526> A_IWL<1525> A_IWL<1524> A_IWL<1523> A_IWL<1522> A_IWL<1521> A_IWL<1520> A_IWL<1519> A_IWL<1518> A_IWL<1517> A_IWL<1516> A_IWL<1515> A_IWL<1514> A_IWL<1513> A_IWL<1512> A_IWL<1511> A_IWL<1510> A_IWL<1509> A_IWL<1508> A_IWL<1507> A_IWL<1506> A_IWL<1505> A_IWL<1504> A_IWL<1503> A_IWL<1502> A_IWL<1501> A_IWL<1500> A_IWL<1499> A_IWL<1498> A_IWL<1497> A_IWL<1496> A_IWL<1495> A_IWL<1494> A_IWL<1493> A_IWL<1492> A_IWL<1491> A_IWL<1490> A_IWL<1489> A_IWL<1488> A_IWL<1487> A_IWL<1486> A_IWL<1485> A_IWL<1484> A_IWL<1483> A_IWL<1482> A_IWL<1481> A_IWL<1480> A_IWL<1479> A_IWL<1478> A_IWL<1477> A_IWL<1476> A_IWL<1475> A_IWL<1474> A_IWL<1473> A_IWL<1472> A_IWL<1471> A_IWL<1470> A_IWL<1469> A_IWL<1468> A_IWL<1467> A_IWL<1466> A_IWL<1465> A_IWL<1464> A_IWL<1463> A_IWL<1462> A_IWL<1461> A_IWL<1460> A_IWL<1459> A_IWL<1458> A_IWL<1457> A_IWL<1456> A_IWL<1455> A_IWL<1454> A_IWL<1453> A_IWL<1452> A_IWL<1451> A_IWL<1450> A_IWL<1449> A_IWL<1448> A_IWL<1447> A_IWL<1446> A_IWL<1445> A_IWL<1444> A_IWL<1443> A_IWL<1442> A_IWL<1441> A_IWL<1440> A_IWL<1439> A_IWL<1438> A_IWL<1437> A_IWL<1436> A_IWL<1435> A_IWL<1434> A_IWL<1433> A_IWL<1432> A_IWL<1431> A_IWL<1430> A_IWL<1429> A_IWL<1428> A_IWL<1427> A_IWL<1426> A_IWL<1425> A_IWL<1424> A_IWL<1423> A_IWL<1422> A_IWL<1421> A_IWL<1420> A_IWL<1419> A_IWL<1418> A_IWL<1417> A_IWL<1416> A_IWL<1415> A_IWL<1414> A_IWL<1413> A_IWL<1412> A_IWL<1411> A_IWL<1410> A_IWL<1409> A_IWL<1408> A_IWL<1407> A_IWL<1406> A_IWL<1405> A_IWL<1404> A_IWL<1403> A_IWL<1402> A_IWL<1401> A_IWL<1400> A_IWL<1399> A_IWL<1398> A_IWL<1397> A_IWL<1396> A_IWL<1395> A_IWL<1394> A_IWL<1393> A_IWL<1392> A_IWL<1391> A_IWL<1390> A_IWL<1389> A_IWL<1388> A_IWL<1387> A_IWL<1386> A_IWL<1385> A_IWL<1384> A_IWL<1383> A_IWL<1382> A_IWL<1381> A_IWL<1380> A_IWL<1379> A_IWL<1378> A_IWL<1377> A_IWL<1376> A_IWL<1375> A_IWL<1374> A_IWL<1373> A_IWL<1372> A_IWL<1371> A_IWL<1370> A_IWL<1369> A_IWL<1368> A_IWL<1367> A_IWL<1366> A_IWL<1365> A_IWL<1364> A_IWL<1363> A_IWL<1362> A_IWL<1361> A_IWL<1360> A_IWL<1359> A_IWL<1358> A_IWL<1357> A_IWL<1356> A_IWL<1355> A_IWL<1354> A_IWL<1353> A_IWL<1352> A_IWL<1351> A_IWL<1350> A_IWL<1349> A_IWL<1348> A_IWL<1347> A_IWL<1346> A_IWL<1345> A_IWL<1344> A_IWL<1343> A_IWL<1342> A_IWL<1341> A_IWL<1340> A_IWL<1339> A_IWL<1338> A_IWL<1337> A_IWL<1336> A_IWL<1335> A_IWL<1334> A_IWL<1333> A_IWL<1332> A_IWL<1331> A_IWL<1330> A_IWL<1329> A_IWL<1328> A_IWL<1327> A_IWL<1326> A_IWL<1325> A_IWL<1324> A_IWL<1323> A_IWL<1322> A_IWL<1321> A_IWL<1320> A_IWL<1319> A_IWL<1318> A_IWL<1317> A_IWL<1316> A_IWL<1315> A_IWL<1314> A_IWL<1313> A_IWL<1312> A_IWL<1311> A_IWL<1310> A_IWL<1309> A_IWL<1308> A_IWL<1307> A_IWL<1306> A_IWL<1305> A_IWL<1304> A_IWL<1303> A_IWL<1302> A_IWL<1301> A_IWL<1300> A_IWL<1299> A_IWL<1298> A_IWL<1297> A_IWL<1296> A_IWL<1295> A_IWL<1294> A_IWL<1293> A_IWL<1292> A_IWL<1291> A_IWL<1290> A_IWL<1289> A_IWL<1288> A_IWL<1287> A_IWL<1286> A_IWL<1285> A_IWL<1284> A_IWL<1283> A_IWL<1282> A_IWL<1281> A_IWL<1280> B_BLC<11> B_BLC<10> B_BLC_TOP<11> B_BLC_TOP<10> B_BLT<11> B_BLT<10> B_BLT_TOP<11> B_BLT_TOP<10> B_IWL<1279> B_IWL<1278> B_IWL<1277> B_IWL<1276> B_IWL<1275> B_IWL<1274> B_IWL<1273> B_IWL<1272> B_IWL<1271> B_IWL<1270> B_IWL<1269> B_IWL<1268> B_IWL<1267> B_IWL<1266> B_IWL<1265> B_IWL<1264> B_IWL<1263> B_IWL<1262> B_IWL<1261> B_IWL<1260> B_IWL<1259> B_IWL<1258> B_IWL<1257> B_IWL<1256> B_IWL<1255> B_IWL<1254> B_IWL<1253> B_IWL<1252> B_IWL<1251> B_IWL<1250> B_IWL<1249> B_IWL<1248> B_IWL<1247> B_IWL<1246> B_IWL<1245> B_IWL<1244> B_IWL<1243> B_IWL<1242> B_IWL<1241> B_IWL<1240> B_IWL<1239> B_IWL<1238> B_IWL<1237> B_IWL<1236> B_IWL<1235> B_IWL<1234> B_IWL<1233> B_IWL<1232> B_IWL<1231> B_IWL<1230> B_IWL<1229> B_IWL<1228> B_IWL<1227> B_IWL<1226> B_IWL<1225> B_IWL<1224> B_IWL<1223> B_IWL<1222> B_IWL<1221> B_IWL<1220> B_IWL<1219> B_IWL<1218> B_IWL<1217> B_IWL<1216> B_IWL<1215> B_IWL<1214> B_IWL<1213> B_IWL<1212> B_IWL<1211> B_IWL<1210> B_IWL<1209> B_IWL<1208> B_IWL<1207> B_IWL<1206> B_IWL<1205> B_IWL<1204> B_IWL<1203> B_IWL<1202> B_IWL<1201> B_IWL<1200> B_IWL<1199> B_IWL<1198> B_IWL<1197> B_IWL<1196> B_IWL<1195> B_IWL<1194> B_IWL<1193> B_IWL<1192> B_IWL<1191> B_IWL<1190> B_IWL<1189> B_IWL<1188> B_IWL<1187> B_IWL<1186> B_IWL<1185> B_IWL<1184> B_IWL<1183> B_IWL<1182> B_IWL<1181> B_IWL<1180> B_IWL<1179> B_IWL<1178> B_IWL<1177> B_IWL<1176> B_IWL<1175> B_IWL<1174> B_IWL<1173> B_IWL<1172> B_IWL<1171> B_IWL<1170> B_IWL<1169> B_IWL<1168> B_IWL<1167> B_IWL<1166> B_IWL<1165> B_IWL<1164> B_IWL<1163> B_IWL<1162> B_IWL<1161> B_IWL<1160> B_IWL<1159> B_IWL<1158> B_IWL<1157> B_IWL<1156> B_IWL<1155> B_IWL<1154> B_IWL<1153> B_IWL<1152> B_IWL<1151> B_IWL<1150> B_IWL<1149> B_IWL<1148> B_IWL<1147> B_IWL<1146> B_IWL<1145> B_IWL<1144> B_IWL<1143> B_IWL<1142> B_IWL<1141> B_IWL<1140> B_IWL<1139> B_IWL<1138> B_IWL<1137> B_IWL<1136> B_IWL<1135> B_IWL<1134> B_IWL<1133> B_IWL<1132> B_IWL<1131> B_IWL<1130> B_IWL<1129> B_IWL<1128> B_IWL<1127> B_IWL<1126> B_IWL<1125> B_IWL<1124> B_IWL<1123> B_IWL<1122> B_IWL<1121> B_IWL<1120> B_IWL<1119> B_IWL<1118> B_IWL<1117> B_IWL<1116> B_IWL<1115> B_IWL<1114> B_IWL<1113> B_IWL<1112> B_IWL<1111> B_IWL<1110> B_IWL<1109> B_IWL<1108> B_IWL<1107> B_IWL<1106> B_IWL<1105> B_IWL<1104> B_IWL<1103> B_IWL<1102> B_IWL<1101> B_IWL<1100> B_IWL<1099> B_IWL<1098> B_IWL<1097> B_IWL<1096> B_IWL<1095> B_IWL<1094> B_IWL<1093> B_IWL<1092> B_IWL<1091> B_IWL<1090> B_IWL<1089> B_IWL<1088> B_IWL<1087> B_IWL<1086> B_IWL<1085> B_IWL<1084> B_IWL<1083> B_IWL<1082> B_IWL<1081> B_IWL<1080> B_IWL<1079> B_IWL<1078> B_IWL<1077> B_IWL<1076> B_IWL<1075> B_IWL<1074> B_IWL<1073> B_IWL<1072> B_IWL<1071> B_IWL<1070> B_IWL<1069> B_IWL<1068> B_IWL<1067> B_IWL<1066> B_IWL<1065> B_IWL<1064> B_IWL<1063> B_IWL<1062> B_IWL<1061> B_IWL<1060> B_IWL<1059> B_IWL<1058> B_IWL<1057> B_IWL<1056> B_IWL<1055> B_IWL<1054> B_IWL<1053> B_IWL<1052> B_IWL<1051> B_IWL<1050> B_IWL<1049> B_IWL<1048> B_IWL<1047> B_IWL<1046> B_IWL<1045> B_IWL<1044> B_IWL<1043> B_IWL<1042> B_IWL<1041> B_IWL<1040> B_IWL<1039> B_IWL<1038> B_IWL<1037> B_IWL<1036> B_IWL<1035> B_IWL<1034> B_IWL<1033> B_IWL<1032> B_IWL<1031> B_IWL<1030> B_IWL<1029> B_IWL<1028> B_IWL<1027> B_IWL<1026> B_IWL<1025> B_IWL<1024> B_IWL<1535> B_IWL<1534> B_IWL<1533> B_IWL<1532> B_IWL<1531> B_IWL<1530> B_IWL<1529> B_IWL<1528> B_IWL<1527> B_IWL<1526> B_IWL<1525> B_IWL<1524> B_IWL<1523> B_IWL<1522> B_IWL<1521> B_IWL<1520> B_IWL<1519> B_IWL<1518> B_IWL<1517> B_IWL<1516> B_IWL<1515> B_IWL<1514> B_IWL<1513> B_IWL<1512> B_IWL<1511> B_IWL<1510> B_IWL<1509> B_IWL<1508> B_IWL<1507> B_IWL<1506> B_IWL<1505> B_IWL<1504> B_IWL<1503> B_IWL<1502> B_IWL<1501> B_IWL<1500> B_IWL<1499> B_IWL<1498> B_IWL<1497> B_IWL<1496> B_IWL<1495> B_IWL<1494> B_IWL<1493> B_IWL<1492> B_IWL<1491> B_IWL<1490> B_IWL<1489> B_IWL<1488> B_IWL<1487> B_IWL<1486> B_IWL<1485> B_IWL<1484> B_IWL<1483> B_IWL<1482> B_IWL<1481> B_IWL<1480> B_IWL<1479> B_IWL<1478> B_IWL<1477> B_IWL<1476> B_IWL<1475> B_IWL<1474> B_IWL<1473> B_IWL<1472> B_IWL<1471> B_IWL<1470> B_IWL<1469> B_IWL<1468> B_IWL<1467> B_IWL<1466> B_IWL<1465> B_IWL<1464> B_IWL<1463> B_IWL<1462> B_IWL<1461> B_IWL<1460> B_IWL<1459> B_IWL<1458> B_IWL<1457> B_IWL<1456> B_IWL<1455> B_IWL<1454> B_IWL<1453> B_IWL<1452> B_IWL<1451> B_IWL<1450> B_IWL<1449> B_IWL<1448> B_IWL<1447> B_IWL<1446> B_IWL<1445> B_IWL<1444> B_IWL<1443> B_IWL<1442> B_IWL<1441> B_IWL<1440> B_IWL<1439> B_IWL<1438> B_IWL<1437> B_IWL<1436> B_IWL<1435> B_IWL<1434> B_IWL<1433> B_IWL<1432> B_IWL<1431> B_IWL<1430> B_IWL<1429> B_IWL<1428> B_IWL<1427> B_IWL<1426> B_IWL<1425> B_IWL<1424> B_IWL<1423> B_IWL<1422> B_IWL<1421> B_IWL<1420> B_IWL<1419> B_IWL<1418> B_IWL<1417> B_IWL<1416> B_IWL<1415> B_IWL<1414> B_IWL<1413> B_IWL<1412> B_IWL<1411> B_IWL<1410> B_IWL<1409> B_IWL<1408> B_IWL<1407> B_IWL<1406> B_IWL<1405> B_IWL<1404> B_IWL<1403> B_IWL<1402> B_IWL<1401> B_IWL<1400> B_IWL<1399> B_IWL<1398> B_IWL<1397> B_IWL<1396> B_IWL<1395> B_IWL<1394> B_IWL<1393> B_IWL<1392> B_IWL<1391> B_IWL<1390> B_IWL<1389> B_IWL<1388> B_IWL<1387> B_IWL<1386> B_IWL<1385> B_IWL<1384> B_IWL<1383> B_IWL<1382> B_IWL<1381> B_IWL<1380> B_IWL<1379> B_IWL<1378> B_IWL<1377> B_IWL<1376> B_IWL<1375> B_IWL<1374> B_IWL<1373> B_IWL<1372> B_IWL<1371> B_IWL<1370> B_IWL<1369> B_IWL<1368> B_IWL<1367> B_IWL<1366> B_IWL<1365> B_IWL<1364> B_IWL<1363> B_IWL<1362> B_IWL<1361> B_IWL<1360> B_IWL<1359> B_IWL<1358> B_IWL<1357> B_IWL<1356> B_IWL<1355> B_IWL<1354> B_IWL<1353> B_IWL<1352> B_IWL<1351> B_IWL<1350> B_IWL<1349> B_IWL<1348> B_IWL<1347> B_IWL<1346> B_IWL<1345> B_IWL<1344> B_IWL<1343> B_IWL<1342> B_IWL<1341> B_IWL<1340> B_IWL<1339> B_IWL<1338> B_IWL<1337> B_IWL<1336> B_IWL<1335> B_IWL<1334> B_IWL<1333> B_IWL<1332> B_IWL<1331> B_IWL<1330> B_IWL<1329> B_IWL<1328> B_IWL<1327> B_IWL<1326> B_IWL<1325> B_IWL<1324> B_IWL<1323> B_IWL<1322> B_IWL<1321> B_IWL<1320> B_IWL<1319> B_IWL<1318> B_IWL<1317> B_IWL<1316> B_IWL<1315> B_IWL<1314> B_IWL<1313> B_IWL<1312> B_IWL<1311> B_IWL<1310> B_IWL<1309> B_IWL<1308> B_IWL<1307> B_IWL<1306> B_IWL<1305> B_IWL<1304> B_IWL<1303> B_IWL<1302> B_IWL<1301> B_IWL<1300> B_IWL<1299> B_IWL<1298> B_IWL<1297> B_IWL<1296> B_IWL<1295> B_IWL<1294> B_IWL<1293> B_IWL<1292> B_IWL<1291> B_IWL<1290> B_IWL<1289> B_IWL<1288> B_IWL<1287> B_IWL<1286> B_IWL<1285> B_IWL<1284> B_IWL<1283> B_IWL<1282> B_IWL<1281> B_IWL<1280> VDD_CORE VSS / RM_IHPSG13_1024x16_c2_2P_COLUMN_pcell_0 +XCOL<4> A_BLC<9> A_BLC<8> A_BLC_TOP<9> A_BLC_TOP<8> A_BLT<9> A_BLT<8> A_BLT_TOP<9> A_BLT_TOP<8> A_IWL<1023> A_IWL<1022> A_IWL<1021> A_IWL<1020> A_IWL<1019> A_IWL<1018> A_IWL<1017> A_IWL<1016> A_IWL<1015> A_IWL<1014> A_IWL<1013> A_IWL<1012> A_IWL<1011> A_IWL<1010> A_IWL<1009> A_IWL<1008> A_IWL<1007> A_IWL<1006> A_IWL<1005> A_IWL<1004> A_IWL<1003> A_IWL<1002> A_IWL<1001> A_IWL<1000> A_IWL<999> A_IWL<998> A_IWL<997> A_IWL<996> A_IWL<995> A_IWL<994> A_IWL<993> A_IWL<992> A_IWL<991> A_IWL<990> A_IWL<989> A_IWL<988> A_IWL<987> A_IWL<986> A_IWL<985> A_IWL<984> A_IWL<983> A_IWL<982> A_IWL<981> A_IWL<980> A_IWL<979> A_IWL<978> A_IWL<977> A_IWL<976> A_IWL<975> A_IWL<974> A_IWL<973> A_IWL<972> A_IWL<971> A_IWL<970> A_IWL<969> A_IWL<968> A_IWL<967> A_IWL<966> A_IWL<965> A_IWL<964> A_IWL<963> A_IWL<962> A_IWL<961> A_IWL<960> A_IWL<959> A_IWL<958> A_IWL<957> A_IWL<956> A_IWL<955> A_IWL<954> A_IWL<953> A_IWL<952> A_IWL<951> A_IWL<950> A_IWL<949> A_IWL<948> A_IWL<947> A_IWL<946> A_IWL<945> A_IWL<944> A_IWL<943> A_IWL<942> A_IWL<941> A_IWL<940> A_IWL<939> A_IWL<938> A_IWL<937> A_IWL<936> A_IWL<935> A_IWL<934> A_IWL<933> A_IWL<932> A_IWL<931> A_IWL<930> A_IWL<929> A_IWL<928> A_IWL<927> A_IWL<926> A_IWL<925> A_IWL<924> A_IWL<923> A_IWL<922> A_IWL<921> A_IWL<920> A_IWL<919> A_IWL<918> A_IWL<917> A_IWL<916> A_IWL<915> A_IWL<914> A_IWL<913> A_IWL<912> A_IWL<911> A_IWL<910> A_IWL<909> A_IWL<908> A_IWL<907> A_IWL<906> A_IWL<905> A_IWL<904> A_IWL<903> A_IWL<902> A_IWL<901> A_IWL<900> A_IWL<899> A_IWL<898> A_IWL<897> A_IWL<896> A_IWL<895> A_IWL<894> A_IWL<893> A_IWL<892> A_IWL<891> A_IWL<890> A_IWL<889> A_IWL<888> A_IWL<887> A_IWL<886> A_IWL<885> A_IWL<884> A_IWL<883> A_IWL<882> A_IWL<881> A_IWL<880> A_IWL<879> A_IWL<878> A_IWL<877> A_IWL<876> A_IWL<875> A_IWL<874> A_IWL<873> A_IWL<872> A_IWL<871> A_IWL<870> A_IWL<869> A_IWL<868> A_IWL<867> A_IWL<866> A_IWL<865> A_IWL<864> A_IWL<863> A_IWL<862> A_IWL<861> A_IWL<860> A_IWL<859> A_IWL<858> A_IWL<857> A_IWL<856> A_IWL<855> A_IWL<854> A_IWL<853> A_IWL<852> A_IWL<851> A_IWL<850> A_IWL<849> A_IWL<848> A_IWL<847> A_IWL<846> A_IWL<845> A_IWL<844> A_IWL<843> A_IWL<842> A_IWL<841> A_IWL<840> A_IWL<839> A_IWL<838> A_IWL<837> A_IWL<836> A_IWL<835> A_IWL<834> A_IWL<833> A_IWL<832> A_IWL<831> A_IWL<830> A_IWL<829> A_IWL<828> A_IWL<827> A_IWL<826> A_IWL<825> A_IWL<824> A_IWL<823> A_IWL<822> A_IWL<821> A_IWL<820> A_IWL<819> A_IWL<818> A_IWL<817> A_IWL<816> A_IWL<815> A_IWL<814> A_IWL<813> A_IWL<812> A_IWL<811> A_IWL<810> A_IWL<809> A_IWL<808> A_IWL<807> A_IWL<806> A_IWL<805> A_IWL<804> A_IWL<803> A_IWL<802> A_IWL<801> A_IWL<800> A_IWL<799> A_IWL<798> A_IWL<797> A_IWL<796> A_IWL<795> A_IWL<794> A_IWL<793> A_IWL<792> A_IWL<791> A_IWL<790> A_IWL<789> A_IWL<788> A_IWL<787> A_IWL<786> A_IWL<785> A_IWL<784> A_IWL<783> A_IWL<782> A_IWL<781> A_IWL<780> A_IWL<779> A_IWL<778> A_IWL<777> A_IWL<776> A_IWL<775> A_IWL<774> A_IWL<773> A_IWL<772> A_IWL<771> A_IWL<770> A_IWL<769> A_IWL<768> A_IWL<1279> A_IWL<1278> A_IWL<1277> A_IWL<1276> A_IWL<1275> A_IWL<1274> A_IWL<1273> A_IWL<1272> A_IWL<1271> A_IWL<1270> A_IWL<1269> A_IWL<1268> A_IWL<1267> A_IWL<1266> A_IWL<1265> A_IWL<1264> A_IWL<1263> A_IWL<1262> A_IWL<1261> A_IWL<1260> A_IWL<1259> A_IWL<1258> A_IWL<1257> A_IWL<1256> A_IWL<1255> A_IWL<1254> A_IWL<1253> A_IWL<1252> A_IWL<1251> A_IWL<1250> A_IWL<1249> A_IWL<1248> A_IWL<1247> A_IWL<1246> A_IWL<1245> A_IWL<1244> A_IWL<1243> A_IWL<1242> A_IWL<1241> A_IWL<1240> A_IWL<1239> A_IWL<1238> A_IWL<1237> A_IWL<1236> A_IWL<1235> A_IWL<1234> A_IWL<1233> A_IWL<1232> A_IWL<1231> A_IWL<1230> A_IWL<1229> A_IWL<1228> A_IWL<1227> A_IWL<1226> A_IWL<1225> A_IWL<1224> A_IWL<1223> A_IWL<1222> A_IWL<1221> A_IWL<1220> A_IWL<1219> A_IWL<1218> A_IWL<1217> A_IWL<1216> A_IWL<1215> A_IWL<1214> A_IWL<1213> A_IWL<1212> A_IWL<1211> A_IWL<1210> A_IWL<1209> A_IWL<1208> A_IWL<1207> A_IWL<1206> A_IWL<1205> A_IWL<1204> A_IWL<1203> A_IWL<1202> A_IWL<1201> A_IWL<1200> A_IWL<1199> A_IWL<1198> A_IWL<1197> A_IWL<1196> A_IWL<1195> A_IWL<1194> A_IWL<1193> A_IWL<1192> A_IWL<1191> A_IWL<1190> A_IWL<1189> A_IWL<1188> A_IWL<1187> A_IWL<1186> A_IWL<1185> A_IWL<1184> A_IWL<1183> A_IWL<1182> A_IWL<1181> A_IWL<1180> A_IWL<1179> A_IWL<1178> A_IWL<1177> A_IWL<1176> A_IWL<1175> A_IWL<1174> A_IWL<1173> A_IWL<1172> A_IWL<1171> A_IWL<1170> A_IWL<1169> A_IWL<1168> A_IWL<1167> A_IWL<1166> A_IWL<1165> A_IWL<1164> A_IWL<1163> A_IWL<1162> A_IWL<1161> A_IWL<1160> A_IWL<1159> A_IWL<1158> A_IWL<1157> A_IWL<1156> A_IWL<1155> A_IWL<1154> A_IWL<1153> A_IWL<1152> A_IWL<1151> A_IWL<1150> A_IWL<1149> A_IWL<1148> A_IWL<1147> A_IWL<1146> A_IWL<1145> A_IWL<1144> A_IWL<1143> A_IWL<1142> A_IWL<1141> A_IWL<1140> A_IWL<1139> A_IWL<1138> A_IWL<1137> A_IWL<1136> A_IWL<1135> A_IWL<1134> A_IWL<1133> A_IWL<1132> A_IWL<1131> A_IWL<1130> A_IWL<1129> A_IWL<1128> A_IWL<1127> A_IWL<1126> A_IWL<1125> A_IWL<1124> A_IWL<1123> A_IWL<1122> A_IWL<1121> A_IWL<1120> A_IWL<1119> A_IWL<1118> A_IWL<1117> A_IWL<1116> A_IWL<1115> A_IWL<1114> A_IWL<1113> A_IWL<1112> A_IWL<1111> A_IWL<1110> A_IWL<1109> A_IWL<1108> A_IWL<1107> A_IWL<1106> A_IWL<1105> A_IWL<1104> A_IWL<1103> A_IWL<1102> A_IWL<1101> A_IWL<1100> A_IWL<1099> A_IWL<1098> A_IWL<1097> A_IWL<1096> A_IWL<1095> A_IWL<1094> A_IWL<1093> A_IWL<1092> A_IWL<1091> A_IWL<1090> A_IWL<1089> A_IWL<1088> A_IWL<1087> A_IWL<1086> A_IWL<1085> A_IWL<1084> A_IWL<1083> A_IWL<1082> A_IWL<1081> A_IWL<1080> A_IWL<1079> A_IWL<1078> A_IWL<1077> A_IWL<1076> A_IWL<1075> A_IWL<1074> A_IWL<1073> A_IWL<1072> A_IWL<1071> A_IWL<1070> A_IWL<1069> A_IWL<1068> A_IWL<1067> A_IWL<1066> A_IWL<1065> A_IWL<1064> A_IWL<1063> A_IWL<1062> A_IWL<1061> A_IWL<1060> A_IWL<1059> A_IWL<1058> A_IWL<1057> A_IWL<1056> A_IWL<1055> A_IWL<1054> A_IWL<1053> A_IWL<1052> A_IWL<1051> A_IWL<1050> A_IWL<1049> A_IWL<1048> A_IWL<1047> A_IWL<1046> A_IWL<1045> A_IWL<1044> A_IWL<1043> A_IWL<1042> A_IWL<1041> A_IWL<1040> A_IWL<1039> A_IWL<1038> A_IWL<1037> A_IWL<1036> A_IWL<1035> A_IWL<1034> A_IWL<1033> A_IWL<1032> A_IWL<1031> A_IWL<1030> A_IWL<1029> A_IWL<1028> A_IWL<1027> A_IWL<1026> A_IWL<1025> A_IWL<1024> B_BLC<9> B_BLC<8> B_BLC_TOP<9> B_BLC_TOP<8> B_BLT<9> B_BLT<8> B_BLT_TOP<9> B_BLT_TOP<8> B_IWL<1023> B_IWL<1022> B_IWL<1021> B_IWL<1020> B_IWL<1019> B_IWL<1018> B_IWL<1017> B_IWL<1016> B_IWL<1015> B_IWL<1014> B_IWL<1013> B_IWL<1012> B_IWL<1011> B_IWL<1010> B_IWL<1009> B_IWL<1008> B_IWL<1007> B_IWL<1006> B_IWL<1005> B_IWL<1004> B_IWL<1003> B_IWL<1002> B_IWL<1001> B_IWL<1000> B_IWL<999> B_IWL<998> B_IWL<997> B_IWL<996> B_IWL<995> B_IWL<994> B_IWL<993> B_IWL<992> B_IWL<991> B_IWL<990> B_IWL<989> B_IWL<988> B_IWL<987> B_IWL<986> B_IWL<985> B_IWL<984> B_IWL<983> B_IWL<982> B_IWL<981> B_IWL<980> B_IWL<979> B_IWL<978> B_IWL<977> B_IWL<976> B_IWL<975> B_IWL<974> B_IWL<973> B_IWL<972> B_IWL<971> B_IWL<970> B_IWL<969> B_IWL<968> B_IWL<967> B_IWL<966> B_IWL<965> B_IWL<964> B_IWL<963> B_IWL<962> B_IWL<961> B_IWL<960> B_IWL<959> B_IWL<958> B_IWL<957> B_IWL<956> B_IWL<955> B_IWL<954> B_IWL<953> B_IWL<952> B_IWL<951> B_IWL<950> B_IWL<949> B_IWL<948> B_IWL<947> B_IWL<946> B_IWL<945> B_IWL<944> B_IWL<943> B_IWL<942> B_IWL<941> B_IWL<940> B_IWL<939> B_IWL<938> B_IWL<937> B_IWL<936> B_IWL<935> B_IWL<934> B_IWL<933> B_IWL<932> B_IWL<931> B_IWL<930> B_IWL<929> B_IWL<928> B_IWL<927> B_IWL<926> B_IWL<925> B_IWL<924> B_IWL<923> B_IWL<922> B_IWL<921> B_IWL<920> B_IWL<919> B_IWL<918> B_IWL<917> B_IWL<916> B_IWL<915> B_IWL<914> B_IWL<913> B_IWL<912> B_IWL<911> B_IWL<910> B_IWL<909> B_IWL<908> B_IWL<907> B_IWL<906> B_IWL<905> B_IWL<904> B_IWL<903> B_IWL<902> B_IWL<901> B_IWL<900> B_IWL<899> B_IWL<898> B_IWL<897> B_IWL<896> B_IWL<895> B_IWL<894> B_IWL<893> B_IWL<892> B_IWL<891> B_IWL<890> B_IWL<889> B_IWL<888> B_IWL<887> B_IWL<886> B_IWL<885> B_IWL<884> B_IWL<883> B_IWL<882> B_IWL<881> B_IWL<880> B_IWL<879> B_IWL<878> B_IWL<877> B_IWL<876> B_IWL<875> B_IWL<874> B_IWL<873> B_IWL<872> B_IWL<871> B_IWL<870> B_IWL<869> B_IWL<868> B_IWL<867> B_IWL<866> B_IWL<865> B_IWL<864> B_IWL<863> B_IWL<862> B_IWL<861> B_IWL<860> B_IWL<859> B_IWL<858> B_IWL<857> B_IWL<856> B_IWL<855> B_IWL<854> B_IWL<853> B_IWL<852> B_IWL<851> B_IWL<850> B_IWL<849> B_IWL<848> B_IWL<847> B_IWL<846> B_IWL<845> B_IWL<844> B_IWL<843> B_IWL<842> B_IWL<841> B_IWL<840> B_IWL<839> B_IWL<838> B_IWL<837> B_IWL<836> B_IWL<835> B_IWL<834> B_IWL<833> B_IWL<832> B_IWL<831> B_IWL<830> B_IWL<829> B_IWL<828> B_IWL<827> B_IWL<826> B_IWL<825> B_IWL<824> B_IWL<823> B_IWL<822> B_IWL<821> B_IWL<820> B_IWL<819> B_IWL<818> B_IWL<817> B_IWL<816> B_IWL<815> B_IWL<814> B_IWL<813> B_IWL<812> B_IWL<811> B_IWL<810> B_IWL<809> B_IWL<808> B_IWL<807> B_IWL<806> B_IWL<805> B_IWL<804> B_IWL<803> B_IWL<802> B_IWL<801> B_IWL<800> B_IWL<799> B_IWL<798> B_IWL<797> B_IWL<796> B_IWL<795> B_IWL<794> B_IWL<793> B_IWL<792> B_IWL<791> B_IWL<790> B_IWL<789> B_IWL<788> B_IWL<787> B_IWL<786> B_IWL<785> B_IWL<784> B_IWL<783> B_IWL<782> B_IWL<781> B_IWL<780> B_IWL<779> B_IWL<778> B_IWL<777> B_IWL<776> B_IWL<775> B_IWL<774> B_IWL<773> B_IWL<772> B_IWL<771> B_IWL<770> B_IWL<769> B_IWL<768> B_IWL<1279> B_IWL<1278> B_IWL<1277> B_IWL<1276> B_IWL<1275> B_IWL<1274> B_IWL<1273> B_IWL<1272> B_IWL<1271> B_IWL<1270> B_IWL<1269> B_IWL<1268> B_IWL<1267> B_IWL<1266> B_IWL<1265> B_IWL<1264> B_IWL<1263> B_IWL<1262> B_IWL<1261> B_IWL<1260> B_IWL<1259> B_IWL<1258> B_IWL<1257> B_IWL<1256> B_IWL<1255> B_IWL<1254> B_IWL<1253> B_IWL<1252> B_IWL<1251> B_IWL<1250> B_IWL<1249> B_IWL<1248> B_IWL<1247> B_IWL<1246> B_IWL<1245> B_IWL<1244> B_IWL<1243> B_IWL<1242> B_IWL<1241> B_IWL<1240> B_IWL<1239> B_IWL<1238> B_IWL<1237> B_IWL<1236> B_IWL<1235> B_IWL<1234> B_IWL<1233> B_IWL<1232> B_IWL<1231> B_IWL<1230> B_IWL<1229> B_IWL<1228> B_IWL<1227> B_IWL<1226> B_IWL<1225> B_IWL<1224> B_IWL<1223> B_IWL<1222> B_IWL<1221> B_IWL<1220> B_IWL<1219> B_IWL<1218> B_IWL<1217> B_IWL<1216> B_IWL<1215> B_IWL<1214> B_IWL<1213> B_IWL<1212> B_IWL<1211> B_IWL<1210> B_IWL<1209> B_IWL<1208> B_IWL<1207> B_IWL<1206> B_IWL<1205> B_IWL<1204> B_IWL<1203> B_IWL<1202> B_IWL<1201> B_IWL<1200> B_IWL<1199> B_IWL<1198> B_IWL<1197> B_IWL<1196> B_IWL<1195> B_IWL<1194> B_IWL<1193> B_IWL<1192> B_IWL<1191> B_IWL<1190> B_IWL<1189> B_IWL<1188> B_IWL<1187> B_IWL<1186> B_IWL<1185> B_IWL<1184> B_IWL<1183> B_IWL<1182> B_IWL<1181> B_IWL<1180> B_IWL<1179> B_IWL<1178> B_IWL<1177> B_IWL<1176> B_IWL<1175> B_IWL<1174> B_IWL<1173> B_IWL<1172> B_IWL<1171> B_IWL<1170> B_IWL<1169> B_IWL<1168> B_IWL<1167> B_IWL<1166> B_IWL<1165> B_IWL<1164> B_IWL<1163> B_IWL<1162> B_IWL<1161> B_IWL<1160> B_IWL<1159> B_IWL<1158> B_IWL<1157> B_IWL<1156> B_IWL<1155> B_IWL<1154> B_IWL<1153> B_IWL<1152> B_IWL<1151> B_IWL<1150> B_IWL<1149> B_IWL<1148> B_IWL<1147> B_IWL<1146> B_IWL<1145> B_IWL<1144> B_IWL<1143> B_IWL<1142> B_IWL<1141> B_IWL<1140> B_IWL<1139> B_IWL<1138> B_IWL<1137> B_IWL<1136> B_IWL<1135> B_IWL<1134> B_IWL<1133> B_IWL<1132> B_IWL<1131> B_IWL<1130> B_IWL<1129> B_IWL<1128> B_IWL<1127> B_IWL<1126> B_IWL<1125> B_IWL<1124> B_IWL<1123> B_IWL<1122> B_IWL<1121> B_IWL<1120> B_IWL<1119> B_IWL<1118> B_IWL<1117> B_IWL<1116> B_IWL<1115> B_IWL<1114> B_IWL<1113> B_IWL<1112> B_IWL<1111> B_IWL<1110> B_IWL<1109> B_IWL<1108> B_IWL<1107> B_IWL<1106> B_IWL<1105> B_IWL<1104> B_IWL<1103> B_IWL<1102> B_IWL<1101> B_IWL<1100> B_IWL<1099> B_IWL<1098> B_IWL<1097> B_IWL<1096> B_IWL<1095> B_IWL<1094> B_IWL<1093> B_IWL<1092> B_IWL<1091> B_IWL<1090> B_IWL<1089> B_IWL<1088> B_IWL<1087> B_IWL<1086> B_IWL<1085> B_IWL<1084> B_IWL<1083> B_IWL<1082> B_IWL<1081> B_IWL<1080> B_IWL<1079> B_IWL<1078> B_IWL<1077> B_IWL<1076> B_IWL<1075> B_IWL<1074> B_IWL<1073> B_IWL<1072> B_IWL<1071> B_IWL<1070> B_IWL<1069> B_IWL<1068> B_IWL<1067> B_IWL<1066> B_IWL<1065> B_IWL<1064> B_IWL<1063> B_IWL<1062> B_IWL<1061> B_IWL<1060> B_IWL<1059> B_IWL<1058> B_IWL<1057> B_IWL<1056> B_IWL<1055> B_IWL<1054> B_IWL<1053> B_IWL<1052> B_IWL<1051> B_IWL<1050> B_IWL<1049> B_IWL<1048> B_IWL<1047> B_IWL<1046> B_IWL<1045> B_IWL<1044> B_IWL<1043> B_IWL<1042> B_IWL<1041> B_IWL<1040> B_IWL<1039> B_IWL<1038> B_IWL<1037> B_IWL<1036> B_IWL<1035> B_IWL<1034> B_IWL<1033> B_IWL<1032> B_IWL<1031> B_IWL<1030> B_IWL<1029> B_IWL<1028> B_IWL<1027> B_IWL<1026> B_IWL<1025> B_IWL<1024> VDD_CORE VSS / RM_IHPSG13_1024x16_c2_2P_COLUMN_pcell_0 +XCOL<3> A_BLC<7> A_BLC<6> A_BLC_TOP<7> A_BLC_TOP<6> A_BLT<7> A_BLT<6> A_BLT_TOP<7> A_BLT_TOP<6> A_IWL<767> A_IWL<766> A_IWL<765> A_IWL<764> A_IWL<763> A_IWL<762> A_IWL<761> A_IWL<760> A_IWL<759> A_IWL<758> A_IWL<757> A_IWL<756> A_IWL<755> A_IWL<754> A_IWL<753> A_IWL<752> A_IWL<751> A_IWL<750> A_IWL<749> A_IWL<748> A_IWL<747> A_IWL<746> A_IWL<745> A_IWL<744> A_IWL<743> A_IWL<742> A_IWL<741> A_IWL<740> A_IWL<739> A_IWL<738> A_IWL<737> A_IWL<736> A_IWL<735> A_IWL<734> A_IWL<733> A_IWL<732> A_IWL<731> A_IWL<730> A_IWL<729> A_IWL<728> A_IWL<727> A_IWL<726> A_IWL<725> A_IWL<724> A_IWL<723> A_IWL<722> A_IWL<721> A_IWL<720> A_IWL<719> A_IWL<718> A_IWL<717> A_IWL<716> A_IWL<715> A_IWL<714> A_IWL<713> A_IWL<712> A_IWL<711> A_IWL<710> A_IWL<709> A_IWL<708> A_IWL<707> A_IWL<706> A_IWL<705> A_IWL<704> A_IWL<703> A_IWL<702> A_IWL<701> A_IWL<700> A_IWL<699> A_IWL<698> A_IWL<697> A_IWL<696> A_IWL<695> A_IWL<694> A_IWL<693> A_IWL<692> A_IWL<691> A_IWL<690> A_IWL<689> A_IWL<688> A_IWL<687> A_IWL<686> A_IWL<685> A_IWL<684> A_IWL<683> A_IWL<682> A_IWL<681> A_IWL<680> A_IWL<679> A_IWL<678> A_IWL<677> A_IWL<676> A_IWL<675> A_IWL<674> A_IWL<673> A_IWL<672> A_IWL<671> A_IWL<670> A_IWL<669> A_IWL<668> A_IWL<667> A_IWL<666> A_IWL<665> A_IWL<664> A_IWL<663> A_IWL<662> A_IWL<661> A_IWL<660> A_IWL<659> A_IWL<658> A_IWL<657> A_IWL<656> A_IWL<655> A_IWL<654> A_IWL<653> A_IWL<652> A_IWL<651> A_IWL<650> A_IWL<649> A_IWL<648> A_IWL<647> A_IWL<646> A_IWL<645> A_IWL<644> A_IWL<643> A_IWL<642> A_IWL<641> A_IWL<640> A_IWL<639> A_IWL<638> A_IWL<637> A_IWL<636> A_IWL<635> A_IWL<634> A_IWL<633> A_IWL<632> A_IWL<631> A_IWL<630> A_IWL<629> A_IWL<628> A_IWL<627> A_IWL<626> A_IWL<625> A_IWL<624> A_IWL<623> A_IWL<622> A_IWL<621> A_IWL<620> A_IWL<619> A_IWL<618> A_IWL<617> A_IWL<616> A_IWL<615> A_IWL<614> A_IWL<613> A_IWL<612> A_IWL<611> A_IWL<610> A_IWL<609> A_IWL<608> A_IWL<607> A_IWL<606> A_IWL<605> A_IWL<604> A_IWL<603> A_IWL<602> A_IWL<601> A_IWL<600> A_IWL<599> A_IWL<598> A_IWL<597> A_IWL<596> A_IWL<595> A_IWL<594> A_IWL<593> A_IWL<592> A_IWL<591> A_IWL<590> A_IWL<589> A_IWL<588> A_IWL<587> A_IWL<586> A_IWL<585> A_IWL<584> A_IWL<583> A_IWL<582> A_IWL<581> A_IWL<580> A_IWL<579> A_IWL<578> A_IWL<577> A_IWL<576> A_IWL<575> A_IWL<574> A_IWL<573> A_IWL<572> A_IWL<571> A_IWL<570> A_IWL<569> A_IWL<568> A_IWL<567> A_IWL<566> A_IWL<565> A_IWL<564> A_IWL<563> A_IWL<562> A_IWL<561> A_IWL<560> A_IWL<559> A_IWL<558> A_IWL<557> A_IWL<556> A_IWL<555> A_IWL<554> A_IWL<553> A_IWL<552> A_IWL<551> A_IWL<550> A_IWL<549> A_IWL<548> A_IWL<547> A_IWL<546> A_IWL<545> A_IWL<544> A_IWL<543> A_IWL<542> A_IWL<541> A_IWL<540> A_IWL<539> A_IWL<538> A_IWL<537> A_IWL<536> A_IWL<535> A_IWL<534> A_IWL<533> A_IWL<532> A_IWL<531> A_IWL<530> A_IWL<529> A_IWL<528> A_IWL<527> A_IWL<526> A_IWL<525> A_IWL<524> A_IWL<523> A_IWL<522> A_IWL<521> A_IWL<520> A_IWL<519> A_IWL<518> A_IWL<517> A_IWL<516> A_IWL<515> A_IWL<514> A_IWL<513> A_IWL<512> A_IWL<1023> A_IWL<1022> A_IWL<1021> A_IWL<1020> A_IWL<1019> A_IWL<1018> A_IWL<1017> A_IWL<1016> A_IWL<1015> A_IWL<1014> A_IWL<1013> A_IWL<1012> A_IWL<1011> A_IWL<1010> A_IWL<1009> A_IWL<1008> A_IWL<1007> A_IWL<1006> A_IWL<1005> A_IWL<1004> A_IWL<1003> A_IWL<1002> A_IWL<1001> A_IWL<1000> A_IWL<999> A_IWL<998> A_IWL<997> A_IWL<996> A_IWL<995> A_IWL<994> A_IWL<993> A_IWL<992> A_IWL<991> A_IWL<990> A_IWL<989> A_IWL<988> A_IWL<987> A_IWL<986> A_IWL<985> A_IWL<984> A_IWL<983> A_IWL<982> A_IWL<981> A_IWL<980> A_IWL<979> A_IWL<978> A_IWL<977> A_IWL<976> A_IWL<975> A_IWL<974> A_IWL<973> A_IWL<972> A_IWL<971> A_IWL<970> A_IWL<969> A_IWL<968> A_IWL<967> A_IWL<966> A_IWL<965> A_IWL<964> A_IWL<963> A_IWL<962> A_IWL<961> A_IWL<960> A_IWL<959> A_IWL<958> A_IWL<957> A_IWL<956> A_IWL<955> A_IWL<954> A_IWL<953> A_IWL<952> A_IWL<951> A_IWL<950> A_IWL<949> A_IWL<948> A_IWL<947> A_IWL<946> A_IWL<945> A_IWL<944> A_IWL<943> A_IWL<942> A_IWL<941> A_IWL<940> A_IWL<939> A_IWL<938> A_IWL<937> A_IWL<936> A_IWL<935> A_IWL<934> A_IWL<933> A_IWL<932> A_IWL<931> A_IWL<930> A_IWL<929> A_IWL<928> A_IWL<927> A_IWL<926> A_IWL<925> A_IWL<924> A_IWL<923> A_IWL<922> A_IWL<921> A_IWL<920> A_IWL<919> A_IWL<918> A_IWL<917> A_IWL<916> A_IWL<915> A_IWL<914> A_IWL<913> A_IWL<912> A_IWL<911> A_IWL<910> A_IWL<909> A_IWL<908> A_IWL<907> A_IWL<906> A_IWL<905> A_IWL<904> A_IWL<903> A_IWL<902> A_IWL<901> A_IWL<900> A_IWL<899> A_IWL<898> A_IWL<897> A_IWL<896> A_IWL<895> A_IWL<894> A_IWL<893> A_IWL<892> A_IWL<891> A_IWL<890> A_IWL<889> A_IWL<888> A_IWL<887> A_IWL<886> A_IWL<885> A_IWL<884> A_IWL<883> A_IWL<882> A_IWL<881> A_IWL<880> A_IWL<879> A_IWL<878> A_IWL<877> A_IWL<876> A_IWL<875> A_IWL<874> A_IWL<873> A_IWL<872> A_IWL<871> A_IWL<870> A_IWL<869> A_IWL<868> A_IWL<867> A_IWL<866> A_IWL<865> A_IWL<864> A_IWL<863> A_IWL<862> A_IWL<861> A_IWL<860> A_IWL<859> A_IWL<858> A_IWL<857> A_IWL<856> A_IWL<855> A_IWL<854> A_IWL<853> A_IWL<852> A_IWL<851> A_IWL<850> A_IWL<849> A_IWL<848> A_IWL<847> A_IWL<846> A_IWL<845> A_IWL<844> A_IWL<843> A_IWL<842> A_IWL<841> A_IWL<840> A_IWL<839> A_IWL<838> A_IWL<837> A_IWL<836> A_IWL<835> A_IWL<834> A_IWL<833> A_IWL<832> A_IWL<831> A_IWL<830> A_IWL<829> A_IWL<828> A_IWL<827> A_IWL<826> A_IWL<825> A_IWL<824> A_IWL<823> A_IWL<822> A_IWL<821> A_IWL<820> A_IWL<819> A_IWL<818> A_IWL<817> A_IWL<816> A_IWL<815> A_IWL<814> A_IWL<813> A_IWL<812> A_IWL<811> A_IWL<810> A_IWL<809> A_IWL<808> A_IWL<807> A_IWL<806> A_IWL<805> A_IWL<804> A_IWL<803> A_IWL<802> A_IWL<801> A_IWL<800> A_IWL<799> A_IWL<798> A_IWL<797> A_IWL<796> A_IWL<795> A_IWL<794> A_IWL<793> A_IWL<792> A_IWL<791> A_IWL<790> A_IWL<789> A_IWL<788> A_IWL<787> A_IWL<786> A_IWL<785> A_IWL<784> A_IWL<783> A_IWL<782> A_IWL<781> A_IWL<780> A_IWL<779> A_IWL<778> A_IWL<777> A_IWL<776> A_IWL<775> A_IWL<774> A_IWL<773> A_IWL<772> A_IWL<771> A_IWL<770> A_IWL<769> A_IWL<768> B_BLC<7> B_BLC<6> B_BLC_TOP<7> B_BLC_TOP<6> B_BLT<7> B_BLT<6> B_BLT_TOP<7> B_BLT_TOP<6> B_IWL<767> B_IWL<766> B_IWL<765> B_IWL<764> B_IWL<763> B_IWL<762> B_IWL<761> B_IWL<760> B_IWL<759> B_IWL<758> B_IWL<757> B_IWL<756> B_IWL<755> B_IWL<754> B_IWL<753> B_IWL<752> B_IWL<751> B_IWL<750> B_IWL<749> B_IWL<748> B_IWL<747> B_IWL<746> B_IWL<745> B_IWL<744> B_IWL<743> B_IWL<742> B_IWL<741> B_IWL<740> B_IWL<739> B_IWL<738> B_IWL<737> B_IWL<736> B_IWL<735> B_IWL<734> B_IWL<733> B_IWL<732> B_IWL<731> B_IWL<730> B_IWL<729> B_IWL<728> B_IWL<727> B_IWL<726> B_IWL<725> B_IWL<724> B_IWL<723> B_IWL<722> B_IWL<721> B_IWL<720> B_IWL<719> B_IWL<718> B_IWL<717> B_IWL<716> B_IWL<715> B_IWL<714> B_IWL<713> B_IWL<712> B_IWL<711> B_IWL<710> B_IWL<709> B_IWL<708> B_IWL<707> B_IWL<706> B_IWL<705> B_IWL<704> B_IWL<703> B_IWL<702> B_IWL<701> B_IWL<700> B_IWL<699> B_IWL<698> B_IWL<697> B_IWL<696> B_IWL<695> B_IWL<694> B_IWL<693> B_IWL<692> B_IWL<691> B_IWL<690> B_IWL<689> B_IWL<688> B_IWL<687> B_IWL<686> B_IWL<685> B_IWL<684> B_IWL<683> B_IWL<682> B_IWL<681> B_IWL<680> B_IWL<679> B_IWL<678> B_IWL<677> B_IWL<676> B_IWL<675> B_IWL<674> B_IWL<673> B_IWL<672> B_IWL<671> B_IWL<670> B_IWL<669> B_IWL<668> B_IWL<667> B_IWL<666> B_IWL<665> B_IWL<664> B_IWL<663> B_IWL<662> B_IWL<661> B_IWL<660> B_IWL<659> B_IWL<658> B_IWL<657> B_IWL<656> B_IWL<655> B_IWL<654> B_IWL<653> B_IWL<652> B_IWL<651> B_IWL<650> B_IWL<649> B_IWL<648> B_IWL<647> B_IWL<646> B_IWL<645> B_IWL<644> B_IWL<643> B_IWL<642> B_IWL<641> B_IWL<640> B_IWL<639> B_IWL<638> B_IWL<637> B_IWL<636> B_IWL<635> B_IWL<634> B_IWL<633> B_IWL<632> B_IWL<631> B_IWL<630> B_IWL<629> B_IWL<628> B_IWL<627> B_IWL<626> B_IWL<625> B_IWL<624> B_IWL<623> B_IWL<622> B_IWL<621> B_IWL<620> B_IWL<619> B_IWL<618> B_IWL<617> B_IWL<616> B_IWL<615> B_IWL<614> B_IWL<613> B_IWL<612> B_IWL<611> B_IWL<610> B_IWL<609> B_IWL<608> B_IWL<607> B_IWL<606> B_IWL<605> B_IWL<604> B_IWL<603> B_IWL<602> B_IWL<601> B_IWL<600> B_IWL<599> B_IWL<598> B_IWL<597> B_IWL<596> B_IWL<595> B_IWL<594> B_IWL<593> B_IWL<592> B_IWL<591> B_IWL<590> B_IWL<589> B_IWL<588> B_IWL<587> B_IWL<586> B_IWL<585> B_IWL<584> B_IWL<583> B_IWL<582> B_IWL<581> B_IWL<580> B_IWL<579> B_IWL<578> B_IWL<577> B_IWL<576> B_IWL<575> B_IWL<574> B_IWL<573> B_IWL<572> B_IWL<571> B_IWL<570> B_IWL<569> B_IWL<568> B_IWL<567> B_IWL<566> B_IWL<565> B_IWL<564> B_IWL<563> B_IWL<562> B_IWL<561> B_IWL<560> B_IWL<559> B_IWL<558> B_IWL<557> B_IWL<556> B_IWL<555> B_IWL<554> B_IWL<553> B_IWL<552> B_IWL<551> B_IWL<550> B_IWL<549> B_IWL<548> B_IWL<547> B_IWL<546> B_IWL<545> B_IWL<544> B_IWL<543> B_IWL<542> B_IWL<541> B_IWL<540> B_IWL<539> B_IWL<538> B_IWL<537> B_IWL<536> B_IWL<535> B_IWL<534> B_IWL<533> B_IWL<532> B_IWL<531> B_IWL<530> B_IWL<529> B_IWL<528> B_IWL<527> B_IWL<526> B_IWL<525> B_IWL<524> B_IWL<523> B_IWL<522> B_IWL<521> B_IWL<520> B_IWL<519> B_IWL<518> B_IWL<517> B_IWL<516> B_IWL<515> B_IWL<514> B_IWL<513> B_IWL<512> B_IWL<1023> B_IWL<1022> B_IWL<1021> B_IWL<1020> B_IWL<1019> B_IWL<1018> B_IWL<1017> B_IWL<1016> B_IWL<1015> B_IWL<1014> B_IWL<1013> B_IWL<1012> B_IWL<1011> B_IWL<1010> B_IWL<1009> B_IWL<1008> B_IWL<1007> B_IWL<1006> B_IWL<1005> B_IWL<1004> B_IWL<1003> B_IWL<1002> B_IWL<1001> B_IWL<1000> B_IWL<999> B_IWL<998> B_IWL<997> B_IWL<996> B_IWL<995> B_IWL<994> B_IWL<993> B_IWL<992> B_IWL<991> B_IWL<990> B_IWL<989> B_IWL<988> B_IWL<987> B_IWL<986> B_IWL<985> B_IWL<984> B_IWL<983> B_IWL<982> B_IWL<981> B_IWL<980> B_IWL<979> B_IWL<978> B_IWL<977> B_IWL<976> B_IWL<975> B_IWL<974> B_IWL<973> B_IWL<972> B_IWL<971> B_IWL<970> B_IWL<969> B_IWL<968> B_IWL<967> B_IWL<966> B_IWL<965> B_IWL<964> B_IWL<963> B_IWL<962> B_IWL<961> B_IWL<960> B_IWL<959> B_IWL<958> B_IWL<957> B_IWL<956> B_IWL<955> B_IWL<954> B_IWL<953> B_IWL<952> B_IWL<951> B_IWL<950> B_IWL<949> B_IWL<948> B_IWL<947> B_IWL<946> B_IWL<945> B_IWL<944> B_IWL<943> B_IWL<942> B_IWL<941> B_IWL<940> B_IWL<939> B_IWL<938> B_IWL<937> B_IWL<936> B_IWL<935> B_IWL<934> B_IWL<933> B_IWL<932> B_IWL<931> B_IWL<930> B_IWL<929> B_IWL<928> B_IWL<927> B_IWL<926> B_IWL<925> B_IWL<924> B_IWL<923> B_IWL<922> B_IWL<921> B_IWL<920> B_IWL<919> B_IWL<918> B_IWL<917> B_IWL<916> B_IWL<915> B_IWL<914> B_IWL<913> B_IWL<912> B_IWL<911> B_IWL<910> B_IWL<909> B_IWL<908> B_IWL<907> B_IWL<906> B_IWL<905> B_IWL<904> B_IWL<903> B_IWL<902> B_IWL<901> B_IWL<900> B_IWL<899> B_IWL<898> B_IWL<897> B_IWL<896> B_IWL<895> B_IWL<894> B_IWL<893> B_IWL<892> B_IWL<891> B_IWL<890> B_IWL<889> B_IWL<888> B_IWL<887> B_IWL<886> B_IWL<885> B_IWL<884> B_IWL<883> B_IWL<882> B_IWL<881> B_IWL<880> B_IWL<879> B_IWL<878> B_IWL<877> B_IWL<876> B_IWL<875> B_IWL<874> B_IWL<873> B_IWL<872> B_IWL<871> B_IWL<870> B_IWL<869> B_IWL<868> B_IWL<867> B_IWL<866> B_IWL<865> B_IWL<864> B_IWL<863> B_IWL<862> B_IWL<861> B_IWL<860> B_IWL<859> B_IWL<858> B_IWL<857> B_IWL<856> B_IWL<855> B_IWL<854> B_IWL<853> B_IWL<852> B_IWL<851> B_IWL<850> B_IWL<849> B_IWL<848> B_IWL<847> B_IWL<846> B_IWL<845> B_IWL<844> B_IWL<843> B_IWL<842> B_IWL<841> B_IWL<840> B_IWL<839> B_IWL<838> B_IWL<837> B_IWL<836> B_IWL<835> B_IWL<834> B_IWL<833> B_IWL<832> B_IWL<831> B_IWL<830> B_IWL<829> B_IWL<828> B_IWL<827> B_IWL<826> B_IWL<825> B_IWL<824> B_IWL<823> B_IWL<822> B_IWL<821> B_IWL<820> B_IWL<819> B_IWL<818> B_IWL<817> B_IWL<816> B_IWL<815> B_IWL<814> B_IWL<813> B_IWL<812> B_IWL<811> B_IWL<810> B_IWL<809> B_IWL<808> B_IWL<807> B_IWL<806> B_IWL<805> B_IWL<804> B_IWL<803> B_IWL<802> B_IWL<801> B_IWL<800> B_IWL<799> B_IWL<798> B_IWL<797> B_IWL<796> B_IWL<795> B_IWL<794> B_IWL<793> B_IWL<792> B_IWL<791> B_IWL<790> B_IWL<789> B_IWL<788> B_IWL<787> B_IWL<786> B_IWL<785> B_IWL<784> B_IWL<783> B_IWL<782> B_IWL<781> B_IWL<780> B_IWL<779> B_IWL<778> B_IWL<777> B_IWL<776> B_IWL<775> B_IWL<774> B_IWL<773> B_IWL<772> B_IWL<771> B_IWL<770> B_IWL<769> B_IWL<768> VDD_CORE VSS / RM_IHPSG13_1024x16_c2_2P_COLUMN_pcell_0 +XCOL<2> A_BLC<5> A_BLC<4> A_BLC_TOP<5> A_BLC_TOP<4> A_BLT<5> A_BLT<4> A_BLT_TOP<5> A_BLT_TOP<4> A_IWL<511> A_IWL<510> A_IWL<509> A_IWL<508> A_IWL<507> A_IWL<506> A_IWL<505> A_IWL<504> A_IWL<503> A_IWL<502> A_IWL<501> A_IWL<500> A_IWL<499> A_IWL<498> A_IWL<497> A_IWL<496> A_IWL<495> A_IWL<494> A_IWL<493> A_IWL<492> A_IWL<491> A_IWL<490> A_IWL<489> A_IWL<488> A_IWL<487> A_IWL<486> A_IWL<485> A_IWL<484> A_IWL<483> A_IWL<482> A_IWL<481> A_IWL<480> A_IWL<479> A_IWL<478> A_IWL<477> A_IWL<476> A_IWL<475> A_IWL<474> A_IWL<473> A_IWL<472> A_IWL<471> A_IWL<470> A_IWL<469> A_IWL<468> A_IWL<467> A_IWL<466> A_IWL<465> A_IWL<464> A_IWL<463> A_IWL<462> A_IWL<461> A_IWL<460> A_IWL<459> A_IWL<458> A_IWL<457> A_IWL<456> A_IWL<455> A_IWL<454> A_IWL<453> A_IWL<452> A_IWL<451> A_IWL<450> A_IWL<449> A_IWL<448> A_IWL<447> A_IWL<446> A_IWL<445> A_IWL<444> A_IWL<443> A_IWL<442> A_IWL<441> A_IWL<440> A_IWL<439> A_IWL<438> A_IWL<437> A_IWL<436> A_IWL<435> A_IWL<434> A_IWL<433> A_IWL<432> A_IWL<431> A_IWL<430> A_IWL<429> A_IWL<428> A_IWL<427> A_IWL<426> A_IWL<425> A_IWL<424> A_IWL<423> A_IWL<422> A_IWL<421> A_IWL<420> A_IWL<419> A_IWL<418> A_IWL<417> A_IWL<416> A_IWL<415> A_IWL<414> A_IWL<413> A_IWL<412> A_IWL<411> A_IWL<410> A_IWL<409> A_IWL<408> A_IWL<407> A_IWL<406> A_IWL<405> A_IWL<404> A_IWL<403> A_IWL<402> A_IWL<401> A_IWL<400> A_IWL<399> A_IWL<398> A_IWL<397> A_IWL<396> A_IWL<395> A_IWL<394> A_IWL<393> A_IWL<392> A_IWL<391> A_IWL<390> A_IWL<389> A_IWL<388> A_IWL<387> A_IWL<386> A_IWL<385> A_IWL<384> A_IWL<383> A_IWL<382> A_IWL<381> A_IWL<380> A_IWL<379> A_IWL<378> A_IWL<377> A_IWL<376> A_IWL<375> A_IWL<374> A_IWL<373> A_IWL<372> A_IWL<371> A_IWL<370> A_IWL<369> A_IWL<368> A_IWL<367> A_IWL<366> A_IWL<365> A_IWL<364> A_IWL<363> A_IWL<362> A_IWL<361> A_IWL<360> A_IWL<359> A_IWL<358> A_IWL<357> A_IWL<356> A_IWL<355> A_IWL<354> A_IWL<353> A_IWL<352> A_IWL<351> A_IWL<350> A_IWL<349> A_IWL<348> A_IWL<347> A_IWL<346> A_IWL<345> A_IWL<344> A_IWL<343> A_IWL<342> A_IWL<341> A_IWL<340> A_IWL<339> A_IWL<338> A_IWL<337> A_IWL<336> A_IWL<335> A_IWL<334> A_IWL<333> A_IWL<332> A_IWL<331> A_IWL<330> A_IWL<329> A_IWL<328> A_IWL<327> A_IWL<326> A_IWL<325> A_IWL<324> A_IWL<323> A_IWL<322> A_IWL<321> A_IWL<320> A_IWL<319> A_IWL<318> A_IWL<317> A_IWL<316> A_IWL<315> A_IWL<314> A_IWL<313> A_IWL<312> A_IWL<311> A_IWL<310> A_IWL<309> A_IWL<308> A_IWL<307> A_IWL<306> A_IWL<305> A_IWL<304> A_IWL<303> A_IWL<302> A_IWL<301> A_IWL<300> A_IWL<299> A_IWL<298> A_IWL<297> A_IWL<296> A_IWL<295> A_IWL<294> A_IWL<293> A_IWL<292> A_IWL<291> A_IWL<290> A_IWL<289> A_IWL<288> A_IWL<287> A_IWL<286> A_IWL<285> A_IWL<284> A_IWL<283> A_IWL<282> A_IWL<281> A_IWL<280> A_IWL<279> A_IWL<278> A_IWL<277> A_IWL<276> A_IWL<275> A_IWL<274> A_IWL<273> A_IWL<272> A_IWL<271> A_IWL<270> A_IWL<269> A_IWL<268> A_IWL<267> A_IWL<266> A_IWL<265> A_IWL<264> A_IWL<263> A_IWL<262> A_IWL<261> A_IWL<260> A_IWL<259> A_IWL<258> A_IWL<257> A_IWL<256> A_IWL<767> A_IWL<766> A_IWL<765> A_IWL<764> A_IWL<763> A_IWL<762> A_IWL<761> A_IWL<760> A_IWL<759> A_IWL<758> A_IWL<757> A_IWL<756> A_IWL<755> A_IWL<754> A_IWL<753> A_IWL<752> A_IWL<751> A_IWL<750> A_IWL<749> A_IWL<748> A_IWL<747> A_IWL<746> A_IWL<745> A_IWL<744> A_IWL<743> A_IWL<742> A_IWL<741> A_IWL<740> A_IWL<739> A_IWL<738> A_IWL<737> A_IWL<736> A_IWL<735> A_IWL<734> A_IWL<733> A_IWL<732> A_IWL<731> A_IWL<730> A_IWL<729> A_IWL<728> A_IWL<727> A_IWL<726> A_IWL<725> A_IWL<724> A_IWL<723> A_IWL<722> A_IWL<721> A_IWL<720> A_IWL<719> A_IWL<718> A_IWL<717> A_IWL<716> A_IWL<715> A_IWL<714> A_IWL<713> A_IWL<712> A_IWL<711> A_IWL<710> A_IWL<709> A_IWL<708> A_IWL<707> A_IWL<706> A_IWL<705> A_IWL<704> A_IWL<703> A_IWL<702> A_IWL<701> A_IWL<700> A_IWL<699> A_IWL<698> A_IWL<697> A_IWL<696> A_IWL<695> A_IWL<694> A_IWL<693> A_IWL<692> A_IWL<691> A_IWL<690> A_IWL<689> A_IWL<688> A_IWL<687> A_IWL<686> A_IWL<685> A_IWL<684> A_IWL<683> A_IWL<682> A_IWL<681> A_IWL<680> A_IWL<679> A_IWL<678> A_IWL<677> A_IWL<676> A_IWL<675> A_IWL<674> A_IWL<673> A_IWL<672> A_IWL<671> A_IWL<670> A_IWL<669> A_IWL<668> A_IWL<667> A_IWL<666> A_IWL<665> A_IWL<664> A_IWL<663> A_IWL<662> A_IWL<661> A_IWL<660> A_IWL<659> A_IWL<658> A_IWL<657> A_IWL<656> A_IWL<655> A_IWL<654> A_IWL<653> A_IWL<652> A_IWL<651> A_IWL<650> A_IWL<649> A_IWL<648> A_IWL<647> A_IWL<646> A_IWL<645> A_IWL<644> A_IWL<643> A_IWL<642> A_IWL<641> A_IWL<640> A_IWL<639> A_IWL<638> A_IWL<637> A_IWL<636> A_IWL<635> A_IWL<634> A_IWL<633> A_IWL<632> A_IWL<631> A_IWL<630> A_IWL<629> A_IWL<628> A_IWL<627> A_IWL<626> A_IWL<625> A_IWL<624> A_IWL<623> A_IWL<622> A_IWL<621> A_IWL<620> A_IWL<619> A_IWL<618> A_IWL<617> A_IWL<616> A_IWL<615> A_IWL<614> A_IWL<613> A_IWL<612> A_IWL<611> A_IWL<610> A_IWL<609> A_IWL<608> A_IWL<607> A_IWL<606> A_IWL<605> A_IWL<604> A_IWL<603> A_IWL<602> A_IWL<601> A_IWL<600> A_IWL<599> A_IWL<598> A_IWL<597> A_IWL<596> A_IWL<595> A_IWL<594> A_IWL<593> A_IWL<592> A_IWL<591> A_IWL<590> A_IWL<589> A_IWL<588> A_IWL<587> A_IWL<586> A_IWL<585> A_IWL<584> A_IWL<583> A_IWL<582> A_IWL<581> A_IWL<580> A_IWL<579> A_IWL<578> A_IWL<577> A_IWL<576> A_IWL<575> A_IWL<574> A_IWL<573> A_IWL<572> A_IWL<571> A_IWL<570> A_IWL<569> A_IWL<568> A_IWL<567> A_IWL<566> A_IWL<565> A_IWL<564> A_IWL<563> A_IWL<562> A_IWL<561> A_IWL<560> A_IWL<559> A_IWL<558> A_IWL<557> A_IWL<556> A_IWL<555> A_IWL<554> A_IWL<553> A_IWL<552> A_IWL<551> A_IWL<550> A_IWL<549> A_IWL<548> A_IWL<547> A_IWL<546> A_IWL<545> A_IWL<544> A_IWL<543> A_IWL<542> A_IWL<541> A_IWL<540> A_IWL<539> A_IWL<538> A_IWL<537> A_IWL<536> A_IWL<535> A_IWL<534> A_IWL<533> A_IWL<532> A_IWL<531> A_IWL<530> A_IWL<529> A_IWL<528> A_IWL<527> A_IWL<526> A_IWL<525> A_IWL<524> A_IWL<523> A_IWL<522> A_IWL<521> A_IWL<520> A_IWL<519> A_IWL<518> A_IWL<517> A_IWL<516> A_IWL<515> A_IWL<514> A_IWL<513> A_IWL<512> B_BLC<5> B_BLC<4> B_BLC_TOP<5> B_BLC_TOP<4> B_BLT<5> B_BLT<4> B_BLT_TOP<5> B_BLT_TOP<4> B_IWL<511> B_IWL<510> B_IWL<509> B_IWL<508> B_IWL<507> B_IWL<506> B_IWL<505> B_IWL<504> B_IWL<503> B_IWL<502> B_IWL<501> B_IWL<500> B_IWL<499> B_IWL<498> B_IWL<497> B_IWL<496> B_IWL<495> B_IWL<494> B_IWL<493> B_IWL<492> B_IWL<491> B_IWL<490> B_IWL<489> B_IWL<488> B_IWL<487> B_IWL<486> B_IWL<485> B_IWL<484> B_IWL<483> B_IWL<482> B_IWL<481> B_IWL<480> B_IWL<479> B_IWL<478> B_IWL<477> B_IWL<476> B_IWL<475> B_IWL<474> B_IWL<473> B_IWL<472> B_IWL<471> B_IWL<470> B_IWL<469> B_IWL<468> B_IWL<467> B_IWL<466> B_IWL<465> B_IWL<464> B_IWL<463> B_IWL<462> B_IWL<461> B_IWL<460> B_IWL<459> B_IWL<458> B_IWL<457> B_IWL<456> B_IWL<455> B_IWL<454> B_IWL<453> B_IWL<452> B_IWL<451> B_IWL<450> B_IWL<449> B_IWL<448> B_IWL<447> B_IWL<446> B_IWL<445> B_IWL<444> B_IWL<443> B_IWL<442> B_IWL<441> B_IWL<440> B_IWL<439> B_IWL<438> B_IWL<437> B_IWL<436> B_IWL<435> B_IWL<434> B_IWL<433> B_IWL<432> B_IWL<431> B_IWL<430> B_IWL<429> B_IWL<428> B_IWL<427> B_IWL<426> B_IWL<425> B_IWL<424> B_IWL<423> B_IWL<422> B_IWL<421> B_IWL<420> B_IWL<419> B_IWL<418> B_IWL<417> B_IWL<416> B_IWL<415> B_IWL<414> B_IWL<413> B_IWL<412> B_IWL<411> B_IWL<410> B_IWL<409> B_IWL<408> B_IWL<407> B_IWL<406> B_IWL<405> B_IWL<404> B_IWL<403> B_IWL<402> B_IWL<401> B_IWL<400> B_IWL<399> B_IWL<398> B_IWL<397> B_IWL<396> B_IWL<395> B_IWL<394> B_IWL<393> B_IWL<392> B_IWL<391> B_IWL<390> B_IWL<389> B_IWL<388> B_IWL<387> B_IWL<386> B_IWL<385> B_IWL<384> B_IWL<383> B_IWL<382> B_IWL<381> B_IWL<380> B_IWL<379> B_IWL<378> B_IWL<377> B_IWL<376> B_IWL<375> B_IWL<374> B_IWL<373> B_IWL<372> B_IWL<371> B_IWL<370> B_IWL<369> B_IWL<368> B_IWL<367> B_IWL<366> B_IWL<365> B_IWL<364> B_IWL<363> B_IWL<362> B_IWL<361> B_IWL<360> B_IWL<359> B_IWL<358> B_IWL<357> B_IWL<356> B_IWL<355> B_IWL<354> B_IWL<353> B_IWL<352> B_IWL<351> B_IWL<350> B_IWL<349> B_IWL<348> B_IWL<347> B_IWL<346> B_IWL<345> B_IWL<344> B_IWL<343> B_IWL<342> B_IWL<341> B_IWL<340> B_IWL<339> B_IWL<338> B_IWL<337> B_IWL<336> B_IWL<335> B_IWL<334> B_IWL<333> B_IWL<332> B_IWL<331> B_IWL<330> B_IWL<329> B_IWL<328> B_IWL<327> B_IWL<326> B_IWL<325> B_IWL<324> B_IWL<323> B_IWL<322> B_IWL<321> B_IWL<320> B_IWL<319> B_IWL<318> B_IWL<317> B_IWL<316> B_IWL<315> B_IWL<314> B_IWL<313> B_IWL<312> B_IWL<311> B_IWL<310> B_IWL<309> B_IWL<308> B_IWL<307> B_IWL<306> B_IWL<305> B_IWL<304> B_IWL<303> B_IWL<302> B_IWL<301> B_IWL<300> B_IWL<299> B_IWL<298> B_IWL<297> B_IWL<296> B_IWL<295> B_IWL<294> B_IWL<293> B_IWL<292> B_IWL<291> B_IWL<290> B_IWL<289> B_IWL<288> B_IWL<287> B_IWL<286> B_IWL<285> B_IWL<284> B_IWL<283> B_IWL<282> B_IWL<281> B_IWL<280> B_IWL<279> B_IWL<278> B_IWL<277> B_IWL<276> B_IWL<275> B_IWL<274> B_IWL<273> B_IWL<272> B_IWL<271> B_IWL<270> B_IWL<269> B_IWL<268> B_IWL<267> B_IWL<266> B_IWL<265> B_IWL<264> B_IWL<263> B_IWL<262> B_IWL<261> B_IWL<260> B_IWL<259> B_IWL<258> B_IWL<257> B_IWL<256> B_IWL<767> B_IWL<766> B_IWL<765> B_IWL<764> B_IWL<763> B_IWL<762> B_IWL<761> B_IWL<760> B_IWL<759> B_IWL<758> B_IWL<757> B_IWL<756> B_IWL<755> B_IWL<754> B_IWL<753> B_IWL<752> B_IWL<751> B_IWL<750> B_IWL<749> B_IWL<748> B_IWL<747> B_IWL<746> B_IWL<745> B_IWL<744> B_IWL<743> B_IWL<742> B_IWL<741> B_IWL<740> B_IWL<739> B_IWL<738> B_IWL<737> B_IWL<736> B_IWL<735> B_IWL<734> B_IWL<733> B_IWL<732> B_IWL<731> B_IWL<730> B_IWL<729> B_IWL<728> B_IWL<727> B_IWL<726> B_IWL<725> B_IWL<724> B_IWL<723> B_IWL<722> B_IWL<721> B_IWL<720> B_IWL<719> B_IWL<718> B_IWL<717> B_IWL<716> B_IWL<715> B_IWL<714> B_IWL<713> B_IWL<712> B_IWL<711> B_IWL<710> B_IWL<709> B_IWL<708> B_IWL<707> B_IWL<706> B_IWL<705> B_IWL<704> B_IWL<703> B_IWL<702> B_IWL<701> B_IWL<700> B_IWL<699> B_IWL<698> B_IWL<697> B_IWL<696> B_IWL<695> B_IWL<694> B_IWL<693> B_IWL<692> B_IWL<691> B_IWL<690> B_IWL<689> B_IWL<688> B_IWL<687> B_IWL<686> B_IWL<685> B_IWL<684> B_IWL<683> B_IWL<682> B_IWL<681> B_IWL<680> B_IWL<679> B_IWL<678> B_IWL<677> B_IWL<676> B_IWL<675> B_IWL<674> B_IWL<673> B_IWL<672> B_IWL<671> B_IWL<670> B_IWL<669> B_IWL<668> B_IWL<667> B_IWL<666> B_IWL<665> B_IWL<664> B_IWL<663> B_IWL<662> B_IWL<661> B_IWL<660> B_IWL<659> B_IWL<658> B_IWL<657> B_IWL<656> B_IWL<655> B_IWL<654> B_IWL<653> B_IWL<652> B_IWL<651> B_IWL<650> B_IWL<649> B_IWL<648> B_IWL<647> B_IWL<646> B_IWL<645> B_IWL<644> B_IWL<643> B_IWL<642> B_IWL<641> B_IWL<640> B_IWL<639> B_IWL<638> B_IWL<637> B_IWL<636> B_IWL<635> B_IWL<634> B_IWL<633> B_IWL<632> B_IWL<631> B_IWL<630> B_IWL<629> B_IWL<628> B_IWL<627> B_IWL<626> B_IWL<625> B_IWL<624> B_IWL<623> B_IWL<622> B_IWL<621> B_IWL<620> B_IWL<619> B_IWL<618> B_IWL<617> B_IWL<616> B_IWL<615> B_IWL<614> B_IWL<613> B_IWL<612> B_IWL<611> B_IWL<610> B_IWL<609> B_IWL<608> B_IWL<607> B_IWL<606> B_IWL<605> B_IWL<604> B_IWL<603> B_IWL<602> B_IWL<601> B_IWL<600> B_IWL<599> B_IWL<598> B_IWL<597> B_IWL<596> B_IWL<595> B_IWL<594> B_IWL<593> B_IWL<592> B_IWL<591> B_IWL<590> B_IWL<589> B_IWL<588> B_IWL<587> B_IWL<586> B_IWL<585> B_IWL<584> B_IWL<583> B_IWL<582> B_IWL<581> B_IWL<580> B_IWL<579> B_IWL<578> B_IWL<577> B_IWL<576> B_IWL<575> B_IWL<574> B_IWL<573> B_IWL<572> B_IWL<571> B_IWL<570> B_IWL<569> B_IWL<568> B_IWL<567> B_IWL<566> B_IWL<565> B_IWL<564> B_IWL<563> B_IWL<562> B_IWL<561> B_IWL<560> B_IWL<559> B_IWL<558> B_IWL<557> B_IWL<556> B_IWL<555> B_IWL<554> B_IWL<553> B_IWL<552> B_IWL<551> B_IWL<550> B_IWL<549> B_IWL<548> B_IWL<547> B_IWL<546> B_IWL<545> B_IWL<544> B_IWL<543> B_IWL<542> B_IWL<541> B_IWL<540> B_IWL<539> B_IWL<538> B_IWL<537> B_IWL<536> B_IWL<535> B_IWL<534> B_IWL<533> B_IWL<532> B_IWL<531> B_IWL<530> B_IWL<529> B_IWL<528> B_IWL<527> B_IWL<526> B_IWL<525> B_IWL<524> B_IWL<523> B_IWL<522> B_IWL<521> B_IWL<520> B_IWL<519> B_IWL<518> B_IWL<517> B_IWL<516> B_IWL<515> B_IWL<514> B_IWL<513> B_IWL<512> VDD_CORE VSS / RM_IHPSG13_1024x16_c2_2P_COLUMN_pcell_0 +XCOL<1> A_BLC<3> A_BLC<2> A_BLC_TOP<3> A_BLC_TOP<2> A_BLT<3> A_BLT<2> A_BLT_TOP<3> A_BLT_TOP<2> A_IWL<255> A_IWL<254> A_IWL<253> A_IWL<252> A_IWL<251> A_IWL<250> A_IWL<249> A_IWL<248> A_IWL<247> A_IWL<246> A_IWL<245> A_IWL<244> A_IWL<243> A_IWL<242> A_IWL<241> A_IWL<240> A_IWL<239> A_IWL<238> A_IWL<237> A_IWL<236> A_IWL<235> A_IWL<234> A_IWL<233> A_IWL<232> A_IWL<231> A_IWL<230> A_IWL<229> A_IWL<228> A_IWL<227> A_IWL<226> A_IWL<225> A_IWL<224> A_IWL<223> A_IWL<222> A_IWL<221> A_IWL<220> A_IWL<219> A_IWL<218> A_IWL<217> A_IWL<216> A_IWL<215> A_IWL<214> A_IWL<213> A_IWL<212> A_IWL<211> A_IWL<210> A_IWL<209> A_IWL<208> A_IWL<207> A_IWL<206> A_IWL<205> A_IWL<204> A_IWL<203> A_IWL<202> A_IWL<201> A_IWL<200> A_IWL<199> A_IWL<198> A_IWL<197> A_IWL<196> A_IWL<195> A_IWL<194> A_IWL<193> A_IWL<192> A_IWL<191> A_IWL<190> A_IWL<189> A_IWL<188> A_IWL<187> A_IWL<186> A_IWL<185> A_IWL<184> A_IWL<183> A_IWL<182> A_IWL<181> A_IWL<180> A_IWL<179> A_IWL<178> A_IWL<177> A_IWL<176> A_IWL<175> A_IWL<174> A_IWL<173> A_IWL<172> A_IWL<171> A_IWL<170> A_IWL<169> A_IWL<168> A_IWL<167> A_IWL<166> A_IWL<165> A_IWL<164> A_IWL<163> A_IWL<162> A_IWL<161> A_IWL<160> A_IWL<159> A_IWL<158> A_IWL<157> A_IWL<156> A_IWL<155> A_IWL<154> A_IWL<153> A_IWL<152> A_IWL<151> A_IWL<150> A_IWL<149> A_IWL<148> A_IWL<147> A_IWL<146> A_IWL<145> A_IWL<144> A_IWL<143> A_IWL<142> A_IWL<141> A_IWL<140> A_IWL<139> A_IWL<138> A_IWL<137> A_IWL<136> A_IWL<135> A_IWL<134> A_IWL<133> A_IWL<132> A_IWL<131> A_IWL<130> A_IWL<129> A_IWL<128> A_IWL<127> A_IWL<126> A_IWL<125> A_IWL<124> A_IWL<123> A_IWL<122> A_IWL<121> A_IWL<120> A_IWL<119> A_IWL<118> A_IWL<117> A_IWL<116> A_IWL<115> A_IWL<114> A_IWL<113> A_IWL<112> A_IWL<111> A_IWL<110> A_IWL<109> A_IWL<108> A_IWL<107> A_IWL<106> A_IWL<105> A_IWL<104> A_IWL<103> A_IWL<102> A_IWL<101> A_IWL<100> A_IWL<99> A_IWL<98> A_IWL<97> A_IWL<96> A_IWL<95> A_IWL<94> A_IWL<93> A_IWL<92> A_IWL<91> A_IWL<90> A_IWL<89> A_IWL<88> A_IWL<87> A_IWL<86> A_IWL<85> A_IWL<84> A_IWL<83> A_IWL<82> A_IWL<81> A_IWL<80> A_IWL<79> A_IWL<78> A_IWL<77> A_IWL<76> A_IWL<75> A_IWL<74> A_IWL<73> A_IWL<72> A_IWL<71> A_IWL<70> A_IWL<69> A_IWL<68> A_IWL<67> A_IWL<66> A_IWL<65> A_IWL<64> A_IWL<63> A_IWL<62> A_IWL<61> A_IWL<60> A_IWL<59> A_IWL<58> A_IWL<57> A_IWL<56> A_IWL<55> A_IWL<54> A_IWL<53> A_IWL<52> A_IWL<51> A_IWL<50> A_IWL<49> A_IWL<48> A_IWL<47> A_IWL<46> A_IWL<45> A_IWL<44> A_IWL<43> A_IWL<42> A_IWL<41> A_IWL<40> A_IWL<39> A_IWL<38> A_IWL<37> A_IWL<36> A_IWL<35> A_IWL<34> A_IWL<33> A_IWL<32> A_IWL<31> A_IWL<30> A_IWL<29> A_IWL<28> A_IWL<27> A_IWL<26> A_IWL<25> A_IWL<24> A_IWL<23> A_IWL<22> A_IWL<21> A_IWL<20> A_IWL<19> A_IWL<18> A_IWL<17> A_IWL<16> A_IWL<15> A_IWL<14> A_IWL<13> A_IWL<12> A_IWL<11> A_IWL<10> A_IWL<9> A_IWL<8> A_IWL<7> A_IWL<6> A_IWL<5> A_IWL<4> A_IWL<3> A_IWL<2> A_IWL<1> A_IWL<0> A_IWL<511> A_IWL<510> A_IWL<509> A_IWL<508> A_IWL<507> A_IWL<506> A_IWL<505> A_IWL<504> A_IWL<503> A_IWL<502> A_IWL<501> A_IWL<500> A_IWL<499> A_IWL<498> A_IWL<497> A_IWL<496> A_IWL<495> A_IWL<494> A_IWL<493> A_IWL<492> A_IWL<491> A_IWL<490> A_IWL<489> A_IWL<488> A_IWL<487> A_IWL<486> A_IWL<485> A_IWL<484> A_IWL<483> A_IWL<482> A_IWL<481> A_IWL<480> A_IWL<479> A_IWL<478> A_IWL<477> A_IWL<476> A_IWL<475> A_IWL<474> A_IWL<473> A_IWL<472> A_IWL<471> A_IWL<470> A_IWL<469> A_IWL<468> A_IWL<467> A_IWL<466> A_IWL<465> A_IWL<464> A_IWL<463> A_IWL<462> A_IWL<461> A_IWL<460> A_IWL<459> A_IWL<458> A_IWL<457> A_IWL<456> A_IWL<455> A_IWL<454> A_IWL<453> A_IWL<452> A_IWL<451> A_IWL<450> A_IWL<449> A_IWL<448> A_IWL<447> A_IWL<446> A_IWL<445> A_IWL<444> A_IWL<443> A_IWL<442> A_IWL<441> A_IWL<440> A_IWL<439> A_IWL<438> A_IWL<437> A_IWL<436> A_IWL<435> A_IWL<434> A_IWL<433> A_IWL<432> A_IWL<431> A_IWL<430> A_IWL<429> A_IWL<428> A_IWL<427> A_IWL<426> A_IWL<425> A_IWL<424> A_IWL<423> A_IWL<422> A_IWL<421> A_IWL<420> A_IWL<419> A_IWL<418> A_IWL<417> A_IWL<416> A_IWL<415> A_IWL<414> A_IWL<413> A_IWL<412> A_IWL<411> A_IWL<410> A_IWL<409> A_IWL<408> A_IWL<407> A_IWL<406> A_IWL<405> A_IWL<404> A_IWL<403> A_IWL<402> A_IWL<401> A_IWL<400> A_IWL<399> A_IWL<398> A_IWL<397> A_IWL<396> A_IWL<395> A_IWL<394> A_IWL<393> A_IWL<392> A_IWL<391> A_IWL<390> A_IWL<389> A_IWL<388> A_IWL<387> A_IWL<386> A_IWL<385> A_IWL<384> A_IWL<383> A_IWL<382> A_IWL<381> A_IWL<380> A_IWL<379> A_IWL<378> A_IWL<377> A_IWL<376> A_IWL<375> A_IWL<374> A_IWL<373> A_IWL<372> A_IWL<371> A_IWL<370> A_IWL<369> A_IWL<368> A_IWL<367> A_IWL<366> A_IWL<365> A_IWL<364> A_IWL<363> A_IWL<362> A_IWL<361> A_IWL<360> A_IWL<359> A_IWL<358> A_IWL<357> A_IWL<356> A_IWL<355> A_IWL<354> A_IWL<353> A_IWL<352> A_IWL<351> A_IWL<350> A_IWL<349> A_IWL<348> A_IWL<347> A_IWL<346> A_IWL<345> A_IWL<344> A_IWL<343> A_IWL<342> A_IWL<341> A_IWL<340> A_IWL<339> A_IWL<338> A_IWL<337> A_IWL<336> A_IWL<335> A_IWL<334> A_IWL<333> A_IWL<332> A_IWL<331> A_IWL<330> A_IWL<329> A_IWL<328> A_IWL<327> A_IWL<326> A_IWL<325> A_IWL<324> A_IWL<323> A_IWL<322> A_IWL<321> A_IWL<320> A_IWL<319> A_IWL<318> A_IWL<317> A_IWL<316> A_IWL<315> A_IWL<314> A_IWL<313> A_IWL<312> A_IWL<311> A_IWL<310> A_IWL<309> A_IWL<308> A_IWL<307> A_IWL<306> A_IWL<305> A_IWL<304> A_IWL<303> A_IWL<302> A_IWL<301> A_IWL<300> A_IWL<299> A_IWL<298> A_IWL<297> A_IWL<296> A_IWL<295> A_IWL<294> A_IWL<293> A_IWL<292> A_IWL<291> A_IWL<290> A_IWL<289> A_IWL<288> A_IWL<287> A_IWL<286> A_IWL<285> A_IWL<284> A_IWL<283> A_IWL<282> A_IWL<281> A_IWL<280> A_IWL<279> A_IWL<278> A_IWL<277> A_IWL<276> A_IWL<275> A_IWL<274> A_IWL<273> A_IWL<272> A_IWL<271> A_IWL<270> A_IWL<269> A_IWL<268> A_IWL<267> A_IWL<266> A_IWL<265> A_IWL<264> A_IWL<263> A_IWL<262> A_IWL<261> A_IWL<260> A_IWL<259> A_IWL<258> A_IWL<257> A_IWL<256> B_BLC<3> B_BLC<2> B_BLC_TOP<3> B_BLC_TOP<2> B_BLT<3> B_BLT<2> B_BLT_TOP<3> B_BLT_TOP<2> B_IWL<255> B_IWL<254> B_IWL<253> B_IWL<252> B_IWL<251> B_IWL<250> B_IWL<249> B_IWL<248> B_IWL<247> B_IWL<246> B_IWL<245> B_IWL<244> B_IWL<243> B_IWL<242> B_IWL<241> B_IWL<240> B_IWL<239> B_IWL<238> B_IWL<237> B_IWL<236> B_IWL<235> B_IWL<234> B_IWL<233> B_IWL<232> B_IWL<231> B_IWL<230> B_IWL<229> B_IWL<228> B_IWL<227> B_IWL<226> B_IWL<225> B_IWL<224> B_IWL<223> B_IWL<222> B_IWL<221> B_IWL<220> B_IWL<219> B_IWL<218> B_IWL<217> B_IWL<216> B_IWL<215> B_IWL<214> B_IWL<213> B_IWL<212> B_IWL<211> B_IWL<210> B_IWL<209> B_IWL<208> B_IWL<207> B_IWL<206> B_IWL<205> B_IWL<204> B_IWL<203> B_IWL<202> B_IWL<201> B_IWL<200> B_IWL<199> B_IWL<198> B_IWL<197> B_IWL<196> B_IWL<195> B_IWL<194> B_IWL<193> B_IWL<192> B_IWL<191> B_IWL<190> B_IWL<189> B_IWL<188> B_IWL<187> B_IWL<186> B_IWL<185> B_IWL<184> B_IWL<183> B_IWL<182> B_IWL<181> B_IWL<180> B_IWL<179> B_IWL<178> B_IWL<177> B_IWL<176> B_IWL<175> B_IWL<174> B_IWL<173> B_IWL<172> B_IWL<171> B_IWL<170> B_IWL<169> B_IWL<168> B_IWL<167> B_IWL<166> B_IWL<165> B_IWL<164> B_IWL<163> B_IWL<162> B_IWL<161> B_IWL<160> B_IWL<159> B_IWL<158> B_IWL<157> B_IWL<156> B_IWL<155> B_IWL<154> B_IWL<153> B_IWL<152> B_IWL<151> B_IWL<150> B_IWL<149> B_IWL<148> B_IWL<147> B_IWL<146> B_IWL<145> B_IWL<144> B_IWL<143> B_IWL<142> B_IWL<141> B_IWL<140> B_IWL<139> B_IWL<138> B_IWL<137> B_IWL<136> B_IWL<135> B_IWL<134> B_IWL<133> B_IWL<132> B_IWL<131> B_IWL<130> B_IWL<129> B_IWL<128> B_IWL<127> B_IWL<126> B_IWL<125> B_IWL<124> B_IWL<123> B_IWL<122> B_IWL<121> B_IWL<120> B_IWL<119> B_IWL<118> B_IWL<117> B_IWL<116> B_IWL<115> B_IWL<114> B_IWL<113> B_IWL<112> B_IWL<111> B_IWL<110> B_IWL<109> B_IWL<108> B_IWL<107> B_IWL<106> B_IWL<105> B_IWL<104> B_IWL<103> B_IWL<102> B_IWL<101> B_IWL<100> B_IWL<99> B_IWL<98> B_IWL<97> B_IWL<96> B_IWL<95> B_IWL<94> B_IWL<93> B_IWL<92> B_IWL<91> B_IWL<90> B_IWL<89> B_IWL<88> B_IWL<87> B_IWL<86> B_IWL<85> B_IWL<84> B_IWL<83> B_IWL<82> B_IWL<81> B_IWL<80> B_IWL<79> B_IWL<78> B_IWL<77> B_IWL<76> B_IWL<75> B_IWL<74> B_IWL<73> B_IWL<72> B_IWL<71> B_IWL<70> B_IWL<69> B_IWL<68> B_IWL<67> B_IWL<66> B_IWL<65> B_IWL<64> B_IWL<63> B_IWL<62> B_IWL<61> B_IWL<60> B_IWL<59> B_IWL<58> B_IWL<57> B_IWL<56> B_IWL<55> B_IWL<54> B_IWL<53> B_IWL<52> B_IWL<51> B_IWL<50> B_IWL<49> B_IWL<48> B_IWL<47> B_IWL<46> B_IWL<45> B_IWL<44> B_IWL<43> B_IWL<42> B_IWL<41> B_IWL<40> B_IWL<39> B_IWL<38> B_IWL<37> B_IWL<36> B_IWL<35> B_IWL<34> B_IWL<33> B_IWL<32> B_IWL<31> B_IWL<30> B_IWL<29> B_IWL<28> B_IWL<27> B_IWL<26> B_IWL<25> B_IWL<24> B_IWL<23> B_IWL<22> B_IWL<21> B_IWL<20> B_IWL<19> B_IWL<18> B_IWL<17> B_IWL<16> B_IWL<15> B_IWL<14> B_IWL<13> B_IWL<12> B_IWL<11> B_IWL<10> B_IWL<9> B_IWL<8> B_IWL<7> B_IWL<6> B_IWL<5> B_IWL<4> B_IWL<3> B_IWL<2> B_IWL<1> B_IWL<0> B_IWL<511> B_IWL<510> B_IWL<509> B_IWL<508> B_IWL<507> B_IWL<506> B_IWL<505> B_IWL<504> B_IWL<503> B_IWL<502> B_IWL<501> B_IWL<500> B_IWL<499> B_IWL<498> B_IWL<497> B_IWL<496> B_IWL<495> B_IWL<494> B_IWL<493> B_IWL<492> B_IWL<491> B_IWL<490> B_IWL<489> B_IWL<488> B_IWL<487> B_IWL<486> B_IWL<485> B_IWL<484> B_IWL<483> B_IWL<482> B_IWL<481> B_IWL<480> B_IWL<479> B_IWL<478> B_IWL<477> B_IWL<476> B_IWL<475> B_IWL<474> B_IWL<473> B_IWL<472> B_IWL<471> B_IWL<470> B_IWL<469> B_IWL<468> B_IWL<467> B_IWL<466> B_IWL<465> B_IWL<464> B_IWL<463> B_IWL<462> B_IWL<461> B_IWL<460> B_IWL<459> B_IWL<458> B_IWL<457> B_IWL<456> B_IWL<455> B_IWL<454> B_IWL<453> B_IWL<452> B_IWL<451> B_IWL<450> B_IWL<449> B_IWL<448> B_IWL<447> B_IWL<446> B_IWL<445> B_IWL<444> B_IWL<443> B_IWL<442> B_IWL<441> B_IWL<440> B_IWL<439> B_IWL<438> B_IWL<437> B_IWL<436> B_IWL<435> B_IWL<434> B_IWL<433> B_IWL<432> B_IWL<431> B_IWL<430> B_IWL<429> B_IWL<428> B_IWL<427> B_IWL<426> B_IWL<425> B_IWL<424> B_IWL<423> B_IWL<422> B_IWL<421> B_IWL<420> B_IWL<419> B_IWL<418> B_IWL<417> B_IWL<416> B_IWL<415> B_IWL<414> B_IWL<413> B_IWL<412> B_IWL<411> B_IWL<410> B_IWL<409> B_IWL<408> B_IWL<407> B_IWL<406> B_IWL<405> B_IWL<404> B_IWL<403> B_IWL<402> B_IWL<401> B_IWL<400> B_IWL<399> B_IWL<398> B_IWL<397> B_IWL<396> B_IWL<395> B_IWL<394> B_IWL<393> B_IWL<392> B_IWL<391> B_IWL<390> B_IWL<389> B_IWL<388> B_IWL<387> B_IWL<386> B_IWL<385> B_IWL<384> B_IWL<383> B_IWL<382> B_IWL<381> B_IWL<380> B_IWL<379> B_IWL<378> B_IWL<377> B_IWL<376> B_IWL<375> B_IWL<374> B_IWL<373> B_IWL<372> B_IWL<371> B_IWL<370> B_IWL<369> B_IWL<368> B_IWL<367> B_IWL<366> B_IWL<365> B_IWL<364> B_IWL<363> B_IWL<362> B_IWL<361> B_IWL<360> B_IWL<359> B_IWL<358> B_IWL<357> B_IWL<356> B_IWL<355> B_IWL<354> B_IWL<353> B_IWL<352> B_IWL<351> B_IWL<350> B_IWL<349> B_IWL<348> B_IWL<347> B_IWL<346> B_IWL<345> B_IWL<344> B_IWL<343> B_IWL<342> B_IWL<341> B_IWL<340> B_IWL<339> B_IWL<338> B_IWL<337> B_IWL<336> B_IWL<335> B_IWL<334> B_IWL<333> B_IWL<332> B_IWL<331> B_IWL<330> B_IWL<329> B_IWL<328> B_IWL<327> B_IWL<326> B_IWL<325> B_IWL<324> B_IWL<323> B_IWL<322> B_IWL<321> B_IWL<320> B_IWL<319> B_IWL<318> B_IWL<317> B_IWL<316> B_IWL<315> B_IWL<314> B_IWL<313> B_IWL<312> B_IWL<311> B_IWL<310> B_IWL<309> B_IWL<308> B_IWL<307> B_IWL<306> B_IWL<305> B_IWL<304> B_IWL<303> B_IWL<302> B_IWL<301> B_IWL<300> B_IWL<299> B_IWL<298> B_IWL<297> B_IWL<296> B_IWL<295> B_IWL<294> B_IWL<293> B_IWL<292> B_IWL<291> B_IWL<290> B_IWL<289> B_IWL<288> B_IWL<287> B_IWL<286> B_IWL<285> B_IWL<284> B_IWL<283> B_IWL<282> B_IWL<281> B_IWL<280> B_IWL<279> B_IWL<278> B_IWL<277> B_IWL<276> B_IWL<275> B_IWL<274> B_IWL<273> B_IWL<272> B_IWL<271> B_IWL<270> B_IWL<269> B_IWL<268> B_IWL<267> B_IWL<266> B_IWL<265> B_IWL<264> B_IWL<263> B_IWL<262> B_IWL<261> B_IWL<260> B_IWL<259> B_IWL<258> B_IWL<257> B_IWL<256> VDD_CORE VSS / RM_IHPSG13_1024x16_c2_2P_COLUMN_pcell_0 +XCOL<0> A_BLC<1> A_BLC<0> A_BLC_TOP<1> A_BLC_TOP<0> A_BLT<1> A_BLT<0> A_BLT_TOP<1> A_BLT_TOP<0> A_WL<255> A_WL<254> A_WL<253> A_WL<252> A_WL<251> A_WL<250> A_WL<249> A_WL<248> A_WL<247> A_WL<246> A_WL<245> A_WL<244> A_WL<243> A_WL<242> A_WL<241> A_WL<240> A_WL<239> A_WL<238> A_WL<237> A_WL<236> A_WL<235> A_WL<234> A_WL<233> A_WL<232> A_WL<231> A_WL<230> A_WL<229> A_WL<228> A_WL<227> A_WL<226> A_WL<225> A_WL<224> A_WL<223> A_WL<222> A_WL<221> A_WL<220> A_WL<219> A_WL<218> A_WL<217> A_WL<216> A_WL<215> A_WL<214> A_WL<213> A_WL<212> A_WL<211> A_WL<210> A_WL<209> A_WL<208> A_WL<207> A_WL<206> A_WL<205> A_WL<204> A_WL<203> A_WL<202> A_WL<201> A_WL<200> A_WL<199> A_WL<198> A_WL<197> A_WL<196> A_WL<195> A_WL<194> A_WL<193> A_WL<192> A_WL<191> A_WL<190> A_WL<189> A_WL<188> A_WL<187> A_WL<186> A_WL<185> A_WL<184> A_WL<183> A_WL<182> A_WL<181> A_WL<180> A_WL<179> A_WL<178> A_WL<177> A_WL<176> A_WL<175> A_WL<174> A_WL<173> A_WL<172> A_WL<171> A_WL<170> A_WL<169> A_WL<168> A_WL<167> A_WL<166> A_WL<165> A_WL<164> A_WL<163> A_WL<162> A_WL<161> A_WL<160> A_WL<159> A_WL<158> A_WL<157> A_WL<156> A_WL<155> A_WL<154> A_WL<153> A_WL<152> A_WL<151> A_WL<150> A_WL<149> A_WL<148> A_WL<147> A_WL<146> A_WL<145> A_WL<144> A_WL<143> A_WL<142> A_WL<141> A_WL<140> A_WL<139> A_WL<138> A_WL<137> A_WL<136> A_WL<135> A_WL<134> A_WL<133> A_WL<132> A_WL<131> A_WL<130> A_WL<129> A_WL<128> A_WL<127> A_WL<126> A_WL<125> A_WL<124> A_WL<123> A_WL<122> A_WL<121> A_WL<120> A_WL<119> A_WL<118> A_WL<117> A_WL<116> A_WL<115> A_WL<114> A_WL<113> A_WL<112> A_WL<111> A_WL<110> A_WL<109> A_WL<108> A_WL<107> A_WL<106> A_WL<105> A_WL<104> A_WL<103> A_WL<102> A_WL<101> A_WL<100> A_WL<99> A_WL<98> A_WL<97> A_WL<96> A_WL<95> A_WL<94> A_WL<93> A_WL<92> A_WL<91> A_WL<90> A_WL<89> A_WL<88> A_WL<87> A_WL<86> A_WL<85> A_WL<84> A_WL<83> A_WL<82> A_WL<81> A_WL<80> A_WL<79> A_WL<78> A_WL<77> A_WL<76> A_WL<75> A_WL<74> A_WL<73> A_WL<72> A_WL<71> A_WL<70> A_WL<69> A_WL<68> A_WL<67> A_WL<66> A_WL<65> A_WL<64> A_WL<63> A_WL<62> A_WL<61> A_WL<60> A_WL<59> A_WL<58> A_WL<57> A_WL<56> A_WL<55> A_WL<54> A_WL<53> A_WL<52> A_WL<51> A_WL<50> A_WL<49> A_WL<48> A_WL<47> A_WL<46> A_WL<45> A_WL<44> A_WL<43> A_WL<42> A_WL<41> A_WL<40> A_WL<39> A_WL<38> A_WL<37> A_WL<36> A_WL<35> A_WL<34> A_WL<33> A_WL<32> A_WL<31> A_WL<30> A_WL<29> A_WL<28> A_WL<27> A_WL<26> A_WL<25> A_WL<24> A_WL<23> A_WL<22> A_WL<21> A_WL<20> A_WL<19> A_WL<18> A_WL<17> A_WL<16> A_WL<15> A_WL<14> A_WL<13> A_WL<12> A_WL<11> A_WL<10> A_WL<9> A_WL<8> A_WL<7> A_WL<6> A_WL<5> A_WL<4> A_WL<3> A_WL<2> A_WL<1> A_WL<0> A_IWL<255> A_IWL<254> A_IWL<253> A_IWL<252> A_IWL<251> A_IWL<250> A_IWL<249> A_IWL<248> A_IWL<247> A_IWL<246> A_IWL<245> A_IWL<244> A_IWL<243> A_IWL<242> A_IWL<241> A_IWL<240> A_IWL<239> A_IWL<238> A_IWL<237> A_IWL<236> A_IWL<235> A_IWL<234> A_IWL<233> A_IWL<232> A_IWL<231> A_IWL<230> A_IWL<229> A_IWL<228> A_IWL<227> A_IWL<226> A_IWL<225> A_IWL<224> A_IWL<223> A_IWL<222> A_IWL<221> A_IWL<220> A_IWL<219> A_IWL<218> A_IWL<217> A_IWL<216> A_IWL<215> A_IWL<214> A_IWL<213> A_IWL<212> A_IWL<211> A_IWL<210> A_IWL<209> A_IWL<208> A_IWL<207> A_IWL<206> A_IWL<205> A_IWL<204> A_IWL<203> A_IWL<202> A_IWL<201> A_IWL<200> A_IWL<199> A_IWL<198> A_IWL<197> A_IWL<196> A_IWL<195> A_IWL<194> A_IWL<193> A_IWL<192> A_IWL<191> A_IWL<190> A_IWL<189> A_IWL<188> A_IWL<187> A_IWL<186> A_IWL<185> A_IWL<184> A_IWL<183> A_IWL<182> A_IWL<181> A_IWL<180> A_IWL<179> A_IWL<178> A_IWL<177> A_IWL<176> A_IWL<175> A_IWL<174> A_IWL<173> A_IWL<172> A_IWL<171> A_IWL<170> A_IWL<169> A_IWL<168> A_IWL<167> A_IWL<166> A_IWL<165> A_IWL<164> A_IWL<163> A_IWL<162> A_IWL<161> A_IWL<160> A_IWL<159> A_IWL<158> A_IWL<157> A_IWL<156> A_IWL<155> A_IWL<154> A_IWL<153> A_IWL<152> A_IWL<151> A_IWL<150> A_IWL<149> A_IWL<148> A_IWL<147> A_IWL<146> A_IWL<145> A_IWL<144> A_IWL<143> A_IWL<142> A_IWL<141> A_IWL<140> A_IWL<139> A_IWL<138> A_IWL<137> A_IWL<136> A_IWL<135> A_IWL<134> A_IWL<133> A_IWL<132> A_IWL<131> A_IWL<130> A_IWL<129> A_IWL<128> A_IWL<127> A_IWL<126> A_IWL<125> A_IWL<124> A_IWL<123> A_IWL<122> A_IWL<121> A_IWL<120> A_IWL<119> A_IWL<118> A_IWL<117> A_IWL<116> A_IWL<115> A_IWL<114> A_IWL<113> A_IWL<112> A_IWL<111> A_IWL<110> A_IWL<109> A_IWL<108> A_IWL<107> A_IWL<106> A_IWL<105> A_IWL<104> A_IWL<103> A_IWL<102> A_IWL<101> A_IWL<100> A_IWL<99> A_IWL<98> A_IWL<97> A_IWL<96> A_IWL<95> A_IWL<94> A_IWL<93> A_IWL<92> A_IWL<91> A_IWL<90> A_IWL<89> A_IWL<88> A_IWL<87> A_IWL<86> A_IWL<85> A_IWL<84> A_IWL<83> A_IWL<82> A_IWL<81> A_IWL<80> A_IWL<79> A_IWL<78> A_IWL<77> A_IWL<76> A_IWL<75> A_IWL<74> A_IWL<73> A_IWL<72> A_IWL<71> A_IWL<70> A_IWL<69> A_IWL<68> A_IWL<67> A_IWL<66> A_IWL<65> A_IWL<64> A_IWL<63> A_IWL<62> A_IWL<61> A_IWL<60> A_IWL<59> A_IWL<58> A_IWL<57> A_IWL<56> A_IWL<55> A_IWL<54> A_IWL<53> A_IWL<52> A_IWL<51> A_IWL<50> A_IWL<49> A_IWL<48> A_IWL<47> A_IWL<46> A_IWL<45> A_IWL<44> A_IWL<43> A_IWL<42> A_IWL<41> A_IWL<40> A_IWL<39> A_IWL<38> A_IWL<37> A_IWL<36> A_IWL<35> A_IWL<34> A_IWL<33> A_IWL<32> A_IWL<31> A_IWL<30> A_IWL<29> A_IWL<28> A_IWL<27> A_IWL<26> A_IWL<25> A_IWL<24> A_IWL<23> A_IWL<22> A_IWL<21> A_IWL<20> A_IWL<19> A_IWL<18> A_IWL<17> A_IWL<16> A_IWL<15> A_IWL<14> A_IWL<13> A_IWL<12> A_IWL<11> A_IWL<10> A_IWL<9> A_IWL<8> A_IWL<7> A_IWL<6> A_IWL<5> A_IWL<4> A_IWL<3> A_IWL<2> A_IWL<1> A_IWL<0> B_BLC<1> B_BLC<0> B_BLC_TOP<1> B_BLC_TOP<0> B_BLT<1> B_BLT<0> B_BLT_TOP<1> B_BLT_TOP<0> B_WL<255> B_WL<254> B_WL<253> B_WL<252> B_WL<251> B_WL<250> B_WL<249> B_WL<248> B_WL<247> B_WL<246> B_WL<245> B_WL<244> B_WL<243> B_WL<242> B_WL<241> B_WL<240> B_WL<239> B_WL<238> B_WL<237> B_WL<236> B_WL<235> B_WL<234> B_WL<233> B_WL<232> B_WL<231> B_WL<230> B_WL<229> B_WL<228> B_WL<227> B_WL<226> B_WL<225> B_WL<224> B_WL<223> B_WL<222> B_WL<221> B_WL<220> B_WL<219> B_WL<218> B_WL<217> B_WL<216> B_WL<215> B_WL<214> B_WL<213> B_WL<212> B_WL<211> B_WL<210> B_WL<209> B_WL<208> B_WL<207> B_WL<206> B_WL<205> B_WL<204> B_WL<203> B_WL<202> B_WL<201> B_WL<200> B_WL<199> B_WL<198> B_WL<197> B_WL<196> B_WL<195> B_WL<194> B_WL<193> B_WL<192> B_WL<191> B_WL<190> B_WL<189> B_WL<188> B_WL<187> B_WL<186> B_WL<185> B_WL<184> B_WL<183> B_WL<182> B_WL<181> B_WL<180> B_WL<179> B_WL<178> B_WL<177> B_WL<176> B_WL<175> B_WL<174> B_WL<173> B_WL<172> B_WL<171> B_WL<170> B_WL<169> B_WL<168> B_WL<167> B_WL<166> B_WL<165> B_WL<164> B_WL<163> B_WL<162> B_WL<161> B_WL<160> B_WL<159> B_WL<158> B_WL<157> B_WL<156> B_WL<155> B_WL<154> B_WL<153> B_WL<152> B_WL<151> B_WL<150> B_WL<149> B_WL<148> B_WL<147> B_WL<146> B_WL<145> B_WL<144> B_WL<143> B_WL<142> B_WL<141> B_WL<140> B_WL<139> B_WL<138> B_WL<137> B_WL<136> B_WL<135> B_WL<134> B_WL<133> B_WL<132> B_WL<131> B_WL<130> B_WL<129> B_WL<128> B_WL<127> B_WL<126> B_WL<125> B_WL<124> B_WL<123> B_WL<122> B_WL<121> B_WL<120> B_WL<119> B_WL<118> B_WL<117> B_WL<116> B_WL<115> B_WL<114> B_WL<113> B_WL<112> B_WL<111> B_WL<110> B_WL<109> B_WL<108> B_WL<107> B_WL<106> B_WL<105> B_WL<104> B_WL<103> B_WL<102> B_WL<101> B_WL<100> B_WL<99> B_WL<98> B_WL<97> B_WL<96> B_WL<95> B_WL<94> B_WL<93> B_WL<92> B_WL<91> B_WL<90> B_WL<89> B_WL<88> B_WL<87> B_WL<86> B_WL<85> B_WL<84> B_WL<83> B_WL<82> B_WL<81> B_WL<80> B_WL<79> B_WL<78> B_WL<77> B_WL<76> B_WL<75> B_WL<74> B_WL<73> B_WL<72> B_WL<71> B_WL<70> B_WL<69> B_WL<68> B_WL<67> B_WL<66> B_WL<65> B_WL<64> B_WL<63> B_WL<62> B_WL<61> B_WL<60> B_WL<59> B_WL<58> B_WL<57> B_WL<56> B_WL<55> B_WL<54> B_WL<53> B_WL<52> B_WL<51> B_WL<50> B_WL<49> B_WL<48> B_WL<47> B_WL<46> B_WL<45> B_WL<44> B_WL<43> B_WL<42> B_WL<41> B_WL<40> B_WL<39> B_WL<38> B_WL<37> B_WL<36> B_WL<35> B_WL<34> B_WL<33> B_WL<32> B_WL<31> B_WL<30> B_WL<29> B_WL<28> B_WL<27> B_WL<26> B_WL<25> B_WL<24> B_WL<23> B_WL<22> B_WL<21> B_WL<20> B_WL<19> B_WL<18> B_WL<17> B_WL<16> B_WL<15> B_WL<14> B_WL<13> B_WL<12> B_WL<11> B_WL<10> B_WL<9> B_WL<8> B_WL<7> B_WL<6> B_WL<5> B_WL<4> B_WL<3> B_WL<2> B_WL<1> B_WL<0> B_IWL<255> B_IWL<254> B_IWL<253> B_IWL<252> B_IWL<251> B_IWL<250> B_IWL<249> B_IWL<248> B_IWL<247> B_IWL<246> B_IWL<245> B_IWL<244> B_IWL<243> B_IWL<242> B_IWL<241> B_IWL<240> B_IWL<239> B_IWL<238> B_IWL<237> B_IWL<236> B_IWL<235> B_IWL<234> B_IWL<233> B_IWL<232> B_IWL<231> B_IWL<230> B_IWL<229> B_IWL<228> B_IWL<227> B_IWL<226> B_IWL<225> B_IWL<224> B_IWL<223> B_IWL<222> B_IWL<221> B_IWL<220> B_IWL<219> B_IWL<218> B_IWL<217> B_IWL<216> B_IWL<215> B_IWL<214> B_IWL<213> B_IWL<212> B_IWL<211> B_IWL<210> B_IWL<209> B_IWL<208> B_IWL<207> B_IWL<206> B_IWL<205> B_IWL<204> B_IWL<203> B_IWL<202> B_IWL<201> B_IWL<200> B_IWL<199> B_IWL<198> B_IWL<197> B_IWL<196> B_IWL<195> B_IWL<194> B_IWL<193> B_IWL<192> B_IWL<191> B_IWL<190> B_IWL<189> B_IWL<188> B_IWL<187> B_IWL<186> B_IWL<185> B_IWL<184> B_IWL<183> B_IWL<182> B_IWL<181> B_IWL<180> B_IWL<179> B_IWL<178> B_IWL<177> B_IWL<176> B_IWL<175> B_IWL<174> B_IWL<173> B_IWL<172> B_IWL<171> B_IWL<170> B_IWL<169> B_IWL<168> B_IWL<167> B_IWL<166> B_IWL<165> B_IWL<164> B_IWL<163> B_IWL<162> B_IWL<161> B_IWL<160> B_IWL<159> B_IWL<158> B_IWL<157> B_IWL<156> B_IWL<155> B_IWL<154> B_IWL<153> B_IWL<152> B_IWL<151> B_IWL<150> B_IWL<149> B_IWL<148> B_IWL<147> B_IWL<146> B_IWL<145> B_IWL<144> B_IWL<143> B_IWL<142> B_IWL<141> B_IWL<140> B_IWL<139> B_IWL<138> B_IWL<137> B_IWL<136> B_IWL<135> B_IWL<134> B_IWL<133> B_IWL<132> B_IWL<131> B_IWL<130> B_IWL<129> B_IWL<128> B_IWL<127> B_IWL<126> B_IWL<125> B_IWL<124> B_IWL<123> B_IWL<122> B_IWL<121> B_IWL<120> B_IWL<119> B_IWL<118> B_IWL<117> B_IWL<116> B_IWL<115> B_IWL<114> B_IWL<113> B_IWL<112> B_IWL<111> B_IWL<110> B_IWL<109> B_IWL<108> B_IWL<107> B_IWL<106> B_IWL<105> B_IWL<104> B_IWL<103> B_IWL<102> B_IWL<101> B_IWL<100> B_IWL<99> B_IWL<98> B_IWL<97> B_IWL<96> B_IWL<95> B_IWL<94> B_IWL<93> B_IWL<92> B_IWL<91> B_IWL<90> B_IWL<89> B_IWL<88> B_IWL<87> B_IWL<86> B_IWL<85> B_IWL<84> B_IWL<83> B_IWL<82> B_IWL<81> B_IWL<80> B_IWL<79> B_IWL<78> B_IWL<77> B_IWL<76> B_IWL<75> B_IWL<74> B_IWL<73> B_IWL<72> B_IWL<71> B_IWL<70> B_IWL<69> B_IWL<68> B_IWL<67> B_IWL<66> B_IWL<65> B_IWL<64> B_IWL<63> B_IWL<62> B_IWL<61> B_IWL<60> B_IWL<59> B_IWL<58> B_IWL<57> B_IWL<56> B_IWL<55> B_IWL<54> B_IWL<53> B_IWL<52> B_IWL<51> B_IWL<50> B_IWL<49> B_IWL<48> B_IWL<47> B_IWL<46> B_IWL<45> B_IWL<44> B_IWL<43> B_IWL<42> B_IWL<41> B_IWL<40> B_IWL<39> B_IWL<38> B_IWL<37> B_IWL<36> B_IWL<35> B_IWL<34> B_IWL<33> B_IWL<32> B_IWL<31> B_IWL<30> B_IWL<29> B_IWL<28> B_IWL<27> B_IWL<26> B_IWL<25> B_IWL<24> B_IWL<23> B_IWL<22> B_IWL<21> B_IWL<20> B_IWL<19> B_IWL<18> B_IWL<17> B_IWL<16> B_IWL<15> B_IWL<14> B_IWL<13> B_IWL<12> B_IWL<11> B_IWL<10> B_IWL<9> B_IWL<8> B_IWL<7> B_IWL<6> B_IWL<5> B_IWL<4> B_IWL<3> B_IWL<2> B_IWL<1> B_IWL<0> VDD_CORE VSS / RM_IHPSG13_1024x16_c2_2P_COLUMN_pcell_0 +.ENDS + + + + +.SUBCKT RM_IHPSG13_1024x16_c2_2P_DLY_pcell_2 A Z VDD VSS + XIDL<2> D<9> Z VDD VSS / RSC_IHPSG13_CDLYX1 + XIDL<1> D<8> D<9> VDD VSS / RSC_IHPSG13_CDLYX1 + XIDM<8> D<7> D<8> VDD VSS / RSC_IHPSG13_CDLYX1_DUMMY + XIDM<7> D<6> D<7> VDD VSS / RSC_IHPSG13_CDLYX1_DUMMY + XIDM<6> D<5> D<6> VDD VSS / RSC_IHPSG13_CDLYX1_DUMMY + XIDM<5> D<4> D<5> VDD VSS / RSC_IHPSG13_CDLYX1_DUMMY + XIDM<4> D<3> D<4> VDD VSS / RSC_IHPSG13_CDLYX1_DUMMY + XIDM<3> D<2> D<3> VDD VSS / RSC_IHPSG13_CDLYX1_DUMMY + XIDM<2> D<1> D<2> VDD VSS / RSC_IHPSG13_CDLYX1_DUMMY + XIDM<1> A D<1> VDD VSS / RSC_IHPSG13_CDLYX1_DUMMY +.ENDS + + +.SUBCKT RM_IHPSG13_1024x16_c2_2P_DLY_pcell_3 A Z VDD VSS + XIDL<4> D<9> Z VDD VSS / RSC_IHPSG13_CDLYX1 + XIDL<3> D<8> D<9> VDD VSS / RSC_IHPSG13_CDLYX1 + XIDL<2> D<7> D<8> VDD VSS / RSC_IHPSG13_CDLYX1 + XIDL<1> D<6> D<7> VDD VSS / RSC_IHPSG13_CDLYX1 + XIDM<6> D<5> D<6> VDD VSS / RSC_IHPSG13_CDLYX1_DUMMY + XIDM<5> D<4> D<5> VDD VSS / RSC_IHPSG13_CDLYX1_DUMMY + XIDM<4> D<3> D<4> VDD VSS / RSC_IHPSG13_CDLYX1_DUMMY + XIDM<3> D<2> D<3> VDD VSS / RSC_IHPSG13_CDLYX1_DUMMY + XIDM<2> D<1> D<2> VDD VSS / RSC_IHPSG13_CDLYX1_DUMMY + XIDM<1> A D<1> VDD VSS / RSC_IHPSG13_CDLYX1_DUMMY +.ENDS + + + +.SUBCKT RM_IHPSG13_2P_1024x16_c2_bm_bist A_ADDR<9> A_ADDR<8> A_ADDR<7> A_ADDR<6> A_ADDR<5> A_ADDR<4> A_ADDR<3> A_ADDR<2> A_ADDR<1> A_ADDR<0> A_BIST_ADDR<9> A_BIST_ADDR<8> A_BIST_ADDR<7> A_BIST_ADDR<6> A_BIST_ADDR<5> A_BIST_ADDR<4> A_BIST_ADDR<3> A_BIST_ADDR<2> A_BIST_ADDR<1> A_BIST_ADDR<0> A_BIST_BM<15> A_BIST_BM<14> A_BIST_BM<13> A_BIST_BM<12> A_BIST_BM<11> A_BIST_BM<10> A_BIST_BM<9> A_BIST_BM<8> A_BIST_BM<7> A_BIST_BM<6> A_BIST_BM<5> A_BIST_BM<4> A_BIST_BM<3> A_BIST_BM<2> A_BIST_BM<1> A_BIST_BM<0> A_BIST_CLK A_BIST_DIN<15> A_BIST_DIN<14> A_BIST_DIN<13> A_BIST_DIN<12> A_BIST_DIN<11> A_BIST_DIN<10> A_BIST_DIN<9> A_BIST_DIN<8> A_BIST_DIN<7> A_BIST_DIN<6> A_BIST_DIN<5> A_BIST_DIN<4> A_BIST_DIN<3> A_BIST_DIN<2> A_BIST_DIN<1> A_BIST_DIN<0> A_BIST_EN A_BIST_MEN A_BIST_REN A_BIST_WEN A_BM<15> A_BM<14> A_BM<13> A_BM<12> A_BM<11> A_BM<10> A_BM<9> A_BM<8> A_BM<7> A_BM<6> A_BM<5> A_BM<4> A_BM<3> A_BM<2> A_BM<1> A_BM<0> A_CLK A_DIN<15> A_DIN<14> A_DIN<13> A_DIN<12> A_DIN<11> A_DIN<10> A_DIN<9> A_DIN<8> A_DIN<7> A_DIN<6> A_DIN<5> A_DIN<4> A_DIN<3> A_DIN<2> A_DIN<1> A_DIN<0> A_DLY A_DOUT<15> A_DOUT<14> A_DOUT<13> A_DOUT<12> A_DOUT<11> A_DOUT<10> A_DOUT<9> A_DOUT<8> A_DOUT<7> A_DOUT<6> A_DOUT<5> A_DOUT<4> A_DOUT<3> A_DOUT<2> A_DOUT<1> A_DOUT<0> A_MEN A_REN A_WEN B_ADDR<9> B_ADDR<8> B_ADDR<7> B_ADDR<6> B_ADDR<5> B_ADDR<4> B_ADDR<3> B_ADDR<2> B_ADDR<1> B_ADDR<0> B_BIST_ADDR<9> B_BIST_ADDR<8> B_BIST_ADDR<7> B_BIST_ADDR<6> B_BIST_ADDR<5> B_BIST_ADDR<4> B_BIST_ADDR<3> B_BIST_ADDR<2> B_BIST_ADDR<1> B_BIST_ADDR<0> B_BIST_BM<15> B_BIST_BM<14> B_BIST_BM<13> B_BIST_BM<12> B_BIST_BM<11> B_BIST_BM<10> B_BIST_BM<9> B_BIST_BM<8> B_BIST_BM<7> B_BIST_BM<6> B_BIST_BM<5> B_BIST_BM<4> B_BIST_BM<3> B_BIST_BM<2> B_BIST_BM<1> B_BIST_BM<0> B_BIST_CLK B_BIST_DIN<15> B_BIST_DIN<14> B_BIST_DIN<13> B_BIST_DIN<12> B_BIST_DIN<11> B_BIST_DIN<10> B_BIST_DIN<9> B_BIST_DIN<8> B_BIST_DIN<7> B_BIST_DIN<6> B_BIST_DIN<5> B_BIST_DIN<4> B_BIST_DIN<3> B_BIST_DIN<2> B_BIST_DIN<1> B_BIST_DIN<0> B_BIST_EN B_BIST_MEN B_BIST_REN B_BIST_WEN B_BM<15> B_BM<14> B_BM<13> B_BM<12> B_BM<11> B_BM<10> B_BM<9> B_BM<8> B_BM<7> B_BM<6> B_BM<5> B_BM<4> B_BM<3> B_BM<2> B_BM<1> B_BM<0> B_CLK B_DIN<15> B_DIN<14> B_DIN<13> B_DIN<12> B_DIN<11> B_DIN<10> B_DIN<9> B_DIN<8> B_DIN<7> B_DIN<6> B_DIN<5> B_DIN<4> B_DIN<3> B_DIN<2> B_DIN<1> B_DIN<0> B_DLY B_DOUT<15> B_DOUT<14> B_DOUT<13> B_DOUT<12> B_DOUT<11> B_DOUT<10> B_DOUT<9> B_DOUT<8> B_DOUT<7> B_DOUT<6> B_DOUT<5> B_DOUT<4> B_DOUT<3> B_DOUT<2> B_DOUT<1> B_DOUT<0> B_MEN B_REN B_WEN VDD! VDDARRAY! VSS! + + +XRAM<1> a_blc_r<31> a_blc_r<30> a_blc_r<29> a_blc_r<28> a_blc_r<27> a_blc_r<26> a_blc_r<25> a_blc_r<24> a_blc_r<23> a_blc_r<22> a_blc_r<21> a_blc_r<20> a_blc_r<19> a_blc_r<18> a_blc_r<17> a_blc_r<16> a_blc_r<15> a_blc_r<14> a_blc_r<13> a_blc_r<12> a_blc_r<11> a_blc_r<10> a_blc_r<9> a_blc_r<8> a_blc_r<7> a_blc_r<6> a_blc_r<5> a_blc_r<4> a_blc_r<3> a_blc_r<2> a_blc_r<1> a_blc_r<0> a_blt_r<31> a_blt_r<30> a_blt_r<29> a_blt_r<28> a_blt_r<27> a_blt_r<26> a_blt_r<25> a_blt_r<24> a_blt_r<23> a_blt_r<22> a_blt_r<21> a_blt_r<20> a_blt_r<19> a_blt_r<18> a_blt_r<17> a_blt_r<16> a_blt_r<15> a_blt_r<14> a_blt_r<13> a_blt_r<12> a_blt_r<11> a_blt_r<10> a_blt_r<9> a_blt_r<8> a_blt_r<7> a_blt_r<6> a_blt_r<5> a_blt_r<4> a_blt_r<3> a_blt_r<2> a_blt_r<1> a_blt_r<0> a_wl_r<255> a_wl_r<254> a_wl_r<253> a_wl_r<252> a_wl_r<251> a_wl_r<250> a_wl_r<249> a_wl_r<248> a_wl_r<247> a_wl_r<246> a_wl_r<245> a_wl_r<244> a_wl_r<243> a_wl_r<242> a_wl_r<241> a_wl_r<240> a_wl_r<239> a_wl_r<238> a_wl_r<237> a_wl_r<236> a_wl_r<235> a_wl_r<234> a_wl_r<233> a_wl_r<232> a_wl_r<231> a_wl_r<230> a_wl_r<229> a_wl_r<228> a_wl_r<227> a_wl_r<226> a_wl_r<225> a_wl_r<224> a_wl_r<223> a_wl_r<222> a_wl_r<221> a_wl_r<220> a_wl_r<219> a_wl_r<218> a_wl_r<217> a_wl_r<216> a_wl_r<215> a_wl_r<214> a_wl_r<213> a_wl_r<212> a_wl_r<211> a_wl_r<210> a_wl_r<209> a_wl_r<208> a_wl_r<207> a_wl_r<206> a_wl_r<205> a_wl_r<204> a_wl_r<203> a_wl_r<202> a_wl_r<201> a_wl_r<200> a_wl_r<199> a_wl_r<198> a_wl_r<197> a_wl_r<196> a_wl_r<195> a_wl_r<194> a_wl_r<193> a_wl_r<192> a_wl_r<191> a_wl_r<190> a_wl_r<189> a_wl_r<188> a_wl_r<187> a_wl_r<186> a_wl_r<185> a_wl_r<184> a_wl_r<183> a_wl_r<182> a_wl_r<181> a_wl_r<180> a_wl_r<179> a_wl_r<178> a_wl_r<177> a_wl_r<176> a_wl_r<175> a_wl_r<174> a_wl_r<173> a_wl_r<172> a_wl_r<171> a_wl_r<170> a_wl_r<169> a_wl_r<168> a_wl_r<167> a_wl_r<166> a_wl_r<165> a_wl_r<164> a_wl_r<163> a_wl_r<162> a_wl_r<161> a_wl_r<160> a_wl_r<159> a_wl_r<158> a_wl_r<157> a_wl_r<156> a_wl_r<155> a_wl_r<154> a_wl_r<153> a_wl_r<152> a_wl_r<151> a_wl_r<150> a_wl_r<149> a_wl_r<148> a_wl_r<147> a_wl_r<146> a_wl_r<145> a_wl_r<144> a_wl_r<143> a_wl_r<142> a_wl_r<141> a_wl_r<140> a_wl_r<139> a_wl_r<138> a_wl_r<137> a_wl_r<136> a_wl_r<135> a_wl_r<134> a_wl_r<133> a_wl_r<132> a_wl_r<131> a_wl_r<130> a_wl_r<129> a_wl_r<128> a_wl_r<127> a_wl_r<126> a_wl_r<125> a_wl_r<124> a_wl_r<123> a_wl_r<122> a_wl_r<121> a_wl_r<120> a_wl_r<119> a_wl_r<118> a_wl_r<117> a_wl_r<116> a_wl_r<115> a_wl_r<114> a_wl_r<113> a_wl_r<112> a_wl_r<111> a_wl_r<110> a_wl_r<109> a_wl_r<108> a_wl_r<107> a_wl_r<106> a_wl_r<105> a_wl_r<104> a_wl_r<103> a_wl_r<102> a_wl_r<101> a_wl_r<100> a_wl_r<99> a_wl_r<98> a_wl_r<97> a_wl_r<96> a_wl_r<95> a_wl_r<94> a_wl_r<93> a_wl_r<92> a_wl_r<91> a_wl_r<90> a_wl_r<89> a_wl_r<88> a_wl_r<87> a_wl_r<86> a_wl_r<85> a_wl_r<84> a_wl_r<83> a_wl_r<82> a_wl_r<81> a_wl_r<80> a_wl_r<79> a_wl_r<78> a_wl_r<77> a_wl_r<76> a_wl_r<75> a_wl_r<74> a_wl_r<73> a_wl_r<72> a_wl_r<71> a_wl_r<70> a_wl_r<69> a_wl_r<68> a_wl_r<67> a_wl_r<66> a_wl_r<65> a_wl_r<64> a_wl_r<63> a_wl_r<62> a_wl_r<61> a_wl_r<60> a_wl_r<59> a_wl_r<58> a_wl_r<57> a_wl_r<56> a_wl_r<55> a_wl_r<54> a_wl_r<53> a_wl_r<52> a_wl_r<51> a_wl_r<50> a_wl_r<49> a_wl_r<48> a_wl_r<47> a_wl_r<46> a_wl_r<45> a_wl_r<44> a_wl_r<43> a_wl_r<42> a_wl_r<41> a_wl_r<40> a_wl_r<39> a_wl_r<38> a_wl_r<37> a_wl_r<36> a_wl_r<35> a_wl_r<34> a_wl_r<33> a_wl_r<32> a_wl_r<31> a_wl_r<30> a_wl_r<29> a_wl_r<28> a_wl_r<27> a_wl_r<26> a_wl_r<25> a_wl_r<24> a_wl_r<23> a_wl_r<22> a_wl_r<21> a_wl_r<20> a_wl_r<19> a_wl_r<18> a_wl_r<17> a_wl_r<16> a_wl_r<15> a_wl_r<14> a_wl_r<13> a_wl_r<12> a_wl_r<11> a_wl_r<10> a_wl_r<9> a_wl_r<8> a_wl_r<7> a_wl_r<6> a_wl_r<5> a_wl_r<4> a_wl_r<3> a_wl_r<2> a_wl_r<1> a_wl_r<0> b_blc_r<31> b_blc_r<30> b_blc_r<29> b_blc_r<28> b_blc_r<27> b_blc_r<26> b_blc_r<25> b_blc_r<24> b_blc_r<23> b_blc_r<22> b_blc_r<21> b_blc_r<20> b_blc_r<19> b_blc_r<18> b_blc_r<17> b_blc_r<16> b_blc_r<15> b_blc_r<14> b_blc_r<13> b_blc_r<12> b_blc_r<11> b_blc_r<10> b_blc_r<9> b_blc_r<8> b_blc_r<7> b_blc_r<6> b_blc_r<5> b_blc_r<4> b_blc_r<3> b_blc_r<2> b_blc_r<1> b_blc_r<0> b_blt_r<31> b_blt_r<30> b_blt_r<29> b_blt_r<28> b_blt_r<27> b_blt_r<26> b_blt_r<25> b_blt_r<24> b_blt_r<23> b_blt_r<22> b_blt_r<21> b_blt_r<20> b_blt_r<19> b_blt_r<18> b_blt_r<17> b_blt_r<16> b_blt_r<15> b_blt_r<14> b_blt_r<13> b_blt_r<12> b_blt_r<11> b_blt_r<10> b_blt_r<9> b_blt_r<8> b_blt_r<7> b_blt_r<6> b_blt_r<5> b_blt_r<4> b_blt_r<3> b_blt_r<2> b_blt_r<1> b_blt_r<0> b_wl_r<255> b_wl_r<254> b_wl_r<253> b_wl_r<252> b_wl_r<251> b_wl_r<250> b_wl_r<249> b_wl_r<248> b_wl_r<247> b_wl_r<246> b_wl_r<245> b_wl_r<244> b_wl_r<243> b_wl_r<242> b_wl_r<241> b_wl_r<240> b_wl_r<239> b_wl_r<238> b_wl_r<237> b_wl_r<236> b_wl_r<235> b_wl_r<234> b_wl_r<233> b_wl_r<232> b_wl_r<231> b_wl_r<230> b_wl_r<229> b_wl_r<228> b_wl_r<227> b_wl_r<226> b_wl_r<225> b_wl_r<224> b_wl_r<223> b_wl_r<222> b_wl_r<221> b_wl_r<220> b_wl_r<219> b_wl_r<218> b_wl_r<217> b_wl_r<216> b_wl_r<215> b_wl_r<214> b_wl_r<213> b_wl_r<212> b_wl_r<211> b_wl_r<210> b_wl_r<209> b_wl_r<208> b_wl_r<207> b_wl_r<206> b_wl_r<205> b_wl_r<204> b_wl_r<203> b_wl_r<202> b_wl_r<201> b_wl_r<200> b_wl_r<199> b_wl_r<198> b_wl_r<197> b_wl_r<196> b_wl_r<195> b_wl_r<194> b_wl_r<193> b_wl_r<192> b_wl_r<191> b_wl_r<190> b_wl_r<189> b_wl_r<188> b_wl_r<187> b_wl_r<186> b_wl_r<185> b_wl_r<184> b_wl_r<183> b_wl_r<182> b_wl_r<181> b_wl_r<180> b_wl_r<179> b_wl_r<178> b_wl_r<177> b_wl_r<176> b_wl_r<175> b_wl_r<174> b_wl_r<173> b_wl_r<172> b_wl_r<171> b_wl_r<170> b_wl_r<169> b_wl_r<168> b_wl_r<167> b_wl_r<166> b_wl_r<165> b_wl_r<164> b_wl_r<163> b_wl_r<162> b_wl_r<161> b_wl_r<160> b_wl_r<159> b_wl_r<158> b_wl_r<157> b_wl_r<156> b_wl_r<155> b_wl_r<154> b_wl_r<153> b_wl_r<152> b_wl_r<151> b_wl_r<150> b_wl_r<149> b_wl_r<148> b_wl_r<147> b_wl_r<146> b_wl_r<145> b_wl_r<144> b_wl_r<143> b_wl_r<142> b_wl_r<141> b_wl_r<140> b_wl_r<139> b_wl_r<138> b_wl_r<137> b_wl_r<136> b_wl_r<135> b_wl_r<134> b_wl_r<133> b_wl_r<132> b_wl_r<131> b_wl_r<130> b_wl_r<129> b_wl_r<128> b_wl_r<127> b_wl_r<126> b_wl_r<125> b_wl_r<124> b_wl_r<123> b_wl_r<122> b_wl_r<121> b_wl_r<120> b_wl_r<119> b_wl_r<118> b_wl_r<117> b_wl_r<116> b_wl_r<115> b_wl_r<114> b_wl_r<113> b_wl_r<112> b_wl_r<111> b_wl_r<110> b_wl_r<109> b_wl_r<108> b_wl_r<107> b_wl_r<106> b_wl_r<105> b_wl_r<104> b_wl_r<103> b_wl_r<102> b_wl_r<101> b_wl_r<100> b_wl_r<99> b_wl_r<98> b_wl_r<97> b_wl_r<96> b_wl_r<95> b_wl_r<94> b_wl_r<93> b_wl_r<92> b_wl_r<91> b_wl_r<90> b_wl_r<89> b_wl_r<88> b_wl_r<87> b_wl_r<86> b_wl_r<85> b_wl_r<84> b_wl_r<83> b_wl_r<82> b_wl_r<81> b_wl_r<80> b_wl_r<79> b_wl_r<78> b_wl_r<77> b_wl_r<76> b_wl_r<75> b_wl_r<74> b_wl_r<73> b_wl_r<72> b_wl_r<71> b_wl_r<70> b_wl_r<69> b_wl_r<68> b_wl_r<67> b_wl_r<66> b_wl_r<65> b_wl_r<64> b_wl_r<63> b_wl_r<62> b_wl_r<61> b_wl_r<60> b_wl_r<59> b_wl_r<58> b_wl_r<57> b_wl_r<56> b_wl_r<55> b_wl_r<54> b_wl_r<53> b_wl_r<52> b_wl_r<51> b_wl_r<50> b_wl_r<49> b_wl_r<48> b_wl_r<47> b_wl_r<46> b_wl_r<45> b_wl_r<44> b_wl_r<43> b_wl_r<42> b_wl_r<41> b_wl_r<40> b_wl_r<39> b_wl_r<38> b_wl_r<37> b_wl_r<36> b_wl_r<35> b_wl_r<34> b_wl_r<33> b_wl_r<32> b_wl_r<31> b_wl_r<30> b_wl_r<29> b_wl_r<28> b_wl_r<27> b_wl_r<26> b_wl_r<25> b_wl_r<24> b_wl_r<23> b_wl_r<22> b_wl_r<21> b_wl_r<20> b_wl_r<19> b_wl_r<18> b_wl_r<17> b_wl_r<16> b_wl_r<15> b_wl_r<14> b_wl_r<13> b_wl_r<12> b_wl_r<11> b_wl_r<10> b_wl_r<9> b_wl_r<8> b_wl_r<7> b_wl_r<6> b_wl_r<5> b_wl_r<4> b_wl_r<3> b_wl_r<2> b_wl_r<1> b_wl_r<0> VDDARRAY! VSS! / RM_IHPSG13_1024x16_c2_2P_MATRIX_pcell_1 +XRAM<0> a_blc_l<31> a_blc_l<30> a_blc_l<29> a_blc_l<28> a_blc_l<27> a_blc_l<26> a_blc_l<25> a_blc_l<24> a_blc_l<23> a_blc_l<22> a_blc_l<21> a_blc_l<20> a_blc_l<19> a_blc_l<18> a_blc_l<17> a_blc_l<16> a_blc_l<15> a_blc_l<14> a_blc_l<13> a_blc_l<12> a_blc_l<11> a_blc_l<10> a_blc_l<9> a_blc_l<8> a_blc_l<7> a_blc_l<6> a_blc_l<5> a_blc_l<4> a_blc_l<3> a_blc_l<2> a_blc_l<1> a_blc_l<0> a_blt_l<31> a_blt_l<30> a_blt_l<29> a_blt_l<28> a_blt_l<27> a_blt_l<26> a_blt_l<25> a_blt_l<24> a_blt_l<23> a_blt_l<22> a_blt_l<21> a_blt_l<20> a_blt_l<19> a_blt_l<18> a_blt_l<17> a_blt_l<16> a_blt_l<15> a_blt_l<14> a_blt_l<13> a_blt_l<12> a_blt_l<11> a_blt_l<10> a_blt_l<9> a_blt_l<8> a_blt_l<7> a_blt_l<6> a_blt_l<5> a_blt_l<4> a_blt_l<3> a_blt_l<2> a_blt_l<1> a_blt_l<0> a_wl_l<255> a_wl_l<254> a_wl_l<253> a_wl_l<252> a_wl_l<251> a_wl_l<250> a_wl_l<249> a_wl_l<248> a_wl_l<247> a_wl_l<246> a_wl_l<245> a_wl_l<244> a_wl_l<243> a_wl_l<242> a_wl_l<241> a_wl_l<240> a_wl_l<239> a_wl_l<238> a_wl_l<237> a_wl_l<236> a_wl_l<235> a_wl_l<234> a_wl_l<233> a_wl_l<232> a_wl_l<231> a_wl_l<230> a_wl_l<229> a_wl_l<228> a_wl_l<227> a_wl_l<226> a_wl_l<225> a_wl_l<224> a_wl_l<223> a_wl_l<222> a_wl_l<221> a_wl_l<220> a_wl_l<219> a_wl_l<218> a_wl_l<217> a_wl_l<216> a_wl_l<215> a_wl_l<214> a_wl_l<213> a_wl_l<212> a_wl_l<211> a_wl_l<210> a_wl_l<209> a_wl_l<208> a_wl_l<207> a_wl_l<206> a_wl_l<205> a_wl_l<204> a_wl_l<203> a_wl_l<202> a_wl_l<201> a_wl_l<200> a_wl_l<199> a_wl_l<198> a_wl_l<197> a_wl_l<196> a_wl_l<195> a_wl_l<194> a_wl_l<193> a_wl_l<192> a_wl_l<191> a_wl_l<190> a_wl_l<189> a_wl_l<188> a_wl_l<187> a_wl_l<186> a_wl_l<185> a_wl_l<184> a_wl_l<183> a_wl_l<182> a_wl_l<181> a_wl_l<180> a_wl_l<179> a_wl_l<178> a_wl_l<177> a_wl_l<176> a_wl_l<175> a_wl_l<174> a_wl_l<173> a_wl_l<172> a_wl_l<171> a_wl_l<170> a_wl_l<169> a_wl_l<168> a_wl_l<167> a_wl_l<166> a_wl_l<165> a_wl_l<164> a_wl_l<163> a_wl_l<162> a_wl_l<161> a_wl_l<160> a_wl_l<159> a_wl_l<158> a_wl_l<157> a_wl_l<156> a_wl_l<155> a_wl_l<154> a_wl_l<153> a_wl_l<152> a_wl_l<151> a_wl_l<150> a_wl_l<149> a_wl_l<148> a_wl_l<147> a_wl_l<146> a_wl_l<145> a_wl_l<144> a_wl_l<143> a_wl_l<142> a_wl_l<141> a_wl_l<140> a_wl_l<139> a_wl_l<138> a_wl_l<137> a_wl_l<136> a_wl_l<135> a_wl_l<134> a_wl_l<133> a_wl_l<132> a_wl_l<131> a_wl_l<130> a_wl_l<129> a_wl_l<128> a_wl_l<127> a_wl_l<126> a_wl_l<125> a_wl_l<124> a_wl_l<123> a_wl_l<122> a_wl_l<121> a_wl_l<120> a_wl_l<119> a_wl_l<118> a_wl_l<117> a_wl_l<116> a_wl_l<115> a_wl_l<114> a_wl_l<113> a_wl_l<112> a_wl_l<111> a_wl_l<110> a_wl_l<109> a_wl_l<108> a_wl_l<107> a_wl_l<106> a_wl_l<105> a_wl_l<104> a_wl_l<103> a_wl_l<102> a_wl_l<101> a_wl_l<100> a_wl_l<99> a_wl_l<98> a_wl_l<97> a_wl_l<96> a_wl_l<95> a_wl_l<94> a_wl_l<93> a_wl_l<92> a_wl_l<91> a_wl_l<90> a_wl_l<89> a_wl_l<88> a_wl_l<87> a_wl_l<86> a_wl_l<85> a_wl_l<84> a_wl_l<83> a_wl_l<82> a_wl_l<81> a_wl_l<80> a_wl_l<79> a_wl_l<78> a_wl_l<77> a_wl_l<76> a_wl_l<75> a_wl_l<74> a_wl_l<73> a_wl_l<72> a_wl_l<71> a_wl_l<70> a_wl_l<69> a_wl_l<68> a_wl_l<67> a_wl_l<66> a_wl_l<65> a_wl_l<64> a_wl_l<63> a_wl_l<62> a_wl_l<61> a_wl_l<60> a_wl_l<59> a_wl_l<58> a_wl_l<57> a_wl_l<56> a_wl_l<55> a_wl_l<54> a_wl_l<53> a_wl_l<52> a_wl_l<51> a_wl_l<50> a_wl_l<49> a_wl_l<48> a_wl_l<47> a_wl_l<46> a_wl_l<45> a_wl_l<44> a_wl_l<43> a_wl_l<42> a_wl_l<41> a_wl_l<40> a_wl_l<39> a_wl_l<38> a_wl_l<37> a_wl_l<36> a_wl_l<35> a_wl_l<34> a_wl_l<33> a_wl_l<32> a_wl_l<31> a_wl_l<30> a_wl_l<29> a_wl_l<28> a_wl_l<27> a_wl_l<26> a_wl_l<25> a_wl_l<24> a_wl_l<23> a_wl_l<22> a_wl_l<21> a_wl_l<20> a_wl_l<19> a_wl_l<18> a_wl_l<17> a_wl_l<16> a_wl_l<15> a_wl_l<14> a_wl_l<13> a_wl_l<12> a_wl_l<11> a_wl_l<10> a_wl_l<9> a_wl_l<8> a_wl_l<7> a_wl_l<6> a_wl_l<5> a_wl_l<4> a_wl_l<3> a_wl_l<2> a_wl_l<1> a_wl_l<0> b_blc_l<31> b_blc_l<30> b_blc_l<29> b_blc_l<28> b_blc_l<27> b_blc_l<26> b_blc_l<25> b_blc_l<24> b_blc_l<23> b_blc_l<22> b_blc_l<21> b_blc_l<20> b_blc_l<19> b_blc_l<18> b_blc_l<17> b_blc_l<16> b_blc_l<15> b_blc_l<14> b_blc_l<13> b_blc_l<12> b_blc_l<11> b_blc_l<10> b_blc_l<9> b_blc_l<8> b_blc_l<7> b_blc_l<6> b_blc_l<5> b_blc_l<4> b_blc_l<3> b_blc_l<2> b_blc_l<1> b_blc_l<0> b_blt_l<31> b_blt_l<30> b_blt_l<29> b_blt_l<28> b_blt_l<27> b_blt_l<26> b_blt_l<25> b_blt_l<24> b_blt_l<23> b_blt_l<22> b_blt_l<21> b_blt_l<20> b_blt_l<19> b_blt_l<18> b_blt_l<17> b_blt_l<16> b_blt_l<15> b_blt_l<14> b_blt_l<13> b_blt_l<12> b_blt_l<11> b_blt_l<10> b_blt_l<9> b_blt_l<8> b_blt_l<7> b_blt_l<6> b_blt_l<5> b_blt_l<4> b_blt_l<3> b_blt_l<2> b_blt_l<1> b_blt_l<0> b_wl_l<255> b_wl_l<254> b_wl_l<253> b_wl_l<252> b_wl_l<251> b_wl_l<250> b_wl_l<249> b_wl_l<248> b_wl_l<247> b_wl_l<246> b_wl_l<245> b_wl_l<244> b_wl_l<243> b_wl_l<242> b_wl_l<241> b_wl_l<240> b_wl_l<239> b_wl_l<238> b_wl_l<237> b_wl_l<236> b_wl_l<235> b_wl_l<234> b_wl_l<233> b_wl_l<232> b_wl_l<231> b_wl_l<230> b_wl_l<229> b_wl_l<228> b_wl_l<227> b_wl_l<226> b_wl_l<225> b_wl_l<224> b_wl_l<223> b_wl_l<222> b_wl_l<221> b_wl_l<220> b_wl_l<219> b_wl_l<218> b_wl_l<217> b_wl_l<216> b_wl_l<215> b_wl_l<214> b_wl_l<213> b_wl_l<212> b_wl_l<211> b_wl_l<210> b_wl_l<209> b_wl_l<208> b_wl_l<207> b_wl_l<206> b_wl_l<205> b_wl_l<204> b_wl_l<203> b_wl_l<202> b_wl_l<201> b_wl_l<200> b_wl_l<199> b_wl_l<198> b_wl_l<197> b_wl_l<196> b_wl_l<195> b_wl_l<194> b_wl_l<193> b_wl_l<192> b_wl_l<191> b_wl_l<190> b_wl_l<189> b_wl_l<188> b_wl_l<187> b_wl_l<186> b_wl_l<185> b_wl_l<184> b_wl_l<183> b_wl_l<182> b_wl_l<181> b_wl_l<180> b_wl_l<179> b_wl_l<178> b_wl_l<177> b_wl_l<176> b_wl_l<175> b_wl_l<174> b_wl_l<173> b_wl_l<172> b_wl_l<171> b_wl_l<170> b_wl_l<169> b_wl_l<168> b_wl_l<167> b_wl_l<166> b_wl_l<165> b_wl_l<164> b_wl_l<163> b_wl_l<162> b_wl_l<161> b_wl_l<160> b_wl_l<159> b_wl_l<158> b_wl_l<157> b_wl_l<156> b_wl_l<155> b_wl_l<154> b_wl_l<153> b_wl_l<152> b_wl_l<151> b_wl_l<150> b_wl_l<149> b_wl_l<148> b_wl_l<147> b_wl_l<146> b_wl_l<145> b_wl_l<144> b_wl_l<143> b_wl_l<142> b_wl_l<141> b_wl_l<140> b_wl_l<139> b_wl_l<138> b_wl_l<137> b_wl_l<136> b_wl_l<135> b_wl_l<134> b_wl_l<133> b_wl_l<132> b_wl_l<131> b_wl_l<130> b_wl_l<129> b_wl_l<128> b_wl_l<127> b_wl_l<126> b_wl_l<125> b_wl_l<124> b_wl_l<123> b_wl_l<122> b_wl_l<121> b_wl_l<120> b_wl_l<119> b_wl_l<118> b_wl_l<117> b_wl_l<116> b_wl_l<115> b_wl_l<114> b_wl_l<113> b_wl_l<112> b_wl_l<111> b_wl_l<110> b_wl_l<109> b_wl_l<108> b_wl_l<107> b_wl_l<106> b_wl_l<105> b_wl_l<104> b_wl_l<103> b_wl_l<102> b_wl_l<101> b_wl_l<100> b_wl_l<99> b_wl_l<98> b_wl_l<97> b_wl_l<96> b_wl_l<95> b_wl_l<94> b_wl_l<93> b_wl_l<92> b_wl_l<91> b_wl_l<90> b_wl_l<89> b_wl_l<88> b_wl_l<87> b_wl_l<86> b_wl_l<85> b_wl_l<84> b_wl_l<83> b_wl_l<82> b_wl_l<81> b_wl_l<80> b_wl_l<79> b_wl_l<78> b_wl_l<77> b_wl_l<76> b_wl_l<75> b_wl_l<74> b_wl_l<73> b_wl_l<72> b_wl_l<71> b_wl_l<70> b_wl_l<69> b_wl_l<68> b_wl_l<67> b_wl_l<66> b_wl_l<65> b_wl_l<64> b_wl_l<63> b_wl_l<62> b_wl_l<61> b_wl_l<60> b_wl_l<59> b_wl_l<58> b_wl_l<57> b_wl_l<56> b_wl_l<55> b_wl_l<54> b_wl_l<53> b_wl_l<52> b_wl_l<51> b_wl_l<50> b_wl_l<49> b_wl_l<48> b_wl_l<47> b_wl_l<46> b_wl_l<45> b_wl_l<44> b_wl_l<43> b_wl_l<42> b_wl_l<41> b_wl_l<40> b_wl_l<39> b_wl_l<38> b_wl_l<37> b_wl_l<36> b_wl_l<35> b_wl_l<34> b_wl_l<33> b_wl_l<32> b_wl_l<31> b_wl_l<30> b_wl_l<29> b_wl_l<28> b_wl_l<27> b_wl_l<26> b_wl_l<25> b_wl_l<24> b_wl_l<23> b_wl_l<22> b_wl_l<21> b_wl_l<20> b_wl_l<19> b_wl_l<18> b_wl_l<17> b_wl_l<16> b_wl_l<15> b_wl_l<14> b_wl_l<13> b_wl_l<12> b_wl_l<11> b_wl_l<10> b_wl_l<9> b_wl_l<8> b_wl_l<7> b_wl_l<6> b_wl_l<5> b_wl_l<4> b_wl_l<3> b_wl_l<2> b_wl_l<1> b_wl_l<0> VDDARRAY! VSS! / RM_IHPSG13_1024x16_c2_2P_MATRIX_pcell_1 + + +XB_COLDRV<1> b_addr_col<1> b_addr_col<0> b_addr_col_r<1> b_addr_col_r<0> b_addr_dec<7> b_addr_dec<6> b_addr_dec<5> b_addr_dec<4> b_addr_dec<3> b_addr_dec<2> b_addr_dec<1> b_addr_dec<0> b_addr_dec_r<7> b_addr_dec_r<6> b_addr_dec_r<5> b_addr_dec_r<4> b_addr_dec_r<3> b_addr_dec_r<2> b_addr_dec_r<1> b_addr_dec_r<0> b_dclk b_dclk_p_r<0> b_rclk b_rclk_p_r<0> b_wclk b_wclk_p_r<0> VDD! VSS! / RM_IHPSG13_1024x16_c2_2P_COLDRV13X4 +XB_COLDRV<0> b_addr_col<1> b_addr_col<0> b_addr_col_l<1> b_addr_col_l<0> b_addr_dec<7> b_addr_dec<6> b_addr_dec<5> b_addr_dec<4> b_addr_dec<3> b_addr_dec<2> b_addr_dec<1> b_addr_dec<0> b_addr_dec_l<7> b_addr_dec_l<6> b_addr_dec_l<5> b_addr_dec_l<4> b_addr_dec_l<3> b_addr_dec_l<2> b_addr_dec_l<1> b_addr_dec_l<0> b_dclk b_dclk_p_l<0> b_rclk b_rclk_p_l<0> b_wclk b_wclk_p_l<0> VDD! VSS! / RM_IHPSG13_1024x16_c2_2P_COLDRV13X4 +XA_COLDRV<1> a_addr_col<1> a_addr_col<0> a_addr_col_r<1> a_addr_col_r<0> a_addr_dec<7> a_addr_dec<6> a_addr_dec<5> a_addr_dec<4> a_addr_dec<3> a_addr_dec<2> a_addr_dec<1> a_addr_dec<0> a_addr_dec_r<7> a_addr_dec_r<6> a_addr_dec_r<5> a_addr_dec_r<4> a_addr_dec_r<3> a_addr_dec_r<2> a_addr_dec_r<1> a_addr_dec_r<0> a_dclk a_dclk_p_r<0> a_rclk a_rclk_p_r<0> a_wclk a_wclk_p_r<0> VDD! VSS! / RM_IHPSG13_1024x16_c2_2P_COLDRV13X4 +XA_COLDRV<0> a_addr_col<1> a_addr_col<0> a_addr_col_l<1> a_addr_col_l<0> a_addr_dec<7> a_addr_dec<6> a_addr_dec<5> a_addr_dec<4> a_addr_dec<3> a_addr_dec<2> a_addr_dec<1> a_addr_dec<0> a_addr_dec_l<7> a_addr_dec_l<6> a_addr_dec_l<5> a_addr_dec_l<4> a_addr_dec_l<3> a_addr_dec_l<2> a_addr_dec_l<1> a_addr_dec_l<0> a_dclk a_dclk_p_l<0> a_rclk a_rclk_p_l<0> a_wclk a_wclk_p_l<0> VDD! VSS! / RM_IHPSG13_1024x16_c2_2P_COLDRV13X4 + + +XB_WLDRV<31> b_wi<255> b_wi<254> b_wi<253> b_wi<252> b_wi<251> b_wi<250> b_wi<249> b_wi<248> b_wi<247> b_wi<246> b_wi<245> b_wi<244> b_wi<243> b_wi<242> b_wi<241> b_wi<240> b_wl_r<255> b_wl_r<254> b_wl_r<253> b_wl_r<252> b_wl_r<251> b_wl_r<250> b_wl_r<249> b_wl_r<248> b_wl_r<247> b_wl_r<246> b_wl_r<245> b_wl_r<244> b_wl_r<243> b_wl_r<242> b_wl_r<241> b_wl_r<240> VDD! VSS! / RM_IHPSG13_1024x16_c2_2P_WLDRV16X4 +XB_WLDRV<30> b_wi<239> b_wi<238> b_wi<237> b_wi<236> b_wi<235> b_wi<234> b_wi<233> b_wi<232> b_wi<231> b_wi<230> b_wi<229> b_wi<228> b_wi<227> b_wi<226> b_wi<225> b_wi<224> b_wl_r<239> b_wl_r<238> b_wl_r<237> b_wl_r<236> b_wl_r<235> b_wl_r<234> b_wl_r<233> b_wl_r<232> b_wl_r<231> b_wl_r<230> b_wl_r<229> b_wl_r<228> b_wl_r<227> b_wl_r<226> b_wl_r<225> b_wl_r<224> VDD! VSS! / RM_IHPSG13_1024x16_c2_2P_WLDRV16X4 +XB_WLDRV<29> b_wi<223> b_wi<222> b_wi<221> b_wi<220> b_wi<219> b_wi<218> b_wi<217> b_wi<216> b_wi<215> b_wi<214> b_wi<213> b_wi<212> b_wi<211> b_wi<210> b_wi<209> b_wi<208> b_wl_r<223> b_wl_r<222> b_wl_r<221> b_wl_r<220> b_wl_r<219> b_wl_r<218> b_wl_r<217> b_wl_r<216> b_wl_r<215> b_wl_r<214> b_wl_r<213> b_wl_r<212> b_wl_r<211> b_wl_r<210> b_wl_r<209> b_wl_r<208> VDD! VSS! / RM_IHPSG13_1024x16_c2_2P_WLDRV16X4 +XB_WLDRV<28> b_wi<207> b_wi<206> b_wi<205> b_wi<204> b_wi<203> b_wi<202> b_wi<201> b_wi<200> b_wi<199> b_wi<198> b_wi<197> b_wi<196> b_wi<195> b_wi<194> b_wi<193> b_wi<192> b_wl_r<207> b_wl_r<206> b_wl_r<205> b_wl_r<204> b_wl_r<203> b_wl_r<202> b_wl_r<201> b_wl_r<200> b_wl_r<199> b_wl_r<198> b_wl_r<197> b_wl_r<196> b_wl_r<195> b_wl_r<194> b_wl_r<193> b_wl_r<192> VDD! VSS! / RM_IHPSG13_1024x16_c2_2P_WLDRV16X4 +XB_WLDRV<27> b_wi<191> b_wi<190> b_wi<189> b_wi<188> b_wi<187> b_wi<186> b_wi<185> b_wi<184> b_wi<183> b_wi<182> b_wi<181> b_wi<180> b_wi<179> b_wi<178> b_wi<177> b_wi<176> b_wl_r<191> b_wl_r<190> b_wl_r<189> b_wl_r<188> b_wl_r<187> b_wl_r<186> b_wl_r<185> b_wl_r<184> b_wl_r<183> b_wl_r<182> b_wl_r<181> b_wl_r<180> b_wl_r<179> b_wl_r<178> b_wl_r<177> b_wl_r<176> VDD! VSS! / RM_IHPSG13_1024x16_c2_2P_WLDRV16X4 +XB_WLDRV<26> b_wi<175> b_wi<174> b_wi<173> b_wi<172> b_wi<171> b_wi<170> b_wi<169> b_wi<168> b_wi<167> b_wi<166> b_wi<165> b_wi<164> b_wi<163> b_wi<162> b_wi<161> b_wi<160> b_wl_r<175> b_wl_r<174> b_wl_r<173> b_wl_r<172> b_wl_r<171> b_wl_r<170> b_wl_r<169> b_wl_r<168> b_wl_r<167> b_wl_r<166> b_wl_r<165> b_wl_r<164> b_wl_r<163> b_wl_r<162> b_wl_r<161> b_wl_r<160> VDD! VSS! / RM_IHPSG13_1024x16_c2_2P_WLDRV16X4 +XB_WLDRV<25> b_wi<159> b_wi<158> b_wi<157> b_wi<156> b_wi<155> b_wi<154> b_wi<153> b_wi<152> b_wi<151> b_wi<150> b_wi<149> b_wi<148> b_wi<147> b_wi<146> b_wi<145> b_wi<144> b_wl_r<159> b_wl_r<158> b_wl_r<157> b_wl_r<156> b_wl_r<155> b_wl_r<154> b_wl_r<153> b_wl_r<152> b_wl_r<151> b_wl_r<150> b_wl_r<149> b_wl_r<148> b_wl_r<147> b_wl_r<146> b_wl_r<145> b_wl_r<144> VDD! VSS! / RM_IHPSG13_1024x16_c2_2P_WLDRV16X4 +XB_WLDRV<24> b_wi<143> b_wi<142> b_wi<141> b_wi<140> b_wi<139> b_wi<138> b_wi<137> b_wi<136> b_wi<135> b_wi<134> b_wi<133> b_wi<132> b_wi<131> b_wi<130> b_wi<129> b_wi<128> b_wl_r<143> b_wl_r<142> b_wl_r<141> b_wl_r<140> b_wl_r<139> b_wl_r<138> b_wl_r<137> b_wl_r<136> b_wl_r<135> b_wl_r<134> b_wl_r<133> b_wl_r<132> b_wl_r<131> b_wl_r<130> b_wl_r<129> b_wl_r<128> VDD! VSS! / RM_IHPSG13_1024x16_c2_2P_WLDRV16X4 +XB_WLDRV<23> b_wi<127> b_wi<126> b_wi<125> b_wi<124> b_wi<123> b_wi<122> b_wi<121> b_wi<120> b_wi<119> b_wi<118> b_wi<117> b_wi<116> b_wi<115> b_wi<114> b_wi<113> b_wi<112> b_wl_r<127> b_wl_r<126> b_wl_r<125> b_wl_r<124> b_wl_r<123> b_wl_r<122> b_wl_r<121> b_wl_r<120> b_wl_r<119> b_wl_r<118> b_wl_r<117> b_wl_r<116> b_wl_r<115> b_wl_r<114> b_wl_r<113> b_wl_r<112> VDD! VSS! / RM_IHPSG13_1024x16_c2_2P_WLDRV16X4 +XB_WLDRV<22> b_wi<111> b_wi<110> b_wi<109> b_wi<108> b_wi<107> b_wi<106> b_wi<105> b_wi<104> b_wi<103> b_wi<102> b_wi<101> b_wi<100> b_wi<99> b_wi<98> b_wi<97> b_wi<96> b_wl_r<111> b_wl_r<110> b_wl_r<109> b_wl_r<108> b_wl_r<107> b_wl_r<106> b_wl_r<105> b_wl_r<104> b_wl_r<103> b_wl_r<102> b_wl_r<101> b_wl_r<100> b_wl_r<99> b_wl_r<98> b_wl_r<97> b_wl_r<96> VDD! VSS! / RM_IHPSG13_1024x16_c2_2P_WLDRV16X4 +XB_WLDRV<21> b_wi<95> b_wi<94> b_wi<93> b_wi<92> b_wi<91> b_wi<90> b_wi<89> b_wi<88> b_wi<87> b_wi<86> b_wi<85> b_wi<84> b_wi<83> b_wi<82> b_wi<81> b_wi<80> b_wl_r<95> b_wl_r<94> b_wl_r<93> b_wl_r<92> b_wl_r<91> b_wl_r<90> b_wl_r<89> b_wl_r<88> b_wl_r<87> b_wl_r<86> b_wl_r<85> b_wl_r<84> b_wl_r<83> b_wl_r<82> b_wl_r<81> b_wl_r<80> VDD! VSS! / RM_IHPSG13_1024x16_c2_2P_WLDRV16X4 +XB_WLDRV<20> b_wi<79> b_wi<78> b_wi<77> b_wi<76> b_wi<75> b_wi<74> b_wi<73> b_wi<72> b_wi<71> b_wi<70> b_wi<69> b_wi<68> b_wi<67> b_wi<66> b_wi<65> b_wi<64> b_wl_r<79> b_wl_r<78> b_wl_r<77> b_wl_r<76> b_wl_r<75> b_wl_r<74> b_wl_r<73> b_wl_r<72> b_wl_r<71> b_wl_r<70> b_wl_r<69> b_wl_r<68> b_wl_r<67> b_wl_r<66> b_wl_r<65> b_wl_r<64> VDD! VSS! / RM_IHPSG13_1024x16_c2_2P_WLDRV16X4 +XB_WLDRV<19> b_wi<63> b_wi<62> b_wi<61> b_wi<60> b_wi<59> b_wi<58> b_wi<57> b_wi<56> b_wi<55> b_wi<54> b_wi<53> b_wi<52> b_wi<51> b_wi<50> b_wi<49> b_wi<48> b_wl_r<63> b_wl_r<62> b_wl_r<61> b_wl_r<60> b_wl_r<59> b_wl_r<58> b_wl_r<57> b_wl_r<56> b_wl_r<55> b_wl_r<54> b_wl_r<53> b_wl_r<52> b_wl_r<51> b_wl_r<50> b_wl_r<49> b_wl_r<48> VDD! VSS! / RM_IHPSG13_1024x16_c2_2P_WLDRV16X4 +XB_WLDRV<18> b_wi<47> b_wi<46> b_wi<45> b_wi<44> b_wi<43> b_wi<42> b_wi<41> b_wi<40> b_wi<39> b_wi<38> b_wi<37> b_wi<36> b_wi<35> b_wi<34> b_wi<33> b_wi<32> b_wl_r<47> b_wl_r<46> b_wl_r<45> b_wl_r<44> b_wl_r<43> b_wl_r<42> b_wl_r<41> b_wl_r<40> b_wl_r<39> b_wl_r<38> b_wl_r<37> b_wl_r<36> b_wl_r<35> b_wl_r<34> b_wl_r<33> b_wl_r<32> VDD! VSS! / RM_IHPSG13_1024x16_c2_2P_WLDRV16X4 +XB_WLDRV<17> b_wi<31> b_wi<30> b_wi<29> b_wi<28> b_wi<27> b_wi<26> b_wi<25> b_wi<24> b_wi<23> b_wi<22> b_wi<21> b_wi<20> b_wi<19> b_wi<18> b_wi<17> b_wi<16> b_wl_r<31> b_wl_r<30> b_wl_r<29> b_wl_r<28> b_wl_r<27> b_wl_r<26> b_wl_r<25> b_wl_r<24> b_wl_r<23> b_wl_r<22> b_wl_r<21> b_wl_r<20> b_wl_r<19> b_wl_r<18> b_wl_r<17> b_wl_r<16> VDD! VSS! / RM_IHPSG13_1024x16_c2_2P_WLDRV16X4 +XB_WLDRV<16> b_wi<15> b_wi<14> b_wi<13> b_wi<12> b_wi<11> b_wi<10> b_wi<9> b_wi<8> b_wi<7> b_wi<6> b_wi<5> b_wi<4> b_wi<3> b_wi<2> b_wi<1> b_wi<0> b_wl_r<15> b_wl_r<14> b_wl_r<13> b_wl_r<12> b_wl_r<11> b_wl_r<10> b_wl_r<9> b_wl_r<8> b_wl_r<7> b_wl_r<6> b_wl_r<5> b_wl_r<4> b_wl_r<3> b_wl_r<2> b_wl_r<1> b_wl_r<0> VDD! VSS! / RM_IHPSG13_1024x16_c2_2P_WLDRV16X4 +XB_WLDRV<15> b_wi<255> b_wi<254> b_wi<253> b_wi<252> b_wi<251> b_wi<250> b_wi<249> b_wi<248> b_wi<247> b_wi<246> b_wi<245> b_wi<244> b_wi<243> b_wi<242> b_wi<241> b_wi<240> b_wl_l<255> b_wl_l<254> b_wl_l<253> b_wl_l<252> b_wl_l<251> b_wl_l<250> b_wl_l<249> b_wl_l<248> b_wl_l<247> b_wl_l<246> b_wl_l<245> b_wl_l<244> b_wl_l<243> b_wl_l<242> b_wl_l<241> b_wl_l<240> VDD! VSS! / RM_IHPSG13_1024x16_c2_2P_WLDRV16X4 +XB_WLDRV<14> b_wi<239> b_wi<238> b_wi<237> b_wi<236> b_wi<235> b_wi<234> b_wi<233> b_wi<232> b_wi<231> b_wi<230> b_wi<229> b_wi<228> b_wi<227> b_wi<226> b_wi<225> b_wi<224> b_wl_l<239> b_wl_l<238> b_wl_l<237> b_wl_l<236> b_wl_l<235> b_wl_l<234> b_wl_l<233> b_wl_l<232> b_wl_l<231> b_wl_l<230> b_wl_l<229> b_wl_l<228> b_wl_l<227> b_wl_l<226> b_wl_l<225> b_wl_l<224> VDD! VSS! / RM_IHPSG13_1024x16_c2_2P_WLDRV16X4 +XB_WLDRV<13> b_wi<223> b_wi<222> b_wi<221> b_wi<220> b_wi<219> b_wi<218> b_wi<217> b_wi<216> b_wi<215> b_wi<214> b_wi<213> b_wi<212> b_wi<211> b_wi<210> b_wi<209> b_wi<208> b_wl_l<223> b_wl_l<222> b_wl_l<221> b_wl_l<220> b_wl_l<219> b_wl_l<218> b_wl_l<217> b_wl_l<216> b_wl_l<215> b_wl_l<214> b_wl_l<213> b_wl_l<212> b_wl_l<211> b_wl_l<210> b_wl_l<209> b_wl_l<208> VDD! VSS! / RM_IHPSG13_1024x16_c2_2P_WLDRV16X4 +XB_WLDRV<12> b_wi<207> b_wi<206> b_wi<205> b_wi<204> b_wi<203> b_wi<202> b_wi<201> b_wi<200> b_wi<199> b_wi<198> b_wi<197> b_wi<196> b_wi<195> b_wi<194> b_wi<193> b_wi<192> b_wl_l<207> b_wl_l<206> b_wl_l<205> b_wl_l<204> b_wl_l<203> b_wl_l<202> b_wl_l<201> b_wl_l<200> b_wl_l<199> b_wl_l<198> b_wl_l<197> b_wl_l<196> b_wl_l<195> b_wl_l<194> b_wl_l<193> b_wl_l<192> VDD! VSS! / RM_IHPSG13_1024x16_c2_2P_WLDRV16X4 +XB_WLDRV<11> b_wi<191> b_wi<190> b_wi<189> b_wi<188> b_wi<187> b_wi<186> b_wi<185> b_wi<184> b_wi<183> b_wi<182> b_wi<181> b_wi<180> b_wi<179> b_wi<178> b_wi<177> b_wi<176> b_wl_l<191> b_wl_l<190> b_wl_l<189> b_wl_l<188> b_wl_l<187> b_wl_l<186> b_wl_l<185> b_wl_l<184> b_wl_l<183> b_wl_l<182> b_wl_l<181> b_wl_l<180> b_wl_l<179> b_wl_l<178> b_wl_l<177> b_wl_l<176> VDD! VSS! / RM_IHPSG13_1024x16_c2_2P_WLDRV16X4 +XB_WLDRV<10> b_wi<175> b_wi<174> b_wi<173> b_wi<172> b_wi<171> b_wi<170> b_wi<169> b_wi<168> b_wi<167> b_wi<166> b_wi<165> b_wi<164> b_wi<163> b_wi<162> b_wi<161> b_wi<160> b_wl_l<175> b_wl_l<174> b_wl_l<173> b_wl_l<172> b_wl_l<171> b_wl_l<170> b_wl_l<169> b_wl_l<168> b_wl_l<167> b_wl_l<166> b_wl_l<165> b_wl_l<164> b_wl_l<163> b_wl_l<162> b_wl_l<161> b_wl_l<160> VDD! VSS! / RM_IHPSG13_1024x16_c2_2P_WLDRV16X4 +XB_WLDRV<9> b_wi<159> b_wi<158> b_wi<157> b_wi<156> b_wi<155> b_wi<154> b_wi<153> b_wi<152> b_wi<151> b_wi<150> b_wi<149> b_wi<148> b_wi<147> b_wi<146> b_wi<145> b_wi<144> b_wl_l<159> b_wl_l<158> b_wl_l<157> b_wl_l<156> b_wl_l<155> b_wl_l<154> b_wl_l<153> b_wl_l<152> b_wl_l<151> b_wl_l<150> b_wl_l<149> b_wl_l<148> b_wl_l<147> b_wl_l<146> b_wl_l<145> b_wl_l<144> VDD! VSS! / RM_IHPSG13_1024x16_c2_2P_WLDRV16X4 +XB_WLDRV<8> b_wi<143> b_wi<142> b_wi<141> b_wi<140> b_wi<139> b_wi<138> b_wi<137> b_wi<136> b_wi<135> b_wi<134> b_wi<133> b_wi<132> b_wi<131> b_wi<130> b_wi<129> b_wi<128> b_wl_l<143> b_wl_l<142> b_wl_l<141> b_wl_l<140> b_wl_l<139> b_wl_l<138> b_wl_l<137> b_wl_l<136> b_wl_l<135> b_wl_l<134> b_wl_l<133> b_wl_l<132> b_wl_l<131> b_wl_l<130> b_wl_l<129> b_wl_l<128> VDD! VSS! / RM_IHPSG13_1024x16_c2_2P_WLDRV16X4 +XB_WLDRV<7> b_wi<127> b_wi<126> b_wi<125> b_wi<124> b_wi<123> b_wi<122> b_wi<121> b_wi<120> b_wi<119> b_wi<118> b_wi<117> b_wi<116> b_wi<115> b_wi<114> b_wi<113> b_wi<112> b_wl_l<127> b_wl_l<126> b_wl_l<125> b_wl_l<124> b_wl_l<123> b_wl_l<122> b_wl_l<121> b_wl_l<120> b_wl_l<119> b_wl_l<118> b_wl_l<117> b_wl_l<116> b_wl_l<115> b_wl_l<114> b_wl_l<113> b_wl_l<112> VDD! VSS! / RM_IHPSG13_1024x16_c2_2P_WLDRV16X4 +XB_WLDRV<6> b_wi<111> b_wi<110> b_wi<109> b_wi<108> b_wi<107> b_wi<106> b_wi<105> b_wi<104> b_wi<103> b_wi<102> b_wi<101> b_wi<100> b_wi<99> b_wi<98> b_wi<97> b_wi<96> b_wl_l<111> b_wl_l<110> b_wl_l<109> b_wl_l<108> b_wl_l<107> b_wl_l<106> b_wl_l<105> b_wl_l<104> b_wl_l<103> b_wl_l<102> b_wl_l<101> b_wl_l<100> b_wl_l<99> b_wl_l<98> b_wl_l<97> b_wl_l<96> VDD! VSS! / RM_IHPSG13_1024x16_c2_2P_WLDRV16X4 +XB_WLDRV<5> b_wi<95> b_wi<94> b_wi<93> b_wi<92> b_wi<91> b_wi<90> b_wi<89> b_wi<88> b_wi<87> b_wi<86> b_wi<85> b_wi<84> b_wi<83> b_wi<82> b_wi<81> b_wi<80> b_wl_l<95> b_wl_l<94> b_wl_l<93> b_wl_l<92> b_wl_l<91> b_wl_l<90> b_wl_l<89> b_wl_l<88> b_wl_l<87> b_wl_l<86> b_wl_l<85> b_wl_l<84> b_wl_l<83> b_wl_l<82> b_wl_l<81> b_wl_l<80> VDD! VSS! / RM_IHPSG13_1024x16_c2_2P_WLDRV16X4 +XB_WLDRV<4> b_wi<79> b_wi<78> b_wi<77> b_wi<76> b_wi<75> b_wi<74> b_wi<73> b_wi<72> b_wi<71> b_wi<70> b_wi<69> b_wi<68> b_wi<67> b_wi<66> b_wi<65> b_wi<64> b_wl_l<79> b_wl_l<78> b_wl_l<77> b_wl_l<76> b_wl_l<75> b_wl_l<74> b_wl_l<73> b_wl_l<72> b_wl_l<71> b_wl_l<70> b_wl_l<69> b_wl_l<68> b_wl_l<67> b_wl_l<66> b_wl_l<65> b_wl_l<64> VDD! VSS! / RM_IHPSG13_1024x16_c2_2P_WLDRV16X4 +XB_WLDRV<3> b_wi<63> b_wi<62> b_wi<61> b_wi<60> b_wi<59> b_wi<58> b_wi<57> b_wi<56> b_wi<55> b_wi<54> b_wi<53> b_wi<52> b_wi<51> b_wi<50> b_wi<49> b_wi<48> b_wl_l<63> b_wl_l<62> b_wl_l<61> b_wl_l<60> b_wl_l<59> b_wl_l<58> b_wl_l<57> b_wl_l<56> b_wl_l<55> b_wl_l<54> b_wl_l<53> b_wl_l<52> b_wl_l<51> b_wl_l<50> b_wl_l<49> b_wl_l<48> VDD! VSS! / RM_IHPSG13_1024x16_c2_2P_WLDRV16X4 +XB_WLDRV<2> b_wi<47> b_wi<46> b_wi<45> b_wi<44> b_wi<43> b_wi<42> b_wi<41> b_wi<40> b_wi<39> b_wi<38> b_wi<37> b_wi<36> b_wi<35> b_wi<34> b_wi<33> b_wi<32> b_wl_l<47> b_wl_l<46> b_wl_l<45> b_wl_l<44> b_wl_l<43> b_wl_l<42> b_wl_l<41> b_wl_l<40> b_wl_l<39> b_wl_l<38> b_wl_l<37> b_wl_l<36> b_wl_l<35> b_wl_l<34> b_wl_l<33> b_wl_l<32> VDD! VSS! / RM_IHPSG13_1024x16_c2_2P_WLDRV16X4 +XB_WLDRV<1> b_wi<31> b_wi<30> b_wi<29> b_wi<28> b_wi<27> b_wi<26> b_wi<25> b_wi<24> b_wi<23> b_wi<22> b_wi<21> b_wi<20> b_wi<19> b_wi<18> b_wi<17> b_wi<16> b_wl_l<31> b_wl_l<30> b_wl_l<29> b_wl_l<28> b_wl_l<27> b_wl_l<26> b_wl_l<25> b_wl_l<24> b_wl_l<23> b_wl_l<22> b_wl_l<21> b_wl_l<20> b_wl_l<19> b_wl_l<18> b_wl_l<17> b_wl_l<16> VDD! VSS! / RM_IHPSG13_1024x16_c2_2P_WLDRV16X4 +XB_WLDRV<0> b_wi<15> b_wi<14> b_wi<13> b_wi<12> b_wi<11> b_wi<10> b_wi<9> b_wi<8> b_wi<7> b_wi<6> b_wi<5> b_wi<4> b_wi<3> b_wi<2> b_wi<1> b_wi<0> b_wl_l<15> b_wl_l<14> b_wl_l<13> b_wl_l<12> b_wl_l<11> b_wl_l<10> b_wl_l<9> b_wl_l<8> b_wl_l<7> b_wl_l<6> b_wl_l<5> b_wl_l<4> b_wl_l<3> b_wl_l<2> b_wl_l<1> b_wl_l<0> VDD! VSS! / RM_IHPSG13_1024x16_c2_2P_WLDRV16X4 +XA_WLDRV<31> a_wi<255> a_wi<254> a_wi<253> a_wi<252> a_wi<251> a_wi<250> a_wi<249> a_wi<248> a_wi<247> a_wi<246> a_wi<245> a_wi<244> a_wi<243> a_wi<242> a_wi<241> a_wi<240> a_wl_r<255> a_wl_r<254> a_wl_r<253> a_wl_r<252> a_wl_r<251> a_wl_r<250> a_wl_r<249> a_wl_r<248> a_wl_r<247> a_wl_r<246> a_wl_r<245> a_wl_r<244> a_wl_r<243> a_wl_r<242> a_wl_r<241> a_wl_r<240> VDD! VSS! / RM_IHPSG13_1024x16_c2_2P_WLDRV16X4 +XA_WLDRV<30> a_wi<239> a_wi<238> a_wi<237> a_wi<236> a_wi<235> a_wi<234> a_wi<233> a_wi<232> a_wi<231> a_wi<230> a_wi<229> a_wi<228> a_wi<227> a_wi<226> a_wi<225> a_wi<224> a_wl_r<239> a_wl_r<238> a_wl_r<237> a_wl_r<236> a_wl_r<235> a_wl_r<234> a_wl_r<233> a_wl_r<232> a_wl_r<231> a_wl_r<230> a_wl_r<229> a_wl_r<228> a_wl_r<227> a_wl_r<226> a_wl_r<225> a_wl_r<224> VDD! VSS! / RM_IHPSG13_1024x16_c2_2P_WLDRV16X4 +XA_WLDRV<29> a_wi<223> a_wi<222> a_wi<221> a_wi<220> a_wi<219> a_wi<218> a_wi<217> a_wi<216> a_wi<215> a_wi<214> a_wi<213> a_wi<212> a_wi<211> a_wi<210> a_wi<209> a_wi<208> a_wl_r<223> a_wl_r<222> a_wl_r<221> a_wl_r<220> a_wl_r<219> a_wl_r<218> a_wl_r<217> a_wl_r<216> a_wl_r<215> a_wl_r<214> a_wl_r<213> a_wl_r<212> a_wl_r<211> a_wl_r<210> a_wl_r<209> a_wl_r<208> VDD! VSS! / RM_IHPSG13_1024x16_c2_2P_WLDRV16X4 +XA_WLDRV<28> a_wi<207> a_wi<206> a_wi<205> a_wi<204> a_wi<203> a_wi<202> a_wi<201> a_wi<200> a_wi<199> a_wi<198> a_wi<197> a_wi<196> a_wi<195> a_wi<194> a_wi<193> a_wi<192> a_wl_r<207> a_wl_r<206> a_wl_r<205> a_wl_r<204> a_wl_r<203> a_wl_r<202> a_wl_r<201> a_wl_r<200> a_wl_r<199> a_wl_r<198> a_wl_r<197> a_wl_r<196> a_wl_r<195> a_wl_r<194> a_wl_r<193> a_wl_r<192> VDD! VSS! / RM_IHPSG13_1024x16_c2_2P_WLDRV16X4 +XA_WLDRV<27> a_wi<191> a_wi<190> a_wi<189> a_wi<188> a_wi<187> a_wi<186> a_wi<185> a_wi<184> a_wi<183> a_wi<182> a_wi<181> a_wi<180> a_wi<179> a_wi<178> a_wi<177> a_wi<176> a_wl_r<191> a_wl_r<190> a_wl_r<189> a_wl_r<188> a_wl_r<187> a_wl_r<186> a_wl_r<185> a_wl_r<184> a_wl_r<183> a_wl_r<182> a_wl_r<181> a_wl_r<180> a_wl_r<179> a_wl_r<178> a_wl_r<177> a_wl_r<176> VDD! VSS! / RM_IHPSG13_1024x16_c2_2P_WLDRV16X4 +XA_WLDRV<26> a_wi<175> a_wi<174> a_wi<173> a_wi<172> a_wi<171> a_wi<170> a_wi<169> a_wi<168> a_wi<167> a_wi<166> a_wi<165> a_wi<164> a_wi<163> a_wi<162> a_wi<161> a_wi<160> a_wl_r<175> a_wl_r<174> a_wl_r<173> a_wl_r<172> a_wl_r<171> a_wl_r<170> a_wl_r<169> a_wl_r<168> a_wl_r<167> a_wl_r<166> a_wl_r<165> a_wl_r<164> a_wl_r<163> a_wl_r<162> a_wl_r<161> a_wl_r<160> VDD! VSS! / RM_IHPSG13_1024x16_c2_2P_WLDRV16X4 +XA_WLDRV<25> a_wi<159> a_wi<158> a_wi<157> a_wi<156> a_wi<155> a_wi<154> a_wi<153> a_wi<152> a_wi<151> a_wi<150> a_wi<149> a_wi<148> a_wi<147> a_wi<146> a_wi<145> a_wi<144> a_wl_r<159> a_wl_r<158> a_wl_r<157> a_wl_r<156> a_wl_r<155> a_wl_r<154> a_wl_r<153> a_wl_r<152> a_wl_r<151> a_wl_r<150> a_wl_r<149> a_wl_r<148> a_wl_r<147> a_wl_r<146> a_wl_r<145> a_wl_r<144> VDD! VSS! / RM_IHPSG13_1024x16_c2_2P_WLDRV16X4 +XA_WLDRV<24> a_wi<143> a_wi<142> a_wi<141> a_wi<140> a_wi<139> a_wi<138> a_wi<137> a_wi<136> a_wi<135> a_wi<134> a_wi<133> a_wi<132> a_wi<131> a_wi<130> a_wi<129> a_wi<128> a_wl_r<143> a_wl_r<142> a_wl_r<141> a_wl_r<140> a_wl_r<139> a_wl_r<138> a_wl_r<137> a_wl_r<136> a_wl_r<135> a_wl_r<134> a_wl_r<133> a_wl_r<132> a_wl_r<131> a_wl_r<130> a_wl_r<129> a_wl_r<128> VDD! VSS! / RM_IHPSG13_1024x16_c2_2P_WLDRV16X4 +XA_WLDRV<23> a_wi<127> a_wi<126> a_wi<125> a_wi<124> a_wi<123> a_wi<122> a_wi<121> a_wi<120> a_wi<119> a_wi<118> a_wi<117> a_wi<116> a_wi<115> a_wi<114> a_wi<113> a_wi<112> a_wl_r<127> a_wl_r<126> a_wl_r<125> a_wl_r<124> a_wl_r<123> a_wl_r<122> a_wl_r<121> a_wl_r<120> a_wl_r<119> a_wl_r<118> a_wl_r<117> a_wl_r<116> a_wl_r<115> a_wl_r<114> a_wl_r<113> a_wl_r<112> VDD! VSS! / RM_IHPSG13_1024x16_c2_2P_WLDRV16X4 +XA_WLDRV<22> a_wi<111> a_wi<110> a_wi<109> a_wi<108> a_wi<107> a_wi<106> a_wi<105> a_wi<104> a_wi<103> a_wi<102> a_wi<101> a_wi<100> a_wi<99> a_wi<98> a_wi<97> a_wi<96> a_wl_r<111> a_wl_r<110> a_wl_r<109> a_wl_r<108> a_wl_r<107> a_wl_r<106> a_wl_r<105> a_wl_r<104> a_wl_r<103> a_wl_r<102> a_wl_r<101> a_wl_r<100> a_wl_r<99> a_wl_r<98> a_wl_r<97> a_wl_r<96> VDD! VSS! / RM_IHPSG13_1024x16_c2_2P_WLDRV16X4 +XA_WLDRV<21> a_wi<95> a_wi<94> a_wi<93> a_wi<92> a_wi<91> a_wi<90> a_wi<89> a_wi<88> a_wi<87> a_wi<86> a_wi<85> a_wi<84> a_wi<83> a_wi<82> a_wi<81> a_wi<80> a_wl_r<95> a_wl_r<94> a_wl_r<93> a_wl_r<92> a_wl_r<91> a_wl_r<90> a_wl_r<89> a_wl_r<88> a_wl_r<87> a_wl_r<86> a_wl_r<85> a_wl_r<84> a_wl_r<83> a_wl_r<82> a_wl_r<81> a_wl_r<80> VDD! VSS! / RM_IHPSG13_1024x16_c2_2P_WLDRV16X4 +XA_WLDRV<20> a_wi<79> a_wi<78> a_wi<77> a_wi<76> a_wi<75> a_wi<74> a_wi<73> a_wi<72> a_wi<71> a_wi<70> a_wi<69> a_wi<68> a_wi<67> a_wi<66> a_wi<65> a_wi<64> a_wl_r<79> a_wl_r<78> a_wl_r<77> a_wl_r<76> a_wl_r<75> a_wl_r<74> a_wl_r<73> a_wl_r<72> a_wl_r<71> a_wl_r<70> a_wl_r<69> a_wl_r<68> a_wl_r<67> a_wl_r<66> a_wl_r<65> a_wl_r<64> VDD! VSS! / RM_IHPSG13_1024x16_c2_2P_WLDRV16X4 +XA_WLDRV<19> a_wi<63> a_wi<62> a_wi<61> a_wi<60> a_wi<59> a_wi<58> a_wi<57> a_wi<56> a_wi<55> a_wi<54> a_wi<53> a_wi<52> a_wi<51> a_wi<50> a_wi<49> a_wi<48> a_wl_r<63> a_wl_r<62> a_wl_r<61> a_wl_r<60> a_wl_r<59> a_wl_r<58> a_wl_r<57> a_wl_r<56> a_wl_r<55> a_wl_r<54> a_wl_r<53> a_wl_r<52> a_wl_r<51> a_wl_r<50> a_wl_r<49> a_wl_r<48> VDD! VSS! / RM_IHPSG13_1024x16_c2_2P_WLDRV16X4 +XA_WLDRV<18> a_wi<47> a_wi<46> a_wi<45> a_wi<44> a_wi<43> a_wi<42> a_wi<41> a_wi<40> a_wi<39> a_wi<38> a_wi<37> a_wi<36> a_wi<35> a_wi<34> a_wi<33> a_wi<32> a_wl_r<47> a_wl_r<46> a_wl_r<45> a_wl_r<44> a_wl_r<43> a_wl_r<42> a_wl_r<41> a_wl_r<40> a_wl_r<39> a_wl_r<38> a_wl_r<37> a_wl_r<36> a_wl_r<35> a_wl_r<34> a_wl_r<33> a_wl_r<32> VDD! VSS! / RM_IHPSG13_1024x16_c2_2P_WLDRV16X4 +XA_WLDRV<17> a_wi<31> a_wi<30> a_wi<29> a_wi<28> a_wi<27> a_wi<26> a_wi<25> a_wi<24> a_wi<23> a_wi<22> a_wi<21> a_wi<20> a_wi<19> a_wi<18> a_wi<17> a_wi<16> a_wl_r<31> a_wl_r<30> a_wl_r<29> a_wl_r<28> a_wl_r<27> a_wl_r<26> a_wl_r<25> a_wl_r<24> a_wl_r<23> a_wl_r<22> a_wl_r<21> a_wl_r<20> a_wl_r<19> a_wl_r<18> a_wl_r<17> a_wl_r<16> VDD! VSS! / RM_IHPSG13_1024x16_c2_2P_WLDRV16X4 +XA_WLDRV<16> a_wi<15> a_wi<14> a_wi<13> a_wi<12> a_wi<11> a_wi<10> a_wi<9> a_wi<8> a_wi<7> a_wi<6> a_wi<5> a_wi<4> a_wi<3> a_wi<2> a_wi<1> a_wi<0> a_wl_r<15> a_wl_r<14> a_wl_r<13> a_wl_r<12> a_wl_r<11> a_wl_r<10> a_wl_r<9> a_wl_r<8> a_wl_r<7> a_wl_r<6> a_wl_r<5> a_wl_r<4> a_wl_r<3> a_wl_r<2> a_wl_r<1> a_wl_r<0> VDD! VSS! / RM_IHPSG13_1024x16_c2_2P_WLDRV16X4 +XA_WLDRV<15> a_wi<255> a_wi<254> a_wi<253> a_wi<252> a_wi<251> a_wi<250> a_wi<249> a_wi<248> a_wi<247> a_wi<246> a_wi<245> a_wi<244> a_wi<243> a_wi<242> a_wi<241> a_wi<240> a_wl_l<255> a_wl_l<254> a_wl_l<253> a_wl_l<252> a_wl_l<251> a_wl_l<250> a_wl_l<249> a_wl_l<248> a_wl_l<247> a_wl_l<246> a_wl_l<245> a_wl_l<244> a_wl_l<243> a_wl_l<242> a_wl_l<241> a_wl_l<240> VDD! VSS! / RM_IHPSG13_1024x16_c2_2P_WLDRV16X4 +XA_WLDRV<14> a_wi<239> a_wi<238> a_wi<237> a_wi<236> a_wi<235> a_wi<234> a_wi<233> a_wi<232> a_wi<231> a_wi<230> a_wi<229> a_wi<228> a_wi<227> a_wi<226> a_wi<225> a_wi<224> a_wl_l<239> a_wl_l<238> a_wl_l<237> a_wl_l<236> a_wl_l<235> a_wl_l<234> a_wl_l<233> a_wl_l<232> a_wl_l<231> a_wl_l<230> a_wl_l<229> a_wl_l<228> a_wl_l<227> a_wl_l<226> a_wl_l<225> a_wl_l<224> VDD! VSS! / RM_IHPSG13_1024x16_c2_2P_WLDRV16X4 +XA_WLDRV<13> a_wi<223> a_wi<222> a_wi<221> a_wi<220> a_wi<219> a_wi<218> a_wi<217> a_wi<216> a_wi<215> a_wi<214> a_wi<213> a_wi<212> a_wi<211> a_wi<210> a_wi<209> a_wi<208> a_wl_l<223> a_wl_l<222> a_wl_l<221> a_wl_l<220> a_wl_l<219> a_wl_l<218> a_wl_l<217> a_wl_l<216> a_wl_l<215> a_wl_l<214> a_wl_l<213> a_wl_l<212> a_wl_l<211> a_wl_l<210> a_wl_l<209> a_wl_l<208> VDD! VSS! / RM_IHPSG13_1024x16_c2_2P_WLDRV16X4 +XA_WLDRV<12> a_wi<207> a_wi<206> a_wi<205> a_wi<204> a_wi<203> a_wi<202> a_wi<201> a_wi<200> a_wi<199> a_wi<198> a_wi<197> a_wi<196> a_wi<195> a_wi<194> a_wi<193> a_wi<192> a_wl_l<207> a_wl_l<206> a_wl_l<205> a_wl_l<204> a_wl_l<203> a_wl_l<202> a_wl_l<201> a_wl_l<200> a_wl_l<199> a_wl_l<198> a_wl_l<197> a_wl_l<196> a_wl_l<195> a_wl_l<194> a_wl_l<193> a_wl_l<192> VDD! VSS! / RM_IHPSG13_1024x16_c2_2P_WLDRV16X4 +XA_WLDRV<11> a_wi<191> a_wi<190> a_wi<189> a_wi<188> a_wi<187> a_wi<186> a_wi<185> a_wi<184> a_wi<183> a_wi<182> a_wi<181> a_wi<180> a_wi<179> a_wi<178> a_wi<177> a_wi<176> a_wl_l<191> a_wl_l<190> a_wl_l<189> a_wl_l<188> a_wl_l<187> a_wl_l<186> a_wl_l<185> a_wl_l<184> a_wl_l<183> a_wl_l<182> a_wl_l<181> a_wl_l<180> a_wl_l<179> a_wl_l<178> a_wl_l<177> a_wl_l<176> VDD! VSS! / RM_IHPSG13_1024x16_c2_2P_WLDRV16X4 +XA_WLDRV<10> a_wi<175> a_wi<174> a_wi<173> a_wi<172> a_wi<171> a_wi<170> a_wi<169> a_wi<168> a_wi<167> a_wi<166> a_wi<165> a_wi<164> a_wi<163> a_wi<162> a_wi<161> a_wi<160> a_wl_l<175> a_wl_l<174> a_wl_l<173> a_wl_l<172> a_wl_l<171> a_wl_l<170> a_wl_l<169> a_wl_l<168> a_wl_l<167> a_wl_l<166> a_wl_l<165> a_wl_l<164> a_wl_l<163> a_wl_l<162> a_wl_l<161> a_wl_l<160> VDD! VSS! / RM_IHPSG13_1024x16_c2_2P_WLDRV16X4 +XA_WLDRV<9> a_wi<159> a_wi<158> a_wi<157> a_wi<156> a_wi<155> a_wi<154> a_wi<153> a_wi<152> a_wi<151> a_wi<150> a_wi<149> a_wi<148> a_wi<147> a_wi<146> a_wi<145> a_wi<144> a_wl_l<159> a_wl_l<158> a_wl_l<157> a_wl_l<156> a_wl_l<155> a_wl_l<154> a_wl_l<153> a_wl_l<152> a_wl_l<151> a_wl_l<150> a_wl_l<149> a_wl_l<148> a_wl_l<147> a_wl_l<146> a_wl_l<145> a_wl_l<144> VDD! VSS! / RM_IHPSG13_1024x16_c2_2P_WLDRV16X4 +XA_WLDRV<8> a_wi<143> a_wi<142> a_wi<141> a_wi<140> a_wi<139> a_wi<138> a_wi<137> a_wi<136> a_wi<135> a_wi<134> a_wi<133> a_wi<132> a_wi<131> a_wi<130> a_wi<129> a_wi<128> a_wl_l<143> a_wl_l<142> a_wl_l<141> a_wl_l<140> a_wl_l<139> a_wl_l<138> a_wl_l<137> a_wl_l<136> a_wl_l<135> a_wl_l<134> a_wl_l<133> a_wl_l<132> a_wl_l<131> a_wl_l<130> a_wl_l<129> a_wl_l<128> VDD! VSS! / RM_IHPSG13_1024x16_c2_2P_WLDRV16X4 +XA_WLDRV<7> a_wi<127> a_wi<126> a_wi<125> a_wi<124> a_wi<123> a_wi<122> a_wi<121> a_wi<120> a_wi<119> a_wi<118> a_wi<117> a_wi<116> a_wi<115> a_wi<114> a_wi<113> a_wi<112> a_wl_l<127> a_wl_l<126> a_wl_l<125> a_wl_l<124> a_wl_l<123> a_wl_l<122> a_wl_l<121> a_wl_l<120> a_wl_l<119> a_wl_l<118> a_wl_l<117> a_wl_l<116> a_wl_l<115> a_wl_l<114> a_wl_l<113> a_wl_l<112> VDD! VSS! / RM_IHPSG13_1024x16_c2_2P_WLDRV16X4 +XA_WLDRV<6> a_wi<111> a_wi<110> a_wi<109> a_wi<108> a_wi<107> a_wi<106> a_wi<105> a_wi<104> a_wi<103> a_wi<102> a_wi<101> a_wi<100> a_wi<99> a_wi<98> a_wi<97> a_wi<96> a_wl_l<111> a_wl_l<110> a_wl_l<109> a_wl_l<108> a_wl_l<107> a_wl_l<106> a_wl_l<105> a_wl_l<104> a_wl_l<103> a_wl_l<102> a_wl_l<101> a_wl_l<100> a_wl_l<99> a_wl_l<98> a_wl_l<97> a_wl_l<96> VDD! VSS! / RM_IHPSG13_1024x16_c2_2P_WLDRV16X4 +XA_WLDRV<5> a_wi<95> a_wi<94> a_wi<93> a_wi<92> a_wi<91> a_wi<90> a_wi<89> a_wi<88> a_wi<87> a_wi<86> a_wi<85> a_wi<84> a_wi<83> a_wi<82> a_wi<81> a_wi<80> a_wl_l<95> a_wl_l<94> a_wl_l<93> a_wl_l<92> a_wl_l<91> a_wl_l<90> a_wl_l<89> a_wl_l<88> a_wl_l<87> a_wl_l<86> a_wl_l<85> a_wl_l<84> a_wl_l<83> a_wl_l<82> a_wl_l<81> a_wl_l<80> VDD! VSS! / RM_IHPSG13_1024x16_c2_2P_WLDRV16X4 +XA_WLDRV<4> a_wi<79> a_wi<78> a_wi<77> a_wi<76> a_wi<75> a_wi<74> a_wi<73> a_wi<72> a_wi<71> a_wi<70> a_wi<69> a_wi<68> a_wi<67> a_wi<66> a_wi<65> a_wi<64> a_wl_l<79> a_wl_l<78> a_wl_l<77> a_wl_l<76> a_wl_l<75> a_wl_l<74> a_wl_l<73> a_wl_l<72> a_wl_l<71> a_wl_l<70> a_wl_l<69> a_wl_l<68> a_wl_l<67> a_wl_l<66> a_wl_l<65> a_wl_l<64> VDD! VSS! / RM_IHPSG13_1024x16_c2_2P_WLDRV16X4 +XA_WLDRV<3> a_wi<63> a_wi<62> a_wi<61> a_wi<60> a_wi<59> a_wi<58> a_wi<57> a_wi<56> a_wi<55> a_wi<54> a_wi<53> a_wi<52> a_wi<51> a_wi<50> a_wi<49> a_wi<48> a_wl_l<63> a_wl_l<62> a_wl_l<61> a_wl_l<60> a_wl_l<59> a_wl_l<58> a_wl_l<57> a_wl_l<56> a_wl_l<55> a_wl_l<54> a_wl_l<53> a_wl_l<52> a_wl_l<51> a_wl_l<50> a_wl_l<49> a_wl_l<48> VDD! VSS! / RM_IHPSG13_1024x16_c2_2P_WLDRV16X4 +XA_WLDRV<2> a_wi<47> a_wi<46> a_wi<45> a_wi<44> a_wi<43> a_wi<42> a_wi<41> a_wi<40> a_wi<39> a_wi<38> a_wi<37> a_wi<36> a_wi<35> a_wi<34> a_wi<33> a_wi<32> a_wl_l<47> a_wl_l<46> a_wl_l<45> a_wl_l<44> a_wl_l<43> a_wl_l<42> a_wl_l<41> a_wl_l<40> a_wl_l<39> a_wl_l<38> a_wl_l<37> a_wl_l<36> a_wl_l<35> a_wl_l<34> a_wl_l<33> a_wl_l<32> VDD! VSS! / RM_IHPSG13_1024x16_c2_2P_WLDRV16X4 +XA_WLDRV<1> a_wi<31> a_wi<30> a_wi<29> a_wi<28> a_wi<27> a_wi<26> a_wi<25> a_wi<24> a_wi<23> a_wi<22> a_wi<21> a_wi<20> a_wi<19> a_wi<18> a_wi<17> a_wi<16> a_wl_l<31> a_wl_l<30> a_wl_l<29> a_wl_l<28> a_wl_l<27> a_wl_l<26> a_wl_l<25> a_wl_l<24> a_wl_l<23> a_wl_l<22> a_wl_l<21> a_wl_l<20> a_wl_l<19> a_wl_l<18> a_wl_l<17> a_wl_l<16> VDD! VSS! / RM_IHPSG13_1024x16_c2_2P_WLDRV16X4 +XA_WLDRV<0> a_wi<15> a_wi<14> a_wi<13> a_wi<12> a_wi<11> a_wi<10> a_wi<9> a_wi<8> a_wi<7> a_wi<6> a_wi<5> a_wi<4> a_wi<3> a_wi<2> a_wi<1> a_wi<0> a_wl_l<15> a_wl_l<14> a_wl_l<13> a_wl_l<12> a_wl_l<11> a_wl_l<10> a_wl_l<9> a_wl_l<8> a_wl_l<7> a_wl_l<6> a_wl_l<5> a_wl_l<4> a_wl_l<3> a_wl_l<2> a_wl_l<1> a_wl_l<0> VDD! VSS! / RM_IHPSG13_1024x16_c2_2P_WLDRV16X4 + + +XB_CTRL b_aclk_n B_BIST_CLK B_BIST_MEN B_BIST_EN B_BIST_REN B_BIST_WEN b_tiel B_CLK B_MEN b_dclk b_eclk b_pulse_h b_pulse_l b_pulse b_rclk B_REN b_cs b_wclk B_WEN VDD! VSS! / RM_IHPSG13_1024x16_c2_2P_CTRL +XA_CTRL a_aclk_n A_BIST_CLK A_BIST_MEN A_BIST_EN A_BIST_REN A_BIST_WEN a_tiel A_CLK A_MEN a_dclk a_eclk a_pulse_h a_pulse_l a_pulse a_rclk A_REN a_cs a_wclk A_WEN VDD! VSS! / RM_IHPSG13_1024x16_c2_2P_CTRL + + +XB_ROWDEC b_addr_row<7> b_addr_row<6> b_addr_row<5> b_addr_row<4> b_addr_row<3> b_addr_row<2> b_addr_row<1> b_addr_row<0> b_cs b_eclk b_wi<255> b_wi<254> b_wi<253> b_wi<252> b_wi<251> b_wi<250> b_wi<249> b_wi<248> b_wi<247> b_wi<246> b_wi<245> b_wi<244> b_wi<243> b_wi<242> b_wi<241> b_wi<240> b_wi<239> b_wi<238> b_wi<237> b_wi<236> b_wi<235> b_wi<234> b_wi<233> b_wi<232> b_wi<231> b_wi<230> b_wi<229> b_wi<228> b_wi<227> b_wi<226> b_wi<225> b_wi<224> b_wi<223> b_wi<222> b_wi<221> b_wi<220> b_wi<219> b_wi<218> b_wi<217> b_wi<216> b_wi<215> b_wi<214> b_wi<213> b_wi<212> b_wi<211> b_wi<210> b_wi<209> b_wi<208> b_wi<207> b_wi<206> b_wi<205> b_wi<204> b_wi<203> b_wi<202> b_wi<201> b_wi<200> b_wi<199> b_wi<198> b_wi<197> b_wi<196> b_wi<195> b_wi<194> b_wi<193> b_wi<192> b_wi<191> b_wi<190> b_wi<189> b_wi<188> b_wi<187> b_wi<186> b_wi<185> b_wi<184> b_wi<183> b_wi<182> b_wi<181> b_wi<180> b_wi<179> b_wi<178> b_wi<177> b_wi<176> b_wi<175> b_wi<174> b_wi<173> b_wi<172> b_wi<171> b_wi<170> b_wi<169> b_wi<168> b_wi<167> b_wi<166> b_wi<165> b_wi<164> b_wi<163> b_wi<162> b_wi<161> b_wi<160> b_wi<159> b_wi<158> b_wi<157> b_wi<156> b_wi<155> b_wi<154> b_wi<153> b_wi<152> b_wi<151> b_wi<150> b_wi<149> b_wi<148> b_wi<147> b_wi<146> b_wi<145> b_wi<144> b_wi<143> b_wi<142> b_wi<141> b_wi<140> b_wi<139> b_wi<138> b_wi<137> b_wi<136> b_wi<135> b_wi<134> b_wi<133> b_wi<132> b_wi<131> b_wi<130> b_wi<129> b_wi<128> b_wi<127> b_wi<126> b_wi<125> b_wi<124> b_wi<123> b_wi<122> b_wi<121> b_wi<120> b_wi<119> b_wi<118> b_wi<117> b_wi<116> b_wi<115> b_wi<114> b_wi<113> b_wi<112> b_wi<111> b_wi<110> b_wi<109> b_wi<108> b_wi<107> b_wi<106> b_wi<105> b_wi<104> b_wi<103> b_wi<102> b_wi<101> b_wi<100> b_wi<99> b_wi<98> b_wi<97> b_wi<96> b_wi<95> b_wi<94> b_wi<93> b_wi<92> b_wi<91> b_wi<90> b_wi<89> b_wi<88> b_wi<87> b_wi<86> b_wi<85> b_wi<84> b_wi<83> b_wi<82> b_wi<81> b_wi<80> b_wi<79> b_wi<78> b_wi<77> b_wi<76> b_wi<75> b_wi<74> b_wi<73> b_wi<72> b_wi<71> b_wi<70> b_wi<69> b_wi<68> b_wi<67> b_wi<66> b_wi<65> b_wi<64> b_wi<63> b_wi<62> b_wi<61> b_wi<60> b_wi<59> b_wi<58> b_wi<57> b_wi<56> b_wi<55> b_wi<54> b_wi<53> b_wi<52> b_wi<51> b_wi<50> b_wi<49> b_wi<48> b_wi<47> b_wi<46> b_wi<45> b_wi<44> b_wi<43> b_wi<42> b_wi<41> b_wi<40> b_wi<39> b_wi<38> b_wi<37> b_wi<36> b_wi<35> b_wi<34> b_wi<33> b_wi<32> b_wi<31> b_wi<30> b_wi<29> b_wi<28> b_wi<27> b_wi<26> b_wi<25> b_wi<24> b_wi<23> b_wi<22> b_wi<21> b_wi<20> b_wi<19> b_wi<18> b_wi<17> b_wi<16> b_wi<15> b_wi<14> b_wi<13> b_wi<12> b_wi<11> b_wi<10> b_wi<9> b_wi<8> b_wi<7> b_wi<6> b_wi<5> b_wi<4> b_wi<3> b_wi<2> b_wi<1> b_wi<0> VDD! VSS! / RM_IHPSG13_1024x16_c2_2P_ROWDEC8 +XA_ROWDEC a_addr_row<7> a_addr_row<6> a_addr_row<5> a_addr_row<4> a_addr_row<3> a_addr_row<2> a_addr_row<1> a_addr_row<0> a_cs a_eclk a_wi<255> a_wi<254> a_wi<253> a_wi<252> a_wi<251> a_wi<250> a_wi<249> a_wi<248> a_wi<247> a_wi<246> a_wi<245> a_wi<244> a_wi<243> a_wi<242> a_wi<241> a_wi<240> a_wi<239> a_wi<238> a_wi<237> a_wi<236> a_wi<235> a_wi<234> a_wi<233> a_wi<232> a_wi<231> a_wi<230> a_wi<229> a_wi<228> a_wi<227> a_wi<226> a_wi<225> a_wi<224> a_wi<223> a_wi<222> a_wi<221> a_wi<220> a_wi<219> a_wi<218> a_wi<217> a_wi<216> a_wi<215> a_wi<214> a_wi<213> a_wi<212> a_wi<211> a_wi<210> a_wi<209> a_wi<208> a_wi<207> a_wi<206> a_wi<205> a_wi<204> a_wi<203> a_wi<202> a_wi<201> a_wi<200> a_wi<199> a_wi<198> a_wi<197> a_wi<196> a_wi<195> a_wi<194> a_wi<193> a_wi<192> a_wi<191> a_wi<190> a_wi<189> a_wi<188> a_wi<187> a_wi<186> a_wi<185> a_wi<184> a_wi<183> a_wi<182> a_wi<181> a_wi<180> a_wi<179> a_wi<178> a_wi<177> a_wi<176> a_wi<175> a_wi<174> a_wi<173> a_wi<172> a_wi<171> a_wi<170> a_wi<169> a_wi<168> a_wi<167> a_wi<166> a_wi<165> a_wi<164> a_wi<163> a_wi<162> a_wi<161> a_wi<160> a_wi<159> a_wi<158> a_wi<157> a_wi<156> a_wi<155> a_wi<154> a_wi<153> a_wi<152> a_wi<151> a_wi<150> a_wi<149> a_wi<148> a_wi<147> a_wi<146> a_wi<145> a_wi<144> a_wi<143> a_wi<142> a_wi<141> a_wi<140> a_wi<139> a_wi<138> a_wi<137> a_wi<136> a_wi<135> a_wi<134> a_wi<133> a_wi<132> a_wi<131> a_wi<130> a_wi<129> a_wi<128> a_wi<127> a_wi<126> a_wi<125> a_wi<124> a_wi<123> a_wi<122> a_wi<121> a_wi<120> a_wi<119> a_wi<118> a_wi<117> a_wi<116> a_wi<115> a_wi<114> a_wi<113> a_wi<112> a_wi<111> a_wi<110> a_wi<109> a_wi<108> a_wi<107> a_wi<106> a_wi<105> a_wi<104> a_wi<103> a_wi<102> a_wi<101> a_wi<100> a_wi<99> a_wi<98> a_wi<97> a_wi<96> a_wi<95> a_wi<94> a_wi<93> a_wi<92> a_wi<91> a_wi<90> a_wi<89> a_wi<88> a_wi<87> a_wi<86> a_wi<85> a_wi<84> a_wi<83> a_wi<82> a_wi<81> a_wi<80> a_wi<79> a_wi<78> a_wi<77> a_wi<76> a_wi<75> a_wi<74> a_wi<73> a_wi<72> a_wi<71> a_wi<70> a_wi<69> a_wi<68> a_wi<67> a_wi<66> a_wi<65> a_wi<64> a_wi<63> a_wi<62> a_wi<61> a_wi<60> a_wi<59> a_wi<58> a_wi<57> a_wi<56> a_wi<55> a_wi<54> a_wi<53> a_wi<52> a_wi<51> a_wi<50> a_wi<49> a_wi<48> a_wi<47> a_wi<46> a_wi<45> a_wi<44> a_wi<43> a_wi<42> a_wi<41> a_wi<40> a_wi<39> a_wi<38> a_wi<37> a_wi<36> a_wi<35> a_wi<34> a_wi<33> a_wi<32> a_wi<31> a_wi<30> a_wi<29> a_wi<28> a_wi<27> a_wi<26> a_wi<25> a_wi<24> a_wi<23> a_wi<22> a_wi<21> a_wi<20> a_wi<19> a_wi<18> a_wi<17> a_wi<16> a_wi<15> a_wi<14> a_wi<13> a_wi<12> a_wi<11> a_wi<10> a_wi<9> a_wi<8> a_wi<7> a_wi<6> a_wi<5> a_wi<4> a_wi<3> a_wi<2> a_wi<1> a_wi<0> VDD! VSS! / RM_IHPSG13_1024x16_c2_2P_ROWDEC8 +XB_ROWREG b_aclk_n B_ADDR<9> B_ADDR<8> B_ADDR<7> B_ADDR<6> B_ADDR<5> B_ADDR<4> B_ADDR<3> B_ADDR<2> b_addr_row<7> b_addr_row<6> b_addr_row<5> b_addr_row<4> b_addr_row<3> b_addr_row<2> b_addr_row<1> b_addr_row<0> B_BIST_ADDR<9> B_BIST_ADDR<8> B_BIST_ADDR<7> B_BIST_ADDR<6> B_BIST_ADDR<5> B_BIST_ADDR<4> B_BIST_ADDR<3> B_BIST_ADDR<2> B_BIST_EN VDD! VSS! / RM_IHPSG13_1024x16_c2_2P_ROWREG8 +XA_ROWREG a_aclk_n A_ADDR<9> A_ADDR<8> A_ADDR<7> A_ADDR<6> A_ADDR<5> A_ADDR<4> A_ADDR<3> A_ADDR<2> a_addr_row<7> a_addr_row<6> a_addr_row<5> a_addr_row<4> a_addr_row<3> a_addr_row<2> a_addr_row<1> a_addr_row<0> A_BIST_ADDR<9> A_BIST_ADDR<8> A_BIST_ADDR<7> A_BIST_ADDR<6> A_BIST_ADDR<5> A_BIST_ADDR<4> A_BIST_ADDR<3> A_BIST_ADDR<2> A_BIST_EN VDD! VSS! / RM_IHPSG13_1024x16_c2_2P_ROWREG8 +XB_COLDEC b_aclk_n B_ADDR<1> B_ADDR<0> b_addr_col<1> b_addr_col<0> b_addr_dec<7> b_addr_dec<6> b_addr_dec<5> b_addr_dec<4> b_addr_dec<3> b_addr_dec<2> b_addr_dec<1> b_addr_dec<0> B_BIST_ADDR<1> B_BIST_ADDR<0> B_BIST_EN VDD! VSS! / RM_IHPSG13_1024x16_c2_2P_COLDEC2 +XA_COLDEC a_aclk_n A_ADDR<1> A_ADDR<0> a_addr_col<1> a_addr_col<0> a_addr_dec<7> a_addr_dec<6> a_addr_dec<5> a_addr_dec<4> a_addr_dec<3> a_addr_dec<2> a_addr_dec<1> a_addr_dec<0> A_BIST_ADDR<1> A_BIST_ADDR<0> A_BIST_EN VDD! VSS! / RM_IHPSG13_1024x16_c2_2P_COLDEC2 + + +XB_DLYH b_pulse b_pulse_h VDD! VSS! / RM_IHPSG13_1024x16_c2_2P_DLY_pcell_2 +XB_DLYL b_pulse_x b_pulse_l VDD! VSS! / RM_IHPSG13_1024x16_c2_2P_DLY_pcell_3 +XA_DLYH a_pulse a_pulse_h VDD! VSS! / RM_IHPSG13_1024x16_c2_2P_DLY_pcell_2 +XA_DLYL a_pulse_x a_pulse_l VDD! VSS! / RM_IHPSG13_1024x16_c2_2P_DLY_pcell_3 +XB_DLYMUX b_pulse_h B_DLY b_pulse_x VDD! VSS! / RM_IHPSG13_1024x16_c2_2P_DLY_MUX +XA_DLYMUX a_pulse_h A_DLY a_pulse_x VDD! VSS! / RM_IHPSG13_1024x16_c2_2P_DLY_MUX + +XCOLCTRL<15> a_addr_dec_r<3> a_addr_dec_r<2> a_addr_dec_r<1> a_addr_dec_r<0> A_BIST_BM<15> A_BIST_DIN<15> A_BIST_EN a_blc_r<31> a_blc_r<30> a_blc_r<29> a_blc_r<28> a_blt_r<31> a_blt_r<30> a_blt_r<29> a_blt_r<28> A_BM<15> a_dclk_n_r<7> a_dclk_n_r<8> a_dclk_p_r<7> a_dclk_p_r<8> A_DOUT<15> A_DIN<15> a_rclk_n_r<7> a_rclk_n_r<8> a_rclk_p_r<7> a_rclk_p_r<8> a_tieh<15> a_wclk_n_r<7> a_wclk_n_r<8> a_wclk_p_r<7> a_wclk_p_r<8> b_addr_dec_r<3> b_addr_dec_r<2> b_addr_dec_r<1> b_addr_dec_r<0> B_BIST_BM<15> B_BIST_DIN<15> B_BIST_EN b_blc_r<31> b_blc_r<30> b_blc_r<29> b_blc_r<28> b_blt_r<31> b_blt_r<30> b_blt_r<29> b_blt_r<28> B_BM<15> b_dclk_n_r<7> b_dclk_n_r<8> b_dclk_p_r<7> b_dclk_p_r<8> B_DOUT<15> B_DIN<15> b_rclk_n_r<7> b_rclk_n_r<8> b_rclk_p_r<7> b_rclk_p_r<8> b_tieh<15> b_wclk_n_r<7> b_wclk_n_r<8> b_wclk_p_r<7> b_wclk_p_r<8> VDD! VSS! / RM_IHPSG13_1024x16_c2_2P_COLCTRL2 +XCOLCTRL<14> a_addr_dec_r<3> a_addr_dec_r<2> a_addr_dec_r<1> a_addr_dec_r<0> A_BIST_BM<14> A_BIST_DIN<14> A_BIST_EN a_blc_r<27> a_blc_r<26> a_blc_r<25> a_blc_r<24> a_blt_r<27> a_blt_r<26> a_blt_r<25> a_blt_r<24> A_BM<14> a_dclk_n_r<6> a_dclk_n_r<7> a_dclk_p_r<6> a_dclk_p_r<7> A_DOUT<14> A_DIN<14> a_rclk_n_r<6> a_rclk_n_r<7> a_rclk_p_r<6> a_rclk_p_r<7> a_tieh<14> a_wclk_n_r<6> a_wclk_n_r<7> a_wclk_p_r<6> a_wclk_p_r<7> b_addr_dec_r<3> b_addr_dec_r<2> b_addr_dec_r<1> b_addr_dec_r<0> B_BIST_BM<14> B_BIST_DIN<14> B_BIST_EN b_blc_r<27> b_blc_r<26> b_blc_r<25> b_blc_r<24> b_blt_r<27> b_blt_r<26> b_blt_r<25> b_blt_r<24> B_BM<14> b_dclk_n_r<6> b_dclk_n_r<7> b_dclk_p_r<6> b_dclk_p_r<7> B_DOUT<14> B_DIN<14> b_rclk_n_r<6> b_rclk_n_r<7> b_rclk_p_r<6> b_rclk_p_r<7> b_tieh<14> b_wclk_n_r<6> b_wclk_n_r<7> b_wclk_p_r<6> b_wclk_p_r<7> VDD! VSS! / RM_IHPSG13_1024x16_c2_2P_COLCTRL2 +XCOLCTRL<13> a_addr_dec_r<3> a_addr_dec_r<2> a_addr_dec_r<1> a_addr_dec_r<0> A_BIST_BM<13> A_BIST_DIN<13> A_BIST_EN a_blc_r<23> a_blc_r<22> a_blc_r<21> a_blc_r<20> a_blt_r<23> a_blt_r<22> a_blt_r<21> a_blt_r<20> A_BM<13> a_dclk_n_r<5> a_dclk_n_r<6> a_dclk_p_r<5> a_dclk_p_r<6> A_DOUT<13> A_DIN<13> a_rclk_n_r<5> a_rclk_n_r<6> a_rclk_p_r<5> a_rclk_p_r<6> a_tieh<13> a_wclk_n_r<5> a_wclk_n_r<6> a_wclk_p_r<5> a_wclk_p_r<6> b_addr_dec_r<3> b_addr_dec_r<2> b_addr_dec_r<1> b_addr_dec_r<0> B_BIST_BM<13> B_BIST_DIN<13> B_BIST_EN b_blc_r<23> b_blc_r<22> b_blc_r<21> b_blc_r<20> b_blt_r<23> b_blt_r<22> b_blt_r<21> b_blt_r<20> B_BM<13> b_dclk_n_r<5> b_dclk_n_r<6> b_dclk_p_r<5> b_dclk_p_r<6> B_DOUT<13> B_DIN<13> b_rclk_n_r<5> b_rclk_n_r<6> b_rclk_p_r<5> b_rclk_p_r<6> b_tieh<13> b_wclk_n_r<5> b_wclk_n_r<6> b_wclk_p_r<5> b_wclk_p_r<6> VDD! VSS! / RM_IHPSG13_1024x16_c2_2P_COLCTRL2 +XCOLCTRL<12> a_addr_dec_r<3> a_addr_dec_r<2> a_addr_dec_r<1> a_addr_dec_r<0> A_BIST_BM<12> A_BIST_DIN<12> A_BIST_EN a_blc_r<19> a_blc_r<18> a_blc_r<17> a_blc_r<16> a_blt_r<19> a_blt_r<18> a_blt_r<17> a_blt_r<16> A_BM<12> a_dclk_n_r<4> a_dclk_n_r<5> a_dclk_p_r<4> a_dclk_p_r<5> A_DOUT<12> A_DIN<12> a_rclk_n_r<4> a_rclk_n_r<5> a_rclk_p_r<4> a_rclk_p_r<5> a_tieh<12> a_wclk_n_r<4> a_wclk_n_r<5> a_wclk_p_r<4> a_wclk_p_r<5> b_addr_dec_r<3> b_addr_dec_r<2> b_addr_dec_r<1> b_addr_dec_r<0> B_BIST_BM<12> B_BIST_DIN<12> B_BIST_EN b_blc_r<19> b_blc_r<18> b_blc_r<17> b_blc_r<16> b_blt_r<19> b_blt_r<18> b_blt_r<17> b_blt_r<16> B_BM<12> b_dclk_n_r<4> b_dclk_n_r<5> b_dclk_p_r<4> b_dclk_p_r<5> B_DOUT<12> B_DIN<12> b_rclk_n_r<4> b_rclk_n_r<5> b_rclk_p_r<4> b_rclk_p_r<5> b_tieh<12> b_wclk_n_r<4> b_wclk_n_r<5> b_wclk_p_r<4> b_wclk_p_r<5> VDD! VSS! / RM_IHPSG13_1024x16_c2_2P_COLCTRL2 +XCOLCTRL<11> a_addr_dec_r<3> a_addr_dec_r<2> a_addr_dec_r<1> a_addr_dec_r<0> A_BIST_BM<11> A_BIST_DIN<11> A_BIST_EN a_blc_r<15> a_blc_r<14> a_blc_r<13> a_blc_r<12> a_blt_r<15> a_blt_r<14> a_blt_r<13> a_blt_r<12> A_BM<11> a_dclk_n_r<3> a_dclk_n_r<4> a_dclk_p_r<3> a_dclk_p_r<4> A_DOUT<11> A_DIN<11> a_rclk_n_r<3> a_rclk_n_r<4> a_rclk_p_r<3> a_rclk_p_r<4> a_tieh<11> a_wclk_n_r<3> a_wclk_n_r<4> a_wclk_p_r<3> a_wclk_p_r<4> b_addr_dec_r<3> b_addr_dec_r<2> b_addr_dec_r<1> b_addr_dec_r<0> B_BIST_BM<11> B_BIST_DIN<11> B_BIST_EN b_blc_r<15> b_blc_r<14> b_blc_r<13> b_blc_r<12> b_blt_r<15> b_blt_r<14> b_blt_r<13> b_blt_r<12> B_BM<11> b_dclk_n_r<3> b_dclk_n_r<4> b_dclk_p_r<3> b_dclk_p_r<4> B_DOUT<11> B_DIN<11> b_rclk_n_r<3> b_rclk_n_r<4> b_rclk_p_r<3> b_rclk_p_r<4> b_tieh<11> b_wclk_n_r<3> b_wclk_n_r<4> b_wclk_p_r<3> b_wclk_p_r<4> VDD! VSS! / RM_IHPSG13_1024x16_c2_2P_COLCTRL2 +XCOLCTRL<10> a_addr_dec_r<3> a_addr_dec_r<2> a_addr_dec_r<1> a_addr_dec_r<0> A_BIST_BM<10> A_BIST_DIN<10> A_BIST_EN a_blc_r<11> a_blc_r<10> a_blc_r<9> a_blc_r<8> a_blt_r<11> a_blt_r<10> a_blt_r<9> a_blt_r<8> A_BM<10> a_dclk_n_r<2> a_dclk_n_r<3> a_dclk_p_r<2> a_dclk_p_r<3> A_DOUT<10> A_DIN<10> a_rclk_n_r<2> a_rclk_n_r<3> a_rclk_p_r<2> a_rclk_p_r<3> a_tieh<10> a_wclk_n_r<2> a_wclk_n_r<3> a_wclk_p_r<2> a_wclk_p_r<3> b_addr_dec_r<3> b_addr_dec_r<2> b_addr_dec_r<1> b_addr_dec_r<0> B_BIST_BM<10> B_BIST_DIN<10> B_BIST_EN b_blc_r<11> b_blc_r<10> b_blc_r<9> b_blc_r<8> b_blt_r<11> b_blt_r<10> b_blt_r<9> b_blt_r<8> B_BM<10> b_dclk_n_r<2> b_dclk_n_r<3> b_dclk_p_r<2> b_dclk_p_r<3> B_DOUT<10> B_DIN<10> b_rclk_n_r<2> b_rclk_n_r<3> b_rclk_p_r<2> b_rclk_p_r<3> b_tieh<10> b_wclk_n_r<2> b_wclk_n_r<3> b_wclk_p_r<2> b_wclk_p_r<3> VDD! VSS! / RM_IHPSG13_1024x16_c2_2P_COLCTRL2 +XCOLCTRL<9> a_addr_dec_r<3> a_addr_dec_r<2> a_addr_dec_r<1> a_addr_dec_r<0> A_BIST_BM<9> A_BIST_DIN<9> A_BIST_EN a_blc_r<7> a_blc_r<6> a_blc_r<5> a_blc_r<4> a_blt_r<7> a_blt_r<6> a_blt_r<5> a_blt_r<4> A_BM<9> a_dclk_n_r<1> a_dclk_n_r<2> a_dclk_p_r<1> a_dclk_p_r<2> A_DOUT<9> A_DIN<9> a_rclk_n_r<1> a_rclk_n_r<2> a_rclk_p_r<1> a_rclk_p_r<2> a_tieh<9> a_wclk_n_r<1> a_wclk_n_r<2> a_wclk_p_r<1> a_wclk_p_r<2> b_addr_dec_r<3> b_addr_dec_r<2> b_addr_dec_r<1> b_addr_dec_r<0> B_BIST_BM<9> B_BIST_DIN<9> B_BIST_EN b_blc_r<7> b_blc_r<6> b_blc_r<5> b_blc_r<4> b_blt_r<7> b_blt_r<6> b_blt_r<5> b_blt_r<4> B_BM<9> b_dclk_n_r<1> b_dclk_n_r<2> b_dclk_p_r<1> b_dclk_p_r<2> B_DOUT<9> B_DIN<9> b_rclk_n_r<1> b_rclk_n_r<2> b_rclk_p_r<1> b_rclk_p_r<2> b_tieh<9> b_wclk_n_r<1> b_wclk_n_r<2> b_wclk_p_r<1> b_wclk_p_r<2> VDD! VSS! / RM_IHPSG13_1024x16_c2_2P_COLCTRL2 +XCOLCTRL<8> a_addr_dec_r<3> a_addr_dec_r<2> a_addr_dec_r<1> a_addr_dec_r<0> A_BIST_BM<8> A_BIST_DIN<8> A_BIST_EN a_blc_r<3> a_blc_r<2> a_blc_r<1> a_blc_r<0> a_blt_r<3> a_blt_r<2> a_blt_r<1> a_blt_r<0> A_BM<8> a_dclk_n_r<0> a_dclk_n_r<1> a_dclk_p_r<0> a_dclk_p_r<1> A_DOUT<8> A_DIN<8> a_rclk_n_r<0> a_rclk_n_r<1> a_rclk_p_r<0> a_rclk_p_r<1> a_tieh<8> a_wclk_n_r<0> a_wclk_n_r<1> a_wclk_p_r<0> a_wclk_p_r<1> b_addr_dec_r<3> b_addr_dec_r<2> b_addr_dec_r<1> b_addr_dec_r<0> B_BIST_BM<8> B_BIST_DIN<8> B_BIST_EN b_blc_r<3> b_blc_r<2> b_blc_r<1> b_blc_r<0> b_blt_r<3> b_blt_r<2> b_blt_r<1> b_blt_r<0> B_BM<8> b_dclk_n_r<0> b_dclk_n_r<1> b_dclk_p_r<0> b_dclk_p_r<1> B_DOUT<8> B_DIN<8> b_rclk_n_r<0> b_rclk_n_r<1> b_rclk_p_r<0> b_rclk_p_r<1> b_tieh<8> b_wclk_n_r<0> b_wclk_n_r<1> b_wclk_p_r<0> b_wclk_p_r<1> VDD! VSS! / RM_IHPSG13_1024x16_c2_2P_COLCTRL2 +XCOLCTRL<7> a_addr_dec_l<3> a_addr_dec_l<2> a_addr_dec_l<1> a_addr_dec_l<0> A_BIST_BM<0> A_BIST_DIN<0> A_BIST_EN a_blc_l<31> a_blc_l<30> a_blc_l<29> a_blc_l<28> a_blt_l<31> a_blt_l<30> a_blt_l<29> a_blt_l<28> A_BM<0> a_dclk_n_l<7> a_dclk_n_l<8> a_dclk_p_l<7> a_dclk_p_l<8> A_DOUT<0> A_DIN<0> a_rclk_n_l<7> a_rclk_n_l<8> a_rclk_p_l<7> a_rclk_p_l<8> a_tieh<0> a_wclk_n_l<7> a_wclk_n_l<8> a_wclk_p_l<7> a_wclk_p_l<8> b_addr_dec_l<3> b_addr_dec_l<2> b_addr_dec_l<1> b_addr_dec_l<0> B_BIST_BM<0> B_BIST_DIN<0> B_BIST_EN b_blc_l<31> b_blc_l<30> b_blc_l<29> b_blc_l<28> b_blt_l<31> b_blt_l<30> b_blt_l<29> b_blt_l<28> B_BM<0> b_dclk_n_l<7> b_dclk_n_l<8> b_dclk_p_l<7> b_dclk_p_l<8> B_DOUT<0> B_DIN<0> b_rclk_n_l<7> b_rclk_n_l<8> b_rclk_p_l<7> b_rclk_p_l<8> b_tieh<0> b_wclk_n_l<7> b_wclk_n_l<8> b_wclk_p_l<7> b_wclk_p_l<8> VDD! VSS! / RM_IHPSG13_1024x16_c2_2P_COLCTRL2 +XCOLCTRL<6> a_addr_dec_l<3> a_addr_dec_l<2> a_addr_dec_l<1> a_addr_dec_l<0> A_BIST_BM<1> A_BIST_DIN<1> A_BIST_EN a_blc_l<27> a_blc_l<26> a_blc_l<25> a_blc_l<24> a_blt_l<27> a_blt_l<26> a_blt_l<25> a_blt_l<24> A_BM<1> a_dclk_n_l<6> a_dclk_n_l<7> a_dclk_p_l<6> a_dclk_p_l<7> A_DOUT<1> A_DIN<1> a_rclk_n_l<6> a_rclk_n_l<7> a_rclk_p_l<6> a_rclk_p_l<7> a_tieh<1> a_wclk_n_l<6> a_wclk_n_l<7> a_wclk_p_l<6> a_wclk_p_l<7> b_addr_dec_l<3> b_addr_dec_l<2> b_addr_dec_l<1> b_addr_dec_l<0> B_BIST_BM<1> B_BIST_DIN<1> B_BIST_EN b_blc_l<27> b_blc_l<26> b_blc_l<25> b_blc_l<24> b_blt_l<27> b_blt_l<26> b_blt_l<25> b_blt_l<24> B_BM<1> b_dclk_n_l<6> b_dclk_n_l<7> b_dclk_p_l<6> b_dclk_p_l<7> B_DOUT<1> B_DIN<1> b_rclk_n_l<6> b_rclk_n_l<7> b_rclk_p_l<6> b_rclk_p_l<7> b_tieh<1> b_wclk_n_l<6> b_wclk_n_l<7> b_wclk_p_l<6> b_wclk_p_l<7> VDD! VSS! / RM_IHPSG13_1024x16_c2_2P_COLCTRL2 +XCOLCTRL<5> a_addr_dec_l<3> a_addr_dec_l<2> a_addr_dec_l<1> a_addr_dec_l<0> A_BIST_BM<2> A_BIST_DIN<2> A_BIST_EN a_blc_l<23> a_blc_l<22> a_blc_l<21> a_blc_l<20> a_blt_l<23> a_blt_l<22> a_blt_l<21> a_blt_l<20> A_BM<2> a_dclk_n_l<5> a_dclk_n_l<6> a_dclk_p_l<5> a_dclk_p_l<6> A_DOUT<2> A_DIN<2> a_rclk_n_l<5> a_rclk_n_l<6> a_rclk_p_l<5> a_rclk_p_l<6> a_tieh<2> a_wclk_n_l<5> a_wclk_n_l<6> a_wclk_p_l<5> a_wclk_p_l<6> b_addr_dec_l<3> b_addr_dec_l<2> b_addr_dec_l<1> b_addr_dec_l<0> B_BIST_BM<2> B_BIST_DIN<2> B_BIST_EN b_blc_l<23> b_blc_l<22> b_blc_l<21> b_blc_l<20> b_blt_l<23> b_blt_l<22> b_blt_l<21> b_blt_l<20> B_BM<2> b_dclk_n_l<5> b_dclk_n_l<6> b_dclk_p_l<5> b_dclk_p_l<6> B_DOUT<2> B_DIN<2> b_rclk_n_l<5> b_rclk_n_l<6> b_rclk_p_l<5> b_rclk_p_l<6> b_tieh<2> b_wclk_n_l<5> b_wclk_n_l<6> b_wclk_p_l<5> b_wclk_p_l<6> VDD! VSS! / RM_IHPSG13_1024x16_c2_2P_COLCTRL2 +XCOLCTRL<4> a_addr_dec_l<3> a_addr_dec_l<2> a_addr_dec_l<1> a_addr_dec_l<0> A_BIST_BM<3> A_BIST_DIN<3> A_BIST_EN a_blc_l<19> a_blc_l<18> a_blc_l<17> a_blc_l<16> a_blt_l<19> a_blt_l<18> a_blt_l<17> a_blt_l<16> A_BM<3> a_dclk_n_l<4> a_dclk_n_l<5> a_dclk_p_l<4> a_dclk_p_l<5> A_DOUT<3> A_DIN<3> a_rclk_n_l<4> a_rclk_n_l<5> a_rclk_p_l<4> a_rclk_p_l<5> a_tieh<3> a_wclk_n_l<4> a_wclk_n_l<5> a_wclk_p_l<4> a_wclk_p_l<5> b_addr_dec_l<3> b_addr_dec_l<2> b_addr_dec_l<1> b_addr_dec_l<0> B_BIST_BM<3> B_BIST_DIN<3> B_BIST_EN b_blc_l<19> b_blc_l<18> b_blc_l<17> b_blc_l<16> b_blt_l<19> b_blt_l<18> b_blt_l<17> b_blt_l<16> B_BM<3> b_dclk_n_l<4> b_dclk_n_l<5> b_dclk_p_l<4> b_dclk_p_l<5> B_DOUT<3> B_DIN<3> b_rclk_n_l<4> b_rclk_n_l<5> b_rclk_p_l<4> b_rclk_p_l<5> b_tieh<3> b_wclk_n_l<4> b_wclk_n_l<5> b_wclk_p_l<4> b_wclk_p_l<5> VDD! VSS! / RM_IHPSG13_1024x16_c2_2P_COLCTRL2 +XCOLCTRL<3> a_addr_dec_l<3> a_addr_dec_l<2> a_addr_dec_l<1> a_addr_dec_l<0> A_BIST_BM<4> A_BIST_DIN<4> A_BIST_EN a_blc_l<15> a_blc_l<14> a_blc_l<13> a_blc_l<12> a_blt_l<15> a_blt_l<14> a_blt_l<13> a_blt_l<12> A_BM<4> a_dclk_n_l<3> a_dclk_n_l<4> a_dclk_p_l<3> a_dclk_p_l<4> A_DOUT<4> A_DIN<4> a_rclk_n_l<3> a_rclk_n_l<4> a_rclk_p_l<3> a_rclk_p_l<4> a_tieh<4> a_wclk_n_l<3> a_wclk_n_l<4> a_wclk_p_l<3> a_wclk_p_l<4> b_addr_dec_l<3> b_addr_dec_l<2> b_addr_dec_l<1> b_addr_dec_l<0> B_BIST_BM<4> B_BIST_DIN<4> B_BIST_EN b_blc_l<15> b_blc_l<14> b_blc_l<13> b_blc_l<12> b_blt_l<15> b_blt_l<14> b_blt_l<13> b_blt_l<12> B_BM<4> b_dclk_n_l<3> b_dclk_n_l<4> b_dclk_p_l<3> b_dclk_p_l<4> B_DOUT<4> B_DIN<4> b_rclk_n_l<3> b_rclk_n_l<4> b_rclk_p_l<3> b_rclk_p_l<4> b_tieh<4> b_wclk_n_l<3> b_wclk_n_l<4> b_wclk_p_l<3> b_wclk_p_l<4> VDD! VSS! / RM_IHPSG13_1024x16_c2_2P_COLCTRL2 +XCOLCTRL<2> a_addr_dec_l<3> a_addr_dec_l<2> a_addr_dec_l<1> a_addr_dec_l<0> A_BIST_BM<5> A_BIST_DIN<5> A_BIST_EN a_blc_l<11> a_blc_l<10> a_blc_l<9> a_blc_l<8> a_blt_l<11> a_blt_l<10> a_blt_l<9> a_blt_l<8> A_BM<5> a_dclk_n_l<2> a_dclk_n_l<3> a_dclk_p_l<2> a_dclk_p_l<3> A_DOUT<5> A_DIN<5> a_rclk_n_l<2> a_rclk_n_l<3> a_rclk_p_l<2> a_rclk_p_l<3> a_tieh<5> a_wclk_n_l<2> a_wclk_n_l<3> a_wclk_p_l<2> a_wclk_p_l<3> b_addr_dec_l<3> b_addr_dec_l<2> b_addr_dec_l<1> b_addr_dec_l<0> B_BIST_BM<5> B_BIST_DIN<5> B_BIST_EN b_blc_l<11> b_blc_l<10> b_blc_l<9> b_blc_l<8> b_blt_l<11> b_blt_l<10> b_blt_l<9> b_blt_l<8> B_BM<5> b_dclk_n_l<2> b_dclk_n_l<3> b_dclk_p_l<2> b_dclk_p_l<3> B_DOUT<5> B_DIN<5> b_rclk_n_l<2> b_rclk_n_l<3> b_rclk_p_l<2> b_rclk_p_l<3> b_tieh<5> b_wclk_n_l<2> b_wclk_n_l<3> b_wclk_p_l<2> b_wclk_p_l<3> VDD! VSS! / RM_IHPSG13_1024x16_c2_2P_COLCTRL2 +XCOLCTRL<1> a_addr_dec_l<3> a_addr_dec_l<2> a_addr_dec_l<1> a_addr_dec_l<0> A_BIST_BM<6> A_BIST_DIN<6> A_BIST_EN a_blc_l<7> a_blc_l<6> a_blc_l<5> a_blc_l<4> a_blt_l<7> a_blt_l<6> a_blt_l<5> a_blt_l<4> A_BM<6> a_dclk_n_l<1> a_dclk_n_l<2> a_dclk_p_l<1> a_dclk_p_l<2> A_DOUT<6> A_DIN<6> a_rclk_n_l<1> a_rclk_n_l<2> a_rclk_p_l<1> a_rclk_p_l<2> a_tieh<6> a_wclk_n_l<1> a_wclk_n_l<2> a_wclk_p_l<1> a_wclk_p_l<2> b_addr_dec_l<3> b_addr_dec_l<2> b_addr_dec_l<1> b_addr_dec_l<0> B_BIST_BM<6> B_BIST_DIN<6> B_BIST_EN b_blc_l<7> b_blc_l<6> b_blc_l<5> b_blc_l<4> b_blt_l<7> b_blt_l<6> b_blt_l<5> b_blt_l<4> B_BM<6> b_dclk_n_l<1> b_dclk_n_l<2> b_dclk_p_l<1> b_dclk_p_l<2> B_DOUT<6> B_DIN<6> b_rclk_n_l<1> b_rclk_n_l<2> b_rclk_p_l<1> b_rclk_p_l<2> b_tieh<6> b_wclk_n_l<1> b_wclk_n_l<2> b_wclk_p_l<1> b_wclk_p_l<2> VDD! VSS! / RM_IHPSG13_1024x16_c2_2P_COLCTRL2 +XCOLCTRL<0> a_addr_dec_l<3> a_addr_dec_l<2> a_addr_dec_l<1> a_addr_dec_l<0> A_BIST_BM<7> A_BIST_DIN<7> A_BIST_EN a_blc_l<3> a_blc_l<2> a_blc_l<1> a_blc_l<0> a_blt_l<3> a_blt_l<2> a_blt_l<1> a_blt_l<0> A_BM<7> a_dclk_n_l<0> a_dclk_n_l<1> a_dclk_p_l<0> a_dclk_p_l<1> A_DOUT<7> A_DIN<7> a_rclk_n_l<0> a_rclk_n_l<1> a_rclk_p_l<0> a_rclk_p_l<1> a_tieh<7> a_wclk_n_l<0> a_wclk_n_l<1> a_wclk_p_l<0> a_wclk_p_l<1> b_addr_dec_l<3> b_addr_dec_l<2> b_addr_dec_l<1> b_addr_dec_l<0> B_BIST_BM<7> B_BIST_DIN<7> B_BIST_EN b_blc_l<3> b_blc_l<2> b_blc_l<1> b_blc_l<0> b_blt_l<3> b_blt_l<2> b_blt_l<1> b_blt_l<0> B_BM<7> b_dclk_n_l<0> b_dclk_n_l<1> b_dclk_p_l<0> b_dclk_p_l<1> B_DOUT<7> B_DIN<7> b_rclk_n_l<0> b_rclk_n_l<1> b_rclk_p_l<0> b_rclk_p_l<1> b_tieh<7> b_wclk_n_l<0> b_wclk_n_l<1> b_wclk_p_l<0> b_wclk_p_l<1> VDD! VSS! / RM_IHPSG13_1024x16_c2_2P_COLCTRL2 + + +XDRVFILL4<1> VDD! VSS! / RM_IHPSG13_1024x16_c2_2P_COLDRV13_FILL4 +XDRVFILL4<2> VDD! VSS! / RM_IHPSG13_1024x16_c2_2P_COLDRV13_FILL4 +XDRVFILL4<3> VDD! VSS! / RM_IHPSG13_1024x16_c2_2P_COLDRV13_FILL4 +XDRVFILL4<4> VDD! VSS! / RM_IHPSG13_1024x16_c2_2P_COLDRV13_FILL4 +XDRVFILL4<5> VDD! VSS! / RM_IHPSG13_1024x16_c2_2P_COLDRV13_FILL4 +XDRVFILL4<6> VDD! VSS! / RM_IHPSG13_1024x16_c2_2P_COLDRV13_FILL4 +XCOLFILL4<1> VDD! VSS! / RM_IHPSG13_1024x16_c2_2P_COLDRV13_FILL4C2 +XCOLFILL4<2> VDD! VSS! / RM_IHPSG13_1024x16_c2_2P_COLDRV13_FILL4C2 +XCOLFILL4<3> VDD! VSS! / RM_IHPSG13_1024x16_c2_2P_COLDRV13_FILL4C2 +XCOLFILL4<4> VDD! VSS! / RM_IHPSG13_1024x16_c2_2P_COLDRV13_FILL4C2 +XCOLFILL4<5> VDD! VSS! / RM_IHPSG13_1024x16_c2_2P_COLDRV13_FILL4C2 +XCOLFILL4<6> VDD! VSS! / RM_IHPSG13_1024x16_c2_2P_COLDRV13_FILL4C2 +XCOLFILL4<7> VDD! VSS! / RM_IHPSG13_1024x16_c2_2P_COLDRV13_FILL4C2 +XCOLFILL4<8> VDD! VSS! / RM_IHPSG13_1024x16_c2_2P_COLDRV13_FILL4C2 +XCOLFILL4<9> VDD! VSS! / RM_IHPSG13_1024x16_c2_2P_COLDRV13_FILL4C2 +XCOLFILL4<10> VDD! VSS! / RM_IHPSG13_1024x16_c2_2P_COLDRV13_FILL4C2 +XCOLFILL4<11> VDD! VSS! / RM_IHPSG13_1024x16_c2_2P_COLDRV13_FILL4C2 +XCOLFILL4<12> VDD! VSS! / RM_IHPSG13_1024x16_c2_2P_COLDRV13_FILL4C2 +XCOLFILL4<13> VDD! VSS! / RM_IHPSG13_1024x16_c2_2P_COLDRV13_FILL4C2 +XCOLFILL4<14> VDD! VSS! / RM_IHPSG13_1024x16_c2_2P_COLDRV13_FILL4C2 +XCOLFILL4<15> VDD! VSS! / RM_IHPSG13_1024x16_c2_2P_COLDRV13_FILL4C2 +XCOLFILL4<16> VDD! VSS! / RM_IHPSG13_1024x16_c2_2P_COLDRV13_FILL4C2 +.ENDS diff --git a/flow/platforms/ihp-sg13g2/cdl/RM_IHPSG13_2P_1024x32_c2_bm_bist.cdl b/flow/platforms/ihp-sg13g2/cdl/RM_IHPSG13_2P_1024x32_c2_bm_bist.cdl new file mode 100644 index 0000000000..2c356c95a4 --- /dev/null +++ b/flow/platforms/ihp-sg13g2/cdl/RM_IHPSG13_2P_1024x32_c2_bm_bist.cdl @@ -0,0 +1,6482 @@ +* ------------------------------------------------------ +* +* Copyright 2025 IHP PDK Authors +* +* Licensed under the Apache License, Version 2.0 (the "License"); +* you may not use this file except in compliance with the License. +* You may obtain a copy of the License at +* +* https://www.apache.org/licenses/LICENSE-2.0 +* +* Unless required by applicable law or agreed to in writing, software +* distributed under the License is distributed on an "AS IS" BASIS, +* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +* See the License for the specific language governing permissions and +* limitations under the License. +* +* Generated on Wed Aug 27 13:09:02 2025 +* +* ------------------------------------------------------ + +.SUBCKT RM_IHPSG13_1024x32_c2_1P_BITKIT_CORNER NW PW VDD VSS +.ENDS +.SUBCKT RM_IHPSG13_1024x32_c2_1P_BITKIT_16x2_CORNER VDD_CORE VSS +XI16 VDD_CORE VSS VDD_CORE VSS / ++ RM_IHPSG13_1024x32_c2_1P_BITKIT_CORNER +.ENDS +.SUBCKT RM_IHPSG13_1024x32_c2_1P_BITKIT_EDGE_LR LWL NW PW VDD VSS +MN1 VSS LWL VSS VSS sg13_lv_nmos m=1 w=300.0n l=130.00n ng=1 nrd=0 nrs=0 +MN0 VSS net9 VSS VSS sg13_lv_nmos m=1 w=300.0n l=130.00n ng=1 nrd=0 nrs=0 +.ENDS +.SUBCKT RM_IHPSG13_1024x32_c2_1P_BITKIT_16x2_EDGE_LR A_WL<15> A_WL<14> A_WL<13> A_WL<12> ++ A_WL<11> A_WL<10> A_WL<9> A_WL<8> A_WL<7> A_WL<6> A_WL<5> A_WL<4> A_WL<3> ++ A_WL<2> A_WL<1> A_WL<0> VDD_CORE VSS +XI0<15> A_WL<15> VDD_CORE VSS VDD_CORE VSS / ++ RM_IHPSG13_1024x32_c2_1P_BITKIT_EDGE_LR +XI0<14> A_WL<14> VDD_CORE VSS VDD_CORE VSS / ++ RM_IHPSG13_1024x32_c2_1P_BITKIT_EDGE_LR +XI0<13> A_WL<13> VDD_CORE VSS VDD_CORE VSS / ++ RM_IHPSG13_1024x32_c2_1P_BITKIT_EDGE_LR +XI0<12> A_WL<12> VDD_CORE VSS VDD_CORE VSS / ++ RM_IHPSG13_1024x32_c2_1P_BITKIT_EDGE_LR +XI0<11> A_WL<11> VDD_CORE VSS VDD_CORE VSS / ++ RM_IHPSG13_1024x32_c2_1P_BITKIT_EDGE_LR +XI0<10> A_WL<10> VDD_CORE VSS VDD_CORE VSS / ++ RM_IHPSG13_1024x32_c2_1P_BITKIT_EDGE_LR +XI0<9> A_WL<9> VDD_CORE VSS VDD_CORE VSS / ++ RM_IHPSG13_1024x32_c2_1P_BITKIT_EDGE_LR +XI0<8> A_WL<8> VDD_CORE VSS VDD_CORE VSS / ++ RM_IHPSG13_1024x32_c2_1P_BITKIT_EDGE_LR +XI0<7> A_WL<7> VDD_CORE VSS VDD_CORE VSS / ++ RM_IHPSG13_1024x32_c2_1P_BITKIT_EDGE_LR +XI0<6> A_WL<6> VDD_CORE VSS VDD_CORE VSS / ++ RM_IHPSG13_1024x32_c2_1P_BITKIT_EDGE_LR +XI0<5> A_WL<5> VDD_CORE VSS VDD_CORE VSS / ++ RM_IHPSG13_1024x32_c2_1P_BITKIT_EDGE_LR +XI0<4> A_WL<4> VDD_CORE VSS VDD_CORE VSS / ++ RM_IHPSG13_1024x32_c2_1P_BITKIT_EDGE_LR +XI0<3> A_WL<3> VDD_CORE VSS VDD_CORE VSS / ++ RM_IHPSG13_1024x32_c2_1P_BITKIT_EDGE_LR +XI0<2> A_WL<2> VDD_CORE VSS VDD_CORE VSS / ++ RM_IHPSG13_1024x32_c2_1P_BITKIT_EDGE_LR +XI0<1> A_WL<1> VDD_CORE VSS VDD_CORE VSS / ++ RM_IHPSG13_1024x32_c2_1P_BITKIT_EDGE_LR +XI0<0> A_WL<0> VDD_CORE VSS VDD_CORE VSS / ++ RM_IHPSG13_1024x32_c2_1P_BITKIT_EDGE_LR +.ENDS +.SUBCKT RM_IHPSG13_1024x32_c2_1P_BITKIT_CELL BLC_BOT BLC_TOP BLT_BOT BLT_TOP LWL NW PW ++ RWL VDD VSS +MN0 NC NT VSS PW sg13_lv_nmos m=1 w=300.0n l=130.00n ng=1 nrd=0 nrs=0 +MN1 NT NC VSS PW sg13_lv_nmos m=1 w=300.0n l=130.00n ng=1 nrd=0 nrs=0 +MN3 NC RWL BLC_TOP PW sg13_lv_nmos m=1 w=300.0n l=130.00n ng=1 nrd=0 nrs=0 +MN2 BLT_BOT LWL NT PW sg13_lv_nmos m=1 w=300.0n l=130.00n ng=1 nrd=0 nrs=0 +MP1 NT NC VDD NW sg13_lv_pmos m=1 w=150.00n l=130.00n ng=1 nrd=0 nrs=0 +MP0 NC NT VDD NW sg13_lv_pmos m=1 w=150.00n l=130.00n ng=1 nrd=0 nrs=0 +R1 BLC_BOT BLC_TOP lvsres w=2.6e-07 l=6e-07 +R0 BLT_BOT BLT_TOP lvsres w=2.6e-07 l=6e-07 +R2 RWL LWL lvsres w=2.6e-07 l=6e-07 +.ENDS +.SUBCKT RM_IHPSG13_1024x32_c2_1P_BITKIT_16x2_SRAM A_BLC_BOT<1> A_BLC_BOT<0> A_BLC_TOP<1> ++ A_BLC_TOP<0> A_BLT_BOT<1> A_BLT_BOT<0> A_BLT_TOP<1> A_BLT_TOP<0> A_LWL<15> ++ A_LWL<14> A_LWL<13> A_LWL<12> A_LWL<11> A_LWL<10> A_LWL<9> A_LWL<8> A_LWL<7> ++ A_LWL<6> A_LWL<5> A_LWL<4> A_LWL<3> A_LWL<2> A_LWL<1> A_LWL<0> A_RWL<15> ++ A_RWL<14> A_RWL<13> A_RWL<12> A_RWL<11> A_RWL<10> A_RWL<9> A_RWL<8> A_RWL<7> ++ A_RWL<6> A_RWL<5> A_RWL<4> A_RWL<3> A_RWL<2> A_RWL<1> A_RWL<0> VDD_CORE ++ VSS +XCELL<31> A_BLC_TOP<1> A_RBLC<15> A_BLT_TOP<1> A_RBLT<15> A_RWL<15> ++ VDD_CORE VSS A_XWL<15> VDD_CORE VSS / ++ RM_IHPSG13_1024x32_c2_1P_BITKIT_CELL +XCELL<30> A_RBLC<14> A_RBLC<15> A_RBLT<14> A_RBLT<15> A_RWL<14> VDD_CORE ++ VSS A_XWL<14> VDD_CORE VSS / RM_IHPSG13_1024x32_c2_1P_BITKIT_CELL +XCELL<29> A_RBLC<14> A_RBLC<13> A_RBLT<14> A_RBLT<13> A_RWL<13> VDD_CORE ++ VSS A_XWL<13> VDD_CORE VSS / RM_IHPSG13_1024x32_c2_1P_BITKIT_CELL +XCELL<28> A_RBLC<12> A_RBLC<13> A_RBLT<12> A_RBLT<13> A_RWL<12> VDD_CORE ++ VSS A_XWL<12> VDD_CORE VSS / RM_IHPSG13_1024x32_c2_1P_BITKIT_CELL +XCELL<27> A_RBLC<12> A_RBLC<11> A_RBLT<12> A_RBLT<11> A_RWL<11> VDD_CORE ++ VSS A_XWL<11> VDD_CORE VSS / RM_IHPSG13_1024x32_c2_1P_BITKIT_CELL +XCELL<26> A_RBLC<10> A_RBLC<11> A_RBLT<10> A_RBLT<11> A_RWL<10> VDD_CORE ++ VSS A_XWL<10> VDD_CORE VSS / RM_IHPSG13_1024x32_c2_1P_BITKIT_CELL +XCELL<25> A_RBLC<10> A_RBLC<9> A_RBLT<10> A_RBLT<9> A_RWL<9> VDD_CORE ++ VSS A_XWL<9> VDD_CORE VSS / RM_IHPSG13_1024x32_c2_1P_BITKIT_CELL +XCELL<24> A_RBLC<8> A_RBLC<9> A_RBLT<8> A_RBLT<9> A_RWL<8> VDD_CORE ++ VSS A_XWL<8> VDD_CORE VSS / RM_IHPSG13_1024x32_c2_1P_BITKIT_CELL +XCELL<23> A_RBLC<8> A_RBLC<7> A_RBLT<8> A_RBLT<7> A_RWL<7> VDD_CORE ++ VSS A_XWL<7> VDD_CORE VSS / RM_IHPSG13_1024x32_c2_1P_BITKIT_CELL +XCELL<22> A_RBLC<6> A_RBLC<7> A_RBLT<6> A_RBLT<7> A_RWL<6> VDD_CORE ++ VSS A_XWL<6> VDD_CORE VSS / RM_IHPSG13_1024x32_c2_1P_BITKIT_CELL +XCELL<21> A_RBLC<6> A_RBLC<5> A_RBLT<6> A_RBLT<5> A_RWL<5> VDD_CORE ++ VSS A_XWL<5> VDD_CORE VSS / RM_IHPSG13_1024x32_c2_1P_BITKIT_CELL +XCELL<20> A_RBLC<4> A_RBLC<5> A_RBLT<4> A_RBLT<5> A_RWL<4> VDD_CORE ++ VSS A_XWL<4> VDD_CORE VSS / RM_IHPSG13_1024x32_c2_1P_BITKIT_CELL +XCELL<19> A_RBLC<4> A_RBLC<3> A_RBLT<4> A_RBLT<3> A_RWL<3> VDD_CORE ++ VSS A_XWL<3> VDD_CORE VSS / RM_IHPSG13_1024x32_c2_1P_BITKIT_CELL +XCELL<18> A_RBLC<2> A_RBLC<3> A_RBLT<2> A_RBLT<3> A_RWL<2> VDD_CORE ++ VSS A_XWL<2> VDD_CORE VSS / RM_IHPSG13_1024x32_c2_1P_BITKIT_CELL +XCELL<17> A_RBLC<2> A_RBLC<1> A_RBLT<2> A_RBLT<1> A_RWL<1> VDD_CORE ++ VSS A_XWL<1> VDD_CORE VSS / RM_IHPSG13_1024x32_c2_1P_BITKIT_CELL +XCELL<16> A_BLC_BOT<1> A_RBLC<1> A_BLT_BOT<1> A_RBLT<1> A_RWL<0> VDD_CORE ++ VSS A_XWL<0> VDD_CORE VSS / RM_IHPSG13_1024x32_c2_1P_BITKIT_CELL +XCELL<15> A_BLC_TOP<0> A_LBLC<15> A_BLT_TOP<0> A_LBLT<15> A_LWL<15> ++ VDD_CORE VSS A_XWL<15> VDD_CORE VSS / ++ RM_IHPSG13_1024x32_c2_1P_BITKIT_CELL +XCELL<14> A_LBLC<14> A_LBLC<15> A_LBLT<14> A_LBLT<15> A_LWL<14> VDD_CORE ++ VSS A_XWL<14> VDD_CORE VSS / RM_IHPSG13_1024x32_c2_1P_BITKIT_CELL +XCELL<13> A_LBLC<14> A_LBLC<13> A_LBLT<14> A_LBLT<13> A_LWL<13> VDD_CORE ++ VSS A_XWL<13> VDD_CORE VSS / RM_IHPSG13_1024x32_c2_1P_BITKIT_CELL +XCELL<12> A_LBLC<12> A_LBLC<13> A_LBLT<12> A_LBLT<13> A_LWL<12> VDD_CORE ++ VSS A_XWL<12> VDD_CORE VSS / RM_IHPSG13_1024x32_c2_1P_BITKIT_CELL +XCELL<11> A_LBLC<12> A_LBLC<11> A_LBLT<12> A_LBLT<11> A_LWL<11> VDD_CORE ++ VSS A_XWL<11> VDD_CORE VSS / RM_IHPSG13_1024x32_c2_1P_BITKIT_CELL +XCELL<10> A_LBLC<10> A_LBLC<11> A_LBLT<10> A_LBLT<11> A_LWL<10> VDD_CORE ++ VSS A_XWL<10> VDD_CORE VSS / RM_IHPSG13_1024x32_c2_1P_BITKIT_CELL +XCELL<9> A_LBLC<10> A_LBLC<9> A_LBLT<10> A_LBLT<9> A_LWL<9> VDD_CORE ++ VSS A_XWL<9> VDD_CORE VSS / RM_IHPSG13_1024x32_c2_1P_BITKIT_CELL +XCELL<8> A_LBLC<8> A_LBLC<9> A_LBLT<8> A_LBLT<9> A_LWL<8> VDD_CORE ++ VSS A_XWL<8> VDD_CORE VSS / RM_IHPSG13_1024x32_c2_1P_BITKIT_CELL +XCELL<7> A_LBLC<8> A_LBLC<7> A_LBLT<8> A_LBLT<7> A_LWL<7> VDD_CORE ++ VSS A_XWL<7> VDD_CORE VSS / RM_IHPSG13_1024x32_c2_1P_BITKIT_CELL +XCELL<6> A_LBLC<6> A_LBLC<7> A_LBLT<6> A_LBLT<7> A_LWL<6> VDD_CORE ++ VSS A_XWL<6> VDD_CORE VSS / RM_IHPSG13_1024x32_c2_1P_BITKIT_CELL +XCELL<5> A_LBLC<6> A_LBLC<5> A_LBLT<6> A_LBLT<5> A_LWL<5> VDD_CORE ++ VSS A_XWL<5> VDD_CORE VSS / RM_IHPSG13_1024x32_c2_1P_BITKIT_CELL +XCELL<4> A_LBLC<4> A_LBLC<5> A_LBLT<4> A_LBLT<5> A_LWL<4> VDD_CORE ++ VSS A_XWL<4> VDD_CORE VSS / RM_IHPSG13_1024x32_c2_1P_BITKIT_CELL +XCELL<3> A_LBLC<4> A_LBLC<3> A_LBLT<4> A_LBLT<3> A_LWL<3> VDD_CORE ++ VSS A_XWL<3> VDD_CORE VSS / RM_IHPSG13_1024x32_c2_1P_BITKIT_CELL +XCELL<2> A_LBLC<2> A_LBLC<3> A_LBLT<2> A_LBLT<3> A_LWL<2> VDD_CORE ++ VSS A_XWL<2> VDD_CORE VSS / RM_IHPSG13_1024x32_c2_1P_BITKIT_CELL +XCELL<1> A_LBLC<2> A_LBLC<1> A_LBLT<2> A_LBLT<1> A_LWL<1> VDD_CORE ++ VSS A_XWL<1> VDD_CORE VSS / RM_IHPSG13_1024x32_c2_1P_BITKIT_CELL +XCELL<0> A_BLC_BOT<0> A_LBLC<1> A_BLT_BOT<0> A_LBLT<1> A_LWL<0> VDD_CORE ++ VSS A_XWL<0> VDD_CORE VSS / RM_IHPSG13_1024x32_c2_1P_BITKIT_CELL +.ENDS +.SUBCKT RM_IHPSG13_1024x32_c2_1P_BITKIT_EDGE_TB BLC BLT NW PW VDD VSS +.ENDS +.SUBCKT RM_IHPSG13_1024x32_c2_1P_BITKIT_16x2_EDGE_TB A_BLC<1> A_BLC<0> A_BLT<1> A_BLT<0> ++ VDD_CORE VSS +XEDGE<1> A_BLC<1> A_BLT<1> VDD_CORE VSS VDD_CORE VSS ++ / RM_IHPSG13_1024x32_c2_1P_BITKIT_EDGE_TB +XEDGE<0> A_BLC<0> A_BLT<0> VDD_CORE VSS VDD_CORE VSS ++ / RM_IHPSG13_1024x32_c2_1P_BITKIT_EDGE_TB +.ENDS + +.SUBCKT RSC_IHPSG13_CBUFX4 A Z VDD VSS +MN0 net9 A VSS VSS sg13_lv_nmos m=1 w=705.000n l=130.00n ng=1 nrd=0 ++ nrs=0 +MN1 Z net9 VSS VSS sg13_lv_nmos m=1 w=1.41u l=130.00n ng=2 nrd=0 nrs=0 +MP0 net9 A VDD VDD sg13_lv_pmos m=1 w=1.62u l=130.00n ng=1 nrd=0 nrs=0 +MP1 Z net9 VDD VDD sg13_lv_pmos m=1 w=3.24u l=130.00n ng=2 nrd=0 nrs=0 +.ENDS +.SUBCKT RM_IHPSG13_1024x32_c2_1P_COLDRV13X4 ADDR_COL_I<1> ADDR_COL_I<0> ADDR_COL_O<1> ++ ADDR_COL_O<0> ADDR_DEC_I<7> ADDR_DEC_I<6> ADDR_DEC_I<5> ADDR_DEC_I<4> ++ ADDR_DEC_I<3> ADDR_DEC_I<2> ADDR_DEC_I<1> ADDR_DEC_I<0> ADDR_DEC_O<7> ++ ADDR_DEC_O<6> ADDR_DEC_O<5> ADDR_DEC_O<4> ADDR_DEC_O<3> ADDR_DEC_O<2> ++ ADDR_DEC_O<1> ADDR_DEC_O<0> DCLK_I DCLK_O RCLK_I RCLK_O WCLK_I WCLK_O ++ VDD VSS +XADDR_COL_DRV<1> ADDR_COL_I<1> ADDR_COL_O<1> VDD VSS / ++ RSC_IHPSG13_CBUFX4 +XADDR_COL_DRV<0> ADDR_COL_I<0> ADDR_COL_O<0> VDD VSS / ++ RSC_IHPSG13_CBUFX4 +XADDR_DEC_DRV<7> ADDR_DEC_I<7> ADDR_DEC_O<7> VDD VSS / ++ RSC_IHPSG13_CBUFX4 +XADDR_DEC_DRV<6> ADDR_DEC_I<6> ADDR_DEC_O<6> VDD VSS / ++ RSC_IHPSG13_CBUFX4 +XADDR_DEC_DRV<5> ADDR_DEC_I<5> ADDR_DEC_O<5> VDD VSS / ++ RSC_IHPSG13_CBUFX4 +XADDR_DEC_DRV<4> ADDR_DEC_I<4> ADDR_DEC_O<4> VDD VSS / ++ RSC_IHPSG13_CBUFX4 +XADDR_DEC_DRV<3> ADDR_DEC_I<3> ADDR_DEC_O<3> VDD VSS / ++ RSC_IHPSG13_CBUFX4 +XADDR_DEC_DRV<2> ADDR_DEC_I<2> ADDR_DEC_O<2> VDD VSS / ++ RSC_IHPSG13_CBUFX4 +XADDR_DEC_DRV<1> ADDR_DEC_I<1> ADDR_DEC_O<1> VDD VSS / ++ RSC_IHPSG13_CBUFX4 +XADDR_DEC_DRV<0> ADDR_DEC_I<0> ADDR_DEC_O<0> VDD VSS / ++ RSC_IHPSG13_CBUFX4 +XDCLK_DRV DCLK_I DCLK_O VDD VSS / RSC_IHPSG13_CBUFX4 +XRCLK_DRV RCLK_I RCLK_O VDD VSS / RSC_IHPSG13_CBUFX4 +XWCLK_DRV WCLK_I WCLK_O VDD VSS / RSC_IHPSG13_CBUFX4 +.ENDS +.SUBCKT RSC_IHPSG13_WLDRVX4 A Z VDD VSS +MN1 Z net6 VSS VSS sg13_lv_nmos m=1 w=705.000n l=130.00n ng=1 nrd=0 ++ nrs=0 +MN0 net6 A VSS VSS sg13_lv_nmos m=1 w=900.0n l=130.00n ng=1 nrd=0 nrs=0 +MP1 Z net6 VDD VDD sg13_lv_pmos m=1 w=3.24u l=130.00n ng=2 nrd=0 nrs=0 +MP0 net6 A VDD VDD sg13_lv_pmos m=1 w=900.0n l=130.00n ng=1 nrd=0 nrs=0 +.ENDS +.SUBCKT RM_IHPSG13_1024x32_c2_1P_WLDRV16X4 A<15> A<14> A<13> A<12> A<11> A<10> A<9> A<8> ++ A<7> A<6> A<5> A<4> A<3> A<2> A<1> A<0> Z<15> Z<14> Z<13> Z<12> Z<11> Z<10> ++ Z<9> Z<8> Z<7> Z<6> Z<5> Z<4> Z<3> Z<2> Z<1> Z<0> VDD VSS +XBUF<15> A<15> Z<15> VDD VSS / RSC_IHPSG13_WLDRVX4 +XBUF<14> A<14> Z<14> VDD VSS / RSC_IHPSG13_WLDRVX4 +XBUF<13> A<13> Z<13> VDD VSS / RSC_IHPSG13_WLDRVX4 +XBUF<12> A<12> Z<12> VDD VSS / RSC_IHPSG13_WLDRVX4 +XBUF<11> A<11> Z<11> VDD VSS / RSC_IHPSG13_WLDRVX4 +XBUF<10> A<10> Z<10> VDD VSS / RSC_IHPSG13_WLDRVX4 +XBUF<9> A<9> Z<9> VDD VSS / RSC_IHPSG13_WLDRVX4 +XBUF<8> A<8> Z<8> VDD VSS / RSC_IHPSG13_WLDRVX4 +XBUF<7> A<7> Z<7> VDD VSS / RSC_IHPSG13_WLDRVX4 +XBUF<6> A<6> Z<6> VDD VSS / RSC_IHPSG13_WLDRVX4 +XBUF<5> A<5> Z<5> VDD VSS / RSC_IHPSG13_WLDRVX4 +XBUF<4> A<4> Z<4> VDD VSS / RSC_IHPSG13_WLDRVX4 +XBUF<3> A<3> Z<3> VDD VSS / RSC_IHPSG13_WLDRVX4 +XBUF<2> A<2> Z<2> VDD VSS / RSC_IHPSG13_WLDRVX4 +XBUF<1> A<1> Z<1> VDD VSS / RSC_IHPSG13_WLDRVX4 +XBUF<0> A<0> Z<0> VDD VSS / RSC_IHPSG13_WLDRVX4 +.ENDS +.SUBCKT RSC_IHPSG13_FILLCAP8 VDD VSS +MN0 vss_r vdd_r VSS VSS sg13_lv_nmos m=1 w=4.98u l=130.00n ng=6 nrd=0 ++ nrs=0 +MP0 vdd_r vss_r VDD VDD sg13_lv_pmos m=1 w=6.48u l=385.000n ng=4 nrd=0 ++ nrs=0 +.ENDS +.SUBCKT RSC_IHPSG13_LHPQX2 CP D Q VDD VSS +MN3 QIN CPN net14 VSS sg13_lv_nmos m=1 w=480.00n l=130.00n ng=1 nrd=0 nrs=0 +MN2 net14 net10 VSS VSS sg13_lv_nmos m=1 w=480.00n l=130.00n ng=1 ++ nrd=0 nrs=0 +MN5 net21 D VSS VSS sg13_lv_nmos m=1 w=870.00n l=130.00n ng=1 nrd=0 ++ nrs=0 +MN6 QIN CP net21 VSS sg13_lv_nmos m=1 w=870.00n l=130.00n ng=1 nrd=0 nrs=0 +MN1 net10 QIN VSS VSS sg13_lv_nmos m=1 w=480.00n l=130.00n ng=1 nrd=0 ++ nrs=0 +MN0 CPN CP VSS VSS sg13_lv_nmos m=1 w=480.00n l=130.00n ng=1 nrd=0 ++ nrs=0 +MN4 Q QIN VSS VSS sg13_lv_nmos m=1 w=980.00n l=130.00n ng=1 nrd=0 nrs=0 +MP2 QIN CP net16 VDD sg13_lv_pmos m=1 w=480.00n l=130.00n ng=1 nrd=0 nrs=0 +MP0 CPN CP VDD VDD sg13_lv_pmos m=1 w=480.00n l=130.00n ng=1 nrd=0 ++ nrs=0 +MP4 Q QIN VDD VDD sg13_lv_pmos m=1 w=1.62u l=130.00n ng=1 nrd=0 nrs=0 +MP3 net10 QIN VDD VDD sg13_lv_pmos m=1 w=480.00n l=130.00n ng=1 nrd=0 ++ nrs=0 +MP1 net16 net10 VDD VDD sg13_lv_pmos m=1 w=480.00n l=130.00n ng=1 ++ nrd=0 nrs=0 +MP6 QIN CPN net20 VDD sg13_lv_pmos m=1 w=975.000n l=130.00n ng=1 nrd=0 ++ nrs=0 +MP5 net20 D VDD VDD sg13_lv_pmos m=1 w=975.000n l=130.00n ng=1 nrd=0 ++ nrs=0 +.ENDS +.SUBCKT RSC_IHPSG13_NAND2X2 A B Z VDD VSS +MP1 Z B VDD VDD sg13_lv_pmos m=1 w=1.62u l=130.00n ng=1 nrd=0 nrs=0 +MP0 Z A VDD VDD sg13_lv_pmos m=1 w=1.62u l=130.00n ng=1 nrd=0 nrs=0 +MN0 Z B net7 VSS sg13_lv_nmos m=1 w=980.00n l=130.00n ng=1 nrd=0 nrs=0 +MN1 net7 A VSS VSS sg13_lv_nmos m=1 w=980.00n l=130.00n ng=1 nrd=0 ++ nrs=0 +.ENDS +.SUBCKT RSC_IHPSG13_CINVX4 A Z VDD VSS +MN0 Z A VSS VSS sg13_lv_nmos m=1 w=1.41u l=130.00n ng=2 nrd=0 nrs=0 +MP0 Z A VDD VDD sg13_lv_pmos m=1 w=3.24u l=130.00n ng=2 nrd=0 nrs=0 +.ENDS +.SUBCKT RSC_IHPSG13_CINVX2 A Z VDD VSS +MN0 Z A VSS VSS sg13_lv_nmos m=1 w=705.000n l=130.00n ng=1 nrd=0 nrs=0 +MP0 Z A VDD VDD sg13_lv_pmos m=1 w=1.62u l=130.00n ng=1 nrd=0 nrs=0 +.ENDS +.SUBCKT RSC_IHPSG13_INVX2 A Z VDD VSS +MN0 Z A VSS VSS sg13_lv_nmos m=1 w=980.00n l=130.00n ng=1 nrd=0 nrs=0 +MP0 Z A VDD VDD sg13_lv_pmos m=1 w=1.62u l=130.00n ng=1 nrd=0 nrs=0 +.ENDS +.SUBCKT RSC_IHPSG13_NAND3X2 A B C Z VDD VSS +MP2 Z A VDD VDD sg13_lv_pmos m=1 w=1.62u l=130.00n ng=1 nrd=0 nrs=0 +MP1 Z B VDD VDD sg13_lv_pmos m=1 w=1.62u l=130.00n ng=1 nrd=0 nrs=0 +MP0 Z C VDD VDD sg13_lv_pmos m=1 w=1.62u l=130.00n ng=1 nrd=0 nrs=0 +MN1 net12 B net16 VSS sg13_lv_nmos m=1 w=980.00n l=130.00n ng=1 nrd=0 nrs=0 +MN0 Z C net12 VSS sg13_lv_nmos m=1 w=980.00n l=130.00n ng=1 nrd=0 nrs=0 +MN2 net16 A VSS VSS sg13_lv_nmos m=1 w=980.00n l=130.00n ng=1 nrd=0 ++ nrs=0 +.ENDS +.SUBCKT RSC_IHPSG13_NOR3X2 A B C Z VDD VSS +MP0 net13 A VDD VDD sg13_lv_pmos m=1 w=1.62u l=130.00n ng=1 nrd=0 nrs=0 +MP2 Z C net10 VDD sg13_lv_pmos m=1 w=1.62u l=130.00n ng=1 nrd=0 nrs=0 +MP1 net10 B net13 VDD sg13_lv_pmos m=1 w=1.62u l=130.00n ng=1 nrd=0 nrs=0 +MN1 Z B VSS VSS sg13_lv_nmos m=1 w=875.000n l=130.00n ng=1 nrd=0 nrs=0 +MN0 Z C VSS VSS sg13_lv_nmos m=1 w=875.000n l=130.00n ng=1 nrd=0 nrs=0 +MN2 Z A VSS VSS sg13_lv_nmos m=1 w=875.000n l=130.00n ng=1 nrd=0 nrs=0 +.ENDS +.SUBCKT RSC_IHPSG13_FILLCAP4 VDD VSS +MN0 vss_r vdd_r VSS VSS sg13_lv_nmos m=1 w=2.49u l=130.00n ng=3 nrd=0 ++ nrs=0 +MP0 vdd_r vss_r VDD VDD sg13_lv_pmos m=1 w=3.24u l=385.000n ng=2 nrd=0 ++ nrs=0 +.ENDS +.SUBCKT RSC_IHPSG13_MET2RES A B +R0 B A lvsres w=2.6e-07 l=6e-07 +.ENDS +.SUBCKT RM_IHPSG13_1024x32_c2_1P_DEC04 ADDR<3> ADDR<2> ADDR<1> ADDR<0> CS ECLK_H_BOT ++ ECLK_H_TOP ECLK_L_BOT ECLK_L_TOP WL<15> WL<14> WL<13> WL<12> WL<11> WL<10> ++ WL<9> WL<8> WL<7> WL<6> WL<5> WL<4> WL<3> WL<2> WL<1> WL<0> VDD VSS +XLATCH<3> CS ADDR<3> PADR<3> VDD VSS / RSC_IHPSG13_LHPQX2 +XLATCH<2> CS ADDR<2> PADR<2> VDD VSS / RSC_IHPSG13_LHPQX2 +XLATCH<1> CS ADDR<1> PADR<1> VDD VSS / RSC_IHPSG13_LHPQX2 +XLATCH<0> CS ADDR<0> PADR<0> VDD VSS / RSC_IHPSG13_LHPQX2 +XI0<3> PADR<1> PADR<0> sel01<3> VDD VSS / RSC_IHPSG13_NAND2X2 +XI0<2> PADR<1> NADR<0> sel01<2> VDD VSS / RSC_IHPSG13_NAND2X2 +XI0<1> NADR<1> PADR<0> sel01<1> VDD VSS / RSC_IHPSG13_NAND2X2 +XI0<0> NADR<1> NADR<0> sel01<0> VDD VSS / RSC_IHPSG13_NAND2X2 +XI4 ECLK_L_BOT EN VDD VSS / RSC_IHPSG13_CINVX4 +XI5 ECLK_H_BOT ECLK_L_BOT VDD VSS / RSC_IHPSG13_CINVX2 +XI3<3> PADR<3> NADR<3> VDD VSS / RSC_IHPSG13_INVX2 +XI3<2> PADR<2> NADR<2> VDD VSS / RSC_IHPSG13_INVX2 +XI3<1> PADR<1> NADR<1> VDD VSS / RSC_IHPSG13_INVX2 +XI3<0> PADR<0> NADR<0> VDD VSS / RSC_IHPSG13_INVX2 +XI1<3> PADR<2> PADR<3> CS sel23<3> VDD VSS / RSC_IHPSG13_NAND3X2 +XI1<2> NADR<2> PADR<3> CS sel23<2> VDD VSS / RSC_IHPSG13_NAND3X2 +XI1<1> PADR<2> NADR<3> CS sel23<1> VDD VSS / RSC_IHPSG13_NAND3X2 +XI1<0> NADR<2> NADR<3> CS sel23<0> VDD VSS / RSC_IHPSG13_NAND3X2 +XI2<15> sel23<3> sel01<3> EN WL<15> VDD VSS / RSC_IHPSG13_NOR3X2 +XI2<14> sel23<3> sel01<2> EN WL<14> VDD VSS / RSC_IHPSG13_NOR3X2 +XI2<13> sel23<3> sel01<1> EN WL<13> VDD VSS / RSC_IHPSG13_NOR3X2 +XI2<12> sel23<3> sel01<0> EN WL<12> VDD VSS / RSC_IHPSG13_NOR3X2 +XI2<11> sel23<2> sel01<3> EN WL<11> VDD VSS / RSC_IHPSG13_NOR3X2 +XI2<10> sel23<2> sel01<2> EN WL<10> VDD VSS / RSC_IHPSG13_NOR3X2 +XI2<9> sel23<2> sel01<1> EN WL<9> VDD VSS / RSC_IHPSG13_NOR3X2 +XI2<8> sel23<2> sel01<0> EN WL<8> VDD VSS / RSC_IHPSG13_NOR3X2 +XI2<7> sel23<1> sel01<3> EN WL<7> VDD VSS / RSC_IHPSG13_NOR3X2 +XI2<6> sel23<1> sel01<2> EN WL<6> VDD VSS / RSC_IHPSG13_NOR3X2 +XI2<5> sel23<1> sel01<1> EN WL<5> VDD VSS / RSC_IHPSG13_NOR3X2 +XI2<4> sel23<1> sel01<0> EN WL<4> VDD VSS / RSC_IHPSG13_NOR3X2 +XI2<3> sel23<0> sel01<3> EN WL<3> VDD VSS / RSC_IHPSG13_NOR3X2 +XI2<2> sel23<0> sel01<2> EN WL<2> VDD VSS / RSC_IHPSG13_NOR3X2 +XI2<1> sel23<0> sel01<1> EN WL<1> VDD VSS / RSC_IHPSG13_NOR3X2 +XI2<0> sel23<0> sel01<0> EN WL<0> VDD VSS / RSC_IHPSG13_NOR3X2 +XCAPS4 VDD VSS / RSC_IHPSG13_FILLCAP4 +XI11 ECLK_L_BOT ECLK_L_TOP / RSC_IHPSG13_MET2RES +XR0 ECLK_H_BOT ECLK_H_TOP / RSC_IHPSG13_MET2RES +.ENDS +.SUBCKT RM_IHPSG13_1024x32_c2_1P_ROWDEC4 ADDR_N_I<3> ADDR_N_I<2> ADDR_N_I<1> ADDR_N_I<0> ++ CS_I ECLK_I WL_O<15> WL_O<14> WL_O<13> WL_O<12> WL_O<11> WL_O<10> WL_O<9> ++ WL_O<8> WL_O<7> WL_O<6> WL_O<5> WL_O<4> WL_O<3> WL_O<2> WL_O<1> WL_O<0> ++ VDD VSS +XL2<8> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<7> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<6> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<5> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<4> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<3> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<2> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<1> VDD VSS / RSC_IHPSG13_FILLCAP8 +XSEL ADDR_N_I<3> ADDR_N_I<2> ADDR_N_I<1> ADDR_N_I<0> CS_I ECLK_I ECLK_H<1> ++ ECLK_B<0> ECLK_B<1> WL_O<15> WL_O<14> WL_O<13> WL_O<12> WL_O<11> WL_O<10> ++ WL_O<9> WL_O<8> WL_O<7> WL_O<6> WL_O<5> WL_O<4> WL_O<3> WL_O<2> WL_O<1> ++ WL_O<0> VDD VSS / RM_IHPSG13_1024x32_c2_1P_DEC04 +.ENDS +.SUBCKT RSC_IHPSG13_CINVX8 A Z VDD VSS +MN0 Z A VSS VSS sg13_lv_nmos m=1 w=2.82u l=130.00n ng=4 nrd=0 nrs=0 +MP0 Z A VDD VDD sg13_lv_pmos m=1 w=6.48u l=130.00n ng=4 nrd=0 nrs=0 +.ENDS +.SUBCKT RSC_IHPSG13_DFNQMX2IX1 BE BI CN D QI QIN VDD VSS +MN15 net026 BI VSS VSS sg13_lv_nmos m=1 w=560.00n l=130.00n ng=1 nrd=0 ++ nrs=0 +MN14 MXI_OUT BE net026 VSS sg13_lv_nmos m=1 w=560.00n l=130.00n ng=1 nrd=0 ++ nrs=0 +MN1 net025 D VSS VSS sg13_lv_nmos m=1 w=560.00n l=130.00n ng=1 nrd=0 ++ nrs=0 +MN0 MXI_OUT BEN net025 VSS sg13_lv_nmos m=1 w=560.00n l=130.00n ng=1 nrd=0 ++ nrs=0 +MN10 QI CNN net21 VSS sg13_lv_nmos m=1 w=850.00n l=130.00n ng=1 nrd=0 nrs=0 +MN11 net21 QI_MS VSS VSS sg13_lv_nmos m=1 w=850.00n l=130.00n ng=1 ++ nrd=0 nrs=0 +MN7 net30 QI_MS VSS VSS sg13_lv_nmos m=1 w=480.00n l=130.00n ng=1 ++ nrd=0 nrs=0 +MN6 QIN_MS CNN net30 VSS sg13_lv_nmos m=1 w=480.00n l=130.00n ng=1 nrd=0 ++ nrs=0 +MN3 QI_MS QIN_MS VSS VSS sg13_lv_nmos m=1 w=480.00n l=130.00n ng=1 ++ nrd=0 nrs=0 +MN12 CNN CN VSS VSS sg13_lv_nmos m=1 w=495.000n l=130.00n ng=1 nrd=0 ++ nrs=0 +MN9 net37 MXI_OUT VSS VSS sg13_lv_nmos m=1 w=870.00n l=130.00n ng=1 ++ nrd=0 nrs=0 +MN8 QIN_MS CN net37 VSS sg13_lv_nmos m=1 w=870.00n l=130.00n ng=1 nrd=0 ++ nrs=0 +MN5 QI CN net25 VSS sg13_lv_nmos m=1 w=480.00n l=130.00n ng=1 nrd=0 nrs=0 +MN4 net25 QIN VSS VSS sg13_lv_nmos m=1 w=480.00n l=130.00n ng=1 nrd=0 ++ nrs=0 +MN2 QIN QI VSS VSS sg13_lv_nmos m=1 w=480.00n l=130.00n ng=1 nrd=0 ++ nrs=0 +MN13 BEN BE VSS VSS sg13_lv_nmos m=1 w=560.00n l=130.00n ng=1 nrd=0 ++ nrs=0 +MP15 MXI_OUT BEN net027 VDD sg13_lv_pmos m=1 w=985.000n l=130.00n ng=1 ++ nrd=0 nrs=0 +MP14 net027 BI VDD VDD sg13_lv_pmos m=1 w=985.000n l=130.00n ng=1 ++ nrd=0 nrs=0 +MP1 MXI_OUT BE net024 VDD sg13_lv_pmos m=1 w=985.000n l=130.00n ng=1 nrd=0 ++ nrs=0 +MP0 net024 D VDD VDD sg13_lv_pmos m=1 w=985.000n l=130.00n ng=1 nrd=0 ++ nrs=0 +MP13 BEN BE VDD VDD sg13_lv_pmos m=1 w=645.000n l=130.00n ng=1 nrd=0 ++ nrs=0 +MP6 QI_MS QIN_MS VDD VDD sg13_lv_pmos m=1 w=480.00n l=130.00n ng=1 ++ nrd=0 nrs=0 +MP3 QI CNN net27 VDD sg13_lv_pmos m=1 w=480.00n l=130.00n ng=1 nrd=0 nrs=0 +MP2 net27 QIN VDD VDD sg13_lv_pmos m=1 w=480.00n l=130.00n ng=1 nrd=0 ++ nrs=0 +MP10 net36 MXI_OUT VDD VDD sg13_lv_pmos m=1 w=975.000n l=130.00n ng=1 ++ nrd=0 nrs=0 +MP11 QIN_MS CNN net36 VDD sg13_lv_pmos m=1 w=975.000n l=130.00n ng=1 nrd=0 ++ nrs=0 +MP4 net32 QI_MS VDD VDD sg13_lv_pmos m=1 w=480.00n l=130.00n ng=1 ++ nrd=0 nrs=0 +MP5 QIN_MS CN net32 VDD sg13_lv_pmos m=1 w=480.00n l=130.00n ng=1 nrd=0 ++ nrs=0 +MP7 QIN QI VDD VDD sg13_lv_pmos m=1 w=480.00n l=130.00n ng=1 nrd=0 ++ nrs=0 +MP12 CNN CN VDD VDD sg13_lv_pmos m=1 w=480.00n l=130.00n ng=1 nrd=0 ++ nrs=0 +MP9 QI CN net19 VDD sg13_lv_pmos m=1 w=990.00n l=130.00n ng=1 nrd=0 nrs=0 +MP8 net19 QI_MS VDD VDD sg13_lv_pmos m=1 w=990.00n l=130.00n ng=1 ++ nrd=0 nrs=0 +.ENDS +.SUBCKT RM_IHPSG13_1024x32_c2_1P_ROWREG4 ACLK_N_I ADDR_I<3> ADDR_I<2> ADDR_I<1> ADDR_I<0> ++ ADDR_N_O<3> ADDR_N_O<2> ADDR_N_O<1> ADDR_N_O<0> BIST_ADDR_I<3> ++ BIST_ADDR_I<2> BIST_ADDR_I<1> BIST_ADDR_I<0> BIST_EN_I VDD VSS +XINV<3> q_int<3> qn_int<3> VDD VSS / RSC_IHPSG13_CINVX2 +XINV<2> q_int<2> qn_int<2> VDD VSS / RSC_IHPSG13_CINVX2 +XINV<1> q_int<1> qn_int<1> VDD VSS / RSC_IHPSG13_CINVX2 +XINV<0> q_int<0> qn_int<0> VDD VSS / RSC_IHPSG13_CINVX2 +XDRV<3> qn_int<3> ADDR_N_O<3> VDD VSS / RSC_IHPSG13_CINVX8 +XDRV<2> qn_int<2> ADDR_N_O<2> VDD VSS / RSC_IHPSG13_CINVX8 +XDRV<1> qn_int<1> ADDR_N_O<1> VDD VSS / RSC_IHPSG13_CINVX8 +XDRV<0> qn_int<0> ADDR_N_O<0> VDD VSS / RSC_IHPSG13_CINVX8 +XDFF<3> BIST_EN_I BIST_ADDR_I<3> ACLK_N_I ADDR_I<3> q_int<3> net2<0> VDD ++ VSS / RSC_IHPSG13_DFNQMX2IX1 +XDFF<2> BIST_EN_I BIST_ADDR_I<2> ACLK_N_I ADDR_I<2> q_int<2> net2<1> VDD ++ VSS / RSC_IHPSG13_DFNQMX2IX1 +XDFF<1> BIST_EN_I BIST_ADDR_I<1> ACLK_N_I ADDR_I<1> q_int<1> net2<2> VDD ++ VSS / RSC_IHPSG13_DFNQMX2IX1 +XDFF<0> BIST_EN_I BIST_ADDR_I<0> ACLK_N_I ADDR_I<0> q_int<0> net2<3> VDD ++ VSS / RSC_IHPSG13_DFNQMX2IX1 +XI11<20> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI11<19> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI11<18> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI11<17> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI11<16> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI11<15> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI11<14> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI11<13> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI11<12> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI11<11> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI11<10> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI11<9> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI11<8> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI11<7> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI11<6> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI11<5> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI11<4> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI11<3> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI11<2> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI11<1> VDD VSS / RSC_IHPSG13_FILLCAP8 +.ENDS +.SUBCKT RSC_IHPSG13_CDLYX1 A Z VDD VSS +MN1 net010 net032 VSS VSS sg13_lv_nmos m=1 w=300.0n l=160.00n ng=1 ++ nrd=0 nrs=0 +MN2 net032 A net014 VSS sg13_lv_nmos m=1 w=300.0n l=160.00n ng=1 nrd=0 ++ nrs=0 +MN0 Z net032 net010 VSS sg13_lv_nmos m=1 w=300.0n l=160.00n ng=1 nrd=0 ++ nrs=0 +MN3 net014 A VSS VSS sg13_lv_nmos m=1 w=300.0n l=160.00n ng=1 nrd=0 ++ nrs=0 +MP1 Z net032 net07 VDD sg13_lv_pmos m=1 w=720.00n l=160.00n ng=1 nrd=0 ++ nrs=0 +MP3 net011 A VDD VDD sg13_lv_pmos m=1 w=720.00n l=160.00n ng=1 nrd=0 ++ nrs=0 +MP0 net07 net032 VDD VDD sg13_lv_pmos m=1 w=720.00n l=160.00n ng=1 ++ nrd=0 nrs=0 +MP2 net032 A net011 VDD sg13_lv_pmos m=1 w=720.00n l=160.00n ng=1 nrd=0 ++ nrs=0 +.ENDS +.SUBCKT RSC_IHPSG13_CDLYX1_DUMMY A Z VDD VSS +MN0 vss_r vdd_r VSS VSS sg13_lv_nmos m=1 w=2.49u l=300.0n ng=3 nrd=0 ++ nrs=0 +MP0 vdd_r vss_r VDD VDD sg13_lv_pmos m=1 w=3.24u l=640.00n ng=2 nrd=0 ++ nrs=0 +R0 Z A lvsres w=2.6e-07 l=6e-07 +.ENDS + +.SUBCKT RSC_IHPSG13_MX2IX1 A0 A1 S ZN VDD VSS +MP4 SN S VDD VDD sg13_lv_pmos m=1 w=645.000n l=130.00n ng=1 nrd=0 nrs=0 +MP3 ZN SN net12 VDD sg13_lv_pmos m=1 w=985.000n l=130.00n ng=1 nrd=0 nrs=0 +MP2 net12 A1 VDD VDD sg13_lv_pmos m=1 w=985.000n l=130.00n ng=1 nrd=0 ++ nrs=0 +MP1 ZN S net17 VDD sg13_lv_pmos m=1 w=985.000n l=130.00n ng=1 nrd=0 nrs=0 +MP0 net17 A0 VDD VDD sg13_lv_pmos m=1 w=985.000n l=130.00n ng=1 nrd=0 ++ nrs=0 +MN5 SN S VSS VSS sg13_lv_nmos m=1 w=480.00n l=130.00n ng=1 nrd=0 nrs=0 +MN3 net13 A1 VSS VSS sg13_lv_nmos m=1 w=480.00n l=130.00n ng=1 nrd=0 ++ nrs=0 +MN2 ZN S net13 VSS sg13_lv_nmos m=1 w=480.00n l=130.00n ng=1 nrd=0 nrs=0 +MN1 net15 A0 VSS VSS sg13_lv_nmos m=1 w=480.00n l=130.00n ng=1 nrd=0 ++ nrs=0 +MN0 ZN SN net15 VSS sg13_lv_nmos m=1 w=480.00n l=130.00n ng=1 nrd=0 nrs=0 +.ENDS +.SUBCKT RM_IHPSG13_1024x32_c2_1P_DLY_MUX A SEL Z VDD VSS +XI11 net4 Z VDD VSS / RSC_IHPSG13_CINVX2 +XI8 A D<3> SEL net4 VDD VSS / RSC_IHPSG13_MX2IX1 +XI20<3> D<2> D<3> VDD VSS / RSC_IHPSG13_CDLYX1 +XI20<2> D<1> D<2> VDD VSS / RSC_IHPSG13_CDLYX1 +XI20<1> A D<1> VDD VSS / RSC_IHPSG13_CDLYX1 +.ENDS +.SUBCKT RSC_IHPSG13_DFNQX2 CN D Q VDD VSS +MN0 Q QIN_SL VSS VSS sg13_lv_nmos m=1 w=980.00n l=130.00n ng=1 nrd=0 ++ nrs=0 +MN10 QIN_SL CNN net21 VSS sg13_lv_nmos m=1 w=850.00n l=130.00n ng=1 nrd=0 ++ nrs=0 +MN11 net21 QI_MS VSS VSS sg13_lv_nmos m=1 w=850.00n l=130.00n ng=1 ++ nrd=0 nrs=0 +MN7 net30 QI_MS VSS VSS sg13_lv_nmos m=1 w=480.00n l=130.00n ng=1 ++ nrd=0 nrs=0 +MN6 QIN_MS CNN net30 VSS sg13_lv_nmos m=1 w=480.00n l=130.00n ng=1 nrd=0 ++ nrs=0 +MN3 QI_MS QIN_MS VSS VSS sg13_lv_nmos m=1 w=480.00n l=130.00n ng=1 ++ nrd=0 nrs=0 +MN12 CNN CN VSS VSS sg13_lv_nmos m=1 w=495.000n l=130.00n ng=1 nrd=0 ++ nrs=0 +MN9 net37 D VSS VSS sg13_lv_nmos m=1 w=870.00n l=130.00n ng=1 nrd=0 ++ nrs=0 +MN8 QIN_MS CN net37 VSS sg13_lv_nmos m=1 w=870.00n l=130.00n ng=1 nrd=0 ++ nrs=0 +MN5 QIN_SL CN net25 VSS sg13_lv_nmos m=1 w=480.00n l=130.00n ng=1 nrd=0 ++ nrs=0 +MN4 net25 QI_SL VSS VSS sg13_lv_nmos m=1 w=480.00n l=130.00n ng=1 ++ nrd=0 nrs=0 +MN2 QI_SL QIN_SL VSS VSS sg13_lv_nmos m=1 w=480.00n l=130.00n ng=1 ++ nrd=0 nrs=0 +MP0 Q QIN_SL VDD VDD sg13_lv_pmos m=1 w=1.62u l=130.00n ng=1 nrd=0 ++ nrs=0 +MP6 QI_MS QIN_MS VDD VDD sg13_lv_pmos m=1 w=480.00n l=130.00n ng=1 ++ nrd=0 nrs=0 +MP3 QIN_SL CNN net27 VDD sg13_lv_pmos m=1 w=480.00n l=130.00n ng=1 nrd=0 ++ nrs=0 +MP2 net27 QI_SL VDD VDD sg13_lv_pmos m=1 w=480.00n l=130.00n ng=1 ++ nrd=0 nrs=0 +MP10 net36 D VDD VDD sg13_lv_pmos m=1 w=975.000n l=130.00n ng=1 nrd=0 ++ nrs=0 +MP11 QIN_MS CNN net36 VDD sg13_lv_pmos m=1 w=975.000n l=130.00n ng=1 nrd=0 ++ nrs=0 +MP4 net32 QI_MS VDD VDD sg13_lv_pmos m=1 w=480.00n l=130.00n ng=1 ++ nrd=0 nrs=0 +MP5 QIN_MS CN net32 VDD sg13_lv_pmos m=1 w=480.00n l=130.00n ng=1 nrd=0 ++ nrs=0 +MP7 QI_SL QIN_SL VDD VDD sg13_lv_pmos m=1 w=480.00n l=130.00n ng=1 ++ nrd=0 nrs=0 +MP12 CNN CN VDD VDD sg13_lv_pmos m=1 w=480.00n l=130.00n ng=1 nrd=0 ++ nrs=0 +MP9 QIN_SL CN net19 VDD sg13_lv_pmos m=1 w=990.00n l=130.00n ng=1 nrd=0 ++ nrs=0 +MP8 net19 QI_MS VDD VDD sg13_lv_pmos m=1 w=990.00n l=130.00n ng=1 ++ nrd=0 nrs=0 +.ENDS +.SUBCKT RSC_IHPSG13_CNAND2X2 A B Z VDD VSS +MN0 Z B net6 VSS sg13_lv_nmos m=1 w=980.00n l=130.00n ng=1 nrd=0 nrs=0 +MN1 net6 A VSS VSS sg13_lv_nmos m=1 w=980.00n l=130.00n ng=1 nrd=0 ++ nrs=0 +MP1 Z B VDD VDD sg13_lv_pmos m=1 w=1.62u l=130.00n ng=1 nrd=0 nrs=0 +MP0 Z A VDD VDD sg13_lv_pmos m=1 w=1.62u l=130.00n ng=1 nrd=0 nrs=0 +.ENDS +.SUBCKT RSC_IHPSG13_CGATEPX4 CP E Q VDD VSS +MN1 net08 QIN VSS VSS sg13_lv_nmos m=1 w=480.00n l=130.00n ng=1 nrd=0 ++ nrs=0 +MN2 net019 net08 VSS VSS sg13_lv_nmos m=1 w=480.00n l=130.00n ng=1 ++ nrd=0 nrs=0 +MN3 QIN CP net019 VSS sg13_lv_nmos m=1 w=480.00n l=130.00n ng=1 nrd=0 nrs=0 +MN6 Q net015 VSS VSS sg13_lv_nmos m=1 w=1.41u l=130.00n ng=2 nrd=0 ++ nrs=0 +MN5 net015 net08 net018 VSS sg13_lv_nmos m=1 w=980.00n l=130.00n ng=1 ++ nrd=0 nrs=0 +MN8 QIN CPN net023 VSS sg13_lv_nmos m=1 w=870.00n l=130.00n ng=1 nrd=0 ++ nrs=0 +MN7 net023 E VSS VSS sg13_lv_nmos m=1 w=870.00n l=130.00n ng=1 nrd=0 ++ nrs=0 +MN4 net018 CP VSS VSS sg13_lv_nmos m=1 w=980.00n l=130.00n ng=1 nrd=0 ++ nrs=0 +MN0 CPN CP VSS VSS sg13_lv_nmos m=1 w=500.0n l=130.00n ng=1 nrd=0 nrs=0 +MP3 net08 QIN VDD VDD sg13_lv_pmos m=1 w=480.00n l=130.00n ng=1 nrd=0 ++ nrs=0 +MP2 QIN CPN net017 VDD sg13_lv_pmos m=1 w=480.00n l=130.00n ng=1 nrd=0 ++ nrs=0 +MP1 net017 net08 VDD VDD sg13_lv_pmos m=1 w=480.00n l=130.00n ng=1 ++ nrd=0 nrs=0 +MP0 CPN CP VDD VDD sg13_lv_pmos m=1 w=500.0n l=130.00n ng=1 nrd=0 nrs=0 +MP8 QIN CP net024 VDD sg13_lv_pmos m=1 w=975.000n l=130.00n ng=1 nrd=0 ++ nrs=0 +MP7 net024 E VDD VDD sg13_lv_pmos m=1 w=975.000n l=130.00n ng=1 nrd=0 ++ nrs=0 +MP4 net015 CP VDD VDD sg13_lv_pmos m=1 w=1.27u l=130.00n ng=1 nrd=0 ++ nrs=0 +MP6 Q net015 VDD VDD sg13_lv_pmos m=1 w=3.24u l=130.00n ng=2 nrd=0 ++ nrs=0 +MP5 net015 net08 VDD VDD sg13_lv_pmos m=1 w=1.27u l=130.00n ng=1 nrd=0 ++ nrs=0 +.ENDS +.SUBCKT RSC_IHPSG13_CBUFX8 A Z VDD VSS +MP0 net4 A VDD VDD sg13_lv_pmos m=1 w=3.24u l=130.00n ng=2 nrd=0 nrs=0 +MP1 Z net4 VDD VDD sg13_lv_pmos m=1 w=6.48u l=130.00n ng=4 nrd=0 nrs=0 +MN1 Z net4 VSS VSS sg13_lv_nmos m=1 w=2.82u l=130.00n ng=4 nrd=0 nrs=0 +MN0 net4 A VSS VSS sg13_lv_nmos m=1 w=1.41u l=130.00n ng=2 nrd=0 nrs=0 +.ENDS +.SUBCKT RSC_IHPSG13_CDLYX2 A Z VDD VSS +MN2 net4 A net9 VSS sg13_lv_nmos m=1 w=320.00n l=200.0n ng=1 nrd=0 nrs=0 +MN0 Z net4 VSS VSS sg13_lv_nmos m=1 w=705.000n l=130.00n ng=1 nrd=0 ++ nrs=0 +MN1 net9 A VSS VSS sg13_lv_nmos m=1 w=320.00n l=200.0n ng=1 nrd=0 nrs=0 +MP2 net4 A net10 VDD sg13_lv_pmos m=1 w=1.2u l=200.0n ng=1 nrd=0 nrs=0 +MP1 net10 A VDD VDD sg13_lv_pmos m=1 w=1.2u l=200.0n ng=1 nrd=0 nrs=0 +MP0 Z net4 VDD VDD sg13_lv_pmos m=1 w=1.62u l=130.00n ng=1 nrd=0 nrs=0 +.ENDS +.SUBCKT RSC_IHPSG13_MX2X2 A0 A1 S Z VDD VSS +MP6 Z net010 VDD VDD sg13_lv_pmos m=1 w=1.62u l=130.00n ng=1 nrd=0 ++ nrs=0 +MP4 SN S VDD VDD sg13_lv_pmos m=1 w=645.000n l=130.00n ng=1 nrd=0 nrs=0 +MP3 net010 SN net12 VDD sg13_lv_pmos m=1 w=985.000n l=130.00n ng=1 nrd=0 ++ nrs=0 +MP2 net12 A1 VDD VDD sg13_lv_pmos m=1 w=985.000n l=130.00n ng=1 nrd=0 ++ nrs=0 +MP1 net010 S net17 VDD sg13_lv_pmos m=1 w=985.000n l=130.00n ng=1 nrd=0 ++ nrs=0 +MP0 net17 A0 VDD VDD sg13_lv_pmos m=1 w=985.000n l=130.00n ng=1 nrd=0 ++ nrs=0 +MN6 Z net010 VSS VSS sg13_lv_nmos m=1 w=705.000n l=130.00n ng=1 nrd=0 ++ nrs=0 +MN5 SN S VSS VSS sg13_lv_nmos m=1 w=560.00n l=130.00n ng=1 nrd=0 nrs=0 +MN3 net13 A1 VSS VSS sg13_lv_nmos m=1 w=560.00n l=130.00n ng=1 nrd=0 ++ nrs=0 +MN2 net010 S net13 VSS sg13_lv_nmos m=1 w=560.00n l=130.00n ng=1 nrd=0 ++ nrs=0 +MN1 net15 A0 VSS VSS sg13_lv_nmos m=1 w=560.00n l=130.00n ng=1 nrd=0 ++ nrs=0 +MN0 net010 SN net15 VSS sg13_lv_nmos m=1 w=560.00n l=130.00n ng=1 nrd=0 ++ nrs=0 +.ENDS +.SUBCKT RSC_IHPSG13_AND2X2 A B Z VDD VSS +MN3 Z net6 VSS VSS sg13_lv_nmos m=1 w=980.00n l=130.00n ng=1 nrd=0 ++ nrs=0 +MN4 net9 B VSS VSS sg13_lv_nmos m=1 w=500.0n l=130.00n ng=1 nrd=0 nrs=0 +MN6 net6 A net9 VSS sg13_lv_nmos m=1 w=500.0n l=130.00n ng=1 nrd=0 nrs=0 +MP2 Z net6 VDD VDD sg13_lv_pmos m=1 w=1.62u l=130.00n ng=1 nrd=0 nrs=0 +MP0 net6 B VDD VDD sg13_lv_pmos m=1 w=860.00n l=130.00n ng=1 nrd=0 ++ nrs=0 +MP1 net6 A VDD VDD sg13_lv_pmos m=1 w=860.00n l=130.00n ng=1 nrd=0 ++ nrs=0 +.ENDS +.SUBCKT RSC_IHPSG13_TIEL Z VDD VSS +MN0 Z net2 VSS VSS sg13_lv_nmos m=1 w=480.00n l=130.00n ng=1 nrd=0 ++ nrs=0 +MP0 net2 net2 VDD VDD sg13_lv_pmos m=1 w=480.00n l=130.00n ng=1 nrd=0 ++ nrs=0 +.ENDS +.SUBCKT RSC_IHPSG13_XOR2X2 A B Z VDD VSS +MP8 net012 B net7 VDD sg13_lv_pmos m=1 w=825.000n l=130.00n ng=1 nrd=0 ++ nrs=0 +MP7 net011 net3 net012 VDD sg13_lv_pmos m=1 w=825.000n l=130.00n ng=1 ++ nrd=0 nrs=0 +MP6 Z net012 VDD VDD sg13_lv_pmos m=1 w=1.535u l=130.00n ng=1 nrd=0 ++ nrs=0 +MP2 net7 A VDD VDD sg13_lv_pmos m=1 w=825.000n l=130.00n ng=1 nrd=0 ++ nrs=0 +MP4 net011 net7 VDD VDD sg13_lv_pmos m=1 w=825.000n l=130.00n ng=1 ++ nrd=0 nrs=0 +MP5 net3 B VDD VDD sg13_lv_pmos m=1 w=580.00n l=130.00n ng=1 nrd=0 ++ nrs=0 +MN7 net012 B net011 VSS sg13_lv_nmos m=1 w=555.000n l=130.00n ng=1 nrd=0 ++ nrs=0 +MN6 net7 net3 net012 VSS sg13_lv_nmos m=1 w=555.000n l=130.00n ng=1 nrd=0 ++ nrs=0 +MN5 Z net012 VSS VSS sg13_lv_nmos m=1 w=775.000n l=130.00n ng=1 nrd=0 ++ nrs=0 +MN2 net7 A VSS VSS sg13_lv_nmos m=1 w=555.000n l=130.00n ng=1 nrd=0 ++ nrs=0 +MN4 net3 B VSS VSS sg13_lv_nmos m=1 w=480.00n l=130.00n ng=1 nrd=0 ++ nrs=0 +MN3 net011 net7 VSS VSS sg13_lv_nmos m=1 w=555.000n l=130.00n ng=1 ++ nrd=0 nrs=0 +.ENDS +.SUBCKT RSC_IHPSG13_OA12X1 A B C Z VDD VSS +MN2 net7 C VSS VSS sg13_lv_nmos m=1 w=980.00n l=130.00n ng=1 nrd=0 ++ nrs=0 +MN3 Z net17 VSS VSS sg13_lv_nmos m=1 w=500.0n l=130.00n ng=1 nrd=0 ++ nrs=0 +MN1 net17 B net7 VSS sg13_lv_nmos m=1 w=980.00n l=130.00n ng=1 nrd=0 nrs=0 +MN0 net17 A net7 VSS sg13_lv_nmos m=1 w=980.00n l=130.00n ng=1 nrd=0 nrs=0 +MP0 net24 A VDD VDD sg13_lv_pmos m=1 w=1.62u l=130.00n ng=1 nrd=0 nrs=0 +MP3 Z net17 VDD VDD sg13_lv_pmos m=1 w=905.000n l=130.00n ng=1 nrd=0 ++ nrs=0 +MP1 net17 B net24 VDD sg13_lv_pmos m=1 w=1.62u l=130.00n ng=1 nrd=0 nrs=0 +MP2 net17 C VDD VDD sg13_lv_pmos m=1 w=905.000n l=130.00n ng=1 nrd=0 ++ nrs=0 +.ENDS +.SUBCKT RM_IHPSG13_1024x32_c2_1P_CTRL ACLK_N BIST_CK_I BIST_CS_I BIST_EN BIST_RE_I ++ BIST_WE_I B_TIEL_O CK_I CS_I DCLK ECLK PULSE_H PULSE_L PULSE_O RCLK RE_I ++ ROW_CS WCLK WE_I VDD VSS +XI17 ck_regs we col_we VDD VSS / RSC_IHPSG13_DFNQX2 +XI16 ck_regs re col_re VDD VSS / RSC_IHPSG13_DFNQX2 +XI18 ck_regs cs net7 VDD VSS / RSC_IHPSG13_DFNQX2 +XI71 ACLK_N net012 PULSE_O VDD VSS / RSC_IHPSG13_DFNQX2 +XI77 col_we net9 net016 VDD VSS / RSC_IHPSG13_CNAND2X2 +XI76 col_re net9 net018 VDD VSS / RSC_IHPSG13_CNAND2X2 +XI15 ck_dly WEorREandCS aclk VDD VSS / RSC_IHPSG13_CGATEPX4 +XI14 ck WEandCS DCLK VDD VSS / RSC_IHPSG13_CGATEPX4 +XI60 net7 ROW_CS VDD VSS / RSC_IHPSG13_CBUFX8 +XI73 PULSE_O net012 VDD VSS / RSC_IHPSG13_CINVX2 +XI8 net9 net8 VDD VSS / RSC_IHPSG13_CINVX2 +XI64 ck ck_dly VDD VSS / RSC_IHPSG13_CDLYX2 +XI86 CS_I BIST_CS_I BIST_EN cs VDD VSS / RSC_IHPSG13_MX2X2 +XI87 CK_I BIST_CK_I BIST_EN ck VDD VSS / RSC_IHPSG13_MX2X2 +XI85 WE_I BIST_WE_I BIST_EN we VDD VSS / RSC_IHPSG13_MX2X2 +XI84 RE_I BIST_RE_I BIST_EN re VDD VSS / RSC_IHPSG13_MX2X2 +XI22 we cs WEandCS VDD VSS / RSC_IHPSG13_AND2X2 +XBM_TIEL B_TIEL_O VDD VSS / RSC_IHPSG13_TIEL +XI48 ck_dly ck_regs VDD VSS / RSC_IHPSG13_CINVX4 +XI81 net016 WCLK VDD VSS / RSC_IHPSG13_CINVX4 +XI80 net018 RCLK VDD VSS / RSC_IHPSG13_CINVX4 +XI78 net8 net020 VDD VSS / RSC_IHPSG13_CINVX4 +XI6 PULSE_L PULSE_H net9 VDD VSS / RSC_IHPSG13_XOR2X2 +XI79 net020 ECLK VDD VSS / RSC_IHPSG13_CINVX8 +XI63 aclk ACLK_N VDD VSS / RSC_IHPSG13_CINVX8 +XI21 re we cs WEorREandCS VDD VSS / RSC_IHPSG13_OA12X1 +.ENDS +.SUBCKT RM_IHPSG13_1024x32_c2_1P_COLDEC2 ACLK_N ADDR<1> ADDR<0> ADDR_COL<1> ADDR_COL<0> ++ ADDR_DEC<7> ADDR_DEC<6> ADDR_DEC<5> ADDR_DEC<4> ADDR_DEC<3> ADDR_DEC<2> ++ ADDR_DEC<1> ADDR_DEC<0> BIST_ADDR<1> BIST_ADDR<0> BIST_EN_I VDD VSS +XI14<5> VDD VSS / RSC_IHPSG13_FILLCAP4 +XI14<4> VDD VSS / RSC_IHPSG13_FILLCAP4 +XI14<3> VDD VSS / RSC_IHPSG13_FILLCAP4 +XI14<2> VDD VSS / RSC_IHPSG13_FILLCAP4 +XI14<1> VDD VSS / RSC_IHPSG13_FILLCAP4 +XDFF<1> BIST_EN_I BIST_ADDR<1> ACLK_N ADDR<1> padr_int<1> net6<0> VDD ++ VSS / RSC_IHPSG13_DFNQMX2IX1 +XDFF<0> BIST_EN_I BIST_ADDR<0> ACLK_N ADDR<0> padr_int<0> net6<1> VDD ++ VSS / RSC_IHPSG13_DFNQMX2IX1 +XI1<3> PADR<1> PADR<0> addr_n<3> VDD VSS / RSC_IHPSG13_NAND2X2 +XI1<2> PADR<1> NADR<0> addr_n<2> VDD VSS / RSC_IHPSG13_NAND2X2 +XI1<1> NADR<1> PADR<0> addr_n<1> VDD VSS / RSC_IHPSG13_NAND2X2 +XI1<0> NADR<1> NADR<0> addr_n<0> VDD VSS / RSC_IHPSG13_NAND2X2 +XI16<37> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI16<36> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI16<35> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI16<34> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI16<33> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI16<32> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI16<31> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI16<30> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI16<29> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI16<28> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI16<27> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI16<26> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI16<25> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI16<24> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI16<23> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI16<22> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI16<21> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI16<20> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI16<19> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI16<18> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI16<17> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI16<16> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI16<15> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI16<14> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI16<13> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI16<12> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI16<11> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI16<10> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI16<9> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI16<8> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI16<7> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI16<6> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI16<5> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI16<4> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI16<3> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI16<2> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI16<1> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI3<1> padr_int<1> NADR<1> VDD VSS / RSC_IHPSG13_INVX2 +XI3<0> padr_int<0> NADR<0> VDD VSS / RSC_IHPSG13_INVX2 +XI13<1> NADR<1> PADR<1> VDD VSS / RSC_IHPSG13_INVX2 +XI13<0> NADR<0> PADR<0> VDD VSS / RSC_IHPSG13_INVX2 +XI2<3> addr_n<3> ADDR_DEC<3> VDD VSS / RSC_IHPSG13_INVX2 +XI2<2> addr_n<2> ADDR_DEC<2> VDD VSS / RSC_IHPSG13_INVX2 +XI2<1> addr_n<1> ADDR_DEC<1> VDD VSS / RSC_IHPSG13_INVX2 +XI2<0> addr_n<0> ADDR_DEC<0> VDD VSS / RSC_IHPSG13_INVX2 +XI15<1> ADDR_COL<1> VDD VSS / RSC_IHPSG13_TIEL +XI15<0> ADDR_COL<0> VDD VSS / RSC_IHPSG13_TIEL +XI17<3> ADDR_DEC<7> VDD VSS / RSC_IHPSG13_TIEL +XI17<2> ADDR_DEC<6> VDD VSS / RSC_IHPSG13_TIEL +XI17<1> ADDR_DEC<5> VDD VSS / RSC_IHPSG13_TIEL +XI17<0> ADDR_DEC<4> VDD VSS / RSC_IHPSG13_TIEL +.ENDS +.SUBCKT RSC_IHPSG13_NOR2X2 A B Z VDD VSS +MP1 Z B net9 VDD sg13_lv_pmos m=1 w=1.62u l=130.00n ng=1 nrd=0 nrs=0 +MP0 net9 A VDD VDD sg13_lv_pmos m=1 w=1.62u l=130.00n ng=1 nrd=0 nrs=0 +MN0 Z B VSS VSS sg13_lv_nmos m=1 w=980.00n l=130.00n ng=1 nrd=0 nrs=0 +MN1 Z A VSS VSS sg13_lv_nmos m=1 w=980.00n l=130.00n ng=1 nrd=0 nrs=0 +.ENDS +.SUBCKT RSC_IHPSG13_CINVX4_WN A Z VDD VSS +MN0 Z A VSS VSS sg13_lv_nmos m=1 w=705.000n l=130.00n ng=1 nrd=0 nrs=0 +MP0 Z A VDD VDD sg13_lv_pmos m=1 w=3.24u l=130.00n ng=2 nrd=0 nrs=0 +.ENDS +.SUBCKT RM_IHPSG13_1024x32_c2_1P_BLDRV BLC BLC_SEL BLT BLT_SEL PRE_N SEL_P WR_ONE WR_ZERO ++ VDD VSS +XCDEC SEL_P WR_ZERO BLC_PMOS_DRIVE VDD VSS / RSC_IHPSG13_NAND2X2 +XTDEC SEL_P WR_ONE BLT_PMOS_DRIVE VDD VSS / RSC_IHPSG13_NAND2X2 +MTWN BLT BLT_NMOS_DRIVE VSS VSS sg13_lv_nmos m=1 w=4.82u l=130.00n ++ ng=2 nrd=0 nrs=0 +MCWN BLC BLC_NMOS_DRIVE VSS VSS sg13_lv_nmos m=1 w=4.82u l=130.00n ++ ng=2 nrd=0 nrs=0 +MCWP BLC BLC_PMOS_DRIVE VDD VDD sg13_lv_pmos m=1 w=1.5u l=130.00n ng=1 ++ nrd=0 nrs=0 +MTWP BLT BLT_PMOS_DRIVE VDD VDD sg13_lv_pmos m=1 w=1.5u l=130.00n ng=1 ++ nrd=0 nrs=0 +MTSP BLT_SEL SEL_N BLT VDD sg13_lv_pmos m=1 w=1.5u l=130.00n ng=1 nrd=0 ++ nrs=0 +MTPR BLT PRE_N VDD VDD sg13_lv_pmos m=1 w=3.000u l=130.00n ng=2 nrd=0 ++ nrs=0 +MCSP BLC_SEL SEL_N BLC VDD sg13_lv_pmos m=1 w=1.5u l=130.00n ng=1 nrd=0 ++ nrs=0 +MCPR BLC PRE_N VDD VDD sg13_lv_pmos m=1 w=3.000u l=130.00n ng=2 nrd=0 ++ nrs=0 +XI86 SEL_P SEL_N VDD VSS / RSC_IHPSG13_INVX2 +XTINV BLC_PMOS_DRIVE BLT_NMOS_DRIVE VDD VSS / RSC_IHPSG13_INVX2 +XCINV BLT_PMOS_DRIVE BLC_NMOS_DRIVE VDD VSS / RSC_IHPSG13_INVX2 +.ENDS +.SUBCKT RSC_IHPSG13_TIEH Z VDD VSS +MN0 net2 net2 VSS VSS sg13_lv_nmos m=1 w=480.00n l=130.00n ng=1 nrd=0 ++ nrs=0 +MP0 Z net2 VDD VDD sg13_lv_pmos m=1 w=480.00n l=130.00n ng=1 nrd=0 ++ nrs=0 +.ENDS +.SUBCKT RSC_IHPSG13_MET3RES A B +R0 B A lvsres w=2.6e-07 l=6e-07 +.ENDS +.SUBCKT RSC_IHPSG13_DFPQD_MSAFFX2 CP DN DP QN QP VDD VSS +MN12 SN RN DIFFP VSS sg13_lv_nmos m=1 w=2.4u l=200.0n ng=2 nrd=0 nrs=0 +MN13 TAIL CP VSS VSS sg13_lv_nmos m=1 w=2.4u l=130.00n ng=2 nrd=0 nrs=0 +MN9 DIFFP DP TAIL VSS sg13_lv_nmos m=1 w=2.4u l=200.0n ng=2 nrd=0 nrs=0 +MN10 DIFFN DN TAIL VSS sg13_lv_nmos m=1 w=2.4u l=200.0n ng=2 nrd=0 nrs=0 +MN11 RN SN DIFFN VSS sg13_lv_nmos m=1 w=2.4u l=200.0n ng=2 nrd=0 nrs=0 +MN19 net33 SN VSS VSS sg13_lv_nmos m=1 w=980.00n l=130.00n ng=1 nrd=0 ++ nrs=0 +MN20 QN QP net37 VSS sg13_lv_nmos m=1 w=980.00n l=130.00n ng=1 nrd=0 nrs=0 +MN18 net37 RN VSS VSS sg13_lv_nmos m=1 w=980.00n l=130.00n ng=1 nrd=0 ++ nrs=0 +MN17 QP QN net33 VSS sg13_lv_nmos m=1 w=980.00n l=130.00n ng=1 nrd=0 nrs=0 +MP15 SN RN VDD VDD sg13_lv_pmos m=1 w=800.0n l=130.00n ng=1 nrd=0 nrs=0 +MP16 RN CP VDD VDD sg13_lv_pmos m=1 w=800.0n l=130.00n ng=1 nrd=0 nrs=0 +MP14 DIFFP CP VDD VDD sg13_lv_pmos m=1 w=800.0n l=130.00n ng=1 nrd=0 ++ nrs=0 +MP12 RN SN VDD VDD sg13_lv_pmos m=1 w=800.0n l=130.00n ng=1 nrd=0 nrs=0 +MP13 DIFFN CP VDD VDD sg13_lv_pmos m=1 w=800.0n l=130.00n ng=1 nrd=0 ++ nrs=0 +MP11 SN CP VDD VDD sg13_lv_pmos m=1 w=800.0n l=130.00n ng=1 nrd=0 nrs=0 +MP19 QN QP VDD VDD sg13_lv_pmos m=1 w=900.0n l=130.00n ng=1 nrd=0 nrs=0 +MP20 QP SN VDD VDD sg13_lv_pmos m=1 w=1.8u l=130.00n ng=2 nrd=0 nrs=0 +MP18 QN RN VDD VDD sg13_lv_pmos m=1 w=1.8u l=130.00n ng=2 nrd=0 nrs=0 +MP17 QP QN VDD VDD sg13_lv_pmos m=1 w=900.0n l=130.00n ng=1 nrd=0 nrs=0 +.ENDS +.SUBCKT RSC_IHPSG13_CBUFX2 A Z VDD VSS +MN1 Z net4 VSS VSS sg13_lv_nmos m=1 w=705.000n l=130.00n ng=1 nrd=0 ++ nrs=0 +MN0 net4 A VSS VSS sg13_lv_nmos m=1 w=540.00n l=130.00n ng=1 nrd=0 ++ nrs=0 +MP1 Z net4 VDD VDD sg13_lv_pmos m=1 w=1.62u l=130.00n ng=1 nrd=0 nrs=0 +MP0 net4 A VDD VDD sg13_lv_pmos m=1 w=1.1u l=130.00n ng=1 nrd=0 nrs=0 +.ENDS +.SUBCKT RSC_IHPSG13_INVX4 A Z VDD VSS +MN0 Z A VSS VSS sg13_lv_nmos m=1 w=1.96u l=130.00n ng=2 nrd=0 nrs=0 +MP0 Z A VDD VDD sg13_lv_pmos m=1 w=3.24u l=130.00n ng=2 nrd=0 nrs=0 +.ENDS +.SUBCKT RM_IHPSG13_1024x32_c2_1P_COLCTRL2 A_ADDR_DEC<3> A_ADDR_DEC<2> A_ADDR_DEC<1> ++ A_ADDR_DEC<0> A_BIST_BM_I A_BIST_DW_I A_BIST_EN_I A_BLC<3> A_BLC<2> A_BLC<1> ++ A_BLC<0> A_BLT<3> A_BLT<2> A_BLT<1> A_BLT<0> A_BM_I A_DCLK_B_L A_DCLK_B_R ++ A_DCLK_L A_DCLK_R A_DR_O A_DW_I A_RCLK_B_L A_RCLK_B_R A_RCLK_L A_RCLK_R ++ A_TIEH_O A_WCLK_B_L A_WCLK_B_R A_WCLK_L A_WCLK_R VDD VSS +XA_DREG A_BIST_EN_I A_BIST_DW_I A_DCLK_B_L A_DW_I A_DI_R net22 VDD VSS ++ / RSC_IHPSG13_DFNQMX2IX1 +XA_BREG A_BIST_EN_I A_BIST_BM_I A_DCLK_B_L A_BM_I A_BM_R net23 VDD VSS ++ / RSC_IHPSG13_DFNQMX2IX1 +XA_CAPS<5> VDD VSS / RSC_IHPSG13_FILLCAP4 +XA_CAPS<4> VDD VSS / RSC_IHPSG13_FILLCAP4 +XA_CAPS<3> VDD VSS / RSC_IHPSG13_FILLCAP4 +XA_CAPS<2> VDD VSS / RSC_IHPSG13_FILLCAP4 +XA_CAPS<1> VDD VSS / RSC_IHPSG13_FILLCAP4 +XA_I80 A_WCLK_B_R A_RCLK_B_R net21 VDD VSS / RSC_IHPSG13_AND2X2 +XA_I75 A_DI_R A_DO_WRITE_P A_WR_ONE VDD VSS / RSC_IHPSG13_AND2X2 +XA_I76 A_DI_N A_DO_WRITE_P A_WR_ZERO VDD VSS / RSC_IHPSG13_AND2X2 +XA_I44 A_WCLK_B_R A_BM_N A_DO_WRITE_P VDD VSS / RSC_IHPSG13_NOR2X2 +XA_I81 net21 A_PRE_N VDD VSS / RSC_IHPSG13_CINVX4_WN +XA_BLTMUX<3> A_BLC<3> A_BLC_SEL A_BLT<3> A_BLT_SEL A_PRE_N A_ADDR_DEC<3> ++ A_WR_ONE A_WR_ZERO VDD VSS / RM_IHPSG13_1024x32_c2_1P_BLDRV +XA_BLTMUX<2> A_BLC<2> A_BLC_SEL A_BLT<2> A_BLT_SEL A_PRE_N A_ADDR_DEC<2> ++ A_WR_ONE A_WR_ZERO VDD VSS / RM_IHPSG13_1024x32_c2_1P_BLDRV +XA_BLTMUX<1> A_BLC<1> A_BLC_SEL A_BLT<1> A_BLT_SEL A_PRE_N A_ADDR_DEC<1> ++ A_WR_ONE A_WR_ZERO VDD VSS / RM_IHPSG13_1024x32_c2_1P_BLDRV +XA_BLTMUX<0> A_BLC<0> A_BLC_SEL A_BLT<0> A_BLT_SEL A_PRE_N A_ADDR_DEC<0> ++ A_WR_ONE A_WR_ZERO VDD VSS / RM_IHPSG13_1024x32_c2_1P_BLDRV +XA_BM_TIEH A_TIEH_O VDD VSS / RSC_IHPSG13_TIEH +XA_I89 A_DCLK_B_L A_DCLK_B_R / RSC_IHPSG13_MET3RES +XA_I88 A_DCLK_L A_DCLK_R / RSC_IHPSG13_MET3RES +XA_I87 A_WCLK_L A_WCLK_R / RSC_IHPSG13_MET3RES +XA_I91 A_RCLK_B_R A_RCLK_B_L / RSC_IHPSG13_MET3RES +XA_R2 A_RCLK_R A_RCLK_L / RSC_IHPSG13_MET3RES +XA_I90 A_WCLK_B_R A_WCLK_B_L / RSC_IHPSG13_MET3RES +XA_ISENSE A_SAE A_BLC_SEL A_BLT_SEL net19 net20 VDD VSS / ++ RSC_IHPSG13_DFPQD_MSAFFX2 +XA_I78 A_RCLK_B_R A_SAE VDD VSS / RSC_IHPSG13_CBUFX2 +XA_I83 A_BM_R A_BM_N VDD VSS / RSC_IHPSG13_INVX2 +XA_I49 A_DI_R A_DI_N VDD VSS / RSC_IHPSG13_INVX2 +XA_I51 net19 A_DR_O VDD VSS / RSC_IHPSG13_INVX4 +XA_I69 A_DCLK_L A_DCLK_B_L VDD VSS / RSC_IHPSG13_CINVX2 +XA_I50 A_WCLK_L A_WCLK_B_R VDD VSS / RSC_IHPSG13_CINVX2 +XA_EBUF A_RCLK_R A_RCLK_B_R VDD VSS / RSC_IHPSG13_CINVX2 +.ENDS +.SUBCKT RM_IHPSG13_1024x32_c2_1P_COLDRV13_FILL4 VDD VSS +XI0<9> VDD VSS / RSC_IHPSG13_FILLCAP4 +XI0<8> VDD VSS / RSC_IHPSG13_FILLCAP4 +XI0<7> VDD VSS / RSC_IHPSG13_FILLCAP4 +XI0<6> VDD VSS / RSC_IHPSG13_FILLCAP4 +XI0<5> VDD VSS / RSC_IHPSG13_FILLCAP4 +XI0<4> VDD VSS / RSC_IHPSG13_FILLCAP4 +XI0<3> VDD VSS / RSC_IHPSG13_FILLCAP4 +XI0<2> VDD VSS / RSC_IHPSG13_FILLCAP4 +XI0<1> VDD VSS / RSC_IHPSG13_FILLCAP4 +.ENDS +.SUBCKT RM_IHPSG13_1024x32_c2_1P_COLDRV13_FILL4C2 VDD VSS +XI0<2> VDD VSS / RSC_IHPSG13_FILLCAP4 +XI0<1> VDD VSS / RSC_IHPSG13_FILLCAP4 +.ENDS + + +.SUBCKT RM_IHPSG13_1024x32_c2_1P_COLDEC4 ACLK_N ADDR<3> ADDR<2> ADDR<1> ADDR<0> ++ ADDR_COL<1> ADDR_COL<0> ADDR_DEC<7> ADDR_DEC<6> ADDR_DEC<5> ADDR_DEC<4> ++ ADDR_DEC<3> ADDR_DEC<2> ADDR_DEC<1> ADDR_DEC<0> BIST_ADDR<3> BIST_ADDR<2> ++ BIST_ADDR<1> BIST_ADDR<0> BIST_EN_I VDD VSS +XI15 ADDR_COL<1> VDD VSS / RSC_IHPSG13_TIEL +XI14 addr_int ADDR_COL<0> VDD VSS / RSC_IHPSG13_CBUFX2 +XDFF<3> BIST_EN_I BIST_ADDR<3> ACLK_N ADDR<3> addr_int net7<0> VDD VSS ++ / RSC_IHPSG13_DFNQMX2IX1 +XDFF<2> BIST_EN_I BIST_ADDR<2> ACLK_N ADDR<2> padr_int<2> net7<1> VDD ++ VSS / RSC_IHPSG13_DFNQMX2IX1 +XDFF<1> BIST_EN_I BIST_ADDR<1> ACLK_N ADDR<1> padr_int<1> net7<2> VDD ++ VSS / RSC_IHPSG13_DFNQMX2IX1 +XDFF<0> BIST_EN_I BIST_ADDR<0> ACLK_N ADDR<0> padr_int<0> net7<3> VDD ++ VSS / RSC_IHPSG13_DFNQMX2IX1 +XI1<7> PADR<0> PADR<1> PADR<2> addr_n<7> VDD VSS / RSC_IHPSG13_NAND3X2 +XI1<6> NADR<0> PADR<1> PADR<2> addr_n<6> VDD VSS / RSC_IHPSG13_NAND3X2 +XI1<5> PADR<0> NADR<1> PADR<2> addr_n<5> VDD VSS / RSC_IHPSG13_NAND3X2 +XI1<4> NADR<0> NADR<1> PADR<2> addr_n<4> VDD VSS / RSC_IHPSG13_NAND3X2 +XI1<3> PADR<0> PADR<1> NADR<2> addr_n<3> VDD VSS / RSC_IHPSG13_NAND3X2 +XI1<2> NADR<0> PADR<1> NADR<2> addr_n<2> VDD VSS / RSC_IHPSG13_NAND3X2 +XI1<1> PADR<0> NADR<1> NADR<2> addr_n<1> VDD VSS / RSC_IHPSG13_NAND3X2 +XI1<0> NADR<0> NADR<1> NADR<2> addr_n<0> VDD VSS / RSC_IHPSG13_NAND3X2 +XI13<2> NADR<2> PADR<2> VDD VSS / RSC_IHPSG13_INVX2 +XI13<1> NADR<1> PADR<1> VDD VSS / RSC_IHPSG13_INVX2 +XI13<0> NADR<0> PADR<0> VDD VSS / RSC_IHPSG13_INVX2 +XI3<2> padr_int<2> NADR<2> VDD VSS / RSC_IHPSG13_INVX2 +XI3<1> padr_int<1> NADR<1> VDD VSS / RSC_IHPSG13_INVX2 +XI3<0> padr_int<0> NADR<0> VDD VSS / RSC_IHPSG13_INVX2 +XI2<7> addr_n<7> ADDR_DEC<7> VDD VSS / RSC_IHPSG13_INVX2 +XI2<6> addr_n<6> ADDR_DEC<6> VDD VSS / RSC_IHPSG13_INVX2 +XI2<5> addr_n<5> ADDR_DEC<5> VDD VSS / RSC_IHPSG13_INVX2 +XI2<4> addr_n<4> ADDR_DEC<4> VDD VSS / RSC_IHPSG13_INVX2 +XI2<3> addr_n<3> ADDR_DEC<3> VDD VSS / RSC_IHPSG13_INVX2 +XI2<2> addr_n<2> ADDR_DEC<2> VDD VSS / RSC_IHPSG13_INVX2 +XI2<1> addr_n<1> ADDR_DEC<1> VDD VSS / RSC_IHPSG13_INVX2 +XI2<0> addr_n<0> ADDR_DEC<0> VDD VSS / RSC_IHPSG13_INVX2 +XI16<3> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI16<2> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI16<1> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI17<2> VDD VSS / RSC_IHPSG13_FILLCAP4 +XI17<1> VDD VSS / RSC_IHPSG13_FILLCAP4 +.ENDS +.SUBCKT RSC_IHPSG13_AND2X4 A B Z VDD VSS +MN3 Z net6 VSS VSS sg13_lv_nmos m=1 w=1.96u l=130.00n ng=2 nrd=0 nrs=0 +MN4 net9 B VSS VSS sg13_lv_nmos m=1 w=500.0n l=130.00n ng=1 nrd=0 nrs=0 +MN6 net6 A net9 VSS sg13_lv_nmos m=1 w=500.0n l=130.00n ng=1 nrd=0 nrs=0 +MP2 Z net6 VDD VDD sg13_lv_pmos m=1 w=3.24u l=130.00n ng=2 nrd=0 nrs=0 +MP0 net6 B VDD VDD sg13_lv_pmos m=1 w=860.00n l=130.00n ng=1 nrd=0 ++ nrs=0 +MP1 net6 A VDD VDD sg13_lv_pmos m=1 w=860.00n l=130.00n ng=1 nrd=0 ++ nrs=0 +.ENDS +.SUBCKT RM_IHPSG13_1024x32_c2_1P_COLCTRL4 A_ADDR_COL A_ADDR_DEC<7> A_ADDR_DEC<6> ++ A_ADDR_DEC<5> A_ADDR_DEC<4> A_ADDR_DEC<3> A_ADDR_DEC<2> A_ADDR_DEC<1> ++ A_ADDR_DEC<0> A_BIST_BM_I A_BIST_DW_I A_BIST_EN_I A_BLC<15> A_BLC<14> ++ A_BLC<13> A_BLC<12> A_BLC<11> A_BLC<10> A_BLC<9> A_BLC<8> A_BLC<7> A_BLC<6> ++ A_BLC<5> A_BLC<4> A_BLC<3> A_BLC<2> A_BLC<1> A_BLC<0> A_BLT<15> A_BLT<14> ++ A_BLT<13> A_BLT<12> A_BLT<11> A_BLT<10> A_BLT<9> A_BLT<8> A_BLT<7> A_BLT<6> ++ A_BLT<5> A_BLT<4> A_BLT<3> A_BLT<2> A_BLT<1> A_BLT<0> A_BM_I A_DCLK_B_L ++ A_DCLK_B_R A_DCLK_L A_DCLK_R A_DR_O A_DW_I A_RCLK_B_L A_RCLK_B_R A_RCLK_L ++ A_RCLK_R A_TIEH_O A_WCLK_B_L A_WCLK_B_R A_WCLK_L A_WCLK_R VDD VSS +XA_I80 A_WCLK_B_L A_RCLK_B_L net21 VDD VSS / RSC_IHPSG13_AND2X2 +XA_I76 A_DO_WRITE_P A_DI_N A_WR_ZERO VDD VSS / RSC_IHPSG13_AND2X4 +XA_I75 A_DI_R A_DO_WRITE_P A_WR_ONE VDD VSS / RSC_IHPSG13_AND2X4 +XA_CAPS<8> VDD VSS / RSC_IHPSG13_FILLCAP4 +XA_CAPS<7> VDD VSS / RSC_IHPSG13_FILLCAP4 +XA_CAPS<6> VDD VSS / RSC_IHPSG13_FILLCAP4 +XA_CAPS<5> VDD VSS / RSC_IHPSG13_FILLCAP4 +XA_CAPS<4> VDD VSS / RSC_IHPSG13_FILLCAP4 +XA_CAPS<3> VDD VSS / RSC_IHPSG13_FILLCAP4 +XA_CAPS<2> VDD VSS / RSC_IHPSG13_FILLCAP4 +XA_CAPS<1> VDD VSS / RSC_IHPSG13_FILLCAP4 +XA_I69 A_DCLK_L A_DCLK_B_L VDD VSS / RSC_IHPSG13_CINVX4 +XA_I50 A_WCLK_L A_WCLK_B_L VDD VSS / RSC_IHPSG13_CINVX4 +XA_EBUF A_RCLK_L A_RCLK_B_L VDD VSS / RSC_IHPSG13_CINVX4 +XA_INV<1> A_N0 A_P0 VDD VSS / RSC_IHPSG13_CINVX4 +XA_INV<0> A_ADDR_COL A_N0 VDD VSS / RSC_IHPSG13_CINVX4 +XA_I81<1> net21 A_PRE_N VDD VSS / RSC_IHPSG13_CINVX4_WN +XA_I81<0> net21 A_PRE_N VDD VSS / RSC_IHPSG13_CINVX4_WN +XA_BLTMUX<15> A_BLC<15> A_BLC_SEL A_BLT<15> A_BLT_SEL A_PRE_N A_SEL_P<15> ++ A_WR_ONE A_WR_ZERO VDD VSS / RM_IHPSG13_1024x32_c2_1P_BLDRV +XA_BLTMUX<14> A_BLC<14> A_BLC_SEL A_BLT<14> A_BLT_SEL A_PRE_N A_SEL_P<14> ++ A_WR_ONE A_WR_ZERO VDD VSS / RM_IHPSG13_1024x32_c2_1P_BLDRV +XA_BLTMUX<13> A_BLC<13> A_BLC_SEL A_BLT<13> A_BLT_SEL A_PRE_N A_SEL_P<13> ++ A_WR_ONE A_WR_ZERO VDD VSS / RM_IHPSG13_1024x32_c2_1P_BLDRV +XA_BLTMUX<12> A_BLC<12> A_BLC_SEL A_BLT<12> A_BLT_SEL A_PRE_N A_SEL_P<12> ++ A_WR_ONE A_WR_ZERO VDD VSS / RM_IHPSG13_1024x32_c2_1P_BLDRV +XA_BLTMUX<11> A_BLC<11> A_BLC_SEL A_BLT<11> A_BLT_SEL A_PRE_N A_SEL_P<11> ++ A_WR_ONE A_WR_ZERO VDD VSS / RM_IHPSG13_1024x32_c2_1P_BLDRV +XA_BLTMUX<10> A_BLC<10> A_BLC_SEL A_BLT<10> A_BLT_SEL A_PRE_N A_SEL_P<10> ++ A_WR_ONE A_WR_ZERO VDD VSS / RM_IHPSG13_1024x32_c2_1P_BLDRV +XA_BLTMUX<9> A_BLC<9> A_BLC_SEL A_BLT<9> A_BLT_SEL A_PRE_N A_SEL_P<9> A_WR_ONE ++ A_WR_ZERO VDD VSS / RM_IHPSG13_1024x32_c2_1P_BLDRV +XA_BLTMUX<8> A_BLC<8> A_BLC_SEL A_BLT<8> A_BLT_SEL A_PRE_N A_SEL_P<8> A_WR_ONE ++ A_WR_ZERO VDD VSS / RM_IHPSG13_1024x32_c2_1P_BLDRV +XA_BLTMUX<7> A_BLC<7> A_BLC_SEL A_BLT<7> A_BLT_SEL A_PRE_N A_SEL_P<7> A_WR_ONE ++ A_WR_ZERO VDD VSS / RM_IHPSG13_1024x32_c2_1P_BLDRV +XA_BLTMUX<6> A_BLC<6> A_BLC_SEL A_BLT<6> A_BLT_SEL A_PRE_N A_SEL_P<6> A_WR_ONE ++ A_WR_ZERO VDD VSS / RM_IHPSG13_1024x32_c2_1P_BLDRV +XA_BLTMUX<5> A_BLC<5> A_BLC_SEL A_BLT<5> A_BLT_SEL A_PRE_N A_SEL_P<5> A_WR_ONE ++ A_WR_ZERO VDD VSS / RM_IHPSG13_1024x32_c2_1P_BLDRV +XA_BLTMUX<4> A_BLC<4> A_BLC_SEL A_BLT<4> A_BLT_SEL A_PRE_N A_SEL_P<4> A_WR_ONE ++ A_WR_ZERO VDD VSS / RM_IHPSG13_1024x32_c2_1P_BLDRV +XA_BLTMUX<3> A_BLC<3> A_BLC_SEL A_BLT<3> A_BLT_SEL A_PRE_N A_SEL_P<3> A_WR_ONE ++ A_WR_ZERO VDD VSS / RM_IHPSG13_1024x32_c2_1P_BLDRV +XA_BLTMUX<2> A_BLC<2> A_BLC_SEL A_BLT<2> A_BLT_SEL A_PRE_N A_SEL_P<2> A_WR_ONE ++ A_WR_ZERO VDD VSS / RM_IHPSG13_1024x32_c2_1P_BLDRV +XA_BLTMUX<1> A_BLC<1> A_BLC_SEL A_BLT<1> A_BLT_SEL A_PRE_N A_SEL_P<1> A_WR_ONE ++ A_WR_ZERO VDD VSS / RM_IHPSG13_1024x32_c2_1P_BLDRV +XA_BLTMUX<0> A_BLC<0> A_BLC_SEL A_BLT<0> A_BLT_SEL A_PRE_N A_SEL_P<0> A_WR_ONE ++ A_WR_ZERO VDD VSS / RM_IHPSG13_1024x32_c2_1P_BLDRV +XA_R2 A_RCLK_L A_RCLK_R / RSC_IHPSG13_MET3RES +XA_I87 A_WCLK_L A_WCLK_R / RSC_IHPSG13_MET3RES +XA_I88 A_DCLK_L A_DCLK_R / RSC_IHPSG13_MET3RES +XA_I89 A_DCLK_B_L A_DCLK_B_R / RSC_IHPSG13_MET3RES +XA_I90 A_WCLK_B_L A_WCLK_B_R / RSC_IHPSG13_MET3RES +XA_I91 A_RCLK_B_L A_RCLK_B_R / RSC_IHPSG13_MET3RES +XA_ISENSE A_SAE A_BLC_SEL A_BLT_SEL net19 net20 VDD VSS / ++ RSC_IHPSG13_DFPQD_MSAFFX2 +XA_I51 net19 A_DR_O VDD VSS / RSC_IHPSG13_INVX4 +XA_I78 A_RCLK_B_L A_SAE VDD VSS / RSC_IHPSG13_CBUFX2 +XA_DREG A_BIST_EN_I A_BIST_DW_I A_DCLK_B_L A_DW_I A_DI_R net22 VDD VSS ++ / RSC_IHPSG13_DFNQMX2IX1 +XA_BREG A_BIST_EN_I A_BIST_BM_I A_DCLK_B_L A_BM_I A_BM_R net24 VDD VSS ++ / RSC_IHPSG13_DFNQMX2IX1 +XA_DEC3INV<15> net23<0> A_SEL_P<15> VDD VSS / RSC_IHPSG13_INVX2 +XA_DEC3INV<14> net23<1> A_SEL_P<14> VDD VSS / RSC_IHPSG13_INVX2 +XA_DEC3INV<13> net23<2> A_SEL_P<13> VDD VSS / RSC_IHPSG13_INVX2 +XA_DEC3INV<12> net23<3> A_SEL_P<12> VDD VSS / RSC_IHPSG13_INVX2 +XA_DEC3INV<11> net23<4> A_SEL_P<11> VDD VSS / RSC_IHPSG13_INVX2 +XA_DEC3INV<10> net23<5> A_SEL_P<10> VDD VSS / RSC_IHPSG13_INVX2 +XA_DEC3INV<9> net23<6> A_SEL_P<9> VDD VSS / RSC_IHPSG13_INVX2 +XA_DEC3INV<8> net23<7> A_SEL_P<8> VDD VSS / RSC_IHPSG13_INVX2 +XA_DEC3INV<7> net23<8> A_SEL_P<7> VDD VSS / RSC_IHPSG13_INVX2 +XA_DEC3INV<6> net23<9> A_SEL_P<6> VDD VSS / RSC_IHPSG13_INVX2 +XA_DEC3INV<5> net23<10> A_SEL_P<5> VDD VSS / RSC_IHPSG13_INVX2 +XA_DEC3INV<4> net23<11> A_SEL_P<4> VDD VSS / RSC_IHPSG13_INVX2 +XA_DEC3INV<3> net23<12> A_SEL_P<3> VDD VSS / RSC_IHPSG13_INVX2 +XA_DEC3INV<2> net23<13> A_SEL_P<2> VDD VSS / RSC_IHPSG13_INVX2 +XA_DEC3INV<1> net23<14> A_SEL_P<1> VDD VSS / RSC_IHPSG13_INVX2 +XA_DEC3INV<0> net23<15> A_SEL_P<0> VDD VSS / RSC_IHPSG13_INVX2 +XA_I83 A_BM_R A_BM_N VDD VSS / RSC_IHPSG13_INVX2 +XA_I49 A_DI_R A_DI_N VDD VSS / RSC_IHPSG13_INVX2 +XA_I70<4> VDD VSS / RSC_IHPSG13_FILLCAP8 +XA_I70<3> VDD VSS / RSC_IHPSG13_FILLCAP8 +XA_I70<2> VDD VSS / RSC_IHPSG13_FILLCAP8 +XA_I70<1> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI73<14> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI73<13> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI73<12> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI73<11> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI73<10> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI73<9> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI73<8> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI73<7> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI73<6> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI73<5> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI73<4> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI73<3> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI73<2> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI73<1> VDD VSS / RSC_IHPSG13_FILLCAP8 +XA_I44 A_BM_N A_WCLK_B_L A_DO_WRITE_P VDD VSS / RSC_IHPSG13_NOR2X2 +XA_DEC3<15> A_P0 A_ADDR_DEC<7> net23<0> VDD VSS / RSC_IHPSG13_NAND2X2 +XA_DEC3<14> A_P0 A_ADDR_DEC<6> net23<1> VDD VSS / RSC_IHPSG13_NAND2X2 +XA_DEC3<13> A_P0 A_ADDR_DEC<5> net23<2> VDD VSS / RSC_IHPSG13_NAND2X2 +XA_DEC3<12> A_P0 A_ADDR_DEC<4> net23<3> VDD VSS / RSC_IHPSG13_NAND2X2 +XA_DEC3<11> A_P0 A_ADDR_DEC<3> net23<4> VDD VSS / RSC_IHPSG13_NAND2X2 +XA_DEC3<10> A_P0 A_ADDR_DEC<2> net23<5> VDD VSS / RSC_IHPSG13_NAND2X2 +XA_DEC3<9> A_P0 A_ADDR_DEC<1> net23<6> VDD VSS / RSC_IHPSG13_NAND2X2 +XA_DEC3<8> A_P0 A_ADDR_DEC<0> net23<7> VDD VSS / RSC_IHPSG13_NAND2X2 +XA_DEC3<7> A_N0 A_ADDR_DEC<7> net23<8> VDD VSS / RSC_IHPSG13_NAND2X2 +XA_DEC3<6> A_N0 A_ADDR_DEC<6> net23<9> VDD VSS / RSC_IHPSG13_NAND2X2 +XA_DEC3<5> A_N0 A_ADDR_DEC<5> net23<10> VDD VSS / RSC_IHPSG13_NAND2X2 +XA_DEC3<4> A_N0 A_ADDR_DEC<4> net23<11> VDD VSS / RSC_IHPSG13_NAND2X2 +XA_DEC3<3> A_N0 A_ADDR_DEC<3> net23<12> VDD VSS / RSC_IHPSG13_NAND2X2 +XA_DEC3<2> A_N0 A_ADDR_DEC<2> net23<13> VDD VSS / RSC_IHPSG13_NAND2X2 +XA_DEC3<1> A_N0 A_ADDR_DEC<1> net23<14> VDD VSS / RSC_IHPSG13_NAND2X2 +XA_DEC3<0> A_N0 A_ADDR_DEC<0> net23<15> VDD VSS / RSC_IHPSG13_NAND2X2 +XA_BM_TIEH A_TIEH_O VDD VSS / RSC_IHPSG13_TIEH +.ENDS + + +.SUBCKT RM_IHPSG13_1024x32_c2_1P_COLDEC3 ACLK_N ADDR<2> ADDR<1> ADDR<0> ADDR_COL<1> ++ ADDR_COL<0> ADDR_DEC<7> ADDR_DEC<6> ADDR_DEC<5> ADDR_DEC<4> ADDR_DEC<3> ++ ADDR_DEC<2> ADDR_DEC<1> ADDR_DEC<0> BIST_ADDR<2> BIST_ADDR<1> BIST_ADDR<0> ++ BIST_EN_I VDD VSS +XI15<1> ADDR_COL<1> VDD VSS / RSC_IHPSG13_TIEL +XI15<0> ADDR_COL<0> VDD VSS / RSC_IHPSG13_TIEL +XI1<7> PADR<0> PADR<1> PADR<2> addr_n<7> VDD VSS / RSC_IHPSG13_NAND3X2 +XI1<6> NADR<0> PADR<1> PADR<2> addr_n<6> VDD VSS / RSC_IHPSG13_NAND3X2 +XI1<5> PADR<0> NADR<1> PADR<2> addr_n<5> VDD VSS / RSC_IHPSG13_NAND3X2 +XI1<4> NADR<0> NADR<1> PADR<2> addr_n<4> VDD VSS / RSC_IHPSG13_NAND3X2 +XI1<3> PADR<0> PADR<1> NADR<2> addr_n<3> VDD VSS / RSC_IHPSG13_NAND3X2 +XI1<2> NADR<0> PADR<1> NADR<2> addr_n<2> VDD VSS / RSC_IHPSG13_NAND3X2 +XI1<1> PADR<0> NADR<1> NADR<2> addr_n<1> VDD VSS / RSC_IHPSG13_NAND3X2 +XI1<0> NADR<0> NADR<1> NADR<2> addr_n<0> VDD VSS / RSC_IHPSG13_NAND3X2 +XDFF<2> BIST_EN_I BIST_ADDR<2> ACLK_N ADDR<2> padr_int<2> net6<0> VDD ++ VSS / RSC_IHPSG13_DFNQMX2IX1 +XDFF<1> BIST_EN_I BIST_ADDR<1> ACLK_N ADDR<1> padr_int<1> net6<1> VDD ++ VSS / RSC_IHPSG13_DFNQMX2IX1 +XDFF<0> BIST_EN_I BIST_ADDR<0> ACLK_N ADDR<0> padr_int<0> net6<2> VDD ++ VSS / RSC_IHPSG13_DFNQMX2IX1 +XI17<2> VDD VSS / RSC_IHPSG13_FILLCAP4 +XI17<1> VDD VSS / RSC_IHPSG13_FILLCAP4 +XI13<2> NADR<2> PADR<2> VDD VSS / RSC_IHPSG13_INVX2 +XI13<1> NADR<1> PADR<1> VDD VSS / RSC_IHPSG13_INVX2 +XI13<0> NADR<0> PADR<0> VDD VSS / RSC_IHPSG13_INVX2 +XI3<2> padr_int<2> NADR<2> VDD VSS / RSC_IHPSG13_INVX2 +XI3<1> padr_int<1> NADR<1> VDD VSS / RSC_IHPSG13_INVX2 +XI3<0> padr_int<0> NADR<0> VDD VSS / RSC_IHPSG13_INVX2 +XI2<7> addr_n<7> ADDR_DEC<7> VDD VSS / RSC_IHPSG13_INVX2 +XI2<6> addr_n<6> ADDR_DEC<6> VDD VSS / RSC_IHPSG13_INVX2 +XI2<5> addr_n<5> ADDR_DEC<5> VDD VSS / RSC_IHPSG13_INVX2 +XI2<4> addr_n<4> ADDR_DEC<4> VDD VSS / RSC_IHPSG13_INVX2 +XI2<3> addr_n<3> ADDR_DEC<3> VDD VSS / RSC_IHPSG13_INVX2 +XI2<2> addr_n<2> ADDR_DEC<2> VDD VSS / RSC_IHPSG13_INVX2 +XI2<1> addr_n<1> ADDR_DEC<1> VDD VSS / RSC_IHPSG13_INVX2 +XI2<0> addr_n<0> ADDR_DEC<0> VDD VSS / RSC_IHPSG13_INVX2 +XI16<6> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI16<5> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI16<4> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI16<3> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI16<2> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI16<1> VDD VSS / RSC_IHPSG13_FILLCAP8 +.ENDS +.SUBCKT RM_IHPSG13_1024x32_c2_1P_COLCTRL3 A_ADDR_DEC<7> A_ADDR_DEC<6> A_ADDR_DEC<5> ++ A_ADDR_DEC<4> A_ADDR_DEC<3> A_ADDR_DEC<2> A_ADDR_DEC<1> A_ADDR_DEC<0> ++ A_BIST_BM_I A_BIST_DW_I A_BIST_EN_I A_BLC<7> A_BLC<6> A_BLC<5> A_BLC<4> ++ A_BLC<3> A_BLC<2> A_BLC<1> A_BLC<0> A_BLT<7> A_BLT<6> A_BLT<5> A_BLT<4> ++ A_BLT<3> A_BLT<2> A_BLT<1> A_BLT<0> A_BM_I A_DCLK_B_L A_DCLK_B_R A_DCLK_L ++ A_DCLK_R A_DR_O A_DW_I A_RCLK_B_L A_RCLK_B_R A_RCLK_L A_RCLK_R A_TIEH_O ++ A_WCLK_B_L A_WCLK_B_R A_WCLK_L A_WCLK_R VDD VSS +XA_DREG A_BIST_EN_I A_BIST_DW_I A_DCLK_B_L A_DW_I A_DI_R net22 VDD VSS ++ / RSC_IHPSG13_DFNQMX2IX1 +XA_BREG A_BIST_EN_I A_BIST_BM_I A_DCLK_B_R A_BM_I A_BM_R net23 VDD VSS ++ / RSC_IHPSG13_DFNQMX2IX1 +XA_I70<8> VDD VSS / RSC_IHPSG13_FILLCAP8 +XA_I70<7> VDD VSS / RSC_IHPSG13_FILLCAP8 +XA_I70<6> VDD VSS / RSC_IHPSG13_FILLCAP8 +XA_I70<5> VDD VSS / RSC_IHPSG13_FILLCAP8 +XA_I70<4> VDD VSS / RSC_IHPSG13_FILLCAP8 +XA_I70<3> VDD VSS / RSC_IHPSG13_FILLCAP8 +XA_I70<2> VDD VSS / RSC_IHPSG13_FILLCAP8 +XA_I70<1> VDD VSS / RSC_IHPSG13_FILLCAP8 +XA_I51 net19 A_DR_O VDD VSS / RSC_IHPSG13_INVX4 +XA_I44 A_BM_N A_WCLK_B_R A_DO_WRITE_P VDD VSS / RSC_IHPSG13_NOR2X2 +XA_BM_TIEH A_TIEH_O VDD VSS / RSC_IHPSG13_TIEH +XA_BLTMUX<7> A_BLC<7> A_BLC_SEL A_BLT<7> A_BLT_SEL A_PRE_N A_ADDR_DEC<7> ++ A_WR_ONE A_WR_ZERO VDD VSS / RM_IHPSG13_1024x32_c2_1P_BLDRV +XA_BLTMUX<6> A_BLC<6> A_BLC_SEL A_BLT<6> A_BLT_SEL A_PRE_N A_ADDR_DEC<6> ++ A_WR_ONE A_WR_ZERO VDD VSS / RM_IHPSG13_1024x32_c2_1P_BLDRV +XA_BLTMUX<5> A_BLC<5> A_BLC_SEL A_BLT<5> A_BLT_SEL A_PRE_N A_ADDR_DEC<5> ++ A_WR_ONE A_WR_ZERO VDD VSS / RM_IHPSG13_1024x32_c2_1P_BLDRV +XA_BLTMUX<4> A_BLC<4> A_BLC_SEL A_BLT<4> A_BLT_SEL A_PRE_N A_ADDR_DEC<4> ++ A_WR_ONE A_WR_ZERO VDD VSS / RM_IHPSG13_1024x32_c2_1P_BLDRV +XA_BLTMUX<3> A_BLC<3> A_BLC_SEL A_BLT<3> A_BLT_SEL A_PRE_N A_ADDR_DEC<3> ++ A_WR_ONE A_WR_ZERO VDD VSS / RM_IHPSG13_1024x32_c2_1P_BLDRV +XA_BLTMUX<2> A_BLC<2> A_BLC_SEL A_BLT<2> A_BLT_SEL A_PRE_N A_ADDR_DEC<2> ++ A_WR_ONE A_WR_ZERO VDD VSS / RM_IHPSG13_1024x32_c2_1P_BLDRV +XA_BLTMUX<1> A_BLC<1> A_BLC_SEL A_BLT<1> A_BLT_SEL A_PRE_N A_ADDR_DEC<1> ++ A_WR_ONE A_WR_ZERO VDD VSS / RM_IHPSG13_1024x32_c2_1P_BLDRV +XA_BLTMUX<0> A_BLC<0> A_BLC_SEL A_BLT<0> A_BLT_SEL A_PRE_N A_ADDR_DEC<0> ++ A_WR_ONE A_WR_ZERO VDD VSS / RM_IHPSG13_1024x32_c2_1P_BLDRV +XA_I49 A_DI_R A_DI_N VDD VSS / RSC_IHPSG13_INVX2 +XA_I83 A_BM_R A_BM_N VDD VSS / RSC_IHPSG13_INVX2 +XA_I69 A_DCLK_L A_DCLK_B_L VDD VSS / RSC_IHPSG13_CINVX2 +XA_I50 A_WCLK_L A_WCLK_B_L VDD VSS / RSC_IHPSG13_CINVX2 +XA_EBUF A_RCLK_L A_RCLK_B_L VDD VSS / RSC_IHPSG13_CINVX2 +XA_I78 A_RCLK_B_L A_SAE VDD VSS / RSC_IHPSG13_CBUFX2 +XA_I88 A_DCLK_L A_DCLK_R / RSC_IHPSG13_MET3RES +XA_I87 A_WCLK_L A_WCLK_R / RSC_IHPSG13_MET3RES +XA_R2 A_RCLK_L A_RCLK_R / RSC_IHPSG13_MET3RES +XA_I91 A_RCLK_B_L A_RCLK_B_R / RSC_IHPSG13_MET3RES +XA_I90 A_WCLK_B_L A_WCLK_B_R / RSC_IHPSG13_MET3RES +XA_I89 A_DCLK_B_L A_DCLK_B_R / RSC_IHPSG13_MET3RES +XA_I80 A_WCLK_B_R A_RCLK_B_R net21 VDD VSS / RSC_IHPSG13_AND2X2 +XA_I76 A_DI_N A_DO_WRITE_P A_WR_ZERO VDD VSS / RSC_IHPSG13_AND2X2 +XA_I75 A_DI_R A_DO_WRITE_P A_WR_ONE VDD VSS / RSC_IHPSG13_AND2X2 +XA_ISENSE A_SAE A_BLC_SEL A_BLT_SEL net19 net20 VDD VSS / ++ RSC_IHPSG13_DFPQD_MSAFFX2 +XA_I81 net21 A_PRE_N VDD VSS / RSC_IHPSG13_CINVX4_WN +XA_CAPS<5> VDD VSS / RSC_IHPSG13_FILLCAP4 +XA_CAPS<4> VDD VSS / RSC_IHPSG13_FILLCAP4 +XA_CAPS<3> VDD VSS / RSC_IHPSG13_FILLCAP4 +XA_CAPS<2> VDD VSS / RSC_IHPSG13_FILLCAP4 +XA_CAPS<1> VDD VSS / RSC_IHPSG13_FILLCAP4 +.ENDS + +.SUBCKT RM_IHPSG13_1024x32_c2_2P_BITKIT_16x2_CORNER VDD_CORE VSS +XI16 VDD_CORE VSS VDD_CORE VSS / ++ RM_IHPSG13_1024x32_c2_1P_BITKIT_CORNER +.ENDS +.SUBCKT RM_IHPSG13_1024x32_c2_2P_BITKIT_EDGE_LR A_WL B_WL NW PW VDD VSS +MN1 VSS A_WL VSS VSS sg13_lv_nmos m=1 w=300.0n l=130.00n ng=1 nrd=0 nrs=0 +MN0 VSS B_WL VSS VSS sg13_lv_nmos m=1 w=300.0n l=130.00n ng=1 nrd=0 nrs=0 +.ENDS +.SUBCKT RM_IHPSG13_1024x32_c2_2P_BITKIT_16x2_EDGE_LR A_WL<15> A_WL<14> A_WL<13> A_WL<12> ++ A_WL<11> A_WL<10> A_WL<9> A_WL<8> A_WL<7> A_WL<6> A_WL<5> A_WL<4> A_WL<3> ++ A_WL<2> A_WL<1> A_WL<0> B_WL<15> B_WL<14> B_WL<13> B_WL<12> B_WL<11> ++ B_WL<10> B_WL<9> B_WL<8> B_WL<7> B_WL<6> B_WL<5> B_WL<4> B_WL<3> B_WL<2> ++ B_WL<1> B_WL<0> VDD_CORE VSS +XI0<15> A_WL<15> B_WL<15> VDD_CORE VSS VDD_CORE VSS ++ / RM_IHPSG13_1024x32_c2_2P_BITKIT_EDGE_LR +XI0<14> A_WL<14> B_WL<14> VDD_CORE VSS VDD_CORE VSS ++ / RM_IHPSG13_1024x32_c2_2P_BITKIT_EDGE_LR +XI0<13> A_WL<13> B_WL<13> VDD_CORE VSS VDD_CORE VSS ++ / RM_IHPSG13_1024x32_c2_2P_BITKIT_EDGE_LR +XI0<12> A_WL<12> B_WL<12> VDD_CORE VSS VDD_CORE VSS ++ / RM_IHPSG13_1024x32_c2_2P_BITKIT_EDGE_LR +XI0<11> A_WL<11> B_WL<11> VDD_CORE VSS VDD_CORE VSS ++ / RM_IHPSG13_1024x32_c2_2P_BITKIT_EDGE_LR +XI0<10> A_WL<10> B_WL<10> VDD_CORE VSS VDD_CORE VSS ++ / RM_IHPSG13_1024x32_c2_2P_BITKIT_EDGE_LR +XI0<9> A_WL<9> B_WL<9> VDD_CORE VSS VDD_CORE VSS / ++ RM_IHPSG13_1024x32_c2_2P_BITKIT_EDGE_LR +XI0<8> A_WL<8> B_WL<8> VDD_CORE VSS VDD_CORE VSS / ++ RM_IHPSG13_1024x32_c2_2P_BITKIT_EDGE_LR +XI0<7> A_WL<7> B_WL<7> VDD_CORE VSS VDD_CORE VSS / ++ RM_IHPSG13_1024x32_c2_2P_BITKIT_EDGE_LR +XI0<6> A_WL<6> B_WL<6> VDD_CORE VSS VDD_CORE VSS / ++ RM_IHPSG13_1024x32_c2_2P_BITKIT_EDGE_LR +XI0<5> A_WL<5> B_WL<5> VDD_CORE VSS VDD_CORE VSS / ++ RM_IHPSG13_1024x32_c2_2P_BITKIT_EDGE_LR +XI0<4> A_WL<4> B_WL<4> VDD_CORE VSS VDD_CORE VSS / ++ RM_IHPSG13_1024x32_c2_2P_BITKIT_EDGE_LR +XI0<3> A_WL<3> B_WL<3> VDD_CORE VSS VDD_CORE VSS / ++ RM_IHPSG13_1024x32_c2_2P_BITKIT_EDGE_LR +XI0<2> A_WL<2> B_WL<2> VDD_CORE VSS VDD_CORE VSS / ++ RM_IHPSG13_1024x32_c2_2P_BITKIT_EDGE_LR +XI0<1> A_WL<1> B_WL<1> VDD_CORE VSS VDD_CORE VSS / ++ RM_IHPSG13_1024x32_c2_2P_BITKIT_EDGE_LR +XI0<0> A_WL<0> B_WL<0> VDD_CORE VSS VDD_CORE VSS / ++ RM_IHPSG13_1024x32_c2_2P_BITKIT_EDGE_LR +.ENDS +.SUBCKT RM_IHPSG13_1024x32_c2_2P_BITKIT_CELL A_BLC_BOT A_BLC_TOP A_BLT_BOT A_BLT_TOP ++ A_LWL A_RWL B_BLC_BOT B_BLC_TOP B_BLT_BOT B_BLT_TOP B_LWL B_RWL NW PW VDD VSS +MN5 NC B_RWL B_BLC_BOT PW sg13_lv_nmos m=1 w=300.0n l=130.00n ng=1 nrd=0 nrs=0 +MN4 B_BLT_BOT B_LWL NT PW sg13_lv_nmos m=1 w=300.0n l=130.00n ng=1 nrd=0 nrs=0 +MN0 NC NT VSS PW sg13_lv_nmos m=1 w=600.0n l=130.00n ng=2 nrd=0 nrs=0 +MN1 NT NC VSS PW sg13_lv_nmos m=1 w=600.0n l=130.00n ng=2 nrd=0 nrs=0 +MN3 NC A_RWL A_BLC_TOP PW sg13_lv_nmos m=1 w=300.0n l=130.00n ng=1 nrd=0 nrs=0 +MN2 A_BLT_TOP A_LWL NT PW sg13_lv_nmos m=1 w=300.0n l=130.00n ng=1 nrd=0 nrs=0 +MP1 NT NC VDD NW sg13_lv_pmos m=1 w=150.00n l=130.00n ng=1 nrd=0 nrs=0 +MP0 NC NT VDD NW sg13_lv_pmos m=1 w=150.00n l=130.00n ng=1 nrd=0 nrs=0 +R5 B_RWL B_LWL lvsres w=2.6e-07 l=6e-07 +R4 B_BLC_BOT B_BLC_TOP lvsres w=2.6e-07 l=6e-07 +R3 B_BLT_BOT B_BLT_TOP lvsres w=2.6e-07 l=6e-07 +R1 A_BLC_BOT A_BLC_TOP lvsres w=2.6e-07 l=6e-07 +R0 A_BLT_BOT A_BLT_TOP lvsres w=2.6e-07 l=6e-07 +R2 A_RWL A_LWL lvsres w=2.6e-07 l=6e-07 +.ENDS +.SUBCKT RM_IHPSG13_1024x32_c2_2P_BITKIT_16x2_SRAM A_BLC_BOT<1> A_BLC_BOT<0> A_BLC_TOP<1> ++ A_BLC_TOP<0> A_BLT_BOT<1> A_BLT_BOT<0> A_BLT_TOP<1> A_BLT_TOP<0> A_LWL<15> ++ A_LWL<14> A_LWL<13> A_LWL<12> A_LWL<11> A_LWL<10> A_LWL<9> A_LWL<8> A_LWL<7> ++ A_LWL<6> A_LWL<5> A_LWL<4> A_LWL<3> A_LWL<2> A_LWL<1> A_LWL<0> A_RWL<15> ++ A_RWL<14> A_RWL<13> A_RWL<12> A_RWL<11> A_RWL<10> A_RWL<9> A_RWL<8> A_RWL<7> ++ A_RWL<6> A_RWL<5> A_RWL<4> A_RWL<3> A_RWL<2> A_RWL<1> A_RWL<0> B_BLC_BOT<1> ++ B_BLC_BOT<0> B_BLC_TOP<1> B_BLC_TOP<0> B_BLT_BOT<1> B_BLT_BOT<0> ++ B_BLT_TOP<1> B_BLT_TOP<0> B_LWL<15> B_LWL<14> B_LWL<13> B_LWL<12> B_LWL<11> ++ B_LWL<10> B_LWL<9> B_LWL<8> B_LWL<7> B_LWL<6> B_LWL<5> B_LWL<4> B_LWL<3> ++ B_LWL<2> B_LWL<1> B_LWL<0> B_RWL<15> B_RWL<14> B_RWL<13> B_RWL<12> B_RWL<11> ++ B_RWL<10> B_RWL<9> B_RWL<8> B_RWL<7> B_RWL<6> B_RWL<5> B_RWL<4> B_RWL<3> ++ B_RWL<2> B_RWL<1> B_RWL<0> VDD_CORE VSS +XCELL<31> A_BLC_TOP<1> A_RBLC<15> A_BLT_TOP<1> A_RBLT<15> A_XWL<15> A_RWL<15> ++ B_BLC_TOP<1> B_RBLC<15> B_BLT_TOP<1> B_RBLT<15> B_XWL<15> B_RWL<15> ++ VDD_CORE VSS VDD_CORE VSS / ++ RM_IHPSG13_1024x32_c2_2P_BITKIT_CELL +XCELL<30> A_RBLC<14> A_RBLC<15> A_RBLT<14> A_RBLT<15> A_XWL<14> A_RWL<14> ++ B_RBLC<14> B_RBLC<15> B_RBLT<14> B_RBLT<15> B_XWL<14> B_RWL<14> VDD_CORE ++ VSS VDD_CORE VSS / RM_IHPSG13_1024x32_c2_2P_BITKIT_CELL +XCELL<29> A_RBLC<14> A_RBLC<13> A_RBLT<14> A_RBLT<13> A_XWL<13> A_RWL<13> ++ B_RBLC<14> B_RBLC<13> B_RBLT<14> B_RBLT<13> B_XWL<13> B_RWL<13> VDD_CORE ++ VSS VDD_CORE VSS / RM_IHPSG13_1024x32_c2_2P_BITKIT_CELL +XCELL<28> A_RBLC<12> A_RBLC<13> A_RBLT<12> A_RBLT<13> A_XWL<12> A_RWL<12> ++ B_RBLC<12> B_RBLC<13> B_RBLT<12> B_RBLT<13> B_XWL<12> B_RWL<12> VDD_CORE ++ VSS VDD_CORE VSS / RM_IHPSG13_1024x32_c2_2P_BITKIT_CELL +XCELL<27> A_RBLC<12> A_RBLC<11> A_RBLT<12> A_RBLT<11> A_XWL<11> A_RWL<11> ++ B_RBLC<12> B_RBLC<11> B_RBLT<12> B_RBLT<11> B_XWL<11> B_RWL<11> VDD_CORE ++ VSS VDD_CORE VSS / RM_IHPSG13_1024x32_c2_2P_BITKIT_CELL +XCELL<26> A_RBLC<10> A_RBLC<11> A_RBLT<10> A_RBLT<11> A_XWL<10> A_RWL<10> ++ B_RBLC<10> B_RBLC<11> B_RBLT<10> B_RBLT<11> B_XWL<10> B_RWL<10> VDD_CORE ++ VSS VDD_CORE VSS / RM_IHPSG13_1024x32_c2_2P_BITKIT_CELL +XCELL<25> A_RBLC<10> A_RBLC<9> A_RBLT<10> A_RBLT<9> A_XWL<9> A_RWL<9> ++ B_RBLC<10> B_RBLC<9> B_RBLT<10> B_RBLT<9> B_XWL<9> B_RWL<9> VDD_CORE ++ VSS VDD_CORE VSS / RM_IHPSG13_1024x32_c2_2P_BITKIT_CELL +XCELL<24> A_RBLC<8> A_RBLC<9> A_RBLT<8> A_RBLT<9> A_XWL<8> A_RWL<8> B_RBLC<8> ++ B_RBLC<9> B_RBLT<8> B_RBLT<9> B_XWL<8> B_RWL<8> VDD_CORE VSS ++ VDD_CORE VSS / RM_IHPSG13_1024x32_c2_2P_BITKIT_CELL +XCELL<23> A_RBLC<8> A_RBLC<7> A_RBLT<8> A_RBLT<7> A_XWL<7> A_RWL<7> B_RBLC<8> ++ B_RBLC<7> B_RBLT<8> B_RBLT<7> B_XWL<7> B_RWL<7> VDD_CORE VSS ++ VDD_CORE VSS / RM_IHPSG13_1024x32_c2_2P_BITKIT_CELL +XCELL<22> A_RBLC<6> A_RBLC<7> A_RBLT<6> A_RBLT<7> A_XWL<6> A_RWL<6> B_RBLC<6> ++ B_RBLC<7> B_RBLT<6> B_RBLT<7> B_XWL<6> B_RWL<6> VDD_CORE VSS ++ VDD_CORE VSS / RM_IHPSG13_1024x32_c2_2P_BITKIT_CELL +XCELL<21> A_RBLC<6> A_RBLC<5> A_RBLT<6> A_RBLT<5> A_XWL<5> A_RWL<5> B_RBLC<6> ++ B_RBLC<5> B_RBLT<6> B_RBLT<5> B_XWL<5> B_RWL<5> VDD_CORE VSS ++ VDD_CORE VSS / RM_IHPSG13_1024x32_c2_2P_BITKIT_CELL +XCELL<20> A_RBLC<4> A_RBLC<5> A_RBLT<4> A_RBLT<5> A_XWL<4> A_RWL<4> B_RBLC<4> ++ B_RBLC<5> B_RBLT<4> B_RBLT<5> B_XWL<4> B_RWL<4> VDD_CORE VSS ++ VDD_CORE VSS / RM_IHPSG13_1024x32_c2_2P_BITKIT_CELL +XCELL<19> A_RBLC<4> A_RBLC<3> A_RBLT<4> A_RBLT<3> A_XWL<3> A_RWL<3> B_RBLC<4> ++ B_RBLC<3> B_RBLT<4> B_RBLT<3> B_XWL<3> B_RWL<3> VDD_CORE VSS ++ VDD_CORE VSS / RM_IHPSG13_1024x32_c2_2P_BITKIT_CELL +XCELL<18> A_RBLC<2> A_RBLC<3> A_RBLT<2> A_RBLT<3> A_XWL<2> A_RWL<2> B_RBLC<2> ++ B_RBLC<3> B_RBLT<2> B_RBLT<3> B_XWL<2> B_RWL<2> VDD_CORE VSS ++ VDD_CORE VSS / RM_IHPSG13_1024x32_c2_2P_BITKIT_CELL +XCELL<17> A_RBLC<2> A_RBLC<1> A_RBLT<2> A_RBLT<1> A_XWL<1> A_RWL<1> B_RBLC<2> ++ B_RBLC<1> B_RBLT<2> B_RBLT<1> B_XWL<1> B_RWL<1> VDD_CORE VSS ++ VDD_CORE VSS / RM_IHPSG13_1024x32_c2_2P_BITKIT_CELL +XCELL<16> A_BLC_BOT<1> A_RBLC<1> A_BLT_BOT<1> A_RBLT<1> A_XWL<0> A_RWL<0> ++ B_BLC_BOT<1> B_RBLC<1> B_BLT_BOT<1> B_RBLT<1> B_XWL<0> B_RWL<0> VDD_CORE ++ VSS VDD_CORE VSS / RM_IHPSG13_1024x32_c2_2P_BITKIT_CELL +XCELL<15> A_BLC_TOP<0> A_LBLC<15> A_BLT_TOP<0> A_LBLT<15> A_LWL<15> A_XWL<15> ++ B_BLC_TOP<0> B_LBLC<15> B_BLT_TOP<0> B_LBLT<15> B_LWL<15> B_XWL<15> ++ VDD_CORE VSS VDD_CORE VSS / ++ RM_IHPSG13_1024x32_c2_2P_BITKIT_CELL +XCELL<14> A_LBLC<14> A_LBLC<15> A_LBLT<14> A_LBLT<15> A_LWL<14> A_XWL<14> ++ B_LBLC<14> B_LBLC<15> B_LBLT<14> B_LBLT<15> B_LWL<14> B_XWL<14> VDD_CORE ++ VSS VDD_CORE VSS / RM_IHPSG13_1024x32_c2_2P_BITKIT_CELL +XCELL<13> A_LBLC<14> A_LBLC<13> A_LBLT<14> A_LBLT<13> A_LWL<13> A_XWL<13> ++ B_LBLC<14> B_LBLC<13> B_LBLT<14> B_LBLT<13> B_LWL<13> B_XWL<13> VDD_CORE ++ VSS VDD_CORE VSS / RM_IHPSG13_1024x32_c2_2P_BITKIT_CELL +XCELL<12> A_LBLC<12> A_LBLC<13> A_LBLT<12> A_LBLT<13> A_LWL<12> A_XWL<12> ++ B_LBLC<12> B_LBLC<13> B_LBLT<12> B_LBLT<13> B_LWL<12> B_XWL<12> VDD_CORE ++ VSS VDD_CORE VSS / RM_IHPSG13_1024x32_c2_2P_BITKIT_CELL +XCELL<11> A_LBLC<12> A_LBLC<11> A_LBLT<12> A_LBLT<11> A_LWL<11> A_XWL<11> ++ B_LBLC<12> B_LBLC<11> B_LBLT<12> B_LBLT<11> B_LWL<11> B_XWL<11> VDD_CORE ++ VSS VDD_CORE VSS / RM_IHPSG13_1024x32_c2_2P_BITKIT_CELL +XCELL<10> A_LBLC<10> A_LBLC<11> A_LBLT<10> A_LBLT<11> A_LWL<10> A_XWL<10> ++ B_LBLC<10> B_LBLC<11> B_LBLT<10> B_LBLT<11> B_LWL<10> B_XWL<10> VDD_CORE ++ VSS VDD_CORE VSS / RM_IHPSG13_1024x32_c2_2P_BITKIT_CELL +XCELL<9> A_LBLC<10> A_LBLC<9> A_LBLT<10> A_LBLT<9> A_LWL<9> A_XWL<9> ++ B_LBLC<10> B_LBLC<9> B_LBLT<10> B_LBLT<9> B_LWL<9> B_XWL<9> VDD_CORE ++ VSS VDD_CORE VSS / RM_IHPSG13_1024x32_c2_2P_BITKIT_CELL +XCELL<8> A_LBLC<8> A_LBLC<9> A_LBLT<8> A_LBLT<9> A_LWL<8> A_XWL<8> B_LBLC<8> ++ B_LBLC<9> B_LBLT<8> B_LBLT<9> B_LWL<8> B_XWL<8> VDD_CORE VSS ++ VDD_CORE VSS / RM_IHPSG13_1024x32_c2_2P_BITKIT_CELL +XCELL<7> A_LBLC<8> A_LBLC<7> A_LBLT<8> A_LBLT<7> A_LWL<7> A_XWL<7> B_LBLC<8> ++ B_LBLC<7> B_LBLT<8> B_LBLT<7> B_LWL<7> B_XWL<7> VDD_CORE VSS ++ VDD_CORE VSS / RM_IHPSG13_1024x32_c2_2P_BITKIT_CELL +XCELL<6> A_LBLC<6> A_LBLC<7> A_LBLT<6> A_LBLT<7> A_LWL<6> A_XWL<6> B_LBLC<6> ++ B_LBLC<7> B_LBLT<6> B_LBLT<7> B_LWL<6> B_XWL<6> VDD_CORE VSS ++ VDD_CORE VSS / RM_IHPSG13_1024x32_c2_2P_BITKIT_CELL +XCELL<5> A_LBLC<6> A_LBLC<5> A_LBLT<6> A_LBLT<5> A_LWL<5> A_XWL<5> B_LBLC<6> ++ B_LBLC<5> B_LBLT<6> B_LBLT<5> B_LWL<5> B_XWL<5> VDD_CORE VSS ++ VDD_CORE VSS / RM_IHPSG13_1024x32_c2_2P_BITKIT_CELL +XCELL<4> A_LBLC<4> A_LBLC<5> A_LBLT<4> A_LBLT<5> A_LWL<4> A_XWL<4> B_LBLC<4> ++ B_LBLC<5> B_LBLT<4> B_LBLT<5> B_LWL<4> B_XWL<4> VDD_CORE VSS ++ VDD_CORE VSS / RM_IHPSG13_1024x32_c2_2P_BITKIT_CELL +XCELL<3> A_LBLC<4> A_LBLC<3> A_LBLT<4> A_LBLT<3> A_LWL<3> A_XWL<3> B_LBLC<4> ++ B_LBLC<3> B_LBLT<4> B_LBLT<3> B_LWL<3> B_XWL<3> VDD_CORE VSS ++ VDD_CORE VSS / RM_IHPSG13_1024x32_c2_2P_BITKIT_CELL +XCELL<2> A_LBLC<2> A_LBLC<3> A_LBLT<2> A_LBLT<3> A_LWL<2> A_XWL<2> B_LBLC<2> ++ B_LBLC<3> B_LBLT<2> B_LBLT<3> B_LWL<2> B_XWL<2> VDD_CORE VSS ++ VDD_CORE VSS / RM_IHPSG13_1024x32_c2_2P_BITKIT_CELL +XCELL<1> A_LBLC<2> A_LBLC<1> A_LBLT<2> A_LBLT<1> A_LWL<1> A_XWL<1> B_LBLC<2> ++ B_LBLC<1> B_LBLT<2> B_LBLT<1> B_LWL<1> B_XWL<1> VDD_CORE VSS ++ VDD_CORE VSS / RM_IHPSG13_1024x32_c2_2P_BITKIT_CELL +XCELL<0> A_BLC_BOT<0> A_LBLC<1> A_BLT_BOT<0> A_LBLT<1> A_LWL<0> A_XWL<0> ++ B_BLC_BOT<0> B_LBLC<1> B_BLT_BOT<0> B_LBLT<1> B_LWL<0> B_XWL<0> VDD_CORE ++ VSS VDD_CORE VSS / RM_IHPSG13_1024x32_c2_2P_BITKIT_CELL +.ENDS +.SUBCKT RM_IHPSG13_1024x32_c2_2P_BITKIT_EDGE_TB A_BLC A_BLT B_BLC B_BLT NW PW VDD VSS +.ENDS +.SUBCKT RM_IHPSG13_1024x32_c2_2P_BITKIT_16x2_EDGE_TB A_BLC<1> A_BLC<0> A_BLT<1> A_BLT<0> ++ B_BLC<1> B_BLC<0> B_BLT<1> B_BLT<0> VDD_CORE VSS +XEDGE<1> A_BLC<1> A_BLT<1> B_BLC<1> B_BLT<1> VDD_CORE VSS ++ VDD_CORE VSS / RM_IHPSG13_1024x32_c2_2P_BITKIT_EDGE_TB +XEDGE<0> A_BLC<0> A_BLT<0> B_BLC<0> B_BLT<0> VDD_CORE VSS ++ VDD_CORE VSS / RM_IHPSG13_1024x32_c2_2P_BITKIT_EDGE_TB +.ENDS +.SUBCKT RM_IHPSG13_1024x32_c2_2P_BITKIT_TAP A_BLC A_BLT B_BLC B_BLT NW PW VDD VSS +.ENDS +.SUBCKT RM_IHPSG13_1024x32_c2_2P_BITKIT_16x2_TAP A_BLC<1> A_BLC<0> A_BLT<1> A_BLT<0> ++ B_BLC<1> B_BLC<0> B_BLT<1> B_BLT<0> VDD_CORE VSS +XIEDGEBP_COL1<1> A_BLC<1> A_BLT<1> B_BLC<1> B_BLT<1> VDD_CORE VSS ++ VDD_CORE VSS / RM_IHPSG13_1024x32_c2_2P_BITKIT_EDGE_TB +XIEDGEBP_COL1<0> A_BLC<1> A_BLT<1> B_BLC<1> B_BLT<1> VDD_CORE VSS ++ VDD_CORE VSS / RM_IHPSG13_1024x32_c2_2P_BITKIT_EDGE_TB +XIEDGEBP_COL2<1> A_BLC<0> A_BLT<0> B_BLC<0> B_BLT<0> VDD_CORE VSS ++ VDD_CORE VSS / RM_IHPSG13_1024x32_c2_2P_BITKIT_EDGE_TB +XIEDGEBP_COL2<0> A_BLC<0> A_BLT<0> B_BLC<0> B_BLT<0> VDD_CORE VSS ++ VDD_CORE VSS / RM_IHPSG13_1024x32_c2_2P_BITKIT_EDGE_TB +XITAP<1> A_BLC<1> A_BLT<1> B_BLC<1> B_BLT<1> VDD_CORE VSS ++ VDD_CORE VSS / RM_IHPSG13_1024x32_c2_2P_BITKIT_TAP +XITAP<0> A_BLC<0> A_BLT<0> B_BLC<0> B_BLT<0> VDD_CORE VSS ++ VDD_CORE VSS / RM_IHPSG13_1024x32_c2_2P_BITKIT_TAP +.ENDS + + +.SUBCKT RM_IHPSG13_1024x32_c2_1P_BITKIT_TAP_LR NW PW VDD VSS +.ENDS +.SUBCKT RM_IHPSG13_1024x32_c2_2P_BITKIT_16x2_TAP_LR VDD_CORE VSS +XCORNER<1> VDD_CORE VSS VDD_CORE VSS / ++ RM_IHPSG13_1024x32_c2_1P_BITKIT_CORNER +XCORNER<0> VDD_CORE VSS VDD_CORE VSS / ++ RM_IHPSG13_1024x32_c2_1P_BITKIT_CORNER +XTAP_BORDER VDD_CORE VSS VDD_CORE VSS / ++ RM_IHPSG13_1024x32_c2_1P_BITKIT_TAP_LR +.ENDS + +.SUBCKT RSC_IHPSG13_CBUFX12 A Z VDD VSS +MN1 Z net6 VSS VSS sg13_lv_nmos m=1 w=4.23u l=130.00n ng=6 nrd=0 nrs=0 +MN0 net6 A VSS VSS sg13_lv_nmos m=1 w=1.41u l=130.00n ng=2 nrd=0 nrs=0 +MP1 Z net6 VDD VDD sg13_lv_pmos m=1 w=9.72u l=130.00n ng=6 nrd=0 nrs=0 +MP0 net6 A VDD VDD sg13_lv_pmos m=1 w=3.24u l=130.00n ng=2 nrd=0 nrs=0 +.ENDS +.SUBCKT RM_IHPSG13_1024x32_c2_2P_COLDRV13X12 ADDR_COL_I<1> ADDR_COL_I<0> ADDR_COL_O<1> ++ ADDR_COL_O<0> ADDR_DEC_I<7> ADDR_DEC_I<6> ADDR_DEC_I<5> ADDR_DEC_I<4> ++ ADDR_DEC_I<3> ADDR_DEC_I<2> ADDR_DEC_I<1> ADDR_DEC_I<0> ADDR_DEC_O<7> ++ ADDR_DEC_O<6> ADDR_DEC_O<5> ADDR_DEC_O<4> ADDR_DEC_O<3> ADDR_DEC_O<2> ++ ADDR_DEC_O<1> ADDR_DEC_O<0> DCLK_I DCLK_O RCLK_I RCLK_O WCLK_I WCLK_O ++ VDD VSS +XI1<3> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI1<2> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI1<1> VDD VSS / RSC_IHPSG13_FILLCAP8 +XWCLK_DRV WCLK_I WCLK_O VDD VSS / RSC_IHPSG13_CBUFX12 +XRCLK_DRV RCLK_I RCLK_O VDD VSS / RSC_IHPSG13_CBUFX12 +XDCLK_DRV DCLK_I DCLK_O VDD VSS / RSC_IHPSG13_CBUFX12 +XADDR_COL_DRV<1> ADDR_COL_I<1> ADDR_COL_O<1> VDD VSS / ++ RSC_IHPSG13_CBUFX12 +XADDR_COL_DRV<0> ADDR_COL_I<0> ADDR_COL_O<0> VDD VSS / ++ RSC_IHPSG13_CBUFX12 +XADDR_DEC_DRV<7> ADDR_DEC_I<7> ADDR_DEC_O<7> VDD VSS / ++ RSC_IHPSG13_CBUFX12 +XADDR_DEC_DRV<6> ADDR_DEC_I<6> ADDR_DEC_O<6> VDD VSS / ++ RSC_IHPSG13_CBUFX12 +XADDR_DEC_DRV<5> ADDR_DEC_I<5> ADDR_DEC_O<5> VDD VSS / ++ RSC_IHPSG13_CBUFX12 +XADDR_DEC_DRV<4> ADDR_DEC_I<4> ADDR_DEC_O<4> VDD VSS / ++ RSC_IHPSG13_CBUFX12 +XADDR_DEC_DRV<3> ADDR_DEC_I<3> ADDR_DEC_O<3> VDD VSS / ++ RSC_IHPSG13_CBUFX12 +XADDR_DEC_DRV<2> ADDR_DEC_I<2> ADDR_DEC_O<2> VDD VSS / ++ RSC_IHPSG13_CBUFX12 +XADDR_DEC_DRV<1> ADDR_DEC_I<1> ADDR_DEC_O<1> VDD VSS / ++ RSC_IHPSG13_CBUFX12 +XADDR_DEC_DRV<0> ADDR_DEC_I<0> ADDR_DEC_O<0> VDD VSS / ++ RSC_IHPSG13_CBUFX12 +XI0<6> VDD VSS / RSC_IHPSG13_FILLCAP4 +XI0<5> VDD VSS / RSC_IHPSG13_FILLCAP4 +XI0<4> VDD VSS / RSC_IHPSG13_FILLCAP4 +XI0<3> VDD VSS / RSC_IHPSG13_FILLCAP4 +XI0<2> VDD VSS / RSC_IHPSG13_FILLCAP4 +XI0<1> VDD VSS / RSC_IHPSG13_FILLCAP4 +.ENDS +.SUBCKT RSC_IHPSG13_WLDRVX12 A Z VDD VSS +MN1 Z net6 VSS VSS sg13_lv_nmos m=1 w=1.41u l=130.00n ng=2 nrd=0 nrs=0 +MN0 net6 A VSS VSS sg13_lv_nmos m=1 w=1.8u l=130.00n ng=2 nrd=0 nrs=0 +MP1 Z net6 VDD VDD sg13_lv_pmos m=1 w=9.72u l=130.00n ng=6 nrd=0 nrs=0 +MP0 net6 A VDD VDD sg13_lv_pmos m=1 w=900.0n l=130.00n ng=1 nrd=0 nrs=0 +.ENDS +.SUBCKT RM_IHPSG13_1024x32_c2_2P_WLDRV16X12 A<15> A<14> A<13> A<12> A<11> A<10> A<9> A<8> ++ A<7> A<6> A<5> A<4> A<3> A<2> A<1> A<0> Z<15> Z<14> Z<13> Z<12> Z<11> Z<10> ++ Z<9> Z<8> Z<7> Z<6> Z<5> Z<4> Z<3> Z<2> Z<1> Z<0> VDD VSS +XBUF<15> A<15> Z<15> VDD VSS / RSC_IHPSG13_WLDRVX12 +XBUF<14> A<14> Z<14> VDD VSS / RSC_IHPSG13_WLDRVX12 +XBUF<13> A<13> Z<13> VDD VSS / RSC_IHPSG13_WLDRVX12 +XBUF<12> A<12> Z<12> VDD VSS / RSC_IHPSG13_WLDRVX12 +XBUF<11> A<11> Z<11> VDD VSS / RSC_IHPSG13_WLDRVX12 +XBUF<10> A<10> Z<10> VDD VSS / RSC_IHPSG13_WLDRVX12 +XBUF<9> A<9> Z<9> VDD VSS / RSC_IHPSG13_WLDRVX12 +XBUF<8> A<8> Z<8> VDD VSS / RSC_IHPSG13_WLDRVX12 +XBUF<7> A<7> Z<7> VDD VSS / RSC_IHPSG13_WLDRVX12 +XBUF<6> A<6> Z<6> VDD VSS / RSC_IHPSG13_WLDRVX12 +XBUF<5> A<5> Z<5> VDD VSS / RSC_IHPSG13_WLDRVX12 +XBUF<4> A<4> Z<4> VDD VSS / RSC_IHPSG13_WLDRVX12 +XBUF<3> A<3> Z<3> VDD VSS / RSC_IHPSG13_WLDRVX12 +XBUF<2> A<2> Z<2> VDD VSS / RSC_IHPSG13_WLDRVX12 +XBUF<1> A<1> Z<1> VDD VSS / RSC_IHPSG13_WLDRVX12 +XBUF<0> A<0> Z<0> VDD VSS / RSC_IHPSG13_WLDRVX12 +.ENDS +.SUBCKT RM_IHPSG13_1024x32_c2_2P_DEC04 ADDR<3> ADDR<2> ADDR<1> ADDR<0> CS ECLK_H_BOT ++ ECLK_H_TOP ECLK_L_BOT ECLK_L_TOP WL<15> WL<14> WL<13> WL<12> WL<11> WL<10> ++ WL<9> WL<8> WL<7> WL<6> WL<5> WL<4> WL<3> WL<2> WL<1> WL<0> VDD VSS +XI0<3> PADR<1> PADR<0> sel01<3> VDD VSS / RSC_IHPSG13_NAND2X2 +XI0<2> PADR<1> NADR<0> sel01<2> VDD VSS / RSC_IHPSG13_NAND2X2 +XI0<1> NADR<1> PADR<0> sel01<1> VDD VSS / RSC_IHPSG13_NAND2X2 +XI0<0> NADR<1> NADR<0> sel01<0> VDD VSS / RSC_IHPSG13_NAND2X2 +XI4 ECLK_L_BOT EN VDD VSS / RSC_IHPSG13_CINVX4 +XI5 ECLK_H_BOT ECLK_L_BOT VDD VSS / RSC_IHPSG13_CINVX2 +XI3<3> PADR<3> NADR<3> VDD VSS / RSC_IHPSG13_INVX2 +XI3<2> PADR<2> NADR<2> VDD VSS / RSC_IHPSG13_INVX2 +XI3<1> PADR<1> NADR<1> VDD VSS / RSC_IHPSG13_INVX2 +XI3<0> PADR<0> NADR<0> VDD VSS / RSC_IHPSG13_INVX2 +XR0 ECLK_H_BOT ECLK_H_TOP / RSC_IHPSG13_MET2RES +XI11 ECLK_L_BOT ECLK_L_TOP / RSC_IHPSG13_MET2RES +XI1<3> PADR<2> PADR<3> CS sel23<3> VDD VSS / RSC_IHPSG13_NAND3X2 +XI1<2> NADR<2> PADR<3> CS sel23<2> VDD VSS / RSC_IHPSG13_NAND3X2 +XI1<1> PADR<2> NADR<3> CS sel23<1> VDD VSS / RSC_IHPSG13_NAND3X2 +XI1<0> NADR<2> NADR<3> CS sel23<0> VDD VSS / RSC_IHPSG13_NAND3X2 +XI2<15> sel23<3> sel01<3> EN WL<15> VDD VSS / RSC_IHPSG13_NOR3X2 +XI2<14> sel23<3> sel01<2> EN WL<14> VDD VSS / RSC_IHPSG13_NOR3X2 +XI2<13> sel23<3> sel01<1> EN WL<13> VDD VSS / RSC_IHPSG13_NOR3X2 +XI2<12> sel23<3> sel01<0> EN WL<12> VDD VSS / RSC_IHPSG13_NOR3X2 +XI2<11> sel23<2> sel01<3> EN WL<11> VDD VSS / RSC_IHPSG13_NOR3X2 +XI2<10> sel23<2> sel01<2> EN WL<10> VDD VSS / RSC_IHPSG13_NOR3X2 +XI2<9> sel23<2> sel01<1> EN WL<9> VDD VSS / RSC_IHPSG13_NOR3X2 +XI2<8> sel23<2> sel01<0> EN WL<8> VDD VSS / RSC_IHPSG13_NOR3X2 +XI2<7> sel23<1> sel01<3> EN WL<7> VDD VSS / RSC_IHPSG13_NOR3X2 +XI2<6> sel23<1> sel01<2> EN WL<6> VDD VSS / RSC_IHPSG13_NOR3X2 +XI2<5> sel23<1> sel01<1> EN WL<5> VDD VSS / RSC_IHPSG13_NOR3X2 +XI2<4> sel23<1> sel01<0> EN WL<4> VDD VSS / RSC_IHPSG13_NOR3X2 +XI2<3> sel23<0> sel01<3> EN WL<3> VDD VSS / RSC_IHPSG13_NOR3X2 +XI2<2> sel23<0> sel01<2> EN WL<2> VDD VSS / RSC_IHPSG13_NOR3X2 +XI2<1> sel23<0> sel01<1> EN WL<1> VDD VSS / RSC_IHPSG13_NOR3X2 +XI2<0> sel23<0> sel01<0> EN WL<0> VDD VSS / RSC_IHPSG13_NOR3X2 +XCAPS4 VDD VSS / RSC_IHPSG13_FILLCAP4 +XLATCH<3> CS ADDR<3> PADR<3> VDD VSS / RSC_IHPSG13_LHPQX2 +XLATCH<2> CS ADDR<2> PADR<2> VDD VSS / RSC_IHPSG13_LHPQX2 +XLATCH<1> CS ADDR<1> PADR<1> VDD VSS / RSC_IHPSG13_LHPQX2 +XLATCH<0> CS ADDR<0> PADR<0> VDD VSS / RSC_IHPSG13_LHPQX2 +.ENDS +.SUBCKT RM_IHPSG13_1024x32_c2_2P_DEC02 ADDR<1> ADDR<0> CS CS_OUT VDD VSS +XDEC ADDR<1> NADDR<0> CS net1 VDD VSS / RSC_IHPSG13_NAND3X2 +XADDRINV ADDR<0> NADDR<0> VDD VSS / RSC_IHPSG13_INVX2 +XDECINV net1 CS_OUT VDD VSS / RSC_IHPSG13_INVX4 +XI2<1> VDD VSS / RSC_IHPSG13_FILLCAP4 +XI2<0> VDD VSS / RSC_IHPSG13_FILLCAP4 +.ENDS +.SUBCKT RM_IHPSG13_1024x32_c2_2P_DEC01 ADDR<1> ADDR<0> CS CS_OUT VDD VSS +XDEC NADDR<1> ADDR<0> CS net1 VDD VSS / RSC_IHPSG13_NAND3X2 +XADDRINV ADDR<1> NADDR<1> VDD VSS / RSC_IHPSG13_INVX2 +XDECINV net1 CS_OUT VDD VSS / RSC_IHPSG13_INVX4 +XI2<1> VDD VSS / RSC_IHPSG13_FILLCAP4 +XI2<0> VDD VSS / RSC_IHPSG13_FILLCAP4 +.ENDS +.SUBCKT RM_IHPSG13_1024x32_c2_2P_DEC00 ADDR<1> ADDR<0> CS CS_OUT VDD VSS +XDEC NADDR<1> NADDR<0> CS net1 VDD VSS / RSC_IHPSG13_NAND3X2 +XADDRINV<1> ADDR<1> NADDR<1> VDD VSS / RSC_IHPSG13_INVX2 +XADDRINV<0> ADDR<0> NADDR<0> VDD VSS / RSC_IHPSG13_INVX2 +XI1<1> VDD VSS / RSC_IHPSG13_FILLCAP4 +XI1<0> VDD VSS / RSC_IHPSG13_FILLCAP4 +XDECINV net1 CS_OUT VDD VSS / RSC_IHPSG13_INVX4 +.ENDS +.SUBCKT RM_IHPSG13_1024x32_c2_2P_DEC03 ADDR<1> ADDR<0> CS CS_OUT VDD VSS +XDEC ADDR<1> ADDR<0> CS net1 VDD VSS / RSC_IHPSG13_NAND3X2 +XDECINV net1 CS_OUT VDD VSS / RSC_IHPSG13_INVX4 +XI0<1> VDD VSS / RSC_IHPSG13_FILLCAP4 +XI0<0> VDD VSS / RSC_IHPSG13_FILLCAP4 +.ENDS +.SUBCKT RM_IHPSG13_1024x32_c2_2P_ROWDEC9 ADDR_N_I<8> ADDR_N_I<7> ADDR_N_I<6> ADDR_N_I<5> ++ ADDR_N_I<4> ADDR_N_I<3> ADDR_N_I<2> ADDR_N_I<1> ADDR_N_I<0> CS_I ECLK_I ++ WL_O<511> WL_O<510> WL_O<509> WL_O<508> WL_O<507> WL_O<506> WL_O<505> ++ WL_O<504> WL_O<503> WL_O<502> WL_O<501> WL_O<500> WL_O<499> WL_O<498> ++ WL_O<497> WL_O<496> WL_O<495> WL_O<494> WL_O<493> WL_O<492> WL_O<491> ++ WL_O<490> WL_O<489> WL_O<488> WL_O<487> WL_O<486> WL_O<485> WL_O<484> ++ WL_O<483> WL_O<482> WL_O<481> WL_O<480> WL_O<479> WL_O<478> WL_O<477> ++ WL_O<476> WL_O<475> WL_O<474> WL_O<473> WL_O<472> WL_O<471> WL_O<470> ++ WL_O<469> WL_O<468> WL_O<467> WL_O<466> WL_O<465> WL_O<464> WL_O<463> ++ WL_O<462> WL_O<461> WL_O<460> WL_O<459> WL_O<458> WL_O<457> WL_O<456> ++ WL_O<455> WL_O<454> WL_O<453> WL_O<452> WL_O<451> WL_O<450> WL_O<449> ++ WL_O<448> WL_O<447> WL_O<446> WL_O<445> WL_O<444> WL_O<443> WL_O<442> ++ WL_O<441> WL_O<440> WL_O<439> WL_O<438> WL_O<437> WL_O<436> WL_O<435> ++ WL_O<434> WL_O<433> WL_O<432> WL_O<431> WL_O<430> WL_O<429> WL_O<428> ++ WL_O<427> WL_O<426> WL_O<425> WL_O<424> WL_O<423> WL_O<422> WL_O<421> ++ WL_O<420> WL_O<419> WL_O<418> WL_O<417> WL_O<416> WL_O<415> WL_O<414> ++ WL_O<413> WL_O<412> WL_O<411> WL_O<410> WL_O<409> WL_O<408> WL_O<407> ++ WL_O<406> WL_O<405> WL_O<404> WL_O<403> WL_O<402> WL_O<401> WL_O<400> ++ WL_O<399> WL_O<398> WL_O<397> WL_O<396> WL_O<395> WL_O<394> WL_O<393> ++ WL_O<392> WL_O<391> WL_O<390> WL_O<389> WL_O<388> WL_O<387> WL_O<386> ++ WL_O<385> WL_O<384> WL_O<383> WL_O<382> WL_O<381> WL_O<380> WL_O<379> ++ WL_O<378> WL_O<377> WL_O<376> WL_O<375> WL_O<374> WL_O<373> WL_O<372> ++ WL_O<371> WL_O<370> WL_O<369> WL_O<368> WL_O<367> WL_O<366> WL_O<365> ++ WL_O<364> WL_O<363> WL_O<362> WL_O<361> WL_O<360> WL_O<359> WL_O<358> ++ WL_O<357> WL_O<356> WL_O<355> WL_O<354> WL_O<353> WL_O<352> WL_O<351> ++ WL_O<350> WL_O<349> WL_O<348> WL_O<347> WL_O<346> WL_O<345> WL_O<344> ++ WL_O<343> WL_O<342> WL_O<341> WL_O<340> WL_O<339> WL_O<338> WL_O<337> ++ WL_O<336> WL_O<335> WL_O<334> WL_O<333> WL_O<332> WL_O<331> WL_O<330> ++ WL_O<329> WL_O<328> WL_O<327> WL_O<326> WL_O<325> WL_O<324> WL_O<323> ++ WL_O<322> WL_O<321> WL_O<320> WL_O<319> WL_O<318> WL_O<317> WL_O<316> ++ WL_O<315> WL_O<314> WL_O<313> WL_O<312> WL_O<311> WL_O<310> WL_O<309> ++ WL_O<308> WL_O<307> WL_O<306> WL_O<305> WL_O<304> WL_O<303> WL_O<302> ++ WL_O<301> WL_O<300> WL_O<299> WL_O<298> WL_O<297> WL_O<296> WL_O<295> ++ WL_O<294> WL_O<293> WL_O<292> WL_O<291> WL_O<290> WL_O<289> WL_O<288> ++ WL_O<287> WL_O<286> WL_O<285> WL_O<284> WL_O<283> WL_O<282> WL_O<281> ++ WL_O<280> WL_O<279> WL_O<278> WL_O<277> WL_O<276> WL_O<275> WL_O<274> ++ WL_O<273> WL_O<272> WL_O<271> WL_O<270> WL_O<269> WL_O<268> WL_O<267> ++ WL_O<266> WL_O<265> WL_O<264> WL_O<263> WL_O<262> WL_O<261> WL_O<260> ++ WL_O<259> WL_O<258> WL_O<257> WL_O<256> WL_O<255> WL_O<254> WL_O<253> ++ WL_O<252> WL_O<251> WL_O<250> WL_O<249> WL_O<248> WL_O<247> WL_O<246> ++ WL_O<245> WL_O<244> WL_O<243> WL_O<242> WL_O<241> WL_O<240> WL_O<239> ++ WL_O<238> WL_O<237> WL_O<236> WL_O<235> WL_O<234> WL_O<233> WL_O<232> ++ WL_O<231> WL_O<230> WL_O<229> WL_O<228> WL_O<227> WL_O<226> WL_O<225> ++ WL_O<224> WL_O<223> WL_O<222> WL_O<221> WL_O<220> WL_O<219> WL_O<218> ++ WL_O<217> WL_O<216> WL_O<215> WL_O<214> WL_O<213> WL_O<212> WL_O<211> ++ WL_O<210> WL_O<209> WL_O<208> WL_O<207> WL_O<206> WL_O<205> WL_O<204> ++ WL_O<203> WL_O<202> WL_O<201> WL_O<200> WL_O<199> WL_O<198> WL_O<197> ++ WL_O<196> WL_O<195> WL_O<194> WL_O<193> WL_O<192> WL_O<191> WL_O<190> ++ WL_O<189> WL_O<188> WL_O<187> WL_O<186> WL_O<185> WL_O<184> WL_O<183> ++ WL_O<182> WL_O<181> WL_O<180> WL_O<179> WL_O<178> WL_O<177> WL_O<176> ++ WL_O<175> WL_O<174> WL_O<173> WL_O<172> WL_O<171> WL_O<170> WL_O<169> ++ WL_O<168> WL_O<167> WL_O<166> WL_O<165> WL_O<164> WL_O<163> WL_O<162> ++ WL_O<161> WL_O<160> WL_O<159> WL_O<158> WL_O<157> WL_O<156> WL_O<155> ++ WL_O<154> WL_O<153> WL_O<152> WL_O<151> WL_O<150> WL_O<149> WL_O<148> ++ WL_O<147> WL_O<146> WL_O<145> WL_O<144> WL_O<143> WL_O<142> WL_O<141> ++ WL_O<140> WL_O<139> WL_O<138> WL_O<137> WL_O<136> WL_O<135> WL_O<134> ++ WL_O<133> WL_O<132> WL_O<131> WL_O<130> WL_O<129> WL_O<128> WL_O<127> ++ WL_O<126> WL_O<125> WL_O<124> WL_O<123> WL_O<122> WL_O<121> WL_O<120> ++ WL_O<119> WL_O<118> WL_O<117> WL_O<116> WL_O<115> WL_O<114> WL_O<113> ++ WL_O<112> WL_O<111> WL_O<110> WL_O<109> WL_O<108> WL_O<107> WL_O<106> ++ WL_O<105> WL_O<104> WL_O<103> WL_O<102> WL_O<101> WL_O<100> WL_O<99> ++ WL_O<98> WL_O<97> WL_O<96> WL_O<95> WL_O<94> WL_O<93> WL_O<92> WL_O<91> ++ WL_O<90> WL_O<89> WL_O<88> WL_O<87> WL_O<86> WL_O<85> WL_O<84> WL_O<83> ++ WL_O<82> WL_O<81> WL_O<80> WL_O<79> WL_O<78> WL_O<77> WL_O<76> WL_O<75> ++ WL_O<74> WL_O<73> WL_O<72> WL_O<71> WL_O<70> WL_O<69> WL_O<68> WL_O<67> ++ WL_O<66> WL_O<65> WL_O<64> WL_O<63> WL_O<62> WL_O<61> WL_O<60> WL_O<59> ++ WL_O<58> WL_O<57> WL_O<56> WL_O<55> WL_O<54> WL_O<53> WL_O<52> WL_O<51> ++ WL_O<50> WL_O<49> WL_O<48> WL_O<47> WL_O<46> WL_O<45> WL_O<44> WL_O<43> ++ WL_O<42> WL_O<41> WL_O<40> WL_O<39> WL_O<38> WL_O<37> WL_O<36> WL_O<35> ++ WL_O<34> WL_O<33> WL_O<32> WL_O<31> WL_O<30> WL_O<29> WL_O<28> WL_O<27> ++ WL_O<26> WL_O<25> WL_O<24> WL_O<23> WL_O<22> WL_O<21> WL_O<20> WL_O<19> ++ WL_O<18> WL_O<17> WL_O<16> WL_O<15> WL_O<14> WL_O<13> WL_O<12> WL_O<11> ++ WL_O<10> WL_O<9> WL_O<8> WL_O<7> WL_O<6> WL_O<5> WL_O<4> WL_O<3> WL_O<2> ++ WL_O<1> WL_O<0> VDD VSS +XSEL<31> ADDR_N_I<3> ADDR_N_I<2> ADDR_N_I<1> ADDR_N_I<0> CS00<31> ECLK_H<31> ++ ECLK_H<32> ECLK_B<31> ECLK_B<32> WL_O<511> WL_O<510> WL_O<509> WL_O<508> ++ WL_O<507> WL_O<506> WL_O<505> WL_O<504> WL_O<503> WL_O<502> WL_O<501> ++ WL_O<500> WL_O<499> WL_O<498> WL_O<497> WL_O<496> VDD VSS / ++ RM_IHPSG13_1024x32_c2_2P_DEC04 +XSEL<30> ADDR_N_I<3> ADDR_N_I<2> ADDR_N_I<1> ADDR_N_I<0> CS00<30> ECLK_H<30> ++ ECLK_H<31> ECLK_B<30> ECLK_B<31> WL_O<495> WL_O<494> WL_O<493> WL_O<492> ++ WL_O<491> WL_O<490> WL_O<489> WL_O<488> WL_O<487> WL_O<486> WL_O<485> ++ WL_O<484> WL_O<483> WL_O<482> WL_O<481> WL_O<480> VDD VSS / ++ RM_IHPSG13_1024x32_c2_2P_DEC04 +XSEL<29> ADDR_N_I<3> ADDR_N_I<2> ADDR_N_I<1> ADDR_N_I<0> CS00<29> ECLK_H<29> ++ ECLK_H<30> ECLK_B<29> ECLK_B<30> WL_O<479> WL_O<478> WL_O<477> WL_O<476> ++ WL_O<475> WL_O<474> WL_O<473> WL_O<472> WL_O<471> WL_O<470> WL_O<469> ++ WL_O<468> WL_O<467> WL_O<466> WL_O<465> WL_O<464> VDD VSS / ++ RM_IHPSG13_1024x32_c2_2P_DEC04 +XSEL<28> ADDR_N_I<3> ADDR_N_I<2> ADDR_N_I<1> ADDR_N_I<0> CS00<28> ECLK_H<28> ++ ECLK_H<29> ECLK_B<28> ECLK_B<29> WL_O<463> WL_O<462> WL_O<461> WL_O<460> ++ WL_O<459> WL_O<458> WL_O<457> WL_O<456> WL_O<455> WL_O<454> WL_O<453> ++ WL_O<452> WL_O<451> WL_O<450> WL_O<449> WL_O<448> VDD VSS / ++ RM_IHPSG13_1024x32_c2_2P_DEC04 +XSEL<27> ADDR_N_I<3> ADDR_N_I<2> ADDR_N_I<1> ADDR_N_I<0> CS00<27> ECLK_H<27> ++ ECLK_H<28> ECLK_B<27> ECLK_B<28> WL_O<447> WL_O<446> WL_O<445> WL_O<444> ++ WL_O<443> WL_O<442> WL_O<441> WL_O<440> WL_O<439> WL_O<438> WL_O<437> ++ WL_O<436> WL_O<435> WL_O<434> WL_O<433> WL_O<432> VDD VSS / ++ RM_IHPSG13_1024x32_c2_2P_DEC04 +XSEL<26> ADDR_N_I<3> ADDR_N_I<2> ADDR_N_I<1> ADDR_N_I<0> CS00<26> ECLK_H<26> ++ ECLK_H<27> ECLK_B<26> ECLK_B<27> WL_O<431> WL_O<430> WL_O<429> WL_O<428> ++ WL_O<427> WL_O<426> WL_O<425> WL_O<424> WL_O<423> WL_O<422> WL_O<421> ++ WL_O<420> WL_O<419> WL_O<418> WL_O<417> WL_O<416> VDD VSS / ++ RM_IHPSG13_1024x32_c2_2P_DEC04 +XSEL<25> ADDR_N_I<3> ADDR_N_I<2> ADDR_N_I<1> ADDR_N_I<0> CS00<25> ECLK_H<25> ++ ECLK_H<26> ECLK_B<25> ECLK_B<26> WL_O<415> WL_O<414> WL_O<413> WL_O<412> ++ WL_O<411> WL_O<410> WL_O<409> WL_O<408> WL_O<407> WL_O<406> WL_O<405> ++ WL_O<404> WL_O<403> WL_O<402> WL_O<401> WL_O<400> VDD VSS / ++ RM_IHPSG13_1024x32_c2_2P_DEC04 +XSEL<24> ADDR_N_I<3> ADDR_N_I<2> ADDR_N_I<1> ADDR_N_I<0> CS00<24> ECLK_H<24> ++ ECLK_H<25> ECLK_B<24> ECLK_B<25> WL_O<399> WL_O<398> WL_O<397> WL_O<396> ++ WL_O<395> WL_O<394> WL_O<393> WL_O<392> WL_O<391> WL_O<390> WL_O<389> ++ WL_O<388> WL_O<387> WL_O<386> WL_O<385> WL_O<384> VDD VSS / ++ RM_IHPSG13_1024x32_c2_2P_DEC04 +XSEL<23> ADDR_N_I<3> ADDR_N_I<2> ADDR_N_I<1> ADDR_N_I<0> CS00<23> ECLK_H<23> ++ ECLK_H<24> ECLK_B<23> ECLK_B<24> WL_O<383> WL_O<382> WL_O<381> WL_O<380> ++ WL_O<379> WL_O<378> WL_O<377> WL_O<376> WL_O<375> WL_O<374> WL_O<373> ++ WL_O<372> WL_O<371> WL_O<370> WL_O<369> WL_O<368> VDD VSS / ++ RM_IHPSG13_1024x32_c2_2P_DEC04 +XSEL<22> ADDR_N_I<3> ADDR_N_I<2> ADDR_N_I<1> ADDR_N_I<0> CS00<22> ECLK_H<22> ++ ECLK_H<23> ECLK_B<22> ECLK_B<23> WL_O<367> WL_O<366> WL_O<365> WL_O<364> ++ WL_O<363> WL_O<362> WL_O<361> WL_O<360> WL_O<359> WL_O<358> WL_O<357> ++ WL_O<356> WL_O<355> WL_O<354> WL_O<353> WL_O<352> VDD VSS / ++ RM_IHPSG13_1024x32_c2_2P_DEC04 +XSEL<21> ADDR_N_I<3> ADDR_N_I<2> ADDR_N_I<1> ADDR_N_I<0> CS00<21> ECLK_H<21> ++ ECLK_H<22> ECLK_B<21> ECLK_B<22> WL_O<351> WL_O<350> WL_O<349> WL_O<348> ++ WL_O<347> WL_O<346> WL_O<345> WL_O<344> WL_O<343> WL_O<342> WL_O<341> ++ WL_O<340> WL_O<339> WL_O<338> WL_O<337> WL_O<336> VDD VSS / ++ RM_IHPSG13_1024x32_c2_2P_DEC04 +XSEL<20> ADDR_N_I<3> ADDR_N_I<2> ADDR_N_I<1> ADDR_N_I<0> CS00<20> ECLK_H<20> ++ ECLK_H<21> ECLK_B<20> ECLK_B<21> WL_O<335> WL_O<334> WL_O<333> WL_O<332> ++ WL_O<331> WL_O<330> WL_O<329> WL_O<328> WL_O<327> WL_O<326> WL_O<325> ++ WL_O<324> WL_O<323> WL_O<322> WL_O<321> WL_O<320> VDD VSS / ++ RM_IHPSG13_1024x32_c2_2P_DEC04 +XSEL<19> ADDR_N_I<3> ADDR_N_I<2> ADDR_N_I<1> ADDR_N_I<0> CS00<19> ECLK_H<19> ++ ECLK_H<20> ECLK_B<19> ECLK_B<20> WL_O<319> WL_O<318> WL_O<317> WL_O<316> ++ WL_O<315> WL_O<314> WL_O<313> WL_O<312> WL_O<311> WL_O<310> WL_O<309> ++ WL_O<308> WL_O<307> WL_O<306> WL_O<305> WL_O<304> VDD VSS / ++ RM_IHPSG13_1024x32_c2_2P_DEC04 +XSEL<18> ADDR_N_I<3> ADDR_N_I<2> ADDR_N_I<1> ADDR_N_I<0> CS00<18> ECLK_H<18> ++ ECLK_H<19> ECLK_B<18> ECLK_B<19> WL_O<303> WL_O<302> WL_O<301> WL_O<300> ++ WL_O<299> WL_O<298> WL_O<297> WL_O<296> WL_O<295> WL_O<294> WL_O<293> ++ WL_O<292> WL_O<291> WL_O<290> WL_O<289> WL_O<288> VDD VSS / ++ RM_IHPSG13_1024x32_c2_2P_DEC04 +XSEL<17> ADDR_N_I<3> ADDR_N_I<2> ADDR_N_I<1> ADDR_N_I<0> CS00<17> ECLK_H<17> ++ ECLK_H<18> ECLK_B<17> ECLK_B<18> WL_O<287> WL_O<286> WL_O<285> WL_O<284> ++ WL_O<283> WL_O<282> WL_O<281> WL_O<280> WL_O<279> WL_O<278> WL_O<277> ++ WL_O<276> WL_O<275> WL_O<274> WL_O<273> WL_O<272> VDD VSS / ++ RM_IHPSG13_1024x32_c2_2P_DEC04 +XSEL<16> ADDR_N_I<3> ADDR_N_I<2> ADDR_N_I<1> ADDR_N_I<0> CS00<16> ECLK_H<16> ++ ECLK_H<17> ECLK_B<16> ECLK_B<17> WL_O<271> WL_O<270> WL_O<269> WL_O<268> ++ WL_O<267> WL_O<266> WL_O<265> WL_O<264> WL_O<263> WL_O<262> WL_O<261> ++ WL_O<260> WL_O<259> WL_O<258> WL_O<257> WL_O<256> VDD VSS / ++ RM_IHPSG13_1024x32_c2_2P_DEC04 +XSEL<15> ADDR_N_I<3> ADDR_N_I<2> ADDR_N_I<1> ADDR_N_I<0> CS00<15> ECLK_H<15> ++ ECLK_H<16> ECLK_B<15> ECLK_B<16> WL_O<255> WL_O<254> WL_O<253> WL_O<252> ++ WL_O<251> WL_O<250> WL_O<249> WL_O<248> WL_O<247> WL_O<246> WL_O<245> ++ WL_O<244> WL_O<243> WL_O<242> WL_O<241> WL_O<240> VDD VSS / ++ RM_IHPSG13_1024x32_c2_2P_DEC04 +XSEL<14> ADDR_N_I<3> ADDR_N_I<2> ADDR_N_I<1> ADDR_N_I<0> CS00<14> ECLK_H<14> ++ ECLK_H<15> ECLK_B<14> ECLK_B<15> WL_O<239> WL_O<238> WL_O<237> WL_O<236> ++ WL_O<235> WL_O<234> WL_O<233> WL_O<232> WL_O<231> WL_O<230> WL_O<229> ++ WL_O<228> WL_O<227> WL_O<226> WL_O<225> WL_O<224> VDD VSS / ++ RM_IHPSG13_1024x32_c2_2P_DEC04 +XSEL<13> ADDR_N_I<3> ADDR_N_I<2> ADDR_N_I<1> ADDR_N_I<0> CS00<13> ECLK_H<13> ++ ECLK_H<14> ECLK_B<13> ECLK_B<14> WL_O<223> WL_O<222> WL_O<221> WL_O<220> ++ WL_O<219> WL_O<218> WL_O<217> WL_O<216> WL_O<215> WL_O<214> WL_O<213> ++ WL_O<212> WL_O<211> WL_O<210> WL_O<209> WL_O<208> VDD VSS / ++ RM_IHPSG13_1024x32_c2_2P_DEC04 +XSEL<12> ADDR_N_I<3> ADDR_N_I<2> ADDR_N_I<1> ADDR_N_I<0> CS00<12> ECLK_H<12> ++ ECLK_H<13> ECLK_B<12> ECLK_B<13> WL_O<207> WL_O<206> WL_O<205> WL_O<204> ++ WL_O<203> WL_O<202> WL_O<201> WL_O<200> WL_O<199> WL_O<198> WL_O<197> ++ WL_O<196> WL_O<195> WL_O<194> WL_O<193> WL_O<192> VDD VSS / ++ RM_IHPSG13_1024x32_c2_2P_DEC04 +XSEL<11> ADDR_N_I<3> ADDR_N_I<2> ADDR_N_I<1> ADDR_N_I<0> CS00<11> ECLK_H<11> ++ ECLK_H<12> ECLK_B<11> ECLK_B<12> WL_O<191> WL_O<190> WL_O<189> WL_O<188> ++ WL_O<187> WL_O<186> WL_O<185> WL_O<184> WL_O<183> WL_O<182> WL_O<181> ++ WL_O<180> WL_O<179> WL_O<178> WL_O<177> WL_O<176> VDD VSS / ++ RM_IHPSG13_1024x32_c2_2P_DEC04 +XSEL<10> ADDR_N_I<3> ADDR_N_I<2> ADDR_N_I<1> ADDR_N_I<0> CS00<10> ECLK_H<10> ++ ECLK_H<11> ECLK_B<10> ECLK_B<11> WL_O<175> WL_O<174> WL_O<173> WL_O<172> ++ WL_O<171> WL_O<170> WL_O<169> WL_O<168> WL_O<167> WL_O<166> WL_O<165> ++ WL_O<164> WL_O<163> WL_O<162> WL_O<161> WL_O<160> VDD VSS / ++ RM_IHPSG13_1024x32_c2_2P_DEC04 +XSEL<9> ADDR_N_I<3> ADDR_N_I<2> ADDR_N_I<1> ADDR_N_I<0> CS00<9> ECLK_H<9> ++ ECLK_H<10> ECLK_B<9> ECLK_B<10> WL_O<159> WL_O<158> WL_O<157> WL_O<156> ++ WL_O<155> WL_O<154> WL_O<153> WL_O<152> WL_O<151> WL_O<150> WL_O<149> ++ WL_O<148> WL_O<147> WL_O<146> WL_O<145> WL_O<144> VDD VSS / ++ RM_IHPSG13_1024x32_c2_2P_DEC04 +XSEL<8> ADDR_N_I<3> ADDR_N_I<2> ADDR_N_I<1> ADDR_N_I<0> CS00<8> ECLK_H<8> ++ ECLK_H<9> ECLK_B<8> ECLK_B<9> WL_O<143> WL_O<142> WL_O<141> WL_O<140> ++ WL_O<139> WL_O<138> WL_O<137> WL_O<136> WL_O<135> WL_O<134> WL_O<133> ++ WL_O<132> WL_O<131> WL_O<130> WL_O<129> WL_O<128> VDD VSS / ++ RM_IHPSG13_1024x32_c2_2P_DEC04 +XSEL<7> ADDR_N_I<3> ADDR_N_I<2> ADDR_N_I<1> ADDR_N_I<0> CS00<7> ECLK_H<7> ++ ECLK_H<8> ECLK_B<7> ECLK_B<8> WL_O<127> WL_O<126> WL_O<125> WL_O<124> ++ WL_O<123> WL_O<122> WL_O<121> WL_O<120> WL_O<119> WL_O<118> WL_O<117> ++ WL_O<116> WL_O<115> WL_O<114> WL_O<113> WL_O<112> VDD VSS / ++ RM_IHPSG13_1024x32_c2_2P_DEC04 +XSEL<6> ADDR_N_I<3> ADDR_N_I<2> ADDR_N_I<1> ADDR_N_I<0> CS00<6> ECLK_H<6> ++ ECLK_H<7> ECLK_B<6> ECLK_B<7> WL_O<111> WL_O<110> WL_O<109> WL_O<108> ++ WL_O<107> WL_O<106> WL_O<105> WL_O<104> WL_O<103> WL_O<102> WL_O<101> ++ WL_O<100> WL_O<99> WL_O<98> WL_O<97> WL_O<96> VDD VSS / ++ RM_IHPSG13_1024x32_c2_2P_DEC04 +XSEL<5> ADDR_N_I<3> ADDR_N_I<2> ADDR_N_I<1> ADDR_N_I<0> CS00<5> ECLK_H<5> ++ ECLK_H<6> ECLK_B<5> ECLK_B<6> WL_O<95> WL_O<94> WL_O<93> WL_O<92> WL_O<91> ++ WL_O<90> WL_O<89> WL_O<88> WL_O<87> WL_O<86> WL_O<85> WL_O<84> WL_O<83> ++ WL_O<82> WL_O<81> WL_O<80> VDD VSS / RM_IHPSG13_1024x32_c2_2P_DEC04 +XSEL<4> ADDR_N_I<3> ADDR_N_I<2> ADDR_N_I<1> ADDR_N_I<0> CS00<4> ECLK_H<4> ++ ECLK_H<5> ECLK_B<4> ECLK_B<5> WL_O<79> WL_O<78> WL_O<77> WL_O<76> WL_O<75> ++ WL_O<74> WL_O<73> WL_O<72> WL_O<71> WL_O<70> WL_O<69> WL_O<68> WL_O<67> ++ WL_O<66> WL_O<65> WL_O<64> VDD VSS / RM_IHPSG13_1024x32_c2_2P_DEC04 +XSEL<3> ADDR_N_I<3> ADDR_N_I<2> ADDR_N_I<1> ADDR_N_I<0> CS00<3> ECLK_H<3> ++ ECLK_H<4> ECLK_B<3> ECLK_B<4> WL_O<63> WL_O<62> WL_O<61> WL_O<60> WL_O<59> ++ WL_O<58> WL_O<57> WL_O<56> WL_O<55> WL_O<54> WL_O<53> WL_O<52> WL_O<51> ++ WL_O<50> WL_O<49> WL_O<48> VDD VSS / RM_IHPSG13_1024x32_c2_2P_DEC04 +XSEL<2> ADDR_N_I<3> ADDR_N_I<2> ADDR_N_I<1> ADDR_N_I<0> CS00<2> ECLK_H<2> ++ ECLK_H<3> ECLK_B<2> ECLK_B<3> WL_O<47> WL_O<46> WL_O<45> WL_O<44> WL_O<43> ++ WL_O<42> WL_O<41> WL_O<40> WL_O<39> WL_O<38> WL_O<37> WL_O<36> WL_O<35> ++ WL_O<34> WL_O<33> WL_O<32> VDD VSS / RM_IHPSG13_1024x32_c2_2P_DEC04 +XSEL<1> ADDR_N_I<3> ADDR_N_I<2> ADDR_N_I<1> ADDR_N_I<0> CS00<1> ECLK_H<1> ++ ECLK_H<2> ECLK_B<1> ECLK_B<2> WL_O<31> WL_O<30> WL_O<29> WL_O<28> WL_O<27> ++ WL_O<26> WL_O<25> WL_O<24> WL_O<23> WL_O<22> WL_O<21> WL_O<20> WL_O<19> ++ WL_O<18> WL_O<17> WL_O<16> VDD VSS / RM_IHPSG13_1024x32_c2_2P_DEC04 +XSEL<0> ADDR_N_I<3> ADDR_N_I<2> ADDR_N_I<1> ADDR_N_I<0> CS00<0> ECLK_I ++ ECLK_H<1> ECLK_B<0> ECLK_B<1> WL_O<15> WL_O<14> WL_O<13> WL_O<12> WL_O<11> ++ WL_O<10> WL_O<9> WL_O<8> WL_O<7> WL_O<6> WL_O<5> WL_O<4> WL_O<3> WL_O<2> ++ WL_O<1> WL_O<0> VDD VSS / RM_IHPSG13_1024x32_c2_2P_DEC04 +XDEC10<9> ADDR_N_I<7> ADDR_N_I<6> CS04<1> CS02<6> VDD VSS / ++ RM_IHPSG13_1024x32_c2_2P_DEC02 +XDEC10<8> ADDR_N_I<7> ADDR_N_I<6> CS04<0> CS02<2> VDD VSS / ++ RM_IHPSG13_1024x32_c2_2P_DEC02 +XDEC10<7> ADDR_N_I<5> ADDR_N_I<4> CS02<7> CS00<30> VDD VSS / ++ RM_IHPSG13_1024x32_c2_2P_DEC02 +XDEC10<6> ADDR_N_I<5> ADDR_N_I<4> CS02<6> CS00<26> VDD VSS / ++ RM_IHPSG13_1024x32_c2_2P_DEC02 +XDEC10<5> ADDR_N_I<5> ADDR_N_I<4> CS02<5> CS00<22> VDD VSS / ++ RM_IHPSG13_1024x32_c2_2P_DEC02 +XDEC10<4> ADDR_N_I<5> ADDR_N_I<4> CS02<4> CS00<18> VDD VSS / ++ RM_IHPSG13_1024x32_c2_2P_DEC02 +XDEC10<3> ADDR_N_I<5> ADDR_N_I<4> CS02<3> CS00<14> VDD VSS / ++ RM_IHPSG13_1024x32_c2_2P_DEC02 +XDEC10<2> ADDR_N_I<5> ADDR_N_I<4> CS02<2> CS00<10> VDD VSS / ++ RM_IHPSG13_1024x32_c2_2P_DEC02 +XDEC10<1> ADDR_N_I<5> ADDR_N_I<4> CS02<1> CS00<6> VDD VSS / ++ RM_IHPSG13_1024x32_c2_2P_DEC02 +XDEC10<0> ADDR_N_I<5> ADDR_N_I<4> CS02<0> CS00<2> VDD VSS / ++ RM_IHPSG13_1024x32_c2_2P_DEC02 +XDEC01<10> ADDR_N_I<9> ADDR_N_I<8> CS_I CS04<1> VDD VSS / ++ RM_IHPSG13_1024x32_c2_2P_DEC01 +XDEC01<9> ADDR_N_I<7> ADDR_N_I<6> CS04<1> CS02<5> VDD VSS / ++ RM_IHPSG13_1024x32_c2_2P_DEC01 +XDEC01<8> ADDR_N_I<7> ADDR_N_I<6> CS04<0> CS02<1> VDD VSS / ++ RM_IHPSG13_1024x32_c2_2P_DEC01 +XDEC01<7> ADDR_N_I<5> ADDR_N_I<4> CS02<7> CS00<29> VDD VSS / ++ RM_IHPSG13_1024x32_c2_2P_DEC01 +XDEC01<6> ADDR_N_I<5> ADDR_N_I<4> CS02<6> CS00<25> VDD VSS / ++ RM_IHPSG13_1024x32_c2_2P_DEC01 +XDEC01<5> ADDR_N_I<5> ADDR_N_I<4> CS02<5> CS00<21> VDD VSS / ++ RM_IHPSG13_1024x32_c2_2P_DEC01 +XDEC01<4> ADDR_N_I<5> ADDR_N_I<4> CS02<4> CS00<17> VDD VSS / ++ RM_IHPSG13_1024x32_c2_2P_DEC01 +XDEC01<3> ADDR_N_I<5> ADDR_N_I<4> CS02<3> CS00<13> VDD VSS / ++ RM_IHPSG13_1024x32_c2_2P_DEC01 +XDEC01<2> ADDR_N_I<5> ADDR_N_I<4> CS02<2> CS00<9> VDD VSS / ++ RM_IHPSG13_1024x32_c2_2P_DEC01 +XDEC01<1> ADDR_N_I<5> ADDR_N_I<4> CS02<1> CS00<5> VDD VSS / ++ RM_IHPSG13_1024x32_c2_2P_DEC01 +XDEC01<0> ADDR_N_I<5> ADDR_N_I<4> CS02<0> CS00<1> VDD VSS / ++ RM_IHPSG13_1024x32_c2_2P_DEC01 +XL2<258> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<257> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<256> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<255> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<254> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<253> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<252> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<251> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<250> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<249> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<248> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<247> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<246> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<245> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<244> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<243> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<242> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<241> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<240> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<239> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<238> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<237> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<236> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<235> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<234> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<233> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<232> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<231> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<230> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<229> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<228> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<227> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<226> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<225> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<224> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<223> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<222> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<221> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<220> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<219> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<218> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<217> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<216> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<215> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<214> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<213> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<212> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<211> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<210> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<209> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<208> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<207> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<206> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<205> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<204> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<203> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<202> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<201> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<200> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<199> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<198> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<197> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<196> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<195> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<194> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<193> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<192> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<191> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<190> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<189> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<188> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<187> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<186> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<185> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<184> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<183> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<182> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<181> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<180> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<179> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<178> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<177> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<176> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<175> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<174> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<173> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<172> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<171> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<170> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<169> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<168> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<167> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<166> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<165> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<164> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<163> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<162> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<161> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<160> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<159> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<158> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<157> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<156> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<155> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<154> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<153> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<152> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<151> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<150> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<149> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<148> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<147> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<146> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<145> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<144> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<143> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<142> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<141> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<140> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<139> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<138> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<137> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<136> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<135> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<134> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<133> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<132> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<131> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<130> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<129> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<128> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<127> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<126> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<125> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<124> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<123> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<122> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<121> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<120> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<119> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<118> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<117> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<116> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<115> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<114> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<113> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<112> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<111> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<110> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<109> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<108> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<107> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<106> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<105> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<104> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<103> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<102> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<101> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<100> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<99> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<98> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<97> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<96> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<95> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<94> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<93> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<92> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<91> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<90> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<89> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<88> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<87> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<86> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<85> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<84> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<83> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<82> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<81> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<80> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<79> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<78> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<77> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<76> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<75> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<74> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<73> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<72> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<71> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<70> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<69> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<68> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<67> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<66> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<65> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<64> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<63> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<62> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<61> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<60> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<59> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<58> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<57> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<56> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<55> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<54> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<53> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<52> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<51> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<50> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<49> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<48> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<47> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<46> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<45> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<44> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<43> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<42> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<41> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<40> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<39> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<38> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<37> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<36> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<35> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<34> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<33> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<32> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<31> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<30> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<29> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<28> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<27> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<26> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<25> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<24> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<23> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<22> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<21> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<20> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<19> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<18> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<17> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<16> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<15> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<14> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<13> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<12> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<11> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<10> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<9> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<8> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<7> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<6> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<5> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<4> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<3> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<2> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<1> VDD VSS / RSC_IHPSG13_FILLCAP8 +XDEC00<10> ADDR_N_I<9> ADDR_N_I<8> CS_I CS04<0> VDD VSS / ++ RM_IHPSG13_1024x32_c2_2P_DEC00 +XDEC00<9> ADDR_N_I<7> ADDR_N_I<6> CS04<1> CS02<4> VDD VSS / ++ RM_IHPSG13_1024x32_c2_2P_DEC00 +XDEC00<8> ADDR_N_I<7> ADDR_N_I<6> CS04<0> CS02<0> VDD VSS / ++ RM_IHPSG13_1024x32_c2_2P_DEC00 +XDEC00<7> ADDR_N_I<5> ADDR_N_I<4> CS02<7> CS00<28> VDD VSS / ++ RM_IHPSG13_1024x32_c2_2P_DEC00 +XDEC00<6> ADDR_N_I<5> ADDR_N_I<4> CS02<6> CS00<24> VDD VSS / ++ RM_IHPSG13_1024x32_c2_2P_DEC00 +XDEC00<5> ADDR_N_I<5> ADDR_N_I<4> CS02<5> CS00<20> VDD VSS / ++ RM_IHPSG13_1024x32_c2_2P_DEC00 +XDEC00<4> ADDR_N_I<5> ADDR_N_I<4> CS02<4> CS00<16> VDD VSS / ++ RM_IHPSG13_1024x32_c2_2P_DEC00 +XDEC00<3> ADDR_N_I<5> ADDR_N_I<4> CS02<3> CS00<12> VDD VSS / ++ RM_IHPSG13_1024x32_c2_2P_DEC00 +XDEC00<2> ADDR_N_I<5> ADDR_N_I<4> CS02<2> CS00<8> VDD VSS / ++ RM_IHPSG13_1024x32_c2_2P_DEC00 +XDEC00<1> ADDR_N_I<5> ADDR_N_I<4> CS02<1> CS00<4> VDD VSS / ++ RM_IHPSG13_1024x32_c2_2P_DEC00 +XDEC00<0> ADDR_N_I<5> ADDR_N_I<4> CS02<0> CS00<0> VDD VSS / ++ RM_IHPSG13_1024x32_c2_2P_DEC00 +XDEC11<9> ADDR_N_I<7> ADDR_N_I<6> CS04<1> CS02<7> VDD VSS / ++ RM_IHPSG13_1024x32_c2_2P_DEC03 +XDEC11<8> ADDR_N_I<7> ADDR_N_I<6> CS04<0> CS02<3> VDD VSS / ++ RM_IHPSG13_1024x32_c2_2P_DEC03 +XDEC11<7> ADDR_N_I<5> ADDR_N_I<4> CS02<7> CS00<31> VDD VSS / ++ RM_IHPSG13_1024x32_c2_2P_DEC03 +XDEC11<6> ADDR_N_I<5> ADDR_N_I<4> CS02<6> CS00<27> VDD VSS / ++ RM_IHPSG13_1024x32_c2_2P_DEC03 +XDEC11<5> ADDR_N_I<5> ADDR_N_I<4> CS02<5> CS00<23> VDD VSS / ++ RM_IHPSG13_1024x32_c2_2P_DEC03 +XDEC11<4> ADDR_N_I<5> ADDR_N_I<4> CS02<4> CS00<19> VDD VSS / ++ RM_IHPSG13_1024x32_c2_2P_DEC03 +XDEC11<3> ADDR_N_I<5> ADDR_N_I<4> CS02<3> CS00<15> VDD VSS / ++ RM_IHPSG13_1024x32_c2_2P_DEC03 +XDEC11<2> ADDR_N_I<5> ADDR_N_I<4> CS02<2> CS00<11> VDD VSS / ++ RM_IHPSG13_1024x32_c2_2P_DEC03 +XDEC11<1> ADDR_N_I<5> ADDR_N_I<4> CS02<1> CS00<7> VDD VSS / ++ RM_IHPSG13_1024x32_c2_2P_DEC03 +XDEC11<0> ADDR_N_I<5> ADDR_N_I<4> CS02<0> CS00<3> VDD VSS / ++ RM_IHPSG13_1024x32_c2_2P_DEC03 +XI0 ADDR_N_I<9> VDD VSS / RSC_IHPSG13_TIEL +.ENDS +.SUBCKT RM_IHPSG13_1024x32_c2_2P_ROWREG9 ACLK_N_I ADDR_I<8> ADDR_I<7> ADDR_I<6> ADDR_I<5> ++ ADDR_I<4> ADDR_I<3> ADDR_I<2> ADDR_I<1> ADDR_I<0> ADDR_N_O<8> ADDR_N_O<7> ++ ADDR_N_O<6> ADDR_N_O<5> ADDR_N_O<4> ADDR_N_O<3> ADDR_N_O<2> ADDR_N_O<1> ++ ADDR_N_O<0> BIST_ADDR_I<8> BIST_ADDR_I<7> BIST_ADDR_I<6> BIST_ADDR_I<5> ++ BIST_ADDR_I<4> BIST_ADDR_I<3> BIST_ADDR_I<2> BIST_ADDR_I<1> BIST_ADDR_I<0> ++ BIST_EN_I VDD VSS +XDFF<8> BIST_EN_I BIST_ADDR_I<8> ACLK_N_I ADDR_I<8> q_int<8> net04<0> VDD ++ VSS / RSC_IHPSG13_DFNQMX2IX1 +XDFF<7> BIST_EN_I BIST_ADDR_I<7> ACLK_N_I ADDR_I<7> q_int<7> net04<1> VDD ++ VSS / RSC_IHPSG13_DFNQMX2IX1 +XDFF<6> BIST_EN_I BIST_ADDR_I<6> ACLK_N_I ADDR_I<6> q_int<6> net04<2> VDD ++ VSS / RSC_IHPSG13_DFNQMX2IX1 +XDFF<5> BIST_EN_I BIST_ADDR_I<5> ACLK_N_I ADDR_I<5> q_int<5> net04<3> VDD ++ VSS / RSC_IHPSG13_DFNQMX2IX1 +XDFF<4> BIST_EN_I BIST_ADDR_I<4> ACLK_N_I ADDR_I<4> q_int<4> net04<4> VDD ++ VSS / RSC_IHPSG13_DFNQMX2IX1 +XDFF<3> BIST_EN_I BIST_ADDR_I<3> ACLK_N_I ADDR_I<3> q_int<3> net04<5> VDD ++ VSS / RSC_IHPSG13_DFNQMX2IX1 +XDFF<2> BIST_EN_I BIST_ADDR_I<2> ACLK_N_I ADDR_I<2> q_int<2> net04<6> VDD ++ VSS / RSC_IHPSG13_DFNQMX2IX1 +XDFF<1> BIST_EN_I BIST_ADDR_I<1> ACLK_N_I ADDR_I<1> q_int<1> net04<7> VDD ++ VSS / RSC_IHPSG13_DFNQMX2IX1 +XDFF<0> BIST_EN_I BIST_ADDR_I<0> ACLK_N_I ADDR_I<0> q_int<0> net04<8> VDD ++ VSS / RSC_IHPSG13_DFNQMX2IX1 +XDRV<8> qn_int<8> ADDR_N_O<8> VDD VSS / RSC_IHPSG13_CINVX8 +XDRV<7> qn_int<7> ADDR_N_O<7> VDD VSS / RSC_IHPSG13_CINVX8 +XDRV<6> qn_int<6> ADDR_N_O<6> VDD VSS / RSC_IHPSG13_CINVX8 +XDRV<5> qn_int<5> ADDR_N_O<5> VDD VSS / RSC_IHPSG13_CINVX8 +XDRV<4> qn_int<4> ADDR_N_O<4> VDD VSS / RSC_IHPSG13_CINVX8 +XDRV<3> qn_int<3> ADDR_N_O<3> VDD VSS / RSC_IHPSG13_CINVX8 +XDRV<2> qn_int<2> ADDR_N_O<2> VDD VSS / RSC_IHPSG13_CINVX8 +XDRV<1> qn_int<1> ADDR_N_O<1> VDD VSS / RSC_IHPSG13_CINVX8 +XDRV<0> qn_int<0> ADDR_N_O<0> VDD VSS / RSC_IHPSG13_CINVX8 +XINV<8> q_int<8> qn_int<8> VDD VSS / RSC_IHPSG13_CINVX2 +XINV<7> q_int<7> qn_int<7> VDD VSS / RSC_IHPSG13_CINVX2 +XINV<6> q_int<6> qn_int<6> VDD VSS / RSC_IHPSG13_CINVX2 +XINV<5> q_int<5> qn_int<5> VDD VSS / RSC_IHPSG13_CINVX2 +XINV<4> q_int<4> qn_int<4> VDD VSS / RSC_IHPSG13_CINVX2 +XINV<3> q_int<3> qn_int<3> VDD VSS / RSC_IHPSG13_CINVX2 +XINV<2> q_int<2> qn_int<2> VDD VSS / RSC_IHPSG13_CINVX2 +XINV<1> q_int<1> qn_int<1> VDD VSS / RSC_IHPSG13_CINVX2 +XINV<0> q_int<0> qn_int<0> VDD VSS / RSC_IHPSG13_CINVX2 +.ENDS + +.SUBCKT RM_IHPSG13_1024x32_c2_2P_DLY_MUX A SEL Z VDD VSS +XI11 net4 Z VDD VSS / RSC_IHPSG13_CINVX2 +XI8 A D<3> SEL net4 VDD VSS / RSC_IHPSG13_MX2IX1 +XI20<3> D<2> D<3> VDD VSS / RSC_IHPSG13_CDLYX1 +XI20<2> D<1> D<2> VDD VSS / RSC_IHPSG13_CDLYX1 +XI20<1> A D<1> VDD VSS / RSC_IHPSG13_CDLYX1 +.ENDS +.SUBCKT RM_IHPSG13_1024x32_c2_2P_CTRL ACLK_N BIST_CK_I BIST_CS_I BIST_EN BIST_RE_I ++ BIST_WE_I B_TIEL_O CK_I CS_I DCLK ECLK PULSE_H PULSE_L PULSE_O RCLK RE_I ++ ROW_CS WCLK WE_I VDD VSS +XI17 ck_regs we col_we VDD VSS / RSC_IHPSG13_DFNQX2 +XI16 ck_regs re col_re VDD VSS / RSC_IHPSG13_DFNQX2 +XI18 ck_regs cs net7 VDD VSS / RSC_IHPSG13_DFNQX2 +XI71 ACLK_N net012 PULSE_O VDD VSS / RSC_IHPSG13_DFNQX2 +XI77 col_we net017 net016 VDD VSS / RSC_IHPSG13_CNAND2X2 +XI76 col_re net017 net018 VDD VSS / RSC_IHPSG13_CNAND2X2 +XI15 ck_dly WEorREandCS aclk VDD VSS / RSC_IHPSG13_CGATEPX4 +XI14 ck WEandCS DCLK VDD VSS / RSC_IHPSG13_CGATEPX4 +XI60 net7 ROW_CS VDD VSS / RSC_IHPSG13_CBUFX8 +XI73 PULSE_O net012 VDD VSS / RSC_IHPSG13_CINVX2 +XI8 net017 net8 VDD VSS / RSC_IHPSG13_CINVX2 +XCAPS4<7> VDD VSS / RSC_IHPSG13_FILLCAP4 +XCAPS4<6> VDD VSS / RSC_IHPSG13_FILLCAP4 +XCAPS4<5> VDD VSS / RSC_IHPSG13_FILLCAP4 +XCAPS4<4> VDD VSS / RSC_IHPSG13_FILLCAP4 +XCAPS4<3> VDD VSS / RSC_IHPSG13_FILLCAP4 +XCAPS4<2> VDD VSS / RSC_IHPSG13_FILLCAP4 +XCAPS4<1> VDD VSS / RSC_IHPSG13_FILLCAP4 +XBM_TIEL B_TIEL_O VDD VSS / RSC_IHPSG13_TIEL +XI64 ck ck_dly VDD VSS / RSC_IHPSG13_CDLYX2 +XI86 CS_I BIST_CS_I BIST_EN cs VDD VSS / RSC_IHPSG13_MX2X2 +XI87 CK_I BIST_CK_I BIST_EN ck VDD VSS / RSC_IHPSG13_MX2X2 +XI85 WE_I BIST_WE_I BIST_EN we VDD VSS / RSC_IHPSG13_MX2X2 +XI84 RE_I BIST_RE_I BIST_EN re VDD VSS / RSC_IHPSG13_MX2X2 +XI48 ck_dly ck_regs VDD VSS / RSC_IHPSG13_CINVX4 +XI81 net016 WCLK VDD VSS / RSC_IHPSG13_CINVX4 +XI80 net018 RCLK VDD VSS / RSC_IHPSG13_CINVX4 +XI78 net8 net020 VDD VSS / RSC_IHPSG13_CINVX4 +XCAPS8<7> VDD VSS / RSC_IHPSG13_FILLCAP8 +XCAPS8<6> VDD VSS / RSC_IHPSG13_FILLCAP8 +XCAPS8<5> VDD VSS / RSC_IHPSG13_FILLCAP8 +XCAPS8<4> VDD VSS / RSC_IHPSG13_FILLCAP8 +XCAPS8<3> VDD VSS / RSC_IHPSG13_FILLCAP8 +XCAPS8<2> VDD VSS / RSC_IHPSG13_FILLCAP8 +XCAPS8<1> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI6 PULSE_L PULSE_H net017 VDD VSS / RSC_IHPSG13_XOR2X2 +XI22 we cs WEandCS VDD VSS / RSC_IHPSG13_AND2X2 +XI79 net020 ECLK VDD VSS / RSC_IHPSG13_CINVX8 +XI63 aclk ACLK_N VDD VSS / RSC_IHPSG13_CINVX8 +XI21 re we cs WEorREandCS VDD VSS / RSC_IHPSG13_OA12X1 +.ENDS +.SUBCKT RM_IHPSG13_1024x32_c2_2P_COLDEC5 ACLK_N ADDR<4> ADDR<3> ADDR<2> ADDR<1> ADDR<0> ++ ADDR_COL<1> ADDR_COL<0> ADDR_DEC<7> ADDR_DEC<6> ADDR_DEC<5> ADDR_DEC<4> ++ ADDR_DEC<3> ADDR_DEC<2> ADDR_DEC<1> ADDR_DEC<0> BIST_ADDR<4> BIST_ADDR<3> ++ BIST_ADDR<2> BIST_ADDR<1> BIST_ADDR<0> BIST_EN_I VDD VSS +XI17<4> VDD VSS / RSC_IHPSG13_FILLCAP4 +XI17<3> VDD VSS / RSC_IHPSG13_FILLCAP4 +XI17<2> VDD VSS / RSC_IHPSG13_FILLCAP4 +XI17<1> VDD VSS / RSC_IHPSG13_FILLCAP4 +XI1<7> PADR<0> PADR<1> PADR<2> addr_n<7> VDD VSS / RSC_IHPSG13_NAND3X2 +XI1<6> NADR<0> PADR<1> PADR<2> addr_n<6> VDD VSS / RSC_IHPSG13_NAND3X2 +XI1<5> PADR<0> NADR<1> PADR<2> addr_n<5> VDD VSS / RSC_IHPSG13_NAND3X2 +XI1<4> NADR<0> NADR<1> PADR<2> addr_n<4> VDD VSS / RSC_IHPSG13_NAND3X2 +XI1<3> PADR<0> PADR<1> NADR<2> addr_n<3> VDD VSS / RSC_IHPSG13_NAND3X2 +XI1<2> NADR<0> PADR<1> NADR<2> addr_n<2> VDD VSS / RSC_IHPSG13_NAND3X2 +XI1<1> PADR<0> NADR<1> NADR<2> addr_n<1> VDD VSS / RSC_IHPSG13_NAND3X2 +XI1<0> NADR<0> NADR<1> NADR<2> addr_n<0> VDD VSS / RSC_IHPSG13_NAND3X2 +XDFF<4> BIST_EN_I BIST_ADDR<4> ACLK_N ADDR<4> addr_int<1> net13<0> VDD ++ VSS / RSC_IHPSG13_DFNQMX2IX1 +XDFF<3> BIST_EN_I BIST_ADDR<3> ACLK_N ADDR<3> addr_int<0> net13<1> VDD ++ VSS / RSC_IHPSG13_DFNQMX2IX1 +XDFF<2> BIST_EN_I BIST_ADDR<2> ACLK_N ADDR<2> padr_int<2> net13<2> VDD ++ VSS / RSC_IHPSG13_DFNQMX2IX1 +XDFF<1> BIST_EN_I BIST_ADDR<1> ACLK_N ADDR<1> padr_int<1> net13<3> VDD ++ VSS / RSC_IHPSG13_DFNQMX2IX1 +XDFF<0> BIST_EN_I BIST_ADDR<0> ACLK_N ADDR<0> padr_int<0> net13<4> VDD ++ VSS / RSC_IHPSG13_DFNQMX2IX1 +XI3<2> padr_int<2> NADR<2> VDD VSS / RSC_IHPSG13_INVX2 +XI3<1> padr_int<1> NADR<1> VDD VSS / RSC_IHPSG13_INVX2 +XI3<0> padr_int<0> NADR<0> VDD VSS / RSC_IHPSG13_INVX2 +XI2<7> addr_n<7> ADDR_DEC<7> VDD VSS / RSC_IHPSG13_INVX2 +XI2<6> addr_n<6> ADDR_DEC<6> VDD VSS / RSC_IHPSG13_INVX2 +XI2<5> addr_n<5> ADDR_DEC<5> VDD VSS / RSC_IHPSG13_INVX2 +XI2<4> addr_n<4> ADDR_DEC<4> VDD VSS / RSC_IHPSG13_INVX2 +XI2<3> addr_n<3> ADDR_DEC<3> VDD VSS / RSC_IHPSG13_INVX2 +XI2<2> addr_n<2> ADDR_DEC<2> VDD VSS / RSC_IHPSG13_INVX2 +XI2<1> addr_n<1> ADDR_DEC<1> VDD VSS / RSC_IHPSG13_INVX2 +XI2<0> addr_n<0> ADDR_DEC<0> VDD VSS / RSC_IHPSG13_INVX2 +XI15<2> NADR<2> PADR<2> VDD VSS / RSC_IHPSG13_INVX2 +XI15<1> NADR<1> PADR<1> VDD VSS / RSC_IHPSG13_INVX2 +XI15<0> NADR<0> PADR<0> VDD VSS / RSC_IHPSG13_INVX2 +XI13<1> addr_int<1> ADDR_COL<1> VDD VSS / RSC_IHPSG13_CBUFX2 +XI13<0> addr_int<0> ADDR_COL<0> VDD VSS / RSC_IHPSG13_CBUFX2 +XI14<5> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI14<4> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI14<3> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI14<2> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI14<1> VDD VSS / RSC_IHPSG13_FILLCAP8 +.ENDS +.SUBCKT RM_IHPSG13_1024x32_c2_2P_BLDRV A_BLC<3> A_BLC<2> A_BLC<1> A_BLC<0> A_BLC_SEL ++ A_BLT<3> A_BLT<2> A_BLT<1> A_BLT<0> A_BLT_SEL A_PRE_N A_SEL_P<3> A_SEL_P<2> ++ A_SEL_P<1> A_SEL_P<0> A_WR_ONE A_WR_ZERO B_BLC<3> B_BLC<2> B_BLC<1> B_BLC<0> ++ B_BLC_SEL B_BLT<3> B_BLT<2> B_BLT<1> B_BLT<0> B_BLT_SEL B_PRE_N B_SEL_P<3> ++ B_SEL_P<2> B_SEL_P<1> B_SEL_P<0> B_WR_ONE B_WR_ZERO VDD VSS +MA_CWN<3> A_BLC<3> A_BLC_NMOS_DRIVE<3> VSS VSS sg13_lv_nmos m=1 ++ w=4.82u l=130.00n ng=2 nrd=0 nrs=0 +MA_CWN<2> A_BLC<2> A_BLC_NMOS_DRIVE<2> VSS VSS sg13_lv_nmos m=1 ++ w=4.82u l=130.00n ng=2 nrd=0 nrs=0 +MA_CWN<1> A_BLC<1> A_BLC_NMOS_DRIVE<1> VSS VSS sg13_lv_nmos m=1 ++ w=4.82u l=130.00n ng=2 nrd=0 nrs=0 +MA_CWN<0> A_BLC<0> A_BLC_NMOS_DRIVE<0> VSS VSS sg13_lv_nmos m=1 ++ w=4.82u l=130.00n ng=2 nrd=0 nrs=0 +MA_TWN<3> A_BLT<3> A_BLT_NMOS_DRIVE<3> VSS VSS sg13_lv_nmos m=1 ++ w=4.82u l=130.00n ng=2 nrd=0 nrs=0 +MA_TWN<2> A_BLT<2> A_BLT_NMOS_DRIVE<2> VSS VSS sg13_lv_nmos m=1 ++ w=4.82u l=130.00n ng=2 nrd=0 nrs=0 +MA_TWN<1> A_BLT<1> A_BLT_NMOS_DRIVE<1> VSS VSS sg13_lv_nmos m=1 ++ w=4.82u l=130.00n ng=2 nrd=0 nrs=0 +MA_TWN<0> A_BLT<0> A_BLT_NMOS_DRIVE<0> VSS VSS sg13_lv_nmos m=1 ++ w=4.82u l=130.00n ng=2 nrd=0 nrs=0 +MB_TWN<3> B_BLT<3> B_BLT_NMOS_DRIVE<3> VSS VSS sg13_lv_nmos m=1 ++ w=4.82u l=130.00n ng=2 nrd=0 nrs=0 +MB_TWN<2> B_BLT<2> B_BLT_NMOS_DRIVE<2> VSS VSS sg13_lv_nmos m=1 ++ w=4.82u l=130.00n ng=2 nrd=0 nrs=0 +MB_TWN<1> B_BLT<1> B_BLT_NMOS_DRIVE<1> VSS VSS sg13_lv_nmos m=1 ++ w=4.82u l=130.00n ng=2 nrd=0 nrs=0 +MB_TWN<0> B_BLT<0> B_BLT_NMOS_DRIVE<0> VSS VSS sg13_lv_nmos m=1 ++ w=4.82u l=130.00n ng=2 nrd=0 nrs=0 +MB_CWN<3> B_BLC<3> B_BLC_NMOS_DRIVE<3> VSS VSS sg13_lv_nmos m=1 ++ w=4.82u l=130.00n ng=2 nrd=0 nrs=0 +MB_CWN<2> B_BLC<2> B_BLC_NMOS_DRIVE<2> VSS VSS sg13_lv_nmos m=1 ++ w=4.82u l=130.00n ng=2 nrd=0 nrs=0 +MB_CWN<1> B_BLC<1> B_BLC_NMOS_DRIVE<1> VSS VSS sg13_lv_nmos m=1 ++ w=4.82u l=130.00n ng=2 nrd=0 nrs=0 +MB_CWN<0> B_BLC<0> B_BLC_NMOS_DRIVE<0> VSS VSS sg13_lv_nmos m=1 ++ w=4.82u l=130.00n ng=2 nrd=0 nrs=0 +MA_CPR<3> A_BLC<3> A_PRE_N VDD VDD sg13_lv_pmos m=1 w=3.000u l=130.00n ++ ng=2 nrd=0 nrs=0 +MA_CPR<2> A_BLC<2> A_PRE_N VDD VDD sg13_lv_pmos m=1 w=3.000u l=130.00n ++ ng=2 nrd=0 nrs=0 +MA_CPR<1> A_BLC<1> A_PRE_N VDD VDD sg13_lv_pmos m=1 w=3.000u l=130.00n ++ ng=2 nrd=0 nrs=0 +MA_CPR<0> A_BLC<0> A_PRE_N VDD VDD sg13_lv_pmos m=1 w=3.000u l=130.00n ++ ng=2 nrd=0 nrs=0 +MA_TWP<3> A_BLT<3> A_BLT_PMOS_DRIVE<3> VDD VDD sg13_lv_pmos m=1 w=1.5u ++ l=130.00n ng=1 nrd=0 nrs=0 +MA_TWP<2> A_BLT<2> A_BLT_PMOS_DRIVE<2> VDD VDD sg13_lv_pmos m=1 w=1.5u ++ l=130.00n ng=1 nrd=0 nrs=0 +MA_TWP<1> A_BLT<1> A_BLT_PMOS_DRIVE<1> VDD VDD sg13_lv_pmos m=1 w=1.5u ++ l=130.00n ng=1 nrd=0 nrs=0 +MA_TWP<0> A_BLT<0> A_BLT_PMOS_DRIVE<0> VDD VDD sg13_lv_pmos m=1 w=1.5u ++ l=130.00n ng=1 nrd=0 nrs=0 +MA_CWP<3> A_BLC<3> A_BLC_PMOS_DRIVE<3> VDD VDD sg13_lv_pmos m=1 w=1.5u ++ l=130.00n ng=1 nrd=0 nrs=0 +MA_CWP<2> A_BLC<2> A_BLC_PMOS_DRIVE<2> VDD VDD sg13_lv_pmos m=1 w=1.5u ++ l=130.00n ng=1 nrd=0 nrs=0 +MA_CWP<1> A_BLC<1> A_BLC_PMOS_DRIVE<1> VDD VDD sg13_lv_pmos m=1 w=1.5u ++ l=130.00n ng=1 nrd=0 nrs=0 +MA_CWP<0> A_BLC<0> A_BLC_PMOS_DRIVE<0> VDD VDD sg13_lv_pmos m=1 w=1.5u ++ l=130.00n ng=1 nrd=0 nrs=0 +MA_TPR<3> A_BLT<3> A_PRE_N VDD VDD sg13_lv_pmos m=1 w=3.000u l=130.00n ++ ng=2 nrd=0 nrs=0 +MA_TPR<2> A_BLT<2> A_PRE_N VDD VDD sg13_lv_pmos m=1 w=3.000u l=130.00n ++ ng=2 nrd=0 nrs=0 +MA_TPR<1> A_BLT<1> A_PRE_N VDD VDD sg13_lv_pmos m=1 w=3.000u l=130.00n ++ ng=2 nrd=0 nrs=0 +MA_TPR<0> A_BLT<0> A_PRE_N VDD VDD sg13_lv_pmos m=1 w=3.000u l=130.00n ++ ng=2 nrd=0 nrs=0 +MA_TSP<3> A_BLT_SEL A_SEL_N<3> A_BLT<3> VDD sg13_lv_pmos m=1 w=1.5u ++ l=130.00n ng=1 nrd=0 nrs=0 +MA_TSP<2> A_BLT_SEL A_SEL_N<2> A_BLT<2> VDD sg13_lv_pmos m=1 w=1.5u ++ l=130.00n ng=1 nrd=0 nrs=0 +MA_TSP<1> A_BLT_SEL A_SEL_N<1> A_BLT<1> VDD sg13_lv_pmos m=1 w=1.5u ++ l=130.00n ng=1 nrd=0 nrs=0 +MA_TSP<0> A_BLT_SEL A_SEL_N<0> A_BLT<0> VDD sg13_lv_pmos m=1 w=1.5u ++ l=130.00n ng=1 nrd=0 nrs=0 +MA_CSP<3> A_BLC_SEL A_SEL_N<3> A_BLC<3> VDD sg13_lv_pmos m=1 w=1.5u ++ l=130.00n ng=1 nrd=0 nrs=0 +MA_CSP<2> A_BLC_SEL A_SEL_N<2> A_BLC<2> VDD sg13_lv_pmos m=1 w=1.5u ++ l=130.00n ng=1 nrd=0 nrs=0 +MA_CSP<1> A_BLC_SEL A_SEL_N<1> A_BLC<1> VDD sg13_lv_pmos m=1 w=1.5u ++ l=130.00n ng=1 nrd=0 nrs=0 +MA_CSP<0> A_BLC_SEL A_SEL_N<0> A_BLC<0> VDD sg13_lv_pmos m=1 w=1.5u ++ l=130.00n ng=1 nrd=0 nrs=0 +MB_CWP<3> B_BLC<3> B_BLC_PMOS_DRIVE<3> VDD VDD sg13_lv_pmos m=1 w=1.5u ++ l=130.00n ng=1 nrd=0 nrs=0 +MB_CWP<2> B_BLC<2> B_BLC_PMOS_DRIVE<2> VDD VDD sg13_lv_pmos m=1 w=1.5u ++ l=130.00n ng=1 nrd=0 nrs=0 +MB_CWP<1> B_BLC<1> B_BLC_PMOS_DRIVE<1> VDD VDD sg13_lv_pmos m=1 w=1.5u ++ l=130.00n ng=1 nrd=0 nrs=0 +MB_CWP<0> B_BLC<0> B_BLC_PMOS_DRIVE<0> VDD VDD sg13_lv_pmos m=1 w=1.5u ++ l=130.00n ng=1 nrd=0 nrs=0 +MB_TWP<3> B_BLT<3> B_BLT_PMOS_DRIVE<3> VDD VDD sg13_lv_pmos m=1 w=1.5u ++ l=130.00n ng=1 nrd=0 nrs=0 +MB_TWP<2> B_BLT<2> B_BLT_PMOS_DRIVE<2> VDD VDD sg13_lv_pmos m=1 w=1.5u ++ l=130.00n ng=1 nrd=0 nrs=0 +MB_TWP<1> B_BLT<1> B_BLT_PMOS_DRIVE<1> VDD VDD sg13_lv_pmos m=1 w=1.5u ++ l=130.00n ng=1 nrd=0 nrs=0 +MB_TWP<0> B_BLT<0> B_BLT_PMOS_DRIVE<0> VDD VDD sg13_lv_pmos m=1 w=1.5u ++ l=130.00n ng=1 nrd=0 nrs=0 +MB_TSP<3> B_BLT_SEL B_SEL_N<3> B_BLT<3> VDD sg13_lv_pmos m=1 w=1.5u ++ l=130.00n ng=1 nrd=0 nrs=0 +MB_TSP<2> B_BLT_SEL B_SEL_N<2> B_BLT<2> VDD sg13_lv_pmos m=1 w=1.5u ++ l=130.00n ng=1 nrd=0 nrs=0 +MB_TSP<1> B_BLT_SEL B_SEL_N<1> B_BLT<1> VDD sg13_lv_pmos m=1 w=1.5u ++ l=130.00n ng=1 nrd=0 nrs=0 +MB_TSP<0> B_BLT_SEL B_SEL_N<0> B_BLT<0> VDD sg13_lv_pmos m=1 w=1.5u ++ l=130.00n ng=1 nrd=0 nrs=0 +MB_TPR<3> B_BLT<3> B_PRE_N VDD VDD sg13_lv_pmos m=1 w=3.000u l=130.00n ++ ng=2 nrd=0 nrs=0 +MB_TPR<2> B_BLT<2> B_PRE_N VDD VDD sg13_lv_pmos m=1 w=3.000u l=130.00n ++ ng=2 nrd=0 nrs=0 +MB_TPR<1> B_BLT<1> B_PRE_N VDD VDD sg13_lv_pmos m=1 w=3.000u l=130.00n ++ ng=2 nrd=0 nrs=0 +MB_TPR<0> B_BLT<0> B_PRE_N VDD VDD sg13_lv_pmos m=1 w=3.000u l=130.00n ++ ng=2 nrd=0 nrs=0 +MB_CSP<3> B_BLC_SEL B_SEL_N<3> B_BLC<3> VDD sg13_lv_pmos m=1 w=1.5u ++ l=130.00n ng=1 nrd=0 nrs=0 +MB_CSP<2> B_BLC_SEL B_SEL_N<2> B_BLC<2> VDD sg13_lv_pmos m=1 w=1.5u ++ l=130.00n ng=1 nrd=0 nrs=0 +MB_CSP<1> B_BLC_SEL B_SEL_N<1> B_BLC<1> VDD sg13_lv_pmos m=1 w=1.5u ++ l=130.00n ng=1 nrd=0 nrs=0 +MB_CSP<0> B_BLC_SEL B_SEL_N<0> B_BLC<0> VDD sg13_lv_pmos m=1 w=1.5u ++ l=130.00n ng=1 nrd=0 nrs=0 +MB_CPR<3> B_BLC<3> B_PRE_N VDD VDD sg13_lv_pmos m=1 w=3.000u l=130.00n ++ ng=2 nrd=0 nrs=0 +MB_CPR<2> B_BLC<2> B_PRE_N VDD VDD sg13_lv_pmos m=1 w=3.000u l=130.00n ++ ng=2 nrd=0 nrs=0 +MB_CPR<1> B_BLC<1> B_PRE_N VDD VDD sg13_lv_pmos m=1 w=3.000u l=130.00n ++ ng=2 nrd=0 nrs=0 +MB_CPR<0> B_BLC<0> B_PRE_N VDD VDD sg13_lv_pmos m=1 w=3.000u l=130.00n ++ ng=2 nrd=0 nrs=0 +XA_SEL<3> A_SEL_P<3> A_SEL_N<3> VDD VSS / RSC_IHPSG13_INVX2 +XA_SEL<2> A_SEL_P<2> A_SEL_N<2> VDD VSS / RSC_IHPSG13_INVX2 +XA_SEL<1> A_SEL_P<1> A_SEL_N<1> VDD VSS / RSC_IHPSG13_INVX2 +XA_SEL<0> A_SEL_P<0> A_SEL_N<0> VDD VSS / RSC_IHPSG13_INVX2 +XA_CINV<3> A_BLT_PMOS_DRIVE<3> A_BLC_NMOS_DRIVE<3> VDD VSS / ++ RSC_IHPSG13_INVX2 +XA_CINV<2> A_BLT_PMOS_DRIVE<2> A_BLC_NMOS_DRIVE<2> VDD VSS / ++ RSC_IHPSG13_INVX2 +XA_CINV<1> A_BLT_PMOS_DRIVE<1> A_BLC_NMOS_DRIVE<1> VDD VSS / ++ RSC_IHPSG13_INVX2 +XA_CINV<0> A_BLT_PMOS_DRIVE<0> A_BLC_NMOS_DRIVE<0> VDD VSS / ++ RSC_IHPSG13_INVX2 +XA_TINV<3> A_BLC_PMOS_DRIVE<3> A_BLT_NMOS_DRIVE<3> VDD VSS / ++ RSC_IHPSG13_INVX2 +XA_TINV<2> A_BLC_PMOS_DRIVE<2> A_BLT_NMOS_DRIVE<2> VDD VSS / ++ RSC_IHPSG13_INVX2 +XA_TINV<1> A_BLC_PMOS_DRIVE<1> A_BLT_NMOS_DRIVE<1> VDD VSS / ++ RSC_IHPSG13_INVX2 +XA_TINV<0> A_BLC_PMOS_DRIVE<0> A_BLT_NMOS_DRIVE<0> VDD VSS / ++ RSC_IHPSG13_INVX2 +XB_SEL<3> B_SEL_P<3> B_SEL_N<3> VDD VSS / RSC_IHPSG13_INVX2 +XB_SEL<2> B_SEL_P<2> B_SEL_N<2> VDD VSS / RSC_IHPSG13_INVX2 +XB_SEL<1> B_SEL_P<1> B_SEL_N<1> VDD VSS / RSC_IHPSG13_INVX2 +XB_SEL<0> B_SEL_P<0> B_SEL_N<0> VDD VSS / RSC_IHPSG13_INVX2 +XB_TINV<3> B_BLC_PMOS_DRIVE<3> B_BLT_NMOS_DRIVE<3> VDD VSS / ++ RSC_IHPSG13_INVX2 +XB_TINV<2> B_BLC_PMOS_DRIVE<2> B_BLT_NMOS_DRIVE<2> VDD VSS / ++ RSC_IHPSG13_INVX2 +XB_TINV<1> B_BLC_PMOS_DRIVE<1> B_BLT_NMOS_DRIVE<1> VDD VSS / ++ RSC_IHPSG13_INVX2 +XB_TINV<0> B_BLC_PMOS_DRIVE<0> B_BLT_NMOS_DRIVE<0> VDD VSS / ++ RSC_IHPSG13_INVX2 +XB_CINV<3> B_BLT_PMOS_DRIVE<3> B_BLC_NMOS_DRIVE<3> VDD VSS / ++ RSC_IHPSG13_INVX2 +XB_CINV<2> B_BLT_PMOS_DRIVE<2> B_BLC_NMOS_DRIVE<2> VDD VSS / ++ RSC_IHPSG13_INVX2 +XB_CINV<1> B_BLT_PMOS_DRIVE<1> B_BLC_NMOS_DRIVE<1> VDD VSS / ++ RSC_IHPSG13_INVX2 +XB_CINV<0> B_BLT_PMOS_DRIVE<0> B_BLC_NMOS_DRIVE<0> VDD VSS / ++ RSC_IHPSG13_INVX2 +XA_TDEC<3> A_SEL_P<3> A_WR_ONE A_BLT_PMOS_DRIVE<3> VDD VSS / ++ RSC_IHPSG13_NAND2X2 +XA_TDEC<2> A_SEL_P<2> A_WR_ONE A_BLT_PMOS_DRIVE<2> VDD VSS / ++ RSC_IHPSG13_NAND2X2 +XA_TDEC<1> A_SEL_P<1> A_WR_ONE A_BLT_PMOS_DRIVE<1> VDD VSS / ++ RSC_IHPSG13_NAND2X2 +XA_TDEC<0> A_SEL_P<0> A_WR_ONE A_BLT_PMOS_DRIVE<0> VDD VSS / ++ RSC_IHPSG13_NAND2X2 +XA_CDEC<3> A_SEL_P<3> A_WR_ZERO A_BLC_PMOS_DRIVE<3> VDD VSS / ++ RSC_IHPSG13_NAND2X2 +XA_CDEC<2> A_SEL_P<2> A_WR_ZERO A_BLC_PMOS_DRIVE<2> VDD VSS / ++ RSC_IHPSG13_NAND2X2 +XA_CDEC<1> A_SEL_P<1> A_WR_ZERO A_BLC_PMOS_DRIVE<1> VDD VSS / ++ RSC_IHPSG13_NAND2X2 +XA_CDEC<0> A_SEL_P<0> A_WR_ZERO A_BLC_PMOS_DRIVE<0> VDD VSS / ++ RSC_IHPSG13_NAND2X2 +XB_CDEC<3> B_SEL_P<3> B_WR_ZERO B_BLC_PMOS_DRIVE<3> VDD VSS / ++ RSC_IHPSG13_NAND2X2 +XB_CDEC<2> B_SEL_P<2> B_WR_ZERO B_BLC_PMOS_DRIVE<2> VDD VSS / ++ RSC_IHPSG13_NAND2X2 +XB_CDEC<1> B_SEL_P<1> B_WR_ZERO B_BLC_PMOS_DRIVE<1> VDD VSS / ++ RSC_IHPSG13_NAND2X2 +XB_CDEC<0> B_SEL_P<0> B_WR_ZERO B_BLC_PMOS_DRIVE<0> VDD VSS / ++ RSC_IHPSG13_NAND2X2 +XB_TDEC<3> B_SEL_P<3> B_WR_ONE B_BLT_PMOS_DRIVE<3> VDD VSS / ++ RSC_IHPSG13_NAND2X2 +XB_TDEC<2> B_SEL_P<2> B_WR_ONE B_BLT_PMOS_DRIVE<2> VDD VSS / ++ RSC_IHPSG13_NAND2X2 +XB_TDEC<1> B_SEL_P<1> B_WR_ONE B_BLT_PMOS_DRIVE<1> VDD VSS / ++ RSC_IHPSG13_NAND2X2 +XB_TDEC<0> B_SEL_P<0> B_WR_ONE B_BLT_PMOS_DRIVE<0> VDD VSS / ++ RSC_IHPSG13_NAND2X2 +.ENDS +.SUBCKT RSC_IHPSG13_AND2X6 A B Z VDD VSS +MN3 Z net6 VSS VSS sg13_lv_nmos m=1 w=2.94u l=130.00n ng=3 nrd=0 nrs=0 +MN4 net9 B VSS VSS sg13_lv_nmos m=1 w=500.0n l=130.00n ng=1 nrd=0 nrs=0 +MN6 net6 A net9 VSS sg13_lv_nmos m=1 w=500.0n l=130.00n ng=1 nrd=0 nrs=0 +MP2 Z net6 VDD VDD sg13_lv_pmos m=1 w=4.86u l=130.00n ng=3 nrd=0 nrs=0 +MP0 net6 B VDD VDD sg13_lv_pmos m=1 w=860.00n l=130.00n ng=1 nrd=0 ++ nrs=0 +MP1 net6 A VDD VDD sg13_lv_pmos m=1 w=860.00n l=130.00n ng=1 nrd=0 ++ nrs=0 +.ENDS +.SUBCKT RM_IHPSG13_1024x32_c2_2P_COLCTRL5 A_ADDR_COL<1> A_ADDR_COL<0> A_ADDR_DEC<7> ++ A_ADDR_DEC<6> A_ADDR_DEC<5> A_ADDR_DEC<4> A_ADDR_DEC<3> A_ADDR_DEC<2> ++ A_ADDR_DEC<1> A_ADDR_DEC<0> A_BIST_BM_I A_BIST_DW_I A_BIST_EN_I A_BLC<31> ++ A_BLC<30> A_BLC<29> A_BLC<28> A_BLC<27> A_BLC<26> A_BLC<25> A_BLC<24> ++ A_BLC<23> A_BLC<22> A_BLC<21> A_BLC<20> A_BLC<19> A_BLC<18> A_BLC<17> ++ A_BLC<16> A_BLC<15> A_BLC<14> A_BLC<13> A_BLC<12> A_BLC<11> A_BLC<10> ++ A_BLC<9> A_BLC<8> A_BLC<7> A_BLC<6> A_BLC<5> A_BLC<4> A_BLC<3> A_BLC<2> ++ A_BLC<1> A_BLC<0> A_BLT<31> A_BLT<30> A_BLT<29> A_BLT<28> A_BLT<27> ++ A_BLT<26> A_BLT<25> A_BLT<24> A_BLT<23> A_BLT<22> A_BLT<21> A_BLT<20> ++ A_BLT<19> A_BLT<18> A_BLT<17> A_BLT<16> A_BLT<15> A_BLT<14> A_BLT<13> ++ A_BLT<12> A_BLT<11> A_BLT<10> A_BLT<9> A_BLT<8> A_BLT<7> A_BLT<6> A_BLT<5> ++ A_BLT<4> A_BLT<3> A_BLT<2> A_BLT<1> A_BLT<0> A_BM_I A_DCLK_B_L A_DCLK_B_R ++ A_DCLK_L A_DCLK_R A_DR_O A_DW_I A_RCLK_B_L A_RCLK_B_R A_RCLK_L A_RCLK_R ++ A_TIEH_O A_WCLK_B_L A_WCLK_B_R A_WCLK_L A_WCLK_R B_ADDR_COL<1> B_ADDR_COL<0> ++ B_ADDR_DEC<7> B_ADDR_DEC<6> B_ADDR_DEC<5> B_ADDR_DEC<4> B_ADDR_DEC<3> ++ B_ADDR_DEC<2> B_ADDR_DEC<1> B_ADDR_DEC<0> B_BIST_BM_I B_BIST_DW_I ++ B_BIST_EN_I B_BLC<31> B_BLC<30> B_BLC<29> B_BLC<28> B_BLC<27> B_BLC<26> ++ B_BLC<25> B_BLC<24> B_BLC<23> B_BLC<22> B_BLC<21> B_BLC<20> B_BLC<19> ++ B_BLC<18> B_BLC<17> B_BLC<16> B_BLC<15> B_BLC<14> B_BLC<13> B_BLC<12> ++ B_BLC<11> B_BLC<10> B_BLC<9> B_BLC<8> B_BLC<7> B_BLC<6> B_BLC<5> B_BLC<4> ++ B_BLC<3> B_BLC<2> B_BLC<1> B_BLC<0> B_BLT<31> B_BLT<30> B_BLT<29> B_BLT<28> ++ B_BLT<27> B_BLT<26> B_BLT<25> B_BLT<24> B_BLT<23> B_BLT<22> B_BLT<21> ++ B_BLT<20> B_BLT<19> B_BLT<18> B_BLT<17> B_BLT<16> B_BLT<15> B_BLT<14> ++ B_BLT<13> B_BLT<12> B_BLT<11> B_BLT<10> B_BLT<9> B_BLT<8> B_BLT<7> B_BLT<6> ++ B_BLT<5> B_BLT<4> B_BLT<3> B_BLT<2> B_BLT<1> B_BLT<0> B_BM_I B_DCLK_B_L ++ B_DCLK_B_R B_DCLK_L B_DCLK_R B_DR_O B_DW_I B_RCLK_B_L B_RCLK_B_R B_RCLK_L ++ B_RCLK_R B_TIEH_O B_WCLK_B_L B_WCLK_B_R B_WCLK_L B_WCLK_R VDD VSS +XB_I80<1> B_WCLK_B_L B_RCLK_B_L B_W_nor_R<1> VDD VSS / ++ RSC_IHPSG13_AND2X2 +XB_I80<0> B_WCLK_B_L B_RCLK_B_L B_W_nor_R<0> VDD VSS / ++ RSC_IHPSG13_AND2X2 +XA_I80<1> A_WCLK_B_L A_RCLK_B_L A_W_nor_R<1> VDD VSS / ++ RSC_IHPSG13_AND2X2 +XA_I80<0> A_WCLK_B_L A_RCLK_B_L A_W_nor_R<0> VDD VSS / ++ RSC_IHPSG13_AND2X2 +XB_I44 B_BM_N B_WCLK_B_L B_DO_WRITE_P VDD VSS / RSC_IHPSG13_NOR2X2 +XA_I44 A_BM_N A_WCLK_B_L A_DO_WRITE_P VDD VSS / RSC_IHPSG13_NOR2X2 +XI_FILL4<16> VDD VSS / RSC_IHPSG13_FILLCAP4 +XI_FILL4<15> VDD VSS / RSC_IHPSG13_FILLCAP4 +XI_FILL4<14> VDD VSS / RSC_IHPSG13_FILLCAP4 +XI_FILL4<13> VDD VSS / RSC_IHPSG13_FILLCAP4 +XI_FILL4<12> VDD VSS / RSC_IHPSG13_FILLCAP4 +XI_FILL4<11> VDD VSS / RSC_IHPSG13_FILLCAP4 +XI_FILL4<10> VDD VSS / RSC_IHPSG13_FILLCAP4 +XI_FILL4<9> VDD VSS / RSC_IHPSG13_FILLCAP4 +XI_FILL4<8> VDD VSS / RSC_IHPSG13_FILLCAP4 +XI_FILL4<7> VDD VSS / RSC_IHPSG13_FILLCAP4 +XI_FILL4<6> VDD VSS / RSC_IHPSG13_FILLCAP4 +XI_FILL4<5> VDD VSS / RSC_IHPSG13_FILLCAP4 +XI_FILL4<4> VDD VSS / RSC_IHPSG13_FILLCAP4 +XI_FILL4<3> VDD VSS / RSC_IHPSG13_FILLCAP4 +XI_FILL4<2> VDD VSS / RSC_IHPSG13_FILLCAP4 +XI_FILL4<1> VDD VSS / RSC_IHPSG13_FILLCAP4 +XB_INV<6> B_N1<1> B_P1<1> VDD VSS / RSC_IHPSG13_CINVX4 +XB_INV<5> B_N0<1> B_P0<1> VDD VSS / RSC_IHPSG13_CINVX4 +XB_INV<4> B_N0<0> B_P0<0> VDD VSS / RSC_IHPSG13_CINVX4 +XB_INV<3> B_ADDR_COL<1> B_N1<1> VDD VSS / RSC_IHPSG13_CINVX4 +XB_INV<2> B_ADDR_COL<1> B_N1<0> VDD VSS / RSC_IHPSG13_CINVX4 +XB_INV<1> B_ADDR_COL<0> B_N0<1> VDD VSS / RSC_IHPSG13_CINVX4 +XB_INV<0> B_ADDR_COL<0> B_N0<0> VDD VSS / RSC_IHPSG13_CINVX4 +XA_INV<6> A_N1<1> A_P1<1> VDD VSS / RSC_IHPSG13_CINVX4 +XA_INV<5> A_N0<1> A_P0<1> VDD VSS / RSC_IHPSG13_CINVX4 +XA_INV<4> A_N0<0> A_P0<0> VDD VSS / RSC_IHPSG13_CINVX4 +XA_INV<3> A_ADDR_COL<1> A_N1<1> VDD VSS / RSC_IHPSG13_CINVX4 +XA_INV<2> A_ADDR_COL<1> A_N1<0> VDD VSS / RSC_IHPSG13_CINVX4 +XA_INV<1> A_ADDR_COL<0> A_N0<1> VDD VSS / RSC_IHPSG13_CINVX4 +XA_INV<0> A_ADDR_COL<0> A_N0<0> VDD VSS / RSC_IHPSG13_CINVX4 +XB_I81<3> B_W_nor_R<1> B_PRE_N VDD VSS / RSC_IHPSG13_CINVX4_WN +XB_I81<2> B_W_nor_R<1> B_PRE_N VDD VSS / RSC_IHPSG13_CINVX4_WN +XB_I81<1> B_W_nor_R<0> B_PRE_N VDD VSS / RSC_IHPSG13_CINVX4_WN +XB_I81<0> B_W_nor_R<0> B_PRE_N VDD VSS / RSC_IHPSG13_CINVX4_WN +XA_I81<3> A_W_nor_R<1> A_PRE_N VDD VSS / RSC_IHPSG13_CINVX4_WN +XA_I81<2> A_W_nor_R<1> A_PRE_N VDD VSS / RSC_IHPSG13_CINVX4_WN +XA_I81<1> A_W_nor_R<0> A_PRE_N VDD VSS / RSC_IHPSG13_CINVX4_WN +XA_I81<0> A_W_nor_R<0> A_PRE_N VDD VSS / RSC_IHPSG13_CINVX4_WN +XI_FILL8<78> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI_FILL8<77> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI_FILL8<76> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI_FILL8<75> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI_FILL8<74> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI_FILL8<73> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI_FILL8<72> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI_FILL8<71> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI_FILL8<70> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI_FILL8<69> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI_FILL8<68> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI_FILL8<67> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI_FILL8<66> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI_FILL8<65> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI_FILL8<64> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI_FILL8<63> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI_FILL8<62> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI_FILL8<61> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI_FILL8<60> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI_FILL8<59> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI_FILL8<58> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI_FILL8<57> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI_FILL8<56> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI_FILL8<55> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI_FILL8<54> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI_FILL8<53> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI_FILL8<52> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI_FILL8<51> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI_FILL8<50> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI_FILL8<49> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI_FILL8<48> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI_FILL8<47> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI_FILL8<46> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI_FILL8<45> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI_FILL8<44> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI_FILL8<43> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI_FILL8<42> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI_FILL8<41> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI_FILL8<40> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI_FILL8<39> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI_FILL8<38> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI_FILL8<37> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI_FILL8<36> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI_FILL8<35> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI_FILL8<34> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI_FILL8<33> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI_FILL8<32> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI_FILL8<31> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI_FILL8<30> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI_FILL8<29> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI_FILL8<28> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI_FILL8<27> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI_FILL8<26> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI_FILL8<25> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI_FILL8<24> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI_FILL8<23> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI_FILL8<22> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI_FILL8<21> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI_FILL8<20> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI_FILL8<19> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI_FILL8<18> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI_FILL8<17> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI_FILL8<16> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI_FILL8<15> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI_FILL8<14> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI_FILL8<13> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI_FILL8<12> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI_FILL8<11> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI_FILL8<10> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI_FILL8<9> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI_FILL8<8> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI_FILL8<7> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI_FILL8<6> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI_FILL8<5> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI_FILL8<4> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI_FILL8<3> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI_FILL8<2> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI_FILL8<1> VDD VSS / RSC_IHPSG13_FILLCAP8 +XAB_BLMUX<7> A_BLC<31> A_BLC<30> A_BLC<29> A_BLC<28> A_BLC_SEL A_BLT<31> ++ A_BLT<30> A_BLT<29> A_BLT<28> A_BLT_SEL A_PRE_N A_SEL_P<31> A_SEL_P<30> ++ A_SEL_P<29> A_SEL_P<28> A_WR_ONE A_WR_ZERO B_BLC<31> B_BLC<30> B_BLC<29> ++ B_BLC<28> B_BLC_SEL B_BLT<31> B_BLT<30> B_BLT<29> B_BLT<28> B_BLT_SEL ++ B_PRE_N B_SEL_P<31> B_SEL_P<30> B_SEL_P<29> B_SEL_P<28> B_WR_ONE B_WR_ZERO ++ VDD VSS / RM_IHPSG13_1024x32_c2_2P_BLDRV +XAB_BLMUX<6> A_BLC<27> A_BLC<26> A_BLC<25> A_BLC<24> A_BLC_SEL A_BLT<27> ++ A_BLT<26> A_BLT<25> A_BLT<24> A_BLT_SEL A_PRE_N A_SEL_P<27> A_SEL_P<26> ++ A_SEL_P<25> A_SEL_P<24> A_WR_ONE A_WR_ZERO B_BLC<27> B_BLC<26> B_BLC<25> ++ B_BLC<24> B_BLC_SEL B_BLT<27> B_BLT<26> B_BLT<25> B_BLT<24> B_BLT_SEL ++ B_PRE_N B_SEL_P<27> B_SEL_P<26> B_SEL_P<25> B_SEL_P<24> B_WR_ONE B_WR_ZERO ++ VDD VSS / RM_IHPSG13_1024x32_c2_2P_BLDRV +XAB_BLMUX<5> A_BLC<23> A_BLC<22> A_BLC<21> A_BLC<20> A_BLC_SEL A_BLT<23> ++ A_BLT<22> A_BLT<21> A_BLT<20> A_BLT_SEL A_PRE_N A_SEL_P<23> A_SEL_P<22> ++ A_SEL_P<21> A_SEL_P<20> A_WR_ONE A_WR_ZERO B_BLC<23> B_BLC<22> B_BLC<21> ++ B_BLC<20> B_BLC_SEL B_BLT<23> B_BLT<22> B_BLT<21> B_BLT<20> B_BLT_SEL ++ B_PRE_N B_SEL_P<23> B_SEL_P<22> B_SEL_P<21> B_SEL_P<20> B_WR_ONE B_WR_ZERO ++ VDD VSS / RM_IHPSG13_1024x32_c2_2P_BLDRV +XAB_BLMUX<4> A_BLC<19> A_BLC<18> A_BLC<17> A_BLC<16> A_BLC_SEL A_BLT<19> ++ A_BLT<18> A_BLT<17> A_BLT<16> A_BLT_SEL A_PRE_N A_SEL_P<19> A_SEL_P<18> ++ A_SEL_P<17> A_SEL_P<16> A_WR_ONE A_WR_ZERO B_BLC<19> B_BLC<18> B_BLC<17> ++ B_BLC<16> B_BLC_SEL B_BLT<19> B_BLT<18> B_BLT<17> B_BLT<16> B_BLT_SEL ++ B_PRE_N B_SEL_P<19> B_SEL_P<18> B_SEL_P<17> B_SEL_P<16> B_WR_ONE B_WR_ZERO ++ VDD VSS / RM_IHPSG13_1024x32_c2_2P_BLDRV +XAB_BLMUX<3> A_BLC<15> A_BLC<14> A_BLC<13> A_BLC<12> A_BLC_SEL A_BLT<15> ++ A_BLT<14> A_BLT<13> A_BLT<12> A_BLT_SEL A_PRE_N A_SEL_P<15> A_SEL_P<14> ++ A_SEL_P<13> A_SEL_P<12> A_WR_ONE A_WR_ZERO B_BLC<15> B_BLC<14> B_BLC<13> ++ B_BLC<12> B_BLC_SEL B_BLT<15> B_BLT<14> B_BLT<13> B_BLT<12> B_BLT_SEL ++ B_PRE_N B_SEL_P<15> B_SEL_P<14> B_SEL_P<13> B_SEL_P<12> B_WR_ONE B_WR_ZERO ++ VDD VSS / RM_IHPSG13_1024x32_c2_2P_BLDRV +XAB_BLMUX<2> A_BLC<11> A_BLC<10> A_BLC<9> A_BLC<8> A_BLC_SEL A_BLT<11> ++ A_BLT<10> A_BLT<9> A_BLT<8> A_BLT_SEL A_PRE_N A_SEL_P<11> A_SEL_P<10> ++ A_SEL_P<9> A_SEL_P<8> A_WR_ONE A_WR_ZERO B_BLC<11> B_BLC<10> B_BLC<9> ++ B_BLC<8> B_BLC_SEL B_BLT<11> B_BLT<10> B_BLT<9> B_BLT<8> B_BLT_SEL B_PRE_N ++ B_SEL_P<11> B_SEL_P<10> B_SEL_P<9> B_SEL_P<8> B_WR_ONE B_WR_ZERO VDD ++ VSS / RM_IHPSG13_1024x32_c2_2P_BLDRV +XAB_BLMUX<1> A_BLC<7> A_BLC<6> A_BLC<5> A_BLC<4> A_BLC_SEL A_BLT<7> A_BLT<6> ++ A_BLT<5> A_BLT<4> A_BLT_SEL A_PRE_N A_SEL_P<7> A_SEL_P<6> A_SEL_P<5> ++ A_SEL_P<4> A_WR_ONE A_WR_ZERO B_BLC<7> B_BLC<6> B_BLC<5> B_BLC<4> B_BLC_SEL ++ B_BLT<7> B_BLT<6> B_BLT<5> B_BLT<4> B_BLT_SEL B_PRE_N B_SEL_P<7> B_SEL_P<6> ++ B_SEL_P<5> B_SEL_P<4> B_WR_ONE B_WR_ZERO VDD VSS / ++ RM_IHPSG13_1024x32_c2_2P_BLDRV +XAB_BLMUX<0> A_BLC<3> A_BLC<2> A_BLC<1> A_BLC<0> A_BLC_SEL A_BLT<3> A_BLT<2> ++ A_BLT<1> A_BLT<0> A_BLT_SEL A_PRE_N A_SEL_P<3> A_SEL_P<2> A_SEL_P<1> ++ A_SEL_P<0> A_WR_ONE A_WR_ZERO B_BLC<3> B_BLC<2> B_BLC<1> B_BLC<0> B_BLC_SEL ++ B_BLT<3> B_BLT<2> B_BLT<1> B_BLT<0> B_BLT_SEL B_PRE_N B_SEL_P<3> B_SEL_P<2> ++ B_SEL_P<1> B_SEL_P<0> B_WR_ONE B_WR_ZERO VDD VSS / ++ RM_IHPSG13_1024x32_c2_2P_BLDRV +XB_I51 net037 B_DR_O VDD VSS / RSC_IHPSG13_INVX4 +XA_I51 net19 A_DR_O VDD VSS / RSC_IHPSG13_INVX4 +XB_I78 B_RCLK_B_L B_SAE VDD VSS / RSC_IHPSG13_CBUFX2 +XA_I78 A_RCLK_B_L A_SAE VDD VSS / RSC_IHPSG13_CBUFX2 +XB_I69 B_DCLK_L B_DCLK_B_L VDD VSS / RSC_IHPSG13_CINVX8 +XB_I50 B_WCLK_L B_WCLK_B_L VDD VSS / RSC_IHPSG13_CINVX8 +XB_EBUF B_RCLK_L B_RCLK_B_L VDD VSS / RSC_IHPSG13_CINVX8 +XA_I69 A_DCLK_L A_DCLK_B_L VDD VSS / RSC_IHPSG13_CINVX8 +XA_I50 A_WCLK_L A_WCLK_B_L VDD VSS / RSC_IHPSG13_CINVX8 +XA_EBUF A_RCLK_L A_RCLK_B_L VDD VSS / RSC_IHPSG13_CINVX8 +XB_I76 B_DI_N B_DO_WRITE_P B_WR_ZERO VDD VSS / RSC_IHPSG13_AND2X6 +XB_I75 B_DI_R B_DO_WRITE_P B_WR_ONE VDD VSS / RSC_IHPSG13_AND2X6 +XA_I76 A_DI_N A_DO_WRITE_P A_WR_ZERO VDD VSS / RSC_IHPSG13_AND2X6 +XA_I75 A_DI_R A_DO_WRITE_P A_WR_ONE VDD VSS / RSC_IHPSG13_AND2X6 +XB_I83 B_BM_R B_BM_N VDD VSS / RSC_IHPSG13_INVX2 +XB_DEC3INV<31> net041<0> B_SEL_P<31> VDD VSS / RSC_IHPSG13_INVX2 +XB_DEC3INV<30> net041<1> B_SEL_P<30> VDD VSS / RSC_IHPSG13_INVX2 +XB_DEC3INV<29> net041<2> B_SEL_P<29> VDD VSS / RSC_IHPSG13_INVX2 +XB_DEC3INV<28> net041<3> B_SEL_P<28> VDD VSS / RSC_IHPSG13_INVX2 +XB_DEC3INV<27> net041<4> B_SEL_P<27> VDD VSS / RSC_IHPSG13_INVX2 +XB_DEC3INV<26> net041<5> B_SEL_P<26> VDD VSS / RSC_IHPSG13_INVX2 +XB_DEC3INV<25> net041<6> B_SEL_P<25> VDD VSS / RSC_IHPSG13_INVX2 +XB_DEC3INV<24> net041<7> B_SEL_P<24> VDD VSS / RSC_IHPSG13_INVX2 +XB_DEC3INV<23> net041<8> B_SEL_P<23> VDD VSS / RSC_IHPSG13_INVX2 +XB_DEC3INV<22> net041<9> B_SEL_P<22> VDD VSS / RSC_IHPSG13_INVX2 +XB_DEC3INV<21> net041<10> B_SEL_P<21> VDD VSS / RSC_IHPSG13_INVX2 +XB_DEC3INV<20> net041<11> B_SEL_P<20> VDD VSS / RSC_IHPSG13_INVX2 +XB_DEC3INV<19> net041<12> B_SEL_P<19> VDD VSS / RSC_IHPSG13_INVX2 +XB_DEC3INV<18> net041<13> B_SEL_P<18> VDD VSS / RSC_IHPSG13_INVX2 +XB_DEC3INV<17> net041<14> B_SEL_P<17> VDD VSS / RSC_IHPSG13_INVX2 +XB_DEC3INV<16> net041<15> B_SEL_P<16> VDD VSS / RSC_IHPSG13_INVX2 +XB_DEC3INV<15> net041<16> B_SEL_P<15> VDD VSS / RSC_IHPSG13_INVX2 +XB_DEC3INV<14> net041<17> B_SEL_P<14> VDD VSS / RSC_IHPSG13_INVX2 +XB_DEC3INV<13> net041<18> B_SEL_P<13> VDD VSS / RSC_IHPSG13_INVX2 +XB_DEC3INV<12> net041<19> B_SEL_P<12> VDD VSS / RSC_IHPSG13_INVX2 +XB_DEC3INV<11> net041<20> B_SEL_P<11> VDD VSS / RSC_IHPSG13_INVX2 +XB_DEC3INV<10> net041<21> B_SEL_P<10> VDD VSS / RSC_IHPSG13_INVX2 +XB_DEC3INV<9> net041<22> B_SEL_P<9> VDD VSS / RSC_IHPSG13_INVX2 +XB_DEC3INV<8> net041<23> B_SEL_P<8> VDD VSS / RSC_IHPSG13_INVX2 +XB_DEC3INV<7> net041<24> B_SEL_P<7> VDD VSS / RSC_IHPSG13_INVX2 +XB_DEC3INV<6> net041<25> B_SEL_P<6> VDD VSS / RSC_IHPSG13_INVX2 +XB_DEC3INV<5> net041<26> B_SEL_P<5> VDD VSS / RSC_IHPSG13_INVX2 +XB_DEC3INV<4> net041<27> B_SEL_P<4> VDD VSS / RSC_IHPSG13_INVX2 +XB_DEC3INV<3> net041<28> B_SEL_P<3> VDD VSS / RSC_IHPSG13_INVX2 +XB_DEC3INV<2> net041<29> B_SEL_P<2> VDD VSS / RSC_IHPSG13_INVX2 +XB_DEC3INV<1> net041<30> B_SEL_P<1> VDD VSS / RSC_IHPSG13_INVX2 +XB_DEC3INV<0> net041<31> B_SEL_P<0> VDD VSS / RSC_IHPSG13_INVX2 +XB_I49 B_DI_R B_DI_N VDD VSS / RSC_IHPSG13_INVX2 +XA_I83 A_BM_R A_BM_N VDD VSS / RSC_IHPSG13_INVX2 +XA_DEC3INV<31> net23<0> A_SEL_P<31> VDD VSS / RSC_IHPSG13_INVX2 +XA_DEC3INV<30> net23<1> A_SEL_P<30> VDD VSS / RSC_IHPSG13_INVX2 +XA_DEC3INV<29> net23<2> A_SEL_P<29> VDD VSS / RSC_IHPSG13_INVX2 +XA_DEC3INV<28> net23<3> A_SEL_P<28> VDD VSS / RSC_IHPSG13_INVX2 +XA_DEC3INV<27> net23<4> A_SEL_P<27> VDD VSS / RSC_IHPSG13_INVX2 +XA_DEC3INV<26> net23<5> A_SEL_P<26> VDD VSS / RSC_IHPSG13_INVX2 +XA_DEC3INV<25> net23<6> A_SEL_P<25> VDD VSS / RSC_IHPSG13_INVX2 +XA_DEC3INV<24> net23<7> A_SEL_P<24> VDD VSS / RSC_IHPSG13_INVX2 +XA_DEC3INV<23> net23<8> A_SEL_P<23> VDD VSS / RSC_IHPSG13_INVX2 +XA_DEC3INV<22> net23<9> A_SEL_P<22> VDD VSS / RSC_IHPSG13_INVX2 +XA_DEC3INV<21> net23<10> A_SEL_P<21> VDD VSS / RSC_IHPSG13_INVX2 +XA_DEC3INV<20> net23<11> A_SEL_P<20> VDD VSS / RSC_IHPSG13_INVX2 +XA_DEC3INV<19> net23<12> A_SEL_P<19> VDD VSS / RSC_IHPSG13_INVX2 +XA_DEC3INV<18> net23<13> A_SEL_P<18> VDD VSS / RSC_IHPSG13_INVX2 +XA_DEC3INV<17> net23<14> A_SEL_P<17> VDD VSS / RSC_IHPSG13_INVX2 +XA_DEC3INV<16> net23<15> A_SEL_P<16> VDD VSS / RSC_IHPSG13_INVX2 +XA_DEC3INV<15> net23<16> A_SEL_P<15> VDD VSS / RSC_IHPSG13_INVX2 +XA_DEC3INV<14> net23<17> A_SEL_P<14> VDD VSS / RSC_IHPSG13_INVX2 +XA_DEC3INV<13> net23<18> A_SEL_P<13> VDD VSS / RSC_IHPSG13_INVX2 +XA_DEC3INV<12> net23<19> A_SEL_P<12> VDD VSS / RSC_IHPSG13_INVX2 +XA_DEC3INV<11> net23<20> A_SEL_P<11> VDD VSS / RSC_IHPSG13_INVX2 +XA_DEC3INV<10> net23<21> A_SEL_P<10> VDD VSS / RSC_IHPSG13_INVX2 +XA_DEC3INV<9> net23<22> A_SEL_P<9> VDD VSS / RSC_IHPSG13_INVX2 +XA_DEC3INV<8> net23<23> A_SEL_P<8> VDD VSS / RSC_IHPSG13_INVX2 +XA_DEC3INV<7> net23<24> A_SEL_P<7> VDD VSS / RSC_IHPSG13_INVX2 +XA_DEC3INV<6> net23<25> A_SEL_P<6> VDD VSS / RSC_IHPSG13_INVX2 +XA_DEC3INV<5> net23<26> A_SEL_P<5> VDD VSS / RSC_IHPSG13_INVX2 +XA_DEC3INV<4> net23<27> A_SEL_P<4> VDD VSS / RSC_IHPSG13_INVX2 +XA_DEC3INV<3> net23<28> A_SEL_P<3> VDD VSS / RSC_IHPSG13_INVX2 +XA_DEC3INV<2> net23<29> A_SEL_P<2> VDD VSS / RSC_IHPSG13_INVX2 +XA_DEC3INV<1> net23<30> A_SEL_P<1> VDD VSS / RSC_IHPSG13_INVX2 +XA_DEC3INV<0> net23<31> A_SEL_P<0> VDD VSS / RSC_IHPSG13_INVX2 +XA_I49 A_DI_R A_DI_N VDD VSS / RSC_IHPSG13_INVX2 +XB_ISENSE B_SAE B_BLC_SEL B_BLT_SEL net037 net038 VDD VSS / ++ RSC_IHPSG13_DFPQD_MSAFFX2 +XA_ISENSE A_SAE A_BLC_SEL A_BLT_SEL net19 net20 VDD VSS / ++ RSC_IHPSG13_DFPQD_MSAFFX2 +XB_DREG B_BIST_EN_I B_BIST_DW_I B_DCLK_B_L B_DW_I B_DI_R net042 VDD ++ VSS / RSC_IHPSG13_DFNQMX2IX1 +XB_BREG B_BIST_EN_I B_BIST_BM_I B_DCLK_B_L B_BM_I B_BM_R net043 VDD ++ VSS / RSC_IHPSG13_DFNQMX2IX1 +XA_DREG A_BIST_EN_I A_BIST_DW_I A_DCLK_B_L A_DW_I A_DI_R net22 VDD VSS ++ / RSC_IHPSG13_DFNQMX2IX1 +XA_BREG A_BIST_EN_I A_BIST_BM_I A_DCLK_B_L A_BM_I A_BM_R net21 VDD VSS ++ / RSC_IHPSG13_DFNQMX2IX1 +XB_DEC3<31> B_P1<1> B_P0<1> B_ADDR_DEC<7> net041<0> VDD VSS / ++ RSC_IHPSG13_NAND3X2 +XB_DEC3<30> B_P1<1> B_P0<1> B_ADDR_DEC<6> net041<1> VDD VSS / ++ RSC_IHPSG13_NAND3X2 +XB_DEC3<29> B_P1<1> B_P0<1> B_ADDR_DEC<5> net041<2> VDD VSS / ++ RSC_IHPSG13_NAND3X2 +XB_DEC3<28> B_P1<1> B_P0<1> B_ADDR_DEC<4> net041<3> VDD VSS / ++ RSC_IHPSG13_NAND3X2 +XB_DEC3<27> B_P1<1> B_P0<1> B_ADDR_DEC<3> net041<4> VDD VSS / ++ RSC_IHPSG13_NAND3X2 +XB_DEC3<26> B_P1<1> B_P0<1> B_ADDR_DEC<2> net041<5> VDD VSS / ++ RSC_IHPSG13_NAND3X2 +XB_DEC3<25> B_P1<1> B_P0<1> B_ADDR_DEC<1> net041<6> VDD VSS / ++ RSC_IHPSG13_NAND3X2 +XB_DEC3<24> B_P1<1> B_P0<1> B_ADDR_DEC<0> net041<7> VDD VSS / ++ RSC_IHPSG13_NAND3X2 +XB_DEC3<23> B_P1<1> B_N0<1> B_ADDR_DEC<7> net041<8> VDD VSS / ++ RSC_IHPSG13_NAND3X2 +XB_DEC3<22> B_P1<1> B_N0<1> B_ADDR_DEC<6> net041<9> VDD VSS / ++ RSC_IHPSG13_NAND3X2 +XB_DEC3<21> B_P1<1> B_N0<1> B_ADDR_DEC<5> net041<10> VDD VSS / ++ RSC_IHPSG13_NAND3X2 +XB_DEC3<20> B_P1<1> B_N0<1> B_ADDR_DEC<4> net041<11> VDD VSS / ++ RSC_IHPSG13_NAND3X2 +XB_DEC3<19> B_P1<1> B_N0<1> B_ADDR_DEC<3> net041<12> VDD VSS / ++ RSC_IHPSG13_NAND3X2 +XB_DEC3<18> B_P1<1> B_N0<1> B_ADDR_DEC<2> net041<13> VDD VSS / ++ RSC_IHPSG13_NAND3X2 +XB_DEC3<17> B_P1<1> B_N0<1> B_ADDR_DEC<1> net041<14> VDD VSS / ++ RSC_IHPSG13_NAND3X2 +XB_DEC3<16> B_P1<1> B_N0<1> B_ADDR_DEC<0> net041<15> VDD VSS / ++ RSC_IHPSG13_NAND3X2 +XB_DEC3<15> B_N1<0> B_P0<0> B_ADDR_DEC<7> net041<16> VDD VSS / ++ RSC_IHPSG13_NAND3X2 +XB_DEC3<14> B_N1<0> B_P0<0> B_ADDR_DEC<6> net041<17> VDD VSS / ++ RSC_IHPSG13_NAND3X2 +XB_DEC3<13> B_N1<0> B_P0<0> B_ADDR_DEC<5> net041<18> VDD VSS / ++ RSC_IHPSG13_NAND3X2 +XB_DEC3<12> B_N1<0> B_P0<0> B_ADDR_DEC<4> net041<19> VDD VSS / ++ RSC_IHPSG13_NAND3X2 +XB_DEC3<11> B_N1<0> B_P0<0> B_ADDR_DEC<3> net041<20> VDD VSS / ++ RSC_IHPSG13_NAND3X2 +XB_DEC3<10> B_N1<0> B_P0<0> B_ADDR_DEC<2> net041<21> VDD VSS / ++ RSC_IHPSG13_NAND3X2 +XB_DEC3<9> B_N1<0> B_P0<0> B_ADDR_DEC<1> net041<22> VDD VSS / ++ RSC_IHPSG13_NAND3X2 +XB_DEC3<8> B_N1<0> B_P0<0> B_ADDR_DEC<0> net041<23> VDD VSS / ++ RSC_IHPSG13_NAND3X2 +XB_DEC3<7> B_N1<0> B_N0<0> B_ADDR_DEC<7> net041<24> VDD VSS / ++ RSC_IHPSG13_NAND3X2 +XB_DEC3<6> B_N1<0> B_N0<0> B_ADDR_DEC<6> net041<25> VDD VSS / ++ RSC_IHPSG13_NAND3X2 +XB_DEC3<5> B_N1<0> B_N0<0> B_ADDR_DEC<5> net041<26> VDD VSS / ++ RSC_IHPSG13_NAND3X2 +XB_DEC3<4> B_N1<0> B_N0<0> B_ADDR_DEC<4> net041<27> VDD VSS / ++ RSC_IHPSG13_NAND3X2 +XB_DEC3<3> B_N1<0> B_N0<0> B_ADDR_DEC<3> net041<28> VDD VSS / ++ RSC_IHPSG13_NAND3X2 +XB_DEC3<2> B_N1<0> B_N0<0> B_ADDR_DEC<2> net041<29> VDD VSS / ++ RSC_IHPSG13_NAND3X2 +XB_DEC3<1> B_N1<0> B_N0<0> B_ADDR_DEC<1> net041<30> VDD VSS / ++ RSC_IHPSG13_NAND3X2 +XB_DEC3<0> B_N1<0> B_N0<0> B_ADDR_DEC<0> net041<31> VDD VSS / ++ RSC_IHPSG13_NAND3X2 +XA_DEC3<31> A_P1<1> A_P0<1> A_ADDR_DEC<7> net23<0> VDD VSS / ++ RSC_IHPSG13_NAND3X2 +XA_DEC3<30> A_P1<1> A_P0<1> A_ADDR_DEC<6> net23<1> VDD VSS / ++ RSC_IHPSG13_NAND3X2 +XA_DEC3<29> A_P1<1> A_P0<1> A_ADDR_DEC<5> net23<2> VDD VSS / ++ RSC_IHPSG13_NAND3X2 +XA_DEC3<28> A_P1<1> A_P0<1> A_ADDR_DEC<4> net23<3> VDD VSS / ++ RSC_IHPSG13_NAND3X2 +XA_DEC3<27> A_P1<1> A_P0<1> A_ADDR_DEC<3> net23<4> VDD VSS / ++ RSC_IHPSG13_NAND3X2 +XA_DEC3<26> A_P1<1> A_P0<1> A_ADDR_DEC<2> net23<5> VDD VSS / ++ RSC_IHPSG13_NAND3X2 +XA_DEC3<25> A_P1<1> A_P0<1> A_ADDR_DEC<1> net23<6> VDD VSS / ++ RSC_IHPSG13_NAND3X2 +XA_DEC3<24> A_P1<1> A_P0<1> A_ADDR_DEC<0> net23<7> VDD VSS / ++ RSC_IHPSG13_NAND3X2 +XA_DEC3<23> A_P1<1> A_N0<1> A_ADDR_DEC<7> net23<8> VDD VSS / ++ RSC_IHPSG13_NAND3X2 +XA_DEC3<22> A_P1<1> A_N0<1> A_ADDR_DEC<6> net23<9> VDD VSS / ++ RSC_IHPSG13_NAND3X2 +XA_DEC3<21> A_P1<1> A_N0<1> A_ADDR_DEC<5> net23<10> VDD VSS / ++ RSC_IHPSG13_NAND3X2 +XA_DEC3<20> A_P1<1> A_N0<1> A_ADDR_DEC<4> net23<11> VDD VSS / ++ RSC_IHPSG13_NAND3X2 +XA_DEC3<19> A_P1<1> A_N0<1> A_ADDR_DEC<3> net23<12> VDD VSS / ++ RSC_IHPSG13_NAND3X2 +XA_DEC3<18> A_P1<1> A_N0<1> A_ADDR_DEC<2> net23<13> VDD VSS / ++ RSC_IHPSG13_NAND3X2 +XA_DEC3<17> A_P1<1> A_N0<1> A_ADDR_DEC<1> net23<14> VDD VSS / ++ RSC_IHPSG13_NAND3X2 +XA_DEC3<16> A_P1<1> A_N0<1> A_ADDR_DEC<0> net23<15> VDD VSS / ++ RSC_IHPSG13_NAND3X2 +XA_DEC3<15> A_N1<0> A_P0<0> A_ADDR_DEC<7> net23<16> VDD VSS / ++ RSC_IHPSG13_NAND3X2 +XA_DEC3<14> A_N1<0> A_P0<0> A_ADDR_DEC<6> net23<17> VDD VSS / ++ RSC_IHPSG13_NAND3X2 +XA_DEC3<13> A_N1<0> A_P0<0> A_ADDR_DEC<5> net23<18> VDD VSS / ++ RSC_IHPSG13_NAND3X2 +XA_DEC3<12> A_N1<0> A_P0<0> A_ADDR_DEC<4> net23<19> VDD VSS / ++ RSC_IHPSG13_NAND3X2 +XA_DEC3<11> A_N1<0> A_P0<0> A_ADDR_DEC<3> net23<20> VDD VSS / ++ RSC_IHPSG13_NAND3X2 +XA_DEC3<10> A_N1<0> A_P0<0> A_ADDR_DEC<2> net23<21> VDD VSS / ++ RSC_IHPSG13_NAND3X2 +XA_DEC3<9> A_N1<0> A_P0<0> A_ADDR_DEC<1> net23<22> VDD VSS / ++ RSC_IHPSG13_NAND3X2 +XA_DEC3<8> A_N1<0> A_P0<0> A_ADDR_DEC<0> net23<23> VDD VSS / ++ RSC_IHPSG13_NAND3X2 +XA_DEC3<7> A_N1<0> A_N0<0> A_ADDR_DEC<7> net23<24> VDD VSS / ++ RSC_IHPSG13_NAND3X2 +XA_DEC3<6> A_N1<0> A_N0<0> A_ADDR_DEC<6> net23<25> VDD VSS / ++ RSC_IHPSG13_NAND3X2 +XA_DEC3<5> A_N1<0> A_N0<0> A_ADDR_DEC<5> net23<26> VDD VSS / ++ RSC_IHPSG13_NAND3X2 +XA_DEC3<4> A_N1<0> A_N0<0> A_ADDR_DEC<4> net23<27> VDD VSS / ++ RSC_IHPSG13_NAND3X2 +XA_DEC3<3> A_N1<0> A_N0<0> A_ADDR_DEC<3> net23<28> VDD VSS / ++ RSC_IHPSG13_NAND3X2 +XA_DEC3<2> A_N1<0> A_N0<0> A_ADDR_DEC<2> net23<29> VDD VSS / ++ RSC_IHPSG13_NAND3X2 +XA_DEC3<1> A_N1<0> A_N0<0> A_ADDR_DEC<1> net23<30> VDD VSS / ++ RSC_IHPSG13_NAND3X2 +XA_DEC3<0> A_N1<0> A_N0<0> A_ADDR_DEC<0> net23<31> VDD VSS / ++ RSC_IHPSG13_NAND3X2 +XB_I89 B_DCLK_B_L B_DCLK_B_R / RSC_IHPSG13_MET3RES +XB_I91 B_RCLK_B_L B_RCLK_B_R / RSC_IHPSG13_MET3RES +XB_I90 B_WCLK_B_L B_WCLK_B_R / RSC_IHPSG13_MET3RES +XB_I88 B_DCLK_L B_DCLK_R / RSC_IHPSG13_MET3RES +XB_I87 B_WCLK_L B_WCLK_R / RSC_IHPSG13_MET3RES +XB_R2 B_RCLK_L B_RCLK_R / RSC_IHPSG13_MET3RES +XA_I89 A_DCLK_B_L A_DCLK_B_R / RSC_IHPSG13_MET3RES +XA_I91 A_RCLK_B_L A_RCLK_B_R / RSC_IHPSG13_MET3RES +XA_I90 A_WCLK_B_L A_WCLK_B_R / RSC_IHPSG13_MET3RES +XA_I88 A_DCLK_L A_DCLK_R / RSC_IHPSG13_MET3RES +XA_I87 A_WCLK_L A_WCLK_R / RSC_IHPSG13_MET3RES +XA_R2 A_RCLK_L A_RCLK_R / RSC_IHPSG13_MET3RES +XB_BM_TIEH B_TIEH_O VDD VSS / RSC_IHPSG13_TIEH +XA_BM_TIEH A_TIEH_O VDD VSS / RSC_IHPSG13_TIEH +.ENDS +.SUBCKT RM_IHPSG13_1024x32_c2_2P_COLDRV13_FILL4 VDD VSS +XI0<11> VDD VSS / RSC_IHPSG13_FILLCAP4 +XI0<10> VDD VSS / RSC_IHPSG13_FILLCAP4 +XI0<9> VDD VSS / RSC_IHPSG13_FILLCAP4 +XI0<8> VDD VSS / RSC_IHPSG13_FILLCAP4 +XI0<7> VDD VSS / RSC_IHPSG13_FILLCAP4 +XI0<6> VDD VSS / RSC_IHPSG13_FILLCAP4 +XI0<5> VDD VSS / RSC_IHPSG13_FILLCAP4 +XI0<4> VDD VSS / RSC_IHPSG13_FILLCAP4 +XI0<3> VDD VSS / RSC_IHPSG13_FILLCAP4 +XI0<2> VDD VSS / RSC_IHPSG13_FILLCAP4 +XI0<1> VDD VSS / RSC_IHPSG13_FILLCAP4 +.ENDS + + +.SUBCKT RSC_IHPSG13_CBUFX16 A Z VDD VSS +MN0 net4 A VSS VSS sg13_lv_nmos m=1 w=2.115u l=130.00n ng=3 nrd=0 nrs=0 +MN1 Z net4 VSS VSS sg13_lv_nmos m=1 w=5.64u l=130.00n ng=8 nrd=0 nrs=0 +MP1 Z net4 VDD VDD sg13_lv_pmos m=1 w=13.000u l=130.00n ng=8 nrd=0 ++ nrs=0 +MP0 net4 A VDD VDD sg13_lv_pmos m=1 w=4.89u l=130.00n ng=3 nrd=0 nrs=0 +.ENDS +.SUBCKT RM_IHPSG13_1024x32_c2_1P_COLDRV13X16 ADDR_COL_I<1> ADDR_COL_I<0> ADDR_COL_O<1> ++ ADDR_COL_O<0> ADDR_DEC_I<7> ADDR_DEC_I<6> ADDR_DEC_I<5> ADDR_DEC_I<4> ++ ADDR_DEC_I<3> ADDR_DEC_I<2> ADDR_DEC_I<1> ADDR_DEC_I<0> ADDR_DEC_O<7> ++ ADDR_DEC_O<6> ADDR_DEC_O<5> ADDR_DEC_O<4> ADDR_DEC_O<3> ADDR_DEC_O<2> ++ ADDR_DEC_O<1> ADDR_DEC_O<0> DCLK_I DCLK_O RCLK_I RCLK_O WCLK_I WCLK_O ++ VDD VSS +XI1<1> VDD VSS / RSC_IHPSG13_FILLCAP4 +XI1<0> VDD VSS / RSC_IHPSG13_FILLCAP4 +XI0<3> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI0<2> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI0<1> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI0<0> VDD VSS / RSC_IHPSG13_FILLCAP8 +XADDR_COL_DRV<1> ADDR_COL_I<1> ADDR_COL_O<1> VDD VSS / ++ RSC_IHPSG13_CBUFX16 +XADDR_COL_DRV<0> ADDR_COL_I<0> ADDR_COL_O<0> VDD VSS / ++ RSC_IHPSG13_CBUFX16 +XADDR_DEC_DRV<7> ADDR_DEC_I<7> ADDR_DEC_O<7> VDD VSS / ++ RSC_IHPSG13_CBUFX16 +XADDR_DEC_DRV<6> ADDR_DEC_I<6> ADDR_DEC_O<6> VDD VSS / ++ RSC_IHPSG13_CBUFX16 +XADDR_DEC_DRV<5> ADDR_DEC_I<5> ADDR_DEC_O<5> VDD VSS / ++ RSC_IHPSG13_CBUFX16 +XADDR_DEC_DRV<4> ADDR_DEC_I<4> ADDR_DEC_O<4> VDD VSS / ++ RSC_IHPSG13_CBUFX16 +XADDR_DEC_DRV<3> ADDR_DEC_I<3> ADDR_DEC_O<3> VDD VSS / ++ RSC_IHPSG13_CBUFX16 +XADDR_DEC_DRV<2> ADDR_DEC_I<2> ADDR_DEC_O<2> VDD VSS / ++ RSC_IHPSG13_CBUFX16 +XADDR_DEC_DRV<1> ADDR_DEC_I<1> ADDR_DEC_O<1> VDD VSS / ++ RSC_IHPSG13_CBUFX16 +XADDR_DEC_DRV<0> ADDR_DEC_I<0> ADDR_DEC_O<0> VDD VSS / ++ RSC_IHPSG13_CBUFX16 +XDCLK_DRV DCLK_I DCLK_O VDD VSS / RSC_IHPSG13_CBUFX16 +XRCLK_DRV RCLK_I RCLK_O VDD VSS / RSC_IHPSG13_CBUFX16 +XWCLK_DRV WCLK_I WCLK_O VDD VSS / RSC_IHPSG13_CBUFX16 +.ENDS +.SUBCKT RSC_IHPSG13_WLDRVX16 A Z VDD VSS +MN1 Z net6 VSS VSS sg13_lv_nmos m=1 w=1.41u l=130.00n ng=2 nrd=0 nrs=0 +MN0 net6 A VSS VSS sg13_lv_nmos m=1 w=1.8u l=130.00n ng=2 nrd=0 nrs=0 +MP1 Z net6 VDD VDD sg13_lv_pmos m=1 w=12.96u l=130.00n ng=8 nrd=0 nrs=0 +MP0 net6 A VDD VDD sg13_lv_pmos m=1 w=900.0n l=130.00n ng=1 nrd=0 nrs=0 +.ENDS +.SUBCKT RM_IHPSG13_1024x32_c2_1P_WLDRV16X16 A<15> A<14> A<13> A<12> A<11> A<10> A<9> A<8> ++ A<7> A<6> A<5> A<4> A<3> A<2> A<1> A<0> Z<15> Z<14> Z<13> Z<12> Z<11> Z<10> ++ Z<9> Z<8> Z<7> Z<6> Z<5> Z<4> Z<3> Z<2> Z<1> Z<0> VDD VSS +XBUF<15> A<15> Z<15> VDD VSS / RSC_IHPSG13_WLDRVX16 +XBUF<14> A<14> Z<14> VDD VSS / RSC_IHPSG13_WLDRVX16 +XBUF<13> A<13> Z<13> VDD VSS / RSC_IHPSG13_WLDRVX16 +XBUF<12> A<12> Z<12> VDD VSS / RSC_IHPSG13_WLDRVX16 +XBUF<11> A<11> Z<11> VDD VSS / RSC_IHPSG13_WLDRVX16 +XBUF<10> A<10> Z<10> VDD VSS / RSC_IHPSG13_WLDRVX16 +XBUF<9> A<9> Z<9> VDD VSS / RSC_IHPSG13_WLDRVX16 +XBUF<8> A<8> Z<8> VDD VSS / RSC_IHPSG13_WLDRVX16 +XBUF<7> A<7> Z<7> VDD VSS / RSC_IHPSG13_WLDRVX16 +XBUF<6> A<6> Z<6> VDD VSS / RSC_IHPSG13_WLDRVX16 +XBUF<5> A<5> Z<5> VDD VSS / RSC_IHPSG13_WLDRVX16 +XBUF<4> A<4> Z<4> VDD VSS / RSC_IHPSG13_WLDRVX16 +XBUF<3> A<3> Z<3> VDD VSS / RSC_IHPSG13_WLDRVX16 +XBUF<2> A<2> Z<2> VDD VSS / RSC_IHPSG13_WLDRVX16 +XBUF<1> A<1> Z<1> VDD VSS / RSC_IHPSG13_WLDRVX16 +XBUF<0> A<0> Z<0> VDD VSS / RSC_IHPSG13_WLDRVX16 +.ENDS + + +.SUBCKT RM_IHPSG13_1024x32_c2_2P_COLDRV13X4 ADDR_COL_I<1> ADDR_COL_I<0> ADDR_COL_O<1> ++ ADDR_COL_O<0> ADDR_DEC_I<7> ADDR_DEC_I<6> ADDR_DEC_I<5> ADDR_DEC_I<4> ++ ADDR_DEC_I<3> ADDR_DEC_I<2> ADDR_DEC_I<1> ADDR_DEC_I<0> ADDR_DEC_O<7> ++ ADDR_DEC_O<6> ADDR_DEC_O<5> ADDR_DEC_O<4> ADDR_DEC_O<3> ADDR_DEC_O<2> ++ ADDR_DEC_O<1> ADDR_DEC_O<0> DCLK_I DCLK_O RCLK_I RCLK_O WCLK_I WCLK_O ++ VDD VSS +XWCLK_DRV WCLK_I WCLK_O VDD VSS / RSC_IHPSG13_CBUFX4 +XRCLK_DRV RCLK_I RCLK_O VDD VSS / RSC_IHPSG13_CBUFX4 +XDCLK_DRV DCLK_I DCLK_O VDD VSS / RSC_IHPSG13_CBUFX4 +XADDR_COL_DRV<1> ADDR_COL_I<1> ADDR_COL_O<1> VDD VSS / ++ RSC_IHPSG13_CBUFX4 +XADDR_COL_DRV<0> ADDR_COL_I<0> ADDR_COL_O<0> VDD VSS / ++ RSC_IHPSG13_CBUFX4 +XADDR_DEC_DRV<7> ADDR_DEC_I<7> ADDR_DEC_O<7> VDD VSS / ++ RSC_IHPSG13_CBUFX4 +XADDR_DEC_DRV<6> ADDR_DEC_I<6> ADDR_DEC_O<6> VDD VSS / ++ RSC_IHPSG13_CBUFX4 +XADDR_DEC_DRV<5> ADDR_DEC_I<5> ADDR_DEC_O<5> VDD VSS / ++ RSC_IHPSG13_CBUFX4 +XADDR_DEC_DRV<4> ADDR_DEC_I<4> ADDR_DEC_O<4> VDD VSS / ++ RSC_IHPSG13_CBUFX4 +XADDR_DEC_DRV<3> ADDR_DEC_I<3> ADDR_DEC_O<3> VDD VSS / ++ RSC_IHPSG13_CBUFX4 +XADDR_DEC_DRV<2> ADDR_DEC_I<2> ADDR_DEC_O<2> VDD VSS / ++ RSC_IHPSG13_CBUFX4 +XADDR_DEC_DRV<1> ADDR_DEC_I<1> ADDR_DEC_O<1> VDD VSS / ++ RSC_IHPSG13_CBUFX4 +XADDR_DEC_DRV<0> ADDR_DEC_I<0> ADDR_DEC_O<0> VDD VSS / ++ RSC_IHPSG13_CBUFX4 +XI0<6> VDD VSS / RSC_IHPSG13_FILLCAP4 +XI0<5> VDD VSS / RSC_IHPSG13_FILLCAP4 +XI0<4> VDD VSS / RSC_IHPSG13_FILLCAP4 +XI0<3> VDD VSS / RSC_IHPSG13_FILLCAP4 +XI0<2> VDD VSS / RSC_IHPSG13_FILLCAP4 +XI0<1> VDD VSS / RSC_IHPSG13_FILLCAP4 +XI1 VDD VSS / RSC_IHPSG13_FILLCAP8 +.ENDS +.SUBCKT RM_IHPSG13_1024x32_c2_2P_WLDRV16X4 A<15> A<14> A<13> A<12> A<11> A<10> A<9> A<8> ++ A<7> A<6> A<5> A<4> A<3> A<2> A<1> A<0> Z<15> Z<14> Z<13> Z<12> Z<11> Z<10> ++ Z<9> Z<8> Z<7> Z<6> Z<5> Z<4> Z<3> Z<2> Z<1> Z<0> VDD VSS +XBUF<15> A<15> Z<15> VDD VSS / RSC_IHPSG13_WLDRVX4 +XBUF<14> A<14> Z<14> VDD VSS / RSC_IHPSG13_WLDRVX4 +XBUF<13> A<13> Z<13> VDD VSS / RSC_IHPSG13_WLDRVX4 +XBUF<12> A<12> Z<12> VDD VSS / RSC_IHPSG13_WLDRVX4 +XBUF<11> A<11> Z<11> VDD VSS / RSC_IHPSG13_WLDRVX4 +XBUF<10> A<10> Z<10> VDD VSS / RSC_IHPSG13_WLDRVX4 +XBUF<9> A<9> Z<9> VDD VSS / RSC_IHPSG13_WLDRVX4 +XBUF<8> A<8> Z<8> VDD VSS / RSC_IHPSG13_WLDRVX4 +XBUF<7> A<7> Z<7> VDD VSS / RSC_IHPSG13_WLDRVX4 +XBUF<6> A<6> Z<6> VDD VSS / RSC_IHPSG13_WLDRVX4 +XBUF<5> A<5> Z<5> VDD VSS / RSC_IHPSG13_WLDRVX4 +XBUF<4> A<4> Z<4> VDD VSS / RSC_IHPSG13_WLDRVX4 +XBUF<3> A<3> Z<3> VDD VSS / RSC_IHPSG13_WLDRVX4 +XBUF<2> A<2> Z<2> VDD VSS / RSC_IHPSG13_WLDRVX4 +XBUF<1> A<1> Z<1> VDD VSS / RSC_IHPSG13_WLDRVX4 +XBUF<0> A<0> Z<0> VDD VSS / RSC_IHPSG13_WLDRVX4 +.ENDS +.SUBCKT RM_IHPSG13_1024x32_c2_2P_ROWDEC8 ADDR_N_I<7> ADDR_N_I<6> ADDR_N_I<5> ADDR_N_I<4> ++ ADDR_N_I<3> ADDR_N_I<2> ADDR_N_I<1> ADDR_N_I<0> CS_I ECLK_I WL_O<255> ++ WL_O<254> WL_O<253> WL_O<252> WL_O<251> WL_O<250> WL_O<249> WL_O<248> ++ WL_O<247> WL_O<246> WL_O<245> WL_O<244> WL_O<243> WL_O<242> WL_O<241> ++ WL_O<240> WL_O<239> WL_O<238> WL_O<237> WL_O<236> WL_O<235> WL_O<234> ++ WL_O<233> WL_O<232> WL_O<231> WL_O<230> WL_O<229> WL_O<228> WL_O<227> ++ WL_O<226> WL_O<225> WL_O<224> WL_O<223> WL_O<222> WL_O<221> WL_O<220> ++ WL_O<219> WL_O<218> WL_O<217> WL_O<216> WL_O<215> WL_O<214> WL_O<213> ++ WL_O<212> WL_O<211> WL_O<210> WL_O<209> WL_O<208> WL_O<207> WL_O<206> ++ WL_O<205> WL_O<204> WL_O<203> WL_O<202> WL_O<201> WL_O<200> WL_O<199> ++ WL_O<198> WL_O<197> WL_O<196> WL_O<195> WL_O<194> WL_O<193> WL_O<192> ++ WL_O<191> WL_O<190> WL_O<189> WL_O<188> WL_O<187> WL_O<186> WL_O<185> ++ WL_O<184> WL_O<183> WL_O<182> WL_O<181> WL_O<180> WL_O<179> WL_O<178> ++ WL_O<177> WL_O<176> WL_O<175> WL_O<174> WL_O<173> WL_O<172> WL_O<171> ++ WL_O<170> WL_O<169> WL_O<168> WL_O<167> WL_O<166> WL_O<165> WL_O<164> ++ WL_O<163> WL_O<162> WL_O<161> WL_O<160> WL_O<159> WL_O<158> WL_O<157> ++ WL_O<156> WL_O<155> WL_O<154> WL_O<153> WL_O<152> WL_O<151> WL_O<150> ++ WL_O<149> WL_O<148> WL_O<147> WL_O<146> WL_O<145> WL_O<144> WL_O<143> ++ WL_O<142> WL_O<141> WL_O<140> WL_O<139> WL_O<138> WL_O<137> WL_O<136> ++ WL_O<135> WL_O<134> WL_O<133> WL_O<132> WL_O<131> WL_O<130> WL_O<129> ++ WL_O<128> WL_O<127> WL_O<126> WL_O<125> WL_O<124> WL_O<123> WL_O<122> ++ WL_O<121> WL_O<120> WL_O<119> WL_O<118> WL_O<117> WL_O<116> WL_O<115> ++ WL_O<114> WL_O<113> WL_O<112> WL_O<111> WL_O<110> WL_O<109> WL_O<108> ++ WL_O<107> WL_O<106> WL_O<105> WL_O<104> WL_O<103> WL_O<102> WL_O<101> ++ WL_O<100> WL_O<99> WL_O<98> WL_O<97> WL_O<96> WL_O<95> WL_O<94> WL_O<93> ++ WL_O<92> WL_O<91> WL_O<90> WL_O<89> WL_O<88> WL_O<87> WL_O<86> WL_O<85> ++ WL_O<84> WL_O<83> WL_O<82> WL_O<81> WL_O<80> WL_O<79> WL_O<78> WL_O<77> ++ WL_O<76> WL_O<75> WL_O<74> WL_O<73> WL_O<72> WL_O<71> WL_O<70> WL_O<69> ++ WL_O<68> WL_O<67> WL_O<66> WL_O<65> WL_O<64> WL_O<63> WL_O<62> WL_O<61> ++ WL_O<60> WL_O<59> WL_O<58> WL_O<57> WL_O<56> WL_O<55> WL_O<54> WL_O<53> ++ WL_O<52> WL_O<51> WL_O<50> WL_O<49> WL_O<48> WL_O<47> WL_O<46> WL_O<45> ++ WL_O<44> WL_O<43> WL_O<42> WL_O<41> WL_O<40> WL_O<39> WL_O<38> WL_O<37> ++ WL_O<36> WL_O<35> WL_O<34> WL_O<33> WL_O<32> WL_O<31> WL_O<30> WL_O<29> ++ WL_O<28> WL_O<27> WL_O<26> WL_O<25> WL_O<24> WL_O<23> WL_O<22> WL_O<21> ++ WL_O<20> WL_O<19> WL_O<18> WL_O<17> WL_O<16> WL_O<15> WL_O<14> WL_O<13> ++ WL_O<12> WL_O<11> WL_O<10> WL_O<9> WL_O<8> WL_O<7> WL_O<6> WL_O<5> WL_O<4> ++ WL_O<3> WL_O<2> WL_O<1> WL_O<0> VDD VSS +XDEC11<4> ADDR_N_I<7> ADDR_N_I<6> CS_I CS04<3> VDD VSS / ++ RM_IHPSG13_1024x32_c2_2P_DEC03 +XDEC11<3> ADDR_N_I<5> ADDR_N_I<4> CS04<3> CS00<15> VDD VSS / ++ RM_IHPSG13_1024x32_c2_2P_DEC03 +XDEC11<2> ADDR_N_I<5> ADDR_N_I<4> CS04<2> CS00<11> VDD VSS / ++ RM_IHPSG13_1024x32_c2_2P_DEC03 +XDEC11<1> ADDR_N_I<5> ADDR_N_I<4> CS04<1> CS00<7> VDD VSS / ++ RM_IHPSG13_1024x32_c2_2P_DEC03 +XDEC11<0> ADDR_N_I<5> ADDR_N_I<4> CS04<0> CS00<3> VDD VSS / ++ RM_IHPSG13_1024x32_c2_2P_DEC03 +XSEL<15> ADDR_N_I<3> ADDR_N_I<2> ADDR_N_I<1> ADDR_N_I<0> CS00<15> ECLK_H<15> ++ ECLK_H<16> ECLK_B<15> ECLK_B<16> WL_O<255> WL_O<254> WL_O<253> WL_O<252> ++ WL_O<251> WL_O<250> WL_O<249> WL_O<248> WL_O<247> WL_O<246> WL_O<245> ++ WL_O<244> WL_O<243> WL_O<242> WL_O<241> WL_O<240> VDD VSS / ++ RM_IHPSG13_1024x32_c2_2P_DEC04 +XSEL<14> ADDR_N_I<3> ADDR_N_I<2> ADDR_N_I<1> ADDR_N_I<0> CS00<14> ECLK_H<14> ++ ECLK_H<15> ECLK_B<14> ECLK_B<15> WL_O<239> WL_O<238> WL_O<237> WL_O<236> ++ WL_O<235> WL_O<234> WL_O<233> WL_O<232> WL_O<231> WL_O<230> WL_O<229> ++ WL_O<228> WL_O<227> WL_O<226> WL_O<225> WL_O<224> VDD VSS / ++ RM_IHPSG13_1024x32_c2_2P_DEC04 +XSEL<13> ADDR_N_I<3> ADDR_N_I<2> ADDR_N_I<1> ADDR_N_I<0> CS00<13> ECLK_H<13> ++ ECLK_H<14> ECLK_B<13> ECLK_B<14> WL_O<223> WL_O<222> WL_O<221> WL_O<220> ++ WL_O<219> WL_O<218> WL_O<217> WL_O<216> WL_O<215> WL_O<214> WL_O<213> ++ WL_O<212> WL_O<211> WL_O<210> WL_O<209> WL_O<208> VDD VSS / ++ RM_IHPSG13_1024x32_c2_2P_DEC04 +XSEL<12> ADDR_N_I<3> ADDR_N_I<2> ADDR_N_I<1> ADDR_N_I<0> CS00<12> ECLK_H<12> ++ ECLK_H<13> ECLK_B<12> ECLK_B<13> WL_O<207> WL_O<206> WL_O<205> WL_O<204> ++ WL_O<203> WL_O<202> WL_O<201> WL_O<200> WL_O<199> WL_O<198> WL_O<197> ++ WL_O<196> WL_O<195> WL_O<194> WL_O<193> WL_O<192> VDD VSS / ++ RM_IHPSG13_1024x32_c2_2P_DEC04 +XSEL<11> ADDR_N_I<3> ADDR_N_I<2> ADDR_N_I<1> ADDR_N_I<0> CS00<11> ECLK_H<11> ++ ECLK_H<12> ECLK_B<11> ECLK_B<12> WL_O<191> WL_O<190> WL_O<189> WL_O<188> ++ WL_O<187> WL_O<186> WL_O<185> WL_O<184> WL_O<183> WL_O<182> WL_O<181> ++ WL_O<180> WL_O<179> WL_O<178> WL_O<177> WL_O<176> VDD VSS / ++ RM_IHPSG13_1024x32_c2_2P_DEC04 +XSEL<10> ADDR_N_I<3> ADDR_N_I<2> ADDR_N_I<1> ADDR_N_I<0> CS00<10> ECLK_H<10> ++ ECLK_H<11> ECLK_B<10> ECLK_B<11> WL_O<175> WL_O<174> WL_O<173> WL_O<172> ++ WL_O<171> WL_O<170> WL_O<169> WL_O<168> WL_O<167> WL_O<166> WL_O<165> ++ WL_O<164> WL_O<163> WL_O<162> WL_O<161> WL_O<160> VDD VSS / ++ RM_IHPSG13_1024x32_c2_2P_DEC04 +XSEL<9> ADDR_N_I<3> ADDR_N_I<2> ADDR_N_I<1> ADDR_N_I<0> CS00<9> ECLK_H<9> ++ ECLK_H<10> ECLK_B<9> ECLK_B<10> WL_O<159> WL_O<158> WL_O<157> WL_O<156> ++ WL_O<155> WL_O<154> WL_O<153> WL_O<152> WL_O<151> WL_O<150> WL_O<149> ++ WL_O<148> WL_O<147> WL_O<146> WL_O<145> WL_O<144> VDD VSS / ++ RM_IHPSG13_1024x32_c2_2P_DEC04 +XSEL<8> ADDR_N_I<3> ADDR_N_I<2> ADDR_N_I<1> ADDR_N_I<0> CS00<8> ECLK_H<8> ++ ECLK_H<9> ECLK_B<8> ECLK_B<9> WL_O<143> WL_O<142> WL_O<141> WL_O<140> ++ WL_O<139> WL_O<138> WL_O<137> WL_O<136> WL_O<135> WL_O<134> WL_O<133> ++ WL_O<132> WL_O<131> WL_O<130> WL_O<129> WL_O<128> VDD VSS / ++ RM_IHPSG13_1024x32_c2_2P_DEC04 +XSEL<7> ADDR_N_I<3> ADDR_N_I<2> ADDR_N_I<1> ADDR_N_I<0> CS00<7> ECLK_H<7> ++ ECLK_H<8> ECLK_B<7> ECLK_B<8> WL_O<127> WL_O<126> WL_O<125> WL_O<124> ++ WL_O<123> WL_O<122> WL_O<121> WL_O<120> WL_O<119> WL_O<118> WL_O<117> ++ WL_O<116> WL_O<115> WL_O<114> WL_O<113> WL_O<112> VDD VSS / ++ RM_IHPSG13_1024x32_c2_2P_DEC04 +XSEL<6> ADDR_N_I<3> ADDR_N_I<2> ADDR_N_I<1> ADDR_N_I<0> CS00<6> ECLK_H<6> ++ ECLK_H<7> ECLK_B<6> ECLK_B<7> WL_O<111> WL_O<110> WL_O<109> WL_O<108> ++ WL_O<107> WL_O<106> WL_O<105> WL_O<104> WL_O<103> WL_O<102> WL_O<101> ++ WL_O<100> WL_O<99> WL_O<98> WL_O<97> WL_O<96> VDD VSS / ++ RM_IHPSG13_1024x32_c2_2P_DEC04 +XSEL<5> ADDR_N_I<3> ADDR_N_I<2> ADDR_N_I<1> ADDR_N_I<0> CS00<5> ECLK_H<5> ++ ECLK_H<6> ECLK_B<5> ECLK_B<6> WL_O<95> WL_O<94> WL_O<93> WL_O<92> WL_O<91> ++ WL_O<90> WL_O<89> WL_O<88> WL_O<87> WL_O<86> WL_O<85> WL_O<84> WL_O<83> ++ WL_O<82> WL_O<81> WL_O<80> VDD VSS / RM_IHPSG13_1024x32_c2_2P_DEC04 +XSEL<4> ADDR_N_I<3> ADDR_N_I<2> ADDR_N_I<1> ADDR_N_I<0> CS00<4> ECLK_H<4> ++ ECLK_H<5> ECLK_B<4> ECLK_B<5> WL_O<79> WL_O<78> WL_O<77> WL_O<76> WL_O<75> ++ WL_O<74> WL_O<73> WL_O<72> WL_O<71> WL_O<70> WL_O<69> WL_O<68> WL_O<67> ++ WL_O<66> WL_O<65> WL_O<64> VDD VSS / RM_IHPSG13_1024x32_c2_2P_DEC04 +XSEL<3> ADDR_N_I<3> ADDR_N_I<2> ADDR_N_I<1> ADDR_N_I<0> CS00<3> ECLK_H<3> ++ ECLK_H<4> ECLK_B<3> ECLK_B<4> WL_O<63> WL_O<62> WL_O<61> WL_O<60> WL_O<59> ++ WL_O<58> WL_O<57> WL_O<56> WL_O<55> WL_O<54> WL_O<53> WL_O<52> WL_O<51> ++ WL_O<50> WL_O<49> WL_O<48> VDD VSS / RM_IHPSG13_1024x32_c2_2P_DEC04 +XSEL<2> ADDR_N_I<3> ADDR_N_I<2> ADDR_N_I<1> ADDR_N_I<0> CS00<2> ECLK_H<2> ++ ECLK_H<3> ECLK_B<2> ECLK_B<3> WL_O<47> WL_O<46> WL_O<45> WL_O<44> WL_O<43> ++ WL_O<42> WL_O<41> WL_O<40> WL_O<39> WL_O<38> WL_O<37> WL_O<36> WL_O<35> ++ WL_O<34> WL_O<33> WL_O<32> VDD VSS / RM_IHPSG13_1024x32_c2_2P_DEC04 +XSEL<1> ADDR_N_I<3> ADDR_N_I<2> ADDR_N_I<1> ADDR_N_I<0> CS00<1> ECLK_H<1> ++ ECLK_H<2> ECLK_B<1> ECLK_B<2> WL_O<31> WL_O<30> WL_O<29> WL_O<28> WL_O<27> ++ WL_O<26> WL_O<25> WL_O<24> WL_O<23> WL_O<22> WL_O<21> WL_O<20> WL_O<19> ++ WL_O<18> WL_O<17> WL_O<16> VDD VSS / RM_IHPSG13_1024x32_c2_2P_DEC04 +XSEL<0> ADDR_N_I<3> ADDR_N_I<2> ADDR_N_I<1> ADDR_N_I<0> CS00<0> ECLK_I ++ ECLK_H<1> ECLK_B<0> ECLK_B<1> WL_O<15> WL_O<14> WL_O<13> WL_O<12> WL_O<11> ++ WL_O<10> WL_O<9> WL_O<8> WL_O<7> WL_O<6> WL_O<5> WL_O<4> WL_O<3> WL_O<2> ++ WL_O<1> WL_O<0> VDD VSS / RM_IHPSG13_1024x32_c2_2P_DEC04 +XDEC10<4> ADDR_N_I<7> ADDR_N_I<6> CS_I CS04<2> VDD VSS / ++ RM_IHPSG13_1024x32_c2_2P_DEC02 +XDEC10<3> ADDR_N_I<5> ADDR_N_I<4> CS04<3> CS00<14> VDD VSS / ++ RM_IHPSG13_1024x32_c2_2P_DEC02 +XDEC10<2> ADDR_N_I<5> ADDR_N_I<4> CS04<2> CS00<10> VDD VSS / ++ RM_IHPSG13_1024x32_c2_2P_DEC02 +XDEC10<1> ADDR_N_I<5> ADDR_N_I<4> CS04<1> CS00<6> VDD VSS / ++ RM_IHPSG13_1024x32_c2_2P_DEC02 +XDEC10<0> ADDR_N_I<5> ADDR_N_I<4> CS04<0> CS00<2> VDD VSS / ++ RM_IHPSG13_1024x32_c2_2P_DEC02 +XL2<132> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<131> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<130> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<129> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<128> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<127> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<126> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<125> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<124> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<123> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<122> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<121> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<120> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<119> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<118> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<117> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<116> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<115> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<114> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<113> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<112> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<111> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<110> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<109> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<108> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<107> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<106> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<105> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<104> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<103> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<102> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<101> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<100> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<99> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<98> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<97> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<96> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<95> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<94> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<93> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<92> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<91> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<90> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<89> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<88> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<87> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<86> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<85> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<84> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<83> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<82> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<81> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<80> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<79> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<78> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<77> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<76> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<75> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<74> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<73> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<72> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<71> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<70> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<69> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<68> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<67> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<66> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<65> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<64> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<63> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<62> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<61> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<60> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<59> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<58> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<57> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<56> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<55> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<54> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<53> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<52> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<51> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<50> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<49> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<48> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<47> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<46> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<45> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<44> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<43> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<42> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<41> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<40> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<39> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<38> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<37> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<36> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<35> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<34> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<33> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<32> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<31> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<30> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<29> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<28> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<27> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<26> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<25> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<24> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<23> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<22> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<21> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<20> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<19> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<18> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<17> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<16> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<15> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<14> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<13> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<12> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<11> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<10> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<9> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<8> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<7> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<6> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<5> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<4> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<3> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<2> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<1> VDD VSS / RSC_IHPSG13_FILLCAP8 +XDEC00<4> ADDR_N_I<7> ADDR_N_I<6> CS_I CS04<0> VDD VSS / ++ RM_IHPSG13_1024x32_c2_2P_DEC00 +XDEC00<3> ADDR_N_I<5> ADDR_N_I<4> CS04<3> CS00<12> VDD VSS / ++ RM_IHPSG13_1024x32_c2_2P_DEC00 +XDEC00<2> ADDR_N_I<5> ADDR_N_I<4> CS04<2> CS00<8> VDD VSS / ++ RM_IHPSG13_1024x32_c2_2P_DEC00 +XDEC00<1> ADDR_N_I<5> ADDR_N_I<4> CS04<1> CS00<4> VDD VSS / ++ RM_IHPSG13_1024x32_c2_2P_DEC00 +XDEC00<0> ADDR_N_I<5> ADDR_N_I<4> CS04<0> CS00<0> VDD VSS / ++ RM_IHPSG13_1024x32_c2_2P_DEC00 +XDEC01<4> ADDR_N_I<7> ADDR_N_I<6> CS_I CS04<1> VDD VSS / ++ RM_IHPSG13_1024x32_c2_2P_DEC01 +XDEC01<3> ADDR_N_I<5> ADDR_N_I<4> CS04<3> CS00<13> VDD VSS / ++ RM_IHPSG13_1024x32_c2_2P_DEC01 +XDEC01<2> ADDR_N_I<5> ADDR_N_I<4> CS04<2> CS00<9> VDD VSS / ++ RM_IHPSG13_1024x32_c2_2P_DEC01 +XDEC01<1> ADDR_N_I<5> ADDR_N_I<4> CS04<1> CS00<5> VDD VSS / ++ RM_IHPSG13_1024x32_c2_2P_DEC01 +XDEC01<0> ADDR_N_I<5> ADDR_N_I<4> CS04<0> CS00<1> VDD VSS / ++ RM_IHPSG13_1024x32_c2_2P_DEC01 +.ENDS +.SUBCKT RM_IHPSG13_1024x32_c2_2P_ROWREG8 ACLK_N_I ADDR_I<7> ADDR_I<6> ADDR_I<5> ADDR_I<4> ++ ADDR_I<3> ADDR_I<2> ADDR_I<1> ADDR_I<0> ADDR_N_O<7> ADDR_N_O<6> ADDR_N_O<5> ++ ADDR_N_O<4> ADDR_N_O<3> ADDR_N_O<2> ADDR_N_O<1> ADDR_N_O<0> BIST_ADDR_I<7> ++ BIST_ADDR_I<6> BIST_ADDR_I<5> BIST_ADDR_I<4> BIST_ADDR_I<3> BIST_ADDR_I<2> ++ BIST_ADDR_I<1> BIST_ADDR_I<0> BIST_EN_I VDD VSS +XINV<7> q_int<7> qn_int<7> VDD VSS / RSC_IHPSG13_CINVX2 +XINV<6> q_int<6> qn_int<6> VDD VSS / RSC_IHPSG13_CINVX2 +XINV<5> q_int<5> qn_int<5> VDD VSS / RSC_IHPSG13_CINVX2 +XINV<4> q_int<4> qn_int<4> VDD VSS / RSC_IHPSG13_CINVX2 +XINV<3> q_int<3> qn_int<3> VDD VSS / RSC_IHPSG13_CINVX2 +XINV<2> q_int<2> qn_int<2> VDD VSS / RSC_IHPSG13_CINVX2 +XINV<1> q_int<1> qn_int<1> VDD VSS / RSC_IHPSG13_CINVX2 +XINV<0> q_int<0> qn_int<0> VDD VSS / RSC_IHPSG13_CINVX2 +XDRV<7> qn_int<7> ADDR_N_O<7> VDD VSS / RSC_IHPSG13_CINVX8 +XDRV<6> qn_int<6> ADDR_N_O<6> VDD VSS / RSC_IHPSG13_CINVX8 +XDRV<5> qn_int<5> ADDR_N_O<5> VDD VSS / RSC_IHPSG13_CINVX8 +XDRV<4> qn_int<4> ADDR_N_O<4> VDD VSS / RSC_IHPSG13_CINVX8 +XDRV<3> qn_int<3> ADDR_N_O<3> VDD VSS / RSC_IHPSG13_CINVX8 +XDRV<2> qn_int<2> ADDR_N_O<2> VDD VSS / RSC_IHPSG13_CINVX8 +XDRV<1> qn_int<1> ADDR_N_O<1> VDD VSS / RSC_IHPSG13_CINVX8 +XDRV<0> qn_int<0> ADDR_N_O<0> VDD VSS / RSC_IHPSG13_CINVX8 +XDFF<7> BIST_EN_I BIST_ADDR_I<7> ACLK_N_I ADDR_I<7> q_int<7> net2<0> VDD ++ VSS / RSC_IHPSG13_DFNQMX2IX1 +XDFF<6> BIST_EN_I BIST_ADDR_I<6> ACLK_N_I ADDR_I<6> q_int<6> net2<1> VDD ++ VSS / RSC_IHPSG13_DFNQMX2IX1 +XDFF<5> BIST_EN_I BIST_ADDR_I<5> ACLK_N_I ADDR_I<5> q_int<5> net2<2> VDD ++ VSS / RSC_IHPSG13_DFNQMX2IX1 +XDFF<4> BIST_EN_I BIST_ADDR_I<4> ACLK_N_I ADDR_I<4> q_int<4> net2<3> VDD ++ VSS / RSC_IHPSG13_DFNQMX2IX1 +XDFF<3> BIST_EN_I BIST_ADDR_I<3> ACLK_N_I ADDR_I<3> q_int<3> net2<4> VDD ++ VSS / RSC_IHPSG13_DFNQMX2IX1 +XDFF<2> BIST_EN_I BIST_ADDR_I<2> ACLK_N_I ADDR_I<2> q_int<2> net2<5> VDD ++ VSS / RSC_IHPSG13_DFNQMX2IX1 +XDFF<1> BIST_EN_I BIST_ADDR_I<1> ACLK_N_I ADDR_I<1> q_int<1> net2<6> VDD ++ VSS / RSC_IHPSG13_DFNQMX2IX1 +XDFF<0> BIST_EN_I BIST_ADDR_I<0> ACLK_N_I ADDR_I<0> q_int<0> net2<7> VDD ++ VSS / RSC_IHPSG13_DFNQMX2IX1 +XI11<4> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI11<3> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI11<2> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI11<1> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI10 VDD VSS / RSC_IHPSG13_FILLCAP4 +.ENDS +.SUBCKT RM_IHPSG13_1024x32_c2_2P_COLDEC4 ACLK_N ADDR<3> ADDR<2> ADDR<1> ADDR<0> ++ ADDR_COL<1> ADDR_COL<0> ADDR_DEC<7> ADDR_DEC<6> ADDR_DEC<5> ADDR_DEC<4> ++ ADDR_DEC<3> ADDR_DEC<2> ADDR_DEC<1> ADDR_DEC<0> BIST_ADDR<3> BIST_ADDR<2> ++ BIST_ADDR<1> BIST_ADDR<0> BIST_EN_I VDD VSS +XI1<7> PADR<0> PADR<1> PADR<2> addr_n<7> VDD VSS / RSC_IHPSG13_NAND3X2 +XI1<6> NADR<0> PADR<1> PADR<2> addr_n<6> VDD VSS / RSC_IHPSG13_NAND3X2 +XI1<5> PADR<0> NADR<1> PADR<2> addr_n<5> VDD VSS / RSC_IHPSG13_NAND3X2 +XI1<4> NADR<0> NADR<1> PADR<2> addr_n<4> VDD VSS / RSC_IHPSG13_NAND3X2 +XI1<3> PADR<0> PADR<1> NADR<2> addr_n<3> VDD VSS / RSC_IHPSG13_NAND3X2 +XI1<2> NADR<0> PADR<1> NADR<2> addr_n<2> VDD VSS / RSC_IHPSG13_NAND3X2 +XI1<1> PADR<0> NADR<1> NADR<2> addr_n<1> VDD VSS / RSC_IHPSG13_NAND3X2 +XI1<0> NADR<0> NADR<1> NADR<2> addr_n<0> VDD VSS / RSC_IHPSG13_NAND3X2 +XDFF<3> BIST_EN_I BIST_ADDR<3> ACLK_N ADDR<3> addr_int net12<0> VDD ++ VSS / RSC_IHPSG13_DFNQMX2IX1 +XDFF<2> BIST_EN_I BIST_ADDR<2> ACLK_N ADDR<2> padr_int<2> net12<1> VDD ++ VSS / RSC_IHPSG13_DFNQMX2IX1 +XDFF<1> BIST_EN_I BIST_ADDR<1> ACLK_N ADDR<1> padr_int<1> net12<2> VDD ++ VSS / RSC_IHPSG13_DFNQMX2IX1 +XDFF<0> BIST_EN_I BIST_ADDR<0> ACLK_N ADDR<0> padr_int<0> net12<3> VDD ++ VSS / RSC_IHPSG13_DFNQMX2IX1 +XI17<4> VDD VSS / RSC_IHPSG13_FILLCAP4 +XI17<3> VDD VSS / RSC_IHPSG13_FILLCAP4 +XI17<2> VDD VSS / RSC_IHPSG13_FILLCAP4 +XI17<1> VDD VSS / RSC_IHPSG13_FILLCAP4 +XI13<2> NADR<2> PADR<2> VDD VSS / RSC_IHPSG13_INVX2 +XI13<1> NADR<1> PADR<1> VDD VSS / RSC_IHPSG13_INVX2 +XI13<0> NADR<0> PADR<0> VDD VSS / RSC_IHPSG13_INVX2 +XI2<7> addr_n<7> ADDR_DEC<7> VDD VSS / RSC_IHPSG13_INVX2 +XI2<6> addr_n<6> ADDR_DEC<6> VDD VSS / RSC_IHPSG13_INVX2 +XI2<5> addr_n<5> ADDR_DEC<5> VDD VSS / RSC_IHPSG13_INVX2 +XI2<4> addr_n<4> ADDR_DEC<4> VDD VSS / RSC_IHPSG13_INVX2 +XI2<3> addr_n<3> ADDR_DEC<3> VDD VSS / RSC_IHPSG13_INVX2 +XI2<2> addr_n<2> ADDR_DEC<2> VDD VSS / RSC_IHPSG13_INVX2 +XI2<1> addr_n<1> ADDR_DEC<1> VDD VSS / RSC_IHPSG13_INVX2 +XI2<0> addr_n<0> ADDR_DEC<0> VDD VSS / RSC_IHPSG13_INVX2 +XI3<2> padr_int<2> NADR<2> VDD VSS / RSC_IHPSG13_INVX2 +XI3<1> padr_int<1> NADR<1> VDD VSS / RSC_IHPSG13_INVX2 +XI3<0> padr_int<0> NADR<0> VDD VSS / RSC_IHPSG13_INVX2 +XI14 addr_int ADDR_COL<0> VDD VSS / RSC_IHPSG13_CBUFX2 +XI16<8> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI16<7> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI16<6> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI16<5> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI16<4> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI16<3> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI16<2> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI16<1> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI15 ADDR_COL<1> VDD VSS / RSC_IHPSG13_TIEL +.ENDS +.SUBCKT RM_IHPSG13_1024x32_c2_2P_COLCTRL4 A_ADDR_COL A_ADDR_DEC<7> A_ADDR_DEC<6> ++ A_ADDR_DEC<5> A_ADDR_DEC<4> A_ADDR_DEC<3> A_ADDR_DEC<2> A_ADDR_DEC<1> ++ A_ADDR_DEC<0> A_BIST_BM_I A_BIST_DW_I A_BIST_EN_I A_BLC<15> A_BLC<14> ++ A_BLC<13> A_BLC<12> A_BLC<11> A_BLC<10> A_BLC<9> A_BLC<8> A_BLC<7> A_BLC<6> ++ A_BLC<5> A_BLC<4> A_BLC<3> A_BLC<2> A_BLC<1> A_BLC<0> A_BLT<15> A_BLT<14> ++ A_BLT<13> A_BLT<12> A_BLT<11> A_BLT<10> A_BLT<9> A_BLT<8> A_BLT<7> A_BLT<6> ++ A_BLT<5> A_BLT<4> A_BLT<3> A_BLT<2> A_BLT<1> A_BLT<0> A_BM_I A_DCLK_B_L ++ A_DCLK_B_R A_DCLK_L A_DCLK_R A_DR_O A_DW_I A_RCLK_B_L A_RCLK_B_R A_RCLK_L ++ A_RCLK_R A_TIEH_O A_WCLK_B_L A_WCLK_B_R A_WCLK_L A_WCLK_R B_ADDR_COL ++ B_ADDR_DEC<7> B_ADDR_DEC<6> B_ADDR_DEC<5> B_ADDR_DEC<4> B_ADDR_DEC<3> ++ B_ADDR_DEC<2> B_ADDR_DEC<1> B_ADDR_DEC<0> B_BIST_BM_I B_BIST_DW_I ++ B_BIST_EN_I B_BLC<15> B_BLC<14> B_BLC<13> B_BLC<12> B_BLC<11> B_BLC<10> ++ B_BLC<9> B_BLC<8> B_BLC<7> B_BLC<6> B_BLC<5> B_BLC<4> B_BLC<3> B_BLC<2> ++ B_BLC<1> B_BLC<0> B_BLT<15> B_BLT<14> B_BLT<13> B_BLT<12> B_BLT<11> ++ B_BLT<10> B_BLT<9> B_BLT<8> B_BLT<7> B_BLT<6> B_BLT<5> B_BLT<4> B_BLT<3> ++ B_BLT<2> B_BLT<1> B_BLT<0> B_BM_I B_DCLK_B_L B_DCLK_B_R B_DCLK_L B_DCLK_R ++ B_DR_O B_DW_I B_RCLK_B_L B_RCLK_B_R B_RCLK_L B_RCLK_R B_TIEH_O B_WCLK_B_L ++ B_WCLK_B_R B_WCLK_L B_WCLK_R VDD VSS +XB_I80 B_RCLK_B_L B_WCLK_B_L net041 VDD VSS / RSC_IHPSG13_AND2X2 +XA_I80 A_RCLK_B_L A_WCLK_B_L net21 VDD VSS / RSC_IHPSG13_AND2X2 +XB_I76 B_DI_N B_DO_WRITE_P B_WR_ZERO VDD VSS / RSC_IHPSG13_AND2X4 +XB_I75 B_DI_R B_DO_WRITE_P B_WR_ONE VDD VSS / RSC_IHPSG13_AND2X4 +XA_I76 A_DI_N A_DO_WRITE_P A_WR_ZERO VDD VSS / RSC_IHPSG13_AND2X4 +XA_I75 A_DI_R A_DO_WRITE_P A_WR_ONE VDD VSS / RSC_IHPSG13_AND2X4 +XI_FILL4<26> VDD VSS / RSC_IHPSG13_FILLCAP4 +XI_FILL4<25> VDD VSS / RSC_IHPSG13_FILLCAP4 +XI_FILL4<24> VDD VSS / RSC_IHPSG13_FILLCAP4 +XI_FILL4<23> VDD VSS / RSC_IHPSG13_FILLCAP4 +XI_FILL4<22> VDD VSS / RSC_IHPSG13_FILLCAP4 +XI_FILL4<21> VDD VSS / RSC_IHPSG13_FILLCAP4 +XI_FILL4<20> VDD VSS / RSC_IHPSG13_FILLCAP4 +XI_FILL4<19> VDD VSS / RSC_IHPSG13_FILLCAP4 +XI_FILL4<18> VDD VSS / RSC_IHPSG13_FILLCAP4 +XI_FILL4<17> VDD VSS / RSC_IHPSG13_FILLCAP4 +XI_FILL4<16> VDD VSS / RSC_IHPSG13_FILLCAP4 +XI_FILL4<15> VDD VSS / RSC_IHPSG13_FILLCAP4 +XI_FILL4<14> VDD VSS / RSC_IHPSG13_FILLCAP4 +XI_FILL4<13> VDD VSS / RSC_IHPSG13_FILLCAP4 +XI_FILL4<12> VDD VSS / RSC_IHPSG13_FILLCAP4 +XI_FILL4<11> VDD VSS / RSC_IHPSG13_FILLCAP4 +XI_FILL4<10> VDD VSS / RSC_IHPSG13_FILLCAP4 +XI_FILL4<9> VDD VSS / RSC_IHPSG13_FILLCAP4 +XI_FILL4<8> VDD VSS / RSC_IHPSG13_FILLCAP4 +XI_FILL4<7> VDD VSS / RSC_IHPSG13_FILLCAP4 +XI_FILL4<6> VDD VSS / RSC_IHPSG13_FILLCAP4 +XI_FILL4<5> VDD VSS / RSC_IHPSG13_FILLCAP4 +XI_FILL4<4> VDD VSS / RSC_IHPSG13_FILLCAP4 +XI_FILL4<3> VDD VSS / RSC_IHPSG13_FILLCAP4 +XI_FILL4<2> VDD VSS / RSC_IHPSG13_FILLCAP4 +XI_FILL4<1> VDD VSS / RSC_IHPSG13_FILLCAP4 +XB_I69 B_DCLK_L B_DCLK_B_L VDD VSS / RSC_IHPSG13_CINVX4 +XB_I50 B_WCLK_L B_WCLK_B_L VDD VSS / RSC_IHPSG13_CINVX4 +XB_EBUF B_RCLK_L B_RCLK_B_L VDD VSS / RSC_IHPSG13_CINVX4 +XB_INV<1> B_N0 B_P0 VDD VSS / RSC_IHPSG13_CINVX4 +XB_INV<0> B_ADDR_COL B_N0 VDD VSS / RSC_IHPSG13_CINVX4 +XA_I69 A_DCLK_L A_DCLK_B_L VDD VSS / RSC_IHPSG13_CINVX4 +XA_I50 A_WCLK_L A_WCLK_B_L VDD VSS / RSC_IHPSG13_CINVX4 +XA_EBUF A_RCLK_L A_RCLK_B_L VDD VSS / RSC_IHPSG13_CINVX4 +XA_INV<1> A_N0 A_P0 VDD VSS / RSC_IHPSG13_CINVX4 +XA_INV<0> A_ADDR_COL A_N0 VDD VSS / RSC_IHPSG13_CINVX4 +XB_I81<1> net041 B_PRE_N VDD VSS / RSC_IHPSG13_CINVX4_WN +XB_I81<0> net041 B_PRE_N VDD VSS / RSC_IHPSG13_CINVX4_WN +XA_I81<1> net21 A_PRE_N VDD VSS / RSC_IHPSG13_CINVX4_WN +XA_I81<0> net21 A_PRE_N VDD VSS / RSC_IHPSG13_CINVX4_WN +XA_R2 A_RCLK_L A_RCLK_R / RSC_IHPSG13_MET3RES +XA_I87 A_WCLK_L A_WCLK_R / RSC_IHPSG13_MET3RES +XA_I88 A_DCLK_L A_DCLK_R / RSC_IHPSG13_MET3RES +XA_I89 A_DCLK_B_L A_DCLK_B_R / RSC_IHPSG13_MET3RES +XA_I90 A_WCLK_B_L A_WCLK_B_R / RSC_IHPSG13_MET3RES +XA_I91 A_RCLK_B_L A_RCLK_B_R / RSC_IHPSG13_MET3RES +XB_R2 B_RCLK_L B_RCLK_R / RSC_IHPSG13_MET3RES +XB_I87 B_WCLK_L B_WCLK_R / RSC_IHPSG13_MET3RES +XB_I88 B_DCLK_L B_DCLK_R / RSC_IHPSG13_MET3RES +XB_I89 B_DCLK_B_L B_DCLK_B_R / RSC_IHPSG13_MET3RES +XB_I90 B_WCLK_B_L B_WCLK_B_R / RSC_IHPSG13_MET3RES +XB_I91 B_RCLK_B_L B_RCLK_B_R / RSC_IHPSG13_MET3RES +XA_ISENSE A_SAE A_BLC_SEL A_BLT_SEL net19 net20 VDD VSS / ++ RSC_IHPSG13_DFPQD_MSAFFX2 +XB_ISENSE B_SAE B_BLC_SEL B_BLT_SEL net037 net038 VDD VSS / ++ RSC_IHPSG13_DFPQD_MSAFFX2 +XAB_BLMUX<3> A_BLC<15> A_BLC<14> A_BLC<13> A_BLC<12> A_BLC_SEL A_BLT<15> ++ A_BLT<14> A_BLT<13> A_BLT<12> A_BLT_SEL A_PRE_N A_SEL_P<15> A_SEL_P<14> ++ A_SEL_P<13> A_SEL_P<12> A_WR_ONE A_WR_ZERO B_BLC<15> B_BLC<14> B_BLC<13> ++ B_BLC<12> B_BLC_SEL B_BLT<15> B_BLT<14> B_BLT<13> B_BLT<12> B_BLT_SEL ++ B_PRE_N B_SEL_P<15> B_SEL_P<14> B_SEL_P<13> B_SEL_P<12> B_WR_ONE B_WR_ZERO ++ VDD VSS / RM_IHPSG13_1024x32_c2_2P_BLDRV +XAB_BLMUX<2> A_BLC<11> A_BLC<10> A_BLC<9> A_BLC<8> A_BLC_SEL A_BLT<11> ++ A_BLT<10> A_BLT<9> A_BLT<8> A_BLT_SEL A_PRE_N A_SEL_P<11> A_SEL_P<10> ++ A_SEL_P<9> A_SEL_P<8> A_WR_ONE A_WR_ZERO B_BLC<11> B_BLC<10> B_BLC<9> ++ B_BLC<8> B_BLC_SEL B_BLT<11> B_BLT<10> B_BLT<9> B_BLT<8> B_BLT_SEL B_PRE_N ++ B_SEL_P<11> B_SEL_P<10> B_SEL_P<9> B_SEL_P<8> B_WR_ONE B_WR_ZERO VDD ++ VSS / RM_IHPSG13_1024x32_c2_2P_BLDRV +XAB_BLMUX<1> A_BLC<7> A_BLC<6> A_BLC<5> A_BLC<4> A_BLC_SEL A_BLT<7> A_BLT<6> ++ A_BLT<5> A_BLT<4> A_BLT_SEL A_PRE_N A_SEL_P<7> A_SEL_P<6> A_SEL_P<5> ++ A_SEL_P<4> A_WR_ONE A_WR_ZERO B_BLC<7> B_BLC<6> B_BLC<5> B_BLC<4> B_BLC_SEL ++ B_BLT<7> B_BLT<6> B_BLT<5> B_BLT<4> B_BLT_SEL B_PRE_N B_SEL_P<7> B_SEL_P<6> ++ B_SEL_P<5> B_SEL_P<4> B_WR_ONE B_WR_ZERO VDD VSS / ++ RM_IHPSG13_1024x32_c2_2P_BLDRV +XAB_BLMUX<0> A_BLC<3> A_BLC<2> A_BLC<1> A_BLC<0> A_BLC_SEL A_BLT<3> A_BLT<2> ++ A_BLT<1> A_BLT<0> A_BLT_SEL A_PRE_N A_SEL_P<3> A_SEL_P<2> A_SEL_P<1> ++ A_SEL_P<0> A_WR_ONE A_WR_ZERO B_BLC<3> B_BLC<2> B_BLC<1> B_BLC<0> B_BLC_SEL ++ B_BLT<3> B_BLT<2> B_BLT<1> B_BLT<0> B_BLT_SEL B_PRE_N B_SEL_P<3> B_SEL_P<2> ++ B_SEL_P<1> B_SEL_P<0> B_WR_ONE B_WR_ZERO VDD VSS / ++ RM_IHPSG13_1024x32_c2_2P_BLDRV +XA_I51 net19 A_DR_O VDD VSS / RSC_IHPSG13_INVX4 +XB_I51 net037 B_DR_O VDD VSS / RSC_IHPSG13_INVX4 +XA_I78 A_RCLK_B_L A_SAE VDD VSS / RSC_IHPSG13_CBUFX2 +XB_I78 B_RCLK_B_L B_SAE VDD VSS / RSC_IHPSG13_CBUFX2 +XA_DREG A_BIST_EN_I A_BIST_DW_I A_DCLK_B_L A_DW_I A_DI_R net22 VDD VSS ++ / RSC_IHPSG13_DFNQMX2IX1 +XB_DREG B_BIST_EN_I B_BIST_DW_I B_DCLK_B_L B_DW_I B_DI_R net046 VDD ++ VSS / RSC_IHPSG13_DFNQMX2IX1 +XB_BREG B_BIST_EN_I B_BIST_BM_I B_DCLK_B_L B_BM_I B_BM_R net045 VDD ++ VSS / RSC_IHPSG13_DFNQMX2IX1 +XA_BREG A_BIST_EN_I A_BIST_BM_I A_DCLK_B_L A_BM_I A_BM_R net24 VDD VSS ++ / RSC_IHPSG13_DFNQMX2IX1 +XA_DEC3INV<15> net23<0> A_SEL_P<15> VDD VSS / RSC_IHPSG13_INVX2 +XA_DEC3INV<14> net23<1> A_SEL_P<14> VDD VSS / RSC_IHPSG13_INVX2 +XA_DEC3INV<13> net23<2> A_SEL_P<13> VDD VSS / RSC_IHPSG13_INVX2 +XA_DEC3INV<12> net23<3> A_SEL_P<12> VDD VSS / RSC_IHPSG13_INVX2 +XA_DEC3INV<11> net23<4> A_SEL_P<11> VDD VSS / RSC_IHPSG13_INVX2 +XA_DEC3INV<10> net23<5> A_SEL_P<10> VDD VSS / RSC_IHPSG13_INVX2 +XA_DEC3INV<9> net23<6> A_SEL_P<9> VDD VSS / RSC_IHPSG13_INVX2 +XA_DEC3INV<8> net23<7> A_SEL_P<8> VDD VSS / RSC_IHPSG13_INVX2 +XA_DEC3INV<7> net23<8> A_SEL_P<7> VDD VSS / RSC_IHPSG13_INVX2 +XA_DEC3INV<6> net23<9> A_SEL_P<6> VDD VSS / RSC_IHPSG13_INVX2 +XA_DEC3INV<5> net23<10> A_SEL_P<5> VDD VSS / RSC_IHPSG13_INVX2 +XA_DEC3INV<4> net23<11> A_SEL_P<4> VDD VSS / RSC_IHPSG13_INVX2 +XA_DEC3INV<3> net23<12> A_SEL_P<3> VDD VSS / RSC_IHPSG13_INVX2 +XA_DEC3INV<2> net23<13> A_SEL_P<2> VDD VSS / RSC_IHPSG13_INVX2 +XA_DEC3INV<1> net23<14> A_SEL_P<1> VDD VSS / RSC_IHPSG13_INVX2 +XA_DEC3INV<0> net23<15> A_SEL_P<0> VDD VSS / RSC_IHPSG13_INVX2 +XA_I83 A_BM_R A_BM_N VDD VSS / RSC_IHPSG13_INVX2 +XA_I49 A_DI_R A_DI_N VDD VSS / RSC_IHPSG13_INVX2 +XB_DEC3INV<15> net044<0> B_SEL_P<15> VDD VSS / RSC_IHPSG13_INVX2 +XB_DEC3INV<14> net044<1> B_SEL_P<14> VDD VSS / RSC_IHPSG13_INVX2 +XB_DEC3INV<13> net044<2> B_SEL_P<13> VDD VSS / RSC_IHPSG13_INVX2 +XB_DEC3INV<12> net044<3> B_SEL_P<12> VDD VSS / RSC_IHPSG13_INVX2 +XB_DEC3INV<11> net044<4> B_SEL_P<11> VDD VSS / RSC_IHPSG13_INVX2 +XB_DEC3INV<10> net044<5> B_SEL_P<10> VDD VSS / RSC_IHPSG13_INVX2 +XB_DEC3INV<9> net044<6> B_SEL_P<9> VDD VSS / RSC_IHPSG13_INVX2 +XB_DEC3INV<8> net044<7> B_SEL_P<8> VDD VSS / RSC_IHPSG13_INVX2 +XB_DEC3INV<7> net044<8> B_SEL_P<7> VDD VSS / RSC_IHPSG13_INVX2 +XB_DEC3INV<6> net044<9> B_SEL_P<6> VDD VSS / RSC_IHPSG13_INVX2 +XB_DEC3INV<5> net044<10> B_SEL_P<5> VDD VSS / RSC_IHPSG13_INVX2 +XB_DEC3INV<4> net044<11> B_SEL_P<4> VDD VSS / RSC_IHPSG13_INVX2 +XB_DEC3INV<3> net044<12> B_SEL_P<3> VDD VSS / RSC_IHPSG13_INVX2 +XB_DEC3INV<2> net044<13> B_SEL_P<2> VDD VSS / RSC_IHPSG13_INVX2 +XB_DEC3INV<1> net044<14> B_SEL_P<1> VDD VSS / RSC_IHPSG13_INVX2 +XB_DEC3INV<0> net044<15> B_SEL_P<0> VDD VSS / RSC_IHPSG13_INVX2 +XB_I83 B_BM_R B_BM_N VDD VSS / RSC_IHPSG13_INVX2 +XB_I49 B_DI_R B_DI_N VDD VSS / RSC_IHPSG13_INVX2 +XI_FILL8<20> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI_FILL8<19> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI_FILL8<18> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI_FILL8<17> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI_FILL8<16> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI_FILL8<15> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI_FILL8<14> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI_FILL8<13> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI_FILL8<12> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI_FILL8<11> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI_FILL8<10> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI_FILL8<9> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI_FILL8<8> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI_FILL8<7> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI_FILL8<6> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI_FILL8<5> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI_FILL8<4> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI_FILL8<3> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI_FILL8<2> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI_FILL8<1> VDD VSS / RSC_IHPSG13_FILLCAP8 +XA_I44 A_BM_N A_WCLK_B_L A_DO_WRITE_P VDD VSS / RSC_IHPSG13_NOR2X2 +XB_I44 B_BM_N B_WCLK_B_L B_DO_WRITE_P VDD VSS / RSC_IHPSG13_NOR2X2 +XA_DEC3<15> A_P0 A_ADDR_DEC<7> net23<0> VDD VSS / RSC_IHPSG13_NAND2X2 +XA_DEC3<14> A_P0 A_ADDR_DEC<6> net23<1> VDD VSS / RSC_IHPSG13_NAND2X2 +XA_DEC3<13> A_P0 A_ADDR_DEC<5> net23<2> VDD VSS / RSC_IHPSG13_NAND2X2 +XA_DEC3<12> A_P0 A_ADDR_DEC<4> net23<3> VDD VSS / RSC_IHPSG13_NAND2X2 +XA_DEC3<11> A_P0 A_ADDR_DEC<3> net23<4> VDD VSS / RSC_IHPSG13_NAND2X2 +XA_DEC3<10> A_P0 A_ADDR_DEC<2> net23<5> VDD VSS / RSC_IHPSG13_NAND2X2 +XA_DEC3<9> A_P0 A_ADDR_DEC<1> net23<6> VDD VSS / RSC_IHPSG13_NAND2X2 +XA_DEC3<8> A_P0 A_ADDR_DEC<0> net23<7> VDD VSS / RSC_IHPSG13_NAND2X2 +XA_DEC3<7> A_N0 A_ADDR_DEC<7> net23<8> VDD VSS / RSC_IHPSG13_NAND2X2 +XA_DEC3<6> A_N0 A_ADDR_DEC<6> net23<9> VDD VSS / RSC_IHPSG13_NAND2X2 +XA_DEC3<5> A_N0 A_ADDR_DEC<5> net23<10> VDD VSS / RSC_IHPSG13_NAND2X2 +XA_DEC3<4> A_N0 A_ADDR_DEC<4> net23<11> VDD VSS / RSC_IHPSG13_NAND2X2 +XA_DEC3<3> A_N0 A_ADDR_DEC<3> net23<12> VDD VSS / RSC_IHPSG13_NAND2X2 +XA_DEC3<2> A_N0 A_ADDR_DEC<2> net23<13> VDD VSS / RSC_IHPSG13_NAND2X2 +XA_DEC3<1> A_N0 A_ADDR_DEC<1> net23<14> VDD VSS / RSC_IHPSG13_NAND2X2 +XA_DEC3<0> A_N0 A_ADDR_DEC<0> net23<15> VDD VSS / RSC_IHPSG13_NAND2X2 +XB_DEC3<15> B_P0 B_ADDR_DEC<7> net044<0> VDD VSS / RSC_IHPSG13_NAND2X2 +XB_DEC3<14> B_P0 B_ADDR_DEC<6> net044<1> VDD VSS / RSC_IHPSG13_NAND2X2 +XB_DEC3<13> B_P0 B_ADDR_DEC<5> net044<2> VDD VSS / RSC_IHPSG13_NAND2X2 +XB_DEC3<12> B_P0 B_ADDR_DEC<4> net044<3> VDD VSS / RSC_IHPSG13_NAND2X2 +XB_DEC3<11> B_P0 B_ADDR_DEC<3> net044<4> VDD VSS / RSC_IHPSG13_NAND2X2 +XB_DEC3<10> B_P0 B_ADDR_DEC<2> net044<5> VDD VSS / RSC_IHPSG13_NAND2X2 +XB_DEC3<9> B_P0 B_ADDR_DEC<1> net044<6> VDD VSS / RSC_IHPSG13_NAND2X2 +XB_DEC3<8> B_P0 B_ADDR_DEC<0> net044<7> VDD VSS / RSC_IHPSG13_NAND2X2 +XB_DEC3<7> B_N0 B_ADDR_DEC<7> net044<8> VDD VSS / RSC_IHPSG13_NAND2X2 +XB_DEC3<6> B_N0 B_ADDR_DEC<6> net044<9> VDD VSS / RSC_IHPSG13_NAND2X2 +XB_DEC3<5> B_N0 B_ADDR_DEC<5> net044<10> VDD VSS / RSC_IHPSG13_NAND2X2 +XB_DEC3<4> B_N0 B_ADDR_DEC<4> net044<11> VDD VSS / RSC_IHPSG13_NAND2X2 +XB_DEC3<3> B_N0 B_ADDR_DEC<3> net044<12> VDD VSS / RSC_IHPSG13_NAND2X2 +XB_DEC3<2> B_N0 B_ADDR_DEC<2> net044<13> VDD VSS / RSC_IHPSG13_NAND2X2 +XB_DEC3<1> B_N0 B_ADDR_DEC<1> net044<14> VDD VSS / RSC_IHPSG13_NAND2X2 +XB_DEC3<0> B_N0 B_ADDR_DEC<0> net044<15> VDD VSS / RSC_IHPSG13_NAND2X2 +XB_BM_TIEH B_TIEH_O VDD VSS / RSC_IHPSG13_TIEH +XA_BM_TIEH A_TIEH_O VDD VSS / RSC_IHPSG13_TIEH +.ENDS + + +.SUBCKT RM_IHPSG13_1024x32_c2_2P_ROWDEC5 ADDR_N_I<4> ADDR_N_I<3> ADDR_N_I<2> ADDR_N_I<1> ++ ADDR_N_I<0> CS_I ECLK_I WL_O<31> WL_O<30> WL_O<29> WL_O<28> WL_O<27> ++ WL_O<26> WL_O<25> WL_O<24> WL_O<23> WL_O<22> WL_O<21> WL_O<20> WL_O<19> ++ WL_O<18> WL_O<17> WL_O<16> WL_O<15> WL_O<14> WL_O<13> WL_O<12> WL_O<11> ++ WL_O<10> WL_O<9> WL_O<8> WL_O<7> WL_O<6> WL_O<5> WL_O<4> WL_O<3> WL_O<2> ++ WL_O<1> WL_O<0> VDD VSS +XDEC00 ADDR_N_I<5> ADDR_N_I<4> CS_I CS00<0> VDD VSS / ++ RM_IHPSG13_1024x32_c2_2P_DEC00 +XSEL<1> ADDR_N_I<3> ADDR_N_I<2> ADDR_N_I<1> ADDR_N_I<0> CS00<1> ECLK_H<1> ++ ECLK_H<2> ECLK_B<1> ECLK_B<2> WL_O<31> WL_O<30> WL_O<29> WL_O<28> WL_O<27> ++ WL_O<26> WL_O<25> WL_O<24> WL_O<23> WL_O<22> WL_O<21> WL_O<20> WL_O<19> ++ WL_O<18> WL_O<17> WL_O<16> VDD VSS / RM_IHPSG13_1024x32_c2_2P_DEC04 +XSEL<0> ADDR_N_I<3> ADDR_N_I<2> ADDR_N_I<1> ADDR_N_I<0> CS00<0> ECLK_I ++ ECLK_H<1> ECLK_B<0> ECLK_B<1> WL_O<15> WL_O<14> WL_O<13> WL_O<12> WL_O<11> ++ WL_O<10> WL_O<9> WL_O<8> WL_O<7> WL_O<6> WL_O<5> WL_O<4> WL_O<3> WL_O<2> ++ WL_O<1> WL_O<0> VDD VSS / RM_IHPSG13_1024x32_c2_2P_DEC04 +XDEC01 ADDR_N_I<5> ADDR_N_I<4> CS_I CS00<1> VDD VSS / ++ RM_IHPSG13_1024x32_c2_2P_DEC01 +XL2<18> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<17> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<16> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<15> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<14> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<13> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<12> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<11> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<10> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<9> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<8> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<7> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<6> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<5> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<4> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<3> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<2> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<1> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI0 ADDR_N_I<5> VDD VSS / RSC_IHPSG13_TIEL +.ENDS +.SUBCKT RM_IHPSG13_1024x32_c2_2P_ROWREG5 ACLK_N_I ADDR_I<4> ADDR_I<3> ADDR_I<2> ADDR_I<1> ++ ADDR_I<0> ADDR_N_O<4> ADDR_N_O<3> ADDR_N_O<2> ADDR_N_O<1> ADDR_N_O<0> ++ BIST_ADDR_I<4> BIST_ADDR_I<3> BIST_ADDR_I<2> BIST_ADDR_I<1> BIST_ADDR_I<0> ++ BIST_EN_I VDD VSS +XINV<4> q_int<4> qn_int<4> VDD VSS / RSC_IHPSG13_CINVX2 +XINV<3> q_int<3> qn_int<3> VDD VSS / RSC_IHPSG13_CINVX2 +XINV<2> q_int<2> qn_int<2> VDD VSS / RSC_IHPSG13_CINVX2 +XINV<1> q_int<1> qn_int<1> VDD VSS / RSC_IHPSG13_CINVX2 +XINV<0> q_int<0> qn_int<0> VDD VSS / RSC_IHPSG13_CINVX2 +XDRV<4> qn_int<4> ADDR_N_O<4> VDD VSS / RSC_IHPSG13_CINVX8 +XDRV<3> qn_int<3> ADDR_N_O<3> VDD VSS / RSC_IHPSG13_CINVX8 +XDRV<2> qn_int<2> ADDR_N_O<2> VDD VSS / RSC_IHPSG13_CINVX8 +XDRV<1> qn_int<1> ADDR_N_O<1> VDD VSS / RSC_IHPSG13_CINVX8 +XDRV<0> qn_int<0> ADDR_N_O<0> VDD VSS / RSC_IHPSG13_CINVX8 +XDFF<4> BIST_EN_I BIST_ADDR_I<4> ACLK_N_I ADDR_I<4> q_int<4> net2<0> VDD ++ VSS / RSC_IHPSG13_DFNQMX2IX1 +XDFF<3> BIST_EN_I BIST_ADDR_I<3> ACLK_N_I ADDR_I<3> q_int<3> net2<1> VDD ++ VSS / RSC_IHPSG13_DFNQMX2IX1 +XDFF<2> BIST_EN_I BIST_ADDR_I<2> ACLK_N_I ADDR_I<2> q_int<2> net2<2> VDD ++ VSS / RSC_IHPSG13_DFNQMX2IX1 +XDFF<1> BIST_EN_I BIST_ADDR_I<1> ACLK_N_I ADDR_I<1> q_int<1> net2<3> VDD ++ VSS / RSC_IHPSG13_DFNQMX2IX1 +XDFF<0> BIST_EN_I BIST_ADDR_I<0> ACLK_N_I ADDR_I<0> q_int<0> net2<4> VDD ++ VSS / RSC_IHPSG13_DFNQMX2IX1 +XI11<16> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI11<15> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI11<14> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI11<13> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI11<12> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI11<11> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI11<10> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI11<9> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI11<8> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI11<7> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI11<6> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI11<5> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI11<4> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI11<3> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI11<2> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI11<1> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI12<3> VDD VSS / RSC_IHPSG13_FILLCAP4 +XI12<2> VDD VSS / RSC_IHPSG13_FILLCAP4 +XI12<1> VDD VSS / RSC_IHPSG13_FILLCAP4 +XI12<0> VDD VSS / RSC_IHPSG13_FILLCAP4 +.ENDS + + +.SUBCKT RM_IHPSG13_1024x32_c2_2P_COLDEC3 ACLK_N ADDR<2> ADDR<1> ADDR<0> ADDR_COL<1> ++ ADDR_COL<0> ADDR_DEC<7> ADDR_DEC<6> ADDR_DEC<5> ADDR_DEC<4> ADDR_DEC<3> ++ ADDR_DEC<2> ADDR_DEC<1> ADDR_DEC<0> BIST_ADDR<2> BIST_ADDR<1> BIST_ADDR<0> ++ BIST_EN_I VDD VSS +XI1<7> PADR<0> PADR<1> PADR<2> addr_n<7> VDD VSS / RSC_IHPSG13_NAND3X2 +XI1<6> NADR<0> PADR<1> PADR<2> addr_n<6> VDD VSS / RSC_IHPSG13_NAND3X2 +XI1<5> PADR<0> NADR<1> PADR<2> addr_n<5> VDD VSS / RSC_IHPSG13_NAND3X2 +XI1<4> NADR<0> NADR<1> PADR<2> addr_n<4> VDD VSS / RSC_IHPSG13_NAND3X2 +XI1<3> PADR<0> PADR<1> NADR<2> addr_n<3> VDD VSS / RSC_IHPSG13_NAND3X2 +XI1<2> NADR<0> PADR<1> NADR<2> addr_n<2> VDD VSS / RSC_IHPSG13_NAND3X2 +XI1<1> PADR<0> NADR<1> NADR<2> addr_n<1> VDD VSS / RSC_IHPSG13_NAND3X2 +XI1<0> NADR<0> NADR<1> NADR<2> addr_n<0> VDD VSS / RSC_IHPSG13_NAND3X2 +XDFF<2> BIST_EN_I BIST_ADDR<2> ACLK_N ADDR<2> padr_int<2> net13<0> VDD ++ VSS / RSC_IHPSG13_DFNQMX2IX1 +XDFF<1> BIST_EN_I BIST_ADDR<1> ACLK_N ADDR<1> padr_int<1> net13<1> VDD ++ VSS / RSC_IHPSG13_DFNQMX2IX1 +XDFF<0> BIST_EN_I BIST_ADDR<0> ACLK_N ADDR<0> padr_int<0> net13<2> VDD ++ VSS / RSC_IHPSG13_DFNQMX2IX1 +XI15<1> ADDR_COL<1> VDD VSS / RSC_IHPSG13_TIEL +XI15<0> ADDR_COL<0> VDD VSS / RSC_IHPSG13_TIEL +XI13<2> NADR<2> PADR<2> VDD VSS / RSC_IHPSG13_INVX2 +XI13<1> NADR<1> PADR<1> VDD VSS / RSC_IHPSG13_INVX2 +XI13<0> NADR<0> PADR<0> VDD VSS / RSC_IHPSG13_INVX2 +XI3<2> padr_int<2> NADR<2> VDD VSS / RSC_IHPSG13_INVX2 +XI3<1> padr_int<1> NADR<1> VDD VSS / RSC_IHPSG13_INVX2 +XI3<0> padr_int<0> NADR<0> VDD VSS / RSC_IHPSG13_INVX2 +XI2<7> addr_n<7> ADDR_DEC<7> VDD VSS / RSC_IHPSG13_INVX2 +XI2<6> addr_n<6> ADDR_DEC<6> VDD VSS / RSC_IHPSG13_INVX2 +XI2<5> addr_n<5> ADDR_DEC<5> VDD VSS / RSC_IHPSG13_INVX2 +XI2<4> addr_n<4> ADDR_DEC<4> VDD VSS / RSC_IHPSG13_INVX2 +XI2<3> addr_n<3> ADDR_DEC<3> VDD VSS / RSC_IHPSG13_INVX2 +XI2<2> addr_n<2> ADDR_DEC<2> VDD VSS / RSC_IHPSG13_INVX2 +XI2<1> addr_n<1> ADDR_DEC<1> VDD VSS / RSC_IHPSG13_INVX2 +XI2<0> addr_n<0> ADDR_DEC<0> VDD VSS / RSC_IHPSG13_INVX2 +XI17<4> VDD VSS / RSC_IHPSG13_FILLCAP4 +XI17<3> VDD VSS / RSC_IHPSG13_FILLCAP4 +XI17<2> VDD VSS / RSC_IHPSG13_FILLCAP4 +XI17<1> VDD VSS / RSC_IHPSG13_FILLCAP4 +XI16<11> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI16<10> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI16<9> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI16<8> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI16<7> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI16<6> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI16<5> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI16<4> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI16<3> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI16<2> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI16<1> VDD VSS / RSC_IHPSG13_FILLCAP8 +.ENDS +.SUBCKT RSC_IHPSG13_DFPQD_MSAFFX2P CP DN DP QN QP VDD VSS +XI_AMP CP DN DP QN QP VDD VSS / RSC_IHPSG13_DFPQD_MSAFFX2 +.ENDS +.SUBCKT RM_IHPSG13_1024x32_c2_2P_COLCTRL3 A_ADDR_DEC<7> A_ADDR_DEC<6> A_ADDR_DEC<5> ++ A_ADDR_DEC<4> A_ADDR_DEC<3> A_ADDR_DEC<2> A_ADDR_DEC<1> A_ADDR_DEC<0> ++ A_BIST_BM_I A_BIST_DW_I A_BIST_EN_I A_BLC<7> A_BLC<6> A_BLC<5> A_BLC<4> ++ A_BLC<3> A_BLC<2> A_BLC<1> A_BLC<0> A_BLT<7> A_BLT<6> A_BLT<5> A_BLT<4> ++ A_BLT<3> A_BLT<2> A_BLT<1> A_BLT<0> A_BM_I A_DCLK_B_L A_DCLK_B_R A_DCLK_L ++ A_DCLK_R A_DR_O A_DW_I A_RCLK_B_L A_RCLK_B_R A_RCLK_L A_RCLK_R A_TIEH_O ++ A_WCLK_B_L A_WCLK_B_R A_WCLK_L A_WCLK_R B_ADDR_DEC<7> B_ADDR_DEC<6> ++ B_ADDR_DEC<5> B_ADDR_DEC<4> B_ADDR_DEC<3> B_ADDR_DEC<2> B_ADDR_DEC<1> ++ B_ADDR_DEC<0> B_BIST_BM_I B_BIST_DW_I B_BIST_EN_I B_BLC<7> B_BLC<6> B_BLC<5> ++ B_BLC<4> B_BLC<3> B_BLC<2> B_BLC<1> B_BLC<0> B_BLT<7> B_BLT<6> B_BLT<5> ++ B_BLT<4> B_BLT<3> B_BLT<2> B_BLT<1> B_BLT<0> B_BM_I B_DCLK_B_L B_DCLK_B_R ++ B_DCLK_L B_DCLK_R B_DR_O B_DW_I B_RCLK_B_L B_RCLK_B_R B_RCLK_L B_RCLK_R ++ B_TIEH_O B_WCLK_B_L B_WCLK_B_R B_WCLK_L B_WCLK_R VDD VSS +XB_DREG B_BIST_EN_I B_BIST_DW_I B_DCLK_B_L B_DW_I B_DI_R net044 VDD ++ VSS / RSC_IHPSG13_DFNQMX2IX1 +XB_BREG B_BIST_EN_I B_BIST_BM_I B_DCLK_B_L B_BM_I B_BM_R net043 VDD ++ VSS / RSC_IHPSG13_DFNQMX2IX1 +XA_DREG A_BIST_EN_I A_BIST_DW_I A_DCLK_B_L A_DW_I A_DI_R net22 VDD VSS ++ / RSC_IHPSG13_DFNQMX2IX1 +XA_BREG A_BIST_EN_I A_BIST_BM_I A_DCLK_B_L A_BM_I A_BM_R net23 VDD VSS ++ / RSC_IHPSG13_DFNQMX2IX1 +XI_FILL8<11> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI_FILL8<10> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI_FILL8<9> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI_FILL8<8> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI_FILL8<7> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI_FILL8<6> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI_FILL8<5> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI_FILL8<4> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI_FILL8<3> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI_FILL8<2> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI_FILL8<1> VDD VSS / RSC_IHPSG13_FILLCAP8 +XB_I51 net037 B_DR_O VDD VSS / RSC_IHPSG13_INVX4 +XA_I51 net19 A_DR_O VDD VSS / RSC_IHPSG13_INVX4 +XB_I44 B_BM_N B_WCLK_B_L B_DO_WRITE_P VDD VSS / RSC_IHPSG13_NOR2X2 +XA_I44 A_BM_N A_WCLK_B_L A_DO_WRITE_P VDD VSS / RSC_IHPSG13_NOR2X2 +XB_BM_TIEH B_TIEH_O VDD VSS / RSC_IHPSG13_TIEH +XA_BM_TIEH A_TIEH_O VDD VSS / RSC_IHPSG13_TIEH +XB_ISENSE B_SAE B_BLC_SEL B_BLT_SEL net037 net038 VDD VSS / ++ RSC_IHPSG13_DFPQD_MSAFFX2P +XA_ISENSE A_SAE A_BLC_SEL A_BLT_SEL net19 net20 VDD VSS / ++ RSC_IHPSG13_DFPQD_MSAFFX2P +XB_I49 B_DI_R B_DI_N VDD VSS / RSC_IHPSG13_INVX2 +XB_I83 B_BM_R B_BM_N VDD VSS / RSC_IHPSG13_INVX2 +XA_I49 A_DI_R A_DI_N VDD VSS / RSC_IHPSG13_INVX2 +XA_I83 A_BM_R A_BM_N VDD VSS / RSC_IHPSG13_INVX2 +XB_I69 B_DCLK_L B_DCLK_B_L VDD VSS / RSC_IHPSG13_CINVX2 +XB_I50 B_WCLK_L B_WCLK_B_L VDD VSS / RSC_IHPSG13_CINVX2 +XB_EBUF B_RCLK_L B_RCLK_B_L VDD VSS / RSC_IHPSG13_CINVX2 +XA_I69 A_DCLK_L A_DCLK_B_L VDD VSS / RSC_IHPSG13_CINVX2 +XA_I50 A_WCLK_L A_WCLK_B_L VDD VSS / RSC_IHPSG13_CINVX2 +XA_EBUF A_RCLK_L A_RCLK_B_L VDD VSS / RSC_IHPSG13_CINVX2 +XAB_BLMUX<1> A_BLC<7> A_BLC<6> A_BLC<5> A_BLC<4> A_BLC_SEL A_BLT<7> A_BLT<6> ++ A_BLT<5> A_BLT<4> A_BLT_SEL A_PRE_N A_ADDR_DEC<7> A_ADDR_DEC<6> ++ A_ADDR_DEC<5> A_ADDR_DEC<4> A_WR_ONE A_WR_ZERO B_BLC<7> B_BLC<6> B_BLC<5> ++ B_BLC<4> B_BLC_SEL B_BLT<7> B_BLT<6> B_BLT<5> B_BLT<4> B_BLT_SEL B_PRE_N ++ B_ADDR_DEC<7> B_ADDR_DEC<6> B_ADDR_DEC<5> B_ADDR_DEC<4> B_WR_ONE B_WR_ZERO ++ VDD VSS / RM_IHPSG13_1024x32_c2_2P_BLDRV +XAB_BLMUX<0> A_BLC<3> A_BLC<2> A_BLC<1> A_BLC<0> A_BLC_SEL A_BLT<3> A_BLT<2> ++ A_BLT<1> A_BLT<0> A_BLT_SEL A_PRE_N A_ADDR_DEC<3> A_ADDR_DEC<2> ++ A_ADDR_DEC<1> A_ADDR_DEC<0> A_WR_ONE A_WR_ZERO B_BLC<3> B_BLC<2> B_BLC<1> ++ B_BLC<0> B_BLC_SEL B_BLT<3> B_BLT<2> B_BLT<1> B_BLT<0> B_BLT_SEL B_PRE_N ++ B_ADDR_DEC<3> B_ADDR_DEC<2> B_ADDR_DEC<1> B_ADDR_DEC<0> B_WR_ONE B_WR_ZERO ++ VDD VSS / RM_IHPSG13_1024x32_c2_2P_BLDRV +XB_I78 B_RCLK_B_L B_SAE VDD VSS / RSC_IHPSG13_CBUFX2 +XA_I78 A_RCLK_B_L A_SAE VDD VSS / RSC_IHPSG13_CBUFX2 +XB_I88 B_DCLK_L B_DCLK_R / RSC_IHPSG13_MET3RES +XB_I87 B_WCLK_L B_WCLK_R / RSC_IHPSG13_MET3RES +XB_R2 B_RCLK_L B_RCLK_R / RSC_IHPSG13_MET3RES +XB_I91 B_RCLK_B_L B_RCLK_B_R / RSC_IHPSG13_MET3RES +XB_I90 B_WCLK_B_L B_WCLK_B_R / RSC_IHPSG13_MET3RES +XB_I89 B_DCLK_B_L B_DCLK_B_R / RSC_IHPSG13_MET3RES +XA_I88 A_DCLK_L A_DCLK_R / RSC_IHPSG13_MET3RES +XA_I87 A_WCLK_L A_WCLK_R / RSC_IHPSG13_MET3RES +XA_R2 A_RCLK_L A_RCLK_R / RSC_IHPSG13_MET3RES +XA_I91 A_RCLK_B_L A_RCLK_B_R / RSC_IHPSG13_MET3RES +XA_I90 A_WCLK_B_L A_WCLK_B_R / RSC_IHPSG13_MET3RES +XA_I89 A_DCLK_B_L A_DCLK_B_R / RSC_IHPSG13_MET3RES +XB_I80 B_WCLK_B_L B_RCLK_B_L net041 VDD VSS / RSC_IHPSG13_AND2X2 +XB_I76 B_DO_WRITE_P B_DI_N B_WR_ZERO VDD VSS / RSC_IHPSG13_AND2X2 +XB_I75 B_DO_WRITE_P B_DI_R B_WR_ONE VDD VSS / RSC_IHPSG13_AND2X2 +XA_I80 A_WCLK_B_L A_RCLK_B_L net21 VDD VSS / RSC_IHPSG13_AND2X2 +XA_I76 A_DI_N A_DO_WRITE_P A_WR_ZERO VDD VSS / RSC_IHPSG13_AND2X2 +XA_I75 A_DI_R A_DO_WRITE_P A_WR_ONE VDD VSS / RSC_IHPSG13_AND2X2 +XB_I81 net041 B_PRE_N VDD VSS / RSC_IHPSG13_CINVX4_WN +XA_I81 net21 A_PRE_N VDD VSS / RSC_IHPSG13_CINVX4_WN +XI_FILL4<10> VDD VSS / RSC_IHPSG13_FILLCAP4 +XI_FILL4<9> VDD VSS / RSC_IHPSG13_FILLCAP4 +XI_FILL4<8> VDD VSS / RSC_IHPSG13_FILLCAP4 +XI_FILL4<7> VDD VSS / RSC_IHPSG13_FILLCAP4 +XI_FILL4<6> VDD VSS / RSC_IHPSG13_FILLCAP4 +XI_FILL4<5> VDD VSS / RSC_IHPSG13_FILLCAP4 +XI_FILL4<4> VDD VSS / RSC_IHPSG13_FILLCAP4 +XI_FILL4<3> VDD VSS / RSC_IHPSG13_FILLCAP4 +XI_FILL4<2> VDD VSS / RSC_IHPSG13_FILLCAP4 +XI_FILL4<1> VDD VSS / RSC_IHPSG13_FILLCAP4 +.ENDS + +.SUBCKT RM_IHPSG13_1024x32_c2_2P_ROWDEC6 ADDR_N_I<5> ADDR_N_I<4> ADDR_N_I<3> ADDR_N_I<2> ++ ADDR_N_I<1> ADDR_N_I<0> CS_I ECLK_I WL_O<63> WL_O<62> WL_O<61> WL_O<60> ++ WL_O<59> WL_O<58> WL_O<57> WL_O<56> WL_O<55> WL_O<54> WL_O<53> WL_O<52> ++ WL_O<51> WL_O<50> WL_O<49> WL_O<48> WL_O<47> WL_O<46> WL_O<45> WL_O<44> ++ WL_O<43> WL_O<42> WL_O<41> WL_O<40> WL_O<39> WL_O<38> WL_O<37> WL_O<36> ++ WL_O<35> WL_O<34> WL_O<33> WL_O<32> WL_O<31> WL_O<30> WL_O<29> WL_O<28> ++ WL_O<27> WL_O<26> WL_O<25> WL_O<24> WL_O<23> WL_O<22> WL_O<21> WL_O<20> ++ WL_O<19> WL_O<18> WL_O<17> WL_O<16> WL_O<15> WL_O<14> WL_O<13> WL_O<12> ++ WL_O<11> WL_O<10> WL_O<9> WL_O<8> WL_O<7> WL_O<6> WL_O<5> WL_O<4> WL_O<3> ++ WL_O<2> WL_O<1> WL_O<0> VDD VSS +XDEC10 ADDR_N_I<5> ADDR_N_I<4> CS_I CS00<2> VDD VSS / ++ RM_IHPSG13_1024x32_c2_2P_DEC02 +XDEC00 ADDR_N_I<5> ADDR_N_I<4> CS_I CS00<0> VDD VSS / ++ RM_IHPSG13_1024x32_c2_2P_DEC00 +XSEL<3> ADDR_N_I<3> ADDR_N_I<2> ADDR_N_I<1> ADDR_N_I<0> CS00<3> ECLK_H<3> ++ ECLK_H<4> ECLK_B<3> ECLK_B<4> WL_O<63> WL_O<62> WL_O<61> WL_O<60> WL_O<59> ++ WL_O<58> WL_O<57> WL_O<56> WL_O<55> WL_O<54> WL_O<53> WL_O<52> WL_O<51> ++ WL_O<50> WL_O<49> WL_O<48> VDD VSS / RM_IHPSG13_1024x32_c2_2P_DEC04 +XSEL<2> ADDR_N_I<3> ADDR_N_I<2> ADDR_N_I<1> ADDR_N_I<0> CS00<2> ECLK_H<2> ++ ECLK_H<3> ECLK_B<2> ECLK_B<3> WL_O<47> WL_O<46> WL_O<45> WL_O<44> WL_O<43> ++ WL_O<42> WL_O<41> WL_O<40> WL_O<39> WL_O<38> WL_O<37> WL_O<36> WL_O<35> ++ WL_O<34> WL_O<33> WL_O<32> VDD VSS / RM_IHPSG13_1024x32_c2_2P_DEC04 +XSEL<1> ADDR_N_I<3> ADDR_N_I<2> ADDR_N_I<1> ADDR_N_I<0> CS00<1> ECLK_H<1> ++ ECLK_H<2> ECLK_B<1> ECLK_B<2> WL_O<31> WL_O<30> WL_O<29> WL_O<28> WL_O<27> ++ WL_O<26> WL_O<25> WL_O<24> WL_O<23> WL_O<22> WL_O<21> WL_O<20> WL_O<19> ++ WL_O<18> WL_O<17> WL_O<16> VDD VSS / RM_IHPSG13_1024x32_c2_2P_DEC04 +XSEL<0> ADDR_N_I<3> ADDR_N_I<2> ADDR_N_I<1> ADDR_N_I<0> CS00<0> ECLK_I ++ ECLK_H<1> ECLK_B<0> ECLK_B<1> WL_O<15> WL_O<14> WL_O<13> WL_O<12> WL_O<11> ++ WL_O<10> WL_O<9> WL_O<8> WL_O<7> WL_O<6> WL_O<5> WL_O<4> WL_O<3> WL_O<2> ++ WL_O<1> WL_O<0> VDD VSS / RM_IHPSG13_1024x32_c2_2P_DEC04 +XDEC11 ADDR_N_I<5> ADDR_N_I<4> CS_I CS00<3> VDD VSS / ++ RM_IHPSG13_1024x32_c2_2P_DEC03 +XL2<36> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<35> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<34> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<33> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<32> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<31> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<30> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<29> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<28> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<27> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<26> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<25> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<24> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<23> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<22> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<21> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<20> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<19> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<18> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<17> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<16> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<15> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<14> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<13> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<12> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<11> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<10> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<9> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<8> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<7> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<6> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<5> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<4> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<3> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<2> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<1> VDD VSS / RSC_IHPSG13_FILLCAP8 +XDEC01 ADDR_N_I<5> ADDR_N_I<4> CS_I CS00<1> VDD VSS / ++ RM_IHPSG13_1024x32_c2_2P_DEC01 +.ENDS +.SUBCKT RM_IHPSG13_1024x32_c2_2P_ROWREG6 ACLK_N_I ADDR_I<5> ADDR_I<4> ADDR_I<3> ADDR_I<2> ++ ADDR_I<1> ADDR_I<0> ADDR_N_O<5> ADDR_N_O<4> ADDR_N_O<3> ADDR_N_O<2> ++ ADDR_N_O<1> ADDR_N_O<0> BIST_ADDR_I<5> BIST_ADDR_I<4> BIST_ADDR_I<3> ++ BIST_ADDR_I<2> BIST_ADDR_I<1> BIST_ADDR_I<0> BIST_EN_I VDD VSS +XINV<5> q_int<5> qn_int<5> VDD VSS / RSC_IHPSG13_CINVX2 +XINV<4> q_int<4> qn_int<4> VDD VSS / RSC_IHPSG13_CINVX2 +XINV<3> q_int<3> qn_int<3> VDD VSS / RSC_IHPSG13_CINVX2 +XINV<2> q_int<2> qn_int<2> VDD VSS / RSC_IHPSG13_CINVX2 +XINV<1> q_int<1> qn_int<1> VDD VSS / RSC_IHPSG13_CINVX2 +XINV<0> q_int<0> qn_int<0> VDD VSS / RSC_IHPSG13_CINVX2 +XDRV<5> qn_int<5> ADDR_N_O<5> VDD VSS / RSC_IHPSG13_CINVX8 +XDRV<4> qn_int<4> ADDR_N_O<4> VDD VSS / RSC_IHPSG13_CINVX8 +XDRV<3> qn_int<3> ADDR_N_O<3> VDD VSS / RSC_IHPSG13_CINVX8 +XDRV<2> qn_int<2> ADDR_N_O<2> VDD VSS / RSC_IHPSG13_CINVX8 +XDRV<1> qn_int<1> ADDR_N_O<1> VDD VSS / RSC_IHPSG13_CINVX8 +XDRV<0> qn_int<0> ADDR_N_O<0> VDD VSS / RSC_IHPSG13_CINVX8 +XDFF<5> BIST_EN_I BIST_ADDR_I<5> ACLK_N_I ADDR_I<5> q_int<5> net2<0> VDD ++ VSS / RSC_IHPSG13_DFNQMX2IX1 +XDFF<4> BIST_EN_I BIST_ADDR_I<4> ACLK_N_I ADDR_I<4> q_int<4> net2<1> VDD ++ VSS / RSC_IHPSG13_DFNQMX2IX1 +XDFF<3> BIST_EN_I BIST_ADDR_I<3> ACLK_N_I ADDR_I<3> q_int<3> net2<2> VDD ++ VSS / RSC_IHPSG13_DFNQMX2IX1 +XDFF<2> BIST_EN_I BIST_ADDR_I<2> ACLK_N_I ADDR_I<2> q_int<2> net2<3> VDD ++ VSS / RSC_IHPSG13_DFNQMX2IX1 +XDFF<1> BIST_EN_I BIST_ADDR_I<1> ACLK_N_I ADDR_I<1> q_int<1> net2<4> VDD ++ VSS / RSC_IHPSG13_DFNQMX2IX1 +XDFF<0> BIST_EN_I BIST_ADDR_I<0> ACLK_N_I ADDR_I<0> q_int<0> net2<5> VDD ++ VSS / RSC_IHPSG13_DFNQMX2IX1 +XI11<12> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI11<11> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI11<10> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI11<9> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI11<8> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI11<7> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI11<6> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI11<5> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI11<4> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI11<3> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI11<2> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI11<1> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI12<2> VDD VSS / RSC_IHPSG13_FILLCAP4 +XI12<1> VDD VSS / RSC_IHPSG13_FILLCAP4 +XI12<0> VDD VSS / RSC_IHPSG13_FILLCAP4 +.ENDS + +.SUBCKT RM_IHPSG13_1024x32_c2_2P_COLDRV13X16 ADDR_COL_I<1> ADDR_COL_I<0> ADDR_COL_O<1> ++ ADDR_COL_O<0> ADDR_DEC_I<7> ADDR_DEC_I<6> ADDR_DEC_I<5> ADDR_DEC_I<4> ++ ADDR_DEC_I<3> ADDR_DEC_I<2> ADDR_DEC_I<1> ADDR_DEC_I<0> ADDR_DEC_O<7> ++ ADDR_DEC_O<6> ADDR_DEC_O<5> ADDR_DEC_O<4> ADDR_DEC_O<3> ADDR_DEC_O<2> ++ ADDR_DEC_O<1> ADDR_DEC_O<0> DCLK_I DCLK_O RCLK_I RCLK_O WCLK_I WCLK_O ++ VDD VSS +XI0<7> VDD VSS / RSC_IHPSG13_FILLCAP4 +XI0<6> VDD VSS / RSC_IHPSG13_FILLCAP4 +XI0<5> VDD VSS / RSC_IHPSG13_FILLCAP4 +XI0<4> VDD VSS / RSC_IHPSG13_FILLCAP4 +XI0<3> VDD VSS / RSC_IHPSG13_FILLCAP4 +XI0<2> VDD VSS / RSC_IHPSG13_FILLCAP4 +XI0<1> VDD VSS / RSC_IHPSG13_FILLCAP4 +XWCLK_DRV WCLK_I WCLK_O VDD VSS / RSC_IHPSG13_CBUFX16 +XRCLK_DRV RCLK_I RCLK_O VDD VSS / RSC_IHPSG13_CBUFX16 +XDCLK_DRV DCLK_I DCLK_O VDD VSS / RSC_IHPSG13_CBUFX16 +XADDR_COL_DRV<1> ADDR_COL_I<1> ADDR_COL_O<1> VDD VSS / ++ RSC_IHPSG13_CBUFX16 +XADDR_COL_DRV<0> ADDR_COL_I<0> ADDR_COL_O<0> VDD VSS / ++ RSC_IHPSG13_CBUFX16 +XADDR_DEC_DRV<7> ADDR_DEC_I<7> ADDR_DEC_O<7> VDD VSS / ++ RSC_IHPSG13_CBUFX16 +XADDR_DEC_DRV<6> ADDR_DEC_I<6> ADDR_DEC_O<6> VDD VSS / ++ RSC_IHPSG13_CBUFX16 +XADDR_DEC_DRV<5> ADDR_DEC_I<5> ADDR_DEC_O<5> VDD VSS / ++ RSC_IHPSG13_CBUFX16 +XADDR_DEC_DRV<4> ADDR_DEC_I<4> ADDR_DEC_O<4> VDD VSS / ++ RSC_IHPSG13_CBUFX16 +XADDR_DEC_DRV<3> ADDR_DEC_I<3> ADDR_DEC_O<3> VDD VSS / ++ RSC_IHPSG13_CBUFX16 +XADDR_DEC_DRV<2> ADDR_DEC_I<2> ADDR_DEC_O<2> VDD VSS / ++ RSC_IHPSG13_CBUFX16 +XADDR_DEC_DRV<1> ADDR_DEC_I<1> ADDR_DEC_O<1> VDD VSS / ++ RSC_IHPSG13_CBUFX16 +XADDR_DEC_DRV<0> ADDR_DEC_I<0> ADDR_DEC_O<0> VDD VSS / ++ RSC_IHPSG13_CBUFX16 +XI1<5> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI1<4> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI1<3> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI1<2> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI1<1> VDD VSS / RSC_IHPSG13_FILLCAP8 +.ENDS +.SUBCKT RM_IHPSG13_1024x32_c2_2P_WLDRV16X16 A<15> A<14> A<13> A<12> A<11> A<10> A<9> A<8> ++ A<7> A<6> A<5> A<4> A<3> A<2> A<1> A<0> Z<15> Z<14> Z<13> Z<12> Z<11> Z<10> ++ Z<9> Z<8> Z<7> Z<6> Z<5> Z<4> Z<3> Z<2> Z<1> Z<0> VDD VSS +XBUF<15> A<15> Z<15> VDD VSS / RSC_IHPSG13_WLDRVX16 +XBUF<14> A<14> Z<14> VDD VSS / RSC_IHPSG13_WLDRVX16 +XBUF<13> A<13> Z<13> VDD VSS / RSC_IHPSG13_WLDRVX16 +XBUF<12> A<12> Z<12> VDD VSS / RSC_IHPSG13_WLDRVX16 +XBUF<11> A<11> Z<11> VDD VSS / RSC_IHPSG13_WLDRVX16 +XBUF<10> A<10> Z<10> VDD VSS / RSC_IHPSG13_WLDRVX16 +XBUF<9> A<9> Z<9> VDD VSS / RSC_IHPSG13_WLDRVX16 +XBUF<8> A<8> Z<8> VDD VSS / RSC_IHPSG13_WLDRVX16 +XBUF<7> A<7> Z<7> VDD VSS / RSC_IHPSG13_WLDRVX16 +XBUF<6> A<6> Z<6> VDD VSS / RSC_IHPSG13_WLDRVX16 +XBUF<5> A<5> Z<5> VDD VSS / RSC_IHPSG13_WLDRVX16 +XBUF<4> A<4> Z<4> VDD VSS / RSC_IHPSG13_WLDRVX16 +XBUF<3> A<3> Z<3> VDD VSS / RSC_IHPSG13_WLDRVX16 +XBUF<2> A<2> Z<2> VDD VSS / RSC_IHPSG13_WLDRVX16 +XBUF<1> A<1> Z<1> VDD VSS / RSC_IHPSG13_WLDRVX16 +XBUF<0> A<0> Z<0> VDD VSS / RSC_IHPSG13_WLDRVX16 +.ENDS + + +.SUBCKT RM_IHPSG13_1024x32_c2_1P_DEC01 ADDR<1> ADDR<0> CS CS_OUT VDD VSS +XDECINV net1 CS_OUT VDD VSS / RSC_IHPSG13_INVX4 +XDEC NADDR<1> ADDR<0> CS net1 VDD VSS / RSC_IHPSG13_NAND3X2 +XI2 VDD VSS / RSC_IHPSG13_FILLCAP4 +XADDRINV ADDR<1> NADDR<1> VDD VSS / RSC_IHPSG13_INVX2 +.ENDS +.SUBCKT RM_IHPSG13_1024x32_c2_1P_DEC00 ADDR<1> ADDR<0> CS CS_OUT VDD VSS +XDECINV net1 CS_OUT VDD VSS / RSC_IHPSG13_INVX4 +XDEC NADDR<1> NADDR<0> CS net1 VDD VSS / RSC_IHPSG13_NAND3X2 +XADDRINV<1> ADDR<1> NADDR<1> VDD VSS / RSC_IHPSG13_INVX2 +XADDRINV<0> ADDR<0> NADDR<0> VDD VSS / RSC_IHPSG13_INVX2 +XI1 VDD VSS / RSC_IHPSG13_FILLCAP4 +.ENDS +.SUBCKT RM_IHPSG13_1024x32_c2_1P_ROWDEC5 ADDR_N_I<4> ADDR_N_I<3> ADDR_N_I<2> ADDR_N_I<1> ++ ADDR_N_I<0> CS_I ECLK_I WL_O<31> WL_O<30> WL_O<29> WL_O<28> WL_O<27> ++ WL_O<26> WL_O<25> WL_O<24> WL_O<23> WL_O<22> WL_O<21> WL_O<20> WL_O<19> ++ WL_O<18> WL_O<17> WL_O<16> WL_O<15> WL_O<14> WL_O<13> WL_O<12> WL_O<11> ++ WL_O<10> WL_O<9> WL_O<8> WL_O<7> WL_O<6> WL_O<5> WL_O<4> WL_O<3> WL_O<2> ++ WL_O<1> WL_O<0> VDD VSS +XL2<12> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<11> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<10> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<9> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<8> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<7> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<6> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<5> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<4> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<3> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<2> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<1> VDD VSS / RSC_IHPSG13_FILLCAP8 +XDEC01 ADDR_N_I<5> ADDR_N_I<4> CS_I CS00<1> VDD VSS / ++ RM_IHPSG13_1024x32_c2_1P_DEC01 +XDEC00 ADDR_N_I<5> ADDR_N_I<4> CS_I CS00<0> VDD VSS / ++ RM_IHPSG13_1024x32_c2_1P_DEC00 +XSEL<1> ADDR_N_I<3> ADDR_N_I<2> ADDR_N_I<1> ADDR_N_I<0> CS00<1> ECLK_H<1> ++ ECLK_H<2> ECLK_B<1> ECLK_B<2> WL_O<31> WL_O<30> WL_O<29> WL_O<28> WL_O<27> ++ WL_O<26> WL_O<25> WL_O<24> WL_O<23> WL_O<22> WL_O<21> WL_O<20> WL_O<19> ++ WL_O<18> WL_O<17> WL_O<16> VDD VSS / RM_IHPSG13_1024x32_c2_1P_DEC04 +XSEL<0> ADDR_N_I<3> ADDR_N_I<2> ADDR_N_I<1> ADDR_N_I<0> CS00<0> ECLK_I ++ ECLK_H<1> ECLK_B<0> ECLK_B<1> WL_O<15> WL_O<14> WL_O<13> WL_O<12> WL_O<11> ++ WL_O<10> WL_O<9> WL_O<8> WL_O<7> WL_O<6> WL_O<5> WL_O<4> WL_O<3> WL_O<2> ++ WL_O<1> WL_O<0> VDD VSS / RM_IHPSG13_1024x32_c2_1P_DEC04 +XI0 ADDR_N_I<5> VDD VSS / RSC_IHPSG13_TIEL +.ENDS +.SUBCKT RM_IHPSG13_1024x32_c2_1P_ROWREG5 ACLK_N_I ADDR_I<4> ADDR_I<3> ADDR_I<2> ADDR_I<1> ++ ADDR_I<0> ADDR_N_O<4> ADDR_N_O<3> ADDR_N_O<2> ADDR_N_O<1> ADDR_N_O<0> ++ BIST_ADDR_I<4> BIST_ADDR_I<3> BIST_ADDR_I<2> BIST_ADDR_I<1> BIST_ADDR_I<0> ++ BIST_EN_I VDD VSS +XINV<4> q_int<4> qn_int<4> VDD VSS / RSC_IHPSG13_CINVX2 +XINV<3> q_int<3> qn_int<3> VDD VSS / RSC_IHPSG13_CINVX2 +XINV<2> q_int<2> qn_int<2> VDD VSS / RSC_IHPSG13_CINVX2 +XINV<1> q_int<1> qn_int<1> VDD VSS / RSC_IHPSG13_CINVX2 +XINV<0> q_int<0> qn_int<0> VDD VSS / RSC_IHPSG13_CINVX2 +XDRV<4> qn_int<4> ADDR_N_O<4> VDD VSS / RSC_IHPSG13_CINVX8 +XDRV<3> qn_int<3> ADDR_N_O<3> VDD VSS / RSC_IHPSG13_CINVX8 +XDRV<2> qn_int<2> ADDR_N_O<2> VDD VSS / RSC_IHPSG13_CINVX8 +XDRV<1> qn_int<1> ADDR_N_O<1> VDD VSS / RSC_IHPSG13_CINVX8 +XDRV<0> qn_int<0> ADDR_N_O<0> VDD VSS / RSC_IHPSG13_CINVX8 +XDFF<4> BIST_EN_I BIST_ADDR_I<4> ACLK_N_I ADDR_I<4> q_int<4> net2<0> VDD ++ VSS / RSC_IHPSG13_DFNQMX2IX1 +XDFF<3> BIST_EN_I BIST_ADDR_I<3> ACLK_N_I ADDR_I<3> q_int<3> net2<1> VDD ++ VSS / RSC_IHPSG13_DFNQMX2IX1 +XDFF<2> BIST_EN_I BIST_ADDR_I<2> ACLK_N_I ADDR_I<2> q_int<2> net2<2> VDD ++ VSS / RSC_IHPSG13_DFNQMX2IX1 +XDFF<1> BIST_EN_I BIST_ADDR_I<1> ACLK_N_I ADDR_I<1> q_int<1> net2<3> VDD ++ VSS / RSC_IHPSG13_DFNQMX2IX1 +XDFF<0> BIST_EN_I BIST_ADDR_I<0> ACLK_N_I ADDR_I<0> q_int<0> net2<4> VDD ++ VSS / RSC_IHPSG13_DFNQMX2IX1 +XI11<16> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI11<15> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI11<14> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI11<13> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI11<12> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI11<11> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI11<10> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI11<9> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI11<8> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI11<7> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI11<6> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI11<5> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI11<4> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI11<3> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI11<2> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI11<1> VDD VSS / RSC_IHPSG13_FILLCAP8 +.ENDS + + +.SUBCKT RM_IHPSG13_1024x32_c2_1P_COLDEC5 ACLK_N ADDR<4> ADDR<3> ADDR<2> ADDR<1> ADDR<0> ++ ADDR_COL<1> ADDR_COL<0> ADDR_DEC<7> ADDR_DEC<6> ADDR_DEC<5> ADDR_DEC<4> ++ ADDR_DEC<3> ADDR_DEC<2> ADDR_DEC<1> ADDR_DEC<0> BIST_ADDR<4> BIST_ADDR<3> ++ BIST_ADDR<2> BIST_ADDR<1> BIST_ADDR<0> BIST_EN_I VDD VSS +XI17<2> VDD VSS / RSC_IHPSG13_FILLCAP4 +XI17<1> VDD VSS / RSC_IHPSG13_FILLCAP4 +XI13<1> addr_int<1> ADDR_COL<1> VDD VSS / RSC_IHPSG13_CBUFX2 +XI13<0> addr_int<0> ADDR_COL<0> VDD VSS / RSC_IHPSG13_CBUFX2 +XDFF<4> BIST_EN_I BIST_ADDR<4> ACLK_N ADDR<4> addr_int<1> net7<0> VDD ++ VSS / RSC_IHPSG13_DFNQMX2IX1 +XDFF<3> BIST_EN_I BIST_ADDR<3> ACLK_N ADDR<3> addr_int<0> net7<1> VDD ++ VSS / RSC_IHPSG13_DFNQMX2IX1 +XDFF<2> BIST_EN_I BIST_ADDR<2> ACLK_N ADDR<2> padr_int<2> net7<2> VDD ++ VSS / RSC_IHPSG13_DFNQMX2IX1 +XDFF<1> BIST_EN_I BIST_ADDR<1> ACLK_N ADDR<1> padr_int<1> net7<3> VDD ++ VSS / RSC_IHPSG13_DFNQMX2IX1 +XDFF<0> BIST_EN_I BIST_ADDR<0> ACLK_N ADDR<0> padr_int<0> net7<4> VDD ++ VSS / RSC_IHPSG13_DFNQMX2IX1 +XI1<7> PADR<0> PADR<1> PADR<2> addr_n<7> VDD VSS / RSC_IHPSG13_NAND3X2 +XI1<6> NADR<0> PADR<1> PADR<2> addr_n<6> VDD VSS / RSC_IHPSG13_NAND3X2 +XI1<5> PADR<0> NADR<1> PADR<2> addr_n<5> VDD VSS / RSC_IHPSG13_NAND3X2 +XI1<4> NADR<0> NADR<1> PADR<2> addr_n<4> VDD VSS / RSC_IHPSG13_NAND3X2 +XI1<3> PADR<0> PADR<1> NADR<2> addr_n<3> VDD VSS / RSC_IHPSG13_NAND3X2 +XI1<2> NADR<0> PADR<1> NADR<2> addr_n<2> VDD VSS / RSC_IHPSG13_NAND3X2 +XI1<1> PADR<0> NADR<1> NADR<2> addr_n<1> VDD VSS / RSC_IHPSG13_NAND3X2 +XI1<0> NADR<0> NADR<1> NADR<2> addr_n<0> VDD VSS / RSC_IHPSG13_NAND3X2 +XI15<2> NADR<2> PADR<2> VDD VSS / RSC_IHPSG13_INVX2 +XI15<1> NADR<1> PADR<1> VDD VSS / RSC_IHPSG13_INVX2 +XI15<0> NADR<0> PADR<0> VDD VSS / RSC_IHPSG13_INVX2 +XI3<2> padr_int<2> NADR<2> VDD VSS / RSC_IHPSG13_INVX2 +XI3<1> padr_int<1> NADR<1> VDD VSS / RSC_IHPSG13_INVX2 +XI3<0> padr_int<0> NADR<0> VDD VSS / RSC_IHPSG13_INVX2 +XI2<7> addr_n<7> ADDR_DEC<7> VDD VSS / RSC_IHPSG13_INVX2 +XI2<6> addr_n<6> ADDR_DEC<6> VDD VSS / RSC_IHPSG13_INVX2 +XI2<5> addr_n<5> ADDR_DEC<5> VDD VSS / RSC_IHPSG13_INVX2 +XI2<4> addr_n<4> ADDR_DEC<4> VDD VSS / RSC_IHPSG13_INVX2 +XI2<3> addr_n<3> ADDR_DEC<3> VDD VSS / RSC_IHPSG13_INVX2 +XI2<2> addr_n<2> ADDR_DEC<2> VDD VSS / RSC_IHPSG13_INVX2 +XI2<1> addr_n<1> ADDR_DEC<1> VDD VSS / RSC_IHPSG13_INVX2 +XI2<0> addr_n<0> ADDR_DEC<0> VDD VSS / RSC_IHPSG13_INVX2 +.ENDS +.SUBCKT RM_IHPSG13_1024x32_c2_1P_COLCTRL5 A_ADDR_COL<1> A_ADDR_COL<0> A_ADDR_DEC<7> ++ A_ADDR_DEC<6> A_ADDR_DEC<5> A_ADDR_DEC<4> A_ADDR_DEC<3> A_ADDR_DEC<2> ++ A_ADDR_DEC<1> A_ADDR_DEC<0> A_BIST_BM_I A_BIST_DW_I A_BIST_EN_I A_BLC<31> ++ A_BLC<30> A_BLC<29> A_BLC<28> A_BLC<27> A_BLC<26> A_BLC<25> A_BLC<24> ++ A_BLC<23> A_BLC<22> A_BLC<21> A_BLC<20> A_BLC<19> A_BLC<18> A_BLC<17> ++ A_BLC<16> A_BLC<15> A_BLC<14> A_BLC<13> A_BLC<12> A_BLC<11> A_BLC<10> ++ A_BLC<9> A_BLC<8> A_BLC<7> A_BLC<6> A_BLC<5> A_BLC<4> A_BLC<3> A_BLC<2> ++ A_BLC<1> A_BLC<0> A_BLT<31> A_BLT<30> A_BLT<29> A_BLT<28> A_BLT<27> ++ A_BLT<26> A_BLT<25> A_BLT<24> A_BLT<23> A_BLT<22> A_BLT<21> A_BLT<20> ++ A_BLT<19> A_BLT<18> A_BLT<17> A_BLT<16> A_BLT<15> A_BLT<14> A_BLT<13> ++ A_BLT<12> A_BLT<11> A_BLT<10> A_BLT<9> A_BLT<8> A_BLT<7> A_BLT<6> A_BLT<5> ++ A_BLT<4> A_BLT<3> A_BLT<2> A_BLT<1> A_BLT<0> A_BM_I A_DCLK_B_L A_DCLK_B_R ++ A_DCLK_L A_DCLK_R A_DR_O A_DW_I A_RCLK_B_L A_RCLK_B_R A_RCLK_L A_RCLK_R ++ A_TIEH_O A_WCLK_B_L A_WCLK_B_R A_WCLK_L A_WCLK_R VDD VSS +XA_I80<1> A_WCLK_B_L A_RCLK_B_L A_W_nor_R<1> VDD VSS / ++ RSC_IHPSG13_AND2X2 +XA_I80<0> A_WCLK_B_L A_RCLK_B_L A_W_nor_R<0> VDD VSS / ++ RSC_IHPSG13_AND2X2 +XA_I44 A_BM_N A_WCLK_B_L A_DO_WRITE_P VDD VSS / RSC_IHPSG13_NOR2X2 +XI80<29> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI80<28> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI80<27> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI80<26> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI80<25> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI80<24> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI80<23> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI80<22> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI80<21> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI80<20> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI80<19> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI80<18> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI80<17> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI80<16> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI80<15> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI80<14> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI80<13> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI80<12> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI80<11> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI80<10> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI80<9> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI80<8> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI80<7> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI80<6> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI80<5> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI80<4> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI80<3> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI80<2> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI80<1> VDD VSS / RSC_IHPSG13_FILLCAP8 +XA_I74<16> VDD VSS / RSC_IHPSG13_FILLCAP8 +XA_I74<15> VDD VSS / RSC_IHPSG13_FILLCAP8 +XA_I74<14> VDD VSS / RSC_IHPSG13_FILLCAP8 +XA_I74<13> VDD VSS / RSC_IHPSG13_FILLCAP8 +XA_I74<12> VDD VSS / RSC_IHPSG13_FILLCAP8 +XA_I74<11> VDD VSS / RSC_IHPSG13_FILLCAP8 +XA_I74<10> VDD VSS / RSC_IHPSG13_FILLCAP8 +XA_I74<9> VDD VSS / RSC_IHPSG13_FILLCAP8 +XA_I74<8> VDD VSS / RSC_IHPSG13_FILLCAP8 +XA_I74<7> VDD VSS / RSC_IHPSG13_FILLCAP8 +XA_I74<6> VDD VSS / RSC_IHPSG13_FILLCAP8 +XA_I74<5> VDD VSS / RSC_IHPSG13_FILLCAP8 +XA_I74<4> VDD VSS / RSC_IHPSG13_FILLCAP8 +XA_I74<3> VDD VSS / RSC_IHPSG13_FILLCAP8 +XA_I74<2> VDD VSS / RSC_IHPSG13_FILLCAP8 +XA_I74<1> VDD VSS / RSC_IHPSG13_FILLCAP8 +XA_INV<6> A_N1<1> A_P1<1> VDD VSS / RSC_IHPSG13_CINVX4 +XA_INV<5> A_N0<1> A_P0<1> VDD VSS / RSC_IHPSG13_CINVX4 +XA_INV<4> A_N0<0> A_P0<0> VDD VSS / RSC_IHPSG13_CINVX4 +XA_INV<3> A_ADDR_COL<1> A_N1<1> VDD VSS / RSC_IHPSG13_CINVX4 +XA_INV<2> A_ADDR_COL<1> A_N1<0> VDD VSS / RSC_IHPSG13_CINVX4 +XA_INV<1> A_ADDR_COL<0> A_N0<1> VDD VSS / RSC_IHPSG13_CINVX4 +XA_INV<0> A_ADDR_COL<0> A_N0<0> VDD VSS / RSC_IHPSG13_CINVX4 +XA_I81<3> A_W_nor_R<1> A_PRE_N VDD VSS / RSC_IHPSG13_CINVX4_WN +XA_I81<2> A_W_nor_R<1> A_PRE_N VDD VSS / RSC_IHPSG13_CINVX4_WN +XA_I81<1> A_W_nor_R<0> A_PRE_N VDD VSS / RSC_IHPSG13_CINVX4_WN +XA_I81<0> A_W_nor_R<0> A_PRE_N VDD VSS / RSC_IHPSG13_CINVX4_WN +XA_BLTMUX<31> A_BLC<31> A_BLC_SEL A_BLT<31> A_BLT_SEL A_PRE_N A_SEL_P<31> ++ A_WR_ONE A_WR_ZERO VDD VSS / RM_IHPSG13_1024x32_c2_1P_BLDRV +XA_BLTMUX<30> A_BLC<30> A_BLC_SEL A_BLT<30> A_BLT_SEL A_PRE_N A_SEL_P<30> ++ A_WR_ONE A_WR_ZERO VDD VSS / RM_IHPSG13_1024x32_c2_1P_BLDRV +XA_BLTMUX<29> A_BLC<29> A_BLC_SEL A_BLT<29> A_BLT_SEL A_PRE_N A_SEL_P<29> ++ A_WR_ONE A_WR_ZERO VDD VSS / RM_IHPSG13_1024x32_c2_1P_BLDRV +XA_BLTMUX<28> A_BLC<28> A_BLC_SEL A_BLT<28> A_BLT_SEL A_PRE_N A_SEL_P<28> ++ A_WR_ONE A_WR_ZERO VDD VSS / RM_IHPSG13_1024x32_c2_1P_BLDRV +XA_BLTMUX<27> A_BLC<27> A_BLC_SEL A_BLT<27> A_BLT_SEL A_PRE_N A_SEL_P<27> ++ A_WR_ONE A_WR_ZERO VDD VSS / RM_IHPSG13_1024x32_c2_1P_BLDRV +XA_BLTMUX<26> A_BLC<26> A_BLC_SEL A_BLT<26> A_BLT_SEL A_PRE_N A_SEL_P<26> ++ A_WR_ONE A_WR_ZERO VDD VSS / RM_IHPSG13_1024x32_c2_1P_BLDRV +XA_BLTMUX<25> A_BLC<25> A_BLC_SEL A_BLT<25> A_BLT_SEL A_PRE_N A_SEL_P<25> ++ A_WR_ONE A_WR_ZERO VDD VSS / RM_IHPSG13_1024x32_c2_1P_BLDRV +XA_BLTMUX<24> A_BLC<24> A_BLC_SEL A_BLT<24> A_BLT_SEL A_PRE_N A_SEL_P<24> ++ A_WR_ONE A_WR_ZERO VDD VSS / RM_IHPSG13_1024x32_c2_1P_BLDRV +XA_BLTMUX<23> A_BLC<23> A_BLC_SEL A_BLT<23> A_BLT_SEL A_PRE_N A_SEL_P<23> ++ A_WR_ONE A_WR_ZERO VDD VSS / RM_IHPSG13_1024x32_c2_1P_BLDRV +XA_BLTMUX<22> A_BLC<22> A_BLC_SEL A_BLT<22> A_BLT_SEL A_PRE_N A_SEL_P<22> ++ A_WR_ONE A_WR_ZERO VDD VSS / RM_IHPSG13_1024x32_c2_1P_BLDRV +XA_BLTMUX<21> A_BLC<21> A_BLC_SEL A_BLT<21> A_BLT_SEL A_PRE_N A_SEL_P<21> ++ A_WR_ONE A_WR_ZERO VDD VSS / RM_IHPSG13_1024x32_c2_1P_BLDRV +XA_BLTMUX<20> A_BLC<20> A_BLC_SEL A_BLT<20> A_BLT_SEL A_PRE_N A_SEL_P<20> ++ A_WR_ONE A_WR_ZERO VDD VSS / RM_IHPSG13_1024x32_c2_1P_BLDRV +XA_BLTMUX<19> A_BLC<19> A_BLC_SEL A_BLT<19> A_BLT_SEL A_PRE_N A_SEL_P<19> ++ A_WR_ONE A_WR_ZERO VDD VSS / RM_IHPSG13_1024x32_c2_1P_BLDRV +XA_BLTMUX<18> A_BLC<18> A_BLC_SEL A_BLT<18> A_BLT_SEL A_PRE_N A_SEL_P<18> ++ A_WR_ONE A_WR_ZERO VDD VSS / RM_IHPSG13_1024x32_c2_1P_BLDRV +XA_BLTMUX<17> A_BLC<17> A_BLC_SEL A_BLT<17> A_BLT_SEL A_PRE_N A_SEL_P<17> ++ A_WR_ONE A_WR_ZERO VDD VSS / RM_IHPSG13_1024x32_c2_1P_BLDRV +XA_BLTMUX<16> A_BLC<16> A_BLC_SEL A_BLT<16> A_BLT_SEL A_PRE_N A_SEL_P<16> ++ A_WR_ONE A_WR_ZERO VDD VSS / RM_IHPSG13_1024x32_c2_1P_BLDRV +XA_BLTMUX<15> A_BLC<15> A_BLC_SEL A_BLT<15> A_BLT_SEL A_PRE_N A_SEL_P<15> ++ A_WR_ONE A_WR_ZERO VDD VSS / RM_IHPSG13_1024x32_c2_1P_BLDRV +XA_BLTMUX<14> A_BLC<14> A_BLC_SEL A_BLT<14> A_BLT_SEL A_PRE_N A_SEL_P<14> ++ A_WR_ONE A_WR_ZERO VDD VSS / RM_IHPSG13_1024x32_c2_1P_BLDRV +XA_BLTMUX<13> A_BLC<13> A_BLC_SEL A_BLT<13> A_BLT_SEL A_PRE_N A_SEL_P<13> ++ A_WR_ONE A_WR_ZERO VDD VSS / RM_IHPSG13_1024x32_c2_1P_BLDRV +XA_BLTMUX<12> A_BLC<12> A_BLC_SEL A_BLT<12> A_BLT_SEL A_PRE_N A_SEL_P<12> ++ A_WR_ONE A_WR_ZERO VDD VSS / RM_IHPSG13_1024x32_c2_1P_BLDRV +XA_BLTMUX<11> A_BLC<11> A_BLC_SEL A_BLT<11> A_BLT_SEL A_PRE_N A_SEL_P<11> ++ A_WR_ONE A_WR_ZERO VDD VSS / RM_IHPSG13_1024x32_c2_1P_BLDRV +XA_BLTMUX<10> A_BLC<10> A_BLC_SEL A_BLT<10> A_BLT_SEL A_PRE_N A_SEL_P<10> ++ A_WR_ONE A_WR_ZERO VDD VSS / RM_IHPSG13_1024x32_c2_1P_BLDRV +XA_BLTMUX<9> A_BLC<9> A_BLC_SEL A_BLT<9> A_BLT_SEL A_PRE_N A_SEL_P<9> A_WR_ONE ++ A_WR_ZERO VDD VSS / RM_IHPSG13_1024x32_c2_1P_BLDRV +XA_BLTMUX<8> A_BLC<8> A_BLC_SEL A_BLT<8> A_BLT_SEL A_PRE_N A_SEL_P<8> A_WR_ONE ++ A_WR_ZERO VDD VSS / RM_IHPSG13_1024x32_c2_1P_BLDRV +XA_BLTMUX<7> A_BLC<7> A_BLC_SEL A_BLT<7> A_BLT_SEL A_PRE_N A_SEL_P<7> A_WR_ONE ++ A_WR_ZERO VDD VSS / RM_IHPSG13_1024x32_c2_1P_BLDRV +XA_BLTMUX<6> A_BLC<6> A_BLC_SEL A_BLT<6> A_BLT_SEL A_PRE_N A_SEL_P<6> A_WR_ONE ++ A_WR_ZERO VDD VSS / RM_IHPSG13_1024x32_c2_1P_BLDRV +XA_BLTMUX<5> A_BLC<5> A_BLC_SEL A_BLT<5> A_BLT_SEL A_PRE_N A_SEL_P<5> A_WR_ONE ++ A_WR_ZERO VDD VSS / RM_IHPSG13_1024x32_c2_1P_BLDRV +XA_BLTMUX<4> A_BLC<4> A_BLC_SEL A_BLT<4> A_BLT_SEL A_PRE_N A_SEL_P<4> A_WR_ONE ++ A_WR_ZERO VDD VSS / RM_IHPSG13_1024x32_c2_1P_BLDRV +XA_BLTMUX<3> A_BLC<3> A_BLC_SEL A_BLT<3> A_BLT_SEL A_PRE_N A_SEL_P<3> A_WR_ONE ++ A_WR_ZERO VDD VSS / RM_IHPSG13_1024x32_c2_1P_BLDRV +XA_BLTMUX<2> A_BLC<2> A_BLC_SEL A_BLT<2> A_BLT_SEL A_PRE_N A_SEL_P<2> A_WR_ONE ++ A_WR_ZERO VDD VSS / RM_IHPSG13_1024x32_c2_1P_BLDRV +XA_BLTMUX<1> A_BLC<1> A_BLC_SEL A_BLT<1> A_BLT_SEL A_PRE_N A_SEL_P<1> A_WR_ONE ++ A_WR_ZERO VDD VSS / RM_IHPSG13_1024x32_c2_1P_BLDRV +XA_BLTMUX<0> A_BLC<0> A_BLC_SEL A_BLT<0> A_BLT_SEL A_PRE_N A_SEL_P<0> A_WR_ONE ++ A_WR_ZERO VDD VSS / RM_IHPSG13_1024x32_c2_1P_BLDRV +XA_CAPS<17> VDD VSS / RSC_IHPSG13_FILLCAP4 +XA_CAPS<16> VDD VSS / RSC_IHPSG13_FILLCAP4 +XA_CAPS<15> VDD VSS / RSC_IHPSG13_FILLCAP4 +XA_CAPS<14> VDD VSS / RSC_IHPSG13_FILLCAP4 +XA_CAPS<13> VDD VSS / RSC_IHPSG13_FILLCAP4 +XA_CAPS<12> VDD VSS / RSC_IHPSG13_FILLCAP4 +XA_CAPS<11> VDD VSS / RSC_IHPSG13_FILLCAP4 +XA_CAPS<10> VDD VSS / RSC_IHPSG13_FILLCAP4 +XA_CAPS<9> VDD VSS / RSC_IHPSG13_FILLCAP4 +XA_CAPS<8> VDD VSS / RSC_IHPSG13_FILLCAP4 +XA_CAPS<7> VDD VSS / RSC_IHPSG13_FILLCAP4 +XA_CAPS<6> VDD VSS / RSC_IHPSG13_FILLCAP4 +XA_CAPS<5> VDD VSS / RSC_IHPSG13_FILLCAP4 +XA_CAPS<4> VDD VSS / RSC_IHPSG13_FILLCAP4 +XA_CAPS<3> VDD VSS / RSC_IHPSG13_FILLCAP4 +XA_CAPS<2> VDD VSS / RSC_IHPSG13_FILLCAP4 +XA_CAPS<1> VDD VSS / RSC_IHPSG13_FILLCAP4 +XA_I51 net19 A_DR_O VDD VSS / RSC_IHPSG13_INVX4 +XA_I78 A_RCLK_B_L A_SAE VDD VSS / RSC_IHPSG13_CBUFX2 +XA_I69 A_DCLK_L A_DCLK_B_L VDD VSS / RSC_IHPSG13_CINVX8 +XA_I50 A_WCLK_L A_WCLK_B_L VDD VSS / RSC_IHPSG13_CINVX8 +XA_EBUF A_RCLK_L A_RCLK_B_L VDD VSS / RSC_IHPSG13_CINVX8 +XA_I76 A_DI_N A_DO_WRITE_P A_WR_ZERO VDD VSS / RSC_IHPSG13_AND2X6 +XA_I75 A_DI_R A_DO_WRITE_P A_WR_ONE VDD VSS / RSC_IHPSG13_AND2X6 +XA_I83 A_BM_R A_BM_N VDD VSS / RSC_IHPSG13_INVX2 +XA_DEC3INV<31> net23<0> A_SEL_P<31> VDD VSS / RSC_IHPSG13_INVX2 +XA_DEC3INV<30> net23<1> A_SEL_P<30> VDD VSS / RSC_IHPSG13_INVX2 +XA_DEC3INV<29> net23<2> A_SEL_P<29> VDD VSS / RSC_IHPSG13_INVX2 +XA_DEC3INV<28> net23<3> A_SEL_P<28> VDD VSS / RSC_IHPSG13_INVX2 +XA_DEC3INV<27> net23<4> A_SEL_P<27> VDD VSS / RSC_IHPSG13_INVX2 +XA_DEC3INV<26> net23<5> A_SEL_P<26> VDD VSS / RSC_IHPSG13_INVX2 +XA_DEC3INV<25> net23<6> A_SEL_P<25> VDD VSS / RSC_IHPSG13_INVX2 +XA_DEC3INV<24> net23<7> A_SEL_P<24> VDD VSS / RSC_IHPSG13_INVX2 +XA_DEC3INV<23> net23<8> A_SEL_P<23> VDD VSS / RSC_IHPSG13_INVX2 +XA_DEC3INV<22> net23<9> A_SEL_P<22> VDD VSS / RSC_IHPSG13_INVX2 +XA_DEC3INV<21> net23<10> A_SEL_P<21> VDD VSS / RSC_IHPSG13_INVX2 +XA_DEC3INV<20> net23<11> A_SEL_P<20> VDD VSS / RSC_IHPSG13_INVX2 +XA_DEC3INV<19> net23<12> A_SEL_P<19> VDD VSS / RSC_IHPSG13_INVX2 +XA_DEC3INV<18> net23<13> A_SEL_P<18> VDD VSS / RSC_IHPSG13_INVX2 +XA_DEC3INV<17> net23<14> A_SEL_P<17> VDD VSS / RSC_IHPSG13_INVX2 +XA_DEC3INV<16> net23<15> A_SEL_P<16> VDD VSS / RSC_IHPSG13_INVX2 +XA_DEC3INV<15> net23<16> A_SEL_P<15> VDD VSS / RSC_IHPSG13_INVX2 +XA_DEC3INV<14> net23<17> A_SEL_P<14> VDD VSS / RSC_IHPSG13_INVX2 +XA_DEC3INV<13> net23<18> A_SEL_P<13> VDD VSS / RSC_IHPSG13_INVX2 +XA_DEC3INV<12> net23<19> A_SEL_P<12> VDD VSS / RSC_IHPSG13_INVX2 +XA_DEC3INV<11> net23<20> A_SEL_P<11> VDD VSS / RSC_IHPSG13_INVX2 +XA_DEC3INV<10> net23<21> A_SEL_P<10> VDD VSS / RSC_IHPSG13_INVX2 +XA_DEC3INV<9> net23<22> A_SEL_P<9> VDD VSS / RSC_IHPSG13_INVX2 +XA_DEC3INV<8> net23<23> A_SEL_P<8> VDD VSS / RSC_IHPSG13_INVX2 +XA_DEC3INV<7> net23<24> A_SEL_P<7> VDD VSS / RSC_IHPSG13_INVX2 +XA_DEC3INV<6> net23<25> A_SEL_P<6> VDD VSS / RSC_IHPSG13_INVX2 +XA_DEC3INV<5> net23<26> A_SEL_P<5> VDD VSS / RSC_IHPSG13_INVX2 +XA_DEC3INV<4> net23<27> A_SEL_P<4> VDD VSS / RSC_IHPSG13_INVX2 +XA_DEC3INV<3> net23<28> A_SEL_P<3> VDD VSS / RSC_IHPSG13_INVX2 +XA_DEC3INV<2> net23<29> A_SEL_P<2> VDD VSS / RSC_IHPSG13_INVX2 +XA_DEC3INV<1> net23<30> A_SEL_P<1> VDD VSS / RSC_IHPSG13_INVX2 +XA_DEC3INV<0> net23<31> A_SEL_P<0> VDD VSS / RSC_IHPSG13_INVX2 +XA_I49 A_DI_R A_DI_N VDD VSS / RSC_IHPSG13_INVX2 +XA_ISENSE A_SAE A_BLC_SEL A_BLT_SEL net19 net20 VDD VSS / ++ RSC_IHPSG13_DFPQD_MSAFFX2 +XA_DREG A_BIST_EN_I A_BIST_DW_I A_DCLK_B_L A_DW_I A_DI_R net22 VDD VSS ++ / RSC_IHPSG13_DFNQMX2IX1 +XA_BREG A_BIST_EN_I A_BIST_BM_I A_DCLK_B_L A_BM_I A_BM_R net21 VDD VSS ++ / RSC_IHPSG13_DFNQMX2IX1 +XA_DEC3<31> A_P1<1> A_P0<1> A_ADDR_DEC<7> net23<0> VDD VSS / ++ RSC_IHPSG13_NAND3X2 +XA_DEC3<30> A_P1<1> A_P0<1> A_ADDR_DEC<6> net23<1> VDD VSS / ++ RSC_IHPSG13_NAND3X2 +XA_DEC3<29> A_P1<1> A_P0<1> A_ADDR_DEC<5> net23<2> VDD VSS / ++ RSC_IHPSG13_NAND3X2 +XA_DEC3<28> A_P1<1> A_P0<1> A_ADDR_DEC<4> net23<3> VDD VSS / ++ RSC_IHPSG13_NAND3X2 +XA_DEC3<27> A_P1<1> A_P0<1> A_ADDR_DEC<3> net23<4> VDD VSS / ++ RSC_IHPSG13_NAND3X2 +XA_DEC3<26> A_P1<1> A_P0<1> A_ADDR_DEC<2> net23<5> VDD VSS / ++ RSC_IHPSG13_NAND3X2 +XA_DEC3<25> A_P1<1> A_P0<1> A_ADDR_DEC<1> net23<6> VDD VSS / ++ RSC_IHPSG13_NAND3X2 +XA_DEC3<24> A_P1<1> A_P0<1> A_ADDR_DEC<0> net23<7> VDD VSS / ++ RSC_IHPSG13_NAND3X2 +XA_DEC3<23> A_P1<1> A_N0<1> A_ADDR_DEC<7> net23<8> VDD VSS / ++ RSC_IHPSG13_NAND3X2 +XA_DEC3<22> A_P1<1> A_N0<1> A_ADDR_DEC<6> net23<9> VDD VSS / ++ RSC_IHPSG13_NAND3X2 +XA_DEC3<21> A_P1<1> A_N0<1> A_ADDR_DEC<5> net23<10> VDD VSS / ++ RSC_IHPSG13_NAND3X2 +XA_DEC3<20> A_P1<1> A_N0<1> A_ADDR_DEC<4> net23<11> VDD VSS / ++ RSC_IHPSG13_NAND3X2 +XA_DEC3<19> A_P1<1> A_N0<1> A_ADDR_DEC<3> net23<12> VDD VSS / ++ RSC_IHPSG13_NAND3X2 +XA_DEC3<18> A_P1<1> A_N0<1> A_ADDR_DEC<2> net23<13> VDD VSS / ++ RSC_IHPSG13_NAND3X2 +XA_DEC3<17> A_P1<1> A_N0<1> A_ADDR_DEC<1> net23<14> VDD VSS / ++ RSC_IHPSG13_NAND3X2 +XA_DEC3<16> A_P1<1> A_N0<1> A_ADDR_DEC<0> net23<15> VDD VSS / ++ RSC_IHPSG13_NAND3X2 +XA_DEC3<15> A_N1<0> A_P0<0> A_ADDR_DEC<7> net23<16> VDD VSS / ++ RSC_IHPSG13_NAND3X2 +XA_DEC3<14> A_N1<0> A_P0<0> A_ADDR_DEC<6> net23<17> VDD VSS / ++ RSC_IHPSG13_NAND3X2 +XA_DEC3<13> A_N1<0> A_P0<0> A_ADDR_DEC<5> net23<18> VDD VSS / ++ RSC_IHPSG13_NAND3X2 +XA_DEC3<12> A_N1<0> A_P0<0> A_ADDR_DEC<4> net23<19> VDD VSS / ++ RSC_IHPSG13_NAND3X2 +XA_DEC3<11> A_N1<0> A_P0<0> A_ADDR_DEC<3> net23<20> VDD VSS / ++ RSC_IHPSG13_NAND3X2 +XA_DEC3<10> A_N1<0> A_P0<0> A_ADDR_DEC<2> net23<21> VDD VSS / ++ RSC_IHPSG13_NAND3X2 +XA_DEC3<9> A_N1<0> A_P0<0> A_ADDR_DEC<1> net23<22> VDD VSS / ++ RSC_IHPSG13_NAND3X2 +XA_DEC3<8> A_N1<0> A_P0<0> A_ADDR_DEC<0> net23<23> VDD VSS / ++ RSC_IHPSG13_NAND3X2 +XA_DEC3<7> A_N1<0> A_N0<0> A_ADDR_DEC<7> net23<24> VDD VSS / ++ RSC_IHPSG13_NAND3X2 +XA_DEC3<6> A_N1<0> A_N0<0> A_ADDR_DEC<6> net23<25> VDD VSS / ++ RSC_IHPSG13_NAND3X2 +XA_DEC3<5> A_N1<0> A_N0<0> A_ADDR_DEC<5> net23<26> VDD VSS / ++ RSC_IHPSG13_NAND3X2 +XA_DEC3<4> A_N1<0> A_N0<0> A_ADDR_DEC<4> net23<27> VDD VSS / ++ RSC_IHPSG13_NAND3X2 +XA_DEC3<3> A_N1<0> A_N0<0> A_ADDR_DEC<3> net23<28> VDD VSS / ++ RSC_IHPSG13_NAND3X2 +XA_DEC3<2> A_N1<0> A_N0<0> A_ADDR_DEC<2> net23<29> VDD VSS / ++ RSC_IHPSG13_NAND3X2 +XA_DEC3<1> A_N1<0> A_N0<0> A_ADDR_DEC<1> net23<30> VDD VSS / ++ RSC_IHPSG13_NAND3X2 +XA_DEC3<0> A_N1<0> A_N0<0> A_ADDR_DEC<0> net23<31> VDD VSS / ++ RSC_IHPSG13_NAND3X2 +XA_I89 A_DCLK_B_L A_DCLK_B_R / RSC_IHPSG13_MET3RES +XA_I91 A_RCLK_B_L A_RCLK_B_R / RSC_IHPSG13_MET3RES +XA_I90 A_WCLK_B_L A_WCLK_B_R / RSC_IHPSG13_MET3RES +XA_I88 A_DCLK_L A_DCLK_R / RSC_IHPSG13_MET3RES +XA_I87 A_WCLK_L A_WCLK_R / RSC_IHPSG13_MET3RES +XA_R2 A_RCLK_L A_RCLK_R / RSC_IHPSG13_MET3RES +XA_BM_TIEH A_TIEH_O VDD VSS / RSC_IHPSG13_TIEH +.ENDS + +.SUBCKT RM_IHPSG13_1024x32_c2_1P_COLDRV13X12 ADDR_COL_I<1> ADDR_COL_I<0> ADDR_COL_O<1> ++ ADDR_COL_O<0> ADDR_DEC_I<7> ADDR_DEC_I<6> ADDR_DEC_I<5> ADDR_DEC_I<4> ++ ADDR_DEC_I<3> ADDR_DEC_I<2> ADDR_DEC_I<1> ADDR_DEC_I<0> ADDR_DEC_O<7> ++ ADDR_DEC_O<6> ADDR_DEC_O<5> ADDR_DEC_O<4> ADDR_DEC_O<3> ADDR_DEC_O<2> ++ ADDR_DEC_O<1> ADDR_DEC_O<0> DCLK_I DCLK_O RCLK_I RCLK_O WCLK_I WCLK_O ++ VDD VSS +XI1<1> VDD VSS / RSC_IHPSG13_FILLCAP4 +XI1<0> VDD VSS / RSC_IHPSG13_FILLCAP4 +XI0<1> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI0<0> VDD VSS / RSC_IHPSG13_FILLCAP8 +XADDR_COL_DRV<1> ADDR_COL_I<1> ADDR_COL_O<1> VDD VSS / ++ RSC_IHPSG13_CBUFX12 +XADDR_COL_DRV<0> ADDR_COL_I<0> ADDR_COL_O<0> VDD VSS / ++ RSC_IHPSG13_CBUFX12 +XADDR_DEC_DRV<7> ADDR_DEC_I<7> ADDR_DEC_O<7> VDD VSS / ++ RSC_IHPSG13_CBUFX12 +XADDR_DEC_DRV<6> ADDR_DEC_I<6> ADDR_DEC_O<6> VDD VSS / ++ RSC_IHPSG13_CBUFX12 +XADDR_DEC_DRV<5> ADDR_DEC_I<5> ADDR_DEC_O<5> VDD VSS / ++ RSC_IHPSG13_CBUFX12 +XADDR_DEC_DRV<4> ADDR_DEC_I<4> ADDR_DEC_O<4> VDD VSS / ++ RSC_IHPSG13_CBUFX12 +XADDR_DEC_DRV<3> ADDR_DEC_I<3> ADDR_DEC_O<3> VDD VSS / ++ RSC_IHPSG13_CBUFX12 +XADDR_DEC_DRV<2> ADDR_DEC_I<2> ADDR_DEC_O<2> VDD VSS / ++ RSC_IHPSG13_CBUFX12 +XADDR_DEC_DRV<1> ADDR_DEC_I<1> ADDR_DEC_O<1> VDD VSS / ++ RSC_IHPSG13_CBUFX12 +XADDR_DEC_DRV<0> ADDR_DEC_I<0> ADDR_DEC_O<0> VDD VSS / ++ RSC_IHPSG13_CBUFX12 +XDCLK_DRV DCLK_I DCLK_O VDD VSS / RSC_IHPSG13_CBUFX12 +XRCLK_DRV RCLK_I RCLK_O VDD VSS / RSC_IHPSG13_CBUFX12 +XWCLK_DRV WCLK_I WCLK_O VDD VSS / RSC_IHPSG13_CBUFX12 +.ENDS +.SUBCKT RM_IHPSG13_1024x32_c2_1P_WLDRV16X12 A<15> A<14> A<13> A<12> A<11> A<10> A<9> A<8> ++ A<7> A<6> A<5> A<4> A<3> A<2> A<1> A<0> Z<15> Z<14> Z<13> Z<12> Z<11> Z<10> ++ Z<9> Z<8> Z<7> Z<6> Z<5> Z<4> Z<3> Z<2> Z<1> Z<0> VDD VSS +XBUF<15> A<15> Z<15> VDD VSS / RSC_IHPSG13_WLDRVX12 +XBUF<14> A<14> Z<14> VDD VSS / RSC_IHPSG13_WLDRVX12 +XBUF<13> A<13> Z<13> VDD VSS / RSC_IHPSG13_WLDRVX12 +XBUF<12> A<12> Z<12> VDD VSS / RSC_IHPSG13_WLDRVX12 +XBUF<11> A<11> Z<11> VDD VSS / RSC_IHPSG13_WLDRVX12 +XBUF<10> A<10> Z<10> VDD VSS / RSC_IHPSG13_WLDRVX12 +XBUF<9> A<9> Z<9> VDD VSS / RSC_IHPSG13_WLDRVX12 +XBUF<8> A<8> Z<8> VDD VSS / RSC_IHPSG13_WLDRVX12 +XBUF<7> A<7> Z<7> VDD VSS / RSC_IHPSG13_WLDRVX12 +XBUF<6> A<6> Z<6> VDD VSS / RSC_IHPSG13_WLDRVX12 +XBUF<5> A<5> Z<5> VDD VSS / RSC_IHPSG13_WLDRVX12 +XBUF<4> A<4> Z<4> VDD VSS / RSC_IHPSG13_WLDRVX12 +XBUF<3> A<3> Z<3> VDD VSS / RSC_IHPSG13_WLDRVX12 +XBUF<2> A<2> Z<2> VDD VSS / RSC_IHPSG13_WLDRVX12 +XBUF<1> A<1> Z<1> VDD VSS / RSC_IHPSG13_WLDRVX12 +XBUF<0> A<0> Z<0> VDD VSS / RSC_IHPSG13_WLDRVX12 +.ENDS + + + +.SUBCKT RM_IHPSG13_1024x32_c2_2P_COLDRV13X8 ADDR_COL_I<1> ADDR_COL_I<0> ADDR_COL_O<1> ++ ADDR_COL_O<0> ADDR_DEC_I<7> ADDR_DEC_I<6> ADDR_DEC_I<5> ADDR_DEC_I<4> ++ ADDR_DEC_I<3> ADDR_DEC_I<2> ADDR_DEC_I<1> ADDR_DEC_I<0> ADDR_DEC_O<7> ++ ADDR_DEC_O<6> ADDR_DEC_O<5> ADDR_DEC_O<4> ADDR_DEC_O<3> ADDR_DEC_O<2> ++ ADDR_DEC_O<1> ADDR_DEC_O<0> DCLK_I DCLK_O RCLK_I RCLK_O WCLK_I WCLK_O ++ VDD VSS +XI0<5> VDD VSS / RSC_IHPSG13_FILLCAP4 +XI0<4> VDD VSS / RSC_IHPSG13_FILLCAP4 +XI0<3> VDD VSS / RSC_IHPSG13_FILLCAP4 +XI0<2> VDD VSS / RSC_IHPSG13_FILLCAP4 +XI0<1> VDD VSS / RSC_IHPSG13_FILLCAP4 +XWCLK_DRV WCLK_I WCLK_O VDD VSS / RSC_IHPSG13_CBUFX8 +XRCLK_DRV RCLK_I RCLK_O VDD VSS / RSC_IHPSG13_CBUFX8 +XDCLK_DRV DCLK_I DCLK_O VDD VSS / RSC_IHPSG13_CBUFX8 +XADDR_COL_DRV<1> ADDR_COL_I<1> ADDR_COL_O<1> VDD VSS / ++ RSC_IHPSG13_CBUFX8 +XADDR_COL_DRV<0> ADDR_COL_I<0> ADDR_COL_O<0> VDD VSS / ++ RSC_IHPSG13_CBUFX8 +XADDR_DEC_DRV<7> ADDR_DEC_I<7> ADDR_DEC_O<7> VDD VSS / ++ RSC_IHPSG13_CBUFX8 +XADDR_DEC_DRV<6> ADDR_DEC_I<6> ADDR_DEC_O<6> VDD VSS / ++ RSC_IHPSG13_CBUFX8 +XADDR_DEC_DRV<5> ADDR_DEC_I<5> ADDR_DEC_O<5> VDD VSS / ++ RSC_IHPSG13_CBUFX8 +XADDR_DEC_DRV<4> ADDR_DEC_I<4> ADDR_DEC_O<4> VDD VSS / ++ RSC_IHPSG13_CBUFX8 +XADDR_DEC_DRV<3> ADDR_DEC_I<3> ADDR_DEC_O<3> VDD VSS / ++ RSC_IHPSG13_CBUFX8 +XADDR_DEC_DRV<2> ADDR_DEC_I<2> ADDR_DEC_O<2> VDD VSS / ++ RSC_IHPSG13_CBUFX8 +XADDR_DEC_DRV<1> ADDR_DEC_I<1> ADDR_DEC_O<1> VDD VSS / ++ RSC_IHPSG13_CBUFX8 +XADDR_DEC_DRV<0> ADDR_DEC_I<0> ADDR_DEC_O<0> VDD VSS / ++ RSC_IHPSG13_CBUFX8 +XI1<3> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI1<2> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI1<1> VDD VSS / RSC_IHPSG13_FILLCAP8 +.ENDS +.SUBCKT RSC_IHPSG13_WLDRVX8 A Z VDD VSS +MN1 Z net6 VSS VSS sg13_lv_nmos m=1 w=1.41u l=130.00n ng=2 nrd=0 nrs=0 +MN0 net6 A VSS VSS sg13_lv_nmos m=1 w=1.8u l=130.00n ng=2 nrd=0 nrs=0 +MP1 Z net6 VDD VDD sg13_lv_pmos m=1 w=6.48u l=130.00n ng=4 nrd=0 nrs=0 +MP0 net6 A VDD VDD sg13_lv_pmos m=1 w=900.0n l=130.00n ng=1 nrd=0 nrs=0 +.ENDS +.SUBCKT RM_IHPSG13_1024x32_c2_2P_WLDRV16X8 A<15> A<14> A<13> A<12> A<11> A<10> A<9> A<8> ++ A<7> A<6> A<5> A<4> A<3> A<2> A<1> A<0> Z<15> Z<14> Z<13> Z<12> Z<11> Z<10> ++ Z<9> Z<8> Z<7> Z<6> Z<5> Z<4> Z<3> Z<2> Z<1> Z<0> VDD VSS +XBUF<15> A<15> Z<15> VDD VSS / RSC_IHPSG13_WLDRVX8 +XBUF<14> A<14> Z<14> VDD VSS / RSC_IHPSG13_WLDRVX8 +XBUF<13> A<13> Z<13> VDD VSS / RSC_IHPSG13_WLDRVX8 +XBUF<12> A<12> Z<12> VDD VSS / RSC_IHPSG13_WLDRVX8 +XBUF<11> A<11> Z<11> VDD VSS / RSC_IHPSG13_WLDRVX8 +XBUF<10> A<10> Z<10> VDD VSS / RSC_IHPSG13_WLDRVX8 +XBUF<9> A<9> Z<9> VDD VSS / RSC_IHPSG13_WLDRVX8 +XBUF<8> A<8> Z<8> VDD VSS / RSC_IHPSG13_WLDRVX8 +XBUF<7> A<7> Z<7> VDD VSS / RSC_IHPSG13_WLDRVX8 +XBUF<6> A<6> Z<6> VDD VSS / RSC_IHPSG13_WLDRVX8 +XBUF<5> A<5> Z<5> VDD VSS / RSC_IHPSG13_WLDRVX8 +XBUF<4> A<4> Z<4> VDD VSS / RSC_IHPSG13_WLDRVX8 +XBUF<3> A<3> Z<3> VDD VSS / RSC_IHPSG13_WLDRVX8 +XBUF<2> A<2> Z<2> VDD VSS / RSC_IHPSG13_WLDRVX8 +XBUF<1> A<1> Z<1> VDD VSS / RSC_IHPSG13_WLDRVX8 +XBUF<0> A<0> Z<0> VDD VSS / RSC_IHPSG13_WLDRVX8 +.ENDS + + + +.SUBCKT RM_IHPSG13_1024x32_c2_2P_COLDEC2 ACLK_N ADDR<1> ADDR<0> ADDR_COL<1> ADDR_COL<0> ++ ADDR_DEC<7> ADDR_DEC<6> ADDR_DEC<5> ADDR_DEC<4> ADDR_DEC<3> ADDR_DEC<2> ++ ADDR_DEC<1> ADDR_DEC<0> BIST_ADDR<1> BIST_ADDR<0> BIST_EN_I VDD VSS +XI16<17> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI16<16> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI16<15> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI16<14> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI16<13> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI16<12> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI16<11> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI16<10> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI16<9> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI16<8> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI16<7> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI16<6> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI16<5> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI16<4> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI16<3> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI16<2> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI16<1> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI18<24> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI18<23> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI18<22> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI18<21> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI18<20> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI18<19> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI18<18> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI18<17> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI18<16> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI18<15> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI18<14> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI18<13> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI18<12> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI18<11> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI18<10> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI18<9> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI18<8> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI18<7> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI18<6> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI18<5> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI18<4> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI18<3> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI18<2> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI18<1> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI1<3> PADR<0> PADR<1> addr_n<3> VDD VSS / RSC_IHPSG13_NAND2X2 +XI1<2> NADR<0> PADR<1> addr_n<2> VDD VSS / RSC_IHPSG13_NAND2X2 +XI1<1> PADR<0> NADR<1> addr_n<1> VDD VSS / RSC_IHPSG13_NAND2X2 +XI1<0> NADR<0> NADR<1> addr_n<0> VDD VSS / RSC_IHPSG13_NAND2X2 +XI17<1> ADDR_COL<1> VDD VSS / RSC_IHPSG13_TIEL +XI17<0> ADDR_COL<0> VDD VSS / RSC_IHPSG13_TIEL +XI14<3> ADDR_DEC<7> VDD VSS / RSC_IHPSG13_TIEL +XI14<2> ADDR_DEC<6> VDD VSS / RSC_IHPSG13_TIEL +XI14<1> ADDR_DEC<5> VDD VSS / RSC_IHPSG13_TIEL +XI14<0> ADDR_DEC<4> VDD VSS / RSC_IHPSG13_TIEL +XI13<1> NADR<1> PADR<1> VDD VSS / RSC_IHPSG13_INVX2 +XI13<0> NADR<0> PADR<0> VDD VSS / RSC_IHPSG13_INVX2 +XI3<1> padr_int<1> NADR<1> VDD VSS / RSC_IHPSG13_INVX2 +XI3<0> padr_int<0> NADR<0> VDD VSS / RSC_IHPSG13_INVX2 +XI2<3> addr_n<3> ADDR_DEC<3> VDD VSS / RSC_IHPSG13_INVX2 +XI2<2> addr_n<2> ADDR_DEC<2> VDD VSS / RSC_IHPSG13_INVX2 +XI2<1> addr_n<1> ADDR_DEC<1> VDD VSS / RSC_IHPSG13_INVX2 +XI2<0> addr_n<0> ADDR_DEC<0> VDD VSS / RSC_IHPSG13_INVX2 +XDFF<1> BIST_EN_I BIST_ADDR<1> ACLK_N ADDR<1> padr_int<1> net12<0> VDD ++ VSS / RSC_IHPSG13_DFNQMX2IX1 +XDFF<0> BIST_EN_I BIST_ADDR<0> ACLK_N ADDR<0> padr_int<0> net12<1> VDD ++ VSS / RSC_IHPSG13_DFNQMX2IX1 +XI15<5> VDD VSS / RSC_IHPSG13_FILLCAP4 +XI15<4> VDD VSS / RSC_IHPSG13_FILLCAP4 +XI15<3> VDD VSS / RSC_IHPSG13_FILLCAP4 +XI15<2> VDD VSS / RSC_IHPSG13_FILLCAP4 +XI15<1> VDD VSS / RSC_IHPSG13_FILLCAP4 +XI19<4> VDD VSS / RSC_IHPSG13_FILLCAP4 +XI19<3> VDD VSS / RSC_IHPSG13_FILLCAP4 +XI19<2> VDD VSS / RSC_IHPSG13_FILLCAP4 +XI19<1> VDD VSS / RSC_IHPSG13_FILLCAP4 +.ENDS +.SUBCKT RM_IHPSG13_1024x32_c2_2P_COLCTRL2 A_ADDR_DEC<3> A_ADDR_DEC<2> A_ADDR_DEC<1> ++ A_ADDR_DEC<0> A_BIST_BM_I A_BIST_DW_I A_BIST_EN_I A_BLC<3> A_BLC<2> A_BLC<1> ++ A_BLC<0> A_BLT<3> A_BLT<2> A_BLT<1> A_BLT<0> A_BM_I A_DCLK_B_L A_DCLK_B_R ++ A_DCLK_L A_DCLK_R A_DR_O A_DW_I A_RCLK_B_L A_RCLK_B_R A_RCLK_L A_RCLK_R ++ A_TIEH_O A_WCLK_B_L A_WCLK_B_R A_WCLK_L A_WCLK_R B_ADDR_DEC<3> B_ADDR_DEC<2> ++ B_ADDR_DEC<1> B_ADDR_DEC<0> B_BIST_BM_I B_BIST_DW_I B_BIST_EN_I B_BLC<3> ++ B_BLC<2> B_BLC<1> B_BLC<0> B_BLT<3> B_BLT<2> B_BLT<1> B_BLT<0> B_BM_I ++ B_DCLK_B_L B_DCLK_B_R B_DCLK_L B_DCLK_R B_DR_O B_DW_I B_RCLK_B_L B_RCLK_B_R ++ B_RCLK_L B_RCLK_R B_TIEH_O B_WCLK_B_L B_WCLK_B_R B_WCLK_L B_WCLK_R VDD ++ VSS +XB_DREG B_BIST_EN_I B_BIST_DW_I B_DCLK_B_L B_DW_I B_DI_R net046 VDD ++ VSS / RSC_IHPSG13_DFNQMX2IX1 +XB_BREG B_BIST_EN_I B_BIST_BM_I B_DCLK_B_L B_BM_I B_BM_R net045 VDD ++ VSS / RSC_IHPSG13_DFNQMX2IX1 +XA_DREG A_BIST_EN_I A_BIST_DW_I A_DCLK_B_L A_DW_I A_DI_R net22 VDD VSS ++ / RSC_IHPSG13_DFNQMX2IX1 +XA_BREG A_BIST_EN_I A_BIST_BM_I A_DCLK_B_L A_BM_I A_BM_R net23 VDD VSS ++ / RSC_IHPSG13_DFNQMX2IX1 +XB_CAPS VDD VSS / RSC_IHPSG13_FILLCAP4 +XA_CAPS VDD VSS / RSC_IHPSG13_FILLCAP4 +XB_I75 B_DI_R B_DO_WRITE_P B_WR_ONE VDD VSS / RSC_IHPSG13_AND2X2 +XB_I80 B_RCLK_B_L B_WCLK_B_L net041 VDD VSS / RSC_IHPSG13_AND2X2 +XB_I76 B_DI_N B_DO_WRITE_P B_WR_ZERO VDD VSS / RSC_IHPSG13_AND2X2 +XA_I80 A_RCLK_B_L A_WCLK_B_L net21 VDD VSS / RSC_IHPSG13_AND2X2 +XA_I75 A_DI_R A_DO_WRITE_P A_WR_ONE VDD VSS / RSC_IHPSG13_AND2X2 +XA_I76 A_DI_N A_DO_WRITE_P A_WR_ZERO VDD VSS / RSC_IHPSG13_AND2X2 +XB_I44 B_WCLK_B_L B_BM_N B_DO_WRITE_P VDD VSS / RSC_IHPSG13_NOR2X2 +XA_I44 A_WCLK_B_L A_BM_N A_DO_WRITE_P VDD VSS / RSC_IHPSG13_NOR2X2 +XB_I81 net041 B_PRE_N VDD VSS / RSC_IHPSG13_CINVX4_WN +XA_I81 net21 A_PRE_N VDD VSS / RSC_IHPSG13_CINVX4_WN +XB_BM_TIEH B_TIEH_O VDD VSS / RSC_IHPSG13_TIEH +XA_BM_TIEH A_TIEH_O VDD VSS / RSC_IHPSG13_TIEH +XA_I89 A_DCLK_B_L A_DCLK_B_R / RSC_IHPSG13_MET3RES +XA_I88 A_DCLK_L A_DCLK_R / RSC_IHPSG13_MET3RES +XA_I87 A_WCLK_L A_WCLK_R / RSC_IHPSG13_MET3RES +XA_I91 A_RCLK_B_L A_RCLK_B_R / RSC_IHPSG13_MET3RES +XB_I87 B_WCLK_L B_WCLK_R / RSC_IHPSG13_MET3RES +XB_I88 B_DCLK_L B_DCLK_R / RSC_IHPSG13_MET3RES +XB_I89 B_DCLK_B_L B_DCLK_B_R / RSC_IHPSG13_MET3RES +XB_I90 B_WCLK_B_L B_WCLK_B_R / RSC_IHPSG13_MET3RES +XB_R2 B_RCLK_L B_RCLK_R / RSC_IHPSG13_MET3RES +XB_I91 B_RCLK_B_L B_RCLK_B_R / RSC_IHPSG13_MET3RES +XA_R2 A_RCLK_L A_RCLK_R / RSC_IHPSG13_MET3RES +XA_I90 A_WCLK_B_L A_WCLK_B_R / RSC_IHPSG13_MET3RES +XAB_BLMUX A_BLC<3> A_BLC<2> A_BLC<1> A_BLC<0> A_BLC_SEL A_BLT<3> A_BLT<2> ++ A_BLT<1> A_BLT<0> A_BLT_SEL A_PRE_N A_ADDR_DEC<3> A_ADDR_DEC<2> ++ A_ADDR_DEC<1> A_ADDR_DEC<0> A_WR_ONE A_WR_ZERO B_BLC<3> B_BLC<2> B_BLC<1> ++ B_BLC<0> B_BLC_SEL B_BLT<3> B_BLT<2> B_BLT<1> B_BLT<0> B_BLT_SEL B_PRE_N ++ B_ADDR_DEC<3> B_ADDR_DEC<2> B_ADDR_DEC<1> B_ADDR_DEC<0> B_WR_ONE B_WR_ZERO ++ VDD VSS / RM_IHPSG13_1024x32_c2_2P_BLDRV +XB_ISENSE B_SAE B_BLC_SEL B_BLT_SEL net039 net040 VDD VSS / ++ RSC_IHPSG13_DFPQD_MSAFFX2 +XA_ISENSE A_SAE A_BLC_SEL A_BLT_SEL net19 net20 VDD VSS / ++ RSC_IHPSG13_DFPQD_MSAFFX2 +XB_I78 B_RCLK_B_L B_SAE VDD VSS / RSC_IHPSG13_CBUFX2 +XA_I78 A_RCLK_B_L A_SAE VDD VSS / RSC_IHPSG13_CBUFX2 +XB_I83 B_BM_R B_BM_N VDD VSS / RSC_IHPSG13_INVX2 +XB_I49 B_DI_R B_DI_N VDD VSS / RSC_IHPSG13_INVX2 +XA_I83 A_BM_R A_BM_N VDD VSS / RSC_IHPSG13_INVX2 +XA_I49 A_DI_R A_DI_N VDD VSS / RSC_IHPSG13_INVX2 +XB_I51 net039 B_DR_O VDD VSS / RSC_IHPSG13_INVX4 +XA_I51 net19 A_DR_O VDD VSS / RSC_IHPSG13_INVX4 +XA_I69 A_DCLK_L A_DCLK_B_L VDD VSS / RSC_IHPSG13_CINVX2 +XA_I50 A_WCLK_L A_WCLK_B_L VDD VSS / RSC_IHPSG13_CINVX2 +XA_EBUF A_RCLK_L A_RCLK_B_L VDD VSS / RSC_IHPSG13_CINVX2 +XB_EBUF B_RCLK_L B_RCLK_B_L VDD VSS / RSC_IHPSG13_CINVX2 +XB_I50 B_WCLK_L B_WCLK_B_L VDD VSS / RSC_IHPSG13_CINVX2 +XB_I69 B_DCLK_L B_DCLK_B_L VDD VSS / RSC_IHPSG13_CINVX2 +.ENDS +.SUBCKT RM_IHPSG13_1024x32_c2_2P_COLDRV13_FILL4C2 VDD VSS +XI0<2> VDD VSS / RSC_IHPSG13_FILLCAP4 +XI0<1> VDD VSS / RSC_IHPSG13_FILLCAP4 +.ENDS + + +.SUBCKT RM_IHPSG13_1024x32_c2_2P_ROWDEC7 ADDR_N_I<6> ADDR_N_I<5> ADDR_N_I<4> ADDR_N_I<3> ++ ADDR_N_I<2> ADDR_N_I<1> ADDR_N_I<0> CS_I ECLK_I WL_O<127> WL_O<126> ++ WL_O<125> WL_O<124> WL_O<123> WL_O<122> WL_O<121> WL_O<120> WL_O<119> ++ WL_O<118> WL_O<117> WL_O<116> WL_O<115> WL_O<114> WL_O<113> WL_O<112> ++ WL_O<111> WL_O<110> WL_O<109> WL_O<108> WL_O<107> WL_O<106> WL_O<105> ++ WL_O<104> WL_O<103> WL_O<102> WL_O<101> WL_O<100> WL_O<99> WL_O<98> WL_O<97> ++ WL_O<96> WL_O<95> WL_O<94> WL_O<93> WL_O<92> WL_O<91> WL_O<90> WL_O<89> ++ WL_O<88> WL_O<87> WL_O<86> WL_O<85> WL_O<84> WL_O<83> WL_O<82> WL_O<81> ++ WL_O<80> WL_O<79> WL_O<78> WL_O<77> WL_O<76> WL_O<75> WL_O<74> WL_O<73> ++ WL_O<72> WL_O<71> WL_O<70> WL_O<69> WL_O<68> WL_O<67> WL_O<66> WL_O<65> ++ WL_O<64> WL_O<63> WL_O<62> WL_O<61> WL_O<60> WL_O<59> WL_O<58> WL_O<57> ++ WL_O<56> WL_O<55> WL_O<54> WL_O<53> WL_O<52> WL_O<51> WL_O<50> WL_O<49> ++ WL_O<48> WL_O<47> WL_O<46> WL_O<45> WL_O<44> WL_O<43> WL_O<42> WL_O<41> ++ WL_O<40> WL_O<39> WL_O<38> WL_O<37> WL_O<36> WL_O<35> WL_O<34> WL_O<33> ++ WL_O<32> WL_O<31> WL_O<30> WL_O<29> WL_O<28> WL_O<27> WL_O<26> WL_O<25> ++ WL_O<24> WL_O<23> WL_O<22> WL_O<21> WL_O<20> WL_O<19> WL_O<18> WL_O<17> ++ WL_O<16> WL_O<15> WL_O<14> WL_O<13> WL_O<12> WL_O<11> WL_O<10> WL_O<9> ++ WL_O<8> WL_O<7> WL_O<6> WL_O<5> WL_O<4> WL_O<3> WL_O<2> WL_O<1> WL_O<0> ++ VDD VSS +XSEL<7> ADDR_N_I<3> ADDR_N_I<2> ADDR_N_I<1> ADDR_N_I<0> CS00<7> ECLK_H<7> ++ ECLK_H<8> ECLK_B<7> ECLK_B<8> WL_O<127> WL_O<126> WL_O<125> WL_O<124> ++ WL_O<123> WL_O<122> WL_O<121> WL_O<120> WL_O<119> WL_O<118> WL_O<117> ++ WL_O<116> WL_O<115> WL_O<114> WL_O<113> WL_O<112> VDD VSS / ++ RM_IHPSG13_1024x32_c2_2P_DEC04 +XSEL<6> ADDR_N_I<3> ADDR_N_I<2> ADDR_N_I<1> ADDR_N_I<0> CS00<6> ECLK_H<6> ++ ECLK_H<7> ECLK_B<6> ECLK_B<7> WL_O<111> WL_O<110> WL_O<109> WL_O<108> ++ WL_O<107> WL_O<106> WL_O<105> WL_O<104> WL_O<103> WL_O<102> WL_O<101> ++ WL_O<100> WL_O<99> WL_O<98> WL_O<97> WL_O<96> VDD VSS / ++ RM_IHPSG13_1024x32_c2_2P_DEC04 +XSEL<5> ADDR_N_I<3> ADDR_N_I<2> ADDR_N_I<1> ADDR_N_I<0> CS00<5> ECLK_H<5> ++ ECLK_H<6> ECLK_B<5> ECLK_B<6> WL_O<95> WL_O<94> WL_O<93> WL_O<92> WL_O<91> ++ WL_O<90> WL_O<89> WL_O<88> WL_O<87> WL_O<86> WL_O<85> WL_O<84> WL_O<83> ++ WL_O<82> WL_O<81> WL_O<80> VDD VSS / RM_IHPSG13_1024x32_c2_2P_DEC04 +XSEL<4> ADDR_N_I<3> ADDR_N_I<2> ADDR_N_I<1> ADDR_N_I<0> CS00<4> ECLK_H<4> ++ ECLK_H<5> ECLK_B<4> ECLK_B<5> WL_O<79> WL_O<78> WL_O<77> WL_O<76> WL_O<75> ++ WL_O<74> WL_O<73> WL_O<72> WL_O<71> WL_O<70> WL_O<69> WL_O<68> WL_O<67> ++ WL_O<66> WL_O<65> WL_O<64> VDD VSS / RM_IHPSG13_1024x32_c2_2P_DEC04 +XSEL<3> ADDR_N_I<3> ADDR_N_I<2> ADDR_N_I<1> ADDR_N_I<0> CS00<3> ECLK_H<3> ++ ECLK_H<4> ECLK_B<3> ECLK_B<4> WL_O<63> WL_O<62> WL_O<61> WL_O<60> WL_O<59> ++ WL_O<58> WL_O<57> WL_O<56> WL_O<55> WL_O<54> WL_O<53> WL_O<52> WL_O<51> ++ WL_O<50> WL_O<49> WL_O<48> VDD VSS / RM_IHPSG13_1024x32_c2_2P_DEC04 +XSEL<2> ADDR_N_I<3> ADDR_N_I<2> ADDR_N_I<1> ADDR_N_I<0> CS00<2> ECLK_H<2> ++ ECLK_H<3> ECLK_B<2> ECLK_B<3> WL_O<47> WL_O<46> WL_O<45> WL_O<44> WL_O<43> ++ WL_O<42> WL_O<41> WL_O<40> WL_O<39> WL_O<38> WL_O<37> WL_O<36> WL_O<35> ++ WL_O<34> WL_O<33> WL_O<32> VDD VSS / RM_IHPSG13_1024x32_c2_2P_DEC04 +XSEL<1> ADDR_N_I<3> ADDR_N_I<2> ADDR_N_I<1> ADDR_N_I<0> CS00<1> ECLK_H<1> ++ ECLK_H<2> ECLK_B<1> ECLK_B<2> WL_O<31> WL_O<30> WL_O<29> WL_O<28> WL_O<27> ++ WL_O<26> WL_O<25> WL_O<24> WL_O<23> WL_O<22> WL_O<21> WL_O<20> WL_O<19> ++ WL_O<18> WL_O<17> WL_O<16> VDD VSS / RM_IHPSG13_1024x32_c2_2P_DEC04 +XSEL<0> ADDR_N_I<3> ADDR_N_I<2> ADDR_N_I<1> ADDR_N_I<0> CS00<0> ECLK_I ++ ECLK_H<1> ECLK_B<0> ECLK_B<1> WL_O<15> WL_O<14> WL_O<13> WL_O<12> WL_O<11> ++ WL_O<10> WL_O<9> WL_O<8> WL_O<7> WL_O<6> WL_O<5> WL_O<4> WL_O<3> WL_O<2> ++ WL_O<1> WL_O<0> VDD VSS / RM_IHPSG13_1024x32_c2_2P_DEC04 +XDEC11<1> ADDR_N_I<5> ADDR_N_I<4> CS04<1> CS00<7> VDD VSS / ++ RM_IHPSG13_1024x32_c2_2P_DEC03 +XDEC11<0> ADDR_N_I<5> ADDR_N_I<4> CS04<0> CS00<3> VDD VSS / ++ RM_IHPSG13_1024x32_c2_2P_DEC03 +XDEC01<2> ADDR_N_I<7> ADDR_N_I<6> CS_I CS04<1> VDD VSS / ++ RM_IHPSG13_1024x32_c2_2P_DEC01 +XDEC01<1> ADDR_N_I<5> ADDR_N_I<4> CS04<1> CS00<5> VDD VSS / ++ RM_IHPSG13_1024x32_c2_2P_DEC01 +XDEC01<0> ADDR_N_I<5> ADDR_N_I<4> CS04<0> CS00<1> VDD VSS / ++ RM_IHPSG13_1024x32_c2_2P_DEC01 +XL2<66> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<65> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<64> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<63> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<62> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<61> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<60> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<59> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<58> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<57> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<56> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<55> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<54> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<53> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<52> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<51> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<50> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<49> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<48> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<47> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<46> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<45> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<44> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<43> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<42> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<41> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<40> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<39> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<38> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<37> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<36> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<35> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<34> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<33> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<32> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<31> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<30> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<29> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<28> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<27> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<26> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<25> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<24> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<23> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<22> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<21> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<20> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<19> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<18> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<17> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<16> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<15> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<14> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<13> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<12> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<11> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<10> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<9> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<8> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<7> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<6> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<5> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<4> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<3> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<2> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<1> VDD VSS / RSC_IHPSG13_FILLCAP8 +XDEC10<1> ADDR_N_I<5> ADDR_N_I<4> CS04<1> CS00<6> VDD VSS / ++ RM_IHPSG13_1024x32_c2_2P_DEC02 +XDEC10<0> ADDR_N_I<5> ADDR_N_I<4> CS04<0> CS00<2> VDD VSS / ++ RM_IHPSG13_1024x32_c2_2P_DEC02 +XDEC00<2> ADDR_N_I<7> ADDR_N_I<6> CS_I CS04<0> VDD VSS / ++ RM_IHPSG13_1024x32_c2_2P_DEC00 +XDEC00<1> ADDR_N_I<5> ADDR_N_I<4> CS04<1> CS00<4> VDD VSS / ++ RM_IHPSG13_1024x32_c2_2P_DEC00 +XDEC00<0> ADDR_N_I<5> ADDR_N_I<4> CS04<0> CS00<0> VDD VSS / ++ RM_IHPSG13_1024x32_c2_2P_DEC00 +XI0 ADDR_N_I<7> VDD VSS / RSC_IHPSG13_TIEL +.ENDS +.SUBCKT RM_IHPSG13_1024x32_c2_2P_ROWREG7 ACLK_N_I ADDR_I<6> ADDR_I<5> ADDR_I<4> ADDR_I<3> ++ ADDR_I<2> ADDR_I<1> ADDR_I<0> ADDR_N_O<6> ADDR_N_O<5> ADDR_N_O<4> ++ ADDR_N_O<3> ADDR_N_O<2> ADDR_N_O<1> ADDR_N_O<0> BIST_ADDR_I<6> ++ BIST_ADDR_I<5> BIST_ADDR_I<4> BIST_ADDR_I<3> BIST_ADDR_I<2> BIST_ADDR_I<1> ++ BIST_ADDR_I<0> BIST_EN_I VDD VSS +XINV<6> q_int<6> qn_int<6> VDD VSS / RSC_IHPSG13_CINVX2 +XINV<5> q_int<5> qn_int<5> VDD VSS / RSC_IHPSG13_CINVX2 +XINV<4> q_int<4> qn_int<4> VDD VSS / RSC_IHPSG13_CINVX2 +XINV<3> q_int<3> qn_int<3> VDD VSS / RSC_IHPSG13_CINVX2 +XINV<2> q_int<2> qn_int<2> VDD VSS / RSC_IHPSG13_CINVX2 +XINV<1> q_int<1> qn_int<1> VDD VSS / RSC_IHPSG13_CINVX2 +XINV<0> q_int<0> qn_int<0> VDD VSS / RSC_IHPSG13_CINVX2 +XDRV<6> qn_int<6> ADDR_N_O<6> VDD VSS / RSC_IHPSG13_CINVX8 +XDRV<5> qn_int<5> ADDR_N_O<5> VDD VSS / RSC_IHPSG13_CINVX8 +XDRV<4> qn_int<4> ADDR_N_O<4> VDD VSS / RSC_IHPSG13_CINVX8 +XDRV<3> qn_int<3> ADDR_N_O<3> VDD VSS / RSC_IHPSG13_CINVX8 +XDRV<2> qn_int<2> ADDR_N_O<2> VDD VSS / RSC_IHPSG13_CINVX8 +XDRV<1> qn_int<1> ADDR_N_O<1> VDD VSS / RSC_IHPSG13_CINVX8 +XDRV<0> qn_int<0> ADDR_N_O<0> VDD VSS / RSC_IHPSG13_CINVX8 +XDFF<6> BIST_EN_I BIST_ADDR_I<6> ACLK_N_I ADDR_I<6> q_int<6> net2<0> VDD ++ VSS / RSC_IHPSG13_DFNQMX2IX1 +XDFF<5> BIST_EN_I BIST_ADDR_I<5> ACLK_N_I ADDR_I<5> q_int<5> net2<1> VDD ++ VSS / RSC_IHPSG13_DFNQMX2IX1 +XDFF<4> BIST_EN_I BIST_ADDR_I<4> ACLK_N_I ADDR_I<4> q_int<4> net2<2> VDD ++ VSS / RSC_IHPSG13_DFNQMX2IX1 +XDFF<3> BIST_EN_I BIST_ADDR_I<3> ACLK_N_I ADDR_I<3> q_int<3> net2<3> VDD ++ VSS / RSC_IHPSG13_DFNQMX2IX1 +XDFF<2> BIST_EN_I BIST_ADDR_I<2> ACLK_N_I ADDR_I<2> q_int<2> net2<4> VDD ++ VSS / RSC_IHPSG13_DFNQMX2IX1 +XDFF<1> BIST_EN_I BIST_ADDR_I<1> ACLK_N_I ADDR_I<1> q_int<1> net2<5> VDD ++ VSS / RSC_IHPSG13_DFNQMX2IX1 +XDFF<0> BIST_EN_I BIST_ADDR_I<0> ACLK_N_I ADDR_I<0> q_int<0> net2<6> VDD ++ VSS / RSC_IHPSG13_DFNQMX2IX1 +XI11<7> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI11<6> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI11<5> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI11<4> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI11<3> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI11<2> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI11<1> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI11<0> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI12<1> VDD VSS / RSC_IHPSG13_FILLCAP4 +XI12<0> VDD VSS / RSC_IHPSG13_FILLCAP4 +.ENDS + +.SUBCKT RM_IHPSG13_1024x32_c2_2P_ROWDEC4 ADDR_N_I<3> ADDR_N_I<2> ADDR_N_I<1> ADDR_N_I<0> ++ CS_I ECLK_I WL_O<15> WL_O<14> WL_O<13> WL_O<12> WL_O<11> WL_O<10> WL_O<9> ++ WL_O<8> WL_O<7> WL_O<6> WL_O<5> WL_O<4> WL_O<3> WL_O<2> WL_O<1> WL_O<0> ++ VDD VSS +XL2<12> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<11> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<10> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<9> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<8> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<7> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<6> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<5> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<4> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<3> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<2> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<1> VDD VSS / RSC_IHPSG13_FILLCAP8 +XSEL ADDR_N_I<3> ADDR_N_I<2> ADDR_N_I<1> ADDR_N_I<0> CS_I ECLK_I ECLK_H<1> ++ ECLK_B<0> ECLK_B<1> WL_O<15> WL_O<14> WL_O<13> WL_O<12> WL_O<11> WL_O<10> ++ WL_O<9> WL_O<8> WL_O<7> WL_O<6> WL_O<5> WL_O<4> WL_O<3> WL_O<2> WL_O<1> ++ WL_O<0> VDD VSS / RM_IHPSG13_1024x32_c2_2P_DEC04 +.ENDS +.SUBCKT RM_IHPSG13_1024x32_c2_2P_ROWREG4 ACLK_N_I ADDR_I<3> ADDR_I<2> ADDR_I<1> ADDR_I<0> ++ ADDR_N_O<3> ADDR_N_O<2> ADDR_N_O<1> ADDR_N_O<0> BIST_ADDR_I<3> ++ BIST_ADDR_I<2> BIST_ADDR_I<1> BIST_ADDR_I<0> BIST_EN_I VDD VSS +XINV<3> q_int<3> qn_int<3> VDD VSS / RSC_IHPSG13_CINVX2 +XINV<2> q_int<2> qn_int<2> VDD VSS / RSC_IHPSG13_CINVX2 +XINV<1> q_int<1> qn_int<1> VDD VSS / RSC_IHPSG13_CINVX2 +XINV<0> q_int<0> qn_int<0> VDD VSS / RSC_IHPSG13_CINVX2 +XDRV<3> qn_int<3> ADDR_N_O<3> VDD VSS / RSC_IHPSG13_CINVX8 +XDRV<2> qn_int<2> ADDR_N_O<2> VDD VSS / RSC_IHPSG13_CINVX8 +XDRV<1> qn_int<1> ADDR_N_O<1> VDD VSS / RSC_IHPSG13_CINVX8 +XDRV<0> qn_int<0> ADDR_N_O<0> VDD VSS / RSC_IHPSG13_CINVX8 +XDFF<3> BIST_EN_I BIST_ADDR_I<3> ACLK_N_I ADDR_I<3> q_int<3> net7<0> VDD ++ VSS / RSC_IHPSG13_DFNQMX2IX1 +XDFF<2> BIST_EN_I BIST_ADDR_I<2> ACLK_N_I ADDR_I<2> q_int<2> net7<1> VDD ++ VSS / RSC_IHPSG13_DFNQMX2IX1 +XDFF<1> BIST_EN_I BIST_ADDR_I<1> ACLK_N_I ADDR_I<1> q_int<1> net7<2> VDD ++ VSS / RSC_IHPSG13_DFNQMX2IX1 +XDFF<0> BIST_EN_I BIST_ADDR_I<0> ACLK_N_I ADDR_I<0> q_int<0> net7<3> VDD ++ VSS / RSC_IHPSG13_DFNQMX2IX1 +XI11<20> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI11<19> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI11<18> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI11<17> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI11<16> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI11<15> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI11<14> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI11<13> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI11<12> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI11<11> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI11<10> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI11<9> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI11<8> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI11<7> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI11<6> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI11<5> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI11<4> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI11<3> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI11<2> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI11<1> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI12<4> VDD VSS / RSC_IHPSG13_FILLCAP4 +XI12<3> VDD VSS / RSC_IHPSG13_FILLCAP4 +XI12<2> VDD VSS / RSC_IHPSG13_FILLCAP4 +XI12<1> VDD VSS / RSC_IHPSG13_FILLCAP4 +XI12<0> VDD VSS / RSC_IHPSG13_FILLCAP4 +.ENDS + + +.SUBCKT RM_IHPSG13_1024x32_c2_1P_BITKIT_TAP BLC BLT NW PW VDD VSS +.ENDS +.SUBCKT RM_IHPSG13_1024x32_c2_1P_BITKIT_16x2_TAP A_BLC<1> A_BLC<0> A_BLT<1> A_BLT<0> ++ VDD_CORE VSS +XITAP<1> A_BLC<1> A_BLT<1> VDD_CORE VSS VDD_CORE VSS ++ / RM_IHPSG13_1024x32_c2_1P_BITKIT_TAP +XITAP<0> A_BLC<0> A_BLT<0> VDD_CORE VSS VDD_CORE VSS ++ / RM_IHPSG13_1024x32_c2_1P_BITKIT_TAP +XIEDGEBP_COL1<1> BLC<1> BLT<1> VDD_CORE VSS VDD_CORE ++ VSS / RM_IHPSG13_1024x32_c2_1P_BITKIT_EDGE_TB +XIEDGEBP_COL1<0> BLC<1> BLT<1> VDD_CORE VSS VDD_CORE ++ VSS / RM_IHPSG13_1024x32_c2_1P_BITKIT_EDGE_TB +XIEDGEBP_COL2<1> BLC<0> BLT<0> VDD_CORE VSS VDD_CORE ++ VSS / RM_IHPSG13_1024x32_c2_1P_BITKIT_EDGE_TB +XIEDGEBP_COL2<0> BLC<0> BLT<0> VDD_CORE VSS VDD_CORE ++ VSS / RM_IHPSG13_1024x32_c2_1P_BITKIT_EDGE_TB +.ENDS +.SUBCKT RM_IHPSG13_1024x32_c2_1P_BITKIT_16x2_TAP_LR VDD_CORE VSS +XCORNER<1> VDD_CORE VSS VDD_CORE VSS / ++ RM_IHPSG13_1024x32_c2_1P_BITKIT_CORNER +XCORNER<0> VDD_CORE VSS VDD_CORE VSS / ++ RM_IHPSG13_1024x32_c2_1P_BITKIT_CORNER +XTAP_BORDER VDD_CORE VSS VDD_CORE VSS / ++ RM_IHPSG13_1024x32_c2_1P_BITKIT_TAP_LR +.ENDS +.SUBCKT RM_IHPSG13_1024x32_c2_1P_DEC03 ADDR<1> ADDR<0> CS CS_OUT VDD VSS +XDECINV net1 CS_OUT VDD VSS / RSC_IHPSG13_INVX4 +XI0 VDD VSS / RSC_IHPSG13_FILLCAP4 +XDEC ADDR<1> ADDR<0> CS net1 VDD VSS / RSC_IHPSG13_NAND3X2 +.ENDS +.SUBCKT RM_IHPSG13_1024x32_c2_1P_DEC02 ADDR<1> ADDR<0> CS CS_OUT VDD VSS +XDECINV net1 CS_OUT VDD VSS / RSC_IHPSG13_INVX4 +XDEC ADDR<1> NADDR<0> CS net1 VDD VSS / RSC_IHPSG13_NAND3X2 +XI2 VDD VSS / RSC_IHPSG13_FILLCAP4 +XADDRINV ADDR<0> NADDR<0> VDD VSS / RSC_IHPSG13_INVX2 +.ENDS +.SUBCKT RM_IHPSG13_1024x32_c2_1P_ROWDEC8 ADDR_N_I<7> ADDR_N_I<6> ADDR_N_I<5> ADDR_N_I<4> ++ ADDR_N_I<3> ADDR_N_I<2> ADDR_N_I<1> ADDR_N_I<0> CS_I ECLK_I WL_O<255> ++ WL_O<254> WL_O<253> WL_O<252> WL_O<251> WL_O<250> WL_O<249> WL_O<248> ++ WL_O<247> WL_O<246> WL_O<245> WL_O<244> WL_O<243> WL_O<242> WL_O<241> ++ WL_O<240> WL_O<239> WL_O<238> WL_O<237> WL_O<236> WL_O<235> WL_O<234> ++ WL_O<233> WL_O<232> WL_O<231> WL_O<230> WL_O<229> WL_O<228> WL_O<227> ++ WL_O<226> WL_O<225> WL_O<224> WL_O<223> WL_O<222> WL_O<221> WL_O<220> ++ WL_O<219> WL_O<218> WL_O<217> WL_O<216> WL_O<215> WL_O<214> WL_O<213> ++ WL_O<212> WL_O<211> WL_O<210> WL_O<209> WL_O<208> WL_O<207> WL_O<206> ++ WL_O<205> WL_O<204> WL_O<203> WL_O<202> WL_O<201> WL_O<200> WL_O<199> ++ WL_O<198> WL_O<197> WL_O<196> WL_O<195> WL_O<194> WL_O<193> WL_O<192> ++ WL_O<191> WL_O<190> WL_O<189> WL_O<188> WL_O<187> WL_O<186> WL_O<185> ++ WL_O<184> WL_O<183> WL_O<182> WL_O<181> WL_O<180> WL_O<179> WL_O<178> ++ WL_O<177> WL_O<176> WL_O<175> WL_O<174> WL_O<173> WL_O<172> WL_O<171> ++ WL_O<170> WL_O<169> WL_O<168> WL_O<167> WL_O<166> WL_O<165> WL_O<164> ++ WL_O<163> WL_O<162> WL_O<161> WL_O<160> WL_O<159> WL_O<158> WL_O<157> ++ WL_O<156> WL_O<155> WL_O<154> WL_O<153> WL_O<152> WL_O<151> WL_O<150> ++ WL_O<149> WL_O<148> WL_O<147> WL_O<146> WL_O<145> WL_O<144> WL_O<143> ++ WL_O<142> WL_O<141> WL_O<140> WL_O<139> WL_O<138> WL_O<137> WL_O<136> ++ WL_O<135> WL_O<134> WL_O<133> WL_O<132> WL_O<131> WL_O<130> WL_O<129> ++ WL_O<128> WL_O<127> WL_O<126> WL_O<125> WL_O<124> WL_O<123> WL_O<122> ++ WL_O<121> WL_O<120> WL_O<119> WL_O<118> WL_O<117> WL_O<116> WL_O<115> ++ WL_O<114> WL_O<113> WL_O<112> WL_O<111> WL_O<110> WL_O<109> WL_O<108> ++ WL_O<107> WL_O<106> WL_O<105> WL_O<104> WL_O<103> WL_O<102> WL_O<101> ++ WL_O<100> WL_O<99> WL_O<98> WL_O<97> WL_O<96> WL_O<95> WL_O<94> WL_O<93> ++ WL_O<92> WL_O<91> WL_O<90> WL_O<89> WL_O<88> WL_O<87> WL_O<86> WL_O<85> ++ WL_O<84> WL_O<83> WL_O<82> WL_O<81> WL_O<80> WL_O<79> WL_O<78> WL_O<77> ++ WL_O<76> WL_O<75> WL_O<74> WL_O<73> WL_O<72> WL_O<71> WL_O<70> WL_O<69> ++ WL_O<68> WL_O<67> WL_O<66> WL_O<65> WL_O<64> WL_O<63> WL_O<62> WL_O<61> ++ WL_O<60> WL_O<59> WL_O<58> WL_O<57> WL_O<56> WL_O<55> WL_O<54> WL_O<53> ++ WL_O<52> WL_O<51> WL_O<50> WL_O<49> WL_O<48> WL_O<47> WL_O<46> WL_O<45> ++ WL_O<44> WL_O<43> WL_O<42> WL_O<41> WL_O<40> WL_O<39> WL_O<38> WL_O<37> ++ WL_O<36> WL_O<35> WL_O<34> WL_O<33> WL_O<32> WL_O<31> WL_O<30> WL_O<29> ++ WL_O<28> WL_O<27> WL_O<26> WL_O<25> WL_O<24> WL_O<23> WL_O<22> WL_O<21> ++ WL_O<20> WL_O<19> WL_O<18> WL_O<17> WL_O<16> WL_O<15> WL_O<14> WL_O<13> ++ WL_O<12> WL_O<11> WL_O<10> WL_O<9> WL_O<8> WL_O<7> WL_O<6> WL_O<5> WL_O<4> ++ WL_O<3> WL_O<2> WL_O<1> WL_O<0> VDD VSS +XDEC11<4> ADDR_N_I<7> ADDR_N_I<6> CS_I CS04<3> VDD VSS / ++ RM_IHPSG13_1024x32_c2_1P_DEC03 +XDEC11<3> ADDR_N_I<5> ADDR_N_I<4> CS04<3> CS00<15> VDD VSS / ++ RM_IHPSG13_1024x32_c2_1P_DEC03 +XDEC11<2> ADDR_N_I<5> ADDR_N_I<4> CS04<2> CS00<11> VDD VSS / ++ RM_IHPSG13_1024x32_c2_1P_DEC03 +XDEC11<1> ADDR_N_I<5> ADDR_N_I<4> CS04<1> CS00<7> VDD VSS / ++ RM_IHPSG13_1024x32_c2_1P_DEC03 +XDEC11<0> ADDR_N_I<5> ADDR_N_I<4> CS04<0> CS00<3> VDD VSS / ++ RM_IHPSG13_1024x32_c2_1P_DEC03 +XL2<88> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<87> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<86> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<85> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<84> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<83> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<82> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<81> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<80> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<79> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<78> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<77> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<76> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<75> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<74> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<73> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<72> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<71> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<70> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<69> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<68> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<67> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<66> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<65> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<64> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<63> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<62> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<61> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<60> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<59> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<58> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<57> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<56> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<55> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<54> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<53> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<52> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<51> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<50> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<49> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<48> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<47> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<46> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<45> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<44> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<43> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<42> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<41> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<40> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<39> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<38> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<37> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<36> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<35> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<34> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<33> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<32> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<31> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<30> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<29> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<28> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<27> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<26> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<25> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<24> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<23> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<22> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<21> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<20> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<19> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<18> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<17> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<16> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<15> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<14> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<13> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<12> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<11> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<10> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<9> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<8> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<7> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<6> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<5> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<4> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<3> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<2> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<1> VDD VSS / RSC_IHPSG13_FILLCAP8 +XDEC10<4> ADDR_N_I<7> ADDR_N_I<6> CS_I CS04<2> VDD VSS / ++ RM_IHPSG13_1024x32_c2_1P_DEC02 +XDEC10<3> ADDR_N_I<5> ADDR_N_I<4> CS04<3> CS00<14> VDD VSS / ++ RM_IHPSG13_1024x32_c2_1P_DEC02 +XDEC10<2> ADDR_N_I<5> ADDR_N_I<4> CS04<2> CS00<10> VDD VSS / ++ RM_IHPSG13_1024x32_c2_1P_DEC02 +XDEC10<1> ADDR_N_I<5> ADDR_N_I<4> CS04<1> CS00<6> VDD VSS / ++ RM_IHPSG13_1024x32_c2_1P_DEC02 +XDEC10<0> ADDR_N_I<5> ADDR_N_I<4> CS04<0> CS00<2> VDD VSS / ++ RM_IHPSG13_1024x32_c2_1P_DEC02 +XDEC00<4> ADDR_N_I<7> ADDR_N_I<6> CS_I CS04<0> VDD VSS / ++ RM_IHPSG13_1024x32_c2_1P_DEC00 +XDEC00<3> ADDR_N_I<5> ADDR_N_I<4> CS04<3> CS00<12> VDD VSS / ++ RM_IHPSG13_1024x32_c2_1P_DEC00 +XDEC00<2> ADDR_N_I<5> ADDR_N_I<4> CS04<2> CS00<8> VDD VSS / ++ RM_IHPSG13_1024x32_c2_1P_DEC00 +XDEC00<1> ADDR_N_I<5> ADDR_N_I<4> CS04<1> CS00<4> VDD VSS / ++ RM_IHPSG13_1024x32_c2_1P_DEC00 +XDEC00<0> ADDR_N_I<5> ADDR_N_I<4> CS04<0> CS00<0> VDD VSS / ++ RM_IHPSG13_1024x32_c2_1P_DEC00 +XSEL<15> ADDR_N_I<3> ADDR_N_I<2> ADDR_N_I<1> ADDR_N_I<0> CS00<15> ECLK_H<15> ++ ECLK_H<16> ECLK_B<15> ECLK_B<16> WL_O<255> WL_O<254> WL_O<253> WL_O<252> ++ WL_O<251> WL_O<250> WL_O<249> WL_O<248> WL_O<247> WL_O<246> WL_O<245> ++ WL_O<244> WL_O<243> WL_O<242> WL_O<241> WL_O<240> VDD VSS / ++ RM_IHPSG13_1024x32_c2_1P_DEC04 +XSEL<14> ADDR_N_I<3> ADDR_N_I<2> ADDR_N_I<1> ADDR_N_I<0> CS00<14> ECLK_H<14> ++ ECLK_H<15> ECLK_B<14> ECLK_B<15> WL_O<239> WL_O<238> WL_O<237> WL_O<236> ++ WL_O<235> WL_O<234> WL_O<233> WL_O<232> WL_O<231> WL_O<230> WL_O<229> ++ WL_O<228> WL_O<227> WL_O<226> WL_O<225> WL_O<224> VDD VSS / ++ RM_IHPSG13_1024x32_c2_1P_DEC04 +XSEL<13> ADDR_N_I<3> ADDR_N_I<2> ADDR_N_I<1> ADDR_N_I<0> CS00<13> ECLK_H<13> ++ ECLK_H<14> ECLK_B<13> ECLK_B<14> WL_O<223> WL_O<222> WL_O<221> WL_O<220> ++ WL_O<219> WL_O<218> WL_O<217> WL_O<216> WL_O<215> WL_O<214> WL_O<213> ++ WL_O<212> WL_O<211> WL_O<210> WL_O<209> WL_O<208> VDD VSS / ++ RM_IHPSG13_1024x32_c2_1P_DEC04 +XSEL<12> ADDR_N_I<3> ADDR_N_I<2> ADDR_N_I<1> ADDR_N_I<0> CS00<12> ECLK_H<12> ++ ECLK_H<13> ECLK_B<12> ECLK_B<13> WL_O<207> WL_O<206> WL_O<205> WL_O<204> ++ WL_O<203> WL_O<202> WL_O<201> WL_O<200> WL_O<199> WL_O<198> WL_O<197> ++ WL_O<196> WL_O<195> WL_O<194> WL_O<193> WL_O<192> VDD VSS / ++ RM_IHPSG13_1024x32_c2_1P_DEC04 +XSEL<11> ADDR_N_I<3> ADDR_N_I<2> ADDR_N_I<1> ADDR_N_I<0> CS00<11> ECLK_H<11> ++ ECLK_H<12> ECLK_B<11> ECLK_B<12> WL_O<191> WL_O<190> WL_O<189> WL_O<188> ++ WL_O<187> WL_O<186> WL_O<185> WL_O<184> WL_O<183> WL_O<182> WL_O<181> ++ WL_O<180> WL_O<179> WL_O<178> WL_O<177> WL_O<176> VDD VSS / ++ RM_IHPSG13_1024x32_c2_1P_DEC04 +XSEL<10> ADDR_N_I<3> ADDR_N_I<2> ADDR_N_I<1> ADDR_N_I<0> CS00<10> ECLK_H<10> ++ ECLK_H<11> ECLK_B<10> ECLK_B<11> WL_O<175> WL_O<174> WL_O<173> WL_O<172> ++ WL_O<171> WL_O<170> WL_O<169> WL_O<168> WL_O<167> WL_O<166> WL_O<165> ++ WL_O<164> WL_O<163> WL_O<162> WL_O<161> WL_O<160> VDD VSS / ++ RM_IHPSG13_1024x32_c2_1P_DEC04 +XSEL<9> ADDR_N_I<3> ADDR_N_I<2> ADDR_N_I<1> ADDR_N_I<0> CS00<9> ECLK_H<9> ++ ECLK_H<10> ECLK_B<9> ECLK_B<10> WL_O<159> WL_O<158> WL_O<157> WL_O<156> ++ WL_O<155> WL_O<154> WL_O<153> WL_O<152> WL_O<151> WL_O<150> WL_O<149> ++ WL_O<148> WL_O<147> WL_O<146> WL_O<145> WL_O<144> VDD VSS / ++ RM_IHPSG13_1024x32_c2_1P_DEC04 +XSEL<8> ADDR_N_I<3> ADDR_N_I<2> ADDR_N_I<1> ADDR_N_I<0> CS00<8> ECLK_H<8> ++ ECLK_H<9> ECLK_B<8> ECLK_B<9> WL_O<143> WL_O<142> WL_O<141> WL_O<140> ++ WL_O<139> WL_O<138> WL_O<137> WL_O<136> WL_O<135> WL_O<134> WL_O<133> ++ WL_O<132> WL_O<131> WL_O<130> WL_O<129> WL_O<128> VDD VSS / ++ RM_IHPSG13_1024x32_c2_1P_DEC04 +XSEL<7> ADDR_N_I<3> ADDR_N_I<2> ADDR_N_I<1> ADDR_N_I<0> CS00<7> ECLK_H<7> ++ ECLK_H<8> ECLK_B<7> ECLK_B<8> WL_O<127> WL_O<126> WL_O<125> WL_O<124> ++ WL_O<123> WL_O<122> WL_O<121> WL_O<120> WL_O<119> WL_O<118> WL_O<117> ++ WL_O<116> WL_O<115> WL_O<114> WL_O<113> WL_O<112> VDD VSS / ++ RM_IHPSG13_1024x32_c2_1P_DEC04 +XSEL<6> ADDR_N_I<3> ADDR_N_I<2> ADDR_N_I<1> ADDR_N_I<0> CS00<6> ECLK_H<6> ++ ECLK_H<7> ECLK_B<6> ECLK_B<7> WL_O<111> WL_O<110> WL_O<109> WL_O<108> ++ WL_O<107> WL_O<106> WL_O<105> WL_O<104> WL_O<103> WL_O<102> WL_O<101> ++ WL_O<100> WL_O<99> WL_O<98> WL_O<97> WL_O<96> VDD VSS / ++ RM_IHPSG13_1024x32_c2_1P_DEC04 +XSEL<5> ADDR_N_I<3> ADDR_N_I<2> ADDR_N_I<1> ADDR_N_I<0> CS00<5> ECLK_H<5> ++ ECLK_H<6> ECLK_B<5> ECLK_B<6> WL_O<95> WL_O<94> WL_O<93> WL_O<92> WL_O<91> ++ WL_O<90> WL_O<89> WL_O<88> WL_O<87> WL_O<86> WL_O<85> WL_O<84> WL_O<83> ++ WL_O<82> WL_O<81> WL_O<80> VDD VSS / RM_IHPSG13_1024x32_c2_1P_DEC04 +XSEL<4> ADDR_N_I<3> ADDR_N_I<2> ADDR_N_I<1> ADDR_N_I<0> CS00<4> ECLK_H<4> ++ ECLK_H<5> ECLK_B<4> ECLK_B<5> WL_O<79> WL_O<78> WL_O<77> WL_O<76> WL_O<75> ++ WL_O<74> WL_O<73> WL_O<72> WL_O<71> WL_O<70> WL_O<69> WL_O<68> WL_O<67> ++ WL_O<66> WL_O<65> WL_O<64> VDD VSS / RM_IHPSG13_1024x32_c2_1P_DEC04 +XSEL<3> ADDR_N_I<3> ADDR_N_I<2> ADDR_N_I<1> ADDR_N_I<0> CS00<3> ECLK_H<3> ++ ECLK_H<4> ECLK_B<3> ECLK_B<4> WL_O<63> WL_O<62> WL_O<61> WL_O<60> WL_O<59> ++ WL_O<58> WL_O<57> WL_O<56> WL_O<55> WL_O<54> WL_O<53> WL_O<52> WL_O<51> ++ WL_O<50> WL_O<49> WL_O<48> VDD VSS / RM_IHPSG13_1024x32_c2_1P_DEC04 +XSEL<2> ADDR_N_I<3> ADDR_N_I<2> ADDR_N_I<1> ADDR_N_I<0> CS00<2> ECLK_H<2> ++ ECLK_H<3> ECLK_B<2> ECLK_B<3> WL_O<47> WL_O<46> WL_O<45> WL_O<44> WL_O<43> ++ WL_O<42> WL_O<41> WL_O<40> WL_O<39> WL_O<38> WL_O<37> WL_O<36> WL_O<35> ++ WL_O<34> WL_O<33> WL_O<32> VDD VSS / RM_IHPSG13_1024x32_c2_1P_DEC04 +XSEL<1> ADDR_N_I<3> ADDR_N_I<2> ADDR_N_I<1> ADDR_N_I<0> CS00<1> ECLK_H<1> ++ ECLK_H<2> ECLK_B<1> ECLK_B<2> WL_O<31> WL_O<30> WL_O<29> WL_O<28> WL_O<27> ++ WL_O<26> WL_O<25> WL_O<24> WL_O<23> WL_O<22> WL_O<21> WL_O<20> WL_O<19> ++ WL_O<18> WL_O<17> WL_O<16> VDD VSS / RM_IHPSG13_1024x32_c2_1P_DEC04 +XSEL<0> ADDR_N_I<3> ADDR_N_I<2> ADDR_N_I<1> ADDR_N_I<0> CS00<0> ECLK_I ++ ECLK_H<1> ECLK_B<0> ECLK_B<1> WL_O<15> WL_O<14> WL_O<13> WL_O<12> WL_O<11> ++ WL_O<10> WL_O<9> WL_O<8> WL_O<7> WL_O<6> WL_O<5> WL_O<4> WL_O<3> WL_O<2> ++ WL_O<1> WL_O<0> VDD VSS / RM_IHPSG13_1024x32_c2_1P_DEC04 +XDEC01<4> ADDR_N_I<7> ADDR_N_I<6> CS_I CS04<1> VDD VSS / ++ RM_IHPSG13_1024x32_c2_1P_DEC01 +XDEC01<3> ADDR_N_I<5> ADDR_N_I<4> CS04<3> CS00<13> VDD VSS / ++ RM_IHPSG13_1024x32_c2_1P_DEC01 +XDEC01<2> ADDR_N_I<5> ADDR_N_I<4> CS04<2> CS00<9> VDD VSS / ++ RM_IHPSG13_1024x32_c2_1P_DEC01 +XDEC01<1> ADDR_N_I<5> ADDR_N_I<4> CS04<1> CS00<5> VDD VSS / ++ RM_IHPSG13_1024x32_c2_1P_DEC01 +XDEC01<0> ADDR_N_I<5> ADDR_N_I<4> CS04<0> CS00<1> VDD VSS / ++ RM_IHPSG13_1024x32_c2_1P_DEC01 +.ENDS +.SUBCKT RM_IHPSG13_1024x32_c2_1P_ROWREG8 ACLK_N_I ADDR_I<7> ADDR_I<6> ADDR_I<5> ADDR_I<4> ++ ADDR_I<3> ADDR_I<2> ADDR_I<1> ADDR_I<0> ADDR_N_O<7> ADDR_N_O<6> ADDR_N_O<5> ++ ADDR_N_O<4> ADDR_N_O<3> ADDR_N_O<2> ADDR_N_O<1> ADDR_N_O<0> BIST_ADDR_I<7> ++ BIST_ADDR_I<6> BIST_ADDR_I<5> BIST_ADDR_I<4> BIST_ADDR_I<3> BIST_ADDR_I<2> ++ BIST_ADDR_I<1> BIST_ADDR_I<0> BIST_EN_I VDD VSS +XINV<7> q_int<7> qn_int<7> VDD VSS / RSC_IHPSG13_CINVX2 +XINV<6> q_int<6> qn_int<6> VDD VSS / RSC_IHPSG13_CINVX2 +XINV<5> q_int<5> qn_int<5> VDD VSS / RSC_IHPSG13_CINVX2 +XINV<4> q_int<4> qn_int<4> VDD VSS / RSC_IHPSG13_CINVX2 +XINV<3> q_int<3> qn_int<3> VDD VSS / RSC_IHPSG13_CINVX2 +XINV<2> q_int<2> qn_int<2> VDD VSS / RSC_IHPSG13_CINVX2 +XINV<1> q_int<1> qn_int<1> VDD VSS / RSC_IHPSG13_CINVX2 +XINV<0> q_int<0> qn_int<0> VDD VSS / RSC_IHPSG13_CINVX2 +XDRV<7> qn_int<7> ADDR_N_O<7> VDD VSS / RSC_IHPSG13_CINVX8 +XDRV<6> qn_int<6> ADDR_N_O<6> VDD VSS / RSC_IHPSG13_CINVX8 +XDRV<5> qn_int<5> ADDR_N_O<5> VDD VSS / RSC_IHPSG13_CINVX8 +XDRV<4> qn_int<4> ADDR_N_O<4> VDD VSS / RSC_IHPSG13_CINVX8 +XDRV<3> qn_int<3> ADDR_N_O<3> VDD VSS / RSC_IHPSG13_CINVX8 +XDRV<2> qn_int<2> ADDR_N_O<2> VDD VSS / RSC_IHPSG13_CINVX8 +XDRV<1> qn_int<1> ADDR_N_O<1> VDD VSS / RSC_IHPSG13_CINVX8 +XDRV<0> qn_int<0> ADDR_N_O<0> VDD VSS / RSC_IHPSG13_CINVX8 +XDFF<7> BIST_EN_I BIST_ADDR_I<7> ACLK_N_I ADDR_I<7> q_int<7> net2<0> VDD ++ VSS / RSC_IHPSG13_DFNQMX2IX1 +XDFF<6> BIST_EN_I BIST_ADDR_I<6> ACLK_N_I ADDR_I<6> q_int<6> net2<1> VDD ++ VSS / RSC_IHPSG13_DFNQMX2IX1 +XDFF<5> BIST_EN_I BIST_ADDR_I<5> ACLK_N_I ADDR_I<5> q_int<5> net2<2> VDD ++ VSS / RSC_IHPSG13_DFNQMX2IX1 +XDFF<4> BIST_EN_I BIST_ADDR_I<4> ACLK_N_I ADDR_I<4> q_int<4> net2<3> VDD ++ VSS / RSC_IHPSG13_DFNQMX2IX1 +XDFF<3> BIST_EN_I BIST_ADDR_I<3> ACLK_N_I ADDR_I<3> q_int<3> net2<4> VDD ++ VSS / RSC_IHPSG13_DFNQMX2IX1 +XDFF<2> BIST_EN_I BIST_ADDR_I<2> ACLK_N_I ADDR_I<2> q_int<2> net2<5> VDD ++ VSS / RSC_IHPSG13_DFNQMX2IX1 +XDFF<1> BIST_EN_I BIST_ADDR_I<1> ACLK_N_I ADDR_I<1> q_int<1> net2<6> VDD ++ VSS / RSC_IHPSG13_DFNQMX2IX1 +XDFF<0> BIST_EN_I BIST_ADDR_I<0> ACLK_N_I ADDR_I<0> q_int<0> net2<7> VDD ++ VSS / RSC_IHPSG13_DFNQMX2IX1 +XI11<4> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI11<3> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI11<2> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI11<1> VDD VSS / RSC_IHPSG13_FILLCAP8 +.ENDS + +.SUBCKT RM_IHPSG13_1024x32_c2_1P_ROWDEC9 ADDR_N_I<8> ADDR_N_I<7> ADDR_N_I<6> ADDR_N_I<5> ++ ADDR_N_I<4> ADDR_N_I<3> ADDR_N_I<2> ADDR_N_I<1> ADDR_N_I<0> CS_I ECLK_I ++ WL_O<511> WL_O<510> WL_O<509> WL_O<508> WL_O<507> WL_O<506> WL_O<505> ++ WL_O<504> WL_O<503> WL_O<502> WL_O<501> WL_O<500> WL_O<499> WL_O<498> ++ WL_O<497> WL_O<496> WL_O<495> WL_O<494> WL_O<493> WL_O<492> WL_O<491> ++ WL_O<490> WL_O<489> WL_O<488> WL_O<487> WL_O<486> WL_O<485> WL_O<484> ++ WL_O<483> WL_O<482> WL_O<481> WL_O<480> WL_O<479> WL_O<478> WL_O<477> ++ WL_O<476> WL_O<475> WL_O<474> WL_O<473> WL_O<472> WL_O<471> WL_O<470> ++ WL_O<469> WL_O<468> WL_O<467> WL_O<466> WL_O<465> WL_O<464> WL_O<463> ++ WL_O<462> WL_O<461> WL_O<460> WL_O<459> WL_O<458> WL_O<457> WL_O<456> ++ WL_O<455> WL_O<454> WL_O<453> WL_O<452> WL_O<451> WL_O<450> WL_O<449> ++ WL_O<448> WL_O<447> WL_O<446> WL_O<445> WL_O<444> WL_O<443> WL_O<442> ++ WL_O<441> WL_O<440> WL_O<439> WL_O<438> WL_O<437> WL_O<436> WL_O<435> ++ WL_O<434> WL_O<433> WL_O<432> WL_O<431> WL_O<430> WL_O<429> WL_O<428> ++ WL_O<427> WL_O<426> WL_O<425> WL_O<424> WL_O<423> WL_O<422> WL_O<421> ++ WL_O<420> WL_O<419> WL_O<418> WL_O<417> WL_O<416> WL_O<415> WL_O<414> ++ WL_O<413> WL_O<412> WL_O<411> WL_O<410> WL_O<409> WL_O<408> WL_O<407> ++ WL_O<406> WL_O<405> WL_O<404> WL_O<403> WL_O<402> WL_O<401> WL_O<400> ++ WL_O<399> WL_O<398> WL_O<397> WL_O<396> WL_O<395> WL_O<394> WL_O<393> ++ WL_O<392> WL_O<391> WL_O<390> WL_O<389> WL_O<388> WL_O<387> WL_O<386> ++ WL_O<385> WL_O<384> WL_O<383> WL_O<382> WL_O<381> WL_O<380> WL_O<379> ++ WL_O<378> WL_O<377> WL_O<376> WL_O<375> WL_O<374> WL_O<373> WL_O<372> ++ WL_O<371> WL_O<370> WL_O<369> WL_O<368> WL_O<367> WL_O<366> WL_O<365> ++ WL_O<364> WL_O<363> WL_O<362> WL_O<361> WL_O<360> WL_O<359> WL_O<358> ++ WL_O<357> WL_O<356> WL_O<355> WL_O<354> WL_O<353> WL_O<352> WL_O<351> ++ WL_O<350> WL_O<349> WL_O<348> WL_O<347> WL_O<346> WL_O<345> WL_O<344> ++ WL_O<343> WL_O<342> WL_O<341> WL_O<340> WL_O<339> WL_O<338> WL_O<337> ++ WL_O<336> WL_O<335> WL_O<334> WL_O<333> WL_O<332> WL_O<331> WL_O<330> ++ WL_O<329> WL_O<328> WL_O<327> WL_O<326> WL_O<325> WL_O<324> WL_O<323> ++ WL_O<322> WL_O<321> WL_O<320> WL_O<319> WL_O<318> WL_O<317> WL_O<316> ++ WL_O<315> WL_O<314> WL_O<313> WL_O<312> WL_O<311> WL_O<310> WL_O<309> ++ WL_O<308> WL_O<307> WL_O<306> WL_O<305> WL_O<304> WL_O<303> WL_O<302> ++ WL_O<301> WL_O<300> WL_O<299> WL_O<298> WL_O<297> WL_O<296> WL_O<295> ++ WL_O<294> WL_O<293> WL_O<292> WL_O<291> WL_O<290> WL_O<289> WL_O<288> ++ WL_O<287> WL_O<286> WL_O<285> WL_O<284> WL_O<283> WL_O<282> WL_O<281> ++ WL_O<280> WL_O<279> WL_O<278> WL_O<277> WL_O<276> WL_O<275> WL_O<274> ++ WL_O<273> WL_O<272> WL_O<271> WL_O<270> WL_O<269> WL_O<268> WL_O<267> ++ WL_O<266> WL_O<265> WL_O<264> WL_O<263> WL_O<262> WL_O<261> WL_O<260> ++ WL_O<259> WL_O<258> WL_O<257> WL_O<256> WL_O<255> WL_O<254> WL_O<253> ++ WL_O<252> WL_O<251> WL_O<250> WL_O<249> WL_O<248> WL_O<247> WL_O<246> ++ WL_O<245> WL_O<244> WL_O<243> WL_O<242> WL_O<241> WL_O<240> WL_O<239> ++ WL_O<238> WL_O<237> WL_O<236> WL_O<235> WL_O<234> WL_O<233> WL_O<232> ++ WL_O<231> WL_O<230> WL_O<229> WL_O<228> WL_O<227> WL_O<226> WL_O<225> ++ WL_O<224> WL_O<223> WL_O<222> WL_O<221> WL_O<220> WL_O<219> WL_O<218> ++ WL_O<217> WL_O<216> WL_O<215> WL_O<214> WL_O<213> WL_O<212> WL_O<211> ++ WL_O<210> WL_O<209> WL_O<208> WL_O<207> WL_O<206> WL_O<205> WL_O<204> ++ WL_O<203> WL_O<202> WL_O<201> WL_O<200> WL_O<199> WL_O<198> WL_O<197> ++ WL_O<196> WL_O<195> WL_O<194> WL_O<193> WL_O<192> WL_O<191> WL_O<190> ++ WL_O<189> WL_O<188> WL_O<187> WL_O<186> WL_O<185> WL_O<184> WL_O<183> ++ WL_O<182> WL_O<181> WL_O<180> WL_O<179> WL_O<178> WL_O<177> WL_O<176> ++ WL_O<175> WL_O<174> WL_O<173> WL_O<172> WL_O<171> WL_O<170> WL_O<169> ++ WL_O<168> WL_O<167> WL_O<166> WL_O<165> WL_O<164> WL_O<163> WL_O<162> ++ WL_O<161> WL_O<160> WL_O<159> WL_O<158> WL_O<157> WL_O<156> WL_O<155> ++ WL_O<154> WL_O<153> WL_O<152> WL_O<151> WL_O<150> WL_O<149> WL_O<148> ++ WL_O<147> WL_O<146> WL_O<145> WL_O<144> WL_O<143> WL_O<142> WL_O<141> ++ WL_O<140> WL_O<139> WL_O<138> WL_O<137> WL_O<136> WL_O<135> WL_O<134> ++ WL_O<133> WL_O<132> WL_O<131> WL_O<130> WL_O<129> WL_O<128> WL_O<127> ++ WL_O<126> WL_O<125> WL_O<124> WL_O<123> WL_O<122> WL_O<121> WL_O<120> ++ WL_O<119> WL_O<118> WL_O<117> WL_O<116> WL_O<115> WL_O<114> WL_O<113> ++ WL_O<112> WL_O<111> WL_O<110> WL_O<109> WL_O<108> WL_O<107> WL_O<106> ++ WL_O<105> WL_O<104> WL_O<103> WL_O<102> WL_O<101> WL_O<100> WL_O<99> ++ WL_O<98> WL_O<97> WL_O<96> WL_O<95> WL_O<94> WL_O<93> WL_O<92> WL_O<91> ++ WL_O<90> WL_O<89> WL_O<88> WL_O<87> WL_O<86> WL_O<85> WL_O<84> WL_O<83> ++ WL_O<82> WL_O<81> WL_O<80> WL_O<79> WL_O<78> WL_O<77> WL_O<76> WL_O<75> ++ WL_O<74> WL_O<73> WL_O<72> WL_O<71> WL_O<70> WL_O<69> WL_O<68> WL_O<67> ++ WL_O<66> WL_O<65> WL_O<64> WL_O<63> WL_O<62> WL_O<61> WL_O<60> WL_O<59> ++ WL_O<58> WL_O<57> WL_O<56> WL_O<55> WL_O<54> WL_O<53> WL_O<52> WL_O<51> ++ WL_O<50> WL_O<49> WL_O<48> WL_O<47> WL_O<46> WL_O<45> WL_O<44> WL_O<43> ++ WL_O<42> WL_O<41> WL_O<40> WL_O<39> WL_O<38> WL_O<37> WL_O<36> WL_O<35> ++ WL_O<34> WL_O<33> WL_O<32> WL_O<31> WL_O<30> WL_O<29> WL_O<28> WL_O<27> ++ WL_O<26> WL_O<25> WL_O<24> WL_O<23> WL_O<22> WL_O<21> WL_O<20> WL_O<19> ++ WL_O<18> WL_O<17> WL_O<16> WL_O<15> WL_O<14> WL_O<13> WL_O<12> WL_O<11> ++ WL_O<10> WL_O<9> WL_O<8> WL_O<7> WL_O<6> WL_O<5> WL_O<4> WL_O<3> WL_O<2> ++ WL_O<1> WL_O<0> VDD VSS +XL2<172> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<171> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<170> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<169> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<168> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<167> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<166> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<165> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<164> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<163> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<162> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<161> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<160> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<159> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<158> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<157> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<156> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<155> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<154> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<153> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<152> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<151> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<150> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<149> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<148> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<147> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<146> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<145> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<144> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<143> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<142> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<141> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<140> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<139> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<138> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<137> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<136> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<135> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<134> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<133> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<132> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<131> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<130> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<129> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<128> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<127> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<126> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<125> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<124> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<123> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<122> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<121> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<120> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<119> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<118> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<117> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<116> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<115> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<114> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<113> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<112> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<111> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<110> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<109> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<108> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<107> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<106> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<105> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<104> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<103> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<102> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<101> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<100> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<99> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<98> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<97> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<96> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<95> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<94> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<93> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<92> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<91> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<90> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<89> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<88> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<87> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<86> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<85> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<84> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<83> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<82> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<81> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<80> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<79> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<78> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<77> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<76> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<75> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<74> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<73> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<72> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<71> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<70> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<69> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<68> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<67> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<66> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<65> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<64> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<63> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<62> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<61> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<60> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<59> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<58> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<57> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<56> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<55> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<54> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<53> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<52> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<51> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<50> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<49> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<48> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<47> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<46> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<45> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<44> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<43> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<42> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<41> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<40> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<39> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<38> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<37> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<36> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<35> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<34> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<33> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<32> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<31> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<30> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<29> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<28> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<27> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<26> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<25> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<24> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<23> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<22> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<21> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<20> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<19> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<18> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<17> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<16> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<15> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<14> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<13> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<12> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<11> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<10> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<9> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<8> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<7> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<6> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<5> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<4> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<3> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<2> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<1> VDD VSS / RSC_IHPSG13_FILLCAP8 +XDEC11<9> ADDR_N_I<7> ADDR_N_I<6> CS04<1> CS02<7> VDD VSS / ++ RM_IHPSG13_1024x32_c2_1P_DEC03 +XDEC11<8> ADDR_N_I<7> ADDR_N_I<6> CS04<0> CS02<3> VDD VSS / ++ RM_IHPSG13_1024x32_c2_1P_DEC03 +XDEC11<7> ADDR_N_I<5> ADDR_N_I<4> CS02<7> CS00<31> VDD VSS / ++ RM_IHPSG13_1024x32_c2_1P_DEC03 +XDEC11<6> ADDR_N_I<5> ADDR_N_I<4> CS02<6> CS00<27> VDD VSS / ++ RM_IHPSG13_1024x32_c2_1P_DEC03 +XDEC11<5> ADDR_N_I<5> ADDR_N_I<4> CS02<5> CS00<23> VDD VSS / ++ RM_IHPSG13_1024x32_c2_1P_DEC03 +XDEC11<4> ADDR_N_I<5> ADDR_N_I<4> CS02<4> CS00<19> VDD VSS / ++ RM_IHPSG13_1024x32_c2_1P_DEC03 +XDEC11<3> ADDR_N_I<5> ADDR_N_I<4> CS02<3> CS00<15> VDD VSS / ++ RM_IHPSG13_1024x32_c2_1P_DEC03 +XDEC11<2> ADDR_N_I<5> ADDR_N_I<4> CS02<2> CS00<11> VDD VSS / ++ RM_IHPSG13_1024x32_c2_1P_DEC03 +XDEC11<1> ADDR_N_I<5> ADDR_N_I<4> CS02<1> CS00<7> VDD VSS / ++ RM_IHPSG13_1024x32_c2_1P_DEC03 +XDEC11<0> ADDR_N_I<5> ADDR_N_I<4> CS02<0> CS00<3> VDD VSS / ++ RM_IHPSG13_1024x32_c2_1P_DEC03 +XDEC00<10> ADDR_N_I<9> ADDR_N_I<8> CS_I CS04<0> VDD VSS / ++ RM_IHPSG13_1024x32_c2_1P_DEC00 +XDEC00<9> ADDR_N_I<7> ADDR_N_I<6> CS04<1> CS02<4> VDD VSS / ++ RM_IHPSG13_1024x32_c2_1P_DEC00 +XDEC00<8> ADDR_N_I<7> ADDR_N_I<6> CS04<0> CS02<0> VDD VSS / ++ RM_IHPSG13_1024x32_c2_1P_DEC00 +XDEC00<7> ADDR_N_I<5> ADDR_N_I<4> CS02<7> CS00<28> VDD VSS / ++ RM_IHPSG13_1024x32_c2_1P_DEC00 +XDEC00<6> ADDR_N_I<5> ADDR_N_I<4> CS02<6> CS00<24> VDD VSS / ++ RM_IHPSG13_1024x32_c2_1P_DEC00 +XDEC00<5> ADDR_N_I<5> ADDR_N_I<4> CS02<5> CS00<20> VDD VSS / ++ RM_IHPSG13_1024x32_c2_1P_DEC00 +XDEC00<4> ADDR_N_I<5> ADDR_N_I<4> CS02<4> CS00<16> VDD VSS / ++ RM_IHPSG13_1024x32_c2_1P_DEC00 +XDEC00<3> ADDR_N_I<5> ADDR_N_I<4> CS02<3> CS00<12> VDD VSS / ++ RM_IHPSG13_1024x32_c2_1P_DEC00 +XDEC00<2> ADDR_N_I<5> ADDR_N_I<4> CS02<2> CS00<8> VDD VSS / ++ RM_IHPSG13_1024x32_c2_1P_DEC00 +XDEC00<1> ADDR_N_I<5> ADDR_N_I<4> CS02<1> CS00<4> VDD VSS / ++ RM_IHPSG13_1024x32_c2_1P_DEC00 +XDEC00<0> ADDR_N_I<5> ADDR_N_I<4> CS02<0> CS00<0> VDD VSS / ++ RM_IHPSG13_1024x32_c2_1P_DEC00 +XSEL<31> ADDR_N_I<3> ADDR_N_I<2> ADDR_N_I<1> ADDR_N_I<0> CS00<31> ECLK_H<31> ++ ECLK_H<32> ECLK_B<31> ECLK_B<32> WL_O<511> WL_O<510> WL_O<509> WL_O<508> ++ WL_O<507> WL_O<506> WL_O<505> WL_O<504> WL_O<503> WL_O<502> WL_O<501> ++ WL_O<500> WL_O<499> WL_O<498> WL_O<497> WL_O<496> VDD VSS / ++ RM_IHPSG13_1024x32_c2_1P_DEC04 +XSEL<30> ADDR_N_I<3> ADDR_N_I<2> ADDR_N_I<1> ADDR_N_I<0> CS00<30> ECLK_H<30> ++ ECLK_H<31> ECLK_B<30> ECLK_B<31> WL_O<495> WL_O<494> WL_O<493> WL_O<492> ++ WL_O<491> WL_O<490> WL_O<489> WL_O<488> WL_O<487> WL_O<486> WL_O<485> ++ WL_O<484> WL_O<483> WL_O<482> WL_O<481> WL_O<480> VDD VSS / ++ RM_IHPSG13_1024x32_c2_1P_DEC04 +XSEL<29> ADDR_N_I<3> ADDR_N_I<2> ADDR_N_I<1> ADDR_N_I<0> CS00<29> ECLK_H<29> ++ ECLK_H<30> ECLK_B<29> ECLK_B<30> WL_O<479> WL_O<478> WL_O<477> WL_O<476> ++ WL_O<475> WL_O<474> WL_O<473> WL_O<472> WL_O<471> WL_O<470> WL_O<469> ++ WL_O<468> WL_O<467> WL_O<466> WL_O<465> WL_O<464> VDD VSS / ++ RM_IHPSG13_1024x32_c2_1P_DEC04 +XSEL<28> ADDR_N_I<3> ADDR_N_I<2> ADDR_N_I<1> ADDR_N_I<0> CS00<28> ECLK_H<28> ++ ECLK_H<29> ECLK_B<28> ECLK_B<29> WL_O<463> WL_O<462> WL_O<461> WL_O<460> ++ WL_O<459> WL_O<458> WL_O<457> WL_O<456> WL_O<455> WL_O<454> WL_O<453> ++ WL_O<452> WL_O<451> WL_O<450> WL_O<449> WL_O<448> VDD VSS / ++ RM_IHPSG13_1024x32_c2_1P_DEC04 +XSEL<27> ADDR_N_I<3> ADDR_N_I<2> ADDR_N_I<1> ADDR_N_I<0> CS00<27> ECLK_H<27> ++ ECLK_H<28> ECLK_B<27> ECLK_B<28> WL_O<447> WL_O<446> WL_O<445> WL_O<444> ++ WL_O<443> WL_O<442> WL_O<441> WL_O<440> WL_O<439> WL_O<438> WL_O<437> ++ WL_O<436> WL_O<435> WL_O<434> WL_O<433> WL_O<432> VDD VSS / ++ RM_IHPSG13_1024x32_c2_1P_DEC04 +XSEL<26> ADDR_N_I<3> ADDR_N_I<2> ADDR_N_I<1> ADDR_N_I<0> CS00<26> ECLK_H<26> ++ ECLK_H<27> ECLK_B<26> ECLK_B<27> WL_O<431> WL_O<430> WL_O<429> WL_O<428> ++ WL_O<427> WL_O<426> WL_O<425> WL_O<424> WL_O<423> WL_O<422> WL_O<421> ++ WL_O<420> WL_O<419> WL_O<418> WL_O<417> WL_O<416> VDD VSS / ++ RM_IHPSG13_1024x32_c2_1P_DEC04 +XSEL<25> ADDR_N_I<3> ADDR_N_I<2> ADDR_N_I<1> ADDR_N_I<0> CS00<25> ECLK_H<25> ++ ECLK_H<26> ECLK_B<25> ECLK_B<26> WL_O<415> WL_O<414> WL_O<413> WL_O<412> ++ WL_O<411> WL_O<410> WL_O<409> WL_O<408> WL_O<407> WL_O<406> WL_O<405> ++ WL_O<404> WL_O<403> WL_O<402> WL_O<401> WL_O<400> VDD VSS / ++ RM_IHPSG13_1024x32_c2_1P_DEC04 +XSEL<24> ADDR_N_I<3> ADDR_N_I<2> ADDR_N_I<1> ADDR_N_I<0> CS00<24> ECLK_H<24> ++ ECLK_H<25> ECLK_B<24> ECLK_B<25> WL_O<399> WL_O<398> WL_O<397> WL_O<396> ++ WL_O<395> WL_O<394> WL_O<393> WL_O<392> WL_O<391> WL_O<390> WL_O<389> ++ WL_O<388> WL_O<387> WL_O<386> WL_O<385> WL_O<384> VDD VSS / ++ RM_IHPSG13_1024x32_c2_1P_DEC04 +XSEL<23> ADDR_N_I<3> ADDR_N_I<2> ADDR_N_I<1> ADDR_N_I<0> CS00<23> ECLK_H<23> ++ ECLK_H<24> ECLK_B<23> ECLK_B<24> WL_O<383> WL_O<382> WL_O<381> WL_O<380> ++ WL_O<379> WL_O<378> WL_O<377> WL_O<376> WL_O<375> WL_O<374> WL_O<373> ++ WL_O<372> WL_O<371> WL_O<370> WL_O<369> WL_O<368> VDD VSS / ++ RM_IHPSG13_1024x32_c2_1P_DEC04 +XSEL<22> ADDR_N_I<3> ADDR_N_I<2> ADDR_N_I<1> ADDR_N_I<0> CS00<22> ECLK_H<22> ++ ECLK_H<23> ECLK_B<22> ECLK_B<23> WL_O<367> WL_O<366> WL_O<365> WL_O<364> ++ WL_O<363> WL_O<362> WL_O<361> WL_O<360> WL_O<359> WL_O<358> WL_O<357> ++ WL_O<356> WL_O<355> WL_O<354> WL_O<353> WL_O<352> VDD VSS / ++ RM_IHPSG13_1024x32_c2_1P_DEC04 +XSEL<21> ADDR_N_I<3> ADDR_N_I<2> ADDR_N_I<1> ADDR_N_I<0> CS00<21> ECLK_H<21> ++ ECLK_H<22> ECLK_B<21> ECLK_B<22> WL_O<351> WL_O<350> WL_O<349> WL_O<348> ++ WL_O<347> WL_O<346> WL_O<345> WL_O<344> WL_O<343> WL_O<342> WL_O<341> ++ WL_O<340> WL_O<339> WL_O<338> WL_O<337> WL_O<336> VDD VSS / ++ RM_IHPSG13_1024x32_c2_1P_DEC04 +XSEL<20> ADDR_N_I<3> ADDR_N_I<2> ADDR_N_I<1> ADDR_N_I<0> CS00<20> ECLK_H<20> ++ ECLK_H<21> ECLK_B<20> ECLK_B<21> WL_O<335> WL_O<334> WL_O<333> WL_O<332> ++ WL_O<331> WL_O<330> WL_O<329> WL_O<328> WL_O<327> WL_O<326> WL_O<325> ++ WL_O<324> WL_O<323> WL_O<322> WL_O<321> WL_O<320> VDD VSS / ++ RM_IHPSG13_1024x32_c2_1P_DEC04 +XSEL<19> ADDR_N_I<3> ADDR_N_I<2> ADDR_N_I<1> ADDR_N_I<0> CS00<19> ECLK_H<19> ++ ECLK_H<20> ECLK_B<19> ECLK_B<20> WL_O<319> WL_O<318> WL_O<317> WL_O<316> ++ WL_O<315> WL_O<314> WL_O<313> WL_O<312> WL_O<311> WL_O<310> WL_O<309> ++ WL_O<308> WL_O<307> WL_O<306> WL_O<305> WL_O<304> VDD VSS / ++ RM_IHPSG13_1024x32_c2_1P_DEC04 +XSEL<18> ADDR_N_I<3> ADDR_N_I<2> ADDR_N_I<1> ADDR_N_I<0> CS00<18> ECLK_H<18> ++ ECLK_H<19> ECLK_B<18> ECLK_B<19> WL_O<303> WL_O<302> WL_O<301> WL_O<300> ++ WL_O<299> WL_O<298> WL_O<297> WL_O<296> WL_O<295> WL_O<294> WL_O<293> ++ WL_O<292> WL_O<291> WL_O<290> WL_O<289> WL_O<288> VDD VSS / ++ RM_IHPSG13_1024x32_c2_1P_DEC04 +XSEL<17> ADDR_N_I<3> ADDR_N_I<2> ADDR_N_I<1> ADDR_N_I<0> CS00<17> ECLK_H<17> ++ ECLK_H<18> ECLK_B<17> ECLK_B<18> WL_O<287> WL_O<286> WL_O<285> WL_O<284> ++ WL_O<283> WL_O<282> WL_O<281> WL_O<280> WL_O<279> WL_O<278> WL_O<277> ++ WL_O<276> WL_O<275> WL_O<274> WL_O<273> WL_O<272> VDD VSS / ++ RM_IHPSG13_1024x32_c2_1P_DEC04 +XSEL<16> ADDR_N_I<3> ADDR_N_I<2> ADDR_N_I<1> ADDR_N_I<0> CS00<16> ECLK_H<16> ++ ECLK_H<17> ECLK_B<16> ECLK_B<17> WL_O<271> WL_O<270> WL_O<269> WL_O<268> ++ WL_O<267> WL_O<266> WL_O<265> WL_O<264> WL_O<263> WL_O<262> WL_O<261> ++ WL_O<260> WL_O<259> WL_O<258> WL_O<257> WL_O<256> VDD VSS / ++ RM_IHPSG13_1024x32_c2_1P_DEC04 +XSEL<15> ADDR_N_I<3> ADDR_N_I<2> ADDR_N_I<1> ADDR_N_I<0> CS00<15> ECLK_H<15> ++ ECLK_H<16> ECLK_B<15> ECLK_B<16> WL_O<255> WL_O<254> WL_O<253> WL_O<252> ++ WL_O<251> WL_O<250> WL_O<249> WL_O<248> WL_O<247> WL_O<246> WL_O<245> ++ WL_O<244> WL_O<243> WL_O<242> WL_O<241> WL_O<240> VDD VSS / ++ RM_IHPSG13_1024x32_c2_1P_DEC04 +XSEL<14> ADDR_N_I<3> ADDR_N_I<2> ADDR_N_I<1> ADDR_N_I<0> CS00<14> ECLK_H<14> ++ ECLK_H<15> ECLK_B<14> ECLK_B<15> WL_O<239> WL_O<238> WL_O<237> WL_O<236> ++ WL_O<235> WL_O<234> WL_O<233> WL_O<232> WL_O<231> WL_O<230> WL_O<229> ++ WL_O<228> WL_O<227> WL_O<226> WL_O<225> WL_O<224> VDD VSS / ++ RM_IHPSG13_1024x32_c2_1P_DEC04 +XSEL<13> ADDR_N_I<3> ADDR_N_I<2> ADDR_N_I<1> ADDR_N_I<0> CS00<13> ECLK_H<13> ++ ECLK_H<14> ECLK_B<13> ECLK_B<14> WL_O<223> WL_O<222> WL_O<221> WL_O<220> ++ WL_O<219> WL_O<218> WL_O<217> WL_O<216> WL_O<215> WL_O<214> WL_O<213> ++ WL_O<212> WL_O<211> WL_O<210> WL_O<209> WL_O<208> VDD VSS / ++ RM_IHPSG13_1024x32_c2_1P_DEC04 +XSEL<12> ADDR_N_I<3> ADDR_N_I<2> ADDR_N_I<1> ADDR_N_I<0> CS00<12> ECLK_H<12> ++ ECLK_H<13> ECLK_B<12> ECLK_B<13> WL_O<207> WL_O<206> WL_O<205> WL_O<204> ++ WL_O<203> WL_O<202> WL_O<201> WL_O<200> WL_O<199> WL_O<198> WL_O<197> ++ WL_O<196> WL_O<195> WL_O<194> WL_O<193> WL_O<192> VDD VSS / ++ RM_IHPSG13_1024x32_c2_1P_DEC04 +XSEL<11> ADDR_N_I<3> ADDR_N_I<2> ADDR_N_I<1> ADDR_N_I<0> CS00<11> ECLK_H<11> ++ ECLK_H<12> ECLK_B<11> ECLK_B<12> WL_O<191> WL_O<190> WL_O<189> WL_O<188> ++ WL_O<187> WL_O<186> WL_O<185> WL_O<184> WL_O<183> WL_O<182> WL_O<181> ++ WL_O<180> WL_O<179> WL_O<178> WL_O<177> WL_O<176> VDD VSS / ++ RM_IHPSG13_1024x32_c2_1P_DEC04 +XSEL<10> ADDR_N_I<3> ADDR_N_I<2> ADDR_N_I<1> ADDR_N_I<0> CS00<10> ECLK_H<10> ++ ECLK_H<11> ECLK_B<10> ECLK_B<11> WL_O<175> WL_O<174> WL_O<173> WL_O<172> ++ WL_O<171> WL_O<170> WL_O<169> WL_O<168> WL_O<167> WL_O<166> WL_O<165> ++ WL_O<164> WL_O<163> WL_O<162> WL_O<161> WL_O<160> VDD VSS / ++ RM_IHPSG13_1024x32_c2_1P_DEC04 +XSEL<9> ADDR_N_I<3> ADDR_N_I<2> ADDR_N_I<1> ADDR_N_I<0> CS00<9> ECLK_H<9> ++ ECLK_H<10> ECLK_B<9> ECLK_B<10> WL_O<159> WL_O<158> WL_O<157> WL_O<156> ++ WL_O<155> WL_O<154> WL_O<153> WL_O<152> WL_O<151> WL_O<150> WL_O<149> ++ WL_O<148> WL_O<147> WL_O<146> WL_O<145> WL_O<144> VDD VSS / ++ RM_IHPSG13_1024x32_c2_1P_DEC04 +XSEL<8> ADDR_N_I<3> ADDR_N_I<2> ADDR_N_I<1> ADDR_N_I<0> CS00<8> ECLK_H<8> ++ ECLK_H<9> ECLK_B<8> ECLK_B<9> WL_O<143> WL_O<142> WL_O<141> WL_O<140> ++ WL_O<139> WL_O<138> WL_O<137> WL_O<136> WL_O<135> WL_O<134> WL_O<133> ++ WL_O<132> WL_O<131> WL_O<130> WL_O<129> WL_O<128> VDD VSS / ++ RM_IHPSG13_1024x32_c2_1P_DEC04 +XSEL<7> ADDR_N_I<3> ADDR_N_I<2> ADDR_N_I<1> ADDR_N_I<0> CS00<7> ECLK_H<7> ++ ECLK_H<8> ECLK_B<7> ECLK_B<8> WL_O<127> WL_O<126> WL_O<125> WL_O<124> ++ WL_O<123> WL_O<122> WL_O<121> WL_O<120> WL_O<119> WL_O<118> WL_O<117> ++ WL_O<116> WL_O<115> WL_O<114> WL_O<113> WL_O<112> VDD VSS / ++ RM_IHPSG13_1024x32_c2_1P_DEC04 +XSEL<6> ADDR_N_I<3> ADDR_N_I<2> ADDR_N_I<1> ADDR_N_I<0> CS00<6> ECLK_H<6> ++ ECLK_H<7> ECLK_B<6> ECLK_B<7> WL_O<111> WL_O<110> WL_O<109> WL_O<108> ++ WL_O<107> WL_O<106> WL_O<105> WL_O<104> WL_O<103> WL_O<102> WL_O<101> ++ WL_O<100> WL_O<99> WL_O<98> WL_O<97> WL_O<96> VDD VSS / ++ RM_IHPSG13_1024x32_c2_1P_DEC04 +XSEL<5> ADDR_N_I<3> ADDR_N_I<2> ADDR_N_I<1> ADDR_N_I<0> CS00<5> ECLK_H<5> ++ ECLK_H<6> ECLK_B<5> ECLK_B<6> WL_O<95> WL_O<94> WL_O<93> WL_O<92> WL_O<91> ++ WL_O<90> WL_O<89> WL_O<88> WL_O<87> WL_O<86> WL_O<85> WL_O<84> WL_O<83> ++ WL_O<82> WL_O<81> WL_O<80> VDD VSS / RM_IHPSG13_1024x32_c2_1P_DEC04 +XSEL<4> ADDR_N_I<3> ADDR_N_I<2> ADDR_N_I<1> ADDR_N_I<0> CS00<4> ECLK_H<4> ++ ECLK_H<5> ECLK_B<4> ECLK_B<5> WL_O<79> WL_O<78> WL_O<77> WL_O<76> WL_O<75> ++ WL_O<74> WL_O<73> WL_O<72> WL_O<71> WL_O<70> WL_O<69> WL_O<68> WL_O<67> ++ WL_O<66> WL_O<65> WL_O<64> VDD VSS / RM_IHPSG13_1024x32_c2_1P_DEC04 +XSEL<3> ADDR_N_I<3> ADDR_N_I<2> ADDR_N_I<1> ADDR_N_I<0> CS00<3> ECLK_H<3> ++ ECLK_H<4> ECLK_B<3> ECLK_B<4> WL_O<63> WL_O<62> WL_O<61> WL_O<60> WL_O<59> ++ WL_O<58> WL_O<57> WL_O<56> WL_O<55> WL_O<54> WL_O<53> WL_O<52> WL_O<51> ++ WL_O<50> WL_O<49> WL_O<48> VDD VSS / RM_IHPSG13_1024x32_c2_1P_DEC04 +XSEL<2> ADDR_N_I<3> ADDR_N_I<2> ADDR_N_I<1> ADDR_N_I<0> CS00<2> ECLK_H<2> ++ ECLK_H<3> ECLK_B<2> ECLK_B<3> WL_O<47> WL_O<46> WL_O<45> WL_O<44> WL_O<43> ++ WL_O<42> WL_O<41> WL_O<40> WL_O<39> WL_O<38> WL_O<37> WL_O<36> WL_O<35> ++ WL_O<34> WL_O<33> WL_O<32> VDD VSS / RM_IHPSG13_1024x32_c2_1P_DEC04 +XSEL<1> ADDR_N_I<3> ADDR_N_I<2> ADDR_N_I<1> ADDR_N_I<0> CS00<1> ECLK_H<1> ++ ECLK_H<2> ECLK_B<1> ECLK_B<2> WL_O<31> WL_O<30> WL_O<29> WL_O<28> WL_O<27> ++ WL_O<26> WL_O<25> WL_O<24> WL_O<23> WL_O<22> WL_O<21> WL_O<20> WL_O<19> ++ WL_O<18> WL_O<17> WL_O<16> VDD VSS / RM_IHPSG13_1024x32_c2_1P_DEC04 +XSEL<0> ADDR_N_I<3> ADDR_N_I<2> ADDR_N_I<1> ADDR_N_I<0> CS00<0> ECLK_I ++ ECLK_H<1> ECLK_B<0> ECLK_B<1> WL_O<15> WL_O<14> WL_O<13> WL_O<12> WL_O<11> ++ WL_O<10> WL_O<9> WL_O<8> WL_O<7> WL_O<6> WL_O<5> WL_O<4> WL_O<3> WL_O<2> ++ WL_O<1> WL_O<0> VDD VSS / RM_IHPSG13_1024x32_c2_1P_DEC04 +XDEC01<10> ADDR_N_I<9> ADDR_N_I<8> CS_I CS04<1> VDD VSS / ++ RM_IHPSG13_1024x32_c2_1P_DEC01 +XDEC01<9> ADDR_N_I<7> ADDR_N_I<6> CS04<1> CS02<5> VDD VSS / ++ RM_IHPSG13_1024x32_c2_1P_DEC01 +XDEC01<8> ADDR_N_I<7> ADDR_N_I<6> CS04<0> CS02<1> VDD VSS / ++ RM_IHPSG13_1024x32_c2_1P_DEC01 +XDEC01<7> ADDR_N_I<5> ADDR_N_I<4> CS02<7> CS00<29> VDD VSS / ++ RM_IHPSG13_1024x32_c2_1P_DEC01 +XDEC01<6> ADDR_N_I<5> ADDR_N_I<4> CS02<6> CS00<25> VDD VSS / ++ RM_IHPSG13_1024x32_c2_1P_DEC01 +XDEC01<5> ADDR_N_I<5> ADDR_N_I<4> CS02<5> CS00<21> VDD VSS / ++ RM_IHPSG13_1024x32_c2_1P_DEC01 +XDEC01<4> ADDR_N_I<5> ADDR_N_I<4> CS02<4> CS00<17> VDD VSS / ++ RM_IHPSG13_1024x32_c2_1P_DEC01 +XDEC01<3> ADDR_N_I<5> ADDR_N_I<4> CS02<3> CS00<13> VDD VSS / ++ RM_IHPSG13_1024x32_c2_1P_DEC01 +XDEC01<2> ADDR_N_I<5> ADDR_N_I<4> CS02<2> CS00<9> VDD VSS / ++ RM_IHPSG13_1024x32_c2_1P_DEC01 +XDEC01<1> ADDR_N_I<5> ADDR_N_I<4> CS02<1> CS00<5> VDD VSS / ++ RM_IHPSG13_1024x32_c2_1P_DEC01 +XDEC01<0> ADDR_N_I<5> ADDR_N_I<4> CS02<0> CS00<1> VDD VSS / ++ RM_IHPSG13_1024x32_c2_1P_DEC01 +XDEC10<9> ADDR_N_I<7> ADDR_N_I<6> CS04<1> CS02<6> VDD VSS / ++ RM_IHPSG13_1024x32_c2_1P_DEC02 +XDEC10<8> ADDR_N_I<7> ADDR_N_I<6> CS04<0> CS02<2> VDD VSS / ++ RM_IHPSG13_1024x32_c2_1P_DEC02 +XDEC10<7> ADDR_N_I<5> ADDR_N_I<4> CS02<7> CS00<30> VDD VSS / ++ RM_IHPSG13_1024x32_c2_1P_DEC02 +XDEC10<6> ADDR_N_I<5> ADDR_N_I<4> CS02<6> CS00<26> VDD VSS / ++ RM_IHPSG13_1024x32_c2_1P_DEC02 +XDEC10<5> ADDR_N_I<5> ADDR_N_I<4> CS02<5> CS00<22> VDD VSS / ++ RM_IHPSG13_1024x32_c2_1P_DEC02 +XDEC10<4> ADDR_N_I<5> ADDR_N_I<4> CS02<4> CS00<18> VDD VSS / ++ RM_IHPSG13_1024x32_c2_1P_DEC02 +XDEC10<3> ADDR_N_I<5> ADDR_N_I<4> CS02<3> CS00<14> VDD VSS / ++ RM_IHPSG13_1024x32_c2_1P_DEC02 +XDEC10<2> ADDR_N_I<5> ADDR_N_I<4> CS02<2> CS00<10> VDD VSS / ++ RM_IHPSG13_1024x32_c2_1P_DEC02 +XDEC10<1> ADDR_N_I<5> ADDR_N_I<4> CS02<1> CS00<6> VDD VSS / ++ RM_IHPSG13_1024x32_c2_1P_DEC02 +XDEC10<0> ADDR_N_I<5> ADDR_N_I<4> CS02<0> CS00<2> VDD VSS / ++ RM_IHPSG13_1024x32_c2_1P_DEC02 +XI0 ADDR_N_I<9> VDD VSS / RSC_IHPSG13_TIEL +.ENDS +.SUBCKT RM_IHPSG13_1024x32_c2_1P_ROWREG9 ACLK_N_I ADDR_I<8> ADDR_I<7> ADDR_I<6> ADDR_I<5> ++ ADDR_I<4> ADDR_I<3> ADDR_I<2> ADDR_I<1> ADDR_I<0> ADDR_N_O<8> ADDR_N_O<7> ++ ADDR_N_O<6> ADDR_N_O<5> ADDR_N_O<4> ADDR_N_O<3> ADDR_N_O<2> ADDR_N_O<1> ++ ADDR_N_O<0> BIST_ADDR_I<8> BIST_ADDR_I<7> BIST_ADDR_I<6> BIST_ADDR_I<5> ++ BIST_ADDR_I<4> BIST_ADDR_I<3> BIST_ADDR_I<2> BIST_ADDR_I<1> BIST_ADDR_I<0> ++ BIST_EN_I VDD VSS +XINV<8> q_int<8> qn_int<8> VDD VSS / RSC_IHPSG13_CINVX2 +XINV<7> q_int<7> qn_int<7> VDD VSS / RSC_IHPSG13_CINVX2 +XINV<6> q_int<6> qn_int<6> VDD VSS / RSC_IHPSG13_CINVX2 +XINV<5> q_int<5> qn_int<5> VDD VSS / RSC_IHPSG13_CINVX2 +XINV<4> q_int<4> qn_int<4> VDD VSS / RSC_IHPSG13_CINVX2 +XINV<3> q_int<3> qn_int<3> VDD VSS / RSC_IHPSG13_CINVX2 +XINV<2> q_int<2> qn_int<2> VDD VSS / RSC_IHPSG13_CINVX2 +XINV<1> q_int<1> qn_int<1> VDD VSS / RSC_IHPSG13_CINVX2 +XINV<0> q_int<0> qn_int<0> VDD VSS / RSC_IHPSG13_CINVX2 +XDRV<8> qn_int<8> ADDR_N_O<8> VDD VSS / RSC_IHPSG13_CINVX8 +XDRV<7> qn_int<7> ADDR_N_O<7> VDD VSS / RSC_IHPSG13_CINVX8 +XDRV<6> qn_int<6> ADDR_N_O<6> VDD VSS / RSC_IHPSG13_CINVX8 +XDRV<5> qn_int<5> ADDR_N_O<5> VDD VSS / RSC_IHPSG13_CINVX8 +XDRV<4> qn_int<4> ADDR_N_O<4> VDD VSS / RSC_IHPSG13_CINVX8 +XDRV<3> qn_int<3> ADDR_N_O<3> VDD VSS / RSC_IHPSG13_CINVX8 +XDRV<2> qn_int<2> ADDR_N_O<2> VDD VSS / RSC_IHPSG13_CINVX8 +XDRV<1> qn_int<1> ADDR_N_O<1> VDD VSS / RSC_IHPSG13_CINVX8 +XDRV<0> qn_int<0> ADDR_N_O<0> VDD VSS / RSC_IHPSG13_CINVX8 +XDFF<8> BIST_EN_I BIST_ADDR_I<8> ACLK_N_I ADDR_I<8> q_int<8> net04<0> VDD ++ VSS / RSC_IHPSG13_DFNQMX2IX1 +XDFF<7> BIST_EN_I BIST_ADDR_I<7> ACLK_N_I ADDR_I<7> q_int<7> net04<1> VDD ++ VSS / RSC_IHPSG13_DFNQMX2IX1 +XDFF<6> BIST_EN_I BIST_ADDR_I<6> ACLK_N_I ADDR_I<6> q_int<6> net04<2> VDD ++ VSS / RSC_IHPSG13_DFNQMX2IX1 +XDFF<5> BIST_EN_I BIST_ADDR_I<5> ACLK_N_I ADDR_I<5> q_int<5> net04<3> VDD ++ VSS / RSC_IHPSG13_DFNQMX2IX1 +XDFF<4> BIST_EN_I BIST_ADDR_I<4> ACLK_N_I ADDR_I<4> q_int<4> net04<4> VDD ++ VSS / RSC_IHPSG13_DFNQMX2IX1 +XDFF<3> BIST_EN_I BIST_ADDR_I<3> ACLK_N_I ADDR_I<3> q_int<3> net04<5> VDD ++ VSS / RSC_IHPSG13_DFNQMX2IX1 +XDFF<2> BIST_EN_I BIST_ADDR_I<2> ACLK_N_I ADDR_I<2> q_int<2> net04<6> VDD ++ VSS / RSC_IHPSG13_DFNQMX2IX1 +XDFF<1> BIST_EN_I BIST_ADDR_I<1> ACLK_N_I ADDR_I<1> q_int<1> net04<7> VDD ++ VSS / RSC_IHPSG13_DFNQMX2IX1 +XDFF<0> BIST_EN_I BIST_ADDR_I<0> ACLK_N_I ADDR_I<0> q_int<0> net04<8> VDD ++ VSS / RSC_IHPSG13_DFNQMX2IX1 +.ENDS + +.SUBCKT RM_IHPSG13_1024x32_c2_1P_ROWDEC7 ADDR_N_I<6> ADDR_N_I<5> ADDR_N_I<4> ADDR_N_I<3> ++ ADDR_N_I<2> ADDR_N_I<1> ADDR_N_I<0> CS_I ECLK_I WL_O<127> WL_O<126> ++ WL_O<125> WL_O<124> WL_O<123> WL_O<122> WL_O<121> WL_O<120> WL_O<119> ++ WL_O<118> WL_O<117> WL_O<116> WL_O<115> WL_O<114> WL_O<113> WL_O<112> ++ WL_O<111> WL_O<110> WL_O<109> WL_O<108> WL_O<107> WL_O<106> WL_O<105> ++ WL_O<104> WL_O<103> WL_O<102> WL_O<101> WL_O<100> WL_O<99> WL_O<98> WL_O<97> ++ WL_O<96> WL_O<95> WL_O<94> WL_O<93> WL_O<92> WL_O<91> WL_O<90> WL_O<89> ++ WL_O<88> WL_O<87> WL_O<86> WL_O<85> WL_O<84> WL_O<83> WL_O<82> WL_O<81> ++ WL_O<80> WL_O<79> WL_O<78> WL_O<77> WL_O<76> WL_O<75> WL_O<74> WL_O<73> ++ WL_O<72> WL_O<71> WL_O<70> WL_O<69> WL_O<68> WL_O<67> WL_O<66> WL_O<65> ++ WL_O<64> WL_O<63> WL_O<62> WL_O<61> WL_O<60> WL_O<59> WL_O<58> WL_O<57> ++ WL_O<56> WL_O<55> WL_O<54> WL_O<53> WL_O<52> WL_O<51> WL_O<50> WL_O<49> ++ WL_O<48> WL_O<47> WL_O<46> WL_O<45> WL_O<44> WL_O<43> WL_O<42> WL_O<41> ++ WL_O<40> WL_O<39> WL_O<38> WL_O<37> WL_O<36> WL_O<35> WL_O<34> WL_O<33> ++ WL_O<32> WL_O<31> WL_O<30> WL_O<29> WL_O<28> WL_O<27> WL_O<26> WL_O<25> ++ WL_O<24> WL_O<23> WL_O<22> WL_O<21> WL_O<20> WL_O<19> WL_O<18> WL_O<17> ++ WL_O<16> WL_O<15> WL_O<14> WL_O<13> WL_O<12> WL_O<11> WL_O<10> WL_O<9> ++ WL_O<8> WL_O<7> WL_O<6> WL_O<5> WL_O<4> WL_O<3> WL_O<2> WL_O<1> WL_O<0> ++ VDD VSS +XDEC11<1> ADDR_N_I<5> ADDR_N_I<4> CS04<1> CS00<7> VDD VSS / ++ RM_IHPSG13_1024x32_c2_1P_DEC03 +XDEC11<0> ADDR_N_I<5> ADDR_N_I<4> CS04<0> CS00<3> VDD VSS / ++ RM_IHPSG13_1024x32_c2_1P_DEC03 +XDEC10<1> ADDR_N_I<5> ADDR_N_I<4> CS04<1> CS00<6> VDD VSS / ++ RM_IHPSG13_1024x32_c2_1P_DEC02 +XDEC10<0> ADDR_N_I<5> ADDR_N_I<4> CS04<0> CS00<2> VDD VSS / ++ RM_IHPSG13_1024x32_c2_1P_DEC02 +XSEL<7> ADDR_N_I<3> ADDR_N_I<2> ADDR_N_I<1> ADDR_N_I<0> CS00<7> ECLK_H<7> ++ ECLK_H<8> ECLK_B<7> ECLK_B<8> WL_O<127> WL_O<126> WL_O<125> WL_O<124> ++ WL_O<123> WL_O<122> WL_O<121> WL_O<120> WL_O<119> WL_O<118> WL_O<117> ++ WL_O<116> WL_O<115> WL_O<114> WL_O<113> WL_O<112> VDD VSS / ++ RM_IHPSG13_1024x32_c2_1P_DEC04 +XSEL<6> ADDR_N_I<3> ADDR_N_I<2> ADDR_N_I<1> ADDR_N_I<0> CS00<6> ECLK_H<6> ++ ECLK_H<7> ECLK_B<6> ECLK_B<7> WL_O<111> WL_O<110> WL_O<109> WL_O<108> ++ WL_O<107> WL_O<106> WL_O<105> WL_O<104> WL_O<103> WL_O<102> WL_O<101> ++ WL_O<100> WL_O<99> WL_O<98> WL_O<97> WL_O<96> VDD VSS / ++ RM_IHPSG13_1024x32_c2_1P_DEC04 +XSEL<5> ADDR_N_I<3> ADDR_N_I<2> ADDR_N_I<1> ADDR_N_I<0> CS00<5> ECLK_H<5> ++ ECLK_H<6> ECLK_B<5> ECLK_B<6> WL_O<95> WL_O<94> WL_O<93> WL_O<92> WL_O<91> ++ WL_O<90> WL_O<89> WL_O<88> WL_O<87> WL_O<86> WL_O<85> WL_O<84> WL_O<83> ++ WL_O<82> WL_O<81> WL_O<80> VDD VSS / RM_IHPSG13_1024x32_c2_1P_DEC04 +XSEL<4> ADDR_N_I<3> ADDR_N_I<2> ADDR_N_I<1> ADDR_N_I<0> CS00<4> ECLK_H<4> ++ ECLK_H<5> ECLK_B<4> ECLK_B<5> WL_O<79> WL_O<78> WL_O<77> WL_O<76> WL_O<75> ++ WL_O<74> WL_O<73> WL_O<72> WL_O<71> WL_O<70> WL_O<69> WL_O<68> WL_O<67> ++ WL_O<66> WL_O<65> WL_O<64> VDD VSS / RM_IHPSG13_1024x32_c2_1P_DEC04 +XSEL<3> ADDR_N_I<3> ADDR_N_I<2> ADDR_N_I<1> ADDR_N_I<0> CS00<3> ECLK_H<3> ++ ECLK_H<4> ECLK_B<3> ECLK_B<4> WL_O<63> WL_O<62> WL_O<61> WL_O<60> WL_O<59> ++ WL_O<58> WL_O<57> WL_O<56> WL_O<55> WL_O<54> WL_O<53> WL_O<52> WL_O<51> ++ WL_O<50> WL_O<49> WL_O<48> VDD VSS / RM_IHPSG13_1024x32_c2_1P_DEC04 +XSEL<2> ADDR_N_I<3> ADDR_N_I<2> ADDR_N_I<1> ADDR_N_I<0> CS00<2> ECLK_H<2> ++ ECLK_H<3> ECLK_B<2> ECLK_B<3> WL_O<47> WL_O<46> WL_O<45> WL_O<44> WL_O<43> ++ WL_O<42> WL_O<41> WL_O<40> WL_O<39> WL_O<38> WL_O<37> WL_O<36> WL_O<35> ++ WL_O<34> WL_O<33> WL_O<32> VDD VSS / RM_IHPSG13_1024x32_c2_1P_DEC04 +XSEL<1> ADDR_N_I<3> ADDR_N_I<2> ADDR_N_I<1> ADDR_N_I<0> CS00<1> ECLK_H<1> ++ ECLK_H<2> ECLK_B<1> ECLK_B<2> WL_O<31> WL_O<30> WL_O<29> WL_O<28> WL_O<27> ++ WL_O<26> WL_O<25> WL_O<24> WL_O<23> WL_O<22> WL_O<21> WL_O<20> WL_O<19> ++ WL_O<18> WL_O<17> WL_O<16> VDD VSS / RM_IHPSG13_1024x32_c2_1P_DEC04 +XSEL<0> ADDR_N_I<3> ADDR_N_I<2> ADDR_N_I<1> ADDR_N_I<0> CS00<0> ECLK_I ++ ECLK_H<1> ECLK_B<0> ECLK_B<1> WL_O<15> WL_O<14> WL_O<13> WL_O<12> WL_O<11> ++ WL_O<10> WL_O<9> WL_O<8> WL_O<7> WL_O<6> WL_O<5> WL_O<4> WL_O<3> WL_O<2> ++ WL_O<1> WL_O<0> VDD VSS / RM_IHPSG13_1024x32_c2_1P_DEC04 +XDEC00<2> ADDR_N_I<7> ADDR_N_I<6> CS_I CS04<0> VDD VSS / ++ RM_IHPSG13_1024x32_c2_1P_DEC00 +XDEC00<1> ADDR_N_I<5> ADDR_N_I<4> CS04<1> CS00<4> VDD VSS / ++ RM_IHPSG13_1024x32_c2_1P_DEC00 +XDEC00<0> ADDR_N_I<5> ADDR_N_I<4> CS04<0> CS00<0> VDD VSS / ++ RM_IHPSG13_1024x32_c2_1P_DEC00 +XDEC01<2> ADDR_N_I<7> ADDR_N_I<6> CS_I CS04<1> VDD VSS / ++ RM_IHPSG13_1024x32_c2_1P_DEC01 +XDEC01<1> ADDR_N_I<5> ADDR_N_I<4> CS04<1> CS00<5> VDD VSS / ++ RM_IHPSG13_1024x32_c2_1P_DEC01 +XDEC01<0> ADDR_N_I<5> ADDR_N_I<4> CS04<0> CS00<1> VDD VSS / ++ RM_IHPSG13_1024x32_c2_1P_DEC01 +XL2<44> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<43> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<42> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<41> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<40> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<39> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<38> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<37> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<36> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<35> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<34> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<33> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<32> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<31> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<30> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<29> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<28> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<27> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<26> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<25> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<24> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<23> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<22> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<21> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<20> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<19> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<18> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<17> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<16> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<15> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<14> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<13> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<12> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<11> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<10> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<9> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<8> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<7> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<6> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<5> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<4> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<3> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<2> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<1> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI0 ADDR_N_I<7> VDD VSS / RSC_IHPSG13_TIEL +.ENDS +.SUBCKT RM_IHPSG13_1024x32_c2_1P_ROWREG7 ACLK_N_I ADDR_I<6> ADDR_I<5> ADDR_I<4> ADDR_I<3> ++ ADDR_I<2> ADDR_I<1> ADDR_I<0> ADDR_N_O<6> ADDR_N_O<5> ADDR_N_O<4> ++ ADDR_N_O<3> ADDR_N_O<2> ADDR_N_O<1> ADDR_N_O<0> BIST_ADDR_I<6> ++ BIST_ADDR_I<5> BIST_ADDR_I<4> BIST_ADDR_I<3> BIST_ADDR_I<2> BIST_ADDR_I<1> ++ BIST_ADDR_I<0> BIST_EN_I VDD VSS +XINV<6> q_int<6> qn_int<6> VDD VSS / RSC_IHPSG13_CINVX2 +XINV<5> q_int<5> qn_int<5> VDD VSS / RSC_IHPSG13_CINVX2 +XINV<4> q_int<4> qn_int<4> VDD VSS / RSC_IHPSG13_CINVX2 +XINV<3> q_int<3> qn_int<3> VDD VSS / RSC_IHPSG13_CINVX2 +XINV<2> q_int<2> qn_int<2> VDD VSS / RSC_IHPSG13_CINVX2 +XINV<1> q_int<1> qn_int<1> VDD VSS / RSC_IHPSG13_CINVX2 +XINV<0> q_int<0> qn_int<0> VDD VSS / RSC_IHPSG13_CINVX2 +XDRV<6> qn_int<6> ADDR_N_O<6> VDD VSS / RSC_IHPSG13_CINVX8 +XDRV<5> qn_int<5> ADDR_N_O<5> VDD VSS / RSC_IHPSG13_CINVX8 +XDRV<4> qn_int<4> ADDR_N_O<4> VDD VSS / RSC_IHPSG13_CINVX8 +XDRV<3> qn_int<3> ADDR_N_O<3> VDD VSS / RSC_IHPSG13_CINVX8 +XDRV<2> qn_int<2> ADDR_N_O<2> VDD VSS / RSC_IHPSG13_CINVX8 +XDRV<1> qn_int<1> ADDR_N_O<1> VDD VSS / RSC_IHPSG13_CINVX8 +XDRV<0> qn_int<0> ADDR_N_O<0> VDD VSS / RSC_IHPSG13_CINVX8 +XDFF<6> BIST_EN_I BIST_ADDR_I<6> ACLK_N_I ADDR_I<6> q_int<6> net2<0> VDD ++ VSS / RSC_IHPSG13_DFNQMX2IX1 +XDFF<5> BIST_EN_I BIST_ADDR_I<5> ACLK_N_I ADDR_I<5> q_int<5> net2<1> VDD ++ VSS / RSC_IHPSG13_DFNQMX2IX1 +XDFF<4> BIST_EN_I BIST_ADDR_I<4> ACLK_N_I ADDR_I<4> q_int<4> net2<2> VDD ++ VSS / RSC_IHPSG13_DFNQMX2IX1 +XDFF<3> BIST_EN_I BIST_ADDR_I<3> ACLK_N_I ADDR_I<3> q_int<3> net2<3> VDD ++ VSS / RSC_IHPSG13_DFNQMX2IX1 +XDFF<2> BIST_EN_I BIST_ADDR_I<2> ACLK_N_I ADDR_I<2> q_int<2> net2<4> VDD ++ VSS / RSC_IHPSG13_DFNQMX2IX1 +XDFF<1> BIST_EN_I BIST_ADDR_I<1> ACLK_N_I ADDR_I<1> q_int<1> net2<5> VDD ++ VSS / RSC_IHPSG13_DFNQMX2IX1 +XDFF<0> BIST_EN_I BIST_ADDR_I<0> ACLK_N_I ADDR_I<0> q_int<0> net2<6> VDD ++ VSS / RSC_IHPSG13_DFNQMX2IX1 +XI11<8> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI11<7> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI11<6> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI11<5> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI11<4> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI11<3> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI11<2> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI11<1> VDD VSS / RSC_IHPSG13_FILLCAP8 +.ENDS + +.SUBCKT RM_IHPSG13_1024x32_c2_1P_COLDRV13X8 ADDR_COL_I<1> ADDR_COL_I<0> ADDR_COL_O<1> ++ ADDR_COL_O<0> ADDR_DEC_I<7> ADDR_DEC_I<6> ADDR_DEC_I<5> ADDR_DEC_I<4> ++ ADDR_DEC_I<3> ADDR_DEC_I<2> ADDR_DEC_I<1> ADDR_DEC_I<0> ADDR_DEC_O<7> ++ ADDR_DEC_O<6> ADDR_DEC_O<5> ADDR_DEC_O<4> ADDR_DEC_O<3> ADDR_DEC_O<2> ++ ADDR_DEC_O<1> ADDR_DEC_O<0> DCLK_I DCLK_O RCLK_I RCLK_O WCLK_I WCLK_O ++ VDD VSS +XI0<1> VDD VSS / RSC_IHPSG13_FILLCAP4 +XI0<0> VDD VSS / RSC_IHPSG13_FILLCAP4 +XADDR_COL_DRV<1> ADDR_COL_I<1> ADDR_COL_O<1> VDD VSS / ++ RSC_IHPSG13_CBUFX8 +XADDR_COL_DRV<0> ADDR_COL_I<0> ADDR_COL_O<0> VDD VSS / ++ RSC_IHPSG13_CBUFX8 +XADDR_DEC_DRV<7> ADDR_DEC_I<7> ADDR_DEC_O<7> VDD VSS / ++ RSC_IHPSG13_CBUFX8 +XADDR_DEC_DRV<6> ADDR_DEC_I<6> ADDR_DEC_O<6> VDD VSS / ++ RSC_IHPSG13_CBUFX8 +XADDR_DEC_DRV<5> ADDR_DEC_I<5> ADDR_DEC_O<5> VDD VSS / ++ RSC_IHPSG13_CBUFX8 +XADDR_DEC_DRV<4> ADDR_DEC_I<4> ADDR_DEC_O<4> VDD VSS / ++ RSC_IHPSG13_CBUFX8 +XADDR_DEC_DRV<3> ADDR_DEC_I<3> ADDR_DEC_O<3> VDD VSS / ++ RSC_IHPSG13_CBUFX8 +XADDR_DEC_DRV<2> ADDR_DEC_I<2> ADDR_DEC_O<2> VDD VSS / ++ RSC_IHPSG13_CBUFX8 +XADDR_DEC_DRV<1> ADDR_DEC_I<1> ADDR_DEC_O<1> VDD VSS / ++ RSC_IHPSG13_CBUFX8 +XADDR_DEC_DRV<0> ADDR_DEC_I<0> ADDR_DEC_O<0> VDD VSS / ++ RSC_IHPSG13_CBUFX8 +XDCLK_DRV DCLK_I DCLK_O VDD VSS / RSC_IHPSG13_CBUFX8 +XRCLK_DRV RCLK_I RCLK_O VDD VSS / RSC_IHPSG13_CBUFX8 +XWCLK_DRV WCLK_I WCLK_O VDD VSS / RSC_IHPSG13_CBUFX8 +.ENDS +.SUBCKT RM_IHPSG13_1024x32_c2_1P_WLDRV16X8 A<15> A<14> A<13> A<12> A<11> A<10> A<9> A<8> ++ A<7> A<6> A<5> A<4> A<3> A<2> A<1> A<0> Z<15> Z<14> Z<13> Z<12> Z<11> Z<10> ++ Z<9> Z<8> Z<7> Z<6> Z<5> Z<4> Z<3> Z<2> Z<1> Z<0> VDD VSS +XBUF<15> A<15> Z<15> VDD VSS / RSC_IHPSG13_WLDRVX8 +XBUF<14> A<14> Z<14> VDD VSS / RSC_IHPSG13_WLDRVX8 +XBUF<13> A<13> Z<13> VDD VSS / RSC_IHPSG13_WLDRVX8 +XBUF<12> A<12> Z<12> VDD VSS / RSC_IHPSG13_WLDRVX8 +XBUF<11> A<11> Z<11> VDD VSS / RSC_IHPSG13_WLDRVX8 +XBUF<10> A<10> Z<10> VDD VSS / RSC_IHPSG13_WLDRVX8 +XBUF<9> A<9> Z<9> VDD VSS / RSC_IHPSG13_WLDRVX8 +XBUF<8> A<8> Z<8> VDD VSS / RSC_IHPSG13_WLDRVX8 +XBUF<7> A<7> Z<7> VDD VSS / RSC_IHPSG13_WLDRVX8 +XBUF<6> A<6> Z<6> VDD VSS / RSC_IHPSG13_WLDRVX8 +XBUF<5> A<5> Z<5> VDD VSS / RSC_IHPSG13_WLDRVX8 +XBUF<4> A<4> Z<4> VDD VSS / RSC_IHPSG13_WLDRVX8 +XBUF<3> A<3> Z<3> VDD VSS / RSC_IHPSG13_WLDRVX8 +XBUF<2> A<2> Z<2> VDD VSS / RSC_IHPSG13_WLDRVX8 +XBUF<1> A<1> Z<1> VDD VSS / RSC_IHPSG13_WLDRVX8 +XBUF<0> A<0> Z<0> VDD VSS / RSC_IHPSG13_WLDRVX8 +.ENDS + + + +.SUBCKT RM_IHPSG13_1024x32_c2_1P_ROWDEC6 ADDR_N_I<5> ADDR_N_I<4> ADDR_N_I<3> ADDR_N_I<2> ++ ADDR_N_I<1> ADDR_N_I<0> CS_I ECLK_I WL_O<63> WL_O<62> WL_O<61> WL_O<60> ++ WL_O<59> WL_O<58> WL_O<57> WL_O<56> WL_O<55> WL_O<54> WL_O<53> WL_O<52> ++ WL_O<51> WL_O<50> WL_O<49> WL_O<48> WL_O<47> WL_O<46> WL_O<45> WL_O<44> ++ WL_O<43> WL_O<42> WL_O<41> WL_O<40> WL_O<39> WL_O<38> WL_O<37> WL_O<36> ++ WL_O<35> WL_O<34> WL_O<33> WL_O<32> WL_O<31> WL_O<30> WL_O<29> WL_O<28> ++ WL_O<27> WL_O<26> WL_O<25> WL_O<24> WL_O<23> WL_O<22> WL_O<21> WL_O<20> ++ WL_O<19> WL_O<18> WL_O<17> WL_O<16> WL_O<15> WL_O<14> WL_O<13> WL_O<12> ++ WL_O<11> WL_O<10> WL_O<9> WL_O<8> WL_O<7> WL_O<6> WL_O<5> WL_O<4> WL_O<3> ++ WL_O<2> WL_O<1> WL_O<0> VDD VSS +XDEC11 ADDR_N_I<5> ADDR_N_I<4> CS_I CS00<3> VDD VSS / ++ RM_IHPSG13_1024x32_c2_1P_DEC03 +XDEC00 ADDR_N_I<5> ADDR_N_I<4> CS_I CS00<0> VDD VSS / ++ RM_IHPSG13_1024x32_c2_1P_DEC00 +XDEC01 ADDR_N_I<5> ADDR_N_I<4> CS_I CS00<1> VDD VSS / ++ RM_IHPSG13_1024x32_c2_1P_DEC01 +XDEC10 ADDR_N_I<5> ADDR_N_I<4> CS_I CS00<2> VDD VSS / ++ RM_IHPSG13_1024x32_c2_1P_DEC02 +XSEL<3> ADDR_N_I<3> ADDR_N_I<2> ADDR_N_I<1> ADDR_N_I<0> CS00<3> ECLK_H<3> ++ ECLK_H<4> ECLK_B<3> ECLK_B<4> WL_O<63> WL_O<62> WL_O<61> WL_O<60> WL_O<59> ++ WL_O<58> WL_O<57> WL_O<56> WL_O<55> WL_O<54> WL_O<53> WL_O<52> WL_O<51> ++ WL_O<50> WL_O<49> WL_O<48> VDD VSS / RM_IHPSG13_1024x32_c2_1P_DEC04 +XSEL<2> ADDR_N_I<3> ADDR_N_I<2> ADDR_N_I<1> ADDR_N_I<0> CS00<2> ECLK_H<2> ++ ECLK_H<3> ECLK_B<2> ECLK_B<3> WL_O<47> WL_O<46> WL_O<45> WL_O<44> WL_O<43> ++ WL_O<42> WL_O<41> WL_O<40> WL_O<39> WL_O<38> WL_O<37> WL_O<36> WL_O<35> ++ WL_O<34> WL_O<33> WL_O<32> VDD VSS / RM_IHPSG13_1024x32_c2_1P_DEC04 +XSEL<1> ADDR_N_I<3> ADDR_N_I<2> ADDR_N_I<1> ADDR_N_I<0> CS00<1> ECLK_H<1> ++ ECLK_H<2> ECLK_B<1> ECLK_B<2> WL_O<31> WL_O<30> WL_O<29> WL_O<28> WL_O<27> ++ WL_O<26> WL_O<25> WL_O<24> WL_O<23> WL_O<22> WL_O<21> WL_O<20> WL_O<19> ++ WL_O<18> WL_O<17> WL_O<16> VDD VSS / RM_IHPSG13_1024x32_c2_1P_DEC04 +XSEL<0> ADDR_N_I<3> ADDR_N_I<2> ADDR_N_I<1> ADDR_N_I<0> CS00<0> ECLK_I ++ ECLK_H<1> ECLK_B<0> ECLK_B<1> WL_O<15> WL_O<14> WL_O<13> WL_O<12> WL_O<11> ++ WL_O<10> WL_O<9> WL_O<8> WL_O<7> WL_O<6> WL_O<5> WL_O<4> WL_O<3> WL_O<2> ++ WL_O<1> WL_O<0> VDD VSS / RM_IHPSG13_1024x32_c2_1P_DEC04 +XL2<24> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<23> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<22> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<21> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<20> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<19> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<18> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<17> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<16> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<15> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<14> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<13> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<12> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<11> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<10> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<9> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<8> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<7> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<6> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<5> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<4> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<3> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<2> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<1> VDD VSS / RSC_IHPSG13_FILLCAP8 +.ENDS +.SUBCKT RM_IHPSG13_1024x32_c2_1P_ROWREG6 ACLK_N_I ADDR_I<5> ADDR_I<4> ADDR_I<3> ADDR_I<2> ++ ADDR_I<1> ADDR_I<0> ADDR_N_O<5> ADDR_N_O<4> ADDR_N_O<3> ADDR_N_O<2> ++ ADDR_N_O<1> ADDR_N_O<0> BIST_ADDR_I<5> BIST_ADDR_I<4> BIST_ADDR_I<3> ++ BIST_ADDR_I<2> BIST_ADDR_I<1> BIST_ADDR_I<0> BIST_EN_I VDD VSS +XINV<5> q_int<5> qn_int<5> VDD VSS / RSC_IHPSG13_CINVX2 +XINV<4> q_int<4> qn_int<4> VDD VSS / RSC_IHPSG13_CINVX2 +XINV<3> q_int<3> qn_int<3> VDD VSS / RSC_IHPSG13_CINVX2 +XINV<2> q_int<2> qn_int<2> VDD VSS / RSC_IHPSG13_CINVX2 +XINV<1> q_int<1> qn_int<1> VDD VSS / RSC_IHPSG13_CINVX2 +XINV<0> q_int<0> qn_int<0> VDD VSS / RSC_IHPSG13_CINVX2 +XDRV<5> qn_int<5> ADDR_N_O<5> VDD VSS / RSC_IHPSG13_CINVX8 +XDRV<4> qn_int<4> ADDR_N_O<4> VDD VSS / RSC_IHPSG13_CINVX8 +XDRV<3> qn_int<3> ADDR_N_O<3> VDD VSS / RSC_IHPSG13_CINVX8 +XDRV<2> qn_int<2> ADDR_N_O<2> VDD VSS / RSC_IHPSG13_CINVX8 +XDRV<1> qn_int<1> ADDR_N_O<1> VDD VSS / RSC_IHPSG13_CINVX8 +XDRV<0> qn_int<0> ADDR_N_O<0> VDD VSS / RSC_IHPSG13_CINVX8 +XDFF<5> BIST_EN_I BIST_ADDR_I<5> ACLK_N_I ADDR_I<5> q_int<5> net2<0> VDD ++ VSS / RSC_IHPSG13_DFNQMX2IX1 +XDFF<4> BIST_EN_I BIST_ADDR_I<4> ACLK_N_I ADDR_I<4> q_int<4> net2<1> VDD ++ VSS / RSC_IHPSG13_DFNQMX2IX1 +XDFF<3> BIST_EN_I BIST_ADDR_I<3> ACLK_N_I ADDR_I<3> q_int<3> net2<2> VDD ++ VSS / RSC_IHPSG13_DFNQMX2IX1 +XDFF<2> BIST_EN_I BIST_ADDR_I<2> ACLK_N_I ADDR_I<2> q_int<2> net2<3> VDD ++ VSS / RSC_IHPSG13_DFNQMX2IX1 +XDFF<1> BIST_EN_I BIST_ADDR_I<1> ACLK_N_I ADDR_I<1> q_int<1> net2<4> VDD ++ VSS / RSC_IHPSG13_DFNQMX2IX1 +XDFF<0> BIST_EN_I BIST_ADDR_I<0> ACLK_N_I ADDR_I<0> q_int<0> net2<5> VDD ++ VSS / RSC_IHPSG13_DFNQMX2IX1 +XI11<12> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI11<11> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI11<10> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI11<9> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI11<8> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI11<7> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI11<6> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI11<5> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI11<4> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI11<3> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI11<2> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI11<1> VDD VSS / RSC_IHPSG13_FILLCAP8 +.ENDS + + +.SUBCKT RM_IHPSG13_1024x32_c2_2P_COLUMN_pcell_0 A_BLC_BOT<1> A_BLC_BOT<0> A_BLC_TOP<1> A_BLC_TOP<0> A_BLT_BOT<1> A_BLT_BOT<0> A_BLT_TOP<1> A_BLT_TOP<0> A_LWL<255> A_LWL<254> A_LWL<253> A_LWL<252> A_LWL<251> A_LWL<250> A_LWL<249> A_LWL<248> A_LWL<247> A_LWL<246> A_LWL<245> A_LWL<244> A_LWL<243> A_LWL<242> A_LWL<241> A_LWL<240> A_LWL<239> A_LWL<238> A_LWL<237> A_LWL<236> A_LWL<235> A_LWL<234> A_LWL<233> A_LWL<232> A_LWL<231> A_LWL<230> A_LWL<229> A_LWL<228> A_LWL<227> A_LWL<226> A_LWL<225> A_LWL<224> A_LWL<223> A_LWL<222> A_LWL<221> A_LWL<220> A_LWL<219> A_LWL<218> A_LWL<217> A_LWL<216> A_LWL<215> A_LWL<214> A_LWL<213> A_LWL<212> A_LWL<211> A_LWL<210> A_LWL<209> A_LWL<208> A_LWL<207> A_LWL<206> A_LWL<205> A_LWL<204> A_LWL<203> A_LWL<202> A_LWL<201> A_LWL<200> A_LWL<199> A_LWL<198> A_LWL<197> A_LWL<196> A_LWL<195> A_LWL<194> A_LWL<193> A_LWL<192> A_LWL<191> A_LWL<190> A_LWL<189> A_LWL<188> A_LWL<187> A_LWL<186> A_LWL<185> A_LWL<184> A_LWL<183> A_LWL<182> A_LWL<181> A_LWL<180> A_LWL<179> A_LWL<178> A_LWL<177> A_LWL<176> A_LWL<175> A_LWL<174> A_LWL<173> A_LWL<172> A_LWL<171> A_LWL<170> A_LWL<169> A_LWL<168> A_LWL<167> A_LWL<166> A_LWL<165> A_LWL<164> A_LWL<163> A_LWL<162> A_LWL<161> A_LWL<160> A_LWL<159> A_LWL<158> A_LWL<157> A_LWL<156> A_LWL<155> A_LWL<154> A_LWL<153> A_LWL<152> A_LWL<151> A_LWL<150> A_LWL<149> A_LWL<148> A_LWL<147> A_LWL<146> A_LWL<145> A_LWL<144> A_LWL<143> A_LWL<142> A_LWL<141> A_LWL<140> A_LWL<139> A_LWL<138> A_LWL<137> A_LWL<136> A_LWL<135> A_LWL<134> A_LWL<133> A_LWL<132> A_LWL<131> A_LWL<130> A_LWL<129> A_LWL<128> A_LWL<127> A_LWL<126> A_LWL<125> A_LWL<124> A_LWL<123> A_LWL<122> A_LWL<121> A_LWL<120> A_LWL<119> A_LWL<118> A_LWL<117> A_LWL<116> A_LWL<115> A_LWL<114> A_LWL<113> A_LWL<112> A_LWL<111> A_LWL<110> A_LWL<109> A_LWL<108> A_LWL<107> A_LWL<106> A_LWL<105> A_LWL<104> A_LWL<103> A_LWL<102> A_LWL<101> A_LWL<100> A_LWL<99> A_LWL<98> A_LWL<97> A_LWL<96> A_LWL<95> A_LWL<94> A_LWL<93> A_LWL<92> A_LWL<91> A_LWL<90> A_LWL<89> A_LWL<88> A_LWL<87> A_LWL<86> A_LWL<85> A_LWL<84> A_LWL<83> A_LWL<82> A_LWL<81> A_LWL<80> A_LWL<79> A_LWL<78> A_LWL<77> A_LWL<76> A_LWL<75> A_LWL<74> A_LWL<73> A_LWL<72> A_LWL<71> A_LWL<70> A_LWL<69> A_LWL<68> A_LWL<67> A_LWL<66> A_LWL<65> A_LWL<64> A_LWL<63> A_LWL<62> A_LWL<61> A_LWL<60> A_LWL<59> A_LWL<58> A_LWL<57> A_LWL<56> A_LWL<55> A_LWL<54> A_LWL<53> A_LWL<52> A_LWL<51> A_LWL<50> A_LWL<49> A_LWL<48> A_LWL<47> A_LWL<46> A_LWL<45> A_LWL<44> A_LWL<43> A_LWL<42> A_LWL<41> A_LWL<40> A_LWL<39> A_LWL<38> A_LWL<37> A_LWL<36> A_LWL<35> A_LWL<34> A_LWL<33> A_LWL<32> A_LWL<31> A_LWL<30> A_LWL<29> A_LWL<28> A_LWL<27> A_LWL<26> A_LWL<25> A_LWL<24> A_LWL<23> A_LWL<22> A_LWL<21> A_LWL<20> A_LWL<19> A_LWL<18> A_LWL<17> A_LWL<16> A_LWL<15> A_LWL<14> A_LWL<13> A_LWL<12> A_LWL<11> A_LWL<10> A_LWL<9> A_LWL<8> A_LWL<7> A_LWL<6> A_LWL<5> A_LWL<4> A_LWL<3> A_LWL<2> A_LWL<1> A_LWL<0> A_RWL<255> A_RWL<254> A_RWL<253> A_RWL<252> A_RWL<251> A_RWL<250> A_RWL<249> A_RWL<248> A_RWL<247> A_RWL<246> A_RWL<245> A_RWL<244> A_RWL<243> A_RWL<242> A_RWL<241> A_RWL<240> A_RWL<239> A_RWL<238> A_RWL<237> A_RWL<236> A_RWL<235> A_RWL<234> A_RWL<233> A_RWL<232> A_RWL<231> A_RWL<230> A_RWL<229> A_RWL<228> A_RWL<227> A_RWL<226> A_RWL<225> A_RWL<224> A_RWL<223> A_RWL<222> A_RWL<221> A_RWL<220> A_RWL<219> A_RWL<218> A_RWL<217> A_RWL<216> A_RWL<215> A_RWL<214> A_RWL<213> A_RWL<212> A_RWL<211> A_RWL<210> A_RWL<209> A_RWL<208> A_RWL<207> A_RWL<206> A_RWL<205> A_RWL<204> A_RWL<203> A_RWL<202> A_RWL<201> A_RWL<200> A_RWL<199> A_RWL<198> A_RWL<197> A_RWL<196> A_RWL<195> A_RWL<194> A_RWL<193> A_RWL<192> A_RWL<191> A_RWL<190> A_RWL<189> A_RWL<188> A_RWL<187> A_RWL<186> A_RWL<185> A_RWL<184> A_RWL<183> A_RWL<182> A_RWL<181> A_RWL<180> A_RWL<179> A_RWL<178> A_RWL<177> A_RWL<176> A_RWL<175> A_RWL<174> A_RWL<173> A_RWL<172> A_RWL<171> A_RWL<170> A_RWL<169> A_RWL<168> A_RWL<167> A_RWL<166> A_RWL<165> A_RWL<164> A_RWL<163> A_RWL<162> A_RWL<161> A_RWL<160> A_RWL<159> A_RWL<158> A_RWL<157> A_RWL<156> A_RWL<155> A_RWL<154> A_RWL<153> A_RWL<152> A_RWL<151> A_RWL<150> A_RWL<149> A_RWL<148> A_RWL<147> A_RWL<146> A_RWL<145> A_RWL<144> A_RWL<143> A_RWL<142> A_RWL<141> A_RWL<140> A_RWL<139> A_RWL<138> A_RWL<137> A_RWL<136> A_RWL<135> A_RWL<134> A_RWL<133> A_RWL<132> A_RWL<131> A_RWL<130> A_RWL<129> A_RWL<128> A_RWL<127> A_RWL<126> A_RWL<125> A_RWL<124> A_RWL<123> A_RWL<122> A_RWL<121> A_RWL<120> A_RWL<119> A_RWL<118> A_RWL<117> A_RWL<116> A_RWL<115> A_RWL<114> A_RWL<113> A_RWL<112> A_RWL<111> A_RWL<110> A_RWL<109> A_RWL<108> A_RWL<107> A_RWL<106> A_RWL<105> A_RWL<104> A_RWL<103> A_RWL<102> A_RWL<101> A_RWL<100> A_RWL<99> A_RWL<98> A_RWL<97> A_RWL<96> A_RWL<95> A_RWL<94> A_RWL<93> A_RWL<92> A_RWL<91> A_RWL<90> A_RWL<89> A_RWL<88> A_RWL<87> A_RWL<86> A_RWL<85> A_RWL<84> A_RWL<83> A_RWL<82> A_RWL<81> A_RWL<80> A_RWL<79> A_RWL<78> A_RWL<77> A_RWL<76> A_RWL<75> A_RWL<74> A_RWL<73> A_RWL<72> A_RWL<71> A_RWL<70> A_RWL<69> A_RWL<68> A_RWL<67> A_RWL<66> A_RWL<65> A_RWL<64> A_RWL<63> A_RWL<62> A_RWL<61> A_RWL<60> A_RWL<59> A_RWL<58> A_RWL<57> A_RWL<56> A_RWL<55> A_RWL<54> A_RWL<53> A_RWL<52> A_RWL<51> A_RWL<50> A_RWL<49> A_RWL<48> A_RWL<47> A_RWL<46> A_RWL<45> A_RWL<44> A_RWL<43> A_RWL<42> A_RWL<41> A_RWL<40> A_RWL<39> A_RWL<38> A_RWL<37> A_RWL<36> A_RWL<35> A_RWL<34> A_RWL<33> A_RWL<32> A_RWL<31> A_RWL<30> A_RWL<29> A_RWL<28> A_RWL<27> A_RWL<26> A_RWL<25> A_RWL<24> A_RWL<23> A_RWL<22> A_RWL<21> A_RWL<20> A_RWL<19> A_RWL<18> A_RWL<17> A_RWL<16> A_RWL<15> A_RWL<14> A_RWL<13> A_RWL<12> A_RWL<11> A_RWL<10> A_RWL<9> A_RWL<8> A_RWL<7> A_RWL<6> A_RWL<5> A_RWL<4> A_RWL<3> A_RWL<2> A_RWL<1> A_RWL<0> B_BLC_BOT<1> B_BLC_BOT<0> B_BLC_TOP<1> B_BLC_TOP<0> B_BLT_BOT<1> B_BLT_BOT<0> B_BLT_TOP<1> B_BLT_TOP<0> B_LWL<255> B_LWL<254> B_LWL<253> B_LWL<252> B_LWL<251> B_LWL<250> B_LWL<249> B_LWL<248> B_LWL<247> B_LWL<246> B_LWL<245> B_LWL<244> B_LWL<243> B_LWL<242> B_LWL<241> B_LWL<240> B_LWL<239> B_LWL<238> B_LWL<237> B_LWL<236> B_LWL<235> B_LWL<234> B_LWL<233> B_LWL<232> B_LWL<231> B_LWL<230> B_LWL<229> B_LWL<228> B_LWL<227> B_LWL<226> B_LWL<225> B_LWL<224> B_LWL<223> B_LWL<222> B_LWL<221> B_LWL<220> B_LWL<219> B_LWL<218> B_LWL<217> B_LWL<216> B_LWL<215> B_LWL<214> B_LWL<213> B_LWL<212> B_LWL<211> B_LWL<210> B_LWL<209> B_LWL<208> B_LWL<207> B_LWL<206> B_LWL<205> B_LWL<204> B_LWL<203> B_LWL<202> B_LWL<201> B_LWL<200> B_LWL<199> B_LWL<198> B_LWL<197> B_LWL<196> B_LWL<195> B_LWL<194> B_LWL<193> B_LWL<192> B_LWL<191> B_LWL<190> B_LWL<189> B_LWL<188> B_LWL<187> B_LWL<186> B_LWL<185> B_LWL<184> B_LWL<183> B_LWL<182> B_LWL<181> B_LWL<180> B_LWL<179> B_LWL<178> B_LWL<177> B_LWL<176> B_LWL<175> B_LWL<174> B_LWL<173> B_LWL<172> B_LWL<171> B_LWL<170> B_LWL<169> B_LWL<168> B_LWL<167> B_LWL<166> B_LWL<165> B_LWL<164> B_LWL<163> B_LWL<162> B_LWL<161> B_LWL<160> B_LWL<159> B_LWL<158> B_LWL<157> B_LWL<156> B_LWL<155> B_LWL<154> B_LWL<153> B_LWL<152> B_LWL<151> B_LWL<150> B_LWL<149> B_LWL<148> B_LWL<147> B_LWL<146> B_LWL<145> B_LWL<144> B_LWL<143> B_LWL<142> B_LWL<141> B_LWL<140> B_LWL<139> B_LWL<138> B_LWL<137> B_LWL<136> B_LWL<135> B_LWL<134> B_LWL<133> B_LWL<132> B_LWL<131> B_LWL<130> B_LWL<129> B_LWL<128> B_LWL<127> B_LWL<126> B_LWL<125> B_LWL<124> B_LWL<123> B_LWL<122> B_LWL<121> B_LWL<120> B_LWL<119> B_LWL<118> B_LWL<117> B_LWL<116> B_LWL<115> B_LWL<114> B_LWL<113> B_LWL<112> B_LWL<111> B_LWL<110> B_LWL<109> B_LWL<108> B_LWL<107> B_LWL<106> B_LWL<105> B_LWL<104> B_LWL<103> B_LWL<102> B_LWL<101> B_LWL<100> B_LWL<99> B_LWL<98> B_LWL<97> B_LWL<96> B_LWL<95> B_LWL<94> B_LWL<93> B_LWL<92> B_LWL<91> B_LWL<90> B_LWL<89> B_LWL<88> B_LWL<87> B_LWL<86> B_LWL<85> B_LWL<84> B_LWL<83> B_LWL<82> B_LWL<81> B_LWL<80> B_LWL<79> B_LWL<78> B_LWL<77> B_LWL<76> B_LWL<75> B_LWL<74> B_LWL<73> B_LWL<72> B_LWL<71> B_LWL<70> B_LWL<69> B_LWL<68> B_LWL<67> B_LWL<66> B_LWL<65> B_LWL<64> B_LWL<63> B_LWL<62> B_LWL<61> B_LWL<60> B_LWL<59> B_LWL<58> B_LWL<57> B_LWL<56> B_LWL<55> B_LWL<54> B_LWL<53> B_LWL<52> B_LWL<51> B_LWL<50> B_LWL<49> B_LWL<48> B_LWL<47> B_LWL<46> B_LWL<45> B_LWL<44> B_LWL<43> B_LWL<42> B_LWL<41> B_LWL<40> B_LWL<39> B_LWL<38> B_LWL<37> B_LWL<36> B_LWL<35> B_LWL<34> B_LWL<33> B_LWL<32> B_LWL<31> B_LWL<30> B_LWL<29> B_LWL<28> B_LWL<27> B_LWL<26> B_LWL<25> B_LWL<24> B_LWL<23> B_LWL<22> B_LWL<21> B_LWL<20> B_LWL<19> B_LWL<18> B_LWL<17> B_LWL<16> B_LWL<15> B_LWL<14> B_LWL<13> B_LWL<12> B_LWL<11> B_LWL<10> B_LWL<9> B_LWL<8> B_LWL<7> B_LWL<6> B_LWL<5> B_LWL<4> B_LWL<3> B_LWL<2> B_LWL<1> B_LWL<0> B_RWL<255> B_RWL<254> B_RWL<253> B_RWL<252> B_RWL<251> B_RWL<250> B_RWL<249> B_RWL<248> B_RWL<247> B_RWL<246> B_RWL<245> B_RWL<244> B_RWL<243> B_RWL<242> B_RWL<241> B_RWL<240> B_RWL<239> B_RWL<238> B_RWL<237> B_RWL<236> B_RWL<235> B_RWL<234> B_RWL<233> B_RWL<232> B_RWL<231> B_RWL<230> B_RWL<229> B_RWL<228> B_RWL<227> B_RWL<226> B_RWL<225> B_RWL<224> B_RWL<223> B_RWL<222> B_RWL<221> B_RWL<220> B_RWL<219> B_RWL<218> B_RWL<217> B_RWL<216> B_RWL<215> B_RWL<214> B_RWL<213> B_RWL<212> B_RWL<211> B_RWL<210> B_RWL<209> B_RWL<208> B_RWL<207> B_RWL<206> B_RWL<205> B_RWL<204> B_RWL<203> B_RWL<202> B_RWL<201> B_RWL<200> B_RWL<199> B_RWL<198> B_RWL<197> B_RWL<196> B_RWL<195> B_RWL<194> B_RWL<193> B_RWL<192> B_RWL<191> B_RWL<190> B_RWL<189> B_RWL<188> B_RWL<187> B_RWL<186> B_RWL<185> B_RWL<184> B_RWL<183> B_RWL<182> B_RWL<181> B_RWL<180> B_RWL<179> B_RWL<178> B_RWL<177> B_RWL<176> B_RWL<175> B_RWL<174> B_RWL<173> B_RWL<172> B_RWL<171> B_RWL<170> B_RWL<169> B_RWL<168> B_RWL<167> B_RWL<166> B_RWL<165> B_RWL<164> B_RWL<163> B_RWL<162> B_RWL<161> B_RWL<160> B_RWL<159> B_RWL<158> B_RWL<157> B_RWL<156> B_RWL<155> B_RWL<154> B_RWL<153> B_RWL<152> B_RWL<151> B_RWL<150> B_RWL<149> B_RWL<148> B_RWL<147> B_RWL<146> B_RWL<145> B_RWL<144> B_RWL<143> B_RWL<142> B_RWL<141> B_RWL<140> B_RWL<139> B_RWL<138> B_RWL<137> B_RWL<136> B_RWL<135> B_RWL<134> B_RWL<133> B_RWL<132> B_RWL<131> B_RWL<130> B_RWL<129> B_RWL<128> B_RWL<127> B_RWL<126> B_RWL<125> B_RWL<124> B_RWL<123> B_RWL<122> B_RWL<121> B_RWL<120> B_RWL<119> B_RWL<118> B_RWL<117> B_RWL<116> B_RWL<115> B_RWL<114> B_RWL<113> B_RWL<112> B_RWL<111> B_RWL<110> B_RWL<109> B_RWL<108> B_RWL<107> B_RWL<106> B_RWL<105> B_RWL<104> B_RWL<103> B_RWL<102> B_RWL<101> B_RWL<100> B_RWL<99> B_RWL<98> B_RWL<97> B_RWL<96> B_RWL<95> B_RWL<94> B_RWL<93> B_RWL<92> B_RWL<91> B_RWL<90> B_RWL<89> B_RWL<88> B_RWL<87> B_RWL<86> B_RWL<85> B_RWL<84> B_RWL<83> B_RWL<82> B_RWL<81> B_RWL<80> B_RWL<79> B_RWL<78> B_RWL<77> B_RWL<76> B_RWL<75> B_RWL<74> B_RWL<73> B_RWL<72> B_RWL<71> B_RWL<70> B_RWL<69> B_RWL<68> B_RWL<67> B_RWL<66> B_RWL<65> B_RWL<64> B_RWL<63> B_RWL<62> B_RWL<61> B_RWL<60> B_RWL<59> B_RWL<58> B_RWL<57> B_RWL<56> B_RWL<55> B_RWL<54> B_RWL<53> B_RWL<52> B_RWL<51> B_RWL<50> B_RWL<49> B_RWL<48> B_RWL<47> B_RWL<46> B_RWL<45> B_RWL<44> B_RWL<43> B_RWL<42> B_RWL<41> B_RWL<40> B_RWL<39> B_RWL<38> B_RWL<37> B_RWL<36> B_RWL<35> B_RWL<34> B_RWL<33> B_RWL<32> B_RWL<31> B_RWL<30> B_RWL<29> B_RWL<28> B_RWL<27> B_RWL<26> B_RWL<25> B_RWL<24> B_RWL<23> B_RWL<22> B_RWL<21> B_RWL<20> B_RWL<19> B_RWL<18> B_RWL<17> B_RWL<16> B_RWL<15> B_RWL<14> B_RWL<13> B_RWL<12> B_RWL<11> B_RWL<10> B_RWL<9> B_RWL<8> B_RWL<7> B_RWL<6> B_RWL<5> B_RWL<4> B_RWL<3> B_RWL<2> B_RWL<1> B_RWL<0> VDD_CORE VSS +XRAM<16> A_BLC<29> A_BLC<28> A_BLC_TOP<1> A_BLC_TOP<0> A_BLT<29> A_BLT<28> A_BLT_TOP<1> A_BLT_TOP<0> A_LWL<255> A_LWL<254> A_LWL<253> A_LWL<252> A_LWL<251> A_LWL<250> A_LWL<249> A_LWL<248> A_LWL<247> A_LWL<246> A_LWL<245> A_LWL<244> A_LWL<243> A_LWL<242> A_LWL<241> A_LWL<240> A_RWL<255> A_RWL<254> A_RWL<253> A_RWL<252> A_RWL<251> A_RWL<250> A_RWL<249> A_RWL<248> A_RWL<247> A_RWL<246> A_RWL<245> A_RWL<244> A_RWL<243> A_RWL<242> A_RWL<241> A_RWL<240> B_BLC<29> B_BLC<28> B_BLC_TOP<1> B_BLC_TOP<0> B_BLT<29> B_BLT<28> B_BLT_TOP<1> B_BLT_TOP<0> B_LWL<255> B_LWL<254> B_LWL<253> B_LWL<252> B_LWL<251> B_LWL<250> B_LWL<249> B_LWL<248> B_LWL<247> B_LWL<246> B_LWL<245> B_LWL<244> B_LWL<243> B_LWL<242> B_LWL<241> B_LWL<240> B_RWL<255> B_RWL<254> B_RWL<253> B_RWL<252> B_RWL<251> B_RWL<250> B_RWL<249> B_RWL<248> B_RWL<247> B_RWL<246> B_RWL<245> B_RWL<244> B_RWL<243> B_RWL<242> B_RWL<241> B_RWL<240> VDD_CORE VSS / RM_IHPSG13_1024x32_c2_2P_BITKIT_16x2_SRAM +XRAM<15> A_BLC<27> A_BLC<26> A_BLC<29> A_BLC<28> A_BLT<27> A_BLT<26> A_BLT<29> A_BLT<28> A_LWL<239> A_LWL<238> A_LWL<237> A_LWL<236> A_LWL<235> A_LWL<234> A_LWL<233> A_LWL<232> A_LWL<231> A_LWL<230> A_LWL<229> A_LWL<228> A_LWL<227> A_LWL<226> A_LWL<225> A_LWL<224> A_RWL<239> A_RWL<238> A_RWL<237> A_RWL<236> A_RWL<235> A_RWL<234> A_RWL<233> A_RWL<232> A_RWL<231> A_RWL<230> A_RWL<229> A_RWL<228> A_RWL<227> A_RWL<226> A_RWL<225> A_RWL<224> B_BLC<27> B_BLC<26> B_BLC<29> B_BLC<28> B_BLT<27> B_BLT<26> B_BLT<29> B_BLT<28> B_LWL<239> B_LWL<238> B_LWL<237> B_LWL<236> B_LWL<235> B_LWL<234> B_LWL<233> B_LWL<232> B_LWL<231> B_LWL<230> B_LWL<229> B_LWL<228> B_LWL<227> B_LWL<226> B_LWL<225> B_LWL<224> B_RWL<239> B_RWL<238> B_RWL<237> B_RWL<236> B_RWL<235> B_RWL<234> B_RWL<233> B_RWL<232> B_RWL<231> B_RWL<230> B_RWL<229> B_RWL<228> B_RWL<227> B_RWL<226> B_RWL<225> B_RWL<224> VDD_CORE VSS / RM_IHPSG13_1024x32_c2_2P_BITKIT_16x2_SRAM +XRAM<14> A_BLC<25> A_BLC<24> A_BLC<27> A_BLC<26> A_BLT<25> A_BLT<24> A_BLT<27> A_BLT<26> A_LWL<223> A_LWL<222> A_LWL<221> A_LWL<220> A_LWL<219> A_LWL<218> A_LWL<217> A_LWL<216> A_LWL<215> A_LWL<214> A_LWL<213> A_LWL<212> A_LWL<211> A_LWL<210> A_LWL<209> A_LWL<208> A_RWL<223> A_RWL<222> A_RWL<221> A_RWL<220> A_RWL<219> A_RWL<218> A_RWL<217> A_RWL<216> A_RWL<215> A_RWL<214> A_RWL<213> A_RWL<212> A_RWL<211> A_RWL<210> A_RWL<209> A_RWL<208> B_BLC<25> B_BLC<24> B_BLC<27> B_BLC<26> B_BLT<25> B_BLT<24> B_BLT<27> B_BLT<26> B_LWL<223> B_LWL<222> B_LWL<221> B_LWL<220> B_LWL<219> B_LWL<218> B_LWL<217> B_LWL<216> B_LWL<215> B_LWL<214> B_LWL<213> B_LWL<212> B_LWL<211> B_LWL<210> B_LWL<209> B_LWL<208> B_RWL<223> B_RWL<222> B_RWL<221> B_RWL<220> B_RWL<219> B_RWL<218> B_RWL<217> B_RWL<216> B_RWL<215> B_RWL<214> B_RWL<213> B_RWL<212> B_RWL<211> B_RWL<210> B_RWL<209> B_RWL<208> VDD_CORE VSS / RM_IHPSG13_1024x32_c2_2P_BITKIT_16x2_SRAM +XRAM<13> A_BLC<23> A_BLC<22> A_BLC<25> A_BLC<24> A_BLT<23> A_BLT<22> A_BLT<25> A_BLT<24> A_LWL<207> A_LWL<206> A_LWL<205> A_LWL<204> A_LWL<203> A_LWL<202> A_LWL<201> A_LWL<200> A_LWL<199> A_LWL<198> A_LWL<197> A_LWL<196> A_LWL<195> A_LWL<194> A_LWL<193> A_LWL<192> A_RWL<207> A_RWL<206> A_RWL<205> A_RWL<204> A_RWL<203> A_RWL<202> A_RWL<201> A_RWL<200> A_RWL<199> A_RWL<198> A_RWL<197> A_RWL<196> A_RWL<195> A_RWL<194> A_RWL<193> A_RWL<192> B_BLC<23> B_BLC<22> B_BLC<25> B_BLC<24> B_BLT<23> B_BLT<22> B_BLT<25> B_BLT<24> B_LWL<207> B_LWL<206> B_LWL<205> B_LWL<204> B_LWL<203> B_LWL<202> B_LWL<201> B_LWL<200> B_LWL<199> B_LWL<198> B_LWL<197> B_LWL<196> B_LWL<195> B_LWL<194> B_LWL<193> B_LWL<192> B_RWL<207> B_RWL<206> B_RWL<205> B_RWL<204> B_RWL<203> B_RWL<202> B_RWL<201> B_RWL<200> B_RWL<199> B_RWL<198> B_RWL<197> B_RWL<196> B_RWL<195> B_RWL<194> B_RWL<193> B_RWL<192> VDD_CORE VSS / RM_IHPSG13_1024x32_c2_2P_BITKIT_16x2_SRAM +XRAM<12> A_BLC<21> A_BLC<20> A_BLC<23> A_BLC<22> A_BLT<21> A_BLT<20> A_BLT<23> A_BLT<22> A_LWL<191> A_LWL<190> A_LWL<189> A_LWL<188> A_LWL<187> A_LWL<186> A_LWL<185> A_LWL<184> A_LWL<183> A_LWL<182> A_LWL<181> A_LWL<180> A_LWL<179> A_LWL<178> A_LWL<177> A_LWL<176> A_RWL<191> A_RWL<190> A_RWL<189> A_RWL<188> A_RWL<187> A_RWL<186> A_RWL<185> A_RWL<184> A_RWL<183> A_RWL<182> A_RWL<181> A_RWL<180> A_RWL<179> A_RWL<178> A_RWL<177> A_RWL<176> B_BLC<21> B_BLC<20> B_BLC<23> B_BLC<22> B_BLT<21> B_BLT<20> B_BLT<23> B_BLT<22> B_LWL<191> B_LWL<190> B_LWL<189> B_LWL<188> B_LWL<187> B_LWL<186> B_LWL<185> B_LWL<184> B_LWL<183> B_LWL<182> B_LWL<181> B_LWL<180> B_LWL<179> B_LWL<178> B_LWL<177> B_LWL<176> B_RWL<191> B_RWL<190> B_RWL<189> B_RWL<188> B_RWL<187> B_RWL<186> B_RWL<185> B_RWL<184> B_RWL<183> B_RWL<182> B_RWL<181> B_RWL<180> B_RWL<179> B_RWL<178> B_RWL<177> B_RWL<176> VDD_CORE VSS / RM_IHPSG13_1024x32_c2_2P_BITKIT_16x2_SRAM +XRAM<11> A_BLC<19> A_BLC<18> A_BLC<21> A_BLC<20> A_BLT<19> A_BLT<18> A_BLT<21> A_BLT<20> A_LWL<175> A_LWL<174> A_LWL<173> A_LWL<172> A_LWL<171> A_LWL<170> A_LWL<169> A_LWL<168> A_LWL<167> A_LWL<166> A_LWL<165> A_LWL<164> A_LWL<163> A_LWL<162> A_LWL<161> A_LWL<160> A_RWL<175> A_RWL<174> A_RWL<173> A_RWL<172> A_RWL<171> A_RWL<170> A_RWL<169> A_RWL<168> A_RWL<167> A_RWL<166> A_RWL<165> A_RWL<164> A_RWL<163> A_RWL<162> A_RWL<161> A_RWL<160> B_BLC<19> B_BLC<18> B_BLC<21> B_BLC<20> B_BLT<19> B_BLT<18> B_BLT<21> B_BLT<20> B_LWL<175> B_LWL<174> B_LWL<173> B_LWL<172> B_LWL<171> B_LWL<170> B_LWL<169> B_LWL<168> B_LWL<167> B_LWL<166> B_LWL<165> B_LWL<164> B_LWL<163> B_LWL<162> B_LWL<161> B_LWL<160> B_RWL<175> B_RWL<174> B_RWL<173> B_RWL<172> B_RWL<171> B_RWL<170> B_RWL<169> B_RWL<168> B_RWL<167> B_RWL<166> B_RWL<165> B_RWL<164> B_RWL<163> B_RWL<162> B_RWL<161> B_RWL<160> VDD_CORE VSS / RM_IHPSG13_1024x32_c2_2P_BITKIT_16x2_SRAM +XRAM<10> A_BLC<17> A_BLC<16> A_BLC<19> A_BLC<18> A_BLT<17> A_BLT<16> A_BLT<19> A_BLT<18> A_LWL<159> A_LWL<158> A_LWL<157> A_LWL<156> A_LWL<155> A_LWL<154> A_LWL<153> A_LWL<152> A_LWL<151> A_LWL<150> A_LWL<149> A_LWL<148> A_LWL<147> A_LWL<146> A_LWL<145> A_LWL<144> A_RWL<159> A_RWL<158> A_RWL<157> A_RWL<156> A_RWL<155> A_RWL<154> A_RWL<153> A_RWL<152> A_RWL<151> A_RWL<150> A_RWL<149> A_RWL<148> A_RWL<147> A_RWL<146> A_RWL<145> A_RWL<144> B_BLC<17> B_BLC<16> B_BLC<19> B_BLC<18> B_BLT<17> B_BLT<16> B_BLT<19> B_BLT<18> B_LWL<159> B_LWL<158> B_LWL<157> B_LWL<156> B_LWL<155> B_LWL<154> B_LWL<153> B_LWL<152> B_LWL<151> B_LWL<150> B_LWL<149> B_LWL<148> B_LWL<147> B_LWL<146> B_LWL<145> B_LWL<144> B_RWL<159> B_RWL<158> B_RWL<157> B_RWL<156> B_RWL<155> B_RWL<154> B_RWL<153> B_RWL<152> B_RWL<151> B_RWL<150> B_RWL<149> B_RWL<148> B_RWL<147> B_RWL<146> B_RWL<145> B_RWL<144> VDD_CORE VSS / RM_IHPSG13_1024x32_c2_2P_BITKIT_16x2_SRAM +XRAM<9> A_BLC<15> A_BLC<14> A_BLC<17> A_BLC<16> A_BLT<15> A_BLT<14> A_BLT<17> A_BLT<16> A_LWL<143> A_LWL<142> A_LWL<141> A_LWL<140> A_LWL<139> A_LWL<138> A_LWL<137> A_LWL<136> A_LWL<135> A_LWL<134> A_LWL<133> A_LWL<132> A_LWL<131> A_LWL<130> A_LWL<129> A_LWL<128> A_RWL<143> A_RWL<142> A_RWL<141> A_RWL<140> A_RWL<139> A_RWL<138> A_RWL<137> A_RWL<136> A_RWL<135> A_RWL<134> A_RWL<133> A_RWL<132> A_RWL<131> A_RWL<130> A_RWL<129> A_RWL<128> B_BLC<15> B_BLC<14> B_BLC<17> B_BLC<16> B_BLT<15> B_BLT<14> B_BLT<17> B_BLT<16> B_LWL<143> B_LWL<142> B_LWL<141> B_LWL<140> B_LWL<139> B_LWL<138> B_LWL<137> B_LWL<136> B_LWL<135> B_LWL<134> B_LWL<133> B_LWL<132> B_LWL<131> B_LWL<130> B_LWL<129> B_LWL<128> B_RWL<143> B_RWL<142> B_RWL<141> B_RWL<140> B_RWL<139> B_RWL<138> B_RWL<137> B_RWL<136> B_RWL<135> B_RWL<134> B_RWL<133> B_RWL<132> B_RWL<131> B_RWL<130> B_RWL<129> B_RWL<128> VDD_CORE VSS / RM_IHPSG13_1024x32_c2_2P_BITKIT_16x2_SRAM +XRAM<8> A_BLC<13> A_BLC<12> A_BLC<15> A_BLC<14> A_BLT<13> A_BLT<12> A_BLT<15> A_BLT<14> A_LWL<127> A_LWL<126> A_LWL<125> A_LWL<124> A_LWL<123> A_LWL<122> A_LWL<121> A_LWL<120> A_LWL<119> A_LWL<118> A_LWL<117> A_LWL<116> A_LWL<115> A_LWL<114> A_LWL<113> A_LWL<112> A_RWL<127> A_RWL<126> A_RWL<125> A_RWL<124> A_RWL<123> A_RWL<122> A_RWL<121> A_RWL<120> A_RWL<119> A_RWL<118> A_RWL<117> A_RWL<116> A_RWL<115> A_RWL<114> A_RWL<113> A_RWL<112> B_BLC<13> B_BLC<12> B_BLC<15> B_BLC<14> B_BLT<13> B_BLT<12> B_BLT<15> B_BLT<14> B_LWL<127> B_LWL<126> B_LWL<125> B_LWL<124> B_LWL<123> B_LWL<122> B_LWL<121> B_LWL<120> B_LWL<119> B_LWL<118> B_LWL<117> B_LWL<116> B_LWL<115> B_LWL<114> B_LWL<113> B_LWL<112> B_RWL<127> B_RWL<126> B_RWL<125> B_RWL<124> B_RWL<123> B_RWL<122> B_RWL<121> B_RWL<120> B_RWL<119> B_RWL<118> B_RWL<117> B_RWL<116> B_RWL<115> B_RWL<114> B_RWL<113> B_RWL<112> VDD_CORE VSS / RM_IHPSG13_1024x32_c2_2P_BITKIT_16x2_SRAM +XRAM<7> A_BLC<11> A_BLC<10> A_BLC<13> A_BLC<12> A_BLT<11> A_BLT<10> A_BLT<13> A_BLT<12> A_LWL<111> A_LWL<110> A_LWL<109> A_LWL<108> A_LWL<107> A_LWL<106> A_LWL<105> A_LWL<104> A_LWL<103> A_LWL<102> A_LWL<101> A_LWL<100> A_LWL<99> A_LWL<98> A_LWL<97> A_LWL<96> A_RWL<111> A_RWL<110> A_RWL<109> A_RWL<108> A_RWL<107> A_RWL<106> A_RWL<105> A_RWL<104> A_RWL<103> A_RWL<102> A_RWL<101> A_RWL<100> A_RWL<99> A_RWL<98> A_RWL<97> A_RWL<96> B_BLC<11> B_BLC<10> B_BLC<13> B_BLC<12> B_BLT<11> B_BLT<10> B_BLT<13> B_BLT<12> B_LWL<111> B_LWL<110> B_LWL<109> B_LWL<108> B_LWL<107> B_LWL<106> B_LWL<105> B_LWL<104> B_LWL<103> B_LWL<102> B_LWL<101> B_LWL<100> B_LWL<99> B_LWL<98> B_LWL<97> B_LWL<96> B_RWL<111> B_RWL<110> B_RWL<109> B_RWL<108> B_RWL<107> B_RWL<106> B_RWL<105> B_RWL<104> B_RWL<103> B_RWL<102> B_RWL<101> B_RWL<100> B_RWL<99> B_RWL<98> B_RWL<97> B_RWL<96> VDD_CORE VSS / RM_IHPSG13_1024x32_c2_2P_BITKIT_16x2_SRAM +XRAM<6> A_BLC<9> A_BLC<8> A_BLC<11> A_BLC<10> A_BLT<9> A_BLT<8> A_BLT<11> A_BLT<10> A_LWL<95> A_LWL<94> A_LWL<93> A_LWL<92> A_LWL<91> A_LWL<90> A_LWL<89> A_LWL<88> A_LWL<87> A_LWL<86> A_LWL<85> A_LWL<84> A_LWL<83> A_LWL<82> A_LWL<81> A_LWL<80> A_RWL<95> A_RWL<94> A_RWL<93> A_RWL<92> A_RWL<91> A_RWL<90> A_RWL<89> A_RWL<88> A_RWL<87> A_RWL<86> A_RWL<85> A_RWL<84> A_RWL<83> A_RWL<82> A_RWL<81> A_RWL<80> B_BLC<9> B_BLC<8> B_BLC<11> B_BLC<10> B_BLT<9> B_BLT<8> B_BLT<11> B_BLT<10> B_LWL<95> B_LWL<94> B_LWL<93> B_LWL<92> B_LWL<91> B_LWL<90> B_LWL<89> B_LWL<88> B_LWL<87> B_LWL<86> B_LWL<85> B_LWL<84> B_LWL<83> B_LWL<82> B_LWL<81> B_LWL<80> B_RWL<95> B_RWL<94> B_RWL<93> B_RWL<92> B_RWL<91> B_RWL<90> B_RWL<89> B_RWL<88> B_RWL<87> B_RWL<86> B_RWL<85> B_RWL<84> B_RWL<83> B_RWL<82> B_RWL<81> B_RWL<80> VDD_CORE VSS / RM_IHPSG13_1024x32_c2_2P_BITKIT_16x2_SRAM +XRAM<5> A_BLC<7> A_BLC<6> A_BLC<9> A_BLC<8> A_BLT<7> A_BLT<6> A_BLT<9> A_BLT<8> A_LWL<79> A_LWL<78> A_LWL<77> A_LWL<76> A_LWL<75> A_LWL<74> A_LWL<73> A_LWL<72> A_LWL<71> A_LWL<70> A_LWL<69> A_LWL<68> A_LWL<67> A_LWL<66> A_LWL<65> A_LWL<64> A_RWL<79> A_RWL<78> A_RWL<77> A_RWL<76> A_RWL<75> A_RWL<74> A_RWL<73> A_RWL<72> A_RWL<71> A_RWL<70> A_RWL<69> A_RWL<68> A_RWL<67> A_RWL<66> A_RWL<65> A_RWL<64> B_BLC<7> B_BLC<6> B_BLC<9> B_BLC<8> B_BLT<7> B_BLT<6> B_BLT<9> B_BLT<8> B_LWL<79> B_LWL<78> B_LWL<77> B_LWL<76> B_LWL<75> B_LWL<74> B_LWL<73> B_LWL<72> B_LWL<71> B_LWL<70> B_LWL<69> B_LWL<68> B_LWL<67> B_LWL<66> B_LWL<65> B_LWL<64> B_RWL<79> B_RWL<78> B_RWL<77> B_RWL<76> B_RWL<75> B_RWL<74> B_RWL<73> B_RWL<72> B_RWL<71> B_RWL<70> B_RWL<69> B_RWL<68> B_RWL<67> B_RWL<66> B_RWL<65> B_RWL<64> VDD_CORE VSS / RM_IHPSG13_1024x32_c2_2P_BITKIT_16x2_SRAM +XRAM<4> A_BLC<5> A_BLC<4> A_BLC<7> A_BLC<6> A_BLT<5> A_BLT<4> A_BLT<7> A_BLT<6> A_LWL<63> A_LWL<62> A_LWL<61> A_LWL<60> A_LWL<59> A_LWL<58> A_LWL<57> A_LWL<56> A_LWL<55> A_LWL<54> A_LWL<53> A_LWL<52> A_LWL<51> A_LWL<50> A_LWL<49> A_LWL<48> A_RWL<63> A_RWL<62> A_RWL<61> A_RWL<60> A_RWL<59> A_RWL<58> A_RWL<57> A_RWL<56> A_RWL<55> A_RWL<54> A_RWL<53> A_RWL<52> A_RWL<51> A_RWL<50> A_RWL<49> A_RWL<48> B_BLC<5> B_BLC<4> B_BLC<7> B_BLC<6> B_BLT<5> B_BLT<4> B_BLT<7> B_BLT<6> B_LWL<63> B_LWL<62> B_LWL<61> B_LWL<60> B_LWL<59> B_LWL<58> B_LWL<57> B_LWL<56> B_LWL<55> B_LWL<54> B_LWL<53> B_LWL<52> B_LWL<51> B_LWL<50> B_LWL<49> B_LWL<48> B_RWL<63> B_RWL<62> B_RWL<61> B_RWL<60> B_RWL<59> B_RWL<58> B_RWL<57> B_RWL<56> B_RWL<55> B_RWL<54> B_RWL<53> B_RWL<52> B_RWL<51> B_RWL<50> B_RWL<49> B_RWL<48> VDD_CORE VSS / RM_IHPSG13_1024x32_c2_2P_BITKIT_16x2_SRAM +XRAM<3> A_BLC<3> A_BLC<2> A_BLC<5> A_BLC<4> A_BLT<3> A_BLT<2> A_BLT<5> A_BLT<4> A_LWL<47> A_LWL<46> A_LWL<45> A_LWL<44> A_LWL<43> A_LWL<42> A_LWL<41> A_LWL<40> A_LWL<39> A_LWL<38> A_LWL<37> A_LWL<36> A_LWL<35> A_LWL<34> A_LWL<33> A_LWL<32> A_RWL<47> A_RWL<46> A_RWL<45> A_RWL<44> A_RWL<43> A_RWL<42> A_RWL<41> A_RWL<40> A_RWL<39> A_RWL<38> A_RWL<37> A_RWL<36> A_RWL<35> A_RWL<34> A_RWL<33> A_RWL<32> B_BLC<3> B_BLC<2> B_BLC<5> B_BLC<4> B_BLT<3> B_BLT<2> B_BLT<5> B_BLT<4> B_LWL<47> B_LWL<46> B_LWL<45> B_LWL<44> B_LWL<43> B_LWL<42> B_LWL<41> B_LWL<40> B_LWL<39> B_LWL<38> B_LWL<37> B_LWL<36> B_LWL<35> B_LWL<34> B_LWL<33> B_LWL<32> B_RWL<47> B_RWL<46> B_RWL<45> B_RWL<44> B_RWL<43> B_RWL<42> B_RWL<41> B_RWL<40> B_RWL<39> B_RWL<38> B_RWL<37> B_RWL<36> B_RWL<35> B_RWL<34> B_RWL<33> B_RWL<32> VDD_CORE VSS / RM_IHPSG13_1024x32_c2_2P_BITKIT_16x2_SRAM +XRAM<2> A_BLC<1> A_BLC<0> A_BLC<3> A_BLC<2> A_BLT<1> A_BLT<0> A_BLT<3> A_BLT<2> A_LWL<31> A_LWL<30> A_LWL<29> A_LWL<28> A_LWL<27> A_LWL<26> A_LWL<25> A_LWL<24> A_LWL<23> A_LWL<22> A_LWL<21> A_LWL<20> A_LWL<19> A_LWL<18> A_LWL<17> A_LWL<16> A_RWL<31> A_RWL<30> A_RWL<29> A_RWL<28> A_RWL<27> A_RWL<26> A_RWL<25> A_RWL<24> A_RWL<23> A_RWL<22> A_RWL<21> A_RWL<20> A_RWL<19> A_RWL<18> A_RWL<17> A_RWL<16> B_BLC<1> B_BLC<0> B_BLC<3> B_BLC<2> B_BLT<1> B_BLT<0> B_BLT<3> B_BLT<2> B_LWL<31> B_LWL<30> B_LWL<29> B_LWL<28> B_LWL<27> B_LWL<26> B_LWL<25> B_LWL<24> B_LWL<23> B_LWL<22> B_LWL<21> B_LWL<20> B_LWL<19> B_LWL<18> B_LWL<17> B_LWL<16> B_RWL<31> B_RWL<30> B_RWL<29> B_RWL<28> B_RWL<27> B_RWL<26> B_RWL<25> B_RWL<24> B_RWL<23> B_RWL<22> B_RWL<21> B_RWL<20> B_RWL<19> B_RWL<18> B_RWL<17> B_RWL<16> VDD_CORE VSS / RM_IHPSG13_1024x32_c2_2P_BITKIT_16x2_SRAM +XRAM<1> A_BLC_BOT<1> A_BLC_BOT<0> A_BLC<1> A_BLC<0> A_BLT_BOT<1> A_BLT_BOT<0> A_BLT<1> A_BLT<0> A_LWL<15> A_LWL<14> A_LWL<13> A_LWL<12> A_LWL<11> A_LWL<10> A_LWL<9> A_LWL<8> A_LWL<7> A_LWL<6> A_LWL<5> A_LWL<4> A_LWL<3> A_LWL<2> A_LWL<1> A_LWL<0> A_RWL<15> A_RWL<14> A_RWL<13> A_RWL<12> A_RWL<11> A_RWL<10> A_RWL<9> A_RWL<8> A_RWL<7> A_RWL<6> A_RWL<5> A_RWL<4> A_RWL<3> A_RWL<2> A_RWL<1> A_RWL<0> B_BLC_BOT<1> B_BLC_BOT<0> B_BLC<1> B_BLC<0> B_BLT_BOT<1> B_BLT_BOT<0> B_BLT<1> B_BLT<0> B_LWL<15> B_LWL<14> B_LWL<13> B_LWL<12> B_LWL<11> B_LWL<10> B_LWL<9> B_LWL<8> B_LWL<7> B_LWL<6> B_LWL<5> B_LWL<4> B_LWL<3> B_LWL<2> B_LWL<1> B_LWL<0> B_RWL<15> B_RWL<14> B_RWL<13> B_RWL<12> B_RWL<11> B_RWL<10> B_RWL<9> B_RWL<8> B_RWL<7> B_RWL<6> B_RWL<5> B_RWL<4> B_RWL<3> B_RWL<2> B_RWL<1> B_RWL<0> VDD_CORE VSS / RM_IHPSG13_1024x32_c2_2P_BITKIT_16x2_SRAM +XEDGE<1> A_BLC_TOP<1> A_BLC_TOP<0> A_BLT_TOP<1> A_BLT_TOP<0> B_BLC_TOP<1> B_BLC_TOP<0> B_BLT_TOP<1> B_BLT_TOP<0> VDD_CORE VSS / RM_IHPSG13_1024x32_c2_2P_BITKIT_16x2_EDGE_TB +XEDGE<0> A_BLC_BOT<1> A_BLC_BOT<0> A_BLT_BOT<1> A_BLT_BOT<0> B_BLC_BOT<1> B_BLC_BOT<0> B_BLT_BOT<1> B_BLT_BOT<0> VDD_CORE VSS / RM_IHPSG13_1024x32_c2_2P_BITKIT_16x2_EDGE_TB +.ENDS + + + + +.SUBCKT RM_IHPSG13_1024x32_c2_2P_MATRIX_pcell_1 A_BLC<63> A_BLC<62> A_BLC<61> A_BLC<60> A_BLC<59> A_BLC<58> A_BLC<57> A_BLC<56> A_BLC<55> A_BLC<54> A_BLC<53> A_BLC<52> A_BLC<51> A_BLC<50> A_BLC<49> A_BLC<48> A_BLC<47> A_BLC<46> A_BLC<45> A_BLC<44> A_BLC<43> A_BLC<42> A_BLC<41> A_BLC<40> A_BLC<39> A_BLC<38> A_BLC<37> A_BLC<36> A_BLC<35> A_BLC<34> A_BLC<33> A_BLC<32> A_BLC<31> A_BLC<30> A_BLC<29> A_BLC<28> A_BLC<27> A_BLC<26> A_BLC<25> A_BLC<24> A_BLC<23> A_BLC<22> A_BLC<21> A_BLC<20> A_BLC<19> A_BLC<18> A_BLC<17> A_BLC<16> A_BLC<15> A_BLC<14> A_BLC<13> A_BLC<12> A_BLC<11> A_BLC<10> A_BLC<9> A_BLC<8> A_BLC<7> A_BLC<6> A_BLC<5> A_BLC<4> A_BLC<3> A_BLC<2> A_BLC<1> A_BLC<0> A_BLT<63> A_BLT<62> A_BLT<61> A_BLT<60> A_BLT<59> A_BLT<58> A_BLT<57> A_BLT<56> A_BLT<55> A_BLT<54> A_BLT<53> A_BLT<52> A_BLT<51> A_BLT<50> A_BLT<49> A_BLT<48> A_BLT<47> A_BLT<46> A_BLT<45> A_BLT<44> A_BLT<43> A_BLT<42> A_BLT<41> A_BLT<40> A_BLT<39> A_BLT<38> A_BLT<37> A_BLT<36> A_BLT<35> A_BLT<34> A_BLT<33> A_BLT<32> A_BLT<31> A_BLT<30> A_BLT<29> A_BLT<28> A_BLT<27> A_BLT<26> A_BLT<25> A_BLT<24> A_BLT<23> A_BLT<22> A_BLT<21> A_BLT<20> A_BLT<19> A_BLT<18> A_BLT<17> A_BLT<16> A_BLT<15> A_BLT<14> A_BLT<13> A_BLT<12> A_BLT<11> A_BLT<10> A_BLT<9> A_BLT<8> A_BLT<7> A_BLT<6> A_BLT<5> A_BLT<4> A_BLT<3> A_BLT<2> A_BLT<1> A_BLT<0> A_WL<255> A_WL<254> A_WL<253> A_WL<252> A_WL<251> A_WL<250> A_WL<249> A_WL<248> A_WL<247> A_WL<246> A_WL<245> A_WL<244> A_WL<243> A_WL<242> A_WL<241> A_WL<240> A_WL<239> A_WL<238> A_WL<237> A_WL<236> A_WL<235> A_WL<234> A_WL<233> A_WL<232> A_WL<231> A_WL<230> A_WL<229> A_WL<228> A_WL<227> A_WL<226> A_WL<225> A_WL<224> A_WL<223> A_WL<222> A_WL<221> A_WL<220> A_WL<219> A_WL<218> A_WL<217> A_WL<216> A_WL<215> A_WL<214> A_WL<213> A_WL<212> A_WL<211> A_WL<210> A_WL<209> A_WL<208> A_WL<207> A_WL<206> A_WL<205> A_WL<204> A_WL<203> A_WL<202> A_WL<201> A_WL<200> A_WL<199> A_WL<198> A_WL<197> A_WL<196> A_WL<195> A_WL<194> A_WL<193> A_WL<192> A_WL<191> A_WL<190> A_WL<189> A_WL<188> A_WL<187> A_WL<186> A_WL<185> A_WL<184> A_WL<183> A_WL<182> A_WL<181> A_WL<180> A_WL<179> A_WL<178> A_WL<177> A_WL<176> A_WL<175> A_WL<174> A_WL<173> A_WL<172> A_WL<171> A_WL<170> A_WL<169> A_WL<168> A_WL<167> A_WL<166> A_WL<165> A_WL<164> A_WL<163> A_WL<162> A_WL<161> A_WL<160> A_WL<159> A_WL<158> A_WL<157> A_WL<156> A_WL<155> A_WL<154> A_WL<153> A_WL<152> A_WL<151> A_WL<150> A_WL<149> A_WL<148> A_WL<147> A_WL<146> A_WL<145> A_WL<144> A_WL<143> A_WL<142> A_WL<141> A_WL<140> A_WL<139> A_WL<138> A_WL<137> A_WL<136> A_WL<135> A_WL<134> A_WL<133> A_WL<132> A_WL<131> A_WL<130> A_WL<129> A_WL<128> A_WL<127> A_WL<126> A_WL<125> A_WL<124> A_WL<123> A_WL<122> A_WL<121> A_WL<120> A_WL<119> A_WL<118> A_WL<117> A_WL<116> A_WL<115> A_WL<114> A_WL<113> A_WL<112> A_WL<111> A_WL<110> A_WL<109> A_WL<108> A_WL<107> A_WL<106> A_WL<105> A_WL<104> A_WL<103> A_WL<102> A_WL<101> A_WL<100> A_WL<99> A_WL<98> A_WL<97> A_WL<96> A_WL<95> A_WL<94> A_WL<93> A_WL<92> A_WL<91> A_WL<90> A_WL<89> A_WL<88> A_WL<87> A_WL<86> A_WL<85> A_WL<84> A_WL<83> A_WL<82> A_WL<81> A_WL<80> A_WL<79> A_WL<78> A_WL<77> A_WL<76> A_WL<75> A_WL<74> A_WL<73> A_WL<72> A_WL<71> A_WL<70> A_WL<69> A_WL<68> A_WL<67> A_WL<66> A_WL<65> A_WL<64> A_WL<63> A_WL<62> A_WL<61> A_WL<60> A_WL<59> A_WL<58> A_WL<57> A_WL<56> A_WL<55> A_WL<54> A_WL<53> A_WL<52> A_WL<51> A_WL<50> A_WL<49> A_WL<48> A_WL<47> A_WL<46> A_WL<45> A_WL<44> A_WL<43> A_WL<42> A_WL<41> A_WL<40> A_WL<39> A_WL<38> A_WL<37> A_WL<36> A_WL<35> A_WL<34> A_WL<33> A_WL<32> A_WL<31> A_WL<30> A_WL<29> A_WL<28> A_WL<27> A_WL<26> A_WL<25> A_WL<24> A_WL<23> A_WL<22> A_WL<21> A_WL<20> A_WL<19> A_WL<18> A_WL<17> A_WL<16> A_WL<15> A_WL<14> A_WL<13> A_WL<12> A_WL<11> A_WL<10> A_WL<9> A_WL<8> A_WL<7> A_WL<6> A_WL<5> A_WL<4> A_WL<3> A_WL<2> A_WL<1> A_WL<0> B_BLC<63> B_BLC<62> B_BLC<61> B_BLC<60> B_BLC<59> B_BLC<58> B_BLC<57> B_BLC<56> B_BLC<55> B_BLC<54> B_BLC<53> B_BLC<52> B_BLC<51> B_BLC<50> B_BLC<49> B_BLC<48> B_BLC<47> B_BLC<46> B_BLC<45> B_BLC<44> B_BLC<43> B_BLC<42> B_BLC<41> B_BLC<40> B_BLC<39> B_BLC<38> B_BLC<37> B_BLC<36> B_BLC<35> B_BLC<34> B_BLC<33> B_BLC<32> B_BLC<31> B_BLC<30> B_BLC<29> B_BLC<28> B_BLC<27> B_BLC<26> B_BLC<25> B_BLC<24> B_BLC<23> B_BLC<22> B_BLC<21> B_BLC<20> B_BLC<19> B_BLC<18> B_BLC<17> B_BLC<16> B_BLC<15> B_BLC<14> B_BLC<13> B_BLC<12> B_BLC<11> B_BLC<10> B_BLC<9> B_BLC<8> B_BLC<7> B_BLC<6> B_BLC<5> B_BLC<4> B_BLC<3> B_BLC<2> B_BLC<1> B_BLC<0> B_BLT<63> B_BLT<62> B_BLT<61> B_BLT<60> B_BLT<59> B_BLT<58> B_BLT<57> B_BLT<56> B_BLT<55> B_BLT<54> B_BLT<53> B_BLT<52> B_BLT<51> B_BLT<50> B_BLT<49> B_BLT<48> B_BLT<47> B_BLT<46> B_BLT<45> B_BLT<44> B_BLT<43> B_BLT<42> B_BLT<41> B_BLT<40> B_BLT<39> B_BLT<38> B_BLT<37> B_BLT<36> B_BLT<35> B_BLT<34> B_BLT<33> B_BLT<32> B_BLT<31> B_BLT<30> B_BLT<29> B_BLT<28> B_BLT<27> B_BLT<26> B_BLT<25> B_BLT<24> B_BLT<23> B_BLT<22> B_BLT<21> B_BLT<20> B_BLT<19> B_BLT<18> B_BLT<17> B_BLT<16> B_BLT<15> B_BLT<14> B_BLT<13> B_BLT<12> B_BLT<11> B_BLT<10> B_BLT<9> B_BLT<8> B_BLT<7> B_BLT<6> B_BLT<5> B_BLT<4> B_BLT<3> B_BLT<2> B_BLT<1> B_BLT<0> B_WL<255> B_WL<254> B_WL<253> B_WL<252> B_WL<251> B_WL<250> B_WL<249> B_WL<248> B_WL<247> B_WL<246> B_WL<245> B_WL<244> B_WL<243> B_WL<242> B_WL<241> B_WL<240> B_WL<239> B_WL<238> B_WL<237> B_WL<236> B_WL<235> B_WL<234> B_WL<233> B_WL<232> B_WL<231> B_WL<230> B_WL<229> B_WL<228> B_WL<227> B_WL<226> B_WL<225> B_WL<224> B_WL<223> B_WL<222> B_WL<221> B_WL<220> B_WL<219> B_WL<218> B_WL<217> B_WL<216> B_WL<215> B_WL<214> B_WL<213> B_WL<212> B_WL<211> B_WL<210> B_WL<209> B_WL<208> B_WL<207> B_WL<206> B_WL<205> B_WL<204> B_WL<203> B_WL<202> B_WL<201> B_WL<200> B_WL<199> B_WL<198> B_WL<197> B_WL<196> B_WL<195> B_WL<194> B_WL<193> B_WL<192> B_WL<191> B_WL<190> B_WL<189> B_WL<188> B_WL<187> B_WL<186> B_WL<185> B_WL<184> B_WL<183> B_WL<182> B_WL<181> B_WL<180> B_WL<179> B_WL<178> B_WL<177> B_WL<176> B_WL<175> B_WL<174> B_WL<173> B_WL<172> B_WL<171> B_WL<170> B_WL<169> B_WL<168> B_WL<167> B_WL<166> B_WL<165> B_WL<164> B_WL<163> B_WL<162> B_WL<161> B_WL<160> B_WL<159> B_WL<158> B_WL<157> B_WL<156> B_WL<155> B_WL<154> B_WL<153> B_WL<152> B_WL<151> B_WL<150> B_WL<149> B_WL<148> B_WL<147> B_WL<146> B_WL<145> B_WL<144> B_WL<143> B_WL<142> B_WL<141> B_WL<140> B_WL<139> B_WL<138> B_WL<137> B_WL<136> B_WL<135> B_WL<134> B_WL<133> B_WL<132> B_WL<131> B_WL<130> B_WL<129> B_WL<128> B_WL<127> B_WL<126> B_WL<125> B_WL<124> B_WL<123> B_WL<122> B_WL<121> B_WL<120> B_WL<119> B_WL<118> B_WL<117> B_WL<116> B_WL<115> B_WL<114> B_WL<113> B_WL<112> B_WL<111> B_WL<110> B_WL<109> B_WL<108> B_WL<107> B_WL<106> B_WL<105> B_WL<104> B_WL<103> B_WL<102> B_WL<101> B_WL<100> B_WL<99> B_WL<98> B_WL<97> B_WL<96> B_WL<95> B_WL<94> B_WL<93> B_WL<92> B_WL<91> B_WL<90> B_WL<89> B_WL<88> B_WL<87> B_WL<86> B_WL<85> B_WL<84> B_WL<83> B_WL<82> B_WL<81> B_WL<80> B_WL<79> B_WL<78> B_WL<77> B_WL<76> B_WL<75> B_WL<74> B_WL<73> B_WL<72> B_WL<71> B_WL<70> B_WL<69> B_WL<68> B_WL<67> B_WL<66> B_WL<65> B_WL<64> B_WL<63> B_WL<62> B_WL<61> B_WL<60> B_WL<59> B_WL<58> B_WL<57> B_WL<56> B_WL<55> B_WL<54> B_WL<53> B_WL<52> B_WL<51> B_WL<50> B_WL<49> B_WL<48> B_WL<47> B_WL<46> B_WL<45> B_WL<44> B_WL<43> B_WL<42> B_WL<41> B_WL<40> B_WL<39> B_WL<38> B_WL<37> B_WL<36> B_WL<35> B_WL<34> B_WL<33> B_WL<32> B_WL<31> B_WL<30> B_WL<29> B_WL<28> B_WL<27> B_WL<26> B_WL<25> B_WL<24> B_WL<23> B_WL<22> B_WL<21> B_WL<20> B_WL<19> B_WL<18> B_WL<17> B_WL<16> B_WL<15> B_WL<14> B_WL<13> B_WL<12> B_WL<11> B_WL<10> B_WL<9> B_WL<8> B_WL<7> B_WL<6> B_WL<5> B_WL<4> B_WL<3> B_WL<2> B_WL<1> B_WL<0> VDD_CORE VSS +XCORNER<3> VDD_CORE VSS / RM_IHPSG13_1024x32_c2_2P_BITKIT_16x2_CORNER +XCORNER<2> VDD_CORE VSS / RM_IHPSG13_1024x32_c2_2P_BITKIT_16x2_CORNER +XCORNER<1> VDD_CORE VSS / RM_IHPSG13_1024x32_c2_2P_BITKIT_16x2_CORNER +XCORNER<0> VDD_CORE VSS / RM_IHPSG13_1024x32_c2_2P_BITKIT_16x2_CORNER +XRAMEDGE_L<15> A_WL<255> A_WL<254> A_WL<253> A_WL<252> A_WL<251> A_WL<250> A_WL<249> A_WL<248> A_WL<247> A_WL<246> A_WL<245> A_WL<244> A_WL<243> A_WL<242> A_WL<241> A_WL<240> B_WL<255> B_WL<254> B_WL<253> B_WL<252> B_WL<251> B_WL<250> B_WL<249> B_WL<248> B_WL<247> B_WL<246> B_WL<245> B_WL<244> B_WL<243> B_WL<242> B_WL<241> B_WL<240> VDD_CORE VSS / RM_IHPSG13_1024x32_c2_2P_BITKIT_16x2_EDGE_LR +XRAMEDGE_L<14> A_WL<239> A_WL<238> A_WL<237> A_WL<236> A_WL<235> A_WL<234> A_WL<233> A_WL<232> A_WL<231> A_WL<230> A_WL<229> A_WL<228> A_WL<227> A_WL<226> A_WL<225> A_WL<224> B_WL<239> B_WL<238> B_WL<237> B_WL<236> B_WL<235> B_WL<234> B_WL<233> B_WL<232> B_WL<231> B_WL<230> B_WL<229> B_WL<228> B_WL<227> B_WL<226> B_WL<225> B_WL<224> VDD_CORE VSS / RM_IHPSG13_1024x32_c2_2P_BITKIT_16x2_EDGE_LR +XRAMEDGE_L<13> A_WL<223> A_WL<222> A_WL<221> A_WL<220> A_WL<219> A_WL<218> A_WL<217> A_WL<216> A_WL<215> A_WL<214> A_WL<213> A_WL<212> A_WL<211> A_WL<210> A_WL<209> A_WL<208> B_WL<223> B_WL<222> B_WL<221> B_WL<220> B_WL<219> B_WL<218> B_WL<217> B_WL<216> B_WL<215> B_WL<214> B_WL<213> B_WL<212> B_WL<211> B_WL<210> B_WL<209> B_WL<208> VDD_CORE VSS / RM_IHPSG13_1024x32_c2_2P_BITKIT_16x2_EDGE_LR +XRAMEDGE_L<12> A_WL<207> A_WL<206> A_WL<205> A_WL<204> A_WL<203> A_WL<202> A_WL<201> A_WL<200> A_WL<199> A_WL<198> A_WL<197> A_WL<196> A_WL<195> A_WL<194> A_WL<193> A_WL<192> B_WL<207> B_WL<206> B_WL<205> B_WL<204> B_WL<203> B_WL<202> B_WL<201> B_WL<200> B_WL<199> B_WL<198> B_WL<197> B_WL<196> B_WL<195> B_WL<194> B_WL<193> B_WL<192> VDD_CORE VSS / RM_IHPSG13_1024x32_c2_2P_BITKIT_16x2_EDGE_LR +XRAMEDGE_L<11> A_WL<191> A_WL<190> A_WL<189> A_WL<188> A_WL<187> A_WL<186> A_WL<185> A_WL<184> A_WL<183> A_WL<182> A_WL<181> A_WL<180> A_WL<179> A_WL<178> A_WL<177> A_WL<176> B_WL<191> B_WL<190> B_WL<189> B_WL<188> B_WL<187> B_WL<186> B_WL<185> B_WL<184> B_WL<183> B_WL<182> B_WL<181> B_WL<180> B_WL<179> B_WL<178> B_WL<177> B_WL<176> VDD_CORE VSS / RM_IHPSG13_1024x32_c2_2P_BITKIT_16x2_EDGE_LR +XRAMEDGE_L<10> A_WL<175> A_WL<174> A_WL<173> A_WL<172> A_WL<171> A_WL<170> A_WL<169> A_WL<168> A_WL<167> A_WL<166> A_WL<165> A_WL<164> A_WL<163> A_WL<162> A_WL<161> A_WL<160> B_WL<175> B_WL<174> B_WL<173> B_WL<172> B_WL<171> B_WL<170> B_WL<169> B_WL<168> B_WL<167> B_WL<166> B_WL<165> B_WL<164> B_WL<163> B_WL<162> B_WL<161> B_WL<160> VDD_CORE VSS / RM_IHPSG13_1024x32_c2_2P_BITKIT_16x2_EDGE_LR +XRAMEDGE_L<9> A_WL<159> A_WL<158> A_WL<157> A_WL<156> A_WL<155> A_WL<154> A_WL<153> A_WL<152> A_WL<151> A_WL<150> A_WL<149> A_WL<148> A_WL<147> A_WL<146> A_WL<145> A_WL<144> B_WL<159> B_WL<158> B_WL<157> B_WL<156> B_WL<155> B_WL<154> B_WL<153> B_WL<152> B_WL<151> B_WL<150> B_WL<149> B_WL<148> B_WL<147> B_WL<146> B_WL<145> B_WL<144> VDD_CORE VSS / RM_IHPSG13_1024x32_c2_2P_BITKIT_16x2_EDGE_LR +XRAMEDGE_L<8> A_WL<143> A_WL<142> A_WL<141> A_WL<140> A_WL<139> A_WL<138> A_WL<137> A_WL<136> A_WL<135> A_WL<134> A_WL<133> A_WL<132> A_WL<131> A_WL<130> A_WL<129> A_WL<128> B_WL<143> B_WL<142> B_WL<141> B_WL<140> B_WL<139> B_WL<138> B_WL<137> B_WL<136> B_WL<135> B_WL<134> B_WL<133> B_WL<132> B_WL<131> B_WL<130> B_WL<129> B_WL<128> VDD_CORE VSS / RM_IHPSG13_1024x32_c2_2P_BITKIT_16x2_EDGE_LR +XRAMEDGE_L<7> A_WL<127> A_WL<126> A_WL<125> A_WL<124> A_WL<123> A_WL<122> A_WL<121> A_WL<120> A_WL<119> A_WL<118> A_WL<117> A_WL<116> A_WL<115> A_WL<114> A_WL<113> A_WL<112> B_WL<127> B_WL<126> B_WL<125> B_WL<124> B_WL<123> B_WL<122> B_WL<121> B_WL<120> B_WL<119> B_WL<118> B_WL<117> B_WL<116> B_WL<115> B_WL<114> B_WL<113> B_WL<112> VDD_CORE VSS / RM_IHPSG13_1024x32_c2_2P_BITKIT_16x2_EDGE_LR +XRAMEDGE_L<6> A_WL<111> A_WL<110> A_WL<109> A_WL<108> A_WL<107> A_WL<106> A_WL<105> A_WL<104> A_WL<103> A_WL<102> A_WL<101> A_WL<100> A_WL<99> A_WL<98> A_WL<97> A_WL<96> B_WL<111> B_WL<110> B_WL<109> B_WL<108> B_WL<107> B_WL<106> B_WL<105> B_WL<104> B_WL<103> B_WL<102> B_WL<101> B_WL<100> B_WL<99> B_WL<98> B_WL<97> B_WL<96> VDD_CORE VSS / RM_IHPSG13_1024x32_c2_2P_BITKIT_16x2_EDGE_LR +XRAMEDGE_L<5> A_WL<95> A_WL<94> A_WL<93> A_WL<92> A_WL<91> A_WL<90> A_WL<89> A_WL<88> A_WL<87> A_WL<86> A_WL<85> A_WL<84> A_WL<83> A_WL<82> A_WL<81> A_WL<80> B_WL<95> B_WL<94> B_WL<93> B_WL<92> B_WL<91> B_WL<90> B_WL<89> B_WL<88> B_WL<87> B_WL<86> B_WL<85> B_WL<84> B_WL<83> B_WL<82> B_WL<81> B_WL<80> VDD_CORE VSS / RM_IHPSG13_1024x32_c2_2P_BITKIT_16x2_EDGE_LR +XRAMEDGE_L<4> A_WL<79> A_WL<78> A_WL<77> A_WL<76> A_WL<75> A_WL<74> A_WL<73> A_WL<72> A_WL<71> A_WL<70> A_WL<69> A_WL<68> A_WL<67> A_WL<66> A_WL<65> A_WL<64> B_WL<79> B_WL<78> B_WL<77> B_WL<76> B_WL<75> B_WL<74> B_WL<73> B_WL<72> B_WL<71> B_WL<70> B_WL<69> B_WL<68> B_WL<67> B_WL<66> B_WL<65> B_WL<64> VDD_CORE VSS / RM_IHPSG13_1024x32_c2_2P_BITKIT_16x2_EDGE_LR +XRAMEDGE_L<3> A_WL<63> A_WL<62> A_WL<61> A_WL<60> A_WL<59> A_WL<58> A_WL<57> A_WL<56> A_WL<55> A_WL<54> A_WL<53> A_WL<52> A_WL<51> A_WL<50> A_WL<49> A_WL<48> B_WL<63> B_WL<62> B_WL<61> B_WL<60> B_WL<59> B_WL<58> B_WL<57> B_WL<56> B_WL<55> B_WL<54> B_WL<53> B_WL<52> B_WL<51> B_WL<50> B_WL<49> B_WL<48> VDD_CORE VSS / RM_IHPSG13_1024x32_c2_2P_BITKIT_16x2_EDGE_LR +XRAMEDGE_L<2> A_WL<47> A_WL<46> A_WL<45> A_WL<44> A_WL<43> A_WL<42> A_WL<41> A_WL<40> A_WL<39> A_WL<38> A_WL<37> A_WL<36> A_WL<35> A_WL<34> A_WL<33> A_WL<32> B_WL<47> B_WL<46> B_WL<45> B_WL<44> B_WL<43> B_WL<42> B_WL<41> B_WL<40> B_WL<39> B_WL<38> B_WL<37> B_WL<36> B_WL<35> B_WL<34> B_WL<33> B_WL<32> VDD_CORE VSS / RM_IHPSG13_1024x32_c2_2P_BITKIT_16x2_EDGE_LR +XRAMEDGE_L<1> A_WL<31> A_WL<30> A_WL<29> A_WL<28> A_WL<27> A_WL<26> A_WL<25> A_WL<24> A_WL<23> A_WL<22> A_WL<21> A_WL<20> A_WL<19> A_WL<18> A_WL<17> A_WL<16> B_WL<31> B_WL<30> B_WL<29> B_WL<28> B_WL<27> B_WL<26> B_WL<25> B_WL<24> B_WL<23> B_WL<22> B_WL<21> B_WL<20> B_WL<19> B_WL<18> B_WL<17> B_WL<16> VDD_CORE VSS / RM_IHPSG13_1024x32_c2_2P_BITKIT_16x2_EDGE_LR +XRAMEDGE_L<0> A_WL<15> A_WL<14> A_WL<13> A_WL<12> A_WL<11> A_WL<10> A_WL<9> A_WL<8> A_WL<7> A_WL<6> A_WL<5> A_WL<4> A_WL<3> A_WL<2> A_WL<1> A_WL<0> B_WL<15> B_WL<14> B_WL<13> B_WL<12> B_WL<11> B_WL<10> B_WL<9> B_WL<8> B_WL<7> B_WL<6> B_WL<5> B_WL<4> B_WL<3> B_WL<2> B_WL<1> B_WL<0> VDD_CORE VSS / RM_IHPSG13_1024x32_c2_2P_BITKIT_16x2_EDGE_LR +XRAMEDGE_R<15> A_IWL<8191> A_IWL<8190> A_IWL<8189> A_IWL<8188> A_IWL<8187> A_IWL<8186> A_IWL<8185> A_IWL<8184> A_IWL<8183> A_IWL<8182> A_IWL<8181> A_IWL<8180> A_IWL<8179> A_IWL<8178> A_IWL<8177> A_IWL<8176> B_IWL<8191> B_IWL<8190> B_IWL<8189> B_IWL<8188> B_IWL<8187> B_IWL<8186> B_IWL<8185> B_IWL<8184> B_IWL<8183> B_IWL<8182> B_IWL<8181> B_IWL<8180> B_IWL<8179> B_IWL<8178> B_IWL<8177> B_IWL<8176> VDD_CORE VSS / RM_IHPSG13_1024x32_c2_2P_BITKIT_16x2_EDGE_LR +XRAMEDGE_R<14> A_IWL<8175> A_IWL<8174> A_IWL<8173> A_IWL<8172> A_IWL<8171> A_IWL<8170> A_IWL<8169> A_IWL<8168> A_IWL<8167> A_IWL<8166> A_IWL<8165> A_IWL<8164> A_IWL<8163> A_IWL<8162> A_IWL<8161> A_IWL<8160> B_IWL<8175> B_IWL<8174> B_IWL<8173> B_IWL<8172> B_IWL<8171> B_IWL<8170> B_IWL<8169> B_IWL<8168> B_IWL<8167> B_IWL<8166> B_IWL<8165> B_IWL<8164> B_IWL<8163> B_IWL<8162> B_IWL<8161> B_IWL<8160> VDD_CORE VSS / RM_IHPSG13_1024x32_c2_2P_BITKIT_16x2_EDGE_LR +XRAMEDGE_R<13> A_IWL<8159> A_IWL<8158> A_IWL<8157> A_IWL<8156> A_IWL<8155> A_IWL<8154> A_IWL<8153> A_IWL<8152> A_IWL<8151> A_IWL<8150> A_IWL<8149> A_IWL<8148> A_IWL<8147> A_IWL<8146> A_IWL<8145> A_IWL<8144> B_IWL<8159> B_IWL<8158> B_IWL<8157> B_IWL<8156> B_IWL<8155> B_IWL<8154> B_IWL<8153> B_IWL<8152> B_IWL<8151> B_IWL<8150> B_IWL<8149> B_IWL<8148> B_IWL<8147> B_IWL<8146> B_IWL<8145> B_IWL<8144> VDD_CORE VSS / RM_IHPSG13_1024x32_c2_2P_BITKIT_16x2_EDGE_LR +XRAMEDGE_R<12> A_IWL<8143> A_IWL<8142> A_IWL<8141> A_IWL<8140> A_IWL<8139> A_IWL<8138> A_IWL<8137> A_IWL<8136> A_IWL<8135> A_IWL<8134> A_IWL<8133> A_IWL<8132> A_IWL<8131> A_IWL<8130> A_IWL<8129> A_IWL<8128> B_IWL<8143> B_IWL<8142> B_IWL<8141> B_IWL<8140> B_IWL<8139> B_IWL<8138> B_IWL<8137> B_IWL<8136> B_IWL<8135> B_IWL<8134> B_IWL<8133> B_IWL<8132> B_IWL<8131> B_IWL<8130> B_IWL<8129> B_IWL<8128> VDD_CORE VSS / RM_IHPSG13_1024x32_c2_2P_BITKIT_16x2_EDGE_LR +XRAMEDGE_R<11> A_IWL<8127> A_IWL<8126> A_IWL<8125> A_IWL<8124> A_IWL<8123> A_IWL<8122> A_IWL<8121> A_IWL<8120> A_IWL<8119> A_IWL<8118> A_IWL<8117> A_IWL<8116> A_IWL<8115> A_IWL<8114> A_IWL<8113> A_IWL<8112> B_IWL<8127> B_IWL<8126> B_IWL<8125> B_IWL<8124> B_IWL<8123> B_IWL<8122> B_IWL<8121> B_IWL<8120> B_IWL<8119> B_IWL<8118> B_IWL<8117> B_IWL<8116> B_IWL<8115> B_IWL<8114> B_IWL<8113> B_IWL<8112> VDD_CORE VSS / RM_IHPSG13_1024x32_c2_2P_BITKIT_16x2_EDGE_LR +XRAMEDGE_R<10> A_IWL<8111> A_IWL<8110> A_IWL<8109> A_IWL<8108> A_IWL<8107> A_IWL<8106> A_IWL<8105> A_IWL<8104> A_IWL<8103> A_IWL<8102> A_IWL<8101> A_IWL<8100> A_IWL<8099> A_IWL<8098> A_IWL<8097> A_IWL<8096> B_IWL<8111> B_IWL<8110> B_IWL<8109> B_IWL<8108> B_IWL<8107> B_IWL<8106> B_IWL<8105> B_IWL<8104> B_IWL<8103> B_IWL<8102> B_IWL<8101> B_IWL<8100> B_IWL<8099> B_IWL<8098> B_IWL<8097> B_IWL<8096> VDD_CORE VSS / RM_IHPSG13_1024x32_c2_2P_BITKIT_16x2_EDGE_LR +XRAMEDGE_R<9> A_IWL<8095> A_IWL<8094> A_IWL<8093> A_IWL<8092> A_IWL<8091> A_IWL<8090> A_IWL<8089> A_IWL<8088> A_IWL<8087> A_IWL<8086> A_IWL<8085> A_IWL<8084> A_IWL<8083> A_IWL<8082> A_IWL<8081> A_IWL<8080> B_IWL<8095> B_IWL<8094> B_IWL<8093> B_IWL<8092> B_IWL<8091> B_IWL<8090> B_IWL<8089> B_IWL<8088> B_IWL<8087> B_IWL<8086> B_IWL<8085> B_IWL<8084> B_IWL<8083> B_IWL<8082> B_IWL<8081> B_IWL<8080> VDD_CORE VSS / RM_IHPSG13_1024x32_c2_2P_BITKIT_16x2_EDGE_LR +XRAMEDGE_R<8> A_IWL<8079> A_IWL<8078> A_IWL<8077> A_IWL<8076> A_IWL<8075> A_IWL<8074> A_IWL<8073> A_IWL<8072> A_IWL<8071> A_IWL<8070> A_IWL<8069> A_IWL<8068> A_IWL<8067> A_IWL<8066> A_IWL<8065> A_IWL<8064> B_IWL<8079> B_IWL<8078> B_IWL<8077> B_IWL<8076> B_IWL<8075> B_IWL<8074> B_IWL<8073> B_IWL<8072> B_IWL<8071> B_IWL<8070> B_IWL<8069> B_IWL<8068> B_IWL<8067> B_IWL<8066> B_IWL<8065> B_IWL<8064> VDD_CORE VSS / RM_IHPSG13_1024x32_c2_2P_BITKIT_16x2_EDGE_LR +XRAMEDGE_R<7> A_IWL<8063> A_IWL<8062> A_IWL<8061> A_IWL<8060> A_IWL<8059> A_IWL<8058> A_IWL<8057> A_IWL<8056> A_IWL<8055> A_IWL<8054> A_IWL<8053> A_IWL<8052> A_IWL<8051> A_IWL<8050> A_IWL<8049> A_IWL<8048> B_IWL<8063> B_IWL<8062> B_IWL<8061> B_IWL<8060> B_IWL<8059> B_IWL<8058> B_IWL<8057> B_IWL<8056> B_IWL<8055> B_IWL<8054> B_IWL<8053> B_IWL<8052> B_IWL<8051> B_IWL<8050> B_IWL<8049> B_IWL<8048> VDD_CORE VSS / RM_IHPSG13_1024x32_c2_2P_BITKIT_16x2_EDGE_LR +XRAMEDGE_R<6> A_IWL<8047> A_IWL<8046> A_IWL<8045> A_IWL<8044> A_IWL<8043> A_IWL<8042> A_IWL<8041> A_IWL<8040> A_IWL<8039> A_IWL<8038> A_IWL<8037> A_IWL<8036> A_IWL<8035> A_IWL<8034> A_IWL<8033> A_IWL<8032> B_IWL<8047> B_IWL<8046> B_IWL<8045> B_IWL<8044> B_IWL<8043> B_IWL<8042> B_IWL<8041> B_IWL<8040> B_IWL<8039> B_IWL<8038> B_IWL<8037> B_IWL<8036> B_IWL<8035> B_IWL<8034> B_IWL<8033> B_IWL<8032> VDD_CORE VSS / RM_IHPSG13_1024x32_c2_2P_BITKIT_16x2_EDGE_LR +XRAMEDGE_R<5> A_IWL<8031> A_IWL<8030> A_IWL<8029> A_IWL<8028> A_IWL<8027> A_IWL<8026> A_IWL<8025> A_IWL<8024> A_IWL<8023> A_IWL<8022> A_IWL<8021> A_IWL<8020> A_IWL<8019> A_IWL<8018> A_IWL<8017> A_IWL<8016> B_IWL<8031> B_IWL<8030> B_IWL<8029> B_IWL<8028> B_IWL<8027> B_IWL<8026> B_IWL<8025> B_IWL<8024> B_IWL<8023> B_IWL<8022> B_IWL<8021> B_IWL<8020> B_IWL<8019> B_IWL<8018> B_IWL<8017> B_IWL<8016> VDD_CORE VSS / RM_IHPSG13_1024x32_c2_2P_BITKIT_16x2_EDGE_LR +XRAMEDGE_R<4> A_IWL<8015> A_IWL<8014> A_IWL<8013> A_IWL<8012> A_IWL<8011> A_IWL<8010> A_IWL<8009> A_IWL<8008> A_IWL<8007> A_IWL<8006> A_IWL<8005> A_IWL<8004> A_IWL<8003> A_IWL<8002> A_IWL<8001> A_IWL<8000> B_IWL<8015> B_IWL<8014> B_IWL<8013> B_IWL<8012> B_IWL<8011> B_IWL<8010> B_IWL<8009> B_IWL<8008> B_IWL<8007> B_IWL<8006> B_IWL<8005> B_IWL<8004> B_IWL<8003> B_IWL<8002> B_IWL<8001> B_IWL<8000> VDD_CORE VSS / RM_IHPSG13_1024x32_c2_2P_BITKIT_16x2_EDGE_LR +XRAMEDGE_R<3> A_IWL<7999> A_IWL<7998> A_IWL<7997> A_IWL<7996> A_IWL<7995> A_IWL<7994> A_IWL<7993> A_IWL<7992> A_IWL<7991> A_IWL<7990> A_IWL<7989> A_IWL<7988> A_IWL<7987> A_IWL<7986> A_IWL<7985> A_IWL<7984> B_IWL<7999> B_IWL<7998> B_IWL<7997> B_IWL<7996> B_IWL<7995> B_IWL<7994> B_IWL<7993> B_IWL<7992> B_IWL<7991> B_IWL<7990> B_IWL<7989> B_IWL<7988> B_IWL<7987> B_IWL<7986> B_IWL<7985> B_IWL<7984> VDD_CORE VSS / RM_IHPSG13_1024x32_c2_2P_BITKIT_16x2_EDGE_LR +XRAMEDGE_R<2> A_IWL<7983> A_IWL<7982> A_IWL<7981> A_IWL<7980> A_IWL<7979> A_IWL<7978> A_IWL<7977> A_IWL<7976> A_IWL<7975> A_IWL<7974> A_IWL<7973> A_IWL<7972> A_IWL<7971> A_IWL<7970> A_IWL<7969> A_IWL<7968> B_IWL<7983> B_IWL<7982> B_IWL<7981> B_IWL<7980> B_IWL<7979> B_IWL<7978> B_IWL<7977> B_IWL<7976> B_IWL<7975> B_IWL<7974> B_IWL<7973> B_IWL<7972> B_IWL<7971> B_IWL<7970> B_IWL<7969> B_IWL<7968> VDD_CORE VSS / RM_IHPSG13_1024x32_c2_2P_BITKIT_16x2_EDGE_LR +XRAMEDGE_R<1> A_IWL<7967> A_IWL<7966> A_IWL<7965> A_IWL<7964> A_IWL<7963> A_IWL<7962> A_IWL<7961> A_IWL<7960> A_IWL<7959> A_IWL<7958> A_IWL<7957> A_IWL<7956> A_IWL<7955> A_IWL<7954> A_IWL<7953> A_IWL<7952> B_IWL<7967> B_IWL<7966> B_IWL<7965> B_IWL<7964> B_IWL<7963> B_IWL<7962> B_IWL<7961> B_IWL<7960> B_IWL<7959> B_IWL<7958> B_IWL<7957> B_IWL<7956> B_IWL<7955> B_IWL<7954> B_IWL<7953> B_IWL<7952> VDD_CORE VSS / RM_IHPSG13_1024x32_c2_2P_BITKIT_16x2_EDGE_LR +XRAMEDGE_R<0> A_IWL<7951> A_IWL<7950> A_IWL<7949> A_IWL<7948> A_IWL<7947> A_IWL<7946> A_IWL<7945> A_IWL<7944> A_IWL<7943> A_IWL<7942> A_IWL<7941> A_IWL<7940> A_IWL<7939> A_IWL<7938> A_IWL<7937> A_IWL<7936> B_IWL<7951> B_IWL<7950> B_IWL<7949> B_IWL<7948> B_IWL<7947> B_IWL<7946> B_IWL<7945> B_IWL<7944> B_IWL<7943> B_IWL<7942> B_IWL<7941> B_IWL<7940> B_IWL<7939> B_IWL<7938> B_IWL<7937> B_IWL<7936> VDD_CORE VSS / RM_IHPSG13_1024x32_c2_2P_BITKIT_16x2_EDGE_LR +XCOL<31> A_BLC<63> A_BLC<62> A_BLC_TOP<63> A_BLC_TOP<62> A_BLT<63> A_BLT<62> A_BLT_TOP<63> A_BLT_TOP<62> A_IWL<7935> A_IWL<7934> A_IWL<7933> A_IWL<7932> A_IWL<7931> A_IWL<7930> A_IWL<7929> A_IWL<7928> A_IWL<7927> A_IWL<7926> A_IWL<7925> A_IWL<7924> A_IWL<7923> A_IWL<7922> A_IWL<7921> A_IWL<7920> A_IWL<7919> A_IWL<7918> A_IWL<7917> A_IWL<7916> A_IWL<7915> A_IWL<7914> A_IWL<7913> A_IWL<7912> A_IWL<7911> A_IWL<7910> A_IWL<7909> A_IWL<7908> A_IWL<7907> A_IWL<7906> A_IWL<7905> A_IWL<7904> A_IWL<7903> A_IWL<7902> A_IWL<7901> A_IWL<7900> A_IWL<7899> A_IWL<7898> A_IWL<7897> A_IWL<7896> A_IWL<7895> A_IWL<7894> A_IWL<7893> A_IWL<7892> A_IWL<7891> A_IWL<7890> A_IWL<7889> A_IWL<7888> A_IWL<7887> A_IWL<7886> A_IWL<7885> A_IWL<7884> A_IWL<7883> A_IWL<7882> A_IWL<7881> A_IWL<7880> A_IWL<7879> A_IWL<7878> A_IWL<7877> A_IWL<7876> A_IWL<7875> A_IWL<7874> A_IWL<7873> A_IWL<7872> A_IWL<7871> A_IWL<7870> A_IWL<7869> A_IWL<7868> A_IWL<7867> A_IWL<7866> A_IWL<7865> A_IWL<7864> A_IWL<7863> A_IWL<7862> A_IWL<7861> A_IWL<7860> A_IWL<7859> A_IWL<7858> A_IWL<7857> A_IWL<7856> A_IWL<7855> A_IWL<7854> A_IWL<7853> A_IWL<7852> A_IWL<7851> A_IWL<7850> A_IWL<7849> A_IWL<7848> A_IWL<7847> A_IWL<7846> A_IWL<7845> A_IWL<7844> A_IWL<7843> A_IWL<7842> A_IWL<7841> A_IWL<7840> A_IWL<7839> A_IWL<7838> A_IWL<7837> A_IWL<7836> A_IWL<7835> A_IWL<7834> A_IWL<7833> A_IWL<7832> A_IWL<7831> A_IWL<7830> A_IWL<7829> A_IWL<7828> A_IWL<7827> A_IWL<7826> A_IWL<7825> A_IWL<7824> A_IWL<7823> A_IWL<7822> A_IWL<7821> A_IWL<7820> A_IWL<7819> A_IWL<7818> A_IWL<7817> A_IWL<7816> A_IWL<7815> A_IWL<7814> A_IWL<7813> A_IWL<7812> A_IWL<7811> A_IWL<7810> A_IWL<7809> A_IWL<7808> A_IWL<7807> A_IWL<7806> A_IWL<7805> A_IWL<7804> A_IWL<7803> A_IWL<7802> A_IWL<7801> A_IWL<7800> A_IWL<7799> A_IWL<7798> A_IWL<7797> A_IWL<7796> A_IWL<7795> A_IWL<7794> A_IWL<7793> A_IWL<7792> A_IWL<7791> A_IWL<7790> A_IWL<7789> A_IWL<7788> A_IWL<7787> A_IWL<7786> A_IWL<7785> A_IWL<7784> A_IWL<7783> A_IWL<7782> A_IWL<7781> A_IWL<7780> A_IWL<7779> A_IWL<7778> A_IWL<7777> A_IWL<7776> A_IWL<7775> A_IWL<7774> A_IWL<7773> A_IWL<7772> A_IWL<7771> A_IWL<7770> A_IWL<7769> A_IWL<7768> A_IWL<7767> A_IWL<7766> A_IWL<7765> A_IWL<7764> A_IWL<7763> A_IWL<7762> A_IWL<7761> A_IWL<7760> A_IWL<7759> A_IWL<7758> A_IWL<7757> A_IWL<7756> A_IWL<7755> A_IWL<7754> A_IWL<7753> A_IWL<7752> A_IWL<7751> A_IWL<7750> A_IWL<7749> A_IWL<7748> A_IWL<7747> A_IWL<7746> A_IWL<7745> A_IWL<7744> A_IWL<7743> A_IWL<7742> A_IWL<7741> A_IWL<7740> A_IWL<7739> A_IWL<7738> A_IWL<7737> A_IWL<7736> A_IWL<7735> A_IWL<7734> A_IWL<7733> A_IWL<7732> A_IWL<7731> A_IWL<7730> A_IWL<7729> A_IWL<7728> A_IWL<7727> A_IWL<7726> A_IWL<7725> A_IWL<7724> A_IWL<7723> A_IWL<7722> A_IWL<7721> A_IWL<7720> A_IWL<7719> A_IWL<7718> A_IWL<7717> A_IWL<7716> A_IWL<7715> A_IWL<7714> A_IWL<7713> A_IWL<7712> A_IWL<7711> A_IWL<7710> A_IWL<7709> A_IWL<7708> A_IWL<7707> A_IWL<7706> A_IWL<7705> A_IWL<7704> A_IWL<7703> A_IWL<7702> A_IWL<7701> A_IWL<7700> A_IWL<7699> A_IWL<7698> A_IWL<7697> A_IWL<7696> A_IWL<7695> A_IWL<7694> A_IWL<7693> A_IWL<7692> A_IWL<7691> A_IWL<7690> A_IWL<7689> A_IWL<7688> A_IWL<7687> A_IWL<7686> A_IWL<7685> A_IWL<7684> A_IWL<7683> A_IWL<7682> A_IWL<7681> A_IWL<7680> A_IWL<8191> A_IWL<8190> A_IWL<8189> A_IWL<8188> A_IWL<8187> A_IWL<8186> A_IWL<8185> A_IWL<8184> A_IWL<8183> A_IWL<8182> A_IWL<8181> A_IWL<8180> A_IWL<8179> A_IWL<8178> A_IWL<8177> A_IWL<8176> A_IWL<8175> A_IWL<8174> A_IWL<8173> A_IWL<8172> A_IWL<8171> A_IWL<8170> A_IWL<8169> A_IWL<8168> A_IWL<8167> A_IWL<8166> A_IWL<8165> A_IWL<8164> A_IWL<8163> A_IWL<8162> A_IWL<8161> A_IWL<8160> A_IWL<8159> A_IWL<8158> A_IWL<8157> A_IWL<8156> A_IWL<8155> A_IWL<8154> A_IWL<8153> A_IWL<8152> A_IWL<8151> A_IWL<8150> A_IWL<8149> A_IWL<8148> A_IWL<8147> A_IWL<8146> A_IWL<8145> A_IWL<8144> A_IWL<8143> A_IWL<8142> A_IWL<8141> A_IWL<8140> A_IWL<8139> A_IWL<8138> A_IWL<8137> A_IWL<8136> A_IWL<8135> A_IWL<8134> A_IWL<8133> A_IWL<8132> A_IWL<8131> A_IWL<8130> A_IWL<8129> A_IWL<8128> A_IWL<8127> A_IWL<8126> A_IWL<8125> A_IWL<8124> A_IWL<8123> A_IWL<8122> A_IWL<8121> A_IWL<8120> A_IWL<8119> A_IWL<8118> A_IWL<8117> A_IWL<8116> A_IWL<8115> A_IWL<8114> A_IWL<8113> A_IWL<8112> A_IWL<8111> A_IWL<8110> A_IWL<8109> A_IWL<8108> A_IWL<8107> A_IWL<8106> A_IWL<8105> A_IWL<8104> A_IWL<8103> A_IWL<8102> A_IWL<8101> A_IWL<8100> A_IWL<8099> A_IWL<8098> A_IWL<8097> A_IWL<8096> A_IWL<8095> A_IWL<8094> A_IWL<8093> A_IWL<8092> A_IWL<8091> A_IWL<8090> A_IWL<8089> A_IWL<8088> A_IWL<8087> A_IWL<8086> A_IWL<8085> A_IWL<8084> A_IWL<8083> A_IWL<8082> A_IWL<8081> A_IWL<8080> A_IWL<8079> A_IWL<8078> A_IWL<8077> A_IWL<8076> A_IWL<8075> A_IWL<8074> A_IWL<8073> A_IWL<8072> A_IWL<8071> A_IWL<8070> A_IWL<8069> A_IWL<8068> A_IWL<8067> A_IWL<8066> A_IWL<8065> A_IWL<8064> A_IWL<8063> A_IWL<8062> A_IWL<8061> A_IWL<8060> A_IWL<8059> A_IWL<8058> A_IWL<8057> A_IWL<8056> A_IWL<8055> A_IWL<8054> A_IWL<8053> A_IWL<8052> A_IWL<8051> A_IWL<8050> A_IWL<8049> A_IWL<8048> A_IWL<8047> A_IWL<8046> A_IWL<8045> A_IWL<8044> A_IWL<8043> A_IWL<8042> A_IWL<8041> A_IWL<8040> A_IWL<8039> A_IWL<8038> A_IWL<8037> A_IWL<8036> A_IWL<8035> A_IWL<8034> A_IWL<8033> A_IWL<8032> A_IWL<8031> A_IWL<8030> A_IWL<8029> A_IWL<8028> A_IWL<8027> A_IWL<8026> A_IWL<8025> A_IWL<8024> A_IWL<8023> A_IWL<8022> A_IWL<8021> A_IWL<8020> A_IWL<8019> A_IWL<8018> A_IWL<8017> A_IWL<8016> A_IWL<8015> A_IWL<8014> A_IWL<8013> A_IWL<8012> A_IWL<8011> A_IWL<8010> A_IWL<8009> A_IWL<8008> A_IWL<8007> A_IWL<8006> A_IWL<8005> A_IWL<8004> A_IWL<8003> A_IWL<8002> A_IWL<8001> A_IWL<8000> A_IWL<7999> A_IWL<7998> A_IWL<7997> A_IWL<7996> A_IWL<7995> A_IWL<7994> A_IWL<7993> A_IWL<7992> A_IWL<7991> A_IWL<7990> A_IWL<7989> A_IWL<7988> A_IWL<7987> A_IWL<7986> A_IWL<7985> A_IWL<7984> A_IWL<7983> A_IWL<7982> A_IWL<7981> A_IWL<7980> A_IWL<7979> A_IWL<7978> A_IWL<7977> A_IWL<7976> A_IWL<7975> A_IWL<7974> A_IWL<7973> A_IWL<7972> A_IWL<7971> A_IWL<7970> A_IWL<7969> A_IWL<7968> A_IWL<7967> A_IWL<7966> A_IWL<7965> A_IWL<7964> A_IWL<7963> A_IWL<7962> A_IWL<7961> A_IWL<7960> A_IWL<7959> A_IWL<7958> A_IWL<7957> A_IWL<7956> A_IWL<7955> A_IWL<7954> A_IWL<7953> A_IWL<7952> A_IWL<7951> A_IWL<7950> A_IWL<7949> A_IWL<7948> A_IWL<7947> A_IWL<7946> A_IWL<7945> A_IWL<7944> A_IWL<7943> A_IWL<7942> A_IWL<7941> A_IWL<7940> A_IWL<7939> A_IWL<7938> A_IWL<7937> A_IWL<7936> B_BLC<63> B_BLC<62> B_BLC_TOP<63> B_BLC_TOP<62> B_BLT<63> B_BLT<62> B_BLT_TOP<63> B_BLT_TOP<62> B_IWL<7935> B_IWL<7934> B_IWL<7933> B_IWL<7932> B_IWL<7931> B_IWL<7930> B_IWL<7929> B_IWL<7928> B_IWL<7927> B_IWL<7926> B_IWL<7925> B_IWL<7924> B_IWL<7923> B_IWL<7922> B_IWL<7921> B_IWL<7920> B_IWL<7919> B_IWL<7918> B_IWL<7917> B_IWL<7916> B_IWL<7915> B_IWL<7914> B_IWL<7913> B_IWL<7912> B_IWL<7911> B_IWL<7910> B_IWL<7909> B_IWL<7908> B_IWL<7907> B_IWL<7906> B_IWL<7905> B_IWL<7904> B_IWL<7903> B_IWL<7902> B_IWL<7901> B_IWL<7900> B_IWL<7899> B_IWL<7898> B_IWL<7897> B_IWL<7896> B_IWL<7895> B_IWL<7894> B_IWL<7893> B_IWL<7892> B_IWL<7891> B_IWL<7890> B_IWL<7889> B_IWL<7888> B_IWL<7887> B_IWL<7886> B_IWL<7885> B_IWL<7884> B_IWL<7883> B_IWL<7882> B_IWL<7881> B_IWL<7880> B_IWL<7879> B_IWL<7878> B_IWL<7877> B_IWL<7876> B_IWL<7875> B_IWL<7874> B_IWL<7873> B_IWL<7872> B_IWL<7871> B_IWL<7870> B_IWL<7869> B_IWL<7868> B_IWL<7867> B_IWL<7866> B_IWL<7865> B_IWL<7864> B_IWL<7863> B_IWL<7862> B_IWL<7861> B_IWL<7860> B_IWL<7859> B_IWL<7858> B_IWL<7857> B_IWL<7856> B_IWL<7855> B_IWL<7854> B_IWL<7853> B_IWL<7852> B_IWL<7851> B_IWL<7850> B_IWL<7849> B_IWL<7848> B_IWL<7847> B_IWL<7846> B_IWL<7845> B_IWL<7844> B_IWL<7843> B_IWL<7842> B_IWL<7841> B_IWL<7840> B_IWL<7839> B_IWL<7838> B_IWL<7837> B_IWL<7836> B_IWL<7835> B_IWL<7834> B_IWL<7833> B_IWL<7832> B_IWL<7831> B_IWL<7830> B_IWL<7829> B_IWL<7828> B_IWL<7827> B_IWL<7826> B_IWL<7825> B_IWL<7824> B_IWL<7823> B_IWL<7822> B_IWL<7821> B_IWL<7820> B_IWL<7819> B_IWL<7818> B_IWL<7817> B_IWL<7816> B_IWL<7815> B_IWL<7814> B_IWL<7813> B_IWL<7812> B_IWL<7811> B_IWL<7810> B_IWL<7809> B_IWL<7808> B_IWL<7807> B_IWL<7806> B_IWL<7805> B_IWL<7804> B_IWL<7803> B_IWL<7802> B_IWL<7801> B_IWL<7800> B_IWL<7799> B_IWL<7798> B_IWL<7797> B_IWL<7796> B_IWL<7795> B_IWL<7794> B_IWL<7793> B_IWL<7792> B_IWL<7791> B_IWL<7790> B_IWL<7789> B_IWL<7788> B_IWL<7787> B_IWL<7786> B_IWL<7785> B_IWL<7784> B_IWL<7783> B_IWL<7782> B_IWL<7781> B_IWL<7780> B_IWL<7779> B_IWL<7778> B_IWL<7777> B_IWL<7776> B_IWL<7775> B_IWL<7774> B_IWL<7773> B_IWL<7772> B_IWL<7771> B_IWL<7770> B_IWL<7769> B_IWL<7768> B_IWL<7767> B_IWL<7766> B_IWL<7765> B_IWL<7764> B_IWL<7763> B_IWL<7762> B_IWL<7761> B_IWL<7760> B_IWL<7759> B_IWL<7758> B_IWL<7757> B_IWL<7756> B_IWL<7755> B_IWL<7754> B_IWL<7753> B_IWL<7752> B_IWL<7751> B_IWL<7750> B_IWL<7749> B_IWL<7748> B_IWL<7747> B_IWL<7746> B_IWL<7745> B_IWL<7744> B_IWL<7743> B_IWL<7742> B_IWL<7741> B_IWL<7740> B_IWL<7739> B_IWL<7738> B_IWL<7737> B_IWL<7736> B_IWL<7735> B_IWL<7734> B_IWL<7733> B_IWL<7732> B_IWL<7731> B_IWL<7730> B_IWL<7729> B_IWL<7728> B_IWL<7727> B_IWL<7726> B_IWL<7725> B_IWL<7724> B_IWL<7723> B_IWL<7722> B_IWL<7721> B_IWL<7720> B_IWL<7719> B_IWL<7718> B_IWL<7717> B_IWL<7716> B_IWL<7715> B_IWL<7714> B_IWL<7713> B_IWL<7712> B_IWL<7711> B_IWL<7710> B_IWL<7709> B_IWL<7708> B_IWL<7707> B_IWL<7706> B_IWL<7705> B_IWL<7704> B_IWL<7703> B_IWL<7702> B_IWL<7701> B_IWL<7700> B_IWL<7699> B_IWL<7698> B_IWL<7697> B_IWL<7696> B_IWL<7695> B_IWL<7694> B_IWL<7693> B_IWL<7692> B_IWL<7691> B_IWL<7690> B_IWL<7689> B_IWL<7688> B_IWL<7687> B_IWL<7686> B_IWL<7685> B_IWL<7684> B_IWL<7683> B_IWL<7682> B_IWL<7681> B_IWL<7680> B_IWL<8191> B_IWL<8190> B_IWL<8189> B_IWL<8188> B_IWL<8187> B_IWL<8186> B_IWL<8185> B_IWL<8184> B_IWL<8183> B_IWL<8182> B_IWL<8181> B_IWL<8180> B_IWL<8179> B_IWL<8178> B_IWL<8177> B_IWL<8176> B_IWL<8175> B_IWL<8174> B_IWL<8173> B_IWL<8172> B_IWL<8171> B_IWL<8170> B_IWL<8169> B_IWL<8168> B_IWL<8167> B_IWL<8166> B_IWL<8165> B_IWL<8164> B_IWL<8163> B_IWL<8162> B_IWL<8161> B_IWL<8160> B_IWL<8159> B_IWL<8158> B_IWL<8157> B_IWL<8156> B_IWL<8155> B_IWL<8154> B_IWL<8153> B_IWL<8152> B_IWL<8151> B_IWL<8150> B_IWL<8149> B_IWL<8148> B_IWL<8147> B_IWL<8146> B_IWL<8145> B_IWL<8144> B_IWL<8143> B_IWL<8142> B_IWL<8141> B_IWL<8140> B_IWL<8139> B_IWL<8138> B_IWL<8137> B_IWL<8136> B_IWL<8135> B_IWL<8134> B_IWL<8133> B_IWL<8132> B_IWL<8131> B_IWL<8130> B_IWL<8129> B_IWL<8128> B_IWL<8127> B_IWL<8126> B_IWL<8125> B_IWL<8124> B_IWL<8123> B_IWL<8122> B_IWL<8121> B_IWL<8120> B_IWL<8119> B_IWL<8118> B_IWL<8117> B_IWL<8116> B_IWL<8115> B_IWL<8114> B_IWL<8113> B_IWL<8112> B_IWL<8111> B_IWL<8110> B_IWL<8109> B_IWL<8108> B_IWL<8107> B_IWL<8106> B_IWL<8105> B_IWL<8104> B_IWL<8103> B_IWL<8102> B_IWL<8101> B_IWL<8100> B_IWL<8099> B_IWL<8098> B_IWL<8097> B_IWL<8096> B_IWL<8095> B_IWL<8094> B_IWL<8093> B_IWL<8092> B_IWL<8091> B_IWL<8090> B_IWL<8089> B_IWL<8088> B_IWL<8087> B_IWL<8086> B_IWL<8085> B_IWL<8084> B_IWL<8083> B_IWL<8082> B_IWL<8081> B_IWL<8080> B_IWL<8079> B_IWL<8078> B_IWL<8077> B_IWL<8076> B_IWL<8075> B_IWL<8074> B_IWL<8073> B_IWL<8072> B_IWL<8071> B_IWL<8070> B_IWL<8069> B_IWL<8068> B_IWL<8067> B_IWL<8066> B_IWL<8065> B_IWL<8064> B_IWL<8063> B_IWL<8062> B_IWL<8061> B_IWL<8060> B_IWL<8059> B_IWL<8058> B_IWL<8057> B_IWL<8056> B_IWL<8055> B_IWL<8054> B_IWL<8053> B_IWL<8052> B_IWL<8051> B_IWL<8050> B_IWL<8049> B_IWL<8048> B_IWL<8047> B_IWL<8046> B_IWL<8045> B_IWL<8044> B_IWL<8043> B_IWL<8042> B_IWL<8041> B_IWL<8040> B_IWL<8039> B_IWL<8038> B_IWL<8037> B_IWL<8036> B_IWL<8035> B_IWL<8034> B_IWL<8033> B_IWL<8032> B_IWL<8031> B_IWL<8030> B_IWL<8029> B_IWL<8028> B_IWL<8027> B_IWL<8026> B_IWL<8025> B_IWL<8024> B_IWL<8023> B_IWL<8022> B_IWL<8021> B_IWL<8020> B_IWL<8019> B_IWL<8018> B_IWL<8017> B_IWL<8016> B_IWL<8015> B_IWL<8014> B_IWL<8013> B_IWL<8012> B_IWL<8011> B_IWL<8010> B_IWL<8009> B_IWL<8008> B_IWL<8007> B_IWL<8006> B_IWL<8005> B_IWL<8004> B_IWL<8003> B_IWL<8002> B_IWL<8001> B_IWL<8000> B_IWL<7999> B_IWL<7998> B_IWL<7997> B_IWL<7996> B_IWL<7995> B_IWL<7994> B_IWL<7993> B_IWL<7992> B_IWL<7991> B_IWL<7990> B_IWL<7989> B_IWL<7988> B_IWL<7987> B_IWL<7986> B_IWL<7985> B_IWL<7984> B_IWL<7983> B_IWL<7982> B_IWL<7981> B_IWL<7980> B_IWL<7979> B_IWL<7978> B_IWL<7977> B_IWL<7976> B_IWL<7975> B_IWL<7974> B_IWL<7973> B_IWL<7972> B_IWL<7971> B_IWL<7970> B_IWL<7969> B_IWL<7968> B_IWL<7967> B_IWL<7966> B_IWL<7965> B_IWL<7964> B_IWL<7963> B_IWL<7962> B_IWL<7961> B_IWL<7960> B_IWL<7959> B_IWL<7958> B_IWL<7957> B_IWL<7956> B_IWL<7955> B_IWL<7954> B_IWL<7953> B_IWL<7952> B_IWL<7951> B_IWL<7950> B_IWL<7949> B_IWL<7948> B_IWL<7947> B_IWL<7946> B_IWL<7945> B_IWL<7944> B_IWL<7943> B_IWL<7942> B_IWL<7941> B_IWL<7940> B_IWL<7939> B_IWL<7938> B_IWL<7937> B_IWL<7936> VDD_CORE VSS / RM_IHPSG13_1024x32_c2_2P_COLUMN_pcell_0 +XCOL<30> A_BLC<61> A_BLC<60> A_BLC_TOP<61> A_BLC_TOP<60> A_BLT<61> A_BLT<60> A_BLT_TOP<61> A_BLT_TOP<60> A_IWL<7679> A_IWL<7678> A_IWL<7677> A_IWL<7676> A_IWL<7675> A_IWL<7674> A_IWL<7673> A_IWL<7672> A_IWL<7671> A_IWL<7670> A_IWL<7669> A_IWL<7668> A_IWL<7667> A_IWL<7666> A_IWL<7665> A_IWL<7664> A_IWL<7663> A_IWL<7662> A_IWL<7661> A_IWL<7660> A_IWL<7659> A_IWL<7658> A_IWL<7657> A_IWL<7656> A_IWL<7655> A_IWL<7654> A_IWL<7653> A_IWL<7652> A_IWL<7651> A_IWL<7650> A_IWL<7649> A_IWL<7648> A_IWL<7647> A_IWL<7646> A_IWL<7645> A_IWL<7644> A_IWL<7643> A_IWL<7642> A_IWL<7641> A_IWL<7640> A_IWL<7639> A_IWL<7638> A_IWL<7637> A_IWL<7636> A_IWL<7635> A_IWL<7634> A_IWL<7633> A_IWL<7632> A_IWL<7631> A_IWL<7630> A_IWL<7629> A_IWL<7628> A_IWL<7627> A_IWL<7626> A_IWL<7625> A_IWL<7624> A_IWL<7623> A_IWL<7622> A_IWL<7621> A_IWL<7620> A_IWL<7619> A_IWL<7618> A_IWL<7617> A_IWL<7616> A_IWL<7615> A_IWL<7614> A_IWL<7613> A_IWL<7612> A_IWL<7611> A_IWL<7610> A_IWL<7609> A_IWL<7608> A_IWL<7607> A_IWL<7606> A_IWL<7605> A_IWL<7604> A_IWL<7603> A_IWL<7602> A_IWL<7601> A_IWL<7600> A_IWL<7599> A_IWL<7598> A_IWL<7597> A_IWL<7596> A_IWL<7595> A_IWL<7594> A_IWL<7593> A_IWL<7592> A_IWL<7591> A_IWL<7590> A_IWL<7589> A_IWL<7588> A_IWL<7587> A_IWL<7586> A_IWL<7585> A_IWL<7584> A_IWL<7583> A_IWL<7582> A_IWL<7581> A_IWL<7580> A_IWL<7579> A_IWL<7578> A_IWL<7577> A_IWL<7576> A_IWL<7575> A_IWL<7574> A_IWL<7573> A_IWL<7572> A_IWL<7571> A_IWL<7570> A_IWL<7569> A_IWL<7568> A_IWL<7567> A_IWL<7566> A_IWL<7565> A_IWL<7564> A_IWL<7563> A_IWL<7562> A_IWL<7561> A_IWL<7560> A_IWL<7559> A_IWL<7558> A_IWL<7557> A_IWL<7556> A_IWL<7555> A_IWL<7554> A_IWL<7553> A_IWL<7552> A_IWL<7551> A_IWL<7550> A_IWL<7549> A_IWL<7548> A_IWL<7547> A_IWL<7546> A_IWL<7545> A_IWL<7544> A_IWL<7543> A_IWL<7542> A_IWL<7541> A_IWL<7540> A_IWL<7539> A_IWL<7538> A_IWL<7537> A_IWL<7536> A_IWL<7535> A_IWL<7534> A_IWL<7533> A_IWL<7532> A_IWL<7531> A_IWL<7530> A_IWL<7529> A_IWL<7528> A_IWL<7527> A_IWL<7526> A_IWL<7525> A_IWL<7524> A_IWL<7523> A_IWL<7522> A_IWL<7521> A_IWL<7520> A_IWL<7519> A_IWL<7518> A_IWL<7517> A_IWL<7516> A_IWL<7515> A_IWL<7514> A_IWL<7513> A_IWL<7512> A_IWL<7511> A_IWL<7510> A_IWL<7509> A_IWL<7508> A_IWL<7507> A_IWL<7506> A_IWL<7505> A_IWL<7504> A_IWL<7503> A_IWL<7502> A_IWL<7501> A_IWL<7500> A_IWL<7499> A_IWL<7498> A_IWL<7497> A_IWL<7496> A_IWL<7495> A_IWL<7494> A_IWL<7493> A_IWL<7492> A_IWL<7491> A_IWL<7490> A_IWL<7489> A_IWL<7488> A_IWL<7487> A_IWL<7486> A_IWL<7485> A_IWL<7484> A_IWL<7483> A_IWL<7482> A_IWL<7481> A_IWL<7480> A_IWL<7479> A_IWL<7478> A_IWL<7477> A_IWL<7476> A_IWL<7475> A_IWL<7474> A_IWL<7473> A_IWL<7472> A_IWL<7471> A_IWL<7470> A_IWL<7469> A_IWL<7468> A_IWL<7467> A_IWL<7466> A_IWL<7465> A_IWL<7464> A_IWL<7463> A_IWL<7462> A_IWL<7461> A_IWL<7460> A_IWL<7459> A_IWL<7458> A_IWL<7457> A_IWL<7456> A_IWL<7455> A_IWL<7454> A_IWL<7453> A_IWL<7452> A_IWL<7451> A_IWL<7450> A_IWL<7449> A_IWL<7448> A_IWL<7447> A_IWL<7446> A_IWL<7445> A_IWL<7444> A_IWL<7443> A_IWL<7442> A_IWL<7441> A_IWL<7440> A_IWL<7439> A_IWL<7438> A_IWL<7437> A_IWL<7436> A_IWL<7435> A_IWL<7434> A_IWL<7433> A_IWL<7432> A_IWL<7431> A_IWL<7430> A_IWL<7429> A_IWL<7428> A_IWL<7427> A_IWL<7426> A_IWL<7425> A_IWL<7424> A_IWL<7935> A_IWL<7934> A_IWL<7933> A_IWL<7932> A_IWL<7931> A_IWL<7930> A_IWL<7929> A_IWL<7928> A_IWL<7927> A_IWL<7926> A_IWL<7925> A_IWL<7924> A_IWL<7923> A_IWL<7922> A_IWL<7921> A_IWL<7920> A_IWL<7919> A_IWL<7918> A_IWL<7917> A_IWL<7916> A_IWL<7915> A_IWL<7914> A_IWL<7913> A_IWL<7912> A_IWL<7911> A_IWL<7910> A_IWL<7909> A_IWL<7908> A_IWL<7907> A_IWL<7906> A_IWL<7905> A_IWL<7904> A_IWL<7903> A_IWL<7902> A_IWL<7901> A_IWL<7900> A_IWL<7899> A_IWL<7898> A_IWL<7897> A_IWL<7896> A_IWL<7895> A_IWL<7894> A_IWL<7893> A_IWL<7892> A_IWL<7891> A_IWL<7890> A_IWL<7889> A_IWL<7888> A_IWL<7887> A_IWL<7886> A_IWL<7885> A_IWL<7884> A_IWL<7883> A_IWL<7882> A_IWL<7881> A_IWL<7880> A_IWL<7879> A_IWL<7878> A_IWL<7877> A_IWL<7876> A_IWL<7875> A_IWL<7874> A_IWL<7873> A_IWL<7872> A_IWL<7871> A_IWL<7870> A_IWL<7869> A_IWL<7868> A_IWL<7867> A_IWL<7866> A_IWL<7865> A_IWL<7864> A_IWL<7863> A_IWL<7862> A_IWL<7861> A_IWL<7860> A_IWL<7859> A_IWL<7858> A_IWL<7857> A_IWL<7856> A_IWL<7855> A_IWL<7854> A_IWL<7853> A_IWL<7852> A_IWL<7851> A_IWL<7850> A_IWL<7849> A_IWL<7848> A_IWL<7847> A_IWL<7846> A_IWL<7845> A_IWL<7844> A_IWL<7843> A_IWL<7842> A_IWL<7841> A_IWL<7840> A_IWL<7839> A_IWL<7838> A_IWL<7837> A_IWL<7836> A_IWL<7835> A_IWL<7834> A_IWL<7833> A_IWL<7832> A_IWL<7831> A_IWL<7830> A_IWL<7829> A_IWL<7828> A_IWL<7827> A_IWL<7826> A_IWL<7825> A_IWL<7824> A_IWL<7823> A_IWL<7822> A_IWL<7821> A_IWL<7820> A_IWL<7819> A_IWL<7818> A_IWL<7817> A_IWL<7816> A_IWL<7815> A_IWL<7814> A_IWL<7813> A_IWL<7812> A_IWL<7811> A_IWL<7810> A_IWL<7809> A_IWL<7808> A_IWL<7807> A_IWL<7806> A_IWL<7805> A_IWL<7804> A_IWL<7803> A_IWL<7802> A_IWL<7801> A_IWL<7800> A_IWL<7799> A_IWL<7798> A_IWL<7797> A_IWL<7796> A_IWL<7795> A_IWL<7794> A_IWL<7793> A_IWL<7792> A_IWL<7791> A_IWL<7790> A_IWL<7789> A_IWL<7788> A_IWL<7787> A_IWL<7786> A_IWL<7785> A_IWL<7784> A_IWL<7783> A_IWL<7782> A_IWL<7781> A_IWL<7780> A_IWL<7779> A_IWL<7778> A_IWL<7777> A_IWL<7776> A_IWL<7775> A_IWL<7774> A_IWL<7773> A_IWL<7772> A_IWL<7771> A_IWL<7770> A_IWL<7769> A_IWL<7768> A_IWL<7767> A_IWL<7766> A_IWL<7765> A_IWL<7764> A_IWL<7763> A_IWL<7762> A_IWL<7761> A_IWL<7760> A_IWL<7759> A_IWL<7758> A_IWL<7757> A_IWL<7756> A_IWL<7755> A_IWL<7754> A_IWL<7753> A_IWL<7752> A_IWL<7751> A_IWL<7750> A_IWL<7749> A_IWL<7748> A_IWL<7747> A_IWL<7746> A_IWL<7745> A_IWL<7744> A_IWL<7743> A_IWL<7742> A_IWL<7741> A_IWL<7740> A_IWL<7739> A_IWL<7738> A_IWL<7737> A_IWL<7736> A_IWL<7735> A_IWL<7734> A_IWL<7733> A_IWL<7732> A_IWL<7731> A_IWL<7730> A_IWL<7729> A_IWL<7728> A_IWL<7727> A_IWL<7726> A_IWL<7725> A_IWL<7724> A_IWL<7723> A_IWL<7722> A_IWL<7721> A_IWL<7720> A_IWL<7719> A_IWL<7718> A_IWL<7717> A_IWL<7716> A_IWL<7715> A_IWL<7714> A_IWL<7713> A_IWL<7712> A_IWL<7711> A_IWL<7710> A_IWL<7709> A_IWL<7708> A_IWL<7707> A_IWL<7706> A_IWL<7705> A_IWL<7704> A_IWL<7703> A_IWL<7702> A_IWL<7701> A_IWL<7700> A_IWL<7699> A_IWL<7698> A_IWL<7697> A_IWL<7696> A_IWL<7695> A_IWL<7694> A_IWL<7693> A_IWL<7692> A_IWL<7691> A_IWL<7690> A_IWL<7689> A_IWL<7688> A_IWL<7687> A_IWL<7686> A_IWL<7685> A_IWL<7684> A_IWL<7683> A_IWL<7682> A_IWL<7681> A_IWL<7680> B_BLC<61> B_BLC<60> B_BLC_TOP<61> B_BLC_TOP<60> B_BLT<61> B_BLT<60> B_BLT_TOP<61> B_BLT_TOP<60> B_IWL<7679> B_IWL<7678> B_IWL<7677> B_IWL<7676> B_IWL<7675> B_IWL<7674> B_IWL<7673> B_IWL<7672> B_IWL<7671> B_IWL<7670> B_IWL<7669> B_IWL<7668> B_IWL<7667> B_IWL<7666> B_IWL<7665> B_IWL<7664> B_IWL<7663> B_IWL<7662> B_IWL<7661> B_IWL<7660> B_IWL<7659> B_IWL<7658> B_IWL<7657> B_IWL<7656> B_IWL<7655> B_IWL<7654> B_IWL<7653> B_IWL<7652> B_IWL<7651> B_IWL<7650> B_IWL<7649> B_IWL<7648> B_IWL<7647> B_IWL<7646> B_IWL<7645> B_IWL<7644> B_IWL<7643> B_IWL<7642> B_IWL<7641> B_IWL<7640> B_IWL<7639> B_IWL<7638> B_IWL<7637> B_IWL<7636> B_IWL<7635> B_IWL<7634> B_IWL<7633> B_IWL<7632> B_IWL<7631> B_IWL<7630> B_IWL<7629> B_IWL<7628> B_IWL<7627> B_IWL<7626> B_IWL<7625> B_IWL<7624> B_IWL<7623> B_IWL<7622> B_IWL<7621> B_IWL<7620> B_IWL<7619> B_IWL<7618> B_IWL<7617> B_IWL<7616> B_IWL<7615> B_IWL<7614> B_IWL<7613> B_IWL<7612> B_IWL<7611> B_IWL<7610> B_IWL<7609> B_IWL<7608> B_IWL<7607> B_IWL<7606> B_IWL<7605> B_IWL<7604> B_IWL<7603> B_IWL<7602> B_IWL<7601> B_IWL<7600> B_IWL<7599> B_IWL<7598> B_IWL<7597> B_IWL<7596> B_IWL<7595> B_IWL<7594> B_IWL<7593> B_IWL<7592> B_IWL<7591> B_IWL<7590> B_IWL<7589> B_IWL<7588> B_IWL<7587> B_IWL<7586> B_IWL<7585> B_IWL<7584> B_IWL<7583> B_IWL<7582> B_IWL<7581> B_IWL<7580> B_IWL<7579> B_IWL<7578> B_IWL<7577> B_IWL<7576> B_IWL<7575> B_IWL<7574> B_IWL<7573> B_IWL<7572> B_IWL<7571> B_IWL<7570> B_IWL<7569> B_IWL<7568> B_IWL<7567> B_IWL<7566> B_IWL<7565> B_IWL<7564> B_IWL<7563> B_IWL<7562> B_IWL<7561> B_IWL<7560> B_IWL<7559> B_IWL<7558> B_IWL<7557> B_IWL<7556> B_IWL<7555> B_IWL<7554> B_IWL<7553> B_IWL<7552> B_IWL<7551> B_IWL<7550> B_IWL<7549> B_IWL<7548> B_IWL<7547> B_IWL<7546> B_IWL<7545> B_IWL<7544> B_IWL<7543> B_IWL<7542> B_IWL<7541> B_IWL<7540> B_IWL<7539> B_IWL<7538> B_IWL<7537> B_IWL<7536> B_IWL<7535> B_IWL<7534> B_IWL<7533> B_IWL<7532> B_IWL<7531> B_IWL<7530> B_IWL<7529> B_IWL<7528> B_IWL<7527> B_IWL<7526> B_IWL<7525> B_IWL<7524> B_IWL<7523> B_IWL<7522> B_IWL<7521> B_IWL<7520> B_IWL<7519> B_IWL<7518> B_IWL<7517> B_IWL<7516> B_IWL<7515> B_IWL<7514> B_IWL<7513> B_IWL<7512> B_IWL<7511> B_IWL<7510> B_IWL<7509> B_IWL<7508> B_IWL<7507> B_IWL<7506> B_IWL<7505> B_IWL<7504> B_IWL<7503> B_IWL<7502> B_IWL<7501> B_IWL<7500> B_IWL<7499> B_IWL<7498> B_IWL<7497> B_IWL<7496> B_IWL<7495> B_IWL<7494> B_IWL<7493> B_IWL<7492> B_IWL<7491> B_IWL<7490> B_IWL<7489> B_IWL<7488> B_IWL<7487> B_IWL<7486> B_IWL<7485> B_IWL<7484> B_IWL<7483> B_IWL<7482> B_IWL<7481> B_IWL<7480> B_IWL<7479> B_IWL<7478> B_IWL<7477> B_IWL<7476> B_IWL<7475> B_IWL<7474> B_IWL<7473> B_IWL<7472> B_IWL<7471> B_IWL<7470> B_IWL<7469> B_IWL<7468> B_IWL<7467> B_IWL<7466> B_IWL<7465> B_IWL<7464> B_IWL<7463> B_IWL<7462> B_IWL<7461> B_IWL<7460> B_IWL<7459> B_IWL<7458> B_IWL<7457> B_IWL<7456> B_IWL<7455> B_IWL<7454> B_IWL<7453> B_IWL<7452> B_IWL<7451> B_IWL<7450> B_IWL<7449> B_IWL<7448> B_IWL<7447> B_IWL<7446> B_IWL<7445> B_IWL<7444> B_IWL<7443> B_IWL<7442> B_IWL<7441> B_IWL<7440> B_IWL<7439> B_IWL<7438> B_IWL<7437> B_IWL<7436> B_IWL<7435> B_IWL<7434> B_IWL<7433> B_IWL<7432> B_IWL<7431> B_IWL<7430> B_IWL<7429> B_IWL<7428> B_IWL<7427> B_IWL<7426> B_IWL<7425> B_IWL<7424> B_IWL<7935> B_IWL<7934> B_IWL<7933> B_IWL<7932> B_IWL<7931> B_IWL<7930> B_IWL<7929> B_IWL<7928> B_IWL<7927> B_IWL<7926> B_IWL<7925> B_IWL<7924> B_IWL<7923> B_IWL<7922> B_IWL<7921> B_IWL<7920> B_IWL<7919> B_IWL<7918> B_IWL<7917> B_IWL<7916> B_IWL<7915> B_IWL<7914> B_IWL<7913> B_IWL<7912> B_IWL<7911> B_IWL<7910> B_IWL<7909> B_IWL<7908> B_IWL<7907> B_IWL<7906> B_IWL<7905> B_IWL<7904> B_IWL<7903> B_IWL<7902> B_IWL<7901> B_IWL<7900> B_IWL<7899> B_IWL<7898> B_IWL<7897> B_IWL<7896> B_IWL<7895> B_IWL<7894> B_IWL<7893> B_IWL<7892> B_IWL<7891> B_IWL<7890> B_IWL<7889> B_IWL<7888> B_IWL<7887> B_IWL<7886> B_IWL<7885> B_IWL<7884> B_IWL<7883> B_IWL<7882> B_IWL<7881> B_IWL<7880> B_IWL<7879> B_IWL<7878> B_IWL<7877> B_IWL<7876> B_IWL<7875> B_IWL<7874> B_IWL<7873> B_IWL<7872> B_IWL<7871> B_IWL<7870> B_IWL<7869> B_IWL<7868> B_IWL<7867> B_IWL<7866> B_IWL<7865> B_IWL<7864> B_IWL<7863> B_IWL<7862> B_IWL<7861> B_IWL<7860> B_IWL<7859> B_IWL<7858> B_IWL<7857> B_IWL<7856> B_IWL<7855> B_IWL<7854> B_IWL<7853> B_IWL<7852> B_IWL<7851> B_IWL<7850> B_IWL<7849> B_IWL<7848> B_IWL<7847> B_IWL<7846> B_IWL<7845> B_IWL<7844> B_IWL<7843> B_IWL<7842> B_IWL<7841> B_IWL<7840> B_IWL<7839> B_IWL<7838> B_IWL<7837> B_IWL<7836> B_IWL<7835> B_IWL<7834> B_IWL<7833> B_IWL<7832> B_IWL<7831> B_IWL<7830> B_IWL<7829> B_IWL<7828> B_IWL<7827> B_IWL<7826> B_IWL<7825> B_IWL<7824> B_IWL<7823> B_IWL<7822> B_IWL<7821> B_IWL<7820> B_IWL<7819> B_IWL<7818> B_IWL<7817> B_IWL<7816> B_IWL<7815> B_IWL<7814> B_IWL<7813> B_IWL<7812> B_IWL<7811> B_IWL<7810> B_IWL<7809> B_IWL<7808> B_IWL<7807> B_IWL<7806> B_IWL<7805> B_IWL<7804> B_IWL<7803> B_IWL<7802> B_IWL<7801> B_IWL<7800> B_IWL<7799> B_IWL<7798> B_IWL<7797> B_IWL<7796> B_IWL<7795> B_IWL<7794> B_IWL<7793> B_IWL<7792> B_IWL<7791> B_IWL<7790> B_IWL<7789> B_IWL<7788> B_IWL<7787> B_IWL<7786> B_IWL<7785> B_IWL<7784> B_IWL<7783> B_IWL<7782> B_IWL<7781> B_IWL<7780> B_IWL<7779> B_IWL<7778> B_IWL<7777> B_IWL<7776> B_IWL<7775> B_IWL<7774> B_IWL<7773> B_IWL<7772> B_IWL<7771> B_IWL<7770> B_IWL<7769> B_IWL<7768> B_IWL<7767> B_IWL<7766> B_IWL<7765> B_IWL<7764> B_IWL<7763> B_IWL<7762> B_IWL<7761> B_IWL<7760> B_IWL<7759> B_IWL<7758> B_IWL<7757> B_IWL<7756> B_IWL<7755> B_IWL<7754> B_IWL<7753> B_IWL<7752> B_IWL<7751> B_IWL<7750> B_IWL<7749> B_IWL<7748> B_IWL<7747> B_IWL<7746> B_IWL<7745> B_IWL<7744> B_IWL<7743> B_IWL<7742> B_IWL<7741> B_IWL<7740> B_IWL<7739> B_IWL<7738> B_IWL<7737> B_IWL<7736> B_IWL<7735> B_IWL<7734> B_IWL<7733> B_IWL<7732> B_IWL<7731> B_IWL<7730> B_IWL<7729> B_IWL<7728> B_IWL<7727> B_IWL<7726> B_IWL<7725> B_IWL<7724> B_IWL<7723> B_IWL<7722> B_IWL<7721> B_IWL<7720> B_IWL<7719> B_IWL<7718> B_IWL<7717> B_IWL<7716> B_IWL<7715> B_IWL<7714> B_IWL<7713> B_IWL<7712> B_IWL<7711> B_IWL<7710> B_IWL<7709> B_IWL<7708> B_IWL<7707> B_IWL<7706> B_IWL<7705> B_IWL<7704> B_IWL<7703> B_IWL<7702> B_IWL<7701> B_IWL<7700> B_IWL<7699> B_IWL<7698> B_IWL<7697> B_IWL<7696> B_IWL<7695> B_IWL<7694> B_IWL<7693> B_IWL<7692> B_IWL<7691> B_IWL<7690> B_IWL<7689> B_IWL<7688> B_IWL<7687> B_IWL<7686> B_IWL<7685> B_IWL<7684> B_IWL<7683> B_IWL<7682> B_IWL<7681> B_IWL<7680> VDD_CORE VSS / RM_IHPSG13_1024x32_c2_2P_COLUMN_pcell_0 +XCOL<29> A_BLC<59> A_BLC<58> A_BLC_TOP<59> A_BLC_TOP<58> A_BLT<59> A_BLT<58> A_BLT_TOP<59> A_BLT_TOP<58> A_IWL<7423> A_IWL<7422> A_IWL<7421> A_IWL<7420> A_IWL<7419> A_IWL<7418> A_IWL<7417> A_IWL<7416> A_IWL<7415> A_IWL<7414> A_IWL<7413> A_IWL<7412> A_IWL<7411> A_IWL<7410> A_IWL<7409> A_IWL<7408> A_IWL<7407> A_IWL<7406> A_IWL<7405> A_IWL<7404> A_IWL<7403> A_IWL<7402> A_IWL<7401> A_IWL<7400> A_IWL<7399> A_IWL<7398> A_IWL<7397> A_IWL<7396> A_IWL<7395> A_IWL<7394> A_IWL<7393> A_IWL<7392> A_IWL<7391> A_IWL<7390> A_IWL<7389> A_IWL<7388> A_IWL<7387> A_IWL<7386> A_IWL<7385> A_IWL<7384> A_IWL<7383> A_IWL<7382> A_IWL<7381> A_IWL<7380> A_IWL<7379> A_IWL<7378> A_IWL<7377> A_IWL<7376> A_IWL<7375> A_IWL<7374> A_IWL<7373> A_IWL<7372> A_IWL<7371> A_IWL<7370> A_IWL<7369> A_IWL<7368> A_IWL<7367> A_IWL<7366> A_IWL<7365> A_IWL<7364> A_IWL<7363> A_IWL<7362> A_IWL<7361> A_IWL<7360> A_IWL<7359> A_IWL<7358> A_IWL<7357> A_IWL<7356> A_IWL<7355> A_IWL<7354> A_IWL<7353> A_IWL<7352> A_IWL<7351> A_IWL<7350> A_IWL<7349> A_IWL<7348> A_IWL<7347> A_IWL<7346> A_IWL<7345> A_IWL<7344> A_IWL<7343> A_IWL<7342> A_IWL<7341> A_IWL<7340> A_IWL<7339> A_IWL<7338> A_IWL<7337> A_IWL<7336> A_IWL<7335> A_IWL<7334> A_IWL<7333> A_IWL<7332> A_IWL<7331> A_IWL<7330> A_IWL<7329> A_IWL<7328> A_IWL<7327> A_IWL<7326> A_IWL<7325> A_IWL<7324> A_IWL<7323> A_IWL<7322> A_IWL<7321> A_IWL<7320> A_IWL<7319> A_IWL<7318> A_IWL<7317> A_IWL<7316> A_IWL<7315> A_IWL<7314> A_IWL<7313> A_IWL<7312> A_IWL<7311> A_IWL<7310> A_IWL<7309> A_IWL<7308> A_IWL<7307> A_IWL<7306> A_IWL<7305> A_IWL<7304> A_IWL<7303> A_IWL<7302> A_IWL<7301> A_IWL<7300> A_IWL<7299> A_IWL<7298> A_IWL<7297> A_IWL<7296> A_IWL<7295> A_IWL<7294> A_IWL<7293> A_IWL<7292> A_IWL<7291> A_IWL<7290> A_IWL<7289> A_IWL<7288> A_IWL<7287> A_IWL<7286> A_IWL<7285> A_IWL<7284> A_IWL<7283> A_IWL<7282> A_IWL<7281> A_IWL<7280> A_IWL<7279> A_IWL<7278> A_IWL<7277> A_IWL<7276> A_IWL<7275> A_IWL<7274> A_IWL<7273> A_IWL<7272> A_IWL<7271> A_IWL<7270> A_IWL<7269> A_IWL<7268> A_IWL<7267> A_IWL<7266> A_IWL<7265> A_IWL<7264> A_IWL<7263> A_IWL<7262> A_IWL<7261> A_IWL<7260> A_IWL<7259> A_IWL<7258> A_IWL<7257> A_IWL<7256> A_IWL<7255> A_IWL<7254> A_IWL<7253> A_IWL<7252> A_IWL<7251> A_IWL<7250> A_IWL<7249> A_IWL<7248> A_IWL<7247> A_IWL<7246> A_IWL<7245> A_IWL<7244> A_IWL<7243> A_IWL<7242> A_IWL<7241> A_IWL<7240> A_IWL<7239> A_IWL<7238> A_IWL<7237> A_IWL<7236> A_IWL<7235> A_IWL<7234> A_IWL<7233> A_IWL<7232> A_IWL<7231> A_IWL<7230> A_IWL<7229> A_IWL<7228> A_IWL<7227> A_IWL<7226> A_IWL<7225> A_IWL<7224> A_IWL<7223> A_IWL<7222> A_IWL<7221> A_IWL<7220> A_IWL<7219> A_IWL<7218> A_IWL<7217> A_IWL<7216> A_IWL<7215> A_IWL<7214> A_IWL<7213> A_IWL<7212> A_IWL<7211> A_IWL<7210> A_IWL<7209> A_IWL<7208> A_IWL<7207> A_IWL<7206> A_IWL<7205> A_IWL<7204> A_IWL<7203> A_IWL<7202> A_IWL<7201> A_IWL<7200> A_IWL<7199> A_IWL<7198> A_IWL<7197> A_IWL<7196> A_IWL<7195> A_IWL<7194> A_IWL<7193> A_IWL<7192> A_IWL<7191> A_IWL<7190> A_IWL<7189> A_IWL<7188> A_IWL<7187> A_IWL<7186> A_IWL<7185> A_IWL<7184> A_IWL<7183> A_IWL<7182> A_IWL<7181> A_IWL<7180> A_IWL<7179> A_IWL<7178> A_IWL<7177> A_IWL<7176> A_IWL<7175> A_IWL<7174> A_IWL<7173> A_IWL<7172> A_IWL<7171> A_IWL<7170> A_IWL<7169> A_IWL<7168> A_IWL<7679> A_IWL<7678> A_IWL<7677> A_IWL<7676> A_IWL<7675> A_IWL<7674> A_IWL<7673> A_IWL<7672> A_IWL<7671> A_IWL<7670> A_IWL<7669> A_IWL<7668> A_IWL<7667> A_IWL<7666> A_IWL<7665> A_IWL<7664> A_IWL<7663> A_IWL<7662> A_IWL<7661> A_IWL<7660> A_IWL<7659> A_IWL<7658> A_IWL<7657> A_IWL<7656> A_IWL<7655> A_IWL<7654> A_IWL<7653> A_IWL<7652> A_IWL<7651> A_IWL<7650> A_IWL<7649> A_IWL<7648> A_IWL<7647> A_IWL<7646> A_IWL<7645> A_IWL<7644> A_IWL<7643> A_IWL<7642> A_IWL<7641> A_IWL<7640> A_IWL<7639> A_IWL<7638> A_IWL<7637> A_IWL<7636> A_IWL<7635> A_IWL<7634> A_IWL<7633> A_IWL<7632> A_IWL<7631> A_IWL<7630> A_IWL<7629> A_IWL<7628> A_IWL<7627> A_IWL<7626> A_IWL<7625> A_IWL<7624> A_IWL<7623> A_IWL<7622> A_IWL<7621> A_IWL<7620> A_IWL<7619> A_IWL<7618> A_IWL<7617> A_IWL<7616> A_IWL<7615> A_IWL<7614> A_IWL<7613> A_IWL<7612> A_IWL<7611> A_IWL<7610> A_IWL<7609> A_IWL<7608> A_IWL<7607> A_IWL<7606> A_IWL<7605> A_IWL<7604> A_IWL<7603> A_IWL<7602> A_IWL<7601> A_IWL<7600> A_IWL<7599> A_IWL<7598> A_IWL<7597> A_IWL<7596> A_IWL<7595> A_IWL<7594> A_IWL<7593> A_IWL<7592> A_IWL<7591> A_IWL<7590> A_IWL<7589> A_IWL<7588> A_IWL<7587> A_IWL<7586> A_IWL<7585> A_IWL<7584> A_IWL<7583> A_IWL<7582> A_IWL<7581> A_IWL<7580> A_IWL<7579> A_IWL<7578> A_IWL<7577> A_IWL<7576> A_IWL<7575> A_IWL<7574> A_IWL<7573> A_IWL<7572> A_IWL<7571> A_IWL<7570> A_IWL<7569> A_IWL<7568> A_IWL<7567> A_IWL<7566> A_IWL<7565> A_IWL<7564> A_IWL<7563> A_IWL<7562> A_IWL<7561> A_IWL<7560> A_IWL<7559> A_IWL<7558> A_IWL<7557> A_IWL<7556> A_IWL<7555> A_IWL<7554> A_IWL<7553> A_IWL<7552> A_IWL<7551> A_IWL<7550> A_IWL<7549> A_IWL<7548> A_IWL<7547> A_IWL<7546> A_IWL<7545> A_IWL<7544> A_IWL<7543> A_IWL<7542> A_IWL<7541> A_IWL<7540> A_IWL<7539> A_IWL<7538> A_IWL<7537> A_IWL<7536> A_IWL<7535> A_IWL<7534> A_IWL<7533> A_IWL<7532> A_IWL<7531> A_IWL<7530> A_IWL<7529> A_IWL<7528> A_IWL<7527> A_IWL<7526> A_IWL<7525> A_IWL<7524> A_IWL<7523> A_IWL<7522> A_IWL<7521> A_IWL<7520> A_IWL<7519> A_IWL<7518> A_IWL<7517> A_IWL<7516> A_IWL<7515> A_IWL<7514> A_IWL<7513> A_IWL<7512> A_IWL<7511> A_IWL<7510> A_IWL<7509> A_IWL<7508> A_IWL<7507> A_IWL<7506> A_IWL<7505> A_IWL<7504> A_IWL<7503> A_IWL<7502> A_IWL<7501> A_IWL<7500> A_IWL<7499> A_IWL<7498> A_IWL<7497> A_IWL<7496> A_IWL<7495> A_IWL<7494> A_IWL<7493> A_IWL<7492> A_IWL<7491> A_IWL<7490> A_IWL<7489> A_IWL<7488> A_IWL<7487> A_IWL<7486> A_IWL<7485> A_IWL<7484> A_IWL<7483> A_IWL<7482> A_IWL<7481> A_IWL<7480> A_IWL<7479> A_IWL<7478> A_IWL<7477> A_IWL<7476> A_IWL<7475> A_IWL<7474> A_IWL<7473> A_IWL<7472> A_IWL<7471> A_IWL<7470> A_IWL<7469> A_IWL<7468> A_IWL<7467> A_IWL<7466> A_IWL<7465> A_IWL<7464> A_IWL<7463> A_IWL<7462> A_IWL<7461> A_IWL<7460> A_IWL<7459> A_IWL<7458> A_IWL<7457> A_IWL<7456> A_IWL<7455> A_IWL<7454> A_IWL<7453> A_IWL<7452> A_IWL<7451> A_IWL<7450> A_IWL<7449> A_IWL<7448> A_IWL<7447> A_IWL<7446> A_IWL<7445> A_IWL<7444> A_IWL<7443> A_IWL<7442> A_IWL<7441> A_IWL<7440> A_IWL<7439> A_IWL<7438> A_IWL<7437> A_IWL<7436> A_IWL<7435> A_IWL<7434> A_IWL<7433> A_IWL<7432> A_IWL<7431> A_IWL<7430> A_IWL<7429> A_IWL<7428> A_IWL<7427> A_IWL<7426> A_IWL<7425> A_IWL<7424> B_BLC<59> B_BLC<58> B_BLC_TOP<59> B_BLC_TOP<58> B_BLT<59> B_BLT<58> B_BLT_TOP<59> B_BLT_TOP<58> B_IWL<7423> B_IWL<7422> B_IWL<7421> B_IWL<7420> B_IWL<7419> B_IWL<7418> B_IWL<7417> B_IWL<7416> B_IWL<7415> B_IWL<7414> B_IWL<7413> B_IWL<7412> B_IWL<7411> B_IWL<7410> B_IWL<7409> B_IWL<7408> B_IWL<7407> B_IWL<7406> B_IWL<7405> B_IWL<7404> B_IWL<7403> B_IWL<7402> B_IWL<7401> B_IWL<7400> B_IWL<7399> B_IWL<7398> B_IWL<7397> B_IWL<7396> B_IWL<7395> B_IWL<7394> B_IWL<7393> B_IWL<7392> B_IWL<7391> B_IWL<7390> B_IWL<7389> B_IWL<7388> B_IWL<7387> B_IWL<7386> B_IWL<7385> B_IWL<7384> B_IWL<7383> B_IWL<7382> B_IWL<7381> B_IWL<7380> B_IWL<7379> B_IWL<7378> B_IWL<7377> B_IWL<7376> B_IWL<7375> B_IWL<7374> B_IWL<7373> B_IWL<7372> B_IWL<7371> B_IWL<7370> B_IWL<7369> B_IWL<7368> B_IWL<7367> B_IWL<7366> B_IWL<7365> B_IWL<7364> B_IWL<7363> B_IWL<7362> B_IWL<7361> B_IWL<7360> B_IWL<7359> B_IWL<7358> B_IWL<7357> B_IWL<7356> B_IWL<7355> B_IWL<7354> B_IWL<7353> B_IWL<7352> B_IWL<7351> B_IWL<7350> B_IWL<7349> B_IWL<7348> B_IWL<7347> B_IWL<7346> B_IWL<7345> B_IWL<7344> B_IWL<7343> B_IWL<7342> B_IWL<7341> B_IWL<7340> B_IWL<7339> B_IWL<7338> B_IWL<7337> B_IWL<7336> B_IWL<7335> B_IWL<7334> B_IWL<7333> B_IWL<7332> B_IWL<7331> B_IWL<7330> B_IWL<7329> B_IWL<7328> B_IWL<7327> B_IWL<7326> B_IWL<7325> B_IWL<7324> B_IWL<7323> B_IWL<7322> B_IWL<7321> B_IWL<7320> B_IWL<7319> B_IWL<7318> B_IWL<7317> B_IWL<7316> B_IWL<7315> B_IWL<7314> B_IWL<7313> B_IWL<7312> B_IWL<7311> B_IWL<7310> B_IWL<7309> B_IWL<7308> B_IWL<7307> B_IWL<7306> B_IWL<7305> B_IWL<7304> B_IWL<7303> B_IWL<7302> B_IWL<7301> B_IWL<7300> B_IWL<7299> B_IWL<7298> B_IWL<7297> B_IWL<7296> B_IWL<7295> B_IWL<7294> B_IWL<7293> B_IWL<7292> B_IWL<7291> B_IWL<7290> B_IWL<7289> B_IWL<7288> B_IWL<7287> B_IWL<7286> B_IWL<7285> B_IWL<7284> B_IWL<7283> B_IWL<7282> B_IWL<7281> B_IWL<7280> B_IWL<7279> B_IWL<7278> B_IWL<7277> B_IWL<7276> B_IWL<7275> B_IWL<7274> B_IWL<7273> B_IWL<7272> B_IWL<7271> B_IWL<7270> B_IWL<7269> B_IWL<7268> B_IWL<7267> B_IWL<7266> B_IWL<7265> B_IWL<7264> B_IWL<7263> B_IWL<7262> B_IWL<7261> B_IWL<7260> B_IWL<7259> B_IWL<7258> B_IWL<7257> B_IWL<7256> B_IWL<7255> B_IWL<7254> B_IWL<7253> B_IWL<7252> B_IWL<7251> B_IWL<7250> B_IWL<7249> B_IWL<7248> B_IWL<7247> B_IWL<7246> B_IWL<7245> B_IWL<7244> B_IWL<7243> B_IWL<7242> B_IWL<7241> B_IWL<7240> B_IWL<7239> B_IWL<7238> B_IWL<7237> B_IWL<7236> B_IWL<7235> B_IWL<7234> B_IWL<7233> B_IWL<7232> B_IWL<7231> B_IWL<7230> B_IWL<7229> B_IWL<7228> B_IWL<7227> B_IWL<7226> B_IWL<7225> B_IWL<7224> B_IWL<7223> B_IWL<7222> B_IWL<7221> B_IWL<7220> B_IWL<7219> B_IWL<7218> B_IWL<7217> B_IWL<7216> B_IWL<7215> B_IWL<7214> B_IWL<7213> B_IWL<7212> B_IWL<7211> B_IWL<7210> B_IWL<7209> B_IWL<7208> B_IWL<7207> B_IWL<7206> B_IWL<7205> B_IWL<7204> B_IWL<7203> B_IWL<7202> B_IWL<7201> B_IWL<7200> B_IWL<7199> B_IWL<7198> B_IWL<7197> B_IWL<7196> B_IWL<7195> B_IWL<7194> B_IWL<7193> B_IWL<7192> B_IWL<7191> B_IWL<7190> B_IWL<7189> B_IWL<7188> B_IWL<7187> B_IWL<7186> B_IWL<7185> B_IWL<7184> B_IWL<7183> B_IWL<7182> B_IWL<7181> B_IWL<7180> B_IWL<7179> B_IWL<7178> B_IWL<7177> B_IWL<7176> B_IWL<7175> B_IWL<7174> B_IWL<7173> B_IWL<7172> B_IWL<7171> B_IWL<7170> B_IWL<7169> B_IWL<7168> B_IWL<7679> B_IWL<7678> B_IWL<7677> B_IWL<7676> B_IWL<7675> B_IWL<7674> B_IWL<7673> B_IWL<7672> B_IWL<7671> B_IWL<7670> B_IWL<7669> B_IWL<7668> B_IWL<7667> B_IWL<7666> B_IWL<7665> B_IWL<7664> B_IWL<7663> B_IWL<7662> B_IWL<7661> B_IWL<7660> B_IWL<7659> B_IWL<7658> B_IWL<7657> B_IWL<7656> B_IWL<7655> B_IWL<7654> B_IWL<7653> B_IWL<7652> B_IWL<7651> B_IWL<7650> B_IWL<7649> B_IWL<7648> B_IWL<7647> B_IWL<7646> B_IWL<7645> B_IWL<7644> B_IWL<7643> B_IWL<7642> B_IWL<7641> B_IWL<7640> B_IWL<7639> B_IWL<7638> B_IWL<7637> B_IWL<7636> B_IWL<7635> B_IWL<7634> B_IWL<7633> B_IWL<7632> B_IWL<7631> B_IWL<7630> B_IWL<7629> B_IWL<7628> B_IWL<7627> B_IWL<7626> B_IWL<7625> B_IWL<7624> B_IWL<7623> B_IWL<7622> B_IWL<7621> B_IWL<7620> B_IWL<7619> B_IWL<7618> B_IWL<7617> B_IWL<7616> B_IWL<7615> B_IWL<7614> B_IWL<7613> B_IWL<7612> B_IWL<7611> B_IWL<7610> B_IWL<7609> B_IWL<7608> B_IWL<7607> B_IWL<7606> B_IWL<7605> B_IWL<7604> B_IWL<7603> B_IWL<7602> B_IWL<7601> B_IWL<7600> B_IWL<7599> B_IWL<7598> B_IWL<7597> B_IWL<7596> B_IWL<7595> B_IWL<7594> B_IWL<7593> B_IWL<7592> B_IWL<7591> B_IWL<7590> B_IWL<7589> B_IWL<7588> B_IWL<7587> B_IWL<7586> B_IWL<7585> B_IWL<7584> B_IWL<7583> B_IWL<7582> B_IWL<7581> B_IWL<7580> B_IWL<7579> B_IWL<7578> B_IWL<7577> B_IWL<7576> B_IWL<7575> B_IWL<7574> B_IWL<7573> B_IWL<7572> B_IWL<7571> B_IWL<7570> B_IWL<7569> B_IWL<7568> B_IWL<7567> B_IWL<7566> B_IWL<7565> B_IWL<7564> B_IWL<7563> B_IWL<7562> B_IWL<7561> B_IWL<7560> B_IWL<7559> B_IWL<7558> B_IWL<7557> B_IWL<7556> B_IWL<7555> B_IWL<7554> B_IWL<7553> B_IWL<7552> B_IWL<7551> B_IWL<7550> B_IWL<7549> B_IWL<7548> B_IWL<7547> B_IWL<7546> B_IWL<7545> B_IWL<7544> B_IWL<7543> B_IWL<7542> B_IWL<7541> B_IWL<7540> B_IWL<7539> B_IWL<7538> B_IWL<7537> B_IWL<7536> B_IWL<7535> B_IWL<7534> B_IWL<7533> B_IWL<7532> B_IWL<7531> B_IWL<7530> B_IWL<7529> B_IWL<7528> B_IWL<7527> B_IWL<7526> B_IWL<7525> B_IWL<7524> B_IWL<7523> B_IWL<7522> B_IWL<7521> B_IWL<7520> B_IWL<7519> B_IWL<7518> B_IWL<7517> B_IWL<7516> B_IWL<7515> B_IWL<7514> B_IWL<7513> B_IWL<7512> B_IWL<7511> B_IWL<7510> B_IWL<7509> B_IWL<7508> B_IWL<7507> B_IWL<7506> B_IWL<7505> B_IWL<7504> B_IWL<7503> B_IWL<7502> B_IWL<7501> B_IWL<7500> B_IWL<7499> B_IWL<7498> B_IWL<7497> B_IWL<7496> B_IWL<7495> B_IWL<7494> B_IWL<7493> B_IWL<7492> B_IWL<7491> B_IWL<7490> B_IWL<7489> B_IWL<7488> B_IWL<7487> B_IWL<7486> B_IWL<7485> B_IWL<7484> B_IWL<7483> B_IWL<7482> B_IWL<7481> B_IWL<7480> B_IWL<7479> B_IWL<7478> B_IWL<7477> B_IWL<7476> B_IWL<7475> B_IWL<7474> B_IWL<7473> B_IWL<7472> B_IWL<7471> B_IWL<7470> B_IWL<7469> B_IWL<7468> B_IWL<7467> B_IWL<7466> B_IWL<7465> B_IWL<7464> B_IWL<7463> B_IWL<7462> B_IWL<7461> B_IWL<7460> B_IWL<7459> B_IWL<7458> B_IWL<7457> B_IWL<7456> B_IWL<7455> B_IWL<7454> B_IWL<7453> B_IWL<7452> B_IWL<7451> B_IWL<7450> B_IWL<7449> B_IWL<7448> B_IWL<7447> B_IWL<7446> B_IWL<7445> B_IWL<7444> B_IWL<7443> B_IWL<7442> B_IWL<7441> B_IWL<7440> B_IWL<7439> B_IWL<7438> B_IWL<7437> B_IWL<7436> B_IWL<7435> B_IWL<7434> B_IWL<7433> B_IWL<7432> B_IWL<7431> B_IWL<7430> B_IWL<7429> B_IWL<7428> B_IWL<7427> B_IWL<7426> B_IWL<7425> B_IWL<7424> VDD_CORE VSS / RM_IHPSG13_1024x32_c2_2P_COLUMN_pcell_0 +XCOL<28> A_BLC<57> A_BLC<56> A_BLC_TOP<57> A_BLC_TOP<56> A_BLT<57> A_BLT<56> A_BLT_TOP<57> A_BLT_TOP<56> A_IWL<7167> A_IWL<7166> A_IWL<7165> A_IWL<7164> A_IWL<7163> A_IWL<7162> A_IWL<7161> A_IWL<7160> A_IWL<7159> A_IWL<7158> A_IWL<7157> A_IWL<7156> A_IWL<7155> A_IWL<7154> A_IWL<7153> A_IWL<7152> A_IWL<7151> A_IWL<7150> A_IWL<7149> A_IWL<7148> A_IWL<7147> A_IWL<7146> A_IWL<7145> A_IWL<7144> A_IWL<7143> A_IWL<7142> A_IWL<7141> A_IWL<7140> A_IWL<7139> A_IWL<7138> A_IWL<7137> A_IWL<7136> A_IWL<7135> A_IWL<7134> A_IWL<7133> A_IWL<7132> A_IWL<7131> A_IWL<7130> A_IWL<7129> A_IWL<7128> A_IWL<7127> A_IWL<7126> A_IWL<7125> A_IWL<7124> A_IWL<7123> A_IWL<7122> A_IWL<7121> A_IWL<7120> A_IWL<7119> A_IWL<7118> A_IWL<7117> A_IWL<7116> A_IWL<7115> A_IWL<7114> A_IWL<7113> A_IWL<7112> A_IWL<7111> A_IWL<7110> A_IWL<7109> A_IWL<7108> A_IWL<7107> A_IWL<7106> A_IWL<7105> A_IWL<7104> A_IWL<7103> A_IWL<7102> A_IWL<7101> A_IWL<7100> A_IWL<7099> A_IWL<7098> A_IWL<7097> A_IWL<7096> A_IWL<7095> A_IWL<7094> A_IWL<7093> A_IWL<7092> A_IWL<7091> A_IWL<7090> A_IWL<7089> A_IWL<7088> A_IWL<7087> A_IWL<7086> A_IWL<7085> A_IWL<7084> A_IWL<7083> A_IWL<7082> A_IWL<7081> A_IWL<7080> A_IWL<7079> A_IWL<7078> A_IWL<7077> A_IWL<7076> A_IWL<7075> A_IWL<7074> A_IWL<7073> A_IWL<7072> A_IWL<7071> A_IWL<7070> A_IWL<7069> A_IWL<7068> A_IWL<7067> A_IWL<7066> A_IWL<7065> A_IWL<7064> A_IWL<7063> A_IWL<7062> A_IWL<7061> A_IWL<7060> A_IWL<7059> A_IWL<7058> A_IWL<7057> A_IWL<7056> A_IWL<7055> A_IWL<7054> A_IWL<7053> A_IWL<7052> A_IWL<7051> A_IWL<7050> A_IWL<7049> A_IWL<7048> A_IWL<7047> A_IWL<7046> A_IWL<7045> A_IWL<7044> A_IWL<7043> A_IWL<7042> A_IWL<7041> A_IWL<7040> A_IWL<7039> A_IWL<7038> A_IWL<7037> A_IWL<7036> A_IWL<7035> A_IWL<7034> A_IWL<7033> A_IWL<7032> A_IWL<7031> A_IWL<7030> A_IWL<7029> A_IWL<7028> A_IWL<7027> A_IWL<7026> A_IWL<7025> A_IWL<7024> A_IWL<7023> A_IWL<7022> A_IWL<7021> A_IWL<7020> A_IWL<7019> A_IWL<7018> A_IWL<7017> A_IWL<7016> A_IWL<7015> A_IWL<7014> A_IWL<7013> A_IWL<7012> A_IWL<7011> A_IWL<7010> A_IWL<7009> A_IWL<7008> A_IWL<7007> A_IWL<7006> A_IWL<7005> A_IWL<7004> A_IWL<7003> A_IWL<7002> A_IWL<7001> A_IWL<7000> A_IWL<6999> A_IWL<6998> A_IWL<6997> A_IWL<6996> A_IWL<6995> A_IWL<6994> A_IWL<6993> A_IWL<6992> A_IWL<6991> A_IWL<6990> A_IWL<6989> A_IWL<6988> A_IWL<6987> A_IWL<6986> A_IWL<6985> A_IWL<6984> A_IWL<6983> A_IWL<6982> A_IWL<6981> A_IWL<6980> A_IWL<6979> A_IWL<6978> A_IWL<6977> A_IWL<6976> A_IWL<6975> A_IWL<6974> A_IWL<6973> A_IWL<6972> A_IWL<6971> A_IWL<6970> A_IWL<6969> A_IWL<6968> A_IWL<6967> A_IWL<6966> A_IWL<6965> A_IWL<6964> A_IWL<6963> A_IWL<6962> A_IWL<6961> A_IWL<6960> A_IWL<6959> A_IWL<6958> A_IWL<6957> A_IWL<6956> A_IWL<6955> A_IWL<6954> A_IWL<6953> A_IWL<6952> A_IWL<6951> A_IWL<6950> A_IWL<6949> A_IWL<6948> A_IWL<6947> A_IWL<6946> A_IWL<6945> A_IWL<6944> A_IWL<6943> A_IWL<6942> A_IWL<6941> A_IWL<6940> A_IWL<6939> A_IWL<6938> A_IWL<6937> A_IWL<6936> A_IWL<6935> A_IWL<6934> A_IWL<6933> A_IWL<6932> A_IWL<6931> A_IWL<6930> A_IWL<6929> A_IWL<6928> A_IWL<6927> A_IWL<6926> A_IWL<6925> A_IWL<6924> A_IWL<6923> A_IWL<6922> A_IWL<6921> A_IWL<6920> A_IWL<6919> A_IWL<6918> A_IWL<6917> A_IWL<6916> A_IWL<6915> A_IWL<6914> A_IWL<6913> A_IWL<6912> A_IWL<7423> A_IWL<7422> A_IWL<7421> A_IWL<7420> A_IWL<7419> A_IWL<7418> A_IWL<7417> A_IWL<7416> A_IWL<7415> A_IWL<7414> A_IWL<7413> A_IWL<7412> A_IWL<7411> A_IWL<7410> A_IWL<7409> A_IWL<7408> A_IWL<7407> A_IWL<7406> A_IWL<7405> A_IWL<7404> A_IWL<7403> A_IWL<7402> A_IWL<7401> A_IWL<7400> A_IWL<7399> A_IWL<7398> A_IWL<7397> A_IWL<7396> A_IWL<7395> A_IWL<7394> A_IWL<7393> A_IWL<7392> A_IWL<7391> A_IWL<7390> A_IWL<7389> A_IWL<7388> A_IWL<7387> A_IWL<7386> A_IWL<7385> A_IWL<7384> A_IWL<7383> A_IWL<7382> A_IWL<7381> A_IWL<7380> A_IWL<7379> A_IWL<7378> A_IWL<7377> A_IWL<7376> A_IWL<7375> A_IWL<7374> A_IWL<7373> A_IWL<7372> A_IWL<7371> A_IWL<7370> A_IWL<7369> A_IWL<7368> A_IWL<7367> A_IWL<7366> A_IWL<7365> A_IWL<7364> A_IWL<7363> A_IWL<7362> A_IWL<7361> A_IWL<7360> A_IWL<7359> A_IWL<7358> A_IWL<7357> A_IWL<7356> A_IWL<7355> A_IWL<7354> A_IWL<7353> A_IWL<7352> A_IWL<7351> A_IWL<7350> A_IWL<7349> A_IWL<7348> A_IWL<7347> A_IWL<7346> A_IWL<7345> A_IWL<7344> A_IWL<7343> A_IWL<7342> A_IWL<7341> A_IWL<7340> A_IWL<7339> A_IWL<7338> A_IWL<7337> A_IWL<7336> A_IWL<7335> A_IWL<7334> A_IWL<7333> A_IWL<7332> A_IWL<7331> A_IWL<7330> A_IWL<7329> A_IWL<7328> A_IWL<7327> A_IWL<7326> A_IWL<7325> A_IWL<7324> A_IWL<7323> A_IWL<7322> A_IWL<7321> A_IWL<7320> A_IWL<7319> A_IWL<7318> A_IWL<7317> A_IWL<7316> A_IWL<7315> A_IWL<7314> A_IWL<7313> A_IWL<7312> A_IWL<7311> A_IWL<7310> A_IWL<7309> A_IWL<7308> A_IWL<7307> A_IWL<7306> A_IWL<7305> A_IWL<7304> A_IWL<7303> A_IWL<7302> A_IWL<7301> A_IWL<7300> A_IWL<7299> A_IWL<7298> A_IWL<7297> A_IWL<7296> A_IWL<7295> A_IWL<7294> A_IWL<7293> A_IWL<7292> A_IWL<7291> A_IWL<7290> A_IWL<7289> A_IWL<7288> A_IWL<7287> A_IWL<7286> A_IWL<7285> A_IWL<7284> A_IWL<7283> A_IWL<7282> A_IWL<7281> A_IWL<7280> A_IWL<7279> A_IWL<7278> A_IWL<7277> A_IWL<7276> A_IWL<7275> A_IWL<7274> A_IWL<7273> A_IWL<7272> A_IWL<7271> A_IWL<7270> A_IWL<7269> A_IWL<7268> A_IWL<7267> A_IWL<7266> A_IWL<7265> A_IWL<7264> A_IWL<7263> A_IWL<7262> A_IWL<7261> A_IWL<7260> A_IWL<7259> A_IWL<7258> A_IWL<7257> A_IWL<7256> A_IWL<7255> A_IWL<7254> A_IWL<7253> A_IWL<7252> A_IWL<7251> A_IWL<7250> A_IWL<7249> A_IWL<7248> A_IWL<7247> A_IWL<7246> A_IWL<7245> A_IWL<7244> A_IWL<7243> A_IWL<7242> A_IWL<7241> A_IWL<7240> A_IWL<7239> A_IWL<7238> A_IWL<7237> A_IWL<7236> A_IWL<7235> A_IWL<7234> A_IWL<7233> A_IWL<7232> A_IWL<7231> A_IWL<7230> A_IWL<7229> A_IWL<7228> A_IWL<7227> A_IWL<7226> A_IWL<7225> A_IWL<7224> A_IWL<7223> A_IWL<7222> A_IWL<7221> A_IWL<7220> A_IWL<7219> A_IWL<7218> A_IWL<7217> A_IWL<7216> A_IWL<7215> A_IWL<7214> A_IWL<7213> A_IWL<7212> A_IWL<7211> A_IWL<7210> A_IWL<7209> A_IWL<7208> A_IWL<7207> A_IWL<7206> A_IWL<7205> A_IWL<7204> A_IWL<7203> A_IWL<7202> A_IWL<7201> A_IWL<7200> A_IWL<7199> A_IWL<7198> A_IWL<7197> A_IWL<7196> A_IWL<7195> A_IWL<7194> A_IWL<7193> A_IWL<7192> A_IWL<7191> A_IWL<7190> A_IWL<7189> A_IWL<7188> A_IWL<7187> A_IWL<7186> A_IWL<7185> A_IWL<7184> A_IWL<7183> A_IWL<7182> A_IWL<7181> A_IWL<7180> A_IWL<7179> A_IWL<7178> A_IWL<7177> A_IWL<7176> A_IWL<7175> A_IWL<7174> A_IWL<7173> A_IWL<7172> A_IWL<7171> A_IWL<7170> A_IWL<7169> A_IWL<7168> B_BLC<57> B_BLC<56> B_BLC_TOP<57> B_BLC_TOP<56> B_BLT<57> B_BLT<56> B_BLT_TOP<57> B_BLT_TOP<56> B_IWL<7167> B_IWL<7166> B_IWL<7165> B_IWL<7164> B_IWL<7163> B_IWL<7162> B_IWL<7161> B_IWL<7160> B_IWL<7159> B_IWL<7158> B_IWL<7157> B_IWL<7156> B_IWL<7155> B_IWL<7154> B_IWL<7153> B_IWL<7152> B_IWL<7151> B_IWL<7150> B_IWL<7149> B_IWL<7148> B_IWL<7147> B_IWL<7146> B_IWL<7145> B_IWL<7144> B_IWL<7143> B_IWL<7142> B_IWL<7141> B_IWL<7140> B_IWL<7139> B_IWL<7138> B_IWL<7137> B_IWL<7136> B_IWL<7135> B_IWL<7134> B_IWL<7133> B_IWL<7132> B_IWL<7131> B_IWL<7130> B_IWL<7129> B_IWL<7128> B_IWL<7127> B_IWL<7126> B_IWL<7125> B_IWL<7124> B_IWL<7123> B_IWL<7122> B_IWL<7121> B_IWL<7120> B_IWL<7119> B_IWL<7118> B_IWL<7117> B_IWL<7116> B_IWL<7115> B_IWL<7114> B_IWL<7113> B_IWL<7112> B_IWL<7111> B_IWL<7110> B_IWL<7109> B_IWL<7108> B_IWL<7107> B_IWL<7106> B_IWL<7105> B_IWL<7104> B_IWL<7103> B_IWL<7102> B_IWL<7101> B_IWL<7100> B_IWL<7099> B_IWL<7098> B_IWL<7097> B_IWL<7096> B_IWL<7095> B_IWL<7094> B_IWL<7093> B_IWL<7092> B_IWL<7091> B_IWL<7090> B_IWL<7089> B_IWL<7088> B_IWL<7087> B_IWL<7086> B_IWL<7085> B_IWL<7084> B_IWL<7083> B_IWL<7082> B_IWL<7081> B_IWL<7080> B_IWL<7079> B_IWL<7078> B_IWL<7077> B_IWL<7076> B_IWL<7075> B_IWL<7074> B_IWL<7073> B_IWL<7072> B_IWL<7071> B_IWL<7070> B_IWL<7069> B_IWL<7068> B_IWL<7067> B_IWL<7066> B_IWL<7065> B_IWL<7064> B_IWL<7063> B_IWL<7062> B_IWL<7061> B_IWL<7060> B_IWL<7059> B_IWL<7058> B_IWL<7057> B_IWL<7056> B_IWL<7055> B_IWL<7054> B_IWL<7053> B_IWL<7052> B_IWL<7051> B_IWL<7050> B_IWL<7049> B_IWL<7048> B_IWL<7047> B_IWL<7046> B_IWL<7045> B_IWL<7044> B_IWL<7043> B_IWL<7042> B_IWL<7041> B_IWL<7040> B_IWL<7039> B_IWL<7038> B_IWL<7037> B_IWL<7036> B_IWL<7035> B_IWL<7034> B_IWL<7033> B_IWL<7032> B_IWL<7031> B_IWL<7030> B_IWL<7029> B_IWL<7028> B_IWL<7027> B_IWL<7026> B_IWL<7025> B_IWL<7024> B_IWL<7023> B_IWL<7022> B_IWL<7021> B_IWL<7020> B_IWL<7019> B_IWL<7018> B_IWL<7017> B_IWL<7016> B_IWL<7015> B_IWL<7014> B_IWL<7013> B_IWL<7012> B_IWL<7011> B_IWL<7010> B_IWL<7009> B_IWL<7008> B_IWL<7007> B_IWL<7006> B_IWL<7005> B_IWL<7004> B_IWL<7003> B_IWL<7002> B_IWL<7001> B_IWL<7000> B_IWL<6999> B_IWL<6998> B_IWL<6997> B_IWL<6996> B_IWL<6995> B_IWL<6994> B_IWL<6993> B_IWL<6992> B_IWL<6991> B_IWL<6990> B_IWL<6989> B_IWL<6988> B_IWL<6987> B_IWL<6986> B_IWL<6985> B_IWL<6984> B_IWL<6983> B_IWL<6982> B_IWL<6981> B_IWL<6980> B_IWL<6979> B_IWL<6978> B_IWL<6977> B_IWL<6976> B_IWL<6975> B_IWL<6974> B_IWL<6973> B_IWL<6972> B_IWL<6971> B_IWL<6970> B_IWL<6969> B_IWL<6968> B_IWL<6967> B_IWL<6966> B_IWL<6965> B_IWL<6964> B_IWL<6963> B_IWL<6962> B_IWL<6961> B_IWL<6960> B_IWL<6959> B_IWL<6958> B_IWL<6957> B_IWL<6956> B_IWL<6955> B_IWL<6954> B_IWL<6953> B_IWL<6952> B_IWL<6951> B_IWL<6950> B_IWL<6949> B_IWL<6948> B_IWL<6947> B_IWL<6946> B_IWL<6945> B_IWL<6944> B_IWL<6943> B_IWL<6942> B_IWL<6941> B_IWL<6940> B_IWL<6939> B_IWL<6938> B_IWL<6937> B_IWL<6936> B_IWL<6935> B_IWL<6934> B_IWL<6933> B_IWL<6932> B_IWL<6931> B_IWL<6930> B_IWL<6929> B_IWL<6928> B_IWL<6927> B_IWL<6926> B_IWL<6925> B_IWL<6924> B_IWL<6923> B_IWL<6922> B_IWL<6921> B_IWL<6920> B_IWL<6919> B_IWL<6918> B_IWL<6917> B_IWL<6916> B_IWL<6915> B_IWL<6914> B_IWL<6913> B_IWL<6912> B_IWL<7423> B_IWL<7422> B_IWL<7421> B_IWL<7420> B_IWL<7419> B_IWL<7418> B_IWL<7417> B_IWL<7416> B_IWL<7415> B_IWL<7414> B_IWL<7413> B_IWL<7412> B_IWL<7411> B_IWL<7410> B_IWL<7409> B_IWL<7408> B_IWL<7407> B_IWL<7406> B_IWL<7405> B_IWL<7404> B_IWL<7403> B_IWL<7402> B_IWL<7401> B_IWL<7400> B_IWL<7399> B_IWL<7398> B_IWL<7397> B_IWL<7396> B_IWL<7395> B_IWL<7394> B_IWL<7393> B_IWL<7392> B_IWL<7391> B_IWL<7390> B_IWL<7389> B_IWL<7388> B_IWL<7387> B_IWL<7386> B_IWL<7385> B_IWL<7384> B_IWL<7383> B_IWL<7382> B_IWL<7381> B_IWL<7380> B_IWL<7379> B_IWL<7378> B_IWL<7377> B_IWL<7376> B_IWL<7375> B_IWL<7374> B_IWL<7373> B_IWL<7372> B_IWL<7371> B_IWL<7370> B_IWL<7369> B_IWL<7368> B_IWL<7367> B_IWL<7366> B_IWL<7365> B_IWL<7364> B_IWL<7363> B_IWL<7362> B_IWL<7361> B_IWL<7360> B_IWL<7359> B_IWL<7358> B_IWL<7357> B_IWL<7356> B_IWL<7355> B_IWL<7354> B_IWL<7353> B_IWL<7352> B_IWL<7351> B_IWL<7350> B_IWL<7349> B_IWL<7348> B_IWL<7347> B_IWL<7346> B_IWL<7345> B_IWL<7344> B_IWL<7343> B_IWL<7342> B_IWL<7341> B_IWL<7340> B_IWL<7339> B_IWL<7338> B_IWL<7337> B_IWL<7336> B_IWL<7335> B_IWL<7334> B_IWL<7333> B_IWL<7332> B_IWL<7331> B_IWL<7330> B_IWL<7329> B_IWL<7328> B_IWL<7327> B_IWL<7326> B_IWL<7325> B_IWL<7324> B_IWL<7323> B_IWL<7322> B_IWL<7321> B_IWL<7320> B_IWL<7319> B_IWL<7318> B_IWL<7317> B_IWL<7316> B_IWL<7315> B_IWL<7314> B_IWL<7313> B_IWL<7312> B_IWL<7311> B_IWL<7310> B_IWL<7309> B_IWL<7308> B_IWL<7307> B_IWL<7306> B_IWL<7305> B_IWL<7304> B_IWL<7303> B_IWL<7302> B_IWL<7301> B_IWL<7300> B_IWL<7299> B_IWL<7298> B_IWL<7297> B_IWL<7296> B_IWL<7295> B_IWL<7294> B_IWL<7293> B_IWL<7292> B_IWL<7291> B_IWL<7290> B_IWL<7289> B_IWL<7288> B_IWL<7287> B_IWL<7286> B_IWL<7285> B_IWL<7284> B_IWL<7283> B_IWL<7282> B_IWL<7281> B_IWL<7280> B_IWL<7279> B_IWL<7278> B_IWL<7277> B_IWL<7276> B_IWL<7275> B_IWL<7274> B_IWL<7273> B_IWL<7272> B_IWL<7271> B_IWL<7270> B_IWL<7269> B_IWL<7268> B_IWL<7267> B_IWL<7266> B_IWL<7265> B_IWL<7264> B_IWL<7263> B_IWL<7262> B_IWL<7261> B_IWL<7260> B_IWL<7259> B_IWL<7258> B_IWL<7257> B_IWL<7256> B_IWL<7255> B_IWL<7254> B_IWL<7253> B_IWL<7252> B_IWL<7251> B_IWL<7250> B_IWL<7249> B_IWL<7248> B_IWL<7247> B_IWL<7246> B_IWL<7245> B_IWL<7244> B_IWL<7243> B_IWL<7242> B_IWL<7241> B_IWL<7240> B_IWL<7239> B_IWL<7238> B_IWL<7237> B_IWL<7236> B_IWL<7235> B_IWL<7234> B_IWL<7233> B_IWL<7232> B_IWL<7231> B_IWL<7230> B_IWL<7229> B_IWL<7228> B_IWL<7227> B_IWL<7226> B_IWL<7225> B_IWL<7224> B_IWL<7223> B_IWL<7222> B_IWL<7221> B_IWL<7220> B_IWL<7219> B_IWL<7218> B_IWL<7217> B_IWL<7216> B_IWL<7215> B_IWL<7214> B_IWL<7213> B_IWL<7212> B_IWL<7211> B_IWL<7210> B_IWL<7209> B_IWL<7208> B_IWL<7207> B_IWL<7206> B_IWL<7205> B_IWL<7204> B_IWL<7203> B_IWL<7202> B_IWL<7201> B_IWL<7200> B_IWL<7199> B_IWL<7198> B_IWL<7197> B_IWL<7196> B_IWL<7195> B_IWL<7194> B_IWL<7193> B_IWL<7192> B_IWL<7191> B_IWL<7190> B_IWL<7189> B_IWL<7188> B_IWL<7187> B_IWL<7186> B_IWL<7185> B_IWL<7184> B_IWL<7183> B_IWL<7182> B_IWL<7181> B_IWL<7180> B_IWL<7179> B_IWL<7178> B_IWL<7177> B_IWL<7176> B_IWL<7175> B_IWL<7174> B_IWL<7173> B_IWL<7172> B_IWL<7171> B_IWL<7170> B_IWL<7169> B_IWL<7168> VDD_CORE VSS / RM_IHPSG13_1024x32_c2_2P_COLUMN_pcell_0 +XCOL<27> A_BLC<55> A_BLC<54> A_BLC_TOP<55> A_BLC_TOP<54> A_BLT<55> A_BLT<54> A_BLT_TOP<55> A_BLT_TOP<54> A_IWL<6911> A_IWL<6910> A_IWL<6909> A_IWL<6908> A_IWL<6907> A_IWL<6906> A_IWL<6905> A_IWL<6904> A_IWL<6903> A_IWL<6902> A_IWL<6901> A_IWL<6900> A_IWL<6899> A_IWL<6898> A_IWL<6897> A_IWL<6896> A_IWL<6895> A_IWL<6894> A_IWL<6893> A_IWL<6892> A_IWL<6891> A_IWL<6890> A_IWL<6889> A_IWL<6888> A_IWL<6887> A_IWL<6886> A_IWL<6885> A_IWL<6884> A_IWL<6883> A_IWL<6882> A_IWL<6881> A_IWL<6880> A_IWL<6879> A_IWL<6878> A_IWL<6877> A_IWL<6876> A_IWL<6875> A_IWL<6874> A_IWL<6873> A_IWL<6872> A_IWL<6871> A_IWL<6870> A_IWL<6869> A_IWL<6868> A_IWL<6867> A_IWL<6866> A_IWL<6865> A_IWL<6864> A_IWL<6863> A_IWL<6862> A_IWL<6861> A_IWL<6860> A_IWL<6859> A_IWL<6858> A_IWL<6857> A_IWL<6856> A_IWL<6855> A_IWL<6854> A_IWL<6853> A_IWL<6852> A_IWL<6851> A_IWL<6850> A_IWL<6849> A_IWL<6848> A_IWL<6847> A_IWL<6846> A_IWL<6845> A_IWL<6844> A_IWL<6843> A_IWL<6842> A_IWL<6841> A_IWL<6840> A_IWL<6839> A_IWL<6838> A_IWL<6837> A_IWL<6836> A_IWL<6835> A_IWL<6834> A_IWL<6833> A_IWL<6832> A_IWL<6831> A_IWL<6830> A_IWL<6829> A_IWL<6828> A_IWL<6827> A_IWL<6826> A_IWL<6825> A_IWL<6824> A_IWL<6823> A_IWL<6822> A_IWL<6821> A_IWL<6820> A_IWL<6819> A_IWL<6818> A_IWL<6817> A_IWL<6816> A_IWL<6815> A_IWL<6814> A_IWL<6813> A_IWL<6812> A_IWL<6811> A_IWL<6810> A_IWL<6809> A_IWL<6808> A_IWL<6807> A_IWL<6806> A_IWL<6805> A_IWL<6804> A_IWL<6803> A_IWL<6802> A_IWL<6801> A_IWL<6800> A_IWL<6799> A_IWL<6798> A_IWL<6797> A_IWL<6796> A_IWL<6795> A_IWL<6794> A_IWL<6793> A_IWL<6792> A_IWL<6791> A_IWL<6790> A_IWL<6789> A_IWL<6788> A_IWL<6787> A_IWL<6786> A_IWL<6785> A_IWL<6784> A_IWL<6783> A_IWL<6782> A_IWL<6781> A_IWL<6780> A_IWL<6779> A_IWL<6778> A_IWL<6777> A_IWL<6776> A_IWL<6775> A_IWL<6774> A_IWL<6773> A_IWL<6772> A_IWL<6771> A_IWL<6770> A_IWL<6769> A_IWL<6768> A_IWL<6767> A_IWL<6766> A_IWL<6765> A_IWL<6764> A_IWL<6763> A_IWL<6762> A_IWL<6761> A_IWL<6760> A_IWL<6759> A_IWL<6758> A_IWL<6757> A_IWL<6756> A_IWL<6755> A_IWL<6754> A_IWL<6753> A_IWL<6752> A_IWL<6751> A_IWL<6750> A_IWL<6749> A_IWL<6748> A_IWL<6747> A_IWL<6746> A_IWL<6745> A_IWL<6744> A_IWL<6743> A_IWL<6742> A_IWL<6741> A_IWL<6740> A_IWL<6739> A_IWL<6738> A_IWL<6737> A_IWL<6736> A_IWL<6735> A_IWL<6734> A_IWL<6733> A_IWL<6732> A_IWL<6731> A_IWL<6730> A_IWL<6729> A_IWL<6728> A_IWL<6727> A_IWL<6726> A_IWL<6725> A_IWL<6724> A_IWL<6723> A_IWL<6722> A_IWL<6721> A_IWL<6720> A_IWL<6719> A_IWL<6718> A_IWL<6717> A_IWL<6716> A_IWL<6715> A_IWL<6714> A_IWL<6713> A_IWL<6712> A_IWL<6711> A_IWL<6710> A_IWL<6709> A_IWL<6708> A_IWL<6707> A_IWL<6706> A_IWL<6705> A_IWL<6704> A_IWL<6703> A_IWL<6702> A_IWL<6701> A_IWL<6700> A_IWL<6699> A_IWL<6698> A_IWL<6697> A_IWL<6696> A_IWL<6695> A_IWL<6694> A_IWL<6693> A_IWL<6692> A_IWL<6691> A_IWL<6690> A_IWL<6689> A_IWL<6688> A_IWL<6687> A_IWL<6686> A_IWL<6685> A_IWL<6684> A_IWL<6683> A_IWL<6682> A_IWL<6681> A_IWL<6680> A_IWL<6679> A_IWL<6678> A_IWL<6677> A_IWL<6676> A_IWL<6675> A_IWL<6674> A_IWL<6673> A_IWL<6672> A_IWL<6671> A_IWL<6670> A_IWL<6669> A_IWL<6668> A_IWL<6667> A_IWL<6666> A_IWL<6665> A_IWL<6664> A_IWL<6663> A_IWL<6662> A_IWL<6661> A_IWL<6660> A_IWL<6659> A_IWL<6658> A_IWL<6657> A_IWL<6656> A_IWL<7167> A_IWL<7166> A_IWL<7165> A_IWL<7164> A_IWL<7163> A_IWL<7162> A_IWL<7161> A_IWL<7160> A_IWL<7159> A_IWL<7158> A_IWL<7157> A_IWL<7156> A_IWL<7155> A_IWL<7154> A_IWL<7153> A_IWL<7152> A_IWL<7151> A_IWL<7150> A_IWL<7149> A_IWL<7148> A_IWL<7147> A_IWL<7146> A_IWL<7145> A_IWL<7144> A_IWL<7143> A_IWL<7142> A_IWL<7141> A_IWL<7140> A_IWL<7139> A_IWL<7138> A_IWL<7137> A_IWL<7136> A_IWL<7135> A_IWL<7134> A_IWL<7133> A_IWL<7132> A_IWL<7131> A_IWL<7130> A_IWL<7129> A_IWL<7128> A_IWL<7127> A_IWL<7126> A_IWL<7125> A_IWL<7124> A_IWL<7123> A_IWL<7122> A_IWL<7121> A_IWL<7120> A_IWL<7119> A_IWL<7118> A_IWL<7117> A_IWL<7116> A_IWL<7115> A_IWL<7114> A_IWL<7113> A_IWL<7112> A_IWL<7111> A_IWL<7110> A_IWL<7109> A_IWL<7108> A_IWL<7107> A_IWL<7106> A_IWL<7105> A_IWL<7104> A_IWL<7103> A_IWL<7102> A_IWL<7101> A_IWL<7100> A_IWL<7099> A_IWL<7098> A_IWL<7097> A_IWL<7096> A_IWL<7095> A_IWL<7094> A_IWL<7093> A_IWL<7092> A_IWL<7091> A_IWL<7090> A_IWL<7089> A_IWL<7088> A_IWL<7087> A_IWL<7086> A_IWL<7085> A_IWL<7084> A_IWL<7083> A_IWL<7082> A_IWL<7081> A_IWL<7080> A_IWL<7079> A_IWL<7078> A_IWL<7077> A_IWL<7076> A_IWL<7075> A_IWL<7074> A_IWL<7073> A_IWL<7072> A_IWL<7071> A_IWL<7070> A_IWL<7069> A_IWL<7068> A_IWL<7067> A_IWL<7066> A_IWL<7065> A_IWL<7064> A_IWL<7063> A_IWL<7062> A_IWL<7061> A_IWL<7060> A_IWL<7059> A_IWL<7058> A_IWL<7057> A_IWL<7056> A_IWL<7055> A_IWL<7054> A_IWL<7053> A_IWL<7052> A_IWL<7051> A_IWL<7050> A_IWL<7049> A_IWL<7048> A_IWL<7047> A_IWL<7046> A_IWL<7045> A_IWL<7044> A_IWL<7043> A_IWL<7042> A_IWL<7041> A_IWL<7040> A_IWL<7039> A_IWL<7038> A_IWL<7037> A_IWL<7036> A_IWL<7035> A_IWL<7034> A_IWL<7033> A_IWL<7032> A_IWL<7031> A_IWL<7030> A_IWL<7029> A_IWL<7028> A_IWL<7027> A_IWL<7026> A_IWL<7025> A_IWL<7024> A_IWL<7023> A_IWL<7022> A_IWL<7021> A_IWL<7020> A_IWL<7019> A_IWL<7018> A_IWL<7017> A_IWL<7016> A_IWL<7015> A_IWL<7014> A_IWL<7013> A_IWL<7012> A_IWL<7011> A_IWL<7010> A_IWL<7009> A_IWL<7008> A_IWL<7007> A_IWL<7006> A_IWL<7005> A_IWL<7004> A_IWL<7003> A_IWL<7002> A_IWL<7001> A_IWL<7000> A_IWL<6999> A_IWL<6998> A_IWL<6997> A_IWL<6996> A_IWL<6995> A_IWL<6994> A_IWL<6993> A_IWL<6992> A_IWL<6991> A_IWL<6990> A_IWL<6989> A_IWL<6988> A_IWL<6987> A_IWL<6986> A_IWL<6985> A_IWL<6984> A_IWL<6983> A_IWL<6982> A_IWL<6981> A_IWL<6980> A_IWL<6979> A_IWL<6978> A_IWL<6977> A_IWL<6976> A_IWL<6975> A_IWL<6974> A_IWL<6973> A_IWL<6972> A_IWL<6971> A_IWL<6970> A_IWL<6969> A_IWL<6968> A_IWL<6967> A_IWL<6966> A_IWL<6965> A_IWL<6964> A_IWL<6963> A_IWL<6962> A_IWL<6961> A_IWL<6960> A_IWL<6959> A_IWL<6958> A_IWL<6957> A_IWL<6956> A_IWL<6955> A_IWL<6954> A_IWL<6953> A_IWL<6952> A_IWL<6951> A_IWL<6950> A_IWL<6949> A_IWL<6948> A_IWL<6947> A_IWL<6946> A_IWL<6945> A_IWL<6944> A_IWL<6943> A_IWL<6942> A_IWL<6941> A_IWL<6940> A_IWL<6939> A_IWL<6938> A_IWL<6937> A_IWL<6936> A_IWL<6935> A_IWL<6934> A_IWL<6933> A_IWL<6932> A_IWL<6931> A_IWL<6930> A_IWL<6929> A_IWL<6928> A_IWL<6927> A_IWL<6926> A_IWL<6925> A_IWL<6924> A_IWL<6923> A_IWL<6922> A_IWL<6921> A_IWL<6920> A_IWL<6919> A_IWL<6918> A_IWL<6917> A_IWL<6916> A_IWL<6915> A_IWL<6914> A_IWL<6913> A_IWL<6912> B_BLC<55> B_BLC<54> B_BLC_TOP<55> B_BLC_TOP<54> B_BLT<55> B_BLT<54> B_BLT_TOP<55> B_BLT_TOP<54> B_IWL<6911> B_IWL<6910> B_IWL<6909> B_IWL<6908> B_IWL<6907> B_IWL<6906> B_IWL<6905> B_IWL<6904> B_IWL<6903> B_IWL<6902> B_IWL<6901> B_IWL<6900> B_IWL<6899> B_IWL<6898> B_IWL<6897> B_IWL<6896> B_IWL<6895> B_IWL<6894> B_IWL<6893> B_IWL<6892> B_IWL<6891> B_IWL<6890> B_IWL<6889> B_IWL<6888> B_IWL<6887> B_IWL<6886> B_IWL<6885> B_IWL<6884> B_IWL<6883> B_IWL<6882> B_IWL<6881> B_IWL<6880> B_IWL<6879> B_IWL<6878> B_IWL<6877> B_IWL<6876> B_IWL<6875> B_IWL<6874> B_IWL<6873> B_IWL<6872> B_IWL<6871> B_IWL<6870> B_IWL<6869> B_IWL<6868> B_IWL<6867> B_IWL<6866> B_IWL<6865> B_IWL<6864> B_IWL<6863> B_IWL<6862> B_IWL<6861> B_IWL<6860> B_IWL<6859> B_IWL<6858> B_IWL<6857> B_IWL<6856> B_IWL<6855> B_IWL<6854> B_IWL<6853> B_IWL<6852> B_IWL<6851> B_IWL<6850> B_IWL<6849> B_IWL<6848> B_IWL<6847> B_IWL<6846> B_IWL<6845> B_IWL<6844> B_IWL<6843> B_IWL<6842> B_IWL<6841> B_IWL<6840> B_IWL<6839> B_IWL<6838> B_IWL<6837> B_IWL<6836> B_IWL<6835> B_IWL<6834> B_IWL<6833> B_IWL<6832> B_IWL<6831> B_IWL<6830> B_IWL<6829> B_IWL<6828> B_IWL<6827> B_IWL<6826> B_IWL<6825> B_IWL<6824> B_IWL<6823> B_IWL<6822> B_IWL<6821> B_IWL<6820> B_IWL<6819> B_IWL<6818> B_IWL<6817> B_IWL<6816> B_IWL<6815> B_IWL<6814> B_IWL<6813> B_IWL<6812> B_IWL<6811> B_IWL<6810> B_IWL<6809> B_IWL<6808> B_IWL<6807> B_IWL<6806> B_IWL<6805> B_IWL<6804> B_IWL<6803> B_IWL<6802> B_IWL<6801> B_IWL<6800> B_IWL<6799> B_IWL<6798> B_IWL<6797> B_IWL<6796> B_IWL<6795> B_IWL<6794> B_IWL<6793> B_IWL<6792> B_IWL<6791> B_IWL<6790> B_IWL<6789> B_IWL<6788> B_IWL<6787> B_IWL<6786> B_IWL<6785> B_IWL<6784> B_IWL<6783> B_IWL<6782> B_IWL<6781> B_IWL<6780> B_IWL<6779> B_IWL<6778> B_IWL<6777> B_IWL<6776> B_IWL<6775> B_IWL<6774> B_IWL<6773> B_IWL<6772> B_IWL<6771> B_IWL<6770> B_IWL<6769> B_IWL<6768> B_IWL<6767> B_IWL<6766> B_IWL<6765> B_IWL<6764> B_IWL<6763> B_IWL<6762> B_IWL<6761> B_IWL<6760> B_IWL<6759> B_IWL<6758> B_IWL<6757> B_IWL<6756> B_IWL<6755> B_IWL<6754> B_IWL<6753> B_IWL<6752> B_IWL<6751> B_IWL<6750> B_IWL<6749> B_IWL<6748> B_IWL<6747> B_IWL<6746> B_IWL<6745> B_IWL<6744> B_IWL<6743> B_IWL<6742> B_IWL<6741> B_IWL<6740> B_IWL<6739> B_IWL<6738> B_IWL<6737> B_IWL<6736> B_IWL<6735> B_IWL<6734> B_IWL<6733> B_IWL<6732> B_IWL<6731> B_IWL<6730> B_IWL<6729> B_IWL<6728> B_IWL<6727> B_IWL<6726> B_IWL<6725> B_IWL<6724> B_IWL<6723> B_IWL<6722> B_IWL<6721> B_IWL<6720> B_IWL<6719> B_IWL<6718> B_IWL<6717> B_IWL<6716> B_IWL<6715> B_IWL<6714> B_IWL<6713> B_IWL<6712> B_IWL<6711> B_IWL<6710> B_IWL<6709> B_IWL<6708> B_IWL<6707> B_IWL<6706> B_IWL<6705> B_IWL<6704> B_IWL<6703> B_IWL<6702> B_IWL<6701> B_IWL<6700> B_IWL<6699> B_IWL<6698> B_IWL<6697> B_IWL<6696> B_IWL<6695> B_IWL<6694> B_IWL<6693> B_IWL<6692> B_IWL<6691> B_IWL<6690> B_IWL<6689> B_IWL<6688> B_IWL<6687> B_IWL<6686> B_IWL<6685> B_IWL<6684> B_IWL<6683> B_IWL<6682> B_IWL<6681> B_IWL<6680> B_IWL<6679> B_IWL<6678> B_IWL<6677> B_IWL<6676> B_IWL<6675> B_IWL<6674> B_IWL<6673> B_IWL<6672> B_IWL<6671> B_IWL<6670> B_IWL<6669> B_IWL<6668> B_IWL<6667> B_IWL<6666> B_IWL<6665> B_IWL<6664> B_IWL<6663> B_IWL<6662> B_IWL<6661> B_IWL<6660> B_IWL<6659> B_IWL<6658> B_IWL<6657> B_IWL<6656> B_IWL<7167> B_IWL<7166> B_IWL<7165> B_IWL<7164> B_IWL<7163> B_IWL<7162> B_IWL<7161> B_IWL<7160> B_IWL<7159> B_IWL<7158> B_IWL<7157> B_IWL<7156> B_IWL<7155> B_IWL<7154> B_IWL<7153> B_IWL<7152> B_IWL<7151> B_IWL<7150> B_IWL<7149> B_IWL<7148> B_IWL<7147> B_IWL<7146> B_IWL<7145> B_IWL<7144> B_IWL<7143> B_IWL<7142> B_IWL<7141> B_IWL<7140> B_IWL<7139> B_IWL<7138> B_IWL<7137> B_IWL<7136> B_IWL<7135> B_IWL<7134> B_IWL<7133> B_IWL<7132> B_IWL<7131> B_IWL<7130> B_IWL<7129> B_IWL<7128> B_IWL<7127> B_IWL<7126> B_IWL<7125> B_IWL<7124> B_IWL<7123> B_IWL<7122> B_IWL<7121> B_IWL<7120> B_IWL<7119> B_IWL<7118> B_IWL<7117> B_IWL<7116> B_IWL<7115> B_IWL<7114> B_IWL<7113> B_IWL<7112> B_IWL<7111> B_IWL<7110> B_IWL<7109> B_IWL<7108> B_IWL<7107> B_IWL<7106> B_IWL<7105> B_IWL<7104> B_IWL<7103> B_IWL<7102> B_IWL<7101> B_IWL<7100> B_IWL<7099> B_IWL<7098> B_IWL<7097> B_IWL<7096> B_IWL<7095> B_IWL<7094> B_IWL<7093> B_IWL<7092> B_IWL<7091> B_IWL<7090> B_IWL<7089> B_IWL<7088> B_IWL<7087> B_IWL<7086> B_IWL<7085> B_IWL<7084> B_IWL<7083> B_IWL<7082> B_IWL<7081> B_IWL<7080> B_IWL<7079> B_IWL<7078> B_IWL<7077> B_IWL<7076> B_IWL<7075> B_IWL<7074> B_IWL<7073> B_IWL<7072> B_IWL<7071> B_IWL<7070> B_IWL<7069> B_IWL<7068> B_IWL<7067> B_IWL<7066> B_IWL<7065> B_IWL<7064> B_IWL<7063> B_IWL<7062> B_IWL<7061> B_IWL<7060> B_IWL<7059> B_IWL<7058> B_IWL<7057> B_IWL<7056> B_IWL<7055> B_IWL<7054> B_IWL<7053> B_IWL<7052> B_IWL<7051> B_IWL<7050> B_IWL<7049> B_IWL<7048> B_IWL<7047> B_IWL<7046> B_IWL<7045> B_IWL<7044> B_IWL<7043> B_IWL<7042> B_IWL<7041> B_IWL<7040> B_IWL<7039> B_IWL<7038> B_IWL<7037> B_IWL<7036> B_IWL<7035> B_IWL<7034> B_IWL<7033> B_IWL<7032> B_IWL<7031> B_IWL<7030> B_IWL<7029> B_IWL<7028> B_IWL<7027> B_IWL<7026> B_IWL<7025> B_IWL<7024> B_IWL<7023> B_IWL<7022> B_IWL<7021> B_IWL<7020> B_IWL<7019> B_IWL<7018> B_IWL<7017> B_IWL<7016> B_IWL<7015> B_IWL<7014> B_IWL<7013> B_IWL<7012> B_IWL<7011> B_IWL<7010> B_IWL<7009> B_IWL<7008> B_IWL<7007> B_IWL<7006> B_IWL<7005> B_IWL<7004> B_IWL<7003> B_IWL<7002> B_IWL<7001> B_IWL<7000> B_IWL<6999> B_IWL<6998> B_IWL<6997> B_IWL<6996> B_IWL<6995> B_IWL<6994> B_IWL<6993> B_IWL<6992> B_IWL<6991> B_IWL<6990> B_IWL<6989> B_IWL<6988> B_IWL<6987> B_IWL<6986> B_IWL<6985> B_IWL<6984> B_IWL<6983> B_IWL<6982> B_IWL<6981> B_IWL<6980> B_IWL<6979> B_IWL<6978> B_IWL<6977> B_IWL<6976> B_IWL<6975> B_IWL<6974> B_IWL<6973> B_IWL<6972> B_IWL<6971> B_IWL<6970> B_IWL<6969> B_IWL<6968> B_IWL<6967> B_IWL<6966> B_IWL<6965> B_IWL<6964> B_IWL<6963> B_IWL<6962> B_IWL<6961> B_IWL<6960> B_IWL<6959> B_IWL<6958> B_IWL<6957> B_IWL<6956> B_IWL<6955> B_IWL<6954> B_IWL<6953> B_IWL<6952> B_IWL<6951> B_IWL<6950> B_IWL<6949> B_IWL<6948> B_IWL<6947> B_IWL<6946> B_IWL<6945> B_IWL<6944> B_IWL<6943> B_IWL<6942> B_IWL<6941> B_IWL<6940> B_IWL<6939> B_IWL<6938> B_IWL<6937> B_IWL<6936> B_IWL<6935> B_IWL<6934> B_IWL<6933> B_IWL<6932> B_IWL<6931> B_IWL<6930> B_IWL<6929> B_IWL<6928> B_IWL<6927> B_IWL<6926> B_IWL<6925> B_IWL<6924> B_IWL<6923> B_IWL<6922> B_IWL<6921> B_IWL<6920> B_IWL<6919> B_IWL<6918> B_IWL<6917> B_IWL<6916> B_IWL<6915> B_IWL<6914> B_IWL<6913> B_IWL<6912> VDD_CORE VSS / RM_IHPSG13_1024x32_c2_2P_COLUMN_pcell_0 +XCOL<26> A_BLC<53> A_BLC<52> A_BLC_TOP<53> A_BLC_TOP<52> A_BLT<53> A_BLT<52> A_BLT_TOP<53> A_BLT_TOP<52> A_IWL<6655> A_IWL<6654> A_IWL<6653> A_IWL<6652> A_IWL<6651> A_IWL<6650> A_IWL<6649> A_IWL<6648> A_IWL<6647> A_IWL<6646> A_IWL<6645> A_IWL<6644> A_IWL<6643> A_IWL<6642> A_IWL<6641> A_IWL<6640> A_IWL<6639> A_IWL<6638> A_IWL<6637> A_IWL<6636> A_IWL<6635> A_IWL<6634> A_IWL<6633> A_IWL<6632> A_IWL<6631> A_IWL<6630> A_IWL<6629> A_IWL<6628> A_IWL<6627> A_IWL<6626> A_IWL<6625> A_IWL<6624> A_IWL<6623> A_IWL<6622> A_IWL<6621> A_IWL<6620> A_IWL<6619> A_IWL<6618> A_IWL<6617> A_IWL<6616> A_IWL<6615> A_IWL<6614> A_IWL<6613> A_IWL<6612> A_IWL<6611> A_IWL<6610> A_IWL<6609> A_IWL<6608> A_IWL<6607> A_IWL<6606> A_IWL<6605> A_IWL<6604> A_IWL<6603> A_IWL<6602> A_IWL<6601> A_IWL<6600> A_IWL<6599> A_IWL<6598> A_IWL<6597> A_IWL<6596> A_IWL<6595> A_IWL<6594> A_IWL<6593> A_IWL<6592> A_IWL<6591> A_IWL<6590> A_IWL<6589> A_IWL<6588> A_IWL<6587> A_IWL<6586> A_IWL<6585> A_IWL<6584> A_IWL<6583> A_IWL<6582> A_IWL<6581> A_IWL<6580> A_IWL<6579> A_IWL<6578> A_IWL<6577> A_IWL<6576> A_IWL<6575> A_IWL<6574> A_IWL<6573> A_IWL<6572> A_IWL<6571> A_IWL<6570> A_IWL<6569> A_IWL<6568> A_IWL<6567> A_IWL<6566> A_IWL<6565> A_IWL<6564> A_IWL<6563> A_IWL<6562> A_IWL<6561> A_IWL<6560> A_IWL<6559> A_IWL<6558> A_IWL<6557> A_IWL<6556> A_IWL<6555> A_IWL<6554> A_IWL<6553> A_IWL<6552> A_IWL<6551> A_IWL<6550> A_IWL<6549> A_IWL<6548> A_IWL<6547> A_IWL<6546> A_IWL<6545> A_IWL<6544> A_IWL<6543> A_IWL<6542> A_IWL<6541> A_IWL<6540> A_IWL<6539> A_IWL<6538> A_IWL<6537> A_IWL<6536> A_IWL<6535> A_IWL<6534> A_IWL<6533> A_IWL<6532> A_IWL<6531> A_IWL<6530> A_IWL<6529> A_IWL<6528> A_IWL<6527> A_IWL<6526> A_IWL<6525> A_IWL<6524> A_IWL<6523> A_IWL<6522> A_IWL<6521> A_IWL<6520> A_IWL<6519> A_IWL<6518> A_IWL<6517> A_IWL<6516> A_IWL<6515> A_IWL<6514> A_IWL<6513> A_IWL<6512> A_IWL<6511> A_IWL<6510> A_IWL<6509> A_IWL<6508> A_IWL<6507> A_IWL<6506> A_IWL<6505> A_IWL<6504> A_IWL<6503> A_IWL<6502> A_IWL<6501> A_IWL<6500> A_IWL<6499> A_IWL<6498> A_IWL<6497> A_IWL<6496> A_IWL<6495> A_IWL<6494> A_IWL<6493> A_IWL<6492> A_IWL<6491> A_IWL<6490> A_IWL<6489> A_IWL<6488> A_IWL<6487> A_IWL<6486> A_IWL<6485> A_IWL<6484> A_IWL<6483> A_IWL<6482> A_IWL<6481> A_IWL<6480> A_IWL<6479> A_IWL<6478> A_IWL<6477> A_IWL<6476> A_IWL<6475> A_IWL<6474> A_IWL<6473> A_IWL<6472> A_IWL<6471> A_IWL<6470> A_IWL<6469> A_IWL<6468> A_IWL<6467> A_IWL<6466> A_IWL<6465> A_IWL<6464> A_IWL<6463> A_IWL<6462> A_IWL<6461> A_IWL<6460> A_IWL<6459> A_IWL<6458> A_IWL<6457> A_IWL<6456> A_IWL<6455> A_IWL<6454> A_IWL<6453> A_IWL<6452> A_IWL<6451> A_IWL<6450> A_IWL<6449> A_IWL<6448> A_IWL<6447> A_IWL<6446> A_IWL<6445> A_IWL<6444> A_IWL<6443> A_IWL<6442> A_IWL<6441> A_IWL<6440> A_IWL<6439> A_IWL<6438> A_IWL<6437> A_IWL<6436> A_IWL<6435> A_IWL<6434> A_IWL<6433> A_IWL<6432> A_IWL<6431> A_IWL<6430> A_IWL<6429> A_IWL<6428> A_IWL<6427> A_IWL<6426> A_IWL<6425> A_IWL<6424> A_IWL<6423> A_IWL<6422> A_IWL<6421> A_IWL<6420> A_IWL<6419> A_IWL<6418> A_IWL<6417> A_IWL<6416> A_IWL<6415> A_IWL<6414> A_IWL<6413> A_IWL<6412> A_IWL<6411> A_IWL<6410> A_IWL<6409> A_IWL<6408> A_IWL<6407> A_IWL<6406> A_IWL<6405> A_IWL<6404> A_IWL<6403> A_IWL<6402> A_IWL<6401> A_IWL<6400> A_IWL<6911> A_IWL<6910> A_IWL<6909> A_IWL<6908> A_IWL<6907> A_IWL<6906> A_IWL<6905> A_IWL<6904> A_IWL<6903> A_IWL<6902> A_IWL<6901> A_IWL<6900> A_IWL<6899> A_IWL<6898> A_IWL<6897> A_IWL<6896> A_IWL<6895> A_IWL<6894> A_IWL<6893> A_IWL<6892> A_IWL<6891> A_IWL<6890> A_IWL<6889> A_IWL<6888> A_IWL<6887> A_IWL<6886> A_IWL<6885> A_IWL<6884> A_IWL<6883> A_IWL<6882> A_IWL<6881> A_IWL<6880> A_IWL<6879> A_IWL<6878> A_IWL<6877> A_IWL<6876> A_IWL<6875> A_IWL<6874> A_IWL<6873> A_IWL<6872> A_IWL<6871> A_IWL<6870> A_IWL<6869> A_IWL<6868> A_IWL<6867> A_IWL<6866> A_IWL<6865> A_IWL<6864> A_IWL<6863> A_IWL<6862> A_IWL<6861> A_IWL<6860> A_IWL<6859> A_IWL<6858> A_IWL<6857> A_IWL<6856> A_IWL<6855> A_IWL<6854> A_IWL<6853> A_IWL<6852> A_IWL<6851> A_IWL<6850> A_IWL<6849> A_IWL<6848> A_IWL<6847> A_IWL<6846> A_IWL<6845> A_IWL<6844> A_IWL<6843> A_IWL<6842> A_IWL<6841> A_IWL<6840> A_IWL<6839> A_IWL<6838> A_IWL<6837> A_IWL<6836> A_IWL<6835> A_IWL<6834> A_IWL<6833> A_IWL<6832> A_IWL<6831> A_IWL<6830> A_IWL<6829> A_IWL<6828> A_IWL<6827> A_IWL<6826> A_IWL<6825> A_IWL<6824> A_IWL<6823> A_IWL<6822> A_IWL<6821> A_IWL<6820> A_IWL<6819> A_IWL<6818> A_IWL<6817> A_IWL<6816> A_IWL<6815> A_IWL<6814> A_IWL<6813> A_IWL<6812> A_IWL<6811> A_IWL<6810> A_IWL<6809> A_IWL<6808> A_IWL<6807> A_IWL<6806> A_IWL<6805> A_IWL<6804> A_IWL<6803> A_IWL<6802> A_IWL<6801> A_IWL<6800> A_IWL<6799> A_IWL<6798> A_IWL<6797> A_IWL<6796> A_IWL<6795> A_IWL<6794> A_IWL<6793> A_IWL<6792> A_IWL<6791> A_IWL<6790> A_IWL<6789> A_IWL<6788> A_IWL<6787> A_IWL<6786> A_IWL<6785> A_IWL<6784> A_IWL<6783> A_IWL<6782> A_IWL<6781> A_IWL<6780> A_IWL<6779> A_IWL<6778> A_IWL<6777> A_IWL<6776> A_IWL<6775> A_IWL<6774> A_IWL<6773> A_IWL<6772> A_IWL<6771> A_IWL<6770> A_IWL<6769> A_IWL<6768> A_IWL<6767> A_IWL<6766> A_IWL<6765> A_IWL<6764> A_IWL<6763> A_IWL<6762> A_IWL<6761> A_IWL<6760> A_IWL<6759> A_IWL<6758> A_IWL<6757> A_IWL<6756> A_IWL<6755> A_IWL<6754> A_IWL<6753> A_IWL<6752> A_IWL<6751> A_IWL<6750> A_IWL<6749> A_IWL<6748> A_IWL<6747> A_IWL<6746> A_IWL<6745> A_IWL<6744> A_IWL<6743> A_IWL<6742> A_IWL<6741> A_IWL<6740> A_IWL<6739> A_IWL<6738> A_IWL<6737> A_IWL<6736> A_IWL<6735> A_IWL<6734> A_IWL<6733> A_IWL<6732> A_IWL<6731> A_IWL<6730> A_IWL<6729> A_IWL<6728> A_IWL<6727> A_IWL<6726> A_IWL<6725> A_IWL<6724> A_IWL<6723> A_IWL<6722> A_IWL<6721> A_IWL<6720> A_IWL<6719> A_IWL<6718> A_IWL<6717> A_IWL<6716> A_IWL<6715> A_IWL<6714> A_IWL<6713> A_IWL<6712> A_IWL<6711> A_IWL<6710> A_IWL<6709> A_IWL<6708> A_IWL<6707> A_IWL<6706> A_IWL<6705> A_IWL<6704> A_IWL<6703> A_IWL<6702> A_IWL<6701> A_IWL<6700> A_IWL<6699> A_IWL<6698> A_IWL<6697> A_IWL<6696> A_IWL<6695> A_IWL<6694> A_IWL<6693> A_IWL<6692> A_IWL<6691> A_IWL<6690> A_IWL<6689> A_IWL<6688> A_IWL<6687> A_IWL<6686> A_IWL<6685> A_IWL<6684> A_IWL<6683> A_IWL<6682> A_IWL<6681> A_IWL<6680> A_IWL<6679> A_IWL<6678> A_IWL<6677> A_IWL<6676> A_IWL<6675> A_IWL<6674> A_IWL<6673> A_IWL<6672> A_IWL<6671> A_IWL<6670> A_IWL<6669> A_IWL<6668> A_IWL<6667> A_IWL<6666> A_IWL<6665> A_IWL<6664> A_IWL<6663> A_IWL<6662> A_IWL<6661> A_IWL<6660> A_IWL<6659> A_IWL<6658> A_IWL<6657> A_IWL<6656> B_BLC<53> B_BLC<52> B_BLC_TOP<53> B_BLC_TOP<52> B_BLT<53> B_BLT<52> B_BLT_TOP<53> B_BLT_TOP<52> B_IWL<6655> B_IWL<6654> B_IWL<6653> B_IWL<6652> B_IWL<6651> B_IWL<6650> B_IWL<6649> B_IWL<6648> B_IWL<6647> B_IWL<6646> B_IWL<6645> B_IWL<6644> B_IWL<6643> B_IWL<6642> B_IWL<6641> B_IWL<6640> B_IWL<6639> B_IWL<6638> B_IWL<6637> B_IWL<6636> B_IWL<6635> B_IWL<6634> B_IWL<6633> B_IWL<6632> B_IWL<6631> B_IWL<6630> B_IWL<6629> B_IWL<6628> B_IWL<6627> B_IWL<6626> B_IWL<6625> B_IWL<6624> B_IWL<6623> B_IWL<6622> B_IWL<6621> B_IWL<6620> B_IWL<6619> B_IWL<6618> B_IWL<6617> B_IWL<6616> B_IWL<6615> B_IWL<6614> B_IWL<6613> B_IWL<6612> B_IWL<6611> B_IWL<6610> B_IWL<6609> B_IWL<6608> B_IWL<6607> B_IWL<6606> B_IWL<6605> B_IWL<6604> B_IWL<6603> B_IWL<6602> B_IWL<6601> B_IWL<6600> B_IWL<6599> B_IWL<6598> B_IWL<6597> B_IWL<6596> B_IWL<6595> B_IWL<6594> B_IWL<6593> B_IWL<6592> B_IWL<6591> B_IWL<6590> B_IWL<6589> B_IWL<6588> B_IWL<6587> B_IWL<6586> B_IWL<6585> B_IWL<6584> B_IWL<6583> B_IWL<6582> B_IWL<6581> B_IWL<6580> B_IWL<6579> B_IWL<6578> B_IWL<6577> B_IWL<6576> B_IWL<6575> B_IWL<6574> B_IWL<6573> B_IWL<6572> B_IWL<6571> B_IWL<6570> B_IWL<6569> B_IWL<6568> B_IWL<6567> B_IWL<6566> B_IWL<6565> B_IWL<6564> B_IWL<6563> B_IWL<6562> B_IWL<6561> B_IWL<6560> B_IWL<6559> B_IWL<6558> B_IWL<6557> B_IWL<6556> B_IWL<6555> B_IWL<6554> B_IWL<6553> B_IWL<6552> B_IWL<6551> B_IWL<6550> B_IWL<6549> B_IWL<6548> B_IWL<6547> B_IWL<6546> B_IWL<6545> B_IWL<6544> B_IWL<6543> B_IWL<6542> B_IWL<6541> B_IWL<6540> B_IWL<6539> B_IWL<6538> B_IWL<6537> B_IWL<6536> B_IWL<6535> B_IWL<6534> B_IWL<6533> B_IWL<6532> B_IWL<6531> B_IWL<6530> B_IWL<6529> B_IWL<6528> B_IWL<6527> B_IWL<6526> B_IWL<6525> B_IWL<6524> B_IWL<6523> B_IWL<6522> B_IWL<6521> B_IWL<6520> B_IWL<6519> B_IWL<6518> B_IWL<6517> B_IWL<6516> B_IWL<6515> B_IWL<6514> B_IWL<6513> B_IWL<6512> B_IWL<6511> B_IWL<6510> B_IWL<6509> B_IWL<6508> B_IWL<6507> B_IWL<6506> B_IWL<6505> B_IWL<6504> B_IWL<6503> B_IWL<6502> B_IWL<6501> B_IWL<6500> B_IWL<6499> B_IWL<6498> B_IWL<6497> B_IWL<6496> B_IWL<6495> B_IWL<6494> B_IWL<6493> B_IWL<6492> B_IWL<6491> B_IWL<6490> B_IWL<6489> B_IWL<6488> B_IWL<6487> B_IWL<6486> B_IWL<6485> B_IWL<6484> B_IWL<6483> B_IWL<6482> B_IWL<6481> B_IWL<6480> B_IWL<6479> B_IWL<6478> B_IWL<6477> B_IWL<6476> B_IWL<6475> B_IWL<6474> B_IWL<6473> B_IWL<6472> B_IWL<6471> B_IWL<6470> B_IWL<6469> B_IWL<6468> B_IWL<6467> B_IWL<6466> B_IWL<6465> B_IWL<6464> B_IWL<6463> B_IWL<6462> B_IWL<6461> B_IWL<6460> B_IWL<6459> B_IWL<6458> B_IWL<6457> B_IWL<6456> B_IWL<6455> B_IWL<6454> B_IWL<6453> B_IWL<6452> B_IWL<6451> B_IWL<6450> B_IWL<6449> B_IWL<6448> B_IWL<6447> B_IWL<6446> B_IWL<6445> B_IWL<6444> B_IWL<6443> B_IWL<6442> B_IWL<6441> B_IWL<6440> B_IWL<6439> B_IWL<6438> B_IWL<6437> B_IWL<6436> B_IWL<6435> B_IWL<6434> B_IWL<6433> B_IWL<6432> B_IWL<6431> B_IWL<6430> B_IWL<6429> B_IWL<6428> B_IWL<6427> B_IWL<6426> B_IWL<6425> B_IWL<6424> B_IWL<6423> B_IWL<6422> B_IWL<6421> B_IWL<6420> B_IWL<6419> B_IWL<6418> B_IWL<6417> B_IWL<6416> B_IWL<6415> B_IWL<6414> B_IWL<6413> B_IWL<6412> B_IWL<6411> B_IWL<6410> B_IWL<6409> B_IWL<6408> B_IWL<6407> B_IWL<6406> B_IWL<6405> B_IWL<6404> B_IWL<6403> B_IWL<6402> B_IWL<6401> B_IWL<6400> B_IWL<6911> B_IWL<6910> B_IWL<6909> B_IWL<6908> B_IWL<6907> B_IWL<6906> B_IWL<6905> B_IWL<6904> B_IWL<6903> B_IWL<6902> B_IWL<6901> B_IWL<6900> B_IWL<6899> B_IWL<6898> B_IWL<6897> B_IWL<6896> B_IWL<6895> B_IWL<6894> B_IWL<6893> B_IWL<6892> B_IWL<6891> B_IWL<6890> B_IWL<6889> B_IWL<6888> B_IWL<6887> B_IWL<6886> B_IWL<6885> B_IWL<6884> B_IWL<6883> B_IWL<6882> B_IWL<6881> B_IWL<6880> B_IWL<6879> B_IWL<6878> B_IWL<6877> B_IWL<6876> B_IWL<6875> B_IWL<6874> B_IWL<6873> B_IWL<6872> B_IWL<6871> B_IWL<6870> B_IWL<6869> B_IWL<6868> B_IWL<6867> B_IWL<6866> B_IWL<6865> B_IWL<6864> B_IWL<6863> B_IWL<6862> B_IWL<6861> B_IWL<6860> B_IWL<6859> B_IWL<6858> B_IWL<6857> B_IWL<6856> B_IWL<6855> B_IWL<6854> B_IWL<6853> B_IWL<6852> B_IWL<6851> B_IWL<6850> B_IWL<6849> B_IWL<6848> B_IWL<6847> B_IWL<6846> B_IWL<6845> B_IWL<6844> B_IWL<6843> B_IWL<6842> B_IWL<6841> B_IWL<6840> B_IWL<6839> B_IWL<6838> B_IWL<6837> B_IWL<6836> B_IWL<6835> B_IWL<6834> B_IWL<6833> B_IWL<6832> B_IWL<6831> B_IWL<6830> B_IWL<6829> B_IWL<6828> B_IWL<6827> B_IWL<6826> B_IWL<6825> B_IWL<6824> B_IWL<6823> B_IWL<6822> B_IWL<6821> B_IWL<6820> B_IWL<6819> B_IWL<6818> B_IWL<6817> B_IWL<6816> B_IWL<6815> B_IWL<6814> B_IWL<6813> B_IWL<6812> B_IWL<6811> B_IWL<6810> B_IWL<6809> B_IWL<6808> B_IWL<6807> B_IWL<6806> B_IWL<6805> B_IWL<6804> B_IWL<6803> B_IWL<6802> B_IWL<6801> B_IWL<6800> B_IWL<6799> B_IWL<6798> B_IWL<6797> B_IWL<6796> B_IWL<6795> B_IWL<6794> B_IWL<6793> B_IWL<6792> B_IWL<6791> B_IWL<6790> B_IWL<6789> B_IWL<6788> B_IWL<6787> B_IWL<6786> B_IWL<6785> B_IWL<6784> B_IWL<6783> B_IWL<6782> B_IWL<6781> B_IWL<6780> B_IWL<6779> B_IWL<6778> B_IWL<6777> B_IWL<6776> B_IWL<6775> B_IWL<6774> B_IWL<6773> B_IWL<6772> B_IWL<6771> B_IWL<6770> B_IWL<6769> B_IWL<6768> B_IWL<6767> B_IWL<6766> B_IWL<6765> B_IWL<6764> B_IWL<6763> B_IWL<6762> B_IWL<6761> B_IWL<6760> B_IWL<6759> B_IWL<6758> B_IWL<6757> B_IWL<6756> B_IWL<6755> B_IWL<6754> B_IWL<6753> B_IWL<6752> B_IWL<6751> B_IWL<6750> B_IWL<6749> B_IWL<6748> B_IWL<6747> B_IWL<6746> B_IWL<6745> B_IWL<6744> B_IWL<6743> B_IWL<6742> B_IWL<6741> B_IWL<6740> B_IWL<6739> B_IWL<6738> B_IWL<6737> B_IWL<6736> B_IWL<6735> B_IWL<6734> B_IWL<6733> B_IWL<6732> B_IWL<6731> B_IWL<6730> B_IWL<6729> B_IWL<6728> B_IWL<6727> B_IWL<6726> B_IWL<6725> B_IWL<6724> B_IWL<6723> B_IWL<6722> B_IWL<6721> B_IWL<6720> B_IWL<6719> B_IWL<6718> B_IWL<6717> B_IWL<6716> B_IWL<6715> B_IWL<6714> B_IWL<6713> B_IWL<6712> B_IWL<6711> B_IWL<6710> B_IWL<6709> B_IWL<6708> B_IWL<6707> B_IWL<6706> B_IWL<6705> B_IWL<6704> B_IWL<6703> B_IWL<6702> B_IWL<6701> B_IWL<6700> B_IWL<6699> B_IWL<6698> B_IWL<6697> B_IWL<6696> B_IWL<6695> B_IWL<6694> B_IWL<6693> B_IWL<6692> B_IWL<6691> B_IWL<6690> B_IWL<6689> B_IWL<6688> B_IWL<6687> B_IWL<6686> B_IWL<6685> B_IWL<6684> B_IWL<6683> B_IWL<6682> B_IWL<6681> B_IWL<6680> B_IWL<6679> B_IWL<6678> B_IWL<6677> B_IWL<6676> B_IWL<6675> B_IWL<6674> B_IWL<6673> B_IWL<6672> B_IWL<6671> B_IWL<6670> B_IWL<6669> B_IWL<6668> B_IWL<6667> B_IWL<6666> B_IWL<6665> B_IWL<6664> B_IWL<6663> B_IWL<6662> B_IWL<6661> B_IWL<6660> B_IWL<6659> B_IWL<6658> B_IWL<6657> B_IWL<6656> VDD_CORE VSS / RM_IHPSG13_1024x32_c2_2P_COLUMN_pcell_0 +XCOL<25> A_BLC<51> A_BLC<50> A_BLC_TOP<51> A_BLC_TOP<50> A_BLT<51> A_BLT<50> A_BLT_TOP<51> A_BLT_TOP<50> A_IWL<6399> A_IWL<6398> A_IWL<6397> A_IWL<6396> A_IWL<6395> A_IWL<6394> A_IWL<6393> A_IWL<6392> A_IWL<6391> A_IWL<6390> A_IWL<6389> A_IWL<6388> A_IWL<6387> A_IWL<6386> A_IWL<6385> A_IWL<6384> A_IWL<6383> A_IWL<6382> A_IWL<6381> A_IWL<6380> A_IWL<6379> A_IWL<6378> A_IWL<6377> A_IWL<6376> A_IWL<6375> A_IWL<6374> A_IWL<6373> A_IWL<6372> A_IWL<6371> A_IWL<6370> A_IWL<6369> A_IWL<6368> A_IWL<6367> A_IWL<6366> A_IWL<6365> A_IWL<6364> A_IWL<6363> A_IWL<6362> A_IWL<6361> A_IWL<6360> A_IWL<6359> A_IWL<6358> A_IWL<6357> A_IWL<6356> A_IWL<6355> A_IWL<6354> A_IWL<6353> A_IWL<6352> A_IWL<6351> A_IWL<6350> A_IWL<6349> A_IWL<6348> A_IWL<6347> A_IWL<6346> A_IWL<6345> A_IWL<6344> A_IWL<6343> A_IWL<6342> A_IWL<6341> A_IWL<6340> A_IWL<6339> A_IWL<6338> A_IWL<6337> A_IWL<6336> A_IWL<6335> A_IWL<6334> A_IWL<6333> A_IWL<6332> A_IWL<6331> A_IWL<6330> A_IWL<6329> A_IWL<6328> A_IWL<6327> A_IWL<6326> A_IWL<6325> A_IWL<6324> A_IWL<6323> A_IWL<6322> A_IWL<6321> A_IWL<6320> A_IWL<6319> A_IWL<6318> A_IWL<6317> A_IWL<6316> A_IWL<6315> A_IWL<6314> A_IWL<6313> A_IWL<6312> A_IWL<6311> A_IWL<6310> A_IWL<6309> A_IWL<6308> A_IWL<6307> A_IWL<6306> A_IWL<6305> A_IWL<6304> A_IWL<6303> A_IWL<6302> A_IWL<6301> A_IWL<6300> A_IWL<6299> A_IWL<6298> A_IWL<6297> A_IWL<6296> A_IWL<6295> A_IWL<6294> A_IWL<6293> A_IWL<6292> A_IWL<6291> A_IWL<6290> A_IWL<6289> A_IWL<6288> A_IWL<6287> A_IWL<6286> A_IWL<6285> A_IWL<6284> A_IWL<6283> A_IWL<6282> A_IWL<6281> A_IWL<6280> A_IWL<6279> A_IWL<6278> A_IWL<6277> A_IWL<6276> A_IWL<6275> A_IWL<6274> A_IWL<6273> A_IWL<6272> A_IWL<6271> A_IWL<6270> A_IWL<6269> A_IWL<6268> A_IWL<6267> A_IWL<6266> A_IWL<6265> A_IWL<6264> A_IWL<6263> A_IWL<6262> A_IWL<6261> A_IWL<6260> A_IWL<6259> A_IWL<6258> A_IWL<6257> A_IWL<6256> A_IWL<6255> A_IWL<6254> A_IWL<6253> A_IWL<6252> A_IWL<6251> A_IWL<6250> A_IWL<6249> A_IWL<6248> A_IWL<6247> A_IWL<6246> A_IWL<6245> A_IWL<6244> A_IWL<6243> A_IWL<6242> A_IWL<6241> A_IWL<6240> A_IWL<6239> A_IWL<6238> A_IWL<6237> A_IWL<6236> A_IWL<6235> A_IWL<6234> A_IWL<6233> A_IWL<6232> A_IWL<6231> A_IWL<6230> A_IWL<6229> A_IWL<6228> A_IWL<6227> A_IWL<6226> A_IWL<6225> A_IWL<6224> A_IWL<6223> A_IWL<6222> A_IWL<6221> A_IWL<6220> A_IWL<6219> A_IWL<6218> A_IWL<6217> A_IWL<6216> A_IWL<6215> A_IWL<6214> A_IWL<6213> A_IWL<6212> A_IWL<6211> A_IWL<6210> A_IWL<6209> A_IWL<6208> A_IWL<6207> A_IWL<6206> A_IWL<6205> A_IWL<6204> A_IWL<6203> A_IWL<6202> A_IWL<6201> A_IWL<6200> A_IWL<6199> A_IWL<6198> A_IWL<6197> A_IWL<6196> A_IWL<6195> A_IWL<6194> A_IWL<6193> A_IWL<6192> A_IWL<6191> A_IWL<6190> A_IWL<6189> A_IWL<6188> A_IWL<6187> A_IWL<6186> A_IWL<6185> A_IWL<6184> A_IWL<6183> A_IWL<6182> A_IWL<6181> A_IWL<6180> A_IWL<6179> A_IWL<6178> A_IWL<6177> A_IWL<6176> A_IWL<6175> A_IWL<6174> A_IWL<6173> A_IWL<6172> A_IWL<6171> A_IWL<6170> A_IWL<6169> A_IWL<6168> A_IWL<6167> A_IWL<6166> A_IWL<6165> A_IWL<6164> A_IWL<6163> A_IWL<6162> A_IWL<6161> A_IWL<6160> A_IWL<6159> A_IWL<6158> A_IWL<6157> A_IWL<6156> A_IWL<6155> A_IWL<6154> A_IWL<6153> A_IWL<6152> A_IWL<6151> A_IWL<6150> A_IWL<6149> A_IWL<6148> A_IWL<6147> A_IWL<6146> A_IWL<6145> A_IWL<6144> A_IWL<6655> A_IWL<6654> A_IWL<6653> A_IWL<6652> A_IWL<6651> A_IWL<6650> A_IWL<6649> A_IWL<6648> A_IWL<6647> A_IWL<6646> A_IWL<6645> A_IWL<6644> A_IWL<6643> A_IWL<6642> A_IWL<6641> A_IWL<6640> A_IWL<6639> A_IWL<6638> A_IWL<6637> A_IWL<6636> A_IWL<6635> A_IWL<6634> A_IWL<6633> A_IWL<6632> A_IWL<6631> A_IWL<6630> A_IWL<6629> A_IWL<6628> A_IWL<6627> A_IWL<6626> A_IWL<6625> A_IWL<6624> A_IWL<6623> A_IWL<6622> A_IWL<6621> A_IWL<6620> A_IWL<6619> A_IWL<6618> A_IWL<6617> A_IWL<6616> A_IWL<6615> A_IWL<6614> A_IWL<6613> A_IWL<6612> A_IWL<6611> A_IWL<6610> A_IWL<6609> A_IWL<6608> A_IWL<6607> A_IWL<6606> A_IWL<6605> A_IWL<6604> A_IWL<6603> A_IWL<6602> A_IWL<6601> A_IWL<6600> A_IWL<6599> A_IWL<6598> A_IWL<6597> A_IWL<6596> A_IWL<6595> A_IWL<6594> A_IWL<6593> A_IWL<6592> A_IWL<6591> A_IWL<6590> A_IWL<6589> A_IWL<6588> A_IWL<6587> A_IWL<6586> A_IWL<6585> A_IWL<6584> A_IWL<6583> A_IWL<6582> A_IWL<6581> A_IWL<6580> A_IWL<6579> A_IWL<6578> A_IWL<6577> A_IWL<6576> A_IWL<6575> A_IWL<6574> A_IWL<6573> A_IWL<6572> A_IWL<6571> A_IWL<6570> A_IWL<6569> A_IWL<6568> A_IWL<6567> A_IWL<6566> A_IWL<6565> A_IWL<6564> A_IWL<6563> A_IWL<6562> A_IWL<6561> A_IWL<6560> A_IWL<6559> A_IWL<6558> A_IWL<6557> A_IWL<6556> A_IWL<6555> A_IWL<6554> A_IWL<6553> A_IWL<6552> A_IWL<6551> A_IWL<6550> A_IWL<6549> A_IWL<6548> A_IWL<6547> A_IWL<6546> A_IWL<6545> A_IWL<6544> A_IWL<6543> A_IWL<6542> A_IWL<6541> A_IWL<6540> A_IWL<6539> A_IWL<6538> A_IWL<6537> A_IWL<6536> A_IWL<6535> A_IWL<6534> A_IWL<6533> A_IWL<6532> A_IWL<6531> A_IWL<6530> A_IWL<6529> A_IWL<6528> A_IWL<6527> A_IWL<6526> A_IWL<6525> A_IWL<6524> A_IWL<6523> A_IWL<6522> A_IWL<6521> A_IWL<6520> A_IWL<6519> A_IWL<6518> A_IWL<6517> A_IWL<6516> A_IWL<6515> A_IWL<6514> A_IWL<6513> A_IWL<6512> A_IWL<6511> A_IWL<6510> A_IWL<6509> A_IWL<6508> A_IWL<6507> A_IWL<6506> A_IWL<6505> A_IWL<6504> A_IWL<6503> A_IWL<6502> A_IWL<6501> A_IWL<6500> A_IWL<6499> A_IWL<6498> A_IWL<6497> A_IWL<6496> A_IWL<6495> A_IWL<6494> A_IWL<6493> A_IWL<6492> A_IWL<6491> A_IWL<6490> A_IWL<6489> A_IWL<6488> A_IWL<6487> A_IWL<6486> A_IWL<6485> A_IWL<6484> A_IWL<6483> A_IWL<6482> A_IWL<6481> A_IWL<6480> A_IWL<6479> A_IWL<6478> A_IWL<6477> A_IWL<6476> A_IWL<6475> A_IWL<6474> A_IWL<6473> A_IWL<6472> A_IWL<6471> A_IWL<6470> A_IWL<6469> A_IWL<6468> A_IWL<6467> A_IWL<6466> A_IWL<6465> A_IWL<6464> A_IWL<6463> A_IWL<6462> A_IWL<6461> A_IWL<6460> A_IWL<6459> A_IWL<6458> A_IWL<6457> A_IWL<6456> A_IWL<6455> A_IWL<6454> A_IWL<6453> A_IWL<6452> A_IWL<6451> A_IWL<6450> A_IWL<6449> A_IWL<6448> A_IWL<6447> A_IWL<6446> A_IWL<6445> A_IWL<6444> A_IWL<6443> A_IWL<6442> A_IWL<6441> A_IWL<6440> A_IWL<6439> A_IWL<6438> A_IWL<6437> A_IWL<6436> A_IWL<6435> A_IWL<6434> A_IWL<6433> A_IWL<6432> A_IWL<6431> A_IWL<6430> A_IWL<6429> A_IWL<6428> A_IWL<6427> A_IWL<6426> A_IWL<6425> A_IWL<6424> A_IWL<6423> A_IWL<6422> A_IWL<6421> A_IWL<6420> A_IWL<6419> A_IWL<6418> A_IWL<6417> A_IWL<6416> A_IWL<6415> A_IWL<6414> A_IWL<6413> A_IWL<6412> A_IWL<6411> A_IWL<6410> A_IWL<6409> A_IWL<6408> A_IWL<6407> A_IWL<6406> A_IWL<6405> A_IWL<6404> A_IWL<6403> A_IWL<6402> A_IWL<6401> A_IWL<6400> B_BLC<51> B_BLC<50> B_BLC_TOP<51> B_BLC_TOP<50> B_BLT<51> B_BLT<50> B_BLT_TOP<51> B_BLT_TOP<50> B_IWL<6399> B_IWL<6398> B_IWL<6397> B_IWL<6396> B_IWL<6395> B_IWL<6394> B_IWL<6393> B_IWL<6392> B_IWL<6391> B_IWL<6390> B_IWL<6389> B_IWL<6388> B_IWL<6387> B_IWL<6386> B_IWL<6385> B_IWL<6384> B_IWL<6383> B_IWL<6382> B_IWL<6381> B_IWL<6380> B_IWL<6379> B_IWL<6378> B_IWL<6377> B_IWL<6376> B_IWL<6375> B_IWL<6374> B_IWL<6373> B_IWL<6372> B_IWL<6371> B_IWL<6370> B_IWL<6369> B_IWL<6368> B_IWL<6367> B_IWL<6366> B_IWL<6365> B_IWL<6364> B_IWL<6363> B_IWL<6362> B_IWL<6361> B_IWL<6360> B_IWL<6359> B_IWL<6358> B_IWL<6357> B_IWL<6356> B_IWL<6355> B_IWL<6354> B_IWL<6353> B_IWL<6352> B_IWL<6351> B_IWL<6350> B_IWL<6349> B_IWL<6348> B_IWL<6347> B_IWL<6346> B_IWL<6345> B_IWL<6344> B_IWL<6343> B_IWL<6342> B_IWL<6341> B_IWL<6340> B_IWL<6339> B_IWL<6338> B_IWL<6337> B_IWL<6336> B_IWL<6335> B_IWL<6334> B_IWL<6333> B_IWL<6332> B_IWL<6331> B_IWL<6330> B_IWL<6329> B_IWL<6328> B_IWL<6327> B_IWL<6326> B_IWL<6325> B_IWL<6324> B_IWL<6323> B_IWL<6322> B_IWL<6321> B_IWL<6320> B_IWL<6319> B_IWL<6318> B_IWL<6317> B_IWL<6316> B_IWL<6315> B_IWL<6314> B_IWL<6313> B_IWL<6312> B_IWL<6311> B_IWL<6310> B_IWL<6309> B_IWL<6308> B_IWL<6307> B_IWL<6306> B_IWL<6305> B_IWL<6304> B_IWL<6303> B_IWL<6302> B_IWL<6301> B_IWL<6300> B_IWL<6299> B_IWL<6298> B_IWL<6297> B_IWL<6296> B_IWL<6295> B_IWL<6294> B_IWL<6293> B_IWL<6292> B_IWL<6291> B_IWL<6290> B_IWL<6289> B_IWL<6288> B_IWL<6287> B_IWL<6286> B_IWL<6285> B_IWL<6284> B_IWL<6283> B_IWL<6282> B_IWL<6281> B_IWL<6280> B_IWL<6279> B_IWL<6278> B_IWL<6277> B_IWL<6276> B_IWL<6275> B_IWL<6274> B_IWL<6273> B_IWL<6272> B_IWL<6271> B_IWL<6270> B_IWL<6269> B_IWL<6268> B_IWL<6267> B_IWL<6266> B_IWL<6265> B_IWL<6264> B_IWL<6263> B_IWL<6262> B_IWL<6261> B_IWL<6260> B_IWL<6259> B_IWL<6258> B_IWL<6257> B_IWL<6256> B_IWL<6255> B_IWL<6254> B_IWL<6253> B_IWL<6252> B_IWL<6251> B_IWL<6250> B_IWL<6249> B_IWL<6248> B_IWL<6247> B_IWL<6246> B_IWL<6245> B_IWL<6244> B_IWL<6243> B_IWL<6242> B_IWL<6241> B_IWL<6240> B_IWL<6239> B_IWL<6238> B_IWL<6237> B_IWL<6236> B_IWL<6235> B_IWL<6234> B_IWL<6233> B_IWL<6232> B_IWL<6231> B_IWL<6230> B_IWL<6229> B_IWL<6228> B_IWL<6227> B_IWL<6226> B_IWL<6225> B_IWL<6224> B_IWL<6223> B_IWL<6222> B_IWL<6221> B_IWL<6220> B_IWL<6219> B_IWL<6218> B_IWL<6217> B_IWL<6216> B_IWL<6215> B_IWL<6214> B_IWL<6213> B_IWL<6212> B_IWL<6211> B_IWL<6210> B_IWL<6209> B_IWL<6208> B_IWL<6207> B_IWL<6206> B_IWL<6205> B_IWL<6204> B_IWL<6203> B_IWL<6202> B_IWL<6201> B_IWL<6200> B_IWL<6199> B_IWL<6198> B_IWL<6197> B_IWL<6196> B_IWL<6195> B_IWL<6194> B_IWL<6193> B_IWL<6192> B_IWL<6191> B_IWL<6190> B_IWL<6189> B_IWL<6188> B_IWL<6187> B_IWL<6186> B_IWL<6185> B_IWL<6184> B_IWL<6183> B_IWL<6182> B_IWL<6181> B_IWL<6180> B_IWL<6179> B_IWL<6178> B_IWL<6177> B_IWL<6176> B_IWL<6175> B_IWL<6174> B_IWL<6173> B_IWL<6172> B_IWL<6171> B_IWL<6170> B_IWL<6169> B_IWL<6168> B_IWL<6167> B_IWL<6166> B_IWL<6165> B_IWL<6164> B_IWL<6163> B_IWL<6162> B_IWL<6161> B_IWL<6160> B_IWL<6159> B_IWL<6158> B_IWL<6157> B_IWL<6156> B_IWL<6155> B_IWL<6154> B_IWL<6153> B_IWL<6152> B_IWL<6151> B_IWL<6150> B_IWL<6149> B_IWL<6148> B_IWL<6147> B_IWL<6146> B_IWL<6145> B_IWL<6144> B_IWL<6655> B_IWL<6654> B_IWL<6653> B_IWL<6652> B_IWL<6651> B_IWL<6650> B_IWL<6649> B_IWL<6648> B_IWL<6647> B_IWL<6646> B_IWL<6645> B_IWL<6644> B_IWL<6643> B_IWL<6642> B_IWL<6641> B_IWL<6640> B_IWL<6639> B_IWL<6638> B_IWL<6637> B_IWL<6636> B_IWL<6635> B_IWL<6634> B_IWL<6633> B_IWL<6632> B_IWL<6631> B_IWL<6630> B_IWL<6629> B_IWL<6628> B_IWL<6627> B_IWL<6626> B_IWL<6625> B_IWL<6624> B_IWL<6623> B_IWL<6622> B_IWL<6621> B_IWL<6620> B_IWL<6619> B_IWL<6618> B_IWL<6617> B_IWL<6616> B_IWL<6615> B_IWL<6614> B_IWL<6613> B_IWL<6612> B_IWL<6611> B_IWL<6610> B_IWL<6609> B_IWL<6608> B_IWL<6607> B_IWL<6606> B_IWL<6605> B_IWL<6604> B_IWL<6603> B_IWL<6602> B_IWL<6601> B_IWL<6600> B_IWL<6599> B_IWL<6598> B_IWL<6597> B_IWL<6596> B_IWL<6595> B_IWL<6594> B_IWL<6593> B_IWL<6592> B_IWL<6591> B_IWL<6590> B_IWL<6589> B_IWL<6588> B_IWL<6587> B_IWL<6586> B_IWL<6585> B_IWL<6584> B_IWL<6583> B_IWL<6582> B_IWL<6581> B_IWL<6580> B_IWL<6579> B_IWL<6578> B_IWL<6577> B_IWL<6576> B_IWL<6575> B_IWL<6574> B_IWL<6573> B_IWL<6572> B_IWL<6571> B_IWL<6570> B_IWL<6569> B_IWL<6568> B_IWL<6567> B_IWL<6566> B_IWL<6565> B_IWL<6564> B_IWL<6563> B_IWL<6562> B_IWL<6561> B_IWL<6560> B_IWL<6559> B_IWL<6558> B_IWL<6557> B_IWL<6556> B_IWL<6555> B_IWL<6554> B_IWL<6553> B_IWL<6552> B_IWL<6551> B_IWL<6550> B_IWL<6549> B_IWL<6548> B_IWL<6547> B_IWL<6546> B_IWL<6545> B_IWL<6544> B_IWL<6543> B_IWL<6542> B_IWL<6541> B_IWL<6540> B_IWL<6539> B_IWL<6538> B_IWL<6537> B_IWL<6536> B_IWL<6535> B_IWL<6534> B_IWL<6533> B_IWL<6532> B_IWL<6531> B_IWL<6530> B_IWL<6529> B_IWL<6528> B_IWL<6527> B_IWL<6526> B_IWL<6525> B_IWL<6524> B_IWL<6523> B_IWL<6522> B_IWL<6521> B_IWL<6520> B_IWL<6519> B_IWL<6518> B_IWL<6517> B_IWL<6516> B_IWL<6515> B_IWL<6514> B_IWL<6513> B_IWL<6512> B_IWL<6511> B_IWL<6510> B_IWL<6509> B_IWL<6508> B_IWL<6507> B_IWL<6506> B_IWL<6505> B_IWL<6504> B_IWL<6503> B_IWL<6502> B_IWL<6501> B_IWL<6500> B_IWL<6499> B_IWL<6498> B_IWL<6497> B_IWL<6496> B_IWL<6495> B_IWL<6494> B_IWL<6493> B_IWL<6492> B_IWL<6491> B_IWL<6490> B_IWL<6489> B_IWL<6488> B_IWL<6487> B_IWL<6486> B_IWL<6485> B_IWL<6484> B_IWL<6483> B_IWL<6482> B_IWL<6481> B_IWL<6480> B_IWL<6479> B_IWL<6478> B_IWL<6477> B_IWL<6476> B_IWL<6475> B_IWL<6474> B_IWL<6473> B_IWL<6472> B_IWL<6471> B_IWL<6470> B_IWL<6469> B_IWL<6468> B_IWL<6467> B_IWL<6466> B_IWL<6465> B_IWL<6464> B_IWL<6463> B_IWL<6462> B_IWL<6461> B_IWL<6460> B_IWL<6459> B_IWL<6458> B_IWL<6457> B_IWL<6456> B_IWL<6455> B_IWL<6454> B_IWL<6453> B_IWL<6452> B_IWL<6451> B_IWL<6450> B_IWL<6449> B_IWL<6448> B_IWL<6447> B_IWL<6446> B_IWL<6445> B_IWL<6444> B_IWL<6443> B_IWL<6442> B_IWL<6441> B_IWL<6440> B_IWL<6439> B_IWL<6438> B_IWL<6437> B_IWL<6436> B_IWL<6435> B_IWL<6434> B_IWL<6433> B_IWL<6432> B_IWL<6431> B_IWL<6430> B_IWL<6429> B_IWL<6428> B_IWL<6427> B_IWL<6426> B_IWL<6425> B_IWL<6424> B_IWL<6423> B_IWL<6422> B_IWL<6421> B_IWL<6420> B_IWL<6419> B_IWL<6418> B_IWL<6417> B_IWL<6416> B_IWL<6415> B_IWL<6414> B_IWL<6413> B_IWL<6412> B_IWL<6411> B_IWL<6410> B_IWL<6409> B_IWL<6408> B_IWL<6407> B_IWL<6406> B_IWL<6405> B_IWL<6404> B_IWL<6403> B_IWL<6402> B_IWL<6401> B_IWL<6400> VDD_CORE VSS / RM_IHPSG13_1024x32_c2_2P_COLUMN_pcell_0 +XCOL<24> A_BLC<49> A_BLC<48> A_BLC_TOP<49> A_BLC_TOP<48> A_BLT<49> A_BLT<48> A_BLT_TOP<49> A_BLT_TOP<48> A_IWL<6143> A_IWL<6142> A_IWL<6141> A_IWL<6140> A_IWL<6139> A_IWL<6138> A_IWL<6137> A_IWL<6136> A_IWL<6135> A_IWL<6134> A_IWL<6133> A_IWL<6132> A_IWL<6131> A_IWL<6130> A_IWL<6129> A_IWL<6128> A_IWL<6127> A_IWL<6126> A_IWL<6125> A_IWL<6124> A_IWL<6123> A_IWL<6122> A_IWL<6121> A_IWL<6120> A_IWL<6119> A_IWL<6118> A_IWL<6117> A_IWL<6116> A_IWL<6115> A_IWL<6114> A_IWL<6113> A_IWL<6112> A_IWL<6111> A_IWL<6110> A_IWL<6109> A_IWL<6108> A_IWL<6107> A_IWL<6106> A_IWL<6105> A_IWL<6104> A_IWL<6103> A_IWL<6102> A_IWL<6101> A_IWL<6100> A_IWL<6099> A_IWL<6098> A_IWL<6097> A_IWL<6096> A_IWL<6095> A_IWL<6094> A_IWL<6093> A_IWL<6092> A_IWL<6091> A_IWL<6090> A_IWL<6089> A_IWL<6088> A_IWL<6087> A_IWL<6086> A_IWL<6085> A_IWL<6084> A_IWL<6083> A_IWL<6082> A_IWL<6081> A_IWL<6080> A_IWL<6079> A_IWL<6078> A_IWL<6077> A_IWL<6076> A_IWL<6075> A_IWL<6074> A_IWL<6073> A_IWL<6072> A_IWL<6071> A_IWL<6070> A_IWL<6069> A_IWL<6068> A_IWL<6067> A_IWL<6066> A_IWL<6065> A_IWL<6064> A_IWL<6063> A_IWL<6062> A_IWL<6061> A_IWL<6060> A_IWL<6059> A_IWL<6058> A_IWL<6057> A_IWL<6056> A_IWL<6055> A_IWL<6054> A_IWL<6053> A_IWL<6052> A_IWL<6051> A_IWL<6050> A_IWL<6049> A_IWL<6048> A_IWL<6047> A_IWL<6046> A_IWL<6045> A_IWL<6044> A_IWL<6043> A_IWL<6042> A_IWL<6041> A_IWL<6040> A_IWL<6039> A_IWL<6038> A_IWL<6037> A_IWL<6036> A_IWL<6035> A_IWL<6034> A_IWL<6033> A_IWL<6032> A_IWL<6031> A_IWL<6030> A_IWL<6029> A_IWL<6028> A_IWL<6027> A_IWL<6026> A_IWL<6025> A_IWL<6024> A_IWL<6023> A_IWL<6022> A_IWL<6021> A_IWL<6020> A_IWL<6019> A_IWL<6018> A_IWL<6017> A_IWL<6016> A_IWL<6015> A_IWL<6014> A_IWL<6013> A_IWL<6012> A_IWL<6011> A_IWL<6010> A_IWL<6009> A_IWL<6008> A_IWL<6007> A_IWL<6006> A_IWL<6005> A_IWL<6004> A_IWL<6003> A_IWL<6002> A_IWL<6001> A_IWL<6000> A_IWL<5999> A_IWL<5998> A_IWL<5997> A_IWL<5996> A_IWL<5995> A_IWL<5994> A_IWL<5993> A_IWL<5992> A_IWL<5991> A_IWL<5990> A_IWL<5989> A_IWL<5988> A_IWL<5987> A_IWL<5986> A_IWL<5985> A_IWL<5984> A_IWL<5983> A_IWL<5982> A_IWL<5981> A_IWL<5980> A_IWL<5979> A_IWL<5978> A_IWL<5977> A_IWL<5976> A_IWL<5975> A_IWL<5974> A_IWL<5973> A_IWL<5972> A_IWL<5971> A_IWL<5970> A_IWL<5969> A_IWL<5968> A_IWL<5967> A_IWL<5966> A_IWL<5965> A_IWL<5964> A_IWL<5963> A_IWL<5962> A_IWL<5961> A_IWL<5960> A_IWL<5959> A_IWL<5958> A_IWL<5957> A_IWL<5956> A_IWL<5955> A_IWL<5954> A_IWL<5953> A_IWL<5952> A_IWL<5951> A_IWL<5950> A_IWL<5949> A_IWL<5948> A_IWL<5947> A_IWL<5946> A_IWL<5945> A_IWL<5944> A_IWL<5943> A_IWL<5942> A_IWL<5941> A_IWL<5940> A_IWL<5939> A_IWL<5938> A_IWL<5937> A_IWL<5936> A_IWL<5935> A_IWL<5934> A_IWL<5933> A_IWL<5932> A_IWL<5931> A_IWL<5930> A_IWL<5929> A_IWL<5928> A_IWL<5927> A_IWL<5926> A_IWL<5925> A_IWL<5924> A_IWL<5923> A_IWL<5922> A_IWL<5921> A_IWL<5920> A_IWL<5919> A_IWL<5918> A_IWL<5917> A_IWL<5916> A_IWL<5915> A_IWL<5914> A_IWL<5913> A_IWL<5912> A_IWL<5911> A_IWL<5910> A_IWL<5909> A_IWL<5908> A_IWL<5907> A_IWL<5906> A_IWL<5905> A_IWL<5904> A_IWL<5903> A_IWL<5902> A_IWL<5901> A_IWL<5900> A_IWL<5899> A_IWL<5898> A_IWL<5897> A_IWL<5896> A_IWL<5895> A_IWL<5894> A_IWL<5893> A_IWL<5892> A_IWL<5891> A_IWL<5890> A_IWL<5889> A_IWL<5888> A_IWL<6399> A_IWL<6398> A_IWL<6397> A_IWL<6396> A_IWL<6395> A_IWL<6394> A_IWL<6393> A_IWL<6392> A_IWL<6391> A_IWL<6390> A_IWL<6389> A_IWL<6388> A_IWL<6387> A_IWL<6386> A_IWL<6385> A_IWL<6384> A_IWL<6383> A_IWL<6382> A_IWL<6381> A_IWL<6380> A_IWL<6379> A_IWL<6378> A_IWL<6377> A_IWL<6376> A_IWL<6375> A_IWL<6374> A_IWL<6373> A_IWL<6372> A_IWL<6371> A_IWL<6370> A_IWL<6369> A_IWL<6368> A_IWL<6367> A_IWL<6366> A_IWL<6365> A_IWL<6364> A_IWL<6363> A_IWL<6362> A_IWL<6361> A_IWL<6360> A_IWL<6359> A_IWL<6358> A_IWL<6357> A_IWL<6356> A_IWL<6355> A_IWL<6354> A_IWL<6353> A_IWL<6352> A_IWL<6351> A_IWL<6350> A_IWL<6349> A_IWL<6348> A_IWL<6347> A_IWL<6346> A_IWL<6345> A_IWL<6344> A_IWL<6343> A_IWL<6342> A_IWL<6341> A_IWL<6340> A_IWL<6339> A_IWL<6338> A_IWL<6337> A_IWL<6336> A_IWL<6335> A_IWL<6334> A_IWL<6333> A_IWL<6332> A_IWL<6331> A_IWL<6330> A_IWL<6329> A_IWL<6328> A_IWL<6327> A_IWL<6326> A_IWL<6325> A_IWL<6324> A_IWL<6323> A_IWL<6322> A_IWL<6321> A_IWL<6320> A_IWL<6319> A_IWL<6318> A_IWL<6317> A_IWL<6316> A_IWL<6315> A_IWL<6314> A_IWL<6313> A_IWL<6312> A_IWL<6311> A_IWL<6310> A_IWL<6309> A_IWL<6308> A_IWL<6307> A_IWL<6306> A_IWL<6305> A_IWL<6304> A_IWL<6303> A_IWL<6302> A_IWL<6301> A_IWL<6300> A_IWL<6299> A_IWL<6298> A_IWL<6297> A_IWL<6296> A_IWL<6295> A_IWL<6294> A_IWL<6293> A_IWL<6292> A_IWL<6291> A_IWL<6290> A_IWL<6289> A_IWL<6288> A_IWL<6287> A_IWL<6286> A_IWL<6285> A_IWL<6284> A_IWL<6283> A_IWL<6282> A_IWL<6281> A_IWL<6280> A_IWL<6279> A_IWL<6278> A_IWL<6277> A_IWL<6276> A_IWL<6275> A_IWL<6274> A_IWL<6273> A_IWL<6272> A_IWL<6271> A_IWL<6270> A_IWL<6269> A_IWL<6268> A_IWL<6267> A_IWL<6266> A_IWL<6265> A_IWL<6264> A_IWL<6263> A_IWL<6262> A_IWL<6261> A_IWL<6260> A_IWL<6259> A_IWL<6258> A_IWL<6257> A_IWL<6256> A_IWL<6255> A_IWL<6254> A_IWL<6253> A_IWL<6252> A_IWL<6251> A_IWL<6250> A_IWL<6249> A_IWL<6248> A_IWL<6247> A_IWL<6246> A_IWL<6245> A_IWL<6244> A_IWL<6243> A_IWL<6242> A_IWL<6241> A_IWL<6240> A_IWL<6239> A_IWL<6238> A_IWL<6237> A_IWL<6236> A_IWL<6235> A_IWL<6234> A_IWL<6233> A_IWL<6232> A_IWL<6231> A_IWL<6230> A_IWL<6229> A_IWL<6228> A_IWL<6227> A_IWL<6226> A_IWL<6225> A_IWL<6224> A_IWL<6223> A_IWL<6222> A_IWL<6221> A_IWL<6220> A_IWL<6219> A_IWL<6218> A_IWL<6217> A_IWL<6216> A_IWL<6215> A_IWL<6214> A_IWL<6213> A_IWL<6212> A_IWL<6211> A_IWL<6210> A_IWL<6209> A_IWL<6208> A_IWL<6207> A_IWL<6206> A_IWL<6205> A_IWL<6204> A_IWL<6203> A_IWL<6202> A_IWL<6201> A_IWL<6200> A_IWL<6199> A_IWL<6198> A_IWL<6197> A_IWL<6196> A_IWL<6195> A_IWL<6194> A_IWL<6193> A_IWL<6192> A_IWL<6191> A_IWL<6190> A_IWL<6189> A_IWL<6188> A_IWL<6187> A_IWL<6186> A_IWL<6185> A_IWL<6184> A_IWL<6183> A_IWL<6182> A_IWL<6181> A_IWL<6180> A_IWL<6179> A_IWL<6178> A_IWL<6177> A_IWL<6176> A_IWL<6175> A_IWL<6174> A_IWL<6173> A_IWL<6172> A_IWL<6171> A_IWL<6170> A_IWL<6169> A_IWL<6168> A_IWL<6167> A_IWL<6166> A_IWL<6165> A_IWL<6164> A_IWL<6163> A_IWL<6162> A_IWL<6161> A_IWL<6160> A_IWL<6159> A_IWL<6158> A_IWL<6157> A_IWL<6156> A_IWL<6155> A_IWL<6154> A_IWL<6153> A_IWL<6152> A_IWL<6151> A_IWL<6150> A_IWL<6149> A_IWL<6148> A_IWL<6147> A_IWL<6146> A_IWL<6145> A_IWL<6144> B_BLC<49> B_BLC<48> B_BLC_TOP<49> B_BLC_TOP<48> B_BLT<49> B_BLT<48> B_BLT_TOP<49> B_BLT_TOP<48> B_IWL<6143> B_IWL<6142> B_IWL<6141> B_IWL<6140> B_IWL<6139> B_IWL<6138> B_IWL<6137> B_IWL<6136> B_IWL<6135> B_IWL<6134> B_IWL<6133> B_IWL<6132> B_IWL<6131> B_IWL<6130> B_IWL<6129> B_IWL<6128> B_IWL<6127> B_IWL<6126> B_IWL<6125> B_IWL<6124> B_IWL<6123> B_IWL<6122> B_IWL<6121> B_IWL<6120> B_IWL<6119> B_IWL<6118> B_IWL<6117> B_IWL<6116> B_IWL<6115> B_IWL<6114> B_IWL<6113> B_IWL<6112> B_IWL<6111> B_IWL<6110> B_IWL<6109> B_IWL<6108> B_IWL<6107> B_IWL<6106> B_IWL<6105> B_IWL<6104> B_IWL<6103> B_IWL<6102> B_IWL<6101> B_IWL<6100> B_IWL<6099> B_IWL<6098> B_IWL<6097> B_IWL<6096> B_IWL<6095> B_IWL<6094> B_IWL<6093> B_IWL<6092> B_IWL<6091> B_IWL<6090> B_IWL<6089> B_IWL<6088> B_IWL<6087> B_IWL<6086> B_IWL<6085> B_IWL<6084> B_IWL<6083> B_IWL<6082> B_IWL<6081> B_IWL<6080> B_IWL<6079> B_IWL<6078> B_IWL<6077> B_IWL<6076> B_IWL<6075> B_IWL<6074> B_IWL<6073> B_IWL<6072> B_IWL<6071> B_IWL<6070> B_IWL<6069> B_IWL<6068> B_IWL<6067> B_IWL<6066> B_IWL<6065> B_IWL<6064> B_IWL<6063> B_IWL<6062> B_IWL<6061> B_IWL<6060> B_IWL<6059> B_IWL<6058> B_IWL<6057> B_IWL<6056> B_IWL<6055> B_IWL<6054> B_IWL<6053> B_IWL<6052> B_IWL<6051> B_IWL<6050> B_IWL<6049> B_IWL<6048> B_IWL<6047> B_IWL<6046> B_IWL<6045> B_IWL<6044> B_IWL<6043> B_IWL<6042> B_IWL<6041> B_IWL<6040> B_IWL<6039> B_IWL<6038> B_IWL<6037> B_IWL<6036> B_IWL<6035> B_IWL<6034> B_IWL<6033> B_IWL<6032> B_IWL<6031> B_IWL<6030> B_IWL<6029> B_IWL<6028> B_IWL<6027> B_IWL<6026> B_IWL<6025> B_IWL<6024> B_IWL<6023> B_IWL<6022> B_IWL<6021> B_IWL<6020> B_IWL<6019> B_IWL<6018> B_IWL<6017> B_IWL<6016> B_IWL<6015> B_IWL<6014> B_IWL<6013> B_IWL<6012> B_IWL<6011> B_IWL<6010> B_IWL<6009> B_IWL<6008> B_IWL<6007> B_IWL<6006> B_IWL<6005> B_IWL<6004> B_IWL<6003> B_IWL<6002> B_IWL<6001> B_IWL<6000> B_IWL<5999> B_IWL<5998> B_IWL<5997> B_IWL<5996> B_IWL<5995> B_IWL<5994> B_IWL<5993> B_IWL<5992> B_IWL<5991> B_IWL<5990> B_IWL<5989> B_IWL<5988> B_IWL<5987> B_IWL<5986> B_IWL<5985> B_IWL<5984> B_IWL<5983> B_IWL<5982> B_IWL<5981> B_IWL<5980> B_IWL<5979> B_IWL<5978> B_IWL<5977> B_IWL<5976> B_IWL<5975> B_IWL<5974> B_IWL<5973> B_IWL<5972> B_IWL<5971> B_IWL<5970> B_IWL<5969> B_IWL<5968> B_IWL<5967> B_IWL<5966> B_IWL<5965> B_IWL<5964> B_IWL<5963> B_IWL<5962> B_IWL<5961> B_IWL<5960> B_IWL<5959> B_IWL<5958> B_IWL<5957> B_IWL<5956> B_IWL<5955> B_IWL<5954> B_IWL<5953> B_IWL<5952> B_IWL<5951> B_IWL<5950> B_IWL<5949> B_IWL<5948> B_IWL<5947> B_IWL<5946> B_IWL<5945> B_IWL<5944> B_IWL<5943> B_IWL<5942> B_IWL<5941> B_IWL<5940> B_IWL<5939> B_IWL<5938> B_IWL<5937> B_IWL<5936> B_IWL<5935> B_IWL<5934> B_IWL<5933> B_IWL<5932> B_IWL<5931> B_IWL<5930> B_IWL<5929> B_IWL<5928> B_IWL<5927> B_IWL<5926> B_IWL<5925> B_IWL<5924> B_IWL<5923> B_IWL<5922> B_IWL<5921> B_IWL<5920> B_IWL<5919> B_IWL<5918> B_IWL<5917> B_IWL<5916> B_IWL<5915> B_IWL<5914> B_IWL<5913> B_IWL<5912> B_IWL<5911> B_IWL<5910> B_IWL<5909> B_IWL<5908> B_IWL<5907> B_IWL<5906> B_IWL<5905> B_IWL<5904> B_IWL<5903> B_IWL<5902> B_IWL<5901> B_IWL<5900> B_IWL<5899> B_IWL<5898> B_IWL<5897> B_IWL<5896> B_IWL<5895> B_IWL<5894> B_IWL<5893> B_IWL<5892> B_IWL<5891> B_IWL<5890> B_IWL<5889> B_IWL<5888> B_IWL<6399> B_IWL<6398> B_IWL<6397> B_IWL<6396> B_IWL<6395> B_IWL<6394> B_IWL<6393> B_IWL<6392> B_IWL<6391> B_IWL<6390> B_IWL<6389> B_IWL<6388> B_IWL<6387> B_IWL<6386> B_IWL<6385> B_IWL<6384> B_IWL<6383> B_IWL<6382> B_IWL<6381> B_IWL<6380> B_IWL<6379> B_IWL<6378> B_IWL<6377> B_IWL<6376> B_IWL<6375> B_IWL<6374> B_IWL<6373> B_IWL<6372> B_IWL<6371> B_IWL<6370> B_IWL<6369> B_IWL<6368> B_IWL<6367> B_IWL<6366> B_IWL<6365> B_IWL<6364> B_IWL<6363> B_IWL<6362> B_IWL<6361> B_IWL<6360> B_IWL<6359> B_IWL<6358> B_IWL<6357> B_IWL<6356> B_IWL<6355> B_IWL<6354> B_IWL<6353> B_IWL<6352> B_IWL<6351> B_IWL<6350> B_IWL<6349> B_IWL<6348> B_IWL<6347> B_IWL<6346> B_IWL<6345> B_IWL<6344> B_IWL<6343> B_IWL<6342> B_IWL<6341> B_IWL<6340> B_IWL<6339> B_IWL<6338> B_IWL<6337> B_IWL<6336> B_IWL<6335> B_IWL<6334> B_IWL<6333> B_IWL<6332> B_IWL<6331> B_IWL<6330> B_IWL<6329> B_IWL<6328> B_IWL<6327> B_IWL<6326> B_IWL<6325> B_IWL<6324> B_IWL<6323> B_IWL<6322> B_IWL<6321> B_IWL<6320> B_IWL<6319> B_IWL<6318> B_IWL<6317> B_IWL<6316> B_IWL<6315> B_IWL<6314> B_IWL<6313> B_IWL<6312> B_IWL<6311> B_IWL<6310> B_IWL<6309> B_IWL<6308> B_IWL<6307> B_IWL<6306> B_IWL<6305> B_IWL<6304> B_IWL<6303> B_IWL<6302> B_IWL<6301> B_IWL<6300> B_IWL<6299> B_IWL<6298> B_IWL<6297> B_IWL<6296> B_IWL<6295> B_IWL<6294> B_IWL<6293> B_IWL<6292> B_IWL<6291> B_IWL<6290> B_IWL<6289> B_IWL<6288> B_IWL<6287> B_IWL<6286> B_IWL<6285> B_IWL<6284> B_IWL<6283> B_IWL<6282> B_IWL<6281> B_IWL<6280> B_IWL<6279> B_IWL<6278> B_IWL<6277> B_IWL<6276> B_IWL<6275> B_IWL<6274> B_IWL<6273> B_IWL<6272> B_IWL<6271> B_IWL<6270> B_IWL<6269> B_IWL<6268> B_IWL<6267> B_IWL<6266> B_IWL<6265> B_IWL<6264> B_IWL<6263> B_IWL<6262> B_IWL<6261> B_IWL<6260> B_IWL<6259> B_IWL<6258> B_IWL<6257> B_IWL<6256> B_IWL<6255> B_IWL<6254> B_IWL<6253> B_IWL<6252> B_IWL<6251> B_IWL<6250> B_IWL<6249> B_IWL<6248> B_IWL<6247> B_IWL<6246> B_IWL<6245> B_IWL<6244> B_IWL<6243> B_IWL<6242> B_IWL<6241> B_IWL<6240> B_IWL<6239> B_IWL<6238> B_IWL<6237> B_IWL<6236> B_IWL<6235> B_IWL<6234> B_IWL<6233> B_IWL<6232> B_IWL<6231> B_IWL<6230> B_IWL<6229> B_IWL<6228> B_IWL<6227> B_IWL<6226> B_IWL<6225> B_IWL<6224> B_IWL<6223> B_IWL<6222> B_IWL<6221> B_IWL<6220> B_IWL<6219> B_IWL<6218> B_IWL<6217> B_IWL<6216> B_IWL<6215> B_IWL<6214> B_IWL<6213> B_IWL<6212> B_IWL<6211> B_IWL<6210> B_IWL<6209> B_IWL<6208> B_IWL<6207> B_IWL<6206> B_IWL<6205> B_IWL<6204> B_IWL<6203> B_IWL<6202> B_IWL<6201> B_IWL<6200> B_IWL<6199> B_IWL<6198> B_IWL<6197> B_IWL<6196> B_IWL<6195> B_IWL<6194> B_IWL<6193> B_IWL<6192> B_IWL<6191> B_IWL<6190> B_IWL<6189> B_IWL<6188> B_IWL<6187> B_IWL<6186> B_IWL<6185> B_IWL<6184> B_IWL<6183> B_IWL<6182> B_IWL<6181> B_IWL<6180> B_IWL<6179> B_IWL<6178> B_IWL<6177> B_IWL<6176> B_IWL<6175> B_IWL<6174> B_IWL<6173> B_IWL<6172> B_IWL<6171> B_IWL<6170> B_IWL<6169> B_IWL<6168> B_IWL<6167> B_IWL<6166> B_IWL<6165> B_IWL<6164> B_IWL<6163> B_IWL<6162> B_IWL<6161> B_IWL<6160> B_IWL<6159> B_IWL<6158> B_IWL<6157> B_IWL<6156> B_IWL<6155> B_IWL<6154> B_IWL<6153> B_IWL<6152> B_IWL<6151> B_IWL<6150> B_IWL<6149> B_IWL<6148> B_IWL<6147> B_IWL<6146> B_IWL<6145> B_IWL<6144> VDD_CORE VSS / RM_IHPSG13_1024x32_c2_2P_COLUMN_pcell_0 +XCOL<23> A_BLC<47> A_BLC<46> A_BLC_TOP<47> A_BLC_TOP<46> A_BLT<47> A_BLT<46> A_BLT_TOP<47> A_BLT_TOP<46> A_IWL<5887> A_IWL<5886> A_IWL<5885> A_IWL<5884> A_IWL<5883> A_IWL<5882> A_IWL<5881> A_IWL<5880> A_IWL<5879> A_IWL<5878> A_IWL<5877> A_IWL<5876> A_IWL<5875> A_IWL<5874> A_IWL<5873> A_IWL<5872> A_IWL<5871> A_IWL<5870> A_IWL<5869> A_IWL<5868> A_IWL<5867> A_IWL<5866> A_IWL<5865> A_IWL<5864> A_IWL<5863> A_IWL<5862> A_IWL<5861> A_IWL<5860> A_IWL<5859> A_IWL<5858> A_IWL<5857> A_IWL<5856> A_IWL<5855> A_IWL<5854> A_IWL<5853> A_IWL<5852> A_IWL<5851> A_IWL<5850> A_IWL<5849> A_IWL<5848> A_IWL<5847> A_IWL<5846> A_IWL<5845> A_IWL<5844> A_IWL<5843> A_IWL<5842> A_IWL<5841> A_IWL<5840> A_IWL<5839> A_IWL<5838> A_IWL<5837> A_IWL<5836> A_IWL<5835> A_IWL<5834> A_IWL<5833> A_IWL<5832> A_IWL<5831> A_IWL<5830> A_IWL<5829> A_IWL<5828> A_IWL<5827> A_IWL<5826> A_IWL<5825> A_IWL<5824> A_IWL<5823> A_IWL<5822> A_IWL<5821> A_IWL<5820> A_IWL<5819> A_IWL<5818> A_IWL<5817> A_IWL<5816> A_IWL<5815> A_IWL<5814> A_IWL<5813> A_IWL<5812> A_IWL<5811> A_IWL<5810> A_IWL<5809> A_IWL<5808> A_IWL<5807> A_IWL<5806> A_IWL<5805> A_IWL<5804> A_IWL<5803> A_IWL<5802> A_IWL<5801> A_IWL<5800> A_IWL<5799> A_IWL<5798> A_IWL<5797> A_IWL<5796> A_IWL<5795> A_IWL<5794> A_IWL<5793> A_IWL<5792> A_IWL<5791> A_IWL<5790> A_IWL<5789> A_IWL<5788> A_IWL<5787> A_IWL<5786> A_IWL<5785> A_IWL<5784> A_IWL<5783> A_IWL<5782> A_IWL<5781> A_IWL<5780> A_IWL<5779> A_IWL<5778> A_IWL<5777> A_IWL<5776> A_IWL<5775> A_IWL<5774> A_IWL<5773> A_IWL<5772> A_IWL<5771> A_IWL<5770> A_IWL<5769> A_IWL<5768> A_IWL<5767> A_IWL<5766> A_IWL<5765> A_IWL<5764> A_IWL<5763> A_IWL<5762> A_IWL<5761> A_IWL<5760> A_IWL<5759> A_IWL<5758> A_IWL<5757> A_IWL<5756> A_IWL<5755> A_IWL<5754> A_IWL<5753> A_IWL<5752> A_IWL<5751> A_IWL<5750> A_IWL<5749> A_IWL<5748> A_IWL<5747> A_IWL<5746> A_IWL<5745> A_IWL<5744> A_IWL<5743> A_IWL<5742> A_IWL<5741> A_IWL<5740> A_IWL<5739> A_IWL<5738> A_IWL<5737> A_IWL<5736> A_IWL<5735> A_IWL<5734> A_IWL<5733> A_IWL<5732> A_IWL<5731> A_IWL<5730> A_IWL<5729> A_IWL<5728> A_IWL<5727> A_IWL<5726> A_IWL<5725> A_IWL<5724> A_IWL<5723> A_IWL<5722> A_IWL<5721> A_IWL<5720> A_IWL<5719> A_IWL<5718> A_IWL<5717> A_IWL<5716> A_IWL<5715> A_IWL<5714> A_IWL<5713> A_IWL<5712> A_IWL<5711> A_IWL<5710> A_IWL<5709> A_IWL<5708> A_IWL<5707> A_IWL<5706> A_IWL<5705> A_IWL<5704> A_IWL<5703> A_IWL<5702> A_IWL<5701> A_IWL<5700> A_IWL<5699> A_IWL<5698> A_IWL<5697> A_IWL<5696> A_IWL<5695> A_IWL<5694> A_IWL<5693> A_IWL<5692> A_IWL<5691> A_IWL<5690> A_IWL<5689> A_IWL<5688> A_IWL<5687> A_IWL<5686> A_IWL<5685> A_IWL<5684> A_IWL<5683> A_IWL<5682> A_IWL<5681> A_IWL<5680> A_IWL<5679> A_IWL<5678> A_IWL<5677> A_IWL<5676> A_IWL<5675> A_IWL<5674> A_IWL<5673> A_IWL<5672> A_IWL<5671> A_IWL<5670> A_IWL<5669> A_IWL<5668> A_IWL<5667> A_IWL<5666> A_IWL<5665> A_IWL<5664> A_IWL<5663> A_IWL<5662> A_IWL<5661> A_IWL<5660> A_IWL<5659> A_IWL<5658> A_IWL<5657> A_IWL<5656> A_IWL<5655> A_IWL<5654> A_IWL<5653> A_IWL<5652> A_IWL<5651> A_IWL<5650> A_IWL<5649> A_IWL<5648> A_IWL<5647> A_IWL<5646> A_IWL<5645> A_IWL<5644> A_IWL<5643> A_IWL<5642> A_IWL<5641> A_IWL<5640> A_IWL<5639> A_IWL<5638> A_IWL<5637> A_IWL<5636> A_IWL<5635> A_IWL<5634> A_IWL<5633> A_IWL<5632> A_IWL<6143> A_IWL<6142> A_IWL<6141> A_IWL<6140> A_IWL<6139> A_IWL<6138> A_IWL<6137> A_IWL<6136> A_IWL<6135> A_IWL<6134> A_IWL<6133> A_IWL<6132> A_IWL<6131> A_IWL<6130> A_IWL<6129> A_IWL<6128> A_IWL<6127> A_IWL<6126> A_IWL<6125> A_IWL<6124> A_IWL<6123> A_IWL<6122> A_IWL<6121> A_IWL<6120> A_IWL<6119> A_IWL<6118> A_IWL<6117> A_IWL<6116> A_IWL<6115> A_IWL<6114> A_IWL<6113> A_IWL<6112> A_IWL<6111> A_IWL<6110> A_IWL<6109> A_IWL<6108> A_IWL<6107> A_IWL<6106> A_IWL<6105> A_IWL<6104> A_IWL<6103> A_IWL<6102> A_IWL<6101> A_IWL<6100> A_IWL<6099> A_IWL<6098> A_IWL<6097> A_IWL<6096> A_IWL<6095> A_IWL<6094> A_IWL<6093> A_IWL<6092> A_IWL<6091> A_IWL<6090> A_IWL<6089> A_IWL<6088> A_IWL<6087> A_IWL<6086> A_IWL<6085> A_IWL<6084> A_IWL<6083> A_IWL<6082> A_IWL<6081> A_IWL<6080> A_IWL<6079> A_IWL<6078> A_IWL<6077> A_IWL<6076> A_IWL<6075> A_IWL<6074> A_IWL<6073> A_IWL<6072> A_IWL<6071> A_IWL<6070> A_IWL<6069> A_IWL<6068> A_IWL<6067> A_IWL<6066> A_IWL<6065> A_IWL<6064> A_IWL<6063> A_IWL<6062> A_IWL<6061> A_IWL<6060> A_IWL<6059> A_IWL<6058> A_IWL<6057> A_IWL<6056> A_IWL<6055> A_IWL<6054> A_IWL<6053> A_IWL<6052> A_IWL<6051> A_IWL<6050> A_IWL<6049> A_IWL<6048> A_IWL<6047> A_IWL<6046> A_IWL<6045> A_IWL<6044> A_IWL<6043> A_IWL<6042> A_IWL<6041> A_IWL<6040> A_IWL<6039> A_IWL<6038> A_IWL<6037> A_IWL<6036> A_IWL<6035> A_IWL<6034> A_IWL<6033> A_IWL<6032> A_IWL<6031> A_IWL<6030> A_IWL<6029> A_IWL<6028> A_IWL<6027> A_IWL<6026> A_IWL<6025> A_IWL<6024> A_IWL<6023> A_IWL<6022> A_IWL<6021> A_IWL<6020> A_IWL<6019> A_IWL<6018> A_IWL<6017> A_IWL<6016> A_IWL<6015> A_IWL<6014> A_IWL<6013> A_IWL<6012> A_IWL<6011> A_IWL<6010> A_IWL<6009> A_IWL<6008> A_IWL<6007> A_IWL<6006> A_IWL<6005> A_IWL<6004> A_IWL<6003> A_IWL<6002> A_IWL<6001> A_IWL<6000> A_IWL<5999> A_IWL<5998> A_IWL<5997> A_IWL<5996> A_IWL<5995> A_IWL<5994> A_IWL<5993> A_IWL<5992> A_IWL<5991> A_IWL<5990> A_IWL<5989> A_IWL<5988> A_IWL<5987> A_IWL<5986> A_IWL<5985> A_IWL<5984> A_IWL<5983> A_IWL<5982> A_IWL<5981> A_IWL<5980> A_IWL<5979> A_IWL<5978> A_IWL<5977> A_IWL<5976> A_IWL<5975> A_IWL<5974> A_IWL<5973> A_IWL<5972> A_IWL<5971> A_IWL<5970> A_IWL<5969> A_IWL<5968> A_IWL<5967> A_IWL<5966> A_IWL<5965> A_IWL<5964> A_IWL<5963> A_IWL<5962> A_IWL<5961> A_IWL<5960> A_IWL<5959> A_IWL<5958> A_IWL<5957> A_IWL<5956> A_IWL<5955> A_IWL<5954> A_IWL<5953> A_IWL<5952> A_IWL<5951> A_IWL<5950> A_IWL<5949> A_IWL<5948> A_IWL<5947> A_IWL<5946> A_IWL<5945> A_IWL<5944> A_IWL<5943> A_IWL<5942> A_IWL<5941> A_IWL<5940> A_IWL<5939> A_IWL<5938> A_IWL<5937> A_IWL<5936> A_IWL<5935> A_IWL<5934> A_IWL<5933> A_IWL<5932> A_IWL<5931> A_IWL<5930> A_IWL<5929> A_IWL<5928> A_IWL<5927> A_IWL<5926> A_IWL<5925> A_IWL<5924> A_IWL<5923> A_IWL<5922> A_IWL<5921> A_IWL<5920> A_IWL<5919> A_IWL<5918> A_IWL<5917> A_IWL<5916> A_IWL<5915> A_IWL<5914> A_IWL<5913> A_IWL<5912> A_IWL<5911> A_IWL<5910> A_IWL<5909> A_IWL<5908> A_IWL<5907> A_IWL<5906> A_IWL<5905> A_IWL<5904> A_IWL<5903> A_IWL<5902> A_IWL<5901> A_IWL<5900> A_IWL<5899> A_IWL<5898> A_IWL<5897> A_IWL<5896> A_IWL<5895> A_IWL<5894> A_IWL<5893> A_IWL<5892> A_IWL<5891> A_IWL<5890> A_IWL<5889> A_IWL<5888> B_BLC<47> B_BLC<46> B_BLC_TOP<47> B_BLC_TOP<46> B_BLT<47> B_BLT<46> B_BLT_TOP<47> B_BLT_TOP<46> B_IWL<5887> B_IWL<5886> B_IWL<5885> B_IWL<5884> B_IWL<5883> B_IWL<5882> B_IWL<5881> B_IWL<5880> B_IWL<5879> B_IWL<5878> B_IWL<5877> B_IWL<5876> B_IWL<5875> B_IWL<5874> B_IWL<5873> B_IWL<5872> B_IWL<5871> B_IWL<5870> B_IWL<5869> B_IWL<5868> B_IWL<5867> B_IWL<5866> B_IWL<5865> B_IWL<5864> B_IWL<5863> B_IWL<5862> B_IWL<5861> B_IWL<5860> B_IWL<5859> B_IWL<5858> B_IWL<5857> B_IWL<5856> B_IWL<5855> B_IWL<5854> B_IWL<5853> B_IWL<5852> B_IWL<5851> B_IWL<5850> B_IWL<5849> B_IWL<5848> B_IWL<5847> B_IWL<5846> B_IWL<5845> B_IWL<5844> B_IWL<5843> B_IWL<5842> B_IWL<5841> B_IWL<5840> B_IWL<5839> B_IWL<5838> B_IWL<5837> B_IWL<5836> B_IWL<5835> B_IWL<5834> B_IWL<5833> B_IWL<5832> B_IWL<5831> B_IWL<5830> B_IWL<5829> B_IWL<5828> B_IWL<5827> B_IWL<5826> B_IWL<5825> B_IWL<5824> B_IWL<5823> B_IWL<5822> B_IWL<5821> B_IWL<5820> B_IWL<5819> B_IWL<5818> B_IWL<5817> B_IWL<5816> B_IWL<5815> B_IWL<5814> B_IWL<5813> B_IWL<5812> B_IWL<5811> B_IWL<5810> B_IWL<5809> B_IWL<5808> B_IWL<5807> B_IWL<5806> B_IWL<5805> B_IWL<5804> B_IWL<5803> B_IWL<5802> B_IWL<5801> B_IWL<5800> B_IWL<5799> B_IWL<5798> B_IWL<5797> B_IWL<5796> B_IWL<5795> B_IWL<5794> B_IWL<5793> B_IWL<5792> B_IWL<5791> B_IWL<5790> B_IWL<5789> B_IWL<5788> B_IWL<5787> B_IWL<5786> B_IWL<5785> B_IWL<5784> B_IWL<5783> B_IWL<5782> B_IWL<5781> B_IWL<5780> B_IWL<5779> B_IWL<5778> B_IWL<5777> B_IWL<5776> B_IWL<5775> B_IWL<5774> B_IWL<5773> B_IWL<5772> B_IWL<5771> B_IWL<5770> B_IWL<5769> B_IWL<5768> B_IWL<5767> B_IWL<5766> B_IWL<5765> B_IWL<5764> B_IWL<5763> B_IWL<5762> B_IWL<5761> B_IWL<5760> B_IWL<5759> B_IWL<5758> B_IWL<5757> B_IWL<5756> B_IWL<5755> B_IWL<5754> B_IWL<5753> B_IWL<5752> B_IWL<5751> B_IWL<5750> B_IWL<5749> B_IWL<5748> B_IWL<5747> B_IWL<5746> B_IWL<5745> B_IWL<5744> B_IWL<5743> B_IWL<5742> B_IWL<5741> B_IWL<5740> B_IWL<5739> B_IWL<5738> B_IWL<5737> B_IWL<5736> B_IWL<5735> B_IWL<5734> B_IWL<5733> B_IWL<5732> B_IWL<5731> B_IWL<5730> B_IWL<5729> B_IWL<5728> B_IWL<5727> B_IWL<5726> B_IWL<5725> B_IWL<5724> B_IWL<5723> B_IWL<5722> B_IWL<5721> B_IWL<5720> B_IWL<5719> B_IWL<5718> B_IWL<5717> B_IWL<5716> B_IWL<5715> B_IWL<5714> B_IWL<5713> B_IWL<5712> B_IWL<5711> B_IWL<5710> B_IWL<5709> B_IWL<5708> B_IWL<5707> B_IWL<5706> B_IWL<5705> B_IWL<5704> B_IWL<5703> B_IWL<5702> B_IWL<5701> B_IWL<5700> B_IWL<5699> B_IWL<5698> B_IWL<5697> B_IWL<5696> B_IWL<5695> B_IWL<5694> B_IWL<5693> B_IWL<5692> B_IWL<5691> B_IWL<5690> B_IWL<5689> B_IWL<5688> B_IWL<5687> B_IWL<5686> B_IWL<5685> B_IWL<5684> B_IWL<5683> B_IWL<5682> B_IWL<5681> B_IWL<5680> B_IWL<5679> B_IWL<5678> B_IWL<5677> B_IWL<5676> B_IWL<5675> B_IWL<5674> B_IWL<5673> B_IWL<5672> B_IWL<5671> B_IWL<5670> B_IWL<5669> B_IWL<5668> B_IWL<5667> B_IWL<5666> B_IWL<5665> B_IWL<5664> B_IWL<5663> B_IWL<5662> B_IWL<5661> B_IWL<5660> B_IWL<5659> B_IWL<5658> B_IWL<5657> B_IWL<5656> B_IWL<5655> B_IWL<5654> B_IWL<5653> B_IWL<5652> B_IWL<5651> B_IWL<5650> B_IWL<5649> B_IWL<5648> B_IWL<5647> B_IWL<5646> B_IWL<5645> B_IWL<5644> B_IWL<5643> B_IWL<5642> B_IWL<5641> B_IWL<5640> B_IWL<5639> B_IWL<5638> B_IWL<5637> B_IWL<5636> B_IWL<5635> B_IWL<5634> B_IWL<5633> B_IWL<5632> B_IWL<6143> B_IWL<6142> B_IWL<6141> B_IWL<6140> B_IWL<6139> B_IWL<6138> B_IWL<6137> B_IWL<6136> B_IWL<6135> B_IWL<6134> B_IWL<6133> B_IWL<6132> B_IWL<6131> B_IWL<6130> B_IWL<6129> B_IWL<6128> B_IWL<6127> B_IWL<6126> B_IWL<6125> B_IWL<6124> B_IWL<6123> B_IWL<6122> B_IWL<6121> B_IWL<6120> B_IWL<6119> B_IWL<6118> B_IWL<6117> B_IWL<6116> B_IWL<6115> B_IWL<6114> B_IWL<6113> B_IWL<6112> B_IWL<6111> B_IWL<6110> B_IWL<6109> B_IWL<6108> B_IWL<6107> B_IWL<6106> B_IWL<6105> B_IWL<6104> B_IWL<6103> B_IWL<6102> B_IWL<6101> B_IWL<6100> B_IWL<6099> B_IWL<6098> B_IWL<6097> B_IWL<6096> B_IWL<6095> B_IWL<6094> B_IWL<6093> B_IWL<6092> B_IWL<6091> B_IWL<6090> B_IWL<6089> B_IWL<6088> B_IWL<6087> B_IWL<6086> B_IWL<6085> B_IWL<6084> B_IWL<6083> B_IWL<6082> B_IWL<6081> B_IWL<6080> B_IWL<6079> B_IWL<6078> B_IWL<6077> B_IWL<6076> B_IWL<6075> B_IWL<6074> B_IWL<6073> B_IWL<6072> B_IWL<6071> B_IWL<6070> B_IWL<6069> B_IWL<6068> B_IWL<6067> B_IWL<6066> B_IWL<6065> B_IWL<6064> B_IWL<6063> B_IWL<6062> B_IWL<6061> B_IWL<6060> B_IWL<6059> B_IWL<6058> B_IWL<6057> B_IWL<6056> B_IWL<6055> B_IWL<6054> B_IWL<6053> B_IWL<6052> B_IWL<6051> B_IWL<6050> B_IWL<6049> B_IWL<6048> B_IWL<6047> B_IWL<6046> B_IWL<6045> B_IWL<6044> B_IWL<6043> B_IWL<6042> B_IWL<6041> B_IWL<6040> B_IWL<6039> B_IWL<6038> B_IWL<6037> B_IWL<6036> B_IWL<6035> B_IWL<6034> B_IWL<6033> B_IWL<6032> B_IWL<6031> B_IWL<6030> B_IWL<6029> B_IWL<6028> B_IWL<6027> B_IWL<6026> B_IWL<6025> B_IWL<6024> B_IWL<6023> B_IWL<6022> B_IWL<6021> B_IWL<6020> B_IWL<6019> B_IWL<6018> B_IWL<6017> B_IWL<6016> B_IWL<6015> B_IWL<6014> B_IWL<6013> B_IWL<6012> B_IWL<6011> B_IWL<6010> B_IWL<6009> B_IWL<6008> B_IWL<6007> B_IWL<6006> B_IWL<6005> B_IWL<6004> B_IWL<6003> B_IWL<6002> B_IWL<6001> B_IWL<6000> B_IWL<5999> B_IWL<5998> B_IWL<5997> B_IWL<5996> B_IWL<5995> B_IWL<5994> B_IWL<5993> B_IWL<5992> B_IWL<5991> B_IWL<5990> B_IWL<5989> B_IWL<5988> B_IWL<5987> B_IWL<5986> B_IWL<5985> B_IWL<5984> B_IWL<5983> B_IWL<5982> B_IWL<5981> B_IWL<5980> B_IWL<5979> B_IWL<5978> B_IWL<5977> B_IWL<5976> B_IWL<5975> B_IWL<5974> B_IWL<5973> B_IWL<5972> B_IWL<5971> B_IWL<5970> B_IWL<5969> B_IWL<5968> B_IWL<5967> B_IWL<5966> B_IWL<5965> B_IWL<5964> B_IWL<5963> B_IWL<5962> B_IWL<5961> B_IWL<5960> B_IWL<5959> B_IWL<5958> B_IWL<5957> B_IWL<5956> B_IWL<5955> B_IWL<5954> B_IWL<5953> B_IWL<5952> B_IWL<5951> B_IWL<5950> B_IWL<5949> B_IWL<5948> B_IWL<5947> B_IWL<5946> B_IWL<5945> B_IWL<5944> B_IWL<5943> B_IWL<5942> B_IWL<5941> B_IWL<5940> B_IWL<5939> B_IWL<5938> B_IWL<5937> B_IWL<5936> B_IWL<5935> B_IWL<5934> B_IWL<5933> B_IWL<5932> B_IWL<5931> B_IWL<5930> B_IWL<5929> B_IWL<5928> B_IWL<5927> B_IWL<5926> B_IWL<5925> B_IWL<5924> B_IWL<5923> B_IWL<5922> B_IWL<5921> B_IWL<5920> B_IWL<5919> B_IWL<5918> B_IWL<5917> B_IWL<5916> B_IWL<5915> B_IWL<5914> B_IWL<5913> B_IWL<5912> B_IWL<5911> B_IWL<5910> B_IWL<5909> B_IWL<5908> B_IWL<5907> B_IWL<5906> B_IWL<5905> B_IWL<5904> B_IWL<5903> B_IWL<5902> B_IWL<5901> B_IWL<5900> B_IWL<5899> B_IWL<5898> B_IWL<5897> B_IWL<5896> B_IWL<5895> B_IWL<5894> B_IWL<5893> B_IWL<5892> B_IWL<5891> B_IWL<5890> B_IWL<5889> B_IWL<5888> VDD_CORE VSS / RM_IHPSG13_1024x32_c2_2P_COLUMN_pcell_0 +XCOL<22> A_BLC<45> A_BLC<44> A_BLC_TOP<45> A_BLC_TOP<44> A_BLT<45> A_BLT<44> A_BLT_TOP<45> A_BLT_TOP<44> A_IWL<5631> A_IWL<5630> A_IWL<5629> A_IWL<5628> A_IWL<5627> A_IWL<5626> A_IWL<5625> A_IWL<5624> A_IWL<5623> A_IWL<5622> A_IWL<5621> A_IWL<5620> A_IWL<5619> A_IWL<5618> A_IWL<5617> A_IWL<5616> A_IWL<5615> A_IWL<5614> A_IWL<5613> A_IWL<5612> A_IWL<5611> A_IWL<5610> A_IWL<5609> A_IWL<5608> A_IWL<5607> A_IWL<5606> A_IWL<5605> A_IWL<5604> A_IWL<5603> A_IWL<5602> A_IWL<5601> A_IWL<5600> A_IWL<5599> A_IWL<5598> A_IWL<5597> A_IWL<5596> A_IWL<5595> A_IWL<5594> A_IWL<5593> A_IWL<5592> A_IWL<5591> A_IWL<5590> A_IWL<5589> A_IWL<5588> A_IWL<5587> A_IWL<5586> A_IWL<5585> A_IWL<5584> A_IWL<5583> A_IWL<5582> A_IWL<5581> A_IWL<5580> A_IWL<5579> A_IWL<5578> A_IWL<5577> A_IWL<5576> A_IWL<5575> A_IWL<5574> A_IWL<5573> A_IWL<5572> A_IWL<5571> A_IWL<5570> A_IWL<5569> A_IWL<5568> A_IWL<5567> A_IWL<5566> A_IWL<5565> A_IWL<5564> A_IWL<5563> A_IWL<5562> A_IWL<5561> A_IWL<5560> A_IWL<5559> A_IWL<5558> A_IWL<5557> A_IWL<5556> A_IWL<5555> A_IWL<5554> A_IWL<5553> A_IWL<5552> A_IWL<5551> A_IWL<5550> A_IWL<5549> A_IWL<5548> A_IWL<5547> A_IWL<5546> A_IWL<5545> A_IWL<5544> A_IWL<5543> A_IWL<5542> A_IWL<5541> A_IWL<5540> A_IWL<5539> A_IWL<5538> A_IWL<5537> A_IWL<5536> A_IWL<5535> A_IWL<5534> A_IWL<5533> A_IWL<5532> A_IWL<5531> A_IWL<5530> A_IWL<5529> A_IWL<5528> A_IWL<5527> A_IWL<5526> A_IWL<5525> A_IWL<5524> A_IWL<5523> A_IWL<5522> A_IWL<5521> A_IWL<5520> A_IWL<5519> A_IWL<5518> A_IWL<5517> A_IWL<5516> A_IWL<5515> A_IWL<5514> A_IWL<5513> A_IWL<5512> A_IWL<5511> A_IWL<5510> A_IWL<5509> A_IWL<5508> A_IWL<5507> A_IWL<5506> A_IWL<5505> A_IWL<5504> A_IWL<5503> A_IWL<5502> A_IWL<5501> A_IWL<5500> A_IWL<5499> A_IWL<5498> A_IWL<5497> A_IWL<5496> A_IWL<5495> A_IWL<5494> A_IWL<5493> A_IWL<5492> A_IWL<5491> A_IWL<5490> A_IWL<5489> A_IWL<5488> A_IWL<5487> A_IWL<5486> A_IWL<5485> A_IWL<5484> A_IWL<5483> A_IWL<5482> A_IWL<5481> A_IWL<5480> A_IWL<5479> A_IWL<5478> A_IWL<5477> A_IWL<5476> A_IWL<5475> A_IWL<5474> A_IWL<5473> A_IWL<5472> A_IWL<5471> A_IWL<5470> A_IWL<5469> A_IWL<5468> A_IWL<5467> A_IWL<5466> A_IWL<5465> A_IWL<5464> A_IWL<5463> A_IWL<5462> A_IWL<5461> A_IWL<5460> A_IWL<5459> A_IWL<5458> A_IWL<5457> A_IWL<5456> A_IWL<5455> A_IWL<5454> A_IWL<5453> A_IWL<5452> A_IWL<5451> A_IWL<5450> A_IWL<5449> A_IWL<5448> A_IWL<5447> A_IWL<5446> A_IWL<5445> A_IWL<5444> A_IWL<5443> A_IWL<5442> A_IWL<5441> A_IWL<5440> A_IWL<5439> A_IWL<5438> A_IWL<5437> A_IWL<5436> A_IWL<5435> A_IWL<5434> A_IWL<5433> A_IWL<5432> A_IWL<5431> A_IWL<5430> A_IWL<5429> A_IWL<5428> A_IWL<5427> A_IWL<5426> A_IWL<5425> A_IWL<5424> A_IWL<5423> A_IWL<5422> A_IWL<5421> A_IWL<5420> A_IWL<5419> A_IWL<5418> A_IWL<5417> A_IWL<5416> A_IWL<5415> A_IWL<5414> A_IWL<5413> A_IWL<5412> A_IWL<5411> A_IWL<5410> A_IWL<5409> A_IWL<5408> A_IWL<5407> A_IWL<5406> A_IWL<5405> A_IWL<5404> A_IWL<5403> A_IWL<5402> A_IWL<5401> A_IWL<5400> A_IWL<5399> A_IWL<5398> A_IWL<5397> A_IWL<5396> A_IWL<5395> A_IWL<5394> A_IWL<5393> A_IWL<5392> A_IWL<5391> A_IWL<5390> A_IWL<5389> A_IWL<5388> A_IWL<5387> A_IWL<5386> A_IWL<5385> A_IWL<5384> A_IWL<5383> A_IWL<5382> A_IWL<5381> A_IWL<5380> A_IWL<5379> A_IWL<5378> A_IWL<5377> A_IWL<5376> A_IWL<5887> A_IWL<5886> A_IWL<5885> A_IWL<5884> A_IWL<5883> A_IWL<5882> A_IWL<5881> A_IWL<5880> A_IWL<5879> A_IWL<5878> A_IWL<5877> A_IWL<5876> A_IWL<5875> A_IWL<5874> A_IWL<5873> A_IWL<5872> A_IWL<5871> A_IWL<5870> A_IWL<5869> A_IWL<5868> A_IWL<5867> A_IWL<5866> A_IWL<5865> A_IWL<5864> A_IWL<5863> A_IWL<5862> A_IWL<5861> A_IWL<5860> A_IWL<5859> A_IWL<5858> A_IWL<5857> A_IWL<5856> A_IWL<5855> A_IWL<5854> A_IWL<5853> A_IWL<5852> A_IWL<5851> A_IWL<5850> A_IWL<5849> A_IWL<5848> A_IWL<5847> A_IWL<5846> A_IWL<5845> A_IWL<5844> A_IWL<5843> A_IWL<5842> A_IWL<5841> A_IWL<5840> A_IWL<5839> A_IWL<5838> A_IWL<5837> A_IWL<5836> A_IWL<5835> A_IWL<5834> A_IWL<5833> A_IWL<5832> A_IWL<5831> A_IWL<5830> A_IWL<5829> A_IWL<5828> A_IWL<5827> A_IWL<5826> A_IWL<5825> A_IWL<5824> A_IWL<5823> A_IWL<5822> A_IWL<5821> A_IWL<5820> A_IWL<5819> A_IWL<5818> A_IWL<5817> A_IWL<5816> A_IWL<5815> A_IWL<5814> A_IWL<5813> A_IWL<5812> A_IWL<5811> A_IWL<5810> A_IWL<5809> A_IWL<5808> A_IWL<5807> A_IWL<5806> A_IWL<5805> A_IWL<5804> A_IWL<5803> A_IWL<5802> A_IWL<5801> A_IWL<5800> A_IWL<5799> A_IWL<5798> A_IWL<5797> A_IWL<5796> A_IWL<5795> A_IWL<5794> A_IWL<5793> A_IWL<5792> A_IWL<5791> A_IWL<5790> A_IWL<5789> A_IWL<5788> A_IWL<5787> A_IWL<5786> A_IWL<5785> A_IWL<5784> A_IWL<5783> A_IWL<5782> A_IWL<5781> A_IWL<5780> A_IWL<5779> A_IWL<5778> A_IWL<5777> A_IWL<5776> A_IWL<5775> A_IWL<5774> A_IWL<5773> A_IWL<5772> A_IWL<5771> A_IWL<5770> A_IWL<5769> A_IWL<5768> A_IWL<5767> A_IWL<5766> A_IWL<5765> A_IWL<5764> A_IWL<5763> A_IWL<5762> A_IWL<5761> A_IWL<5760> A_IWL<5759> A_IWL<5758> A_IWL<5757> A_IWL<5756> A_IWL<5755> A_IWL<5754> A_IWL<5753> A_IWL<5752> A_IWL<5751> A_IWL<5750> A_IWL<5749> A_IWL<5748> A_IWL<5747> A_IWL<5746> A_IWL<5745> A_IWL<5744> A_IWL<5743> A_IWL<5742> A_IWL<5741> A_IWL<5740> A_IWL<5739> A_IWL<5738> A_IWL<5737> A_IWL<5736> A_IWL<5735> A_IWL<5734> A_IWL<5733> A_IWL<5732> A_IWL<5731> A_IWL<5730> A_IWL<5729> A_IWL<5728> A_IWL<5727> A_IWL<5726> A_IWL<5725> A_IWL<5724> A_IWL<5723> A_IWL<5722> A_IWL<5721> A_IWL<5720> A_IWL<5719> A_IWL<5718> A_IWL<5717> A_IWL<5716> A_IWL<5715> A_IWL<5714> A_IWL<5713> A_IWL<5712> A_IWL<5711> A_IWL<5710> A_IWL<5709> A_IWL<5708> A_IWL<5707> A_IWL<5706> A_IWL<5705> A_IWL<5704> A_IWL<5703> A_IWL<5702> A_IWL<5701> A_IWL<5700> A_IWL<5699> A_IWL<5698> A_IWL<5697> A_IWL<5696> A_IWL<5695> A_IWL<5694> A_IWL<5693> A_IWL<5692> A_IWL<5691> A_IWL<5690> A_IWL<5689> A_IWL<5688> A_IWL<5687> A_IWL<5686> A_IWL<5685> A_IWL<5684> A_IWL<5683> A_IWL<5682> A_IWL<5681> A_IWL<5680> A_IWL<5679> A_IWL<5678> A_IWL<5677> A_IWL<5676> A_IWL<5675> A_IWL<5674> A_IWL<5673> A_IWL<5672> A_IWL<5671> A_IWL<5670> A_IWL<5669> A_IWL<5668> A_IWL<5667> A_IWL<5666> A_IWL<5665> A_IWL<5664> A_IWL<5663> A_IWL<5662> A_IWL<5661> A_IWL<5660> A_IWL<5659> A_IWL<5658> A_IWL<5657> A_IWL<5656> A_IWL<5655> A_IWL<5654> A_IWL<5653> A_IWL<5652> A_IWL<5651> A_IWL<5650> A_IWL<5649> A_IWL<5648> A_IWL<5647> A_IWL<5646> A_IWL<5645> A_IWL<5644> A_IWL<5643> A_IWL<5642> A_IWL<5641> A_IWL<5640> A_IWL<5639> A_IWL<5638> A_IWL<5637> A_IWL<5636> A_IWL<5635> A_IWL<5634> A_IWL<5633> A_IWL<5632> B_BLC<45> B_BLC<44> B_BLC_TOP<45> B_BLC_TOP<44> B_BLT<45> B_BLT<44> B_BLT_TOP<45> B_BLT_TOP<44> B_IWL<5631> B_IWL<5630> B_IWL<5629> B_IWL<5628> B_IWL<5627> B_IWL<5626> B_IWL<5625> B_IWL<5624> B_IWL<5623> B_IWL<5622> B_IWL<5621> B_IWL<5620> B_IWL<5619> B_IWL<5618> B_IWL<5617> B_IWL<5616> B_IWL<5615> B_IWL<5614> B_IWL<5613> B_IWL<5612> B_IWL<5611> B_IWL<5610> B_IWL<5609> B_IWL<5608> B_IWL<5607> B_IWL<5606> B_IWL<5605> B_IWL<5604> B_IWL<5603> B_IWL<5602> B_IWL<5601> B_IWL<5600> B_IWL<5599> B_IWL<5598> B_IWL<5597> B_IWL<5596> B_IWL<5595> B_IWL<5594> B_IWL<5593> B_IWL<5592> B_IWL<5591> B_IWL<5590> B_IWL<5589> B_IWL<5588> B_IWL<5587> B_IWL<5586> B_IWL<5585> B_IWL<5584> B_IWL<5583> B_IWL<5582> B_IWL<5581> B_IWL<5580> B_IWL<5579> B_IWL<5578> B_IWL<5577> B_IWL<5576> B_IWL<5575> B_IWL<5574> B_IWL<5573> B_IWL<5572> B_IWL<5571> B_IWL<5570> B_IWL<5569> B_IWL<5568> B_IWL<5567> B_IWL<5566> B_IWL<5565> B_IWL<5564> B_IWL<5563> B_IWL<5562> B_IWL<5561> B_IWL<5560> B_IWL<5559> B_IWL<5558> B_IWL<5557> B_IWL<5556> B_IWL<5555> B_IWL<5554> B_IWL<5553> B_IWL<5552> B_IWL<5551> B_IWL<5550> B_IWL<5549> B_IWL<5548> B_IWL<5547> B_IWL<5546> B_IWL<5545> B_IWL<5544> B_IWL<5543> B_IWL<5542> B_IWL<5541> B_IWL<5540> B_IWL<5539> B_IWL<5538> B_IWL<5537> B_IWL<5536> B_IWL<5535> B_IWL<5534> B_IWL<5533> B_IWL<5532> B_IWL<5531> B_IWL<5530> B_IWL<5529> B_IWL<5528> B_IWL<5527> B_IWL<5526> B_IWL<5525> B_IWL<5524> B_IWL<5523> B_IWL<5522> B_IWL<5521> B_IWL<5520> B_IWL<5519> B_IWL<5518> B_IWL<5517> B_IWL<5516> B_IWL<5515> B_IWL<5514> B_IWL<5513> B_IWL<5512> B_IWL<5511> B_IWL<5510> B_IWL<5509> B_IWL<5508> B_IWL<5507> B_IWL<5506> B_IWL<5505> B_IWL<5504> B_IWL<5503> B_IWL<5502> B_IWL<5501> B_IWL<5500> B_IWL<5499> B_IWL<5498> B_IWL<5497> B_IWL<5496> B_IWL<5495> B_IWL<5494> B_IWL<5493> B_IWL<5492> B_IWL<5491> B_IWL<5490> B_IWL<5489> B_IWL<5488> B_IWL<5487> B_IWL<5486> B_IWL<5485> B_IWL<5484> B_IWL<5483> B_IWL<5482> B_IWL<5481> B_IWL<5480> B_IWL<5479> B_IWL<5478> B_IWL<5477> B_IWL<5476> B_IWL<5475> B_IWL<5474> B_IWL<5473> B_IWL<5472> B_IWL<5471> B_IWL<5470> B_IWL<5469> B_IWL<5468> B_IWL<5467> B_IWL<5466> B_IWL<5465> B_IWL<5464> B_IWL<5463> B_IWL<5462> B_IWL<5461> B_IWL<5460> B_IWL<5459> B_IWL<5458> B_IWL<5457> B_IWL<5456> B_IWL<5455> B_IWL<5454> B_IWL<5453> B_IWL<5452> B_IWL<5451> B_IWL<5450> B_IWL<5449> B_IWL<5448> B_IWL<5447> B_IWL<5446> B_IWL<5445> B_IWL<5444> B_IWL<5443> B_IWL<5442> B_IWL<5441> B_IWL<5440> B_IWL<5439> B_IWL<5438> B_IWL<5437> B_IWL<5436> B_IWL<5435> B_IWL<5434> B_IWL<5433> B_IWL<5432> B_IWL<5431> B_IWL<5430> B_IWL<5429> B_IWL<5428> B_IWL<5427> B_IWL<5426> B_IWL<5425> B_IWL<5424> B_IWL<5423> B_IWL<5422> B_IWL<5421> B_IWL<5420> B_IWL<5419> B_IWL<5418> B_IWL<5417> B_IWL<5416> B_IWL<5415> B_IWL<5414> B_IWL<5413> B_IWL<5412> B_IWL<5411> B_IWL<5410> B_IWL<5409> B_IWL<5408> B_IWL<5407> B_IWL<5406> B_IWL<5405> B_IWL<5404> B_IWL<5403> B_IWL<5402> B_IWL<5401> B_IWL<5400> B_IWL<5399> B_IWL<5398> B_IWL<5397> B_IWL<5396> B_IWL<5395> B_IWL<5394> B_IWL<5393> B_IWL<5392> B_IWL<5391> B_IWL<5390> B_IWL<5389> B_IWL<5388> B_IWL<5387> B_IWL<5386> B_IWL<5385> B_IWL<5384> B_IWL<5383> B_IWL<5382> B_IWL<5381> B_IWL<5380> B_IWL<5379> B_IWL<5378> B_IWL<5377> B_IWL<5376> B_IWL<5887> B_IWL<5886> B_IWL<5885> B_IWL<5884> B_IWL<5883> B_IWL<5882> B_IWL<5881> B_IWL<5880> B_IWL<5879> B_IWL<5878> B_IWL<5877> B_IWL<5876> B_IWL<5875> B_IWL<5874> B_IWL<5873> B_IWL<5872> B_IWL<5871> B_IWL<5870> B_IWL<5869> B_IWL<5868> B_IWL<5867> B_IWL<5866> B_IWL<5865> B_IWL<5864> B_IWL<5863> B_IWL<5862> B_IWL<5861> B_IWL<5860> B_IWL<5859> B_IWL<5858> B_IWL<5857> B_IWL<5856> B_IWL<5855> B_IWL<5854> B_IWL<5853> B_IWL<5852> B_IWL<5851> B_IWL<5850> B_IWL<5849> B_IWL<5848> B_IWL<5847> B_IWL<5846> B_IWL<5845> B_IWL<5844> B_IWL<5843> B_IWL<5842> B_IWL<5841> B_IWL<5840> B_IWL<5839> B_IWL<5838> B_IWL<5837> B_IWL<5836> B_IWL<5835> B_IWL<5834> B_IWL<5833> B_IWL<5832> B_IWL<5831> B_IWL<5830> B_IWL<5829> B_IWL<5828> B_IWL<5827> B_IWL<5826> B_IWL<5825> B_IWL<5824> B_IWL<5823> B_IWL<5822> B_IWL<5821> B_IWL<5820> B_IWL<5819> B_IWL<5818> B_IWL<5817> B_IWL<5816> B_IWL<5815> B_IWL<5814> B_IWL<5813> B_IWL<5812> B_IWL<5811> B_IWL<5810> B_IWL<5809> B_IWL<5808> B_IWL<5807> B_IWL<5806> B_IWL<5805> B_IWL<5804> B_IWL<5803> B_IWL<5802> B_IWL<5801> B_IWL<5800> B_IWL<5799> B_IWL<5798> B_IWL<5797> B_IWL<5796> B_IWL<5795> B_IWL<5794> B_IWL<5793> B_IWL<5792> B_IWL<5791> B_IWL<5790> B_IWL<5789> B_IWL<5788> B_IWL<5787> B_IWL<5786> B_IWL<5785> B_IWL<5784> B_IWL<5783> B_IWL<5782> B_IWL<5781> B_IWL<5780> B_IWL<5779> B_IWL<5778> B_IWL<5777> B_IWL<5776> B_IWL<5775> B_IWL<5774> B_IWL<5773> B_IWL<5772> B_IWL<5771> B_IWL<5770> B_IWL<5769> B_IWL<5768> B_IWL<5767> B_IWL<5766> B_IWL<5765> B_IWL<5764> B_IWL<5763> B_IWL<5762> B_IWL<5761> B_IWL<5760> B_IWL<5759> B_IWL<5758> B_IWL<5757> B_IWL<5756> B_IWL<5755> B_IWL<5754> B_IWL<5753> B_IWL<5752> B_IWL<5751> B_IWL<5750> B_IWL<5749> B_IWL<5748> B_IWL<5747> B_IWL<5746> B_IWL<5745> B_IWL<5744> B_IWL<5743> B_IWL<5742> B_IWL<5741> B_IWL<5740> B_IWL<5739> B_IWL<5738> B_IWL<5737> B_IWL<5736> B_IWL<5735> B_IWL<5734> B_IWL<5733> B_IWL<5732> B_IWL<5731> B_IWL<5730> B_IWL<5729> B_IWL<5728> B_IWL<5727> B_IWL<5726> B_IWL<5725> B_IWL<5724> B_IWL<5723> B_IWL<5722> B_IWL<5721> B_IWL<5720> B_IWL<5719> B_IWL<5718> B_IWL<5717> B_IWL<5716> B_IWL<5715> B_IWL<5714> B_IWL<5713> B_IWL<5712> B_IWL<5711> B_IWL<5710> B_IWL<5709> B_IWL<5708> B_IWL<5707> B_IWL<5706> B_IWL<5705> B_IWL<5704> B_IWL<5703> B_IWL<5702> B_IWL<5701> B_IWL<5700> B_IWL<5699> B_IWL<5698> B_IWL<5697> B_IWL<5696> B_IWL<5695> B_IWL<5694> B_IWL<5693> B_IWL<5692> B_IWL<5691> B_IWL<5690> B_IWL<5689> B_IWL<5688> B_IWL<5687> B_IWL<5686> B_IWL<5685> B_IWL<5684> B_IWL<5683> B_IWL<5682> B_IWL<5681> B_IWL<5680> B_IWL<5679> B_IWL<5678> B_IWL<5677> B_IWL<5676> B_IWL<5675> B_IWL<5674> B_IWL<5673> B_IWL<5672> B_IWL<5671> B_IWL<5670> B_IWL<5669> B_IWL<5668> B_IWL<5667> B_IWL<5666> B_IWL<5665> B_IWL<5664> B_IWL<5663> B_IWL<5662> B_IWL<5661> B_IWL<5660> B_IWL<5659> B_IWL<5658> B_IWL<5657> B_IWL<5656> B_IWL<5655> B_IWL<5654> B_IWL<5653> B_IWL<5652> B_IWL<5651> B_IWL<5650> B_IWL<5649> B_IWL<5648> B_IWL<5647> B_IWL<5646> B_IWL<5645> B_IWL<5644> B_IWL<5643> B_IWL<5642> B_IWL<5641> B_IWL<5640> B_IWL<5639> B_IWL<5638> B_IWL<5637> B_IWL<5636> B_IWL<5635> B_IWL<5634> B_IWL<5633> B_IWL<5632> VDD_CORE VSS / RM_IHPSG13_1024x32_c2_2P_COLUMN_pcell_0 +XCOL<21> A_BLC<43> A_BLC<42> A_BLC_TOP<43> A_BLC_TOP<42> A_BLT<43> A_BLT<42> A_BLT_TOP<43> A_BLT_TOP<42> A_IWL<5375> A_IWL<5374> A_IWL<5373> A_IWL<5372> A_IWL<5371> A_IWL<5370> A_IWL<5369> A_IWL<5368> A_IWL<5367> A_IWL<5366> A_IWL<5365> A_IWL<5364> A_IWL<5363> A_IWL<5362> A_IWL<5361> A_IWL<5360> A_IWL<5359> A_IWL<5358> A_IWL<5357> A_IWL<5356> A_IWL<5355> A_IWL<5354> A_IWL<5353> A_IWL<5352> A_IWL<5351> A_IWL<5350> A_IWL<5349> A_IWL<5348> A_IWL<5347> A_IWL<5346> A_IWL<5345> A_IWL<5344> A_IWL<5343> A_IWL<5342> A_IWL<5341> A_IWL<5340> A_IWL<5339> A_IWL<5338> A_IWL<5337> A_IWL<5336> A_IWL<5335> A_IWL<5334> A_IWL<5333> A_IWL<5332> A_IWL<5331> A_IWL<5330> A_IWL<5329> A_IWL<5328> A_IWL<5327> A_IWL<5326> A_IWL<5325> A_IWL<5324> A_IWL<5323> A_IWL<5322> A_IWL<5321> A_IWL<5320> A_IWL<5319> A_IWL<5318> A_IWL<5317> A_IWL<5316> A_IWL<5315> A_IWL<5314> A_IWL<5313> A_IWL<5312> A_IWL<5311> A_IWL<5310> A_IWL<5309> A_IWL<5308> A_IWL<5307> A_IWL<5306> A_IWL<5305> A_IWL<5304> A_IWL<5303> A_IWL<5302> A_IWL<5301> A_IWL<5300> A_IWL<5299> A_IWL<5298> A_IWL<5297> A_IWL<5296> A_IWL<5295> A_IWL<5294> A_IWL<5293> A_IWL<5292> A_IWL<5291> A_IWL<5290> A_IWL<5289> A_IWL<5288> A_IWL<5287> A_IWL<5286> A_IWL<5285> A_IWL<5284> A_IWL<5283> A_IWL<5282> A_IWL<5281> A_IWL<5280> A_IWL<5279> A_IWL<5278> A_IWL<5277> A_IWL<5276> A_IWL<5275> A_IWL<5274> A_IWL<5273> A_IWL<5272> A_IWL<5271> A_IWL<5270> A_IWL<5269> A_IWL<5268> A_IWL<5267> A_IWL<5266> A_IWL<5265> A_IWL<5264> A_IWL<5263> A_IWL<5262> A_IWL<5261> A_IWL<5260> A_IWL<5259> A_IWL<5258> A_IWL<5257> A_IWL<5256> A_IWL<5255> A_IWL<5254> A_IWL<5253> A_IWL<5252> A_IWL<5251> A_IWL<5250> A_IWL<5249> A_IWL<5248> A_IWL<5247> A_IWL<5246> A_IWL<5245> A_IWL<5244> A_IWL<5243> A_IWL<5242> A_IWL<5241> A_IWL<5240> A_IWL<5239> A_IWL<5238> A_IWL<5237> A_IWL<5236> A_IWL<5235> A_IWL<5234> A_IWL<5233> A_IWL<5232> A_IWL<5231> A_IWL<5230> A_IWL<5229> A_IWL<5228> A_IWL<5227> A_IWL<5226> A_IWL<5225> A_IWL<5224> A_IWL<5223> A_IWL<5222> A_IWL<5221> A_IWL<5220> A_IWL<5219> A_IWL<5218> A_IWL<5217> A_IWL<5216> A_IWL<5215> A_IWL<5214> A_IWL<5213> A_IWL<5212> A_IWL<5211> A_IWL<5210> A_IWL<5209> A_IWL<5208> A_IWL<5207> A_IWL<5206> A_IWL<5205> A_IWL<5204> A_IWL<5203> A_IWL<5202> A_IWL<5201> A_IWL<5200> A_IWL<5199> A_IWL<5198> A_IWL<5197> A_IWL<5196> A_IWL<5195> A_IWL<5194> A_IWL<5193> A_IWL<5192> A_IWL<5191> A_IWL<5190> A_IWL<5189> A_IWL<5188> A_IWL<5187> A_IWL<5186> A_IWL<5185> A_IWL<5184> A_IWL<5183> A_IWL<5182> A_IWL<5181> A_IWL<5180> A_IWL<5179> A_IWL<5178> A_IWL<5177> A_IWL<5176> A_IWL<5175> A_IWL<5174> A_IWL<5173> A_IWL<5172> A_IWL<5171> A_IWL<5170> A_IWL<5169> A_IWL<5168> A_IWL<5167> A_IWL<5166> A_IWL<5165> A_IWL<5164> A_IWL<5163> A_IWL<5162> A_IWL<5161> A_IWL<5160> A_IWL<5159> A_IWL<5158> A_IWL<5157> A_IWL<5156> A_IWL<5155> A_IWL<5154> A_IWL<5153> A_IWL<5152> A_IWL<5151> A_IWL<5150> A_IWL<5149> A_IWL<5148> A_IWL<5147> A_IWL<5146> A_IWL<5145> A_IWL<5144> A_IWL<5143> A_IWL<5142> A_IWL<5141> A_IWL<5140> A_IWL<5139> A_IWL<5138> A_IWL<5137> A_IWL<5136> A_IWL<5135> A_IWL<5134> A_IWL<5133> A_IWL<5132> A_IWL<5131> A_IWL<5130> A_IWL<5129> A_IWL<5128> A_IWL<5127> A_IWL<5126> A_IWL<5125> A_IWL<5124> A_IWL<5123> A_IWL<5122> A_IWL<5121> A_IWL<5120> A_IWL<5631> A_IWL<5630> A_IWL<5629> A_IWL<5628> A_IWL<5627> A_IWL<5626> A_IWL<5625> A_IWL<5624> A_IWL<5623> A_IWL<5622> A_IWL<5621> A_IWL<5620> A_IWL<5619> A_IWL<5618> A_IWL<5617> A_IWL<5616> A_IWL<5615> A_IWL<5614> A_IWL<5613> A_IWL<5612> A_IWL<5611> A_IWL<5610> A_IWL<5609> A_IWL<5608> A_IWL<5607> A_IWL<5606> A_IWL<5605> A_IWL<5604> A_IWL<5603> A_IWL<5602> A_IWL<5601> A_IWL<5600> A_IWL<5599> A_IWL<5598> A_IWL<5597> A_IWL<5596> A_IWL<5595> A_IWL<5594> A_IWL<5593> A_IWL<5592> A_IWL<5591> A_IWL<5590> A_IWL<5589> A_IWL<5588> A_IWL<5587> A_IWL<5586> A_IWL<5585> A_IWL<5584> A_IWL<5583> A_IWL<5582> A_IWL<5581> A_IWL<5580> A_IWL<5579> A_IWL<5578> A_IWL<5577> A_IWL<5576> A_IWL<5575> A_IWL<5574> A_IWL<5573> A_IWL<5572> A_IWL<5571> A_IWL<5570> A_IWL<5569> A_IWL<5568> A_IWL<5567> A_IWL<5566> A_IWL<5565> A_IWL<5564> A_IWL<5563> A_IWL<5562> A_IWL<5561> A_IWL<5560> A_IWL<5559> A_IWL<5558> A_IWL<5557> A_IWL<5556> A_IWL<5555> A_IWL<5554> A_IWL<5553> A_IWL<5552> A_IWL<5551> A_IWL<5550> A_IWL<5549> A_IWL<5548> A_IWL<5547> A_IWL<5546> A_IWL<5545> A_IWL<5544> A_IWL<5543> A_IWL<5542> A_IWL<5541> A_IWL<5540> A_IWL<5539> A_IWL<5538> A_IWL<5537> A_IWL<5536> A_IWL<5535> A_IWL<5534> A_IWL<5533> A_IWL<5532> A_IWL<5531> A_IWL<5530> A_IWL<5529> A_IWL<5528> A_IWL<5527> A_IWL<5526> A_IWL<5525> A_IWL<5524> A_IWL<5523> A_IWL<5522> A_IWL<5521> A_IWL<5520> A_IWL<5519> A_IWL<5518> A_IWL<5517> A_IWL<5516> A_IWL<5515> A_IWL<5514> A_IWL<5513> A_IWL<5512> A_IWL<5511> A_IWL<5510> A_IWL<5509> A_IWL<5508> A_IWL<5507> A_IWL<5506> A_IWL<5505> A_IWL<5504> A_IWL<5503> A_IWL<5502> A_IWL<5501> A_IWL<5500> A_IWL<5499> A_IWL<5498> A_IWL<5497> A_IWL<5496> A_IWL<5495> A_IWL<5494> A_IWL<5493> A_IWL<5492> A_IWL<5491> A_IWL<5490> A_IWL<5489> A_IWL<5488> A_IWL<5487> A_IWL<5486> A_IWL<5485> A_IWL<5484> A_IWL<5483> A_IWL<5482> A_IWL<5481> A_IWL<5480> A_IWL<5479> A_IWL<5478> A_IWL<5477> A_IWL<5476> A_IWL<5475> A_IWL<5474> A_IWL<5473> A_IWL<5472> A_IWL<5471> A_IWL<5470> A_IWL<5469> A_IWL<5468> A_IWL<5467> A_IWL<5466> A_IWL<5465> A_IWL<5464> A_IWL<5463> A_IWL<5462> A_IWL<5461> A_IWL<5460> A_IWL<5459> A_IWL<5458> A_IWL<5457> A_IWL<5456> A_IWL<5455> A_IWL<5454> A_IWL<5453> A_IWL<5452> A_IWL<5451> A_IWL<5450> A_IWL<5449> A_IWL<5448> A_IWL<5447> A_IWL<5446> A_IWL<5445> A_IWL<5444> A_IWL<5443> A_IWL<5442> A_IWL<5441> A_IWL<5440> A_IWL<5439> A_IWL<5438> A_IWL<5437> A_IWL<5436> A_IWL<5435> A_IWL<5434> A_IWL<5433> A_IWL<5432> A_IWL<5431> A_IWL<5430> A_IWL<5429> A_IWL<5428> A_IWL<5427> A_IWL<5426> A_IWL<5425> A_IWL<5424> A_IWL<5423> A_IWL<5422> A_IWL<5421> A_IWL<5420> A_IWL<5419> A_IWL<5418> A_IWL<5417> A_IWL<5416> A_IWL<5415> A_IWL<5414> A_IWL<5413> A_IWL<5412> A_IWL<5411> A_IWL<5410> A_IWL<5409> A_IWL<5408> A_IWL<5407> A_IWL<5406> A_IWL<5405> A_IWL<5404> A_IWL<5403> A_IWL<5402> A_IWL<5401> A_IWL<5400> A_IWL<5399> A_IWL<5398> A_IWL<5397> A_IWL<5396> A_IWL<5395> A_IWL<5394> A_IWL<5393> A_IWL<5392> A_IWL<5391> A_IWL<5390> A_IWL<5389> A_IWL<5388> A_IWL<5387> A_IWL<5386> A_IWL<5385> A_IWL<5384> A_IWL<5383> A_IWL<5382> A_IWL<5381> A_IWL<5380> A_IWL<5379> A_IWL<5378> A_IWL<5377> A_IWL<5376> B_BLC<43> B_BLC<42> B_BLC_TOP<43> B_BLC_TOP<42> B_BLT<43> B_BLT<42> B_BLT_TOP<43> B_BLT_TOP<42> B_IWL<5375> B_IWL<5374> B_IWL<5373> B_IWL<5372> B_IWL<5371> B_IWL<5370> B_IWL<5369> B_IWL<5368> B_IWL<5367> B_IWL<5366> B_IWL<5365> B_IWL<5364> B_IWL<5363> B_IWL<5362> B_IWL<5361> B_IWL<5360> B_IWL<5359> B_IWL<5358> B_IWL<5357> B_IWL<5356> B_IWL<5355> B_IWL<5354> B_IWL<5353> B_IWL<5352> B_IWL<5351> B_IWL<5350> B_IWL<5349> B_IWL<5348> B_IWL<5347> B_IWL<5346> B_IWL<5345> B_IWL<5344> B_IWL<5343> B_IWL<5342> B_IWL<5341> B_IWL<5340> B_IWL<5339> B_IWL<5338> B_IWL<5337> B_IWL<5336> B_IWL<5335> B_IWL<5334> B_IWL<5333> B_IWL<5332> B_IWL<5331> B_IWL<5330> B_IWL<5329> B_IWL<5328> B_IWL<5327> B_IWL<5326> B_IWL<5325> B_IWL<5324> B_IWL<5323> B_IWL<5322> B_IWL<5321> B_IWL<5320> B_IWL<5319> B_IWL<5318> B_IWL<5317> B_IWL<5316> B_IWL<5315> B_IWL<5314> B_IWL<5313> B_IWL<5312> B_IWL<5311> B_IWL<5310> B_IWL<5309> B_IWL<5308> B_IWL<5307> B_IWL<5306> B_IWL<5305> B_IWL<5304> B_IWL<5303> B_IWL<5302> B_IWL<5301> B_IWL<5300> B_IWL<5299> B_IWL<5298> B_IWL<5297> B_IWL<5296> B_IWL<5295> B_IWL<5294> B_IWL<5293> B_IWL<5292> B_IWL<5291> B_IWL<5290> B_IWL<5289> B_IWL<5288> B_IWL<5287> B_IWL<5286> B_IWL<5285> B_IWL<5284> B_IWL<5283> B_IWL<5282> B_IWL<5281> B_IWL<5280> B_IWL<5279> B_IWL<5278> B_IWL<5277> B_IWL<5276> B_IWL<5275> B_IWL<5274> B_IWL<5273> B_IWL<5272> B_IWL<5271> B_IWL<5270> B_IWL<5269> B_IWL<5268> B_IWL<5267> B_IWL<5266> B_IWL<5265> B_IWL<5264> B_IWL<5263> B_IWL<5262> B_IWL<5261> B_IWL<5260> B_IWL<5259> B_IWL<5258> B_IWL<5257> B_IWL<5256> B_IWL<5255> B_IWL<5254> B_IWL<5253> B_IWL<5252> B_IWL<5251> B_IWL<5250> B_IWL<5249> B_IWL<5248> B_IWL<5247> B_IWL<5246> B_IWL<5245> B_IWL<5244> B_IWL<5243> B_IWL<5242> B_IWL<5241> B_IWL<5240> B_IWL<5239> B_IWL<5238> B_IWL<5237> B_IWL<5236> B_IWL<5235> B_IWL<5234> B_IWL<5233> B_IWL<5232> B_IWL<5231> B_IWL<5230> B_IWL<5229> B_IWL<5228> B_IWL<5227> B_IWL<5226> B_IWL<5225> B_IWL<5224> B_IWL<5223> B_IWL<5222> B_IWL<5221> B_IWL<5220> B_IWL<5219> B_IWL<5218> B_IWL<5217> B_IWL<5216> B_IWL<5215> B_IWL<5214> B_IWL<5213> B_IWL<5212> B_IWL<5211> B_IWL<5210> B_IWL<5209> B_IWL<5208> B_IWL<5207> B_IWL<5206> B_IWL<5205> B_IWL<5204> B_IWL<5203> B_IWL<5202> B_IWL<5201> B_IWL<5200> B_IWL<5199> B_IWL<5198> B_IWL<5197> B_IWL<5196> B_IWL<5195> B_IWL<5194> B_IWL<5193> B_IWL<5192> B_IWL<5191> B_IWL<5190> B_IWL<5189> B_IWL<5188> B_IWL<5187> B_IWL<5186> B_IWL<5185> B_IWL<5184> B_IWL<5183> B_IWL<5182> B_IWL<5181> B_IWL<5180> B_IWL<5179> B_IWL<5178> B_IWL<5177> B_IWL<5176> B_IWL<5175> B_IWL<5174> B_IWL<5173> B_IWL<5172> B_IWL<5171> B_IWL<5170> B_IWL<5169> B_IWL<5168> B_IWL<5167> B_IWL<5166> B_IWL<5165> B_IWL<5164> B_IWL<5163> B_IWL<5162> B_IWL<5161> B_IWL<5160> B_IWL<5159> B_IWL<5158> B_IWL<5157> B_IWL<5156> B_IWL<5155> B_IWL<5154> B_IWL<5153> B_IWL<5152> B_IWL<5151> B_IWL<5150> B_IWL<5149> B_IWL<5148> B_IWL<5147> B_IWL<5146> B_IWL<5145> B_IWL<5144> B_IWL<5143> B_IWL<5142> B_IWL<5141> B_IWL<5140> B_IWL<5139> B_IWL<5138> B_IWL<5137> B_IWL<5136> B_IWL<5135> B_IWL<5134> B_IWL<5133> B_IWL<5132> B_IWL<5131> B_IWL<5130> B_IWL<5129> B_IWL<5128> B_IWL<5127> B_IWL<5126> B_IWL<5125> B_IWL<5124> B_IWL<5123> B_IWL<5122> B_IWL<5121> B_IWL<5120> B_IWL<5631> B_IWL<5630> B_IWL<5629> B_IWL<5628> B_IWL<5627> B_IWL<5626> B_IWL<5625> B_IWL<5624> B_IWL<5623> B_IWL<5622> B_IWL<5621> B_IWL<5620> B_IWL<5619> B_IWL<5618> B_IWL<5617> B_IWL<5616> B_IWL<5615> B_IWL<5614> B_IWL<5613> B_IWL<5612> B_IWL<5611> B_IWL<5610> B_IWL<5609> B_IWL<5608> B_IWL<5607> B_IWL<5606> B_IWL<5605> B_IWL<5604> B_IWL<5603> B_IWL<5602> B_IWL<5601> B_IWL<5600> B_IWL<5599> B_IWL<5598> B_IWL<5597> B_IWL<5596> B_IWL<5595> B_IWL<5594> B_IWL<5593> B_IWL<5592> B_IWL<5591> B_IWL<5590> B_IWL<5589> B_IWL<5588> B_IWL<5587> B_IWL<5586> B_IWL<5585> B_IWL<5584> B_IWL<5583> B_IWL<5582> B_IWL<5581> B_IWL<5580> B_IWL<5579> B_IWL<5578> B_IWL<5577> B_IWL<5576> B_IWL<5575> B_IWL<5574> B_IWL<5573> B_IWL<5572> B_IWL<5571> B_IWL<5570> B_IWL<5569> B_IWL<5568> B_IWL<5567> B_IWL<5566> B_IWL<5565> B_IWL<5564> B_IWL<5563> B_IWL<5562> B_IWL<5561> B_IWL<5560> B_IWL<5559> B_IWL<5558> B_IWL<5557> B_IWL<5556> B_IWL<5555> B_IWL<5554> B_IWL<5553> B_IWL<5552> B_IWL<5551> B_IWL<5550> B_IWL<5549> B_IWL<5548> B_IWL<5547> B_IWL<5546> B_IWL<5545> B_IWL<5544> B_IWL<5543> B_IWL<5542> B_IWL<5541> B_IWL<5540> B_IWL<5539> B_IWL<5538> B_IWL<5537> B_IWL<5536> B_IWL<5535> B_IWL<5534> B_IWL<5533> B_IWL<5532> B_IWL<5531> B_IWL<5530> B_IWL<5529> B_IWL<5528> B_IWL<5527> B_IWL<5526> B_IWL<5525> B_IWL<5524> B_IWL<5523> B_IWL<5522> B_IWL<5521> B_IWL<5520> B_IWL<5519> B_IWL<5518> B_IWL<5517> B_IWL<5516> B_IWL<5515> B_IWL<5514> B_IWL<5513> B_IWL<5512> B_IWL<5511> B_IWL<5510> B_IWL<5509> B_IWL<5508> B_IWL<5507> B_IWL<5506> B_IWL<5505> B_IWL<5504> B_IWL<5503> B_IWL<5502> B_IWL<5501> B_IWL<5500> B_IWL<5499> B_IWL<5498> B_IWL<5497> B_IWL<5496> B_IWL<5495> B_IWL<5494> B_IWL<5493> B_IWL<5492> B_IWL<5491> B_IWL<5490> B_IWL<5489> B_IWL<5488> B_IWL<5487> B_IWL<5486> B_IWL<5485> B_IWL<5484> B_IWL<5483> B_IWL<5482> B_IWL<5481> B_IWL<5480> B_IWL<5479> B_IWL<5478> B_IWL<5477> B_IWL<5476> B_IWL<5475> B_IWL<5474> B_IWL<5473> B_IWL<5472> B_IWL<5471> B_IWL<5470> B_IWL<5469> B_IWL<5468> B_IWL<5467> B_IWL<5466> B_IWL<5465> B_IWL<5464> B_IWL<5463> B_IWL<5462> B_IWL<5461> B_IWL<5460> B_IWL<5459> B_IWL<5458> B_IWL<5457> B_IWL<5456> B_IWL<5455> B_IWL<5454> B_IWL<5453> B_IWL<5452> B_IWL<5451> B_IWL<5450> B_IWL<5449> B_IWL<5448> B_IWL<5447> B_IWL<5446> B_IWL<5445> B_IWL<5444> B_IWL<5443> B_IWL<5442> B_IWL<5441> B_IWL<5440> B_IWL<5439> B_IWL<5438> B_IWL<5437> B_IWL<5436> B_IWL<5435> B_IWL<5434> B_IWL<5433> B_IWL<5432> B_IWL<5431> B_IWL<5430> B_IWL<5429> B_IWL<5428> B_IWL<5427> B_IWL<5426> B_IWL<5425> B_IWL<5424> B_IWL<5423> B_IWL<5422> B_IWL<5421> B_IWL<5420> B_IWL<5419> B_IWL<5418> B_IWL<5417> B_IWL<5416> B_IWL<5415> B_IWL<5414> B_IWL<5413> B_IWL<5412> B_IWL<5411> B_IWL<5410> B_IWL<5409> B_IWL<5408> B_IWL<5407> B_IWL<5406> B_IWL<5405> B_IWL<5404> B_IWL<5403> B_IWL<5402> B_IWL<5401> B_IWL<5400> B_IWL<5399> B_IWL<5398> B_IWL<5397> B_IWL<5396> B_IWL<5395> B_IWL<5394> B_IWL<5393> B_IWL<5392> B_IWL<5391> B_IWL<5390> B_IWL<5389> B_IWL<5388> B_IWL<5387> B_IWL<5386> B_IWL<5385> B_IWL<5384> B_IWL<5383> B_IWL<5382> B_IWL<5381> B_IWL<5380> B_IWL<5379> B_IWL<5378> B_IWL<5377> B_IWL<5376> VDD_CORE VSS / RM_IHPSG13_1024x32_c2_2P_COLUMN_pcell_0 +XCOL<20> A_BLC<41> A_BLC<40> A_BLC_TOP<41> A_BLC_TOP<40> A_BLT<41> A_BLT<40> A_BLT_TOP<41> A_BLT_TOP<40> A_IWL<5119> A_IWL<5118> A_IWL<5117> A_IWL<5116> A_IWL<5115> A_IWL<5114> A_IWL<5113> A_IWL<5112> A_IWL<5111> A_IWL<5110> A_IWL<5109> A_IWL<5108> A_IWL<5107> A_IWL<5106> A_IWL<5105> A_IWL<5104> A_IWL<5103> A_IWL<5102> A_IWL<5101> A_IWL<5100> A_IWL<5099> A_IWL<5098> A_IWL<5097> A_IWL<5096> A_IWL<5095> A_IWL<5094> A_IWL<5093> A_IWL<5092> A_IWL<5091> A_IWL<5090> A_IWL<5089> A_IWL<5088> A_IWL<5087> A_IWL<5086> A_IWL<5085> A_IWL<5084> A_IWL<5083> A_IWL<5082> A_IWL<5081> A_IWL<5080> A_IWL<5079> A_IWL<5078> A_IWL<5077> A_IWL<5076> A_IWL<5075> A_IWL<5074> A_IWL<5073> A_IWL<5072> A_IWL<5071> A_IWL<5070> A_IWL<5069> A_IWL<5068> A_IWL<5067> A_IWL<5066> A_IWL<5065> A_IWL<5064> A_IWL<5063> A_IWL<5062> A_IWL<5061> A_IWL<5060> A_IWL<5059> A_IWL<5058> A_IWL<5057> A_IWL<5056> A_IWL<5055> A_IWL<5054> A_IWL<5053> A_IWL<5052> A_IWL<5051> A_IWL<5050> A_IWL<5049> A_IWL<5048> A_IWL<5047> A_IWL<5046> A_IWL<5045> A_IWL<5044> A_IWL<5043> A_IWL<5042> A_IWL<5041> A_IWL<5040> A_IWL<5039> A_IWL<5038> A_IWL<5037> A_IWL<5036> A_IWL<5035> A_IWL<5034> A_IWL<5033> A_IWL<5032> A_IWL<5031> A_IWL<5030> A_IWL<5029> A_IWL<5028> A_IWL<5027> A_IWL<5026> A_IWL<5025> A_IWL<5024> A_IWL<5023> A_IWL<5022> A_IWL<5021> A_IWL<5020> A_IWL<5019> A_IWL<5018> A_IWL<5017> A_IWL<5016> A_IWL<5015> A_IWL<5014> A_IWL<5013> A_IWL<5012> A_IWL<5011> A_IWL<5010> A_IWL<5009> A_IWL<5008> A_IWL<5007> A_IWL<5006> A_IWL<5005> A_IWL<5004> A_IWL<5003> A_IWL<5002> A_IWL<5001> A_IWL<5000> A_IWL<4999> A_IWL<4998> A_IWL<4997> A_IWL<4996> A_IWL<4995> A_IWL<4994> A_IWL<4993> A_IWL<4992> A_IWL<4991> A_IWL<4990> A_IWL<4989> A_IWL<4988> A_IWL<4987> A_IWL<4986> A_IWL<4985> A_IWL<4984> A_IWL<4983> A_IWL<4982> A_IWL<4981> A_IWL<4980> A_IWL<4979> A_IWL<4978> A_IWL<4977> A_IWL<4976> A_IWL<4975> A_IWL<4974> A_IWL<4973> A_IWL<4972> A_IWL<4971> A_IWL<4970> A_IWL<4969> A_IWL<4968> A_IWL<4967> A_IWL<4966> A_IWL<4965> A_IWL<4964> A_IWL<4963> A_IWL<4962> A_IWL<4961> A_IWL<4960> A_IWL<4959> A_IWL<4958> A_IWL<4957> A_IWL<4956> A_IWL<4955> A_IWL<4954> A_IWL<4953> A_IWL<4952> A_IWL<4951> A_IWL<4950> A_IWL<4949> A_IWL<4948> A_IWL<4947> A_IWL<4946> A_IWL<4945> A_IWL<4944> A_IWL<4943> A_IWL<4942> A_IWL<4941> A_IWL<4940> A_IWL<4939> A_IWL<4938> A_IWL<4937> A_IWL<4936> A_IWL<4935> A_IWL<4934> A_IWL<4933> A_IWL<4932> A_IWL<4931> A_IWL<4930> A_IWL<4929> A_IWL<4928> A_IWL<4927> A_IWL<4926> A_IWL<4925> A_IWL<4924> A_IWL<4923> A_IWL<4922> A_IWL<4921> A_IWL<4920> A_IWL<4919> A_IWL<4918> A_IWL<4917> A_IWL<4916> A_IWL<4915> A_IWL<4914> A_IWL<4913> A_IWL<4912> A_IWL<4911> A_IWL<4910> A_IWL<4909> A_IWL<4908> A_IWL<4907> A_IWL<4906> A_IWL<4905> A_IWL<4904> A_IWL<4903> A_IWL<4902> A_IWL<4901> A_IWL<4900> A_IWL<4899> A_IWL<4898> A_IWL<4897> A_IWL<4896> A_IWL<4895> A_IWL<4894> A_IWL<4893> A_IWL<4892> A_IWL<4891> A_IWL<4890> A_IWL<4889> A_IWL<4888> A_IWL<4887> A_IWL<4886> A_IWL<4885> A_IWL<4884> A_IWL<4883> A_IWL<4882> A_IWL<4881> A_IWL<4880> A_IWL<4879> A_IWL<4878> A_IWL<4877> A_IWL<4876> A_IWL<4875> A_IWL<4874> A_IWL<4873> A_IWL<4872> A_IWL<4871> A_IWL<4870> A_IWL<4869> A_IWL<4868> A_IWL<4867> A_IWL<4866> A_IWL<4865> A_IWL<4864> A_IWL<5375> A_IWL<5374> A_IWL<5373> A_IWL<5372> A_IWL<5371> A_IWL<5370> A_IWL<5369> A_IWL<5368> A_IWL<5367> A_IWL<5366> A_IWL<5365> A_IWL<5364> A_IWL<5363> A_IWL<5362> A_IWL<5361> A_IWL<5360> A_IWL<5359> A_IWL<5358> A_IWL<5357> A_IWL<5356> A_IWL<5355> A_IWL<5354> A_IWL<5353> A_IWL<5352> A_IWL<5351> A_IWL<5350> A_IWL<5349> A_IWL<5348> A_IWL<5347> A_IWL<5346> A_IWL<5345> A_IWL<5344> A_IWL<5343> A_IWL<5342> A_IWL<5341> A_IWL<5340> A_IWL<5339> A_IWL<5338> A_IWL<5337> A_IWL<5336> A_IWL<5335> A_IWL<5334> A_IWL<5333> A_IWL<5332> A_IWL<5331> A_IWL<5330> A_IWL<5329> A_IWL<5328> A_IWL<5327> A_IWL<5326> A_IWL<5325> A_IWL<5324> A_IWL<5323> A_IWL<5322> A_IWL<5321> A_IWL<5320> A_IWL<5319> A_IWL<5318> A_IWL<5317> A_IWL<5316> A_IWL<5315> A_IWL<5314> A_IWL<5313> A_IWL<5312> A_IWL<5311> A_IWL<5310> A_IWL<5309> A_IWL<5308> A_IWL<5307> A_IWL<5306> A_IWL<5305> A_IWL<5304> A_IWL<5303> A_IWL<5302> A_IWL<5301> A_IWL<5300> A_IWL<5299> A_IWL<5298> A_IWL<5297> A_IWL<5296> A_IWL<5295> A_IWL<5294> A_IWL<5293> A_IWL<5292> A_IWL<5291> A_IWL<5290> A_IWL<5289> A_IWL<5288> A_IWL<5287> A_IWL<5286> A_IWL<5285> A_IWL<5284> A_IWL<5283> A_IWL<5282> A_IWL<5281> A_IWL<5280> A_IWL<5279> A_IWL<5278> A_IWL<5277> A_IWL<5276> A_IWL<5275> A_IWL<5274> A_IWL<5273> A_IWL<5272> A_IWL<5271> A_IWL<5270> A_IWL<5269> A_IWL<5268> A_IWL<5267> A_IWL<5266> A_IWL<5265> A_IWL<5264> A_IWL<5263> A_IWL<5262> A_IWL<5261> A_IWL<5260> A_IWL<5259> A_IWL<5258> A_IWL<5257> A_IWL<5256> A_IWL<5255> A_IWL<5254> A_IWL<5253> A_IWL<5252> A_IWL<5251> A_IWL<5250> A_IWL<5249> A_IWL<5248> A_IWL<5247> A_IWL<5246> A_IWL<5245> A_IWL<5244> A_IWL<5243> A_IWL<5242> A_IWL<5241> A_IWL<5240> A_IWL<5239> A_IWL<5238> A_IWL<5237> A_IWL<5236> A_IWL<5235> A_IWL<5234> A_IWL<5233> A_IWL<5232> A_IWL<5231> A_IWL<5230> A_IWL<5229> A_IWL<5228> A_IWL<5227> A_IWL<5226> A_IWL<5225> A_IWL<5224> A_IWL<5223> A_IWL<5222> A_IWL<5221> A_IWL<5220> A_IWL<5219> A_IWL<5218> A_IWL<5217> A_IWL<5216> A_IWL<5215> A_IWL<5214> A_IWL<5213> A_IWL<5212> A_IWL<5211> A_IWL<5210> A_IWL<5209> A_IWL<5208> A_IWL<5207> A_IWL<5206> A_IWL<5205> A_IWL<5204> A_IWL<5203> A_IWL<5202> A_IWL<5201> A_IWL<5200> A_IWL<5199> A_IWL<5198> A_IWL<5197> A_IWL<5196> A_IWL<5195> A_IWL<5194> A_IWL<5193> A_IWL<5192> A_IWL<5191> A_IWL<5190> A_IWL<5189> A_IWL<5188> A_IWL<5187> A_IWL<5186> A_IWL<5185> A_IWL<5184> A_IWL<5183> A_IWL<5182> A_IWL<5181> A_IWL<5180> A_IWL<5179> A_IWL<5178> A_IWL<5177> A_IWL<5176> A_IWL<5175> A_IWL<5174> A_IWL<5173> A_IWL<5172> A_IWL<5171> A_IWL<5170> A_IWL<5169> A_IWL<5168> A_IWL<5167> A_IWL<5166> A_IWL<5165> A_IWL<5164> A_IWL<5163> A_IWL<5162> A_IWL<5161> A_IWL<5160> A_IWL<5159> A_IWL<5158> A_IWL<5157> A_IWL<5156> A_IWL<5155> A_IWL<5154> A_IWL<5153> A_IWL<5152> A_IWL<5151> A_IWL<5150> A_IWL<5149> A_IWL<5148> A_IWL<5147> A_IWL<5146> A_IWL<5145> A_IWL<5144> A_IWL<5143> A_IWL<5142> A_IWL<5141> A_IWL<5140> A_IWL<5139> A_IWL<5138> A_IWL<5137> A_IWL<5136> A_IWL<5135> A_IWL<5134> A_IWL<5133> A_IWL<5132> A_IWL<5131> A_IWL<5130> A_IWL<5129> A_IWL<5128> A_IWL<5127> A_IWL<5126> A_IWL<5125> A_IWL<5124> A_IWL<5123> A_IWL<5122> A_IWL<5121> A_IWL<5120> B_BLC<41> B_BLC<40> B_BLC_TOP<41> B_BLC_TOP<40> B_BLT<41> B_BLT<40> B_BLT_TOP<41> B_BLT_TOP<40> B_IWL<5119> B_IWL<5118> B_IWL<5117> B_IWL<5116> B_IWL<5115> B_IWL<5114> B_IWL<5113> B_IWL<5112> B_IWL<5111> B_IWL<5110> B_IWL<5109> B_IWL<5108> B_IWL<5107> B_IWL<5106> B_IWL<5105> B_IWL<5104> B_IWL<5103> B_IWL<5102> B_IWL<5101> B_IWL<5100> B_IWL<5099> B_IWL<5098> B_IWL<5097> B_IWL<5096> B_IWL<5095> B_IWL<5094> B_IWL<5093> B_IWL<5092> B_IWL<5091> B_IWL<5090> B_IWL<5089> B_IWL<5088> B_IWL<5087> B_IWL<5086> B_IWL<5085> B_IWL<5084> B_IWL<5083> B_IWL<5082> B_IWL<5081> B_IWL<5080> B_IWL<5079> B_IWL<5078> B_IWL<5077> B_IWL<5076> B_IWL<5075> B_IWL<5074> B_IWL<5073> B_IWL<5072> B_IWL<5071> B_IWL<5070> B_IWL<5069> B_IWL<5068> B_IWL<5067> B_IWL<5066> B_IWL<5065> B_IWL<5064> B_IWL<5063> B_IWL<5062> B_IWL<5061> B_IWL<5060> B_IWL<5059> B_IWL<5058> B_IWL<5057> B_IWL<5056> B_IWL<5055> B_IWL<5054> B_IWL<5053> B_IWL<5052> B_IWL<5051> B_IWL<5050> B_IWL<5049> B_IWL<5048> B_IWL<5047> B_IWL<5046> B_IWL<5045> B_IWL<5044> B_IWL<5043> B_IWL<5042> B_IWL<5041> B_IWL<5040> B_IWL<5039> B_IWL<5038> B_IWL<5037> B_IWL<5036> B_IWL<5035> B_IWL<5034> B_IWL<5033> B_IWL<5032> B_IWL<5031> B_IWL<5030> B_IWL<5029> B_IWL<5028> B_IWL<5027> B_IWL<5026> B_IWL<5025> B_IWL<5024> B_IWL<5023> B_IWL<5022> B_IWL<5021> B_IWL<5020> B_IWL<5019> B_IWL<5018> B_IWL<5017> B_IWL<5016> B_IWL<5015> B_IWL<5014> B_IWL<5013> B_IWL<5012> B_IWL<5011> B_IWL<5010> B_IWL<5009> B_IWL<5008> B_IWL<5007> B_IWL<5006> B_IWL<5005> B_IWL<5004> B_IWL<5003> B_IWL<5002> B_IWL<5001> B_IWL<5000> B_IWL<4999> B_IWL<4998> B_IWL<4997> B_IWL<4996> B_IWL<4995> B_IWL<4994> B_IWL<4993> B_IWL<4992> B_IWL<4991> B_IWL<4990> B_IWL<4989> B_IWL<4988> B_IWL<4987> B_IWL<4986> B_IWL<4985> B_IWL<4984> B_IWL<4983> B_IWL<4982> B_IWL<4981> B_IWL<4980> B_IWL<4979> B_IWL<4978> B_IWL<4977> B_IWL<4976> B_IWL<4975> B_IWL<4974> B_IWL<4973> B_IWL<4972> B_IWL<4971> B_IWL<4970> B_IWL<4969> B_IWL<4968> B_IWL<4967> B_IWL<4966> B_IWL<4965> B_IWL<4964> B_IWL<4963> B_IWL<4962> B_IWL<4961> B_IWL<4960> B_IWL<4959> B_IWL<4958> B_IWL<4957> B_IWL<4956> B_IWL<4955> B_IWL<4954> B_IWL<4953> B_IWL<4952> B_IWL<4951> B_IWL<4950> B_IWL<4949> B_IWL<4948> B_IWL<4947> B_IWL<4946> B_IWL<4945> B_IWL<4944> B_IWL<4943> B_IWL<4942> B_IWL<4941> B_IWL<4940> B_IWL<4939> B_IWL<4938> B_IWL<4937> B_IWL<4936> B_IWL<4935> B_IWL<4934> B_IWL<4933> B_IWL<4932> B_IWL<4931> B_IWL<4930> B_IWL<4929> B_IWL<4928> B_IWL<4927> B_IWL<4926> B_IWL<4925> B_IWL<4924> B_IWL<4923> B_IWL<4922> B_IWL<4921> B_IWL<4920> B_IWL<4919> B_IWL<4918> B_IWL<4917> B_IWL<4916> B_IWL<4915> B_IWL<4914> B_IWL<4913> B_IWL<4912> B_IWL<4911> B_IWL<4910> B_IWL<4909> B_IWL<4908> B_IWL<4907> B_IWL<4906> B_IWL<4905> B_IWL<4904> B_IWL<4903> B_IWL<4902> B_IWL<4901> B_IWL<4900> B_IWL<4899> B_IWL<4898> B_IWL<4897> B_IWL<4896> B_IWL<4895> B_IWL<4894> B_IWL<4893> B_IWL<4892> B_IWL<4891> B_IWL<4890> B_IWL<4889> B_IWL<4888> B_IWL<4887> B_IWL<4886> B_IWL<4885> B_IWL<4884> B_IWL<4883> B_IWL<4882> B_IWL<4881> B_IWL<4880> B_IWL<4879> B_IWL<4878> B_IWL<4877> B_IWL<4876> B_IWL<4875> B_IWL<4874> B_IWL<4873> B_IWL<4872> B_IWL<4871> B_IWL<4870> B_IWL<4869> B_IWL<4868> B_IWL<4867> B_IWL<4866> B_IWL<4865> B_IWL<4864> B_IWL<5375> B_IWL<5374> B_IWL<5373> B_IWL<5372> B_IWL<5371> B_IWL<5370> B_IWL<5369> B_IWL<5368> B_IWL<5367> B_IWL<5366> B_IWL<5365> B_IWL<5364> B_IWL<5363> B_IWL<5362> B_IWL<5361> B_IWL<5360> B_IWL<5359> B_IWL<5358> B_IWL<5357> B_IWL<5356> B_IWL<5355> B_IWL<5354> B_IWL<5353> B_IWL<5352> B_IWL<5351> B_IWL<5350> B_IWL<5349> B_IWL<5348> B_IWL<5347> B_IWL<5346> B_IWL<5345> B_IWL<5344> B_IWL<5343> B_IWL<5342> B_IWL<5341> B_IWL<5340> B_IWL<5339> B_IWL<5338> B_IWL<5337> B_IWL<5336> B_IWL<5335> B_IWL<5334> B_IWL<5333> B_IWL<5332> B_IWL<5331> B_IWL<5330> B_IWL<5329> B_IWL<5328> B_IWL<5327> B_IWL<5326> B_IWL<5325> B_IWL<5324> B_IWL<5323> B_IWL<5322> B_IWL<5321> B_IWL<5320> B_IWL<5319> B_IWL<5318> B_IWL<5317> B_IWL<5316> B_IWL<5315> B_IWL<5314> B_IWL<5313> B_IWL<5312> B_IWL<5311> B_IWL<5310> B_IWL<5309> B_IWL<5308> B_IWL<5307> B_IWL<5306> B_IWL<5305> B_IWL<5304> B_IWL<5303> B_IWL<5302> B_IWL<5301> B_IWL<5300> B_IWL<5299> B_IWL<5298> B_IWL<5297> B_IWL<5296> B_IWL<5295> B_IWL<5294> B_IWL<5293> B_IWL<5292> B_IWL<5291> B_IWL<5290> B_IWL<5289> B_IWL<5288> B_IWL<5287> B_IWL<5286> B_IWL<5285> B_IWL<5284> B_IWL<5283> B_IWL<5282> B_IWL<5281> B_IWL<5280> B_IWL<5279> B_IWL<5278> B_IWL<5277> B_IWL<5276> B_IWL<5275> B_IWL<5274> B_IWL<5273> B_IWL<5272> B_IWL<5271> B_IWL<5270> B_IWL<5269> B_IWL<5268> B_IWL<5267> B_IWL<5266> B_IWL<5265> B_IWL<5264> B_IWL<5263> B_IWL<5262> B_IWL<5261> B_IWL<5260> B_IWL<5259> B_IWL<5258> B_IWL<5257> B_IWL<5256> B_IWL<5255> B_IWL<5254> B_IWL<5253> B_IWL<5252> B_IWL<5251> B_IWL<5250> B_IWL<5249> B_IWL<5248> B_IWL<5247> B_IWL<5246> B_IWL<5245> B_IWL<5244> B_IWL<5243> B_IWL<5242> B_IWL<5241> B_IWL<5240> B_IWL<5239> B_IWL<5238> B_IWL<5237> B_IWL<5236> B_IWL<5235> B_IWL<5234> B_IWL<5233> B_IWL<5232> B_IWL<5231> B_IWL<5230> B_IWL<5229> B_IWL<5228> B_IWL<5227> B_IWL<5226> B_IWL<5225> B_IWL<5224> B_IWL<5223> B_IWL<5222> B_IWL<5221> B_IWL<5220> B_IWL<5219> B_IWL<5218> B_IWL<5217> B_IWL<5216> B_IWL<5215> B_IWL<5214> B_IWL<5213> B_IWL<5212> B_IWL<5211> B_IWL<5210> B_IWL<5209> B_IWL<5208> B_IWL<5207> B_IWL<5206> B_IWL<5205> B_IWL<5204> B_IWL<5203> B_IWL<5202> B_IWL<5201> B_IWL<5200> B_IWL<5199> B_IWL<5198> B_IWL<5197> B_IWL<5196> B_IWL<5195> B_IWL<5194> B_IWL<5193> B_IWL<5192> B_IWL<5191> B_IWL<5190> B_IWL<5189> B_IWL<5188> B_IWL<5187> B_IWL<5186> B_IWL<5185> B_IWL<5184> B_IWL<5183> B_IWL<5182> B_IWL<5181> B_IWL<5180> B_IWL<5179> B_IWL<5178> B_IWL<5177> B_IWL<5176> B_IWL<5175> B_IWL<5174> B_IWL<5173> B_IWL<5172> B_IWL<5171> B_IWL<5170> B_IWL<5169> B_IWL<5168> B_IWL<5167> B_IWL<5166> B_IWL<5165> B_IWL<5164> B_IWL<5163> B_IWL<5162> B_IWL<5161> B_IWL<5160> B_IWL<5159> B_IWL<5158> B_IWL<5157> B_IWL<5156> B_IWL<5155> B_IWL<5154> B_IWL<5153> B_IWL<5152> B_IWL<5151> B_IWL<5150> B_IWL<5149> B_IWL<5148> B_IWL<5147> B_IWL<5146> B_IWL<5145> B_IWL<5144> B_IWL<5143> B_IWL<5142> B_IWL<5141> B_IWL<5140> B_IWL<5139> B_IWL<5138> B_IWL<5137> B_IWL<5136> B_IWL<5135> B_IWL<5134> B_IWL<5133> B_IWL<5132> B_IWL<5131> B_IWL<5130> B_IWL<5129> B_IWL<5128> B_IWL<5127> B_IWL<5126> B_IWL<5125> B_IWL<5124> B_IWL<5123> B_IWL<5122> B_IWL<5121> B_IWL<5120> VDD_CORE VSS / RM_IHPSG13_1024x32_c2_2P_COLUMN_pcell_0 +XCOL<19> A_BLC<39> A_BLC<38> A_BLC_TOP<39> A_BLC_TOP<38> A_BLT<39> A_BLT<38> A_BLT_TOP<39> A_BLT_TOP<38> A_IWL<4863> A_IWL<4862> A_IWL<4861> A_IWL<4860> A_IWL<4859> A_IWL<4858> A_IWL<4857> A_IWL<4856> A_IWL<4855> A_IWL<4854> A_IWL<4853> A_IWL<4852> A_IWL<4851> A_IWL<4850> A_IWL<4849> A_IWL<4848> A_IWL<4847> A_IWL<4846> A_IWL<4845> A_IWL<4844> A_IWL<4843> A_IWL<4842> A_IWL<4841> A_IWL<4840> A_IWL<4839> A_IWL<4838> A_IWL<4837> A_IWL<4836> A_IWL<4835> A_IWL<4834> A_IWL<4833> A_IWL<4832> A_IWL<4831> A_IWL<4830> A_IWL<4829> A_IWL<4828> A_IWL<4827> A_IWL<4826> A_IWL<4825> A_IWL<4824> A_IWL<4823> A_IWL<4822> A_IWL<4821> A_IWL<4820> A_IWL<4819> A_IWL<4818> A_IWL<4817> A_IWL<4816> A_IWL<4815> A_IWL<4814> A_IWL<4813> A_IWL<4812> A_IWL<4811> A_IWL<4810> A_IWL<4809> A_IWL<4808> A_IWL<4807> A_IWL<4806> A_IWL<4805> A_IWL<4804> A_IWL<4803> A_IWL<4802> A_IWL<4801> A_IWL<4800> A_IWL<4799> A_IWL<4798> A_IWL<4797> A_IWL<4796> A_IWL<4795> A_IWL<4794> A_IWL<4793> A_IWL<4792> A_IWL<4791> A_IWL<4790> A_IWL<4789> A_IWL<4788> A_IWL<4787> A_IWL<4786> A_IWL<4785> A_IWL<4784> A_IWL<4783> A_IWL<4782> A_IWL<4781> A_IWL<4780> A_IWL<4779> A_IWL<4778> A_IWL<4777> A_IWL<4776> A_IWL<4775> A_IWL<4774> A_IWL<4773> A_IWL<4772> A_IWL<4771> A_IWL<4770> A_IWL<4769> A_IWL<4768> A_IWL<4767> A_IWL<4766> A_IWL<4765> A_IWL<4764> A_IWL<4763> A_IWL<4762> A_IWL<4761> A_IWL<4760> A_IWL<4759> A_IWL<4758> A_IWL<4757> A_IWL<4756> A_IWL<4755> A_IWL<4754> A_IWL<4753> A_IWL<4752> A_IWL<4751> A_IWL<4750> A_IWL<4749> A_IWL<4748> A_IWL<4747> A_IWL<4746> A_IWL<4745> A_IWL<4744> A_IWL<4743> A_IWL<4742> A_IWL<4741> A_IWL<4740> A_IWL<4739> A_IWL<4738> A_IWL<4737> A_IWL<4736> A_IWL<4735> A_IWL<4734> A_IWL<4733> A_IWL<4732> A_IWL<4731> A_IWL<4730> A_IWL<4729> A_IWL<4728> A_IWL<4727> A_IWL<4726> A_IWL<4725> A_IWL<4724> A_IWL<4723> A_IWL<4722> A_IWL<4721> A_IWL<4720> A_IWL<4719> A_IWL<4718> A_IWL<4717> A_IWL<4716> A_IWL<4715> A_IWL<4714> A_IWL<4713> A_IWL<4712> A_IWL<4711> A_IWL<4710> A_IWL<4709> A_IWL<4708> A_IWL<4707> A_IWL<4706> A_IWL<4705> A_IWL<4704> A_IWL<4703> A_IWL<4702> A_IWL<4701> A_IWL<4700> A_IWL<4699> A_IWL<4698> A_IWL<4697> A_IWL<4696> A_IWL<4695> A_IWL<4694> A_IWL<4693> A_IWL<4692> A_IWL<4691> A_IWL<4690> A_IWL<4689> A_IWL<4688> A_IWL<4687> A_IWL<4686> A_IWL<4685> A_IWL<4684> A_IWL<4683> A_IWL<4682> A_IWL<4681> A_IWL<4680> A_IWL<4679> A_IWL<4678> A_IWL<4677> A_IWL<4676> A_IWL<4675> A_IWL<4674> A_IWL<4673> A_IWL<4672> A_IWL<4671> A_IWL<4670> A_IWL<4669> A_IWL<4668> A_IWL<4667> A_IWL<4666> A_IWL<4665> A_IWL<4664> A_IWL<4663> A_IWL<4662> A_IWL<4661> A_IWL<4660> A_IWL<4659> A_IWL<4658> A_IWL<4657> A_IWL<4656> A_IWL<4655> A_IWL<4654> A_IWL<4653> A_IWL<4652> A_IWL<4651> A_IWL<4650> A_IWL<4649> A_IWL<4648> A_IWL<4647> A_IWL<4646> A_IWL<4645> A_IWL<4644> A_IWL<4643> A_IWL<4642> A_IWL<4641> A_IWL<4640> A_IWL<4639> A_IWL<4638> A_IWL<4637> A_IWL<4636> A_IWL<4635> A_IWL<4634> A_IWL<4633> A_IWL<4632> A_IWL<4631> A_IWL<4630> A_IWL<4629> A_IWL<4628> A_IWL<4627> A_IWL<4626> A_IWL<4625> A_IWL<4624> A_IWL<4623> A_IWL<4622> A_IWL<4621> A_IWL<4620> A_IWL<4619> A_IWL<4618> A_IWL<4617> A_IWL<4616> A_IWL<4615> A_IWL<4614> A_IWL<4613> A_IWL<4612> A_IWL<4611> A_IWL<4610> A_IWL<4609> A_IWL<4608> A_IWL<5119> A_IWL<5118> A_IWL<5117> A_IWL<5116> A_IWL<5115> A_IWL<5114> A_IWL<5113> A_IWL<5112> A_IWL<5111> A_IWL<5110> A_IWL<5109> A_IWL<5108> A_IWL<5107> A_IWL<5106> A_IWL<5105> A_IWL<5104> A_IWL<5103> A_IWL<5102> A_IWL<5101> A_IWL<5100> A_IWL<5099> A_IWL<5098> A_IWL<5097> A_IWL<5096> A_IWL<5095> A_IWL<5094> A_IWL<5093> A_IWL<5092> A_IWL<5091> A_IWL<5090> A_IWL<5089> A_IWL<5088> A_IWL<5087> A_IWL<5086> A_IWL<5085> A_IWL<5084> A_IWL<5083> A_IWL<5082> A_IWL<5081> A_IWL<5080> A_IWL<5079> A_IWL<5078> A_IWL<5077> A_IWL<5076> A_IWL<5075> A_IWL<5074> A_IWL<5073> A_IWL<5072> A_IWL<5071> A_IWL<5070> A_IWL<5069> A_IWL<5068> A_IWL<5067> A_IWL<5066> A_IWL<5065> A_IWL<5064> A_IWL<5063> A_IWL<5062> A_IWL<5061> A_IWL<5060> A_IWL<5059> A_IWL<5058> A_IWL<5057> A_IWL<5056> A_IWL<5055> A_IWL<5054> A_IWL<5053> A_IWL<5052> A_IWL<5051> A_IWL<5050> A_IWL<5049> A_IWL<5048> A_IWL<5047> A_IWL<5046> A_IWL<5045> A_IWL<5044> A_IWL<5043> A_IWL<5042> A_IWL<5041> A_IWL<5040> A_IWL<5039> A_IWL<5038> A_IWL<5037> A_IWL<5036> A_IWL<5035> A_IWL<5034> A_IWL<5033> A_IWL<5032> A_IWL<5031> A_IWL<5030> A_IWL<5029> A_IWL<5028> A_IWL<5027> A_IWL<5026> A_IWL<5025> A_IWL<5024> A_IWL<5023> A_IWL<5022> A_IWL<5021> A_IWL<5020> A_IWL<5019> A_IWL<5018> A_IWL<5017> A_IWL<5016> A_IWL<5015> A_IWL<5014> A_IWL<5013> A_IWL<5012> A_IWL<5011> A_IWL<5010> A_IWL<5009> A_IWL<5008> A_IWL<5007> A_IWL<5006> A_IWL<5005> A_IWL<5004> A_IWL<5003> A_IWL<5002> A_IWL<5001> A_IWL<5000> A_IWL<4999> A_IWL<4998> A_IWL<4997> A_IWL<4996> A_IWL<4995> A_IWL<4994> A_IWL<4993> A_IWL<4992> A_IWL<4991> A_IWL<4990> A_IWL<4989> A_IWL<4988> A_IWL<4987> A_IWL<4986> A_IWL<4985> A_IWL<4984> A_IWL<4983> A_IWL<4982> A_IWL<4981> A_IWL<4980> A_IWL<4979> A_IWL<4978> A_IWL<4977> A_IWL<4976> A_IWL<4975> A_IWL<4974> A_IWL<4973> A_IWL<4972> A_IWL<4971> A_IWL<4970> A_IWL<4969> A_IWL<4968> A_IWL<4967> A_IWL<4966> A_IWL<4965> A_IWL<4964> A_IWL<4963> A_IWL<4962> A_IWL<4961> A_IWL<4960> A_IWL<4959> A_IWL<4958> A_IWL<4957> A_IWL<4956> A_IWL<4955> A_IWL<4954> A_IWL<4953> A_IWL<4952> A_IWL<4951> A_IWL<4950> A_IWL<4949> A_IWL<4948> A_IWL<4947> A_IWL<4946> A_IWL<4945> A_IWL<4944> A_IWL<4943> A_IWL<4942> A_IWL<4941> A_IWL<4940> A_IWL<4939> A_IWL<4938> A_IWL<4937> A_IWL<4936> A_IWL<4935> A_IWL<4934> A_IWL<4933> A_IWL<4932> A_IWL<4931> A_IWL<4930> A_IWL<4929> A_IWL<4928> A_IWL<4927> A_IWL<4926> A_IWL<4925> A_IWL<4924> A_IWL<4923> A_IWL<4922> A_IWL<4921> A_IWL<4920> A_IWL<4919> A_IWL<4918> A_IWL<4917> A_IWL<4916> A_IWL<4915> A_IWL<4914> A_IWL<4913> A_IWL<4912> A_IWL<4911> A_IWL<4910> A_IWL<4909> A_IWL<4908> A_IWL<4907> A_IWL<4906> A_IWL<4905> A_IWL<4904> A_IWL<4903> A_IWL<4902> A_IWL<4901> A_IWL<4900> A_IWL<4899> A_IWL<4898> A_IWL<4897> A_IWL<4896> A_IWL<4895> A_IWL<4894> A_IWL<4893> A_IWL<4892> A_IWL<4891> A_IWL<4890> A_IWL<4889> A_IWL<4888> A_IWL<4887> A_IWL<4886> A_IWL<4885> A_IWL<4884> A_IWL<4883> A_IWL<4882> A_IWL<4881> A_IWL<4880> A_IWL<4879> A_IWL<4878> A_IWL<4877> A_IWL<4876> A_IWL<4875> A_IWL<4874> A_IWL<4873> A_IWL<4872> A_IWL<4871> A_IWL<4870> A_IWL<4869> A_IWL<4868> A_IWL<4867> A_IWL<4866> A_IWL<4865> A_IWL<4864> B_BLC<39> B_BLC<38> B_BLC_TOP<39> B_BLC_TOP<38> B_BLT<39> B_BLT<38> B_BLT_TOP<39> B_BLT_TOP<38> B_IWL<4863> B_IWL<4862> B_IWL<4861> B_IWL<4860> B_IWL<4859> B_IWL<4858> B_IWL<4857> B_IWL<4856> B_IWL<4855> B_IWL<4854> B_IWL<4853> B_IWL<4852> B_IWL<4851> B_IWL<4850> B_IWL<4849> B_IWL<4848> B_IWL<4847> B_IWL<4846> B_IWL<4845> B_IWL<4844> B_IWL<4843> B_IWL<4842> B_IWL<4841> B_IWL<4840> B_IWL<4839> B_IWL<4838> B_IWL<4837> B_IWL<4836> B_IWL<4835> B_IWL<4834> B_IWL<4833> B_IWL<4832> B_IWL<4831> B_IWL<4830> B_IWL<4829> B_IWL<4828> B_IWL<4827> B_IWL<4826> B_IWL<4825> B_IWL<4824> B_IWL<4823> B_IWL<4822> B_IWL<4821> B_IWL<4820> B_IWL<4819> B_IWL<4818> B_IWL<4817> B_IWL<4816> B_IWL<4815> B_IWL<4814> B_IWL<4813> B_IWL<4812> B_IWL<4811> B_IWL<4810> B_IWL<4809> B_IWL<4808> B_IWL<4807> B_IWL<4806> B_IWL<4805> B_IWL<4804> B_IWL<4803> B_IWL<4802> B_IWL<4801> B_IWL<4800> B_IWL<4799> B_IWL<4798> B_IWL<4797> B_IWL<4796> B_IWL<4795> B_IWL<4794> B_IWL<4793> B_IWL<4792> B_IWL<4791> B_IWL<4790> B_IWL<4789> B_IWL<4788> B_IWL<4787> B_IWL<4786> B_IWL<4785> B_IWL<4784> B_IWL<4783> B_IWL<4782> B_IWL<4781> B_IWL<4780> B_IWL<4779> B_IWL<4778> B_IWL<4777> B_IWL<4776> B_IWL<4775> B_IWL<4774> B_IWL<4773> B_IWL<4772> B_IWL<4771> B_IWL<4770> B_IWL<4769> B_IWL<4768> B_IWL<4767> B_IWL<4766> B_IWL<4765> B_IWL<4764> B_IWL<4763> B_IWL<4762> B_IWL<4761> B_IWL<4760> B_IWL<4759> B_IWL<4758> B_IWL<4757> B_IWL<4756> B_IWL<4755> B_IWL<4754> B_IWL<4753> B_IWL<4752> B_IWL<4751> B_IWL<4750> B_IWL<4749> B_IWL<4748> B_IWL<4747> B_IWL<4746> B_IWL<4745> B_IWL<4744> B_IWL<4743> B_IWL<4742> B_IWL<4741> B_IWL<4740> B_IWL<4739> B_IWL<4738> B_IWL<4737> B_IWL<4736> B_IWL<4735> B_IWL<4734> B_IWL<4733> B_IWL<4732> B_IWL<4731> B_IWL<4730> B_IWL<4729> B_IWL<4728> B_IWL<4727> B_IWL<4726> B_IWL<4725> B_IWL<4724> B_IWL<4723> B_IWL<4722> B_IWL<4721> B_IWL<4720> B_IWL<4719> B_IWL<4718> B_IWL<4717> B_IWL<4716> B_IWL<4715> B_IWL<4714> B_IWL<4713> B_IWL<4712> B_IWL<4711> B_IWL<4710> B_IWL<4709> B_IWL<4708> B_IWL<4707> B_IWL<4706> B_IWL<4705> B_IWL<4704> B_IWL<4703> B_IWL<4702> B_IWL<4701> B_IWL<4700> B_IWL<4699> B_IWL<4698> B_IWL<4697> B_IWL<4696> B_IWL<4695> B_IWL<4694> B_IWL<4693> B_IWL<4692> B_IWL<4691> B_IWL<4690> B_IWL<4689> B_IWL<4688> B_IWL<4687> B_IWL<4686> B_IWL<4685> B_IWL<4684> B_IWL<4683> B_IWL<4682> B_IWL<4681> B_IWL<4680> B_IWL<4679> B_IWL<4678> B_IWL<4677> B_IWL<4676> B_IWL<4675> B_IWL<4674> B_IWL<4673> B_IWL<4672> B_IWL<4671> B_IWL<4670> B_IWL<4669> B_IWL<4668> B_IWL<4667> B_IWL<4666> B_IWL<4665> B_IWL<4664> B_IWL<4663> B_IWL<4662> B_IWL<4661> B_IWL<4660> B_IWL<4659> B_IWL<4658> B_IWL<4657> B_IWL<4656> B_IWL<4655> B_IWL<4654> B_IWL<4653> B_IWL<4652> B_IWL<4651> B_IWL<4650> B_IWL<4649> B_IWL<4648> B_IWL<4647> B_IWL<4646> B_IWL<4645> B_IWL<4644> B_IWL<4643> B_IWL<4642> B_IWL<4641> B_IWL<4640> B_IWL<4639> B_IWL<4638> B_IWL<4637> B_IWL<4636> B_IWL<4635> B_IWL<4634> B_IWL<4633> B_IWL<4632> B_IWL<4631> B_IWL<4630> B_IWL<4629> B_IWL<4628> B_IWL<4627> B_IWL<4626> B_IWL<4625> B_IWL<4624> B_IWL<4623> B_IWL<4622> B_IWL<4621> B_IWL<4620> B_IWL<4619> B_IWL<4618> B_IWL<4617> B_IWL<4616> B_IWL<4615> B_IWL<4614> B_IWL<4613> B_IWL<4612> B_IWL<4611> B_IWL<4610> B_IWL<4609> B_IWL<4608> B_IWL<5119> B_IWL<5118> B_IWL<5117> B_IWL<5116> B_IWL<5115> B_IWL<5114> B_IWL<5113> B_IWL<5112> B_IWL<5111> B_IWL<5110> B_IWL<5109> B_IWL<5108> B_IWL<5107> B_IWL<5106> B_IWL<5105> B_IWL<5104> B_IWL<5103> B_IWL<5102> B_IWL<5101> B_IWL<5100> B_IWL<5099> B_IWL<5098> B_IWL<5097> B_IWL<5096> B_IWL<5095> B_IWL<5094> B_IWL<5093> B_IWL<5092> B_IWL<5091> B_IWL<5090> B_IWL<5089> B_IWL<5088> B_IWL<5087> B_IWL<5086> B_IWL<5085> B_IWL<5084> B_IWL<5083> B_IWL<5082> B_IWL<5081> B_IWL<5080> B_IWL<5079> B_IWL<5078> B_IWL<5077> B_IWL<5076> B_IWL<5075> B_IWL<5074> B_IWL<5073> B_IWL<5072> B_IWL<5071> B_IWL<5070> B_IWL<5069> B_IWL<5068> B_IWL<5067> B_IWL<5066> B_IWL<5065> B_IWL<5064> B_IWL<5063> B_IWL<5062> B_IWL<5061> B_IWL<5060> B_IWL<5059> B_IWL<5058> B_IWL<5057> B_IWL<5056> B_IWL<5055> B_IWL<5054> B_IWL<5053> B_IWL<5052> B_IWL<5051> B_IWL<5050> B_IWL<5049> B_IWL<5048> B_IWL<5047> B_IWL<5046> B_IWL<5045> B_IWL<5044> B_IWL<5043> B_IWL<5042> B_IWL<5041> B_IWL<5040> B_IWL<5039> B_IWL<5038> B_IWL<5037> B_IWL<5036> B_IWL<5035> B_IWL<5034> B_IWL<5033> B_IWL<5032> B_IWL<5031> B_IWL<5030> B_IWL<5029> B_IWL<5028> B_IWL<5027> B_IWL<5026> B_IWL<5025> B_IWL<5024> B_IWL<5023> B_IWL<5022> B_IWL<5021> B_IWL<5020> B_IWL<5019> B_IWL<5018> B_IWL<5017> B_IWL<5016> B_IWL<5015> B_IWL<5014> B_IWL<5013> B_IWL<5012> B_IWL<5011> B_IWL<5010> B_IWL<5009> B_IWL<5008> B_IWL<5007> B_IWL<5006> B_IWL<5005> B_IWL<5004> B_IWL<5003> B_IWL<5002> B_IWL<5001> B_IWL<5000> B_IWL<4999> B_IWL<4998> B_IWL<4997> B_IWL<4996> B_IWL<4995> B_IWL<4994> B_IWL<4993> B_IWL<4992> B_IWL<4991> B_IWL<4990> B_IWL<4989> B_IWL<4988> B_IWL<4987> B_IWL<4986> B_IWL<4985> B_IWL<4984> B_IWL<4983> B_IWL<4982> B_IWL<4981> B_IWL<4980> B_IWL<4979> B_IWL<4978> B_IWL<4977> B_IWL<4976> B_IWL<4975> B_IWL<4974> B_IWL<4973> B_IWL<4972> B_IWL<4971> B_IWL<4970> B_IWL<4969> B_IWL<4968> B_IWL<4967> B_IWL<4966> B_IWL<4965> B_IWL<4964> B_IWL<4963> B_IWL<4962> B_IWL<4961> B_IWL<4960> B_IWL<4959> B_IWL<4958> B_IWL<4957> B_IWL<4956> B_IWL<4955> B_IWL<4954> B_IWL<4953> B_IWL<4952> B_IWL<4951> B_IWL<4950> B_IWL<4949> B_IWL<4948> B_IWL<4947> B_IWL<4946> B_IWL<4945> B_IWL<4944> B_IWL<4943> B_IWL<4942> B_IWL<4941> B_IWL<4940> B_IWL<4939> B_IWL<4938> B_IWL<4937> B_IWL<4936> B_IWL<4935> B_IWL<4934> B_IWL<4933> B_IWL<4932> B_IWL<4931> B_IWL<4930> B_IWL<4929> B_IWL<4928> B_IWL<4927> B_IWL<4926> B_IWL<4925> B_IWL<4924> B_IWL<4923> B_IWL<4922> B_IWL<4921> B_IWL<4920> B_IWL<4919> B_IWL<4918> B_IWL<4917> B_IWL<4916> B_IWL<4915> B_IWL<4914> B_IWL<4913> B_IWL<4912> B_IWL<4911> B_IWL<4910> B_IWL<4909> B_IWL<4908> B_IWL<4907> B_IWL<4906> B_IWL<4905> B_IWL<4904> B_IWL<4903> B_IWL<4902> B_IWL<4901> B_IWL<4900> B_IWL<4899> B_IWL<4898> B_IWL<4897> B_IWL<4896> B_IWL<4895> B_IWL<4894> B_IWL<4893> B_IWL<4892> B_IWL<4891> B_IWL<4890> B_IWL<4889> B_IWL<4888> B_IWL<4887> B_IWL<4886> B_IWL<4885> B_IWL<4884> B_IWL<4883> B_IWL<4882> B_IWL<4881> B_IWL<4880> B_IWL<4879> B_IWL<4878> B_IWL<4877> B_IWL<4876> B_IWL<4875> B_IWL<4874> B_IWL<4873> B_IWL<4872> B_IWL<4871> B_IWL<4870> B_IWL<4869> B_IWL<4868> B_IWL<4867> B_IWL<4866> B_IWL<4865> B_IWL<4864> VDD_CORE VSS / RM_IHPSG13_1024x32_c2_2P_COLUMN_pcell_0 +XCOL<18> A_BLC<37> A_BLC<36> A_BLC_TOP<37> A_BLC_TOP<36> A_BLT<37> A_BLT<36> A_BLT_TOP<37> A_BLT_TOP<36> A_IWL<4607> A_IWL<4606> A_IWL<4605> A_IWL<4604> A_IWL<4603> A_IWL<4602> A_IWL<4601> A_IWL<4600> A_IWL<4599> A_IWL<4598> A_IWL<4597> A_IWL<4596> A_IWL<4595> A_IWL<4594> A_IWL<4593> A_IWL<4592> A_IWL<4591> A_IWL<4590> A_IWL<4589> A_IWL<4588> A_IWL<4587> A_IWL<4586> A_IWL<4585> A_IWL<4584> A_IWL<4583> A_IWL<4582> A_IWL<4581> A_IWL<4580> A_IWL<4579> A_IWL<4578> A_IWL<4577> A_IWL<4576> A_IWL<4575> A_IWL<4574> A_IWL<4573> A_IWL<4572> A_IWL<4571> A_IWL<4570> A_IWL<4569> A_IWL<4568> A_IWL<4567> A_IWL<4566> A_IWL<4565> A_IWL<4564> A_IWL<4563> A_IWL<4562> A_IWL<4561> A_IWL<4560> A_IWL<4559> A_IWL<4558> A_IWL<4557> A_IWL<4556> A_IWL<4555> A_IWL<4554> A_IWL<4553> A_IWL<4552> A_IWL<4551> A_IWL<4550> A_IWL<4549> A_IWL<4548> A_IWL<4547> A_IWL<4546> A_IWL<4545> A_IWL<4544> A_IWL<4543> A_IWL<4542> A_IWL<4541> A_IWL<4540> A_IWL<4539> A_IWL<4538> A_IWL<4537> A_IWL<4536> A_IWL<4535> A_IWL<4534> A_IWL<4533> A_IWL<4532> A_IWL<4531> A_IWL<4530> A_IWL<4529> A_IWL<4528> A_IWL<4527> A_IWL<4526> A_IWL<4525> A_IWL<4524> A_IWL<4523> A_IWL<4522> A_IWL<4521> A_IWL<4520> A_IWL<4519> A_IWL<4518> A_IWL<4517> A_IWL<4516> A_IWL<4515> A_IWL<4514> A_IWL<4513> A_IWL<4512> A_IWL<4511> A_IWL<4510> A_IWL<4509> A_IWL<4508> A_IWL<4507> A_IWL<4506> A_IWL<4505> A_IWL<4504> A_IWL<4503> A_IWL<4502> A_IWL<4501> A_IWL<4500> A_IWL<4499> A_IWL<4498> A_IWL<4497> A_IWL<4496> A_IWL<4495> A_IWL<4494> A_IWL<4493> A_IWL<4492> A_IWL<4491> A_IWL<4490> A_IWL<4489> A_IWL<4488> A_IWL<4487> A_IWL<4486> A_IWL<4485> A_IWL<4484> A_IWL<4483> A_IWL<4482> A_IWL<4481> A_IWL<4480> A_IWL<4479> A_IWL<4478> A_IWL<4477> A_IWL<4476> A_IWL<4475> A_IWL<4474> A_IWL<4473> A_IWL<4472> A_IWL<4471> A_IWL<4470> A_IWL<4469> A_IWL<4468> A_IWL<4467> A_IWL<4466> A_IWL<4465> A_IWL<4464> A_IWL<4463> A_IWL<4462> A_IWL<4461> A_IWL<4460> A_IWL<4459> A_IWL<4458> A_IWL<4457> A_IWL<4456> A_IWL<4455> A_IWL<4454> A_IWL<4453> A_IWL<4452> A_IWL<4451> A_IWL<4450> A_IWL<4449> A_IWL<4448> A_IWL<4447> A_IWL<4446> A_IWL<4445> A_IWL<4444> A_IWL<4443> A_IWL<4442> A_IWL<4441> A_IWL<4440> A_IWL<4439> A_IWL<4438> A_IWL<4437> A_IWL<4436> A_IWL<4435> A_IWL<4434> A_IWL<4433> A_IWL<4432> A_IWL<4431> A_IWL<4430> A_IWL<4429> A_IWL<4428> A_IWL<4427> A_IWL<4426> A_IWL<4425> A_IWL<4424> A_IWL<4423> A_IWL<4422> A_IWL<4421> A_IWL<4420> A_IWL<4419> A_IWL<4418> A_IWL<4417> A_IWL<4416> A_IWL<4415> A_IWL<4414> A_IWL<4413> A_IWL<4412> A_IWL<4411> A_IWL<4410> A_IWL<4409> A_IWL<4408> A_IWL<4407> A_IWL<4406> A_IWL<4405> A_IWL<4404> A_IWL<4403> A_IWL<4402> A_IWL<4401> A_IWL<4400> A_IWL<4399> A_IWL<4398> A_IWL<4397> A_IWL<4396> A_IWL<4395> A_IWL<4394> A_IWL<4393> A_IWL<4392> A_IWL<4391> A_IWL<4390> A_IWL<4389> A_IWL<4388> A_IWL<4387> A_IWL<4386> A_IWL<4385> A_IWL<4384> A_IWL<4383> A_IWL<4382> A_IWL<4381> A_IWL<4380> A_IWL<4379> A_IWL<4378> A_IWL<4377> A_IWL<4376> A_IWL<4375> A_IWL<4374> A_IWL<4373> A_IWL<4372> A_IWL<4371> A_IWL<4370> A_IWL<4369> A_IWL<4368> A_IWL<4367> A_IWL<4366> A_IWL<4365> A_IWL<4364> A_IWL<4363> A_IWL<4362> A_IWL<4361> A_IWL<4360> A_IWL<4359> A_IWL<4358> A_IWL<4357> A_IWL<4356> A_IWL<4355> A_IWL<4354> A_IWL<4353> A_IWL<4352> A_IWL<4863> A_IWL<4862> A_IWL<4861> A_IWL<4860> A_IWL<4859> A_IWL<4858> A_IWL<4857> A_IWL<4856> A_IWL<4855> A_IWL<4854> A_IWL<4853> A_IWL<4852> A_IWL<4851> A_IWL<4850> A_IWL<4849> A_IWL<4848> A_IWL<4847> A_IWL<4846> A_IWL<4845> A_IWL<4844> A_IWL<4843> A_IWL<4842> A_IWL<4841> A_IWL<4840> A_IWL<4839> A_IWL<4838> A_IWL<4837> A_IWL<4836> A_IWL<4835> A_IWL<4834> A_IWL<4833> A_IWL<4832> A_IWL<4831> A_IWL<4830> A_IWL<4829> A_IWL<4828> A_IWL<4827> A_IWL<4826> A_IWL<4825> A_IWL<4824> A_IWL<4823> A_IWL<4822> A_IWL<4821> A_IWL<4820> A_IWL<4819> A_IWL<4818> A_IWL<4817> A_IWL<4816> A_IWL<4815> A_IWL<4814> A_IWL<4813> A_IWL<4812> A_IWL<4811> A_IWL<4810> A_IWL<4809> A_IWL<4808> A_IWL<4807> A_IWL<4806> A_IWL<4805> A_IWL<4804> A_IWL<4803> A_IWL<4802> A_IWL<4801> A_IWL<4800> A_IWL<4799> A_IWL<4798> A_IWL<4797> A_IWL<4796> A_IWL<4795> A_IWL<4794> A_IWL<4793> A_IWL<4792> A_IWL<4791> A_IWL<4790> A_IWL<4789> A_IWL<4788> A_IWL<4787> A_IWL<4786> A_IWL<4785> A_IWL<4784> A_IWL<4783> A_IWL<4782> A_IWL<4781> A_IWL<4780> A_IWL<4779> A_IWL<4778> A_IWL<4777> A_IWL<4776> A_IWL<4775> A_IWL<4774> A_IWL<4773> A_IWL<4772> A_IWL<4771> A_IWL<4770> A_IWL<4769> A_IWL<4768> A_IWL<4767> A_IWL<4766> A_IWL<4765> A_IWL<4764> A_IWL<4763> A_IWL<4762> A_IWL<4761> A_IWL<4760> A_IWL<4759> A_IWL<4758> A_IWL<4757> A_IWL<4756> A_IWL<4755> A_IWL<4754> A_IWL<4753> A_IWL<4752> A_IWL<4751> A_IWL<4750> A_IWL<4749> A_IWL<4748> A_IWL<4747> A_IWL<4746> A_IWL<4745> A_IWL<4744> A_IWL<4743> A_IWL<4742> A_IWL<4741> A_IWL<4740> A_IWL<4739> A_IWL<4738> A_IWL<4737> A_IWL<4736> A_IWL<4735> A_IWL<4734> A_IWL<4733> A_IWL<4732> A_IWL<4731> A_IWL<4730> A_IWL<4729> A_IWL<4728> A_IWL<4727> A_IWL<4726> A_IWL<4725> A_IWL<4724> A_IWL<4723> A_IWL<4722> A_IWL<4721> A_IWL<4720> A_IWL<4719> A_IWL<4718> A_IWL<4717> A_IWL<4716> A_IWL<4715> A_IWL<4714> A_IWL<4713> A_IWL<4712> A_IWL<4711> A_IWL<4710> A_IWL<4709> A_IWL<4708> A_IWL<4707> A_IWL<4706> A_IWL<4705> A_IWL<4704> A_IWL<4703> A_IWL<4702> A_IWL<4701> A_IWL<4700> A_IWL<4699> A_IWL<4698> A_IWL<4697> A_IWL<4696> A_IWL<4695> A_IWL<4694> A_IWL<4693> A_IWL<4692> A_IWL<4691> A_IWL<4690> A_IWL<4689> A_IWL<4688> A_IWL<4687> A_IWL<4686> A_IWL<4685> A_IWL<4684> A_IWL<4683> A_IWL<4682> A_IWL<4681> A_IWL<4680> A_IWL<4679> A_IWL<4678> A_IWL<4677> A_IWL<4676> A_IWL<4675> A_IWL<4674> A_IWL<4673> A_IWL<4672> A_IWL<4671> A_IWL<4670> A_IWL<4669> A_IWL<4668> A_IWL<4667> A_IWL<4666> A_IWL<4665> A_IWL<4664> A_IWL<4663> A_IWL<4662> A_IWL<4661> A_IWL<4660> A_IWL<4659> A_IWL<4658> A_IWL<4657> A_IWL<4656> A_IWL<4655> A_IWL<4654> A_IWL<4653> A_IWL<4652> A_IWL<4651> A_IWL<4650> A_IWL<4649> A_IWL<4648> A_IWL<4647> A_IWL<4646> A_IWL<4645> A_IWL<4644> A_IWL<4643> A_IWL<4642> A_IWL<4641> A_IWL<4640> A_IWL<4639> A_IWL<4638> A_IWL<4637> A_IWL<4636> A_IWL<4635> A_IWL<4634> A_IWL<4633> A_IWL<4632> A_IWL<4631> A_IWL<4630> A_IWL<4629> A_IWL<4628> A_IWL<4627> A_IWL<4626> A_IWL<4625> A_IWL<4624> A_IWL<4623> A_IWL<4622> A_IWL<4621> A_IWL<4620> A_IWL<4619> A_IWL<4618> A_IWL<4617> A_IWL<4616> A_IWL<4615> A_IWL<4614> A_IWL<4613> A_IWL<4612> A_IWL<4611> A_IWL<4610> A_IWL<4609> A_IWL<4608> B_BLC<37> B_BLC<36> B_BLC_TOP<37> B_BLC_TOP<36> B_BLT<37> B_BLT<36> B_BLT_TOP<37> B_BLT_TOP<36> B_IWL<4607> B_IWL<4606> B_IWL<4605> B_IWL<4604> B_IWL<4603> B_IWL<4602> B_IWL<4601> B_IWL<4600> B_IWL<4599> B_IWL<4598> B_IWL<4597> B_IWL<4596> B_IWL<4595> B_IWL<4594> B_IWL<4593> B_IWL<4592> B_IWL<4591> B_IWL<4590> B_IWL<4589> B_IWL<4588> B_IWL<4587> B_IWL<4586> B_IWL<4585> B_IWL<4584> B_IWL<4583> B_IWL<4582> B_IWL<4581> B_IWL<4580> B_IWL<4579> B_IWL<4578> B_IWL<4577> B_IWL<4576> B_IWL<4575> B_IWL<4574> B_IWL<4573> B_IWL<4572> B_IWL<4571> B_IWL<4570> B_IWL<4569> B_IWL<4568> B_IWL<4567> B_IWL<4566> B_IWL<4565> B_IWL<4564> B_IWL<4563> B_IWL<4562> B_IWL<4561> B_IWL<4560> B_IWL<4559> B_IWL<4558> B_IWL<4557> B_IWL<4556> B_IWL<4555> B_IWL<4554> B_IWL<4553> B_IWL<4552> B_IWL<4551> B_IWL<4550> B_IWL<4549> B_IWL<4548> B_IWL<4547> B_IWL<4546> B_IWL<4545> B_IWL<4544> B_IWL<4543> B_IWL<4542> B_IWL<4541> B_IWL<4540> B_IWL<4539> B_IWL<4538> B_IWL<4537> B_IWL<4536> B_IWL<4535> B_IWL<4534> B_IWL<4533> B_IWL<4532> B_IWL<4531> B_IWL<4530> B_IWL<4529> B_IWL<4528> B_IWL<4527> B_IWL<4526> B_IWL<4525> B_IWL<4524> B_IWL<4523> B_IWL<4522> B_IWL<4521> B_IWL<4520> B_IWL<4519> B_IWL<4518> B_IWL<4517> B_IWL<4516> B_IWL<4515> B_IWL<4514> B_IWL<4513> B_IWL<4512> B_IWL<4511> B_IWL<4510> B_IWL<4509> B_IWL<4508> B_IWL<4507> B_IWL<4506> B_IWL<4505> B_IWL<4504> B_IWL<4503> B_IWL<4502> B_IWL<4501> B_IWL<4500> B_IWL<4499> B_IWL<4498> B_IWL<4497> B_IWL<4496> B_IWL<4495> B_IWL<4494> B_IWL<4493> B_IWL<4492> B_IWL<4491> B_IWL<4490> B_IWL<4489> B_IWL<4488> B_IWL<4487> B_IWL<4486> B_IWL<4485> B_IWL<4484> B_IWL<4483> B_IWL<4482> B_IWL<4481> B_IWL<4480> B_IWL<4479> B_IWL<4478> B_IWL<4477> B_IWL<4476> B_IWL<4475> B_IWL<4474> B_IWL<4473> B_IWL<4472> B_IWL<4471> B_IWL<4470> B_IWL<4469> B_IWL<4468> B_IWL<4467> B_IWL<4466> B_IWL<4465> B_IWL<4464> B_IWL<4463> B_IWL<4462> B_IWL<4461> B_IWL<4460> B_IWL<4459> B_IWL<4458> B_IWL<4457> B_IWL<4456> B_IWL<4455> B_IWL<4454> B_IWL<4453> B_IWL<4452> B_IWL<4451> B_IWL<4450> B_IWL<4449> B_IWL<4448> B_IWL<4447> B_IWL<4446> B_IWL<4445> B_IWL<4444> B_IWL<4443> B_IWL<4442> B_IWL<4441> B_IWL<4440> B_IWL<4439> B_IWL<4438> B_IWL<4437> B_IWL<4436> B_IWL<4435> B_IWL<4434> B_IWL<4433> B_IWL<4432> B_IWL<4431> B_IWL<4430> B_IWL<4429> B_IWL<4428> B_IWL<4427> B_IWL<4426> B_IWL<4425> B_IWL<4424> B_IWL<4423> B_IWL<4422> B_IWL<4421> B_IWL<4420> B_IWL<4419> B_IWL<4418> B_IWL<4417> B_IWL<4416> B_IWL<4415> B_IWL<4414> B_IWL<4413> B_IWL<4412> B_IWL<4411> B_IWL<4410> B_IWL<4409> B_IWL<4408> B_IWL<4407> B_IWL<4406> B_IWL<4405> B_IWL<4404> B_IWL<4403> B_IWL<4402> B_IWL<4401> B_IWL<4400> B_IWL<4399> B_IWL<4398> B_IWL<4397> B_IWL<4396> B_IWL<4395> B_IWL<4394> B_IWL<4393> B_IWL<4392> B_IWL<4391> B_IWL<4390> B_IWL<4389> B_IWL<4388> B_IWL<4387> B_IWL<4386> B_IWL<4385> B_IWL<4384> B_IWL<4383> B_IWL<4382> B_IWL<4381> B_IWL<4380> B_IWL<4379> B_IWL<4378> B_IWL<4377> B_IWL<4376> B_IWL<4375> B_IWL<4374> B_IWL<4373> B_IWL<4372> B_IWL<4371> B_IWL<4370> B_IWL<4369> B_IWL<4368> B_IWL<4367> B_IWL<4366> B_IWL<4365> B_IWL<4364> B_IWL<4363> B_IWL<4362> B_IWL<4361> B_IWL<4360> B_IWL<4359> B_IWL<4358> B_IWL<4357> B_IWL<4356> B_IWL<4355> B_IWL<4354> B_IWL<4353> B_IWL<4352> B_IWL<4863> B_IWL<4862> B_IWL<4861> B_IWL<4860> B_IWL<4859> B_IWL<4858> B_IWL<4857> B_IWL<4856> B_IWL<4855> B_IWL<4854> B_IWL<4853> B_IWL<4852> B_IWL<4851> B_IWL<4850> B_IWL<4849> B_IWL<4848> B_IWL<4847> B_IWL<4846> B_IWL<4845> B_IWL<4844> B_IWL<4843> B_IWL<4842> B_IWL<4841> B_IWL<4840> B_IWL<4839> B_IWL<4838> B_IWL<4837> B_IWL<4836> B_IWL<4835> B_IWL<4834> B_IWL<4833> B_IWL<4832> B_IWL<4831> B_IWL<4830> B_IWL<4829> B_IWL<4828> B_IWL<4827> B_IWL<4826> B_IWL<4825> B_IWL<4824> B_IWL<4823> B_IWL<4822> B_IWL<4821> B_IWL<4820> B_IWL<4819> B_IWL<4818> B_IWL<4817> B_IWL<4816> B_IWL<4815> B_IWL<4814> B_IWL<4813> B_IWL<4812> B_IWL<4811> B_IWL<4810> B_IWL<4809> B_IWL<4808> B_IWL<4807> B_IWL<4806> B_IWL<4805> B_IWL<4804> B_IWL<4803> B_IWL<4802> B_IWL<4801> B_IWL<4800> B_IWL<4799> B_IWL<4798> B_IWL<4797> B_IWL<4796> B_IWL<4795> B_IWL<4794> B_IWL<4793> B_IWL<4792> B_IWL<4791> B_IWL<4790> B_IWL<4789> B_IWL<4788> B_IWL<4787> B_IWL<4786> B_IWL<4785> B_IWL<4784> B_IWL<4783> B_IWL<4782> B_IWL<4781> B_IWL<4780> B_IWL<4779> B_IWL<4778> B_IWL<4777> B_IWL<4776> B_IWL<4775> B_IWL<4774> B_IWL<4773> B_IWL<4772> B_IWL<4771> B_IWL<4770> B_IWL<4769> B_IWL<4768> B_IWL<4767> B_IWL<4766> B_IWL<4765> B_IWL<4764> B_IWL<4763> B_IWL<4762> B_IWL<4761> B_IWL<4760> B_IWL<4759> B_IWL<4758> B_IWL<4757> B_IWL<4756> B_IWL<4755> B_IWL<4754> B_IWL<4753> B_IWL<4752> B_IWL<4751> B_IWL<4750> B_IWL<4749> B_IWL<4748> B_IWL<4747> B_IWL<4746> B_IWL<4745> B_IWL<4744> B_IWL<4743> B_IWL<4742> B_IWL<4741> B_IWL<4740> B_IWL<4739> B_IWL<4738> B_IWL<4737> B_IWL<4736> B_IWL<4735> B_IWL<4734> B_IWL<4733> B_IWL<4732> B_IWL<4731> B_IWL<4730> B_IWL<4729> B_IWL<4728> B_IWL<4727> B_IWL<4726> B_IWL<4725> B_IWL<4724> B_IWL<4723> B_IWL<4722> B_IWL<4721> B_IWL<4720> B_IWL<4719> B_IWL<4718> B_IWL<4717> B_IWL<4716> B_IWL<4715> B_IWL<4714> B_IWL<4713> B_IWL<4712> B_IWL<4711> B_IWL<4710> B_IWL<4709> B_IWL<4708> B_IWL<4707> B_IWL<4706> B_IWL<4705> B_IWL<4704> B_IWL<4703> B_IWL<4702> B_IWL<4701> B_IWL<4700> B_IWL<4699> B_IWL<4698> B_IWL<4697> B_IWL<4696> B_IWL<4695> B_IWL<4694> B_IWL<4693> B_IWL<4692> B_IWL<4691> B_IWL<4690> B_IWL<4689> B_IWL<4688> B_IWL<4687> B_IWL<4686> B_IWL<4685> B_IWL<4684> B_IWL<4683> B_IWL<4682> B_IWL<4681> B_IWL<4680> B_IWL<4679> B_IWL<4678> B_IWL<4677> B_IWL<4676> B_IWL<4675> B_IWL<4674> B_IWL<4673> B_IWL<4672> B_IWL<4671> B_IWL<4670> B_IWL<4669> B_IWL<4668> B_IWL<4667> B_IWL<4666> B_IWL<4665> B_IWL<4664> B_IWL<4663> B_IWL<4662> B_IWL<4661> B_IWL<4660> B_IWL<4659> B_IWL<4658> B_IWL<4657> B_IWL<4656> B_IWL<4655> B_IWL<4654> B_IWL<4653> B_IWL<4652> B_IWL<4651> B_IWL<4650> B_IWL<4649> B_IWL<4648> B_IWL<4647> B_IWL<4646> B_IWL<4645> B_IWL<4644> B_IWL<4643> B_IWL<4642> B_IWL<4641> B_IWL<4640> B_IWL<4639> B_IWL<4638> B_IWL<4637> B_IWL<4636> B_IWL<4635> B_IWL<4634> B_IWL<4633> B_IWL<4632> B_IWL<4631> B_IWL<4630> B_IWL<4629> B_IWL<4628> B_IWL<4627> B_IWL<4626> B_IWL<4625> B_IWL<4624> B_IWL<4623> B_IWL<4622> B_IWL<4621> B_IWL<4620> B_IWL<4619> B_IWL<4618> B_IWL<4617> B_IWL<4616> B_IWL<4615> B_IWL<4614> B_IWL<4613> B_IWL<4612> B_IWL<4611> B_IWL<4610> B_IWL<4609> B_IWL<4608> VDD_CORE VSS / RM_IHPSG13_1024x32_c2_2P_COLUMN_pcell_0 +XCOL<17> A_BLC<35> A_BLC<34> A_BLC_TOP<35> A_BLC_TOP<34> A_BLT<35> A_BLT<34> A_BLT_TOP<35> A_BLT_TOP<34> A_IWL<4351> A_IWL<4350> A_IWL<4349> A_IWL<4348> A_IWL<4347> A_IWL<4346> A_IWL<4345> A_IWL<4344> A_IWL<4343> A_IWL<4342> A_IWL<4341> A_IWL<4340> A_IWL<4339> A_IWL<4338> A_IWL<4337> A_IWL<4336> A_IWL<4335> A_IWL<4334> A_IWL<4333> A_IWL<4332> A_IWL<4331> A_IWL<4330> A_IWL<4329> A_IWL<4328> A_IWL<4327> A_IWL<4326> A_IWL<4325> A_IWL<4324> A_IWL<4323> A_IWL<4322> A_IWL<4321> A_IWL<4320> A_IWL<4319> A_IWL<4318> A_IWL<4317> A_IWL<4316> A_IWL<4315> A_IWL<4314> A_IWL<4313> A_IWL<4312> A_IWL<4311> A_IWL<4310> A_IWL<4309> A_IWL<4308> A_IWL<4307> A_IWL<4306> A_IWL<4305> A_IWL<4304> A_IWL<4303> A_IWL<4302> A_IWL<4301> A_IWL<4300> A_IWL<4299> A_IWL<4298> A_IWL<4297> A_IWL<4296> A_IWL<4295> A_IWL<4294> A_IWL<4293> A_IWL<4292> A_IWL<4291> A_IWL<4290> A_IWL<4289> A_IWL<4288> A_IWL<4287> A_IWL<4286> A_IWL<4285> A_IWL<4284> A_IWL<4283> A_IWL<4282> A_IWL<4281> A_IWL<4280> A_IWL<4279> A_IWL<4278> A_IWL<4277> A_IWL<4276> A_IWL<4275> A_IWL<4274> A_IWL<4273> A_IWL<4272> A_IWL<4271> A_IWL<4270> A_IWL<4269> A_IWL<4268> A_IWL<4267> A_IWL<4266> A_IWL<4265> A_IWL<4264> A_IWL<4263> A_IWL<4262> A_IWL<4261> A_IWL<4260> A_IWL<4259> A_IWL<4258> A_IWL<4257> A_IWL<4256> A_IWL<4255> A_IWL<4254> A_IWL<4253> A_IWL<4252> A_IWL<4251> A_IWL<4250> A_IWL<4249> A_IWL<4248> A_IWL<4247> A_IWL<4246> A_IWL<4245> A_IWL<4244> A_IWL<4243> A_IWL<4242> A_IWL<4241> A_IWL<4240> A_IWL<4239> A_IWL<4238> A_IWL<4237> A_IWL<4236> A_IWL<4235> A_IWL<4234> A_IWL<4233> A_IWL<4232> A_IWL<4231> A_IWL<4230> A_IWL<4229> A_IWL<4228> A_IWL<4227> A_IWL<4226> A_IWL<4225> A_IWL<4224> A_IWL<4223> A_IWL<4222> A_IWL<4221> A_IWL<4220> A_IWL<4219> A_IWL<4218> A_IWL<4217> A_IWL<4216> A_IWL<4215> A_IWL<4214> A_IWL<4213> A_IWL<4212> A_IWL<4211> A_IWL<4210> A_IWL<4209> A_IWL<4208> A_IWL<4207> A_IWL<4206> A_IWL<4205> A_IWL<4204> A_IWL<4203> A_IWL<4202> A_IWL<4201> A_IWL<4200> A_IWL<4199> A_IWL<4198> A_IWL<4197> A_IWL<4196> A_IWL<4195> A_IWL<4194> A_IWL<4193> A_IWL<4192> A_IWL<4191> A_IWL<4190> A_IWL<4189> A_IWL<4188> A_IWL<4187> A_IWL<4186> A_IWL<4185> A_IWL<4184> A_IWL<4183> A_IWL<4182> A_IWL<4181> A_IWL<4180> A_IWL<4179> A_IWL<4178> A_IWL<4177> A_IWL<4176> A_IWL<4175> A_IWL<4174> A_IWL<4173> A_IWL<4172> A_IWL<4171> A_IWL<4170> A_IWL<4169> A_IWL<4168> A_IWL<4167> A_IWL<4166> A_IWL<4165> A_IWL<4164> A_IWL<4163> A_IWL<4162> A_IWL<4161> A_IWL<4160> A_IWL<4159> A_IWL<4158> A_IWL<4157> A_IWL<4156> A_IWL<4155> A_IWL<4154> A_IWL<4153> A_IWL<4152> A_IWL<4151> A_IWL<4150> A_IWL<4149> A_IWL<4148> A_IWL<4147> A_IWL<4146> A_IWL<4145> A_IWL<4144> A_IWL<4143> A_IWL<4142> A_IWL<4141> A_IWL<4140> A_IWL<4139> A_IWL<4138> A_IWL<4137> A_IWL<4136> A_IWL<4135> A_IWL<4134> A_IWL<4133> A_IWL<4132> A_IWL<4131> A_IWL<4130> A_IWL<4129> A_IWL<4128> A_IWL<4127> A_IWL<4126> A_IWL<4125> A_IWL<4124> A_IWL<4123> A_IWL<4122> A_IWL<4121> A_IWL<4120> A_IWL<4119> A_IWL<4118> A_IWL<4117> A_IWL<4116> A_IWL<4115> A_IWL<4114> A_IWL<4113> A_IWL<4112> A_IWL<4111> A_IWL<4110> A_IWL<4109> A_IWL<4108> A_IWL<4107> A_IWL<4106> A_IWL<4105> A_IWL<4104> A_IWL<4103> A_IWL<4102> A_IWL<4101> A_IWL<4100> A_IWL<4099> A_IWL<4098> A_IWL<4097> A_IWL<4096> A_IWL<4607> A_IWL<4606> A_IWL<4605> A_IWL<4604> A_IWL<4603> A_IWL<4602> A_IWL<4601> A_IWL<4600> A_IWL<4599> A_IWL<4598> A_IWL<4597> A_IWL<4596> A_IWL<4595> A_IWL<4594> A_IWL<4593> A_IWL<4592> A_IWL<4591> A_IWL<4590> A_IWL<4589> A_IWL<4588> A_IWL<4587> A_IWL<4586> A_IWL<4585> A_IWL<4584> A_IWL<4583> A_IWL<4582> A_IWL<4581> A_IWL<4580> A_IWL<4579> A_IWL<4578> A_IWL<4577> A_IWL<4576> A_IWL<4575> A_IWL<4574> A_IWL<4573> A_IWL<4572> A_IWL<4571> A_IWL<4570> A_IWL<4569> A_IWL<4568> A_IWL<4567> A_IWL<4566> A_IWL<4565> A_IWL<4564> A_IWL<4563> A_IWL<4562> A_IWL<4561> A_IWL<4560> A_IWL<4559> A_IWL<4558> A_IWL<4557> A_IWL<4556> A_IWL<4555> A_IWL<4554> A_IWL<4553> A_IWL<4552> A_IWL<4551> A_IWL<4550> A_IWL<4549> A_IWL<4548> A_IWL<4547> A_IWL<4546> A_IWL<4545> A_IWL<4544> A_IWL<4543> A_IWL<4542> A_IWL<4541> A_IWL<4540> A_IWL<4539> A_IWL<4538> A_IWL<4537> A_IWL<4536> A_IWL<4535> A_IWL<4534> A_IWL<4533> A_IWL<4532> A_IWL<4531> A_IWL<4530> A_IWL<4529> A_IWL<4528> A_IWL<4527> A_IWL<4526> A_IWL<4525> A_IWL<4524> A_IWL<4523> A_IWL<4522> A_IWL<4521> A_IWL<4520> A_IWL<4519> A_IWL<4518> A_IWL<4517> A_IWL<4516> A_IWL<4515> A_IWL<4514> A_IWL<4513> A_IWL<4512> A_IWL<4511> A_IWL<4510> A_IWL<4509> A_IWL<4508> A_IWL<4507> A_IWL<4506> A_IWL<4505> A_IWL<4504> A_IWL<4503> A_IWL<4502> A_IWL<4501> A_IWL<4500> A_IWL<4499> A_IWL<4498> A_IWL<4497> A_IWL<4496> A_IWL<4495> A_IWL<4494> A_IWL<4493> A_IWL<4492> A_IWL<4491> A_IWL<4490> A_IWL<4489> A_IWL<4488> A_IWL<4487> A_IWL<4486> A_IWL<4485> A_IWL<4484> A_IWL<4483> A_IWL<4482> A_IWL<4481> A_IWL<4480> A_IWL<4479> A_IWL<4478> A_IWL<4477> A_IWL<4476> A_IWL<4475> A_IWL<4474> A_IWL<4473> A_IWL<4472> A_IWL<4471> A_IWL<4470> A_IWL<4469> A_IWL<4468> A_IWL<4467> A_IWL<4466> A_IWL<4465> A_IWL<4464> A_IWL<4463> A_IWL<4462> A_IWL<4461> A_IWL<4460> A_IWL<4459> A_IWL<4458> A_IWL<4457> A_IWL<4456> A_IWL<4455> A_IWL<4454> A_IWL<4453> A_IWL<4452> A_IWL<4451> A_IWL<4450> A_IWL<4449> A_IWL<4448> A_IWL<4447> A_IWL<4446> A_IWL<4445> A_IWL<4444> A_IWL<4443> A_IWL<4442> A_IWL<4441> A_IWL<4440> A_IWL<4439> A_IWL<4438> A_IWL<4437> A_IWL<4436> A_IWL<4435> A_IWL<4434> A_IWL<4433> A_IWL<4432> A_IWL<4431> A_IWL<4430> A_IWL<4429> A_IWL<4428> A_IWL<4427> A_IWL<4426> A_IWL<4425> A_IWL<4424> A_IWL<4423> A_IWL<4422> A_IWL<4421> A_IWL<4420> A_IWL<4419> A_IWL<4418> A_IWL<4417> A_IWL<4416> A_IWL<4415> A_IWL<4414> A_IWL<4413> A_IWL<4412> A_IWL<4411> A_IWL<4410> A_IWL<4409> A_IWL<4408> A_IWL<4407> A_IWL<4406> A_IWL<4405> A_IWL<4404> A_IWL<4403> A_IWL<4402> A_IWL<4401> A_IWL<4400> A_IWL<4399> A_IWL<4398> A_IWL<4397> A_IWL<4396> A_IWL<4395> A_IWL<4394> A_IWL<4393> A_IWL<4392> A_IWL<4391> A_IWL<4390> A_IWL<4389> A_IWL<4388> A_IWL<4387> A_IWL<4386> A_IWL<4385> A_IWL<4384> A_IWL<4383> A_IWL<4382> A_IWL<4381> A_IWL<4380> A_IWL<4379> A_IWL<4378> A_IWL<4377> A_IWL<4376> A_IWL<4375> A_IWL<4374> A_IWL<4373> A_IWL<4372> A_IWL<4371> A_IWL<4370> A_IWL<4369> A_IWL<4368> A_IWL<4367> A_IWL<4366> A_IWL<4365> A_IWL<4364> A_IWL<4363> A_IWL<4362> A_IWL<4361> A_IWL<4360> A_IWL<4359> A_IWL<4358> A_IWL<4357> A_IWL<4356> A_IWL<4355> A_IWL<4354> A_IWL<4353> A_IWL<4352> B_BLC<35> B_BLC<34> B_BLC_TOP<35> B_BLC_TOP<34> B_BLT<35> B_BLT<34> B_BLT_TOP<35> B_BLT_TOP<34> B_IWL<4351> B_IWL<4350> B_IWL<4349> B_IWL<4348> B_IWL<4347> B_IWL<4346> B_IWL<4345> B_IWL<4344> B_IWL<4343> B_IWL<4342> B_IWL<4341> B_IWL<4340> B_IWL<4339> B_IWL<4338> B_IWL<4337> B_IWL<4336> B_IWL<4335> B_IWL<4334> B_IWL<4333> B_IWL<4332> B_IWL<4331> B_IWL<4330> B_IWL<4329> B_IWL<4328> B_IWL<4327> B_IWL<4326> B_IWL<4325> B_IWL<4324> B_IWL<4323> B_IWL<4322> B_IWL<4321> B_IWL<4320> B_IWL<4319> B_IWL<4318> B_IWL<4317> B_IWL<4316> B_IWL<4315> B_IWL<4314> B_IWL<4313> B_IWL<4312> B_IWL<4311> B_IWL<4310> B_IWL<4309> B_IWL<4308> B_IWL<4307> B_IWL<4306> B_IWL<4305> B_IWL<4304> B_IWL<4303> B_IWL<4302> B_IWL<4301> B_IWL<4300> B_IWL<4299> B_IWL<4298> B_IWL<4297> B_IWL<4296> B_IWL<4295> B_IWL<4294> B_IWL<4293> B_IWL<4292> B_IWL<4291> B_IWL<4290> B_IWL<4289> B_IWL<4288> B_IWL<4287> B_IWL<4286> B_IWL<4285> B_IWL<4284> B_IWL<4283> B_IWL<4282> B_IWL<4281> B_IWL<4280> B_IWL<4279> B_IWL<4278> B_IWL<4277> B_IWL<4276> B_IWL<4275> B_IWL<4274> B_IWL<4273> B_IWL<4272> B_IWL<4271> B_IWL<4270> B_IWL<4269> B_IWL<4268> B_IWL<4267> B_IWL<4266> B_IWL<4265> B_IWL<4264> B_IWL<4263> B_IWL<4262> B_IWL<4261> B_IWL<4260> B_IWL<4259> B_IWL<4258> B_IWL<4257> B_IWL<4256> B_IWL<4255> B_IWL<4254> B_IWL<4253> B_IWL<4252> B_IWL<4251> B_IWL<4250> B_IWL<4249> B_IWL<4248> B_IWL<4247> B_IWL<4246> B_IWL<4245> B_IWL<4244> B_IWL<4243> B_IWL<4242> B_IWL<4241> B_IWL<4240> B_IWL<4239> B_IWL<4238> B_IWL<4237> B_IWL<4236> B_IWL<4235> B_IWL<4234> B_IWL<4233> B_IWL<4232> B_IWL<4231> B_IWL<4230> B_IWL<4229> B_IWL<4228> B_IWL<4227> B_IWL<4226> B_IWL<4225> B_IWL<4224> B_IWL<4223> B_IWL<4222> B_IWL<4221> B_IWL<4220> B_IWL<4219> B_IWL<4218> B_IWL<4217> B_IWL<4216> B_IWL<4215> B_IWL<4214> B_IWL<4213> B_IWL<4212> B_IWL<4211> B_IWL<4210> B_IWL<4209> B_IWL<4208> B_IWL<4207> B_IWL<4206> B_IWL<4205> B_IWL<4204> B_IWL<4203> B_IWL<4202> B_IWL<4201> B_IWL<4200> B_IWL<4199> B_IWL<4198> B_IWL<4197> B_IWL<4196> B_IWL<4195> B_IWL<4194> B_IWL<4193> B_IWL<4192> B_IWL<4191> B_IWL<4190> B_IWL<4189> B_IWL<4188> B_IWL<4187> B_IWL<4186> B_IWL<4185> B_IWL<4184> B_IWL<4183> B_IWL<4182> B_IWL<4181> B_IWL<4180> B_IWL<4179> B_IWL<4178> B_IWL<4177> B_IWL<4176> B_IWL<4175> B_IWL<4174> B_IWL<4173> B_IWL<4172> B_IWL<4171> B_IWL<4170> B_IWL<4169> B_IWL<4168> B_IWL<4167> B_IWL<4166> B_IWL<4165> B_IWL<4164> B_IWL<4163> B_IWL<4162> B_IWL<4161> B_IWL<4160> B_IWL<4159> B_IWL<4158> B_IWL<4157> B_IWL<4156> B_IWL<4155> B_IWL<4154> B_IWL<4153> B_IWL<4152> B_IWL<4151> B_IWL<4150> B_IWL<4149> B_IWL<4148> B_IWL<4147> B_IWL<4146> B_IWL<4145> B_IWL<4144> B_IWL<4143> B_IWL<4142> B_IWL<4141> B_IWL<4140> B_IWL<4139> B_IWL<4138> B_IWL<4137> B_IWL<4136> B_IWL<4135> B_IWL<4134> B_IWL<4133> B_IWL<4132> B_IWL<4131> B_IWL<4130> B_IWL<4129> B_IWL<4128> B_IWL<4127> B_IWL<4126> B_IWL<4125> B_IWL<4124> B_IWL<4123> B_IWL<4122> B_IWL<4121> B_IWL<4120> B_IWL<4119> B_IWL<4118> B_IWL<4117> B_IWL<4116> B_IWL<4115> B_IWL<4114> B_IWL<4113> B_IWL<4112> B_IWL<4111> B_IWL<4110> B_IWL<4109> B_IWL<4108> B_IWL<4107> B_IWL<4106> B_IWL<4105> B_IWL<4104> B_IWL<4103> B_IWL<4102> B_IWL<4101> B_IWL<4100> B_IWL<4099> B_IWL<4098> B_IWL<4097> B_IWL<4096> B_IWL<4607> B_IWL<4606> B_IWL<4605> B_IWL<4604> B_IWL<4603> B_IWL<4602> B_IWL<4601> B_IWL<4600> B_IWL<4599> B_IWL<4598> B_IWL<4597> B_IWL<4596> B_IWL<4595> B_IWL<4594> B_IWL<4593> B_IWL<4592> B_IWL<4591> B_IWL<4590> B_IWL<4589> B_IWL<4588> B_IWL<4587> B_IWL<4586> B_IWL<4585> B_IWL<4584> B_IWL<4583> B_IWL<4582> B_IWL<4581> B_IWL<4580> B_IWL<4579> B_IWL<4578> B_IWL<4577> B_IWL<4576> B_IWL<4575> B_IWL<4574> B_IWL<4573> B_IWL<4572> B_IWL<4571> B_IWL<4570> B_IWL<4569> B_IWL<4568> B_IWL<4567> B_IWL<4566> B_IWL<4565> B_IWL<4564> B_IWL<4563> B_IWL<4562> B_IWL<4561> B_IWL<4560> B_IWL<4559> B_IWL<4558> B_IWL<4557> B_IWL<4556> B_IWL<4555> B_IWL<4554> B_IWL<4553> B_IWL<4552> B_IWL<4551> B_IWL<4550> B_IWL<4549> B_IWL<4548> B_IWL<4547> B_IWL<4546> B_IWL<4545> B_IWL<4544> B_IWL<4543> B_IWL<4542> B_IWL<4541> B_IWL<4540> B_IWL<4539> B_IWL<4538> B_IWL<4537> B_IWL<4536> B_IWL<4535> B_IWL<4534> B_IWL<4533> B_IWL<4532> B_IWL<4531> B_IWL<4530> B_IWL<4529> B_IWL<4528> B_IWL<4527> B_IWL<4526> B_IWL<4525> B_IWL<4524> B_IWL<4523> B_IWL<4522> B_IWL<4521> B_IWL<4520> B_IWL<4519> B_IWL<4518> B_IWL<4517> B_IWL<4516> B_IWL<4515> B_IWL<4514> B_IWL<4513> B_IWL<4512> B_IWL<4511> B_IWL<4510> B_IWL<4509> B_IWL<4508> B_IWL<4507> B_IWL<4506> B_IWL<4505> B_IWL<4504> B_IWL<4503> B_IWL<4502> B_IWL<4501> B_IWL<4500> B_IWL<4499> B_IWL<4498> B_IWL<4497> B_IWL<4496> B_IWL<4495> B_IWL<4494> B_IWL<4493> B_IWL<4492> B_IWL<4491> B_IWL<4490> B_IWL<4489> B_IWL<4488> B_IWL<4487> B_IWL<4486> B_IWL<4485> B_IWL<4484> B_IWL<4483> B_IWL<4482> B_IWL<4481> B_IWL<4480> B_IWL<4479> B_IWL<4478> B_IWL<4477> B_IWL<4476> B_IWL<4475> B_IWL<4474> B_IWL<4473> B_IWL<4472> B_IWL<4471> B_IWL<4470> B_IWL<4469> B_IWL<4468> B_IWL<4467> B_IWL<4466> B_IWL<4465> B_IWL<4464> B_IWL<4463> B_IWL<4462> B_IWL<4461> B_IWL<4460> B_IWL<4459> B_IWL<4458> B_IWL<4457> B_IWL<4456> B_IWL<4455> B_IWL<4454> B_IWL<4453> B_IWL<4452> B_IWL<4451> B_IWL<4450> B_IWL<4449> B_IWL<4448> B_IWL<4447> B_IWL<4446> B_IWL<4445> B_IWL<4444> B_IWL<4443> B_IWL<4442> B_IWL<4441> B_IWL<4440> B_IWL<4439> B_IWL<4438> B_IWL<4437> B_IWL<4436> B_IWL<4435> B_IWL<4434> B_IWL<4433> B_IWL<4432> B_IWL<4431> B_IWL<4430> B_IWL<4429> B_IWL<4428> B_IWL<4427> B_IWL<4426> B_IWL<4425> B_IWL<4424> B_IWL<4423> B_IWL<4422> B_IWL<4421> B_IWL<4420> B_IWL<4419> B_IWL<4418> B_IWL<4417> B_IWL<4416> B_IWL<4415> B_IWL<4414> B_IWL<4413> B_IWL<4412> B_IWL<4411> B_IWL<4410> B_IWL<4409> B_IWL<4408> B_IWL<4407> B_IWL<4406> B_IWL<4405> B_IWL<4404> B_IWL<4403> B_IWL<4402> B_IWL<4401> B_IWL<4400> B_IWL<4399> B_IWL<4398> B_IWL<4397> B_IWL<4396> B_IWL<4395> B_IWL<4394> B_IWL<4393> B_IWL<4392> B_IWL<4391> B_IWL<4390> B_IWL<4389> B_IWL<4388> B_IWL<4387> B_IWL<4386> B_IWL<4385> B_IWL<4384> B_IWL<4383> B_IWL<4382> B_IWL<4381> B_IWL<4380> B_IWL<4379> B_IWL<4378> B_IWL<4377> B_IWL<4376> B_IWL<4375> B_IWL<4374> B_IWL<4373> B_IWL<4372> B_IWL<4371> B_IWL<4370> B_IWL<4369> B_IWL<4368> B_IWL<4367> B_IWL<4366> B_IWL<4365> B_IWL<4364> B_IWL<4363> B_IWL<4362> B_IWL<4361> B_IWL<4360> B_IWL<4359> B_IWL<4358> B_IWL<4357> B_IWL<4356> B_IWL<4355> B_IWL<4354> B_IWL<4353> B_IWL<4352> VDD_CORE VSS / RM_IHPSG13_1024x32_c2_2P_COLUMN_pcell_0 +XCOL<16> A_BLC<33> A_BLC<32> A_BLC_TOP<33> A_BLC_TOP<32> A_BLT<33> A_BLT<32> A_BLT_TOP<33> A_BLT_TOP<32> A_IWL<4095> A_IWL<4094> A_IWL<4093> A_IWL<4092> A_IWL<4091> A_IWL<4090> A_IWL<4089> A_IWL<4088> A_IWL<4087> A_IWL<4086> A_IWL<4085> A_IWL<4084> A_IWL<4083> A_IWL<4082> A_IWL<4081> A_IWL<4080> A_IWL<4079> A_IWL<4078> A_IWL<4077> A_IWL<4076> A_IWL<4075> A_IWL<4074> A_IWL<4073> A_IWL<4072> A_IWL<4071> A_IWL<4070> A_IWL<4069> A_IWL<4068> A_IWL<4067> A_IWL<4066> A_IWL<4065> A_IWL<4064> A_IWL<4063> A_IWL<4062> A_IWL<4061> A_IWL<4060> A_IWL<4059> A_IWL<4058> A_IWL<4057> A_IWL<4056> A_IWL<4055> A_IWL<4054> A_IWL<4053> A_IWL<4052> A_IWL<4051> A_IWL<4050> A_IWL<4049> A_IWL<4048> A_IWL<4047> A_IWL<4046> A_IWL<4045> A_IWL<4044> A_IWL<4043> A_IWL<4042> A_IWL<4041> A_IWL<4040> A_IWL<4039> A_IWL<4038> A_IWL<4037> A_IWL<4036> A_IWL<4035> A_IWL<4034> A_IWL<4033> A_IWL<4032> A_IWL<4031> A_IWL<4030> A_IWL<4029> A_IWL<4028> A_IWL<4027> A_IWL<4026> A_IWL<4025> A_IWL<4024> A_IWL<4023> A_IWL<4022> A_IWL<4021> A_IWL<4020> A_IWL<4019> A_IWL<4018> A_IWL<4017> A_IWL<4016> A_IWL<4015> A_IWL<4014> A_IWL<4013> A_IWL<4012> A_IWL<4011> A_IWL<4010> A_IWL<4009> A_IWL<4008> A_IWL<4007> A_IWL<4006> A_IWL<4005> A_IWL<4004> A_IWL<4003> A_IWL<4002> A_IWL<4001> A_IWL<4000> A_IWL<3999> A_IWL<3998> A_IWL<3997> A_IWL<3996> A_IWL<3995> A_IWL<3994> A_IWL<3993> A_IWL<3992> A_IWL<3991> A_IWL<3990> A_IWL<3989> A_IWL<3988> A_IWL<3987> A_IWL<3986> A_IWL<3985> A_IWL<3984> A_IWL<3983> A_IWL<3982> A_IWL<3981> A_IWL<3980> A_IWL<3979> A_IWL<3978> A_IWL<3977> A_IWL<3976> A_IWL<3975> A_IWL<3974> A_IWL<3973> A_IWL<3972> A_IWL<3971> A_IWL<3970> A_IWL<3969> A_IWL<3968> A_IWL<3967> A_IWL<3966> A_IWL<3965> A_IWL<3964> A_IWL<3963> A_IWL<3962> A_IWL<3961> A_IWL<3960> A_IWL<3959> A_IWL<3958> A_IWL<3957> A_IWL<3956> A_IWL<3955> A_IWL<3954> A_IWL<3953> A_IWL<3952> A_IWL<3951> A_IWL<3950> A_IWL<3949> A_IWL<3948> A_IWL<3947> A_IWL<3946> A_IWL<3945> A_IWL<3944> A_IWL<3943> A_IWL<3942> A_IWL<3941> A_IWL<3940> A_IWL<3939> A_IWL<3938> A_IWL<3937> A_IWL<3936> A_IWL<3935> A_IWL<3934> A_IWL<3933> A_IWL<3932> A_IWL<3931> A_IWL<3930> A_IWL<3929> A_IWL<3928> A_IWL<3927> A_IWL<3926> A_IWL<3925> A_IWL<3924> A_IWL<3923> A_IWL<3922> A_IWL<3921> A_IWL<3920> A_IWL<3919> A_IWL<3918> A_IWL<3917> A_IWL<3916> A_IWL<3915> A_IWL<3914> A_IWL<3913> A_IWL<3912> A_IWL<3911> A_IWL<3910> A_IWL<3909> A_IWL<3908> A_IWL<3907> A_IWL<3906> A_IWL<3905> A_IWL<3904> A_IWL<3903> A_IWL<3902> A_IWL<3901> A_IWL<3900> A_IWL<3899> A_IWL<3898> A_IWL<3897> A_IWL<3896> A_IWL<3895> A_IWL<3894> A_IWL<3893> A_IWL<3892> A_IWL<3891> A_IWL<3890> A_IWL<3889> A_IWL<3888> A_IWL<3887> A_IWL<3886> A_IWL<3885> A_IWL<3884> A_IWL<3883> A_IWL<3882> A_IWL<3881> A_IWL<3880> A_IWL<3879> A_IWL<3878> A_IWL<3877> A_IWL<3876> A_IWL<3875> A_IWL<3874> A_IWL<3873> A_IWL<3872> A_IWL<3871> A_IWL<3870> A_IWL<3869> A_IWL<3868> A_IWL<3867> A_IWL<3866> A_IWL<3865> A_IWL<3864> A_IWL<3863> A_IWL<3862> A_IWL<3861> A_IWL<3860> A_IWL<3859> A_IWL<3858> A_IWL<3857> A_IWL<3856> A_IWL<3855> A_IWL<3854> A_IWL<3853> A_IWL<3852> A_IWL<3851> A_IWL<3850> A_IWL<3849> A_IWL<3848> A_IWL<3847> A_IWL<3846> A_IWL<3845> A_IWL<3844> A_IWL<3843> A_IWL<3842> A_IWL<3841> A_IWL<3840> A_IWL<4351> A_IWL<4350> A_IWL<4349> A_IWL<4348> A_IWL<4347> A_IWL<4346> A_IWL<4345> A_IWL<4344> A_IWL<4343> A_IWL<4342> A_IWL<4341> A_IWL<4340> A_IWL<4339> A_IWL<4338> A_IWL<4337> A_IWL<4336> A_IWL<4335> A_IWL<4334> A_IWL<4333> A_IWL<4332> A_IWL<4331> A_IWL<4330> A_IWL<4329> A_IWL<4328> A_IWL<4327> A_IWL<4326> A_IWL<4325> A_IWL<4324> A_IWL<4323> A_IWL<4322> A_IWL<4321> A_IWL<4320> A_IWL<4319> A_IWL<4318> A_IWL<4317> A_IWL<4316> A_IWL<4315> A_IWL<4314> A_IWL<4313> A_IWL<4312> A_IWL<4311> A_IWL<4310> A_IWL<4309> A_IWL<4308> A_IWL<4307> A_IWL<4306> A_IWL<4305> A_IWL<4304> A_IWL<4303> A_IWL<4302> A_IWL<4301> A_IWL<4300> A_IWL<4299> A_IWL<4298> A_IWL<4297> A_IWL<4296> A_IWL<4295> A_IWL<4294> A_IWL<4293> A_IWL<4292> A_IWL<4291> A_IWL<4290> A_IWL<4289> A_IWL<4288> A_IWL<4287> A_IWL<4286> A_IWL<4285> A_IWL<4284> A_IWL<4283> A_IWL<4282> A_IWL<4281> A_IWL<4280> A_IWL<4279> A_IWL<4278> A_IWL<4277> A_IWL<4276> A_IWL<4275> A_IWL<4274> A_IWL<4273> A_IWL<4272> A_IWL<4271> A_IWL<4270> A_IWL<4269> A_IWL<4268> A_IWL<4267> A_IWL<4266> A_IWL<4265> A_IWL<4264> A_IWL<4263> A_IWL<4262> A_IWL<4261> A_IWL<4260> A_IWL<4259> A_IWL<4258> A_IWL<4257> A_IWL<4256> A_IWL<4255> A_IWL<4254> A_IWL<4253> A_IWL<4252> A_IWL<4251> A_IWL<4250> A_IWL<4249> A_IWL<4248> A_IWL<4247> A_IWL<4246> A_IWL<4245> A_IWL<4244> A_IWL<4243> A_IWL<4242> A_IWL<4241> A_IWL<4240> A_IWL<4239> A_IWL<4238> A_IWL<4237> A_IWL<4236> A_IWL<4235> A_IWL<4234> A_IWL<4233> A_IWL<4232> A_IWL<4231> A_IWL<4230> A_IWL<4229> A_IWL<4228> A_IWL<4227> A_IWL<4226> A_IWL<4225> A_IWL<4224> A_IWL<4223> A_IWL<4222> A_IWL<4221> A_IWL<4220> A_IWL<4219> A_IWL<4218> A_IWL<4217> A_IWL<4216> A_IWL<4215> A_IWL<4214> A_IWL<4213> A_IWL<4212> A_IWL<4211> A_IWL<4210> A_IWL<4209> A_IWL<4208> A_IWL<4207> A_IWL<4206> A_IWL<4205> A_IWL<4204> A_IWL<4203> A_IWL<4202> A_IWL<4201> A_IWL<4200> A_IWL<4199> A_IWL<4198> A_IWL<4197> A_IWL<4196> A_IWL<4195> A_IWL<4194> A_IWL<4193> A_IWL<4192> A_IWL<4191> A_IWL<4190> A_IWL<4189> A_IWL<4188> A_IWL<4187> A_IWL<4186> A_IWL<4185> A_IWL<4184> A_IWL<4183> A_IWL<4182> A_IWL<4181> A_IWL<4180> A_IWL<4179> A_IWL<4178> A_IWL<4177> A_IWL<4176> A_IWL<4175> A_IWL<4174> A_IWL<4173> A_IWL<4172> A_IWL<4171> A_IWL<4170> A_IWL<4169> A_IWL<4168> A_IWL<4167> A_IWL<4166> A_IWL<4165> A_IWL<4164> A_IWL<4163> A_IWL<4162> A_IWL<4161> A_IWL<4160> A_IWL<4159> A_IWL<4158> A_IWL<4157> A_IWL<4156> A_IWL<4155> A_IWL<4154> A_IWL<4153> A_IWL<4152> A_IWL<4151> A_IWL<4150> A_IWL<4149> A_IWL<4148> A_IWL<4147> A_IWL<4146> A_IWL<4145> A_IWL<4144> A_IWL<4143> A_IWL<4142> A_IWL<4141> A_IWL<4140> A_IWL<4139> A_IWL<4138> A_IWL<4137> A_IWL<4136> A_IWL<4135> A_IWL<4134> A_IWL<4133> A_IWL<4132> A_IWL<4131> A_IWL<4130> A_IWL<4129> A_IWL<4128> A_IWL<4127> A_IWL<4126> A_IWL<4125> A_IWL<4124> A_IWL<4123> A_IWL<4122> A_IWL<4121> A_IWL<4120> A_IWL<4119> A_IWL<4118> A_IWL<4117> A_IWL<4116> A_IWL<4115> A_IWL<4114> A_IWL<4113> A_IWL<4112> A_IWL<4111> A_IWL<4110> A_IWL<4109> A_IWL<4108> A_IWL<4107> A_IWL<4106> A_IWL<4105> A_IWL<4104> A_IWL<4103> A_IWL<4102> A_IWL<4101> A_IWL<4100> A_IWL<4099> A_IWL<4098> A_IWL<4097> A_IWL<4096> B_BLC<33> B_BLC<32> B_BLC_TOP<33> B_BLC_TOP<32> B_BLT<33> B_BLT<32> B_BLT_TOP<33> B_BLT_TOP<32> B_IWL<4095> B_IWL<4094> B_IWL<4093> B_IWL<4092> B_IWL<4091> B_IWL<4090> B_IWL<4089> B_IWL<4088> B_IWL<4087> B_IWL<4086> B_IWL<4085> B_IWL<4084> B_IWL<4083> B_IWL<4082> B_IWL<4081> B_IWL<4080> B_IWL<4079> B_IWL<4078> B_IWL<4077> B_IWL<4076> B_IWL<4075> B_IWL<4074> B_IWL<4073> B_IWL<4072> B_IWL<4071> B_IWL<4070> B_IWL<4069> B_IWL<4068> B_IWL<4067> B_IWL<4066> B_IWL<4065> B_IWL<4064> B_IWL<4063> B_IWL<4062> B_IWL<4061> B_IWL<4060> B_IWL<4059> B_IWL<4058> B_IWL<4057> B_IWL<4056> B_IWL<4055> B_IWL<4054> B_IWL<4053> B_IWL<4052> B_IWL<4051> B_IWL<4050> B_IWL<4049> B_IWL<4048> B_IWL<4047> B_IWL<4046> B_IWL<4045> B_IWL<4044> B_IWL<4043> B_IWL<4042> B_IWL<4041> B_IWL<4040> B_IWL<4039> B_IWL<4038> B_IWL<4037> B_IWL<4036> B_IWL<4035> B_IWL<4034> B_IWL<4033> B_IWL<4032> B_IWL<4031> B_IWL<4030> B_IWL<4029> B_IWL<4028> B_IWL<4027> B_IWL<4026> B_IWL<4025> B_IWL<4024> B_IWL<4023> B_IWL<4022> B_IWL<4021> B_IWL<4020> B_IWL<4019> B_IWL<4018> B_IWL<4017> B_IWL<4016> B_IWL<4015> B_IWL<4014> B_IWL<4013> B_IWL<4012> B_IWL<4011> B_IWL<4010> B_IWL<4009> B_IWL<4008> B_IWL<4007> B_IWL<4006> B_IWL<4005> B_IWL<4004> B_IWL<4003> B_IWL<4002> B_IWL<4001> B_IWL<4000> B_IWL<3999> B_IWL<3998> B_IWL<3997> B_IWL<3996> B_IWL<3995> B_IWL<3994> B_IWL<3993> B_IWL<3992> B_IWL<3991> B_IWL<3990> B_IWL<3989> B_IWL<3988> B_IWL<3987> B_IWL<3986> B_IWL<3985> B_IWL<3984> B_IWL<3983> B_IWL<3982> B_IWL<3981> B_IWL<3980> B_IWL<3979> B_IWL<3978> B_IWL<3977> B_IWL<3976> B_IWL<3975> B_IWL<3974> B_IWL<3973> B_IWL<3972> B_IWL<3971> B_IWL<3970> B_IWL<3969> B_IWL<3968> B_IWL<3967> B_IWL<3966> B_IWL<3965> B_IWL<3964> B_IWL<3963> B_IWL<3962> B_IWL<3961> B_IWL<3960> B_IWL<3959> B_IWL<3958> B_IWL<3957> B_IWL<3956> B_IWL<3955> B_IWL<3954> B_IWL<3953> B_IWL<3952> B_IWL<3951> B_IWL<3950> B_IWL<3949> B_IWL<3948> B_IWL<3947> B_IWL<3946> B_IWL<3945> B_IWL<3944> B_IWL<3943> B_IWL<3942> B_IWL<3941> B_IWL<3940> B_IWL<3939> B_IWL<3938> B_IWL<3937> B_IWL<3936> B_IWL<3935> B_IWL<3934> B_IWL<3933> B_IWL<3932> B_IWL<3931> B_IWL<3930> B_IWL<3929> B_IWL<3928> B_IWL<3927> B_IWL<3926> B_IWL<3925> B_IWL<3924> B_IWL<3923> B_IWL<3922> B_IWL<3921> B_IWL<3920> B_IWL<3919> B_IWL<3918> B_IWL<3917> B_IWL<3916> B_IWL<3915> B_IWL<3914> B_IWL<3913> B_IWL<3912> B_IWL<3911> B_IWL<3910> B_IWL<3909> B_IWL<3908> B_IWL<3907> B_IWL<3906> B_IWL<3905> B_IWL<3904> B_IWL<3903> B_IWL<3902> B_IWL<3901> B_IWL<3900> B_IWL<3899> B_IWL<3898> B_IWL<3897> B_IWL<3896> B_IWL<3895> B_IWL<3894> B_IWL<3893> B_IWL<3892> B_IWL<3891> B_IWL<3890> B_IWL<3889> B_IWL<3888> B_IWL<3887> B_IWL<3886> B_IWL<3885> B_IWL<3884> B_IWL<3883> B_IWL<3882> B_IWL<3881> B_IWL<3880> B_IWL<3879> B_IWL<3878> B_IWL<3877> B_IWL<3876> B_IWL<3875> B_IWL<3874> B_IWL<3873> B_IWL<3872> B_IWL<3871> B_IWL<3870> B_IWL<3869> B_IWL<3868> B_IWL<3867> B_IWL<3866> B_IWL<3865> B_IWL<3864> B_IWL<3863> B_IWL<3862> B_IWL<3861> B_IWL<3860> B_IWL<3859> B_IWL<3858> B_IWL<3857> B_IWL<3856> B_IWL<3855> B_IWL<3854> B_IWL<3853> B_IWL<3852> B_IWL<3851> B_IWL<3850> B_IWL<3849> B_IWL<3848> B_IWL<3847> B_IWL<3846> B_IWL<3845> B_IWL<3844> B_IWL<3843> B_IWL<3842> B_IWL<3841> B_IWL<3840> B_IWL<4351> B_IWL<4350> B_IWL<4349> B_IWL<4348> B_IWL<4347> B_IWL<4346> B_IWL<4345> B_IWL<4344> B_IWL<4343> B_IWL<4342> B_IWL<4341> B_IWL<4340> B_IWL<4339> B_IWL<4338> B_IWL<4337> B_IWL<4336> B_IWL<4335> B_IWL<4334> B_IWL<4333> B_IWL<4332> B_IWL<4331> B_IWL<4330> B_IWL<4329> B_IWL<4328> B_IWL<4327> B_IWL<4326> B_IWL<4325> B_IWL<4324> B_IWL<4323> B_IWL<4322> B_IWL<4321> B_IWL<4320> B_IWL<4319> B_IWL<4318> B_IWL<4317> B_IWL<4316> B_IWL<4315> B_IWL<4314> B_IWL<4313> B_IWL<4312> B_IWL<4311> B_IWL<4310> B_IWL<4309> B_IWL<4308> B_IWL<4307> B_IWL<4306> B_IWL<4305> B_IWL<4304> B_IWL<4303> B_IWL<4302> B_IWL<4301> B_IWL<4300> B_IWL<4299> B_IWL<4298> B_IWL<4297> B_IWL<4296> B_IWL<4295> B_IWL<4294> B_IWL<4293> B_IWL<4292> B_IWL<4291> B_IWL<4290> B_IWL<4289> B_IWL<4288> B_IWL<4287> B_IWL<4286> B_IWL<4285> B_IWL<4284> B_IWL<4283> B_IWL<4282> B_IWL<4281> B_IWL<4280> B_IWL<4279> B_IWL<4278> B_IWL<4277> B_IWL<4276> B_IWL<4275> B_IWL<4274> B_IWL<4273> B_IWL<4272> B_IWL<4271> B_IWL<4270> B_IWL<4269> B_IWL<4268> B_IWL<4267> B_IWL<4266> B_IWL<4265> B_IWL<4264> B_IWL<4263> B_IWL<4262> B_IWL<4261> B_IWL<4260> B_IWL<4259> B_IWL<4258> B_IWL<4257> B_IWL<4256> B_IWL<4255> B_IWL<4254> B_IWL<4253> B_IWL<4252> B_IWL<4251> B_IWL<4250> B_IWL<4249> B_IWL<4248> B_IWL<4247> B_IWL<4246> B_IWL<4245> B_IWL<4244> B_IWL<4243> B_IWL<4242> B_IWL<4241> B_IWL<4240> B_IWL<4239> B_IWL<4238> B_IWL<4237> B_IWL<4236> B_IWL<4235> B_IWL<4234> B_IWL<4233> B_IWL<4232> B_IWL<4231> B_IWL<4230> B_IWL<4229> B_IWL<4228> B_IWL<4227> B_IWL<4226> B_IWL<4225> B_IWL<4224> B_IWL<4223> B_IWL<4222> B_IWL<4221> B_IWL<4220> B_IWL<4219> B_IWL<4218> B_IWL<4217> B_IWL<4216> B_IWL<4215> B_IWL<4214> B_IWL<4213> B_IWL<4212> B_IWL<4211> B_IWL<4210> B_IWL<4209> B_IWL<4208> B_IWL<4207> B_IWL<4206> B_IWL<4205> B_IWL<4204> B_IWL<4203> B_IWL<4202> B_IWL<4201> B_IWL<4200> B_IWL<4199> B_IWL<4198> B_IWL<4197> B_IWL<4196> B_IWL<4195> B_IWL<4194> B_IWL<4193> B_IWL<4192> B_IWL<4191> B_IWL<4190> B_IWL<4189> B_IWL<4188> B_IWL<4187> B_IWL<4186> B_IWL<4185> B_IWL<4184> B_IWL<4183> B_IWL<4182> B_IWL<4181> B_IWL<4180> B_IWL<4179> B_IWL<4178> B_IWL<4177> B_IWL<4176> B_IWL<4175> B_IWL<4174> B_IWL<4173> B_IWL<4172> B_IWL<4171> B_IWL<4170> B_IWL<4169> B_IWL<4168> B_IWL<4167> B_IWL<4166> B_IWL<4165> B_IWL<4164> B_IWL<4163> B_IWL<4162> B_IWL<4161> B_IWL<4160> B_IWL<4159> B_IWL<4158> B_IWL<4157> B_IWL<4156> B_IWL<4155> B_IWL<4154> B_IWL<4153> B_IWL<4152> B_IWL<4151> B_IWL<4150> B_IWL<4149> B_IWL<4148> B_IWL<4147> B_IWL<4146> B_IWL<4145> B_IWL<4144> B_IWL<4143> B_IWL<4142> B_IWL<4141> B_IWL<4140> B_IWL<4139> B_IWL<4138> B_IWL<4137> B_IWL<4136> B_IWL<4135> B_IWL<4134> B_IWL<4133> B_IWL<4132> B_IWL<4131> B_IWL<4130> B_IWL<4129> B_IWL<4128> B_IWL<4127> B_IWL<4126> B_IWL<4125> B_IWL<4124> B_IWL<4123> B_IWL<4122> B_IWL<4121> B_IWL<4120> B_IWL<4119> B_IWL<4118> B_IWL<4117> B_IWL<4116> B_IWL<4115> B_IWL<4114> B_IWL<4113> B_IWL<4112> B_IWL<4111> B_IWL<4110> B_IWL<4109> B_IWL<4108> B_IWL<4107> B_IWL<4106> B_IWL<4105> B_IWL<4104> B_IWL<4103> B_IWL<4102> B_IWL<4101> B_IWL<4100> B_IWL<4099> B_IWL<4098> B_IWL<4097> B_IWL<4096> VDD_CORE VSS / RM_IHPSG13_1024x32_c2_2P_COLUMN_pcell_0 +XCOL<15> A_BLC<31> A_BLC<30> A_BLC_TOP<31> A_BLC_TOP<30> A_BLT<31> A_BLT<30> A_BLT_TOP<31> A_BLT_TOP<30> A_IWL<3839> A_IWL<3838> A_IWL<3837> A_IWL<3836> A_IWL<3835> A_IWL<3834> A_IWL<3833> A_IWL<3832> A_IWL<3831> A_IWL<3830> A_IWL<3829> A_IWL<3828> A_IWL<3827> A_IWL<3826> A_IWL<3825> A_IWL<3824> A_IWL<3823> A_IWL<3822> A_IWL<3821> A_IWL<3820> A_IWL<3819> A_IWL<3818> A_IWL<3817> A_IWL<3816> A_IWL<3815> A_IWL<3814> A_IWL<3813> A_IWL<3812> A_IWL<3811> A_IWL<3810> A_IWL<3809> A_IWL<3808> A_IWL<3807> A_IWL<3806> A_IWL<3805> A_IWL<3804> A_IWL<3803> A_IWL<3802> A_IWL<3801> A_IWL<3800> A_IWL<3799> A_IWL<3798> A_IWL<3797> A_IWL<3796> A_IWL<3795> A_IWL<3794> A_IWL<3793> A_IWL<3792> A_IWL<3791> A_IWL<3790> A_IWL<3789> A_IWL<3788> A_IWL<3787> A_IWL<3786> A_IWL<3785> A_IWL<3784> A_IWL<3783> A_IWL<3782> A_IWL<3781> A_IWL<3780> A_IWL<3779> A_IWL<3778> A_IWL<3777> A_IWL<3776> A_IWL<3775> A_IWL<3774> A_IWL<3773> A_IWL<3772> A_IWL<3771> A_IWL<3770> A_IWL<3769> A_IWL<3768> A_IWL<3767> A_IWL<3766> A_IWL<3765> A_IWL<3764> A_IWL<3763> A_IWL<3762> A_IWL<3761> A_IWL<3760> A_IWL<3759> A_IWL<3758> A_IWL<3757> A_IWL<3756> A_IWL<3755> A_IWL<3754> A_IWL<3753> A_IWL<3752> A_IWL<3751> A_IWL<3750> A_IWL<3749> A_IWL<3748> A_IWL<3747> A_IWL<3746> A_IWL<3745> A_IWL<3744> A_IWL<3743> A_IWL<3742> A_IWL<3741> A_IWL<3740> A_IWL<3739> A_IWL<3738> A_IWL<3737> A_IWL<3736> A_IWL<3735> A_IWL<3734> A_IWL<3733> A_IWL<3732> A_IWL<3731> A_IWL<3730> A_IWL<3729> A_IWL<3728> A_IWL<3727> A_IWL<3726> A_IWL<3725> A_IWL<3724> A_IWL<3723> A_IWL<3722> A_IWL<3721> A_IWL<3720> A_IWL<3719> A_IWL<3718> A_IWL<3717> A_IWL<3716> A_IWL<3715> A_IWL<3714> A_IWL<3713> A_IWL<3712> A_IWL<3711> A_IWL<3710> A_IWL<3709> A_IWL<3708> A_IWL<3707> A_IWL<3706> A_IWL<3705> A_IWL<3704> A_IWL<3703> A_IWL<3702> A_IWL<3701> A_IWL<3700> A_IWL<3699> A_IWL<3698> A_IWL<3697> A_IWL<3696> A_IWL<3695> A_IWL<3694> A_IWL<3693> A_IWL<3692> A_IWL<3691> A_IWL<3690> A_IWL<3689> A_IWL<3688> A_IWL<3687> A_IWL<3686> A_IWL<3685> A_IWL<3684> A_IWL<3683> A_IWL<3682> A_IWL<3681> A_IWL<3680> A_IWL<3679> A_IWL<3678> A_IWL<3677> A_IWL<3676> A_IWL<3675> A_IWL<3674> A_IWL<3673> A_IWL<3672> A_IWL<3671> A_IWL<3670> A_IWL<3669> A_IWL<3668> A_IWL<3667> A_IWL<3666> A_IWL<3665> A_IWL<3664> A_IWL<3663> A_IWL<3662> A_IWL<3661> A_IWL<3660> A_IWL<3659> A_IWL<3658> A_IWL<3657> A_IWL<3656> A_IWL<3655> A_IWL<3654> A_IWL<3653> A_IWL<3652> A_IWL<3651> A_IWL<3650> A_IWL<3649> A_IWL<3648> A_IWL<3647> A_IWL<3646> A_IWL<3645> A_IWL<3644> A_IWL<3643> A_IWL<3642> A_IWL<3641> A_IWL<3640> A_IWL<3639> A_IWL<3638> A_IWL<3637> A_IWL<3636> A_IWL<3635> A_IWL<3634> A_IWL<3633> A_IWL<3632> A_IWL<3631> A_IWL<3630> A_IWL<3629> A_IWL<3628> A_IWL<3627> A_IWL<3626> A_IWL<3625> A_IWL<3624> A_IWL<3623> A_IWL<3622> A_IWL<3621> A_IWL<3620> A_IWL<3619> A_IWL<3618> A_IWL<3617> A_IWL<3616> A_IWL<3615> A_IWL<3614> A_IWL<3613> A_IWL<3612> A_IWL<3611> A_IWL<3610> A_IWL<3609> A_IWL<3608> A_IWL<3607> A_IWL<3606> A_IWL<3605> A_IWL<3604> A_IWL<3603> A_IWL<3602> A_IWL<3601> A_IWL<3600> A_IWL<3599> A_IWL<3598> A_IWL<3597> A_IWL<3596> A_IWL<3595> A_IWL<3594> A_IWL<3593> A_IWL<3592> A_IWL<3591> A_IWL<3590> A_IWL<3589> A_IWL<3588> A_IWL<3587> A_IWL<3586> A_IWL<3585> A_IWL<3584> A_IWL<4095> A_IWL<4094> A_IWL<4093> A_IWL<4092> A_IWL<4091> A_IWL<4090> A_IWL<4089> A_IWL<4088> A_IWL<4087> A_IWL<4086> A_IWL<4085> A_IWL<4084> A_IWL<4083> A_IWL<4082> A_IWL<4081> A_IWL<4080> A_IWL<4079> A_IWL<4078> A_IWL<4077> A_IWL<4076> A_IWL<4075> A_IWL<4074> A_IWL<4073> A_IWL<4072> A_IWL<4071> A_IWL<4070> A_IWL<4069> A_IWL<4068> A_IWL<4067> A_IWL<4066> A_IWL<4065> A_IWL<4064> A_IWL<4063> A_IWL<4062> A_IWL<4061> A_IWL<4060> A_IWL<4059> A_IWL<4058> A_IWL<4057> A_IWL<4056> A_IWL<4055> A_IWL<4054> A_IWL<4053> A_IWL<4052> A_IWL<4051> A_IWL<4050> A_IWL<4049> A_IWL<4048> A_IWL<4047> A_IWL<4046> A_IWL<4045> A_IWL<4044> A_IWL<4043> A_IWL<4042> A_IWL<4041> A_IWL<4040> A_IWL<4039> A_IWL<4038> A_IWL<4037> A_IWL<4036> A_IWL<4035> A_IWL<4034> A_IWL<4033> A_IWL<4032> A_IWL<4031> A_IWL<4030> A_IWL<4029> A_IWL<4028> A_IWL<4027> A_IWL<4026> A_IWL<4025> A_IWL<4024> A_IWL<4023> A_IWL<4022> A_IWL<4021> A_IWL<4020> A_IWL<4019> A_IWL<4018> A_IWL<4017> A_IWL<4016> A_IWL<4015> A_IWL<4014> A_IWL<4013> A_IWL<4012> A_IWL<4011> A_IWL<4010> A_IWL<4009> A_IWL<4008> A_IWL<4007> A_IWL<4006> A_IWL<4005> A_IWL<4004> A_IWL<4003> A_IWL<4002> A_IWL<4001> A_IWL<4000> A_IWL<3999> A_IWL<3998> A_IWL<3997> A_IWL<3996> A_IWL<3995> A_IWL<3994> A_IWL<3993> A_IWL<3992> A_IWL<3991> A_IWL<3990> A_IWL<3989> A_IWL<3988> A_IWL<3987> A_IWL<3986> A_IWL<3985> A_IWL<3984> A_IWL<3983> A_IWL<3982> A_IWL<3981> A_IWL<3980> A_IWL<3979> A_IWL<3978> A_IWL<3977> A_IWL<3976> A_IWL<3975> A_IWL<3974> A_IWL<3973> A_IWL<3972> A_IWL<3971> A_IWL<3970> A_IWL<3969> A_IWL<3968> A_IWL<3967> A_IWL<3966> A_IWL<3965> A_IWL<3964> A_IWL<3963> A_IWL<3962> A_IWL<3961> A_IWL<3960> A_IWL<3959> A_IWL<3958> A_IWL<3957> A_IWL<3956> A_IWL<3955> A_IWL<3954> A_IWL<3953> A_IWL<3952> A_IWL<3951> A_IWL<3950> A_IWL<3949> A_IWL<3948> A_IWL<3947> A_IWL<3946> A_IWL<3945> A_IWL<3944> A_IWL<3943> A_IWL<3942> A_IWL<3941> A_IWL<3940> A_IWL<3939> A_IWL<3938> A_IWL<3937> A_IWL<3936> A_IWL<3935> A_IWL<3934> A_IWL<3933> A_IWL<3932> A_IWL<3931> A_IWL<3930> A_IWL<3929> A_IWL<3928> A_IWL<3927> A_IWL<3926> A_IWL<3925> A_IWL<3924> A_IWL<3923> A_IWL<3922> A_IWL<3921> A_IWL<3920> A_IWL<3919> A_IWL<3918> A_IWL<3917> A_IWL<3916> A_IWL<3915> A_IWL<3914> A_IWL<3913> A_IWL<3912> A_IWL<3911> A_IWL<3910> A_IWL<3909> A_IWL<3908> A_IWL<3907> A_IWL<3906> A_IWL<3905> A_IWL<3904> A_IWL<3903> A_IWL<3902> A_IWL<3901> A_IWL<3900> A_IWL<3899> A_IWL<3898> A_IWL<3897> A_IWL<3896> A_IWL<3895> A_IWL<3894> A_IWL<3893> A_IWL<3892> A_IWL<3891> A_IWL<3890> A_IWL<3889> A_IWL<3888> A_IWL<3887> A_IWL<3886> A_IWL<3885> A_IWL<3884> A_IWL<3883> A_IWL<3882> A_IWL<3881> A_IWL<3880> A_IWL<3879> A_IWL<3878> A_IWL<3877> A_IWL<3876> A_IWL<3875> A_IWL<3874> A_IWL<3873> A_IWL<3872> A_IWL<3871> A_IWL<3870> A_IWL<3869> A_IWL<3868> A_IWL<3867> A_IWL<3866> A_IWL<3865> A_IWL<3864> A_IWL<3863> A_IWL<3862> A_IWL<3861> A_IWL<3860> A_IWL<3859> A_IWL<3858> A_IWL<3857> A_IWL<3856> A_IWL<3855> A_IWL<3854> A_IWL<3853> A_IWL<3852> A_IWL<3851> A_IWL<3850> A_IWL<3849> A_IWL<3848> A_IWL<3847> A_IWL<3846> A_IWL<3845> A_IWL<3844> A_IWL<3843> A_IWL<3842> A_IWL<3841> A_IWL<3840> B_BLC<31> B_BLC<30> B_BLC_TOP<31> B_BLC_TOP<30> B_BLT<31> B_BLT<30> B_BLT_TOP<31> B_BLT_TOP<30> B_IWL<3839> B_IWL<3838> B_IWL<3837> B_IWL<3836> B_IWL<3835> B_IWL<3834> B_IWL<3833> B_IWL<3832> B_IWL<3831> B_IWL<3830> B_IWL<3829> B_IWL<3828> B_IWL<3827> B_IWL<3826> B_IWL<3825> B_IWL<3824> B_IWL<3823> B_IWL<3822> B_IWL<3821> B_IWL<3820> B_IWL<3819> B_IWL<3818> B_IWL<3817> B_IWL<3816> B_IWL<3815> B_IWL<3814> B_IWL<3813> B_IWL<3812> B_IWL<3811> B_IWL<3810> B_IWL<3809> B_IWL<3808> B_IWL<3807> B_IWL<3806> B_IWL<3805> B_IWL<3804> B_IWL<3803> B_IWL<3802> B_IWL<3801> B_IWL<3800> B_IWL<3799> B_IWL<3798> B_IWL<3797> B_IWL<3796> B_IWL<3795> B_IWL<3794> B_IWL<3793> B_IWL<3792> B_IWL<3791> B_IWL<3790> B_IWL<3789> B_IWL<3788> B_IWL<3787> B_IWL<3786> B_IWL<3785> B_IWL<3784> B_IWL<3783> B_IWL<3782> B_IWL<3781> B_IWL<3780> B_IWL<3779> B_IWL<3778> B_IWL<3777> B_IWL<3776> B_IWL<3775> B_IWL<3774> B_IWL<3773> B_IWL<3772> B_IWL<3771> B_IWL<3770> B_IWL<3769> B_IWL<3768> B_IWL<3767> B_IWL<3766> B_IWL<3765> B_IWL<3764> B_IWL<3763> B_IWL<3762> B_IWL<3761> B_IWL<3760> B_IWL<3759> B_IWL<3758> B_IWL<3757> B_IWL<3756> B_IWL<3755> B_IWL<3754> B_IWL<3753> B_IWL<3752> B_IWL<3751> B_IWL<3750> B_IWL<3749> B_IWL<3748> B_IWL<3747> B_IWL<3746> B_IWL<3745> B_IWL<3744> B_IWL<3743> B_IWL<3742> B_IWL<3741> B_IWL<3740> B_IWL<3739> B_IWL<3738> B_IWL<3737> B_IWL<3736> B_IWL<3735> B_IWL<3734> B_IWL<3733> B_IWL<3732> B_IWL<3731> B_IWL<3730> B_IWL<3729> B_IWL<3728> B_IWL<3727> B_IWL<3726> B_IWL<3725> B_IWL<3724> B_IWL<3723> B_IWL<3722> B_IWL<3721> B_IWL<3720> B_IWL<3719> B_IWL<3718> B_IWL<3717> B_IWL<3716> B_IWL<3715> B_IWL<3714> B_IWL<3713> B_IWL<3712> B_IWL<3711> B_IWL<3710> B_IWL<3709> B_IWL<3708> B_IWL<3707> B_IWL<3706> B_IWL<3705> B_IWL<3704> B_IWL<3703> B_IWL<3702> B_IWL<3701> B_IWL<3700> B_IWL<3699> B_IWL<3698> B_IWL<3697> B_IWL<3696> B_IWL<3695> B_IWL<3694> B_IWL<3693> B_IWL<3692> B_IWL<3691> B_IWL<3690> B_IWL<3689> B_IWL<3688> B_IWL<3687> B_IWL<3686> B_IWL<3685> B_IWL<3684> B_IWL<3683> B_IWL<3682> B_IWL<3681> B_IWL<3680> B_IWL<3679> B_IWL<3678> B_IWL<3677> B_IWL<3676> B_IWL<3675> B_IWL<3674> B_IWL<3673> B_IWL<3672> B_IWL<3671> B_IWL<3670> B_IWL<3669> B_IWL<3668> B_IWL<3667> B_IWL<3666> B_IWL<3665> B_IWL<3664> B_IWL<3663> B_IWL<3662> B_IWL<3661> B_IWL<3660> B_IWL<3659> B_IWL<3658> B_IWL<3657> B_IWL<3656> B_IWL<3655> B_IWL<3654> B_IWL<3653> B_IWL<3652> B_IWL<3651> B_IWL<3650> B_IWL<3649> B_IWL<3648> B_IWL<3647> B_IWL<3646> B_IWL<3645> B_IWL<3644> B_IWL<3643> B_IWL<3642> B_IWL<3641> B_IWL<3640> B_IWL<3639> B_IWL<3638> B_IWL<3637> B_IWL<3636> B_IWL<3635> B_IWL<3634> B_IWL<3633> B_IWL<3632> B_IWL<3631> B_IWL<3630> B_IWL<3629> B_IWL<3628> B_IWL<3627> B_IWL<3626> B_IWL<3625> B_IWL<3624> B_IWL<3623> B_IWL<3622> B_IWL<3621> B_IWL<3620> B_IWL<3619> B_IWL<3618> B_IWL<3617> B_IWL<3616> B_IWL<3615> B_IWL<3614> B_IWL<3613> B_IWL<3612> B_IWL<3611> B_IWL<3610> B_IWL<3609> B_IWL<3608> B_IWL<3607> B_IWL<3606> B_IWL<3605> B_IWL<3604> B_IWL<3603> B_IWL<3602> B_IWL<3601> B_IWL<3600> B_IWL<3599> B_IWL<3598> B_IWL<3597> B_IWL<3596> B_IWL<3595> B_IWL<3594> B_IWL<3593> B_IWL<3592> B_IWL<3591> B_IWL<3590> B_IWL<3589> B_IWL<3588> B_IWL<3587> B_IWL<3586> B_IWL<3585> B_IWL<3584> B_IWL<4095> B_IWL<4094> B_IWL<4093> B_IWL<4092> B_IWL<4091> B_IWL<4090> B_IWL<4089> B_IWL<4088> B_IWL<4087> B_IWL<4086> B_IWL<4085> B_IWL<4084> B_IWL<4083> B_IWL<4082> B_IWL<4081> B_IWL<4080> B_IWL<4079> B_IWL<4078> B_IWL<4077> B_IWL<4076> B_IWL<4075> B_IWL<4074> B_IWL<4073> B_IWL<4072> B_IWL<4071> B_IWL<4070> B_IWL<4069> B_IWL<4068> B_IWL<4067> B_IWL<4066> B_IWL<4065> B_IWL<4064> B_IWL<4063> B_IWL<4062> B_IWL<4061> B_IWL<4060> B_IWL<4059> B_IWL<4058> B_IWL<4057> B_IWL<4056> B_IWL<4055> B_IWL<4054> B_IWL<4053> B_IWL<4052> B_IWL<4051> B_IWL<4050> B_IWL<4049> B_IWL<4048> B_IWL<4047> B_IWL<4046> B_IWL<4045> B_IWL<4044> B_IWL<4043> B_IWL<4042> B_IWL<4041> B_IWL<4040> B_IWL<4039> B_IWL<4038> B_IWL<4037> B_IWL<4036> B_IWL<4035> B_IWL<4034> B_IWL<4033> B_IWL<4032> B_IWL<4031> B_IWL<4030> B_IWL<4029> B_IWL<4028> B_IWL<4027> B_IWL<4026> B_IWL<4025> B_IWL<4024> B_IWL<4023> B_IWL<4022> B_IWL<4021> B_IWL<4020> B_IWL<4019> B_IWL<4018> B_IWL<4017> B_IWL<4016> B_IWL<4015> B_IWL<4014> B_IWL<4013> B_IWL<4012> B_IWL<4011> B_IWL<4010> B_IWL<4009> B_IWL<4008> B_IWL<4007> B_IWL<4006> B_IWL<4005> B_IWL<4004> B_IWL<4003> B_IWL<4002> B_IWL<4001> B_IWL<4000> B_IWL<3999> B_IWL<3998> B_IWL<3997> B_IWL<3996> B_IWL<3995> B_IWL<3994> B_IWL<3993> B_IWL<3992> B_IWL<3991> B_IWL<3990> B_IWL<3989> B_IWL<3988> B_IWL<3987> B_IWL<3986> B_IWL<3985> B_IWL<3984> B_IWL<3983> B_IWL<3982> B_IWL<3981> B_IWL<3980> B_IWL<3979> B_IWL<3978> B_IWL<3977> B_IWL<3976> B_IWL<3975> B_IWL<3974> B_IWL<3973> B_IWL<3972> B_IWL<3971> B_IWL<3970> B_IWL<3969> B_IWL<3968> B_IWL<3967> B_IWL<3966> B_IWL<3965> B_IWL<3964> B_IWL<3963> B_IWL<3962> B_IWL<3961> B_IWL<3960> B_IWL<3959> B_IWL<3958> B_IWL<3957> B_IWL<3956> B_IWL<3955> B_IWL<3954> B_IWL<3953> B_IWL<3952> B_IWL<3951> B_IWL<3950> B_IWL<3949> B_IWL<3948> B_IWL<3947> B_IWL<3946> B_IWL<3945> B_IWL<3944> B_IWL<3943> B_IWL<3942> B_IWL<3941> B_IWL<3940> B_IWL<3939> B_IWL<3938> B_IWL<3937> B_IWL<3936> B_IWL<3935> B_IWL<3934> B_IWL<3933> B_IWL<3932> B_IWL<3931> B_IWL<3930> B_IWL<3929> B_IWL<3928> B_IWL<3927> B_IWL<3926> B_IWL<3925> B_IWL<3924> B_IWL<3923> B_IWL<3922> B_IWL<3921> B_IWL<3920> B_IWL<3919> B_IWL<3918> B_IWL<3917> B_IWL<3916> B_IWL<3915> B_IWL<3914> B_IWL<3913> B_IWL<3912> B_IWL<3911> B_IWL<3910> B_IWL<3909> B_IWL<3908> B_IWL<3907> B_IWL<3906> B_IWL<3905> B_IWL<3904> B_IWL<3903> B_IWL<3902> B_IWL<3901> B_IWL<3900> B_IWL<3899> B_IWL<3898> B_IWL<3897> B_IWL<3896> B_IWL<3895> B_IWL<3894> B_IWL<3893> B_IWL<3892> B_IWL<3891> B_IWL<3890> B_IWL<3889> B_IWL<3888> B_IWL<3887> B_IWL<3886> B_IWL<3885> B_IWL<3884> B_IWL<3883> B_IWL<3882> B_IWL<3881> B_IWL<3880> B_IWL<3879> B_IWL<3878> B_IWL<3877> B_IWL<3876> B_IWL<3875> B_IWL<3874> B_IWL<3873> B_IWL<3872> B_IWL<3871> B_IWL<3870> B_IWL<3869> B_IWL<3868> B_IWL<3867> B_IWL<3866> B_IWL<3865> B_IWL<3864> B_IWL<3863> B_IWL<3862> B_IWL<3861> B_IWL<3860> B_IWL<3859> B_IWL<3858> B_IWL<3857> B_IWL<3856> B_IWL<3855> B_IWL<3854> B_IWL<3853> B_IWL<3852> B_IWL<3851> B_IWL<3850> B_IWL<3849> B_IWL<3848> B_IWL<3847> B_IWL<3846> B_IWL<3845> B_IWL<3844> B_IWL<3843> B_IWL<3842> B_IWL<3841> B_IWL<3840> VDD_CORE VSS / RM_IHPSG13_1024x32_c2_2P_COLUMN_pcell_0 +XCOL<14> A_BLC<29> A_BLC<28> A_BLC_TOP<29> A_BLC_TOP<28> A_BLT<29> A_BLT<28> A_BLT_TOP<29> A_BLT_TOP<28> A_IWL<3583> A_IWL<3582> A_IWL<3581> A_IWL<3580> A_IWL<3579> A_IWL<3578> A_IWL<3577> A_IWL<3576> A_IWL<3575> A_IWL<3574> A_IWL<3573> A_IWL<3572> A_IWL<3571> A_IWL<3570> A_IWL<3569> A_IWL<3568> A_IWL<3567> A_IWL<3566> A_IWL<3565> A_IWL<3564> A_IWL<3563> A_IWL<3562> A_IWL<3561> A_IWL<3560> A_IWL<3559> A_IWL<3558> A_IWL<3557> A_IWL<3556> A_IWL<3555> A_IWL<3554> A_IWL<3553> A_IWL<3552> A_IWL<3551> A_IWL<3550> A_IWL<3549> A_IWL<3548> A_IWL<3547> A_IWL<3546> A_IWL<3545> A_IWL<3544> A_IWL<3543> A_IWL<3542> A_IWL<3541> A_IWL<3540> A_IWL<3539> A_IWL<3538> A_IWL<3537> A_IWL<3536> A_IWL<3535> A_IWL<3534> A_IWL<3533> A_IWL<3532> A_IWL<3531> A_IWL<3530> A_IWL<3529> A_IWL<3528> A_IWL<3527> A_IWL<3526> A_IWL<3525> A_IWL<3524> A_IWL<3523> A_IWL<3522> A_IWL<3521> A_IWL<3520> A_IWL<3519> A_IWL<3518> A_IWL<3517> A_IWL<3516> A_IWL<3515> A_IWL<3514> A_IWL<3513> A_IWL<3512> A_IWL<3511> A_IWL<3510> A_IWL<3509> A_IWL<3508> A_IWL<3507> A_IWL<3506> A_IWL<3505> A_IWL<3504> A_IWL<3503> A_IWL<3502> A_IWL<3501> A_IWL<3500> A_IWL<3499> A_IWL<3498> A_IWL<3497> A_IWL<3496> A_IWL<3495> A_IWL<3494> A_IWL<3493> A_IWL<3492> A_IWL<3491> A_IWL<3490> A_IWL<3489> A_IWL<3488> A_IWL<3487> A_IWL<3486> A_IWL<3485> A_IWL<3484> A_IWL<3483> A_IWL<3482> A_IWL<3481> A_IWL<3480> A_IWL<3479> A_IWL<3478> A_IWL<3477> A_IWL<3476> A_IWL<3475> A_IWL<3474> A_IWL<3473> A_IWL<3472> A_IWL<3471> A_IWL<3470> A_IWL<3469> A_IWL<3468> A_IWL<3467> A_IWL<3466> A_IWL<3465> A_IWL<3464> A_IWL<3463> A_IWL<3462> A_IWL<3461> A_IWL<3460> A_IWL<3459> A_IWL<3458> A_IWL<3457> A_IWL<3456> A_IWL<3455> A_IWL<3454> A_IWL<3453> A_IWL<3452> A_IWL<3451> A_IWL<3450> A_IWL<3449> A_IWL<3448> A_IWL<3447> A_IWL<3446> A_IWL<3445> A_IWL<3444> A_IWL<3443> A_IWL<3442> A_IWL<3441> A_IWL<3440> A_IWL<3439> A_IWL<3438> A_IWL<3437> A_IWL<3436> A_IWL<3435> A_IWL<3434> A_IWL<3433> A_IWL<3432> A_IWL<3431> A_IWL<3430> A_IWL<3429> A_IWL<3428> A_IWL<3427> A_IWL<3426> A_IWL<3425> A_IWL<3424> A_IWL<3423> A_IWL<3422> A_IWL<3421> A_IWL<3420> A_IWL<3419> A_IWL<3418> A_IWL<3417> A_IWL<3416> A_IWL<3415> A_IWL<3414> A_IWL<3413> A_IWL<3412> A_IWL<3411> A_IWL<3410> A_IWL<3409> A_IWL<3408> A_IWL<3407> A_IWL<3406> A_IWL<3405> A_IWL<3404> A_IWL<3403> A_IWL<3402> A_IWL<3401> A_IWL<3400> A_IWL<3399> A_IWL<3398> A_IWL<3397> A_IWL<3396> A_IWL<3395> A_IWL<3394> A_IWL<3393> A_IWL<3392> A_IWL<3391> A_IWL<3390> A_IWL<3389> A_IWL<3388> A_IWL<3387> A_IWL<3386> A_IWL<3385> A_IWL<3384> A_IWL<3383> A_IWL<3382> A_IWL<3381> A_IWL<3380> A_IWL<3379> A_IWL<3378> A_IWL<3377> A_IWL<3376> A_IWL<3375> A_IWL<3374> A_IWL<3373> A_IWL<3372> A_IWL<3371> A_IWL<3370> A_IWL<3369> A_IWL<3368> A_IWL<3367> A_IWL<3366> A_IWL<3365> A_IWL<3364> A_IWL<3363> A_IWL<3362> A_IWL<3361> A_IWL<3360> A_IWL<3359> A_IWL<3358> A_IWL<3357> A_IWL<3356> A_IWL<3355> A_IWL<3354> A_IWL<3353> A_IWL<3352> A_IWL<3351> A_IWL<3350> A_IWL<3349> A_IWL<3348> A_IWL<3347> A_IWL<3346> A_IWL<3345> A_IWL<3344> A_IWL<3343> A_IWL<3342> A_IWL<3341> A_IWL<3340> A_IWL<3339> A_IWL<3338> A_IWL<3337> A_IWL<3336> A_IWL<3335> A_IWL<3334> A_IWL<3333> A_IWL<3332> A_IWL<3331> A_IWL<3330> A_IWL<3329> A_IWL<3328> A_IWL<3839> A_IWL<3838> A_IWL<3837> A_IWL<3836> A_IWL<3835> A_IWL<3834> A_IWL<3833> A_IWL<3832> A_IWL<3831> A_IWL<3830> A_IWL<3829> A_IWL<3828> A_IWL<3827> A_IWL<3826> A_IWL<3825> A_IWL<3824> A_IWL<3823> A_IWL<3822> A_IWL<3821> A_IWL<3820> A_IWL<3819> A_IWL<3818> A_IWL<3817> A_IWL<3816> A_IWL<3815> A_IWL<3814> A_IWL<3813> A_IWL<3812> A_IWL<3811> A_IWL<3810> A_IWL<3809> A_IWL<3808> A_IWL<3807> A_IWL<3806> A_IWL<3805> A_IWL<3804> A_IWL<3803> A_IWL<3802> A_IWL<3801> A_IWL<3800> A_IWL<3799> A_IWL<3798> A_IWL<3797> A_IWL<3796> A_IWL<3795> A_IWL<3794> A_IWL<3793> A_IWL<3792> A_IWL<3791> A_IWL<3790> A_IWL<3789> A_IWL<3788> A_IWL<3787> A_IWL<3786> A_IWL<3785> A_IWL<3784> A_IWL<3783> A_IWL<3782> A_IWL<3781> A_IWL<3780> A_IWL<3779> A_IWL<3778> A_IWL<3777> A_IWL<3776> A_IWL<3775> A_IWL<3774> A_IWL<3773> A_IWL<3772> A_IWL<3771> A_IWL<3770> A_IWL<3769> A_IWL<3768> A_IWL<3767> A_IWL<3766> A_IWL<3765> A_IWL<3764> A_IWL<3763> A_IWL<3762> A_IWL<3761> A_IWL<3760> A_IWL<3759> A_IWL<3758> A_IWL<3757> A_IWL<3756> A_IWL<3755> A_IWL<3754> A_IWL<3753> A_IWL<3752> A_IWL<3751> A_IWL<3750> A_IWL<3749> A_IWL<3748> A_IWL<3747> A_IWL<3746> A_IWL<3745> A_IWL<3744> A_IWL<3743> A_IWL<3742> A_IWL<3741> A_IWL<3740> A_IWL<3739> A_IWL<3738> A_IWL<3737> A_IWL<3736> A_IWL<3735> A_IWL<3734> A_IWL<3733> A_IWL<3732> A_IWL<3731> A_IWL<3730> A_IWL<3729> A_IWL<3728> A_IWL<3727> A_IWL<3726> A_IWL<3725> A_IWL<3724> A_IWL<3723> A_IWL<3722> A_IWL<3721> A_IWL<3720> A_IWL<3719> A_IWL<3718> A_IWL<3717> A_IWL<3716> A_IWL<3715> A_IWL<3714> A_IWL<3713> A_IWL<3712> A_IWL<3711> A_IWL<3710> A_IWL<3709> A_IWL<3708> A_IWL<3707> A_IWL<3706> A_IWL<3705> A_IWL<3704> A_IWL<3703> A_IWL<3702> A_IWL<3701> A_IWL<3700> A_IWL<3699> A_IWL<3698> A_IWL<3697> A_IWL<3696> A_IWL<3695> A_IWL<3694> A_IWL<3693> A_IWL<3692> A_IWL<3691> A_IWL<3690> A_IWL<3689> A_IWL<3688> A_IWL<3687> A_IWL<3686> A_IWL<3685> A_IWL<3684> A_IWL<3683> A_IWL<3682> A_IWL<3681> A_IWL<3680> A_IWL<3679> A_IWL<3678> A_IWL<3677> A_IWL<3676> A_IWL<3675> A_IWL<3674> A_IWL<3673> A_IWL<3672> A_IWL<3671> A_IWL<3670> A_IWL<3669> A_IWL<3668> A_IWL<3667> A_IWL<3666> A_IWL<3665> A_IWL<3664> A_IWL<3663> A_IWL<3662> A_IWL<3661> A_IWL<3660> A_IWL<3659> A_IWL<3658> A_IWL<3657> A_IWL<3656> A_IWL<3655> A_IWL<3654> A_IWL<3653> A_IWL<3652> A_IWL<3651> A_IWL<3650> A_IWL<3649> A_IWL<3648> A_IWL<3647> A_IWL<3646> A_IWL<3645> A_IWL<3644> A_IWL<3643> A_IWL<3642> A_IWL<3641> A_IWL<3640> A_IWL<3639> A_IWL<3638> A_IWL<3637> A_IWL<3636> A_IWL<3635> A_IWL<3634> A_IWL<3633> A_IWL<3632> A_IWL<3631> A_IWL<3630> A_IWL<3629> A_IWL<3628> A_IWL<3627> A_IWL<3626> A_IWL<3625> A_IWL<3624> A_IWL<3623> A_IWL<3622> A_IWL<3621> A_IWL<3620> A_IWL<3619> A_IWL<3618> A_IWL<3617> A_IWL<3616> A_IWL<3615> A_IWL<3614> A_IWL<3613> A_IWL<3612> A_IWL<3611> A_IWL<3610> A_IWL<3609> A_IWL<3608> A_IWL<3607> A_IWL<3606> A_IWL<3605> A_IWL<3604> A_IWL<3603> A_IWL<3602> A_IWL<3601> A_IWL<3600> A_IWL<3599> A_IWL<3598> A_IWL<3597> A_IWL<3596> A_IWL<3595> A_IWL<3594> A_IWL<3593> A_IWL<3592> A_IWL<3591> A_IWL<3590> A_IWL<3589> A_IWL<3588> A_IWL<3587> A_IWL<3586> A_IWL<3585> A_IWL<3584> B_BLC<29> B_BLC<28> B_BLC_TOP<29> B_BLC_TOP<28> B_BLT<29> B_BLT<28> B_BLT_TOP<29> B_BLT_TOP<28> B_IWL<3583> B_IWL<3582> B_IWL<3581> B_IWL<3580> B_IWL<3579> B_IWL<3578> B_IWL<3577> B_IWL<3576> B_IWL<3575> B_IWL<3574> B_IWL<3573> B_IWL<3572> B_IWL<3571> B_IWL<3570> B_IWL<3569> B_IWL<3568> B_IWL<3567> B_IWL<3566> B_IWL<3565> B_IWL<3564> B_IWL<3563> B_IWL<3562> B_IWL<3561> B_IWL<3560> B_IWL<3559> B_IWL<3558> B_IWL<3557> B_IWL<3556> B_IWL<3555> B_IWL<3554> B_IWL<3553> B_IWL<3552> B_IWL<3551> B_IWL<3550> B_IWL<3549> B_IWL<3548> B_IWL<3547> B_IWL<3546> B_IWL<3545> B_IWL<3544> B_IWL<3543> B_IWL<3542> B_IWL<3541> B_IWL<3540> B_IWL<3539> B_IWL<3538> B_IWL<3537> B_IWL<3536> B_IWL<3535> B_IWL<3534> B_IWL<3533> B_IWL<3532> B_IWL<3531> B_IWL<3530> B_IWL<3529> B_IWL<3528> B_IWL<3527> B_IWL<3526> B_IWL<3525> B_IWL<3524> B_IWL<3523> B_IWL<3522> B_IWL<3521> B_IWL<3520> B_IWL<3519> B_IWL<3518> B_IWL<3517> B_IWL<3516> B_IWL<3515> B_IWL<3514> B_IWL<3513> B_IWL<3512> B_IWL<3511> B_IWL<3510> B_IWL<3509> B_IWL<3508> B_IWL<3507> B_IWL<3506> B_IWL<3505> B_IWL<3504> B_IWL<3503> B_IWL<3502> B_IWL<3501> B_IWL<3500> B_IWL<3499> B_IWL<3498> B_IWL<3497> B_IWL<3496> B_IWL<3495> B_IWL<3494> B_IWL<3493> B_IWL<3492> B_IWL<3491> B_IWL<3490> B_IWL<3489> B_IWL<3488> B_IWL<3487> B_IWL<3486> B_IWL<3485> B_IWL<3484> B_IWL<3483> B_IWL<3482> B_IWL<3481> B_IWL<3480> B_IWL<3479> B_IWL<3478> B_IWL<3477> B_IWL<3476> B_IWL<3475> B_IWL<3474> B_IWL<3473> B_IWL<3472> B_IWL<3471> B_IWL<3470> B_IWL<3469> B_IWL<3468> B_IWL<3467> B_IWL<3466> B_IWL<3465> B_IWL<3464> B_IWL<3463> B_IWL<3462> B_IWL<3461> B_IWL<3460> B_IWL<3459> B_IWL<3458> B_IWL<3457> B_IWL<3456> B_IWL<3455> B_IWL<3454> B_IWL<3453> B_IWL<3452> B_IWL<3451> B_IWL<3450> B_IWL<3449> B_IWL<3448> B_IWL<3447> B_IWL<3446> B_IWL<3445> B_IWL<3444> B_IWL<3443> B_IWL<3442> B_IWL<3441> B_IWL<3440> B_IWL<3439> B_IWL<3438> B_IWL<3437> B_IWL<3436> B_IWL<3435> B_IWL<3434> B_IWL<3433> B_IWL<3432> B_IWL<3431> B_IWL<3430> B_IWL<3429> B_IWL<3428> B_IWL<3427> B_IWL<3426> B_IWL<3425> B_IWL<3424> B_IWL<3423> B_IWL<3422> B_IWL<3421> B_IWL<3420> B_IWL<3419> B_IWL<3418> B_IWL<3417> B_IWL<3416> B_IWL<3415> B_IWL<3414> B_IWL<3413> B_IWL<3412> B_IWL<3411> B_IWL<3410> B_IWL<3409> B_IWL<3408> B_IWL<3407> B_IWL<3406> B_IWL<3405> B_IWL<3404> B_IWL<3403> B_IWL<3402> B_IWL<3401> B_IWL<3400> B_IWL<3399> B_IWL<3398> B_IWL<3397> B_IWL<3396> B_IWL<3395> B_IWL<3394> B_IWL<3393> B_IWL<3392> B_IWL<3391> B_IWL<3390> B_IWL<3389> B_IWL<3388> B_IWL<3387> B_IWL<3386> B_IWL<3385> B_IWL<3384> B_IWL<3383> B_IWL<3382> B_IWL<3381> B_IWL<3380> B_IWL<3379> B_IWL<3378> B_IWL<3377> B_IWL<3376> B_IWL<3375> B_IWL<3374> B_IWL<3373> B_IWL<3372> B_IWL<3371> B_IWL<3370> B_IWL<3369> B_IWL<3368> B_IWL<3367> B_IWL<3366> B_IWL<3365> B_IWL<3364> B_IWL<3363> B_IWL<3362> B_IWL<3361> B_IWL<3360> B_IWL<3359> B_IWL<3358> B_IWL<3357> B_IWL<3356> B_IWL<3355> B_IWL<3354> B_IWL<3353> B_IWL<3352> B_IWL<3351> B_IWL<3350> B_IWL<3349> B_IWL<3348> B_IWL<3347> B_IWL<3346> B_IWL<3345> B_IWL<3344> B_IWL<3343> B_IWL<3342> B_IWL<3341> B_IWL<3340> B_IWL<3339> B_IWL<3338> B_IWL<3337> B_IWL<3336> B_IWL<3335> B_IWL<3334> B_IWL<3333> B_IWL<3332> B_IWL<3331> B_IWL<3330> B_IWL<3329> B_IWL<3328> B_IWL<3839> B_IWL<3838> B_IWL<3837> B_IWL<3836> B_IWL<3835> B_IWL<3834> B_IWL<3833> B_IWL<3832> B_IWL<3831> B_IWL<3830> B_IWL<3829> B_IWL<3828> B_IWL<3827> B_IWL<3826> B_IWL<3825> B_IWL<3824> B_IWL<3823> B_IWL<3822> B_IWL<3821> B_IWL<3820> B_IWL<3819> B_IWL<3818> B_IWL<3817> B_IWL<3816> B_IWL<3815> B_IWL<3814> B_IWL<3813> B_IWL<3812> B_IWL<3811> B_IWL<3810> B_IWL<3809> B_IWL<3808> B_IWL<3807> B_IWL<3806> B_IWL<3805> B_IWL<3804> B_IWL<3803> B_IWL<3802> B_IWL<3801> B_IWL<3800> B_IWL<3799> B_IWL<3798> B_IWL<3797> B_IWL<3796> B_IWL<3795> B_IWL<3794> B_IWL<3793> B_IWL<3792> B_IWL<3791> B_IWL<3790> B_IWL<3789> B_IWL<3788> B_IWL<3787> B_IWL<3786> B_IWL<3785> B_IWL<3784> B_IWL<3783> B_IWL<3782> B_IWL<3781> B_IWL<3780> B_IWL<3779> B_IWL<3778> B_IWL<3777> B_IWL<3776> B_IWL<3775> B_IWL<3774> B_IWL<3773> B_IWL<3772> B_IWL<3771> B_IWL<3770> B_IWL<3769> B_IWL<3768> B_IWL<3767> B_IWL<3766> B_IWL<3765> B_IWL<3764> B_IWL<3763> B_IWL<3762> B_IWL<3761> B_IWL<3760> B_IWL<3759> B_IWL<3758> B_IWL<3757> B_IWL<3756> B_IWL<3755> B_IWL<3754> B_IWL<3753> B_IWL<3752> B_IWL<3751> B_IWL<3750> B_IWL<3749> B_IWL<3748> B_IWL<3747> B_IWL<3746> B_IWL<3745> B_IWL<3744> B_IWL<3743> B_IWL<3742> B_IWL<3741> B_IWL<3740> B_IWL<3739> B_IWL<3738> B_IWL<3737> B_IWL<3736> B_IWL<3735> B_IWL<3734> B_IWL<3733> B_IWL<3732> B_IWL<3731> B_IWL<3730> B_IWL<3729> B_IWL<3728> B_IWL<3727> B_IWL<3726> B_IWL<3725> B_IWL<3724> B_IWL<3723> B_IWL<3722> B_IWL<3721> B_IWL<3720> B_IWL<3719> B_IWL<3718> B_IWL<3717> B_IWL<3716> B_IWL<3715> B_IWL<3714> B_IWL<3713> B_IWL<3712> B_IWL<3711> B_IWL<3710> B_IWL<3709> B_IWL<3708> B_IWL<3707> B_IWL<3706> B_IWL<3705> B_IWL<3704> B_IWL<3703> B_IWL<3702> B_IWL<3701> B_IWL<3700> B_IWL<3699> B_IWL<3698> B_IWL<3697> B_IWL<3696> B_IWL<3695> B_IWL<3694> B_IWL<3693> B_IWL<3692> B_IWL<3691> B_IWL<3690> B_IWL<3689> B_IWL<3688> B_IWL<3687> B_IWL<3686> B_IWL<3685> B_IWL<3684> B_IWL<3683> B_IWL<3682> B_IWL<3681> B_IWL<3680> B_IWL<3679> B_IWL<3678> B_IWL<3677> B_IWL<3676> B_IWL<3675> B_IWL<3674> B_IWL<3673> B_IWL<3672> B_IWL<3671> B_IWL<3670> B_IWL<3669> B_IWL<3668> B_IWL<3667> B_IWL<3666> B_IWL<3665> B_IWL<3664> B_IWL<3663> B_IWL<3662> B_IWL<3661> B_IWL<3660> B_IWL<3659> B_IWL<3658> B_IWL<3657> B_IWL<3656> B_IWL<3655> B_IWL<3654> B_IWL<3653> B_IWL<3652> B_IWL<3651> B_IWL<3650> B_IWL<3649> B_IWL<3648> B_IWL<3647> B_IWL<3646> B_IWL<3645> B_IWL<3644> B_IWL<3643> B_IWL<3642> B_IWL<3641> B_IWL<3640> B_IWL<3639> B_IWL<3638> B_IWL<3637> B_IWL<3636> B_IWL<3635> B_IWL<3634> B_IWL<3633> B_IWL<3632> B_IWL<3631> B_IWL<3630> B_IWL<3629> B_IWL<3628> B_IWL<3627> B_IWL<3626> B_IWL<3625> B_IWL<3624> B_IWL<3623> B_IWL<3622> B_IWL<3621> B_IWL<3620> B_IWL<3619> B_IWL<3618> B_IWL<3617> B_IWL<3616> B_IWL<3615> B_IWL<3614> B_IWL<3613> B_IWL<3612> B_IWL<3611> B_IWL<3610> B_IWL<3609> B_IWL<3608> B_IWL<3607> B_IWL<3606> B_IWL<3605> B_IWL<3604> B_IWL<3603> B_IWL<3602> B_IWL<3601> B_IWL<3600> B_IWL<3599> B_IWL<3598> B_IWL<3597> B_IWL<3596> B_IWL<3595> B_IWL<3594> B_IWL<3593> B_IWL<3592> B_IWL<3591> B_IWL<3590> B_IWL<3589> B_IWL<3588> B_IWL<3587> B_IWL<3586> B_IWL<3585> B_IWL<3584> VDD_CORE VSS / RM_IHPSG13_1024x32_c2_2P_COLUMN_pcell_0 +XCOL<13> A_BLC<27> A_BLC<26> A_BLC_TOP<27> A_BLC_TOP<26> A_BLT<27> A_BLT<26> A_BLT_TOP<27> A_BLT_TOP<26> A_IWL<3327> A_IWL<3326> A_IWL<3325> A_IWL<3324> A_IWL<3323> A_IWL<3322> A_IWL<3321> A_IWL<3320> A_IWL<3319> A_IWL<3318> A_IWL<3317> A_IWL<3316> A_IWL<3315> A_IWL<3314> A_IWL<3313> A_IWL<3312> A_IWL<3311> A_IWL<3310> A_IWL<3309> A_IWL<3308> A_IWL<3307> A_IWL<3306> A_IWL<3305> A_IWL<3304> A_IWL<3303> A_IWL<3302> A_IWL<3301> A_IWL<3300> A_IWL<3299> A_IWL<3298> A_IWL<3297> A_IWL<3296> A_IWL<3295> A_IWL<3294> A_IWL<3293> A_IWL<3292> A_IWL<3291> A_IWL<3290> A_IWL<3289> A_IWL<3288> A_IWL<3287> A_IWL<3286> A_IWL<3285> A_IWL<3284> A_IWL<3283> A_IWL<3282> A_IWL<3281> A_IWL<3280> A_IWL<3279> A_IWL<3278> A_IWL<3277> A_IWL<3276> A_IWL<3275> A_IWL<3274> A_IWL<3273> A_IWL<3272> A_IWL<3271> A_IWL<3270> A_IWL<3269> A_IWL<3268> A_IWL<3267> A_IWL<3266> A_IWL<3265> A_IWL<3264> A_IWL<3263> A_IWL<3262> A_IWL<3261> A_IWL<3260> A_IWL<3259> A_IWL<3258> A_IWL<3257> A_IWL<3256> A_IWL<3255> A_IWL<3254> A_IWL<3253> A_IWL<3252> A_IWL<3251> A_IWL<3250> A_IWL<3249> A_IWL<3248> A_IWL<3247> A_IWL<3246> A_IWL<3245> A_IWL<3244> A_IWL<3243> A_IWL<3242> A_IWL<3241> A_IWL<3240> A_IWL<3239> A_IWL<3238> A_IWL<3237> A_IWL<3236> A_IWL<3235> A_IWL<3234> A_IWL<3233> A_IWL<3232> A_IWL<3231> A_IWL<3230> A_IWL<3229> A_IWL<3228> A_IWL<3227> A_IWL<3226> A_IWL<3225> A_IWL<3224> A_IWL<3223> A_IWL<3222> A_IWL<3221> A_IWL<3220> A_IWL<3219> A_IWL<3218> A_IWL<3217> A_IWL<3216> A_IWL<3215> A_IWL<3214> A_IWL<3213> A_IWL<3212> A_IWL<3211> A_IWL<3210> A_IWL<3209> A_IWL<3208> A_IWL<3207> A_IWL<3206> A_IWL<3205> A_IWL<3204> A_IWL<3203> A_IWL<3202> A_IWL<3201> A_IWL<3200> A_IWL<3199> A_IWL<3198> A_IWL<3197> A_IWL<3196> A_IWL<3195> A_IWL<3194> A_IWL<3193> A_IWL<3192> A_IWL<3191> A_IWL<3190> A_IWL<3189> A_IWL<3188> A_IWL<3187> A_IWL<3186> A_IWL<3185> A_IWL<3184> A_IWL<3183> A_IWL<3182> A_IWL<3181> A_IWL<3180> A_IWL<3179> A_IWL<3178> A_IWL<3177> A_IWL<3176> A_IWL<3175> A_IWL<3174> A_IWL<3173> A_IWL<3172> A_IWL<3171> A_IWL<3170> A_IWL<3169> A_IWL<3168> A_IWL<3167> A_IWL<3166> A_IWL<3165> A_IWL<3164> A_IWL<3163> A_IWL<3162> A_IWL<3161> A_IWL<3160> A_IWL<3159> A_IWL<3158> A_IWL<3157> A_IWL<3156> A_IWL<3155> A_IWL<3154> A_IWL<3153> A_IWL<3152> A_IWL<3151> A_IWL<3150> A_IWL<3149> A_IWL<3148> A_IWL<3147> A_IWL<3146> A_IWL<3145> A_IWL<3144> A_IWL<3143> A_IWL<3142> A_IWL<3141> A_IWL<3140> A_IWL<3139> A_IWL<3138> A_IWL<3137> A_IWL<3136> A_IWL<3135> A_IWL<3134> A_IWL<3133> A_IWL<3132> A_IWL<3131> A_IWL<3130> A_IWL<3129> A_IWL<3128> A_IWL<3127> A_IWL<3126> A_IWL<3125> A_IWL<3124> A_IWL<3123> A_IWL<3122> A_IWL<3121> A_IWL<3120> A_IWL<3119> A_IWL<3118> A_IWL<3117> A_IWL<3116> A_IWL<3115> A_IWL<3114> A_IWL<3113> A_IWL<3112> A_IWL<3111> A_IWL<3110> A_IWL<3109> A_IWL<3108> A_IWL<3107> A_IWL<3106> A_IWL<3105> A_IWL<3104> A_IWL<3103> A_IWL<3102> A_IWL<3101> A_IWL<3100> A_IWL<3099> A_IWL<3098> A_IWL<3097> A_IWL<3096> A_IWL<3095> A_IWL<3094> A_IWL<3093> A_IWL<3092> A_IWL<3091> A_IWL<3090> A_IWL<3089> A_IWL<3088> A_IWL<3087> A_IWL<3086> A_IWL<3085> A_IWL<3084> A_IWL<3083> A_IWL<3082> A_IWL<3081> A_IWL<3080> A_IWL<3079> A_IWL<3078> A_IWL<3077> A_IWL<3076> A_IWL<3075> A_IWL<3074> A_IWL<3073> A_IWL<3072> A_IWL<3583> A_IWL<3582> A_IWL<3581> A_IWL<3580> A_IWL<3579> A_IWL<3578> A_IWL<3577> A_IWL<3576> A_IWL<3575> A_IWL<3574> A_IWL<3573> A_IWL<3572> A_IWL<3571> A_IWL<3570> A_IWL<3569> A_IWL<3568> A_IWL<3567> A_IWL<3566> A_IWL<3565> A_IWL<3564> A_IWL<3563> A_IWL<3562> A_IWL<3561> A_IWL<3560> A_IWL<3559> A_IWL<3558> A_IWL<3557> A_IWL<3556> A_IWL<3555> A_IWL<3554> A_IWL<3553> A_IWL<3552> A_IWL<3551> A_IWL<3550> A_IWL<3549> A_IWL<3548> A_IWL<3547> A_IWL<3546> A_IWL<3545> A_IWL<3544> A_IWL<3543> A_IWL<3542> A_IWL<3541> A_IWL<3540> A_IWL<3539> A_IWL<3538> A_IWL<3537> A_IWL<3536> A_IWL<3535> A_IWL<3534> A_IWL<3533> A_IWL<3532> A_IWL<3531> A_IWL<3530> A_IWL<3529> A_IWL<3528> A_IWL<3527> A_IWL<3526> A_IWL<3525> A_IWL<3524> A_IWL<3523> A_IWL<3522> A_IWL<3521> A_IWL<3520> A_IWL<3519> A_IWL<3518> A_IWL<3517> A_IWL<3516> A_IWL<3515> A_IWL<3514> A_IWL<3513> A_IWL<3512> A_IWL<3511> A_IWL<3510> A_IWL<3509> A_IWL<3508> A_IWL<3507> A_IWL<3506> A_IWL<3505> A_IWL<3504> A_IWL<3503> A_IWL<3502> A_IWL<3501> A_IWL<3500> A_IWL<3499> A_IWL<3498> A_IWL<3497> A_IWL<3496> A_IWL<3495> A_IWL<3494> A_IWL<3493> A_IWL<3492> A_IWL<3491> A_IWL<3490> A_IWL<3489> A_IWL<3488> A_IWL<3487> A_IWL<3486> A_IWL<3485> A_IWL<3484> A_IWL<3483> A_IWL<3482> A_IWL<3481> A_IWL<3480> A_IWL<3479> A_IWL<3478> A_IWL<3477> A_IWL<3476> A_IWL<3475> A_IWL<3474> A_IWL<3473> A_IWL<3472> A_IWL<3471> A_IWL<3470> A_IWL<3469> A_IWL<3468> A_IWL<3467> A_IWL<3466> A_IWL<3465> A_IWL<3464> A_IWL<3463> A_IWL<3462> A_IWL<3461> A_IWL<3460> A_IWL<3459> A_IWL<3458> A_IWL<3457> A_IWL<3456> A_IWL<3455> A_IWL<3454> A_IWL<3453> A_IWL<3452> A_IWL<3451> A_IWL<3450> A_IWL<3449> A_IWL<3448> A_IWL<3447> A_IWL<3446> A_IWL<3445> A_IWL<3444> A_IWL<3443> A_IWL<3442> A_IWL<3441> A_IWL<3440> A_IWL<3439> A_IWL<3438> A_IWL<3437> A_IWL<3436> A_IWL<3435> A_IWL<3434> A_IWL<3433> A_IWL<3432> A_IWL<3431> A_IWL<3430> A_IWL<3429> A_IWL<3428> A_IWL<3427> A_IWL<3426> A_IWL<3425> A_IWL<3424> A_IWL<3423> A_IWL<3422> A_IWL<3421> A_IWL<3420> A_IWL<3419> A_IWL<3418> A_IWL<3417> A_IWL<3416> A_IWL<3415> A_IWL<3414> A_IWL<3413> A_IWL<3412> A_IWL<3411> A_IWL<3410> A_IWL<3409> A_IWL<3408> A_IWL<3407> A_IWL<3406> A_IWL<3405> A_IWL<3404> A_IWL<3403> A_IWL<3402> A_IWL<3401> A_IWL<3400> A_IWL<3399> A_IWL<3398> A_IWL<3397> A_IWL<3396> A_IWL<3395> A_IWL<3394> A_IWL<3393> A_IWL<3392> A_IWL<3391> A_IWL<3390> A_IWL<3389> A_IWL<3388> A_IWL<3387> A_IWL<3386> A_IWL<3385> A_IWL<3384> A_IWL<3383> A_IWL<3382> A_IWL<3381> A_IWL<3380> A_IWL<3379> A_IWL<3378> A_IWL<3377> A_IWL<3376> A_IWL<3375> A_IWL<3374> A_IWL<3373> A_IWL<3372> A_IWL<3371> A_IWL<3370> A_IWL<3369> A_IWL<3368> A_IWL<3367> A_IWL<3366> A_IWL<3365> A_IWL<3364> A_IWL<3363> A_IWL<3362> A_IWL<3361> A_IWL<3360> A_IWL<3359> A_IWL<3358> A_IWL<3357> A_IWL<3356> A_IWL<3355> A_IWL<3354> A_IWL<3353> A_IWL<3352> A_IWL<3351> A_IWL<3350> A_IWL<3349> A_IWL<3348> A_IWL<3347> A_IWL<3346> A_IWL<3345> A_IWL<3344> A_IWL<3343> A_IWL<3342> A_IWL<3341> A_IWL<3340> A_IWL<3339> A_IWL<3338> A_IWL<3337> A_IWL<3336> A_IWL<3335> A_IWL<3334> A_IWL<3333> A_IWL<3332> A_IWL<3331> A_IWL<3330> A_IWL<3329> A_IWL<3328> B_BLC<27> B_BLC<26> B_BLC_TOP<27> B_BLC_TOP<26> B_BLT<27> B_BLT<26> B_BLT_TOP<27> B_BLT_TOP<26> B_IWL<3327> B_IWL<3326> B_IWL<3325> B_IWL<3324> B_IWL<3323> B_IWL<3322> B_IWL<3321> B_IWL<3320> B_IWL<3319> B_IWL<3318> B_IWL<3317> B_IWL<3316> B_IWL<3315> B_IWL<3314> B_IWL<3313> B_IWL<3312> B_IWL<3311> B_IWL<3310> B_IWL<3309> B_IWL<3308> B_IWL<3307> B_IWL<3306> B_IWL<3305> B_IWL<3304> B_IWL<3303> B_IWL<3302> B_IWL<3301> B_IWL<3300> B_IWL<3299> B_IWL<3298> B_IWL<3297> B_IWL<3296> B_IWL<3295> B_IWL<3294> B_IWL<3293> B_IWL<3292> B_IWL<3291> B_IWL<3290> B_IWL<3289> B_IWL<3288> B_IWL<3287> B_IWL<3286> B_IWL<3285> B_IWL<3284> B_IWL<3283> B_IWL<3282> B_IWL<3281> B_IWL<3280> B_IWL<3279> B_IWL<3278> B_IWL<3277> B_IWL<3276> B_IWL<3275> B_IWL<3274> B_IWL<3273> B_IWL<3272> B_IWL<3271> B_IWL<3270> B_IWL<3269> B_IWL<3268> B_IWL<3267> B_IWL<3266> B_IWL<3265> B_IWL<3264> B_IWL<3263> B_IWL<3262> B_IWL<3261> B_IWL<3260> B_IWL<3259> B_IWL<3258> B_IWL<3257> B_IWL<3256> B_IWL<3255> B_IWL<3254> B_IWL<3253> B_IWL<3252> B_IWL<3251> B_IWL<3250> B_IWL<3249> B_IWL<3248> B_IWL<3247> B_IWL<3246> B_IWL<3245> B_IWL<3244> B_IWL<3243> B_IWL<3242> B_IWL<3241> B_IWL<3240> B_IWL<3239> B_IWL<3238> B_IWL<3237> B_IWL<3236> B_IWL<3235> B_IWL<3234> B_IWL<3233> B_IWL<3232> B_IWL<3231> B_IWL<3230> B_IWL<3229> B_IWL<3228> B_IWL<3227> B_IWL<3226> B_IWL<3225> B_IWL<3224> B_IWL<3223> B_IWL<3222> B_IWL<3221> B_IWL<3220> B_IWL<3219> B_IWL<3218> B_IWL<3217> B_IWL<3216> B_IWL<3215> B_IWL<3214> B_IWL<3213> B_IWL<3212> B_IWL<3211> B_IWL<3210> B_IWL<3209> B_IWL<3208> B_IWL<3207> B_IWL<3206> B_IWL<3205> B_IWL<3204> B_IWL<3203> B_IWL<3202> B_IWL<3201> B_IWL<3200> B_IWL<3199> B_IWL<3198> B_IWL<3197> B_IWL<3196> B_IWL<3195> B_IWL<3194> B_IWL<3193> B_IWL<3192> B_IWL<3191> B_IWL<3190> B_IWL<3189> B_IWL<3188> B_IWL<3187> B_IWL<3186> B_IWL<3185> B_IWL<3184> B_IWL<3183> B_IWL<3182> B_IWL<3181> B_IWL<3180> B_IWL<3179> B_IWL<3178> B_IWL<3177> B_IWL<3176> B_IWL<3175> B_IWL<3174> B_IWL<3173> B_IWL<3172> B_IWL<3171> B_IWL<3170> B_IWL<3169> B_IWL<3168> B_IWL<3167> B_IWL<3166> B_IWL<3165> B_IWL<3164> B_IWL<3163> B_IWL<3162> B_IWL<3161> B_IWL<3160> B_IWL<3159> B_IWL<3158> B_IWL<3157> B_IWL<3156> B_IWL<3155> B_IWL<3154> B_IWL<3153> B_IWL<3152> B_IWL<3151> B_IWL<3150> B_IWL<3149> B_IWL<3148> B_IWL<3147> B_IWL<3146> B_IWL<3145> B_IWL<3144> B_IWL<3143> B_IWL<3142> B_IWL<3141> B_IWL<3140> B_IWL<3139> B_IWL<3138> B_IWL<3137> B_IWL<3136> B_IWL<3135> B_IWL<3134> B_IWL<3133> B_IWL<3132> B_IWL<3131> B_IWL<3130> B_IWL<3129> B_IWL<3128> B_IWL<3127> B_IWL<3126> B_IWL<3125> B_IWL<3124> B_IWL<3123> B_IWL<3122> B_IWL<3121> B_IWL<3120> B_IWL<3119> B_IWL<3118> B_IWL<3117> B_IWL<3116> B_IWL<3115> B_IWL<3114> B_IWL<3113> B_IWL<3112> B_IWL<3111> B_IWL<3110> B_IWL<3109> B_IWL<3108> B_IWL<3107> B_IWL<3106> B_IWL<3105> B_IWL<3104> B_IWL<3103> B_IWL<3102> B_IWL<3101> B_IWL<3100> B_IWL<3099> B_IWL<3098> B_IWL<3097> B_IWL<3096> B_IWL<3095> B_IWL<3094> B_IWL<3093> B_IWL<3092> B_IWL<3091> B_IWL<3090> B_IWL<3089> B_IWL<3088> B_IWL<3087> B_IWL<3086> B_IWL<3085> B_IWL<3084> B_IWL<3083> B_IWL<3082> B_IWL<3081> B_IWL<3080> B_IWL<3079> B_IWL<3078> B_IWL<3077> B_IWL<3076> B_IWL<3075> B_IWL<3074> B_IWL<3073> B_IWL<3072> B_IWL<3583> B_IWL<3582> B_IWL<3581> B_IWL<3580> B_IWL<3579> B_IWL<3578> B_IWL<3577> B_IWL<3576> B_IWL<3575> B_IWL<3574> B_IWL<3573> B_IWL<3572> B_IWL<3571> B_IWL<3570> B_IWL<3569> B_IWL<3568> B_IWL<3567> B_IWL<3566> B_IWL<3565> B_IWL<3564> B_IWL<3563> B_IWL<3562> B_IWL<3561> B_IWL<3560> B_IWL<3559> B_IWL<3558> B_IWL<3557> B_IWL<3556> B_IWL<3555> B_IWL<3554> B_IWL<3553> B_IWL<3552> B_IWL<3551> B_IWL<3550> B_IWL<3549> B_IWL<3548> B_IWL<3547> B_IWL<3546> B_IWL<3545> B_IWL<3544> B_IWL<3543> B_IWL<3542> B_IWL<3541> B_IWL<3540> B_IWL<3539> B_IWL<3538> B_IWL<3537> B_IWL<3536> B_IWL<3535> B_IWL<3534> B_IWL<3533> B_IWL<3532> B_IWL<3531> B_IWL<3530> B_IWL<3529> B_IWL<3528> B_IWL<3527> B_IWL<3526> B_IWL<3525> B_IWL<3524> B_IWL<3523> B_IWL<3522> B_IWL<3521> B_IWL<3520> B_IWL<3519> B_IWL<3518> B_IWL<3517> B_IWL<3516> B_IWL<3515> B_IWL<3514> B_IWL<3513> B_IWL<3512> B_IWL<3511> B_IWL<3510> B_IWL<3509> B_IWL<3508> B_IWL<3507> B_IWL<3506> B_IWL<3505> B_IWL<3504> B_IWL<3503> B_IWL<3502> B_IWL<3501> B_IWL<3500> B_IWL<3499> B_IWL<3498> B_IWL<3497> B_IWL<3496> B_IWL<3495> B_IWL<3494> B_IWL<3493> B_IWL<3492> B_IWL<3491> B_IWL<3490> B_IWL<3489> B_IWL<3488> B_IWL<3487> B_IWL<3486> B_IWL<3485> B_IWL<3484> B_IWL<3483> B_IWL<3482> B_IWL<3481> B_IWL<3480> B_IWL<3479> B_IWL<3478> B_IWL<3477> B_IWL<3476> B_IWL<3475> B_IWL<3474> B_IWL<3473> B_IWL<3472> B_IWL<3471> B_IWL<3470> B_IWL<3469> B_IWL<3468> B_IWL<3467> B_IWL<3466> B_IWL<3465> B_IWL<3464> B_IWL<3463> B_IWL<3462> B_IWL<3461> B_IWL<3460> B_IWL<3459> B_IWL<3458> B_IWL<3457> B_IWL<3456> B_IWL<3455> B_IWL<3454> B_IWL<3453> B_IWL<3452> B_IWL<3451> B_IWL<3450> B_IWL<3449> B_IWL<3448> B_IWL<3447> B_IWL<3446> B_IWL<3445> B_IWL<3444> B_IWL<3443> B_IWL<3442> B_IWL<3441> B_IWL<3440> B_IWL<3439> B_IWL<3438> B_IWL<3437> B_IWL<3436> B_IWL<3435> B_IWL<3434> B_IWL<3433> B_IWL<3432> B_IWL<3431> B_IWL<3430> B_IWL<3429> B_IWL<3428> B_IWL<3427> B_IWL<3426> B_IWL<3425> B_IWL<3424> B_IWL<3423> B_IWL<3422> B_IWL<3421> B_IWL<3420> B_IWL<3419> B_IWL<3418> B_IWL<3417> B_IWL<3416> B_IWL<3415> B_IWL<3414> B_IWL<3413> B_IWL<3412> B_IWL<3411> B_IWL<3410> B_IWL<3409> B_IWL<3408> B_IWL<3407> B_IWL<3406> B_IWL<3405> B_IWL<3404> B_IWL<3403> B_IWL<3402> B_IWL<3401> B_IWL<3400> B_IWL<3399> B_IWL<3398> B_IWL<3397> B_IWL<3396> B_IWL<3395> B_IWL<3394> B_IWL<3393> B_IWL<3392> B_IWL<3391> B_IWL<3390> B_IWL<3389> B_IWL<3388> B_IWL<3387> B_IWL<3386> B_IWL<3385> B_IWL<3384> B_IWL<3383> B_IWL<3382> B_IWL<3381> B_IWL<3380> B_IWL<3379> B_IWL<3378> B_IWL<3377> B_IWL<3376> B_IWL<3375> B_IWL<3374> B_IWL<3373> B_IWL<3372> B_IWL<3371> B_IWL<3370> B_IWL<3369> B_IWL<3368> B_IWL<3367> B_IWL<3366> B_IWL<3365> B_IWL<3364> B_IWL<3363> B_IWL<3362> B_IWL<3361> B_IWL<3360> B_IWL<3359> B_IWL<3358> B_IWL<3357> B_IWL<3356> B_IWL<3355> B_IWL<3354> B_IWL<3353> B_IWL<3352> B_IWL<3351> B_IWL<3350> B_IWL<3349> B_IWL<3348> B_IWL<3347> B_IWL<3346> B_IWL<3345> B_IWL<3344> B_IWL<3343> B_IWL<3342> B_IWL<3341> B_IWL<3340> B_IWL<3339> B_IWL<3338> B_IWL<3337> B_IWL<3336> B_IWL<3335> B_IWL<3334> B_IWL<3333> B_IWL<3332> B_IWL<3331> B_IWL<3330> B_IWL<3329> B_IWL<3328> VDD_CORE VSS / RM_IHPSG13_1024x32_c2_2P_COLUMN_pcell_0 +XCOL<12> A_BLC<25> A_BLC<24> A_BLC_TOP<25> A_BLC_TOP<24> A_BLT<25> A_BLT<24> A_BLT_TOP<25> A_BLT_TOP<24> A_IWL<3071> A_IWL<3070> A_IWL<3069> A_IWL<3068> A_IWL<3067> A_IWL<3066> A_IWL<3065> A_IWL<3064> A_IWL<3063> A_IWL<3062> A_IWL<3061> A_IWL<3060> A_IWL<3059> A_IWL<3058> A_IWL<3057> A_IWL<3056> A_IWL<3055> A_IWL<3054> A_IWL<3053> A_IWL<3052> A_IWL<3051> A_IWL<3050> A_IWL<3049> A_IWL<3048> A_IWL<3047> A_IWL<3046> A_IWL<3045> A_IWL<3044> A_IWL<3043> A_IWL<3042> A_IWL<3041> A_IWL<3040> A_IWL<3039> A_IWL<3038> A_IWL<3037> A_IWL<3036> A_IWL<3035> A_IWL<3034> A_IWL<3033> A_IWL<3032> A_IWL<3031> A_IWL<3030> A_IWL<3029> A_IWL<3028> A_IWL<3027> A_IWL<3026> A_IWL<3025> A_IWL<3024> A_IWL<3023> A_IWL<3022> A_IWL<3021> A_IWL<3020> A_IWL<3019> A_IWL<3018> A_IWL<3017> A_IWL<3016> A_IWL<3015> A_IWL<3014> A_IWL<3013> A_IWL<3012> A_IWL<3011> A_IWL<3010> A_IWL<3009> A_IWL<3008> A_IWL<3007> A_IWL<3006> A_IWL<3005> A_IWL<3004> A_IWL<3003> A_IWL<3002> A_IWL<3001> A_IWL<3000> A_IWL<2999> A_IWL<2998> A_IWL<2997> A_IWL<2996> A_IWL<2995> A_IWL<2994> A_IWL<2993> A_IWL<2992> A_IWL<2991> A_IWL<2990> A_IWL<2989> A_IWL<2988> A_IWL<2987> A_IWL<2986> A_IWL<2985> A_IWL<2984> A_IWL<2983> A_IWL<2982> A_IWL<2981> A_IWL<2980> A_IWL<2979> A_IWL<2978> A_IWL<2977> A_IWL<2976> A_IWL<2975> A_IWL<2974> A_IWL<2973> A_IWL<2972> A_IWL<2971> A_IWL<2970> A_IWL<2969> A_IWL<2968> A_IWL<2967> A_IWL<2966> A_IWL<2965> A_IWL<2964> A_IWL<2963> A_IWL<2962> A_IWL<2961> A_IWL<2960> A_IWL<2959> A_IWL<2958> A_IWL<2957> A_IWL<2956> A_IWL<2955> A_IWL<2954> A_IWL<2953> A_IWL<2952> A_IWL<2951> A_IWL<2950> A_IWL<2949> A_IWL<2948> A_IWL<2947> A_IWL<2946> A_IWL<2945> A_IWL<2944> A_IWL<2943> A_IWL<2942> A_IWL<2941> A_IWL<2940> A_IWL<2939> A_IWL<2938> A_IWL<2937> A_IWL<2936> A_IWL<2935> A_IWL<2934> A_IWL<2933> A_IWL<2932> A_IWL<2931> A_IWL<2930> A_IWL<2929> A_IWL<2928> A_IWL<2927> A_IWL<2926> A_IWL<2925> A_IWL<2924> A_IWL<2923> A_IWL<2922> A_IWL<2921> A_IWL<2920> A_IWL<2919> A_IWL<2918> A_IWL<2917> A_IWL<2916> A_IWL<2915> A_IWL<2914> A_IWL<2913> A_IWL<2912> A_IWL<2911> A_IWL<2910> A_IWL<2909> A_IWL<2908> A_IWL<2907> A_IWL<2906> A_IWL<2905> A_IWL<2904> A_IWL<2903> A_IWL<2902> A_IWL<2901> A_IWL<2900> A_IWL<2899> A_IWL<2898> A_IWL<2897> A_IWL<2896> A_IWL<2895> A_IWL<2894> A_IWL<2893> A_IWL<2892> A_IWL<2891> A_IWL<2890> A_IWL<2889> A_IWL<2888> A_IWL<2887> A_IWL<2886> A_IWL<2885> A_IWL<2884> A_IWL<2883> A_IWL<2882> A_IWL<2881> A_IWL<2880> A_IWL<2879> A_IWL<2878> A_IWL<2877> A_IWL<2876> A_IWL<2875> A_IWL<2874> A_IWL<2873> A_IWL<2872> A_IWL<2871> A_IWL<2870> A_IWL<2869> A_IWL<2868> A_IWL<2867> A_IWL<2866> A_IWL<2865> A_IWL<2864> A_IWL<2863> A_IWL<2862> A_IWL<2861> A_IWL<2860> A_IWL<2859> A_IWL<2858> A_IWL<2857> A_IWL<2856> A_IWL<2855> A_IWL<2854> A_IWL<2853> A_IWL<2852> A_IWL<2851> A_IWL<2850> A_IWL<2849> A_IWL<2848> A_IWL<2847> A_IWL<2846> A_IWL<2845> A_IWL<2844> A_IWL<2843> A_IWL<2842> A_IWL<2841> A_IWL<2840> A_IWL<2839> A_IWL<2838> A_IWL<2837> A_IWL<2836> A_IWL<2835> A_IWL<2834> A_IWL<2833> A_IWL<2832> A_IWL<2831> A_IWL<2830> A_IWL<2829> A_IWL<2828> A_IWL<2827> A_IWL<2826> A_IWL<2825> A_IWL<2824> A_IWL<2823> A_IWL<2822> A_IWL<2821> A_IWL<2820> A_IWL<2819> A_IWL<2818> A_IWL<2817> A_IWL<2816> A_IWL<3327> A_IWL<3326> A_IWL<3325> A_IWL<3324> A_IWL<3323> A_IWL<3322> A_IWL<3321> A_IWL<3320> A_IWL<3319> A_IWL<3318> A_IWL<3317> A_IWL<3316> A_IWL<3315> A_IWL<3314> A_IWL<3313> A_IWL<3312> A_IWL<3311> A_IWL<3310> A_IWL<3309> A_IWL<3308> A_IWL<3307> A_IWL<3306> A_IWL<3305> A_IWL<3304> A_IWL<3303> A_IWL<3302> A_IWL<3301> A_IWL<3300> A_IWL<3299> A_IWL<3298> A_IWL<3297> A_IWL<3296> A_IWL<3295> A_IWL<3294> A_IWL<3293> A_IWL<3292> A_IWL<3291> A_IWL<3290> A_IWL<3289> A_IWL<3288> A_IWL<3287> A_IWL<3286> A_IWL<3285> A_IWL<3284> A_IWL<3283> A_IWL<3282> A_IWL<3281> A_IWL<3280> A_IWL<3279> A_IWL<3278> A_IWL<3277> A_IWL<3276> A_IWL<3275> A_IWL<3274> A_IWL<3273> A_IWL<3272> A_IWL<3271> A_IWL<3270> A_IWL<3269> A_IWL<3268> A_IWL<3267> A_IWL<3266> A_IWL<3265> A_IWL<3264> A_IWL<3263> A_IWL<3262> A_IWL<3261> A_IWL<3260> A_IWL<3259> A_IWL<3258> A_IWL<3257> A_IWL<3256> A_IWL<3255> A_IWL<3254> A_IWL<3253> A_IWL<3252> A_IWL<3251> A_IWL<3250> A_IWL<3249> A_IWL<3248> A_IWL<3247> A_IWL<3246> A_IWL<3245> A_IWL<3244> A_IWL<3243> A_IWL<3242> A_IWL<3241> A_IWL<3240> A_IWL<3239> A_IWL<3238> A_IWL<3237> A_IWL<3236> A_IWL<3235> A_IWL<3234> A_IWL<3233> A_IWL<3232> A_IWL<3231> A_IWL<3230> A_IWL<3229> A_IWL<3228> A_IWL<3227> A_IWL<3226> A_IWL<3225> A_IWL<3224> A_IWL<3223> A_IWL<3222> A_IWL<3221> A_IWL<3220> A_IWL<3219> A_IWL<3218> A_IWL<3217> A_IWL<3216> A_IWL<3215> A_IWL<3214> A_IWL<3213> A_IWL<3212> A_IWL<3211> A_IWL<3210> A_IWL<3209> A_IWL<3208> A_IWL<3207> A_IWL<3206> A_IWL<3205> A_IWL<3204> A_IWL<3203> A_IWL<3202> A_IWL<3201> A_IWL<3200> A_IWL<3199> A_IWL<3198> A_IWL<3197> A_IWL<3196> A_IWL<3195> A_IWL<3194> A_IWL<3193> A_IWL<3192> A_IWL<3191> A_IWL<3190> A_IWL<3189> A_IWL<3188> A_IWL<3187> A_IWL<3186> A_IWL<3185> A_IWL<3184> A_IWL<3183> A_IWL<3182> A_IWL<3181> A_IWL<3180> A_IWL<3179> A_IWL<3178> A_IWL<3177> A_IWL<3176> A_IWL<3175> A_IWL<3174> A_IWL<3173> A_IWL<3172> A_IWL<3171> A_IWL<3170> A_IWL<3169> A_IWL<3168> A_IWL<3167> A_IWL<3166> A_IWL<3165> A_IWL<3164> A_IWL<3163> A_IWL<3162> A_IWL<3161> A_IWL<3160> A_IWL<3159> A_IWL<3158> A_IWL<3157> A_IWL<3156> A_IWL<3155> A_IWL<3154> A_IWL<3153> A_IWL<3152> A_IWL<3151> A_IWL<3150> A_IWL<3149> A_IWL<3148> A_IWL<3147> A_IWL<3146> A_IWL<3145> A_IWL<3144> A_IWL<3143> A_IWL<3142> A_IWL<3141> A_IWL<3140> A_IWL<3139> A_IWL<3138> A_IWL<3137> A_IWL<3136> A_IWL<3135> A_IWL<3134> A_IWL<3133> A_IWL<3132> A_IWL<3131> A_IWL<3130> A_IWL<3129> A_IWL<3128> A_IWL<3127> A_IWL<3126> A_IWL<3125> A_IWL<3124> A_IWL<3123> A_IWL<3122> A_IWL<3121> A_IWL<3120> A_IWL<3119> A_IWL<3118> A_IWL<3117> A_IWL<3116> A_IWL<3115> A_IWL<3114> A_IWL<3113> A_IWL<3112> A_IWL<3111> A_IWL<3110> A_IWL<3109> A_IWL<3108> A_IWL<3107> A_IWL<3106> A_IWL<3105> A_IWL<3104> A_IWL<3103> A_IWL<3102> A_IWL<3101> A_IWL<3100> A_IWL<3099> A_IWL<3098> A_IWL<3097> A_IWL<3096> A_IWL<3095> A_IWL<3094> A_IWL<3093> A_IWL<3092> A_IWL<3091> A_IWL<3090> A_IWL<3089> A_IWL<3088> A_IWL<3087> A_IWL<3086> A_IWL<3085> A_IWL<3084> A_IWL<3083> A_IWL<3082> A_IWL<3081> A_IWL<3080> A_IWL<3079> A_IWL<3078> A_IWL<3077> A_IWL<3076> A_IWL<3075> A_IWL<3074> A_IWL<3073> A_IWL<3072> B_BLC<25> B_BLC<24> B_BLC_TOP<25> B_BLC_TOP<24> B_BLT<25> B_BLT<24> B_BLT_TOP<25> B_BLT_TOP<24> B_IWL<3071> B_IWL<3070> B_IWL<3069> B_IWL<3068> B_IWL<3067> B_IWL<3066> B_IWL<3065> B_IWL<3064> B_IWL<3063> B_IWL<3062> B_IWL<3061> B_IWL<3060> B_IWL<3059> B_IWL<3058> B_IWL<3057> B_IWL<3056> B_IWL<3055> B_IWL<3054> B_IWL<3053> B_IWL<3052> B_IWL<3051> B_IWL<3050> B_IWL<3049> B_IWL<3048> B_IWL<3047> B_IWL<3046> B_IWL<3045> B_IWL<3044> B_IWL<3043> B_IWL<3042> B_IWL<3041> B_IWL<3040> B_IWL<3039> B_IWL<3038> B_IWL<3037> B_IWL<3036> B_IWL<3035> B_IWL<3034> B_IWL<3033> B_IWL<3032> B_IWL<3031> B_IWL<3030> B_IWL<3029> B_IWL<3028> B_IWL<3027> B_IWL<3026> B_IWL<3025> B_IWL<3024> B_IWL<3023> B_IWL<3022> B_IWL<3021> B_IWL<3020> B_IWL<3019> B_IWL<3018> B_IWL<3017> B_IWL<3016> B_IWL<3015> B_IWL<3014> B_IWL<3013> B_IWL<3012> B_IWL<3011> B_IWL<3010> B_IWL<3009> B_IWL<3008> B_IWL<3007> B_IWL<3006> B_IWL<3005> B_IWL<3004> B_IWL<3003> B_IWL<3002> B_IWL<3001> B_IWL<3000> B_IWL<2999> B_IWL<2998> B_IWL<2997> B_IWL<2996> B_IWL<2995> B_IWL<2994> B_IWL<2993> B_IWL<2992> B_IWL<2991> B_IWL<2990> B_IWL<2989> B_IWL<2988> B_IWL<2987> B_IWL<2986> B_IWL<2985> B_IWL<2984> B_IWL<2983> B_IWL<2982> B_IWL<2981> B_IWL<2980> B_IWL<2979> B_IWL<2978> B_IWL<2977> B_IWL<2976> B_IWL<2975> B_IWL<2974> B_IWL<2973> B_IWL<2972> B_IWL<2971> B_IWL<2970> B_IWL<2969> B_IWL<2968> B_IWL<2967> B_IWL<2966> B_IWL<2965> B_IWL<2964> B_IWL<2963> B_IWL<2962> B_IWL<2961> B_IWL<2960> B_IWL<2959> B_IWL<2958> B_IWL<2957> B_IWL<2956> B_IWL<2955> B_IWL<2954> B_IWL<2953> B_IWL<2952> B_IWL<2951> B_IWL<2950> B_IWL<2949> B_IWL<2948> B_IWL<2947> B_IWL<2946> B_IWL<2945> B_IWL<2944> B_IWL<2943> B_IWL<2942> B_IWL<2941> B_IWL<2940> B_IWL<2939> B_IWL<2938> B_IWL<2937> B_IWL<2936> B_IWL<2935> B_IWL<2934> B_IWL<2933> B_IWL<2932> B_IWL<2931> B_IWL<2930> B_IWL<2929> B_IWL<2928> B_IWL<2927> B_IWL<2926> B_IWL<2925> B_IWL<2924> B_IWL<2923> B_IWL<2922> B_IWL<2921> B_IWL<2920> B_IWL<2919> B_IWL<2918> B_IWL<2917> B_IWL<2916> B_IWL<2915> B_IWL<2914> B_IWL<2913> B_IWL<2912> B_IWL<2911> B_IWL<2910> B_IWL<2909> B_IWL<2908> B_IWL<2907> B_IWL<2906> B_IWL<2905> B_IWL<2904> B_IWL<2903> B_IWL<2902> B_IWL<2901> B_IWL<2900> B_IWL<2899> B_IWL<2898> B_IWL<2897> B_IWL<2896> B_IWL<2895> B_IWL<2894> B_IWL<2893> B_IWL<2892> B_IWL<2891> B_IWL<2890> B_IWL<2889> B_IWL<2888> B_IWL<2887> B_IWL<2886> B_IWL<2885> B_IWL<2884> B_IWL<2883> B_IWL<2882> B_IWL<2881> B_IWL<2880> B_IWL<2879> B_IWL<2878> B_IWL<2877> B_IWL<2876> B_IWL<2875> B_IWL<2874> B_IWL<2873> B_IWL<2872> B_IWL<2871> B_IWL<2870> B_IWL<2869> B_IWL<2868> B_IWL<2867> B_IWL<2866> B_IWL<2865> B_IWL<2864> B_IWL<2863> B_IWL<2862> B_IWL<2861> B_IWL<2860> B_IWL<2859> B_IWL<2858> B_IWL<2857> B_IWL<2856> B_IWL<2855> B_IWL<2854> B_IWL<2853> B_IWL<2852> B_IWL<2851> B_IWL<2850> B_IWL<2849> B_IWL<2848> B_IWL<2847> B_IWL<2846> B_IWL<2845> B_IWL<2844> B_IWL<2843> B_IWL<2842> B_IWL<2841> B_IWL<2840> B_IWL<2839> B_IWL<2838> B_IWL<2837> B_IWL<2836> B_IWL<2835> B_IWL<2834> B_IWL<2833> B_IWL<2832> B_IWL<2831> B_IWL<2830> B_IWL<2829> B_IWL<2828> B_IWL<2827> B_IWL<2826> B_IWL<2825> B_IWL<2824> B_IWL<2823> B_IWL<2822> B_IWL<2821> B_IWL<2820> B_IWL<2819> B_IWL<2818> B_IWL<2817> B_IWL<2816> B_IWL<3327> B_IWL<3326> B_IWL<3325> B_IWL<3324> B_IWL<3323> B_IWL<3322> B_IWL<3321> B_IWL<3320> B_IWL<3319> B_IWL<3318> B_IWL<3317> B_IWL<3316> B_IWL<3315> B_IWL<3314> B_IWL<3313> B_IWL<3312> B_IWL<3311> B_IWL<3310> B_IWL<3309> B_IWL<3308> B_IWL<3307> B_IWL<3306> B_IWL<3305> B_IWL<3304> B_IWL<3303> B_IWL<3302> B_IWL<3301> B_IWL<3300> B_IWL<3299> B_IWL<3298> B_IWL<3297> B_IWL<3296> B_IWL<3295> B_IWL<3294> B_IWL<3293> B_IWL<3292> B_IWL<3291> B_IWL<3290> B_IWL<3289> B_IWL<3288> B_IWL<3287> B_IWL<3286> B_IWL<3285> B_IWL<3284> B_IWL<3283> B_IWL<3282> B_IWL<3281> B_IWL<3280> B_IWL<3279> B_IWL<3278> B_IWL<3277> B_IWL<3276> B_IWL<3275> B_IWL<3274> B_IWL<3273> B_IWL<3272> B_IWL<3271> B_IWL<3270> B_IWL<3269> B_IWL<3268> B_IWL<3267> B_IWL<3266> B_IWL<3265> B_IWL<3264> B_IWL<3263> B_IWL<3262> B_IWL<3261> B_IWL<3260> B_IWL<3259> B_IWL<3258> B_IWL<3257> B_IWL<3256> B_IWL<3255> B_IWL<3254> B_IWL<3253> B_IWL<3252> B_IWL<3251> B_IWL<3250> B_IWL<3249> B_IWL<3248> B_IWL<3247> B_IWL<3246> B_IWL<3245> B_IWL<3244> B_IWL<3243> B_IWL<3242> B_IWL<3241> B_IWL<3240> B_IWL<3239> B_IWL<3238> B_IWL<3237> B_IWL<3236> B_IWL<3235> B_IWL<3234> B_IWL<3233> B_IWL<3232> B_IWL<3231> B_IWL<3230> B_IWL<3229> B_IWL<3228> B_IWL<3227> B_IWL<3226> B_IWL<3225> B_IWL<3224> B_IWL<3223> B_IWL<3222> B_IWL<3221> B_IWL<3220> B_IWL<3219> B_IWL<3218> B_IWL<3217> B_IWL<3216> B_IWL<3215> B_IWL<3214> B_IWL<3213> B_IWL<3212> B_IWL<3211> B_IWL<3210> B_IWL<3209> B_IWL<3208> B_IWL<3207> B_IWL<3206> B_IWL<3205> B_IWL<3204> B_IWL<3203> B_IWL<3202> B_IWL<3201> B_IWL<3200> B_IWL<3199> B_IWL<3198> B_IWL<3197> B_IWL<3196> B_IWL<3195> B_IWL<3194> B_IWL<3193> B_IWL<3192> B_IWL<3191> B_IWL<3190> B_IWL<3189> B_IWL<3188> B_IWL<3187> B_IWL<3186> B_IWL<3185> B_IWL<3184> B_IWL<3183> B_IWL<3182> B_IWL<3181> B_IWL<3180> B_IWL<3179> B_IWL<3178> B_IWL<3177> B_IWL<3176> B_IWL<3175> B_IWL<3174> B_IWL<3173> B_IWL<3172> B_IWL<3171> B_IWL<3170> B_IWL<3169> B_IWL<3168> B_IWL<3167> B_IWL<3166> B_IWL<3165> B_IWL<3164> B_IWL<3163> B_IWL<3162> B_IWL<3161> B_IWL<3160> B_IWL<3159> B_IWL<3158> B_IWL<3157> B_IWL<3156> B_IWL<3155> B_IWL<3154> B_IWL<3153> B_IWL<3152> B_IWL<3151> B_IWL<3150> B_IWL<3149> B_IWL<3148> B_IWL<3147> B_IWL<3146> B_IWL<3145> B_IWL<3144> B_IWL<3143> B_IWL<3142> B_IWL<3141> B_IWL<3140> B_IWL<3139> B_IWL<3138> B_IWL<3137> B_IWL<3136> B_IWL<3135> B_IWL<3134> B_IWL<3133> B_IWL<3132> B_IWL<3131> B_IWL<3130> B_IWL<3129> B_IWL<3128> B_IWL<3127> B_IWL<3126> B_IWL<3125> B_IWL<3124> B_IWL<3123> B_IWL<3122> B_IWL<3121> B_IWL<3120> B_IWL<3119> B_IWL<3118> B_IWL<3117> B_IWL<3116> B_IWL<3115> B_IWL<3114> B_IWL<3113> B_IWL<3112> B_IWL<3111> B_IWL<3110> B_IWL<3109> B_IWL<3108> B_IWL<3107> B_IWL<3106> B_IWL<3105> B_IWL<3104> B_IWL<3103> B_IWL<3102> B_IWL<3101> B_IWL<3100> B_IWL<3099> B_IWL<3098> B_IWL<3097> B_IWL<3096> B_IWL<3095> B_IWL<3094> B_IWL<3093> B_IWL<3092> B_IWL<3091> B_IWL<3090> B_IWL<3089> B_IWL<3088> B_IWL<3087> B_IWL<3086> B_IWL<3085> B_IWL<3084> B_IWL<3083> B_IWL<3082> B_IWL<3081> B_IWL<3080> B_IWL<3079> B_IWL<3078> B_IWL<3077> B_IWL<3076> B_IWL<3075> B_IWL<3074> B_IWL<3073> B_IWL<3072> VDD_CORE VSS / RM_IHPSG13_1024x32_c2_2P_COLUMN_pcell_0 +XCOL<11> A_BLC<23> A_BLC<22> A_BLC_TOP<23> A_BLC_TOP<22> A_BLT<23> A_BLT<22> A_BLT_TOP<23> A_BLT_TOP<22> A_IWL<2815> A_IWL<2814> A_IWL<2813> A_IWL<2812> A_IWL<2811> A_IWL<2810> A_IWL<2809> A_IWL<2808> A_IWL<2807> A_IWL<2806> A_IWL<2805> A_IWL<2804> A_IWL<2803> A_IWL<2802> A_IWL<2801> A_IWL<2800> A_IWL<2799> A_IWL<2798> A_IWL<2797> A_IWL<2796> A_IWL<2795> A_IWL<2794> A_IWL<2793> A_IWL<2792> A_IWL<2791> A_IWL<2790> A_IWL<2789> A_IWL<2788> A_IWL<2787> A_IWL<2786> A_IWL<2785> A_IWL<2784> A_IWL<2783> A_IWL<2782> A_IWL<2781> A_IWL<2780> A_IWL<2779> A_IWL<2778> A_IWL<2777> A_IWL<2776> A_IWL<2775> A_IWL<2774> A_IWL<2773> A_IWL<2772> A_IWL<2771> A_IWL<2770> A_IWL<2769> A_IWL<2768> A_IWL<2767> A_IWL<2766> A_IWL<2765> A_IWL<2764> A_IWL<2763> A_IWL<2762> A_IWL<2761> A_IWL<2760> A_IWL<2759> A_IWL<2758> A_IWL<2757> A_IWL<2756> A_IWL<2755> A_IWL<2754> A_IWL<2753> A_IWL<2752> A_IWL<2751> A_IWL<2750> A_IWL<2749> A_IWL<2748> A_IWL<2747> A_IWL<2746> A_IWL<2745> A_IWL<2744> A_IWL<2743> A_IWL<2742> A_IWL<2741> A_IWL<2740> A_IWL<2739> A_IWL<2738> A_IWL<2737> A_IWL<2736> A_IWL<2735> A_IWL<2734> A_IWL<2733> A_IWL<2732> A_IWL<2731> A_IWL<2730> A_IWL<2729> A_IWL<2728> A_IWL<2727> A_IWL<2726> A_IWL<2725> A_IWL<2724> A_IWL<2723> A_IWL<2722> A_IWL<2721> A_IWL<2720> A_IWL<2719> A_IWL<2718> A_IWL<2717> A_IWL<2716> A_IWL<2715> A_IWL<2714> A_IWL<2713> A_IWL<2712> A_IWL<2711> A_IWL<2710> A_IWL<2709> A_IWL<2708> A_IWL<2707> A_IWL<2706> A_IWL<2705> A_IWL<2704> A_IWL<2703> A_IWL<2702> A_IWL<2701> A_IWL<2700> A_IWL<2699> A_IWL<2698> A_IWL<2697> A_IWL<2696> A_IWL<2695> A_IWL<2694> A_IWL<2693> A_IWL<2692> A_IWL<2691> A_IWL<2690> A_IWL<2689> A_IWL<2688> A_IWL<2687> A_IWL<2686> A_IWL<2685> A_IWL<2684> A_IWL<2683> A_IWL<2682> A_IWL<2681> A_IWL<2680> A_IWL<2679> A_IWL<2678> A_IWL<2677> A_IWL<2676> A_IWL<2675> A_IWL<2674> A_IWL<2673> A_IWL<2672> A_IWL<2671> A_IWL<2670> A_IWL<2669> A_IWL<2668> A_IWL<2667> A_IWL<2666> A_IWL<2665> A_IWL<2664> A_IWL<2663> A_IWL<2662> A_IWL<2661> A_IWL<2660> A_IWL<2659> A_IWL<2658> A_IWL<2657> A_IWL<2656> A_IWL<2655> A_IWL<2654> A_IWL<2653> A_IWL<2652> A_IWL<2651> A_IWL<2650> A_IWL<2649> A_IWL<2648> A_IWL<2647> A_IWL<2646> A_IWL<2645> A_IWL<2644> A_IWL<2643> A_IWL<2642> A_IWL<2641> A_IWL<2640> A_IWL<2639> A_IWL<2638> A_IWL<2637> A_IWL<2636> A_IWL<2635> A_IWL<2634> A_IWL<2633> A_IWL<2632> A_IWL<2631> A_IWL<2630> A_IWL<2629> A_IWL<2628> A_IWL<2627> A_IWL<2626> A_IWL<2625> A_IWL<2624> A_IWL<2623> A_IWL<2622> A_IWL<2621> A_IWL<2620> A_IWL<2619> A_IWL<2618> A_IWL<2617> A_IWL<2616> A_IWL<2615> A_IWL<2614> A_IWL<2613> A_IWL<2612> A_IWL<2611> A_IWL<2610> A_IWL<2609> A_IWL<2608> A_IWL<2607> A_IWL<2606> A_IWL<2605> A_IWL<2604> A_IWL<2603> A_IWL<2602> A_IWL<2601> A_IWL<2600> A_IWL<2599> A_IWL<2598> A_IWL<2597> A_IWL<2596> A_IWL<2595> A_IWL<2594> A_IWL<2593> A_IWL<2592> A_IWL<2591> A_IWL<2590> A_IWL<2589> A_IWL<2588> A_IWL<2587> A_IWL<2586> A_IWL<2585> A_IWL<2584> A_IWL<2583> A_IWL<2582> A_IWL<2581> A_IWL<2580> A_IWL<2579> A_IWL<2578> A_IWL<2577> A_IWL<2576> A_IWL<2575> A_IWL<2574> A_IWL<2573> A_IWL<2572> A_IWL<2571> A_IWL<2570> A_IWL<2569> A_IWL<2568> A_IWL<2567> A_IWL<2566> A_IWL<2565> A_IWL<2564> A_IWL<2563> A_IWL<2562> A_IWL<2561> A_IWL<2560> A_IWL<3071> A_IWL<3070> A_IWL<3069> A_IWL<3068> A_IWL<3067> A_IWL<3066> A_IWL<3065> A_IWL<3064> A_IWL<3063> A_IWL<3062> A_IWL<3061> A_IWL<3060> A_IWL<3059> A_IWL<3058> A_IWL<3057> A_IWL<3056> A_IWL<3055> A_IWL<3054> A_IWL<3053> A_IWL<3052> A_IWL<3051> A_IWL<3050> A_IWL<3049> A_IWL<3048> A_IWL<3047> A_IWL<3046> A_IWL<3045> A_IWL<3044> A_IWL<3043> A_IWL<3042> A_IWL<3041> A_IWL<3040> A_IWL<3039> A_IWL<3038> A_IWL<3037> A_IWL<3036> A_IWL<3035> A_IWL<3034> A_IWL<3033> A_IWL<3032> A_IWL<3031> A_IWL<3030> A_IWL<3029> A_IWL<3028> A_IWL<3027> A_IWL<3026> A_IWL<3025> A_IWL<3024> A_IWL<3023> A_IWL<3022> A_IWL<3021> A_IWL<3020> A_IWL<3019> A_IWL<3018> A_IWL<3017> A_IWL<3016> A_IWL<3015> A_IWL<3014> A_IWL<3013> A_IWL<3012> A_IWL<3011> A_IWL<3010> A_IWL<3009> A_IWL<3008> A_IWL<3007> A_IWL<3006> A_IWL<3005> A_IWL<3004> A_IWL<3003> A_IWL<3002> A_IWL<3001> A_IWL<3000> A_IWL<2999> A_IWL<2998> A_IWL<2997> A_IWL<2996> A_IWL<2995> A_IWL<2994> A_IWL<2993> A_IWL<2992> A_IWL<2991> A_IWL<2990> A_IWL<2989> A_IWL<2988> A_IWL<2987> A_IWL<2986> A_IWL<2985> A_IWL<2984> A_IWL<2983> A_IWL<2982> A_IWL<2981> A_IWL<2980> A_IWL<2979> A_IWL<2978> A_IWL<2977> A_IWL<2976> A_IWL<2975> A_IWL<2974> A_IWL<2973> A_IWL<2972> A_IWL<2971> A_IWL<2970> A_IWL<2969> A_IWL<2968> A_IWL<2967> A_IWL<2966> A_IWL<2965> A_IWL<2964> A_IWL<2963> A_IWL<2962> A_IWL<2961> A_IWL<2960> A_IWL<2959> A_IWL<2958> A_IWL<2957> A_IWL<2956> A_IWL<2955> A_IWL<2954> A_IWL<2953> A_IWL<2952> A_IWL<2951> A_IWL<2950> A_IWL<2949> A_IWL<2948> A_IWL<2947> A_IWL<2946> A_IWL<2945> A_IWL<2944> A_IWL<2943> A_IWL<2942> A_IWL<2941> A_IWL<2940> A_IWL<2939> A_IWL<2938> A_IWL<2937> A_IWL<2936> A_IWL<2935> A_IWL<2934> A_IWL<2933> A_IWL<2932> A_IWL<2931> A_IWL<2930> A_IWL<2929> A_IWL<2928> A_IWL<2927> A_IWL<2926> A_IWL<2925> A_IWL<2924> A_IWL<2923> A_IWL<2922> A_IWL<2921> A_IWL<2920> A_IWL<2919> A_IWL<2918> A_IWL<2917> A_IWL<2916> A_IWL<2915> A_IWL<2914> A_IWL<2913> A_IWL<2912> A_IWL<2911> A_IWL<2910> A_IWL<2909> A_IWL<2908> A_IWL<2907> A_IWL<2906> A_IWL<2905> A_IWL<2904> A_IWL<2903> A_IWL<2902> A_IWL<2901> A_IWL<2900> A_IWL<2899> A_IWL<2898> A_IWL<2897> A_IWL<2896> A_IWL<2895> A_IWL<2894> A_IWL<2893> A_IWL<2892> A_IWL<2891> A_IWL<2890> A_IWL<2889> A_IWL<2888> A_IWL<2887> A_IWL<2886> A_IWL<2885> A_IWL<2884> A_IWL<2883> A_IWL<2882> A_IWL<2881> A_IWL<2880> A_IWL<2879> A_IWL<2878> A_IWL<2877> A_IWL<2876> A_IWL<2875> A_IWL<2874> A_IWL<2873> A_IWL<2872> A_IWL<2871> A_IWL<2870> A_IWL<2869> A_IWL<2868> A_IWL<2867> A_IWL<2866> A_IWL<2865> A_IWL<2864> A_IWL<2863> A_IWL<2862> A_IWL<2861> A_IWL<2860> A_IWL<2859> A_IWL<2858> A_IWL<2857> A_IWL<2856> A_IWL<2855> A_IWL<2854> A_IWL<2853> A_IWL<2852> A_IWL<2851> A_IWL<2850> A_IWL<2849> A_IWL<2848> A_IWL<2847> A_IWL<2846> A_IWL<2845> A_IWL<2844> A_IWL<2843> A_IWL<2842> A_IWL<2841> A_IWL<2840> A_IWL<2839> A_IWL<2838> A_IWL<2837> A_IWL<2836> A_IWL<2835> A_IWL<2834> A_IWL<2833> A_IWL<2832> A_IWL<2831> A_IWL<2830> A_IWL<2829> A_IWL<2828> A_IWL<2827> A_IWL<2826> A_IWL<2825> A_IWL<2824> A_IWL<2823> A_IWL<2822> A_IWL<2821> A_IWL<2820> A_IWL<2819> A_IWL<2818> A_IWL<2817> A_IWL<2816> B_BLC<23> B_BLC<22> B_BLC_TOP<23> B_BLC_TOP<22> B_BLT<23> B_BLT<22> B_BLT_TOP<23> B_BLT_TOP<22> B_IWL<2815> B_IWL<2814> B_IWL<2813> B_IWL<2812> B_IWL<2811> B_IWL<2810> B_IWL<2809> B_IWL<2808> B_IWL<2807> B_IWL<2806> B_IWL<2805> B_IWL<2804> B_IWL<2803> B_IWL<2802> B_IWL<2801> B_IWL<2800> B_IWL<2799> B_IWL<2798> B_IWL<2797> B_IWL<2796> B_IWL<2795> B_IWL<2794> B_IWL<2793> B_IWL<2792> B_IWL<2791> B_IWL<2790> B_IWL<2789> B_IWL<2788> B_IWL<2787> B_IWL<2786> B_IWL<2785> B_IWL<2784> B_IWL<2783> B_IWL<2782> B_IWL<2781> B_IWL<2780> B_IWL<2779> B_IWL<2778> B_IWL<2777> B_IWL<2776> B_IWL<2775> B_IWL<2774> B_IWL<2773> B_IWL<2772> B_IWL<2771> B_IWL<2770> B_IWL<2769> B_IWL<2768> B_IWL<2767> B_IWL<2766> B_IWL<2765> B_IWL<2764> B_IWL<2763> B_IWL<2762> B_IWL<2761> B_IWL<2760> B_IWL<2759> B_IWL<2758> B_IWL<2757> B_IWL<2756> B_IWL<2755> B_IWL<2754> B_IWL<2753> B_IWL<2752> B_IWL<2751> B_IWL<2750> B_IWL<2749> B_IWL<2748> B_IWL<2747> B_IWL<2746> B_IWL<2745> B_IWL<2744> B_IWL<2743> B_IWL<2742> B_IWL<2741> B_IWL<2740> B_IWL<2739> B_IWL<2738> B_IWL<2737> B_IWL<2736> B_IWL<2735> B_IWL<2734> B_IWL<2733> B_IWL<2732> B_IWL<2731> B_IWL<2730> B_IWL<2729> B_IWL<2728> B_IWL<2727> B_IWL<2726> B_IWL<2725> B_IWL<2724> B_IWL<2723> B_IWL<2722> B_IWL<2721> B_IWL<2720> B_IWL<2719> B_IWL<2718> B_IWL<2717> B_IWL<2716> B_IWL<2715> B_IWL<2714> B_IWL<2713> B_IWL<2712> B_IWL<2711> B_IWL<2710> B_IWL<2709> B_IWL<2708> B_IWL<2707> B_IWL<2706> B_IWL<2705> B_IWL<2704> B_IWL<2703> B_IWL<2702> B_IWL<2701> B_IWL<2700> B_IWL<2699> B_IWL<2698> B_IWL<2697> B_IWL<2696> B_IWL<2695> B_IWL<2694> B_IWL<2693> B_IWL<2692> B_IWL<2691> B_IWL<2690> B_IWL<2689> B_IWL<2688> B_IWL<2687> B_IWL<2686> B_IWL<2685> B_IWL<2684> B_IWL<2683> B_IWL<2682> B_IWL<2681> B_IWL<2680> B_IWL<2679> B_IWL<2678> B_IWL<2677> B_IWL<2676> B_IWL<2675> B_IWL<2674> B_IWL<2673> B_IWL<2672> B_IWL<2671> B_IWL<2670> B_IWL<2669> B_IWL<2668> B_IWL<2667> B_IWL<2666> B_IWL<2665> B_IWL<2664> B_IWL<2663> B_IWL<2662> B_IWL<2661> B_IWL<2660> B_IWL<2659> B_IWL<2658> B_IWL<2657> B_IWL<2656> B_IWL<2655> B_IWL<2654> B_IWL<2653> B_IWL<2652> B_IWL<2651> B_IWL<2650> B_IWL<2649> B_IWL<2648> B_IWL<2647> B_IWL<2646> B_IWL<2645> B_IWL<2644> B_IWL<2643> B_IWL<2642> B_IWL<2641> B_IWL<2640> B_IWL<2639> B_IWL<2638> B_IWL<2637> B_IWL<2636> B_IWL<2635> B_IWL<2634> B_IWL<2633> B_IWL<2632> B_IWL<2631> B_IWL<2630> B_IWL<2629> B_IWL<2628> B_IWL<2627> B_IWL<2626> B_IWL<2625> B_IWL<2624> B_IWL<2623> B_IWL<2622> B_IWL<2621> B_IWL<2620> B_IWL<2619> B_IWL<2618> B_IWL<2617> B_IWL<2616> B_IWL<2615> B_IWL<2614> B_IWL<2613> B_IWL<2612> B_IWL<2611> B_IWL<2610> B_IWL<2609> B_IWL<2608> B_IWL<2607> B_IWL<2606> B_IWL<2605> B_IWL<2604> B_IWL<2603> B_IWL<2602> B_IWL<2601> B_IWL<2600> B_IWL<2599> B_IWL<2598> B_IWL<2597> B_IWL<2596> B_IWL<2595> B_IWL<2594> B_IWL<2593> B_IWL<2592> B_IWL<2591> B_IWL<2590> B_IWL<2589> B_IWL<2588> B_IWL<2587> B_IWL<2586> B_IWL<2585> B_IWL<2584> B_IWL<2583> B_IWL<2582> B_IWL<2581> B_IWL<2580> B_IWL<2579> B_IWL<2578> B_IWL<2577> B_IWL<2576> B_IWL<2575> B_IWL<2574> B_IWL<2573> B_IWL<2572> B_IWL<2571> B_IWL<2570> B_IWL<2569> B_IWL<2568> B_IWL<2567> B_IWL<2566> B_IWL<2565> B_IWL<2564> B_IWL<2563> B_IWL<2562> B_IWL<2561> B_IWL<2560> B_IWL<3071> B_IWL<3070> B_IWL<3069> B_IWL<3068> B_IWL<3067> B_IWL<3066> B_IWL<3065> B_IWL<3064> B_IWL<3063> B_IWL<3062> B_IWL<3061> B_IWL<3060> B_IWL<3059> B_IWL<3058> B_IWL<3057> B_IWL<3056> B_IWL<3055> B_IWL<3054> B_IWL<3053> B_IWL<3052> B_IWL<3051> B_IWL<3050> B_IWL<3049> B_IWL<3048> B_IWL<3047> B_IWL<3046> B_IWL<3045> B_IWL<3044> B_IWL<3043> B_IWL<3042> B_IWL<3041> B_IWL<3040> B_IWL<3039> B_IWL<3038> B_IWL<3037> B_IWL<3036> B_IWL<3035> B_IWL<3034> B_IWL<3033> B_IWL<3032> B_IWL<3031> B_IWL<3030> B_IWL<3029> B_IWL<3028> B_IWL<3027> B_IWL<3026> B_IWL<3025> B_IWL<3024> B_IWL<3023> B_IWL<3022> B_IWL<3021> B_IWL<3020> B_IWL<3019> B_IWL<3018> B_IWL<3017> B_IWL<3016> B_IWL<3015> B_IWL<3014> B_IWL<3013> B_IWL<3012> B_IWL<3011> B_IWL<3010> B_IWL<3009> B_IWL<3008> B_IWL<3007> B_IWL<3006> B_IWL<3005> B_IWL<3004> B_IWL<3003> B_IWL<3002> B_IWL<3001> B_IWL<3000> B_IWL<2999> B_IWL<2998> B_IWL<2997> B_IWL<2996> B_IWL<2995> B_IWL<2994> B_IWL<2993> B_IWL<2992> B_IWL<2991> B_IWL<2990> B_IWL<2989> B_IWL<2988> B_IWL<2987> B_IWL<2986> B_IWL<2985> B_IWL<2984> B_IWL<2983> B_IWL<2982> B_IWL<2981> B_IWL<2980> B_IWL<2979> B_IWL<2978> B_IWL<2977> B_IWL<2976> B_IWL<2975> B_IWL<2974> B_IWL<2973> B_IWL<2972> B_IWL<2971> B_IWL<2970> B_IWL<2969> B_IWL<2968> B_IWL<2967> B_IWL<2966> B_IWL<2965> B_IWL<2964> B_IWL<2963> B_IWL<2962> B_IWL<2961> B_IWL<2960> B_IWL<2959> B_IWL<2958> B_IWL<2957> B_IWL<2956> B_IWL<2955> B_IWL<2954> B_IWL<2953> B_IWL<2952> B_IWL<2951> B_IWL<2950> B_IWL<2949> B_IWL<2948> B_IWL<2947> B_IWL<2946> B_IWL<2945> B_IWL<2944> B_IWL<2943> B_IWL<2942> B_IWL<2941> B_IWL<2940> B_IWL<2939> B_IWL<2938> B_IWL<2937> B_IWL<2936> B_IWL<2935> B_IWL<2934> B_IWL<2933> B_IWL<2932> B_IWL<2931> B_IWL<2930> B_IWL<2929> B_IWL<2928> B_IWL<2927> B_IWL<2926> B_IWL<2925> B_IWL<2924> B_IWL<2923> B_IWL<2922> B_IWL<2921> B_IWL<2920> B_IWL<2919> B_IWL<2918> B_IWL<2917> B_IWL<2916> B_IWL<2915> B_IWL<2914> B_IWL<2913> B_IWL<2912> B_IWL<2911> B_IWL<2910> B_IWL<2909> B_IWL<2908> B_IWL<2907> B_IWL<2906> B_IWL<2905> B_IWL<2904> B_IWL<2903> B_IWL<2902> B_IWL<2901> B_IWL<2900> B_IWL<2899> B_IWL<2898> B_IWL<2897> B_IWL<2896> B_IWL<2895> B_IWL<2894> B_IWL<2893> B_IWL<2892> B_IWL<2891> B_IWL<2890> B_IWL<2889> B_IWL<2888> B_IWL<2887> B_IWL<2886> B_IWL<2885> B_IWL<2884> B_IWL<2883> B_IWL<2882> B_IWL<2881> B_IWL<2880> B_IWL<2879> B_IWL<2878> B_IWL<2877> B_IWL<2876> B_IWL<2875> B_IWL<2874> B_IWL<2873> B_IWL<2872> B_IWL<2871> B_IWL<2870> B_IWL<2869> B_IWL<2868> B_IWL<2867> B_IWL<2866> B_IWL<2865> B_IWL<2864> B_IWL<2863> B_IWL<2862> B_IWL<2861> B_IWL<2860> B_IWL<2859> B_IWL<2858> B_IWL<2857> B_IWL<2856> B_IWL<2855> B_IWL<2854> B_IWL<2853> B_IWL<2852> B_IWL<2851> B_IWL<2850> B_IWL<2849> B_IWL<2848> B_IWL<2847> B_IWL<2846> B_IWL<2845> B_IWL<2844> B_IWL<2843> B_IWL<2842> B_IWL<2841> B_IWL<2840> B_IWL<2839> B_IWL<2838> B_IWL<2837> B_IWL<2836> B_IWL<2835> B_IWL<2834> B_IWL<2833> B_IWL<2832> B_IWL<2831> B_IWL<2830> B_IWL<2829> B_IWL<2828> B_IWL<2827> B_IWL<2826> B_IWL<2825> B_IWL<2824> B_IWL<2823> B_IWL<2822> B_IWL<2821> B_IWL<2820> B_IWL<2819> B_IWL<2818> B_IWL<2817> B_IWL<2816> VDD_CORE VSS / RM_IHPSG13_1024x32_c2_2P_COLUMN_pcell_0 +XCOL<10> A_BLC<21> A_BLC<20> A_BLC_TOP<21> A_BLC_TOP<20> A_BLT<21> A_BLT<20> A_BLT_TOP<21> A_BLT_TOP<20> A_IWL<2559> A_IWL<2558> A_IWL<2557> A_IWL<2556> A_IWL<2555> A_IWL<2554> A_IWL<2553> A_IWL<2552> A_IWL<2551> A_IWL<2550> A_IWL<2549> A_IWL<2548> A_IWL<2547> A_IWL<2546> A_IWL<2545> A_IWL<2544> A_IWL<2543> A_IWL<2542> A_IWL<2541> A_IWL<2540> A_IWL<2539> A_IWL<2538> A_IWL<2537> A_IWL<2536> A_IWL<2535> A_IWL<2534> A_IWL<2533> A_IWL<2532> A_IWL<2531> A_IWL<2530> A_IWL<2529> A_IWL<2528> A_IWL<2527> A_IWL<2526> A_IWL<2525> A_IWL<2524> A_IWL<2523> A_IWL<2522> A_IWL<2521> A_IWL<2520> A_IWL<2519> A_IWL<2518> A_IWL<2517> A_IWL<2516> A_IWL<2515> A_IWL<2514> A_IWL<2513> A_IWL<2512> A_IWL<2511> A_IWL<2510> A_IWL<2509> A_IWL<2508> A_IWL<2507> A_IWL<2506> A_IWL<2505> A_IWL<2504> A_IWL<2503> A_IWL<2502> A_IWL<2501> A_IWL<2500> A_IWL<2499> A_IWL<2498> A_IWL<2497> A_IWL<2496> A_IWL<2495> A_IWL<2494> A_IWL<2493> A_IWL<2492> A_IWL<2491> A_IWL<2490> A_IWL<2489> A_IWL<2488> A_IWL<2487> A_IWL<2486> A_IWL<2485> A_IWL<2484> A_IWL<2483> A_IWL<2482> A_IWL<2481> A_IWL<2480> A_IWL<2479> A_IWL<2478> A_IWL<2477> A_IWL<2476> A_IWL<2475> A_IWL<2474> A_IWL<2473> A_IWL<2472> A_IWL<2471> A_IWL<2470> A_IWL<2469> A_IWL<2468> A_IWL<2467> A_IWL<2466> A_IWL<2465> A_IWL<2464> A_IWL<2463> A_IWL<2462> A_IWL<2461> A_IWL<2460> A_IWL<2459> A_IWL<2458> A_IWL<2457> A_IWL<2456> A_IWL<2455> A_IWL<2454> A_IWL<2453> A_IWL<2452> A_IWL<2451> A_IWL<2450> A_IWL<2449> A_IWL<2448> A_IWL<2447> A_IWL<2446> A_IWL<2445> A_IWL<2444> A_IWL<2443> A_IWL<2442> A_IWL<2441> A_IWL<2440> A_IWL<2439> A_IWL<2438> A_IWL<2437> A_IWL<2436> A_IWL<2435> A_IWL<2434> A_IWL<2433> A_IWL<2432> A_IWL<2431> A_IWL<2430> A_IWL<2429> A_IWL<2428> A_IWL<2427> A_IWL<2426> A_IWL<2425> A_IWL<2424> A_IWL<2423> A_IWL<2422> A_IWL<2421> A_IWL<2420> A_IWL<2419> A_IWL<2418> A_IWL<2417> A_IWL<2416> A_IWL<2415> A_IWL<2414> A_IWL<2413> A_IWL<2412> A_IWL<2411> A_IWL<2410> A_IWL<2409> A_IWL<2408> A_IWL<2407> A_IWL<2406> A_IWL<2405> A_IWL<2404> A_IWL<2403> A_IWL<2402> A_IWL<2401> A_IWL<2400> A_IWL<2399> A_IWL<2398> A_IWL<2397> A_IWL<2396> A_IWL<2395> A_IWL<2394> A_IWL<2393> A_IWL<2392> A_IWL<2391> A_IWL<2390> A_IWL<2389> A_IWL<2388> A_IWL<2387> A_IWL<2386> A_IWL<2385> A_IWL<2384> A_IWL<2383> A_IWL<2382> A_IWL<2381> A_IWL<2380> A_IWL<2379> A_IWL<2378> A_IWL<2377> A_IWL<2376> A_IWL<2375> A_IWL<2374> A_IWL<2373> A_IWL<2372> A_IWL<2371> A_IWL<2370> A_IWL<2369> A_IWL<2368> A_IWL<2367> A_IWL<2366> A_IWL<2365> A_IWL<2364> A_IWL<2363> A_IWL<2362> A_IWL<2361> A_IWL<2360> A_IWL<2359> A_IWL<2358> A_IWL<2357> A_IWL<2356> A_IWL<2355> A_IWL<2354> A_IWL<2353> A_IWL<2352> A_IWL<2351> A_IWL<2350> A_IWL<2349> A_IWL<2348> A_IWL<2347> A_IWL<2346> A_IWL<2345> A_IWL<2344> A_IWL<2343> A_IWL<2342> A_IWL<2341> A_IWL<2340> A_IWL<2339> A_IWL<2338> A_IWL<2337> A_IWL<2336> A_IWL<2335> A_IWL<2334> A_IWL<2333> A_IWL<2332> A_IWL<2331> A_IWL<2330> A_IWL<2329> A_IWL<2328> A_IWL<2327> A_IWL<2326> A_IWL<2325> A_IWL<2324> A_IWL<2323> A_IWL<2322> A_IWL<2321> A_IWL<2320> A_IWL<2319> A_IWL<2318> A_IWL<2317> A_IWL<2316> A_IWL<2315> A_IWL<2314> A_IWL<2313> A_IWL<2312> A_IWL<2311> A_IWL<2310> A_IWL<2309> A_IWL<2308> A_IWL<2307> A_IWL<2306> A_IWL<2305> A_IWL<2304> A_IWL<2815> A_IWL<2814> A_IWL<2813> A_IWL<2812> A_IWL<2811> A_IWL<2810> A_IWL<2809> A_IWL<2808> A_IWL<2807> A_IWL<2806> A_IWL<2805> A_IWL<2804> A_IWL<2803> A_IWL<2802> A_IWL<2801> A_IWL<2800> A_IWL<2799> A_IWL<2798> A_IWL<2797> A_IWL<2796> A_IWL<2795> A_IWL<2794> A_IWL<2793> A_IWL<2792> A_IWL<2791> A_IWL<2790> A_IWL<2789> A_IWL<2788> A_IWL<2787> A_IWL<2786> A_IWL<2785> A_IWL<2784> A_IWL<2783> A_IWL<2782> A_IWL<2781> A_IWL<2780> A_IWL<2779> A_IWL<2778> A_IWL<2777> A_IWL<2776> A_IWL<2775> A_IWL<2774> A_IWL<2773> A_IWL<2772> A_IWL<2771> A_IWL<2770> A_IWL<2769> A_IWL<2768> A_IWL<2767> A_IWL<2766> A_IWL<2765> A_IWL<2764> A_IWL<2763> A_IWL<2762> A_IWL<2761> A_IWL<2760> A_IWL<2759> A_IWL<2758> A_IWL<2757> A_IWL<2756> A_IWL<2755> A_IWL<2754> A_IWL<2753> A_IWL<2752> A_IWL<2751> A_IWL<2750> A_IWL<2749> A_IWL<2748> A_IWL<2747> A_IWL<2746> A_IWL<2745> A_IWL<2744> A_IWL<2743> A_IWL<2742> A_IWL<2741> A_IWL<2740> A_IWL<2739> A_IWL<2738> A_IWL<2737> A_IWL<2736> A_IWL<2735> A_IWL<2734> A_IWL<2733> A_IWL<2732> A_IWL<2731> A_IWL<2730> A_IWL<2729> A_IWL<2728> A_IWL<2727> A_IWL<2726> A_IWL<2725> A_IWL<2724> A_IWL<2723> A_IWL<2722> A_IWL<2721> A_IWL<2720> A_IWL<2719> A_IWL<2718> A_IWL<2717> A_IWL<2716> A_IWL<2715> A_IWL<2714> A_IWL<2713> A_IWL<2712> A_IWL<2711> A_IWL<2710> A_IWL<2709> A_IWL<2708> A_IWL<2707> A_IWL<2706> A_IWL<2705> A_IWL<2704> A_IWL<2703> A_IWL<2702> A_IWL<2701> A_IWL<2700> A_IWL<2699> A_IWL<2698> A_IWL<2697> A_IWL<2696> A_IWL<2695> A_IWL<2694> A_IWL<2693> A_IWL<2692> A_IWL<2691> A_IWL<2690> A_IWL<2689> A_IWL<2688> A_IWL<2687> A_IWL<2686> A_IWL<2685> A_IWL<2684> A_IWL<2683> A_IWL<2682> A_IWL<2681> A_IWL<2680> A_IWL<2679> A_IWL<2678> A_IWL<2677> A_IWL<2676> A_IWL<2675> A_IWL<2674> A_IWL<2673> A_IWL<2672> A_IWL<2671> A_IWL<2670> A_IWL<2669> A_IWL<2668> A_IWL<2667> A_IWL<2666> A_IWL<2665> A_IWL<2664> A_IWL<2663> A_IWL<2662> A_IWL<2661> A_IWL<2660> A_IWL<2659> A_IWL<2658> A_IWL<2657> A_IWL<2656> A_IWL<2655> A_IWL<2654> A_IWL<2653> A_IWL<2652> A_IWL<2651> A_IWL<2650> A_IWL<2649> A_IWL<2648> A_IWL<2647> A_IWL<2646> A_IWL<2645> A_IWL<2644> A_IWL<2643> A_IWL<2642> A_IWL<2641> A_IWL<2640> A_IWL<2639> A_IWL<2638> A_IWL<2637> A_IWL<2636> A_IWL<2635> A_IWL<2634> A_IWL<2633> A_IWL<2632> A_IWL<2631> A_IWL<2630> A_IWL<2629> A_IWL<2628> A_IWL<2627> A_IWL<2626> A_IWL<2625> A_IWL<2624> A_IWL<2623> A_IWL<2622> A_IWL<2621> A_IWL<2620> A_IWL<2619> A_IWL<2618> A_IWL<2617> A_IWL<2616> A_IWL<2615> A_IWL<2614> A_IWL<2613> A_IWL<2612> A_IWL<2611> A_IWL<2610> A_IWL<2609> A_IWL<2608> A_IWL<2607> A_IWL<2606> A_IWL<2605> A_IWL<2604> A_IWL<2603> A_IWL<2602> A_IWL<2601> A_IWL<2600> A_IWL<2599> A_IWL<2598> A_IWL<2597> A_IWL<2596> A_IWL<2595> A_IWL<2594> A_IWL<2593> A_IWL<2592> A_IWL<2591> A_IWL<2590> A_IWL<2589> A_IWL<2588> A_IWL<2587> A_IWL<2586> A_IWL<2585> A_IWL<2584> A_IWL<2583> A_IWL<2582> A_IWL<2581> A_IWL<2580> A_IWL<2579> A_IWL<2578> A_IWL<2577> A_IWL<2576> A_IWL<2575> A_IWL<2574> A_IWL<2573> A_IWL<2572> A_IWL<2571> A_IWL<2570> A_IWL<2569> A_IWL<2568> A_IWL<2567> A_IWL<2566> A_IWL<2565> A_IWL<2564> A_IWL<2563> A_IWL<2562> A_IWL<2561> A_IWL<2560> B_BLC<21> B_BLC<20> B_BLC_TOP<21> B_BLC_TOP<20> B_BLT<21> B_BLT<20> B_BLT_TOP<21> B_BLT_TOP<20> B_IWL<2559> B_IWL<2558> B_IWL<2557> B_IWL<2556> B_IWL<2555> B_IWL<2554> B_IWL<2553> B_IWL<2552> B_IWL<2551> B_IWL<2550> B_IWL<2549> B_IWL<2548> B_IWL<2547> B_IWL<2546> B_IWL<2545> B_IWL<2544> B_IWL<2543> B_IWL<2542> B_IWL<2541> B_IWL<2540> B_IWL<2539> B_IWL<2538> B_IWL<2537> B_IWL<2536> B_IWL<2535> B_IWL<2534> B_IWL<2533> B_IWL<2532> B_IWL<2531> B_IWL<2530> B_IWL<2529> B_IWL<2528> B_IWL<2527> B_IWL<2526> B_IWL<2525> B_IWL<2524> B_IWL<2523> B_IWL<2522> B_IWL<2521> B_IWL<2520> B_IWL<2519> B_IWL<2518> B_IWL<2517> B_IWL<2516> B_IWL<2515> B_IWL<2514> B_IWL<2513> B_IWL<2512> B_IWL<2511> B_IWL<2510> B_IWL<2509> B_IWL<2508> B_IWL<2507> B_IWL<2506> B_IWL<2505> B_IWL<2504> B_IWL<2503> B_IWL<2502> B_IWL<2501> B_IWL<2500> B_IWL<2499> B_IWL<2498> B_IWL<2497> B_IWL<2496> B_IWL<2495> B_IWL<2494> B_IWL<2493> B_IWL<2492> B_IWL<2491> B_IWL<2490> B_IWL<2489> B_IWL<2488> B_IWL<2487> B_IWL<2486> B_IWL<2485> B_IWL<2484> B_IWL<2483> B_IWL<2482> B_IWL<2481> B_IWL<2480> B_IWL<2479> B_IWL<2478> B_IWL<2477> B_IWL<2476> B_IWL<2475> B_IWL<2474> B_IWL<2473> B_IWL<2472> B_IWL<2471> B_IWL<2470> B_IWL<2469> B_IWL<2468> B_IWL<2467> B_IWL<2466> B_IWL<2465> B_IWL<2464> B_IWL<2463> B_IWL<2462> B_IWL<2461> B_IWL<2460> B_IWL<2459> B_IWL<2458> B_IWL<2457> B_IWL<2456> B_IWL<2455> B_IWL<2454> B_IWL<2453> B_IWL<2452> B_IWL<2451> B_IWL<2450> B_IWL<2449> B_IWL<2448> B_IWL<2447> B_IWL<2446> B_IWL<2445> B_IWL<2444> B_IWL<2443> B_IWL<2442> B_IWL<2441> B_IWL<2440> B_IWL<2439> B_IWL<2438> B_IWL<2437> B_IWL<2436> B_IWL<2435> B_IWL<2434> B_IWL<2433> B_IWL<2432> B_IWL<2431> B_IWL<2430> B_IWL<2429> B_IWL<2428> B_IWL<2427> B_IWL<2426> B_IWL<2425> B_IWL<2424> B_IWL<2423> B_IWL<2422> B_IWL<2421> B_IWL<2420> B_IWL<2419> B_IWL<2418> B_IWL<2417> B_IWL<2416> B_IWL<2415> B_IWL<2414> B_IWL<2413> B_IWL<2412> B_IWL<2411> B_IWL<2410> B_IWL<2409> B_IWL<2408> B_IWL<2407> B_IWL<2406> B_IWL<2405> B_IWL<2404> B_IWL<2403> B_IWL<2402> B_IWL<2401> B_IWL<2400> B_IWL<2399> B_IWL<2398> B_IWL<2397> B_IWL<2396> B_IWL<2395> B_IWL<2394> B_IWL<2393> B_IWL<2392> B_IWL<2391> B_IWL<2390> B_IWL<2389> B_IWL<2388> B_IWL<2387> B_IWL<2386> B_IWL<2385> B_IWL<2384> B_IWL<2383> B_IWL<2382> B_IWL<2381> B_IWL<2380> B_IWL<2379> B_IWL<2378> B_IWL<2377> B_IWL<2376> B_IWL<2375> B_IWL<2374> B_IWL<2373> B_IWL<2372> B_IWL<2371> B_IWL<2370> B_IWL<2369> B_IWL<2368> B_IWL<2367> B_IWL<2366> B_IWL<2365> B_IWL<2364> B_IWL<2363> B_IWL<2362> B_IWL<2361> B_IWL<2360> B_IWL<2359> B_IWL<2358> B_IWL<2357> B_IWL<2356> B_IWL<2355> B_IWL<2354> B_IWL<2353> B_IWL<2352> B_IWL<2351> B_IWL<2350> B_IWL<2349> B_IWL<2348> B_IWL<2347> B_IWL<2346> B_IWL<2345> B_IWL<2344> B_IWL<2343> B_IWL<2342> B_IWL<2341> B_IWL<2340> B_IWL<2339> B_IWL<2338> B_IWL<2337> B_IWL<2336> B_IWL<2335> B_IWL<2334> B_IWL<2333> B_IWL<2332> B_IWL<2331> B_IWL<2330> B_IWL<2329> B_IWL<2328> B_IWL<2327> B_IWL<2326> B_IWL<2325> B_IWL<2324> B_IWL<2323> B_IWL<2322> B_IWL<2321> B_IWL<2320> B_IWL<2319> B_IWL<2318> B_IWL<2317> B_IWL<2316> B_IWL<2315> B_IWL<2314> B_IWL<2313> B_IWL<2312> B_IWL<2311> B_IWL<2310> B_IWL<2309> B_IWL<2308> B_IWL<2307> B_IWL<2306> B_IWL<2305> B_IWL<2304> B_IWL<2815> B_IWL<2814> B_IWL<2813> B_IWL<2812> B_IWL<2811> B_IWL<2810> B_IWL<2809> B_IWL<2808> B_IWL<2807> B_IWL<2806> B_IWL<2805> B_IWL<2804> B_IWL<2803> B_IWL<2802> B_IWL<2801> B_IWL<2800> B_IWL<2799> B_IWL<2798> B_IWL<2797> B_IWL<2796> B_IWL<2795> B_IWL<2794> B_IWL<2793> B_IWL<2792> B_IWL<2791> B_IWL<2790> B_IWL<2789> B_IWL<2788> B_IWL<2787> B_IWL<2786> B_IWL<2785> B_IWL<2784> B_IWL<2783> B_IWL<2782> B_IWL<2781> B_IWL<2780> B_IWL<2779> B_IWL<2778> B_IWL<2777> B_IWL<2776> B_IWL<2775> B_IWL<2774> B_IWL<2773> B_IWL<2772> B_IWL<2771> B_IWL<2770> B_IWL<2769> B_IWL<2768> B_IWL<2767> B_IWL<2766> B_IWL<2765> B_IWL<2764> B_IWL<2763> B_IWL<2762> B_IWL<2761> B_IWL<2760> B_IWL<2759> B_IWL<2758> B_IWL<2757> B_IWL<2756> B_IWL<2755> B_IWL<2754> B_IWL<2753> B_IWL<2752> B_IWL<2751> B_IWL<2750> B_IWL<2749> B_IWL<2748> B_IWL<2747> B_IWL<2746> B_IWL<2745> B_IWL<2744> B_IWL<2743> B_IWL<2742> B_IWL<2741> B_IWL<2740> B_IWL<2739> B_IWL<2738> B_IWL<2737> B_IWL<2736> B_IWL<2735> B_IWL<2734> B_IWL<2733> B_IWL<2732> B_IWL<2731> B_IWL<2730> B_IWL<2729> B_IWL<2728> B_IWL<2727> B_IWL<2726> B_IWL<2725> B_IWL<2724> B_IWL<2723> B_IWL<2722> B_IWL<2721> B_IWL<2720> B_IWL<2719> B_IWL<2718> B_IWL<2717> B_IWL<2716> B_IWL<2715> B_IWL<2714> B_IWL<2713> B_IWL<2712> B_IWL<2711> B_IWL<2710> B_IWL<2709> B_IWL<2708> B_IWL<2707> B_IWL<2706> B_IWL<2705> B_IWL<2704> B_IWL<2703> B_IWL<2702> B_IWL<2701> B_IWL<2700> B_IWL<2699> B_IWL<2698> B_IWL<2697> B_IWL<2696> B_IWL<2695> B_IWL<2694> B_IWL<2693> B_IWL<2692> B_IWL<2691> B_IWL<2690> B_IWL<2689> B_IWL<2688> B_IWL<2687> B_IWL<2686> B_IWL<2685> B_IWL<2684> B_IWL<2683> B_IWL<2682> B_IWL<2681> B_IWL<2680> B_IWL<2679> B_IWL<2678> B_IWL<2677> B_IWL<2676> B_IWL<2675> B_IWL<2674> B_IWL<2673> B_IWL<2672> B_IWL<2671> B_IWL<2670> B_IWL<2669> B_IWL<2668> B_IWL<2667> B_IWL<2666> B_IWL<2665> B_IWL<2664> B_IWL<2663> B_IWL<2662> B_IWL<2661> B_IWL<2660> B_IWL<2659> B_IWL<2658> B_IWL<2657> B_IWL<2656> B_IWL<2655> B_IWL<2654> B_IWL<2653> B_IWL<2652> B_IWL<2651> B_IWL<2650> B_IWL<2649> B_IWL<2648> B_IWL<2647> B_IWL<2646> B_IWL<2645> B_IWL<2644> B_IWL<2643> B_IWL<2642> B_IWL<2641> B_IWL<2640> B_IWL<2639> B_IWL<2638> B_IWL<2637> B_IWL<2636> B_IWL<2635> B_IWL<2634> B_IWL<2633> B_IWL<2632> B_IWL<2631> B_IWL<2630> B_IWL<2629> B_IWL<2628> B_IWL<2627> B_IWL<2626> B_IWL<2625> B_IWL<2624> B_IWL<2623> B_IWL<2622> B_IWL<2621> B_IWL<2620> B_IWL<2619> B_IWL<2618> B_IWL<2617> B_IWL<2616> B_IWL<2615> B_IWL<2614> B_IWL<2613> B_IWL<2612> B_IWL<2611> B_IWL<2610> B_IWL<2609> B_IWL<2608> B_IWL<2607> B_IWL<2606> B_IWL<2605> B_IWL<2604> B_IWL<2603> B_IWL<2602> B_IWL<2601> B_IWL<2600> B_IWL<2599> B_IWL<2598> B_IWL<2597> B_IWL<2596> B_IWL<2595> B_IWL<2594> B_IWL<2593> B_IWL<2592> B_IWL<2591> B_IWL<2590> B_IWL<2589> B_IWL<2588> B_IWL<2587> B_IWL<2586> B_IWL<2585> B_IWL<2584> B_IWL<2583> B_IWL<2582> B_IWL<2581> B_IWL<2580> B_IWL<2579> B_IWL<2578> B_IWL<2577> B_IWL<2576> B_IWL<2575> B_IWL<2574> B_IWL<2573> B_IWL<2572> B_IWL<2571> B_IWL<2570> B_IWL<2569> B_IWL<2568> B_IWL<2567> B_IWL<2566> B_IWL<2565> B_IWL<2564> B_IWL<2563> B_IWL<2562> B_IWL<2561> B_IWL<2560> VDD_CORE VSS / RM_IHPSG13_1024x32_c2_2P_COLUMN_pcell_0 +XCOL<9> A_BLC<19> A_BLC<18> A_BLC_TOP<19> A_BLC_TOP<18> A_BLT<19> A_BLT<18> A_BLT_TOP<19> A_BLT_TOP<18> A_IWL<2303> A_IWL<2302> A_IWL<2301> A_IWL<2300> A_IWL<2299> A_IWL<2298> A_IWL<2297> A_IWL<2296> A_IWL<2295> A_IWL<2294> A_IWL<2293> A_IWL<2292> A_IWL<2291> A_IWL<2290> A_IWL<2289> A_IWL<2288> A_IWL<2287> A_IWL<2286> A_IWL<2285> A_IWL<2284> A_IWL<2283> A_IWL<2282> A_IWL<2281> A_IWL<2280> A_IWL<2279> A_IWL<2278> A_IWL<2277> A_IWL<2276> A_IWL<2275> A_IWL<2274> A_IWL<2273> A_IWL<2272> A_IWL<2271> A_IWL<2270> A_IWL<2269> A_IWL<2268> A_IWL<2267> A_IWL<2266> A_IWL<2265> A_IWL<2264> A_IWL<2263> A_IWL<2262> A_IWL<2261> A_IWL<2260> A_IWL<2259> A_IWL<2258> A_IWL<2257> A_IWL<2256> A_IWL<2255> A_IWL<2254> A_IWL<2253> A_IWL<2252> A_IWL<2251> A_IWL<2250> A_IWL<2249> A_IWL<2248> A_IWL<2247> A_IWL<2246> A_IWL<2245> A_IWL<2244> A_IWL<2243> A_IWL<2242> A_IWL<2241> A_IWL<2240> A_IWL<2239> A_IWL<2238> A_IWL<2237> A_IWL<2236> A_IWL<2235> A_IWL<2234> A_IWL<2233> A_IWL<2232> A_IWL<2231> A_IWL<2230> A_IWL<2229> A_IWL<2228> A_IWL<2227> A_IWL<2226> A_IWL<2225> A_IWL<2224> A_IWL<2223> A_IWL<2222> A_IWL<2221> A_IWL<2220> A_IWL<2219> A_IWL<2218> A_IWL<2217> A_IWL<2216> A_IWL<2215> A_IWL<2214> A_IWL<2213> A_IWL<2212> A_IWL<2211> A_IWL<2210> A_IWL<2209> A_IWL<2208> A_IWL<2207> A_IWL<2206> A_IWL<2205> A_IWL<2204> A_IWL<2203> A_IWL<2202> A_IWL<2201> A_IWL<2200> A_IWL<2199> A_IWL<2198> A_IWL<2197> A_IWL<2196> A_IWL<2195> A_IWL<2194> A_IWL<2193> A_IWL<2192> A_IWL<2191> A_IWL<2190> A_IWL<2189> A_IWL<2188> A_IWL<2187> A_IWL<2186> A_IWL<2185> A_IWL<2184> A_IWL<2183> A_IWL<2182> A_IWL<2181> A_IWL<2180> A_IWL<2179> A_IWL<2178> A_IWL<2177> A_IWL<2176> A_IWL<2175> A_IWL<2174> A_IWL<2173> A_IWL<2172> A_IWL<2171> A_IWL<2170> A_IWL<2169> A_IWL<2168> A_IWL<2167> A_IWL<2166> A_IWL<2165> A_IWL<2164> A_IWL<2163> A_IWL<2162> A_IWL<2161> A_IWL<2160> A_IWL<2159> A_IWL<2158> A_IWL<2157> A_IWL<2156> A_IWL<2155> A_IWL<2154> A_IWL<2153> A_IWL<2152> A_IWL<2151> A_IWL<2150> A_IWL<2149> A_IWL<2148> A_IWL<2147> A_IWL<2146> A_IWL<2145> A_IWL<2144> A_IWL<2143> A_IWL<2142> A_IWL<2141> A_IWL<2140> A_IWL<2139> A_IWL<2138> A_IWL<2137> A_IWL<2136> A_IWL<2135> A_IWL<2134> A_IWL<2133> A_IWL<2132> A_IWL<2131> A_IWL<2130> A_IWL<2129> A_IWL<2128> A_IWL<2127> A_IWL<2126> A_IWL<2125> A_IWL<2124> A_IWL<2123> A_IWL<2122> A_IWL<2121> A_IWL<2120> A_IWL<2119> A_IWL<2118> A_IWL<2117> A_IWL<2116> A_IWL<2115> A_IWL<2114> A_IWL<2113> A_IWL<2112> A_IWL<2111> A_IWL<2110> A_IWL<2109> A_IWL<2108> A_IWL<2107> A_IWL<2106> A_IWL<2105> A_IWL<2104> A_IWL<2103> A_IWL<2102> A_IWL<2101> A_IWL<2100> A_IWL<2099> A_IWL<2098> A_IWL<2097> A_IWL<2096> A_IWL<2095> A_IWL<2094> A_IWL<2093> A_IWL<2092> A_IWL<2091> A_IWL<2090> A_IWL<2089> A_IWL<2088> A_IWL<2087> A_IWL<2086> A_IWL<2085> A_IWL<2084> A_IWL<2083> A_IWL<2082> A_IWL<2081> A_IWL<2080> A_IWL<2079> A_IWL<2078> A_IWL<2077> A_IWL<2076> A_IWL<2075> A_IWL<2074> A_IWL<2073> A_IWL<2072> A_IWL<2071> A_IWL<2070> A_IWL<2069> A_IWL<2068> A_IWL<2067> A_IWL<2066> A_IWL<2065> A_IWL<2064> A_IWL<2063> A_IWL<2062> A_IWL<2061> A_IWL<2060> A_IWL<2059> A_IWL<2058> A_IWL<2057> A_IWL<2056> A_IWL<2055> A_IWL<2054> A_IWL<2053> A_IWL<2052> A_IWL<2051> A_IWL<2050> A_IWL<2049> A_IWL<2048> A_IWL<2559> A_IWL<2558> A_IWL<2557> A_IWL<2556> A_IWL<2555> A_IWL<2554> A_IWL<2553> A_IWL<2552> A_IWL<2551> A_IWL<2550> A_IWL<2549> A_IWL<2548> A_IWL<2547> A_IWL<2546> A_IWL<2545> A_IWL<2544> A_IWL<2543> A_IWL<2542> A_IWL<2541> A_IWL<2540> A_IWL<2539> A_IWL<2538> A_IWL<2537> A_IWL<2536> A_IWL<2535> A_IWL<2534> A_IWL<2533> A_IWL<2532> A_IWL<2531> A_IWL<2530> A_IWL<2529> A_IWL<2528> A_IWL<2527> A_IWL<2526> A_IWL<2525> A_IWL<2524> A_IWL<2523> A_IWL<2522> A_IWL<2521> A_IWL<2520> A_IWL<2519> A_IWL<2518> A_IWL<2517> A_IWL<2516> A_IWL<2515> A_IWL<2514> A_IWL<2513> A_IWL<2512> A_IWL<2511> A_IWL<2510> A_IWL<2509> A_IWL<2508> A_IWL<2507> A_IWL<2506> A_IWL<2505> A_IWL<2504> A_IWL<2503> A_IWL<2502> A_IWL<2501> A_IWL<2500> A_IWL<2499> A_IWL<2498> A_IWL<2497> A_IWL<2496> A_IWL<2495> A_IWL<2494> A_IWL<2493> A_IWL<2492> A_IWL<2491> A_IWL<2490> A_IWL<2489> A_IWL<2488> A_IWL<2487> A_IWL<2486> A_IWL<2485> A_IWL<2484> A_IWL<2483> A_IWL<2482> A_IWL<2481> A_IWL<2480> A_IWL<2479> A_IWL<2478> A_IWL<2477> A_IWL<2476> A_IWL<2475> A_IWL<2474> A_IWL<2473> A_IWL<2472> A_IWL<2471> A_IWL<2470> A_IWL<2469> A_IWL<2468> A_IWL<2467> A_IWL<2466> A_IWL<2465> A_IWL<2464> A_IWL<2463> A_IWL<2462> A_IWL<2461> A_IWL<2460> A_IWL<2459> A_IWL<2458> A_IWL<2457> A_IWL<2456> A_IWL<2455> A_IWL<2454> A_IWL<2453> A_IWL<2452> A_IWL<2451> A_IWL<2450> A_IWL<2449> A_IWL<2448> A_IWL<2447> A_IWL<2446> A_IWL<2445> A_IWL<2444> A_IWL<2443> A_IWL<2442> A_IWL<2441> A_IWL<2440> A_IWL<2439> A_IWL<2438> A_IWL<2437> A_IWL<2436> A_IWL<2435> A_IWL<2434> A_IWL<2433> A_IWL<2432> A_IWL<2431> A_IWL<2430> A_IWL<2429> A_IWL<2428> A_IWL<2427> A_IWL<2426> A_IWL<2425> A_IWL<2424> A_IWL<2423> A_IWL<2422> A_IWL<2421> A_IWL<2420> A_IWL<2419> A_IWL<2418> A_IWL<2417> A_IWL<2416> A_IWL<2415> A_IWL<2414> A_IWL<2413> A_IWL<2412> A_IWL<2411> A_IWL<2410> A_IWL<2409> A_IWL<2408> A_IWL<2407> A_IWL<2406> A_IWL<2405> A_IWL<2404> A_IWL<2403> A_IWL<2402> A_IWL<2401> A_IWL<2400> A_IWL<2399> A_IWL<2398> A_IWL<2397> A_IWL<2396> A_IWL<2395> A_IWL<2394> A_IWL<2393> A_IWL<2392> A_IWL<2391> A_IWL<2390> A_IWL<2389> A_IWL<2388> A_IWL<2387> A_IWL<2386> A_IWL<2385> A_IWL<2384> A_IWL<2383> A_IWL<2382> A_IWL<2381> A_IWL<2380> A_IWL<2379> A_IWL<2378> A_IWL<2377> A_IWL<2376> A_IWL<2375> A_IWL<2374> A_IWL<2373> A_IWL<2372> A_IWL<2371> A_IWL<2370> A_IWL<2369> A_IWL<2368> A_IWL<2367> A_IWL<2366> A_IWL<2365> A_IWL<2364> A_IWL<2363> A_IWL<2362> A_IWL<2361> A_IWL<2360> A_IWL<2359> A_IWL<2358> A_IWL<2357> A_IWL<2356> A_IWL<2355> A_IWL<2354> A_IWL<2353> A_IWL<2352> A_IWL<2351> A_IWL<2350> A_IWL<2349> A_IWL<2348> A_IWL<2347> A_IWL<2346> A_IWL<2345> A_IWL<2344> A_IWL<2343> A_IWL<2342> A_IWL<2341> A_IWL<2340> A_IWL<2339> A_IWL<2338> A_IWL<2337> A_IWL<2336> A_IWL<2335> A_IWL<2334> A_IWL<2333> A_IWL<2332> A_IWL<2331> A_IWL<2330> A_IWL<2329> A_IWL<2328> A_IWL<2327> A_IWL<2326> A_IWL<2325> A_IWL<2324> A_IWL<2323> A_IWL<2322> A_IWL<2321> A_IWL<2320> A_IWL<2319> A_IWL<2318> A_IWL<2317> A_IWL<2316> A_IWL<2315> A_IWL<2314> A_IWL<2313> A_IWL<2312> A_IWL<2311> A_IWL<2310> A_IWL<2309> A_IWL<2308> A_IWL<2307> A_IWL<2306> A_IWL<2305> A_IWL<2304> B_BLC<19> B_BLC<18> B_BLC_TOP<19> B_BLC_TOP<18> B_BLT<19> B_BLT<18> B_BLT_TOP<19> B_BLT_TOP<18> B_IWL<2303> B_IWL<2302> B_IWL<2301> B_IWL<2300> B_IWL<2299> B_IWL<2298> B_IWL<2297> B_IWL<2296> B_IWL<2295> B_IWL<2294> B_IWL<2293> B_IWL<2292> B_IWL<2291> B_IWL<2290> B_IWL<2289> B_IWL<2288> B_IWL<2287> B_IWL<2286> B_IWL<2285> B_IWL<2284> B_IWL<2283> B_IWL<2282> B_IWL<2281> B_IWL<2280> B_IWL<2279> B_IWL<2278> B_IWL<2277> B_IWL<2276> B_IWL<2275> B_IWL<2274> B_IWL<2273> B_IWL<2272> B_IWL<2271> B_IWL<2270> B_IWL<2269> B_IWL<2268> B_IWL<2267> B_IWL<2266> B_IWL<2265> B_IWL<2264> B_IWL<2263> B_IWL<2262> B_IWL<2261> B_IWL<2260> B_IWL<2259> B_IWL<2258> B_IWL<2257> B_IWL<2256> B_IWL<2255> B_IWL<2254> B_IWL<2253> B_IWL<2252> B_IWL<2251> B_IWL<2250> B_IWL<2249> B_IWL<2248> B_IWL<2247> B_IWL<2246> B_IWL<2245> B_IWL<2244> B_IWL<2243> B_IWL<2242> B_IWL<2241> B_IWL<2240> B_IWL<2239> B_IWL<2238> B_IWL<2237> B_IWL<2236> B_IWL<2235> B_IWL<2234> B_IWL<2233> B_IWL<2232> B_IWL<2231> B_IWL<2230> B_IWL<2229> B_IWL<2228> B_IWL<2227> B_IWL<2226> B_IWL<2225> B_IWL<2224> B_IWL<2223> B_IWL<2222> B_IWL<2221> B_IWL<2220> B_IWL<2219> B_IWL<2218> B_IWL<2217> B_IWL<2216> B_IWL<2215> B_IWL<2214> B_IWL<2213> B_IWL<2212> B_IWL<2211> B_IWL<2210> B_IWL<2209> B_IWL<2208> B_IWL<2207> B_IWL<2206> B_IWL<2205> B_IWL<2204> B_IWL<2203> B_IWL<2202> B_IWL<2201> B_IWL<2200> B_IWL<2199> B_IWL<2198> B_IWL<2197> B_IWL<2196> B_IWL<2195> B_IWL<2194> B_IWL<2193> B_IWL<2192> B_IWL<2191> B_IWL<2190> B_IWL<2189> B_IWL<2188> B_IWL<2187> B_IWL<2186> B_IWL<2185> B_IWL<2184> B_IWL<2183> B_IWL<2182> B_IWL<2181> B_IWL<2180> B_IWL<2179> B_IWL<2178> B_IWL<2177> B_IWL<2176> B_IWL<2175> B_IWL<2174> B_IWL<2173> B_IWL<2172> B_IWL<2171> B_IWL<2170> B_IWL<2169> B_IWL<2168> B_IWL<2167> B_IWL<2166> B_IWL<2165> B_IWL<2164> B_IWL<2163> B_IWL<2162> B_IWL<2161> B_IWL<2160> B_IWL<2159> B_IWL<2158> B_IWL<2157> B_IWL<2156> B_IWL<2155> B_IWL<2154> B_IWL<2153> B_IWL<2152> B_IWL<2151> B_IWL<2150> B_IWL<2149> B_IWL<2148> B_IWL<2147> B_IWL<2146> B_IWL<2145> B_IWL<2144> B_IWL<2143> B_IWL<2142> B_IWL<2141> B_IWL<2140> B_IWL<2139> B_IWL<2138> B_IWL<2137> B_IWL<2136> B_IWL<2135> B_IWL<2134> B_IWL<2133> B_IWL<2132> B_IWL<2131> B_IWL<2130> B_IWL<2129> B_IWL<2128> B_IWL<2127> B_IWL<2126> B_IWL<2125> B_IWL<2124> B_IWL<2123> B_IWL<2122> B_IWL<2121> B_IWL<2120> B_IWL<2119> B_IWL<2118> B_IWL<2117> B_IWL<2116> B_IWL<2115> B_IWL<2114> B_IWL<2113> B_IWL<2112> B_IWL<2111> B_IWL<2110> B_IWL<2109> B_IWL<2108> B_IWL<2107> B_IWL<2106> B_IWL<2105> B_IWL<2104> B_IWL<2103> B_IWL<2102> B_IWL<2101> B_IWL<2100> B_IWL<2099> B_IWL<2098> B_IWL<2097> B_IWL<2096> B_IWL<2095> B_IWL<2094> B_IWL<2093> B_IWL<2092> B_IWL<2091> B_IWL<2090> B_IWL<2089> B_IWL<2088> B_IWL<2087> B_IWL<2086> B_IWL<2085> B_IWL<2084> B_IWL<2083> B_IWL<2082> B_IWL<2081> B_IWL<2080> B_IWL<2079> B_IWL<2078> B_IWL<2077> B_IWL<2076> B_IWL<2075> B_IWL<2074> B_IWL<2073> B_IWL<2072> B_IWL<2071> B_IWL<2070> B_IWL<2069> B_IWL<2068> B_IWL<2067> B_IWL<2066> B_IWL<2065> B_IWL<2064> B_IWL<2063> B_IWL<2062> B_IWL<2061> B_IWL<2060> B_IWL<2059> B_IWL<2058> B_IWL<2057> B_IWL<2056> B_IWL<2055> B_IWL<2054> B_IWL<2053> B_IWL<2052> B_IWL<2051> B_IWL<2050> B_IWL<2049> B_IWL<2048> B_IWL<2559> B_IWL<2558> B_IWL<2557> B_IWL<2556> B_IWL<2555> B_IWL<2554> B_IWL<2553> B_IWL<2552> B_IWL<2551> B_IWL<2550> B_IWL<2549> B_IWL<2548> B_IWL<2547> B_IWL<2546> B_IWL<2545> B_IWL<2544> B_IWL<2543> B_IWL<2542> B_IWL<2541> B_IWL<2540> B_IWL<2539> B_IWL<2538> B_IWL<2537> B_IWL<2536> B_IWL<2535> B_IWL<2534> B_IWL<2533> B_IWL<2532> B_IWL<2531> B_IWL<2530> B_IWL<2529> B_IWL<2528> B_IWL<2527> B_IWL<2526> B_IWL<2525> B_IWL<2524> B_IWL<2523> B_IWL<2522> B_IWL<2521> B_IWL<2520> B_IWL<2519> B_IWL<2518> B_IWL<2517> B_IWL<2516> B_IWL<2515> B_IWL<2514> B_IWL<2513> B_IWL<2512> B_IWL<2511> B_IWL<2510> B_IWL<2509> B_IWL<2508> B_IWL<2507> B_IWL<2506> B_IWL<2505> B_IWL<2504> B_IWL<2503> B_IWL<2502> B_IWL<2501> B_IWL<2500> B_IWL<2499> B_IWL<2498> B_IWL<2497> B_IWL<2496> B_IWL<2495> B_IWL<2494> B_IWL<2493> B_IWL<2492> B_IWL<2491> B_IWL<2490> B_IWL<2489> B_IWL<2488> B_IWL<2487> B_IWL<2486> B_IWL<2485> B_IWL<2484> B_IWL<2483> B_IWL<2482> B_IWL<2481> B_IWL<2480> B_IWL<2479> B_IWL<2478> B_IWL<2477> B_IWL<2476> B_IWL<2475> B_IWL<2474> B_IWL<2473> B_IWL<2472> B_IWL<2471> B_IWL<2470> B_IWL<2469> B_IWL<2468> B_IWL<2467> B_IWL<2466> B_IWL<2465> B_IWL<2464> B_IWL<2463> B_IWL<2462> B_IWL<2461> B_IWL<2460> B_IWL<2459> B_IWL<2458> B_IWL<2457> B_IWL<2456> B_IWL<2455> B_IWL<2454> B_IWL<2453> B_IWL<2452> B_IWL<2451> B_IWL<2450> B_IWL<2449> B_IWL<2448> B_IWL<2447> B_IWL<2446> B_IWL<2445> B_IWL<2444> B_IWL<2443> B_IWL<2442> B_IWL<2441> B_IWL<2440> B_IWL<2439> B_IWL<2438> B_IWL<2437> B_IWL<2436> B_IWL<2435> B_IWL<2434> B_IWL<2433> B_IWL<2432> B_IWL<2431> B_IWL<2430> B_IWL<2429> B_IWL<2428> B_IWL<2427> B_IWL<2426> B_IWL<2425> B_IWL<2424> B_IWL<2423> B_IWL<2422> B_IWL<2421> B_IWL<2420> B_IWL<2419> B_IWL<2418> B_IWL<2417> B_IWL<2416> B_IWL<2415> B_IWL<2414> B_IWL<2413> B_IWL<2412> B_IWL<2411> B_IWL<2410> B_IWL<2409> B_IWL<2408> B_IWL<2407> B_IWL<2406> B_IWL<2405> B_IWL<2404> B_IWL<2403> B_IWL<2402> B_IWL<2401> B_IWL<2400> B_IWL<2399> B_IWL<2398> B_IWL<2397> B_IWL<2396> B_IWL<2395> B_IWL<2394> B_IWL<2393> B_IWL<2392> B_IWL<2391> B_IWL<2390> B_IWL<2389> B_IWL<2388> B_IWL<2387> B_IWL<2386> B_IWL<2385> B_IWL<2384> B_IWL<2383> B_IWL<2382> B_IWL<2381> B_IWL<2380> B_IWL<2379> B_IWL<2378> B_IWL<2377> B_IWL<2376> B_IWL<2375> B_IWL<2374> B_IWL<2373> B_IWL<2372> B_IWL<2371> B_IWL<2370> B_IWL<2369> B_IWL<2368> B_IWL<2367> B_IWL<2366> B_IWL<2365> B_IWL<2364> B_IWL<2363> B_IWL<2362> B_IWL<2361> B_IWL<2360> B_IWL<2359> B_IWL<2358> B_IWL<2357> B_IWL<2356> B_IWL<2355> B_IWL<2354> B_IWL<2353> B_IWL<2352> B_IWL<2351> B_IWL<2350> B_IWL<2349> B_IWL<2348> B_IWL<2347> B_IWL<2346> B_IWL<2345> B_IWL<2344> B_IWL<2343> B_IWL<2342> B_IWL<2341> B_IWL<2340> B_IWL<2339> B_IWL<2338> B_IWL<2337> B_IWL<2336> B_IWL<2335> B_IWL<2334> B_IWL<2333> B_IWL<2332> B_IWL<2331> B_IWL<2330> B_IWL<2329> B_IWL<2328> B_IWL<2327> B_IWL<2326> B_IWL<2325> B_IWL<2324> B_IWL<2323> B_IWL<2322> B_IWL<2321> B_IWL<2320> B_IWL<2319> B_IWL<2318> B_IWL<2317> B_IWL<2316> B_IWL<2315> B_IWL<2314> B_IWL<2313> B_IWL<2312> B_IWL<2311> B_IWL<2310> B_IWL<2309> B_IWL<2308> B_IWL<2307> B_IWL<2306> B_IWL<2305> B_IWL<2304> VDD_CORE VSS / RM_IHPSG13_1024x32_c2_2P_COLUMN_pcell_0 +XCOL<8> A_BLC<17> A_BLC<16> A_BLC_TOP<17> A_BLC_TOP<16> A_BLT<17> A_BLT<16> A_BLT_TOP<17> A_BLT_TOP<16> A_IWL<2047> A_IWL<2046> A_IWL<2045> A_IWL<2044> A_IWL<2043> A_IWL<2042> A_IWL<2041> A_IWL<2040> A_IWL<2039> A_IWL<2038> A_IWL<2037> A_IWL<2036> A_IWL<2035> A_IWL<2034> A_IWL<2033> A_IWL<2032> A_IWL<2031> A_IWL<2030> A_IWL<2029> A_IWL<2028> A_IWL<2027> A_IWL<2026> A_IWL<2025> A_IWL<2024> A_IWL<2023> A_IWL<2022> A_IWL<2021> A_IWL<2020> A_IWL<2019> A_IWL<2018> A_IWL<2017> A_IWL<2016> A_IWL<2015> A_IWL<2014> A_IWL<2013> A_IWL<2012> A_IWL<2011> A_IWL<2010> A_IWL<2009> A_IWL<2008> A_IWL<2007> A_IWL<2006> A_IWL<2005> A_IWL<2004> A_IWL<2003> A_IWL<2002> A_IWL<2001> A_IWL<2000> A_IWL<1999> A_IWL<1998> A_IWL<1997> A_IWL<1996> A_IWL<1995> A_IWL<1994> A_IWL<1993> A_IWL<1992> A_IWL<1991> A_IWL<1990> A_IWL<1989> A_IWL<1988> A_IWL<1987> A_IWL<1986> A_IWL<1985> A_IWL<1984> A_IWL<1983> A_IWL<1982> A_IWL<1981> A_IWL<1980> A_IWL<1979> A_IWL<1978> A_IWL<1977> A_IWL<1976> A_IWL<1975> A_IWL<1974> A_IWL<1973> A_IWL<1972> A_IWL<1971> A_IWL<1970> A_IWL<1969> A_IWL<1968> A_IWL<1967> A_IWL<1966> A_IWL<1965> A_IWL<1964> A_IWL<1963> A_IWL<1962> A_IWL<1961> A_IWL<1960> A_IWL<1959> A_IWL<1958> A_IWL<1957> A_IWL<1956> A_IWL<1955> A_IWL<1954> A_IWL<1953> A_IWL<1952> A_IWL<1951> A_IWL<1950> A_IWL<1949> A_IWL<1948> A_IWL<1947> A_IWL<1946> A_IWL<1945> A_IWL<1944> A_IWL<1943> A_IWL<1942> A_IWL<1941> A_IWL<1940> A_IWL<1939> A_IWL<1938> A_IWL<1937> A_IWL<1936> A_IWL<1935> A_IWL<1934> A_IWL<1933> A_IWL<1932> A_IWL<1931> A_IWL<1930> A_IWL<1929> A_IWL<1928> A_IWL<1927> A_IWL<1926> A_IWL<1925> A_IWL<1924> A_IWL<1923> A_IWL<1922> A_IWL<1921> A_IWL<1920> A_IWL<1919> A_IWL<1918> A_IWL<1917> A_IWL<1916> A_IWL<1915> A_IWL<1914> A_IWL<1913> A_IWL<1912> A_IWL<1911> A_IWL<1910> A_IWL<1909> A_IWL<1908> A_IWL<1907> A_IWL<1906> A_IWL<1905> A_IWL<1904> A_IWL<1903> A_IWL<1902> A_IWL<1901> A_IWL<1900> A_IWL<1899> A_IWL<1898> A_IWL<1897> A_IWL<1896> A_IWL<1895> A_IWL<1894> A_IWL<1893> A_IWL<1892> A_IWL<1891> A_IWL<1890> A_IWL<1889> A_IWL<1888> A_IWL<1887> A_IWL<1886> A_IWL<1885> A_IWL<1884> A_IWL<1883> A_IWL<1882> A_IWL<1881> A_IWL<1880> A_IWL<1879> A_IWL<1878> A_IWL<1877> A_IWL<1876> A_IWL<1875> A_IWL<1874> A_IWL<1873> A_IWL<1872> A_IWL<1871> A_IWL<1870> A_IWL<1869> A_IWL<1868> A_IWL<1867> A_IWL<1866> A_IWL<1865> A_IWL<1864> A_IWL<1863> A_IWL<1862> A_IWL<1861> A_IWL<1860> A_IWL<1859> A_IWL<1858> A_IWL<1857> A_IWL<1856> A_IWL<1855> A_IWL<1854> A_IWL<1853> A_IWL<1852> A_IWL<1851> A_IWL<1850> A_IWL<1849> A_IWL<1848> A_IWL<1847> A_IWL<1846> A_IWL<1845> A_IWL<1844> A_IWL<1843> A_IWL<1842> A_IWL<1841> A_IWL<1840> A_IWL<1839> A_IWL<1838> A_IWL<1837> A_IWL<1836> A_IWL<1835> A_IWL<1834> A_IWL<1833> A_IWL<1832> A_IWL<1831> A_IWL<1830> A_IWL<1829> A_IWL<1828> A_IWL<1827> A_IWL<1826> A_IWL<1825> A_IWL<1824> A_IWL<1823> A_IWL<1822> A_IWL<1821> A_IWL<1820> A_IWL<1819> A_IWL<1818> A_IWL<1817> A_IWL<1816> A_IWL<1815> A_IWL<1814> A_IWL<1813> A_IWL<1812> A_IWL<1811> A_IWL<1810> A_IWL<1809> A_IWL<1808> A_IWL<1807> A_IWL<1806> A_IWL<1805> A_IWL<1804> A_IWL<1803> A_IWL<1802> A_IWL<1801> A_IWL<1800> A_IWL<1799> A_IWL<1798> A_IWL<1797> A_IWL<1796> A_IWL<1795> A_IWL<1794> A_IWL<1793> A_IWL<1792> A_IWL<2303> A_IWL<2302> A_IWL<2301> A_IWL<2300> A_IWL<2299> A_IWL<2298> A_IWL<2297> A_IWL<2296> A_IWL<2295> A_IWL<2294> A_IWL<2293> A_IWL<2292> A_IWL<2291> A_IWL<2290> A_IWL<2289> A_IWL<2288> A_IWL<2287> A_IWL<2286> A_IWL<2285> A_IWL<2284> A_IWL<2283> A_IWL<2282> A_IWL<2281> A_IWL<2280> A_IWL<2279> A_IWL<2278> A_IWL<2277> A_IWL<2276> A_IWL<2275> A_IWL<2274> A_IWL<2273> A_IWL<2272> A_IWL<2271> A_IWL<2270> A_IWL<2269> A_IWL<2268> A_IWL<2267> A_IWL<2266> A_IWL<2265> A_IWL<2264> A_IWL<2263> A_IWL<2262> A_IWL<2261> A_IWL<2260> A_IWL<2259> A_IWL<2258> A_IWL<2257> A_IWL<2256> A_IWL<2255> A_IWL<2254> A_IWL<2253> A_IWL<2252> A_IWL<2251> A_IWL<2250> A_IWL<2249> A_IWL<2248> A_IWL<2247> A_IWL<2246> A_IWL<2245> A_IWL<2244> A_IWL<2243> A_IWL<2242> A_IWL<2241> A_IWL<2240> A_IWL<2239> A_IWL<2238> A_IWL<2237> A_IWL<2236> A_IWL<2235> A_IWL<2234> A_IWL<2233> A_IWL<2232> A_IWL<2231> A_IWL<2230> A_IWL<2229> A_IWL<2228> A_IWL<2227> A_IWL<2226> A_IWL<2225> A_IWL<2224> A_IWL<2223> A_IWL<2222> A_IWL<2221> A_IWL<2220> A_IWL<2219> A_IWL<2218> A_IWL<2217> A_IWL<2216> A_IWL<2215> A_IWL<2214> A_IWL<2213> A_IWL<2212> A_IWL<2211> A_IWL<2210> A_IWL<2209> A_IWL<2208> A_IWL<2207> A_IWL<2206> A_IWL<2205> A_IWL<2204> A_IWL<2203> A_IWL<2202> A_IWL<2201> A_IWL<2200> A_IWL<2199> A_IWL<2198> A_IWL<2197> A_IWL<2196> A_IWL<2195> A_IWL<2194> A_IWL<2193> A_IWL<2192> A_IWL<2191> A_IWL<2190> A_IWL<2189> A_IWL<2188> A_IWL<2187> A_IWL<2186> A_IWL<2185> A_IWL<2184> A_IWL<2183> A_IWL<2182> A_IWL<2181> A_IWL<2180> A_IWL<2179> A_IWL<2178> A_IWL<2177> A_IWL<2176> A_IWL<2175> A_IWL<2174> A_IWL<2173> A_IWL<2172> A_IWL<2171> A_IWL<2170> A_IWL<2169> A_IWL<2168> A_IWL<2167> A_IWL<2166> A_IWL<2165> A_IWL<2164> A_IWL<2163> A_IWL<2162> A_IWL<2161> A_IWL<2160> A_IWL<2159> A_IWL<2158> A_IWL<2157> A_IWL<2156> A_IWL<2155> A_IWL<2154> A_IWL<2153> A_IWL<2152> A_IWL<2151> A_IWL<2150> A_IWL<2149> A_IWL<2148> A_IWL<2147> A_IWL<2146> A_IWL<2145> A_IWL<2144> A_IWL<2143> A_IWL<2142> A_IWL<2141> A_IWL<2140> A_IWL<2139> A_IWL<2138> A_IWL<2137> A_IWL<2136> A_IWL<2135> A_IWL<2134> A_IWL<2133> A_IWL<2132> A_IWL<2131> A_IWL<2130> A_IWL<2129> A_IWL<2128> A_IWL<2127> A_IWL<2126> A_IWL<2125> A_IWL<2124> A_IWL<2123> A_IWL<2122> A_IWL<2121> A_IWL<2120> A_IWL<2119> A_IWL<2118> A_IWL<2117> A_IWL<2116> A_IWL<2115> A_IWL<2114> A_IWL<2113> A_IWL<2112> A_IWL<2111> A_IWL<2110> A_IWL<2109> A_IWL<2108> A_IWL<2107> A_IWL<2106> A_IWL<2105> A_IWL<2104> A_IWL<2103> A_IWL<2102> A_IWL<2101> A_IWL<2100> A_IWL<2099> A_IWL<2098> A_IWL<2097> A_IWL<2096> A_IWL<2095> A_IWL<2094> A_IWL<2093> A_IWL<2092> A_IWL<2091> A_IWL<2090> A_IWL<2089> A_IWL<2088> A_IWL<2087> A_IWL<2086> A_IWL<2085> A_IWL<2084> A_IWL<2083> A_IWL<2082> A_IWL<2081> A_IWL<2080> A_IWL<2079> A_IWL<2078> A_IWL<2077> A_IWL<2076> A_IWL<2075> A_IWL<2074> A_IWL<2073> A_IWL<2072> A_IWL<2071> A_IWL<2070> A_IWL<2069> A_IWL<2068> A_IWL<2067> A_IWL<2066> A_IWL<2065> A_IWL<2064> A_IWL<2063> A_IWL<2062> A_IWL<2061> A_IWL<2060> A_IWL<2059> A_IWL<2058> A_IWL<2057> A_IWL<2056> A_IWL<2055> A_IWL<2054> A_IWL<2053> A_IWL<2052> A_IWL<2051> A_IWL<2050> A_IWL<2049> A_IWL<2048> B_BLC<17> B_BLC<16> B_BLC_TOP<17> B_BLC_TOP<16> B_BLT<17> B_BLT<16> B_BLT_TOP<17> B_BLT_TOP<16> B_IWL<2047> B_IWL<2046> B_IWL<2045> B_IWL<2044> B_IWL<2043> B_IWL<2042> B_IWL<2041> B_IWL<2040> B_IWL<2039> B_IWL<2038> B_IWL<2037> B_IWL<2036> B_IWL<2035> B_IWL<2034> B_IWL<2033> B_IWL<2032> B_IWL<2031> B_IWL<2030> B_IWL<2029> B_IWL<2028> B_IWL<2027> B_IWL<2026> B_IWL<2025> B_IWL<2024> B_IWL<2023> B_IWL<2022> B_IWL<2021> B_IWL<2020> B_IWL<2019> B_IWL<2018> B_IWL<2017> B_IWL<2016> B_IWL<2015> B_IWL<2014> B_IWL<2013> B_IWL<2012> B_IWL<2011> B_IWL<2010> B_IWL<2009> B_IWL<2008> B_IWL<2007> B_IWL<2006> B_IWL<2005> B_IWL<2004> B_IWL<2003> B_IWL<2002> B_IWL<2001> B_IWL<2000> B_IWL<1999> B_IWL<1998> B_IWL<1997> B_IWL<1996> B_IWL<1995> B_IWL<1994> B_IWL<1993> B_IWL<1992> B_IWL<1991> B_IWL<1990> B_IWL<1989> B_IWL<1988> B_IWL<1987> B_IWL<1986> B_IWL<1985> B_IWL<1984> B_IWL<1983> B_IWL<1982> B_IWL<1981> B_IWL<1980> B_IWL<1979> B_IWL<1978> B_IWL<1977> B_IWL<1976> B_IWL<1975> B_IWL<1974> B_IWL<1973> B_IWL<1972> B_IWL<1971> B_IWL<1970> B_IWL<1969> B_IWL<1968> B_IWL<1967> B_IWL<1966> B_IWL<1965> B_IWL<1964> B_IWL<1963> B_IWL<1962> B_IWL<1961> B_IWL<1960> B_IWL<1959> B_IWL<1958> B_IWL<1957> B_IWL<1956> B_IWL<1955> B_IWL<1954> B_IWL<1953> B_IWL<1952> B_IWL<1951> B_IWL<1950> B_IWL<1949> B_IWL<1948> B_IWL<1947> B_IWL<1946> B_IWL<1945> B_IWL<1944> B_IWL<1943> B_IWL<1942> B_IWL<1941> B_IWL<1940> B_IWL<1939> B_IWL<1938> B_IWL<1937> B_IWL<1936> B_IWL<1935> B_IWL<1934> B_IWL<1933> B_IWL<1932> B_IWL<1931> B_IWL<1930> B_IWL<1929> B_IWL<1928> B_IWL<1927> B_IWL<1926> B_IWL<1925> B_IWL<1924> B_IWL<1923> B_IWL<1922> B_IWL<1921> B_IWL<1920> B_IWL<1919> B_IWL<1918> B_IWL<1917> B_IWL<1916> B_IWL<1915> B_IWL<1914> B_IWL<1913> B_IWL<1912> B_IWL<1911> B_IWL<1910> B_IWL<1909> B_IWL<1908> B_IWL<1907> B_IWL<1906> B_IWL<1905> B_IWL<1904> B_IWL<1903> B_IWL<1902> B_IWL<1901> B_IWL<1900> B_IWL<1899> B_IWL<1898> B_IWL<1897> B_IWL<1896> B_IWL<1895> B_IWL<1894> B_IWL<1893> B_IWL<1892> B_IWL<1891> B_IWL<1890> B_IWL<1889> B_IWL<1888> B_IWL<1887> B_IWL<1886> B_IWL<1885> B_IWL<1884> B_IWL<1883> B_IWL<1882> B_IWL<1881> B_IWL<1880> B_IWL<1879> B_IWL<1878> B_IWL<1877> B_IWL<1876> B_IWL<1875> B_IWL<1874> B_IWL<1873> B_IWL<1872> B_IWL<1871> B_IWL<1870> B_IWL<1869> B_IWL<1868> B_IWL<1867> B_IWL<1866> B_IWL<1865> B_IWL<1864> B_IWL<1863> B_IWL<1862> B_IWL<1861> B_IWL<1860> B_IWL<1859> B_IWL<1858> B_IWL<1857> B_IWL<1856> B_IWL<1855> B_IWL<1854> B_IWL<1853> B_IWL<1852> B_IWL<1851> B_IWL<1850> B_IWL<1849> B_IWL<1848> B_IWL<1847> B_IWL<1846> B_IWL<1845> B_IWL<1844> B_IWL<1843> B_IWL<1842> B_IWL<1841> B_IWL<1840> B_IWL<1839> B_IWL<1838> B_IWL<1837> B_IWL<1836> B_IWL<1835> B_IWL<1834> B_IWL<1833> B_IWL<1832> B_IWL<1831> B_IWL<1830> B_IWL<1829> B_IWL<1828> B_IWL<1827> B_IWL<1826> B_IWL<1825> B_IWL<1824> B_IWL<1823> B_IWL<1822> B_IWL<1821> B_IWL<1820> B_IWL<1819> B_IWL<1818> B_IWL<1817> B_IWL<1816> B_IWL<1815> B_IWL<1814> B_IWL<1813> B_IWL<1812> B_IWL<1811> B_IWL<1810> B_IWL<1809> B_IWL<1808> B_IWL<1807> B_IWL<1806> B_IWL<1805> B_IWL<1804> B_IWL<1803> B_IWL<1802> B_IWL<1801> B_IWL<1800> B_IWL<1799> B_IWL<1798> B_IWL<1797> B_IWL<1796> B_IWL<1795> B_IWL<1794> B_IWL<1793> B_IWL<1792> B_IWL<2303> B_IWL<2302> B_IWL<2301> B_IWL<2300> B_IWL<2299> B_IWL<2298> B_IWL<2297> B_IWL<2296> B_IWL<2295> B_IWL<2294> B_IWL<2293> B_IWL<2292> B_IWL<2291> B_IWL<2290> B_IWL<2289> B_IWL<2288> B_IWL<2287> B_IWL<2286> B_IWL<2285> B_IWL<2284> B_IWL<2283> B_IWL<2282> B_IWL<2281> B_IWL<2280> B_IWL<2279> B_IWL<2278> B_IWL<2277> B_IWL<2276> B_IWL<2275> B_IWL<2274> B_IWL<2273> B_IWL<2272> B_IWL<2271> B_IWL<2270> B_IWL<2269> B_IWL<2268> B_IWL<2267> B_IWL<2266> B_IWL<2265> B_IWL<2264> B_IWL<2263> B_IWL<2262> B_IWL<2261> B_IWL<2260> B_IWL<2259> B_IWL<2258> B_IWL<2257> B_IWL<2256> B_IWL<2255> B_IWL<2254> B_IWL<2253> B_IWL<2252> B_IWL<2251> B_IWL<2250> B_IWL<2249> B_IWL<2248> B_IWL<2247> B_IWL<2246> B_IWL<2245> B_IWL<2244> B_IWL<2243> B_IWL<2242> B_IWL<2241> B_IWL<2240> B_IWL<2239> B_IWL<2238> B_IWL<2237> B_IWL<2236> B_IWL<2235> B_IWL<2234> B_IWL<2233> B_IWL<2232> B_IWL<2231> B_IWL<2230> B_IWL<2229> B_IWL<2228> B_IWL<2227> B_IWL<2226> B_IWL<2225> B_IWL<2224> B_IWL<2223> B_IWL<2222> B_IWL<2221> B_IWL<2220> B_IWL<2219> B_IWL<2218> B_IWL<2217> B_IWL<2216> B_IWL<2215> B_IWL<2214> B_IWL<2213> B_IWL<2212> B_IWL<2211> B_IWL<2210> B_IWL<2209> B_IWL<2208> B_IWL<2207> B_IWL<2206> B_IWL<2205> B_IWL<2204> B_IWL<2203> B_IWL<2202> B_IWL<2201> B_IWL<2200> B_IWL<2199> B_IWL<2198> B_IWL<2197> B_IWL<2196> B_IWL<2195> B_IWL<2194> B_IWL<2193> B_IWL<2192> B_IWL<2191> B_IWL<2190> B_IWL<2189> B_IWL<2188> B_IWL<2187> B_IWL<2186> B_IWL<2185> B_IWL<2184> B_IWL<2183> B_IWL<2182> B_IWL<2181> B_IWL<2180> B_IWL<2179> B_IWL<2178> B_IWL<2177> B_IWL<2176> B_IWL<2175> B_IWL<2174> B_IWL<2173> B_IWL<2172> B_IWL<2171> B_IWL<2170> B_IWL<2169> B_IWL<2168> B_IWL<2167> B_IWL<2166> B_IWL<2165> B_IWL<2164> B_IWL<2163> B_IWL<2162> B_IWL<2161> B_IWL<2160> B_IWL<2159> B_IWL<2158> B_IWL<2157> B_IWL<2156> B_IWL<2155> B_IWL<2154> B_IWL<2153> B_IWL<2152> B_IWL<2151> B_IWL<2150> B_IWL<2149> B_IWL<2148> B_IWL<2147> B_IWL<2146> B_IWL<2145> B_IWL<2144> B_IWL<2143> B_IWL<2142> B_IWL<2141> B_IWL<2140> B_IWL<2139> B_IWL<2138> B_IWL<2137> B_IWL<2136> B_IWL<2135> B_IWL<2134> B_IWL<2133> B_IWL<2132> B_IWL<2131> B_IWL<2130> B_IWL<2129> B_IWL<2128> B_IWL<2127> B_IWL<2126> B_IWL<2125> B_IWL<2124> B_IWL<2123> B_IWL<2122> B_IWL<2121> B_IWL<2120> B_IWL<2119> B_IWL<2118> B_IWL<2117> B_IWL<2116> B_IWL<2115> B_IWL<2114> B_IWL<2113> B_IWL<2112> B_IWL<2111> B_IWL<2110> B_IWL<2109> B_IWL<2108> B_IWL<2107> B_IWL<2106> B_IWL<2105> B_IWL<2104> B_IWL<2103> B_IWL<2102> B_IWL<2101> B_IWL<2100> B_IWL<2099> B_IWL<2098> B_IWL<2097> B_IWL<2096> B_IWL<2095> B_IWL<2094> B_IWL<2093> B_IWL<2092> B_IWL<2091> B_IWL<2090> B_IWL<2089> B_IWL<2088> B_IWL<2087> B_IWL<2086> B_IWL<2085> B_IWL<2084> B_IWL<2083> B_IWL<2082> B_IWL<2081> B_IWL<2080> B_IWL<2079> B_IWL<2078> B_IWL<2077> B_IWL<2076> B_IWL<2075> B_IWL<2074> B_IWL<2073> B_IWL<2072> B_IWL<2071> B_IWL<2070> B_IWL<2069> B_IWL<2068> B_IWL<2067> B_IWL<2066> B_IWL<2065> B_IWL<2064> B_IWL<2063> B_IWL<2062> B_IWL<2061> B_IWL<2060> B_IWL<2059> B_IWL<2058> B_IWL<2057> B_IWL<2056> B_IWL<2055> B_IWL<2054> B_IWL<2053> B_IWL<2052> B_IWL<2051> B_IWL<2050> B_IWL<2049> B_IWL<2048> VDD_CORE VSS / RM_IHPSG13_1024x32_c2_2P_COLUMN_pcell_0 +XCOL<7> A_BLC<15> A_BLC<14> A_BLC_TOP<15> A_BLC_TOP<14> A_BLT<15> A_BLT<14> A_BLT_TOP<15> A_BLT_TOP<14> A_IWL<1791> A_IWL<1790> A_IWL<1789> A_IWL<1788> A_IWL<1787> A_IWL<1786> A_IWL<1785> A_IWL<1784> A_IWL<1783> A_IWL<1782> A_IWL<1781> A_IWL<1780> A_IWL<1779> A_IWL<1778> A_IWL<1777> A_IWL<1776> A_IWL<1775> A_IWL<1774> A_IWL<1773> A_IWL<1772> A_IWL<1771> A_IWL<1770> A_IWL<1769> A_IWL<1768> A_IWL<1767> A_IWL<1766> A_IWL<1765> A_IWL<1764> A_IWL<1763> A_IWL<1762> A_IWL<1761> A_IWL<1760> A_IWL<1759> A_IWL<1758> A_IWL<1757> A_IWL<1756> A_IWL<1755> A_IWL<1754> A_IWL<1753> A_IWL<1752> A_IWL<1751> A_IWL<1750> A_IWL<1749> A_IWL<1748> A_IWL<1747> A_IWL<1746> A_IWL<1745> A_IWL<1744> A_IWL<1743> A_IWL<1742> A_IWL<1741> A_IWL<1740> A_IWL<1739> A_IWL<1738> A_IWL<1737> A_IWL<1736> A_IWL<1735> A_IWL<1734> A_IWL<1733> A_IWL<1732> A_IWL<1731> A_IWL<1730> A_IWL<1729> A_IWL<1728> A_IWL<1727> A_IWL<1726> A_IWL<1725> A_IWL<1724> A_IWL<1723> A_IWL<1722> A_IWL<1721> A_IWL<1720> A_IWL<1719> A_IWL<1718> A_IWL<1717> A_IWL<1716> A_IWL<1715> A_IWL<1714> A_IWL<1713> A_IWL<1712> A_IWL<1711> A_IWL<1710> A_IWL<1709> A_IWL<1708> A_IWL<1707> A_IWL<1706> A_IWL<1705> A_IWL<1704> A_IWL<1703> A_IWL<1702> A_IWL<1701> A_IWL<1700> A_IWL<1699> A_IWL<1698> A_IWL<1697> A_IWL<1696> A_IWL<1695> A_IWL<1694> A_IWL<1693> A_IWL<1692> A_IWL<1691> A_IWL<1690> A_IWL<1689> A_IWL<1688> A_IWL<1687> A_IWL<1686> A_IWL<1685> A_IWL<1684> A_IWL<1683> A_IWL<1682> A_IWL<1681> A_IWL<1680> A_IWL<1679> A_IWL<1678> A_IWL<1677> A_IWL<1676> A_IWL<1675> A_IWL<1674> A_IWL<1673> A_IWL<1672> A_IWL<1671> A_IWL<1670> A_IWL<1669> A_IWL<1668> A_IWL<1667> A_IWL<1666> A_IWL<1665> A_IWL<1664> A_IWL<1663> A_IWL<1662> A_IWL<1661> A_IWL<1660> A_IWL<1659> A_IWL<1658> A_IWL<1657> A_IWL<1656> A_IWL<1655> A_IWL<1654> A_IWL<1653> A_IWL<1652> A_IWL<1651> A_IWL<1650> A_IWL<1649> A_IWL<1648> A_IWL<1647> A_IWL<1646> A_IWL<1645> A_IWL<1644> A_IWL<1643> A_IWL<1642> A_IWL<1641> A_IWL<1640> A_IWL<1639> A_IWL<1638> A_IWL<1637> A_IWL<1636> A_IWL<1635> A_IWL<1634> A_IWL<1633> A_IWL<1632> A_IWL<1631> A_IWL<1630> A_IWL<1629> A_IWL<1628> A_IWL<1627> A_IWL<1626> A_IWL<1625> A_IWL<1624> A_IWL<1623> A_IWL<1622> A_IWL<1621> A_IWL<1620> A_IWL<1619> A_IWL<1618> A_IWL<1617> A_IWL<1616> A_IWL<1615> A_IWL<1614> A_IWL<1613> A_IWL<1612> A_IWL<1611> A_IWL<1610> A_IWL<1609> A_IWL<1608> A_IWL<1607> A_IWL<1606> A_IWL<1605> A_IWL<1604> A_IWL<1603> A_IWL<1602> A_IWL<1601> A_IWL<1600> A_IWL<1599> A_IWL<1598> A_IWL<1597> A_IWL<1596> A_IWL<1595> A_IWL<1594> A_IWL<1593> A_IWL<1592> A_IWL<1591> A_IWL<1590> A_IWL<1589> A_IWL<1588> A_IWL<1587> A_IWL<1586> A_IWL<1585> A_IWL<1584> A_IWL<1583> A_IWL<1582> A_IWL<1581> A_IWL<1580> A_IWL<1579> A_IWL<1578> A_IWL<1577> A_IWL<1576> A_IWL<1575> A_IWL<1574> A_IWL<1573> A_IWL<1572> A_IWL<1571> A_IWL<1570> A_IWL<1569> A_IWL<1568> A_IWL<1567> A_IWL<1566> A_IWL<1565> A_IWL<1564> A_IWL<1563> A_IWL<1562> A_IWL<1561> A_IWL<1560> A_IWL<1559> A_IWL<1558> A_IWL<1557> A_IWL<1556> A_IWL<1555> A_IWL<1554> A_IWL<1553> A_IWL<1552> A_IWL<1551> A_IWL<1550> A_IWL<1549> A_IWL<1548> A_IWL<1547> A_IWL<1546> A_IWL<1545> A_IWL<1544> A_IWL<1543> A_IWL<1542> A_IWL<1541> A_IWL<1540> A_IWL<1539> A_IWL<1538> A_IWL<1537> A_IWL<1536> A_IWL<2047> A_IWL<2046> A_IWL<2045> A_IWL<2044> A_IWL<2043> A_IWL<2042> A_IWL<2041> A_IWL<2040> A_IWL<2039> A_IWL<2038> A_IWL<2037> A_IWL<2036> A_IWL<2035> A_IWL<2034> A_IWL<2033> A_IWL<2032> A_IWL<2031> A_IWL<2030> A_IWL<2029> A_IWL<2028> A_IWL<2027> A_IWL<2026> A_IWL<2025> A_IWL<2024> A_IWL<2023> A_IWL<2022> A_IWL<2021> A_IWL<2020> A_IWL<2019> A_IWL<2018> A_IWL<2017> A_IWL<2016> A_IWL<2015> A_IWL<2014> A_IWL<2013> A_IWL<2012> A_IWL<2011> A_IWL<2010> A_IWL<2009> A_IWL<2008> A_IWL<2007> A_IWL<2006> A_IWL<2005> A_IWL<2004> A_IWL<2003> A_IWL<2002> A_IWL<2001> A_IWL<2000> A_IWL<1999> A_IWL<1998> A_IWL<1997> A_IWL<1996> A_IWL<1995> A_IWL<1994> A_IWL<1993> A_IWL<1992> A_IWL<1991> A_IWL<1990> A_IWL<1989> A_IWL<1988> A_IWL<1987> A_IWL<1986> A_IWL<1985> A_IWL<1984> A_IWL<1983> A_IWL<1982> A_IWL<1981> A_IWL<1980> A_IWL<1979> A_IWL<1978> A_IWL<1977> A_IWL<1976> A_IWL<1975> A_IWL<1974> A_IWL<1973> A_IWL<1972> A_IWL<1971> A_IWL<1970> A_IWL<1969> A_IWL<1968> A_IWL<1967> A_IWL<1966> A_IWL<1965> A_IWL<1964> A_IWL<1963> A_IWL<1962> A_IWL<1961> A_IWL<1960> A_IWL<1959> A_IWL<1958> A_IWL<1957> A_IWL<1956> A_IWL<1955> A_IWL<1954> A_IWL<1953> A_IWL<1952> A_IWL<1951> A_IWL<1950> A_IWL<1949> A_IWL<1948> A_IWL<1947> A_IWL<1946> A_IWL<1945> A_IWL<1944> A_IWL<1943> A_IWL<1942> A_IWL<1941> A_IWL<1940> A_IWL<1939> A_IWL<1938> A_IWL<1937> A_IWL<1936> A_IWL<1935> A_IWL<1934> A_IWL<1933> A_IWL<1932> A_IWL<1931> A_IWL<1930> A_IWL<1929> A_IWL<1928> A_IWL<1927> A_IWL<1926> A_IWL<1925> A_IWL<1924> A_IWL<1923> A_IWL<1922> A_IWL<1921> A_IWL<1920> A_IWL<1919> A_IWL<1918> A_IWL<1917> A_IWL<1916> A_IWL<1915> A_IWL<1914> A_IWL<1913> A_IWL<1912> A_IWL<1911> A_IWL<1910> A_IWL<1909> A_IWL<1908> A_IWL<1907> A_IWL<1906> A_IWL<1905> A_IWL<1904> A_IWL<1903> A_IWL<1902> A_IWL<1901> A_IWL<1900> A_IWL<1899> A_IWL<1898> A_IWL<1897> A_IWL<1896> A_IWL<1895> A_IWL<1894> A_IWL<1893> A_IWL<1892> A_IWL<1891> A_IWL<1890> A_IWL<1889> A_IWL<1888> A_IWL<1887> A_IWL<1886> A_IWL<1885> A_IWL<1884> A_IWL<1883> A_IWL<1882> A_IWL<1881> A_IWL<1880> A_IWL<1879> A_IWL<1878> A_IWL<1877> A_IWL<1876> A_IWL<1875> A_IWL<1874> A_IWL<1873> A_IWL<1872> A_IWL<1871> A_IWL<1870> A_IWL<1869> A_IWL<1868> A_IWL<1867> A_IWL<1866> A_IWL<1865> A_IWL<1864> A_IWL<1863> A_IWL<1862> A_IWL<1861> A_IWL<1860> A_IWL<1859> A_IWL<1858> A_IWL<1857> A_IWL<1856> A_IWL<1855> A_IWL<1854> A_IWL<1853> A_IWL<1852> A_IWL<1851> A_IWL<1850> A_IWL<1849> A_IWL<1848> A_IWL<1847> A_IWL<1846> A_IWL<1845> A_IWL<1844> A_IWL<1843> A_IWL<1842> A_IWL<1841> A_IWL<1840> A_IWL<1839> A_IWL<1838> A_IWL<1837> A_IWL<1836> A_IWL<1835> A_IWL<1834> A_IWL<1833> A_IWL<1832> A_IWL<1831> A_IWL<1830> A_IWL<1829> A_IWL<1828> A_IWL<1827> A_IWL<1826> A_IWL<1825> A_IWL<1824> A_IWL<1823> A_IWL<1822> A_IWL<1821> A_IWL<1820> A_IWL<1819> A_IWL<1818> A_IWL<1817> A_IWL<1816> A_IWL<1815> A_IWL<1814> A_IWL<1813> A_IWL<1812> A_IWL<1811> A_IWL<1810> A_IWL<1809> A_IWL<1808> A_IWL<1807> A_IWL<1806> A_IWL<1805> A_IWL<1804> A_IWL<1803> A_IWL<1802> A_IWL<1801> A_IWL<1800> A_IWL<1799> A_IWL<1798> A_IWL<1797> A_IWL<1796> A_IWL<1795> A_IWL<1794> A_IWL<1793> A_IWL<1792> B_BLC<15> B_BLC<14> B_BLC_TOP<15> B_BLC_TOP<14> B_BLT<15> B_BLT<14> B_BLT_TOP<15> B_BLT_TOP<14> B_IWL<1791> B_IWL<1790> B_IWL<1789> B_IWL<1788> B_IWL<1787> B_IWL<1786> B_IWL<1785> B_IWL<1784> B_IWL<1783> B_IWL<1782> B_IWL<1781> B_IWL<1780> B_IWL<1779> B_IWL<1778> B_IWL<1777> B_IWL<1776> B_IWL<1775> B_IWL<1774> B_IWL<1773> B_IWL<1772> B_IWL<1771> B_IWL<1770> B_IWL<1769> B_IWL<1768> B_IWL<1767> B_IWL<1766> B_IWL<1765> B_IWL<1764> B_IWL<1763> B_IWL<1762> B_IWL<1761> B_IWL<1760> B_IWL<1759> B_IWL<1758> B_IWL<1757> B_IWL<1756> B_IWL<1755> B_IWL<1754> B_IWL<1753> B_IWL<1752> B_IWL<1751> B_IWL<1750> B_IWL<1749> B_IWL<1748> B_IWL<1747> B_IWL<1746> B_IWL<1745> B_IWL<1744> B_IWL<1743> B_IWL<1742> B_IWL<1741> B_IWL<1740> B_IWL<1739> B_IWL<1738> B_IWL<1737> B_IWL<1736> B_IWL<1735> B_IWL<1734> B_IWL<1733> B_IWL<1732> B_IWL<1731> B_IWL<1730> B_IWL<1729> B_IWL<1728> B_IWL<1727> B_IWL<1726> B_IWL<1725> B_IWL<1724> B_IWL<1723> B_IWL<1722> B_IWL<1721> B_IWL<1720> B_IWL<1719> B_IWL<1718> B_IWL<1717> B_IWL<1716> B_IWL<1715> B_IWL<1714> B_IWL<1713> B_IWL<1712> B_IWL<1711> B_IWL<1710> B_IWL<1709> B_IWL<1708> B_IWL<1707> B_IWL<1706> B_IWL<1705> B_IWL<1704> B_IWL<1703> B_IWL<1702> B_IWL<1701> B_IWL<1700> B_IWL<1699> B_IWL<1698> B_IWL<1697> B_IWL<1696> B_IWL<1695> B_IWL<1694> B_IWL<1693> B_IWL<1692> B_IWL<1691> B_IWL<1690> B_IWL<1689> B_IWL<1688> B_IWL<1687> B_IWL<1686> B_IWL<1685> B_IWL<1684> B_IWL<1683> B_IWL<1682> B_IWL<1681> B_IWL<1680> B_IWL<1679> B_IWL<1678> B_IWL<1677> B_IWL<1676> B_IWL<1675> B_IWL<1674> B_IWL<1673> B_IWL<1672> B_IWL<1671> B_IWL<1670> B_IWL<1669> B_IWL<1668> B_IWL<1667> B_IWL<1666> B_IWL<1665> B_IWL<1664> B_IWL<1663> B_IWL<1662> B_IWL<1661> B_IWL<1660> B_IWL<1659> B_IWL<1658> B_IWL<1657> B_IWL<1656> B_IWL<1655> B_IWL<1654> B_IWL<1653> B_IWL<1652> B_IWL<1651> B_IWL<1650> B_IWL<1649> B_IWL<1648> B_IWL<1647> B_IWL<1646> B_IWL<1645> B_IWL<1644> B_IWL<1643> B_IWL<1642> B_IWL<1641> B_IWL<1640> B_IWL<1639> B_IWL<1638> B_IWL<1637> B_IWL<1636> B_IWL<1635> B_IWL<1634> B_IWL<1633> B_IWL<1632> B_IWL<1631> B_IWL<1630> B_IWL<1629> B_IWL<1628> B_IWL<1627> B_IWL<1626> B_IWL<1625> B_IWL<1624> B_IWL<1623> B_IWL<1622> B_IWL<1621> B_IWL<1620> B_IWL<1619> B_IWL<1618> B_IWL<1617> B_IWL<1616> B_IWL<1615> B_IWL<1614> B_IWL<1613> B_IWL<1612> B_IWL<1611> B_IWL<1610> B_IWL<1609> B_IWL<1608> B_IWL<1607> B_IWL<1606> B_IWL<1605> B_IWL<1604> B_IWL<1603> B_IWL<1602> B_IWL<1601> B_IWL<1600> B_IWL<1599> B_IWL<1598> B_IWL<1597> B_IWL<1596> B_IWL<1595> B_IWL<1594> B_IWL<1593> B_IWL<1592> B_IWL<1591> B_IWL<1590> B_IWL<1589> B_IWL<1588> B_IWL<1587> B_IWL<1586> B_IWL<1585> B_IWL<1584> B_IWL<1583> B_IWL<1582> B_IWL<1581> B_IWL<1580> B_IWL<1579> B_IWL<1578> B_IWL<1577> B_IWL<1576> B_IWL<1575> B_IWL<1574> B_IWL<1573> B_IWL<1572> B_IWL<1571> B_IWL<1570> B_IWL<1569> B_IWL<1568> B_IWL<1567> B_IWL<1566> B_IWL<1565> B_IWL<1564> B_IWL<1563> B_IWL<1562> B_IWL<1561> B_IWL<1560> B_IWL<1559> B_IWL<1558> B_IWL<1557> B_IWL<1556> B_IWL<1555> B_IWL<1554> B_IWL<1553> B_IWL<1552> B_IWL<1551> B_IWL<1550> B_IWL<1549> B_IWL<1548> B_IWL<1547> B_IWL<1546> B_IWL<1545> B_IWL<1544> B_IWL<1543> B_IWL<1542> B_IWL<1541> B_IWL<1540> B_IWL<1539> B_IWL<1538> B_IWL<1537> B_IWL<1536> B_IWL<2047> B_IWL<2046> B_IWL<2045> B_IWL<2044> B_IWL<2043> B_IWL<2042> B_IWL<2041> B_IWL<2040> B_IWL<2039> B_IWL<2038> B_IWL<2037> B_IWL<2036> B_IWL<2035> B_IWL<2034> B_IWL<2033> B_IWL<2032> B_IWL<2031> B_IWL<2030> B_IWL<2029> B_IWL<2028> B_IWL<2027> B_IWL<2026> B_IWL<2025> B_IWL<2024> B_IWL<2023> B_IWL<2022> B_IWL<2021> B_IWL<2020> B_IWL<2019> B_IWL<2018> B_IWL<2017> B_IWL<2016> B_IWL<2015> B_IWL<2014> B_IWL<2013> B_IWL<2012> B_IWL<2011> B_IWL<2010> B_IWL<2009> B_IWL<2008> B_IWL<2007> B_IWL<2006> B_IWL<2005> B_IWL<2004> B_IWL<2003> B_IWL<2002> B_IWL<2001> B_IWL<2000> B_IWL<1999> B_IWL<1998> B_IWL<1997> B_IWL<1996> B_IWL<1995> B_IWL<1994> B_IWL<1993> B_IWL<1992> B_IWL<1991> B_IWL<1990> B_IWL<1989> B_IWL<1988> B_IWL<1987> B_IWL<1986> B_IWL<1985> B_IWL<1984> B_IWL<1983> B_IWL<1982> B_IWL<1981> B_IWL<1980> B_IWL<1979> B_IWL<1978> B_IWL<1977> B_IWL<1976> B_IWL<1975> B_IWL<1974> B_IWL<1973> B_IWL<1972> B_IWL<1971> B_IWL<1970> B_IWL<1969> B_IWL<1968> B_IWL<1967> B_IWL<1966> B_IWL<1965> B_IWL<1964> B_IWL<1963> B_IWL<1962> B_IWL<1961> B_IWL<1960> B_IWL<1959> B_IWL<1958> B_IWL<1957> B_IWL<1956> B_IWL<1955> B_IWL<1954> B_IWL<1953> B_IWL<1952> B_IWL<1951> B_IWL<1950> B_IWL<1949> B_IWL<1948> B_IWL<1947> B_IWL<1946> B_IWL<1945> B_IWL<1944> B_IWL<1943> B_IWL<1942> B_IWL<1941> B_IWL<1940> B_IWL<1939> B_IWL<1938> B_IWL<1937> B_IWL<1936> B_IWL<1935> B_IWL<1934> B_IWL<1933> B_IWL<1932> B_IWL<1931> B_IWL<1930> B_IWL<1929> B_IWL<1928> B_IWL<1927> B_IWL<1926> B_IWL<1925> B_IWL<1924> B_IWL<1923> B_IWL<1922> B_IWL<1921> B_IWL<1920> B_IWL<1919> B_IWL<1918> B_IWL<1917> B_IWL<1916> B_IWL<1915> B_IWL<1914> B_IWL<1913> B_IWL<1912> B_IWL<1911> B_IWL<1910> B_IWL<1909> B_IWL<1908> B_IWL<1907> B_IWL<1906> B_IWL<1905> B_IWL<1904> B_IWL<1903> B_IWL<1902> B_IWL<1901> B_IWL<1900> B_IWL<1899> B_IWL<1898> B_IWL<1897> B_IWL<1896> B_IWL<1895> B_IWL<1894> B_IWL<1893> B_IWL<1892> B_IWL<1891> B_IWL<1890> B_IWL<1889> B_IWL<1888> B_IWL<1887> B_IWL<1886> B_IWL<1885> B_IWL<1884> B_IWL<1883> B_IWL<1882> B_IWL<1881> B_IWL<1880> B_IWL<1879> B_IWL<1878> B_IWL<1877> B_IWL<1876> B_IWL<1875> B_IWL<1874> B_IWL<1873> B_IWL<1872> B_IWL<1871> B_IWL<1870> B_IWL<1869> B_IWL<1868> B_IWL<1867> B_IWL<1866> B_IWL<1865> B_IWL<1864> B_IWL<1863> B_IWL<1862> B_IWL<1861> B_IWL<1860> B_IWL<1859> B_IWL<1858> B_IWL<1857> B_IWL<1856> B_IWL<1855> B_IWL<1854> B_IWL<1853> B_IWL<1852> B_IWL<1851> B_IWL<1850> B_IWL<1849> B_IWL<1848> B_IWL<1847> B_IWL<1846> B_IWL<1845> B_IWL<1844> B_IWL<1843> B_IWL<1842> B_IWL<1841> B_IWL<1840> B_IWL<1839> B_IWL<1838> B_IWL<1837> B_IWL<1836> B_IWL<1835> B_IWL<1834> B_IWL<1833> B_IWL<1832> B_IWL<1831> B_IWL<1830> B_IWL<1829> B_IWL<1828> B_IWL<1827> B_IWL<1826> B_IWL<1825> B_IWL<1824> B_IWL<1823> B_IWL<1822> B_IWL<1821> B_IWL<1820> B_IWL<1819> B_IWL<1818> B_IWL<1817> B_IWL<1816> B_IWL<1815> B_IWL<1814> B_IWL<1813> B_IWL<1812> B_IWL<1811> B_IWL<1810> B_IWL<1809> B_IWL<1808> B_IWL<1807> B_IWL<1806> B_IWL<1805> B_IWL<1804> B_IWL<1803> B_IWL<1802> B_IWL<1801> B_IWL<1800> B_IWL<1799> B_IWL<1798> B_IWL<1797> B_IWL<1796> B_IWL<1795> B_IWL<1794> B_IWL<1793> B_IWL<1792> VDD_CORE VSS / RM_IHPSG13_1024x32_c2_2P_COLUMN_pcell_0 +XCOL<6> A_BLC<13> A_BLC<12> A_BLC_TOP<13> A_BLC_TOP<12> A_BLT<13> A_BLT<12> A_BLT_TOP<13> A_BLT_TOP<12> A_IWL<1535> A_IWL<1534> A_IWL<1533> A_IWL<1532> A_IWL<1531> A_IWL<1530> A_IWL<1529> A_IWL<1528> A_IWL<1527> A_IWL<1526> A_IWL<1525> A_IWL<1524> A_IWL<1523> A_IWL<1522> A_IWL<1521> A_IWL<1520> A_IWL<1519> A_IWL<1518> A_IWL<1517> A_IWL<1516> A_IWL<1515> A_IWL<1514> A_IWL<1513> A_IWL<1512> A_IWL<1511> A_IWL<1510> A_IWL<1509> A_IWL<1508> A_IWL<1507> A_IWL<1506> A_IWL<1505> A_IWL<1504> A_IWL<1503> A_IWL<1502> A_IWL<1501> A_IWL<1500> A_IWL<1499> A_IWL<1498> A_IWL<1497> A_IWL<1496> A_IWL<1495> A_IWL<1494> A_IWL<1493> A_IWL<1492> A_IWL<1491> A_IWL<1490> A_IWL<1489> A_IWL<1488> A_IWL<1487> A_IWL<1486> A_IWL<1485> A_IWL<1484> A_IWL<1483> A_IWL<1482> A_IWL<1481> A_IWL<1480> A_IWL<1479> A_IWL<1478> A_IWL<1477> A_IWL<1476> A_IWL<1475> A_IWL<1474> A_IWL<1473> A_IWL<1472> A_IWL<1471> A_IWL<1470> A_IWL<1469> A_IWL<1468> A_IWL<1467> A_IWL<1466> A_IWL<1465> A_IWL<1464> A_IWL<1463> A_IWL<1462> A_IWL<1461> A_IWL<1460> A_IWL<1459> A_IWL<1458> A_IWL<1457> A_IWL<1456> A_IWL<1455> A_IWL<1454> A_IWL<1453> A_IWL<1452> A_IWL<1451> A_IWL<1450> A_IWL<1449> A_IWL<1448> A_IWL<1447> A_IWL<1446> A_IWL<1445> A_IWL<1444> A_IWL<1443> A_IWL<1442> A_IWL<1441> A_IWL<1440> A_IWL<1439> A_IWL<1438> A_IWL<1437> A_IWL<1436> A_IWL<1435> A_IWL<1434> A_IWL<1433> A_IWL<1432> A_IWL<1431> A_IWL<1430> A_IWL<1429> A_IWL<1428> A_IWL<1427> A_IWL<1426> A_IWL<1425> A_IWL<1424> A_IWL<1423> A_IWL<1422> A_IWL<1421> A_IWL<1420> A_IWL<1419> A_IWL<1418> A_IWL<1417> A_IWL<1416> A_IWL<1415> A_IWL<1414> A_IWL<1413> A_IWL<1412> A_IWL<1411> A_IWL<1410> A_IWL<1409> A_IWL<1408> A_IWL<1407> A_IWL<1406> A_IWL<1405> A_IWL<1404> A_IWL<1403> A_IWL<1402> A_IWL<1401> A_IWL<1400> A_IWL<1399> A_IWL<1398> A_IWL<1397> A_IWL<1396> A_IWL<1395> A_IWL<1394> A_IWL<1393> A_IWL<1392> A_IWL<1391> A_IWL<1390> A_IWL<1389> A_IWL<1388> A_IWL<1387> A_IWL<1386> A_IWL<1385> A_IWL<1384> A_IWL<1383> A_IWL<1382> A_IWL<1381> A_IWL<1380> A_IWL<1379> A_IWL<1378> A_IWL<1377> A_IWL<1376> A_IWL<1375> A_IWL<1374> A_IWL<1373> A_IWL<1372> A_IWL<1371> A_IWL<1370> A_IWL<1369> A_IWL<1368> A_IWL<1367> A_IWL<1366> A_IWL<1365> A_IWL<1364> A_IWL<1363> A_IWL<1362> A_IWL<1361> A_IWL<1360> A_IWL<1359> A_IWL<1358> A_IWL<1357> A_IWL<1356> A_IWL<1355> A_IWL<1354> A_IWL<1353> A_IWL<1352> A_IWL<1351> A_IWL<1350> A_IWL<1349> A_IWL<1348> A_IWL<1347> A_IWL<1346> A_IWL<1345> A_IWL<1344> A_IWL<1343> A_IWL<1342> A_IWL<1341> A_IWL<1340> A_IWL<1339> A_IWL<1338> A_IWL<1337> A_IWL<1336> A_IWL<1335> A_IWL<1334> A_IWL<1333> A_IWL<1332> A_IWL<1331> A_IWL<1330> A_IWL<1329> A_IWL<1328> A_IWL<1327> A_IWL<1326> A_IWL<1325> A_IWL<1324> A_IWL<1323> A_IWL<1322> A_IWL<1321> A_IWL<1320> A_IWL<1319> A_IWL<1318> A_IWL<1317> A_IWL<1316> A_IWL<1315> A_IWL<1314> A_IWL<1313> A_IWL<1312> A_IWL<1311> A_IWL<1310> A_IWL<1309> A_IWL<1308> A_IWL<1307> A_IWL<1306> A_IWL<1305> A_IWL<1304> A_IWL<1303> A_IWL<1302> A_IWL<1301> A_IWL<1300> A_IWL<1299> A_IWL<1298> A_IWL<1297> A_IWL<1296> A_IWL<1295> A_IWL<1294> A_IWL<1293> A_IWL<1292> A_IWL<1291> A_IWL<1290> A_IWL<1289> A_IWL<1288> A_IWL<1287> A_IWL<1286> A_IWL<1285> A_IWL<1284> A_IWL<1283> A_IWL<1282> A_IWL<1281> A_IWL<1280> A_IWL<1791> A_IWL<1790> A_IWL<1789> A_IWL<1788> A_IWL<1787> A_IWL<1786> A_IWL<1785> A_IWL<1784> A_IWL<1783> A_IWL<1782> A_IWL<1781> A_IWL<1780> A_IWL<1779> A_IWL<1778> A_IWL<1777> A_IWL<1776> A_IWL<1775> A_IWL<1774> A_IWL<1773> A_IWL<1772> A_IWL<1771> A_IWL<1770> A_IWL<1769> A_IWL<1768> A_IWL<1767> A_IWL<1766> A_IWL<1765> A_IWL<1764> A_IWL<1763> A_IWL<1762> A_IWL<1761> A_IWL<1760> A_IWL<1759> A_IWL<1758> A_IWL<1757> A_IWL<1756> A_IWL<1755> A_IWL<1754> A_IWL<1753> A_IWL<1752> A_IWL<1751> A_IWL<1750> A_IWL<1749> A_IWL<1748> A_IWL<1747> A_IWL<1746> A_IWL<1745> A_IWL<1744> A_IWL<1743> A_IWL<1742> A_IWL<1741> A_IWL<1740> A_IWL<1739> A_IWL<1738> A_IWL<1737> A_IWL<1736> A_IWL<1735> A_IWL<1734> A_IWL<1733> A_IWL<1732> A_IWL<1731> A_IWL<1730> A_IWL<1729> A_IWL<1728> A_IWL<1727> A_IWL<1726> A_IWL<1725> A_IWL<1724> A_IWL<1723> A_IWL<1722> A_IWL<1721> A_IWL<1720> A_IWL<1719> A_IWL<1718> A_IWL<1717> A_IWL<1716> A_IWL<1715> A_IWL<1714> A_IWL<1713> A_IWL<1712> A_IWL<1711> A_IWL<1710> A_IWL<1709> A_IWL<1708> A_IWL<1707> A_IWL<1706> A_IWL<1705> A_IWL<1704> A_IWL<1703> A_IWL<1702> A_IWL<1701> A_IWL<1700> A_IWL<1699> A_IWL<1698> A_IWL<1697> A_IWL<1696> A_IWL<1695> A_IWL<1694> A_IWL<1693> A_IWL<1692> A_IWL<1691> A_IWL<1690> A_IWL<1689> A_IWL<1688> A_IWL<1687> A_IWL<1686> A_IWL<1685> A_IWL<1684> A_IWL<1683> A_IWL<1682> A_IWL<1681> A_IWL<1680> A_IWL<1679> A_IWL<1678> A_IWL<1677> A_IWL<1676> A_IWL<1675> A_IWL<1674> A_IWL<1673> A_IWL<1672> A_IWL<1671> A_IWL<1670> A_IWL<1669> A_IWL<1668> A_IWL<1667> A_IWL<1666> A_IWL<1665> A_IWL<1664> A_IWL<1663> A_IWL<1662> A_IWL<1661> A_IWL<1660> A_IWL<1659> A_IWL<1658> A_IWL<1657> A_IWL<1656> A_IWL<1655> A_IWL<1654> A_IWL<1653> A_IWL<1652> A_IWL<1651> A_IWL<1650> A_IWL<1649> A_IWL<1648> A_IWL<1647> A_IWL<1646> A_IWL<1645> A_IWL<1644> A_IWL<1643> A_IWL<1642> A_IWL<1641> A_IWL<1640> A_IWL<1639> A_IWL<1638> A_IWL<1637> A_IWL<1636> A_IWL<1635> A_IWL<1634> A_IWL<1633> A_IWL<1632> A_IWL<1631> A_IWL<1630> A_IWL<1629> A_IWL<1628> A_IWL<1627> A_IWL<1626> A_IWL<1625> A_IWL<1624> A_IWL<1623> A_IWL<1622> A_IWL<1621> A_IWL<1620> A_IWL<1619> A_IWL<1618> A_IWL<1617> A_IWL<1616> A_IWL<1615> A_IWL<1614> A_IWL<1613> A_IWL<1612> A_IWL<1611> A_IWL<1610> A_IWL<1609> A_IWL<1608> A_IWL<1607> A_IWL<1606> A_IWL<1605> A_IWL<1604> A_IWL<1603> A_IWL<1602> A_IWL<1601> A_IWL<1600> A_IWL<1599> A_IWL<1598> A_IWL<1597> A_IWL<1596> A_IWL<1595> A_IWL<1594> A_IWL<1593> A_IWL<1592> A_IWL<1591> A_IWL<1590> A_IWL<1589> A_IWL<1588> A_IWL<1587> A_IWL<1586> A_IWL<1585> A_IWL<1584> A_IWL<1583> A_IWL<1582> A_IWL<1581> A_IWL<1580> A_IWL<1579> A_IWL<1578> A_IWL<1577> A_IWL<1576> A_IWL<1575> A_IWL<1574> A_IWL<1573> A_IWL<1572> A_IWL<1571> A_IWL<1570> A_IWL<1569> A_IWL<1568> A_IWL<1567> A_IWL<1566> A_IWL<1565> A_IWL<1564> A_IWL<1563> A_IWL<1562> A_IWL<1561> A_IWL<1560> A_IWL<1559> A_IWL<1558> A_IWL<1557> A_IWL<1556> A_IWL<1555> A_IWL<1554> A_IWL<1553> A_IWL<1552> A_IWL<1551> A_IWL<1550> A_IWL<1549> A_IWL<1548> A_IWL<1547> A_IWL<1546> A_IWL<1545> A_IWL<1544> A_IWL<1543> A_IWL<1542> A_IWL<1541> A_IWL<1540> A_IWL<1539> A_IWL<1538> A_IWL<1537> A_IWL<1536> B_BLC<13> B_BLC<12> B_BLC_TOP<13> B_BLC_TOP<12> B_BLT<13> B_BLT<12> B_BLT_TOP<13> B_BLT_TOP<12> B_IWL<1535> B_IWL<1534> B_IWL<1533> B_IWL<1532> B_IWL<1531> B_IWL<1530> B_IWL<1529> B_IWL<1528> B_IWL<1527> B_IWL<1526> B_IWL<1525> B_IWL<1524> B_IWL<1523> B_IWL<1522> B_IWL<1521> B_IWL<1520> B_IWL<1519> B_IWL<1518> B_IWL<1517> B_IWL<1516> B_IWL<1515> B_IWL<1514> B_IWL<1513> B_IWL<1512> B_IWL<1511> B_IWL<1510> B_IWL<1509> B_IWL<1508> B_IWL<1507> B_IWL<1506> B_IWL<1505> B_IWL<1504> B_IWL<1503> B_IWL<1502> B_IWL<1501> B_IWL<1500> B_IWL<1499> B_IWL<1498> B_IWL<1497> B_IWL<1496> B_IWL<1495> B_IWL<1494> B_IWL<1493> B_IWL<1492> B_IWL<1491> B_IWL<1490> B_IWL<1489> B_IWL<1488> B_IWL<1487> B_IWL<1486> B_IWL<1485> B_IWL<1484> B_IWL<1483> B_IWL<1482> B_IWL<1481> B_IWL<1480> B_IWL<1479> B_IWL<1478> B_IWL<1477> B_IWL<1476> B_IWL<1475> B_IWL<1474> B_IWL<1473> B_IWL<1472> B_IWL<1471> B_IWL<1470> B_IWL<1469> B_IWL<1468> B_IWL<1467> B_IWL<1466> B_IWL<1465> B_IWL<1464> B_IWL<1463> B_IWL<1462> B_IWL<1461> B_IWL<1460> B_IWL<1459> B_IWL<1458> B_IWL<1457> B_IWL<1456> B_IWL<1455> B_IWL<1454> B_IWL<1453> B_IWL<1452> B_IWL<1451> B_IWL<1450> B_IWL<1449> B_IWL<1448> B_IWL<1447> B_IWL<1446> B_IWL<1445> B_IWL<1444> B_IWL<1443> B_IWL<1442> B_IWL<1441> B_IWL<1440> B_IWL<1439> B_IWL<1438> B_IWL<1437> B_IWL<1436> B_IWL<1435> B_IWL<1434> B_IWL<1433> B_IWL<1432> B_IWL<1431> B_IWL<1430> B_IWL<1429> B_IWL<1428> B_IWL<1427> B_IWL<1426> B_IWL<1425> B_IWL<1424> B_IWL<1423> B_IWL<1422> B_IWL<1421> B_IWL<1420> B_IWL<1419> B_IWL<1418> B_IWL<1417> B_IWL<1416> B_IWL<1415> B_IWL<1414> B_IWL<1413> B_IWL<1412> B_IWL<1411> B_IWL<1410> B_IWL<1409> B_IWL<1408> B_IWL<1407> B_IWL<1406> B_IWL<1405> B_IWL<1404> B_IWL<1403> B_IWL<1402> B_IWL<1401> B_IWL<1400> B_IWL<1399> B_IWL<1398> B_IWL<1397> B_IWL<1396> B_IWL<1395> B_IWL<1394> B_IWL<1393> B_IWL<1392> B_IWL<1391> B_IWL<1390> B_IWL<1389> B_IWL<1388> B_IWL<1387> B_IWL<1386> B_IWL<1385> B_IWL<1384> B_IWL<1383> B_IWL<1382> B_IWL<1381> B_IWL<1380> B_IWL<1379> B_IWL<1378> B_IWL<1377> B_IWL<1376> B_IWL<1375> B_IWL<1374> B_IWL<1373> B_IWL<1372> B_IWL<1371> B_IWL<1370> B_IWL<1369> B_IWL<1368> B_IWL<1367> B_IWL<1366> B_IWL<1365> B_IWL<1364> B_IWL<1363> B_IWL<1362> B_IWL<1361> B_IWL<1360> B_IWL<1359> B_IWL<1358> B_IWL<1357> B_IWL<1356> B_IWL<1355> B_IWL<1354> B_IWL<1353> B_IWL<1352> B_IWL<1351> B_IWL<1350> B_IWL<1349> B_IWL<1348> B_IWL<1347> B_IWL<1346> B_IWL<1345> B_IWL<1344> B_IWL<1343> B_IWL<1342> B_IWL<1341> B_IWL<1340> B_IWL<1339> B_IWL<1338> B_IWL<1337> B_IWL<1336> B_IWL<1335> B_IWL<1334> B_IWL<1333> B_IWL<1332> B_IWL<1331> B_IWL<1330> B_IWL<1329> B_IWL<1328> B_IWL<1327> B_IWL<1326> B_IWL<1325> B_IWL<1324> B_IWL<1323> B_IWL<1322> B_IWL<1321> B_IWL<1320> B_IWL<1319> B_IWL<1318> B_IWL<1317> B_IWL<1316> B_IWL<1315> B_IWL<1314> B_IWL<1313> B_IWL<1312> B_IWL<1311> B_IWL<1310> B_IWL<1309> B_IWL<1308> B_IWL<1307> B_IWL<1306> B_IWL<1305> B_IWL<1304> B_IWL<1303> B_IWL<1302> B_IWL<1301> B_IWL<1300> B_IWL<1299> B_IWL<1298> B_IWL<1297> B_IWL<1296> B_IWL<1295> B_IWL<1294> B_IWL<1293> B_IWL<1292> B_IWL<1291> B_IWL<1290> B_IWL<1289> B_IWL<1288> B_IWL<1287> B_IWL<1286> B_IWL<1285> B_IWL<1284> B_IWL<1283> B_IWL<1282> B_IWL<1281> B_IWL<1280> B_IWL<1791> B_IWL<1790> B_IWL<1789> B_IWL<1788> B_IWL<1787> B_IWL<1786> B_IWL<1785> B_IWL<1784> B_IWL<1783> B_IWL<1782> B_IWL<1781> B_IWL<1780> B_IWL<1779> B_IWL<1778> B_IWL<1777> B_IWL<1776> B_IWL<1775> B_IWL<1774> B_IWL<1773> B_IWL<1772> B_IWL<1771> B_IWL<1770> B_IWL<1769> B_IWL<1768> B_IWL<1767> B_IWL<1766> B_IWL<1765> B_IWL<1764> B_IWL<1763> B_IWL<1762> B_IWL<1761> B_IWL<1760> B_IWL<1759> B_IWL<1758> B_IWL<1757> B_IWL<1756> B_IWL<1755> B_IWL<1754> B_IWL<1753> B_IWL<1752> B_IWL<1751> B_IWL<1750> B_IWL<1749> B_IWL<1748> B_IWL<1747> B_IWL<1746> B_IWL<1745> B_IWL<1744> B_IWL<1743> B_IWL<1742> B_IWL<1741> B_IWL<1740> B_IWL<1739> B_IWL<1738> B_IWL<1737> B_IWL<1736> B_IWL<1735> B_IWL<1734> B_IWL<1733> B_IWL<1732> B_IWL<1731> B_IWL<1730> B_IWL<1729> B_IWL<1728> B_IWL<1727> B_IWL<1726> B_IWL<1725> B_IWL<1724> B_IWL<1723> B_IWL<1722> B_IWL<1721> B_IWL<1720> B_IWL<1719> B_IWL<1718> B_IWL<1717> B_IWL<1716> B_IWL<1715> B_IWL<1714> B_IWL<1713> B_IWL<1712> B_IWL<1711> B_IWL<1710> B_IWL<1709> B_IWL<1708> B_IWL<1707> B_IWL<1706> B_IWL<1705> B_IWL<1704> B_IWL<1703> B_IWL<1702> B_IWL<1701> B_IWL<1700> B_IWL<1699> B_IWL<1698> B_IWL<1697> B_IWL<1696> B_IWL<1695> B_IWL<1694> B_IWL<1693> B_IWL<1692> B_IWL<1691> B_IWL<1690> B_IWL<1689> B_IWL<1688> B_IWL<1687> B_IWL<1686> B_IWL<1685> B_IWL<1684> B_IWL<1683> B_IWL<1682> B_IWL<1681> B_IWL<1680> B_IWL<1679> B_IWL<1678> B_IWL<1677> B_IWL<1676> B_IWL<1675> B_IWL<1674> B_IWL<1673> B_IWL<1672> B_IWL<1671> B_IWL<1670> B_IWL<1669> B_IWL<1668> B_IWL<1667> B_IWL<1666> B_IWL<1665> B_IWL<1664> B_IWL<1663> B_IWL<1662> B_IWL<1661> B_IWL<1660> B_IWL<1659> B_IWL<1658> B_IWL<1657> B_IWL<1656> B_IWL<1655> B_IWL<1654> B_IWL<1653> B_IWL<1652> B_IWL<1651> B_IWL<1650> B_IWL<1649> B_IWL<1648> B_IWL<1647> B_IWL<1646> B_IWL<1645> B_IWL<1644> B_IWL<1643> B_IWL<1642> B_IWL<1641> B_IWL<1640> B_IWL<1639> B_IWL<1638> B_IWL<1637> B_IWL<1636> B_IWL<1635> B_IWL<1634> B_IWL<1633> B_IWL<1632> B_IWL<1631> B_IWL<1630> B_IWL<1629> B_IWL<1628> B_IWL<1627> B_IWL<1626> B_IWL<1625> B_IWL<1624> B_IWL<1623> B_IWL<1622> B_IWL<1621> B_IWL<1620> B_IWL<1619> B_IWL<1618> B_IWL<1617> B_IWL<1616> B_IWL<1615> B_IWL<1614> B_IWL<1613> B_IWL<1612> B_IWL<1611> B_IWL<1610> B_IWL<1609> B_IWL<1608> B_IWL<1607> B_IWL<1606> B_IWL<1605> B_IWL<1604> B_IWL<1603> B_IWL<1602> B_IWL<1601> B_IWL<1600> B_IWL<1599> B_IWL<1598> B_IWL<1597> B_IWL<1596> B_IWL<1595> B_IWL<1594> B_IWL<1593> B_IWL<1592> B_IWL<1591> B_IWL<1590> B_IWL<1589> B_IWL<1588> B_IWL<1587> B_IWL<1586> B_IWL<1585> B_IWL<1584> B_IWL<1583> B_IWL<1582> B_IWL<1581> B_IWL<1580> B_IWL<1579> B_IWL<1578> B_IWL<1577> B_IWL<1576> B_IWL<1575> B_IWL<1574> B_IWL<1573> B_IWL<1572> B_IWL<1571> B_IWL<1570> B_IWL<1569> B_IWL<1568> B_IWL<1567> B_IWL<1566> B_IWL<1565> B_IWL<1564> B_IWL<1563> B_IWL<1562> B_IWL<1561> B_IWL<1560> B_IWL<1559> B_IWL<1558> B_IWL<1557> B_IWL<1556> B_IWL<1555> B_IWL<1554> B_IWL<1553> B_IWL<1552> B_IWL<1551> B_IWL<1550> B_IWL<1549> B_IWL<1548> B_IWL<1547> B_IWL<1546> B_IWL<1545> B_IWL<1544> B_IWL<1543> B_IWL<1542> B_IWL<1541> B_IWL<1540> B_IWL<1539> B_IWL<1538> B_IWL<1537> B_IWL<1536> VDD_CORE VSS / RM_IHPSG13_1024x32_c2_2P_COLUMN_pcell_0 +XCOL<5> A_BLC<11> A_BLC<10> A_BLC_TOP<11> A_BLC_TOP<10> A_BLT<11> A_BLT<10> A_BLT_TOP<11> A_BLT_TOP<10> A_IWL<1279> A_IWL<1278> A_IWL<1277> A_IWL<1276> A_IWL<1275> A_IWL<1274> A_IWL<1273> A_IWL<1272> A_IWL<1271> A_IWL<1270> A_IWL<1269> A_IWL<1268> A_IWL<1267> A_IWL<1266> A_IWL<1265> A_IWL<1264> A_IWL<1263> A_IWL<1262> A_IWL<1261> A_IWL<1260> A_IWL<1259> A_IWL<1258> A_IWL<1257> A_IWL<1256> A_IWL<1255> A_IWL<1254> A_IWL<1253> A_IWL<1252> A_IWL<1251> A_IWL<1250> A_IWL<1249> A_IWL<1248> A_IWL<1247> A_IWL<1246> A_IWL<1245> A_IWL<1244> A_IWL<1243> A_IWL<1242> A_IWL<1241> A_IWL<1240> A_IWL<1239> A_IWL<1238> A_IWL<1237> A_IWL<1236> A_IWL<1235> A_IWL<1234> A_IWL<1233> A_IWL<1232> A_IWL<1231> A_IWL<1230> A_IWL<1229> A_IWL<1228> A_IWL<1227> A_IWL<1226> A_IWL<1225> A_IWL<1224> A_IWL<1223> A_IWL<1222> A_IWL<1221> A_IWL<1220> A_IWL<1219> A_IWL<1218> A_IWL<1217> A_IWL<1216> A_IWL<1215> A_IWL<1214> A_IWL<1213> A_IWL<1212> A_IWL<1211> A_IWL<1210> A_IWL<1209> A_IWL<1208> A_IWL<1207> A_IWL<1206> A_IWL<1205> A_IWL<1204> A_IWL<1203> A_IWL<1202> A_IWL<1201> A_IWL<1200> A_IWL<1199> A_IWL<1198> A_IWL<1197> A_IWL<1196> A_IWL<1195> A_IWL<1194> A_IWL<1193> A_IWL<1192> A_IWL<1191> A_IWL<1190> A_IWL<1189> A_IWL<1188> A_IWL<1187> A_IWL<1186> A_IWL<1185> A_IWL<1184> A_IWL<1183> A_IWL<1182> A_IWL<1181> A_IWL<1180> A_IWL<1179> A_IWL<1178> A_IWL<1177> A_IWL<1176> A_IWL<1175> A_IWL<1174> A_IWL<1173> A_IWL<1172> A_IWL<1171> A_IWL<1170> A_IWL<1169> A_IWL<1168> A_IWL<1167> A_IWL<1166> A_IWL<1165> A_IWL<1164> A_IWL<1163> A_IWL<1162> A_IWL<1161> A_IWL<1160> A_IWL<1159> A_IWL<1158> A_IWL<1157> A_IWL<1156> A_IWL<1155> A_IWL<1154> A_IWL<1153> A_IWL<1152> A_IWL<1151> A_IWL<1150> A_IWL<1149> A_IWL<1148> A_IWL<1147> A_IWL<1146> A_IWL<1145> A_IWL<1144> A_IWL<1143> A_IWL<1142> A_IWL<1141> A_IWL<1140> A_IWL<1139> A_IWL<1138> A_IWL<1137> A_IWL<1136> A_IWL<1135> A_IWL<1134> A_IWL<1133> A_IWL<1132> A_IWL<1131> A_IWL<1130> A_IWL<1129> A_IWL<1128> A_IWL<1127> A_IWL<1126> A_IWL<1125> A_IWL<1124> A_IWL<1123> A_IWL<1122> A_IWL<1121> A_IWL<1120> A_IWL<1119> A_IWL<1118> A_IWL<1117> A_IWL<1116> A_IWL<1115> A_IWL<1114> A_IWL<1113> A_IWL<1112> A_IWL<1111> A_IWL<1110> A_IWL<1109> A_IWL<1108> A_IWL<1107> A_IWL<1106> A_IWL<1105> A_IWL<1104> A_IWL<1103> A_IWL<1102> A_IWL<1101> A_IWL<1100> A_IWL<1099> A_IWL<1098> A_IWL<1097> A_IWL<1096> A_IWL<1095> A_IWL<1094> A_IWL<1093> A_IWL<1092> A_IWL<1091> A_IWL<1090> A_IWL<1089> A_IWL<1088> A_IWL<1087> A_IWL<1086> A_IWL<1085> A_IWL<1084> A_IWL<1083> A_IWL<1082> A_IWL<1081> A_IWL<1080> A_IWL<1079> A_IWL<1078> A_IWL<1077> A_IWL<1076> A_IWL<1075> A_IWL<1074> A_IWL<1073> A_IWL<1072> A_IWL<1071> A_IWL<1070> A_IWL<1069> A_IWL<1068> A_IWL<1067> A_IWL<1066> A_IWL<1065> A_IWL<1064> A_IWL<1063> A_IWL<1062> A_IWL<1061> A_IWL<1060> A_IWL<1059> A_IWL<1058> A_IWL<1057> A_IWL<1056> A_IWL<1055> A_IWL<1054> A_IWL<1053> A_IWL<1052> A_IWL<1051> A_IWL<1050> A_IWL<1049> A_IWL<1048> A_IWL<1047> A_IWL<1046> A_IWL<1045> A_IWL<1044> A_IWL<1043> A_IWL<1042> A_IWL<1041> A_IWL<1040> A_IWL<1039> A_IWL<1038> A_IWL<1037> A_IWL<1036> A_IWL<1035> A_IWL<1034> A_IWL<1033> A_IWL<1032> A_IWL<1031> A_IWL<1030> A_IWL<1029> A_IWL<1028> A_IWL<1027> A_IWL<1026> A_IWL<1025> A_IWL<1024> A_IWL<1535> A_IWL<1534> A_IWL<1533> A_IWL<1532> A_IWL<1531> A_IWL<1530> A_IWL<1529> A_IWL<1528> A_IWL<1527> A_IWL<1526> A_IWL<1525> A_IWL<1524> A_IWL<1523> A_IWL<1522> A_IWL<1521> A_IWL<1520> A_IWL<1519> A_IWL<1518> A_IWL<1517> A_IWL<1516> A_IWL<1515> A_IWL<1514> A_IWL<1513> A_IWL<1512> A_IWL<1511> A_IWL<1510> A_IWL<1509> A_IWL<1508> A_IWL<1507> A_IWL<1506> A_IWL<1505> A_IWL<1504> A_IWL<1503> A_IWL<1502> A_IWL<1501> A_IWL<1500> A_IWL<1499> A_IWL<1498> A_IWL<1497> A_IWL<1496> A_IWL<1495> A_IWL<1494> A_IWL<1493> A_IWL<1492> A_IWL<1491> A_IWL<1490> A_IWL<1489> A_IWL<1488> A_IWL<1487> A_IWL<1486> A_IWL<1485> A_IWL<1484> A_IWL<1483> A_IWL<1482> A_IWL<1481> A_IWL<1480> A_IWL<1479> A_IWL<1478> A_IWL<1477> A_IWL<1476> A_IWL<1475> A_IWL<1474> A_IWL<1473> A_IWL<1472> A_IWL<1471> A_IWL<1470> A_IWL<1469> A_IWL<1468> A_IWL<1467> A_IWL<1466> A_IWL<1465> A_IWL<1464> A_IWL<1463> A_IWL<1462> A_IWL<1461> A_IWL<1460> A_IWL<1459> A_IWL<1458> A_IWL<1457> A_IWL<1456> A_IWL<1455> A_IWL<1454> A_IWL<1453> A_IWL<1452> A_IWL<1451> A_IWL<1450> A_IWL<1449> A_IWL<1448> A_IWL<1447> A_IWL<1446> A_IWL<1445> A_IWL<1444> A_IWL<1443> A_IWL<1442> A_IWL<1441> A_IWL<1440> A_IWL<1439> A_IWL<1438> A_IWL<1437> A_IWL<1436> A_IWL<1435> A_IWL<1434> A_IWL<1433> A_IWL<1432> A_IWL<1431> A_IWL<1430> A_IWL<1429> A_IWL<1428> A_IWL<1427> A_IWL<1426> A_IWL<1425> A_IWL<1424> A_IWL<1423> A_IWL<1422> A_IWL<1421> A_IWL<1420> A_IWL<1419> A_IWL<1418> A_IWL<1417> A_IWL<1416> A_IWL<1415> A_IWL<1414> A_IWL<1413> A_IWL<1412> A_IWL<1411> A_IWL<1410> A_IWL<1409> A_IWL<1408> A_IWL<1407> A_IWL<1406> A_IWL<1405> A_IWL<1404> A_IWL<1403> A_IWL<1402> A_IWL<1401> A_IWL<1400> A_IWL<1399> A_IWL<1398> A_IWL<1397> A_IWL<1396> A_IWL<1395> A_IWL<1394> A_IWL<1393> A_IWL<1392> A_IWL<1391> A_IWL<1390> A_IWL<1389> A_IWL<1388> A_IWL<1387> A_IWL<1386> A_IWL<1385> A_IWL<1384> A_IWL<1383> A_IWL<1382> A_IWL<1381> A_IWL<1380> A_IWL<1379> A_IWL<1378> A_IWL<1377> A_IWL<1376> A_IWL<1375> A_IWL<1374> A_IWL<1373> A_IWL<1372> A_IWL<1371> A_IWL<1370> A_IWL<1369> A_IWL<1368> A_IWL<1367> A_IWL<1366> A_IWL<1365> A_IWL<1364> A_IWL<1363> A_IWL<1362> A_IWL<1361> A_IWL<1360> A_IWL<1359> A_IWL<1358> A_IWL<1357> A_IWL<1356> A_IWL<1355> A_IWL<1354> A_IWL<1353> A_IWL<1352> A_IWL<1351> A_IWL<1350> A_IWL<1349> A_IWL<1348> A_IWL<1347> A_IWL<1346> A_IWL<1345> A_IWL<1344> A_IWL<1343> A_IWL<1342> A_IWL<1341> A_IWL<1340> A_IWL<1339> A_IWL<1338> A_IWL<1337> A_IWL<1336> A_IWL<1335> A_IWL<1334> A_IWL<1333> A_IWL<1332> A_IWL<1331> A_IWL<1330> A_IWL<1329> A_IWL<1328> A_IWL<1327> A_IWL<1326> A_IWL<1325> A_IWL<1324> A_IWL<1323> A_IWL<1322> A_IWL<1321> A_IWL<1320> A_IWL<1319> A_IWL<1318> A_IWL<1317> A_IWL<1316> A_IWL<1315> A_IWL<1314> A_IWL<1313> A_IWL<1312> A_IWL<1311> A_IWL<1310> A_IWL<1309> A_IWL<1308> A_IWL<1307> A_IWL<1306> A_IWL<1305> A_IWL<1304> A_IWL<1303> A_IWL<1302> A_IWL<1301> A_IWL<1300> A_IWL<1299> A_IWL<1298> A_IWL<1297> A_IWL<1296> A_IWL<1295> A_IWL<1294> A_IWL<1293> A_IWL<1292> A_IWL<1291> A_IWL<1290> A_IWL<1289> A_IWL<1288> A_IWL<1287> A_IWL<1286> A_IWL<1285> A_IWL<1284> A_IWL<1283> A_IWL<1282> A_IWL<1281> A_IWL<1280> B_BLC<11> B_BLC<10> B_BLC_TOP<11> B_BLC_TOP<10> B_BLT<11> B_BLT<10> B_BLT_TOP<11> B_BLT_TOP<10> B_IWL<1279> B_IWL<1278> B_IWL<1277> B_IWL<1276> B_IWL<1275> B_IWL<1274> B_IWL<1273> B_IWL<1272> B_IWL<1271> B_IWL<1270> B_IWL<1269> B_IWL<1268> B_IWL<1267> B_IWL<1266> B_IWL<1265> B_IWL<1264> B_IWL<1263> B_IWL<1262> B_IWL<1261> B_IWL<1260> B_IWL<1259> B_IWL<1258> B_IWL<1257> B_IWL<1256> B_IWL<1255> B_IWL<1254> B_IWL<1253> B_IWL<1252> B_IWL<1251> B_IWL<1250> B_IWL<1249> B_IWL<1248> B_IWL<1247> B_IWL<1246> B_IWL<1245> B_IWL<1244> B_IWL<1243> B_IWL<1242> B_IWL<1241> B_IWL<1240> B_IWL<1239> B_IWL<1238> B_IWL<1237> B_IWL<1236> B_IWL<1235> B_IWL<1234> B_IWL<1233> B_IWL<1232> B_IWL<1231> B_IWL<1230> B_IWL<1229> B_IWL<1228> B_IWL<1227> B_IWL<1226> B_IWL<1225> B_IWL<1224> B_IWL<1223> B_IWL<1222> B_IWL<1221> B_IWL<1220> B_IWL<1219> B_IWL<1218> B_IWL<1217> B_IWL<1216> B_IWL<1215> B_IWL<1214> B_IWL<1213> B_IWL<1212> B_IWL<1211> B_IWL<1210> B_IWL<1209> B_IWL<1208> B_IWL<1207> B_IWL<1206> B_IWL<1205> B_IWL<1204> B_IWL<1203> B_IWL<1202> B_IWL<1201> B_IWL<1200> B_IWL<1199> B_IWL<1198> B_IWL<1197> B_IWL<1196> B_IWL<1195> B_IWL<1194> B_IWL<1193> B_IWL<1192> B_IWL<1191> B_IWL<1190> B_IWL<1189> B_IWL<1188> B_IWL<1187> B_IWL<1186> B_IWL<1185> B_IWL<1184> B_IWL<1183> B_IWL<1182> B_IWL<1181> B_IWL<1180> B_IWL<1179> B_IWL<1178> B_IWL<1177> B_IWL<1176> B_IWL<1175> B_IWL<1174> B_IWL<1173> B_IWL<1172> B_IWL<1171> B_IWL<1170> B_IWL<1169> B_IWL<1168> B_IWL<1167> B_IWL<1166> B_IWL<1165> B_IWL<1164> B_IWL<1163> B_IWL<1162> B_IWL<1161> B_IWL<1160> B_IWL<1159> B_IWL<1158> B_IWL<1157> B_IWL<1156> B_IWL<1155> B_IWL<1154> B_IWL<1153> B_IWL<1152> B_IWL<1151> B_IWL<1150> B_IWL<1149> B_IWL<1148> B_IWL<1147> B_IWL<1146> B_IWL<1145> B_IWL<1144> B_IWL<1143> B_IWL<1142> B_IWL<1141> B_IWL<1140> B_IWL<1139> B_IWL<1138> B_IWL<1137> B_IWL<1136> B_IWL<1135> B_IWL<1134> B_IWL<1133> B_IWL<1132> B_IWL<1131> B_IWL<1130> B_IWL<1129> B_IWL<1128> B_IWL<1127> B_IWL<1126> B_IWL<1125> B_IWL<1124> B_IWL<1123> B_IWL<1122> B_IWL<1121> B_IWL<1120> B_IWL<1119> B_IWL<1118> B_IWL<1117> B_IWL<1116> B_IWL<1115> B_IWL<1114> B_IWL<1113> B_IWL<1112> B_IWL<1111> B_IWL<1110> B_IWL<1109> B_IWL<1108> B_IWL<1107> B_IWL<1106> B_IWL<1105> B_IWL<1104> B_IWL<1103> B_IWL<1102> B_IWL<1101> B_IWL<1100> B_IWL<1099> B_IWL<1098> B_IWL<1097> B_IWL<1096> B_IWL<1095> B_IWL<1094> B_IWL<1093> B_IWL<1092> B_IWL<1091> B_IWL<1090> B_IWL<1089> B_IWL<1088> B_IWL<1087> B_IWL<1086> B_IWL<1085> B_IWL<1084> B_IWL<1083> B_IWL<1082> B_IWL<1081> B_IWL<1080> B_IWL<1079> B_IWL<1078> B_IWL<1077> B_IWL<1076> B_IWL<1075> B_IWL<1074> B_IWL<1073> B_IWL<1072> B_IWL<1071> B_IWL<1070> B_IWL<1069> B_IWL<1068> B_IWL<1067> B_IWL<1066> B_IWL<1065> B_IWL<1064> B_IWL<1063> B_IWL<1062> B_IWL<1061> B_IWL<1060> B_IWL<1059> B_IWL<1058> B_IWL<1057> B_IWL<1056> B_IWL<1055> B_IWL<1054> B_IWL<1053> B_IWL<1052> B_IWL<1051> B_IWL<1050> B_IWL<1049> B_IWL<1048> B_IWL<1047> B_IWL<1046> B_IWL<1045> B_IWL<1044> B_IWL<1043> B_IWL<1042> B_IWL<1041> B_IWL<1040> B_IWL<1039> B_IWL<1038> B_IWL<1037> B_IWL<1036> B_IWL<1035> B_IWL<1034> B_IWL<1033> B_IWL<1032> B_IWL<1031> B_IWL<1030> B_IWL<1029> B_IWL<1028> B_IWL<1027> B_IWL<1026> B_IWL<1025> B_IWL<1024> B_IWL<1535> B_IWL<1534> B_IWL<1533> B_IWL<1532> B_IWL<1531> B_IWL<1530> B_IWL<1529> B_IWL<1528> B_IWL<1527> B_IWL<1526> B_IWL<1525> B_IWL<1524> B_IWL<1523> B_IWL<1522> B_IWL<1521> B_IWL<1520> B_IWL<1519> B_IWL<1518> B_IWL<1517> B_IWL<1516> B_IWL<1515> B_IWL<1514> B_IWL<1513> B_IWL<1512> B_IWL<1511> B_IWL<1510> B_IWL<1509> B_IWL<1508> B_IWL<1507> B_IWL<1506> B_IWL<1505> B_IWL<1504> B_IWL<1503> B_IWL<1502> B_IWL<1501> B_IWL<1500> B_IWL<1499> B_IWL<1498> B_IWL<1497> B_IWL<1496> B_IWL<1495> B_IWL<1494> B_IWL<1493> B_IWL<1492> B_IWL<1491> B_IWL<1490> B_IWL<1489> B_IWL<1488> B_IWL<1487> B_IWL<1486> B_IWL<1485> B_IWL<1484> B_IWL<1483> B_IWL<1482> B_IWL<1481> B_IWL<1480> B_IWL<1479> B_IWL<1478> B_IWL<1477> B_IWL<1476> B_IWL<1475> B_IWL<1474> B_IWL<1473> B_IWL<1472> B_IWL<1471> B_IWL<1470> B_IWL<1469> B_IWL<1468> B_IWL<1467> B_IWL<1466> B_IWL<1465> B_IWL<1464> B_IWL<1463> B_IWL<1462> B_IWL<1461> B_IWL<1460> B_IWL<1459> B_IWL<1458> B_IWL<1457> B_IWL<1456> B_IWL<1455> B_IWL<1454> B_IWL<1453> B_IWL<1452> B_IWL<1451> B_IWL<1450> B_IWL<1449> B_IWL<1448> B_IWL<1447> B_IWL<1446> B_IWL<1445> B_IWL<1444> B_IWL<1443> B_IWL<1442> B_IWL<1441> B_IWL<1440> B_IWL<1439> B_IWL<1438> B_IWL<1437> B_IWL<1436> B_IWL<1435> B_IWL<1434> B_IWL<1433> B_IWL<1432> B_IWL<1431> B_IWL<1430> B_IWL<1429> B_IWL<1428> B_IWL<1427> B_IWL<1426> B_IWL<1425> B_IWL<1424> B_IWL<1423> B_IWL<1422> B_IWL<1421> B_IWL<1420> B_IWL<1419> B_IWL<1418> B_IWL<1417> B_IWL<1416> B_IWL<1415> B_IWL<1414> B_IWL<1413> B_IWL<1412> B_IWL<1411> B_IWL<1410> B_IWL<1409> B_IWL<1408> B_IWL<1407> B_IWL<1406> B_IWL<1405> B_IWL<1404> B_IWL<1403> B_IWL<1402> B_IWL<1401> B_IWL<1400> B_IWL<1399> B_IWL<1398> B_IWL<1397> B_IWL<1396> B_IWL<1395> B_IWL<1394> B_IWL<1393> B_IWL<1392> B_IWL<1391> B_IWL<1390> B_IWL<1389> B_IWL<1388> B_IWL<1387> B_IWL<1386> B_IWL<1385> B_IWL<1384> B_IWL<1383> B_IWL<1382> B_IWL<1381> B_IWL<1380> B_IWL<1379> B_IWL<1378> B_IWL<1377> B_IWL<1376> B_IWL<1375> B_IWL<1374> B_IWL<1373> B_IWL<1372> B_IWL<1371> B_IWL<1370> B_IWL<1369> B_IWL<1368> B_IWL<1367> B_IWL<1366> B_IWL<1365> B_IWL<1364> B_IWL<1363> B_IWL<1362> B_IWL<1361> B_IWL<1360> B_IWL<1359> B_IWL<1358> B_IWL<1357> B_IWL<1356> B_IWL<1355> B_IWL<1354> B_IWL<1353> B_IWL<1352> B_IWL<1351> B_IWL<1350> B_IWL<1349> B_IWL<1348> B_IWL<1347> B_IWL<1346> B_IWL<1345> B_IWL<1344> B_IWL<1343> B_IWL<1342> B_IWL<1341> B_IWL<1340> B_IWL<1339> B_IWL<1338> B_IWL<1337> B_IWL<1336> B_IWL<1335> B_IWL<1334> B_IWL<1333> B_IWL<1332> B_IWL<1331> B_IWL<1330> B_IWL<1329> B_IWL<1328> B_IWL<1327> B_IWL<1326> B_IWL<1325> B_IWL<1324> B_IWL<1323> B_IWL<1322> B_IWL<1321> B_IWL<1320> B_IWL<1319> B_IWL<1318> B_IWL<1317> B_IWL<1316> B_IWL<1315> B_IWL<1314> B_IWL<1313> B_IWL<1312> B_IWL<1311> B_IWL<1310> B_IWL<1309> B_IWL<1308> B_IWL<1307> B_IWL<1306> B_IWL<1305> B_IWL<1304> B_IWL<1303> B_IWL<1302> B_IWL<1301> B_IWL<1300> B_IWL<1299> B_IWL<1298> B_IWL<1297> B_IWL<1296> B_IWL<1295> B_IWL<1294> B_IWL<1293> B_IWL<1292> B_IWL<1291> B_IWL<1290> B_IWL<1289> B_IWL<1288> B_IWL<1287> B_IWL<1286> B_IWL<1285> B_IWL<1284> B_IWL<1283> B_IWL<1282> B_IWL<1281> B_IWL<1280> VDD_CORE VSS / RM_IHPSG13_1024x32_c2_2P_COLUMN_pcell_0 +XCOL<4> A_BLC<9> A_BLC<8> A_BLC_TOP<9> A_BLC_TOP<8> A_BLT<9> A_BLT<8> A_BLT_TOP<9> A_BLT_TOP<8> A_IWL<1023> A_IWL<1022> A_IWL<1021> A_IWL<1020> A_IWL<1019> A_IWL<1018> A_IWL<1017> A_IWL<1016> A_IWL<1015> A_IWL<1014> A_IWL<1013> A_IWL<1012> A_IWL<1011> A_IWL<1010> A_IWL<1009> A_IWL<1008> A_IWL<1007> A_IWL<1006> A_IWL<1005> A_IWL<1004> A_IWL<1003> A_IWL<1002> A_IWL<1001> A_IWL<1000> A_IWL<999> A_IWL<998> A_IWL<997> A_IWL<996> A_IWL<995> A_IWL<994> A_IWL<993> A_IWL<992> A_IWL<991> A_IWL<990> A_IWL<989> A_IWL<988> A_IWL<987> A_IWL<986> A_IWL<985> A_IWL<984> A_IWL<983> A_IWL<982> A_IWL<981> A_IWL<980> A_IWL<979> A_IWL<978> A_IWL<977> A_IWL<976> A_IWL<975> A_IWL<974> A_IWL<973> A_IWL<972> A_IWL<971> A_IWL<970> A_IWL<969> A_IWL<968> A_IWL<967> A_IWL<966> A_IWL<965> A_IWL<964> A_IWL<963> A_IWL<962> A_IWL<961> A_IWL<960> A_IWL<959> A_IWL<958> A_IWL<957> A_IWL<956> A_IWL<955> A_IWL<954> A_IWL<953> A_IWL<952> A_IWL<951> A_IWL<950> A_IWL<949> A_IWL<948> A_IWL<947> A_IWL<946> A_IWL<945> A_IWL<944> A_IWL<943> A_IWL<942> A_IWL<941> A_IWL<940> A_IWL<939> A_IWL<938> A_IWL<937> A_IWL<936> A_IWL<935> A_IWL<934> A_IWL<933> A_IWL<932> A_IWL<931> A_IWL<930> A_IWL<929> A_IWL<928> A_IWL<927> A_IWL<926> A_IWL<925> A_IWL<924> A_IWL<923> A_IWL<922> A_IWL<921> A_IWL<920> A_IWL<919> A_IWL<918> A_IWL<917> A_IWL<916> A_IWL<915> A_IWL<914> A_IWL<913> A_IWL<912> A_IWL<911> A_IWL<910> A_IWL<909> A_IWL<908> A_IWL<907> A_IWL<906> A_IWL<905> A_IWL<904> A_IWL<903> A_IWL<902> A_IWL<901> A_IWL<900> A_IWL<899> A_IWL<898> A_IWL<897> A_IWL<896> A_IWL<895> A_IWL<894> A_IWL<893> A_IWL<892> A_IWL<891> A_IWL<890> A_IWL<889> A_IWL<888> A_IWL<887> A_IWL<886> A_IWL<885> A_IWL<884> A_IWL<883> A_IWL<882> A_IWL<881> A_IWL<880> A_IWL<879> A_IWL<878> A_IWL<877> A_IWL<876> A_IWL<875> A_IWL<874> A_IWL<873> A_IWL<872> A_IWL<871> A_IWL<870> A_IWL<869> A_IWL<868> A_IWL<867> A_IWL<866> A_IWL<865> A_IWL<864> A_IWL<863> A_IWL<862> A_IWL<861> A_IWL<860> A_IWL<859> A_IWL<858> A_IWL<857> A_IWL<856> A_IWL<855> A_IWL<854> A_IWL<853> A_IWL<852> A_IWL<851> A_IWL<850> A_IWL<849> A_IWL<848> A_IWL<847> A_IWL<846> A_IWL<845> A_IWL<844> A_IWL<843> A_IWL<842> A_IWL<841> A_IWL<840> A_IWL<839> A_IWL<838> A_IWL<837> A_IWL<836> A_IWL<835> A_IWL<834> A_IWL<833> A_IWL<832> A_IWL<831> A_IWL<830> A_IWL<829> A_IWL<828> A_IWL<827> A_IWL<826> A_IWL<825> A_IWL<824> A_IWL<823> A_IWL<822> A_IWL<821> A_IWL<820> A_IWL<819> A_IWL<818> A_IWL<817> A_IWL<816> A_IWL<815> A_IWL<814> A_IWL<813> A_IWL<812> A_IWL<811> A_IWL<810> A_IWL<809> A_IWL<808> A_IWL<807> A_IWL<806> A_IWL<805> A_IWL<804> A_IWL<803> A_IWL<802> A_IWL<801> A_IWL<800> A_IWL<799> A_IWL<798> A_IWL<797> A_IWL<796> A_IWL<795> A_IWL<794> A_IWL<793> A_IWL<792> A_IWL<791> A_IWL<790> A_IWL<789> A_IWL<788> A_IWL<787> A_IWL<786> A_IWL<785> A_IWL<784> A_IWL<783> A_IWL<782> A_IWL<781> A_IWL<780> A_IWL<779> A_IWL<778> A_IWL<777> A_IWL<776> A_IWL<775> A_IWL<774> A_IWL<773> A_IWL<772> A_IWL<771> A_IWL<770> A_IWL<769> A_IWL<768> A_IWL<1279> A_IWL<1278> A_IWL<1277> A_IWL<1276> A_IWL<1275> A_IWL<1274> A_IWL<1273> A_IWL<1272> A_IWL<1271> A_IWL<1270> A_IWL<1269> A_IWL<1268> A_IWL<1267> A_IWL<1266> A_IWL<1265> A_IWL<1264> A_IWL<1263> A_IWL<1262> A_IWL<1261> A_IWL<1260> A_IWL<1259> A_IWL<1258> A_IWL<1257> A_IWL<1256> A_IWL<1255> A_IWL<1254> A_IWL<1253> A_IWL<1252> A_IWL<1251> A_IWL<1250> A_IWL<1249> A_IWL<1248> A_IWL<1247> A_IWL<1246> A_IWL<1245> A_IWL<1244> A_IWL<1243> A_IWL<1242> A_IWL<1241> A_IWL<1240> A_IWL<1239> A_IWL<1238> A_IWL<1237> A_IWL<1236> A_IWL<1235> A_IWL<1234> A_IWL<1233> A_IWL<1232> A_IWL<1231> A_IWL<1230> A_IWL<1229> A_IWL<1228> A_IWL<1227> A_IWL<1226> A_IWL<1225> A_IWL<1224> A_IWL<1223> A_IWL<1222> A_IWL<1221> A_IWL<1220> A_IWL<1219> A_IWL<1218> A_IWL<1217> A_IWL<1216> A_IWL<1215> A_IWL<1214> A_IWL<1213> A_IWL<1212> A_IWL<1211> A_IWL<1210> A_IWL<1209> A_IWL<1208> A_IWL<1207> A_IWL<1206> A_IWL<1205> A_IWL<1204> A_IWL<1203> A_IWL<1202> A_IWL<1201> A_IWL<1200> A_IWL<1199> A_IWL<1198> A_IWL<1197> A_IWL<1196> A_IWL<1195> A_IWL<1194> A_IWL<1193> A_IWL<1192> A_IWL<1191> A_IWL<1190> A_IWL<1189> A_IWL<1188> A_IWL<1187> A_IWL<1186> A_IWL<1185> A_IWL<1184> A_IWL<1183> A_IWL<1182> A_IWL<1181> A_IWL<1180> A_IWL<1179> A_IWL<1178> A_IWL<1177> A_IWL<1176> A_IWL<1175> A_IWL<1174> A_IWL<1173> A_IWL<1172> A_IWL<1171> A_IWL<1170> A_IWL<1169> A_IWL<1168> A_IWL<1167> A_IWL<1166> A_IWL<1165> A_IWL<1164> A_IWL<1163> A_IWL<1162> A_IWL<1161> A_IWL<1160> A_IWL<1159> A_IWL<1158> A_IWL<1157> A_IWL<1156> A_IWL<1155> A_IWL<1154> A_IWL<1153> A_IWL<1152> A_IWL<1151> A_IWL<1150> A_IWL<1149> A_IWL<1148> A_IWL<1147> A_IWL<1146> A_IWL<1145> A_IWL<1144> A_IWL<1143> A_IWL<1142> A_IWL<1141> A_IWL<1140> A_IWL<1139> A_IWL<1138> A_IWL<1137> A_IWL<1136> A_IWL<1135> A_IWL<1134> A_IWL<1133> A_IWL<1132> A_IWL<1131> A_IWL<1130> A_IWL<1129> A_IWL<1128> A_IWL<1127> A_IWL<1126> A_IWL<1125> A_IWL<1124> A_IWL<1123> A_IWL<1122> A_IWL<1121> A_IWL<1120> A_IWL<1119> A_IWL<1118> A_IWL<1117> A_IWL<1116> A_IWL<1115> A_IWL<1114> A_IWL<1113> A_IWL<1112> A_IWL<1111> A_IWL<1110> A_IWL<1109> A_IWL<1108> A_IWL<1107> A_IWL<1106> A_IWL<1105> A_IWL<1104> A_IWL<1103> A_IWL<1102> A_IWL<1101> A_IWL<1100> A_IWL<1099> A_IWL<1098> A_IWL<1097> A_IWL<1096> A_IWL<1095> A_IWL<1094> A_IWL<1093> A_IWL<1092> A_IWL<1091> A_IWL<1090> A_IWL<1089> A_IWL<1088> A_IWL<1087> A_IWL<1086> A_IWL<1085> A_IWL<1084> A_IWL<1083> A_IWL<1082> A_IWL<1081> A_IWL<1080> A_IWL<1079> A_IWL<1078> A_IWL<1077> A_IWL<1076> A_IWL<1075> A_IWL<1074> A_IWL<1073> A_IWL<1072> A_IWL<1071> A_IWL<1070> A_IWL<1069> A_IWL<1068> A_IWL<1067> A_IWL<1066> A_IWL<1065> A_IWL<1064> A_IWL<1063> A_IWL<1062> A_IWL<1061> A_IWL<1060> A_IWL<1059> A_IWL<1058> A_IWL<1057> A_IWL<1056> A_IWL<1055> A_IWL<1054> A_IWL<1053> A_IWL<1052> A_IWL<1051> A_IWL<1050> A_IWL<1049> A_IWL<1048> A_IWL<1047> A_IWL<1046> A_IWL<1045> A_IWL<1044> A_IWL<1043> A_IWL<1042> A_IWL<1041> A_IWL<1040> A_IWL<1039> A_IWL<1038> A_IWL<1037> A_IWL<1036> A_IWL<1035> A_IWL<1034> A_IWL<1033> A_IWL<1032> A_IWL<1031> A_IWL<1030> A_IWL<1029> A_IWL<1028> A_IWL<1027> A_IWL<1026> A_IWL<1025> A_IWL<1024> B_BLC<9> B_BLC<8> B_BLC_TOP<9> B_BLC_TOP<8> B_BLT<9> B_BLT<8> B_BLT_TOP<9> B_BLT_TOP<8> B_IWL<1023> B_IWL<1022> B_IWL<1021> B_IWL<1020> B_IWL<1019> B_IWL<1018> B_IWL<1017> B_IWL<1016> B_IWL<1015> B_IWL<1014> B_IWL<1013> B_IWL<1012> B_IWL<1011> B_IWL<1010> B_IWL<1009> B_IWL<1008> B_IWL<1007> B_IWL<1006> B_IWL<1005> B_IWL<1004> B_IWL<1003> B_IWL<1002> B_IWL<1001> B_IWL<1000> B_IWL<999> B_IWL<998> B_IWL<997> B_IWL<996> B_IWL<995> B_IWL<994> B_IWL<993> B_IWL<992> B_IWL<991> B_IWL<990> B_IWL<989> B_IWL<988> B_IWL<987> B_IWL<986> B_IWL<985> B_IWL<984> B_IWL<983> B_IWL<982> B_IWL<981> B_IWL<980> B_IWL<979> B_IWL<978> B_IWL<977> B_IWL<976> B_IWL<975> B_IWL<974> B_IWL<973> B_IWL<972> B_IWL<971> B_IWL<970> B_IWL<969> B_IWL<968> B_IWL<967> B_IWL<966> B_IWL<965> B_IWL<964> B_IWL<963> B_IWL<962> B_IWL<961> B_IWL<960> B_IWL<959> B_IWL<958> B_IWL<957> B_IWL<956> B_IWL<955> B_IWL<954> B_IWL<953> B_IWL<952> B_IWL<951> B_IWL<950> B_IWL<949> B_IWL<948> B_IWL<947> B_IWL<946> B_IWL<945> B_IWL<944> B_IWL<943> B_IWL<942> B_IWL<941> B_IWL<940> B_IWL<939> B_IWL<938> B_IWL<937> B_IWL<936> B_IWL<935> B_IWL<934> B_IWL<933> B_IWL<932> B_IWL<931> B_IWL<930> B_IWL<929> B_IWL<928> B_IWL<927> B_IWL<926> B_IWL<925> B_IWL<924> B_IWL<923> B_IWL<922> B_IWL<921> B_IWL<920> B_IWL<919> B_IWL<918> B_IWL<917> B_IWL<916> B_IWL<915> B_IWL<914> B_IWL<913> B_IWL<912> B_IWL<911> B_IWL<910> B_IWL<909> B_IWL<908> B_IWL<907> B_IWL<906> B_IWL<905> B_IWL<904> B_IWL<903> B_IWL<902> B_IWL<901> B_IWL<900> B_IWL<899> B_IWL<898> B_IWL<897> B_IWL<896> B_IWL<895> B_IWL<894> B_IWL<893> B_IWL<892> B_IWL<891> B_IWL<890> B_IWL<889> B_IWL<888> B_IWL<887> B_IWL<886> B_IWL<885> B_IWL<884> B_IWL<883> B_IWL<882> B_IWL<881> B_IWL<880> B_IWL<879> B_IWL<878> B_IWL<877> B_IWL<876> B_IWL<875> B_IWL<874> B_IWL<873> B_IWL<872> B_IWL<871> B_IWL<870> B_IWL<869> B_IWL<868> B_IWL<867> B_IWL<866> B_IWL<865> B_IWL<864> B_IWL<863> B_IWL<862> B_IWL<861> B_IWL<860> B_IWL<859> B_IWL<858> B_IWL<857> B_IWL<856> B_IWL<855> B_IWL<854> B_IWL<853> B_IWL<852> B_IWL<851> B_IWL<850> B_IWL<849> B_IWL<848> B_IWL<847> B_IWL<846> B_IWL<845> B_IWL<844> B_IWL<843> B_IWL<842> B_IWL<841> B_IWL<840> B_IWL<839> B_IWL<838> B_IWL<837> B_IWL<836> B_IWL<835> B_IWL<834> B_IWL<833> B_IWL<832> B_IWL<831> B_IWL<830> B_IWL<829> B_IWL<828> B_IWL<827> B_IWL<826> B_IWL<825> B_IWL<824> B_IWL<823> B_IWL<822> B_IWL<821> B_IWL<820> B_IWL<819> B_IWL<818> B_IWL<817> B_IWL<816> B_IWL<815> B_IWL<814> B_IWL<813> B_IWL<812> B_IWL<811> B_IWL<810> B_IWL<809> B_IWL<808> B_IWL<807> B_IWL<806> B_IWL<805> B_IWL<804> B_IWL<803> B_IWL<802> B_IWL<801> B_IWL<800> B_IWL<799> B_IWL<798> B_IWL<797> B_IWL<796> B_IWL<795> B_IWL<794> B_IWL<793> B_IWL<792> B_IWL<791> B_IWL<790> B_IWL<789> B_IWL<788> B_IWL<787> B_IWL<786> B_IWL<785> B_IWL<784> B_IWL<783> B_IWL<782> B_IWL<781> B_IWL<780> B_IWL<779> B_IWL<778> B_IWL<777> B_IWL<776> B_IWL<775> B_IWL<774> B_IWL<773> B_IWL<772> B_IWL<771> B_IWL<770> B_IWL<769> B_IWL<768> B_IWL<1279> B_IWL<1278> B_IWL<1277> B_IWL<1276> B_IWL<1275> B_IWL<1274> B_IWL<1273> B_IWL<1272> B_IWL<1271> B_IWL<1270> B_IWL<1269> B_IWL<1268> B_IWL<1267> B_IWL<1266> B_IWL<1265> B_IWL<1264> B_IWL<1263> B_IWL<1262> B_IWL<1261> B_IWL<1260> B_IWL<1259> B_IWL<1258> B_IWL<1257> B_IWL<1256> B_IWL<1255> B_IWL<1254> B_IWL<1253> B_IWL<1252> B_IWL<1251> B_IWL<1250> B_IWL<1249> B_IWL<1248> B_IWL<1247> B_IWL<1246> B_IWL<1245> B_IWL<1244> B_IWL<1243> B_IWL<1242> B_IWL<1241> B_IWL<1240> B_IWL<1239> B_IWL<1238> B_IWL<1237> B_IWL<1236> B_IWL<1235> B_IWL<1234> B_IWL<1233> B_IWL<1232> B_IWL<1231> B_IWL<1230> B_IWL<1229> B_IWL<1228> B_IWL<1227> B_IWL<1226> B_IWL<1225> B_IWL<1224> B_IWL<1223> B_IWL<1222> B_IWL<1221> B_IWL<1220> B_IWL<1219> B_IWL<1218> B_IWL<1217> B_IWL<1216> B_IWL<1215> B_IWL<1214> B_IWL<1213> B_IWL<1212> B_IWL<1211> B_IWL<1210> B_IWL<1209> B_IWL<1208> B_IWL<1207> B_IWL<1206> B_IWL<1205> B_IWL<1204> B_IWL<1203> B_IWL<1202> B_IWL<1201> B_IWL<1200> B_IWL<1199> B_IWL<1198> B_IWL<1197> B_IWL<1196> B_IWL<1195> B_IWL<1194> B_IWL<1193> B_IWL<1192> B_IWL<1191> B_IWL<1190> B_IWL<1189> B_IWL<1188> B_IWL<1187> B_IWL<1186> B_IWL<1185> B_IWL<1184> B_IWL<1183> B_IWL<1182> B_IWL<1181> B_IWL<1180> B_IWL<1179> B_IWL<1178> B_IWL<1177> B_IWL<1176> B_IWL<1175> B_IWL<1174> B_IWL<1173> B_IWL<1172> B_IWL<1171> B_IWL<1170> B_IWL<1169> B_IWL<1168> B_IWL<1167> B_IWL<1166> B_IWL<1165> B_IWL<1164> B_IWL<1163> B_IWL<1162> B_IWL<1161> B_IWL<1160> B_IWL<1159> B_IWL<1158> B_IWL<1157> B_IWL<1156> B_IWL<1155> B_IWL<1154> B_IWL<1153> B_IWL<1152> B_IWL<1151> B_IWL<1150> B_IWL<1149> B_IWL<1148> B_IWL<1147> B_IWL<1146> B_IWL<1145> B_IWL<1144> B_IWL<1143> B_IWL<1142> B_IWL<1141> B_IWL<1140> B_IWL<1139> B_IWL<1138> B_IWL<1137> B_IWL<1136> B_IWL<1135> B_IWL<1134> B_IWL<1133> B_IWL<1132> B_IWL<1131> B_IWL<1130> B_IWL<1129> B_IWL<1128> B_IWL<1127> B_IWL<1126> B_IWL<1125> B_IWL<1124> B_IWL<1123> B_IWL<1122> B_IWL<1121> B_IWL<1120> B_IWL<1119> B_IWL<1118> B_IWL<1117> B_IWL<1116> B_IWL<1115> B_IWL<1114> B_IWL<1113> B_IWL<1112> B_IWL<1111> B_IWL<1110> B_IWL<1109> B_IWL<1108> B_IWL<1107> B_IWL<1106> B_IWL<1105> B_IWL<1104> B_IWL<1103> B_IWL<1102> B_IWL<1101> B_IWL<1100> B_IWL<1099> B_IWL<1098> B_IWL<1097> B_IWL<1096> B_IWL<1095> B_IWL<1094> B_IWL<1093> B_IWL<1092> B_IWL<1091> B_IWL<1090> B_IWL<1089> B_IWL<1088> B_IWL<1087> B_IWL<1086> B_IWL<1085> B_IWL<1084> B_IWL<1083> B_IWL<1082> B_IWL<1081> B_IWL<1080> B_IWL<1079> B_IWL<1078> B_IWL<1077> B_IWL<1076> B_IWL<1075> B_IWL<1074> B_IWL<1073> B_IWL<1072> B_IWL<1071> B_IWL<1070> B_IWL<1069> B_IWL<1068> B_IWL<1067> B_IWL<1066> B_IWL<1065> B_IWL<1064> B_IWL<1063> B_IWL<1062> B_IWL<1061> B_IWL<1060> B_IWL<1059> B_IWL<1058> B_IWL<1057> B_IWL<1056> B_IWL<1055> B_IWL<1054> B_IWL<1053> B_IWL<1052> B_IWL<1051> B_IWL<1050> B_IWL<1049> B_IWL<1048> B_IWL<1047> B_IWL<1046> B_IWL<1045> B_IWL<1044> B_IWL<1043> B_IWL<1042> B_IWL<1041> B_IWL<1040> B_IWL<1039> B_IWL<1038> B_IWL<1037> B_IWL<1036> B_IWL<1035> B_IWL<1034> B_IWL<1033> B_IWL<1032> B_IWL<1031> B_IWL<1030> B_IWL<1029> B_IWL<1028> B_IWL<1027> B_IWL<1026> B_IWL<1025> B_IWL<1024> VDD_CORE VSS / RM_IHPSG13_1024x32_c2_2P_COLUMN_pcell_0 +XCOL<3> A_BLC<7> A_BLC<6> A_BLC_TOP<7> A_BLC_TOP<6> A_BLT<7> A_BLT<6> A_BLT_TOP<7> A_BLT_TOP<6> A_IWL<767> A_IWL<766> A_IWL<765> A_IWL<764> A_IWL<763> A_IWL<762> A_IWL<761> A_IWL<760> A_IWL<759> A_IWL<758> A_IWL<757> A_IWL<756> A_IWL<755> A_IWL<754> A_IWL<753> A_IWL<752> A_IWL<751> A_IWL<750> A_IWL<749> A_IWL<748> A_IWL<747> A_IWL<746> A_IWL<745> A_IWL<744> A_IWL<743> A_IWL<742> A_IWL<741> A_IWL<740> A_IWL<739> A_IWL<738> A_IWL<737> A_IWL<736> A_IWL<735> A_IWL<734> A_IWL<733> A_IWL<732> A_IWL<731> A_IWL<730> A_IWL<729> A_IWL<728> A_IWL<727> A_IWL<726> A_IWL<725> A_IWL<724> A_IWL<723> A_IWL<722> A_IWL<721> A_IWL<720> A_IWL<719> A_IWL<718> A_IWL<717> A_IWL<716> A_IWL<715> A_IWL<714> A_IWL<713> A_IWL<712> A_IWL<711> A_IWL<710> A_IWL<709> A_IWL<708> A_IWL<707> A_IWL<706> A_IWL<705> A_IWL<704> A_IWL<703> A_IWL<702> A_IWL<701> A_IWL<700> A_IWL<699> A_IWL<698> A_IWL<697> A_IWL<696> A_IWL<695> A_IWL<694> A_IWL<693> A_IWL<692> A_IWL<691> A_IWL<690> A_IWL<689> A_IWL<688> A_IWL<687> A_IWL<686> A_IWL<685> A_IWL<684> A_IWL<683> A_IWL<682> A_IWL<681> A_IWL<680> A_IWL<679> A_IWL<678> A_IWL<677> A_IWL<676> A_IWL<675> A_IWL<674> A_IWL<673> A_IWL<672> A_IWL<671> A_IWL<670> A_IWL<669> A_IWL<668> A_IWL<667> A_IWL<666> A_IWL<665> A_IWL<664> A_IWL<663> A_IWL<662> A_IWL<661> A_IWL<660> A_IWL<659> A_IWL<658> A_IWL<657> A_IWL<656> A_IWL<655> A_IWL<654> A_IWL<653> A_IWL<652> A_IWL<651> A_IWL<650> A_IWL<649> A_IWL<648> A_IWL<647> A_IWL<646> A_IWL<645> A_IWL<644> A_IWL<643> A_IWL<642> A_IWL<641> A_IWL<640> A_IWL<639> A_IWL<638> A_IWL<637> A_IWL<636> A_IWL<635> A_IWL<634> A_IWL<633> A_IWL<632> A_IWL<631> A_IWL<630> A_IWL<629> A_IWL<628> A_IWL<627> A_IWL<626> A_IWL<625> A_IWL<624> A_IWL<623> A_IWL<622> A_IWL<621> A_IWL<620> A_IWL<619> A_IWL<618> A_IWL<617> A_IWL<616> A_IWL<615> A_IWL<614> A_IWL<613> A_IWL<612> A_IWL<611> A_IWL<610> A_IWL<609> A_IWL<608> A_IWL<607> A_IWL<606> A_IWL<605> A_IWL<604> A_IWL<603> A_IWL<602> A_IWL<601> A_IWL<600> A_IWL<599> A_IWL<598> A_IWL<597> A_IWL<596> A_IWL<595> A_IWL<594> A_IWL<593> A_IWL<592> A_IWL<591> A_IWL<590> A_IWL<589> A_IWL<588> A_IWL<587> A_IWL<586> A_IWL<585> A_IWL<584> A_IWL<583> A_IWL<582> A_IWL<581> A_IWL<580> A_IWL<579> A_IWL<578> A_IWL<577> A_IWL<576> A_IWL<575> A_IWL<574> A_IWL<573> A_IWL<572> A_IWL<571> A_IWL<570> A_IWL<569> A_IWL<568> A_IWL<567> A_IWL<566> A_IWL<565> A_IWL<564> A_IWL<563> A_IWL<562> A_IWL<561> A_IWL<560> A_IWL<559> A_IWL<558> A_IWL<557> A_IWL<556> A_IWL<555> A_IWL<554> A_IWL<553> A_IWL<552> A_IWL<551> A_IWL<550> A_IWL<549> A_IWL<548> A_IWL<547> A_IWL<546> A_IWL<545> A_IWL<544> A_IWL<543> A_IWL<542> A_IWL<541> A_IWL<540> A_IWL<539> A_IWL<538> A_IWL<537> A_IWL<536> A_IWL<535> A_IWL<534> A_IWL<533> A_IWL<532> A_IWL<531> A_IWL<530> A_IWL<529> A_IWL<528> A_IWL<527> A_IWL<526> A_IWL<525> A_IWL<524> A_IWL<523> A_IWL<522> A_IWL<521> A_IWL<520> A_IWL<519> A_IWL<518> A_IWL<517> A_IWL<516> A_IWL<515> A_IWL<514> A_IWL<513> A_IWL<512> A_IWL<1023> A_IWL<1022> A_IWL<1021> A_IWL<1020> A_IWL<1019> A_IWL<1018> A_IWL<1017> A_IWL<1016> A_IWL<1015> A_IWL<1014> A_IWL<1013> A_IWL<1012> A_IWL<1011> A_IWL<1010> A_IWL<1009> A_IWL<1008> A_IWL<1007> A_IWL<1006> A_IWL<1005> A_IWL<1004> A_IWL<1003> A_IWL<1002> A_IWL<1001> A_IWL<1000> A_IWL<999> A_IWL<998> A_IWL<997> A_IWL<996> A_IWL<995> A_IWL<994> A_IWL<993> A_IWL<992> A_IWL<991> A_IWL<990> A_IWL<989> A_IWL<988> A_IWL<987> A_IWL<986> A_IWL<985> A_IWL<984> A_IWL<983> A_IWL<982> A_IWL<981> A_IWL<980> A_IWL<979> A_IWL<978> A_IWL<977> A_IWL<976> A_IWL<975> A_IWL<974> A_IWL<973> A_IWL<972> A_IWL<971> A_IWL<970> A_IWL<969> A_IWL<968> A_IWL<967> A_IWL<966> A_IWL<965> A_IWL<964> A_IWL<963> A_IWL<962> A_IWL<961> A_IWL<960> A_IWL<959> A_IWL<958> A_IWL<957> A_IWL<956> A_IWL<955> A_IWL<954> A_IWL<953> A_IWL<952> A_IWL<951> A_IWL<950> A_IWL<949> A_IWL<948> A_IWL<947> A_IWL<946> A_IWL<945> A_IWL<944> A_IWL<943> A_IWL<942> A_IWL<941> A_IWL<940> A_IWL<939> A_IWL<938> A_IWL<937> A_IWL<936> A_IWL<935> A_IWL<934> A_IWL<933> A_IWL<932> A_IWL<931> A_IWL<930> A_IWL<929> A_IWL<928> A_IWL<927> A_IWL<926> A_IWL<925> A_IWL<924> A_IWL<923> A_IWL<922> A_IWL<921> A_IWL<920> A_IWL<919> A_IWL<918> A_IWL<917> A_IWL<916> A_IWL<915> A_IWL<914> A_IWL<913> A_IWL<912> A_IWL<911> A_IWL<910> A_IWL<909> A_IWL<908> A_IWL<907> A_IWL<906> A_IWL<905> A_IWL<904> A_IWL<903> A_IWL<902> A_IWL<901> A_IWL<900> A_IWL<899> A_IWL<898> A_IWL<897> A_IWL<896> A_IWL<895> A_IWL<894> A_IWL<893> A_IWL<892> A_IWL<891> A_IWL<890> A_IWL<889> A_IWL<888> A_IWL<887> A_IWL<886> A_IWL<885> A_IWL<884> A_IWL<883> A_IWL<882> A_IWL<881> A_IWL<880> A_IWL<879> A_IWL<878> A_IWL<877> A_IWL<876> A_IWL<875> A_IWL<874> A_IWL<873> A_IWL<872> A_IWL<871> A_IWL<870> A_IWL<869> A_IWL<868> A_IWL<867> A_IWL<866> A_IWL<865> A_IWL<864> A_IWL<863> A_IWL<862> A_IWL<861> A_IWL<860> A_IWL<859> A_IWL<858> A_IWL<857> A_IWL<856> A_IWL<855> A_IWL<854> A_IWL<853> A_IWL<852> A_IWL<851> A_IWL<850> A_IWL<849> A_IWL<848> A_IWL<847> A_IWL<846> A_IWL<845> A_IWL<844> A_IWL<843> A_IWL<842> A_IWL<841> A_IWL<840> A_IWL<839> A_IWL<838> A_IWL<837> A_IWL<836> A_IWL<835> A_IWL<834> A_IWL<833> A_IWL<832> A_IWL<831> A_IWL<830> A_IWL<829> A_IWL<828> A_IWL<827> A_IWL<826> A_IWL<825> A_IWL<824> A_IWL<823> A_IWL<822> A_IWL<821> A_IWL<820> A_IWL<819> A_IWL<818> A_IWL<817> A_IWL<816> A_IWL<815> A_IWL<814> A_IWL<813> A_IWL<812> A_IWL<811> A_IWL<810> A_IWL<809> A_IWL<808> A_IWL<807> A_IWL<806> A_IWL<805> A_IWL<804> A_IWL<803> A_IWL<802> A_IWL<801> A_IWL<800> A_IWL<799> A_IWL<798> A_IWL<797> A_IWL<796> A_IWL<795> A_IWL<794> A_IWL<793> A_IWL<792> A_IWL<791> A_IWL<790> A_IWL<789> A_IWL<788> A_IWL<787> A_IWL<786> A_IWL<785> A_IWL<784> A_IWL<783> A_IWL<782> A_IWL<781> A_IWL<780> A_IWL<779> A_IWL<778> A_IWL<777> A_IWL<776> A_IWL<775> A_IWL<774> A_IWL<773> A_IWL<772> A_IWL<771> A_IWL<770> A_IWL<769> A_IWL<768> B_BLC<7> B_BLC<6> B_BLC_TOP<7> B_BLC_TOP<6> B_BLT<7> B_BLT<6> B_BLT_TOP<7> B_BLT_TOP<6> B_IWL<767> B_IWL<766> B_IWL<765> B_IWL<764> B_IWL<763> B_IWL<762> B_IWL<761> B_IWL<760> B_IWL<759> B_IWL<758> B_IWL<757> B_IWL<756> B_IWL<755> B_IWL<754> B_IWL<753> B_IWL<752> B_IWL<751> B_IWL<750> B_IWL<749> B_IWL<748> B_IWL<747> B_IWL<746> B_IWL<745> B_IWL<744> B_IWL<743> B_IWL<742> B_IWL<741> B_IWL<740> B_IWL<739> B_IWL<738> B_IWL<737> B_IWL<736> B_IWL<735> B_IWL<734> B_IWL<733> B_IWL<732> B_IWL<731> B_IWL<730> B_IWL<729> B_IWL<728> B_IWL<727> B_IWL<726> B_IWL<725> B_IWL<724> B_IWL<723> B_IWL<722> B_IWL<721> B_IWL<720> B_IWL<719> B_IWL<718> B_IWL<717> B_IWL<716> B_IWL<715> B_IWL<714> B_IWL<713> B_IWL<712> B_IWL<711> B_IWL<710> B_IWL<709> B_IWL<708> B_IWL<707> B_IWL<706> B_IWL<705> B_IWL<704> B_IWL<703> B_IWL<702> B_IWL<701> B_IWL<700> B_IWL<699> B_IWL<698> B_IWL<697> B_IWL<696> B_IWL<695> B_IWL<694> B_IWL<693> B_IWL<692> B_IWL<691> B_IWL<690> B_IWL<689> B_IWL<688> B_IWL<687> B_IWL<686> B_IWL<685> B_IWL<684> B_IWL<683> B_IWL<682> B_IWL<681> B_IWL<680> B_IWL<679> B_IWL<678> B_IWL<677> B_IWL<676> B_IWL<675> B_IWL<674> B_IWL<673> B_IWL<672> B_IWL<671> B_IWL<670> B_IWL<669> B_IWL<668> B_IWL<667> B_IWL<666> B_IWL<665> B_IWL<664> B_IWL<663> B_IWL<662> B_IWL<661> B_IWL<660> B_IWL<659> B_IWL<658> B_IWL<657> B_IWL<656> B_IWL<655> B_IWL<654> B_IWL<653> B_IWL<652> B_IWL<651> B_IWL<650> B_IWL<649> B_IWL<648> B_IWL<647> B_IWL<646> B_IWL<645> B_IWL<644> B_IWL<643> B_IWL<642> B_IWL<641> B_IWL<640> B_IWL<639> B_IWL<638> B_IWL<637> B_IWL<636> B_IWL<635> B_IWL<634> B_IWL<633> B_IWL<632> B_IWL<631> B_IWL<630> B_IWL<629> B_IWL<628> B_IWL<627> B_IWL<626> B_IWL<625> B_IWL<624> B_IWL<623> B_IWL<622> B_IWL<621> B_IWL<620> B_IWL<619> B_IWL<618> B_IWL<617> B_IWL<616> B_IWL<615> B_IWL<614> B_IWL<613> B_IWL<612> B_IWL<611> B_IWL<610> B_IWL<609> B_IWL<608> B_IWL<607> B_IWL<606> B_IWL<605> B_IWL<604> B_IWL<603> B_IWL<602> B_IWL<601> B_IWL<600> B_IWL<599> B_IWL<598> B_IWL<597> B_IWL<596> B_IWL<595> B_IWL<594> B_IWL<593> B_IWL<592> B_IWL<591> B_IWL<590> B_IWL<589> B_IWL<588> B_IWL<587> B_IWL<586> B_IWL<585> B_IWL<584> B_IWL<583> B_IWL<582> B_IWL<581> B_IWL<580> B_IWL<579> B_IWL<578> B_IWL<577> B_IWL<576> B_IWL<575> B_IWL<574> B_IWL<573> B_IWL<572> B_IWL<571> B_IWL<570> B_IWL<569> B_IWL<568> B_IWL<567> B_IWL<566> B_IWL<565> B_IWL<564> B_IWL<563> B_IWL<562> B_IWL<561> B_IWL<560> B_IWL<559> B_IWL<558> B_IWL<557> B_IWL<556> B_IWL<555> B_IWL<554> B_IWL<553> B_IWL<552> B_IWL<551> B_IWL<550> B_IWL<549> B_IWL<548> B_IWL<547> B_IWL<546> B_IWL<545> B_IWL<544> B_IWL<543> B_IWL<542> B_IWL<541> B_IWL<540> B_IWL<539> B_IWL<538> B_IWL<537> B_IWL<536> B_IWL<535> B_IWL<534> B_IWL<533> B_IWL<532> B_IWL<531> B_IWL<530> B_IWL<529> B_IWL<528> B_IWL<527> B_IWL<526> B_IWL<525> B_IWL<524> B_IWL<523> B_IWL<522> B_IWL<521> B_IWL<520> B_IWL<519> B_IWL<518> B_IWL<517> B_IWL<516> B_IWL<515> B_IWL<514> B_IWL<513> B_IWL<512> B_IWL<1023> B_IWL<1022> B_IWL<1021> B_IWL<1020> B_IWL<1019> B_IWL<1018> B_IWL<1017> B_IWL<1016> B_IWL<1015> B_IWL<1014> B_IWL<1013> B_IWL<1012> B_IWL<1011> B_IWL<1010> B_IWL<1009> B_IWL<1008> B_IWL<1007> B_IWL<1006> B_IWL<1005> B_IWL<1004> B_IWL<1003> B_IWL<1002> B_IWL<1001> B_IWL<1000> B_IWL<999> B_IWL<998> B_IWL<997> B_IWL<996> B_IWL<995> B_IWL<994> B_IWL<993> B_IWL<992> B_IWL<991> B_IWL<990> B_IWL<989> B_IWL<988> B_IWL<987> B_IWL<986> B_IWL<985> B_IWL<984> B_IWL<983> B_IWL<982> B_IWL<981> B_IWL<980> B_IWL<979> B_IWL<978> B_IWL<977> B_IWL<976> B_IWL<975> B_IWL<974> B_IWL<973> B_IWL<972> B_IWL<971> B_IWL<970> B_IWL<969> B_IWL<968> B_IWL<967> B_IWL<966> B_IWL<965> B_IWL<964> B_IWL<963> B_IWL<962> B_IWL<961> B_IWL<960> B_IWL<959> B_IWL<958> B_IWL<957> B_IWL<956> B_IWL<955> B_IWL<954> B_IWL<953> B_IWL<952> B_IWL<951> B_IWL<950> B_IWL<949> B_IWL<948> B_IWL<947> B_IWL<946> B_IWL<945> B_IWL<944> B_IWL<943> B_IWL<942> B_IWL<941> B_IWL<940> B_IWL<939> B_IWL<938> B_IWL<937> B_IWL<936> B_IWL<935> B_IWL<934> B_IWL<933> B_IWL<932> B_IWL<931> B_IWL<930> B_IWL<929> B_IWL<928> B_IWL<927> B_IWL<926> B_IWL<925> B_IWL<924> B_IWL<923> B_IWL<922> B_IWL<921> B_IWL<920> B_IWL<919> B_IWL<918> B_IWL<917> B_IWL<916> B_IWL<915> B_IWL<914> B_IWL<913> B_IWL<912> B_IWL<911> B_IWL<910> B_IWL<909> B_IWL<908> B_IWL<907> B_IWL<906> B_IWL<905> B_IWL<904> B_IWL<903> B_IWL<902> B_IWL<901> B_IWL<900> B_IWL<899> B_IWL<898> B_IWL<897> B_IWL<896> B_IWL<895> B_IWL<894> B_IWL<893> B_IWL<892> B_IWL<891> B_IWL<890> B_IWL<889> B_IWL<888> B_IWL<887> B_IWL<886> B_IWL<885> B_IWL<884> B_IWL<883> B_IWL<882> B_IWL<881> B_IWL<880> B_IWL<879> B_IWL<878> B_IWL<877> B_IWL<876> B_IWL<875> B_IWL<874> B_IWL<873> B_IWL<872> B_IWL<871> B_IWL<870> B_IWL<869> B_IWL<868> B_IWL<867> B_IWL<866> B_IWL<865> B_IWL<864> B_IWL<863> B_IWL<862> B_IWL<861> B_IWL<860> B_IWL<859> B_IWL<858> B_IWL<857> B_IWL<856> B_IWL<855> B_IWL<854> B_IWL<853> B_IWL<852> B_IWL<851> B_IWL<850> B_IWL<849> B_IWL<848> B_IWL<847> B_IWL<846> B_IWL<845> B_IWL<844> B_IWL<843> B_IWL<842> B_IWL<841> B_IWL<840> B_IWL<839> B_IWL<838> B_IWL<837> B_IWL<836> B_IWL<835> B_IWL<834> B_IWL<833> B_IWL<832> B_IWL<831> B_IWL<830> B_IWL<829> B_IWL<828> B_IWL<827> B_IWL<826> B_IWL<825> B_IWL<824> B_IWL<823> B_IWL<822> B_IWL<821> B_IWL<820> B_IWL<819> B_IWL<818> B_IWL<817> B_IWL<816> B_IWL<815> B_IWL<814> B_IWL<813> B_IWL<812> B_IWL<811> B_IWL<810> B_IWL<809> B_IWL<808> B_IWL<807> B_IWL<806> B_IWL<805> B_IWL<804> B_IWL<803> B_IWL<802> B_IWL<801> B_IWL<800> B_IWL<799> B_IWL<798> B_IWL<797> B_IWL<796> B_IWL<795> B_IWL<794> B_IWL<793> B_IWL<792> B_IWL<791> B_IWL<790> B_IWL<789> B_IWL<788> B_IWL<787> B_IWL<786> B_IWL<785> B_IWL<784> B_IWL<783> B_IWL<782> B_IWL<781> B_IWL<780> B_IWL<779> B_IWL<778> B_IWL<777> B_IWL<776> B_IWL<775> B_IWL<774> B_IWL<773> B_IWL<772> B_IWL<771> B_IWL<770> B_IWL<769> B_IWL<768> VDD_CORE VSS / RM_IHPSG13_1024x32_c2_2P_COLUMN_pcell_0 +XCOL<2> A_BLC<5> A_BLC<4> A_BLC_TOP<5> A_BLC_TOP<4> A_BLT<5> A_BLT<4> A_BLT_TOP<5> A_BLT_TOP<4> A_IWL<511> A_IWL<510> A_IWL<509> A_IWL<508> A_IWL<507> A_IWL<506> A_IWL<505> A_IWL<504> A_IWL<503> A_IWL<502> A_IWL<501> A_IWL<500> A_IWL<499> A_IWL<498> A_IWL<497> A_IWL<496> A_IWL<495> A_IWL<494> A_IWL<493> A_IWL<492> A_IWL<491> A_IWL<490> A_IWL<489> A_IWL<488> A_IWL<487> A_IWL<486> A_IWL<485> A_IWL<484> A_IWL<483> A_IWL<482> A_IWL<481> A_IWL<480> A_IWL<479> A_IWL<478> A_IWL<477> A_IWL<476> A_IWL<475> A_IWL<474> A_IWL<473> A_IWL<472> A_IWL<471> A_IWL<470> A_IWL<469> A_IWL<468> A_IWL<467> A_IWL<466> A_IWL<465> A_IWL<464> A_IWL<463> A_IWL<462> A_IWL<461> A_IWL<460> A_IWL<459> A_IWL<458> A_IWL<457> A_IWL<456> A_IWL<455> A_IWL<454> A_IWL<453> A_IWL<452> A_IWL<451> A_IWL<450> A_IWL<449> A_IWL<448> A_IWL<447> A_IWL<446> A_IWL<445> A_IWL<444> A_IWL<443> A_IWL<442> A_IWL<441> A_IWL<440> A_IWL<439> A_IWL<438> A_IWL<437> A_IWL<436> A_IWL<435> A_IWL<434> A_IWL<433> A_IWL<432> A_IWL<431> A_IWL<430> A_IWL<429> A_IWL<428> A_IWL<427> A_IWL<426> A_IWL<425> A_IWL<424> A_IWL<423> A_IWL<422> A_IWL<421> A_IWL<420> A_IWL<419> A_IWL<418> A_IWL<417> A_IWL<416> A_IWL<415> A_IWL<414> A_IWL<413> A_IWL<412> A_IWL<411> A_IWL<410> A_IWL<409> A_IWL<408> A_IWL<407> A_IWL<406> A_IWL<405> A_IWL<404> A_IWL<403> A_IWL<402> A_IWL<401> A_IWL<400> A_IWL<399> A_IWL<398> A_IWL<397> A_IWL<396> A_IWL<395> A_IWL<394> A_IWL<393> A_IWL<392> A_IWL<391> A_IWL<390> A_IWL<389> A_IWL<388> A_IWL<387> A_IWL<386> A_IWL<385> A_IWL<384> A_IWL<383> A_IWL<382> A_IWL<381> A_IWL<380> A_IWL<379> A_IWL<378> A_IWL<377> A_IWL<376> A_IWL<375> A_IWL<374> A_IWL<373> A_IWL<372> A_IWL<371> A_IWL<370> A_IWL<369> A_IWL<368> A_IWL<367> A_IWL<366> A_IWL<365> A_IWL<364> A_IWL<363> A_IWL<362> A_IWL<361> A_IWL<360> A_IWL<359> A_IWL<358> A_IWL<357> A_IWL<356> A_IWL<355> A_IWL<354> A_IWL<353> A_IWL<352> A_IWL<351> A_IWL<350> A_IWL<349> A_IWL<348> A_IWL<347> A_IWL<346> A_IWL<345> A_IWL<344> A_IWL<343> A_IWL<342> A_IWL<341> A_IWL<340> A_IWL<339> A_IWL<338> A_IWL<337> A_IWL<336> A_IWL<335> A_IWL<334> A_IWL<333> A_IWL<332> A_IWL<331> A_IWL<330> A_IWL<329> A_IWL<328> A_IWL<327> A_IWL<326> A_IWL<325> A_IWL<324> A_IWL<323> A_IWL<322> A_IWL<321> A_IWL<320> A_IWL<319> A_IWL<318> A_IWL<317> A_IWL<316> A_IWL<315> A_IWL<314> A_IWL<313> A_IWL<312> A_IWL<311> A_IWL<310> A_IWL<309> A_IWL<308> A_IWL<307> A_IWL<306> A_IWL<305> A_IWL<304> A_IWL<303> A_IWL<302> A_IWL<301> A_IWL<300> A_IWL<299> A_IWL<298> A_IWL<297> A_IWL<296> A_IWL<295> A_IWL<294> A_IWL<293> A_IWL<292> A_IWL<291> A_IWL<290> A_IWL<289> A_IWL<288> A_IWL<287> A_IWL<286> A_IWL<285> A_IWL<284> A_IWL<283> A_IWL<282> A_IWL<281> A_IWL<280> A_IWL<279> A_IWL<278> A_IWL<277> A_IWL<276> A_IWL<275> A_IWL<274> A_IWL<273> A_IWL<272> A_IWL<271> A_IWL<270> A_IWL<269> A_IWL<268> A_IWL<267> A_IWL<266> A_IWL<265> A_IWL<264> A_IWL<263> A_IWL<262> A_IWL<261> A_IWL<260> A_IWL<259> A_IWL<258> A_IWL<257> A_IWL<256> A_IWL<767> A_IWL<766> A_IWL<765> A_IWL<764> A_IWL<763> A_IWL<762> A_IWL<761> A_IWL<760> A_IWL<759> A_IWL<758> A_IWL<757> A_IWL<756> A_IWL<755> A_IWL<754> A_IWL<753> A_IWL<752> A_IWL<751> A_IWL<750> A_IWL<749> A_IWL<748> A_IWL<747> A_IWL<746> A_IWL<745> A_IWL<744> A_IWL<743> A_IWL<742> A_IWL<741> A_IWL<740> A_IWL<739> A_IWL<738> A_IWL<737> A_IWL<736> A_IWL<735> A_IWL<734> A_IWL<733> A_IWL<732> A_IWL<731> A_IWL<730> A_IWL<729> A_IWL<728> A_IWL<727> A_IWL<726> A_IWL<725> A_IWL<724> A_IWL<723> A_IWL<722> A_IWL<721> A_IWL<720> A_IWL<719> A_IWL<718> A_IWL<717> A_IWL<716> A_IWL<715> A_IWL<714> A_IWL<713> A_IWL<712> A_IWL<711> A_IWL<710> A_IWL<709> A_IWL<708> A_IWL<707> A_IWL<706> A_IWL<705> A_IWL<704> A_IWL<703> A_IWL<702> A_IWL<701> A_IWL<700> A_IWL<699> A_IWL<698> A_IWL<697> A_IWL<696> A_IWL<695> A_IWL<694> A_IWL<693> A_IWL<692> A_IWL<691> A_IWL<690> A_IWL<689> A_IWL<688> A_IWL<687> A_IWL<686> A_IWL<685> A_IWL<684> A_IWL<683> A_IWL<682> A_IWL<681> A_IWL<680> A_IWL<679> A_IWL<678> A_IWL<677> A_IWL<676> A_IWL<675> A_IWL<674> A_IWL<673> A_IWL<672> A_IWL<671> A_IWL<670> A_IWL<669> A_IWL<668> A_IWL<667> A_IWL<666> A_IWL<665> A_IWL<664> A_IWL<663> A_IWL<662> A_IWL<661> A_IWL<660> A_IWL<659> A_IWL<658> A_IWL<657> A_IWL<656> A_IWL<655> A_IWL<654> A_IWL<653> A_IWL<652> A_IWL<651> A_IWL<650> A_IWL<649> A_IWL<648> A_IWL<647> A_IWL<646> A_IWL<645> A_IWL<644> A_IWL<643> A_IWL<642> A_IWL<641> A_IWL<640> A_IWL<639> A_IWL<638> A_IWL<637> A_IWL<636> A_IWL<635> A_IWL<634> A_IWL<633> A_IWL<632> A_IWL<631> A_IWL<630> A_IWL<629> A_IWL<628> A_IWL<627> A_IWL<626> A_IWL<625> A_IWL<624> A_IWL<623> A_IWL<622> A_IWL<621> A_IWL<620> A_IWL<619> A_IWL<618> A_IWL<617> A_IWL<616> A_IWL<615> A_IWL<614> A_IWL<613> A_IWL<612> A_IWL<611> A_IWL<610> A_IWL<609> A_IWL<608> A_IWL<607> A_IWL<606> A_IWL<605> A_IWL<604> A_IWL<603> A_IWL<602> A_IWL<601> A_IWL<600> A_IWL<599> A_IWL<598> A_IWL<597> A_IWL<596> A_IWL<595> A_IWL<594> A_IWL<593> A_IWL<592> A_IWL<591> A_IWL<590> A_IWL<589> A_IWL<588> A_IWL<587> A_IWL<586> A_IWL<585> A_IWL<584> A_IWL<583> A_IWL<582> A_IWL<581> A_IWL<580> A_IWL<579> A_IWL<578> A_IWL<577> A_IWL<576> A_IWL<575> A_IWL<574> A_IWL<573> A_IWL<572> A_IWL<571> A_IWL<570> A_IWL<569> A_IWL<568> A_IWL<567> A_IWL<566> A_IWL<565> A_IWL<564> A_IWL<563> A_IWL<562> A_IWL<561> A_IWL<560> A_IWL<559> A_IWL<558> A_IWL<557> A_IWL<556> A_IWL<555> A_IWL<554> A_IWL<553> A_IWL<552> A_IWL<551> A_IWL<550> A_IWL<549> A_IWL<548> A_IWL<547> A_IWL<546> A_IWL<545> A_IWL<544> A_IWL<543> A_IWL<542> A_IWL<541> A_IWL<540> A_IWL<539> A_IWL<538> A_IWL<537> A_IWL<536> A_IWL<535> A_IWL<534> A_IWL<533> A_IWL<532> A_IWL<531> A_IWL<530> A_IWL<529> A_IWL<528> A_IWL<527> A_IWL<526> A_IWL<525> A_IWL<524> A_IWL<523> A_IWL<522> A_IWL<521> A_IWL<520> A_IWL<519> A_IWL<518> A_IWL<517> A_IWL<516> A_IWL<515> A_IWL<514> A_IWL<513> A_IWL<512> B_BLC<5> B_BLC<4> B_BLC_TOP<5> B_BLC_TOP<4> B_BLT<5> B_BLT<4> B_BLT_TOP<5> B_BLT_TOP<4> B_IWL<511> B_IWL<510> B_IWL<509> B_IWL<508> B_IWL<507> B_IWL<506> B_IWL<505> B_IWL<504> B_IWL<503> B_IWL<502> B_IWL<501> B_IWL<500> B_IWL<499> B_IWL<498> B_IWL<497> B_IWL<496> B_IWL<495> B_IWL<494> B_IWL<493> B_IWL<492> B_IWL<491> B_IWL<490> B_IWL<489> B_IWL<488> B_IWL<487> B_IWL<486> B_IWL<485> B_IWL<484> B_IWL<483> B_IWL<482> B_IWL<481> B_IWL<480> B_IWL<479> B_IWL<478> B_IWL<477> B_IWL<476> B_IWL<475> B_IWL<474> B_IWL<473> B_IWL<472> B_IWL<471> B_IWL<470> B_IWL<469> B_IWL<468> B_IWL<467> B_IWL<466> B_IWL<465> B_IWL<464> B_IWL<463> B_IWL<462> B_IWL<461> B_IWL<460> B_IWL<459> B_IWL<458> B_IWL<457> B_IWL<456> B_IWL<455> B_IWL<454> B_IWL<453> B_IWL<452> B_IWL<451> B_IWL<450> B_IWL<449> B_IWL<448> B_IWL<447> B_IWL<446> B_IWL<445> B_IWL<444> B_IWL<443> B_IWL<442> B_IWL<441> B_IWL<440> B_IWL<439> B_IWL<438> B_IWL<437> B_IWL<436> B_IWL<435> B_IWL<434> B_IWL<433> B_IWL<432> B_IWL<431> B_IWL<430> B_IWL<429> B_IWL<428> B_IWL<427> B_IWL<426> B_IWL<425> B_IWL<424> B_IWL<423> B_IWL<422> B_IWL<421> B_IWL<420> B_IWL<419> B_IWL<418> B_IWL<417> B_IWL<416> B_IWL<415> B_IWL<414> B_IWL<413> B_IWL<412> B_IWL<411> B_IWL<410> B_IWL<409> B_IWL<408> B_IWL<407> B_IWL<406> B_IWL<405> B_IWL<404> B_IWL<403> B_IWL<402> B_IWL<401> B_IWL<400> B_IWL<399> B_IWL<398> B_IWL<397> B_IWL<396> B_IWL<395> B_IWL<394> B_IWL<393> B_IWL<392> B_IWL<391> B_IWL<390> B_IWL<389> B_IWL<388> B_IWL<387> B_IWL<386> B_IWL<385> B_IWL<384> B_IWL<383> B_IWL<382> B_IWL<381> B_IWL<380> B_IWL<379> B_IWL<378> B_IWL<377> B_IWL<376> B_IWL<375> B_IWL<374> B_IWL<373> B_IWL<372> B_IWL<371> B_IWL<370> B_IWL<369> B_IWL<368> B_IWL<367> B_IWL<366> B_IWL<365> B_IWL<364> B_IWL<363> B_IWL<362> B_IWL<361> B_IWL<360> B_IWL<359> B_IWL<358> B_IWL<357> B_IWL<356> B_IWL<355> B_IWL<354> B_IWL<353> B_IWL<352> B_IWL<351> B_IWL<350> B_IWL<349> B_IWL<348> B_IWL<347> B_IWL<346> B_IWL<345> B_IWL<344> B_IWL<343> B_IWL<342> B_IWL<341> B_IWL<340> B_IWL<339> B_IWL<338> B_IWL<337> B_IWL<336> B_IWL<335> B_IWL<334> B_IWL<333> B_IWL<332> B_IWL<331> B_IWL<330> B_IWL<329> B_IWL<328> B_IWL<327> B_IWL<326> B_IWL<325> B_IWL<324> B_IWL<323> B_IWL<322> B_IWL<321> B_IWL<320> B_IWL<319> B_IWL<318> B_IWL<317> B_IWL<316> B_IWL<315> B_IWL<314> B_IWL<313> B_IWL<312> B_IWL<311> B_IWL<310> B_IWL<309> B_IWL<308> B_IWL<307> B_IWL<306> B_IWL<305> B_IWL<304> B_IWL<303> B_IWL<302> B_IWL<301> B_IWL<300> B_IWL<299> B_IWL<298> B_IWL<297> B_IWL<296> B_IWL<295> B_IWL<294> B_IWL<293> B_IWL<292> B_IWL<291> B_IWL<290> B_IWL<289> B_IWL<288> B_IWL<287> B_IWL<286> B_IWL<285> B_IWL<284> B_IWL<283> B_IWL<282> B_IWL<281> B_IWL<280> B_IWL<279> B_IWL<278> B_IWL<277> B_IWL<276> B_IWL<275> B_IWL<274> B_IWL<273> B_IWL<272> B_IWL<271> B_IWL<270> B_IWL<269> B_IWL<268> B_IWL<267> B_IWL<266> B_IWL<265> B_IWL<264> B_IWL<263> B_IWL<262> B_IWL<261> B_IWL<260> B_IWL<259> B_IWL<258> B_IWL<257> B_IWL<256> B_IWL<767> B_IWL<766> B_IWL<765> B_IWL<764> B_IWL<763> B_IWL<762> B_IWL<761> B_IWL<760> B_IWL<759> B_IWL<758> B_IWL<757> B_IWL<756> B_IWL<755> B_IWL<754> B_IWL<753> B_IWL<752> B_IWL<751> B_IWL<750> B_IWL<749> B_IWL<748> B_IWL<747> B_IWL<746> B_IWL<745> B_IWL<744> B_IWL<743> B_IWL<742> B_IWL<741> B_IWL<740> B_IWL<739> B_IWL<738> B_IWL<737> B_IWL<736> B_IWL<735> B_IWL<734> B_IWL<733> B_IWL<732> B_IWL<731> B_IWL<730> B_IWL<729> B_IWL<728> B_IWL<727> B_IWL<726> B_IWL<725> B_IWL<724> B_IWL<723> B_IWL<722> B_IWL<721> B_IWL<720> B_IWL<719> B_IWL<718> B_IWL<717> B_IWL<716> B_IWL<715> B_IWL<714> B_IWL<713> B_IWL<712> B_IWL<711> B_IWL<710> B_IWL<709> B_IWL<708> B_IWL<707> B_IWL<706> B_IWL<705> B_IWL<704> B_IWL<703> B_IWL<702> B_IWL<701> B_IWL<700> B_IWL<699> B_IWL<698> B_IWL<697> B_IWL<696> B_IWL<695> B_IWL<694> B_IWL<693> B_IWL<692> B_IWL<691> B_IWL<690> B_IWL<689> B_IWL<688> B_IWL<687> B_IWL<686> B_IWL<685> B_IWL<684> B_IWL<683> B_IWL<682> B_IWL<681> B_IWL<680> B_IWL<679> B_IWL<678> B_IWL<677> B_IWL<676> B_IWL<675> B_IWL<674> B_IWL<673> B_IWL<672> B_IWL<671> B_IWL<670> B_IWL<669> B_IWL<668> B_IWL<667> B_IWL<666> B_IWL<665> B_IWL<664> B_IWL<663> B_IWL<662> B_IWL<661> B_IWL<660> B_IWL<659> B_IWL<658> B_IWL<657> B_IWL<656> B_IWL<655> B_IWL<654> B_IWL<653> B_IWL<652> B_IWL<651> B_IWL<650> B_IWL<649> B_IWL<648> B_IWL<647> B_IWL<646> B_IWL<645> B_IWL<644> B_IWL<643> B_IWL<642> B_IWL<641> B_IWL<640> B_IWL<639> B_IWL<638> B_IWL<637> B_IWL<636> B_IWL<635> B_IWL<634> B_IWL<633> B_IWL<632> B_IWL<631> B_IWL<630> B_IWL<629> B_IWL<628> B_IWL<627> B_IWL<626> B_IWL<625> B_IWL<624> B_IWL<623> B_IWL<622> B_IWL<621> B_IWL<620> B_IWL<619> B_IWL<618> B_IWL<617> B_IWL<616> B_IWL<615> B_IWL<614> B_IWL<613> B_IWL<612> B_IWL<611> B_IWL<610> B_IWL<609> B_IWL<608> B_IWL<607> B_IWL<606> B_IWL<605> B_IWL<604> B_IWL<603> B_IWL<602> B_IWL<601> B_IWL<600> B_IWL<599> B_IWL<598> B_IWL<597> B_IWL<596> B_IWL<595> B_IWL<594> B_IWL<593> B_IWL<592> B_IWL<591> B_IWL<590> B_IWL<589> B_IWL<588> B_IWL<587> B_IWL<586> B_IWL<585> B_IWL<584> B_IWL<583> B_IWL<582> B_IWL<581> B_IWL<580> B_IWL<579> B_IWL<578> B_IWL<577> B_IWL<576> B_IWL<575> B_IWL<574> B_IWL<573> B_IWL<572> B_IWL<571> B_IWL<570> B_IWL<569> B_IWL<568> B_IWL<567> B_IWL<566> B_IWL<565> B_IWL<564> B_IWL<563> B_IWL<562> B_IWL<561> B_IWL<560> B_IWL<559> B_IWL<558> B_IWL<557> B_IWL<556> B_IWL<555> B_IWL<554> B_IWL<553> B_IWL<552> B_IWL<551> B_IWL<550> B_IWL<549> B_IWL<548> B_IWL<547> B_IWL<546> B_IWL<545> B_IWL<544> B_IWL<543> B_IWL<542> B_IWL<541> B_IWL<540> B_IWL<539> B_IWL<538> B_IWL<537> B_IWL<536> B_IWL<535> B_IWL<534> B_IWL<533> B_IWL<532> B_IWL<531> B_IWL<530> B_IWL<529> B_IWL<528> B_IWL<527> B_IWL<526> B_IWL<525> B_IWL<524> B_IWL<523> B_IWL<522> B_IWL<521> B_IWL<520> B_IWL<519> B_IWL<518> B_IWL<517> B_IWL<516> B_IWL<515> B_IWL<514> B_IWL<513> B_IWL<512> VDD_CORE VSS / RM_IHPSG13_1024x32_c2_2P_COLUMN_pcell_0 +XCOL<1> A_BLC<3> A_BLC<2> A_BLC_TOP<3> A_BLC_TOP<2> A_BLT<3> A_BLT<2> A_BLT_TOP<3> A_BLT_TOP<2> A_IWL<255> A_IWL<254> A_IWL<253> A_IWL<252> A_IWL<251> A_IWL<250> A_IWL<249> A_IWL<248> A_IWL<247> A_IWL<246> A_IWL<245> A_IWL<244> A_IWL<243> A_IWL<242> A_IWL<241> A_IWL<240> A_IWL<239> A_IWL<238> A_IWL<237> A_IWL<236> A_IWL<235> A_IWL<234> A_IWL<233> A_IWL<232> A_IWL<231> A_IWL<230> A_IWL<229> A_IWL<228> A_IWL<227> A_IWL<226> A_IWL<225> A_IWL<224> A_IWL<223> A_IWL<222> A_IWL<221> A_IWL<220> A_IWL<219> A_IWL<218> A_IWL<217> A_IWL<216> A_IWL<215> A_IWL<214> A_IWL<213> A_IWL<212> A_IWL<211> A_IWL<210> A_IWL<209> A_IWL<208> A_IWL<207> A_IWL<206> A_IWL<205> A_IWL<204> A_IWL<203> A_IWL<202> A_IWL<201> A_IWL<200> A_IWL<199> A_IWL<198> A_IWL<197> A_IWL<196> A_IWL<195> A_IWL<194> A_IWL<193> A_IWL<192> A_IWL<191> A_IWL<190> A_IWL<189> A_IWL<188> A_IWL<187> A_IWL<186> A_IWL<185> A_IWL<184> A_IWL<183> A_IWL<182> A_IWL<181> A_IWL<180> A_IWL<179> A_IWL<178> A_IWL<177> A_IWL<176> A_IWL<175> A_IWL<174> A_IWL<173> A_IWL<172> A_IWL<171> A_IWL<170> A_IWL<169> A_IWL<168> A_IWL<167> A_IWL<166> A_IWL<165> A_IWL<164> A_IWL<163> A_IWL<162> A_IWL<161> A_IWL<160> A_IWL<159> A_IWL<158> A_IWL<157> A_IWL<156> A_IWL<155> A_IWL<154> A_IWL<153> A_IWL<152> A_IWL<151> A_IWL<150> A_IWL<149> A_IWL<148> A_IWL<147> A_IWL<146> A_IWL<145> A_IWL<144> A_IWL<143> A_IWL<142> A_IWL<141> A_IWL<140> A_IWL<139> A_IWL<138> A_IWL<137> A_IWL<136> A_IWL<135> A_IWL<134> A_IWL<133> A_IWL<132> A_IWL<131> A_IWL<130> A_IWL<129> A_IWL<128> A_IWL<127> A_IWL<126> A_IWL<125> A_IWL<124> A_IWL<123> A_IWL<122> A_IWL<121> A_IWL<120> A_IWL<119> A_IWL<118> A_IWL<117> A_IWL<116> A_IWL<115> A_IWL<114> A_IWL<113> A_IWL<112> A_IWL<111> A_IWL<110> A_IWL<109> A_IWL<108> A_IWL<107> A_IWL<106> A_IWL<105> A_IWL<104> A_IWL<103> A_IWL<102> A_IWL<101> A_IWL<100> A_IWL<99> A_IWL<98> A_IWL<97> A_IWL<96> A_IWL<95> A_IWL<94> A_IWL<93> A_IWL<92> A_IWL<91> A_IWL<90> A_IWL<89> A_IWL<88> A_IWL<87> A_IWL<86> A_IWL<85> A_IWL<84> A_IWL<83> A_IWL<82> A_IWL<81> A_IWL<80> A_IWL<79> A_IWL<78> A_IWL<77> A_IWL<76> A_IWL<75> A_IWL<74> A_IWL<73> A_IWL<72> A_IWL<71> A_IWL<70> A_IWL<69> A_IWL<68> A_IWL<67> A_IWL<66> A_IWL<65> A_IWL<64> A_IWL<63> A_IWL<62> A_IWL<61> A_IWL<60> A_IWL<59> A_IWL<58> A_IWL<57> A_IWL<56> A_IWL<55> A_IWL<54> A_IWL<53> A_IWL<52> A_IWL<51> A_IWL<50> A_IWL<49> A_IWL<48> A_IWL<47> A_IWL<46> A_IWL<45> A_IWL<44> A_IWL<43> A_IWL<42> A_IWL<41> A_IWL<40> A_IWL<39> A_IWL<38> A_IWL<37> A_IWL<36> A_IWL<35> A_IWL<34> A_IWL<33> A_IWL<32> A_IWL<31> A_IWL<30> A_IWL<29> A_IWL<28> A_IWL<27> A_IWL<26> A_IWL<25> A_IWL<24> A_IWL<23> A_IWL<22> A_IWL<21> A_IWL<20> A_IWL<19> A_IWL<18> A_IWL<17> A_IWL<16> A_IWL<15> A_IWL<14> A_IWL<13> A_IWL<12> A_IWL<11> A_IWL<10> A_IWL<9> A_IWL<8> A_IWL<7> A_IWL<6> A_IWL<5> A_IWL<4> A_IWL<3> A_IWL<2> A_IWL<1> A_IWL<0> A_IWL<511> A_IWL<510> A_IWL<509> A_IWL<508> A_IWL<507> A_IWL<506> A_IWL<505> A_IWL<504> A_IWL<503> A_IWL<502> A_IWL<501> A_IWL<500> A_IWL<499> A_IWL<498> A_IWL<497> A_IWL<496> A_IWL<495> A_IWL<494> A_IWL<493> A_IWL<492> A_IWL<491> A_IWL<490> A_IWL<489> A_IWL<488> A_IWL<487> A_IWL<486> A_IWL<485> A_IWL<484> A_IWL<483> A_IWL<482> A_IWL<481> A_IWL<480> A_IWL<479> A_IWL<478> A_IWL<477> A_IWL<476> A_IWL<475> A_IWL<474> A_IWL<473> A_IWL<472> A_IWL<471> A_IWL<470> A_IWL<469> A_IWL<468> A_IWL<467> A_IWL<466> A_IWL<465> A_IWL<464> A_IWL<463> A_IWL<462> A_IWL<461> A_IWL<460> A_IWL<459> A_IWL<458> A_IWL<457> A_IWL<456> A_IWL<455> A_IWL<454> A_IWL<453> A_IWL<452> A_IWL<451> A_IWL<450> A_IWL<449> A_IWL<448> A_IWL<447> A_IWL<446> A_IWL<445> A_IWL<444> A_IWL<443> A_IWL<442> A_IWL<441> A_IWL<440> A_IWL<439> A_IWL<438> A_IWL<437> A_IWL<436> A_IWL<435> A_IWL<434> A_IWL<433> A_IWL<432> A_IWL<431> A_IWL<430> A_IWL<429> A_IWL<428> A_IWL<427> A_IWL<426> A_IWL<425> A_IWL<424> A_IWL<423> A_IWL<422> A_IWL<421> A_IWL<420> A_IWL<419> A_IWL<418> A_IWL<417> A_IWL<416> A_IWL<415> A_IWL<414> A_IWL<413> A_IWL<412> A_IWL<411> A_IWL<410> A_IWL<409> A_IWL<408> A_IWL<407> A_IWL<406> A_IWL<405> A_IWL<404> A_IWL<403> A_IWL<402> A_IWL<401> A_IWL<400> A_IWL<399> A_IWL<398> A_IWL<397> A_IWL<396> A_IWL<395> A_IWL<394> A_IWL<393> A_IWL<392> A_IWL<391> A_IWL<390> A_IWL<389> A_IWL<388> A_IWL<387> A_IWL<386> A_IWL<385> A_IWL<384> A_IWL<383> A_IWL<382> A_IWL<381> A_IWL<380> A_IWL<379> A_IWL<378> A_IWL<377> A_IWL<376> A_IWL<375> A_IWL<374> A_IWL<373> A_IWL<372> A_IWL<371> A_IWL<370> A_IWL<369> A_IWL<368> A_IWL<367> A_IWL<366> A_IWL<365> A_IWL<364> A_IWL<363> A_IWL<362> A_IWL<361> A_IWL<360> A_IWL<359> A_IWL<358> A_IWL<357> A_IWL<356> A_IWL<355> A_IWL<354> A_IWL<353> A_IWL<352> A_IWL<351> A_IWL<350> A_IWL<349> A_IWL<348> A_IWL<347> A_IWL<346> A_IWL<345> A_IWL<344> A_IWL<343> A_IWL<342> A_IWL<341> A_IWL<340> A_IWL<339> A_IWL<338> A_IWL<337> A_IWL<336> A_IWL<335> A_IWL<334> A_IWL<333> A_IWL<332> A_IWL<331> A_IWL<330> A_IWL<329> A_IWL<328> A_IWL<327> A_IWL<326> A_IWL<325> A_IWL<324> A_IWL<323> A_IWL<322> A_IWL<321> A_IWL<320> A_IWL<319> A_IWL<318> A_IWL<317> A_IWL<316> A_IWL<315> A_IWL<314> A_IWL<313> A_IWL<312> A_IWL<311> A_IWL<310> A_IWL<309> A_IWL<308> A_IWL<307> A_IWL<306> A_IWL<305> A_IWL<304> A_IWL<303> A_IWL<302> A_IWL<301> A_IWL<300> A_IWL<299> A_IWL<298> A_IWL<297> A_IWL<296> A_IWL<295> A_IWL<294> A_IWL<293> A_IWL<292> A_IWL<291> A_IWL<290> A_IWL<289> A_IWL<288> A_IWL<287> A_IWL<286> A_IWL<285> A_IWL<284> A_IWL<283> A_IWL<282> A_IWL<281> A_IWL<280> A_IWL<279> A_IWL<278> A_IWL<277> A_IWL<276> A_IWL<275> A_IWL<274> A_IWL<273> A_IWL<272> A_IWL<271> A_IWL<270> A_IWL<269> A_IWL<268> A_IWL<267> A_IWL<266> A_IWL<265> A_IWL<264> A_IWL<263> A_IWL<262> A_IWL<261> A_IWL<260> A_IWL<259> A_IWL<258> A_IWL<257> A_IWL<256> B_BLC<3> B_BLC<2> B_BLC_TOP<3> B_BLC_TOP<2> B_BLT<3> B_BLT<2> B_BLT_TOP<3> B_BLT_TOP<2> B_IWL<255> B_IWL<254> B_IWL<253> B_IWL<252> B_IWL<251> B_IWL<250> B_IWL<249> B_IWL<248> B_IWL<247> B_IWL<246> B_IWL<245> B_IWL<244> B_IWL<243> B_IWL<242> B_IWL<241> B_IWL<240> B_IWL<239> B_IWL<238> B_IWL<237> B_IWL<236> B_IWL<235> B_IWL<234> B_IWL<233> B_IWL<232> B_IWL<231> B_IWL<230> B_IWL<229> B_IWL<228> B_IWL<227> B_IWL<226> B_IWL<225> B_IWL<224> B_IWL<223> B_IWL<222> B_IWL<221> B_IWL<220> B_IWL<219> B_IWL<218> B_IWL<217> B_IWL<216> B_IWL<215> B_IWL<214> B_IWL<213> B_IWL<212> B_IWL<211> B_IWL<210> B_IWL<209> B_IWL<208> B_IWL<207> B_IWL<206> B_IWL<205> B_IWL<204> B_IWL<203> B_IWL<202> B_IWL<201> B_IWL<200> B_IWL<199> B_IWL<198> B_IWL<197> B_IWL<196> B_IWL<195> B_IWL<194> B_IWL<193> B_IWL<192> B_IWL<191> B_IWL<190> B_IWL<189> B_IWL<188> B_IWL<187> B_IWL<186> B_IWL<185> B_IWL<184> B_IWL<183> B_IWL<182> B_IWL<181> B_IWL<180> B_IWL<179> B_IWL<178> B_IWL<177> B_IWL<176> B_IWL<175> B_IWL<174> B_IWL<173> B_IWL<172> B_IWL<171> B_IWL<170> B_IWL<169> B_IWL<168> B_IWL<167> B_IWL<166> B_IWL<165> B_IWL<164> B_IWL<163> B_IWL<162> B_IWL<161> B_IWL<160> B_IWL<159> B_IWL<158> B_IWL<157> B_IWL<156> B_IWL<155> B_IWL<154> B_IWL<153> B_IWL<152> B_IWL<151> B_IWL<150> B_IWL<149> B_IWL<148> B_IWL<147> B_IWL<146> B_IWL<145> B_IWL<144> B_IWL<143> B_IWL<142> B_IWL<141> B_IWL<140> B_IWL<139> B_IWL<138> B_IWL<137> B_IWL<136> B_IWL<135> B_IWL<134> B_IWL<133> B_IWL<132> B_IWL<131> B_IWL<130> B_IWL<129> B_IWL<128> B_IWL<127> B_IWL<126> B_IWL<125> B_IWL<124> B_IWL<123> B_IWL<122> B_IWL<121> B_IWL<120> B_IWL<119> B_IWL<118> B_IWL<117> B_IWL<116> B_IWL<115> B_IWL<114> B_IWL<113> B_IWL<112> B_IWL<111> B_IWL<110> B_IWL<109> B_IWL<108> B_IWL<107> B_IWL<106> B_IWL<105> B_IWL<104> B_IWL<103> B_IWL<102> B_IWL<101> B_IWL<100> B_IWL<99> B_IWL<98> B_IWL<97> B_IWL<96> B_IWL<95> B_IWL<94> B_IWL<93> B_IWL<92> B_IWL<91> B_IWL<90> B_IWL<89> B_IWL<88> B_IWL<87> B_IWL<86> B_IWL<85> B_IWL<84> B_IWL<83> B_IWL<82> B_IWL<81> B_IWL<80> B_IWL<79> B_IWL<78> B_IWL<77> B_IWL<76> B_IWL<75> B_IWL<74> B_IWL<73> B_IWL<72> B_IWL<71> B_IWL<70> B_IWL<69> B_IWL<68> B_IWL<67> B_IWL<66> B_IWL<65> B_IWL<64> B_IWL<63> B_IWL<62> B_IWL<61> B_IWL<60> B_IWL<59> B_IWL<58> B_IWL<57> B_IWL<56> B_IWL<55> B_IWL<54> B_IWL<53> B_IWL<52> B_IWL<51> B_IWL<50> B_IWL<49> B_IWL<48> B_IWL<47> B_IWL<46> B_IWL<45> B_IWL<44> B_IWL<43> B_IWL<42> B_IWL<41> B_IWL<40> B_IWL<39> B_IWL<38> B_IWL<37> B_IWL<36> B_IWL<35> B_IWL<34> B_IWL<33> B_IWL<32> B_IWL<31> B_IWL<30> B_IWL<29> B_IWL<28> B_IWL<27> B_IWL<26> B_IWL<25> B_IWL<24> B_IWL<23> B_IWL<22> B_IWL<21> B_IWL<20> B_IWL<19> B_IWL<18> B_IWL<17> B_IWL<16> B_IWL<15> B_IWL<14> B_IWL<13> B_IWL<12> B_IWL<11> B_IWL<10> B_IWL<9> B_IWL<8> B_IWL<7> B_IWL<6> B_IWL<5> B_IWL<4> B_IWL<3> B_IWL<2> B_IWL<1> B_IWL<0> B_IWL<511> B_IWL<510> B_IWL<509> B_IWL<508> B_IWL<507> B_IWL<506> B_IWL<505> B_IWL<504> B_IWL<503> B_IWL<502> B_IWL<501> B_IWL<500> B_IWL<499> B_IWL<498> B_IWL<497> B_IWL<496> B_IWL<495> B_IWL<494> B_IWL<493> B_IWL<492> B_IWL<491> B_IWL<490> B_IWL<489> B_IWL<488> B_IWL<487> B_IWL<486> B_IWL<485> B_IWL<484> B_IWL<483> B_IWL<482> B_IWL<481> B_IWL<480> B_IWL<479> B_IWL<478> B_IWL<477> B_IWL<476> B_IWL<475> B_IWL<474> B_IWL<473> B_IWL<472> B_IWL<471> B_IWL<470> B_IWL<469> B_IWL<468> B_IWL<467> B_IWL<466> B_IWL<465> B_IWL<464> B_IWL<463> B_IWL<462> B_IWL<461> B_IWL<460> B_IWL<459> B_IWL<458> B_IWL<457> B_IWL<456> B_IWL<455> B_IWL<454> B_IWL<453> B_IWL<452> B_IWL<451> B_IWL<450> B_IWL<449> B_IWL<448> B_IWL<447> B_IWL<446> B_IWL<445> B_IWL<444> B_IWL<443> B_IWL<442> B_IWL<441> B_IWL<440> B_IWL<439> B_IWL<438> B_IWL<437> B_IWL<436> B_IWL<435> B_IWL<434> B_IWL<433> B_IWL<432> B_IWL<431> B_IWL<430> B_IWL<429> B_IWL<428> B_IWL<427> B_IWL<426> B_IWL<425> B_IWL<424> B_IWL<423> B_IWL<422> B_IWL<421> B_IWL<420> B_IWL<419> B_IWL<418> B_IWL<417> B_IWL<416> B_IWL<415> B_IWL<414> B_IWL<413> B_IWL<412> B_IWL<411> B_IWL<410> B_IWL<409> B_IWL<408> B_IWL<407> B_IWL<406> B_IWL<405> B_IWL<404> B_IWL<403> B_IWL<402> B_IWL<401> B_IWL<400> B_IWL<399> B_IWL<398> B_IWL<397> B_IWL<396> B_IWL<395> B_IWL<394> B_IWL<393> B_IWL<392> B_IWL<391> B_IWL<390> B_IWL<389> B_IWL<388> B_IWL<387> B_IWL<386> B_IWL<385> B_IWL<384> B_IWL<383> B_IWL<382> B_IWL<381> B_IWL<380> B_IWL<379> B_IWL<378> B_IWL<377> B_IWL<376> B_IWL<375> B_IWL<374> B_IWL<373> B_IWL<372> B_IWL<371> B_IWL<370> B_IWL<369> B_IWL<368> B_IWL<367> B_IWL<366> B_IWL<365> B_IWL<364> B_IWL<363> B_IWL<362> B_IWL<361> B_IWL<360> B_IWL<359> B_IWL<358> B_IWL<357> B_IWL<356> B_IWL<355> B_IWL<354> B_IWL<353> B_IWL<352> B_IWL<351> B_IWL<350> B_IWL<349> B_IWL<348> B_IWL<347> B_IWL<346> B_IWL<345> B_IWL<344> B_IWL<343> B_IWL<342> B_IWL<341> B_IWL<340> B_IWL<339> B_IWL<338> B_IWL<337> B_IWL<336> B_IWL<335> B_IWL<334> B_IWL<333> B_IWL<332> B_IWL<331> B_IWL<330> B_IWL<329> B_IWL<328> B_IWL<327> B_IWL<326> B_IWL<325> B_IWL<324> B_IWL<323> B_IWL<322> B_IWL<321> B_IWL<320> B_IWL<319> B_IWL<318> B_IWL<317> B_IWL<316> B_IWL<315> B_IWL<314> B_IWL<313> B_IWL<312> B_IWL<311> B_IWL<310> B_IWL<309> B_IWL<308> B_IWL<307> B_IWL<306> B_IWL<305> B_IWL<304> B_IWL<303> B_IWL<302> B_IWL<301> B_IWL<300> B_IWL<299> B_IWL<298> B_IWL<297> B_IWL<296> B_IWL<295> B_IWL<294> B_IWL<293> B_IWL<292> B_IWL<291> B_IWL<290> B_IWL<289> B_IWL<288> B_IWL<287> B_IWL<286> B_IWL<285> B_IWL<284> B_IWL<283> B_IWL<282> B_IWL<281> B_IWL<280> B_IWL<279> B_IWL<278> B_IWL<277> B_IWL<276> B_IWL<275> B_IWL<274> B_IWL<273> B_IWL<272> B_IWL<271> B_IWL<270> B_IWL<269> B_IWL<268> B_IWL<267> B_IWL<266> B_IWL<265> B_IWL<264> B_IWL<263> B_IWL<262> B_IWL<261> B_IWL<260> B_IWL<259> B_IWL<258> B_IWL<257> B_IWL<256> VDD_CORE VSS / RM_IHPSG13_1024x32_c2_2P_COLUMN_pcell_0 +XCOL<0> A_BLC<1> A_BLC<0> A_BLC_TOP<1> A_BLC_TOP<0> A_BLT<1> A_BLT<0> A_BLT_TOP<1> A_BLT_TOP<0> A_WL<255> A_WL<254> A_WL<253> A_WL<252> A_WL<251> A_WL<250> A_WL<249> A_WL<248> A_WL<247> A_WL<246> A_WL<245> A_WL<244> A_WL<243> A_WL<242> A_WL<241> A_WL<240> A_WL<239> A_WL<238> A_WL<237> A_WL<236> A_WL<235> A_WL<234> A_WL<233> A_WL<232> A_WL<231> A_WL<230> A_WL<229> A_WL<228> A_WL<227> A_WL<226> A_WL<225> A_WL<224> A_WL<223> A_WL<222> A_WL<221> A_WL<220> A_WL<219> A_WL<218> A_WL<217> A_WL<216> A_WL<215> A_WL<214> A_WL<213> A_WL<212> A_WL<211> A_WL<210> A_WL<209> A_WL<208> A_WL<207> A_WL<206> A_WL<205> A_WL<204> A_WL<203> A_WL<202> A_WL<201> A_WL<200> A_WL<199> A_WL<198> A_WL<197> A_WL<196> A_WL<195> A_WL<194> A_WL<193> A_WL<192> A_WL<191> A_WL<190> A_WL<189> A_WL<188> A_WL<187> A_WL<186> A_WL<185> A_WL<184> A_WL<183> A_WL<182> A_WL<181> A_WL<180> A_WL<179> A_WL<178> A_WL<177> A_WL<176> A_WL<175> A_WL<174> A_WL<173> A_WL<172> A_WL<171> A_WL<170> A_WL<169> A_WL<168> A_WL<167> A_WL<166> A_WL<165> A_WL<164> A_WL<163> A_WL<162> A_WL<161> A_WL<160> A_WL<159> A_WL<158> A_WL<157> A_WL<156> A_WL<155> A_WL<154> A_WL<153> A_WL<152> A_WL<151> A_WL<150> A_WL<149> A_WL<148> A_WL<147> A_WL<146> A_WL<145> A_WL<144> A_WL<143> A_WL<142> A_WL<141> A_WL<140> A_WL<139> A_WL<138> A_WL<137> A_WL<136> A_WL<135> A_WL<134> A_WL<133> A_WL<132> A_WL<131> A_WL<130> A_WL<129> A_WL<128> A_WL<127> A_WL<126> A_WL<125> A_WL<124> A_WL<123> A_WL<122> A_WL<121> A_WL<120> A_WL<119> A_WL<118> A_WL<117> A_WL<116> A_WL<115> A_WL<114> A_WL<113> A_WL<112> A_WL<111> A_WL<110> A_WL<109> A_WL<108> A_WL<107> A_WL<106> A_WL<105> A_WL<104> A_WL<103> A_WL<102> A_WL<101> A_WL<100> A_WL<99> A_WL<98> A_WL<97> A_WL<96> A_WL<95> A_WL<94> A_WL<93> A_WL<92> A_WL<91> A_WL<90> A_WL<89> A_WL<88> A_WL<87> A_WL<86> A_WL<85> A_WL<84> A_WL<83> A_WL<82> A_WL<81> A_WL<80> A_WL<79> A_WL<78> A_WL<77> A_WL<76> A_WL<75> A_WL<74> A_WL<73> A_WL<72> A_WL<71> A_WL<70> A_WL<69> A_WL<68> A_WL<67> A_WL<66> A_WL<65> A_WL<64> A_WL<63> A_WL<62> A_WL<61> A_WL<60> A_WL<59> A_WL<58> A_WL<57> A_WL<56> A_WL<55> A_WL<54> A_WL<53> A_WL<52> A_WL<51> A_WL<50> A_WL<49> A_WL<48> A_WL<47> A_WL<46> A_WL<45> A_WL<44> A_WL<43> A_WL<42> A_WL<41> A_WL<40> A_WL<39> A_WL<38> A_WL<37> A_WL<36> A_WL<35> A_WL<34> A_WL<33> A_WL<32> A_WL<31> A_WL<30> A_WL<29> A_WL<28> A_WL<27> A_WL<26> A_WL<25> A_WL<24> A_WL<23> A_WL<22> A_WL<21> A_WL<20> A_WL<19> A_WL<18> A_WL<17> A_WL<16> A_WL<15> A_WL<14> A_WL<13> A_WL<12> A_WL<11> A_WL<10> A_WL<9> A_WL<8> A_WL<7> A_WL<6> A_WL<5> A_WL<4> A_WL<3> A_WL<2> A_WL<1> A_WL<0> A_IWL<255> A_IWL<254> A_IWL<253> A_IWL<252> A_IWL<251> A_IWL<250> A_IWL<249> A_IWL<248> A_IWL<247> A_IWL<246> A_IWL<245> A_IWL<244> A_IWL<243> A_IWL<242> A_IWL<241> A_IWL<240> A_IWL<239> A_IWL<238> A_IWL<237> A_IWL<236> A_IWL<235> A_IWL<234> A_IWL<233> A_IWL<232> A_IWL<231> A_IWL<230> A_IWL<229> A_IWL<228> A_IWL<227> A_IWL<226> A_IWL<225> A_IWL<224> A_IWL<223> A_IWL<222> A_IWL<221> A_IWL<220> A_IWL<219> A_IWL<218> A_IWL<217> A_IWL<216> A_IWL<215> A_IWL<214> A_IWL<213> A_IWL<212> A_IWL<211> A_IWL<210> A_IWL<209> A_IWL<208> A_IWL<207> A_IWL<206> A_IWL<205> A_IWL<204> A_IWL<203> A_IWL<202> A_IWL<201> A_IWL<200> A_IWL<199> A_IWL<198> A_IWL<197> A_IWL<196> A_IWL<195> A_IWL<194> A_IWL<193> A_IWL<192> A_IWL<191> A_IWL<190> A_IWL<189> A_IWL<188> A_IWL<187> A_IWL<186> A_IWL<185> A_IWL<184> A_IWL<183> A_IWL<182> A_IWL<181> A_IWL<180> A_IWL<179> A_IWL<178> A_IWL<177> A_IWL<176> A_IWL<175> A_IWL<174> A_IWL<173> A_IWL<172> A_IWL<171> A_IWL<170> A_IWL<169> A_IWL<168> A_IWL<167> A_IWL<166> A_IWL<165> A_IWL<164> A_IWL<163> A_IWL<162> A_IWL<161> A_IWL<160> A_IWL<159> A_IWL<158> A_IWL<157> A_IWL<156> A_IWL<155> A_IWL<154> A_IWL<153> A_IWL<152> A_IWL<151> A_IWL<150> A_IWL<149> A_IWL<148> A_IWL<147> A_IWL<146> A_IWL<145> A_IWL<144> A_IWL<143> A_IWL<142> A_IWL<141> A_IWL<140> A_IWL<139> A_IWL<138> A_IWL<137> A_IWL<136> A_IWL<135> A_IWL<134> A_IWL<133> A_IWL<132> A_IWL<131> A_IWL<130> A_IWL<129> A_IWL<128> A_IWL<127> A_IWL<126> A_IWL<125> A_IWL<124> A_IWL<123> A_IWL<122> A_IWL<121> A_IWL<120> A_IWL<119> A_IWL<118> A_IWL<117> A_IWL<116> A_IWL<115> A_IWL<114> A_IWL<113> A_IWL<112> A_IWL<111> A_IWL<110> A_IWL<109> A_IWL<108> A_IWL<107> A_IWL<106> A_IWL<105> A_IWL<104> A_IWL<103> A_IWL<102> A_IWL<101> A_IWL<100> A_IWL<99> A_IWL<98> A_IWL<97> A_IWL<96> A_IWL<95> A_IWL<94> A_IWL<93> A_IWL<92> A_IWL<91> A_IWL<90> A_IWL<89> A_IWL<88> A_IWL<87> A_IWL<86> A_IWL<85> A_IWL<84> A_IWL<83> A_IWL<82> A_IWL<81> A_IWL<80> A_IWL<79> A_IWL<78> A_IWL<77> A_IWL<76> A_IWL<75> A_IWL<74> A_IWL<73> A_IWL<72> A_IWL<71> A_IWL<70> A_IWL<69> A_IWL<68> A_IWL<67> A_IWL<66> A_IWL<65> A_IWL<64> A_IWL<63> A_IWL<62> A_IWL<61> A_IWL<60> A_IWL<59> A_IWL<58> A_IWL<57> A_IWL<56> A_IWL<55> A_IWL<54> A_IWL<53> A_IWL<52> A_IWL<51> A_IWL<50> A_IWL<49> A_IWL<48> A_IWL<47> A_IWL<46> A_IWL<45> A_IWL<44> A_IWL<43> A_IWL<42> A_IWL<41> A_IWL<40> A_IWL<39> A_IWL<38> A_IWL<37> A_IWL<36> A_IWL<35> A_IWL<34> A_IWL<33> A_IWL<32> A_IWL<31> A_IWL<30> A_IWL<29> A_IWL<28> A_IWL<27> A_IWL<26> A_IWL<25> A_IWL<24> A_IWL<23> A_IWL<22> A_IWL<21> A_IWL<20> A_IWL<19> A_IWL<18> A_IWL<17> A_IWL<16> A_IWL<15> A_IWL<14> A_IWL<13> A_IWL<12> A_IWL<11> A_IWL<10> A_IWL<9> A_IWL<8> A_IWL<7> A_IWL<6> A_IWL<5> A_IWL<4> A_IWL<3> A_IWL<2> A_IWL<1> A_IWL<0> B_BLC<1> B_BLC<0> B_BLC_TOP<1> B_BLC_TOP<0> B_BLT<1> B_BLT<0> B_BLT_TOP<1> B_BLT_TOP<0> B_WL<255> B_WL<254> B_WL<253> B_WL<252> B_WL<251> B_WL<250> B_WL<249> B_WL<248> B_WL<247> B_WL<246> B_WL<245> B_WL<244> B_WL<243> B_WL<242> B_WL<241> B_WL<240> B_WL<239> B_WL<238> B_WL<237> B_WL<236> B_WL<235> B_WL<234> B_WL<233> B_WL<232> B_WL<231> B_WL<230> B_WL<229> B_WL<228> B_WL<227> B_WL<226> B_WL<225> B_WL<224> B_WL<223> B_WL<222> B_WL<221> B_WL<220> B_WL<219> B_WL<218> B_WL<217> B_WL<216> B_WL<215> B_WL<214> B_WL<213> B_WL<212> B_WL<211> B_WL<210> B_WL<209> B_WL<208> B_WL<207> B_WL<206> B_WL<205> B_WL<204> B_WL<203> B_WL<202> B_WL<201> B_WL<200> B_WL<199> B_WL<198> B_WL<197> B_WL<196> B_WL<195> B_WL<194> B_WL<193> B_WL<192> B_WL<191> B_WL<190> B_WL<189> B_WL<188> B_WL<187> B_WL<186> B_WL<185> B_WL<184> B_WL<183> B_WL<182> B_WL<181> B_WL<180> B_WL<179> B_WL<178> B_WL<177> B_WL<176> B_WL<175> B_WL<174> B_WL<173> B_WL<172> B_WL<171> B_WL<170> B_WL<169> B_WL<168> B_WL<167> B_WL<166> B_WL<165> B_WL<164> B_WL<163> B_WL<162> B_WL<161> B_WL<160> B_WL<159> B_WL<158> B_WL<157> B_WL<156> B_WL<155> B_WL<154> B_WL<153> B_WL<152> B_WL<151> B_WL<150> B_WL<149> B_WL<148> B_WL<147> B_WL<146> B_WL<145> B_WL<144> B_WL<143> B_WL<142> B_WL<141> B_WL<140> B_WL<139> B_WL<138> B_WL<137> B_WL<136> B_WL<135> B_WL<134> B_WL<133> B_WL<132> B_WL<131> B_WL<130> B_WL<129> B_WL<128> B_WL<127> B_WL<126> B_WL<125> B_WL<124> B_WL<123> B_WL<122> B_WL<121> B_WL<120> B_WL<119> B_WL<118> B_WL<117> B_WL<116> B_WL<115> B_WL<114> B_WL<113> B_WL<112> B_WL<111> B_WL<110> B_WL<109> B_WL<108> B_WL<107> B_WL<106> B_WL<105> B_WL<104> B_WL<103> B_WL<102> B_WL<101> B_WL<100> B_WL<99> B_WL<98> B_WL<97> B_WL<96> B_WL<95> B_WL<94> B_WL<93> B_WL<92> B_WL<91> B_WL<90> B_WL<89> B_WL<88> B_WL<87> B_WL<86> B_WL<85> B_WL<84> B_WL<83> B_WL<82> B_WL<81> B_WL<80> B_WL<79> B_WL<78> B_WL<77> B_WL<76> B_WL<75> B_WL<74> B_WL<73> B_WL<72> B_WL<71> B_WL<70> B_WL<69> B_WL<68> B_WL<67> B_WL<66> B_WL<65> B_WL<64> B_WL<63> B_WL<62> B_WL<61> B_WL<60> B_WL<59> B_WL<58> B_WL<57> B_WL<56> B_WL<55> B_WL<54> B_WL<53> B_WL<52> B_WL<51> B_WL<50> B_WL<49> B_WL<48> B_WL<47> B_WL<46> B_WL<45> B_WL<44> B_WL<43> B_WL<42> B_WL<41> B_WL<40> B_WL<39> B_WL<38> B_WL<37> B_WL<36> B_WL<35> B_WL<34> B_WL<33> B_WL<32> B_WL<31> B_WL<30> B_WL<29> B_WL<28> B_WL<27> B_WL<26> B_WL<25> B_WL<24> B_WL<23> B_WL<22> B_WL<21> B_WL<20> B_WL<19> B_WL<18> B_WL<17> B_WL<16> B_WL<15> B_WL<14> B_WL<13> B_WL<12> B_WL<11> B_WL<10> B_WL<9> B_WL<8> B_WL<7> B_WL<6> B_WL<5> B_WL<4> B_WL<3> B_WL<2> B_WL<1> B_WL<0> B_IWL<255> B_IWL<254> B_IWL<253> B_IWL<252> B_IWL<251> B_IWL<250> B_IWL<249> B_IWL<248> B_IWL<247> B_IWL<246> B_IWL<245> B_IWL<244> B_IWL<243> B_IWL<242> B_IWL<241> B_IWL<240> B_IWL<239> B_IWL<238> B_IWL<237> B_IWL<236> B_IWL<235> B_IWL<234> B_IWL<233> B_IWL<232> B_IWL<231> B_IWL<230> B_IWL<229> B_IWL<228> B_IWL<227> B_IWL<226> B_IWL<225> B_IWL<224> B_IWL<223> B_IWL<222> B_IWL<221> B_IWL<220> B_IWL<219> B_IWL<218> B_IWL<217> B_IWL<216> B_IWL<215> B_IWL<214> B_IWL<213> B_IWL<212> B_IWL<211> B_IWL<210> B_IWL<209> B_IWL<208> B_IWL<207> B_IWL<206> B_IWL<205> B_IWL<204> B_IWL<203> B_IWL<202> B_IWL<201> B_IWL<200> B_IWL<199> B_IWL<198> B_IWL<197> B_IWL<196> B_IWL<195> B_IWL<194> B_IWL<193> B_IWL<192> B_IWL<191> B_IWL<190> B_IWL<189> B_IWL<188> B_IWL<187> B_IWL<186> B_IWL<185> B_IWL<184> B_IWL<183> B_IWL<182> B_IWL<181> B_IWL<180> B_IWL<179> B_IWL<178> B_IWL<177> B_IWL<176> B_IWL<175> B_IWL<174> B_IWL<173> B_IWL<172> B_IWL<171> B_IWL<170> B_IWL<169> B_IWL<168> B_IWL<167> B_IWL<166> B_IWL<165> B_IWL<164> B_IWL<163> B_IWL<162> B_IWL<161> B_IWL<160> B_IWL<159> B_IWL<158> B_IWL<157> B_IWL<156> B_IWL<155> B_IWL<154> B_IWL<153> B_IWL<152> B_IWL<151> B_IWL<150> B_IWL<149> B_IWL<148> B_IWL<147> B_IWL<146> B_IWL<145> B_IWL<144> B_IWL<143> B_IWL<142> B_IWL<141> B_IWL<140> B_IWL<139> B_IWL<138> B_IWL<137> B_IWL<136> B_IWL<135> B_IWL<134> B_IWL<133> B_IWL<132> B_IWL<131> B_IWL<130> B_IWL<129> B_IWL<128> B_IWL<127> B_IWL<126> B_IWL<125> B_IWL<124> B_IWL<123> B_IWL<122> B_IWL<121> B_IWL<120> B_IWL<119> B_IWL<118> B_IWL<117> B_IWL<116> B_IWL<115> B_IWL<114> B_IWL<113> B_IWL<112> B_IWL<111> B_IWL<110> B_IWL<109> B_IWL<108> B_IWL<107> B_IWL<106> B_IWL<105> B_IWL<104> B_IWL<103> B_IWL<102> B_IWL<101> B_IWL<100> B_IWL<99> B_IWL<98> B_IWL<97> B_IWL<96> B_IWL<95> B_IWL<94> B_IWL<93> B_IWL<92> B_IWL<91> B_IWL<90> B_IWL<89> B_IWL<88> B_IWL<87> B_IWL<86> B_IWL<85> B_IWL<84> B_IWL<83> B_IWL<82> B_IWL<81> B_IWL<80> B_IWL<79> B_IWL<78> B_IWL<77> B_IWL<76> B_IWL<75> B_IWL<74> B_IWL<73> B_IWL<72> B_IWL<71> B_IWL<70> B_IWL<69> B_IWL<68> B_IWL<67> B_IWL<66> B_IWL<65> B_IWL<64> B_IWL<63> B_IWL<62> B_IWL<61> B_IWL<60> B_IWL<59> B_IWL<58> B_IWL<57> B_IWL<56> B_IWL<55> B_IWL<54> B_IWL<53> B_IWL<52> B_IWL<51> B_IWL<50> B_IWL<49> B_IWL<48> B_IWL<47> B_IWL<46> B_IWL<45> B_IWL<44> B_IWL<43> B_IWL<42> B_IWL<41> B_IWL<40> B_IWL<39> B_IWL<38> B_IWL<37> B_IWL<36> B_IWL<35> B_IWL<34> B_IWL<33> B_IWL<32> B_IWL<31> B_IWL<30> B_IWL<29> B_IWL<28> B_IWL<27> B_IWL<26> B_IWL<25> B_IWL<24> B_IWL<23> B_IWL<22> B_IWL<21> B_IWL<20> B_IWL<19> B_IWL<18> B_IWL<17> B_IWL<16> B_IWL<15> B_IWL<14> B_IWL<13> B_IWL<12> B_IWL<11> B_IWL<10> B_IWL<9> B_IWL<8> B_IWL<7> B_IWL<6> B_IWL<5> B_IWL<4> B_IWL<3> B_IWL<2> B_IWL<1> B_IWL<0> VDD_CORE VSS / RM_IHPSG13_1024x32_c2_2P_COLUMN_pcell_0 +.ENDS + + + + +.SUBCKT RM_IHPSG13_1024x32_c2_2P_DLY_pcell_2 A Z VDD VSS + XIDL<2> D<9> Z VDD VSS / RSC_IHPSG13_CDLYX1 + XIDL<1> D<8> D<9> VDD VSS / RSC_IHPSG13_CDLYX1 + XIDM<8> D<7> D<8> VDD VSS / RSC_IHPSG13_CDLYX1_DUMMY + XIDM<7> D<6> D<7> VDD VSS / RSC_IHPSG13_CDLYX1_DUMMY + XIDM<6> D<5> D<6> VDD VSS / RSC_IHPSG13_CDLYX1_DUMMY + XIDM<5> D<4> D<5> VDD VSS / RSC_IHPSG13_CDLYX1_DUMMY + XIDM<4> D<3> D<4> VDD VSS / RSC_IHPSG13_CDLYX1_DUMMY + XIDM<3> D<2> D<3> VDD VSS / RSC_IHPSG13_CDLYX1_DUMMY + XIDM<2> D<1> D<2> VDD VSS / RSC_IHPSG13_CDLYX1_DUMMY + XIDM<1> A D<1> VDD VSS / RSC_IHPSG13_CDLYX1_DUMMY +.ENDS + + +.SUBCKT RM_IHPSG13_1024x32_c2_2P_DLY_pcell_3 A Z VDD VSS + XIDL<4> D<9> Z VDD VSS / RSC_IHPSG13_CDLYX1 + XIDL<3> D<8> D<9> VDD VSS / RSC_IHPSG13_CDLYX1 + XIDL<2> D<7> D<8> VDD VSS / RSC_IHPSG13_CDLYX1 + XIDL<1> D<6> D<7> VDD VSS / RSC_IHPSG13_CDLYX1 + XIDM<6> D<5> D<6> VDD VSS / RSC_IHPSG13_CDLYX1_DUMMY + XIDM<5> D<4> D<5> VDD VSS / RSC_IHPSG13_CDLYX1_DUMMY + XIDM<4> D<3> D<4> VDD VSS / RSC_IHPSG13_CDLYX1_DUMMY + XIDM<3> D<2> D<3> VDD VSS / RSC_IHPSG13_CDLYX1_DUMMY + XIDM<2> D<1> D<2> VDD VSS / RSC_IHPSG13_CDLYX1_DUMMY + XIDM<1> A D<1> VDD VSS / RSC_IHPSG13_CDLYX1_DUMMY +.ENDS + + + +.SUBCKT RM_IHPSG13_2P_1024x32_c2_bm_bist A_ADDR<9> A_ADDR<8> A_ADDR<7> A_ADDR<6> A_ADDR<5> A_ADDR<4> A_ADDR<3> A_ADDR<2> A_ADDR<1> A_ADDR<0> A_BIST_ADDR<9> A_BIST_ADDR<8> A_BIST_ADDR<7> A_BIST_ADDR<6> A_BIST_ADDR<5> A_BIST_ADDR<4> A_BIST_ADDR<3> A_BIST_ADDR<2> A_BIST_ADDR<1> A_BIST_ADDR<0> A_BIST_BM<31> A_BIST_BM<30> A_BIST_BM<29> A_BIST_BM<28> A_BIST_BM<27> A_BIST_BM<26> A_BIST_BM<25> A_BIST_BM<24> A_BIST_BM<23> A_BIST_BM<22> A_BIST_BM<21> A_BIST_BM<20> A_BIST_BM<19> A_BIST_BM<18> A_BIST_BM<17> A_BIST_BM<16> A_BIST_BM<15> A_BIST_BM<14> A_BIST_BM<13> A_BIST_BM<12> A_BIST_BM<11> A_BIST_BM<10> A_BIST_BM<9> A_BIST_BM<8> A_BIST_BM<7> A_BIST_BM<6> A_BIST_BM<5> A_BIST_BM<4> A_BIST_BM<3> A_BIST_BM<2> A_BIST_BM<1> A_BIST_BM<0> A_BIST_CLK A_BIST_DIN<31> A_BIST_DIN<30> A_BIST_DIN<29> A_BIST_DIN<28> A_BIST_DIN<27> A_BIST_DIN<26> A_BIST_DIN<25> A_BIST_DIN<24> A_BIST_DIN<23> A_BIST_DIN<22> A_BIST_DIN<21> A_BIST_DIN<20> A_BIST_DIN<19> A_BIST_DIN<18> A_BIST_DIN<17> A_BIST_DIN<16> A_BIST_DIN<15> A_BIST_DIN<14> A_BIST_DIN<13> A_BIST_DIN<12> A_BIST_DIN<11> A_BIST_DIN<10> A_BIST_DIN<9> A_BIST_DIN<8> A_BIST_DIN<7> A_BIST_DIN<6> A_BIST_DIN<5> A_BIST_DIN<4> A_BIST_DIN<3> A_BIST_DIN<2> A_BIST_DIN<1> A_BIST_DIN<0> A_BIST_EN A_BIST_MEN A_BIST_REN A_BIST_WEN A_BM<31> A_BM<30> A_BM<29> A_BM<28> A_BM<27> A_BM<26> A_BM<25> A_BM<24> A_BM<23> A_BM<22> A_BM<21> A_BM<20> A_BM<19> A_BM<18> A_BM<17> A_BM<16> A_BM<15> A_BM<14> A_BM<13> A_BM<12> A_BM<11> A_BM<10> A_BM<9> A_BM<8> A_BM<7> A_BM<6> A_BM<5> A_BM<4> A_BM<3> A_BM<2> A_BM<1> A_BM<0> A_CLK A_DIN<31> A_DIN<30> A_DIN<29> A_DIN<28> A_DIN<27> A_DIN<26> A_DIN<25> A_DIN<24> A_DIN<23> A_DIN<22> A_DIN<21> A_DIN<20> A_DIN<19> A_DIN<18> A_DIN<17> A_DIN<16> A_DIN<15> A_DIN<14> A_DIN<13> A_DIN<12> A_DIN<11> A_DIN<10> A_DIN<9> A_DIN<8> A_DIN<7> A_DIN<6> A_DIN<5> A_DIN<4> A_DIN<3> A_DIN<2> A_DIN<1> A_DIN<0> A_DLY A_DOUT<31> A_DOUT<30> A_DOUT<29> A_DOUT<28> A_DOUT<27> A_DOUT<26> A_DOUT<25> A_DOUT<24> A_DOUT<23> A_DOUT<22> A_DOUT<21> A_DOUT<20> A_DOUT<19> A_DOUT<18> A_DOUT<17> A_DOUT<16> A_DOUT<15> A_DOUT<14> A_DOUT<13> A_DOUT<12> A_DOUT<11> A_DOUT<10> A_DOUT<9> A_DOUT<8> A_DOUT<7> A_DOUT<6> A_DOUT<5> A_DOUT<4> A_DOUT<3> A_DOUT<2> A_DOUT<1> A_DOUT<0> A_MEN A_REN A_WEN B_ADDR<9> B_ADDR<8> B_ADDR<7> B_ADDR<6> B_ADDR<5> B_ADDR<4> B_ADDR<3> B_ADDR<2> B_ADDR<1> B_ADDR<0> B_BIST_ADDR<9> B_BIST_ADDR<8> B_BIST_ADDR<7> B_BIST_ADDR<6> B_BIST_ADDR<5> B_BIST_ADDR<4> B_BIST_ADDR<3> B_BIST_ADDR<2> B_BIST_ADDR<1> B_BIST_ADDR<0> B_BIST_BM<31> B_BIST_BM<30> B_BIST_BM<29> B_BIST_BM<28> B_BIST_BM<27> B_BIST_BM<26> B_BIST_BM<25> B_BIST_BM<24> B_BIST_BM<23> B_BIST_BM<22> B_BIST_BM<21> B_BIST_BM<20> B_BIST_BM<19> B_BIST_BM<18> B_BIST_BM<17> B_BIST_BM<16> B_BIST_BM<15> B_BIST_BM<14> B_BIST_BM<13> B_BIST_BM<12> B_BIST_BM<11> B_BIST_BM<10> B_BIST_BM<9> B_BIST_BM<8> B_BIST_BM<7> B_BIST_BM<6> B_BIST_BM<5> B_BIST_BM<4> B_BIST_BM<3> B_BIST_BM<2> B_BIST_BM<1> B_BIST_BM<0> B_BIST_CLK B_BIST_DIN<31> B_BIST_DIN<30> B_BIST_DIN<29> B_BIST_DIN<28> B_BIST_DIN<27> B_BIST_DIN<26> B_BIST_DIN<25> B_BIST_DIN<24> B_BIST_DIN<23> B_BIST_DIN<22> B_BIST_DIN<21> B_BIST_DIN<20> B_BIST_DIN<19> B_BIST_DIN<18> B_BIST_DIN<17> B_BIST_DIN<16> B_BIST_DIN<15> B_BIST_DIN<14> B_BIST_DIN<13> B_BIST_DIN<12> B_BIST_DIN<11> B_BIST_DIN<10> B_BIST_DIN<9> B_BIST_DIN<8> B_BIST_DIN<7> B_BIST_DIN<6> B_BIST_DIN<5> B_BIST_DIN<4> B_BIST_DIN<3> B_BIST_DIN<2> B_BIST_DIN<1> B_BIST_DIN<0> B_BIST_EN B_BIST_MEN B_BIST_REN B_BIST_WEN B_BM<31> B_BM<30> B_BM<29> B_BM<28> B_BM<27> B_BM<26> B_BM<25> B_BM<24> B_BM<23> B_BM<22> B_BM<21> B_BM<20> B_BM<19> B_BM<18> B_BM<17> B_BM<16> B_BM<15> B_BM<14> B_BM<13> B_BM<12> B_BM<11> B_BM<10> B_BM<9> B_BM<8> B_BM<7> B_BM<6> B_BM<5> B_BM<4> B_BM<3> B_BM<2> B_BM<1> B_BM<0> B_CLK B_DIN<31> B_DIN<30> B_DIN<29> B_DIN<28> B_DIN<27> B_DIN<26> B_DIN<25> B_DIN<24> B_DIN<23> B_DIN<22> B_DIN<21> B_DIN<20> B_DIN<19> B_DIN<18> B_DIN<17> B_DIN<16> B_DIN<15> B_DIN<14> B_DIN<13> B_DIN<12> B_DIN<11> B_DIN<10> B_DIN<9> B_DIN<8> B_DIN<7> B_DIN<6> B_DIN<5> B_DIN<4> B_DIN<3> B_DIN<2> B_DIN<1> B_DIN<0> B_DLY B_DOUT<31> B_DOUT<30> B_DOUT<29> B_DOUT<28> B_DOUT<27> B_DOUT<26> B_DOUT<25> B_DOUT<24> B_DOUT<23> B_DOUT<22> B_DOUT<21> B_DOUT<20> B_DOUT<19> B_DOUT<18> B_DOUT<17> B_DOUT<16> B_DOUT<15> B_DOUT<14> B_DOUT<13> B_DOUT<12> B_DOUT<11> B_DOUT<10> B_DOUT<9> B_DOUT<8> B_DOUT<7> B_DOUT<6> B_DOUT<5> B_DOUT<4> B_DOUT<3> B_DOUT<2> B_DOUT<1> B_DOUT<0> B_MEN B_REN B_WEN VDD! VDDARRAY! VSS! + + +XRAM<1> a_blc_r<63> a_blc_r<62> a_blc_r<61> a_blc_r<60> a_blc_r<59> a_blc_r<58> a_blc_r<57> a_blc_r<56> a_blc_r<55> a_blc_r<54> a_blc_r<53> a_blc_r<52> a_blc_r<51> a_blc_r<50> a_blc_r<49> a_blc_r<48> a_blc_r<47> a_blc_r<46> a_blc_r<45> a_blc_r<44> a_blc_r<43> a_blc_r<42> a_blc_r<41> a_blc_r<40> a_blc_r<39> a_blc_r<38> a_blc_r<37> a_blc_r<36> a_blc_r<35> a_blc_r<34> a_blc_r<33> a_blc_r<32> a_blc_r<31> a_blc_r<30> a_blc_r<29> a_blc_r<28> a_blc_r<27> a_blc_r<26> a_blc_r<25> a_blc_r<24> a_blc_r<23> a_blc_r<22> a_blc_r<21> a_blc_r<20> a_blc_r<19> a_blc_r<18> a_blc_r<17> a_blc_r<16> a_blc_r<15> a_blc_r<14> a_blc_r<13> a_blc_r<12> a_blc_r<11> a_blc_r<10> a_blc_r<9> a_blc_r<8> a_blc_r<7> a_blc_r<6> a_blc_r<5> a_blc_r<4> a_blc_r<3> a_blc_r<2> a_blc_r<1> a_blc_r<0> a_blt_r<63> a_blt_r<62> a_blt_r<61> a_blt_r<60> a_blt_r<59> a_blt_r<58> a_blt_r<57> a_blt_r<56> a_blt_r<55> a_blt_r<54> a_blt_r<53> a_blt_r<52> a_blt_r<51> a_blt_r<50> a_blt_r<49> a_blt_r<48> a_blt_r<47> a_blt_r<46> a_blt_r<45> a_blt_r<44> a_blt_r<43> a_blt_r<42> a_blt_r<41> a_blt_r<40> a_blt_r<39> a_blt_r<38> a_blt_r<37> a_blt_r<36> a_blt_r<35> a_blt_r<34> a_blt_r<33> a_blt_r<32> a_blt_r<31> a_blt_r<30> a_blt_r<29> a_blt_r<28> a_blt_r<27> a_blt_r<26> a_blt_r<25> a_blt_r<24> a_blt_r<23> a_blt_r<22> a_blt_r<21> a_blt_r<20> a_blt_r<19> a_blt_r<18> a_blt_r<17> a_blt_r<16> a_blt_r<15> a_blt_r<14> a_blt_r<13> a_blt_r<12> a_blt_r<11> a_blt_r<10> a_blt_r<9> a_blt_r<8> a_blt_r<7> a_blt_r<6> a_blt_r<5> a_blt_r<4> a_blt_r<3> a_blt_r<2> a_blt_r<1> a_blt_r<0> a_wl_r<255> a_wl_r<254> a_wl_r<253> a_wl_r<252> a_wl_r<251> a_wl_r<250> a_wl_r<249> a_wl_r<248> a_wl_r<247> a_wl_r<246> a_wl_r<245> a_wl_r<244> a_wl_r<243> a_wl_r<242> a_wl_r<241> a_wl_r<240> a_wl_r<239> a_wl_r<238> a_wl_r<237> a_wl_r<236> a_wl_r<235> a_wl_r<234> a_wl_r<233> a_wl_r<232> a_wl_r<231> a_wl_r<230> a_wl_r<229> a_wl_r<228> a_wl_r<227> a_wl_r<226> a_wl_r<225> a_wl_r<224> a_wl_r<223> a_wl_r<222> a_wl_r<221> a_wl_r<220> a_wl_r<219> a_wl_r<218> a_wl_r<217> a_wl_r<216> a_wl_r<215> a_wl_r<214> a_wl_r<213> a_wl_r<212> a_wl_r<211> a_wl_r<210> a_wl_r<209> a_wl_r<208> a_wl_r<207> a_wl_r<206> a_wl_r<205> a_wl_r<204> a_wl_r<203> a_wl_r<202> a_wl_r<201> a_wl_r<200> a_wl_r<199> a_wl_r<198> a_wl_r<197> a_wl_r<196> a_wl_r<195> a_wl_r<194> a_wl_r<193> a_wl_r<192> a_wl_r<191> a_wl_r<190> a_wl_r<189> a_wl_r<188> a_wl_r<187> a_wl_r<186> a_wl_r<185> a_wl_r<184> a_wl_r<183> a_wl_r<182> a_wl_r<181> a_wl_r<180> a_wl_r<179> a_wl_r<178> a_wl_r<177> a_wl_r<176> a_wl_r<175> a_wl_r<174> a_wl_r<173> a_wl_r<172> a_wl_r<171> a_wl_r<170> a_wl_r<169> a_wl_r<168> a_wl_r<167> a_wl_r<166> a_wl_r<165> a_wl_r<164> a_wl_r<163> a_wl_r<162> a_wl_r<161> a_wl_r<160> a_wl_r<159> a_wl_r<158> a_wl_r<157> a_wl_r<156> a_wl_r<155> a_wl_r<154> a_wl_r<153> a_wl_r<152> a_wl_r<151> a_wl_r<150> a_wl_r<149> a_wl_r<148> a_wl_r<147> a_wl_r<146> a_wl_r<145> a_wl_r<144> a_wl_r<143> a_wl_r<142> a_wl_r<141> a_wl_r<140> a_wl_r<139> a_wl_r<138> a_wl_r<137> a_wl_r<136> a_wl_r<135> a_wl_r<134> a_wl_r<133> a_wl_r<132> a_wl_r<131> a_wl_r<130> a_wl_r<129> a_wl_r<128> a_wl_r<127> a_wl_r<126> a_wl_r<125> a_wl_r<124> a_wl_r<123> a_wl_r<122> a_wl_r<121> a_wl_r<120> a_wl_r<119> a_wl_r<118> a_wl_r<117> a_wl_r<116> a_wl_r<115> a_wl_r<114> a_wl_r<113> a_wl_r<112> a_wl_r<111> a_wl_r<110> a_wl_r<109> a_wl_r<108> a_wl_r<107> a_wl_r<106> a_wl_r<105> a_wl_r<104> a_wl_r<103> a_wl_r<102> a_wl_r<101> a_wl_r<100> a_wl_r<99> a_wl_r<98> a_wl_r<97> a_wl_r<96> a_wl_r<95> a_wl_r<94> a_wl_r<93> a_wl_r<92> a_wl_r<91> a_wl_r<90> a_wl_r<89> a_wl_r<88> a_wl_r<87> a_wl_r<86> a_wl_r<85> a_wl_r<84> a_wl_r<83> a_wl_r<82> a_wl_r<81> a_wl_r<80> a_wl_r<79> a_wl_r<78> a_wl_r<77> a_wl_r<76> a_wl_r<75> a_wl_r<74> a_wl_r<73> a_wl_r<72> a_wl_r<71> a_wl_r<70> a_wl_r<69> a_wl_r<68> a_wl_r<67> a_wl_r<66> a_wl_r<65> a_wl_r<64> a_wl_r<63> a_wl_r<62> a_wl_r<61> a_wl_r<60> a_wl_r<59> a_wl_r<58> a_wl_r<57> a_wl_r<56> a_wl_r<55> a_wl_r<54> a_wl_r<53> a_wl_r<52> a_wl_r<51> a_wl_r<50> a_wl_r<49> a_wl_r<48> a_wl_r<47> a_wl_r<46> a_wl_r<45> a_wl_r<44> a_wl_r<43> a_wl_r<42> a_wl_r<41> a_wl_r<40> a_wl_r<39> a_wl_r<38> a_wl_r<37> a_wl_r<36> a_wl_r<35> a_wl_r<34> a_wl_r<33> a_wl_r<32> a_wl_r<31> a_wl_r<30> a_wl_r<29> a_wl_r<28> a_wl_r<27> a_wl_r<26> a_wl_r<25> a_wl_r<24> a_wl_r<23> a_wl_r<22> a_wl_r<21> a_wl_r<20> a_wl_r<19> a_wl_r<18> a_wl_r<17> a_wl_r<16> a_wl_r<15> a_wl_r<14> a_wl_r<13> a_wl_r<12> a_wl_r<11> a_wl_r<10> a_wl_r<9> a_wl_r<8> a_wl_r<7> a_wl_r<6> a_wl_r<5> a_wl_r<4> a_wl_r<3> a_wl_r<2> a_wl_r<1> a_wl_r<0> b_blc_r<63> b_blc_r<62> b_blc_r<61> b_blc_r<60> b_blc_r<59> b_blc_r<58> b_blc_r<57> b_blc_r<56> b_blc_r<55> b_blc_r<54> b_blc_r<53> b_blc_r<52> b_blc_r<51> b_blc_r<50> b_blc_r<49> b_blc_r<48> b_blc_r<47> b_blc_r<46> b_blc_r<45> b_blc_r<44> b_blc_r<43> b_blc_r<42> b_blc_r<41> b_blc_r<40> b_blc_r<39> b_blc_r<38> b_blc_r<37> b_blc_r<36> b_blc_r<35> b_blc_r<34> b_blc_r<33> b_blc_r<32> b_blc_r<31> b_blc_r<30> b_blc_r<29> b_blc_r<28> b_blc_r<27> b_blc_r<26> b_blc_r<25> b_blc_r<24> b_blc_r<23> b_blc_r<22> b_blc_r<21> b_blc_r<20> b_blc_r<19> b_blc_r<18> b_blc_r<17> b_blc_r<16> b_blc_r<15> b_blc_r<14> b_blc_r<13> b_blc_r<12> b_blc_r<11> b_blc_r<10> b_blc_r<9> b_blc_r<8> b_blc_r<7> b_blc_r<6> b_blc_r<5> b_blc_r<4> b_blc_r<3> b_blc_r<2> b_blc_r<1> b_blc_r<0> b_blt_r<63> b_blt_r<62> b_blt_r<61> b_blt_r<60> b_blt_r<59> b_blt_r<58> b_blt_r<57> b_blt_r<56> b_blt_r<55> b_blt_r<54> b_blt_r<53> b_blt_r<52> b_blt_r<51> b_blt_r<50> b_blt_r<49> b_blt_r<48> b_blt_r<47> b_blt_r<46> b_blt_r<45> b_blt_r<44> b_blt_r<43> b_blt_r<42> b_blt_r<41> b_blt_r<40> b_blt_r<39> b_blt_r<38> b_blt_r<37> b_blt_r<36> b_blt_r<35> b_blt_r<34> b_blt_r<33> b_blt_r<32> b_blt_r<31> b_blt_r<30> b_blt_r<29> b_blt_r<28> b_blt_r<27> b_blt_r<26> b_blt_r<25> b_blt_r<24> b_blt_r<23> b_blt_r<22> b_blt_r<21> b_blt_r<20> b_blt_r<19> b_blt_r<18> b_blt_r<17> b_blt_r<16> b_blt_r<15> b_blt_r<14> b_blt_r<13> b_blt_r<12> b_blt_r<11> b_blt_r<10> b_blt_r<9> b_blt_r<8> b_blt_r<7> b_blt_r<6> b_blt_r<5> b_blt_r<4> b_blt_r<3> b_blt_r<2> b_blt_r<1> b_blt_r<0> b_wl_r<255> b_wl_r<254> b_wl_r<253> b_wl_r<252> b_wl_r<251> b_wl_r<250> b_wl_r<249> b_wl_r<248> b_wl_r<247> b_wl_r<246> b_wl_r<245> b_wl_r<244> b_wl_r<243> b_wl_r<242> b_wl_r<241> b_wl_r<240> b_wl_r<239> b_wl_r<238> b_wl_r<237> b_wl_r<236> b_wl_r<235> b_wl_r<234> b_wl_r<233> b_wl_r<232> b_wl_r<231> b_wl_r<230> b_wl_r<229> b_wl_r<228> b_wl_r<227> b_wl_r<226> b_wl_r<225> b_wl_r<224> b_wl_r<223> b_wl_r<222> b_wl_r<221> b_wl_r<220> b_wl_r<219> b_wl_r<218> b_wl_r<217> b_wl_r<216> b_wl_r<215> b_wl_r<214> b_wl_r<213> b_wl_r<212> b_wl_r<211> b_wl_r<210> b_wl_r<209> b_wl_r<208> b_wl_r<207> b_wl_r<206> b_wl_r<205> b_wl_r<204> b_wl_r<203> b_wl_r<202> b_wl_r<201> b_wl_r<200> b_wl_r<199> b_wl_r<198> b_wl_r<197> b_wl_r<196> b_wl_r<195> b_wl_r<194> b_wl_r<193> b_wl_r<192> b_wl_r<191> b_wl_r<190> b_wl_r<189> b_wl_r<188> b_wl_r<187> b_wl_r<186> b_wl_r<185> b_wl_r<184> b_wl_r<183> b_wl_r<182> b_wl_r<181> b_wl_r<180> b_wl_r<179> b_wl_r<178> b_wl_r<177> b_wl_r<176> b_wl_r<175> b_wl_r<174> b_wl_r<173> b_wl_r<172> b_wl_r<171> b_wl_r<170> b_wl_r<169> b_wl_r<168> b_wl_r<167> b_wl_r<166> b_wl_r<165> b_wl_r<164> b_wl_r<163> b_wl_r<162> b_wl_r<161> b_wl_r<160> b_wl_r<159> b_wl_r<158> b_wl_r<157> b_wl_r<156> b_wl_r<155> b_wl_r<154> b_wl_r<153> b_wl_r<152> b_wl_r<151> b_wl_r<150> b_wl_r<149> b_wl_r<148> b_wl_r<147> b_wl_r<146> b_wl_r<145> b_wl_r<144> b_wl_r<143> b_wl_r<142> b_wl_r<141> b_wl_r<140> b_wl_r<139> b_wl_r<138> b_wl_r<137> b_wl_r<136> b_wl_r<135> b_wl_r<134> b_wl_r<133> b_wl_r<132> b_wl_r<131> b_wl_r<130> b_wl_r<129> b_wl_r<128> b_wl_r<127> b_wl_r<126> b_wl_r<125> b_wl_r<124> b_wl_r<123> b_wl_r<122> b_wl_r<121> b_wl_r<120> b_wl_r<119> b_wl_r<118> b_wl_r<117> b_wl_r<116> b_wl_r<115> b_wl_r<114> b_wl_r<113> b_wl_r<112> b_wl_r<111> b_wl_r<110> b_wl_r<109> b_wl_r<108> b_wl_r<107> b_wl_r<106> b_wl_r<105> b_wl_r<104> b_wl_r<103> b_wl_r<102> b_wl_r<101> b_wl_r<100> b_wl_r<99> b_wl_r<98> b_wl_r<97> b_wl_r<96> b_wl_r<95> b_wl_r<94> b_wl_r<93> b_wl_r<92> b_wl_r<91> b_wl_r<90> b_wl_r<89> b_wl_r<88> b_wl_r<87> b_wl_r<86> b_wl_r<85> b_wl_r<84> b_wl_r<83> b_wl_r<82> b_wl_r<81> b_wl_r<80> b_wl_r<79> b_wl_r<78> b_wl_r<77> b_wl_r<76> b_wl_r<75> b_wl_r<74> b_wl_r<73> b_wl_r<72> b_wl_r<71> b_wl_r<70> b_wl_r<69> b_wl_r<68> b_wl_r<67> b_wl_r<66> b_wl_r<65> b_wl_r<64> b_wl_r<63> b_wl_r<62> b_wl_r<61> b_wl_r<60> b_wl_r<59> b_wl_r<58> b_wl_r<57> b_wl_r<56> b_wl_r<55> b_wl_r<54> b_wl_r<53> b_wl_r<52> b_wl_r<51> b_wl_r<50> b_wl_r<49> b_wl_r<48> b_wl_r<47> b_wl_r<46> b_wl_r<45> b_wl_r<44> b_wl_r<43> b_wl_r<42> b_wl_r<41> b_wl_r<40> b_wl_r<39> b_wl_r<38> b_wl_r<37> b_wl_r<36> b_wl_r<35> b_wl_r<34> b_wl_r<33> b_wl_r<32> b_wl_r<31> b_wl_r<30> b_wl_r<29> b_wl_r<28> b_wl_r<27> b_wl_r<26> b_wl_r<25> b_wl_r<24> b_wl_r<23> b_wl_r<22> b_wl_r<21> b_wl_r<20> b_wl_r<19> b_wl_r<18> b_wl_r<17> b_wl_r<16> b_wl_r<15> b_wl_r<14> b_wl_r<13> b_wl_r<12> b_wl_r<11> b_wl_r<10> b_wl_r<9> b_wl_r<8> b_wl_r<7> b_wl_r<6> b_wl_r<5> b_wl_r<4> b_wl_r<3> b_wl_r<2> b_wl_r<1> b_wl_r<0> VDDARRAY! VSS! / RM_IHPSG13_1024x32_c2_2P_MATRIX_pcell_1 +XRAM<0> a_blc_l<63> a_blc_l<62> a_blc_l<61> a_blc_l<60> a_blc_l<59> a_blc_l<58> a_blc_l<57> a_blc_l<56> a_blc_l<55> a_blc_l<54> a_blc_l<53> a_blc_l<52> a_blc_l<51> a_blc_l<50> a_blc_l<49> a_blc_l<48> a_blc_l<47> a_blc_l<46> a_blc_l<45> a_blc_l<44> a_blc_l<43> a_blc_l<42> a_blc_l<41> a_blc_l<40> a_blc_l<39> a_blc_l<38> a_blc_l<37> a_blc_l<36> a_blc_l<35> a_blc_l<34> a_blc_l<33> a_blc_l<32> a_blc_l<31> a_blc_l<30> a_blc_l<29> a_blc_l<28> a_blc_l<27> a_blc_l<26> a_blc_l<25> a_blc_l<24> a_blc_l<23> a_blc_l<22> a_blc_l<21> a_blc_l<20> a_blc_l<19> a_blc_l<18> a_blc_l<17> a_blc_l<16> a_blc_l<15> a_blc_l<14> a_blc_l<13> a_blc_l<12> a_blc_l<11> a_blc_l<10> a_blc_l<9> a_blc_l<8> a_blc_l<7> a_blc_l<6> a_blc_l<5> a_blc_l<4> a_blc_l<3> a_blc_l<2> a_blc_l<1> a_blc_l<0> a_blt_l<63> a_blt_l<62> a_blt_l<61> a_blt_l<60> a_blt_l<59> a_blt_l<58> a_blt_l<57> a_blt_l<56> a_blt_l<55> a_blt_l<54> a_blt_l<53> a_blt_l<52> a_blt_l<51> a_blt_l<50> a_blt_l<49> a_blt_l<48> a_blt_l<47> a_blt_l<46> a_blt_l<45> a_blt_l<44> a_blt_l<43> a_blt_l<42> a_blt_l<41> a_blt_l<40> a_blt_l<39> a_blt_l<38> a_blt_l<37> a_blt_l<36> a_blt_l<35> a_blt_l<34> a_blt_l<33> a_blt_l<32> a_blt_l<31> a_blt_l<30> a_blt_l<29> a_blt_l<28> a_blt_l<27> a_blt_l<26> a_blt_l<25> a_blt_l<24> a_blt_l<23> a_blt_l<22> a_blt_l<21> a_blt_l<20> a_blt_l<19> a_blt_l<18> a_blt_l<17> a_blt_l<16> a_blt_l<15> a_blt_l<14> a_blt_l<13> a_blt_l<12> a_blt_l<11> a_blt_l<10> a_blt_l<9> a_blt_l<8> a_blt_l<7> a_blt_l<6> a_blt_l<5> a_blt_l<4> a_blt_l<3> a_blt_l<2> a_blt_l<1> a_blt_l<0> a_wl_l<255> a_wl_l<254> a_wl_l<253> a_wl_l<252> a_wl_l<251> a_wl_l<250> a_wl_l<249> a_wl_l<248> a_wl_l<247> a_wl_l<246> a_wl_l<245> a_wl_l<244> a_wl_l<243> a_wl_l<242> a_wl_l<241> a_wl_l<240> a_wl_l<239> a_wl_l<238> a_wl_l<237> a_wl_l<236> a_wl_l<235> a_wl_l<234> a_wl_l<233> a_wl_l<232> a_wl_l<231> a_wl_l<230> a_wl_l<229> a_wl_l<228> a_wl_l<227> a_wl_l<226> a_wl_l<225> a_wl_l<224> a_wl_l<223> a_wl_l<222> a_wl_l<221> a_wl_l<220> a_wl_l<219> a_wl_l<218> a_wl_l<217> a_wl_l<216> a_wl_l<215> a_wl_l<214> a_wl_l<213> a_wl_l<212> a_wl_l<211> a_wl_l<210> a_wl_l<209> a_wl_l<208> a_wl_l<207> a_wl_l<206> a_wl_l<205> a_wl_l<204> a_wl_l<203> a_wl_l<202> a_wl_l<201> a_wl_l<200> a_wl_l<199> a_wl_l<198> a_wl_l<197> a_wl_l<196> a_wl_l<195> a_wl_l<194> a_wl_l<193> a_wl_l<192> a_wl_l<191> a_wl_l<190> a_wl_l<189> a_wl_l<188> a_wl_l<187> a_wl_l<186> a_wl_l<185> a_wl_l<184> a_wl_l<183> a_wl_l<182> a_wl_l<181> a_wl_l<180> a_wl_l<179> a_wl_l<178> a_wl_l<177> a_wl_l<176> a_wl_l<175> a_wl_l<174> a_wl_l<173> a_wl_l<172> a_wl_l<171> a_wl_l<170> a_wl_l<169> a_wl_l<168> a_wl_l<167> a_wl_l<166> a_wl_l<165> a_wl_l<164> a_wl_l<163> a_wl_l<162> a_wl_l<161> a_wl_l<160> a_wl_l<159> a_wl_l<158> a_wl_l<157> a_wl_l<156> a_wl_l<155> a_wl_l<154> a_wl_l<153> a_wl_l<152> a_wl_l<151> a_wl_l<150> a_wl_l<149> a_wl_l<148> a_wl_l<147> a_wl_l<146> a_wl_l<145> a_wl_l<144> a_wl_l<143> a_wl_l<142> a_wl_l<141> a_wl_l<140> a_wl_l<139> a_wl_l<138> a_wl_l<137> a_wl_l<136> a_wl_l<135> a_wl_l<134> a_wl_l<133> a_wl_l<132> a_wl_l<131> a_wl_l<130> a_wl_l<129> a_wl_l<128> a_wl_l<127> a_wl_l<126> a_wl_l<125> a_wl_l<124> a_wl_l<123> a_wl_l<122> a_wl_l<121> a_wl_l<120> a_wl_l<119> a_wl_l<118> a_wl_l<117> a_wl_l<116> a_wl_l<115> a_wl_l<114> a_wl_l<113> a_wl_l<112> a_wl_l<111> a_wl_l<110> a_wl_l<109> a_wl_l<108> a_wl_l<107> a_wl_l<106> a_wl_l<105> a_wl_l<104> a_wl_l<103> a_wl_l<102> a_wl_l<101> a_wl_l<100> a_wl_l<99> a_wl_l<98> a_wl_l<97> a_wl_l<96> a_wl_l<95> a_wl_l<94> a_wl_l<93> a_wl_l<92> a_wl_l<91> a_wl_l<90> a_wl_l<89> a_wl_l<88> a_wl_l<87> a_wl_l<86> a_wl_l<85> a_wl_l<84> a_wl_l<83> a_wl_l<82> a_wl_l<81> a_wl_l<80> a_wl_l<79> a_wl_l<78> a_wl_l<77> a_wl_l<76> a_wl_l<75> a_wl_l<74> a_wl_l<73> a_wl_l<72> a_wl_l<71> a_wl_l<70> a_wl_l<69> a_wl_l<68> a_wl_l<67> a_wl_l<66> a_wl_l<65> a_wl_l<64> a_wl_l<63> a_wl_l<62> a_wl_l<61> a_wl_l<60> a_wl_l<59> a_wl_l<58> a_wl_l<57> a_wl_l<56> a_wl_l<55> a_wl_l<54> a_wl_l<53> a_wl_l<52> a_wl_l<51> a_wl_l<50> a_wl_l<49> a_wl_l<48> a_wl_l<47> a_wl_l<46> a_wl_l<45> a_wl_l<44> a_wl_l<43> a_wl_l<42> a_wl_l<41> a_wl_l<40> a_wl_l<39> a_wl_l<38> a_wl_l<37> a_wl_l<36> a_wl_l<35> a_wl_l<34> a_wl_l<33> a_wl_l<32> a_wl_l<31> a_wl_l<30> a_wl_l<29> a_wl_l<28> a_wl_l<27> a_wl_l<26> a_wl_l<25> a_wl_l<24> a_wl_l<23> a_wl_l<22> a_wl_l<21> a_wl_l<20> a_wl_l<19> a_wl_l<18> a_wl_l<17> a_wl_l<16> a_wl_l<15> a_wl_l<14> a_wl_l<13> a_wl_l<12> a_wl_l<11> a_wl_l<10> a_wl_l<9> a_wl_l<8> a_wl_l<7> a_wl_l<6> a_wl_l<5> a_wl_l<4> a_wl_l<3> a_wl_l<2> a_wl_l<1> a_wl_l<0> b_blc_l<63> b_blc_l<62> b_blc_l<61> b_blc_l<60> b_blc_l<59> b_blc_l<58> b_blc_l<57> b_blc_l<56> b_blc_l<55> b_blc_l<54> b_blc_l<53> b_blc_l<52> b_blc_l<51> b_blc_l<50> b_blc_l<49> b_blc_l<48> b_blc_l<47> b_blc_l<46> b_blc_l<45> b_blc_l<44> b_blc_l<43> b_blc_l<42> b_blc_l<41> b_blc_l<40> b_blc_l<39> b_blc_l<38> b_blc_l<37> b_blc_l<36> b_blc_l<35> b_blc_l<34> b_blc_l<33> b_blc_l<32> b_blc_l<31> b_blc_l<30> b_blc_l<29> b_blc_l<28> b_blc_l<27> b_blc_l<26> b_blc_l<25> b_blc_l<24> b_blc_l<23> b_blc_l<22> b_blc_l<21> b_blc_l<20> b_blc_l<19> b_blc_l<18> b_blc_l<17> b_blc_l<16> b_blc_l<15> b_blc_l<14> b_blc_l<13> b_blc_l<12> b_blc_l<11> b_blc_l<10> b_blc_l<9> b_blc_l<8> b_blc_l<7> b_blc_l<6> b_blc_l<5> b_blc_l<4> b_blc_l<3> b_blc_l<2> b_blc_l<1> b_blc_l<0> b_blt_l<63> b_blt_l<62> b_blt_l<61> b_blt_l<60> b_blt_l<59> b_blt_l<58> b_blt_l<57> b_blt_l<56> b_blt_l<55> b_blt_l<54> b_blt_l<53> b_blt_l<52> b_blt_l<51> b_blt_l<50> b_blt_l<49> b_blt_l<48> b_blt_l<47> b_blt_l<46> b_blt_l<45> b_blt_l<44> b_blt_l<43> b_blt_l<42> b_blt_l<41> b_blt_l<40> b_blt_l<39> b_blt_l<38> b_blt_l<37> b_blt_l<36> b_blt_l<35> b_blt_l<34> b_blt_l<33> b_blt_l<32> b_blt_l<31> b_blt_l<30> b_blt_l<29> b_blt_l<28> b_blt_l<27> b_blt_l<26> b_blt_l<25> b_blt_l<24> b_blt_l<23> b_blt_l<22> b_blt_l<21> b_blt_l<20> b_blt_l<19> b_blt_l<18> b_blt_l<17> b_blt_l<16> b_blt_l<15> b_blt_l<14> b_blt_l<13> b_blt_l<12> b_blt_l<11> b_blt_l<10> b_blt_l<9> b_blt_l<8> b_blt_l<7> b_blt_l<6> b_blt_l<5> b_blt_l<4> b_blt_l<3> b_blt_l<2> b_blt_l<1> b_blt_l<0> b_wl_l<255> b_wl_l<254> b_wl_l<253> b_wl_l<252> b_wl_l<251> b_wl_l<250> b_wl_l<249> b_wl_l<248> b_wl_l<247> b_wl_l<246> b_wl_l<245> b_wl_l<244> b_wl_l<243> b_wl_l<242> b_wl_l<241> b_wl_l<240> b_wl_l<239> b_wl_l<238> b_wl_l<237> b_wl_l<236> b_wl_l<235> b_wl_l<234> b_wl_l<233> b_wl_l<232> b_wl_l<231> b_wl_l<230> b_wl_l<229> b_wl_l<228> b_wl_l<227> b_wl_l<226> b_wl_l<225> b_wl_l<224> b_wl_l<223> b_wl_l<222> b_wl_l<221> b_wl_l<220> b_wl_l<219> b_wl_l<218> b_wl_l<217> b_wl_l<216> b_wl_l<215> b_wl_l<214> b_wl_l<213> b_wl_l<212> b_wl_l<211> b_wl_l<210> b_wl_l<209> b_wl_l<208> b_wl_l<207> b_wl_l<206> b_wl_l<205> b_wl_l<204> b_wl_l<203> b_wl_l<202> b_wl_l<201> b_wl_l<200> b_wl_l<199> b_wl_l<198> b_wl_l<197> b_wl_l<196> b_wl_l<195> b_wl_l<194> b_wl_l<193> b_wl_l<192> b_wl_l<191> b_wl_l<190> b_wl_l<189> b_wl_l<188> b_wl_l<187> b_wl_l<186> b_wl_l<185> b_wl_l<184> b_wl_l<183> b_wl_l<182> b_wl_l<181> b_wl_l<180> b_wl_l<179> b_wl_l<178> b_wl_l<177> b_wl_l<176> b_wl_l<175> b_wl_l<174> b_wl_l<173> b_wl_l<172> b_wl_l<171> b_wl_l<170> b_wl_l<169> b_wl_l<168> b_wl_l<167> b_wl_l<166> b_wl_l<165> b_wl_l<164> b_wl_l<163> b_wl_l<162> b_wl_l<161> b_wl_l<160> b_wl_l<159> b_wl_l<158> b_wl_l<157> b_wl_l<156> b_wl_l<155> b_wl_l<154> b_wl_l<153> b_wl_l<152> b_wl_l<151> b_wl_l<150> b_wl_l<149> b_wl_l<148> b_wl_l<147> b_wl_l<146> b_wl_l<145> b_wl_l<144> b_wl_l<143> b_wl_l<142> b_wl_l<141> b_wl_l<140> b_wl_l<139> b_wl_l<138> b_wl_l<137> b_wl_l<136> b_wl_l<135> b_wl_l<134> b_wl_l<133> b_wl_l<132> b_wl_l<131> b_wl_l<130> b_wl_l<129> b_wl_l<128> b_wl_l<127> b_wl_l<126> b_wl_l<125> b_wl_l<124> b_wl_l<123> b_wl_l<122> b_wl_l<121> b_wl_l<120> b_wl_l<119> b_wl_l<118> b_wl_l<117> b_wl_l<116> b_wl_l<115> b_wl_l<114> b_wl_l<113> b_wl_l<112> b_wl_l<111> b_wl_l<110> b_wl_l<109> b_wl_l<108> b_wl_l<107> b_wl_l<106> b_wl_l<105> b_wl_l<104> b_wl_l<103> b_wl_l<102> b_wl_l<101> b_wl_l<100> b_wl_l<99> b_wl_l<98> b_wl_l<97> b_wl_l<96> b_wl_l<95> b_wl_l<94> b_wl_l<93> b_wl_l<92> b_wl_l<91> b_wl_l<90> b_wl_l<89> b_wl_l<88> b_wl_l<87> b_wl_l<86> b_wl_l<85> b_wl_l<84> b_wl_l<83> b_wl_l<82> b_wl_l<81> b_wl_l<80> b_wl_l<79> b_wl_l<78> b_wl_l<77> b_wl_l<76> b_wl_l<75> b_wl_l<74> b_wl_l<73> b_wl_l<72> b_wl_l<71> b_wl_l<70> b_wl_l<69> b_wl_l<68> b_wl_l<67> b_wl_l<66> b_wl_l<65> b_wl_l<64> b_wl_l<63> b_wl_l<62> b_wl_l<61> b_wl_l<60> b_wl_l<59> b_wl_l<58> b_wl_l<57> b_wl_l<56> b_wl_l<55> b_wl_l<54> b_wl_l<53> b_wl_l<52> b_wl_l<51> b_wl_l<50> b_wl_l<49> b_wl_l<48> b_wl_l<47> b_wl_l<46> b_wl_l<45> b_wl_l<44> b_wl_l<43> b_wl_l<42> b_wl_l<41> b_wl_l<40> b_wl_l<39> b_wl_l<38> b_wl_l<37> b_wl_l<36> b_wl_l<35> b_wl_l<34> b_wl_l<33> b_wl_l<32> b_wl_l<31> b_wl_l<30> b_wl_l<29> b_wl_l<28> b_wl_l<27> b_wl_l<26> b_wl_l<25> b_wl_l<24> b_wl_l<23> b_wl_l<22> b_wl_l<21> b_wl_l<20> b_wl_l<19> b_wl_l<18> b_wl_l<17> b_wl_l<16> b_wl_l<15> b_wl_l<14> b_wl_l<13> b_wl_l<12> b_wl_l<11> b_wl_l<10> b_wl_l<9> b_wl_l<8> b_wl_l<7> b_wl_l<6> b_wl_l<5> b_wl_l<4> b_wl_l<3> b_wl_l<2> b_wl_l<1> b_wl_l<0> VDDARRAY! VSS! / RM_IHPSG13_1024x32_c2_2P_MATRIX_pcell_1 + + +XB_COLDRV<1> b_addr_col<1> b_addr_col<0> b_addr_col_r<1> b_addr_col_r<0> b_addr_dec<7> b_addr_dec<6> b_addr_dec<5> b_addr_dec<4> b_addr_dec<3> b_addr_dec<2> b_addr_dec<1> b_addr_dec<0> b_addr_dec_r<7> b_addr_dec_r<6> b_addr_dec_r<5> b_addr_dec_r<4> b_addr_dec_r<3> b_addr_dec_r<2> b_addr_dec_r<1> b_addr_dec_r<0> b_dclk b_dclk_p_r<0> b_rclk b_rclk_p_r<0> b_wclk b_wclk_p_r<0> VDD! VSS! / RM_IHPSG13_1024x32_c2_2P_COLDRV13X4 +XB_COLDRV<0> b_addr_col<1> b_addr_col<0> b_addr_col_l<1> b_addr_col_l<0> b_addr_dec<7> b_addr_dec<6> b_addr_dec<5> b_addr_dec<4> b_addr_dec<3> b_addr_dec<2> b_addr_dec<1> b_addr_dec<0> b_addr_dec_l<7> b_addr_dec_l<6> b_addr_dec_l<5> b_addr_dec_l<4> b_addr_dec_l<3> b_addr_dec_l<2> b_addr_dec_l<1> b_addr_dec_l<0> b_dclk b_dclk_p_l<0> b_rclk b_rclk_p_l<0> b_wclk b_wclk_p_l<0> VDD! VSS! / RM_IHPSG13_1024x32_c2_2P_COLDRV13X4 +XA_COLDRV<1> a_addr_col<1> a_addr_col<0> a_addr_col_r<1> a_addr_col_r<0> a_addr_dec<7> a_addr_dec<6> a_addr_dec<5> a_addr_dec<4> a_addr_dec<3> a_addr_dec<2> a_addr_dec<1> a_addr_dec<0> a_addr_dec_r<7> a_addr_dec_r<6> a_addr_dec_r<5> a_addr_dec_r<4> a_addr_dec_r<3> a_addr_dec_r<2> a_addr_dec_r<1> a_addr_dec_r<0> a_dclk a_dclk_p_r<0> a_rclk a_rclk_p_r<0> a_wclk a_wclk_p_r<0> VDD! VSS! / RM_IHPSG13_1024x32_c2_2P_COLDRV13X4 +XA_COLDRV<0> a_addr_col<1> a_addr_col<0> a_addr_col_l<1> a_addr_col_l<0> a_addr_dec<7> a_addr_dec<6> a_addr_dec<5> a_addr_dec<4> a_addr_dec<3> a_addr_dec<2> a_addr_dec<1> a_addr_dec<0> a_addr_dec_l<7> a_addr_dec_l<6> a_addr_dec_l<5> a_addr_dec_l<4> a_addr_dec_l<3> a_addr_dec_l<2> a_addr_dec_l<1> a_addr_dec_l<0> a_dclk a_dclk_p_l<0> a_rclk a_rclk_p_l<0> a_wclk a_wclk_p_l<0> VDD! VSS! / RM_IHPSG13_1024x32_c2_2P_COLDRV13X4 + + +XB_WLDRV<31> b_wi<255> b_wi<254> b_wi<253> b_wi<252> b_wi<251> b_wi<250> b_wi<249> b_wi<248> b_wi<247> b_wi<246> b_wi<245> b_wi<244> b_wi<243> b_wi<242> b_wi<241> b_wi<240> b_wl_r<255> b_wl_r<254> b_wl_r<253> b_wl_r<252> b_wl_r<251> b_wl_r<250> b_wl_r<249> b_wl_r<248> b_wl_r<247> b_wl_r<246> b_wl_r<245> b_wl_r<244> b_wl_r<243> b_wl_r<242> b_wl_r<241> b_wl_r<240> VDD! VSS! / RM_IHPSG13_1024x32_c2_2P_WLDRV16X4 +XB_WLDRV<30> b_wi<239> b_wi<238> b_wi<237> b_wi<236> b_wi<235> b_wi<234> b_wi<233> b_wi<232> b_wi<231> b_wi<230> b_wi<229> b_wi<228> b_wi<227> b_wi<226> b_wi<225> b_wi<224> b_wl_r<239> b_wl_r<238> b_wl_r<237> b_wl_r<236> b_wl_r<235> b_wl_r<234> b_wl_r<233> b_wl_r<232> b_wl_r<231> b_wl_r<230> b_wl_r<229> b_wl_r<228> b_wl_r<227> b_wl_r<226> b_wl_r<225> b_wl_r<224> VDD! VSS! / RM_IHPSG13_1024x32_c2_2P_WLDRV16X4 +XB_WLDRV<29> b_wi<223> b_wi<222> b_wi<221> b_wi<220> b_wi<219> b_wi<218> b_wi<217> b_wi<216> b_wi<215> b_wi<214> b_wi<213> b_wi<212> b_wi<211> b_wi<210> b_wi<209> b_wi<208> b_wl_r<223> b_wl_r<222> b_wl_r<221> b_wl_r<220> b_wl_r<219> b_wl_r<218> b_wl_r<217> b_wl_r<216> b_wl_r<215> b_wl_r<214> b_wl_r<213> b_wl_r<212> b_wl_r<211> b_wl_r<210> b_wl_r<209> b_wl_r<208> VDD! VSS! / RM_IHPSG13_1024x32_c2_2P_WLDRV16X4 +XB_WLDRV<28> b_wi<207> b_wi<206> b_wi<205> b_wi<204> b_wi<203> b_wi<202> b_wi<201> b_wi<200> b_wi<199> b_wi<198> b_wi<197> b_wi<196> b_wi<195> b_wi<194> b_wi<193> b_wi<192> b_wl_r<207> b_wl_r<206> b_wl_r<205> b_wl_r<204> b_wl_r<203> b_wl_r<202> b_wl_r<201> b_wl_r<200> b_wl_r<199> b_wl_r<198> b_wl_r<197> b_wl_r<196> b_wl_r<195> b_wl_r<194> b_wl_r<193> b_wl_r<192> VDD! VSS! / RM_IHPSG13_1024x32_c2_2P_WLDRV16X4 +XB_WLDRV<27> b_wi<191> b_wi<190> b_wi<189> b_wi<188> b_wi<187> b_wi<186> b_wi<185> b_wi<184> b_wi<183> b_wi<182> b_wi<181> b_wi<180> b_wi<179> b_wi<178> b_wi<177> b_wi<176> b_wl_r<191> b_wl_r<190> b_wl_r<189> b_wl_r<188> b_wl_r<187> b_wl_r<186> b_wl_r<185> b_wl_r<184> b_wl_r<183> b_wl_r<182> b_wl_r<181> b_wl_r<180> b_wl_r<179> b_wl_r<178> b_wl_r<177> b_wl_r<176> VDD! VSS! / RM_IHPSG13_1024x32_c2_2P_WLDRV16X4 +XB_WLDRV<26> b_wi<175> b_wi<174> b_wi<173> b_wi<172> b_wi<171> b_wi<170> b_wi<169> b_wi<168> b_wi<167> b_wi<166> b_wi<165> b_wi<164> b_wi<163> b_wi<162> b_wi<161> b_wi<160> b_wl_r<175> b_wl_r<174> b_wl_r<173> b_wl_r<172> b_wl_r<171> b_wl_r<170> b_wl_r<169> b_wl_r<168> b_wl_r<167> b_wl_r<166> b_wl_r<165> b_wl_r<164> b_wl_r<163> b_wl_r<162> b_wl_r<161> b_wl_r<160> VDD! VSS! / RM_IHPSG13_1024x32_c2_2P_WLDRV16X4 +XB_WLDRV<25> b_wi<159> b_wi<158> b_wi<157> b_wi<156> b_wi<155> b_wi<154> b_wi<153> b_wi<152> b_wi<151> b_wi<150> b_wi<149> b_wi<148> b_wi<147> b_wi<146> b_wi<145> b_wi<144> b_wl_r<159> b_wl_r<158> b_wl_r<157> b_wl_r<156> b_wl_r<155> b_wl_r<154> b_wl_r<153> b_wl_r<152> b_wl_r<151> b_wl_r<150> b_wl_r<149> b_wl_r<148> b_wl_r<147> b_wl_r<146> b_wl_r<145> b_wl_r<144> VDD! VSS! / RM_IHPSG13_1024x32_c2_2P_WLDRV16X4 +XB_WLDRV<24> b_wi<143> b_wi<142> b_wi<141> b_wi<140> b_wi<139> b_wi<138> b_wi<137> b_wi<136> b_wi<135> b_wi<134> b_wi<133> b_wi<132> b_wi<131> b_wi<130> b_wi<129> b_wi<128> b_wl_r<143> b_wl_r<142> b_wl_r<141> b_wl_r<140> b_wl_r<139> b_wl_r<138> b_wl_r<137> b_wl_r<136> b_wl_r<135> b_wl_r<134> b_wl_r<133> b_wl_r<132> b_wl_r<131> b_wl_r<130> b_wl_r<129> b_wl_r<128> VDD! VSS! / RM_IHPSG13_1024x32_c2_2P_WLDRV16X4 +XB_WLDRV<23> b_wi<127> b_wi<126> b_wi<125> b_wi<124> b_wi<123> b_wi<122> b_wi<121> b_wi<120> b_wi<119> b_wi<118> b_wi<117> b_wi<116> b_wi<115> b_wi<114> b_wi<113> b_wi<112> b_wl_r<127> b_wl_r<126> b_wl_r<125> b_wl_r<124> b_wl_r<123> b_wl_r<122> b_wl_r<121> b_wl_r<120> b_wl_r<119> b_wl_r<118> b_wl_r<117> b_wl_r<116> b_wl_r<115> b_wl_r<114> b_wl_r<113> b_wl_r<112> VDD! VSS! / RM_IHPSG13_1024x32_c2_2P_WLDRV16X4 +XB_WLDRV<22> b_wi<111> b_wi<110> b_wi<109> b_wi<108> b_wi<107> b_wi<106> b_wi<105> b_wi<104> b_wi<103> b_wi<102> b_wi<101> b_wi<100> b_wi<99> b_wi<98> b_wi<97> b_wi<96> b_wl_r<111> b_wl_r<110> b_wl_r<109> b_wl_r<108> b_wl_r<107> b_wl_r<106> b_wl_r<105> b_wl_r<104> b_wl_r<103> b_wl_r<102> b_wl_r<101> b_wl_r<100> b_wl_r<99> b_wl_r<98> b_wl_r<97> b_wl_r<96> VDD! VSS! / RM_IHPSG13_1024x32_c2_2P_WLDRV16X4 +XB_WLDRV<21> b_wi<95> b_wi<94> b_wi<93> b_wi<92> b_wi<91> b_wi<90> b_wi<89> b_wi<88> b_wi<87> b_wi<86> b_wi<85> b_wi<84> b_wi<83> b_wi<82> b_wi<81> b_wi<80> b_wl_r<95> b_wl_r<94> b_wl_r<93> b_wl_r<92> b_wl_r<91> b_wl_r<90> b_wl_r<89> b_wl_r<88> b_wl_r<87> b_wl_r<86> b_wl_r<85> b_wl_r<84> b_wl_r<83> b_wl_r<82> b_wl_r<81> b_wl_r<80> VDD! VSS! / RM_IHPSG13_1024x32_c2_2P_WLDRV16X4 +XB_WLDRV<20> b_wi<79> b_wi<78> b_wi<77> b_wi<76> b_wi<75> b_wi<74> b_wi<73> b_wi<72> b_wi<71> b_wi<70> b_wi<69> b_wi<68> b_wi<67> b_wi<66> b_wi<65> b_wi<64> b_wl_r<79> b_wl_r<78> b_wl_r<77> b_wl_r<76> b_wl_r<75> b_wl_r<74> b_wl_r<73> b_wl_r<72> b_wl_r<71> b_wl_r<70> b_wl_r<69> b_wl_r<68> b_wl_r<67> b_wl_r<66> b_wl_r<65> b_wl_r<64> VDD! VSS! / RM_IHPSG13_1024x32_c2_2P_WLDRV16X4 +XB_WLDRV<19> b_wi<63> b_wi<62> b_wi<61> b_wi<60> b_wi<59> b_wi<58> b_wi<57> b_wi<56> b_wi<55> b_wi<54> b_wi<53> b_wi<52> b_wi<51> b_wi<50> b_wi<49> b_wi<48> b_wl_r<63> b_wl_r<62> b_wl_r<61> b_wl_r<60> b_wl_r<59> b_wl_r<58> b_wl_r<57> b_wl_r<56> b_wl_r<55> b_wl_r<54> b_wl_r<53> b_wl_r<52> b_wl_r<51> b_wl_r<50> b_wl_r<49> b_wl_r<48> VDD! VSS! / RM_IHPSG13_1024x32_c2_2P_WLDRV16X4 +XB_WLDRV<18> b_wi<47> b_wi<46> b_wi<45> b_wi<44> b_wi<43> b_wi<42> b_wi<41> b_wi<40> b_wi<39> b_wi<38> b_wi<37> b_wi<36> b_wi<35> b_wi<34> b_wi<33> b_wi<32> b_wl_r<47> b_wl_r<46> b_wl_r<45> b_wl_r<44> b_wl_r<43> b_wl_r<42> b_wl_r<41> b_wl_r<40> b_wl_r<39> b_wl_r<38> b_wl_r<37> b_wl_r<36> b_wl_r<35> b_wl_r<34> b_wl_r<33> b_wl_r<32> VDD! VSS! / RM_IHPSG13_1024x32_c2_2P_WLDRV16X4 +XB_WLDRV<17> b_wi<31> b_wi<30> b_wi<29> b_wi<28> b_wi<27> b_wi<26> b_wi<25> b_wi<24> b_wi<23> b_wi<22> b_wi<21> b_wi<20> b_wi<19> b_wi<18> b_wi<17> b_wi<16> b_wl_r<31> b_wl_r<30> b_wl_r<29> b_wl_r<28> b_wl_r<27> b_wl_r<26> b_wl_r<25> b_wl_r<24> b_wl_r<23> b_wl_r<22> b_wl_r<21> b_wl_r<20> b_wl_r<19> b_wl_r<18> b_wl_r<17> b_wl_r<16> VDD! VSS! / RM_IHPSG13_1024x32_c2_2P_WLDRV16X4 +XB_WLDRV<16> b_wi<15> b_wi<14> b_wi<13> b_wi<12> b_wi<11> b_wi<10> b_wi<9> b_wi<8> b_wi<7> b_wi<6> b_wi<5> b_wi<4> b_wi<3> b_wi<2> b_wi<1> b_wi<0> b_wl_r<15> b_wl_r<14> b_wl_r<13> b_wl_r<12> b_wl_r<11> b_wl_r<10> b_wl_r<9> b_wl_r<8> b_wl_r<7> b_wl_r<6> b_wl_r<5> b_wl_r<4> b_wl_r<3> b_wl_r<2> b_wl_r<1> b_wl_r<0> VDD! VSS! / RM_IHPSG13_1024x32_c2_2P_WLDRV16X4 +XB_WLDRV<15> b_wi<255> b_wi<254> b_wi<253> b_wi<252> b_wi<251> b_wi<250> b_wi<249> b_wi<248> b_wi<247> b_wi<246> b_wi<245> b_wi<244> b_wi<243> b_wi<242> b_wi<241> b_wi<240> b_wl_l<255> b_wl_l<254> b_wl_l<253> b_wl_l<252> b_wl_l<251> b_wl_l<250> b_wl_l<249> b_wl_l<248> b_wl_l<247> b_wl_l<246> b_wl_l<245> b_wl_l<244> b_wl_l<243> b_wl_l<242> b_wl_l<241> b_wl_l<240> VDD! VSS! / RM_IHPSG13_1024x32_c2_2P_WLDRV16X4 +XB_WLDRV<14> b_wi<239> b_wi<238> b_wi<237> b_wi<236> b_wi<235> b_wi<234> b_wi<233> b_wi<232> b_wi<231> b_wi<230> b_wi<229> b_wi<228> b_wi<227> b_wi<226> b_wi<225> b_wi<224> b_wl_l<239> b_wl_l<238> b_wl_l<237> b_wl_l<236> b_wl_l<235> b_wl_l<234> b_wl_l<233> b_wl_l<232> b_wl_l<231> b_wl_l<230> b_wl_l<229> b_wl_l<228> b_wl_l<227> b_wl_l<226> b_wl_l<225> b_wl_l<224> VDD! VSS! / RM_IHPSG13_1024x32_c2_2P_WLDRV16X4 +XB_WLDRV<13> b_wi<223> b_wi<222> b_wi<221> b_wi<220> b_wi<219> b_wi<218> b_wi<217> b_wi<216> b_wi<215> b_wi<214> b_wi<213> b_wi<212> b_wi<211> b_wi<210> b_wi<209> b_wi<208> b_wl_l<223> b_wl_l<222> b_wl_l<221> b_wl_l<220> b_wl_l<219> b_wl_l<218> b_wl_l<217> b_wl_l<216> b_wl_l<215> b_wl_l<214> b_wl_l<213> b_wl_l<212> b_wl_l<211> b_wl_l<210> b_wl_l<209> b_wl_l<208> VDD! VSS! / RM_IHPSG13_1024x32_c2_2P_WLDRV16X4 +XB_WLDRV<12> b_wi<207> b_wi<206> b_wi<205> b_wi<204> b_wi<203> b_wi<202> b_wi<201> b_wi<200> b_wi<199> b_wi<198> b_wi<197> b_wi<196> b_wi<195> b_wi<194> b_wi<193> b_wi<192> b_wl_l<207> b_wl_l<206> b_wl_l<205> b_wl_l<204> b_wl_l<203> b_wl_l<202> b_wl_l<201> b_wl_l<200> b_wl_l<199> b_wl_l<198> b_wl_l<197> b_wl_l<196> b_wl_l<195> b_wl_l<194> b_wl_l<193> b_wl_l<192> VDD! VSS! / RM_IHPSG13_1024x32_c2_2P_WLDRV16X4 +XB_WLDRV<11> b_wi<191> b_wi<190> b_wi<189> b_wi<188> b_wi<187> b_wi<186> b_wi<185> b_wi<184> b_wi<183> b_wi<182> b_wi<181> b_wi<180> b_wi<179> b_wi<178> b_wi<177> b_wi<176> b_wl_l<191> b_wl_l<190> b_wl_l<189> b_wl_l<188> b_wl_l<187> b_wl_l<186> b_wl_l<185> b_wl_l<184> b_wl_l<183> b_wl_l<182> b_wl_l<181> b_wl_l<180> b_wl_l<179> b_wl_l<178> b_wl_l<177> b_wl_l<176> VDD! VSS! / RM_IHPSG13_1024x32_c2_2P_WLDRV16X4 +XB_WLDRV<10> b_wi<175> b_wi<174> b_wi<173> b_wi<172> b_wi<171> b_wi<170> b_wi<169> b_wi<168> b_wi<167> b_wi<166> b_wi<165> b_wi<164> b_wi<163> b_wi<162> b_wi<161> b_wi<160> b_wl_l<175> b_wl_l<174> b_wl_l<173> b_wl_l<172> b_wl_l<171> b_wl_l<170> b_wl_l<169> b_wl_l<168> b_wl_l<167> b_wl_l<166> b_wl_l<165> b_wl_l<164> b_wl_l<163> b_wl_l<162> b_wl_l<161> b_wl_l<160> VDD! VSS! / RM_IHPSG13_1024x32_c2_2P_WLDRV16X4 +XB_WLDRV<9> b_wi<159> b_wi<158> b_wi<157> b_wi<156> b_wi<155> b_wi<154> b_wi<153> b_wi<152> b_wi<151> b_wi<150> b_wi<149> b_wi<148> b_wi<147> b_wi<146> b_wi<145> b_wi<144> b_wl_l<159> b_wl_l<158> b_wl_l<157> b_wl_l<156> b_wl_l<155> b_wl_l<154> b_wl_l<153> b_wl_l<152> b_wl_l<151> b_wl_l<150> b_wl_l<149> b_wl_l<148> b_wl_l<147> b_wl_l<146> b_wl_l<145> b_wl_l<144> VDD! VSS! / RM_IHPSG13_1024x32_c2_2P_WLDRV16X4 +XB_WLDRV<8> b_wi<143> b_wi<142> b_wi<141> b_wi<140> b_wi<139> b_wi<138> b_wi<137> b_wi<136> b_wi<135> b_wi<134> b_wi<133> b_wi<132> b_wi<131> b_wi<130> b_wi<129> b_wi<128> b_wl_l<143> b_wl_l<142> b_wl_l<141> b_wl_l<140> b_wl_l<139> b_wl_l<138> b_wl_l<137> b_wl_l<136> b_wl_l<135> b_wl_l<134> b_wl_l<133> b_wl_l<132> b_wl_l<131> b_wl_l<130> b_wl_l<129> b_wl_l<128> VDD! VSS! / RM_IHPSG13_1024x32_c2_2P_WLDRV16X4 +XB_WLDRV<7> b_wi<127> b_wi<126> b_wi<125> b_wi<124> b_wi<123> b_wi<122> b_wi<121> b_wi<120> b_wi<119> b_wi<118> b_wi<117> b_wi<116> b_wi<115> b_wi<114> b_wi<113> b_wi<112> b_wl_l<127> b_wl_l<126> b_wl_l<125> b_wl_l<124> b_wl_l<123> b_wl_l<122> b_wl_l<121> b_wl_l<120> b_wl_l<119> b_wl_l<118> b_wl_l<117> b_wl_l<116> b_wl_l<115> b_wl_l<114> b_wl_l<113> b_wl_l<112> VDD! VSS! / RM_IHPSG13_1024x32_c2_2P_WLDRV16X4 +XB_WLDRV<6> b_wi<111> b_wi<110> b_wi<109> b_wi<108> b_wi<107> b_wi<106> b_wi<105> b_wi<104> b_wi<103> b_wi<102> b_wi<101> b_wi<100> b_wi<99> b_wi<98> b_wi<97> b_wi<96> b_wl_l<111> b_wl_l<110> b_wl_l<109> b_wl_l<108> b_wl_l<107> b_wl_l<106> b_wl_l<105> b_wl_l<104> b_wl_l<103> b_wl_l<102> b_wl_l<101> b_wl_l<100> b_wl_l<99> b_wl_l<98> b_wl_l<97> b_wl_l<96> VDD! VSS! / RM_IHPSG13_1024x32_c2_2P_WLDRV16X4 +XB_WLDRV<5> b_wi<95> b_wi<94> b_wi<93> b_wi<92> b_wi<91> b_wi<90> b_wi<89> b_wi<88> b_wi<87> b_wi<86> b_wi<85> b_wi<84> b_wi<83> b_wi<82> b_wi<81> b_wi<80> b_wl_l<95> b_wl_l<94> b_wl_l<93> b_wl_l<92> b_wl_l<91> b_wl_l<90> b_wl_l<89> b_wl_l<88> b_wl_l<87> b_wl_l<86> b_wl_l<85> b_wl_l<84> b_wl_l<83> b_wl_l<82> b_wl_l<81> b_wl_l<80> VDD! VSS! / RM_IHPSG13_1024x32_c2_2P_WLDRV16X4 +XB_WLDRV<4> b_wi<79> b_wi<78> b_wi<77> b_wi<76> b_wi<75> b_wi<74> b_wi<73> b_wi<72> b_wi<71> b_wi<70> b_wi<69> b_wi<68> b_wi<67> b_wi<66> b_wi<65> b_wi<64> b_wl_l<79> b_wl_l<78> b_wl_l<77> b_wl_l<76> b_wl_l<75> b_wl_l<74> b_wl_l<73> b_wl_l<72> b_wl_l<71> b_wl_l<70> b_wl_l<69> b_wl_l<68> b_wl_l<67> b_wl_l<66> b_wl_l<65> b_wl_l<64> VDD! VSS! / RM_IHPSG13_1024x32_c2_2P_WLDRV16X4 +XB_WLDRV<3> b_wi<63> b_wi<62> b_wi<61> b_wi<60> b_wi<59> b_wi<58> b_wi<57> b_wi<56> b_wi<55> b_wi<54> b_wi<53> b_wi<52> b_wi<51> b_wi<50> b_wi<49> b_wi<48> b_wl_l<63> b_wl_l<62> b_wl_l<61> b_wl_l<60> b_wl_l<59> b_wl_l<58> b_wl_l<57> b_wl_l<56> b_wl_l<55> b_wl_l<54> b_wl_l<53> b_wl_l<52> b_wl_l<51> b_wl_l<50> b_wl_l<49> b_wl_l<48> VDD! VSS! / RM_IHPSG13_1024x32_c2_2P_WLDRV16X4 +XB_WLDRV<2> b_wi<47> b_wi<46> b_wi<45> b_wi<44> b_wi<43> b_wi<42> b_wi<41> b_wi<40> b_wi<39> b_wi<38> b_wi<37> b_wi<36> b_wi<35> b_wi<34> b_wi<33> b_wi<32> b_wl_l<47> b_wl_l<46> b_wl_l<45> b_wl_l<44> b_wl_l<43> b_wl_l<42> b_wl_l<41> b_wl_l<40> b_wl_l<39> b_wl_l<38> b_wl_l<37> b_wl_l<36> b_wl_l<35> b_wl_l<34> b_wl_l<33> b_wl_l<32> VDD! VSS! / RM_IHPSG13_1024x32_c2_2P_WLDRV16X4 +XB_WLDRV<1> b_wi<31> b_wi<30> b_wi<29> b_wi<28> b_wi<27> b_wi<26> b_wi<25> b_wi<24> b_wi<23> b_wi<22> b_wi<21> b_wi<20> b_wi<19> b_wi<18> b_wi<17> b_wi<16> b_wl_l<31> b_wl_l<30> b_wl_l<29> b_wl_l<28> b_wl_l<27> b_wl_l<26> b_wl_l<25> b_wl_l<24> b_wl_l<23> b_wl_l<22> b_wl_l<21> b_wl_l<20> b_wl_l<19> b_wl_l<18> b_wl_l<17> b_wl_l<16> VDD! VSS! / RM_IHPSG13_1024x32_c2_2P_WLDRV16X4 +XB_WLDRV<0> b_wi<15> b_wi<14> b_wi<13> b_wi<12> b_wi<11> b_wi<10> b_wi<9> b_wi<8> b_wi<7> b_wi<6> b_wi<5> b_wi<4> b_wi<3> b_wi<2> b_wi<1> b_wi<0> b_wl_l<15> b_wl_l<14> b_wl_l<13> b_wl_l<12> b_wl_l<11> b_wl_l<10> b_wl_l<9> b_wl_l<8> b_wl_l<7> b_wl_l<6> b_wl_l<5> b_wl_l<4> b_wl_l<3> b_wl_l<2> b_wl_l<1> b_wl_l<0> VDD! VSS! / RM_IHPSG13_1024x32_c2_2P_WLDRV16X4 +XA_WLDRV<31> a_wi<255> a_wi<254> a_wi<253> a_wi<252> a_wi<251> a_wi<250> a_wi<249> a_wi<248> a_wi<247> a_wi<246> a_wi<245> a_wi<244> a_wi<243> a_wi<242> a_wi<241> a_wi<240> a_wl_r<255> a_wl_r<254> a_wl_r<253> a_wl_r<252> a_wl_r<251> a_wl_r<250> a_wl_r<249> a_wl_r<248> a_wl_r<247> a_wl_r<246> a_wl_r<245> a_wl_r<244> a_wl_r<243> a_wl_r<242> a_wl_r<241> a_wl_r<240> VDD! VSS! / RM_IHPSG13_1024x32_c2_2P_WLDRV16X4 +XA_WLDRV<30> a_wi<239> a_wi<238> a_wi<237> a_wi<236> a_wi<235> a_wi<234> a_wi<233> a_wi<232> a_wi<231> a_wi<230> a_wi<229> a_wi<228> a_wi<227> a_wi<226> a_wi<225> a_wi<224> a_wl_r<239> a_wl_r<238> a_wl_r<237> a_wl_r<236> a_wl_r<235> a_wl_r<234> a_wl_r<233> a_wl_r<232> a_wl_r<231> a_wl_r<230> a_wl_r<229> a_wl_r<228> a_wl_r<227> a_wl_r<226> a_wl_r<225> a_wl_r<224> VDD! VSS! / RM_IHPSG13_1024x32_c2_2P_WLDRV16X4 +XA_WLDRV<29> a_wi<223> a_wi<222> a_wi<221> a_wi<220> a_wi<219> a_wi<218> a_wi<217> a_wi<216> a_wi<215> a_wi<214> a_wi<213> a_wi<212> a_wi<211> a_wi<210> a_wi<209> a_wi<208> a_wl_r<223> a_wl_r<222> a_wl_r<221> a_wl_r<220> a_wl_r<219> a_wl_r<218> a_wl_r<217> a_wl_r<216> a_wl_r<215> a_wl_r<214> a_wl_r<213> a_wl_r<212> a_wl_r<211> a_wl_r<210> a_wl_r<209> a_wl_r<208> VDD! VSS! / RM_IHPSG13_1024x32_c2_2P_WLDRV16X4 +XA_WLDRV<28> a_wi<207> a_wi<206> a_wi<205> a_wi<204> a_wi<203> a_wi<202> a_wi<201> a_wi<200> a_wi<199> a_wi<198> a_wi<197> a_wi<196> a_wi<195> a_wi<194> a_wi<193> a_wi<192> a_wl_r<207> a_wl_r<206> a_wl_r<205> a_wl_r<204> a_wl_r<203> a_wl_r<202> a_wl_r<201> a_wl_r<200> a_wl_r<199> a_wl_r<198> a_wl_r<197> a_wl_r<196> a_wl_r<195> a_wl_r<194> a_wl_r<193> a_wl_r<192> VDD! VSS! / RM_IHPSG13_1024x32_c2_2P_WLDRV16X4 +XA_WLDRV<27> a_wi<191> a_wi<190> a_wi<189> a_wi<188> a_wi<187> a_wi<186> a_wi<185> a_wi<184> a_wi<183> a_wi<182> a_wi<181> a_wi<180> a_wi<179> a_wi<178> a_wi<177> a_wi<176> a_wl_r<191> a_wl_r<190> a_wl_r<189> a_wl_r<188> a_wl_r<187> a_wl_r<186> a_wl_r<185> a_wl_r<184> a_wl_r<183> a_wl_r<182> a_wl_r<181> a_wl_r<180> a_wl_r<179> a_wl_r<178> a_wl_r<177> a_wl_r<176> VDD! VSS! / RM_IHPSG13_1024x32_c2_2P_WLDRV16X4 +XA_WLDRV<26> a_wi<175> a_wi<174> a_wi<173> a_wi<172> a_wi<171> a_wi<170> a_wi<169> a_wi<168> a_wi<167> a_wi<166> a_wi<165> a_wi<164> a_wi<163> a_wi<162> a_wi<161> a_wi<160> a_wl_r<175> a_wl_r<174> a_wl_r<173> a_wl_r<172> a_wl_r<171> a_wl_r<170> a_wl_r<169> a_wl_r<168> a_wl_r<167> a_wl_r<166> a_wl_r<165> a_wl_r<164> a_wl_r<163> a_wl_r<162> a_wl_r<161> a_wl_r<160> VDD! VSS! / RM_IHPSG13_1024x32_c2_2P_WLDRV16X4 +XA_WLDRV<25> a_wi<159> a_wi<158> a_wi<157> a_wi<156> a_wi<155> a_wi<154> a_wi<153> a_wi<152> a_wi<151> a_wi<150> a_wi<149> a_wi<148> a_wi<147> a_wi<146> a_wi<145> a_wi<144> a_wl_r<159> a_wl_r<158> a_wl_r<157> a_wl_r<156> a_wl_r<155> a_wl_r<154> a_wl_r<153> a_wl_r<152> a_wl_r<151> a_wl_r<150> a_wl_r<149> a_wl_r<148> a_wl_r<147> a_wl_r<146> a_wl_r<145> a_wl_r<144> VDD! VSS! / RM_IHPSG13_1024x32_c2_2P_WLDRV16X4 +XA_WLDRV<24> a_wi<143> a_wi<142> a_wi<141> a_wi<140> a_wi<139> a_wi<138> a_wi<137> a_wi<136> a_wi<135> a_wi<134> a_wi<133> a_wi<132> a_wi<131> a_wi<130> a_wi<129> a_wi<128> a_wl_r<143> a_wl_r<142> a_wl_r<141> a_wl_r<140> a_wl_r<139> a_wl_r<138> a_wl_r<137> a_wl_r<136> a_wl_r<135> a_wl_r<134> a_wl_r<133> a_wl_r<132> a_wl_r<131> a_wl_r<130> a_wl_r<129> a_wl_r<128> VDD! VSS! / RM_IHPSG13_1024x32_c2_2P_WLDRV16X4 +XA_WLDRV<23> a_wi<127> a_wi<126> a_wi<125> a_wi<124> a_wi<123> a_wi<122> a_wi<121> a_wi<120> a_wi<119> a_wi<118> a_wi<117> a_wi<116> a_wi<115> a_wi<114> a_wi<113> a_wi<112> a_wl_r<127> a_wl_r<126> a_wl_r<125> a_wl_r<124> a_wl_r<123> a_wl_r<122> a_wl_r<121> a_wl_r<120> a_wl_r<119> a_wl_r<118> a_wl_r<117> a_wl_r<116> a_wl_r<115> a_wl_r<114> a_wl_r<113> a_wl_r<112> VDD! VSS! / RM_IHPSG13_1024x32_c2_2P_WLDRV16X4 +XA_WLDRV<22> a_wi<111> a_wi<110> a_wi<109> a_wi<108> a_wi<107> a_wi<106> a_wi<105> a_wi<104> a_wi<103> a_wi<102> a_wi<101> a_wi<100> a_wi<99> a_wi<98> a_wi<97> a_wi<96> a_wl_r<111> a_wl_r<110> a_wl_r<109> a_wl_r<108> a_wl_r<107> a_wl_r<106> a_wl_r<105> a_wl_r<104> a_wl_r<103> a_wl_r<102> a_wl_r<101> a_wl_r<100> a_wl_r<99> a_wl_r<98> a_wl_r<97> a_wl_r<96> VDD! VSS! / RM_IHPSG13_1024x32_c2_2P_WLDRV16X4 +XA_WLDRV<21> a_wi<95> a_wi<94> a_wi<93> a_wi<92> a_wi<91> a_wi<90> a_wi<89> a_wi<88> a_wi<87> a_wi<86> a_wi<85> a_wi<84> a_wi<83> a_wi<82> a_wi<81> a_wi<80> a_wl_r<95> a_wl_r<94> a_wl_r<93> a_wl_r<92> a_wl_r<91> a_wl_r<90> a_wl_r<89> a_wl_r<88> a_wl_r<87> a_wl_r<86> a_wl_r<85> a_wl_r<84> a_wl_r<83> a_wl_r<82> a_wl_r<81> a_wl_r<80> VDD! VSS! / RM_IHPSG13_1024x32_c2_2P_WLDRV16X4 +XA_WLDRV<20> a_wi<79> a_wi<78> a_wi<77> a_wi<76> a_wi<75> a_wi<74> a_wi<73> a_wi<72> a_wi<71> a_wi<70> a_wi<69> a_wi<68> a_wi<67> a_wi<66> a_wi<65> a_wi<64> a_wl_r<79> a_wl_r<78> a_wl_r<77> a_wl_r<76> a_wl_r<75> a_wl_r<74> a_wl_r<73> a_wl_r<72> a_wl_r<71> a_wl_r<70> a_wl_r<69> a_wl_r<68> a_wl_r<67> a_wl_r<66> a_wl_r<65> a_wl_r<64> VDD! VSS! / RM_IHPSG13_1024x32_c2_2P_WLDRV16X4 +XA_WLDRV<19> a_wi<63> a_wi<62> a_wi<61> a_wi<60> a_wi<59> a_wi<58> a_wi<57> a_wi<56> a_wi<55> a_wi<54> a_wi<53> a_wi<52> a_wi<51> a_wi<50> a_wi<49> a_wi<48> a_wl_r<63> a_wl_r<62> a_wl_r<61> a_wl_r<60> a_wl_r<59> a_wl_r<58> a_wl_r<57> a_wl_r<56> a_wl_r<55> a_wl_r<54> a_wl_r<53> a_wl_r<52> a_wl_r<51> a_wl_r<50> a_wl_r<49> a_wl_r<48> VDD! VSS! / RM_IHPSG13_1024x32_c2_2P_WLDRV16X4 +XA_WLDRV<18> a_wi<47> a_wi<46> a_wi<45> a_wi<44> a_wi<43> a_wi<42> a_wi<41> a_wi<40> a_wi<39> a_wi<38> a_wi<37> a_wi<36> a_wi<35> a_wi<34> a_wi<33> a_wi<32> a_wl_r<47> a_wl_r<46> a_wl_r<45> a_wl_r<44> a_wl_r<43> a_wl_r<42> a_wl_r<41> a_wl_r<40> a_wl_r<39> a_wl_r<38> a_wl_r<37> a_wl_r<36> a_wl_r<35> a_wl_r<34> a_wl_r<33> a_wl_r<32> VDD! VSS! / RM_IHPSG13_1024x32_c2_2P_WLDRV16X4 +XA_WLDRV<17> a_wi<31> a_wi<30> a_wi<29> a_wi<28> a_wi<27> a_wi<26> a_wi<25> a_wi<24> a_wi<23> a_wi<22> a_wi<21> a_wi<20> a_wi<19> a_wi<18> a_wi<17> a_wi<16> a_wl_r<31> a_wl_r<30> a_wl_r<29> a_wl_r<28> a_wl_r<27> a_wl_r<26> a_wl_r<25> a_wl_r<24> a_wl_r<23> a_wl_r<22> a_wl_r<21> a_wl_r<20> a_wl_r<19> a_wl_r<18> a_wl_r<17> a_wl_r<16> VDD! VSS! / RM_IHPSG13_1024x32_c2_2P_WLDRV16X4 +XA_WLDRV<16> a_wi<15> a_wi<14> a_wi<13> a_wi<12> a_wi<11> a_wi<10> a_wi<9> a_wi<8> a_wi<7> a_wi<6> a_wi<5> a_wi<4> a_wi<3> a_wi<2> a_wi<1> a_wi<0> a_wl_r<15> a_wl_r<14> a_wl_r<13> a_wl_r<12> a_wl_r<11> a_wl_r<10> a_wl_r<9> a_wl_r<8> a_wl_r<7> a_wl_r<6> a_wl_r<5> a_wl_r<4> a_wl_r<3> a_wl_r<2> a_wl_r<1> a_wl_r<0> VDD! VSS! / RM_IHPSG13_1024x32_c2_2P_WLDRV16X4 +XA_WLDRV<15> a_wi<255> a_wi<254> a_wi<253> a_wi<252> a_wi<251> a_wi<250> a_wi<249> a_wi<248> a_wi<247> a_wi<246> a_wi<245> a_wi<244> a_wi<243> a_wi<242> a_wi<241> a_wi<240> a_wl_l<255> a_wl_l<254> a_wl_l<253> a_wl_l<252> a_wl_l<251> a_wl_l<250> a_wl_l<249> a_wl_l<248> a_wl_l<247> a_wl_l<246> a_wl_l<245> a_wl_l<244> a_wl_l<243> a_wl_l<242> a_wl_l<241> a_wl_l<240> VDD! VSS! / RM_IHPSG13_1024x32_c2_2P_WLDRV16X4 +XA_WLDRV<14> a_wi<239> a_wi<238> a_wi<237> a_wi<236> a_wi<235> a_wi<234> a_wi<233> a_wi<232> a_wi<231> a_wi<230> a_wi<229> a_wi<228> a_wi<227> a_wi<226> a_wi<225> a_wi<224> a_wl_l<239> a_wl_l<238> a_wl_l<237> a_wl_l<236> a_wl_l<235> a_wl_l<234> a_wl_l<233> a_wl_l<232> a_wl_l<231> a_wl_l<230> a_wl_l<229> a_wl_l<228> a_wl_l<227> a_wl_l<226> a_wl_l<225> a_wl_l<224> VDD! VSS! / RM_IHPSG13_1024x32_c2_2P_WLDRV16X4 +XA_WLDRV<13> a_wi<223> a_wi<222> a_wi<221> a_wi<220> a_wi<219> a_wi<218> a_wi<217> a_wi<216> a_wi<215> a_wi<214> a_wi<213> a_wi<212> a_wi<211> a_wi<210> a_wi<209> a_wi<208> a_wl_l<223> a_wl_l<222> a_wl_l<221> a_wl_l<220> a_wl_l<219> a_wl_l<218> a_wl_l<217> a_wl_l<216> a_wl_l<215> a_wl_l<214> a_wl_l<213> a_wl_l<212> a_wl_l<211> a_wl_l<210> a_wl_l<209> a_wl_l<208> VDD! VSS! / RM_IHPSG13_1024x32_c2_2P_WLDRV16X4 +XA_WLDRV<12> a_wi<207> a_wi<206> a_wi<205> a_wi<204> a_wi<203> a_wi<202> a_wi<201> a_wi<200> a_wi<199> a_wi<198> a_wi<197> a_wi<196> a_wi<195> a_wi<194> a_wi<193> a_wi<192> a_wl_l<207> a_wl_l<206> a_wl_l<205> a_wl_l<204> a_wl_l<203> a_wl_l<202> a_wl_l<201> a_wl_l<200> a_wl_l<199> a_wl_l<198> a_wl_l<197> a_wl_l<196> a_wl_l<195> a_wl_l<194> a_wl_l<193> a_wl_l<192> VDD! VSS! / RM_IHPSG13_1024x32_c2_2P_WLDRV16X4 +XA_WLDRV<11> a_wi<191> a_wi<190> a_wi<189> a_wi<188> a_wi<187> a_wi<186> a_wi<185> a_wi<184> a_wi<183> a_wi<182> a_wi<181> a_wi<180> a_wi<179> a_wi<178> a_wi<177> a_wi<176> a_wl_l<191> a_wl_l<190> a_wl_l<189> a_wl_l<188> a_wl_l<187> a_wl_l<186> a_wl_l<185> a_wl_l<184> a_wl_l<183> a_wl_l<182> a_wl_l<181> a_wl_l<180> a_wl_l<179> a_wl_l<178> a_wl_l<177> a_wl_l<176> VDD! VSS! / RM_IHPSG13_1024x32_c2_2P_WLDRV16X4 +XA_WLDRV<10> a_wi<175> a_wi<174> a_wi<173> a_wi<172> a_wi<171> a_wi<170> a_wi<169> a_wi<168> a_wi<167> a_wi<166> a_wi<165> a_wi<164> a_wi<163> a_wi<162> a_wi<161> a_wi<160> a_wl_l<175> a_wl_l<174> a_wl_l<173> a_wl_l<172> a_wl_l<171> a_wl_l<170> a_wl_l<169> a_wl_l<168> a_wl_l<167> a_wl_l<166> a_wl_l<165> a_wl_l<164> a_wl_l<163> a_wl_l<162> a_wl_l<161> a_wl_l<160> VDD! VSS! / RM_IHPSG13_1024x32_c2_2P_WLDRV16X4 +XA_WLDRV<9> a_wi<159> a_wi<158> a_wi<157> a_wi<156> a_wi<155> a_wi<154> a_wi<153> a_wi<152> a_wi<151> a_wi<150> a_wi<149> a_wi<148> a_wi<147> a_wi<146> a_wi<145> a_wi<144> a_wl_l<159> a_wl_l<158> a_wl_l<157> a_wl_l<156> a_wl_l<155> a_wl_l<154> a_wl_l<153> a_wl_l<152> a_wl_l<151> a_wl_l<150> a_wl_l<149> a_wl_l<148> a_wl_l<147> a_wl_l<146> a_wl_l<145> a_wl_l<144> VDD! VSS! / RM_IHPSG13_1024x32_c2_2P_WLDRV16X4 +XA_WLDRV<8> a_wi<143> a_wi<142> a_wi<141> a_wi<140> a_wi<139> a_wi<138> a_wi<137> a_wi<136> a_wi<135> a_wi<134> a_wi<133> a_wi<132> a_wi<131> a_wi<130> a_wi<129> a_wi<128> a_wl_l<143> a_wl_l<142> a_wl_l<141> a_wl_l<140> a_wl_l<139> a_wl_l<138> a_wl_l<137> a_wl_l<136> a_wl_l<135> a_wl_l<134> a_wl_l<133> a_wl_l<132> a_wl_l<131> a_wl_l<130> a_wl_l<129> a_wl_l<128> VDD! VSS! / RM_IHPSG13_1024x32_c2_2P_WLDRV16X4 +XA_WLDRV<7> a_wi<127> a_wi<126> a_wi<125> a_wi<124> a_wi<123> a_wi<122> a_wi<121> a_wi<120> a_wi<119> a_wi<118> a_wi<117> a_wi<116> a_wi<115> a_wi<114> a_wi<113> a_wi<112> a_wl_l<127> a_wl_l<126> a_wl_l<125> a_wl_l<124> a_wl_l<123> a_wl_l<122> a_wl_l<121> a_wl_l<120> a_wl_l<119> a_wl_l<118> a_wl_l<117> a_wl_l<116> a_wl_l<115> a_wl_l<114> a_wl_l<113> a_wl_l<112> VDD! VSS! / RM_IHPSG13_1024x32_c2_2P_WLDRV16X4 +XA_WLDRV<6> a_wi<111> a_wi<110> a_wi<109> a_wi<108> a_wi<107> a_wi<106> a_wi<105> a_wi<104> a_wi<103> a_wi<102> a_wi<101> a_wi<100> a_wi<99> a_wi<98> a_wi<97> a_wi<96> a_wl_l<111> a_wl_l<110> a_wl_l<109> a_wl_l<108> a_wl_l<107> a_wl_l<106> a_wl_l<105> a_wl_l<104> a_wl_l<103> a_wl_l<102> a_wl_l<101> a_wl_l<100> a_wl_l<99> a_wl_l<98> a_wl_l<97> a_wl_l<96> VDD! VSS! / RM_IHPSG13_1024x32_c2_2P_WLDRV16X4 +XA_WLDRV<5> a_wi<95> a_wi<94> a_wi<93> a_wi<92> a_wi<91> a_wi<90> a_wi<89> a_wi<88> a_wi<87> a_wi<86> a_wi<85> a_wi<84> a_wi<83> a_wi<82> a_wi<81> a_wi<80> a_wl_l<95> a_wl_l<94> a_wl_l<93> a_wl_l<92> a_wl_l<91> a_wl_l<90> a_wl_l<89> a_wl_l<88> a_wl_l<87> a_wl_l<86> a_wl_l<85> a_wl_l<84> a_wl_l<83> a_wl_l<82> a_wl_l<81> a_wl_l<80> VDD! VSS! / RM_IHPSG13_1024x32_c2_2P_WLDRV16X4 +XA_WLDRV<4> a_wi<79> a_wi<78> a_wi<77> a_wi<76> a_wi<75> a_wi<74> a_wi<73> a_wi<72> a_wi<71> a_wi<70> a_wi<69> a_wi<68> a_wi<67> a_wi<66> a_wi<65> a_wi<64> a_wl_l<79> a_wl_l<78> a_wl_l<77> a_wl_l<76> a_wl_l<75> a_wl_l<74> a_wl_l<73> a_wl_l<72> a_wl_l<71> a_wl_l<70> a_wl_l<69> a_wl_l<68> a_wl_l<67> a_wl_l<66> a_wl_l<65> a_wl_l<64> VDD! VSS! / RM_IHPSG13_1024x32_c2_2P_WLDRV16X4 +XA_WLDRV<3> a_wi<63> a_wi<62> a_wi<61> a_wi<60> a_wi<59> a_wi<58> a_wi<57> a_wi<56> a_wi<55> a_wi<54> a_wi<53> a_wi<52> a_wi<51> a_wi<50> a_wi<49> a_wi<48> a_wl_l<63> a_wl_l<62> a_wl_l<61> a_wl_l<60> a_wl_l<59> a_wl_l<58> a_wl_l<57> a_wl_l<56> a_wl_l<55> a_wl_l<54> a_wl_l<53> a_wl_l<52> a_wl_l<51> a_wl_l<50> a_wl_l<49> a_wl_l<48> VDD! VSS! / RM_IHPSG13_1024x32_c2_2P_WLDRV16X4 +XA_WLDRV<2> a_wi<47> a_wi<46> a_wi<45> a_wi<44> a_wi<43> a_wi<42> a_wi<41> a_wi<40> a_wi<39> a_wi<38> a_wi<37> a_wi<36> a_wi<35> a_wi<34> a_wi<33> a_wi<32> a_wl_l<47> a_wl_l<46> a_wl_l<45> a_wl_l<44> a_wl_l<43> a_wl_l<42> a_wl_l<41> a_wl_l<40> a_wl_l<39> a_wl_l<38> a_wl_l<37> a_wl_l<36> a_wl_l<35> a_wl_l<34> a_wl_l<33> a_wl_l<32> VDD! VSS! / RM_IHPSG13_1024x32_c2_2P_WLDRV16X4 +XA_WLDRV<1> a_wi<31> a_wi<30> a_wi<29> a_wi<28> a_wi<27> a_wi<26> a_wi<25> a_wi<24> a_wi<23> a_wi<22> a_wi<21> a_wi<20> a_wi<19> a_wi<18> a_wi<17> a_wi<16> a_wl_l<31> a_wl_l<30> a_wl_l<29> a_wl_l<28> a_wl_l<27> a_wl_l<26> a_wl_l<25> a_wl_l<24> a_wl_l<23> a_wl_l<22> a_wl_l<21> a_wl_l<20> a_wl_l<19> a_wl_l<18> a_wl_l<17> a_wl_l<16> VDD! VSS! / RM_IHPSG13_1024x32_c2_2P_WLDRV16X4 +XA_WLDRV<0> a_wi<15> a_wi<14> a_wi<13> a_wi<12> a_wi<11> a_wi<10> a_wi<9> a_wi<8> a_wi<7> a_wi<6> a_wi<5> a_wi<4> a_wi<3> a_wi<2> a_wi<1> a_wi<0> a_wl_l<15> a_wl_l<14> a_wl_l<13> a_wl_l<12> a_wl_l<11> a_wl_l<10> a_wl_l<9> a_wl_l<8> a_wl_l<7> a_wl_l<6> a_wl_l<5> a_wl_l<4> a_wl_l<3> a_wl_l<2> a_wl_l<1> a_wl_l<0> VDD! VSS! / RM_IHPSG13_1024x32_c2_2P_WLDRV16X4 + + +XB_CTRL b_aclk_n B_BIST_CLK B_BIST_MEN B_BIST_EN B_BIST_REN B_BIST_WEN b_tiel B_CLK B_MEN b_dclk b_eclk b_pulse_h b_pulse_l b_pulse b_rclk B_REN b_cs b_wclk B_WEN VDD! VSS! / RM_IHPSG13_1024x32_c2_2P_CTRL +XA_CTRL a_aclk_n A_BIST_CLK A_BIST_MEN A_BIST_EN A_BIST_REN A_BIST_WEN a_tiel A_CLK A_MEN a_dclk a_eclk a_pulse_h a_pulse_l a_pulse a_rclk A_REN a_cs a_wclk A_WEN VDD! VSS! / RM_IHPSG13_1024x32_c2_2P_CTRL + + +XB_ROWDEC b_addr_row<7> b_addr_row<6> b_addr_row<5> b_addr_row<4> b_addr_row<3> b_addr_row<2> b_addr_row<1> b_addr_row<0> b_cs b_eclk b_wi<255> b_wi<254> b_wi<253> b_wi<252> b_wi<251> b_wi<250> b_wi<249> b_wi<248> b_wi<247> b_wi<246> b_wi<245> b_wi<244> b_wi<243> b_wi<242> b_wi<241> b_wi<240> b_wi<239> b_wi<238> b_wi<237> b_wi<236> b_wi<235> b_wi<234> b_wi<233> b_wi<232> b_wi<231> b_wi<230> b_wi<229> b_wi<228> b_wi<227> b_wi<226> b_wi<225> b_wi<224> b_wi<223> b_wi<222> b_wi<221> b_wi<220> b_wi<219> b_wi<218> b_wi<217> b_wi<216> b_wi<215> b_wi<214> b_wi<213> b_wi<212> b_wi<211> b_wi<210> b_wi<209> b_wi<208> b_wi<207> b_wi<206> b_wi<205> b_wi<204> b_wi<203> b_wi<202> b_wi<201> b_wi<200> b_wi<199> b_wi<198> b_wi<197> b_wi<196> b_wi<195> b_wi<194> b_wi<193> b_wi<192> b_wi<191> b_wi<190> b_wi<189> b_wi<188> b_wi<187> b_wi<186> b_wi<185> b_wi<184> b_wi<183> b_wi<182> b_wi<181> b_wi<180> b_wi<179> b_wi<178> b_wi<177> b_wi<176> b_wi<175> b_wi<174> b_wi<173> b_wi<172> b_wi<171> b_wi<170> b_wi<169> b_wi<168> b_wi<167> b_wi<166> b_wi<165> b_wi<164> b_wi<163> b_wi<162> b_wi<161> b_wi<160> b_wi<159> b_wi<158> b_wi<157> b_wi<156> b_wi<155> b_wi<154> b_wi<153> b_wi<152> b_wi<151> b_wi<150> b_wi<149> b_wi<148> b_wi<147> b_wi<146> b_wi<145> b_wi<144> b_wi<143> b_wi<142> b_wi<141> b_wi<140> b_wi<139> b_wi<138> b_wi<137> b_wi<136> b_wi<135> b_wi<134> b_wi<133> b_wi<132> b_wi<131> b_wi<130> b_wi<129> b_wi<128> b_wi<127> b_wi<126> b_wi<125> b_wi<124> b_wi<123> b_wi<122> b_wi<121> b_wi<120> b_wi<119> b_wi<118> b_wi<117> b_wi<116> b_wi<115> b_wi<114> b_wi<113> b_wi<112> b_wi<111> b_wi<110> b_wi<109> b_wi<108> b_wi<107> b_wi<106> b_wi<105> b_wi<104> b_wi<103> b_wi<102> b_wi<101> b_wi<100> b_wi<99> b_wi<98> b_wi<97> b_wi<96> b_wi<95> b_wi<94> b_wi<93> b_wi<92> b_wi<91> b_wi<90> b_wi<89> b_wi<88> b_wi<87> b_wi<86> b_wi<85> b_wi<84> b_wi<83> b_wi<82> b_wi<81> b_wi<80> b_wi<79> b_wi<78> b_wi<77> b_wi<76> b_wi<75> b_wi<74> b_wi<73> b_wi<72> b_wi<71> b_wi<70> b_wi<69> b_wi<68> b_wi<67> b_wi<66> b_wi<65> b_wi<64> b_wi<63> b_wi<62> b_wi<61> b_wi<60> b_wi<59> b_wi<58> b_wi<57> b_wi<56> b_wi<55> b_wi<54> b_wi<53> b_wi<52> b_wi<51> b_wi<50> b_wi<49> b_wi<48> b_wi<47> b_wi<46> b_wi<45> b_wi<44> b_wi<43> b_wi<42> b_wi<41> b_wi<40> b_wi<39> b_wi<38> b_wi<37> b_wi<36> b_wi<35> b_wi<34> b_wi<33> b_wi<32> b_wi<31> b_wi<30> b_wi<29> b_wi<28> b_wi<27> b_wi<26> b_wi<25> b_wi<24> b_wi<23> b_wi<22> b_wi<21> b_wi<20> b_wi<19> b_wi<18> b_wi<17> b_wi<16> b_wi<15> b_wi<14> b_wi<13> b_wi<12> b_wi<11> b_wi<10> b_wi<9> b_wi<8> b_wi<7> b_wi<6> b_wi<5> b_wi<4> b_wi<3> b_wi<2> b_wi<1> b_wi<0> VDD! VSS! / RM_IHPSG13_1024x32_c2_2P_ROWDEC8 +XA_ROWDEC a_addr_row<7> a_addr_row<6> a_addr_row<5> a_addr_row<4> a_addr_row<3> a_addr_row<2> a_addr_row<1> a_addr_row<0> a_cs a_eclk a_wi<255> a_wi<254> a_wi<253> a_wi<252> a_wi<251> a_wi<250> a_wi<249> a_wi<248> a_wi<247> a_wi<246> a_wi<245> a_wi<244> a_wi<243> a_wi<242> a_wi<241> a_wi<240> a_wi<239> a_wi<238> a_wi<237> a_wi<236> a_wi<235> a_wi<234> a_wi<233> a_wi<232> a_wi<231> a_wi<230> a_wi<229> a_wi<228> a_wi<227> a_wi<226> a_wi<225> a_wi<224> a_wi<223> a_wi<222> a_wi<221> a_wi<220> a_wi<219> a_wi<218> a_wi<217> a_wi<216> a_wi<215> a_wi<214> a_wi<213> a_wi<212> a_wi<211> a_wi<210> a_wi<209> a_wi<208> a_wi<207> a_wi<206> a_wi<205> a_wi<204> a_wi<203> a_wi<202> a_wi<201> a_wi<200> a_wi<199> a_wi<198> a_wi<197> a_wi<196> a_wi<195> a_wi<194> a_wi<193> a_wi<192> a_wi<191> a_wi<190> a_wi<189> a_wi<188> a_wi<187> a_wi<186> a_wi<185> a_wi<184> a_wi<183> a_wi<182> a_wi<181> a_wi<180> a_wi<179> a_wi<178> a_wi<177> a_wi<176> a_wi<175> a_wi<174> a_wi<173> a_wi<172> a_wi<171> a_wi<170> a_wi<169> a_wi<168> a_wi<167> a_wi<166> a_wi<165> a_wi<164> a_wi<163> a_wi<162> a_wi<161> a_wi<160> a_wi<159> a_wi<158> a_wi<157> a_wi<156> a_wi<155> a_wi<154> a_wi<153> a_wi<152> a_wi<151> a_wi<150> a_wi<149> a_wi<148> a_wi<147> a_wi<146> a_wi<145> a_wi<144> a_wi<143> a_wi<142> a_wi<141> a_wi<140> a_wi<139> a_wi<138> a_wi<137> a_wi<136> a_wi<135> a_wi<134> a_wi<133> a_wi<132> a_wi<131> a_wi<130> a_wi<129> a_wi<128> a_wi<127> a_wi<126> a_wi<125> a_wi<124> a_wi<123> a_wi<122> a_wi<121> a_wi<120> a_wi<119> a_wi<118> a_wi<117> a_wi<116> a_wi<115> a_wi<114> a_wi<113> a_wi<112> a_wi<111> a_wi<110> a_wi<109> a_wi<108> a_wi<107> a_wi<106> a_wi<105> a_wi<104> a_wi<103> a_wi<102> a_wi<101> a_wi<100> a_wi<99> a_wi<98> a_wi<97> a_wi<96> a_wi<95> a_wi<94> a_wi<93> a_wi<92> a_wi<91> a_wi<90> a_wi<89> a_wi<88> a_wi<87> a_wi<86> a_wi<85> a_wi<84> a_wi<83> a_wi<82> a_wi<81> a_wi<80> a_wi<79> a_wi<78> a_wi<77> a_wi<76> a_wi<75> a_wi<74> a_wi<73> a_wi<72> a_wi<71> a_wi<70> a_wi<69> a_wi<68> a_wi<67> a_wi<66> a_wi<65> a_wi<64> a_wi<63> a_wi<62> a_wi<61> a_wi<60> a_wi<59> a_wi<58> a_wi<57> a_wi<56> a_wi<55> a_wi<54> a_wi<53> a_wi<52> a_wi<51> a_wi<50> a_wi<49> a_wi<48> a_wi<47> a_wi<46> a_wi<45> a_wi<44> a_wi<43> a_wi<42> a_wi<41> a_wi<40> a_wi<39> a_wi<38> a_wi<37> a_wi<36> a_wi<35> a_wi<34> a_wi<33> a_wi<32> a_wi<31> a_wi<30> a_wi<29> a_wi<28> a_wi<27> a_wi<26> a_wi<25> a_wi<24> a_wi<23> a_wi<22> a_wi<21> a_wi<20> a_wi<19> a_wi<18> a_wi<17> a_wi<16> a_wi<15> a_wi<14> a_wi<13> a_wi<12> a_wi<11> a_wi<10> a_wi<9> a_wi<8> a_wi<7> a_wi<6> a_wi<5> a_wi<4> a_wi<3> a_wi<2> a_wi<1> a_wi<0> VDD! VSS! / RM_IHPSG13_1024x32_c2_2P_ROWDEC8 +XB_ROWREG b_aclk_n B_ADDR<9> B_ADDR<8> B_ADDR<7> B_ADDR<6> B_ADDR<5> B_ADDR<4> B_ADDR<3> B_ADDR<2> b_addr_row<7> b_addr_row<6> b_addr_row<5> b_addr_row<4> b_addr_row<3> b_addr_row<2> b_addr_row<1> b_addr_row<0> B_BIST_ADDR<9> B_BIST_ADDR<8> B_BIST_ADDR<7> B_BIST_ADDR<6> B_BIST_ADDR<5> B_BIST_ADDR<4> B_BIST_ADDR<3> B_BIST_ADDR<2> B_BIST_EN VDD! VSS! / RM_IHPSG13_1024x32_c2_2P_ROWREG8 +XA_ROWREG a_aclk_n A_ADDR<9> A_ADDR<8> A_ADDR<7> A_ADDR<6> A_ADDR<5> A_ADDR<4> A_ADDR<3> A_ADDR<2> a_addr_row<7> a_addr_row<6> a_addr_row<5> a_addr_row<4> a_addr_row<3> a_addr_row<2> a_addr_row<1> a_addr_row<0> A_BIST_ADDR<9> A_BIST_ADDR<8> A_BIST_ADDR<7> A_BIST_ADDR<6> A_BIST_ADDR<5> A_BIST_ADDR<4> A_BIST_ADDR<3> A_BIST_ADDR<2> A_BIST_EN VDD! VSS! / RM_IHPSG13_1024x32_c2_2P_ROWREG8 +XB_COLDEC b_aclk_n B_ADDR<1> B_ADDR<0> b_addr_col<1> b_addr_col<0> b_addr_dec<7> b_addr_dec<6> b_addr_dec<5> b_addr_dec<4> b_addr_dec<3> b_addr_dec<2> b_addr_dec<1> b_addr_dec<0> B_BIST_ADDR<1> B_BIST_ADDR<0> B_BIST_EN VDD! VSS! / RM_IHPSG13_1024x32_c2_2P_COLDEC2 +XA_COLDEC a_aclk_n A_ADDR<1> A_ADDR<0> a_addr_col<1> a_addr_col<0> a_addr_dec<7> a_addr_dec<6> a_addr_dec<5> a_addr_dec<4> a_addr_dec<3> a_addr_dec<2> a_addr_dec<1> a_addr_dec<0> A_BIST_ADDR<1> A_BIST_ADDR<0> A_BIST_EN VDD! VSS! / RM_IHPSG13_1024x32_c2_2P_COLDEC2 + + +XB_DLYH b_pulse b_pulse_h VDD! VSS! / RM_IHPSG13_1024x32_c2_2P_DLY_pcell_2 +XB_DLYL b_pulse_x b_pulse_l VDD! VSS! / RM_IHPSG13_1024x32_c2_2P_DLY_pcell_3 +XA_DLYH a_pulse a_pulse_h VDD! VSS! / RM_IHPSG13_1024x32_c2_2P_DLY_pcell_2 +XA_DLYL a_pulse_x a_pulse_l VDD! VSS! / RM_IHPSG13_1024x32_c2_2P_DLY_pcell_3 +XB_DLYMUX b_pulse_h B_DLY b_pulse_x VDD! VSS! / RM_IHPSG13_1024x32_c2_2P_DLY_MUX +XA_DLYMUX a_pulse_h A_DLY a_pulse_x VDD! VSS! / RM_IHPSG13_1024x32_c2_2P_DLY_MUX + +XCOLCTRL<31> a_addr_dec_r<3> a_addr_dec_r<2> a_addr_dec_r<1> a_addr_dec_r<0> A_BIST_BM<31> A_BIST_DIN<31> A_BIST_EN a_blc_r<63> a_blc_r<62> a_blc_r<61> a_blc_r<60> a_blt_r<63> a_blt_r<62> a_blt_r<61> a_blt_r<60> A_BM<31> a_dclk_n_r<15> a_dclk_n_r<16> a_dclk_p_r<15> a_dclk_p_r<16> A_DOUT<31> A_DIN<31> a_rclk_n_r<15> a_rclk_n_r<16> a_rclk_p_r<15> a_rclk_p_r<16> a_tieh<31> a_wclk_n_r<15> a_wclk_n_r<16> a_wclk_p_r<15> a_wclk_p_r<16> b_addr_dec_r<3> b_addr_dec_r<2> b_addr_dec_r<1> b_addr_dec_r<0> B_BIST_BM<31> B_BIST_DIN<31> B_BIST_EN b_blc_r<63> b_blc_r<62> b_blc_r<61> b_blc_r<60> b_blt_r<63> b_blt_r<62> b_blt_r<61> b_blt_r<60> B_BM<31> b_dclk_n_r<15> b_dclk_n_r<16> b_dclk_p_r<15> b_dclk_p_r<16> B_DOUT<31> B_DIN<31> b_rclk_n_r<15> b_rclk_n_r<16> b_rclk_p_r<15> b_rclk_p_r<16> b_tieh<31> b_wclk_n_r<15> b_wclk_n_r<16> b_wclk_p_r<15> b_wclk_p_r<16> VDD! VSS! / RM_IHPSG13_1024x32_c2_2P_COLCTRL2 +XCOLCTRL<30> a_addr_dec_r<3> a_addr_dec_r<2> a_addr_dec_r<1> a_addr_dec_r<0> A_BIST_BM<30> A_BIST_DIN<30> A_BIST_EN a_blc_r<59> a_blc_r<58> a_blc_r<57> a_blc_r<56> a_blt_r<59> a_blt_r<58> a_blt_r<57> a_blt_r<56> A_BM<30> a_dclk_n_r<14> a_dclk_n_r<15> a_dclk_p_r<14> a_dclk_p_r<15> A_DOUT<30> A_DIN<30> a_rclk_n_r<14> a_rclk_n_r<15> a_rclk_p_r<14> a_rclk_p_r<15> a_tieh<30> a_wclk_n_r<14> a_wclk_n_r<15> a_wclk_p_r<14> a_wclk_p_r<15> b_addr_dec_r<3> b_addr_dec_r<2> b_addr_dec_r<1> b_addr_dec_r<0> B_BIST_BM<30> B_BIST_DIN<30> B_BIST_EN b_blc_r<59> b_blc_r<58> b_blc_r<57> b_blc_r<56> b_blt_r<59> b_blt_r<58> b_blt_r<57> b_blt_r<56> B_BM<30> b_dclk_n_r<14> b_dclk_n_r<15> b_dclk_p_r<14> b_dclk_p_r<15> B_DOUT<30> B_DIN<30> b_rclk_n_r<14> b_rclk_n_r<15> b_rclk_p_r<14> b_rclk_p_r<15> b_tieh<30> b_wclk_n_r<14> b_wclk_n_r<15> b_wclk_p_r<14> b_wclk_p_r<15> VDD! VSS! / RM_IHPSG13_1024x32_c2_2P_COLCTRL2 +XCOLCTRL<29> a_addr_dec_r<3> a_addr_dec_r<2> a_addr_dec_r<1> a_addr_dec_r<0> A_BIST_BM<29> A_BIST_DIN<29> A_BIST_EN a_blc_r<55> a_blc_r<54> a_blc_r<53> a_blc_r<52> a_blt_r<55> a_blt_r<54> a_blt_r<53> a_blt_r<52> A_BM<29> a_dclk_n_r<13> a_dclk_n_r<14> a_dclk_p_r<13> a_dclk_p_r<14> A_DOUT<29> A_DIN<29> a_rclk_n_r<13> a_rclk_n_r<14> a_rclk_p_r<13> a_rclk_p_r<14> a_tieh<29> a_wclk_n_r<13> a_wclk_n_r<14> a_wclk_p_r<13> a_wclk_p_r<14> b_addr_dec_r<3> b_addr_dec_r<2> b_addr_dec_r<1> b_addr_dec_r<0> B_BIST_BM<29> B_BIST_DIN<29> B_BIST_EN b_blc_r<55> b_blc_r<54> b_blc_r<53> b_blc_r<52> b_blt_r<55> b_blt_r<54> b_blt_r<53> b_blt_r<52> B_BM<29> b_dclk_n_r<13> b_dclk_n_r<14> b_dclk_p_r<13> b_dclk_p_r<14> B_DOUT<29> B_DIN<29> b_rclk_n_r<13> b_rclk_n_r<14> b_rclk_p_r<13> b_rclk_p_r<14> b_tieh<29> b_wclk_n_r<13> b_wclk_n_r<14> b_wclk_p_r<13> b_wclk_p_r<14> VDD! VSS! / RM_IHPSG13_1024x32_c2_2P_COLCTRL2 +XCOLCTRL<28> a_addr_dec_r<3> a_addr_dec_r<2> a_addr_dec_r<1> a_addr_dec_r<0> A_BIST_BM<28> A_BIST_DIN<28> A_BIST_EN a_blc_r<51> a_blc_r<50> a_blc_r<49> a_blc_r<48> a_blt_r<51> a_blt_r<50> a_blt_r<49> a_blt_r<48> A_BM<28> a_dclk_n_r<12> a_dclk_n_r<13> a_dclk_p_r<12> a_dclk_p_r<13> A_DOUT<28> A_DIN<28> a_rclk_n_r<12> a_rclk_n_r<13> a_rclk_p_r<12> a_rclk_p_r<13> a_tieh<28> a_wclk_n_r<12> a_wclk_n_r<13> a_wclk_p_r<12> a_wclk_p_r<13> b_addr_dec_r<3> b_addr_dec_r<2> b_addr_dec_r<1> b_addr_dec_r<0> B_BIST_BM<28> B_BIST_DIN<28> B_BIST_EN b_blc_r<51> b_blc_r<50> b_blc_r<49> b_blc_r<48> b_blt_r<51> b_blt_r<50> b_blt_r<49> b_blt_r<48> B_BM<28> b_dclk_n_r<12> b_dclk_n_r<13> b_dclk_p_r<12> b_dclk_p_r<13> B_DOUT<28> B_DIN<28> b_rclk_n_r<12> b_rclk_n_r<13> b_rclk_p_r<12> b_rclk_p_r<13> b_tieh<28> b_wclk_n_r<12> b_wclk_n_r<13> b_wclk_p_r<12> b_wclk_p_r<13> VDD! VSS! / RM_IHPSG13_1024x32_c2_2P_COLCTRL2 +XCOLCTRL<27> a_addr_dec_r<3> a_addr_dec_r<2> a_addr_dec_r<1> a_addr_dec_r<0> A_BIST_BM<27> A_BIST_DIN<27> A_BIST_EN a_blc_r<47> a_blc_r<46> a_blc_r<45> a_blc_r<44> a_blt_r<47> a_blt_r<46> a_blt_r<45> a_blt_r<44> A_BM<27> a_dclk_n_r<11> a_dclk_n_r<12> a_dclk_p_r<11> a_dclk_p_r<12> A_DOUT<27> A_DIN<27> a_rclk_n_r<11> a_rclk_n_r<12> a_rclk_p_r<11> a_rclk_p_r<12> a_tieh<27> a_wclk_n_r<11> a_wclk_n_r<12> a_wclk_p_r<11> a_wclk_p_r<12> b_addr_dec_r<3> b_addr_dec_r<2> b_addr_dec_r<1> b_addr_dec_r<0> B_BIST_BM<27> B_BIST_DIN<27> B_BIST_EN b_blc_r<47> b_blc_r<46> b_blc_r<45> b_blc_r<44> b_blt_r<47> b_blt_r<46> b_blt_r<45> b_blt_r<44> B_BM<27> b_dclk_n_r<11> b_dclk_n_r<12> b_dclk_p_r<11> b_dclk_p_r<12> B_DOUT<27> B_DIN<27> b_rclk_n_r<11> b_rclk_n_r<12> b_rclk_p_r<11> b_rclk_p_r<12> b_tieh<27> b_wclk_n_r<11> b_wclk_n_r<12> b_wclk_p_r<11> b_wclk_p_r<12> VDD! VSS! / RM_IHPSG13_1024x32_c2_2P_COLCTRL2 +XCOLCTRL<26> a_addr_dec_r<3> a_addr_dec_r<2> a_addr_dec_r<1> a_addr_dec_r<0> A_BIST_BM<26> A_BIST_DIN<26> A_BIST_EN a_blc_r<43> a_blc_r<42> a_blc_r<41> a_blc_r<40> a_blt_r<43> a_blt_r<42> a_blt_r<41> a_blt_r<40> A_BM<26> a_dclk_n_r<10> a_dclk_n_r<11> a_dclk_p_r<10> a_dclk_p_r<11> A_DOUT<26> A_DIN<26> a_rclk_n_r<10> a_rclk_n_r<11> a_rclk_p_r<10> a_rclk_p_r<11> a_tieh<26> a_wclk_n_r<10> a_wclk_n_r<11> a_wclk_p_r<10> a_wclk_p_r<11> b_addr_dec_r<3> b_addr_dec_r<2> b_addr_dec_r<1> b_addr_dec_r<0> B_BIST_BM<26> B_BIST_DIN<26> B_BIST_EN b_blc_r<43> b_blc_r<42> b_blc_r<41> b_blc_r<40> b_blt_r<43> b_blt_r<42> b_blt_r<41> b_blt_r<40> B_BM<26> b_dclk_n_r<10> b_dclk_n_r<11> b_dclk_p_r<10> b_dclk_p_r<11> B_DOUT<26> B_DIN<26> b_rclk_n_r<10> b_rclk_n_r<11> b_rclk_p_r<10> b_rclk_p_r<11> b_tieh<26> b_wclk_n_r<10> b_wclk_n_r<11> b_wclk_p_r<10> b_wclk_p_r<11> VDD! VSS! / RM_IHPSG13_1024x32_c2_2P_COLCTRL2 +XCOLCTRL<25> a_addr_dec_r<3> a_addr_dec_r<2> a_addr_dec_r<1> a_addr_dec_r<0> A_BIST_BM<25> A_BIST_DIN<25> A_BIST_EN a_blc_r<39> a_blc_r<38> a_blc_r<37> a_blc_r<36> a_blt_r<39> a_blt_r<38> a_blt_r<37> a_blt_r<36> A_BM<25> a_dclk_n_r<9> a_dclk_n_r<10> a_dclk_p_r<9> a_dclk_p_r<10> A_DOUT<25> A_DIN<25> a_rclk_n_r<9> a_rclk_n_r<10> a_rclk_p_r<9> a_rclk_p_r<10> a_tieh<25> a_wclk_n_r<9> a_wclk_n_r<10> a_wclk_p_r<9> a_wclk_p_r<10> b_addr_dec_r<3> b_addr_dec_r<2> b_addr_dec_r<1> b_addr_dec_r<0> B_BIST_BM<25> B_BIST_DIN<25> B_BIST_EN b_blc_r<39> b_blc_r<38> b_blc_r<37> b_blc_r<36> b_blt_r<39> b_blt_r<38> b_blt_r<37> b_blt_r<36> B_BM<25> b_dclk_n_r<9> b_dclk_n_r<10> b_dclk_p_r<9> b_dclk_p_r<10> B_DOUT<25> B_DIN<25> b_rclk_n_r<9> b_rclk_n_r<10> b_rclk_p_r<9> b_rclk_p_r<10> b_tieh<25> b_wclk_n_r<9> b_wclk_n_r<10> b_wclk_p_r<9> b_wclk_p_r<10> VDD! VSS! / RM_IHPSG13_1024x32_c2_2P_COLCTRL2 +XCOLCTRL<24> a_addr_dec_r<3> a_addr_dec_r<2> a_addr_dec_r<1> a_addr_dec_r<0> A_BIST_BM<24> A_BIST_DIN<24> A_BIST_EN a_blc_r<35> a_blc_r<34> a_blc_r<33> a_blc_r<32> a_blt_r<35> a_blt_r<34> a_blt_r<33> a_blt_r<32> A_BM<24> a_dclk_n_r<8> a_dclk_n_r<9> a_dclk_p_r<8> a_dclk_p_r<9> A_DOUT<24> A_DIN<24> a_rclk_n_r<8> a_rclk_n_r<9> a_rclk_p_r<8> a_rclk_p_r<9> a_tieh<24> a_wclk_n_r<8> a_wclk_n_r<9> a_wclk_p_r<8> a_wclk_p_r<9> b_addr_dec_r<3> b_addr_dec_r<2> b_addr_dec_r<1> b_addr_dec_r<0> B_BIST_BM<24> B_BIST_DIN<24> B_BIST_EN b_blc_r<35> b_blc_r<34> b_blc_r<33> b_blc_r<32> b_blt_r<35> b_blt_r<34> b_blt_r<33> b_blt_r<32> B_BM<24> b_dclk_n_r<8> b_dclk_n_r<9> b_dclk_p_r<8> b_dclk_p_r<9> B_DOUT<24> B_DIN<24> b_rclk_n_r<8> b_rclk_n_r<9> b_rclk_p_r<8> b_rclk_p_r<9> b_tieh<24> b_wclk_n_r<8> b_wclk_n_r<9> b_wclk_p_r<8> b_wclk_p_r<9> VDD! VSS! / RM_IHPSG13_1024x32_c2_2P_COLCTRL2 +XCOLCTRL<23> a_addr_dec_r<3> a_addr_dec_r<2> a_addr_dec_r<1> a_addr_dec_r<0> A_BIST_BM<23> A_BIST_DIN<23> A_BIST_EN a_blc_r<31> a_blc_r<30> a_blc_r<29> a_blc_r<28> a_blt_r<31> a_blt_r<30> a_blt_r<29> a_blt_r<28> A_BM<23> a_dclk_n_r<7> a_dclk_n_r<8> a_dclk_p_r<7> a_dclk_p_r<8> A_DOUT<23> A_DIN<23> a_rclk_n_r<7> a_rclk_n_r<8> a_rclk_p_r<7> a_rclk_p_r<8> a_tieh<23> a_wclk_n_r<7> a_wclk_n_r<8> a_wclk_p_r<7> a_wclk_p_r<8> b_addr_dec_r<3> b_addr_dec_r<2> b_addr_dec_r<1> b_addr_dec_r<0> B_BIST_BM<23> B_BIST_DIN<23> B_BIST_EN b_blc_r<31> b_blc_r<30> b_blc_r<29> b_blc_r<28> b_blt_r<31> b_blt_r<30> b_blt_r<29> b_blt_r<28> B_BM<23> b_dclk_n_r<7> b_dclk_n_r<8> b_dclk_p_r<7> b_dclk_p_r<8> B_DOUT<23> B_DIN<23> b_rclk_n_r<7> b_rclk_n_r<8> b_rclk_p_r<7> b_rclk_p_r<8> b_tieh<23> b_wclk_n_r<7> b_wclk_n_r<8> b_wclk_p_r<7> b_wclk_p_r<8> VDD! VSS! / RM_IHPSG13_1024x32_c2_2P_COLCTRL2 +XCOLCTRL<22> a_addr_dec_r<3> a_addr_dec_r<2> a_addr_dec_r<1> a_addr_dec_r<0> A_BIST_BM<22> A_BIST_DIN<22> A_BIST_EN a_blc_r<27> a_blc_r<26> a_blc_r<25> a_blc_r<24> a_blt_r<27> a_blt_r<26> a_blt_r<25> a_blt_r<24> A_BM<22> a_dclk_n_r<6> a_dclk_n_r<7> a_dclk_p_r<6> a_dclk_p_r<7> A_DOUT<22> A_DIN<22> a_rclk_n_r<6> a_rclk_n_r<7> a_rclk_p_r<6> a_rclk_p_r<7> a_tieh<22> a_wclk_n_r<6> a_wclk_n_r<7> a_wclk_p_r<6> a_wclk_p_r<7> b_addr_dec_r<3> b_addr_dec_r<2> b_addr_dec_r<1> b_addr_dec_r<0> B_BIST_BM<22> B_BIST_DIN<22> B_BIST_EN b_blc_r<27> b_blc_r<26> b_blc_r<25> b_blc_r<24> b_blt_r<27> b_blt_r<26> b_blt_r<25> b_blt_r<24> B_BM<22> b_dclk_n_r<6> b_dclk_n_r<7> b_dclk_p_r<6> b_dclk_p_r<7> B_DOUT<22> B_DIN<22> b_rclk_n_r<6> b_rclk_n_r<7> b_rclk_p_r<6> b_rclk_p_r<7> b_tieh<22> b_wclk_n_r<6> b_wclk_n_r<7> b_wclk_p_r<6> b_wclk_p_r<7> VDD! VSS! / RM_IHPSG13_1024x32_c2_2P_COLCTRL2 +XCOLCTRL<21> a_addr_dec_r<3> a_addr_dec_r<2> a_addr_dec_r<1> a_addr_dec_r<0> A_BIST_BM<21> A_BIST_DIN<21> A_BIST_EN a_blc_r<23> a_blc_r<22> a_blc_r<21> a_blc_r<20> a_blt_r<23> a_blt_r<22> a_blt_r<21> a_blt_r<20> A_BM<21> a_dclk_n_r<5> a_dclk_n_r<6> a_dclk_p_r<5> a_dclk_p_r<6> A_DOUT<21> A_DIN<21> a_rclk_n_r<5> a_rclk_n_r<6> a_rclk_p_r<5> a_rclk_p_r<6> a_tieh<21> a_wclk_n_r<5> a_wclk_n_r<6> a_wclk_p_r<5> a_wclk_p_r<6> b_addr_dec_r<3> b_addr_dec_r<2> b_addr_dec_r<1> b_addr_dec_r<0> B_BIST_BM<21> B_BIST_DIN<21> B_BIST_EN b_blc_r<23> b_blc_r<22> b_blc_r<21> b_blc_r<20> b_blt_r<23> b_blt_r<22> b_blt_r<21> b_blt_r<20> B_BM<21> b_dclk_n_r<5> b_dclk_n_r<6> b_dclk_p_r<5> b_dclk_p_r<6> B_DOUT<21> B_DIN<21> b_rclk_n_r<5> b_rclk_n_r<6> b_rclk_p_r<5> b_rclk_p_r<6> b_tieh<21> b_wclk_n_r<5> b_wclk_n_r<6> b_wclk_p_r<5> b_wclk_p_r<6> VDD! VSS! / RM_IHPSG13_1024x32_c2_2P_COLCTRL2 +XCOLCTRL<20> a_addr_dec_r<3> a_addr_dec_r<2> a_addr_dec_r<1> a_addr_dec_r<0> A_BIST_BM<20> A_BIST_DIN<20> A_BIST_EN a_blc_r<19> a_blc_r<18> a_blc_r<17> a_blc_r<16> a_blt_r<19> a_blt_r<18> a_blt_r<17> a_blt_r<16> A_BM<20> a_dclk_n_r<4> a_dclk_n_r<5> a_dclk_p_r<4> a_dclk_p_r<5> A_DOUT<20> A_DIN<20> a_rclk_n_r<4> a_rclk_n_r<5> a_rclk_p_r<4> a_rclk_p_r<5> a_tieh<20> a_wclk_n_r<4> a_wclk_n_r<5> a_wclk_p_r<4> a_wclk_p_r<5> b_addr_dec_r<3> b_addr_dec_r<2> b_addr_dec_r<1> b_addr_dec_r<0> B_BIST_BM<20> B_BIST_DIN<20> B_BIST_EN b_blc_r<19> b_blc_r<18> b_blc_r<17> b_blc_r<16> b_blt_r<19> b_blt_r<18> b_blt_r<17> b_blt_r<16> B_BM<20> b_dclk_n_r<4> b_dclk_n_r<5> b_dclk_p_r<4> b_dclk_p_r<5> B_DOUT<20> B_DIN<20> b_rclk_n_r<4> b_rclk_n_r<5> b_rclk_p_r<4> b_rclk_p_r<5> b_tieh<20> b_wclk_n_r<4> b_wclk_n_r<5> b_wclk_p_r<4> b_wclk_p_r<5> VDD! VSS! / RM_IHPSG13_1024x32_c2_2P_COLCTRL2 +XCOLCTRL<19> a_addr_dec_r<3> a_addr_dec_r<2> a_addr_dec_r<1> a_addr_dec_r<0> A_BIST_BM<19> A_BIST_DIN<19> A_BIST_EN a_blc_r<15> a_blc_r<14> a_blc_r<13> a_blc_r<12> a_blt_r<15> a_blt_r<14> a_blt_r<13> a_blt_r<12> A_BM<19> a_dclk_n_r<3> a_dclk_n_r<4> a_dclk_p_r<3> a_dclk_p_r<4> A_DOUT<19> A_DIN<19> a_rclk_n_r<3> a_rclk_n_r<4> a_rclk_p_r<3> a_rclk_p_r<4> a_tieh<19> a_wclk_n_r<3> a_wclk_n_r<4> a_wclk_p_r<3> a_wclk_p_r<4> b_addr_dec_r<3> b_addr_dec_r<2> b_addr_dec_r<1> b_addr_dec_r<0> B_BIST_BM<19> B_BIST_DIN<19> B_BIST_EN b_blc_r<15> b_blc_r<14> b_blc_r<13> b_blc_r<12> b_blt_r<15> b_blt_r<14> b_blt_r<13> b_blt_r<12> B_BM<19> b_dclk_n_r<3> b_dclk_n_r<4> b_dclk_p_r<3> b_dclk_p_r<4> B_DOUT<19> B_DIN<19> b_rclk_n_r<3> b_rclk_n_r<4> b_rclk_p_r<3> b_rclk_p_r<4> b_tieh<19> b_wclk_n_r<3> b_wclk_n_r<4> b_wclk_p_r<3> b_wclk_p_r<4> VDD! VSS! / RM_IHPSG13_1024x32_c2_2P_COLCTRL2 +XCOLCTRL<18> a_addr_dec_r<3> a_addr_dec_r<2> a_addr_dec_r<1> a_addr_dec_r<0> A_BIST_BM<18> A_BIST_DIN<18> A_BIST_EN a_blc_r<11> a_blc_r<10> a_blc_r<9> a_blc_r<8> a_blt_r<11> a_blt_r<10> a_blt_r<9> a_blt_r<8> A_BM<18> a_dclk_n_r<2> a_dclk_n_r<3> a_dclk_p_r<2> a_dclk_p_r<3> A_DOUT<18> A_DIN<18> a_rclk_n_r<2> a_rclk_n_r<3> a_rclk_p_r<2> a_rclk_p_r<3> a_tieh<18> a_wclk_n_r<2> a_wclk_n_r<3> a_wclk_p_r<2> a_wclk_p_r<3> b_addr_dec_r<3> b_addr_dec_r<2> b_addr_dec_r<1> b_addr_dec_r<0> B_BIST_BM<18> B_BIST_DIN<18> B_BIST_EN b_blc_r<11> b_blc_r<10> b_blc_r<9> b_blc_r<8> b_blt_r<11> b_blt_r<10> b_blt_r<9> b_blt_r<8> B_BM<18> b_dclk_n_r<2> b_dclk_n_r<3> b_dclk_p_r<2> b_dclk_p_r<3> B_DOUT<18> B_DIN<18> b_rclk_n_r<2> b_rclk_n_r<3> b_rclk_p_r<2> b_rclk_p_r<3> b_tieh<18> b_wclk_n_r<2> b_wclk_n_r<3> b_wclk_p_r<2> b_wclk_p_r<3> VDD! VSS! / RM_IHPSG13_1024x32_c2_2P_COLCTRL2 +XCOLCTRL<17> a_addr_dec_r<3> a_addr_dec_r<2> a_addr_dec_r<1> a_addr_dec_r<0> A_BIST_BM<17> A_BIST_DIN<17> A_BIST_EN a_blc_r<7> a_blc_r<6> a_blc_r<5> a_blc_r<4> a_blt_r<7> a_blt_r<6> a_blt_r<5> a_blt_r<4> A_BM<17> a_dclk_n_r<1> a_dclk_n_r<2> a_dclk_p_r<1> a_dclk_p_r<2> A_DOUT<17> A_DIN<17> a_rclk_n_r<1> a_rclk_n_r<2> a_rclk_p_r<1> a_rclk_p_r<2> a_tieh<17> a_wclk_n_r<1> a_wclk_n_r<2> a_wclk_p_r<1> a_wclk_p_r<2> b_addr_dec_r<3> b_addr_dec_r<2> b_addr_dec_r<1> b_addr_dec_r<0> B_BIST_BM<17> B_BIST_DIN<17> B_BIST_EN b_blc_r<7> b_blc_r<6> b_blc_r<5> b_blc_r<4> b_blt_r<7> b_blt_r<6> b_blt_r<5> b_blt_r<4> B_BM<17> b_dclk_n_r<1> b_dclk_n_r<2> b_dclk_p_r<1> b_dclk_p_r<2> B_DOUT<17> B_DIN<17> b_rclk_n_r<1> b_rclk_n_r<2> b_rclk_p_r<1> b_rclk_p_r<2> b_tieh<17> b_wclk_n_r<1> b_wclk_n_r<2> b_wclk_p_r<1> b_wclk_p_r<2> VDD! VSS! / RM_IHPSG13_1024x32_c2_2P_COLCTRL2 +XCOLCTRL<16> a_addr_dec_r<3> a_addr_dec_r<2> a_addr_dec_r<1> a_addr_dec_r<0> A_BIST_BM<16> A_BIST_DIN<16> A_BIST_EN a_blc_r<3> a_blc_r<2> a_blc_r<1> a_blc_r<0> a_blt_r<3> a_blt_r<2> a_blt_r<1> a_blt_r<0> A_BM<16> a_dclk_n_r<0> a_dclk_n_r<1> a_dclk_p_r<0> a_dclk_p_r<1> A_DOUT<16> A_DIN<16> a_rclk_n_r<0> a_rclk_n_r<1> a_rclk_p_r<0> a_rclk_p_r<1> a_tieh<16> a_wclk_n_r<0> a_wclk_n_r<1> a_wclk_p_r<0> a_wclk_p_r<1> b_addr_dec_r<3> b_addr_dec_r<2> b_addr_dec_r<1> b_addr_dec_r<0> B_BIST_BM<16> B_BIST_DIN<16> B_BIST_EN b_blc_r<3> b_blc_r<2> b_blc_r<1> b_blc_r<0> b_blt_r<3> b_blt_r<2> b_blt_r<1> b_blt_r<0> B_BM<16> b_dclk_n_r<0> b_dclk_n_r<1> b_dclk_p_r<0> b_dclk_p_r<1> B_DOUT<16> B_DIN<16> b_rclk_n_r<0> b_rclk_n_r<1> b_rclk_p_r<0> b_rclk_p_r<1> b_tieh<16> b_wclk_n_r<0> b_wclk_n_r<1> b_wclk_p_r<0> b_wclk_p_r<1> VDD! VSS! / RM_IHPSG13_1024x32_c2_2P_COLCTRL2 +XCOLCTRL<15> a_addr_dec_l<3> a_addr_dec_l<2> a_addr_dec_l<1> a_addr_dec_l<0> A_BIST_BM<0> A_BIST_DIN<0> A_BIST_EN a_blc_l<63> a_blc_l<62> a_blc_l<61> a_blc_l<60> a_blt_l<63> a_blt_l<62> a_blt_l<61> a_blt_l<60> A_BM<0> a_dclk_n_l<15> a_dclk_n_l<16> a_dclk_p_l<15> a_dclk_p_l<16> A_DOUT<0> A_DIN<0> a_rclk_n_l<15> a_rclk_n_l<16> a_rclk_p_l<15> a_rclk_p_l<16> a_tieh<0> a_wclk_n_l<15> a_wclk_n_l<16> a_wclk_p_l<15> a_wclk_p_l<16> b_addr_dec_l<3> b_addr_dec_l<2> b_addr_dec_l<1> b_addr_dec_l<0> B_BIST_BM<0> B_BIST_DIN<0> B_BIST_EN b_blc_l<63> b_blc_l<62> b_blc_l<61> b_blc_l<60> b_blt_l<63> b_blt_l<62> b_blt_l<61> b_blt_l<60> B_BM<0> b_dclk_n_l<15> b_dclk_n_l<16> b_dclk_p_l<15> b_dclk_p_l<16> B_DOUT<0> B_DIN<0> b_rclk_n_l<15> b_rclk_n_l<16> b_rclk_p_l<15> b_rclk_p_l<16> b_tieh<0> b_wclk_n_l<15> b_wclk_n_l<16> b_wclk_p_l<15> b_wclk_p_l<16> VDD! VSS! / RM_IHPSG13_1024x32_c2_2P_COLCTRL2 +XCOLCTRL<14> a_addr_dec_l<3> a_addr_dec_l<2> a_addr_dec_l<1> a_addr_dec_l<0> A_BIST_BM<1> A_BIST_DIN<1> A_BIST_EN a_blc_l<59> a_blc_l<58> a_blc_l<57> a_blc_l<56> a_blt_l<59> a_blt_l<58> a_blt_l<57> a_blt_l<56> A_BM<1> a_dclk_n_l<14> a_dclk_n_l<15> a_dclk_p_l<14> a_dclk_p_l<15> A_DOUT<1> A_DIN<1> a_rclk_n_l<14> a_rclk_n_l<15> a_rclk_p_l<14> a_rclk_p_l<15> a_tieh<1> a_wclk_n_l<14> a_wclk_n_l<15> a_wclk_p_l<14> a_wclk_p_l<15> b_addr_dec_l<3> b_addr_dec_l<2> b_addr_dec_l<1> b_addr_dec_l<0> B_BIST_BM<1> B_BIST_DIN<1> B_BIST_EN b_blc_l<59> b_blc_l<58> b_blc_l<57> b_blc_l<56> b_blt_l<59> b_blt_l<58> b_blt_l<57> b_blt_l<56> B_BM<1> b_dclk_n_l<14> b_dclk_n_l<15> b_dclk_p_l<14> b_dclk_p_l<15> B_DOUT<1> B_DIN<1> b_rclk_n_l<14> b_rclk_n_l<15> b_rclk_p_l<14> b_rclk_p_l<15> b_tieh<1> b_wclk_n_l<14> b_wclk_n_l<15> b_wclk_p_l<14> b_wclk_p_l<15> VDD! VSS! / RM_IHPSG13_1024x32_c2_2P_COLCTRL2 +XCOLCTRL<13> a_addr_dec_l<3> a_addr_dec_l<2> a_addr_dec_l<1> a_addr_dec_l<0> A_BIST_BM<2> A_BIST_DIN<2> A_BIST_EN a_blc_l<55> a_blc_l<54> a_blc_l<53> a_blc_l<52> a_blt_l<55> a_blt_l<54> a_blt_l<53> a_blt_l<52> A_BM<2> a_dclk_n_l<13> a_dclk_n_l<14> a_dclk_p_l<13> a_dclk_p_l<14> A_DOUT<2> A_DIN<2> a_rclk_n_l<13> a_rclk_n_l<14> a_rclk_p_l<13> a_rclk_p_l<14> a_tieh<2> a_wclk_n_l<13> a_wclk_n_l<14> a_wclk_p_l<13> a_wclk_p_l<14> b_addr_dec_l<3> b_addr_dec_l<2> b_addr_dec_l<1> b_addr_dec_l<0> B_BIST_BM<2> B_BIST_DIN<2> B_BIST_EN b_blc_l<55> b_blc_l<54> b_blc_l<53> b_blc_l<52> b_blt_l<55> b_blt_l<54> b_blt_l<53> b_blt_l<52> B_BM<2> b_dclk_n_l<13> b_dclk_n_l<14> b_dclk_p_l<13> b_dclk_p_l<14> B_DOUT<2> B_DIN<2> b_rclk_n_l<13> b_rclk_n_l<14> b_rclk_p_l<13> b_rclk_p_l<14> b_tieh<2> b_wclk_n_l<13> b_wclk_n_l<14> b_wclk_p_l<13> b_wclk_p_l<14> VDD! VSS! / RM_IHPSG13_1024x32_c2_2P_COLCTRL2 +XCOLCTRL<12> a_addr_dec_l<3> a_addr_dec_l<2> a_addr_dec_l<1> a_addr_dec_l<0> A_BIST_BM<3> A_BIST_DIN<3> A_BIST_EN a_blc_l<51> a_blc_l<50> a_blc_l<49> a_blc_l<48> a_blt_l<51> a_blt_l<50> a_blt_l<49> a_blt_l<48> A_BM<3> a_dclk_n_l<12> a_dclk_n_l<13> a_dclk_p_l<12> a_dclk_p_l<13> A_DOUT<3> A_DIN<3> a_rclk_n_l<12> a_rclk_n_l<13> a_rclk_p_l<12> a_rclk_p_l<13> a_tieh<3> a_wclk_n_l<12> a_wclk_n_l<13> a_wclk_p_l<12> a_wclk_p_l<13> b_addr_dec_l<3> b_addr_dec_l<2> b_addr_dec_l<1> b_addr_dec_l<0> B_BIST_BM<3> B_BIST_DIN<3> B_BIST_EN b_blc_l<51> b_blc_l<50> b_blc_l<49> b_blc_l<48> b_blt_l<51> b_blt_l<50> b_blt_l<49> b_blt_l<48> B_BM<3> b_dclk_n_l<12> b_dclk_n_l<13> b_dclk_p_l<12> b_dclk_p_l<13> B_DOUT<3> B_DIN<3> b_rclk_n_l<12> b_rclk_n_l<13> b_rclk_p_l<12> b_rclk_p_l<13> b_tieh<3> b_wclk_n_l<12> b_wclk_n_l<13> b_wclk_p_l<12> b_wclk_p_l<13> VDD! VSS! / RM_IHPSG13_1024x32_c2_2P_COLCTRL2 +XCOLCTRL<11> a_addr_dec_l<3> a_addr_dec_l<2> a_addr_dec_l<1> a_addr_dec_l<0> A_BIST_BM<4> A_BIST_DIN<4> A_BIST_EN a_blc_l<47> a_blc_l<46> a_blc_l<45> a_blc_l<44> a_blt_l<47> a_blt_l<46> a_blt_l<45> a_blt_l<44> A_BM<4> a_dclk_n_l<11> a_dclk_n_l<12> a_dclk_p_l<11> a_dclk_p_l<12> A_DOUT<4> A_DIN<4> a_rclk_n_l<11> a_rclk_n_l<12> a_rclk_p_l<11> a_rclk_p_l<12> a_tieh<4> a_wclk_n_l<11> a_wclk_n_l<12> a_wclk_p_l<11> a_wclk_p_l<12> b_addr_dec_l<3> b_addr_dec_l<2> b_addr_dec_l<1> b_addr_dec_l<0> B_BIST_BM<4> B_BIST_DIN<4> B_BIST_EN b_blc_l<47> b_blc_l<46> b_blc_l<45> b_blc_l<44> b_blt_l<47> b_blt_l<46> b_blt_l<45> b_blt_l<44> B_BM<4> b_dclk_n_l<11> b_dclk_n_l<12> b_dclk_p_l<11> b_dclk_p_l<12> B_DOUT<4> B_DIN<4> b_rclk_n_l<11> b_rclk_n_l<12> b_rclk_p_l<11> b_rclk_p_l<12> b_tieh<4> b_wclk_n_l<11> b_wclk_n_l<12> b_wclk_p_l<11> b_wclk_p_l<12> VDD! VSS! / RM_IHPSG13_1024x32_c2_2P_COLCTRL2 +XCOLCTRL<10> a_addr_dec_l<3> a_addr_dec_l<2> a_addr_dec_l<1> a_addr_dec_l<0> A_BIST_BM<5> A_BIST_DIN<5> A_BIST_EN a_blc_l<43> a_blc_l<42> a_blc_l<41> a_blc_l<40> a_blt_l<43> a_blt_l<42> a_blt_l<41> a_blt_l<40> A_BM<5> a_dclk_n_l<10> a_dclk_n_l<11> a_dclk_p_l<10> a_dclk_p_l<11> A_DOUT<5> A_DIN<5> a_rclk_n_l<10> a_rclk_n_l<11> a_rclk_p_l<10> a_rclk_p_l<11> a_tieh<5> a_wclk_n_l<10> a_wclk_n_l<11> a_wclk_p_l<10> a_wclk_p_l<11> b_addr_dec_l<3> b_addr_dec_l<2> b_addr_dec_l<1> b_addr_dec_l<0> B_BIST_BM<5> B_BIST_DIN<5> B_BIST_EN b_blc_l<43> b_blc_l<42> b_blc_l<41> b_blc_l<40> b_blt_l<43> b_blt_l<42> b_blt_l<41> b_blt_l<40> B_BM<5> b_dclk_n_l<10> b_dclk_n_l<11> b_dclk_p_l<10> b_dclk_p_l<11> B_DOUT<5> B_DIN<5> b_rclk_n_l<10> b_rclk_n_l<11> b_rclk_p_l<10> b_rclk_p_l<11> b_tieh<5> b_wclk_n_l<10> b_wclk_n_l<11> b_wclk_p_l<10> b_wclk_p_l<11> VDD! VSS! / RM_IHPSG13_1024x32_c2_2P_COLCTRL2 +XCOLCTRL<9> a_addr_dec_l<3> a_addr_dec_l<2> a_addr_dec_l<1> a_addr_dec_l<0> A_BIST_BM<6> A_BIST_DIN<6> A_BIST_EN a_blc_l<39> a_blc_l<38> a_blc_l<37> a_blc_l<36> a_blt_l<39> a_blt_l<38> a_blt_l<37> a_blt_l<36> A_BM<6> a_dclk_n_l<9> a_dclk_n_l<10> a_dclk_p_l<9> a_dclk_p_l<10> A_DOUT<6> A_DIN<6> a_rclk_n_l<9> a_rclk_n_l<10> a_rclk_p_l<9> a_rclk_p_l<10> a_tieh<6> a_wclk_n_l<9> a_wclk_n_l<10> a_wclk_p_l<9> a_wclk_p_l<10> b_addr_dec_l<3> b_addr_dec_l<2> b_addr_dec_l<1> b_addr_dec_l<0> B_BIST_BM<6> B_BIST_DIN<6> B_BIST_EN b_blc_l<39> b_blc_l<38> b_blc_l<37> b_blc_l<36> b_blt_l<39> b_blt_l<38> b_blt_l<37> b_blt_l<36> B_BM<6> b_dclk_n_l<9> b_dclk_n_l<10> b_dclk_p_l<9> b_dclk_p_l<10> B_DOUT<6> B_DIN<6> b_rclk_n_l<9> b_rclk_n_l<10> b_rclk_p_l<9> b_rclk_p_l<10> b_tieh<6> b_wclk_n_l<9> b_wclk_n_l<10> b_wclk_p_l<9> b_wclk_p_l<10> VDD! VSS! / RM_IHPSG13_1024x32_c2_2P_COLCTRL2 +XCOLCTRL<8> a_addr_dec_l<3> a_addr_dec_l<2> a_addr_dec_l<1> a_addr_dec_l<0> A_BIST_BM<7> A_BIST_DIN<7> A_BIST_EN a_blc_l<35> a_blc_l<34> a_blc_l<33> a_blc_l<32> a_blt_l<35> a_blt_l<34> a_blt_l<33> a_blt_l<32> A_BM<7> a_dclk_n_l<8> a_dclk_n_l<9> a_dclk_p_l<8> a_dclk_p_l<9> A_DOUT<7> A_DIN<7> a_rclk_n_l<8> a_rclk_n_l<9> a_rclk_p_l<8> a_rclk_p_l<9> a_tieh<7> a_wclk_n_l<8> a_wclk_n_l<9> a_wclk_p_l<8> a_wclk_p_l<9> b_addr_dec_l<3> b_addr_dec_l<2> b_addr_dec_l<1> b_addr_dec_l<0> B_BIST_BM<7> B_BIST_DIN<7> B_BIST_EN b_blc_l<35> b_blc_l<34> b_blc_l<33> b_blc_l<32> b_blt_l<35> b_blt_l<34> b_blt_l<33> b_blt_l<32> B_BM<7> b_dclk_n_l<8> b_dclk_n_l<9> b_dclk_p_l<8> b_dclk_p_l<9> B_DOUT<7> B_DIN<7> b_rclk_n_l<8> b_rclk_n_l<9> b_rclk_p_l<8> b_rclk_p_l<9> b_tieh<7> b_wclk_n_l<8> b_wclk_n_l<9> b_wclk_p_l<8> b_wclk_p_l<9> VDD! VSS! / RM_IHPSG13_1024x32_c2_2P_COLCTRL2 +XCOLCTRL<7> a_addr_dec_l<3> a_addr_dec_l<2> a_addr_dec_l<1> a_addr_dec_l<0> A_BIST_BM<8> A_BIST_DIN<8> A_BIST_EN a_blc_l<31> a_blc_l<30> a_blc_l<29> a_blc_l<28> a_blt_l<31> a_blt_l<30> a_blt_l<29> a_blt_l<28> A_BM<8> a_dclk_n_l<7> a_dclk_n_l<8> a_dclk_p_l<7> a_dclk_p_l<8> A_DOUT<8> A_DIN<8> a_rclk_n_l<7> a_rclk_n_l<8> a_rclk_p_l<7> a_rclk_p_l<8> a_tieh<8> a_wclk_n_l<7> a_wclk_n_l<8> a_wclk_p_l<7> a_wclk_p_l<8> b_addr_dec_l<3> b_addr_dec_l<2> b_addr_dec_l<1> b_addr_dec_l<0> B_BIST_BM<8> B_BIST_DIN<8> B_BIST_EN b_blc_l<31> b_blc_l<30> b_blc_l<29> b_blc_l<28> b_blt_l<31> b_blt_l<30> b_blt_l<29> b_blt_l<28> B_BM<8> b_dclk_n_l<7> b_dclk_n_l<8> b_dclk_p_l<7> b_dclk_p_l<8> B_DOUT<8> B_DIN<8> b_rclk_n_l<7> b_rclk_n_l<8> b_rclk_p_l<7> b_rclk_p_l<8> b_tieh<8> b_wclk_n_l<7> b_wclk_n_l<8> b_wclk_p_l<7> b_wclk_p_l<8> VDD! VSS! / RM_IHPSG13_1024x32_c2_2P_COLCTRL2 +XCOLCTRL<6> a_addr_dec_l<3> a_addr_dec_l<2> a_addr_dec_l<1> a_addr_dec_l<0> A_BIST_BM<9> A_BIST_DIN<9> A_BIST_EN a_blc_l<27> a_blc_l<26> a_blc_l<25> a_blc_l<24> a_blt_l<27> a_blt_l<26> a_blt_l<25> a_blt_l<24> A_BM<9> a_dclk_n_l<6> a_dclk_n_l<7> a_dclk_p_l<6> a_dclk_p_l<7> A_DOUT<9> A_DIN<9> a_rclk_n_l<6> a_rclk_n_l<7> a_rclk_p_l<6> a_rclk_p_l<7> a_tieh<9> a_wclk_n_l<6> a_wclk_n_l<7> a_wclk_p_l<6> a_wclk_p_l<7> b_addr_dec_l<3> b_addr_dec_l<2> b_addr_dec_l<1> b_addr_dec_l<0> B_BIST_BM<9> B_BIST_DIN<9> B_BIST_EN b_blc_l<27> b_blc_l<26> b_blc_l<25> b_blc_l<24> b_blt_l<27> b_blt_l<26> b_blt_l<25> b_blt_l<24> B_BM<9> b_dclk_n_l<6> b_dclk_n_l<7> b_dclk_p_l<6> b_dclk_p_l<7> B_DOUT<9> B_DIN<9> b_rclk_n_l<6> b_rclk_n_l<7> b_rclk_p_l<6> b_rclk_p_l<7> b_tieh<9> b_wclk_n_l<6> b_wclk_n_l<7> b_wclk_p_l<6> b_wclk_p_l<7> VDD! VSS! / RM_IHPSG13_1024x32_c2_2P_COLCTRL2 +XCOLCTRL<5> a_addr_dec_l<3> a_addr_dec_l<2> a_addr_dec_l<1> a_addr_dec_l<0> A_BIST_BM<10> A_BIST_DIN<10> A_BIST_EN a_blc_l<23> a_blc_l<22> a_blc_l<21> a_blc_l<20> a_blt_l<23> a_blt_l<22> a_blt_l<21> a_blt_l<20> A_BM<10> a_dclk_n_l<5> a_dclk_n_l<6> a_dclk_p_l<5> a_dclk_p_l<6> A_DOUT<10> A_DIN<10> a_rclk_n_l<5> a_rclk_n_l<6> a_rclk_p_l<5> a_rclk_p_l<6> a_tieh<10> a_wclk_n_l<5> a_wclk_n_l<6> a_wclk_p_l<5> a_wclk_p_l<6> b_addr_dec_l<3> b_addr_dec_l<2> b_addr_dec_l<1> b_addr_dec_l<0> B_BIST_BM<10> B_BIST_DIN<10> B_BIST_EN b_blc_l<23> b_blc_l<22> b_blc_l<21> b_blc_l<20> b_blt_l<23> b_blt_l<22> b_blt_l<21> b_blt_l<20> B_BM<10> b_dclk_n_l<5> b_dclk_n_l<6> b_dclk_p_l<5> b_dclk_p_l<6> B_DOUT<10> B_DIN<10> b_rclk_n_l<5> b_rclk_n_l<6> b_rclk_p_l<5> b_rclk_p_l<6> b_tieh<10> b_wclk_n_l<5> b_wclk_n_l<6> b_wclk_p_l<5> b_wclk_p_l<6> VDD! VSS! / RM_IHPSG13_1024x32_c2_2P_COLCTRL2 +XCOLCTRL<4> a_addr_dec_l<3> a_addr_dec_l<2> a_addr_dec_l<1> a_addr_dec_l<0> A_BIST_BM<11> A_BIST_DIN<11> A_BIST_EN a_blc_l<19> a_blc_l<18> a_blc_l<17> a_blc_l<16> a_blt_l<19> a_blt_l<18> a_blt_l<17> a_blt_l<16> A_BM<11> a_dclk_n_l<4> a_dclk_n_l<5> a_dclk_p_l<4> a_dclk_p_l<5> A_DOUT<11> A_DIN<11> a_rclk_n_l<4> a_rclk_n_l<5> a_rclk_p_l<4> a_rclk_p_l<5> a_tieh<11> a_wclk_n_l<4> a_wclk_n_l<5> a_wclk_p_l<4> a_wclk_p_l<5> b_addr_dec_l<3> b_addr_dec_l<2> b_addr_dec_l<1> b_addr_dec_l<0> B_BIST_BM<11> B_BIST_DIN<11> B_BIST_EN b_blc_l<19> b_blc_l<18> b_blc_l<17> b_blc_l<16> b_blt_l<19> b_blt_l<18> b_blt_l<17> b_blt_l<16> B_BM<11> b_dclk_n_l<4> b_dclk_n_l<5> b_dclk_p_l<4> b_dclk_p_l<5> B_DOUT<11> B_DIN<11> b_rclk_n_l<4> b_rclk_n_l<5> b_rclk_p_l<4> b_rclk_p_l<5> b_tieh<11> b_wclk_n_l<4> b_wclk_n_l<5> b_wclk_p_l<4> b_wclk_p_l<5> VDD! VSS! / RM_IHPSG13_1024x32_c2_2P_COLCTRL2 +XCOLCTRL<3> a_addr_dec_l<3> a_addr_dec_l<2> a_addr_dec_l<1> a_addr_dec_l<0> A_BIST_BM<12> A_BIST_DIN<12> A_BIST_EN a_blc_l<15> a_blc_l<14> a_blc_l<13> a_blc_l<12> a_blt_l<15> a_blt_l<14> a_blt_l<13> a_blt_l<12> A_BM<12> a_dclk_n_l<3> a_dclk_n_l<4> a_dclk_p_l<3> a_dclk_p_l<4> A_DOUT<12> A_DIN<12> a_rclk_n_l<3> a_rclk_n_l<4> a_rclk_p_l<3> a_rclk_p_l<4> a_tieh<12> a_wclk_n_l<3> a_wclk_n_l<4> a_wclk_p_l<3> a_wclk_p_l<4> b_addr_dec_l<3> b_addr_dec_l<2> b_addr_dec_l<1> b_addr_dec_l<0> B_BIST_BM<12> B_BIST_DIN<12> B_BIST_EN b_blc_l<15> b_blc_l<14> b_blc_l<13> b_blc_l<12> b_blt_l<15> b_blt_l<14> b_blt_l<13> b_blt_l<12> B_BM<12> b_dclk_n_l<3> b_dclk_n_l<4> b_dclk_p_l<3> b_dclk_p_l<4> B_DOUT<12> B_DIN<12> b_rclk_n_l<3> b_rclk_n_l<4> b_rclk_p_l<3> b_rclk_p_l<4> b_tieh<12> b_wclk_n_l<3> b_wclk_n_l<4> b_wclk_p_l<3> b_wclk_p_l<4> VDD! VSS! / RM_IHPSG13_1024x32_c2_2P_COLCTRL2 +XCOLCTRL<2> a_addr_dec_l<3> a_addr_dec_l<2> a_addr_dec_l<1> a_addr_dec_l<0> A_BIST_BM<13> A_BIST_DIN<13> A_BIST_EN a_blc_l<11> a_blc_l<10> a_blc_l<9> a_blc_l<8> a_blt_l<11> a_blt_l<10> a_blt_l<9> a_blt_l<8> A_BM<13> a_dclk_n_l<2> a_dclk_n_l<3> a_dclk_p_l<2> a_dclk_p_l<3> A_DOUT<13> A_DIN<13> a_rclk_n_l<2> a_rclk_n_l<3> a_rclk_p_l<2> a_rclk_p_l<3> a_tieh<13> a_wclk_n_l<2> a_wclk_n_l<3> a_wclk_p_l<2> a_wclk_p_l<3> b_addr_dec_l<3> b_addr_dec_l<2> b_addr_dec_l<1> b_addr_dec_l<0> B_BIST_BM<13> B_BIST_DIN<13> B_BIST_EN b_blc_l<11> b_blc_l<10> b_blc_l<9> b_blc_l<8> b_blt_l<11> b_blt_l<10> b_blt_l<9> b_blt_l<8> B_BM<13> b_dclk_n_l<2> b_dclk_n_l<3> b_dclk_p_l<2> b_dclk_p_l<3> B_DOUT<13> B_DIN<13> b_rclk_n_l<2> b_rclk_n_l<3> b_rclk_p_l<2> b_rclk_p_l<3> b_tieh<13> b_wclk_n_l<2> b_wclk_n_l<3> b_wclk_p_l<2> b_wclk_p_l<3> VDD! VSS! / RM_IHPSG13_1024x32_c2_2P_COLCTRL2 +XCOLCTRL<1> a_addr_dec_l<3> a_addr_dec_l<2> a_addr_dec_l<1> a_addr_dec_l<0> A_BIST_BM<14> A_BIST_DIN<14> A_BIST_EN a_blc_l<7> a_blc_l<6> a_blc_l<5> a_blc_l<4> a_blt_l<7> a_blt_l<6> a_blt_l<5> a_blt_l<4> A_BM<14> a_dclk_n_l<1> a_dclk_n_l<2> a_dclk_p_l<1> a_dclk_p_l<2> A_DOUT<14> A_DIN<14> a_rclk_n_l<1> a_rclk_n_l<2> a_rclk_p_l<1> a_rclk_p_l<2> a_tieh<14> a_wclk_n_l<1> a_wclk_n_l<2> a_wclk_p_l<1> a_wclk_p_l<2> b_addr_dec_l<3> b_addr_dec_l<2> b_addr_dec_l<1> b_addr_dec_l<0> B_BIST_BM<14> B_BIST_DIN<14> B_BIST_EN b_blc_l<7> b_blc_l<6> b_blc_l<5> b_blc_l<4> b_blt_l<7> b_blt_l<6> b_blt_l<5> b_blt_l<4> B_BM<14> b_dclk_n_l<1> b_dclk_n_l<2> b_dclk_p_l<1> b_dclk_p_l<2> B_DOUT<14> B_DIN<14> b_rclk_n_l<1> b_rclk_n_l<2> b_rclk_p_l<1> b_rclk_p_l<2> b_tieh<14> b_wclk_n_l<1> b_wclk_n_l<2> b_wclk_p_l<1> b_wclk_p_l<2> VDD! VSS! / RM_IHPSG13_1024x32_c2_2P_COLCTRL2 +XCOLCTRL<0> a_addr_dec_l<3> a_addr_dec_l<2> a_addr_dec_l<1> a_addr_dec_l<0> A_BIST_BM<15> A_BIST_DIN<15> A_BIST_EN a_blc_l<3> a_blc_l<2> a_blc_l<1> a_blc_l<0> a_blt_l<3> a_blt_l<2> a_blt_l<1> a_blt_l<0> A_BM<15> a_dclk_n_l<0> a_dclk_n_l<1> a_dclk_p_l<0> a_dclk_p_l<1> A_DOUT<15> A_DIN<15> a_rclk_n_l<0> a_rclk_n_l<1> a_rclk_p_l<0> a_rclk_p_l<1> a_tieh<15> a_wclk_n_l<0> a_wclk_n_l<1> a_wclk_p_l<0> a_wclk_p_l<1> b_addr_dec_l<3> b_addr_dec_l<2> b_addr_dec_l<1> b_addr_dec_l<0> B_BIST_BM<15> B_BIST_DIN<15> B_BIST_EN b_blc_l<3> b_blc_l<2> b_blc_l<1> b_blc_l<0> b_blt_l<3> b_blt_l<2> b_blt_l<1> b_blt_l<0> B_BM<15> b_dclk_n_l<0> b_dclk_n_l<1> b_dclk_p_l<0> b_dclk_p_l<1> B_DOUT<15> B_DIN<15> b_rclk_n_l<0> b_rclk_n_l<1> b_rclk_p_l<0> b_rclk_p_l<1> b_tieh<15> b_wclk_n_l<0> b_wclk_n_l<1> b_wclk_p_l<0> b_wclk_p_l<1> VDD! VSS! / RM_IHPSG13_1024x32_c2_2P_COLCTRL2 + + +XDRVFILL4<1> VDD! VSS! / RM_IHPSG13_1024x32_c2_2P_COLDRV13_FILL4 +XDRVFILL4<2> VDD! VSS! / RM_IHPSG13_1024x32_c2_2P_COLDRV13_FILL4 +XDRVFILL4<3> VDD! VSS! / RM_IHPSG13_1024x32_c2_2P_COLDRV13_FILL4 +XDRVFILL4<4> VDD! VSS! / RM_IHPSG13_1024x32_c2_2P_COLDRV13_FILL4 +XDRVFILL4<5> VDD! VSS! / RM_IHPSG13_1024x32_c2_2P_COLDRV13_FILL4 +XDRVFILL4<6> VDD! VSS! / RM_IHPSG13_1024x32_c2_2P_COLDRV13_FILL4 +XCOLFILL4<1> VDD! VSS! / RM_IHPSG13_1024x32_c2_2P_COLDRV13_FILL4C2 +XCOLFILL4<2> VDD! VSS! / RM_IHPSG13_1024x32_c2_2P_COLDRV13_FILL4C2 +XCOLFILL4<3> VDD! VSS! / RM_IHPSG13_1024x32_c2_2P_COLDRV13_FILL4C2 +XCOLFILL4<4> VDD! VSS! / RM_IHPSG13_1024x32_c2_2P_COLDRV13_FILL4C2 +XCOLFILL4<5> VDD! VSS! / RM_IHPSG13_1024x32_c2_2P_COLDRV13_FILL4C2 +XCOLFILL4<6> VDD! VSS! / RM_IHPSG13_1024x32_c2_2P_COLDRV13_FILL4C2 +XCOLFILL4<7> VDD! VSS! / RM_IHPSG13_1024x32_c2_2P_COLDRV13_FILL4C2 +XCOLFILL4<8> VDD! VSS! / RM_IHPSG13_1024x32_c2_2P_COLDRV13_FILL4C2 +XCOLFILL4<9> VDD! VSS! / RM_IHPSG13_1024x32_c2_2P_COLDRV13_FILL4C2 +XCOLFILL4<10> VDD! VSS! / RM_IHPSG13_1024x32_c2_2P_COLDRV13_FILL4C2 +XCOLFILL4<11> VDD! VSS! / RM_IHPSG13_1024x32_c2_2P_COLDRV13_FILL4C2 +XCOLFILL4<12> VDD! VSS! / RM_IHPSG13_1024x32_c2_2P_COLDRV13_FILL4C2 +XCOLFILL4<13> VDD! VSS! / RM_IHPSG13_1024x32_c2_2P_COLDRV13_FILL4C2 +XCOLFILL4<14> VDD! VSS! / RM_IHPSG13_1024x32_c2_2P_COLDRV13_FILL4C2 +XCOLFILL4<15> VDD! VSS! / RM_IHPSG13_1024x32_c2_2P_COLDRV13_FILL4C2 +XCOLFILL4<16> VDD! VSS! / RM_IHPSG13_1024x32_c2_2P_COLDRV13_FILL4C2 +.ENDS diff --git a/flow/platforms/ihp-sg13g2/cdl/RM_IHPSG13_2P_256x16_c2_bm_bist.cdl b/flow/platforms/ihp-sg13g2/cdl/RM_IHPSG13_2P_256x16_c2_bm_bist.cdl new file mode 100644 index 0000000000..eb4e99f1ef --- /dev/null +++ b/flow/platforms/ihp-sg13g2/cdl/RM_IHPSG13_2P_256x16_c2_bm_bist.cdl @@ -0,0 +1,6378 @@ +* ------------------------------------------------------ +* +* Copyright 2025 IHP PDK Authors +* +* Licensed under the Apache License, Version 2.0 (the "License"); +* you may not use this file except in compliance with the License. +* You may obtain a copy of the License at +* +* https://www.apache.org/licenses/LICENSE-2.0 +* +* Unless required by applicable law or agreed to in writing, software +* distributed under the License is distributed on an "AS IS" BASIS, +* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +* See the License for the specific language governing permissions and +* limitations under the License. +* +* Generated on Wed Aug 27 13:19:48 2025 +* +* ------------------------------------------------------ + +.SUBCKT RM_IHPSG13_256x16_c2_1P_BITKIT_CORNER NW PW VDD VSS +.ENDS +.SUBCKT RM_IHPSG13_256x16_c2_1P_BITKIT_16x2_CORNER VDD_CORE VSS +XI16 VDD_CORE VSS VDD_CORE VSS / ++ RM_IHPSG13_256x16_c2_1P_BITKIT_CORNER +.ENDS +.SUBCKT RM_IHPSG13_256x16_c2_1P_BITKIT_EDGE_LR LWL NW PW VDD VSS +MN1 VSS LWL VSS VSS sg13_lv_nmos m=1 w=300.0n l=130.00n ng=1 nrd=0 nrs=0 +MN0 VSS net9 VSS VSS sg13_lv_nmos m=1 w=300.0n l=130.00n ng=1 nrd=0 nrs=0 +.ENDS +.SUBCKT RM_IHPSG13_256x16_c2_1P_BITKIT_16x2_EDGE_LR A_WL<15> A_WL<14> A_WL<13> A_WL<12> ++ A_WL<11> A_WL<10> A_WL<9> A_WL<8> A_WL<7> A_WL<6> A_WL<5> A_WL<4> A_WL<3> ++ A_WL<2> A_WL<1> A_WL<0> VDD_CORE VSS +XI0<15> A_WL<15> VDD_CORE VSS VDD_CORE VSS / ++ RM_IHPSG13_256x16_c2_1P_BITKIT_EDGE_LR +XI0<14> A_WL<14> VDD_CORE VSS VDD_CORE VSS / ++ RM_IHPSG13_256x16_c2_1P_BITKIT_EDGE_LR +XI0<13> A_WL<13> VDD_CORE VSS VDD_CORE VSS / ++ RM_IHPSG13_256x16_c2_1P_BITKIT_EDGE_LR +XI0<12> A_WL<12> VDD_CORE VSS VDD_CORE VSS / ++ RM_IHPSG13_256x16_c2_1P_BITKIT_EDGE_LR +XI0<11> A_WL<11> VDD_CORE VSS VDD_CORE VSS / ++ RM_IHPSG13_256x16_c2_1P_BITKIT_EDGE_LR +XI0<10> A_WL<10> VDD_CORE VSS VDD_CORE VSS / ++ RM_IHPSG13_256x16_c2_1P_BITKIT_EDGE_LR +XI0<9> A_WL<9> VDD_CORE VSS VDD_CORE VSS / ++ RM_IHPSG13_256x16_c2_1P_BITKIT_EDGE_LR +XI0<8> A_WL<8> VDD_CORE VSS VDD_CORE VSS / ++ RM_IHPSG13_256x16_c2_1P_BITKIT_EDGE_LR +XI0<7> A_WL<7> VDD_CORE VSS VDD_CORE VSS / ++ RM_IHPSG13_256x16_c2_1P_BITKIT_EDGE_LR +XI0<6> A_WL<6> VDD_CORE VSS VDD_CORE VSS / ++ RM_IHPSG13_256x16_c2_1P_BITKIT_EDGE_LR +XI0<5> A_WL<5> VDD_CORE VSS VDD_CORE VSS / ++ RM_IHPSG13_256x16_c2_1P_BITKIT_EDGE_LR +XI0<4> A_WL<4> VDD_CORE VSS VDD_CORE VSS / ++ RM_IHPSG13_256x16_c2_1P_BITKIT_EDGE_LR +XI0<3> A_WL<3> VDD_CORE VSS VDD_CORE VSS / ++ RM_IHPSG13_256x16_c2_1P_BITKIT_EDGE_LR +XI0<2> A_WL<2> VDD_CORE VSS VDD_CORE VSS / ++ RM_IHPSG13_256x16_c2_1P_BITKIT_EDGE_LR +XI0<1> A_WL<1> VDD_CORE VSS VDD_CORE VSS / ++ RM_IHPSG13_256x16_c2_1P_BITKIT_EDGE_LR +XI0<0> A_WL<0> VDD_CORE VSS VDD_CORE VSS / ++ RM_IHPSG13_256x16_c2_1P_BITKIT_EDGE_LR +.ENDS +.SUBCKT RM_IHPSG13_256x16_c2_1P_BITKIT_CELL BLC_BOT BLC_TOP BLT_BOT BLT_TOP LWL NW PW ++ RWL VDD VSS +MN0 NC NT VSS PW sg13_lv_nmos m=1 w=300.0n l=130.00n ng=1 nrd=0 nrs=0 +MN1 NT NC VSS PW sg13_lv_nmos m=1 w=300.0n l=130.00n ng=1 nrd=0 nrs=0 +MN3 NC RWL BLC_TOP PW sg13_lv_nmos m=1 w=300.0n l=130.00n ng=1 nrd=0 nrs=0 +MN2 BLT_BOT LWL NT PW sg13_lv_nmos m=1 w=300.0n l=130.00n ng=1 nrd=0 nrs=0 +MP1 NT NC VDD NW sg13_lv_pmos m=1 w=150.00n l=130.00n ng=1 nrd=0 nrs=0 +MP0 NC NT VDD NW sg13_lv_pmos m=1 w=150.00n l=130.00n ng=1 nrd=0 nrs=0 +R1 BLC_BOT BLC_TOP lvsres w=2.6e-07 l=6e-07 +R0 BLT_BOT BLT_TOP lvsres w=2.6e-07 l=6e-07 +R2 RWL LWL lvsres w=2.6e-07 l=6e-07 +.ENDS +.SUBCKT RM_IHPSG13_256x16_c2_1P_BITKIT_16x2_SRAM A_BLC_BOT<1> A_BLC_BOT<0> A_BLC_TOP<1> ++ A_BLC_TOP<0> A_BLT_BOT<1> A_BLT_BOT<0> A_BLT_TOP<1> A_BLT_TOP<0> A_LWL<15> ++ A_LWL<14> A_LWL<13> A_LWL<12> A_LWL<11> A_LWL<10> A_LWL<9> A_LWL<8> A_LWL<7> ++ A_LWL<6> A_LWL<5> A_LWL<4> A_LWL<3> A_LWL<2> A_LWL<1> A_LWL<0> A_RWL<15> ++ A_RWL<14> A_RWL<13> A_RWL<12> A_RWL<11> A_RWL<10> A_RWL<9> A_RWL<8> A_RWL<7> ++ A_RWL<6> A_RWL<5> A_RWL<4> A_RWL<3> A_RWL<2> A_RWL<1> A_RWL<0> VDD_CORE ++ VSS +XCELL<31> A_BLC_TOP<1> A_RBLC<15> A_BLT_TOP<1> A_RBLT<15> A_RWL<15> ++ VDD_CORE VSS A_XWL<15> VDD_CORE VSS / ++ RM_IHPSG13_256x16_c2_1P_BITKIT_CELL +XCELL<30> A_RBLC<14> A_RBLC<15> A_RBLT<14> A_RBLT<15> A_RWL<14> VDD_CORE ++ VSS A_XWL<14> VDD_CORE VSS / RM_IHPSG13_256x16_c2_1P_BITKIT_CELL +XCELL<29> A_RBLC<14> A_RBLC<13> A_RBLT<14> A_RBLT<13> A_RWL<13> VDD_CORE ++ VSS A_XWL<13> VDD_CORE VSS / RM_IHPSG13_256x16_c2_1P_BITKIT_CELL +XCELL<28> A_RBLC<12> A_RBLC<13> A_RBLT<12> A_RBLT<13> A_RWL<12> VDD_CORE ++ VSS A_XWL<12> VDD_CORE VSS / RM_IHPSG13_256x16_c2_1P_BITKIT_CELL +XCELL<27> A_RBLC<12> A_RBLC<11> A_RBLT<12> A_RBLT<11> A_RWL<11> VDD_CORE ++ VSS A_XWL<11> VDD_CORE VSS / RM_IHPSG13_256x16_c2_1P_BITKIT_CELL +XCELL<26> A_RBLC<10> A_RBLC<11> A_RBLT<10> A_RBLT<11> A_RWL<10> VDD_CORE ++ VSS A_XWL<10> VDD_CORE VSS / RM_IHPSG13_256x16_c2_1P_BITKIT_CELL +XCELL<25> A_RBLC<10> A_RBLC<9> A_RBLT<10> A_RBLT<9> A_RWL<9> VDD_CORE ++ VSS A_XWL<9> VDD_CORE VSS / RM_IHPSG13_256x16_c2_1P_BITKIT_CELL +XCELL<24> A_RBLC<8> A_RBLC<9> A_RBLT<8> A_RBLT<9> A_RWL<8> VDD_CORE ++ VSS A_XWL<8> VDD_CORE VSS / RM_IHPSG13_256x16_c2_1P_BITKIT_CELL +XCELL<23> A_RBLC<8> A_RBLC<7> A_RBLT<8> A_RBLT<7> A_RWL<7> VDD_CORE ++ VSS A_XWL<7> VDD_CORE VSS / RM_IHPSG13_256x16_c2_1P_BITKIT_CELL +XCELL<22> A_RBLC<6> A_RBLC<7> A_RBLT<6> A_RBLT<7> A_RWL<6> VDD_CORE ++ VSS A_XWL<6> VDD_CORE VSS / RM_IHPSG13_256x16_c2_1P_BITKIT_CELL +XCELL<21> A_RBLC<6> A_RBLC<5> A_RBLT<6> A_RBLT<5> A_RWL<5> VDD_CORE ++ VSS A_XWL<5> VDD_CORE VSS / RM_IHPSG13_256x16_c2_1P_BITKIT_CELL +XCELL<20> A_RBLC<4> A_RBLC<5> A_RBLT<4> A_RBLT<5> A_RWL<4> VDD_CORE ++ VSS A_XWL<4> VDD_CORE VSS / RM_IHPSG13_256x16_c2_1P_BITKIT_CELL +XCELL<19> A_RBLC<4> A_RBLC<3> A_RBLT<4> A_RBLT<3> A_RWL<3> VDD_CORE ++ VSS A_XWL<3> VDD_CORE VSS / RM_IHPSG13_256x16_c2_1P_BITKIT_CELL +XCELL<18> A_RBLC<2> A_RBLC<3> A_RBLT<2> A_RBLT<3> A_RWL<2> VDD_CORE ++ VSS A_XWL<2> VDD_CORE VSS / RM_IHPSG13_256x16_c2_1P_BITKIT_CELL +XCELL<17> A_RBLC<2> A_RBLC<1> A_RBLT<2> A_RBLT<1> A_RWL<1> VDD_CORE ++ VSS A_XWL<1> VDD_CORE VSS / RM_IHPSG13_256x16_c2_1P_BITKIT_CELL +XCELL<16> A_BLC_BOT<1> A_RBLC<1> A_BLT_BOT<1> A_RBLT<1> A_RWL<0> VDD_CORE ++ VSS A_XWL<0> VDD_CORE VSS / RM_IHPSG13_256x16_c2_1P_BITKIT_CELL +XCELL<15> A_BLC_TOP<0> A_LBLC<15> A_BLT_TOP<0> A_LBLT<15> A_LWL<15> ++ VDD_CORE VSS A_XWL<15> VDD_CORE VSS / ++ RM_IHPSG13_256x16_c2_1P_BITKIT_CELL +XCELL<14> A_LBLC<14> A_LBLC<15> A_LBLT<14> A_LBLT<15> A_LWL<14> VDD_CORE ++ VSS A_XWL<14> VDD_CORE VSS / RM_IHPSG13_256x16_c2_1P_BITKIT_CELL +XCELL<13> A_LBLC<14> A_LBLC<13> A_LBLT<14> A_LBLT<13> A_LWL<13> VDD_CORE ++ VSS A_XWL<13> VDD_CORE VSS / RM_IHPSG13_256x16_c2_1P_BITKIT_CELL +XCELL<12> A_LBLC<12> A_LBLC<13> A_LBLT<12> A_LBLT<13> A_LWL<12> VDD_CORE ++ VSS A_XWL<12> VDD_CORE VSS / RM_IHPSG13_256x16_c2_1P_BITKIT_CELL +XCELL<11> A_LBLC<12> A_LBLC<11> A_LBLT<12> A_LBLT<11> A_LWL<11> VDD_CORE ++ VSS A_XWL<11> VDD_CORE VSS / RM_IHPSG13_256x16_c2_1P_BITKIT_CELL +XCELL<10> A_LBLC<10> A_LBLC<11> A_LBLT<10> A_LBLT<11> A_LWL<10> VDD_CORE ++ VSS A_XWL<10> VDD_CORE VSS / RM_IHPSG13_256x16_c2_1P_BITKIT_CELL +XCELL<9> A_LBLC<10> A_LBLC<9> A_LBLT<10> A_LBLT<9> A_LWL<9> VDD_CORE ++ VSS A_XWL<9> VDD_CORE VSS / RM_IHPSG13_256x16_c2_1P_BITKIT_CELL +XCELL<8> A_LBLC<8> A_LBLC<9> A_LBLT<8> A_LBLT<9> A_LWL<8> VDD_CORE ++ VSS A_XWL<8> VDD_CORE VSS / RM_IHPSG13_256x16_c2_1P_BITKIT_CELL +XCELL<7> A_LBLC<8> A_LBLC<7> A_LBLT<8> A_LBLT<7> A_LWL<7> VDD_CORE ++ VSS A_XWL<7> VDD_CORE VSS / RM_IHPSG13_256x16_c2_1P_BITKIT_CELL +XCELL<6> A_LBLC<6> A_LBLC<7> A_LBLT<6> A_LBLT<7> A_LWL<6> VDD_CORE ++ VSS A_XWL<6> VDD_CORE VSS / RM_IHPSG13_256x16_c2_1P_BITKIT_CELL +XCELL<5> A_LBLC<6> A_LBLC<5> A_LBLT<6> A_LBLT<5> A_LWL<5> VDD_CORE ++ VSS A_XWL<5> VDD_CORE VSS / RM_IHPSG13_256x16_c2_1P_BITKIT_CELL +XCELL<4> A_LBLC<4> A_LBLC<5> A_LBLT<4> A_LBLT<5> A_LWL<4> VDD_CORE ++ VSS A_XWL<4> VDD_CORE VSS / RM_IHPSG13_256x16_c2_1P_BITKIT_CELL +XCELL<3> A_LBLC<4> A_LBLC<3> A_LBLT<4> A_LBLT<3> A_LWL<3> VDD_CORE ++ VSS A_XWL<3> VDD_CORE VSS / RM_IHPSG13_256x16_c2_1P_BITKIT_CELL +XCELL<2> A_LBLC<2> A_LBLC<3> A_LBLT<2> A_LBLT<3> A_LWL<2> VDD_CORE ++ VSS A_XWL<2> VDD_CORE VSS / RM_IHPSG13_256x16_c2_1P_BITKIT_CELL +XCELL<1> A_LBLC<2> A_LBLC<1> A_LBLT<2> A_LBLT<1> A_LWL<1> VDD_CORE ++ VSS A_XWL<1> VDD_CORE VSS / RM_IHPSG13_256x16_c2_1P_BITKIT_CELL +XCELL<0> A_BLC_BOT<0> A_LBLC<1> A_BLT_BOT<0> A_LBLT<1> A_LWL<0> VDD_CORE ++ VSS A_XWL<0> VDD_CORE VSS / RM_IHPSG13_256x16_c2_1P_BITKIT_CELL +.ENDS +.SUBCKT RM_IHPSG13_256x16_c2_1P_BITKIT_EDGE_TB BLC BLT NW PW VDD VSS +.ENDS +.SUBCKT RM_IHPSG13_256x16_c2_1P_BITKIT_16x2_EDGE_TB A_BLC<1> A_BLC<0> A_BLT<1> A_BLT<0> ++ VDD_CORE VSS +XEDGE<1> A_BLC<1> A_BLT<1> VDD_CORE VSS VDD_CORE VSS ++ / RM_IHPSG13_256x16_c2_1P_BITKIT_EDGE_TB +XEDGE<0> A_BLC<0> A_BLT<0> VDD_CORE VSS VDD_CORE VSS ++ / RM_IHPSG13_256x16_c2_1P_BITKIT_EDGE_TB +.ENDS + +.SUBCKT RSC_IHPSG13_CBUFX4 A Z VDD VSS +MN0 net9 A VSS VSS sg13_lv_nmos m=1 w=705.000n l=130.00n ng=1 nrd=0 ++ nrs=0 +MN1 Z net9 VSS VSS sg13_lv_nmos m=1 w=1.41u l=130.00n ng=2 nrd=0 nrs=0 +MP0 net9 A VDD VDD sg13_lv_pmos m=1 w=1.62u l=130.00n ng=1 nrd=0 nrs=0 +MP1 Z net9 VDD VDD sg13_lv_pmos m=1 w=3.24u l=130.00n ng=2 nrd=0 nrs=0 +.ENDS +.SUBCKT RM_IHPSG13_256x16_c2_1P_COLDRV13X4 ADDR_COL_I<1> ADDR_COL_I<0> ADDR_COL_O<1> ++ ADDR_COL_O<0> ADDR_DEC_I<7> ADDR_DEC_I<6> ADDR_DEC_I<5> ADDR_DEC_I<4> ++ ADDR_DEC_I<3> ADDR_DEC_I<2> ADDR_DEC_I<1> ADDR_DEC_I<0> ADDR_DEC_O<7> ++ ADDR_DEC_O<6> ADDR_DEC_O<5> ADDR_DEC_O<4> ADDR_DEC_O<3> ADDR_DEC_O<2> ++ ADDR_DEC_O<1> ADDR_DEC_O<0> DCLK_I DCLK_O RCLK_I RCLK_O WCLK_I WCLK_O ++ VDD VSS +XADDR_COL_DRV<1> ADDR_COL_I<1> ADDR_COL_O<1> VDD VSS / ++ RSC_IHPSG13_CBUFX4 +XADDR_COL_DRV<0> ADDR_COL_I<0> ADDR_COL_O<0> VDD VSS / ++ RSC_IHPSG13_CBUFX4 +XADDR_DEC_DRV<7> ADDR_DEC_I<7> ADDR_DEC_O<7> VDD VSS / ++ RSC_IHPSG13_CBUFX4 +XADDR_DEC_DRV<6> ADDR_DEC_I<6> ADDR_DEC_O<6> VDD VSS / ++ RSC_IHPSG13_CBUFX4 +XADDR_DEC_DRV<5> ADDR_DEC_I<5> ADDR_DEC_O<5> VDD VSS / ++ RSC_IHPSG13_CBUFX4 +XADDR_DEC_DRV<4> ADDR_DEC_I<4> ADDR_DEC_O<4> VDD VSS / ++ RSC_IHPSG13_CBUFX4 +XADDR_DEC_DRV<3> ADDR_DEC_I<3> ADDR_DEC_O<3> VDD VSS / ++ RSC_IHPSG13_CBUFX4 +XADDR_DEC_DRV<2> ADDR_DEC_I<2> ADDR_DEC_O<2> VDD VSS / ++ RSC_IHPSG13_CBUFX4 +XADDR_DEC_DRV<1> ADDR_DEC_I<1> ADDR_DEC_O<1> VDD VSS / ++ RSC_IHPSG13_CBUFX4 +XADDR_DEC_DRV<0> ADDR_DEC_I<0> ADDR_DEC_O<0> VDD VSS / ++ RSC_IHPSG13_CBUFX4 +XDCLK_DRV DCLK_I DCLK_O VDD VSS / RSC_IHPSG13_CBUFX4 +XRCLK_DRV RCLK_I RCLK_O VDD VSS / RSC_IHPSG13_CBUFX4 +XWCLK_DRV WCLK_I WCLK_O VDD VSS / RSC_IHPSG13_CBUFX4 +.ENDS +.SUBCKT RSC_IHPSG13_WLDRVX4 A Z VDD VSS +MN1 Z net6 VSS VSS sg13_lv_nmos m=1 w=705.000n l=130.00n ng=1 nrd=0 ++ nrs=0 +MN0 net6 A VSS VSS sg13_lv_nmos m=1 w=900.0n l=130.00n ng=1 nrd=0 nrs=0 +MP1 Z net6 VDD VDD sg13_lv_pmos m=1 w=3.24u l=130.00n ng=2 nrd=0 nrs=0 +MP0 net6 A VDD VDD sg13_lv_pmos m=1 w=900.0n l=130.00n ng=1 nrd=0 nrs=0 +.ENDS +.SUBCKT RM_IHPSG13_256x16_c2_1P_WLDRV16X4 A<15> A<14> A<13> A<12> A<11> A<10> A<9> A<8> ++ A<7> A<6> A<5> A<4> A<3> A<2> A<1> A<0> Z<15> Z<14> Z<13> Z<12> Z<11> Z<10> ++ Z<9> Z<8> Z<7> Z<6> Z<5> Z<4> Z<3> Z<2> Z<1> Z<0> VDD VSS +XBUF<15> A<15> Z<15> VDD VSS / RSC_IHPSG13_WLDRVX4 +XBUF<14> A<14> Z<14> VDD VSS / RSC_IHPSG13_WLDRVX4 +XBUF<13> A<13> Z<13> VDD VSS / RSC_IHPSG13_WLDRVX4 +XBUF<12> A<12> Z<12> VDD VSS / RSC_IHPSG13_WLDRVX4 +XBUF<11> A<11> Z<11> VDD VSS / RSC_IHPSG13_WLDRVX4 +XBUF<10> A<10> Z<10> VDD VSS / RSC_IHPSG13_WLDRVX4 +XBUF<9> A<9> Z<9> VDD VSS / RSC_IHPSG13_WLDRVX4 +XBUF<8> A<8> Z<8> VDD VSS / RSC_IHPSG13_WLDRVX4 +XBUF<7> A<7> Z<7> VDD VSS / RSC_IHPSG13_WLDRVX4 +XBUF<6> A<6> Z<6> VDD VSS / RSC_IHPSG13_WLDRVX4 +XBUF<5> A<5> Z<5> VDD VSS / RSC_IHPSG13_WLDRVX4 +XBUF<4> A<4> Z<4> VDD VSS / RSC_IHPSG13_WLDRVX4 +XBUF<3> A<3> Z<3> VDD VSS / RSC_IHPSG13_WLDRVX4 +XBUF<2> A<2> Z<2> VDD VSS / RSC_IHPSG13_WLDRVX4 +XBUF<1> A<1> Z<1> VDD VSS / RSC_IHPSG13_WLDRVX4 +XBUF<0> A<0> Z<0> VDD VSS / RSC_IHPSG13_WLDRVX4 +.ENDS +.SUBCKT RSC_IHPSG13_FILLCAP8 VDD VSS +MN0 vss_r vdd_r VSS VSS sg13_lv_nmos m=1 w=4.98u l=130.00n ng=6 nrd=0 ++ nrs=0 +MP0 vdd_r vss_r VDD VDD sg13_lv_pmos m=1 w=6.48u l=385.000n ng=4 nrd=0 ++ nrs=0 +.ENDS +.SUBCKT RSC_IHPSG13_LHPQX2 CP D Q VDD VSS +MN3 QIN CPN net14 VSS sg13_lv_nmos m=1 w=480.00n l=130.00n ng=1 nrd=0 nrs=0 +MN2 net14 net10 VSS VSS sg13_lv_nmos m=1 w=480.00n l=130.00n ng=1 ++ nrd=0 nrs=0 +MN5 net21 D VSS VSS sg13_lv_nmos m=1 w=870.00n l=130.00n ng=1 nrd=0 ++ nrs=0 +MN6 QIN CP net21 VSS sg13_lv_nmos m=1 w=870.00n l=130.00n ng=1 nrd=0 nrs=0 +MN1 net10 QIN VSS VSS sg13_lv_nmos m=1 w=480.00n l=130.00n ng=1 nrd=0 ++ nrs=0 +MN0 CPN CP VSS VSS sg13_lv_nmos m=1 w=480.00n l=130.00n ng=1 nrd=0 ++ nrs=0 +MN4 Q QIN VSS VSS sg13_lv_nmos m=1 w=980.00n l=130.00n ng=1 nrd=0 nrs=0 +MP2 QIN CP net16 VDD sg13_lv_pmos m=1 w=480.00n l=130.00n ng=1 nrd=0 nrs=0 +MP0 CPN CP VDD VDD sg13_lv_pmos m=1 w=480.00n l=130.00n ng=1 nrd=0 ++ nrs=0 +MP4 Q QIN VDD VDD sg13_lv_pmos m=1 w=1.62u l=130.00n ng=1 nrd=0 nrs=0 +MP3 net10 QIN VDD VDD sg13_lv_pmos m=1 w=480.00n l=130.00n ng=1 nrd=0 ++ nrs=0 +MP1 net16 net10 VDD VDD sg13_lv_pmos m=1 w=480.00n l=130.00n ng=1 ++ nrd=0 nrs=0 +MP6 QIN CPN net20 VDD sg13_lv_pmos m=1 w=975.000n l=130.00n ng=1 nrd=0 ++ nrs=0 +MP5 net20 D VDD VDD sg13_lv_pmos m=1 w=975.000n l=130.00n ng=1 nrd=0 ++ nrs=0 +.ENDS +.SUBCKT RSC_IHPSG13_NAND2X2 A B Z VDD VSS +MP1 Z B VDD VDD sg13_lv_pmos m=1 w=1.62u l=130.00n ng=1 nrd=0 nrs=0 +MP0 Z A VDD VDD sg13_lv_pmos m=1 w=1.62u l=130.00n ng=1 nrd=0 nrs=0 +MN0 Z B net7 VSS sg13_lv_nmos m=1 w=980.00n l=130.00n ng=1 nrd=0 nrs=0 +MN1 net7 A VSS VSS sg13_lv_nmos m=1 w=980.00n l=130.00n ng=1 nrd=0 ++ nrs=0 +.ENDS +.SUBCKT RSC_IHPSG13_CINVX4 A Z VDD VSS +MN0 Z A VSS VSS sg13_lv_nmos m=1 w=1.41u l=130.00n ng=2 nrd=0 nrs=0 +MP0 Z A VDD VDD sg13_lv_pmos m=1 w=3.24u l=130.00n ng=2 nrd=0 nrs=0 +.ENDS +.SUBCKT RSC_IHPSG13_CINVX2 A Z VDD VSS +MN0 Z A VSS VSS sg13_lv_nmos m=1 w=705.000n l=130.00n ng=1 nrd=0 nrs=0 +MP0 Z A VDD VDD sg13_lv_pmos m=1 w=1.62u l=130.00n ng=1 nrd=0 nrs=0 +.ENDS +.SUBCKT RSC_IHPSG13_INVX2 A Z VDD VSS +MN0 Z A VSS VSS sg13_lv_nmos m=1 w=980.00n l=130.00n ng=1 nrd=0 nrs=0 +MP0 Z A VDD VDD sg13_lv_pmos m=1 w=1.62u l=130.00n ng=1 nrd=0 nrs=0 +.ENDS +.SUBCKT RSC_IHPSG13_NAND3X2 A B C Z VDD VSS +MP2 Z A VDD VDD sg13_lv_pmos m=1 w=1.62u l=130.00n ng=1 nrd=0 nrs=0 +MP1 Z B VDD VDD sg13_lv_pmos m=1 w=1.62u l=130.00n ng=1 nrd=0 nrs=0 +MP0 Z C VDD VDD sg13_lv_pmos m=1 w=1.62u l=130.00n ng=1 nrd=0 nrs=0 +MN1 net12 B net16 VSS sg13_lv_nmos m=1 w=980.00n l=130.00n ng=1 nrd=0 nrs=0 +MN0 Z C net12 VSS sg13_lv_nmos m=1 w=980.00n l=130.00n ng=1 nrd=0 nrs=0 +MN2 net16 A VSS VSS sg13_lv_nmos m=1 w=980.00n l=130.00n ng=1 nrd=0 ++ nrs=0 +.ENDS +.SUBCKT RSC_IHPSG13_NOR3X2 A B C Z VDD VSS +MP0 net13 A VDD VDD sg13_lv_pmos m=1 w=1.62u l=130.00n ng=1 nrd=0 nrs=0 +MP2 Z C net10 VDD sg13_lv_pmos m=1 w=1.62u l=130.00n ng=1 nrd=0 nrs=0 +MP1 net10 B net13 VDD sg13_lv_pmos m=1 w=1.62u l=130.00n ng=1 nrd=0 nrs=0 +MN1 Z B VSS VSS sg13_lv_nmos m=1 w=875.000n l=130.00n ng=1 nrd=0 nrs=0 +MN0 Z C VSS VSS sg13_lv_nmos m=1 w=875.000n l=130.00n ng=1 nrd=0 nrs=0 +MN2 Z A VSS VSS sg13_lv_nmos m=1 w=875.000n l=130.00n ng=1 nrd=0 nrs=0 +.ENDS +.SUBCKT RSC_IHPSG13_FILLCAP4 VDD VSS +MN0 vss_r vdd_r VSS VSS sg13_lv_nmos m=1 w=2.49u l=130.00n ng=3 nrd=0 ++ nrs=0 +MP0 vdd_r vss_r VDD VDD sg13_lv_pmos m=1 w=3.24u l=385.000n ng=2 nrd=0 ++ nrs=0 +.ENDS +.SUBCKT RSC_IHPSG13_MET2RES A B +R0 B A lvsres w=2.6e-07 l=6e-07 +.ENDS +.SUBCKT RM_IHPSG13_256x16_c2_1P_DEC04 ADDR<3> ADDR<2> ADDR<1> ADDR<0> CS ECLK_H_BOT ++ ECLK_H_TOP ECLK_L_BOT ECLK_L_TOP WL<15> WL<14> WL<13> WL<12> WL<11> WL<10> ++ WL<9> WL<8> WL<7> WL<6> WL<5> WL<4> WL<3> WL<2> WL<1> WL<0> VDD VSS +XLATCH<3> CS ADDR<3> PADR<3> VDD VSS / RSC_IHPSG13_LHPQX2 +XLATCH<2> CS ADDR<2> PADR<2> VDD VSS / RSC_IHPSG13_LHPQX2 +XLATCH<1> CS ADDR<1> PADR<1> VDD VSS / RSC_IHPSG13_LHPQX2 +XLATCH<0> CS ADDR<0> PADR<0> VDD VSS / RSC_IHPSG13_LHPQX2 +XI0<3> PADR<1> PADR<0> sel01<3> VDD VSS / RSC_IHPSG13_NAND2X2 +XI0<2> PADR<1> NADR<0> sel01<2> VDD VSS / RSC_IHPSG13_NAND2X2 +XI0<1> NADR<1> PADR<0> sel01<1> VDD VSS / RSC_IHPSG13_NAND2X2 +XI0<0> NADR<1> NADR<0> sel01<0> VDD VSS / RSC_IHPSG13_NAND2X2 +XI4 ECLK_L_BOT EN VDD VSS / RSC_IHPSG13_CINVX4 +XI5 ECLK_H_BOT ECLK_L_BOT VDD VSS / RSC_IHPSG13_CINVX2 +XI3<3> PADR<3> NADR<3> VDD VSS / RSC_IHPSG13_INVX2 +XI3<2> PADR<2> NADR<2> VDD VSS / RSC_IHPSG13_INVX2 +XI3<1> PADR<1> NADR<1> VDD VSS / RSC_IHPSG13_INVX2 +XI3<0> PADR<0> NADR<0> VDD VSS / RSC_IHPSG13_INVX2 +XI1<3> PADR<2> PADR<3> CS sel23<3> VDD VSS / RSC_IHPSG13_NAND3X2 +XI1<2> NADR<2> PADR<3> CS sel23<2> VDD VSS / RSC_IHPSG13_NAND3X2 +XI1<1> PADR<2> NADR<3> CS sel23<1> VDD VSS / RSC_IHPSG13_NAND3X2 +XI1<0> NADR<2> NADR<3> CS sel23<0> VDD VSS / RSC_IHPSG13_NAND3X2 +XI2<15> sel23<3> sel01<3> EN WL<15> VDD VSS / RSC_IHPSG13_NOR3X2 +XI2<14> sel23<3> sel01<2> EN WL<14> VDD VSS / RSC_IHPSG13_NOR3X2 +XI2<13> sel23<3> sel01<1> EN WL<13> VDD VSS / RSC_IHPSG13_NOR3X2 +XI2<12> sel23<3> sel01<0> EN WL<12> VDD VSS / RSC_IHPSG13_NOR3X2 +XI2<11> sel23<2> sel01<3> EN WL<11> VDD VSS / RSC_IHPSG13_NOR3X2 +XI2<10> sel23<2> sel01<2> EN WL<10> VDD VSS / RSC_IHPSG13_NOR3X2 +XI2<9> sel23<2> sel01<1> EN WL<9> VDD VSS / RSC_IHPSG13_NOR3X2 +XI2<8> sel23<2> sel01<0> EN WL<8> VDD VSS / RSC_IHPSG13_NOR3X2 +XI2<7> sel23<1> sel01<3> EN WL<7> VDD VSS / RSC_IHPSG13_NOR3X2 +XI2<6> sel23<1> sel01<2> EN WL<6> VDD VSS / RSC_IHPSG13_NOR3X2 +XI2<5> sel23<1> sel01<1> EN WL<5> VDD VSS / RSC_IHPSG13_NOR3X2 +XI2<4> sel23<1> sel01<0> EN WL<4> VDD VSS / RSC_IHPSG13_NOR3X2 +XI2<3> sel23<0> sel01<3> EN WL<3> VDD VSS / RSC_IHPSG13_NOR3X2 +XI2<2> sel23<0> sel01<2> EN WL<2> VDD VSS / RSC_IHPSG13_NOR3X2 +XI2<1> sel23<0> sel01<1> EN WL<1> VDD VSS / RSC_IHPSG13_NOR3X2 +XI2<0> sel23<0> sel01<0> EN WL<0> VDD VSS / RSC_IHPSG13_NOR3X2 +XCAPS4 VDD VSS / RSC_IHPSG13_FILLCAP4 +XI11 ECLK_L_BOT ECLK_L_TOP / RSC_IHPSG13_MET2RES +XR0 ECLK_H_BOT ECLK_H_TOP / RSC_IHPSG13_MET2RES +.ENDS +.SUBCKT RM_IHPSG13_256x16_c2_1P_ROWDEC4 ADDR_N_I<3> ADDR_N_I<2> ADDR_N_I<1> ADDR_N_I<0> ++ CS_I ECLK_I WL_O<15> WL_O<14> WL_O<13> WL_O<12> WL_O<11> WL_O<10> WL_O<9> ++ WL_O<8> WL_O<7> WL_O<6> WL_O<5> WL_O<4> WL_O<3> WL_O<2> WL_O<1> WL_O<0> ++ VDD VSS +XL2<8> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<7> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<6> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<5> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<4> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<3> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<2> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<1> VDD VSS / RSC_IHPSG13_FILLCAP8 +XSEL ADDR_N_I<3> ADDR_N_I<2> ADDR_N_I<1> ADDR_N_I<0> CS_I ECLK_I ECLK_H<1> ++ ECLK_B<0> ECLK_B<1> WL_O<15> WL_O<14> WL_O<13> WL_O<12> WL_O<11> WL_O<10> ++ WL_O<9> WL_O<8> WL_O<7> WL_O<6> WL_O<5> WL_O<4> WL_O<3> WL_O<2> WL_O<1> ++ WL_O<0> VDD VSS / RM_IHPSG13_256x16_c2_1P_DEC04 +.ENDS +.SUBCKT RSC_IHPSG13_CINVX8 A Z VDD VSS +MN0 Z A VSS VSS sg13_lv_nmos m=1 w=2.82u l=130.00n ng=4 nrd=0 nrs=0 +MP0 Z A VDD VDD sg13_lv_pmos m=1 w=6.48u l=130.00n ng=4 nrd=0 nrs=0 +.ENDS +.SUBCKT RSC_IHPSG13_DFNQMX2IX1 BE BI CN D QI QIN VDD VSS +MN15 net026 BI VSS VSS sg13_lv_nmos m=1 w=560.00n l=130.00n ng=1 nrd=0 ++ nrs=0 +MN14 MXI_OUT BE net026 VSS sg13_lv_nmos m=1 w=560.00n l=130.00n ng=1 nrd=0 ++ nrs=0 +MN1 net025 D VSS VSS sg13_lv_nmos m=1 w=560.00n l=130.00n ng=1 nrd=0 ++ nrs=0 +MN0 MXI_OUT BEN net025 VSS sg13_lv_nmos m=1 w=560.00n l=130.00n ng=1 nrd=0 ++ nrs=0 +MN10 QI CNN net21 VSS sg13_lv_nmos m=1 w=850.00n l=130.00n ng=1 nrd=0 nrs=0 +MN11 net21 QI_MS VSS VSS sg13_lv_nmos m=1 w=850.00n l=130.00n ng=1 ++ nrd=0 nrs=0 +MN7 net30 QI_MS VSS VSS sg13_lv_nmos m=1 w=480.00n l=130.00n ng=1 ++ nrd=0 nrs=0 +MN6 QIN_MS CNN net30 VSS sg13_lv_nmos m=1 w=480.00n l=130.00n ng=1 nrd=0 ++ nrs=0 +MN3 QI_MS QIN_MS VSS VSS sg13_lv_nmos m=1 w=480.00n l=130.00n ng=1 ++ nrd=0 nrs=0 +MN12 CNN CN VSS VSS sg13_lv_nmos m=1 w=495.000n l=130.00n ng=1 nrd=0 ++ nrs=0 +MN9 net37 MXI_OUT VSS VSS sg13_lv_nmos m=1 w=870.00n l=130.00n ng=1 ++ nrd=0 nrs=0 +MN8 QIN_MS CN net37 VSS sg13_lv_nmos m=1 w=870.00n l=130.00n ng=1 nrd=0 ++ nrs=0 +MN5 QI CN net25 VSS sg13_lv_nmos m=1 w=480.00n l=130.00n ng=1 nrd=0 nrs=0 +MN4 net25 QIN VSS VSS sg13_lv_nmos m=1 w=480.00n l=130.00n ng=1 nrd=0 ++ nrs=0 +MN2 QIN QI VSS VSS sg13_lv_nmos m=1 w=480.00n l=130.00n ng=1 nrd=0 ++ nrs=0 +MN13 BEN BE VSS VSS sg13_lv_nmos m=1 w=560.00n l=130.00n ng=1 nrd=0 ++ nrs=0 +MP15 MXI_OUT BEN net027 VDD sg13_lv_pmos m=1 w=985.000n l=130.00n ng=1 ++ nrd=0 nrs=0 +MP14 net027 BI VDD VDD sg13_lv_pmos m=1 w=985.000n l=130.00n ng=1 ++ nrd=0 nrs=0 +MP1 MXI_OUT BE net024 VDD sg13_lv_pmos m=1 w=985.000n l=130.00n ng=1 nrd=0 ++ nrs=0 +MP0 net024 D VDD VDD sg13_lv_pmos m=1 w=985.000n l=130.00n ng=1 nrd=0 ++ nrs=0 +MP13 BEN BE VDD VDD sg13_lv_pmos m=1 w=645.000n l=130.00n ng=1 nrd=0 ++ nrs=0 +MP6 QI_MS QIN_MS VDD VDD sg13_lv_pmos m=1 w=480.00n l=130.00n ng=1 ++ nrd=0 nrs=0 +MP3 QI CNN net27 VDD sg13_lv_pmos m=1 w=480.00n l=130.00n ng=1 nrd=0 nrs=0 +MP2 net27 QIN VDD VDD sg13_lv_pmos m=1 w=480.00n l=130.00n ng=1 nrd=0 ++ nrs=0 +MP10 net36 MXI_OUT VDD VDD sg13_lv_pmos m=1 w=975.000n l=130.00n ng=1 ++ nrd=0 nrs=0 +MP11 QIN_MS CNN net36 VDD sg13_lv_pmos m=1 w=975.000n l=130.00n ng=1 nrd=0 ++ nrs=0 +MP4 net32 QI_MS VDD VDD sg13_lv_pmos m=1 w=480.00n l=130.00n ng=1 ++ nrd=0 nrs=0 +MP5 QIN_MS CN net32 VDD sg13_lv_pmos m=1 w=480.00n l=130.00n ng=1 nrd=0 ++ nrs=0 +MP7 QIN QI VDD VDD sg13_lv_pmos m=1 w=480.00n l=130.00n ng=1 nrd=0 ++ nrs=0 +MP12 CNN CN VDD VDD sg13_lv_pmos m=1 w=480.00n l=130.00n ng=1 nrd=0 ++ nrs=0 +MP9 QI CN net19 VDD sg13_lv_pmos m=1 w=990.00n l=130.00n ng=1 nrd=0 nrs=0 +MP8 net19 QI_MS VDD VDD sg13_lv_pmos m=1 w=990.00n l=130.00n ng=1 ++ nrd=0 nrs=0 +.ENDS +.SUBCKT RM_IHPSG13_256x16_c2_1P_ROWREG4 ACLK_N_I ADDR_I<3> ADDR_I<2> ADDR_I<1> ADDR_I<0> ++ ADDR_N_O<3> ADDR_N_O<2> ADDR_N_O<1> ADDR_N_O<0> BIST_ADDR_I<3> ++ BIST_ADDR_I<2> BIST_ADDR_I<1> BIST_ADDR_I<0> BIST_EN_I VDD VSS +XINV<3> q_int<3> qn_int<3> VDD VSS / RSC_IHPSG13_CINVX2 +XINV<2> q_int<2> qn_int<2> VDD VSS / RSC_IHPSG13_CINVX2 +XINV<1> q_int<1> qn_int<1> VDD VSS / RSC_IHPSG13_CINVX2 +XINV<0> q_int<0> qn_int<0> VDD VSS / RSC_IHPSG13_CINVX2 +XDRV<3> qn_int<3> ADDR_N_O<3> VDD VSS / RSC_IHPSG13_CINVX8 +XDRV<2> qn_int<2> ADDR_N_O<2> VDD VSS / RSC_IHPSG13_CINVX8 +XDRV<1> qn_int<1> ADDR_N_O<1> VDD VSS / RSC_IHPSG13_CINVX8 +XDRV<0> qn_int<0> ADDR_N_O<0> VDD VSS / RSC_IHPSG13_CINVX8 +XDFF<3> BIST_EN_I BIST_ADDR_I<3> ACLK_N_I ADDR_I<3> q_int<3> net2<0> VDD ++ VSS / RSC_IHPSG13_DFNQMX2IX1 +XDFF<2> BIST_EN_I BIST_ADDR_I<2> ACLK_N_I ADDR_I<2> q_int<2> net2<1> VDD ++ VSS / RSC_IHPSG13_DFNQMX2IX1 +XDFF<1> BIST_EN_I BIST_ADDR_I<1> ACLK_N_I ADDR_I<1> q_int<1> net2<2> VDD ++ VSS / RSC_IHPSG13_DFNQMX2IX1 +XDFF<0> BIST_EN_I BIST_ADDR_I<0> ACLK_N_I ADDR_I<0> q_int<0> net2<3> VDD ++ VSS / RSC_IHPSG13_DFNQMX2IX1 +XI11<20> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI11<19> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI11<18> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI11<17> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI11<16> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI11<15> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI11<14> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI11<13> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI11<12> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI11<11> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI11<10> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI11<9> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI11<8> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI11<7> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI11<6> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI11<5> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI11<4> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI11<3> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI11<2> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI11<1> VDD VSS / RSC_IHPSG13_FILLCAP8 +.ENDS +.SUBCKT RSC_IHPSG13_CDLYX1 A Z VDD VSS +MN1 net010 net032 VSS VSS sg13_lv_nmos m=1 w=300.0n l=160.00n ng=1 ++ nrd=0 nrs=0 +MN2 net032 A net014 VSS sg13_lv_nmos m=1 w=300.0n l=160.00n ng=1 nrd=0 ++ nrs=0 +MN0 Z net032 net010 VSS sg13_lv_nmos m=1 w=300.0n l=160.00n ng=1 nrd=0 ++ nrs=0 +MN3 net014 A VSS VSS sg13_lv_nmos m=1 w=300.0n l=160.00n ng=1 nrd=0 ++ nrs=0 +MP1 Z net032 net07 VDD sg13_lv_pmos m=1 w=720.00n l=160.00n ng=1 nrd=0 ++ nrs=0 +MP3 net011 A VDD VDD sg13_lv_pmos m=1 w=720.00n l=160.00n ng=1 nrd=0 ++ nrs=0 +MP0 net07 net032 VDD VDD sg13_lv_pmos m=1 w=720.00n l=160.00n ng=1 ++ nrd=0 nrs=0 +MP2 net032 A net011 VDD sg13_lv_pmos m=1 w=720.00n l=160.00n ng=1 nrd=0 ++ nrs=0 +.ENDS +.SUBCKT RSC_IHPSG13_CDLYX1_DUMMY A Z VDD VSS +MN0 vss_r vdd_r VSS VSS sg13_lv_nmos m=1 w=2.49u l=300.0n ng=3 nrd=0 ++ nrs=0 +MP0 vdd_r vss_r VDD VDD sg13_lv_pmos m=1 w=3.24u l=640.00n ng=2 nrd=0 ++ nrs=0 +R0 Z A lvsres w=2.6e-07 l=6e-07 +.ENDS + +.SUBCKT RSC_IHPSG13_MX2IX1 A0 A1 S ZN VDD VSS +MP4 SN S VDD VDD sg13_lv_pmos m=1 w=645.000n l=130.00n ng=1 nrd=0 nrs=0 +MP3 ZN SN net12 VDD sg13_lv_pmos m=1 w=985.000n l=130.00n ng=1 nrd=0 nrs=0 +MP2 net12 A1 VDD VDD sg13_lv_pmos m=1 w=985.000n l=130.00n ng=1 nrd=0 ++ nrs=0 +MP1 ZN S net17 VDD sg13_lv_pmos m=1 w=985.000n l=130.00n ng=1 nrd=0 nrs=0 +MP0 net17 A0 VDD VDD sg13_lv_pmos m=1 w=985.000n l=130.00n ng=1 nrd=0 ++ nrs=0 +MN5 SN S VSS VSS sg13_lv_nmos m=1 w=480.00n l=130.00n ng=1 nrd=0 nrs=0 +MN3 net13 A1 VSS VSS sg13_lv_nmos m=1 w=480.00n l=130.00n ng=1 nrd=0 ++ nrs=0 +MN2 ZN S net13 VSS sg13_lv_nmos m=1 w=480.00n l=130.00n ng=1 nrd=0 nrs=0 +MN1 net15 A0 VSS VSS sg13_lv_nmos m=1 w=480.00n l=130.00n ng=1 nrd=0 ++ nrs=0 +MN0 ZN SN net15 VSS sg13_lv_nmos m=1 w=480.00n l=130.00n ng=1 nrd=0 nrs=0 +.ENDS +.SUBCKT RM_IHPSG13_256x16_c2_1P_DLY_MUX A SEL Z VDD VSS +XI11 net4 Z VDD VSS / RSC_IHPSG13_CINVX2 +XI8 A D<3> SEL net4 VDD VSS / RSC_IHPSG13_MX2IX1 +XI20<3> D<2> D<3> VDD VSS / RSC_IHPSG13_CDLYX1 +XI20<2> D<1> D<2> VDD VSS / RSC_IHPSG13_CDLYX1 +XI20<1> A D<1> VDD VSS / RSC_IHPSG13_CDLYX1 +.ENDS +.SUBCKT RSC_IHPSG13_DFNQX2 CN D Q VDD VSS +MN0 Q QIN_SL VSS VSS sg13_lv_nmos m=1 w=980.00n l=130.00n ng=1 nrd=0 ++ nrs=0 +MN10 QIN_SL CNN net21 VSS sg13_lv_nmos m=1 w=850.00n l=130.00n ng=1 nrd=0 ++ nrs=0 +MN11 net21 QI_MS VSS VSS sg13_lv_nmos m=1 w=850.00n l=130.00n ng=1 ++ nrd=0 nrs=0 +MN7 net30 QI_MS VSS VSS sg13_lv_nmos m=1 w=480.00n l=130.00n ng=1 ++ nrd=0 nrs=0 +MN6 QIN_MS CNN net30 VSS sg13_lv_nmos m=1 w=480.00n l=130.00n ng=1 nrd=0 ++ nrs=0 +MN3 QI_MS QIN_MS VSS VSS sg13_lv_nmos m=1 w=480.00n l=130.00n ng=1 ++ nrd=0 nrs=0 +MN12 CNN CN VSS VSS sg13_lv_nmos m=1 w=495.000n l=130.00n ng=1 nrd=0 ++ nrs=0 +MN9 net37 D VSS VSS sg13_lv_nmos m=1 w=870.00n l=130.00n ng=1 nrd=0 ++ nrs=0 +MN8 QIN_MS CN net37 VSS sg13_lv_nmos m=1 w=870.00n l=130.00n ng=1 nrd=0 ++ nrs=0 +MN5 QIN_SL CN net25 VSS sg13_lv_nmos m=1 w=480.00n l=130.00n ng=1 nrd=0 ++ nrs=0 +MN4 net25 QI_SL VSS VSS sg13_lv_nmos m=1 w=480.00n l=130.00n ng=1 ++ nrd=0 nrs=0 +MN2 QI_SL QIN_SL VSS VSS sg13_lv_nmos m=1 w=480.00n l=130.00n ng=1 ++ nrd=0 nrs=0 +MP0 Q QIN_SL VDD VDD sg13_lv_pmos m=1 w=1.62u l=130.00n ng=1 nrd=0 ++ nrs=0 +MP6 QI_MS QIN_MS VDD VDD sg13_lv_pmos m=1 w=480.00n l=130.00n ng=1 ++ nrd=0 nrs=0 +MP3 QIN_SL CNN net27 VDD sg13_lv_pmos m=1 w=480.00n l=130.00n ng=1 nrd=0 ++ nrs=0 +MP2 net27 QI_SL VDD VDD sg13_lv_pmos m=1 w=480.00n l=130.00n ng=1 ++ nrd=0 nrs=0 +MP10 net36 D VDD VDD sg13_lv_pmos m=1 w=975.000n l=130.00n ng=1 nrd=0 ++ nrs=0 +MP11 QIN_MS CNN net36 VDD sg13_lv_pmos m=1 w=975.000n l=130.00n ng=1 nrd=0 ++ nrs=0 +MP4 net32 QI_MS VDD VDD sg13_lv_pmos m=1 w=480.00n l=130.00n ng=1 ++ nrd=0 nrs=0 +MP5 QIN_MS CN net32 VDD sg13_lv_pmos m=1 w=480.00n l=130.00n ng=1 nrd=0 ++ nrs=0 +MP7 QI_SL QIN_SL VDD VDD sg13_lv_pmos m=1 w=480.00n l=130.00n ng=1 ++ nrd=0 nrs=0 +MP12 CNN CN VDD VDD sg13_lv_pmos m=1 w=480.00n l=130.00n ng=1 nrd=0 ++ nrs=0 +MP9 QIN_SL CN net19 VDD sg13_lv_pmos m=1 w=990.00n l=130.00n ng=1 nrd=0 ++ nrs=0 +MP8 net19 QI_MS VDD VDD sg13_lv_pmos m=1 w=990.00n l=130.00n ng=1 ++ nrd=0 nrs=0 +.ENDS +.SUBCKT RSC_IHPSG13_CNAND2X2 A B Z VDD VSS +MN0 Z B net6 VSS sg13_lv_nmos m=1 w=980.00n l=130.00n ng=1 nrd=0 nrs=0 +MN1 net6 A VSS VSS sg13_lv_nmos m=1 w=980.00n l=130.00n ng=1 nrd=0 ++ nrs=0 +MP1 Z B VDD VDD sg13_lv_pmos m=1 w=1.62u l=130.00n ng=1 nrd=0 nrs=0 +MP0 Z A VDD VDD sg13_lv_pmos m=1 w=1.62u l=130.00n ng=1 nrd=0 nrs=0 +.ENDS +.SUBCKT RSC_IHPSG13_CGATEPX4 CP E Q VDD VSS +MN1 net08 QIN VSS VSS sg13_lv_nmos m=1 w=480.00n l=130.00n ng=1 nrd=0 ++ nrs=0 +MN2 net019 net08 VSS VSS sg13_lv_nmos m=1 w=480.00n l=130.00n ng=1 ++ nrd=0 nrs=0 +MN3 QIN CP net019 VSS sg13_lv_nmos m=1 w=480.00n l=130.00n ng=1 nrd=0 nrs=0 +MN6 Q net015 VSS VSS sg13_lv_nmos m=1 w=1.41u l=130.00n ng=2 nrd=0 ++ nrs=0 +MN5 net015 net08 net018 VSS sg13_lv_nmos m=1 w=980.00n l=130.00n ng=1 ++ nrd=0 nrs=0 +MN8 QIN CPN net023 VSS sg13_lv_nmos m=1 w=870.00n l=130.00n ng=1 nrd=0 ++ nrs=0 +MN7 net023 E VSS VSS sg13_lv_nmos m=1 w=870.00n l=130.00n ng=1 nrd=0 ++ nrs=0 +MN4 net018 CP VSS VSS sg13_lv_nmos m=1 w=980.00n l=130.00n ng=1 nrd=0 ++ nrs=0 +MN0 CPN CP VSS VSS sg13_lv_nmos m=1 w=500.0n l=130.00n ng=1 nrd=0 nrs=0 +MP3 net08 QIN VDD VDD sg13_lv_pmos m=1 w=480.00n l=130.00n ng=1 nrd=0 ++ nrs=0 +MP2 QIN CPN net017 VDD sg13_lv_pmos m=1 w=480.00n l=130.00n ng=1 nrd=0 ++ nrs=0 +MP1 net017 net08 VDD VDD sg13_lv_pmos m=1 w=480.00n l=130.00n ng=1 ++ nrd=0 nrs=0 +MP0 CPN CP VDD VDD sg13_lv_pmos m=1 w=500.0n l=130.00n ng=1 nrd=0 nrs=0 +MP8 QIN CP net024 VDD sg13_lv_pmos m=1 w=975.000n l=130.00n ng=1 nrd=0 ++ nrs=0 +MP7 net024 E VDD VDD sg13_lv_pmos m=1 w=975.000n l=130.00n ng=1 nrd=0 ++ nrs=0 +MP4 net015 CP VDD VDD sg13_lv_pmos m=1 w=1.27u l=130.00n ng=1 nrd=0 ++ nrs=0 +MP6 Q net015 VDD VDD sg13_lv_pmos m=1 w=3.24u l=130.00n ng=2 nrd=0 ++ nrs=0 +MP5 net015 net08 VDD VDD sg13_lv_pmos m=1 w=1.27u l=130.00n ng=1 nrd=0 ++ nrs=0 +.ENDS +.SUBCKT RSC_IHPSG13_CBUFX8 A Z VDD VSS +MP0 net4 A VDD VDD sg13_lv_pmos m=1 w=3.24u l=130.00n ng=2 nrd=0 nrs=0 +MP1 Z net4 VDD VDD sg13_lv_pmos m=1 w=6.48u l=130.00n ng=4 nrd=0 nrs=0 +MN1 Z net4 VSS VSS sg13_lv_nmos m=1 w=2.82u l=130.00n ng=4 nrd=0 nrs=0 +MN0 net4 A VSS VSS sg13_lv_nmos m=1 w=1.41u l=130.00n ng=2 nrd=0 nrs=0 +.ENDS +.SUBCKT RSC_IHPSG13_CDLYX2 A Z VDD VSS +MN2 net4 A net9 VSS sg13_lv_nmos m=1 w=320.00n l=200.0n ng=1 nrd=0 nrs=0 +MN0 Z net4 VSS VSS sg13_lv_nmos m=1 w=705.000n l=130.00n ng=1 nrd=0 ++ nrs=0 +MN1 net9 A VSS VSS sg13_lv_nmos m=1 w=320.00n l=200.0n ng=1 nrd=0 nrs=0 +MP2 net4 A net10 VDD sg13_lv_pmos m=1 w=1.2u l=200.0n ng=1 nrd=0 nrs=0 +MP1 net10 A VDD VDD sg13_lv_pmos m=1 w=1.2u l=200.0n ng=1 nrd=0 nrs=0 +MP0 Z net4 VDD VDD sg13_lv_pmos m=1 w=1.62u l=130.00n ng=1 nrd=0 nrs=0 +.ENDS +.SUBCKT RSC_IHPSG13_MX2X2 A0 A1 S Z VDD VSS +MP6 Z net010 VDD VDD sg13_lv_pmos m=1 w=1.62u l=130.00n ng=1 nrd=0 ++ nrs=0 +MP4 SN S VDD VDD sg13_lv_pmos m=1 w=645.000n l=130.00n ng=1 nrd=0 nrs=0 +MP3 net010 SN net12 VDD sg13_lv_pmos m=1 w=985.000n l=130.00n ng=1 nrd=0 ++ nrs=0 +MP2 net12 A1 VDD VDD sg13_lv_pmos m=1 w=985.000n l=130.00n ng=1 nrd=0 ++ nrs=0 +MP1 net010 S net17 VDD sg13_lv_pmos m=1 w=985.000n l=130.00n ng=1 nrd=0 ++ nrs=0 +MP0 net17 A0 VDD VDD sg13_lv_pmos m=1 w=985.000n l=130.00n ng=1 nrd=0 ++ nrs=0 +MN6 Z net010 VSS VSS sg13_lv_nmos m=1 w=705.000n l=130.00n ng=1 nrd=0 ++ nrs=0 +MN5 SN S VSS VSS sg13_lv_nmos m=1 w=560.00n l=130.00n ng=1 nrd=0 nrs=0 +MN3 net13 A1 VSS VSS sg13_lv_nmos m=1 w=560.00n l=130.00n ng=1 nrd=0 ++ nrs=0 +MN2 net010 S net13 VSS sg13_lv_nmos m=1 w=560.00n l=130.00n ng=1 nrd=0 ++ nrs=0 +MN1 net15 A0 VSS VSS sg13_lv_nmos m=1 w=560.00n l=130.00n ng=1 nrd=0 ++ nrs=0 +MN0 net010 SN net15 VSS sg13_lv_nmos m=1 w=560.00n l=130.00n ng=1 nrd=0 ++ nrs=0 +.ENDS +.SUBCKT RSC_IHPSG13_AND2X2 A B Z VDD VSS +MN3 Z net6 VSS VSS sg13_lv_nmos m=1 w=980.00n l=130.00n ng=1 nrd=0 ++ nrs=0 +MN4 net9 B VSS VSS sg13_lv_nmos m=1 w=500.0n l=130.00n ng=1 nrd=0 nrs=0 +MN6 net6 A net9 VSS sg13_lv_nmos m=1 w=500.0n l=130.00n ng=1 nrd=0 nrs=0 +MP2 Z net6 VDD VDD sg13_lv_pmos m=1 w=1.62u l=130.00n ng=1 nrd=0 nrs=0 +MP0 net6 B VDD VDD sg13_lv_pmos m=1 w=860.00n l=130.00n ng=1 nrd=0 ++ nrs=0 +MP1 net6 A VDD VDD sg13_lv_pmos m=1 w=860.00n l=130.00n ng=1 nrd=0 ++ nrs=0 +.ENDS +.SUBCKT RSC_IHPSG13_TIEL Z VDD VSS +MN0 Z net2 VSS VSS sg13_lv_nmos m=1 w=480.00n l=130.00n ng=1 nrd=0 ++ nrs=0 +MP0 net2 net2 VDD VDD sg13_lv_pmos m=1 w=480.00n l=130.00n ng=1 nrd=0 ++ nrs=0 +.ENDS +.SUBCKT RSC_IHPSG13_XOR2X2 A B Z VDD VSS +MP8 net012 B net7 VDD sg13_lv_pmos m=1 w=825.000n l=130.00n ng=1 nrd=0 ++ nrs=0 +MP7 net011 net3 net012 VDD sg13_lv_pmos m=1 w=825.000n l=130.00n ng=1 ++ nrd=0 nrs=0 +MP6 Z net012 VDD VDD sg13_lv_pmos m=1 w=1.535u l=130.00n ng=1 nrd=0 ++ nrs=0 +MP2 net7 A VDD VDD sg13_lv_pmos m=1 w=825.000n l=130.00n ng=1 nrd=0 ++ nrs=0 +MP4 net011 net7 VDD VDD sg13_lv_pmos m=1 w=825.000n l=130.00n ng=1 ++ nrd=0 nrs=0 +MP5 net3 B VDD VDD sg13_lv_pmos m=1 w=580.00n l=130.00n ng=1 nrd=0 ++ nrs=0 +MN7 net012 B net011 VSS sg13_lv_nmos m=1 w=555.000n l=130.00n ng=1 nrd=0 ++ nrs=0 +MN6 net7 net3 net012 VSS sg13_lv_nmos m=1 w=555.000n l=130.00n ng=1 nrd=0 ++ nrs=0 +MN5 Z net012 VSS VSS sg13_lv_nmos m=1 w=775.000n l=130.00n ng=1 nrd=0 ++ nrs=0 +MN2 net7 A VSS VSS sg13_lv_nmos m=1 w=555.000n l=130.00n ng=1 nrd=0 ++ nrs=0 +MN4 net3 B VSS VSS sg13_lv_nmos m=1 w=480.00n l=130.00n ng=1 nrd=0 ++ nrs=0 +MN3 net011 net7 VSS VSS sg13_lv_nmos m=1 w=555.000n l=130.00n ng=1 ++ nrd=0 nrs=0 +.ENDS +.SUBCKT RSC_IHPSG13_OA12X1 A B C Z VDD VSS +MN2 net7 C VSS VSS sg13_lv_nmos m=1 w=980.00n l=130.00n ng=1 nrd=0 ++ nrs=0 +MN3 Z net17 VSS VSS sg13_lv_nmos m=1 w=500.0n l=130.00n ng=1 nrd=0 ++ nrs=0 +MN1 net17 B net7 VSS sg13_lv_nmos m=1 w=980.00n l=130.00n ng=1 nrd=0 nrs=0 +MN0 net17 A net7 VSS sg13_lv_nmos m=1 w=980.00n l=130.00n ng=1 nrd=0 nrs=0 +MP0 net24 A VDD VDD sg13_lv_pmos m=1 w=1.62u l=130.00n ng=1 nrd=0 nrs=0 +MP3 Z net17 VDD VDD sg13_lv_pmos m=1 w=905.000n l=130.00n ng=1 nrd=0 ++ nrs=0 +MP1 net17 B net24 VDD sg13_lv_pmos m=1 w=1.62u l=130.00n ng=1 nrd=0 nrs=0 +MP2 net17 C VDD VDD sg13_lv_pmos m=1 w=905.000n l=130.00n ng=1 nrd=0 ++ nrs=0 +.ENDS +.SUBCKT RM_IHPSG13_256x16_c2_1P_CTRL ACLK_N BIST_CK_I BIST_CS_I BIST_EN BIST_RE_I ++ BIST_WE_I B_TIEL_O CK_I CS_I DCLK ECLK PULSE_H PULSE_L PULSE_O RCLK RE_I ++ ROW_CS WCLK WE_I VDD VSS +XI17 ck_regs we col_we VDD VSS / RSC_IHPSG13_DFNQX2 +XI16 ck_regs re col_re VDD VSS / RSC_IHPSG13_DFNQX2 +XI18 ck_regs cs net7 VDD VSS / RSC_IHPSG13_DFNQX2 +XI71 ACLK_N net012 PULSE_O VDD VSS / RSC_IHPSG13_DFNQX2 +XI77 col_we net9 net016 VDD VSS / RSC_IHPSG13_CNAND2X2 +XI76 col_re net9 net018 VDD VSS / RSC_IHPSG13_CNAND2X2 +XI15 ck_dly WEorREandCS aclk VDD VSS / RSC_IHPSG13_CGATEPX4 +XI14 ck WEandCS DCLK VDD VSS / RSC_IHPSG13_CGATEPX4 +XI60 net7 ROW_CS VDD VSS / RSC_IHPSG13_CBUFX8 +XI73 PULSE_O net012 VDD VSS / RSC_IHPSG13_CINVX2 +XI8 net9 net8 VDD VSS / RSC_IHPSG13_CINVX2 +XI64 ck ck_dly VDD VSS / RSC_IHPSG13_CDLYX2 +XI86 CS_I BIST_CS_I BIST_EN cs VDD VSS / RSC_IHPSG13_MX2X2 +XI87 CK_I BIST_CK_I BIST_EN ck VDD VSS / RSC_IHPSG13_MX2X2 +XI85 WE_I BIST_WE_I BIST_EN we VDD VSS / RSC_IHPSG13_MX2X2 +XI84 RE_I BIST_RE_I BIST_EN re VDD VSS / RSC_IHPSG13_MX2X2 +XI22 we cs WEandCS VDD VSS / RSC_IHPSG13_AND2X2 +XBM_TIEL B_TIEL_O VDD VSS / RSC_IHPSG13_TIEL +XI48 ck_dly ck_regs VDD VSS / RSC_IHPSG13_CINVX4 +XI81 net016 WCLK VDD VSS / RSC_IHPSG13_CINVX4 +XI80 net018 RCLK VDD VSS / RSC_IHPSG13_CINVX4 +XI78 net8 net020 VDD VSS / RSC_IHPSG13_CINVX4 +XI6 PULSE_L PULSE_H net9 VDD VSS / RSC_IHPSG13_XOR2X2 +XI79 net020 ECLK VDD VSS / RSC_IHPSG13_CINVX8 +XI63 aclk ACLK_N VDD VSS / RSC_IHPSG13_CINVX8 +XI21 re we cs WEorREandCS VDD VSS / RSC_IHPSG13_OA12X1 +.ENDS +.SUBCKT RM_IHPSG13_256x16_c2_1P_COLDEC2 ACLK_N ADDR<1> ADDR<0> ADDR_COL<1> ADDR_COL<0> ++ ADDR_DEC<7> ADDR_DEC<6> ADDR_DEC<5> ADDR_DEC<4> ADDR_DEC<3> ADDR_DEC<2> ++ ADDR_DEC<1> ADDR_DEC<0> BIST_ADDR<1> BIST_ADDR<0> BIST_EN_I VDD VSS +XI14<5> VDD VSS / RSC_IHPSG13_FILLCAP4 +XI14<4> VDD VSS / RSC_IHPSG13_FILLCAP4 +XI14<3> VDD VSS / RSC_IHPSG13_FILLCAP4 +XI14<2> VDD VSS / RSC_IHPSG13_FILLCAP4 +XI14<1> VDD VSS / RSC_IHPSG13_FILLCAP4 +XDFF<1> BIST_EN_I BIST_ADDR<1> ACLK_N ADDR<1> padr_int<1> net6<0> VDD ++ VSS / RSC_IHPSG13_DFNQMX2IX1 +XDFF<0> BIST_EN_I BIST_ADDR<0> ACLK_N ADDR<0> padr_int<0> net6<1> VDD ++ VSS / RSC_IHPSG13_DFNQMX2IX1 +XI1<3> PADR<1> PADR<0> addr_n<3> VDD VSS / RSC_IHPSG13_NAND2X2 +XI1<2> PADR<1> NADR<0> addr_n<2> VDD VSS / RSC_IHPSG13_NAND2X2 +XI1<1> NADR<1> PADR<0> addr_n<1> VDD VSS / RSC_IHPSG13_NAND2X2 +XI1<0> NADR<1> NADR<0> addr_n<0> VDD VSS / RSC_IHPSG13_NAND2X2 +XI16<37> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI16<36> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI16<35> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI16<34> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI16<33> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI16<32> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI16<31> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI16<30> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI16<29> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI16<28> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI16<27> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI16<26> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI16<25> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI16<24> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI16<23> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI16<22> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI16<21> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI16<20> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI16<19> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI16<18> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI16<17> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI16<16> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI16<15> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI16<14> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI16<13> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI16<12> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI16<11> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI16<10> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI16<9> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI16<8> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI16<7> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI16<6> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI16<5> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI16<4> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI16<3> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI16<2> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI16<1> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI3<1> padr_int<1> NADR<1> VDD VSS / RSC_IHPSG13_INVX2 +XI3<0> padr_int<0> NADR<0> VDD VSS / RSC_IHPSG13_INVX2 +XI13<1> NADR<1> PADR<1> VDD VSS / RSC_IHPSG13_INVX2 +XI13<0> NADR<0> PADR<0> VDD VSS / RSC_IHPSG13_INVX2 +XI2<3> addr_n<3> ADDR_DEC<3> VDD VSS / RSC_IHPSG13_INVX2 +XI2<2> addr_n<2> ADDR_DEC<2> VDD VSS / RSC_IHPSG13_INVX2 +XI2<1> addr_n<1> ADDR_DEC<1> VDD VSS / RSC_IHPSG13_INVX2 +XI2<0> addr_n<0> ADDR_DEC<0> VDD VSS / RSC_IHPSG13_INVX2 +XI15<1> ADDR_COL<1> VDD VSS / RSC_IHPSG13_TIEL +XI15<0> ADDR_COL<0> VDD VSS / RSC_IHPSG13_TIEL +XI17<3> ADDR_DEC<7> VDD VSS / RSC_IHPSG13_TIEL +XI17<2> ADDR_DEC<6> VDD VSS / RSC_IHPSG13_TIEL +XI17<1> ADDR_DEC<5> VDD VSS / RSC_IHPSG13_TIEL +XI17<0> ADDR_DEC<4> VDD VSS / RSC_IHPSG13_TIEL +.ENDS +.SUBCKT RSC_IHPSG13_NOR2X2 A B Z VDD VSS +MP1 Z B net9 VDD sg13_lv_pmos m=1 w=1.62u l=130.00n ng=1 nrd=0 nrs=0 +MP0 net9 A VDD VDD sg13_lv_pmos m=1 w=1.62u l=130.00n ng=1 nrd=0 nrs=0 +MN0 Z B VSS VSS sg13_lv_nmos m=1 w=980.00n l=130.00n ng=1 nrd=0 nrs=0 +MN1 Z A VSS VSS sg13_lv_nmos m=1 w=980.00n l=130.00n ng=1 nrd=0 nrs=0 +.ENDS +.SUBCKT RSC_IHPSG13_CINVX4_WN A Z VDD VSS +MN0 Z A VSS VSS sg13_lv_nmos m=1 w=705.000n l=130.00n ng=1 nrd=0 nrs=0 +MP0 Z A VDD VDD sg13_lv_pmos m=1 w=3.24u l=130.00n ng=2 nrd=0 nrs=0 +.ENDS +.SUBCKT RM_IHPSG13_256x16_c2_1P_BLDRV BLC BLC_SEL BLT BLT_SEL PRE_N SEL_P WR_ONE WR_ZERO ++ VDD VSS +XCDEC SEL_P WR_ZERO BLC_PMOS_DRIVE VDD VSS / RSC_IHPSG13_NAND2X2 +XTDEC SEL_P WR_ONE BLT_PMOS_DRIVE VDD VSS / RSC_IHPSG13_NAND2X2 +MTWN BLT BLT_NMOS_DRIVE VSS VSS sg13_lv_nmos m=1 w=4.82u l=130.00n ++ ng=2 nrd=0 nrs=0 +MCWN BLC BLC_NMOS_DRIVE VSS VSS sg13_lv_nmos m=1 w=4.82u l=130.00n ++ ng=2 nrd=0 nrs=0 +MCWP BLC BLC_PMOS_DRIVE VDD VDD sg13_lv_pmos m=1 w=1.5u l=130.00n ng=1 ++ nrd=0 nrs=0 +MTWP BLT BLT_PMOS_DRIVE VDD VDD sg13_lv_pmos m=1 w=1.5u l=130.00n ng=1 ++ nrd=0 nrs=0 +MTSP BLT_SEL SEL_N BLT VDD sg13_lv_pmos m=1 w=1.5u l=130.00n ng=1 nrd=0 ++ nrs=0 +MTPR BLT PRE_N VDD VDD sg13_lv_pmos m=1 w=3.000u l=130.00n ng=2 nrd=0 ++ nrs=0 +MCSP BLC_SEL SEL_N BLC VDD sg13_lv_pmos m=1 w=1.5u l=130.00n ng=1 nrd=0 ++ nrs=0 +MCPR BLC PRE_N VDD VDD sg13_lv_pmos m=1 w=3.000u l=130.00n ng=2 nrd=0 ++ nrs=0 +XI86 SEL_P SEL_N VDD VSS / RSC_IHPSG13_INVX2 +XTINV BLC_PMOS_DRIVE BLT_NMOS_DRIVE VDD VSS / RSC_IHPSG13_INVX2 +XCINV BLT_PMOS_DRIVE BLC_NMOS_DRIVE VDD VSS / RSC_IHPSG13_INVX2 +.ENDS +.SUBCKT RSC_IHPSG13_TIEH Z VDD VSS +MN0 net2 net2 VSS VSS sg13_lv_nmos m=1 w=480.00n l=130.00n ng=1 nrd=0 ++ nrs=0 +MP0 Z net2 VDD VDD sg13_lv_pmos m=1 w=480.00n l=130.00n ng=1 nrd=0 ++ nrs=0 +.ENDS +.SUBCKT RSC_IHPSG13_MET3RES A B +R0 B A lvsres w=2.6e-07 l=6e-07 +.ENDS +.SUBCKT RSC_IHPSG13_DFPQD_MSAFFX2 CP DN DP QN QP VDD VSS +MN12 SN RN DIFFP VSS sg13_lv_nmos m=1 w=2.4u l=200.0n ng=2 nrd=0 nrs=0 +MN13 TAIL CP VSS VSS sg13_lv_nmos m=1 w=2.4u l=130.00n ng=2 nrd=0 nrs=0 +MN9 DIFFP DP TAIL VSS sg13_lv_nmos m=1 w=2.4u l=200.0n ng=2 nrd=0 nrs=0 +MN10 DIFFN DN TAIL VSS sg13_lv_nmos m=1 w=2.4u l=200.0n ng=2 nrd=0 nrs=0 +MN11 RN SN DIFFN VSS sg13_lv_nmos m=1 w=2.4u l=200.0n ng=2 nrd=0 nrs=0 +MN19 net33 SN VSS VSS sg13_lv_nmos m=1 w=980.00n l=130.00n ng=1 nrd=0 ++ nrs=0 +MN20 QN QP net37 VSS sg13_lv_nmos m=1 w=980.00n l=130.00n ng=1 nrd=0 nrs=0 +MN18 net37 RN VSS VSS sg13_lv_nmos m=1 w=980.00n l=130.00n ng=1 nrd=0 ++ nrs=0 +MN17 QP QN net33 VSS sg13_lv_nmos m=1 w=980.00n l=130.00n ng=1 nrd=0 nrs=0 +MP15 SN RN VDD VDD sg13_lv_pmos m=1 w=800.0n l=130.00n ng=1 nrd=0 nrs=0 +MP16 RN CP VDD VDD sg13_lv_pmos m=1 w=800.0n l=130.00n ng=1 nrd=0 nrs=0 +MP14 DIFFP CP VDD VDD sg13_lv_pmos m=1 w=800.0n l=130.00n ng=1 nrd=0 ++ nrs=0 +MP12 RN SN VDD VDD sg13_lv_pmos m=1 w=800.0n l=130.00n ng=1 nrd=0 nrs=0 +MP13 DIFFN CP VDD VDD sg13_lv_pmos m=1 w=800.0n l=130.00n ng=1 nrd=0 ++ nrs=0 +MP11 SN CP VDD VDD sg13_lv_pmos m=1 w=800.0n l=130.00n ng=1 nrd=0 nrs=0 +MP19 QN QP VDD VDD sg13_lv_pmos m=1 w=900.0n l=130.00n ng=1 nrd=0 nrs=0 +MP20 QP SN VDD VDD sg13_lv_pmos m=1 w=1.8u l=130.00n ng=2 nrd=0 nrs=0 +MP18 QN RN VDD VDD sg13_lv_pmos m=1 w=1.8u l=130.00n ng=2 nrd=0 nrs=0 +MP17 QP QN VDD VDD sg13_lv_pmos m=1 w=900.0n l=130.00n ng=1 nrd=0 nrs=0 +.ENDS +.SUBCKT RSC_IHPSG13_CBUFX2 A Z VDD VSS +MN1 Z net4 VSS VSS sg13_lv_nmos m=1 w=705.000n l=130.00n ng=1 nrd=0 ++ nrs=0 +MN0 net4 A VSS VSS sg13_lv_nmos m=1 w=540.00n l=130.00n ng=1 nrd=0 ++ nrs=0 +MP1 Z net4 VDD VDD sg13_lv_pmos m=1 w=1.62u l=130.00n ng=1 nrd=0 nrs=0 +MP0 net4 A VDD VDD sg13_lv_pmos m=1 w=1.1u l=130.00n ng=1 nrd=0 nrs=0 +.ENDS +.SUBCKT RSC_IHPSG13_INVX4 A Z VDD VSS +MN0 Z A VSS VSS sg13_lv_nmos m=1 w=1.96u l=130.00n ng=2 nrd=0 nrs=0 +MP0 Z A VDD VDD sg13_lv_pmos m=1 w=3.24u l=130.00n ng=2 nrd=0 nrs=0 +.ENDS +.SUBCKT RM_IHPSG13_256x16_c2_1P_COLCTRL2 A_ADDR_DEC<3> A_ADDR_DEC<2> A_ADDR_DEC<1> ++ A_ADDR_DEC<0> A_BIST_BM_I A_BIST_DW_I A_BIST_EN_I A_BLC<3> A_BLC<2> A_BLC<1> ++ A_BLC<0> A_BLT<3> A_BLT<2> A_BLT<1> A_BLT<0> A_BM_I A_DCLK_B_L A_DCLK_B_R ++ A_DCLK_L A_DCLK_R A_DR_O A_DW_I A_RCLK_B_L A_RCLK_B_R A_RCLK_L A_RCLK_R ++ A_TIEH_O A_WCLK_B_L A_WCLK_B_R A_WCLK_L A_WCLK_R VDD VSS +XA_DREG A_BIST_EN_I A_BIST_DW_I A_DCLK_B_L A_DW_I A_DI_R net22 VDD VSS ++ / RSC_IHPSG13_DFNQMX2IX1 +XA_BREG A_BIST_EN_I A_BIST_BM_I A_DCLK_B_L A_BM_I A_BM_R net23 VDD VSS ++ / RSC_IHPSG13_DFNQMX2IX1 +XA_CAPS<5> VDD VSS / RSC_IHPSG13_FILLCAP4 +XA_CAPS<4> VDD VSS / RSC_IHPSG13_FILLCAP4 +XA_CAPS<3> VDD VSS / RSC_IHPSG13_FILLCAP4 +XA_CAPS<2> VDD VSS / RSC_IHPSG13_FILLCAP4 +XA_CAPS<1> VDD VSS / RSC_IHPSG13_FILLCAP4 +XA_I80 A_WCLK_B_R A_RCLK_B_R net21 VDD VSS / RSC_IHPSG13_AND2X2 +XA_I75 A_DI_R A_DO_WRITE_P A_WR_ONE VDD VSS / RSC_IHPSG13_AND2X2 +XA_I76 A_DI_N A_DO_WRITE_P A_WR_ZERO VDD VSS / RSC_IHPSG13_AND2X2 +XA_I44 A_WCLK_B_R A_BM_N A_DO_WRITE_P VDD VSS / RSC_IHPSG13_NOR2X2 +XA_I81 net21 A_PRE_N VDD VSS / RSC_IHPSG13_CINVX4_WN +XA_BLTMUX<3> A_BLC<3> A_BLC_SEL A_BLT<3> A_BLT_SEL A_PRE_N A_ADDR_DEC<3> ++ A_WR_ONE A_WR_ZERO VDD VSS / RM_IHPSG13_256x16_c2_1P_BLDRV +XA_BLTMUX<2> A_BLC<2> A_BLC_SEL A_BLT<2> A_BLT_SEL A_PRE_N A_ADDR_DEC<2> ++ A_WR_ONE A_WR_ZERO VDD VSS / RM_IHPSG13_256x16_c2_1P_BLDRV +XA_BLTMUX<1> A_BLC<1> A_BLC_SEL A_BLT<1> A_BLT_SEL A_PRE_N A_ADDR_DEC<1> ++ A_WR_ONE A_WR_ZERO VDD VSS / RM_IHPSG13_256x16_c2_1P_BLDRV +XA_BLTMUX<0> A_BLC<0> A_BLC_SEL A_BLT<0> A_BLT_SEL A_PRE_N A_ADDR_DEC<0> ++ A_WR_ONE A_WR_ZERO VDD VSS / RM_IHPSG13_256x16_c2_1P_BLDRV +XA_BM_TIEH A_TIEH_O VDD VSS / RSC_IHPSG13_TIEH +XA_I89 A_DCLK_B_L A_DCLK_B_R / RSC_IHPSG13_MET3RES +XA_I88 A_DCLK_L A_DCLK_R / RSC_IHPSG13_MET3RES +XA_I87 A_WCLK_L A_WCLK_R / RSC_IHPSG13_MET3RES +XA_I91 A_RCLK_B_R A_RCLK_B_L / RSC_IHPSG13_MET3RES +XA_R2 A_RCLK_R A_RCLK_L / RSC_IHPSG13_MET3RES +XA_I90 A_WCLK_B_R A_WCLK_B_L / RSC_IHPSG13_MET3RES +XA_ISENSE A_SAE A_BLC_SEL A_BLT_SEL net19 net20 VDD VSS / ++ RSC_IHPSG13_DFPQD_MSAFFX2 +XA_I78 A_RCLK_B_R A_SAE VDD VSS / RSC_IHPSG13_CBUFX2 +XA_I83 A_BM_R A_BM_N VDD VSS / RSC_IHPSG13_INVX2 +XA_I49 A_DI_R A_DI_N VDD VSS / RSC_IHPSG13_INVX2 +XA_I51 net19 A_DR_O VDD VSS / RSC_IHPSG13_INVX4 +XA_I69 A_DCLK_L A_DCLK_B_L VDD VSS / RSC_IHPSG13_CINVX2 +XA_I50 A_WCLK_L A_WCLK_B_R VDD VSS / RSC_IHPSG13_CINVX2 +XA_EBUF A_RCLK_R A_RCLK_B_R VDD VSS / RSC_IHPSG13_CINVX2 +.ENDS +.SUBCKT RM_IHPSG13_256x16_c2_1P_COLDRV13_FILL4 VDD VSS +XI0<9> VDD VSS / RSC_IHPSG13_FILLCAP4 +XI0<8> VDD VSS / RSC_IHPSG13_FILLCAP4 +XI0<7> VDD VSS / RSC_IHPSG13_FILLCAP4 +XI0<6> VDD VSS / RSC_IHPSG13_FILLCAP4 +XI0<5> VDD VSS / RSC_IHPSG13_FILLCAP4 +XI0<4> VDD VSS / RSC_IHPSG13_FILLCAP4 +XI0<3> VDD VSS / RSC_IHPSG13_FILLCAP4 +XI0<2> VDD VSS / RSC_IHPSG13_FILLCAP4 +XI0<1> VDD VSS / RSC_IHPSG13_FILLCAP4 +.ENDS +.SUBCKT RM_IHPSG13_256x16_c2_1P_COLDRV13_FILL4C2 VDD VSS +XI0<2> VDD VSS / RSC_IHPSG13_FILLCAP4 +XI0<1> VDD VSS / RSC_IHPSG13_FILLCAP4 +.ENDS + + +.SUBCKT RM_IHPSG13_256x16_c2_1P_COLDEC4 ACLK_N ADDR<3> ADDR<2> ADDR<1> ADDR<0> ++ ADDR_COL<1> ADDR_COL<0> ADDR_DEC<7> ADDR_DEC<6> ADDR_DEC<5> ADDR_DEC<4> ++ ADDR_DEC<3> ADDR_DEC<2> ADDR_DEC<1> ADDR_DEC<0> BIST_ADDR<3> BIST_ADDR<2> ++ BIST_ADDR<1> BIST_ADDR<0> BIST_EN_I VDD VSS +XI15 ADDR_COL<1> VDD VSS / RSC_IHPSG13_TIEL +XI14 addr_int ADDR_COL<0> VDD VSS / RSC_IHPSG13_CBUFX2 +XDFF<3> BIST_EN_I BIST_ADDR<3> ACLK_N ADDR<3> addr_int net7<0> VDD VSS ++ / RSC_IHPSG13_DFNQMX2IX1 +XDFF<2> BIST_EN_I BIST_ADDR<2> ACLK_N ADDR<2> padr_int<2> net7<1> VDD ++ VSS / RSC_IHPSG13_DFNQMX2IX1 +XDFF<1> BIST_EN_I BIST_ADDR<1> ACLK_N ADDR<1> padr_int<1> net7<2> VDD ++ VSS / RSC_IHPSG13_DFNQMX2IX1 +XDFF<0> BIST_EN_I BIST_ADDR<0> ACLK_N ADDR<0> padr_int<0> net7<3> VDD ++ VSS / RSC_IHPSG13_DFNQMX2IX1 +XI1<7> PADR<0> PADR<1> PADR<2> addr_n<7> VDD VSS / RSC_IHPSG13_NAND3X2 +XI1<6> NADR<0> PADR<1> PADR<2> addr_n<6> VDD VSS / RSC_IHPSG13_NAND3X2 +XI1<5> PADR<0> NADR<1> PADR<2> addr_n<5> VDD VSS / RSC_IHPSG13_NAND3X2 +XI1<4> NADR<0> NADR<1> PADR<2> addr_n<4> VDD VSS / RSC_IHPSG13_NAND3X2 +XI1<3> PADR<0> PADR<1> NADR<2> addr_n<3> VDD VSS / RSC_IHPSG13_NAND3X2 +XI1<2> NADR<0> PADR<1> NADR<2> addr_n<2> VDD VSS / RSC_IHPSG13_NAND3X2 +XI1<1> PADR<0> NADR<1> NADR<2> addr_n<1> VDD VSS / RSC_IHPSG13_NAND3X2 +XI1<0> NADR<0> NADR<1> NADR<2> addr_n<0> VDD VSS / RSC_IHPSG13_NAND3X2 +XI13<2> NADR<2> PADR<2> VDD VSS / RSC_IHPSG13_INVX2 +XI13<1> NADR<1> PADR<1> VDD VSS / RSC_IHPSG13_INVX2 +XI13<0> NADR<0> PADR<0> VDD VSS / RSC_IHPSG13_INVX2 +XI3<2> padr_int<2> NADR<2> VDD VSS / RSC_IHPSG13_INVX2 +XI3<1> padr_int<1> NADR<1> VDD VSS / RSC_IHPSG13_INVX2 +XI3<0> padr_int<0> NADR<0> VDD VSS / RSC_IHPSG13_INVX2 +XI2<7> addr_n<7> ADDR_DEC<7> VDD VSS / RSC_IHPSG13_INVX2 +XI2<6> addr_n<6> ADDR_DEC<6> VDD VSS / RSC_IHPSG13_INVX2 +XI2<5> addr_n<5> ADDR_DEC<5> VDD VSS / RSC_IHPSG13_INVX2 +XI2<4> addr_n<4> ADDR_DEC<4> VDD VSS / RSC_IHPSG13_INVX2 +XI2<3> addr_n<3> ADDR_DEC<3> VDD VSS / RSC_IHPSG13_INVX2 +XI2<2> addr_n<2> ADDR_DEC<2> VDD VSS / RSC_IHPSG13_INVX2 +XI2<1> addr_n<1> ADDR_DEC<1> VDD VSS / RSC_IHPSG13_INVX2 +XI2<0> addr_n<0> ADDR_DEC<0> VDD VSS / RSC_IHPSG13_INVX2 +XI16<3> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI16<2> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI16<1> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI17<2> VDD VSS / RSC_IHPSG13_FILLCAP4 +XI17<1> VDD VSS / RSC_IHPSG13_FILLCAP4 +.ENDS +.SUBCKT RSC_IHPSG13_AND2X4 A B Z VDD VSS +MN3 Z net6 VSS VSS sg13_lv_nmos m=1 w=1.96u l=130.00n ng=2 nrd=0 nrs=0 +MN4 net9 B VSS VSS sg13_lv_nmos m=1 w=500.0n l=130.00n ng=1 nrd=0 nrs=0 +MN6 net6 A net9 VSS sg13_lv_nmos m=1 w=500.0n l=130.00n ng=1 nrd=0 nrs=0 +MP2 Z net6 VDD VDD sg13_lv_pmos m=1 w=3.24u l=130.00n ng=2 nrd=0 nrs=0 +MP0 net6 B VDD VDD sg13_lv_pmos m=1 w=860.00n l=130.00n ng=1 nrd=0 ++ nrs=0 +MP1 net6 A VDD VDD sg13_lv_pmos m=1 w=860.00n l=130.00n ng=1 nrd=0 ++ nrs=0 +.ENDS +.SUBCKT RM_IHPSG13_256x16_c2_1P_COLCTRL4 A_ADDR_COL A_ADDR_DEC<7> A_ADDR_DEC<6> ++ A_ADDR_DEC<5> A_ADDR_DEC<4> A_ADDR_DEC<3> A_ADDR_DEC<2> A_ADDR_DEC<1> ++ A_ADDR_DEC<0> A_BIST_BM_I A_BIST_DW_I A_BIST_EN_I A_BLC<15> A_BLC<14> ++ A_BLC<13> A_BLC<12> A_BLC<11> A_BLC<10> A_BLC<9> A_BLC<8> A_BLC<7> A_BLC<6> ++ A_BLC<5> A_BLC<4> A_BLC<3> A_BLC<2> A_BLC<1> A_BLC<0> A_BLT<15> A_BLT<14> ++ A_BLT<13> A_BLT<12> A_BLT<11> A_BLT<10> A_BLT<9> A_BLT<8> A_BLT<7> A_BLT<6> ++ A_BLT<5> A_BLT<4> A_BLT<3> A_BLT<2> A_BLT<1> A_BLT<0> A_BM_I A_DCLK_B_L ++ A_DCLK_B_R A_DCLK_L A_DCLK_R A_DR_O A_DW_I A_RCLK_B_L A_RCLK_B_R A_RCLK_L ++ A_RCLK_R A_TIEH_O A_WCLK_B_L A_WCLK_B_R A_WCLK_L A_WCLK_R VDD VSS +XA_I80 A_WCLK_B_L A_RCLK_B_L net21 VDD VSS / RSC_IHPSG13_AND2X2 +XA_I76 A_DO_WRITE_P A_DI_N A_WR_ZERO VDD VSS / RSC_IHPSG13_AND2X4 +XA_I75 A_DI_R A_DO_WRITE_P A_WR_ONE VDD VSS / RSC_IHPSG13_AND2X4 +XA_CAPS<8> VDD VSS / RSC_IHPSG13_FILLCAP4 +XA_CAPS<7> VDD VSS / RSC_IHPSG13_FILLCAP4 +XA_CAPS<6> VDD VSS / RSC_IHPSG13_FILLCAP4 +XA_CAPS<5> VDD VSS / RSC_IHPSG13_FILLCAP4 +XA_CAPS<4> VDD VSS / RSC_IHPSG13_FILLCAP4 +XA_CAPS<3> VDD VSS / RSC_IHPSG13_FILLCAP4 +XA_CAPS<2> VDD VSS / RSC_IHPSG13_FILLCAP4 +XA_CAPS<1> VDD VSS / RSC_IHPSG13_FILLCAP4 +XA_I69 A_DCLK_L A_DCLK_B_L VDD VSS / RSC_IHPSG13_CINVX4 +XA_I50 A_WCLK_L A_WCLK_B_L VDD VSS / RSC_IHPSG13_CINVX4 +XA_EBUF A_RCLK_L A_RCLK_B_L VDD VSS / RSC_IHPSG13_CINVX4 +XA_INV<1> A_N0 A_P0 VDD VSS / RSC_IHPSG13_CINVX4 +XA_INV<0> A_ADDR_COL A_N0 VDD VSS / RSC_IHPSG13_CINVX4 +XA_I81<1> net21 A_PRE_N VDD VSS / RSC_IHPSG13_CINVX4_WN +XA_I81<0> net21 A_PRE_N VDD VSS / RSC_IHPSG13_CINVX4_WN +XA_BLTMUX<15> A_BLC<15> A_BLC_SEL A_BLT<15> A_BLT_SEL A_PRE_N A_SEL_P<15> ++ A_WR_ONE A_WR_ZERO VDD VSS / RM_IHPSG13_256x16_c2_1P_BLDRV +XA_BLTMUX<14> A_BLC<14> A_BLC_SEL A_BLT<14> A_BLT_SEL A_PRE_N A_SEL_P<14> ++ A_WR_ONE A_WR_ZERO VDD VSS / RM_IHPSG13_256x16_c2_1P_BLDRV +XA_BLTMUX<13> A_BLC<13> A_BLC_SEL A_BLT<13> A_BLT_SEL A_PRE_N A_SEL_P<13> ++ A_WR_ONE A_WR_ZERO VDD VSS / RM_IHPSG13_256x16_c2_1P_BLDRV +XA_BLTMUX<12> A_BLC<12> A_BLC_SEL A_BLT<12> A_BLT_SEL A_PRE_N A_SEL_P<12> ++ A_WR_ONE A_WR_ZERO VDD VSS / RM_IHPSG13_256x16_c2_1P_BLDRV +XA_BLTMUX<11> A_BLC<11> A_BLC_SEL A_BLT<11> A_BLT_SEL A_PRE_N A_SEL_P<11> ++ A_WR_ONE A_WR_ZERO VDD VSS / RM_IHPSG13_256x16_c2_1P_BLDRV +XA_BLTMUX<10> A_BLC<10> A_BLC_SEL A_BLT<10> A_BLT_SEL A_PRE_N A_SEL_P<10> ++ A_WR_ONE A_WR_ZERO VDD VSS / RM_IHPSG13_256x16_c2_1P_BLDRV +XA_BLTMUX<9> A_BLC<9> A_BLC_SEL A_BLT<9> A_BLT_SEL A_PRE_N A_SEL_P<9> A_WR_ONE ++ A_WR_ZERO VDD VSS / RM_IHPSG13_256x16_c2_1P_BLDRV +XA_BLTMUX<8> A_BLC<8> A_BLC_SEL A_BLT<8> A_BLT_SEL A_PRE_N A_SEL_P<8> A_WR_ONE ++ A_WR_ZERO VDD VSS / RM_IHPSG13_256x16_c2_1P_BLDRV +XA_BLTMUX<7> A_BLC<7> A_BLC_SEL A_BLT<7> A_BLT_SEL A_PRE_N A_SEL_P<7> A_WR_ONE ++ A_WR_ZERO VDD VSS / RM_IHPSG13_256x16_c2_1P_BLDRV +XA_BLTMUX<6> A_BLC<6> A_BLC_SEL A_BLT<6> A_BLT_SEL A_PRE_N A_SEL_P<6> A_WR_ONE ++ A_WR_ZERO VDD VSS / RM_IHPSG13_256x16_c2_1P_BLDRV +XA_BLTMUX<5> A_BLC<5> A_BLC_SEL A_BLT<5> A_BLT_SEL A_PRE_N A_SEL_P<5> A_WR_ONE ++ A_WR_ZERO VDD VSS / RM_IHPSG13_256x16_c2_1P_BLDRV +XA_BLTMUX<4> A_BLC<4> A_BLC_SEL A_BLT<4> A_BLT_SEL A_PRE_N A_SEL_P<4> A_WR_ONE ++ A_WR_ZERO VDD VSS / RM_IHPSG13_256x16_c2_1P_BLDRV +XA_BLTMUX<3> A_BLC<3> A_BLC_SEL A_BLT<3> A_BLT_SEL A_PRE_N A_SEL_P<3> A_WR_ONE ++ A_WR_ZERO VDD VSS / RM_IHPSG13_256x16_c2_1P_BLDRV +XA_BLTMUX<2> A_BLC<2> A_BLC_SEL A_BLT<2> A_BLT_SEL A_PRE_N A_SEL_P<2> A_WR_ONE ++ A_WR_ZERO VDD VSS / RM_IHPSG13_256x16_c2_1P_BLDRV +XA_BLTMUX<1> A_BLC<1> A_BLC_SEL A_BLT<1> A_BLT_SEL A_PRE_N A_SEL_P<1> A_WR_ONE ++ A_WR_ZERO VDD VSS / RM_IHPSG13_256x16_c2_1P_BLDRV +XA_BLTMUX<0> A_BLC<0> A_BLC_SEL A_BLT<0> A_BLT_SEL A_PRE_N A_SEL_P<0> A_WR_ONE ++ A_WR_ZERO VDD VSS / RM_IHPSG13_256x16_c2_1P_BLDRV +XA_R2 A_RCLK_L A_RCLK_R / RSC_IHPSG13_MET3RES +XA_I87 A_WCLK_L A_WCLK_R / RSC_IHPSG13_MET3RES +XA_I88 A_DCLK_L A_DCLK_R / RSC_IHPSG13_MET3RES +XA_I89 A_DCLK_B_L A_DCLK_B_R / RSC_IHPSG13_MET3RES +XA_I90 A_WCLK_B_L A_WCLK_B_R / RSC_IHPSG13_MET3RES +XA_I91 A_RCLK_B_L A_RCLK_B_R / RSC_IHPSG13_MET3RES +XA_ISENSE A_SAE A_BLC_SEL A_BLT_SEL net19 net20 VDD VSS / ++ RSC_IHPSG13_DFPQD_MSAFFX2 +XA_I51 net19 A_DR_O VDD VSS / RSC_IHPSG13_INVX4 +XA_I78 A_RCLK_B_L A_SAE VDD VSS / RSC_IHPSG13_CBUFX2 +XA_DREG A_BIST_EN_I A_BIST_DW_I A_DCLK_B_L A_DW_I A_DI_R net22 VDD VSS ++ / RSC_IHPSG13_DFNQMX2IX1 +XA_BREG A_BIST_EN_I A_BIST_BM_I A_DCLK_B_L A_BM_I A_BM_R net24 VDD VSS ++ / RSC_IHPSG13_DFNQMX2IX1 +XA_DEC3INV<15> net23<0> A_SEL_P<15> VDD VSS / RSC_IHPSG13_INVX2 +XA_DEC3INV<14> net23<1> A_SEL_P<14> VDD VSS / RSC_IHPSG13_INVX2 +XA_DEC3INV<13> net23<2> A_SEL_P<13> VDD VSS / RSC_IHPSG13_INVX2 +XA_DEC3INV<12> net23<3> A_SEL_P<12> VDD VSS / RSC_IHPSG13_INVX2 +XA_DEC3INV<11> net23<4> A_SEL_P<11> VDD VSS / RSC_IHPSG13_INVX2 +XA_DEC3INV<10> net23<5> A_SEL_P<10> VDD VSS / RSC_IHPSG13_INVX2 +XA_DEC3INV<9> net23<6> A_SEL_P<9> VDD VSS / RSC_IHPSG13_INVX2 +XA_DEC3INV<8> net23<7> A_SEL_P<8> VDD VSS / RSC_IHPSG13_INVX2 +XA_DEC3INV<7> net23<8> A_SEL_P<7> VDD VSS / RSC_IHPSG13_INVX2 +XA_DEC3INV<6> net23<9> A_SEL_P<6> VDD VSS / RSC_IHPSG13_INVX2 +XA_DEC3INV<5> net23<10> A_SEL_P<5> VDD VSS / RSC_IHPSG13_INVX2 +XA_DEC3INV<4> net23<11> A_SEL_P<4> VDD VSS / RSC_IHPSG13_INVX2 +XA_DEC3INV<3> net23<12> A_SEL_P<3> VDD VSS / RSC_IHPSG13_INVX2 +XA_DEC3INV<2> net23<13> A_SEL_P<2> VDD VSS / RSC_IHPSG13_INVX2 +XA_DEC3INV<1> net23<14> A_SEL_P<1> VDD VSS / RSC_IHPSG13_INVX2 +XA_DEC3INV<0> net23<15> A_SEL_P<0> VDD VSS / RSC_IHPSG13_INVX2 +XA_I83 A_BM_R A_BM_N VDD VSS / RSC_IHPSG13_INVX2 +XA_I49 A_DI_R A_DI_N VDD VSS / RSC_IHPSG13_INVX2 +XA_I70<4> VDD VSS / RSC_IHPSG13_FILLCAP8 +XA_I70<3> VDD VSS / RSC_IHPSG13_FILLCAP8 +XA_I70<2> VDD VSS / RSC_IHPSG13_FILLCAP8 +XA_I70<1> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI73<14> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI73<13> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI73<12> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI73<11> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI73<10> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI73<9> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI73<8> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI73<7> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI73<6> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI73<5> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI73<4> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI73<3> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI73<2> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI73<1> VDD VSS / RSC_IHPSG13_FILLCAP8 +XA_I44 A_BM_N A_WCLK_B_L A_DO_WRITE_P VDD VSS / RSC_IHPSG13_NOR2X2 +XA_DEC3<15> A_P0 A_ADDR_DEC<7> net23<0> VDD VSS / RSC_IHPSG13_NAND2X2 +XA_DEC3<14> A_P0 A_ADDR_DEC<6> net23<1> VDD VSS / RSC_IHPSG13_NAND2X2 +XA_DEC3<13> A_P0 A_ADDR_DEC<5> net23<2> VDD VSS / RSC_IHPSG13_NAND2X2 +XA_DEC3<12> A_P0 A_ADDR_DEC<4> net23<3> VDD VSS / RSC_IHPSG13_NAND2X2 +XA_DEC3<11> A_P0 A_ADDR_DEC<3> net23<4> VDD VSS / RSC_IHPSG13_NAND2X2 +XA_DEC3<10> A_P0 A_ADDR_DEC<2> net23<5> VDD VSS / RSC_IHPSG13_NAND2X2 +XA_DEC3<9> A_P0 A_ADDR_DEC<1> net23<6> VDD VSS / RSC_IHPSG13_NAND2X2 +XA_DEC3<8> A_P0 A_ADDR_DEC<0> net23<7> VDD VSS / RSC_IHPSG13_NAND2X2 +XA_DEC3<7> A_N0 A_ADDR_DEC<7> net23<8> VDD VSS / RSC_IHPSG13_NAND2X2 +XA_DEC3<6> A_N0 A_ADDR_DEC<6> net23<9> VDD VSS / RSC_IHPSG13_NAND2X2 +XA_DEC3<5> A_N0 A_ADDR_DEC<5> net23<10> VDD VSS / RSC_IHPSG13_NAND2X2 +XA_DEC3<4> A_N0 A_ADDR_DEC<4> net23<11> VDD VSS / RSC_IHPSG13_NAND2X2 +XA_DEC3<3> A_N0 A_ADDR_DEC<3> net23<12> VDD VSS / RSC_IHPSG13_NAND2X2 +XA_DEC3<2> A_N0 A_ADDR_DEC<2> net23<13> VDD VSS / RSC_IHPSG13_NAND2X2 +XA_DEC3<1> A_N0 A_ADDR_DEC<1> net23<14> VDD VSS / RSC_IHPSG13_NAND2X2 +XA_DEC3<0> A_N0 A_ADDR_DEC<0> net23<15> VDD VSS / RSC_IHPSG13_NAND2X2 +XA_BM_TIEH A_TIEH_O VDD VSS / RSC_IHPSG13_TIEH +.ENDS + + +.SUBCKT RM_IHPSG13_256x16_c2_1P_COLDEC3 ACLK_N ADDR<2> ADDR<1> ADDR<0> ADDR_COL<1> ++ ADDR_COL<0> ADDR_DEC<7> ADDR_DEC<6> ADDR_DEC<5> ADDR_DEC<4> ADDR_DEC<3> ++ ADDR_DEC<2> ADDR_DEC<1> ADDR_DEC<0> BIST_ADDR<2> BIST_ADDR<1> BIST_ADDR<0> ++ BIST_EN_I VDD VSS +XI15<1> ADDR_COL<1> VDD VSS / RSC_IHPSG13_TIEL +XI15<0> ADDR_COL<0> VDD VSS / RSC_IHPSG13_TIEL +XI1<7> PADR<0> PADR<1> PADR<2> addr_n<7> VDD VSS / RSC_IHPSG13_NAND3X2 +XI1<6> NADR<0> PADR<1> PADR<2> addr_n<6> VDD VSS / RSC_IHPSG13_NAND3X2 +XI1<5> PADR<0> NADR<1> PADR<2> addr_n<5> VDD VSS / RSC_IHPSG13_NAND3X2 +XI1<4> NADR<0> NADR<1> PADR<2> addr_n<4> VDD VSS / RSC_IHPSG13_NAND3X2 +XI1<3> PADR<0> PADR<1> NADR<2> addr_n<3> VDD VSS / RSC_IHPSG13_NAND3X2 +XI1<2> NADR<0> PADR<1> NADR<2> addr_n<2> VDD VSS / RSC_IHPSG13_NAND3X2 +XI1<1> PADR<0> NADR<1> NADR<2> addr_n<1> VDD VSS / RSC_IHPSG13_NAND3X2 +XI1<0> NADR<0> NADR<1> NADR<2> addr_n<0> VDD VSS / RSC_IHPSG13_NAND3X2 +XDFF<2> BIST_EN_I BIST_ADDR<2> ACLK_N ADDR<2> padr_int<2> net6<0> VDD ++ VSS / RSC_IHPSG13_DFNQMX2IX1 +XDFF<1> BIST_EN_I BIST_ADDR<1> ACLK_N ADDR<1> padr_int<1> net6<1> VDD ++ VSS / RSC_IHPSG13_DFNQMX2IX1 +XDFF<0> BIST_EN_I BIST_ADDR<0> ACLK_N ADDR<0> padr_int<0> net6<2> VDD ++ VSS / RSC_IHPSG13_DFNQMX2IX1 +XI17<2> VDD VSS / RSC_IHPSG13_FILLCAP4 +XI17<1> VDD VSS / RSC_IHPSG13_FILLCAP4 +XI13<2> NADR<2> PADR<2> VDD VSS / RSC_IHPSG13_INVX2 +XI13<1> NADR<1> PADR<1> VDD VSS / RSC_IHPSG13_INVX2 +XI13<0> NADR<0> PADR<0> VDD VSS / RSC_IHPSG13_INVX2 +XI3<2> padr_int<2> NADR<2> VDD VSS / RSC_IHPSG13_INVX2 +XI3<1> padr_int<1> NADR<1> VDD VSS / RSC_IHPSG13_INVX2 +XI3<0> padr_int<0> NADR<0> VDD VSS / RSC_IHPSG13_INVX2 +XI2<7> addr_n<7> ADDR_DEC<7> VDD VSS / RSC_IHPSG13_INVX2 +XI2<6> addr_n<6> ADDR_DEC<6> VDD VSS / RSC_IHPSG13_INVX2 +XI2<5> addr_n<5> ADDR_DEC<5> VDD VSS / RSC_IHPSG13_INVX2 +XI2<4> addr_n<4> ADDR_DEC<4> VDD VSS / RSC_IHPSG13_INVX2 +XI2<3> addr_n<3> ADDR_DEC<3> VDD VSS / RSC_IHPSG13_INVX2 +XI2<2> addr_n<2> ADDR_DEC<2> VDD VSS / RSC_IHPSG13_INVX2 +XI2<1> addr_n<1> ADDR_DEC<1> VDD VSS / RSC_IHPSG13_INVX2 +XI2<0> addr_n<0> ADDR_DEC<0> VDD VSS / RSC_IHPSG13_INVX2 +XI16<6> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI16<5> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI16<4> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI16<3> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI16<2> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI16<1> VDD VSS / RSC_IHPSG13_FILLCAP8 +.ENDS +.SUBCKT RM_IHPSG13_256x16_c2_1P_COLCTRL3 A_ADDR_DEC<7> A_ADDR_DEC<6> A_ADDR_DEC<5> ++ A_ADDR_DEC<4> A_ADDR_DEC<3> A_ADDR_DEC<2> A_ADDR_DEC<1> A_ADDR_DEC<0> ++ A_BIST_BM_I A_BIST_DW_I A_BIST_EN_I A_BLC<7> A_BLC<6> A_BLC<5> A_BLC<4> ++ A_BLC<3> A_BLC<2> A_BLC<1> A_BLC<0> A_BLT<7> A_BLT<6> A_BLT<5> A_BLT<4> ++ A_BLT<3> A_BLT<2> A_BLT<1> A_BLT<0> A_BM_I A_DCLK_B_L A_DCLK_B_R A_DCLK_L ++ A_DCLK_R A_DR_O A_DW_I A_RCLK_B_L A_RCLK_B_R A_RCLK_L A_RCLK_R A_TIEH_O ++ A_WCLK_B_L A_WCLK_B_R A_WCLK_L A_WCLK_R VDD VSS +XA_DREG A_BIST_EN_I A_BIST_DW_I A_DCLK_B_L A_DW_I A_DI_R net22 VDD VSS ++ / RSC_IHPSG13_DFNQMX2IX1 +XA_BREG A_BIST_EN_I A_BIST_BM_I A_DCLK_B_R A_BM_I A_BM_R net23 VDD VSS ++ / RSC_IHPSG13_DFNQMX2IX1 +XA_I70<8> VDD VSS / RSC_IHPSG13_FILLCAP8 +XA_I70<7> VDD VSS / RSC_IHPSG13_FILLCAP8 +XA_I70<6> VDD VSS / RSC_IHPSG13_FILLCAP8 +XA_I70<5> VDD VSS / RSC_IHPSG13_FILLCAP8 +XA_I70<4> VDD VSS / RSC_IHPSG13_FILLCAP8 +XA_I70<3> VDD VSS / RSC_IHPSG13_FILLCAP8 +XA_I70<2> VDD VSS / RSC_IHPSG13_FILLCAP8 +XA_I70<1> VDD VSS / RSC_IHPSG13_FILLCAP8 +XA_I51 net19 A_DR_O VDD VSS / RSC_IHPSG13_INVX4 +XA_I44 A_BM_N A_WCLK_B_R A_DO_WRITE_P VDD VSS / RSC_IHPSG13_NOR2X2 +XA_BM_TIEH A_TIEH_O VDD VSS / RSC_IHPSG13_TIEH +XA_BLTMUX<7> A_BLC<7> A_BLC_SEL A_BLT<7> A_BLT_SEL A_PRE_N A_ADDR_DEC<7> ++ A_WR_ONE A_WR_ZERO VDD VSS / RM_IHPSG13_256x16_c2_1P_BLDRV +XA_BLTMUX<6> A_BLC<6> A_BLC_SEL A_BLT<6> A_BLT_SEL A_PRE_N A_ADDR_DEC<6> ++ A_WR_ONE A_WR_ZERO VDD VSS / RM_IHPSG13_256x16_c2_1P_BLDRV +XA_BLTMUX<5> A_BLC<5> A_BLC_SEL A_BLT<5> A_BLT_SEL A_PRE_N A_ADDR_DEC<5> ++ A_WR_ONE A_WR_ZERO VDD VSS / RM_IHPSG13_256x16_c2_1P_BLDRV +XA_BLTMUX<4> A_BLC<4> A_BLC_SEL A_BLT<4> A_BLT_SEL A_PRE_N A_ADDR_DEC<4> ++ A_WR_ONE A_WR_ZERO VDD VSS / RM_IHPSG13_256x16_c2_1P_BLDRV +XA_BLTMUX<3> A_BLC<3> A_BLC_SEL A_BLT<3> A_BLT_SEL A_PRE_N A_ADDR_DEC<3> ++ A_WR_ONE A_WR_ZERO VDD VSS / RM_IHPSG13_256x16_c2_1P_BLDRV +XA_BLTMUX<2> A_BLC<2> A_BLC_SEL A_BLT<2> A_BLT_SEL A_PRE_N A_ADDR_DEC<2> ++ A_WR_ONE A_WR_ZERO VDD VSS / RM_IHPSG13_256x16_c2_1P_BLDRV +XA_BLTMUX<1> A_BLC<1> A_BLC_SEL A_BLT<1> A_BLT_SEL A_PRE_N A_ADDR_DEC<1> ++ A_WR_ONE A_WR_ZERO VDD VSS / RM_IHPSG13_256x16_c2_1P_BLDRV +XA_BLTMUX<0> A_BLC<0> A_BLC_SEL A_BLT<0> A_BLT_SEL A_PRE_N A_ADDR_DEC<0> ++ A_WR_ONE A_WR_ZERO VDD VSS / RM_IHPSG13_256x16_c2_1P_BLDRV +XA_I49 A_DI_R A_DI_N VDD VSS / RSC_IHPSG13_INVX2 +XA_I83 A_BM_R A_BM_N VDD VSS / RSC_IHPSG13_INVX2 +XA_I69 A_DCLK_L A_DCLK_B_L VDD VSS / RSC_IHPSG13_CINVX2 +XA_I50 A_WCLK_L A_WCLK_B_L VDD VSS / RSC_IHPSG13_CINVX2 +XA_EBUF A_RCLK_L A_RCLK_B_L VDD VSS / RSC_IHPSG13_CINVX2 +XA_I78 A_RCLK_B_L A_SAE VDD VSS / RSC_IHPSG13_CBUFX2 +XA_I88 A_DCLK_L A_DCLK_R / RSC_IHPSG13_MET3RES +XA_I87 A_WCLK_L A_WCLK_R / RSC_IHPSG13_MET3RES +XA_R2 A_RCLK_L A_RCLK_R / RSC_IHPSG13_MET3RES +XA_I91 A_RCLK_B_L A_RCLK_B_R / RSC_IHPSG13_MET3RES +XA_I90 A_WCLK_B_L A_WCLK_B_R / RSC_IHPSG13_MET3RES +XA_I89 A_DCLK_B_L A_DCLK_B_R / RSC_IHPSG13_MET3RES +XA_I80 A_WCLK_B_R A_RCLK_B_R net21 VDD VSS / RSC_IHPSG13_AND2X2 +XA_I76 A_DI_N A_DO_WRITE_P A_WR_ZERO VDD VSS / RSC_IHPSG13_AND2X2 +XA_I75 A_DI_R A_DO_WRITE_P A_WR_ONE VDD VSS / RSC_IHPSG13_AND2X2 +XA_ISENSE A_SAE A_BLC_SEL A_BLT_SEL net19 net20 VDD VSS / ++ RSC_IHPSG13_DFPQD_MSAFFX2 +XA_I81 net21 A_PRE_N VDD VSS / RSC_IHPSG13_CINVX4_WN +XA_CAPS<5> VDD VSS / RSC_IHPSG13_FILLCAP4 +XA_CAPS<4> VDD VSS / RSC_IHPSG13_FILLCAP4 +XA_CAPS<3> VDD VSS / RSC_IHPSG13_FILLCAP4 +XA_CAPS<2> VDD VSS / RSC_IHPSG13_FILLCAP4 +XA_CAPS<1> VDD VSS / RSC_IHPSG13_FILLCAP4 +.ENDS + +.SUBCKT RM_IHPSG13_256x16_c2_2P_BITKIT_16x2_CORNER VDD_CORE VSS +XI16 VDD_CORE VSS VDD_CORE VSS / ++ RM_IHPSG13_256x16_c2_1P_BITKIT_CORNER +.ENDS +.SUBCKT RM_IHPSG13_256x16_c2_2P_BITKIT_EDGE_LR A_WL B_WL NW PW VDD VSS +MN1 VSS A_WL VSS VSS sg13_lv_nmos m=1 w=300.0n l=130.00n ng=1 nrd=0 nrs=0 +MN0 VSS B_WL VSS VSS sg13_lv_nmos m=1 w=300.0n l=130.00n ng=1 nrd=0 nrs=0 +.ENDS +.SUBCKT RM_IHPSG13_256x16_c2_2P_BITKIT_16x2_EDGE_LR A_WL<15> A_WL<14> A_WL<13> A_WL<12> ++ A_WL<11> A_WL<10> A_WL<9> A_WL<8> A_WL<7> A_WL<6> A_WL<5> A_WL<4> A_WL<3> ++ A_WL<2> A_WL<1> A_WL<0> B_WL<15> B_WL<14> B_WL<13> B_WL<12> B_WL<11> ++ B_WL<10> B_WL<9> B_WL<8> B_WL<7> B_WL<6> B_WL<5> B_WL<4> B_WL<3> B_WL<2> ++ B_WL<1> B_WL<0> VDD_CORE VSS +XI0<15> A_WL<15> B_WL<15> VDD_CORE VSS VDD_CORE VSS ++ / RM_IHPSG13_256x16_c2_2P_BITKIT_EDGE_LR +XI0<14> A_WL<14> B_WL<14> VDD_CORE VSS VDD_CORE VSS ++ / RM_IHPSG13_256x16_c2_2P_BITKIT_EDGE_LR +XI0<13> A_WL<13> B_WL<13> VDD_CORE VSS VDD_CORE VSS ++ / RM_IHPSG13_256x16_c2_2P_BITKIT_EDGE_LR +XI0<12> A_WL<12> B_WL<12> VDD_CORE VSS VDD_CORE VSS ++ / RM_IHPSG13_256x16_c2_2P_BITKIT_EDGE_LR +XI0<11> A_WL<11> B_WL<11> VDD_CORE VSS VDD_CORE VSS ++ / RM_IHPSG13_256x16_c2_2P_BITKIT_EDGE_LR +XI0<10> A_WL<10> B_WL<10> VDD_CORE VSS VDD_CORE VSS ++ / RM_IHPSG13_256x16_c2_2P_BITKIT_EDGE_LR +XI0<9> A_WL<9> B_WL<9> VDD_CORE VSS VDD_CORE VSS / ++ RM_IHPSG13_256x16_c2_2P_BITKIT_EDGE_LR +XI0<8> A_WL<8> B_WL<8> VDD_CORE VSS VDD_CORE VSS / ++ RM_IHPSG13_256x16_c2_2P_BITKIT_EDGE_LR +XI0<7> A_WL<7> B_WL<7> VDD_CORE VSS VDD_CORE VSS / ++ RM_IHPSG13_256x16_c2_2P_BITKIT_EDGE_LR +XI0<6> A_WL<6> B_WL<6> VDD_CORE VSS VDD_CORE VSS / ++ RM_IHPSG13_256x16_c2_2P_BITKIT_EDGE_LR +XI0<5> A_WL<5> B_WL<5> VDD_CORE VSS VDD_CORE VSS / ++ RM_IHPSG13_256x16_c2_2P_BITKIT_EDGE_LR +XI0<4> A_WL<4> B_WL<4> VDD_CORE VSS VDD_CORE VSS / ++ RM_IHPSG13_256x16_c2_2P_BITKIT_EDGE_LR +XI0<3> A_WL<3> B_WL<3> VDD_CORE VSS VDD_CORE VSS / ++ RM_IHPSG13_256x16_c2_2P_BITKIT_EDGE_LR +XI0<2> A_WL<2> B_WL<2> VDD_CORE VSS VDD_CORE VSS / ++ RM_IHPSG13_256x16_c2_2P_BITKIT_EDGE_LR +XI0<1> A_WL<1> B_WL<1> VDD_CORE VSS VDD_CORE VSS / ++ RM_IHPSG13_256x16_c2_2P_BITKIT_EDGE_LR +XI0<0> A_WL<0> B_WL<0> VDD_CORE VSS VDD_CORE VSS / ++ RM_IHPSG13_256x16_c2_2P_BITKIT_EDGE_LR +.ENDS +.SUBCKT RM_IHPSG13_256x16_c2_2P_BITKIT_CELL A_BLC_BOT A_BLC_TOP A_BLT_BOT A_BLT_TOP ++ A_LWL A_RWL B_BLC_BOT B_BLC_TOP B_BLT_BOT B_BLT_TOP B_LWL B_RWL NW PW VDD VSS +MN5 NC B_RWL B_BLC_BOT PW sg13_lv_nmos m=1 w=300.0n l=130.00n ng=1 nrd=0 nrs=0 +MN4 B_BLT_BOT B_LWL NT PW sg13_lv_nmos m=1 w=300.0n l=130.00n ng=1 nrd=0 nrs=0 +MN0 NC NT VSS PW sg13_lv_nmos m=1 w=600.0n l=130.00n ng=2 nrd=0 nrs=0 +MN1 NT NC VSS PW sg13_lv_nmos m=1 w=600.0n l=130.00n ng=2 nrd=0 nrs=0 +MN3 NC A_RWL A_BLC_TOP PW sg13_lv_nmos m=1 w=300.0n l=130.00n ng=1 nrd=0 nrs=0 +MN2 A_BLT_TOP A_LWL NT PW sg13_lv_nmos m=1 w=300.0n l=130.00n ng=1 nrd=0 nrs=0 +MP1 NT NC VDD NW sg13_lv_pmos m=1 w=150.00n l=130.00n ng=1 nrd=0 nrs=0 +MP0 NC NT VDD NW sg13_lv_pmos m=1 w=150.00n l=130.00n ng=1 nrd=0 nrs=0 +R5 B_RWL B_LWL lvsres w=2.6e-07 l=6e-07 +R4 B_BLC_BOT B_BLC_TOP lvsres w=2.6e-07 l=6e-07 +R3 B_BLT_BOT B_BLT_TOP lvsres w=2.6e-07 l=6e-07 +R1 A_BLC_BOT A_BLC_TOP lvsres w=2.6e-07 l=6e-07 +R0 A_BLT_BOT A_BLT_TOP lvsres w=2.6e-07 l=6e-07 +R2 A_RWL A_LWL lvsres w=2.6e-07 l=6e-07 +.ENDS +.SUBCKT RM_IHPSG13_256x16_c2_2P_BITKIT_16x2_SRAM A_BLC_BOT<1> A_BLC_BOT<0> A_BLC_TOP<1> ++ A_BLC_TOP<0> A_BLT_BOT<1> A_BLT_BOT<0> A_BLT_TOP<1> A_BLT_TOP<0> A_LWL<15> ++ A_LWL<14> A_LWL<13> A_LWL<12> A_LWL<11> A_LWL<10> A_LWL<9> A_LWL<8> A_LWL<7> ++ A_LWL<6> A_LWL<5> A_LWL<4> A_LWL<3> A_LWL<2> A_LWL<1> A_LWL<0> A_RWL<15> ++ A_RWL<14> A_RWL<13> A_RWL<12> A_RWL<11> A_RWL<10> A_RWL<9> A_RWL<8> A_RWL<7> ++ A_RWL<6> A_RWL<5> A_RWL<4> A_RWL<3> A_RWL<2> A_RWL<1> A_RWL<0> B_BLC_BOT<1> ++ B_BLC_BOT<0> B_BLC_TOP<1> B_BLC_TOP<0> B_BLT_BOT<1> B_BLT_BOT<0> ++ B_BLT_TOP<1> B_BLT_TOP<0> B_LWL<15> B_LWL<14> B_LWL<13> B_LWL<12> B_LWL<11> ++ B_LWL<10> B_LWL<9> B_LWL<8> B_LWL<7> B_LWL<6> B_LWL<5> B_LWL<4> B_LWL<3> ++ B_LWL<2> B_LWL<1> B_LWL<0> B_RWL<15> B_RWL<14> B_RWL<13> B_RWL<12> B_RWL<11> ++ B_RWL<10> B_RWL<9> B_RWL<8> B_RWL<7> B_RWL<6> B_RWL<5> B_RWL<4> B_RWL<3> ++ B_RWL<2> B_RWL<1> B_RWL<0> VDD_CORE VSS +XCELL<31> A_BLC_TOP<1> A_RBLC<15> A_BLT_TOP<1> A_RBLT<15> A_XWL<15> A_RWL<15> ++ B_BLC_TOP<1> B_RBLC<15> B_BLT_TOP<1> B_RBLT<15> B_XWL<15> B_RWL<15> ++ VDD_CORE VSS VDD_CORE VSS / ++ RM_IHPSG13_256x16_c2_2P_BITKIT_CELL +XCELL<30> A_RBLC<14> A_RBLC<15> A_RBLT<14> A_RBLT<15> A_XWL<14> A_RWL<14> ++ B_RBLC<14> B_RBLC<15> B_RBLT<14> B_RBLT<15> B_XWL<14> B_RWL<14> VDD_CORE ++ VSS VDD_CORE VSS / RM_IHPSG13_256x16_c2_2P_BITKIT_CELL +XCELL<29> A_RBLC<14> A_RBLC<13> A_RBLT<14> A_RBLT<13> A_XWL<13> A_RWL<13> ++ B_RBLC<14> B_RBLC<13> B_RBLT<14> B_RBLT<13> B_XWL<13> B_RWL<13> VDD_CORE ++ VSS VDD_CORE VSS / RM_IHPSG13_256x16_c2_2P_BITKIT_CELL +XCELL<28> A_RBLC<12> A_RBLC<13> A_RBLT<12> A_RBLT<13> A_XWL<12> A_RWL<12> ++ B_RBLC<12> B_RBLC<13> B_RBLT<12> B_RBLT<13> B_XWL<12> B_RWL<12> VDD_CORE ++ VSS VDD_CORE VSS / RM_IHPSG13_256x16_c2_2P_BITKIT_CELL +XCELL<27> A_RBLC<12> A_RBLC<11> A_RBLT<12> A_RBLT<11> A_XWL<11> A_RWL<11> ++ B_RBLC<12> B_RBLC<11> B_RBLT<12> B_RBLT<11> B_XWL<11> B_RWL<11> VDD_CORE ++ VSS VDD_CORE VSS / RM_IHPSG13_256x16_c2_2P_BITKIT_CELL +XCELL<26> A_RBLC<10> A_RBLC<11> A_RBLT<10> A_RBLT<11> A_XWL<10> A_RWL<10> ++ B_RBLC<10> B_RBLC<11> B_RBLT<10> B_RBLT<11> B_XWL<10> B_RWL<10> VDD_CORE ++ VSS VDD_CORE VSS / RM_IHPSG13_256x16_c2_2P_BITKIT_CELL +XCELL<25> A_RBLC<10> A_RBLC<9> A_RBLT<10> A_RBLT<9> A_XWL<9> A_RWL<9> ++ B_RBLC<10> B_RBLC<9> B_RBLT<10> B_RBLT<9> B_XWL<9> B_RWL<9> VDD_CORE ++ VSS VDD_CORE VSS / RM_IHPSG13_256x16_c2_2P_BITKIT_CELL +XCELL<24> A_RBLC<8> A_RBLC<9> A_RBLT<8> A_RBLT<9> A_XWL<8> A_RWL<8> B_RBLC<8> ++ B_RBLC<9> B_RBLT<8> B_RBLT<9> B_XWL<8> B_RWL<8> VDD_CORE VSS ++ VDD_CORE VSS / RM_IHPSG13_256x16_c2_2P_BITKIT_CELL +XCELL<23> A_RBLC<8> A_RBLC<7> A_RBLT<8> A_RBLT<7> A_XWL<7> A_RWL<7> B_RBLC<8> ++ B_RBLC<7> B_RBLT<8> B_RBLT<7> B_XWL<7> B_RWL<7> VDD_CORE VSS ++ VDD_CORE VSS / RM_IHPSG13_256x16_c2_2P_BITKIT_CELL +XCELL<22> A_RBLC<6> A_RBLC<7> A_RBLT<6> A_RBLT<7> A_XWL<6> A_RWL<6> B_RBLC<6> ++ B_RBLC<7> B_RBLT<6> B_RBLT<7> B_XWL<6> B_RWL<6> VDD_CORE VSS ++ VDD_CORE VSS / RM_IHPSG13_256x16_c2_2P_BITKIT_CELL +XCELL<21> A_RBLC<6> A_RBLC<5> A_RBLT<6> A_RBLT<5> A_XWL<5> A_RWL<5> B_RBLC<6> ++ B_RBLC<5> B_RBLT<6> B_RBLT<5> B_XWL<5> B_RWL<5> VDD_CORE VSS ++ VDD_CORE VSS / RM_IHPSG13_256x16_c2_2P_BITKIT_CELL +XCELL<20> A_RBLC<4> A_RBLC<5> A_RBLT<4> A_RBLT<5> A_XWL<4> A_RWL<4> B_RBLC<4> ++ B_RBLC<5> B_RBLT<4> B_RBLT<5> B_XWL<4> B_RWL<4> VDD_CORE VSS ++ VDD_CORE VSS / RM_IHPSG13_256x16_c2_2P_BITKIT_CELL +XCELL<19> A_RBLC<4> A_RBLC<3> A_RBLT<4> A_RBLT<3> A_XWL<3> A_RWL<3> B_RBLC<4> ++ B_RBLC<3> B_RBLT<4> B_RBLT<3> B_XWL<3> B_RWL<3> VDD_CORE VSS ++ VDD_CORE VSS / RM_IHPSG13_256x16_c2_2P_BITKIT_CELL +XCELL<18> A_RBLC<2> A_RBLC<3> A_RBLT<2> A_RBLT<3> A_XWL<2> A_RWL<2> B_RBLC<2> ++ B_RBLC<3> B_RBLT<2> B_RBLT<3> B_XWL<2> B_RWL<2> VDD_CORE VSS ++ VDD_CORE VSS / RM_IHPSG13_256x16_c2_2P_BITKIT_CELL +XCELL<17> A_RBLC<2> A_RBLC<1> A_RBLT<2> A_RBLT<1> A_XWL<1> A_RWL<1> B_RBLC<2> ++ B_RBLC<1> B_RBLT<2> B_RBLT<1> B_XWL<1> B_RWL<1> VDD_CORE VSS ++ VDD_CORE VSS / RM_IHPSG13_256x16_c2_2P_BITKIT_CELL +XCELL<16> A_BLC_BOT<1> A_RBLC<1> A_BLT_BOT<1> A_RBLT<1> A_XWL<0> A_RWL<0> ++ B_BLC_BOT<1> B_RBLC<1> B_BLT_BOT<1> B_RBLT<1> B_XWL<0> B_RWL<0> VDD_CORE ++ VSS VDD_CORE VSS / RM_IHPSG13_256x16_c2_2P_BITKIT_CELL +XCELL<15> A_BLC_TOP<0> A_LBLC<15> A_BLT_TOP<0> A_LBLT<15> A_LWL<15> A_XWL<15> ++ B_BLC_TOP<0> B_LBLC<15> B_BLT_TOP<0> B_LBLT<15> B_LWL<15> B_XWL<15> ++ VDD_CORE VSS VDD_CORE VSS / ++ RM_IHPSG13_256x16_c2_2P_BITKIT_CELL +XCELL<14> A_LBLC<14> A_LBLC<15> A_LBLT<14> A_LBLT<15> A_LWL<14> A_XWL<14> ++ B_LBLC<14> B_LBLC<15> B_LBLT<14> B_LBLT<15> B_LWL<14> B_XWL<14> VDD_CORE ++ VSS VDD_CORE VSS / RM_IHPSG13_256x16_c2_2P_BITKIT_CELL +XCELL<13> A_LBLC<14> A_LBLC<13> A_LBLT<14> A_LBLT<13> A_LWL<13> A_XWL<13> ++ B_LBLC<14> B_LBLC<13> B_LBLT<14> B_LBLT<13> B_LWL<13> B_XWL<13> VDD_CORE ++ VSS VDD_CORE VSS / RM_IHPSG13_256x16_c2_2P_BITKIT_CELL +XCELL<12> A_LBLC<12> A_LBLC<13> A_LBLT<12> A_LBLT<13> A_LWL<12> A_XWL<12> ++ B_LBLC<12> B_LBLC<13> B_LBLT<12> B_LBLT<13> B_LWL<12> B_XWL<12> VDD_CORE ++ VSS VDD_CORE VSS / RM_IHPSG13_256x16_c2_2P_BITKIT_CELL +XCELL<11> A_LBLC<12> A_LBLC<11> A_LBLT<12> A_LBLT<11> A_LWL<11> A_XWL<11> ++ B_LBLC<12> B_LBLC<11> B_LBLT<12> B_LBLT<11> B_LWL<11> B_XWL<11> VDD_CORE ++ VSS VDD_CORE VSS / RM_IHPSG13_256x16_c2_2P_BITKIT_CELL +XCELL<10> A_LBLC<10> A_LBLC<11> A_LBLT<10> A_LBLT<11> A_LWL<10> A_XWL<10> ++ B_LBLC<10> B_LBLC<11> B_LBLT<10> B_LBLT<11> B_LWL<10> B_XWL<10> VDD_CORE ++ VSS VDD_CORE VSS / RM_IHPSG13_256x16_c2_2P_BITKIT_CELL +XCELL<9> A_LBLC<10> A_LBLC<9> A_LBLT<10> A_LBLT<9> A_LWL<9> A_XWL<9> ++ B_LBLC<10> B_LBLC<9> B_LBLT<10> B_LBLT<9> B_LWL<9> B_XWL<9> VDD_CORE ++ VSS VDD_CORE VSS / RM_IHPSG13_256x16_c2_2P_BITKIT_CELL +XCELL<8> A_LBLC<8> A_LBLC<9> A_LBLT<8> A_LBLT<9> A_LWL<8> A_XWL<8> B_LBLC<8> ++ B_LBLC<9> B_LBLT<8> B_LBLT<9> B_LWL<8> B_XWL<8> VDD_CORE VSS ++ VDD_CORE VSS / RM_IHPSG13_256x16_c2_2P_BITKIT_CELL +XCELL<7> A_LBLC<8> A_LBLC<7> A_LBLT<8> A_LBLT<7> A_LWL<7> A_XWL<7> B_LBLC<8> ++ B_LBLC<7> B_LBLT<8> B_LBLT<7> B_LWL<7> B_XWL<7> VDD_CORE VSS ++ VDD_CORE VSS / RM_IHPSG13_256x16_c2_2P_BITKIT_CELL +XCELL<6> A_LBLC<6> A_LBLC<7> A_LBLT<6> A_LBLT<7> A_LWL<6> A_XWL<6> B_LBLC<6> ++ B_LBLC<7> B_LBLT<6> B_LBLT<7> B_LWL<6> B_XWL<6> VDD_CORE VSS ++ VDD_CORE VSS / RM_IHPSG13_256x16_c2_2P_BITKIT_CELL +XCELL<5> A_LBLC<6> A_LBLC<5> A_LBLT<6> A_LBLT<5> A_LWL<5> A_XWL<5> B_LBLC<6> ++ B_LBLC<5> B_LBLT<6> B_LBLT<5> B_LWL<5> B_XWL<5> VDD_CORE VSS ++ VDD_CORE VSS / RM_IHPSG13_256x16_c2_2P_BITKIT_CELL +XCELL<4> A_LBLC<4> A_LBLC<5> A_LBLT<4> A_LBLT<5> A_LWL<4> A_XWL<4> B_LBLC<4> ++ B_LBLC<5> B_LBLT<4> B_LBLT<5> B_LWL<4> B_XWL<4> VDD_CORE VSS ++ VDD_CORE VSS / RM_IHPSG13_256x16_c2_2P_BITKIT_CELL +XCELL<3> A_LBLC<4> A_LBLC<3> A_LBLT<4> A_LBLT<3> A_LWL<3> A_XWL<3> B_LBLC<4> ++ B_LBLC<3> B_LBLT<4> B_LBLT<3> B_LWL<3> B_XWL<3> VDD_CORE VSS ++ VDD_CORE VSS / RM_IHPSG13_256x16_c2_2P_BITKIT_CELL +XCELL<2> A_LBLC<2> A_LBLC<3> A_LBLT<2> A_LBLT<3> A_LWL<2> A_XWL<2> B_LBLC<2> ++ B_LBLC<3> B_LBLT<2> B_LBLT<3> B_LWL<2> B_XWL<2> VDD_CORE VSS ++ VDD_CORE VSS / RM_IHPSG13_256x16_c2_2P_BITKIT_CELL +XCELL<1> A_LBLC<2> A_LBLC<1> A_LBLT<2> A_LBLT<1> A_LWL<1> A_XWL<1> B_LBLC<2> ++ B_LBLC<1> B_LBLT<2> B_LBLT<1> B_LWL<1> B_XWL<1> VDD_CORE VSS ++ VDD_CORE VSS / RM_IHPSG13_256x16_c2_2P_BITKIT_CELL +XCELL<0> A_BLC_BOT<0> A_LBLC<1> A_BLT_BOT<0> A_LBLT<1> A_LWL<0> A_XWL<0> ++ B_BLC_BOT<0> B_LBLC<1> B_BLT_BOT<0> B_LBLT<1> B_LWL<0> B_XWL<0> VDD_CORE ++ VSS VDD_CORE VSS / RM_IHPSG13_256x16_c2_2P_BITKIT_CELL +.ENDS +.SUBCKT RM_IHPSG13_256x16_c2_2P_BITKIT_EDGE_TB A_BLC A_BLT B_BLC B_BLT NW PW VDD VSS +.ENDS +.SUBCKT RM_IHPSG13_256x16_c2_2P_BITKIT_16x2_EDGE_TB A_BLC<1> A_BLC<0> A_BLT<1> A_BLT<0> ++ B_BLC<1> B_BLC<0> B_BLT<1> B_BLT<0> VDD_CORE VSS +XEDGE<1> A_BLC<1> A_BLT<1> B_BLC<1> B_BLT<1> VDD_CORE VSS ++ VDD_CORE VSS / RM_IHPSG13_256x16_c2_2P_BITKIT_EDGE_TB +XEDGE<0> A_BLC<0> A_BLT<0> B_BLC<0> B_BLT<0> VDD_CORE VSS ++ VDD_CORE VSS / RM_IHPSG13_256x16_c2_2P_BITKIT_EDGE_TB +.ENDS +.SUBCKT RM_IHPSG13_256x16_c2_2P_BITKIT_TAP A_BLC A_BLT B_BLC B_BLT NW PW VDD VSS +.ENDS +.SUBCKT RM_IHPSG13_256x16_c2_2P_BITKIT_16x2_TAP A_BLC<1> A_BLC<0> A_BLT<1> A_BLT<0> ++ B_BLC<1> B_BLC<0> B_BLT<1> B_BLT<0> VDD_CORE VSS +XIEDGEBP_COL1<1> A_BLC<1> A_BLT<1> B_BLC<1> B_BLT<1> VDD_CORE VSS ++ VDD_CORE VSS / RM_IHPSG13_256x16_c2_2P_BITKIT_EDGE_TB +XIEDGEBP_COL1<0> A_BLC<1> A_BLT<1> B_BLC<1> B_BLT<1> VDD_CORE VSS ++ VDD_CORE VSS / RM_IHPSG13_256x16_c2_2P_BITKIT_EDGE_TB +XIEDGEBP_COL2<1> A_BLC<0> A_BLT<0> B_BLC<0> B_BLT<0> VDD_CORE VSS ++ VDD_CORE VSS / RM_IHPSG13_256x16_c2_2P_BITKIT_EDGE_TB +XIEDGEBP_COL2<0> A_BLC<0> A_BLT<0> B_BLC<0> B_BLT<0> VDD_CORE VSS ++ VDD_CORE VSS / RM_IHPSG13_256x16_c2_2P_BITKIT_EDGE_TB +XITAP<1> A_BLC<1> A_BLT<1> B_BLC<1> B_BLT<1> VDD_CORE VSS ++ VDD_CORE VSS / RM_IHPSG13_256x16_c2_2P_BITKIT_TAP +XITAP<0> A_BLC<0> A_BLT<0> B_BLC<0> B_BLT<0> VDD_CORE VSS ++ VDD_CORE VSS / RM_IHPSG13_256x16_c2_2P_BITKIT_TAP +.ENDS + + +.SUBCKT RM_IHPSG13_256x16_c2_1P_BITKIT_TAP_LR NW PW VDD VSS +.ENDS +.SUBCKT RM_IHPSG13_256x16_c2_2P_BITKIT_16x2_TAP_LR VDD_CORE VSS +XCORNER<1> VDD_CORE VSS VDD_CORE VSS / ++ RM_IHPSG13_256x16_c2_1P_BITKIT_CORNER +XCORNER<0> VDD_CORE VSS VDD_CORE VSS / ++ RM_IHPSG13_256x16_c2_1P_BITKIT_CORNER +XTAP_BORDER VDD_CORE VSS VDD_CORE VSS / ++ RM_IHPSG13_256x16_c2_1P_BITKIT_TAP_LR +.ENDS + +.SUBCKT RSC_IHPSG13_CBUFX12 A Z VDD VSS +MN1 Z net6 VSS VSS sg13_lv_nmos m=1 w=4.23u l=130.00n ng=6 nrd=0 nrs=0 +MN0 net6 A VSS VSS sg13_lv_nmos m=1 w=1.41u l=130.00n ng=2 nrd=0 nrs=0 +MP1 Z net6 VDD VDD sg13_lv_pmos m=1 w=9.72u l=130.00n ng=6 nrd=0 nrs=0 +MP0 net6 A VDD VDD sg13_lv_pmos m=1 w=3.24u l=130.00n ng=2 nrd=0 nrs=0 +.ENDS +.SUBCKT RM_IHPSG13_256x16_c2_2P_COLDRV13X12 ADDR_COL_I<1> ADDR_COL_I<0> ADDR_COL_O<1> ++ ADDR_COL_O<0> ADDR_DEC_I<7> ADDR_DEC_I<6> ADDR_DEC_I<5> ADDR_DEC_I<4> ++ ADDR_DEC_I<3> ADDR_DEC_I<2> ADDR_DEC_I<1> ADDR_DEC_I<0> ADDR_DEC_O<7> ++ ADDR_DEC_O<6> ADDR_DEC_O<5> ADDR_DEC_O<4> ADDR_DEC_O<3> ADDR_DEC_O<2> ++ ADDR_DEC_O<1> ADDR_DEC_O<0> DCLK_I DCLK_O RCLK_I RCLK_O WCLK_I WCLK_O ++ VDD VSS +XI1<3> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI1<2> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI1<1> VDD VSS / RSC_IHPSG13_FILLCAP8 +XWCLK_DRV WCLK_I WCLK_O VDD VSS / RSC_IHPSG13_CBUFX12 +XRCLK_DRV RCLK_I RCLK_O VDD VSS / RSC_IHPSG13_CBUFX12 +XDCLK_DRV DCLK_I DCLK_O VDD VSS / RSC_IHPSG13_CBUFX12 +XADDR_COL_DRV<1> ADDR_COL_I<1> ADDR_COL_O<1> VDD VSS / ++ RSC_IHPSG13_CBUFX12 +XADDR_COL_DRV<0> ADDR_COL_I<0> ADDR_COL_O<0> VDD VSS / ++ RSC_IHPSG13_CBUFX12 +XADDR_DEC_DRV<7> ADDR_DEC_I<7> ADDR_DEC_O<7> VDD VSS / ++ RSC_IHPSG13_CBUFX12 +XADDR_DEC_DRV<6> ADDR_DEC_I<6> ADDR_DEC_O<6> VDD VSS / ++ RSC_IHPSG13_CBUFX12 +XADDR_DEC_DRV<5> ADDR_DEC_I<5> ADDR_DEC_O<5> VDD VSS / ++ RSC_IHPSG13_CBUFX12 +XADDR_DEC_DRV<4> ADDR_DEC_I<4> ADDR_DEC_O<4> VDD VSS / ++ RSC_IHPSG13_CBUFX12 +XADDR_DEC_DRV<3> ADDR_DEC_I<3> ADDR_DEC_O<3> VDD VSS / ++ RSC_IHPSG13_CBUFX12 +XADDR_DEC_DRV<2> ADDR_DEC_I<2> ADDR_DEC_O<2> VDD VSS / ++ RSC_IHPSG13_CBUFX12 +XADDR_DEC_DRV<1> ADDR_DEC_I<1> ADDR_DEC_O<1> VDD VSS / ++ RSC_IHPSG13_CBUFX12 +XADDR_DEC_DRV<0> ADDR_DEC_I<0> ADDR_DEC_O<0> VDD VSS / ++ RSC_IHPSG13_CBUFX12 +XI0<6> VDD VSS / RSC_IHPSG13_FILLCAP4 +XI0<5> VDD VSS / RSC_IHPSG13_FILLCAP4 +XI0<4> VDD VSS / RSC_IHPSG13_FILLCAP4 +XI0<3> VDD VSS / RSC_IHPSG13_FILLCAP4 +XI0<2> VDD VSS / RSC_IHPSG13_FILLCAP4 +XI0<1> VDD VSS / RSC_IHPSG13_FILLCAP4 +.ENDS +.SUBCKT RSC_IHPSG13_WLDRVX12 A Z VDD VSS +MN1 Z net6 VSS VSS sg13_lv_nmos m=1 w=1.41u l=130.00n ng=2 nrd=0 nrs=0 +MN0 net6 A VSS VSS sg13_lv_nmos m=1 w=1.8u l=130.00n ng=2 nrd=0 nrs=0 +MP1 Z net6 VDD VDD sg13_lv_pmos m=1 w=9.72u l=130.00n ng=6 nrd=0 nrs=0 +MP0 net6 A VDD VDD sg13_lv_pmos m=1 w=900.0n l=130.00n ng=1 nrd=0 nrs=0 +.ENDS +.SUBCKT RM_IHPSG13_256x16_c2_2P_WLDRV16X12 A<15> A<14> A<13> A<12> A<11> A<10> A<9> A<8> ++ A<7> A<6> A<5> A<4> A<3> A<2> A<1> A<0> Z<15> Z<14> Z<13> Z<12> Z<11> Z<10> ++ Z<9> Z<8> Z<7> Z<6> Z<5> Z<4> Z<3> Z<2> Z<1> Z<0> VDD VSS +XBUF<15> A<15> Z<15> VDD VSS / RSC_IHPSG13_WLDRVX12 +XBUF<14> A<14> Z<14> VDD VSS / RSC_IHPSG13_WLDRVX12 +XBUF<13> A<13> Z<13> VDD VSS / RSC_IHPSG13_WLDRVX12 +XBUF<12> A<12> Z<12> VDD VSS / RSC_IHPSG13_WLDRVX12 +XBUF<11> A<11> Z<11> VDD VSS / RSC_IHPSG13_WLDRVX12 +XBUF<10> A<10> Z<10> VDD VSS / RSC_IHPSG13_WLDRVX12 +XBUF<9> A<9> Z<9> VDD VSS / RSC_IHPSG13_WLDRVX12 +XBUF<8> A<8> Z<8> VDD VSS / RSC_IHPSG13_WLDRVX12 +XBUF<7> A<7> Z<7> VDD VSS / RSC_IHPSG13_WLDRVX12 +XBUF<6> A<6> Z<6> VDD VSS / RSC_IHPSG13_WLDRVX12 +XBUF<5> A<5> Z<5> VDD VSS / RSC_IHPSG13_WLDRVX12 +XBUF<4> A<4> Z<4> VDD VSS / RSC_IHPSG13_WLDRVX12 +XBUF<3> A<3> Z<3> VDD VSS / RSC_IHPSG13_WLDRVX12 +XBUF<2> A<2> Z<2> VDD VSS / RSC_IHPSG13_WLDRVX12 +XBUF<1> A<1> Z<1> VDD VSS / RSC_IHPSG13_WLDRVX12 +XBUF<0> A<0> Z<0> VDD VSS / RSC_IHPSG13_WLDRVX12 +.ENDS +.SUBCKT RM_IHPSG13_256x16_c2_2P_DEC04 ADDR<3> ADDR<2> ADDR<1> ADDR<0> CS ECLK_H_BOT ++ ECLK_H_TOP ECLK_L_BOT ECLK_L_TOP WL<15> WL<14> WL<13> WL<12> WL<11> WL<10> ++ WL<9> WL<8> WL<7> WL<6> WL<5> WL<4> WL<3> WL<2> WL<1> WL<0> VDD VSS +XI0<3> PADR<1> PADR<0> sel01<3> VDD VSS / RSC_IHPSG13_NAND2X2 +XI0<2> PADR<1> NADR<0> sel01<2> VDD VSS / RSC_IHPSG13_NAND2X2 +XI0<1> NADR<1> PADR<0> sel01<1> VDD VSS / RSC_IHPSG13_NAND2X2 +XI0<0> NADR<1> NADR<0> sel01<0> VDD VSS / RSC_IHPSG13_NAND2X2 +XI4 ECLK_L_BOT EN VDD VSS / RSC_IHPSG13_CINVX4 +XI5 ECLK_H_BOT ECLK_L_BOT VDD VSS / RSC_IHPSG13_CINVX2 +XI3<3> PADR<3> NADR<3> VDD VSS / RSC_IHPSG13_INVX2 +XI3<2> PADR<2> NADR<2> VDD VSS / RSC_IHPSG13_INVX2 +XI3<1> PADR<1> NADR<1> VDD VSS / RSC_IHPSG13_INVX2 +XI3<0> PADR<0> NADR<0> VDD VSS / RSC_IHPSG13_INVX2 +XR0 ECLK_H_BOT ECLK_H_TOP / RSC_IHPSG13_MET2RES +XI11 ECLK_L_BOT ECLK_L_TOP / RSC_IHPSG13_MET2RES +XI1<3> PADR<2> PADR<3> CS sel23<3> VDD VSS / RSC_IHPSG13_NAND3X2 +XI1<2> NADR<2> PADR<3> CS sel23<2> VDD VSS / RSC_IHPSG13_NAND3X2 +XI1<1> PADR<2> NADR<3> CS sel23<1> VDD VSS / RSC_IHPSG13_NAND3X2 +XI1<0> NADR<2> NADR<3> CS sel23<0> VDD VSS / RSC_IHPSG13_NAND3X2 +XI2<15> sel23<3> sel01<3> EN WL<15> VDD VSS / RSC_IHPSG13_NOR3X2 +XI2<14> sel23<3> sel01<2> EN WL<14> VDD VSS / RSC_IHPSG13_NOR3X2 +XI2<13> sel23<3> sel01<1> EN WL<13> VDD VSS / RSC_IHPSG13_NOR3X2 +XI2<12> sel23<3> sel01<0> EN WL<12> VDD VSS / RSC_IHPSG13_NOR3X2 +XI2<11> sel23<2> sel01<3> EN WL<11> VDD VSS / RSC_IHPSG13_NOR3X2 +XI2<10> sel23<2> sel01<2> EN WL<10> VDD VSS / RSC_IHPSG13_NOR3X2 +XI2<9> sel23<2> sel01<1> EN WL<9> VDD VSS / RSC_IHPSG13_NOR3X2 +XI2<8> sel23<2> sel01<0> EN WL<8> VDD VSS / RSC_IHPSG13_NOR3X2 +XI2<7> sel23<1> sel01<3> EN WL<7> VDD VSS / RSC_IHPSG13_NOR3X2 +XI2<6> sel23<1> sel01<2> EN WL<6> VDD VSS / RSC_IHPSG13_NOR3X2 +XI2<5> sel23<1> sel01<1> EN WL<5> VDD VSS / RSC_IHPSG13_NOR3X2 +XI2<4> sel23<1> sel01<0> EN WL<4> VDD VSS / RSC_IHPSG13_NOR3X2 +XI2<3> sel23<0> sel01<3> EN WL<3> VDD VSS / RSC_IHPSG13_NOR3X2 +XI2<2> sel23<0> sel01<2> EN WL<2> VDD VSS / RSC_IHPSG13_NOR3X2 +XI2<1> sel23<0> sel01<1> EN WL<1> VDD VSS / RSC_IHPSG13_NOR3X2 +XI2<0> sel23<0> sel01<0> EN WL<0> VDD VSS / RSC_IHPSG13_NOR3X2 +XCAPS4 VDD VSS / RSC_IHPSG13_FILLCAP4 +XLATCH<3> CS ADDR<3> PADR<3> VDD VSS / RSC_IHPSG13_LHPQX2 +XLATCH<2> CS ADDR<2> PADR<2> VDD VSS / RSC_IHPSG13_LHPQX2 +XLATCH<1> CS ADDR<1> PADR<1> VDD VSS / RSC_IHPSG13_LHPQX2 +XLATCH<0> CS ADDR<0> PADR<0> VDD VSS / RSC_IHPSG13_LHPQX2 +.ENDS +.SUBCKT RM_IHPSG13_256x16_c2_2P_DEC02 ADDR<1> ADDR<0> CS CS_OUT VDD VSS +XDEC ADDR<1> NADDR<0> CS net1 VDD VSS / RSC_IHPSG13_NAND3X2 +XADDRINV ADDR<0> NADDR<0> VDD VSS / RSC_IHPSG13_INVX2 +XDECINV net1 CS_OUT VDD VSS / RSC_IHPSG13_INVX4 +XI2<1> VDD VSS / RSC_IHPSG13_FILLCAP4 +XI2<0> VDD VSS / RSC_IHPSG13_FILLCAP4 +.ENDS +.SUBCKT RM_IHPSG13_256x16_c2_2P_DEC01 ADDR<1> ADDR<0> CS CS_OUT VDD VSS +XDEC NADDR<1> ADDR<0> CS net1 VDD VSS / RSC_IHPSG13_NAND3X2 +XADDRINV ADDR<1> NADDR<1> VDD VSS / RSC_IHPSG13_INVX2 +XDECINV net1 CS_OUT VDD VSS / RSC_IHPSG13_INVX4 +XI2<1> VDD VSS / RSC_IHPSG13_FILLCAP4 +XI2<0> VDD VSS / RSC_IHPSG13_FILLCAP4 +.ENDS +.SUBCKT RM_IHPSG13_256x16_c2_2P_DEC00 ADDR<1> ADDR<0> CS CS_OUT VDD VSS +XDEC NADDR<1> NADDR<0> CS net1 VDD VSS / RSC_IHPSG13_NAND3X2 +XADDRINV<1> ADDR<1> NADDR<1> VDD VSS / RSC_IHPSG13_INVX2 +XADDRINV<0> ADDR<0> NADDR<0> VDD VSS / RSC_IHPSG13_INVX2 +XI1<1> VDD VSS / RSC_IHPSG13_FILLCAP4 +XI1<0> VDD VSS / RSC_IHPSG13_FILLCAP4 +XDECINV net1 CS_OUT VDD VSS / RSC_IHPSG13_INVX4 +.ENDS +.SUBCKT RM_IHPSG13_256x16_c2_2P_DEC03 ADDR<1> ADDR<0> CS CS_OUT VDD VSS +XDEC ADDR<1> ADDR<0> CS net1 VDD VSS / RSC_IHPSG13_NAND3X2 +XDECINV net1 CS_OUT VDD VSS / RSC_IHPSG13_INVX4 +XI0<1> VDD VSS / RSC_IHPSG13_FILLCAP4 +XI0<0> VDD VSS / RSC_IHPSG13_FILLCAP4 +.ENDS +.SUBCKT RM_IHPSG13_256x16_c2_2P_ROWDEC9 ADDR_N_I<8> ADDR_N_I<7> ADDR_N_I<6> ADDR_N_I<5> ++ ADDR_N_I<4> ADDR_N_I<3> ADDR_N_I<2> ADDR_N_I<1> ADDR_N_I<0> CS_I ECLK_I ++ WL_O<511> WL_O<510> WL_O<509> WL_O<508> WL_O<507> WL_O<506> WL_O<505> ++ WL_O<504> WL_O<503> WL_O<502> WL_O<501> WL_O<500> WL_O<499> WL_O<498> ++ WL_O<497> WL_O<496> WL_O<495> WL_O<494> WL_O<493> WL_O<492> WL_O<491> ++ WL_O<490> WL_O<489> WL_O<488> WL_O<487> WL_O<486> WL_O<485> WL_O<484> ++ WL_O<483> WL_O<482> WL_O<481> WL_O<480> WL_O<479> WL_O<478> WL_O<477> ++ WL_O<476> WL_O<475> WL_O<474> WL_O<473> WL_O<472> WL_O<471> WL_O<470> ++ WL_O<469> WL_O<468> WL_O<467> WL_O<466> WL_O<465> WL_O<464> WL_O<463> ++ WL_O<462> WL_O<461> WL_O<460> WL_O<459> WL_O<458> WL_O<457> WL_O<456> ++ WL_O<455> WL_O<454> WL_O<453> WL_O<452> WL_O<451> WL_O<450> WL_O<449> ++ WL_O<448> WL_O<447> WL_O<446> WL_O<445> WL_O<444> WL_O<443> WL_O<442> ++ WL_O<441> WL_O<440> WL_O<439> WL_O<438> WL_O<437> WL_O<436> WL_O<435> ++ WL_O<434> WL_O<433> WL_O<432> WL_O<431> WL_O<430> WL_O<429> WL_O<428> ++ WL_O<427> WL_O<426> WL_O<425> WL_O<424> WL_O<423> WL_O<422> WL_O<421> ++ WL_O<420> WL_O<419> WL_O<418> WL_O<417> WL_O<416> WL_O<415> WL_O<414> ++ WL_O<413> WL_O<412> WL_O<411> WL_O<410> WL_O<409> WL_O<408> WL_O<407> ++ WL_O<406> WL_O<405> WL_O<404> WL_O<403> WL_O<402> WL_O<401> WL_O<400> ++ WL_O<399> WL_O<398> WL_O<397> WL_O<396> WL_O<395> WL_O<394> WL_O<393> ++ WL_O<392> WL_O<391> WL_O<390> WL_O<389> WL_O<388> WL_O<387> WL_O<386> ++ WL_O<385> WL_O<384> WL_O<383> WL_O<382> WL_O<381> WL_O<380> WL_O<379> ++ WL_O<378> WL_O<377> WL_O<376> WL_O<375> WL_O<374> WL_O<373> WL_O<372> ++ WL_O<371> WL_O<370> WL_O<369> WL_O<368> WL_O<367> WL_O<366> WL_O<365> ++ WL_O<364> WL_O<363> WL_O<362> WL_O<361> WL_O<360> WL_O<359> WL_O<358> ++ WL_O<357> WL_O<356> WL_O<355> WL_O<354> WL_O<353> WL_O<352> WL_O<351> ++ WL_O<350> WL_O<349> WL_O<348> WL_O<347> WL_O<346> WL_O<345> WL_O<344> ++ WL_O<343> WL_O<342> WL_O<341> WL_O<340> WL_O<339> WL_O<338> WL_O<337> ++ WL_O<336> WL_O<335> WL_O<334> WL_O<333> WL_O<332> WL_O<331> WL_O<330> ++ WL_O<329> WL_O<328> WL_O<327> WL_O<326> WL_O<325> WL_O<324> WL_O<323> ++ WL_O<322> WL_O<321> WL_O<320> WL_O<319> WL_O<318> WL_O<317> WL_O<316> ++ WL_O<315> WL_O<314> WL_O<313> WL_O<312> WL_O<311> WL_O<310> WL_O<309> ++ WL_O<308> WL_O<307> WL_O<306> WL_O<305> WL_O<304> WL_O<303> WL_O<302> ++ WL_O<301> WL_O<300> WL_O<299> WL_O<298> WL_O<297> WL_O<296> WL_O<295> ++ WL_O<294> WL_O<293> WL_O<292> WL_O<291> WL_O<290> WL_O<289> WL_O<288> ++ WL_O<287> WL_O<286> WL_O<285> WL_O<284> WL_O<283> WL_O<282> WL_O<281> ++ WL_O<280> WL_O<279> WL_O<278> WL_O<277> WL_O<276> WL_O<275> WL_O<274> ++ WL_O<273> WL_O<272> WL_O<271> WL_O<270> WL_O<269> WL_O<268> WL_O<267> ++ WL_O<266> WL_O<265> WL_O<264> WL_O<263> WL_O<262> WL_O<261> WL_O<260> ++ WL_O<259> WL_O<258> WL_O<257> WL_O<256> WL_O<255> WL_O<254> WL_O<253> ++ WL_O<252> WL_O<251> WL_O<250> WL_O<249> WL_O<248> WL_O<247> WL_O<246> ++ WL_O<245> WL_O<244> WL_O<243> WL_O<242> WL_O<241> WL_O<240> WL_O<239> ++ WL_O<238> WL_O<237> WL_O<236> WL_O<235> WL_O<234> WL_O<233> WL_O<232> ++ WL_O<231> WL_O<230> WL_O<229> WL_O<228> WL_O<227> WL_O<226> WL_O<225> ++ WL_O<224> WL_O<223> WL_O<222> WL_O<221> WL_O<220> WL_O<219> WL_O<218> ++ WL_O<217> WL_O<216> WL_O<215> WL_O<214> WL_O<213> WL_O<212> WL_O<211> ++ WL_O<210> WL_O<209> WL_O<208> WL_O<207> WL_O<206> WL_O<205> WL_O<204> ++ WL_O<203> WL_O<202> WL_O<201> WL_O<200> WL_O<199> WL_O<198> WL_O<197> ++ WL_O<196> WL_O<195> WL_O<194> WL_O<193> WL_O<192> WL_O<191> WL_O<190> ++ WL_O<189> WL_O<188> WL_O<187> WL_O<186> WL_O<185> WL_O<184> WL_O<183> ++ WL_O<182> WL_O<181> WL_O<180> WL_O<179> WL_O<178> WL_O<177> WL_O<176> ++ WL_O<175> WL_O<174> WL_O<173> WL_O<172> WL_O<171> WL_O<170> WL_O<169> ++ WL_O<168> WL_O<167> WL_O<166> WL_O<165> WL_O<164> WL_O<163> WL_O<162> ++ WL_O<161> WL_O<160> WL_O<159> WL_O<158> WL_O<157> WL_O<156> WL_O<155> ++ WL_O<154> WL_O<153> WL_O<152> WL_O<151> WL_O<150> WL_O<149> WL_O<148> ++ WL_O<147> WL_O<146> WL_O<145> WL_O<144> WL_O<143> WL_O<142> WL_O<141> ++ WL_O<140> WL_O<139> WL_O<138> WL_O<137> WL_O<136> WL_O<135> WL_O<134> ++ WL_O<133> WL_O<132> WL_O<131> WL_O<130> WL_O<129> WL_O<128> WL_O<127> ++ WL_O<126> WL_O<125> WL_O<124> WL_O<123> WL_O<122> WL_O<121> WL_O<120> ++ WL_O<119> WL_O<118> WL_O<117> WL_O<116> WL_O<115> WL_O<114> WL_O<113> ++ WL_O<112> WL_O<111> WL_O<110> WL_O<109> WL_O<108> WL_O<107> WL_O<106> ++ WL_O<105> WL_O<104> WL_O<103> WL_O<102> WL_O<101> WL_O<100> WL_O<99> ++ WL_O<98> WL_O<97> WL_O<96> WL_O<95> WL_O<94> WL_O<93> WL_O<92> WL_O<91> ++ WL_O<90> WL_O<89> WL_O<88> WL_O<87> WL_O<86> WL_O<85> WL_O<84> WL_O<83> ++ WL_O<82> WL_O<81> WL_O<80> WL_O<79> WL_O<78> WL_O<77> WL_O<76> WL_O<75> ++ WL_O<74> WL_O<73> WL_O<72> WL_O<71> WL_O<70> WL_O<69> WL_O<68> WL_O<67> ++ WL_O<66> WL_O<65> WL_O<64> WL_O<63> WL_O<62> WL_O<61> WL_O<60> WL_O<59> ++ WL_O<58> WL_O<57> WL_O<56> WL_O<55> WL_O<54> WL_O<53> WL_O<52> WL_O<51> ++ WL_O<50> WL_O<49> WL_O<48> WL_O<47> WL_O<46> WL_O<45> WL_O<44> WL_O<43> ++ WL_O<42> WL_O<41> WL_O<40> WL_O<39> WL_O<38> WL_O<37> WL_O<36> WL_O<35> ++ WL_O<34> WL_O<33> WL_O<32> WL_O<31> WL_O<30> WL_O<29> WL_O<28> WL_O<27> ++ WL_O<26> WL_O<25> WL_O<24> WL_O<23> WL_O<22> WL_O<21> WL_O<20> WL_O<19> ++ WL_O<18> WL_O<17> WL_O<16> WL_O<15> WL_O<14> WL_O<13> WL_O<12> WL_O<11> ++ WL_O<10> WL_O<9> WL_O<8> WL_O<7> WL_O<6> WL_O<5> WL_O<4> WL_O<3> WL_O<2> ++ WL_O<1> WL_O<0> VDD VSS +XSEL<31> ADDR_N_I<3> ADDR_N_I<2> ADDR_N_I<1> ADDR_N_I<0> CS00<31> ECLK_H<31> ++ ECLK_H<32> ECLK_B<31> ECLK_B<32> WL_O<511> WL_O<510> WL_O<509> WL_O<508> ++ WL_O<507> WL_O<506> WL_O<505> WL_O<504> WL_O<503> WL_O<502> WL_O<501> ++ WL_O<500> WL_O<499> WL_O<498> WL_O<497> WL_O<496> VDD VSS / ++ RM_IHPSG13_256x16_c2_2P_DEC04 +XSEL<30> ADDR_N_I<3> ADDR_N_I<2> ADDR_N_I<1> ADDR_N_I<0> CS00<30> ECLK_H<30> ++ ECLK_H<31> ECLK_B<30> ECLK_B<31> WL_O<495> WL_O<494> WL_O<493> WL_O<492> ++ WL_O<491> WL_O<490> WL_O<489> WL_O<488> WL_O<487> WL_O<486> WL_O<485> ++ WL_O<484> WL_O<483> WL_O<482> WL_O<481> WL_O<480> VDD VSS / ++ RM_IHPSG13_256x16_c2_2P_DEC04 +XSEL<29> ADDR_N_I<3> ADDR_N_I<2> ADDR_N_I<1> ADDR_N_I<0> CS00<29> ECLK_H<29> ++ ECLK_H<30> ECLK_B<29> ECLK_B<30> WL_O<479> WL_O<478> WL_O<477> WL_O<476> ++ WL_O<475> WL_O<474> WL_O<473> WL_O<472> WL_O<471> WL_O<470> WL_O<469> ++ WL_O<468> WL_O<467> WL_O<466> WL_O<465> WL_O<464> VDD VSS / ++ RM_IHPSG13_256x16_c2_2P_DEC04 +XSEL<28> ADDR_N_I<3> ADDR_N_I<2> ADDR_N_I<1> ADDR_N_I<0> CS00<28> ECLK_H<28> ++ ECLK_H<29> ECLK_B<28> ECLK_B<29> WL_O<463> WL_O<462> WL_O<461> WL_O<460> ++ WL_O<459> WL_O<458> WL_O<457> WL_O<456> WL_O<455> WL_O<454> WL_O<453> ++ WL_O<452> WL_O<451> WL_O<450> WL_O<449> WL_O<448> VDD VSS / ++ RM_IHPSG13_256x16_c2_2P_DEC04 +XSEL<27> ADDR_N_I<3> ADDR_N_I<2> ADDR_N_I<1> ADDR_N_I<0> CS00<27> ECLK_H<27> ++ ECLK_H<28> ECLK_B<27> ECLK_B<28> WL_O<447> WL_O<446> WL_O<445> WL_O<444> ++ WL_O<443> WL_O<442> WL_O<441> WL_O<440> WL_O<439> WL_O<438> WL_O<437> ++ WL_O<436> WL_O<435> WL_O<434> WL_O<433> WL_O<432> VDD VSS / ++ RM_IHPSG13_256x16_c2_2P_DEC04 +XSEL<26> ADDR_N_I<3> ADDR_N_I<2> ADDR_N_I<1> ADDR_N_I<0> CS00<26> ECLK_H<26> ++ ECLK_H<27> ECLK_B<26> ECLK_B<27> WL_O<431> WL_O<430> WL_O<429> WL_O<428> ++ WL_O<427> WL_O<426> WL_O<425> WL_O<424> WL_O<423> WL_O<422> WL_O<421> ++ WL_O<420> WL_O<419> WL_O<418> WL_O<417> WL_O<416> VDD VSS / ++ RM_IHPSG13_256x16_c2_2P_DEC04 +XSEL<25> ADDR_N_I<3> ADDR_N_I<2> ADDR_N_I<1> ADDR_N_I<0> CS00<25> ECLK_H<25> ++ ECLK_H<26> ECLK_B<25> ECLK_B<26> WL_O<415> WL_O<414> WL_O<413> WL_O<412> ++ WL_O<411> WL_O<410> WL_O<409> WL_O<408> WL_O<407> WL_O<406> WL_O<405> ++ WL_O<404> WL_O<403> WL_O<402> WL_O<401> WL_O<400> VDD VSS / ++ RM_IHPSG13_256x16_c2_2P_DEC04 +XSEL<24> ADDR_N_I<3> ADDR_N_I<2> ADDR_N_I<1> ADDR_N_I<0> CS00<24> ECLK_H<24> ++ ECLK_H<25> ECLK_B<24> ECLK_B<25> WL_O<399> WL_O<398> WL_O<397> WL_O<396> ++ WL_O<395> WL_O<394> WL_O<393> WL_O<392> WL_O<391> WL_O<390> WL_O<389> ++ WL_O<388> WL_O<387> WL_O<386> WL_O<385> WL_O<384> VDD VSS / ++ RM_IHPSG13_256x16_c2_2P_DEC04 +XSEL<23> ADDR_N_I<3> ADDR_N_I<2> ADDR_N_I<1> ADDR_N_I<0> CS00<23> ECLK_H<23> ++ ECLK_H<24> ECLK_B<23> ECLK_B<24> WL_O<383> WL_O<382> WL_O<381> WL_O<380> ++ WL_O<379> WL_O<378> WL_O<377> WL_O<376> WL_O<375> WL_O<374> WL_O<373> ++ WL_O<372> WL_O<371> WL_O<370> WL_O<369> WL_O<368> VDD VSS / ++ RM_IHPSG13_256x16_c2_2P_DEC04 +XSEL<22> ADDR_N_I<3> ADDR_N_I<2> ADDR_N_I<1> ADDR_N_I<0> CS00<22> ECLK_H<22> ++ ECLK_H<23> ECLK_B<22> ECLK_B<23> WL_O<367> WL_O<366> WL_O<365> WL_O<364> ++ WL_O<363> WL_O<362> WL_O<361> WL_O<360> WL_O<359> WL_O<358> WL_O<357> ++ WL_O<356> WL_O<355> WL_O<354> WL_O<353> WL_O<352> VDD VSS / ++ RM_IHPSG13_256x16_c2_2P_DEC04 +XSEL<21> ADDR_N_I<3> ADDR_N_I<2> ADDR_N_I<1> ADDR_N_I<0> CS00<21> ECLK_H<21> ++ ECLK_H<22> ECLK_B<21> ECLK_B<22> WL_O<351> WL_O<350> WL_O<349> WL_O<348> ++ WL_O<347> WL_O<346> WL_O<345> WL_O<344> WL_O<343> WL_O<342> WL_O<341> ++ WL_O<340> WL_O<339> WL_O<338> WL_O<337> WL_O<336> VDD VSS / ++ RM_IHPSG13_256x16_c2_2P_DEC04 +XSEL<20> ADDR_N_I<3> ADDR_N_I<2> ADDR_N_I<1> ADDR_N_I<0> CS00<20> ECLK_H<20> ++ ECLK_H<21> ECLK_B<20> ECLK_B<21> WL_O<335> WL_O<334> WL_O<333> WL_O<332> ++ WL_O<331> WL_O<330> WL_O<329> WL_O<328> WL_O<327> WL_O<326> WL_O<325> ++ WL_O<324> WL_O<323> WL_O<322> WL_O<321> WL_O<320> VDD VSS / ++ RM_IHPSG13_256x16_c2_2P_DEC04 +XSEL<19> ADDR_N_I<3> ADDR_N_I<2> ADDR_N_I<1> ADDR_N_I<0> CS00<19> ECLK_H<19> ++ ECLK_H<20> ECLK_B<19> ECLK_B<20> WL_O<319> WL_O<318> WL_O<317> WL_O<316> ++ WL_O<315> WL_O<314> WL_O<313> WL_O<312> WL_O<311> WL_O<310> WL_O<309> ++ WL_O<308> WL_O<307> WL_O<306> WL_O<305> WL_O<304> VDD VSS / ++ RM_IHPSG13_256x16_c2_2P_DEC04 +XSEL<18> ADDR_N_I<3> ADDR_N_I<2> ADDR_N_I<1> ADDR_N_I<0> CS00<18> ECLK_H<18> ++ ECLK_H<19> ECLK_B<18> ECLK_B<19> WL_O<303> WL_O<302> WL_O<301> WL_O<300> ++ WL_O<299> WL_O<298> WL_O<297> WL_O<296> WL_O<295> WL_O<294> WL_O<293> ++ WL_O<292> WL_O<291> WL_O<290> WL_O<289> WL_O<288> VDD VSS / ++ RM_IHPSG13_256x16_c2_2P_DEC04 +XSEL<17> ADDR_N_I<3> ADDR_N_I<2> ADDR_N_I<1> ADDR_N_I<0> CS00<17> ECLK_H<17> ++ ECLK_H<18> ECLK_B<17> ECLK_B<18> WL_O<287> WL_O<286> WL_O<285> WL_O<284> ++ WL_O<283> WL_O<282> WL_O<281> WL_O<280> WL_O<279> WL_O<278> WL_O<277> ++ WL_O<276> WL_O<275> WL_O<274> WL_O<273> WL_O<272> VDD VSS / ++ RM_IHPSG13_256x16_c2_2P_DEC04 +XSEL<16> ADDR_N_I<3> ADDR_N_I<2> ADDR_N_I<1> ADDR_N_I<0> CS00<16> ECLK_H<16> ++ ECLK_H<17> ECLK_B<16> ECLK_B<17> WL_O<271> WL_O<270> WL_O<269> WL_O<268> ++ WL_O<267> WL_O<266> WL_O<265> WL_O<264> WL_O<263> WL_O<262> WL_O<261> ++ WL_O<260> WL_O<259> WL_O<258> WL_O<257> WL_O<256> VDD VSS / ++ RM_IHPSG13_256x16_c2_2P_DEC04 +XSEL<15> ADDR_N_I<3> ADDR_N_I<2> ADDR_N_I<1> ADDR_N_I<0> CS00<15> ECLK_H<15> ++ ECLK_H<16> ECLK_B<15> ECLK_B<16> WL_O<255> WL_O<254> WL_O<253> WL_O<252> ++ WL_O<251> WL_O<250> WL_O<249> WL_O<248> WL_O<247> WL_O<246> WL_O<245> ++ WL_O<244> WL_O<243> WL_O<242> WL_O<241> WL_O<240> VDD VSS / ++ RM_IHPSG13_256x16_c2_2P_DEC04 +XSEL<14> ADDR_N_I<3> ADDR_N_I<2> ADDR_N_I<1> ADDR_N_I<0> CS00<14> ECLK_H<14> ++ ECLK_H<15> ECLK_B<14> ECLK_B<15> WL_O<239> WL_O<238> WL_O<237> WL_O<236> ++ WL_O<235> WL_O<234> WL_O<233> WL_O<232> WL_O<231> WL_O<230> WL_O<229> ++ WL_O<228> WL_O<227> WL_O<226> WL_O<225> WL_O<224> VDD VSS / ++ RM_IHPSG13_256x16_c2_2P_DEC04 +XSEL<13> ADDR_N_I<3> ADDR_N_I<2> ADDR_N_I<1> ADDR_N_I<0> CS00<13> ECLK_H<13> ++ ECLK_H<14> ECLK_B<13> ECLK_B<14> WL_O<223> WL_O<222> WL_O<221> WL_O<220> ++ WL_O<219> WL_O<218> WL_O<217> WL_O<216> WL_O<215> WL_O<214> WL_O<213> ++ WL_O<212> WL_O<211> WL_O<210> WL_O<209> WL_O<208> VDD VSS / ++ RM_IHPSG13_256x16_c2_2P_DEC04 +XSEL<12> ADDR_N_I<3> ADDR_N_I<2> ADDR_N_I<1> ADDR_N_I<0> CS00<12> ECLK_H<12> ++ ECLK_H<13> ECLK_B<12> ECLK_B<13> WL_O<207> WL_O<206> WL_O<205> WL_O<204> ++ WL_O<203> WL_O<202> WL_O<201> WL_O<200> WL_O<199> WL_O<198> WL_O<197> ++ WL_O<196> WL_O<195> WL_O<194> WL_O<193> WL_O<192> VDD VSS / ++ RM_IHPSG13_256x16_c2_2P_DEC04 +XSEL<11> ADDR_N_I<3> ADDR_N_I<2> ADDR_N_I<1> ADDR_N_I<0> CS00<11> ECLK_H<11> ++ ECLK_H<12> ECLK_B<11> ECLK_B<12> WL_O<191> WL_O<190> WL_O<189> WL_O<188> ++ WL_O<187> WL_O<186> WL_O<185> WL_O<184> WL_O<183> WL_O<182> WL_O<181> ++ WL_O<180> WL_O<179> WL_O<178> WL_O<177> WL_O<176> VDD VSS / ++ RM_IHPSG13_256x16_c2_2P_DEC04 +XSEL<10> ADDR_N_I<3> ADDR_N_I<2> ADDR_N_I<1> ADDR_N_I<0> CS00<10> ECLK_H<10> ++ ECLK_H<11> ECLK_B<10> ECLK_B<11> WL_O<175> WL_O<174> WL_O<173> WL_O<172> ++ WL_O<171> WL_O<170> WL_O<169> WL_O<168> WL_O<167> WL_O<166> WL_O<165> ++ WL_O<164> WL_O<163> WL_O<162> WL_O<161> WL_O<160> VDD VSS / ++ RM_IHPSG13_256x16_c2_2P_DEC04 +XSEL<9> ADDR_N_I<3> ADDR_N_I<2> ADDR_N_I<1> ADDR_N_I<0> CS00<9> ECLK_H<9> ++ ECLK_H<10> ECLK_B<9> ECLK_B<10> WL_O<159> WL_O<158> WL_O<157> WL_O<156> ++ WL_O<155> WL_O<154> WL_O<153> WL_O<152> WL_O<151> WL_O<150> WL_O<149> ++ WL_O<148> WL_O<147> WL_O<146> WL_O<145> WL_O<144> VDD VSS / ++ RM_IHPSG13_256x16_c2_2P_DEC04 +XSEL<8> ADDR_N_I<3> ADDR_N_I<2> ADDR_N_I<1> ADDR_N_I<0> CS00<8> ECLK_H<8> ++ ECLK_H<9> ECLK_B<8> ECLK_B<9> WL_O<143> WL_O<142> WL_O<141> WL_O<140> ++ WL_O<139> WL_O<138> WL_O<137> WL_O<136> WL_O<135> WL_O<134> WL_O<133> ++ WL_O<132> WL_O<131> WL_O<130> WL_O<129> WL_O<128> VDD VSS / ++ RM_IHPSG13_256x16_c2_2P_DEC04 +XSEL<7> ADDR_N_I<3> ADDR_N_I<2> ADDR_N_I<1> ADDR_N_I<0> CS00<7> ECLK_H<7> ++ ECLK_H<8> ECLK_B<7> ECLK_B<8> WL_O<127> WL_O<126> WL_O<125> WL_O<124> ++ WL_O<123> WL_O<122> WL_O<121> WL_O<120> WL_O<119> WL_O<118> WL_O<117> ++ WL_O<116> WL_O<115> WL_O<114> WL_O<113> WL_O<112> VDD VSS / ++ RM_IHPSG13_256x16_c2_2P_DEC04 +XSEL<6> ADDR_N_I<3> ADDR_N_I<2> ADDR_N_I<1> ADDR_N_I<0> CS00<6> ECLK_H<6> ++ ECLK_H<7> ECLK_B<6> ECLK_B<7> WL_O<111> WL_O<110> WL_O<109> WL_O<108> ++ WL_O<107> WL_O<106> WL_O<105> WL_O<104> WL_O<103> WL_O<102> WL_O<101> ++ WL_O<100> WL_O<99> WL_O<98> WL_O<97> WL_O<96> VDD VSS / ++ RM_IHPSG13_256x16_c2_2P_DEC04 +XSEL<5> ADDR_N_I<3> ADDR_N_I<2> ADDR_N_I<1> ADDR_N_I<0> CS00<5> ECLK_H<5> ++ ECLK_H<6> ECLK_B<5> ECLK_B<6> WL_O<95> WL_O<94> WL_O<93> WL_O<92> WL_O<91> ++ WL_O<90> WL_O<89> WL_O<88> WL_O<87> WL_O<86> WL_O<85> WL_O<84> WL_O<83> ++ WL_O<82> WL_O<81> WL_O<80> VDD VSS / RM_IHPSG13_256x16_c2_2P_DEC04 +XSEL<4> ADDR_N_I<3> ADDR_N_I<2> ADDR_N_I<1> ADDR_N_I<0> CS00<4> ECLK_H<4> ++ ECLK_H<5> ECLK_B<4> ECLK_B<5> WL_O<79> WL_O<78> WL_O<77> WL_O<76> WL_O<75> ++ WL_O<74> WL_O<73> WL_O<72> WL_O<71> WL_O<70> WL_O<69> WL_O<68> WL_O<67> ++ WL_O<66> WL_O<65> WL_O<64> VDD VSS / RM_IHPSG13_256x16_c2_2P_DEC04 +XSEL<3> ADDR_N_I<3> ADDR_N_I<2> ADDR_N_I<1> ADDR_N_I<0> CS00<3> ECLK_H<3> ++ ECLK_H<4> ECLK_B<3> ECLK_B<4> WL_O<63> WL_O<62> WL_O<61> WL_O<60> WL_O<59> ++ WL_O<58> WL_O<57> WL_O<56> WL_O<55> WL_O<54> WL_O<53> WL_O<52> WL_O<51> ++ WL_O<50> WL_O<49> WL_O<48> VDD VSS / RM_IHPSG13_256x16_c2_2P_DEC04 +XSEL<2> ADDR_N_I<3> ADDR_N_I<2> ADDR_N_I<1> ADDR_N_I<0> CS00<2> ECLK_H<2> ++ ECLK_H<3> ECLK_B<2> ECLK_B<3> WL_O<47> WL_O<46> WL_O<45> WL_O<44> WL_O<43> ++ WL_O<42> WL_O<41> WL_O<40> WL_O<39> WL_O<38> WL_O<37> WL_O<36> WL_O<35> ++ WL_O<34> WL_O<33> WL_O<32> VDD VSS / RM_IHPSG13_256x16_c2_2P_DEC04 +XSEL<1> ADDR_N_I<3> ADDR_N_I<2> ADDR_N_I<1> ADDR_N_I<0> CS00<1> ECLK_H<1> ++ ECLK_H<2> ECLK_B<1> ECLK_B<2> WL_O<31> WL_O<30> WL_O<29> WL_O<28> WL_O<27> ++ WL_O<26> WL_O<25> WL_O<24> WL_O<23> WL_O<22> WL_O<21> WL_O<20> WL_O<19> ++ WL_O<18> WL_O<17> WL_O<16> VDD VSS / RM_IHPSG13_256x16_c2_2P_DEC04 +XSEL<0> ADDR_N_I<3> ADDR_N_I<2> ADDR_N_I<1> ADDR_N_I<0> CS00<0> ECLK_I ++ ECLK_H<1> ECLK_B<0> ECLK_B<1> WL_O<15> WL_O<14> WL_O<13> WL_O<12> WL_O<11> ++ WL_O<10> WL_O<9> WL_O<8> WL_O<7> WL_O<6> WL_O<5> WL_O<4> WL_O<3> WL_O<2> ++ WL_O<1> WL_O<0> VDD VSS / RM_IHPSG13_256x16_c2_2P_DEC04 +XDEC10<9> ADDR_N_I<7> ADDR_N_I<6> CS04<1> CS02<6> VDD VSS / ++ RM_IHPSG13_256x16_c2_2P_DEC02 +XDEC10<8> ADDR_N_I<7> ADDR_N_I<6> CS04<0> CS02<2> VDD VSS / ++ RM_IHPSG13_256x16_c2_2P_DEC02 +XDEC10<7> ADDR_N_I<5> ADDR_N_I<4> CS02<7> CS00<30> VDD VSS / ++ RM_IHPSG13_256x16_c2_2P_DEC02 +XDEC10<6> ADDR_N_I<5> ADDR_N_I<4> CS02<6> CS00<26> VDD VSS / ++ RM_IHPSG13_256x16_c2_2P_DEC02 +XDEC10<5> ADDR_N_I<5> ADDR_N_I<4> CS02<5> CS00<22> VDD VSS / ++ RM_IHPSG13_256x16_c2_2P_DEC02 +XDEC10<4> ADDR_N_I<5> ADDR_N_I<4> CS02<4> CS00<18> VDD VSS / ++ RM_IHPSG13_256x16_c2_2P_DEC02 +XDEC10<3> ADDR_N_I<5> ADDR_N_I<4> CS02<3> CS00<14> VDD VSS / ++ RM_IHPSG13_256x16_c2_2P_DEC02 +XDEC10<2> ADDR_N_I<5> ADDR_N_I<4> CS02<2> CS00<10> VDD VSS / ++ RM_IHPSG13_256x16_c2_2P_DEC02 +XDEC10<1> ADDR_N_I<5> ADDR_N_I<4> CS02<1> CS00<6> VDD VSS / ++ RM_IHPSG13_256x16_c2_2P_DEC02 +XDEC10<0> ADDR_N_I<5> ADDR_N_I<4> CS02<0> CS00<2> VDD VSS / ++ RM_IHPSG13_256x16_c2_2P_DEC02 +XDEC01<10> ADDR_N_I<9> ADDR_N_I<8> CS_I CS04<1> VDD VSS / ++ RM_IHPSG13_256x16_c2_2P_DEC01 +XDEC01<9> ADDR_N_I<7> ADDR_N_I<6> CS04<1> CS02<5> VDD VSS / ++ RM_IHPSG13_256x16_c2_2P_DEC01 +XDEC01<8> ADDR_N_I<7> ADDR_N_I<6> CS04<0> CS02<1> VDD VSS / ++ RM_IHPSG13_256x16_c2_2P_DEC01 +XDEC01<7> ADDR_N_I<5> ADDR_N_I<4> CS02<7> CS00<29> VDD VSS / ++ RM_IHPSG13_256x16_c2_2P_DEC01 +XDEC01<6> ADDR_N_I<5> ADDR_N_I<4> CS02<6> CS00<25> VDD VSS / ++ RM_IHPSG13_256x16_c2_2P_DEC01 +XDEC01<5> ADDR_N_I<5> ADDR_N_I<4> CS02<5> CS00<21> VDD VSS / ++ RM_IHPSG13_256x16_c2_2P_DEC01 +XDEC01<4> ADDR_N_I<5> ADDR_N_I<4> CS02<4> CS00<17> VDD VSS / ++ RM_IHPSG13_256x16_c2_2P_DEC01 +XDEC01<3> ADDR_N_I<5> ADDR_N_I<4> CS02<3> CS00<13> VDD VSS / ++ RM_IHPSG13_256x16_c2_2P_DEC01 +XDEC01<2> ADDR_N_I<5> ADDR_N_I<4> CS02<2> CS00<9> VDD VSS / ++ RM_IHPSG13_256x16_c2_2P_DEC01 +XDEC01<1> ADDR_N_I<5> ADDR_N_I<4> CS02<1> CS00<5> VDD VSS / ++ RM_IHPSG13_256x16_c2_2P_DEC01 +XDEC01<0> ADDR_N_I<5> ADDR_N_I<4> CS02<0> CS00<1> VDD VSS / ++ RM_IHPSG13_256x16_c2_2P_DEC01 +XL2<258> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<257> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<256> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<255> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<254> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<253> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<252> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<251> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<250> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<249> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<248> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<247> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<246> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<245> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<244> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<243> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<242> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<241> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<240> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<239> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<238> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<237> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<236> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<235> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<234> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<233> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<232> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<231> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<230> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<229> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<228> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<227> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<226> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<225> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<224> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<223> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<222> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<221> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<220> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<219> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<218> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<217> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<216> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<215> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<214> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<213> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<212> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<211> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<210> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<209> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<208> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<207> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<206> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<205> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<204> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<203> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<202> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<201> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<200> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<199> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<198> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<197> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<196> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<195> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<194> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<193> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<192> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<191> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<190> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<189> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<188> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<187> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<186> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<185> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<184> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<183> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<182> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<181> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<180> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<179> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<178> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<177> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<176> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<175> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<174> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<173> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<172> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<171> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<170> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<169> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<168> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<167> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<166> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<165> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<164> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<163> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<162> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<161> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<160> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<159> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<158> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<157> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<156> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<155> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<154> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<153> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<152> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<151> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<150> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<149> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<148> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<147> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<146> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<145> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<144> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<143> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<142> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<141> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<140> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<139> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<138> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<137> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<136> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<135> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<134> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<133> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<132> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<131> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<130> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<129> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<128> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<127> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<126> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<125> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<124> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<123> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<122> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<121> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<120> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<119> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<118> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<117> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<116> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<115> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<114> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<113> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<112> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<111> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<110> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<109> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<108> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<107> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<106> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<105> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<104> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<103> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<102> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<101> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<100> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<99> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<98> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<97> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<96> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<95> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<94> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<93> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<92> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<91> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<90> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<89> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<88> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<87> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<86> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<85> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<84> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<83> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<82> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<81> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<80> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<79> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<78> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<77> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<76> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<75> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<74> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<73> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<72> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<71> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<70> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<69> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<68> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<67> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<66> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<65> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<64> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<63> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<62> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<61> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<60> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<59> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<58> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<57> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<56> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<55> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<54> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<53> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<52> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<51> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<50> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<49> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<48> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<47> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<46> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<45> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<44> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<43> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<42> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<41> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<40> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<39> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<38> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<37> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<36> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<35> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<34> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<33> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<32> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<31> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<30> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<29> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<28> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<27> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<26> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<25> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<24> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<23> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<22> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<21> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<20> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<19> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<18> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<17> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<16> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<15> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<14> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<13> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<12> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<11> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<10> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<9> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<8> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<7> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<6> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<5> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<4> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<3> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<2> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<1> VDD VSS / RSC_IHPSG13_FILLCAP8 +XDEC00<10> ADDR_N_I<9> ADDR_N_I<8> CS_I CS04<0> VDD VSS / ++ RM_IHPSG13_256x16_c2_2P_DEC00 +XDEC00<9> ADDR_N_I<7> ADDR_N_I<6> CS04<1> CS02<4> VDD VSS / ++ RM_IHPSG13_256x16_c2_2P_DEC00 +XDEC00<8> ADDR_N_I<7> ADDR_N_I<6> CS04<0> CS02<0> VDD VSS / ++ RM_IHPSG13_256x16_c2_2P_DEC00 +XDEC00<7> ADDR_N_I<5> ADDR_N_I<4> CS02<7> CS00<28> VDD VSS / ++ RM_IHPSG13_256x16_c2_2P_DEC00 +XDEC00<6> ADDR_N_I<5> ADDR_N_I<4> CS02<6> CS00<24> VDD VSS / ++ RM_IHPSG13_256x16_c2_2P_DEC00 +XDEC00<5> ADDR_N_I<5> ADDR_N_I<4> CS02<5> CS00<20> VDD VSS / ++ RM_IHPSG13_256x16_c2_2P_DEC00 +XDEC00<4> ADDR_N_I<5> ADDR_N_I<4> CS02<4> CS00<16> VDD VSS / ++ RM_IHPSG13_256x16_c2_2P_DEC00 +XDEC00<3> ADDR_N_I<5> ADDR_N_I<4> CS02<3> CS00<12> VDD VSS / ++ RM_IHPSG13_256x16_c2_2P_DEC00 +XDEC00<2> ADDR_N_I<5> ADDR_N_I<4> CS02<2> CS00<8> VDD VSS / ++ RM_IHPSG13_256x16_c2_2P_DEC00 +XDEC00<1> ADDR_N_I<5> ADDR_N_I<4> CS02<1> CS00<4> VDD VSS / ++ RM_IHPSG13_256x16_c2_2P_DEC00 +XDEC00<0> ADDR_N_I<5> ADDR_N_I<4> CS02<0> CS00<0> VDD VSS / ++ RM_IHPSG13_256x16_c2_2P_DEC00 +XDEC11<9> ADDR_N_I<7> ADDR_N_I<6> CS04<1> CS02<7> VDD VSS / ++ RM_IHPSG13_256x16_c2_2P_DEC03 +XDEC11<8> ADDR_N_I<7> ADDR_N_I<6> CS04<0> CS02<3> VDD VSS / ++ RM_IHPSG13_256x16_c2_2P_DEC03 +XDEC11<7> ADDR_N_I<5> ADDR_N_I<4> CS02<7> CS00<31> VDD VSS / ++ RM_IHPSG13_256x16_c2_2P_DEC03 +XDEC11<6> ADDR_N_I<5> ADDR_N_I<4> CS02<6> CS00<27> VDD VSS / ++ RM_IHPSG13_256x16_c2_2P_DEC03 +XDEC11<5> ADDR_N_I<5> ADDR_N_I<4> CS02<5> CS00<23> VDD VSS / ++ RM_IHPSG13_256x16_c2_2P_DEC03 +XDEC11<4> ADDR_N_I<5> ADDR_N_I<4> CS02<4> CS00<19> VDD VSS / ++ RM_IHPSG13_256x16_c2_2P_DEC03 +XDEC11<3> ADDR_N_I<5> ADDR_N_I<4> CS02<3> CS00<15> VDD VSS / ++ RM_IHPSG13_256x16_c2_2P_DEC03 +XDEC11<2> ADDR_N_I<5> ADDR_N_I<4> CS02<2> CS00<11> VDD VSS / ++ RM_IHPSG13_256x16_c2_2P_DEC03 +XDEC11<1> ADDR_N_I<5> ADDR_N_I<4> CS02<1> CS00<7> VDD VSS / ++ RM_IHPSG13_256x16_c2_2P_DEC03 +XDEC11<0> ADDR_N_I<5> ADDR_N_I<4> CS02<0> CS00<3> VDD VSS / ++ RM_IHPSG13_256x16_c2_2P_DEC03 +XI0 ADDR_N_I<9> VDD VSS / RSC_IHPSG13_TIEL +.ENDS +.SUBCKT RM_IHPSG13_256x16_c2_2P_ROWREG9 ACLK_N_I ADDR_I<8> ADDR_I<7> ADDR_I<6> ADDR_I<5> ++ ADDR_I<4> ADDR_I<3> ADDR_I<2> ADDR_I<1> ADDR_I<0> ADDR_N_O<8> ADDR_N_O<7> ++ ADDR_N_O<6> ADDR_N_O<5> ADDR_N_O<4> ADDR_N_O<3> ADDR_N_O<2> ADDR_N_O<1> ++ ADDR_N_O<0> BIST_ADDR_I<8> BIST_ADDR_I<7> BIST_ADDR_I<6> BIST_ADDR_I<5> ++ BIST_ADDR_I<4> BIST_ADDR_I<3> BIST_ADDR_I<2> BIST_ADDR_I<1> BIST_ADDR_I<0> ++ BIST_EN_I VDD VSS +XDFF<8> BIST_EN_I BIST_ADDR_I<8> ACLK_N_I ADDR_I<8> q_int<8> net04<0> VDD ++ VSS / RSC_IHPSG13_DFNQMX2IX1 +XDFF<7> BIST_EN_I BIST_ADDR_I<7> ACLK_N_I ADDR_I<7> q_int<7> net04<1> VDD ++ VSS / RSC_IHPSG13_DFNQMX2IX1 +XDFF<6> BIST_EN_I BIST_ADDR_I<6> ACLK_N_I ADDR_I<6> q_int<6> net04<2> VDD ++ VSS / RSC_IHPSG13_DFNQMX2IX1 +XDFF<5> BIST_EN_I BIST_ADDR_I<5> ACLK_N_I ADDR_I<5> q_int<5> net04<3> VDD ++ VSS / RSC_IHPSG13_DFNQMX2IX1 +XDFF<4> BIST_EN_I BIST_ADDR_I<4> ACLK_N_I ADDR_I<4> q_int<4> net04<4> VDD ++ VSS / RSC_IHPSG13_DFNQMX2IX1 +XDFF<3> BIST_EN_I BIST_ADDR_I<3> ACLK_N_I ADDR_I<3> q_int<3> net04<5> VDD ++ VSS / RSC_IHPSG13_DFNQMX2IX1 +XDFF<2> BIST_EN_I BIST_ADDR_I<2> ACLK_N_I ADDR_I<2> q_int<2> net04<6> VDD ++ VSS / RSC_IHPSG13_DFNQMX2IX1 +XDFF<1> BIST_EN_I BIST_ADDR_I<1> ACLK_N_I ADDR_I<1> q_int<1> net04<7> VDD ++ VSS / RSC_IHPSG13_DFNQMX2IX1 +XDFF<0> BIST_EN_I BIST_ADDR_I<0> ACLK_N_I ADDR_I<0> q_int<0> net04<8> VDD ++ VSS / RSC_IHPSG13_DFNQMX2IX1 +XDRV<8> qn_int<8> ADDR_N_O<8> VDD VSS / RSC_IHPSG13_CINVX8 +XDRV<7> qn_int<7> ADDR_N_O<7> VDD VSS / RSC_IHPSG13_CINVX8 +XDRV<6> qn_int<6> ADDR_N_O<6> VDD VSS / RSC_IHPSG13_CINVX8 +XDRV<5> qn_int<5> ADDR_N_O<5> VDD VSS / RSC_IHPSG13_CINVX8 +XDRV<4> qn_int<4> ADDR_N_O<4> VDD VSS / RSC_IHPSG13_CINVX8 +XDRV<3> qn_int<3> ADDR_N_O<3> VDD VSS / RSC_IHPSG13_CINVX8 +XDRV<2> qn_int<2> ADDR_N_O<2> VDD VSS / RSC_IHPSG13_CINVX8 +XDRV<1> qn_int<1> ADDR_N_O<1> VDD VSS / RSC_IHPSG13_CINVX8 +XDRV<0> qn_int<0> ADDR_N_O<0> VDD VSS / RSC_IHPSG13_CINVX8 +XINV<8> q_int<8> qn_int<8> VDD VSS / RSC_IHPSG13_CINVX2 +XINV<7> q_int<7> qn_int<7> VDD VSS / RSC_IHPSG13_CINVX2 +XINV<6> q_int<6> qn_int<6> VDD VSS / RSC_IHPSG13_CINVX2 +XINV<5> q_int<5> qn_int<5> VDD VSS / RSC_IHPSG13_CINVX2 +XINV<4> q_int<4> qn_int<4> VDD VSS / RSC_IHPSG13_CINVX2 +XINV<3> q_int<3> qn_int<3> VDD VSS / RSC_IHPSG13_CINVX2 +XINV<2> q_int<2> qn_int<2> VDD VSS / RSC_IHPSG13_CINVX2 +XINV<1> q_int<1> qn_int<1> VDD VSS / RSC_IHPSG13_CINVX2 +XINV<0> q_int<0> qn_int<0> VDD VSS / RSC_IHPSG13_CINVX2 +.ENDS + +.SUBCKT RM_IHPSG13_256x16_c2_2P_DLY_MUX A SEL Z VDD VSS +XI11 net4 Z VDD VSS / RSC_IHPSG13_CINVX2 +XI8 A D<3> SEL net4 VDD VSS / RSC_IHPSG13_MX2IX1 +XI20<3> D<2> D<3> VDD VSS / RSC_IHPSG13_CDLYX1 +XI20<2> D<1> D<2> VDD VSS / RSC_IHPSG13_CDLYX1 +XI20<1> A D<1> VDD VSS / RSC_IHPSG13_CDLYX1 +.ENDS +.SUBCKT RM_IHPSG13_256x16_c2_2P_CTRL ACLK_N BIST_CK_I BIST_CS_I BIST_EN BIST_RE_I ++ BIST_WE_I B_TIEL_O CK_I CS_I DCLK ECLK PULSE_H PULSE_L PULSE_O RCLK RE_I ++ ROW_CS WCLK WE_I VDD VSS +XI17 ck_regs we col_we VDD VSS / RSC_IHPSG13_DFNQX2 +XI16 ck_regs re col_re VDD VSS / RSC_IHPSG13_DFNQX2 +XI18 ck_regs cs net7 VDD VSS / RSC_IHPSG13_DFNQX2 +XI71 ACLK_N net012 PULSE_O VDD VSS / RSC_IHPSG13_DFNQX2 +XI77 col_we net017 net016 VDD VSS / RSC_IHPSG13_CNAND2X2 +XI76 col_re net017 net018 VDD VSS / RSC_IHPSG13_CNAND2X2 +XI15 ck_dly WEorREandCS aclk VDD VSS / RSC_IHPSG13_CGATEPX4 +XI14 ck WEandCS DCLK VDD VSS / RSC_IHPSG13_CGATEPX4 +XI60 net7 ROW_CS VDD VSS / RSC_IHPSG13_CBUFX8 +XI73 PULSE_O net012 VDD VSS / RSC_IHPSG13_CINVX2 +XI8 net017 net8 VDD VSS / RSC_IHPSG13_CINVX2 +XCAPS4<7> VDD VSS / RSC_IHPSG13_FILLCAP4 +XCAPS4<6> VDD VSS / RSC_IHPSG13_FILLCAP4 +XCAPS4<5> VDD VSS / RSC_IHPSG13_FILLCAP4 +XCAPS4<4> VDD VSS / RSC_IHPSG13_FILLCAP4 +XCAPS4<3> VDD VSS / RSC_IHPSG13_FILLCAP4 +XCAPS4<2> VDD VSS / RSC_IHPSG13_FILLCAP4 +XCAPS4<1> VDD VSS / RSC_IHPSG13_FILLCAP4 +XBM_TIEL B_TIEL_O VDD VSS / RSC_IHPSG13_TIEL +XI64 ck ck_dly VDD VSS / RSC_IHPSG13_CDLYX2 +XI86 CS_I BIST_CS_I BIST_EN cs VDD VSS / RSC_IHPSG13_MX2X2 +XI87 CK_I BIST_CK_I BIST_EN ck VDD VSS / RSC_IHPSG13_MX2X2 +XI85 WE_I BIST_WE_I BIST_EN we VDD VSS / RSC_IHPSG13_MX2X2 +XI84 RE_I BIST_RE_I BIST_EN re VDD VSS / RSC_IHPSG13_MX2X2 +XI48 ck_dly ck_regs VDD VSS / RSC_IHPSG13_CINVX4 +XI81 net016 WCLK VDD VSS / RSC_IHPSG13_CINVX4 +XI80 net018 RCLK VDD VSS / RSC_IHPSG13_CINVX4 +XI78 net8 net020 VDD VSS / RSC_IHPSG13_CINVX4 +XCAPS8<7> VDD VSS / RSC_IHPSG13_FILLCAP8 +XCAPS8<6> VDD VSS / RSC_IHPSG13_FILLCAP8 +XCAPS8<5> VDD VSS / RSC_IHPSG13_FILLCAP8 +XCAPS8<4> VDD VSS / RSC_IHPSG13_FILLCAP8 +XCAPS8<3> VDD VSS / RSC_IHPSG13_FILLCAP8 +XCAPS8<2> VDD VSS / RSC_IHPSG13_FILLCAP8 +XCAPS8<1> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI6 PULSE_L PULSE_H net017 VDD VSS / RSC_IHPSG13_XOR2X2 +XI22 we cs WEandCS VDD VSS / RSC_IHPSG13_AND2X2 +XI79 net020 ECLK VDD VSS / RSC_IHPSG13_CINVX8 +XI63 aclk ACLK_N VDD VSS / RSC_IHPSG13_CINVX8 +XI21 re we cs WEorREandCS VDD VSS / RSC_IHPSG13_OA12X1 +.ENDS +.SUBCKT RM_IHPSG13_256x16_c2_2P_COLDEC5 ACLK_N ADDR<4> ADDR<3> ADDR<2> ADDR<1> ADDR<0> ++ ADDR_COL<1> ADDR_COL<0> ADDR_DEC<7> ADDR_DEC<6> ADDR_DEC<5> ADDR_DEC<4> ++ ADDR_DEC<3> ADDR_DEC<2> ADDR_DEC<1> ADDR_DEC<0> BIST_ADDR<4> BIST_ADDR<3> ++ BIST_ADDR<2> BIST_ADDR<1> BIST_ADDR<0> BIST_EN_I VDD VSS +XI17<4> VDD VSS / RSC_IHPSG13_FILLCAP4 +XI17<3> VDD VSS / RSC_IHPSG13_FILLCAP4 +XI17<2> VDD VSS / RSC_IHPSG13_FILLCAP4 +XI17<1> VDD VSS / RSC_IHPSG13_FILLCAP4 +XI1<7> PADR<0> PADR<1> PADR<2> addr_n<7> VDD VSS / RSC_IHPSG13_NAND3X2 +XI1<6> NADR<0> PADR<1> PADR<2> addr_n<6> VDD VSS / RSC_IHPSG13_NAND3X2 +XI1<5> PADR<0> NADR<1> PADR<2> addr_n<5> VDD VSS / RSC_IHPSG13_NAND3X2 +XI1<4> NADR<0> NADR<1> PADR<2> addr_n<4> VDD VSS / RSC_IHPSG13_NAND3X2 +XI1<3> PADR<0> PADR<1> NADR<2> addr_n<3> VDD VSS / RSC_IHPSG13_NAND3X2 +XI1<2> NADR<0> PADR<1> NADR<2> addr_n<2> VDD VSS / RSC_IHPSG13_NAND3X2 +XI1<1> PADR<0> NADR<1> NADR<2> addr_n<1> VDD VSS / RSC_IHPSG13_NAND3X2 +XI1<0> NADR<0> NADR<1> NADR<2> addr_n<0> VDD VSS / RSC_IHPSG13_NAND3X2 +XDFF<4> BIST_EN_I BIST_ADDR<4> ACLK_N ADDR<4> addr_int<1> net13<0> VDD ++ VSS / RSC_IHPSG13_DFNQMX2IX1 +XDFF<3> BIST_EN_I BIST_ADDR<3> ACLK_N ADDR<3> addr_int<0> net13<1> VDD ++ VSS / RSC_IHPSG13_DFNQMX2IX1 +XDFF<2> BIST_EN_I BIST_ADDR<2> ACLK_N ADDR<2> padr_int<2> net13<2> VDD ++ VSS / RSC_IHPSG13_DFNQMX2IX1 +XDFF<1> BIST_EN_I BIST_ADDR<1> ACLK_N ADDR<1> padr_int<1> net13<3> VDD ++ VSS / RSC_IHPSG13_DFNQMX2IX1 +XDFF<0> BIST_EN_I BIST_ADDR<0> ACLK_N ADDR<0> padr_int<0> net13<4> VDD ++ VSS / RSC_IHPSG13_DFNQMX2IX1 +XI3<2> padr_int<2> NADR<2> VDD VSS / RSC_IHPSG13_INVX2 +XI3<1> padr_int<1> NADR<1> VDD VSS / RSC_IHPSG13_INVX2 +XI3<0> padr_int<0> NADR<0> VDD VSS / RSC_IHPSG13_INVX2 +XI2<7> addr_n<7> ADDR_DEC<7> VDD VSS / RSC_IHPSG13_INVX2 +XI2<6> addr_n<6> ADDR_DEC<6> VDD VSS / RSC_IHPSG13_INVX2 +XI2<5> addr_n<5> ADDR_DEC<5> VDD VSS / RSC_IHPSG13_INVX2 +XI2<4> addr_n<4> ADDR_DEC<4> VDD VSS / RSC_IHPSG13_INVX2 +XI2<3> addr_n<3> ADDR_DEC<3> VDD VSS / RSC_IHPSG13_INVX2 +XI2<2> addr_n<2> ADDR_DEC<2> VDD VSS / RSC_IHPSG13_INVX2 +XI2<1> addr_n<1> ADDR_DEC<1> VDD VSS / RSC_IHPSG13_INVX2 +XI2<0> addr_n<0> ADDR_DEC<0> VDD VSS / RSC_IHPSG13_INVX2 +XI15<2> NADR<2> PADR<2> VDD VSS / RSC_IHPSG13_INVX2 +XI15<1> NADR<1> PADR<1> VDD VSS / RSC_IHPSG13_INVX2 +XI15<0> NADR<0> PADR<0> VDD VSS / RSC_IHPSG13_INVX2 +XI13<1> addr_int<1> ADDR_COL<1> VDD VSS / RSC_IHPSG13_CBUFX2 +XI13<0> addr_int<0> ADDR_COL<0> VDD VSS / RSC_IHPSG13_CBUFX2 +XI14<5> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI14<4> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI14<3> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI14<2> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI14<1> VDD VSS / RSC_IHPSG13_FILLCAP8 +.ENDS +.SUBCKT RM_IHPSG13_256x16_c2_2P_BLDRV A_BLC<3> A_BLC<2> A_BLC<1> A_BLC<0> A_BLC_SEL ++ A_BLT<3> A_BLT<2> A_BLT<1> A_BLT<0> A_BLT_SEL A_PRE_N A_SEL_P<3> A_SEL_P<2> ++ A_SEL_P<1> A_SEL_P<0> A_WR_ONE A_WR_ZERO B_BLC<3> B_BLC<2> B_BLC<1> B_BLC<0> ++ B_BLC_SEL B_BLT<3> B_BLT<2> B_BLT<1> B_BLT<0> B_BLT_SEL B_PRE_N B_SEL_P<3> ++ B_SEL_P<2> B_SEL_P<1> B_SEL_P<0> B_WR_ONE B_WR_ZERO VDD VSS +MA_CWN<3> A_BLC<3> A_BLC_NMOS_DRIVE<3> VSS VSS sg13_lv_nmos m=1 ++ w=4.82u l=130.00n ng=2 nrd=0 nrs=0 +MA_CWN<2> A_BLC<2> A_BLC_NMOS_DRIVE<2> VSS VSS sg13_lv_nmos m=1 ++ w=4.82u l=130.00n ng=2 nrd=0 nrs=0 +MA_CWN<1> A_BLC<1> A_BLC_NMOS_DRIVE<1> VSS VSS sg13_lv_nmos m=1 ++ w=4.82u l=130.00n ng=2 nrd=0 nrs=0 +MA_CWN<0> A_BLC<0> A_BLC_NMOS_DRIVE<0> VSS VSS sg13_lv_nmos m=1 ++ w=4.82u l=130.00n ng=2 nrd=0 nrs=0 +MA_TWN<3> A_BLT<3> A_BLT_NMOS_DRIVE<3> VSS VSS sg13_lv_nmos m=1 ++ w=4.82u l=130.00n ng=2 nrd=0 nrs=0 +MA_TWN<2> A_BLT<2> A_BLT_NMOS_DRIVE<2> VSS VSS sg13_lv_nmos m=1 ++ w=4.82u l=130.00n ng=2 nrd=0 nrs=0 +MA_TWN<1> A_BLT<1> A_BLT_NMOS_DRIVE<1> VSS VSS sg13_lv_nmos m=1 ++ w=4.82u l=130.00n ng=2 nrd=0 nrs=0 +MA_TWN<0> A_BLT<0> A_BLT_NMOS_DRIVE<0> VSS VSS sg13_lv_nmos m=1 ++ w=4.82u l=130.00n ng=2 nrd=0 nrs=0 +MB_TWN<3> B_BLT<3> B_BLT_NMOS_DRIVE<3> VSS VSS sg13_lv_nmos m=1 ++ w=4.82u l=130.00n ng=2 nrd=0 nrs=0 +MB_TWN<2> B_BLT<2> B_BLT_NMOS_DRIVE<2> VSS VSS sg13_lv_nmos m=1 ++ w=4.82u l=130.00n ng=2 nrd=0 nrs=0 +MB_TWN<1> B_BLT<1> B_BLT_NMOS_DRIVE<1> VSS VSS sg13_lv_nmos m=1 ++ w=4.82u l=130.00n ng=2 nrd=0 nrs=0 +MB_TWN<0> B_BLT<0> B_BLT_NMOS_DRIVE<0> VSS VSS sg13_lv_nmos m=1 ++ w=4.82u l=130.00n ng=2 nrd=0 nrs=0 +MB_CWN<3> B_BLC<3> B_BLC_NMOS_DRIVE<3> VSS VSS sg13_lv_nmos m=1 ++ w=4.82u l=130.00n ng=2 nrd=0 nrs=0 +MB_CWN<2> B_BLC<2> B_BLC_NMOS_DRIVE<2> VSS VSS sg13_lv_nmos m=1 ++ w=4.82u l=130.00n ng=2 nrd=0 nrs=0 +MB_CWN<1> B_BLC<1> B_BLC_NMOS_DRIVE<1> VSS VSS sg13_lv_nmos m=1 ++ w=4.82u l=130.00n ng=2 nrd=0 nrs=0 +MB_CWN<0> B_BLC<0> B_BLC_NMOS_DRIVE<0> VSS VSS sg13_lv_nmos m=1 ++ w=4.82u l=130.00n ng=2 nrd=0 nrs=0 +MA_CPR<3> A_BLC<3> A_PRE_N VDD VDD sg13_lv_pmos m=1 w=3.000u l=130.00n ++ ng=2 nrd=0 nrs=0 +MA_CPR<2> A_BLC<2> A_PRE_N VDD VDD sg13_lv_pmos m=1 w=3.000u l=130.00n ++ ng=2 nrd=0 nrs=0 +MA_CPR<1> A_BLC<1> A_PRE_N VDD VDD sg13_lv_pmos m=1 w=3.000u l=130.00n ++ ng=2 nrd=0 nrs=0 +MA_CPR<0> A_BLC<0> A_PRE_N VDD VDD sg13_lv_pmos m=1 w=3.000u l=130.00n ++ ng=2 nrd=0 nrs=0 +MA_TWP<3> A_BLT<3> A_BLT_PMOS_DRIVE<3> VDD VDD sg13_lv_pmos m=1 w=1.5u ++ l=130.00n ng=1 nrd=0 nrs=0 +MA_TWP<2> A_BLT<2> A_BLT_PMOS_DRIVE<2> VDD VDD sg13_lv_pmos m=1 w=1.5u ++ l=130.00n ng=1 nrd=0 nrs=0 +MA_TWP<1> A_BLT<1> A_BLT_PMOS_DRIVE<1> VDD VDD sg13_lv_pmos m=1 w=1.5u ++ l=130.00n ng=1 nrd=0 nrs=0 +MA_TWP<0> A_BLT<0> A_BLT_PMOS_DRIVE<0> VDD VDD sg13_lv_pmos m=1 w=1.5u ++ l=130.00n ng=1 nrd=0 nrs=0 +MA_CWP<3> A_BLC<3> A_BLC_PMOS_DRIVE<3> VDD VDD sg13_lv_pmos m=1 w=1.5u ++ l=130.00n ng=1 nrd=0 nrs=0 +MA_CWP<2> A_BLC<2> A_BLC_PMOS_DRIVE<2> VDD VDD sg13_lv_pmos m=1 w=1.5u ++ l=130.00n ng=1 nrd=0 nrs=0 +MA_CWP<1> A_BLC<1> A_BLC_PMOS_DRIVE<1> VDD VDD sg13_lv_pmos m=1 w=1.5u ++ l=130.00n ng=1 nrd=0 nrs=0 +MA_CWP<0> A_BLC<0> A_BLC_PMOS_DRIVE<0> VDD VDD sg13_lv_pmos m=1 w=1.5u ++ l=130.00n ng=1 nrd=0 nrs=0 +MA_TPR<3> A_BLT<3> A_PRE_N VDD VDD sg13_lv_pmos m=1 w=3.000u l=130.00n ++ ng=2 nrd=0 nrs=0 +MA_TPR<2> A_BLT<2> A_PRE_N VDD VDD sg13_lv_pmos m=1 w=3.000u l=130.00n ++ ng=2 nrd=0 nrs=0 +MA_TPR<1> A_BLT<1> A_PRE_N VDD VDD sg13_lv_pmos m=1 w=3.000u l=130.00n ++ ng=2 nrd=0 nrs=0 +MA_TPR<0> A_BLT<0> A_PRE_N VDD VDD sg13_lv_pmos m=1 w=3.000u l=130.00n ++ ng=2 nrd=0 nrs=0 +MA_TSP<3> A_BLT_SEL A_SEL_N<3> A_BLT<3> VDD sg13_lv_pmos m=1 w=1.5u ++ l=130.00n ng=1 nrd=0 nrs=0 +MA_TSP<2> A_BLT_SEL A_SEL_N<2> A_BLT<2> VDD sg13_lv_pmos m=1 w=1.5u ++ l=130.00n ng=1 nrd=0 nrs=0 +MA_TSP<1> A_BLT_SEL A_SEL_N<1> A_BLT<1> VDD sg13_lv_pmos m=1 w=1.5u ++ l=130.00n ng=1 nrd=0 nrs=0 +MA_TSP<0> A_BLT_SEL A_SEL_N<0> A_BLT<0> VDD sg13_lv_pmos m=1 w=1.5u ++ l=130.00n ng=1 nrd=0 nrs=0 +MA_CSP<3> A_BLC_SEL A_SEL_N<3> A_BLC<3> VDD sg13_lv_pmos m=1 w=1.5u ++ l=130.00n ng=1 nrd=0 nrs=0 +MA_CSP<2> A_BLC_SEL A_SEL_N<2> A_BLC<2> VDD sg13_lv_pmos m=1 w=1.5u ++ l=130.00n ng=1 nrd=0 nrs=0 +MA_CSP<1> A_BLC_SEL A_SEL_N<1> A_BLC<1> VDD sg13_lv_pmos m=1 w=1.5u ++ l=130.00n ng=1 nrd=0 nrs=0 +MA_CSP<0> A_BLC_SEL A_SEL_N<0> A_BLC<0> VDD sg13_lv_pmos m=1 w=1.5u ++ l=130.00n ng=1 nrd=0 nrs=0 +MB_CWP<3> B_BLC<3> B_BLC_PMOS_DRIVE<3> VDD VDD sg13_lv_pmos m=1 w=1.5u ++ l=130.00n ng=1 nrd=0 nrs=0 +MB_CWP<2> B_BLC<2> B_BLC_PMOS_DRIVE<2> VDD VDD sg13_lv_pmos m=1 w=1.5u ++ l=130.00n ng=1 nrd=0 nrs=0 +MB_CWP<1> B_BLC<1> B_BLC_PMOS_DRIVE<1> VDD VDD sg13_lv_pmos m=1 w=1.5u ++ l=130.00n ng=1 nrd=0 nrs=0 +MB_CWP<0> B_BLC<0> B_BLC_PMOS_DRIVE<0> VDD VDD sg13_lv_pmos m=1 w=1.5u ++ l=130.00n ng=1 nrd=0 nrs=0 +MB_TWP<3> B_BLT<3> B_BLT_PMOS_DRIVE<3> VDD VDD sg13_lv_pmos m=1 w=1.5u ++ l=130.00n ng=1 nrd=0 nrs=0 +MB_TWP<2> B_BLT<2> B_BLT_PMOS_DRIVE<2> VDD VDD sg13_lv_pmos m=1 w=1.5u ++ l=130.00n ng=1 nrd=0 nrs=0 +MB_TWP<1> B_BLT<1> B_BLT_PMOS_DRIVE<1> VDD VDD sg13_lv_pmos m=1 w=1.5u ++ l=130.00n ng=1 nrd=0 nrs=0 +MB_TWP<0> B_BLT<0> B_BLT_PMOS_DRIVE<0> VDD VDD sg13_lv_pmos m=1 w=1.5u ++ l=130.00n ng=1 nrd=0 nrs=0 +MB_TSP<3> B_BLT_SEL B_SEL_N<3> B_BLT<3> VDD sg13_lv_pmos m=1 w=1.5u ++ l=130.00n ng=1 nrd=0 nrs=0 +MB_TSP<2> B_BLT_SEL B_SEL_N<2> B_BLT<2> VDD sg13_lv_pmos m=1 w=1.5u ++ l=130.00n ng=1 nrd=0 nrs=0 +MB_TSP<1> B_BLT_SEL B_SEL_N<1> B_BLT<1> VDD sg13_lv_pmos m=1 w=1.5u ++ l=130.00n ng=1 nrd=0 nrs=0 +MB_TSP<0> B_BLT_SEL B_SEL_N<0> B_BLT<0> VDD sg13_lv_pmos m=1 w=1.5u ++ l=130.00n ng=1 nrd=0 nrs=0 +MB_TPR<3> B_BLT<3> B_PRE_N VDD VDD sg13_lv_pmos m=1 w=3.000u l=130.00n ++ ng=2 nrd=0 nrs=0 +MB_TPR<2> B_BLT<2> B_PRE_N VDD VDD sg13_lv_pmos m=1 w=3.000u l=130.00n ++ ng=2 nrd=0 nrs=0 +MB_TPR<1> B_BLT<1> B_PRE_N VDD VDD sg13_lv_pmos m=1 w=3.000u l=130.00n ++ ng=2 nrd=0 nrs=0 +MB_TPR<0> B_BLT<0> B_PRE_N VDD VDD sg13_lv_pmos m=1 w=3.000u l=130.00n ++ ng=2 nrd=0 nrs=0 +MB_CSP<3> B_BLC_SEL B_SEL_N<3> B_BLC<3> VDD sg13_lv_pmos m=1 w=1.5u ++ l=130.00n ng=1 nrd=0 nrs=0 +MB_CSP<2> B_BLC_SEL B_SEL_N<2> B_BLC<2> VDD sg13_lv_pmos m=1 w=1.5u ++ l=130.00n ng=1 nrd=0 nrs=0 +MB_CSP<1> B_BLC_SEL B_SEL_N<1> B_BLC<1> VDD sg13_lv_pmos m=1 w=1.5u ++ l=130.00n ng=1 nrd=0 nrs=0 +MB_CSP<0> B_BLC_SEL B_SEL_N<0> B_BLC<0> VDD sg13_lv_pmos m=1 w=1.5u ++ l=130.00n ng=1 nrd=0 nrs=0 +MB_CPR<3> B_BLC<3> B_PRE_N VDD VDD sg13_lv_pmos m=1 w=3.000u l=130.00n ++ ng=2 nrd=0 nrs=0 +MB_CPR<2> B_BLC<2> B_PRE_N VDD VDD sg13_lv_pmos m=1 w=3.000u l=130.00n ++ ng=2 nrd=0 nrs=0 +MB_CPR<1> B_BLC<1> B_PRE_N VDD VDD sg13_lv_pmos m=1 w=3.000u l=130.00n ++ ng=2 nrd=0 nrs=0 +MB_CPR<0> B_BLC<0> B_PRE_N VDD VDD sg13_lv_pmos m=1 w=3.000u l=130.00n ++ ng=2 nrd=0 nrs=0 +XA_SEL<3> A_SEL_P<3> A_SEL_N<3> VDD VSS / RSC_IHPSG13_INVX2 +XA_SEL<2> A_SEL_P<2> A_SEL_N<2> VDD VSS / RSC_IHPSG13_INVX2 +XA_SEL<1> A_SEL_P<1> A_SEL_N<1> VDD VSS / RSC_IHPSG13_INVX2 +XA_SEL<0> A_SEL_P<0> A_SEL_N<0> VDD VSS / RSC_IHPSG13_INVX2 +XA_CINV<3> A_BLT_PMOS_DRIVE<3> A_BLC_NMOS_DRIVE<3> VDD VSS / ++ RSC_IHPSG13_INVX2 +XA_CINV<2> A_BLT_PMOS_DRIVE<2> A_BLC_NMOS_DRIVE<2> VDD VSS / ++ RSC_IHPSG13_INVX2 +XA_CINV<1> A_BLT_PMOS_DRIVE<1> A_BLC_NMOS_DRIVE<1> VDD VSS / ++ RSC_IHPSG13_INVX2 +XA_CINV<0> A_BLT_PMOS_DRIVE<0> A_BLC_NMOS_DRIVE<0> VDD VSS / ++ RSC_IHPSG13_INVX2 +XA_TINV<3> A_BLC_PMOS_DRIVE<3> A_BLT_NMOS_DRIVE<3> VDD VSS / ++ RSC_IHPSG13_INVX2 +XA_TINV<2> A_BLC_PMOS_DRIVE<2> A_BLT_NMOS_DRIVE<2> VDD VSS / ++ RSC_IHPSG13_INVX2 +XA_TINV<1> A_BLC_PMOS_DRIVE<1> A_BLT_NMOS_DRIVE<1> VDD VSS / ++ RSC_IHPSG13_INVX2 +XA_TINV<0> A_BLC_PMOS_DRIVE<0> A_BLT_NMOS_DRIVE<0> VDD VSS / ++ RSC_IHPSG13_INVX2 +XB_SEL<3> B_SEL_P<3> B_SEL_N<3> VDD VSS / RSC_IHPSG13_INVX2 +XB_SEL<2> B_SEL_P<2> B_SEL_N<2> VDD VSS / RSC_IHPSG13_INVX2 +XB_SEL<1> B_SEL_P<1> B_SEL_N<1> VDD VSS / RSC_IHPSG13_INVX2 +XB_SEL<0> B_SEL_P<0> B_SEL_N<0> VDD VSS / RSC_IHPSG13_INVX2 +XB_TINV<3> B_BLC_PMOS_DRIVE<3> B_BLT_NMOS_DRIVE<3> VDD VSS / ++ RSC_IHPSG13_INVX2 +XB_TINV<2> B_BLC_PMOS_DRIVE<2> B_BLT_NMOS_DRIVE<2> VDD VSS / ++ RSC_IHPSG13_INVX2 +XB_TINV<1> B_BLC_PMOS_DRIVE<1> B_BLT_NMOS_DRIVE<1> VDD VSS / ++ RSC_IHPSG13_INVX2 +XB_TINV<0> B_BLC_PMOS_DRIVE<0> B_BLT_NMOS_DRIVE<0> VDD VSS / ++ RSC_IHPSG13_INVX2 +XB_CINV<3> B_BLT_PMOS_DRIVE<3> B_BLC_NMOS_DRIVE<3> VDD VSS / ++ RSC_IHPSG13_INVX2 +XB_CINV<2> B_BLT_PMOS_DRIVE<2> B_BLC_NMOS_DRIVE<2> VDD VSS / ++ RSC_IHPSG13_INVX2 +XB_CINV<1> B_BLT_PMOS_DRIVE<1> B_BLC_NMOS_DRIVE<1> VDD VSS / ++ RSC_IHPSG13_INVX2 +XB_CINV<0> B_BLT_PMOS_DRIVE<0> B_BLC_NMOS_DRIVE<0> VDD VSS / ++ RSC_IHPSG13_INVX2 +XA_TDEC<3> A_SEL_P<3> A_WR_ONE A_BLT_PMOS_DRIVE<3> VDD VSS / ++ RSC_IHPSG13_NAND2X2 +XA_TDEC<2> A_SEL_P<2> A_WR_ONE A_BLT_PMOS_DRIVE<2> VDD VSS / ++ RSC_IHPSG13_NAND2X2 +XA_TDEC<1> A_SEL_P<1> A_WR_ONE A_BLT_PMOS_DRIVE<1> VDD VSS / ++ RSC_IHPSG13_NAND2X2 +XA_TDEC<0> A_SEL_P<0> A_WR_ONE A_BLT_PMOS_DRIVE<0> VDD VSS / ++ RSC_IHPSG13_NAND2X2 +XA_CDEC<3> A_SEL_P<3> A_WR_ZERO A_BLC_PMOS_DRIVE<3> VDD VSS / ++ RSC_IHPSG13_NAND2X2 +XA_CDEC<2> A_SEL_P<2> A_WR_ZERO A_BLC_PMOS_DRIVE<2> VDD VSS / ++ RSC_IHPSG13_NAND2X2 +XA_CDEC<1> A_SEL_P<1> A_WR_ZERO A_BLC_PMOS_DRIVE<1> VDD VSS / ++ RSC_IHPSG13_NAND2X2 +XA_CDEC<0> A_SEL_P<0> A_WR_ZERO A_BLC_PMOS_DRIVE<0> VDD VSS / ++ RSC_IHPSG13_NAND2X2 +XB_CDEC<3> B_SEL_P<3> B_WR_ZERO B_BLC_PMOS_DRIVE<3> VDD VSS / ++ RSC_IHPSG13_NAND2X2 +XB_CDEC<2> B_SEL_P<2> B_WR_ZERO B_BLC_PMOS_DRIVE<2> VDD VSS / ++ RSC_IHPSG13_NAND2X2 +XB_CDEC<1> B_SEL_P<1> B_WR_ZERO B_BLC_PMOS_DRIVE<1> VDD VSS / ++ RSC_IHPSG13_NAND2X2 +XB_CDEC<0> B_SEL_P<0> B_WR_ZERO B_BLC_PMOS_DRIVE<0> VDD VSS / ++ RSC_IHPSG13_NAND2X2 +XB_TDEC<3> B_SEL_P<3> B_WR_ONE B_BLT_PMOS_DRIVE<3> VDD VSS / ++ RSC_IHPSG13_NAND2X2 +XB_TDEC<2> B_SEL_P<2> B_WR_ONE B_BLT_PMOS_DRIVE<2> VDD VSS / ++ RSC_IHPSG13_NAND2X2 +XB_TDEC<1> B_SEL_P<1> B_WR_ONE B_BLT_PMOS_DRIVE<1> VDD VSS / ++ RSC_IHPSG13_NAND2X2 +XB_TDEC<0> B_SEL_P<0> B_WR_ONE B_BLT_PMOS_DRIVE<0> VDD VSS / ++ RSC_IHPSG13_NAND2X2 +.ENDS +.SUBCKT RSC_IHPSG13_AND2X6 A B Z VDD VSS +MN3 Z net6 VSS VSS sg13_lv_nmos m=1 w=2.94u l=130.00n ng=3 nrd=0 nrs=0 +MN4 net9 B VSS VSS sg13_lv_nmos m=1 w=500.0n l=130.00n ng=1 nrd=0 nrs=0 +MN6 net6 A net9 VSS sg13_lv_nmos m=1 w=500.0n l=130.00n ng=1 nrd=0 nrs=0 +MP2 Z net6 VDD VDD sg13_lv_pmos m=1 w=4.86u l=130.00n ng=3 nrd=0 nrs=0 +MP0 net6 B VDD VDD sg13_lv_pmos m=1 w=860.00n l=130.00n ng=1 nrd=0 ++ nrs=0 +MP1 net6 A VDD VDD sg13_lv_pmos m=1 w=860.00n l=130.00n ng=1 nrd=0 ++ nrs=0 +.ENDS +.SUBCKT RM_IHPSG13_256x16_c2_2P_COLCTRL5 A_ADDR_COL<1> A_ADDR_COL<0> A_ADDR_DEC<7> ++ A_ADDR_DEC<6> A_ADDR_DEC<5> A_ADDR_DEC<4> A_ADDR_DEC<3> A_ADDR_DEC<2> ++ A_ADDR_DEC<1> A_ADDR_DEC<0> A_BIST_BM_I A_BIST_DW_I A_BIST_EN_I A_BLC<31> ++ A_BLC<30> A_BLC<29> A_BLC<28> A_BLC<27> A_BLC<26> A_BLC<25> A_BLC<24> ++ A_BLC<23> A_BLC<22> A_BLC<21> A_BLC<20> A_BLC<19> A_BLC<18> A_BLC<17> ++ A_BLC<16> A_BLC<15> A_BLC<14> A_BLC<13> A_BLC<12> A_BLC<11> A_BLC<10> ++ A_BLC<9> A_BLC<8> A_BLC<7> A_BLC<6> A_BLC<5> A_BLC<4> A_BLC<3> A_BLC<2> ++ A_BLC<1> A_BLC<0> A_BLT<31> A_BLT<30> A_BLT<29> A_BLT<28> A_BLT<27> ++ A_BLT<26> A_BLT<25> A_BLT<24> A_BLT<23> A_BLT<22> A_BLT<21> A_BLT<20> ++ A_BLT<19> A_BLT<18> A_BLT<17> A_BLT<16> A_BLT<15> A_BLT<14> A_BLT<13> ++ A_BLT<12> A_BLT<11> A_BLT<10> A_BLT<9> A_BLT<8> A_BLT<7> A_BLT<6> A_BLT<5> ++ A_BLT<4> A_BLT<3> A_BLT<2> A_BLT<1> A_BLT<0> A_BM_I A_DCLK_B_L A_DCLK_B_R ++ A_DCLK_L A_DCLK_R A_DR_O A_DW_I A_RCLK_B_L A_RCLK_B_R A_RCLK_L A_RCLK_R ++ A_TIEH_O A_WCLK_B_L A_WCLK_B_R A_WCLK_L A_WCLK_R B_ADDR_COL<1> B_ADDR_COL<0> ++ B_ADDR_DEC<7> B_ADDR_DEC<6> B_ADDR_DEC<5> B_ADDR_DEC<4> B_ADDR_DEC<3> ++ B_ADDR_DEC<2> B_ADDR_DEC<1> B_ADDR_DEC<0> B_BIST_BM_I B_BIST_DW_I ++ B_BIST_EN_I B_BLC<31> B_BLC<30> B_BLC<29> B_BLC<28> B_BLC<27> B_BLC<26> ++ B_BLC<25> B_BLC<24> B_BLC<23> B_BLC<22> B_BLC<21> B_BLC<20> B_BLC<19> ++ B_BLC<18> B_BLC<17> B_BLC<16> B_BLC<15> B_BLC<14> B_BLC<13> B_BLC<12> ++ B_BLC<11> B_BLC<10> B_BLC<9> B_BLC<8> B_BLC<7> B_BLC<6> B_BLC<5> B_BLC<4> ++ B_BLC<3> B_BLC<2> B_BLC<1> B_BLC<0> B_BLT<31> B_BLT<30> B_BLT<29> B_BLT<28> ++ B_BLT<27> B_BLT<26> B_BLT<25> B_BLT<24> B_BLT<23> B_BLT<22> B_BLT<21> ++ B_BLT<20> B_BLT<19> B_BLT<18> B_BLT<17> B_BLT<16> B_BLT<15> B_BLT<14> ++ B_BLT<13> B_BLT<12> B_BLT<11> B_BLT<10> B_BLT<9> B_BLT<8> B_BLT<7> B_BLT<6> ++ B_BLT<5> B_BLT<4> B_BLT<3> B_BLT<2> B_BLT<1> B_BLT<0> B_BM_I B_DCLK_B_L ++ B_DCLK_B_R B_DCLK_L B_DCLK_R B_DR_O B_DW_I B_RCLK_B_L B_RCLK_B_R B_RCLK_L ++ B_RCLK_R B_TIEH_O B_WCLK_B_L B_WCLK_B_R B_WCLK_L B_WCLK_R VDD VSS +XB_I80<1> B_WCLK_B_L B_RCLK_B_L B_W_nor_R<1> VDD VSS / ++ RSC_IHPSG13_AND2X2 +XB_I80<0> B_WCLK_B_L B_RCLK_B_L B_W_nor_R<0> VDD VSS / ++ RSC_IHPSG13_AND2X2 +XA_I80<1> A_WCLK_B_L A_RCLK_B_L A_W_nor_R<1> VDD VSS / ++ RSC_IHPSG13_AND2X2 +XA_I80<0> A_WCLK_B_L A_RCLK_B_L A_W_nor_R<0> VDD VSS / ++ RSC_IHPSG13_AND2X2 +XB_I44 B_BM_N B_WCLK_B_L B_DO_WRITE_P VDD VSS / RSC_IHPSG13_NOR2X2 +XA_I44 A_BM_N A_WCLK_B_L A_DO_WRITE_P VDD VSS / RSC_IHPSG13_NOR2X2 +XI_FILL4<16> VDD VSS / RSC_IHPSG13_FILLCAP4 +XI_FILL4<15> VDD VSS / RSC_IHPSG13_FILLCAP4 +XI_FILL4<14> VDD VSS / RSC_IHPSG13_FILLCAP4 +XI_FILL4<13> VDD VSS / RSC_IHPSG13_FILLCAP4 +XI_FILL4<12> VDD VSS / RSC_IHPSG13_FILLCAP4 +XI_FILL4<11> VDD VSS / RSC_IHPSG13_FILLCAP4 +XI_FILL4<10> VDD VSS / RSC_IHPSG13_FILLCAP4 +XI_FILL4<9> VDD VSS / RSC_IHPSG13_FILLCAP4 +XI_FILL4<8> VDD VSS / RSC_IHPSG13_FILLCAP4 +XI_FILL4<7> VDD VSS / RSC_IHPSG13_FILLCAP4 +XI_FILL4<6> VDD VSS / RSC_IHPSG13_FILLCAP4 +XI_FILL4<5> VDD VSS / RSC_IHPSG13_FILLCAP4 +XI_FILL4<4> VDD VSS / RSC_IHPSG13_FILLCAP4 +XI_FILL4<3> VDD VSS / RSC_IHPSG13_FILLCAP4 +XI_FILL4<2> VDD VSS / RSC_IHPSG13_FILLCAP4 +XI_FILL4<1> VDD VSS / RSC_IHPSG13_FILLCAP4 +XB_INV<6> B_N1<1> B_P1<1> VDD VSS / RSC_IHPSG13_CINVX4 +XB_INV<5> B_N0<1> B_P0<1> VDD VSS / RSC_IHPSG13_CINVX4 +XB_INV<4> B_N0<0> B_P0<0> VDD VSS / RSC_IHPSG13_CINVX4 +XB_INV<3> B_ADDR_COL<1> B_N1<1> VDD VSS / RSC_IHPSG13_CINVX4 +XB_INV<2> B_ADDR_COL<1> B_N1<0> VDD VSS / RSC_IHPSG13_CINVX4 +XB_INV<1> B_ADDR_COL<0> B_N0<1> VDD VSS / RSC_IHPSG13_CINVX4 +XB_INV<0> B_ADDR_COL<0> B_N0<0> VDD VSS / RSC_IHPSG13_CINVX4 +XA_INV<6> A_N1<1> A_P1<1> VDD VSS / RSC_IHPSG13_CINVX4 +XA_INV<5> A_N0<1> A_P0<1> VDD VSS / RSC_IHPSG13_CINVX4 +XA_INV<4> A_N0<0> A_P0<0> VDD VSS / RSC_IHPSG13_CINVX4 +XA_INV<3> A_ADDR_COL<1> A_N1<1> VDD VSS / RSC_IHPSG13_CINVX4 +XA_INV<2> A_ADDR_COL<1> A_N1<0> VDD VSS / RSC_IHPSG13_CINVX4 +XA_INV<1> A_ADDR_COL<0> A_N0<1> VDD VSS / RSC_IHPSG13_CINVX4 +XA_INV<0> A_ADDR_COL<0> A_N0<0> VDD VSS / RSC_IHPSG13_CINVX4 +XB_I81<3> B_W_nor_R<1> B_PRE_N VDD VSS / RSC_IHPSG13_CINVX4_WN +XB_I81<2> B_W_nor_R<1> B_PRE_N VDD VSS / RSC_IHPSG13_CINVX4_WN +XB_I81<1> B_W_nor_R<0> B_PRE_N VDD VSS / RSC_IHPSG13_CINVX4_WN +XB_I81<0> B_W_nor_R<0> B_PRE_N VDD VSS / RSC_IHPSG13_CINVX4_WN +XA_I81<3> A_W_nor_R<1> A_PRE_N VDD VSS / RSC_IHPSG13_CINVX4_WN +XA_I81<2> A_W_nor_R<1> A_PRE_N VDD VSS / RSC_IHPSG13_CINVX4_WN +XA_I81<1> A_W_nor_R<0> A_PRE_N VDD VSS / RSC_IHPSG13_CINVX4_WN +XA_I81<0> A_W_nor_R<0> A_PRE_N VDD VSS / RSC_IHPSG13_CINVX4_WN +XI_FILL8<78> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI_FILL8<77> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI_FILL8<76> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI_FILL8<75> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI_FILL8<74> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI_FILL8<73> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI_FILL8<72> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI_FILL8<71> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI_FILL8<70> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI_FILL8<69> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI_FILL8<68> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI_FILL8<67> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI_FILL8<66> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI_FILL8<65> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI_FILL8<64> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI_FILL8<63> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI_FILL8<62> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI_FILL8<61> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI_FILL8<60> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI_FILL8<59> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI_FILL8<58> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI_FILL8<57> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI_FILL8<56> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI_FILL8<55> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI_FILL8<54> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI_FILL8<53> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI_FILL8<52> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI_FILL8<51> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI_FILL8<50> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI_FILL8<49> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI_FILL8<48> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI_FILL8<47> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI_FILL8<46> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI_FILL8<45> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI_FILL8<44> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI_FILL8<43> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI_FILL8<42> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI_FILL8<41> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI_FILL8<40> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI_FILL8<39> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI_FILL8<38> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI_FILL8<37> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI_FILL8<36> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI_FILL8<35> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI_FILL8<34> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI_FILL8<33> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI_FILL8<32> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI_FILL8<31> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI_FILL8<30> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI_FILL8<29> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI_FILL8<28> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI_FILL8<27> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI_FILL8<26> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI_FILL8<25> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI_FILL8<24> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI_FILL8<23> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI_FILL8<22> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI_FILL8<21> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI_FILL8<20> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI_FILL8<19> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI_FILL8<18> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI_FILL8<17> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI_FILL8<16> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI_FILL8<15> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI_FILL8<14> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI_FILL8<13> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI_FILL8<12> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI_FILL8<11> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI_FILL8<10> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI_FILL8<9> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI_FILL8<8> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI_FILL8<7> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI_FILL8<6> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI_FILL8<5> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI_FILL8<4> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI_FILL8<3> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI_FILL8<2> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI_FILL8<1> VDD VSS / RSC_IHPSG13_FILLCAP8 +XAB_BLMUX<7> A_BLC<31> A_BLC<30> A_BLC<29> A_BLC<28> A_BLC_SEL A_BLT<31> ++ A_BLT<30> A_BLT<29> A_BLT<28> A_BLT_SEL A_PRE_N A_SEL_P<31> A_SEL_P<30> ++ A_SEL_P<29> A_SEL_P<28> A_WR_ONE A_WR_ZERO B_BLC<31> B_BLC<30> B_BLC<29> ++ B_BLC<28> B_BLC_SEL B_BLT<31> B_BLT<30> B_BLT<29> B_BLT<28> B_BLT_SEL ++ B_PRE_N B_SEL_P<31> B_SEL_P<30> B_SEL_P<29> B_SEL_P<28> B_WR_ONE B_WR_ZERO ++ VDD VSS / RM_IHPSG13_256x16_c2_2P_BLDRV +XAB_BLMUX<6> A_BLC<27> A_BLC<26> A_BLC<25> A_BLC<24> A_BLC_SEL A_BLT<27> ++ A_BLT<26> A_BLT<25> A_BLT<24> A_BLT_SEL A_PRE_N A_SEL_P<27> A_SEL_P<26> ++ A_SEL_P<25> A_SEL_P<24> A_WR_ONE A_WR_ZERO B_BLC<27> B_BLC<26> B_BLC<25> ++ B_BLC<24> B_BLC_SEL B_BLT<27> B_BLT<26> B_BLT<25> B_BLT<24> B_BLT_SEL ++ B_PRE_N B_SEL_P<27> B_SEL_P<26> B_SEL_P<25> B_SEL_P<24> B_WR_ONE B_WR_ZERO ++ VDD VSS / RM_IHPSG13_256x16_c2_2P_BLDRV +XAB_BLMUX<5> A_BLC<23> A_BLC<22> A_BLC<21> A_BLC<20> A_BLC_SEL A_BLT<23> ++ A_BLT<22> A_BLT<21> A_BLT<20> A_BLT_SEL A_PRE_N A_SEL_P<23> A_SEL_P<22> ++ A_SEL_P<21> A_SEL_P<20> A_WR_ONE A_WR_ZERO B_BLC<23> B_BLC<22> B_BLC<21> ++ B_BLC<20> B_BLC_SEL B_BLT<23> B_BLT<22> B_BLT<21> B_BLT<20> B_BLT_SEL ++ B_PRE_N B_SEL_P<23> B_SEL_P<22> B_SEL_P<21> B_SEL_P<20> B_WR_ONE B_WR_ZERO ++ VDD VSS / RM_IHPSG13_256x16_c2_2P_BLDRV +XAB_BLMUX<4> A_BLC<19> A_BLC<18> A_BLC<17> A_BLC<16> A_BLC_SEL A_BLT<19> ++ A_BLT<18> A_BLT<17> A_BLT<16> A_BLT_SEL A_PRE_N A_SEL_P<19> A_SEL_P<18> ++ A_SEL_P<17> A_SEL_P<16> A_WR_ONE A_WR_ZERO B_BLC<19> B_BLC<18> B_BLC<17> ++ B_BLC<16> B_BLC_SEL B_BLT<19> B_BLT<18> B_BLT<17> B_BLT<16> B_BLT_SEL ++ B_PRE_N B_SEL_P<19> B_SEL_P<18> B_SEL_P<17> B_SEL_P<16> B_WR_ONE B_WR_ZERO ++ VDD VSS / RM_IHPSG13_256x16_c2_2P_BLDRV +XAB_BLMUX<3> A_BLC<15> A_BLC<14> A_BLC<13> A_BLC<12> A_BLC_SEL A_BLT<15> ++ A_BLT<14> A_BLT<13> A_BLT<12> A_BLT_SEL A_PRE_N A_SEL_P<15> A_SEL_P<14> ++ A_SEL_P<13> A_SEL_P<12> A_WR_ONE A_WR_ZERO B_BLC<15> B_BLC<14> B_BLC<13> ++ B_BLC<12> B_BLC_SEL B_BLT<15> B_BLT<14> B_BLT<13> B_BLT<12> B_BLT_SEL ++ B_PRE_N B_SEL_P<15> B_SEL_P<14> B_SEL_P<13> B_SEL_P<12> B_WR_ONE B_WR_ZERO ++ VDD VSS / RM_IHPSG13_256x16_c2_2P_BLDRV +XAB_BLMUX<2> A_BLC<11> A_BLC<10> A_BLC<9> A_BLC<8> A_BLC_SEL A_BLT<11> ++ A_BLT<10> A_BLT<9> A_BLT<8> A_BLT_SEL A_PRE_N A_SEL_P<11> A_SEL_P<10> ++ A_SEL_P<9> A_SEL_P<8> A_WR_ONE A_WR_ZERO B_BLC<11> B_BLC<10> B_BLC<9> ++ B_BLC<8> B_BLC_SEL B_BLT<11> B_BLT<10> B_BLT<9> B_BLT<8> B_BLT_SEL B_PRE_N ++ B_SEL_P<11> B_SEL_P<10> B_SEL_P<9> B_SEL_P<8> B_WR_ONE B_WR_ZERO VDD ++ VSS / RM_IHPSG13_256x16_c2_2P_BLDRV +XAB_BLMUX<1> A_BLC<7> A_BLC<6> A_BLC<5> A_BLC<4> A_BLC_SEL A_BLT<7> A_BLT<6> ++ A_BLT<5> A_BLT<4> A_BLT_SEL A_PRE_N A_SEL_P<7> A_SEL_P<6> A_SEL_P<5> ++ A_SEL_P<4> A_WR_ONE A_WR_ZERO B_BLC<7> B_BLC<6> B_BLC<5> B_BLC<4> B_BLC_SEL ++ B_BLT<7> B_BLT<6> B_BLT<5> B_BLT<4> B_BLT_SEL B_PRE_N B_SEL_P<7> B_SEL_P<6> ++ B_SEL_P<5> B_SEL_P<4> B_WR_ONE B_WR_ZERO VDD VSS / ++ RM_IHPSG13_256x16_c2_2P_BLDRV +XAB_BLMUX<0> A_BLC<3> A_BLC<2> A_BLC<1> A_BLC<0> A_BLC_SEL A_BLT<3> A_BLT<2> ++ A_BLT<1> A_BLT<0> A_BLT_SEL A_PRE_N A_SEL_P<3> A_SEL_P<2> A_SEL_P<1> ++ A_SEL_P<0> A_WR_ONE A_WR_ZERO B_BLC<3> B_BLC<2> B_BLC<1> B_BLC<0> B_BLC_SEL ++ B_BLT<3> B_BLT<2> B_BLT<1> B_BLT<0> B_BLT_SEL B_PRE_N B_SEL_P<3> B_SEL_P<2> ++ B_SEL_P<1> B_SEL_P<0> B_WR_ONE B_WR_ZERO VDD VSS / ++ RM_IHPSG13_256x16_c2_2P_BLDRV +XB_I51 net037 B_DR_O VDD VSS / RSC_IHPSG13_INVX4 +XA_I51 net19 A_DR_O VDD VSS / RSC_IHPSG13_INVX4 +XB_I78 B_RCLK_B_L B_SAE VDD VSS / RSC_IHPSG13_CBUFX2 +XA_I78 A_RCLK_B_L A_SAE VDD VSS / RSC_IHPSG13_CBUFX2 +XB_I69 B_DCLK_L B_DCLK_B_L VDD VSS / RSC_IHPSG13_CINVX8 +XB_I50 B_WCLK_L B_WCLK_B_L VDD VSS / RSC_IHPSG13_CINVX8 +XB_EBUF B_RCLK_L B_RCLK_B_L VDD VSS / RSC_IHPSG13_CINVX8 +XA_I69 A_DCLK_L A_DCLK_B_L VDD VSS / RSC_IHPSG13_CINVX8 +XA_I50 A_WCLK_L A_WCLK_B_L VDD VSS / RSC_IHPSG13_CINVX8 +XA_EBUF A_RCLK_L A_RCLK_B_L VDD VSS / RSC_IHPSG13_CINVX8 +XB_I76 B_DI_N B_DO_WRITE_P B_WR_ZERO VDD VSS / RSC_IHPSG13_AND2X6 +XB_I75 B_DI_R B_DO_WRITE_P B_WR_ONE VDD VSS / RSC_IHPSG13_AND2X6 +XA_I76 A_DI_N A_DO_WRITE_P A_WR_ZERO VDD VSS / RSC_IHPSG13_AND2X6 +XA_I75 A_DI_R A_DO_WRITE_P A_WR_ONE VDD VSS / RSC_IHPSG13_AND2X6 +XB_I83 B_BM_R B_BM_N VDD VSS / RSC_IHPSG13_INVX2 +XB_DEC3INV<31> net041<0> B_SEL_P<31> VDD VSS / RSC_IHPSG13_INVX2 +XB_DEC3INV<30> net041<1> B_SEL_P<30> VDD VSS / RSC_IHPSG13_INVX2 +XB_DEC3INV<29> net041<2> B_SEL_P<29> VDD VSS / RSC_IHPSG13_INVX2 +XB_DEC3INV<28> net041<3> B_SEL_P<28> VDD VSS / RSC_IHPSG13_INVX2 +XB_DEC3INV<27> net041<4> B_SEL_P<27> VDD VSS / RSC_IHPSG13_INVX2 +XB_DEC3INV<26> net041<5> B_SEL_P<26> VDD VSS / RSC_IHPSG13_INVX2 +XB_DEC3INV<25> net041<6> B_SEL_P<25> VDD VSS / RSC_IHPSG13_INVX2 +XB_DEC3INV<24> net041<7> B_SEL_P<24> VDD VSS / RSC_IHPSG13_INVX2 +XB_DEC3INV<23> net041<8> B_SEL_P<23> VDD VSS / RSC_IHPSG13_INVX2 +XB_DEC3INV<22> net041<9> B_SEL_P<22> VDD VSS / RSC_IHPSG13_INVX2 +XB_DEC3INV<21> net041<10> B_SEL_P<21> VDD VSS / RSC_IHPSG13_INVX2 +XB_DEC3INV<20> net041<11> B_SEL_P<20> VDD VSS / RSC_IHPSG13_INVX2 +XB_DEC3INV<19> net041<12> B_SEL_P<19> VDD VSS / RSC_IHPSG13_INVX2 +XB_DEC3INV<18> net041<13> B_SEL_P<18> VDD VSS / RSC_IHPSG13_INVX2 +XB_DEC3INV<17> net041<14> B_SEL_P<17> VDD VSS / RSC_IHPSG13_INVX2 +XB_DEC3INV<16> net041<15> B_SEL_P<16> VDD VSS / RSC_IHPSG13_INVX2 +XB_DEC3INV<15> net041<16> B_SEL_P<15> VDD VSS / RSC_IHPSG13_INVX2 +XB_DEC3INV<14> net041<17> B_SEL_P<14> VDD VSS / RSC_IHPSG13_INVX2 +XB_DEC3INV<13> net041<18> B_SEL_P<13> VDD VSS / RSC_IHPSG13_INVX2 +XB_DEC3INV<12> net041<19> B_SEL_P<12> VDD VSS / RSC_IHPSG13_INVX2 +XB_DEC3INV<11> net041<20> B_SEL_P<11> VDD VSS / RSC_IHPSG13_INVX2 +XB_DEC3INV<10> net041<21> B_SEL_P<10> VDD VSS / RSC_IHPSG13_INVX2 +XB_DEC3INV<9> net041<22> B_SEL_P<9> VDD VSS / RSC_IHPSG13_INVX2 +XB_DEC3INV<8> net041<23> B_SEL_P<8> VDD VSS / RSC_IHPSG13_INVX2 +XB_DEC3INV<7> net041<24> B_SEL_P<7> VDD VSS / RSC_IHPSG13_INVX2 +XB_DEC3INV<6> net041<25> B_SEL_P<6> VDD VSS / RSC_IHPSG13_INVX2 +XB_DEC3INV<5> net041<26> B_SEL_P<5> VDD VSS / RSC_IHPSG13_INVX2 +XB_DEC3INV<4> net041<27> B_SEL_P<4> VDD VSS / RSC_IHPSG13_INVX2 +XB_DEC3INV<3> net041<28> B_SEL_P<3> VDD VSS / RSC_IHPSG13_INVX2 +XB_DEC3INV<2> net041<29> B_SEL_P<2> VDD VSS / RSC_IHPSG13_INVX2 +XB_DEC3INV<1> net041<30> B_SEL_P<1> VDD VSS / RSC_IHPSG13_INVX2 +XB_DEC3INV<0> net041<31> B_SEL_P<0> VDD VSS / RSC_IHPSG13_INVX2 +XB_I49 B_DI_R B_DI_N VDD VSS / RSC_IHPSG13_INVX2 +XA_I83 A_BM_R A_BM_N VDD VSS / RSC_IHPSG13_INVX2 +XA_DEC3INV<31> net23<0> A_SEL_P<31> VDD VSS / RSC_IHPSG13_INVX2 +XA_DEC3INV<30> net23<1> A_SEL_P<30> VDD VSS / RSC_IHPSG13_INVX2 +XA_DEC3INV<29> net23<2> A_SEL_P<29> VDD VSS / RSC_IHPSG13_INVX2 +XA_DEC3INV<28> net23<3> A_SEL_P<28> VDD VSS / RSC_IHPSG13_INVX2 +XA_DEC3INV<27> net23<4> A_SEL_P<27> VDD VSS / RSC_IHPSG13_INVX2 +XA_DEC3INV<26> net23<5> A_SEL_P<26> VDD VSS / RSC_IHPSG13_INVX2 +XA_DEC3INV<25> net23<6> A_SEL_P<25> VDD VSS / RSC_IHPSG13_INVX2 +XA_DEC3INV<24> net23<7> A_SEL_P<24> VDD VSS / RSC_IHPSG13_INVX2 +XA_DEC3INV<23> net23<8> A_SEL_P<23> VDD VSS / RSC_IHPSG13_INVX2 +XA_DEC3INV<22> net23<9> A_SEL_P<22> VDD VSS / RSC_IHPSG13_INVX2 +XA_DEC3INV<21> net23<10> A_SEL_P<21> VDD VSS / RSC_IHPSG13_INVX2 +XA_DEC3INV<20> net23<11> A_SEL_P<20> VDD VSS / RSC_IHPSG13_INVX2 +XA_DEC3INV<19> net23<12> A_SEL_P<19> VDD VSS / RSC_IHPSG13_INVX2 +XA_DEC3INV<18> net23<13> A_SEL_P<18> VDD VSS / RSC_IHPSG13_INVX2 +XA_DEC3INV<17> net23<14> A_SEL_P<17> VDD VSS / RSC_IHPSG13_INVX2 +XA_DEC3INV<16> net23<15> A_SEL_P<16> VDD VSS / RSC_IHPSG13_INVX2 +XA_DEC3INV<15> net23<16> A_SEL_P<15> VDD VSS / RSC_IHPSG13_INVX2 +XA_DEC3INV<14> net23<17> A_SEL_P<14> VDD VSS / RSC_IHPSG13_INVX2 +XA_DEC3INV<13> net23<18> A_SEL_P<13> VDD VSS / RSC_IHPSG13_INVX2 +XA_DEC3INV<12> net23<19> A_SEL_P<12> VDD VSS / RSC_IHPSG13_INVX2 +XA_DEC3INV<11> net23<20> A_SEL_P<11> VDD VSS / RSC_IHPSG13_INVX2 +XA_DEC3INV<10> net23<21> A_SEL_P<10> VDD VSS / RSC_IHPSG13_INVX2 +XA_DEC3INV<9> net23<22> A_SEL_P<9> VDD VSS / RSC_IHPSG13_INVX2 +XA_DEC3INV<8> net23<23> A_SEL_P<8> VDD VSS / RSC_IHPSG13_INVX2 +XA_DEC3INV<7> net23<24> A_SEL_P<7> VDD VSS / RSC_IHPSG13_INVX2 +XA_DEC3INV<6> net23<25> A_SEL_P<6> VDD VSS / RSC_IHPSG13_INVX2 +XA_DEC3INV<5> net23<26> A_SEL_P<5> VDD VSS / RSC_IHPSG13_INVX2 +XA_DEC3INV<4> net23<27> A_SEL_P<4> VDD VSS / RSC_IHPSG13_INVX2 +XA_DEC3INV<3> net23<28> A_SEL_P<3> VDD VSS / RSC_IHPSG13_INVX2 +XA_DEC3INV<2> net23<29> A_SEL_P<2> VDD VSS / RSC_IHPSG13_INVX2 +XA_DEC3INV<1> net23<30> A_SEL_P<1> VDD VSS / RSC_IHPSG13_INVX2 +XA_DEC3INV<0> net23<31> A_SEL_P<0> VDD VSS / RSC_IHPSG13_INVX2 +XA_I49 A_DI_R A_DI_N VDD VSS / RSC_IHPSG13_INVX2 +XB_ISENSE B_SAE B_BLC_SEL B_BLT_SEL net037 net038 VDD VSS / ++ RSC_IHPSG13_DFPQD_MSAFFX2 +XA_ISENSE A_SAE A_BLC_SEL A_BLT_SEL net19 net20 VDD VSS / ++ RSC_IHPSG13_DFPQD_MSAFFX2 +XB_DREG B_BIST_EN_I B_BIST_DW_I B_DCLK_B_L B_DW_I B_DI_R net042 VDD ++ VSS / RSC_IHPSG13_DFNQMX2IX1 +XB_BREG B_BIST_EN_I B_BIST_BM_I B_DCLK_B_L B_BM_I B_BM_R net043 VDD ++ VSS / RSC_IHPSG13_DFNQMX2IX1 +XA_DREG A_BIST_EN_I A_BIST_DW_I A_DCLK_B_L A_DW_I A_DI_R net22 VDD VSS ++ / RSC_IHPSG13_DFNQMX2IX1 +XA_BREG A_BIST_EN_I A_BIST_BM_I A_DCLK_B_L A_BM_I A_BM_R net21 VDD VSS ++ / RSC_IHPSG13_DFNQMX2IX1 +XB_DEC3<31> B_P1<1> B_P0<1> B_ADDR_DEC<7> net041<0> VDD VSS / ++ RSC_IHPSG13_NAND3X2 +XB_DEC3<30> B_P1<1> B_P0<1> B_ADDR_DEC<6> net041<1> VDD VSS / ++ RSC_IHPSG13_NAND3X2 +XB_DEC3<29> B_P1<1> B_P0<1> B_ADDR_DEC<5> net041<2> VDD VSS / ++ RSC_IHPSG13_NAND3X2 +XB_DEC3<28> B_P1<1> B_P0<1> B_ADDR_DEC<4> net041<3> VDD VSS / ++ RSC_IHPSG13_NAND3X2 +XB_DEC3<27> B_P1<1> B_P0<1> B_ADDR_DEC<3> net041<4> VDD VSS / ++ RSC_IHPSG13_NAND3X2 +XB_DEC3<26> B_P1<1> B_P0<1> B_ADDR_DEC<2> net041<5> VDD VSS / ++ RSC_IHPSG13_NAND3X2 +XB_DEC3<25> B_P1<1> B_P0<1> B_ADDR_DEC<1> net041<6> VDD VSS / ++ RSC_IHPSG13_NAND3X2 +XB_DEC3<24> B_P1<1> B_P0<1> B_ADDR_DEC<0> net041<7> VDD VSS / ++ RSC_IHPSG13_NAND3X2 +XB_DEC3<23> B_P1<1> B_N0<1> B_ADDR_DEC<7> net041<8> VDD VSS / ++ RSC_IHPSG13_NAND3X2 +XB_DEC3<22> B_P1<1> B_N0<1> B_ADDR_DEC<6> net041<9> VDD VSS / ++ RSC_IHPSG13_NAND3X2 +XB_DEC3<21> B_P1<1> B_N0<1> B_ADDR_DEC<5> net041<10> VDD VSS / ++ RSC_IHPSG13_NAND3X2 +XB_DEC3<20> B_P1<1> B_N0<1> B_ADDR_DEC<4> net041<11> VDD VSS / ++ RSC_IHPSG13_NAND3X2 +XB_DEC3<19> B_P1<1> B_N0<1> B_ADDR_DEC<3> net041<12> VDD VSS / ++ RSC_IHPSG13_NAND3X2 +XB_DEC3<18> B_P1<1> B_N0<1> B_ADDR_DEC<2> net041<13> VDD VSS / ++ RSC_IHPSG13_NAND3X2 +XB_DEC3<17> B_P1<1> B_N0<1> B_ADDR_DEC<1> net041<14> VDD VSS / ++ RSC_IHPSG13_NAND3X2 +XB_DEC3<16> B_P1<1> B_N0<1> B_ADDR_DEC<0> net041<15> VDD VSS / ++ RSC_IHPSG13_NAND3X2 +XB_DEC3<15> B_N1<0> B_P0<0> B_ADDR_DEC<7> net041<16> VDD VSS / ++ RSC_IHPSG13_NAND3X2 +XB_DEC3<14> B_N1<0> B_P0<0> B_ADDR_DEC<6> net041<17> VDD VSS / ++ RSC_IHPSG13_NAND3X2 +XB_DEC3<13> B_N1<0> B_P0<0> B_ADDR_DEC<5> net041<18> VDD VSS / ++ RSC_IHPSG13_NAND3X2 +XB_DEC3<12> B_N1<0> B_P0<0> B_ADDR_DEC<4> net041<19> VDD VSS / ++ RSC_IHPSG13_NAND3X2 +XB_DEC3<11> B_N1<0> B_P0<0> B_ADDR_DEC<3> net041<20> VDD VSS / ++ RSC_IHPSG13_NAND3X2 +XB_DEC3<10> B_N1<0> B_P0<0> B_ADDR_DEC<2> net041<21> VDD VSS / ++ RSC_IHPSG13_NAND3X2 +XB_DEC3<9> B_N1<0> B_P0<0> B_ADDR_DEC<1> net041<22> VDD VSS / ++ RSC_IHPSG13_NAND3X2 +XB_DEC3<8> B_N1<0> B_P0<0> B_ADDR_DEC<0> net041<23> VDD VSS / ++ RSC_IHPSG13_NAND3X2 +XB_DEC3<7> B_N1<0> B_N0<0> B_ADDR_DEC<7> net041<24> VDD VSS / ++ RSC_IHPSG13_NAND3X2 +XB_DEC3<6> B_N1<0> B_N0<0> B_ADDR_DEC<6> net041<25> VDD VSS / ++ RSC_IHPSG13_NAND3X2 +XB_DEC3<5> B_N1<0> B_N0<0> B_ADDR_DEC<5> net041<26> VDD VSS / ++ RSC_IHPSG13_NAND3X2 +XB_DEC3<4> B_N1<0> B_N0<0> B_ADDR_DEC<4> net041<27> VDD VSS / ++ RSC_IHPSG13_NAND3X2 +XB_DEC3<3> B_N1<0> B_N0<0> B_ADDR_DEC<3> net041<28> VDD VSS / ++ RSC_IHPSG13_NAND3X2 +XB_DEC3<2> B_N1<0> B_N0<0> B_ADDR_DEC<2> net041<29> VDD VSS / ++ RSC_IHPSG13_NAND3X2 +XB_DEC3<1> B_N1<0> B_N0<0> B_ADDR_DEC<1> net041<30> VDD VSS / ++ RSC_IHPSG13_NAND3X2 +XB_DEC3<0> B_N1<0> B_N0<0> B_ADDR_DEC<0> net041<31> VDD VSS / ++ RSC_IHPSG13_NAND3X2 +XA_DEC3<31> A_P1<1> A_P0<1> A_ADDR_DEC<7> net23<0> VDD VSS / ++ RSC_IHPSG13_NAND3X2 +XA_DEC3<30> A_P1<1> A_P0<1> A_ADDR_DEC<6> net23<1> VDD VSS / ++ RSC_IHPSG13_NAND3X2 +XA_DEC3<29> A_P1<1> A_P0<1> A_ADDR_DEC<5> net23<2> VDD VSS / ++ RSC_IHPSG13_NAND3X2 +XA_DEC3<28> A_P1<1> A_P0<1> A_ADDR_DEC<4> net23<3> VDD VSS / ++ RSC_IHPSG13_NAND3X2 +XA_DEC3<27> A_P1<1> A_P0<1> A_ADDR_DEC<3> net23<4> VDD VSS / ++ RSC_IHPSG13_NAND3X2 +XA_DEC3<26> A_P1<1> A_P0<1> A_ADDR_DEC<2> net23<5> VDD VSS / ++ RSC_IHPSG13_NAND3X2 +XA_DEC3<25> A_P1<1> A_P0<1> A_ADDR_DEC<1> net23<6> VDD VSS / ++ RSC_IHPSG13_NAND3X2 +XA_DEC3<24> A_P1<1> A_P0<1> A_ADDR_DEC<0> net23<7> VDD VSS / ++ RSC_IHPSG13_NAND3X2 +XA_DEC3<23> A_P1<1> A_N0<1> A_ADDR_DEC<7> net23<8> VDD VSS / ++ RSC_IHPSG13_NAND3X2 +XA_DEC3<22> A_P1<1> A_N0<1> A_ADDR_DEC<6> net23<9> VDD VSS / ++ RSC_IHPSG13_NAND3X2 +XA_DEC3<21> A_P1<1> A_N0<1> A_ADDR_DEC<5> net23<10> VDD VSS / ++ RSC_IHPSG13_NAND3X2 +XA_DEC3<20> A_P1<1> A_N0<1> A_ADDR_DEC<4> net23<11> VDD VSS / ++ RSC_IHPSG13_NAND3X2 +XA_DEC3<19> A_P1<1> A_N0<1> A_ADDR_DEC<3> net23<12> VDD VSS / ++ RSC_IHPSG13_NAND3X2 +XA_DEC3<18> A_P1<1> A_N0<1> A_ADDR_DEC<2> net23<13> VDD VSS / ++ RSC_IHPSG13_NAND3X2 +XA_DEC3<17> A_P1<1> A_N0<1> A_ADDR_DEC<1> net23<14> VDD VSS / ++ RSC_IHPSG13_NAND3X2 +XA_DEC3<16> A_P1<1> A_N0<1> A_ADDR_DEC<0> net23<15> VDD VSS / ++ RSC_IHPSG13_NAND3X2 +XA_DEC3<15> A_N1<0> A_P0<0> A_ADDR_DEC<7> net23<16> VDD VSS / ++ RSC_IHPSG13_NAND3X2 +XA_DEC3<14> A_N1<0> A_P0<0> A_ADDR_DEC<6> net23<17> VDD VSS / ++ RSC_IHPSG13_NAND3X2 +XA_DEC3<13> A_N1<0> A_P0<0> A_ADDR_DEC<5> net23<18> VDD VSS / ++ RSC_IHPSG13_NAND3X2 +XA_DEC3<12> A_N1<0> A_P0<0> A_ADDR_DEC<4> net23<19> VDD VSS / ++ RSC_IHPSG13_NAND3X2 +XA_DEC3<11> A_N1<0> A_P0<0> A_ADDR_DEC<3> net23<20> VDD VSS / ++ RSC_IHPSG13_NAND3X2 +XA_DEC3<10> A_N1<0> A_P0<0> A_ADDR_DEC<2> net23<21> VDD VSS / ++ RSC_IHPSG13_NAND3X2 +XA_DEC3<9> A_N1<0> A_P0<0> A_ADDR_DEC<1> net23<22> VDD VSS / ++ RSC_IHPSG13_NAND3X2 +XA_DEC3<8> A_N1<0> A_P0<0> A_ADDR_DEC<0> net23<23> VDD VSS / ++ RSC_IHPSG13_NAND3X2 +XA_DEC3<7> A_N1<0> A_N0<0> A_ADDR_DEC<7> net23<24> VDD VSS / ++ RSC_IHPSG13_NAND3X2 +XA_DEC3<6> A_N1<0> A_N0<0> A_ADDR_DEC<6> net23<25> VDD VSS / ++ RSC_IHPSG13_NAND3X2 +XA_DEC3<5> A_N1<0> A_N0<0> A_ADDR_DEC<5> net23<26> VDD VSS / ++ RSC_IHPSG13_NAND3X2 +XA_DEC3<4> A_N1<0> A_N0<0> A_ADDR_DEC<4> net23<27> VDD VSS / ++ RSC_IHPSG13_NAND3X2 +XA_DEC3<3> A_N1<0> A_N0<0> A_ADDR_DEC<3> net23<28> VDD VSS / ++ RSC_IHPSG13_NAND3X2 +XA_DEC3<2> A_N1<0> A_N0<0> A_ADDR_DEC<2> net23<29> VDD VSS / ++ RSC_IHPSG13_NAND3X2 +XA_DEC3<1> A_N1<0> A_N0<0> A_ADDR_DEC<1> net23<30> VDD VSS / ++ RSC_IHPSG13_NAND3X2 +XA_DEC3<0> A_N1<0> A_N0<0> A_ADDR_DEC<0> net23<31> VDD VSS / ++ RSC_IHPSG13_NAND3X2 +XB_I89 B_DCLK_B_L B_DCLK_B_R / RSC_IHPSG13_MET3RES +XB_I91 B_RCLK_B_L B_RCLK_B_R / RSC_IHPSG13_MET3RES +XB_I90 B_WCLK_B_L B_WCLK_B_R / RSC_IHPSG13_MET3RES +XB_I88 B_DCLK_L B_DCLK_R / RSC_IHPSG13_MET3RES +XB_I87 B_WCLK_L B_WCLK_R / RSC_IHPSG13_MET3RES +XB_R2 B_RCLK_L B_RCLK_R / RSC_IHPSG13_MET3RES +XA_I89 A_DCLK_B_L A_DCLK_B_R / RSC_IHPSG13_MET3RES +XA_I91 A_RCLK_B_L A_RCLK_B_R / RSC_IHPSG13_MET3RES +XA_I90 A_WCLK_B_L A_WCLK_B_R / RSC_IHPSG13_MET3RES +XA_I88 A_DCLK_L A_DCLK_R / RSC_IHPSG13_MET3RES +XA_I87 A_WCLK_L A_WCLK_R / RSC_IHPSG13_MET3RES +XA_R2 A_RCLK_L A_RCLK_R / RSC_IHPSG13_MET3RES +XB_BM_TIEH B_TIEH_O VDD VSS / RSC_IHPSG13_TIEH +XA_BM_TIEH A_TIEH_O VDD VSS / RSC_IHPSG13_TIEH +.ENDS +.SUBCKT RM_IHPSG13_256x16_c2_2P_COLDRV13_FILL4 VDD VSS +XI0<11> VDD VSS / RSC_IHPSG13_FILLCAP4 +XI0<10> VDD VSS / RSC_IHPSG13_FILLCAP4 +XI0<9> VDD VSS / RSC_IHPSG13_FILLCAP4 +XI0<8> VDD VSS / RSC_IHPSG13_FILLCAP4 +XI0<7> VDD VSS / RSC_IHPSG13_FILLCAP4 +XI0<6> VDD VSS / RSC_IHPSG13_FILLCAP4 +XI0<5> VDD VSS / RSC_IHPSG13_FILLCAP4 +XI0<4> VDD VSS / RSC_IHPSG13_FILLCAP4 +XI0<3> VDD VSS / RSC_IHPSG13_FILLCAP4 +XI0<2> VDD VSS / RSC_IHPSG13_FILLCAP4 +XI0<1> VDD VSS / RSC_IHPSG13_FILLCAP4 +.ENDS + + +.SUBCKT RSC_IHPSG13_CBUFX16 A Z VDD VSS +MN0 net4 A VSS VSS sg13_lv_nmos m=1 w=2.115u l=130.00n ng=3 nrd=0 nrs=0 +MN1 Z net4 VSS VSS sg13_lv_nmos m=1 w=5.64u l=130.00n ng=8 nrd=0 nrs=0 +MP1 Z net4 VDD VDD sg13_lv_pmos m=1 w=13.000u l=130.00n ng=8 nrd=0 ++ nrs=0 +MP0 net4 A VDD VDD sg13_lv_pmos m=1 w=4.89u l=130.00n ng=3 nrd=0 nrs=0 +.ENDS +.SUBCKT RM_IHPSG13_256x16_c2_1P_COLDRV13X16 ADDR_COL_I<1> ADDR_COL_I<0> ADDR_COL_O<1> ++ ADDR_COL_O<0> ADDR_DEC_I<7> ADDR_DEC_I<6> ADDR_DEC_I<5> ADDR_DEC_I<4> ++ ADDR_DEC_I<3> ADDR_DEC_I<2> ADDR_DEC_I<1> ADDR_DEC_I<0> ADDR_DEC_O<7> ++ ADDR_DEC_O<6> ADDR_DEC_O<5> ADDR_DEC_O<4> ADDR_DEC_O<3> ADDR_DEC_O<2> ++ ADDR_DEC_O<1> ADDR_DEC_O<0> DCLK_I DCLK_O RCLK_I RCLK_O WCLK_I WCLK_O ++ VDD VSS +XI1<1> VDD VSS / RSC_IHPSG13_FILLCAP4 +XI1<0> VDD VSS / RSC_IHPSG13_FILLCAP4 +XI0<3> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI0<2> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI0<1> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI0<0> VDD VSS / RSC_IHPSG13_FILLCAP8 +XADDR_COL_DRV<1> ADDR_COL_I<1> ADDR_COL_O<1> VDD VSS / ++ RSC_IHPSG13_CBUFX16 +XADDR_COL_DRV<0> ADDR_COL_I<0> ADDR_COL_O<0> VDD VSS / ++ RSC_IHPSG13_CBUFX16 +XADDR_DEC_DRV<7> ADDR_DEC_I<7> ADDR_DEC_O<7> VDD VSS / ++ RSC_IHPSG13_CBUFX16 +XADDR_DEC_DRV<6> ADDR_DEC_I<6> ADDR_DEC_O<6> VDD VSS / ++ RSC_IHPSG13_CBUFX16 +XADDR_DEC_DRV<5> ADDR_DEC_I<5> ADDR_DEC_O<5> VDD VSS / ++ RSC_IHPSG13_CBUFX16 +XADDR_DEC_DRV<4> ADDR_DEC_I<4> ADDR_DEC_O<4> VDD VSS / ++ RSC_IHPSG13_CBUFX16 +XADDR_DEC_DRV<3> ADDR_DEC_I<3> ADDR_DEC_O<3> VDD VSS / ++ RSC_IHPSG13_CBUFX16 +XADDR_DEC_DRV<2> ADDR_DEC_I<2> ADDR_DEC_O<2> VDD VSS / ++ RSC_IHPSG13_CBUFX16 +XADDR_DEC_DRV<1> ADDR_DEC_I<1> ADDR_DEC_O<1> VDD VSS / ++ RSC_IHPSG13_CBUFX16 +XADDR_DEC_DRV<0> ADDR_DEC_I<0> ADDR_DEC_O<0> VDD VSS / ++ RSC_IHPSG13_CBUFX16 +XDCLK_DRV DCLK_I DCLK_O VDD VSS / RSC_IHPSG13_CBUFX16 +XRCLK_DRV RCLK_I RCLK_O VDD VSS / RSC_IHPSG13_CBUFX16 +XWCLK_DRV WCLK_I WCLK_O VDD VSS / RSC_IHPSG13_CBUFX16 +.ENDS +.SUBCKT RSC_IHPSG13_WLDRVX16 A Z VDD VSS +MN1 Z net6 VSS VSS sg13_lv_nmos m=1 w=1.41u l=130.00n ng=2 nrd=0 nrs=0 +MN0 net6 A VSS VSS sg13_lv_nmos m=1 w=1.8u l=130.00n ng=2 nrd=0 nrs=0 +MP1 Z net6 VDD VDD sg13_lv_pmos m=1 w=12.96u l=130.00n ng=8 nrd=0 nrs=0 +MP0 net6 A VDD VDD sg13_lv_pmos m=1 w=900.0n l=130.00n ng=1 nrd=0 nrs=0 +.ENDS +.SUBCKT RM_IHPSG13_256x16_c2_1P_WLDRV16X16 A<15> A<14> A<13> A<12> A<11> A<10> A<9> A<8> ++ A<7> A<6> A<5> A<4> A<3> A<2> A<1> A<0> Z<15> Z<14> Z<13> Z<12> Z<11> Z<10> ++ Z<9> Z<8> Z<7> Z<6> Z<5> Z<4> Z<3> Z<2> Z<1> Z<0> VDD VSS +XBUF<15> A<15> Z<15> VDD VSS / RSC_IHPSG13_WLDRVX16 +XBUF<14> A<14> Z<14> VDD VSS / RSC_IHPSG13_WLDRVX16 +XBUF<13> A<13> Z<13> VDD VSS / RSC_IHPSG13_WLDRVX16 +XBUF<12> A<12> Z<12> VDD VSS / RSC_IHPSG13_WLDRVX16 +XBUF<11> A<11> Z<11> VDD VSS / RSC_IHPSG13_WLDRVX16 +XBUF<10> A<10> Z<10> VDD VSS / RSC_IHPSG13_WLDRVX16 +XBUF<9> A<9> Z<9> VDD VSS / RSC_IHPSG13_WLDRVX16 +XBUF<8> A<8> Z<8> VDD VSS / RSC_IHPSG13_WLDRVX16 +XBUF<7> A<7> Z<7> VDD VSS / RSC_IHPSG13_WLDRVX16 +XBUF<6> A<6> Z<6> VDD VSS / RSC_IHPSG13_WLDRVX16 +XBUF<5> A<5> Z<5> VDD VSS / RSC_IHPSG13_WLDRVX16 +XBUF<4> A<4> Z<4> VDD VSS / RSC_IHPSG13_WLDRVX16 +XBUF<3> A<3> Z<3> VDD VSS / RSC_IHPSG13_WLDRVX16 +XBUF<2> A<2> Z<2> VDD VSS / RSC_IHPSG13_WLDRVX16 +XBUF<1> A<1> Z<1> VDD VSS / RSC_IHPSG13_WLDRVX16 +XBUF<0> A<0> Z<0> VDD VSS / RSC_IHPSG13_WLDRVX16 +.ENDS + + +.SUBCKT RM_IHPSG13_256x16_c2_2P_COLDRV13X4 ADDR_COL_I<1> ADDR_COL_I<0> ADDR_COL_O<1> ++ ADDR_COL_O<0> ADDR_DEC_I<7> ADDR_DEC_I<6> ADDR_DEC_I<5> ADDR_DEC_I<4> ++ ADDR_DEC_I<3> ADDR_DEC_I<2> ADDR_DEC_I<1> ADDR_DEC_I<0> ADDR_DEC_O<7> ++ ADDR_DEC_O<6> ADDR_DEC_O<5> ADDR_DEC_O<4> ADDR_DEC_O<3> ADDR_DEC_O<2> ++ ADDR_DEC_O<1> ADDR_DEC_O<0> DCLK_I DCLK_O RCLK_I RCLK_O WCLK_I WCLK_O ++ VDD VSS +XWCLK_DRV WCLK_I WCLK_O VDD VSS / RSC_IHPSG13_CBUFX4 +XRCLK_DRV RCLK_I RCLK_O VDD VSS / RSC_IHPSG13_CBUFX4 +XDCLK_DRV DCLK_I DCLK_O VDD VSS / RSC_IHPSG13_CBUFX4 +XADDR_COL_DRV<1> ADDR_COL_I<1> ADDR_COL_O<1> VDD VSS / ++ RSC_IHPSG13_CBUFX4 +XADDR_COL_DRV<0> ADDR_COL_I<0> ADDR_COL_O<0> VDD VSS / ++ RSC_IHPSG13_CBUFX4 +XADDR_DEC_DRV<7> ADDR_DEC_I<7> ADDR_DEC_O<7> VDD VSS / ++ RSC_IHPSG13_CBUFX4 +XADDR_DEC_DRV<6> ADDR_DEC_I<6> ADDR_DEC_O<6> VDD VSS / ++ RSC_IHPSG13_CBUFX4 +XADDR_DEC_DRV<5> ADDR_DEC_I<5> ADDR_DEC_O<5> VDD VSS / ++ RSC_IHPSG13_CBUFX4 +XADDR_DEC_DRV<4> ADDR_DEC_I<4> ADDR_DEC_O<4> VDD VSS / ++ RSC_IHPSG13_CBUFX4 +XADDR_DEC_DRV<3> ADDR_DEC_I<3> ADDR_DEC_O<3> VDD VSS / ++ RSC_IHPSG13_CBUFX4 +XADDR_DEC_DRV<2> ADDR_DEC_I<2> ADDR_DEC_O<2> VDD VSS / ++ RSC_IHPSG13_CBUFX4 +XADDR_DEC_DRV<1> ADDR_DEC_I<1> ADDR_DEC_O<1> VDD VSS / ++ RSC_IHPSG13_CBUFX4 +XADDR_DEC_DRV<0> ADDR_DEC_I<0> ADDR_DEC_O<0> VDD VSS / ++ RSC_IHPSG13_CBUFX4 +XI0<6> VDD VSS / RSC_IHPSG13_FILLCAP4 +XI0<5> VDD VSS / RSC_IHPSG13_FILLCAP4 +XI0<4> VDD VSS / RSC_IHPSG13_FILLCAP4 +XI0<3> VDD VSS / RSC_IHPSG13_FILLCAP4 +XI0<2> VDD VSS / RSC_IHPSG13_FILLCAP4 +XI0<1> VDD VSS / RSC_IHPSG13_FILLCAP4 +XI1 VDD VSS / RSC_IHPSG13_FILLCAP8 +.ENDS +.SUBCKT RM_IHPSG13_256x16_c2_2P_WLDRV16X4 A<15> A<14> A<13> A<12> A<11> A<10> A<9> A<8> ++ A<7> A<6> A<5> A<4> A<3> A<2> A<1> A<0> Z<15> Z<14> Z<13> Z<12> Z<11> Z<10> ++ Z<9> Z<8> Z<7> Z<6> Z<5> Z<4> Z<3> Z<2> Z<1> Z<0> VDD VSS +XBUF<15> A<15> Z<15> VDD VSS / RSC_IHPSG13_WLDRVX4 +XBUF<14> A<14> Z<14> VDD VSS / RSC_IHPSG13_WLDRVX4 +XBUF<13> A<13> Z<13> VDD VSS / RSC_IHPSG13_WLDRVX4 +XBUF<12> A<12> Z<12> VDD VSS / RSC_IHPSG13_WLDRVX4 +XBUF<11> A<11> Z<11> VDD VSS / RSC_IHPSG13_WLDRVX4 +XBUF<10> A<10> Z<10> VDD VSS / RSC_IHPSG13_WLDRVX4 +XBUF<9> A<9> Z<9> VDD VSS / RSC_IHPSG13_WLDRVX4 +XBUF<8> A<8> Z<8> VDD VSS / RSC_IHPSG13_WLDRVX4 +XBUF<7> A<7> Z<7> VDD VSS / RSC_IHPSG13_WLDRVX4 +XBUF<6> A<6> Z<6> VDD VSS / RSC_IHPSG13_WLDRVX4 +XBUF<5> A<5> Z<5> VDD VSS / RSC_IHPSG13_WLDRVX4 +XBUF<4> A<4> Z<4> VDD VSS / RSC_IHPSG13_WLDRVX4 +XBUF<3> A<3> Z<3> VDD VSS / RSC_IHPSG13_WLDRVX4 +XBUF<2> A<2> Z<2> VDD VSS / RSC_IHPSG13_WLDRVX4 +XBUF<1> A<1> Z<1> VDD VSS / RSC_IHPSG13_WLDRVX4 +XBUF<0> A<0> Z<0> VDD VSS / RSC_IHPSG13_WLDRVX4 +.ENDS +.SUBCKT RM_IHPSG13_256x16_c2_2P_ROWDEC8 ADDR_N_I<7> ADDR_N_I<6> ADDR_N_I<5> ADDR_N_I<4> ++ ADDR_N_I<3> ADDR_N_I<2> ADDR_N_I<1> ADDR_N_I<0> CS_I ECLK_I WL_O<255> ++ WL_O<254> WL_O<253> WL_O<252> WL_O<251> WL_O<250> WL_O<249> WL_O<248> ++ WL_O<247> WL_O<246> WL_O<245> WL_O<244> WL_O<243> WL_O<242> WL_O<241> ++ WL_O<240> WL_O<239> WL_O<238> WL_O<237> WL_O<236> WL_O<235> WL_O<234> ++ WL_O<233> WL_O<232> WL_O<231> WL_O<230> WL_O<229> WL_O<228> WL_O<227> ++ WL_O<226> WL_O<225> WL_O<224> WL_O<223> WL_O<222> WL_O<221> WL_O<220> ++ WL_O<219> WL_O<218> WL_O<217> WL_O<216> WL_O<215> WL_O<214> WL_O<213> ++ WL_O<212> WL_O<211> WL_O<210> WL_O<209> WL_O<208> WL_O<207> WL_O<206> ++ WL_O<205> WL_O<204> WL_O<203> WL_O<202> WL_O<201> WL_O<200> WL_O<199> ++ WL_O<198> WL_O<197> WL_O<196> WL_O<195> WL_O<194> WL_O<193> WL_O<192> ++ WL_O<191> WL_O<190> WL_O<189> WL_O<188> WL_O<187> WL_O<186> WL_O<185> ++ WL_O<184> WL_O<183> WL_O<182> WL_O<181> WL_O<180> WL_O<179> WL_O<178> ++ WL_O<177> WL_O<176> WL_O<175> WL_O<174> WL_O<173> WL_O<172> WL_O<171> ++ WL_O<170> WL_O<169> WL_O<168> WL_O<167> WL_O<166> WL_O<165> WL_O<164> ++ WL_O<163> WL_O<162> WL_O<161> WL_O<160> WL_O<159> WL_O<158> WL_O<157> ++ WL_O<156> WL_O<155> WL_O<154> WL_O<153> WL_O<152> WL_O<151> WL_O<150> ++ WL_O<149> WL_O<148> WL_O<147> WL_O<146> WL_O<145> WL_O<144> WL_O<143> ++ WL_O<142> WL_O<141> WL_O<140> WL_O<139> WL_O<138> WL_O<137> WL_O<136> ++ WL_O<135> WL_O<134> WL_O<133> WL_O<132> WL_O<131> WL_O<130> WL_O<129> ++ WL_O<128> WL_O<127> WL_O<126> WL_O<125> WL_O<124> WL_O<123> WL_O<122> ++ WL_O<121> WL_O<120> WL_O<119> WL_O<118> WL_O<117> WL_O<116> WL_O<115> ++ WL_O<114> WL_O<113> WL_O<112> WL_O<111> WL_O<110> WL_O<109> WL_O<108> ++ WL_O<107> WL_O<106> WL_O<105> WL_O<104> WL_O<103> WL_O<102> WL_O<101> ++ WL_O<100> WL_O<99> WL_O<98> WL_O<97> WL_O<96> WL_O<95> WL_O<94> WL_O<93> ++ WL_O<92> WL_O<91> WL_O<90> WL_O<89> WL_O<88> WL_O<87> WL_O<86> WL_O<85> ++ WL_O<84> WL_O<83> WL_O<82> WL_O<81> WL_O<80> WL_O<79> WL_O<78> WL_O<77> ++ WL_O<76> WL_O<75> WL_O<74> WL_O<73> WL_O<72> WL_O<71> WL_O<70> WL_O<69> ++ WL_O<68> WL_O<67> WL_O<66> WL_O<65> WL_O<64> WL_O<63> WL_O<62> WL_O<61> ++ WL_O<60> WL_O<59> WL_O<58> WL_O<57> WL_O<56> WL_O<55> WL_O<54> WL_O<53> ++ WL_O<52> WL_O<51> WL_O<50> WL_O<49> WL_O<48> WL_O<47> WL_O<46> WL_O<45> ++ WL_O<44> WL_O<43> WL_O<42> WL_O<41> WL_O<40> WL_O<39> WL_O<38> WL_O<37> ++ WL_O<36> WL_O<35> WL_O<34> WL_O<33> WL_O<32> WL_O<31> WL_O<30> WL_O<29> ++ WL_O<28> WL_O<27> WL_O<26> WL_O<25> WL_O<24> WL_O<23> WL_O<22> WL_O<21> ++ WL_O<20> WL_O<19> WL_O<18> WL_O<17> WL_O<16> WL_O<15> WL_O<14> WL_O<13> ++ WL_O<12> WL_O<11> WL_O<10> WL_O<9> WL_O<8> WL_O<7> WL_O<6> WL_O<5> WL_O<4> ++ WL_O<3> WL_O<2> WL_O<1> WL_O<0> VDD VSS +XDEC11<4> ADDR_N_I<7> ADDR_N_I<6> CS_I CS04<3> VDD VSS / ++ RM_IHPSG13_256x16_c2_2P_DEC03 +XDEC11<3> ADDR_N_I<5> ADDR_N_I<4> CS04<3> CS00<15> VDD VSS / ++ RM_IHPSG13_256x16_c2_2P_DEC03 +XDEC11<2> ADDR_N_I<5> ADDR_N_I<4> CS04<2> CS00<11> VDD VSS / ++ RM_IHPSG13_256x16_c2_2P_DEC03 +XDEC11<1> ADDR_N_I<5> ADDR_N_I<4> CS04<1> CS00<7> VDD VSS / ++ RM_IHPSG13_256x16_c2_2P_DEC03 +XDEC11<0> ADDR_N_I<5> ADDR_N_I<4> CS04<0> CS00<3> VDD VSS / ++ RM_IHPSG13_256x16_c2_2P_DEC03 +XSEL<15> ADDR_N_I<3> ADDR_N_I<2> ADDR_N_I<1> ADDR_N_I<0> CS00<15> ECLK_H<15> ++ ECLK_H<16> ECLK_B<15> ECLK_B<16> WL_O<255> WL_O<254> WL_O<253> WL_O<252> ++ WL_O<251> WL_O<250> WL_O<249> WL_O<248> WL_O<247> WL_O<246> WL_O<245> ++ WL_O<244> WL_O<243> WL_O<242> WL_O<241> WL_O<240> VDD VSS / ++ RM_IHPSG13_256x16_c2_2P_DEC04 +XSEL<14> ADDR_N_I<3> ADDR_N_I<2> ADDR_N_I<1> ADDR_N_I<0> CS00<14> ECLK_H<14> ++ ECLK_H<15> ECLK_B<14> ECLK_B<15> WL_O<239> WL_O<238> WL_O<237> WL_O<236> ++ WL_O<235> WL_O<234> WL_O<233> WL_O<232> WL_O<231> WL_O<230> WL_O<229> ++ WL_O<228> WL_O<227> WL_O<226> WL_O<225> WL_O<224> VDD VSS / ++ RM_IHPSG13_256x16_c2_2P_DEC04 +XSEL<13> ADDR_N_I<3> ADDR_N_I<2> ADDR_N_I<1> ADDR_N_I<0> CS00<13> ECLK_H<13> ++ ECLK_H<14> ECLK_B<13> ECLK_B<14> WL_O<223> WL_O<222> WL_O<221> WL_O<220> ++ WL_O<219> WL_O<218> WL_O<217> WL_O<216> WL_O<215> WL_O<214> WL_O<213> ++ WL_O<212> WL_O<211> WL_O<210> WL_O<209> WL_O<208> VDD VSS / ++ RM_IHPSG13_256x16_c2_2P_DEC04 +XSEL<12> ADDR_N_I<3> ADDR_N_I<2> ADDR_N_I<1> ADDR_N_I<0> CS00<12> ECLK_H<12> ++ ECLK_H<13> ECLK_B<12> ECLK_B<13> WL_O<207> WL_O<206> WL_O<205> WL_O<204> ++ WL_O<203> WL_O<202> WL_O<201> WL_O<200> WL_O<199> WL_O<198> WL_O<197> ++ WL_O<196> WL_O<195> WL_O<194> WL_O<193> WL_O<192> VDD VSS / ++ RM_IHPSG13_256x16_c2_2P_DEC04 +XSEL<11> ADDR_N_I<3> ADDR_N_I<2> ADDR_N_I<1> ADDR_N_I<0> CS00<11> ECLK_H<11> ++ ECLK_H<12> ECLK_B<11> ECLK_B<12> WL_O<191> WL_O<190> WL_O<189> WL_O<188> ++ WL_O<187> WL_O<186> WL_O<185> WL_O<184> WL_O<183> WL_O<182> WL_O<181> ++ WL_O<180> WL_O<179> WL_O<178> WL_O<177> WL_O<176> VDD VSS / ++ RM_IHPSG13_256x16_c2_2P_DEC04 +XSEL<10> ADDR_N_I<3> ADDR_N_I<2> ADDR_N_I<1> ADDR_N_I<0> CS00<10> ECLK_H<10> ++ ECLK_H<11> ECLK_B<10> ECLK_B<11> WL_O<175> WL_O<174> WL_O<173> WL_O<172> ++ WL_O<171> WL_O<170> WL_O<169> WL_O<168> WL_O<167> WL_O<166> WL_O<165> ++ WL_O<164> WL_O<163> WL_O<162> WL_O<161> WL_O<160> VDD VSS / ++ RM_IHPSG13_256x16_c2_2P_DEC04 +XSEL<9> ADDR_N_I<3> ADDR_N_I<2> ADDR_N_I<1> ADDR_N_I<0> CS00<9> ECLK_H<9> ++ ECLK_H<10> ECLK_B<9> ECLK_B<10> WL_O<159> WL_O<158> WL_O<157> WL_O<156> ++ WL_O<155> WL_O<154> WL_O<153> WL_O<152> WL_O<151> WL_O<150> WL_O<149> ++ WL_O<148> WL_O<147> WL_O<146> WL_O<145> WL_O<144> VDD VSS / ++ RM_IHPSG13_256x16_c2_2P_DEC04 +XSEL<8> ADDR_N_I<3> ADDR_N_I<2> ADDR_N_I<1> ADDR_N_I<0> CS00<8> ECLK_H<8> ++ ECLK_H<9> ECLK_B<8> ECLK_B<9> WL_O<143> WL_O<142> WL_O<141> WL_O<140> ++ WL_O<139> WL_O<138> WL_O<137> WL_O<136> WL_O<135> WL_O<134> WL_O<133> ++ WL_O<132> WL_O<131> WL_O<130> WL_O<129> WL_O<128> VDD VSS / ++ RM_IHPSG13_256x16_c2_2P_DEC04 +XSEL<7> ADDR_N_I<3> ADDR_N_I<2> ADDR_N_I<1> ADDR_N_I<0> CS00<7> ECLK_H<7> ++ ECLK_H<8> ECLK_B<7> ECLK_B<8> WL_O<127> WL_O<126> WL_O<125> WL_O<124> ++ WL_O<123> WL_O<122> WL_O<121> WL_O<120> WL_O<119> WL_O<118> WL_O<117> ++ WL_O<116> WL_O<115> WL_O<114> WL_O<113> WL_O<112> VDD VSS / ++ RM_IHPSG13_256x16_c2_2P_DEC04 +XSEL<6> ADDR_N_I<3> ADDR_N_I<2> ADDR_N_I<1> ADDR_N_I<0> CS00<6> ECLK_H<6> ++ ECLK_H<7> ECLK_B<6> ECLK_B<7> WL_O<111> WL_O<110> WL_O<109> WL_O<108> ++ WL_O<107> WL_O<106> WL_O<105> WL_O<104> WL_O<103> WL_O<102> WL_O<101> ++ WL_O<100> WL_O<99> WL_O<98> WL_O<97> WL_O<96> VDD VSS / ++ RM_IHPSG13_256x16_c2_2P_DEC04 +XSEL<5> ADDR_N_I<3> ADDR_N_I<2> ADDR_N_I<1> ADDR_N_I<0> CS00<5> ECLK_H<5> ++ ECLK_H<6> ECLK_B<5> ECLK_B<6> WL_O<95> WL_O<94> WL_O<93> WL_O<92> WL_O<91> ++ WL_O<90> WL_O<89> WL_O<88> WL_O<87> WL_O<86> WL_O<85> WL_O<84> WL_O<83> ++ WL_O<82> WL_O<81> WL_O<80> VDD VSS / RM_IHPSG13_256x16_c2_2P_DEC04 +XSEL<4> ADDR_N_I<3> ADDR_N_I<2> ADDR_N_I<1> ADDR_N_I<0> CS00<4> ECLK_H<4> ++ ECLK_H<5> ECLK_B<4> ECLK_B<5> WL_O<79> WL_O<78> WL_O<77> WL_O<76> WL_O<75> ++ WL_O<74> WL_O<73> WL_O<72> WL_O<71> WL_O<70> WL_O<69> WL_O<68> WL_O<67> ++ WL_O<66> WL_O<65> WL_O<64> VDD VSS / RM_IHPSG13_256x16_c2_2P_DEC04 +XSEL<3> ADDR_N_I<3> ADDR_N_I<2> ADDR_N_I<1> ADDR_N_I<0> CS00<3> ECLK_H<3> ++ ECLK_H<4> ECLK_B<3> ECLK_B<4> WL_O<63> WL_O<62> WL_O<61> WL_O<60> WL_O<59> ++ WL_O<58> WL_O<57> WL_O<56> WL_O<55> WL_O<54> WL_O<53> WL_O<52> WL_O<51> ++ WL_O<50> WL_O<49> WL_O<48> VDD VSS / RM_IHPSG13_256x16_c2_2P_DEC04 +XSEL<2> ADDR_N_I<3> ADDR_N_I<2> ADDR_N_I<1> ADDR_N_I<0> CS00<2> ECLK_H<2> ++ ECLK_H<3> ECLK_B<2> ECLK_B<3> WL_O<47> WL_O<46> WL_O<45> WL_O<44> WL_O<43> ++ WL_O<42> WL_O<41> WL_O<40> WL_O<39> WL_O<38> WL_O<37> WL_O<36> WL_O<35> ++ WL_O<34> WL_O<33> WL_O<32> VDD VSS / RM_IHPSG13_256x16_c2_2P_DEC04 +XSEL<1> ADDR_N_I<3> ADDR_N_I<2> ADDR_N_I<1> ADDR_N_I<0> CS00<1> ECLK_H<1> ++ ECLK_H<2> ECLK_B<1> ECLK_B<2> WL_O<31> WL_O<30> WL_O<29> WL_O<28> WL_O<27> ++ WL_O<26> WL_O<25> WL_O<24> WL_O<23> WL_O<22> WL_O<21> WL_O<20> WL_O<19> ++ WL_O<18> WL_O<17> WL_O<16> VDD VSS / RM_IHPSG13_256x16_c2_2P_DEC04 +XSEL<0> ADDR_N_I<3> ADDR_N_I<2> ADDR_N_I<1> ADDR_N_I<0> CS00<0> ECLK_I ++ ECLK_H<1> ECLK_B<0> ECLK_B<1> WL_O<15> WL_O<14> WL_O<13> WL_O<12> WL_O<11> ++ WL_O<10> WL_O<9> WL_O<8> WL_O<7> WL_O<6> WL_O<5> WL_O<4> WL_O<3> WL_O<2> ++ WL_O<1> WL_O<0> VDD VSS / RM_IHPSG13_256x16_c2_2P_DEC04 +XDEC10<4> ADDR_N_I<7> ADDR_N_I<6> CS_I CS04<2> VDD VSS / ++ RM_IHPSG13_256x16_c2_2P_DEC02 +XDEC10<3> ADDR_N_I<5> ADDR_N_I<4> CS04<3> CS00<14> VDD VSS / ++ RM_IHPSG13_256x16_c2_2P_DEC02 +XDEC10<2> ADDR_N_I<5> ADDR_N_I<4> CS04<2> CS00<10> VDD VSS / ++ RM_IHPSG13_256x16_c2_2P_DEC02 +XDEC10<1> ADDR_N_I<5> ADDR_N_I<4> CS04<1> CS00<6> VDD VSS / ++ RM_IHPSG13_256x16_c2_2P_DEC02 +XDEC10<0> ADDR_N_I<5> ADDR_N_I<4> CS04<0> CS00<2> VDD VSS / ++ RM_IHPSG13_256x16_c2_2P_DEC02 +XL2<132> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<131> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<130> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<129> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<128> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<127> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<126> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<125> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<124> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<123> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<122> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<121> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<120> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<119> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<118> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<117> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<116> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<115> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<114> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<113> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<112> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<111> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<110> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<109> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<108> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<107> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<106> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<105> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<104> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<103> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<102> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<101> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<100> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<99> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<98> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<97> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<96> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<95> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<94> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<93> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<92> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<91> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<90> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<89> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<88> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<87> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<86> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<85> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<84> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<83> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<82> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<81> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<80> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<79> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<78> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<77> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<76> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<75> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<74> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<73> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<72> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<71> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<70> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<69> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<68> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<67> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<66> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<65> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<64> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<63> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<62> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<61> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<60> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<59> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<58> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<57> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<56> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<55> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<54> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<53> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<52> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<51> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<50> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<49> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<48> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<47> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<46> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<45> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<44> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<43> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<42> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<41> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<40> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<39> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<38> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<37> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<36> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<35> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<34> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<33> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<32> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<31> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<30> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<29> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<28> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<27> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<26> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<25> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<24> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<23> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<22> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<21> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<20> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<19> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<18> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<17> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<16> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<15> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<14> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<13> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<12> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<11> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<10> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<9> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<8> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<7> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<6> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<5> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<4> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<3> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<2> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<1> VDD VSS / RSC_IHPSG13_FILLCAP8 +XDEC00<4> ADDR_N_I<7> ADDR_N_I<6> CS_I CS04<0> VDD VSS / ++ RM_IHPSG13_256x16_c2_2P_DEC00 +XDEC00<3> ADDR_N_I<5> ADDR_N_I<4> CS04<3> CS00<12> VDD VSS / ++ RM_IHPSG13_256x16_c2_2P_DEC00 +XDEC00<2> ADDR_N_I<5> ADDR_N_I<4> CS04<2> CS00<8> VDD VSS / ++ RM_IHPSG13_256x16_c2_2P_DEC00 +XDEC00<1> ADDR_N_I<5> ADDR_N_I<4> CS04<1> CS00<4> VDD VSS / ++ RM_IHPSG13_256x16_c2_2P_DEC00 +XDEC00<0> ADDR_N_I<5> ADDR_N_I<4> CS04<0> CS00<0> VDD VSS / ++ RM_IHPSG13_256x16_c2_2P_DEC00 +XDEC01<4> ADDR_N_I<7> ADDR_N_I<6> CS_I CS04<1> VDD VSS / ++ RM_IHPSG13_256x16_c2_2P_DEC01 +XDEC01<3> ADDR_N_I<5> ADDR_N_I<4> CS04<3> CS00<13> VDD VSS / ++ RM_IHPSG13_256x16_c2_2P_DEC01 +XDEC01<2> ADDR_N_I<5> ADDR_N_I<4> CS04<2> CS00<9> VDD VSS / ++ RM_IHPSG13_256x16_c2_2P_DEC01 +XDEC01<1> ADDR_N_I<5> ADDR_N_I<4> CS04<1> CS00<5> VDD VSS / ++ RM_IHPSG13_256x16_c2_2P_DEC01 +XDEC01<0> ADDR_N_I<5> ADDR_N_I<4> CS04<0> CS00<1> VDD VSS / ++ RM_IHPSG13_256x16_c2_2P_DEC01 +.ENDS +.SUBCKT RM_IHPSG13_256x16_c2_2P_ROWREG8 ACLK_N_I ADDR_I<7> ADDR_I<6> ADDR_I<5> ADDR_I<4> ++ ADDR_I<3> ADDR_I<2> ADDR_I<1> ADDR_I<0> ADDR_N_O<7> ADDR_N_O<6> ADDR_N_O<5> ++ ADDR_N_O<4> ADDR_N_O<3> ADDR_N_O<2> ADDR_N_O<1> ADDR_N_O<0> BIST_ADDR_I<7> ++ BIST_ADDR_I<6> BIST_ADDR_I<5> BIST_ADDR_I<4> BIST_ADDR_I<3> BIST_ADDR_I<2> ++ BIST_ADDR_I<1> BIST_ADDR_I<0> BIST_EN_I VDD VSS +XINV<7> q_int<7> qn_int<7> VDD VSS / RSC_IHPSG13_CINVX2 +XINV<6> q_int<6> qn_int<6> VDD VSS / RSC_IHPSG13_CINVX2 +XINV<5> q_int<5> qn_int<5> VDD VSS / RSC_IHPSG13_CINVX2 +XINV<4> q_int<4> qn_int<4> VDD VSS / RSC_IHPSG13_CINVX2 +XINV<3> q_int<3> qn_int<3> VDD VSS / RSC_IHPSG13_CINVX2 +XINV<2> q_int<2> qn_int<2> VDD VSS / RSC_IHPSG13_CINVX2 +XINV<1> q_int<1> qn_int<1> VDD VSS / RSC_IHPSG13_CINVX2 +XINV<0> q_int<0> qn_int<0> VDD VSS / RSC_IHPSG13_CINVX2 +XDRV<7> qn_int<7> ADDR_N_O<7> VDD VSS / RSC_IHPSG13_CINVX8 +XDRV<6> qn_int<6> ADDR_N_O<6> VDD VSS / RSC_IHPSG13_CINVX8 +XDRV<5> qn_int<5> ADDR_N_O<5> VDD VSS / RSC_IHPSG13_CINVX8 +XDRV<4> qn_int<4> ADDR_N_O<4> VDD VSS / RSC_IHPSG13_CINVX8 +XDRV<3> qn_int<3> ADDR_N_O<3> VDD VSS / RSC_IHPSG13_CINVX8 +XDRV<2> qn_int<2> ADDR_N_O<2> VDD VSS / RSC_IHPSG13_CINVX8 +XDRV<1> qn_int<1> ADDR_N_O<1> VDD VSS / RSC_IHPSG13_CINVX8 +XDRV<0> qn_int<0> ADDR_N_O<0> VDD VSS / RSC_IHPSG13_CINVX8 +XDFF<7> BIST_EN_I BIST_ADDR_I<7> ACLK_N_I ADDR_I<7> q_int<7> net2<0> VDD ++ VSS / RSC_IHPSG13_DFNQMX2IX1 +XDFF<6> BIST_EN_I BIST_ADDR_I<6> ACLK_N_I ADDR_I<6> q_int<6> net2<1> VDD ++ VSS / RSC_IHPSG13_DFNQMX2IX1 +XDFF<5> BIST_EN_I BIST_ADDR_I<5> ACLK_N_I ADDR_I<5> q_int<5> net2<2> VDD ++ VSS / RSC_IHPSG13_DFNQMX2IX1 +XDFF<4> BIST_EN_I BIST_ADDR_I<4> ACLK_N_I ADDR_I<4> q_int<4> net2<3> VDD ++ VSS / RSC_IHPSG13_DFNQMX2IX1 +XDFF<3> BIST_EN_I BIST_ADDR_I<3> ACLK_N_I ADDR_I<3> q_int<3> net2<4> VDD ++ VSS / RSC_IHPSG13_DFNQMX2IX1 +XDFF<2> BIST_EN_I BIST_ADDR_I<2> ACLK_N_I ADDR_I<2> q_int<2> net2<5> VDD ++ VSS / RSC_IHPSG13_DFNQMX2IX1 +XDFF<1> BIST_EN_I BIST_ADDR_I<1> ACLK_N_I ADDR_I<1> q_int<1> net2<6> VDD ++ VSS / RSC_IHPSG13_DFNQMX2IX1 +XDFF<0> BIST_EN_I BIST_ADDR_I<0> ACLK_N_I ADDR_I<0> q_int<0> net2<7> VDD ++ VSS / RSC_IHPSG13_DFNQMX2IX1 +XI11<4> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI11<3> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI11<2> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI11<1> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI10 VDD VSS / RSC_IHPSG13_FILLCAP4 +.ENDS +.SUBCKT RM_IHPSG13_256x16_c2_2P_COLDEC4 ACLK_N ADDR<3> ADDR<2> ADDR<1> ADDR<0> ++ ADDR_COL<1> ADDR_COL<0> ADDR_DEC<7> ADDR_DEC<6> ADDR_DEC<5> ADDR_DEC<4> ++ ADDR_DEC<3> ADDR_DEC<2> ADDR_DEC<1> ADDR_DEC<0> BIST_ADDR<3> BIST_ADDR<2> ++ BIST_ADDR<1> BIST_ADDR<0> BIST_EN_I VDD VSS +XI1<7> PADR<0> PADR<1> PADR<2> addr_n<7> VDD VSS / RSC_IHPSG13_NAND3X2 +XI1<6> NADR<0> PADR<1> PADR<2> addr_n<6> VDD VSS / RSC_IHPSG13_NAND3X2 +XI1<5> PADR<0> NADR<1> PADR<2> addr_n<5> VDD VSS / RSC_IHPSG13_NAND3X2 +XI1<4> NADR<0> NADR<1> PADR<2> addr_n<4> VDD VSS / RSC_IHPSG13_NAND3X2 +XI1<3> PADR<0> PADR<1> NADR<2> addr_n<3> VDD VSS / RSC_IHPSG13_NAND3X2 +XI1<2> NADR<0> PADR<1> NADR<2> addr_n<2> VDD VSS / RSC_IHPSG13_NAND3X2 +XI1<1> PADR<0> NADR<1> NADR<2> addr_n<1> VDD VSS / RSC_IHPSG13_NAND3X2 +XI1<0> NADR<0> NADR<1> NADR<2> addr_n<0> VDD VSS / RSC_IHPSG13_NAND3X2 +XDFF<3> BIST_EN_I BIST_ADDR<3> ACLK_N ADDR<3> addr_int net12<0> VDD ++ VSS / RSC_IHPSG13_DFNQMX2IX1 +XDFF<2> BIST_EN_I BIST_ADDR<2> ACLK_N ADDR<2> padr_int<2> net12<1> VDD ++ VSS / RSC_IHPSG13_DFNQMX2IX1 +XDFF<1> BIST_EN_I BIST_ADDR<1> ACLK_N ADDR<1> padr_int<1> net12<2> VDD ++ VSS / RSC_IHPSG13_DFNQMX2IX1 +XDFF<0> BIST_EN_I BIST_ADDR<0> ACLK_N ADDR<0> padr_int<0> net12<3> VDD ++ VSS / RSC_IHPSG13_DFNQMX2IX1 +XI17<4> VDD VSS / RSC_IHPSG13_FILLCAP4 +XI17<3> VDD VSS / RSC_IHPSG13_FILLCAP4 +XI17<2> VDD VSS / RSC_IHPSG13_FILLCAP4 +XI17<1> VDD VSS / RSC_IHPSG13_FILLCAP4 +XI13<2> NADR<2> PADR<2> VDD VSS / RSC_IHPSG13_INVX2 +XI13<1> NADR<1> PADR<1> VDD VSS / RSC_IHPSG13_INVX2 +XI13<0> NADR<0> PADR<0> VDD VSS / RSC_IHPSG13_INVX2 +XI2<7> addr_n<7> ADDR_DEC<7> VDD VSS / RSC_IHPSG13_INVX2 +XI2<6> addr_n<6> ADDR_DEC<6> VDD VSS / RSC_IHPSG13_INVX2 +XI2<5> addr_n<5> ADDR_DEC<5> VDD VSS / RSC_IHPSG13_INVX2 +XI2<4> addr_n<4> ADDR_DEC<4> VDD VSS / RSC_IHPSG13_INVX2 +XI2<3> addr_n<3> ADDR_DEC<3> VDD VSS / RSC_IHPSG13_INVX2 +XI2<2> addr_n<2> ADDR_DEC<2> VDD VSS / RSC_IHPSG13_INVX2 +XI2<1> addr_n<1> ADDR_DEC<1> VDD VSS / RSC_IHPSG13_INVX2 +XI2<0> addr_n<0> ADDR_DEC<0> VDD VSS / RSC_IHPSG13_INVX2 +XI3<2> padr_int<2> NADR<2> VDD VSS / RSC_IHPSG13_INVX2 +XI3<1> padr_int<1> NADR<1> VDD VSS / RSC_IHPSG13_INVX2 +XI3<0> padr_int<0> NADR<0> VDD VSS / RSC_IHPSG13_INVX2 +XI14 addr_int ADDR_COL<0> VDD VSS / RSC_IHPSG13_CBUFX2 +XI16<8> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI16<7> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI16<6> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI16<5> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI16<4> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI16<3> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI16<2> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI16<1> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI15 ADDR_COL<1> VDD VSS / RSC_IHPSG13_TIEL +.ENDS +.SUBCKT RM_IHPSG13_256x16_c2_2P_COLCTRL4 A_ADDR_COL A_ADDR_DEC<7> A_ADDR_DEC<6> ++ A_ADDR_DEC<5> A_ADDR_DEC<4> A_ADDR_DEC<3> A_ADDR_DEC<2> A_ADDR_DEC<1> ++ A_ADDR_DEC<0> A_BIST_BM_I A_BIST_DW_I A_BIST_EN_I A_BLC<15> A_BLC<14> ++ A_BLC<13> A_BLC<12> A_BLC<11> A_BLC<10> A_BLC<9> A_BLC<8> A_BLC<7> A_BLC<6> ++ A_BLC<5> A_BLC<4> A_BLC<3> A_BLC<2> A_BLC<1> A_BLC<0> A_BLT<15> A_BLT<14> ++ A_BLT<13> A_BLT<12> A_BLT<11> A_BLT<10> A_BLT<9> A_BLT<8> A_BLT<7> A_BLT<6> ++ A_BLT<5> A_BLT<4> A_BLT<3> A_BLT<2> A_BLT<1> A_BLT<0> A_BM_I A_DCLK_B_L ++ A_DCLK_B_R A_DCLK_L A_DCLK_R A_DR_O A_DW_I A_RCLK_B_L A_RCLK_B_R A_RCLK_L ++ A_RCLK_R A_TIEH_O A_WCLK_B_L A_WCLK_B_R A_WCLK_L A_WCLK_R B_ADDR_COL ++ B_ADDR_DEC<7> B_ADDR_DEC<6> B_ADDR_DEC<5> B_ADDR_DEC<4> B_ADDR_DEC<3> ++ B_ADDR_DEC<2> B_ADDR_DEC<1> B_ADDR_DEC<0> B_BIST_BM_I B_BIST_DW_I ++ B_BIST_EN_I B_BLC<15> B_BLC<14> B_BLC<13> B_BLC<12> B_BLC<11> B_BLC<10> ++ B_BLC<9> B_BLC<8> B_BLC<7> B_BLC<6> B_BLC<5> B_BLC<4> B_BLC<3> B_BLC<2> ++ B_BLC<1> B_BLC<0> B_BLT<15> B_BLT<14> B_BLT<13> B_BLT<12> B_BLT<11> ++ B_BLT<10> B_BLT<9> B_BLT<8> B_BLT<7> B_BLT<6> B_BLT<5> B_BLT<4> B_BLT<3> ++ B_BLT<2> B_BLT<1> B_BLT<0> B_BM_I B_DCLK_B_L B_DCLK_B_R B_DCLK_L B_DCLK_R ++ B_DR_O B_DW_I B_RCLK_B_L B_RCLK_B_R B_RCLK_L B_RCLK_R B_TIEH_O B_WCLK_B_L ++ B_WCLK_B_R B_WCLK_L B_WCLK_R VDD VSS +XB_I80 B_RCLK_B_L B_WCLK_B_L net041 VDD VSS / RSC_IHPSG13_AND2X2 +XA_I80 A_RCLK_B_L A_WCLK_B_L net21 VDD VSS / RSC_IHPSG13_AND2X2 +XB_I76 B_DI_N B_DO_WRITE_P B_WR_ZERO VDD VSS / RSC_IHPSG13_AND2X4 +XB_I75 B_DI_R B_DO_WRITE_P B_WR_ONE VDD VSS / RSC_IHPSG13_AND2X4 +XA_I76 A_DI_N A_DO_WRITE_P A_WR_ZERO VDD VSS / RSC_IHPSG13_AND2X4 +XA_I75 A_DI_R A_DO_WRITE_P A_WR_ONE VDD VSS / RSC_IHPSG13_AND2X4 +XI_FILL4<26> VDD VSS / RSC_IHPSG13_FILLCAP4 +XI_FILL4<25> VDD VSS / RSC_IHPSG13_FILLCAP4 +XI_FILL4<24> VDD VSS / RSC_IHPSG13_FILLCAP4 +XI_FILL4<23> VDD VSS / RSC_IHPSG13_FILLCAP4 +XI_FILL4<22> VDD VSS / RSC_IHPSG13_FILLCAP4 +XI_FILL4<21> VDD VSS / RSC_IHPSG13_FILLCAP4 +XI_FILL4<20> VDD VSS / RSC_IHPSG13_FILLCAP4 +XI_FILL4<19> VDD VSS / RSC_IHPSG13_FILLCAP4 +XI_FILL4<18> VDD VSS / RSC_IHPSG13_FILLCAP4 +XI_FILL4<17> VDD VSS / RSC_IHPSG13_FILLCAP4 +XI_FILL4<16> VDD VSS / RSC_IHPSG13_FILLCAP4 +XI_FILL4<15> VDD VSS / RSC_IHPSG13_FILLCAP4 +XI_FILL4<14> VDD VSS / RSC_IHPSG13_FILLCAP4 +XI_FILL4<13> VDD VSS / RSC_IHPSG13_FILLCAP4 +XI_FILL4<12> VDD VSS / RSC_IHPSG13_FILLCAP4 +XI_FILL4<11> VDD VSS / RSC_IHPSG13_FILLCAP4 +XI_FILL4<10> VDD VSS / RSC_IHPSG13_FILLCAP4 +XI_FILL4<9> VDD VSS / RSC_IHPSG13_FILLCAP4 +XI_FILL4<8> VDD VSS / RSC_IHPSG13_FILLCAP4 +XI_FILL4<7> VDD VSS / RSC_IHPSG13_FILLCAP4 +XI_FILL4<6> VDD VSS / RSC_IHPSG13_FILLCAP4 +XI_FILL4<5> VDD VSS / RSC_IHPSG13_FILLCAP4 +XI_FILL4<4> VDD VSS / RSC_IHPSG13_FILLCAP4 +XI_FILL4<3> VDD VSS / RSC_IHPSG13_FILLCAP4 +XI_FILL4<2> VDD VSS / RSC_IHPSG13_FILLCAP4 +XI_FILL4<1> VDD VSS / RSC_IHPSG13_FILLCAP4 +XB_I69 B_DCLK_L B_DCLK_B_L VDD VSS / RSC_IHPSG13_CINVX4 +XB_I50 B_WCLK_L B_WCLK_B_L VDD VSS / RSC_IHPSG13_CINVX4 +XB_EBUF B_RCLK_L B_RCLK_B_L VDD VSS / RSC_IHPSG13_CINVX4 +XB_INV<1> B_N0 B_P0 VDD VSS / RSC_IHPSG13_CINVX4 +XB_INV<0> B_ADDR_COL B_N0 VDD VSS / RSC_IHPSG13_CINVX4 +XA_I69 A_DCLK_L A_DCLK_B_L VDD VSS / RSC_IHPSG13_CINVX4 +XA_I50 A_WCLK_L A_WCLK_B_L VDD VSS / RSC_IHPSG13_CINVX4 +XA_EBUF A_RCLK_L A_RCLK_B_L VDD VSS / RSC_IHPSG13_CINVX4 +XA_INV<1> A_N0 A_P0 VDD VSS / RSC_IHPSG13_CINVX4 +XA_INV<0> A_ADDR_COL A_N0 VDD VSS / RSC_IHPSG13_CINVX4 +XB_I81<1> net041 B_PRE_N VDD VSS / RSC_IHPSG13_CINVX4_WN +XB_I81<0> net041 B_PRE_N VDD VSS / RSC_IHPSG13_CINVX4_WN +XA_I81<1> net21 A_PRE_N VDD VSS / RSC_IHPSG13_CINVX4_WN +XA_I81<0> net21 A_PRE_N VDD VSS / RSC_IHPSG13_CINVX4_WN +XA_R2 A_RCLK_L A_RCLK_R / RSC_IHPSG13_MET3RES +XA_I87 A_WCLK_L A_WCLK_R / RSC_IHPSG13_MET3RES +XA_I88 A_DCLK_L A_DCLK_R / RSC_IHPSG13_MET3RES +XA_I89 A_DCLK_B_L A_DCLK_B_R / RSC_IHPSG13_MET3RES +XA_I90 A_WCLK_B_L A_WCLK_B_R / RSC_IHPSG13_MET3RES +XA_I91 A_RCLK_B_L A_RCLK_B_R / RSC_IHPSG13_MET3RES +XB_R2 B_RCLK_L B_RCLK_R / RSC_IHPSG13_MET3RES +XB_I87 B_WCLK_L B_WCLK_R / RSC_IHPSG13_MET3RES +XB_I88 B_DCLK_L B_DCLK_R / RSC_IHPSG13_MET3RES +XB_I89 B_DCLK_B_L B_DCLK_B_R / RSC_IHPSG13_MET3RES +XB_I90 B_WCLK_B_L B_WCLK_B_R / RSC_IHPSG13_MET3RES +XB_I91 B_RCLK_B_L B_RCLK_B_R / RSC_IHPSG13_MET3RES +XA_ISENSE A_SAE A_BLC_SEL A_BLT_SEL net19 net20 VDD VSS / ++ RSC_IHPSG13_DFPQD_MSAFFX2 +XB_ISENSE B_SAE B_BLC_SEL B_BLT_SEL net037 net038 VDD VSS / ++ RSC_IHPSG13_DFPQD_MSAFFX2 +XAB_BLMUX<3> A_BLC<15> A_BLC<14> A_BLC<13> A_BLC<12> A_BLC_SEL A_BLT<15> ++ A_BLT<14> A_BLT<13> A_BLT<12> A_BLT_SEL A_PRE_N A_SEL_P<15> A_SEL_P<14> ++ A_SEL_P<13> A_SEL_P<12> A_WR_ONE A_WR_ZERO B_BLC<15> B_BLC<14> B_BLC<13> ++ B_BLC<12> B_BLC_SEL B_BLT<15> B_BLT<14> B_BLT<13> B_BLT<12> B_BLT_SEL ++ B_PRE_N B_SEL_P<15> B_SEL_P<14> B_SEL_P<13> B_SEL_P<12> B_WR_ONE B_WR_ZERO ++ VDD VSS / RM_IHPSG13_256x16_c2_2P_BLDRV +XAB_BLMUX<2> A_BLC<11> A_BLC<10> A_BLC<9> A_BLC<8> A_BLC_SEL A_BLT<11> ++ A_BLT<10> A_BLT<9> A_BLT<8> A_BLT_SEL A_PRE_N A_SEL_P<11> A_SEL_P<10> ++ A_SEL_P<9> A_SEL_P<8> A_WR_ONE A_WR_ZERO B_BLC<11> B_BLC<10> B_BLC<9> ++ B_BLC<8> B_BLC_SEL B_BLT<11> B_BLT<10> B_BLT<9> B_BLT<8> B_BLT_SEL B_PRE_N ++ B_SEL_P<11> B_SEL_P<10> B_SEL_P<9> B_SEL_P<8> B_WR_ONE B_WR_ZERO VDD ++ VSS / RM_IHPSG13_256x16_c2_2P_BLDRV +XAB_BLMUX<1> A_BLC<7> A_BLC<6> A_BLC<5> A_BLC<4> A_BLC_SEL A_BLT<7> A_BLT<6> ++ A_BLT<5> A_BLT<4> A_BLT_SEL A_PRE_N A_SEL_P<7> A_SEL_P<6> A_SEL_P<5> ++ A_SEL_P<4> A_WR_ONE A_WR_ZERO B_BLC<7> B_BLC<6> B_BLC<5> B_BLC<4> B_BLC_SEL ++ B_BLT<7> B_BLT<6> B_BLT<5> B_BLT<4> B_BLT_SEL B_PRE_N B_SEL_P<7> B_SEL_P<6> ++ B_SEL_P<5> B_SEL_P<4> B_WR_ONE B_WR_ZERO VDD VSS / ++ RM_IHPSG13_256x16_c2_2P_BLDRV +XAB_BLMUX<0> A_BLC<3> A_BLC<2> A_BLC<1> A_BLC<0> A_BLC_SEL A_BLT<3> A_BLT<2> ++ A_BLT<1> A_BLT<0> A_BLT_SEL A_PRE_N A_SEL_P<3> A_SEL_P<2> A_SEL_P<1> ++ A_SEL_P<0> A_WR_ONE A_WR_ZERO B_BLC<3> B_BLC<2> B_BLC<1> B_BLC<0> B_BLC_SEL ++ B_BLT<3> B_BLT<2> B_BLT<1> B_BLT<0> B_BLT_SEL B_PRE_N B_SEL_P<3> B_SEL_P<2> ++ B_SEL_P<1> B_SEL_P<0> B_WR_ONE B_WR_ZERO VDD VSS / ++ RM_IHPSG13_256x16_c2_2P_BLDRV +XA_I51 net19 A_DR_O VDD VSS / RSC_IHPSG13_INVX4 +XB_I51 net037 B_DR_O VDD VSS / RSC_IHPSG13_INVX4 +XA_I78 A_RCLK_B_L A_SAE VDD VSS / RSC_IHPSG13_CBUFX2 +XB_I78 B_RCLK_B_L B_SAE VDD VSS / RSC_IHPSG13_CBUFX2 +XA_DREG A_BIST_EN_I A_BIST_DW_I A_DCLK_B_L A_DW_I A_DI_R net22 VDD VSS ++ / RSC_IHPSG13_DFNQMX2IX1 +XB_DREG B_BIST_EN_I B_BIST_DW_I B_DCLK_B_L B_DW_I B_DI_R net046 VDD ++ VSS / RSC_IHPSG13_DFNQMX2IX1 +XB_BREG B_BIST_EN_I B_BIST_BM_I B_DCLK_B_L B_BM_I B_BM_R net045 VDD ++ VSS / RSC_IHPSG13_DFNQMX2IX1 +XA_BREG A_BIST_EN_I A_BIST_BM_I A_DCLK_B_L A_BM_I A_BM_R net24 VDD VSS ++ / RSC_IHPSG13_DFNQMX2IX1 +XA_DEC3INV<15> net23<0> A_SEL_P<15> VDD VSS / RSC_IHPSG13_INVX2 +XA_DEC3INV<14> net23<1> A_SEL_P<14> VDD VSS / RSC_IHPSG13_INVX2 +XA_DEC3INV<13> net23<2> A_SEL_P<13> VDD VSS / RSC_IHPSG13_INVX2 +XA_DEC3INV<12> net23<3> A_SEL_P<12> VDD VSS / RSC_IHPSG13_INVX2 +XA_DEC3INV<11> net23<4> A_SEL_P<11> VDD VSS / RSC_IHPSG13_INVX2 +XA_DEC3INV<10> net23<5> A_SEL_P<10> VDD VSS / RSC_IHPSG13_INVX2 +XA_DEC3INV<9> net23<6> A_SEL_P<9> VDD VSS / RSC_IHPSG13_INVX2 +XA_DEC3INV<8> net23<7> A_SEL_P<8> VDD VSS / RSC_IHPSG13_INVX2 +XA_DEC3INV<7> net23<8> A_SEL_P<7> VDD VSS / RSC_IHPSG13_INVX2 +XA_DEC3INV<6> net23<9> A_SEL_P<6> VDD VSS / RSC_IHPSG13_INVX2 +XA_DEC3INV<5> net23<10> A_SEL_P<5> VDD VSS / RSC_IHPSG13_INVX2 +XA_DEC3INV<4> net23<11> A_SEL_P<4> VDD VSS / RSC_IHPSG13_INVX2 +XA_DEC3INV<3> net23<12> A_SEL_P<3> VDD VSS / RSC_IHPSG13_INVX2 +XA_DEC3INV<2> net23<13> A_SEL_P<2> VDD VSS / RSC_IHPSG13_INVX2 +XA_DEC3INV<1> net23<14> A_SEL_P<1> VDD VSS / RSC_IHPSG13_INVX2 +XA_DEC3INV<0> net23<15> A_SEL_P<0> VDD VSS / RSC_IHPSG13_INVX2 +XA_I83 A_BM_R A_BM_N VDD VSS / RSC_IHPSG13_INVX2 +XA_I49 A_DI_R A_DI_N VDD VSS / RSC_IHPSG13_INVX2 +XB_DEC3INV<15> net044<0> B_SEL_P<15> VDD VSS / RSC_IHPSG13_INVX2 +XB_DEC3INV<14> net044<1> B_SEL_P<14> VDD VSS / RSC_IHPSG13_INVX2 +XB_DEC3INV<13> net044<2> B_SEL_P<13> VDD VSS / RSC_IHPSG13_INVX2 +XB_DEC3INV<12> net044<3> B_SEL_P<12> VDD VSS / RSC_IHPSG13_INVX2 +XB_DEC3INV<11> net044<4> B_SEL_P<11> VDD VSS / RSC_IHPSG13_INVX2 +XB_DEC3INV<10> net044<5> B_SEL_P<10> VDD VSS / RSC_IHPSG13_INVX2 +XB_DEC3INV<9> net044<6> B_SEL_P<9> VDD VSS / RSC_IHPSG13_INVX2 +XB_DEC3INV<8> net044<7> B_SEL_P<8> VDD VSS / RSC_IHPSG13_INVX2 +XB_DEC3INV<7> net044<8> B_SEL_P<7> VDD VSS / RSC_IHPSG13_INVX2 +XB_DEC3INV<6> net044<9> B_SEL_P<6> VDD VSS / RSC_IHPSG13_INVX2 +XB_DEC3INV<5> net044<10> B_SEL_P<5> VDD VSS / RSC_IHPSG13_INVX2 +XB_DEC3INV<4> net044<11> B_SEL_P<4> VDD VSS / RSC_IHPSG13_INVX2 +XB_DEC3INV<3> net044<12> B_SEL_P<3> VDD VSS / RSC_IHPSG13_INVX2 +XB_DEC3INV<2> net044<13> B_SEL_P<2> VDD VSS / RSC_IHPSG13_INVX2 +XB_DEC3INV<1> net044<14> B_SEL_P<1> VDD VSS / RSC_IHPSG13_INVX2 +XB_DEC3INV<0> net044<15> B_SEL_P<0> VDD VSS / RSC_IHPSG13_INVX2 +XB_I83 B_BM_R B_BM_N VDD VSS / RSC_IHPSG13_INVX2 +XB_I49 B_DI_R B_DI_N VDD VSS / RSC_IHPSG13_INVX2 +XI_FILL8<20> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI_FILL8<19> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI_FILL8<18> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI_FILL8<17> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI_FILL8<16> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI_FILL8<15> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI_FILL8<14> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI_FILL8<13> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI_FILL8<12> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI_FILL8<11> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI_FILL8<10> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI_FILL8<9> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI_FILL8<8> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI_FILL8<7> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI_FILL8<6> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI_FILL8<5> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI_FILL8<4> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI_FILL8<3> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI_FILL8<2> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI_FILL8<1> VDD VSS / RSC_IHPSG13_FILLCAP8 +XA_I44 A_BM_N A_WCLK_B_L A_DO_WRITE_P VDD VSS / RSC_IHPSG13_NOR2X2 +XB_I44 B_BM_N B_WCLK_B_L B_DO_WRITE_P VDD VSS / RSC_IHPSG13_NOR2X2 +XA_DEC3<15> A_P0 A_ADDR_DEC<7> net23<0> VDD VSS / RSC_IHPSG13_NAND2X2 +XA_DEC3<14> A_P0 A_ADDR_DEC<6> net23<1> VDD VSS / RSC_IHPSG13_NAND2X2 +XA_DEC3<13> A_P0 A_ADDR_DEC<5> net23<2> VDD VSS / RSC_IHPSG13_NAND2X2 +XA_DEC3<12> A_P0 A_ADDR_DEC<4> net23<3> VDD VSS / RSC_IHPSG13_NAND2X2 +XA_DEC3<11> A_P0 A_ADDR_DEC<3> net23<4> VDD VSS / RSC_IHPSG13_NAND2X2 +XA_DEC3<10> A_P0 A_ADDR_DEC<2> net23<5> VDD VSS / RSC_IHPSG13_NAND2X2 +XA_DEC3<9> A_P0 A_ADDR_DEC<1> net23<6> VDD VSS / RSC_IHPSG13_NAND2X2 +XA_DEC3<8> A_P0 A_ADDR_DEC<0> net23<7> VDD VSS / RSC_IHPSG13_NAND2X2 +XA_DEC3<7> A_N0 A_ADDR_DEC<7> net23<8> VDD VSS / RSC_IHPSG13_NAND2X2 +XA_DEC3<6> A_N0 A_ADDR_DEC<6> net23<9> VDD VSS / RSC_IHPSG13_NAND2X2 +XA_DEC3<5> A_N0 A_ADDR_DEC<5> net23<10> VDD VSS / RSC_IHPSG13_NAND2X2 +XA_DEC3<4> A_N0 A_ADDR_DEC<4> net23<11> VDD VSS / RSC_IHPSG13_NAND2X2 +XA_DEC3<3> A_N0 A_ADDR_DEC<3> net23<12> VDD VSS / RSC_IHPSG13_NAND2X2 +XA_DEC3<2> A_N0 A_ADDR_DEC<2> net23<13> VDD VSS / RSC_IHPSG13_NAND2X2 +XA_DEC3<1> A_N0 A_ADDR_DEC<1> net23<14> VDD VSS / RSC_IHPSG13_NAND2X2 +XA_DEC3<0> A_N0 A_ADDR_DEC<0> net23<15> VDD VSS / RSC_IHPSG13_NAND2X2 +XB_DEC3<15> B_P0 B_ADDR_DEC<7> net044<0> VDD VSS / RSC_IHPSG13_NAND2X2 +XB_DEC3<14> B_P0 B_ADDR_DEC<6> net044<1> VDD VSS / RSC_IHPSG13_NAND2X2 +XB_DEC3<13> B_P0 B_ADDR_DEC<5> net044<2> VDD VSS / RSC_IHPSG13_NAND2X2 +XB_DEC3<12> B_P0 B_ADDR_DEC<4> net044<3> VDD VSS / RSC_IHPSG13_NAND2X2 +XB_DEC3<11> B_P0 B_ADDR_DEC<3> net044<4> VDD VSS / RSC_IHPSG13_NAND2X2 +XB_DEC3<10> B_P0 B_ADDR_DEC<2> net044<5> VDD VSS / RSC_IHPSG13_NAND2X2 +XB_DEC3<9> B_P0 B_ADDR_DEC<1> net044<6> VDD VSS / RSC_IHPSG13_NAND2X2 +XB_DEC3<8> B_P0 B_ADDR_DEC<0> net044<7> VDD VSS / RSC_IHPSG13_NAND2X2 +XB_DEC3<7> B_N0 B_ADDR_DEC<7> net044<8> VDD VSS / RSC_IHPSG13_NAND2X2 +XB_DEC3<6> B_N0 B_ADDR_DEC<6> net044<9> VDD VSS / RSC_IHPSG13_NAND2X2 +XB_DEC3<5> B_N0 B_ADDR_DEC<5> net044<10> VDD VSS / RSC_IHPSG13_NAND2X2 +XB_DEC3<4> B_N0 B_ADDR_DEC<4> net044<11> VDD VSS / RSC_IHPSG13_NAND2X2 +XB_DEC3<3> B_N0 B_ADDR_DEC<3> net044<12> VDD VSS / RSC_IHPSG13_NAND2X2 +XB_DEC3<2> B_N0 B_ADDR_DEC<2> net044<13> VDD VSS / RSC_IHPSG13_NAND2X2 +XB_DEC3<1> B_N0 B_ADDR_DEC<1> net044<14> VDD VSS / RSC_IHPSG13_NAND2X2 +XB_DEC3<0> B_N0 B_ADDR_DEC<0> net044<15> VDD VSS / RSC_IHPSG13_NAND2X2 +XB_BM_TIEH B_TIEH_O VDD VSS / RSC_IHPSG13_TIEH +XA_BM_TIEH A_TIEH_O VDD VSS / RSC_IHPSG13_TIEH +.ENDS + + +.SUBCKT RM_IHPSG13_256x16_c2_2P_ROWDEC5 ADDR_N_I<4> ADDR_N_I<3> ADDR_N_I<2> ADDR_N_I<1> ++ ADDR_N_I<0> CS_I ECLK_I WL_O<31> WL_O<30> WL_O<29> WL_O<28> WL_O<27> ++ WL_O<26> WL_O<25> WL_O<24> WL_O<23> WL_O<22> WL_O<21> WL_O<20> WL_O<19> ++ WL_O<18> WL_O<17> WL_O<16> WL_O<15> WL_O<14> WL_O<13> WL_O<12> WL_O<11> ++ WL_O<10> WL_O<9> WL_O<8> WL_O<7> WL_O<6> WL_O<5> WL_O<4> WL_O<3> WL_O<2> ++ WL_O<1> WL_O<0> VDD VSS +XDEC00 ADDR_N_I<5> ADDR_N_I<4> CS_I CS00<0> VDD VSS / ++ RM_IHPSG13_256x16_c2_2P_DEC00 +XSEL<1> ADDR_N_I<3> ADDR_N_I<2> ADDR_N_I<1> ADDR_N_I<0> CS00<1> ECLK_H<1> ++ ECLK_H<2> ECLK_B<1> ECLK_B<2> WL_O<31> WL_O<30> WL_O<29> WL_O<28> WL_O<27> ++ WL_O<26> WL_O<25> WL_O<24> WL_O<23> WL_O<22> WL_O<21> WL_O<20> WL_O<19> ++ WL_O<18> WL_O<17> WL_O<16> VDD VSS / RM_IHPSG13_256x16_c2_2P_DEC04 +XSEL<0> ADDR_N_I<3> ADDR_N_I<2> ADDR_N_I<1> ADDR_N_I<0> CS00<0> ECLK_I ++ ECLK_H<1> ECLK_B<0> ECLK_B<1> WL_O<15> WL_O<14> WL_O<13> WL_O<12> WL_O<11> ++ WL_O<10> WL_O<9> WL_O<8> WL_O<7> WL_O<6> WL_O<5> WL_O<4> WL_O<3> WL_O<2> ++ WL_O<1> WL_O<0> VDD VSS / RM_IHPSG13_256x16_c2_2P_DEC04 +XDEC01 ADDR_N_I<5> ADDR_N_I<4> CS_I CS00<1> VDD VSS / ++ RM_IHPSG13_256x16_c2_2P_DEC01 +XL2<18> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<17> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<16> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<15> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<14> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<13> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<12> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<11> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<10> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<9> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<8> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<7> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<6> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<5> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<4> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<3> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<2> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<1> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI0 ADDR_N_I<5> VDD VSS / RSC_IHPSG13_TIEL +.ENDS +.SUBCKT RM_IHPSG13_256x16_c2_2P_ROWREG5 ACLK_N_I ADDR_I<4> ADDR_I<3> ADDR_I<2> ADDR_I<1> ++ ADDR_I<0> ADDR_N_O<4> ADDR_N_O<3> ADDR_N_O<2> ADDR_N_O<1> ADDR_N_O<0> ++ BIST_ADDR_I<4> BIST_ADDR_I<3> BIST_ADDR_I<2> BIST_ADDR_I<1> BIST_ADDR_I<0> ++ BIST_EN_I VDD VSS +XINV<4> q_int<4> qn_int<4> VDD VSS / RSC_IHPSG13_CINVX2 +XINV<3> q_int<3> qn_int<3> VDD VSS / RSC_IHPSG13_CINVX2 +XINV<2> q_int<2> qn_int<2> VDD VSS / RSC_IHPSG13_CINVX2 +XINV<1> q_int<1> qn_int<1> VDD VSS / RSC_IHPSG13_CINVX2 +XINV<0> q_int<0> qn_int<0> VDD VSS / RSC_IHPSG13_CINVX2 +XDRV<4> qn_int<4> ADDR_N_O<4> VDD VSS / RSC_IHPSG13_CINVX8 +XDRV<3> qn_int<3> ADDR_N_O<3> VDD VSS / RSC_IHPSG13_CINVX8 +XDRV<2> qn_int<2> ADDR_N_O<2> VDD VSS / RSC_IHPSG13_CINVX8 +XDRV<1> qn_int<1> ADDR_N_O<1> VDD VSS / RSC_IHPSG13_CINVX8 +XDRV<0> qn_int<0> ADDR_N_O<0> VDD VSS / RSC_IHPSG13_CINVX8 +XDFF<4> BIST_EN_I BIST_ADDR_I<4> ACLK_N_I ADDR_I<4> q_int<4> net2<0> VDD ++ VSS / RSC_IHPSG13_DFNQMX2IX1 +XDFF<3> BIST_EN_I BIST_ADDR_I<3> ACLK_N_I ADDR_I<3> q_int<3> net2<1> VDD ++ VSS / RSC_IHPSG13_DFNQMX2IX1 +XDFF<2> BIST_EN_I BIST_ADDR_I<2> ACLK_N_I ADDR_I<2> q_int<2> net2<2> VDD ++ VSS / RSC_IHPSG13_DFNQMX2IX1 +XDFF<1> BIST_EN_I BIST_ADDR_I<1> ACLK_N_I ADDR_I<1> q_int<1> net2<3> VDD ++ VSS / RSC_IHPSG13_DFNQMX2IX1 +XDFF<0> BIST_EN_I BIST_ADDR_I<0> ACLK_N_I ADDR_I<0> q_int<0> net2<4> VDD ++ VSS / RSC_IHPSG13_DFNQMX2IX1 +XI11<16> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI11<15> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI11<14> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI11<13> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI11<12> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI11<11> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI11<10> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI11<9> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI11<8> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI11<7> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI11<6> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI11<5> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI11<4> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI11<3> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI11<2> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI11<1> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI12<3> VDD VSS / RSC_IHPSG13_FILLCAP4 +XI12<2> VDD VSS / RSC_IHPSG13_FILLCAP4 +XI12<1> VDD VSS / RSC_IHPSG13_FILLCAP4 +XI12<0> VDD VSS / RSC_IHPSG13_FILLCAP4 +.ENDS + + +.SUBCKT RM_IHPSG13_256x16_c2_2P_COLDEC3 ACLK_N ADDR<2> ADDR<1> ADDR<0> ADDR_COL<1> ++ ADDR_COL<0> ADDR_DEC<7> ADDR_DEC<6> ADDR_DEC<5> ADDR_DEC<4> ADDR_DEC<3> ++ ADDR_DEC<2> ADDR_DEC<1> ADDR_DEC<0> BIST_ADDR<2> BIST_ADDR<1> BIST_ADDR<0> ++ BIST_EN_I VDD VSS +XI1<7> PADR<0> PADR<1> PADR<2> addr_n<7> VDD VSS / RSC_IHPSG13_NAND3X2 +XI1<6> NADR<0> PADR<1> PADR<2> addr_n<6> VDD VSS / RSC_IHPSG13_NAND3X2 +XI1<5> PADR<0> NADR<1> PADR<2> addr_n<5> VDD VSS / RSC_IHPSG13_NAND3X2 +XI1<4> NADR<0> NADR<1> PADR<2> addr_n<4> VDD VSS / RSC_IHPSG13_NAND3X2 +XI1<3> PADR<0> PADR<1> NADR<2> addr_n<3> VDD VSS / RSC_IHPSG13_NAND3X2 +XI1<2> NADR<0> PADR<1> NADR<2> addr_n<2> VDD VSS / RSC_IHPSG13_NAND3X2 +XI1<1> PADR<0> NADR<1> NADR<2> addr_n<1> VDD VSS / RSC_IHPSG13_NAND3X2 +XI1<0> NADR<0> NADR<1> NADR<2> addr_n<0> VDD VSS / RSC_IHPSG13_NAND3X2 +XDFF<2> BIST_EN_I BIST_ADDR<2> ACLK_N ADDR<2> padr_int<2> net13<0> VDD ++ VSS / RSC_IHPSG13_DFNQMX2IX1 +XDFF<1> BIST_EN_I BIST_ADDR<1> ACLK_N ADDR<1> padr_int<1> net13<1> VDD ++ VSS / RSC_IHPSG13_DFNQMX2IX1 +XDFF<0> BIST_EN_I BIST_ADDR<0> ACLK_N ADDR<0> padr_int<0> net13<2> VDD ++ VSS / RSC_IHPSG13_DFNQMX2IX1 +XI15<1> ADDR_COL<1> VDD VSS / RSC_IHPSG13_TIEL +XI15<0> ADDR_COL<0> VDD VSS / RSC_IHPSG13_TIEL +XI13<2> NADR<2> PADR<2> VDD VSS / RSC_IHPSG13_INVX2 +XI13<1> NADR<1> PADR<1> VDD VSS / RSC_IHPSG13_INVX2 +XI13<0> NADR<0> PADR<0> VDD VSS / RSC_IHPSG13_INVX2 +XI3<2> padr_int<2> NADR<2> VDD VSS / RSC_IHPSG13_INVX2 +XI3<1> padr_int<1> NADR<1> VDD VSS / RSC_IHPSG13_INVX2 +XI3<0> padr_int<0> NADR<0> VDD VSS / RSC_IHPSG13_INVX2 +XI2<7> addr_n<7> ADDR_DEC<7> VDD VSS / RSC_IHPSG13_INVX2 +XI2<6> addr_n<6> ADDR_DEC<6> VDD VSS / RSC_IHPSG13_INVX2 +XI2<5> addr_n<5> ADDR_DEC<5> VDD VSS / RSC_IHPSG13_INVX2 +XI2<4> addr_n<4> ADDR_DEC<4> VDD VSS / RSC_IHPSG13_INVX2 +XI2<3> addr_n<3> ADDR_DEC<3> VDD VSS / RSC_IHPSG13_INVX2 +XI2<2> addr_n<2> ADDR_DEC<2> VDD VSS / RSC_IHPSG13_INVX2 +XI2<1> addr_n<1> ADDR_DEC<1> VDD VSS / RSC_IHPSG13_INVX2 +XI2<0> addr_n<0> ADDR_DEC<0> VDD VSS / RSC_IHPSG13_INVX2 +XI17<4> VDD VSS / RSC_IHPSG13_FILLCAP4 +XI17<3> VDD VSS / RSC_IHPSG13_FILLCAP4 +XI17<2> VDD VSS / RSC_IHPSG13_FILLCAP4 +XI17<1> VDD VSS / RSC_IHPSG13_FILLCAP4 +XI16<11> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI16<10> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI16<9> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI16<8> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI16<7> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI16<6> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI16<5> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI16<4> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI16<3> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI16<2> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI16<1> VDD VSS / RSC_IHPSG13_FILLCAP8 +.ENDS +.SUBCKT RSC_IHPSG13_DFPQD_MSAFFX2P CP DN DP QN QP VDD VSS +XI_AMP CP DN DP QN QP VDD VSS / RSC_IHPSG13_DFPQD_MSAFFX2 +.ENDS +.SUBCKT RM_IHPSG13_256x16_c2_2P_COLCTRL3 A_ADDR_DEC<7> A_ADDR_DEC<6> A_ADDR_DEC<5> ++ A_ADDR_DEC<4> A_ADDR_DEC<3> A_ADDR_DEC<2> A_ADDR_DEC<1> A_ADDR_DEC<0> ++ A_BIST_BM_I A_BIST_DW_I A_BIST_EN_I A_BLC<7> A_BLC<6> A_BLC<5> A_BLC<4> ++ A_BLC<3> A_BLC<2> A_BLC<1> A_BLC<0> A_BLT<7> A_BLT<6> A_BLT<5> A_BLT<4> ++ A_BLT<3> A_BLT<2> A_BLT<1> A_BLT<0> A_BM_I A_DCLK_B_L A_DCLK_B_R A_DCLK_L ++ A_DCLK_R A_DR_O A_DW_I A_RCLK_B_L A_RCLK_B_R A_RCLK_L A_RCLK_R A_TIEH_O ++ A_WCLK_B_L A_WCLK_B_R A_WCLK_L A_WCLK_R B_ADDR_DEC<7> B_ADDR_DEC<6> ++ B_ADDR_DEC<5> B_ADDR_DEC<4> B_ADDR_DEC<3> B_ADDR_DEC<2> B_ADDR_DEC<1> ++ B_ADDR_DEC<0> B_BIST_BM_I B_BIST_DW_I B_BIST_EN_I B_BLC<7> B_BLC<6> B_BLC<5> ++ B_BLC<4> B_BLC<3> B_BLC<2> B_BLC<1> B_BLC<0> B_BLT<7> B_BLT<6> B_BLT<5> ++ B_BLT<4> B_BLT<3> B_BLT<2> B_BLT<1> B_BLT<0> B_BM_I B_DCLK_B_L B_DCLK_B_R ++ B_DCLK_L B_DCLK_R B_DR_O B_DW_I B_RCLK_B_L B_RCLK_B_R B_RCLK_L B_RCLK_R ++ B_TIEH_O B_WCLK_B_L B_WCLK_B_R B_WCLK_L B_WCLK_R VDD VSS +XB_DREG B_BIST_EN_I B_BIST_DW_I B_DCLK_B_L B_DW_I B_DI_R net044 VDD ++ VSS / RSC_IHPSG13_DFNQMX2IX1 +XB_BREG B_BIST_EN_I B_BIST_BM_I B_DCLK_B_L B_BM_I B_BM_R net043 VDD ++ VSS / RSC_IHPSG13_DFNQMX2IX1 +XA_DREG A_BIST_EN_I A_BIST_DW_I A_DCLK_B_L A_DW_I A_DI_R net22 VDD VSS ++ / RSC_IHPSG13_DFNQMX2IX1 +XA_BREG A_BIST_EN_I A_BIST_BM_I A_DCLK_B_L A_BM_I A_BM_R net23 VDD VSS ++ / RSC_IHPSG13_DFNQMX2IX1 +XI_FILL8<11> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI_FILL8<10> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI_FILL8<9> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI_FILL8<8> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI_FILL8<7> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI_FILL8<6> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI_FILL8<5> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI_FILL8<4> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI_FILL8<3> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI_FILL8<2> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI_FILL8<1> VDD VSS / RSC_IHPSG13_FILLCAP8 +XB_I51 net037 B_DR_O VDD VSS / RSC_IHPSG13_INVX4 +XA_I51 net19 A_DR_O VDD VSS / RSC_IHPSG13_INVX4 +XB_I44 B_BM_N B_WCLK_B_L B_DO_WRITE_P VDD VSS / RSC_IHPSG13_NOR2X2 +XA_I44 A_BM_N A_WCLK_B_L A_DO_WRITE_P VDD VSS / RSC_IHPSG13_NOR2X2 +XB_BM_TIEH B_TIEH_O VDD VSS / RSC_IHPSG13_TIEH +XA_BM_TIEH A_TIEH_O VDD VSS / RSC_IHPSG13_TIEH +XB_ISENSE B_SAE B_BLC_SEL B_BLT_SEL net037 net038 VDD VSS / ++ RSC_IHPSG13_DFPQD_MSAFFX2P +XA_ISENSE A_SAE A_BLC_SEL A_BLT_SEL net19 net20 VDD VSS / ++ RSC_IHPSG13_DFPQD_MSAFFX2P +XB_I49 B_DI_R B_DI_N VDD VSS / RSC_IHPSG13_INVX2 +XB_I83 B_BM_R B_BM_N VDD VSS / RSC_IHPSG13_INVX2 +XA_I49 A_DI_R A_DI_N VDD VSS / RSC_IHPSG13_INVX2 +XA_I83 A_BM_R A_BM_N VDD VSS / RSC_IHPSG13_INVX2 +XB_I69 B_DCLK_L B_DCLK_B_L VDD VSS / RSC_IHPSG13_CINVX2 +XB_I50 B_WCLK_L B_WCLK_B_L VDD VSS / RSC_IHPSG13_CINVX2 +XB_EBUF B_RCLK_L B_RCLK_B_L VDD VSS / RSC_IHPSG13_CINVX2 +XA_I69 A_DCLK_L A_DCLK_B_L VDD VSS / RSC_IHPSG13_CINVX2 +XA_I50 A_WCLK_L A_WCLK_B_L VDD VSS / RSC_IHPSG13_CINVX2 +XA_EBUF A_RCLK_L A_RCLK_B_L VDD VSS / RSC_IHPSG13_CINVX2 +XAB_BLMUX<1> A_BLC<7> A_BLC<6> A_BLC<5> A_BLC<4> A_BLC_SEL A_BLT<7> A_BLT<6> ++ A_BLT<5> A_BLT<4> A_BLT_SEL A_PRE_N A_ADDR_DEC<7> A_ADDR_DEC<6> ++ A_ADDR_DEC<5> A_ADDR_DEC<4> A_WR_ONE A_WR_ZERO B_BLC<7> B_BLC<6> B_BLC<5> ++ B_BLC<4> B_BLC_SEL B_BLT<7> B_BLT<6> B_BLT<5> B_BLT<4> B_BLT_SEL B_PRE_N ++ B_ADDR_DEC<7> B_ADDR_DEC<6> B_ADDR_DEC<5> B_ADDR_DEC<4> B_WR_ONE B_WR_ZERO ++ VDD VSS / RM_IHPSG13_256x16_c2_2P_BLDRV +XAB_BLMUX<0> A_BLC<3> A_BLC<2> A_BLC<1> A_BLC<0> A_BLC_SEL A_BLT<3> A_BLT<2> ++ A_BLT<1> A_BLT<0> A_BLT_SEL A_PRE_N A_ADDR_DEC<3> A_ADDR_DEC<2> ++ A_ADDR_DEC<1> A_ADDR_DEC<0> A_WR_ONE A_WR_ZERO B_BLC<3> B_BLC<2> B_BLC<1> ++ B_BLC<0> B_BLC_SEL B_BLT<3> B_BLT<2> B_BLT<1> B_BLT<0> B_BLT_SEL B_PRE_N ++ B_ADDR_DEC<3> B_ADDR_DEC<2> B_ADDR_DEC<1> B_ADDR_DEC<0> B_WR_ONE B_WR_ZERO ++ VDD VSS / RM_IHPSG13_256x16_c2_2P_BLDRV +XB_I78 B_RCLK_B_L B_SAE VDD VSS / RSC_IHPSG13_CBUFX2 +XA_I78 A_RCLK_B_L A_SAE VDD VSS / RSC_IHPSG13_CBUFX2 +XB_I88 B_DCLK_L B_DCLK_R / RSC_IHPSG13_MET3RES +XB_I87 B_WCLK_L B_WCLK_R / RSC_IHPSG13_MET3RES +XB_R2 B_RCLK_L B_RCLK_R / RSC_IHPSG13_MET3RES +XB_I91 B_RCLK_B_L B_RCLK_B_R / RSC_IHPSG13_MET3RES +XB_I90 B_WCLK_B_L B_WCLK_B_R / RSC_IHPSG13_MET3RES +XB_I89 B_DCLK_B_L B_DCLK_B_R / RSC_IHPSG13_MET3RES +XA_I88 A_DCLK_L A_DCLK_R / RSC_IHPSG13_MET3RES +XA_I87 A_WCLK_L A_WCLK_R / RSC_IHPSG13_MET3RES +XA_R2 A_RCLK_L A_RCLK_R / RSC_IHPSG13_MET3RES +XA_I91 A_RCLK_B_L A_RCLK_B_R / RSC_IHPSG13_MET3RES +XA_I90 A_WCLK_B_L A_WCLK_B_R / RSC_IHPSG13_MET3RES +XA_I89 A_DCLK_B_L A_DCLK_B_R / RSC_IHPSG13_MET3RES +XB_I80 B_WCLK_B_L B_RCLK_B_L net041 VDD VSS / RSC_IHPSG13_AND2X2 +XB_I76 B_DO_WRITE_P B_DI_N B_WR_ZERO VDD VSS / RSC_IHPSG13_AND2X2 +XB_I75 B_DO_WRITE_P B_DI_R B_WR_ONE VDD VSS / RSC_IHPSG13_AND2X2 +XA_I80 A_WCLK_B_L A_RCLK_B_L net21 VDD VSS / RSC_IHPSG13_AND2X2 +XA_I76 A_DI_N A_DO_WRITE_P A_WR_ZERO VDD VSS / RSC_IHPSG13_AND2X2 +XA_I75 A_DI_R A_DO_WRITE_P A_WR_ONE VDD VSS / RSC_IHPSG13_AND2X2 +XB_I81 net041 B_PRE_N VDD VSS / RSC_IHPSG13_CINVX4_WN +XA_I81 net21 A_PRE_N VDD VSS / RSC_IHPSG13_CINVX4_WN +XI_FILL4<10> VDD VSS / RSC_IHPSG13_FILLCAP4 +XI_FILL4<9> VDD VSS / RSC_IHPSG13_FILLCAP4 +XI_FILL4<8> VDD VSS / RSC_IHPSG13_FILLCAP4 +XI_FILL4<7> VDD VSS / RSC_IHPSG13_FILLCAP4 +XI_FILL4<6> VDD VSS / RSC_IHPSG13_FILLCAP4 +XI_FILL4<5> VDD VSS / RSC_IHPSG13_FILLCAP4 +XI_FILL4<4> VDD VSS / RSC_IHPSG13_FILLCAP4 +XI_FILL4<3> VDD VSS / RSC_IHPSG13_FILLCAP4 +XI_FILL4<2> VDD VSS / RSC_IHPSG13_FILLCAP4 +XI_FILL4<1> VDD VSS / RSC_IHPSG13_FILLCAP4 +.ENDS + +.SUBCKT RM_IHPSG13_256x16_c2_2P_ROWDEC6 ADDR_N_I<5> ADDR_N_I<4> ADDR_N_I<3> ADDR_N_I<2> ++ ADDR_N_I<1> ADDR_N_I<0> CS_I ECLK_I WL_O<63> WL_O<62> WL_O<61> WL_O<60> ++ WL_O<59> WL_O<58> WL_O<57> WL_O<56> WL_O<55> WL_O<54> WL_O<53> WL_O<52> ++ WL_O<51> WL_O<50> WL_O<49> WL_O<48> WL_O<47> WL_O<46> WL_O<45> WL_O<44> ++ WL_O<43> WL_O<42> WL_O<41> WL_O<40> WL_O<39> WL_O<38> WL_O<37> WL_O<36> ++ WL_O<35> WL_O<34> WL_O<33> WL_O<32> WL_O<31> WL_O<30> WL_O<29> WL_O<28> ++ WL_O<27> WL_O<26> WL_O<25> WL_O<24> WL_O<23> WL_O<22> WL_O<21> WL_O<20> ++ WL_O<19> WL_O<18> WL_O<17> WL_O<16> WL_O<15> WL_O<14> WL_O<13> WL_O<12> ++ WL_O<11> WL_O<10> WL_O<9> WL_O<8> WL_O<7> WL_O<6> WL_O<5> WL_O<4> WL_O<3> ++ WL_O<2> WL_O<1> WL_O<0> VDD VSS +XDEC10 ADDR_N_I<5> ADDR_N_I<4> CS_I CS00<2> VDD VSS / ++ RM_IHPSG13_256x16_c2_2P_DEC02 +XDEC00 ADDR_N_I<5> ADDR_N_I<4> CS_I CS00<0> VDD VSS / ++ RM_IHPSG13_256x16_c2_2P_DEC00 +XSEL<3> ADDR_N_I<3> ADDR_N_I<2> ADDR_N_I<1> ADDR_N_I<0> CS00<3> ECLK_H<3> ++ ECLK_H<4> ECLK_B<3> ECLK_B<4> WL_O<63> WL_O<62> WL_O<61> WL_O<60> WL_O<59> ++ WL_O<58> WL_O<57> WL_O<56> WL_O<55> WL_O<54> WL_O<53> WL_O<52> WL_O<51> ++ WL_O<50> WL_O<49> WL_O<48> VDD VSS / RM_IHPSG13_256x16_c2_2P_DEC04 +XSEL<2> ADDR_N_I<3> ADDR_N_I<2> ADDR_N_I<1> ADDR_N_I<0> CS00<2> ECLK_H<2> ++ ECLK_H<3> ECLK_B<2> ECLK_B<3> WL_O<47> WL_O<46> WL_O<45> WL_O<44> WL_O<43> ++ WL_O<42> WL_O<41> WL_O<40> WL_O<39> WL_O<38> WL_O<37> WL_O<36> WL_O<35> ++ WL_O<34> WL_O<33> WL_O<32> VDD VSS / RM_IHPSG13_256x16_c2_2P_DEC04 +XSEL<1> ADDR_N_I<3> ADDR_N_I<2> ADDR_N_I<1> ADDR_N_I<0> CS00<1> ECLK_H<1> ++ ECLK_H<2> ECLK_B<1> ECLK_B<2> WL_O<31> WL_O<30> WL_O<29> WL_O<28> WL_O<27> ++ WL_O<26> WL_O<25> WL_O<24> WL_O<23> WL_O<22> WL_O<21> WL_O<20> WL_O<19> ++ WL_O<18> WL_O<17> WL_O<16> VDD VSS / RM_IHPSG13_256x16_c2_2P_DEC04 +XSEL<0> ADDR_N_I<3> ADDR_N_I<2> ADDR_N_I<1> ADDR_N_I<0> CS00<0> ECLK_I ++ ECLK_H<1> ECLK_B<0> ECLK_B<1> WL_O<15> WL_O<14> WL_O<13> WL_O<12> WL_O<11> ++ WL_O<10> WL_O<9> WL_O<8> WL_O<7> WL_O<6> WL_O<5> WL_O<4> WL_O<3> WL_O<2> ++ WL_O<1> WL_O<0> VDD VSS / RM_IHPSG13_256x16_c2_2P_DEC04 +XDEC11 ADDR_N_I<5> ADDR_N_I<4> CS_I CS00<3> VDD VSS / ++ RM_IHPSG13_256x16_c2_2P_DEC03 +XL2<36> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<35> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<34> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<33> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<32> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<31> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<30> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<29> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<28> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<27> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<26> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<25> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<24> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<23> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<22> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<21> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<20> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<19> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<18> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<17> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<16> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<15> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<14> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<13> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<12> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<11> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<10> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<9> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<8> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<7> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<6> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<5> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<4> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<3> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<2> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<1> VDD VSS / RSC_IHPSG13_FILLCAP8 +XDEC01 ADDR_N_I<5> ADDR_N_I<4> CS_I CS00<1> VDD VSS / ++ RM_IHPSG13_256x16_c2_2P_DEC01 +.ENDS +.SUBCKT RM_IHPSG13_256x16_c2_2P_ROWREG6 ACLK_N_I ADDR_I<5> ADDR_I<4> ADDR_I<3> ADDR_I<2> ++ ADDR_I<1> ADDR_I<0> ADDR_N_O<5> ADDR_N_O<4> ADDR_N_O<3> ADDR_N_O<2> ++ ADDR_N_O<1> ADDR_N_O<0> BIST_ADDR_I<5> BIST_ADDR_I<4> BIST_ADDR_I<3> ++ BIST_ADDR_I<2> BIST_ADDR_I<1> BIST_ADDR_I<0> BIST_EN_I VDD VSS +XINV<5> q_int<5> qn_int<5> VDD VSS / RSC_IHPSG13_CINVX2 +XINV<4> q_int<4> qn_int<4> VDD VSS / RSC_IHPSG13_CINVX2 +XINV<3> q_int<3> qn_int<3> VDD VSS / RSC_IHPSG13_CINVX2 +XINV<2> q_int<2> qn_int<2> VDD VSS / RSC_IHPSG13_CINVX2 +XINV<1> q_int<1> qn_int<1> VDD VSS / RSC_IHPSG13_CINVX2 +XINV<0> q_int<0> qn_int<0> VDD VSS / RSC_IHPSG13_CINVX2 +XDRV<5> qn_int<5> ADDR_N_O<5> VDD VSS / RSC_IHPSG13_CINVX8 +XDRV<4> qn_int<4> ADDR_N_O<4> VDD VSS / RSC_IHPSG13_CINVX8 +XDRV<3> qn_int<3> ADDR_N_O<3> VDD VSS / RSC_IHPSG13_CINVX8 +XDRV<2> qn_int<2> ADDR_N_O<2> VDD VSS / RSC_IHPSG13_CINVX8 +XDRV<1> qn_int<1> ADDR_N_O<1> VDD VSS / RSC_IHPSG13_CINVX8 +XDRV<0> qn_int<0> ADDR_N_O<0> VDD VSS / RSC_IHPSG13_CINVX8 +XDFF<5> BIST_EN_I BIST_ADDR_I<5> ACLK_N_I ADDR_I<5> q_int<5> net2<0> VDD ++ VSS / RSC_IHPSG13_DFNQMX2IX1 +XDFF<4> BIST_EN_I BIST_ADDR_I<4> ACLK_N_I ADDR_I<4> q_int<4> net2<1> VDD ++ VSS / RSC_IHPSG13_DFNQMX2IX1 +XDFF<3> BIST_EN_I BIST_ADDR_I<3> ACLK_N_I ADDR_I<3> q_int<3> net2<2> VDD ++ VSS / RSC_IHPSG13_DFNQMX2IX1 +XDFF<2> BIST_EN_I BIST_ADDR_I<2> ACLK_N_I ADDR_I<2> q_int<2> net2<3> VDD ++ VSS / RSC_IHPSG13_DFNQMX2IX1 +XDFF<1> BIST_EN_I BIST_ADDR_I<1> ACLK_N_I ADDR_I<1> q_int<1> net2<4> VDD ++ VSS / RSC_IHPSG13_DFNQMX2IX1 +XDFF<0> BIST_EN_I BIST_ADDR_I<0> ACLK_N_I ADDR_I<0> q_int<0> net2<5> VDD ++ VSS / RSC_IHPSG13_DFNQMX2IX1 +XI11<12> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI11<11> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI11<10> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI11<9> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI11<8> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI11<7> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI11<6> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI11<5> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI11<4> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI11<3> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI11<2> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI11<1> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI12<2> VDD VSS / RSC_IHPSG13_FILLCAP4 +XI12<1> VDD VSS / RSC_IHPSG13_FILLCAP4 +XI12<0> VDD VSS / RSC_IHPSG13_FILLCAP4 +.ENDS + +.SUBCKT RM_IHPSG13_256x16_c2_2P_COLDRV13X16 ADDR_COL_I<1> ADDR_COL_I<0> ADDR_COL_O<1> ++ ADDR_COL_O<0> ADDR_DEC_I<7> ADDR_DEC_I<6> ADDR_DEC_I<5> ADDR_DEC_I<4> ++ ADDR_DEC_I<3> ADDR_DEC_I<2> ADDR_DEC_I<1> ADDR_DEC_I<0> ADDR_DEC_O<7> ++ ADDR_DEC_O<6> ADDR_DEC_O<5> ADDR_DEC_O<4> ADDR_DEC_O<3> ADDR_DEC_O<2> ++ ADDR_DEC_O<1> ADDR_DEC_O<0> DCLK_I DCLK_O RCLK_I RCLK_O WCLK_I WCLK_O ++ VDD VSS +XI0<7> VDD VSS / RSC_IHPSG13_FILLCAP4 +XI0<6> VDD VSS / RSC_IHPSG13_FILLCAP4 +XI0<5> VDD VSS / RSC_IHPSG13_FILLCAP4 +XI0<4> VDD VSS / RSC_IHPSG13_FILLCAP4 +XI0<3> VDD VSS / RSC_IHPSG13_FILLCAP4 +XI0<2> VDD VSS / RSC_IHPSG13_FILLCAP4 +XI0<1> VDD VSS / RSC_IHPSG13_FILLCAP4 +XWCLK_DRV WCLK_I WCLK_O VDD VSS / RSC_IHPSG13_CBUFX16 +XRCLK_DRV RCLK_I RCLK_O VDD VSS / RSC_IHPSG13_CBUFX16 +XDCLK_DRV DCLK_I DCLK_O VDD VSS / RSC_IHPSG13_CBUFX16 +XADDR_COL_DRV<1> ADDR_COL_I<1> ADDR_COL_O<1> VDD VSS / ++ RSC_IHPSG13_CBUFX16 +XADDR_COL_DRV<0> ADDR_COL_I<0> ADDR_COL_O<0> VDD VSS / ++ RSC_IHPSG13_CBUFX16 +XADDR_DEC_DRV<7> ADDR_DEC_I<7> ADDR_DEC_O<7> VDD VSS / ++ RSC_IHPSG13_CBUFX16 +XADDR_DEC_DRV<6> ADDR_DEC_I<6> ADDR_DEC_O<6> VDD VSS / ++ RSC_IHPSG13_CBUFX16 +XADDR_DEC_DRV<5> ADDR_DEC_I<5> ADDR_DEC_O<5> VDD VSS / ++ RSC_IHPSG13_CBUFX16 +XADDR_DEC_DRV<4> ADDR_DEC_I<4> ADDR_DEC_O<4> VDD VSS / ++ RSC_IHPSG13_CBUFX16 +XADDR_DEC_DRV<3> ADDR_DEC_I<3> ADDR_DEC_O<3> VDD VSS / ++ RSC_IHPSG13_CBUFX16 +XADDR_DEC_DRV<2> ADDR_DEC_I<2> ADDR_DEC_O<2> VDD VSS / ++ RSC_IHPSG13_CBUFX16 +XADDR_DEC_DRV<1> ADDR_DEC_I<1> ADDR_DEC_O<1> VDD VSS / ++ RSC_IHPSG13_CBUFX16 +XADDR_DEC_DRV<0> ADDR_DEC_I<0> ADDR_DEC_O<0> VDD VSS / ++ RSC_IHPSG13_CBUFX16 +XI1<5> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI1<4> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI1<3> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI1<2> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI1<1> VDD VSS / RSC_IHPSG13_FILLCAP8 +.ENDS +.SUBCKT RM_IHPSG13_256x16_c2_2P_WLDRV16X16 A<15> A<14> A<13> A<12> A<11> A<10> A<9> A<8> ++ A<7> A<6> A<5> A<4> A<3> A<2> A<1> A<0> Z<15> Z<14> Z<13> Z<12> Z<11> Z<10> ++ Z<9> Z<8> Z<7> Z<6> Z<5> Z<4> Z<3> Z<2> Z<1> Z<0> VDD VSS +XBUF<15> A<15> Z<15> VDD VSS / RSC_IHPSG13_WLDRVX16 +XBUF<14> A<14> Z<14> VDD VSS / RSC_IHPSG13_WLDRVX16 +XBUF<13> A<13> Z<13> VDD VSS / RSC_IHPSG13_WLDRVX16 +XBUF<12> A<12> Z<12> VDD VSS / RSC_IHPSG13_WLDRVX16 +XBUF<11> A<11> Z<11> VDD VSS / RSC_IHPSG13_WLDRVX16 +XBUF<10> A<10> Z<10> VDD VSS / RSC_IHPSG13_WLDRVX16 +XBUF<9> A<9> Z<9> VDD VSS / RSC_IHPSG13_WLDRVX16 +XBUF<8> A<8> Z<8> VDD VSS / RSC_IHPSG13_WLDRVX16 +XBUF<7> A<7> Z<7> VDD VSS / RSC_IHPSG13_WLDRVX16 +XBUF<6> A<6> Z<6> VDD VSS / RSC_IHPSG13_WLDRVX16 +XBUF<5> A<5> Z<5> VDD VSS / RSC_IHPSG13_WLDRVX16 +XBUF<4> A<4> Z<4> VDD VSS / RSC_IHPSG13_WLDRVX16 +XBUF<3> A<3> Z<3> VDD VSS / RSC_IHPSG13_WLDRVX16 +XBUF<2> A<2> Z<2> VDD VSS / RSC_IHPSG13_WLDRVX16 +XBUF<1> A<1> Z<1> VDD VSS / RSC_IHPSG13_WLDRVX16 +XBUF<0> A<0> Z<0> VDD VSS / RSC_IHPSG13_WLDRVX16 +.ENDS + + +.SUBCKT RM_IHPSG13_256x16_c2_1P_DEC01 ADDR<1> ADDR<0> CS CS_OUT VDD VSS +XDECINV net1 CS_OUT VDD VSS / RSC_IHPSG13_INVX4 +XDEC NADDR<1> ADDR<0> CS net1 VDD VSS / RSC_IHPSG13_NAND3X2 +XI2 VDD VSS / RSC_IHPSG13_FILLCAP4 +XADDRINV ADDR<1> NADDR<1> VDD VSS / RSC_IHPSG13_INVX2 +.ENDS +.SUBCKT RM_IHPSG13_256x16_c2_1P_DEC00 ADDR<1> ADDR<0> CS CS_OUT VDD VSS +XDECINV net1 CS_OUT VDD VSS / RSC_IHPSG13_INVX4 +XDEC NADDR<1> NADDR<0> CS net1 VDD VSS / RSC_IHPSG13_NAND3X2 +XADDRINV<1> ADDR<1> NADDR<1> VDD VSS / RSC_IHPSG13_INVX2 +XADDRINV<0> ADDR<0> NADDR<0> VDD VSS / RSC_IHPSG13_INVX2 +XI1 VDD VSS / RSC_IHPSG13_FILLCAP4 +.ENDS +.SUBCKT RM_IHPSG13_256x16_c2_1P_ROWDEC5 ADDR_N_I<4> ADDR_N_I<3> ADDR_N_I<2> ADDR_N_I<1> ++ ADDR_N_I<0> CS_I ECLK_I WL_O<31> WL_O<30> WL_O<29> WL_O<28> WL_O<27> ++ WL_O<26> WL_O<25> WL_O<24> WL_O<23> WL_O<22> WL_O<21> WL_O<20> WL_O<19> ++ WL_O<18> WL_O<17> WL_O<16> WL_O<15> WL_O<14> WL_O<13> WL_O<12> WL_O<11> ++ WL_O<10> WL_O<9> WL_O<8> WL_O<7> WL_O<6> WL_O<5> WL_O<4> WL_O<3> WL_O<2> ++ WL_O<1> WL_O<0> VDD VSS +XL2<12> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<11> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<10> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<9> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<8> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<7> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<6> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<5> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<4> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<3> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<2> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<1> VDD VSS / RSC_IHPSG13_FILLCAP8 +XDEC01 ADDR_N_I<5> ADDR_N_I<4> CS_I CS00<1> VDD VSS / ++ RM_IHPSG13_256x16_c2_1P_DEC01 +XDEC00 ADDR_N_I<5> ADDR_N_I<4> CS_I CS00<0> VDD VSS / ++ RM_IHPSG13_256x16_c2_1P_DEC00 +XSEL<1> ADDR_N_I<3> ADDR_N_I<2> ADDR_N_I<1> ADDR_N_I<0> CS00<1> ECLK_H<1> ++ ECLK_H<2> ECLK_B<1> ECLK_B<2> WL_O<31> WL_O<30> WL_O<29> WL_O<28> WL_O<27> ++ WL_O<26> WL_O<25> WL_O<24> WL_O<23> WL_O<22> WL_O<21> WL_O<20> WL_O<19> ++ WL_O<18> WL_O<17> WL_O<16> VDD VSS / RM_IHPSG13_256x16_c2_1P_DEC04 +XSEL<0> ADDR_N_I<3> ADDR_N_I<2> ADDR_N_I<1> ADDR_N_I<0> CS00<0> ECLK_I ++ ECLK_H<1> ECLK_B<0> ECLK_B<1> WL_O<15> WL_O<14> WL_O<13> WL_O<12> WL_O<11> ++ WL_O<10> WL_O<9> WL_O<8> WL_O<7> WL_O<6> WL_O<5> WL_O<4> WL_O<3> WL_O<2> ++ WL_O<1> WL_O<0> VDD VSS / RM_IHPSG13_256x16_c2_1P_DEC04 +XI0 ADDR_N_I<5> VDD VSS / RSC_IHPSG13_TIEL +.ENDS +.SUBCKT RM_IHPSG13_256x16_c2_1P_ROWREG5 ACLK_N_I ADDR_I<4> ADDR_I<3> ADDR_I<2> ADDR_I<1> ++ ADDR_I<0> ADDR_N_O<4> ADDR_N_O<3> ADDR_N_O<2> ADDR_N_O<1> ADDR_N_O<0> ++ BIST_ADDR_I<4> BIST_ADDR_I<3> BIST_ADDR_I<2> BIST_ADDR_I<1> BIST_ADDR_I<0> ++ BIST_EN_I VDD VSS +XINV<4> q_int<4> qn_int<4> VDD VSS / RSC_IHPSG13_CINVX2 +XINV<3> q_int<3> qn_int<3> VDD VSS / RSC_IHPSG13_CINVX2 +XINV<2> q_int<2> qn_int<2> VDD VSS / RSC_IHPSG13_CINVX2 +XINV<1> q_int<1> qn_int<1> VDD VSS / RSC_IHPSG13_CINVX2 +XINV<0> q_int<0> qn_int<0> VDD VSS / RSC_IHPSG13_CINVX2 +XDRV<4> qn_int<4> ADDR_N_O<4> VDD VSS / RSC_IHPSG13_CINVX8 +XDRV<3> qn_int<3> ADDR_N_O<3> VDD VSS / RSC_IHPSG13_CINVX8 +XDRV<2> qn_int<2> ADDR_N_O<2> VDD VSS / RSC_IHPSG13_CINVX8 +XDRV<1> qn_int<1> ADDR_N_O<1> VDD VSS / RSC_IHPSG13_CINVX8 +XDRV<0> qn_int<0> ADDR_N_O<0> VDD VSS / RSC_IHPSG13_CINVX8 +XDFF<4> BIST_EN_I BIST_ADDR_I<4> ACLK_N_I ADDR_I<4> q_int<4> net2<0> VDD ++ VSS / RSC_IHPSG13_DFNQMX2IX1 +XDFF<3> BIST_EN_I BIST_ADDR_I<3> ACLK_N_I ADDR_I<3> q_int<3> net2<1> VDD ++ VSS / RSC_IHPSG13_DFNQMX2IX1 +XDFF<2> BIST_EN_I BIST_ADDR_I<2> ACLK_N_I ADDR_I<2> q_int<2> net2<2> VDD ++ VSS / RSC_IHPSG13_DFNQMX2IX1 +XDFF<1> BIST_EN_I BIST_ADDR_I<1> ACLK_N_I ADDR_I<1> q_int<1> net2<3> VDD ++ VSS / RSC_IHPSG13_DFNQMX2IX1 +XDFF<0> BIST_EN_I BIST_ADDR_I<0> ACLK_N_I ADDR_I<0> q_int<0> net2<4> VDD ++ VSS / RSC_IHPSG13_DFNQMX2IX1 +XI11<16> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI11<15> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI11<14> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI11<13> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI11<12> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI11<11> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI11<10> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI11<9> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI11<8> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI11<7> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI11<6> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI11<5> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI11<4> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI11<3> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI11<2> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI11<1> VDD VSS / RSC_IHPSG13_FILLCAP8 +.ENDS + + +.SUBCKT RM_IHPSG13_256x16_c2_1P_COLDEC5 ACLK_N ADDR<4> ADDR<3> ADDR<2> ADDR<1> ADDR<0> ++ ADDR_COL<1> ADDR_COL<0> ADDR_DEC<7> ADDR_DEC<6> ADDR_DEC<5> ADDR_DEC<4> ++ ADDR_DEC<3> ADDR_DEC<2> ADDR_DEC<1> ADDR_DEC<0> BIST_ADDR<4> BIST_ADDR<3> ++ BIST_ADDR<2> BIST_ADDR<1> BIST_ADDR<0> BIST_EN_I VDD VSS +XI17<2> VDD VSS / RSC_IHPSG13_FILLCAP4 +XI17<1> VDD VSS / RSC_IHPSG13_FILLCAP4 +XI13<1> addr_int<1> ADDR_COL<1> VDD VSS / RSC_IHPSG13_CBUFX2 +XI13<0> addr_int<0> ADDR_COL<0> VDD VSS / RSC_IHPSG13_CBUFX2 +XDFF<4> BIST_EN_I BIST_ADDR<4> ACLK_N ADDR<4> addr_int<1> net7<0> VDD ++ VSS / RSC_IHPSG13_DFNQMX2IX1 +XDFF<3> BIST_EN_I BIST_ADDR<3> ACLK_N ADDR<3> addr_int<0> net7<1> VDD ++ VSS / RSC_IHPSG13_DFNQMX2IX1 +XDFF<2> BIST_EN_I BIST_ADDR<2> ACLK_N ADDR<2> padr_int<2> net7<2> VDD ++ VSS / RSC_IHPSG13_DFNQMX2IX1 +XDFF<1> BIST_EN_I BIST_ADDR<1> ACLK_N ADDR<1> padr_int<1> net7<3> VDD ++ VSS / RSC_IHPSG13_DFNQMX2IX1 +XDFF<0> BIST_EN_I BIST_ADDR<0> ACLK_N ADDR<0> padr_int<0> net7<4> VDD ++ VSS / RSC_IHPSG13_DFNQMX2IX1 +XI1<7> PADR<0> PADR<1> PADR<2> addr_n<7> VDD VSS / RSC_IHPSG13_NAND3X2 +XI1<6> NADR<0> PADR<1> PADR<2> addr_n<6> VDD VSS / RSC_IHPSG13_NAND3X2 +XI1<5> PADR<0> NADR<1> PADR<2> addr_n<5> VDD VSS / RSC_IHPSG13_NAND3X2 +XI1<4> NADR<0> NADR<1> PADR<2> addr_n<4> VDD VSS / RSC_IHPSG13_NAND3X2 +XI1<3> PADR<0> PADR<1> NADR<2> addr_n<3> VDD VSS / RSC_IHPSG13_NAND3X2 +XI1<2> NADR<0> PADR<1> NADR<2> addr_n<2> VDD VSS / RSC_IHPSG13_NAND3X2 +XI1<1> PADR<0> NADR<1> NADR<2> addr_n<1> VDD VSS / RSC_IHPSG13_NAND3X2 +XI1<0> NADR<0> NADR<1> NADR<2> addr_n<0> VDD VSS / RSC_IHPSG13_NAND3X2 +XI15<2> NADR<2> PADR<2> VDD VSS / RSC_IHPSG13_INVX2 +XI15<1> NADR<1> PADR<1> VDD VSS / RSC_IHPSG13_INVX2 +XI15<0> NADR<0> PADR<0> VDD VSS / RSC_IHPSG13_INVX2 +XI3<2> padr_int<2> NADR<2> VDD VSS / RSC_IHPSG13_INVX2 +XI3<1> padr_int<1> NADR<1> VDD VSS / RSC_IHPSG13_INVX2 +XI3<0> padr_int<0> NADR<0> VDD VSS / RSC_IHPSG13_INVX2 +XI2<7> addr_n<7> ADDR_DEC<7> VDD VSS / RSC_IHPSG13_INVX2 +XI2<6> addr_n<6> ADDR_DEC<6> VDD VSS / RSC_IHPSG13_INVX2 +XI2<5> addr_n<5> ADDR_DEC<5> VDD VSS / RSC_IHPSG13_INVX2 +XI2<4> addr_n<4> ADDR_DEC<4> VDD VSS / RSC_IHPSG13_INVX2 +XI2<3> addr_n<3> ADDR_DEC<3> VDD VSS / RSC_IHPSG13_INVX2 +XI2<2> addr_n<2> ADDR_DEC<2> VDD VSS / RSC_IHPSG13_INVX2 +XI2<1> addr_n<1> ADDR_DEC<1> VDD VSS / RSC_IHPSG13_INVX2 +XI2<0> addr_n<0> ADDR_DEC<0> VDD VSS / RSC_IHPSG13_INVX2 +.ENDS +.SUBCKT RM_IHPSG13_256x16_c2_1P_COLCTRL5 A_ADDR_COL<1> A_ADDR_COL<0> A_ADDR_DEC<7> ++ A_ADDR_DEC<6> A_ADDR_DEC<5> A_ADDR_DEC<4> A_ADDR_DEC<3> A_ADDR_DEC<2> ++ A_ADDR_DEC<1> A_ADDR_DEC<0> A_BIST_BM_I A_BIST_DW_I A_BIST_EN_I A_BLC<31> ++ A_BLC<30> A_BLC<29> A_BLC<28> A_BLC<27> A_BLC<26> A_BLC<25> A_BLC<24> ++ A_BLC<23> A_BLC<22> A_BLC<21> A_BLC<20> A_BLC<19> A_BLC<18> A_BLC<17> ++ A_BLC<16> A_BLC<15> A_BLC<14> A_BLC<13> A_BLC<12> A_BLC<11> A_BLC<10> ++ A_BLC<9> A_BLC<8> A_BLC<7> A_BLC<6> A_BLC<5> A_BLC<4> A_BLC<3> A_BLC<2> ++ A_BLC<1> A_BLC<0> A_BLT<31> A_BLT<30> A_BLT<29> A_BLT<28> A_BLT<27> ++ A_BLT<26> A_BLT<25> A_BLT<24> A_BLT<23> A_BLT<22> A_BLT<21> A_BLT<20> ++ A_BLT<19> A_BLT<18> A_BLT<17> A_BLT<16> A_BLT<15> A_BLT<14> A_BLT<13> ++ A_BLT<12> A_BLT<11> A_BLT<10> A_BLT<9> A_BLT<8> A_BLT<7> A_BLT<6> A_BLT<5> ++ A_BLT<4> A_BLT<3> A_BLT<2> A_BLT<1> A_BLT<0> A_BM_I A_DCLK_B_L A_DCLK_B_R ++ A_DCLK_L A_DCLK_R A_DR_O A_DW_I A_RCLK_B_L A_RCLK_B_R A_RCLK_L A_RCLK_R ++ A_TIEH_O A_WCLK_B_L A_WCLK_B_R A_WCLK_L A_WCLK_R VDD VSS +XA_I80<1> A_WCLK_B_L A_RCLK_B_L A_W_nor_R<1> VDD VSS / ++ RSC_IHPSG13_AND2X2 +XA_I80<0> A_WCLK_B_L A_RCLK_B_L A_W_nor_R<0> VDD VSS / ++ RSC_IHPSG13_AND2X2 +XA_I44 A_BM_N A_WCLK_B_L A_DO_WRITE_P VDD VSS / RSC_IHPSG13_NOR2X2 +XI80<29> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI80<28> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI80<27> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI80<26> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI80<25> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI80<24> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI80<23> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI80<22> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI80<21> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI80<20> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI80<19> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI80<18> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI80<17> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI80<16> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI80<15> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI80<14> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI80<13> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI80<12> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI80<11> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI80<10> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI80<9> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI80<8> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI80<7> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI80<6> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI80<5> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI80<4> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI80<3> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI80<2> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI80<1> VDD VSS / RSC_IHPSG13_FILLCAP8 +XA_I74<16> VDD VSS / RSC_IHPSG13_FILLCAP8 +XA_I74<15> VDD VSS / RSC_IHPSG13_FILLCAP8 +XA_I74<14> VDD VSS / RSC_IHPSG13_FILLCAP8 +XA_I74<13> VDD VSS / RSC_IHPSG13_FILLCAP8 +XA_I74<12> VDD VSS / RSC_IHPSG13_FILLCAP8 +XA_I74<11> VDD VSS / RSC_IHPSG13_FILLCAP8 +XA_I74<10> VDD VSS / RSC_IHPSG13_FILLCAP8 +XA_I74<9> VDD VSS / RSC_IHPSG13_FILLCAP8 +XA_I74<8> VDD VSS / RSC_IHPSG13_FILLCAP8 +XA_I74<7> VDD VSS / RSC_IHPSG13_FILLCAP8 +XA_I74<6> VDD VSS / RSC_IHPSG13_FILLCAP8 +XA_I74<5> VDD VSS / RSC_IHPSG13_FILLCAP8 +XA_I74<4> VDD VSS / RSC_IHPSG13_FILLCAP8 +XA_I74<3> VDD VSS / RSC_IHPSG13_FILLCAP8 +XA_I74<2> VDD VSS / RSC_IHPSG13_FILLCAP8 +XA_I74<1> VDD VSS / RSC_IHPSG13_FILLCAP8 +XA_INV<6> A_N1<1> A_P1<1> VDD VSS / RSC_IHPSG13_CINVX4 +XA_INV<5> A_N0<1> A_P0<1> VDD VSS / RSC_IHPSG13_CINVX4 +XA_INV<4> A_N0<0> A_P0<0> VDD VSS / RSC_IHPSG13_CINVX4 +XA_INV<3> A_ADDR_COL<1> A_N1<1> VDD VSS / RSC_IHPSG13_CINVX4 +XA_INV<2> A_ADDR_COL<1> A_N1<0> VDD VSS / RSC_IHPSG13_CINVX4 +XA_INV<1> A_ADDR_COL<0> A_N0<1> VDD VSS / RSC_IHPSG13_CINVX4 +XA_INV<0> A_ADDR_COL<0> A_N0<0> VDD VSS / RSC_IHPSG13_CINVX4 +XA_I81<3> A_W_nor_R<1> A_PRE_N VDD VSS / RSC_IHPSG13_CINVX4_WN +XA_I81<2> A_W_nor_R<1> A_PRE_N VDD VSS / RSC_IHPSG13_CINVX4_WN +XA_I81<1> A_W_nor_R<0> A_PRE_N VDD VSS / RSC_IHPSG13_CINVX4_WN +XA_I81<0> A_W_nor_R<0> A_PRE_N VDD VSS / RSC_IHPSG13_CINVX4_WN +XA_BLTMUX<31> A_BLC<31> A_BLC_SEL A_BLT<31> A_BLT_SEL A_PRE_N A_SEL_P<31> ++ A_WR_ONE A_WR_ZERO VDD VSS / RM_IHPSG13_256x16_c2_1P_BLDRV +XA_BLTMUX<30> A_BLC<30> A_BLC_SEL A_BLT<30> A_BLT_SEL A_PRE_N A_SEL_P<30> ++ A_WR_ONE A_WR_ZERO VDD VSS / RM_IHPSG13_256x16_c2_1P_BLDRV +XA_BLTMUX<29> A_BLC<29> A_BLC_SEL A_BLT<29> A_BLT_SEL A_PRE_N A_SEL_P<29> ++ A_WR_ONE A_WR_ZERO VDD VSS / RM_IHPSG13_256x16_c2_1P_BLDRV +XA_BLTMUX<28> A_BLC<28> A_BLC_SEL A_BLT<28> A_BLT_SEL A_PRE_N A_SEL_P<28> ++ A_WR_ONE A_WR_ZERO VDD VSS / RM_IHPSG13_256x16_c2_1P_BLDRV +XA_BLTMUX<27> A_BLC<27> A_BLC_SEL A_BLT<27> A_BLT_SEL A_PRE_N A_SEL_P<27> ++ A_WR_ONE A_WR_ZERO VDD VSS / RM_IHPSG13_256x16_c2_1P_BLDRV +XA_BLTMUX<26> A_BLC<26> A_BLC_SEL A_BLT<26> A_BLT_SEL A_PRE_N A_SEL_P<26> ++ A_WR_ONE A_WR_ZERO VDD VSS / RM_IHPSG13_256x16_c2_1P_BLDRV +XA_BLTMUX<25> A_BLC<25> A_BLC_SEL A_BLT<25> A_BLT_SEL A_PRE_N A_SEL_P<25> ++ A_WR_ONE A_WR_ZERO VDD VSS / RM_IHPSG13_256x16_c2_1P_BLDRV +XA_BLTMUX<24> A_BLC<24> A_BLC_SEL A_BLT<24> A_BLT_SEL A_PRE_N A_SEL_P<24> ++ A_WR_ONE A_WR_ZERO VDD VSS / RM_IHPSG13_256x16_c2_1P_BLDRV +XA_BLTMUX<23> A_BLC<23> A_BLC_SEL A_BLT<23> A_BLT_SEL A_PRE_N A_SEL_P<23> ++ A_WR_ONE A_WR_ZERO VDD VSS / RM_IHPSG13_256x16_c2_1P_BLDRV +XA_BLTMUX<22> A_BLC<22> A_BLC_SEL A_BLT<22> A_BLT_SEL A_PRE_N A_SEL_P<22> ++ A_WR_ONE A_WR_ZERO VDD VSS / RM_IHPSG13_256x16_c2_1P_BLDRV +XA_BLTMUX<21> A_BLC<21> A_BLC_SEL A_BLT<21> A_BLT_SEL A_PRE_N A_SEL_P<21> ++ A_WR_ONE A_WR_ZERO VDD VSS / RM_IHPSG13_256x16_c2_1P_BLDRV +XA_BLTMUX<20> A_BLC<20> A_BLC_SEL A_BLT<20> A_BLT_SEL A_PRE_N A_SEL_P<20> ++ A_WR_ONE A_WR_ZERO VDD VSS / RM_IHPSG13_256x16_c2_1P_BLDRV +XA_BLTMUX<19> A_BLC<19> A_BLC_SEL A_BLT<19> A_BLT_SEL A_PRE_N A_SEL_P<19> ++ A_WR_ONE A_WR_ZERO VDD VSS / RM_IHPSG13_256x16_c2_1P_BLDRV +XA_BLTMUX<18> A_BLC<18> A_BLC_SEL A_BLT<18> A_BLT_SEL A_PRE_N A_SEL_P<18> ++ A_WR_ONE A_WR_ZERO VDD VSS / RM_IHPSG13_256x16_c2_1P_BLDRV +XA_BLTMUX<17> A_BLC<17> A_BLC_SEL A_BLT<17> A_BLT_SEL A_PRE_N A_SEL_P<17> ++ A_WR_ONE A_WR_ZERO VDD VSS / RM_IHPSG13_256x16_c2_1P_BLDRV +XA_BLTMUX<16> A_BLC<16> A_BLC_SEL A_BLT<16> A_BLT_SEL A_PRE_N A_SEL_P<16> ++ A_WR_ONE A_WR_ZERO VDD VSS / RM_IHPSG13_256x16_c2_1P_BLDRV +XA_BLTMUX<15> A_BLC<15> A_BLC_SEL A_BLT<15> A_BLT_SEL A_PRE_N A_SEL_P<15> ++ A_WR_ONE A_WR_ZERO VDD VSS / RM_IHPSG13_256x16_c2_1P_BLDRV +XA_BLTMUX<14> A_BLC<14> A_BLC_SEL A_BLT<14> A_BLT_SEL A_PRE_N A_SEL_P<14> ++ A_WR_ONE A_WR_ZERO VDD VSS / RM_IHPSG13_256x16_c2_1P_BLDRV +XA_BLTMUX<13> A_BLC<13> A_BLC_SEL A_BLT<13> A_BLT_SEL A_PRE_N A_SEL_P<13> ++ A_WR_ONE A_WR_ZERO VDD VSS / RM_IHPSG13_256x16_c2_1P_BLDRV +XA_BLTMUX<12> A_BLC<12> A_BLC_SEL A_BLT<12> A_BLT_SEL A_PRE_N A_SEL_P<12> ++ A_WR_ONE A_WR_ZERO VDD VSS / RM_IHPSG13_256x16_c2_1P_BLDRV +XA_BLTMUX<11> A_BLC<11> A_BLC_SEL A_BLT<11> A_BLT_SEL A_PRE_N A_SEL_P<11> ++ A_WR_ONE A_WR_ZERO VDD VSS / RM_IHPSG13_256x16_c2_1P_BLDRV +XA_BLTMUX<10> A_BLC<10> A_BLC_SEL A_BLT<10> A_BLT_SEL A_PRE_N A_SEL_P<10> ++ A_WR_ONE A_WR_ZERO VDD VSS / RM_IHPSG13_256x16_c2_1P_BLDRV +XA_BLTMUX<9> A_BLC<9> A_BLC_SEL A_BLT<9> A_BLT_SEL A_PRE_N A_SEL_P<9> A_WR_ONE ++ A_WR_ZERO VDD VSS / RM_IHPSG13_256x16_c2_1P_BLDRV +XA_BLTMUX<8> A_BLC<8> A_BLC_SEL A_BLT<8> A_BLT_SEL A_PRE_N A_SEL_P<8> A_WR_ONE ++ A_WR_ZERO VDD VSS / RM_IHPSG13_256x16_c2_1P_BLDRV +XA_BLTMUX<7> A_BLC<7> A_BLC_SEL A_BLT<7> A_BLT_SEL A_PRE_N A_SEL_P<7> A_WR_ONE ++ A_WR_ZERO VDD VSS / RM_IHPSG13_256x16_c2_1P_BLDRV +XA_BLTMUX<6> A_BLC<6> A_BLC_SEL A_BLT<6> A_BLT_SEL A_PRE_N A_SEL_P<6> A_WR_ONE ++ A_WR_ZERO VDD VSS / RM_IHPSG13_256x16_c2_1P_BLDRV +XA_BLTMUX<5> A_BLC<5> A_BLC_SEL A_BLT<5> A_BLT_SEL A_PRE_N A_SEL_P<5> A_WR_ONE ++ A_WR_ZERO VDD VSS / RM_IHPSG13_256x16_c2_1P_BLDRV +XA_BLTMUX<4> A_BLC<4> A_BLC_SEL A_BLT<4> A_BLT_SEL A_PRE_N A_SEL_P<4> A_WR_ONE ++ A_WR_ZERO VDD VSS / RM_IHPSG13_256x16_c2_1P_BLDRV +XA_BLTMUX<3> A_BLC<3> A_BLC_SEL A_BLT<3> A_BLT_SEL A_PRE_N A_SEL_P<3> A_WR_ONE ++ A_WR_ZERO VDD VSS / RM_IHPSG13_256x16_c2_1P_BLDRV +XA_BLTMUX<2> A_BLC<2> A_BLC_SEL A_BLT<2> A_BLT_SEL A_PRE_N A_SEL_P<2> A_WR_ONE ++ A_WR_ZERO VDD VSS / RM_IHPSG13_256x16_c2_1P_BLDRV +XA_BLTMUX<1> A_BLC<1> A_BLC_SEL A_BLT<1> A_BLT_SEL A_PRE_N A_SEL_P<1> A_WR_ONE ++ A_WR_ZERO VDD VSS / RM_IHPSG13_256x16_c2_1P_BLDRV +XA_BLTMUX<0> A_BLC<0> A_BLC_SEL A_BLT<0> A_BLT_SEL A_PRE_N A_SEL_P<0> A_WR_ONE ++ A_WR_ZERO VDD VSS / RM_IHPSG13_256x16_c2_1P_BLDRV +XA_CAPS<17> VDD VSS / RSC_IHPSG13_FILLCAP4 +XA_CAPS<16> VDD VSS / RSC_IHPSG13_FILLCAP4 +XA_CAPS<15> VDD VSS / RSC_IHPSG13_FILLCAP4 +XA_CAPS<14> VDD VSS / RSC_IHPSG13_FILLCAP4 +XA_CAPS<13> VDD VSS / RSC_IHPSG13_FILLCAP4 +XA_CAPS<12> VDD VSS / RSC_IHPSG13_FILLCAP4 +XA_CAPS<11> VDD VSS / RSC_IHPSG13_FILLCAP4 +XA_CAPS<10> VDD VSS / RSC_IHPSG13_FILLCAP4 +XA_CAPS<9> VDD VSS / RSC_IHPSG13_FILLCAP4 +XA_CAPS<8> VDD VSS / RSC_IHPSG13_FILLCAP4 +XA_CAPS<7> VDD VSS / RSC_IHPSG13_FILLCAP4 +XA_CAPS<6> VDD VSS / RSC_IHPSG13_FILLCAP4 +XA_CAPS<5> VDD VSS / RSC_IHPSG13_FILLCAP4 +XA_CAPS<4> VDD VSS / RSC_IHPSG13_FILLCAP4 +XA_CAPS<3> VDD VSS / RSC_IHPSG13_FILLCAP4 +XA_CAPS<2> VDD VSS / RSC_IHPSG13_FILLCAP4 +XA_CAPS<1> VDD VSS / RSC_IHPSG13_FILLCAP4 +XA_I51 net19 A_DR_O VDD VSS / RSC_IHPSG13_INVX4 +XA_I78 A_RCLK_B_L A_SAE VDD VSS / RSC_IHPSG13_CBUFX2 +XA_I69 A_DCLK_L A_DCLK_B_L VDD VSS / RSC_IHPSG13_CINVX8 +XA_I50 A_WCLK_L A_WCLK_B_L VDD VSS / RSC_IHPSG13_CINVX8 +XA_EBUF A_RCLK_L A_RCLK_B_L VDD VSS / RSC_IHPSG13_CINVX8 +XA_I76 A_DI_N A_DO_WRITE_P A_WR_ZERO VDD VSS / RSC_IHPSG13_AND2X6 +XA_I75 A_DI_R A_DO_WRITE_P A_WR_ONE VDD VSS / RSC_IHPSG13_AND2X6 +XA_I83 A_BM_R A_BM_N VDD VSS / RSC_IHPSG13_INVX2 +XA_DEC3INV<31> net23<0> A_SEL_P<31> VDD VSS / RSC_IHPSG13_INVX2 +XA_DEC3INV<30> net23<1> A_SEL_P<30> VDD VSS / RSC_IHPSG13_INVX2 +XA_DEC3INV<29> net23<2> A_SEL_P<29> VDD VSS / RSC_IHPSG13_INVX2 +XA_DEC3INV<28> net23<3> A_SEL_P<28> VDD VSS / RSC_IHPSG13_INVX2 +XA_DEC3INV<27> net23<4> A_SEL_P<27> VDD VSS / RSC_IHPSG13_INVX2 +XA_DEC3INV<26> net23<5> A_SEL_P<26> VDD VSS / RSC_IHPSG13_INVX2 +XA_DEC3INV<25> net23<6> A_SEL_P<25> VDD VSS / RSC_IHPSG13_INVX2 +XA_DEC3INV<24> net23<7> A_SEL_P<24> VDD VSS / RSC_IHPSG13_INVX2 +XA_DEC3INV<23> net23<8> A_SEL_P<23> VDD VSS / RSC_IHPSG13_INVX2 +XA_DEC3INV<22> net23<9> A_SEL_P<22> VDD VSS / RSC_IHPSG13_INVX2 +XA_DEC3INV<21> net23<10> A_SEL_P<21> VDD VSS / RSC_IHPSG13_INVX2 +XA_DEC3INV<20> net23<11> A_SEL_P<20> VDD VSS / RSC_IHPSG13_INVX2 +XA_DEC3INV<19> net23<12> A_SEL_P<19> VDD VSS / RSC_IHPSG13_INVX2 +XA_DEC3INV<18> net23<13> A_SEL_P<18> VDD VSS / RSC_IHPSG13_INVX2 +XA_DEC3INV<17> net23<14> A_SEL_P<17> VDD VSS / RSC_IHPSG13_INVX2 +XA_DEC3INV<16> net23<15> A_SEL_P<16> VDD VSS / RSC_IHPSG13_INVX2 +XA_DEC3INV<15> net23<16> A_SEL_P<15> VDD VSS / RSC_IHPSG13_INVX2 +XA_DEC3INV<14> net23<17> A_SEL_P<14> VDD VSS / RSC_IHPSG13_INVX2 +XA_DEC3INV<13> net23<18> A_SEL_P<13> VDD VSS / RSC_IHPSG13_INVX2 +XA_DEC3INV<12> net23<19> A_SEL_P<12> VDD VSS / RSC_IHPSG13_INVX2 +XA_DEC3INV<11> net23<20> A_SEL_P<11> VDD VSS / RSC_IHPSG13_INVX2 +XA_DEC3INV<10> net23<21> A_SEL_P<10> VDD VSS / RSC_IHPSG13_INVX2 +XA_DEC3INV<9> net23<22> A_SEL_P<9> VDD VSS / RSC_IHPSG13_INVX2 +XA_DEC3INV<8> net23<23> A_SEL_P<8> VDD VSS / RSC_IHPSG13_INVX2 +XA_DEC3INV<7> net23<24> A_SEL_P<7> VDD VSS / RSC_IHPSG13_INVX2 +XA_DEC3INV<6> net23<25> A_SEL_P<6> VDD VSS / RSC_IHPSG13_INVX2 +XA_DEC3INV<5> net23<26> A_SEL_P<5> VDD VSS / RSC_IHPSG13_INVX2 +XA_DEC3INV<4> net23<27> A_SEL_P<4> VDD VSS / RSC_IHPSG13_INVX2 +XA_DEC3INV<3> net23<28> A_SEL_P<3> VDD VSS / RSC_IHPSG13_INVX2 +XA_DEC3INV<2> net23<29> A_SEL_P<2> VDD VSS / RSC_IHPSG13_INVX2 +XA_DEC3INV<1> net23<30> A_SEL_P<1> VDD VSS / RSC_IHPSG13_INVX2 +XA_DEC3INV<0> net23<31> A_SEL_P<0> VDD VSS / RSC_IHPSG13_INVX2 +XA_I49 A_DI_R A_DI_N VDD VSS / RSC_IHPSG13_INVX2 +XA_ISENSE A_SAE A_BLC_SEL A_BLT_SEL net19 net20 VDD VSS / ++ RSC_IHPSG13_DFPQD_MSAFFX2 +XA_DREG A_BIST_EN_I A_BIST_DW_I A_DCLK_B_L A_DW_I A_DI_R net22 VDD VSS ++ / RSC_IHPSG13_DFNQMX2IX1 +XA_BREG A_BIST_EN_I A_BIST_BM_I A_DCLK_B_L A_BM_I A_BM_R net21 VDD VSS ++ / RSC_IHPSG13_DFNQMX2IX1 +XA_DEC3<31> A_P1<1> A_P0<1> A_ADDR_DEC<7> net23<0> VDD VSS / ++ RSC_IHPSG13_NAND3X2 +XA_DEC3<30> A_P1<1> A_P0<1> A_ADDR_DEC<6> net23<1> VDD VSS / ++ RSC_IHPSG13_NAND3X2 +XA_DEC3<29> A_P1<1> A_P0<1> A_ADDR_DEC<5> net23<2> VDD VSS / ++ RSC_IHPSG13_NAND3X2 +XA_DEC3<28> A_P1<1> A_P0<1> A_ADDR_DEC<4> net23<3> VDD VSS / ++ RSC_IHPSG13_NAND3X2 +XA_DEC3<27> A_P1<1> A_P0<1> A_ADDR_DEC<3> net23<4> VDD VSS / ++ RSC_IHPSG13_NAND3X2 +XA_DEC3<26> A_P1<1> A_P0<1> A_ADDR_DEC<2> net23<5> VDD VSS / ++ RSC_IHPSG13_NAND3X2 +XA_DEC3<25> A_P1<1> A_P0<1> A_ADDR_DEC<1> net23<6> VDD VSS / ++ RSC_IHPSG13_NAND3X2 +XA_DEC3<24> A_P1<1> A_P0<1> A_ADDR_DEC<0> net23<7> VDD VSS / ++ RSC_IHPSG13_NAND3X2 +XA_DEC3<23> A_P1<1> A_N0<1> A_ADDR_DEC<7> net23<8> VDD VSS / ++ RSC_IHPSG13_NAND3X2 +XA_DEC3<22> A_P1<1> A_N0<1> A_ADDR_DEC<6> net23<9> VDD VSS / ++ RSC_IHPSG13_NAND3X2 +XA_DEC3<21> A_P1<1> A_N0<1> A_ADDR_DEC<5> net23<10> VDD VSS / ++ RSC_IHPSG13_NAND3X2 +XA_DEC3<20> A_P1<1> A_N0<1> A_ADDR_DEC<4> net23<11> VDD VSS / ++ RSC_IHPSG13_NAND3X2 +XA_DEC3<19> A_P1<1> A_N0<1> A_ADDR_DEC<3> net23<12> VDD VSS / ++ RSC_IHPSG13_NAND3X2 +XA_DEC3<18> A_P1<1> A_N0<1> A_ADDR_DEC<2> net23<13> VDD VSS / ++ RSC_IHPSG13_NAND3X2 +XA_DEC3<17> A_P1<1> A_N0<1> A_ADDR_DEC<1> net23<14> VDD VSS / ++ RSC_IHPSG13_NAND3X2 +XA_DEC3<16> A_P1<1> A_N0<1> A_ADDR_DEC<0> net23<15> VDD VSS / ++ RSC_IHPSG13_NAND3X2 +XA_DEC3<15> A_N1<0> A_P0<0> A_ADDR_DEC<7> net23<16> VDD VSS / ++ RSC_IHPSG13_NAND3X2 +XA_DEC3<14> A_N1<0> A_P0<0> A_ADDR_DEC<6> net23<17> VDD VSS / ++ RSC_IHPSG13_NAND3X2 +XA_DEC3<13> A_N1<0> A_P0<0> A_ADDR_DEC<5> net23<18> VDD VSS / ++ RSC_IHPSG13_NAND3X2 +XA_DEC3<12> A_N1<0> A_P0<0> A_ADDR_DEC<4> net23<19> VDD VSS / ++ RSC_IHPSG13_NAND3X2 +XA_DEC3<11> A_N1<0> A_P0<0> A_ADDR_DEC<3> net23<20> VDD VSS / ++ RSC_IHPSG13_NAND3X2 +XA_DEC3<10> A_N1<0> A_P0<0> A_ADDR_DEC<2> net23<21> VDD VSS / ++ RSC_IHPSG13_NAND3X2 +XA_DEC3<9> A_N1<0> A_P0<0> A_ADDR_DEC<1> net23<22> VDD VSS / ++ RSC_IHPSG13_NAND3X2 +XA_DEC3<8> A_N1<0> A_P0<0> A_ADDR_DEC<0> net23<23> VDD VSS / ++ RSC_IHPSG13_NAND3X2 +XA_DEC3<7> A_N1<0> A_N0<0> A_ADDR_DEC<7> net23<24> VDD VSS / ++ RSC_IHPSG13_NAND3X2 +XA_DEC3<6> A_N1<0> A_N0<0> A_ADDR_DEC<6> net23<25> VDD VSS / ++ RSC_IHPSG13_NAND3X2 +XA_DEC3<5> A_N1<0> A_N0<0> A_ADDR_DEC<5> net23<26> VDD VSS / ++ RSC_IHPSG13_NAND3X2 +XA_DEC3<4> A_N1<0> A_N0<0> A_ADDR_DEC<4> net23<27> VDD VSS / ++ RSC_IHPSG13_NAND3X2 +XA_DEC3<3> A_N1<0> A_N0<0> A_ADDR_DEC<3> net23<28> VDD VSS / ++ RSC_IHPSG13_NAND3X2 +XA_DEC3<2> A_N1<0> A_N0<0> A_ADDR_DEC<2> net23<29> VDD VSS / ++ RSC_IHPSG13_NAND3X2 +XA_DEC3<1> A_N1<0> A_N0<0> A_ADDR_DEC<1> net23<30> VDD VSS / ++ RSC_IHPSG13_NAND3X2 +XA_DEC3<0> A_N1<0> A_N0<0> A_ADDR_DEC<0> net23<31> VDD VSS / ++ RSC_IHPSG13_NAND3X2 +XA_I89 A_DCLK_B_L A_DCLK_B_R / RSC_IHPSG13_MET3RES +XA_I91 A_RCLK_B_L A_RCLK_B_R / RSC_IHPSG13_MET3RES +XA_I90 A_WCLK_B_L A_WCLK_B_R / RSC_IHPSG13_MET3RES +XA_I88 A_DCLK_L A_DCLK_R / RSC_IHPSG13_MET3RES +XA_I87 A_WCLK_L A_WCLK_R / RSC_IHPSG13_MET3RES +XA_R2 A_RCLK_L A_RCLK_R / RSC_IHPSG13_MET3RES +XA_BM_TIEH A_TIEH_O VDD VSS / RSC_IHPSG13_TIEH +.ENDS + +.SUBCKT RM_IHPSG13_256x16_c2_1P_COLDRV13X12 ADDR_COL_I<1> ADDR_COL_I<0> ADDR_COL_O<1> ++ ADDR_COL_O<0> ADDR_DEC_I<7> ADDR_DEC_I<6> ADDR_DEC_I<5> ADDR_DEC_I<4> ++ ADDR_DEC_I<3> ADDR_DEC_I<2> ADDR_DEC_I<1> ADDR_DEC_I<0> ADDR_DEC_O<7> ++ ADDR_DEC_O<6> ADDR_DEC_O<5> ADDR_DEC_O<4> ADDR_DEC_O<3> ADDR_DEC_O<2> ++ ADDR_DEC_O<1> ADDR_DEC_O<0> DCLK_I DCLK_O RCLK_I RCLK_O WCLK_I WCLK_O ++ VDD VSS +XI1<1> VDD VSS / RSC_IHPSG13_FILLCAP4 +XI1<0> VDD VSS / RSC_IHPSG13_FILLCAP4 +XI0<1> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI0<0> VDD VSS / RSC_IHPSG13_FILLCAP8 +XADDR_COL_DRV<1> ADDR_COL_I<1> ADDR_COL_O<1> VDD VSS / ++ RSC_IHPSG13_CBUFX12 +XADDR_COL_DRV<0> ADDR_COL_I<0> ADDR_COL_O<0> VDD VSS / ++ RSC_IHPSG13_CBUFX12 +XADDR_DEC_DRV<7> ADDR_DEC_I<7> ADDR_DEC_O<7> VDD VSS / ++ RSC_IHPSG13_CBUFX12 +XADDR_DEC_DRV<6> ADDR_DEC_I<6> ADDR_DEC_O<6> VDD VSS / ++ RSC_IHPSG13_CBUFX12 +XADDR_DEC_DRV<5> ADDR_DEC_I<5> ADDR_DEC_O<5> VDD VSS / ++ RSC_IHPSG13_CBUFX12 +XADDR_DEC_DRV<4> ADDR_DEC_I<4> ADDR_DEC_O<4> VDD VSS / ++ RSC_IHPSG13_CBUFX12 +XADDR_DEC_DRV<3> ADDR_DEC_I<3> ADDR_DEC_O<3> VDD VSS / ++ RSC_IHPSG13_CBUFX12 +XADDR_DEC_DRV<2> ADDR_DEC_I<2> ADDR_DEC_O<2> VDD VSS / ++ RSC_IHPSG13_CBUFX12 +XADDR_DEC_DRV<1> ADDR_DEC_I<1> ADDR_DEC_O<1> VDD VSS / ++ RSC_IHPSG13_CBUFX12 +XADDR_DEC_DRV<0> ADDR_DEC_I<0> ADDR_DEC_O<0> VDD VSS / ++ RSC_IHPSG13_CBUFX12 +XDCLK_DRV DCLK_I DCLK_O VDD VSS / RSC_IHPSG13_CBUFX12 +XRCLK_DRV RCLK_I RCLK_O VDD VSS / RSC_IHPSG13_CBUFX12 +XWCLK_DRV WCLK_I WCLK_O VDD VSS / RSC_IHPSG13_CBUFX12 +.ENDS +.SUBCKT RM_IHPSG13_256x16_c2_1P_WLDRV16X12 A<15> A<14> A<13> A<12> A<11> A<10> A<9> A<8> ++ A<7> A<6> A<5> A<4> A<3> A<2> A<1> A<0> Z<15> Z<14> Z<13> Z<12> Z<11> Z<10> ++ Z<9> Z<8> Z<7> Z<6> Z<5> Z<4> Z<3> Z<2> Z<1> Z<0> VDD VSS +XBUF<15> A<15> Z<15> VDD VSS / RSC_IHPSG13_WLDRVX12 +XBUF<14> A<14> Z<14> VDD VSS / RSC_IHPSG13_WLDRVX12 +XBUF<13> A<13> Z<13> VDD VSS / RSC_IHPSG13_WLDRVX12 +XBUF<12> A<12> Z<12> VDD VSS / RSC_IHPSG13_WLDRVX12 +XBUF<11> A<11> Z<11> VDD VSS / RSC_IHPSG13_WLDRVX12 +XBUF<10> A<10> Z<10> VDD VSS / RSC_IHPSG13_WLDRVX12 +XBUF<9> A<9> Z<9> VDD VSS / RSC_IHPSG13_WLDRVX12 +XBUF<8> A<8> Z<8> VDD VSS / RSC_IHPSG13_WLDRVX12 +XBUF<7> A<7> Z<7> VDD VSS / RSC_IHPSG13_WLDRVX12 +XBUF<6> A<6> Z<6> VDD VSS / RSC_IHPSG13_WLDRVX12 +XBUF<5> A<5> Z<5> VDD VSS / RSC_IHPSG13_WLDRVX12 +XBUF<4> A<4> Z<4> VDD VSS / RSC_IHPSG13_WLDRVX12 +XBUF<3> A<3> Z<3> VDD VSS / RSC_IHPSG13_WLDRVX12 +XBUF<2> A<2> Z<2> VDD VSS / RSC_IHPSG13_WLDRVX12 +XBUF<1> A<1> Z<1> VDD VSS / RSC_IHPSG13_WLDRVX12 +XBUF<0> A<0> Z<0> VDD VSS / RSC_IHPSG13_WLDRVX12 +.ENDS + + + +.SUBCKT RM_IHPSG13_256x16_c2_2P_COLDRV13X8 ADDR_COL_I<1> ADDR_COL_I<0> ADDR_COL_O<1> ++ ADDR_COL_O<0> ADDR_DEC_I<7> ADDR_DEC_I<6> ADDR_DEC_I<5> ADDR_DEC_I<4> ++ ADDR_DEC_I<3> ADDR_DEC_I<2> ADDR_DEC_I<1> ADDR_DEC_I<0> ADDR_DEC_O<7> ++ ADDR_DEC_O<6> ADDR_DEC_O<5> ADDR_DEC_O<4> ADDR_DEC_O<3> ADDR_DEC_O<2> ++ ADDR_DEC_O<1> ADDR_DEC_O<0> DCLK_I DCLK_O RCLK_I RCLK_O WCLK_I WCLK_O ++ VDD VSS +XI0<5> VDD VSS / RSC_IHPSG13_FILLCAP4 +XI0<4> VDD VSS / RSC_IHPSG13_FILLCAP4 +XI0<3> VDD VSS / RSC_IHPSG13_FILLCAP4 +XI0<2> VDD VSS / RSC_IHPSG13_FILLCAP4 +XI0<1> VDD VSS / RSC_IHPSG13_FILLCAP4 +XWCLK_DRV WCLK_I WCLK_O VDD VSS / RSC_IHPSG13_CBUFX8 +XRCLK_DRV RCLK_I RCLK_O VDD VSS / RSC_IHPSG13_CBUFX8 +XDCLK_DRV DCLK_I DCLK_O VDD VSS / RSC_IHPSG13_CBUFX8 +XADDR_COL_DRV<1> ADDR_COL_I<1> ADDR_COL_O<1> VDD VSS / ++ RSC_IHPSG13_CBUFX8 +XADDR_COL_DRV<0> ADDR_COL_I<0> ADDR_COL_O<0> VDD VSS / ++ RSC_IHPSG13_CBUFX8 +XADDR_DEC_DRV<7> ADDR_DEC_I<7> ADDR_DEC_O<7> VDD VSS / ++ RSC_IHPSG13_CBUFX8 +XADDR_DEC_DRV<6> ADDR_DEC_I<6> ADDR_DEC_O<6> VDD VSS / ++ RSC_IHPSG13_CBUFX8 +XADDR_DEC_DRV<5> ADDR_DEC_I<5> ADDR_DEC_O<5> VDD VSS / ++ RSC_IHPSG13_CBUFX8 +XADDR_DEC_DRV<4> ADDR_DEC_I<4> ADDR_DEC_O<4> VDD VSS / ++ RSC_IHPSG13_CBUFX8 +XADDR_DEC_DRV<3> ADDR_DEC_I<3> ADDR_DEC_O<3> VDD VSS / ++ RSC_IHPSG13_CBUFX8 +XADDR_DEC_DRV<2> ADDR_DEC_I<2> ADDR_DEC_O<2> VDD VSS / ++ RSC_IHPSG13_CBUFX8 +XADDR_DEC_DRV<1> ADDR_DEC_I<1> ADDR_DEC_O<1> VDD VSS / ++ RSC_IHPSG13_CBUFX8 +XADDR_DEC_DRV<0> ADDR_DEC_I<0> ADDR_DEC_O<0> VDD VSS / ++ RSC_IHPSG13_CBUFX8 +XI1<3> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI1<2> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI1<1> VDD VSS / RSC_IHPSG13_FILLCAP8 +.ENDS +.SUBCKT RSC_IHPSG13_WLDRVX8 A Z VDD VSS +MN1 Z net6 VSS VSS sg13_lv_nmos m=1 w=1.41u l=130.00n ng=2 nrd=0 nrs=0 +MN0 net6 A VSS VSS sg13_lv_nmos m=1 w=1.8u l=130.00n ng=2 nrd=0 nrs=0 +MP1 Z net6 VDD VDD sg13_lv_pmos m=1 w=6.48u l=130.00n ng=4 nrd=0 nrs=0 +MP0 net6 A VDD VDD sg13_lv_pmos m=1 w=900.0n l=130.00n ng=1 nrd=0 nrs=0 +.ENDS +.SUBCKT RM_IHPSG13_256x16_c2_2P_WLDRV16X8 A<15> A<14> A<13> A<12> A<11> A<10> A<9> A<8> ++ A<7> A<6> A<5> A<4> A<3> A<2> A<1> A<0> Z<15> Z<14> Z<13> Z<12> Z<11> Z<10> ++ Z<9> Z<8> Z<7> Z<6> Z<5> Z<4> Z<3> Z<2> Z<1> Z<0> VDD VSS +XBUF<15> A<15> Z<15> VDD VSS / RSC_IHPSG13_WLDRVX8 +XBUF<14> A<14> Z<14> VDD VSS / RSC_IHPSG13_WLDRVX8 +XBUF<13> A<13> Z<13> VDD VSS / RSC_IHPSG13_WLDRVX8 +XBUF<12> A<12> Z<12> VDD VSS / RSC_IHPSG13_WLDRVX8 +XBUF<11> A<11> Z<11> VDD VSS / RSC_IHPSG13_WLDRVX8 +XBUF<10> A<10> Z<10> VDD VSS / RSC_IHPSG13_WLDRVX8 +XBUF<9> A<9> Z<9> VDD VSS / RSC_IHPSG13_WLDRVX8 +XBUF<8> A<8> Z<8> VDD VSS / RSC_IHPSG13_WLDRVX8 +XBUF<7> A<7> Z<7> VDD VSS / RSC_IHPSG13_WLDRVX8 +XBUF<6> A<6> Z<6> VDD VSS / RSC_IHPSG13_WLDRVX8 +XBUF<5> A<5> Z<5> VDD VSS / RSC_IHPSG13_WLDRVX8 +XBUF<4> A<4> Z<4> VDD VSS / RSC_IHPSG13_WLDRVX8 +XBUF<3> A<3> Z<3> VDD VSS / RSC_IHPSG13_WLDRVX8 +XBUF<2> A<2> Z<2> VDD VSS / RSC_IHPSG13_WLDRVX8 +XBUF<1> A<1> Z<1> VDD VSS / RSC_IHPSG13_WLDRVX8 +XBUF<0> A<0> Z<0> VDD VSS / RSC_IHPSG13_WLDRVX8 +.ENDS + + + +.SUBCKT RM_IHPSG13_256x16_c2_2P_COLDEC2 ACLK_N ADDR<1> ADDR<0> ADDR_COL<1> ADDR_COL<0> ++ ADDR_DEC<7> ADDR_DEC<6> ADDR_DEC<5> ADDR_DEC<4> ADDR_DEC<3> ADDR_DEC<2> ++ ADDR_DEC<1> ADDR_DEC<0> BIST_ADDR<1> BIST_ADDR<0> BIST_EN_I VDD VSS +XI16<17> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI16<16> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI16<15> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI16<14> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI16<13> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI16<12> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI16<11> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI16<10> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI16<9> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI16<8> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI16<7> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI16<6> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI16<5> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI16<4> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI16<3> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI16<2> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI16<1> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI18<24> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI18<23> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI18<22> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI18<21> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI18<20> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI18<19> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI18<18> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI18<17> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI18<16> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI18<15> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI18<14> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI18<13> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI18<12> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI18<11> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI18<10> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI18<9> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI18<8> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI18<7> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI18<6> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI18<5> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI18<4> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI18<3> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI18<2> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI18<1> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI1<3> PADR<0> PADR<1> addr_n<3> VDD VSS / RSC_IHPSG13_NAND2X2 +XI1<2> NADR<0> PADR<1> addr_n<2> VDD VSS / RSC_IHPSG13_NAND2X2 +XI1<1> PADR<0> NADR<1> addr_n<1> VDD VSS / RSC_IHPSG13_NAND2X2 +XI1<0> NADR<0> NADR<1> addr_n<0> VDD VSS / RSC_IHPSG13_NAND2X2 +XI17<1> ADDR_COL<1> VDD VSS / RSC_IHPSG13_TIEL +XI17<0> ADDR_COL<0> VDD VSS / RSC_IHPSG13_TIEL +XI14<3> ADDR_DEC<7> VDD VSS / RSC_IHPSG13_TIEL +XI14<2> ADDR_DEC<6> VDD VSS / RSC_IHPSG13_TIEL +XI14<1> ADDR_DEC<5> VDD VSS / RSC_IHPSG13_TIEL +XI14<0> ADDR_DEC<4> VDD VSS / RSC_IHPSG13_TIEL +XI13<1> NADR<1> PADR<1> VDD VSS / RSC_IHPSG13_INVX2 +XI13<0> NADR<0> PADR<0> VDD VSS / RSC_IHPSG13_INVX2 +XI3<1> padr_int<1> NADR<1> VDD VSS / RSC_IHPSG13_INVX2 +XI3<0> padr_int<0> NADR<0> VDD VSS / RSC_IHPSG13_INVX2 +XI2<3> addr_n<3> ADDR_DEC<3> VDD VSS / RSC_IHPSG13_INVX2 +XI2<2> addr_n<2> ADDR_DEC<2> VDD VSS / RSC_IHPSG13_INVX2 +XI2<1> addr_n<1> ADDR_DEC<1> VDD VSS / RSC_IHPSG13_INVX2 +XI2<0> addr_n<0> ADDR_DEC<0> VDD VSS / RSC_IHPSG13_INVX2 +XDFF<1> BIST_EN_I BIST_ADDR<1> ACLK_N ADDR<1> padr_int<1> net12<0> VDD ++ VSS / RSC_IHPSG13_DFNQMX2IX1 +XDFF<0> BIST_EN_I BIST_ADDR<0> ACLK_N ADDR<0> padr_int<0> net12<1> VDD ++ VSS / RSC_IHPSG13_DFNQMX2IX1 +XI15<5> VDD VSS / RSC_IHPSG13_FILLCAP4 +XI15<4> VDD VSS / RSC_IHPSG13_FILLCAP4 +XI15<3> VDD VSS / RSC_IHPSG13_FILLCAP4 +XI15<2> VDD VSS / RSC_IHPSG13_FILLCAP4 +XI15<1> VDD VSS / RSC_IHPSG13_FILLCAP4 +XI19<4> VDD VSS / RSC_IHPSG13_FILLCAP4 +XI19<3> VDD VSS / RSC_IHPSG13_FILLCAP4 +XI19<2> VDD VSS / RSC_IHPSG13_FILLCAP4 +XI19<1> VDD VSS / RSC_IHPSG13_FILLCAP4 +.ENDS +.SUBCKT RM_IHPSG13_256x16_c2_2P_COLCTRL2 A_ADDR_DEC<3> A_ADDR_DEC<2> A_ADDR_DEC<1> ++ A_ADDR_DEC<0> A_BIST_BM_I A_BIST_DW_I A_BIST_EN_I A_BLC<3> A_BLC<2> A_BLC<1> ++ A_BLC<0> A_BLT<3> A_BLT<2> A_BLT<1> A_BLT<0> A_BM_I A_DCLK_B_L A_DCLK_B_R ++ A_DCLK_L A_DCLK_R A_DR_O A_DW_I A_RCLK_B_L A_RCLK_B_R A_RCLK_L A_RCLK_R ++ A_TIEH_O A_WCLK_B_L A_WCLK_B_R A_WCLK_L A_WCLK_R B_ADDR_DEC<3> B_ADDR_DEC<2> ++ B_ADDR_DEC<1> B_ADDR_DEC<0> B_BIST_BM_I B_BIST_DW_I B_BIST_EN_I B_BLC<3> ++ B_BLC<2> B_BLC<1> B_BLC<0> B_BLT<3> B_BLT<2> B_BLT<1> B_BLT<0> B_BM_I ++ B_DCLK_B_L B_DCLK_B_R B_DCLK_L B_DCLK_R B_DR_O B_DW_I B_RCLK_B_L B_RCLK_B_R ++ B_RCLK_L B_RCLK_R B_TIEH_O B_WCLK_B_L B_WCLK_B_R B_WCLK_L B_WCLK_R VDD ++ VSS +XB_DREG B_BIST_EN_I B_BIST_DW_I B_DCLK_B_L B_DW_I B_DI_R net046 VDD ++ VSS / RSC_IHPSG13_DFNQMX2IX1 +XB_BREG B_BIST_EN_I B_BIST_BM_I B_DCLK_B_L B_BM_I B_BM_R net045 VDD ++ VSS / RSC_IHPSG13_DFNQMX2IX1 +XA_DREG A_BIST_EN_I A_BIST_DW_I A_DCLK_B_L A_DW_I A_DI_R net22 VDD VSS ++ / RSC_IHPSG13_DFNQMX2IX1 +XA_BREG A_BIST_EN_I A_BIST_BM_I A_DCLK_B_L A_BM_I A_BM_R net23 VDD VSS ++ / RSC_IHPSG13_DFNQMX2IX1 +XB_CAPS VDD VSS / RSC_IHPSG13_FILLCAP4 +XA_CAPS VDD VSS / RSC_IHPSG13_FILLCAP4 +XB_I75 B_DI_R B_DO_WRITE_P B_WR_ONE VDD VSS / RSC_IHPSG13_AND2X2 +XB_I80 B_RCLK_B_L B_WCLK_B_L net041 VDD VSS / RSC_IHPSG13_AND2X2 +XB_I76 B_DI_N B_DO_WRITE_P B_WR_ZERO VDD VSS / RSC_IHPSG13_AND2X2 +XA_I80 A_RCLK_B_L A_WCLK_B_L net21 VDD VSS / RSC_IHPSG13_AND2X2 +XA_I75 A_DI_R A_DO_WRITE_P A_WR_ONE VDD VSS / RSC_IHPSG13_AND2X2 +XA_I76 A_DI_N A_DO_WRITE_P A_WR_ZERO VDD VSS / RSC_IHPSG13_AND2X2 +XB_I44 B_WCLK_B_L B_BM_N B_DO_WRITE_P VDD VSS / RSC_IHPSG13_NOR2X2 +XA_I44 A_WCLK_B_L A_BM_N A_DO_WRITE_P VDD VSS / RSC_IHPSG13_NOR2X2 +XB_I81 net041 B_PRE_N VDD VSS / RSC_IHPSG13_CINVX4_WN +XA_I81 net21 A_PRE_N VDD VSS / RSC_IHPSG13_CINVX4_WN +XB_BM_TIEH B_TIEH_O VDD VSS / RSC_IHPSG13_TIEH +XA_BM_TIEH A_TIEH_O VDD VSS / RSC_IHPSG13_TIEH +XA_I89 A_DCLK_B_L A_DCLK_B_R / RSC_IHPSG13_MET3RES +XA_I88 A_DCLK_L A_DCLK_R / RSC_IHPSG13_MET3RES +XA_I87 A_WCLK_L A_WCLK_R / RSC_IHPSG13_MET3RES +XA_I91 A_RCLK_B_L A_RCLK_B_R / RSC_IHPSG13_MET3RES +XB_I87 B_WCLK_L B_WCLK_R / RSC_IHPSG13_MET3RES +XB_I88 B_DCLK_L B_DCLK_R / RSC_IHPSG13_MET3RES +XB_I89 B_DCLK_B_L B_DCLK_B_R / RSC_IHPSG13_MET3RES +XB_I90 B_WCLK_B_L B_WCLK_B_R / RSC_IHPSG13_MET3RES +XB_R2 B_RCLK_L B_RCLK_R / RSC_IHPSG13_MET3RES +XB_I91 B_RCLK_B_L B_RCLK_B_R / RSC_IHPSG13_MET3RES +XA_R2 A_RCLK_L A_RCLK_R / RSC_IHPSG13_MET3RES +XA_I90 A_WCLK_B_L A_WCLK_B_R / RSC_IHPSG13_MET3RES +XAB_BLMUX A_BLC<3> A_BLC<2> A_BLC<1> A_BLC<0> A_BLC_SEL A_BLT<3> A_BLT<2> ++ A_BLT<1> A_BLT<0> A_BLT_SEL A_PRE_N A_ADDR_DEC<3> A_ADDR_DEC<2> ++ A_ADDR_DEC<1> A_ADDR_DEC<0> A_WR_ONE A_WR_ZERO B_BLC<3> B_BLC<2> B_BLC<1> ++ B_BLC<0> B_BLC_SEL B_BLT<3> B_BLT<2> B_BLT<1> B_BLT<0> B_BLT_SEL B_PRE_N ++ B_ADDR_DEC<3> B_ADDR_DEC<2> B_ADDR_DEC<1> B_ADDR_DEC<0> B_WR_ONE B_WR_ZERO ++ VDD VSS / RM_IHPSG13_256x16_c2_2P_BLDRV +XB_ISENSE B_SAE B_BLC_SEL B_BLT_SEL net039 net040 VDD VSS / ++ RSC_IHPSG13_DFPQD_MSAFFX2 +XA_ISENSE A_SAE A_BLC_SEL A_BLT_SEL net19 net20 VDD VSS / ++ RSC_IHPSG13_DFPQD_MSAFFX2 +XB_I78 B_RCLK_B_L B_SAE VDD VSS / RSC_IHPSG13_CBUFX2 +XA_I78 A_RCLK_B_L A_SAE VDD VSS / RSC_IHPSG13_CBUFX2 +XB_I83 B_BM_R B_BM_N VDD VSS / RSC_IHPSG13_INVX2 +XB_I49 B_DI_R B_DI_N VDD VSS / RSC_IHPSG13_INVX2 +XA_I83 A_BM_R A_BM_N VDD VSS / RSC_IHPSG13_INVX2 +XA_I49 A_DI_R A_DI_N VDD VSS / RSC_IHPSG13_INVX2 +XB_I51 net039 B_DR_O VDD VSS / RSC_IHPSG13_INVX4 +XA_I51 net19 A_DR_O VDD VSS / RSC_IHPSG13_INVX4 +XA_I69 A_DCLK_L A_DCLK_B_L VDD VSS / RSC_IHPSG13_CINVX2 +XA_I50 A_WCLK_L A_WCLK_B_L VDD VSS / RSC_IHPSG13_CINVX2 +XA_EBUF A_RCLK_L A_RCLK_B_L VDD VSS / RSC_IHPSG13_CINVX2 +XB_EBUF B_RCLK_L B_RCLK_B_L VDD VSS / RSC_IHPSG13_CINVX2 +XB_I50 B_WCLK_L B_WCLK_B_L VDD VSS / RSC_IHPSG13_CINVX2 +XB_I69 B_DCLK_L B_DCLK_B_L VDD VSS / RSC_IHPSG13_CINVX2 +.ENDS +.SUBCKT RM_IHPSG13_256x16_c2_2P_COLDRV13_FILL4C2 VDD VSS +XI0<2> VDD VSS / RSC_IHPSG13_FILLCAP4 +XI0<1> VDD VSS / RSC_IHPSG13_FILLCAP4 +.ENDS + + +.SUBCKT RM_IHPSG13_256x16_c2_2P_ROWDEC7 ADDR_N_I<6> ADDR_N_I<5> ADDR_N_I<4> ADDR_N_I<3> ++ ADDR_N_I<2> ADDR_N_I<1> ADDR_N_I<0> CS_I ECLK_I WL_O<127> WL_O<126> ++ WL_O<125> WL_O<124> WL_O<123> WL_O<122> WL_O<121> WL_O<120> WL_O<119> ++ WL_O<118> WL_O<117> WL_O<116> WL_O<115> WL_O<114> WL_O<113> WL_O<112> ++ WL_O<111> WL_O<110> WL_O<109> WL_O<108> WL_O<107> WL_O<106> WL_O<105> ++ WL_O<104> WL_O<103> WL_O<102> WL_O<101> WL_O<100> WL_O<99> WL_O<98> WL_O<97> ++ WL_O<96> WL_O<95> WL_O<94> WL_O<93> WL_O<92> WL_O<91> WL_O<90> WL_O<89> ++ WL_O<88> WL_O<87> WL_O<86> WL_O<85> WL_O<84> WL_O<83> WL_O<82> WL_O<81> ++ WL_O<80> WL_O<79> WL_O<78> WL_O<77> WL_O<76> WL_O<75> WL_O<74> WL_O<73> ++ WL_O<72> WL_O<71> WL_O<70> WL_O<69> WL_O<68> WL_O<67> WL_O<66> WL_O<65> ++ WL_O<64> WL_O<63> WL_O<62> WL_O<61> WL_O<60> WL_O<59> WL_O<58> WL_O<57> ++ WL_O<56> WL_O<55> WL_O<54> WL_O<53> WL_O<52> WL_O<51> WL_O<50> WL_O<49> ++ WL_O<48> WL_O<47> WL_O<46> WL_O<45> WL_O<44> WL_O<43> WL_O<42> WL_O<41> ++ WL_O<40> WL_O<39> WL_O<38> WL_O<37> WL_O<36> WL_O<35> WL_O<34> WL_O<33> ++ WL_O<32> WL_O<31> WL_O<30> WL_O<29> WL_O<28> WL_O<27> WL_O<26> WL_O<25> ++ WL_O<24> WL_O<23> WL_O<22> WL_O<21> WL_O<20> WL_O<19> WL_O<18> WL_O<17> ++ WL_O<16> WL_O<15> WL_O<14> WL_O<13> WL_O<12> WL_O<11> WL_O<10> WL_O<9> ++ WL_O<8> WL_O<7> WL_O<6> WL_O<5> WL_O<4> WL_O<3> WL_O<2> WL_O<1> WL_O<0> ++ VDD VSS +XSEL<7> ADDR_N_I<3> ADDR_N_I<2> ADDR_N_I<1> ADDR_N_I<0> CS00<7> ECLK_H<7> ++ ECLK_H<8> ECLK_B<7> ECLK_B<8> WL_O<127> WL_O<126> WL_O<125> WL_O<124> ++ WL_O<123> WL_O<122> WL_O<121> WL_O<120> WL_O<119> WL_O<118> WL_O<117> ++ WL_O<116> WL_O<115> WL_O<114> WL_O<113> WL_O<112> VDD VSS / ++ RM_IHPSG13_256x16_c2_2P_DEC04 +XSEL<6> ADDR_N_I<3> ADDR_N_I<2> ADDR_N_I<1> ADDR_N_I<0> CS00<6> ECLK_H<6> ++ ECLK_H<7> ECLK_B<6> ECLK_B<7> WL_O<111> WL_O<110> WL_O<109> WL_O<108> ++ WL_O<107> WL_O<106> WL_O<105> WL_O<104> WL_O<103> WL_O<102> WL_O<101> ++ WL_O<100> WL_O<99> WL_O<98> WL_O<97> WL_O<96> VDD VSS / ++ RM_IHPSG13_256x16_c2_2P_DEC04 +XSEL<5> ADDR_N_I<3> ADDR_N_I<2> ADDR_N_I<1> ADDR_N_I<0> CS00<5> ECLK_H<5> ++ ECLK_H<6> ECLK_B<5> ECLK_B<6> WL_O<95> WL_O<94> WL_O<93> WL_O<92> WL_O<91> ++ WL_O<90> WL_O<89> WL_O<88> WL_O<87> WL_O<86> WL_O<85> WL_O<84> WL_O<83> ++ WL_O<82> WL_O<81> WL_O<80> VDD VSS / RM_IHPSG13_256x16_c2_2P_DEC04 +XSEL<4> ADDR_N_I<3> ADDR_N_I<2> ADDR_N_I<1> ADDR_N_I<0> CS00<4> ECLK_H<4> ++ ECLK_H<5> ECLK_B<4> ECLK_B<5> WL_O<79> WL_O<78> WL_O<77> WL_O<76> WL_O<75> ++ WL_O<74> WL_O<73> WL_O<72> WL_O<71> WL_O<70> WL_O<69> WL_O<68> WL_O<67> ++ WL_O<66> WL_O<65> WL_O<64> VDD VSS / RM_IHPSG13_256x16_c2_2P_DEC04 +XSEL<3> ADDR_N_I<3> ADDR_N_I<2> ADDR_N_I<1> ADDR_N_I<0> CS00<3> ECLK_H<3> ++ ECLK_H<4> ECLK_B<3> ECLK_B<4> WL_O<63> WL_O<62> WL_O<61> WL_O<60> WL_O<59> ++ WL_O<58> WL_O<57> WL_O<56> WL_O<55> WL_O<54> WL_O<53> WL_O<52> WL_O<51> ++ WL_O<50> WL_O<49> WL_O<48> VDD VSS / RM_IHPSG13_256x16_c2_2P_DEC04 +XSEL<2> ADDR_N_I<3> ADDR_N_I<2> ADDR_N_I<1> ADDR_N_I<0> CS00<2> ECLK_H<2> ++ ECLK_H<3> ECLK_B<2> ECLK_B<3> WL_O<47> WL_O<46> WL_O<45> WL_O<44> WL_O<43> ++ WL_O<42> WL_O<41> WL_O<40> WL_O<39> WL_O<38> WL_O<37> WL_O<36> WL_O<35> ++ WL_O<34> WL_O<33> WL_O<32> VDD VSS / RM_IHPSG13_256x16_c2_2P_DEC04 +XSEL<1> ADDR_N_I<3> ADDR_N_I<2> ADDR_N_I<1> ADDR_N_I<0> CS00<1> ECLK_H<1> ++ ECLK_H<2> ECLK_B<1> ECLK_B<2> WL_O<31> WL_O<30> WL_O<29> WL_O<28> WL_O<27> ++ WL_O<26> WL_O<25> WL_O<24> WL_O<23> WL_O<22> WL_O<21> WL_O<20> WL_O<19> ++ WL_O<18> WL_O<17> WL_O<16> VDD VSS / RM_IHPSG13_256x16_c2_2P_DEC04 +XSEL<0> ADDR_N_I<3> ADDR_N_I<2> ADDR_N_I<1> ADDR_N_I<0> CS00<0> ECLK_I ++ ECLK_H<1> ECLK_B<0> ECLK_B<1> WL_O<15> WL_O<14> WL_O<13> WL_O<12> WL_O<11> ++ WL_O<10> WL_O<9> WL_O<8> WL_O<7> WL_O<6> WL_O<5> WL_O<4> WL_O<3> WL_O<2> ++ WL_O<1> WL_O<0> VDD VSS / RM_IHPSG13_256x16_c2_2P_DEC04 +XDEC11<1> ADDR_N_I<5> ADDR_N_I<4> CS04<1> CS00<7> VDD VSS / ++ RM_IHPSG13_256x16_c2_2P_DEC03 +XDEC11<0> ADDR_N_I<5> ADDR_N_I<4> CS04<0> CS00<3> VDD VSS / ++ RM_IHPSG13_256x16_c2_2P_DEC03 +XDEC01<2> ADDR_N_I<7> ADDR_N_I<6> CS_I CS04<1> VDD VSS / ++ RM_IHPSG13_256x16_c2_2P_DEC01 +XDEC01<1> ADDR_N_I<5> ADDR_N_I<4> CS04<1> CS00<5> VDD VSS / ++ RM_IHPSG13_256x16_c2_2P_DEC01 +XDEC01<0> ADDR_N_I<5> ADDR_N_I<4> CS04<0> CS00<1> VDD VSS / ++ RM_IHPSG13_256x16_c2_2P_DEC01 +XL2<66> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<65> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<64> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<63> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<62> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<61> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<60> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<59> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<58> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<57> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<56> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<55> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<54> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<53> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<52> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<51> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<50> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<49> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<48> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<47> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<46> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<45> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<44> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<43> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<42> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<41> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<40> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<39> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<38> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<37> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<36> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<35> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<34> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<33> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<32> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<31> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<30> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<29> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<28> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<27> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<26> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<25> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<24> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<23> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<22> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<21> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<20> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<19> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<18> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<17> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<16> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<15> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<14> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<13> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<12> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<11> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<10> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<9> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<8> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<7> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<6> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<5> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<4> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<3> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<2> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<1> VDD VSS / RSC_IHPSG13_FILLCAP8 +XDEC10<1> ADDR_N_I<5> ADDR_N_I<4> CS04<1> CS00<6> VDD VSS / ++ RM_IHPSG13_256x16_c2_2P_DEC02 +XDEC10<0> ADDR_N_I<5> ADDR_N_I<4> CS04<0> CS00<2> VDD VSS / ++ RM_IHPSG13_256x16_c2_2P_DEC02 +XDEC00<2> ADDR_N_I<7> ADDR_N_I<6> CS_I CS04<0> VDD VSS / ++ RM_IHPSG13_256x16_c2_2P_DEC00 +XDEC00<1> ADDR_N_I<5> ADDR_N_I<4> CS04<1> CS00<4> VDD VSS / ++ RM_IHPSG13_256x16_c2_2P_DEC00 +XDEC00<0> ADDR_N_I<5> ADDR_N_I<4> CS04<0> CS00<0> VDD VSS / ++ RM_IHPSG13_256x16_c2_2P_DEC00 +XI0 ADDR_N_I<7> VDD VSS / RSC_IHPSG13_TIEL +.ENDS +.SUBCKT RM_IHPSG13_256x16_c2_2P_ROWREG7 ACLK_N_I ADDR_I<6> ADDR_I<5> ADDR_I<4> ADDR_I<3> ++ ADDR_I<2> ADDR_I<1> ADDR_I<0> ADDR_N_O<6> ADDR_N_O<5> ADDR_N_O<4> ++ ADDR_N_O<3> ADDR_N_O<2> ADDR_N_O<1> ADDR_N_O<0> BIST_ADDR_I<6> ++ BIST_ADDR_I<5> BIST_ADDR_I<4> BIST_ADDR_I<3> BIST_ADDR_I<2> BIST_ADDR_I<1> ++ BIST_ADDR_I<0> BIST_EN_I VDD VSS +XINV<6> q_int<6> qn_int<6> VDD VSS / RSC_IHPSG13_CINVX2 +XINV<5> q_int<5> qn_int<5> VDD VSS / RSC_IHPSG13_CINVX2 +XINV<4> q_int<4> qn_int<4> VDD VSS / RSC_IHPSG13_CINVX2 +XINV<3> q_int<3> qn_int<3> VDD VSS / RSC_IHPSG13_CINVX2 +XINV<2> q_int<2> qn_int<2> VDD VSS / RSC_IHPSG13_CINVX2 +XINV<1> q_int<1> qn_int<1> VDD VSS / RSC_IHPSG13_CINVX2 +XINV<0> q_int<0> qn_int<0> VDD VSS / RSC_IHPSG13_CINVX2 +XDRV<6> qn_int<6> ADDR_N_O<6> VDD VSS / RSC_IHPSG13_CINVX8 +XDRV<5> qn_int<5> ADDR_N_O<5> VDD VSS / RSC_IHPSG13_CINVX8 +XDRV<4> qn_int<4> ADDR_N_O<4> VDD VSS / RSC_IHPSG13_CINVX8 +XDRV<3> qn_int<3> ADDR_N_O<3> VDD VSS / RSC_IHPSG13_CINVX8 +XDRV<2> qn_int<2> ADDR_N_O<2> VDD VSS / RSC_IHPSG13_CINVX8 +XDRV<1> qn_int<1> ADDR_N_O<1> VDD VSS / RSC_IHPSG13_CINVX8 +XDRV<0> qn_int<0> ADDR_N_O<0> VDD VSS / RSC_IHPSG13_CINVX8 +XDFF<6> BIST_EN_I BIST_ADDR_I<6> ACLK_N_I ADDR_I<6> q_int<6> net2<0> VDD ++ VSS / RSC_IHPSG13_DFNQMX2IX1 +XDFF<5> BIST_EN_I BIST_ADDR_I<5> ACLK_N_I ADDR_I<5> q_int<5> net2<1> VDD ++ VSS / RSC_IHPSG13_DFNQMX2IX1 +XDFF<4> BIST_EN_I BIST_ADDR_I<4> ACLK_N_I ADDR_I<4> q_int<4> net2<2> VDD ++ VSS / RSC_IHPSG13_DFNQMX2IX1 +XDFF<3> BIST_EN_I BIST_ADDR_I<3> ACLK_N_I ADDR_I<3> q_int<3> net2<3> VDD ++ VSS / RSC_IHPSG13_DFNQMX2IX1 +XDFF<2> BIST_EN_I BIST_ADDR_I<2> ACLK_N_I ADDR_I<2> q_int<2> net2<4> VDD ++ VSS / RSC_IHPSG13_DFNQMX2IX1 +XDFF<1> BIST_EN_I BIST_ADDR_I<1> ACLK_N_I ADDR_I<1> q_int<1> net2<5> VDD ++ VSS / RSC_IHPSG13_DFNQMX2IX1 +XDFF<0> BIST_EN_I BIST_ADDR_I<0> ACLK_N_I ADDR_I<0> q_int<0> net2<6> VDD ++ VSS / RSC_IHPSG13_DFNQMX2IX1 +XI11<7> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI11<6> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI11<5> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI11<4> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI11<3> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI11<2> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI11<1> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI11<0> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI12<1> VDD VSS / RSC_IHPSG13_FILLCAP4 +XI12<0> VDD VSS / RSC_IHPSG13_FILLCAP4 +.ENDS + +.SUBCKT RM_IHPSG13_256x16_c2_2P_ROWDEC4 ADDR_N_I<3> ADDR_N_I<2> ADDR_N_I<1> ADDR_N_I<0> ++ CS_I ECLK_I WL_O<15> WL_O<14> WL_O<13> WL_O<12> WL_O<11> WL_O<10> WL_O<9> ++ WL_O<8> WL_O<7> WL_O<6> WL_O<5> WL_O<4> WL_O<3> WL_O<2> WL_O<1> WL_O<0> ++ VDD VSS +XL2<12> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<11> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<10> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<9> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<8> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<7> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<6> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<5> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<4> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<3> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<2> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<1> VDD VSS / RSC_IHPSG13_FILLCAP8 +XSEL ADDR_N_I<3> ADDR_N_I<2> ADDR_N_I<1> ADDR_N_I<0> CS_I ECLK_I ECLK_H<1> ++ ECLK_B<0> ECLK_B<1> WL_O<15> WL_O<14> WL_O<13> WL_O<12> WL_O<11> WL_O<10> ++ WL_O<9> WL_O<8> WL_O<7> WL_O<6> WL_O<5> WL_O<4> WL_O<3> WL_O<2> WL_O<1> ++ WL_O<0> VDD VSS / RM_IHPSG13_256x16_c2_2P_DEC04 +.ENDS +.SUBCKT RM_IHPSG13_256x16_c2_2P_ROWREG4 ACLK_N_I ADDR_I<3> ADDR_I<2> ADDR_I<1> ADDR_I<0> ++ ADDR_N_O<3> ADDR_N_O<2> ADDR_N_O<1> ADDR_N_O<0> BIST_ADDR_I<3> ++ BIST_ADDR_I<2> BIST_ADDR_I<1> BIST_ADDR_I<0> BIST_EN_I VDD VSS +XINV<3> q_int<3> qn_int<3> VDD VSS / RSC_IHPSG13_CINVX2 +XINV<2> q_int<2> qn_int<2> VDD VSS / RSC_IHPSG13_CINVX2 +XINV<1> q_int<1> qn_int<1> VDD VSS / RSC_IHPSG13_CINVX2 +XINV<0> q_int<0> qn_int<0> VDD VSS / RSC_IHPSG13_CINVX2 +XDRV<3> qn_int<3> ADDR_N_O<3> VDD VSS / RSC_IHPSG13_CINVX8 +XDRV<2> qn_int<2> ADDR_N_O<2> VDD VSS / RSC_IHPSG13_CINVX8 +XDRV<1> qn_int<1> ADDR_N_O<1> VDD VSS / RSC_IHPSG13_CINVX8 +XDRV<0> qn_int<0> ADDR_N_O<0> VDD VSS / RSC_IHPSG13_CINVX8 +XDFF<3> BIST_EN_I BIST_ADDR_I<3> ACLK_N_I ADDR_I<3> q_int<3> net7<0> VDD ++ VSS / RSC_IHPSG13_DFNQMX2IX1 +XDFF<2> BIST_EN_I BIST_ADDR_I<2> ACLK_N_I ADDR_I<2> q_int<2> net7<1> VDD ++ VSS / RSC_IHPSG13_DFNQMX2IX1 +XDFF<1> BIST_EN_I BIST_ADDR_I<1> ACLK_N_I ADDR_I<1> q_int<1> net7<2> VDD ++ VSS / RSC_IHPSG13_DFNQMX2IX1 +XDFF<0> BIST_EN_I BIST_ADDR_I<0> ACLK_N_I ADDR_I<0> q_int<0> net7<3> VDD ++ VSS / RSC_IHPSG13_DFNQMX2IX1 +XI11<20> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI11<19> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI11<18> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI11<17> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI11<16> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI11<15> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI11<14> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI11<13> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI11<12> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI11<11> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI11<10> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI11<9> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI11<8> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI11<7> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI11<6> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI11<5> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI11<4> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI11<3> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI11<2> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI11<1> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI12<4> VDD VSS / RSC_IHPSG13_FILLCAP4 +XI12<3> VDD VSS / RSC_IHPSG13_FILLCAP4 +XI12<2> VDD VSS / RSC_IHPSG13_FILLCAP4 +XI12<1> VDD VSS / RSC_IHPSG13_FILLCAP4 +XI12<0> VDD VSS / RSC_IHPSG13_FILLCAP4 +.ENDS + + +.SUBCKT RM_IHPSG13_256x16_c2_1P_BITKIT_TAP BLC BLT NW PW VDD VSS +.ENDS +.SUBCKT RM_IHPSG13_256x16_c2_1P_BITKIT_16x2_TAP A_BLC<1> A_BLC<0> A_BLT<1> A_BLT<0> ++ VDD_CORE VSS +XITAP<1> A_BLC<1> A_BLT<1> VDD_CORE VSS VDD_CORE VSS ++ / RM_IHPSG13_256x16_c2_1P_BITKIT_TAP +XITAP<0> A_BLC<0> A_BLT<0> VDD_CORE VSS VDD_CORE VSS ++ / RM_IHPSG13_256x16_c2_1P_BITKIT_TAP +XIEDGEBP_COL1<1> BLC<1> BLT<1> VDD_CORE VSS VDD_CORE ++ VSS / RM_IHPSG13_256x16_c2_1P_BITKIT_EDGE_TB +XIEDGEBP_COL1<0> BLC<1> BLT<1> VDD_CORE VSS VDD_CORE ++ VSS / RM_IHPSG13_256x16_c2_1P_BITKIT_EDGE_TB +XIEDGEBP_COL2<1> BLC<0> BLT<0> VDD_CORE VSS VDD_CORE ++ VSS / RM_IHPSG13_256x16_c2_1P_BITKIT_EDGE_TB +XIEDGEBP_COL2<0> BLC<0> BLT<0> VDD_CORE VSS VDD_CORE ++ VSS / RM_IHPSG13_256x16_c2_1P_BITKIT_EDGE_TB +.ENDS +.SUBCKT RM_IHPSG13_256x16_c2_1P_BITKIT_16x2_TAP_LR VDD_CORE VSS +XCORNER<1> VDD_CORE VSS VDD_CORE VSS / ++ RM_IHPSG13_256x16_c2_1P_BITKIT_CORNER +XCORNER<0> VDD_CORE VSS VDD_CORE VSS / ++ RM_IHPSG13_256x16_c2_1P_BITKIT_CORNER +XTAP_BORDER VDD_CORE VSS VDD_CORE VSS / ++ RM_IHPSG13_256x16_c2_1P_BITKIT_TAP_LR +.ENDS +.SUBCKT RM_IHPSG13_256x16_c2_1P_DEC03 ADDR<1> ADDR<0> CS CS_OUT VDD VSS +XDECINV net1 CS_OUT VDD VSS / RSC_IHPSG13_INVX4 +XI0 VDD VSS / RSC_IHPSG13_FILLCAP4 +XDEC ADDR<1> ADDR<0> CS net1 VDD VSS / RSC_IHPSG13_NAND3X2 +.ENDS +.SUBCKT RM_IHPSG13_256x16_c2_1P_DEC02 ADDR<1> ADDR<0> CS CS_OUT VDD VSS +XDECINV net1 CS_OUT VDD VSS / RSC_IHPSG13_INVX4 +XDEC ADDR<1> NADDR<0> CS net1 VDD VSS / RSC_IHPSG13_NAND3X2 +XI2 VDD VSS / RSC_IHPSG13_FILLCAP4 +XADDRINV ADDR<0> NADDR<0> VDD VSS / RSC_IHPSG13_INVX2 +.ENDS +.SUBCKT RM_IHPSG13_256x16_c2_1P_ROWDEC8 ADDR_N_I<7> ADDR_N_I<6> ADDR_N_I<5> ADDR_N_I<4> ++ ADDR_N_I<3> ADDR_N_I<2> ADDR_N_I<1> ADDR_N_I<0> CS_I ECLK_I WL_O<255> ++ WL_O<254> WL_O<253> WL_O<252> WL_O<251> WL_O<250> WL_O<249> WL_O<248> ++ WL_O<247> WL_O<246> WL_O<245> WL_O<244> WL_O<243> WL_O<242> WL_O<241> ++ WL_O<240> WL_O<239> WL_O<238> WL_O<237> WL_O<236> WL_O<235> WL_O<234> ++ WL_O<233> WL_O<232> WL_O<231> WL_O<230> WL_O<229> WL_O<228> WL_O<227> ++ WL_O<226> WL_O<225> WL_O<224> WL_O<223> WL_O<222> WL_O<221> WL_O<220> ++ WL_O<219> WL_O<218> WL_O<217> WL_O<216> WL_O<215> WL_O<214> WL_O<213> ++ WL_O<212> WL_O<211> WL_O<210> WL_O<209> WL_O<208> WL_O<207> WL_O<206> ++ WL_O<205> WL_O<204> WL_O<203> WL_O<202> WL_O<201> WL_O<200> WL_O<199> ++ WL_O<198> WL_O<197> WL_O<196> WL_O<195> WL_O<194> WL_O<193> WL_O<192> ++ WL_O<191> WL_O<190> WL_O<189> WL_O<188> WL_O<187> WL_O<186> WL_O<185> ++ WL_O<184> WL_O<183> WL_O<182> WL_O<181> WL_O<180> WL_O<179> WL_O<178> ++ WL_O<177> WL_O<176> WL_O<175> WL_O<174> WL_O<173> WL_O<172> WL_O<171> ++ WL_O<170> WL_O<169> WL_O<168> WL_O<167> WL_O<166> WL_O<165> WL_O<164> ++ WL_O<163> WL_O<162> WL_O<161> WL_O<160> WL_O<159> WL_O<158> WL_O<157> ++ WL_O<156> WL_O<155> WL_O<154> WL_O<153> WL_O<152> WL_O<151> WL_O<150> ++ WL_O<149> WL_O<148> WL_O<147> WL_O<146> WL_O<145> WL_O<144> WL_O<143> ++ WL_O<142> WL_O<141> WL_O<140> WL_O<139> WL_O<138> WL_O<137> WL_O<136> ++ WL_O<135> WL_O<134> WL_O<133> WL_O<132> WL_O<131> WL_O<130> WL_O<129> ++ WL_O<128> WL_O<127> WL_O<126> WL_O<125> WL_O<124> WL_O<123> WL_O<122> ++ WL_O<121> WL_O<120> WL_O<119> WL_O<118> WL_O<117> WL_O<116> WL_O<115> ++ WL_O<114> WL_O<113> WL_O<112> WL_O<111> WL_O<110> WL_O<109> WL_O<108> ++ WL_O<107> WL_O<106> WL_O<105> WL_O<104> WL_O<103> WL_O<102> WL_O<101> ++ WL_O<100> WL_O<99> WL_O<98> WL_O<97> WL_O<96> WL_O<95> WL_O<94> WL_O<93> ++ WL_O<92> WL_O<91> WL_O<90> WL_O<89> WL_O<88> WL_O<87> WL_O<86> WL_O<85> ++ WL_O<84> WL_O<83> WL_O<82> WL_O<81> WL_O<80> WL_O<79> WL_O<78> WL_O<77> ++ WL_O<76> WL_O<75> WL_O<74> WL_O<73> WL_O<72> WL_O<71> WL_O<70> WL_O<69> ++ WL_O<68> WL_O<67> WL_O<66> WL_O<65> WL_O<64> WL_O<63> WL_O<62> WL_O<61> ++ WL_O<60> WL_O<59> WL_O<58> WL_O<57> WL_O<56> WL_O<55> WL_O<54> WL_O<53> ++ WL_O<52> WL_O<51> WL_O<50> WL_O<49> WL_O<48> WL_O<47> WL_O<46> WL_O<45> ++ WL_O<44> WL_O<43> WL_O<42> WL_O<41> WL_O<40> WL_O<39> WL_O<38> WL_O<37> ++ WL_O<36> WL_O<35> WL_O<34> WL_O<33> WL_O<32> WL_O<31> WL_O<30> WL_O<29> ++ WL_O<28> WL_O<27> WL_O<26> WL_O<25> WL_O<24> WL_O<23> WL_O<22> WL_O<21> ++ WL_O<20> WL_O<19> WL_O<18> WL_O<17> WL_O<16> WL_O<15> WL_O<14> WL_O<13> ++ WL_O<12> WL_O<11> WL_O<10> WL_O<9> WL_O<8> WL_O<7> WL_O<6> WL_O<5> WL_O<4> ++ WL_O<3> WL_O<2> WL_O<1> WL_O<0> VDD VSS +XDEC11<4> ADDR_N_I<7> ADDR_N_I<6> CS_I CS04<3> VDD VSS / ++ RM_IHPSG13_256x16_c2_1P_DEC03 +XDEC11<3> ADDR_N_I<5> ADDR_N_I<4> CS04<3> CS00<15> VDD VSS / ++ RM_IHPSG13_256x16_c2_1P_DEC03 +XDEC11<2> ADDR_N_I<5> ADDR_N_I<4> CS04<2> CS00<11> VDD VSS / ++ RM_IHPSG13_256x16_c2_1P_DEC03 +XDEC11<1> ADDR_N_I<5> ADDR_N_I<4> CS04<1> CS00<7> VDD VSS / ++ RM_IHPSG13_256x16_c2_1P_DEC03 +XDEC11<0> ADDR_N_I<5> ADDR_N_I<4> CS04<0> CS00<3> VDD VSS / ++ RM_IHPSG13_256x16_c2_1P_DEC03 +XL2<88> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<87> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<86> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<85> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<84> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<83> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<82> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<81> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<80> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<79> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<78> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<77> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<76> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<75> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<74> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<73> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<72> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<71> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<70> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<69> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<68> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<67> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<66> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<65> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<64> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<63> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<62> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<61> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<60> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<59> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<58> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<57> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<56> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<55> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<54> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<53> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<52> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<51> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<50> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<49> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<48> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<47> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<46> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<45> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<44> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<43> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<42> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<41> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<40> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<39> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<38> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<37> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<36> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<35> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<34> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<33> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<32> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<31> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<30> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<29> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<28> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<27> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<26> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<25> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<24> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<23> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<22> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<21> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<20> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<19> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<18> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<17> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<16> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<15> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<14> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<13> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<12> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<11> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<10> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<9> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<8> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<7> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<6> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<5> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<4> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<3> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<2> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<1> VDD VSS / RSC_IHPSG13_FILLCAP8 +XDEC10<4> ADDR_N_I<7> ADDR_N_I<6> CS_I CS04<2> VDD VSS / ++ RM_IHPSG13_256x16_c2_1P_DEC02 +XDEC10<3> ADDR_N_I<5> ADDR_N_I<4> CS04<3> CS00<14> VDD VSS / ++ RM_IHPSG13_256x16_c2_1P_DEC02 +XDEC10<2> ADDR_N_I<5> ADDR_N_I<4> CS04<2> CS00<10> VDD VSS / ++ RM_IHPSG13_256x16_c2_1P_DEC02 +XDEC10<1> ADDR_N_I<5> ADDR_N_I<4> CS04<1> CS00<6> VDD VSS / ++ RM_IHPSG13_256x16_c2_1P_DEC02 +XDEC10<0> ADDR_N_I<5> ADDR_N_I<4> CS04<0> CS00<2> VDD VSS / ++ RM_IHPSG13_256x16_c2_1P_DEC02 +XDEC00<4> ADDR_N_I<7> ADDR_N_I<6> CS_I CS04<0> VDD VSS / ++ RM_IHPSG13_256x16_c2_1P_DEC00 +XDEC00<3> ADDR_N_I<5> ADDR_N_I<4> CS04<3> CS00<12> VDD VSS / ++ RM_IHPSG13_256x16_c2_1P_DEC00 +XDEC00<2> ADDR_N_I<5> ADDR_N_I<4> CS04<2> CS00<8> VDD VSS / ++ RM_IHPSG13_256x16_c2_1P_DEC00 +XDEC00<1> ADDR_N_I<5> ADDR_N_I<4> CS04<1> CS00<4> VDD VSS / ++ RM_IHPSG13_256x16_c2_1P_DEC00 +XDEC00<0> ADDR_N_I<5> ADDR_N_I<4> CS04<0> CS00<0> VDD VSS / ++ RM_IHPSG13_256x16_c2_1P_DEC00 +XSEL<15> ADDR_N_I<3> ADDR_N_I<2> ADDR_N_I<1> ADDR_N_I<0> CS00<15> ECLK_H<15> ++ ECLK_H<16> ECLK_B<15> ECLK_B<16> WL_O<255> WL_O<254> WL_O<253> WL_O<252> ++ WL_O<251> WL_O<250> WL_O<249> WL_O<248> WL_O<247> WL_O<246> WL_O<245> ++ WL_O<244> WL_O<243> WL_O<242> WL_O<241> WL_O<240> VDD VSS / ++ RM_IHPSG13_256x16_c2_1P_DEC04 +XSEL<14> ADDR_N_I<3> ADDR_N_I<2> ADDR_N_I<1> ADDR_N_I<0> CS00<14> ECLK_H<14> ++ ECLK_H<15> ECLK_B<14> ECLK_B<15> WL_O<239> WL_O<238> WL_O<237> WL_O<236> ++ WL_O<235> WL_O<234> WL_O<233> WL_O<232> WL_O<231> WL_O<230> WL_O<229> ++ WL_O<228> WL_O<227> WL_O<226> WL_O<225> WL_O<224> VDD VSS / ++ RM_IHPSG13_256x16_c2_1P_DEC04 +XSEL<13> ADDR_N_I<3> ADDR_N_I<2> ADDR_N_I<1> ADDR_N_I<0> CS00<13> ECLK_H<13> ++ ECLK_H<14> ECLK_B<13> ECLK_B<14> WL_O<223> WL_O<222> WL_O<221> WL_O<220> ++ WL_O<219> WL_O<218> WL_O<217> WL_O<216> WL_O<215> WL_O<214> WL_O<213> ++ WL_O<212> WL_O<211> WL_O<210> WL_O<209> WL_O<208> VDD VSS / ++ RM_IHPSG13_256x16_c2_1P_DEC04 +XSEL<12> ADDR_N_I<3> ADDR_N_I<2> ADDR_N_I<1> ADDR_N_I<0> CS00<12> ECLK_H<12> ++ ECLK_H<13> ECLK_B<12> ECLK_B<13> WL_O<207> WL_O<206> WL_O<205> WL_O<204> ++ WL_O<203> WL_O<202> WL_O<201> WL_O<200> WL_O<199> WL_O<198> WL_O<197> ++ WL_O<196> WL_O<195> WL_O<194> WL_O<193> WL_O<192> VDD VSS / ++ RM_IHPSG13_256x16_c2_1P_DEC04 +XSEL<11> ADDR_N_I<3> ADDR_N_I<2> ADDR_N_I<1> ADDR_N_I<0> CS00<11> ECLK_H<11> ++ ECLK_H<12> ECLK_B<11> ECLK_B<12> WL_O<191> WL_O<190> WL_O<189> WL_O<188> ++ WL_O<187> WL_O<186> WL_O<185> WL_O<184> WL_O<183> WL_O<182> WL_O<181> ++ WL_O<180> WL_O<179> WL_O<178> WL_O<177> WL_O<176> VDD VSS / ++ RM_IHPSG13_256x16_c2_1P_DEC04 +XSEL<10> ADDR_N_I<3> ADDR_N_I<2> ADDR_N_I<1> ADDR_N_I<0> CS00<10> ECLK_H<10> ++ ECLK_H<11> ECLK_B<10> ECLK_B<11> WL_O<175> WL_O<174> WL_O<173> WL_O<172> ++ WL_O<171> WL_O<170> WL_O<169> WL_O<168> WL_O<167> WL_O<166> WL_O<165> ++ WL_O<164> WL_O<163> WL_O<162> WL_O<161> WL_O<160> VDD VSS / ++ RM_IHPSG13_256x16_c2_1P_DEC04 +XSEL<9> ADDR_N_I<3> ADDR_N_I<2> ADDR_N_I<1> ADDR_N_I<0> CS00<9> ECLK_H<9> ++ ECLK_H<10> ECLK_B<9> ECLK_B<10> WL_O<159> WL_O<158> WL_O<157> WL_O<156> ++ WL_O<155> WL_O<154> WL_O<153> WL_O<152> WL_O<151> WL_O<150> WL_O<149> ++ WL_O<148> WL_O<147> WL_O<146> WL_O<145> WL_O<144> VDD VSS / ++ RM_IHPSG13_256x16_c2_1P_DEC04 +XSEL<8> ADDR_N_I<3> ADDR_N_I<2> ADDR_N_I<1> ADDR_N_I<0> CS00<8> ECLK_H<8> ++ ECLK_H<9> ECLK_B<8> ECLK_B<9> WL_O<143> WL_O<142> WL_O<141> WL_O<140> ++ WL_O<139> WL_O<138> WL_O<137> WL_O<136> WL_O<135> WL_O<134> WL_O<133> ++ WL_O<132> WL_O<131> WL_O<130> WL_O<129> WL_O<128> VDD VSS / ++ RM_IHPSG13_256x16_c2_1P_DEC04 +XSEL<7> ADDR_N_I<3> ADDR_N_I<2> ADDR_N_I<1> ADDR_N_I<0> CS00<7> ECLK_H<7> ++ ECLK_H<8> ECLK_B<7> ECLK_B<8> WL_O<127> WL_O<126> WL_O<125> WL_O<124> ++ WL_O<123> WL_O<122> WL_O<121> WL_O<120> WL_O<119> WL_O<118> WL_O<117> ++ WL_O<116> WL_O<115> WL_O<114> WL_O<113> WL_O<112> VDD VSS / ++ RM_IHPSG13_256x16_c2_1P_DEC04 +XSEL<6> ADDR_N_I<3> ADDR_N_I<2> ADDR_N_I<1> ADDR_N_I<0> CS00<6> ECLK_H<6> ++ ECLK_H<7> ECLK_B<6> ECLK_B<7> WL_O<111> WL_O<110> WL_O<109> WL_O<108> ++ WL_O<107> WL_O<106> WL_O<105> WL_O<104> WL_O<103> WL_O<102> WL_O<101> ++ WL_O<100> WL_O<99> WL_O<98> WL_O<97> WL_O<96> VDD VSS / ++ RM_IHPSG13_256x16_c2_1P_DEC04 +XSEL<5> ADDR_N_I<3> ADDR_N_I<2> ADDR_N_I<1> ADDR_N_I<0> CS00<5> ECLK_H<5> ++ ECLK_H<6> ECLK_B<5> ECLK_B<6> WL_O<95> WL_O<94> WL_O<93> WL_O<92> WL_O<91> ++ WL_O<90> WL_O<89> WL_O<88> WL_O<87> WL_O<86> WL_O<85> WL_O<84> WL_O<83> ++ WL_O<82> WL_O<81> WL_O<80> VDD VSS / RM_IHPSG13_256x16_c2_1P_DEC04 +XSEL<4> ADDR_N_I<3> ADDR_N_I<2> ADDR_N_I<1> ADDR_N_I<0> CS00<4> ECLK_H<4> ++ ECLK_H<5> ECLK_B<4> ECLK_B<5> WL_O<79> WL_O<78> WL_O<77> WL_O<76> WL_O<75> ++ WL_O<74> WL_O<73> WL_O<72> WL_O<71> WL_O<70> WL_O<69> WL_O<68> WL_O<67> ++ WL_O<66> WL_O<65> WL_O<64> VDD VSS / RM_IHPSG13_256x16_c2_1P_DEC04 +XSEL<3> ADDR_N_I<3> ADDR_N_I<2> ADDR_N_I<1> ADDR_N_I<0> CS00<3> ECLK_H<3> ++ ECLK_H<4> ECLK_B<3> ECLK_B<4> WL_O<63> WL_O<62> WL_O<61> WL_O<60> WL_O<59> ++ WL_O<58> WL_O<57> WL_O<56> WL_O<55> WL_O<54> WL_O<53> WL_O<52> WL_O<51> ++ WL_O<50> WL_O<49> WL_O<48> VDD VSS / RM_IHPSG13_256x16_c2_1P_DEC04 +XSEL<2> ADDR_N_I<3> ADDR_N_I<2> ADDR_N_I<1> ADDR_N_I<0> CS00<2> ECLK_H<2> ++ ECLK_H<3> ECLK_B<2> ECLK_B<3> WL_O<47> WL_O<46> WL_O<45> WL_O<44> WL_O<43> ++ WL_O<42> WL_O<41> WL_O<40> WL_O<39> WL_O<38> WL_O<37> WL_O<36> WL_O<35> ++ WL_O<34> WL_O<33> WL_O<32> VDD VSS / RM_IHPSG13_256x16_c2_1P_DEC04 +XSEL<1> ADDR_N_I<3> ADDR_N_I<2> ADDR_N_I<1> ADDR_N_I<0> CS00<1> ECLK_H<1> ++ ECLK_H<2> ECLK_B<1> ECLK_B<2> WL_O<31> WL_O<30> WL_O<29> WL_O<28> WL_O<27> ++ WL_O<26> WL_O<25> WL_O<24> WL_O<23> WL_O<22> WL_O<21> WL_O<20> WL_O<19> ++ WL_O<18> WL_O<17> WL_O<16> VDD VSS / RM_IHPSG13_256x16_c2_1P_DEC04 +XSEL<0> ADDR_N_I<3> ADDR_N_I<2> ADDR_N_I<1> ADDR_N_I<0> CS00<0> ECLK_I ++ ECLK_H<1> ECLK_B<0> ECLK_B<1> WL_O<15> WL_O<14> WL_O<13> WL_O<12> WL_O<11> ++ WL_O<10> WL_O<9> WL_O<8> WL_O<7> WL_O<6> WL_O<5> WL_O<4> WL_O<3> WL_O<2> ++ WL_O<1> WL_O<0> VDD VSS / RM_IHPSG13_256x16_c2_1P_DEC04 +XDEC01<4> ADDR_N_I<7> ADDR_N_I<6> CS_I CS04<1> VDD VSS / ++ RM_IHPSG13_256x16_c2_1P_DEC01 +XDEC01<3> ADDR_N_I<5> ADDR_N_I<4> CS04<3> CS00<13> VDD VSS / ++ RM_IHPSG13_256x16_c2_1P_DEC01 +XDEC01<2> ADDR_N_I<5> ADDR_N_I<4> CS04<2> CS00<9> VDD VSS / ++ RM_IHPSG13_256x16_c2_1P_DEC01 +XDEC01<1> ADDR_N_I<5> ADDR_N_I<4> CS04<1> CS00<5> VDD VSS / ++ RM_IHPSG13_256x16_c2_1P_DEC01 +XDEC01<0> ADDR_N_I<5> ADDR_N_I<4> CS04<0> CS00<1> VDD VSS / ++ RM_IHPSG13_256x16_c2_1P_DEC01 +.ENDS +.SUBCKT RM_IHPSG13_256x16_c2_1P_ROWREG8 ACLK_N_I ADDR_I<7> ADDR_I<6> ADDR_I<5> ADDR_I<4> ++ ADDR_I<3> ADDR_I<2> ADDR_I<1> ADDR_I<0> ADDR_N_O<7> ADDR_N_O<6> ADDR_N_O<5> ++ ADDR_N_O<4> ADDR_N_O<3> ADDR_N_O<2> ADDR_N_O<1> ADDR_N_O<0> BIST_ADDR_I<7> ++ BIST_ADDR_I<6> BIST_ADDR_I<5> BIST_ADDR_I<4> BIST_ADDR_I<3> BIST_ADDR_I<2> ++ BIST_ADDR_I<1> BIST_ADDR_I<0> BIST_EN_I VDD VSS +XINV<7> q_int<7> qn_int<7> VDD VSS / RSC_IHPSG13_CINVX2 +XINV<6> q_int<6> qn_int<6> VDD VSS / RSC_IHPSG13_CINVX2 +XINV<5> q_int<5> qn_int<5> VDD VSS / RSC_IHPSG13_CINVX2 +XINV<4> q_int<4> qn_int<4> VDD VSS / RSC_IHPSG13_CINVX2 +XINV<3> q_int<3> qn_int<3> VDD VSS / RSC_IHPSG13_CINVX2 +XINV<2> q_int<2> qn_int<2> VDD VSS / RSC_IHPSG13_CINVX2 +XINV<1> q_int<1> qn_int<1> VDD VSS / RSC_IHPSG13_CINVX2 +XINV<0> q_int<0> qn_int<0> VDD VSS / RSC_IHPSG13_CINVX2 +XDRV<7> qn_int<7> ADDR_N_O<7> VDD VSS / RSC_IHPSG13_CINVX8 +XDRV<6> qn_int<6> ADDR_N_O<6> VDD VSS / RSC_IHPSG13_CINVX8 +XDRV<5> qn_int<5> ADDR_N_O<5> VDD VSS / RSC_IHPSG13_CINVX8 +XDRV<4> qn_int<4> ADDR_N_O<4> VDD VSS / RSC_IHPSG13_CINVX8 +XDRV<3> qn_int<3> ADDR_N_O<3> VDD VSS / RSC_IHPSG13_CINVX8 +XDRV<2> qn_int<2> ADDR_N_O<2> VDD VSS / RSC_IHPSG13_CINVX8 +XDRV<1> qn_int<1> ADDR_N_O<1> VDD VSS / RSC_IHPSG13_CINVX8 +XDRV<0> qn_int<0> ADDR_N_O<0> VDD VSS / RSC_IHPSG13_CINVX8 +XDFF<7> BIST_EN_I BIST_ADDR_I<7> ACLK_N_I ADDR_I<7> q_int<7> net2<0> VDD ++ VSS / RSC_IHPSG13_DFNQMX2IX1 +XDFF<6> BIST_EN_I BIST_ADDR_I<6> ACLK_N_I ADDR_I<6> q_int<6> net2<1> VDD ++ VSS / RSC_IHPSG13_DFNQMX2IX1 +XDFF<5> BIST_EN_I BIST_ADDR_I<5> ACLK_N_I ADDR_I<5> q_int<5> net2<2> VDD ++ VSS / RSC_IHPSG13_DFNQMX2IX1 +XDFF<4> BIST_EN_I BIST_ADDR_I<4> ACLK_N_I ADDR_I<4> q_int<4> net2<3> VDD ++ VSS / RSC_IHPSG13_DFNQMX2IX1 +XDFF<3> BIST_EN_I BIST_ADDR_I<3> ACLK_N_I ADDR_I<3> q_int<3> net2<4> VDD ++ VSS / RSC_IHPSG13_DFNQMX2IX1 +XDFF<2> BIST_EN_I BIST_ADDR_I<2> ACLK_N_I ADDR_I<2> q_int<2> net2<5> VDD ++ VSS / RSC_IHPSG13_DFNQMX2IX1 +XDFF<1> BIST_EN_I BIST_ADDR_I<1> ACLK_N_I ADDR_I<1> q_int<1> net2<6> VDD ++ VSS / RSC_IHPSG13_DFNQMX2IX1 +XDFF<0> BIST_EN_I BIST_ADDR_I<0> ACLK_N_I ADDR_I<0> q_int<0> net2<7> VDD ++ VSS / RSC_IHPSG13_DFNQMX2IX1 +XI11<4> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI11<3> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI11<2> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI11<1> VDD VSS / RSC_IHPSG13_FILLCAP8 +.ENDS + +.SUBCKT RM_IHPSG13_256x16_c2_1P_ROWDEC9 ADDR_N_I<8> ADDR_N_I<7> ADDR_N_I<6> ADDR_N_I<5> ++ ADDR_N_I<4> ADDR_N_I<3> ADDR_N_I<2> ADDR_N_I<1> ADDR_N_I<0> CS_I ECLK_I ++ WL_O<511> WL_O<510> WL_O<509> WL_O<508> WL_O<507> WL_O<506> WL_O<505> ++ WL_O<504> WL_O<503> WL_O<502> WL_O<501> WL_O<500> WL_O<499> WL_O<498> ++ WL_O<497> WL_O<496> WL_O<495> WL_O<494> WL_O<493> WL_O<492> WL_O<491> ++ WL_O<490> WL_O<489> WL_O<488> WL_O<487> WL_O<486> WL_O<485> WL_O<484> ++ WL_O<483> WL_O<482> WL_O<481> WL_O<480> WL_O<479> WL_O<478> WL_O<477> ++ WL_O<476> WL_O<475> WL_O<474> WL_O<473> WL_O<472> WL_O<471> WL_O<470> ++ WL_O<469> WL_O<468> WL_O<467> WL_O<466> WL_O<465> WL_O<464> WL_O<463> ++ WL_O<462> WL_O<461> WL_O<460> WL_O<459> WL_O<458> WL_O<457> WL_O<456> ++ WL_O<455> WL_O<454> WL_O<453> WL_O<452> WL_O<451> WL_O<450> WL_O<449> ++ WL_O<448> WL_O<447> WL_O<446> WL_O<445> WL_O<444> WL_O<443> WL_O<442> ++ WL_O<441> WL_O<440> WL_O<439> WL_O<438> WL_O<437> WL_O<436> WL_O<435> ++ WL_O<434> WL_O<433> WL_O<432> WL_O<431> WL_O<430> WL_O<429> WL_O<428> ++ WL_O<427> WL_O<426> WL_O<425> WL_O<424> WL_O<423> WL_O<422> WL_O<421> ++ WL_O<420> WL_O<419> WL_O<418> WL_O<417> WL_O<416> WL_O<415> WL_O<414> ++ WL_O<413> WL_O<412> WL_O<411> WL_O<410> WL_O<409> WL_O<408> WL_O<407> ++ WL_O<406> WL_O<405> WL_O<404> WL_O<403> WL_O<402> WL_O<401> WL_O<400> ++ WL_O<399> WL_O<398> WL_O<397> WL_O<396> WL_O<395> WL_O<394> WL_O<393> ++ WL_O<392> WL_O<391> WL_O<390> WL_O<389> WL_O<388> WL_O<387> WL_O<386> ++ WL_O<385> WL_O<384> WL_O<383> WL_O<382> WL_O<381> WL_O<380> WL_O<379> ++ WL_O<378> WL_O<377> WL_O<376> WL_O<375> WL_O<374> WL_O<373> WL_O<372> ++ WL_O<371> WL_O<370> WL_O<369> WL_O<368> WL_O<367> WL_O<366> WL_O<365> ++ WL_O<364> WL_O<363> WL_O<362> WL_O<361> WL_O<360> WL_O<359> WL_O<358> ++ WL_O<357> WL_O<356> WL_O<355> WL_O<354> WL_O<353> WL_O<352> WL_O<351> ++ WL_O<350> WL_O<349> WL_O<348> WL_O<347> WL_O<346> WL_O<345> WL_O<344> ++ WL_O<343> WL_O<342> WL_O<341> WL_O<340> WL_O<339> WL_O<338> WL_O<337> ++ WL_O<336> WL_O<335> WL_O<334> WL_O<333> WL_O<332> WL_O<331> WL_O<330> ++ WL_O<329> WL_O<328> WL_O<327> WL_O<326> WL_O<325> WL_O<324> WL_O<323> ++ WL_O<322> WL_O<321> WL_O<320> WL_O<319> WL_O<318> WL_O<317> WL_O<316> ++ WL_O<315> WL_O<314> WL_O<313> WL_O<312> WL_O<311> WL_O<310> WL_O<309> ++ WL_O<308> WL_O<307> WL_O<306> WL_O<305> WL_O<304> WL_O<303> WL_O<302> ++ WL_O<301> WL_O<300> WL_O<299> WL_O<298> WL_O<297> WL_O<296> WL_O<295> ++ WL_O<294> WL_O<293> WL_O<292> WL_O<291> WL_O<290> WL_O<289> WL_O<288> ++ WL_O<287> WL_O<286> WL_O<285> WL_O<284> WL_O<283> WL_O<282> WL_O<281> ++ WL_O<280> WL_O<279> WL_O<278> WL_O<277> WL_O<276> WL_O<275> WL_O<274> ++ WL_O<273> WL_O<272> WL_O<271> WL_O<270> WL_O<269> WL_O<268> WL_O<267> ++ WL_O<266> WL_O<265> WL_O<264> WL_O<263> WL_O<262> WL_O<261> WL_O<260> ++ WL_O<259> WL_O<258> WL_O<257> WL_O<256> WL_O<255> WL_O<254> WL_O<253> ++ WL_O<252> WL_O<251> WL_O<250> WL_O<249> WL_O<248> WL_O<247> WL_O<246> ++ WL_O<245> WL_O<244> WL_O<243> WL_O<242> WL_O<241> WL_O<240> WL_O<239> ++ WL_O<238> WL_O<237> WL_O<236> WL_O<235> WL_O<234> WL_O<233> WL_O<232> ++ WL_O<231> WL_O<230> WL_O<229> WL_O<228> WL_O<227> WL_O<226> WL_O<225> ++ WL_O<224> WL_O<223> WL_O<222> WL_O<221> WL_O<220> WL_O<219> WL_O<218> ++ WL_O<217> WL_O<216> WL_O<215> WL_O<214> WL_O<213> WL_O<212> WL_O<211> ++ WL_O<210> WL_O<209> WL_O<208> WL_O<207> WL_O<206> WL_O<205> WL_O<204> ++ WL_O<203> WL_O<202> WL_O<201> WL_O<200> WL_O<199> WL_O<198> WL_O<197> ++ WL_O<196> WL_O<195> WL_O<194> WL_O<193> WL_O<192> WL_O<191> WL_O<190> ++ WL_O<189> WL_O<188> WL_O<187> WL_O<186> WL_O<185> WL_O<184> WL_O<183> ++ WL_O<182> WL_O<181> WL_O<180> WL_O<179> WL_O<178> WL_O<177> WL_O<176> ++ WL_O<175> WL_O<174> WL_O<173> WL_O<172> WL_O<171> WL_O<170> WL_O<169> ++ WL_O<168> WL_O<167> WL_O<166> WL_O<165> WL_O<164> WL_O<163> WL_O<162> ++ WL_O<161> WL_O<160> WL_O<159> WL_O<158> WL_O<157> WL_O<156> WL_O<155> ++ WL_O<154> WL_O<153> WL_O<152> WL_O<151> WL_O<150> WL_O<149> WL_O<148> ++ WL_O<147> WL_O<146> WL_O<145> WL_O<144> WL_O<143> WL_O<142> WL_O<141> ++ WL_O<140> WL_O<139> WL_O<138> WL_O<137> WL_O<136> WL_O<135> WL_O<134> ++ WL_O<133> WL_O<132> WL_O<131> WL_O<130> WL_O<129> WL_O<128> WL_O<127> ++ WL_O<126> WL_O<125> WL_O<124> WL_O<123> WL_O<122> WL_O<121> WL_O<120> ++ WL_O<119> WL_O<118> WL_O<117> WL_O<116> WL_O<115> WL_O<114> WL_O<113> ++ WL_O<112> WL_O<111> WL_O<110> WL_O<109> WL_O<108> WL_O<107> WL_O<106> ++ WL_O<105> WL_O<104> WL_O<103> WL_O<102> WL_O<101> WL_O<100> WL_O<99> ++ WL_O<98> WL_O<97> WL_O<96> WL_O<95> WL_O<94> WL_O<93> WL_O<92> WL_O<91> ++ WL_O<90> WL_O<89> WL_O<88> WL_O<87> WL_O<86> WL_O<85> WL_O<84> WL_O<83> ++ WL_O<82> WL_O<81> WL_O<80> WL_O<79> WL_O<78> WL_O<77> WL_O<76> WL_O<75> ++ WL_O<74> WL_O<73> WL_O<72> WL_O<71> WL_O<70> WL_O<69> WL_O<68> WL_O<67> ++ WL_O<66> WL_O<65> WL_O<64> WL_O<63> WL_O<62> WL_O<61> WL_O<60> WL_O<59> ++ WL_O<58> WL_O<57> WL_O<56> WL_O<55> WL_O<54> WL_O<53> WL_O<52> WL_O<51> ++ WL_O<50> WL_O<49> WL_O<48> WL_O<47> WL_O<46> WL_O<45> WL_O<44> WL_O<43> ++ WL_O<42> WL_O<41> WL_O<40> WL_O<39> WL_O<38> WL_O<37> WL_O<36> WL_O<35> ++ WL_O<34> WL_O<33> WL_O<32> WL_O<31> WL_O<30> WL_O<29> WL_O<28> WL_O<27> ++ WL_O<26> WL_O<25> WL_O<24> WL_O<23> WL_O<22> WL_O<21> WL_O<20> WL_O<19> ++ WL_O<18> WL_O<17> WL_O<16> WL_O<15> WL_O<14> WL_O<13> WL_O<12> WL_O<11> ++ WL_O<10> WL_O<9> WL_O<8> WL_O<7> WL_O<6> WL_O<5> WL_O<4> WL_O<3> WL_O<2> ++ WL_O<1> WL_O<0> VDD VSS +XL2<172> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<171> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<170> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<169> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<168> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<167> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<166> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<165> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<164> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<163> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<162> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<161> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<160> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<159> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<158> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<157> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<156> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<155> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<154> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<153> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<152> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<151> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<150> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<149> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<148> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<147> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<146> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<145> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<144> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<143> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<142> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<141> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<140> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<139> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<138> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<137> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<136> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<135> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<134> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<133> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<132> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<131> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<130> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<129> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<128> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<127> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<126> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<125> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<124> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<123> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<122> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<121> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<120> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<119> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<118> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<117> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<116> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<115> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<114> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<113> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<112> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<111> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<110> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<109> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<108> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<107> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<106> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<105> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<104> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<103> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<102> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<101> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<100> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<99> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<98> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<97> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<96> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<95> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<94> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<93> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<92> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<91> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<90> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<89> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<88> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<87> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<86> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<85> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<84> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<83> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<82> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<81> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<80> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<79> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<78> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<77> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<76> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<75> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<74> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<73> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<72> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<71> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<70> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<69> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<68> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<67> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<66> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<65> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<64> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<63> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<62> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<61> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<60> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<59> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<58> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<57> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<56> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<55> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<54> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<53> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<52> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<51> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<50> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<49> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<48> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<47> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<46> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<45> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<44> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<43> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<42> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<41> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<40> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<39> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<38> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<37> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<36> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<35> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<34> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<33> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<32> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<31> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<30> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<29> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<28> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<27> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<26> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<25> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<24> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<23> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<22> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<21> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<20> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<19> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<18> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<17> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<16> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<15> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<14> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<13> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<12> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<11> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<10> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<9> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<8> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<7> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<6> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<5> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<4> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<3> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<2> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<1> VDD VSS / RSC_IHPSG13_FILLCAP8 +XDEC11<9> ADDR_N_I<7> ADDR_N_I<6> CS04<1> CS02<7> VDD VSS / ++ RM_IHPSG13_256x16_c2_1P_DEC03 +XDEC11<8> ADDR_N_I<7> ADDR_N_I<6> CS04<0> CS02<3> VDD VSS / ++ RM_IHPSG13_256x16_c2_1P_DEC03 +XDEC11<7> ADDR_N_I<5> ADDR_N_I<4> CS02<7> CS00<31> VDD VSS / ++ RM_IHPSG13_256x16_c2_1P_DEC03 +XDEC11<6> ADDR_N_I<5> ADDR_N_I<4> CS02<6> CS00<27> VDD VSS / ++ RM_IHPSG13_256x16_c2_1P_DEC03 +XDEC11<5> ADDR_N_I<5> ADDR_N_I<4> CS02<5> CS00<23> VDD VSS / ++ RM_IHPSG13_256x16_c2_1P_DEC03 +XDEC11<4> ADDR_N_I<5> ADDR_N_I<4> CS02<4> CS00<19> VDD VSS / ++ RM_IHPSG13_256x16_c2_1P_DEC03 +XDEC11<3> ADDR_N_I<5> ADDR_N_I<4> CS02<3> CS00<15> VDD VSS / ++ RM_IHPSG13_256x16_c2_1P_DEC03 +XDEC11<2> ADDR_N_I<5> ADDR_N_I<4> CS02<2> CS00<11> VDD VSS / ++ RM_IHPSG13_256x16_c2_1P_DEC03 +XDEC11<1> ADDR_N_I<5> ADDR_N_I<4> CS02<1> CS00<7> VDD VSS / ++ RM_IHPSG13_256x16_c2_1P_DEC03 +XDEC11<0> ADDR_N_I<5> ADDR_N_I<4> CS02<0> CS00<3> VDD VSS / ++ RM_IHPSG13_256x16_c2_1P_DEC03 +XDEC00<10> ADDR_N_I<9> ADDR_N_I<8> CS_I CS04<0> VDD VSS / ++ RM_IHPSG13_256x16_c2_1P_DEC00 +XDEC00<9> ADDR_N_I<7> ADDR_N_I<6> CS04<1> CS02<4> VDD VSS / ++ RM_IHPSG13_256x16_c2_1P_DEC00 +XDEC00<8> ADDR_N_I<7> ADDR_N_I<6> CS04<0> CS02<0> VDD VSS / ++ RM_IHPSG13_256x16_c2_1P_DEC00 +XDEC00<7> ADDR_N_I<5> ADDR_N_I<4> CS02<7> CS00<28> VDD VSS / ++ RM_IHPSG13_256x16_c2_1P_DEC00 +XDEC00<6> ADDR_N_I<5> ADDR_N_I<4> CS02<6> CS00<24> VDD VSS / ++ RM_IHPSG13_256x16_c2_1P_DEC00 +XDEC00<5> ADDR_N_I<5> ADDR_N_I<4> CS02<5> CS00<20> VDD VSS / ++ RM_IHPSG13_256x16_c2_1P_DEC00 +XDEC00<4> ADDR_N_I<5> ADDR_N_I<4> CS02<4> CS00<16> VDD VSS / ++ RM_IHPSG13_256x16_c2_1P_DEC00 +XDEC00<3> ADDR_N_I<5> ADDR_N_I<4> CS02<3> CS00<12> VDD VSS / ++ RM_IHPSG13_256x16_c2_1P_DEC00 +XDEC00<2> ADDR_N_I<5> ADDR_N_I<4> CS02<2> CS00<8> VDD VSS / ++ RM_IHPSG13_256x16_c2_1P_DEC00 +XDEC00<1> ADDR_N_I<5> ADDR_N_I<4> CS02<1> CS00<4> VDD VSS / ++ RM_IHPSG13_256x16_c2_1P_DEC00 +XDEC00<0> ADDR_N_I<5> ADDR_N_I<4> CS02<0> CS00<0> VDD VSS / ++ RM_IHPSG13_256x16_c2_1P_DEC00 +XSEL<31> ADDR_N_I<3> ADDR_N_I<2> ADDR_N_I<1> ADDR_N_I<0> CS00<31> ECLK_H<31> ++ ECLK_H<32> ECLK_B<31> ECLK_B<32> WL_O<511> WL_O<510> WL_O<509> WL_O<508> ++ WL_O<507> WL_O<506> WL_O<505> WL_O<504> WL_O<503> WL_O<502> WL_O<501> ++ WL_O<500> WL_O<499> WL_O<498> WL_O<497> WL_O<496> VDD VSS / ++ RM_IHPSG13_256x16_c2_1P_DEC04 +XSEL<30> ADDR_N_I<3> ADDR_N_I<2> ADDR_N_I<1> ADDR_N_I<0> CS00<30> ECLK_H<30> ++ ECLK_H<31> ECLK_B<30> ECLK_B<31> WL_O<495> WL_O<494> WL_O<493> WL_O<492> ++ WL_O<491> WL_O<490> WL_O<489> WL_O<488> WL_O<487> WL_O<486> WL_O<485> ++ WL_O<484> WL_O<483> WL_O<482> WL_O<481> WL_O<480> VDD VSS / ++ RM_IHPSG13_256x16_c2_1P_DEC04 +XSEL<29> ADDR_N_I<3> ADDR_N_I<2> ADDR_N_I<1> ADDR_N_I<0> CS00<29> ECLK_H<29> ++ ECLK_H<30> ECLK_B<29> ECLK_B<30> WL_O<479> WL_O<478> WL_O<477> WL_O<476> ++ WL_O<475> WL_O<474> WL_O<473> WL_O<472> WL_O<471> WL_O<470> WL_O<469> ++ WL_O<468> WL_O<467> WL_O<466> WL_O<465> WL_O<464> VDD VSS / ++ RM_IHPSG13_256x16_c2_1P_DEC04 +XSEL<28> ADDR_N_I<3> ADDR_N_I<2> ADDR_N_I<1> ADDR_N_I<0> CS00<28> ECLK_H<28> ++ ECLK_H<29> ECLK_B<28> ECLK_B<29> WL_O<463> WL_O<462> WL_O<461> WL_O<460> ++ WL_O<459> WL_O<458> WL_O<457> WL_O<456> WL_O<455> WL_O<454> WL_O<453> ++ WL_O<452> WL_O<451> WL_O<450> WL_O<449> WL_O<448> VDD VSS / ++ RM_IHPSG13_256x16_c2_1P_DEC04 +XSEL<27> ADDR_N_I<3> ADDR_N_I<2> ADDR_N_I<1> ADDR_N_I<0> CS00<27> ECLK_H<27> ++ ECLK_H<28> ECLK_B<27> ECLK_B<28> WL_O<447> WL_O<446> WL_O<445> WL_O<444> ++ WL_O<443> WL_O<442> WL_O<441> WL_O<440> WL_O<439> WL_O<438> WL_O<437> ++ WL_O<436> WL_O<435> WL_O<434> WL_O<433> WL_O<432> VDD VSS / ++ RM_IHPSG13_256x16_c2_1P_DEC04 +XSEL<26> ADDR_N_I<3> ADDR_N_I<2> ADDR_N_I<1> ADDR_N_I<0> CS00<26> ECLK_H<26> ++ ECLK_H<27> ECLK_B<26> ECLK_B<27> WL_O<431> WL_O<430> WL_O<429> WL_O<428> ++ WL_O<427> WL_O<426> WL_O<425> WL_O<424> WL_O<423> WL_O<422> WL_O<421> ++ WL_O<420> WL_O<419> WL_O<418> WL_O<417> WL_O<416> VDD VSS / ++ RM_IHPSG13_256x16_c2_1P_DEC04 +XSEL<25> ADDR_N_I<3> ADDR_N_I<2> ADDR_N_I<1> ADDR_N_I<0> CS00<25> ECLK_H<25> ++ ECLK_H<26> ECLK_B<25> ECLK_B<26> WL_O<415> WL_O<414> WL_O<413> WL_O<412> ++ WL_O<411> WL_O<410> WL_O<409> WL_O<408> WL_O<407> WL_O<406> WL_O<405> ++ WL_O<404> WL_O<403> WL_O<402> WL_O<401> WL_O<400> VDD VSS / ++ RM_IHPSG13_256x16_c2_1P_DEC04 +XSEL<24> ADDR_N_I<3> ADDR_N_I<2> ADDR_N_I<1> ADDR_N_I<0> CS00<24> ECLK_H<24> ++ ECLK_H<25> ECLK_B<24> ECLK_B<25> WL_O<399> WL_O<398> WL_O<397> WL_O<396> ++ WL_O<395> WL_O<394> WL_O<393> WL_O<392> WL_O<391> WL_O<390> WL_O<389> ++ WL_O<388> WL_O<387> WL_O<386> WL_O<385> WL_O<384> VDD VSS / ++ RM_IHPSG13_256x16_c2_1P_DEC04 +XSEL<23> ADDR_N_I<3> ADDR_N_I<2> ADDR_N_I<1> ADDR_N_I<0> CS00<23> ECLK_H<23> ++ ECLK_H<24> ECLK_B<23> ECLK_B<24> WL_O<383> WL_O<382> WL_O<381> WL_O<380> ++ WL_O<379> WL_O<378> WL_O<377> WL_O<376> WL_O<375> WL_O<374> WL_O<373> ++ WL_O<372> WL_O<371> WL_O<370> WL_O<369> WL_O<368> VDD VSS / ++ RM_IHPSG13_256x16_c2_1P_DEC04 +XSEL<22> ADDR_N_I<3> ADDR_N_I<2> ADDR_N_I<1> ADDR_N_I<0> CS00<22> ECLK_H<22> ++ ECLK_H<23> ECLK_B<22> ECLK_B<23> WL_O<367> WL_O<366> WL_O<365> WL_O<364> ++ WL_O<363> WL_O<362> WL_O<361> WL_O<360> WL_O<359> WL_O<358> WL_O<357> ++ WL_O<356> WL_O<355> WL_O<354> WL_O<353> WL_O<352> VDD VSS / ++ RM_IHPSG13_256x16_c2_1P_DEC04 +XSEL<21> ADDR_N_I<3> ADDR_N_I<2> ADDR_N_I<1> ADDR_N_I<0> CS00<21> ECLK_H<21> ++ ECLK_H<22> ECLK_B<21> ECLK_B<22> WL_O<351> WL_O<350> WL_O<349> WL_O<348> ++ WL_O<347> WL_O<346> WL_O<345> WL_O<344> WL_O<343> WL_O<342> WL_O<341> ++ WL_O<340> WL_O<339> WL_O<338> WL_O<337> WL_O<336> VDD VSS / ++ RM_IHPSG13_256x16_c2_1P_DEC04 +XSEL<20> ADDR_N_I<3> ADDR_N_I<2> ADDR_N_I<1> ADDR_N_I<0> CS00<20> ECLK_H<20> ++ ECLK_H<21> ECLK_B<20> ECLK_B<21> WL_O<335> WL_O<334> WL_O<333> WL_O<332> ++ WL_O<331> WL_O<330> WL_O<329> WL_O<328> WL_O<327> WL_O<326> WL_O<325> ++ WL_O<324> WL_O<323> WL_O<322> WL_O<321> WL_O<320> VDD VSS / ++ RM_IHPSG13_256x16_c2_1P_DEC04 +XSEL<19> ADDR_N_I<3> ADDR_N_I<2> ADDR_N_I<1> ADDR_N_I<0> CS00<19> ECLK_H<19> ++ ECLK_H<20> ECLK_B<19> ECLK_B<20> WL_O<319> WL_O<318> WL_O<317> WL_O<316> ++ WL_O<315> WL_O<314> WL_O<313> WL_O<312> WL_O<311> WL_O<310> WL_O<309> ++ WL_O<308> WL_O<307> WL_O<306> WL_O<305> WL_O<304> VDD VSS / ++ RM_IHPSG13_256x16_c2_1P_DEC04 +XSEL<18> ADDR_N_I<3> ADDR_N_I<2> ADDR_N_I<1> ADDR_N_I<0> CS00<18> ECLK_H<18> ++ ECLK_H<19> ECLK_B<18> ECLK_B<19> WL_O<303> WL_O<302> WL_O<301> WL_O<300> ++ WL_O<299> WL_O<298> WL_O<297> WL_O<296> WL_O<295> WL_O<294> WL_O<293> ++ WL_O<292> WL_O<291> WL_O<290> WL_O<289> WL_O<288> VDD VSS / ++ RM_IHPSG13_256x16_c2_1P_DEC04 +XSEL<17> ADDR_N_I<3> ADDR_N_I<2> ADDR_N_I<1> ADDR_N_I<0> CS00<17> ECLK_H<17> ++ ECLK_H<18> ECLK_B<17> ECLK_B<18> WL_O<287> WL_O<286> WL_O<285> WL_O<284> ++ WL_O<283> WL_O<282> WL_O<281> WL_O<280> WL_O<279> WL_O<278> WL_O<277> ++ WL_O<276> WL_O<275> WL_O<274> WL_O<273> WL_O<272> VDD VSS / ++ RM_IHPSG13_256x16_c2_1P_DEC04 +XSEL<16> ADDR_N_I<3> ADDR_N_I<2> ADDR_N_I<1> ADDR_N_I<0> CS00<16> ECLK_H<16> ++ ECLK_H<17> ECLK_B<16> ECLK_B<17> WL_O<271> WL_O<270> WL_O<269> WL_O<268> ++ WL_O<267> WL_O<266> WL_O<265> WL_O<264> WL_O<263> WL_O<262> WL_O<261> ++ WL_O<260> WL_O<259> WL_O<258> WL_O<257> WL_O<256> VDD VSS / ++ RM_IHPSG13_256x16_c2_1P_DEC04 +XSEL<15> ADDR_N_I<3> ADDR_N_I<2> ADDR_N_I<1> ADDR_N_I<0> CS00<15> ECLK_H<15> ++ ECLK_H<16> ECLK_B<15> ECLK_B<16> WL_O<255> WL_O<254> WL_O<253> WL_O<252> ++ WL_O<251> WL_O<250> WL_O<249> WL_O<248> WL_O<247> WL_O<246> WL_O<245> ++ WL_O<244> WL_O<243> WL_O<242> WL_O<241> WL_O<240> VDD VSS / ++ RM_IHPSG13_256x16_c2_1P_DEC04 +XSEL<14> ADDR_N_I<3> ADDR_N_I<2> ADDR_N_I<1> ADDR_N_I<0> CS00<14> ECLK_H<14> ++ ECLK_H<15> ECLK_B<14> ECLK_B<15> WL_O<239> WL_O<238> WL_O<237> WL_O<236> ++ WL_O<235> WL_O<234> WL_O<233> WL_O<232> WL_O<231> WL_O<230> WL_O<229> ++ WL_O<228> WL_O<227> WL_O<226> WL_O<225> WL_O<224> VDD VSS / ++ RM_IHPSG13_256x16_c2_1P_DEC04 +XSEL<13> ADDR_N_I<3> ADDR_N_I<2> ADDR_N_I<1> ADDR_N_I<0> CS00<13> ECLK_H<13> ++ ECLK_H<14> ECLK_B<13> ECLK_B<14> WL_O<223> WL_O<222> WL_O<221> WL_O<220> ++ WL_O<219> WL_O<218> WL_O<217> WL_O<216> WL_O<215> WL_O<214> WL_O<213> ++ WL_O<212> WL_O<211> WL_O<210> WL_O<209> WL_O<208> VDD VSS / ++ RM_IHPSG13_256x16_c2_1P_DEC04 +XSEL<12> ADDR_N_I<3> ADDR_N_I<2> ADDR_N_I<1> ADDR_N_I<0> CS00<12> ECLK_H<12> ++ ECLK_H<13> ECLK_B<12> ECLK_B<13> WL_O<207> WL_O<206> WL_O<205> WL_O<204> ++ WL_O<203> WL_O<202> WL_O<201> WL_O<200> WL_O<199> WL_O<198> WL_O<197> ++ WL_O<196> WL_O<195> WL_O<194> WL_O<193> WL_O<192> VDD VSS / ++ RM_IHPSG13_256x16_c2_1P_DEC04 +XSEL<11> ADDR_N_I<3> ADDR_N_I<2> ADDR_N_I<1> ADDR_N_I<0> CS00<11> ECLK_H<11> ++ ECLK_H<12> ECLK_B<11> ECLK_B<12> WL_O<191> WL_O<190> WL_O<189> WL_O<188> ++ WL_O<187> WL_O<186> WL_O<185> WL_O<184> WL_O<183> WL_O<182> WL_O<181> ++ WL_O<180> WL_O<179> WL_O<178> WL_O<177> WL_O<176> VDD VSS / ++ RM_IHPSG13_256x16_c2_1P_DEC04 +XSEL<10> ADDR_N_I<3> ADDR_N_I<2> ADDR_N_I<1> ADDR_N_I<0> CS00<10> ECLK_H<10> ++ ECLK_H<11> ECLK_B<10> ECLK_B<11> WL_O<175> WL_O<174> WL_O<173> WL_O<172> ++ WL_O<171> WL_O<170> WL_O<169> WL_O<168> WL_O<167> WL_O<166> WL_O<165> ++ WL_O<164> WL_O<163> WL_O<162> WL_O<161> WL_O<160> VDD VSS / ++ RM_IHPSG13_256x16_c2_1P_DEC04 +XSEL<9> ADDR_N_I<3> ADDR_N_I<2> ADDR_N_I<1> ADDR_N_I<0> CS00<9> ECLK_H<9> ++ ECLK_H<10> ECLK_B<9> ECLK_B<10> WL_O<159> WL_O<158> WL_O<157> WL_O<156> ++ WL_O<155> WL_O<154> WL_O<153> WL_O<152> WL_O<151> WL_O<150> WL_O<149> ++ WL_O<148> WL_O<147> WL_O<146> WL_O<145> WL_O<144> VDD VSS / ++ RM_IHPSG13_256x16_c2_1P_DEC04 +XSEL<8> ADDR_N_I<3> ADDR_N_I<2> ADDR_N_I<1> ADDR_N_I<0> CS00<8> ECLK_H<8> ++ ECLK_H<9> ECLK_B<8> ECLK_B<9> WL_O<143> WL_O<142> WL_O<141> WL_O<140> ++ WL_O<139> WL_O<138> WL_O<137> WL_O<136> WL_O<135> WL_O<134> WL_O<133> ++ WL_O<132> WL_O<131> WL_O<130> WL_O<129> WL_O<128> VDD VSS / ++ RM_IHPSG13_256x16_c2_1P_DEC04 +XSEL<7> ADDR_N_I<3> ADDR_N_I<2> ADDR_N_I<1> ADDR_N_I<0> CS00<7> ECLK_H<7> ++ ECLK_H<8> ECLK_B<7> ECLK_B<8> WL_O<127> WL_O<126> WL_O<125> WL_O<124> ++ WL_O<123> WL_O<122> WL_O<121> WL_O<120> WL_O<119> WL_O<118> WL_O<117> ++ WL_O<116> WL_O<115> WL_O<114> WL_O<113> WL_O<112> VDD VSS / ++ RM_IHPSG13_256x16_c2_1P_DEC04 +XSEL<6> ADDR_N_I<3> ADDR_N_I<2> ADDR_N_I<1> ADDR_N_I<0> CS00<6> ECLK_H<6> ++ ECLK_H<7> ECLK_B<6> ECLK_B<7> WL_O<111> WL_O<110> WL_O<109> WL_O<108> ++ WL_O<107> WL_O<106> WL_O<105> WL_O<104> WL_O<103> WL_O<102> WL_O<101> ++ WL_O<100> WL_O<99> WL_O<98> WL_O<97> WL_O<96> VDD VSS / ++ RM_IHPSG13_256x16_c2_1P_DEC04 +XSEL<5> ADDR_N_I<3> ADDR_N_I<2> ADDR_N_I<1> ADDR_N_I<0> CS00<5> ECLK_H<5> ++ ECLK_H<6> ECLK_B<5> ECLK_B<6> WL_O<95> WL_O<94> WL_O<93> WL_O<92> WL_O<91> ++ WL_O<90> WL_O<89> WL_O<88> WL_O<87> WL_O<86> WL_O<85> WL_O<84> WL_O<83> ++ WL_O<82> WL_O<81> WL_O<80> VDD VSS / RM_IHPSG13_256x16_c2_1P_DEC04 +XSEL<4> ADDR_N_I<3> ADDR_N_I<2> ADDR_N_I<1> ADDR_N_I<0> CS00<4> ECLK_H<4> ++ ECLK_H<5> ECLK_B<4> ECLK_B<5> WL_O<79> WL_O<78> WL_O<77> WL_O<76> WL_O<75> ++ WL_O<74> WL_O<73> WL_O<72> WL_O<71> WL_O<70> WL_O<69> WL_O<68> WL_O<67> ++ WL_O<66> WL_O<65> WL_O<64> VDD VSS / RM_IHPSG13_256x16_c2_1P_DEC04 +XSEL<3> ADDR_N_I<3> ADDR_N_I<2> ADDR_N_I<1> ADDR_N_I<0> CS00<3> ECLK_H<3> ++ ECLK_H<4> ECLK_B<3> ECLK_B<4> WL_O<63> WL_O<62> WL_O<61> WL_O<60> WL_O<59> ++ WL_O<58> WL_O<57> WL_O<56> WL_O<55> WL_O<54> WL_O<53> WL_O<52> WL_O<51> ++ WL_O<50> WL_O<49> WL_O<48> VDD VSS / RM_IHPSG13_256x16_c2_1P_DEC04 +XSEL<2> ADDR_N_I<3> ADDR_N_I<2> ADDR_N_I<1> ADDR_N_I<0> CS00<2> ECLK_H<2> ++ ECLK_H<3> ECLK_B<2> ECLK_B<3> WL_O<47> WL_O<46> WL_O<45> WL_O<44> WL_O<43> ++ WL_O<42> WL_O<41> WL_O<40> WL_O<39> WL_O<38> WL_O<37> WL_O<36> WL_O<35> ++ WL_O<34> WL_O<33> WL_O<32> VDD VSS / RM_IHPSG13_256x16_c2_1P_DEC04 +XSEL<1> ADDR_N_I<3> ADDR_N_I<2> ADDR_N_I<1> ADDR_N_I<0> CS00<1> ECLK_H<1> ++ ECLK_H<2> ECLK_B<1> ECLK_B<2> WL_O<31> WL_O<30> WL_O<29> WL_O<28> WL_O<27> ++ WL_O<26> WL_O<25> WL_O<24> WL_O<23> WL_O<22> WL_O<21> WL_O<20> WL_O<19> ++ WL_O<18> WL_O<17> WL_O<16> VDD VSS / RM_IHPSG13_256x16_c2_1P_DEC04 +XSEL<0> ADDR_N_I<3> ADDR_N_I<2> ADDR_N_I<1> ADDR_N_I<0> CS00<0> ECLK_I ++ ECLK_H<1> ECLK_B<0> ECLK_B<1> WL_O<15> WL_O<14> WL_O<13> WL_O<12> WL_O<11> ++ WL_O<10> WL_O<9> WL_O<8> WL_O<7> WL_O<6> WL_O<5> WL_O<4> WL_O<3> WL_O<2> ++ WL_O<1> WL_O<0> VDD VSS / RM_IHPSG13_256x16_c2_1P_DEC04 +XDEC01<10> ADDR_N_I<9> ADDR_N_I<8> CS_I CS04<1> VDD VSS / ++ RM_IHPSG13_256x16_c2_1P_DEC01 +XDEC01<9> ADDR_N_I<7> ADDR_N_I<6> CS04<1> CS02<5> VDD VSS / ++ RM_IHPSG13_256x16_c2_1P_DEC01 +XDEC01<8> ADDR_N_I<7> ADDR_N_I<6> CS04<0> CS02<1> VDD VSS / ++ RM_IHPSG13_256x16_c2_1P_DEC01 +XDEC01<7> ADDR_N_I<5> ADDR_N_I<4> CS02<7> CS00<29> VDD VSS / ++ RM_IHPSG13_256x16_c2_1P_DEC01 +XDEC01<6> ADDR_N_I<5> ADDR_N_I<4> CS02<6> CS00<25> VDD VSS / ++ RM_IHPSG13_256x16_c2_1P_DEC01 +XDEC01<5> ADDR_N_I<5> ADDR_N_I<4> CS02<5> CS00<21> VDD VSS / ++ RM_IHPSG13_256x16_c2_1P_DEC01 +XDEC01<4> ADDR_N_I<5> ADDR_N_I<4> CS02<4> CS00<17> VDD VSS / ++ RM_IHPSG13_256x16_c2_1P_DEC01 +XDEC01<3> ADDR_N_I<5> ADDR_N_I<4> CS02<3> CS00<13> VDD VSS / ++ RM_IHPSG13_256x16_c2_1P_DEC01 +XDEC01<2> ADDR_N_I<5> ADDR_N_I<4> CS02<2> CS00<9> VDD VSS / ++ RM_IHPSG13_256x16_c2_1P_DEC01 +XDEC01<1> ADDR_N_I<5> ADDR_N_I<4> CS02<1> CS00<5> VDD VSS / ++ RM_IHPSG13_256x16_c2_1P_DEC01 +XDEC01<0> ADDR_N_I<5> ADDR_N_I<4> CS02<0> CS00<1> VDD VSS / ++ RM_IHPSG13_256x16_c2_1P_DEC01 +XDEC10<9> ADDR_N_I<7> ADDR_N_I<6> CS04<1> CS02<6> VDD VSS / ++ RM_IHPSG13_256x16_c2_1P_DEC02 +XDEC10<8> ADDR_N_I<7> ADDR_N_I<6> CS04<0> CS02<2> VDD VSS / ++ RM_IHPSG13_256x16_c2_1P_DEC02 +XDEC10<7> ADDR_N_I<5> ADDR_N_I<4> CS02<7> CS00<30> VDD VSS / ++ RM_IHPSG13_256x16_c2_1P_DEC02 +XDEC10<6> ADDR_N_I<5> ADDR_N_I<4> CS02<6> CS00<26> VDD VSS / ++ RM_IHPSG13_256x16_c2_1P_DEC02 +XDEC10<5> ADDR_N_I<5> ADDR_N_I<4> CS02<5> CS00<22> VDD VSS / ++ RM_IHPSG13_256x16_c2_1P_DEC02 +XDEC10<4> ADDR_N_I<5> ADDR_N_I<4> CS02<4> CS00<18> VDD VSS / ++ RM_IHPSG13_256x16_c2_1P_DEC02 +XDEC10<3> ADDR_N_I<5> ADDR_N_I<4> CS02<3> CS00<14> VDD VSS / ++ RM_IHPSG13_256x16_c2_1P_DEC02 +XDEC10<2> ADDR_N_I<5> ADDR_N_I<4> CS02<2> CS00<10> VDD VSS / ++ RM_IHPSG13_256x16_c2_1P_DEC02 +XDEC10<1> ADDR_N_I<5> ADDR_N_I<4> CS02<1> CS00<6> VDD VSS / ++ RM_IHPSG13_256x16_c2_1P_DEC02 +XDEC10<0> ADDR_N_I<5> ADDR_N_I<4> CS02<0> CS00<2> VDD VSS / ++ RM_IHPSG13_256x16_c2_1P_DEC02 +XI0 ADDR_N_I<9> VDD VSS / RSC_IHPSG13_TIEL +.ENDS +.SUBCKT RM_IHPSG13_256x16_c2_1P_ROWREG9 ACLK_N_I ADDR_I<8> ADDR_I<7> ADDR_I<6> ADDR_I<5> ++ ADDR_I<4> ADDR_I<3> ADDR_I<2> ADDR_I<1> ADDR_I<0> ADDR_N_O<8> ADDR_N_O<7> ++ ADDR_N_O<6> ADDR_N_O<5> ADDR_N_O<4> ADDR_N_O<3> ADDR_N_O<2> ADDR_N_O<1> ++ ADDR_N_O<0> BIST_ADDR_I<8> BIST_ADDR_I<7> BIST_ADDR_I<6> BIST_ADDR_I<5> ++ BIST_ADDR_I<4> BIST_ADDR_I<3> BIST_ADDR_I<2> BIST_ADDR_I<1> BIST_ADDR_I<0> ++ BIST_EN_I VDD VSS +XINV<8> q_int<8> qn_int<8> VDD VSS / RSC_IHPSG13_CINVX2 +XINV<7> q_int<7> qn_int<7> VDD VSS / RSC_IHPSG13_CINVX2 +XINV<6> q_int<6> qn_int<6> VDD VSS / RSC_IHPSG13_CINVX2 +XINV<5> q_int<5> qn_int<5> VDD VSS / RSC_IHPSG13_CINVX2 +XINV<4> q_int<4> qn_int<4> VDD VSS / RSC_IHPSG13_CINVX2 +XINV<3> q_int<3> qn_int<3> VDD VSS / RSC_IHPSG13_CINVX2 +XINV<2> q_int<2> qn_int<2> VDD VSS / RSC_IHPSG13_CINVX2 +XINV<1> q_int<1> qn_int<1> VDD VSS / RSC_IHPSG13_CINVX2 +XINV<0> q_int<0> qn_int<0> VDD VSS / RSC_IHPSG13_CINVX2 +XDRV<8> qn_int<8> ADDR_N_O<8> VDD VSS / RSC_IHPSG13_CINVX8 +XDRV<7> qn_int<7> ADDR_N_O<7> VDD VSS / RSC_IHPSG13_CINVX8 +XDRV<6> qn_int<6> ADDR_N_O<6> VDD VSS / RSC_IHPSG13_CINVX8 +XDRV<5> qn_int<5> ADDR_N_O<5> VDD VSS / RSC_IHPSG13_CINVX8 +XDRV<4> qn_int<4> ADDR_N_O<4> VDD VSS / RSC_IHPSG13_CINVX8 +XDRV<3> qn_int<3> ADDR_N_O<3> VDD VSS / RSC_IHPSG13_CINVX8 +XDRV<2> qn_int<2> ADDR_N_O<2> VDD VSS / RSC_IHPSG13_CINVX8 +XDRV<1> qn_int<1> ADDR_N_O<1> VDD VSS / RSC_IHPSG13_CINVX8 +XDRV<0> qn_int<0> ADDR_N_O<0> VDD VSS / RSC_IHPSG13_CINVX8 +XDFF<8> BIST_EN_I BIST_ADDR_I<8> ACLK_N_I ADDR_I<8> q_int<8> net04<0> VDD ++ VSS / RSC_IHPSG13_DFNQMX2IX1 +XDFF<7> BIST_EN_I BIST_ADDR_I<7> ACLK_N_I ADDR_I<7> q_int<7> net04<1> VDD ++ VSS / RSC_IHPSG13_DFNQMX2IX1 +XDFF<6> BIST_EN_I BIST_ADDR_I<6> ACLK_N_I ADDR_I<6> q_int<6> net04<2> VDD ++ VSS / RSC_IHPSG13_DFNQMX2IX1 +XDFF<5> BIST_EN_I BIST_ADDR_I<5> ACLK_N_I ADDR_I<5> q_int<5> net04<3> VDD ++ VSS / RSC_IHPSG13_DFNQMX2IX1 +XDFF<4> BIST_EN_I BIST_ADDR_I<4> ACLK_N_I ADDR_I<4> q_int<4> net04<4> VDD ++ VSS / RSC_IHPSG13_DFNQMX2IX1 +XDFF<3> BIST_EN_I BIST_ADDR_I<3> ACLK_N_I ADDR_I<3> q_int<3> net04<5> VDD ++ VSS / RSC_IHPSG13_DFNQMX2IX1 +XDFF<2> BIST_EN_I BIST_ADDR_I<2> ACLK_N_I ADDR_I<2> q_int<2> net04<6> VDD ++ VSS / RSC_IHPSG13_DFNQMX2IX1 +XDFF<1> BIST_EN_I BIST_ADDR_I<1> ACLK_N_I ADDR_I<1> q_int<1> net04<7> VDD ++ VSS / RSC_IHPSG13_DFNQMX2IX1 +XDFF<0> BIST_EN_I BIST_ADDR_I<0> ACLK_N_I ADDR_I<0> q_int<0> net04<8> VDD ++ VSS / RSC_IHPSG13_DFNQMX2IX1 +.ENDS + +.SUBCKT RM_IHPSG13_256x16_c2_1P_ROWDEC7 ADDR_N_I<6> ADDR_N_I<5> ADDR_N_I<4> ADDR_N_I<3> ++ ADDR_N_I<2> ADDR_N_I<1> ADDR_N_I<0> CS_I ECLK_I WL_O<127> WL_O<126> ++ WL_O<125> WL_O<124> WL_O<123> WL_O<122> WL_O<121> WL_O<120> WL_O<119> ++ WL_O<118> WL_O<117> WL_O<116> WL_O<115> WL_O<114> WL_O<113> WL_O<112> ++ WL_O<111> WL_O<110> WL_O<109> WL_O<108> WL_O<107> WL_O<106> WL_O<105> ++ WL_O<104> WL_O<103> WL_O<102> WL_O<101> WL_O<100> WL_O<99> WL_O<98> WL_O<97> ++ WL_O<96> WL_O<95> WL_O<94> WL_O<93> WL_O<92> WL_O<91> WL_O<90> WL_O<89> ++ WL_O<88> WL_O<87> WL_O<86> WL_O<85> WL_O<84> WL_O<83> WL_O<82> WL_O<81> ++ WL_O<80> WL_O<79> WL_O<78> WL_O<77> WL_O<76> WL_O<75> WL_O<74> WL_O<73> ++ WL_O<72> WL_O<71> WL_O<70> WL_O<69> WL_O<68> WL_O<67> WL_O<66> WL_O<65> ++ WL_O<64> WL_O<63> WL_O<62> WL_O<61> WL_O<60> WL_O<59> WL_O<58> WL_O<57> ++ WL_O<56> WL_O<55> WL_O<54> WL_O<53> WL_O<52> WL_O<51> WL_O<50> WL_O<49> ++ WL_O<48> WL_O<47> WL_O<46> WL_O<45> WL_O<44> WL_O<43> WL_O<42> WL_O<41> ++ WL_O<40> WL_O<39> WL_O<38> WL_O<37> WL_O<36> WL_O<35> WL_O<34> WL_O<33> ++ WL_O<32> WL_O<31> WL_O<30> WL_O<29> WL_O<28> WL_O<27> WL_O<26> WL_O<25> ++ WL_O<24> WL_O<23> WL_O<22> WL_O<21> WL_O<20> WL_O<19> WL_O<18> WL_O<17> ++ WL_O<16> WL_O<15> WL_O<14> WL_O<13> WL_O<12> WL_O<11> WL_O<10> WL_O<9> ++ WL_O<8> WL_O<7> WL_O<6> WL_O<5> WL_O<4> WL_O<3> WL_O<2> WL_O<1> WL_O<0> ++ VDD VSS +XDEC11<1> ADDR_N_I<5> ADDR_N_I<4> CS04<1> CS00<7> VDD VSS / ++ RM_IHPSG13_256x16_c2_1P_DEC03 +XDEC11<0> ADDR_N_I<5> ADDR_N_I<4> CS04<0> CS00<3> VDD VSS / ++ RM_IHPSG13_256x16_c2_1P_DEC03 +XDEC10<1> ADDR_N_I<5> ADDR_N_I<4> CS04<1> CS00<6> VDD VSS / ++ RM_IHPSG13_256x16_c2_1P_DEC02 +XDEC10<0> ADDR_N_I<5> ADDR_N_I<4> CS04<0> CS00<2> VDD VSS / ++ RM_IHPSG13_256x16_c2_1P_DEC02 +XSEL<7> ADDR_N_I<3> ADDR_N_I<2> ADDR_N_I<1> ADDR_N_I<0> CS00<7> ECLK_H<7> ++ ECLK_H<8> ECLK_B<7> ECLK_B<8> WL_O<127> WL_O<126> WL_O<125> WL_O<124> ++ WL_O<123> WL_O<122> WL_O<121> WL_O<120> WL_O<119> WL_O<118> WL_O<117> ++ WL_O<116> WL_O<115> WL_O<114> WL_O<113> WL_O<112> VDD VSS / ++ RM_IHPSG13_256x16_c2_1P_DEC04 +XSEL<6> ADDR_N_I<3> ADDR_N_I<2> ADDR_N_I<1> ADDR_N_I<0> CS00<6> ECLK_H<6> ++ ECLK_H<7> ECLK_B<6> ECLK_B<7> WL_O<111> WL_O<110> WL_O<109> WL_O<108> ++ WL_O<107> WL_O<106> WL_O<105> WL_O<104> WL_O<103> WL_O<102> WL_O<101> ++ WL_O<100> WL_O<99> WL_O<98> WL_O<97> WL_O<96> VDD VSS / ++ RM_IHPSG13_256x16_c2_1P_DEC04 +XSEL<5> ADDR_N_I<3> ADDR_N_I<2> ADDR_N_I<1> ADDR_N_I<0> CS00<5> ECLK_H<5> ++ ECLK_H<6> ECLK_B<5> ECLK_B<6> WL_O<95> WL_O<94> WL_O<93> WL_O<92> WL_O<91> ++ WL_O<90> WL_O<89> WL_O<88> WL_O<87> WL_O<86> WL_O<85> WL_O<84> WL_O<83> ++ WL_O<82> WL_O<81> WL_O<80> VDD VSS / RM_IHPSG13_256x16_c2_1P_DEC04 +XSEL<4> ADDR_N_I<3> ADDR_N_I<2> ADDR_N_I<1> ADDR_N_I<0> CS00<4> ECLK_H<4> ++ ECLK_H<5> ECLK_B<4> ECLK_B<5> WL_O<79> WL_O<78> WL_O<77> WL_O<76> WL_O<75> ++ WL_O<74> WL_O<73> WL_O<72> WL_O<71> WL_O<70> WL_O<69> WL_O<68> WL_O<67> ++ WL_O<66> WL_O<65> WL_O<64> VDD VSS / RM_IHPSG13_256x16_c2_1P_DEC04 +XSEL<3> ADDR_N_I<3> ADDR_N_I<2> ADDR_N_I<1> ADDR_N_I<0> CS00<3> ECLK_H<3> ++ ECLK_H<4> ECLK_B<3> ECLK_B<4> WL_O<63> WL_O<62> WL_O<61> WL_O<60> WL_O<59> ++ WL_O<58> WL_O<57> WL_O<56> WL_O<55> WL_O<54> WL_O<53> WL_O<52> WL_O<51> ++ WL_O<50> WL_O<49> WL_O<48> VDD VSS / RM_IHPSG13_256x16_c2_1P_DEC04 +XSEL<2> ADDR_N_I<3> ADDR_N_I<2> ADDR_N_I<1> ADDR_N_I<0> CS00<2> ECLK_H<2> ++ ECLK_H<3> ECLK_B<2> ECLK_B<3> WL_O<47> WL_O<46> WL_O<45> WL_O<44> WL_O<43> ++ WL_O<42> WL_O<41> WL_O<40> WL_O<39> WL_O<38> WL_O<37> WL_O<36> WL_O<35> ++ WL_O<34> WL_O<33> WL_O<32> VDD VSS / RM_IHPSG13_256x16_c2_1P_DEC04 +XSEL<1> ADDR_N_I<3> ADDR_N_I<2> ADDR_N_I<1> ADDR_N_I<0> CS00<1> ECLK_H<1> ++ ECLK_H<2> ECLK_B<1> ECLK_B<2> WL_O<31> WL_O<30> WL_O<29> WL_O<28> WL_O<27> ++ WL_O<26> WL_O<25> WL_O<24> WL_O<23> WL_O<22> WL_O<21> WL_O<20> WL_O<19> ++ WL_O<18> WL_O<17> WL_O<16> VDD VSS / RM_IHPSG13_256x16_c2_1P_DEC04 +XSEL<0> ADDR_N_I<3> ADDR_N_I<2> ADDR_N_I<1> ADDR_N_I<0> CS00<0> ECLK_I ++ ECLK_H<1> ECLK_B<0> ECLK_B<1> WL_O<15> WL_O<14> WL_O<13> WL_O<12> WL_O<11> ++ WL_O<10> WL_O<9> WL_O<8> WL_O<7> WL_O<6> WL_O<5> WL_O<4> WL_O<3> WL_O<2> ++ WL_O<1> WL_O<0> VDD VSS / RM_IHPSG13_256x16_c2_1P_DEC04 +XDEC00<2> ADDR_N_I<7> ADDR_N_I<6> CS_I CS04<0> VDD VSS / ++ RM_IHPSG13_256x16_c2_1P_DEC00 +XDEC00<1> ADDR_N_I<5> ADDR_N_I<4> CS04<1> CS00<4> VDD VSS / ++ RM_IHPSG13_256x16_c2_1P_DEC00 +XDEC00<0> ADDR_N_I<5> ADDR_N_I<4> CS04<0> CS00<0> VDD VSS / ++ RM_IHPSG13_256x16_c2_1P_DEC00 +XDEC01<2> ADDR_N_I<7> ADDR_N_I<6> CS_I CS04<1> VDD VSS / ++ RM_IHPSG13_256x16_c2_1P_DEC01 +XDEC01<1> ADDR_N_I<5> ADDR_N_I<4> CS04<1> CS00<5> VDD VSS / ++ RM_IHPSG13_256x16_c2_1P_DEC01 +XDEC01<0> ADDR_N_I<5> ADDR_N_I<4> CS04<0> CS00<1> VDD VSS / ++ RM_IHPSG13_256x16_c2_1P_DEC01 +XL2<44> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<43> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<42> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<41> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<40> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<39> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<38> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<37> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<36> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<35> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<34> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<33> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<32> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<31> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<30> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<29> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<28> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<27> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<26> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<25> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<24> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<23> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<22> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<21> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<20> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<19> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<18> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<17> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<16> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<15> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<14> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<13> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<12> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<11> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<10> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<9> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<8> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<7> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<6> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<5> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<4> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<3> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<2> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<1> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI0 ADDR_N_I<7> VDD VSS / RSC_IHPSG13_TIEL +.ENDS +.SUBCKT RM_IHPSG13_256x16_c2_1P_ROWREG7 ACLK_N_I ADDR_I<6> ADDR_I<5> ADDR_I<4> ADDR_I<3> ++ ADDR_I<2> ADDR_I<1> ADDR_I<0> ADDR_N_O<6> ADDR_N_O<5> ADDR_N_O<4> ++ ADDR_N_O<3> ADDR_N_O<2> ADDR_N_O<1> ADDR_N_O<0> BIST_ADDR_I<6> ++ BIST_ADDR_I<5> BIST_ADDR_I<4> BIST_ADDR_I<3> BIST_ADDR_I<2> BIST_ADDR_I<1> ++ BIST_ADDR_I<0> BIST_EN_I VDD VSS +XINV<6> q_int<6> qn_int<6> VDD VSS / RSC_IHPSG13_CINVX2 +XINV<5> q_int<5> qn_int<5> VDD VSS / RSC_IHPSG13_CINVX2 +XINV<4> q_int<4> qn_int<4> VDD VSS / RSC_IHPSG13_CINVX2 +XINV<3> q_int<3> qn_int<3> VDD VSS / RSC_IHPSG13_CINVX2 +XINV<2> q_int<2> qn_int<2> VDD VSS / RSC_IHPSG13_CINVX2 +XINV<1> q_int<1> qn_int<1> VDD VSS / RSC_IHPSG13_CINVX2 +XINV<0> q_int<0> qn_int<0> VDD VSS / RSC_IHPSG13_CINVX2 +XDRV<6> qn_int<6> ADDR_N_O<6> VDD VSS / RSC_IHPSG13_CINVX8 +XDRV<5> qn_int<5> ADDR_N_O<5> VDD VSS / RSC_IHPSG13_CINVX8 +XDRV<4> qn_int<4> ADDR_N_O<4> VDD VSS / RSC_IHPSG13_CINVX8 +XDRV<3> qn_int<3> ADDR_N_O<3> VDD VSS / RSC_IHPSG13_CINVX8 +XDRV<2> qn_int<2> ADDR_N_O<2> VDD VSS / RSC_IHPSG13_CINVX8 +XDRV<1> qn_int<1> ADDR_N_O<1> VDD VSS / RSC_IHPSG13_CINVX8 +XDRV<0> qn_int<0> ADDR_N_O<0> VDD VSS / RSC_IHPSG13_CINVX8 +XDFF<6> BIST_EN_I BIST_ADDR_I<6> ACLK_N_I ADDR_I<6> q_int<6> net2<0> VDD ++ VSS / RSC_IHPSG13_DFNQMX2IX1 +XDFF<5> BIST_EN_I BIST_ADDR_I<5> ACLK_N_I ADDR_I<5> q_int<5> net2<1> VDD ++ VSS / RSC_IHPSG13_DFNQMX2IX1 +XDFF<4> BIST_EN_I BIST_ADDR_I<4> ACLK_N_I ADDR_I<4> q_int<4> net2<2> VDD ++ VSS / RSC_IHPSG13_DFNQMX2IX1 +XDFF<3> BIST_EN_I BIST_ADDR_I<3> ACLK_N_I ADDR_I<3> q_int<3> net2<3> VDD ++ VSS / RSC_IHPSG13_DFNQMX2IX1 +XDFF<2> BIST_EN_I BIST_ADDR_I<2> ACLK_N_I ADDR_I<2> q_int<2> net2<4> VDD ++ VSS / RSC_IHPSG13_DFNQMX2IX1 +XDFF<1> BIST_EN_I BIST_ADDR_I<1> ACLK_N_I ADDR_I<1> q_int<1> net2<5> VDD ++ VSS / RSC_IHPSG13_DFNQMX2IX1 +XDFF<0> BIST_EN_I BIST_ADDR_I<0> ACLK_N_I ADDR_I<0> q_int<0> net2<6> VDD ++ VSS / RSC_IHPSG13_DFNQMX2IX1 +XI11<8> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI11<7> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI11<6> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI11<5> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI11<4> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI11<3> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI11<2> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI11<1> VDD VSS / RSC_IHPSG13_FILLCAP8 +.ENDS + +.SUBCKT RM_IHPSG13_256x16_c2_1P_COLDRV13X8 ADDR_COL_I<1> ADDR_COL_I<0> ADDR_COL_O<1> ++ ADDR_COL_O<0> ADDR_DEC_I<7> ADDR_DEC_I<6> ADDR_DEC_I<5> ADDR_DEC_I<4> ++ ADDR_DEC_I<3> ADDR_DEC_I<2> ADDR_DEC_I<1> ADDR_DEC_I<0> ADDR_DEC_O<7> ++ ADDR_DEC_O<6> ADDR_DEC_O<5> ADDR_DEC_O<4> ADDR_DEC_O<3> ADDR_DEC_O<2> ++ ADDR_DEC_O<1> ADDR_DEC_O<0> DCLK_I DCLK_O RCLK_I RCLK_O WCLK_I WCLK_O ++ VDD VSS +XI0<1> VDD VSS / RSC_IHPSG13_FILLCAP4 +XI0<0> VDD VSS / RSC_IHPSG13_FILLCAP4 +XADDR_COL_DRV<1> ADDR_COL_I<1> ADDR_COL_O<1> VDD VSS / ++ RSC_IHPSG13_CBUFX8 +XADDR_COL_DRV<0> ADDR_COL_I<0> ADDR_COL_O<0> VDD VSS / ++ RSC_IHPSG13_CBUFX8 +XADDR_DEC_DRV<7> ADDR_DEC_I<7> ADDR_DEC_O<7> VDD VSS / ++ RSC_IHPSG13_CBUFX8 +XADDR_DEC_DRV<6> ADDR_DEC_I<6> ADDR_DEC_O<6> VDD VSS / ++ RSC_IHPSG13_CBUFX8 +XADDR_DEC_DRV<5> ADDR_DEC_I<5> ADDR_DEC_O<5> VDD VSS / ++ RSC_IHPSG13_CBUFX8 +XADDR_DEC_DRV<4> ADDR_DEC_I<4> ADDR_DEC_O<4> VDD VSS / ++ RSC_IHPSG13_CBUFX8 +XADDR_DEC_DRV<3> ADDR_DEC_I<3> ADDR_DEC_O<3> VDD VSS / ++ RSC_IHPSG13_CBUFX8 +XADDR_DEC_DRV<2> ADDR_DEC_I<2> ADDR_DEC_O<2> VDD VSS / ++ RSC_IHPSG13_CBUFX8 +XADDR_DEC_DRV<1> ADDR_DEC_I<1> ADDR_DEC_O<1> VDD VSS / ++ RSC_IHPSG13_CBUFX8 +XADDR_DEC_DRV<0> ADDR_DEC_I<0> ADDR_DEC_O<0> VDD VSS / ++ RSC_IHPSG13_CBUFX8 +XDCLK_DRV DCLK_I DCLK_O VDD VSS / RSC_IHPSG13_CBUFX8 +XRCLK_DRV RCLK_I RCLK_O VDD VSS / RSC_IHPSG13_CBUFX8 +XWCLK_DRV WCLK_I WCLK_O VDD VSS / RSC_IHPSG13_CBUFX8 +.ENDS +.SUBCKT RM_IHPSG13_256x16_c2_1P_WLDRV16X8 A<15> A<14> A<13> A<12> A<11> A<10> A<9> A<8> ++ A<7> A<6> A<5> A<4> A<3> A<2> A<1> A<0> Z<15> Z<14> Z<13> Z<12> Z<11> Z<10> ++ Z<9> Z<8> Z<7> Z<6> Z<5> Z<4> Z<3> Z<2> Z<1> Z<0> VDD VSS +XBUF<15> A<15> Z<15> VDD VSS / RSC_IHPSG13_WLDRVX8 +XBUF<14> A<14> Z<14> VDD VSS / RSC_IHPSG13_WLDRVX8 +XBUF<13> A<13> Z<13> VDD VSS / RSC_IHPSG13_WLDRVX8 +XBUF<12> A<12> Z<12> VDD VSS / RSC_IHPSG13_WLDRVX8 +XBUF<11> A<11> Z<11> VDD VSS / RSC_IHPSG13_WLDRVX8 +XBUF<10> A<10> Z<10> VDD VSS / RSC_IHPSG13_WLDRVX8 +XBUF<9> A<9> Z<9> VDD VSS / RSC_IHPSG13_WLDRVX8 +XBUF<8> A<8> Z<8> VDD VSS / RSC_IHPSG13_WLDRVX8 +XBUF<7> A<7> Z<7> VDD VSS / RSC_IHPSG13_WLDRVX8 +XBUF<6> A<6> Z<6> VDD VSS / RSC_IHPSG13_WLDRVX8 +XBUF<5> A<5> Z<5> VDD VSS / RSC_IHPSG13_WLDRVX8 +XBUF<4> A<4> Z<4> VDD VSS / RSC_IHPSG13_WLDRVX8 +XBUF<3> A<3> Z<3> VDD VSS / RSC_IHPSG13_WLDRVX8 +XBUF<2> A<2> Z<2> VDD VSS / RSC_IHPSG13_WLDRVX8 +XBUF<1> A<1> Z<1> VDD VSS / RSC_IHPSG13_WLDRVX8 +XBUF<0> A<0> Z<0> VDD VSS / RSC_IHPSG13_WLDRVX8 +.ENDS + + + +.SUBCKT RM_IHPSG13_256x16_c2_1P_ROWDEC6 ADDR_N_I<5> ADDR_N_I<4> ADDR_N_I<3> ADDR_N_I<2> ++ ADDR_N_I<1> ADDR_N_I<0> CS_I ECLK_I WL_O<63> WL_O<62> WL_O<61> WL_O<60> ++ WL_O<59> WL_O<58> WL_O<57> WL_O<56> WL_O<55> WL_O<54> WL_O<53> WL_O<52> ++ WL_O<51> WL_O<50> WL_O<49> WL_O<48> WL_O<47> WL_O<46> WL_O<45> WL_O<44> ++ WL_O<43> WL_O<42> WL_O<41> WL_O<40> WL_O<39> WL_O<38> WL_O<37> WL_O<36> ++ WL_O<35> WL_O<34> WL_O<33> WL_O<32> WL_O<31> WL_O<30> WL_O<29> WL_O<28> ++ WL_O<27> WL_O<26> WL_O<25> WL_O<24> WL_O<23> WL_O<22> WL_O<21> WL_O<20> ++ WL_O<19> WL_O<18> WL_O<17> WL_O<16> WL_O<15> WL_O<14> WL_O<13> WL_O<12> ++ WL_O<11> WL_O<10> WL_O<9> WL_O<8> WL_O<7> WL_O<6> WL_O<5> WL_O<4> WL_O<3> ++ WL_O<2> WL_O<1> WL_O<0> VDD VSS +XDEC11 ADDR_N_I<5> ADDR_N_I<4> CS_I CS00<3> VDD VSS / ++ RM_IHPSG13_256x16_c2_1P_DEC03 +XDEC00 ADDR_N_I<5> ADDR_N_I<4> CS_I CS00<0> VDD VSS / ++ RM_IHPSG13_256x16_c2_1P_DEC00 +XDEC01 ADDR_N_I<5> ADDR_N_I<4> CS_I CS00<1> VDD VSS / ++ RM_IHPSG13_256x16_c2_1P_DEC01 +XDEC10 ADDR_N_I<5> ADDR_N_I<4> CS_I CS00<2> VDD VSS / ++ RM_IHPSG13_256x16_c2_1P_DEC02 +XSEL<3> ADDR_N_I<3> ADDR_N_I<2> ADDR_N_I<1> ADDR_N_I<0> CS00<3> ECLK_H<3> ++ ECLK_H<4> ECLK_B<3> ECLK_B<4> WL_O<63> WL_O<62> WL_O<61> WL_O<60> WL_O<59> ++ WL_O<58> WL_O<57> WL_O<56> WL_O<55> WL_O<54> WL_O<53> WL_O<52> WL_O<51> ++ WL_O<50> WL_O<49> WL_O<48> VDD VSS / RM_IHPSG13_256x16_c2_1P_DEC04 +XSEL<2> ADDR_N_I<3> ADDR_N_I<2> ADDR_N_I<1> ADDR_N_I<0> CS00<2> ECLK_H<2> ++ ECLK_H<3> ECLK_B<2> ECLK_B<3> WL_O<47> WL_O<46> WL_O<45> WL_O<44> WL_O<43> ++ WL_O<42> WL_O<41> WL_O<40> WL_O<39> WL_O<38> WL_O<37> WL_O<36> WL_O<35> ++ WL_O<34> WL_O<33> WL_O<32> VDD VSS / RM_IHPSG13_256x16_c2_1P_DEC04 +XSEL<1> ADDR_N_I<3> ADDR_N_I<2> ADDR_N_I<1> ADDR_N_I<0> CS00<1> ECLK_H<1> ++ ECLK_H<2> ECLK_B<1> ECLK_B<2> WL_O<31> WL_O<30> WL_O<29> WL_O<28> WL_O<27> ++ WL_O<26> WL_O<25> WL_O<24> WL_O<23> WL_O<22> WL_O<21> WL_O<20> WL_O<19> ++ WL_O<18> WL_O<17> WL_O<16> VDD VSS / RM_IHPSG13_256x16_c2_1P_DEC04 +XSEL<0> ADDR_N_I<3> ADDR_N_I<2> ADDR_N_I<1> ADDR_N_I<0> CS00<0> ECLK_I ++ ECLK_H<1> ECLK_B<0> ECLK_B<1> WL_O<15> WL_O<14> WL_O<13> WL_O<12> WL_O<11> ++ WL_O<10> WL_O<9> WL_O<8> WL_O<7> WL_O<6> WL_O<5> WL_O<4> WL_O<3> WL_O<2> ++ WL_O<1> WL_O<0> VDD VSS / RM_IHPSG13_256x16_c2_1P_DEC04 +XL2<24> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<23> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<22> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<21> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<20> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<19> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<18> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<17> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<16> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<15> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<14> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<13> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<12> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<11> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<10> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<9> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<8> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<7> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<6> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<5> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<4> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<3> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<2> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<1> VDD VSS / RSC_IHPSG13_FILLCAP8 +.ENDS +.SUBCKT RM_IHPSG13_256x16_c2_1P_ROWREG6 ACLK_N_I ADDR_I<5> ADDR_I<4> ADDR_I<3> ADDR_I<2> ++ ADDR_I<1> ADDR_I<0> ADDR_N_O<5> ADDR_N_O<4> ADDR_N_O<3> ADDR_N_O<2> ++ ADDR_N_O<1> ADDR_N_O<0> BIST_ADDR_I<5> BIST_ADDR_I<4> BIST_ADDR_I<3> ++ BIST_ADDR_I<2> BIST_ADDR_I<1> BIST_ADDR_I<0> BIST_EN_I VDD VSS +XINV<5> q_int<5> qn_int<5> VDD VSS / RSC_IHPSG13_CINVX2 +XINV<4> q_int<4> qn_int<4> VDD VSS / RSC_IHPSG13_CINVX2 +XINV<3> q_int<3> qn_int<3> VDD VSS / RSC_IHPSG13_CINVX2 +XINV<2> q_int<2> qn_int<2> VDD VSS / RSC_IHPSG13_CINVX2 +XINV<1> q_int<1> qn_int<1> VDD VSS / RSC_IHPSG13_CINVX2 +XINV<0> q_int<0> qn_int<0> VDD VSS / RSC_IHPSG13_CINVX2 +XDRV<5> qn_int<5> ADDR_N_O<5> VDD VSS / RSC_IHPSG13_CINVX8 +XDRV<4> qn_int<4> ADDR_N_O<4> VDD VSS / RSC_IHPSG13_CINVX8 +XDRV<3> qn_int<3> ADDR_N_O<3> VDD VSS / RSC_IHPSG13_CINVX8 +XDRV<2> qn_int<2> ADDR_N_O<2> VDD VSS / RSC_IHPSG13_CINVX8 +XDRV<1> qn_int<1> ADDR_N_O<1> VDD VSS / RSC_IHPSG13_CINVX8 +XDRV<0> qn_int<0> ADDR_N_O<0> VDD VSS / RSC_IHPSG13_CINVX8 +XDFF<5> BIST_EN_I BIST_ADDR_I<5> ACLK_N_I ADDR_I<5> q_int<5> net2<0> VDD ++ VSS / RSC_IHPSG13_DFNQMX2IX1 +XDFF<4> BIST_EN_I BIST_ADDR_I<4> ACLK_N_I ADDR_I<4> q_int<4> net2<1> VDD ++ VSS / RSC_IHPSG13_DFNQMX2IX1 +XDFF<3> BIST_EN_I BIST_ADDR_I<3> ACLK_N_I ADDR_I<3> q_int<3> net2<2> VDD ++ VSS / RSC_IHPSG13_DFNQMX2IX1 +XDFF<2> BIST_EN_I BIST_ADDR_I<2> ACLK_N_I ADDR_I<2> q_int<2> net2<3> VDD ++ VSS / RSC_IHPSG13_DFNQMX2IX1 +XDFF<1> BIST_EN_I BIST_ADDR_I<1> ACLK_N_I ADDR_I<1> q_int<1> net2<4> VDD ++ VSS / RSC_IHPSG13_DFNQMX2IX1 +XDFF<0> BIST_EN_I BIST_ADDR_I<0> ACLK_N_I ADDR_I<0> q_int<0> net2<5> VDD ++ VSS / RSC_IHPSG13_DFNQMX2IX1 +XI11<12> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI11<11> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI11<10> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI11<9> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI11<8> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI11<7> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI11<6> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI11<5> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI11<4> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI11<3> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI11<2> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI11<1> VDD VSS / RSC_IHPSG13_FILLCAP8 +.ENDS + + +.SUBCKT RM_IHPSG13_256x16_c2_2P_COLUMN_pcell_0 A_BLC_BOT<1> A_BLC_BOT<0> A_BLC_TOP<1> A_BLC_TOP<0> A_BLT_BOT<1> A_BLT_BOT<0> A_BLT_TOP<1> A_BLT_TOP<0> A_LWL<63> A_LWL<62> A_LWL<61> A_LWL<60> A_LWL<59> A_LWL<58> A_LWL<57> A_LWL<56> A_LWL<55> A_LWL<54> A_LWL<53> A_LWL<52> A_LWL<51> A_LWL<50> A_LWL<49> A_LWL<48> A_LWL<47> A_LWL<46> A_LWL<45> A_LWL<44> A_LWL<43> A_LWL<42> A_LWL<41> A_LWL<40> A_LWL<39> A_LWL<38> A_LWL<37> A_LWL<36> A_LWL<35> A_LWL<34> A_LWL<33> A_LWL<32> A_LWL<31> A_LWL<30> A_LWL<29> A_LWL<28> A_LWL<27> A_LWL<26> A_LWL<25> A_LWL<24> A_LWL<23> A_LWL<22> A_LWL<21> A_LWL<20> A_LWL<19> A_LWL<18> A_LWL<17> A_LWL<16> A_LWL<15> A_LWL<14> A_LWL<13> A_LWL<12> A_LWL<11> A_LWL<10> A_LWL<9> A_LWL<8> A_LWL<7> A_LWL<6> A_LWL<5> A_LWL<4> A_LWL<3> A_LWL<2> A_LWL<1> A_LWL<0> A_RWL<63> A_RWL<62> A_RWL<61> A_RWL<60> A_RWL<59> A_RWL<58> A_RWL<57> A_RWL<56> A_RWL<55> A_RWL<54> A_RWL<53> A_RWL<52> A_RWL<51> A_RWL<50> A_RWL<49> A_RWL<48> A_RWL<47> A_RWL<46> A_RWL<45> A_RWL<44> A_RWL<43> A_RWL<42> A_RWL<41> A_RWL<40> A_RWL<39> A_RWL<38> A_RWL<37> A_RWL<36> A_RWL<35> A_RWL<34> A_RWL<33> A_RWL<32> A_RWL<31> A_RWL<30> A_RWL<29> A_RWL<28> A_RWL<27> A_RWL<26> A_RWL<25> A_RWL<24> A_RWL<23> A_RWL<22> A_RWL<21> A_RWL<20> A_RWL<19> A_RWL<18> A_RWL<17> A_RWL<16> A_RWL<15> A_RWL<14> A_RWL<13> A_RWL<12> A_RWL<11> A_RWL<10> A_RWL<9> A_RWL<8> A_RWL<7> A_RWL<6> A_RWL<5> A_RWL<4> A_RWL<3> A_RWL<2> A_RWL<1> A_RWL<0> B_BLC_BOT<1> B_BLC_BOT<0> B_BLC_TOP<1> B_BLC_TOP<0> B_BLT_BOT<1> B_BLT_BOT<0> B_BLT_TOP<1> B_BLT_TOP<0> B_LWL<63> B_LWL<62> B_LWL<61> B_LWL<60> B_LWL<59> B_LWL<58> B_LWL<57> B_LWL<56> B_LWL<55> B_LWL<54> B_LWL<53> B_LWL<52> B_LWL<51> B_LWL<50> B_LWL<49> B_LWL<48> B_LWL<47> B_LWL<46> B_LWL<45> B_LWL<44> B_LWL<43> B_LWL<42> B_LWL<41> B_LWL<40> B_LWL<39> B_LWL<38> B_LWL<37> B_LWL<36> B_LWL<35> B_LWL<34> B_LWL<33> B_LWL<32> B_LWL<31> B_LWL<30> B_LWL<29> B_LWL<28> B_LWL<27> B_LWL<26> B_LWL<25> B_LWL<24> B_LWL<23> B_LWL<22> B_LWL<21> B_LWL<20> B_LWL<19> B_LWL<18> B_LWL<17> B_LWL<16> B_LWL<15> B_LWL<14> B_LWL<13> B_LWL<12> B_LWL<11> B_LWL<10> B_LWL<9> B_LWL<8> B_LWL<7> B_LWL<6> B_LWL<5> B_LWL<4> B_LWL<3> B_LWL<2> B_LWL<1> B_LWL<0> B_RWL<63> B_RWL<62> B_RWL<61> B_RWL<60> B_RWL<59> B_RWL<58> B_RWL<57> B_RWL<56> B_RWL<55> B_RWL<54> B_RWL<53> B_RWL<52> B_RWL<51> B_RWL<50> B_RWL<49> B_RWL<48> B_RWL<47> B_RWL<46> B_RWL<45> B_RWL<44> B_RWL<43> B_RWL<42> B_RWL<41> B_RWL<40> B_RWL<39> B_RWL<38> B_RWL<37> B_RWL<36> B_RWL<35> B_RWL<34> B_RWL<33> B_RWL<32> B_RWL<31> B_RWL<30> B_RWL<29> B_RWL<28> B_RWL<27> B_RWL<26> B_RWL<25> B_RWL<24> B_RWL<23> B_RWL<22> B_RWL<21> B_RWL<20> B_RWL<19> B_RWL<18> B_RWL<17> B_RWL<16> B_RWL<15> B_RWL<14> B_RWL<13> B_RWL<12> B_RWL<11> B_RWL<10> B_RWL<9> B_RWL<8> B_RWL<7> B_RWL<6> B_RWL<5> B_RWL<4> B_RWL<3> B_RWL<2> B_RWL<1> B_RWL<0> VDD_CORE VSS +XRAM<4> A_BLC<5> A_BLC<4> A_BLC_TOP<1> A_BLC_TOP<0> A_BLT<5> A_BLT<4> A_BLT_TOP<1> A_BLT_TOP<0> A_LWL<63> A_LWL<62> A_LWL<61> A_LWL<60> A_LWL<59> A_LWL<58> A_LWL<57> A_LWL<56> A_LWL<55> A_LWL<54> A_LWL<53> A_LWL<52> A_LWL<51> A_LWL<50> A_LWL<49> A_LWL<48> A_RWL<63> A_RWL<62> A_RWL<61> A_RWL<60> A_RWL<59> A_RWL<58> A_RWL<57> A_RWL<56> A_RWL<55> A_RWL<54> A_RWL<53> A_RWL<52> A_RWL<51> A_RWL<50> A_RWL<49> A_RWL<48> B_BLC<5> B_BLC<4> B_BLC_TOP<1> B_BLC_TOP<0> B_BLT<5> B_BLT<4> B_BLT_TOP<1> B_BLT_TOP<0> B_LWL<63> B_LWL<62> B_LWL<61> B_LWL<60> B_LWL<59> B_LWL<58> B_LWL<57> B_LWL<56> B_LWL<55> B_LWL<54> B_LWL<53> B_LWL<52> B_LWL<51> B_LWL<50> B_LWL<49> B_LWL<48> B_RWL<63> B_RWL<62> B_RWL<61> B_RWL<60> B_RWL<59> B_RWL<58> B_RWL<57> B_RWL<56> B_RWL<55> B_RWL<54> B_RWL<53> B_RWL<52> B_RWL<51> B_RWL<50> B_RWL<49> B_RWL<48> VDD_CORE VSS / RM_IHPSG13_256x16_c2_2P_BITKIT_16x2_SRAM +XRAM<3> A_BLC<3> A_BLC<2> A_BLC<5> A_BLC<4> A_BLT<3> A_BLT<2> A_BLT<5> A_BLT<4> A_LWL<47> A_LWL<46> A_LWL<45> A_LWL<44> A_LWL<43> A_LWL<42> A_LWL<41> A_LWL<40> A_LWL<39> A_LWL<38> A_LWL<37> A_LWL<36> A_LWL<35> A_LWL<34> A_LWL<33> A_LWL<32> A_RWL<47> A_RWL<46> A_RWL<45> A_RWL<44> A_RWL<43> A_RWL<42> A_RWL<41> A_RWL<40> A_RWL<39> A_RWL<38> A_RWL<37> A_RWL<36> A_RWL<35> A_RWL<34> A_RWL<33> A_RWL<32> B_BLC<3> B_BLC<2> B_BLC<5> B_BLC<4> B_BLT<3> B_BLT<2> B_BLT<5> B_BLT<4> B_LWL<47> B_LWL<46> B_LWL<45> B_LWL<44> B_LWL<43> B_LWL<42> B_LWL<41> B_LWL<40> B_LWL<39> B_LWL<38> B_LWL<37> B_LWL<36> B_LWL<35> B_LWL<34> B_LWL<33> B_LWL<32> B_RWL<47> B_RWL<46> B_RWL<45> B_RWL<44> B_RWL<43> B_RWL<42> B_RWL<41> B_RWL<40> B_RWL<39> B_RWL<38> B_RWL<37> B_RWL<36> B_RWL<35> B_RWL<34> B_RWL<33> B_RWL<32> VDD_CORE VSS / RM_IHPSG13_256x16_c2_2P_BITKIT_16x2_SRAM +XRAM<2> A_BLC<1> A_BLC<0> A_BLC<3> A_BLC<2> A_BLT<1> A_BLT<0> A_BLT<3> A_BLT<2> A_LWL<31> A_LWL<30> A_LWL<29> A_LWL<28> A_LWL<27> A_LWL<26> A_LWL<25> A_LWL<24> A_LWL<23> A_LWL<22> A_LWL<21> A_LWL<20> A_LWL<19> A_LWL<18> A_LWL<17> A_LWL<16> A_RWL<31> A_RWL<30> A_RWL<29> A_RWL<28> A_RWL<27> A_RWL<26> A_RWL<25> A_RWL<24> A_RWL<23> A_RWL<22> A_RWL<21> A_RWL<20> A_RWL<19> A_RWL<18> A_RWL<17> A_RWL<16> B_BLC<1> B_BLC<0> B_BLC<3> B_BLC<2> B_BLT<1> B_BLT<0> B_BLT<3> B_BLT<2> B_LWL<31> B_LWL<30> B_LWL<29> B_LWL<28> B_LWL<27> B_LWL<26> B_LWL<25> B_LWL<24> B_LWL<23> B_LWL<22> B_LWL<21> B_LWL<20> B_LWL<19> B_LWL<18> B_LWL<17> B_LWL<16> B_RWL<31> B_RWL<30> B_RWL<29> B_RWL<28> B_RWL<27> B_RWL<26> B_RWL<25> B_RWL<24> B_RWL<23> B_RWL<22> B_RWL<21> B_RWL<20> B_RWL<19> B_RWL<18> B_RWL<17> B_RWL<16> VDD_CORE VSS / RM_IHPSG13_256x16_c2_2P_BITKIT_16x2_SRAM +XRAM<1> A_BLC_BOT<1> A_BLC_BOT<0> A_BLC<1> A_BLC<0> A_BLT_BOT<1> A_BLT_BOT<0> A_BLT<1> A_BLT<0> A_LWL<15> A_LWL<14> A_LWL<13> A_LWL<12> A_LWL<11> A_LWL<10> A_LWL<9> A_LWL<8> A_LWL<7> A_LWL<6> A_LWL<5> A_LWL<4> A_LWL<3> A_LWL<2> A_LWL<1> A_LWL<0> A_RWL<15> A_RWL<14> A_RWL<13> A_RWL<12> A_RWL<11> A_RWL<10> A_RWL<9> A_RWL<8> A_RWL<7> A_RWL<6> A_RWL<5> A_RWL<4> A_RWL<3> A_RWL<2> A_RWL<1> A_RWL<0> B_BLC_BOT<1> B_BLC_BOT<0> B_BLC<1> B_BLC<0> B_BLT_BOT<1> B_BLT_BOT<0> B_BLT<1> B_BLT<0> B_LWL<15> B_LWL<14> B_LWL<13> B_LWL<12> B_LWL<11> B_LWL<10> B_LWL<9> B_LWL<8> B_LWL<7> B_LWL<6> B_LWL<5> B_LWL<4> B_LWL<3> B_LWL<2> B_LWL<1> B_LWL<0> B_RWL<15> B_RWL<14> B_RWL<13> B_RWL<12> B_RWL<11> B_RWL<10> B_RWL<9> B_RWL<8> B_RWL<7> B_RWL<6> B_RWL<5> B_RWL<4> B_RWL<3> B_RWL<2> B_RWL<1> B_RWL<0> VDD_CORE VSS / RM_IHPSG13_256x16_c2_2P_BITKIT_16x2_SRAM +XEDGE<1> A_BLC_TOP<1> A_BLC_TOP<0> A_BLT_TOP<1> A_BLT_TOP<0> B_BLC_TOP<1> B_BLC_TOP<0> B_BLT_TOP<1> B_BLT_TOP<0> VDD_CORE VSS / RM_IHPSG13_256x16_c2_2P_BITKIT_16x2_EDGE_TB +XEDGE<0> A_BLC_BOT<1> A_BLC_BOT<0> A_BLT_BOT<1> A_BLT_BOT<0> B_BLC_BOT<1> B_BLC_BOT<0> B_BLT_BOT<1> B_BLT_BOT<0> VDD_CORE VSS / RM_IHPSG13_256x16_c2_2P_BITKIT_16x2_EDGE_TB +.ENDS + + + + +.SUBCKT RM_IHPSG13_256x16_c2_2P_MATRIX_pcell_1 A_BLC<31> A_BLC<30> A_BLC<29> A_BLC<28> A_BLC<27> A_BLC<26> A_BLC<25> A_BLC<24> A_BLC<23> A_BLC<22> A_BLC<21> A_BLC<20> A_BLC<19> A_BLC<18> A_BLC<17> A_BLC<16> A_BLC<15> A_BLC<14> A_BLC<13> A_BLC<12> A_BLC<11> A_BLC<10> A_BLC<9> A_BLC<8> A_BLC<7> A_BLC<6> A_BLC<5> A_BLC<4> A_BLC<3> A_BLC<2> A_BLC<1> A_BLC<0> A_BLT<31> A_BLT<30> A_BLT<29> A_BLT<28> A_BLT<27> A_BLT<26> A_BLT<25> A_BLT<24> A_BLT<23> A_BLT<22> A_BLT<21> A_BLT<20> A_BLT<19> A_BLT<18> A_BLT<17> A_BLT<16> A_BLT<15> A_BLT<14> A_BLT<13> A_BLT<12> A_BLT<11> A_BLT<10> A_BLT<9> A_BLT<8> A_BLT<7> A_BLT<6> A_BLT<5> A_BLT<4> A_BLT<3> A_BLT<2> A_BLT<1> A_BLT<0> A_WL<63> A_WL<62> A_WL<61> A_WL<60> A_WL<59> A_WL<58> A_WL<57> A_WL<56> A_WL<55> A_WL<54> A_WL<53> A_WL<52> A_WL<51> A_WL<50> A_WL<49> A_WL<48> A_WL<47> A_WL<46> A_WL<45> A_WL<44> A_WL<43> A_WL<42> A_WL<41> A_WL<40> A_WL<39> A_WL<38> A_WL<37> A_WL<36> A_WL<35> A_WL<34> A_WL<33> A_WL<32> A_WL<31> A_WL<30> A_WL<29> A_WL<28> A_WL<27> A_WL<26> A_WL<25> A_WL<24> A_WL<23> A_WL<22> A_WL<21> A_WL<20> A_WL<19> A_WL<18> A_WL<17> A_WL<16> A_WL<15> A_WL<14> A_WL<13> A_WL<12> A_WL<11> A_WL<10> A_WL<9> A_WL<8> A_WL<7> A_WL<6> A_WL<5> A_WL<4> A_WL<3> A_WL<2> A_WL<1> A_WL<0> B_BLC<31> B_BLC<30> B_BLC<29> B_BLC<28> B_BLC<27> B_BLC<26> B_BLC<25> B_BLC<24> B_BLC<23> B_BLC<22> B_BLC<21> B_BLC<20> B_BLC<19> B_BLC<18> B_BLC<17> B_BLC<16> B_BLC<15> B_BLC<14> B_BLC<13> B_BLC<12> B_BLC<11> B_BLC<10> B_BLC<9> B_BLC<8> B_BLC<7> B_BLC<6> B_BLC<5> B_BLC<4> B_BLC<3> B_BLC<2> B_BLC<1> B_BLC<0> B_BLT<31> B_BLT<30> B_BLT<29> B_BLT<28> B_BLT<27> B_BLT<26> B_BLT<25> B_BLT<24> B_BLT<23> B_BLT<22> B_BLT<21> B_BLT<20> B_BLT<19> B_BLT<18> B_BLT<17> B_BLT<16> B_BLT<15> B_BLT<14> B_BLT<13> B_BLT<12> B_BLT<11> B_BLT<10> B_BLT<9> B_BLT<8> B_BLT<7> B_BLT<6> B_BLT<5> B_BLT<4> B_BLT<3> B_BLT<2> B_BLT<1> B_BLT<0> B_WL<63> B_WL<62> B_WL<61> B_WL<60> B_WL<59> B_WL<58> B_WL<57> B_WL<56> B_WL<55> B_WL<54> B_WL<53> B_WL<52> B_WL<51> B_WL<50> B_WL<49> B_WL<48> B_WL<47> B_WL<46> B_WL<45> B_WL<44> B_WL<43> B_WL<42> B_WL<41> B_WL<40> B_WL<39> B_WL<38> B_WL<37> B_WL<36> B_WL<35> B_WL<34> B_WL<33> B_WL<32> B_WL<31> B_WL<30> B_WL<29> B_WL<28> B_WL<27> B_WL<26> B_WL<25> B_WL<24> B_WL<23> B_WL<22> B_WL<21> B_WL<20> B_WL<19> B_WL<18> B_WL<17> B_WL<16> B_WL<15> B_WL<14> B_WL<13> B_WL<12> B_WL<11> B_WL<10> B_WL<9> B_WL<8> B_WL<7> B_WL<6> B_WL<5> B_WL<4> B_WL<3> B_WL<2> B_WL<1> B_WL<0> VDD_CORE VSS +XCORNER<3> VDD_CORE VSS / RM_IHPSG13_256x16_c2_2P_BITKIT_16x2_CORNER +XCORNER<2> VDD_CORE VSS / RM_IHPSG13_256x16_c2_2P_BITKIT_16x2_CORNER +XCORNER<1> VDD_CORE VSS / RM_IHPSG13_256x16_c2_2P_BITKIT_16x2_CORNER +XCORNER<0> VDD_CORE VSS / RM_IHPSG13_256x16_c2_2P_BITKIT_16x2_CORNER +XRAMEDGE_L<3> A_WL<63> A_WL<62> A_WL<61> A_WL<60> A_WL<59> A_WL<58> A_WL<57> A_WL<56> A_WL<55> A_WL<54> A_WL<53> A_WL<52> A_WL<51> A_WL<50> A_WL<49> A_WL<48> B_WL<63> B_WL<62> B_WL<61> B_WL<60> B_WL<59> B_WL<58> B_WL<57> B_WL<56> B_WL<55> B_WL<54> B_WL<53> B_WL<52> B_WL<51> B_WL<50> B_WL<49> B_WL<48> VDD_CORE VSS / RM_IHPSG13_256x16_c2_2P_BITKIT_16x2_EDGE_LR +XRAMEDGE_L<2> A_WL<47> A_WL<46> A_WL<45> A_WL<44> A_WL<43> A_WL<42> A_WL<41> A_WL<40> A_WL<39> A_WL<38> A_WL<37> A_WL<36> A_WL<35> A_WL<34> A_WL<33> A_WL<32> B_WL<47> B_WL<46> B_WL<45> B_WL<44> B_WL<43> B_WL<42> B_WL<41> B_WL<40> B_WL<39> B_WL<38> B_WL<37> B_WL<36> B_WL<35> B_WL<34> B_WL<33> B_WL<32> VDD_CORE VSS / RM_IHPSG13_256x16_c2_2P_BITKIT_16x2_EDGE_LR +XRAMEDGE_L<1> A_WL<31> A_WL<30> A_WL<29> A_WL<28> A_WL<27> A_WL<26> A_WL<25> A_WL<24> A_WL<23> A_WL<22> A_WL<21> A_WL<20> A_WL<19> A_WL<18> A_WL<17> A_WL<16> B_WL<31> B_WL<30> B_WL<29> B_WL<28> B_WL<27> B_WL<26> B_WL<25> B_WL<24> B_WL<23> B_WL<22> B_WL<21> B_WL<20> B_WL<19> B_WL<18> B_WL<17> B_WL<16> VDD_CORE VSS / RM_IHPSG13_256x16_c2_2P_BITKIT_16x2_EDGE_LR +XRAMEDGE_L<0> A_WL<15> A_WL<14> A_WL<13> A_WL<12> A_WL<11> A_WL<10> A_WL<9> A_WL<8> A_WL<7> A_WL<6> A_WL<5> A_WL<4> A_WL<3> A_WL<2> A_WL<1> A_WL<0> B_WL<15> B_WL<14> B_WL<13> B_WL<12> B_WL<11> B_WL<10> B_WL<9> B_WL<8> B_WL<7> B_WL<6> B_WL<5> B_WL<4> B_WL<3> B_WL<2> B_WL<1> B_WL<0> VDD_CORE VSS / RM_IHPSG13_256x16_c2_2P_BITKIT_16x2_EDGE_LR +XRAMEDGE_R<3> A_IWL<1023> A_IWL<1022> A_IWL<1021> A_IWL<1020> A_IWL<1019> A_IWL<1018> A_IWL<1017> A_IWL<1016> A_IWL<1015> A_IWL<1014> A_IWL<1013> A_IWL<1012> A_IWL<1011> A_IWL<1010> A_IWL<1009> A_IWL<1008> B_IWL<1023> B_IWL<1022> B_IWL<1021> B_IWL<1020> B_IWL<1019> B_IWL<1018> B_IWL<1017> B_IWL<1016> B_IWL<1015> B_IWL<1014> B_IWL<1013> B_IWL<1012> B_IWL<1011> B_IWL<1010> B_IWL<1009> B_IWL<1008> VDD_CORE VSS / RM_IHPSG13_256x16_c2_2P_BITKIT_16x2_EDGE_LR +XRAMEDGE_R<2> A_IWL<1007> A_IWL<1006> A_IWL<1005> A_IWL<1004> A_IWL<1003> A_IWL<1002> A_IWL<1001> A_IWL<1000> A_IWL<999> A_IWL<998> A_IWL<997> A_IWL<996> A_IWL<995> A_IWL<994> A_IWL<993> A_IWL<992> B_IWL<1007> B_IWL<1006> B_IWL<1005> B_IWL<1004> B_IWL<1003> B_IWL<1002> B_IWL<1001> B_IWL<1000> B_IWL<999> B_IWL<998> B_IWL<997> B_IWL<996> B_IWL<995> B_IWL<994> B_IWL<993> B_IWL<992> VDD_CORE VSS / RM_IHPSG13_256x16_c2_2P_BITKIT_16x2_EDGE_LR +XRAMEDGE_R<1> A_IWL<991> A_IWL<990> A_IWL<989> A_IWL<988> A_IWL<987> A_IWL<986> A_IWL<985> A_IWL<984> A_IWL<983> A_IWL<982> A_IWL<981> A_IWL<980> A_IWL<979> A_IWL<978> A_IWL<977> A_IWL<976> B_IWL<991> B_IWL<990> B_IWL<989> B_IWL<988> B_IWL<987> B_IWL<986> B_IWL<985> B_IWL<984> B_IWL<983> B_IWL<982> B_IWL<981> B_IWL<980> B_IWL<979> B_IWL<978> B_IWL<977> B_IWL<976> VDD_CORE VSS / RM_IHPSG13_256x16_c2_2P_BITKIT_16x2_EDGE_LR +XRAMEDGE_R<0> A_IWL<975> A_IWL<974> A_IWL<973> A_IWL<972> A_IWL<971> A_IWL<970> A_IWL<969> A_IWL<968> A_IWL<967> A_IWL<966> A_IWL<965> A_IWL<964> A_IWL<963> A_IWL<962> A_IWL<961> A_IWL<960> B_IWL<975> B_IWL<974> B_IWL<973> B_IWL<972> B_IWL<971> B_IWL<970> B_IWL<969> B_IWL<968> B_IWL<967> B_IWL<966> B_IWL<965> B_IWL<964> B_IWL<963> B_IWL<962> B_IWL<961> B_IWL<960> VDD_CORE VSS / RM_IHPSG13_256x16_c2_2P_BITKIT_16x2_EDGE_LR +XCOL<15> A_BLC<31> A_BLC<30> A_BLC_TOP<31> A_BLC_TOP<30> A_BLT<31> A_BLT<30> A_BLT_TOP<31> A_BLT_TOP<30> A_IWL<959> A_IWL<958> A_IWL<957> A_IWL<956> A_IWL<955> A_IWL<954> A_IWL<953> A_IWL<952> A_IWL<951> A_IWL<950> A_IWL<949> A_IWL<948> A_IWL<947> A_IWL<946> A_IWL<945> A_IWL<944> A_IWL<943> A_IWL<942> A_IWL<941> A_IWL<940> A_IWL<939> A_IWL<938> A_IWL<937> A_IWL<936> A_IWL<935> A_IWL<934> A_IWL<933> A_IWL<932> A_IWL<931> A_IWL<930> A_IWL<929> A_IWL<928> A_IWL<927> A_IWL<926> A_IWL<925> A_IWL<924> A_IWL<923> A_IWL<922> A_IWL<921> A_IWL<920> A_IWL<919> A_IWL<918> A_IWL<917> A_IWL<916> A_IWL<915> A_IWL<914> A_IWL<913> A_IWL<912> A_IWL<911> A_IWL<910> A_IWL<909> A_IWL<908> A_IWL<907> A_IWL<906> A_IWL<905> A_IWL<904> A_IWL<903> A_IWL<902> A_IWL<901> A_IWL<900> A_IWL<899> A_IWL<898> A_IWL<897> A_IWL<896> A_IWL<1023> A_IWL<1022> A_IWL<1021> A_IWL<1020> A_IWL<1019> A_IWL<1018> A_IWL<1017> A_IWL<1016> A_IWL<1015> A_IWL<1014> A_IWL<1013> A_IWL<1012> A_IWL<1011> A_IWL<1010> A_IWL<1009> A_IWL<1008> A_IWL<1007> A_IWL<1006> A_IWL<1005> A_IWL<1004> A_IWL<1003> A_IWL<1002> A_IWL<1001> A_IWL<1000> A_IWL<999> A_IWL<998> A_IWL<997> A_IWL<996> A_IWL<995> A_IWL<994> A_IWL<993> A_IWL<992> A_IWL<991> A_IWL<990> A_IWL<989> A_IWL<988> A_IWL<987> A_IWL<986> A_IWL<985> A_IWL<984> A_IWL<983> A_IWL<982> A_IWL<981> A_IWL<980> A_IWL<979> A_IWL<978> A_IWL<977> A_IWL<976> A_IWL<975> A_IWL<974> A_IWL<973> A_IWL<972> A_IWL<971> A_IWL<970> A_IWL<969> A_IWL<968> A_IWL<967> A_IWL<966> A_IWL<965> A_IWL<964> A_IWL<963> A_IWL<962> A_IWL<961> A_IWL<960> B_BLC<31> B_BLC<30> B_BLC_TOP<31> B_BLC_TOP<30> B_BLT<31> B_BLT<30> B_BLT_TOP<31> B_BLT_TOP<30> B_IWL<959> B_IWL<958> B_IWL<957> B_IWL<956> B_IWL<955> B_IWL<954> B_IWL<953> B_IWL<952> B_IWL<951> B_IWL<950> B_IWL<949> B_IWL<948> B_IWL<947> B_IWL<946> B_IWL<945> B_IWL<944> B_IWL<943> B_IWL<942> B_IWL<941> B_IWL<940> B_IWL<939> B_IWL<938> B_IWL<937> B_IWL<936> B_IWL<935> B_IWL<934> B_IWL<933> B_IWL<932> B_IWL<931> B_IWL<930> B_IWL<929> B_IWL<928> B_IWL<927> B_IWL<926> B_IWL<925> B_IWL<924> B_IWL<923> B_IWL<922> B_IWL<921> B_IWL<920> B_IWL<919> B_IWL<918> B_IWL<917> B_IWL<916> B_IWL<915> B_IWL<914> B_IWL<913> B_IWL<912> B_IWL<911> B_IWL<910> B_IWL<909> B_IWL<908> B_IWL<907> B_IWL<906> B_IWL<905> B_IWL<904> B_IWL<903> B_IWL<902> B_IWL<901> B_IWL<900> B_IWL<899> B_IWL<898> B_IWL<897> B_IWL<896> B_IWL<1023> B_IWL<1022> B_IWL<1021> B_IWL<1020> B_IWL<1019> B_IWL<1018> B_IWL<1017> B_IWL<1016> B_IWL<1015> B_IWL<1014> B_IWL<1013> B_IWL<1012> B_IWL<1011> B_IWL<1010> B_IWL<1009> B_IWL<1008> B_IWL<1007> B_IWL<1006> B_IWL<1005> B_IWL<1004> B_IWL<1003> B_IWL<1002> B_IWL<1001> B_IWL<1000> B_IWL<999> B_IWL<998> B_IWL<997> B_IWL<996> B_IWL<995> B_IWL<994> B_IWL<993> B_IWL<992> B_IWL<991> B_IWL<990> B_IWL<989> B_IWL<988> B_IWL<987> B_IWL<986> B_IWL<985> B_IWL<984> B_IWL<983> B_IWL<982> B_IWL<981> B_IWL<980> B_IWL<979> B_IWL<978> B_IWL<977> B_IWL<976> B_IWL<975> B_IWL<974> B_IWL<973> B_IWL<972> B_IWL<971> B_IWL<970> B_IWL<969> B_IWL<968> B_IWL<967> B_IWL<966> B_IWL<965> B_IWL<964> B_IWL<963> B_IWL<962> B_IWL<961> B_IWL<960> VDD_CORE VSS / RM_IHPSG13_256x16_c2_2P_COLUMN_pcell_0 +XCOL<14> A_BLC<29> A_BLC<28> A_BLC_TOP<29> A_BLC_TOP<28> A_BLT<29> A_BLT<28> A_BLT_TOP<29> A_BLT_TOP<28> A_IWL<895> A_IWL<894> A_IWL<893> A_IWL<892> A_IWL<891> A_IWL<890> A_IWL<889> A_IWL<888> A_IWL<887> A_IWL<886> A_IWL<885> A_IWL<884> A_IWL<883> A_IWL<882> A_IWL<881> A_IWL<880> A_IWL<879> A_IWL<878> A_IWL<877> A_IWL<876> A_IWL<875> A_IWL<874> A_IWL<873> A_IWL<872> A_IWL<871> A_IWL<870> A_IWL<869> A_IWL<868> A_IWL<867> A_IWL<866> A_IWL<865> A_IWL<864> A_IWL<863> A_IWL<862> A_IWL<861> A_IWL<860> A_IWL<859> A_IWL<858> A_IWL<857> A_IWL<856> A_IWL<855> A_IWL<854> A_IWL<853> A_IWL<852> A_IWL<851> A_IWL<850> A_IWL<849> A_IWL<848> A_IWL<847> A_IWL<846> A_IWL<845> A_IWL<844> A_IWL<843> A_IWL<842> A_IWL<841> A_IWL<840> A_IWL<839> A_IWL<838> A_IWL<837> A_IWL<836> A_IWL<835> A_IWL<834> A_IWL<833> A_IWL<832> A_IWL<959> A_IWL<958> A_IWL<957> A_IWL<956> A_IWL<955> A_IWL<954> A_IWL<953> A_IWL<952> A_IWL<951> A_IWL<950> A_IWL<949> A_IWL<948> A_IWL<947> A_IWL<946> A_IWL<945> A_IWL<944> A_IWL<943> A_IWL<942> A_IWL<941> A_IWL<940> A_IWL<939> A_IWL<938> A_IWL<937> A_IWL<936> A_IWL<935> A_IWL<934> A_IWL<933> A_IWL<932> A_IWL<931> A_IWL<930> A_IWL<929> A_IWL<928> A_IWL<927> A_IWL<926> A_IWL<925> A_IWL<924> A_IWL<923> A_IWL<922> A_IWL<921> A_IWL<920> A_IWL<919> A_IWL<918> A_IWL<917> A_IWL<916> A_IWL<915> A_IWL<914> A_IWL<913> A_IWL<912> A_IWL<911> A_IWL<910> A_IWL<909> A_IWL<908> A_IWL<907> A_IWL<906> A_IWL<905> A_IWL<904> A_IWL<903> A_IWL<902> A_IWL<901> A_IWL<900> A_IWL<899> A_IWL<898> A_IWL<897> A_IWL<896> B_BLC<29> B_BLC<28> B_BLC_TOP<29> B_BLC_TOP<28> B_BLT<29> B_BLT<28> B_BLT_TOP<29> B_BLT_TOP<28> B_IWL<895> B_IWL<894> B_IWL<893> B_IWL<892> B_IWL<891> B_IWL<890> B_IWL<889> B_IWL<888> B_IWL<887> B_IWL<886> B_IWL<885> B_IWL<884> B_IWL<883> B_IWL<882> B_IWL<881> B_IWL<880> B_IWL<879> B_IWL<878> B_IWL<877> B_IWL<876> B_IWL<875> B_IWL<874> B_IWL<873> B_IWL<872> B_IWL<871> B_IWL<870> B_IWL<869> B_IWL<868> B_IWL<867> B_IWL<866> B_IWL<865> B_IWL<864> B_IWL<863> B_IWL<862> B_IWL<861> B_IWL<860> B_IWL<859> B_IWL<858> B_IWL<857> B_IWL<856> B_IWL<855> B_IWL<854> B_IWL<853> B_IWL<852> B_IWL<851> B_IWL<850> B_IWL<849> B_IWL<848> B_IWL<847> B_IWL<846> B_IWL<845> B_IWL<844> B_IWL<843> B_IWL<842> B_IWL<841> B_IWL<840> B_IWL<839> B_IWL<838> B_IWL<837> B_IWL<836> B_IWL<835> B_IWL<834> B_IWL<833> B_IWL<832> B_IWL<959> B_IWL<958> B_IWL<957> B_IWL<956> B_IWL<955> B_IWL<954> B_IWL<953> B_IWL<952> B_IWL<951> B_IWL<950> B_IWL<949> B_IWL<948> B_IWL<947> B_IWL<946> B_IWL<945> B_IWL<944> B_IWL<943> B_IWL<942> B_IWL<941> B_IWL<940> B_IWL<939> B_IWL<938> B_IWL<937> B_IWL<936> B_IWL<935> B_IWL<934> B_IWL<933> B_IWL<932> B_IWL<931> B_IWL<930> B_IWL<929> B_IWL<928> B_IWL<927> B_IWL<926> B_IWL<925> B_IWL<924> B_IWL<923> B_IWL<922> B_IWL<921> B_IWL<920> B_IWL<919> B_IWL<918> B_IWL<917> B_IWL<916> B_IWL<915> B_IWL<914> B_IWL<913> B_IWL<912> B_IWL<911> B_IWL<910> B_IWL<909> B_IWL<908> B_IWL<907> B_IWL<906> B_IWL<905> B_IWL<904> B_IWL<903> B_IWL<902> B_IWL<901> B_IWL<900> B_IWL<899> B_IWL<898> B_IWL<897> B_IWL<896> VDD_CORE VSS / RM_IHPSG13_256x16_c2_2P_COLUMN_pcell_0 +XCOL<13> A_BLC<27> A_BLC<26> A_BLC_TOP<27> A_BLC_TOP<26> A_BLT<27> A_BLT<26> A_BLT_TOP<27> A_BLT_TOP<26> A_IWL<831> A_IWL<830> A_IWL<829> A_IWL<828> A_IWL<827> A_IWL<826> A_IWL<825> A_IWL<824> A_IWL<823> A_IWL<822> A_IWL<821> A_IWL<820> A_IWL<819> A_IWL<818> A_IWL<817> A_IWL<816> A_IWL<815> A_IWL<814> A_IWL<813> A_IWL<812> A_IWL<811> A_IWL<810> A_IWL<809> A_IWL<808> A_IWL<807> A_IWL<806> A_IWL<805> A_IWL<804> A_IWL<803> A_IWL<802> A_IWL<801> A_IWL<800> A_IWL<799> A_IWL<798> A_IWL<797> A_IWL<796> A_IWL<795> A_IWL<794> A_IWL<793> A_IWL<792> A_IWL<791> A_IWL<790> A_IWL<789> A_IWL<788> A_IWL<787> A_IWL<786> A_IWL<785> A_IWL<784> A_IWL<783> A_IWL<782> A_IWL<781> A_IWL<780> A_IWL<779> A_IWL<778> A_IWL<777> A_IWL<776> A_IWL<775> A_IWL<774> A_IWL<773> A_IWL<772> A_IWL<771> A_IWL<770> A_IWL<769> A_IWL<768> A_IWL<895> A_IWL<894> A_IWL<893> A_IWL<892> A_IWL<891> A_IWL<890> A_IWL<889> A_IWL<888> A_IWL<887> A_IWL<886> A_IWL<885> A_IWL<884> A_IWL<883> A_IWL<882> A_IWL<881> A_IWL<880> A_IWL<879> A_IWL<878> A_IWL<877> A_IWL<876> A_IWL<875> A_IWL<874> A_IWL<873> A_IWL<872> A_IWL<871> A_IWL<870> A_IWL<869> A_IWL<868> A_IWL<867> A_IWL<866> A_IWL<865> A_IWL<864> A_IWL<863> A_IWL<862> A_IWL<861> A_IWL<860> A_IWL<859> A_IWL<858> A_IWL<857> A_IWL<856> A_IWL<855> A_IWL<854> A_IWL<853> A_IWL<852> A_IWL<851> A_IWL<850> A_IWL<849> A_IWL<848> A_IWL<847> A_IWL<846> A_IWL<845> A_IWL<844> A_IWL<843> A_IWL<842> A_IWL<841> A_IWL<840> A_IWL<839> A_IWL<838> A_IWL<837> A_IWL<836> A_IWL<835> A_IWL<834> A_IWL<833> A_IWL<832> B_BLC<27> B_BLC<26> B_BLC_TOP<27> B_BLC_TOP<26> B_BLT<27> B_BLT<26> B_BLT_TOP<27> B_BLT_TOP<26> B_IWL<831> B_IWL<830> B_IWL<829> B_IWL<828> B_IWL<827> B_IWL<826> B_IWL<825> B_IWL<824> B_IWL<823> B_IWL<822> B_IWL<821> B_IWL<820> B_IWL<819> B_IWL<818> B_IWL<817> B_IWL<816> B_IWL<815> B_IWL<814> B_IWL<813> B_IWL<812> B_IWL<811> B_IWL<810> B_IWL<809> B_IWL<808> B_IWL<807> B_IWL<806> B_IWL<805> B_IWL<804> B_IWL<803> B_IWL<802> B_IWL<801> B_IWL<800> B_IWL<799> B_IWL<798> B_IWL<797> B_IWL<796> B_IWL<795> B_IWL<794> B_IWL<793> B_IWL<792> B_IWL<791> B_IWL<790> B_IWL<789> B_IWL<788> B_IWL<787> B_IWL<786> B_IWL<785> B_IWL<784> B_IWL<783> B_IWL<782> B_IWL<781> B_IWL<780> B_IWL<779> B_IWL<778> B_IWL<777> B_IWL<776> B_IWL<775> B_IWL<774> B_IWL<773> B_IWL<772> B_IWL<771> B_IWL<770> B_IWL<769> B_IWL<768> B_IWL<895> B_IWL<894> B_IWL<893> B_IWL<892> B_IWL<891> B_IWL<890> B_IWL<889> B_IWL<888> B_IWL<887> B_IWL<886> B_IWL<885> B_IWL<884> B_IWL<883> B_IWL<882> B_IWL<881> B_IWL<880> B_IWL<879> B_IWL<878> B_IWL<877> B_IWL<876> B_IWL<875> B_IWL<874> B_IWL<873> B_IWL<872> B_IWL<871> B_IWL<870> B_IWL<869> B_IWL<868> B_IWL<867> B_IWL<866> B_IWL<865> B_IWL<864> B_IWL<863> B_IWL<862> B_IWL<861> B_IWL<860> B_IWL<859> B_IWL<858> B_IWL<857> B_IWL<856> B_IWL<855> B_IWL<854> B_IWL<853> B_IWL<852> B_IWL<851> B_IWL<850> B_IWL<849> B_IWL<848> B_IWL<847> B_IWL<846> B_IWL<845> B_IWL<844> B_IWL<843> B_IWL<842> B_IWL<841> B_IWL<840> B_IWL<839> B_IWL<838> B_IWL<837> B_IWL<836> B_IWL<835> B_IWL<834> B_IWL<833> B_IWL<832> VDD_CORE VSS / RM_IHPSG13_256x16_c2_2P_COLUMN_pcell_0 +XCOL<12> A_BLC<25> A_BLC<24> A_BLC_TOP<25> A_BLC_TOP<24> A_BLT<25> A_BLT<24> A_BLT_TOP<25> A_BLT_TOP<24> A_IWL<767> A_IWL<766> A_IWL<765> A_IWL<764> A_IWL<763> A_IWL<762> A_IWL<761> A_IWL<760> A_IWL<759> A_IWL<758> A_IWL<757> A_IWL<756> A_IWL<755> A_IWL<754> A_IWL<753> A_IWL<752> A_IWL<751> A_IWL<750> A_IWL<749> A_IWL<748> A_IWL<747> A_IWL<746> A_IWL<745> A_IWL<744> A_IWL<743> A_IWL<742> A_IWL<741> A_IWL<740> A_IWL<739> A_IWL<738> A_IWL<737> A_IWL<736> A_IWL<735> A_IWL<734> A_IWL<733> A_IWL<732> A_IWL<731> A_IWL<730> A_IWL<729> A_IWL<728> A_IWL<727> A_IWL<726> A_IWL<725> A_IWL<724> A_IWL<723> A_IWL<722> A_IWL<721> A_IWL<720> A_IWL<719> A_IWL<718> A_IWL<717> A_IWL<716> A_IWL<715> A_IWL<714> A_IWL<713> A_IWL<712> A_IWL<711> A_IWL<710> A_IWL<709> A_IWL<708> A_IWL<707> A_IWL<706> A_IWL<705> A_IWL<704> A_IWL<831> A_IWL<830> A_IWL<829> A_IWL<828> A_IWL<827> A_IWL<826> A_IWL<825> A_IWL<824> A_IWL<823> A_IWL<822> A_IWL<821> A_IWL<820> A_IWL<819> A_IWL<818> A_IWL<817> A_IWL<816> A_IWL<815> A_IWL<814> A_IWL<813> A_IWL<812> A_IWL<811> A_IWL<810> A_IWL<809> A_IWL<808> A_IWL<807> A_IWL<806> A_IWL<805> A_IWL<804> A_IWL<803> A_IWL<802> A_IWL<801> A_IWL<800> A_IWL<799> A_IWL<798> A_IWL<797> A_IWL<796> A_IWL<795> A_IWL<794> A_IWL<793> A_IWL<792> A_IWL<791> A_IWL<790> A_IWL<789> A_IWL<788> A_IWL<787> A_IWL<786> A_IWL<785> A_IWL<784> A_IWL<783> A_IWL<782> A_IWL<781> A_IWL<780> A_IWL<779> A_IWL<778> A_IWL<777> A_IWL<776> A_IWL<775> A_IWL<774> A_IWL<773> A_IWL<772> A_IWL<771> A_IWL<770> A_IWL<769> A_IWL<768> B_BLC<25> B_BLC<24> B_BLC_TOP<25> B_BLC_TOP<24> B_BLT<25> B_BLT<24> B_BLT_TOP<25> B_BLT_TOP<24> B_IWL<767> B_IWL<766> B_IWL<765> B_IWL<764> B_IWL<763> B_IWL<762> B_IWL<761> B_IWL<760> B_IWL<759> B_IWL<758> B_IWL<757> B_IWL<756> B_IWL<755> B_IWL<754> B_IWL<753> B_IWL<752> B_IWL<751> B_IWL<750> B_IWL<749> B_IWL<748> B_IWL<747> B_IWL<746> B_IWL<745> B_IWL<744> B_IWL<743> B_IWL<742> B_IWL<741> B_IWL<740> B_IWL<739> B_IWL<738> B_IWL<737> B_IWL<736> B_IWL<735> B_IWL<734> B_IWL<733> B_IWL<732> B_IWL<731> B_IWL<730> B_IWL<729> B_IWL<728> B_IWL<727> B_IWL<726> B_IWL<725> B_IWL<724> B_IWL<723> B_IWL<722> B_IWL<721> B_IWL<720> B_IWL<719> B_IWL<718> B_IWL<717> B_IWL<716> B_IWL<715> B_IWL<714> B_IWL<713> B_IWL<712> B_IWL<711> B_IWL<710> B_IWL<709> B_IWL<708> B_IWL<707> B_IWL<706> B_IWL<705> B_IWL<704> B_IWL<831> B_IWL<830> B_IWL<829> B_IWL<828> B_IWL<827> B_IWL<826> B_IWL<825> B_IWL<824> B_IWL<823> B_IWL<822> B_IWL<821> B_IWL<820> B_IWL<819> B_IWL<818> B_IWL<817> B_IWL<816> B_IWL<815> B_IWL<814> B_IWL<813> B_IWL<812> B_IWL<811> B_IWL<810> B_IWL<809> B_IWL<808> B_IWL<807> B_IWL<806> B_IWL<805> B_IWL<804> B_IWL<803> B_IWL<802> B_IWL<801> B_IWL<800> B_IWL<799> B_IWL<798> B_IWL<797> B_IWL<796> B_IWL<795> B_IWL<794> B_IWL<793> B_IWL<792> B_IWL<791> B_IWL<790> B_IWL<789> B_IWL<788> B_IWL<787> B_IWL<786> B_IWL<785> B_IWL<784> B_IWL<783> B_IWL<782> B_IWL<781> B_IWL<780> B_IWL<779> B_IWL<778> B_IWL<777> B_IWL<776> B_IWL<775> B_IWL<774> B_IWL<773> B_IWL<772> B_IWL<771> B_IWL<770> B_IWL<769> B_IWL<768> VDD_CORE VSS / RM_IHPSG13_256x16_c2_2P_COLUMN_pcell_0 +XCOL<11> A_BLC<23> A_BLC<22> A_BLC_TOP<23> A_BLC_TOP<22> A_BLT<23> A_BLT<22> A_BLT_TOP<23> A_BLT_TOP<22> A_IWL<703> A_IWL<702> A_IWL<701> A_IWL<700> A_IWL<699> A_IWL<698> A_IWL<697> A_IWL<696> A_IWL<695> A_IWL<694> A_IWL<693> A_IWL<692> A_IWL<691> A_IWL<690> A_IWL<689> A_IWL<688> A_IWL<687> A_IWL<686> A_IWL<685> A_IWL<684> A_IWL<683> A_IWL<682> A_IWL<681> A_IWL<680> A_IWL<679> A_IWL<678> A_IWL<677> A_IWL<676> A_IWL<675> A_IWL<674> A_IWL<673> A_IWL<672> A_IWL<671> A_IWL<670> A_IWL<669> A_IWL<668> A_IWL<667> A_IWL<666> A_IWL<665> A_IWL<664> A_IWL<663> A_IWL<662> A_IWL<661> A_IWL<660> A_IWL<659> A_IWL<658> A_IWL<657> A_IWL<656> A_IWL<655> A_IWL<654> A_IWL<653> A_IWL<652> A_IWL<651> A_IWL<650> A_IWL<649> A_IWL<648> A_IWL<647> A_IWL<646> A_IWL<645> A_IWL<644> A_IWL<643> A_IWL<642> A_IWL<641> A_IWL<640> A_IWL<767> A_IWL<766> A_IWL<765> A_IWL<764> A_IWL<763> A_IWL<762> A_IWL<761> A_IWL<760> A_IWL<759> A_IWL<758> A_IWL<757> A_IWL<756> A_IWL<755> A_IWL<754> A_IWL<753> A_IWL<752> A_IWL<751> A_IWL<750> A_IWL<749> A_IWL<748> A_IWL<747> A_IWL<746> A_IWL<745> A_IWL<744> A_IWL<743> A_IWL<742> A_IWL<741> A_IWL<740> A_IWL<739> A_IWL<738> A_IWL<737> A_IWL<736> A_IWL<735> A_IWL<734> A_IWL<733> A_IWL<732> A_IWL<731> A_IWL<730> A_IWL<729> A_IWL<728> A_IWL<727> A_IWL<726> A_IWL<725> A_IWL<724> A_IWL<723> A_IWL<722> A_IWL<721> A_IWL<720> A_IWL<719> A_IWL<718> A_IWL<717> A_IWL<716> A_IWL<715> A_IWL<714> A_IWL<713> A_IWL<712> A_IWL<711> A_IWL<710> A_IWL<709> A_IWL<708> A_IWL<707> A_IWL<706> A_IWL<705> A_IWL<704> B_BLC<23> B_BLC<22> B_BLC_TOP<23> B_BLC_TOP<22> B_BLT<23> B_BLT<22> B_BLT_TOP<23> B_BLT_TOP<22> B_IWL<703> B_IWL<702> B_IWL<701> B_IWL<700> B_IWL<699> B_IWL<698> B_IWL<697> B_IWL<696> B_IWL<695> B_IWL<694> B_IWL<693> B_IWL<692> B_IWL<691> B_IWL<690> B_IWL<689> B_IWL<688> B_IWL<687> B_IWL<686> B_IWL<685> B_IWL<684> B_IWL<683> B_IWL<682> B_IWL<681> B_IWL<680> B_IWL<679> B_IWL<678> B_IWL<677> B_IWL<676> B_IWL<675> B_IWL<674> B_IWL<673> B_IWL<672> B_IWL<671> B_IWL<670> B_IWL<669> B_IWL<668> B_IWL<667> B_IWL<666> B_IWL<665> B_IWL<664> B_IWL<663> B_IWL<662> B_IWL<661> B_IWL<660> B_IWL<659> B_IWL<658> B_IWL<657> B_IWL<656> B_IWL<655> B_IWL<654> B_IWL<653> B_IWL<652> B_IWL<651> B_IWL<650> B_IWL<649> B_IWL<648> B_IWL<647> B_IWL<646> B_IWL<645> B_IWL<644> B_IWL<643> B_IWL<642> B_IWL<641> B_IWL<640> B_IWL<767> B_IWL<766> B_IWL<765> B_IWL<764> B_IWL<763> B_IWL<762> B_IWL<761> B_IWL<760> B_IWL<759> B_IWL<758> B_IWL<757> B_IWL<756> B_IWL<755> B_IWL<754> B_IWL<753> B_IWL<752> B_IWL<751> B_IWL<750> B_IWL<749> B_IWL<748> B_IWL<747> B_IWL<746> B_IWL<745> B_IWL<744> B_IWL<743> B_IWL<742> B_IWL<741> B_IWL<740> B_IWL<739> B_IWL<738> B_IWL<737> B_IWL<736> B_IWL<735> B_IWL<734> B_IWL<733> B_IWL<732> B_IWL<731> B_IWL<730> B_IWL<729> B_IWL<728> B_IWL<727> B_IWL<726> B_IWL<725> B_IWL<724> B_IWL<723> B_IWL<722> B_IWL<721> B_IWL<720> B_IWL<719> B_IWL<718> B_IWL<717> B_IWL<716> B_IWL<715> B_IWL<714> B_IWL<713> B_IWL<712> B_IWL<711> B_IWL<710> B_IWL<709> B_IWL<708> B_IWL<707> B_IWL<706> B_IWL<705> B_IWL<704> VDD_CORE VSS / RM_IHPSG13_256x16_c2_2P_COLUMN_pcell_0 +XCOL<10> A_BLC<21> A_BLC<20> A_BLC_TOP<21> A_BLC_TOP<20> A_BLT<21> A_BLT<20> A_BLT_TOP<21> A_BLT_TOP<20> A_IWL<639> A_IWL<638> A_IWL<637> A_IWL<636> A_IWL<635> A_IWL<634> A_IWL<633> A_IWL<632> A_IWL<631> A_IWL<630> A_IWL<629> A_IWL<628> A_IWL<627> A_IWL<626> A_IWL<625> A_IWL<624> A_IWL<623> A_IWL<622> A_IWL<621> A_IWL<620> A_IWL<619> A_IWL<618> A_IWL<617> A_IWL<616> A_IWL<615> A_IWL<614> A_IWL<613> A_IWL<612> A_IWL<611> A_IWL<610> A_IWL<609> A_IWL<608> A_IWL<607> A_IWL<606> A_IWL<605> A_IWL<604> A_IWL<603> A_IWL<602> A_IWL<601> A_IWL<600> A_IWL<599> A_IWL<598> A_IWL<597> A_IWL<596> A_IWL<595> A_IWL<594> A_IWL<593> A_IWL<592> A_IWL<591> A_IWL<590> A_IWL<589> A_IWL<588> A_IWL<587> A_IWL<586> A_IWL<585> A_IWL<584> A_IWL<583> A_IWL<582> A_IWL<581> A_IWL<580> A_IWL<579> A_IWL<578> A_IWL<577> A_IWL<576> A_IWL<703> A_IWL<702> A_IWL<701> A_IWL<700> A_IWL<699> A_IWL<698> A_IWL<697> A_IWL<696> A_IWL<695> A_IWL<694> A_IWL<693> A_IWL<692> A_IWL<691> A_IWL<690> A_IWL<689> A_IWL<688> A_IWL<687> A_IWL<686> A_IWL<685> A_IWL<684> A_IWL<683> A_IWL<682> A_IWL<681> A_IWL<680> A_IWL<679> A_IWL<678> A_IWL<677> A_IWL<676> A_IWL<675> A_IWL<674> A_IWL<673> A_IWL<672> A_IWL<671> A_IWL<670> A_IWL<669> A_IWL<668> A_IWL<667> A_IWL<666> A_IWL<665> A_IWL<664> A_IWL<663> A_IWL<662> A_IWL<661> A_IWL<660> A_IWL<659> A_IWL<658> A_IWL<657> A_IWL<656> A_IWL<655> A_IWL<654> A_IWL<653> A_IWL<652> A_IWL<651> A_IWL<650> A_IWL<649> A_IWL<648> A_IWL<647> A_IWL<646> A_IWL<645> A_IWL<644> A_IWL<643> A_IWL<642> A_IWL<641> A_IWL<640> B_BLC<21> B_BLC<20> B_BLC_TOP<21> B_BLC_TOP<20> B_BLT<21> B_BLT<20> B_BLT_TOP<21> B_BLT_TOP<20> B_IWL<639> B_IWL<638> B_IWL<637> B_IWL<636> B_IWL<635> B_IWL<634> B_IWL<633> B_IWL<632> B_IWL<631> B_IWL<630> B_IWL<629> B_IWL<628> B_IWL<627> B_IWL<626> B_IWL<625> B_IWL<624> B_IWL<623> B_IWL<622> B_IWL<621> B_IWL<620> B_IWL<619> B_IWL<618> B_IWL<617> B_IWL<616> B_IWL<615> B_IWL<614> B_IWL<613> B_IWL<612> B_IWL<611> B_IWL<610> B_IWL<609> B_IWL<608> B_IWL<607> B_IWL<606> B_IWL<605> B_IWL<604> B_IWL<603> B_IWL<602> B_IWL<601> B_IWL<600> B_IWL<599> B_IWL<598> B_IWL<597> B_IWL<596> B_IWL<595> B_IWL<594> B_IWL<593> B_IWL<592> B_IWL<591> B_IWL<590> B_IWL<589> B_IWL<588> B_IWL<587> B_IWL<586> B_IWL<585> B_IWL<584> B_IWL<583> B_IWL<582> B_IWL<581> B_IWL<580> B_IWL<579> B_IWL<578> B_IWL<577> B_IWL<576> B_IWL<703> B_IWL<702> B_IWL<701> B_IWL<700> B_IWL<699> B_IWL<698> B_IWL<697> B_IWL<696> B_IWL<695> B_IWL<694> B_IWL<693> B_IWL<692> B_IWL<691> B_IWL<690> B_IWL<689> B_IWL<688> B_IWL<687> B_IWL<686> B_IWL<685> B_IWL<684> B_IWL<683> B_IWL<682> B_IWL<681> B_IWL<680> B_IWL<679> B_IWL<678> B_IWL<677> B_IWL<676> B_IWL<675> B_IWL<674> B_IWL<673> B_IWL<672> B_IWL<671> B_IWL<670> B_IWL<669> B_IWL<668> B_IWL<667> B_IWL<666> B_IWL<665> B_IWL<664> B_IWL<663> B_IWL<662> B_IWL<661> B_IWL<660> B_IWL<659> B_IWL<658> B_IWL<657> B_IWL<656> B_IWL<655> B_IWL<654> B_IWL<653> B_IWL<652> B_IWL<651> B_IWL<650> B_IWL<649> B_IWL<648> B_IWL<647> B_IWL<646> B_IWL<645> B_IWL<644> B_IWL<643> B_IWL<642> B_IWL<641> B_IWL<640> VDD_CORE VSS / RM_IHPSG13_256x16_c2_2P_COLUMN_pcell_0 +XCOL<9> A_BLC<19> A_BLC<18> A_BLC_TOP<19> A_BLC_TOP<18> A_BLT<19> A_BLT<18> A_BLT_TOP<19> A_BLT_TOP<18> A_IWL<575> A_IWL<574> A_IWL<573> A_IWL<572> A_IWL<571> A_IWL<570> A_IWL<569> A_IWL<568> A_IWL<567> A_IWL<566> A_IWL<565> A_IWL<564> A_IWL<563> A_IWL<562> A_IWL<561> A_IWL<560> A_IWL<559> A_IWL<558> A_IWL<557> A_IWL<556> A_IWL<555> A_IWL<554> A_IWL<553> A_IWL<552> A_IWL<551> A_IWL<550> A_IWL<549> A_IWL<548> A_IWL<547> A_IWL<546> A_IWL<545> A_IWL<544> A_IWL<543> A_IWL<542> A_IWL<541> A_IWL<540> A_IWL<539> A_IWL<538> A_IWL<537> A_IWL<536> A_IWL<535> A_IWL<534> A_IWL<533> A_IWL<532> A_IWL<531> A_IWL<530> A_IWL<529> A_IWL<528> A_IWL<527> A_IWL<526> A_IWL<525> A_IWL<524> A_IWL<523> A_IWL<522> A_IWL<521> A_IWL<520> A_IWL<519> A_IWL<518> A_IWL<517> A_IWL<516> A_IWL<515> A_IWL<514> A_IWL<513> A_IWL<512> A_IWL<639> A_IWL<638> A_IWL<637> A_IWL<636> A_IWL<635> A_IWL<634> A_IWL<633> A_IWL<632> A_IWL<631> A_IWL<630> A_IWL<629> A_IWL<628> A_IWL<627> A_IWL<626> A_IWL<625> A_IWL<624> A_IWL<623> A_IWL<622> A_IWL<621> A_IWL<620> A_IWL<619> A_IWL<618> A_IWL<617> A_IWL<616> A_IWL<615> A_IWL<614> A_IWL<613> A_IWL<612> A_IWL<611> A_IWL<610> A_IWL<609> A_IWL<608> A_IWL<607> A_IWL<606> A_IWL<605> A_IWL<604> A_IWL<603> A_IWL<602> A_IWL<601> A_IWL<600> A_IWL<599> A_IWL<598> A_IWL<597> A_IWL<596> A_IWL<595> A_IWL<594> A_IWL<593> A_IWL<592> A_IWL<591> A_IWL<590> A_IWL<589> A_IWL<588> A_IWL<587> A_IWL<586> A_IWL<585> A_IWL<584> A_IWL<583> A_IWL<582> A_IWL<581> A_IWL<580> A_IWL<579> A_IWL<578> A_IWL<577> A_IWL<576> B_BLC<19> B_BLC<18> B_BLC_TOP<19> B_BLC_TOP<18> B_BLT<19> B_BLT<18> B_BLT_TOP<19> B_BLT_TOP<18> B_IWL<575> B_IWL<574> B_IWL<573> B_IWL<572> B_IWL<571> B_IWL<570> B_IWL<569> B_IWL<568> B_IWL<567> B_IWL<566> B_IWL<565> B_IWL<564> B_IWL<563> B_IWL<562> B_IWL<561> B_IWL<560> B_IWL<559> B_IWL<558> B_IWL<557> B_IWL<556> B_IWL<555> B_IWL<554> B_IWL<553> B_IWL<552> B_IWL<551> B_IWL<550> B_IWL<549> B_IWL<548> B_IWL<547> B_IWL<546> B_IWL<545> B_IWL<544> B_IWL<543> B_IWL<542> B_IWL<541> B_IWL<540> B_IWL<539> B_IWL<538> B_IWL<537> B_IWL<536> B_IWL<535> B_IWL<534> B_IWL<533> B_IWL<532> B_IWL<531> B_IWL<530> B_IWL<529> B_IWL<528> B_IWL<527> B_IWL<526> B_IWL<525> B_IWL<524> B_IWL<523> B_IWL<522> B_IWL<521> B_IWL<520> B_IWL<519> B_IWL<518> B_IWL<517> B_IWL<516> B_IWL<515> B_IWL<514> B_IWL<513> B_IWL<512> B_IWL<639> B_IWL<638> B_IWL<637> B_IWL<636> B_IWL<635> B_IWL<634> B_IWL<633> B_IWL<632> B_IWL<631> B_IWL<630> B_IWL<629> B_IWL<628> B_IWL<627> B_IWL<626> B_IWL<625> B_IWL<624> B_IWL<623> B_IWL<622> B_IWL<621> B_IWL<620> B_IWL<619> B_IWL<618> B_IWL<617> B_IWL<616> B_IWL<615> B_IWL<614> B_IWL<613> B_IWL<612> B_IWL<611> B_IWL<610> B_IWL<609> B_IWL<608> B_IWL<607> B_IWL<606> B_IWL<605> B_IWL<604> B_IWL<603> B_IWL<602> B_IWL<601> B_IWL<600> B_IWL<599> B_IWL<598> B_IWL<597> B_IWL<596> B_IWL<595> B_IWL<594> B_IWL<593> B_IWL<592> B_IWL<591> B_IWL<590> B_IWL<589> B_IWL<588> B_IWL<587> B_IWL<586> B_IWL<585> B_IWL<584> B_IWL<583> B_IWL<582> B_IWL<581> B_IWL<580> B_IWL<579> B_IWL<578> B_IWL<577> B_IWL<576> VDD_CORE VSS / RM_IHPSG13_256x16_c2_2P_COLUMN_pcell_0 +XCOL<8> A_BLC<17> A_BLC<16> A_BLC_TOP<17> A_BLC_TOP<16> A_BLT<17> A_BLT<16> A_BLT_TOP<17> A_BLT_TOP<16> A_IWL<511> A_IWL<510> A_IWL<509> A_IWL<508> A_IWL<507> A_IWL<506> A_IWL<505> A_IWL<504> A_IWL<503> A_IWL<502> A_IWL<501> A_IWL<500> A_IWL<499> A_IWL<498> A_IWL<497> A_IWL<496> A_IWL<495> A_IWL<494> A_IWL<493> A_IWL<492> A_IWL<491> A_IWL<490> A_IWL<489> A_IWL<488> A_IWL<487> A_IWL<486> A_IWL<485> A_IWL<484> A_IWL<483> A_IWL<482> A_IWL<481> A_IWL<480> A_IWL<479> A_IWL<478> A_IWL<477> A_IWL<476> A_IWL<475> A_IWL<474> A_IWL<473> A_IWL<472> A_IWL<471> A_IWL<470> A_IWL<469> A_IWL<468> A_IWL<467> A_IWL<466> A_IWL<465> A_IWL<464> A_IWL<463> A_IWL<462> A_IWL<461> A_IWL<460> A_IWL<459> A_IWL<458> A_IWL<457> A_IWL<456> A_IWL<455> A_IWL<454> A_IWL<453> A_IWL<452> A_IWL<451> A_IWL<450> A_IWL<449> A_IWL<448> A_IWL<575> A_IWL<574> A_IWL<573> A_IWL<572> A_IWL<571> A_IWL<570> A_IWL<569> A_IWL<568> A_IWL<567> A_IWL<566> A_IWL<565> A_IWL<564> A_IWL<563> A_IWL<562> A_IWL<561> A_IWL<560> A_IWL<559> A_IWL<558> A_IWL<557> A_IWL<556> A_IWL<555> A_IWL<554> A_IWL<553> A_IWL<552> A_IWL<551> A_IWL<550> A_IWL<549> A_IWL<548> A_IWL<547> A_IWL<546> A_IWL<545> A_IWL<544> A_IWL<543> A_IWL<542> A_IWL<541> A_IWL<540> A_IWL<539> A_IWL<538> A_IWL<537> A_IWL<536> A_IWL<535> A_IWL<534> A_IWL<533> A_IWL<532> A_IWL<531> A_IWL<530> A_IWL<529> A_IWL<528> A_IWL<527> A_IWL<526> A_IWL<525> A_IWL<524> A_IWL<523> A_IWL<522> A_IWL<521> A_IWL<520> A_IWL<519> A_IWL<518> A_IWL<517> A_IWL<516> A_IWL<515> A_IWL<514> A_IWL<513> A_IWL<512> B_BLC<17> B_BLC<16> B_BLC_TOP<17> B_BLC_TOP<16> B_BLT<17> B_BLT<16> B_BLT_TOP<17> B_BLT_TOP<16> B_IWL<511> B_IWL<510> B_IWL<509> B_IWL<508> B_IWL<507> B_IWL<506> B_IWL<505> B_IWL<504> B_IWL<503> B_IWL<502> B_IWL<501> B_IWL<500> B_IWL<499> B_IWL<498> B_IWL<497> B_IWL<496> B_IWL<495> B_IWL<494> B_IWL<493> B_IWL<492> B_IWL<491> B_IWL<490> B_IWL<489> B_IWL<488> B_IWL<487> B_IWL<486> B_IWL<485> B_IWL<484> B_IWL<483> B_IWL<482> B_IWL<481> B_IWL<480> B_IWL<479> B_IWL<478> B_IWL<477> B_IWL<476> B_IWL<475> B_IWL<474> B_IWL<473> B_IWL<472> B_IWL<471> B_IWL<470> B_IWL<469> B_IWL<468> B_IWL<467> B_IWL<466> B_IWL<465> B_IWL<464> B_IWL<463> B_IWL<462> B_IWL<461> B_IWL<460> B_IWL<459> B_IWL<458> B_IWL<457> B_IWL<456> B_IWL<455> B_IWL<454> B_IWL<453> B_IWL<452> B_IWL<451> B_IWL<450> B_IWL<449> B_IWL<448> B_IWL<575> B_IWL<574> B_IWL<573> B_IWL<572> B_IWL<571> B_IWL<570> B_IWL<569> B_IWL<568> B_IWL<567> B_IWL<566> B_IWL<565> B_IWL<564> B_IWL<563> B_IWL<562> B_IWL<561> B_IWL<560> B_IWL<559> B_IWL<558> B_IWL<557> B_IWL<556> B_IWL<555> B_IWL<554> B_IWL<553> B_IWL<552> B_IWL<551> B_IWL<550> B_IWL<549> B_IWL<548> B_IWL<547> B_IWL<546> B_IWL<545> B_IWL<544> B_IWL<543> B_IWL<542> B_IWL<541> B_IWL<540> B_IWL<539> B_IWL<538> B_IWL<537> B_IWL<536> B_IWL<535> B_IWL<534> B_IWL<533> B_IWL<532> B_IWL<531> B_IWL<530> B_IWL<529> B_IWL<528> B_IWL<527> B_IWL<526> B_IWL<525> B_IWL<524> B_IWL<523> B_IWL<522> B_IWL<521> B_IWL<520> B_IWL<519> B_IWL<518> B_IWL<517> B_IWL<516> B_IWL<515> B_IWL<514> B_IWL<513> B_IWL<512> VDD_CORE VSS / RM_IHPSG13_256x16_c2_2P_COLUMN_pcell_0 +XCOL<7> A_BLC<15> A_BLC<14> A_BLC_TOP<15> A_BLC_TOP<14> A_BLT<15> A_BLT<14> A_BLT_TOP<15> A_BLT_TOP<14> A_IWL<447> A_IWL<446> A_IWL<445> A_IWL<444> A_IWL<443> A_IWL<442> A_IWL<441> A_IWL<440> A_IWL<439> A_IWL<438> A_IWL<437> A_IWL<436> A_IWL<435> A_IWL<434> A_IWL<433> A_IWL<432> A_IWL<431> A_IWL<430> A_IWL<429> A_IWL<428> A_IWL<427> A_IWL<426> A_IWL<425> A_IWL<424> A_IWL<423> A_IWL<422> A_IWL<421> A_IWL<420> A_IWL<419> A_IWL<418> A_IWL<417> A_IWL<416> A_IWL<415> A_IWL<414> A_IWL<413> A_IWL<412> A_IWL<411> A_IWL<410> A_IWL<409> A_IWL<408> A_IWL<407> A_IWL<406> A_IWL<405> A_IWL<404> A_IWL<403> A_IWL<402> A_IWL<401> A_IWL<400> A_IWL<399> A_IWL<398> A_IWL<397> A_IWL<396> A_IWL<395> A_IWL<394> A_IWL<393> A_IWL<392> A_IWL<391> A_IWL<390> A_IWL<389> A_IWL<388> A_IWL<387> A_IWL<386> A_IWL<385> A_IWL<384> A_IWL<511> A_IWL<510> A_IWL<509> A_IWL<508> A_IWL<507> A_IWL<506> A_IWL<505> A_IWL<504> A_IWL<503> A_IWL<502> A_IWL<501> A_IWL<500> A_IWL<499> A_IWL<498> A_IWL<497> A_IWL<496> A_IWL<495> A_IWL<494> A_IWL<493> A_IWL<492> A_IWL<491> A_IWL<490> A_IWL<489> A_IWL<488> A_IWL<487> A_IWL<486> A_IWL<485> A_IWL<484> A_IWL<483> A_IWL<482> A_IWL<481> A_IWL<480> A_IWL<479> A_IWL<478> A_IWL<477> A_IWL<476> A_IWL<475> A_IWL<474> A_IWL<473> A_IWL<472> A_IWL<471> A_IWL<470> A_IWL<469> A_IWL<468> A_IWL<467> A_IWL<466> A_IWL<465> A_IWL<464> A_IWL<463> A_IWL<462> A_IWL<461> A_IWL<460> A_IWL<459> A_IWL<458> A_IWL<457> A_IWL<456> A_IWL<455> A_IWL<454> A_IWL<453> A_IWL<452> A_IWL<451> A_IWL<450> A_IWL<449> A_IWL<448> B_BLC<15> B_BLC<14> B_BLC_TOP<15> B_BLC_TOP<14> B_BLT<15> B_BLT<14> B_BLT_TOP<15> B_BLT_TOP<14> B_IWL<447> B_IWL<446> B_IWL<445> B_IWL<444> B_IWL<443> B_IWL<442> B_IWL<441> B_IWL<440> B_IWL<439> B_IWL<438> B_IWL<437> B_IWL<436> B_IWL<435> B_IWL<434> B_IWL<433> B_IWL<432> B_IWL<431> B_IWL<430> B_IWL<429> B_IWL<428> B_IWL<427> B_IWL<426> B_IWL<425> B_IWL<424> B_IWL<423> B_IWL<422> B_IWL<421> B_IWL<420> B_IWL<419> B_IWL<418> B_IWL<417> B_IWL<416> B_IWL<415> B_IWL<414> B_IWL<413> B_IWL<412> B_IWL<411> B_IWL<410> B_IWL<409> B_IWL<408> B_IWL<407> B_IWL<406> B_IWL<405> B_IWL<404> B_IWL<403> B_IWL<402> B_IWL<401> B_IWL<400> B_IWL<399> B_IWL<398> B_IWL<397> B_IWL<396> B_IWL<395> B_IWL<394> B_IWL<393> B_IWL<392> B_IWL<391> B_IWL<390> B_IWL<389> B_IWL<388> B_IWL<387> B_IWL<386> B_IWL<385> B_IWL<384> B_IWL<511> B_IWL<510> B_IWL<509> B_IWL<508> B_IWL<507> B_IWL<506> B_IWL<505> B_IWL<504> B_IWL<503> B_IWL<502> B_IWL<501> B_IWL<500> B_IWL<499> B_IWL<498> B_IWL<497> B_IWL<496> B_IWL<495> B_IWL<494> B_IWL<493> B_IWL<492> B_IWL<491> B_IWL<490> B_IWL<489> B_IWL<488> B_IWL<487> B_IWL<486> B_IWL<485> B_IWL<484> B_IWL<483> B_IWL<482> B_IWL<481> B_IWL<480> B_IWL<479> B_IWL<478> B_IWL<477> B_IWL<476> B_IWL<475> B_IWL<474> B_IWL<473> B_IWL<472> B_IWL<471> B_IWL<470> B_IWL<469> B_IWL<468> B_IWL<467> B_IWL<466> B_IWL<465> B_IWL<464> B_IWL<463> B_IWL<462> B_IWL<461> B_IWL<460> B_IWL<459> B_IWL<458> B_IWL<457> B_IWL<456> B_IWL<455> B_IWL<454> B_IWL<453> B_IWL<452> B_IWL<451> B_IWL<450> B_IWL<449> B_IWL<448> VDD_CORE VSS / RM_IHPSG13_256x16_c2_2P_COLUMN_pcell_0 +XCOL<6> A_BLC<13> A_BLC<12> A_BLC_TOP<13> A_BLC_TOP<12> A_BLT<13> A_BLT<12> A_BLT_TOP<13> A_BLT_TOP<12> A_IWL<383> A_IWL<382> A_IWL<381> A_IWL<380> A_IWL<379> A_IWL<378> A_IWL<377> A_IWL<376> A_IWL<375> A_IWL<374> A_IWL<373> A_IWL<372> A_IWL<371> A_IWL<370> A_IWL<369> A_IWL<368> A_IWL<367> A_IWL<366> A_IWL<365> A_IWL<364> A_IWL<363> A_IWL<362> A_IWL<361> A_IWL<360> A_IWL<359> A_IWL<358> A_IWL<357> A_IWL<356> A_IWL<355> A_IWL<354> A_IWL<353> A_IWL<352> A_IWL<351> A_IWL<350> A_IWL<349> A_IWL<348> A_IWL<347> A_IWL<346> A_IWL<345> A_IWL<344> A_IWL<343> A_IWL<342> A_IWL<341> A_IWL<340> A_IWL<339> A_IWL<338> A_IWL<337> A_IWL<336> A_IWL<335> A_IWL<334> A_IWL<333> A_IWL<332> A_IWL<331> A_IWL<330> A_IWL<329> A_IWL<328> A_IWL<327> A_IWL<326> A_IWL<325> A_IWL<324> A_IWL<323> A_IWL<322> A_IWL<321> A_IWL<320> A_IWL<447> A_IWL<446> A_IWL<445> A_IWL<444> A_IWL<443> A_IWL<442> A_IWL<441> A_IWL<440> A_IWL<439> A_IWL<438> A_IWL<437> A_IWL<436> A_IWL<435> A_IWL<434> A_IWL<433> A_IWL<432> A_IWL<431> A_IWL<430> A_IWL<429> A_IWL<428> A_IWL<427> A_IWL<426> A_IWL<425> A_IWL<424> A_IWL<423> A_IWL<422> A_IWL<421> A_IWL<420> A_IWL<419> A_IWL<418> A_IWL<417> A_IWL<416> A_IWL<415> A_IWL<414> A_IWL<413> A_IWL<412> A_IWL<411> A_IWL<410> A_IWL<409> A_IWL<408> A_IWL<407> A_IWL<406> A_IWL<405> A_IWL<404> A_IWL<403> A_IWL<402> A_IWL<401> A_IWL<400> A_IWL<399> A_IWL<398> A_IWL<397> A_IWL<396> A_IWL<395> A_IWL<394> A_IWL<393> A_IWL<392> A_IWL<391> A_IWL<390> A_IWL<389> A_IWL<388> A_IWL<387> A_IWL<386> A_IWL<385> A_IWL<384> B_BLC<13> B_BLC<12> B_BLC_TOP<13> B_BLC_TOP<12> B_BLT<13> B_BLT<12> B_BLT_TOP<13> B_BLT_TOP<12> B_IWL<383> B_IWL<382> B_IWL<381> B_IWL<380> B_IWL<379> B_IWL<378> B_IWL<377> B_IWL<376> B_IWL<375> B_IWL<374> B_IWL<373> B_IWL<372> B_IWL<371> B_IWL<370> B_IWL<369> B_IWL<368> B_IWL<367> B_IWL<366> B_IWL<365> B_IWL<364> B_IWL<363> B_IWL<362> B_IWL<361> B_IWL<360> B_IWL<359> B_IWL<358> B_IWL<357> B_IWL<356> B_IWL<355> B_IWL<354> B_IWL<353> B_IWL<352> B_IWL<351> B_IWL<350> B_IWL<349> B_IWL<348> B_IWL<347> B_IWL<346> B_IWL<345> B_IWL<344> B_IWL<343> B_IWL<342> B_IWL<341> B_IWL<340> B_IWL<339> B_IWL<338> B_IWL<337> B_IWL<336> B_IWL<335> B_IWL<334> B_IWL<333> B_IWL<332> B_IWL<331> B_IWL<330> B_IWL<329> B_IWL<328> B_IWL<327> B_IWL<326> B_IWL<325> B_IWL<324> B_IWL<323> B_IWL<322> B_IWL<321> B_IWL<320> B_IWL<447> B_IWL<446> B_IWL<445> B_IWL<444> B_IWL<443> B_IWL<442> B_IWL<441> B_IWL<440> B_IWL<439> B_IWL<438> B_IWL<437> B_IWL<436> B_IWL<435> B_IWL<434> B_IWL<433> B_IWL<432> B_IWL<431> B_IWL<430> B_IWL<429> B_IWL<428> B_IWL<427> B_IWL<426> B_IWL<425> B_IWL<424> B_IWL<423> B_IWL<422> B_IWL<421> B_IWL<420> B_IWL<419> B_IWL<418> B_IWL<417> B_IWL<416> B_IWL<415> B_IWL<414> B_IWL<413> B_IWL<412> B_IWL<411> B_IWL<410> B_IWL<409> B_IWL<408> B_IWL<407> B_IWL<406> B_IWL<405> B_IWL<404> B_IWL<403> B_IWL<402> B_IWL<401> B_IWL<400> B_IWL<399> B_IWL<398> B_IWL<397> B_IWL<396> B_IWL<395> B_IWL<394> B_IWL<393> B_IWL<392> B_IWL<391> B_IWL<390> B_IWL<389> B_IWL<388> B_IWL<387> B_IWL<386> B_IWL<385> B_IWL<384> VDD_CORE VSS / RM_IHPSG13_256x16_c2_2P_COLUMN_pcell_0 +XCOL<5> A_BLC<11> A_BLC<10> A_BLC_TOP<11> A_BLC_TOP<10> A_BLT<11> A_BLT<10> A_BLT_TOP<11> A_BLT_TOP<10> A_IWL<319> A_IWL<318> A_IWL<317> A_IWL<316> A_IWL<315> A_IWL<314> A_IWL<313> A_IWL<312> A_IWL<311> A_IWL<310> A_IWL<309> A_IWL<308> A_IWL<307> A_IWL<306> A_IWL<305> A_IWL<304> A_IWL<303> A_IWL<302> A_IWL<301> A_IWL<300> A_IWL<299> A_IWL<298> A_IWL<297> A_IWL<296> A_IWL<295> A_IWL<294> A_IWL<293> A_IWL<292> A_IWL<291> A_IWL<290> A_IWL<289> A_IWL<288> A_IWL<287> A_IWL<286> A_IWL<285> A_IWL<284> A_IWL<283> A_IWL<282> A_IWL<281> A_IWL<280> A_IWL<279> A_IWL<278> A_IWL<277> A_IWL<276> A_IWL<275> A_IWL<274> A_IWL<273> A_IWL<272> A_IWL<271> A_IWL<270> A_IWL<269> A_IWL<268> A_IWL<267> A_IWL<266> A_IWL<265> A_IWL<264> A_IWL<263> A_IWL<262> A_IWL<261> A_IWL<260> A_IWL<259> A_IWL<258> A_IWL<257> A_IWL<256> A_IWL<383> A_IWL<382> A_IWL<381> A_IWL<380> A_IWL<379> A_IWL<378> A_IWL<377> A_IWL<376> A_IWL<375> A_IWL<374> A_IWL<373> A_IWL<372> A_IWL<371> A_IWL<370> A_IWL<369> A_IWL<368> A_IWL<367> A_IWL<366> A_IWL<365> A_IWL<364> A_IWL<363> A_IWL<362> A_IWL<361> A_IWL<360> A_IWL<359> A_IWL<358> A_IWL<357> A_IWL<356> A_IWL<355> A_IWL<354> A_IWL<353> A_IWL<352> A_IWL<351> A_IWL<350> A_IWL<349> A_IWL<348> A_IWL<347> A_IWL<346> A_IWL<345> A_IWL<344> A_IWL<343> A_IWL<342> A_IWL<341> A_IWL<340> A_IWL<339> A_IWL<338> A_IWL<337> A_IWL<336> A_IWL<335> A_IWL<334> A_IWL<333> A_IWL<332> A_IWL<331> A_IWL<330> A_IWL<329> A_IWL<328> A_IWL<327> A_IWL<326> A_IWL<325> A_IWL<324> A_IWL<323> A_IWL<322> A_IWL<321> A_IWL<320> B_BLC<11> B_BLC<10> B_BLC_TOP<11> B_BLC_TOP<10> B_BLT<11> B_BLT<10> B_BLT_TOP<11> B_BLT_TOP<10> B_IWL<319> B_IWL<318> B_IWL<317> B_IWL<316> B_IWL<315> B_IWL<314> B_IWL<313> B_IWL<312> B_IWL<311> B_IWL<310> B_IWL<309> B_IWL<308> B_IWL<307> B_IWL<306> B_IWL<305> B_IWL<304> B_IWL<303> B_IWL<302> B_IWL<301> B_IWL<300> B_IWL<299> B_IWL<298> B_IWL<297> B_IWL<296> B_IWL<295> B_IWL<294> B_IWL<293> B_IWL<292> B_IWL<291> B_IWL<290> B_IWL<289> B_IWL<288> B_IWL<287> B_IWL<286> B_IWL<285> B_IWL<284> B_IWL<283> B_IWL<282> B_IWL<281> B_IWL<280> B_IWL<279> B_IWL<278> B_IWL<277> B_IWL<276> B_IWL<275> B_IWL<274> B_IWL<273> B_IWL<272> B_IWL<271> B_IWL<270> B_IWL<269> B_IWL<268> B_IWL<267> B_IWL<266> B_IWL<265> B_IWL<264> B_IWL<263> B_IWL<262> B_IWL<261> B_IWL<260> B_IWL<259> B_IWL<258> B_IWL<257> B_IWL<256> B_IWL<383> B_IWL<382> B_IWL<381> B_IWL<380> B_IWL<379> B_IWL<378> B_IWL<377> B_IWL<376> B_IWL<375> B_IWL<374> B_IWL<373> B_IWL<372> B_IWL<371> B_IWL<370> B_IWL<369> B_IWL<368> B_IWL<367> B_IWL<366> B_IWL<365> B_IWL<364> B_IWL<363> B_IWL<362> B_IWL<361> B_IWL<360> B_IWL<359> B_IWL<358> B_IWL<357> B_IWL<356> B_IWL<355> B_IWL<354> B_IWL<353> B_IWL<352> B_IWL<351> B_IWL<350> B_IWL<349> B_IWL<348> B_IWL<347> B_IWL<346> B_IWL<345> B_IWL<344> B_IWL<343> B_IWL<342> B_IWL<341> B_IWL<340> B_IWL<339> B_IWL<338> B_IWL<337> B_IWL<336> B_IWL<335> B_IWL<334> B_IWL<333> B_IWL<332> B_IWL<331> B_IWL<330> B_IWL<329> B_IWL<328> B_IWL<327> B_IWL<326> B_IWL<325> B_IWL<324> B_IWL<323> B_IWL<322> B_IWL<321> B_IWL<320> VDD_CORE VSS / RM_IHPSG13_256x16_c2_2P_COLUMN_pcell_0 +XCOL<4> A_BLC<9> A_BLC<8> A_BLC_TOP<9> A_BLC_TOP<8> A_BLT<9> A_BLT<8> A_BLT_TOP<9> A_BLT_TOP<8> A_IWL<255> A_IWL<254> A_IWL<253> A_IWL<252> A_IWL<251> A_IWL<250> A_IWL<249> A_IWL<248> A_IWL<247> A_IWL<246> A_IWL<245> A_IWL<244> A_IWL<243> A_IWL<242> A_IWL<241> A_IWL<240> A_IWL<239> A_IWL<238> A_IWL<237> A_IWL<236> A_IWL<235> A_IWL<234> A_IWL<233> A_IWL<232> A_IWL<231> A_IWL<230> A_IWL<229> A_IWL<228> A_IWL<227> A_IWL<226> A_IWL<225> A_IWL<224> A_IWL<223> A_IWL<222> A_IWL<221> A_IWL<220> A_IWL<219> A_IWL<218> A_IWL<217> A_IWL<216> A_IWL<215> A_IWL<214> A_IWL<213> A_IWL<212> A_IWL<211> A_IWL<210> A_IWL<209> A_IWL<208> A_IWL<207> A_IWL<206> A_IWL<205> A_IWL<204> A_IWL<203> A_IWL<202> A_IWL<201> A_IWL<200> A_IWL<199> A_IWL<198> A_IWL<197> A_IWL<196> A_IWL<195> A_IWL<194> A_IWL<193> A_IWL<192> A_IWL<319> A_IWL<318> A_IWL<317> A_IWL<316> A_IWL<315> A_IWL<314> A_IWL<313> A_IWL<312> A_IWL<311> A_IWL<310> A_IWL<309> A_IWL<308> A_IWL<307> A_IWL<306> A_IWL<305> A_IWL<304> A_IWL<303> A_IWL<302> A_IWL<301> A_IWL<300> A_IWL<299> A_IWL<298> A_IWL<297> A_IWL<296> A_IWL<295> A_IWL<294> A_IWL<293> A_IWL<292> A_IWL<291> A_IWL<290> A_IWL<289> A_IWL<288> A_IWL<287> A_IWL<286> A_IWL<285> A_IWL<284> A_IWL<283> A_IWL<282> A_IWL<281> A_IWL<280> A_IWL<279> A_IWL<278> A_IWL<277> A_IWL<276> A_IWL<275> A_IWL<274> A_IWL<273> A_IWL<272> A_IWL<271> A_IWL<270> A_IWL<269> A_IWL<268> A_IWL<267> A_IWL<266> A_IWL<265> A_IWL<264> A_IWL<263> A_IWL<262> A_IWL<261> A_IWL<260> A_IWL<259> A_IWL<258> A_IWL<257> A_IWL<256> B_BLC<9> B_BLC<8> B_BLC_TOP<9> B_BLC_TOP<8> B_BLT<9> B_BLT<8> B_BLT_TOP<9> B_BLT_TOP<8> B_IWL<255> B_IWL<254> B_IWL<253> B_IWL<252> B_IWL<251> B_IWL<250> B_IWL<249> B_IWL<248> B_IWL<247> B_IWL<246> B_IWL<245> B_IWL<244> B_IWL<243> B_IWL<242> B_IWL<241> B_IWL<240> B_IWL<239> B_IWL<238> B_IWL<237> B_IWL<236> B_IWL<235> B_IWL<234> B_IWL<233> B_IWL<232> B_IWL<231> B_IWL<230> B_IWL<229> B_IWL<228> B_IWL<227> B_IWL<226> B_IWL<225> B_IWL<224> B_IWL<223> B_IWL<222> B_IWL<221> B_IWL<220> B_IWL<219> B_IWL<218> B_IWL<217> B_IWL<216> B_IWL<215> B_IWL<214> B_IWL<213> B_IWL<212> B_IWL<211> B_IWL<210> B_IWL<209> B_IWL<208> B_IWL<207> B_IWL<206> B_IWL<205> B_IWL<204> B_IWL<203> B_IWL<202> B_IWL<201> B_IWL<200> B_IWL<199> B_IWL<198> B_IWL<197> B_IWL<196> B_IWL<195> B_IWL<194> B_IWL<193> B_IWL<192> B_IWL<319> B_IWL<318> B_IWL<317> B_IWL<316> B_IWL<315> B_IWL<314> B_IWL<313> B_IWL<312> B_IWL<311> B_IWL<310> B_IWL<309> B_IWL<308> B_IWL<307> B_IWL<306> B_IWL<305> B_IWL<304> B_IWL<303> B_IWL<302> B_IWL<301> B_IWL<300> B_IWL<299> B_IWL<298> B_IWL<297> B_IWL<296> B_IWL<295> B_IWL<294> B_IWL<293> B_IWL<292> B_IWL<291> B_IWL<290> B_IWL<289> B_IWL<288> B_IWL<287> B_IWL<286> B_IWL<285> B_IWL<284> B_IWL<283> B_IWL<282> B_IWL<281> B_IWL<280> B_IWL<279> B_IWL<278> B_IWL<277> B_IWL<276> B_IWL<275> B_IWL<274> B_IWL<273> B_IWL<272> B_IWL<271> B_IWL<270> B_IWL<269> B_IWL<268> B_IWL<267> B_IWL<266> B_IWL<265> B_IWL<264> B_IWL<263> B_IWL<262> B_IWL<261> B_IWL<260> B_IWL<259> B_IWL<258> B_IWL<257> B_IWL<256> VDD_CORE VSS / RM_IHPSG13_256x16_c2_2P_COLUMN_pcell_0 +XCOL<3> A_BLC<7> A_BLC<6> A_BLC_TOP<7> A_BLC_TOP<6> A_BLT<7> A_BLT<6> A_BLT_TOP<7> A_BLT_TOP<6> A_IWL<191> A_IWL<190> A_IWL<189> A_IWL<188> A_IWL<187> A_IWL<186> A_IWL<185> A_IWL<184> A_IWL<183> A_IWL<182> A_IWL<181> A_IWL<180> A_IWL<179> A_IWL<178> A_IWL<177> A_IWL<176> A_IWL<175> A_IWL<174> A_IWL<173> A_IWL<172> A_IWL<171> A_IWL<170> A_IWL<169> A_IWL<168> A_IWL<167> A_IWL<166> A_IWL<165> A_IWL<164> A_IWL<163> A_IWL<162> A_IWL<161> A_IWL<160> A_IWL<159> A_IWL<158> A_IWL<157> A_IWL<156> A_IWL<155> A_IWL<154> A_IWL<153> A_IWL<152> A_IWL<151> A_IWL<150> A_IWL<149> A_IWL<148> A_IWL<147> A_IWL<146> A_IWL<145> A_IWL<144> A_IWL<143> A_IWL<142> A_IWL<141> A_IWL<140> A_IWL<139> A_IWL<138> A_IWL<137> A_IWL<136> A_IWL<135> A_IWL<134> A_IWL<133> A_IWL<132> A_IWL<131> A_IWL<130> A_IWL<129> A_IWL<128> A_IWL<255> A_IWL<254> A_IWL<253> A_IWL<252> A_IWL<251> A_IWL<250> A_IWL<249> A_IWL<248> A_IWL<247> A_IWL<246> A_IWL<245> A_IWL<244> A_IWL<243> A_IWL<242> A_IWL<241> A_IWL<240> A_IWL<239> A_IWL<238> A_IWL<237> A_IWL<236> A_IWL<235> A_IWL<234> A_IWL<233> A_IWL<232> A_IWL<231> A_IWL<230> A_IWL<229> A_IWL<228> A_IWL<227> A_IWL<226> A_IWL<225> A_IWL<224> A_IWL<223> A_IWL<222> A_IWL<221> A_IWL<220> A_IWL<219> A_IWL<218> A_IWL<217> A_IWL<216> A_IWL<215> A_IWL<214> A_IWL<213> A_IWL<212> A_IWL<211> A_IWL<210> A_IWL<209> A_IWL<208> A_IWL<207> A_IWL<206> A_IWL<205> A_IWL<204> A_IWL<203> A_IWL<202> A_IWL<201> A_IWL<200> A_IWL<199> A_IWL<198> A_IWL<197> A_IWL<196> A_IWL<195> A_IWL<194> A_IWL<193> A_IWL<192> B_BLC<7> B_BLC<6> B_BLC_TOP<7> B_BLC_TOP<6> B_BLT<7> B_BLT<6> B_BLT_TOP<7> B_BLT_TOP<6> B_IWL<191> B_IWL<190> B_IWL<189> B_IWL<188> B_IWL<187> B_IWL<186> B_IWL<185> B_IWL<184> B_IWL<183> B_IWL<182> B_IWL<181> B_IWL<180> B_IWL<179> B_IWL<178> B_IWL<177> B_IWL<176> B_IWL<175> B_IWL<174> B_IWL<173> B_IWL<172> B_IWL<171> B_IWL<170> B_IWL<169> B_IWL<168> B_IWL<167> B_IWL<166> B_IWL<165> B_IWL<164> B_IWL<163> B_IWL<162> B_IWL<161> B_IWL<160> B_IWL<159> B_IWL<158> B_IWL<157> B_IWL<156> B_IWL<155> B_IWL<154> B_IWL<153> B_IWL<152> B_IWL<151> B_IWL<150> B_IWL<149> B_IWL<148> B_IWL<147> B_IWL<146> B_IWL<145> B_IWL<144> B_IWL<143> B_IWL<142> B_IWL<141> B_IWL<140> B_IWL<139> B_IWL<138> B_IWL<137> B_IWL<136> B_IWL<135> B_IWL<134> B_IWL<133> B_IWL<132> B_IWL<131> B_IWL<130> B_IWL<129> B_IWL<128> B_IWL<255> B_IWL<254> B_IWL<253> B_IWL<252> B_IWL<251> B_IWL<250> B_IWL<249> B_IWL<248> B_IWL<247> B_IWL<246> B_IWL<245> B_IWL<244> B_IWL<243> B_IWL<242> B_IWL<241> B_IWL<240> B_IWL<239> B_IWL<238> B_IWL<237> B_IWL<236> B_IWL<235> B_IWL<234> B_IWL<233> B_IWL<232> B_IWL<231> B_IWL<230> B_IWL<229> B_IWL<228> B_IWL<227> B_IWL<226> B_IWL<225> B_IWL<224> B_IWL<223> B_IWL<222> B_IWL<221> B_IWL<220> B_IWL<219> B_IWL<218> B_IWL<217> B_IWL<216> B_IWL<215> B_IWL<214> B_IWL<213> B_IWL<212> B_IWL<211> B_IWL<210> B_IWL<209> B_IWL<208> B_IWL<207> B_IWL<206> B_IWL<205> B_IWL<204> B_IWL<203> B_IWL<202> B_IWL<201> B_IWL<200> B_IWL<199> B_IWL<198> B_IWL<197> B_IWL<196> B_IWL<195> B_IWL<194> B_IWL<193> B_IWL<192> VDD_CORE VSS / RM_IHPSG13_256x16_c2_2P_COLUMN_pcell_0 +XCOL<2> A_BLC<5> A_BLC<4> A_BLC_TOP<5> A_BLC_TOP<4> A_BLT<5> A_BLT<4> A_BLT_TOP<5> A_BLT_TOP<4> A_IWL<127> A_IWL<126> A_IWL<125> A_IWL<124> A_IWL<123> A_IWL<122> A_IWL<121> A_IWL<120> A_IWL<119> A_IWL<118> A_IWL<117> A_IWL<116> A_IWL<115> A_IWL<114> A_IWL<113> A_IWL<112> A_IWL<111> A_IWL<110> A_IWL<109> A_IWL<108> A_IWL<107> A_IWL<106> A_IWL<105> A_IWL<104> A_IWL<103> A_IWL<102> A_IWL<101> A_IWL<100> A_IWL<99> A_IWL<98> A_IWL<97> A_IWL<96> A_IWL<95> A_IWL<94> A_IWL<93> A_IWL<92> A_IWL<91> A_IWL<90> A_IWL<89> A_IWL<88> A_IWL<87> A_IWL<86> A_IWL<85> A_IWL<84> A_IWL<83> A_IWL<82> A_IWL<81> A_IWL<80> A_IWL<79> A_IWL<78> A_IWL<77> A_IWL<76> A_IWL<75> A_IWL<74> A_IWL<73> A_IWL<72> A_IWL<71> A_IWL<70> A_IWL<69> A_IWL<68> A_IWL<67> A_IWL<66> A_IWL<65> A_IWL<64> A_IWL<191> A_IWL<190> A_IWL<189> A_IWL<188> A_IWL<187> A_IWL<186> A_IWL<185> A_IWL<184> A_IWL<183> A_IWL<182> A_IWL<181> A_IWL<180> A_IWL<179> A_IWL<178> A_IWL<177> A_IWL<176> A_IWL<175> A_IWL<174> A_IWL<173> A_IWL<172> A_IWL<171> A_IWL<170> A_IWL<169> A_IWL<168> A_IWL<167> A_IWL<166> A_IWL<165> A_IWL<164> A_IWL<163> A_IWL<162> A_IWL<161> A_IWL<160> A_IWL<159> A_IWL<158> A_IWL<157> A_IWL<156> A_IWL<155> A_IWL<154> A_IWL<153> A_IWL<152> A_IWL<151> A_IWL<150> A_IWL<149> A_IWL<148> A_IWL<147> A_IWL<146> A_IWL<145> A_IWL<144> A_IWL<143> A_IWL<142> A_IWL<141> A_IWL<140> A_IWL<139> A_IWL<138> A_IWL<137> A_IWL<136> A_IWL<135> A_IWL<134> A_IWL<133> A_IWL<132> A_IWL<131> A_IWL<130> A_IWL<129> A_IWL<128> B_BLC<5> B_BLC<4> B_BLC_TOP<5> B_BLC_TOP<4> B_BLT<5> B_BLT<4> B_BLT_TOP<5> B_BLT_TOP<4> B_IWL<127> B_IWL<126> B_IWL<125> B_IWL<124> B_IWL<123> B_IWL<122> B_IWL<121> B_IWL<120> B_IWL<119> B_IWL<118> B_IWL<117> B_IWL<116> B_IWL<115> B_IWL<114> B_IWL<113> B_IWL<112> B_IWL<111> B_IWL<110> B_IWL<109> B_IWL<108> B_IWL<107> B_IWL<106> B_IWL<105> B_IWL<104> B_IWL<103> B_IWL<102> B_IWL<101> B_IWL<100> B_IWL<99> B_IWL<98> B_IWL<97> B_IWL<96> B_IWL<95> B_IWL<94> B_IWL<93> B_IWL<92> B_IWL<91> B_IWL<90> B_IWL<89> B_IWL<88> B_IWL<87> B_IWL<86> B_IWL<85> B_IWL<84> B_IWL<83> B_IWL<82> B_IWL<81> B_IWL<80> B_IWL<79> B_IWL<78> B_IWL<77> B_IWL<76> B_IWL<75> B_IWL<74> B_IWL<73> B_IWL<72> B_IWL<71> B_IWL<70> B_IWL<69> B_IWL<68> B_IWL<67> B_IWL<66> B_IWL<65> B_IWL<64> B_IWL<191> B_IWL<190> B_IWL<189> B_IWL<188> B_IWL<187> B_IWL<186> B_IWL<185> B_IWL<184> B_IWL<183> B_IWL<182> B_IWL<181> B_IWL<180> B_IWL<179> B_IWL<178> B_IWL<177> B_IWL<176> B_IWL<175> B_IWL<174> B_IWL<173> B_IWL<172> B_IWL<171> B_IWL<170> B_IWL<169> B_IWL<168> B_IWL<167> B_IWL<166> B_IWL<165> B_IWL<164> B_IWL<163> B_IWL<162> B_IWL<161> B_IWL<160> B_IWL<159> B_IWL<158> B_IWL<157> B_IWL<156> B_IWL<155> B_IWL<154> B_IWL<153> B_IWL<152> B_IWL<151> B_IWL<150> B_IWL<149> B_IWL<148> B_IWL<147> B_IWL<146> B_IWL<145> B_IWL<144> B_IWL<143> B_IWL<142> B_IWL<141> B_IWL<140> B_IWL<139> B_IWL<138> B_IWL<137> B_IWL<136> B_IWL<135> B_IWL<134> B_IWL<133> B_IWL<132> B_IWL<131> B_IWL<130> B_IWL<129> B_IWL<128> VDD_CORE VSS / RM_IHPSG13_256x16_c2_2P_COLUMN_pcell_0 +XCOL<1> A_BLC<3> A_BLC<2> A_BLC_TOP<3> A_BLC_TOP<2> A_BLT<3> A_BLT<2> A_BLT_TOP<3> A_BLT_TOP<2> A_IWL<63> A_IWL<62> A_IWL<61> A_IWL<60> A_IWL<59> A_IWL<58> A_IWL<57> A_IWL<56> A_IWL<55> A_IWL<54> A_IWL<53> A_IWL<52> A_IWL<51> A_IWL<50> A_IWL<49> A_IWL<48> A_IWL<47> A_IWL<46> A_IWL<45> A_IWL<44> A_IWL<43> A_IWL<42> A_IWL<41> A_IWL<40> A_IWL<39> A_IWL<38> A_IWL<37> A_IWL<36> A_IWL<35> A_IWL<34> A_IWL<33> A_IWL<32> A_IWL<31> A_IWL<30> A_IWL<29> A_IWL<28> A_IWL<27> A_IWL<26> A_IWL<25> A_IWL<24> A_IWL<23> A_IWL<22> A_IWL<21> A_IWL<20> A_IWL<19> A_IWL<18> A_IWL<17> A_IWL<16> A_IWL<15> A_IWL<14> A_IWL<13> A_IWL<12> A_IWL<11> A_IWL<10> A_IWL<9> A_IWL<8> A_IWL<7> A_IWL<6> A_IWL<5> A_IWL<4> A_IWL<3> A_IWL<2> A_IWL<1> A_IWL<0> A_IWL<127> A_IWL<126> A_IWL<125> A_IWL<124> A_IWL<123> A_IWL<122> A_IWL<121> A_IWL<120> A_IWL<119> A_IWL<118> A_IWL<117> A_IWL<116> A_IWL<115> A_IWL<114> A_IWL<113> A_IWL<112> A_IWL<111> A_IWL<110> A_IWL<109> A_IWL<108> A_IWL<107> A_IWL<106> A_IWL<105> A_IWL<104> A_IWL<103> A_IWL<102> A_IWL<101> A_IWL<100> A_IWL<99> A_IWL<98> A_IWL<97> A_IWL<96> A_IWL<95> A_IWL<94> A_IWL<93> A_IWL<92> A_IWL<91> A_IWL<90> A_IWL<89> A_IWL<88> A_IWL<87> A_IWL<86> A_IWL<85> A_IWL<84> A_IWL<83> A_IWL<82> A_IWL<81> A_IWL<80> A_IWL<79> A_IWL<78> A_IWL<77> A_IWL<76> A_IWL<75> A_IWL<74> A_IWL<73> A_IWL<72> A_IWL<71> A_IWL<70> A_IWL<69> A_IWL<68> A_IWL<67> A_IWL<66> A_IWL<65> A_IWL<64> B_BLC<3> B_BLC<2> B_BLC_TOP<3> B_BLC_TOP<2> B_BLT<3> B_BLT<2> B_BLT_TOP<3> B_BLT_TOP<2> B_IWL<63> B_IWL<62> B_IWL<61> B_IWL<60> B_IWL<59> B_IWL<58> B_IWL<57> B_IWL<56> B_IWL<55> B_IWL<54> B_IWL<53> B_IWL<52> B_IWL<51> B_IWL<50> B_IWL<49> B_IWL<48> B_IWL<47> B_IWL<46> B_IWL<45> B_IWL<44> B_IWL<43> B_IWL<42> B_IWL<41> B_IWL<40> B_IWL<39> B_IWL<38> B_IWL<37> B_IWL<36> B_IWL<35> B_IWL<34> B_IWL<33> B_IWL<32> B_IWL<31> B_IWL<30> B_IWL<29> B_IWL<28> B_IWL<27> B_IWL<26> B_IWL<25> B_IWL<24> B_IWL<23> B_IWL<22> B_IWL<21> B_IWL<20> B_IWL<19> B_IWL<18> B_IWL<17> B_IWL<16> B_IWL<15> B_IWL<14> B_IWL<13> B_IWL<12> B_IWL<11> B_IWL<10> B_IWL<9> B_IWL<8> B_IWL<7> B_IWL<6> B_IWL<5> B_IWL<4> B_IWL<3> B_IWL<2> B_IWL<1> B_IWL<0> B_IWL<127> B_IWL<126> B_IWL<125> B_IWL<124> B_IWL<123> B_IWL<122> B_IWL<121> B_IWL<120> B_IWL<119> B_IWL<118> B_IWL<117> B_IWL<116> B_IWL<115> B_IWL<114> B_IWL<113> B_IWL<112> B_IWL<111> B_IWL<110> B_IWL<109> B_IWL<108> B_IWL<107> B_IWL<106> B_IWL<105> B_IWL<104> B_IWL<103> B_IWL<102> B_IWL<101> B_IWL<100> B_IWL<99> B_IWL<98> B_IWL<97> B_IWL<96> B_IWL<95> B_IWL<94> B_IWL<93> B_IWL<92> B_IWL<91> B_IWL<90> B_IWL<89> B_IWL<88> B_IWL<87> B_IWL<86> B_IWL<85> B_IWL<84> B_IWL<83> B_IWL<82> B_IWL<81> B_IWL<80> B_IWL<79> B_IWL<78> B_IWL<77> B_IWL<76> B_IWL<75> B_IWL<74> B_IWL<73> B_IWL<72> B_IWL<71> B_IWL<70> B_IWL<69> B_IWL<68> B_IWL<67> B_IWL<66> B_IWL<65> B_IWL<64> VDD_CORE VSS / RM_IHPSG13_256x16_c2_2P_COLUMN_pcell_0 +XCOL<0> A_BLC<1> A_BLC<0> A_BLC_TOP<1> A_BLC_TOP<0> A_BLT<1> A_BLT<0> A_BLT_TOP<1> A_BLT_TOP<0> A_WL<63> A_WL<62> A_WL<61> A_WL<60> A_WL<59> A_WL<58> A_WL<57> A_WL<56> A_WL<55> A_WL<54> A_WL<53> A_WL<52> A_WL<51> A_WL<50> A_WL<49> A_WL<48> A_WL<47> A_WL<46> A_WL<45> A_WL<44> A_WL<43> A_WL<42> A_WL<41> A_WL<40> A_WL<39> A_WL<38> A_WL<37> A_WL<36> A_WL<35> A_WL<34> A_WL<33> A_WL<32> A_WL<31> A_WL<30> A_WL<29> A_WL<28> A_WL<27> A_WL<26> A_WL<25> A_WL<24> A_WL<23> A_WL<22> A_WL<21> A_WL<20> A_WL<19> A_WL<18> A_WL<17> A_WL<16> A_WL<15> A_WL<14> A_WL<13> A_WL<12> A_WL<11> A_WL<10> A_WL<9> A_WL<8> A_WL<7> A_WL<6> A_WL<5> A_WL<4> A_WL<3> A_WL<2> A_WL<1> A_WL<0> A_IWL<63> A_IWL<62> A_IWL<61> A_IWL<60> A_IWL<59> A_IWL<58> A_IWL<57> A_IWL<56> A_IWL<55> A_IWL<54> A_IWL<53> A_IWL<52> A_IWL<51> A_IWL<50> A_IWL<49> A_IWL<48> A_IWL<47> A_IWL<46> A_IWL<45> A_IWL<44> A_IWL<43> A_IWL<42> A_IWL<41> A_IWL<40> A_IWL<39> A_IWL<38> A_IWL<37> A_IWL<36> A_IWL<35> A_IWL<34> A_IWL<33> A_IWL<32> A_IWL<31> A_IWL<30> A_IWL<29> A_IWL<28> A_IWL<27> A_IWL<26> A_IWL<25> A_IWL<24> A_IWL<23> A_IWL<22> A_IWL<21> A_IWL<20> A_IWL<19> A_IWL<18> A_IWL<17> A_IWL<16> A_IWL<15> A_IWL<14> A_IWL<13> A_IWL<12> A_IWL<11> A_IWL<10> A_IWL<9> A_IWL<8> A_IWL<7> A_IWL<6> A_IWL<5> A_IWL<4> A_IWL<3> A_IWL<2> A_IWL<1> A_IWL<0> B_BLC<1> B_BLC<0> B_BLC_TOP<1> B_BLC_TOP<0> B_BLT<1> B_BLT<0> B_BLT_TOP<1> B_BLT_TOP<0> B_WL<63> B_WL<62> B_WL<61> B_WL<60> B_WL<59> B_WL<58> B_WL<57> B_WL<56> B_WL<55> B_WL<54> B_WL<53> B_WL<52> B_WL<51> B_WL<50> B_WL<49> B_WL<48> B_WL<47> B_WL<46> B_WL<45> B_WL<44> B_WL<43> B_WL<42> B_WL<41> B_WL<40> B_WL<39> B_WL<38> B_WL<37> B_WL<36> B_WL<35> B_WL<34> B_WL<33> B_WL<32> B_WL<31> B_WL<30> B_WL<29> B_WL<28> B_WL<27> B_WL<26> B_WL<25> B_WL<24> B_WL<23> B_WL<22> B_WL<21> B_WL<20> B_WL<19> B_WL<18> B_WL<17> B_WL<16> B_WL<15> B_WL<14> B_WL<13> B_WL<12> B_WL<11> B_WL<10> B_WL<9> B_WL<8> B_WL<7> B_WL<6> B_WL<5> B_WL<4> B_WL<3> B_WL<2> B_WL<1> B_WL<0> B_IWL<63> B_IWL<62> B_IWL<61> B_IWL<60> B_IWL<59> B_IWL<58> B_IWL<57> B_IWL<56> B_IWL<55> B_IWL<54> B_IWL<53> B_IWL<52> B_IWL<51> B_IWL<50> B_IWL<49> B_IWL<48> B_IWL<47> B_IWL<46> B_IWL<45> B_IWL<44> B_IWL<43> B_IWL<42> B_IWL<41> B_IWL<40> B_IWL<39> B_IWL<38> B_IWL<37> B_IWL<36> B_IWL<35> B_IWL<34> B_IWL<33> B_IWL<32> B_IWL<31> B_IWL<30> B_IWL<29> B_IWL<28> B_IWL<27> B_IWL<26> B_IWL<25> B_IWL<24> B_IWL<23> B_IWL<22> B_IWL<21> B_IWL<20> B_IWL<19> B_IWL<18> B_IWL<17> B_IWL<16> B_IWL<15> B_IWL<14> B_IWL<13> B_IWL<12> B_IWL<11> B_IWL<10> B_IWL<9> B_IWL<8> B_IWL<7> B_IWL<6> B_IWL<5> B_IWL<4> B_IWL<3> B_IWL<2> B_IWL<1> B_IWL<0> VDD_CORE VSS / RM_IHPSG13_256x16_c2_2P_COLUMN_pcell_0 +.ENDS + + + + +.SUBCKT RM_IHPSG13_256x16_c2_2P_DLY_pcell_2 A Z VDD VSS + XIDL D<9> Z VDD VSS / RSC_IHPSG13_CDLYX1 + XIDM<9> D<8> D<9> VDD VSS / RSC_IHPSG13_CDLYX1_DUMMY + XIDM<8> D<7> D<8> VDD VSS / RSC_IHPSG13_CDLYX1_DUMMY + XIDM<7> D<6> D<7> VDD VSS / RSC_IHPSG13_CDLYX1_DUMMY + XIDM<6> D<5> D<6> VDD VSS / RSC_IHPSG13_CDLYX1_DUMMY + XIDM<5> D<4> D<5> VDD VSS / RSC_IHPSG13_CDLYX1_DUMMY + XIDM<4> D<3> D<4> VDD VSS / RSC_IHPSG13_CDLYX1_DUMMY + XIDM<3> D<2> D<3> VDD VSS / RSC_IHPSG13_CDLYX1_DUMMY + XIDM<2> D<1> D<2> VDD VSS / RSC_IHPSG13_CDLYX1_DUMMY + XIDM<1> A D<1> VDD VSS / RSC_IHPSG13_CDLYX1_DUMMY +.ENDS + + +.SUBCKT RM_IHPSG13_256x16_c2_2P_DLY_pcell_3 A Z VDD VSS + XIDM<10> D<9> Z VDD VSS / RSC_IHPSG13_CDLYX1_DUMMY + XIDM<9> D<8> D<9> VDD VSS / RSC_IHPSG13_CDLYX1_DUMMY + XIDM<8> D<7> D<8> VDD VSS / RSC_IHPSG13_CDLYX1_DUMMY + XIDM<7> D<6> D<7> VDD VSS / RSC_IHPSG13_CDLYX1_DUMMY + XIDM<6> D<5> D<6> VDD VSS / RSC_IHPSG13_CDLYX1_DUMMY + XIDM<5> D<4> D<5> VDD VSS / RSC_IHPSG13_CDLYX1_DUMMY + XIDM<4> D<3> D<4> VDD VSS / RSC_IHPSG13_CDLYX1_DUMMY + XIDM<3> D<2> D<3> VDD VSS / RSC_IHPSG13_CDLYX1_DUMMY + XIDM<2> D<1> D<2> VDD VSS / RSC_IHPSG13_CDLYX1_DUMMY + XIDM<1> A D<1> VDD VSS / RSC_IHPSG13_CDLYX1_DUMMY +.ENDS + + + +.SUBCKT RM_IHPSG13_2P_256x16_c2_bm_bist A_ADDR<7> A_ADDR<6> A_ADDR<5> A_ADDR<4> A_ADDR<3> A_ADDR<2> A_ADDR<1> A_ADDR<0> A_BIST_ADDR<7> A_BIST_ADDR<6> A_BIST_ADDR<5> A_BIST_ADDR<4> A_BIST_ADDR<3> A_BIST_ADDR<2> A_BIST_ADDR<1> A_BIST_ADDR<0> A_BIST_BM<15> A_BIST_BM<14> A_BIST_BM<13> A_BIST_BM<12> A_BIST_BM<11> A_BIST_BM<10> A_BIST_BM<9> A_BIST_BM<8> A_BIST_BM<7> A_BIST_BM<6> A_BIST_BM<5> A_BIST_BM<4> A_BIST_BM<3> A_BIST_BM<2> A_BIST_BM<1> A_BIST_BM<0> A_BIST_CLK A_BIST_DIN<15> A_BIST_DIN<14> A_BIST_DIN<13> A_BIST_DIN<12> A_BIST_DIN<11> A_BIST_DIN<10> A_BIST_DIN<9> A_BIST_DIN<8> A_BIST_DIN<7> A_BIST_DIN<6> A_BIST_DIN<5> A_BIST_DIN<4> A_BIST_DIN<3> A_BIST_DIN<2> A_BIST_DIN<1> A_BIST_DIN<0> A_BIST_EN A_BIST_MEN A_BIST_REN A_BIST_WEN A_BM<15> A_BM<14> A_BM<13> A_BM<12> A_BM<11> A_BM<10> A_BM<9> A_BM<8> A_BM<7> A_BM<6> A_BM<5> A_BM<4> A_BM<3> A_BM<2> A_BM<1> A_BM<0> A_CLK A_DIN<15> A_DIN<14> A_DIN<13> A_DIN<12> A_DIN<11> A_DIN<10> A_DIN<9> A_DIN<8> A_DIN<7> A_DIN<6> A_DIN<5> A_DIN<4> A_DIN<3> A_DIN<2> A_DIN<1> A_DIN<0> A_DLY A_DOUT<15> A_DOUT<14> A_DOUT<13> A_DOUT<12> A_DOUT<11> A_DOUT<10> A_DOUT<9> A_DOUT<8> A_DOUT<7> A_DOUT<6> A_DOUT<5> A_DOUT<4> A_DOUT<3> A_DOUT<2> A_DOUT<1> A_DOUT<0> A_MEN A_REN A_WEN B_ADDR<7> B_ADDR<6> B_ADDR<5> B_ADDR<4> B_ADDR<3> B_ADDR<2> B_ADDR<1> B_ADDR<0> B_BIST_ADDR<7> B_BIST_ADDR<6> B_BIST_ADDR<5> B_BIST_ADDR<4> B_BIST_ADDR<3> B_BIST_ADDR<2> B_BIST_ADDR<1> B_BIST_ADDR<0> B_BIST_BM<15> B_BIST_BM<14> B_BIST_BM<13> B_BIST_BM<12> B_BIST_BM<11> B_BIST_BM<10> B_BIST_BM<9> B_BIST_BM<8> B_BIST_BM<7> B_BIST_BM<6> B_BIST_BM<5> B_BIST_BM<4> B_BIST_BM<3> B_BIST_BM<2> B_BIST_BM<1> B_BIST_BM<0> B_BIST_CLK B_BIST_DIN<15> B_BIST_DIN<14> B_BIST_DIN<13> B_BIST_DIN<12> B_BIST_DIN<11> B_BIST_DIN<10> B_BIST_DIN<9> B_BIST_DIN<8> B_BIST_DIN<7> B_BIST_DIN<6> B_BIST_DIN<5> B_BIST_DIN<4> B_BIST_DIN<3> B_BIST_DIN<2> B_BIST_DIN<1> B_BIST_DIN<0> B_BIST_EN B_BIST_MEN B_BIST_REN B_BIST_WEN B_BM<15> B_BM<14> B_BM<13> B_BM<12> B_BM<11> B_BM<10> B_BM<9> B_BM<8> B_BM<7> B_BM<6> B_BM<5> B_BM<4> B_BM<3> B_BM<2> B_BM<1> B_BM<0> B_CLK B_DIN<15> B_DIN<14> B_DIN<13> B_DIN<12> B_DIN<11> B_DIN<10> B_DIN<9> B_DIN<8> B_DIN<7> B_DIN<6> B_DIN<5> B_DIN<4> B_DIN<3> B_DIN<2> B_DIN<1> B_DIN<0> B_DLY B_DOUT<15> B_DOUT<14> B_DOUT<13> B_DOUT<12> B_DOUT<11> B_DOUT<10> B_DOUT<9> B_DOUT<8> B_DOUT<7> B_DOUT<6> B_DOUT<5> B_DOUT<4> B_DOUT<3> B_DOUT<2> B_DOUT<1> B_DOUT<0> B_MEN B_REN B_WEN VDD! VDDARRAY! VSS! + + +XRAM<1> a_blc_r<31> a_blc_r<30> a_blc_r<29> a_blc_r<28> a_blc_r<27> a_blc_r<26> a_blc_r<25> a_blc_r<24> a_blc_r<23> a_blc_r<22> a_blc_r<21> a_blc_r<20> a_blc_r<19> a_blc_r<18> a_blc_r<17> a_blc_r<16> a_blc_r<15> a_blc_r<14> a_blc_r<13> a_blc_r<12> a_blc_r<11> a_blc_r<10> a_blc_r<9> a_blc_r<8> a_blc_r<7> a_blc_r<6> a_blc_r<5> a_blc_r<4> a_blc_r<3> a_blc_r<2> a_blc_r<1> a_blc_r<0> a_blt_r<31> a_blt_r<30> a_blt_r<29> a_blt_r<28> a_blt_r<27> a_blt_r<26> a_blt_r<25> a_blt_r<24> a_blt_r<23> a_blt_r<22> a_blt_r<21> a_blt_r<20> a_blt_r<19> a_blt_r<18> a_blt_r<17> a_blt_r<16> a_blt_r<15> a_blt_r<14> a_blt_r<13> a_blt_r<12> a_blt_r<11> a_blt_r<10> a_blt_r<9> a_blt_r<8> a_blt_r<7> a_blt_r<6> a_blt_r<5> a_blt_r<4> a_blt_r<3> a_blt_r<2> a_blt_r<1> a_blt_r<0> a_wl_r<63> a_wl_r<62> a_wl_r<61> a_wl_r<60> a_wl_r<59> a_wl_r<58> a_wl_r<57> a_wl_r<56> a_wl_r<55> a_wl_r<54> a_wl_r<53> a_wl_r<52> a_wl_r<51> a_wl_r<50> a_wl_r<49> a_wl_r<48> a_wl_r<47> a_wl_r<46> a_wl_r<45> a_wl_r<44> a_wl_r<43> a_wl_r<42> a_wl_r<41> a_wl_r<40> a_wl_r<39> a_wl_r<38> a_wl_r<37> a_wl_r<36> a_wl_r<35> a_wl_r<34> a_wl_r<33> a_wl_r<32> a_wl_r<31> a_wl_r<30> a_wl_r<29> a_wl_r<28> a_wl_r<27> a_wl_r<26> a_wl_r<25> a_wl_r<24> a_wl_r<23> a_wl_r<22> a_wl_r<21> a_wl_r<20> a_wl_r<19> a_wl_r<18> a_wl_r<17> a_wl_r<16> a_wl_r<15> a_wl_r<14> a_wl_r<13> a_wl_r<12> a_wl_r<11> a_wl_r<10> a_wl_r<9> a_wl_r<8> a_wl_r<7> a_wl_r<6> a_wl_r<5> a_wl_r<4> a_wl_r<3> a_wl_r<2> a_wl_r<1> a_wl_r<0> b_blc_r<31> b_blc_r<30> b_blc_r<29> b_blc_r<28> b_blc_r<27> b_blc_r<26> b_blc_r<25> b_blc_r<24> b_blc_r<23> b_blc_r<22> b_blc_r<21> b_blc_r<20> b_blc_r<19> b_blc_r<18> b_blc_r<17> b_blc_r<16> b_blc_r<15> b_blc_r<14> b_blc_r<13> b_blc_r<12> b_blc_r<11> b_blc_r<10> b_blc_r<9> b_blc_r<8> b_blc_r<7> b_blc_r<6> b_blc_r<5> b_blc_r<4> b_blc_r<3> b_blc_r<2> b_blc_r<1> b_blc_r<0> b_blt_r<31> b_blt_r<30> b_blt_r<29> b_blt_r<28> b_blt_r<27> b_blt_r<26> b_blt_r<25> b_blt_r<24> b_blt_r<23> b_blt_r<22> b_blt_r<21> b_blt_r<20> b_blt_r<19> b_blt_r<18> b_blt_r<17> b_blt_r<16> b_blt_r<15> b_blt_r<14> b_blt_r<13> b_blt_r<12> b_blt_r<11> b_blt_r<10> b_blt_r<9> b_blt_r<8> b_blt_r<7> b_blt_r<6> b_blt_r<5> b_blt_r<4> b_blt_r<3> b_blt_r<2> b_blt_r<1> b_blt_r<0> b_wl_r<63> b_wl_r<62> b_wl_r<61> b_wl_r<60> b_wl_r<59> b_wl_r<58> b_wl_r<57> b_wl_r<56> b_wl_r<55> b_wl_r<54> b_wl_r<53> b_wl_r<52> b_wl_r<51> b_wl_r<50> b_wl_r<49> b_wl_r<48> b_wl_r<47> b_wl_r<46> b_wl_r<45> b_wl_r<44> b_wl_r<43> b_wl_r<42> b_wl_r<41> b_wl_r<40> b_wl_r<39> b_wl_r<38> b_wl_r<37> b_wl_r<36> b_wl_r<35> b_wl_r<34> b_wl_r<33> b_wl_r<32> b_wl_r<31> b_wl_r<30> b_wl_r<29> b_wl_r<28> b_wl_r<27> b_wl_r<26> b_wl_r<25> b_wl_r<24> b_wl_r<23> b_wl_r<22> b_wl_r<21> b_wl_r<20> b_wl_r<19> b_wl_r<18> b_wl_r<17> b_wl_r<16> b_wl_r<15> b_wl_r<14> b_wl_r<13> b_wl_r<12> b_wl_r<11> b_wl_r<10> b_wl_r<9> b_wl_r<8> b_wl_r<7> b_wl_r<6> b_wl_r<5> b_wl_r<4> b_wl_r<3> b_wl_r<2> b_wl_r<1> b_wl_r<0> VDDARRAY! VSS! / RM_IHPSG13_256x16_c2_2P_MATRIX_pcell_1 +XRAM<0> a_blc_l<31> a_blc_l<30> a_blc_l<29> a_blc_l<28> a_blc_l<27> a_blc_l<26> a_blc_l<25> a_blc_l<24> a_blc_l<23> a_blc_l<22> a_blc_l<21> a_blc_l<20> a_blc_l<19> a_blc_l<18> a_blc_l<17> a_blc_l<16> a_blc_l<15> a_blc_l<14> a_blc_l<13> a_blc_l<12> a_blc_l<11> a_blc_l<10> a_blc_l<9> a_blc_l<8> a_blc_l<7> a_blc_l<6> a_blc_l<5> a_blc_l<4> a_blc_l<3> a_blc_l<2> a_blc_l<1> a_blc_l<0> a_blt_l<31> a_blt_l<30> a_blt_l<29> a_blt_l<28> a_blt_l<27> a_blt_l<26> a_blt_l<25> a_blt_l<24> a_blt_l<23> a_blt_l<22> a_blt_l<21> a_blt_l<20> a_blt_l<19> a_blt_l<18> a_blt_l<17> a_blt_l<16> a_blt_l<15> a_blt_l<14> a_blt_l<13> a_blt_l<12> a_blt_l<11> a_blt_l<10> a_blt_l<9> a_blt_l<8> a_blt_l<7> a_blt_l<6> a_blt_l<5> a_blt_l<4> a_blt_l<3> a_blt_l<2> a_blt_l<1> a_blt_l<0> a_wl_l<63> a_wl_l<62> a_wl_l<61> a_wl_l<60> a_wl_l<59> a_wl_l<58> a_wl_l<57> a_wl_l<56> a_wl_l<55> a_wl_l<54> a_wl_l<53> a_wl_l<52> a_wl_l<51> a_wl_l<50> a_wl_l<49> a_wl_l<48> a_wl_l<47> a_wl_l<46> a_wl_l<45> a_wl_l<44> a_wl_l<43> a_wl_l<42> a_wl_l<41> a_wl_l<40> a_wl_l<39> a_wl_l<38> a_wl_l<37> a_wl_l<36> a_wl_l<35> a_wl_l<34> a_wl_l<33> a_wl_l<32> a_wl_l<31> a_wl_l<30> a_wl_l<29> a_wl_l<28> a_wl_l<27> a_wl_l<26> a_wl_l<25> a_wl_l<24> a_wl_l<23> a_wl_l<22> a_wl_l<21> a_wl_l<20> a_wl_l<19> a_wl_l<18> a_wl_l<17> a_wl_l<16> a_wl_l<15> a_wl_l<14> a_wl_l<13> a_wl_l<12> a_wl_l<11> a_wl_l<10> a_wl_l<9> a_wl_l<8> a_wl_l<7> a_wl_l<6> a_wl_l<5> a_wl_l<4> a_wl_l<3> a_wl_l<2> a_wl_l<1> a_wl_l<0> b_blc_l<31> b_blc_l<30> b_blc_l<29> b_blc_l<28> b_blc_l<27> b_blc_l<26> b_blc_l<25> b_blc_l<24> b_blc_l<23> b_blc_l<22> b_blc_l<21> b_blc_l<20> b_blc_l<19> b_blc_l<18> b_blc_l<17> b_blc_l<16> b_blc_l<15> b_blc_l<14> b_blc_l<13> b_blc_l<12> b_blc_l<11> b_blc_l<10> b_blc_l<9> b_blc_l<8> b_blc_l<7> b_blc_l<6> b_blc_l<5> b_blc_l<4> b_blc_l<3> b_blc_l<2> b_blc_l<1> b_blc_l<0> b_blt_l<31> b_blt_l<30> b_blt_l<29> b_blt_l<28> b_blt_l<27> b_blt_l<26> b_blt_l<25> b_blt_l<24> b_blt_l<23> b_blt_l<22> b_blt_l<21> b_blt_l<20> b_blt_l<19> b_blt_l<18> b_blt_l<17> b_blt_l<16> b_blt_l<15> b_blt_l<14> b_blt_l<13> b_blt_l<12> b_blt_l<11> b_blt_l<10> b_blt_l<9> b_blt_l<8> b_blt_l<7> b_blt_l<6> b_blt_l<5> b_blt_l<4> b_blt_l<3> b_blt_l<2> b_blt_l<1> b_blt_l<0> b_wl_l<63> b_wl_l<62> b_wl_l<61> b_wl_l<60> b_wl_l<59> b_wl_l<58> b_wl_l<57> b_wl_l<56> b_wl_l<55> b_wl_l<54> b_wl_l<53> b_wl_l<52> b_wl_l<51> b_wl_l<50> b_wl_l<49> b_wl_l<48> b_wl_l<47> b_wl_l<46> b_wl_l<45> b_wl_l<44> b_wl_l<43> b_wl_l<42> b_wl_l<41> b_wl_l<40> b_wl_l<39> b_wl_l<38> b_wl_l<37> b_wl_l<36> b_wl_l<35> b_wl_l<34> b_wl_l<33> b_wl_l<32> b_wl_l<31> b_wl_l<30> b_wl_l<29> b_wl_l<28> b_wl_l<27> b_wl_l<26> b_wl_l<25> b_wl_l<24> b_wl_l<23> b_wl_l<22> b_wl_l<21> b_wl_l<20> b_wl_l<19> b_wl_l<18> b_wl_l<17> b_wl_l<16> b_wl_l<15> b_wl_l<14> b_wl_l<13> b_wl_l<12> b_wl_l<11> b_wl_l<10> b_wl_l<9> b_wl_l<8> b_wl_l<7> b_wl_l<6> b_wl_l<5> b_wl_l<4> b_wl_l<3> b_wl_l<2> b_wl_l<1> b_wl_l<0> VDDARRAY! VSS! / RM_IHPSG13_256x16_c2_2P_MATRIX_pcell_1 + + +XB_COLDRV<1> b_addr_col<1> b_addr_col<0> b_addr_col_r<1> b_addr_col_r<0> b_addr_dec<7> b_addr_dec<6> b_addr_dec<5> b_addr_dec<4> b_addr_dec<3> b_addr_dec<2> b_addr_dec<1> b_addr_dec<0> b_addr_dec_r<7> b_addr_dec_r<6> b_addr_dec_r<5> b_addr_dec_r<4> b_addr_dec_r<3> b_addr_dec_r<2> b_addr_dec_r<1> b_addr_dec_r<0> b_dclk b_dclk_p_r<0> b_rclk b_rclk_p_r<0> b_wclk b_wclk_p_r<0> VDD! VSS! / RM_IHPSG13_256x16_c2_2P_COLDRV13X8 +XB_COLDRV<0> b_addr_col<1> b_addr_col<0> b_addr_col_l<1> b_addr_col_l<0> b_addr_dec<7> b_addr_dec<6> b_addr_dec<5> b_addr_dec<4> b_addr_dec<3> b_addr_dec<2> b_addr_dec<1> b_addr_dec<0> b_addr_dec_l<7> b_addr_dec_l<6> b_addr_dec_l<5> b_addr_dec_l<4> b_addr_dec_l<3> b_addr_dec_l<2> b_addr_dec_l<1> b_addr_dec_l<0> b_dclk b_dclk_p_l<0> b_rclk b_rclk_p_l<0> b_wclk b_wclk_p_l<0> VDD! VSS! / RM_IHPSG13_256x16_c2_2P_COLDRV13X8 +XA_COLDRV<1> a_addr_col<1> a_addr_col<0> a_addr_col_r<1> a_addr_col_r<0> a_addr_dec<7> a_addr_dec<6> a_addr_dec<5> a_addr_dec<4> a_addr_dec<3> a_addr_dec<2> a_addr_dec<1> a_addr_dec<0> a_addr_dec_r<7> a_addr_dec_r<6> a_addr_dec_r<5> a_addr_dec_r<4> a_addr_dec_r<3> a_addr_dec_r<2> a_addr_dec_r<1> a_addr_dec_r<0> a_dclk a_dclk_p_r<0> a_rclk a_rclk_p_r<0> a_wclk a_wclk_p_r<0> VDD! VSS! / RM_IHPSG13_256x16_c2_2P_COLDRV13X8 +XA_COLDRV<0> a_addr_col<1> a_addr_col<0> a_addr_col_l<1> a_addr_col_l<0> a_addr_dec<7> a_addr_dec<6> a_addr_dec<5> a_addr_dec<4> a_addr_dec<3> a_addr_dec<2> a_addr_dec<1> a_addr_dec<0> a_addr_dec_l<7> a_addr_dec_l<6> a_addr_dec_l<5> a_addr_dec_l<4> a_addr_dec_l<3> a_addr_dec_l<2> a_addr_dec_l<1> a_addr_dec_l<0> a_dclk a_dclk_p_l<0> a_rclk a_rclk_p_l<0> a_wclk a_wclk_p_l<0> VDD! VSS! / RM_IHPSG13_256x16_c2_2P_COLDRV13X8 + + +XB_WLDRV<7> b_wi<63> b_wi<62> b_wi<61> b_wi<60> b_wi<59> b_wi<58> b_wi<57> b_wi<56> b_wi<55> b_wi<54> b_wi<53> b_wi<52> b_wi<51> b_wi<50> b_wi<49> b_wi<48> b_wl_r<63> b_wl_r<62> b_wl_r<61> b_wl_r<60> b_wl_r<59> b_wl_r<58> b_wl_r<57> b_wl_r<56> b_wl_r<55> b_wl_r<54> b_wl_r<53> b_wl_r<52> b_wl_r<51> b_wl_r<50> b_wl_r<49> b_wl_r<48> VDD! VSS! / RM_IHPSG13_256x16_c2_2P_WLDRV16X8 +XB_WLDRV<6> b_wi<47> b_wi<46> b_wi<45> b_wi<44> b_wi<43> b_wi<42> b_wi<41> b_wi<40> b_wi<39> b_wi<38> b_wi<37> b_wi<36> b_wi<35> b_wi<34> b_wi<33> b_wi<32> b_wl_r<47> b_wl_r<46> b_wl_r<45> b_wl_r<44> b_wl_r<43> b_wl_r<42> b_wl_r<41> b_wl_r<40> b_wl_r<39> b_wl_r<38> b_wl_r<37> b_wl_r<36> b_wl_r<35> b_wl_r<34> b_wl_r<33> b_wl_r<32> VDD! VSS! / RM_IHPSG13_256x16_c2_2P_WLDRV16X8 +XB_WLDRV<5> b_wi<31> b_wi<30> b_wi<29> b_wi<28> b_wi<27> b_wi<26> b_wi<25> b_wi<24> b_wi<23> b_wi<22> b_wi<21> b_wi<20> b_wi<19> b_wi<18> b_wi<17> b_wi<16> b_wl_r<31> b_wl_r<30> b_wl_r<29> b_wl_r<28> b_wl_r<27> b_wl_r<26> b_wl_r<25> b_wl_r<24> b_wl_r<23> b_wl_r<22> b_wl_r<21> b_wl_r<20> b_wl_r<19> b_wl_r<18> b_wl_r<17> b_wl_r<16> VDD! VSS! / RM_IHPSG13_256x16_c2_2P_WLDRV16X8 +XB_WLDRV<4> b_wi<15> b_wi<14> b_wi<13> b_wi<12> b_wi<11> b_wi<10> b_wi<9> b_wi<8> b_wi<7> b_wi<6> b_wi<5> b_wi<4> b_wi<3> b_wi<2> b_wi<1> b_wi<0> b_wl_r<15> b_wl_r<14> b_wl_r<13> b_wl_r<12> b_wl_r<11> b_wl_r<10> b_wl_r<9> b_wl_r<8> b_wl_r<7> b_wl_r<6> b_wl_r<5> b_wl_r<4> b_wl_r<3> b_wl_r<2> b_wl_r<1> b_wl_r<0> VDD! VSS! / RM_IHPSG13_256x16_c2_2P_WLDRV16X8 +XB_WLDRV<3> b_wi<63> b_wi<62> b_wi<61> b_wi<60> b_wi<59> b_wi<58> b_wi<57> b_wi<56> b_wi<55> b_wi<54> b_wi<53> b_wi<52> b_wi<51> b_wi<50> b_wi<49> b_wi<48> b_wl_l<63> b_wl_l<62> b_wl_l<61> b_wl_l<60> b_wl_l<59> b_wl_l<58> b_wl_l<57> b_wl_l<56> b_wl_l<55> b_wl_l<54> b_wl_l<53> b_wl_l<52> b_wl_l<51> b_wl_l<50> b_wl_l<49> b_wl_l<48> VDD! VSS! / RM_IHPSG13_256x16_c2_2P_WLDRV16X8 +XB_WLDRV<2> b_wi<47> b_wi<46> b_wi<45> b_wi<44> b_wi<43> b_wi<42> b_wi<41> b_wi<40> b_wi<39> b_wi<38> b_wi<37> b_wi<36> b_wi<35> b_wi<34> b_wi<33> b_wi<32> b_wl_l<47> b_wl_l<46> b_wl_l<45> b_wl_l<44> b_wl_l<43> b_wl_l<42> b_wl_l<41> b_wl_l<40> b_wl_l<39> b_wl_l<38> b_wl_l<37> b_wl_l<36> b_wl_l<35> b_wl_l<34> b_wl_l<33> b_wl_l<32> VDD! VSS! / RM_IHPSG13_256x16_c2_2P_WLDRV16X8 +XB_WLDRV<1> b_wi<31> b_wi<30> b_wi<29> b_wi<28> b_wi<27> b_wi<26> b_wi<25> b_wi<24> b_wi<23> b_wi<22> b_wi<21> b_wi<20> b_wi<19> b_wi<18> b_wi<17> b_wi<16> b_wl_l<31> b_wl_l<30> b_wl_l<29> b_wl_l<28> b_wl_l<27> b_wl_l<26> b_wl_l<25> b_wl_l<24> b_wl_l<23> b_wl_l<22> b_wl_l<21> b_wl_l<20> b_wl_l<19> b_wl_l<18> b_wl_l<17> b_wl_l<16> VDD! VSS! / RM_IHPSG13_256x16_c2_2P_WLDRV16X8 +XB_WLDRV<0> b_wi<15> b_wi<14> b_wi<13> b_wi<12> b_wi<11> b_wi<10> b_wi<9> b_wi<8> b_wi<7> b_wi<6> b_wi<5> b_wi<4> b_wi<3> b_wi<2> b_wi<1> b_wi<0> b_wl_l<15> b_wl_l<14> b_wl_l<13> b_wl_l<12> b_wl_l<11> b_wl_l<10> b_wl_l<9> b_wl_l<8> b_wl_l<7> b_wl_l<6> b_wl_l<5> b_wl_l<4> b_wl_l<3> b_wl_l<2> b_wl_l<1> b_wl_l<0> VDD! VSS! / RM_IHPSG13_256x16_c2_2P_WLDRV16X8 +XA_WLDRV<7> a_wi<63> a_wi<62> a_wi<61> a_wi<60> a_wi<59> a_wi<58> a_wi<57> a_wi<56> a_wi<55> a_wi<54> a_wi<53> a_wi<52> a_wi<51> a_wi<50> a_wi<49> a_wi<48> a_wl_r<63> a_wl_r<62> a_wl_r<61> a_wl_r<60> a_wl_r<59> a_wl_r<58> a_wl_r<57> a_wl_r<56> a_wl_r<55> a_wl_r<54> a_wl_r<53> a_wl_r<52> a_wl_r<51> a_wl_r<50> a_wl_r<49> a_wl_r<48> VDD! VSS! / RM_IHPSG13_256x16_c2_2P_WLDRV16X8 +XA_WLDRV<6> a_wi<47> a_wi<46> a_wi<45> a_wi<44> a_wi<43> a_wi<42> a_wi<41> a_wi<40> a_wi<39> a_wi<38> a_wi<37> a_wi<36> a_wi<35> a_wi<34> a_wi<33> a_wi<32> a_wl_r<47> a_wl_r<46> a_wl_r<45> a_wl_r<44> a_wl_r<43> a_wl_r<42> a_wl_r<41> a_wl_r<40> a_wl_r<39> a_wl_r<38> a_wl_r<37> a_wl_r<36> a_wl_r<35> a_wl_r<34> a_wl_r<33> a_wl_r<32> VDD! VSS! / RM_IHPSG13_256x16_c2_2P_WLDRV16X8 +XA_WLDRV<5> a_wi<31> a_wi<30> a_wi<29> a_wi<28> a_wi<27> a_wi<26> a_wi<25> a_wi<24> a_wi<23> a_wi<22> a_wi<21> a_wi<20> a_wi<19> a_wi<18> a_wi<17> a_wi<16> a_wl_r<31> a_wl_r<30> a_wl_r<29> a_wl_r<28> a_wl_r<27> a_wl_r<26> a_wl_r<25> a_wl_r<24> a_wl_r<23> a_wl_r<22> a_wl_r<21> a_wl_r<20> a_wl_r<19> a_wl_r<18> a_wl_r<17> a_wl_r<16> VDD! VSS! / RM_IHPSG13_256x16_c2_2P_WLDRV16X8 +XA_WLDRV<4> a_wi<15> a_wi<14> a_wi<13> a_wi<12> a_wi<11> a_wi<10> a_wi<9> a_wi<8> a_wi<7> a_wi<6> a_wi<5> a_wi<4> a_wi<3> a_wi<2> a_wi<1> a_wi<0> a_wl_r<15> a_wl_r<14> a_wl_r<13> a_wl_r<12> a_wl_r<11> a_wl_r<10> a_wl_r<9> a_wl_r<8> a_wl_r<7> a_wl_r<6> a_wl_r<5> a_wl_r<4> a_wl_r<3> a_wl_r<2> a_wl_r<1> a_wl_r<0> VDD! VSS! / RM_IHPSG13_256x16_c2_2P_WLDRV16X8 +XA_WLDRV<3> a_wi<63> a_wi<62> a_wi<61> a_wi<60> a_wi<59> a_wi<58> a_wi<57> a_wi<56> a_wi<55> a_wi<54> a_wi<53> a_wi<52> a_wi<51> a_wi<50> a_wi<49> a_wi<48> a_wl_l<63> a_wl_l<62> a_wl_l<61> a_wl_l<60> a_wl_l<59> a_wl_l<58> a_wl_l<57> a_wl_l<56> a_wl_l<55> a_wl_l<54> a_wl_l<53> a_wl_l<52> a_wl_l<51> a_wl_l<50> a_wl_l<49> a_wl_l<48> VDD! VSS! / RM_IHPSG13_256x16_c2_2P_WLDRV16X8 +XA_WLDRV<2> a_wi<47> a_wi<46> a_wi<45> a_wi<44> a_wi<43> a_wi<42> a_wi<41> a_wi<40> a_wi<39> a_wi<38> a_wi<37> a_wi<36> a_wi<35> a_wi<34> a_wi<33> a_wi<32> a_wl_l<47> a_wl_l<46> a_wl_l<45> a_wl_l<44> a_wl_l<43> a_wl_l<42> a_wl_l<41> a_wl_l<40> a_wl_l<39> a_wl_l<38> a_wl_l<37> a_wl_l<36> a_wl_l<35> a_wl_l<34> a_wl_l<33> a_wl_l<32> VDD! VSS! / RM_IHPSG13_256x16_c2_2P_WLDRV16X8 +XA_WLDRV<1> a_wi<31> a_wi<30> a_wi<29> a_wi<28> a_wi<27> a_wi<26> a_wi<25> a_wi<24> a_wi<23> a_wi<22> a_wi<21> a_wi<20> a_wi<19> a_wi<18> a_wi<17> a_wi<16> a_wl_l<31> a_wl_l<30> a_wl_l<29> a_wl_l<28> a_wl_l<27> a_wl_l<26> a_wl_l<25> a_wl_l<24> a_wl_l<23> a_wl_l<22> a_wl_l<21> a_wl_l<20> a_wl_l<19> a_wl_l<18> a_wl_l<17> a_wl_l<16> VDD! VSS! / RM_IHPSG13_256x16_c2_2P_WLDRV16X8 +XA_WLDRV<0> a_wi<15> a_wi<14> a_wi<13> a_wi<12> a_wi<11> a_wi<10> a_wi<9> a_wi<8> a_wi<7> a_wi<6> a_wi<5> a_wi<4> a_wi<3> a_wi<2> a_wi<1> a_wi<0> a_wl_l<15> a_wl_l<14> a_wl_l<13> a_wl_l<12> a_wl_l<11> a_wl_l<10> a_wl_l<9> a_wl_l<8> a_wl_l<7> a_wl_l<6> a_wl_l<5> a_wl_l<4> a_wl_l<3> a_wl_l<2> a_wl_l<1> a_wl_l<0> VDD! VSS! / RM_IHPSG13_256x16_c2_2P_WLDRV16X8 + + +XB_CTRL b_aclk_n B_BIST_CLK B_BIST_MEN B_BIST_EN B_BIST_REN B_BIST_WEN b_tiel B_CLK B_MEN b_dclk b_eclk b_pulse_h b_pulse_l b_pulse b_rclk B_REN b_cs b_wclk B_WEN VDD! VSS! / RM_IHPSG13_256x16_c2_2P_CTRL +XA_CTRL a_aclk_n A_BIST_CLK A_BIST_MEN A_BIST_EN A_BIST_REN A_BIST_WEN a_tiel A_CLK A_MEN a_dclk a_eclk a_pulse_h a_pulse_l a_pulse a_rclk A_REN a_cs a_wclk A_WEN VDD! VSS! / RM_IHPSG13_256x16_c2_2P_CTRL + + +XB_ROWDEC b_addr_row<5> b_addr_row<4> b_addr_row<3> b_addr_row<2> b_addr_row<1> b_addr_row<0> b_cs b_eclk b_wi<63> b_wi<62> b_wi<61> b_wi<60> b_wi<59> b_wi<58> b_wi<57> b_wi<56> b_wi<55> b_wi<54> b_wi<53> b_wi<52> b_wi<51> b_wi<50> b_wi<49> b_wi<48> b_wi<47> b_wi<46> b_wi<45> b_wi<44> b_wi<43> b_wi<42> b_wi<41> b_wi<40> b_wi<39> b_wi<38> b_wi<37> b_wi<36> b_wi<35> b_wi<34> b_wi<33> b_wi<32> b_wi<31> b_wi<30> b_wi<29> b_wi<28> b_wi<27> b_wi<26> b_wi<25> b_wi<24> b_wi<23> b_wi<22> b_wi<21> b_wi<20> b_wi<19> b_wi<18> b_wi<17> b_wi<16> b_wi<15> b_wi<14> b_wi<13> b_wi<12> b_wi<11> b_wi<10> b_wi<9> b_wi<8> b_wi<7> b_wi<6> b_wi<5> b_wi<4> b_wi<3> b_wi<2> b_wi<1> b_wi<0> VDD! VSS! / RM_IHPSG13_256x16_c2_2P_ROWDEC6 +XA_ROWDEC a_addr_row<5> a_addr_row<4> a_addr_row<3> a_addr_row<2> a_addr_row<1> a_addr_row<0> a_cs a_eclk a_wi<63> a_wi<62> a_wi<61> a_wi<60> a_wi<59> a_wi<58> a_wi<57> a_wi<56> a_wi<55> a_wi<54> a_wi<53> a_wi<52> a_wi<51> a_wi<50> a_wi<49> a_wi<48> a_wi<47> a_wi<46> a_wi<45> a_wi<44> a_wi<43> a_wi<42> a_wi<41> a_wi<40> a_wi<39> a_wi<38> a_wi<37> a_wi<36> a_wi<35> a_wi<34> a_wi<33> a_wi<32> a_wi<31> a_wi<30> a_wi<29> a_wi<28> a_wi<27> a_wi<26> a_wi<25> a_wi<24> a_wi<23> a_wi<22> a_wi<21> a_wi<20> a_wi<19> a_wi<18> a_wi<17> a_wi<16> a_wi<15> a_wi<14> a_wi<13> a_wi<12> a_wi<11> a_wi<10> a_wi<9> a_wi<8> a_wi<7> a_wi<6> a_wi<5> a_wi<4> a_wi<3> a_wi<2> a_wi<1> a_wi<0> VDD! VSS! / RM_IHPSG13_256x16_c2_2P_ROWDEC6 +XB_ROWREG b_aclk_n B_ADDR<7> B_ADDR<6> B_ADDR<5> B_ADDR<4> B_ADDR<3> B_ADDR<2> b_addr_row<5> b_addr_row<4> b_addr_row<3> b_addr_row<2> b_addr_row<1> b_addr_row<0> B_BIST_ADDR<7> B_BIST_ADDR<6> B_BIST_ADDR<5> B_BIST_ADDR<4> B_BIST_ADDR<3> B_BIST_ADDR<2> B_BIST_EN VDD! VSS! / RM_IHPSG13_256x16_c2_2P_ROWREG6 +XA_ROWREG a_aclk_n A_ADDR<7> A_ADDR<6> A_ADDR<5> A_ADDR<4> A_ADDR<3> A_ADDR<2> a_addr_row<5> a_addr_row<4> a_addr_row<3> a_addr_row<2> a_addr_row<1> a_addr_row<0> A_BIST_ADDR<7> A_BIST_ADDR<6> A_BIST_ADDR<5> A_BIST_ADDR<4> A_BIST_ADDR<3> A_BIST_ADDR<2> A_BIST_EN VDD! VSS! / RM_IHPSG13_256x16_c2_2P_ROWREG6 +XB_COLDEC b_aclk_n B_ADDR<1> B_ADDR<0> b_addr_col<1> b_addr_col<0> b_addr_dec<7> b_addr_dec<6> b_addr_dec<5> b_addr_dec<4> b_addr_dec<3> b_addr_dec<2> b_addr_dec<1> b_addr_dec<0> B_BIST_ADDR<1> B_BIST_ADDR<0> B_BIST_EN VDD! VSS! / RM_IHPSG13_256x16_c2_2P_COLDEC2 +XA_COLDEC a_aclk_n A_ADDR<1> A_ADDR<0> a_addr_col<1> a_addr_col<0> a_addr_dec<7> a_addr_dec<6> a_addr_dec<5> a_addr_dec<4> a_addr_dec<3> a_addr_dec<2> a_addr_dec<1> a_addr_dec<0> A_BIST_ADDR<1> A_BIST_ADDR<0> A_BIST_EN VDD! VSS! / RM_IHPSG13_256x16_c2_2P_COLDEC2 + + +XB_DLYH b_pulse b_pulse_h VDD! VSS! / RM_IHPSG13_256x16_c2_2P_DLY_pcell_2 +XB_DLYL b_pulse_x b_pulse_l VDD! VSS! / RM_IHPSG13_256x16_c2_2P_DLY_pcell_3 +XA_DLYH a_pulse a_pulse_h VDD! VSS! / RM_IHPSG13_256x16_c2_2P_DLY_pcell_2 +XA_DLYL a_pulse_x a_pulse_l VDD! VSS! / RM_IHPSG13_256x16_c2_2P_DLY_pcell_3 +XB_DLYMUX b_pulse_h B_DLY b_pulse_x VDD! VSS! / RM_IHPSG13_256x16_c2_2P_DLY_MUX +XA_DLYMUX a_pulse_h A_DLY a_pulse_x VDD! VSS! / RM_IHPSG13_256x16_c2_2P_DLY_MUX + +XCOLCTRL<15> a_addr_dec_r<3> a_addr_dec_r<2> a_addr_dec_r<1> a_addr_dec_r<0> A_BIST_BM<15> A_BIST_DIN<15> A_BIST_EN a_blc_r<31> a_blc_r<30> a_blc_r<29> a_blc_r<28> a_blt_r<31> a_blt_r<30> a_blt_r<29> a_blt_r<28> A_BM<15> a_dclk_n_r<7> a_dclk_n_r<8> a_dclk_p_r<7> a_dclk_p_r<8> A_DOUT<15> A_DIN<15> a_rclk_n_r<7> a_rclk_n_r<8> a_rclk_p_r<7> a_rclk_p_r<8> a_tieh<15> a_wclk_n_r<7> a_wclk_n_r<8> a_wclk_p_r<7> a_wclk_p_r<8> b_addr_dec_r<3> b_addr_dec_r<2> b_addr_dec_r<1> b_addr_dec_r<0> B_BIST_BM<15> B_BIST_DIN<15> B_BIST_EN b_blc_r<31> b_blc_r<30> b_blc_r<29> b_blc_r<28> b_blt_r<31> b_blt_r<30> b_blt_r<29> b_blt_r<28> B_BM<15> b_dclk_n_r<7> b_dclk_n_r<8> b_dclk_p_r<7> b_dclk_p_r<8> B_DOUT<15> B_DIN<15> b_rclk_n_r<7> b_rclk_n_r<8> b_rclk_p_r<7> b_rclk_p_r<8> b_tieh<15> b_wclk_n_r<7> b_wclk_n_r<8> b_wclk_p_r<7> b_wclk_p_r<8> VDD! VSS! / RM_IHPSG13_256x16_c2_2P_COLCTRL2 +XCOLCTRL<14> a_addr_dec_r<3> a_addr_dec_r<2> a_addr_dec_r<1> a_addr_dec_r<0> A_BIST_BM<14> A_BIST_DIN<14> A_BIST_EN a_blc_r<27> a_blc_r<26> a_blc_r<25> a_blc_r<24> a_blt_r<27> a_blt_r<26> a_blt_r<25> a_blt_r<24> A_BM<14> a_dclk_n_r<6> a_dclk_n_r<7> a_dclk_p_r<6> a_dclk_p_r<7> A_DOUT<14> A_DIN<14> a_rclk_n_r<6> a_rclk_n_r<7> a_rclk_p_r<6> a_rclk_p_r<7> a_tieh<14> a_wclk_n_r<6> a_wclk_n_r<7> a_wclk_p_r<6> a_wclk_p_r<7> b_addr_dec_r<3> b_addr_dec_r<2> b_addr_dec_r<1> b_addr_dec_r<0> B_BIST_BM<14> B_BIST_DIN<14> B_BIST_EN b_blc_r<27> b_blc_r<26> b_blc_r<25> b_blc_r<24> b_blt_r<27> b_blt_r<26> b_blt_r<25> b_blt_r<24> B_BM<14> b_dclk_n_r<6> b_dclk_n_r<7> b_dclk_p_r<6> b_dclk_p_r<7> B_DOUT<14> B_DIN<14> b_rclk_n_r<6> b_rclk_n_r<7> b_rclk_p_r<6> b_rclk_p_r<7> b_tieh<14> b_wclk_n_r<6> b_wclk_n_r<7> b_wclk_p_r<6> b_wclk_p_r<7> VDD! VSS! / RM_IHPSG13_256x16_c2_2P_COLCTRL2 +XCOLCTRL<13> a_addr_dec_r<3> a_addr_dec_r<2> a_addr_dec_r<1> a_addr_dec_r<0> A_BIST_BM<13> A_BIST_DIN<13> A_BIST_EN a_blc_r<23> a_blc_r<22> a_blc_r<21> a_blc_r<20> a_blt_r<23> a_blt_r<22> a_blt_r<21> a_blt_r<20> A_BM<13> a_dclk_n_r<5> a_dclk_n_r<6> a_dclk_p_r<5> a_dclk_p_r<6> A_DOUT<13> A_DIN<13> a_rclk_n_r<5> a_rclk_n_r<6> a_rclk_p_r<5> a_rclk_p_r<6> a_tieh<13> a_wclk_n_r<5> a_wclk_n_r<6> a_wclk_p_r<5> a_wclk_p_r<6> b_addr_dec_r<3> b_addr_dec_r<2> b_addr_dec_r<1> b_addr_dec_r<0> B_BIST_BM<13> B_BIST_DIN<13> B_BIST_EN b_blc_r<23> b_blc_r<22> b_blc_r<21> b_blc_r<20> b_blt_r<23> b_blt_r<22> b_blt_r<21> b_blt_r<20> B_BM<13> b_dclk_n_r<5> b_dclk_n_r<6> b_dclk_p_r<5> b_dclk_p_r<6> B_DOUT<13> B_DIN<13> b_rclk_n_r<5> b_rclk_n_r<6> b_rclk_p_r<5> b_rclk_p_r<6> b_tieh<13> b_wclk_n_r<5> b_wclk_n_r<6> b_wclk_p_r<5> b_wclk_p_r<6> VDD! VSS! / RM_IHPSG13_256x16_c2_2P_COLCTRL2 +XCOLCTRL<12> a_addr_dec_r<3> a_addr_dec_r<2> a_addr_dec_r<1> a_addr_dec_r<0> A_BIST_BM<12> A_BIST_DIN<12> A_BIST_EN a_blc_r<19> a_blc_r<18> a_blc_r<17> a_blc_r<16> a_blt_r<19> a_blt_r<18> a_blt_r<17> a_blt_r<16> A_BM<12> a_dclk_n_r<4> a_dclk_n_r<5> a_dclk_p_r<4> a_dclk_p_r<5> A_DOUT<12> A_DIN<12> a_rclk_n_r<4> a_rclk_n_r<5> a_rclk_p_r<4> a_rclk_p_r<5> a_tieh<12> a_wclk_n_r<4> a_wclk_n_r<5> a_wclk_p_r<4> a_wclk_p_r<5> b_addr_dec_r<3> b_addr_dec_r<2> b_addr_dec_r<1> b_addr_dec_r<0> B_BIST_BM<12> B_BIST_DIN<12> B_BIST_EN b_blc_r<19> b_blc_r<18> b_blc_r<17> b_blc_r<16> b_blt_r<19> b_blt_r<18> b_blt_r<17> b_blt_r<16> B_BM<12> b_dclk_n_r<4> b_dclk_n_r<5> b_dclk_p_r<4> b_dclk_p_r<5> B_DOUT<12> B_DIN<12> b_rclk_n_r<4> b_rclk_n_r<5> b_rclk_p_r<4> b_rclk_p_r<5> b_tieh<12> b_wclk_n_r<4> b_wclk_n_r<5> b_wclk_p_r<4> b_wclk_p_r<5> VDD! VSS! / RM_IHPSG13_256x16_c2_2P_COLCTRL2 +XCOLCTRL<11> a_addr_dec_r<3> a_addr_dec_r<2> a_addr_dec_r<1> a_addr_dec_r<0> A_BIST_BM<11> A_BIST_DIN<11> A_BIST_EN a_blc_r<15> a_blc_r<14> a_blc_r<13> a_blc_r<12> a_blt_r<15> a_blt_r<14> a_blt_r<13> a_blt_r<12> A_BM<11> a_dclk_n_r<3> a_dclk_n_r<4> a_dclk_p_r<3> a_dclk_p_r<4> A_DOUT<11> A_DIN<11> a_rclk_n_r<3> a_rclk_n_r<4> a_rclk_p_r<3> a_rclk_p_r<4> a_tieh<11> a_wclk_n_r<3> a_wclk_n_r<4> a_wclk_p_r<3> a_wclk_p_r<4> b_addr_dec_r<3> b_addr_dec_r<2> b_addr_dec_r<1> b_addr_dec_r<0> B_BIST_BM<11> B_BIST_DIN<11> B_BIST_EN b_blc_r<15> b_blc_r<14> b_blc_r<13> b_blc_r<12> b_blt_r<15> b_blt_r<14> b_blt_r<13> b_blt_r<12> B_BM<11> b_dclk_n_r<3> b_dclk_n_r<4> b_dclk_p_r<3> b_dclk_p_r<4> B_DOUT<11> B_DIN<11> b_rclk_n_r<3> b_rclk_n_r<4> b_rclk_p_r<3> b_rclk_p_r<4> b_tieh<11> b_wclk_n_r<3> b_wclk_n_r<4> b_wclk_p_r<3> b_wclk_p_r<4> VDD! VSS! / RM_IHPSG13_256x16_c2_2P_COLCTRL2 +XCOLCTRL<10> a_addr_dec_r<3> a_addr_dec_r<2> a_addr_dec_r<1> a_addr_dec_r<0> A_BIST_BM<10> A_BIST_DIN<10> A_BIST_EN a_blc_r<11> a_blc_r<10> a_blc_r<9> a_blc_r<8> a_blt_r<11> a_blt_r<10> a_blt_r<9> a_blt_r<8> A_BM<10> a_dclk_n_r<2> a_dclk_n_r<3> a_dclk_p_r<2> a_dclk_p_r<3> A_DOUT<10> A_DIN<10> a_rclk_n_r<2> a_rclk_n_r<3> a_rclk_p_r<2> a_rclk_p_r<3> a_tieh<10> a_wclk_n_r<2> a_wclk_n_r<3> a_wclk_p_r<2> a_wclk_p_r<3> b_addr_dec_r<3> b_addr_dec_r<2> b_addr_dec_r<1> b_addr_dec_r<0> B_BIST_BM<10> B_BIST_DIN<10> B_BIST_EN b_blc_r<11> b_blc_r<10> b_blc_r<9> b_blc_r<8> b_blt_r<11> b_blt_r<10> b_blt_r<9> b_blt_r<8> B_BM<10> b_dclk_n_r<2> b_dclk_n_r<3> b_dclk_p_r<2> b_dclk_p_r<3> B_DOUT<10> B_DIN<10> b_rclk_n_r<2> b_rclk_n_r<3> b_rclk_p_r<2> b_rclk_p_r<3> b_tieh<10> b_wclk_n_r<2> b_wclk_n_r<3> b_wclk_p_r<2> b_wclk_p_r<3> VDD! VSS! / RM_IHPSG13_256x16_c2_2P_COLCTRL2 +XCOLCTRL<9> a_addr_dec_r<3> a_addr_dec_r<2> a_addr_dec_r<1> a_addr_dec_r<0> A_BIST_BM<9> A_BIST_DIN<9> A_BIST_EN a_blc_r<7> a_blc_r<6> a_blc_r<5> a_blc_r<4> a_blt_r<7> a_blt_r<6> a_blt_r<5> a_blt_r<4> A_BM<9> a_dclk_n_r<1> a_dclk_n_r<2> a_dclk_p_r<1> a_dclk_p_r<2> A_DOUT<9> A_DIN<9> a_rclk_n_r<1> a_rclk_n_r<2> a_rclk_p_r<1> a_rclk_p_r<2> a_tieh<9> a_wclk_n_r<1> a_wclk_n_r<2> a_wclk_p_r<1> a_wclk_p_r<2> b_addr_dec_r<3> b_addr_dec_r<2> b_addr_dec_r<1> b_addr_dec_r<0> B_BIST_BM<9> B_BIST_DIN<9> B_BIST_EN b_blc_r<7> b_blc_r<6> b_blc_r<5> b_blc_r<4> b_blt_r<7> b_blt_r<6> b_blt_r<5> b_blt_r<4> B_BM<9> b_dclk_n_r<1> b_dclk_n_r<2> b_dclk_p_r<1> b_dclk_p_r<2> B_DOUT<9> B_DIN<9> b_rclk_n_r<1> b_rclk_n_r<2> b_rclk_p_r<1> b_rclk_p_r<2> b_tieh<9> b_wclk_n_r<1> b_wclk_n_r<2> b_wclk_p_r<1> b_wclk_p_r<2> VDD! VSS! / RM_IHPSG13_256x16_c2_2P_COLCTRL2 +XCOLCTRL<8> a_addr_dec_r<3> a_addr_dec_r<2> a_addr_dec_r<1> a_addr_dec_r<0> A_BIST_BM<8> A_BIST_DIN<8> A_BIST_EN a_blc_r<3> a_blc_r<2> a_blc_r<1> a_blc_r<0> a_blt_r<3> a_blt_r<2> a_blt_r<1> a_blt_r<0> A_BM<8> a_dclk_n_r<0> a_dclk_n_r<1> a_dclk_p_r<0> a_dclk_p_r<1> A_DOUT<8> A_DIN<8> a_rclk_n_r<0> a_rclk_n_r<1> a_rclk_p_r<0> a_rclk_p_r<1> a_tieh<8> a_wclk_n_r<0> a_wclk_n_r<1> a_wclk_p_r<0> a_wclk_p_r<1> b_addr_dec_r<3> b_addr_dec_r<2> b_addr_dec_r<1> b_addr_dec_r<0> B_BIST_BM<8> B_BIST_DIN<8> B_BIST_EN b_blc_r<3> b_blc_r<2> b_blc_r<1> b_blc_r<0> b_blt_r<3> b_blt_r<2> b_blt_r<1> b_blt_r<0> B_BM<8> b_dclk_n_r<0> b_dclk_n_r<1> b_dclk_p_r<0> b_dclk_p_r<1> B_DOUT<8> B_DIN<8> b_rclk_n_r<0> b_rclk_n_r<1> b_rclk_p_r<0> b_rclk_p_r<1> b_tieh<8> b_wclk_n_r<0> b_wclk_n_r<1> b_wclk_p_r<0> b_wclk_p_r<1> VDD! VSS! / RM_IHPSG13_256x16_c2_2P_COLCTRL2 +XCOLCTRL<7> a_addr_dec_l<3> a_addr_dec_l<2> a_addr_dec_l<1> a_addr_dec_l<0> A_BIST_BM<0> A_BIST_DIN<0> A_BIST_EN a_blc_l<31> a_blc_l<30> a_blc_l<29> a_blc_l<28> a_blt_l<31> a_blt_l<30> a_blt_l<29> a_blt_l<28> A_BM<0> a_dclk_n_l<7> a_dclk_n_l<8> a_dclk_p_l<7> a_dclk_p_l<8> A_DOUT<0> A_DIN<0> a_rclk_n_l<7> a_rclk_n_l<8> a_rclk_p_l<7> a_rclk_p_l<8> a_tieh<0> a_wclk_n_l<7> a_wclk_n_l<8> a_wclk_p_l<7> a_wclk_p_l<8> b_addr_dec_l<3> b_addr_dec_l<2> b_addr_dec_l<1> b_addr_dec_l<0> B_BIST_BM<0> B_BIST_DIN<0> B_BIST_EN b_blc_l<31> b_blc_l<30> b_blc_l<29> b_blc_l<28> b_blt_l<31> b_blt_l<30> b_blt_l<29> b_blt_l<28> B_BM<0> b_dclk_n_l<7> b_dclk_n_l<8> b_dclk_p_l<7> b_dclk_p_l<8> B_DOUT<0> B_DIN<0> b_rclk_n_l<7> b_rclk_n_l<8> b_rclk_p_l<7> b_rclk_p_l<8> b_tieh<0> b_wclk_n_l<7> b_wclk_n_l<8> b_wclk_p_l<7> b_wclk_p_l<8> VDD! VSS! / RM_IHPSG13_256x16_c2_2P_COLCTRL2 +XCOLCTRL<6> a_addr_dec_l<3> a_addr_dec_l<2> a_addr_dec_l<1> a_addr_dec_l<0> A_BIST_BM<1> A_BIST_DIN<1> A_BIST_EN a_blc_l<27> a_blc_l<26> a_blc_l<25> a_blc_l<24> a_blt_l<27> a_blt_l<26> a_blt_l<25> a_blt_l<24> A_BM<1> a_dclk_n_l<6> a_dclk_n_l<7> a_dclk_p_l<6> a_dclk_p_l<7> A_DOUT<1> A_DIN<1> a_rclk_n_l<6> a_rclk_n_l<7> a_rclk_p_l<6> a_rclk_p_l<7> a_tieh<1> a_wclk_n_l<6> a_wclk_n_l<7> a_wclk_p_l<6> a_wclk_p_l<7> b_addr_dec_l<3> b_addr_dec_l<2> b_addr_dec_l<1> b_addr_dec_l<0> B_BIST_BM<1> B_BIST_DIN<1> B_BIST_EN b_blc_l<27> b_blc_l<26> b_blc_l<25> b_blc_l<24> b_blt_l<27> b_blt_l<26> b_blt_l<25> b_blt_l<24> B_BM<1> b_dclk_n_l<6> b_dclk_n_l<7> b_dclk_p_l<6> b_dclk_p_l<7> B_DOUT<1> B_DIN<1> b_rclk_n_l<6> b_rclk_n_l<7> b_rclk_p_l<6> b_rclk_p_l<7> b_tieh<1> b_wclk_n_l<6> b_wclk_n_l<7> b_wclk_p_l<6> b_wclk_p_l<7> VDD! VSS! / RM_IHPSG13_256x16_c2_2P_COLCTRL2 +XCOLCTRL<5> a_addr_dec_l<3> a_addr_dec_l<2> a_addr_dec_l<1> a_addr_dec_l<0> A_BIST_BM<2> A_BIST_DIN<2> A_BIST_EN a_blc_l<23> a_blc_l<22> a_blc_l<21> a_blc_l<20> a_blt_l<23> a_blt_l<22> a_blt_l<21> a_blt_l<20> A_BM<2> a_dclk_n_l<5> a_dclk_n_l<6> a_dclk_p_l<5> a_dclk_p_l<6> A_DOUT<2> A_DIN<2> a_rclk_n_l<5> a_rclk_n_l<6> a_rclk_p_l<5> a_rclk_p_l<6> a_tieh<2> a_wclk_n_l<5> a_wclk_n_l<6> a_wclk_p_l<5> a_wclk_p_l<6> b_addr_dec_l<3> b_addr_dec_l<2> b_addr_dec_l<1> b_addr_dec_l<0> B_BIST_BM<2> B_BIST_DIN<2> B_BIST_EN b_blc_l<23> b_blc_l<22> b_blc_l<21> b_blc_l<20> b_blt_l<23> b_blt_l<22> b_blt_l<21> b_blt_l<20> B_BM<2> b_dclk_n_l<5> b_dclk_n_l<6> b_dclk_p_l<5> b_dclk_p_l<6> B_DOUT<2> B_DIN<2> b_rclk_n_l<5> b_rclk_n_l<6> b_rclk_p_l<5> b_rclk_p_l<6> b_tieh<2> b_wclk_n_l<5> b_wclk_n_l<6> b_wclk_p_l<5> b_wclk_p_l<6> VDD! VSS! / RM_IHPSG13_256x16_c2_2P_COLCTRL2 +XCOLCTRL<4> a_addr_dec_l<3> a_addr_dec_l<2> a_addr_dec_l<1> a_addr_dec_l<0> A_BIST_BM<3> A_BIST_DIN<3> A_BIST_EN a_blc_l<19> a_blc_l<18> a_blc_l<17> a_blc_l<16> a_blt_l<19> a_blt_l<18> a_blt_l<17> a_blt_l<16> A_BM<3> a_dclk_n_l<4> a_dclk_n_l<5> a_dclk_p_l<4> a_dclk_p_l<5> A_DOUT<3> A_DIN<3> a_rclk_n_l<4> a_rclk_n_l<5> a_rclk_p_l<4> a_rclk_p_l<5> a_tieh<3> a_wclk_n_l<4> a_wclk_n_l<5> a_wclk_p_l<4> a_wclk_p_l<5> b_addr_dec_l<3> b_addr_dec_l<2> b_addr_dec_l<1> b_addr_dec_l<0> B_BIST_BM<3> B_BIST_DIN<3> B_BIST_EN b_blc_l<19> b_blc_l<18> b_blc_l<17> b_blc_l<16> b_blt_l<19> b_blt_l<18> b_blt_l<17> b_blt_l<16> B_BM<3> b_dclk_n_l<4> b_dclk_n_l<5> b_dclk_p_l<4> b_dclk_p_l<5> B_DOUT<3> B_DIN<3> b_rclk_n_l<4> b_rclk_n_l<5> b_rclk_p_l<4> b_rclk_p_l<5> b_tieh<3> b_wclk_n_l<4> b_wclk_n_l<5> b_wclk_p_l<4> b_wclk_p_l<5> VDD! VSS! / RM_IHPSG13_256x16_c2_2P_COLCTRL2 +XCOLCTRL<3> a_addr_dec_l<3> a_addr_dec_l<2> a_addr_dec_l<1> a_addr_dec_l<0> A_BIST_BM<4> A_BIST_DIN<4> A_BIST_EN a_blc_l<15> a_blc_l<14> a_blc_l<13> a_blc_l<12> a_blt_l<15> a_blt_l<14> a_blt_l<13> a_blt_l<12> A_BM<4> a_dclk_n_l<3> a_dclk_n_l<4> a_dclk_p_l<3> a_dclk_p_l<4> A_DOUT<4> A_DIN<4> a_rclk_n_l<3> a_rclk_n_l<4> a_rclk_p_l<3> a_rclk_p_l<4> a_tieh<4> a_wclk_n_l<3> a_wclk_n_l<4> a_wclk_p_l<3> a_wclk_p_l<4> b_addr_dec_l<3> b_addr_dec_l<2> b_addr_dec_l<1> b_addr_dec_l<0> B_BIST_BM<4> B_BIST_DIN<4> B_BIST_EN b_blc_l<15> b_blc_l<14> b_blc_l<13> b_blc_l<12> b_blt_l<15> b_blt_l<14> b_blt_l<13> b_blt_l<12> B_BM<4> b_dclk_n_l<3> b_dclk_n_l<4> b_dclk_p_l<3> b_dclk_p_l<4> B_DOUT<4> B_DIN<4> b_rclk_n_l<3> b_rclk_n_l<4> b_rclk_p_l<3> b_rclk_p_l<4> b_tieh<4> b_wclk_n_l<3> b_wclk_n_l<4> b_wclk_p_l<3> b_wclk_p_l<4> VDD! VSS! / RM_IHPSG13_256x16_c2_2P_COLCTRL2 +XCOLCTRL<2> a_addr_dec_l<3> a_addr_dec_l<2> a_addr_dec_l<1> a_addr_dec_l<0> A_BIST_BM<5> A_BIST_DIN<5> A_BIST_EN a_blc_l<11> a_blc_l<10> a_blc_l<9> a_blc_l<8> a_blt_l<11> a_blt_l<10> a_blt_l<9> a_blt_l<8> A_BM<5> a_dclk_n_l<2> a_dclk_n_l<3> a_dclk_p_l<2> a_dclk_p_l<3> A_DOUT<5> A_DIN<5> a_rclk_n_l<2> a_rclk_n_l<3> a_rclk_p_l<2> a_rclk_p_l<3> a_tieh<5> a_wclk_n_l<2> a_wclk_n_l<3> a_wclk_p_l<2> a_wclk_p_l<3> b_addr_dec_l<3> b_addr_dec_l<2> b_addr_dec_l<1> b_addr_dec_l<0> B_BIST_BM<5> B_BIST_DIN<5> B_BIST_EN b_blc_l<11> b_blc_l<10> b_blc_l<9> b_blc_l<8> b_blt_l<11> b_blt_l<10> b_blt_l<9> b_blt_l<8> B_BM<5> b_dclk_n_l<2> b_dclk_n_l<3> b_dclk_p_l<2> b_dclk_p_l<3> B_DOUT<5> B_DIN<5> b_rclk_n_l<2> b_rclk_n_l<3> b_rclk_p_l<2> b_rclk_p_l<3> b_tieh<5> b_wclk_n_l<2> b_wclk_n_l<3> b_wclk_p_l<2> b_wclk_p_l<3> VDD! VSS! / RM_IHPSG13_256x16_c2_2P_COLCTRL2 +XCOLCTRL<1> a_addr_dec_l<3> a_addr_dec_l<2> a_addr_dec_l<1> a_addr_dec_l<0> A_BIST_BM<6> A_BIST_DIN<6> A_BIST_EN a_blc_l<7> a_blc_l<6> a_blc_l<5> a_blc_l<4> a_blt_l<7> a_blt_l<6> a_blt_l<5> a_blt_l<4> A_BM<6> a_dclk_n_l<1> a_dclk_n_l<2> a_dclk_p_l<1> a_dclk_p_l<2> A_DOUT<6> A_DIN<6> a_rclk_n_l<1> a_rclk_n_l<2> a_rclk_p_l<1> a_rclk_p_l<2> a_tieh<6> a_wclk_n_l<1> a_wclk_n_l<2> a_wclk_p_l<1> a_wclk_p_l<2> b_addr_dec_l<3> b_addr_dec_l<2> b_addr_dec_l<1> b_addr_dec_l<0> B_BIST_BM<6> B_BIST_DIN<6> B_BIST_EN b_blc_l<7> b_blc_l<6> b_blc_l<5> b_blc_l<4> b_blt_l<7> b_blt_l<6> b_blt_l<5> b_blt_l<4> B_BM<6> b_dclk_n_l<1> b_dclk_n_l<2> b_dclk_p_l<1> b_dclk_p_l<2> B_DOUT<6> B_DIN<6> b_rclk_n_l<1> b_rclk_n_l<2> b_rclk_p_l<1> b_rclk_p_l<2> b_tieh<6> b_wclk_n_l<1> b_wclk_n_l<2> b_wclk_p_l<1> b_wclk_p_l<2> VDD! VSS! / RM_IHPSG13_256x16_c2_2P_COLCTRL2 +XCOLCTRL<0> a_addr_dec_l<3> a_addr_dec_l<2> a_addr_dec_l<1> a_addr_dec_l<0> A_BIST_BM<7> A_BIST_DIN<7> A_BIST_EN a_blc_l<3> a_blc_l<2> a_blc_l<1> a_blc_l<0> a_blt_l<3> a_blt_l<2> a_blt_l<1> a_blt_l<0> A_BM<7> a_dclk_n_l<0> a_dclk_n_l<1> a_dclk_p_l<0> a_dclk_p_l<1> A_DOUT<7> A_DIN<7> a_rclk_n_l<0> a_rclk_n_l<1> a_rclk_p_l<0> a_rclk_p_l<1> a_tieh<7> a_wclk_n_l<0> a_wclk_n_l<1> a_wclk_p_l<0> a_wclk_p_l<1> b_addr_dec_l<3> b_addr_dec_l<2> b_addr_dec_l<1> b_addr_dec_l<0> B_BIST_BM<7> B_BIST_DIN<7> B_BIST_EN b_blc_l<3> b_blc_l<2> b_blc_l<1> b_blc_l<0> b_blt_l<3> b_blt_l<2> b_blt_l<1> b_blt_l<0> B_BM<7> b_dclk_n_l<0> b_dclk_n_l<1> b_dclk_p_l<0> b_dclk_p_l<1> B_DOUT<7> B_DIN<7> b_rclk_n_l<0> b_rclk_n_l<1> b_rclk_p_l<0> b_rclk_p_l<1> b_tieh<7> b_wclk_n_l<0> b_wclk_n_l<1> b_wclk_p_l<0> b_wclk_p_l<1> VDD! VSS! / RM_IHPSG13_256x16_c2_2P_COLCTRL2 + + +XDRVFILL4<1> VDD! VSS! / RM_IHPSG13_256x16_c2_2P_COLDRV13_FILL4 +XDRVFILL4<2> VDD! VSS! / RM_IHPSG13_256x16_c2_2P_COLDRV13_FILL4 +XDRVFILL4<3> VDD! VSS! / RM_IHPSG13_256x16_c2_2P_COLDRV13_FILL4 +XDRVFILL4<4> VDD! VSS! / RM_IHPSG13_256x16_c2_2P_COLDRV13_FILL4 +XDRVFILL4<5> VDD! VSS! / RM_IHPSG13_256x16_c2_2P_COLDRV13_FILL4 +XDRVFILL4<6> VDD! VSS! / RM_IHPSG13_256x16_c2_2P_COLDRV13_FILL4 +XDRVFILL4<7> VDD! VSS! / RM_IHPSG13_256x16_c2_2P_COLDRV13_FILL4 +XDRVFILL4<8> VDD! VSS! / RM_IHPSG13_256x16_c2_2P_COLDRV13_FILL4 +XDRVFILL4<9> VDD! VSS! / RM_IHPSG13_256x16_c2_2P_COLDRV13_FILL4 +XDRVFILL4<10> VDD! VSS! / RM_IHPSG13_256x16_c2_2P_COLDRV13_FILL4 +XCOLFILL4<1> VDD! VSS! / RM_IHPSG13_256x16_c2_2P_COLDRV13_FILL4C2 +XCOLFILL4<2> VDD! VSS! / RM_IHPSG13_256x16_c2_2P_COLDRV13_FILL4C2 +XCOLFILL4<3> VDD! VSS! / RM_IHPSG13_256x16_c2_2P_COLDRV13_FILL4C2 +XCOLFILL4<4> VDD! VSS! / RM_IHPSG13_256x16_c2_2P_COLDRV13_FILL4C2 +XCOLFILL4<5> VDD! VSS! / RM_IHPSG13_256x16_c2_2P_COLDRV13_FILL4C2 +XCOLFILL4<6> VDD! VSS! / RM_IHPSG13_256x16_c2_2P_COLDRV13_FILL4C2 +XCOLFILL4<7> VDD! VSS! / RM_IHPSG13_256x16_c2_2P_COLDRV13_FILL4C2 +XCOLFILL4<8> VDD! VSS! / RM_IHPSG13_256x16_c2_2P_COLDRV13_FILL4C2 +XCOLFILL4<9> VDD! VSS! / RM_IHPSG13_256x16_c2_2P_COLDRV13_FILL4C2 +XCOLFILL4<10> VDD! VSS! / RM_IHPSG13_256x16_c2_2P_COLDRV13_FILL4C2 +XCOLFILL4<11> VDD! VSS! / RM_IHPSG13_256x16_c2_2P_COLDRV13_FILL4C2 +XCOLFILL4<12> VDD! VSS! / RM_IHPSG13_256x16_c2_2P_COLDRV13_FILL4C2 +XCOLFILL4<13> VDD! VSS! / RM_IHPSG13_256x16_c2_2P_COLDRV13_FILL4C2 +XCOLFILL4<14> VDD! VSS! / RM_IHPSG13_256x16_c2_2P_COLDRV13_FILL4C2 +XCOLFILL4<15> VDD! VSS! / RM_IHPSG13_256x16_c2_2P_COLDRV13_FILL4C2 +XCOLFILL4<16> VDD! VSS! / RM_IHPSG13_256x16_c2_2P_COLDRV13_FILL4C2 +XCOLFILL4<17> VDD! VSS! / RM_IHPSG13_256x16_c2_2P_COLDRV13_FILL4C2 +XCOLFILL4<18> VDD! VSS! / RM_IHPSG13_256x16_c2_2P_COLDRV13_FILL4C2 +XCOLFILL4<19> VDD! VSS! / RM_IHPSG13_256x16_c2_2P_COLDRV13_FILL4C2 +XCOLFILL4<20> VDD! VSS! / RM_IHPSG13_256x16_c2_2P_COLDRV13_FILL4C2 +XCOLFILL4<21> VDD! VSS! / RM_IHPSG13_256x16_c2_2P_COLDRV13_FILL4C2 +XCOLFILL4<22> VDD! VSS! / RM_IHPSG13_256x16_c2_2P_COLDRV13_FILL4C2 +XCOLFILL4<23> VDD! VSS! / RM_IHPSG13_256x16_c2_2P_COLDRV13_FILL4C2 +XCOLFILL4<24> VDD! VSS! / RM_IHPSG13_256x16_c2_2P_COLDRV13_FILL4C2 +.ENDS diff --git a/flow/platforms/ihp-sg13g2/cdl/RM_IHPSG13_2P_256x32_c2_bm_bist.cdl b/flow/platforms/ihp-sg13g2/cdl/RM_IHPSG13_2P_256x32_c2_bm_bist.cdl new file mode 100644 index 0000000000..f439f0d1c9 --- /dev/null +++ b/flow/platforms/ihp-sg13g2/cdl/RM_IHPSG13_2P_256x32_c2_bm_bist.cdl @@ -0,0 +1,6410 @@ +* ------------------------------------------------------ +* +* Copyright 2025 IHP PDK Authors +* +* Licensed under the Apache License, Version 2.0 (the "License"); +* you may not use this file except in compliance with the License. +* You may obtain a copy of the License at +* +* https://www.apache.org/licenses/LICENSE-2.0 +* +* Unless required by applicable law or agreed to in writing, software +* distributed under the License is distributed on an "AS IS" BASIS, +* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +* See the License for the specific language governing permissions and +* limitations under the License. +* +* Generated on Wed Aug 27 13:14:43 2025 +* +* ------------------------------------------------------ + +.SUBCKT RM_IHPSG13_256x32_c2_1P_BITKIT_CORNER NW PW VDD VSS +.ENDS +.SUBCKT RM_IHPSG13_256x32_c2_1P_BITKIT_16x2_CORNER VDD_CORE VSS +XI16 VDD_CORE VSS VDD_CORE VSS / ++ RM_IHPSG13_256x32_c2_1P_BITKIT_CORNER +.ENDS +.SUBCKT RM_IHPSG13_256x32_c2_1P_BITKIT_EDGE_LR LWL NW PW VDD VSS +MN1 VSS LWL VSS VSS sg13_lv_nmos m=1 w=300.0n l=130.00n ng=1 nrd=0 nrs=0 +MN0 VSS net9 VSS VSS sg13_lv_nmos m=1 w=300.0n l=130.00n ng=1 nrd=0 nrs=0 +.ENDS +.SUBCKT RM_IHPSG13_256x32_c2_1P_BITKIT_16x2_EDGE_LR A_WL<15> A_WL<14> A_WL<13> A_WL<12> ++ A_WL<11> A_WL<10> A_WL<9> A_WL<8> A_WL<7> A_WL<6> A_WL<5> A_WL<4> A_WL<3> ++ A_WL<2> A_WL<1> A_WL<0> VDD_CORE VSS +XI0<15> A_WL<15> VDD_CORE VSS VDD_CORE VSS / ++ RM_IHPSG13_256x32_c2_1P_BITKIT_EDGE_LR +XI0<14> A_WL<14> VDD_CORE VSS VDD_CORE VSS / ++ RM_IHPSG13_256x32_c2_1P_BITKIT_EDGE_LR +XI0<13> A_WL<13> VDD_CORE VSS VDD_CORE VSS / ++ RM_IHPSG13_256x32_c2_1P_BITKIT_EDGE_LR +XI0<12> A_WL<12> VDD_CORE VSS VDD_CORE VSS / ++ RM_IHPSG13_256x32_c2_1P_BITKIT_EDGE_LR +XI0<11> A_WL<11> VDD_CORE VSS VDD_CORE VSS / ++ RM_IHPSG13_256x32_c2_1P_BITKIT_EDGE_LR +XI0<10> A_WL<10> VDD_CORE VSS VDD_CORE VSS / ++ RM_IHPSG13_256x32_c2_1P_BITKIT_EDGE_LR +XI0<9> A_WL<9> VDD_CORE VSS VDD_CORE VSS / ++ RM_IHPSG13_256x32_c2_1P_BITKIT_EDGE_LR +XI0<8> A_WL<8> VDD_CORE VSS VDD_CORE VSS / ++ RM_IHPSG13_256x32_c2_1P_BITKIT_EDGE_LR +XI0<7> A_WL<7> VDD_CORE VSS VDD_CORE VSS / ++ RM_IHPSG13_256x32_c2_1P_BITKIT_EDGE_LR +XI0<6> A_WL<6> VDD_CORE VSS VDD_CORE VSS / ++ RM_IHPSG13_256x32_c2_1P_BITKIT_EDGE_LR +XI0<5> A_WL<5> VDD_CORE VSS VDD_CORE VSS / ++ RM_IHPSG13_256x32_c2_1P_BITKIT_EDGE_LR +XI0<4> A_WL<4> VDD_CORE VSS VDD_CORE VSS / ++ RM_IHPSG13_256x32_c2_1P_BITKIT_EDGE_LR +XI0<3> A_WL<3> VDD_CORE VSS VDD_CORE VSS / ++ RM_IHPSG13_256x32_c2_1P_BITKIT_EDGE_LR +XI0<2> A_WL<2> VDD_CORE VSS VDD_CORE VSS / ++ RM_IHPSG13_256x32_c2_1P_BITKIT_EDGE_LR +XI0<1> A_WL<1> VDD_CORE VSS VDD_CORE VSS / ++ RM_IHPSG13_256x32_c2_1P_BITKIT_EDGE_LR +XI0<0> A_WL<0> VDD_CORE VSS VDD_CORE VSS / ++ RM_IHPSG13_256x32_c2_1P_BITKIT_EDGE_LR +.ENDS +.SUBCKT RM_IHPSG13_256x32_c2_1P_BITKIT_CELL BLC_BOT BLC_TOP BLT_BOT BLT_TOP LWL NW PW ++ RWL VDD VSS +MN0 NC NT VSS PW sg13_lv_nmos m=1 w=300.0n l=130.00n ng=1 nrd=0 nrs=0 +MN1 NT NC VSS PW sg13_lv_nmos m=1 w=300.0n l=130.00n ng=1 nrd=0 nrs=0 +MN3 NC RWL BLC_TOP PW sg13_lv_nmos m=1 w=300.0n l=130.00n ng=1 nrd=0 nrs=0 +MN2 BLT_BOT LWL NT PW sg13_lv_nmos m=1 w=300.0n l=130.00n ng=1 nrd=0 nrs=0 +MP1 NT NC VDD NW sg13_lv_pmos m=1 w=150.00n l=130.00n ng=1 nrd=0 nrs=0 +MP0 NC NT VDD NW sg13_lv_pmos m=1 w=150.00n l=130.00n ng=1 nrd=0 nrs=0 +R1 BLC_BOT BLC_TOP lvsres w=2.6e-07 l=6e-07 +R0 BLT_BOT BLT_TOP lvsres w=2.6e-07 l=6e-07 +R2 RWL LWL lvsres w=2.6e-07 l=6e-07 +.ENDS +.SUBCKT RM_IHPSG13_256x32_c2_1P_BITKIT_16x2_SRAM A_BLC_BOT<1> A_BLC_BOT<0> A_BLC_TOP<1> ++ A_BLC_TOP<0> A_BLT_BOT<1> A_BLT_BOT<0> A_BLT_TOP<1> A_BLT_TOP<0> A_LWL<15> ++ A_LWL<14> A_LWL<13> A_LWL<12> A_LWL<11> A_LWL<10> A_LWL<9> A_LWL<8> A_LWL<7> ++ A_LWL<6> A_LWL<5> A_LWL<4> A_LWL<3> A_LWL<2> A_LWL<1> A_LWL<0> A_RWL<15> ++ A_RWL<14> A_RWL<13> A_RWL<12> A_RWL<11> A_RWL<10> A_RWL<9> A_RWL<8> A_RWL<7> ++ A_RWL<6> A_RWL<5> A_RWL<4> A_RWL<3> A_RWL<2> A_RWL<1> A_RWL<0> VDD_CORE ++ VSS +XCELL<31> A_BLC_TOP<1> A_RBLC<15> A_BLT_TOP<1> A_RBLT<15> A_RWL<15> ++ VDD_CORE VSS A_XWL<15> VDD_CORE VSS / ++ RM_IHPSG13_256x32_c2_1P_BITKIT_CELL +XCELL<30> A_RBLC<14> A_RBLC<15> A_RBLT<14> A_RBLT<15> A_RWL<14> VDD_CORE ++ VSS A_XWL<14> VDD_CORE VSS / RM_IHPSG13_256x32_c2_1P_BITKIT_CELL +XCELL<29> A_RBLC<14> A_RBLC<13> A_RBLT<14> A_RBLT<13> A_RWL<13> VDD_CORE ++ VSS A_XWL<13> VDD_CORE VSS / RM_IHPSG13_256x32_c2_1P_BITKIT_CELL +XCELL<28> A_RBLC<12> A_RBLC<13> A_RBLT<12> A_RBLT<13> A_RWL<12> VDD_CORE ++ VSS A_XWL<12> VDD_CORE VSS / RM_IHPSG13_256x32_c2_1P_BITKIT_CELL +XCELL<27> A_RBLC<12> A_RBLC<11> A_RBLT<12> A_RBLT<11> A_RWL<11> VDD_CORE ++ VSS A_XWL<11> VDD_CORE VSS / RM_IHPSG13_256x32_c2_1P_BITKIT_CELL +XCELL<26> A_RBLC<10> A_RBLC<11> A_RBLT<10> A_RBLT<11> A_RWL<10> VDD_CORE ++ VSS A_XWL<10> VDD_CORE VSS / RM_IHPSG13_256x32_c2_1P_BITKIT_CELL +XCELL<25> A_RBLC<10> A_RBLC<9> A_RBLT<10> A_RBLT<9> A_RWL<9> VDD_CORE ++ VSS A_XWL<9> VDD_CORE VSS / RM_IHPSG13_256x32_c2_1P_BITKIT_CELL +XCELL<24> A_RBLC<8> A_RBLC<9> A_RBLT<8> A_RBLT<9> A_RWL<8> VDD_CORE ++ VSS A_XWL<8> VDD_CORE VSS / RM_IHPSG13_256x32_c2_1P_BITKIT_CELL +XCELL<23> A_RBLC<8> A_RBLC<7> A_RBLT<8> A_RBLT<7> A_RWL<7> VDD_CORE ++ VSS A_XWL<7> VDD_CORE VSS / RM_IHPSG13_256x32_c2_1P_BITKIT_CELL +XCELL<22> A_RBLC<6> A_RBLC<7> A_RBLT<6> A_RBLT<7> A_RWL<6> VDD_CORE ++ VSS A_XWL<6> VDD_CORE VSS / RM_IHPSG13_256x32_c2_1P_BITKIT_CELL +XCELL<21> A_RBLC<6> A_RBLC<5> A_RBLT<6> A_RBLT<5> A_RWL<5> VDD_CORE ++ VSS A_XWL<5> VDD_CORE VSS / RM_IHPSG13_256x32_c2_1P_BITKIT_CELL +XCELL<20> A_RBLC<4> A_RBLC<5> A_RBLT<4> A_RBLT<5> A_RWL<4> VDD_CORE ++ VSS A_XWL<4> VDD_CORE VSS / RM_IHPSG13_256x32_c2_1P_BITKIT_CELL +XCELL<19> A_RBLC<4> A_RBLC<3> A_RBLT<4> A_RBLT<3> A_RWL<3> VDD_CORE ++ VSS A_XWL<3> VDD_CORE VSS / RM_IHPSG13_256x32_c2_1P_BITKIT_CELL +XCELL<18> A_RBLC<2> A_RBLC<3> A_RBLT<2> A_RBLT<3> A_RWL<2> VDD_CORE ++ VSS A_XWL<2> VDD_CORE VSS / RM_IHPSG13_256x32_c2_1P_BITKIT_CELL +XCELL<17> A_RBLC<2> A_RBLC<1> A_RBLT<2> A_RBLT<1> A_RWL<1> VDD_CORE ++ VSS A_XWL<1> VDD_CORE VSS / RM_IHPSG13_256x32_c2_1P_BITKIT_CELL +XCELL<16> A_BLC_BOT<1> A_RBLC<1> A_BLT_BOT<1> A_RBLT<1> A_RWL<0> VDD_CORE ++ VSS A_XWL<0> VDD_CORE VSS / RM_IHPSG13_256x32_c2_1P_BITKIT_CELL +XCELL<15> A_BLC_TOP<0> A_LBLC<15> A_BLT_TOP<0> A_LBLT<15> A_LWL<15> ++ VDD_CORE VSS A_XWL<15> VDD_CORE VSS / ++ RM_IHPSG13_256x32_c2_1P_BITKIT_CELL +XCELL<14> A_LBLC<14> A_LBLC<15> A_LBLT<14> A_LBLT<15> A_LWL<14> VDD_CORE ++ VSS A_XWL<14> VDD_CORE VSS / RM_IHPSG13_256x32_c2_1P_BITKIT_CELL +XCELL<13> A_LBLC<14> A_LBLC<13> A_LBLT<14> A_LBLT<13> A_LWL<13> VDD_CORE ++ VSS A_XWL<13> VDD_CORE VSS / RM_IHPSG13_256x32_c2_1P_BITKIT_CELL +XCELL<12> A_LBLC<12> A_LBLC<13> A_LBLT<12> A_LBLT<13> A_LWL<12> VDD_CORE ++ VSS A_XWL<12> VDD_CORE VSS / RM_IHPSG13_256x32_c2_1P_BITKIT_CELL +XCELL<11> A_LBLC<12> A_LBLC<11> A_LBLT<12> A_LBLT<11> A_LWL<11> VDD_CORE ++ VSS A_XWL<11> VDD_CORE VSS / RM_IHPSG13_256x32_c2_1P_BITKIT_CELL +XCELL<10> A_LBLC<10> A_LBLC<11> A_LBLT<10> A_LBLT<11> A_LWL<10> VDD_CORE ++ VSS A_XWL<10> VDD_CORE VSS / RM_IHPSG13_256x32_c2_1P_BITKIT_CELL +XCELL<9> A_LBLC<10> A_LBLC<9> A_LBLT<10> A_LBLT<9> A_LWL<9> VDD_CORE ++ VSS A_XWL<9> VDD_CORE VSS / RM_IHPSG13_256x32_c2_1P_BITKIT_CELL +XCELL<8> A_LBLC<8> A_LBLC<9> A_LBLT<8> A_LBLT<9> A_LWL<8> VDD_CORE ++ VSS A_XWL<8> VDD_CORE VSS / RM_IHPSG13_256x32_c2_1P_BITKIT_CELL +XCELL<7> A_LBLC<8> A_LBLC<7> A_LBLT<8> A_LBLT<7> A_LWL<7> VDD_CORE ++ VSS A_XWL<7> VDD_CORE VSS / RM_IHPSG13_256x32_c2_1P_BITKIT_CELL +XCELL<6> A_LBLC<6> A_LBLC<7> A_LBLT<6> A_LBLT<7> A_LWL<6> VDD_CORE ++ VSS A_XWL<6> VDD_CORE VSS / RM_IHPSG13_256x32_c2_1P_BITKIT_CELL +XCELL<5> A_LBLC<6> A_LBLC<5> A_LBLT<6> A_LBLT<5> A_LWL<5> VDD_CORE ++ VSS A_XWL<5> VDD_CORE VSS / RM_IHPSG13_256x32_c2_1P_BITKIT_CELL +XCELL<4> A_LBLC<4> A_LBLC<5> A_LBLT<4> A_LBLT<5> A_LWL<4> VDD_CORE ++ VSS A_XWL<4> VDD_CORE VSS / RM_IHPSG13_256x32_c2_1P_BITKIT_CELL +XCELL<3> A_LBLC<4> A_LBLC<3> A_LBLT<4> A_LBLT<3> A_LWL<3> VDD_CORE ++ VSS A_XWL<3> VDD_CORE VSS / RM_IHPSG13_256x32_c2_1P_BITKIT_CELL +XCELL<2> A_LBLC<2> A_LBLC<3> A_LBLT<2> A_LBLT<3> A_LWL<2> VDD_CORE ++ VSS A_XWL<2> VDD_CORE VSS / RM_IHPSG13_256x32_c2_1P_BITKIT_CELL +XCELL<1> A_LBLC<2> A_LBLC<1> A_LBLT<2> A_LBLT<1> A_LWL<1> VDD_CORE ++ VSS A_XWL<1> VDD_CORE VSS / RM_IHPSG13_256x32_c2_1P_BITKIT_CELL +XCELL<0> A_BLC_BOT<0> A_LBLC<1> A_BLT_BOT<0> A_LBLT<1> A_LWL<0> VDD_CORE ++ VSS A_XWL<0> VDD_CORE VSS / RM_IHPSG13_256x32_c2_1P_BITKIT_CELL +.ENDS +.SUBCKT RM_IHPSG13_256x32_c2_1P_BITKIT_EDGE_TB BLC BLT NW PW VDD VSS +.ENDS +.SUBCKT RM_IHPSG13_256x32_c2_1P_BITKIT_16x2_EDGE_TB A_BLC<1> A_BLC<0> A_BLT<1> A_BLT<0> ++ VDD_CORE VSS +XEDGE<1> A_BLC<1> A_BLT<1> VDD_CORE VSS VDD_CORE VSS ++ / RM_IHPSG13_256x32_c2_1P_BITKIT_EDGE_TB +XEDGE<0> A_BLC<0> A_BLT<0> VDD_CORE VSS VDD_CORE VSS ++ / RM_IHPSG13_256x32_c2_1P_BITKIT_EDGE_TB +.ENDS + +.SUBCKT RSC_IHPSG13_CBUFX4 A Z VDD VSS +MN0 net9 A VSS VSS sg13_lv_nmos m=1 w=705.000n l=130.00n ng=1 nrd=0 ++ nrs=0 +MN1 Z net9 VSS VSS sg13_lv_nmos m=1 w=1.41u l=130.00n ng=2 nrd=0 nrs=0 +MP0 net9 A VDD VDD sg13_lv_pmos m=1 w=1.62u l=130.00n ng=1 nrd=0 nrs=0 +MP1 Z net9 VDD VDD sg13_lv_pmos m=1 w=3.24u l=130.00n ng=2 nrd=0 nrs=0 +.ENDS +.SUBCKT RM_IHPSG13_256x32_c2_1P_COLDRV13X4 ADDR_COL_I<1> ADDR_COL_I<0> ADDR_COL_O<1> ++ ADDR_COL_O<0> ADDR_DEC_I<7> ADDR_DEC_I<6> ADDR_DEC_I<5> ADDR_DEC_I<4> ++ ADDR_DEC_I<3> ADDR_DEC_I<2> ADDR_DEC_I<1> ADDR_DEC_I<0> ADDR_DEC_O<7> ++ ADDR_DEC_O<6> ADDR_DEC_O<5> ADDR_DEC_O<4> ADDR_DEC_O<3> ADDR_DEC_O<2> ++ ADDR_DEC_O<1> ADDR_DEC_O<0> DCLK_I DCLK_O RCLK_I RCLK_O WCLK_I WCLK_O ++ VDD VSS +XADDR_COL_DRV<1> ADDR_COL_I<1> ADDR_COL_O<1> VDD VSS / ++ RSC_IHPSG13_CBUFX4 +XADDR_COL_DRV<0> ADDR_COL_I<0> ADDR_COL_O<0> VDD VSS / ++ RSC_IHPSG13_CBUFX4 +XADDR_DEC_DRV<7> ADDR_DEC_I<7> ADDR_DEC_O<7> VDD VSS / ++ RSC_IHPSG13_CBUFX4 +XADDR_DEC_DRV<6> ADDR_DEC_I<6> ADDR_DEC_O<6> VDD VSS / ++ RSC_IHPSG13_CBUFX4 +XADDR_DEC_DRV<5> ADDR_DEC_I<5> ADDR_DEC_O<5> VDD VSS / ++ RSC_IHPSG13_CBUFX4 +XADDR_DEC_DRV<4> ADDR_DEC_I<4> ADDR_DEC_O<4> VDD VSS / ++ RSC_IHPSG13_CBUFX4 +XADDR_DEC_DRV<3> ADDR_DEC_I<3> ADDR_DEC_O<3> VDD VSS / ++ RSC_IHPSG13_CBUFX4 +XADDR_DEC_DRV<2> ADDR_DEC_I<2> ADDR_DEC_O<2> VDD VSS / ++ RSC_IHPSG13_CBUFX4 +XADDR_DEC_DRV<1> ADDR_DEC_I<1> ADDR_DEC_O<1> VDD VSS / ++ RSC_IHPSG13_CBUFX4 +XADDR_DEC_DRV<0> ADDR_DEC_I<0> ADDR_DEC_O<0> VDD VSS / ++ RSC_IHPSG13_CBUFX4 +XDCLK_DRV DCLK_I DCLK_O VDD VSS / RSC_IHPSG13_CBUFX4 +XRCLK_DRV RCLK_I RCLK_O VDD VSS / RSC_IHPSG13_CBUFX4 +XWCLK_DRV WCLK_I WCLK_O VDD VSS / RSC_IHPSG13_CBUFX4 +.ENDS +.SUBCKT RSC_IHPSG13_WLDRVX4 A Z VDD VSS +MN1 Z net6 VSS VSS sg13_lv_nmos m=1 w=705.000n l=130.00n ng=1 nrd=0 ++ nrs=0 +MN0 net6 A VSS VSS sg13_lv_nmos m=1 w=900.0n l=130.00n ng=1 nrd=0 nrs=0 +MP1 Z net6 VDD VDD sg13_lv_pmos m=1 w=3.24u l=130.00n ng=2 nrd=0 nrs=0 +MP0 net6 A VDD VDD sg13_lv_pmos m=1 w=900.0n l=130.00n ng=1 nrd=0 nrs=0 +.ENDS +.SUBCKT RM_IHPSG13_256x32_c2_1P_WLDRV16X4 A<15> A<14> A<13> A<12> A<11> A<10> A<9> A<8> ++ A<7> A<6> A<5> A<4> A<3> A<2> A<1> A<0> Z<15> Z<14> Z<13> Z<12> Z<11> Z<10> ++ Z<9> Z<8> Z<7> Z<6> Z<5> Z<4> Z<3> Z<2> Z<1> Z<0> VDD VSS +XBUF<15> A<15> Z<15> VDD VSS / RSC_IHPSG13_WLDRVX4 +XBUF<14> A<14> Z<14> VDD VSS / RSC_IHPSG13_WLDRVX4 +XBUF<13> A<13> Z<13> VDD VSS / RSC_IHPSG13_WLDRVX4 +XBUF<12> A<12> Z<12> VDD VSS / RSC_IHPSG13_WLDRVX4 +XBUF<11> A<11> Z<11> VDD VSS / RSC_IHPSG13_WLDRVX4 +XBUF<10> A<10> Z<10> VDD VSS / RSC_IHPSG13_WLDRVX4 +XBUF<9> A<9> Z<9> VDD VSS / RSC_IHPSG13_WLDRVX4 +XBUF<8> A<8> Z<8> VDD VSS / RSC_IHPSG13_WLDRVX4 +XBUF<7> A<7> Z<7> VDD VSS / RSC_IHPSG13_WLDRVX4 +XBUF<6> A<6> Z<6> VDD VSS / RSC_IHPSG13_WLDRVX4 +XBUF<5> A<5> Z<5> VDD VSS / RSC_IHPSG13_WLDRVX4 +XBUF<4> A<4> Z<4> VDD VSS / RSC_IHPSG13_WLDRVX4 +XBUF<3> A<3> Z<3> VDD VSS / RSC_IHPSG13_WLDRVX4 +XBUF<2> A<2> Z<2> VDD VSS / RSC_IHPSG13_WLDRVX4 +XBUF<1> A<1> Z<1> VDD VSS / RSC_IHPSG13_WLDRVX4 +XBUF<0> A<0> Z<0> VDD VSS / RSC_IHPSG13_WLDRVX4 +.ENDS +.SUBCKT RSC_IHPSG13_FILLCAP8 VDD VSS +MN0 vss_r vdd_r VSS VSS sg13_lv_nmos m=1 w=4.98u l=130.00n ng=6 nrd=0 ++ nrs=0 +MP0 vdd_r vss_r VDD VDD sg13_lv_pmos m=1 w=6.48u l=385.000n ng=4 nrd=0 ++ nrs=0 +.ENDS +.SUBCKT RSC_IHPSG13_LHPQX2 CP D Q VDD VSS +MN3 QIN CPN net14 VSS sg13_lv_nmos m=1 w=480.00n l=130.00n ng=1 nrd=0 nrs=0 +MN2 net14 net10 VSS VSS sg13_lv_nmos m=1 w=480.00n l=130.00n ng=1 ++ nrd=0 nrs=0 +MN5 net21 D VSS VSS sg13_lv_nmos m=1 w=870.00n l=130.00n ng=1 nrd=0 ++ nrs=0 +MN6 QIN CP net21 VSS sg13_lv_nmos m=1 w=870.00n l=130.00n ng=1 nrd=0 nrs=0 +MN1 net10 QIN VSS VSS sg13_lv_nmos m=1 w=480.00n l=130.00n ng=1 nrd=0 ++ nrs=0 +MN0 CPN CP VSS VSS sg13_lv_nmos m=1 w=480.00n l=130.00n ng=1 nrd=0 ++ nrs=0 +MN4 Q QIN VSS VSS sg13_lv_nmos m=1 w=980.00n l=130.00n ng=1 nrd=0 nrs=0 +MP2 QIN CP net16 VDD sg13_lv_pmos m=1 w=480.00n l=130.00n ng=1 nrd=0 nrs=0 +MP0 CPN CP VDD VDD sg13_lv_pmos m=1 w=480.00n l=130.00n ng=1 nrd=0 ++ nrs=0 +MP4 Q QIN VDD VDD sg13_lv_pmos m=1 w=1.62u l=130.00n ng=1 nrd=0 nrs=0 +MP3 net10 QIN VDD VDD sg13_lv_pmos m=1 w=480.00n l=130.00n ng=1 nrd=0 ++ nrs=0 +MP1 net16 net10 VDD VDD sg13_lv_pmos m=1 w=480.00n l=130.00n ng=1 ++ nrd=0 nrs=0 +MP6 QIN CPN net20 VDD sg13_lv_pmos m=1 w=975.000n l=130.00n ng=1 nrd=0 ++ nrs=0 +MP5 net20 D VDD VDD sg13_lv_pmos m=1 w=975.000n l=130.00n ng=1 nrd=0 ++ nrs=0 +.ENDS +.SUBCKT RSC_IHPSG13_NAND2X2 A B Z VDD VSS +MP1 Z B VDD VDD sg13_lv_pmos m=1 w=1.62u l=130.00n ng=1 nrd=0 nrs=0 +MP0 Z A VDD VDD sg13_lv_pmos m=1 w=1.62u l=130.00n ng=1 nrd=0 nrs=0 +MN0 Z B net7 VSS sg13_lv_nmos m=1 w=980.00n l=130.00n ng=1 nrd=0 nrs=0 +MN1 net7 A VSS VSS sg13_lv_nmos m=1 w=980.00n l=130.00n ng=1 nrd=0 ++ nrs=0 +.ENDS +.SUBCKT RSC_IHPSG13_CINVX4 A Z VDD VSS +MN0 Z A VSS VSS sg13_lv_nmos m=1 w=1.41u l=130.00n ng=2 nrd=0 nrs=0 +MP0 Z A VDD VDD sg13_lv_pmos m=1 w=3.24u l=130.00n ng=2 nrd=0 nrs=0 +.ENDS +.SUBCKT RSC_IHPSG13_CINVX2 A Z VDD VSS +MN0 Z A VSS VSS sg13_lv_nmos m=1 w=705.000n l=130.00n ng=1 nrd=0 nrs=0 +MP0 Z A VDD VDD sg13_lv_pmos m=1 w=1.62u l=130.00n ng=1 nrd=0 nrs=0 +.ENDS +.SUBCKT RSC_IHPSG13_INVX2 A Z VDD VSS +MN0 Z A VSS VSS sg13_lv_nmos m=1 w=980.00n l=130.00n ng=1 nrd=0 nrs=0 +MP0 Z A VDD VDD sg13_lv_pmos m=1 w=1.62u l=130.00n ng=1 nrd=0 nrs=0 +.ENDS +.SUBCKT RSC_IHPSG13_NAND3X2 A B C Z VDD VSS +MP2 Z A VDD VDD sg13_lv_pmos m=1 w=1.62u l=130.00n ng=1 nrd=0 nrs=0 +MP1 Z B VDD VDD sg13_lv_pmos m=1 w=1.62u l=130.00n ng=1 nrd=0 nrs=0 +MP0 Z C VDD VDD sg13_lv_pmos m=1 w=1.62u l=130.00n ng=1 nrd=0 nrs=0 +MN1 net12 B net16 VSS sg13_lv_nmos m=1 w=980.00n l=130.00n ng=1 nrd=0 nrs=0 +MN0 Z C net12 VSS sg13_lv_nmos m=1 w=980.00n l=130.00n ng=1 nrd=0 nrs=0 +MN2 net16 A VSS VSS sg13_lv_nmos m=1 w=980.00n l=130.00n ng=1 nrd=0 ++ nrs=0 +.ENDS +.SUBCKT RSC_IHPSG13_NOR3X2 A B C Z VDD VSS +MP0 net13 A VDD VDD sg13_lv_pmos m=1 w=1.62u l=130.00n ng=1 nrd=0 nrs=0 +MP2 Z C net10 VDD sg13_lv_pmos m=1 w=1.62u l=130.00n ng=1 nrd=0 nrs=0 +MP1 net10 B net13 VDD sg13_lv_pmos m=1 w=1.62u l=130.00n ng=1 nrd=0 nrs=0 +MN1 Z B VSS VSS sg13_lv_nmos m=1 w=875.000n l=130.00n ng=1 nrd=0 nrs=0 +MN0 Z C VSS VSS sg13_lv_nmos m=1 w=875.000n l=130.00n ng=1 nrd=0 nrs=0 +MN2 Z A VSS VSS sg13_lv_nmos m=1 w=875.000n l=130.00n ng=1 nrd=0 nrs=0 +.ENDS +.SUBCKT RSC_IHPSG13_FILLCAP4 VDD VSS +MN0 vss_r vdd_r VSS VSS sg13_lv_nmos m=1 w=2.49u l=130.00n ng=3 nrd=0 ++ nrs=0 +MP0 vdd_r vss_r VDD VDD sg13_lv_pmos m=1 w=3.24u l=385.000n ng=2 nrd=0 ++ nrs=0 +.ENDS +.SUBCKT RSC_IHPSG13_MET2RES A B +R0 B A lvsres w=2.6e-07 l=6e-07 +.ENDS +.SUBCKT RM_IHPSG13_256x32_c2_1P_DEC04 ADDR<3> ADDR<2> ADDR<1> ADDR<0> CS ECLK_H_BOT ++ ECLK_H_TOP ECLK_L_BOT ECLK_L_TOP WL<15> WL<14> WL<13> WL<12> WL<11> WL<10> ++ WL<9> WL<8> WL<7> WL<6> WL<5> WL<4> WL<3> WL<2> WL<1> WL<0> VDD VSS +XLATCH<3> CS ADDR<3> PADR<3> VDD VSS / RSC_IHPSG13_LHPQX2 +XLATCH<2> CS ADDR<2> PADR<2> VDD VSS / RSC_IHPSG13_LHPQX2 +XLATCH<1> CS ADDR<1> PADR<1> VDD VSS / RSC_IHPSG13_LHPQX2 +XLATCH<0> CS ADDR<0> PADR<0> VDD VSS / RSC_IHPSG13_LHPQX2 +XI0<3> PADR<1> PADR<0> sel01<3> VDD VSS / RSC_IHPSG13_NAND2X2 +XI0<2> PADR<1> NADR<0> sel01<2> VDD VSS / RSC_IHPSG13_NAND2X2 +XI0<1> NADR<1> PADR<0> sel01<1> VDD VSS / RSC_IHPSG13_NAND2X2 +XI0<0> NADR<1> NADR<0> sel01<0> VDD VSS / RSC_IHPSG13_NAND2X2 +XI4 ECLK_L_BOT EN VDD VSS / RSC_IHPSG13_CINVX4 +XI5 ECLK_H_BOT ECLK_L_BOT VDD VSS / RSC_IHPSG13_CINVX2 +XI3<3> PADR<3> NADR<3> VDD VSS / RSC_IHPSG13_INVX2 +XI3<2> PADR<2> NADR<2> VDD VSS / RSC_IHPSG13_INVX2 +XI3<1> PADR<1> NADR<1> VDD VSS / RSC_IHPSG13_INVX2 +XI3<0> PADR<0> NADR<0> VDD VSS / RSC_IHPSG13_INVX2 +XI1<3> PADR<2> PADR<3> CS sel23<3> VDD VSS / RSC_IHPSG13_NAND3X2 +XI1<2> NADR<2> PADR<3> CS sel23<2> VDD VSS / RSC_IHPSG13_NAND3X2 +XI1<1> PADR<2> NADR<3> CS sel23<1> VDD VSS / RSC_IHPSG13_NAND3X2 +XI1<0> NADR<2> NADR<3> CS sel23<0> VDD VSS / RSC_IHPSG13_NAND3X2 +XI2<15> sel23<3> sel01<3> EN WL<15> VDD VSS / RSC_IHPSG13_NOR3X2 +XI2<14> sel23<3> sel01<2> EN WL<14> VDD VSS / RSC_IHPSG13_NOR3X2 +XI2<13> sel23<3> sel01<1> EN WL<13> VDD VSS / RSC_IHPSG13_NOR3X2 +XI2<12> sel23<3> sel01<0> EN WL<12> VDD VSS / RSC_IHPSG13_NOR3X2 +XI2<11> sel23<2> sel01<3> EN WL<11> VDD VSS / RSC_IHPSG13_NOR3X2 +XI2<10> sel23<2> sel01<2> EN WL<10> VDD VSS / RSC_IHPSG13_NOR3X2 +XI2<9> sel23<2> sel01<1> EN WL<9> VDD VSS / RSC_IHPSG13_NOR3X2 +XI2<8> sel23<2> sel01<0> EN WL<8> VDD VSS / RSC_IHPSG13_NOR3X2 +XI2<7> sel23<1> sel01<3> EN WL<7> VDD VSS / RSC_IHPSG13_NOR3X2 +XI2<6> sel23<1> sel01<2> EN WL<6> VDD VSS / RSC_IHPSG13_NOR3X2 +XI2<5> sel23<1> sel01<1> EN WL<5> VDD VSS / RSC_IHPSG13_NOR3X2 +XI2<4> sel23<1> sel01<0> EN WL<4> VDD VSS / RSC_IHPSG13_NOR3X2 +XI2<3> sel23<0> sel01<3> EN WL<3> VDD VSS / RSC_IHPSG13_NOR3X2 +XI2<2> sel23<0> sel01<2> EN WL<2> VDD VSS / RSC_IHPSG13_NOR3X2 +XI2<1> sel23<0> sel01<1> EN WL<1> VDD VSS / RSC_IHPSG13_NOR3X2 +XI2<0> sel23<0> sel01<0> EN WL<0> VDD VSS / RSC_IHPSG13_NOR3X2 +XCAPS4 VDD VSS / RSC_IHPSG13_FILLCAP4 +XI11 ECLK_L_BOT ECLK_L_TOP / RSC_IHPSG13_MET2RES +XR0 ECLK_H_BOT ECLK_H_TOP / RSC_IHPSG13_MET2RES +.ENDS +.SUBCKT RM_IHPSG13_256x32_c2_1P_ROWDEC4 ADDR_N_I<3> ADDR_N_I<2> ADDR_N_I<1> ADDR_N_I<0> ++ CS_I ECLK_I WL_O<15> WL_O<14> WL_O<13> WL_O<12> WL_O<11> WL_O<10> WL_O<9> ++ WL_O<8> WL_O<7> WL_O<6> WL_O<5> WL_O<4> WL_O<3> WL_O<2> WL_O<1> WL_O<0> ++ VDD VSS +XL2<8> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<7> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<6> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<5> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<4> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<3> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<2> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<1> VDD VSS / RSC_IHPSG13_FILLCAP8 +XSEL ADDR_N_I<3> ADDR_N_I<2> ADDR_N_I<1> ADDR_N_I<0> CS_I ECLK_I ECLK_H<1> ++ ECLK_B<0> ECLK_B<1> WL_O<15> WL_O<14> WL_O<13> WL_O<12> WL_O<11> WL_O<10> ++ WL_O<9> WL_O<8> WL_O<7> WL_O<6> WL_O<5> WL_O<4> WL_O<3> WL_O<2> WL_O<1> ++ WL_O<0> VDD VSS / RM_IHPSG13_256x32_c2_1P_DEC04 +.ENDS +.SUBCKT RSC_IHPSG13_CINVX8 A Z VDD VSS +MN0 Z A VSS VSS sg13_lv_nmos m=1 w=2.82u l=130.00n ng=4 nrd=0 nrs=0 +MP0 Z A VDD VDD sg13_lv_pmos m=1 w=6.48u l=130.00n ng=4 nrd=0 nrs=0 +.ENDS +.SUBCKT RSC_IHPSG13_DFNQMX2IX1 BE BI CN D QI QIN VDD VSS +MN15 net026 BI VSS VSS sg13_lv_nmos m=1 w=560.00n l=130.00n ng=1 nrd=0 ++ nrs=0 +MN14 MXI_OUT BE net026 VSS sg13_lv_nmos m=1 w=560.00n l=130.00n ng=1 nrd=0 ++ nrs=0 +MN1 net025 D VSS VSS sg13_lv_nmos m=1 w=560.00n l=130.00n ng=1 nrd=0 ++ nrs=0 +MN0 MXI_OUT BEN net025 VSS sg13_lv_nmos m=1 w=560.00n l=130.00n ng=1 nrd=0 ++ nrs=0 +MN10 QI CNN net21 VSS sg13_lv_nmos m=1 w=850.00n l=130.00n ng=1 nrd=0 nrs=0 +MN11 net21 QI_MS VSS VSS sg13_lv_nmos m=1 w=850.00n l=130.00n ng=1 ++ nrd=0 nrs=0 +MN7 net30 QI_MS VSS VSS sg13_lv_nmos m=1 w=480.00n l=130.00n ng=1 ++ nrd=0 nrs=0 +MN6 QIN_MS CNN net30 VSS sg13_lv_nmos m=1 w=480.00n l=130.00n ng=1 nrd=0 ++ nrs=0 +MN3 QI_MS QIN_MS VSS VSS sg13_lv_nmos m=1 w=480.00n l=130.00n ng=1 ++ nrd=0 nrs=0 +MN12 CNN CN VSS VSS sg13_lv_nmos m=1 w=495.000n l=130.00n ng=1 nrd=0 ++ nrs=0 +MN9 net37 MXI_OUT VSS VSS sg13_lv_nmos m=1 w=870.00n l=130.00n ng=1 ++ nrd=0 nrs=0 +MN8 QIN_MS CN net37 VSS sg13_lv_nmos m=1 w=870.00n l=130.00n ng=1 nrd=0 ++ nrs=0 +MN5 QI CN net25 VSS sg13_lv_nmos m=1 w=480.00n l=130.00n ng=1 nrd=0 nrs=0 +MN4 net25 QIN VSS VSS sg13_lv_nmos m=1 w=480.00n l=130.00n ng=1 nrd=0 ++ nrs=0 +MN2 QIN QI VSS VSS sg13_lv_nmos m=1 w=480.00n l=130.00n ng=1 nrd=0 ++ nrs=0 +MN13 BEN BE VSS VSS sg13_lv_nmos m=1 w=560.00n l=130.00n ng=1 nrd=0 ++ nrs=0 +MP15 MXI_OUT BEN net027 VDD sg13_lv_pmos m=1 w=985.000n l=130.00n ng=1 ++ nrd=0 nrs=0 +MP14 net027 BI VDD VDD sg13_lv_pmos m=1 w=985.000n l=130.00n ng=1 ++ nrd=0 nrs=0 +MP1 MXI_OUT BE net024 VDD sg13_lv_pmos m=1 w=985.000n l=130.00n ng=1 nrd=0 ++ nrs=0 +MP0 net024 D VDD VDD sg13_lv_pmos m=1 w=985.000n l=130.00n ng=1 nrd=0 ++ nrs=0 +MP13 BEN BE VDD VDD sg13_lv_pmos m=1 w=645.000n l=130.00n ng=1 nrd=0 ++ nrs=0 +MP6 QI_MS QIN_MS VDD VDD sg13_lv_pmos m=1 w=480.00n l=130.00n ng=1 ++ nrd=0 nrs=0 +MP3 QI CNN net27 VDD sg13_lv_pmos m=1 w=480.00n l=130.00n ng=1 nrd=0 nrs=0 +MP2 net27 QIN VDD VDD sg13_lv_pmos m=1 w=480.00n l=130.00n ng=1 nrd=0 ++ nrs=0 +MP10 net36 MXI_OUT VDD VDD sg13_lv_pmos m=1 w=975.000n l=130.00n ng=1 ++ nrd=0 nrs=0 +MP11 QIN_MS CNN net36 VDD sg13_lv_pmos m=1 w=975.000n l=130.00n ng=1 nrd=0 ++ nrs=0 +MP4 net32 QI_MS VDD VDD sg13_lv_pmos m=1 w=480.00n l=130.00n ng=1 ++ nrd=0 nrs=0 +MP5 QIN_MS CN net32 VDD sg13_lv_pmos m=1 w=480.00n l=130.00n ng=1 nrd=0 ++ nrs=0 +MP7 QIN QI VDD VDD sg13_lv_pmos m=1 w=480.00n l=130.00n ng=1 nrd=0 ++ nrs=0 +MP12 CNN CN VDD VDD sg13_lv_pmos m=1 w=480.00n l=130.00n ng=1 nrd=0 ++ nrs=0 +MP9 QI CN net19 VDD sg13_lv_pmos m=1 w=990.00n l=130.00n ng=1 nrd=0 nrs=0 +MP8 net19 QI_MS VDD VDD sg13_lv_pmos m=1 w=990.00n l=130.00n ng=1 ++ nrd=0 nrs=0 +.ENDS +.SUBCKT RM_IHPSG13_256x32_c2_1P_ROWREG4 ACLK_N_I ADDR_I<3> ADDR_I<2> ADDR_I<1> ADDR_I<0> ++ ADDR_N_O<3> ADDR_N_O<2> ADDR_N_O<1> ADDR_N_O<0> BIST_ADDR_I<3> ++ BIST_ADDR_I<2> BIST_ADDR_I<1> BIST_ADDR_I<0> BIST_EN_I VDD VSS +XINV<3> q_int<3> qn_int<3> VDD VSS / RSC_IHPSG13_CINVX2 +XINV<2> q_int<2> qn_int<2> VDD VSS / RSC_IHPSG13_CINVX2 +XINV<1> q_int<1> qn_int<1> VDD VSS / RSC_IHPSG13_CINVX2 +XINV<0> q_int<0> qn_int<0> VDD VSS / RSC_IHPSG13_CINVX2 +XDRV<3> qn_int<3> ADDR_N_O<3> VDD VSS / RSC_IHPSG13_CINVX8 +XDRV<2> qn_int<2> ADDR_N_O<2> VDD VSS / RSC_IHPSG13_CINVX8 +XDRV<1> qn_int<1> ADDR_N_O<1> VDD VSS / RSC_IHPSG13_CINVX8 +XDRV<0> qn_int<0> ADDR_N_O<0> VDD VSS / RSC_IHPSG13_CINVX8 +XDFF<3> BIST_EN_I BIST_ADDR_I<3> ACLK_N_I ADDR_I<3> q_int<3> net2<0> VDD ++ VSS / RSC_IHPSG13_DFNQMX2IX1 +XDFF<2> BIST_EN_I BIST_ADDR_I<2> ACLK_N_I ADDR_I<2> q_int<2> net2<1> VDD ++ VSS / RSC_IHPSG13_DFNQMX2IX1 +XDFF<1> BIST_EN_I BIST_ADDR_I<1> ACLK_N_I ADDR_I<1> q_int<1> net2<2> VDD ++ VSS / RSC_IHPSG13_DFNQMX2IX1 +XDFF<0> BIST_EN_I BIST_ADDR_I<0> ACLK_N_I ADDR_I<0> q_int<0> net2<3> VDD ++ VSS / RSC_IHPSG13_DFNQMX2IX1 +XI11<20> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI11<19> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI11<18> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI11<17> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI11<16> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI11<15> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI11<14> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI11<13> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI11<12> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI11<11> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI11<10> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI11<9> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI11<8> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI11<7> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI11<6> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI11<5> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI11<4> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI11<3> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI11<2> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI11<1> VDD VSS / RSC_IHPSG13_FILLCAP8 +.ENDS +.SUBCKT RSC_IHPSG13_CDLYX1 A Z VDD VSS +MN1 net010 net032 VSS VSS sg13_lv_nmos m=1 w=300.0n l=160.00n ng=1 ++ nrd=0 nrs=0 +MN2 net032 A net014 VSS sg13_lv_nmos m=1 w=300.0n l=160.00n ng=1 nrd=0 ++ nrs=0 +MN0 Z net032 net010 VSS sg13_lv_nmos m=1 w=300.0n l=160.00n ng=1 nrd=0 ++ nrs=0 +MN3 net014 A VSS VSS sg13_lv_nmos m=1 w=300.0n l=160.00n ng=1 nrd=0 ++ nrs=0 +MP1 Z net032 net07 VDD sg13_lv_pmos m=1 w=720.00n l=160.00n ng=1 nrd=0 ++ nrs=0 +MP3 net011 A VDD VDD sg13_lv_pmos m=1 w=720.00n l=160.00n ng=1 nrd=0 ++ nrs=0 +MP0 net07 net032 VDD VDD sg13_lv_pmos m=1 w=720.00n l=160.00n ng=1 ++ nrd=0 nrs=0 +MP2 net032 A net011 VDD sg13_lv_pmos m=1 w=720.00n l=160.00n ng=1 nrd=0 ++ nrs=0 +.ENDS +.SUBCKT RSC_IHPSG13_CDLYX1_DUMMY A Z VDD VSS +MN0 vss_r vdd_r VSS VSS sg13_lv_nmos m=1 w=2.49u l=300.0n ng=3 nrd=0 ++ nrs=0 +MP0 vdd_r vss_r VDD VDD sg13_lv_pmos m=1 w=3.24u l=640.00n ng=2 nrd=0 ++ nrs=0 +R0 Z A lvsres w=2.6e-07 l=6e-07 +.ENDS + +.SUBCKT RSC_IHPSG13_MX2IX1 A0 A1 S ZN VDD VSS +MP4 SN S VDD VDD sg13_lv_pmos m=1 w=645.000n l=130.00n ng=1 nrd=0 nrs=0 +MP3 ZN SN net12 VDD sg13_lv_pmos m=1 w=985.000n l=130.00n ng=1 nrd=0 nrs=0 +MP2 net12 A1 VDD VDD sg13_lv_pmos m=1 w=985.000n l=130.00n ng=1 nrd=0 ++ nrs=0 +MP1 ZN S net17 VDD sg13_lv_pmos m=1 w=985.000n l=130.00n ng=1 nrd=0 nrs=0 +MP0 net17 A0 VDD VDD sg13_lv_pmos m=1 w=985.000n l=130.00n ng=1 nrd=0 ++ nrs=0 +MN5 SN S VSS VSS sg13_lv_nmos m=1 w=480.00n l=130.00n ng=1 nrd=0 nrs=0 +MN3 net13 A1 VSS VSS sg13_lv_nmos m=1 w=480.00n l=130.00n ng=1 nrd=0 ++ nrs=0 +MN2 ZN S net13 VSS sg13_lv_nmos m=1 w=480.00n l=130.00n ng=1 nrd=0 nrs=0 +MN1 net15 A0 VSS VSS sg13_lv_nmos m=1 w=480.00n l=130.00n ng=1 nrd=0 ++ nrs=0 +MN0 ZN SN net15 VSS sg13_lv_nmos m=1 w=480.00n l=130.00n ng=1 nrd=0 nrs=0 +.ENDS +.SUBCKT RM_IHPSG13_256x32_c2_1P_DLY_MUX A SEL Z VDD VSS +XI11 net4 Z VDD VSS / RSC_IHPSG13_CINVX2 +XI8 A D<3> SEL net4 VDD VSS / RSC_IHPSG13_MX2IX1 +XI20<3> D<2> D<3> VDD VSS / RSC_IHPSG13_CDLYX1 +XI20<2> D<1> D<2> VDD VSS / RSC_IHPSG13_CDLYX1 +XI20<1> A D<1> VDD VSS / RSC_IHPSG13_CDLYX1 +.ENDS +.SUBCKT RSC_IHPSG13_DFNQX2 CN D Q VDD VSS +MN0 Q QIN_SL VSS VSS sg13_lv_nmos m=1 w=980.00n l=130.00n ng=1 nrd=0 ++ nrs=0 +MN10 QIN_SL CNN net21 VSS sg13_lv_nmos m=1 w=850.00n l=130.00n ng=1 nrd=0 ++ nrs=0 +MN11 net21 QI_MS VSS VSS sg13_lv_nmos m=1 w=850.00n l=130.00n ng=1 ++ nrd=0 nrs=0 +MN7 net30 QI_MS VSS VSS sg13_lv_nmos m=1 w=480.00n l=130.00n ng=1 ++ nrd=0 nrs=0 +MN6 QIN_MS CNN net30 VSS sg13_lv_nmos m=1 w=480.00n l=130.00n ng=1 nrd=0 ++ nrs=0 +MN3 QI_MS QIN_MS VSS VSS sg13_lv_nmos m=1 w=480.00n l=130.00n ng=1 ++ nrd=0 nrs=0 +MN12 CNN CN VSS VSS sg13_lv_nmos m=1 w=495.000n l=130.00n ng=1 nrd=0 ++ nrs=0 +MN9 net37 D VSS VSS sg13_lv_nmos m=1 w=870.00n l=130.00n ng=1 nrd=0 ++ nrs=0 +MN8 QIN_MS CN net37 VSS sg13_lv_nmos m=1 w=870.00n l=130.00n ng=1 nrd=0 ++ nrs=0 +MN5 QIN_SL CN net25 VSS sg13_lv_nmos m=1 w=480.00n l=130.00n ng=1 nrd=0 ++ nrs=0 +MN4 net25 QI_SL VSS VSS sg13_lv_nmos m=1 w=480.00n l=130.00n ng=1 ++ nrd=0 nrs=0 +MN2 QI_SL QIN_SL VSS VSS sg13_lv_nmos m=1 w=480.00n l=130.00n ng=1 ++ nrd=0 nrs=0 +MP0 Q QIN_SL VDD VDD sg13_lv_pmos m=1 w=1.62u l=130.00n ng=1 nrd=0 ++ nrs=0 +MP6 QI_MS QIN_MS VDD VDD sg13_lv_pmos m=1 w=480.00n l=130.00n ng=1 ++ nrd=0 nrs=0 +MP3 QIN_SL CNN net27 VDD sg13_lv_pmos m=1 w=480.00n l=130.00n ng=1 nrd=0 ++ nrs=0 +MP2 net27 QI_SL VDD VDD sg13_lv_pmos m=1 w=480.00n l=130.00n ng=1 ++ nrd=0 nrs=0 +MP10 net36 D VDD VDD sg13_lv_pmos m=1 w=975.000n l=130.00n ng=1 nrd=0 ++ nrs=0 +MP11 QIN_MS CNN net36 VDD sg13_lv_pmos m=1 w=975.000n l=130.00n ng=1 nrd=0 ++ nrs=0 +MP4 net32 QI_MS VDD VDD sg13_lv_pmos m=1 w=480.00n l=130.00n ng=1 ++ nrd=0 nrs=0 +MP5 QIN_MS CN net32 VDD sg13_lv_pmos m=1 w=480.00n l=130.00n ng=1 nrd=0 ++ nrs=0 +MP7 QI_SL QIN_SL VDD VDD sg13_lv_pmos m=1 w=480.00n l=130.00n ng=1 ++ nrd=0 nrs=0 +MP12 CNN CN VDD VDD sg13_lv_pmos m=1 w=480.00n l=130.00n ng=1 nrd=0 ++ nrs=0 +MP9 QIN_SL CN net19 VDD sg13_lv_pmos m=1 w=990.00n l=130.00n ng=1 nrd=0 ++ nrs=0 +MP8 net19 QI_MS VDD VDD sg13_lv_pmos m=1 w=990.00n l=130.00n ng=1 ++ nrd=0 nrs=0 +.ENDS +.SUBCKT RSC_IHPSG13_CNAND2X2 A B Z VDD VSS +MN0 Z B net6 VSS sg13_lv_nmos m=1 w=980.00n l=130.00n ng=1 nrd=0 nrs=0 +MN1 net6 A VSS VSS sg13_lv_nmos m=1 w=980.00n l=130.00n ng=1 nrd=0 ++ nrs=0 +MP1 Z B VDD VDD sg13_lv_pmos m=1 w=1.62u l=130.00n ng=1 nrd=0 nrs=0 +MP0 Z A VDD VDD sg13_lv_pmos m=1 w=1.62u l=130.00n ng=1 nrd=0 nrs=0 +.ENDS +.SUBCKT RSC_IHPSG13_CGATEPX4 CP E Q VDD VSS +MN1 net08 QIN VSS VSS sg13_lv_nmos m=1 w=480.00n l=130.00n ng=1 nrd=0 ++ nrs=0 +MN2 net019 net08 VSS VSS sg13_lv_nmos m=1 w=480.00n l=130.00n ng=1 ++ nrd=0 nrs=0 +MN3 QIN CP net019 VSS sg13_lv_nmos m=1 w=480.00n l=130.00n ng=1 nrd=0 nrs=0 +MN6 Q net015 VSS VSS sg13_lv_nmos m=1 w=1.41u l=130.00n ng=2 nrd=0 ++ nrs=0 +MN5 net015 net08 net018 VSS sg13_lv_nmos m=1 w=980.00n l=130.00n ng=1 ++ nrd=0 nrs=0 +MN8 QIN CPN net023 VSS sg13_lv_nmos m=1 w=870.00n l=130.00n ng=1 nrd=0 ++ nrs=0 +MN7 net023 E VSS VSS sg13_lv_nmos m=1 w=870.00n l=130.00n ng=1 nrd=0 ++ nrs=0 +MN4 net018 CP VSS VSS sg13_lv_nmos m=1 w=980.00n l=130.00n ng=1 nrd=0 ++ nrs=0 +MN0 CPN CP VSS VSS sg13_lv_nmos m=1 w=500.0n l=130.00n ng=1 nrd=0 nrs=0 +MP3 net08 QIN VDD VDD sg13_lv_pmos m=1 w=480.00n l=130.00n ng=1 nrd=0 ++ nrs=0 +MP2 QIN CPN net017 VDD sg13_lv_pmos m=1 w=480.00n l=130.00n ng=1 nrd=0 ++ nrs=0 +MP1 net017 net08 VDD VDD sg13_lv_pmos m=1 w=480.00n l=130.00n ng=1 ++ nrd=0 nrs=0 +MP0 CPN CP VDD VDD sg13_lv_pmos m=1 w=500.0n l=130.00n ng=1 nrd=0 nrs=0 +MP8 QIN CP net024 VDD sg13_lv_pmos m=1 w=975.000n l=130.00n ng=1 nrd=0 ++ nrs=0 +MP7 net024 E VDD VDD sg13_lv_pmos m=1 w=975.000n l=130.00n ng=1 nrd=0 ++ nrs=0 +MP4 net015 CP VDD VDD sg13_lv_pmos m=1 w=1.27u l=130.00n ng=1 nrd=0 ++ nrs=0 +MP6 Q net015 VDD VDD sg13_lv_pmos m=1 w=3.24u l=130.00n ng=2 nrd=0 ++ nrs=0 +MP5 net015 net08 VDD VDD sg13_lv_pmos m=1 w=1.27u l=130.00n ng=1 nrd=0 ++ nrs=0 +.ENDS +.SUBCKT RSC_IHPSG13_CBUFX8 A Z VDD VSS +MP0 net4 A VDD VDD sg13_lv_pmos m=1 w=3.24u l=130.00n ng=2 nrd=0 nrs=0 +MP1 Z net4 VDD VDD sg13_lv_pmos m=1 w=6.48u l=130.00n ng=4 nrd=0 nrs=0 +MN1 Z net4 VSS VSS sg13_lv_nmos m=1 w=2.82u l=130.00n ng=4 nrd=0 nrs=0 +MN0 net4 A VSS VSS sg13_lv_nmos m=1 w=1.41u l=130.00n ng=2 nrd=0 nrs=0 +.ENDS +.SUBCKT RSC_IHPSG13_CDLYX2 A Z VDD VSS +MN2 net4 A net9 VSS sg13_lv_nmos m=1 w=320.00n l=200.0n ng=1 nrd=0 nrs=0 +MN0 Z net4 VSS VSS sg13_lv_nmos m=1 w=705.000n l=130.00n ng=1 nrd=0 ++ nrs=0 +MN1 net9 A VSS VSS sg13_lv_nmos m=1 w=320.00n l=200.0n ng=1 nrd=0 nrs=0 +MP2 net4 A net10 VDD sg13_lv_pmos m=1 w=1.2u l=200.0n ng=1 nrd=0 nrs=0 +MP1 net10 A VDD VDD sg13_lv_pmos m=1 w=1.2u l=200.0n ng=1 nrd=0 nrs=0 +MP0 Z net4 VDD VDD sg13_lv_pmos m=1 w=1.62u l=130.00n ng=1 nrd=0 nrs=0 +.ENDS +.SUBCKT RSC_IHPSG13_MX2X2 A0 A1 S Z VDD VSS +MP6 Z net010 VDD VDD sg13_lv_pmos m=1 w=1.62u l=130.00n ng=1 nrd=0 ++ nrs=0 +MP4 SN S VDD VDD sg13_lv_pmos m=1 w=645.000n l=130.00n ng=1 nrd=0 nrs=0 +MP3 net010 SN net12 VDD sg13_lv_pmos m=1 w=985.000n l=130.00n ng=1 nrd=0 ++ nrs=0 +MP2 net12 A1 VDD VDD sg13_lv_pmos m=1 w=985.000n l=130.00n ng=1 nrd=0 ++ nrs=0 +MP1 net010 S net17 VDD sg13_lv_pmos m=1 w=985.000n l=130.00n ng=1 nrd=0 ++ nrs=0 +MP0 net17 A0 VDD VDD sg13_lv_pmos m=1 w=985.000n l=130.00n ng=1 nrd=0 ++ nrs=0 +MN6 Z net010 VSS VSS sg13_lv_nmos m=1 w=705.000n l=130.00n ng=1 nrd=0 ++ nrs=0 +MN5 SN S VSS VSS sg13_lv_nmos m=1 w=560.00n l=130.00n ng=1 nrd=0 nrs=0 +MN3 net13 A1 VSS VSS sg13_lv_nmos m=1 w=560.00n l=130.00n ng=1 nrd=0 ++ nrs=0 +MN2 net010 S net13 VSS sg13_lv_nmos m=1 w=560.00n l=130.00n ng=1 nrd=0 ++ nrs=0 +MN1 net15 A0 VSS VSS sg13_lv_nmos m=1 w=560.00n l=130.00n ng=1 nrd=0 ++ nrs=0 +MN0 net010 SN net15 VSS sg13_lv_nmos m=1 w=560.00n l=130.00n ng=1 nrd=0 ++ nrs=0 +.ENDS +.SUBCKT RSC_IHPSG13_AND2X2 A B Z VDD VSS +MN3 Z net6 VSS VSS sg13_lv_nmos m=1 w=980.00n l=130.00n ng=1 nrd=0 ++ nrs=0 +MN4 net9 B VSS VSS sg13_lv_nmos m=1 w=500.0n l=130.00n ng=1 nrd=0 nrs=0 +MN6 net6 A net9 VSS sg13_lv_nmos m=1 w=500.0n l=130.00n ng=1 nrd=0 nrs=0 +MP2 Z net6 VDD VDD sg13_lv_pmos m=1 w=1.62u l=130.00n ng=1 nrd=0 nrs=0 +MP0 net6 B VDD VDD sg13_lv_pmos m=1 w=860.00n l=130.00n ng=1 nrd=0 ++ nrs=0 +MP1 net6 A VDD VDD sg13_lv_pmos m=1 w=860.00n l=130.00n ng=1 nrd=0 ++ nrs=0 +.ENDS +.SUBCKT RSC_IHPSG13_TIEL Z VDD VSS +MN0 Z net2 VSS VSS sg13_lv_nmos m=1 w=480.00n l=130.00n ng=1 nrd=0 ++ nrs=0 +MP0 net2 net2 VDD VDD sg13_lv_pmos m=1 w=480.00n l=130.00n ng=1 nrd=0 ++ nrs=0 +.ENDS +.SUBCKT RSC_IHPSG13_XOR2X2 A B Z VDD VSS +MP8 net012 B net7 VDD sg13_lv_pmos m=1 w=825.000n l=130.00n ng=1 nrd=0 ++ nrs=0 +MP7 net011 net3 net012 VDD sg13_lv_pmos m=1 w=825.000n l=130.00n ng=1 ++ nrd=0 nrs=0 +MP6 Z net012 VDD VDD sg13_lv_pmos m=1 w=1.535u l=130.00n ng=1 nrd=0 ++ nrs=0 +MP2 net7 A VDD VDD sg13_lv_pmos m=1 w=825.000n l=130.00n ng=1 nrd=0 ++ nrs=0 +MP4 net011 net7 VDD VDD sg13_lv_pmos m=1 w=825.000n l=130.00n ng=1 ++ nrd=0 nrs=0 +MP5 net3 B VDD VDD sg13_lv_pmos m=1 w=580.00n l=130.00n ng=1 nrd=0 ++ nrs=0 +MN7 net012 B net011 VSS sg13_lv_nmos m=1 w=555.000n l=130.00n ng=1 nrd=0 ++ nrs=0 +MN6 net7 net3 net012 VSS sg13_lv_nmos m=1 w=555.000n l=130.00n ng=1 nrd=0 ++ nrs=0 +MN5 Z net012 VSS VSS sg13_lv_nmos m=1 w=775.000n l=130.00n ng=1 nrd=0 ++ nrs=0 +MN2 net7 A VSS VSS sg13_lv_nmos m=1 w=555.000n l=130.00n ng=1 nrd=0 ++ nrs=0 +MN4 net3 B VSS VSS sg13_lv_nmos m=1 w=480.00n l=130.00n ng=1 nrd=0 ++ nrs=0 +MN3 net011 net7 VSS VSS sg13_lv_nmos m=1 w=555.000n l=130.00n ng=1 ++ nrd=0 nrs=0 +.ENDS +.SUBCKT RSC_IHPSG13_OA12X1 A B C Z VDD VSS +MN2 net7 C VSS VSS sg13_lv_nmos m=1 w=980.00n l=130.00n ng=1 nrd=0 ++ nrs=0 +MN3 Z net17 VSS VSS sg13_lv_nmos m=1 w=500.0n l=130.00n ng=1 nrd=0 ++ nrs=0 +MN1 net17 B net7 VSS sg13_lv_nmos m=1 w=980.00n l=130.00n ng=1 nrd=0 nrs=0 +MN0 net17 A net7 VSS sg13_lv_nmos m=1 w=980.00n l=130.00n ng=1 nrd=0 nrs=0 +MP0 net24 A VDD VDD sg13_lv_pmos m=1 w=1.62u l=130.00n ng=1 nrd=0 nrs=0 +MP3 Z net17 VDD VDD sg13_lv_pmos m=1 w=905.000n l=130.00n ng=1 nrd=0 ++ nrs=0 +MP1 net17 B net24 VDD sg13_lv_pmos m=1 w=1.62u l=130.00n ng=1 nrd=0 nrs=0 +MP2 net17 C VDD VDD sg13_lv_pmos m=1 w=905.000n l=130.00n ng=1 nrd=0 ++ nrs=0 +.ENDS +.SUBCKT RM_IHPSG13_256x32_c2_1P_CTRL ACLK_N BIST_CK_I BIST_CS_I BIST_EN BIST_RE_I ++ BIST_WE_I B_TIEL_O CK_I CS_I DCLK ECLK PULSE_H PULSE_L PULSE_O RCLK RE_I ++ ROW_CS WCLK WE_I VDD VSS +XI17 ck_regs we col_we VDD VSS / RSC_IHPSG13_DFNQX2 +XI16 ck_regs re col_re VDD VSS / RSC_IHPSG13_DFNQX2 +XI18 ck_regs cs net7 VDD VSS / RSC_IHPSG13_DFNQX2 +XI71 ACLK_N net012 PULSE_O VDD VSS / RSC_IHPSG13_DFNQX2 +XI77 col_we net9 net016 VDD VSS / RSC_IHPSG13_CNAND2X2 +XI76 col_re net9 net018 VDD VSS / RSC_IHPSG13_CNAND2X2 +XI15 ck_dly WEorREandCS aclk VDD VSS / RSC_IHPSG13_CGATEPX4 +XI14 ck WEandCS DCLK VDD VSS / RSC_IHPSG13_CGATEPX4 +XI60 net7 ROW_CS VDD VSS / RSC_IHPSG13_CBUFX8 +XI73 PULSE_O net012 VDD VSS / RSC_IHPSG13_CINVX2 +XI8 net9 net8 VDD VSS / RSC_IHPSG13_CINVX2 +XI64 ck ck_dly VDD VSS / RSC_IHPSG13_CDLYX2 +XI86 CS_I BIST_CS_I BIST_EN cs VDD VSS / RSC_IHPSG13_MX2X2 +XI87 CK_I BIST_CK_I BIST_EN ck VDD VSS / RSC_IHPSG13_MX2X2 +XI85 WE_I BIST_WE_I BIST_EN we VDD VSS / RSC_IHPSG13_MX2X2 +XI84 RE_I BIST_RE_I BIST_EN re VDD VSS / RSC_IHPSG13_MX2X2 +XI22 we cs WEandCS VDD VSS / RSC_IHPSG13_AND2X2 +XBM_TIEL B_TIEL_O VDD VSS / RSC_IHPSG13_TIEL +XI48 ck_dly ck_regs VDD VSS / RSC_IHPSG13_CINVX4 +XI81 net016 WCLK VDD VSS / RSC_IHPSG13_CINVX4 +XI80 net018 RCLK VDD VSS / RSC_IHPSG13_CINVX4 +XI78 net8 net020 VDD VSS / RSC_IHPSG13_CINVX4 +XI6 PULSE_L PULSE_H net9 VDD VSS / RSC_IHPSG13_XOR2X2 +XI79 net020 ECLK VDD VSS / RSC_IHPSG13_CINVX8 +XI63 aclk ACLK_N VDD VSS / RSC_IHPSG13_CINVX8 +XI21 re we cs WEorREandCS VDD VSS / RSC_IHPSG13_OA12X1 +.ENDS +.SUBCKT RM_IHPSG13_256x32_c2_1P_COLDEC2 ACLK_N ADDR<1> ADDR<0> ADDR_COL<1> ADDR_COL<0> ++ ADDR_DEC<7> ADDR_DEC<6> ADDR_DEC<5> ADDR_DEC<4> ADDR_DEC<3> ADDR_DEC<2> ++ ADDR_DEC<1> ADDR_DEC<0> BIST_ADDR<1> BIST_ADDR<0> BIST_EN_I VDD VSS +XI14<5> VDD VSS / RSC_IHPSG13_FILLCAP4 +XI14<4> VDD VSS / RSC_IHPSG13_FILLCAP4 +XI14<3> VDD VSS / RSC_IHPSG13_FILLCAP4 +XI14<2> VDD VSS / RSC_IHPSG13_FILLCAP4 +XI14<1> VDD VSS / RSC_IHPSG13_FILLCAP4 +XDFF<1> BIST_EN_I BIST_ADDR<1> ACLK_N ADDR<1> padr_int<1> net6<0> VDD ++ VSS / RSC_IHPSG13_DFNQMX2IX1 +XDFF<0> BIST_EN_I BIST_ADDR<0> ACLK_N ADDR<0> padr_int<0> net6<1> VDD ++ VSS / RSC_IHPSG13_DFNQMX2IX1 +XI1<3> PADR<1> PADR<0> addr_n<3> VDD VSS / RSC_IHPSG13_NAND2X2 +XI1<2> PADR<1> NADR<0> addr_n<2> VDD VSS / RSC_IHPSG13_NAND2X2 +XI1<1> NADR<1> PADR<0> addr_n<1> VDD VSS / RSC_IHPSG13_NAND2X2 +XI1<0> NADR<1> NADR<0> addr_n<0> VDD VSS / RSC_IHPSG13_NAND2X2 +XI16<37> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI16<36> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI16<35> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI16<34> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI16<33> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI16<32> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI16<31> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI16<30> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI16<29> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI16<28> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI16<27> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI16<26> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI16<25> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI16<24> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI16<23> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI16<22> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI16<21> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI16<20> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI16<19> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI16<18> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI16<17> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI16<16> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI16<15> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI16<14> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI16<13> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI16<12> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI16<11> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI16<10> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI16<9> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI16<8> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI16<7> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI16<6> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI16<5> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI16<4> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI16<3> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI16<2> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI16<1> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI3<1> padr_int<1> NADR<1> VDD VSS / RSC_IHPSG13_INVX2 +XI3<0> padr_int<0> NADR<0> VDD VSS / RSC_IHPSG13_INVX2 +XI13<1> NADR<1> PADR<1> VDD VSS / RSC_IHPSG13_INVX2 +XI13<0> NADR<0> PADR<0> VDD VSS / RSC_IHPSG13_INVX2 +XI2<3> addr_n<3> ADDR_DEC<3> VDD VSS / RSC_IHPSG13_INVX2 +XI2<2> addr_n<2> ADDR_DEC<2> VDD VSS / RSC_IHPSG13_INVX2 +XI2<1> addr_n<1> ADDR_DEC<1> VDD VSS / RSC_IHPSG13_INVX2 +XI2<0> addr_n<0> ADDR_DEC<0> VDD VSS / RSC_IHPSG13_INVX2 +XI15<1> ADDR_COL<1> VDD VSS / RSC_IHPSG13_TIEL +XI15<0> ADDR_COL<0> VDD VSS / RSC_IHPSG13_TIEL +XI17<3> ADDR_DEC<7> VDD VSS / RSC_IHPSG13_TIEL +XI17<2> ADDR_DEC<6> VDD VSS / RSC_IHPSG13_TIEL +XI17<1> ADDR_DEC<5> VDD VSS / RSC_IHPSG13_TIEL +XI17<0> ADDR_DEC<4> VDD VSS / RSC_IHPSG13_TIEL +.ENDS +.SUBCKT RSC_IHPSG13_NOR2X2 A B Z VDD VSS +MP1 Z B net9 VDD sg13_lv_pmos m=1 w=1.62u l=130.00n ng=1 nrd=0 nrs=0 +MP0 net9 A VDD VDD sg13_lv_pmos m=1 w=1.62u l=130.00n ng=1 nrd=0 nrs=0 +MN0 Z B VSS VSS sg13_lv_nmos m=1 w=980.00n l=130.00n ng=1 nrd=0 nrs=0 +MN1 Z A VSS VSS sg13_lv_nmos m=1 w=980.00n l=130.00n ng=1 nrd=0 nrs=0 +.ENDS +.SUBCKT RSC_IHPSG13_CINVX4_WN A Z VDD VSS +MN0 Z A VSS VSS sg13_lv_nmos m=1 w=705.000n l=130.00n ng=1 nrd=0 nrs=0 +MP0 Z A VDD VDD sg13_lv_pmos m=1 w=3.24u l=130.00n ng=2 nrd=0 nrs=0 +.ENDS +.SUBCKT RM_IHPSG13_256x32_c2_1P_BLDRV BLC BLC_SEL BLT BLT_SEL PRE_N SEL_P WR_ONE WR_ZERO ++ VDD VSS +XCDEC SEL_P WR_ZERO BLC_PMOS_DRIVE VDD VSS / RSC_IHPSG13_NAND2X2 +XTDEC SEL_P WR_ONE BLT_PMOS_DRIVE VDD VSS / RSC_IHPSG13_NAND2X2 +MTWN BLT BLT_NMOS_DRIVE VSS VSS sg13_lv_nmos m=1 w=4.82u l=130.00n ++ ng=2 nrd=0 nrs=0 +MCWN BLC BLC_NMOS_DRIVE VSS VSS sg13_lv_nmos m=1 w=4.82u l=130.00n ++ ng=2 nrd=0 nrs=0 +MCWP BLC BLC_PMOS_DRIVE VDD VDD sg13_lv_pmos m=1 w=1.5u l=130.00n ng=1 ++ nrd=0 nrs=0 +MTWP BLT BLT_PMOS_DRIVE VDD VDD sg13_lv_pmos m=1 w=1.5u l=130.00n ng=1 ++ nrd=0 nrs=0 +MTSP BLT_SEL SEL_N BLT VDD sg13_lv_pmos m=1 w=1.5u l=130.00n ng=1 nrd=0 ++ nrs=0 +MTPR BLT PRE_N VDD VDD sg13_lv_pmos m=1 w=3.000u l=130.00n ng=2 nrd=0 ++ nrs=0 +MCSP BLC_SEL SEL_N BLC VDD sg13_lv_pmos m=1 w=1.5u l=130.00n ng=1 nrd=0 ++ nrs=0 +MCPR BLC PRE_N VDD VDD sg13_lv_pmos m=1 w=3.000u l=130.00n ng=2 nrd=0 ++ nrs=0 +XI86 SEL_P SEL_N VDD VSS / RSC_IHPSG13_INVX2 +XTINV BLC_PMOS_DRIVE BLT_NMOS_DRIVE VDD VSS / RSC_IHPSG13_INVX2 +XCINV BLT_PMOS_DRIVE BLC_NMOS_DRIVE VDD VSS / RSC_IHPSG13_INVX2 +.ENDS +.SUBCKT RSC_IHPSG13_TIEH Z VDD VSS +MN0 net2 net2 VSS VSS sg13_lv_nmos m=1 w=480.00n l=130.00n ng=1 nrd=0 ++ nrs=0 +MP0 Z net2 VDD VDD sg13_lv_pmos m=1 w=480.00n l=130.00n ng=1 nrd=0 ++ nrs=0 +.ENDS +.SUBCKT RSC_IHPSG13_MET3RES A B +R0 B A lvsres w=2.6e-07 l=6e-07 +.ENDS +.SUBCKT RSC_IHPSG13_DFPQD_MSAFFX2 CP DN DP QN QP VDD VSS +MN12 SN RN DIFFP VSS sg13_lv_nmos m=1 w=2.4u l=200.0n ng=2 nrd=0 nrs=0 +MN13 TAIL CP VSS VSS sg13_lv_nmos m=1 w=2.4u l=130.00n ng=2 nrd=0 nrs=0 +MN9 DIFFP DP TAIL VSS sg13_lv_nmos m=1 w=2.4u l=200.0n ng=2 nrd=0 nrs=0 +MN10 DIFFN DN TAIL VSS sg13_lv_nmos m=1 w=2.4u l=200.0n ng=2 nrd=0 nrs=0 +MN11 RN SN DIFFN VSS sg13_lv_nmos m=1 w=2.4u l=200.0n ng=2 nrd=0 nrs=0 +MN19 net33 SN VSS VSS sg13_lv_nmos m=1 w=980.00n l=130.00n ng=1 nrd=0 ++ nrs=0 +MN20 QN QP net37 VSS sg13_lv_nmos m=1 w=980.00n l=130.00n ng=1 nrd=0 nrs=0 +MN18 net37 RN VSS VSS sg13_lv_nmos m=1 w=980.00n l=130.00n ng=1 nrd=0 ++ nrs=0 +MN17 QP QN net33 VSS sg13_lv_nmos m=1 w=980.00n l=130.00n ng=1 nrd=0 nrs=0 +MP15 SN RN VDD VDD sg13_lv_pmos m=1 w=800.0n l=130.00n ng=1 nrd=0 nrs=0 +MP16 RN CP VDD VDD sg13_lv_pmos m=1 w=800.0n l=130.00n ng=1 nrd=0 nrs=0 +MP14 DIFFP CP VDD VDD sg13_lv_pmos m=1 w=800.0n l=130.00n ng=1 nrd=0 ++ nrs=0 +MP12 RN SN VDD VDD sg13_lv_pmos m=1 w=800.0n l=130.00n ng=1 nrd=0 nrs=0 +MP13 DIFFN CP VDD VDD sg13_lv_pmos m=1 w=800.0n l=130.00n ng=1 nrd=0 ++ nrs=0 +MP11 SN CP VDD VDD sg13_lv_pmos m=1 w=800.0n l=130.00n ng=1 nrd=0 nrs=0 +MP19 QN QP VDD VDD sg13_lv_pmos m=1 w=900.0n l=130.00n ng=1 nrd=0 nrs=0 +MP20 QP SN VDD VDD sg13_lv_pmos m=1 w=1.8u l=130.00n ng=2 nrd=0 nrs=0 +MP18 QN RN VDD VDD sg13_lv_pmos m=1 w=1.8u l=130.00n ng=2 nrd=0 nrs=0 +MP17 QP QN VDD VDD sg13_lv_pmos m=1 w=900.0n l=130.00n ng=1 nrd=0 nrs=0 +.ENDS +.SUBCKT RSC_IHPSG13_CBUFX2 A Z VDD VSS +MN1 Z net4 VSS VSS sg13_lv_nmos m=1 w=705.000n l=130.00n ng=1 nrd=0 ++ nrs=0 +MN0 net4 A VSS VSS sg13_lv_nmos m=1 w=540.00n l=130.00n ng=1 nrd=0 ++ nrs=0 +MP1 Z net4 VDD VDD sg13_lv_pmos m=1 w=1.62u l=130.00n ng=1 nrd=0 nrs=0 +MP0 net4 A VDD VDD sg13_lv_pmos m=1 w=1.1u l=130.00n ng=1 nrd=0 nrs=0 +.ENDS +.SUBCKT RSC_IHPSG13_INVX4 A Z VDD VSS +MN0 Z A VSS VSS sg13_lv_nmos m=1 w=1.96u l=130.00n ng=2 nrd=0 nrs=0 +MP0 Z A VDD VDD sg13_lv_pmos m=1 w=3.24u l=130.00n ng=2 nrd=0 nrs=0 +.ENDS +.SUBCKT RM_IHPSG13_256x32_c2_1P_COLCTRL2 A_ADDR_DEC<3> A_ADDR_DEC<2> A_ADDR_DEC<1> ++ A_ADDR_DEC<0> A_BIST_BM_I A_BIST_DW_I A_BIST_EN_I A_BLC<3> A_BLC<2> A_BLC<1> ++ A_BLC<0> A_BLT<3> A_BLT<2> A_BLT<1> A_BLT<0> A_BM_I A_DCLK_B_L A_DCLK_B_R ++ A_DCLK_L A_DCLK_R A_DR_O A_DW_I A_RCLK_B_L A_RCLK_B_R A_RCLK_L A_RCLK_R ++ A_TIEH_O A_WCLK_B_L A_WCLK_B_R A_WCLK_L A_WCLK_R VDD VSS +XA_DREG A_BIST_EN_I A_BIST_DW_I A_DCLK_B_L A_DW_I A_DI_R net22 VDD VSS ++ / RSC_IHPSG13_DFNQMX2IX1 +XA_BREG A_BIST_EN_I A_BIST_BM_I A_DCLK_B_L A_BM_I A_BM_R net23 VDD VSS ++ / RSC_IHPSG13_DFNQMX2IX1 +XA_CAPS<5> VDD VSS / RSC_IHPSG13_FILLCAP4 +XA_CAPS<4> VDD VSS / RSC_IHPSG13_FILLCAP4 +XA_CAPS<3> VDD VSS / RSC_IHPSG13_FILLCAP4 +XA_CAPS<2> VDD VSS / RSC_IHPSG13_FILLCAP4 +XA_CAPS<1> VDD VSS / RSC_IHPSG13_FILLCAP4 +XA_I80 A_WCLK_B_R A_RCLK_B_R net21 VDD VSS / RSC_IHPSG13_AND2X2 +XA_I75 A_DI_R A_DO_WRITE_P A_WR_ONE VDD VSS / RSC_IHPSG13_AND2X2 +XA_I76 A_DI_N A_DO_WRITE_P A_WR_ZERO VDD VSS / RSC_IHPSG13_AND2X2 +XA_I44 A_WCLK_B_R A_BM_N A_DO_WRITE_P VDD VSS / RSC_IHPSG13_NOR2X2 +XA_I81 net21 A_PRE_N VDD VSS / RSC_IHPSG13_CINVX4_WN +XA_BLTMUX<3> A_BLC<3> A_BLC_SEL A_BLT<3> A_BLT_SEL A_PRE_N A_ADDR_DEC<3> ++ A_WR_ONE A_WR_ZERO VDD VSS / RM_IHPSG13_256x32_c2_1P_BLDRV +XA_BLTMUX<2> A_BLC<2> A_BLC_SEL A_BLT<2> A_BLT_SEL A_PRE_N A_ADDR_DEC<2> ++ A_WR_ONE A_WR_ZERO VDD VSS / RM_IHPSG13_256x32_c2_1P_BLDRV +XA_BLTMUX<1> A_BLC<1> A_BLC_SEL A_BLT<1> A_BLT_SEL A_PRE_N A_ADDR_DEC<1> ++ A_WR_ONE A_WR_ZERO VDD VSS / RM_IHPSG13_256x32_c2_1P_BLDRV +XA_BLTMUX<0> A_BLC<0> A_BLC_SEL A_BLT<0> A_BLT_SEL A_PRE_N A_ADDR_DEC<0> ++ A_WR_ONE A_WR_ZERO VDD VSS / RM_IHPSG13_256x32_c2_1P_BLDRV +XA_BM_TIEH A_TIEH_O VDD VSS / RSC_IHPSG13_TIEH +XA_I89 A_DCLK_B_L A_DCLK_B_R / RSC_IHPSG13_MET3RES +XA_I88 A_DCLK_L A_DCLK_R / RSC_IHPSG13_MET3RES +XA_I87 A_WCLK_L A_WCLK_R / RSC_IHPSG13_MET3RES +XA_I91 A_RCLK_B_R A_RCLK_B_L / RSC_IHPSG13_MET3RES +XA_R2 A_RCLK_R A_RCLK_L / RSC_IHPSG13_MET3RES +XA_I90 A_WCLK_B_R A_WCLK_B_L / RSC_IHPSG13_MET3RES +XA_ISENSE A_SAE A_BLC_SEL A_BLT_SEL net19 net20 VDD VSS / ++ RSC_IHPSG13_DFPQD_MSAFFX2 +XA_I78 A_RCLK_B_R A_SAE VDD VSS / RSC_IHPSG13_CBUFX2 +XA_I83 A_BM_R A_BM_N VDD VSS / RSC_IHPSG13_INVX2 +XA_I49 A_DI_R A_DI_N VDD VSS / RSC_IHPSG13_INVX2 +XA_I51 net19 A_DR_O VDD VSS / RSC_IHPSG13_INVX4 +XA_I69 A_DCLK_L A_DCLK_B_L VDD VSS / RSC_IHPSG13_CINVX2 +XA_I50 A_WCLK_L A_WCLK_B_R VDD VSS / RSC_IHPSG13_CINVX2 +XA_EBUF A_RCLK_R A_RCLK_B_R VDD VSS / RSC_IHPSG13_CINVX2 +.ENDS +.SUBCKT RM_IHPSG13_256x32_c2_1P_COLDRV13_FILL4 VDD VSS +XI0<9> VDD VSS / RSC_IHPSG13_FILLCAP4 +XI0<8> VDD VSS / RSC_IHPSG13_FILLCAP4 +XI0<7> VDD VSS / RSC_IHPSG13_FILLCAP4 +XI0<6> VDD VSS / RSC_IHPSG13_FILLCAP4 +XI0<5> VDD VSS / RSC_IHPSG13_FILLCAP4 +XI0<4> VDD VSS / RSC_IHPSG13_FILLCAP4 +XI0<3> VDD VSS / RSC_IHPSG13_FILLCAP4 +XI0<2> VDD VSS / RSC_IHPSG13_FILLCAP4 +XI0<1> VDD VSS / RSC_IHPSG13_FILLCAP4 +.ENDS +.SUBCKT RM_IHPSG13_256x32_c2_1P_COLDRV13_FILL4C2 VDD VSS +XI0<2> VDD VSS / RSC_IHPSG13_FILLCAP4 +XI0<1> VDD VSS / RSC_IHPSG13_FILLCAP4 +.ENDS + + +.SUBCKT RM_IHPSG13_256x32_c2_1P_COLDEC4 ACLK_N ADDR<3> ADDR<2> ADDR<1> ADDR<0> ++ ADDR_COL<1> ADDR_COL<0> ADDR_DEC<7> ADDR_DEC<6> ADDR_DEC<5> ADDR_DEC<4> ++ ADDR_DEC<3> ADDR_DEC<2> ADDR_DEC<1> ADDR_DEC<0> BIST_ADDR<3> BIST_ADDR<2> ++ BIST_ADDR<1> BIST_ADDR<0> BIST_EN_I VDD VSS +XI15 ADDR_COL<1> VDD VSS / RSC_IHPSG13_TIEL +XI14 addr_int ADDR_COL<0> VDD VSS / RSC_IHPSG13_CBUFX2 +XDFF<3> BIST_EN_I BIST_ADDR<3> ACLK_N ADDR<3> addr_int net7<0> VDD VSS ++ / RSC_IHPSG13_DFNQMX2IX1 +XDFF<2> BIST_EN_I BIST_ADDR<2> ACLK_N ADDR<2> padr_int<2> net7<1> VDD ++ VSS / RSC_IHPSG13_DFNQMX2IX1 +XDFF<1> BIST_EN_I BIST_ADDR<1> ACLK_N ADDR<1> padr_int<1> net7<2> VDD ++ VSS / RSC_IHPSG13_DFNQMX2IX1 +XDFF<0> BIST_EN_I BIST_ADDR<0> ACLK_N ADDR<0> padr_int<0> net7<3> VDD ++ VSS / RSC_IHPSG13_DFNQMX2IX1 +XI1<7> PADR<0> PADR<1> PADR<2> addr_n<7> VDD VSS / RSC_IHPSG13_NAND3X2 +XI1<6> NADR<0> PADR<1> PADR<2> addr_n<6> VDD VSS / RSC_IHPSG13_NAND3X2 +XI1<5> PADR<0> NADR<1> PADR<2> addr_n<5> VDD VSS / RSC_IHPSG13_NAND3X2 +XI1<4> NADR<0> NADR<1> PADR<2> addr_n<4> VDD VSS / RSC_IHPSG13_NAND3X2 +XI1<3> PADR<0> PADR<1> NADR<2> addr_n<3> VDD VSS / RSC_IHPSG13_NAND3X2 +XI1<2> NADR<0> PADR<1> NADR<2> addr_n<2> VDD VSS / RSC_IHPSG13_NAND3X2 +XI1<1> PADR<0> NADR<1> NADR<2> addr_n<1> VDD VSS / RSC_IHPSG13_NAND3X2 +XI1<0> NADR<0> NADR<1> NADR<2> addr_n<0> VDD VSS / RSC_IHPSG13_NAND3X2 +XI13<2> NADR<2> PADR<2> VDD VSS / RSC_IHPSG13_INVX2 +XI13<1> NADR<1> PADR<1> VDD VSS / RSC_IHPSG13_INVX2 +XI13<0> NADR<0> PADR<0> VDD VSS / RSC_IHPSG13_INVX2 +XI3<2> padr_int<2> NADR<2> VDD VSS / RSC_IHPSG13_INVX2 +XI3<1> padr_int<1> NADR<1> VDD VSS / RSC_IHPSG13_INVX2 +XI3<0> padr_int<0> NADR<0> VDD VSS / RSC_IHPSG13_INVX2 +XI2<7> addr_n<7> ADDR_DEC<7> VDD VSS / RSC_IHPSG13_INVX2 +XI2<6> addr_n<6> ADDR_DEC<6> VDD VSS / RSC_IHPSG13_INVX2 +XI2<5> addr_n<5> ADDR_DEC<5> VDD VSS / RSC_IHPSG13_INVX2 +XI2<4> addr_n<4> ADDR_DEC<4> VDD VSS / RSC_IHPSG13_INVX2 +XI2<3> addr_n<3> ADDR_DEC<3> VDD VSS / RSC_IHPSG13_INVX2 +XI2<2> addr_n<2> ADDR_DEC<2> VDD VSS / RSC_IHPSG13_INVX2 +XI2<1> addr_n<1> ADDR_DEC<1> VDD VSS / RSC_IHPSG13_INVX2 +XI2<0> addr_n<0> ADDR_DEC<0> VDD VSS / RSC_IHPSG13_INVX2 +XI16<3> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI16<2> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI16<1> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI17<2> VDD VSS / RSC_IHPSG13_FILLCAP4 +XI17<1> VDD VSS / RSC_IHPSG13_FILLCAP4 +.ENDS +.SUBCKT RSC_IHPSG13_AND2X4 A B Z VDD VSS +MN3 Z net6 VSS VSS sg13_lv_nmos m=1 w=1.96u l=130.00n ng=2 nrd=0 nrs=0 +MN4 net9 B VSS VSS sg13_lv_nmos m=1 w=500.0n l=130.00n ng=1 nrd=0 nrs=0 +MN6 net6 A net9 VSS sg13_lv_nmos m=1 w=500.0n l=130.00n ng=1 nrd=0 nrs=0 +MP2 Z net6 VDD VDD sg13_lv_pmos m=1 w=3.24u l=130.00n ng=2 nrd=0 nrs=0 +MP0 net6 B VDD VDD sg13_lv_pmos m=1 w=860.00n l=130.00n ng=1 nrd=0 ++ nrs=0 +MP1 net6 A VDD VDD sg13_lv_pmos m=1 w=860.00n l=130.00n ng=1 nrd=0 ++ nrs=0 +.ENDS +.SUBCKT RM_IHPSG13_256x32_c2_1P_COLCTRL4 A_ADDR_COL A_ADDR_DEC<7> A_ADDR_DEC<6> ++ A_ADDR_DEC<5> A_ADDR_DEC<4> A_ADDR_DEC<3> A_ADDR_DEC<2> A_ADDR_DEC<1> ++ A_ADDR_DEC<0> A_BIST_BM_I A_BIST_DW_I A_BIST_EN_I A_BLC<15> A_BLC<14> ++ A_BLC<13> A_BLC<12> A_BLC<11> A_BLC<10> A_BLC<9> A_BLC<8> A_BLC<7> A_BLC<6> ++ A_BLC<5> A_BLC<4> A_BLC<3> A_BLC<2> A_BLC<1> A_BLC<0> A_BLT<15> A_BLT<14> ++ A_BLT<13> A_BLT<12> A_BLT<11> A_BLT<10> A_BLT<9> A_BLT<8> A_BLT<7> A_BLT<6> ++ A_BLT<5> A_BLT<4> A_BLT<3> A_BLT<2> A_BLT<1> A_BLT<0> A_BM_I A_DCLK_B_L ++ A_DCLK_B_R A_DCLK_L A_DCLK_R A_DR_O A_DW_I A_RCLK_B_L A_RCLK_B_R A_RCLK_L ++ A_RCLK_R A_TIEH_O A_WCLK_B_L A_WCLK_B_R A_WCLK_L A_WCLK_R VDD VSS +XA_I80 A_WCLK_B_L A_RCLK_B_L net21 VDD VSS / RSC_IHPSG13_AND2X2 +XA_I76 A_DO_WRITE_P A_DI_N A_WR_ZERO VDD VSS / RSC_IHPSG13_AND2X4 +XA_I75 A_DI_R A_DO_WRITE_P A_WR_ONE VDD VSS / RSC_IHPSG13_AND2X4 +XA_CAPS<8> VDD VSS / RSC_IHPSG13_FILLCAP4 +XA_CAPS<7> VDD VSS / RSC_IHPSG13_FILLCAP4 +XA_CAPS<6> VDD VSS / RSC_IHPSG13_FILLCAP4 +XA_CAPS<5> VDD VSS / RSC_IHPSG13_FILLCAP4 +XA_CAPS<4> VDD VSS / RSC_IHPSG13_FILLCAP4 +XA_CAPS<3> VDD VSS / RSC_IHPSG13_FILLCAP4 +XA_CAPS<2> VDD VSS / RSC_IHPSG13_FILLCAP4 +XA_CAPS<1> VDD VSS / RSC_IHPSG13_FILLCAP4 +XA_I69 A_DCLK_L A_DCLK_B_L VDD VSS / RSC_IHPSG13_CINVX4 +XA_I50 A_WCLK_L A_WCLK_B_L VDD VSS / RSC_IHPSG13_CINVX4 +XA_EBUF A_RCLK_L A_RCLK_B_L VDD VSS / RSC_IHPSG13_CINVX4 +XA_INV<1> A_N0 A_P0 VDD VSS / RSC_IHPSG13_CINVX4 +XA_INV<0> A_ADDR_COL A_N0 VDD VSS / RSC_IHPSG13_CINVX4 +XA_I81<1> net21 A_PRE_N VDD VSS / RSC_IHPSG13_CINVX4_WN +XA_I81<0> net21 A_PRE_N VDD VSS / RSC_IHPSG13_CINVX4_WN +XA_BLTMUX<15> A_BLC<15> A_BLC_SEL A_BLT<15> A_BLT_SEL A_PRE_N A_SEL_P<15> ++ A_WR_ONE A_WR_ZERO VDD VSS / RM_IHPSG13_256x32_c2_1P_BLDRV +XA_BLTMUX<14> A_BLC<14> A_BLC_SEL A_BLT<14> A_BLT_SEL A_PRE_N A_SEL_P<14> ++ A_WR_ONE A_WR_ZERO VDD VSS / RM_IHPSG13_256x32_c2_1P_BLDRV +XA_BLTMUX<13> A_BLC<13> A_BLC_SEL A_BLT<13> A_BLT_SEL A_PRE_N A_SEL_P<13> ++ A_WR_ONE A_WR_ZERO VDD VSS / RM_IHPSG13_256x32_c2_1P_BLDRV +XA_BLTMUX<12> A_BLC<12> A_BLC_SEL A_BLT<12> A_BLT_SEL A_PRE_N A_SEL_P<12> ++ A_WR_ONE A_WR_ZERO VDD VSS / RM_IHPSG13_256x32_c2_1P_BLDRV +XA_BLTMUX<11> A_BLC<11> A_BLC_SEL A_BLT<11> A_BLT_SEL A_PRE_N A_SEL_P<11> ++ A_WR_ONE A_WR_ZERO VDD VSS / RM_IHPSG13_256x32_c2_1P_BLDRV +XA_BLTMUX<10> A_BLC<10> A_BLC_SEL A_BLT<10> A_BLT_SEL A_PRE_N A_SEL_P<10> ++ A_WR_ONE A_WR_ZERO VDD VSS / RM_IHPSG13_256x32_c2_1P_BLDRV +XA_BLTMUX<9> A_BLC<9> A_BLC_SEL A_BLT<9> A_BLT_SEL A_PRE_N A_SEL_P<9> A_WR_ONE ++ A_WR_ZERO VDD VSS / RM_IHPSG13_256x32_c2_1P_BLDRV +XA_BLTMUX<8> A_BLC<8> A_BLC_SEL A_BLT<8> A_BLT_SEL A_PRE_N A_SEL_P<8> A_WR_ONE ++ A_WR_ZERO VDD VSS / RM_IHPSG13_256x32_c2_1P_BLDRV +XA_BLTMUX<7> A_BLC<7> A_BLC_SEL A_BLT<7> A_BLT_SEL A_PRE_N A_SEL_P<7> A_WR_ONE ++ A_WR_ZERO VDD VSS / RM_IHPSG13_256x32_c2_1P_BLDRV +XA_BLTMUX<6> A_BLC<6> A_BLC_SEL A_BLT<6> A_BLT_SEL A_PRE_N A_SEL_P<6> A_WR_ONE ++ A_WR_ZERO VDD VSS / RM_IHPSG13_256x32_c2_1P_BLDRV +XA_BLTMUX<5> A_BLC<5> A_BLC_SEL A_BLT<5> A_BLT_SEL A_PRE_N A_SEL_P<5> A_WR_ONE ++ A_WR_ZERO VDD VSS / RM_IHPSG13_256x32_c2_1P_BLDRV +XA_BLTMUX<4> A_BLC<4> A_BLC_SEL A_BLT<4> A_BLT_SEL A_PRE_N A_SEL_P<4> A_WR_ONE ++ A_WR_ZERO VDD VSS / RM_IHPSG13_256x32_c2_1P_BLDRV +XA_BLTMUX<3> A_BLC<3> A_BLC_SEL A_BLT<3> A_BLT_SEL A_PRE_N A_SEL_P<3> A_WR_ONE ++ A_WR_ZERO VDD VSS / RM_IHPSG13_256x32_c2_1P_BLDRV +XA_BLTMUX<2> A_BLC<2> A_BLC_SEL A_BLT<2> A_BLT_SEL A_PRE_N A_SEL_P<2> A_WR_ONE ++ A_WR_ZERO VDD VSS / RM_IHPSG13_256x32_c2_1P_BLDRV +XA_BLTMUX<1> A_BLC<1> A_BLC_SEL A_BLT<1> A_BLT_SEL A_PRE_N A_SEL_P<1> A_WR_ONE ++ A_WR_ZERO VDD VSS / RM_IHPSG13_256x32_c2_1P_BLDRV +XA_BLTMUX<0> A_BLC<0> A_BLC_SEL A_BLT<0> A_BLT_SEL A_PRE_N A_SEL_P<0> A_WR_ONE ++ A_WR_ZERO VDD VSS / RM_IHPSG13_256x32_c2_1P_BLDRV +XA_R2 A_RCLK_L A_RCLK_R / RSC_IHPSG13_MET3RES +XA_I87 A_WCLK_L A_WCLK_R / RSC_IHPSG13_MET3RES +XA_I88 A_DCLK_L A_DCLK_R / RSC_IHPSG13_MET3RES +XA_I89 A_DCLK_B_L A_DCLK_B_R / RSC_IHPSG13_MET3RES +XA_I90 A_WCLK_B_L A_WCLK_B_R / RSC_IHPSG13_MET3RES +XA_I91 A_RCLK_B_L A_RCLK_B_R / RSC_IHPSG13_MET3RES +XA_ISENSE A_SAE A_BLC_SEL A_BLT_SEL net19 net20 VDD VSS / ++ RSC_IHPSG13_DFPQD_MSAFFX2 +XA_I51 net19 A_DR_O VDD VSS / RSC_IHPSG13_INVX4 +XA_I78 A_RCLK_B_L A_SAE VDD VSS / RSC_IHPSG13_CBUFX2 +XA_DREG A_BIST_EN_I A_BIST_DW_I A_DCLK_B_L A_DW_I A_DI_R net22 VDD VSS ++ / RSC_IHPSG13_DFNQMX2IX1 +XA_BREG A_BIST_EN_I A_BIST_BM_I A_DCLK_B_L A_BM_I A_BM_R net24 VDD VSS ++ / RSC_IHPSG13_DFNQMX2IX1 +XA_DEC3INV<15> net23<0> A_SEL_P<15> VDD VSS / RSC_IHPSG13_INVX2 +XA_DEC3INV<14> net23<1> A_SEL_P<14> VDD VSS / RSC_IHPSG13_INVX2 +XA_DEC3INV<13> net23<2> A_SEL_P<13> VDD VSS / RSC_IHPSG13_INVX2 +XA_DEC3INV<12> net23<3> A_SEL_P<12> VDD VSS / RSC_IHPSG13_INVX2 +XA_DEC3INV<11> net23<4> A_SEL_P<11> VDD VSS / RSC_IHPSG13_INVX2 +XA_DEC3INV<10> net23<5> A_SEL_P<10> VDD VSS / RSC_IHPSG13_INVX2 +XA_DEC3INV<9> net23<6> A_SEL_P<9> VDD VSS / RSC_IHPSG13_INVX2 +XA_DEC3INV<8> net23<7> A_SEL_P<8> VDD VSS / RSC_IHPSG13_INVX2 +XA_DEC3INV<7> net23<8> A_SEL_P<7> VDD VSS / RSC_IHPSG13_INVX2 +XA_DEC3INV<6> net23<9> A_SEL_P<6> VDD VSS / RSC_IHPSG13_INVX2 +XA_DEC3INV<5> net23<10> A_SEL_P<5> VDD VSS / RSC_IHPSG13_INVX2 +XA_DEC3INV<4> net23<11> A_SEL_P<4> VDD VSS / RSC_IHPSG13_INVX2 +XA_DEC3INV<3> net23<12> A_SEL_P<3> VDD VSS / RSC_IHPSG13_INVX2 +XA_DEC3INV<2> net23<13> A_SEL_P<2> VDD VSS / RSC_IHPSG13_INVX2 +XA_DEC3INV<1> net23<14> A_SEL_P<1> VDD VSS / RSC_IHPSG13_INVX2 +XA_DEC3INV<0> net23<15> A_SEL_P<0> VDD VSS / RSC_IHPSG13_INVX2 +XA_I83 A_BM_R A_BM_N VDD VSS / RSC_IHPSG13_INVX2 +XA_I49 A_DI_R A_DI_N VDD VSS / RSC_IHPSG13_INVX2 +XA_I70<4> VDD VSS / RSC_IHPSG13_FILLCAP8 +XA_I70<3> VDD VSS / RSC_IHPSG13_FILLCAP8 +XA_I70<2> VDD VSS / RSC_IHPSG13_FILLCAP8 +XA_I70<1> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI73<14> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI73<13> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI73<12> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI73<11> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI73<10> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI73<9> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI73<8> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI73<7> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI73<6> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI73<5> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI73<4> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI73<3> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI73<2> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI73<1> VDD VSS / RSC_IHPSG13_FILLCAP8 +XA_I44 A_BM_N A_WCLK_B_L A_DO_WRITE_P VDD VSS / RSC_IHPSG13_NOR2X2 +XA_DEC3<15> A_P0 A_ADDR_DEC<7> net23<0> VDD VSS / RSC_IHPSG13_NAND2X2 +XA_DEC3<14> A_P0 A_ADDR_DEC<6> net23<1> VDD VSS / RSC_IHPSG13_NAND2X2 +XA_DEC3<13> A_P0 A_ADDR_DEC<5> net23<2> VDD VSS / RSC_IHPSG13_NAND2X2 +XA_DEC3<12> A_P0 A_ADDR_DEC<4> net23<3> VDD VSS / RSC_IHPSG13_NAND2X2 +XA_DEC3<11> A_P0 A_ADDR_DEC<3> net23<4> VDD VSS / RSC_IHPSG13_NAND2X2 +XA_DEC3<10> A_P0 A_ADDR_DEC<2> net23<5> VDD VSS / RSC_IHPSG13_NAND2X2 +XA_DEC3<9> A_P0 A_ADDR_DEC<1> net23<6> VDD VSS / RSC_IHPSG13_NAND2X2 +XA_DEC3<8> A_P0 A_ADDR_DEC<0> net23<7> VDD VSS / RSC_IHPSG13_NAND2X2 +XA_DEC3<7> A_N0 A_ADDR_DEC<7> net23<8> VDD VSS / RSC_IHPSG13_NAND2X2 +XA_DEC3<6> A_N0 A_ADDR_DEC<6> net23<9> VDD VSS / RSC_IHPSG13_NAND2X2 +XA_DEC3<5> A_N0 A_ADDR_DEC<5> net23<10> VDD VSS / RSC_IHPSG13_NAND2X2 +XA_DEC3<4> A_N0 A_ADDR_DEC<4> net23<11> VDD VSS / RSC_IHPSG13_NAND2X2 +XA_DEC3<3> A_N0 A_ADDR_DEC<3> net23<12> VDD VSS / RSC_IHPSG13_NAND2X2 +XA_DEC3<2> A_N0 A_ADDR_DEC<2> net23<13> VDD VSS / RSC_IHPSG13_NAND2X2 +XA_DEC3<1> A_N0 A_ADDR_DEC<1> net23<14> VDD VSS / RSC_IHPSG13_NAND2X2 +XA_DEC3<0> A_N0 A_ADDR_DEC<0> net23<15> VDD VSS / RSC_IHPSG13_NAND2X2 +XA_BM_TIEH A_TIEH_O VDD VSS / RSC_IHPSG13_TIEH +.ENDS + + +.SUBCKT RM_IHPSG13_256x32_c2_1P_COLDEC3 ACLK_N ADDR<2> ADDR<1> ADDR<0> ADDR_COL<1> ++ ADDR_COL<0> ADDR_DEC<7> ADDR_DEC<6> ADDR_DEC<5> ADDR_DEC<4> ADDR_DEC<3> ++ ADDR_DEC<2> ADDR_DEC<1> ADDR_DEC<0> BIST_ADDR<2> BIST_ADDR<1> BIST_ADDR<0> ++ BIST_EN_I VDD VSS +XI15<1> ADDR_COL<1> VDD VSS / RSC_IHPSG13_TIEL +XI15<0> ADDR_COL<0> VDD VSS / RSC_IHPSG13_TIEL +XI1<7> PADR<0> PADR<1> PADR<2> addr_n<7> VDD VSS / RSC_IHPSG13_NAND3X2 +XI1<6> NADR<0> PADR<1> PADR<2> addr_n<6> VDD VSS / RSC_IHPSG13_NAND3X2 +XI1<5> PADR<0> NADR<1> PADR<2> addr_n<5> VDD VSS / RSC_IHPSG13_NAND3X2 +XI1<4> NADR<0> NADR<1> PADR<2> addr_n<4> VDD VSS / RSC_IHPSG13_NAND3X2 +XI1<3> PADR<0> PADR<1> NADR<2> addr_n<3> VDD VSS / RSC_IHPSG13_NAND3X2 +XI1<2> NADR<0> PADR<1> NADR<2> addr_n<2> VDD VSS / RSC_IHPSG13_NAND3X2 +XI1<1> PADR<0> NADR<1> NADR<2> addr_n<1> VDD VSS / RSC_IHPSG13_NAND3X2 +XI1<0> NADR<0> NADR<1> NADR<2> addr_n<0> VDD VSS / RSC_IHPSG13_NAND3X2 +XDFF<2> BIST_EN_I BIST_ADDR<2> ACLK_N ADDR<2> padr_int<2> net6<0> VDD ++ VSS / RSC_IHPSG13_DFNQMX2IX1 +XDFF<1> BIST_EN_I BIST_ADDR<1> ACLK_N ADDR<1> padr_int<1> net6<1> VDD ++ VSS / RSC_IHPSG13_DFNQMX2IX1 +XDFF<0> BIST_EN_I BIST_ADDR<0> ACLK_N ADDR<0> padr_int<0> net6<2> VDD ++ VSS / RSC_IHPSG13_DFNQMX2IX1 +XI17<2> VDD VSS / RSC_IHPSG13_FILLCAP4 +XI17<1> VDD VSS / RSC_IHPSG13_FILLCAP4 +XI13<2> NADR<2> PADR<2> VDD VSS / RSC_IHPSG13_INVX2 +XI13<1> NADR<1> PADR<1> VDD VSS / RSC_IHPSG13_INVX2 +XI13<0> NADR<0> PADR<0> VDD VSS / RSC_IHPSG13_INVX2 +XI3<2> padr_int<2> NADR<2> VDD VSS / RSC_IHPSG13_INVX2 +XI3<1> padr_int<1> NADR<1> VDD VSS / RSC_IHPSG13_INVX2 +XI3<0> padr_int<0> NADR<0> VDD VSS / RSC_IHPSG13_INVX2 +XI2<7> addr_n<7> ADDR_DEC<7> VDD VSS / RSC_IHPSG13_INVX2 +XI2<6> addr_n<6> ADDR_DEC<6> VDD VSS / RSC_IHPSG13_INVX2 +XI2<5> addr_n<5> ADDR_DEC<5> VDD VSS / RSC_IHPSG13_INVX2 +XI2<4> addr_n<4> ADDR_DEC<4> VDD VSS / RSC_IHPSG13_INVX2 +XI2<3> addr_n<3> ADDR_DEC<3> VDD VSS / RSC_IHPSG13_INVX2 +XI2<2> addr_n<2> ADDR_DEC<2> VDD VSS / RSC_IHPSG13_INVX2 +XI2<1> addr_n<1> ADDR_DEC<1> VDD VSS / RSC_IHPSG13_INVX2 +XI2<0> addr_n<0> ADDR_DEC<0> VDD VSS / RSC_IHPSG13_INVX2 +XI16<6> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI16<5> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI16<4> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI16<3> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI16<2> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI16<1> VDD VSS / RSC_IHPSG13_FILLCAP8 +.ENDS +.SUBCKT RM_IHPSG13_256x32_c2_1P_COLCTRL3 A_ADDR_DEC<7> A_ADDR_DEC<6> A_ADDR_DEC<5> ++ A_ADDR_DEC<4> A_ADDR_DEC<3> A_ADDR_DEC<2> A_ADDR_DEC<1> A_ADDR_DEC<0> ++ A_BIST_BM_I A_BIST_DW_I A_BIST_EN_I A_BLC<7> A_BLC<6> A_BLC<5> A_BLC<4> ++ A_BLC<3> A_BLC<2> A_BLC<1> A_BLC<0> A_BLT<7> A_BLT<6> A_BLT<5> A_BLT<4> ++ A_BLT<3> A_BLT<2> A_BLT<1> A_BLT<0> A_BM_I A_DCLK_B_L A_DCLK_B_R A_DCLK_L ++ A_DCLK_R A_DR_O A_DW_I A_RCLK_B_L A_RCLK_B_R A_RCLK_L A_RCLK_R A_TIEH_O ++ A_WCLK_B_L A_WCLK_B_R A_WCLK_L A_WCLK_R VDD VSS +XA_DREG A_BIST_EN_I A_BIST_DW_I A_DCLK_B_L A_DW_I A_DI_R net22 VDD VSS ++ / RSC_IHPSG13_DFNQMX2IX1 +XA_BREG A_BIST_EN_I A_BIST_BM_I A_DCLK_B_R A_BM_I A_BM_R net23 VDD VSS ++ / RSC_IHPSG13_DFNQMX2IX1 +XA_I70<8> VDD VSS / RSC_IHPSG13_FILLCAP8 +XA_I70<7> VDD VSS / RSC_IHPSG13_FILLCAP8 +XA_I70<6> VDD VSS / RSC_IHPSG13_FILLCAP8 +XA_I70<5> VDD VSS / RSC_IHPSG13_FILLCAP8 +XA_I70<4> VDD VSS / RSC_IHPSG13_FILLCAP8 +XA_I70<3> VDD VSS / RSC_IHPSG13_FILLCAP8 +XA_I70<2> VDD VSS / RSC_IHPSG13_FILLCAP8 +XA_I70<1> VDD VSS / RSC_IHPSG13_FILLCAP8 +XA_I51 net19 A_DR_O VDD VSS / RSC_IHPSG13_INVX4 +XA_I44 A_BM_N A_WCLK_B_R A_DO_WRITE_P VDD VSS / RSC_IHPSG13_NOR2X2 +XA_BM_TIEH A_TIEH_O VDD VSS / RSC_IHPSG13_TIEH +XA_BLTMUX<7> A_BLC<7> A_BLC_SEL A_BLT<7> A_BLT_SEL A_PRE_N A_ADDR_DEC<7> ++ A_WR_ONE A_WR_ZERO VDD VSS / RM_IHPSG13_256x32_c2_1P_BLDRV +XA_BLTMUX<6> A_BLC<6> A_BLC_SEL A_BLT<6> A_BLT_SEL A_PRE_N A_ADDR_DEC<6> ++ A_WR_ONE A_WR_ZERO VDD VSS / RM_IHPSG13_256x32_c2_1P_BLDRV +XA_BLTMUX<5> A_BLC<5> A_BLC_SEL A_BLT<5> A_BLT_SEL A_PRE_N A_ADDR_DEC<5> ++ A_WR_ONE A_WR_ZERO VDD VSS / RM_IHPSG13_256x32_c2_1P_BLDRV +XA_BLTMUX<4> A_BLC<4> A_BLC_SEL A_BLT<4> A_BLT_SEL A_PRE_N A_ADDR_DEC<4> ++ A_WR_ONE A_WR_ZERO VDD VSS / RM_IHPSG13_256x32_c2_1P_BLDRV +XA_BLTMUX<3> A_BLC<3> A_BLC_SEL A_BLT<3> A_BLT_SEL A_PRE_N A_ADDR_DEC<3> ++ A_WR_ONE A_WR_ZERO VDD VSS / RM_IHPSG13_256x32_c2_1P_BLDRV +XA_BLTMUX<2> A_BLC<2> A_BLC_SEL A_BLT<2> A_BLT_SEL A_PRE_N A_ADDR_DEC<2> ++ A_WR_ONE A_WR_ZERO VDD VSS / RM_IHPSG13_256x32_c2_1P_BLDRV +XA_BLTMUX<1> A_BLC<1> A_BLC_SEL A_BLT<1> A_BLT_SEL A_PRE_N A_ADDR_DEC<1> ++ A_WR_ONE A_WR_ZERO VDD VSS / RM_IHPSG13_256x32_c2_1P_BLDRV +XA_BLTMUX<0> A_BLC<0> A_BLC_SEL A_BLT<0> A_BLT_SEL A_PRE_N A_ADDR_DEC<0> ++ A_WR_ONE A_WR_ZERO VDD VSS / RM_IHPSG13_256x32_c2_1P_BLDRV +XA_I49 A_DI_R A_DI_N VDD VSS / RSC_IHPSG13_INVX2 +XA_I83 A_BM_R A_BM_N VDD VSS / RSC_IHPSG13_INVX2 +XA_I69 A_DCLK_L A_DCLK_B_L VDD VSS / RSC_IHPSG13_CINVX2 +XA_I50 A_WCLK_L A_WCLK_B_L VDD VSS / RSC_IHPSG13_CINVX2 +XA_EBUF A_RCLK_L A_RCLK_B_L VDD VSS / RSC_IHPSG13_CINVX2 +XA_I78 A_RCLK_B_L A_SAE VDD VSS / RSC_IHPSG13_CBUFX2 +XA_I88 A_DCLK_L A_DCLK_R / RSC_IHPSG13_MET3RES +XA_I87 A_WCLK_L A_WCLK_R / RSC_IHPSG13_MET3RES +XA_R2 A_RCLK_L A_RCLK_R / RSC_IHPSG13_MET3RES +XA_I91 A_RCLK_B_L A_RCLK_B_R / RSC_IHPSG13_MET3RES +XA_I90 A_WCLK_B_L A_WCLK_B_R / RSC_IHPSG13_MET3RES +XA_I89 A_DCLK_B_L A_DCLK_B_R / RSC_IHPSG13_MET3RES +XA_I80 A_WCLK_B_R A_RCLK_B_R net21 VDD VSS / RSC_IHPSG13_AND2X2 +XA_I76 A_DI_N A_DO_WRITE_P A_WR_ZERO VDD VSS / RSC_IHPSG13_AND2X2 +XA_I75 A_DI_R A_DO_WRITE_P A_WR_ONE VDD VSS / RSC_IHPSG13_AND2X2 +XA_ISENSE A_SAE A_BLC_SEL A_BLT_SEL net19 net20 VDD VSS / ++ RSC_IHPSG13_DFPQD_MSAFFX2 +XA_I81 net21 A_PRE_N VDD VSS / RSC_IHPSG13_CINVX4_WN +XA_CAPS<5> VDD VSS / RSC_IHPSG13_FILLCAP4 +XA_CAPS<4> VDD VSS / RSC_IHPSG13_FILLCAP4 +XA_CAPS<3> VDD VSS / RSC_IHPSG13_FILLCAP4 +XA_CAPS<2> VDD VSS / RSC_IHPSG13_FILLCAP4 +XA_CAPS<1> VDD VSS / RSC_IHPSG13_FILLCAP4 +.ENDS + +.SUBCKT RM_IHPSG13_256x32_c2_2P_BITKIT_16x2_CORNER VDD_CORE VSS +XI16 VDD_CORE VSS VDD_CORE VSS / ++ RM_IHPSG13_256x32_c2_1P_BITKIT_CORNER +.ENDS +.SUBCKT RM_IHPSG13_256x32_c2_2P_BITKIT_EDGE_LR A_WL B_WL NW PW VDD VSS +MN1 VSS A_WL VSS VSS sg13_lv_nmos m=1 w=300.0n l=130.00n ng=1 nrd=0 nrs=0 +MN0 VSS B_WL VSS VSS sg13_lv_nmos m=1 w=300.0n l=130.00n ng=1 nrd=0 nrs=0 +.ENDS +.SUBCKT RM_IHPSG13_256x32_c2_2P_BITKIT_16x2_EDGE_LR A_WL<15> A_WL<14> A_WL<13> A_WL<12> ++ A_WL<11> A_WL<10> A_WL<9> A_WL<8> A_WL<7> A_WL<6> A_WL<5> A_WL<4> A_WL<3> ++ A_WL<2> A_WL<1> A_WL<0> B_WL<15> B_WL<14> B_WL<13> B_WL<12> B_WL<11> ++ B_WL<10> B_WL<9> B_WL<8> B_WL<7> B_WL<6> B_WL<5> B_WL<4> B_WL<3> B_WL<2> ++ B_WL<1> B_WL<0> VDD_CORE VSS +XI0<15> A_WL<15> B_WL<15> VDD_CORE VSS VDD_CORE VSS ++ / RM_IHPSG13_256x32_c2_2P_BITKIT_EDGE_LR +XI0<14> A_WL<14> B_WL<14> VDD_CORE VSS VDD_CORE VSS ++ / RM_IHPSG13_256x32_c2_2P_BITKIT_EDGE_LR +XI0<13> A_WL<13> B_WL<13> VDD_CORE VSS VDD_CORE VSS ++ / RM_IHPSG13_256x32_c2_2P_BITKIT_EDGE_LR +XI0<12> A_WL<12> B_WL<12> VDD_CORE VSS VDD_CORE VSS ++ / RM_IHPSG13_256x32_c2_2P_BITKIT_EDGE_LR +XI0<11> A_WL<11> B_WL<11> VDD_CORE VSS VDD_CORE VSS ++ / RM_IHPSG13_256x32_c2_2P_BITKIT_EDGE_LR +XI0<10> A_WL<10> B_WL<10> VDD_CORE VSS VDD_CORE VSS ++ / RM_IHPSG13_256x32_c2_2P_BITKIT_EDGE_LR +XI0<9> A_WL<9> B_WL<9> VDD_CORE VSS VDD_CORE VSS / ++ RM_IHPSG13_256x32_c2_2P_BITKIT_EDGE_LR +XI0<8> A_WL<8> B_WL<8> VDD_CORE VSS VDD_CORE VSS / ++ RM_IHPSG13_256x32_c2_2P_BITKIT_EDGE_LR +XI0<7> A_WL<7> B_WL<7> VDD_CORE VSS VDD_CORE VSS / ++ RM_IHPSG13_256x32_c2_2P_BITKIT_EDGE_LR +XI0<6> A_WL<6> B_WL<6> VDD_CORE VSS VDD_CORE VSS / ++ RM_IHPSG13_256x32_c2_2P_BITKIT_EDGE_LR +XI0<5> A_WL<5> B_WL<5> VDD_CORE VSS VDD_CORE VSS / ++ RM_IHPSG13_256x32_c2_2P_BITKIT_EDGE_LR +XI0<4> A_WL<4> B_WL<4> VDD_CORE VSS VDD_CORE VSS / ++ RM_IHPSG13_256x32_c2_2P_BITKIT_EDGE_LR +XI0<3> A_WL<3> B_WL<3> VDD_CORE VSS VDD_CORE VSS / ++ RM_IHPSG13_256x32_c2_2P_BITKIT_EDGE_LR +XI0<2> A_WL<2> B_WL<2> VDD_CORE VSS VDD_CORE VSS / ++ RM_IHPSG13_256x32_c2_2P_BITKIT_EDGE_LR +XI0<1> A_WL<1> B_WL<1> VDD_CORE VSS VDD_CORE VSS / ++ RM_IHPSG13_256x32_c2_2P_BITKIT_EDGE_LR +XI0<0> A_WL<0> B_WL<0> VDD_CORE VSS VDD_CORE VSS / ++ RM_IHPSG13_256x32_c2_2P_BITKIT_EDGE_LR +.ENDS +.SUBCKT RM_IHPSG13_256x32_c2_2P_BITKIT_CELL A_BLC_BOT A_BLC_TOP A_BLT_BOT A_BLT_TOP ++ A_LWL A_RWL B_BLC_BOT B_BLC_TOP B_BLT_BOT B_BLT_TOP B_LWL B_RWL NW PW VDD VSS +MN5 NC B_RWL B_BLC_BOT PW sg13_lv_nmos m=1 w=300.0n l=130.00n ng=1 nrd=0 nrs=0 +MN4 B_BLT_BOT B_LWL NT PW sg13_lv_nmos m=1 w=300.0n l=130.00n ng=1 nrd=0 nrs=0 +MN0 NC NT VSS PW sg13_lv_nmos m=1 w=600.0n l=130.00n ng=2 nrd=0 nrs=0 +MN1 NT NC VSS PW sg13_lv_nmos m=1 w=600.0n l=130.00n ng=2 nrd=0 nrs=0 +MN3 NC A_RWL A_BLC_TOP PW sg13_lv_nmos m=1 w=300.0n l=130.00n ng=1 nrd=0 nrs=0 +MN2 A_BLT_TOP A_LWL NT PW sg13_lv_nmos m=1 w=300.0n l=130.00n ng=1 nrd=0 nrs=0 +MP1 NT NC VDD NW sg13_lv_pmos m=1 w=150.00n l=130.00n ng=1 nrd=0 nrs=0 +MP0 NC NT VDD NW sg13_lv_pmos m=1 w=150.00n l=130.00n ng=1 nrd=0 nrs=0 +R5 B_RWL B_LWL lvsres w=2.6e-07 l=6e-07 +R4 B_BLC_BOT B_BLC_TOP lvsres w=2.6e-07 l=6e-07 +R3 B_BLT_BOT B_BLT_TOP lvsres w=2.6e-07 l=6e-07 +R1 A_BLC_BOT A_BLC_TOP lvsres w=2.6e-07 l=6e-07 +R0 A_BLT_BOT A_BLT_TOP lvsres w=2.6e-07 l=6e-07 +R2 A_RWL A_LWL lvsres w=2.6e-07 l=6e-07 +.ENDS +.SUBCKT RM_IHPSG13_256x32_c2_2P_BITKIT_16x2_SRAM A_BLC_BOT<1> A_BLC_BOT<0> A_BLC_TOP<1> ++ A_BLC_TOP<0> A_BLT_BOT<1> A_BLT_BOT<0> A_BLT_TOP<1> A_BLT_TOP<0> A_LWL<15> ++ A_LWL<14> A_LWL<13> A_LWL<12> A_LWL<11> A_LWL<10> A_LWL<9> A_LWL<8> A_LWL<7> ++ A_LWL<6> A_LWL<5> A_LWL<4> A_LWL<3> A_LWL<2> A_LWL<1> A_LWL<0> A_RWL<15> ++ A_RWL<14> A_RWL<13> A_RWL<12> A_RWL<11> A_RWL<10> A_RWL<9> A_RWL<8> A_RWL<7> ++ A_RWL<6> A_RWL<5> A_RWL<4> A_RWL<3> A_RWL<2> A_RWL<1> A_RWL<0> B_BLC_BOT<1> ++ B_BLC_BOT<0> B_BLC_TOP<1> B_BLC_TOP<0> B_BLT_BOT<1> B_BLT_BOT<0> ++ B_BLT_TOP<1> B_BLT_TOP<0> B_LWL<15> B_LWL<14> B_LWL<13> B_LWL<12> B_LWL<11> ++ B_LWL<10> B_LWL<9> B_LWL<8> B_LWL<7> B_LWL<6> B_LWL<5> B_LWL<4> B_LWL<3> ++ B_LWL<2> B_LWL<1> B_LWL<0> B_RWL<15> B_RWL<14> B_RWL<13> B_RWL<12> B_RWL<11> ++ B_RWL<10> B_RWL<9> B_RWL<8> B_RWL<7> B_RWL<6> B_RWL<5> B_RWL<4> B_RWL<3> ++ B_RWL<2> B_RWL<1> B_RWL<0> VDD_CORE VSS +XCELL<31> A_BLC_TOP<1> A_RBLC<15> A_BLT_TOP<1> A_RBLT<15> A_XWL<15> A_RWL<15> ++ B_BLC_TOP<1> B_RBLC<15> B_BLT_TOP<1> B_RBLT<15> B_XWL<15> B_RWL<15> ++ VDD_CORE VSS VDD_CORE VSS / ++ RM_IHPSG13_256x32_c2_2P_BITKIT_CELL +XCELL<30> A_RBLC<14> A_RBLC<15> A_RBLT<14> A_RBLT<15> A_XWL<14> A_RWL<14> ++ B_RBLC<14> B_RBLC<15> B_RBLT<14> B_RBLT<15> B_XWL<14> B_RWL<14> VDD_CORE ++ VSS VDD_CORE VSS / RM_IHPSG13_256x32_c2_2P_BITKIT_CELL +XCELL<29> A_RBLC<14> A_RBLC<13> A_RBLT<14> A_RBLT<13> A_XWL<13> A_RWL<13> ++ B_RBLC<14> B_RBLC<13> B_RBLT<14> B_RBLT<13> B_XWL<13> B_RWL<13> VDD_CORE ++ VSS VDD_CORE VSS / RM_IHPSG13_256x32_c2_2P_BITKIT_CELL +XCELL<28> A_RBLC<12> A_RBLC<13> A_RBLT<12> A_RBLT<13> A_XWL<12> A_RWL<12> ++ B_RBLC<12> B_RBLC<13> B_RBLT<12> B_RBLT<13> B_XWL<12> B_RWL<12> VDD_CORE ++ VSS VDD_CORE VSS / RM_IHPSG13_256x32_c2_2P_BITKIT_CELL +XCELL<27> A_RBLC<12> A_RBLC<11> A_RBLT<12> A_RBLT<11> A_XWL<11> A_RWL<11> ++ B_RBLC<12> B_RBLC<11> B_RBLT<12> B_RBLT<11> B_XWL<11> B_RWL<11> VDD_CORE ++ VSS VDD_CORE VSS / RM_IHPSG13_256x32_c2_2P_BITKIT_CELL +XCELL<26> A_RBLC<10> A_RBLC<11> A_RBLT<10> A_RBLT<11> A_XWL<10> A_RWL<10> ++ B_RBLC<10> B_RBLC<11> B_RBLT<10> B_RBLT<11> B_XWL<10> B_RWL<10> VDD_CORE ++ VSS VDD_CORE VSS / RM_IHPSG13_256x32_c2_2P_BITKIT_CELL +XCELL<25> A_RBLC<10> A_RBLC<9> A_RBLT<10> A_RBLT<9> A_XWL<9> A_RWL<9> ++ B_RBLC<10> B_RBLC<9> B_RBLT<10> B_RBLT<9> B_XWL<9> B_RWL<9> VDD_CORE ++ VSS VDD_CORE VSS / RM_IHPSG13_256x32_c2_2P_BITKIT_CELL +XCELL<24> A_RBLC<8> A_RBLC<9> A_RBLT<8> A_RBLT<9> A_XWL<8> A_RWL<8> B_RBLC<8> ++ B_RBLC<9> B_RBLT<8> B_RBLT<9> B_XWL<8> B_RWL<8> VDD_CORE VSS ++ VDD_CORE VSS / RM_IHPSG13_256x32_c2_2P_BITKIT_CELL +XCELL<23> A_RBLC<8> A_RBLC<7> A_RBLT<8> A_RBLT<7> A_XWL<7> A_RWL<7> B_RBLC<8> ++ B_RBLC<7> B_RBLT<8> B_RBLT<7> B_XWL<7> B_RWL<7> VDD_CORE VSS ++ VDD_CORE VSS / RM_IHPSG13_256x32_c2_2P_BITKIT_CELL +XCELL<22> A_RBLC<6> A_RBLC<7> A_RBLT<6> A_RBLT<7> A_XWL<6> A_RWL<6> B_RBLC<6> ++ B_RBLC<7> B_RBLT<6> B_RBLT<7> B_XWL<6> B_RWL<6> VDD_CORE VSS ++ VDD_CORE VSS / RM_IHPSG13_256x32_c2_2P_BITKIT_CELL +XCELL<21> A_RBLC<6> A_RBLC<5> A_RBLT<6> A_RBLT<5> A_XWL<5> A_RWL<5> B_RBLC<6> ++ B_RBLC<5> B_RBLT<6> B_RBLT<5> B_XWL<5> B_RWL<5> VDD_CORE VSS ++ VDD_CORE VSS / RM_IHPSG13_256x32_c2_2P_BITKIT_CELL +XCELL<20> A_RBLC<4> A_RBLC<5> A_RBLT<4> A_RBLT<5> A_XWL<4> A_RWL<4> B_RBLC<4> ++ B_RBLC<5> B_RBLT<4> B_RBLT<5> B_XWL<4> B_RWL<4> VDD_CORE VSS ++ VDD_CORE VSS / RM_IHPSG13_256x32_c2_2P_BITKIT_CELL +XCELL<19> A_RBLC<4> A_RBLC<3> A_RBLT<4> A_RBLT<3> A_XWL<3> A_RWL<3> B_RBLC<4> ++ B_RBLC<3> B_RBLT<4> B_RBLT<3> B_XWL<3> B_RWL<3> VDD_CORE VSS ++ VDD_CORE VSS / RM_IHPSG13_256x32_c2_2P_BITKIT_CELL +XCELL<18> A_RBLC<2> A_RBLC<3> A_RBLT<2> A_RBLT<3> A_XWL<2> A_RWL<2> B_RBLC<2> ++ B_RBLC<3> B_RBLT<2> B_RBLT<3> B_XWL<2> B_RWL<2> VDD_CORE VSS ++ VDD_CORE VSS / RM_IHPSG13_256x32_c2_2P_BITKIT_CELL +XCELL<17> A_RBLC<2> A_RBLC<1> A_RBLT<2> A_RBLT<1> A_XWL<1> A_RWL<1> B_RBLC<2> ++ B_RBLC<1> B_RBLT<2> B_RBLT<1> B_XWL<1> B_RWL<1> VDD_CORE VSS ++ VDD_CORE VSS / RM_IHPSG13_256x32_c2_2P_BITKIT_CELL +XCELL<16> A_BLC_BOT<1> A_RBLC<1> A_BLT_BOT<1> A_RBLT<1> A_XWL<0> A_RWL<0> ++ B_BLC_BOT<1> B_RBLC<1> B_BLT_BOT<1> B_RBLT<1> B_XWL<0> B_RWL<0> VDD_CORE ++ VSS VDD_CORE VSS / RM_IHPSG13_256x32_c2_2P_BITKIT_CELL +XCELL<15> A_BLC_TOP<0> A_LBLC<15> A_BLT_TOP<0> A_LBLT<15> A_LWL<15> A_XWL<15> ++ B_BLC_TOP<0> B_LBLC<15> B_BLT_TOP<0> B_LBLT<15> B_LWL<15> B_XWL<15> ++ VDD_CORE VSS VDD_CORE VSS / ++ RM_IHPSG13_256x32_c2_2P_BITKIT_CELL +XCELL<14> A_LBLC<14> A_LBLC<15> A_LBLT<14> A_LBLT<15> A_LWL<14> A_XWL<14> ++ B_LBLC<14> B_LBLC<15> B_LBLT<14> B_LBLT<15> B_LWL<14> B_XWL<14> VDD_CORE ++ VSS VDD_CORE VSS / RM_IHPSG13_256x32_c2_2P_BITKIT_CELL +XCELL<13> A_LBLC<14> A_LBLC<13> A_LBLT<14> A_LBLT<13> A_LWL<13> A_XWL<13> ++ B_LBLC<14> B_LBLC<13> B_LBLT<14> B_LBLT<13> B_LWL<13> B_XWL<13> VDD_CORE ++ VSS VDD_CORE VSS / RM_IHPSG13_256x32_c2_2P_BITKIT_CELL +XCELL<12> A_LBLC<12> A_LBLC<13> A_LBLT<12> A_LBLT<13> A_LWL<12> A_XWL<12> ++ B_LBLC<12> B_LBLC<13> B_LBLT<12> B_LBLT<13> B_LWL<12> B_XWL<12> VDD_CORE ++ VSS VDD_CORE VSS / RM_IHPSG13_256x32_c2_2P_BITKIT_CELL +XCELL<11> A_LBLC<12> A_LBLC<11> A_LBLT<12> A_LBLT<11> A_LWL<11> A_XWL<11> ++ B_LBLC<12> B_LBLC<11> B_LBLT<12> B_LBLT<11> B_LWL<11> B_XWL<11> VDD_CORE ++ VSS VDD_CORE VSS / RM_IHPSG13_256x32_c2_2P_BITKIT_CELL +XCELL<10> A_LBLC<10> A_LBLC<11> A_LBLT<10> A_LBLT<11> A_LWL<10> A_XWL<10> ++ B_LBLC<10> B_LBLC<11> B_LBLT<10> B_LBLT<11> B_LWL<10> B_XWL<10> VDD_CORE ++ VSS VDD_CORE VSS / RM_IHPSG13_256x32_c2_2P_BITKIT_CELL +XCELL<9> A_LBLC<10> A_LBLC<9> A_LBLT<10> A_LBLT<9> A_LWL<9> A_XWL<9> ++ B_LBLC<10> B_LBLC<9> B_LBLT<10> B_LBLT<9> B_LWL<9> B_XWL<9> VDD_CORE ++ VSS VDD_CORE VSS / RM_IHPSG13_256x32_c2_2P_BITKIT_CELL +XCELL<8> A_LBLC<8> A_LBLC<9> A_LBLT<8> A_LBLT<9> A_LWL<8> A_XWL<8> B_LBLC<8> ++ B_LBLC<9> B_LBLT<8> B_LBLT<9> B_LWL<8> B_XWL<8> VDD_CORE VSS ++ VDD_CORE VSS / RM_IHPSG13_256x32_c2_2P_BITKIT_CELL +XCELL<7> A_LBLC<8> A_LBLC<7> A_LBLT<8> A_LBLT<7> A_LWL<7> A_XWL<7> B_LBLC<8> ++ B_LBLC<7> B_LBLT<8> B_LBLT<7> B_LWL<7> B_XWL<7> VDD_CORE VSS ++ VDD_CORE VSS / RM_IHPSG13_256x32_c2_2P_BITKIT_CELL +XCELL<6> A_LBLC<6> A_LBLC<7> A_LBLT<6> A_LBLT<7> A_LWL<6> A_XWL<6> B_LBLC<6> ++ B_LBLC<7> B_LBLT<6> B_LBLT<7> B_LWL<6> B_XWL<6> VDD_CORE VSS ++ VDD_CORE VSS / RM_IHPSG13_256x32_c2_2P_BITKIT_CELL +XCELL<5> A_LBLC<6> A_LBLC<5> A_LBLT<6> A_LBLT<5> A_LWL<5> A_XWL<5> B_LBLC<6> ++ B_LBLC<5> B_LBLT<6> B_LBLT<5> B_LWL<5> B_XWL<5> VDD_CORE VSS ++ VDD_CORE VSS / RM_IHPSG13_256x32_c2_2P_BITKIT_CELL +XCELL<4> A_LBLC<4> A_LBLC<5> A_LBLT<4> A_LBLT<5> A_LWL<4> A_XWL<4> B_LBLC<4> ++ B_LBLC<5> B_LBLT<4> B_LBLT<5> B_LWL<4> B_XWL<4> VDD_CORE VSS ++ VDD_CORE VSS / RM_IHPSG13_256x32_c2_2P_BITKIT_CELL +XCELL<3> A_LBLC<4> A_LBLC<3> A_LBLT<4> A_LBLT<3> A_LWL<3> A_XWL<3> B_LBLC<4> ++ B_LBLC<3> B_LBLT<4> B_LBLT<3> B_LWL<3> B_XWL<3> VDD_CORE VSS ++ VDD_CORE VSS / RM_IHPSG13_256x32_c2_2P_BITKIT_CELL +XCELL<2> A_LBLC<2> A_LBLC<3> A_LBLT<2> A_LBLT<3> A_LWL<2> A_XWL<2> B_LBLC<2> ++ B_LBLC<3> B_LBLT<2> B_LBLT<3> B_LWL<2> B_XWL<2> VDD_CORE VSS ++ VDD_CORE VSS / RM_IHPSG13_256x32_c2_2P_BITKIT_CELL +XCELL<1> A_LBLC<2> A_LBLC<1> A_LBLT<2> A_LBLT<1> A_LWL<1> A_XWL<1> B_LBLC<2> ++ B_LBLC<1> B_LBLT<2> B_LBLT<1> B_LWL<1> B_XWL<1> VDD_CORE VSS ++ VDD_CORE VSS / RM_IHPSG13_256x32_c2_2P_BITKIT_CELL +XCELL<0> A_BLC_BOT<0> A_LBLC<1> A_BLT_BOT<0> A_LBLT<1> A_LWL<0> A_XWL<0> ++ B_BLC_BOT<0> B_LBLC<1> B_BLT_BOT<0> B_LBLT<1> B_LWL<0> B_XWL<0> VDD_CORE ++ VSS VDD_CORE VSS / RM_IHPSG13_256x32_c2_2P_BITKIT_CELL +.ENDS +.SUBCKT RM_IHPSG13_256x32_c2_2P_BITKIT_EDGE_TB A_BLC A_BLT B_BLC B_BLT NW PW VDD VSS +.ENDS +.SUBCKT RM_IHPSG13_256x32_c2_2P_BITKIT_16x2_EDGE_TB A_BLC<1> A_BLC<0> A_BLT<1> A_BLT<0> ++ B_BLC<1> B_BLC<0> B_BLT<1> B_BLT<0> VDD_CORE VSS +XEDGE<1> A_BLC<1> A_BLT<1> B_BLC<1> B_BLT<1> VDD_CORE VSS ++ VDD_CORE VSS / RM_IHPSG13_256x32_c2_2P_BITKIT_EDGE_TB +XEDGE<0> A_BLC<0> A_BLT<0> B_BLC<0> B_BLT<0> VDD_CORE VSS ++ VDD_CORE VSS / RM_IHPSG13_256x32_c2_2P_BITKIT_EDGE_TB +.ENDS +.SUBCKT RM_IHPSG13_256x32_c2_2P_BITKIT_TAP A_BLC A_BLT B_BLC B_BLT NW PW VDD VSS +.ENDS +.SUBCKT RM_IHPSG13_256x32_c2_2P_BITKIT_16x2_TAP A_BLC<1> A_BLC<0> A_BLT<1> A_BLT<0> ++ B_BLC<1> B_BLC<0> B_BLT<1> B_BLT<0> VDD_CORE VSS +XIEDGEBP_COL1<1> A_BLC<1> A_BLT<1> B_BLC<1> B_BLT<1> VDD_CORE VSS ++ VDD_CORE VSS / RM_IHPSG13_256x32_c2_2P_BITKIT_EDGE_TB +XIEDGEBP_COL1<0> A_BLC<1> A_BLT<1> B_BLC<1> B_BLT<1> VDD_CORE VSS ++ VDD_CORE VSS / RM_IHPSG13_256x32_c2_2P_BITKIT_EDGE_TB +XIEDGEBP_COL2<1> A_BLC<0> A_BLT<0> B_BLC<0> B_BLT<0> VDD_CORE VSS ++ VDD_CORE VSS / RM_IHPSG13_256x32_c2_2P_BITKIT_EDGE_TB +XIEDGEBP_COL2<0> A_BLC<0> A_BLT<0> B_BLC<0> B_BLT<0> VDD_CORE VSS ++ VDD_CORE VSS / RM_IHPSG13_256x32_c2_2P_BITKIT_EDGE_TB +XITAP<1> A_BLC<1> A_BLT<1> B_BLC<1> B_BLT<1> VDD_CORE VSS ++ VDD_CORE VSS / RM_IHPSG13_256x32_c2_2P_BITKIT_TAP +XITAP<0> A_BLC<0> A_BLT<0> B_BLC<0> B_BLT<0> VDD_CORE VSS ++ VDD_CORE VSS / RM_IHPSG13_256x32_c2_2P_BITKIT_TAP +.ENDS + + +.SUBCKT RM_IHPSG13_256x32_c2_1P_BITKIT_TAP_LR NW PW VDD VSS +.ENDS +.SUBCKT RM_IHPSG13_256x32_c2_2P_BITKIT_16x2_TAP_LR VDD_CORE VSS +XCORNER<1> VDD_CORE VSS VDD_CORE VSS / ++ RM_IHPSG13_256x32_c2_1P_BITKIT_CORNER +XCORNER<0> VDD_CORE VSS VDD_CORE VSS / ++ RM_IHPSG13_256x32_c2_1P_BITKIT_CORNER +XTAP_BORDER VDD_CORE VSS VDD_CORE VSS / ++ RM_IHPSG13_256x32_c2_1P_BITKIT_TAP_LR +.ENDS + +.SUBCKT RSC_IHPSG13_CBUFX12 A Z VDD VSS +MN1 Z net6 VSS VSS sg13_lv_nmos m=1 w=4.23u l=130.00n ng=6 nrd=0 nrs=0 +MN0 net6 A VSS VSS sg13_lv_nmos m=1 w=1.41u l=130.00n ng=2 nrd=0 nrs=0 +MP1 Z net6 VDD VDD sg13_lv_pmos m=1 w=9.72u l=130.00n ng=6 nrd=0 nrs=0 +MP0 net6 A VDD VDD sg13_lv_pmos m=1 w=3.24u l=130.00n ng=2 nrd=0 nrs=0 +.ENDS +.SUBCKT RM_IHPSG13_256x32_c2_2P_COLDRV13X12 ADDR_COL_I<1> ADDR_COL_I<0> ADDR_COL_O<1> ++ ADDR_COL_O<0> ADDR_DEC_I<7> ADDR_DEC_I<6> ADDR_DEC_I<5> ADDR_DEC_I<4> ++ ADDR_DEC_I<3> ADDR_DEC_I<2> ADDR_DEC_I<1> ADDR_DEC_I<0> ADDR_DEC_O<7> ++ ADDR_DEC_O<6> ADDR_DEC_O<5> ADDR_DEC_O<4> ADDR_DEC_O<3> ADDR_DEC_O<2> ++ ADDR_DEC_O<1> ADDR_DEC_O<0> DCLK_I DCLK_O RCLK_I RCLK_O WCLK_I WCLK_O ++ VDD VSS +XI1<3> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI1<2> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI1<1> VDD VSS / RSC_IHPSG13_FILLCAP8 +XWCLK_DRV WCLK_I WCLK_O VDD VSS / RSC_IHPSG13_CBUFX12 +XRCLK_DRV RCLK_I RCLK_O VDD VSS / RSC_IHPSG13_CBUFX12 +XDCLK_DRV DCLK_I DCLK_O VDD VSS / RSC_IHPSG13_CBUFX12 +XADDR_COL_DRV<1> ADDR_COL_I<1> ADDR_COL_O<1> VDD VSS / ++ RSC_IHPSG13_CBUFX12 +XADDR_COL_DRV<0> ADDR_COL_I<0> ADDR_COL_O<0> VDD VSS / ++ RSC_IHPSG13_CBUFX12 +XADDR_DEC_DRV<7> ADDR_DEC_I<7> ADDR_DEC_O<7> VDD VSS / ++ RSC_IHPSG13_CBUFX12 +XADDR_DEC_DRV<6> ADDR_DEC_I<6> ADDR_DEC_O<6> VDD VSS / ++ RSC_IHPSG13_CBUFX12 +XADDR_DEC_DRV<5> ADDR_DEC_I<5> ADDR_DEC_O<5> VDD VSS / ++ RSC_IHPSG13_CBUFX12 +XADDR_DEC_DRV<4> ADDR_DEC_I<4> ADDR_DEC_O<4> VDD VSS / ++ RSC_IHPSG13_CBUFX12 +XADDR_DEC_DRV<3> ADDR_DEC_I<3> ADDR_DEC_O<3> VDD VSS / ++ RSC_IHPSG13_CBUFX12 +XADDR_DEC_DRV<2> ADDR_DEC_I<2> ADDR_DEC_O<2> VDD VSS / ++ RSC_IHPSG13_CBUFX12 +XADDR_DEC_DRV<1> ADDR_DEC_I<1> ADDR_DEC_O<1> VDD VSS / ++ RSC_IHPSG13_CBUFX12 +XADDR_DEC_DRV<0> ADDR_DEC_I<0> ADDR_DEC_O<0> VDD VSS / ++ RSC_IHPSG13_CBUFX12 +XI0<6> VDD VSS / RSC_IHPSG13_FILLCAP4 +XI0<5> VDD VSS / RSC_IHPSG13_FILLCAP4 +XI0<4> VDD VSS / RSC_IHPSG13_FILLCAP4 +XI0<3> VDD VSS / RSC_IHPSG13_FILLCAP4 +XI0<2> VDD VSS / RSC_IHPSG13_FILLCAP4 +XI0<1> VDD VSS / RSC_IHPSG13_FILLCAP4 +.ENDS +.SUBCKT RSC_IHPSG13_WLDRVX12 A Z VDD VSS +MN1 Z net6 VSS VSS sg13_lv_nmos m=1 w=1.41u l=130.00n ng=2 nrd=0 nrs=0 +MN0 net6 A VSS VSS sg13_lv_nmos m=1 w=1.8u l=130.00n ng=2 nrd=0 nrs=0 +MP1 Z net6 VDD VDD sg13_lv_pmos m=1 w=9.72u l=130.00n ng=6 nrd=0 nrs=0 +MP0 net6 A VDD VDD sg13_lv_pmos m=1 w=900.0n l=130.00n ng=1 nrd=0 nrs=0 +.ENDS +.SUBCKT RM_IHPSG13_256x32_c2_2P_WLDRV16X12 A<15> A<14> A<13> A<12> A<11> A<10> A<9> A<8> ++ A<7> A<6> A<5> A<4> A<3> A<2> A<1> A<0> Z<15> Z<14> Z<13> Z<12> Z<11> Z<10> ++ Z<9> Z<8> Z<7> Z<6> Z<5> Z<4> Z<3> Z<2> Z<1> Z<0> VDD VSS +XBUF<15> A<15> Z<15> VDD VSS / RSC_IHPSG13_WLDRVX12 +XBUF<14> A<14> Z<14> VDD VSS / RSC_IHPSG13_WLDRVX12 +XBUF<13> A<13> Z<13> VDD VSS / RSC_IHPSG13_WLDRVX12 +XBUF<12> A<12> Z<12> VDD VSS / RSC_IHPSG13_WLDRVX12 +XBUF<11> A<11> Z<11> VDD VSS / RSC_IHPSG13_WLDRVX12 +XBUF<10> A<10> Z<10> VDD VSS / RSC_IHPSG13_WLDRVX12 +XBUF<9> A<9> Z<9> VDD VSS / RSC_IHPSG13_WLDRVX12 +XBUF<8> A<8> Z<8> VDD VSS / RSC_IHPSG13_WLDRVX12 +XBUF<7> A<7> Z<7> VDD VSS / RSC_IHPSG13_WLDRVX12 +XBUF<6> A<6> Z<6> VDD VSS / RSC_IHPSG13_WLDRVX12 +XBUF<5> A<5> Z<5> VDD VSS / RSC_IHPSG13_WLDRVX12 +XBUF<4> A<4> Z<4> VDD VSS / RSC_IHPSG13_WLDRVX12 +XBUF<3> A<3> Z<3> VDD VSS / RSC_IHPSG13_WLDRVX12 +XBUF<2> A<2> Z<2> VDD VSS / RSC_IHPSG13_WLDRVX12 +XBUF<1> A<1> Z<1> VDD VSS / RSC_IHPSG13_WLDRVX12 +XBUF<0> A<0> Z<0> VDD VSS / RSC_IHPSG13_WLDRVX12 +.ENDS +.SUBCKT RM_IHPSG13_256x32_c2_2P_DEC04 ADDR<3> ADDR<2> ADDR<1> ADDR<0> CS ECLK_H_BOT ++ ECLK_H_TOP ECLK_L_BOT ECLK_L_TOP WL<15> WL<14> WL<13> WL<12> WL<11> WL<10> ++ WL<9> WL<8> WL<7> WL<6> WL<5> WL<4> WL<3> WL<2> WL<1> WL<0> VDD VSS +XI0<3> PADR<1> PADR<0> sel01<3> VDD VSS / RSC_IHPSG13_NAND2X2 +XI0<2> PADR<1> NADR<0> sel01<2> VDD VSS / RSC_IHPSG13_NAND2X2 +XI0<1> NADR<1> PADR<0> sel01<1> VDD VSS / RSC_IHPSG13_NAND2X2 +XI0<0> NADR<1> NADR<0> sel01<0> VDD VSS / RSC_IHPSG13_NAND2X2 +XI4 ECLK_L_BOT EN VDD VSS / RSC_IHPSG13_CINVX4 +XI5 ECLK_H_BOT ECLK_L_BOT VDD VSS / RSC_IHPSG13_CINVX2 +XI3<3> PADR<3> NADR<3> VDD VSS / RSC_IHPSG13_INVX2 +XI3<2> PADR<2> NADR<2> VDD VSS / RSC_IHPSG13_INVX2 +XI3<1> PADR<1> NADR<1> VDD VSS / RSC_IHPSG13_INVX2 +XI3<0> PADR<0> NADR<0> VDD VSS / RSC_IHPSG13_INVX2 +XR0 ECLK_H_BOT ECLK_H_TOP / RSC_IHPSG13_MET2RES +XI11 ECLK_L_BOT ECLK_L_TOP / RSC_IHPSG13_MET2RES +XI1<3> PADR<2> PADR<3> CS sel23<3> VDD VSS / RSC_IHPSG13_NAND3X2 +XI1<2> NADR<2> PADR<3> CS sel23<2> VDD VSS / RSC_IHPSG13_NAND3X2 +XI1<1> PADR<2> NADR<3> CS sel23<1> VDD VSS / RSC_IHPSG13_NAND3X2 +XI1<0> NADR<2> NADR<3> CS sel23<0> VDD VSS / RSC_IHPSG13_NAND3X2 +XI2<15> sel23<3> sel01<3> EN WL<15> VDD VSS / RSC_IHPSG13_NOR3X2 +XI2<14> sel23<3> sel01<2> EN WL<14> VDD VSS / RSC_IHPSG13_NOR3X2 +XI2<13> sel23<3> sel01<1> EN WL<13> VDD VSS / RSC_IHPSG13_NOR3X2 +XI2<12> sel23<3> sel01<0> EN WL<12> VDD VSS / RSC_IHPSG13_NOR3X2 +XI2<11> sel23<2> sel01<3> EN WL<11> VDD VSS / RSC_IHPSG13_NOR3X2 +XI2<10> sel23<2> sel01<2> EN WL<10> VDD VSS / RSC_IHPSG13_NOR3X2 +XI2<9> sel23<2> sel01<1> EN WL<9> VDD VSS / RSC_IHPSG13_NOR3X2 +XI2<8> sel23<2> sel01<0> EN WL<8> VDD VSS / RSC_IHPSG13_NOR3X2 +XI2<7> sel23<1> sel01<3> EN WL<7> VDD VSS / RSC_IHPSG13_NOR3X2 +XI2<6> sel23<1> sel01<2> EN WL<6> VDD VSS / RSC_IHPSG13_NOR3X2 +XI2<5> sel23<1> sel01<1> EN WL<5> VDD VSS / RSC_IHPSG13_NOR3X2 +XI2<4> sel23<1> sel01<0> EN WL<4> VDD VSS / RSC_IHPSG13_NOR3X2 +XI2<3> sel23<0> sel01<3> EN WL<3> VDD VSS / RSC_IHPSG13_NOR3X2 +XI2<2> sel23<0> sel01<2> EN WL<2> VDD VSS / RSC_IHPSG13_NOR3X2 +XI2<1> sel23<0> sel01<1> EN WL<1> VDD VSS / RSC_IHPSG13_NOR3X2 +XI2<0> sel23<0> sel01<0> EN WL<0> VDD VSS / RSC_IHPSG13_NOR3X2 +XCAPS4 VDD VSS / RSC_IHPSG13_FILLCAP4 +XLATCH<3> CS ADDR<3> PADR<3> VDD VSS / RSC_IHPSG13_LHPQX2 +XLATCH<2> CS ADDR<2> PADR<2> VDD VSS / RSC_IHPSG13_LHPQX2 +XLATCH<1> CS ADDR<1> PADR<1> VDD VSS / RSC_IHPSG13_LHPQX2 +XLATCH<0> CS ADDR<0> PADR<0> VDD VSS / RSC_IHPSG13_LHPQX2 +.ENDS +.SUBCKT RM_IHPSG13_256x32_c2_2P_DEC02 ADDR<1> ADDR<0> CS CS_OUT VDD VSS +XDEC ADDR<1> NADDR<0> CS net1 VDD VSS / RSC_IHPSG13_NAND3X2 +XADDRINV ADDR<0> NADDR<0> VDD VSS / RSC_IHPSG13_INVX2 +XDECINV net1 CS_OUT VDD VSS / RSC_IHPSG13_INVX4 +XI2<1> VDD VSS / RSC_IHPSG13_FILLCAP4 +XI2<0> VDD VSS / RSC_IHPSG13_FILLCAP4 +.ENDS +.SUBCKT RM_IHPSG13_256x32_c2_2P_DEC01 ADDR<1> ADDR<0> CS CS_OUT VDD VSS +XDEC NADDR<1> ADDR<0> CS net1 VDD VSS / RSC_IHPSG13_NAND3X2 +XADDRINV ADDR<1> NADDR<1> VDD VSS / RSC_IHPSG13_INVX2 +XDECINV net1 CS_OUT VDD VSS / RSC_IHPSG13_INVX4 +XI2<1> VDD VSS / RSC_IHPSG13_FILLCAP4 +XI2<0> VDD VSS / RSC_IHPSG13_FILLCAP4 +.ENDS +.SUBCKT RM_IHPSG13_256x32_c2_2P_DEC00 ADDR<1> ADDR<0> CS CS_OUT VDD VSS +XDEC NADDR<1> NADDR<0> CS net1 VDD VSS / RSC_IHPSG13_NAND3X2 +XADDRINV<1> ADDR<1> NADDR<1> VDD VSS / RSC_IHPSG13_INVX2 +XADDRINV<0> ADDR<0> NADDR<0> VDD VSS / RSC_IHPSG13_INVX2 +XI1<1> VDD VSS / RSC_IHPSG13_FILLCAP4 +XI1<0> VDD VSS / RSC_IHPSG13_FILLCAP4 +XDECINV net1 CS_OUT VDD VSS / RSC_IHPSG13_INVX4 +.ENDS +.SUBCKT RM_IHPSG13_256x32_c2_2P_DEC03 ADDR<1> ADDR<0> CS CS_OUT VDD VSS +XDEC ADDR<1> ADDR<0> CS net1 VDD VSS / RSC_IHPSG13_NAND3X2 +XDECINV net1 CS_OUT VDD VSS / RSC_IHPSG13_INVX4 +XI0<1> VDD VSS / RSC_IHPSG13_FILLCAP4 +XI0<0> VDD VSS / RSC_IHPSG13_FILLCAP4 +.ENDS +.SUBCKT RM_IHPSG13_256x32_c2_2P_ROWDEC9 ADDR_N_I<8> ADDR_N_I<7> ADDR_N_I<6> ADDR_N_I<5> ++ ADDR_N_I<4> ADDR_N_I<3> ADDR_N_I<2> ADDR_N_I<1> ADDR_N_I<0> CS_I ECLK_I ++ WL_O<511> WL_O<510> WL_O<509> WL_O<508> WL_O<507> WL_O<506> WL_O<505> ++ WL_O<504> WL_O<503> WL_O<502> WL_O<501> WL_O<500> WL_O<499> WL_O<498> ++ WL_O<497> WL_O<496> WL_O<495> WL_O<494> WL_O<493> WL_O<492> WL_O<491> ++ WL_O<490> WL_O<489> WL_O<488> WL_O<487> WL_O<486> WL_O<485> WL_O<484> ++ WL_O<483> WL_O<482> WL_O<481> WL_O<480> WL_O<479> WL_O<478> WL_O<477> ++ WL_O<476> WL_O<475> WL_O<474> WL_O<473> WL_O<472> WL_O<471> WL_O<470> ++ WL_O<469> WL_O<468> WL_O<467> WL_O<466> WL_O<465> WL_O<464> WL_O<463> ++ WL_O<462> WL_O<461> WL_O<460> WL_O<459> WL_O<458> WL_O<457> WL_O<456> ++ WL_O<455> WL_O<454> WL_O<453> WL_O<452> WL_O<451> WL_O<450> WL_O<449> ++ WL_O<448> WL_O<447> WL_O<446> WL_O<445> WL_O<444> WL_O<443> WL_O<442> ++ WL_O<441> WL_O<440> WL_O<439> WL_O<438> WL_O<437> WL_O<436> WL_O<435> ++ WL_O<434> WL_O<433> WL_O<432> WL_O<431> WL_O<430> WL_O<429> WL_O<428> ++ WL_O<427> WL_O<426> WL_O<425> WL_O<424> WL_O<423> WL_O<422> WL_O<421> ++ WL_O<420> WL_O<419> WL_O<418> WL_O<417> WL_O<416> WL_O<415> WL_O<414> ++ WL_O<413> WL_O<412> WL_O<411> WL_O<410> WL_O<409> WL_O<408> WL_O<407> ++ WL_O<406> WL_O<405> WL_O<404> WL_O<403> WL_O<402> WL_O<401> WL_O<400> ++ WL_O<399> WL_O<398> WL_O<397> WL_O<396> WL_O<395> WL_O<394> WL_O<393> ++ WL_O<392> WL_O<391> WL_O<390> WL_O<389> WL_O<388> WL_O<387> WL_O<386> ++ WL_O<385> WL_O<384> WL_O<383> WL_O<382> WL_O<381> WL_O<380> WL_O<379> ++ WL_O<378> WL_O<377> WL_O<376> WL_O<375> WL_O<374> WL_O<373> WL_O<372> ++ WL_O<371> WL_O<370> WL_O<369> WL_O<368> WL_O<367> WL_O<366> WL_O<365> ++ WL_O<364> WL_O<363> WL_O<362> WL_O<361> WL_O<360> WL_O<359> WL_O<358> ++ WL_O<357> WL_O<356> WL_O<355> WL_O<354> WL_O<353> WL_O<352> WL_O<351> ++ WL_O<350> WL_O<349> WL_O<348> WL_O<347> WL_O<346> WL_O<345> WL_O<344> ++ WL_O<343> WL_O<342> WL_O<341> WL_O<340> WL_O<339> WL_O<338> WL_O<337> ++ WL_O<336> WL_O<335> WL_O<334> WL_O<333> WL_O<332> WL_O<331> WL_O<330> ++ WL_O<329> WL_O<328> WL_O<327> WL_O<326> WL_O<325> WL_O<324> WL_O<323> ++ WL_O<322> WL_O<321> WL_O<320> WL_O<319> WL_O<318> WL_O<317> WL_O<316> ++ WL_O<315> WL_O<314> WL_O<313> WL_O<312> WL_O<311> WL_O<310> WL_O<309> ++ WL_O<308> WL_O<307> WL_O<306> WL_O<305> WL_O<304> WL_O<303> WL_O<302> ++ WL_O<301> WL_O<300> WL_O<299> WL_O<298> WL_O<297> WL_O<296> WL_O<295> ++ WL_O<294> WL_O<293> WL_O<292> WL_O<291> WL_O<290> WL_O<289> WL_O<288> ++ WL_O<287> WL_O<286> WL_O<285> WL_O<284> WL_O<283> WL_O<282> WL_O<281> ++ WL_O<280> WL_O<279> WL_O<278> WL_O<277> WL_O<276> WL_O<275> WL_O<274> ++ WL_O<273> WL_O<272> WL_O<271> WL_O<270> WL_O<269> WL_O<268> WL_O<267> ++ WL_O<266> WL_O<265> WL_O<264> WL_O<263> WL_O<262> WL_O<261> WL_O<260> ++ WL_O<259> WL_O<258> WL_O<257> WL_O<256> WL_O<255> WL_O<254> WL_O<253> ++ WL_O<252> WL_O<251> WL_O<250> WL_O<249> WL_O<248> WL_O<247> WL_O<246> ++ WL_O<245> WL_O<244> WL_O<243> WL_O<242> WL_O<241> WL_O<240> WL_O<239> ++ WL_O<238> WL_O<237> WL_O<236> WL_O<235> WL_O<234> WL_O<233> WL_O<232> ++ WL_O<231> WL_O<230> WL_O<229> WL_O<228> WL_O<227> WL_O<226> WL_O<225> ++ WL_O<224> WL_O<223> WL_O<222> WL_O<221> WL_O<220> WL_O<219> WL_O<218> ++ WL_O<217> WL_O<216> WL_O<215> WL_O<214> WL_O<213> WL_O<212> WL_O<211> ++ WL_O<210> WL_O<209> WL_O<208> WL_O<207> WL_O<206> WL_O<205> WL_O<204> ++ WL_O<203> WL_O<202> WL_O<201> WL_O<200> WL_O<199> WL_O<198> WL_O<197> ++ WL_O<196> WL_O<195> WL_O<194> WL_O<193> WL_O<192> WL_O<191> WL_O<190> ++ WL_O<189> WL_O<188> WL_O<187> WL_O<186> WL_O<185> WL_O<184> WL_O<183> ++ WL_O<182> WL_O<181> WL_O<180> WL_O<179> WL_O<178> WL_O<177> WL_O<176> ++ WL_O<175> WL_O<174> WL_O<173> WL_O<172> WL_O<171> WL_O<170> WL_O<169> ++ WL_O<168> WL_O<167> WL_O<166> WL_O<165> WL_O<164> WL_O<163> WL_O<162> ++ WL_O<161> WL_O<160> WL_O<159> WL_O<158> WL_O<157> WL_O<156> WL_O<155> ++ WL_O<154> WL_O<153> WL_O<152> WL_O<151> WL_O<150> WL_O<149> WL_O<148> ++ WL_O<147> WL_O<146> WL_O<145> WL_O<144> WL_O<143> WL_O<142> WL_O<141> ++ WL_O<140> WL_O<139> WL_O<138> WL_O<137> WL_O<136> WL_O<135> WL_O<134> ++ WL_O<133> WL_O<132> WL_O<131> WL_O<130> WL_O<129> WL_O<128> WL_O<127> ++ WL_O<126> WL_O<125> WL_O<124> WL_O<123> WL_O<122> WL_O<121> WL_O<120> ++ WL_O<119> WL_O<118> WL_O<117> WL_O<116> WL_O<115> WL_O<114> WL_O<113> ++ WL_O<112> WL_O<111> WL_O<110> WL_O<109> WL_O<108> WL_O<107> WL_O<106> ++ WL_O<105> WL_O<104> WL_O<103> WL_O<102> WL_O<101> WL_O<100> WL_O<99> ++ WL_O<98> WL_O<97> WL_O<96> WL_O<95> WL_O<94> WL_O<93> WL_O<92> WL_O<91> ++ WL_O<90> WL_O<89> WL_O<88> WL_O<87> WL_O<86> WL_O<85> WL_O<84> WL_O<83> ++ WL_O<82> WL_O<81> WL_O<80> WL_O<79> WL_O<78> WL_O<77> WL_O<76> WL_O<75> ++ WL_O<74> WL_O<73> WL_O<72> WL_O<71> WL_O<70> WL_O<69> WL_O<68> WL_O<67> ++ WL_O<66> WL_O<65> WL_O<64> WL_O<63> WL_O<62> WL_O<61> WL_O<60> WL_O<59> ++ WL_O<58> WL_O<57> WL_O<56> WL_O<55> WL_O<54> WL_O<53> WL_O<52> WL_O<51> ++ WL_O<50> WL_O<49> WL_O<48> WL_O<47> WL_O<46> WL_O<45> WL_O<44> WL_O<43> ++ WL_O<42> WL_O<41> WL_O<40> WL_O<39> WL_O<38> WL_O<37> WL_O<36> WL_O<35> ++ WL_O<34> WL_O<33> WL_O<32> WL_O<31> WL_O<30> WL_O<29> WL_O<28> WL_O<27> ++ WL_O<26> WL_O<25> WL_O<24> WL_O<23> WL_O<22> WL_O<21> WL_O<20> WL_O<19> ++ WL_O<18> WL_O<17> WL_O<16> WL_O<15> WL_O<14> WL_O<13> WL_O<12> WL_O<11> ++ WL_O<10> WL_O<9> WL_O<8> WL_O<7> WL_O<6> WL_O<5> WL_O<4> WL_O<3> WL_O<2> ++ WL_O<1> WL_O<0> VDD VSS +XSEL<31> ADDR_N_I<3> ADDR_N_I<2> ADDR_N_I<1> ADDR_N_I<0> CS00<31> ECLK_H<31> ++ ECLK_H<32> ECLK_B<31> ECLK_B<32> WL_O<511> WL_O<510> WL_O<509> WL_O<508> ++ WL_O<507> WL_O<506> WL_O<505> WL_O<504> WL_O<503> WL_O<502> WL_O<501> ++ WL_O<500> WL_O<499> WL_O<498> WL_O<497> WL_O<496> VDD VSS / ++ RM_IHPSG13_256x32_c2_2P_DEC04 +XSEL<30> ADDR_N_I<3> ADDR_N_I<2> ADDR_N_I<1> ADDR_N_I<0> CS00<30> ECLK_H<30> ++ ECLK_H<31> ECLK_B<30> ECLK_B<31> WL_O<495> WL_O<494> WL_O<493> WL_O<492> ++ WL_O<491> WL_O<490> WL_O<489> WL_O<488> WL_O<487> WL_O<486> WL_O<485> ++ WL_O<484> WL_O<483> WL_O<482> WL_O<481> WL_O<480> VDD VSS / ++ RM_IHPSG13_256x32_c2_2P_DEC04 +XSEL<29> ADDR_N_I<3> ADDR_N_I<2> ADDR_N_I<1> ADDR_N_I<0> CS00<29> ECLK_H<29> ++ ECLK_H<30> ECLK_B<29> ECLK_B<30> WL_O<479> WL_O<478> WL_O<477> WL_O<476> ++ WL_O<475> WL_O<474> WL_O<473> WL_O<472> WL_O<471> WL_O<470> WL_O<469> ++ WL_O<468> WL_O<467> WL_O<466> WL_O<465> WL_O<464> VDD VSS / ++ RM_IHPSG13_256x32_c2_2P_DEC04 +XSEL<28> ADDR_N_I<3> ADDR_N_I<2> ADDR_N_I<1> ADDR_N_I<0> CS00<28> ECLK_H<28> ++ ECLK_H<29> ECLK_B<28> ECLK_B<29> WL_O<463> WL_O<462> WL_O<461> WL_O<460> ++ WL_O<459> WL_O<458> WL_O<457> WL_O<456> WL_O<455> WL_O<454> WL_O<453> ++ WL_O<452> WL_O<451> WL_O<450> WL_O<449> WL_O<448> VDD VSS / ++ RM_IHPSG13_256x32_c2_2P_DEC04 +XSEL<27> ADDR_N_I<3> ADDR_N_I<2> ADDR_N_I<1> ADDR_N_I<0> CS00<27> ECLK_H<27> ++ ECLK_H<28> ECLK_B<27> ECLK_B<28> WL_O<447> WL_O<446> WL_O<445> WL_O<444> ++ WL_O<443> WL_O<442> WL_O<441> WL_O<440> WL_O<439> WL_O<438> WL_O<437> ++ WL_O<436> WL_O<435> WL_O<434> WL_O<433> WL_O<432> VDD VSS / ++ RM_IHPSG13_256x32_c2_2P_DEC04 +XSEL<26> ADDR_N_I<3> ADDR_N_I<2> ADDR_N_I<1> ADDR_N_I<0> CS00<26> ECLK_H<26> ++ ECLK_H<27> ECLK_B<26> ECLK_B<27> WL_O<431> WL_O<430> WL_O<429> WL_O<428> ++ WL_O<427> WL_O<426> WL_O<425> WL_O<424> WL_O<423> WL_O<422> WL_O<421> ++ WL_O<420> WL_O<419> WL_O<418> WL_O<417> WL_O<416> VDD VSS / ++ RM_IHPSG13_256x32_c2_2P_DEC04 +XSEL<25> ADDR_N_I<3> ADDR_N_I<2> ADDR_N_I<1> ADDR_N_I<0> CS00<25> ECLK_H<25> ++ ECLK_H<26> ECLK_B<25> ECLK_B<26> WL_O<415> WL_O<414> WL_O<413> WL_O<412> ++ WL_O<411> WL_O<410> WL_O<409> WL_O<408> WL_O<407> WL_O<406> WL_O<405> ++ WL_O<404> WL_O<403> WL_O<402> WL_O<401> WL_O<400> VDD VSS / ++ RM_IHPSG13_256x32_c2_2P_DEC04 +XSEL<24> ADDR_N_I<3> ADDR_N_I<2> ADDR_N_I<1> ADDR_N_I<0> CS00<24> ECLK_H<24> ++ ECLK_H<25> ECLK_B<24> ECLK_B<25> WL_O<399> WL_O<398> WL_O<397> WL_O<396> ++ WL_O<395> WL_O<394> WL_O<393> WL_O<392> WL_O<391> WL_O<390> WL_O<389> ++ WL_O<388> WL_O<387> WL_O<386> WL_O<385> WL_O<384> VDD VSS / ++ RM_IHPSG13_256x32_c2_2P_DEC04 +XSEL<23> ADDR_N_I<3> ADDR_N_I<2> ADDR_N_I<1> ADDR_N_I<0> CS00<23> ECLK_H<23> ++ ECLK_H<24> ECLK_B<23> ECLK_B<24> WL_O<383> WL_O<382> WL_O<381> WL_O<380> ++ WL_O<379> WL_O<378> WL_O<377> WL_O<376> WL_O<375> WL_O<374> WL_O<373> ++ WL_O<372> WL_O<371> WL_O<370> WL_O<369> WL_O<368> VDD VSS / ++ RM_IHPSG13_256x32_c2_2P_DEC04 +XSEL<22> ADDR_N_I<3> ADDR_N_I<2> ADDR_N_I<1> ADDR_N_I<0> CS00<22> ECLK_H<22> ++ ECLK_H<23> ECLK_B<22> ECLK_B<23> WL_O<367> WL_O<366> WL_O<365> WL_O<364> ++ WL_O<363> WL_O<362> WL_O<361> WL_O<360> WL_O<359> WL_O<358> WL_O<357> ++ WL_O<356> WL_O<355> WL_O<354> WL_O<353> WL_O<352> VDD VSS / ++ RM_IHPSG13_256x32_c2_2P_DEC04 +XSEL<21> ADDR_N_I<3> ADDR_N_I<2> ADDR_N_I<1> ADDR_N_I<0> CS00<21> ECLK_H<21> ++ ECLK_H<22> ECLK_B<21> ECLK_B<22> WL_O<351> WL_O<350> WL_O<349> WL_O<348> ++ WL_O<347> WL_O<346> WL_O<345> WL_O<344> WL_O<343> WL_O<342> WL_O<341> ++ WL_O<340> WL_O<339> WL_O<338> WL_O<337> WL_O<336> VDD VSS / ++ RM_IHPSG13_256x32_c2_2P_DEC04 +XSEL<20> ADDR_N_I<3> ADDR_N_I<2> ADDR_N_I<1> ADDR_N_I<0> CS00<20> ECLK_H<20> ++ ECLK_H<21> ECLK_B<20> ECLK_B<21> WL_O<335> WL_O<334> WL_O<333> WL_O<332> ++ WL_O<331> WL_O<330> WL_O<329> WL_O<328> WL_O<327> WL_O<326> WL_O<325> ++ WL_O<324> WL_O<323> WL_O<322> WL_O<321> WL_O<320> VDD VSS / ++ RM_IHPSG13_256x32_c2_2P_DEC04 +XSEL<19> ADDR_N_I<3> ADDR_N_I<2> ADDR_N_I<1> ADDR_N_I<0> CS00<19> ECLK_H<19> ++ ECLK_H<20> ECLK_B<19> ECLK_B<20> WL_O<319> WL_O<318> WL_O<317> WL_O<316> ++ WL_O<315> WL_O<314> WL_O<313> WL_O<312> WL_O<311> WL_O<310> WL_O<309> ++ WL_O<308> WL_O<307> WL_O<306> WL_O<305> WL_O<304> VDD VSS / ++ RM_IHPSG13_256x32_c2_2P_DEC04 +XSEL<18> ADDR_N_I<3> ADDR_N_I<2> ADDR_N_I<1> ADDR_N_I<0> CS00<18> ECLK_H<18> ++ ECLK_H<19> ECLK_B<18> ECLK_B<19> WL_O<303> WL_O<302> WL_O<301> WL_O<300> ++ WL_O<299> WL_O<298> WL_O<297> WL_O<296> WL_O<295> WL_O<294> WL_O<293> ++ WL_O<292> WL_O<291> WL_O<290> WL_O<289> WL_O<288> VDD VSS / ++ RM_IHPSG13_256x32_c2_2P_DEC04 +XSEL<17> ADDR_N_I<3> ADDR_N_I<2> ADDR_N_I<1> ADDR_N_I<0> CS00<17> ECLK_H<17> ++ ECLK_H<18> ECLK_B<17> ECLK_B<18> WL_O<287> WL_O<286> WL_O<285> WL_O<284> ++ WL_O<283> WL_O<282> WL_O<281> WL_O<280> WL_O<279> WL_O<278> WL_O<277> ++ WL_O<276> WL_O<275> WL_O<274> WL_O<273> WL_O<272> VDD VSS / ++ RM_IHPSG13_256x32_c2_2P_DEC04 +XSEL<16> ADDR_N_I<3> ADDR_N_I<2> ADDR_N_I<1> ADDR_N_I<0> CS00<16> ECLK_H<16> ++ ECLK_H<17> ECLK_B<16> ECLK_B<17> WL_O<271> WL_O<270> WL_O<269> WL_O<268> ++ WL_O<267> WL_O<266> WL_O<265> WL_O<264> WL_O<263> WL_O<262> WL_O<261> ++ WL_O<260> WL_O<259> WL_O<258> WL_O<257> WL_O<256> VDD VSS / ++ RM_IHPSG13_256x32_c2_2P_DEC04 +XSEL<15> ADDR_N_I<3> ADDR_N_I<2> ADDR_N_I<1> ADDR_N_I<0> CS00<15> ECLK_H<15> ++ ECLK_H<16> ECLK_B<15> ECLK_B<16> WL_O<255> WL_O<254> WL_O<253> WL_O<252> ++ WL_O<251> WL_O<250> WL_O<249> WL_O<248> WL_O<247> WL_O<246> WL_O<245> ++ WL_O<244> WL_O<243> WL_O<242> WL_O<241> WL_O<240> VDD VSS / ++ RM_IHPSG13_256x32_c2_2P_DEC04 +XSEL<14> ADDR_N_I<3> ADDR_N_I<2> ADDR_N_I<1> ADDR_N_I<0> CS00<14> ECLK_H<14> ++ ECLK_H<15> ECLK_B<14> ECLK_B<15> WL_O<239> WL_O<238> WL_O<237> WL_O<236> ++ WL_O<235> WL_O<234> WL_O<233> WL_O<232> WL_O<231> WL_O<230> WL_O<229> ++ WL_O<228> WL_O<227> WL_O<226> WL_O<225> WL_O<224> VDD VSS / ++ RM_IHPSG13_256x32_c2_2P_DEC04 +XSEL<13> ADDR_N_I<3> ADDR_N_I<2> ADDR_N_I<1> ADDR_N_I<0> CS00<13> ECLK_H<13> ++ ECLK_H<14> ECLK_B<13> ECLK_B<14> WL_O<223> WL_O<222> WL_O<221> WL_O<220> ++ WL_O<219> WL_O<218> WL_O<217> WL_O<216> WL_O<215> WL_O<214> WL_O<213> ++ WL_O<212> WL_O<211> WL_O<210> WL_O<209> WL_O<208> VDD VSS / ++ RM_IHPSG13_256x32_c2_2P_DEC04 +XSEL<12> ADDR_N_I<3> ADDR_N_I<2> ADDR_N_I<1> ADDR_N_I<0> CS00<12> ECLK_H<12> ++ ECLK_H<13> ECLK_B<12> ECLK_B<13> WL_O<207> WL_O<206> WL_O<205> WL_O<204> ++ WL_O<203> WL_O<202> WL_O<201> WL_O<200> WL_O<199> WL_O<198> WL_O<197> ++ WL_O<196> WL_O<195> WL_O<194> WL_O<193> WL_O<192> VDD VSS / ++ RM_IHPSG13_256x32_c2_2P_DEC04 +XSEL<11> ADDR_N_I<3> ADDR_N_I<2> ADDR_N_I<1> ADDR_N_I<0> CS00<11> ECLK_H<11> ++ ECLK_H<12> ECLK_B<11> ECLK_B<12> WL_O<191> WL_O<190> WL_O<189> WL_O<188> ++ WL_O<187> WL_O<186> WL_O<185> WL_O<184> WL_O<183> WL_O<182> WL_O<181> ++ WL_O<180> WL_O<179> WL_O<178> WL_O<177> WL_O<176> VDD VSS / ++ RM_IHPSG13_256x32_c2_2P_DEC04 +XSEL<10> ADDR_N_I<3> ADDR_N_I<2> ADDR_N_I<1> ADDR_N_I<0> CS00<10> ECLK_H<10> ++ ECLK_H<11> ECLK_B<10> ECLK_B<11> WL_O<175> WL_O<174> WL_O<173> WL_O<172> ++ WL_O<171> WL_O<170> WL_O<169> WL_O<168> WL_O<167> WL_O<166> WL_O<165> ++ WL_O<164> WL_O<163> WL_O<162> WL_O<161> WL_O<160> VDD VSS / ++ RM_IHPSG13_256x32_c2_2P_DEC04 +XSEL<9> ADDR_N_I<3> ADDR_N_I<2> ADDR_N_I<1> ADDR_N_I<0> CS00<9> ECLK_H<9> ++ ECLK_H<10> ECLK_B<9> ECLK_B<10> WL_O<159> WL_O<158> WL_O<157> WL_O<156> ++ WL_O<155> WL_O<154> WL_O<153> WL_O<152> WL_O<151> WL_O<150> WL_O<149> ++ WL_O<148> WL_O<147> WL_O<146> WL_O<145> WL_O<144> VDD VSS / ++ RM_IHPSG13_256x32_c2_2P_DEC04 +XSEL<8> ADDR_N_I<3> ADDR_N_I<2> ADDR_N_I<1> ADDR_N_I<0> CS00<8> ECLK_H<8> ++ ECLK_H<9> ECLK_B<8> ECLK_B<9> WL_O<143> WL_O<142> WL_O<141> WL_O<140> ++ WL_O<139> WL_O<138> WL_O<137> WL_O<136> WL_O<135> WL_O<134> WL_O<133> ++ WL_O<132> WL_O<131> WL_O<130> WL_O<129> WL_O<128> VDD VSS / ++ RM_IHPSG13_256x32_c2_2P_DEC04 +XSEL<7> ADDR_N_I<3> ADDR_N_I<2> ADDR_N_I<1> ADDR_N_I<0> CS00<7> ECLK_H<7> ++ ECLK_H<8> ECLK_B<7> ECLK_B<8> WL_O<127> WL_O<126> WL_O<125> WL_O<124> ++ WL_O<123> WL_O<122> WL_O<121> WL_O<120> WL_O<119> WL_O<118> WL_O<117> ++ WL_O<116> WL_O<115> WL_O<114> WL_O<113> WL_O<112> VDD VSS / ++ RM_IHPSG13_256x32_c2_2P_DEC04 +XSEL<6> ADDR_N_I<3> ADDR_N_I<2> ADDR_N_I<1> ADDR_N_I<0> CS00<6> ECLK_H<6> ++ ECLK_H<7> ECLK_B<6> ECLK_B<7> WL_O<111> WL_O<110> WL_O<109> WL_O<108> ++ WL_O<107> WL_O<106> WL_O<105> WL_O<104> WL_O<103> WL_O<102> WL_O<101> ++ WL_O<100> WL_O<99> WL_O<98> WL_O<97> WL_O<96> VDD VSS / ++ RM_IHPSG13_256x32_c2_2P_DEC04 +XSEL<5> ADDR_N_I<3> ADDR_N_I<2> ADDR_N_I<1> ADDR_N_I<0> CS00<5> ECLK_H<5> ++ ECLK_H<6> ECLK_B<5> ECLK_B<6> WL_O<95> WL_O<94> WL_O<93> WL_O<92> WL_O<91> ++ WL_O<90> WL_O<89> WL_O<88> WL_O<87> WL_O<86> WL_O<85> WL_O<84> WL_O<83> ++ WL_O<82> WL_O<81> WL_O<80> VDD VSS / RM_IHPSG13_256x32_c2_2P_DEC04 +XSEL<4> ADDR_N_I<3> ADDR_N_I<2> ADDR_N_I<1> ADDR_N_I<0> CS00<4> ECLK_H<4> ++ ECLK_H<5> ECLK_B<4> ECLK_B<5> WL_O<79> WL_O<78> WL_O<77> WL_O<76> WL_O<75> ++ WL_O<74> WL_O<73> WL_O<72> WL_O<71> WL_O<70> WL_O<69> WL_O<68> WL_O<67> ++ WL_O<66> WL_O<65> WL_O<64> VDD VSS / RM_IHPSG13_256x32_c2_2P_DEC04 +XSEL<3> ADDR_N_I<3> ADDR_N_I<2> ADDR_N_I<1> ADDR_N_I<0> CS00<3> ECLK_H<3> ++ ECLK_H<4> ECLK_B<3> ECLK_B<4> WL_O<63> WL_O<62> WL_O<61> WL_O<60> WL_O<59> ++ WL_O<58> WL_O<57> WL_O<56> WL_O<55> WL_O<54> WL_O<53> WL_O<52> WL_O<51> ++ WL_O<50> WL_O<49> WL_O<48> VDD VSS / RM_IHPSG13_256x32_c2_2P_DEC04 +XSEL<2> ADDR_N_I<3> ADDR_N_I<2> ADDR_N_I<1> ADDR_N_I<0> CS00<2> ECLK_H<2> ++ ECLK_H<3> ECLK_B<2> ECLK_B<3> WL_O<47> WL_O<46> WL_O<45> WL_O<44> WL_O<43> ++ WL_O<42> WL_O<41> WL_O<40> WL_O<39> WL_O<38> WL_O<37> WL_O<36> WL_O<35> ++ WL_O<34> WL_O<33> WL_O<32> VDD VSS / RM_IHPSG13_256x32_c2_2P_DEC04 +XSEL<1> ADDR_N_I<3> ADDR_N_I<2> ADDR_N_I<1> ADDR_N_I<0> CS00<1> ECLK_H<1> ++ ECLK_H<2> ECLK_B<1> ECLK_B<2> WL_O<31> WL_O<30> WL_O<29> WL_O<28> WL_O<27> ++ WL_O<26> WL_O<25> WL_O<24> WL_O<23> WL_O<22> WL_O<21> WL_O<20> WL_O<19> ++ WL_O<18> WL_O<17> WL_O<16> VDD VSS / RM_IHPSG13_256x32_c2_2P_DEC04 +XSEL<0> ADDR_N_I<3> ADDR_N_I<2> ADDR_N_I<1> ADDR_N_I<0> CS00<0> ECLK_I ++ ECLK_H<1> ECLK_B<0> ECLK_B<1> WL_O<15> WL_O<14> WL_O<13> WL_O<12> WL_O<11> ++ WL_O<10> WL_O<9> WL_O<8> WL_O<7> WL_O<6> WL_O<5> WL_O<4> WL_O<3> WL_O<2> ++ WL_O<1> WL_O<0> VDD VSS / RM_IHPSG13_256x32_c2_2P_DEC04 +XDEC10<9> ADDR_N_I<7> ADDR_N_I<6> CS04<1> CS02<6> VDD VSS / ++ RM_IHPSG13_256x32_c2_2P_DEC02 +XDEC10<8> ADDR_N_I<7> ADDR_N_I<6> CS04<0> CS02<2> VDD VSS / ++ RM_IHPSG13_256x32_c2_2P_DEC02 +XDEC10<7> ADDR_N_I<5> ADDR_N_I<4> CS02<7> CS00<30> VDD VSS / ++ RM_IHPSG13_256x32_c2_2P_DEC02 +XDEC10<6> ADDR_N_I<5> ADDR_N_I<4> CS02<6> CS00<26> VDD VSS / ++ RM_IHPSG13_256x32_c2_2P_DEC02 +XDEC10<5> ADDR_N_I<5> ADDR_N_I<4> CS02<5> CS00<22> VDD VSS / ++ RM_IHPSG13_256x32_c2_2P_DEC02 +XDEC10<4> ADDR_N_I<5> ADDR_N_I<4> CS02<4> CS00<18> VDD VSS / ++ RM_IHPSG13_256x32_c2_2P_DEC02 +XDEC10<3> ADDR_N_I<5> ADDR_N_I<4> CS02<3> CS00<14> VDD VSS / ++ RM_IHPSG13_256x32_c2_2P_DEC02 +XDEC10<2> ADDR_N_I<5> ADDR_N_I<4> CS02<2> CS00<10> VDD VSS / ++ RM_IHPSG13_256x32_c2_2P_DEC02 +XDEC10<1> ADDR_N_I<5> ADDR_N_I<4> CS02<1> CS00<6> VDD VSS / ++ RM_IHPSG13_256x32_c2_2P_DEC02 +XDEC10<0> ADDR_N_I<5> ADDR_N_I<4> CS02<0> CS00<2> VDD VSS / ++ RM_IHPSG13_256x32_c2_2P_DEC02 +XDEC01<10> ADDR_N_I<9> ADDR_N_I<8> CS_I CS04<1> VDD VSS / ++ RM_IHPSG13_256x32_c2_2P_DEC01 +XDEC01<9> ADDR_N_I<7> ADDR_N_I<6> CS04<1> CS02<5> VDD VSS / ++ RM_IHPSG13_256x32_c2_2P_DEC01 +XDEC01<8> ADDR_N_I<7> ADDR_N_I<6> CS04<0> CS02<1> VDD VSS / ++ RM_IHPSG13_256x32_c2_2P_DEC01 +XDEC01<7> ADDR_N_I<5> ADDR_N_I<4> CS02<7> CS00<29> VDD VSS / ++ RM_IHPSG13_256x32_c2_2P_DEC01 +XDEC01<6> ADDR_N_I<5> ADDR_N_I<4> CS02<6> CS00<25> VDD VSS / ++ RM_IHPSG13_256x32_c2_2P_DEC01 +XDEC01<5> ADDR_N_I<5> ADDR_N_I<4> CS02<5> CS00<21> VDD VSS / ++ RM_IHPSG13_256x32_c2_2P_DEC01 +XDEC01<4> ADDR_N_I<5> ADDR_N_I<4> CS02<4> CS00<17> VDD VSS / ++ RM_IHPSG13_256x32_c2_2P_DEC01 +XDEC01<3> ADDR_N_I<5> ADDR_N_I<4> CS02<3> CS00<13> VDD VSS / ++ RM_IHPSG13_256x32_c2_2P_DEC01 +XDEC01<2> ADDR_N_I<5> ADDR_N_I<4> CS02<2> CS00<9> VDD VSS / ++ RM_IHPSG13_256x32_c2_2P_DEC01 +XDEC01<1> ADDR_N_I<5> ADDR_N_I<4> CS02<1> CS00<5> VDD VSS / ++ RM_IHPSG13_256x32_c2_2P_DEC01 +XDEC01<0> ADDR_N_I<5> ADDR_N_I<4> CS02<0> CS00<1> VDD VSS / ++ RM_IHPSG13_256x32_c2_2P_DEC01 +XL2<258> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<257> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<256> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<255> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<254> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<253> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<252> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<251> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<250> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<249> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<248> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<247> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<246> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<245> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<244> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<243> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<242> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<241> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<240> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<239> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<238> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<237> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<236> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<235> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<234> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<233> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<232> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<231> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<230> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<229> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<228> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<227> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<226> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<225> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<224> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<223> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<222> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<221> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<220> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<219> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<218> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<217> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<216> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<215> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<214> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<213> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<212> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<211> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<210> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<209> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<208> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<207> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<206> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<205> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<204> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<203> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<202> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<201> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<200> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<199> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<198> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<197> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<196> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<195> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<194> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<193> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<192> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<191> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<190> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<189> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<188> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<187> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<186> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<185> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<184> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<183> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<182> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<181> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<180> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<179> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<178> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<177> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<176> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<175> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<174> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<173> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<172> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<171> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<170> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<169> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<168> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<167> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<166> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<165> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<164> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<163> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<162> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<161> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<160> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<159> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<158> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<157> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<156> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<155> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<154> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<153> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<152> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<151> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<150> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<149> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<148> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<147> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<146> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<145> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<144> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<143> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<142> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<141> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<140> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<139> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<138> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<137> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<136> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<135> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<134> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<133> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<132> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<131> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<130> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<129> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<128> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<127> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<126> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<125> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<124> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<123> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<122> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<121> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<120> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<119> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<118> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<117> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<116> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<115> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<114> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<113> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<112> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<111> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<110> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<109> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<108> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<107> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<106> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<105> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<104> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<103> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<102> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<101> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<100> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<99> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<98> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<97> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<96> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<95> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<94> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<93> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<92> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<91> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<90> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<89> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<88> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<87> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<86> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<85> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<84> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<83> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<82> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<81> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<80> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<79> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<78> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<77> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<76> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<75> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<74> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<73> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<72> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<71> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<70> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<69> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<68> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<67> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<66> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<65> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<64> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<63> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<62> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<61> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<60> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<59> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<58> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<57> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<56> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<55> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<54> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<53> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<52> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<51> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<50> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<49> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<48> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<47> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<46> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<45> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<44> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<43> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<42> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<41> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<40> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<39> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<38> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<37> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<36> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<35> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<34> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<33> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<32> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<31> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<30> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<29> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<28> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<27> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<26> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<25> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<24> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<23> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<22> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<21> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<20> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<19> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<18> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<17> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<16> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<15> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<14> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<13> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<12> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<11> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<10> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<9> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<8> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<7> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<6> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<5> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<4> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<3> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<2> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<1> VDD VSS / RSC_IHPSG13_FILLCAP8 +XDEC00<10> ADDR_N_I<9> ADDR_N_I<8> CS_I CS04<0> VDD VSS / ++ RM_IHPSG13_256x32_c2_2P_DEC00 +XDEC00<9> ADDR_N_I<7> ADDR_N_I<6> CS04<1> CS02<4> VDD VSS / ++ RM_IHPSG13_256x32_c2_2P_DEC00 +XDEC00<8> ADDR_N_I<7> ADDR_N_I<6> CS04<0> CS02<0> VDD VSS / ++ RM_IHPSG13_256x32_c2_2P_DEC00 +XDEC00<7> ADDR_N_I<5> ADDR_N_I<4> CS02<7> CS00<28> VDD VSS / ++ RM_IHPSG13_256x32_c2_2P_DEC00 +XDEC00<6> ADDR_N_I<5> ADDR_N_I<4> CS02<6> CS00<24> VDD VSS / ++ RM_IHPSG13_256x32_c2_2P_DEC00 +XDEC00<5> ADDR_N_I<5> ADDR_N_I<4> CS02<5> CS00<20> VDD VSS / ++ RM_IHPSG13_256x32_c2_2P_DEC00 +XDEC00<4> ADDR_N_I<5> ADDR_N_I<4> CS02<4> CS00<16> VDD VSS / ++ RM_IHPSG13_256x32_c2_2P_DEC00 +XDEC00<3> ADDR_N_I<5> ADDR_N_I<4> CS02<3> CS00<12> VDD VSS / ++ RM_IHPSG13_256x32_c2_2P_DEC00 +XDEC00<2> ADDR_N_I<5> ADDR_N_I<4> CS02<2> CS00<8> VDD VSS / ++ RM_IHPSG13_256x32_c2_2P_DEC00 +XDEC00<1> ADDR_N_I<5> ADDR_N_I<4> CS02<1> CS00<4> VDD VSS / ++ RM_IHPSG13_256x32_c2_2P_DEC00 +XDEC00<0> ADDR_N_I<5> ADDR_N_I<4> CS02<0> CS00<0> VDD VSS / ++ RM_IHPSG13_256x32_c2_2P_DEC00 +XDEC11<9> ADDR_N_I<7> ADDR_N_I<6> CS04<1> CS02<7> VDD VSS / ++ RM_IHPSG13_256x32_c2_2P_DEC03 +XDEC11<8> ADDR_N_I<7> ADDR_N_I<6> CS04<0> CS02<3> VDD VSS / ++ RM_IHPSG13_256x32_c2_2P_DEC03 +XDEC11<7> ADDR_N_I<5> ADDR_N_I<4> CS02<7> CS00<31> VDD VSS / ++ RM_IHPSG13_256x32_c2_2P_DEC03 +XDEC11<6> ADDR_N_I<5> ADDR_N_I<4> CS02<6> CS00<27> VDD VSS / ++ RM_IHPSG13_256x32_c2_2P_DEC03 +XDEC11<5> ADDR_N_I<5> ADDR_N_I<4> CS02<5> CS00<23> VDD VSS / ++ RM_IHPSG13_256x32_c2_2P_DEC03 +XDEC11<4> ADDR_N_I<5> ADDR_N_I<4> CS02<4> CS00<19> VDD VSS / ++ RM_IHPSG13_256x32_c2_2P_DEC03 +XDEC11<3> ADDR_N_I<5> ADDR_N_I<4> CS02<3> CS00<15> VDD VSS / ++ RM_IHPSG13_256x32_c2_2P_DEC03 +XDEC11<2> ADDR_N_I<5> ADDR_N_I<4> CS02<2> CS00<11> VDD VSS / ++ RM_IHPSG13_256x32_c2_2P_DEC03 +XDEC11<1> ADDR_N_I<5> ADDR_N_I<4> CS02<1> CS00<7> VDD VSS / ++ RM_IHPSG13_256x32_c2_2P_DEC03 +XDEC11<0> ADDR_N_I<5> ADDR_N_I<4> CS02<0> CS00<3> VDD VSS / ++ RM_IHPSG13_256x32_c2_2P_DEC03 +XI0 ADDR_N_I<9> VDD VSS / RSC_IHPSG13_TIEL +.ENDS +.SUBCKT RM_IHPSG13_256x32_c2_2P_ROWREG9 ACLK_N_I ADDR_I<8> ADDR_I<7> ADDR_I<6> ADDR_I<5> ++ ADDR_I<4> ADDR_I<3> ADDR_I<2> ADDR_I<1> ADDR_I<0> ADDR_N_O<8> ADDR_N_O<7> ++ ADDR_N_O<6> ADDR_N_O<5> ADDR_N_O<4> ADDR_N_O<3> ADDR_N_O<2> ADDR_N_O<1> ++ ADDR_N_O<0> BIST_ADDR_I<8> BIST_ADDR_I<7> BIST_ADDR_I<6> BIST_ADDR_I<5> ++ BIST_ADDR_I<4> BIST_ADDR_I<3> BIST_ADDR_I<2> BIST_ADDR_I<1> BIST_ADDR_I<0> ++ BIST_EN_I VDD VSS +XDFF<8> BIST_EN_I BIST_ADDR_I<8> ACLK_N_I ADDR_I<8> q_int<8> net04<0> VDD ++ VSS / RSC_IHPSG13_DFNQMX2IX1 +XDFF<7> BIST_EN_I BIST_ADDR_I<7> ACLK_N_I ADDR_I<7> q_int<7> net04<1> VDD ++ VSS / RSC_IHPSG13_DFNQMX2IX1 +XDFF<6> BIST_EN_I BIST_ADDR_I<6> ACLK_N_I ADDR_I<6> q_int<6> net04<2> VDD ++ VSS / RSC_IHPSG13_DFNQMX2IX1 +XDFF<5> BIST_EN_I BIST_ADDR_I<5> ACLK_N_I ADDR_I<5> q_int<5> net04<3> VDD ++ VSS / RSC_IHPSG13_DFNQMX2IX1 +XDFF<4> BIST_EN_I BIST_ADDR_I<4> ACLK_N_I ADDR_I<4> q_int<4> net04<4> VDD ++ VSS / RSC_IHPSG13_DFNQMX2IX1 +XDFF<3> BIST_EN_I BIST_ADDR_I<3> ACLK_N_I ADDR_I<3> q_int<3> net04<5> VDD ++ VSS / RSC_IHPSG13_DFNQMX2IX1 +XDFF<2> BIST_EN_I BIST_ADDR_I<2> ACLK_N_I ADDR_I<2> q_int<2> net04<6> VDD ++ VSS / RSC_IHPSG13_DFNQMX2IX1 +XDFF<1> BIST_EN_I BIST_ADDR_I<1> ACLK_N_I ADDR_I<1> q_int<1> net04<7> VDD ++ VSS / RSC_IHPSG13_DFNQMX2IX1 +XDFF<0> BIST_EN_I BIST_ADDR_I<0> ACLK_N_I ADDR_I<0> q_int<0> net04<8> VDD ++ VSS / RSC_IHPSG13_DFNQMX2IX1 +XDRV<8> qn_int<8> ADDR_N_O<8> VDD VSS / RSC_IHPSG13_CINVX8 +XDRV<7> qn_int<7> ADDR_N_O<7> VDD VSS / RSC_IHPSG13_CINVX8 +XDRV<6> qn_int<6> ADDR_N_O<6> VDD VSS / RSC_IHPSG13_CINVX8 +XDRV<5> qn_int<5> ADDR_N_O<5> VDD VSS / RSC_IHPSG13_CINVX8 +XDRV<4> qn_int<4> ADDR_N_O<4> VDD VSS / RSC_IHPSG13_CINVX8 +XDRV<3> qn_int<3> ADDR_N_O<3> VDD VSS / RSC_IHPSG13_CINVX8 +XDRV<2> qn_int<2> ADDR_N_O<2> VDD VSS / RSC_IHPSG13_CINVX8 +XDRV<1> qn_int<1> ADDR_N_O<1> VDD VSS / RSC_IHPSG13_CINVX8 +XDRV<0> qn_int<0> ADDR_N_O<0> VDD VSS / RSC_IHPSG13_CINVX8 +XINV<8> q_int<8> qn_int<8> VDD VSS / RSC_IHPSG13_CINVX2 +XINV<7> q_int<7> qn_int<7> VDD VSS / RSC_IHPSG13_CINVX2 +XINV<6> q_int<6> qn_int<6> VDD VSS / RSC_IHPSG13_CINVX2 +XINV<5> q_int<5> qn_int<5> VDD VSS / RSC_IHPSG13_CINVX2 +XINV<4> q_int<4> qn_int<4> VDD VSS / RSC_IHPSG13_CINVX2 +XINV<3> q_int<3> qn_int<3> VDD VSS / RSC_IHPSG13_CINVX2 +XINV<2> q_int<2> qn_int<2> VDD VSS / RSC_IHPSG13_CINVX2 +XINV<1> q_int<1> qn_int<1> VDD VSS / RSC_IHPSG13_CINVX2 +XINV<0> q_int<0> qn_int<0> VDD VSS / RSC_IHPSG13_CINVX2 +.ENDS + +.SUBCKT RM_IHPSG13_256x32_c2_2P_DLY_MUX A SEL Z VDD VSS +XI11 net4 Z VDD VSS / RSC_IHPSG13_CINVX2 +XI8 A D<3> SEL net4 VDD VSS / RSC_IHPSG13_MX2IX1 +XI20<3> D<2> D<3> VDD VSS / RSC_IHPSG13_CDLYX1 +XI20<2> D<1> D<2> VDD VSS / RSC_IHPSG13_CDLYX1 +XI20<1> A D<1> VDD VSS / RSC_IHPSG13_CDLYX1 +.ENDS +.SUBCKT RM_IHPSG13_256x32_c2_2P_CTRL ACLK_N BIST_CK_I BIST_CS_I BIST_EN BIST_RE_I ++ BIST_WE_I B_TIEL_O CK_I CS_I DCLK ECLK PULSE_H PULSE_L PULSE_O RCLK RE_I ++ ROW_CS WCLK WE_I VDD VSS +XI17 ck_regs we col_we VDD VSS / RSC_IHPSG13_DFNQX2 +XI16 ck_regs re col_re VDD VSS / RSC_IHPSG13_DFNQX2 +XI18 ck_regs cs net7 VDD VSS / RSC_IHPSG13_DFNQX2 +XI71 ACLK_N net012 PULSE_O VDD VSS / RSC_IHPSG13_DFNQX2 +XI77 col_we net017 net016 VDD VSS / RSC_IHPSG13_CNAND2X2 +XI76 col_re net017 net018 VDD VSS / RSC_IHPSG13_CNAND2X2 +XI15 ck_dly WEorREandCS aclk VDD VSS / RSC_IHPSG13_CGATEPX4 +XI14 ck WEandCS DCLK VDD VSS / RSC_IHPSG13_CGATEPX4 +XI60 net7 ROW_CS VDD VSS / RSC_IHPSG13_CBUFX8 +XI73 PULSE_O net012 VDD VSS / RSC_IHPSG13_CINVX2 +XI8 net017 net8 VDD VSS / RSC_IHPSG13_CINVX2 +XCAPS4<7> VDD VSS / RSC_IHPSG13_FILLCAP4 +XCAPS4<6> VDD VSS / RSC_IHPSG13_FILLCAP4 +XCAPS4<5> VDD VSS / RSC_IHPSG13_FILLCAP4 +XCAPS4<4> VDD VSS / RSC_IHPSG13_FILLCAP4 +XCAPS4<3> VDD VSS / RSC_IHPSG13_FILLCAP4 +XCAPS4<2> VDD VSS / RSC_IHPSG13_FILLCAP4 +XCAPS4<1> VDD VSS / RSC_IHPSG13_FILLCAP4 +XBM_TIEL B_TIEL_O VDD VSS / RSC_IHPSG13_TIEL +XI64 ck ck_dly VDD VSS / RSC_IHPSG13_CDLYX2 +XI86 CS_I BIST_CS_I BIST_EN cs VDD VSS / RSC_IHPSG13_MX2X2 +XI87 CK_I BIST_CK_I BIST_EN ck VDD VSS / RSC_IHPSG13_MX2X2 +XI85 WE_I BIST_WE_I BIST_EN we VDD VSS / RSC_IHPSG13_MX2X2 +XI84 RE_I BIST_RE_I BIST_EN re VDD VSS / RSC_IHPSG13_MX2X2 +XI48 ck_dly ck_regs VDD VSS / RSC_IHPSG13_CINVX4 +XI81 net016 WCLK VDD VSS / RSC_IHPSG13_CINVX4 +XI80 net018 RCLK VDD VSS / RSC_IHPSG13_CINVX4 +XI78 net8 net020 VDD VSS / RSC_IHPSG13_CINVX4 +XCAPS8<7> VDD VSS / RSC_IHPSG13_FILLCAP8 +XCAPS8<6> VDD VSS / RSC_IHPSG13_FILLCAP8 +XCAPS8<5> VDD VSS / RSC_IHPSG13_FILLCAP8 +XCAPS8<4> VDD VSS / RSC_IHPSG13_FILLCAP8 +XCAPS8<3> VDD VSS / RSC_IHPSG13_FILLCAP8 +XCAPS8<2> VDD VSS / RSC_IHPSG13_FILLCAP8 +XCAPS8<1> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI6 PULSE_L PULSE_H net017 VDD VSS / RSC_IHPSG13_XOR2X2 +XI22 we cs WEandCS VDD VSS / RSC_IHPSG13_AND2X2 +XI79 net020 ECLK VDD VSS / RSC_IHPSG13_CINVX8 +XI63 aclk ACLK_N VDD VSS / RSC_IHPSG13_CINVX8 +XI21 re we cs WEorREandCS VDD VSS / RSC_IHPSG13_OA12X1 +.ENDS +.SUBCKT RM_IHPSG13_256x32_c2_2P_COLDEC5 ACLK_N ADDR<4> ADDR<3> ADDR<2> ADDR<1> ADDR<0> ++ ADDR_COL<1> ADDR_COL<0> ADDR_DEC<7> ADDR_DEC<6> ADDR_DEC<5> ADDR_DEC<4> ++ ADDR_DEC<3> ADDR_DEC<2> ADDR_DEC<1> ADDR_DEC<0> BIST_ADDR<4> BIST_ADDR<3> ++ BIST_ADDR<2> BIST_ADDR<1> BIST_ADDR<0> BIST_EN_I VDD VSS +XI17<4> VDD VSS / RSC_IHPSG13_FILLCAP4 +XI17<3> VDD VSS / RSC_IHPSG13_FILLCAP4 +XI17<2> VDD VSS / RSC_IHPSG13_FILLCAP4 +XI17<1> VDD VSS / RSC_IHPSG13_FILLCAP4 +XI1<7> PADR<0> PADR<1> PADR<2> addr_n<7> VDD VSS / RSC_IHPSG13_NAND3X2 +XI1<6> NADR<0> PADR<1> PADR<2> addr_n<6> VDD VSS / RSC_IHPSG13_NAND3X2 +XI1<5> PADR<0> NADR<1> PADR<2> addr_n<5> VDD VSS / RSC_IHPSG13_NAND3X2 +XI1<4> NADR<0> NADR<1> PADR<2> addr_n<4> VDD VSS / RSC_IHPSG13_NAND3X2 +XI1<3> PADR<0> PADR<1> NADR<2> addr_n<3> VDD VSS / RSC_IHPSG13_NAND3X2 +XI1<2> NADR<0> PADR<1> NADR<2> addr_n<2> VDD VSS / RSC_IHPSG13_NAND3X2 +XI1<1> PADR<0> NADR<1> NADR<2> addr_n<1> VDD VSS / RSC_IHPSG13_NAND3X2 +XI1<0> NADR<0> NADR<1> NADR<2> addr_n<0> VDD VSS / RSC_IHPSG13_NAND3X2 +XDFF<4> BIST_EN_I BIST_ADDR<4> ACLK_N ADDR<4> addr_int<1> net13<0> VDD ++ VSS / RSC_IHPSG13_DFNQMX2IX1 +XDFF<3> BIST_EN_I BIST_ADDR<3> ACLK_N ADDR<3> addr_int<0> net13<1> VDD ++ VSS / RSC_IHPSG13_DFNQMX2IX1 +XDFF<2> BIST_EN_I BIST_ADDR<2> ACLK_N ADDR<2> padr_int<2> net13<2> VDD ++ VSS / RSC_IHPSG13_DFNQMX2IX1 +XDFF<1> BIST_EN_I BIST_ADDR<1> ACLK_N ADDR<1> padr_int<1> net13<3> VDD ++ VSS / RSC_IHPSG13_DFNQMX2IX1 +XDFF<0> BIST_EN_I BIST_ADDR<0> ACLK_N ADDR<0> padr_int<0> net13<4> VDD ++ VSS / RSC_IHPSG13_DFNQMX2IX1 +XI3<2> padr_int<2> NADR<2> VDD VSS / RSC_IHPSG13_INVX2 +XI3<1> padr_int<1> NADR<1> VDD VSS / RSC_IHPSG13_INVX2 +XI3<0> padr_int<0> NADR<0> VDD VSS / RSC_IHPSG13_INVX2 +XI2<7> addr_n<7> ADDR_DEC<7> VDD VSS / RSC_IHPSG13_INVX2 +XI2<6> addr_n<6> ADDR_DEC<6> VDD VSS / RSC_IHPSG13_INVX2 +XI2<5> addr_n<5> ADDR_DEC<5> VDD VSS / RSC_IHPSG13_INVX2 +XI2<4> addr_n<4> ADDR_DEC<4> VDD VSS / RSC_IHPSG13_INVX2 +XI2<3> addr_n<3> ADDR_DEC<3> VDD VSS / RSC_IHPSG13_INVX2 +XI2<2> addr_n<2> ADDR_DEC<2> VDD VSS / RSC_IHPSG13_INVX2 +XI2<1> addr_n<1> ADDR_DEC<1> VDD VSS / RSC_IHPSG13_INVX2 +XI2<0> addr_n<0> ADDR_DEC<0> VDD VSS / RSC_IHPSG13_INVX2 +XI15<2> NADR<2> PADR<2> VDD VSS / RSC_IHPSG13_INVX2 +XI15<1> NADR<1> PADR<1> VDD VSS / RSC_IHPSG13_INVX2 +XI15<0> NADR<0> PADR<0> VDD VSS / RSC_IHPSG13_INVX2 +XI13<1> addr_int<1> ADDR_COL<1> VDD VSS / RSC_IHPSG13_CBUFX2 +XI13<0> addr_int<0> ADDR_COL<0> VDD VSS / RSC_IHPSG13_CBUFX2 +XI14<5> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI14<4> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI14<3> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI14<2> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI14<1> VDD VSS / RSC_IHPSG13_FILLCAP8 +.ENDS +.SUBCKT RM_IHPSG13_256x32_c2_2P_BLDRV A_BLC<3> A_BLC<2> A_BLC<1> A_BLC<0> A_BLC_SEL ++ A_BLT<3> A_BLT<2> A_BLT<1> A_BLT<0> A_BLT_SEL A_PRE_N A_SEL_P<3> A_SEL_P<2> ++ A_SEL_P<1> A_SEL_P<0> A_WR_ONE A_WR_ZERO B_BLC<3> B_BLC<2> B_BLC<1> B_BLC<0> ++ B_BLC_SEL B_BLT<3> B_BLT<2> B_BLT<1> B_BLT<0> B_BLT_SEL B_PRE_N B_SEL_P<3> ++ B_SEL_P<2> B_SEL_P<1> B_SEL_P<0> B_WR_ONE B_WR_ZERO VDD VSS +MA_CWN<3> A_BLC<3> A_BLC_NMOS_DRIVE<3> VSS VSS sg13_lv_nmos m=1 ++ w=4.82u l=130.00n ng=2 nrd=0 nrs=0 +MA_CWN<2> A_BLC<2> A_BLC_NMOS_DRIVE<2> VSS VSS sg13_lv_nmos m=1 ++ w=4.82u l=130.00n ng=2 nrd=0 nrs=0 +MA_CWN<1> A_BLC<1> A_BLC_NMOS_DRIVE<1> VSS VSS sg13_lv_nmos m=1 ++ w=4.82u l=130.00n ng=2 nrd=0 nrs=0 +MA_CWN<0> A_BLC<0> A_BLC_NMOS_DRIVE<0> VSS VSS sg13_lv_nmos m=1 ++ w=4.82u l=130.00n ng=2 nrd=0 nrs=0 +MA_TWN<3> A_BLT<3> A_BLT_NMOS_DRIVE<3> VSS VSS sg13_lv_nmos m=1 ++ w=4.82u l=130.00n ng=2 nrd=0 nrs=0 +MA_TWN<2> A_BLT<2> A_BLT_NMOS_DRIVE<2> VSS VSS sg13_lv_nmos m=1 ++ w=4.82u l=130.00n ng=2 nrd=0 nrs=0 +MA_TWN<1> A_BLT<1> A_BLT_NMOS_DRIVE<1> VSS VSS sg13_lv_nmos m=1 ++ w=4.82u l=130.00n ng=2 nrd=0 nrs=0 +MA_TWN<0> A_BLT<0> A_BLT_NMOS_DRIVE<0> VSS VSS sg13_lv_nmos m=1 ++ w=4.82u l=130.00n ng=2 nrd=0 nrs=0 +MB_TWN<3> B_BLT<3> B_BLT_NMOS_DRIVE<3> VSS VSS sg13_lv_nmos m=1 ++ w=4.82u l=130.00n ng=2 nrd=0 nrs=0 +MB_TWN<2> B_BLT<2> B_BLT_NMOS_DRIVE<2> VSS VSS sg13_lv_nmos m=1 ++ w=4.82u l=130.00n ng=2 nrd=0 nrs=0 +MB_TWN<1> B_BLT<1> B_BLT_NMOS_DRIVE<1> VSS VSS sg13_lv_nmos m=1 ++ w=4.82u l=130.00n ng=2 nrd=0 nrs=0 +MB_TWN<0> B_BLT<0> B_BLT_NMOS_DRIVE<0> VSS VSS sg13_lv_nmos m=1 ++ w=4.82u l=130.00n ng=2 nrd=0 nrs=0 +MB_CWN<3> B_BLC<3> B_BLC_NMOS_DRIVE<3> VSS VSS sg13_lv_nmos m=1 ++ w=4.82u l=130.00n ng=2 nrd=0 nrs=0 +MB_CWN<2> B_BLC<2> B_BLC_NMOS_DRIVE<2> VSS VSS sg13_lv_nmos m=1 ++ w=4.82u l=130.00n ng=2 nrd=0 nrs=0 +MB_CWN<1> B_BLC<1> B_BLC_NMOS_DRIVE<1> VSS VSS sg13_lv_nmos m=1 ++ w=4.82u l=130.00n ng=2 nrd=0 nrs=0 +MB_CWN<0> B_BLC<0> B_BLC_NMOS_DRIVE<0> VSS VSS sg13_lv_nmos m=1 ++ w=4.82u l=130.00n ng=2 nrd=0 nrs=0 +MA_CPR<3> A_BLC<3> A_PRE_N VDD VDD sg13_lv_pmos m=1 w=3.000u l=130.00n ++ ng=2 nrd=0 nrs=0 +MA_CPR<2> A_BLC<2> A_PRE_N VDD VDD sg13_lv_pmos m=1 w=3.000u l=130.00n ++ ng=2 nrd=0 nrs=0 +MA_CPR<1> A_BLC<1> A_PRE_N VDD VDD sg13_lv_pmos m=1 w=3.000u l=130.00n ++ ng=2 nrd=0 nrs=0 +MA_CPR<0> A_BLC<0> A_PRE_N VDD VDD sg13_lv_pmos m=1 w=3.000u l=130.00n ++ ng=2 nrd=0 nrs=0 +MA_TWP<3> A_BLT<3> A_BLT_PMOS_DRIVE<3> VDD VDD sg13_lv_pmos m=1 w=1.5u ++ l=130.00n ng=1 nrd=0 nrs=0 +MA_TWP<2> A_BLT<2> A_BLT_PMOS_DRIVE<2> VDD VDD sg13_lv_pmos m=1 w=1.5u ++ l=130.00n ng=1 nrd=0 nrs=0 +MA_TWP<1> A_BLT<1> A_BLT_PMOS_DRIVE<1> VDD VDD sg13_lv_pmos m=1 w=1.5u ++ l=130.00n ng=1 nrd=0 nrs=0 +MA_TWP<0> A_BLT<0> A_BLT_PMOS_DRIVE<0> VDD VDD sg13_lv_pmos m=1 w=1.5u ++ l=130.00n ng=1 nrd=0 nrs=0 +MA_CWP<3> A_BLC<3> A_BLC_PMOS_DRIVE<3> VDD VDD sg13_lv_pmos m=1 w=1.5u ++ l=130.00n ng=1 nrd=0 nrs=0 +MA_CWP<2> A_BLC<2> A_BLC_PMOS_DRIVE<2> VDD VDD sg13_lv_pmos m=1 w=1.5u ++ l=130.00n ng=1 nrd=0 nrs=0 +MA_CWP<1> A_BLC<1> A_BLC_PMOS_DRIVE<1> VDD VDD sg13_lv_pmos m=1 w=1.5u ++ l=130.00n ng=1 nrd=0 nrs=0 +MA_CWP<0> A_BLC<0> A_BLC_PMOS_DRIVE<0> VDD VDD sg13_lv_pmos m=1 w=1.5u ++ l=130.00n ng=1 nrd=0 nrs=0 +MA_TPR<3> A_BLT<3> A_PRE_N VDD VDD sg13_lv_pmos m=1 w=3.000u l=130.00n ++ ng=2 nrd=0 nrs=0 +MA_TPR<2> A_BLT<2> A_PRE_N VDD VDD sg13_lv_pmos m=1 w=3.000u l=130.00n ++ ng=2 nrd=0 nrs=0 +MA_TPR<1> A_BLT<1> A_PRE_N VDD VDD sg13_lv_pmos m=1 w=3.000u l=130.00n ++ ng=2 nrd=0 nrs=0 +MA_TPR<0> A_BLT<0> A_PRE_N VDD VDD sg13_lv_pmos m=1 w=3.000u l=130.00n ++ ng=2 nrd=0 nrs=0 +MA_TSP<3> A_BLT_SEL A_SEL_N<3> A_BLT<3> VDD sg13_lv_pmos m=1 w=1.5u ++ l=130.00n ng=1 nrd=0 nrs=0 +MA_TSP<2> A_BLT_SEL A_SEL_N<2> A_BLT<2> VDD sg13_lv_pmos m=1 w=1.5u ++ l=130.00n ng=1 nrd=0 nrs=0 +MA_TSP<1> A_BLT_SEL A_SEL_N<1> A_BLT<1> VDD sg13_lv_pmos m=1 w=1.5u ++ l=130.00n ng=1 nrd=0 nrs=0 +MA_TSP<0> A_BLT_SEL A_SEL_N<0> A_BLT<0> VDD sg13_lv_pmos m=1 w=1.5u ++ l=130.00n ng=1 nrd=0 nrs=0 +MA_CSP<3> A_BLC_SEL A_SEL_N<3> A_BLC<3> VDD sg13_lv_pmos m=1 w=1.5u ++ l=130.00n ng=1 nrd=0 nrs=0 +MA_CSP<2> A_BLC_SEL A_SEL_N<2> A_BLC<2> VDD sg13_lv_pmos m=1 w=1.5u ++ l=130.00n ng=1 nrd=0 nrs=0 +MA_CSP<1> A_BLC_SEL A_SEL_N<1> A_BLC<1> VDD sg13_lv_pmos m=1 w=1.5u ++ l=130.00n ng=1 nrd=0 nrs=0 +MA_CSP<0> A_BLC_SEL A_SEL_N<0> A_BLC<0> VDD sg13_lv_pmos m=1 w=1.5u ++ l=130.00n ng=1 nrd=0 nrs=0 +MB_CWP<3> B_BLC<3> B_BLC_PMOS_DRIVE<3> VDD VDD sg13_lv_pmos m=1 w=1.5u ++ l=130.00n ng=1 nrd=0 nrs=0 +MB_CWP<2> B_BLC<2> B_BLC_PMOS_DRIVE<2> VDD VDD sg13_lv_pmos m=1 w=1.5u ++ l=130.00n ng=1 nrd=0 nrs=0 +MB_CWP<1> B_BLC<1> B_BLC_PMOS_DRIVE<1> VDD VDD sg13_lv_pmos m=1 w=1.5u ++ l=130.00n ng=1 nrd=0 nrs=0 +MB_CWP<0> B_BLC<0> B_BLC_PMOS_DRIVE<0> VDD VDD sg13_lv_pmos m=1 w=1.5u ++ l=130.00n ng=1 nrd=0 nrs=0 +MB_TWP<3> B_BLT<3> B_BLT_PMOS_DRIVE<3> VDD VDD sg13_lv_pmos m=1 w=1.5u ++ l=130.00n ng=1 nrd=0 nrs=0 +MB_TWP<2> B_BLT<2> B_BLT_PMOS_DRIVE<2> VDD VDD sg13_lv_pmos m=1 w=1.5u ++ l=130.00n ng=1 nrd=0 nrs=0 +MB_TWP<1> B_BLT<1> B_BLT_PMOS_DRIVE<1> VDD VDD sg13_lv_pmos m=1 w=1.5u ++ l=130.00n ng=1 nrd=0 nrs=0 +MB_TWP<0> B_BLT<0> B_BLT_PMOS_DRIVE<0> VDD VDD sg13_lv_pmos m=1 w=1.5u ++ l=130.00n ng=1 nrd=0 nrs=0 +MB_TSP<3> B_BLT_SEL B_SEL_N<3> B_BLT<3> VDD sg13_lv_pmos m=1 w=1.5u ++ l=130.00n ng=1 nrd=0 nrs=0 +MB_TSP<2> B_BLT_SEL B_SEL_N<2> B_BLT<2> VDD sg13_lv_pmos m=1 w=1.5u ++ l=130.00n ng=1 nrd=0 nrs=0 +MB_TSP<1> B_BLT_SEL B_SEL_N<1> B_BLT<1> VDD sg13_lv_pmos m=1 w=1.5u ++ l=130.00n ng=1 nrd=0 nrs=0 +MB_TSP<0> B_BLT_SEL B_SEL_N<0> B_BLT<0> VDD sg13_lv_pmos m=1 w=1.5u ++ l=130.00n ng=1 nrd=0 nrs=0 +MB_TPR<3> B_BLT<3> B_PRE_N VDD VDD sg13_lv_pmos m=1 w=3.000u l=130.00n ++ ng=2 nrd=0 nrs=0 +MB_TPR<2> B_BLT<2> B_PRE_N VDD VDD sg13_lv_pmos m=1 w=3.000u l=130.00n ++ ng=2 nrd=0 nrs=0 +MB_TPR<1> B_BLT<1> B_PRE_N VDD VDD sg13_lv_pmos m=1 w=3.000u l=130.00n ++ ng=2 nrd=0 nrs=0 +MB_TPR<0> B_BLT<0> B_PRE_N VDD VDD sg13_lv_pmos m=1 w=3.000u l=130.00n ++ ng=2 nrd=0 nrs=0 +MB_CSP<3> B_BLC_SEL B_SEL_N<3> B_BLC<3> VDD sg13_lv_pmos m=1 w=1.5u ++ l=130.00n ng=1 nrd=0 nrs=0 +MB_CSP<2> B_BLC_SEL B_SEL_N<2> B_BLC<2> VDD sg13_lv_pmos m=1 w=1.5u ++ l=130.00n ng=1 nrd=0 nrs=0 +MB_CSP<1> B_BLC_SEL B_SEL_N<1> B_BLC<1> VDD sg13_lv_pmos m=1 w=1.5u ++ l=130.00n ng=1 nrd=0 nrs=0 +MB_CSP<0> B_BLC_SEL B_SEL_N<0> B_BLC<0> VDD sg13_lv_pmos m=1 w=1.5u ++ l=130.00n ng=1 nrd=0 nrs=0 +MB_CPR<3> B_BLC<3> B_PRE_N VDD VDD sg13_lv_pmos m=1 w=3.000u l=130.00n ++ ng=2 nrd=0 nrs=0 +MB_CPR<2> B_BLC<2> B_PRE_N VDD VDD sg13_lv_pmos m=1 w=3.000u l=130.00n ++ ng=2 nrd=0 nrs=0 +MB_CPR<1> B_BLC<1> B_PRE_N VDD VDD sg13_lv_pmos m=1 w=3.000u l=130.00n ++ ng=2 nrd=0 nrs=0 +MB_CPR<0> B_BLC<0> B_PRE_N VDD VDD sg13_lv_pmos m=1 w=3.000u l=130.00n ++ ng=2 nrd=0 nrs=0 +XA_SEL<3> A_SEL_P<3> A_SEL_N<3> VDD VSS / RSC_IHPSG13_INVX2 +XA_SEL<2> A_SEL_P<2> A_SEL_N<2> VDD VSS / RSC_IHPSG13_INVX2 +XA_SEL<1> A_SEL_P<1> A_SEL_N<1> VDD VSS / RSC_IHPSG13_INVX2 +XA_SEL<0> A_SEL_P<0> A_SEL_N<0> VDD VSS / RSC_IHPSG13_INVX2 +XA_CINV<3> A_BLT_PMOS_DRIVE<3> A_BLC_NMOS_DRIVE<3> VDD VSS / ++ RSC_IHPSG13_INVX2 +XA_CINV<2> A_BLT_PMOS_DRIVE<2> A_BLC_NMOS_DRIVE<2> VDD VSS / ++ RSC_IHPSG13_INVX2 +XA_CINV<1> A_BLT_PMOS_DRIVE<1> A_BLC_NMOS_DRIVE<1> VDD VSS / ++ RSC_IHPSG13_INVX2 +XA_CINV<0> A_BLT_PMOS_DRIVE<0> A_BLC_NMOS_DRIVE<0> VDD VSS / ++ RSC_IHPSG13_INVX2 +XA_TINV<3> A_BLC_PMOS_DRIVE<3> A_BLT_NMOS_DRIVE<3> VDD VSS / ++ RSC_IHPSG13_INVX2 +XA_TINV<2> A_BLC_PMOS_DRIVE<2> A_BLT_NMOS_DRIVE<2> VDD VSS / ++ RSC_IHPSG13_INVX2 +XA_TINV<1> A_BLC_PMOS_DRIVE<1> A_BLT_NMOS_DRIVE<1> VDD VSS / ++ RSC_IHPSG13_INVX2 +XA_TINV<0> A_BLC_PMOS_DRIVE<0> A_BLT_NMOS_DRIVE<0> VDD VSS / ++ RSC_IHPSG13_INVX2 +XB_SEL<3> B_SEL_P<3> B_SEL_N<3> VDD VSS / RSC_IHPSG13_INVX2 +XB_SEL<2> B_SEL_P<2> B_SEL_N<2> VDD VSS / RSC_IHPSG13_INVX2 +XB_SEL<1> B_SEL_P<1> B_SEL_N<1> VDD VSS / RSC_IHPSG13_INVX2 +XB_SEL<0> B_SEL_P<0> B_SEL_N<0> VDD VSS / RSC_IHPSG13_INVX2 +XB_TINV<3> B_BLC_PMOS_DRIVE<3> B_BLT_NMOS_DRIVE<3> VDD VSS / ++ RSC_IHPSG13_INVX2 +XB_TINV<2> B_BLC_PMOS_DRIVE<2> B_BLT_NMOS_DRIVE<2> VDD VSS / ++ RSC_IHPSG13_INVX2 +XB_TINV<1> B_BLC_PMOS_DRIVE<1> B_BLT_NMOS_DRIVE<1> VDD VSS / ++ RSC_IHPSG13_INVX2 +XB_TINV<0> B_BLC_PMOS_DRIVE<0> B_BLT_NMOS_DRIVE<0> VDD VSS / ++ RSC_IHPSG13_INVX2 +XB_CINV<3> B_BLT_PMOS_DRIVE<3> B_BLC_NMOS_DRIVE<3> VDD VSS / ++ RSC_IHPSG13_INVX2 +XB_CINV<2> B_BLT_PMOS_DRIVE<2> B_BLC_NMOS_DRIVE<2> VDD VSS / ++ RSC_IHPSG13_INVX2 +XB_CINV<1> B_BLT_PMOS_DRIVE<1> B_BLC_NMOS_DRIVE<1> VDD VSS / ++ RSC_IHPSG13_INVX2 +XB_CINV<0> B_BLT_PMOS_DRIVE<0> B_BLC_NMOS_DRIVE<0> VDD VSS / ++ RSC_IHPSG13_INVX2 +XA_TDEC<3> A_SEL_P<3> A_WR_ONE A_BLT_PMOS_DRIVE<3> VDD VSS / ++ RSC_IHPSG13_NAND2X2 +XA_TDEC<2> A_SEL_P<2> A_WR_ONE A_BLT_PMOS_DRIVE<2> VDD VSS / ++ RSC_IHPSG13_NAND2X2 +XA_TDEC<1> A_SEL_P<1> A_WR_ONE A_BLT_PMOS_DRIVE<1> VDD VSS / ++ RSC_IHPSG13_NAND2X2 +XA_TDEC<0> A_SEL_P<0> A_WR_ONE A_BLT_PMOS_DRIVE<0> VDD VSS / ++ RSC_IHPSG13_NAND2X2 +XA_CDEC<3> A_SEL_P<3> A_WR_ZERO A_BLC_PMOS_DRIVE<3> VDD VSS / ++ RSC_IHPSG13_NAND2X2 +XA_CDEC<2> A_SEL_P<2> A_WR_ZERO A_BLC_PMOS_DRIVE<2> VDD VSS / ++ RSC_IHPSG13_NAND2X2 +XA_CDEC<1> A_SEL_P<1> A_WR_ZERO A_BLC_PMOS_DRIVE<1> VDD VSS / ++ RSC_IHPSG13_NAND2X2 +XA_CDEC<0> A_SEL_P<0> A_WR_ZERO A_BLC_PMOS_DRIVE<0> VDD VSS / ++ RSC_IHPSG13_NAND2X2 +XB_CDEC<3> B_SEL_P<3> B_WR_ZERO B_BLC_PMOS_DRIVE<3> VDD VSS / ++ RSC_IHPSG13_NAND2X2 +XB_CDEC<2> B_SEL_P<2> B_WR_ZERO B_BLC_PMOS_DRIVE<2> VDD VSS / ++ RSC_IHPSG13_NAND2X2 +XB_CDEC<1> B_SEL_P<1> B_WR_ZERO B_BLC_PMOS_DRIVE<1> VDD VSS / ++ RSC_IHPSG13_NAND2X2 +XB_CDEC<0> B_SEL_P<0> B_WR_ZERO B_BLC_PMOS_DRIVE<0> VDD VSS / ++ RSC_IHPSG13_NAND2X2 +XB_TDEC<3> B_SEL_P<3> B_WR_ONE B_BLT_PMOS_DRIVE<3> VDD VSS / ++ RSC_IHPSG13_NAND2X2 +XB_TDEC<2> B_SEL_P<2> B_WR_ONE B_BLT_PMOS_DRIVE<2> VDD VSS / ++ RSC_IHPSG13_NAND2X2 +XB_TDEC<1> B_SEL_P<1> B_WR_ONE B_BLT_PMOS_DRIVE<1> VDD VSS / ++ RSC_IHPSG13_NAND2X2 +XB_TDEC<0> B_SEL_P<0> B_WR_ONE B_BLT_PMOS_DRIVE<0> VDD VSS / ++ RSC_IHPSG13_NAND2X2 +.ENDS +.SUBCKT RSC_IHPSG13_AND2X6 A B Z VDD VSS +MN3 Z net6 VSS VSS sg13_lv_nmos m=1 w=2.94u l=130.00n ng=3 nrd=0 nrs=0 +MN4 net9 B VSS VSS sg13_lv_nmos m=1 w=500.0n l=130.00n ng=1 nrd=0 nrs=0 +MN6 net6 A net9 VSS sg13_lv_nmos m=1 w=500.0n l=130.00n ng=1 nrd=0 nrs=0 +MP2 Z net6 VDD VDD sg13_lv_pmos m=1 w=4.86u l=130.00n ng=3 nrd=0 nrs=0 +MP0 net6 B VDD VDD sg13_lv_pmos m=1 w=860.00n l=130.00n ng=1 nrd=0 ++ nrs=0 +MP1 net6 A VDD VDD sg13_lv_pmos m=1 w=860.00n l=130.00n ng=1 nrd=0 ++ nrs=0 +.ENDS +.SUBCKT RM_IHPSG13_256x32_c2_2P_COLCTRL5 A_ADDR_COL<1> A_ADDR_COL<0> A_ADDR_DEC<7> ++ A_ADDR_DEC<6> A_ADDR_DEC<5> A_ADDR_DEC<4> A_ADDR_DEC<3> A_ADDR_DEC<2> ++ A_ADDR_DEC<1> A_ADDR_DEC<0> A_BIST_BM_I A_BIST_DW_I A_BIST_EN_I A_BLC<31> ++ A_BLC<30> A_BLC<29> A_BLC<28> A_BLC<27> A_BLC<26> A_BLC<25> A_BLC<24> ++ A_BLC<23> A_BLC<22> A_BLC<21> A_BLC<20> A_BLC<19> A_BLC<18> A_BLC<17> ++ A_BLC<16> A_BLC<15> A_BLC<14> A_BLC<13> A_BLC<12> A_BLC<11> A_BLC<10> ++ A_BLC<9> A_BLC<8> A_BLC<7> A_BLC<6> A_BLC<5> A_BLC<4> A_BLC<3> A_BLC<2> ++ A_BLC<1> A_BLC<0> A_BLT<31> A_BLT<30> A_BLT<29> A_BLT<28> A_BLT<27> ++ A_BLT<26> A_BLT<25> A_BLT<24> A_BLT<23> A_BLT<22> A_BLT<21> A_BLT<20> ++ A_BLT<19> A_BLT<18> A_BLT<17> A_BLT<16> A_BLT<15> A_BLT<14> A_BLT<13> ++ A_BLT<12> A_BLT<11> A_BLT<10> A_BLT<9> A_BLT<8> A_BLT<7> A_BLT<6> A_BLT<5> ++ A_BLT<4> A_BLT<3> A_BLT<2> A_BLT<1> A_BLT<0> A_BM_I A_DCLK_B_L A_DCLK_B_R ++ A_DCLK_L A_DCLK_R A_DR_O A_DW_I A_RCLK_B_L A_RCLK_B_R A_RCLK_L A_RCLK_R ++ A_TIEH_O A_WCLK_B_L A_WCLK_B_R A_WCLK_L A_WCLK_R B_ADDR_COL<1> B_ADDR_COL<0> ++ B_ADDR_DEC<7> B_ADDR_DEC<6> B_ADDR_DEC<5> B_ADDR_DEC<4> B_ADDR_DEC<3> ++ B_ADDR_DEC<2> B_ADDR_DEC<1> B_ADDR_DEC<0> B_BIST_BM_I B_BIST_DW_I ++ B_BIST_EN_I B_BLC<31> B_BLC<30> B_BLC<29> B_BLC<28> B_BLC<27> B_BLC<26> ++ B_BLC<25> B_BLC<24> B_BLC<23> B_BLC<22> B_BLC<21> B_BLC<20> B_BLC<19> ++ B_BLC<18> B_BLC<17> B_BLC<16> B_BLC<15> B_BLC<14> B_BLC<13> B_BLC<12> ++ B_BLC<11> B_BLC<10> B_BLC<9> B_BLC<8> B_BLC<7> B_BLC<6> B_BLC<5> B_BLC<4> ++ B_BLC<3> B_BLC<2> B_BLC<1> B_BLC<0> B_BLT<31> B_BLT<30> B_BLT<29> B_BLT<28> ++ B_BLT<27> B_BLT<26> B_BLT<25> B_BLT<24> B_BLT<23> B_BLT<22> B_BLT<21> ++ B_BLT<20> B_BLT<19> B_BLT<18> B_BLT<17> B_BLT<16> B_BLT<15> B_BLT<14> ++ B_BLT<13> B_BLT<12> B_BLT<11> B_BLT<10> B_BLT<9> B_BLT<8> B_BLT<7> B_BLT<6> ++ B_BLT<5> B_BLT<4> B_BLT<3> B_BLT<2> B_BLT<1> B_BLT<0> B_BM_I B_DCLK_B_L ++ B_DCLK_B_R B_DCLK_L B_DCLK_R B_DR_O B_DW_I B_RCLK_B_L B_RCLK_B_R B_RCLK_L ++ B_RCLK_R B_TIEH_O B_WCLK_B_L B_WCLK_B_R B_WCLK_L B_WCLK_R VDD VSS +XB_I80<1> B_WCLK_B_L B_RCLK_B_L B_W_nor_R<1> VDD VSS / ++ RSC_IHPSG13_AND2X2 +XB_I80<0> B_WCLK_B_L B_RCLK_B_L B_W_nor_R<0> VDD VSS / ++ RSC_IHPSG13_AND2X2 +XA_I80<1> A_WCLK_B_L A_RCLK_B_L A_W_nor_R<1> VDD VSS / ++ RSC_IHPSG13_AND2X2 +XA_I80<0> A_WCLK_B_L A_RCLK_B_L A_W_nor_R<0> VDD VSS / ++ RSC_IHPSG13_AND2X2 +XB_I44 B_BM_N B_WCLK_B_L B_DO_WRITE_P VDD VSS / RSC_IHPSG13_NOR2X2 +XA_I44 A_BM_N A_WCLK_B_L A_DO_WRITE_P VDD VSS / RSC_IHPSG13_NOR2X2 +XI_FILL4<16> VDD VSS / RSC_IHPSG13_FILLCAP4 +XI_FILL4<15> VDD VSS / RSC_IHPSG13_FILLCAP4 +XI_FILL4<14> VDD VSS / RSC_IHPSG13_FILLCAP4 +XI_FILL4<13> VDD VSS / RSC_IHPSG13_FILLCAP4 +XI_FILL4<12> VDD VSS / RSC_IHPSG13_FILLCAP4 +XI_FILL4<11> VDD VSS / RSC_IHPSG13_FILLCAP4 +XI_FILL4<10> VDD VSS / RSC_IHPSG13_FILLCAP4 +XI_FILL4<9> VDD VSS / RSC_IHPSG13_FILLCAP4 +XI_FILL4<8> VDD VSS / RSC_IHPSG13_FILLCAP4 +XI_FILL4<7> VDD VSS / RSC_IHPSG13_FILLCAP4 +XI_FILL4<6> VDD VSS / RSC_IHPSG13_FILLCAP4 +XI_FILL4<5> VDD VSS / RSC_IHPSG13_FILLCAP4 +XI_FILL4<4> VDD VSS / RSC_IHPSG13_FILLCAP4 +XI_FILL4<3> VDD VSS / RSC_IHPSG13_FILLCAP4 +XI_FILL4<2> VDD VSS / RSC_IHPSG13_FILLCAP4 +XI_FILL4<1> VDD VSS / RSC_IHPSG13_FILLCAP4 +XB_INV<6> B_N1<1> B_P1<1> VDD VSS / RSC_IHPSG13_CINVX4 +XB_INV<5> B_N0<1> B_P0<1> VDD VSS / RSC_IHPSG13_CINVX4 +XB_INV<4> B_N0<0> B_P0<0> VDD VSS / RSC_IHPSG13_CINVX4 +XB_INV<3> B_ADDR_COL<1> B_N1<1> VDD VSS / RSC_IHPSG13_CINVX4 +XB_INV<2> B_ADDR_COL<1> B_N1<0> VDD VSS / RSC_IHPSG13_CINVX4 +XB_INV<1> B_ADDR_COL<0> B_N0<1> VDD VSS / RSC_IHPSG13_CINVX4 +XB_INV<0> B_ADDR_COL<0> B_N0<0> VDD VSS / RSC_IHPSG13_CINVX4 +XA_INV<6> A_N1<1> A_P1<1> VDD VSS / RSC_IHPSG13_CINVX4 +XA_INV<5> A_N0<1> A_P0<1> VDD VSS / RSC_IHPSG13_CINVX4 +XA_INV<4> A_N0<0> A_P0<0> VDD VSS / RSC_IHPSG13_CINVX4 +XA_INV<3> A_ADDR_COL<1> A_N1<1> VDD VSS / RSC_IHPSG13_CINVX4 +XA_INV<2> A_ADDR_COL<1> A_N1<0> VDD VSS / RSC_IHPSG13_CINVX4 +XA_INV<1> A_ADDR_COL<0> A_N0<1> VDD VSS / RSC_IHPSG13_CINVX4 +XA_INV<0> A_ADDR_COL<0> A_N0<0> VDD VSS / RSC_IHPSG13_CINVX4 +XB_I81<3> B_W_nor_R<1> B_PRE_N VDD VSS / RSC_IHPSG13_CINVX4_WN +XB_I81<2> B_W_nor_R<1> B_PRE_N VDD VSS / RSC_IHPSG13_CINVX4_WN +XB_I81<1> B_W_nor_R<0> B_PRE_N VDD VSS / RSC_IHPSG13_CINVX4_WN +XB_I81<0> B_W_nor_R<0> B_PRE_N VDD VSS / RSC_IHPSG13_CINVX4_WN +XA_I81<3> A_W_nor_R<1> A_PRE_N VDD VSS / RSC_IHPSG13_CINVX4_WN +XA_I81<2> A_W_nor_R<1> A_PRE_N VDD VSS / RSC_IHPSG13_CINVX4_WN +XA_I81<1> A_W_nor_R<0> A_PRE_N VDD VSS / RSC_IHPSG13_CINVX4_WN +XA_I81<0> A_W_nor_R<0> A_PRE_N VDD VSS / RSC_IHPSG13_CINVX4_WN +XI_FILL8<78> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI_FILL8<77> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI_FILL8<76> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI_FILL8<75> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI_FILL8<74> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI_FILL8<73> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI_FILL8<72> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI_FILL8<71> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI_FILL8<70> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI_FILL8<69> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI_FILL8<68> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI_FILL8<67> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI_FILL8<66> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI_FILL8<65> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI_FILL8<64> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI_FILL8<63> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI_FILL8<62> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI_FILL8<61> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI_FILL8<60> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI_FILL8<59> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI_FILL8<58> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI_FILL8<57> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI_FILL8<56> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI_FILL8<55> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI_FILL8<54> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI_FILL8<53> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI_FILL8<52> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI_FILL8<51> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI_FILL8<50> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI_FILL8<49> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI_FILL8<48> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI_FILL8<47> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI_FILL8<46> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI_FILL8<45> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI_FILL8<44> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI_FILL8<43> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI_FILL8<42> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI_FILL8<41> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI_FILL8<40> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI_FILL8<39> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI_FILL8<38> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI_FILL8<37> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI_FILL8<36> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI_FILL8<35> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI_FILL8<34> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI_FILL8<33> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI_FILL8<32> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI_FILL8<31> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI_FILL8<30> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI_FILL8<29> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI_FILL8<28> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI_FILL8<27> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI_FILL8<26> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI_FILL8<25> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI_FILL8<24> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI_FILL8<23> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI_FILL8<22> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI_FILL8<21> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI_FILL8<20> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI_FILL8<19> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI_FILL8<18> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI_FILL8<17> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI_FILL8<16> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI_FILL8<15> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI_FILL8<14> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI_FILL8<13> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI_FILL8<12> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI_FILL8<11> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI_FILL8<10> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI_FILL8<9> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI_FILL8<8> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI_FILL8<7> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI_FILL8<6> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI_FILL8<5> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI_FILL8<4> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI_FILL8<3> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI_FILL8<2> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI_FILL8<1> VDD VSS / RSC_IHPSG13_FILLCAP8 +XAB_BLMUX<7> A_BLC<31> A_BLC<30> A_BLC<29> A_BLC<28> A_BLC_SEL A_BLT<31> ++ A_BLT<30> A_BLT<29> A_BLT<28> A_BLT_SEL A_PRE_N A_SEL_P<31> A_SEL_P<30> ++ A_SEL_P<29> A_SEL_P<28> A_WR_ONE A_WR_ZERO B_BLC<31> B_BLC<30> B_BLC<29> ++ B_BLC<28> B_BLC_SEL B_BLT<31> B_BLT<30> B_BLT<29> B_BLT<28> B_BLT_SEL ++ B_PRE_N B_SEL_P<31> B_SEL_P<30> B_SEL_P<29> B_SEL_P<28> B_WR_ONE B_WR_ZERO ++ VDD VSS / RM_IHPSG13_256x32_c2_2P_BLDRV +XAB_BLMUX<6> A_BLC<27> A_BLC<26> A_BLC<25> A_BLC<24> A_BLC_SEL A_BLT<27> ++ A_BLT<26> A_BLT<25> A_BLT<24> A_BLT_SEL A_PRE_N A_SEL_P<27> A_SEL_P<26> ++ A_SEL_P<25> A_SEL_P<24> A_WR_ONE A_WR_ZERO B_BLC<27> B_BLC<26> B_BLC<25> ++ B_BLC<24> B_BLC_SEL B_BLT<27> B_BLT<26> B_BLT<25> B_BLT<24> B_BLT_SEL ++ B_PRE_N B_SEL_P<27> B_SEL_P<26> B_SEL_P<25> B_SEL_P<24> B_WR_ONE B_WR_ZERO ++ VDD VSS / RM_IHPSG13_256x32_c2_2P_BLDRV +XAB_BLMUX<5> A_BLC<23> A_BLC<22> A_BLC<21> A_BLC<20> A_BLC_SEL A_BLT<23> ++ A_BLT<22> A_BLT<21> A_BLT<20> A_BLT_SEL A_PRE_N A_SEL_P<23> A_SEL_P<22> ++ A_SEL_P<21> A_SEL_P<20> A_WR_ONE A_WR_ZERO B_BLC<23> B_BLC<22> B_BLC<21> ++ B_BLC<20> B_BLC_SEL B_BLT<23> B_BLT<22> B_BLT<21> B_BLT<20> B_BLT_SEL ++ B_PRE_N B_SEL_P<23> B_SEL_P<22> B_SEL_P<21> B_SEL_P<20> B_WR_ONE B_WR_ZERO ++ VDD VSS / RM_IHPSG13_256x32_c2_2P_BLDRV +XAB_BLMUX<4> A_BLC<19> A_BLC<18> A_BLC<17> A_BLC<16> A_BLC_SEL A_BLT<19> ++ A_BLT<18> A_BLT<17> A_BLT<16> A_BLT_SEL A_PRE_N A_SEL_P<19> A_SEL_P<18> ++ A_SEL_P<17> A_SEL_P<16> A_WR_ONE A_WR_ZERO B_BLC<19> B_BLC<18> B_BLC<17> ++ B_BLC<16> B_BLC_SEL B_BLT<19> B_BLT<18> B_BLT<17> B_BLT<16> B_BLT_SEL ++ B_PRE_N B_SEL_P<19> B_SEL_P<18> B_SEL_P<17> B_SEL_P<16> B_WR_ONE B_WR_ZERO ++ VDD VSS / RM_IHPSG13_256x32_c2_2P_BLDRV +XAB_BLMUX<3> A_BLC<15> A_BLC<14> A_BLC<13> A_BLC<12> A_BLC_SEL A_BLT<15> ++ A_BLT<14> A_BLT<13> A_BLT<12> A_BLT_SEL A_PRE_N A_SEL_P<15> A_SEL_P<14> ++ A_SEL_P<13> A_SEL_P<12> A_WR_ONE A_WR_ZERO B_BLC<15> B_BLC<14> B_BLC<13> ++ B_BLC<12> B_BLC_SEL B_BLT<15> B_BLT<14> B_BLT<13> B_BLT<12> B_BLT_SEL ++ B_PRE_N B_SEL_P<15> B_SEL_P<14> B_SEL_P<13> B_SEL_P<12> B_WR_ONE B_WR_ZERO ++ VDD VSS / RM_IHPSG13_256x32_c2_2P_BLDRV +XAB_BLMUX<2> A_BLC<11> A_BLC<10> A_BLC<9> A_BLC<8> A_BLC_SEL A_BLT<11> ++ A_BLT<10> A_BLT<9> A_BLT<8> A_BLT_SEL A_PRE_N A_SEL_P<11> A_SEL_P<10> ++ A_SEL_P<9> A_SEL_P<8> A_WR_ONE A_WR_ZERO B_BLC<11> B_BLC<10> B_BLC<9> ++ B_BLC<8> B_BLC_SEL B_BLT<11> B_BLT<10> B_BLT<9> B_BLT<8> B_BLT_SEL B_PRE_N ++ B_SEL_P<11> B_SEL_P<10> B_SEL_P<9> B_SEL_P<8> B_WR_ONE B_WR_ZERO VDD ++ VSS / RM_IHPSG13_256x32_c2_2P_BLDRV +XAB_BLMUX<1> A_BLC<7> A_BLC<6> A_BLC<5> A_BLC<4> A_BLC_SEL A_BLT<7> A_BLT<6> ++ A_BLT<5> A_BLT<4> A_BLT_SEL A_PRE_N A_SEL_P<7> A_SEL_P<6> A_SEL_P<5> ++ A_SEL_P<4> A_WR_ONE A_WR_ZERO B_BLC<7> B_BLC<6> B_BLC<5> B_BLC<4> B_BLC_SEL ++ B_BLT<7> B_BLT<6> B_BLT<5> B_BLT<4> B_BLT_SEL B_PRE_N B_SEL_P<7> B_SEL_P<6> ++ B_SEL_P<5> B_SEL_P<4> B_WR_ONE B_WR_ZERO VDD VSS / ++ RM_IHPSG13_256x32_c2_2P_BLDRV +XAB_BLMUX<0> A_BLC<3> A_BLC<2> A_BLC<1> A_BLC<0> A_BLC_SEL A_BLT<3> A_BLT<2> ++ A_BLT<1> A_BLT<0> A_BLT_SEL A_PRE_N A_SEL_P<3> A_SEL_P<2> A_SEL_P<1> ++ A_SEL_P<0> A_WR_ONE A_WR_ZERO B_BLC<3> B_BLC<2> B_BLC<1> B_BLC<0> B_BLC_SEL ++ B_BLT<3> B_BLT<2> B_BLT<1> B_BLT<0> B_BLT_SEL B_PRE_N B_SEL_P<3> B_SEL_P<2> ++ B_SEL_P<1> B_SEL_P<0> B_WR_ONE B_WR_ZERO VDD VSS / ++ RM_IHPSG13_256x32_c2_2P_BLDRV +XB_I51 net037 B_DR_O VDD VSS / RSC_IHPSG13_INVX4 +XA_I51 net19 A_DR_O VDD VSS / RSC_IHPSG13_INVX4 +XB_I78 B_RCLK_B_L B_SAE VDD VSS / RSC_IHPSG13_CBUFX2 +XA_I78 A_RCLK_B_L A_SAE VDD VSS / RSC_IHPSG13_CBUFX2 +XB_I69 B_DCLK_L B_DCLK_B_L VDD VSS / RSC_IHPSG13_CINVX8 +XB_I50 B_WCLK_L B_WCLK_B_L VDD VSS / RSC_IHPSG13_CINVX8 +XB_EBUF B_RCLK_L B_RCLK_B_L VDD VSS / RSC_IHPSG13_CINVX8 +XA_I69 A_DCLK_L A_DCLK_B_L VDD VSS / RSC_IHPSG13_CINVX8 +XA_I50 A_WCLK_L A_WCLK_B_L VDD VSS / RSC_IHPSG13_CINVX8 +XA_EBUF A_RCLK_L A_RCLK_B_L VDD VSS / RSC_IHPSG13_CINVX8 +XB_I76 B_DI_N B_DO_WRITE_P B_WR_ZERO VDD VSS / RSC_IHPSG13_AND2X6 +XB_I75 B_DI_R B_DO_WRITE_P B_WR_ONE VDD VSS / RSC_IHPSG13_AND2X6 +XA_I76 A_DI_N A_DO_WRITE_P A_WR_ZERO VDD VSS / RSC_IHPSG13_AND2X6 +XA_I75 A_DI_R A_DO_WRITE_P A_WR_ONE VDD VSS / RSC_IHPSG13_AND2X6 +XB_I83 B_BM_R B_BM_N VDD VSS / RSC_IHPSG13_INVX2 +XB_DEC3INV<31> net041<0> B_SEL_P<31> VDD VSS / RSC_IHPSG13_INVX2 +XB_DEC3INV<30> net041<1> B_SEL_P<30> VDD VSS / RSC_IHPSG13_INVX2 +XB_DEC3INV<29> net041<2> B_SEL_P<29> VDD VSS / RSC_IHPSG13_INVX2 +XB_DEC3INV<28> net041<3> B_SEL_P<28> VDD VSS / RSC_IHPSG13_INVX2 +XB_DEC3INV<27> net041<4> B_SEL_P<27> VDD VSS / RSC_IHPSG13_INVX2 +XB_DEC3INV<26> net041<5> B_SEL_P<26> VDD VSS / RSC_IHPSG13_INVX2 +XB_DEC3INV<25> net041<6> B_SEL_P<25> VDD VSS / RSC_IHPSG13_INVX2 +XB_DEC3INV<24> net041<7> B_SEL_P<24> VDD VSS / RSC_IHPSG13_INVX2 +XB_DEC3INV<23> net041<8> B_SEL_P<23> VDD VSS / RSC_IHPSG13_INVX2 +XB_DEC3INV<22> net041<9> B_SEL_P<22> VDD VSS / RSC_IHPSG13_INVX2 +XB_DEC3INV<21> net041<10> B_SEL_P<21> VDD VSS / RSC_IHPSG13_INVX2 +XB_DEC3INV<20> net041<11> B_SEL_P<20> VDD VSS / RSC_IHPSG13_INVX2 +XB_DEC3INV<19> net041<12> B_SEL_P<19> VDD VSS / RSC_IHPSG13_INVX2 +XB_DEC3INV<18> net041<13> B_SEL_P<18> VDD VSS / RSC_IHPSG13_INVX2 +XB_DEC3INV<17> net041<14> B_SEL_P<17> VDD VSS / RSC_IHPSG13_INVX2 +XB_DEC3INV<16> net041<15> B_SEL_P<16> VDD VSS / RSC_IHPSG13_INVX2 +XB_DEC3INV<15> net041<16> B_SEL_P<15> VDD VSS / RSC_IHPSG13_INVX2 +XB_DEC3INV<14> net041<17> B_SEL_P<14> VDD VSS / RSC_IHPSG13_INVX2 +XB_DEC3INV<13> net041<18> B_SEL_P<13> VDD VSS / RSC_IHPSG13_INVX2 +XB_DEC3INV<12> net041<19> B_SEL_P<12> VDD VSS / RSC_IHPSG13_INVX2 +XB_DEC3INV<11> net041<20> B_SEL_P<11> VDD VSS / RSC_IHPSG13_INVX2 +XB_DEC3INV<10> net041<21> B_SEL_P<10> VDD VSS / RSC_IHPSG13_INVX2 +XB_DEC3INV<9> net041<22> B_SEL_P<9> VDD VSS / RSC_IHPSG13_INVX2 +XB_DEC3INV<8> net041<23> B_SEL_P<8> VDD VSS / RSC_IHPSG13_INVX2 +XB_DEC3INV<7> net041<24> B_SEL_P<7> VDD VSS / RSC_IHPSG13_INVX2 +XB_DEC3INV<6> net041<25> B_SEL_P<6> VDD VSS / RSC_IHPSG13_INVX2 +XB_DEC3INV<5> net041<26> B_SEL_P<5> VDD VSS / RSC_IHPSG13_INVX2 +XB_DEC3INV<4> net041<27> B_SEL_P<4> VDD VSS / RSC_IHPSG13_INVX2 +XB_DEC3INV<3> net041<28> B_SEL_P<3> VDD VSS / RSC_IHPSG13_INVX2 +XB_DEC3INV<2> net041<29> B_SEL_P<2> VDD VSS / RSC_IHPSG13_INVX2 +XB_DEC3INV<1> net041<30> B_SEL_P<1> VDD VSS / RSC_IHPSG13_INVX2 +XB_DEC3INV<0> net041<31> B_SEL_P<0> VDD VSS / RSC_IHPSG13_INVX2 +XB_I49 B_DI_R B_DI_N VDD VSS / RSC_IHPSG13_INVX2 +XA_I83 A_BM_R A_BM_N VDD VSS / RSC_IHPSG13_INVX2 +XA_DEC3INV<31> net23<0> A_SEL_P<31> VDD VSS / RSC_IHPSG13_INVX2 +XA_DEC3INV<30> net23<1> A_SEL_P<30> VDD VSS / RSC_IHPSG13_INVX2 +XA_DEC3INV<29> net23<2> A_SEL_P<29> VDD VSS / RSC_IHPSG13_INVX2 +XA_DEC3INV<28> net23<3> A_SEL_P<28> VDD VSS / RSC_IHPSG13_INVX2 +XA_DEC3INV<27> net23<4> A_SEL_P<27> VDD VSS / RSC_IHPSG13_INVX2 +XA_DEC3INV<26> net23<5> A_SEL_P<26> VDD VSS / RSC_IHPSG13_INVX2 +XA_DEC3INV<25> net23<6> A_SEL_P<25> VDD VSS / RSC_IHPSG13_INVX2 +XA_DEC3INV<24> net23<7> A_SEL_P<24> VDD VSS / RSC_IHPSG13_INVX2 +XA_DEC3INV<23> net23<8> A_SEL_P<23> VDD VSS / RSC_IHPSG13_INVX2 +XA_DEC3INV<22> net23<9> A_SEL_P<22> VDD VSS / RSC_IHPSG13_INVX2 +XA_DEC3INV<21> net23<10> A_SEL_P<21> VDD VSS / RSC_IHPSG13_INVX2 +XA_DEC3INV<20> net23<11> A_SEL_P<20> VDD VSS / RSC_IHPSG13_INVX2 +XA_DEC3INV<19> net23<12> A_SEL_P<19> VDD VSS / RSC_IHPSG13_INVX2 +XA_DEC3INV<18> net23<13> A_SEL_P<18> VDD VSS / RSC_IHPSG13_INVX2 +XA_DEC3INV<17> net23<14> A_SEL_P<17> VDD VSS / RSC_IHPSG13_INVX2 +XA_DEC3INV<16> net23<15> A_SEL_P<16> VDD VSS / RSC_IHPSG13_INVX2 +XA_DEC3INV<15> net23<16> A_SEL_P<15> VDD VSS / RSC_IHPSG13_INVX2 +XA_DEC3INV<14> net23<17> A_SEL_P<14> VDD VSS / RSC_IHPSG13_INVX2 +XA_DEC3INV<13> net23<18> A_SEL_P<13> VDD VSS / RSC_IHPSG13_INVX2 +XA_DEC3INV<12> net23<19> A_SEL_P<12> VDD VSS / RSC_IHPSG13_INVX2 +XA_DEC3INV<11> net23<20> A_SEL_P<11> VDD VSS / RSC_IHPSG13_INVX2 +XA_DEC3INV<10> net23<21> A_SEL_P<10> VDD VSS / RSC_IHPSG13_INVX2 +XA_DEC3INV<9> net23<22> A_SEL_P<9> VDD VSS / RSC_IHPSG13_INVX2 +XA_DEC3INV<8> net23<23> A_SEL_P<8> VDD VSS / RSC_IHPSG13_INVX2 +XA_DEC3INV<7> net23<24> A_SEL_P<7> VDD VSS / RSC_IHPSG13_INVX2 +XA_DEC3INV<6> net23<25> A_SEL_P<6> VDD VSS / RSC_IHPSG13_INVX2 +XA_DEC3INV<5> net23<26> A_SEL_P<5> VDD VSS / RSC_IHPSG13_INVX2 +XA_DEC3INV<4> net23<27> A_SEL_P<4> VDD VSS / RSC_IHPSG13_INVX2 +XA_DEC3INV<3> net23<28> A_SEL_P<3> VDD VSS / RSC_IHPSG13_INVX2 +XA_DEC3INV<2> net23<29> A_SEL_P<2> VDD VSS / RSC_IHPSG13_INVX2 +XA_DEC3INV<1> net23<30> A_SEL_P<1> VDD VSS / RSC_IHPSG13_INVX2 +XA_DEC3INV<0> net23<31> A_SEL_P<0> VDD VSS / RSC_IHPSG13_INVX2 +XA_I49 A_DI_R A_DI_N VDD VSS / RSC_IHPSG13_INVX2 +XB_ISENSE B_SAE B_BLC_SEL B_BLT_SEL net037 net038 VDD VSS / ++ RSC_IHPSG13_DFPQD_MSAFFX2 +XA_ISENSE A_SAE A_BLC_SEL A_BLT_SEL net19 net20 VDD VSS / ++ RSC_IHPSG13_DFPQD_MSAFFX2 +XB_DREG B_BIST_EN_I B_BIST_DW_I B_DCLK_B_L B_DW_I B_DI_R net042 VDD ++ VSS / RSC_IHPSG13_DFNQMX2IX1 +XB_BREG B_BIST_EN_I B_BIST_BM_I B_DCLK_B_L B_BM_I B_BM_R net043 VDD ++ VSS / RSC_IHPSG13_DFNQMX2IX1 +XA_DREG A_BIST_EN_I A_BIST_DW_I A_DCLK_B_L A_DW_I A_DI_R net22 VDD VSS ++ / RSC_IHPSG13_DFNQMX2IX1 +XA_BREG A_BIST_EN_I A_BIST_BM_I A_DCLK_B_L A_BM_I A_BM_R net21 VDD VSS ++ / RSC_IHPSG13_DFNQMX2IX1 +XB_DEC3<31> B_P1<1> B_P0<1> B_ADDR_DEC<7> net041<0> VDD VSS / ++ RSC_IHPSG13_NAND3X2 +XB_DEC3<30> B_P1<1> B_P0<1> B_ADDR_DEC<6> net041<1> VDD VSS / ++ RSC_IHPSG13_NAND3X2 +XB_DEC3<29> B_P1<1> B_P0<1> B_ADDR_DEC<5> net041<2> VDD VSS / ++ RSC_IHPSG13_NAND3X2 +XB_DEC3<28> B_P1<1> B_P0<1> B_ADDR_DEC<4> net041<3> VDD VSS / ++ RSC_IHPSG13_NAND3X2 +XB_DEC3<27> B_P1<1> B_P0<1> B_ADDR_DEC<3> net041<4> VDD VSS / ++ RSC_IHPSG13_NAND3X2 +XB_DEC3<26> B_P1<1> B_P0<1> B_ADDR_DEC<2> net041<5> VDD VSS / ++ RSC_IHPSG13_NAND3X2 +XB_DEC3<25> B_P1<1> B_P0<1> B_ADDR_DEC<1> net041<6> VDD VSS / ++ RSC_IHPSG13_NAND3X2 +XB_DEC3<24> B_P1<1> B_P0<1> B_ADDR_DEC<0> net041<7> VDD VSS / ++ RSC_IHPSG13_NAND3X2 +XB_DEC3<23> B_P1<1> B_N0<1> B_ADDR_DEC<7> net041<8> VDD VSS / ++ RSC_IHPSG13_NAND3X2 +XB_DEC3<22> B_P1<1> B_N0<1> B_ADDR_DEC<6> net041<9> VDD VSS / ++ RSC_IHPSG13_NAND3X2 +XB_DEC3<21> B_P1<1> B_N0<1> B_ADDR_DEC<5> net041<10> VDD VSS / ++ RSC_IHPSG13_NAND3X2 +XB_DEC3<20> B_P1<1> B_N0<1> B_ADDR_DEC<4> net041<11> VDD VSS / ++ RSC_IHPSG13_NAND3X2 +XB_DEC3<19> B_P1<1> B_N0<1> B_ADDR_DEC<3> net041<12> VDD VSS / ++ RSC_IHPSG13_NAND3X2 +XB_DEC3<18> B_P1<1> B_N0<1> B_ADDR_DEC<2> net041<13> VDD VSS / ++ RSC_IHPSG13_NAND3X2 +XB_DEC3<17> B_P1<1> B_N0<1> B_ADDR_DEC<1> net041<14> VDD VSS / ++ RSC_IHPSG13_NAND3X2 +XB_DEC3<16> B_P1<1> B_N0<1> B_ADDR_DEC<0> net041<15> VDD VSS / ++ RSC_IHPSG13_NAND3X2 +XB_DEC3<15> B_N1<0> B_P0<0> B_ADDR_DEC<7> net041<16> VDD VSS / ++ RSC_IHPSG13_NAND3X2 +XB_DEC3<14> B_N1<0> B_P0<0> B_ADDR_DEC<6> net041<17> VDD VSS / ++ RSC_IHPSG13_NAND3X2 +XB_DEC3<13> B_N1<0> B_P0<0> B_ADDR_DEC<5> net041<18> VDD VSS / ++ RSC_IHPSG13_NAND3X2 +XB_DEC3<12> B_N1<0> B_P0<0> B_ADDR_DEC<4> net041<19> VDD VSS / ++ RSC_IHPSG13_NAND3X2 +XB_DEC3<11> B_N1<0> B_P0<0> B_ADDR_DEC<3> net041<20> VDD VSS / ++ RSC_IHPSG13_NAND3X2 +XB_DEC3<10> B_N1<0> B_P0<0> B_ADDR_DEC<2> net041<21> VDD VSS / ++ RSC_IHPSG13_NAND3X2 +XB_DEC3<9> B_N1<0> B_P0<0> B_ADDR_DEC<1> net041<22> VDD VSS / ++ RSC_IHPSG13_NAND3X2 +XB_DEC3<8> B_N1<0> B_P0<0> B_ADDR_DEC<0> net041<23> VDD VSS / ++ RSC_IHPSG13_NAND3X2 +XB_DEC3<7> B_N1<0> B_N0<0> B_ADDR_DEC<7> net041<24> VDD VSS / ++ RSC_IHPSG13_NAND3X2 +XB_DEC3<6> B_N1<0> B_N0<0> B_ADDR_DEC<6> net041<25> VDD VSS / ++ RSC_IHPSG13_NAND3X2 +XB_DEC3<5> B_N1<0> B_N0<0> B_ADDR_DEC<5> net041<26> VDD VSS / ++ RSC_IHPSG13_NAND3X2 +XB_DEC3<4> B_N1<0> B_N0<0> B_ADDR_DEC<4> net041<27> VDD VSS / ++ RSC_IHPSG13_NAND3X2 +XB_DEC3<3> B_N1<0> B_N0<0> B_ADDR_DEC<3> net041<28> VDD VSS / ++ RSC_IHPSG13_NAND3X2 +XB_DEC3<2> B_N1<0> B_N0<0> B_ADDR_DEC<2> net041<29> VDD VSS / ++ RSC_IHPSG13_NAND3X2 +XB_DEC3<1> B_N1<0> B_N0<0> B_ADDR_DEC<1> net041<30> VDD VSS / ++ RSC_IHPSG13_NAND3X2 +XB_DEC3<0> B_N1<0> B_N0<0> B_ADDR_DEC<0> net041<31> VDD VSS / ++ RSC_IHPSG13_NAND3X2 +XA_DEC3<31> A_P1<1> A_P0<1> A_ADDR_DEC<7> net23<0> VDD VSS / ++ RSC_IHPSG13_NAND3X2 +XA_DEC3<30> A_P1<1> A_P0<1> A_ADDR_DEC<6> net23<1> VDD VSS / ++ RSC_IHPSG13_NAND3X2 +XA_DEC3<29> A_P1<1> A_P0<1> A_ADDR_DEC<5> net23<2> VDD VSS / ++ RSC_IHPSG13_NAND3X2 +XA_DEC3<28> A_P1<1> A_P0<1> A_ADDR_DEC<4> net23<3> VDD VSS / ++ RSC_IHPSG13_NAND3X2 +XA_DEC3<27> A_P1<1> A_P0<1> A_ADDR_DEC<3> net23<4> VDD VSS / ++ RSC_IHPSG13_NAND3X2 +XA_DEC3<26> A_P1<1> A_P0<1> A_ADDR_DEC<2> net23<5> VDD VSS / ++ RSC_IHPSG13_NAND3X2 +XA_DEC3<25> A_P1<1> A_P0<1> A_ADDR_DEC<1> net23<6> VDD VSS / ++ RSC_IHPSG13_NAND3X2 +XA_DEC3<24> A_P1<1> A_P0<1> A_ADDR_DEC<0> net23<7> VDD VSS / ++ RSC_IHPSG13_NAND3X2 +XA_DEC3<23> A_P1<1> A_N0<1> A_ADDR_DEC<7> net23<8> VDD VSS / ++ RSC_IHPSG13_NAND3X2 +XA_DEC3<22> A_P1<1> A_N0<1> A_ADDR_DEC<6> net23<9> VDD VSS / ++ RSC_IHPSG13_NAND3X2 +XA_DEC3<21> A_P1<1> A_N0<1> A_ADDR_DEC<5> net23<10> VDD VSS / ++ RSC_IHPSG13_NAND3X2 +XA_DEC3<20> A_P1<1> A_N0<1> A_ADDR_DEC<4> net23<11> VDD VSS / ++ RSC_IHPSG13_NAND3X2 +XA_DEC3<19> A_P1<1> A_N0<1> A_ADDR_DEC<3> net23<12> VDD VSS / ++ RSC_IHPSG13_NAND3X2 +XA_DEC3<18> A_P1<1> A_N0<1> A_ADDR_DEC<2> net23<13> VDD VSS / ++ RSC_IHPSG13_NAND3X2 +XA_DEC3<17> A_P1<1> A_N0<1> A_ADDR_DEC<1> net23<14> VDD VSS / ++ RSC_IHPSG13_NAND3X2 +XA_DEC3<16> A_P1<1> A_N0<1> A_ADDR_DEC<0> net23<15> VDD VSS / ++ RSC_IHPSG13_NAND3X2 +XA_DEC3<15> A_N1<0> A_P0<0> A_ADDR_DEC<7> net23<16> VDD VSS / ++ RSC_IHPSG13_NAND3X2 +XA_DEC3<14> A_N1<0> A_P0<0> A_ADDR_DEC<6> net23<17> VDD VSS / ++ RSC_IHPSG13_NAND3X2 +XA_DEC3<13> A_N1<0> A_P0<0> A_ADDR_DEC<5> net23<18> VDD VSS / ++ RSC_IHPSG13_NAND3X2 +XA_DEC3<12> A_N1<0> A_P0<0> A_ADDR_DEC<4> net23<19> VDD VSS / ++ RSC_IHPSG13_NAND3X2 +XA_DEC3<11> A_N1<0> A_P0<0> A_ADDR_DEC<3> net23<20> VDD VSS / ++ RSC_IHPSG13_NAND3X2 +XA_DEC3<10> A_N1<0> A_P0<0> A_ADDR_DEC<2> net23<21> VDD VSS / ++ RSC_IHPSG13_NAND3X2 +XA_DEC3<9> A_N1<0> A_P0<0> A_ADDR_DEC<1> net23<22> VDD VSS / ++ RSC_IHPSG13_NAND3X2 +XA_DEC3<8> A_N1<0> A_P0<0> A_ADDR_DEC<0> net23<23> VDD VSS / ++ RSC_IHPSG13_NAND3X2 +XA_DEC3<7> A_N1<0> A_N0<0> A_ADDR_DEC<7> net23<24> VDD VSS / ++ RSC_IHPSG13_NAND3X2 +XA_DEC3<6> A_N1<0> A_N0<0> A_ADDR_DEC<6> net23<25> VDD VSS / ++ RSC_IHPSG13_NAND3X2 +XA_DEC3<5> A_N1<0> A_N0<0> A_ADDR_DEC<5> net23<26> VDD VSS / ++ RSC_IHPSG13_NAND3X2 +XA_DEC3<4> A_N1<0> A_N0<0> A_ADDR_DEC<4> net23<27> VDD VSS / ++ RSC_IHPSG13_NAND3X2 +XA_DEC3<3> A_N1<0> A_N0<0> A_ADDR_DEC<3> net23<28> VDD VSS / ++ RSC_IHPSG13_NAND3X2 +XA_DEC3<2> A_N1<0> A_N0<0> A_ADDR_DEC<2> net23<29> VDD VSS / ++ RSC_IHPSG13_NAND3X2 +XA_DEC3<1> A_N1<0> A_N0<0> A_ADDR_DEC<1> net23<30> VDD VSS / ++ RSC_IHPSG13_NAND3X2 +XA_DEC3<0> A_N1<0> A_N0<0> A_ADDR_DEC<0> net23<31> VDD VSS / ++ RSC_IHPSG13_NAND3X2 +XB_I89 B_DCLK_B_L B_DCLK_B_R / RSC_IHPSG13_MET3RES +XB_I91 B_RCLK_B_L B_RCLK_B_R / RSC_IHPSG13_MET3RES +XB_I90 B_WCLK_B_L B_WCLK_B_R / RSC_IHPSG13_MET3RES +XB_I88 B_DCLK_L B_DCLK_R / RSC_IHPSG13_MET3RES +XB_I87 B_WCLK_L B_WCLK_R / RSC_IHPSG13_MET3RES +XB_R2 B_RCLK_L B_RCLK_R / RSC_IHPSG13_MET3RES +XA_I89 A_DCLK_B_L A_DCLK_B_R / RSC_IHPSG13_MET3RES +XA_I91 A_RCLK_B_L A_RCLK_B_R / RSC_IHPSG13_MET3RES +XA_I90 A_WCLK_B_L A_WCLK_B_R / RSC_IHPSG13_MET3RES +XA_I88 A_DCLK_L A_DCLK_R / RSC_IHPSG13_MET3RES +XA_I87 A_WCLK_L A_WCLK_R / RSC_IHPSG13_MET3RES +XA_R2 A_RCLK_L A_RCLK_R / RSC_IHPSG13_MET3RES +XB_BM_TIEH B_TIEH_O VDD VSS / RSC_IHPSG13_TIEH +XA_BM_TIEH A_TIEH_O VDD VSS / RSC_IHPSG13_TIEH +.ENDS +.SUBCKT RM_IHPSG13_256x32_c2_2P_COLDRV13_FILL4 VDD VSS +XI0<11> VDD VSS / RSC_IHPSG13_FILLCAP4 +XI0<10> VDD VSS / RSC_IHPSG13_FILLCAP4 +XI0<9> VDD VSS / RSC_IHPSG13_FILLCAP4 +XI0<8> VDD VSS / RSC_IHPSG13_FILLCAP4 +XI0<7> VDD VSS / RSC_IHPSG13_FILLCAP4 +XI0<6> VDD VSS / RSC_IHPSG13_FILLCAP4 +XI0<5> VDD VSS / RSC_IHPSG13_FILLCAP4 +XI0<4> VDD VSS / RSC_IHPSG13_FILLCAP4 +XI0<3> VDD VSS / RSC_IHPSG13_FILLCAP4 +XI0<2> VDD VSS / RSC_IHPSG13_FILLCAP4 +XI0<1> VDD VSS / RSC_IHPSG13_FILLCAP4 +.ENDS + + +.SUBCKT RSC_IHPSG13_CBUFX16 A Z VDD VSS +MN0 net4 A VSS VSS sg13_lv_nmos m=1 w=2.115u l=130.00n ng=3 nrd=0 nrs=0 +MN1 Z net4 VSS VSS sg13_lv_nmos m=1 w=5.64u l=130.00n ng=8 nrd=0 nrs=0 +MP1 Z net4 VDD VDD sg13_lv_pmos m=1 w=13.000u l=130.00n ng=8 nrd=0 ++ nrs=0 +MP0 net4 A VDD VDD sg13_lv_pmos m=1 w=4.89u l=130.00n ng=3 nrd=0 nrs=0 +.ENDS +.SUBCKT RM_IHPSG13_256x32_c2_1P_COLDRV13X16 ADDR_COL_I<1> ADDR_COL_I<0> ADDR_COL_O<1> ++ ADDR_COL_O<0> ADDR_DEC_I<7> ADDR_DEC_I<6> ADDR_DEC_I<5> ADDR_DEC_I<4> ++ ADDR_DEC_I<3> ADDR_DEC_I<2> ADDR_DEC_I<1> ADDR_DEC_I<0> ADDR_DEC_O<7> ++ ADDR_DEC_O<6> ADDR_DEC_O<5> ADDR_DEC_O<4> ADDR_DEC_O<3> ADDR_DEC_O<2> ++ ADDR_DEC_O<1> ADDR_DEC_O<0> DCLK_I DCLK_O RCLK_I RCLK_O WCLK_I WCLK_O ++ VDD VSS +XI1<1> VDD VSS / RSC_IHPSG13_FILLCAP4 +XI1<0> VDD VSS / RSC_IHPSG13_FILLCAP4 +XI0<3> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI0<2> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI0<1> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI0<0> VDD VSS / RSC_IHPSG13_FILLCAP8 +XADDR_COL_DRV<1> ADDR_COL_I<1> ADDR_COL_O<1> VDD VSS / ++ RSC_IHPSG13_CBUFX16 +XADDR_COL_DRV<0> ADDR_COL_I<0> ADDR_COL_O<0> VDD VSS / ++ RSC_IHPSG13_CBUFX16 +XADDR_DEC_DRV<7> ADDR_DEC_I<7> ADDR_DEC_O<7> VDD VSS / ++ RSC_IHPSG13_CBUFX16 +XADDR_DEC_DRV<6> ADDR_DEC_I<6> ADDR_DEC_O<6> VDD VSS / ++ RSC_IHPSG13_CBUFX16 +XADDR_DEC_DRV<5> ADDR_DEC_I<5> ADDR_DEC_O<5> VDD VSS / ++ RSC_IHPSG13_CBUFX16 +XADDR_DEC_DRV<4> ADDR_DEC_I<4> ADDR_DEC_O<4> VDD VSS / ++ RSC_IHPSG13_CBUFX16 +XADDR_DEC_DRV<3> ADDR_DEC_I<3> ADDR_DEC_O<3> VDD VSS / ++ RSC_IHPSG13_CBUFX16 +XADDR_DEC_DRV<2> ADDR_DEC_I<2> ADDR_DEC_O<2> VDD VSS / ++ RSC_IHPSG13_CBUFX16 +XADDR_DEC_DRV<1> ADDR_DEC_I<1> ADDR_DEC_O<1> VDD VSS / ++ RSC_IHPSG13_CBUFX16 +XADDR_DEC_DRV<0> ADDR_DEC_I<0> ADDR_DEC_O<0> VDD VSS / ++ RSC_IHPSG13_CBUFX16 +XDCLK_DRV DCLK_I DCLK_O VDD VSS / RSC_IHPSG13_CBUFX16 +XRCLK_DRV RCLK_I RCLK_O VDD VSS / RSC_IHPSG13_CBUFX16 +XWCLK_DRV WCLK_I WCLK_O VDD VSS / RSC_IHPSG13_CBUFX16 +.ENDS +.SUBCKT RSC_IHPSG13_WLDRVX16 A Z VDD VSS +MN1 Z net6 VSS VSS sg13_lv_nmos m=1 w=1.41u l=130.00n ng=2 nrd=0 nrs=0 +MN0 net6 A VSS VSS sg13_lv_nmos m=1 w=1.8u l=130.00n ng=2 nrd=0 nrs=0 +MP1 Z net6 VDD VDD sg13_lv_pmos m=1 w=12.96u l=130.00n ng=8 nrd=0 nrs=0 +MP0 net6 A VDD VDD sg13_lv_pmos m=1 w=900.0n l=130.00n ng=1 nrd=0 nrs=0 +.ENDS +.SUBCKT RM_IHPSG13_256x32_c2_1P_WLDRV16X16 A<15> A<14> A<13> A<12> A<11> A<10> A<9> A<8> ++ A<7> A<6> A<5> A<4> A<3> A<2> A<1> A<0> Z<15> Z<14> Z<13> Z<12> Z<11> Z<10> ++ Z<9> Z<8> Z<7> Z<6> Z<5> Z<4> Z<3> Z<2> Z<1> Z<0> VDD VSS +XBUF<15> A<15> Z<15> VDD VSS / RSC_IHPSG13_WLDRVX16 +XBUF<14> A<14> Z<14> VDD VSS / RSC_IHPSG13_WLDRVX16 +XBUF<13> A<13> Z<13> VDD VSS / RSC_IHPSG13_WLDRVX16 +XBUF<12> A<12> Z<12> VDD VSS / RSC_IHPSG13_WLDRVX16 +XBUF<11> A<11> Z<11> VDD VSS / RSC_IHPSG13_WLDRVX16 +XBUF<10> A<10> Z<10> VDD VSS / RSC_IHPSG13_WLDRVX16 +XBUF<9> A<9> Z<9> VDD VSS / RSC_IHPSG13_WLDRVX16 +XBUF<8> A<8> Z<8> VDD VSS / RSC_IHPSG13_WLDRVX16 +XBUF<7> A<7> Z<7> VDD VSS / RSC_IHPSG13_WLDRVX16 +XBUF<6> A<6> Z<6> VDD VSS / RSC_IHPSG13_WLDRVX16 +XBUF<5> A<5> Z<5> VDD VSS / RSC_IHPSG13_WLDRVX16 +XBUF<4> A<4> Z<4> VDD VSS / RSC_IHPSG13_WLDRVX16 +XBUF<3> A<3> Z<3> VDD VSS / RSC_IHPSG13_WLDRVX16 +XBUF<2> A<2> Z<2> VDD VSS / RSC_IHPSG13_WLDRVX16 +XBUF<1> A<1> Z<1> VDD VSS / RSC_IHPSG13_WLDRVX16 +XBUF<0> A<0> Z<0> VDD VSS / RSC_IHPSG13_WLDRVX16 +.ENDS + + +.SUBCKT RM_IHPSG13_256x32_c2_2P_COLDRV13X4 ADDR_COL_I<1> ADDR_COL_I<0> ADDR_COL_O<1> ++ ADDR_COL_O<0> ADDR_DEC_I<7> ADDR_DEC_I<6> ADDR_DEC_I<5> ADDR_DEC_I<4> ++ ADDR_DEC_I<3> ADDR_DEC_I<2> ADDR_DEC_I<1> ADDR_DEC_I<0> ADDR_DEC_O<7> ++ ADDR_DEC_O<6> ADDR_DEC_O<5> ADDR_DEC_O<4> ADDR_DEC_O<3> ADDR_DEC_O<2> ++ ADDR_DEC_O<1> ADDR_DEC_O<0> DCLK_I DCLK_O RCLK_I RCLK_O WCLK_I WCLK_O ++ VDD VSS +XWCLK_DRV WCLK_I WCLK_O VDD VSS / RSC_IHPSG13_CBUFX4 +XRCLK_DRV RCLK_I RCLK_O VDD VSS / RSC_IHPSG13_CBUFX4 +XDCLK_DRV DCLK_I DCLK_O VDD VSS / RSC_IHPSG13_CBUFX4 +XADDR_COL_DRV<1> ADDR_COL_I<1> ADDR_COL_O<1> VDD VSS / ++ RSC_IHPSG13_CBUFX4 +XADDR_COL_DRV<0> ADDR_COL_I<0> ADDR_COL_O<0> VDD VSS / ++ RSC_IHPSG13_CBUFX4 +XADDR_DEC_DRV<7> ADDR_DEC_I<7> ADDR_DEC_O<7> VDD VSS / ++ RSC_IHPSG13_CBUFX4 +XADDR_DEC_DRV<6> ADDR_DEC_I<6> ADDR_DEC_O<6> VDD VSS / ++ RSC_IHPSG13_CBUFX4 +XADDR_DEC_DRV<5> ADDR_DEC_I<5> ADDR_DEC_O<5> VDD VSS / ++ RSC_IHPSG13_CBUFX4 +XADDR_DEC_DRV<4> ADDR_DEC_I<4> ADDR_DEC_O<4> VDD VSS / ++ RSC_IHPSG13_CBUFX4 +XADDR_DEC_DRV<3> ADDR_DEC_I<3> ADDR_DEC_O<3> VDD VSS / ++ RSC_IHPSG13_CBUFX4 +XADDR_DEC_DRV<2> ADDR_DEC_I<2> ADDR_DEC_O<2> VDD VSS / ++ RSC_IHPSG13_CBUFX4 +XADDR_DEC_DRV<1> ADDR_DEC_I<1> ADDR_DEC_O<1> VDD VSS / ++ RSC_IHPSG13_CBUFX4 +XADDR_DEC_DRV<0> ADDR_DEC_I<0> ADDR_DEC_O<0> VDD VSS / ++ RSC_IHPSG13_CBUFX4 +XI0<6> VDD VSS / RSC_IHPSG13_FILLCAP4 +XI0<5> VDD VSS / RSC_IHPSG13_FILLCAP4 +XI0<4> VDD VSS / RSC_IHPSG13_FILLCAP4 +XI0<3> VDD VSS / RSC_IHPSG13_FILLCAP4 +XI0<2> VDD VSS / RSC_IHPSG13_FILLCAP4 +XI0<1> VDD VSS / RSC_IHPSG13_FILLCAP4 +XI1 VDD VSS / RSC_IHPSG13_FILLCAP8 +.ENDS +.SUBCKT RM_IHPSG13_256x32_c2_2P_WLDRV16X4 A<15> A<14> A<13> A<12> A<11> A<10> A<9> A<8> ++ A<7> A<6> A<5> A<4> A<3> A<2> A<1> A<0> Z<15> Z<14> Z<13> Z<12> Z<11> Z<10> ++ Z<9> Z<8> Z<7> Z<6> Z<5> Z<4> Z<3> Z<2> Z<1> Z<0> VDD VSS +XBUF<15> A<15> Z<15> VDD VSS / RSC_IHPSG13_WLDRVX4 +XBUF<14> A<14> Z<14> VDD VSS / RSC_IHPSG13_WLDRVX4 +XBUF<13> A<13> Z<13> VDD VSS / RSC_IHPSG13_WLDRVX4 +XBUF<12> A<12> Z<12> VDD VSS / RSC_IHPSG13_WLDRVX4 +XBUF<11> A<11> Z<11> VDD VSS / RSC_IHPSG13_WLDRVX4 +XBUF<10> A<10> Z<10> VDD VSS / RSC_IHPSG13_WLDRVX4 +XBUF<9> A<9> Z<9> VDD VSS / RSC_IHPSG13_WLDRVX4 +XBUF<8> A<8> Z<8> VDD VSS / RSC_IHPSG13_WLDRVX4 +XBUF<7> A<7> Z<7> VDD VSS / RSC_IHPSG13_WLDRVX4 +XBUF<6> A<6> Z<6> VDD VSS / RSC_IHPSG13_WLDRVX4 +XBUF<5> A<5> Z<5> VDD VSS / RSC_IHPSG13_WLDRVX4 +XBUF<4> A<4> Z<4> VDD VSS / RSC_IHPSG13_WLDRVX4 +XBUF<3> A<3> Z<3> VDD VSS / RSC_IHPSG13_WLDRVX4 +XBUF<2> A<2> Z<2> VDD VSS / RSC_IHPSG13_WLDRVX4 +XBUF<1> A<1> Z<1> VDD VSS / RSC_IHPSG13_WLDRVX4 +XBUF<0> A<0> Z<0> VDD VSS / RSC_IHPSG13_WLDRVX4 +.ENDS +.SUBCKT RM_IHPSG13_256x32_c2_2P_ROWDEC8 ADDR_N_I<7> ADDR_N_I<6> ADDR_N_I<5> ADDR_N_I<4> ++ ADDR_N_I<3> ADDR_N_I<2> ADDR_N_I<1> ADDR_N_I<0> CS_I ECLK_I WL_O<255> ++ WL_O<254> WL_O<253> WL_O<252> WL_O<251> WL_O<250> WL_O<249> WL_O<248> ++ WL_O<247> WL_O<246> WL_O<245> WL_O<244> WL_O<243> WL_O<242> WL_O<241> ++ WL_O<240> WL_O<239> WL_O<238> WL_O<237> WL_O<236> WL_O<235> WL_O<234> ++ WL_O<233> WL_O<232> WL_O<231> WL_O<230> WL_O<229> WL_O<228> WL_O<227> ++ WL_O<226> WL_O<225> WL_O<224> WL_O<223> WL_O<222> WL_O<221> WL_O<220> ++ WL_O<219> WL_O<218> WL_O<217> WL_O<216> WL_O<215> WL_O<214> WL_O<213> ++ WL_O<212> WL_O<211> WL_O<210> WL_O<209> WL_O<208> WL_O<207> WL_O<206> ++ WL_O<205> WL_O<204> WL_O<203> WL_O<202> WL_O<201> WL_O<200> WL_O<199> ++ WL_O<198> WL_O<197> WL_O<196> WL_O<195> WL_O<194> WL_O<193> WL_O<192> ++ WL_O<191> WL_O<190> WL_O<189> WL_O<188> WL_O<187> WL_O<186> WL_O<185> ++ WL_O<184> WL_O<183> WL_O<182> WL_O<181> WL_O<180> WL_O<179> WL_O<178> ++ WL_O<177> WL_O<176> WL_O<175> WL_O<174> WL_O<173> WL_O<172> WL_O<171> ++ WL_O<170> WL_O<169> WL_O<168> WL_O<167> WL_O<166> WL_O<165> WL_O<164> ++ WL_O<163> WL_O<162> WL_O<161> WL_O<160> WL_O<159> WL_O<158> WL_O<157> ++ WL_O<156> WL_O<155> WL_O<154> WL_O<153> WL_O<152> WL_O<151> WL_O<150> ++ WL_O<149> WL_O<148> WL_O<147> WL_O<146> WL_O<145> WL_O<144> WL_O<143> ++ WL_O<142> WL_O<141> WL_O<140> WL_O<139> WL_O<138> WL_O<137> WL_O<136> ++ WL_O<135> WL_O<134> WL_O<133> WL_O<132> WL_O<131> WL_O<130> WL_O<129> ++ WL_O<128> WL_O<127> WL_O<126> WL_O<125> WL_O<124> WL_O<123> WL_O<122> ++ WL_O<121> WL_O<120> WL_O<119> WL_O<118> WL_O<117> WL_O<116> WL_O<115> ++ WL_O<114> WL_O<113> WL_O<112> WL_O<111> WL_O<110> WL_O<109> WL_O<108> ++ WL_O<107> WL_O<106> WL_O<105> WL_O<104> WL_O<103> WL_O<102> WL_O<101> ++ WL_O<100> WL_O<99> WL_O<98> WL_O<97> WL_O<96> WL_O<95> WL_O<94> WL_O<93> ++ WL_O<92> WL_O<91> WL_O<90> WL_O<89> WL_O<88> WL_O<87> WL_O<86> WL_O<85> ++ WL_O<84> WL_O<83> WL_O<82> WL_O<81> WL_O<80> WL_O<79> WL_O<78> WL_O<77> ++ WL_O<76> WL_O<75> WL_O<74> WL_O<73> WL_O<72> WL_O<71> WL_O<70> WL_O<69> ++ WL_O<68> WL_O<67> WL_O<66> WL_O<65> WL_O<64> WL_O<63> WL_O<62> WL_O<61> ++ WL_O<60> WL_O<59> WL_O<58> WL_O<57> WL_O<56> WL_O<55> WL_O<54> WL_O<53> ++ WL_O<52> WL_O<51> WL_O<50> WL_O<49> WL_O<48> WL_O<47> WL_O<46> WL_O<45> ++ WL_O<44> WL_O<43> WL_O<42> WL_O<41> WL_O<40> WL_O<39> WL_O<38> WL_O<37> ++ WL_O<36> WL_O<35> WL_O<34> WL_O<33> WL_O<32> WL_O<31> WL_O<30> WL_O<29> ++ WL_O<28> WL_O<27> WL_O<26> WL_O<25> WL_O<24> WL_O<23> WL_O<22> WL_O<21> ++ WL_O<20> WL_O<19> WL_O<18> WL_O<17> WL_O<16> WL_O<15> WL_O<14> WL_O<13> ++ WL_O<12> WL_O<11> WL_O<10> WL_O<9> WL_O<8> WL_O<7> WL_O<6> WL_O<5> WL_O<4> ++ WL_O<3> WL_O<2> WL_O<1> WL_O<0> VDD VSS +XDEC11<4> ADDR_N_I<7> ADDR_N_I<6> CS_I CS04<3> VDD VSS / ++ RM_IHPSG13_256x32_c2_2P_DEC03 +XDEC11<3> ADDR_N_I<5> ADDR_N_I<4> CS04<3> CS00<15> VDD VSS / ++ RM_IHPSG13_256x32_c2_2P_DEC03 +XDEC11<2> ADDR_N_I<5> ADDR_N_I<4> CS04<2> CS00<11> VDD VSS / ++ RM_IHPSG13_256x32_c2_2P_DEC03 +XDEC11<1> ADDR_N_I<5> ADDR_N_I<4> CS04<1> CS00<7> VDD VSS / ++ RM_IHPSG13_256x32_c2_2P_DEC03 +XDEC11<0> ADDR_N_I<5> ADDR_N_I<4> CS04<0> CS00<3> VDD VSS / ++ RM_IHPSG13_256x32_c2_2P_DEC03 +XSEL<15> ADDR_N_I<3> ADDR_N_I<2> ADDR_N_I<1> ADDR_N_I<0> CS00<15> ECLK_H<15> ++ ECLK_H<16> ECLK_B<15> ECLK_B<16> WL_O<255> WL_O<254> WL_O<253> WL_O<252> ++ WL_O<251> WL_O<250> WL_O<249> WL_O<248> WL_O<247> WL_O<246> WL_O<245> ++ WL_O<244> WL_O<243> WL_O<242> WL_O<241> WL_O<240> VDD VSS / ++ RM_IHPSG13_256x32_c2_2P_DEC04 +XSEL<14> ADDR_N_I<3> ADDR_N_I<2> ADDR_N_I<1> ADDR_N_I<0> CS00<14> ECLK_H<14> ++ ECLK_H<15> ECLK_B<14> ECLK_B<15> WL_O<239> WL_O<238> WL_O<237> WL_O<236> ++ WL_O<235> WL_O<234> WL_O<233> WL_O<232> WL_O<231> WL_O<230> WL_O<229> ++ WL_O<228> WL_O<227> WL_O<226> WL_O<225> WL_O<224> VDD VSS / ++ RM_IHPSG13_256x32_c2_2P_DEC04 +XSEL<13> ADDR_N_I<3> ADDR_N_I<2> ADDR_N_I<1> ADDR_N_I<0> CS00<13> ECLK_H<13> ++ ECLK_H<14> ECLK_B<13> ECLK_B<14> WL_O<223> WL_O<222> WL_O<221> WL_O<220> ++ WL_O<219> WL_O<218> WL_O<217> WL_O<216> WL_O<215> WL_O<214> WL_O<213> ++ WL_O<212> WL_O<211> WL_O<210> WL_O<209> WL_O<208> VDD VSS / ++ RM_IHPSG13_256x32_c2_2P_DEC04 +XSEL<12> ADDR_N_I<3> ADDR_N_I<2> ADDR_N_I<1> ADDR_N_I<0> CS00<12> ECLK_H<12> ++ ECLK_H<13> ECLK_B<12> ECLK_B<13> WL_O<207> WL_O<206> WL_O<205> WL_O<204> ++ WL_O<203> WL_O<202> WL_O<201> WL_O<200> WL_O<199> WL_O<198> WL_O<197> ++ WL_O<196> WL_O<195> WL_O<194> WL_O<193> WL_O<192> VDD VSS / ++ RM_IHPSG13_256x32_c2_2P_DEC04 +XSEL<11> ADDR_N_I<3> ADDR_N_I<2> ADDR_N_I<1> ADDR_N_I<0> CS00<11> ECLK_H<11> ++ ECLK_H<12> ECLK_B<11> ECLK_B<12> WL_O<191> WL_O<190> WL_O<189> WL_O<188> ++ WL_O<187> WL_O<186> WL_O<185> WL_O<184> WL_O<183> WL_O<182> WL_O<181> ++ WL_O<180> WL_O<179> WL_O<178> WL_O<177> WL_O<176> VDD VSS / ++ RM_IHPSG13_256x32_c2_2P_DEC04 +XSEL<10> ADDR_N_I<3> ADDR_N_I<2> ADDR_N_I<1> ADDR_N_I<0> CS00<10> ECLK_H<10> ++ ECLK_H<11> ECLK_B<10> ECLK_B<11> WL_O<175> WL_O<174> WL_O<173> WL_O<172> ++ WL_O<171> WL_O<170> WL_O<169> WL_O<168> WL_O<167> WL_O<166> WL_O<165> ++ WL_O<164> WL_O<163> WL_O<162> WL_O<161> WL_O<160> VDD VSS / ++ RM_IHPSG13_256x32_c2_2P_DEC04 +XSEL<9> ADDR_N_I<3> ADDR_N_I<2> ADDR_N_I<1> ADDR_N_I<0> CS00<9> ECLK_H<9> ++ ECLK_H<10> ECLK_B<9> ECLK_B<10> WL_O<159> WL_O<158> WL_O<157> WL_O<156> ++ WL_O<155> WL_O<154> WL_O<153> WL_O<152> WL_O<151> WL_O<150> WL_O<149> ++ WL_O<148> WL_O<147> WL_O<146> WL_O<145> WL_O<144> VDD VSS / ++ RM_IHPSG13_256x32_c2_2P_DEC04 +XSEL<8> ADDR_N_I<3> ADDR_N_I<2> ADDR_N_I<1> ADDR_N_I<0> CS00<8> ECLK_H<8> ++ ECLK_H<9> ECLK_B<8> ECLK_B<9> WL_O<143> WL_O<142> WL_O<141> WL_O<140> ++ WL_O<139> WL_O<138> WL_O<137> WL_O<136> WL_O<135> WL_O<134> WL_O<133> ++ WL_O<132> WL_O<131> WL_O<130> WL_O<129> WL_O<128> VDD VSS / ++ RM_IHPSG13_256x32_c2_2P_DEC04 +XSEL<7> ADDR_N_I<3> ADDR_N_I<2> ADDR_N_I<1> ADDR_N_I<0> CS00<7> ECLK_H<7> ++ ECLK_H<8> ECLK_B<7> ECLK_B<8> WL_O<127> WL_O<126> WL_O<125> WL_O<124> ++ WL_O<123> WL_O<122> WL_O<121> WL_O<120> WL_O<119> WL_O<118> WL_O<117> ++ WL_O<116> WL_O<115> WL_O<114> WL_O<113> WL_O<112> VDD VSS / ++ RM_IHPSG13_256x32_c2_2P_DEC04 +XSEL<6> ADDR_N_I<3> ADDR_N_I<2> ADDR_N_I<1> ADDR_N_I<0> CS00<6> ECLK_H<6> ++ ECLK_H<7> ECLK_B<6> ECLK_B<7> WL_O<111> WL_O<110> WL_O<109> WL_O<108> ++ WL_O<107> WL_O<106> WL_O<105> WL_O<104> WL_O<103> WL_O<102> WL_O<101> ++ WL_O<100> WL_O<99> WL_O<98> WL_O<97> WL_O<96> VDD VSS / ++ RM_IHPSG13_256x32_c2_2P_DEC04 +XSEL<5> ADDR_N_I<3> ADDR_N_I<2> ADDR_N_I<1> ADDR_N_I<0> CS00<5> ECLK_H<5> ++ ECLK_H<6> ECLK_B<5> ECLK_B<6> WL_O<95> WL_O<94> WL_O<93> WL_O<92> WL_O<91> ++ WL_O<90> WL_O<89> WL_O<88> WL_O<87> WL_O<86> WL_O<85> WL_O<84> WL_O<83> ++ WL_O<82> WL_O<81> WL_O<80> VDD VSS / RM_IHPSG13_256x32_c2_2P_DEC04 +XSEL<4> ADDR_N_I<3> ADDR_N_I<2> ADDR_N_I<1> ADDR_N_I<0> CS00<4> ECLK_H<4> ++ ECLK_H<5> ECLK_B<4> ECLK_B<5> WL_O<79> WL_O<78> WL_O<77> WL_O<76> WL_O<75> ++ WL_O<74> WL_O<73> WL_O<72> WL_O<71> WL_O<70> WL_O<69> WL_O<68> WL_O<67> ++ WL_O<66> WL_O<65> WL_O<64> VDD VSS / RM_IHPSG13_256x32_c2_2P_DEC04 +XSEL<3> ADDR_N_I<3> ADDR_N_I<2> ADDR_N_I<1> ADDR_N_I<0> CS00<3> ECLK_H<3> ++ ECLK_H<4> ECLK_B<3> ECLK_B<4> WL_O<63> WL_O<62> WL_O<61> WL_O<60> WL_O<59> ++ WL_O<58> WL_O<57> WL_O<56> WL_O<55> WL_O<54> WL_O<53> WL_O<52> WL_O<51> ++ WL_O<50> WL_O<49> WL_O<48> VDD VSS / RM_IHPSG13_256x32_c2_2P_DEC04 +XSEL<2> ADDR_N_I<3> ADDR_N_I<2> ADDR_N_I<1> ADDR_N_I<0> CS00<2> ECLK_H<2> ++ ECLK_H<3> ECLK_B<2> ECLK_B<3> WL_O<47> WL_O<46> WL_O<45> WL_O<44> WL_O<43> ++ WL_O<42> WL_O<41> WL_O<40> WL_O<39> WL_O<38> WL_O<37> WL_O<36> WL_O<35> ++ WL_O<34> WL_O<33> WL_O<32> VDD VSS / RM_IHPSG13_256x32_c2_2P_DEC04 +XSEL<1> ADDR_N_I<3> ADDR_N_I<2> ADDR_N_I<1> ADDR_N_I<0> CS00<1> ECLK_H<1> ++ ECLK_H<2> ECLK_B<1> ECLK_B<2> WL_O<31> WL_O<30> WL_O<29> WL_O<28> WL_O<27> ++ WL_O<26> WL_O<25> WL_O<24> WL_O<23> WL_O<22> WL_O<21> WL_O<20> WL_O<19> ++ WL_O<18> WL_O<17> WL_O<16> VDD VSS / RM_IHPSG13_256x32_c2_2P_DEC04 +XSEL<0> ADDR_N_I<3> ADDR_N_I<2> ADDR_N_I<1> ADDR_N_I<0> CS00<0> ECLK_I ++ ECLK_H<1> ECLK_B<0> ECLK_B<1> WL_O<15> WL_O<14> WL_O<13> WL_O<12> WL_O<11> ++ WL_O<10> WL_O<9> WL_O<8> WL_O<7> WL_O<6> WL_O<5> WL_O<4> WL_O<3> WL_O<2> ++ WL_O<1> WL_O<0> VDD VSS / RM_IHPSG13_256x32_c2_2P_DEC04 +XDEC10<4> ADDR_N_I<7> ADDR_N_I<6> CS_I CS04<2> VDD VSS / ++ RM_IHPSG13_256x32_c2_2P_DEC02 +XDEC10<3> ADDR_N_I<5> ADDR_N_I<4> CS04<3> CS00<14> VDD VSS / ++ RM_IHPSG13_256x32_c2_2P_DEC02 +XDEC10<2> ADDR_N_I<5> ADDR_N_I<4> CS04<2> CS00<10> VDD VSS / ++ RM_IHPSG13_256x32_c2_2P_DEC02 +XDEC10<1> ADDR_N_I<5> ADDR_N_I<4> CS04<1> CS00<6> VDD VSS / ++ RM_IHPSG13_256x32_c2_2P_DEC02 +XDEC10<0> ADDR_N_I<5> ADDR_N_I<4> CS04<0> CS00<2> VDD VSS / ++ RM_IHPSG13_256x32_c2_2P_DEC02 +XL2<132> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<131> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<130> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<129> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<128> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<127> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<126> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<125> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<124> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<123> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<122> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<121> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<120> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<119> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<118> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<117> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<116> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<115> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<114> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<113> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<112> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<111> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<110> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<109> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<108> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<107> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<106> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<105> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<104> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<103> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<102> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<101> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<100> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<99> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<98> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<97> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<96> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<95> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<94> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<93> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<92> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<91> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<90> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<89> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<88> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<87> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<86> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<85> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<84> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<83> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<82> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<81> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<80> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<79> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<78> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<77> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<76> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<75> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<74> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<73> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<72> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<71> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<70> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<69> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<68> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<67> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<66> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<65> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<64> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<63> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<62> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<61> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<60> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<59> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<58> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<57> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<56> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<55> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<54> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<53> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<52> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<51> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<50> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<49> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<48> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<47> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<46> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<45> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<44> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<43> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<42> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<41> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<40> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<39> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<38> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<37> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<36> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<35> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<34> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<33> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<32> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<31> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<30> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<29> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<28> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<27> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<26> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<25> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<24> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<23> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<22> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<21> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<20> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<19> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<18> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<17> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<16> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<15> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<14> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<13> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<12> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<11> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<10> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<9> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<8> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<7> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<6> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<5> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<4> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<3> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<2> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<1> VDD VSS / RSC_IHPSG13_FILLCAP8 +XDEC00<4> ADDR_N_I<7> ADDR_N_I<6> CS_I CS04<0> VDD VSS / ++ RM_IHPSG13_256x32_c2_2P_DEC00 +XDEC00<3> ADDR_N_I<5> ADDR_N_I<4> CS04<3> CS00<12> VDD VSS / ++ RM_IHPSG13_256x32_c2_2P_DEC00 +XDEC00<2> ADDR_N_I<5> ADDR_N_I<4> CS04<2> CS00<8> VDD VSS / ++ RM_IHPSG13_256x32_c2_2P_DEC00 +XDEC00<1> ADDR_N_I<5> ADDR_N_I<4> CS04<1> CS00<4> VDD VSS / ++ RM_IHPSG13_256x32_c2_2P_DEC00 +XDEC00<0> ADDR_N_I<5> ADDR_N_I<4> CS04<0> CS00<0> VDD VSS / ++ RM_IHPSG13_256x32_c2_2P_DEC00 +XDEC01<4> ADDR_N_I<7> ADDR_N_I<6> CS_I CS04<1> VDD VSS / ++ RM_IHPSG13_256x32_c2_2P_DEC01 +XDEC01<3> ADDR_N_I<5> ADDR_N_I<4> CS04<3> CS00<13> VDD VSS / ++ RM_IHPSG13_256x32_c2_2P_DEC01 +XDEC01<2> ADDR_N_I<5> ADDR_N_I<4> CS04<2> CS00<9> VDD VSS / ++ RM_IHPSG13_256x32_c2_2P_DEC01 +XDEC01<1> ADDR_N_I<5> ADDR_N_I<4> CS04<1> CS00<5> VDD VSS / ++ RM_IHPSG13_256x32_c2_2P_DEC01 +XDEC01<0> ADDR_N_I<5> ADDR_N_I<4> CS04<0> CS00<1> VDD VSS / ++ RM_IHPSG13_256x32_c2_2P_DEC01 +.ENDS +.SUBCKT RM_IHPSG13_256x32_c2_2P_ROWREG8 ACLK_N_I ADDR_I<7> ADDR_I<6> ADDR_I<5> ADDR_I<4> ++ ADDR_I<3> ADDR_I<2> ADDR_I<1> ADDR_I<0> ADDR_N_O<7> ADDR_N_O<6> ADDR_N_O<5> ++ ADDR_N_O<4> ADDR_N_O<3> ADDR_N_O<2> ADDR_N_O<1> ADDR_N_O<0> BIST_ADDR_I<7> ++ BIST_ADDR_I<6> BIST_ADDR_I<5> BIST_ADDR_I<4> BIST_ADDR_I<3> BIST_ADDR_I<2> ++ BIST_ADDR_I<1> BIST_ADDR_I<0> BIST_EN_I VDD VSS +XINV<7> q_int<7> qn_int<7> VDD VSS / RSC_IHPSG13_CINVX2 +XINV<6> q_int<6> qn_int<6> VDD VSS / RSC_IHPSG13_CINVX2 +XINV<5> q_int<5> qn_int<5> VDD VSS / RSC_IHPSG13_CINVX2 +XINV<4> q_int<4> qn_int<4> VDD VSS / RSC_IHPSG13_CINVX2 +XINV<3> q_int<3> qn_int<3> VDD VSS / RSC_IHPSG13_CINVX2 +XINV<2> q_int<2> qn_int<2> VDD VSS / RSC_IHPSG13_CINVX2 +XINV<1> q_int<1> qn_int<1> VDD VSS / RSC_IHPSG13_CINVX2 +XINV<0> q_int<0> qn_int<0> VDD VSS / RSC_IHPSG13_CINVX2 +XDRV<7> qn_int<7> ADDR_N_O<7> VDD VSS / RSC_IHPSG13_CINVX8 +XDRV<6> qn_int<6> ADDR_N_O<6> VDD VSS / RSC_IHPSG13_CINVX8 +XDRV<5> qn_int<5> ADDR_N_O<5> VDD VSS / RSC_IHPSG13_CINVX8 +XDRV<4> qn_int<4> ADDR_N_O<4> VDD VSS / RSC_IHPSG13_CINVX8 +XDRV<3> qn_int<3> ADDR_N_O<3> VDD VSS / RSC_IHPSG13_CINVX8 +XDRV<2> qn_int<2> ADDR_N_O<2> VDD VSS / RSC_IHPSG13_CINVX8 +XDRV<1> qn_int<1> ADDR_N_O<1> VDD VSS / RSC_IHPSG13_CINVX8 +XDRV<0> qn_int<0> ADDR_N_O<0> VDD VSS / RSC_IHPSG13_CINVX8 +XDFF<7> BIST_EN_I BIST_ADDR_I<7> ACLK_N_I ADDR_I<7> q_int<7> net2<0> VDD ++ VSS / RSC_IHPSG13_DFNQMX2IX1 +XDFF<6> BIST_EN_I BIST_ADDR_I<6> ACLK_N_I ADDR_I<6> q_int<6> net2<1> VDD ++ VSS / RSC_IHPSG13_DFNQMX2IX1 +XDFF<5> BIST_EN_I BIST_ADDR_I<5> ACLK_N_I ADDR_I<5> q_int<5> net2<2> VDD ++ VSS / RSC_IHPSG13_DFNQMX2IX1 +XDFF<4> BIST_EN_I BIST_ADDR_I<4> ACLK_N_I ADDR_I<4> q_int<4> net2<3> VDD ++ VSS / RSC_IHPSG13_DFNQMX2IX1 +XDFF<3> BIST_EN_I BIST_ADDR_I<3> ACLK_N_I ADDR_I<3> q_int<3> net2<4> VDD ++ VSS / RSC_IHPSG13_DFNQMX2IX1 +XDFF<2> BIST_EN_I BIST_ADDR_I<2> ACLK_N_I ADDR_I<2> q_int<2> net2<5> VDD ++ VSS / RSC_IHPSG13_DFNQMX2IX1 +XDFF<1> BIST_EN_I BIST_ADDR_I<1> ACLK_N_I ADDR_I<1> q_int<1> net2<6> VDD ++ VSS / RSC_IHPSG13_DFNQMX2IX1 +XDFF<0> BIST_EN_I BIST_ADDR_I<0> ACLK_N_I ADDR_I<0> q_int<0> net2<7> VDD ++ VSS / RSC_IHPSG13_DFNQMX2IX1 +XI11<4> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI11<3> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI11<2> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI11<1> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI10 VDD VSS / RSC_IHPSG13_FILLCAP4 +.ENDS +.SUBCKT RM_IHPSG13_256x32_c2_2P_COLDEC4 ACLK_N ADDR<3> ADDR<2> ADDR<1> ADDR<0> ++ ADDR_COL<1> ADDR_COL<0> ADDR_DEC<7> ADDR_DEC<6> ADDR_DEC<5> ADDR_DEC<4> ++ ADDR_DEC<3> ADDR_DEC<2> ADDR_DEC<1> ADDR_DEC<0> BIST_ADDR<3> BIST_ADDR<2> ++ BIST_ADDR<1> BIST_ADDR<0> BIST_EN_I VDD VSS +XI1<7> PADR<0> PADR<1> PADR<2> addr_n<7> VDD VSS / RSC_IHPSG13_NAND3X2 +XI1<6> NADR<0> PADR<1> PADR<2> addr_n<6> VDD VSS / RSC_IHPSG13_NAND3X2 +XI1<5> PADR<0> NADR<1> PADR<2> addr_n<5> VDD VSS / RSC_IHPSG13_NAND3X2 +XI1<4> NADR<0> NADR<1> PADR<2> addr_n<4> VDD VSS / RSC_IHPSG13_NAND3X2 +XI1<3> PADR<0> PADR<1> NADR<2> addr_n<3> VDD VSS / RSC_IHPSG13_NAND3X2 +XI1<2> NADR<0> PADR<1> NADR<2> addr_n<2> VDD VSS / RSC_IHPSG13_NAND3X2 +XI1<1> PADR<0> NADR<1> NADR<2> addr_n<1> VDD VSS / RSC_IHPSG13_NAND3X2 +XI1<0> NADR<0> NADR<1> NADR<2> addr_n<0> VDD VSS / RSC_IHPSG13_NAND3X2 +XDFF<3> BIST_EN_I BIST_ADDR<3> ACLK_N ADDR<3> addr_int net12<0> VDD ++ VSS / RSC_IHPSG13_DFNQMX2IX1 +XDFF<2> BIST_EN_I BIST_ADDR<2> ACLK_N ADDR<2> padr_int<2> net12<1> VDD ++ VSS / RSC_IHPSG13_DFNQMX2IX1 +XDFF<1> BIST_EN_I BIST_ADDR<1> ACLK_N ADDR<1> padr_int<1> net12<2> VDD ++ VSS / RSC_IHPSG13_DFNQMX2IX1 +XDFF<0> BIST_EN_I BIST_ADDR<0> ACLK_N ADDR<0> padr_int<0> net12<3> VDD ++ VSS / RSC_IHPSG13_DFNQMX2IX1 +XI17<4> VDD VSS / RSC_IHPSG13_FILLCAP4 +XI17<3> VDD VSS / RSC_IHPSG13_FILLCAP4 +XI17<2> VDD VSS / RSC_IHPSG13_FILLCAP4 +XI17<1> VDD VSS / RSC_IHPSG13_FILLCAP4 +XI13<2> NADR<2> PADR<2> VDD VSS / RSC_IHPSG13_INVX2 +XI13<1> NADR<1> PADR<1> VDD VSS / RSC_IHPSG13_INVX2 +XI13<0> NADR<0> PADR<0> VDD VSS / RSC_IHPSG13_INVX2 +XI2<7> addr_n<7> ADDR_DEC<7> VDD VSS / RSC_IHPSG13_INVX2 +XI2<6> addr_n<6> ADDR_DEC<6> VDD VSS / RSC_IHPSG13_INVX2 +XI2<5> addr_n<5> ADDR_DEC<5> VDD VSS / RSC_IHPSG13_INVX2 +XI2<4> addr_n<4> ADDR_DEC<4> VDD VSS / RSC_IHPSG13_INVX2 +XI2<3> addr_n<3> ADDR_DEC<3> VDD VSS / RSC_IHPSG13_INVX2 +XI2<2> addr_n<2> ADDR_DEC<2> VDD VSS / RSC_IHPSG13_INVX2 +XI2<1> addr_n<1> ADDR_DEC<1> VDD VSS / RSC_IHPSG13_INVX2 +XI2<0> addr_n<0> ADDR_DEC<0> VDD VSS / RSC_IHPSG13_INVX2 +XI3<2> padr_int<2> NADR<2> VDD VSS / RSC_IHPSG13_INVX2 +XI3<1> padr_int<1> NADR<1> VDD VSS / RSC_IHPSG13_INVX2 +XI3<0> padr_int<0> NADR<0> VDD VSS / RSC_IHPSG13_INVX2 +XI14 addr_int ADDR_COL<0> VDD VSS / RSC_IHPSG13_CBUFX2 +XI16<8> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI16<7> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI16<6> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI16<5> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI16<4> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI16<3> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI16<2> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI16<1> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI15 ADDR_COL<1> VDD VSS / RSC_IHPSG13_TIEL +.ENDS +.SUBCKT RM_IHPSG13_256x32_c2_2P_COLCTRL4 A_ADDR_COL A_ADDR_DEC<7> A_ADDR_DEC<6> ++ A_ADDR_DEC<5> A_ADDR_DEC<4> A_ADDR_DEC<3> A_ADDR_DEC<2> A_ADDR_DEC<1> ++ A_ADDR_DEC<0> A_BIST_BM_I A_BIST_DW_I A_BIST_EN_I A_BLC<15> A_BLC<14> ++ A_BLC<13> A_BLC<12> A_BLC<11> A_BLC<10> A_BLC<9> A_BLC<8> A_BLC<7> A_BLC<6> ++ A_BLC<5> A_BLC<4> A_BLC<3> A_BLC<2> A_BLC<1> A_BLC<0> A_BLT<15> A_BLT<14> ++ A_BLT<13> A_BLT<12> A_BLT<11> A_BLT<10> A_BLT<9> A_BLT<8> A_BLT<7> A_BLT<6> ++ A_BLT<5> A_BLT<4> A_BLT<3> A_BLT<2> A_BLT<1> A_BLT<0> A_BM_I A_DCLK_B_L ++ A_DCLK_B_R A_DCLK_L A_DCLK_R A_DR_O A_DW_I A_RCLK_B_L A_RCLK_B_R A_RCLK_L ++ A_RCLK_R A_TIEH_O A_WCLK_B_L A_WCLK_B_R A_WCLK_L A_WCLK_R B_ADDR_COL ++ B_ADDR_DEC<7> B_ADDR_DEC<6> B_ADDR_DEC<5> B_ADDR_DEC<4> B_ADDR_DEC<3> ++ B_ADDR_DEC<2> B_ADDR_DEC<1> B_ADDR_DEC<0> B_BIST_BM_I B_BIST_DW_I ++ B_BIST_EN_I B_BLC<15> B_BLC<14> B_BLC<13> B_BLC<12> B_BLC<11> B_BLC<10> ++ B_BLC<9> B_BLC<8> B_BLC<7> B_BLC<6> B_BLC<5> B_BLC<4> B_BLC<3> B_BLC<2> ++ B_BLC<1> B_BLC<0> B_BLT<15> B_BLT<14> B_BLT<13> B_BLT<12> B_BLT<11> ++ B_BLT<10> B_BLT<9> B_BLT<8> B_BLT<7> B_BLT<6> B_BLT<5> B_BLT<4> B_BLT<3> ++ B_BLT<2> B_BLT<1> B_BLT<0> B_BM_I B_DCLK_B_L B_DCLK_B_R B_DCLK_L B_DCLK_R ++ B_DR_O B_DW_I B_RCLK_B_L B_RCLK_B_R B_RCLK_L B_RCLK_R B_TIEH_O B_WCLK_B_L ++ B_WCLK_B_R B_WCLK_L B_WCLK_R VDD VSS +XB_I80 B_RCLK_B_L B_WCLK_B_L net041 VDD VSS / RSC_IHPSG13_AND2X2 +XA_I80 A_RCLK_B_L A_WCLK_B_L net21 VDD VSS / RSC_IHPSG13_AND2X2 +XB_I76 B_DI_N B_DO_WRITE_P B_WR_ZERO VDD VSS / RSC_IHPSG13_AND2X4 +XB_I75 B_DI_R B_DO_WRITE_P B_WR_ONE VDD VSS / RSC_IHPSG13_AND2X4 +XA_I76 A_DI_N A_DO_WRITE_P A_WR_ZERO VDD VSS / RSC_IHPSG13_AND2X4 +XA_I75 A_DI_R A_DO_WRITE_P A_WR_ONE VDD VSS / RSC_IHPSG13_AND2X4 +XI_FILL4<26> VDD VSS / RSC_IHPSG13_FILLCAP4 +XI_FILL4<25> VDD VSS / RSC_IHPSG13_FILLCAP4 +XI_FILL4<24> VDD VSS / RSC_IHPSG13_FILLCAP4 +XI_FILL4<23> VDD VSS / RSC_IHPSG13_FILLCAP4 +XI_FILL4<22> VDD VSS / RSC_IHPSG13_FILLCAP4 +XI_FILL4<21> VDD VSS / RSC_IHPSG13_FILLCAP4 +XI_FILL4<20> VDD VSS / RSC_IHPSG13_FILLCAP4 +XI_FILL4<19> VDD VSS / RSC_IHPSG13_FILLCAP4 +XI_FILL4<18> VDD VSS / RSC_IHPSG13_FILLCAP4 +XI_FILL4<17> VDD VSS / RSC_IHPSG13_FILLCAP4 +XI_FILL4<16> VDD VSS / RSC_IHPSG13_FILLCAP4 +XI_FILL4<15> VDD VSS / RSC_IHPSG13_FILLCAP4 +XI_FILL4<14> VDD VSS / RSC_IHPSG13_FILLCAP4 +XI_FILL4<13> VDD VSS / RSC_IHPSG13_FILLCAP4 +XI_FILL4<12> VDD VSS / RSC_IHPSG13_FILLCAP4 +XI_FILL4<11> VDD VSS / RSC_IHPSG13_FILLCAP4 +XI_FILL4<10> VDD VSS / RSC_IHPSG13_FILLCAP4 +XI_FILL4<9> VDD VSS / RSC_IHPSG13_FILLCAP4 +XI_FILL4<8> VDD VSS / RSC_IHPSG13_FILLCAP4 +XI_FILL4<7> VDD VSS / RSC_IHPSG13_FILLCAP4 +XI_FILL4<6> VDD VSS / RSC_IHPSG13_FILLCAP4 +XI_FILL4<5> VDD VSS / RSC_IHPSG13_FILLCAP4 +XI_FILL4<4> VDD VSS / RSC_IHPSG13_FILLCAP4 +XI_FILL4<3> VDD VSS / RSC_IHPSG13_FILLCAP4 +XI_FILL4<2> VDD VSS / RSC_IHPSG13_FILLCAP4 +XI_FILL4<1> VDD VSS / RSC_IHPSG13_FILLCAP4 +XB_I69 B_DCLK_L B_DCLK_B_L VDD VSS / RSC_IHPSG13_CINVX4 +XB_I50 B_WCLK_L B_WCLK_B_L VDD VSS / RSC_IHPSG13_CINVX4 +XB_EBUF B_RCLK_L B_RCLK_B_L VDD VSS / RSC_IHPSG13_CINVX4 +XB_INV<1> B_N0 B_P0 VDD VSS / RSC_IHPSG13_CINVX4 +XB_INV<0> B_ADDR_COL B_N0 VDD VSS / RSC_IHPSG13_CINVX4 +XA_I69 A_DCLK_L A_DCLK_B_L VDD VSS / RSC_IHPSG13_CINVX4 +XA_I50 A_WCLK_L A_WCLK_B_L VDD VSS / RSC_IHPSG13_CINVX4 +XA_EBUF A_RCLK_L A_RCLK_B_L VDD VSS / RSC_IHPSG13_CINVX4 +XA_INV<1> A_N0 A_P0 VDD VSS / RSC_IHPSG13_CINVX4 +XA_INV<0> A_ADDR_COL A_N0 VDD VSS / RSC_IHPSG13_CINVX4 +XB_I81<1> net041 B_PRE_N VDD VSS / RSC_IHPSG13_CINVX4_WN +XB_I81<0> net041 B_PRE_N VDD VSS / RSC_IHPSG13_CINVX4_WN +XA_I81<1> net21 A_PRE_N VDD VSS / RSC_IHPSG13_CINVX4_WN +XA_I81<0> net21 A_PRE_N VDD VSS / RSC_IHPSG13_CINVX4_WN +XA_R2 A_RCLK_L A_RCLK_R / RSC_IHPSG13_MET3RES +XA_I87 A_WCLK_L A_WCLK_R / RSC_IHPSG13_MET3RES +XA_I88 A_DCLK_L A_DCLK_R / RSC_IHPSG13_MET3RES +XA_I89 A_DCLK_B_L A_DCLK_B_R / RSC_IHPSG13_MET3RES +XA_I90 A_WCLK_B_L A_WCLK_B_R / RSC_IHPSG13_MET3RES +XA_I91 A_RCLK_B_L A_RCLK_B_R / RSC_IHPSG13_MET3RES +XB_R2 B_RCLK_L B_RCLK_R / RSC_IHPSG13_MET3RES +XB_I87 B_WCLK_L B_WCLK_R / RSC_IHPSG13_MET3RES +XB_I88 B_DCLK_L B_DCLK_R / RSC_IHPSG13_MET3RES +XB_I89 B_DCLK_B_L B_DCLK_B_R / RSC_IHPSG13_MET3RES +XB_I90 B_WCLK_B_L B_WCLK_B_R / RSC_IHPSG13_MET3RES +XB_I91 B_RCLK_B_L B_RCLK_B_R / RSC_IHPSG13_MET3RES +XA_ISENSE A_SAE A_BLC_SEL A_BLT_SEL net19 net20 VDD VSS / ++ RSC_IHPSG13_DFPQD_MSAFFX2 +XB_ISENSE B_SAE B_BLC_SEL B_BLT_SEL net037 net038 VDD VSS / ++ RSC_IHPSG13_DFPQD_MSAFFX2 +XAB_BLMUX<3> A_BLC<15> A_BLC<14> A_BLC<13> A_BLC<12> A_BLC_SEL A_BLT<15> ++ A_BLT<14> A_BLT<13> A_BLT<12> A_BLT_SEL A_PRE_N A_SEL_P<15> A_SEL_P<14> ++ A_SEL_P<13> A_SEL_P<12> A_WR_ONE A_WR_ZERO B_BLC<15> B_BLC<14> B_BLC<13> ++ B_BLC<12> B_BLC_SEL B_BLT<15> B_BLT<14> B_BLT<13> B_BLT<12> B_BLT_SEL ++ B_PRE_N B_SEL_P<15> B_SEL_P<14> B_SEL_P<13> B_SEL_P<12> B_WR_ONE B_WR_ZERO ++ VDD VSS / RM_IHPSG13_256x32_c2_2P_BLDRV +XAB_BLMUX<2> A_BLC<11> A_BLC<10> A_BLC<9> A_BLC<8> A_BLC_SEL A_BLT<11> ++ A_BLT<10> A_BLT<9> A_BLT<8> A_BLT_SEL A_PRE_N A_SEL_P<11> A_SEL_P<10> ++ A_SEL_P<9> A_SEL_P<8> A_WR_ONE A_WR_ZERO B_BLC<11> B_BLC<10> B_BLC<9> ++ B_BLC<8> B_BLC_SEL B_BLT<11> B_BLT<10> B_BLT<9> B_BLT<8> B_BLT_SEL B_PRE_N ++ B_SEL_P<11> B_SEL_P<10> B_SEL_P<9> B_SEL_P<8> B_WR_ONE B_WR_ZERO VDD ++ VSS / RM_IHPSG13_256x32_c2_2P_BLDRV +XAB_BLMUX<1> A_BLC<7> A_BLC<6> A_BLC<5> A_BLC<4> A_BLC_SEL A_BLT<7> A_BLT<6> ++ A_BLT<5> A_BLT<4> A_BLT_SEL A_PRE_N A_SEL_P<7> A_SEL_P<6> A_SEL_P<5> ++ A_SEL_P<4> A_WR_ONE A_WR_ZERO B_BLC<7> B_BLC<6> B_BLC<5> B_BLC<4> B_BLC_SEL ++ B_BLT<7> B_BLT<6> B_BLT<5> B_BLT<4> B_BLT_SEL B_PRE_N B_SEL_P<7> B_SEL_P<6> ++ B_SEL_P<5> B_SEL_P<4> B_WR_ONE B_WR_ZERO VDD VSS / ++ RM_IHPSG13_256x32_c2_2P_BLDRV +XAB_BLMUX<0> A_BLC<3> A_BLC<2> A_BLC<1> A_BLC<0> A_BLC_SEL A_BLT<3> A_BLT<2> ++ A_BLT<1> A_BLT<0> A_BLT_SEL A_PRE_N A_SEL_P<3> A_SEL_P<2> A_SEL_P<1> ++ A_SEL_P<0> A_WR_ONE A_WR_ZERO B_BLC<3> B_BLC<2> B_BLC<1> B_BLC<0> B_BLC_SEL ++ B_BLT<3> B_BLT<2> B_BLT<1> B_BLT<0> B_BLT_SEL B_PRE_N B_SEL_P<3> B_SEL_P<2> ++ B_SEL_P<1> B_SEL_P<0> B_WR_ONE B_WR_ZERO VDD VSS / ++ RM_IHPSG13_256x32_c2_2P_BLDRV +XA_I51 net19 A_DR_O VDD VSS / RSC_IHPSG13_INVX4 +XB_I51 net037 B_DR_O VDD VSS / RSC_IHPSG13_INVX4 +XA_I78 A_RCLK_B_L A_SAE VDD VSS / RSC_IHPSG13_CBUFX2 +XB_I78 B_RCLK_B_L B_SAE VDD VSS / RSC_IHPSG13_CBUFX2 +XA_DREG A_BIST_EN_I A_BIST_DW_I A_DCLK_B_L A_DW_I A_DI_R net22 VDD VSS ++ / RSC_IHPSG13_DFNQMX2IX1 +XB_DREG B_BIST_EN_I B_BIST_DW_I B_DCLK_B_L B_DW_I B_DI_R net046 VDD ++ VSS / RSC_IHPSG13_DFNQMX2IX1 +XB_BREG B_BIST_EN_I B_BIST_BM_I B_DCLK_B_L B_BM_I B_BM_R net045 VDD ++ VSS / RSC_IHPSG13_DFNQMX2IX1 +XA_BREG A_BIST_EN_I A_BIST_BM_I A_DCLK_B_L A_BM_I A_BM_R net24 VDD VSS ++ / RSC_IHPSG13_DFNQMX2IX1 +XA_DEC3INV<15> net23<0> A_SEL_P<15> VDD VSS / RSC_IHPSG13_INVX2 +XA_DEC3INV<14> net23<1> A_SEL_P<14> VDD VSS / RSC_IHPSG13_INVX2 +XA_DEC3INV<13> net23<2> A_SEL_P<13> VDD VSS / RSC_IHPSG13_INVX2 +XA_DEC3INV<12> net23<3> A_SEL_P<12> VDD VSS / RSC_IHPSG13_INVX2 +XA_DEC3INV<11> net23<4> A_SEL_P<11> VDD VSS / RSC_IHPSG13_INVX2 +XA_DEC3INV<10> net23<5> A_SEL_P<10> VDD VSS / RSC_IHPSG13_INVX2 +XA_DEC3INV<9> net23<6> A_SEL_P<9> VDD VSS / RSC_IHPSG13_INVX2 +XA_DEC3INV<8> net23<7> A_SEL_P<8> VDD VSS / RSC_IHPSG13_INVX2 +XA_DEC3INV<7> net23<8> A_SEL_P<7> VDD VSS / RSC_IHPSG13_INVX2 +XA_DEC3INV<6> net23<9> A_SEL_P<6> VDD VSS / RSC_IHPSG13_INVX2 +XA_DEC3INV<5> net23<10> A_SEL_P<5> VDD VSS / RSC_IHPSG13_INVX2 +XA_DEC3INV<4> net23<11> A_SEL_P<4> VDD VSS / RSC_IHPSG13_INVX2 +XA_DEC3INV<3> net23<12> A_SEL_P<3> VDD VSS / RSC_IHPSG13_INVX2 +XA_DEC3INV<2> net23<13> A_SEL_P<2> VDD VSS / RSC_IHPSG13_INVX2 +XA_DEC3INV<1> net23<14> A_SEL_P<1> VDD VSS / RSC_IHPSG13_INVX2 +XA_DEC3INV<0> net23<15> A_SEL_P<0> VDD VSS / RSC_IHPSG13_INVX2 +XA_I83 A_BM_R A_BM_N VDD VSS / RSC_IHPSG13_INVX2 +XA_I49 A_DI_R A_DI_N VDD VSS / RSC_IHPSG13_INVX2 +XB_DEC3INV<15> net044<0> B_SEL_P<15> VDD VSS / RSC_IHPSG13_INVX2 +XB_DEC3INV<14> net044<1> B_SEL_P<14> VDD VSS / RSC_IHPSG13_INVX2 +XB_DEC3INV<13> net044<2> B_SEL_P<13> VDD VSS / RSC_IHPSG13_INVX2 +XB_DEC3INV<12> net044<3> B_SEL_P<12> VDD VSS / RSC_IHPSG13_INVX2 +XB_DEC3INV<11> net044<4> B_SEL_P<11> VDD VSS / RSC_IHPSG13_INVX2 +XB_DEC3INV<10> net044<5> B_SEL_P<10> VDD VSS / RSC_IHPSG13_INVX2 +XB_DEC3INV<9> net044<6> B_SEL_P<9> VDD VSS / RSC_IHPSG13_INVX2 +XB_DEC3INV<8> net044<7> B_SEL_P<8> VDD VSS / RSC_IHPSG13_INVX2 +XB_DEC3INV<7> net044<8> B_SEL_P<7> VDD VSS / RSC_IHPSG13_INVX2 +XB_DEC3INV<6> net044<9> B_SEL_P<6> VDD VSS / RSC_IHPSG13_INVX2 +XB_DEC3INV<5> net044<10> B_SEL_P<5> VDD VSS / RSC_IHPSG13_INVX2 +XB_DEC3INV<4> net044<11> B_SEL_P<4> VDD VSS / RSC_IHPSG13_INVX2 +XB_DEC3INV<3> net044<12> B_SEL_P<3> VDD VSS / RSC_IHPSG13_INVX2 +XB_DEC3INV<2> net044<13> B_SEL_P<2> VDD VSS / RSC_IHPSG13_INVX2 +XB_DEC3INV<1> net044<14> B_SEL_P<1> VDD VSS / RSC_IHPSG13_INVX2 +XB_DEC3INV<0> net044<15> B_SEL_P<0> VDD VSS / RSC_IHPSG13_INVX2 +XB_I83 B_BM_R B_BM_N VDD VSS / RSC_IHPSG13_INVX2 +XB_I49 B_DI_R B_DI_N VDD VSS / RSC_IHPSG13_INVX2 +XI_FILL8<20> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI_FILL8<19> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI_FILL8<18> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI_FILL8<17> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI_FILL8<16> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI_FILL8<15> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI_FILL8<14> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI_FILL8<13> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI_FILL8<12> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI_FILL8<11> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI_FILL8<10> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI_FILL8<9> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI_FILL8<8> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI_FILL8<7> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI_FILL8<6> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI_FILL8<5> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI_FILL8<4> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI_FILL8<3> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI_FILL8<2> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI_FILL8<1> VDD VSS / RSC_IHPSG13_FILLCAP8 +XA_I44 A_BM_N A_WCLK_B_L A_DO_WRITE_P VDD VSS / RSC_IHPSG13_NOR2X2 +XB_I44 B_BM_N B_WCLK_B_L B_DO_WRITE_P VDD VSS / RSC_IHPSG13_NOR2X2 +XA_DEC3<15> A_P0 A_ADDR_DEC<7> net23<0> VDD VSS / RSC_IHPSG13_NAND2X2 +XA_DEC3<14> A_P0 A_ADDR_DEC<6> net23<1> VDD VSS / RSC_IHPSG13_NAND2X2 +XA_DEC3<13> A_P0 A_ADDR_DEC<5> net23<2> VDD VSS / RSC_IHPSG13_NAND2X2 +XA_DEC3<12> A_P0 A_ADDR_DEC<4> net23<3> VDD VSS / RSC_IHPSG13_NAND2X2 +XA_DEC3<11> A_P0 A_ADDR_DEC<3> net23<4> VDD VSS / RSC_IHPSG13_NAND2X2 +XA_DEC3<10> A_P0 A_ADDR_DEC<2> net23<5> VDD VSS / RSC_IHPSG13_NAND2X2 +XA_DEC3<9> A_P0 A_ADDR_DEC<1> net23<6> VDD VSS / RSC_IHPSG13_NAND2X2 +XA_DEC3<8> A_P0 A_ADDR_DEC<0> net23<7> VDD VSS / RSC_IHPSG13_NAND2X2 +XA_DEC3<7> A_N0 A_ADDR_DEC<7> net23<8> VDD VSS / RSC_IHPSG13_NAND2X2 +XA_DEC3<6> A_N0 A_ADDR_DEC<6> net23<9> VDD VSS / RSC_IHPSG13_NAND2X2 +XA_DEC3<5> A_N0 A_ADDR_DEC<5> net23<10> VDD VSS / RSC_IHPSG13_NAND2X2 +XA_DEC3<4> A_N0 A_ADDR_DEC<4> net23<11> VDD VSS / RSC_IHPSG13_NAND2X2 +XA_DEC3<3> A_N0 A_ADDR_DEC<3> net23<12> VDD VSS / RSC_IHPSG13_NAND2X2 +XA_DEC3<2> A_N0 A_ADDR_DEC<2> net23<13> VDD VSS / RSC_IHPSG13_NAND2X2 +XA_DEC3<1> A_N0 A_ADDR_DEC<1> net23<14> VDD VSS / RSC_IHPSG13_NAND2X2 +XA_DEC3<0> A_N0 A_ADDR_DEC<0> net23<15> VDD VSS / RSC_IHPSG13_NAND2X2 +XB_DEC3<15> B_P0 B_ADDR_DEC<7> net044<0> VDD VSS / RSC_IHPSG13_NAND2X2 +XB_DEC3<14> B_P0 B_ADDR_DEC<6> net044<1> VDD VSS / RSC_IHPSG13_NAND2X2 +XB_DEC3<13> B_P0 B_ADDR_DEC<5> net044<2> VDD VSS / RSC_IHPSG13_NAND2X2 +XB_DEC3<12> B_P0 B_ADDR_DEC<4> net044<3> VDD VSS / RSC_IHPSG13_NAND2X2 +XB_DEC3<11> B_P0 B_ADDR_DEC<3> net044<4> VDD VSS / RSC_IHPSG13_NAND2X2 +XB_DEC3<10> B_P0 B_ADDR_DEC<2> net044<5> VDD VSS / RSC_IHPSG13_NAND2X2 +XB_DEC3<9> B_P0 B_ADDR_DEC<1> net044<6> VDD VSS / RSC_IHPSG13_NAND2X2 +XB_DEC3<8> B_P0 B_ADDR_DEC<0> net044<7> VDD VSS / RSC_IHPSG13_NAND2X2 +XB_DEC3<7> B_N0 B_ADDR_DEC<7> net044<8> VDD VSS / RSC_IHPSG13_NAND2X2 +XB_DEC3<6> B_N0 B_ADDR_DEC<6> net044<9> VDD VSS / RSC_IHPSG13_NAND2X2 +XB_DEC3<5> B_N0 B_ADDR_DEC<5> net044<10> VDD VSS / RSC_IHPSG13_NAND2X2 +XB_DEC3<4> B_N0 B_ADDR_DEC<4> net044<11> VDD VSS / RSC_IHPSG13_NAND2X2 +XB_DEC3<3> B_N0 B_ADDR_DEC<3> net044<12> VDD VSS / RSC_IHPSG13_NAND2X2 +XB_DEC3<2> B_N0 B_ADDR_DEC<2> net044<13> VDD VSS / RSC_IHPSG13_NAND2X2 +XB_DEC3<1> B_N0 B_ADDR_DEC<1> net044<14> VDD VSS / RSC_IHPSG13_NAND2X2 +XB_DEC3<0> B_N0 B_ADDR_DEC<0> net044<15> VDD VSS / RSC_IHPSG13_NAND2X2 +XB_BM_TIEH B_TIEH_O VDD VSS / RSC_IHPSG13_TIEH +XA_BM_TIEH A_TIEH_O VDD VSS / RSC_IHPSG13_TIEH +.ENDS + + +.SUBCKT RM_IHPSG13_256x32_c2_2P_ROWDEC5 ADDR_N_I<4> ADDR_N_I<3> ADDR_N_I<2> ADDR_N_I<1> ++ ADDR_N_I<0> CS_I ECLK_I WL_O<31> WL_O<30> WL_O<29> WL_O<28> WL_O<27> ++ WL_O<26> WL_O<25> WL_O<24> WL_O<23> WL_O<22> WL_O<21> WL_O<20> WL_O<19> ++ WL_O<18> WL_O<17> WL_O<16> WL_O<15> WL_O<14> WL_O<13> WL_O<12> WL_O<11> ++ WL_O<10> WL_O<9> WL_O<8> WL_O<7> WL_O<6> WL_O<5> WL_O<4> WL_O<3> WL_O<2> ++ WL_O<1> WL_O<0> VDD VSS +XDEC00 ADDR_N_I<5> ADDR_N_I<4> CS_I CS00<0> VDD VSS / ++ RM_IHPSG13_256x32_c2_2P_DEC00 +XSEL<1> ADDR_N_I<3> ADDR_N_I<2> ADDR_N_I<1> ADDR_N_I<0> CS00<1> ECLK_H<1> ++ ECLK_H<2> ECLK_B<1> ECLK_B<2> WL_O<31> WL_O<30> WL_O<29> WL_O<28> WL_O<27> ++ WL_O<26> WL_O<25> WL_O<24> WL_O<23> WL_O<22> WL_O<21> WL_O<20> WL_O<19> ++ WL_O<18> WL_O<17> WL_O<16> VDD VSS / RM_IHPSG13_256x32_c2_2P_DEC04 +XSEL<0> ADDR_N_I<3> ADDR_N_I<2> ADDR_N_I<1> ADDR_N_I<0> CS00<0> ECLK_I ++ ECLK_H<1> ECLK_B<0> ECLK_B<1> WL_O<15> WL_O<14> WL_O<13> WL_O<12> WL_O<11> ++ WL_O<10> WL_O<9> WL_O<8> WL_O<7> WL_O<6> WL_O<5> WL_O<4> WL_O<3> WL_O<2> ++ WL_O<1> WL_O<0> VDD VSS / RM_IHPSG13_256x32_c2_2P_DEC04 +XDEC01 ADDR_N_I<5> ADDR_N_I<4> CS_I CS00<1> VDD VSS / ++ RM_IHPSG13_256x32_c2_2P_DEC01 +XL2<18> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<17> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<16> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<15> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<14> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<13> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<12> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<11> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<10> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<9> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<8> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<7> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<6> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<5> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<4> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<3> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<2> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<1> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI0 ADDR_N_I<5> VDD VSS / RSC_IHPSG13_TIEL +.ENDS +.SUBCKT RM_IHPSG13_256x32_c2_2P_ROWREG5 ACLK_N_I ADDR_I<4> ADDR_I<3> ADDR_I<2> ADDR_I<1> ++ ADDR_I<0> ADDR_N_O<4> ADDR_N_O<3> ADDR_N_O<2> ADDR_N_O<1> ADDR_N_O<0> ++ BIST_ADDR_I<4> BIST_ADDR_I<3> BIST_ADDR_I<2> BIST_ADDR_I<1> BIST_ADDR_I<0> ++ BIST_EN_I VDD VSS +XINV<4> q_int<4> qn_int<4> VDD VSS / RSC_IHPSG13_CINVX2 +XINV<3> q_int<3> qn_int<3> VDD VSS / RSC_IHPSG13_CINVX2 +XINV<2> q_int<2> qn_int<2> VDD VSS / RSC_IHPSG13_CINVX2 +XINV<1> q_int<1> qn_int<1> VDD VSS / RSC_IHPSG13_CINVX2 +XINV<0> q_int<0> qn_int<0> VDD VSS / RSC_IHPSG13_CINVX2 +XDRV<4> qn_int<4> ADDR_N_O<4> VDD VSS / RSC_IHPSG13_CINVX8 +XDRV<3> qn_int<3> ADDR_N_O<3> VDD VSS / RSC_IHPSG13_CINVX8 +XDRV<2> qn_int<2> ADDR_N_O<2> VDD VSS / RSC_IHPSG13_CINVX8 +XDRV<1> qn_int<1> ADDR_N_O<1> VDD VSS / RSC_IHPSG13_CINVX8 +XDRV<0> qn_int<0> ADDR_N_O<0> VDD VSS / RSC_IHPSG13_CINVX8 +XDFF<4> BIST_EN_I BIST_ADDR_I<4> ACLK_N_I ADDR_I<4> q_int<4> net2<0> VDD ++ VSS / RSC_IHPSG13_DFNQMX2IX1 +XDFF<3> BIST_EN_I BIST_ADDR_I<3> ACLK_N_I ADDR_I<3> q_int<3> net2<1> VDD ++ VSS / RSC_IHPSG13_DFNQMX2IX1 +XDFF<2> BIST_EN_I BIST_ADDR_I<2> ACLK_N_I ADDR_I<2> q_int<2> net2<2> VDD ++ VSS / RSC_IHPSG13_DFNQMX2IX1 +XDFF<1> BIST_EN_I BIST_ADDR_I<1> ACLK_N_I ADDR_I<1> q_int<1> net2<3> VDD ++ VSS / RSC_IHPSG13_DFNQMX2IX1 +XDFF<0> BIST_EN_I BIST_ADDR_I<0> ACLK_N_I ADDR_I<0> q_int<0> net2<4> VDD ++ VSS / RSC_IHPSG13_DFNQMX2IX1 +XI11<16> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI11<15> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI11<14> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI11<13> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI11<12> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI11<11> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI11<10> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI11<9> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI11<8> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI11<7> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI11<6> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI11<5> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI11<4> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI11<3> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI11<2> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI11<1> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI12<3> VDD VSS / RSC_IHPSG13_FILLCAP4 +XI12<2> VDD VSS / RSC_IHPSG13_FILLCAP4 +XI12<1> VDD VSS / RSC_IHPSG13_FILLCAP4 +XI12<0> VDD VSS / RSC_IHPSG13_FILLCAP4 +.ENDS + + +.SUBCKT RM_IHPSG13_256x32_c2_2P_COLDEC3 ACLK_N ADDR<2> ADDR<1> ADDR<0> ADDR_COL<1> ++ ADDR_COL<0> ADDR_DEC<7> ADDR_DEC<6> ADDR_DEC<5> ADDR_DEC<4> ADDR_DEC<3> ++ ADDR_DEC<2> ADDR_DEC<1> ADDR_DEC<0> BIST_ADDR<2> BIST_ADDR<1> BIST_ADDR<0> ++ BIST_EN_I VDD VSS +XI1<7> PADR<0> PADR<1> PADR<2> addr_n<7> VDD VSS / RSC_IHPSG13_NAND3X2 +XI1<6> NADR<0> PADR<1> PADR<2> addr_n<6> VDD VSS / RSC_IHPSG13_NAND3X2 +XI1<5> PADR<0> NADR<1> PADR<2> addr_n<5> VDD VSS / RSC_IHPSG13_NAND3X2 +XI1<4> NADR<0> NADR<1> PADR<2> addr_n<4> VDD VSS / RSC_IHPSG13_NAND3X2 +XI1<3> PADR<0> PADR<1> NADR<2> addr_n<3> VDD VSS / RSC_IHPSG13_NAND3X2 +XI1<2> NADR<0> PADR<1> NADR<2> addr_n<2> VDD VSS / RSC_IHPSG13_NAND3X2 +XI1<1> PADR<0> NADR<1> NADR<2> addr_n<1> VDD VSS / RSC_IHPSG13_NAND3X2 +XI1<0> NADR<0> NADR<1> NADR<2> addr_n<0> VDD VSS / RSC_IHPSG13_NAND3X2 +XDFF<2> BIST_EN_I BIST_ADDR<2> ACLK_N ADDR<2> padr_int<2> net13<0> VDD ++ VSS / RSC_IHPSG13_DFNQMX2IX1 +XDFF<1> BIST_EN_I BIST_ADDR<1> ACLK_N ADDR<1> padr_int<1> net13<1> VDD ++ VSS / RSC_IHPSG13_DFNQMX2IX1 +XDFF<0> BIST_EN_I BIST_ADDR<0> ACLK_N ADDR<0> padr_int<0> net13<2> VDD ++ VSS / RSC_IHPSG13_DFNQMX2IX1 +XI15<1> ADDR_COL<1> VDD VSS / RSC_IHPSG13_TIEL +XI15<0> ADDR_COL<0> VDD VSS / RSC_IHPSG13_TIEL +XI13<2> NADR<2> PADR<2> VDD VSS / RSC_IHPSG13_INVX2 +XI13<1> NADR<1> PADR<1> VDD VSS / RSC_IHPSG13_INVX2 +XI13<0> NADR<0> PADR<0> VDD VSS / RSC_IHPSG13_INVX2 +XI3<2> padr_int<2> NADR<2> VDD VSS / RSC_IHPSG13_INVX2 +XI3<1> padr_int<1> NADR<1> VDD VSS / RSC_IHPSG13_INVX2 +XI3<0> padr_int<0> NADR<0> VDD VSS / RSC_IHPSG13_INVX2 +XI2<7> addr_n<7> ADDR_DEC<7> VDD VSS / RSC_IHPSG13_INVX2 +XI2<6> addr_n<6> ADDR_DEC<6> VDD VSS / RSC_IHPSG13_INVX2 +XI2<5> addr_n<5> ADDR_DEC<5> VDD VSS / RSC_IHPSG13_INVX2 +XI2<4> addr_n<4> ADDR_DEC<4> VDD VSS / RSC_IHPSG13_INVX2 +XI2<3> addr_n<3> ADDR_DEC<3> VDD VSS / RSC_IHPSG13_INVX2 +XI2<2> addr_n<2> ADDR_DEC<2> VDD VSS / RSC_IHPSG13_INVX2 +XI2<1> addr_n<1> ADDR_DEC<1> VDD VSS / RSC_IHPSG13_INVX2 +XI2<0> addr_n<0> ADDR_DEC<0> VDD VSS / RSC_IHPSG13_INVX2 +XI17<4> VDD VSS / RSC_IHPSG13_FILLCAP4 +XI17<3> VDD VSS / RSC_IHPSG13_FILLCAP4 +XI17<2> VDD VSS / RSC_IHPSG13_FILLCAP4 +XI17<1> VDD VSS / RSC_IHPSG13_FILLCAP4 +XI16<11> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI16<10> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI16<9> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI16<8> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI16<7> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI16<6> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI16<5> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI16<4> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI16<3> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI16<2> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI16<1> VDD VSS / RSC_IHPSG13_FILLCAP8 +.ENDS +.SUBCKT RSC_IHPSG13_DFPQD_MSAFFX2P CP DN DP QN QP VDD VSS +XI_AMP CP DN DP QN QP VDD VSS / RSC_IHPSG13_DFPQD_MSAFFX2 +.ENDS +.SUBCKT RM_IHPSG13_256x32_c2_2P_COLCTRL3 A_ADDR_DEC<7> A_ADDR_DEC<6> A_ADDR_DEC<5> ++ A_ADDR_DEC<4> A_ADDR_DEC<3> A_ADDR_DEC<2> A_ADDR_DEC<1> A_ADDR_DEC<0> ++ A_BIST_BM_I A_BIST_DW_I A_BIST_EN_I A_BLC<7> A_BLC<6> A_BLC<5> A_BLC<4> ++ A_BLC<3> A_BLC<2> A_BLC<1> A_BLC<0> A_BLT<7> A_BLT<6> A_BLT<5> A_BLT<4> ++ A_BLT<3> A_BLT<2> A_BLT<1> A_BLT<0> A_BM_I A_DCLK_B_L A_DCLK_B_R A_DCLK_L ++ A_DCLK_R A_DR_O A_DW_I A_RCLK_B_L A_RCLK_B_R A_RCLK_L A_RCLK_R A_TIEH_O ++ A_WCLK_B_L A_WCLK_B_R A_WCLK_L A_WCLK_R B_ADDR_DEC<7> B_ADDR_DEC<6> ++ B_ADDR_DEC<5> B_ADDR_DEC<4> B_ADDR_DEC<3> B_ADDR_DEC<2> B_ADDR_DEC<1> ++ B_ADDR_DEC<0> B_BIST_BM_I B_BIST_DW_I B_BIST_EN_I B_BLC<7> B_BLC<6> B_BLC<5> ++ B_BLC<4> B_BLC<3> B_BLC<2> B_BLC<1> B_BLC<0> B_BLT<7> B_BLT<6> B_BLT<5> ++ B_BLT<4> B_BLT<3> B_BLT<2> B_BLT<1> B_BLT<0> B_BM_I B_DCLK_B_L B_DCLK_B_R ++ B_DCLK_L B_DCLK_R B_DR_O B_DW_I B_RCLK_B_L B_RCLK_B_R B_RCLK_L B_RCLK_R ++ B_TIEH_O B_WCLK_B_L B_WCLK_B_R B_WCLK_L B_WCLK_R VDD VSS +XB_DREG B_BIST_EN_I B_BIST_DW_I B_DCLK_B_L B_DW_I B_DI_R net044 VDD ++ VSS / RSC_IHPSG13_DFNQMX2IX1 +XB_BREG B_BIST_EN_I B_BIST_BM_I B_DCLK_B_L B_BM_I B_BM_R net043 VDD ++ VSS / RSC_IHPSG13_DFNQMX2IX1 +XA_DREG A_BIST_EN_I A_BIST_DW_I A_DCLK_B_L A_DW_I A_DI_R net22 VDD VSS ++ / RSC_IHPSG13_DFNQMX2IX1 +XA_BREG A_BIST_EN_I A_BIST_BM_I A_DCLK_B_L A_BM_I A_BM_R net23 VDD VSS ++ / RSC_IHPSG13_DFNQMX2IX1 +XI_FILL8<11> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI_FILL8<10> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI_FILL8<9> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI_FILL8<8> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI_FILL8<7> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI_FILL8<6> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI_FILL8<5> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI_FILL8<4> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI_FILL8<3> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI_FILL8<2> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI_FILL8<1> VDD VSS / RSC_IHPSG13_FILLCAP8 +XB_I51 net037 B_DR_O VDD VSS / RSC_IHPSG13_INVX4 +XA_I51 net19 A_DR_O VDD VSS / RSC_IHPSG13_INVX4 +XB_I44 B_BM_N B_WCLK_B_L B_DO_WRITE_P VDD VSS / RSC_IHPSG13_NOR2X2 +XA_I44 A_BM_N A_WCLK_B_L A_DO_WRITE_P VDD VSS / RSC_IHPSG13_NOR2X2 +XB_BM_TIEH B_TIEH_O VDD VSS / RSC_IHPSG13_TIEH +XA_BM_TIEH A_TIEH_O VDD VSS / RSC_IHPSG13_TIEH +XB_ISENSE B_SAE B_BLC_SEL B_BLT_SEL net037 net038 VDD VSS / ++ RSC_IHPSG13_DFPQD_MSAFFX2P +XA_ISENSE A_SAE A_BLC_SEL A_BLT_SEL net19 net20 VDD VSS / ++ RSC_IHPSG13_DFPQD_MSAFFX2P +XB_I49 B_DI_R B_DI_N VDD VSS / RSC_IHPSG13_INVX2 +XB_I83 B_BM_R B_BM_N VDD VSS / RSC_IHPSG13_INVX2 +XA_I49 A_DI_R A_DI_N VDD VSS / RSC_IHPSG13_INVX2 +XA_I83 A_BM_R A_BM_N VDD VSS / RSC_IHPSG13_INVX2 +XB_I69 B_DCLK_L B_DCLK_B_L VDD VSS / RSC_IHPSG13_CINVX2 +XB_I50 B_WCLK_L B_WCLK_B_L VDD VSS / RSC_IHPSG13_CINVX2 +XB_EBUF B_RCLK_L B_RCLK_B_L VDD VSS / RSC_IHPSG13_CINVX2 +XA_I69 A_DCLK_L A_DCLK_B_L VDD VSS / RSC_IHPSG13_CINVX2 +XA_I50 A_WCLK_L A_WCLK_B_L VDD VSS / RSC_IHPSG13_CINVX2 +XA_EBUF A_RCLK_L A_RCLK_B_L VDD VSS / RSC_IHPSG13_CINVX2 +XAB_BLMUX<1> A_BLC<7> A_BLC<6> A_BLC<5> A_BLC<4> A_BLC_SEL A_BLT<7> A_BLT<6> ++ A_BLT<5> A_BLT<4> A_BLT_SEL A_PRE_N A_ADDR_DEC<7> A_ADDR_DEC<6> ++ A_ADDR_DEC<5> A_ADDR_DEC<4> A_WR_ONE A_WR_ZERO B_BLC<7> B_BLC<6> B_BLC<5> ++ B_BLC<4> B_BLC_SEL B_BLT<7> B_BLT<6> B_BLT<5> B_BLT<4> B_BLT_SEL B_PRE_N ++ B_ADDR_DEC<7> B_ADDR_DEC<6> B_ADDR_DEC<5> B_ADDR_DEC<4> B_WR_ONE B_WR_ZERO ++ VDD VSS / RM_IHPSG13_256x32_c2_2P_BLDRV +XAB_BLMUX<0> A_BLC<3> A_BLC<2> A_BLC<1> A_BLC<0> A_BLC_SEL A_BLT<3> A_BLT<2> ++ A_BLT<1> A_BLT<0> A_BLT_SEL A_PRE_N A_ADDR_DEC<3> A_ADDR_DEC<2> ++ A_ADDR_DEC<1> A_ADDR_DEC<0> A_WR_ONE A_WR_ZERO B_BLC<3> B_BLC<2> B_BLC<1> ++ B_BLC<0> B_BLC_SEL B_BLT<3> B_BLT<2> B_BLT<1> B_BLT<0> B_BLT_SEL B_PRE_N ++ B_ADDR_DEC<3> B_ADDR_DEC<2> B_ADDR_DEC<1> B_ADDR_DEC<0> B_WR_ONE B_WR_ZERO ++ VDD VSS / RM_IHPSG13_256x32_c2_2P_BLDRV +XB_I78 B_RCLK_B_L B_SAE VDD VSS / RSC_IHPSG13_CBUFX2 +XA_I78 A_RCLK_B_L A_SAE VDD VSS / RSC_IHPSG13_CBUFX2 +XB_I88 B_DCLK_L B_DCLK_R / RSC_IHPSG13_MET3RES +XB_I87 B_WCLK_L B_WCLK_R / RSC_IHPSG13_MET3RES +XB_R2 B_RCLK_L B_RCLK_R / RSC_IHPSG13_MET3RES +XB_I91 B_RCLK_B_L B_RCLK_B_R / RSC_IHPSG13_MET3RES +XB_I90 B_WCLK_B_L B_WCLK_B_R / RSC_IHPSG13_MET3RES +XB_I89 B_DCLK_B_L B_DCLK_B_R / RSC_IHPSG13_MET3RES +XA_I88 A_DCLK_L A_DCLK_R / RSC_IHPSG13_MET3RES +XA_I87 A_WCLK_L A_WCLK_R / RSC_IHPSG13_MET3RES +XA_R2 A_RCLK_L A_RCLK_R / RSC_IHPSG13_MET3RES +XA_I91 A_RCLK_B_L A_RCLK_B_R / RSC_IHPSG13_MET3RES +XA_I90 A_WCLK_B_L A_WCLK_B_R / RSC_IHPSG13_MET3RES +XA_I89 A_DCLK_B_L A_DCLK_B_R / RSC_IHPSG13_MET3RES +XB_I80 B_WCLK_B_L B_RCLK_B_L net041 VDD VSS / RSC_IHPSG13_AND2X2 +XB_I76 B_DO_WRITE_P B_DI_N B_WR_ZERO VDD VSS / RSC_IHPSG13_AND2X2 +XB_I75 B_DO_WRITE_P B_DI_R B_WR_ONE VDD VSS / RSC_IHPSG13_AND2X2 +XA_I80 A_WCLK_B_L A_RCLK_B_L net21 VDD VSS / RSC_IHPSG13_AND2X2 +XA_I76 A_DI_N A_DO_WRITE_P A_WR_ZERO VDD VSS / RSC_IHPSG13_AND2X2 +XA_I75 A_DI_R A_DO_WRITE_P A_WR_ONE VDD VSS / RSC_IHPSG13_AND2X2 +XB_I81 net041 B_PRE_N VDD VSS / RSC_IHPSG13_CINVX4_WN +XA_I81 net21 A_PRE_N VDD VSS / RSC_IHPSG13_CINVX4_WN +XI_FILL4<10> VDD VSS / RSC_IHPSG13_FILLCAP4 +XI_FILL4<9> VDD VSS / RSC_IHPSG13_FILLCAP4 +XI_FILL4<8> VDD VSS / RSC_IHPSG13_FILLCAP4 +XI_FILL4<7> VDD VSS / RSC_IHPSG13_FILLCAP4 +XI_FILL4<6> VDD VSS / RSC_IHPSG13_FILLCAP4 +XI_FILL4<5> VDD VSS / RSC_IHPSG13_FILLCAP4 +XI_FILL4<4> VDD VSS / RSC_IHPSG13_FILLCAP4 +XI_FILL4<3> VDD VSS / RSC_IHPSG13_FILLCAP4 +XI_FILL4<2> VDD VSS / RSC_IHPSG13_FILLCAP4 +XI_FILL4<1> VDD VSS / RSC_IHPSG13_FILLCAP4 +.ENDS + +.SUBCKT RM_IHPSG13_256x32_c2_2P_ROWDEC6 ADDR_N_I<5> ADDR_N_I<4> ADDR_N_I<3> ADDR_N_I<2> ++ ADDR_N_I<1> ADDR_N_I<0> CS_I ECLK_I WL_O<63> WL_O<62> WL_O<61> WL_O<60> ++ WL_O<59> WL_O<58> WL_O<57> WL_O<56> WL_O<55> WL_O<54> WL_O<53> WL_O<52> ++ WL_O<51> WL_O<50> WL_O<49> WL_O<48> WL_O<47> WL_O<46> WL_O<45> WL_O<44> ++ WL_O<43> WL_O<42> WL_O<41> WL_O<40> WL_O<39> WL_O<38> WL_O<37> WL_O<36> ++ WL_O<35> WL_O<34> WL_O<33> WL_O<32> WL_O<31> WL_O<30> WL_O<29> WL_O<28> ++ WL_O<27> WL_O<26> WL_O<25> WL_O<24> WL_O<23> WL_O<22> WL_O<21> WL_O<20> ++ WL_O<19> WL_O<18> WL_O<17> WL_O<16> WL_O<15> WL_O<14> WL_O<13> WL_O<12> ++ WL_O<11> WL_O<10> WL_O<9> WL_O<8> WL_O<7> WL_O<6> WL_O<5> WL_O<4> WL_O<3> ++ WL_O<2> WL_O<1> WL_O<0> VDD VSS +XDEC10 ADDR_N_I<5> ADDR_N_I<4> CS_I CS00<2> VDD VSS / ++ RM_IHPSG13_256x32_c2_2P_DEC02 +XDEC00 ADDR_N_I<5> ADDR_N_I<4> CS_I CS00<0> VDD VSS / ++ RM_IHPSG13_256x32_c2_2P_DEC00 +XSEL<3> ADDR_N_I<3> ADDR_N_I<2> ADDR_N_I<1> ADDR_N_I<0> CS00<3> ECLK_H<3> ++ ECLK_H<4> ECLK_B<3> ECLK_B<4> WL_O<63> WL_O<62> WL_O<61> WL_O<60> WL_O<59> ++ WL_O<58> WL_O<57> WL_O<56> WL_O<55> WL_O<54> WL_O<53> WL_O<52> WL_O<51> ++ WL_O<50> WL_O<49> WL_O<48> VDD VSS / RM_IHPSG13_256x32_c2_2P_DEC04 +XSEL<2> ADDR_N_I<3> ADDR_N_I<2> ADDR_N_I<1> ADDR_N_I<0> CS00<2> ECLK_H<2> ++ ECLK_H<3> ECLK_B<2> ECLK_B<3> WL_O<47> WL_O<46> WL_O<45> WL_O<44> WL_O<43> ++ WL_O<42> WL_O<41> WL_O<40> WL_O<39> WL_O<38> WL_O<37> WL_O<36> WL_O<35> ++ WL_O<34> WL_O<33> WL_O<32> VDD VSS / RM_IHPSG13_256x32_c2_2P_DEC04 +XSEL<1> ADDR_N_I<3> ADDR_N_I<2> ADDR_N_I<1> ADDR_N_I<0> CS00<1> ECLK_H<1> ++ ECLK_H<2> ECLK_B<1> ECLK_B<2> WL_O<31> WL_O<30> WL_O<29> WL_O<28> WL_O<27> ++ WL_O<26> WL_O<25> WL_O<24> WL_O<23> WL_O<22> WL_O<21> WL_O<20> WL_O<19> ++ WL_O<18> WL_O<17> WL_O<16> VDD VSS / RM_IHPSG13_256x32_c2_2P_DEC04 +XSEL<0> ADDR_N_I<3> ADDR_N_I<2> ADDR_N_I<1> ADDR_N_I<0> CS00<0> ECLK_I ++ ECLK_H<1> ECLK_B<0> ECLK_B<1> WL_O<15> WL_O<14> WL_O<13> WL_O<12> WL_O<11> ++ WL_O<10> WL_O<9> WL_O<8> WL_O<7> WL_O<6> WL_O<5> WL_O<4> WL_O<3> WL_O<2> ++ WL_O<1> WL_O<0> VDD VSS / RM_IHPSG13_256x32_c2_2P_DEC04 +XDEC11 ADDR_N_I<5> ADDR_N_I<4> CS_I CS00<3> VDD VSS / ++ RM_IHPSG13_256x32_c2_2P_DEC03 +XL2<36> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<35> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<34> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<33> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<32> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<31> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<30> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<29> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<28> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<27> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<26> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<25> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<24> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<23> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<22> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<21> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<20> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<19> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<18> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<17> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<16> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<15> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<14> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<13> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<12> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<11> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<10> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<9> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<8> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<7> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<6> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<5> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<4> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<3> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<2> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<1> VDD VSS / RSC_IHPSG13_FILLCAP8 +XDEC01 ADDR_N_I<5> ADDR_N_I<4> CS_I CS00<1> VDD VSS / ++ RM_IHPSG13_256x32_c2_2P_DEC01 +.ENDS +.SUBCKT RM_IHPSG13_256x32_c2_2P_ROWREG6 ACLK_N_I ADDR_I<5> ADDR_I<4> ADDR_I<3> ADDR_I<2> ++ ADDR_I<1> ADDR_I<0> ADDR_N_O<5> ADDR_N_O<4> ADDR_N_O<3> ADDR_N_O<2> ++ ADDR_N_O<1> ADDR_N_O<0> BIST_ADDR_I<5> BIST_ADDR_I<4> BIST_ADDR_I<3> ++ BIST_ADDR_I<2> BIST_ADDR_I<1> BIST_ADDR_I<0> BIST_EN_I VDD VSS +XINV<5> q_int<5> qn_int<5> VDD VSS / RSC_IHPSG13_CINVX2 +XINV<4> q_int<4> qn_int<4> VDD VSS / RSC_IHPSG13_CINVX2 +XINV<3> q_int<3> qn_int<3> VDD VSS / RSC_IHPSG13_CINVX2 +XINV<2> q_int<2> qn_int<2> VDD VSS / RSC_IHPSG13_CINVX2 +XINV<1> q_int<1> qn_int<1> VDD VSS / RSC_IHPSG13_CINVX2 +XINV<0> q_int<0> qn_int<0> VDD VSS / RSC_IHPSG13_CINVX2 +XDRV<5> qn_int<5> ADDR_N_O<5> VDD VSS / RSC_IHPSG13_CINVX8 +XDRV<4> qn_int<4> ADDR_N_O<4> VDD VSS / RSC_IHPSG13_CINVX8 +XDRV<3> qn_int<3> ADDR_N_O<3> VDD VSS / RSC_IHPSG13_CINVX8 +XDRV<2> qn_int<2> ADDR_N_O<2> VDD VSS / RSC_IHPSG13_CINVX8 +XDRV<1> qn_int<1> ADDR_N_O<1> VDD VSS / RSC_IHPSG13_CINVX8 +XDRV<0> qn_int<0> ADDR_N_O<0> VDD VSS / RSC_IHPSG13_CINVX8 +XDFF<5> BIST_EN_I BIST_ADDR_I<5> ACLK_N_I ADDR_I<5> q_int<5> net2<0> VDD ++ VSS / RSC_IHPSG13_DFNQMX2IX1 +XDFF<4> BIST_EN_I BIST_ADDR_I<4> ACLK_N_I ADDR_I<4> q_int<4> net2<1> VDD ++ VSS / RSC_IHPSG13_DFNQMX2IX1 +XDFF<3> BIST_EN_I BIST_ADDR_I<3> ACLK_N_I ADDR_I<3> q_int<3> net2<2> VDD ++ VSS / RSC_IHPSG13_DFNQMX2IX1 +XDFF<2> BIST_EN_I BIST_ADDR_I<2> ACLK_N_I ADDR_I<2> q_int<2> net2<3> VDD ++ VSS / RSC_IHPSG13_DFNQMX2IX1 +XDFF<1> BIST_EN_I BIST_ADDR_I<1> ACLK_N_I ADDR_I<1> q_int<1> net2<4> VDD ++ VSS / RSC_IHPSG13_DFNQMX2IX1 +XDFF<0> BIST_EN_I BIST_ADDR_I<0> ACLK_N_I ADDR_I<0> q_int<0> net2<5> VDD ++ VSS / RSC_IHPSG13_DFNQMX2IX1 +XI11<12> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI11<11> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI11<10> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI11<9> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI11<8> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI11<7> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI11<6> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI11<5> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI11<4> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI11<3> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI11<2> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI11<1> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI12<2> VDD VSS / RSC_IHPSG13_FILLCAP4 +XI12<1> VDD VSS / RSC_IHPSG13_FILLCAP4 +XI12<0> VDD VSS / RSC_IHPSG13_FILLCAP4 +.ENDS + +.SUBCKT RM_IHPSG13_256x32_c2_2P_COLDRV13X16 ADDR_COL_I<1> ADDR_COL_I<0> ADDR_COL_O<1> ++ ADDR_COL_O<0> ADDR_DEC_I<7> ADDR_DEC_I<6> ADDR_DEC_I<5> ADDR_DEC_I<4> ++ ADDR_DEC_I<3> ADDR_DEC_I<2> ADDR_DEC_I<1> ADDR_DEC_I<0> ADDR_DEC_O<7> ++ ADDR_DEC_O<6> ADDR_DEC_O<5> ADDR_DEC_O<4> ADDR_DEC_O<3> ADDR_DEC_O<2> ++ ADDR_DEC_O<1> ADDR_DEC_O<0> DCLK_I DCLK_O RCLK_I RCLK_O WCLK_I WCLK_O ++ VDD VSS +XI0<7> VDD VSS / RSC_IHPSG13_FILLCAP4 +XI0<6> VDD VSS / RSC_IHPSG13_FILLCAP4 +XI0<5> VDD VSS / RSC_IHPSG13_FILLCAP4 +XI0<4> VDD VSS / RSC_IHPSG13_FILLCAP4 +XI0<3> VDD VSS / RSC_IHPSG13_FILLCAP4 +XI0<2> VDD VSS / RSC_IHPSG13_FILLCAP4 +XI0<1> VDD VSS / RSC_IHPSG13_FILLCAP4 +XWCLK_DRV WCLK_I WCLK_O VDD VSS / RSC_IHPSG13_CBUFX16 +XRCLK_DRV RCLK_I RCLK_O VDD VSS / RSC_IHPSG13_CBUFX16 +XDCLK_DRV DCLK_I DCLK_O VDD VSS / RSC_IHPSG13_CBUFX16 +XADDR_COL_DRV<1> ADDR_COL_I<1> ADDR_COL_O<1> VDD VSS / ++ RSC_IHPSG13_CBUFX16 +XADDR_COL_DRV<0> ADDR_COL_I<0> ADDR_COL_O<0> VDD VSS / ++ RSC_IHPSG13_CBUFX16 +XADDR_DEC_DRV<7> ADDR_DEC_I<7> ADDR_DEC_O<7> VDD VSS / ++ RSC_IHPSG13_CBUFX16 +XADDR_DEC_DRV<6> ADDR_DEC_I<6> ADDR_DEC_O<6> VDD VSS / ++ RSC_IHPSG13_CBUFX16 +XADDR_DEC_DRV<5> ADDR_DEC_I<5> ADDR_DEC_O<5> VDD VSS / ++ RSC_IHPSG13_CBUFX16 +XADDR_DEC_DRV<4> ADDR_DEC_I<4> ADDR_DEC_O<4> VDD VSS / ++ RSC_IHPSG13_CBUFX16 +XADDR_DEC_DRV<3> ADDR_DEC_I<3> ADDR_DEC_O<3> VDD VSS / ++ RSC_IHPSG13_CBUFX16 +XADDR_DEC_DRV<2> ADDR_DEC_I<2> ADDR_DEC_O<2> VDD VSS / ++ RSC_IHPSG13_CBUFX16 +XADDR_DEC_DRV<1> ADDR_DEC_I<1> ADDR_DEC_O<1> VDD VSS / ++ RSC_IHPSG13_CBUFX16 +XADDR_DEC_DRV<0> ADDR_DEC_I<0> ADDR_DEC_O<0> VDD VSS / ++ RSC_IHPSG13_CBUFX16 +XI1<5> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI1<4> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI1<3> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI1<2> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI1<1> VDD VSS / RSC_IHPSG13_FILLCAP8 +.ENDS +.SUBCKT RM_IHPSG13_256x32_c2_2P_WLDRV16X16 A<15> A<14> A<13> A<12> A<11> A<10> A<9> A<8> ++ A<7> A<6> A<5> A<4> A<3> A<2> A<1> A<0> Z<15> Z<14> Z<13> Z<12> Z<11> Z<10> ++ Z<9> Z<8> Z<7> Z<6> Z<5> Z<4> Z<3> Z<2> Z<1> Z<0> VDD VSS +XBUF<15> A<15> Z<15> VDD VSS / RSC_IHPSG13_WLDRVX16 +XBUF<14> A<14> Z<14> VDD VSS / RSC_IHPSG13_WLDRVX16 +XBUF<13> A<13> Z<13> VDD VSS / RSC_IHPSG13_WLDRVX16 +XBUF<12> A<12> Z<12> VDD VSS / RSC_IHPSG13_WLDRVX16 +XBUF<11> A<11> Z<11> VDD VSS / RSC_IHPSG13_WLDRVX16 +XBUF<10> A<10> Z<10> VDD VSS / RSC_IHPSG13_WLDRVX16 +XBUF<9> A<9> Z<9> VDD VSS / RSC_IHPSG13_WLDRVX16 +XBUF<8> A<8> Z<8> VDD VSS / RSC_IHPSG13_WLDRVX16 +XBUF<7> A<7> Z<7> VDD VSS / RSC_IHPSG13_WLDRVX16 +XBUF<6> A<6> Z<6> VDD VSS / RSC_IHPSG13_WLDRVX16 +XBUF<5> A<5> Z<5> VDD VSS / RSC_IHPSG13_WLDRVX16 +XBUF<4> A<4> Z<4> VDD VSS / RSC_IHPSG13_WLDRVX16 +XBUF<3> A<3> Z<3> VDD VSS / RSC_IHPSG13_WLDRVX16 +XBUF<2> A<2> Z<2> VDD VSS / RSC_IHPSG13_WLDRVX16 +XBUF<1> A<1> Z<1> VDD VSS / RSC_IHPSG13_WLDRVX16 +XBUF<0> A<0> Z<0> VDD VSS / RSC_IHPSG13_WLDRVX16 +.ENDS + + +.SUBCKT RM_IHPSG13_256x32_c2_1P_DEC01 ADDR<1> ADDR<0> CS CS_OUT VDD VSS +XDECINV net1 CS_OUT VDD VSS / RSC_IHPSG13_INVX4 +XDEC NADDR<1> ADDR<0> CS net1 VDD VSS / RSC_IHPSG13_NAND3X2 +XI2 VDD VSS / RSC_IHPSG13_FILLCAP4 +XADDRINV ADDR<1> NADDR<1> VDD VSS / RSC_IHPSG13_INVX2 +.ENDS +.SUBCKT RM_IHPSG13_256x32_c2_1P_DEC00 ADDR<1> ADDR<0> CS CS_OUT VDD VSS +XDECINV net1 CS_OUT VDD VSS / RSC_IHPSG13_INVX4 +XDEC NADDR<1> NADDR<0> CS net1 VDD VSS / RSC_IHPSG13_NAND3X2 +XADDRINV<1> ADDR<1> NADDR<1> VDD VSS / RSC_IHPSG13_INVX2 +XADDRINV<0> ADDR<0> NADDR<0> VDD VSS / RSC_IHPSG13_INVX2 +XI1 VDD VSS / RSC_IHPSG13_FILLCAP4 +.ENDS +.SUBCKT RM_IHPSG13_256x32_c2_1P_ROWDEC5 ADDR_N_I<4> ADDR_N_I<3> ADDR_N_I<2> ADDR_N_I<1> ++ ADDR_N_I<0> CS_I ECLK_I WL_O<31> WL_O<30> WL_O<29> WL_O<28> WL_O<27> ++ WL_O<26> WL_O<25> WL_O<24> WL_O<23> WL_O<22> WL_O<21> WL_O<20> WL_O<19> ++ WL_O<18> WL_O<17> WL_O<16> WL_O<15> WL_O<14> WL_O<13> WL_O<12> WL_O<11> ++ WL_O<10> WL_O<9> WL_O<8> WL_O<7> WL_O<6> WL_O<5> WL_O<4> WL_O<3> WL_O<2> ++ WL_O<1> WL_O<0> VDD VSS +XL2<12> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<11> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<10> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<9> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<8> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<7> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<6> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<5> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<4> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<3> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<2> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<1> VDD VSS / RSC_IHPSG13_FILLCAP8 +XDEC01 ADDR_N_I<5> ADDR_N_I<4> CS_I CS00<1> VDD VSS / ++ RM_IHPSG13_256x32_c2_1P_DEC01 +XDEC00 ADDR_N_I<5> ADDR_N_I<4> CS_I CS00<0> VDD VSS / ++ RM_IHPSG13_256x32_c2_1P_DEC00 +XSEL<1> ADDR_N_I<3> ADDR_N_I<2> ADDR_N_I<1> ADDR_N_I<0> CS00<1> ECLK_H<1> ++ ECLK_H<2> ECLK_B<1> ECLK_B<2> WL_O<31> WL_O<30> WL_O<29> WL_O<28> WL_O<27> ++ WL_O<26> WL_O<25> WL_O<24> WL_O<23> WL_O<22> WL_O<21> WL_O<20> WL_O<19> ++ WL_O<18> WL_O<17> WL_O<16> VDD VSS / RM_IHPSG13_256x32_c2_1P_DEC04 +XSEL<0> ADDR_N_I<3> ADDR_N_I<2> ADDR_N_I<1> ADDR_N_I<0> CS00<0> ECLK_I ++ ECLK_H<1> ECLK_B<0> ECLK_B<1> WL_O<15> WL_O<14> WL_O<13> WL_O<12> WL_O<11> ++ WL_O<10> WL_O<9> WL_O<8> WL_O<7> WL_O<6> WL_O<5> WL_O<4> WL_O<3> WL_O<2> ++ WL_O<1> WL_O<0> VDD VSS / RM_IHPSG13_256x32_c2_1P_DEC04 +XI0 ADDR_N_I<5> VDD VSS / RSC_IHPSG13_TIEL +.ENDS +.SUBCKT RM_IHPSG13_256x32_c2_1P_ROWREG5 ACLK_N_I ADDR_I<4> ADDR_I<3> ADDR_I<2> ADDR_I<1> ++ ADDR_I<0> ADDR_N_O<4> ADDR_N_O<3> ADDR_N_O<2> ADDR_N_O<1> ADDR_N_O<0> ++ BIST_ADDR_I<4> BIST_ADDR_I<3> BIST_ADDR_I<2> BIST_ADDR_I<1> BIST_ADDR_I<0> ++ BIST_EN_I VDD VSS +XINV<4> q_int<4> qn_int<4> VDD VSS / RSC_IHPSG13_CINVX2 +XINV<3> q_int<3> qn_int<3> VDD VSS / RSC_IHPSG13_CINVX2 +XINV<2> q_int<2> qn_int<2> VDD VSS / RSC_IHPSG13_CINVX2 +XINV<1> q_int<1> qn_int<1> VDD VSS / RSC_IHPSG13_CINVX2 +XINV<0> q_int<0> qn_int<0> VDD VSS / RSC_IHPSG13_CINVX2 +XDRV<4> qn_int<4> ADDR_N_O<4> VDD VSS / RSC_IHPSG13_CINVX8 +XDRV<3> qn_int<3> ADDR_N_O<3> VDD VSS / RSC_IHPSG13_CINVX8 +XDRV<2> qn_int<2> ADDR_N_O<2> VDD VSS / RSC_IHPSG13_CINVX8 +XDRV<1> qn_int<1> ADDR_N_O<1> VDD VSS / RSC_IHPSG13_CINVX8 +XDRV<0> qn_int<0> ADDR_N_O<0> VDD VSS / RSC_IHPSG13_CINVX8 +XDFF<4> BIST_EN_I BIST_ADDR_I<4> ACLK_N_I ADDR_I<4> q_int<4> net2<0> VDD ++ VSS / RSC_IHPSG13_DFNQMX2IX1 +XDFF<3> BIST_EN_I BIST_ADDR_I<3> ACLK_N_I ADDR_I<3> q_int<3> net2<1> VDD ++ VSS / RSC_IHPSG13_DFNQMX2IX1 +XDFF<2> BIST_EN_I BIST_ADDR_I<2> ACLK_N_I ADDR_I<2> q_int<2> net2<2> VDD ++ VSS / RSC_IHPSG13_DFNQMX2IX1 +XDFF<1> BIST_EN_I BIST_ADDR_I<1> ACLK_N_I ADDR_I<1> q_int<1> net2<3> VDD ++ VSS / RSC_IHPSG13_DFNQMX2IX1 +XDFF<0> BIST_EN_I BIST_ADDR_I<0> ACLK_N_I ADDR_I<0> q_int<0> net2<4> VDD ++ VSS / RSC_IHPSG13_DFNQMX2IX1 +XI11<16> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI11<15> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI11<14> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI11<13> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI11<12> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI11<11> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI11<10> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI11<9> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI11<8> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI11<7> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI11<6> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI11<5> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI11<4> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI11<3> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI11<2> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI11<1> VDD VSS / RSC_IHPSG13_FILLCAP8 +.ENDS + + +.SUBCKT RM_IHPSG13_256x32_c2_1P_COLDEC5 ACLK_N ADDR<4> ADDR<3> ADDR<2> ADDR<1> ADDR<0> ++ ADDR_COL<1> ADDR_COL<0> ADDR_DEC<7> ADDR_DEC<6> ADDR_DEC<5> ADDR_DEC<4> ++ ADDR_DEC<3> ADDR_DEC<2> ADDR_DEC<1> ADDR_DEC<0> BIST_ADDR<4> BIST_ADDR<3> ++ BIST_ADDR<2> BIST_ADDR<1> BIST_ADDR<0> BIST_EN_I VDD VSS +XI17<2> VDD VSS / RSC_IHPSG13_FILLCAP4 +XI17<1> VDD VSS / RSC_IHPSG13_FILLCAP4 +XI13<1> addr_int<1> ADDR_COL<1> VDD VSS / RSC_IHPSG13_CBUFX2 +XI13<0> addr_int<0> ADDR_COL<0> VDD VSS / RSC_IHPSG13_CBUFX2 +XDFF<4> BIST_EN_I BIST_ADDR<4> ACLK_N ADDR<4> addr_int<1> net7<0> VDD ++ VSS / RSC_IHPSG13_DFNQMX2IX1 +XDFF<3> BIST_EN_I BIST_ADDR<3> ACLK_N ADDR<3> addr_int<0> net7<1> VDD ++ VSS / RSC_IHPSG13_DFNQMX2IX1 +XDFF<2> BIST_EN_I BIST_ADDR<2> ACLK_N ADDR<2> padr_int<2> net7<2> VDD ++ VSS / RSC_IHPSG13_DFNQMX2IX1 +XDFF<1> BIST_EN_I BIST_ADDR<1> ACLK_N ADDR<1> padr_int<1> net7<3> VDD ++ VSS / RSC_IHPSG13_DFNQMX2IX1 +XDFF<0> BIST_EN_I BIST_ADDR<0> ACLK_N ADDR<0> padr_int<0> net7<4> VDD ++ VSS / RSC_IHPSG13_DFNQMX2IX1 +XI1<7> PADR<0> PADR<1> PADR<2> addr_n<7> VDD VSS / RSC_IHPSG13_NAND3X2 +XI1<6> NADR<0> PADR<1> PADR<2> addr_n<6> VDD VSS / RSC_IHPSG13_NAND3X2 +XI1<5> PADR<0> NADR<1> PADR<2> addr_n<5> VDD VSS / RSC_IHPSG13_NAND3X2 +XI1<4> NADR<0> NADR<1> PADR<2> addr_n<4> VDD VSS / RSC_IHPSG13_NAND3X2 +XI1<3> PADR<0> PADR<1> NADR<2> addr_n<3> VDD VSS / RSC_IHPSG13_NAND3X2 +XI1<2> NADR<0> PADR<1> NADR<2> addr_n<2> VDD VSS / RSC_IHPSG13_NAND3X2 +XI1<1> PADR<0> NADR<1> NADR<2> addr_n<1> VDD VSS / RSC_IHPSG13_NAND3X2 +XI1<0> NADR<0> NADR<1> NADR<2> addr_n<0> VDD VSS / RSC_IHPSG13_NAND3X2 +XI15<2> NADR<2> PADR<2> VDD VSS / RSC_IHPSG13_INVX2 +XI15<1> NADR<1> PADR<1> VDD VSS / RSC_IHPSG13_INVX2 +XI15<0> NADR<0> PADR<0> VDD VSS / RSC_IHPSG13_INVX2 +XI3<2> padr_int<2> NADR<2> VDD VSS / RSC_IHPSG13_INVX2 +XI3<1> padr_int<1> NADR<1> VDD VSS / RSC_IHPSG13_INVX2 +XI3<0> padr_int<0> NADR<0> VDD VSS / RSC_IHPSG13_INVX2 +XI2<7> addr_n<7> ADDR_DEC<7> VDD VSS / RSC_IHPSG13_INVX2 +XI2<6> addr_n<6> ADDR_DEC<6> VDD VSS / RSC_IHPSG13_INVX2 +XI2<5> addr_n<5> ADDR_DEC<5> VDD VSS / RSC_IHPSG13_INVX2 +XI2<4> addr_n<4> ADDR_DEC<4> VDD VSS / RSC_IHPSG13_INVX2 +XI2<3> addr_n<3> ADDR_DEC<3> VDD VSS / RSC_IHPSG13_INVX2 +XI2<2> addr_n<2> ADDR_DEC<2> VDD VSS / RSC_IHPSG13_INVX2 +XI2<1> addr_n<1> ADDR_DEC<1> VDD VSS / RSC_IHPSG13_INVX2 +XI2<0> addr_n<0> ADDR_DEC<0> VDD VSS / RSC_IHPSG13_INVX2 +.ENDS +.SUBCKT RM_IHPSG13_256x32_c2_1P_COLCTRL5 A_ADDR_COL<1> A_ADDR_COL<0> A_ADDR_DEC<7> ++ A_ADDR_DEC<6> A_ADDR_DEC<5> A_ADDR_DEC<4> A_ADDR_DEC<3> A_ADDR_DEC<2> ++ A_ADDR_DEC<1> A_ADDR_DEC<0> A_BIST_BM_I A_BIST_DW_I A_BIST_EN_I A_BLC<31> ++ A_BLC<30> A_BLC<29> A_BLC<28> A_BLC<27> A_BLC<26> A_BLC<25> A_BLC<24> ++ A_BLC<23> A_BLC<22> A_BLC<21> A_BLC<20> A_BLC<19> A_BLC<18> A_BLC<17> ++ A_BLC<16> A_BLC<15> A_BLC<14> A_BLC<13> A_BLC<12> A_BLC<11> A_BLC<10> ++ A_BLC<9> A_BLC<8> A_BLC<7> A_BLC<6> A_BLC<5> A_BLC<4> A_BLC<3> A_BLC<2> ++ A_BLC<1> A_BLC<0> A_BLT<31> A_BLT<30> A_BLT<29> A_BLT<28> A_BLT<27> ++ A_BLT<26> A_BLT<25> A_BLT<24> A_BLT<23> A_BLT<22> A_BLT<21> A_BLT<20> ++ A_BLT<19> A_BLT<18> A_BLT<17> A_BLT<16> A_BLT<15> A_BLT<14> A_BLT<13> ++ A_BLT<12> A_BLT<11> A_BLT<10> A_BLT<9> A_BLT<8> A_BLT<7> A_BLT<6> A_BLT<5> ++ A_BLT<4> A_BLT<3> A_BLT<2> A_BLT<1> A_BLT<0> A_BM_I A_DCLK_B_L A_DCLK_B_R ++ A_DCLK_L A_DCLK_R A_DR_O A_DW_I A_RCLK_B_L A_RCLK_B_R A_RCLK_L A_RCLK_R ++ A_TIEH_O A_WCLK_B_L A_WCLK_B_R A_WCLK_L A_WCLK_R VDD VSS +XA_I80<1> A_WCLK_B_L A_RCLK_B_L A_W_nor_R<1> VDD VSS / ++ RSC_IHPSG13_AND2X2 +XA_I80<0> A_WCLK_B_L A_RCLK_B_L A_W_nor_R<0> VDD VSS / ++ RSC_IHPSG13_AND2X2 +XA_I44 A_BM_N A_WCLK_B_L A_DO_WRITE_P VDD VSS / RSC_IHPSG13_NOR2X2 +XI80<29> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI80<28> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI80<27> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI80<26> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI80<25> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI80<24> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI80<23> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI80<22> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI80<21> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI80<20> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI80<19> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI80<18> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI80<17> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI80<16> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI80<15> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI80<14> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI80<13> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI80<12> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI80<11> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI80<10> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI80<9> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI80<8> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI80<7> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI80<6> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI80<5> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI80<4> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI80<3> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI80<2> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI80<1> VDD VSS / RSC_IHPSG13_FILLCAP8 +XA_I74<16> VDD VSS / RSC_IHPSG13_FILLCAP8 +XA_I74<15> VDD VSS / RSC_IHPSG13_FILLCAP8 +XA_I74<14> VDD VSS / RSC_IHPSG13_FILLCAP8 +XA_I74<13> VDD VSS / RSC_IHPSG13_FILLCAP8 +XA_I74<12> VDD VSS / RSC_IHPSG13_FILLCAP8 +XA_I74<11> VDD VSS / RSC_IHPSG13_FILLCAP8 +XA_I74<10> VDD VSS / RSC_IHPSG13_FILLCAP8 +XA_I74<9> VDD VSS / RSC_IHPSG13_FILLCAP8 +XA_I74<8> VDD VSS / RSC_IHPSG13_FILLCAP8 +XA_I74<7> VDD VSS / RSC_IHPSG13_FILLCAP8 +XA_I74<6> VDD VSS / RSC_IHPSG13_FILLCAP8 +XA_I74<5> VDD VSS / RSC_IHPSG13_FILLCAP8 +XA_I74<4> VDD VSS / RSC_IHPSG13_FILLCAP8 +XA_I74<3> VDD VSS / RSC_IHPSG13_FILLCAP8 +XA_I74<2> VDD VSS / RSC_IHPSG13_FILLCAP8 +XA_I74<1> VDD VSS / RSC_IHPSG13_FILLCAP8 +XA_INV<6> A_N1<1> A_P1<1> VDD VSS / RSC_IHPSG13_CINVX4 +XA_INV<5> A_N0<1> A_P0<1> VDD VSS / RSC_IHPSG13_CINVX4 +XA_INV<4> A_N0<0> A_P0<0> VDD VSS / RSC_IHPSG13_CINVX4 +XA_INV<3> A_ADDR_COL<1> A_N1<1> VDD VSS / RSC_IHPSG13_CINVX4 +XA_INV<2> A_ADDR_COL<1> A_N1<0> VDD VSS / RSC_IHPSG13_CINVX4 +XA_INV<1> A_ADDR_COL<0> A_N0<1> VDD VSS / RSC_IHPSG13_CINVX4 +XA_INV<0> A_ADDR_COL<0> A_N0<0> VDD VSS / RSC_IHPSG13_CINVX4 +XA_I81<3> A_W_nor_R<1> A_PRE_N VDD VSS / RSC_IHPSG13_CINVX4_WN +XA_I81<2> A_W_nor_R<1> A_PRE_N VDD VSS / RSC_IHPSG13_CINVX4_WN +XA_I81<1> A_W_nor_R<0> A_PRE_N VDD VSS / RSC_IHPSG13_CINVX4_WN +XA_I81<0> A_W_nor_R<0> A_PRE_N VDD VSS / RSC_IHPSG13_CINVX4_WN +XA_BLTMUX<31> A_BLC<31> A_BLC_SEL A_BLT<31> A_BLT_SEL A_PRE_N A_SEL_P<31> ++ A_WR_ONE A_WR_ZERO VDD VSS / RM_IHPSG13_256x32_c2_1P_BLDRV +XA_BLTMUX<30> A_BLC<30> A_BLC_SEL A_BLT<30> A_BLT_SEL A_PRE_N A_SEL_P<30> ++ A_WR_ONE A_WR_ZERO VDD VSS / RM_IHPSG13_256x32_c2_1P_BLDRV +XA_BLTMUX<29> A_BLC<29> A_BLC_SEL A_BLT<29> A_BLT_SEL A_PRE_N A_SEL_P<29> ++ A_WR_ONE A_WR_ZERO VDD VSS / RM_IHPSG13_256x32_c2_1P_BLDRV +XA_BLTMUX<28> A_BLC<28> A_BLC_SEL A_BLT<28> A_BLT_SEL A_PRE_N A_SEL_P<28> ++ A_WR_ONE A_WR_ZERO VDD VSS / RM_IHPSG13_256x32_c2_1P_BLDRV +XA_BLTMUX<27> A_BLC<27> A_BLC_SEL A_BLT<27> A_BLT_SEL A_PRE_N A_SEL_P<27> ++ A_WR_ONE A_WR_ZERO VDD VSS / RM_IHPSG13_256x32_c2_1P_BLDRV +XA_BLTMUX<26> A_BLC<26> A_BLC_SEL A_BLT<26> A_BLT_SEL A_PRE_N A_SEL_P<26> ++ A_WR_ONE A_WR_ZERO VDD VSS / RM_IHPSG13_256x32_c2_1P_BLDRV +XA_BLTMUX<25> A_BLC<25> A_BLC_SEL A_BLT<25> A_BLT_SEL A_PRE_N A_SEL_P<25> ++ A_WR_ONE A_WR_ZERO VDD VSS / RM_IHPSG13_256x32_c2_1P_BLDRV +XA_BLTMUX<24> A_BLC<24> A_BLC_SEL A_BLT<24> A_BLT_SEL A_PRE_N A_SEL_P<24> ++ A_WR_ONE A_WR_ZERO VDD VSS / RM_IHPSG13_256x32_c2_1P_BLDRV +XA_BLTMUX<23> A_BLC<23> A_BLC_SEL A_BLT<23> A_BLT_SEL A_PRE_N A_SEL_P<23> ++ A_WR_ONE A_WR_ZERO VDD VSS / RM_IHPSG13_256x32_c2_1P_BLDRV +XA_BLTMUX<22> A_BLC<22> A_BLC_SEL A_BLT<22> A_BLT_SEL A_PRE_N A_SEL_P<22> ++ A_WR_ONE A_WR_ZERO VDD VSS / RM_IHPSG13_256x32_c2_1P_BLDRV +XA_BLTMUX<21> A_BLC<21> A_BLC_SEL A_BLT<21> A_BLT_SEL A_PRE_N A_SEL_P<21> ++ A_WR_ONE A_WR_ZERO VDD VSS / RM_IHPSG13_256x32_c2_1P_BLDRV +XA_BLTMUX<20> A_BLC<20> A_BLC_SEL A_BLT<20> A_BLT_SEL A_PRE_N A_SEL_P<20> ++ A_WR_ONE A_WR_ZERO VDD VSS / RM_IHPSG13_256x32_c2_1P_BLDRV +XA_BLTMUX<19> A_BLC<19> A_BLC_SEL A_BLT<19> A_BLT_SEL A_PRE_N A_SEL_P<19> ++ A_WR_ONE A_WR_ZERO VDD VSS / RM_IHPSG13_256x32_c2_1P_BLDRV +XA_BLTMUX<18> A_BLC<18> A_BLC_SEL A_BLT<18> A_BLT_SEL A_PRE_N A_SEL_P<18> ++ A_WR_ONE A_WR_ZERO VDD VSS / RM_IHPSG13_256x32_c2_1P_BLDRV +XA_BLTMUX<17> A_BLC<17> A_BLC_SEL A_BLT<17> A_BLT_SEL A_PRE_N A_SEL_P<17> ++ A_WR_ONE A_WR_ZERO VDD VSS / RM_IHPSG13_256x32_c2_1P_BLDRV +XA_BLTMUX<16> A_BLC<16> A_BLC_SEL A_BLT<16> A_BLT_SEL A_PRE_N A_SEL_P<16> ++ A_WR_ONE A_WR_ZERO VDD VSS / RM_IHPSG13_256x32_c2_1P_BLDRV +XA_BLTMUX<15> A_BLC<15> A_BLC_SEL A_BLT<15> A_BLT_SEL A_PRE_N A_SEL_P<15> ++ A_WR_ONE A_WR_ZERO VDD VSS / RM_IHPSG13_256x32_c2_1P_BLDRV +XA_BLTMUX<14> A_BLC<14> A_BLC_SEL A_BLT<14> A_BLT_SEL A_PRE_N A_SEL_P<14> ++ A_WR_ONE A_WR_ZERO VDD VSS / RM_IHPSG13_256x32_c2_1P_BLDRV +XA_BLTMUX<13> A_BLC<13> A_BLC_SEL A_BLT<13> A_BLT_SEL A_PRE_N A_SEL_P<13> ++ A_WR_ONE A_WR_ZERO VDD VSS / RM_IHPSG13_256x32_c2_1P_BLDRV +XA_BLTMUX<12> A_BLC<12> A_BLC_SEL A_BLT<12> A_BLT_SEL A_PRE_N A_SEL_P<12> ++ A_WR_ONE A_WR_ZERO VDD VSS / RM_IHPSG13_256x32_c2_1P_BLDRV +XA_BLTMUX<11> A_BLC<11> A_BLC_SEL A_BLT<11> A_BLT_SEL A_PRE_N A_SEL_P<11> ++ A_WR_ONE A_WR_ZERO VDD VSS / RM_IHPSG13_256x32_c2_1P_BLDRV +XA_BLTMUX<10> A_BLC<10> A_BLC_SEL A_BLT<10> A_BLT_SEL A_PRE_N A_SEL_P<10> ++ A_WR_ONE A_WR_ZERO VDD VSS / RM_IHPSG13_256x32_c2_1P_BLDRV +XA_BLTMUX<9> A_BLC<9> A_BLC_SEL A_BLT<9> A_BLT_SEL A_PRE_N A_SEL_P<9> A_WR_ONE ++ A_WR_ZERO VDD VSS / RM_IHPSG13_256x32_c2_1P_BLDRV +XA_BLTMUX<8> A_BLC<8> A_BLC_SEL A_BLT<8> A_BLT_SEL A_PRE_N A_SEL_P<8> A_WR_ONE ++ A_WR_ZERO VDD VSS / RM_IHPSG13_256x32_c2_1P_BLDRV +XA_BLTMUX<7> A_BLC<7> A_BLC_SEL A_BLT<7> A_BLT_SEL A_PRE_N A_SEL_P<7> A_WR_ONE ++ A_WR_ZERO VDD VSS / RM_IHPSG13_256x32_c2_1P_BLDRV +XA_BLTMUX<6> A_BLC<6> A_BLC_SEL A_BLT<6> A_BLT_SEL A_PRE_N A_SEL_P<6> A_WR_ONE ++ A_WR_ZERO VDD VSS / RM_IHPSG13_256x32_c2_1P_BLDRV +XA_BLTMUX<5> A_BLC<5> A_BLC_SEL A_BLT<5> A_BLT_SEL A_PRE_N A_SEL_P<5> A_WR_ONE ++ A_WR_ZERO VDD VSS / RM_IHPSG13_256x32_c2_1P_BLDRV +XA_BLTMUX<4> A_BLC<4> A_BLC_SEL A_BLT<4> A_BLT_SEL A_PRE_N A_SEL_P<4> A_WR_ONE ++ A_WR_ZERO VDD VSS / RM_IHPSG13_256x32_c2_1P_BLDRV +XA_BLTMUX<3> A_BLC<3> A_BLC_SEL A_BLT<3> A_BLT_SEL A_PRE_N A_SEL_P<3> A_WR_ONE ++ A_WR_ZERO VDD VSS / RM_IHPSG13_256x32_c2_1P_BLDRV +XA_BLTMUX<2> A_BLC<2> A_BLC_SEL A_BLT<2> A_BLT_SEL A_PRE_N A_SEL_P<2> A_WR_ONE ++ A_WR_ZERO VDD VSS / RM_IHPSG13_256x32_c2_1P_BLDRV +XA_BLTMUX<1> A_BLC<1> A_BLC_SEL A_BLT<1> A_BLT_SEL A_PRE_N A_SEL_P<1> A_WR_ONE ++ A_WR_ZERO VDD VSS / RM_IHPSG13_256x32_c2_1P_BLDRV +XA_BLTMUX<0> A_BLC<0> A_BLC_SEL A_BLT<0> A_BLT_SEL A_PRE_N A_SEL_P<0> A_WR_ONE ++ A_WR_ZERO VDD VSS / RM_IHPSG13_256x32_c2_1P_BLDRV +XA_CAPS<17> VDD VSS / RSC_IHPSG13_FILLCAP4 +XA_CAPS<16> VDD VSS / RSC_IHPSG13_FILLCAP4 +XA_CAPS<15> VDD VSS / RSC_IHPSG13_FILLCAP4 +XA_CAPS<14> VDD VSS / RSC_IHPSG13_FILLCAP4 +XA_CAPS<13> VDD VSS / RSC_IHPSG13_FILLCAP4 +XA_CAPS<12> VDD VSS / RSC_IHPSG13_FILLCAP4 +XA_CAPS<11> VDD VSS / RSC_IHPSG13_FILLCAP4 +XA_CAPS<10> VDD VSS / RSC_IHPSG13_FILLCAP4 +XA_CAPS<9> VDD VSS / RSC_IHPSG13_FILLCAP4 +XA_CAPS<8> VDD VSS / RSC_IHPSG13_FILLCAP4 +XA_CAPS<7> VDD VSS / RSC_IHPSG13_FILLCAP4 +XA_CAPS<6> VDD VSS / RSC_IHPSG13_FILLCAP4 +XA_CAPS<5> VDD VSS / RSC_IHPSG13_FILLCAP4 +XA_CAPS<4> VDD VSS / RSC_IHPSG13_FILLCAP4 +XA_CAPS<3> VDD VSS / RSC_IHPSG13_FILLCAP4 +XA_CAPS<2> VDD VSS / RSC_IHPSG13_FILLCAP4 +XA_CAPS<1> VDD VSS / RSC_IHPSG13_FILLCAP4 +XA_I51 net19 A_DR_O VDD VSS / RSC_IHPSG13_INVX4 +XA_I78 A_RCLK_B_L A_SAE VDD VSS / RSC_IHPSG13_CBUFX2 +XA_I69 A_DCLK_L A_DCLK_B_L VDD VSS / RSC_IHPSG13_CINVX8 +XA_I50 A_WCLK_L A_WCLK_B_L VDD VSS / RSC_IHPSG13_CINVX8 +XA_EBUF A_RCLK_L A_RCLK_B_L VDD VSS / RSC_IHPSG13_CINVX8 +XA_I76 A_DI_N A_DO_WRITE_P A_WR_ZERO VDD VSS / RSC_IHPSG13_AND2X6 +XA_I75 A_DI_R A_DO_WRITE_P A_WR_ONE VDD VSS / RSC_IHPSG13_AND2X6 +XA_I83 A_BM_R A_BM_N VDD VSS / RSC_IHPSG13_INVX2 +XA_DEC3INV<31> net23<0> A_SEL_P<31> VDD VSS / RSC_IHPSG13_INVX2 +XA_DEC3INV<30> net23<1> A_SEL_P<30> VDD VSS / RSC_IHPSG13_INVX2 +XA_DEC3INV<29> net23<2> A_SEL_P<29> VDD VSS / RSC_IHPSG13_INVX2 +XA_DEC3INV<28> net23<3> A_SEL_P<28> VDD VSS / RSC_IHPSG13_INVX2 +XA_DEC3INV<27> net23<4> A_SEL_P<27> VDD VSS / RSC_IHPSG13_INVX2 +XA_DEC3INV<26> net23<5> A_SEL_P<26> VDD VSS / RSC_IHPSG13_INVX2 +XA_DEC3INV<25> net23<6> A_SEL_P<25> VDD VSS / RSC_IHPSG13_INVX2 +XA_DEC3INV<24> net23<7> A_SEL_P<24> VDD VSS / RSC_IHPSG13_INVX2 +XA_DEC3INV<23> net23<8> A_SEL_P<23> VDD VSS / RSC_IHPSG13_INVX2 +XA_DEC3INV<22> net23<9> A_SEL_P<22> VDD VSS / RSC_IHPSG13_INVX2 +XA_DEC3INV<21> net23<10> A_SEL_P<21> VDD VSS / RSC_IHPSG13_INVX2 +XA_DEC3INV<20> net23<11> A_SEL_P<20> VDD VSS / RSC_IHPSG13_INVX2 +XA_DEC3INV<19> net23<12> A_SEL_P<19> VDD VSS / RSC_IHPSG13_INVX2 +XA_DEC3INV<18> net23<13> A_SEL_P<18> VDD VSS / RSC_IHPSG13_INVX2 +XA_DEC3INV<17> net23<14> A_SEL_P<17> VDD VSS / RSC_IHPSG13_INVX2 +XA_DEC3INV<16> net23<15> A_SEL_P<16> VDD VSS / RSC_IHPSG13_INVX2 +XA_DEC3INV<15> net23<16> A_SEL_P<15> VDD VSS / RSC_IHPSG13_INVX2 +XA_DEC3INV<14> net23<17> A_SEL_P<14> VDD VSS / RSC_IHPSG13_INVX2 +XA_DEC3INV<13> net23<18> A_SEL_P<13> VDD VSS / RSC_IHPSG13_INVX2 +XA_DEC3INV<12> net23<19> A_SEL_P<12> VDD VSS / RSC_IHPSG13_INVX2 +XA_DEC3INV<11> net23<20> A_SEL_P<11> VDD VSS / RSC_IHPSG13_INVX2 +XA_DEC3INV<10> net23<21> A_SEL_P<10> VDD VSS / RSC_IHPSG13_INVX2 +XA_DEC3INV<9> net23<22> A_SEL_P<9> VDD VSS / RSC_IHPSG13_INVX2 +XA_DEC3INV<8> net23<23> A_SEL_P<8> VDD VSS / RSC_IHPSG13_INVX2 +XA_DEC3INV<7> net23<24> A_SEL_P<7> VDD VSS / RSC_IHPSG13_INVX2 +XA_DEC3INV<6> net23<25> A_SEL_P<6> VDD VSS / RSC_IHPSG13_INVX2 +XA_DEC3INV<5> net23<26> A_SEL_P<5> VDD VSS / RSC_IHPSG13_INVX2 +XA_DEC3INV<4> net23<27> A_SEL_P<4> VDD VSS / RSC_IHPSG13_INVX2 +XA_DEC3INV<3> net23<28> A_SEL_P<3> VDD VSS / RSC_IHPSG13_INVX2 +XA_DEC3INV<2> net23<29> A_SEL_P<2> VDD VSS / RSC_IHPSG13_INVX2 +XA_DEC3INV<1> net23<30> A_SEL_P<1> VDD VSS / RSC_IHPSG13_INVX2 +XA_DEC3INV<0> net23<31> A_SEL_P<0> VDD VSS / RSC_IHPSG13_INVX2 +XA_I49 A_DI_R A_DI_N VDD VSS / RSC_IHPSG13_INVX2 +XA_ISENSE A_SAE A_BLC_SEL A_BLT_SEL net19 net20 VDD VSS / ++ RSC_IHPSG13_DFPQD_MSAFFX2 +XA_DREG A_BIST_EN_I A_BIST_DW_I A_DCLK_B_L A_DW_I A_DI_R net22 VDD VSS ++ / RSC_IHPSG13_DFNQMX2IX1 +XA_BREG A_BIST_EN_I A_BIST_BM_I A_DCLK_B_L A_BM_I A_BM_R net21 VDD VSS ++ / RSC_IHPSG13_DFNQMX2IX1 +XA_DEC3<31> A_P1<1> A_P0<1> A_ADDR_DEC<7> net23<0> VDD VSS / ++ RSC_IHPSG13_NAND3X2 +XA_DEC3<30> A_P1<1> A_P0<1> A_ADDR_DEC<6> net23<1> VDD VSS / ++ RSC_IHPSG13_NAND3X2 +XA_DEC3<29> A_P1<1> A_P0<1> A_ADDR_DEC<5> net23<2> VDD VSS / ++ RSC_IHPSG13_NAND3X2 +XA_DEC3<28> A_P1<1> A_P0<1> A_ADDR_DEC<4> net23<3> VDD VSS / ++ RSC_IHPSG13_NAND3X2 +XA_DEC3<27> A_P1<1> A_P0<1> A_ADDR_DEC<3> net23<4> VDD VSS / ++ RSC_IHPSG13_NAND3X2 +XA_DEC3<26> A_P1<1> A_P0<1> A_ADDR_DEC<2> net23<5> VDD VSS / ++ RSC_IHPSG13_NAND3X2 +XA_DEC3<25> A_P1<1> A_P0<1> A_ADDR_DEC<1> net23<6> VDD VSS / ++ RSC_IHPSG13_NAND3X2 +XA_DEC3<24> A_P1<1> A_P0<1> A_ADDR_DEC<0> net23<7> VDD VSS / ++ RSC_IHPSG13_NAND3X2 +XA_DEC3<23> A_P1<1> A_N0<1> A_ADDR_DEC<7> net23<8> VDD VSS / ++ RSC_IHPSG13_NAND3X2 +XA_DEC3<22> A_P1<1> A_N0<1> A_ADDR_DEC<6> net23<9> VDD VSS / ++ RSC_IHPSG13_NAND3X2 +XA_DEC3<21> A_P1<1> A_N0<1> A_ADDR_DEC<5> net23<10> VDD VSS / ++ RSC_IHPSG13_NAND3X2 +XA_DEC3<20> A_P1<1> A_N0<1> A_ADDR_DEC<4> net23<11> VDD VSS / ++ RSC_IHPSG13_NAND3X2 +XA_DEC3<19> A_P1<1> A_N0<1> A_ADDR_DEC<3> net23<12> VDD VSS / ++ RSC_IHPSG13_NAND3X2 +XA_DEC3<18> A_P1<1> A_N0<1> A_ADDR_DEC<2> net23<13> VDD VSS / ++ RSC_IHPSG13_NAND3X2 +XA_DEC3<17> A_P1<1> A_N0<1> A_ADDR_DEC<1> net23<14> VDD VSS / ++ RSC_IHPSG13_NAND3X2 +XA_DEC3<16> A_P1<1> A_N0<1> A_ADDR_DEC<0> net23<15> VDD VSS / ++ RSC_IHPSG13_NAND3X2 +XA_DEC3<15> A_N1<0> A_P0<0> A_ADDR_DEC<7> net23<16> VDD VSS / ++ RSC_IHPSG13_NAND3X2 +XA_DEC3<14> A_N1<0> A_P0<0> A_ADDR_DEC<6> net23<17> VDD VSS / ++ RSC_IHPSG13_NAND3X2 +XA_DEC3<13> A_N1<0> A_P0<0> A_ADDR_DEC<5> net23<18> VDD VSS / ++ RSC_IHPSG13_NAND3X2 +XA_DEC3<12> A_N1<0> A_P0<0> A_ADDR_DEC<4> net23<19> VDD VSS / ++ RSC_IHPSG13_NAND3X2 +XA_DEC3<11> A_N1<0> A_P0<0> A_ADDR_DEC<3> net23<20> VDD VSS / ++ RSC_IHPSG13_NAND3X2 +XA_DEC3<10> A_N1<0> A_P0<0> A_ADDR_DEC<2> net23<21> VDD VSS / ++ RSC_IHPSG13_NAND3X2 +XA_DEC3<9> A_N1<0> A_P0<0> A_ADDR_DEC<1> net23<22> VDD VSS / ++ RSC_IHPSG13_NAND3X2 +XA_DEC3<8> A_N1<0> A_P0<0> A_ADDR_DEC<0> net23<23> VDD VSS / ++ RSC_IHPSG13_NAND3X2 +XA_DEC3<7> A_N1<0> A_N0<0> A_ADDR_DEC<7> net23<24> VDD VSS / ++ RSC_IHPSG13_NAND3X2 +XA_DEC3<6> A_N1<0> A_N0<0> A_ADDR_DEC<6> net23<25> VDD VSS / ++ RSC_IHPSG13_NAND3X2 +XA_DEC3<5> A_N1<0> A_N0<0> A_ADDR_DEC<5> net23<26> VDD VSS / ++ RSC_IHPSG13_NAND3X2 +XA_DEC3<4> A_N1<0> A_N0<0> A_ADDR_DEC<4> net23<27> VDD VSS / ++ RSC_IHPSG13_NAND3X2 +XA_DEC3<3> A_N1<0> A_N0<0> A_ADDR_DEC<3> net23<28> VDD VSS / ++ RSC_IHPSG13_NAND3X2 +XA_DEC3<2> A_N1<0> A_N0<0> A_ADDR_DEC<2> net23<29> VDD VSS / ++ RSC_IHPSG13_NAND3X2 +XA_DEC3<1> A_N1<0> A_N0<0> A_ADDR_DEC<1> net23<30> VDD VSS / ++ RSC_IHPSG13_NAND3X2 +XA_DEC3<0> A_N1<0> A_N0<0> A_ADDR_DEC<0> net23<31> VDD VSS / ++ RSC_IHPSG13_NAND3X2 +XA_I89 A_DCLK_B_L A_DCLK_B_R / RSC_IHPSG13_MET3RES +XA_I91 A_RCLK_B_L A_RCLK_B_R / RSC_IHPSG13_MET3RES +XA_I90 A_WCLK_B_L A_WCLK_B_R / RSC_IHPSG13_MET3RES +XA_I88 A_DCLK_L A_DCLK_R / RSC_IHPSG13_MET3RES +XA_I87 A_WCLK_L A_WCLK_R / RSC_IHPSG13_MET3RES +XA_R2 A_RCLK_L A_RCLK_R / RSC_IHPSG13_MET3RES +XA_BM_TIEH A_TIEH_O VDD VSS / RSC_IHPSG13_TIEH +.ENDS + +.SUBCKT RM_IHPSG13_256x32_c2_1P_COLDRV13X12 ADDR_COL_I<1> ADDR_COL_I<0> ADDR_COL_O<1> ++ ADDR_COL_O<0> ADDR_DEC_I<7> ADDR_DEC_I<6> ADDR_DEC_I<5> ADDR_DEC_I<4> ++ ADDR_DEC_I<3> ADDR_DEC_I<2> ADDR_DEC_I<1> ADDR_DEC_I<0> ADDR_DEC_O<7> ++ ADDR_DEC_O<6> ADDR_DEC_O<5> ADDR_DEC_O<4> ADDR_DEC_O<3> ADDR_DEC_O<2> ++ ADDR_DEC_O<1> ADDR_DEC_O<0> DCLK_I DCLK_O RCLK_I RCLK_O WCLK_I WCLK_O ++ VDD VSS +XI1<1> VDD VSS / RSC_IHPSG13_FILLCAP4 +XI1<0> VDD VSS / RSC_IHPSG13_FILLCAP4 +XI0<1> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI0<0> VDD VSS / RSC_IHPSG13_FILLCAP8 +XADDR_COL_DRV<1> ADDR_COL_I<1> ADDR_COL_O<1> VDD VSS / ++ RSC_IHPSG13_CBUFX12 +XADDR_COL_DRV<0> ADDR_COL_I<0> ADDR_COL_O<0> VDD VSS / ++ RSC_IHPSG13_CBUFX12 +XADDR_DEC_DRV<7> ADDR_DEC_I<7> ADDR_DEC_O<7> VDD VSS / ++ RSC_IHPSG13_CBUFX12 +XADDR_DEC_DRV<6> ADDR_DEC_I<6> ADDR_DEC_O<6> VDD VSS / ++ RSC_IHPSG13_CBUFX12 +XADDR_DEC_DRV<5> ADDR_DEC_I<5> ADDR_DEC_O<5> VDD VSS / ++ RSC_IHPSG13_CBUFX12 +XADDR_DEC_DRV<4> ADDR_DEC_I<4> ADDR_DEC_O<4> VDD VSS / ++ RSC_IHPSG13_CBUFX12 +XADDR_DEC_DRV<3> ADDR_DEC_I<3> ADDR_DEC_O<3> VDD VSS / ++ RSC_IHPSG13_CBUFX12 +XADDR_DEC_DRV<2> ADDR_DEC_I<2> ADDR_DEC_O<2> VDD VSS / ++ RSC_IHPSG13_CBUFX12 +XADDR_DEC_DRV<1> ADDR_DEC_I<1> ADDR_DEC_O<1> VDD VSS / ++ RSC_IHPSG13_CBUFX12 +XADDR_DEC_DRV<0> ADDR_DEC_I<0> ADDR_DEC_O<0> VDD VSS / ++ RSC_IHPSG13_CBUFX12 +XDCLK_DRV DCLK_I DCLK_O VDD VSS / RSC_IHPSG13_CBUFX12 +XRCLK_DRV RCLK_I RCLK_O VDD VSS / RSC_IHPSG13_CBUFX12 +XWCLK_DRV WCLK_I WCLK_O VDD VSS / RSC_IHPSG13_CBUFX12 +.ENDS +.SUBCKT RM_IHPSG13_256x32_c2_1P_WLDRV16X12 A<15> A<14> A<13> A<12> A<11> A<10> A<9> A<8> ++ A<7> A<6> A<5> A<4> A<3> A<2> A<1> A<0> Z<15> Z<14> Z<13> Z<12> Z<11> Z<10> ++ Z<9> Z<8> Z<7> Z<6> Z<5> Z<4> Z<3> Z<2> Z<1> Z<0> VDD VSS +XBUF<15> A<15> Z<15> VDD VSS / RSC_IHPSG13_WLDRVX12 +XBUF<14> A<14> Z<14> VDD VSS / RSC_IHPSG13_WLDRVX12 +XBUF<13> A<13> Z<13> VDD VSS / RSC_IHPSG13_WLDRVX12 +XBUF<12> A<12> Z<12> VDD VSS / RSC_IHPSG13_WLDRVX12 +XBUF<11> A<11> Z<11> VDD VSS / RSC_IHPSG13_WLDRVX12 +XBUF<10> A<10> Z<10> VDD VSS / RSC_IHPSG13_WLDRVX12 +XBUF<9> A<9> Z<9> VDD VSS / RSC_IHPSG13_WLDRVX12 +XBUF<8> A<8> Z<8> VDD VSS / RSC_IHPSG13_WLDRVX12 +XBUF<7> A<7> Z<7> VDD VSS / RSC_IHPSG13_WLDRVX12 +XBUF<6> A<6> Z<6> VDD VSS / RSC_IHPSG13_WLDRVX12 +XBUF<5> A<5> Z<5> VDD VSS / RSC_IHPSG13_WLDRVX12 +XBUF<4> A<4> Z<4> VDD VSS / RSC_IHPSG13_WLDRVX12 +XBUF<3> A<3> Z<3> VDD VSS / RSC_IHPSG13_WLDRVX12 +XBUF<2> A<2> Z<2> VDD VSS / RSC_IHPSG13_WLDRVX12 +XBUF<1> A<1> Z<1> VDD VSS / RSC_IHPSG13_WLDRVX12 +XBUF<0> A<0> Z<0> VDD VSS / RSC_IHPSG13_WLDRVX12 +.ENDS + + + +.SUBCKT RM_IHPSG13_256x32_c2_2P_COLDRV13X8 ADDR_COL_I<1> ADDR_COL_I<0> ADDR_COL_O<1> ++ ADDR_COL_O<0> ADDR_DEC_I<7> ADDR_DEC_I<6> ADDR_DEC_I<5> ADDR_DEC_I<4> ++ ADDR_DEC_I<3> ADDR_DEC_I<2> ADDR_DEC_I<1> ADDR_DEC_I<0> ADDR_DEC_O<7> ++ ADDR_DEC_O<6> ADDR_DEC_O<5> ADDR_DEC_O<4> ADDR_DEC_O<3> ADDR_DEC_O<2> ++ ADDR_DEC_O<1> ADDR_DEC_O<0> DCLK_I DCLK_O RCLK_I RCLK_O WCLK_I WCLK_O ++ VDD VSS +XI0<5> VDD VSS / RSC_IHPSG13_FILLCAP4 +XI0<4> VDD VSS / RSC_IHPSG13_FILLCAP4 +XI0<3> VDD VSS / RSC_IHPSG13_FILLCAP4 +XI0<2> VDD VSS / RSC_IHPSG13_FILLCAP4 +XI0<1> VDD VSS / RSC_IHPSG13_FILLCAP4 +XWCLK_DRV WCLK_I WCLK_O VDD VSS / RSC_IHPSG13_CBUFX8 +XRCLK_DRV RCLK_I RCLK_O VDD VSS / RSC_IHPSG13_CBUFX8 +XDCLK_DRV DCLK_I DCLK_O VDD VSS / RSC_IHPSG13_CBUFX8 +XADDR_COL_DRV<1> ADDR_COL_I<1> ADDR_COL_O<1> VDD VSS / ++ RSC_IHPSG13_CBUFX8 +XADDR_COL_DRV<0> ADDR_COL_I<0> ADDR_COL_O<0> VDD VSS / ++ RSC_IHPSG13_CBUFX8 +XADDR_DEC_DRV<7> ADDR_DEC_I<7> ADDR_DEC_O<7> VDD VSS / ++ RSC_IHPSG13_CBUFX8 +XADDR_DEC_DRV<6> ADDR_DEC_I<6> ADDR_DEC_O<6> VDD VSS / ++ RSC_IHPSG13_CBUFX8 +XADDR_DEC_DRV<5> ADDR_DEC_I<5> ADDR_DEC_O<5> VDD VSS / ++ RSC_IHPSG13_CBUFX8 +XADDR_DEC_DRV<4> ADDR_DEC_I<4> ADDR_DEC_O<4> VDD VSS / ++ RSC_IHPSG13_CBUFX8 +XADDR_DEC_DRV<3> ADDR_DEC_I<3> ADDR_DEC_O<3> VDD VSS / ++ RSC_IHPSG13_CBUFX8 +XADDR_DEC_DRV<2> ADDR_DEC_I<2> ADDR_DEC_O<2> VDD VSS / ++ RSC_IHPSG13_CBUFX8 +XADDR_DEC_DRV<1> ADDR_DEC_I<1> ADDR_DEC_O<1> VDD VSS / ++ RSC_IHPSG13_CBUFX8 +XADDR_DEC_DRV<0> ADDR_DEC_I<0> ADDR_DEC_O<0> VDD VSS / ++ RSC_IHPSG13_CBUFX8 +XI1<3> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI1<2> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI1<1> VDD VSS / RSC_IHPSG13_FILLCAP8 +.ENDS +.SUBCKT RSC_IHPSG13_WLDRVX8 A Z VDD VSS +MN1 Z net6 VSS VSS sg13_lv_nmos m=1 w=1.41u l=130.00n ng=2 nrd=0 nrs=0 +MN0 net6 A VSS VSS sg13_lv_nmos m=1 w=1.8u l=130.00n ng=2 nrd=0 nrs=0 +MP1 Z net6 VDD VDD sg13_lv_pmos m=1 w=6.48u l=130.00n ng=4 nrd=0 nrs=0 +MP0 net6 A VDD VDD sg13_lv_pmos m=1 w=900.0n l=130.00n ng=1 nrd=0 nrs=0 +.ENDS +.SUBCKT RM_IHPSG13_256x32_c2_2P_WLDRV16X8 A<15> A<14> A<13> A<12> A<11> A<10> A<9> A<8> ++ A<7> A<6> A<5> A<4> A<3> A<2> A<1> A<0> Z<15> Z<14> Z<13> Z<12> Z<11> Z<10> ++ Z<9> Z<8> Z<7> Z<6> Z<5> Z<4> Z<3> Z<2> Z<1> Z<0> VDD VSS +XBUF<15> A<15> Z<15> VDD VSS / RSC_IHPSG13_WLDRVX8 +XBUF<14> A<14> Z<14> VDD VSS / RSC_IHPSG13_WLDRVX8 +XBUF<13> A<13> Z<13> VDD VSS / RSC_IHPSG13_WLDRVX8 +XBUF<12> A<12> Z<12> VDD VSS / RSC_IHPSG13_WLDRVX8 +XBUF<11> A<11> Z<11> VDD VSS / RSC_IHPSG13_WLDRVX8 +XBUF<10> A<10> Z<10> VDD VSS / RSC_IHPSG13_WLDRVX8 +XBUF<9> A<9> Z<9> VDD VSS / RSC_IHPSG13_WLDRVX8 +XBUF<8> A<8> Z<8> VDD VSS / RSC_IHPSG13_WLDRVX8 +XBUF<7> A<7> Z<7> VDD VSS / RSC_IHPSG13_WLDRVX8 +XBUF<6> A<6> Z<6> VDD VSS / RSC_IHPSG13_WLDRVX8 +XBUF<5> A<5> Z<5> VDD VSS / RSC_IHPSG13_WLDRVX8 +XBUF<4> A<4> Z<4> VDD VSS / RSC_IHPSG13_WLDRVX8 +XBUF<3> A<3> Z<3> VDD VSS / RSC_IHPSG13_WLDRVX8 +XBUF<2> A<2> Z<2> VDD VSS / RSC_IHPSG13_WLDRVX8 +XBUF<1> A<1> Z<1> VDD VSS / RSC_IHPSG13_WLDRVX8 +XBUF<0> A<0> Z<0> VDD VSS / RSC_IHPSG13_WLDRVX8 +.ENDS + + + +.SUBCKT RM_IHPSG13_256x32_c2_2P_COLDEC2 ACLK_N ADDR<1> ADDR<0> ADDR_COL<1> ADDR_COL<0> ++ ADDR_DEC<7> ADDR_DEC<6> ADDR_DEC<5> ADDR_DEC<4> ADDR_DEC<3> ADDR_DEC<2> ++ ADDR_DEC<1> ADDR_DEC<0> BIST_ADDR<1> BIST_ADDR<0> BIST_EN_I VDD VSS +XI16<17> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI16<16> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI16<15> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI16<14> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI16<13> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI16<12> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI16<11> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI16<10> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI16<9> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI16<8> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI16<7> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI16<6> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI16<5> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI16<4> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI16<3> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI16<2> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI16<1> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI18<24> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI18<23> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI18<22> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI18<21> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI18<20> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI18<19> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI18<18> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI18<17> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI18<16> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI18<15> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI18<14> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI18<13> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI18<12> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI18<11> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI18<10> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI18<9> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI18<8> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI18<7> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI18<6> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI18<5> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI18<4> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI18<3> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI18<2> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI18<1> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI1<3> PADR<0> PADR<1> addr_n<3> VDD VSS / RSC_IHPSG13_NAND2X2 +XI1<2> NADR<0> PADR<1> addr_n<2> VDD VSS / RSC_IHPSG13_NAND2X2 +XI1<1> PADR<0> NADR<1> addr_n<1> VDD VSS / RSC_IHPSG13_NAND2X2 +XI1<0> NADR<0> NADR<1> addr_n<0> VDD VSS / RSC_IHPSG13_NAND2X2 +XI17<1> ADDR_COL<1> VDD VSS / RSC_IHPSG13_TIEL +XI17<0> ADDR_COL<0> VDD VSS / RSC_IHPSG13_TIEL +XI14<3> ADDR_DEC<7> VDD VSS / RSC_IHPSG13_TIEL +XI14<2> ADDR_DEC<6> VDD VSS / RSC_IHPSG13_TIEL +XI14<1> ADDR_DEC<5> VDD VSS / RSC_IHPSG13_TIEL +XI14<0> ADDR_DEC<4> VDD VSS / RSC_IHPSG13_TIEL +XI13<1> NADR<1> PADR<1> VDD VSS / RSC_IHPSG13_INVX2 +XI13<0> NADR<0> PADR<0> VDD VSS / RSC_IHPSG13_INVX2 +XI3<1> padr_int<1> NADR<1> VDD VSS / RSC_IHPSG13_INVX2 +XI3<0> padr_int<0> NADR<0> VDD VSS / RSC_IHPSG13_INVX2 +XI2<3> addr_n<3> ADDR_DEC<3> VDD VSS / RSC_IHPSG13_INVX2 +XI2<2> addr_n<2> ADDR_DEC<2> VDD VSS / RSC_IHPSG13_INVX2 +XI2<1> addr_n<1> ADDR_DEC<1> VDD VSS / RSC_IHPSG13_INVX2 +XI2<0> addr_n<0> ADDR_DEC<0> VDD VSS / RSC_IHPSG13_INVX2 +XDFF<1> BIST_EN_I BIST_ADDR<1> ACLK_N ADDR<1> padr_int<1> net12<0> VDD ++ VSS / RSC_IHPSG13_DFNQMX2IX1 +XDFF<0> BIST_EN_I BIST_ADDR<0> ACLK_N ADDR<0> padr_int<0> net12<1> VDD ++ VSS / RSC_IHPSG13_DFNQMX2IX1 +XI15<5> VDD VSS / RSC_IHPSG13_FILLCAP4 +XI15<4> VDD VSS / RSC_IHPSG13_FILLCAP4 +XI15<3> VDD VSS / RSC_IHPSG13_FILLCAP4 +XI15<2> VDD VSS / RSC_IHPSG13_FILLCAP4 +XI15<1> VDD VSS / RSC_IHPSG13_FILLCAP4 +XI19<4> VDD VSS / RSC_IHPSG13_FILLCAP4 +XI19<3> VDD VSS / RSC_IHPSG13_FILLCAP4 +XI19<2> VDD VSS / RSC_IHPSG13_FILLCAP4 +XI19<1> VDD VSS / RSC_IHPSG13_FILLCAP4 +.ENDS +.SUBCKT RM_IHPSG13_256x32_c2_2P_COLCTRL2 A_ADDR_DEC<3> A_ADDR_DEC<2> A_ADDR_DEC<1> ++ A_ADDR_DEC<0> A_BIST_BM_I A_BIST_DW_I A_BIST_EN_I A_BLC<3> A_BLC<2> A_BLC<1> ++ A_BLC<0> A_BLT<3> A_BLT<2> A_BLT<1> A_BLT<0> A_BM_I A_DCLK_B_L A_DCLK_B_R ++ A_DCLK_L A_DCLK_R A_DR_O A_DW_I A_RCLK_B_L A_RCLK_B_R A_RCLK_L A_RCLK_R ++ A_TIEH_O A_WCLK_B_L A_WCLK_B_R A_WCLK_L A_WCLK_R B_ADDR_DEC<3> B_ADDR_DEC<2> ++ B_ADDR_DEC<1> B_ADDR_DEC<0> B_BIST_BM_I B_BIST_DW_I B_BIST_EN_I B_BLC<3> ++ B_BLC<2> B_BLC<1> B_BLC<0> B_BLT<3> B_BLT<2> B_BLT<1> B_BLT<0> B_BM_I ++ B_DCLK_B_L B_DCLK_B_R B_DCLK_L B_DCLK_R B_DR_O B_DW_I B_RCLK_B_L B_RCLK_B_R ++ B_RCLK_L B_RCLK_R B_TIEH_O B_WCLK_B_L B_WCLK_B_R B_WCLK_L B_WCLK_R VDD ++ VSS +XB_DREG B_BIST_EN_I B_BIST_DW_I B_DCLK_B_L B_DW_I B_DI_R net046 VDD ++ VSS / RSC_IHPSG13_DFNQMX2IX1 +XB_BREG B_BIST_EN_I B_BIST_BM_I B_DCLK_B_L B_BM_I B_BM_R net045 VDD ++ VSS / RSC_IHPSG13_DFNQMX2IX1 +XA_DREG A_BIST_EN_I A_BIST_DW_I A_DCLK_B_L A_DW_I A_DI_R net22 VDD VSS ++ / RSC_IHPSG13_DFNQMX2IX1 +XA_BREG A_BIST_EN_I A_BIST_BM_I A_DCLK_B_L A_BM_I A_BM_R net23 VDD VSS ++ / RSC_IHPSG13_DFNQMX2IX1 +XB_CAPS VDD VSS / RSC_IHPSG13_FILLCAP4 +XA_CAPS VDD VSS / RSC_IHPSG13_FILLCAP4 +XB_I75 B_DI_R B_DO_WRITE_P B_WR_ONE VDD VSS / RSC_IHPSG13_AND2X2 +XB_I80 B_RCLK_B_L B_WCLK_B_L net041 VDD VSS / RSC_IHPSG13_AND2X2 +XB_I76 B_DI_N B_DO_WRITE_P B_WR_ZERO VDD VSS / RSC_IHPSG13_AND2X2 +XA_I80 A_RCLK_B_L A_WCLK_B_L net21 VDD VSS / RSC_IHPSG13_AND2X2 +XA_I75 A_DI_R A_DO_WRITE_P A_WR_ONE VDD VSS / RSC_IHPSG13_AND2X2 +XA_I76 A_DI_N A_DO_WRITE_P A_WR_ZERO VDD VSS / RSC_IHPSG13_AND2X2 +XB_I44 B_WCLK_B_L B_BM_N B_DO_WRITE_P VDD VSS / RSC_IHPSG13_NOR2X2 +XA_I44 A_WCLK_B_L A_BM_N A_DO_WRITE_P VDD VSS / RSC_IHPSG13_NOR2X2 +XB_I81 net041 B_PRE_N VDD VSS / RSC_IHPSG13_CINVX4_WN +XA_I81 net21 A_PRE_N VDD VSS / RSC_IHPSG13_CINVX4_WN +XB_BM_TIEH B_TIEH_O VDD VSS / RSC_IHPSG13_TIEH +XA_BM_TIEH A_TIEH_O VDD VSS / RSC_IHPSG13_TIEH +XA_I89 A_DCLK_B_L A_DCLK_B_R / RSC_IHPSG13_MET3RES +XA_I88 A_DCLK_L A_DCLK_R / RSC_IHPSG13_MET3RES +XA_I87 A_WCLK_L A_WCLK_R / RSC_IHPSG13_MET3RES +XA_I91 A_RCLK_B_L A_RCLK_B_R / RSC_IHPSG13_MET3RES +XB_I87 B_WCLK_L B_WCLK_R / RSC_IHPSG13_MET3RES +XB_I88 B_DCLK_L B_DCLK_R / RSC_IHPSG13_MET3RES +XB_I89 B_DCLK_B_L B_DCLK_B_R / RSC_IHPSG13_MET3RES +XB_I90 B_WCLK_B_L B_WCLK_B_R / RSC_IHPSG13_MET3RES +XB_R2 B_RCLK_L B_RCLK_R / RSC_IHPSG13_MET3RES +XB_I91 B_RCLK_B_L B_RCLK_B_R / RSC_IHPSG13_MET3RES +XA_R2 A_RCLK_L A_RCLK_R / RSC_IHPSG13_MET3RES +XA_I90 A_WCLK_B_L A_WCLK_B_R / RSC_IHPSG13_MET3RES +XAB_BLMUX A_BLC<3> A_BLC<2> A_BLC<1> A_BLC<0> A_BLC_SEL A_BLT<3> A_BLT<2> ++ A_BLT<1> A_BLT<0> A_BLT_SEL A_PRE_N A_ADDR_DEC<3> A_ADDR_DEC<2> ++ A_ADDR_DEC<1> A_ADDR_DEC<0> A_WR_ONE A_WR_ZERO B_BLC<3> B_BLC<2> B_BLC<1> ++ B_BLC<0> B_BLC_SEL B_BLT<3> B_BLT<2> B_BLT<1> B_BLT<0> B_BLT_SEL B_PRE_N ++ B_ADDR_DEC<3> B_ADDR_DEC<2> B_ADDR_DEC<1> B_ADDR_DEC<0> B_WR_ONE B_WR_ZERO ++ VDD VSS / RM_IHPSG13_256x32_c2_2P_BLDRV +XB_ISENSE B_SAE B_BLC_SEL B_BLT_SEL net039 net040 VDD VSS / ++ RSC_IHPSG13_DFPQD_MSAFFX2 +XA_ISENSE A_SAE A_BLC_SEL A_BLT_SEL net19 net20 VDD VSS / ++ RSC_IHPSG13_DFPQD_MSAFFX2 +XB_I78 B_RCLK_B_L B_SAE VDD VSS / RSC_IHPSG13_CBUFX2 +XA_I78 A_RCLK_B_L A_SAE VDD VSS / RSC_IHPSG13_CBUFX2 +XB_I83 B_BM_R B_BM_N VDD VSS / RSC_IHPSG13_INVX2 +XB_I49 B_DI_R B_DI_N VDD VSS / RSC_IHPSG13_INVX2 +XA_I83 A_BM_R A_BM_N VDD VSS / RSC_IHPSG13_INVX2 +XA_I49 A_DI_R A_DI_N VDD VSS / RSC_IHPSG13_INVX2 +XB_I51 net039 B_DR_O VDD VSS / RSC_IHPSG13_INVX4 +XA_I51 net19 A_DR_O VDD VSS / RSC_IHPSG13_INVX4 +XA_I69 A_DCLK_L A_DCLK_B_L VDD VSS / RSC_IHPSG13_CINVX2 +XA_I50 A_WCLK_L A_WCLK_B_L VDD VSS / RSC_IHPSG13_CINVX2 +XA_EBUF A_RCLK_L A_RCLK_B_L VDD VSS / RSC_IHPSG13_CINVX2 +XB_EBUF B_RCLK_L B_RCLK_B_L VDD VSS / RSC_IHPSG13_CINVX2 +XB_I50 B_WCLK_L B_WCLK_B_L VDD VSS / RSC_IHPSG13_CINVX2 +XB_I69 B_DCLK_L B_DCLK_B_L VDD VSS / RSC_IHPSG13_CINVX2 +.ENDS +.SUBCKT RM_IHPSG13_256x32_c2_2P_COLDRV13_FILL4C2 VDD VSS +XI0<2> VDD VSS / RSC_IHPSG13_FILLCAP4 +XI0<1> VDD VSS / RSC_IHPSG13_FILLCAP4 +.ENDS + + +.SUBCKT RM_IHPSG13_256x32_c2_2P_ROWDEC7 ADDR_N_I<6> ADDR_N_I<5> ADDR_N_I<4> ADDR_N_I<3> ++ ADDR_N_I<2> ADDR_N_I<1> ADDR_N_I<0> CS_I ECLK_I WL_O<127> WL_O<126> ++ WL_O<125> WL_O<124> WL_O<123> WL_O<122> WL_O<121> WL_O<120> WL_O<119> ++ WL_O<118> WL_O<117> WL_O<116> WL_O<115> WL_O<114> WL_O<113> WL_O<112> ++ WL_O<111> WL_O<110> WL_O<109> WL_O<108> WL_O<107> WL_O<106> WL_O<105> ++ WL_O<104> WL_O<103> WL_O<102> WL_O<101> WL_O<100> WL_O<99> WL_O<98> WL_O<97> ++ WL_O<96> WL_O<95> WL_O<94> WL_O<93> WL_O<92> WL_O<91> WL_O<90> WL_O<89> ++ WL_O<88> WL_O<87> WL_O<86> WL_O<85> WL_O<84> WL_O<83> WL_O<82> WL_O<81> ++ WL_O<80> WL_O<79> WL_O<78> WL_O<77> WL_O<76> WL_O<75> WL_O<74> WL_O<73> ++ WL_O<72> WL_O<71> WL_O<70> WL_O<69> WL_O<68> WL_O<67> WL_O<66> WL_O<65> ++ WL_O<64> WL_O<63> WL_O<62> WL_O<61> WL_O<60> WL_O<59> WL_O<58> WL_O<57> ++ WL_O<56> WL_O<55> WL_O<54> WL_O<53> WL_O<52> WL_O<51> WL_O<50> WL_O<49> ++ WL_O<48> WL_O<47> WL_O<46> WL_O<45> WL_O<44> WL_O<43> WL_O<42> WL_O<41> ++ WL_O<40> WL_O<39> WL_O<38> WL_O<37> WL_O<36> WL_O<35> WL_O<34> WL_O<33> ++ WL_O<32> WL_O<31> WL_O<30> WL_O<29> WL_O<28> WL_O<27> WL_O<26> WL_O<25> ++ WL_O<24> WL_O<23> WL_O<22> WL_O<21> WL_O<20> WL_O<19> WL_O<18> WL_O<17> ++ WL_O<16> WL_O<15> WL_O<14> WL_O<13> WL_O<12> WL_O<11> WL_O<10> WL_O<9> ++ WL_O<8> WL_O<7> WL_O<6> WL_O<5> WL_O<4> WL_O<3> WL_O<2> WL_O<1> WL_O<0> ++ VDD VSS +XSEL<7> ADDR_N_I<3> ADDR_N_I<2> ADDR_N_I<1> ADDR_N_I<0> CS00<7> ECLK_H<7> ++ ECLK_H<8> ECLK_B<7> ECLK_B<8> WL_O<127> WL_O<126> WL_O<125> WL_O<124> ++ WL_O<123> WL_O<122> WL_O<121> WL_O<120> WL_O<119> WL_O<118> WL_O<117> ++ WL_O<116> WL_O<115> WL_O<114> WL_O<113> WL_O<112> VDD VSS / ++ RM_IHPSG13_256x32_c2_2P_DEC04 +XSEL<6> ADDR_N_I<3> ADDR_N_I<2> ADDR_N_I<1> ADDR_N_I<0> CS00<6> ECLK_H<6> ++ ECLK_H<7> ECLK_B<6> ECLK_B<7> WL_O<111> WL_O<110> WL_O<109> WL_O<108> ++ WL_O<107> WL_O<106> WL_O<105> WL_O<104> WL_O<103> WL_O<102> WL_O<101> ++ WL_O<100> WL_O<99> WL_O<98> WL_O<97> WL_O<96> VDD VSS / ++ RM_IHPSG13_256x32_c2_2P_DEC04 +XSEL<5> ADDR_N_I<3> ADDR_N_I<2> ADDR_N_I<1> ADDR_N_I<0> CS00<5> ECLK_H<5> ++ ECLK_H<6> ECLK_B<5> ECLK_B<6> WL_O<95> WL_O<94> WL_O<93> WL_O<92> WL_O<91> ++ WL_O<90> WL_O<89> WL_O<88> WL_O<87> WL_O<86> WL_O<85> WL_O<84> WL_O<83> ++ WL_O<82> WL_O<81> WL_O<80> VDD VSS / RM_IHPSG13_256x32_c2_2P_DEC04 +XSEL<4> ADDR_N_I<3> ADDR_N_I<2> ADDR_N_I<1> ADDR_N_I<0> CS00<4> ECLK_H<4> ++ ECLK_H<5> ECLK_B<4> ECLK_B<5> WL_O<79> WL_O<78> WL_O<77> WL_O<76> WL_O<75> ++ WL_O<74> WL_O<73> WL_O<72> WL_O<71> WL_O<70> WL_O<69> WL_O<68> WL_O<67> ++ WL_O<66> WL_O<65> WL_O<64> VDD VSS / RM_IHPSG13_256x32_c2_2P_DEC04 +XSEL<3> ADDR_N_I<3> ADDR_N_I<2> ADDR_N_I<1> ADDR_N_I<0> CS00<3> ECLK_H<3> ++ ECLK_H<4> ECLK_B<3> ECLK_B<4> WL_O<63> WL_O<62> WL_O<61> WL_O<60> WL_O<59> ++ WL_O<58> WL_O<57> WL_O<56> WL_O<55> WL_O<54> WL_O<53> WL_O<52> WL_O<51> ++ WL_O<50> WL_O<49> WL_O<48> VDD VSS / RM_IHPSG13_256x32_c2_2P_DEC04 +XSEL<2> ADDR_N_I<3> ADDR_N_I<2> ADDR_N_I<1> ADDR_N_I<0> CS00<2> ECLK_H<2> ++ ECLK_H<3> ECLK_B<2> ECLK_B<3> WL_O<47> WL_O<46> WL_O<45> WL_O<44> WL_O<43> ++ WL_O<42> WL_O<41> WL_O<40> WL_O<39> WL_O<38> WL_O<37> WL_O<36> WL_O<35> ++ WL_O<34> WL_O<33> WL_O<32> VDD VSS / RM_IHPSG13_256x32_c2_2P_DEC04 +XSEL<1> ADDR_N_I<3> ADDR_N_I<2> ADDR_N_I<1> ADDR_N_I<0> CS00<1> ECLK_H<1> ++ ECLK_H<2> ECLK_B<1> ECLK_B<2> WL_O<31> WL_O<30> WL_O<29> WL_O<28> WL_O<27> ++ WL_O<26> WL_O<25> WL_O<24> WL_O<23> WL_O<22> WL_O<21> WL_O<20> WL_O<19> ++ WL_O<18> WL_O<17> WL_O<16> VDD VSS / RM_IHPSG13_256x32_c2_2P_DEC04 +XSEL<0> ADDR_N_I<3> ADDR_N_I<2> ADDR_N_I<1> ADDR_N_I<0> CS00<0> ECLK_I ++ ECLK_H<1> ECLK_B<0> ECLK_B<1> WL_O<15> WL_O<14> WL_O<13> WL_O<12> WL_O<11> ++ WL_O<10> WL_O<9> WL_O<8> WL_O<7> WL_O<6> WL_O<5> WL_O<4> WL_O<3> WL_O<2> ++ WL_O<1> WL_O<0> VDD VSS / RM_IHPSG13_256x32_c2_2P_DEC04 +XDEC11<1> ADDR_N_I<5> ADDR_N_I<4> CS04<1> CS00<7> VDD VSS / ++ RM_IHPSG13_256x32_c2_2P_DEC03 +XDEC11<0> ADDR_N_I<5> ADDR_N_I<4> CS04<0> CS00<3> VDD VSS / ++ RM_IHPSG13_256x32_c2_2P_DEC03 +XDEC01<2> ADDR_N_I<7> ADDR_N_I<6> CS_I CS04<1> VDD VSS / ++ RM_IHPSG13_256x32_c2_2P_DEC01 +XDEC01<1> ADDR_N_I<5> ADDR_N_I<4> CS04<1> CS00<5> VDD VSS / ++ RM_IHPSG13_256x32_c2_2P_DEC01 +XDEC01<0> ADDR_N_I<5> ADDR_N_I<4> CS04<0> CS00<1> VDD VSS / ++ RM_IHPSG13_256x32_c2_2P_DEC01 +XL2<66> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<65> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<64> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<63> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<62> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<61> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<60> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<59> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<58> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<57> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<56> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<55> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<54> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<53> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<52> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<51> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<50> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<49> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<48> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<47> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<46> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<45> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<44> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<43> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<42> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<41> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<40> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<39> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<38> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<37> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<36> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<35> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<34> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<33> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<32> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<31> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<30> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<29> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<28> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<27> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<26> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<25> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<24> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<23> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<22> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<21> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<20> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<19> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<18> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<17> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<16> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<15> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<14> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<13> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<12> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<11> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<10> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<9> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<8> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<7> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<6> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<5> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<4> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<3> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<2> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<1> VDD VSS / RSC_IHPSG13_FILLCAP8 +XDEC10<1> ADDR_N_I<5> ADDR_N_I<4> CS04<1> CS00<6> VDD VSS / ++ RM_IHPSG13_256x32_c2_2P_DEC02 +XDEC10<0> ADDR_N_I<5> ADDR_N_I<4> CS04<0> CS00<2> VDD VSS / ++ RM_IHPSG13_256x32_c2_2P_DEC02 +XDEC00<2> ADDR_N_I<7> ADDR_N_I<6> CS_I CS04<0> VDD VSS / ++ RM_IHPSG13_256x32_c2_2P_DEC00 +XDEC00<1> ADDR_N_I<5> ADDR_N_I<4> CS04<1> CS00<4> VDD VSS / ++ RM_IHPSG13_256x32_c2_2P_DEC00 +XDEC00<0> ADDR_N_I<5> ADDR_N_I<4> CS04<0> CS00<0> VDD VSS / ++ RM_IHPSG13_256x32_c2_2P_DEC00 +XI0 ADDR_N_I<7> VDD VSS / RSC_IHPSG13_TIEL +.ENDS +.SUBCKT RM_IHPSG13_256x32_c2_2P_ROWREG7 ACLK_N_I ADDR_I<6> ADDR_I<5> ADDR_I<4> ADDR_I<3> ++ ADDR_I<2> ADDR_I<1> ADDR_I<0> ADDR_N_O<6> ADDR_N_O<5> ADDR_N_O<4> ++ ADDR_N_O<3> ADDR_N_O<2> ADDR_N_O<1> ADDR_N_O<0> BIST_ADDR_I<6> ++ BIST_ADDR_I<5> BIST_ADDR_I<4> BIST_ADDR_I<3> BIST_ADDR_I<2> BIST_ADDR_I<1> ++ BIST_ADDR_I<0> BIST_EN_I VDD VSS +XINV<6> q_int<6> qn_int<6> VDD VSS / RSC_IHPSG13_CINVX2 +XINV<5> q_int<5> qn_int<5> VDD VSS / RSC_IHPSG13_CINVX2 +XINV<4> q_int<4> qn_int<4> VDD VSS / RSC_IHPSG13_CINVX2 +XINV<3> q_int<3> qn_int<3> VDD VSS / RSC_IHPSG13_CINVX2 +XINV<2> q_int<2> qn_int<2> VDD VSS / RSC_IHPSG13_CINVX2 +XINV<1> q_int<1> qn_int<1> VDD VSS / RSC_IHPSG13_CINVX2 +XINV<0> q_int<0> qn_int<0> VDD VSS / RSC_IHPSG13_CINVX2 +XDRV<6> qn_int<6> ADDR_N_O<6> VDD VSS / RSC_IHPSG13_CINVX8 +XDRV<5> qn_int<5> ADDR_N_O<5> VDD VSS / RSC_IHPSG13_CINVX8 +XDRV<4> qn_int<4> ADDR_N_O<4> VDD VSS / RSC_IHPSG13_CINVX8 +XDRV<3> qn_int<3> ADDR_N_O<3> VDD VSS / RSC_IHPSG13_CINVX8 +XDRV<2> qn_int<2> ADDR_N_O<2> VDD VSS / RSC_IHPSG13_CINVX8 +XDRV<1> qn_int<1> ADDR_N_O<1> VDD VSS / RSC_IHPSG13_CINVX8 +XDRV<0> qn_int<0> ADDR_N_O<0> VDD VSS / RSC_IHPSG13_CINVX8 +XDFF<6> BIST_EN_I BIST_ADDR_I<6> ACLK_N_I ADDR_I<6> q_int<6> net2<0> VDD ++ VSS / RSC_IHPSG13_DFNQMX2IX1 +XDFF<5> BIST_EN_I BIST_ADDR_I<5> ACLK_N_I ADDR_I<5> q_int<5> net2<1> VDD ++ VSS / RSC_IHPSG13_DFNQMX2IX1 +XDFF<4> BIST_EN_I BIST_ADDR_I<4> ACLK_N_I ADDR_I<4> q_int<4> net2<2> VDD ++ VSS / RSC_IHPSG13_DFNQMX2IX1 +XDFF<3> BIST_EN_I BIST_ADDR_I<3> ACLK_N_I ADDR_I<3> q_int<3> net2<3> VDD ++ VSS / RSC_IHPSG13_DFNQMX2IX1 +XDFF<2> BIST_EN_I BIST_ADDR_I<2> ACLK_N_I ADDR_I<2> q_int<2> net2<4> VDD ++ VSS / RSC_IHPSG13_DFNQMX2IX1 +XDFF<1> BIST_EN_I BIST_ADDR_I<1> ACLK_N_I ADDR_I<1> q_int<1> net2<5> VDD ++ VSS / RSC_IHPSG13_DFNQMX2IX1 +XDFF<0> BIST_EN_I BIST_ADDR_I<0> ACLK_N_I ADDR_I<0> q_int<0> net2<6> VDD ++ VSS / RSC_IHPSG13_DFNQMX2IX1 +XI11<7> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI11<6> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI11<5> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI11<4> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI11<3> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI11<2> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI11<1> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI11<0> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI12<1> VDD VSS / RSC_IHPSG13_FILLCAP4 +XI12<0> VDD VSS / RSC_IHPSG13_FILLCAP4 +.ENDS + +.SUBCKT RM_IHPSG13_256x32_c2_2P_ROWDEC4 ADDR_N_I<3> ADDR_N_I<2> ADDR_N_I<1> ADDR_N_I<0> ++ CS_I ECLK_I WL_O<15> WL_O<14> WL_O<13> WL_O<12> WL_O<11> WL_O<10> WL_O<9> ++ WL_O<8> WL_O<7> WL_O<6> WL_O<5> WL_O<4> WL_O<3> WL_O<2> WL_O<1> WL_O<0> ++ VDD VSS +XL2<12> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<11> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<10> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<9> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<8> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<7> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<6> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<5> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<4> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<3> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<2> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<1> VDD VSS / RSC_IHPSG13_FILLCAP8 +XSEL ADDR_N_I<3> ADDR_N_I<2> ADDR_N_I<1> ADDR_N_I<0> CS_I ECLK_I ECLK_H<1> ++ ECLK_B<0> ECLK_B<1> WL_O<15> WL_O<14> WL_O<13> WL_O<12> WL_O<11> WL_O<10> ++ WL_O<9> WL_O<8> WL_O<7> WL_O<6> WL_O<5> WL_O<4> WL_O<3> WL_O<2> WL_O<1> ++ WL_O<0> VDD VSS / RM_IHPSG13_256x32_c2_2P_DEC04 +.ENDS +.SUBCKT RM_IHPSG13_256x32_c2_2P_ROWREG4 ACLK_N_I ADDR_I<3> ADDR_I<2> ADDR_I<1> ADDR_I<0> ++ ADDR_N_O<3> ADDR_N_O<2> ADDR_N_O<1> ADDR_N_O<0> BIST_ADDR_I<3> ++ BIST_ADDR_I<2> BIST_ADDR_I<1> BIST_ADDR_I<0> BIST_EN_I VDD VSS +XINV<3> q_int<3> qn_int<3> VDD VSS / RSC_IHPSG13_CINVX2 +XINV<2> q_int<2> qn_int<2> VDD VSS / RSC_IHPSG13_CINVX2 +XINV<1> q_int<1> qn_int<1> VDD VSS / RSC_IHPSG13_CINVX2 +XINV<0> q_int<0> qn_int<0> VDD VSS / RSC_IHPSG13_CINVX2 +XDRV<3> qn_int<3> ADDR_N_O<3> VDD VSS / RSC_IHPSG13_CINVX8 +XDRV<2> qn_int<2> ADDR_N_O<2> VDD VSS / RSC_IHPSG13_CINVX8 +XDRV<1> qn_int<1> ADDR_N_O<1> VDD VSS / RSC_IHPSG13_CINVX8 +XDRV<0> qn_int<0> ADDR_N_O<0> VDD VSS / RSC_IHPSG13_CINVX8 +XDFF<3> BIST_EN_I BIST_ADDR_I<3> ACLK_N_I ADDR_I<3> q_int<3> net7<0> VDD ++ VSS / RSC_IHPSG13_DFNQMX2IX1 +XDFF<2> BIST_EN_I BIST_ADDR_I<2> ACLK_N_I ADDR_I<2> q_int<2> net7<1> VDD ++ VSS / RSC_IHPSG13_DFNQMX2IX1 +XDFF<1> BIST_EN_I BIST_ADDR_I<1> ACLK_N_I ADDR_I<1> q_int<1> net7<2> VDD ++ VSS / RSC_IHPSG13_DFNQMX2IX1 +XDFF<0> BIST_EN_I BIST_ADDR_I<0> ACLK_N_I ADDR_I<0> q_int<0> net7<3> VDD ++ VSS / RSC_IHPSG13_DFNQMX2IX1 +XI11<20> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI11<19> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI11<18> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI11<17> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI11<16> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI11<15> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI11<14> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI11<13> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI11<12> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI11<11> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI11<10> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI11<9> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI11<8> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI11<7> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI11<6> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI11<5> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI11<4> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI11<3> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI11<2> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI11<1> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI12<4> VDD VSS / RSC_IHPSG13_FILLCAP4 +XI12<3> VDD VSS / RSC_IHPSG13_FILLCAP4 +XI12<2> VDD VSS / RSC_IHPSG13_FILLCAP4 +XI12<1> VDD VSS / RSC_IHPSG13_FILLCAP4 +XI12<0> VDD VSS / RSC_IHPSG13_FILLCAP4 +.ENDS + + +.SUBCKT RM_IHPSG13_256x32_c2_1P_BITKIT_TAP BLC BLT NW PW VDD VSS +.ENDS +.SUBCKT RM_IHPSG13_256x32_c2_1P_BITKIT_16x2_TAP A_BLC<1> A_BLC<0> A_BLT<1> A_BLT<0> ++ VDD_CORE VSS +XITAP<1> A_BLC<1> A_BLT<1> VDD_CORE VSS VDD_CORE VSS ++ / RM_IHPSG13_256x32_c2_1P_BITKIT_TAP +XITAP<0> A_BLC<0> A_BLT<0> VDD_CORE VSS VDD_CORE VSS ++ / RM_IHPSG13_256x32_c2_1P_BITKIT_TAP +XIEDGEBP_COL1<1> BLC<1> BLT<1> VDD_CORE VSS VDD_CORE ++ VSS / RM_IHPSG13_256x32_c2_1P_BITKIT_EDGE_TB +XIEDGEBP_COL1<0> BLC<1> BLT<1> VDD_CORE VSS VDD_CORE ++ VSS / RM_IHPSG13_256x32_c2_1P_BITKIT_EDGE_TB +XIEDGEBP_COL2<1> BLC<0> BLT<0> VDD_CORE VSS VDD_CORE ++ VSS / RM_IHPSG13_256x32_c2_1P_BITKIT_EDGE_TB +XIEDGEBP_COL2<0> BLC<0> BLT<0> VDD_CORE VSS VDD_CORE ++ VSS / RM_IHPSG13_256x32_c2_1P_BITKIT_EDGE_TB +.ENDS +.SUBCKT RM_IHPSG13_256x32_c2_1P_BITKIT_16x2_TAP_LR VDD_CORE VSS +XCORNER<1> VDD_CORE VSS VDD_CORE VSS / ++ RM_IHPSG13_256x32_c2_1P_BITKIT_CORNER +XCORNER<0> VDD_CORE VSS VDD_CORE VSS / ++ RM_IHPSG13_256x32_c2_1P_BITKIT_CORNER +XTAP_BORDER VDD_CORE VSS VDD_CORE VSS / ++ RM_IHPSG13_256x32_c2_1P_BITKIT_TAP_LR +.ENDS +.SUBCKT RM_IHPSG13_256x32_c2_1P_DEC03 ADDR<1> ADDR<0> CS CS_OUT VDD VSS +XDECINV net1 CS_OUT VDD VSS / RSC_IHPSG13_INVX4 +XI0 VDD VSS / RSC_IHPSG13_FILLCAP4 +XDEC ADDR<1> ADDR<0> CS net1 VDD VSS / RSC_IHPSG13_NAND3X2 +.ENDS +.SUBCKT RM_IHPSG13_256x32_c2_1P_DEC02 ADDR<1> ADDR<0> CS CS_OUT VDD VSS +XDECINV net1 CS_OUT VDD VSS / RSC_IHPSG13_INVX4 +XDEC ADDR<1> NADDR<0> CS net1 VDD VSS / RSC_IHPSG13_NAND3X2 +XI2 VDD VSS / RSC_IHPSG13_FILLCAP4 +XADDRINV ADDR<0> NADDR<0> VDD VSS / RSC_IHPSG13_INVX2 +.ENDS +.SUBCKT RM_IHPSG13_256x32_c2_1P_ROWDEC8 ADDR_N_I<7> ADDR_N_I<6> ADDR_N_I<5> ADDR_N_I<4> ++ ADDR_N_I<3> ADDR_N_I<2> ADDR_N_I<1> ADDR_N_I<0> CS_I ECLK_I WL_O<255> ++ WL_O<254> WL_O<253> WL_O<252> WL_O<251> WL_O<250> WL_O<249> WL_O<248> ++ WL_O<247> WL_O<246> WL_O<245> WL_O<244> WL_O<243> WL_O<242> WL_O<241> ++ WL_O<240> WL_O<239> WL_O<238> WL_O<237> WL_O<236> WL_O<235> WL_O<234> ++ WL_O<233> WL_O<232> WL_O<231> WL_O<230> WL_O<229> WL_O<228> WL_O<227> ++ WL_O<226> WL_O<225> WL_O<224> WL_O<223> WL_O<222> WL_O<221> WL_O<220> ++ WL_O<219> WL_O<218> WL_O<217> WL_O<216> WL_O<215> WL_O<214> WL_O<213> ++ WL_O<212> WL_O<211> WL_O<210> WL_O<209> WL_O<208> WL_O<207> WL_O<206> ++ WL_O<205> WL_O<204> WL_O<203> WL_O<202> WL_O<201> WL_O<200> WL_O<199> ++ WL_O<198> WL_O<197> WL_O<196> WL_O<195> WL_O<194> WL_O<193> WL_O<192> ++ WL_O<191> WL_O<190> WL_O<189> WL_O<188> WL_O<187> WL_O<186> WL_O<185> ++ WL_O<184> WL_O<183> WL_O<182> WL_O<181> WL_O<180> WL_O<179> WL_O<178> ++ WL_O<177> WL_O<176> WL_O<175> WL_O<174> WL_O<173> WL_O<172> WL_O<171> ++ WL_O<170> WL_O<169> WL_O<168> WL_O<167> WL_O<166> WL_O<165> WL_O<164> ++ WL_O<163> WL_O<162> WL_O<161> WL_O<160> WL_O<159> WL_O<158> WL_O<157> ++ WL_O<156> WL_O<155> WL_O<154> WL_O<153> WL_O<152> WL_O<151> WL_O<150> ++ WL_O<149> WL_O<148> WL_O<147> WL_O<146> WL_O<145> WL_O<144> WL_O<143> ++ WL_O<142> WL_O<141> WL_O<140> WL_O<139> WL_O<138> WL_O<137> WL_O<136> ++ WL_O<135> WL_O<134> WL_O<133> WL_O<132> WL_O<131> WL_O<130> WL_O<129> ++ WL_O<128> WL_O<127> WL_O<126> WL_O<125> WL_O<124> WL_O<123> WL_O<122> ++ WL_O<121> WL_O<120> WL_O<119> WL_O<118> WL_O<117> WL_O<116> WL_O<115> ++ WL_O<114> WL_O<113> WL_O<112> WL_O<111> WL_O<110> WL_O<109> WL_O<108> ++ WL_O<107> WL_O<106> WL_O<105> WL_O<104> WL_O<103> WL_O<102> WL_O<101> ++ WL_O<100> WL_O<99> WL_O<98> WL_O<97> WL_O<96> WL_O<95> WL_O<94> WL_O<93> ++ WL_O<92> WL_O<91> WL_O<90> WL_O<89> WL_O<88> WL_O<87> WL_O<86> WL_O<85> ++ WL_O<84> WL_O<83> WL_O<82> WL_O<81> WL_O<80> WL_O<79> WL_O<78> WL_O<77> ++ WL_O<76> WL_O<75> WL_O<74> WL_O<73> WL_O<72> WL_O<71> WL_O<70> WL_O<69> ++ WL_O<68> WL_O<67> WL_O<66> WL_O<65> WL_O<64> WL_O<63> WL_O<62> WL_O<61> ++ WL_O<60> WL_O<59> WL_O<58> WL_O<57> WL_O<56> WL_O<55> WL_O<54> WL_O<53> ++ WL_O<52> WL_O<51> WL_O<50> WL_O<49> WL_O<48> WL_O<47> WL_O<46> WL_O<45> ++ WL_O<44> WL_O<43> WL_O<42> WL_O<41> WL_O<40> WL_O<39> WL_O<38> WL_O<37> ++ WL_O<36> WL_O<35> WL_O<34> WL_O<33> WL_O<32> WL_O<31> WL_O<30> WL_O<29> ++ WL_O<28> WL_O<27> WL_O<26> WL_O<25> WL_O<24> WL_O<23> WL_O<22> WL_O<21> ++ WL_O<20> WL_O<19> WL_O<18> WL_O<17> WL_O<16> WL_O<15> WL_O<14> WL_O<13> ++ WL_O<12> WL_O<11> WL_O<10> WL_O<9> WL_O<8> WL_O<7> WL_O<6> WL_O<5> WL_O<4> ++ WL_O<3> WL_O<2> WL_O<1> WL_O<0> VDD VSS +XDEC11<4> ADDR_N_I<7> ADDR_N_I<6> CS_I CS04<3> VDD VSS / ++ RM_IHPSG13_256x32_c2_1P_DEC03 +XDEC11<3> ADDR_N_I<5> ADDR_N_I<4> CS04<3> CS00<15> VDD VSS / ++ RM_IHPSG13_256x32_c2_1P_DEC03 +XDEC11<2> ADDR_N_I<5> ADDR_N_I<4> CS04<2> CS00<11> VDD VSS / ++ RM_IHPSG13_256x32_c2_1P_DEC03 +XDEC11<1> ADDR_N_I<5> ADDR_N_I<4> CS04<1> CS00<7> VDD VSS / ++ RM_IHPSG13_256x32_c2_1P_DEC03 +XDEC11<0> ADDR_N_I<5> ADDR_N_I<4> CS04<0> CS00<3> VDD VSS / ++ RM_IHPSG13_256x32_c2_1P_DEC03 +XL2<88> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<87> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<86> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<85> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<84> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<83> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<82> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<81> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<80> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<79> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<78> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<77> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<76> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<75> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<74> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<73> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<72> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<71> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<70> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<69> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<68> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<67> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<66> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<65> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<64> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<63> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<62> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<61> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<60> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<59> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<58> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<57> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<56> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<55> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<54> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<53> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<52> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<51> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<50> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<49> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<48> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<47> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<46> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<45> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<44> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<43> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<42> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<41> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<40> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<39> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<38> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<37> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<36> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<35> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<34> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<33> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<32> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<31> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<30> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<29> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<28> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<27> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<26> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<25> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<24> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<23> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<22> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<21> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<20> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<19> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<18> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<17> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<16> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<15> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<14> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<13> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<12> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<11> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<10> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<9> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<8> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<7> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<6> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<5> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<4> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<3> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<2> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<1> VDD VSS / RSC_IHPSG13_FILLCAP8 +XDEC10<4> ADDR_N_I<7> ADDR_N_I<6> CS_I CS04<2> VDD VSS / ++ RM_IHPSG13_256x32_c2_1P_DEC02 +XDEC10<3> ADDR_N_I<5> ADDR_N_I<4> CS04<3> CS00<14> VDD VSS / ++ RM_IHPSG13_256x32_c2_1P_DEC02 +XDEC10<2> ADDR_N_I<5> ADDR_N_I<4> CS04<2> CS00<10> VDD VSS / ++ RM_IHPSG13_256x32_c2_1P_DEC02 +XDEC10<1> ADDR_N_I<5> ADDR_N_I<4> CS04<1> CS00<6> VDD VSS / ++ RM_IHPSG13_256x32_c2_1P_DEC02 +XDEC10<0> ADDR_N_I<5> ADDR_N_I<4> CS04<0> CS00<2> VDD VSS / ++ RM_IHPSG13_256x32_c2_1P_DEC02 +XDEC00<4> ADDR_N_I<7> ADDR_N_I<6> CS_I CS04<0> VDD VSS / ++ RM_IHPSG13_256x32_c2_1P_DEC00 +XDEC00<3> ADDR_N_I<5> ADDR_N_I<4> CS04<3> CS00<12> VDD VSS / ++ RM_IHPSG13_256x32_c2_1P_DEC00 +XDEC00<2> ADDR_N_I<5> ADDR_N_I<4> CS04<2> CS00<8> VDD VSS / ++ RM_IHPSG13_256x32_c2_1P_DEC00 +XDEC00<1> ADDR_N_I<5> ADDR_N_I<4> CS04<1> CS00<4> VDD VSS / ++ RM_IHPSG13_256x32_c2_1P_DEC00 +XDEC00<0> ADDR_N_I<5> ADDR_N_I<4> CS04<0> CS00<0> VDD VSS / ++ RM_IHPSG13_256x32_c2_1P_DEC00 +XSEL<15> ADDR_N_I<3> ADDR_N_I<2> ADDR_N_I<1> ADDR_N_I<0> CS00<15> ECLK_H<15> ++ ECLK_H<16> ECLK_B<15> ECLK_B<16> WL_O<255> WL_O<254> WL_O<253> WL_O<252> ++ WL_O<251> WL_O<250> WL_O<249> WL_O<248> WL_O<247> WL_O<246> WL_O<245> ++ WL_O<244> WL_O<243> WL_O<242> WL_O<241> WL_O<240> VDD VSS / ++ RM_IHPSG13_256x32_c2_1P_DEC04 +XSEL<14> ADDR_N_I<3> ADDR_N_I<2> ADDR_N_I<1> ADDR_N_I<0> CS00<14> ECLK_H<14> ++ ECLK_H<15> ECLK_B<14> ECLK_B<15> WL_O<239> WL_O<238> WL_O<237> WL_O<236> ++ WL_O<235> WL_O<234> WL_O<233> WL_O<232> WL_O<231> WL_O<230> WL_O<229> ++ WL_O<228> WL_O<227> WL_O<226> WL_O<225> WL_O<224> VDD VSS / ++ RM_IHPSG13_256x32_c2_1P_DEC04 +XSEL<13> ADDR_N_I<3> ADDR_N_I<2> ADDR_N_I<1> ADDR_N_I<0> CS00<13> ECLK_H<13> ++ ECLK_H<14> ECLK_B<13> ECLK_B<14> WL_O<223> WL_O<222> WL_O<221> WL_O<220> ++ WL_O<219> WL_O<218> WL_O<217> WL_O<216> WL_O<215> WL_O<214> WL_O<213> ++ WL_O<212> WL_O<211> WL_O<210> WL_O<209> WL_O<208> VDD VSS / ++ RM_IHPSG13_256x32_c2_1P_DEC04 +XSEL<12> ADDR_N_I<3> ADDR_N_I<2> ADDR_N_I<1> ADDR_N_I<0> CS00<12> ECLK_H<12> ++ ECLK_H<13> ECLK_B<12> ECLK_B<13> WL_O<207> WL_O<206> WL_O<205> WL_O<204> ++ WL_O<203> WL_O<202> WL_O<201> WL_O<200> WL_O<199> WL_O<198> WL_O<197> ++ WL_O<196> WL_O<195> WL_O<194> WL_O<193> WL_O<192> VDD VSS / ++ RM_IHPSG13_256x32_c2_1P_DEC04 +XSEL<11> ADDR_N_I<3> ADDR_N_I<2> ADDR_N_I<1> ADDR_N_I<0> CS00<11> ECLK_H<11> ++ ECLK_H<12> ECLK_B<11> ECLK_B<12> WL_O<191> WL_O<190> WL_O<189> WL_O<188> ++ WL_O<187> WL_O<186> WL_O<185> WL_O<184> WL_O<183> WL_O<182> WL_O<181> ++ WL_O<180> WL_O<179> WL_O<178> WL_O<177> WL_O<176> VDD VSS / ++ RM_IHPSG13_256x32_c2_1P_DEC04 +XSEL<10> ADDR_N_I<3> ADDR_N_I<2> ADDR_N_I<1> ADDR_N_I<0> CS00<10> ECLK_H<10> ++ ECLK_H<11> ECLK_B<10> ECLK_B<11> WL_O<175> WL_O<174> WL_O<173> WL_O<172> ++ WL_O<171> WL_O<170> WL_O<169> WL_O<168> WL_O<167> WL_O<166> WL_O<165> ++ WL_O<164> WL_O<163> WL_O<162> WL_O<161> WL_O<160> VDD VSS / ++ RM_IHPSG13_256x32_c2_1P_DEC04 +XSEL<9> ADDR_N_I<3> ADDR_N_I<2> ADDR_N_I<1> ADDR_N_I<0> CS00<9> ECLK_H<9> ++ ECLK_H<10> ECLK_B<9> ECLK_B<10> WL_O<159> WL_O<158> WL_O<157> WL_O<156> ++ WL_O<155> WL_O<154> WL_O<153> WL_O<152> WL_O<151> WL_O<150> WL_O<149> ++ WL_O<148> WL_O<147> WL_O<146> WL_O<145> WL_O<144> VDD VSS / ++ RM_IHPSG13_256x32_c2_1P_DEC04 +XSEL<8> ADDR_N_I<3> ADDR_N_I<2> ADDR_N_I<1> ADDR_N_I<0> CS00<8> ECLK_H<8> ++ ECLK_H<9> ECLK_B<8> ECLK_B<9> WL_O<143> WL_O<142> WL_O<141> WL_O<140> ++ WL_O<139> WL_O<138> WL_O<137> WL_O<136> WL_O<135> WL_O<134> WL_O<133> ++ WL_O<132> WL_O<131> WL_O<130> WL_O<129> WL_O<128> VDD VSS / ++ RM_IHPSG13_256x32_c2_1P_DEC04 +XSEL<7> ADDR_N_I<3> ADDR_N_I<2> ADDR_N_I<1> ADDR_N_I<0> CS00<7> ECLK_H<7> ++ ECLK_H<8> ECLK_B<7> ECLK_B<8> WL_O<127> WL_O<126> WL_O<125> WL_O<124> ++ WL_O<123> WL_O<122> WL_O<121> WL_O<120> WL_O<119> WL_O<118> WL_O<117> ++ WL_O<116> WL_O<115> WL_O<114> WL_O<113> WL_O<112> VDD VSS / ++ RM_IHPSG13_256x32_c2_1P_DEC04 +XSEL<6> ADDR_N_I<3> ADDR_N_I<2> ADDR_N_I<1> ADDR_N_I<0> CS00<6> ECLK_H<6> ++ ECLK_H<7> ECLK_B<6> ECLK_B<7> WL_O<111> WL_O<110> WL_O<109> WL_O<108> ++ WL_O<107> WL_O<106> WL_O<105> WL_O<104> WL_O<103> WL_O<102> WL_O<101> ++ WL_O<100> WL_O<99> WL_O<98> WL_O<97> WL_O<96> VDD VSS / ++ RM_IHPSG13_256x32_c2_1P_DEC04 +XSEL<5> ADDR_N_I<3> ADDR_N_I<2> ADDR_N_I<1> ADDR_N_I<0> CS00<5> ECLK_H<5> ++ ECLK_H<6> ECLK_B<5> ECLK_B<6> WL_O<95> WL_O<94> WL_O<93> WL_O<92> WL_O<91> ++ WL_O<90> WL_O<89> WL_O<88> WL_O<87> WL_O<86> WL_O<85> WL_O<84> WL_O<83> ++ WL_O<82> WL_O<81> WL_O<80> VDD VSS / RM_IHPSG13_256x32_c2_1P_DEC04 +XSEL<4> ADDR_N_I<3> ADDR_N_I<2> ADDR_N_I<1> ADDR_N_I<0> CS00<4> ECLK_H<4> ++ ECLK_H<5> ECLK_B<4> ECLK_B<5> WL_O<79> WL_O<78> WL_O<77> WL_O<76> WL_O<75> ++ WL_O<74> WL_O<73> WL_O<72> WL_O<71> WL_O<70> WL_O<69> WL_O<68> WL_O<67> ++ WL_O<66> WL_O<65> WL_O<64> VDD VSS / RM_IHPSG13_256x32_c2_1P_DEC04 +XSEL<3> ADDR_N_I<3> ADDR_N_I<2> ADDR_N_I<1> ADDR_N_I<0> CS00<3> ECLK_H<3> ++ ECLK_H<4> ECLK_B<3> ECLK_B<4> WL_O<63> WL_O<62> WL_O<61> WL_O<60> WL_O<59> ++ WL_O<58> WL_O<57> WL_O<56> WL_O<55> WL_O<54> WL_O<53> WL_O<52> WL_O<51> ++ WL_O<50> WL_O<49> WL_O<48> VDD VSS / RM_IHPSG13_256x32_c2_1P_DEC04 +XSEL<2> ADDR_N_I<3> ADDR_N_I<2> ADDR_N_I<1> ADDR_N_I<0> CS00<2> ECLK_H<2> ++ ECLK_H<3> ECLK_B<2> ECLK_B<3> WL_O<47> WL_O<46> WL_O<45> WL_O<44> WL_O<43> ++ WL_O<42> WL_O<41> WL_O<40> WL_O<39> WL_O<38> WL_O<37> WL_O<36> WL_O<35> ++ WL_O<34> WL_O<33> WL_O<32> VDD VSS / RM_IHPSG13_256x32_c2_1P_DEC04 +XSEL<1> ADDR_N_I<3> ADDR_N_I<2> ADDR_N_I<1> ADDR_N_I<0> CS00<1> ECLK_H<1> ++ ECLK_H<2> ECLK_B<1> ECLK_B<2> WL_O<31> WL_O<30> WL_O<29> WL_O<28> WL_O<27> ++ WL_O<26> WL_O<25> WL_O<24> WL_O<23> WL_O<22> WL_O<21> WL_O<20> WL_O<19> ++ WL_O<18> WL_O<17> WL_O<16> VDD VSS / RM_IHPSG13_256x32_c2_1P_DEC04 +XSEL<0> ADDR_N_I<3> ADDR_N_I<2> ADDR_N_I<1> ADDR_N_I<0> CS00<0> ECLK_I ++ ECLK_H<1> ECLK_B<0> ECLK_B<1> WL_O<15> WL_O<14> WL_O<13> WL_O<12> WL_O<11> ++ WL_O<10> WL_O<9> WL_O<8> WL_O<7> WL_O<6> WL_O<5> WL_O<4> WL_O<3> WL_O<2> ++ WL_O<1> WL_O<0> VDD VSS / RM_IHPSG13_256x32_c2_1P_DEC04 +XDEC01<4> ADDR_N_I<7> ADDR_N_I<6> CS_I CS04<1> VDD VSS / ++ RM_IHPSG13_256x32_c2_1P_DEC01 +XDEC01<3> ADDR_N_I<5> ADDR_N_I<4> CS04<3> CS00<13> VDD VSS / ++ RM_IHPSG13_256x32_c2_1P_DEC01 +XDEC01<2> ADDR_N_I<5> ADDR_N_I<4> CS04<2> CS00<9> VDD VSS / ++ RM_IHPSG13_256x32_c2_1P_DEC01 +XDEC01<1> ADDR_N_I<5> ADDR_N_I<4> CS04<1> CS00<5> VDD VSS / ++ RM_IHPSG13_256x32_c2_1P_DEC01 +XDEC01<0> ADDR_N_I<5> ADDR_N_I<4> CS04<0> CS00<1> VDD VSS / ++ RM_IHPSG13_256x32_c2_1P_DEC01 +.ENDS +.SUBCKT RM_IHPSG13_256x32_c2_1P_ROWREG8 ACLK_N_I ADDR_I<7> ADDR_I<6> ADDR_I<5> ADDR_I<4> ++ ADDR_I<3> ADDR_I<2> ADDR_I<1> ADDR_I<0> ADDR_N_O<7> ADDR_N_O<6> ADDR_N_O<5> ++ ADDR_N_O<4> ADDR_N_O<3> ADDR_N_O<2> ADDR_N_O<1> ADDR_N_O<0> BIST_ADDR_I<7> ++ BIST_ADDR_I<6> BIST_ADDR_I<5> BIST_ADDR_I<4> BIST_ADDR_I<3> BIST_ADDR_I<2> ++ BIST_ADDR_I<1> BIST_ADDR_I<0> BIST_EN_I VDD VSS +XINV<7> q_int<7> qn_int<7> VDD VSS / RSC_IHPSG13_CINVX2 +XINV<6> q_int<6> qn_int<6> VDD VSS / RSC_IHPSG13_CINVX2 +XINV<5> q_int<5> qn_int<5> VDD VSS / RSC_IHPSG13_CINVX2 +XINV<4> q_int<4> qn_int<4> VDD VSS / RSC_IHPSG13_CINVX2 +XINV<3> q_int<3> qn_int<3> VDD VSS / RSC_IHPSG13_CINVX2 +XINV<2> q_int<2> qn_int<2> VDD VSS / RSC_IHPSG13_CINVX2 +XINV<1> q_int<1> qn_int<1> VDD VSS / RSC_IHPSG13_CINVX2 +XINV<0> q_int<0> qn_int<0> VDD VSS / RSC_IHPSG13_CINVX2 +XDRV<7> qn_int<7> ADDR_N_O<7> VDD VSS / RSC_IHPSG13_CINVX8 +XDRV<6> qn_int<6> ADDR_N_O<6> VDD VSS / RSC_IHPSG13_CINVX8 +XDRV<5> qn_int<5> ADDR_N_O<5> VDD VSS / RSC_IHPSG13_CINVX8 +XDRV<4> qn_int<4> ADDR_N_O<4> VDD VSS / RSC_IHPSG13_CINVX8 +XDRV<3> qn_int<3> ADDR_N_O<3> VDD VSS / RSC_IHPSG13_CINVX8 +XDRV<2> qn_int<2> ADDR_N_O<2> VDD VSS / RSC_IHPSG13_CINVX8 +XDRV<1> qn_int<1> ADDR_N_O<1> VDD VSS / RSC_IHPSG13_CINVX8 +XDRV<0> qn_int<0> ADDR_N_O<0> VDD VSS / RSC_IHPSG13_CINVX8 +XDFF<7> BIST_EN_I BIST_ADDR_I<7> ACLK_N_I ADDR_I<7> q_int<7> net2<0> VDD ++ VSS / RSC_IHPSG13_DFNQMX2IX1 +XDFF<6> BIST_EN_I BIST_ADDR_I<6> ACLK_N_I ADDR_I<6> q_int<6> net2<1> VDD ++ VSS / RSC_IHPSG13_DFNQMX2IX1 +XDFF<5> BIST_EN_I BIST_ADDR_I<5> ACLK_N_I ADDR_I<5> q_int<5> net2<2> VDD ++ VSS / RSC_IHPSG13_DFNQMX2IX1 +XDFF<4> BIST_EN_I BIST_ADDR_I<4> ACLK_N_I ADDR_I<4> q_int<4> net2<3> VDD ++ VSS / RSC_IHPSG13_DFNQMX2IX1 +XDFF<3> BIST_EN_I BIST_ADDR_I<3> ACLK_N_I ADDR_I<3> q_int<3> net2<4> VDD ++ VSS / RSC_IHPSG13_DFNQMX2IX1 +XDFF<2> BIST_EN_I BIST_ADDR_I<2> ACLK_N_I ADDR_I<2> q_int<2> net2<5> VDD ++ VSS / RSC_IHPSG13_DFNQMX2IX1 +XDFF<1> BIST_EN_I BIST_ADDR_I<1> ACLK_N_I ADDR_I<1> q_int<1> net2<6> VDD ++ VSS / RSC_IHPSG13_DFNQMX2IX1 +XDFF<0> BIST_EN_I BIST_ADDR_I<0> ACLK_N_I ADDR_I<0> q_int<0> net2<7> VDD ++ VSS / RSC_IHPSG13_DFNQMX2IX1 +XI11<4> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI11<3> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI11<2> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI11<1> VDD VSS / RSC_IHPSG13_FILLCAP8 +.ENDS + +.SUBCKT RM_IHPSG13_256x32_c2_1P_ROWDEC9 ADDR_N_I<8> ADDR_N_I<7> ADDR_N_I<6> ADDR_N_I<5> ++ ADDR_N_I<4> ADDR_N_I<3> ADDR_N_I<2> ADDR_N_I<1> ADDR_N_I<0> CS_I ECLK_I ++ WL_O<511> WL_O<510> WL_O<509> WL_O<508> WL_O<507> WL_O<506> WL_O<505> ++ WL_O<504> WL_O<503> WL_O<502> WL_O<501> WL_O<500> WL_O<499> WL_O<498> ++ WL_O<497> WL_O<496> WL_O<495> WL_O<494> WL_O<493> WL_O<492> WL_O<491> ++ WL_O<490> WL_O<489> WL_O<488> WL_O<487> WL_O<486> WL_O<485> WL_O<484> ++ WL_O<483> WL_O<482> WL_O<481> WL_O<480> WL_O<479> WL_O<478> WL_O<477> ++ WL_O<476> WL_O<475> WL_O<474> WL_O<473> WL_O<472> WL_O<471> WL_O<470> ++ WL_O<469> WL_O<468> WL_O<467> WL_O<466> WL_O<465> WL_O<464> WL_O<463> ++ WL_O<462> WL_O<461> WL_O<460> WL_O<459> WL_O<458> WL_O<457> WL_O<456> ++ WL_O<455> WL_O<454> WL_O<453> WL_O<452> WL_O<451> WL_O<450> WL_O<449> ++ WL_O<448> WL_O<447> WL_O<446> WL_O<445> WL_O<444> WL_O<443> WL_O<442> ++ WL_O<441> WL_O<440> WL_O<439> WL_O<438> WL_O<437> WL_O<436> WL_O<435> ++ WL_O<434> WL_O<433> WL_O<432> WL_O<431> WL_O<430> WL_O<429> WL_O<428> ++ WL_O<427> WL_O<426> WL_O<425> WL_O<424> WL_O<423> WL_O<422> WL_O<421> ++ WL_O<420> WL_O<419> WL_O<418> WL_O<417> WL_O<416> WL_O<415> WL_O<414> ++ WL_O<413> WL_O<412> WL_O<411> WL_O<410> WL_O<409> WL_O<408> WL_O<407> ++ WL_O<406> WL_O<405> WL_O<404> WL_O<403> WL_O<402> WL_O<401> WL_O<400> ++ WL_O<399> WL_O<398> WL_O<397> WL_O<396> WL_O<395> WL_O<394> WL_O<393> ++ WL_O<392> WL_O<391> WL_O<390> WL_O<389> WL_O<388> WL_O<387> WL_O<386> ++ WL_O<385> WL_O<384> WL_O<383> WL_O<382> WL_O<381> WL_O<380> WL_O<379> ++ WL_O<378> WL_O<377> WL_O<376> WL_O<375> WL_O<374> WL_O<373> WL_O<372> ++ WL_O<371> WL_O<370> WL_O<369> WL_O<368> WL_O<367> WL_O<366> WL_O<365> ++ WL_O<364> WL_O<363> WL_O<362> WL_O<361> WL_O<360> WL_O<359> WL_O<358> ++ WL_O<357> WL_O<356> WL_O<355> WL_O<354> WL_O<353> WL_O<352> WL_O<351> ++ WL_O<350> WL_O<349> WL_O<348> WL_O<347> WL_O<346> WL_O<345> WL_O<344> ++ WL_O<343> WL_O<342> WL_O<341> WL_O<340> WL_O<339> WL_O<338> WL_O<337> ++ WL_O<336> WL_O<335> WL_O<334> WL_O<333> WL_O<332> WL_O<331> WL_O<330> ++ WL_O<329> WL_O<328> WL_O<327> WL_O<326> WL_O<325> WL_O<324> WL_O<323> ++ WL_O<322> WL_O<321> WL_O<320> WL_O<319> WL_O<318> WL_O<317> WL_O<316> ++ WL_O<315> WL_O<314> WL_O<313> WL_O<312> WL_O<311> WL_O<310> WL_O<309> ++ WL_O<308> WL_O<307> WL_O<306> WL_O<305> WL_O<304> WL_O<303> WL_O<302> ++ WL_O<301> WL_O<300> WL_O<299> WL_O<298> WL_O<297> WL_O<296> WL_O<295> ++ WL_O<294> WL_O<293> WL_O<292> WL_O<291> WL_O<290> WL_O<289> WL_O<288> ++ WL_O<287> WL_O<286> WL_O<285> WL_O<284> WL_O<283> WL_O<282> WL_O<281> ++ WL_O<280> WL_O<279> WL_O<278> WL_O<277> WL_O<276> WL_O<275> WL_O<274> ++ WL_O<273> WL_O<272> WL_O<271> WL_O<270> WL_O<269> WL_O<268> WL_O<267> ++ WL_O<266> WL_O<265> WL_O<264> WL_O<263> WL_O<262> WL_O<261> WL_O<260> ++ WL_O<259> WL_O<258> WL_O<257> WL_O<256> WL_O<255> WL_O<254> WL_O<253> ++ WL_O<252> WL_O<251> WL_O<250> WL_O<249> WL_O<248> WL_O<247> WL_O<246> ++ WL_O<245> WL_O<244> WL_O<243> WL_O<242> WL_O<241> WL_O<240> WL_O<239> ++ WL_O<238> WL_O<237> WL_O<236> WL_O<235> WL_O<234> WL_O<233> WL_O<232> ++ WL_O<231> WL_O<230> WL_O<229> WL_O<228> WL_O<227> WL_O<226> WL_O<225> ++ WL_O<224> WL_O<223> WL_O<222> WL_O<221> WL_O<220> WL_O<219> WL_O<218> ++ WL_O<217> WL_O<216> WL_O<215> WL_O<214> WL_O<213> WL_O<212> WL_O<211> ++ WL_O<210> WL_O<209> WL_O<208> WL_O<207> WL_O<206> WL_O<205> WL_O<204> ++ WL_O<203> WL_O<202> WL_O<201> WL_O<200> WL_O<199> WL_O<198> WL_O<197> ++ WL_O<196> WL_O<195> WL_O<194> WL_O<193> WL_O<192> WL_O<191> WL_O<190> ++ WL_O<189> WL_O<188> WL_O<187> WL_O<186> WL_O<185> WL_O<184> WL_O<183> ++ WL_O<182> WL_O<181> WL_O<180> WL_O<179> WL_O<178> WL_O<177> WL_O<176> ++ WL_O<175> WL_O<174> WL_O<173> WL_O<172> WL_O<171> WL_O<170> WL_O<169> ++ WL_O<168> WL_O<167> WL_O<166> WL_O<165> WL_O<164> WL_O<163> WL_O<162> ++ WL_O<161> WL_O<160> WL_O<159> WL_O<158> WL_O<157> WL_O<156> WL_O<155> ++ WL_O<154> WL_O<153> WL_O<152> WL_O<151> WL_O<150> WL_O<149> WL_O<148> ++ WL_O<147> WL_O<146> WL_O<145> WL_O<144> WL_O<143> WL_O<142> WL_O<141> ++ WL_O<140> WL_O<139> WL_O<138> WL_O<137> WL_O<136> WL_O<135> WL_O<134> ++ WL_O<133> WL_O<132> WL_O<131> WL_O<130> WL_O<129> WL_O<128> WL_O<127> ++ WL_O<126> WL_O<125> WL_O<124> WL_O<123> WL_O<122> WL_O<121> WL_O<120> ++ WL_O<119> WL_O<118> WL_O<117> WL_O<116> WL_O<115> WL_O<114> WL_O<113> ++ WL_O<112> WL_O<111> WL_O<110> WL_O<109> WL_O<108> WL_O<107> WL_O<106> ++ WL_O<105> WL_O<104> WL_O<103> WL_O<102> WL_O<101> WL_O<100> WL_O<99> ++ WL_O<98> WL_O<97> WL_O<96> WL_O<95> WL_O<94> WL_O<93> WL_O<92> WL_O<91> ++ WL_O<90> WL_O<89> WL_O<88> WL_O<87> WL_O<86> WL_O<85> WL_O<84> WL_O<83> ++ WL_O<82> WL_O<81> WL_O<80> WL_O<79> WL_O<78> WL_O<77> WL_O<76> WL_O<75> ++ WL_O<74> WL_O<73> WL_O<72> WL_O<71> WL_O<70> WL_O<69> WL_O<68> WL_O<67> ++ WL_O<66> WL_O<65> WL_O<64> WL_O<63> WL_O<62> WL_O<61> WL_O<60> WL_O<59> ++ WL_O<58> WL_O<57> WL_O<56> WL_O<55> WL_O<54> WL_O<53> WL_O<52> WL_O<51> ++ WL_O<50> WL_O<49> WL_O<48> WL_O<47> WL_O<46> WL_O<45> WL_O<44> WL_O<43> ++ WL_O<42> WL_O<41> WL_O<40> WL_O<39> WL_O<38> WL_O<37> WL_O<36> WL_O<35> ++ WL_O<34> WL_O<33> WL_O<32> WL_O<31> WL_O<30> WL_O<29> WL_O<28> WL_O<27> ++ WL_O<26> WL_O<25> WL_O<24> WL_O<23> WL_O<22> WL_O<21> WL_O<20> WL_O<19> ++ WL_O<18> WL_O<17> WL_O<16> WL_O<15> WL_O<14> WL_O<13> WL_O<12> WL_O<11> ++ WL_O<10> WL_O<9> WL_O<8> WL_O<7> WL_O<6> WL_O<5> WL_O<4> WL_O<3> WL_O<2> ++ WL_O<1> WL_O<0> VDD VSS +XL2<172> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<171> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<170> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<169> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<168> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<167> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<166> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<165> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<164> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<163> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<162> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<161> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<160> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<159> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<158> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<157> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<156> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<155> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<154> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<153> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<152> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<151> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<150> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<149> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<148> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<147> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<146> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<145> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<144> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<143> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<142> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<141> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<140> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<139> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<138> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<137> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<136> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<135> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<134> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<133> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<132> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<131> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<130> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<129> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<128> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<127> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<126> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<125> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<124> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<123> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<122> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<121> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<120> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<119> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<118> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<117> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<116> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<115> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<114> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<113> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<112> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<111> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<110> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<109> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<108> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<107> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<106> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<105> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<104> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<103> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<102> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<101> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<100> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<99> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<98> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<97> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<96> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<95> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<94> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<93> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<92> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<91> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<90> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<89> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<88> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<87> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<86> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<85> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<84> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<83> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<82> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<81> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<80> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<79> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<78> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<77> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<76> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<75> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<74> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<73> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<72> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<71> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<70> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<69> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<68> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<67> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<66> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<65> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<64> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<63> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<62> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<61> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<60> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<59> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<58> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<57> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<56> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<55> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<54> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<53> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<52> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<51> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<50> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<49> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<48> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<47> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<46> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<45> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<44> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<43> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<42> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<41> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<40> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<39> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<38> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<37> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<36> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<35> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<34> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<33> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<32> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<31> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<30> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<29> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<28> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<27> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<26> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<25> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<24> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<23> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<22> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<21> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<20> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<19> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<18> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<17> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<16> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<15> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<14> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<13> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<12> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<11> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<10> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<9> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<8> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<7> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<6> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<5> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<4> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<3> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<2> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<1> VDD VSS / RSC_IHPSG13_FILLCAP8 +XDEC11<9> ADDR_N_I<7> ADDR_N_I<6> CS04<1> CS02<7> VDD VSS / ++ RM_IHPSG13_256x32_c2_1P_DEC03 +XDEC11<8> ADDR_N_I<7> ADDR_N_I<6> CS04<0> CS02<3> VDD VSS / ++ RM_IHPSG13_256x32_c2_1P_DEC03 +XDEC11<7> ADDR_N_I<5> ADDR_N_I<4> CS02<7> CS00<31> VDD VSS / ++ RM_IHPSG13_256x32_c2_1P_DEC03 +XDEC11<6> ADDR_N_I<5> ADDR_N_I<4> CS02<6> CS00<27> VDD VSS / ++ RM_IHPSG13_256x32_c2_1P_DEC03 +XDEC11<5> ADDR_N_I<5> ADDR_N_I<4> CS02<5> CS00<23> VDD VSS / ++ RM_IHPSG13_256x32_c2_1P_DEC03 +XDEC11<4> ADDR_N_I<5> ADDR_N_I<4> CS02<4> CS00<19> VDD VSS / ++ RM_IHPSG13_256x32_c2_1P_DEC03 +XDEC11<3> ADDR_N_I<5> ADDR_N_I<4> CS02<3> CS00<15> VDD VSS / ++ RM_IHPSG13_256x32_c2_1P_DEC03 +XDEC11<2> ADDR_N_I<5> ADDR_N_I<4> CS02<2> CS00<11> VDD VSS / ++ RM_IHPSG13_256x32_c2_1P_DEC03 +XDEC11<1> ADDR_N_I<5> ADDR_N_I<4> CS02<1> CS00<7> VDD VSS / ++ RM_IHPSG13_256x32_c2_1P_DEC03 +XDEC11<0> ADDR_N_I<5> ADDR_N_I<4> CS02<0> CS00<3> VDD VSS / ++ RM_IHPSG13_256x32_c2_1P_DEC03 +XDEC00<10> ADDR_N_I<9> ADDR_N_I<8> CS_I CS04<0> VDD VSS / ++ RM_IHPSG13_256x32_c2_1P_DEC00 +XDEC00<9> ADDR_N_I<7> ADDR_N_I<6> CS04<1> CS02<4> VDD VSS / ++ RM_IHPSG13_256x32_c2_1P_DEC00 +XDEC00<8> ADDR_N_I<7> ADDR_N_I<6> CS04<0> CS02<0> VDD VSS / ++ RM_IHPSG13_256x32_c2_1P_DEC00 +XDEC00<7> ADDR_N_I<5> ADDR_N_I<4> CS02<7> CS00<28> VDD VSS / ++ RM_IHPSG13_256x32_c2_1P_DEC00 +XDEC00<6> ADDR_N_I<5> ADDR_N_I<4> CS02<6> CS00<24> VDD VSS / ++ RM_IHPSG13_256x32_c2_1P_DEC00 +XDEC00<5> ADDR_N_I<5> ADDR_N_I<4> CS02<5> CS00<20> VDD VSS / ++ RM_IHPSG13_256x32_c2_1P_DEC00 +XDEC00<4> ADDR_N_I<5> ADDR_N_I<4> CS02<4> CS00<16> VDD VSS / ++ RM_IHPSG13_256x32_c2_1P_DEC00 +XDEC00<3> ADDR_N_I<5> ADDR_N_I<4> CS02<3> CS00<12> VDD VSS / ++ RM_IHPSG13_256x32_c2_1P_DEC00 +XDEC00<2> ADDR_N_I<5> ADDR_N_I<4> CS02<2> CS00<8> VDD VSS / ++ RM_IHPSG13_256x32_c2_1P_DEC00 +XDEC00<1> ADDR_N_I<5> ADDR_N_I<4> CS02<1> CS00<4> VDD VSS / ++ RM_IHPSG13_256x32_c2_1P_DEC00 +XDEC00<0> ADDR_N_I<5> ADDR_N_I<4> CS02<0> CS00<0> VDD VSS / ++ RM_IHPSG13_256x32_c2_1P_DEC00 +XSEL<31> ADDR_N_I<3> ADDR_N_I<2> ADDR_N_I<1> ADDR_N_I<0> CS00<31> ECLK_H<31> ++ ECLK_H<32> ECLK_B<31> ECLK_B<32> WL_O<511> WL_O<510> WL_O<509> WL_O<508> ++ WL_O<507> WL_O<506> WL_O<505> WL_O<504> WL_O<503> WL_O<502> WL_O<501> ++ WL_O<500> WL_O<499> WL_O<498> WL_O<497> WL_O<496> VDD VSS / ++ RM_IHPSG13_256x32_c2_1P_DEC04 +XSEL<30> ADDR_N_I<3> ADDR_N_I<2> ADDR_N_I<1> ADDR_N_I<0> CS00<30> ECLK_H<30> ++ ECLK_H<31> ECLK_B<30> ECLK_B<31> WL_O<495> WL_O<494> WL_O<493> WL_O<492> ++ WL_O<491> WL_O<490> WL_O<489> WL_O<488> WL_O<487> WL_O<486> WL_O<485> ++ WL_O<484> WL_O<483> WL_O<482> WL_O<481> WL_O<480> VDD VSS / ++ RM_IHPSG13_256x32_c2_1P_DEC04 +XSEL<29> ADDR_N_I<3> ADDR_N_I<2> ADDR_N_I<1> ADDR_N_I<0> CS00<29> ECLK_H<29> ++ ECLK_H<30> ECLK_B<29> ECLK_B<30> WL_O<479> WL_O<478> WL_O<477> WL_O<476> ++ WL_O<475> WL_O<474> WL_O<473> WL_O<472> WL_O<471> WL_O<470> WL_O<469> ++ WL_O<468> WL_O<467> WL_O<466> WL_O<465> WL_O<464> VDD VSS / ++ RM_IHPSG13_256x32_c2_1P_DEC04 +XSEL<28> ADDR_N_I<3> ADDR_N_I<2> ADDR_N_I<1> ADDR_N_I<0> CS00<28> ECLK_H<28> ++ ECLK_H<29> ECLK_B<28> ECLK_B<29> WL_O<463> WL_O<462> WL_O<461> WL_O<460> ++ WL_O<459> WL_O<458> WL_O<457> WL_O<456> WL_O<455> WL_O<454> WL_O<453> ++ WL_O<452> WL_O<451> WL_O<450> WL_O<449> WL_O<448> VDD VSS / ++ RM_IHPSG13_256x32_c2_1P_DEC04 +XSEL<27> ADDR_N_I<3> ADDR_N_I<2> ADDR_N_I<1> ADDR_N_I<0> CS00<27> ECLK_H<27> ++ ECLK_H<28> ECLK_B<27> ECLK_B<28> WL_O<447> WL_O<446> WL_O<445> WL_O<444> ++ WL_O<443> WL_O<442> WL_O<441> WL_O<440> WL_O<439> WL_O<438> WL_O<437> ++ WL_O<436> WL_O<435> WL_O<434> WL_O<433> WL_O<432> VDD VSS / ++ RM_IHPSG13_256x32_c2_1P_DEC04 +XSEL<26> ADDR_N_I<3> ADDR_N_I<2> ADDR_N_I<1> ADDR_N_I<0> CS00<26> ECLK_H<26> ++ ECLK_H<27> ECLK_B<26> ECLK_B<27> WL_O<431> WL_O<430> WL_O<429> WL_O<428> ++ WL_O<427> WL_O<426> WL_O<425> WL_O<424> WL_O<423> WL_O<422> WL_O<421> ++ WL_O<420> WL_O<419> WL_O<418> WL_O<417> WL_O<416> VDD VSS / ++ RM_IHPSG13_256x32_c2_1P_DEC04 +XSEL<25> ADDR_N_I<3> ADDR_N_I<2> ADDR_N_I<1> ADDR_N_I<0> CS00<25> ECLK_H<25> ++ ECLK_H<26> ECLK_B<25> ECLK_B<26> WL_O<415> WL_O<414> WL_O<413> WL_O<412> ++ WL_O<411> WL_O<410> WL_O<409> WL_O<408> WL_O<407> WL_O<406> WL_O<405> ++ WL_O<404> WL_O<403> WL_O<402> WL_O<401> WL_O<400> VDD VSS / ++ RM_IHPSG13_256x32_c2_1P_DEC04 +XSEL<24> ADDR_N_I<3> ADDR_N_I<2> ADDR_N_I<1> ADDR_N_I<0> CS00<24> ECLK_H<24> ++ ECLK_H<25> ECLK_B<24> ECLK_B<25> WL_O<399> WL_O<398> WL_O<397> WL_O<396> ++ WL_O<395> WL_O<394> WL_O<393> WL_O<392> WL_O<391> WL_O<390> WL_O<389> ++ WL_O<388> WL_O<387> WL_O<386> WL_O<385> WL_O<384> VDD VSS / ++ RM_IHPSG13_256x32_c2_1P_DEC04 +XSEL<23> ADDR_N_I<3> ADDR_N_I<2> ADDR_N_I<1> ADDR_N_I<0> CS00<23> ECLK_H<23> ++ ECLK_H<24> ECLK_B<23> ECLK_B<24> WL_O<383> WL_O<382> WL_O<381> WL_O<380> ++ WL_O<379> WL_O<378> WL_O<377> WL_O<376> WL_O<375> WL_O<374> WL_O<373> ++ WL_O<372> WL_O<371> WL_O<370> WL_O<369> WL_O<368> VDD VSS / ++ RM_IHPSG13_256x32_c2_1P_DEC04 +XSEL<22> ADDR_N_I<3> ADDR_N_I<2> ADDR_N_I<1> ADDR_N_I<0> CS00<22> ECLK_H<22> ++ ECLK_H<23> ECLK_B<22> ECLK_B<23> WL_O<367> WL_O<366> WL_O<365> WL_O<364> ++ WL_O<363> WL_O<362> WL_O<361> WL_O<360> WL_O<359> WL_O<358> WL_O<357> ++ WL_O<356> WL_O<355> WL_O<354> WL_O<353> WL_O<352> VDD VSS / ++ RM_IHPSG13_256x32_c2_1P_DEC04 +XSEL<21> ADDR_N_I<3> ADDR_N_I<2> ADDR_N_I<1> ADDR_N_I<0> CS00<21> ECLK_H<21> ++ ECLK_H<22> ECLK_B<21> ECLK_B<22> WL_O<351> WL_O<350> WL_O<349> WL_O<348> ++ WL_O<347> WL_O<346> WL_O<345> WL_O<344> WL_O<343> WL_O<342> WL_O<341> ++ WL_O<340> WL_O<339> WL_O<338> WL_O<337> WL_O<336> VDD VSS / ++ RM_IHPSG13_256x32_c2_1P_DEC04 +XSEL<20> ADDR_N_I<3> ADDR_N_I<2> ADDR_N_I<1> ADDR_N_I<0> CS00<20> ECLK_H<20> ++ ECLK_H<21> ECLK_B<20> ECLK_B<21> WL_O<335> WL_O<334> WL_O<333> WL_O<332> ++ WL_O<331> WL_O<330> WL_O<329> WL_O<328> WL_O<327> WL_O<326> WL_O<325> ++ WL_O<324> WL_O<323> WL_O<322> WL_O<321> WL_O<320> VDD VSS / ++ RM_IHPSG13_256x32_c2_1P_DEC04 +XSEL<19> ADDR_N_I<3> ADDR_N_I<2> ADDR_N_I<1> ADDR_N_I<0> CS00<19> ECLK_H<19> ++ ECLK_H<20> ECLK_B<19> ECLK_B<20> WL_O<319> WL_O<318> WL_O<317> WL_O<316> ++ WL_O<315> WL_O<314> WL_O<313> WL_O<312> WL_O<311> WL_O<310> WL_O<309> ++ WL_O<308> WL_O<307> WL_O<306> WL_O<305> WL_O<304> VDD VSS / ++ RM_IHPSG13_256x32_c2_1P_DEC04 +XSEL<18> ADDR_N_I<3> ADDR_N_I<2> ADDR_N_I<1> ADDR_N_I<0> CS00<18> ECLK_H<18> ++ ECLK_H<19> ECLK_B<18> ECLK_B<19> WL_O<303> WL_O<302> WL_O<301> WL_O<300> ++ WL_O<299> WL_O<298> WL_O<297> WL_O<296> WL_O<295> WL_O<294> WL_O<293> ++ WL_O<292> WL_O<291> WL_O<290> WL_O<289> WL_O<288> VDD VSS / ++ RM_IHPSG13_256x32_c2_1P_DEC04 +XSEL<17> ADDR_N_I<3> ADDR_N_I<2> ADDR_N_I<1> ADDR_N_I<0> CS00<17> ECLK_H<17> ++ ECLK_H<18> ECLK_B<17> ECLK_B<18> WL_O<287> WL_O<286> WL_O<285> WL_O<284> ++ WL_O<283> WL_O<282> WL_O<281> WL_O<280> WL_O<279> WL_O<278> WL_O<277> ++ WL_O<276> WL_O<275> WL_O<274> WL_O<273> WL_O<272> VDD VSS / ++ RM_IHPSG13_256x32_c2_1P_DEC04 +XSEL<16> ADDR_N_I<3> ADDR_N_I<2> ADDR_N_I<1> ADDR_N_I<0> CS00<16> ECLK_H<16> ++ ECLK_H<17> ECLK_B<16> ECLK_B<17> WL_O<271> WL_O<270> WL_O<269> WL_O<268> ++ WL_O<267> WL_O<266> WL_O<265> WL_O<264> WL_O<263> WL_O<262> WL_O<261> ++ WL_O<260> WL_O<259> WL_O<258> WL_O<257> WL_O<256> VDD VSS / ++ RM_IHPSG13_256x32_c2_1P_DEC04 +XSEL<15> ADDR_N_I<3> ADDR_N_I<2> ADDR_N_I<1> ADDR_N_I<0> CS00<15> ECLK_H<15> ++ ECLK_H<16> ECLK_B<15> ECLK_B<16> WL_O<255> WL_O<254> WL_O<253> WL_O<252> ++ WL_O<251> WL_O<250> WL_O<249> WL_O<248> WL_O<247> WL_O<246> WL_O<245> ++ WL_O<244> WL_O<243> WL_O<242> WL_O<241> WL_O<240> VDD VSS / ++ RM_IHPSG13_256x32_c2_1P_DEC04 +XSEL<14> ADDR_N_I<3> ADDR_N_I<2> ADDR_N_I<1> ADDR_N_I<0> CS00<14> ECLK_H<14> ++ ECLK_H<15> ECLK_B<14> ECLK_B<15> WL_O<239> WL_O<238> WL_O<237> WL_O<236> ++ WL_O<235> WL_O<234> WL_O<233> WL_O<232> WL_O<231> WL_O<230> WL_O<229> ++ WL_O<228> WL_O<227> WL_O<226> WL_O<225> WL_O<224> VDD VSS / ++ RM_IHPSG13_256x32_c2_1P_DEC04 +XSEL<13> ADDR_N_I<3> ADDR_N_I<2> ADDR_N_I<1> ADDR_N_I<0> CS00<13> ECLK_H<13> ++ ECLK_H<14> ECLK_B<13> ECLK_B<14> WL_O<223> WL_O<222> WL_O<221> WL_O<220> ++ WL_O<219> WL_O<218> WL_O<217> WL_O<216> WL_O<215> WL_O<214> WL_O<213> ++ WL_O<212> WL_O<211> WL_O<210> WL_O<209> WL_O<208> VDD VSS / ++ RM_IHPSG13_256x32_c2_1P_DEC04 +XSEL<12> ADDR_N_I<3> ADDR_N_I<2> ADDR_N_I<1> ADDR_N_I<0> CS00<12> ECLK_H<12> ++ ECLK_H<13> ECLK_B<12> ECLK_B<13> WL_O<207> WL_O<206> WL_O<205> WL_O<204> ++ WL_O<203> WL_O<202> WL_O<201> WL_O<200> WL_O<199> WL_O<198> WL_O<197> ++ WL_O<196> WL_O<195> WL_O<194> WL_O<193> WL_O<192> VDD VSS / ++ RM_IHPSG13_256x32_c2_1P_DEC04 +XSEL<11> ADDR_N_I<3> ADDR_N_I<2> ADDR_N_I<1> ADDR_N_I<0> CS00<11> ECLK_H<11> ++ ECLK_H<12> ECLK_B<11> ECLK_B<12> WL_O<191> WL_O<190> WL_O<189> WL_O<188> ++ WL_O<187> WL_O<186> WL_O<185> WL_O<184> WL_O<183> WL_O<182> WL_O<181> ++ WL_O<180> WL_O<179> WL_O<178> WL_O<177> WL_O<176> VDD VSS / ++ RM_IHPSG13_256x32_c2_1P_DEC04 +XSEL<10> ADDR_N_I<3> ADDR_N_I<2> ADDR_N_I<1> ADDR_N_I<0> CS00<10> ECLK_H<10> ++ ECLK_H<11> ECLK_B<10> ECLK_B<11> WL_O<175> WL_O<174> WL_O<173> WL_O<172> ++ WL_O<171> WL_O<170> WL_O<169> WL_O<168> WL_O<167> WL_O<166> WL_O<165> ++ WL_O<164> WL_O<163> WL_O<162> WL_O<161> WL_O<160> VDD VSS / ++ RM_IHPSG13_256x32_c2_1P_DEC04 +XSEL<9> ADDR_N_I<3> ADDR_N_I<2> ADDR_N_I<1> ADDR_N_I<0> CS00<9> ECLK_H<9> ++ ECLK_H<10> ECLK_B<9> ECLK_B<10> WL_O<159> WL_O<158> WL_O<157> WL_O<156> ++ WL_O<155> WL_O<154> WL_O<153> WL_O<152> WL_O<151> WL_O<150> WL_O<149> ++ WL_O<148> WL_O<147> WL_O<146> WL_O<145> WL_O<144> VDD VSS / ++ RM_IHPSG13_256x32_c2_1P_DEC04 +XSEL<8> ADDR_N_I<3> ADDR_N_I<2> ADDR_N_I<1> ADDR_N_I<0> CS00<8> ECLK_H<8> ++ ECLK_H<9> ECLK_B<8> ECLK_B<9> WL_O<143> WL_O<142> WL_O<141> WL_O<140> ++ WL_O<139> WL_O<138> WL_O<137> WL_O<136> WL_O<135> WL_O<134> WL_O<133> ++ WL_O<132> WL_O<131> WL_O<130> WL_O<129> WL_O<128> VDD VSS / ++ RM_IHPSG13_256x32_c2_1P_DEC04 +XSEL<7> ADDR_N_I<3> ADDR_N_I<2> ADDR_N_I<1> ADDR_N_I<0> CS00<7> ECLK_H<7> ++ ECLK_H<8> ECLK_B<7> ECLK_B<8> WL_O<127> WL_O<126> WL_O<125> WL_O<124> ++ WL_O<123> WL_O<122> WL_O<121> WL_O<120> WL_O<119> WL_O<118> WL_O<117> ++ WL_O<116> WL_O<115> WL_O<114> WL_O<113> WL_O<112> VDD VSS / ++ RM_IHPSG13_256x32_c2_1P_DEC04 +XSEL<6> ADDR_N_I<3> ADDR_N_I<2> ADDR_N_I<1> ADDR_N_I<0> CS00<6> ECLK_H<6> ++ ECLK_H<7> ECLK_B<6> ECLK_B<7> WL_O<111> WL_O<110> WL_O<109> WL_O<108> ++ WL_O<107> WL_O<106> WL_O<105> WL_O<104> WL_O<103> WL_O<102> WL_O<101> ++ WL_O<100> WL_O<99> WL_O<98> WL_O<97> WL_O<96> VDD VSS / ++ RM_IHPSG13_256x32_c2_1P_DEC04 +XSEL<5> ADDR_N_I<3> ADDR_N_I<2> ADDR_N_I<1> ADDR_N_I<0> CS00<5> ECLK_H<5> ++ ECLK_H<6> ECLK_B<5> ECLK_B<6> WL_O<95> WL_O<94> WL_O<93> WL_O<92> WL_O<91> ++ WL_O<90> WL_O<89> WL_O<88> WL_O<87> WL_O<86> WL_O<85> WL_O<84> WL_O<83> ++ WL_O<82> WL_O<81> WL_O<80> VDD VSS / RM_IHPSG13_256x32_c2_1P_DEC04 +XSEL<4> ADDR_N_I<3> ADDR_N_I<2> ADDR_N_I<1> ADDR_N_I<0> CS00<4> ECLK_H<4> ++ ECLK_H<5> ECLK_B<4> ECLK_B<5> WL_O<79> WL_O<78> WL_O<77> WL_O<76> WL_O<75> ++ WL_O<74> WL_O<73> WL_O<72> WL_O<71> WL_O<70> WL_O<69> WL_O<68> WL_O<67> ++ WL_O<66> WL_O<65> WL_O<64> VDD VSS / RM_IHPSG13_256x32_c2_1P_DEC04 +XSEL<3> ADDR_N_I<3> ADDR_N_I<2> ADDR_N_I<1> ADDR_N_I<0> CS00<3> ECLK_H<3> ++ ECLK_H<4> ECLK_B<3> ECLK_B<4> WL_O<63> WL_O<62> WL_O<61> WL_O<60> WL_O<59> ++ WL_O<58> WL_O<57> WL_O<56> WL_O<55> WL_O<54> WL_O<53> WL_O<52> WL_O<51> ++ WL_O<50> WL_O<49> WL_O<48> VDD VSS / RM_IHPSG13_256x32_c2_1P_DEC04 +XSEL<2> ADDR_N_I<3> ADDR_N_I<2> ADDR_N_I<1> ADDR_N_I<0> CS00<2> ECLK_H<2> ++ ECLK_H<3> ECLK_B<2> ECLK_B<3> WL_O<47> WL_O<46> WL_O<45> WL_O<44> WL_O<43> ++ WL_O<42> WL_O<41> WL_O<40> WL_O<39> WL_O<38> WL_O<37> WL_O<36> WL_O<35> ++ WL_O<34> WL_O<33> WL_O<32> VDD VSS / RM_IHPSG13_256x32_c2_1P_DEC04 +XSEL<1> ADDR_N_I<3> ADDR_N_I<2> ADDR_N_I<1> ADDR_N_I<0> CS00<1> ECLK_H<1> ++ ECLK_H<2> ECLK_B<1> ECLK_B<2> WL_O<31> WL_O<30> WL_O<29> WL_O<28> WL_O<27> ++ WL_O<26> WL_O<25> WL_O<24> WL_O<23> WL_O<22> WL_O<21> WL_O<20> WL_O<19> ++ WL_O<18> WL_O<17> WL_O<16> VDD VSS / RM_IHPSG13_256x32_c2_1P_DEC04 +XSEL<0> ADDR_N_I<3> ADDR_N_I<2> ADDR_N_I<1> ADDR_N_I<0> CS00<0> ECLK_I ++ ECLK_H<1> ECLK_B<0> ECLK_B<1> WL_O<15> WL_O<14> WL_O<13> WL_O<12> WL_O<11> ++ WL_O<10> WL_O<9> WL_O<8> WL_O<7> WL_O<6> WL_O<5> WL_O<4> WL_O<3> WL_O<2> ++ WL_O<1> WL_O<0> VDD VSS / RM_IHPSG13_256x32_c2_1P_DEC04 +XDEC01<10> ADDR_N_I<9> ADDR_N_I<8> CS_I CS04<1> VDD VSS / ++ RM_IHPSG13_256x32_c2_1P_DEC01 +XDEC01<9> ADDR_N_I<7> ADDR_N_I<6> CS04<1> CS02<5> VDD VSS / ++ RM_IHPSG13_256x32_c2_1P_DEC01 +XDEC01<8> ADDR_N_I<7> ADDR_N_I<6> CS04<0> CS02<1> VDD VSS / ++ RM_IHPSG13_256x32_c2_1P_DEC01 +XDEC01<7> ADDR_N_I<5> ADDR_N_I<4> CS02<7> CS00<29> VDD VSS / ++ RM_IHPSG13_256x32_c2_1P_DEC01 +XDEC01<6> ADDR_N_I<5> ADDR_N_I<4> CS02<6> CS00<25> VDD VSS / ++ RM_IHPSG13_256x32_c2_1P_DEC01 +XDEC01<5> ADDR_N_I<5> ADDR_N_I<4> CS02<5> CS00<21> VDD VSS / ++ RM_IHPSG13_256x32_c2_1P_DEC01 +XDEC01<4> ADDR_N_I<5> ADDR_N_I<4> CS02<4> CS00<17> VDD VSS / ++ RM_IHPSG13_256x32_c2_1P_DEC01 +XDEC01<3> ADDR_N_I<5> ADDR_N_I<4> CS02<3> CS00<13> VDD VSS / ++ RM_IHPSG13_256x32_c2_1P_DEC01 +XDEC01<2> ADDR_N_I<5> ADDR_N_I<4> CS02<2> CS00<9> VDD VSS / ++ RM_IHPSG13_256x32_c2_1P_DEC01 +XDEC01<1> ADDR_N_I<5> ADDR_N_I<4> CS02<1> CS00<5> VDD VSS / ++ RM_IHPSG13_256x32_c2_1P_DEC01 +XDEC01<0> ADDR_N_I<5> ADDR_N_I<4> CS02<0> CS00<1> VDD VSS / ++ RM_IHPSG13_256x32_c2_1P_DEC01 +XDEC10<9> ADDR_N_I<7> ADDR_N_I<6> CS04<1> CS02<6> VDD VSS / ++ RM_IHPSG13_256x32_c2_1P_DEC02 +XDEC10<8> ADDR_N_I<7> ADDR_N_I<6> CS04<0> CS02<2> VDD VSS / ++ RM_IHPSG13_256x32_c2_1P_DEC02 +XDEC10<7> ADDR_N_I<5> ADDR_N_I<4> CS02<7> CS00<30> VDD VSS / ++ RM_IHPSG13_256x32_c2_1P_DEC02 +XDEC10<6> ADDR_N_I<5> ADDR_N_I<4> CS02<6> CS00<26> VDD VSS / ++ RM_IHPSG13_256x32_c2_1P_DEC02 +XDEC10<5> ADDR_N_I<5> ADDR_N_I<4> CS02<5> CS00<22> VDD VSS / ++ RM_IHPSG13_256x32_c2_1P_DEC02 +XDEC10<4> ADDR_N_I<5> ADDR_N_I<4> CS02<4> CS00<18> VDD VSS / ++ RM_IHPSG13_256x32_c2_1P_DEC02 +XDEC10<3> ADDR_N_I<5> ADDR_N_I<4> CS02<3> CS00<14> VDD VSS / ++ RM_IHPSG13_256x32_c2_1P_DEC02 +XDEC10<2> ADDR_N_I<5> ADDR_N_I<4> CS02<2> CS00<10> VDD VSS / ++ RM_IHPSG13_256x32_c2_1P_DEC02 +XDEC10<1> ADDR_N_I<5> ADDR_N_I<4> CS02<1> CS00<6> VDD VSS / ++ RM_IHPSG13_256x32_c2_1P_DEC02 +XDEC10<0> ADDR_N_I<5> ADDR_N_I<4> CS02<0> CS00<2> VDD VSS / ++ RM_IHPSG13_256x32_c2_1P_DEC02 +XI0 ADDR_N_I<9> VDD VSS / RSC_IHPSG13_TIEL +.ENDS +.SUBCKT RM_IHPSG13_256x32_c2_1P_ROWREG9 ACLK_N_I ADDR_I<8> ADDR_I<7> ADDR_I<6> ADDR_I<5> ++ ADDR_I<4> ADDR_I<3> ADDR_I<2> ADDR_I<1> ADDR_I<0> ADDR_N_O<8> ADDR_N_O<7> ++ ADDR_N_O<6> ADDR_N_O<5> ADDR_N_O<4> ADDR_N_O<3> ADDR_N_O<2> ADDR_N_O<1> ++ ADDR_N_O<0> BIST_ADDR_I<8> BIST_ADDR_I<7> BIST_ADDR_I<6> BIST_ADDR_I<5> ++ BIST_ADDR_I<4> BIST_ADDR_I<3> BIST_ADDR_I<2> BIST_ADDR_I<1> BIST_ADDR_I<0> ++ BIST_EN_I VDD VSS +XINV<8> q_int<8> qn_int<8> VDD VSS / RSC_IHPSG13_CINVX2 +XINV<7> q_int<7> qn_int<7> VDD VSS / RSC_IHPSG13_CINVX2 +XINV<6> q_int<6> qn_int<6> VDD VSS / RSC_IHPSG13_CINVX2 +XINV<5> q_int<5> qn_int<5> VDD VSS / RSC_IHPSG13_CINVX2 +XINV<4> q_int<4> qn_int<4> VDD VSS / RSC_IHPSG13_CINVX2 +XINV<3> q_int<3> qn_int<3> VDD VSS / RSC_IHPSG13_CINVX2 +XINV<2> q_int<2> qn_int<2> VDD VSS / RSC_IHPSG13_CINVX2 +XINV<1> q_int<1> qn_int<1> VDD VSS / RSC_IHPSG13_CINVX2 +XINV<0> q_int<0> qn_int<0> VDD VSS / RSC_IHPSG13_CINVX2 +XDRV<8> qn_int<8> ADDR_N_O<8> VDD VSS / RSC_IHPSG13_CINVX8 +XDRV<7> qn_int<7> ADDR_N_O<7> VDD VSS / RSC_IHPSG13_CINVX8 +XDRV<6> qn_int<6> ADDR_N_O<6> VDD VSS / RSC_IHPSG13_CINVX8 +XDRV<5> qn_int<5> ADDR_N_O<5> VDD VSS / RSC_IHPSG13_CINVX8 +XDRV<4> qn_int<4> ADDR_N_O<4> VDD VSS / RSC_IHPSG13_CINVX8 +XDRV<3> qn_int<3> ADDR_N_O<3> VDD VSS / RSC_IHPSG13_CINVX8 +XDRV<2> qn_int<2> ADDR_N_O<2> VDD VSS / RSC_IHPSG13_CINVX8 +XDRV<1> qn_int<1> ADDR_N_O<1> VDD VSS / RSC_IHPSG13_CINVX8 +XDRV<0> qn_int<0> ADDR_N_O<0> VDD VSS / RSC_IHPSG13_CINVX8 +XDFF<8> BIST_EN_I BIST_ADDR_I<8> ACLK_N_I ADDR_I<8> q_int<8> net04<0> VDD ++ VSS / RSC_IHPSG13_DFNQMX2IX1 +XDFF<7> BIST_EN_I BIST_ADDR_I<7> ACLK_N_I ADDR_I<7> q_int<7> net04<1> VDD ++ VSS / RSC_IHPSG13_DFNQMX2IX1 +XDFF<6> BIST_EN_I BIST_ADDR_I<6> ACLK_N_I ADDR_I<6> q_int<6> net04<2> VDD ++ VSS / RSC_IHPSG13_DFNQMX2IX1 +XDFF<5> BIST_EN_I BIST_ADDR_I<5> ACLK_N_I ADDR_I<5> q_int<5> net04<3> VDD ++ VSS / RSC_IHPSG13_DFNQMX2IX1 +XDFF<4> BIST_EN_I BIST_ADDR_I<4> ACLK_N_I ADDR_I<4> q_int<4> net04<4> VDD ++ VSS / RSC_IHPSG13_DFNQMX2IX1 +XDFF<3> BIST_EN_I BIST_ADDR_I<3> ACLK_N_I ADDR_I<3> q_int<3> net04<5> VDD ++ VSS / RSC_IHPSG13_DFNQMX2IX1 +XDFF<2> BIST_EN_I BIST_ADDR_I<2> ACLK_N_I ADDR_I<2> q_int<2> net04<6> VDD ++ VSS / RSC_IHPSG13_DFNQMX2IX1 +XDFF<1> BIST_EN_I BIST_ADDR_I<1> ACLK_N_I ADDR_I<1> q_int<1> net04<7> VDD ++ VSS / RSC_IHPSG13_DFNQMX2IX1 +XDFF<0> BIST_EN_I BIST_ADDR_I<0> ACLK_N_I ADDR_I<0> q_int<0> net04<8> VDD ++ VSS / RSC_IHPSG13_DFNQMX2IX1 +.ENDS + +.SUBCKT RM_IHPSG13_256x32_c2_1P_ROWDEC7 ADDR_N_I<6> ADDR_N_I<5> ADDR_N_I<4> ADDR_N_I<3> ++ ADDR_N_I<2> ADDR_N_I<1> ADDR_N_I<0> CS_I ECLK_I WL_O<127> WL_O<126> ++ WL_O<125> WL_O<124> WL_O<123> WL_O<122> WL_O<121> WL_O<120> WL_O<119> ++ WL_O<118> WL_O<117> WL_O<116> WL_O<115> WL_O<114> WL_O<113> WL_O<112> ++ WL_O<111> WL_O<110> WL_O<109> WL_O<108> WL_O<107> WL_O<106> WL_O<105> ++ WL_O<104> WL_O<103> WL_O<102> WL_O<101> WL_O<100> WL_O<99> WL_O<98> WL_O<97> ++ WL_O<96> WL_O<95> WL_O<94> WL_O<93> WL_O<92> WL_O<91> WL_O<90> WL_O<89> ++ WL_O<88> WL_O<87> WL_O<86> WL_O<85> WL_O<84> WL_O<83> WL_O<82> WL_O<81> ++ WL_O<80> WL_O<79> WL_O<78> WL_O<77> WL_O<76> WL_O<75> WL_O<74> WL_O<73> ++ WL_O<72> WL_O<71> WL_O<70> WL_O<69> WL_O<68> WL_O<67> WL_O<66> WL_O<65> ++ WL_O<64> WL_O<63> WL_O<62> WL_O<61> WL_O<60> WL_O<59> WL_O<58> WL_O<57> ++ WL_O<56> WL_O<55> WL_O<54> WL_O<53> WL_O<52> WL_O<51> WL_O<50> WL_O<49> ++ WL_O<48> WL_O<47> WL_O<46> WL_O<45> WL_O<44> WL_O<43> WL_O<42> WL_O<41> ++ WL_O<40> WL_O<39> WL_O<38> WL_O<37> WL_O<36> WL_O<35> WL_O<34> WL_O<33> ++ WL_O<32> WL_O<31> WL_O<30> WL_O<29> WL_O<28> WL_O<27> WL_O<26> WL_O<25> ++ WL_O<24> WL_O<23> WL_O<22> WL_O<21> WL_O<20> WL_O<19> WL_O<18> WL_O<17> ++ WL_O<16> WL_O<15> WL_O<14> WL_O<13> WL_O<12> WL_O<11> WL_O<10> WL_O<9> ++ WL_O<8> WL_O<7> WL_O<6> WL_O<5> WL_O<4> WL_O<3> WL_O<2> WL_O<1> WL_O<0> ++ VDD VSS +XDEC11<1> ADDR_N_I<5> ADDR_N_I<4> CS04<1> CS00<7> VDD VSS / ++ RM_IHPSG13_256x32_c2_1P_DEC03 +XDEC11<0> ADDR_N_I<5> ADDR_N_I<4> CS04<0> CS00<3> VDD VSS / ++ RM_IHPSG13_256x32_c2_1P_DEC03 +XDEC10<1> ADDR_N_I<5> ADDR_N_I<4> CS04<1> CS00<6> VDD VSS / ++ RM_IHPSG13_256x32_c2_1P_DEC02 +XDEC10<0> ADDR_N_I<5> ADDR_N_I<4> CS04<0> CS00<2> VDD VSS / ++ RM_IHPSG13_256x32_c2_1P_DEC02 +XSEL<7> ADDR_N_I<3> ADDR_N_I<2> ADDR_N_I<1> ADDR_N_I<0> CS00<7> ECLK_H<7> ++ ECLK_H<8> ECLK_B<7> ECLK_B<8> WL_O<127> WL_O<126> WL_O<125> WL_O<124> ++ WL_O<123> WL_O<122> WL_O<121> WL_O<120> WL_O<119> WL_O<118> WL_O<117> ++ WL_O<116> WL_O<115> WL_O<114> WL_O<113> WL_O<112> VDD VSS / ++ RM_IHPSG13_256x32_c2_1P_DEC04 +XSEL<6> ADDR_N_I<3> ADDR_N_I<2> ADDR_N_I<1> ADDR_N_I<0> CS00<6> ECLK_H<6> ++ ECLK_H<7> ECLK_B<6> ECLK_B<7> WL_O<111> WL_O<110> WL_O<109> WL_O<108> ++ WL_O<107> WL_O<106> WL_O<105> WL_O<104> WL_O<103> WL_O<102> WL_O<101> ++ WL_O<100> WL_O<99> WL_O<98> WL_O<97> WL_O<96> VDD VSS / ++ RM_IHPSG13_256x32_c2_1P_DEC04 +XSEL<5> ADDR_N_I<3> ADDR_N_I<2> ADDR_N_I<1> ADDR_N_I<0> CS00<5> ECLK_H<5> ++ ECLK_H<6> ECLK_B<5> ECLK_B<6> WL_O<95> WL_O<94> WL_O<93> WL_O<92> WL_O<91> ++ WL_O<90> WL_O<89> WL_O<88> WL_O<87> WL_O<86> WL_O<85> WL_O<84> WL_O<83> ++ WL_O<82> WL_O<81> WL_O<80> VDD VSS / RM_IHPSG13_256x32_c2_1P_DEC04 +XSEL<4> ADDR_N_I<3> ADDR_N_I<2> ADDR_N_I<1> ADDR_N_I<0> CS00<4> ECLK_H<4> ++ ECLK_H<5> ECLK_B<4> ECLK_B<5> WL_O<79> WL_O<78> WL_O<77> WL_O<76> WL_O<75> ++ WL_O<74> WL_O<73> WL_O<72> WL_O<71> WL_O<70> WL_O<69> WL_O<68> WL_O<67> ++ WL_O<66> WL_O<65> WL_O<64> VDD VSS / RM_IHPSG13_256x32_c2_1P_DEC04 +XSEL<3> ADDR_N_I<3> ADDR_N_I<2> ADDR_N_I<1> ADDR_N_I<0> CS00<3> ECLK_H<3> ++ ECLK_H<4> ECLK_B<3> ECLK_B<4> WL_O<63> WL_O<62> WL_O<61> WL_O<60> WL_O<59> ++ WL_O<58> WL_O<57> WL_O<56> WL_O<55> WL_O<54> WL_O<53> WL_O<52> WL_O<51> ++ WL_O<50> WL_O<49> WL_O<48> VDD VSS / RM_IHPSG13_256x32_c2_1P_DEC04 +XSEL<2> ADDR_N_I<3> ADDR_N_I<2> ADDR_N_I<1> ADDR_N_I<0> CS00<2> ECLK_H<2> ++ ECLK_H<3> ECLK_B<2> ECLK_B<3> WL_O<47> WL_O<46> WL_O<45> WL_O<44> WL_O<43> ++ WL_O<42> WL_O<41> WL_O<40> WL_O<39> WL_O<38> WL_O<37> WL_O<36> WL_O<35> ++ WL_O<34> WL_O<33> WL_O<32> VDD VSS / RM_IHPSG13_256x32_c2_1P_DEC04 +XSEL<1> ADDR_N_I<3> ADDR_N_I<2> ADDR_N_I<1> ADDR_N_I<0> CS00<1> ECLK_H<1> ++ ECLK_H<2> ECLK_B<1> ECLK_B<2> WL_O<31> WL_O<30> WL_O<29> WL_O<28> WL_O<27> ++ WL_O<26> WL_O<25> WL_O<24> WL_O<23> WL_O<22> WL_O<21> WL_O<20> WL_O<19> ++ WL_O<18> WL_O<17> WL_O<16> VDD VSS / RM_IHPSG13_256x32_c2_1P_DEC04 +XSEL<0> ADDR_N_I<3> ADDR_N_I<2> ADDR_N_I<1> ADDR_N_I<0> CS00<0> ECLK_I ++ ECLK_H<1> ECLK_B<0> ECLK_B<1> WL_O<15> WL_O<14> WL_O<13> WL_O<12> WL_O<11> ++ WL_O<10> WL_O<9> WL_O<8> WL_O<7> WL_O<6> WL_O<5> WL_O<4> WL_O<3> WL_O<2> ++ WL_O<1> WL_O<0> VDD VSS / RM_IHPSG13_256x32_c2_1P_DEC04 +XDEC00<2> ADDR_N_I<7> ADDR_N_I<6> CS_I CS04<0> VDD VSS / ++ RM_IHPSG13_256x32_c2_1P_DEC00 +XDEC00<1> ADDR_N_I<5> ADDR_N_I<4> CS04<1> CS00<4> VDD VSS / ++ RM_IHPSG13_256x32_c2_1P_DEC00 +XDEC00<0> ADDR_N_I<5> ADDR_N_I<4> CS04<0> CS00<0> VDD VSS / ++ RM_IHPSG13_256x32_c2_1P_DEC00 +XDEC01<2> ADDR_N_I<7> ADDR_N_I<6> CS_I CS04<1> VDD VSS / ++ RM_IHPSG13_256x32_c2_1P_DEC01 +XDEC01<1> ADDR_N_I<5> ADDR_N_I<4> CS04<1> CS00<5> VDD VSS / ++ RM_IHPSG13_256x32_c2_1P_DEC01 +XDEC01<0> ADDR_N_I<5> ADDR_N_I<4> CS04<0> CS00<1> VDD VSS / ++ RM_IHPSG13_256x32_c2_1P_DEC01 +XL2<44> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<43> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<42> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<41> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<40> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<39> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<38> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<37> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<36> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<35> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<34> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<33> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<32> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<31> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<30> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<29> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<28> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<27> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<26> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<25> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<24> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<23> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<22> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<21> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<20> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<19> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<18> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<17> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<16> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<15> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<14> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<13> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<12> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<11> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<10> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<9> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<8> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<7> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<6> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<5> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<4> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<3> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<2> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<1> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI0 ADDR_N_I<7> VDD VSS / RSC_IHPSG13_TIEL +.ENDS +.SUBCKT RM_IHPSG13_256x32_c2_1P_ROWREG7 ACLK_N_I ADDR_I<6> ADDR_I<5> ADDR_I<4> ADDR_I<3> ++ ADDR_I<2> ADDR_I<1> ADDR_I<0> ADDR_N_O<6> ADDR_N_O<5> ADDR_N_O<4> ++ ADDR_N_O<3> ADDR_N_O<2> ADDR_N_O<1> ADDR_N_O<0> BIST_ADDR_I<6> ++ BIST_ADDR_I<5> BIST_ADDR_I<4> BIST_ADDR_I<3> BIST_ADDR_I<2> BIST_ADDR_I<1> ++ BIST_ADDR_I<0> BIST_EN_I VDD VSS +XINV<6> q_int<6> qn_int<6> VDD VSS / RSC_IHPSG13_CINVX2 +XINV<5> q_int<5> qn_int<5> VDD VSS / RSC_IHPSG13_CINVX2 +XINV<4> q_int<4> qn_int<4> VDD VSS / RSC_IHPSG13_CINVX2 +XINV<3> q_int<3> qn_int<3> VDD VSS / RSC_IHPSG13_CINVX2 +XINV<2> q_int<2> qn_int<2> VDD VSS / RSC_IHPSG13_CINVX2 +XINV<1> q_int<1> qn_int<1> VDD VSS / RSC_IHPSG13_CINVX2 +XINV<0> q_int<0> qn_int<0> VDD VSS / RSC_IHPSG13_CINVX2 +XDRV<6> qn_int<6> ADDR_N_O<6> VDD VSS / RSC_IHPSG13_CINVX8 +XDRV<5> qn_int<5> ADDR_N_O<5> VDD VSS / RSC_IHPSG13_CINVX8 +XDRV<4> qn_int<4> ADDR_N_O<4> VDD VSS / RSC_IHPSG13_CINVX8 +XDRV<3> qn_int<3> ADDR_N_O<3> VDD VSS / RSC_IHPSG13_CINVX8 +XDRV<2> qn_int<2> ADDR_N_O<2> VDD VSS / RSC_IHPSG13_CINVX8 +XDRV<1> qn_int<1> ADDR_N_O<1> VDD VSS / RSC_IHPSG13_CINVX8 +XDRV<0> qn_int<0> ADDR_N_O<0> VDD VSS / RSC_IHPSG13_CINVX8 +XDFF<6> BIST_EN_I BIST_ADDR_I<6> ACLK_N_I ADDR_I<6> q_int<6> net2<0> VDD ++ VSS / RSC_IHPSG13_DFNQMX2IX1 +XDFF<5> BIST_EN_I BIST_ADDR_I<5> ACLK_N_I ADDR_I<5> q_int<5> net2<1> VDD ++ VSS / RSC_IHPSG13_DFNQMX2IX1 +XDFF<4> BIST_EN_I BIST_ADDR_I<4> ACLK_N_I ADDR_I<4> q_int<4> net2<2> VDD ++ VSS / RSC_IHPSG13_DFNQMX2IX1 +XDFF<3> BIST_EN_I BIST_ADDR_I<3> ACLK_N_I ADDR_I<3> q_int<3> net2<3> VDD ++ VSS / RSC_IHPSG13_DFNQMX2IX1 +XDFF<2> BIST_EN_I BIST_ADDR_I<2> ACLK_N_I ADDR_I<2> q_int<2> net2<4> VDD ++ VSS / RSC_IHPSG13_DFNQMX2IX1 +XDFF<1> BIST_EN_I BIST_ADDR_I<1> ACLK_N_I ADDR_I<1> q_int<1> net2<5> VDD ++ VSS / RSC_IHPSG13_DFNQMX2IX1 +XDFF<0> BIST_EN_I BIST_ADDR_I<0> ACLK_N_I ADDR_I<0> q_int<0> net2<6> VDD ++ VSS / RSC_IHPSG13_DFNQMX2IX1 +XI11<8> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI11<7> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI11<6> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI11<5> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI11<4> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI11<3> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI11<2> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI11<1> VDD VSS / RSC_IHPSG13_FILLCAP8 +.ENDS + +.SUBCKT RM_IHPSG13_256x32_c2_1P_COLDRV13X8 ADDR_COL_I<1> ADDR_COL_I<0> ADDR_COL_O<1> ++ ADDR_COL_O<0> ADDR_DEC_I<7> ADDR_DEC_I<6> ADDR_DEC_I<5> ADDR_DEC_I<4> ++ ADDR_DEC_I<3> ADDR_DEC_I<2> ADDR_DEC_I<1> ADDR_DEC_I<0> ADDR_DEC_O<7> ++ ADDR_DEC_O<6> ADDR_DEC_O<5> ADDR_DEC_O<4> ADDR_DEC_O<3> ADDR_DEC_O<2> ++ ADDR_DEC_O<1> ADDR_DEC_O<0> DCLK_I DCLK_O RCLK_I RCLK_O WCLK_I WCLK_O ++ VDD VSS +XI0<1> VDD VSS / RSC_IHPSG13_FILLCAP4 +XI0<0> VDD VSS / RSC_IHPSG13_FILLCAP4 +XADDR_COL_DRV<1> ADDR_COL_I<1> ADDR_COL_O<1> VDD VSS / ++ RSC_IHPSG13_CBUFX8 +XADDR_COL_DRV<0> ADDR_COL_I<0> ADDR_COL_O<0> VDD VSS / ++ RSC_IHPSG13_CBUFX8 +XADDR_DEC_DRV<7> ADDR_DEC_I<7> ADDR_DEC_O<7> VDD VSS / ++ RSC_IHPSG13_CBUFX8 +XADDR_DEC_DRV<6> ADDR_DEC_I<6> ADDR_DEC_O<6> VDD VSS / ++ RSC_IHPSG13_CBUFX8 +XADDR_DEC_DRV<5> ADDR_DEC_I<5> ADDR_DEC_O<5> VDD VSS / ++ RSC_IHPSG13_CBUFX8 +XADDR_DEC_DRV<4> ADDR_DEC_I<4> ADDR_DEC_O<4> VDD VSS / ++ RSC_IHPSG13_CBUFX8 +XADDR_DEC_DRV<3> ADDR_DEC_I<3> ADDR_DEC_O<3> VDD VSS / ++ RSC_IHPSG13_CBUFX8 +XADDR_DEC_DRV<2> ADDR_DEC_I<2> ADDR_DEC_O<2> VDD VSS / ++ RSC_IHPSG13_CBUFX8 +XADDR_DEC_DRV<1> ADDR_DEC_I<1> ADDR_DEC_O<1> VDD VSS / ++ RSC_IHPSG13_CBUFX8 +XADDR_DEC_DRV<0> ADDR_DEC_I<0> ADDR_DEC_O<0> VDD VSS / ++ RSC_IHPSG13_CBUFX8 +XDCLK_DRV DCLK_I DCLK_O VDD VSS / RSC_IHPSG13_CBUFX8 +XRCLK_DRV RCLK_I RCLK_O VDD VSS / RSC_IHPSG13_CBUFX8 +XWCLK_DRV WCLK_I WCLK_O VDD VSS / RSC_IHPSG13_CBUFX8 +.ENDS +.SUBCKT RM_IHPSG13_256x32_c2_1P_WLDRV16X8 A<15> A<14> A<13> A<12> A<11> A<10> A<9> A<8> ++ A<7> A<6> A<5> A<4> A<3> A<2> A<1> A<0> Z<15> Z<14> Z<13> Z<12> Z<11> Z<10> ++ Z<9> Z<8> Z<7> Z<6> Z<5> Z<4> Z<3> Z<2> Z<1> Z<0> VDD VSS +XBUF<15> A<15> Z<15> VDD VSS / RSC_IHPSG13_WLDRVX8 +XBUF<14> A<14> Z<14> VDD VSS / RSC_IHPSG13_WLDRVX8 +XBUF<13> A<13> Z<13> VDD VSS / RSC_IHPSG13_WLDRVX8 +XBUF<12> A<12> Z<12> VDD VSS / RSC_IHPSG13_WLDRVX8 +XBUF<11> A<11> Z<11> VDD VSS / RSC_IHPSG13_WLDRVX8 +XBUF<10> A<10> Z<10> VDD VSS / RSC_IHPSG13_WLDRVX8 +XBUF<9> A<9> Z<9> VDD VSS / RSC_IHPSG13_WLDRVX8 +XBUF<8> A<8> Z<8> VDD VSS / RSC_IHPSG13_WLDRVX8 +XBUF<7> A<7> Z<7> VDD VSS / RSC_IHPSG13_WLDRVX8 +XBUF<6> A<6> Z<6> VDD VSS / RSC_IHPSG13_WLDRVX8 +XBUF<5> A<5> Z<5> VDD VSS / RSC_IHPSG13_WLDRVX8 +XBUF<4> A<4> Z<4> VDD VSS / RSC_IHPSG13_WLDRVX8 +XBUF<3> A<3> Z<3> VDD VSS / RSC_IHPSG13_WLDRVX8 +XBUF<2> A<2> Z<2> VDD VSS / RSC_IHPSG13_WLDRVX8 +XBUF<1> A<1> Z<1> VDD VSS / RSC_IHPSG13_WLDRVX8 +XBUF<0> A<0> Z<0> VDD VSS / RSC_IHPSG13_WLDRVX8 +.ENDS + + + +.SUBCKT RM_IHPSG13_256x32_c2_1P_ROWDEC6 ADDR_N_I<5> ADDR_N_I<4> ADDR_N_I<3> ADDR_N_I<2> ++ ADDR_N_I<1> ADDR_N_I<0> CS_I ECLK_I WL_O<63> WL_O<62> WL_O<61> WL_O<60> ++ WL_O<59> WL_O<58> WL_O<57> WL_O<56> WL_O<55> WL_O<54> WL_O<53> WL_O<52> ++ WL_O<51> WL_O<50> WL_O<49> WL_O<48> WL_O<47> WL_O<46> WL_O<45> WL_O<44> ++ WL_O<43> WL_O<42> WL_O<41> WL_O<40> WL_O<39> WL_O<38> WL_O<37> WL_O<36> ++ WL_O<35> WL_O<34> WL_O<33> WL_O<32> WL_O<31> WL_O<30> WL_O<29> WL_O<28> ++ WL_O<27> WL_O<26> WL_O<25> WL_O<24> WL_O<23> WL_O<22> WL_O<21> WL_O<20> ++ WL_O<19> WL_O<18> WL_O<17> WL_O<16> WL_O<15> WL_O<14> WL_O<13> WL_O<12> ++ WL_O<11> WL_O<10> WL_O<9> WL_O<8> WL_O<7> WL_O<6> WL_O<5> WL_O<4> WL_O<3> ++ WL_O<2> WL_O<1> WL_O<0> VDD VSS +XDEC11 ADDR_N_I<5> ADDR_N_I<4> CS_I CS00<3> VDD VSS / ++ RM_IHPSG13_256x32_c2_1P_DEC03 +XDEC00 ADDR_N_I<5> ADDR_N_I<4> CS_I CS00<0> VDD VSS / ++ RM_IHPSG13_256x32_c2_1P_DEC00 +XDEC01 ADDR_N_I<5> ADDR_N_I<4> CS_I CS00<1> VDD VSS / ++ RM_IHPSG13_256x32_c2_1P_DEC01 +XDEC10 ADDR_N_I<5> ADDR_N_I<4> CS_I CS00<2> VDD VSS / ++ RM_IHPSG13_256x32_c2_1P_DEC02 +XSEL<3> ADDR_N_I<3> ADDR_N_I<2> ADDR_N_I<1> ADDR_N_I<0> CS00<3> ECLK_H<3> ++ ECLK_H<4> ECLK_B<3> ECLK_B<4> WL_O<63> WL_O<62> WL_O<61> WL_O<60> WL_O<59> ++ WL_O<58> WL_O<57> WL_O<56> WL_O<55> WL_O<54> WL_O<53> WL_O<52> WL_O<51> ++ WL_O<50> WL_O<49> WL_O<48> VDD VSS / RM_IHPSG13_256x32_c2_1P_DEC04 +XSEL<2> ADDR_N_I<3> ADDR_N_I<2> ADDR_N_I<1> ADDR_N_I<0> CS00<2> ECLK_H<2> ++ ECLK_H<3> ECLK_B<2> ECLK_B<3> WL_O<47> WL_O<46> WL_O<45> WL_O<44> WL_O<43> ++ WL_O<42> WL_O<41> WL_O<40> WL_O<39> WL_O<38> WL_O<37> WL_O<36> WL_O<35> ++ WL_O<34> WL_O<33> WL_O<32> VDD VSS / RM_IHPSG13_256x32_c2_1P_DEC04 +XSEL<1> ADDR_N_I<3> ADDR_N_I<2> ADDR_N_I<1> ADDR_N_I<0> CS00<1> ECLK_H<1> ++ ECLK_H<2> ECLK_B<1> ECLK_B<2> WL_O<31> WL_O<30> WL_O<29> WL_O<28> WL_O<27> ++ WL_O<26> WL_O<25> WL_O<24> WL_O<23> WL_O<22> WL_O<21> WL_O<20> WL_O<19> ++ WL_O<18> WL_O<17> WL_O<16> VDD VSS / RM_IHPSG13_256x32_c2_1P_DEC04 +XSEL<0> ADDR_N_I<3> ADDR_N_I<2> ADDR_N_I<1> ADDR_N_I<0> CS00<0> ECLK_I ++ ECLK_H<1> ECLK_B<0> ECLK_B<1> WL_O<15> WL_O<14> WL_O<13> WL_O<12> WL_O<11> ++ WL_O<10> WL_O<9> WL_O<8> WL_O<7> WL_O<6> WL_O<5> WL_O<4> WL_O<3> WL_O<2> ++ WL_O<1> WL_O<0> VDD VSS / RM_IHPSG13_256x32_c2_1P_DEC04 +XL2<24> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<23> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<22> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<21> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<20> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<19> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<18> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<17> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<16> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<15> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<14> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<13> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<12> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<11> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<10> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<9> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<8> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<7> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<6> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<5> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<4> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<3> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<2> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<1> VDD VSS / RSC_IHPSG13_FILLCAP8 +.ENDS +.SUBCKT RM_IHPSG13_256x32_c2_1P_ROWREG6 ACLK_N_I ADDR_I<5> ADDR_I<4> ADDR_I<3> ADDR_I<2> ++ ADDR_I<1> ADDR_I<0> ADDR_N_O<5> ADDR_N_O<4> ADDR_N_O<3> ADDR_N_O<2> ++ ADDR_N_O<1> ADDR_N_O<0> BIST_ADDR_I<5> BIST_ADDR_I<4> BIST_ADDR_I<3> ++ BIST_ADDR_I<2> BIST_ADDR_I<1> BIST_ADDR_I<0> BIST_EN_I VDD VSS +XINV<5> q_int<5> qn_int<5> VDD VSS / RSC_IHPSG13_CINVX2 +XINV<4> q_int<4> qn_int<4> VDD VSS / RSC_IHPSG13_CINVX2 +XINV<3> q_int<3> qn_int<3> VDD VSS / RSC_IHPSG13_CINVX2 +XINV<2> q_int<2> qn_int<2> VDD VSS / RSC_IHPSG13_CINVX2 +XINV<1> q_int<1> qn_int<1> VDD VSS / RSC_IHPSG13_CINVX2 +XINV<0> q_int<0> qn_int<0> VDD VSS / RSC_IHPSG13_CINVX2 +XDRV<5> qn_int<5> ADDR_N_O<5> VDD VSS / RSC_IHPSG13_CINVX8 +XDRV<4> qn_int<4> ADDR_N_O<4> VDD VSS / RSC_IHPSG13_CINVX8 +XDRV<3> qn_int<3> ADDR_N_O<3> VDD VSS / RSC_IHPSG13_CINVX8 +XDRV<2> qn_int<2> ADDR_N_O<2> VDD VSS / RSC_IHPSG13_CINVX8 +XDRV<1> qn_int<1> ADDR_N_O<1> VDD VSS / RSC_IHPSG13_CINVX8 +XDRV<0> qn_int<0> ADDR_N_O<0> VDD VSS / RSC_IHPSG13_CINVX8 +XDFF<5> BIST_EN_I BIST_ADDR_I<5> ACLK_N_I ADDR_I<5> q_int<5> net2<0> VDD ++ VSS / RSC_IHPSG13_DFNQMX2IX1 +XDFF<4> BIST_EN_I BIST_ADDR_I<4> ACLK_N_I ADDR_I<4> q_int<4> net2<1> VDD ++ VSS / RSC_IHPSG13_DFNQMX2IX1 +XDFF<3> BIST_EN_I BIST_ADDR_I<3> ACLK_N_I ADDR_I<3> q_int<3> net2<2> VDD ++ VSS / RSC_IHPSG13_DFNQMX2IX1 +XDFF<2> BIST_EN_I BIST_ADDR_I<2> ACLK_N_I ADDR_I<2> q_int<2> net2<3> VDD ++ VSS / RSC_IHPSG13_DFNQMX2IX1 +XDFF<1> BIST_EN_I BIST_ADDR_I<1> ACLK_N_I ADDR_I<1> q_int<1> net2<4> VDD ++ VSS / RSC_IHPSG13_DFNQMX2IX1 +XDFF<0> BIST_EN_I BIST_ADDR_I<0> ACLK_N_I ADDR_I<0> q_int<0> net2<5> VDD ++ VSS / RSC_IHPSG13_DFNQMX2IX1 +XI11<12> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI11<11> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI11<10> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI11<9> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI11<8> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI11<7> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI11<6> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI11<5> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI11<4> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI11<3> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI11<2> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI11<1> VDD VSS / RSC_IHPSG13_FILLCAP8 +.ENDS + + +.SUBCKT RM_IHPSG13_256x32_c2_2P_COLUMN_pcell_0 A_BLC_BOT<1> A_BLC_BOT<0> A_BLC_TOP<1> A_BLC_TOP<0> A_BLT_BOT<1> A_BLT_BOT<0> A_BLT_TOP<1> A_BLT_TOP<0> A_LWL<63> A_LWL<62> A_LWL<61> A_LWL<60> A_LWL<59> A_LWL<58> A_LWL<57> A_LWL<56> A_LWL<55> A_LWL<54> A_LWL<53> A_LWL<52> A_LWL<51> A_LWL<50> A_LWL<49> A_LWL<48> A_LWL<47> A_LWL<46> A_LWL<45> A_LWL<44> A_LWL<43> A_LWL<42> A_LWL<41> A_LWL<40> A_LWL<39> A_LWL<38> A_LWL<37> A_LWL<36> A_LWL<35> A_LWL<34> A_LWL<33> A_LWL<32> A_LWL<31> A_LWL<30> A_LWL<29> A_LWL<28> A_LWL<27> A_LWL<26> A_LWL<25> A_LWL<24> A_LWL<23> A_LWL<22> A_LWL<21> A_LWL<20> A_LWL<19> A_LWL<18> A_LWL<17> A_LWL<16> A_LWL<15> A_LWL<14> A_LWL<13> A_LWL<12> A_LWL<11> A_LWL<10> A_LWL<9> A_LWL<8> A_LWL<7> A_LWL<6> A_LWL<5> A_LWL<4> A_LWL<3> A_LWL<2> A_LWL<1> A_LWL<0> A_RWL<63> A_RWL<62> A_RWL<61> A_RWL<60> A_RWL<59> A_RWL<58> A_RWL<57> A_RWL<56> A_RWL<55> A_RWL<54> A_RWL<53> A_RWL<52> A_RWL<51> A_RWL<50> A_RWL<49> A_RWL<48> A_RWL<47> A_RWL<46> A_RWL<45> A_RWL<44> A_RWL<43> A_RWL<42> A_RWL<41> A_RWL<40> A_RWL<39> A_RWL<38> A_RWL<37> A_RWL<36> A_RWL<35> A_RWL<34> A_RWL<33> A_RWL<32> A_RWL<31> A_RWL<30> A_RWL<29> A_RWL<28> A_RWL<27> A_RWL<26> A_RWL<25> A_RWL<24> A_RWL<23> A_RWL<22> A_RWL<21> A_RWL<20> A_RWL<19> A_RWL<18> A_RWL<17> A_RWL<16> A_RWL<15> A_RWL<14> A_RWL<13> A_RWL<12> A_RWL<11> A_RWL<10> A_RWL<9> A_RWL<8> A_RWL<7> A_RWL<6> A_RWL<5> A_RWL<4> A_RWL<3> A_RWL<2> A_RWL<1> A_RWL<0> B_BLC_BOT<1> B_BLC_BOT<0> B_BLC_TOP<1> B_BLC_TOP<0> B_BLT_BOT<1> B_BLT_BOT<0> B_BLT_TOP<1> B_BLT_TOP<0> B_LWL<63> B_LWL<62> B_LWL<61> B_LWL<60> B_LWL<59> B_LWL<58> B_LWL<57> B_LWL<56> B_LWL<55> B_LWL<54> B_LWL<53> B_LWL<52> B_LWL<51> B_LWL<50> B_LWL<49> B_LWL<48> B_LWL<47> B_LWL<46> B_LWL<45> B_LWL<44> B_LWL<43> B_LWL<42> B_LWL<41> B_LWL<40> B_LWL<39> B_LWL<38> B_LWL<37> B_LWL<36> B_LWL<35> B_LWL<34> B_LWL<33> B_LWL<32> B_LWL<31> B_LWL<30> B_LWL<29> B_LWL<28> B_LWL<27> B_LWL<26> B_LWL<25> B_LWL<24> B_LWL<23> B_LWL<22> B_LWL<21> B_LWL<20> B_LWL<19> B_LWL<18> B_LWL<17> B_LWL<16> B_LWL<15> B_LWL<14> B_LWL<13> B_LWL<12> B_LWL<11> B_LWL<10> B_LWL<9> B_LWL<8> B_LWL<7> B_LWL<6> B_LWL<5> B_LWL<4> B_LWL<3> B_LWL<2> B_LWL<1> B_LWL<0> B_RWL<63> B_RWL<62> B_RWL<61> B_RWL<60> B_RWL<59> B_RWL<58> B_RWL<57> B_RWL<56> B_RWL<55> B_RWL<54> B_RWL<53> B_RWL<52> B_RWL<51> B_RWL<50> B_RWL<49> B_RWL<48> B_RWL<47> B_RWL<46> B_RWL<45> B_RWL<44> B_RWL<43> B_RWL<42> B_RWL<41> B_RWL<40> B_RWL<39> B_RWL<38> B_RWL<37> B_RWL<36> B_RWL<35> B_RWL<34> B_RWL<33> B_RWL<32> B_RWL<31> B_RWL<30> B_RWL<29> B_RWL<28> B_RWL<27> B_RWL<26> B_RWL<25> B_RWL<24> B_RWL<23> B_RWL<22> B_RWL<21> B_RWL<20> B_RWL<19> B_RWL<18> B_RWL<17> B_RWL<16> B_RWL<15> B_RWL<14> B_RWL<13> B_RWL<12> B_RWL<11> B_RWL<10> B_RWL<9> B_RWL<8> B_RWL<7> B_RWL<6> B_RWL<5> B_RWL<4> B_RWL<3> B_RWL<2> B_RWL<1> B_RWL<0> VDD_CORE VSS +XRAM<4> A_BLC<5> A_BLC<4> A_BLC_TOP<1> A_BLC_TOP<0> A_BLT<5> A_BLT<4> A_BLT_TOP<1> A_BLT_TOP<0> A_LWL<63> A_LWL<62> A_LWL<61> A_LWL<60> A_LWL<59> A_LWL<58> A_LWL<57> A_LWL<56> A_LWL<55> A_LWL<54> A_LWL<53> A_LWL<52> A_LWL<51> A_LWL<50> A_LWL<49> A_LWL<48> A_RWL<63> A_RWL<62> A_RWL<61> A_RWL<60> A_RWL<59> A_RWL<58> A_RWL<57> A_RWL<56> A_RWL<55> A_RWL<54> A_RWL<53> A_RWL<52> A_RWL<51> A_RWL<50> A_RWL<49> A_RWL<48> B_BLC<5> B_BLC<4> B_BLC_TOP<1> B_BLC_TOP<0> B_BLT<5> B_BLT<4> B_BLT_TOP<1> B_BLT_TOP<0> B_LWL<63> B_LWL<62> B_LWL<61> B_LWL<60> B_LWL<59> B_LWL<58> B_LWL<57> B_LWL<56> B_LWL<55> B_LWL<54> B_LWL<53> B_LWL<52> B_LWL<51> B_LWL<50> B_LWL<49> B_LWL<48> B_RWL<63> B_RWL<62> B_RWL<61> B_RWL<60> B_RWL<59> B_RWL<58> B_RWL<57> B_RWL<56> B_RWL<55> B_RWL<54> B_RWL<53> B_RWL<52> B_RWL<51> B_RWL<50> B_RWL<49> B_RWL<48> VDD_CORE VSS / RM_IHPSG13_256x32_c2_2P_BITKIT_16x2_SRAM +XRAM<3> A_BLC<3> A_BLC<2> A_BLC<5> A_BLC<4> A_BLT<3> A_BLT<2> A_BLT<5> A_BLT<4> A_LWL<47> A_LWL<46> A_LWL<45> A_LWL<44> A_LWL<43> A_LWL<42> A_LWL<41> A_LWL<40> A_LWL<39> A_LWL<38> A_LWL<37> A_LWL<36> A_LWL<35> A_LWL<34> A_LWL<33> A_LWL<32> A_RWL<47> A_RWL<46> A_RWL<45> A_RWL<44> A_RWL<43> A_RWL<42> A_RWL<41> A_RWL<40> A_RWL<39> A_RWL<38> A_RWL<37> A_RWL<36> A_RWL<35> A_RWL<34> A_RWL<33> A_RWL<32> B_BLC<3> B_BLC<2> B_BLC<5> B_BLC<4> B_BLT<3> B_BLT<2> B_BLT<5> B_BLT<4> B_LWL<47> B_LWL<46> B_LWL<45> B_LWL<44> B_LWL<43> B_LWL<42> B_LWL<41> B_LWL<40> B_LWL<39> B_LWL<38> B_LWL<37> B_LWL<36> B_LWL<35> B_LWL<34> B_LWL<33> B_LWL<32> B_RWL<47> B_RWL<46> B_RWL<45> B_RWL<44> B_RWL<43> B_RWL<42> B_RWL<41> B_RWL<40> B_RWL<39> B_RWL<38> B_RWL<37> B_RWL<36> B_RWL<35> B_RWL<34> B_RWL<33> B_RWL<32> VDD_CORE VSS / RM_IHPSG13_256x32_c2_2P_BITKIT_16x2_SRAM +XRAM<2> A_BLC<1> A_BLC<0> A_BLC<3> A_BLC<2> A_BLT<1> A_BLT<0> A_BLT<3> A_BLT<2> A_LWL<31> A_LWL<30> A_LWL<29> A_LWL<28> A_LWL<27> A_LWL<26> A_LWL<25> A_LWL<24> A_LWL<23> A_LWL<22> A_LWL<21> A_LWL<20> A_LWL<19> A_LWL<18> A_LWL<17> A_LWL<16> A_RWL<31> A_RWL<30> A_RWL<29> A_RWL<28> A_RWL<27> A_RWL<26> A_RWL<25> A_RWL<24> A_RWL<23> A_RWL<22> A_RWL<21> A_RWL<20> A_RWL<19> A_RWL<18> A_RWL<17> A_RWL<16> B_BLC<1> B_BLC<0> B_BLC<3> B_BLC<2> B_BLT<1> B_BLT<0> B_BLT<3> B_BLT<2> B_LWL<31> B_LWL<30> B_LWL<29> B_LWL<28> B_LWL<27> B_LWL<26> B_LWL<25> B_LWL<24> B_LWL<23> B_LWL<22> B_LWL<21> B_LWL<20> B_LWL<19> B_LWL<18> B_LWL<17> B_LWL<16> B_RWL<31> B_RWL<30> B_RWL<29> B_RWL<28> B_RWL<27> B_RWL<26> B_RWL<25> B_RWL<24> B_RWL<23> B_RWL<22> B_RWL<21> B_RWL<20> B_RWL<19> B_RWL<18> B_RWL<17> B_RWL<16> VDD_CORE VSS / RM_IHPSG13_256x32_c2_2P_BITKIT_16x2_SRAM +XRAM<1> A_BLC_BOT<1> A_BLC_BOT<0> A_BLC<1> A_BLC<0> A_BLT_BOT<1> A_BLT_BOT<0> A_BLT<1> A_BLT<0> A_LWL<15> A_LWL<14> A_LWL<13> A_LWL<12> A_LWL<11> A_LWL<10> A_LWL<9> A_LWL<8> A_LWL<7> A_LWL<6> A_LWL<5> A_LWL<4> A_LWL<3> A_LWL<2> A_LWL<1> A_LWL<0> A_RWL<15> A_RWL<14> A_RWL<13> A_RWL<12> A_RWL<11> A_RWL<10> A_RWL<9> A_RWL<8> A_RWL<7> A_RWL<6> A_RWL<5> A_RWL<4> A_RWL<3> A_RWL<2> A_RWL<1> A_RWL<0> B_BLC_BOT<1> B_BLC_BOT<0> B_BLC<1> B_BLC<0> B_BLT_BOT<1> B_BLT_BOT<0> B_BLT<1> B_BLT<0> B_LWL<15> B_LWL<14> B_LWL<13> B_LWL<12> B_LWL<11> B_LWL<10> B_LWL<9> B_LWL<8> B_LWL<7> B_LWL<6> B_LWL<5> B_LWL<4> B_LWL<3> B_LWL<2> B_LWL<1> B_LWL<0> B_RWL<15> B_RWL<14> B_RWL<13> B_RWL<12> B_RWL<11> B_RWL<10> B_RWL<9> B_RWL<8> B_RWL<7> B_RWL<6> B_RWL<5> B_RWL<4> B_RWL<3> B_RWL<2> B_RWL<1> B_RWL<0> VDD_CORE VSS / RM_IHPSG13_256x32_c2_2P_BITKIT_16x2_SRAM +XEDGE<1> A_BLC_TOP<1> A_BLC_TOP<0> A_BLT_TOP<1> A_BLT_TOP<0> B_BLC_TOP<1> B_BLC_TOP<0> B_BLT_TOP<1> B_BLT_TOP<0> VDD_CORE VSS / RM_IHPSG13_256x32_c2_2P_BITKIT_16x2_EDGE_TB +XEDGE<0> A_BLC_BOT<1> A_BLC_BOT<0> A_BLT_BOT<1> A_BLT_BOT<0> B_BLC_BOT<1> B_BLC_BOT<0> B_BLT_BOT<1> B_BLT_BOT<0> VDD_CORE VSS / RM_IHPSG13_256x32_c2_2P_BITKIT_16x2_EDGE_TB +.ENDS + + + + +.SUBCKT RM_IHPSG13_256x32_c2_2P_MATRIX_pcell_1 A_BLC<63> A_BLC<62> A_BLC<61> A_BLC<60> A_BLC<59> A_BLC<58> A_BLC<57> A_BLC<56> A_BLC<55> A_BLC<54> A_BLC<53> A_BLC<52> A_BLC<51> A_BLC<50> A_BLC<49> A_BLC<48> A_BLC<47> A_BLC<46> A_BLC<45> A_BLC<44> A_BLC<43> A_BLC<42> A_BLC<41> A_BLC<40> A_BLC<39> A_BLC<38> A_BLC<37> A_BLC<36> A_BLC<35> A_BLC<34> A_BLC<33> A_BLC<32> A_BLC<31> A_BLC<30> A_BLC<29> A_BLC<28> A_BLC<27> A_BLC<26> A_BLC<25> A_BLC<24> A_BLC<23> A_BLC<22> A_BLC<21> A_BLC<20> A_BLC<19> A_BLC<18> A_BLC<17> A_BLC<16> A_BLC<15> A_BLC<14> A_BLC<13> A_BLC<12> A_BLC<11> A_BLC<10> A_BLC<9> A_BLC<8> A_BLC<7> A_BLC<6> A_BLC<5> A_BLC<4> A_BLC<3> A_BLC<2> A_BLC<1> A_BLC<0> A_BLT<63> A_BLT<62> A_BLT<61> A_BLT<60> A_BLT<59> A_BLT<58> A_BLT<57> A_BLT<56> A_BLT<55> A_BLT<54> A_BLT<53> A_BLT<52> A_BLT<51> A_BLT<50> A_BLT<49> A_BLT<48> A_BLT<47> A_BLT<46> A_BLT<45> A_BLT<44> A_BLT<43> A_BLT<42> A_BLT<41> A_BLT<40> A_BLT<39> A_BLT<38> A_BLT<37> A_BLT<36> A_BLT<35> A_BLT<34> A_BLT<33> A_BLT<32> A_BLT<31> A_BLT<30> A_BLT<29> A_BLT<28> A_BLT<27> A_BLT<26> A_BLT<25> A_BLT<24> A_BLT<23> A_BLT<22> A_BLT<21> A_BLT<20> A_BLT<19> A_BLT<18> A_BLT<17> A_BLT<16> A_BLT<15> A_BLT<14> A_BLT<13> A_BLT<12> A_BLT<11> A_BLT<10> A_BLT<9> A_BLT<8> A_BLT<7> A_BLT<6> A_BLT<5> A_BLT<4> A_BLT<3> A_BLT<2> A_BLT<1> A_BLT<0> A_WL<63> A_WL<62> A_WL<61> A_WL<60> A_WL<59> A_WL<58> A_WL<57> A_WL<56> A_WL<55> A_WL<54> A_WL<53> A_WL<52> A_WL<51> A_WL<50> A_WL<49> A_WL<48> A_WL<47> A_WL<46> A_WL<45> A_WL<44> A_WL<43> A_WL<42> A_WL<41> A_WL<40> A_WL<39> A_WL<38> A_WL<37> A_WL<36> A_WL<35> A_WL<34> A_WL<33> A_WL<32> A_WL<31> A_WL<30> A_WL<29> A_WL<28> A_WL<27> A_WL<26> A_WL<25> A_WL<24> A_WL<23> A_WL<22> A_WL<21> A_WL<20> A_WL<19> A_WL<18> A_WL<17> A_WL<16> A_WL<15> A_WL<14> A_WL<13> A_WL<12> A_WL<11> A_WL<10> A_WL<9> A_WL<8> A_WL<7> A_WL<6> A_WL<5> A_WL<4> A_WL<3> A_WL<2> A_WL<1> A_WL<0> B_BLC<63> B_BLC<62> B_BLC<61> B_BLC<60> B_BLC<59> B_BLC<58> B_BLC<57> B_BLC<56> B_BLC<55> B_BLC<54> B_BLC<53> B_BLC<52> B_BLC<51> B_BLC<50> B_BLC<49> B_BLC<48> B_BLC<47> B_BLC<46> B_BLC<45> B_BLC<44> B_BLC<43> B_BLC<42> B_BLC<41> B_BLC<40> B_BLC<39> B_BLC<38> B_BLC<37> B_BLC<36> B_BLC<35> B_BLC<34> B_BLC<33> B_BLC<32> B_BLC<31> B_BLC<30> B_BLC<29> B_BLC<28> B_BLC<27> B_BLC<26> B_BLC<25> B_BLC<24> B_BLC<23> B_BLC<22> B_BLC<21> B_BLC<20> B_BLC<19> B_BLC<18> B_BLC<17> B_BLC<16> B_BLC<15> B_BLC<14> B_BLC<13> B_BLC<12> B_BLC<11> B_BLC<10> B_BLC<9> B_BLC<8> B_BLC<7> B_BLC<6> B_BLC<5> B_BLC<4> B_BLC<3> B_BLC<2> B_BLC<1> B_BLC<0> B_BLT<63> B_BLT<62> B_BLT<61> B_BLT<60> B_BLT<59> B_BLT<58> B_BLT<57> B_BLT<56> B_BLT<55> B_BLT<54> B_BLT<53> B_BLT<52> B_BLT<51> B_BLT<50> B_BLT<49> B_BLT<48> B_BLT<47> B_BLT<46> B_BLT<45> B_BLT<44> B_BLT<43> B_BLT<42> B_BLT<41> B_BLT<40> B_BLT<39> B_BLT<38> B_BLT<37> B_BLT<36> B_BLT<35> B_BLT<34> B_BLT<33> B_BLT<32> B_BLT<31> B_BLT<30> B_BLT<29> B_BLT<28> B_BLT<27> B_BLT<26> B_BLT<25> B_BLT<24> B_BLT<23> B_BLT<22> B_BLT<21> B_BLT<20> B_BLT<19> B_BLT<18> B_BLT<17> B_BLT<16> B_BLT<15> B_BLT<14> B_BLT<13> B_BLT<12> B_BLT<11> B_BLT<10> B_BLT<9> B_BLT<8> B_BLT<7> B_BLT<6> B_BLT<5> B_BLT<4> B_BLT<3> B_BLT<2> B_BLT<1> B_BLT<0> B_WL<63> B_WL<62> B_WL<61> B_WL<60> B_WL<59> B_WL<58> B_WL<57> B_WL<56> B_WL<55> B_WL<54> B_WL<53> B_WL<52> B_WL<51> B_WL<50> B_WL<49> B_WL<48> B_WL<47> B_WL<46> B_WL<45> B_WL<44> B_WL<43> B_WL<42> B_WL<41> B_WL<40> B_WL<39> B_WL<38> B_WL<37> B_WL<36> B_WL<35> B_WL<34> B_WL<33> B_WL<32> B_WL<31> B_WL<30> B_WL<29> B_WL<28> B_WL<27> B_WL<26> B_WL<25> B_WL<24> B_WL<23> B_WL<22> B_WL<21> B_WL<20> B_WL<19> B_WL<18> B_WL<17> B_WL<16> B_WL<15> B_WL<14> B_WL<13> B_WL<12> B_WL<11> B_WL<10> B_WL<9> B_WL<8> B_WL<7> B_WL<6> B_WL<5> B_WL<4> B_WL<3> B_WL<2> B_WL<1> B_WL<0> VDD_CORE VSS +XCORNER<3> VDD_CORE VSS / RM_IHPSG13_256x32_c2_2P_BITKIT_16x2_CORNER +XCORNER<2> VDD_CORE VSS / RM_IHPSG13_256x32_c2_2P_BITKIT_16x2_CORNER +XCORNER<1> VDD_CORE VSS / RM_IHPSG13_256x32_c2_2P_BITKIT_16x2_CORNER +XCORNER<0> VDD_CORE VSS / RM_IHPSG13_256x32_c2_2P_BITKIT_16x2_CORNER +XRAMEDGE_L<3> A_WL<63> A_WL<62> A_WL<61> A_WL<60> A_WL<59> A_WL<58> A_WL<57> A_WL<56> A_WL<55> A_WL<54> A_WL<53> A_WL<52> A_WL<51> A_WL<50> A_WL<49> A_WL<48> B_WL<63> B_WL<62> B_WL<61> B_WL<60> B_WL<59> B_WL<58> B_WL<57> B_WL<56> B_WL<55> B_WL<54> B_WL<53> B_WL<52> B_WL<51> B_WL<50> B_WL<49> B_WL<48> VDD_CORE VSS / RM_IHPSG13_256x32_c2_2P_BITKIT_16x2_EDGE_LR +XRAMEDGE_L<2> A_WL<47> A_WL<46> A_WL<45> A_WL<44> A_WL<43> A_WL<42> A_WL<41> A_WL<40> A_WL<39> A_WL<38> A_WL<37> A_WL<36> A_WL<35> A_WL<34> A_WL<33> A_WL<32> B_WL<47> B_WL<46> B_WL<45> B_WL<44> B_WL<43> B_WL<42> B_WL<41> B_WL<40> B_WL<39> B_WL<38> B_WL<37> B_WL<36> B_WL<35> B_WL<34> B_WL<33> B_WL<32> VDD_CORE VSS / RM_IHPSG13_256x32_c2_2P_BITKIT_16x2_EDGE_LR +XRAMEDGE_L<1> A_WL<31> A_WL<30> A_WL<29> A_WL<28> A_WL<27> A_WL<26> A_WL<25> A_WL<24> A_WL<23> A_WL<22> A_WL<21> A_WL<20> A_WL<19> A_WL<18> A_WL<17> A_WL<16> B_WL<31> B_WL<30> B_WL<29> B_WL<28> B_WL<27> B_WL<26> B_WL<25> B_WL<24> B_WL<23> B_WL<22> B_WL<21> B_WL<20> B_WL<19> B_WL<18> B_WL<17> B_WL<16> VDD_CORE VSS / RM_IHPSG13_256x32_c2_2P_BITKIT_16x2_EDGE_LR +XRAMEDGE_L<0> A_WL<15> A_WL<14> A_WL<13> A_WL<12> A_WL<11> A_WL<10> A_WL<9> A_WL<8> A_WL<7> A_WL<6> A_WL<5> A_WL<4> A_WL<3> A_WL<2> A_WL<1> A_WL<0> B_WL<15> B_WL<14> B_WL<13> B_WL<12> B_WL<11> B_WL<10> B_WL<9> B_WL<8> B_WL<7> B_WL<6> B_WL<5> B_WL<4> B_WL<3> B_WL<2> B_WL<1> B_WL<0> VDD_CORE VSS / RM_IHPSG13_256x32_c2_2P_BITKIT_16x2_EDGE_LR +XRAMEDGE_R<3> A_IWL<2047> A_IWL<2046> A_IWL<2045> A_IWL<2044> A_IWL<2043> A_IWL<2042> A_IWL<2041> A_IWL<2040> A_IWL<2039> A_IWL<2038> A_IWL<2037> A_IWL<2036> A_IWL<2035> A_IWL<2034> A_IWL<2033> A_IWL<2032> B_IWL<2047> B_IWL<2046> B_IWL<2045> B_IWL<2044> B_IWL<2043> B_IWL<2042> B_IWL<2041> B_IWL<2040> B_IWL<2039> B_IWL<2038> B_IWL<2037> B_IWL<2036> B_IWL<2035> B_IWL<2034> B_IWL<2033> B_IWL<2032> VDD_CORE VSS / RM_IHPSG13_256x32_c2_2P_BITKIT_16x2_EDGE_LR +XRAMEDGE_R<2> A_IWL<2031> A_IWL<2030> A_IWL<2029> A_IWL<2028> A_IWL<2027> A_IWL<2026> A_IWL<2025> A_IWL<2024> A_IWL<2023> A_IWL<2022> A_IWL<2021> A_IWL<2020> A_IWL<2019> A_IWL<2018> A_IWL<2017> A_IWL<2016> B_IWL<2031> B_IWL<2030> B_IWL<2029> B_IWL<2028> B_IWL<2027> B_IWL<2026> B_IWL<2025> B_IWL<2024> B_IWL<2023> B_IWL<2022> B_IWL<2021> B_IWL<2020> B_IWL<2019> B_IWL<2018> B_IWL<2017> B_IWL<2016> VDD_CORE VSS / RM_IHPSG13_256x32_c2_2P_BITKIT_16x2_EDGE_LR +XRAMEDGE_R<1> A_IWL<2015> A_IWL<2014> A_IWL<2013> A_IWL<2012> A_IWL<2011> A_IWL<2010> A_IWL<2009> A_IWL<2008> A_IWL<2007> A_IWL<2006> A_IWL<2005> A_IWL<2004> A_IWL<2003> A_IWL<2002> A_IWL<2001> A_IWL<2000> B_IWL<2015> B_IWL<2014> B_IWL<2013> B_IWL<2012> B_IWL<2011> B_IWL<2010> B_IWL<2009> B_IWL<2008> B_IWL<2007> B_IWL<2006> B_IWL<2005> B_IWL<2004> B_IWL<2003> B_IWL<2002> B_IWL<2001> B_IWL<2000> VDD_CORE VSS / RM_IHPSG13_256x32_c2_2P_BITKIT_16x2_EDGE_LR +XRAMEDGE_R<0> A_IWL<1999> A_IWL<1998> A_IWL<1997> A_IWL<1996> A_IWL<1995> A_IWL<1994> A_IWL<1993> A_IWL<1992> A_IWL<1991> A_IWL<1990> A_IWL<1989> A_IWL<1988> A_IWL<1987> A_IWL<1986> A_IWL<1985> A_IWL<1984> B_IWL<1999> B_IWL<1998> B_IWL<1997> B_IWL<1996> B_IWL<1995> B_IWL<1994> B_IWL<1993> B_IWL<1992> B_IWL<1991> B_IWL<1990> B_IWL<1989> B_IWL<1988> B_IWL<1987> B_IWL<1986> B_IWL<1985> B_IWL<1984> VDD_CORE VSS / RM_IHPSG13_256x32_c2_2P_BITKIT_16x2_EDGE_LR +XCOL<31> A_BLC<63> A_BLC<62> A_BLC_TOP<63> A_BLC_TOP<62> A_BLT<63> A_BLT<62> A_BLT_TOP<63> A_BLT_TOP<62> A_IWL<1983> A_IWL<1982> A_IWL<1981> A_IWL<1980> A_IWL<1979> A_IWL<1978> A_IWL<1977> A_IWL<1976> A_IWL<1975> A_IWL<1974> A_IWL<1973> A_IWL<1972> A_IWL<1971> A_IWL<1970> A_IWL<1969> A_IWL<1968> A_IWL<1967> A_IWL<1966> A_IWL<1965> A_IWL<1964> A_IWL<1963> A_IWL<1962> A_IWL<1961> A_IWL<1960> A_IWL<1959> A_IWL<1958> A_IWL<1957> A_IWL<1956> A_IWL<1955> A_IWL<1954> A_IWL<1953> A_IWL<1952> A_IWL<1951> A_IWL<1950> A_IWL<1949> A_IWL<1948> A_IWL<1947> A_IWL<1946> A_IWL<1945> A_IWL<1944> A_IWL<1943> A_IWL<1942> A_IWL<1941> A_IWL<1940> A_IWL<1939> A_IWL<1938> A_IWL<1937> A_IWL<1936> A_IWL<1935> A_IWL<1934> A_IWL<1933> A_IWL<1932> A_IWL<1931> A_IWL<1930> A_IWL<1929> A_IWL<1928> A_IWL<1927> A_IWL<1926> A_IWL<1925> A_IWL<1924> A_IWL<1923> A_IWL<1922> A_IWL<1921> A_IWL<1920> A_IWL<2047> A_IWL<2046> A_IWL<2045> A_IWL<2044> A_IWL<2043> A_IWL<2042> A_IWL<2041> A_IWL<2040> A_IWL<2039> A_IWL<2038> A_IWL<2037> A_IWL<2036> A_IWL<2035> A_IWL<2034> A_IWL<2033> A_IWL<2032> A_IWL<2031> A_IWL<2030> A_IWL<2029> A_IWL<2028> A_IWL<2027> A_IWL<2026> A_IWL<2025> A_IWL<2024> A_IWL<2023> A_IWL<2022> A_IWL<2021> A_IWL<2020> A_IWL<2019> A_IWL<2018> A_IWL<2017> A_IWL<2016> A_IWL<2015> A_IWL<2014> A_IWL<2013> A_IWL<2012> A_IWL<2011> A_IWL<2010> A_IWL<2009> A_IWL<2008> A_IWL<2007> A_IWL<2006> A_IWL<2005> A_IWL<2004> A_IWL<2003> A_IWL<2002> A_IWL<2001> A_IWL<2000> A_IWL<1999> A_IWL<1998> A_IWL<1997> A_IWL<1996> A_IWL<1995> A_IWL<1994> A_IWL<1993> A_IWL<1992> A_IWL<1991> A_IWL<1990> A_IWL<1989> A_IWL<1988> A_IWL<1987> A_IWL<1986> A_IWL<1985> A_IWL<1984> B_BLC<63> B_BLC<62> B_BLC_TOP<63> B_BLC_TOP<62> B_BLT<63> B_BLT<62> B_BLT_TOP<63> B_BLT_TOP<62> B_IWL<1983> B_IWL<1982> B_IWL<1981> B_IWL<1980> B_IWL<1979> B_IWL<1978> B_IWL<1977> B_IWL<1976> B_IWL<1975> B_IWL<1974> B_IWL<1973> B_IWL<1972> B_IWL<1971> B_IWL<1970> B_IWL<1969> B_IWL<1968> B_IWL<1967> B_IWL<1966> B_IWL<1965> B_IWL<1964> B_IWL<1963> B_IWL<1962> B_IWL<1961> B_IWL<1960> B_IWL<1959> B_IWL<1958> B_IWL<1957> B_IWL<1956> B_IWL<1955> B_IWL<1954> B_IWL<1953> B_IWL<1952> B_IWL<1951> B_IWL<1950> B_IWL<1949> B_IWL<1948> B_IWL<1947> B_IWL<1946> B_IWL<1945> B_IWL<1944> B_IWL<1943> B_IWL<1942> B_IWL<1941> B_IWL<1940> B_IWL<1939> B_IWL<1938> B_IWL<1937> B_IWL<1936> B_IWL<1935> B_IWL<1934> B_IWL<1933> B_IWL<1932> B_IWL<1931> B_IWL<1930> B_IWL<1929> B_IWL<1928> B_IWL<1927> B_IWL<1926> B_IWL<1925> B_IWL<1924> B_IWL<1923> B_IWL<1922> B_IWL<1921> B_IWL<1920> B_IWL<2047> B_IWL<2046> B_IWL<2045> B_IWL<2044> B_IWL<2043> B_IWL<2042> B_IWL<2041> B_IWL<2040> B_IWL<2039> B_IWL<2038> B_IWL<2037> B_IWL<2036> B_IWL<2035> B_IWL<2034> B_IWL<2033> B_IWL<2032> B_IWL<2031> B_IWL<2030> B_IWL<2029> B_IWL<2028> B_IWL<2027> B_IWL<2026> B_IWL<2025> B_IWL<2024> B_IWL<2023> B_IWL<2022> B_IWL<2021> B_IWL<2020> B_IWL<2019> B_IWL<2018> B_IWL<2017> B_IWL<2016> B_IWL<2015> B_IWL<2014> B_IWL<2013> B_IWL<2012> B_IWL<2011> B_IWL<2010> B_IWL<2009> B_IWL<2008> B_IWL<2007> B_IWL<2006> B_IWL<2005> B_IWL<2004> B_IWL<2003> B_IWL<2002> B_IWL<2001> B_IWL<2000> B_IWL<1999> B_IWL<1998> B_IWL<1997> B_IWL<1996> B_IWL<1995> B_IWL<1994> B_IWL<1993> B_IWL<1992> B_IWL<1991> B_IWL<1990> B_IWL<1989> B_IWL<1988> B_IWL<1987> B_IWL<1986> B_IWL<1985> B_IWL<1984> VDD_CORE VSS / RM_IHPSG13_256x32_c2_2P_COLUMN_pcell_0 +XCOL<30> A_BLC<61> A_BLC<60> A_BLC_TOP<61> A_BLC_TOP<60> A_BLT<61> A_BLT<60> A_BLT_TOP<61> A_BLT_TOP<60> A_IWL<1919> A_IWL<1918> A_IWL<1917> A_IWL<1916> A_IWL<1915> A_IWL<1914> A_IWL<1913> A_IWL<1912> A_IWL<1911> A_IWL<1910> A_IWL<1909> A_IWL<1908> A_IWL<1907> A_IWL<1906> A_IWL<1905> A_IWL<1904> A_IWL<1903> A_IWL<1902> A_IWL<1901> A_IWL<1900> A_IWL<1899> A_IWL<1898> A_IWL<1897> A_IWL<1896> A_IWL<1895> A_IWL<1894> A_IWL<1893> A_IWL<1892> A_IWL<1891> A_IWL<1890> A_IWL<1889> A_IWL<1888> A_IWL<1887> A_IWL<1886> A_IWL<1885> A_IWL<1884> A_IWL<1883> A_IWL<1882> A_IWL<1881> A_IWL<1880> A_IWL<1879> A_IWL<1878> A_IWL<1877> A_IWL<1876> A_IWL<1875> A_IWL<1874> A_IWL<1873> A_IWL<1872> A_IWL<1871> A_IWL<1870> A_IWL<1869> A_IWL<1868> A_IWL<1867> A_IWL<1866> A_IWL<1865> A_IWL<1864> A_IWL<1863> A_IWL<1862> A_IWL<1861> A_IWL<1860> A_IWL<1859> A_IWL<1858> A_IWL<1857> A_IWL<1856> A_IWL<1983> A_IWL<1982> A_IWL<1981> A_IWL<1980> A_IWL<1979> A_IWL<1978> A_IWL<1977> A_IWL<1976> A_IWL<1975> A_IWL<1974> A_IWL<1973> A_IWL<1972> A_IWL<1971> A_IWL<1970> A_IWL<1969> A_IWL<1968> A_IWL<1967> A_IWL<1966> A_IWL<1965> A_IWL<1964> A_IWL<1963> A_IWL<1962> A_IWL<1961> A_IWL<1960> A_IWL<1959> A_IWL<1958> A_IWL<1957> A_IWL<1956> A_IWL<1955> A_IWL<1954> A_IWL<1953> A_IWL<1952> A_IWL<1951> A_IWL<1950> A_IWL<1949> A_IWL<1948> A_IWL<1947> A_IWL<1946> A_IWL<1945> A_IWL<1944> A_IWL<1943> A_IWL<1942> A_IWL<1941> A_IWL<1940> A_IWL<1939> A_IWL<1938> A_IWL<1937> A_IWL<1936> A_IWL<1935> A_IWL<1934> A_IWL<1933> A_IWL<1932> A_IWL<1931> A_IWL<1930> A_IWL<1929> A_IWL<1928> A_IWL<1927> A_IWL<1926> A_IWL<1925> A_IWL<1924> A_IWL<1923> A_IWL<1922> A_IWL<1921> A_IWL<1920> B_BLC<61> B_BLC<60> B_BLC_TOP<61> B_BLC_TOP<60> B_BLT<61> B_BLT<60> B_BLT_TOP<61> B_BLT_TOP<60> B_IWL<1919> B_IWL<1918> B_IWL<1917> B_IWL<1916> B_IWL<1915> B_IWL<1914> B_IWL<1913> B_IWL<1912> B_IWL<1911> B_IWL<1910> B_IWL<1909> B_IWL<1908> B_IWL<1907> B_IWL<1906> B_IWL<1905> B_IWL<1904> B_IWL<1903> B_IWL<1902> B_IWL<1901> B_IWL<1900> B_IWL<1899> B_IWL<1898> B_IWL<1897> B_IWL<1896> B_IWL<1895> B_IWL<1894> B_IWL<1893> B_IWL<1892> B_IWL<1891> B_IWL<1890> B_IWL<1889> B_IWL<1888> B_IWL<1887> B_IWL<1886> B_IWL<1885> B_IWL<1884> B_IWL<1883> B_IWL<1882> B_IWL<1881> B_IWL<1880> B_IWL<1879> B_IWL<1878> B_IWL<1877> B_IWL<1876> B_IWL<1875> B_IWL<1874> B_IWL<1873> B_IWL<1872> B_IWL<1871> B_IWL<1870> B_IWL<1869> B_IWL<1868> B_IWL<1867> B_IWL<1866> B_IWL<1865> B_IWL<1864> B_IWL<1863> B_IWL<1862> B_IWL<1861> B_IWL<1860> B_IWL<1859> B_IWL<1858> B_IWL<1857> B_IWL<1856> B_IWL<1983> B_IWL<1982> B_IWL<1981> B_IWL<1980> B_IWL<1979> B_IWL<1978> B_IWL<1977> B_IWL<1976> B_IWL<1975> B_IWL<1974> B_IWL<1973> B_IWL<1972> B_IWL<1971> B_IWL<1970> B_IWL<1969> B_IWL<1968> B_IWL<1967> B_IWL<1966> B_IWL<1965> B_IWL<1964> B_IWL<1963> B_IWL<1962> B_IWL<1961> B_IWL<1960> B_IWL<1959> B_IWL<1958> B_IWL<1957> B_IWL<1956> B_IWL<1955> B_IWL<1954> B_IWL<1953> B_IWL<1952> B_IWL<1951> B_IWL<1950> B_IWL<1949> B_IWL<1948> B_IWL<1947> B_IWL<1946> B_IWL<1945> B_IWL<1944> B_IWL<1943> B_IWL<1942> B_IWL<1941> B_IWL<1940> B_IWL<1939> B_IWL<1938> B_IWL<1937> B_IWL<1936> B_IWL<1935> B_IWL<1934> B_IWL<1933> B_IWL<1932> B_IWL<1931> B_IWL<1930> B_IWL<1929> B_IWL<1928> B_IWL<1927> B_IWL<1926> B_IWL<1925> B_IWL<1924> B_IWL<1923> B_IWL<1922> B_IWL<1921> B_IWL<1920> VDD_CORE VSS / RM_IHPSG13_256x32_c2_2P_COLUMN_pcell_0 +XCOL<29> A_BLC<59> A_BLC<58> A_BLC_TOP<59> A_BLC_TOP<58> A_BLT<59> A_BLT<58> A_BLT_TOP<59> A_BLT_TOP<58> A_IWL<1855> A_IWL<1854> A_IWL<1853> A_IWL<1852> A_IWL<1851> A_IWL<1850> A_IWL<1849> A_IWL<1848> A_IWL<1847> A_IWL<1846> A_IWL<1845> A_IWL<1844> A_IWL<1843> A_IWL<1842> A_IWL<1841> A_IWL<1840> A_IWL<1839> A_IWL<1838> A_IWL<1837> A_IWL<1836> A_IWL<1835> A_IWL<1834> A_IWL<1833> A_IWL<1832> A_IWL<1831> A_IWL<1830> A_IWL<1829> A_IWL<1828> A_IWL<1827> A_IWL<1826> A_IWL<1825> A_IWL<1824> A_IWL<1823> A_IWL<1822> A_IWL<1821> A_IWL<1820> A_IWL<1819> A_IWL<1818> A_IWL<1817> A_IWL<1816> A_IWL<1815> A_IWL<1814> A_IWL<1813> A_IWL<1812> A_IWL<1811> A_IWL<1810> A_IWL<1809> A_IWL<1808> A_IWL<1807> A_IWL<1806> A_IWL<1805> A_IWL<1804> A_IWL<1803> A_IWL<1802> A_IWL<1801> A_IWL<1800> A_IWL<1799> A_IWL<1798> A_IWL<1797> A_IWL<1796> A_IWL<1795> A_IWL<1794> A_IWL<1793> A_IWL<1792> A_IWL<1919> A_IWL<1918> A_IWL<1917> A_IWL<1916> A_IWL<1915> A_IWL<1914> A_IWL<1913> A_IWL<1912> A_IWL<1911> A_IWL<1910> A_IWL<1909> A_IWL<1908> A_IWL<1907> A_IWL<1906> A_IWL<1905> A_IWL<1904> A_IWL<1903> A_IWL<1902> A_IWL<1901> A_IWL<1900> A_IWL<1899> A_IWL<1898> A_IWL<1897> A_IWL<1896> A_IWL<1895> A_IWL<1894> A_IWL<1893> A_IWL<1892> A_IWL<1891> A_IWL<1890> A_IWL<1889> A_IWL<1888> A_IWL<1887> A_IWL<1886> A_IWL<1885> A_IWL<1884> A_IWL<1883> A_IWL<1882> A_IWL<1881> A_IWL<1880> A_IWL<1879> A_IWL<1878> A_IWL<1877> A_IWL<1876> A_IWL<1875> A_IWL<1874> A_IWL<1873> A_IWL<1872> A_IWL<1871> A_IWL<1870> A_IWL<1869> A_IWL<1868> A_IWL<1867> A_IWL<1866> A_IWL<1865> A_IWL<1864> A_IWL<1863> A_IWL<1862> A_IWL<1861> A_IWL<1860> A_IWL<1859> A_IWL<1858> A_IWL<1857> A_IWL<1856> B_BLC<59> B_BLC<58> B_BLC_TOP<59> B_BLC_TOP<58> B_BLT<59> B_BLT<58> B_BLT_TOP<59> B_BLT_TOP<58> B_IWL<1855> B_IWL<1854> B_IWL<1853> B_IWL<1852> B_IWL<1851> B_IWL<1850> B_IWL<1849> B_IWL<1848> B_IWL<1847> B_IWL<1846> B_IWL<1845> B_IWL<1844> B_IWL<1843> B_IWL<1842> B_IWL<1841> B_IWL<1840> B_IWL<1839> B_IWL<1838> B_IWL<1837> B_IWL<1836> B_IWL<1835> B_IWL<1834> B_IWL<1833> B_IWL<1832> B_IWL<1831> B_IWL<1830> B_IWL<1829> B_IWL<1828> B_IWL<1827> B_IWL<1826> B_IWL<1825> B_IWL<1824> B_IWL<1823> B_IWL<1822> B_IWL<1821> B_IWL<1820> B_IWL<1819> B_IWL<1818> B_IWL<1817> B_IWL<1816> B_IWL<1815> B_IWL<1814> B_IWL<1813> B_IWL<1812> B_IWL<1811> B_IWL<1810> B_IWL<1809> B_IWL<1808> B_IWL<1807> B_IWL<1806> B_IWL<1805> B_IWL<1804> B_IWL<1803> B_IWL<1802> B_IWL<1801> B_IWL<1800> B_IWL<1799> B_IWL<1798> B_IWL<1797> B_IWL<1796> B_IWL<1795> B_IWL<1794> B_IWL<1793> B_IWL<1792> B_IWL<1919> B_IWL<1918> B_IWL<1917> B_IWL<1916> B_IWL<1915> B_IWL<1914> B_IWL<1913> B_IWL<1912> B_IWL<1911> B_IWL<1910> B_IWL<1909> B_IWL<1908> B_IWL<1907> B_IWL<1906> B_IWL<1905> B_IWL<1904> B_IWL<1903> B_IWL<1902> B_IWL<1901> B_IWL<1900> B_IWL<1899> B_IWL<1898> B_IWL<1897> B_IWL<1896> B_IWL<1895> B_IWL<1894> B_IWL<1893> B_IWL<1892> B_IWL<1891> B_IWL<1890> B_IWL<1889> B_IWL<1888> B_IWL<1887> B_IWL<1886> B_IWL<1885> B_IWL<1884> B_IWL<1883> B_IWL<1882> B_IWL<1881> B_IWL<1880> B_IWL<1879> B_IWL<1878> B_IWL<1877> B_IWL<1876> B_IWL<1875> B_IWL<1874> B_IWL<1873> B_IWL<1872> B_IWL<1871> B_IWL<1870> B_IWL<1869> B_IWL<1868> B_IWL<1867> B_IWL<1866> B_IWL<1865> B_IWL<1864> B_IWL<1863> B_IWL<1862> B_IWL<1861> B_IWL<1860> B_IWL<1859> B_IWL<1858> B_IWL<1857> B_IWL<1856> VDD_CORE VSS / RM_IHPSG13_256x32_c2_2P_COLUMN_pcell_0 +XCOL<28> A_BLC<57> A_BLC<56> A_BLC_TOP<57> A_BLC_TOP<56> A_BLT<57> A_BLT<56> A_BLT_TOP<57> A_BLT_TOP<56> A_IWL<1791> A_IWL<1790> A_IWL<1789> A_IWL<1788> A_IWL<1787> A_IWL<1786> A_IWL<1785> A_IWL<1784> A_IWL<1783> A_IWL<1782> A_IWL<1781> A_IWL<1780> A_IWL<1779> A_IWL<1778> A_IWL<1777> A_IWL<1776> A_IWL<1775> A_IWL<1774> A_IWL<1773> A_IWL<1772> A_IWL<1771> A_IWL<1770> A_IWL<1769> A_IWL<1768> A_IWL<1767> A_IWL<1766> A_IWL<1765> A_IWL<1764> A_IWL<1763> A_IWL<1762> A_IWL<1761> A_IWL<1760> A_IWL<1759> A_IWL<1758> A_IWL<1757> A_IWL<1756> A_IWL<1755> A_IWL<1754> A_IWL<1753> A_IWL<1752> A_IWL<1751> A_IWL<1750> A_IWL<1749> A_IWL<1748> A_IWL<1747> A_IWL<1746> A_IWL<1745> A_IWL<1744> A_IWL<1743> A_IWL<1742> A_IWL<1741> A_IWL<1740> A_IWL<1739> A_IWL<1738> A_IWL<1737> A_IWL<1736> A_IWL<1735> A_IWL<1734> A_IWL<1733> A_IWL<1732> A_IWL<1731> A_IWL<1730> A_IWL<1729> A_IWL<1728> A_IWL<1855> A_IWL<1854> A_IWL<1853> A_IWL<1852> A_IWL<1851> A_IWL<1850> A_IWL<1849> A_IWL<1848> A_IWL<1847> A_IWL<1846> A_IWL<1845> A_IWL<1844> A_IWL<1843> A_IWL<1842> A_IWL<1841> A_IWL<1840> A_IWL<1839> A_IWL<1838> A_IWL<1837> A_IWL<1836> A_IWL<1835> A_IWL<1834> A_IWL<1833> A_IWL<1832> A_IWL<1831> A_IWL<1830> A_IWL<1829> A_IWL<1828> A_IWL<1827> A_IWL<1826> A_IWL<1825> A_IWL<1824> A_IWL<1823> A_IWL<1822> A_IWL<1821> A_IWL<1820> A_IWL<1819> A_IWL<1818> A_IWL<1817> A_IWL<1816> A_IWL<1815> A_IWL<1814> A_IWL<1813> A_IWL<1812> A_IWL<1811> A_IWL<1810> A_IWL<1809> A_IWL<1808> A_IWL<1807> A_IWL<1806> A_IWL<1805> A_IWL<1804> A_IWL<1803> A_IWL<1802> A_IWL<1801> A_IWL<1800> A_IWL<1799> A_IWL<1798> A_IWL<1797> A_IWL<1796> A_IWL<1795> A_IWL<1794> A_IWL<1793> A_IWL<1792> B_BLC<57> B_BLC<56> B_BLC_TOP<57> B_BLC_TOP<56> B_BLT<57> B_BLT<56> B_BLT_TOP<57> B_BLT_TOP<56> B_IWL<1791> B_IWL<1790> B_IWL<1789> B_IWL<1788> B_IWL<1787> B_IWL<1786> B_IWL<1785> B_IWL<1784> B_IWL<1783> B_IWL<1782> B_IWL<1781> B_IWL<1780> B_IWL<1779> B_IWL<1778> B_IWL<1777> B_IWL<1776> B_IWL<1775> B_IWL<1774> B_IWL<1773> B_IWL<1772> B_IWL<1771> B_IWL<1770> B_IWL<1769> B_IWL<1768> B_IWL<1767> B_IWL<1766> B_IWL<1765> B_IWL<1764> B_IWL<1763> B_IWL<1762> B_IWL<1761> B_IWL<1760> B_IWL<1759> B_IWL<1758> B_IWL<1757> B_IWL<1756> B_IWL<1755> B_IWL<1754> B_IWL<1753> B_IWL<1752> B_IWL<1751> B_IWL<1750> B_IWL<1749> B_IWL<1748> B_IWL<1747> B_IWL<1746> B_IWL<1745> B_IWL<1744> B_IWL<1743> B_IWL<1742> B_IWL<1741> B_IWL<1740> B_IWL<1739> B_IWL<1738> B_IWL<1737> B_IWL<1736> B_IWL<1735> B_IWL<1734> B_IWL<1733> B_IWL<1732> B_IWL<1731> B_IWL<1730> B_IWL<1729> B_IWL<1728> B_IWL<1855> B_IWL<1854> B_IWL<1853> B_IWL<1852> B_IWL<1851> B_IWL<1850> B_IWL<1849> B_IWL<1848> B_IWL<1847> B_IWL<1846> B_IWL<1845> B_IWL<1844> B_IWL<1843> B_IWL<1842> B_IWL<1841> B_IWL<1840> B_IWL<1839> B_IWL<1838> B_IWL<1837> B_IWL<1836> B_IWL<1835> B_IWL<1834> B_IWL<1833> B_IWL<1832> B_IWL<1831> B_IWL<1830> B_IWL<1829> B_IWL<1828> B_IWL<1827> B_IWL<1826> B_IWL<1825> B_IWL<1824> B_IWL<1823> B_IWL<1822> B_IWL<1821> B_IWL<1820> B_IWL<1819> B_IWL<1818> B_IWL<1817> B_IWL<1816> B_IWL<1815> B_IWL<1814> B_IWL<1813> B_IWL<1812> B_IWL<1811> B_IWL<1810> B_IWL<1809> B_IWL<1808> B_IWL<1807> B_IWL<1806> B_IWL<1805> B_IWL<1804> B_IWL<1803> B_IWL<1802> B_IWL<1801> B_IWL<1800> B_IWL<1799> B_IWL<1798> B_IWL<1797> B_IWL<1796> B_IWL<1795> B_IWL<1794> B_IWL<1793> B_IWL<1792> VDD_CORE VSS / RM_IHPSG13_256x32_c2_2P_COLUMN_pcell_0 +XCOL<27> A_BLC<55> A_BLC<54> A_BLC_TOP<55> A_BLC_TOP<54> A_BLT<55> A_BLT<54> A_BLT_TOP<55> A_BLT_TOP<54> A_IWL<1727> A_IWL<1726> A_IWL<1725> A_IWL<1724> A_IWL<1723> A_IWL<1722> A_IWL<1721> A_IWL<1720> A_IWL<1719> A_IWL<1718> A_IWL<1717> A_IWL<1716> A_IWL<1715> A_IWL<1714> A_IWL<1713> A_IWL<1712> A_IWL<1711> A_IWL<1710> A_IWL<1709> A_IWL<1708> A_IWL<1707> A_IWL<1706> A_IWL<1705> A_IWL<1704> A_IWL<1703> A_IWL<1702> A_IWL<1701> A_IWL<1700> A_IWL<1699> A_IWL<1698> A_IWL<1697> A_IWL<1696> A_IWL<1695> A_IWL<1694> A_IWL<1693> A_IWL<1692> A_IWL<1691> A_IWL<1690> A_IWL<1689> A_IWL<1688> A_IWL<1687> A_IWL<1686> A_IWL<1685> A_IWL<1684> A_IWL<1683> A_IWL<1682> A_IWL<1681> A_IWL<1680> A_IWL<1679> A_IWL<1678> A_IWL<1677> A_IWL<1676> A_IWL<1675> A_IWL<1674> A_IWL<1673> A_IWL<1672> A_IWL<1671> A_IWL<1670> A_IWL<1669> A_IWL<1668> A_IWL<1667> A_IWL<1666> A_IWL<1665> A_IWL<1664> A_IWL<1791> A_IWL<1790> A_IWL<1789> A_IWL<1788> A_IWL<1787> A_IWL<1786> A_IWL<1785> A_IWL<1784> A_IWL<1783> A_IWL<1782> A_IWL<1781> A_IWL<1780> A_IWL<1779> A_IWL<1778> A_IWL<1777> A_IWL<1776> A_IWL<1775> A_IWL<1774> A_IWL<1773> A_IWL<1772> A_IWL<1771> A_IWL<1770> A_IWL<1769> A_IWL<1768> A_IWL<1767> A_IWL<1766> A_IWL<1765> A_IWL<1764> A_IWL<1763> A_IWL<1762> A_IWL<1761> A_IWL<1760> A_IWL<1759> A_IWL<1758> A_IWL<1757> A_IWL<1756> A_IWL<1755> A_IWL<1754> A_IWL<1753> A_IWL<1752> A_IWL<1751> A_IWL<1750> A_IWL<1749> A_IWL<1748> A_IWL<1747> A_IWL<1746> A_IWL<1745> A_IWL<1744> A_IWL<1743> A_IWL<1742> A_IWL<1741> A_IWL<1740> A_IWL<1739> A_IWL<1738> A_IWL<1737> A_IWL<1736> A_IWL<1735> A_IWL<1734> A_IWL<1733> A_IWL<1732> A_IWL<1731> A_IWL<1730> A_IWL<1729> A_IWL<1728> B_BLC<55> B_BLC<54> B_BLC_TOP<55> B_BLC_TOP<54> B_BLT<55> B_BLT<54> B_BLT_TOP<55> B_BLT_TOP<54> B_IWL<1727> B_IWL<1726> B_IWL<1725> B_IWL<1724> B_IWL<1723> B_IWL<1722> B_IWL<1721> B_IWL<1720> B_IWL<1719> B_IWL<1718> B_IWL<1717> B_IWL<1716> B_IWL<1715> B_IWL<1714> B_IWL<1713> B_IWL<1712> B_IWL<1711> B_IWL<1710> B_IWL<1709> B_IWL<1708> B_IWL<1707> B_IWL<1706> B_IWL<1705> B_IWL<1704> B_IWL<1703> B_IWL<1702> B_IWL<1701> B_IWL<1700> B_IWL<1699> B_IWL<1698> B_IWL<1697> B_IWL<1696> B_IWL<1695> B_IWL<1694> B_IWL<1693> B_IWL<1692> B_IWL<1691> B_IWL<1690> B_IWL<1689> B_IWL<1688> B_IWL<1687> B_IWL<1686> B_IWL<1685> B_IWL<1684> B_IWL<1683> B_IWL<1682> B_IWL<1681> B_IWL<1680> B_IWL<1679> B_IWL<1678> B_IWL<1677> B_IWL<1676> B_IWL<1675> B_IWL<1674> B_IWL<1673> B_IWL<1672> B_IWL<1671> B_IWL<1670> B_IWL<1669> B_IWL<1668> B_IWL<1667> B_IWL<1666> B_IWL<1665> B_IWL<1664> B_IWL<1791> B_IWL<1790> B_IWL<1789> B_IWL<1788> B_IWL<1787> B_IWL<1786> B_IWL<1785> B_IWL<1784> B_IWL<1783> B_IWL<1782> B_IWL<1781> B_IWL<1780> B_IWL<1779> B_IWL<1778> B_IWL<1777> B_IWL<1776> B_IWL<1775> B_IWL<1774> B_IWL<1773> B_IWL<1772> B_IWL<1771> B_IWL<1770> B_IWL<1769> B_IWL<1768> B_IWL<1767> B_IWL<1766> B_IWL<1765> B_IWL<1764> B_IWL<1763> B_IWL<1762> B_IWL<1761> B_IWL<1760> B_IWL<1759> B_IWL<1758> B_IWL<1757> B_IWL<1756> B_IWL<1755> B_IWL<1754> B_IWL<1753> B_IWL<1752> B_IWL<1751> B_IWL<1750> B_IWL<1749> B_IWL<1748> B_IWL<1747> B_IWL<1746> B_IWL<1745> B_IWL<1744> B_IWL<1743> B_IWL<1742> B_IWL<1741> B_IWL<1740> B_IWL<1739> B_IWL<1738> B_IWL<1737> B_IWL<1736> B_IWL<1735> B_IWL<1734> B_IWL<1733> B_IWL<1732> B_IWL<1731> B_IWL<1730> B_IWL<1729> B_IWL<1728> VDD_CORE VSS / RM_IHPSG13_256x32_c2_2P_COLUMN_pcell_0 +XCOL<26> A_BLC<53> A_BLC<52> A_BLC_TOP<53> A_BLC_TOP<52> A_BLT<53> A_BLT<52> A_BLT_TOP<53> A_BLT_TOP<52> A_IWL<1663> A_IWL<1662> A_IWL<1661> A_IWL<1660> A_IWL<1659> A_IWL<1658> A_IWL<1657> A_IWL<1656> A_IWL<1655> A_IWL<1654> A_IWL<1653> A_IWL<1652> A_IWL<1651> A_IWL<1650> A_IWL<1649> A_IWL<1648> A_IWL<1647> A_IWL<1646> A_IWL<1645> A_IWL<1644> A_IWL<1643> A_IWL<1642> A_IWL<1641> A_IWL<1640> A_IWL<1639> A_IWL<1638> A_IWL<1637> A_IWL<1636> A_IWL<1635> A_IWL<1634> A_IWL<1633> A_IWL<1632> A_IWL<1631> A_IWL<1630> A_IWL<1629> A_IWL<1628> A_IWL<1627> A_IWL<1626> A_IWL<1625> A_IWL<1624> A_IWL<1623> A_IWL<1622> A_IWL<1621> A_IWL<1620> A_IWL<1619> A_IWL<1618> A_IWL<1617> A_IWL<1616> A_IWL<1615> A_IWL<1614> A_IWL<1613> A_IWL<1612> A_IWL<1611> A_IWL<1610> A_IWL<1609> A_IWL<1608> A_IWL<1607> A_IWL<1606> A_IWL<1605> A_IWL<1604> A_IWL<1603> A_IWL<1602> A_IWL<1601> A_IWL<1600> A_IWL<1727> A_IWL<1726> A_IWL<1725> A_IWL<1724> A_IWL<1723> A_IWL<1722> A_IWL<1721> A_IWL<1720> A_IWL<1719> A_IWL<1718> A_IWL<1717> A_IWL<1716> A_IWL<1715> A_IWL<1714> A_IWL<1713> A_IWL<1712> A_IWL<1711> A_IWL<1710> A_IWL<1709> A_IWL<1708> A_IWL<1707> A_IWL<1706> A_IWL<1705> A_IWL<1704> A_IWL<1703> A_IWL<1702> A_IWL<1701> A_IWL<1700> A_IWL<1699> A_IWL<1698> A_IWL<1697> A_IWL<1696> A_IWL<1695> A_IWL<1694> A_IWL<1693> A_IWL<1692> A_IWL<1691> A_IWL<1690> A_IWL<1689> A_IWL<1688> A_IWL<1687> A_IWL<1686> A_IWL<1685> A_IWL<1684> A_IWL<1683> A_IWL<1682> A_IWL<1681> A_IWL<1680> A_IWL<1679> A_IWL<1678> A_IWL<1677> A_IWL<1676> A_IWL<1675> A_IWL<1674> A_IWL<1673> A_IWL<1672> A_IWL<1671> A_IWL<1670> A_IWL<1669> A_IWL<1668> A_IWL<1667> A_IWL<1666> A_IWL<1665> A_IWL<1664> B_BLC<53> B_BLC<52> B_BLC_TOP<53> B_BLC_TOP<52> B_BLT<53> B_BLT<52> B_BLT_TOP<53> B_BLT_TOP<52> B_IWL<1663> B_IWL<1662> B_IWL<1661> B_IWL<1660> B_IWL<1659> B_IWL<1658> B_IWL<1657> B_IWL<1656> B_IWL<1655> B_IWL<1654> B_IWL<1653> B_IWL<1652> B_IWL<1651> B_IWL<1650> B_IWL<1649> B_IWL<1648> B_IWL<1647> B_IWL<1646> B_IWL<1645> B_IWL<1644> B_IWL<1643> B_IWL<1642> B_IWL<1641> B_IWL<1640> B_IWL<1639> B_IWL<1638> B_IWL<1637> B_IWL<1636> B_IWL<1635> B_IWL<1634> B_IWL<1633> B_IWL<1632> B_IWL<1631> B_IWL<1630> B_IWL<1629> B_IWL<1628> B_IWL<1627> B_IWL<1626> B_IWL<1625> B_IWL<1624> B_IWL<1623> B_IWL<1622> B_IWL<1621> B_IWL<1620> B_IWL<1619> B_IWL<1618> B_IWL<1617> B_IWL<1616> B_IWL<1615> B_IWL<1614> B_IWL<1613> B_IWL<1612> B_IWL<1611> B_IWL<1610> B_IWL<1609> B_IWL<1608> B_IWL<1607> B_IWL<1606> B_IWL<1605> B_IWL<1604> B_IWL<1603> B_IWL<1602> B_IWL<1601> B_IWL<1600> B_IWL<1727> B_IWL<1726> B_IWL<1725> B_IWL<1724> B_IWL<1723> B_IWL<1722> B_IWL<1721> B_IWL<1720> B_IWL<1719> B_IWL<1718> B_IWL<1717> B_IWL<1716> B_IWL<1715> B_IWL<1714> B_IWL<1713> B_IWL<1712> B_IWL<1711> B_IWL<1710> B_IWL<1709> B_IWL<1708> B_IWL<1707> B_IWL<1706> B_IWL<1705> B_IWL<1704> B_IWL<1703> B_IWL<1702> B_IWL<1701> B_IWL<1700> B_IWL<1699> B_IWL<1698> B_IWL<1697> B_IWL<1696> B_IWL<1695> B_IWL<1694> B_IWL<1693> B_IWL<1692> B_IWL<1691> B_IWL<1690> B_IWL<1689> B_IWL<1688> B_IWL<1687> B_IWL<1686> B_IWL<1685> B_IWL<1684> B_IWL<1683> B_IWL<1682> B_IWL<1681> B_IWL<1680> B_IWL<1679> B_IWL<1678> B_IWL<1677> B_IWL<1676> B_IWL<1675> B_IWL<1674> B_IWL<1673> B_IWL<1672> B_IWL<1671> B_IWL<1670> B_IWL<1669> B_IWL<1668> B_IWL<1667> B_IWL<1666> B_IWL<1665> B_IWL<1664> VDD_CORE VSS / RM_IHPSG13_256x32_c2_2P_COLUMN_pcell_0 +XCOL<25> A_BLC<51> A_BLC<50> A_BLC_TOP<51> A_BLC_TOP<50> A_BLT<51> A_BLT<50> A_BLT_TOP<51> A_BLT_TOP<50> A_IWL<1599> A_IWL<1598> A_IWL<1597> A_IWL<1596> A_IWL<1595> A_IWL<1594> A_IWL<1593> A_IWL<1592> A_IWL<1591> A_IWL<1590> A_IWL<1589> A_IWL<1588> A_IWL<1587> A_IWL<1586> A_IWL<1585> A_IWL<1584> A_IWL<1583> A_IWL<1582> A_IWL<1581> A_IWL<1580> A_IWL<1579> A_IWL<1578> A_IWL<1577> A_IWL<1576> A_IWL<1575> A_IWL<1574> A_IWL<1573> A_IWL<1572> A_IWL<1571> A_IWL<1570> A_IWL<1569> A_IWL<1568> A_IWL<1567> A_IWL<1566> A_IWL<1565> A_IWL<1564> A_IWL<1563> A_IWL<1562> A_IWL<1561> A_IWL<1560> A_IWL<1559> A_IWL<1558> A_IWL<1557> A_IWL<1556> A_IWL<1555> A_IWL<1554> A_IWL<1553> A_IWL<1552> A_IWL<1551> A_IWL<1550> A_IWL<1549> A_IWL<1548> A_IWL<1547> A_IWL<1546> A_IWL<1545> A_IWL<1544> A_IWL<1543> A_IWL<1542> A_IWL<1541> A_IWL<1540> A_IWL<1539> A_IWL<1538> A_IWL<1537> A_IWL<1536> A_IWL<1663> A_IWL<1662> A_IWL<1661> A_IWL<1660> A_IWL<1659> A_IWL<1658> A_IWL<1657> A_IWL<1656> A_IWL<1655> A_IWL<1654> A_IWL<1653> A_IWL<1652> A_IWL<1651> A_IWL<1650> A_IWL<1649> A_IWL<1648> A_IWL<1647> A_IWL<1646> A_IWL<1645> A_IWL<1644> A_IWL<1643> A_IWL<1642> A_IWL<1641> A_IWL<1640> A_IWL<1639> A_IWL<1638> A_IWL<1637> A_IWL<1636> A_IWL<1635> A_IWL<1634> A_IWL<1633> A_IWL<1632> A_IWL<1631> A_IWL<1630> A_IWL<1629> A_IWL<1628> A_IWL<1627> A_IWL<1626> A_IWL<1625> A_IWL<1624> A_IWL<1623> A_IWL<1622> A_IWL<1621> A_IWL<1620> A_IWL<1619> A_IWL<1618> A_IWL<1617> A_IWL<1616> A_IWL<1615> A_IWL<1614> A_IWL<1613> A_IWL<1612> A_IWL<1611> A_IWL<1610> A_IWL<1609> A_IWL<1608> A_IWL<1607> A_IWL<1606> A_IWL<1605> A_IWL<1604> A_IWL<1603> A_IWL<1602> A_IWL<1601> A_IWL<1600> B_BLC<51> B_BLC<50> B_BLC_TOP<51> B_BLC_TOP<50> B_BLT<51> B_BLT<50> B_BLT_TOP<51> B_BLT_TOP<50> B_IWL<1599> B_IWL<1598> B_IWL<1597> B_IWL<1596> B_IWL<1595> B_IWL<1594> B_IWL<1593> B_IWL<1592> B_IWL<1591> B_IWL<1590> B_IWL<1589> B_IWL<1588> B_IWL<1587> B_IWL<1586> B_IWL<1585> B_IWL<1584> B_IWL<1583> B_IWL<1582> B_IWL<1581> B_IWL<1580> B_IWL<1579> B_IWL<1578> B_IWL<1577> B_IWL<1576> B_IWL<1575> B_IWL<1574> B_IWL<1573> B_IWL<1572> B_IWL<1571> B_IWL<1570> B_IWL<1569> B_IWL<1568> B_IWL<1567> B_IWL<1566> B_IWL<1565> B_IWL<1564> B_IWL<1563> B_IWL<1562> B_IWL<1561> B_IWL<1560> B_IWL<1559> B_IWL<1558> B_IWL<1557> B_IWL<1556> B_IWL<1555> B_IWL<1554> B_IWL<1553> B_IWL<1552> B_IWL<1551> B_IWL<1550> B_IWL<1549> B_IWL<1548> B_IWL<1547> B_IWL<1546> B_IWL<1545> B_IWL<1544> B_IWL<1543> B_IWL<1542> B_IWL<1541> B_IWL<1540> B_IWL<1539> B_IWL<1538> B_IWL<1537> B_IWL<1536> B_IWL<1663> B_IWL<1662> B_IWL<1661> B_IWL<1660> B_IWL<1659> B_IWL<1658> B_IWL<1657> B_IWL<1656> B_IWL<1655> B_IWL<1654> B_IWL<1653> B_IWL<1652> B_IWL<1651> B_IWL<1650> B_IWL<1649> B_IWL<1648> B_IWL<1647> B_IWL<1646> B_IWL<1645> B_IWL<1644> B_IWL<1643> B_IWL<1642> B_IWL<1641> B_IWL<1640> B_IWL<1639> B_IWL<1638> B_IWL<1637> B_IWL<1636> B_IWL<1635> B_IWL<1634> B_IWL<1633> B_IWL<1632> B_IWL<1631> B_IWL<1630> B_IWL<1629> B_IWL<1628> B_IWL<1627> B_IWL<1626> B_IWL<1625> B_IWL<1624> B_IWL<1623> B_IWL<1622> B_IWL<1621> B_IWL<1620> B_IWL<1619> B_IWL<1618> B_IWL<1617> B_IWL<1616> B_IWL<1615> B_IWL<1614> B_IWL<1613> B_IWL<1612> B_IWL<1611> B_IWL<1610> B_IWL<1609> B_IWL<1608> B_IWL<1607> B_IWL<1606> B_IWL<1605> B_IWL<1604> B_IWL<1603> B_IWL<1602> B_IWL<1601> B_IWL<1600> VDD_CORE VSS / RM_IHPSG13_256x32_c2_2P_COLUMN_pcell_0 +XCOL<24> A_BLC<49> A_BLC<48> A_BLC_TOP<49> A_BLC_TOP<48> A_BLT<49> A_BLT<48> A_BLT_TOP<49> A_BLT_TOP<48> A_IWL<1535> A_IWL<1534> A_IWL<1533> A_IWL<1532> A_IWL<1531> A_IWL<1530> A_IWL<1529> A_IWL<1528> A_IWL<1527> A_IWL<1526> A_IWL<1525> A_IWL<1524> A_IWL<1523> A_IWL<1522> A_IWL<1521> A_IWL<1520> A_IWL<1519> A_IWL<1518> A_IWL<1517> A_IWL<1516> A_IWL<1515> A_IWL<1514> A_IWL<1513> A_IWL<1512> A_IWL<1511> A_IWL<1510> A_IWL<1509> A_IWL<1508> A_IWL<1507> A_IWL<1506> A_IWL<1505> A_IWL<1504> A_IWL<1503> A_IWL<1502> A_IWL<1501> A_IWL<1500> A_IWL<1499> A_IWL<1498> A_IWL<1497> A_IWL<1496> A_IWL<1495> A_IWL<1494> A_IWL<1493> A_IWL<1492> A_IWL<1491> A_IWL<1490> A_IWL<1489> A_IWL<1488> A_IWL<1487> A_IWL<1486> A_IWL<1485> A_IWL<1484> A_IWL<1483> A_IWL<1482> A_IWL<1481> A_IWL<1480> A_IWL<1479> A_IWL<1478> A_IWL<1477> A_IWL<1476> A_IWL<1475> A_IWL<1474> A_IWL<1473> A_IWL<1472> A_IWL<1599> A_IWL<1598> A_IWL<1597> A_IWL<1596> A_IWL<1595> A_IWL<1594> A_IWL<1593> A_IWL<1592> A_IWL<1591> A_IWL<1590> A_IWL<1589> A_IWL<1588> A_IWL<1587> A_IWL<1586> A_IWL<1585> A_IWL<1584> A_IWL<1583> A_IWL<1582> A_IWL<1581> A_IWL<1580> A_IWL<1579> A_IWL<1578> A_IWL<1577> A_IWL<1576> A_IWL<1575> A_IWL<1574> A_IWL<1573> A_IWL<1572> A_IWL<1571> A_IWL<1570> A_IWL<1569> A_IWL<1568> A_IWL<1567> A_IWL<1566> A_IWL<1565> A_IWL<1564> A_IWL<1563> A_IWL<1562> A_IWL<1561> A_IWL<1560> A_IWL<1559> A_IWL<1558> A_IWL<1557> A_IWL<1556> A_IWL<1555> A_IWL<1554> A_IWL<1553> A_IWL<1552> A_IWL<1551> A_IWL<1550> A_IWL<1549> A_IWL<1548> A_IWL<1547> A_IWL<1546> A_IWL<1545> A_IWL<1544> A_IWL<1543> A_IWL<1542> A_IWL<1541> A_IWL<1540> A_IWL<1539> A_IWL<1538> A_IWL<1537> A_IWL<1536> B_BLC<49> B_BLC<48> B_BLC_TOP<49> B_BLC_TOP<48> B_BLT<49> B_BLT<48> B_BLT_TOP<49> B_BLT_TOP<48> B_IWL<1535> B_IWL<1534> B_IWL<1533> B_IWL<1532> B_IWL<1531> B_IWL<1530> B_IWL<1529> B_IWL<1528> B_IWL<1527> B_IWL<1526> B_IWL<1525> B_IWL<1524> B_IWL<1523> B_IWL<1522> B_IWL<1521> B_IWL<1520> B_IWL<1519> B_IWL<1518> B_IWL<1517> B_IWL<1516> B_IWL<1515> B_IWL<1514> B_IWL<1513> B_IWL<1512> B_IWL<1511> B_IWL<1510> B_IWL<1509> B_IWL<1508> B_IWL<1507> B_IWL<1506> B_IWL<1505> B_IWL<1504> B_IWL<1503> B_IWL<1502> B_IWL<1501> B_IWL<1500> B_IWL<1499> B_IWL<1498> B_IWL<1497> B_IWL<1496> B_IWL<1495> B_IWL<1494> B_IWL<1493> B_IWL<1492> B_IWL<1491> B_IWL<1490> B_IWL<1489> B_IWL<1488> B_IWL<1487> B_IWL<1486> B_IWL<1485> B_IWL<1484> B_IWL<1483> B_IWL<1482> B_IWL<1481> B_IWL<1480> B_IWL<1479> B_IWL<1478> B_IWL<1477> B_IWL<1476> B_IWL<1475> B_IWL<1474> B_IWL<1473> B_IWL<1472> B_IWL<1599> B_IWL<1598> B_IWL<1597> B_IWL<1596> B_IWL<1595> B_IWL<1594> B_IWL<1593> B_IWL<1592> B_IWL<1591> B_IWL<1590> B_IWL<1589> B_IWL<1588> B_IWL<1587> B_IWL<1586> B_IWL<1585> B_IWL<1584> B_IWL<1583> B_IWL<1582> B_IWL<1581> B_IWL<1580> B_IWL<1579> B_IWL<1578> B_IWL<1577> B_IWL<1576> B_IWL<1575> B_IWL<1574> B_IWL<1573> B_IWL<1572> B_IWL<1571> B_IWL<1570> B_IWL<1569> B_IWL<1568> B_IWL<1567> B_IWL<1566> B_IWL<1565> B_IWL<1564> B_IWL<1563> B_IWL<1562> B_IWL<1561> B_IWL<1560> B_IWL<1559> B_IWL<1558> B_IWL<1557> B_IWL<1556> B_IWL<1555> B_IWL<1554> B_IWL<1553> B_IWL<1552> B_IWL<1551> B_IWL<1550> B_IWL<1549> B_IWL<1548> B_IWL<1547> B_IWL<1546> B_IWL<1545> B_IWL<1544> B_IWL<1543> B_IWL<1542> B_IWL<1541> B_IWL<1540> B_IWL<1539> B_IWL<1538> B_IWL<1537> B_IWL<1536> VDD_CORE VSS / RM_IHPSG13_256x32_c2_2P_COLUMN_pcell_0 +XCOL<23> A_BLC<47> A_BLC<46> A_BLC_TOP<47> A_BLC_TOP<46> A_BLT<47> A_BLT<46> A_BLT_TOP<47> A_BLT_TOP<46> A_IWL<1471> A_IWL<1470> A_IWL<1469> A_IWL<1468> A_IWL<1467> A_IWL<1466> A_IWL<1465> A_IWL<1464> A_IWL<1463> A_IWL<1462> A_IWL<1461> A_IWL<1460> A_IWL<1459> A_IWL<1458> A_IWL<1457> A_IWL<1456> A_IWL<1455> A_IWL<1454> A_IWL<1453> A_IWL<1452> A_IWL<1451> A_IWL<1450> A_IWL<1449> A_IWL<1448> A_IWL<1447> A_IWL<1446> A_IWL<1445> A_IWL<1444> A_IWL<1443> A_IWL<1442> A_IWL<1441> A_IWL<1440> A_IWL<1439> A_IWL<1438> A_IWL<1437> A_IWL<1436> A_IWL<1435> A_IWL<1434> A_IWL<1433> A_IWL<1432> A_IWL<1431> A_IWL<1430> A_IWL<1429> A_IWL<1428> A_IWL<1427> A_IWL<1426> A_IWL<1425> A_IWL<1424> A_IWL<1423> A_IWL<1422> A_IWL<1421> A_IWL<1420> A_IWL<1419> A_IWL<1418> A_IWL<1417> A_IWL<1416> A_IWL<1415> A_IWL<1414> A_IWL<1413> A_IWL<1412> A_IWL<1411> A_IWL<1410> A_IWL<1409> A_IWL<1408> A_IWL<1535> A_IWL<1534> A_IWL<1533> A_IWL<1532> A_IWL<1531> A_IWL<1530> A_IWL<1529> A_IWL<1528> A_IWL<1527> A_IWL<1526> A_IWL<1525> A_IWL<1524> A_IWL<1523> A_IWL<1522> A_IWL<1521> A_IWL<1520> A_IWL<1519> A_IWL<1518> A_IWL<1517> A_IWL<1516> A_IWL<1515> A_IWL<1514> A_IWL<1513> A_IWL<1512> A_IWL<1511> A_IWL<1510> A_IWL<1509> A_IWL<1508> A_IWL<1507> A_IWL<1506> A_IWL<1505> A_IWL<1504> A_IWL<1503> A_IWL<1502> A_IWL<1501> A_IWL<1500> A_IWL<1499> A_IWL<1498> A_IWL<1497> A_IWL<1496> A_IWL<1495> A_IWL<1494> A_IWL<1493> A_IWL<1492> A_IWL<1491> A_IWL<1490> A_IWL<1489> A_IWL<1488> A_IWL<1487> A_IWL<1486> A_IWL<1485> A_IWL<1484> A_IWL<1483> A_IWL<1482> A_IWL<1481> A_IWL<1480> A_IWL<1479> A_IWL<1478> A_IWL<1477> A_IWL<1476> A_IWL<1475> A_IWL<1474> A_IWL<1473> A_IWL<1472> B_BLC<47> B_BLC<46> B_BLC_TOP<47> B_BLC_TOP<46> B_BLT<47> B_BLT<46> B_BLT_TOP<47> B_BLT_TOP<46> B_IWL<1471> B_IWL<1470> B_IWL<1469> B_IWL<1468> B_IWL<1467> B_IWL<1466> B_IWL<1465> B_IWL<1464> B_IWL<1463> B_IWL<1462> B_IWL<1461> B_IWL<1460> B_IWL<1459> B_IWL<1458> B_IWL<1457> B_IWL<1456> B_IWL<1455> B_IWL<1454> B_IWL<1453> B_IWL<1452> B_IWL<1451> B_IWL<1450> B_IWL<1449> B_IWL<1448> B_IWL<1447> B_IWL<1446> B_IWL<1445> B_IWL<1444> B_IWL<1443> B_IWL<1442> B_IWL<1441> B_IWL<1440> B_IWL<1439> B_IWL<1438> B_IWL<1437> B_IWL<1436> B_IWL<1435> B_IWL<1434> B_IWL<1433> B_IWL<1432> B_IWL<1431> B_IWL<1430> B_IWL<1429> B_IWL<1428> B_IWL<1427> B_IWL<1426> B_IWL<1425> B_IWL<1424> B_IWL<1423> B_IWL<1422> B_IWL<1421> B_IWL<1420> B_IWL<1419> B_IWL<1418> B_IWL<1417> B_IWL<1416> B_IWL<1415> B_IWL<1414> B_IWL<1413> B_IWL<1412> B_IWL<1411> B_IWL<1410> B_IWL<1409> B_IWL<1408> B_IWL<1535> B_IWL<1534> B_IWL<1533> B_IWL<1532> B_IWL<1531> B_IWL<1530> B_IWL<1529> B_IWL<1528> B_IWL<1527> B_IWL<1526> B_IWL<1525> B_IWL<1524> B_IWL<1523> B_IWL<1522> B_IWL<1521> B_IWL<1520> B_IWL<1519> B_IWL<1518> B_IWL<1517> B_IWL<1516> B_IWL<1515> B_IWL<1514> B_IWL<1513> B_IWL<1512> B_IWL<1511> B_IWL<1510> B_IWL<1509> B_IWL<1508> B_IWL<1507> B_IWL<1506> B_IWL<1505> B_IWL<1504> B_IWL<1503> B_IWL<1502> B_IWL<1501> B_IWL<1500> B_IWL<1499> B_IWL<1498> B_IWL<1497> B_IWL<1496> B_IWL<1495> B_IWL<1494> B_IWL<1493> B_IWL<1492> B_IWL<1491> B_IWL<1490> B_IWL<1489> B_IWL<1488> B_IWL<1487> B_IWL<1486> B_IWL<1485> B_IWL<1484> B_IWL<1483> B_IWL<1482> B_IWL<1481> B_IWL<1480> B_IWL<1479> B_IWL<1478> B_IWL<1477> B_IWL<1476> B_IWL<1475> B_IWL<1474> B_IWL<1473> B_IWL<1472> VDD_CORE VSS / RM_IHPSG13_256x32_c2_2P_COLUMN_pcell_0 +XCOL<22> A_BLC<45> A_BLC<44> A_BLC_TOP<45> A_BLC_TOP<44> A_BLT<45> A_BLT<44> A_BLT_TOP<45> A_BLT_TOP<44> A_IWL<1407> A_IWL<1406> A_IWL<1405> A_IWL<1404> A_IWL<1403> A_IWL<1402> A_IWL<1401> A_IWL<1400> A_IWL<1399> A_IWL<1398> A_IWL<1397> A_IWL<1396> A_IWL<1395> A_IWL<1394> A_IWL<1393> A_IWL<1392> A_IWL<1391> A_IWL<1390> A_IWL<1389> A_IWL<1388> A_IWL<1387> A_IWL<1386> A_IWL<1385> A_IWL<1384> A_IWL<1383> A_IWL<1382> A_IWL<1381> A_IWL<1380> A_IWL<1379> A_IWL<1378> A_IWL<1377> A_IWL<1376> A_IWL<1375> A_IWL<1374> A_IWL<1373> A_IWL<1372> A_IWL<1371> A_IWL<1370> A_IWL<1369> A_IWL<1368> A_IWL<1367> A_IWL<1366> A_IWL<1365> A_IWL<1364> A_IWL<1363> A_IWL<1362> A_IWL<1361> A_IWL<1360> A_IWL<1359> A_IWL<1358> A_IWL<1357> A_IWL<1356> A_IWL<1355> A_IWL<1354> A_IWL<1353> A_IWL<1352> A_IWL<1351> A_IWL<1350> A_IWL<1349> A_IWL<1348> A_IWL<1347> A_IWL<1346> A_IWL<1345> A_IWL<1344> A_IWL<1471> A_IWL<1470> A_IWL<1469> A_IWL<1468> A_IWL<1467> A_IWL<1466> A_IWL<1465> A_IWL<1464> A_IWL<1463> A_IWL<1462> A_IWL<1461> A_IWL<1460> A_IWL<1459> A_IWL<1458> A_IWL<1457> A_IWL<1456> A_IWL<1455> A_IWL<1454> A_IWL<1453> A_IWL<1452> A_IWL<1451> A_IWL<1450> A_IWL<1449> A_IWL<1448> A_IWL<1447> A_IWL<1446> A_IWL<1445> A_IWL<1444> A_IWL<1443> A_IWL<1442> A_IWL<1441> A_IWL<1440> A_IWL<1439> A_IWL<1438> A_IWL<1437> A_IWL<1436> A_IWL<1435> A_IWL<1434> A_IWL<1433> A_IWL<1432> A_IWL<1431> A_IWL<1430> A_IWL<1429> A_IWL<1428> A_IWL<1427> A_IWL<1426> A_IWL<1425> A_IWL<1424> A_IWL<1423> A_IWL<1422> A_IWL<1421> A_IWL<1420> A_IWL<1419> A_IWL<1418> A_IWL<1417> A_IWL<1416> A_IWL<1415> A_IWL<1414> A_IWL<1413> A_IWL<1412> A_IWL<1411> A_IWL<1410> A_IWL<1409> A_IWL<1408> B_BLC<45> B_BLC<44> B_BLC_TOP<45> B_BLC_TOP<44> B_BLT<45> B_BLT<44> B_BLT_TOP<45> B_BLT_TOP<44> B_IWL<1407> B_IWL<1406> B_IWL<1405> B_IWL<1404> B_IWL<1403> B_IWL<1402> B_IWL<1401> B_IWL<1400> B_IWL<1399> B_IWL<1398> B_IWL<1397> B_IWL<1396> B_IWL<1395> B_IWL<1394> B_IWL<1393> B_IWL<1392> B_IWL<1391> B_IWL<1390> B_IWL<1389> B_IWL<1388> B_IWL<1387> B_IWL<1386> B_IWL<1385> B_IWL<1384> B_IWL<1383> B_IWL<1382> B_IWL<1381> B_IWL<1380> B_IWL<1379> B_IWL<1378> B_IWL<1377> B_IWL<1376> B_IWL<1375> B_IWL<1374> B_IWL<1373> B_IWL<1372> B_IWL<1371> B_IWL<1370> B_IWL<1369> B_IWL<1368> B_IWL<1367> B_IWL<1366> B_IWL<1365> B_IWL<1364> B_IWL<1363> B_IWL<1362> B_IWL<1361> B_IWL<1360> B_IWL<1359> B_IWL<1358> B_IWL<1357> B_IWL<1356> B_IWL<1355> B_IWL<1354> B_IWL<1353> B_IWL<1352> B_IWL<1351> B_IWL<1350> B_IWL<1349> B_IWL<1348> B_IWL<1347> B_IWL<1346> B_IWL<1345> B_IWL<1344> B_IWL<1471> B_IWL<1470> B_IWL<1469> B_IWL<1468> B_IWL<1467> B_IWL<1466> B_IWL<1465> B_IWL<1464> B_IWL<1463> B_IWL<1462> B_IWL<1461> B_IWL<1460> B_IWL<1459> B_IWL<1458> B_IWL<1457> B_IWL<1456> B_IWL<1455> B_IWL<1454> B_IWL<1453> B_IWL<1452> B_IWL<1451> B_IWL<1450> B_IWL<1449> B_IWL<1448> B_IWL<1447> B_IWL<1446> B_IWL<1445> B_IWL<1444> B_IWL<1443> B_IWL<1442> B_IWL<1441> B_IWL<1440> B_IWL<1439> B_IWL<1438> B_IWL<1437> B_IWL<1436> B_IWL<1435> B_IWL<1434> B_IWL<1433> B_IWL<1432> B_IWL<1431> B_IWL<1430> B_IWL<1429> B_IWL<1428> B_IWL<1427> B_IWL<1426> B_IWL<1425> B_IWL<1424> B_IWL<1423> B_IWL<1422> B_IWL<1421> B_IWL<1420> B_IWL<1419> B_IWL<1418> B_IWL<1417> B_IWL<1416> B_IWL<1415> B_IWL<1414> B_IWL<1413> B_IWL<1412> B_IWL<1411> B_IWL<1410> B_IWL<1409> B_IWL<1408> VDD_CORE VSS / RM_IHPSG13_256x32_c2_2P_COLUMN_pcell_0 +XCOL<21> A_BLC<43> A_BLC<42> A_BLC_TOP<43> A_BLC_TOP<42> A_BLT<43> A_BLT<42> A_BLT_TOP<43> A_BLT_TOP<42> A_IWL<1343> A_IWL<1342> A_IWL<1341> A_IWL<1340> A_IWL<1339> A_IWL<1338> A_IWL<1337> A_IWL<1336> A_IWL<1335> A_IWL<1334> A_IWL<1333> A_IWL<1332> A_IWL<1331> A_IWL<1330> A_IWL<1329> A_IWL<1328> A_IWL<1327> A_IWL<1326> A_IWL<1325> A_IWL<1324> A_IWL<1323> A_IWL<1322> A_IWL<1321> A_IWL<1320> A_IWL<1319> A_IWL<1318> A_IWL<1317> A_IWL<1316> A_IWL<1315> A_IWL<1314> A_IWL<1313> A_IWL<1312> A_IWL<1311> A_IWL<1310> A_IWL<1309> A_IWL<1308> A_IWL<1307> A_IWL<1306> A_IWL<1305> A_IWL<1304> A_IWL<1303> A_IWL<1302> A_IWL<1301> A_IWL<1300> A_IWL<1299> A_IWL<1298> A_IWL<1297> A_IWL<1296> A_IWL<1295> A_IWL<1294> A_IWL<1293> A_IWL<1292> A_IWL<1291> A_IWL<1290> A_IWL<1289> A_IWL<1288> A_IWL<1287> A_IWL<1286> A_IWL<1285> A_IWL<1284> A_IWL<1283> A_IWL<1282> A_IWL<1281> A_IWL<1280> A_IWL<1407> A_IWL<1406> A_IWL<1405> A_IWL<1404> A_IWL<1403> A_IWL<1402> A_IWL<1401> A_IWL<1400> A_IWL<1399> A_IWL<1398> A_IWL<1397> A_IWL<1396> A_IWL<1395> A_IWL<1394> A_IWL<1393> A_IWL<1392> A_IWL<1391> A_IWL<1390> A_IWL<1389> A_IWL<1388> A_IWL<1387> A_IWL<1386> A_IWL<1385> A_IWL<1384> A_IWL<1383> A_IWL<1382> A_IWL<1381> A_IWL<1380> A_IWL<1379> A_IWL<1378> A_IWL<1377> A_IWL<1376> A_IWL<1375> A_IWL<1374> A_IWL<1373> A_IWL<1372> A_IWL<1371> A_IWL<1370> A_IWL<1369> A_IWL<1368> A_IWL<1367> A_IWL<1366> A_IWL<1365> A_IWL<1364> A_IWL<1363> A_IWL<1362> A_IWL<1361> A_IWL<1360> A_IWL<1359> A_IWL<1358> A_IWL<1357> A_IWL<1356> A_IWL<1355> A_IWL<1354> A_IWL<1353> A_IWL<1352> A_IWL<1351> A_IWL<1350> A_IWL<1349> A_IWL<1348> A_IWL<1347> A_IWL<1346> A_IWL<1345> A_IWL<1344> B_BLC<43> B_BLC<42> B_BLC_TOP<43> B_BLC_TOP<42> B_BLT<43> B_BLT<42> B_BLT_TOP<43> B_BLT_TOP<42> B_IWL<1343> B_IWL<1342> B_IWL<1341> B_IWL<1340> B_IWL<1339> B_IWL<1338> B_IWL<1337> B_IWL<1336> B_IWL<1335> B_IWL<1334> B_IWL<1333> B_IWL<1332> B_IWL<1331> B_IWL<1330> B_IWL<1329> B_IWL<1328> B_IWL<1327> B_IWL<1326> B_IWL<1325> B_IWL<1324> B_IWL<1323> B_IWL<1322> B_IWL<1321> B_IWL<1320> B_IWL<1319> B_IWL<1318> B_IWL<1317> B_IWL<1316> B_IWL<1315> B_IWL<1314> B_IWL<1313> B_IWL<1312> B_IWL<1311> B_IWL<1310> B_IWL<1309> B_IWL<1308> B_IWL<1307> B_IWL<1306> B_IWL<1305> B_IWL<1304> B_IWL<1303> B_IWL<1302> B_IWL<1301> B_IWL<1300> B_IWL<1299> B_IWL<1298> B_IWL<1297> B_IWL<1296> B_IWL<1295> B_IWL<1294> B_IWL<1293> B_IWL<1292> B_IWL<1291> B_IWL<1290> B_IWL<1289> B_IWL<1288> B_IWL<1287> B_IWL<1286> B_IWL<1285> B_IWL<1284> B_IWL<1283> B_IWL<1282> B_IWL<1281> B_IWL<1280> B_IWL<1407> B_IWL<1406> B_IWL<1405> B_IWL<1404> B_IWL<1403> B_IWL<1402> B_IWL<1401> B_IWL<1400> B_IWL<1399> B_IWL<1398> B_IWL<1397> B_IWL<1396> B_IWL<1395> B_IWL<1394> B_IWL<1393> B_IWL<1392> B_IWL<1391> B_IWL<1390> B_IWL<1389> B_IWL<1388> B_IWL<1387> B_IWL<1386> B_IWL<1385> B_IWL<1384> B_IWL<1383> B_IWL<1382> B_IWL<1381> B_IWL<1380> B_IWL<1379> B_IWL<1378> B_IWL<1377> B_IWL<1376> B_IWL<1375> B_IWL<1374> B_IWL<1373> B_IWL<1372> B_IWL<1371> B_IWL<1370> B_IWL<1369> B_IWL<1368> B_IWL<1367> B_IWL<1366> B_IWL<1365> B_IWL<1364> B_IWL<1363> B_IWL<1362> B_IWL<1361> B_IWL<1360> B_IWL<1359> B_IWL<1358> B_IWL<1357> B_IWL<1356> B_IWL<1355> B_IWL<1354> B_IWL<1353> B_IWL<1352> B_IWL<1351> B_IWL<1350> B_IWL<1349> B_IWL<1348> B_IWL<1347> B_IWL<1346> B_IWL<1345> B_IWL<1344> VDD_CORE VSS / RM_IHPSG13_256x32_c2_2P_COLUMN_pcell_0 +XCOL<20> A_BLC<41> A_BLC<40> A_BLC_TOP<41> A_BLC_TOP<40> A_BLT<41> A_BLT<40> A_BLT_TOP<41> A_BLT_TOP<40> A_IWL<1279> A_IWL<1278> A_IWL<1277> A_IWL<1276> A_IWL<1275> A_IWL<1274> A_IWL<1273> A_IWL<1272> A_IWL<1271> A_IWL<1270> A_IWL<1269> A_IWL<1268> A_IWL<1267> A_IWL<1266> A_IWL<1265> A_IWL<1264> A_IWL<1263> A_IWL<1262> A_IWL<1261> A_IWL<1260> A_IWL<1259> A_IWL<1258> A_IWL<1257> A_IWL<1256> A_IWL<1255> A_IWL<1254> A_IWL<1253> A_IWL<1252> A_IWL<1251> A_IWL<1250> A_IWL<1249> A_IWL<1248> A_IWL<1247> A_IWL<1246> A_IWL<1245> A_IWL<1244> A_IWL<1243> A_IWL<1242> A_IWL<1241> A_IWL<1240> A_IWL<1239> A_IWL<1238> A_IWL<1237> A_IWL<1236> A_IWL<1235> A_IWL<1234> A_IWL<1233> A_IWL<1232> A_IWL<1231> A_IWL<1230> A_IWL<1229> A_IWL<1228> A_IWL<1227> A_IWL<1226> A_IWL<1225> A_IWL<1224> A_IWL<1223> A_IWL<1222> A_IWL<1221> A_IWL<1220> A_IWL<1219> A_IWL<1218> A_IWL<1217> A_IWL<1216> A_IWL<1343> A_IWL<1342> A_IWL<1341> A_IWL<1340> A_IWL<1339> A_IWL<1338> A_IWL<1337> A_IWL<1336> A_IWL<1335> A_IWL<1334> A_IWL<1333> A_IWL<1332> A_IWL<1331> A_IWL<1330> A_IWL<1329> A_IWL<1328> A_IWL<1327> A_IWL<1326> A_IWL<1325> A_IWL<1324> A_IWL<1323> A_IWL<1322> A_IWL<1321> A_IWL<1320> A_IWL<1319> A_IWL<1318> A_IWL<1317> A_IWL<1316> A_IWL<1315> A_IWL<1314> A_IWL<1313> A_IWL<1312> A_IWL<1311> A_IWL<1310> A_IWL<1309> A_IWL<1308> A_IWL<1307> A_IWL<1306> A_IWL<1305> A_IWL<1304> A_IWL<1303> A_IWL<1302> A_IWL<1301> A_IWL<1300> A_IWL<1299> A_IWL<1298> A_IWL<1297> A_IWL<1296> A_IWL<1295> A_IWL<1294> A_IWL<1293> A_IWL<1292> A_IWL<1291> A_IWL<1290> A_IWL<1289> A_IWL<1288> A_IWL<1287> A_IWL<1286> A_IWL<1285> A_IWL<1284> A_IWL<1283> A_IWL<1282> A_IWL<1281> A_IWL<1280> B_BLC<41> B_BLC<40> B_BLC_TOP<41> B_BLC_TOP<40> B_BLT<41> B_BLT<40> B_BLT_TOP<41> B_BLT_TOP<40> B_IWL<1279> B_IWL<1278> B_IWL<1277> B_IWL<1276> B_IWL<1275> B_IWL<1274> B_IWL<1273> B_IWL<1272> B_IWL<1271> B_IWL<1270> B_IWL<1269> B_IWL<1268> B_IWL<1267> B_IWL<1266> B_IWL<1265> B_IWL<1264> B_IWL<1263> B_IWL<1262> B_IWL<1261> B_IWL<1260> B_IWL<1259> B_IWL<1258> B_IWL<1257> B_IWL<1256> B_IWL<1255> B_IWL<1254> B_IWL<1253> B_IWL<1252> B_IWL<1251> B_IWL<1250> B_IWL<1249> B_IWL<1248> B_IWL<1247> B_IWL<1246> B_IWL<1245> B_IWL<1244> B_IWL<1243> B_IWL<1242> B_IWL<1241> B_IWL<1240> B_IWL<1239> B_IWL<1238> B_IWL<1237> B_IWL<1236> B_IWL<1235> B_IWL<1234> B_IWL<1233> B_IWL<1232> B_IWL<1231> B_IWL<1230> B_IWL<1229> B_IWL<1228> B_IWL<1227> B_IWL<1226> B_IWL<1225> B_IWL<1224> B_IWL<1223> B_IWL<1222> B_IWL<1221> B_IWL<1220> B_IWL<1219> B_IWL<1218> B_IWL<1217> B_IWL<1216> B_IWL<1343> B_IWL<1342> B_IWL<1341> B_IWL<1340> B_IWL<1339> B_IWL<1338> B_IWL<1337> B_IWL<1336> B_IWL<1335> B_IWL<1334> B_IWL<1333> B_IWL<1332> B_IWL<1331> B_IWL<1330> B_IWL<1329> B_IWL<1328> B_IWL<1327> B_IWL<1326> B_IWL<1325> B_IWL<1324> B_IWL<1323> B_IWL<1322> B_IWL<1321> B_IWL<1320> B_IWL<1319> B_IWL<1318> B_IWL<1317> B_IWL<1316> B_IWL<1315> B_IWL<1314> B_IWL<1313> B_IWL<1312> B_IWL<1311> B_IWL<1310> B_IWL<1309> B_IWL<1308> B_IWL<1307> B_IWL<1306> B_IWL<1305> B_IWL<1304> B_IWL<1303> B_IWL<1302> B_IWL<1301> B_IWL<1300> B_IWL<1299> B_IWL<1298> B_IWL<1297> B_IWL<1296> B_IWL<1295> B_IWL<1294> B_IWL<1293> B_IWL<1292> B_IWL<1291> B_IWL<1290> B_IWL<1289> B_IWL<1288> B_IWL<1287> B_IWL<1286> B_IWL<1285> B_IWL<1284> B_IWL<1283> B_IWL<1282> B_IWL<1281> B_IWL<1280> VDD_CORE VSS / RM_IHPSG13_256x32_c2_2P_COLUMN_pcell_0 +XCOL<19> A_BLC<39> A_BLC<38> A_BLC_TOP<39> A_BLC_TOP<38> A_BLT<39> A_BLT<38> A_BLT_TOP<39> A_BLT_TOP<38> A_IWL<1215> A_IWL<1214> A_IWL<1213> A_IWL<1212> A_IWL<1211> A_IWL<1210> A_IWL<1209> A_IWL<1208> A_IWL<1207> A_IWL<1206> A_IWL<1205> A_IWL<1204> A_IWL<1203> A_IWL<1202> A_IWL<1201> A_IWL<1200> A_IWL<1199> A_IWL<1198> A_IWL<1197> A_IWL<1196> A_IWL<1195> A_IWL<1194> A_IWL<1193> A_IWL<1192> A_IWL<1191> A_IWL<1190> A_IWL<1189> A_IWL<1188> A_IWL<1187> A_IWL<1186> A_IWL<1185> A_IWL<1184> A_IWL<1183> A_IWL<1182> A_IWL<1181> A_IWL<1180> A_IWL<1179> A_IWL<1178> A_IWL<1177> A_IWL<1176> A_IWL<1175> A_IWL<1174> A_IWL<1173> A_IWL<1172> A_IWL<1171> A_IWL<1170> A_IWL<1169> A_IWL<1168> A_IWL<1167> A_IWL<1166> A_IWL<1165> A_IWL<1164> A_IWL<1163> A_IWL<1162> A_IWL<1161> A_IWL<1160> A_IWL<1159> A_IWL<1158> A_IWL<1157> A_IWL<1156> A_IWL<1155> A_IWL<1154> A_IWL<1153> A_IWL<1152> A_IWL<1279> A_IWL<1278> A_IWL<1277> A_IWL<1276> A_IWL<1275> A_IWL<1274> A_IWL<1273> A_IWL<1272> A_IWL<1271> A_IWL<1270> A_IWL<1269> A_IWL<1268> A_IWL<1267> A_IWL<1266> A_IWL<1265> A_IWL<1264> A_IWL<1263> A_IWL<1262> A_IWL<1261> A_IWL<1260> A_IWL<1259> A_IWL<1258> A_IWL<1257> A_IWL<1256> A_IWL<1255> A_IWL<1254> A_IWL<1253> A_IWL<1252> A_IWL<1251> A_IWL<1250> A_IWL<1249> A_IWL<1248> A_IWL<1247> A_IWL<1246> A_IWL<1245> A_IWL<1244> A_IWL<1243> A_IWL<1242> A_IWL<1241> A_IWL<1240> A_IWL<1239> A_IWL<1238> A_IWL<1237> A_IWL<1236> A_IWL<1235> A_IWL<1234> A_IWL<1233> A_IWL<1232> A_IWL<1231> A_IWL<1230> A_IWL<1229> A_IWL<1228> A_IWL<1227> A_IWL<1226> A_IWL<1225> A_IWL<1224> A_IWL<1223> A_IWL<1222> A_IWL<1221> A_IWL<1220> A_IWL<1219> A_IWL<1218> A_IWL<1217> A_IWL<1216> B_BLC<39> B_BLC<38> B_BLC_TOP<39> B_BLC_TOP<38> B_BLT<39> B_BLT<38> B_BLT_TOP<39> B_BLT_TOP<38> B_IWL<1215> B_IWL<1214> B_IWL<1213> B_IWL<1212> B_IWL<1211> B_IWL<1210> B_IWL<1209> B_IWL<1208> B_IWL<1207> B_IWL<1206> B_IWL<1205> B_IWL<1204> B_IWL<1203> B_IWL<1202> B_IWL<1201> B_IWL<1200> B_IWL<1199> B_IWL<1198> B_IWL<1197> B_IWL<1196> B_IWL<1195> B_IWL<1194> B_IWL<1193> B_IWL<1192> B_IWL<1191> B_IWL<1190> B_IWL<1189> B_IWL<1188> B_IWL<1187> B_IWL<1186> B_IWL<1185> B_IWL<1184> B_IWL<1183> B_IWL<1182> B_IWL<1181> B_IWL<1180> B_IWL<1179> B_IWL<1178> B_IWL<1177> B_IWL<1176> B_IWL<1175> B_IWL<1174> B_IWL<1173> B_IWL<1172> B_IWL<1171> B_IWL<1170> B_IWL<1169> B_IWL<1168> B_IWL<1167> B_IWL<1166> B_IWL<1165> B_IWL<1164> B_IWL<1163> B_IWL<1162> B_IWL<1161> B_IWL<1160> B_IWL<1159> B_IWL<1158> B_IWL<1157> B_IWL<1156> B_IWL<1155> B_IWL<1154> B_IWL<1153> B_IWL<1152> B_IWL<1279> B_IWL<1278> B_IWL<1277> B_IWL<1276> B_IWL<1275> B_IWL<1274> B_IWL<1273> B_IWL<1272> B_IWL<1271> B_IWL<1270> B_IWL<1269> B_IWL<1268> B_IWL<1267> B_IWL<1266> B_IWL<1265> B_IWL<1264> B_IWL<1263> B_IWL<1262> B_IWL<1261> B_IWL<1260> B_IWL<1259> B_IWL<1258> B_IWL<1257> B_IWL<1256> B_IWL<1255> B_IWL<1254> B_IWL<1253> B_IWL<1252> B_IWL<1251> B_IWL<1250> B_IWL<1249> B_IWL<1248> B_IWL<1247> B_IWL<1246> B_IWL<1245> B_IWL<1244> B_IWL<1243> B_IWL<1242> B_IWL<1241> B_IWL<1240> B_IWL<1239> B_IWL<1238> B_IWL<1237> B_IWL<1236> B_IWL<1235> B_IWL<1234> B_IWL<1233> B_IWL<1232> B_IWL<1231> B_IWL<1230> B_IWL<1229> B_IWL<1228> B_IWL<1227> B_IWL<1226> B_IWL<1225> B_IWL<1224> B_IWL<1223> B_IWL<1222> B_IWL<1221> B_IWL<1220> B_IWL<1219> B_IWL<1218> B_IWL<1217> B_IWL<1216> VDD_CORE VSS / RM_IHPSG13_256x32_c2_2P_COLUMN_pcell_0 +XCOL<18> A_BLC<37> A_BLC<36> A_BLC_TOP<37> A_BLC_TOP<36> A_BLT<37> A_BLT<36> A_BLT_TOP<37> A_BLT_TOP<36> A_IWL<1151> A_IWL<1150> A_IWL<1149> A_IWL<1148> A_IWL<1147> A_IWL<1146> A_IWL<1145> A_IWL<1144> A_IWL<1143> A_IWL<1142> A_IWL<1141> A_IWL<1140> A_IWL<1139> A_IWL<1138> A_IWL<1137> A_IWL<1136> A_IWL<1135> A_IWL<1134> A_IWL<1133> A_IWL<1132> A_IWL<1131> A_IWL<1130> A_IWL<1129> A_IWL<1128> A_IWL<1127> A_IWL<1126> A_IWL<1125> A_IWL<1124> A_IWL<1123> A_IWL<1122> A_IWL<1121> A_IWL<1120> A_IWL<1119> A_IWL<1118> A_IWL<1117> A_IWL<1116> A_IWL<1115> A_IWL<1114> A_IWL<1113> A_IWL<1112> A_IWL<1111> A_IWL<1110> A_IWL<1109> A_IWL<1108> A_IWL<1107> A_IWL<1106> A_IWL<1105> A_IWL<1104> A_IWL<1103> A_IWL<1102> A_IWL<1101> A_IWL<1100> A_IWL<1099> A_IWL<1098> A_IWL<1097> A_IWL<1096> A_IWL<1095> A_IWL<1094> A_IWL<1093> A_IWL<1092> A_IWL<1091> A_IWL<1090> A_IWL<1089> A_IWL<1088> A_IWL<1215> A_IWL<1214> A_IWL<1213> A_IWL<1212> A_IWL<1211> A_IWL<1210> A_IWL<1209> A_IWL<1208> A_IWL<1207> A_IWL<1206> A_IWL<1205> A_IWL<1204> A_IWL<1203> A_IWL<1202> A_IWL<1201> A_IWL<1200> A_IWL<1199> A_IWL<1198> A_IWL<1197> A_IWL<1196> A_IWL<1195> A_IWL<1194> A_IWL<1193> A_IWL<1192> A_IWL<1191> A_IWL<1190> A_IWL<1189> A_IWL<1188> A_IWL<1187> A_IWL<1186> A_IWL<1185> A_IWL<1184> A_IWL<1183> A_IWL<1182> A_IWL<1181> A_IWL<1180> A_IWL<1179> A_IWL<1178> A_IWL<1177> A_IWL<1176> A_IWL<1175> A_IWL<1174> A_IWL<1173> A_IWL<1172> A_IWL<1171> A_IWL<1170> A_IWL<1169> A_IWL<1168> A_IWL<1167> A_IWL<1166> A_IWL<1165> A_IWL<1164> A_IWL<1163> A_IWL<1162> A_IWL<1161> A_IWL<1160> A_IWL<1159> A_IWL<1158> A_IWL<1157> A_IWL<1156> A_IWL<1155> A_IWL<1154> A_IWL<1153> A_IWL<1152> B_BLC<37> B_BLC<36> B_BLC_TOP<37> B_BLC_TOP<36> B_BLT<37> B_BLT<36> B_BLT_TOP<37> B_BLT_TOP<36> B_IWL<1151> B_IWL<1150> B_IWL<1149> B_IWL<1148> B_IWL<1147> B_IWL<1146> B_IWL<1145> B_IWL<1144> B_IWL<1143> B_IWL<1142> B_IWL<1141> B_IWL<1140> B_IWL<1139> B_IWL<1138> B_IWL<1137> B_IWL<1136> B_IWL<1135> B_IWL<1134> B_IWL<1133> B_IWL<1132> B_IWL<1131> B_IWL<1130> B_IWL<1129> B_IWL<1128> B_IWL<1127> B_IWL<1126> B_IWL<1125> B_IWL<1124> B_IWL<1123> B_IWL<1122> B_IWL<1121> B_IWL<1120> B_IWL<1119> B_IWL<1118> B_IWL<1117> B_IWL<1116> B_IWL<1115> B_IWL<1114> B_IWL<1113> B_IWL<1112> B_IWL<1111> B_IWL<1110> B_IWL<1109> B_IWL<1108> B_IWL<1107> B_IWL<1106> B_IWL<1105> B_IWL<1104> B_IWL<1103> B_IWL<1102> B_IWL<1101> B_IWL<1100> B_IWL<1099> B_IWL<1098> B_IWL<1097> B_IWL<1096> B_IWL<1095> B_IWL<1094> B_IWL<1093> B_IWL<1092> B_IWL<1091> B_IWL<1090> B_IWL<1089> B_IWL<1088> B_IWL<1215> B_IWL<1214> B_IWL<1213> B_IWL<1212> B_IWL<1211> B_IWL<1210> B_IWL<1209> B_IWL<1208> B_IWL<1207> B_IWL<1206> B_IWL<1205> B_IWL<1204> B_IWL<1203> B_IWL<1202> B_IWL<1201> B_IWL<1200> B_IWL<1199> B_IWL<1198> B_IWL<1197> B_IWL<1196> B_IWL<1195> B_IWL<1194> B_IWL<1193> B_IWL<1192> B_IWL<1191> B_IWL<1190> B_IWL<1189> B_IWL<1188> B_IWL<1187> B_IWL<1186> B_IWL<1185> B_IWL<1184> B_IWL<1183> B_IWL<1182> B_IWL<1181> B_IWL<1180> B_IWL<1179> B_IWL<1178> B_IWL<1177> B_IWL<1176> B_IWL<1175> B_IWL<1174> B_IWL<1173> B_IWL<1172> B_IWL<1171> B_IWL<1170> B_IWL<1169> B_IWL<1168> B_IWL<1167> B_IWL<1166> B_IWL<1165> B_IWL<1164> B_IWL<1163> B_IWL<1162> B_IWL<1161> B_IWL<1160> B_IWL<1159> B_IWL<1158> B_IWL<1157> B_IWL<1156> B_IWL<1155> B_IWL<1154> B_IWL<1153> B_IWL<1152> VDD_CORE VSS / RM_IHPSG13_256x32_c2_2P_COLUMN_pcell_0 +XCOL<17> A_BLC<35> A_BLC<34> A_BLC_TOP<35> A_BLC_TOP<34> A_BLT<35> A_BLT<34> A_BLT_TOP<35> A_BLT_TOP<34> A_IWL<1087> A_IWL<1086> A_IWL<1085> A_IWL<1084> A_IWL<1083> A_IWL<1082> A_IWL<1081> A_IWL<1080> A_IWL<1079> A_IWL<1078> A_IWL<1077> A_IWL<1076> A_IWL<1075> A_IWL<1074> A_IWL<1073> A_IWL<1072> A_IWL<1071> A_IWL<1070> A_IWL<1069> A_IWL<1068> A_IWL<1067> A_IWL<1066> A_IWL<1065> A_IWL<1064> A_IWL<1063> A_IWL<1062> A_IWL<1061> A_IWL<1060> A_IWL<1059> A_IWL<1058> A_IWL<1057> A_IWL<1056> A_IWL<1055> A_IWL<1054> A_IWL<1053> A_IWL<1052> A_IWL<1051> A_IWL<1050> A_IWL<1049> A_IWL<1048> A_IWL<1047> A_IWL<1046> A_IWL<1045> A_IWL<1044> A_IWL<1043> A_IWL<1042> A_IWL<1041> A_IWL<1040> A_IWL<1039> A_IWL<1038> A_IWL<1037> A_IWL<1036> A_IWL<1035> A_IWL<1034> A_IWL<1033> A_IWL<1032> A_IWL<1031> A_IWL<1030> A_IWL<1029> A_IWL<1028> A_IWL<1027> A_IWL<1026> A_IWL<1025> A_IWL<1024> A_IWL<1151> A_IWL<1150> A_IWL<1149> A_IWL<1148> A_IWL<1147> A_IWL<1146> A_IWL<1145> A_IWL<1144> A_IWL<1143> A_IWL<1142> A_IWL<1141> A_IWL<1140> A_IWL<1139> A_IWL<1138> A_IWL<1137> A_IWL<1136> A_IWL<1135> A_IWL<1134> A_IWL<1133> A_IWL<1132> A_IWL<1131> A_IWL<1130> A_IWL<1129> A_IWL<1128> A_IWL<1127> A_IWL<1126> A_IWL<1125> A_IWL<1124> A_IWL<1123> A_IWL<1122> A_IWL<1121> A_IWL<1120> A_IWL<1119> A_IWL<1118> A_IWL<1117> A_IWL<1116> A_IWL<1115> A_IWL<1114> A_IWL<1113> A_IWL<1112> A_IWL<1111> A_IWL<1110> A_IWL<1109> A_IWL<1108> A_IWL<1107> A_IWL<1106> A_IWL<1105> A_IWL<1104> A_IWL<1103> A_IWL<1102> A_IWL<1101> A_IWL<1100> A_IWL<1099> A_IWL<1098> A_IWL<1097> A_IWL<1096> A_IWL<1095> A_IWL<1094> A_IWL<1093> A_IWL<1092> A_IWL<1091> A_IWL<1090> A_IWL<1089> A_IWL<1088> B_BLC<35> B_BLC<34> B_BLC_TOP<35> B_BLC_TOP<34> B_BLT<35> B_BLT<34> B_BLT_TOP<35> B_BLT_TOP<34> B_IWL<1087> B_IWL<1086> B_IWL<1085> B_IWL<1084> B_IWL<1083> B_IWL<1082> B_IWL<1081> B_IWL<1080> B_IWL<1079> B_IWL<1078> B_IWL<1077> B_IWL<1076> B_IWL<1075> B_IWL<1074> B_IWL<1073> B_IWL<1072> B_IWL<1071> B_IWL<1070> B_IWL<1069> B_IWL<1068> B_IWL<1067> B_IWL<1066> B_IWL<1065> B_IWL<1064> B_IWL<1063> B_IWL<1062> B_IWL<1061> B_IWL<1060> B_IWL<1059> B_IWL<1058> B_IWL<1057> B_IWL<1056> B_IWL<1055> B_IWL<1054> B_IWL<1053> B_IWL<1052> B_IWL<1051> B_IWL<1050> B_IWL<1049> B_IWL<1048> B_IWL<1047> B_IWL<1046> B_IWL<1045> B_IWL<1044> B_IWL<1043> B_IWL<1042> B_IWL<1041> B_IWL<1040> B_IWL<1039> B_IWL<1038> B_IWL<1037> B_IWL<1036> B_IWL<1035> B_IWL<1034> B_IWL<1033> B_IWL<1032> B_IWL<1031> B_IWL<1030> B_IWL<1029> B_IWL<1028> B_IWL<1027> B_IWL<1026> B_IWL<1025> B_IWL<1024> B_IWL<1151> B_IWL<1150> B_IWL<1149> B_IWL<1148> B_IWL<1147> B_IWL<1146> B_IWL<1145> B_IWL<1144> B_IWL<1143> B_IWL<1142> B_IWL<1141> B_IWL<1140> B_IWL<1139> B_IWL<1138> B_IWL<1137> B_IWL<1136> B_IWL<1135> B_IWL<1134> B_IWL<1133> B_IWL<1132> B_IWL<1131> B_IWL<1130> B_IWL<1129> B_IWL<1128> B_IWL<1127> B_IWL<1126> B_IWL<1125> B_IWL<1124> B_IWL<1123> B_IWL<1122> B_IWL<1121> B_IWL<1120> B_IWL<1119> B_IWL<1118> B_IWL<1117> B_IWL<1116> B_IWL<1115> B_IWL<1114> B_IWL<1113> B_IWL<1112> B_IWL<1111> B_IWL<1110> B_IWL<1109> B_IWL<1108> B_IWL<1107> B_IWL<1106> B_IWL<1105> B_IWL<1104> B_IWL<1103> B_IWL<1102> B_IWL<1101> B_IWL<1100> B_IWL<1099> B_IWL<1098> B_IWL<1097> B_IWL<1096> B_IWL<1095> B_IWL<1094> B_IWL<1093> B_IWL<1092> B_IWL<1091> B_IWL<1090> B_IWL<1089> B_IWL<1088> VDD_CORE VSS / RM_IHPSG13_256x32_c2_2P_COLUMN_pcell_0 +XCOL<16> A_BLC<33> A_BLC<32> A_BLC_TOP<33> A_BLC_TOP<32> A_BLT<33> A_BLT<32> A_BLT_TOP<33> A_BLT_TOP<32> A_IWL<1023> A_IWL<1022> A_IWL<1021> A_IWL<1020> A_IWL<1019> A_IWL<1018> A_IWL<1017> A_IWL<1016> A_IWL<1015> A_IWL<1014> A_IWL<1013> A_IWL<1012> A_IWL<1011> A_IWL<1010> A_IWL<1009> A_IWL<1008> A_IWL<1007> A_IWL<1006> A_IWL<1005> A_IWL<1004> A_IWL<1003> A_IWL<1002> A_IWL<1001> A_IWL<1000> A_IWL<999> A_IWL<998> A_IWL<997> A_IWL<996> A_IWL<995> A_IWL<994> A_IWL<993> A_IWL<992> A_IWL<991> A_IWL<990> A_IWL<989> A_IWL<988> A_IWL<987> A_IWL<986> A_IWL<985> A_IWL<984> A_IWL<983> A_IWL<982> A_IWL<981> A_IWL<980> A_IWL<979> A_IWL<978> A_IWL<977> A_IWL<976> A_IWL<975> A_IWL<974> A_IWL<973> A_IWL<972> A_IWL<971> A_IWL<970> A_IWL<969> A_IWL<968> A_IWL<967> A_IWL<966> A_IWL<965> A_IWL<964> A_IWL<963> A_IWL<962> A_IWL<961> A_IWL<960> A_IWL<1087> A_IWL<1086> A_IWL<1085> A_IWL<1084> A_IWL<1083> A_IWL<1082> A_IWL<1081> A_IWL<1080> A_IWL<1079> A_IWL<1078> A_IWL<1077> A_IWL<1076> A_IWL<1075> A_IWL<1074> A_IWL<1073> A_IWL<1072> A_IWL<1071> A_IWL<1070> A_IWL<1069> A_IWL<1068> A_IWL<1067> A_IWL<1066> A_IWL<1065> A_IWL<1064> A_IWL<1063> A_IWL<1062> A_IWL<1061> A_IWL<1060> A_IWL<1059> A_IWL<1058> A_IWL<1057> A_IWL<1056> A_IWL<1055> A_IWL<1054> A_IWL<1053> A_IWL<1052> A_IWL<1051> A_IWL<1050> A_IWL<1049> A_IWL<1048> A_IWL<1047> A_IWL<1046> A_IWL<1045> A_IWL<1044> A_IWL<1043> A_IWL<1042> A_IWL<1041> A_IWL<1040> A_IWL<1039> A_IWL<1038> A_IWL<1037> A_IWL<1036> A_IWL<1035> A_IWL<1034> A_IWL<1033> A_IWL<1032> A_IWL<1031> A_IWL<1030> A_IWL<1029> A_IWL<1028> A_IWL<1027> A_IWL<1026> A_IWL<1025> A_IWL<1024> B_BLC<33> B_BLC<32> B_BLC_TOP<33> B_BLC_TOP<32> B_BLT<33> B_BLT<32> B_BLT_TOP<33> B_BLT_TOP<32> B_IWL<1023> B_IWL<1022> B_IWL<1021> B_IWL<1020> B_IWL<1019> B_IWL<1018> B_IWL<1017> B_IWL<1016> B_IWL<1015> B_IWL<1014> B_IWL<1013> B_IWL<1012> B_IWL<1011> B_IWL<1010> B_IWL<1009> B_IWL<1008> B_IWL<1007> B_IWL<1006> B_IWL<1005> B_IWL<1004> B_IWL<1003> B_IWL<1002> B_IWL<1001> B_IWL<1000> B_IWL<999> B_IWL<998> B_IWL<997> B_IWL<996> B_IWL<995> B_IWL<994> B_IWL<993> B_IWL<992> B_IWL<991> B_IWL<990> B_IWL<989> B_IWL<988> B_IWL<987> B_IWL<986> B_IWL<985> B_IWL<984> B_IWL<983> B_IWL<982> B_IWL<981> B_IWL<980> B_IWL<979> B_IWL<978> B_IWL<977> B_IWL<976> B_IWL<975> B_IWL<974> B_IWL<973> B_IWL<972> B_IWL<971> B_IWL<970> B_IWL<969> B_IWL<968> B_IWL<967> B_IWL<966> B_IWL<965> B_IWL<964> B_IWL<963> B_IWL<962> B_IWL<961> B_IWL<960> B_IWL<1087> B_IWL<1086> B_IWL<1085> B_IWL<1084> B_IWL<1083> B_IWL<1082> B_IWL<1081> B_IWL<1080> B_IWL<1079> B_IWL<1078> B_IWL<1077> B_IWL<1076> B_IWL<1075> B_IWL<1074> B_IWL<1073> B_IWL<1072> B_IWL<1071> B_IWL<1070> B_IWL<1069> B_IWL<1068> B_IWL<1067> B_IWL<1066> B_IWL<1065> B_IWL<1064> B_IWL<1063> B_IWL<1062> B_IWL<1061> B_IWL<1060> B_IWL<1059> B_IWL<1058> B_IWL<1057> B_IWL<1056> B_IWL<1055> B_IWL<1054> B_IWL<1053> B_IWL<1052> B_IWL<1051> B_IWL<1050> B_IWL<1049> B_IWL<1048> B_IWL<1047> B_IWL<1046> B_IWL<1045> B_IWL<1044> B_IWL<1043> B_IWL<1042> B_IWL<1041> B_IWL<1040> B_IWL<1039> B_IWL<1038> B_IWL<1037> B_IWL<1036> B_IWL<1035> B_IWL<1034> B_IWL<1033> B_IWL<1032> B_IWL<1031> B_IWL<1030> B_IWL<1029> B_IWL<1028> B_IWL<1027> B_IWL<1026> B_IWL<1025> B_IWL<1024> VDD_CORE VSS / RM_IHPSG13_256x32_c2_2P_COLUMN_pcell_0 +XCOL<15> A_BLC<31> A_BLC<30> A_BLC_TOP<31> A_BLC_TOP<30> A_BLT<31> A_BLT<30> A_BLT_TOP<31> A_BLT_TOP<30> A_IWL<959> A_IWL<958> A_IWL<957> A_IWL<956> A_IWL<955> A_IWL<954> A_IWL<953> A_IWL<952> A_IWL<951> A_IWL<950> A_IWL<949> A_IWL<948> A_IWL<947> A_IWL<946> A_IWL<945> A_IWL<944> A_IWL<943> A_IWL<942> A_IWL<941> A_IWL<940> A_IWL<939> A_IWL<938> A_IWL<937> A_IWL<936> A_IWL<935> A_IWL<934> A_IWL<933> A_IWL<932> A_IWL<931> A_IWL<930> A_IWL<929> A_IWL<928> A_IWL<927> A_IWL<926> A_IWL<925> A_IWL<924> A_IWL<923> A_IWL<922> A_IWL<921> A_IWL<920> A_IWL<919> A_IWL<918> A_IWL<917> A_IWL<916> A_IWL<915> A_IWL<914> A_IWL<913> A_IWL<912> A_IWL<911> A_IWL<910> A_IWL<909> A_IWL<908> A_IWL<907> A_IWL<906> A_IWL<905> A_IWL<904> A_IWL<903> A_IWL<902> A_IWL<901> A_IWL<900> A_IWL<899> A_IWL<898> A_IWL<897> A_IWL<896> A_IWL<1023> A_IWL<1022> A_IWL<1021> A_IWL<1020> A_IWL<1019> A_IWL<1018> A_IWL<1017> A_IWL<1016> A_IWL<1015> A_IWL<1014> A_IWL<1013> A_IWL<1012> A_IWL<1011> A_IWL<1010> A_IWL<1009> A_IWL<1008> A_IWL<1007> A_IWL<1006> A_IWL<1005> A_IWL<1004> A_IWL<1003> A_IWL<1002> A_IWL<1001> A_IWL<1000> A_IWL<999> A_IWL<998> A_IWL<997> A_IWL<996> A_IWL<995> A_IWL<994> A_IWL<993> A_IWL<992> A_IWL<991> A_IWL<990> A_IWL<989> A_IWL<988> A_IWL<987> A_IWL<986> A_IWL<985> A_IWL<984> A_IWL<983> A_IWL<982> A_IWL<981> A_IWL<980> A_IWL<979> A_IWL<978> A_IWL<977> A_IWL<976> A_IWL<975> A_IWL<974> A_IWL<973> A_IWL<972> A_IWL<971> A_IWL<970> A_IWL<969> A_IWL<968> A_IWL<967> A_IWL<966> A_IWL<965> A_IWL<964> A_IWL<963> A_IWL<962> A_IWL<961> A_IWL<960> B_BLC<31> B_BLC<30> B_BLC_TOP<31> B_BLC_TOP<30> B_BLT<31> B_BLT<30> B_BLT_TOP<31> B_BLT_TOP<30> B_IWL<959> B_IWL<958> B_IWL<957> B_IWL<956> B_IWL<955> B_IWL<954> B_IWL<953> B_IWL<952> B_IWL<951> B_IWL<950> B_IWL<949> B_IWL<948> B_IWL<947> B_IWL<946> B_IWL<945> B_IWL<944> B_IWL<943> B_IWL<942> B_IWL<941> B_IWL<940> B_IWL<939> B_IWL<938> B_IWL<937> B_IWL<936> B_IWL<935> B_IWL<934> B_IWL<933> B_IWL<932> B_IWL<931> B_IWL<930> B_IWL<929> B_IWL<928> B_IWL<927> B_IWL<926> B_IWL<925> B_IWL<924> B_IWL<923> B_IWL<922> B_IWL<921> B_IWL<920> B_IWL<919> B_IWL<918> B_IWL<917> B_IWL<916> B_IWL<915> B_IWL<914> B_IWL<913> B_IWL<912> B_IWL<911> B_IWL<910> B_IWL<909> B_IWL<908> B_IWL<907> B_IWL<906> B_IWL<905> B_IWL<904> B_IWL<903> B_IWL<902> B_IWL<901> B_IWL<900> B_IWL<899> B_IWL<898> B_IWL<897> B_IWL<896> B_IWL<1023> B_IWL<1022> B_IWL<1021> B_IWL<1020> B_IWL<1019> B_IWL<1018> B_IWL<1017> B_IWL<1016> B_IWL<1015> B_IWL<1014> B_IWL<1013> B_IWL<1012> B_IWL<1011> B_IWL<1010> B_IWL<1009> B_IWL<1008> B_IWL<1007> B_IWL<1006> B_IWL<1005> B_IWL<1004> B_IWL<1003> B_IWL<1002> B_IWL<1001> B_IWL<1000> B_IWL<999> B_IWL<998> B_IWL<997> B_IWL<996> B_IWL<995> B_IWL<994> B_IWL<993> B_IWL<992> B_IWL<991> B_IWL<990> B_IWL<989> B_IWL<988> B_IWL<987> B_IWL<986> B_IWL<985> B_IWL<984> B_IWL<983> B_IWL<982> B_IWL<981> B_IWL<980> B_IWL<979> B_IWL<978> B_IWL<977> B_IWL<976> B_IWL<975> B_IWL<974> B_IWL<973> B_IWL<972> B_IWL<971> B_IWL<970> B_IWL<969> B_IWL<968> B_IWL<967> B_IWL<966> B_IWL<965> B_IWL<964> B_IWL<963> B_IWL<962> B_IWL<961> B_IWL<960> VDD_CORE VSS / RM_IHPSG13_256x32_c2_2P_COLUMN_pcell_0 +XCOL<14> A_BLC<29> A_BLC<28> A_BLC_TOP<29> A_BLC_TOP<28> A_BLT<29> A_BLT<28> A_BLT_TOP<29> A_BLT_TOP<28> A_IWL<895> A_IWL<894> A_IWL<893> A_IWL<892> A_IWL<891> A_IWL<890> A_IWL<889> A_IWL<888> A_IWL<887> A_IWL<886> A_IWL<885> A_IWL<884> A_IWL<883> A_IWL<882> A_IWL<881> A_IWL<880> A_IWL<879> A_IWL<878> A_IWL<877> A_IWL<876> A_IWL<875> A_IWL<874> A_IWL<873> A_IWL<872> A_IWL<871> A_IWL<870> A_IWL<869> A_IWL<868> A_IWL<867> A_IWL<866> A_IWL<865> A_IWL<864> A_IWL<863> A_IWL<862> A_IWL<861> A_IWL<860> A_IWL<859> A_IWL<858> A_IWL<857> A_IWL<856> A_IWL<855> A_IWL<854> A_IWL<853> A_IWL<852> A_IWL<851> A_IWL<850> A_IWL<849> A_IWL<848> A_IWL<847> A_IWL<846> A_IWL<845> A_IWL<844> A_IWL<843> A_IWL<842> A_IWL<841> A_IWL<840> A_IWL<839> A_IWL<838> A_IWL<837> A_IWL<836> A_IWL<835> A_IWL<834> A_IWL<833> A_IWL<832> A_IWL<959> A_IWL<958> A_IWL<957> A_IWL<956> A_IWL<955> A_IWL<954> A_IWL<953> A_IWL<952> A_IWL<951> A_IWL<950> A_IWL<949> A_IWL<948> A_IWL<947> A_IWL<946> A_IWL<945> A_IWL<944> A_IWL<943> A_IWL<942> A_IWL<941> A_IWL<940> A_IWL<939> A_IWL<938> A_IWL<937> A_IWL<936> A_IWL<935> A_IWL<934> A_IWL<933> A_IWL<932> A_IWL<931> A_IWL<930> A_IWL<929> A_IWL<928> A_IWL<927> A_IWL<926> A_IWL<925> A_IWL<924> A_IWL<923> A_IWL<922> A_IWL<921> A_IWL<920> A_IWL<919> A_IWL<918> A_IWL<917> A_IWL<916> A_IWL<915> A_IWL<914> A_IWL<913> A_IWL<912> A_IWL<911> A_IWL<910> A_IWL<909> A_IWL<908> A_IWL<907> A_IWL<906> A_IWL<905> A_IWL<904> A_IWL<903> A_IWL<902> A_IWL<901> A_IWL<900> A_IWL<899> A_IWL<898> A_IWL<897> A_IWL<896> B_BLC<29> B_BLC<28> B_BLC_TOP<29> B_BLC_TOP<28> B_BLT<29> B_BLT<28> B_BLT_TOP<29> B_BLT_TOP<28> B_IWL<895> B_IWL<894> B_IWL<893> B_IWL<892> B_IWL<891> B_IWL<890> B_IWL<889> B_IWL<888> B_IWL<887> B_IWL<886> B_IWL<885> B_IWL<884> B_IWL<883> B_IWL<882> B_IWL<881> B_IWL<880> B_IWL<879> B_IWL<878> B_IWL<877> B_IWL<876> B_IWL<875> B_IWL<874> B_IWL<873> B_IWL<872> B_IWL<871> B_IWL<870> B_IWL<869> B_IWL<868> B_IWL<867> B_IWL<866> B_IWL<865> B_IWL<864> B_IWL<863> B_IWL<862> B_IWL<861> B_IWL<860> B_IWL<859> B_IWL<858> B_IWL<857> B_IWL<856> B_IWL<855> B_IWL<854> B_IWL<853> B_IWL<852> B_IWL<851> B_IWL<850> B_IWL<849> B_IWL<848> B_IWL<847> B_IWL<846> B_IWL<845> B_IWL<844> B_IWL<843> B_IWL<842> B_IWL<841> B_IWL<840> B_IWL<839> B_IWL<838> B_IWL<837> B_IWL<836> B_IWL<835> B_IWL<834> B_IWL<833> B_IWL<832> B_IWL<959> B_IWL<958> B_IWL<957> B_IWL<956> B_IWL<955> B_IWL<954> B_IWL<953> B_IWL<952> B_IWL<951> B_IWL<950> B_IWL<949> B_IWL<948> B_IWL<947> B_IWL<946> B_IWL<945> B_IWL<944> B_IWL<943> B_IWL<942> B_IWL<941> B_IWL<940> B_IWL<939> B_IWL<938> B_IWL<937> B_IWL<936> B_IWL<935> B_IWL<934> B_IWL<933> B_IWL<932> B_IWL<931> B_IWL<930> B_IWL<929> B_IWL<928> B_IWL<927> B_IWL<926> B_IWL<925> B_IWL<924> B_IWL<923> B_IWL<922> B_IWL<921> B_IWL<920> B_IWL<919> B_IWL<918> B_IWL<917> B_IWL<916> B_IWL<915> B_IWL<914> B_IWL<913> B_IWL<912> B_IWL<911> B_IWL<910> B_IWL<909> B_IWL<908> B_IWL<907> B_IWL<906> B_IWL<905> B_IWL<904> B_IWL<903> B_IWL<902> B_IWL<901> B_IWL<900> B_IWL<899> B_IWL<898> B_IWL<897> B_IWL<896> VDD_CORE VSS / RM_IHPSG13_256x32_c2_2P_COLUMN_pcell_0 +XCOL<13> A_BLC<27> A_BLC<26> A_BLC_TOP<27> A_BLC_TOP<26> A_BLT<27> A_BLT<26> A_BLT_TOP<27> A_BLT_TOP<26> A_IWL<831> A_IWL<830> A_IWL<829> A_IWL<828> A_IWL<827> A_IWL<826> A_IWL<825> A_IWL<824> A_IWL<823> A_IWL<822> A_IWL<821> A_IWL<820> A_IWL<819> A_IWL<818> A_IWL<817> A_IWL<816> A_IWL<815> A_IWL<814> A_IWL<813> A_IWL<812> A_IWL<811> A_IWL<810> A_IWL<809> A_IWL<808> A_IWL<807> A_IWL<806> A_IWL<805> A_IWL<804> A_IWL<803> A_IWL<802> A_IWL<801> A_IWL<800> A_IWL<799> A_IWL<798> A_IWL<797> A_IWL<796> A_IWL<795> A_IWL<794> A_IWL<793> A_IWL<792> A_IWL<791> A_IWL<790> A_IWL<789> A_IWL<788> A_IWL<787> A_IWL<786> A_IWL<785> A_IWL<784> A_IWL<783> A_IWL<782> A_IWL<781> A_IWL<780> A_IWL<779> A_IWL<778> A_IWL<777> A_IWL<776> A_IWL<775> A_IWL<774> A_IWL<773> A_IWL<772> A_IWL<771> A_IWL<770> A_IWL<769> A_IWL<768> A_IWL<895> A_IWL<894> A_IWL<893> A_IWL<892> A_IWL<891> A_IWL<890> A_IWL<889> A_IWL<888> A_IWL<887> A_IWL<886> A_IWL<885> A_IWL<884> A_IWL<883> A_IWL<882> A_IWL<881> A_IWL<880> A_IWL<879> A_IWL<878> A_IWL<877> A_IWL<876> A_IWL<875> A_IWL<874> A_IWL<873> A_IWL<872> A_IWL<871> A_IWL<870> A_IWL<869> A_IWL<868> A_IWL<867> A_IWL<866> A_IWL<865> A_IWL<864> A_IWL<863> A_IWL<862> A_IWL<861> A_IWL<860> A_IWL<859> A_IWL<858> A_IWL<857> A_IWL<856> A_IWL<855> A_IWL<854> A_IWL<853> A_IWL<852> A_IWL<851> A_IWL<850> A_IWL<849> A_IWL<848> A_IWL<847> A_IWL<846> A_IWL<845> A_IWL<844> A_IWL<843> A_IWL<842> A_IWL<841> A_IWL<840> A_IWL<839> A_IWL<838> A_IWL<837> A_IWL<836> A_IWL<835> A_IWL<834> A_IWL<833> A_IWL<832> B_BLC<27> B_BLC<26> B_BLC_TOP<27> B_BLC_TOP<26> B_BLT<27> B_BLT<26> B_BLT_TOP<27> B_BLT_TOP<26> B_IWL<831> B_IWL<830> B_IWL<829> B_IWL<828> B_IWL<827> B_IWL<826> B_IWL<825> B_IWL<824> B_IWL<823> B_IWL<822> B_IWL<821> B_IWL<820> B_IWL<819> B_IWL<818> B_IWL<817> B_IWL<816> B_IWL<815> B_IWL<814> B_IWL<813> B_IWL<812> B_IWL<811> B_IWL<810> B_IWL<809> B_IWL<808> B_IWL<807> B_IWL<806> B_IWL<805> B_IWL<804> B_IWL<803> B_IWL<802> B_IWL<801> B_IWL<800> B_IWL<799> B_IWL<798> B_IWL<797> B_IWL<796> B_IWL<795> B_IWL<794> B_IWL<793> B_IWL<792> B_IWL<791> B_IWL<790> B_IWL<789> B_IWL<788> B_IWL<787> B_IWL<786> B_IWL<785> B_IWL<784> B_IWL<783> B_IWL<782> B_IWL<781> B_IWL<780> B_IWL<779> B_IWL<778> B_IWL<777> B_IWL<776> B_IWL<775> B_IWL<774> B_IWL<773> B_IWL<772> B_IWL<771> B_IWL<770> B_IWL<769> B_IWL<768> B_IWL<895> B_IWL<894> B_IWL<893> B_IWL<892> B_IWL<891> B_IWL<890> B_IWL<889> B_IWL<888> B_IWL<887> B_IWL<886> B_IWL<885> B_IWL<884> B_IWL<883> B_IWL<882> B_IWL<881> B_IWL<880> B_IWL<879> B_IWL<878> B_IWL<877> B_IWL<876> B_IWL<875> B_IWL<874> B_IWL<873> B_IWL<872> B_IWL<871> B_IWL<870> B_IWL<869> B_IWL<868> B_IWL<867> B_IWL<866> B_IWL<865> B_IWL<864> B_IWL<863> B_IWL<862> B_IWL<861> B_IWL<860> B_IWL<859> B_IWL<858> B_IWL<857> B_IWL<856> B_IWL<855> B_IWL<854> B_IWL<853> B_IWL<852> B_IWL<851> B_IWL<850> B_IWL<849> B_IWL<848> B_IWL<847> B_IWL<846> B_IWL<845> B_IWL<844> B_IWL<843> B_IWL<842> B_IWL<841> B_IWL<840> B_IWL<839> B_IWL<838> B_IWL<837> B_IWL<836> B_IWL<835> B_IWL<834> B_IWL<833> B_IWL<832> VDD_CORE VSS / RM_IHPSG13_256x32_c2_2P_COLUMN_pcell_0 +XCOL<12> A_BLC<25> A_BLC<24> A_BLC_TOP<25> A_BLC_TOP<24> A_BLT<25> A_BLT<24> A_BLT_TOP<25> A_BLT_TOP<24> A_IWL<767> A_IWL<766> A_IWL<765> A_IWL<764> A_IWL<763> A_IWL<762> A_IWL<761> A_IWL<760> A_IWL<759> A_IWL<758> A_IWL<757> A_IWL<756> A_IWL<755> A_IWL<754> A_IWL<753> A_IWL<752> A_IWL<751> A_IWL<750> A_IWL<749> A_IWL<748> A_IWL<747> A_IWL<746> A_IWL<745> A_IWL<744> A_IWL<743> A_IWL<742> A_IWL<741> A_IWL<740> A_IWL<739> A_IWL<738> A_IWL<737> A_IWL<736> A_IWL<735> A_IWL<734> A_IWL<733> A_IWL<732> A_IWL<731> A_IWL<730> A_IWL<729> A_IWL<728> A_IWL<727> A_IWL<726> A_IWL<725> A_IWL<724> A_IWL<723> A_IWL<722> A_IWL<721> A_IWL<720> A_IWL<719> A_IWL<718> A_IWL<717> A_IWL<716> A_IWL<715> A_IWL<714> A_IWL<713> A_IWL<712> A_IWL<711> A_IWL<710> A_IWL<709> A_IWL<708> A_IWL<707> A_IWL<706> A_IWL<705> A_IWL<704> A_IWL<831> A_IWL<830> A_IWL<829> A_IWL<828> A_IWL<827> A_IWL<826> A_IWL<825> A_IWL<824> A_IWL<823> A_IWL<822> A_IWL<821> A_IWL<820> A_IWL<819> A_IWL<818> A_IWL<817> A_IWL<816> A_IWL<815> A_IWL<814> A_IWL<813> A_IWL<812> A_IWL<811> A_IWL<810> A_IWL<809> A_IWL<808> A_IWL<807> A_IWL<806> A_IWL<805> A_IWL<804> A_IWL<803> A_IWL<802> A_IWL<801> A_IWL<800> A_IWL<799> A_IWL<798> A_IWL<797> A_IWL<796> A_IWL<795> A_IWL<794> A_IWL<793> A_IWL<792> A_IWL<791> A_IWL<790> A_IWL<789> A_IWL<788> A_IWL<787> A_IWL<786> A_IWL<785> A_IWL<784> A_IWL<783> A_IWL<782> A_IWL<781> A_IWL<780> A_IWL<779> A_IWL<778> A_IWL<777> A_IWL<776> A_IWL<775> A_IWL<774> A_IWL<773> A_IWL<772> A_IWL<771> A_IWL<770> A_IWL<769> A_IWL<768> B_BLC<25> B_BLC<24> B_BLC_TOP<25> B_BLC_TOP<24> B_BLT<25> B_BLT<24> B_BLT_TOP<25> B_BLT_TOP<24> B_IWL<767> B_IWL<766> B_IWL<765> B_IWL<764> B_IWL<763> B_IWL<762> B_IWL<761> B_IWL<760> B_IWL<759> B_IWL<758> B_IWL<757> B_IWL<756> B_IWL<755> B_IWL<754> B_IWL<753> B_IWL<752> B_IWL<751> B_IWL<750> B_IWL<749> B_IWL<748> B_IWL<747> B_IWL<746> B_IWL<745> B_IWL<744> B_IWL<743> B_IWL<742> B_IWL<741> B_IWL<740> B_IWL<739> B_IWL<738> B_IWL<737> B_IWL<736> B_IWL<735> B_IWL<734> B_IWL<733> B_IWL<732> B_IWL<731> B_IWL<730> B_IWL<729> B_IWL<728> B_IWL<727> B_IWL<726> B_IWL<725> B_IWL<724> B_IWL<723> B_IWL<722> B_IWL<721> B_IWL<720> B_IWL<719> B_IWL<718> B_IWL<717> B_IWL<716> B_IWL<715> B_IWL<714> B_IWL<713> B_IWL<712> B_IWL<711> B_IWL<710> B_IWL<709> B_IWL<708> B_IWL<707> B_IWL<706> B_IWL<705> B_IWL<704> B_IWL<831> B_IWL<830> B_IWL<829> B_IWL<828> B_IWL<827> B_IWL<826> B_IWL<825> B_IWL<824> B_IWL<823> B_IWL<822> B_IWL<821> B_IWL<820> B_IWL<819> B_IWL<818> B_IWL<817> B_IWL<816> B_IWL<815> B_IWL<814> B_IWL<813> B_IWL<812> B_IWL<811> B_IWL<810> B_IWL<809> B_IWL<808> B_IWL<807> B_IWL<806> B_IWL<805> B_IWL<804> B_IWL<803> B_IWL<802> B_IWL<801> B_IWL<800> B_IWL<799> B_IWL<798> B_IWL<797> B_IWL<796> B_IWL<795> B_IWL<794> B_IWL<793> B_IWL<792> B_IWL<791> B_IWL<790> B_IWL<789> B_IWL<788> B_IWL<787> B_IWL<786> B_IWL<785> B_IWL<784> B_IWL<783> B_IWL<782> B_IWL<781> B_IWL<780> B_IWL<779> B_IWL<778> B_IWL<777> B_IWL<776> B_IWL<775> B_IWL<774> B_IWL<773> B_IWL<772> B_IWL<771> B_IWL<770> B_IWL<769> B_IWL<768> VDD_CORE VSS / RM_IHPSG13_256x32_c2_2P_COLUMN_pcell_0 +XCOL<11> A_BLC<23> A_BLC<22> A_BLC_TOP<23> A_BLC_TOP<22> A_BLT<23> A_BLT<22> A_BLT_TOP<23> A_BLT_TOP<22> A_IWL<703> A_IWL<702> A_IWL<701> A_IWL<700> A_IWL<699> A_IWL<698> A_IWL<697> A_IWL<696> A_IWL<695> A_IWL<694> A_IWL<693> A_IWL<692> A_IWL<691> A_IWL<690> A_IWL<689> A_IWL<688> A_IWL<687> A_IWL<686> A_IWL<685> A_IWL<684> A_IWL<683> A_IWL<682> A_IWL<681> A_IWL<680> A_IWL<679> A_IWL<678> A_IWL<677> A_IWL<676> A_IWL<675> A_IWL<674> A_IWL<673> A_IWL<672> A_IWL<671> A_IWL<670> A_IWL<669> A_IWL<668> A_IWL<667> A_IWL<666> A_IWL<665> A_IWL<664> A_IWL<663> A_IWL<662> A_IWL<661> A_IWL<660> A_IWL<659> A_IWL<658> A_IWL<657> A_IWL<656> A_IWL<655> A_IWL<654> A_IWL<653> A_IWL<652> A_IWL<651> A_IWL<650> A_IWL<649> A_IWL<648> A_IWL<647> A_IWL<646> A_IWL<645> A_IWL<644> A_IWL<643> A_IWL<642> A_IWL<641> A_IWL<640> A_IWL<767> A_IWL<766> A_IWL<765> A_IWL<764> A_IWL<763> A_IWL<762> A_IWL<761> A_IWL<760> A_IWL<759> A_IWL<758> A_IWL<757> A_IWL<756> A_IWL<755> A_IWL<754> A_IWL<753> A_IWL<752> A_IWL<751> A_IWL<750> A_IWL<749> A_IWL<748> A_IWL<747> A_IWL<746> A_IWL<745> A_IWL<744> A_IWL<743> A_IWL<742> A_IWL<741> A_IWL<740> A_IWL<739> A_IWL<738> A_IWL<737> A_IWL<736> A_IWL<735> A_IWL<734> A_IWL<733> A_IWL<732> A_IWL<731> A_IWL<730> A_IWL<729> A_IWL<728> A_IWL<727> A_IWL<726> A_IWL<725> A_IWL<724> A_IWL<723> A_IWL<722> A_IWL<721> A_IWL<720> A_IWL<719> A_IWL<718> A_IWL<717> A_IWL<716> A_IWL<715> A_IWL<714> A_IWL<713> A_IWL<712> A_IWL<711> A_IWL<710> A_IWL<709> A_IWL<708> A_IWL<707> A_IWL<706> A_IWL<705> A_IWL<704> B_BLC<23> B_BLC<22> B_BLC_TOP<23> B_BLC_TOP<22> B_BLT<23> B_BLT<22> B_BLT_TOP<23> B_BLT_TOP<22> B_IWL<703> B_IWL<702> B_IWL<701> B_IWL<700> B_IWL<699> B_IWL<698> B_IWL<697> B_IWL<696> B_IWL<695> B_IWL<694> B_IWL<693> B_IWL<692> B_IWL<691> B_IWL<690> B_IWL<689> B_IWL<688> B_IWL<687> B_IWL<686> B_IWL<685> B_IWL<684> B_IWL<683> B_IWL<682> B_IWL<681> B_IWL<680> B_IWL<679> B_IWL<678> B_IWL<677> B_IWL<676> B_IWL<675> B_IWL<674> B_IWL<673> B_IWL<672> B_IWL<671> B_IWL<670> B_IWL<669> B_IWL<668> B_IWL<667> B_IWL<666> B_IWL<665> B_IWL<664> B_IWL<663> B_IWL<662> B_IWL<661> B_IWL<660> B_IWL<659> B_IWL<658> B_IWL<657> B_IWL<656> B_IWL<655> B_IWL<654> B_IWL<653> B_IWL<652> B_IWL<651> B_IWL<650> B_IWL<649> B_IWL<648> B_IWL<647> B_IWL<646> B_IWL<645> B_IWL<644> B_IWL<643> B_IWL<642> B_IWL<641> B_IWL<640> B_IWL<767> B_IWL<766> B_IWL<765> B_IWL<764> B_IWL<763> B_IWL<762> B_IWL<761> B_IWL<760> B_IWL<759> B_IWL<758> B_IWL<757> B_IWL<756> B_IWL<755> B_IWL<754> B_IWL<753> B_IWL<752> B_IWL<751> B_IWL<750> B_IWL<749> B_IWL<748> B_IWL<747> B_IWL<746> B_IWL<745> B_IWL<744> B_IWL<743> B_IWL<742> B_IWL<741> B_IWL<740> B_IWL<739> B_IWL<738> B_IWL<737> B_IWL<736> B_IWL<735> B_IWL<734> B_IWL<733> B_IWL<732> B_IWL<731> B_IWL<730> B_IWL<729> B_IWL<728> B_IWL<727> B_IWL<726> B_IWL<725> B_IWL<724> B_IWL<723> B_IWL<722> B_IWL<721> B_IWL<720> B_IWL<719> B_IWL<718> B_IWL<717> B_IWL<716> B_IWL<715> B_IWL<714> B_IWL<713> B_IWL<712> B_IWL<711> B_IWL<710> B_IWL<709> B_IWL<708> B_IWL<707> B_IWL<706> B_IWL<705> B_IWL<704> VDD_CORE VSS / RM_IHPSG13_256x32_c2_2P_COLUMN_pcell_0 +XCOL<10> A_BLC<21> A_BLC<20> A_BLC_TOP<21> A_BLC_TOP<20> A_BLT<21> A_BLT<20> A_BLT_TOP<21> A_BLT_TOP<20> A_IWL<639> A_IWL<638> A_IWL<637> A_IWL<636> A_IWL<635> A_IWL<634> A_IWL<633> A_IWL<632> A_IWL<631> A_IWL<630> A_IWL<629> A_IWL<628> A_IWL<627> A_IWL<626> A_IWL<625> A_IWL<624> A_IWL<623> A_IWL<622> A_IWL<621> A_IWL<620> A_IWL<619> A_IWL<618> A_IWL<617> A_IWL<616> A_IWL<615> A_IWL<614> A_IWL<613> A_IWL<612> A_IWL<611> A_IWL<610> A_IWL<609> A_IWL<608> A_IWL<607> A_IWL<606> A_IWL<605> A_IWL<604> A_IWL<603> A_IWL<602> A_IWL<601> A_IWL<600> A_IWL<599> A_IWL<598> A_IWL<597> A_IWL<596> A_IWL<595> A_IWL<594> A_IWL<593> A_IWL<592> A_IWL<591> A_IWL<590> A_IWL<589> A_IWL<588> A_IWL<587> A_IWL<586> A_IWL<585> A_IWL<584> A_IWL<583> A_IWL<582> A_IWL<581> A_IWL<580> A_IWL<579> A_IWL<578> A_IWL<577> A_IWL<576> A_IWL<703> A_IWL<702> A_IWL<701> A_IWL<700> A_IWL<699> A_IWL<698> A_IWL<697> A_IWL<696> A_IWL<695> A_IWL<694> A_IWL<693> A_IWL<692> A_IWL<691> A_IWL<690> A_IWL<689> A_IWL<688> A_IWL<687> A_IWL<686> A_IWL<685> A_IWL<684> A_IWL<683> A_IWL<682> A_IWL<681> A_IWL<680> A_IWL<679> A_IWL<678> A_IWL<677> A_IWL<676> A_IWL<675> A_IWL<674> A_IWL<673> A_IWL<672> A_IWL<671> A_IWL<670> A_IWL<669> A_IWL<668> A_IWL<667> A_IWL<666> A_IWL<665> A_IWL<664> A_IWL<663> A_IWL<662> A_IWL<661> A_IWL<660> A_IWL<659> A_IWL<658> A_IWL<657> A_IWL<656> A_IWL<655> A_IWL<654> A_IWL<653> A_IWL<652> A_IWL<651> A_IWL<650> A_IWL<649> A_IWL<648> A_IWL<647> A_IWL<646> A_IWL<645> A_IWL<644> A_IWL<643> A_IWL<642> A_IWL<641> A_IWL<640> B_BLC<21> B_BLC<20> B_BLC_TOP<21> B_BLC_TOP<20> B_BLT<21> B_BLT<20> B_BLT_TOP<21> B_BLT_TOP<20> B_IWL<639> B_IWL<638> B_IWL<637> B_IWL<636> B_IWL<635> B_IWL<634> B_IWL<633> B_IWL<632> B_IWL<631> B_IWL<630> B_IWL<629> B_IWL<628> B_IWL<627> B_IWL<626> B_IWL<625> B_IWL<624> B_IWL<623> B_IWL<622> B_IWL<621> B_IWL<620> B_IWL<619> B_IWL<618> B_IWL<617> B_IWL<616> B_IWL<615> B_IWL<614> B_IWL<613> B_IWL<612> B_IWL<611> B_IWL<610> B_IWL<609> B_IWL<608> B_IWL<607> B_IWL<606> B_IWL<605> B_IWL<604> B_IWL<603> B_IWL<602> B_IWL<601> B_IWL<600> B_IWL<599> B_IWL<598> B_IWL<597> B_IWL<596> B_IWL<595> B_IWL<594> B_IWL<593> B_IWL<592> B_IWL<591> B_IWL<590> B_IWL<589> B_IWL<588> B_IWL<587> B_IWL<586> B_IWL<585> B_IWL<584> B_IWL<583> B_IWL<582> B_IWL<581> B_IWL<580> B_IWL<579> B_IWL<578> B_IWL<577> B_IWL<576> B_IWL<703> B_IWL<702> B_IWL<701> B_IWL<700> B_IWL<699> B_IWL<698> B_IWL<697> B_IWL<696> B_IWL<695> B_IWL<694> B_IWL<693> B_IWL<692> B_IWL<691> B_IWL<690> B_IWL<689> B_IWL<688> B_IWL<687> B_IWL<686> B_IWL<685> B_IWL<684> B_IWL<683> B_IWL<682> B_IWL<681> B_IWL<680> B_IWL<679> B_IWL<678> B_IWL<677> B_IWL<676> B_IWL<675> B_IWL<674> B_IWL<673> B_IWL<672> B_IWL<671> B_IWL<670> B_IWL<669> B_IWL<668> B_IWL<667> B_IWL<666> B_IWL<665> B_IWL<664> B_IWL<663> B_IWL<662> B_IWL<661> B_IWL<660> B_IWL<659> B_IWL<658> B_IWL<657> B_IWL<656> B_IWL<655> B_IWL<654> B_IWL<653> B_IWL<652> B_IWL<651> B_IWL<650> B_IWL<649> B_IWL<648> B_IWL<647> B_IWL<646> B_IWL<645> B_IWL<644> B_IWL<643> B_IWL<642> B_IWL<641> B_IWL<640> VDD_CORE VSS / RM_IHPSG13_256x32_c2_2P_COLUMN_pcell_0 +XCOL<9> A_BLC<19> A_BLC<18> A_BLC_TOP<19> A_BLC_TOP<18> A_BLT<19> A_BLT<18> A_BLT_TOP<19> A_BLT_TOP<18> A_IWL<575> A_IWL<574> A_IWL<573> A_IWL<572> A_IWL<571> A_IWL<570> A_IWL<569> A_IWL<568> A_IWL<567> A_IWL<566> A_IWL<565> A_IWL<564> A_IWL<563> A_IWL<562> A_IWL<561> A_IWL<560> A_IWL<559> A_IWL<558> A_IWL<557> A_IWL<556> A_IWL<555> A_IWL<554> A_IWL<553> A_IWL<552> A_IWL<551> A_IWL<550> A_IWL<549> A_IWL<548> A_IWL<547> A_IWL<546> A_IWL<545> A_IWL<544> A_IWL<543> A_IWL<542> A_IWL<541> A_IWL<540> A_IWL<539> A_IWL<538> A_IWL<537> A_IWL<536> A_IWL<535> A_IWL<534> A_IWL<533> A_IWL<532> A_IWL<531> A_IWL<530> A_IWL<529> A_IWL<528> A_IWL<527> A_IWL<526> A_IWL<525> A_IWL<524> A_IWL<523> A_IWL<522> A_IWL<521> A_IWL<520> A_IWL<519> A_IWL<518> A_IWL<517> A_IWL<516> A_IWL<515> A_IWL<514> A_IWL<513> A_IWL<512> A_IWL<639> A_IWL<638> A_IWL<637> A_IWL<636> A_IWL<635> A_IWL<634> A_IWL<633> A_IWL<632> A_IWL<631> A_IWL<630> A_IWL<629> A_IWL<628> A_IWL<627> A_IWL<626> A_IWL<625> A_IWL<624> A_IWL<623> A_IWL<622> A_IWL<621> A_IWL<620> A_IWL<619> A_IWL<618> A_IWL<617> A_IWL<616> A_IWL<615> A_IWL<614> A_IWL<613> A_IWL<612> A_IWL<611> A_IWL<610> A_IWL<609> A_IWL<608> A_IWL<607> A_IWL<606> A_IWL<605> A_IWL<604> A_IWL<603> A_IWL<602> A_IWL<601> A_IWL<600> A_IWL<599> A_IWL<598> A_IWL<597> A_IWL<596> A_IWL<595> A_IWL<594> A_IWL<593> A_IWL<592> A_IWL<591> A_IWL<590> A_IWL<589> A_IWL<588> A_IWL<587> A_IWL<586> A_IWL<585> A_IWL<584> A_IWL<583> A_IWL<582> A_IWL<581> A_IWL<580> A_IWL<579> A_IWL<578> A_IWL<577> A_IWL<576> B_BLC<19> B_BLC<18> B_BLC_TOP<19> B_BLC_TOP<18> B_BLT<19> B_BLT<18> B_BLT_TOP<19> B_BLT_TOP<18> B_IWL<575> B_IWL<574> B_IWL<573> B_IWL<572> B_IWL<571> B_IWL<570> B_IWL<569> B_IWL<568> B_IWL<567> B_IWL<566> B_IWL<565> B_IWL<564> B_IWL<563> B_IWL<562> B_IWL<561> B_IWL<560> B_IWL<559> B_IWL<558> B_IWL<557> B_IWL<556> B_IWL<555> B_IWL<554> B_IWL<553> B_IWL<552> B_IWL<551> B_IWL<550> B_IWL<549> B_IWL<548> B_IWL<547> B_IWL<546> B_IWL<545> B_IWL<544> B_IWL<543> B_IWL<542> B_IWL<541> B_IWL<540> B_IWL<539> B_IWL<538> B_IWL<537> B_IWL<536> B_IWL<535> B_IWL<534> B_IWL<533> B_IWL<532> B_IWL<531> B_IWL<530> B_IWL<529> B_IWL<528> B_IWL<527> B_IWL<526> B_IWL<525> B_IWL<524> B_IWL<523> B_IWL<522> B_IWL<521> B_IWL<520> B_IWL<519> B_IWL<518> B_IWL<517> B_IWL<516> B_IWL<515> B_IWL<514> B_IWL<513> B_IWL<512> B_IWL<639> B_IWL<638> B_IWL<637> B_IWL<636> B_IWL<635> B_IWL<634> B_IWL<633> B_IWL<632> B_IWL<631> B_IWL<630> B_IWL<629> B_IWL<628> B_IWL<627> B_IWL<626> B_IWL<625> B_IWL<624> B_IWL<623> B_IWL<622> B_IWL<621> B_IWL<620> B_IWL<619> B_IWL<618> B_IWL<617> B_IWL<616> B_IWL<615> B_IWL<614> B_IWL<613> B_IWL<612> B_IWL<611> B_IWL<610> B_IWL<609> B_IWL<608> B_IWL<607> B_IWL<606> B_IWL<605> B_IWL<604> B_IWL<603> B_IWL<602> B_IWL<601> B_IWL<600> B_IWL<599> B_IWL<598> B_IWL<597> B_IWL<596> B_IWL<595> B_IWL<594> B_IWL<593> B_IWL<592> B_IWL<591> B_IWL<590> B_IWL<589> B_IWL<588> B_IWL<587> B_IWL<586> B_IWL<585> B_IWL<584> B_IWL<583> B_IWL<582> B_IWL<581> B_IWL<580> B_IWL<579> B_IWL<578> B_IWL<577> B_IWL<576> VDD_CORE VSS / RM_IHPSG13_256x32_c2_2P_COLUMN_pcell_0 +XCOL<8> A_BLC<17> A_BLC<16> A_BLC_TOP<17> A_BLC_TOP<16> A_BLT<17> A_BLT<16> A_BLT_TOP<17> A_BLT_TOP<16> A_IWL<511> A_IWL<510> A_IWL<509> A_IWL<508> A_IWL<507> A_IWL<506> A_IWL<505> A_IWL<504> A_IWL<503> A_IWL<502> A_IWL<501> A_IWL<500> A_IWL<499> A_IWL<498> A_IWL<497> A_IWL<496> A_IWL<495> A_IWL<494> A_IWL<493> A_IWL<492> A_IWL<491> A_IWL<490> A_IWL<489> A_IWL<488> A_IWL<487> A_IWL<486> A_IWL<485> A_IWL<484> A_IWL<483> A_IWL<482> A_IWL<481> A_IWL<480> A_IWL<479> A_IWL<478> A_IWL<477> A_IWL<476> A_IWL<475> A_IWL<474> A_IWL<473> A_IWL<472> A_IWL<471> A_IWL<470> A_IWL<469> A_IWL<468> A_IWL<467> A_IWL<466> A_IWL<465> A_IWL<464> A_IWL<463> A_IWL<462> A_IWL<461> A_IWL<460> A_IWL<459> A_IWL<458> A_IWL<457> A_IWL<456> A_IWL<455> A_IWL<454> A_IWL<453> A_IWL<452> A_IWL<451> A_IWL<450> A_IWL<449> A_IWL<448> A_IWL<575> A_IWL<574> A_IWL<573> A_IWL<572> A_IWL<571> A_IWL<570> A_IWL<569> A_IWL<568> A_IWL<567> A_IWL<566> A_IWL<565> A_IWL<564> A_IWL<563> A_IWL<562> A_IWL<561> A_IWL<560> A_IWL<559> A_IWL<558> A_IWL<557> A_IWL<556> A_IWL<555> A_IWL<554> A_IWL<553> A_IWL<552> A_IWL<551> A_IWL<550> A_IWL<549> A_IWL<548> A_IWL<547> A_IWL<546> A_IWL<545> A_IWL<544> A_IWL<543> A_IWL<542> A_IWL<541> A_IWL<540> A_IWL<539> A_IWL<538> A_IWL<537> A_IWL<536> A_IWL<535> A_IWL<534> A_IWL<533> A_IWL<532> A_IWL<531> A_IWL<530> A_IWL<529> A_IWL<528> A_IWL<527> A_IWL<526> A_IWL<525> A_IWL<524> A_IWL<523> A_IWL<522> A_IWL<521> A_IWL<520> A_IWL<519> A_IWL<518> A_IWL<517> A_IWL<516> A_IWL<515> A_IWL<514> A_IWL<513> A_IWL<512> B_BLC<17> B_BLC<16> B_BLC_TOP<17> B_BLC_TOP<16> B_BLT<17> B_BLT<16> B_BLT_TOP<17> B_BLT_TOP<16> B_IWL<511> B_IWL<510> B_IWL<509> B_IWL<508> B_IWL<507> B_IWL<506> B_IWL<505> B_IWL<504> B_IWL<503> B_IWL<502> B_IWL<501> B_IWL<500> B_IWL<499> B_IWL<498> B_IWL<497> B_IWL<496> B_IWL<495> B_IWL<494> B_IWL<493> B_IWL<492> B_IWL<491> B_IWL<490> B_IWL<489> B_IWL<488> B_IWL<487> B_IWL<486> B_IWL<485> B_IWL<484> B_IWL<483> B_IWL<482> B_IWL<481> B_IWL<480> B_IWL<479> B_IWL<478> B_IWL<477> B_IWL<476> B_IWL<475> B_IWL<474> B_IWL<473> B_IWL<472> B_IWL<471> B_IWL<470> B_IWL<469> B_IWL<468> B_IWL<467> B_IWL<466> B_IWL<465> B_IWL<464> B_IWL<463> B_IWL<462> B_IWL<461> B_IWL<460> B_IWL<459> B_IWL<458> B_IWL<457> B_IWL<456> B_IWL<455> B_IWL<454> B_IWL<453> B_IWL<452> B_IWL<451> B_IWL<450> B_IWL<449> B_IWL<448> B_IWL<575> B_IWL<574> B_IWL<573> B_IWL<572> B_IWL<571> B_IWL<570> B_IWL<569> B_IWL<568> B_IWL<567> B_IWL<566> B_IWL<565> B_IWL<564> B_IWL<563> B_IWL<562> B_IWL<561> B_IWL<560> B_IWL<559> B_IWL<558> B_IWL<557> B_IWL<556> B_IWL<555> B_IWL<554> B_IWL<553> B_IWL<552> B_IWL<551> B_IWL<550> B_IWL<549> B_IWL<548> B_IWL<547> B_IWL<546> B_IWL<545> B_IWL<544> B_IWL<543> B_IWL<542> B_IWL<541> B_IWL<540> B_IWL<539> B_IWL<538> B_IWL<537> B_IWL<536> B_IWL<535> B_IWL<534> B_IWL<533> B_IWL<532> B_IWL<531> B_IWL<530> B_IWL<529> B_IWL<528> B_IWL<527> B_IWL<526> B_IWL<525> B_IWL<524> B_IWL<523> B_IWL<522> B_IWL<521> B_IWL<520> B_IWL<519> B_IWL<518> B_IWL<517> B_IWL<516> B_IWL<515> B_IWL<514> B_IWL<513> B_IWL<512> VDD_CORE VSS / RM_IHPSG13_256x32_c2_2P_COLUMN_pcell_0 +XCOL<7> A_BLC<15> A_BLC<14> A_BLC_TOP<15> A_BLC_TOP<14> A_BLT<15> A_BLT<14> A_BLT_TOP<15> A_BLT_TOP<14> A_IWL<447> A_IWL<446> A_IWL<445> A_IWL<444> A_IWL<443> A_IWL<442> A_IWL<441> A_IWL<440> A_IWL<439> A_IWL<438> A_IWL<437> A_IWL<436> A_IWL<435> A_IWL<434> A_IWL<433> A_IWL<432> A_IWL<431> A_IWL<430> A_IWL<429> A_IWL<428> A_IWL<427> A_IWL<426> A_IWL<425> A_IWL<424> A_IWL<423> A_IWL<422> A_IWL<421> A_IWL<420> A_IWL<419> A_IWL<418> A_IWL<417> A_IWL<416> A_IWL<415> A_IWL<414> A_IWL<413> A_IWL<412> A_IWL<411> A_IWL<410> A_IWL<409> A_IWL<408> A_IWL<407> A_IWL<406> A_IWL<405> A_IWL<404> A_IWL<403> A_IWL<402> A_IWL<401> A_IWL<400> A_IWL<399> A_IWL<398> A_IWL<397> A_IWL<396> A_IWL<395> A_IWL<394> A_IWL<393> A_IWL<392> A_IWL<391> A_IWL<390> A_IWL<389> A_IWL<388> A_IWL<387> A_IWL<386> A_IWL<385> A_IWL<384> A_IWL<511> A_IWL<510> A_IWL<509> A_IWL<508> A_IWL<507> A_IWL<506> A_IWL<505> A_IWL<504> A_IWL<503> A_IWL<502> A_IWL<501> A_IWL<500> A_IWL<499> A_IWL<498> A_IWL<497> A_IWL<496> A_IWL<495> A_IWL<494> A_IWL<493> A_IWL<492> A_IWL<491> A_IWL<490> A_IWL<489> A_IWL<488> A_IWL<487> A_IWL<486> A_IWL<485> A_IWL<484> A_IWL<483> A_IWL<482> A_IWL<481> A_IWL<480> A_IWL<479> A_IWL<478> A_IWL<477> A_IWL<476> A_IWL<475> A_IWL<474> A_IWL<473> A_IWL<472> A_IWL<471> A_IWL<470> A_IWL<469> A_IWL<468> A_IWL<467> A_IWL<466> A_IWL<465> A_IWL<464> A_IWL<463> A_IWL<462> A_IWL<461> A_IWL<460> A_IWL<459> A_IWL<458> A_IWL<457> A_IWL<456> A_IWL<455> A_IWL<454> A_IWL<453> A_IWL<452> A_IWL<451> A_IWL<450> A_IWL<449> A_IWL<448> B_BLC<15> B_BLC<14> B_BLC_TOP<15> B_BLC_TOP<14> B_BLT<15> B_BLT<14> B_BLT_TOP<15> B_BLT_TOP<14> B_IWL<447> B_IWL<446> B_IWL<445> B_IWL<444> B_IWL<443> B_IWL<442> B_IWL<441> B_IWL<440> B_IWL<439> B_IWL<438> B_IWL<437> B_IWL<436> B_IWL<435> B_IWL<434> B_IWL<433> B_IWL<432> B_IWL<431> B_IWL<430> B_IWL<429> B_IWL<428> B_IWL<427> B_IWL<426> B_IWL<425> B_IWL<424> B_IWL<423> B_IWL<422> B_IWL<421> B_IWL<420> B_IWL<419> B_IWL<418> B_IWL<417> B_IWL<416> B_IWL<415> B_IWL<414> B_IWL<413> B_IWL<412> B_IWL<411> B_IWL<410> B_IWL<409> B_IWL<408> B_IWL<407> B_IWL<406> B_IWL<405> B_IWL<404> B_IWL<403> B_IWL<402> B_IWL<401> B_IWL<400> B_IWL<399> B_IWL<398> B_IWL<397> B_IWL<396> B_IWL<395> B_IWL<394> B_IWL<393> B_IWL<392> B_IWL<391> B_IWL<390> B_IWL<389> B_IWL<388> B_IWL<387> B_IWL<386> B_IWL<385> B_IWL<384> B_IWL<511> B_IWL<510> B_IWL<509> B_IWL<508> B_IWL<507> B_IWL<506> B_IWL<505> B_IWL<504> B_IWL<503> B_IWL<502> B_IWL<501> B_IWL<500> B_IWL<499> B_IWL<498> B_IWL<497> B_IWL<496> B_IWL<495> B_IWL<494> B_IWL<493> B_IWL<492> B_IWL<491> B_IWL<490> B_IWL<489> B_IWL<488> B_IWL<487> B_IWL<486> B_IWL<485> B_IWL<484> B_IWL<483> B_IWL<482> B_IWL<481> B_IWL<480> B_IWL<479> B_IWL<478> B_IWL<477> B_IWL<476> B_IWL<475> B_IWL<474> B_IWL<473> B_IWL<472> B_IWL<471> B_IWL<470> B_IWL<469> B_IWL<468> B_IWL<467> B_IWL<466> B_IWL<465> B_IWL<464> B_IWL<463> B_IWL<462> B_IWL<461> B_IWL<460> B_IWL<459> B_IWL<458> B_IWL<457> B_IWL<456> B_IWL<455> B_IWL<454> B_IWL<453> B_IWL<452> B_IWL<451> B_IWL<450> B_IWL<449> B_IWL<448> VDD_CORE VSS / RM_IHPSG13_256x32_c2_2P_COLUMN_pcell_0 +XCOL<6> A_BLC<13> A_BLC<12> A_BLC_TOP<13> A_BLC_TOP<12> A_BLT<13> A_BLT<12> A_BLT_TOP<13> A_BLT_TOP<12> A_IWL<383> A_IWL<382> A_IWL<381> A_IWL<380> A_IWL<379> A_IWL<378> A_IWL<377> A_IWL<376> A_IWL<375> A_IWL<374> A_IWL<373> A_IWL<372> A_IWL<371> A_IWL<370> A_IWL<369> A_IWL<368> A_IWL<367> A_IWL<366> A_IWL<365> A_IWL<364> A_IWL<363> A_IWL<362> A_IWL<361> A_IWL<360> A_IWL<359> A_IWL<358> A_IWL<357> A_IWL<356> A_IWL<355> A_IWL<354> A_IWL<353> A_IWL<352> A_IWL<351> A_IWL<350> A_IWL<349> A_IWL<348> A_IWL<347> A_IWL<346> A_IWL<345> A_IWL<344> A_IWL<343> A_IWL<342> A_IWL<341> A_IWL<340> A_IWL<339> A_IWL<338> A_IWL<337> A_IWL<336> A_IWL<335> A_IWL<334> A_IWL<333> A_IWL<332> A_IWL<331> A_IWL<330> A_IWL<329> A_IWL<328> A_IWL<327> A_IWL<326> A_IWL<325> A_IWL<324> A_IWL<323> A_IWL<322> A_IWL<321> A_IWL<320> A_IWL<447> A_IWL<446> A_IWL<445> A_IWL<444> A_IWL<443> A_IWL<442> A_IWL<441> A_IWL<440> A_IWL<439> A_IWL<438> A_IWL<437> A_IWL<436> A_IWL<435> A_IWL<434> A_IWL<433> A_IWL<432> A_IWL<431> A_IWL<430> A_IWL<429> A_IWL<428> A_IWL<427> A_IWL<426> A_IWL<425> A_IWL<424> A_IWL<423> A_IWL<422> A_IWL<421> A_IWL<420> A_IWL<419> A_IWL<418> A_IWL<417> A_IWL<416> A_IWL<415> A_IWL<414> A_IWL<413> A_IWL<412> A_IWL<411> A_IWL<410> A_IWL<409> A_IWL<408> A_IWL<407> A_IWL<406> A_IWL<405> A_IWL<404> A_IWL<403> A_IWL<402> A_IWL<401> A_IWL<400> A_IWL<399> A_IWL<398> A_IWL<397> A_IWL<396> A_IWL<395> A_IWL<394> A_IWL<393> A_IWL<392> A_IWL<391> A_IWL<390> A_IWL<389> A_IWL<388> A_IWL<387> A_IWL<386> A_IWL<385> A_IWL<384> B_BLC<13> B_BLC<12> B_BLC_TOP<13> B_BLC_TOP<12> B_BLT<13> B_BLT<12> B_BLT_TOP<13> B_BLT_TOP<12> B_IWL<383> B_IWL<382> B_IWL<381> B_IWL<380> B_IWL<379> B_IWL<378> B_IWL<377> B_IWL<376> B_IWL<375> B_IWL<374> B_IWL<373> B_IWL<372> B_IWL<371> B_IWL<370> B_IWL<369> B_IWL<368> B_IWL<367> B_IWL<366> B_IWL<365> B_IWL<364> B_IWL<363> B_IWL<362> B_IWL<361> B_IWL<360> B_IWL<359> B_IWL<358> B_IWL<357> B_IWL<356> B_IWL<355> B_IWL<354> B_IWL<353> B_IWL<352> B_IWL<351> B_IWL<350> B_IWL<349> B_IWL<348> B_IWL<347> B_IWL<346> B_IWL<345> B_IWL<344> B_IWL<343> B_IWL<342> B_IWL<341> B_IWL<340> B_IWL<339> B_IWL<338> B_IWL<337> B_IWL<336> B_IWL<335> B_IWL<334> B_IWL<333> B_IWL<332> B_IWL<331> B_IWL<330> B_IWL<329> B_IWL<328> B_IWL<327> B_IWL<326> B_IWL<325> B_IWL<324> B_IWL<323> B_IWL<322> B_IWL<321> B_IWL<320> B_IWL<447> B_IWL<446> B_IWL<445> B_IWL<444> B_IWL<443> B_IWL<442> B_IWL<441> B_IWL<440> B_IWL<439> B_IWL<438> B_IWL<437> B_IWL<436> B_IWL<435> B_IWL<434> B_IWL<433> B_IWL<432> B_IWL<431> B_IWL<430> B_IWL<429> B_IWL<428> B_IWL<427> B_IWL<426> B_IWL<425> B_IWL<424> B_IWL<423> B_IWL<422> B_IWL<421> B_IWL<420> B_IWL<419> B_IWL<418> B_IWL<417> B_IWL<416> B_IWL<415> B_IWL<414> B_IWL<413> B_IWL<412> B_IWL<411> B_IWL<410> B_IWL<409> B_IWL<408> B_IWL<407> B_IWL<406> B_IWL<405> B_IWL<404> B_IWL<403> B_IWL<402> B_IWL<401> B_IWL<400> B_IWL<399> B_IWL<398> B_IWL<397> B_IWL<396> B_IWL<395> B_IWL<394> B_IWL<393> B_IWL<392> B_IWL<391> B_IWL<390> B_IWL<389> B_IWL<388> B_IWL<387> B_IWL<386> B_IWL<385> B_IWL<384> VDD_CORE VSS / RM_IHPSG13_256x32_c2_2P_COLUMN_pcell_0 +XCOL<5> A_BLC<11> A_BLC<10> A_BLC_TOP<11> A_BLC_TOP<10> A_BLT<11> A_BLT<10> A_BLT_TOP<11> A_BLT_TOP<10> A_IWL<319> A_IWL<318> A_IWL<317> A_IWL<316> A_IWL<315> A_IWL<314> A_IWL<313> A_IWL<312> A_IWL<311> A_IWL<310> A_IWL<309> A_IWL<308> A_IWL<307> A_IWL<306> A_IWL<305> A_IWL<304> A_IWL<303> A_IWL<302> A_IWL<301> A_IWL<300> A_IWL<299> A_IWL<298> A_IWL<297> A_IWL<296> A_IWL<295> A_IWL<294> A_IWL<293> A_IWL<292> A_IWL<291> A_IWL<290> A_IWL<289> A_IWL<288> A_IWL<287> A_IWL<286> A_IWL<285> A_IWL<284> A_IWL<283> A_IWL<282> A_IWL<281> A_IWL<280> A_IWL<279> A_IWL<278> A_IWL<277> A_IWL<276> A_IWL<275> A_IWL<274> A_IWL<273> A_IWL<272> A_IWL<271> A_IWL<270> A_IWL<269> A_IWL<268> A_IWL<267> A_IWL<266> A_IWL<265> A_IWL<264> A_IWL<263> A_IWL<262> A_IWL<261> A_IWL<260> A_IWL<259> A_IWL<258> A_IWL<257> A_IWL<256> A_IWL<383> A_IWL<382> A_IWL<381> A_IWL<380> A_IWL<379> A_IWL<378> A_IWL<377> A_IWL<376> A_IWL<375> A_IWL<374> A_IWL<373> A_IWL<372> A_IWL<371> A_IWL<370> A_IWL<369> A_IWL<368> A_IWL<367> A_IWL<366> A_IWL<365> A_IWL<364> A_IWL<363> A_IWL<362> A_IWL<361> A_IWL<360> A_IWL<359> A_IWL<358> A_IWL<357> A_IWL<356> A_IWL<355> A_IWL<354> A_IWL<353> A_IWL<352> A_IWL<351> A_IWL<350> A_IWL<349> A_IWL<348> A_IWL<347> A_IWL<346> A_IWL<345> A_IWL<344> A_IWL<343> A_IWL<342> A_IWL<341> A_IWL<340> A_IWL<339> A_IWL<338> A_IWL<337> A_IWL<336> A_IWL<335> A_IWL<334> A_IWL<333> A_IWL<332> A_IWL<331> A_IWL<330> A_IWL<329> A_IWL<328> A_IWL<327> A_IWL<326> A_IWL<325> A_IWL<324> A_IWL<323> A_IWL<322> A_IWL<321> A_IWL<320> B_BLC<11> B_BLC<10> B_BLC_TOP<11> B_BLC_TOP<10> B_BLT<11> B_BLT<10> B_BLT_TOP<11> B_BLT_TOP<10> B_IWL<319> B_IWL<318> B_IWL<317> B_IWL<316> B_IWL<315> B_IWL<314> B_IWL<313> B_IWL<312> B_IWL<311> B_IWL<310> B_IWL<309> B_IWL<308> B_IWL<307> B_IWL<306> B_IWL<305> B_IWL<304> B_IWL<303> B_IWL<302> B_IWL<301> B_IWL<300> B_IWL<299> B_IWL<298> B_IWL<297> B_IWL<296> B_IWL<295> B_IWL<294> B_IWL<293> B_IWL<292> B_IWL<291> B_IWL<290> B_IWL<289> B_IWL<288> B_IWL<287> B_IWL<286> B_IWL<285> B_IWL<284> B_IWL<283> B_IWL<282> B_IWL<281> B_IWL<280> B_IWL<279> B_IWL<278> B_IWL<277> B_IWL<276> B_IWL<275> B_IWL<274> B_IWL<273> B_IWL<272> B_IWL<271> B_IWL<270> B_IWL<269> B_IWL<268> B_IWL<267> B_IWL<266> B_IWL<265> B_IWL<264> B_IWL<263> B_IWL<262> B_IWL<261> B_IWL<260> B_IWL<259> B_IWL<258> B_IWL<257> B_IWL<256> B_IWL<383> B_IWL<382> B_IWL<381> B_IWL<380> B_IWL<379> B_IWL<378> B_IWL<377> B_IWL<376> B_IWL<375> B_IWL<374> B_IWL<373> B_IWL<372> B_IWL<371> B_IWL<370> B_IWL<369> B_IWL<368> B_IWL<367> B_IWL<366> B_IWL<365> B_IWL<364> B_IWL<363> B_IWL<362> B_IWL<361> B_IWL<360> B_IWL<359> B_IWL<358> B_IWL<357> B_IWL<356> B_IWL<355> B_IWL<354> B_IWL<353> B_IWL<352> B_IWL<351> B_IWL<350> B_IWL<349> B_IWL<348> B_IWL<347> B_IWL<346> B_IWL<345> B_IWL<344> B_IWL<343> B_IWL<342> B_IWL<341> B_IWL<340> B_IWL<339> B_IWL<338> B_IWL<337> B_IWL<336> B_IWL<335> B_IWL<334> B_IWL<333> B_IWL<332> B_IWL<331> B_IWL<330> B_IWL<329> B_IWL<328> B_IWL<327> B_IWL<326> B_IWL<325> B_IWL<324> B_IWL<323> B_IWL<322> B_IWL<321> B_IWL<320> VDD_CORE VSS / RM_IHPSG13_256x32_c2_2P_COLUMN_pcell_0 +XCOL<4> A_BLC<9> A_BLC<8> A_BLC_TOP<9> A_BLC_TOP<8> A_BLT<9> A_BLT<8> A_BLT_TOP<9> A_BLT_TOP<8> A_IWL<255> A_IWL<254> A_IWL<253> A_IWL<252> A_IWL<251> A_IWL<250> A_IWL<249> A_IWL<248> A_IWL<247> A_IWL<246> A_IWL<245> A_IWL<244> A_IWL<243> A_IWL<242> A_IWL<241> A_IWL<240> A_IWL<239> A_IWL<238> A_IWL<237> A_IWL<236> A_IWL<235> A_IWL<234> A_IWL<233> A_IWL<232> A_IWL<231> A_IWL<230> A_IWL<229> A_IWL<228> A_IWL<227> A_IWL<226> A_IWL<225> A_IWL<224> A_IWL<223> A_IWL<222> A_IWL<221> A_IWL<220> A_IWL<219> A_IWL<218> A_IWL<217> A_IWL<216> A_IWL<215> A_IWL<214> A_IWL<213> A_IWL<212> A_IWL<211> A_IWL<210> A_IWL<209> A_IWL<208> A_IWL<207> A_IWL<206> A_IWL<205> A_IWL<204> A_IWL<203> A_IWL<202> A_IWL<201> A_IWL<200> A_IWL<199> A_IWL<198> A_IWL<197> A_IWL<196> A_IWL<195> A_IWL<194> A_IWL<193> A_IWL<192> A_IWL<319> A_IWL<318> A_IWL<317> A_IWL<316> A_IWL<315> A_IWL<314> A_IWL<313> A_IWL<312> A_IWL<311> A_IWL<310> A_IWL<309> A_IWL<308> A_IWL<307> A_IWL<306> A_IWL<305> A_IWL<304> A_IWL<303> A_IWL<302> A_IWL<301> A_IWL<300> A_IWL<299> A_IWL<298> A_IWL<297> A_IWL<296> A_IWL<295> A_IWL<294> A_IWL<293> A_IWL<292> A_IWL<291> A_IWL<290> A_IWL<289> A_IWL<288> A_IWL<287> A_IWL<286> A_IWL<285> A_IWL<284> A_IWL<283> A_IWL<282> A_IWL<281> A_IWL<280> A_IWL<279> A_IWL<278> A_IWL<277> A_IWL<276> A_IWL<275> A_IWL<274> A_IWL<273> A_IWL<272> A_IWL<271> A_IWL<270> A_IWL<269> A_IWL<268> A_IWL<267> A_IWL<266> A_IWL<265> A_IWL<264> A_IWL<263> A_IWL<262> A_IWL<261> A_IWL<260> A_IWL<259> A_IWL<258> A_IWL<257> A_IWL<256> B_BLC<9> B_BLC<8> B_BLC_TOP<9> B_BLC_TOP<8> B_BLT<9> B_BLT<8> B_BLT_TOP<9> B_BLT_TOP<8> B_IWL<255> B_IWL<254> B_IWL<253> B_IWL<252> B_IWL<251> B_IWL<250> B_IWL<249> B_IWL<248> B_IWL<247> B_IWL<246> B_IWL<245> B_IWL<244> B_IWL<243> B_IWL<242> B_IWL<241> B_IWL<240> B_IWL<239> B_IWL<238> B_IWL<237> B_IWL<236> B_IWL<235> B_IWL<234> B_IWL<233> B_IWL<232> B_IWL<231> B_IWL<230> B_IWL<229> B_IWL<228> B_IWL<227> B_IWL<226> B_IWL<225> B_IWL<224> B_IWL<223> B_IWL<222> B_IWL<221> B_IWL<220> B_IWL<219> B_IWL<218> B_IWL<217> B_IWL<216> B_IWL<215> B_IWL<214> B_IWL<213> B_IWL<212> B_IWL<211> B_IWL<210> B_IWL<209> B_IWL<208> B_IWL<207> B_IWL<206> B_IWL<205> B_IWL<204> B_IWL<203> B_IWL<202> B_IWL<201> B_IWL<200> B_IWL<199> B_IWL<198> B_IWL<197> B_IWL<196> B_IWL<195> B_IWL<194> B_IWL<193> B_IWL<192> B_IWL<319> B_IWL<318> B_IWL<317> B_IWL<316> B_IWL<315> B_IWL<314> B_IWL<313> B_IWL<312> B_IWL<311> B_IWL<310> B_IWL<309> B_IWL<308> B_IWL<307> B_IWL<306> B_IWL<305> B_IWL<304> B_IWL<303> B_IWL<302> B_IWL<301> B_IWL<300> B_IWL<299> B_IWL<298> B_IWL<297> B_IWL<296> B_IWL<295> B_IWL<294> B_IWL<293> B_IWL<292> B_IWL<291> B_IWL<290> B_IWL<289> B_IWL<288> B_IWL<287> B_IWL<286> B_IWL<285> B_IWL<284> B_IWL<283> B_IWL<282> B_IWL<281> B_IWL<280> B_IWL<279> B_IWL<278> B_IWL<277> B_IWL<276> B_IWL<275> B_IWL<274> B_IWL<273> B_IWL<272> B_IWL<271> B_IWL<270> B_IWL<269> B_IWL<268> B_IWL<267> B_IWL<266> B_IWL<265> B_IWL<264> B_IWL<263> B_IWL<262> B_IWL<261> B_IWL<260> B_IWL<259> B_IWL<258> B_IWL<257> B_IWL<256> VDD_CORE VSS / RM_IHPSG13_256x32_c2_2P_COLUMN_pcell_0 +XCOL<3> A_BLC<7> A_BLC<6> A_BLC_TOP<7> A_BLC_TOP<6> A_BLT<7> A_BLT<6> A_BLT_TOP<7> A_BLT_TOP<6> A_IWL<191> A_IWL<190> A_IWL<189> A_IWL<188> A_IWL<187> A_IWL<186> A_IWL<185> A_IWL<184> A_IWL<183> A_IWL<182> A_IWL<181> A_IWL<180> A_IWL<179> A_IWL<178> A_IWL<177> A_IWL<176> A_IWL<175> A_IWL<174> A_IWL<173> A_IWL<172> A_IWL<171> A_IWL<170> A_IWL<169> A_IWL<168> A_IWL<167> A_IWL<166> A_IWL<165> A_IWL<164> A_IWL<163> A_IWL<162> A_IWL<161> A_IWL<160> A_IWL<159> A_IWL<158> A_IWL<157> A_IWL<156> A_IWL<155> A_IWL<154> A_IWL<153> A_IWL<152> A_IWL<151> A_IWL<150> A_IWL<149> A_IWL<148> A_IWL<147> A_IWL<146> A_IWL<145> A_IWL<144> A_IWL<143> A_IWL<142> A_IWL<141> A_IWL<140> A_IWL<139> A_IWL<138> A_IWL<137> A_IWL<136> A_IWL<135> A_IWL<134> A_IWL<133> A_IWL<132> A_IWL<131> A_IWL<130> A_IWL<129> A_IWL<128> A_IWL<255> A_IWL<254> A_IWL<253> A_IWL<252> A_IWL<251> A_IWL<250> A_IWL<249> A_IWL<248> A_IWL<247> A_IWL<246> A_IWL<245> A_IWL<244> A_IWL<243> A_IWL<242> A_IWL<241> A_IWL<240> A_IWL<239> A_IWL<238> A_IWL<237> A_IWL<236> A_IWL<235> A_IWL<234> A_IWL<233> A_IWL<232> A_IWL<231> A_IWL<230> A_IWL<229> A_IWL<228> A_IWL<227> A_IWL<226> A_IWL<225> A_IWL<224> A_IWL<223> A_IWL<222> A_IWL<221> A_IWL<220> A_IWL<219> A_IWL<218> A_IWL<217> A_IWL<216> A_IWL<215> A_IWL<214> A_IWL<213> A_IWL<212> A_IWL<211> A_IWL<210> A_IWL<209> A_IWL<208> A_IWL<207> A_IWL<206> A_IWL<205> A_IWL<204> A_IWL<203> A_IWL<202> A_IWL<201> A_IWL<200> A_IWL<199> A_IWL<198> A_IWL<197> A_IWL<196> A_IWL<195> A_IWL<194> A_IWL<193> A_IWL<192> B_BLC<7> B_BLC<6> B_BLC_TOP<7> B_BLC_TOP<6> B_BLT<7> B_BLT<6> B_BLT_TOP<7> B_BLT_TOP<6> B_IWL<191> B_IWL<190> B_IWL<189> B_IWL<188> B_IWL<187> B_IWL<186> B_IWL<185> B_IWL<184> B_IWL<183> B_IWL<182> B_IWL<181> B_IWL<180> B_IWL<179> B_IWL<178> B_IWL<177> B_IWL<176> B_IWL<175> B_IWL<174> B_IWL<173> B_IWL<172> B_IWL<171> B_IWL<170> B_IWL<169> B_IWL<168> B_IWL<167> B_IWL<166> B_IWL<165> B_IWL<164> B_IWL<163> B_IWL<162> B_IWL<161> B_IWL<160> B_IWL<159> B_IWL<158> B_IWL<157> B_IWL<156> B_IWL<155> B_IWL<154> B_IWL<153> B_IWL<152> B_IWL<151> B_IWL<150> B_IWL<149> B_IWL<148> B_IWL<147> B_IWL<146> B_IWL<145> B_IWL<144> B_IWL<143> B_IWL<142> B_IWL<141> B_IWL<140> B_IWL<139> B_IWL<138> B_IWL<137> B_IWL<136> B_IWL<135> B_IWL<134> B_IWL<133> B_IWL<132> B_IWL<131> B_IWL<130> B_IWL<129> B_IWL<128> B_IWL<255> B_IWL<254> B_IWL<253> B_IWL<252> B_IWL<251> B_IWL<250> B_IWL<249> B_IWL<248> B_IWL<247> B_IWL<246> B_IWL<245> B_IWL<244> B_IWL<243> B_IWL<242> B_IWL<241> B_IWL<240> B_IWL<239> B_IWL<238> B_IWL<237> B_IWL<236> B_IWL<235> B_IWL<234> B_IWL<233> B_IWL<232> B_IWL<231> B_IWL<230> B_IWL<229> B_IWL<228> B_IWL<227> B_IWL<226> B_IWL<225> B_IWL<224> B_IWL<223> B_IWL<222> B_IWL<221> B_IWL<220> B_IWL<219> B_IWL<218> B_IWL<217> B_IWL<216> B_IWL<215> B_IWL<214> B_IWL<213> B_IWL<212> B_IWL<211> B_IWL<210> B_IWL<209> B_IWL<208> B_IWL<207> B_IWL<206> B_IWL<205> B_IWL<204> B_IWL<203> B_IWL<202> B_IWL<201> B_IWL<200> B_IWL<199> B_IWL<198> B_IWL<197> B_IWL<196> B_IWL<195> B_IWL<194> B_IWL<193> B_IWL<192> VDD_CORE VSS / RM_IHPSG13_256x32_c2_2P_COLUMN_pcell_0 +XCOL<2> A_BLC<5> A_BLC<4> A_BLC_TOP<5> A_BLC_TOP<4> A_BLT<5> A_BLT<4> A_BLT_TOP<5> A_BLT_TOP<4> A_IWL<127> A_IWL<126> A_IWL<125> A_IWL<124> A_IWL<123> A_IWL<122> A_IWL<121> A_IWL<120> A_IWL<119> A_IWL<118> A_IWL<117> A_IWL<116> A_IWL<115> A_IWL<114> A_IWL<113> A_IWL<112> A_IWL<111> A_IWL<110> A_IWL<109> A_IWL<108> A_IWL<107> A_IWL<106> A_IWL<105> A_IWL<104> A_IWL<103> A_IWL<102> A_IWL<101> A_IWL<100> A_IWL<99> A_IWL<98> A_IWL<97> A_IWL<96> A_IWL<95> A_IWL<94> A_IWL<93> A_IWL<92> A_IWL<91> A_IWL<90> A_IWL<89> A_IWL<88> A_IWL<87> A_IWL<86> A_IWL<85> A_IWL<84> A_IWL<83> A_IWL<82> A_IWL<81> A_IWL<80> A_IWL<79> A_IWL<78> A_IWL<77> A_IWL<76> A_IWL<75> A_IWL<74> A_IWL<73> A_IWL<72> A_IWL<71> A_IWL<70> A_IWL<69> A_IWL<68> A_IWL<67> A_IWL<66> A_IWL<65> A_IWL<64> A_IWL<191> A_IWL<190> A_IWL<189> A_IWL<188> A_IWL<187> A_IWL<186> A_IWL<185> A_IWL<184> A_IWL<183> A_IWL<182> A_IWL<181> A_IWL<180> A_IWL<179> A_IWL<178> A_IWL<177> A_IWL<176> A_IWL<175> A_IWL<174> A_IWL<173> A_IWL<172> A_IWL<171> A_IWL<170> A_IWL<169> A_IWL<168> A_IWL<167> A_IWL<166> A_IWL<165> A_IWL<164> A_IWL<163> A_IWL<162> A_IWL<161> A_IWL<160> A_IWL<159> A_IWL<158> A_IWL<157> A_IWL<156> A_IWL<155> A_IWL<154> A_IWL<153> A_IWL<152> A_IWL<151> A_IWL<150> A_IWL<149> A_IWL<148> A_IWL<147> A_IWL<146> A_IWL<145> A_IWL<144> A_IWL<143> A_IWL<142> A_IWL<141> A_IWL<140> A_IWL<139> A_IWL<138> A_IWL<137> A_IWL<136> A_IWL<135> A_IWL<134> A_IWL<133> A_IWL<132> A_IWL<131> A_IWL<130> A_IWL<129> A_IWL<128> B_BLC<5> B_BLC<4> B_BLC_TOP<5> B_BLC_TOP<4> B_BLT<5> B_BLT<4> B_BLT_TOP<5> B_BLT_TOP<4> B_IWL<127> B_IWL<126> B_IWL<125> B_IWL<124> B_IWL<123> B_IWL<122> B_IWL<121> B_IWL<120> B_IWL<119> B_IWL<118> B_IWL<117> B_IWL<116> B_IWL<115> B_IWL<114> B_IWL<113> B_IWL<112> B_IWL<111> B_IWL<110> B_IWL<109> B_IWL<108> B_IWL<107> B_IWL<106> B_IWL<105> B_IWL<104> B_IWL<103> B_IWL<102> B_IWL<101> B_IWL<100> B_IWL<99> B_IWL<98> B_IWL<97> B_IWL<96> B_IWL<95> B_IWL<94> B_IWL<93> B_IWL<92> B_IWL<91> B_IWL<90> B_IWL<89> B_IWL<88> B_IWL<87> B_IWL<86> B_IWL<85> B_IWL<84> B_IWL<83> B_IWL<82> B_IWL<81> B_IWL<80> B_IWL<79> B_IWL<78> B_IWL<77> B_IWL<76> B_IWL<75> B_IWL<74> B_IWL<73> B_IWL<72> B_IWL<71> B_IWL<70> B_IWL<69> B_IWL<68> B_IWL<67> B_IWL<66> B_IWL<65> B_IWL<64> B_IWL<191> B_IWL<190> B_IWL<189> B_IWL<188> B_IWL<187> B_IWL<186> B_IWL<185> B_IWL<184> B_IWL<183> B_IWL<182> B_IWL<181> B_IWL<180> B_IWL<179> B_IWL<178> B_IWL<177> B_IWL<176> B_IWL<175> B_IWL<174> B_IWL<173> B_IWL<172> B_IWL<171> B_IWL<170> B_IWL<169> B_IWL<168> B_IWL<167> B_IWL<166> B_IWL<165> B_IWL<164> B_IWL<163> B_IWL<162> B_IWL<161> B_IWL<160> B_IWL<159> B_IWL<158> B_IWL<157> B_IWL<156> B_IWL<155> B_IWL<154> B_IWL<153> B_IWL<152> B_IWL<151> B_IWL<150> B_IWL<149> B_IWL<148> B_IWL<147> B_IWL<146> B_IWL<145> B_IWL<144> B_IWL<143> B_IWL<142> B_IWL<141> B_IWL<140> B_IWL<139> B_IWL<138> B_IWL<137> B_IWL<136> B_IWL<135> B_IWL<134> B_IWL<133> B_IWL<132> B_IWL<131> B_IWL<130> B_IWL<129> B_IWL<128> VDD_CORE VSS / RM_IHPSG13_256x32_c2_2P_COLUMN_pcell_0 +XCOL<1> A_BLC<3> A_BLC<2> A_BLC_TOP<3> A_BLC_TOP<2> A_BLT<3> A_BLT<2> A_BLT_TOP<3> A_BLT_TOP<2> A_IWL<63> A_IWL<62> A_IWL<61> A_IWL<60> A_IWL<59> A_IWL<58> A_IWL<57> A_IWL<56> A_IWL<55> A_IWL<54> A_IWL<53> A_IWL<52> A_IWL<51> A_IWL<50> A_IWL<49> A_IWL<48> A_IWL<47> A_IWL<46> A_IWL<45> A_IWL<44> A_IWL<43> A_IWL<42> A_IWL<41> A_IWL<40> A_IWL<39> A_IWL<38> A_IWL<37> A_IWL<36> A_IWL<35> A_IWL<34> A_IWL<33> A_IWL<32> A_IWL<31> A_IWL<30> A_IWL<29> A_IWL<28> A_IWL<27> A_IWL<26> A_IWL<25> A_IWL<24> A_IWL<23> A_IWL<22> A_IWL<21> A_IWL<20> A_IWL<19> A_IWL<18> A_IWL<17> A_IWL<16> A_IWL<15> A_IWL<14> A_IWL<13> A_IWL<12> A_IWL<11> A_IWL<10> A_IWL<9> A_IWL<8> A_IWL<7> A_IWL<6> A_IWL<5> A_IWL<4> A_IWL<3> A_IWL<2> A_IWL<1> A_IWL<0> A_IWL<127> A_IWL<126> A_IWL<125> A_IWL<124> A_IWL<123> A_IWL<122> A_IWL<121> A_IWL<120> A_IWL<119> A_IWL<118> A_IWL<117> A_IWL<116> A_IWL<115> A_IWL<114> A_IWL<113> A_IWL<112> A_IWL<111> A_IWL<110> A_IWL<109> A_IWL<108> A_IWL<107> A_IWL<106> A_IWL<105> A_IWL<104> A_IWL<103> A_IWL<102> A_IWL<101> A_IWL<100> A_IWL<99> A_IWL<98> A_IWL<97> A_IWL<96> A_IWL<95> A_IWL<94> A_IWL<93> A_IWL<92> A_IWL<91> A_IWL<90> A_IWL<89> A_IWL<88> A_IWL<87> A_IWL<86> A_IWL<85> A_IWL<84> A_IWL<83> A_IWL<82> A_IWL<81> A_IWL<80> A_IWL<79> A_IWL<78> A_IWL<77> A_IWL<76> A_IWL<75> A_IWL<74> A_IWL<73> A_IWL<72> A_IWL<71> A_IWL<70> A_IWL<69> A_IWL<68> A_IWL<67> A_IWL<66> A_IWL<65> A_IWL<64> B_BLC<3> B_BLC<2> B_BLC_TOP<3> B_BLC_TOP<2> B_BLT<3> B_BLT<2> B_BLT_TOP<3> B_BLT_TOP<2> B_IWL<63> B_IWL<62> B_IWL<61> B_IWL<60> B_IWL<59> B_IWL<58> B_IWL<57> B_IWL<56> B_IWL<55> B_IWL<54> B_IWL<53> B_IWL<52> B_IWL<51> B_IWL<50> B_IWL<49> B_IWL<48> B_IWL<47> B_IWL<46> B_IWL<45> B_IWL<44> B_IWL<43> B_IWL<42> B_IWL<41> B_IWL<40> B_IWL<39> B_IWL<38> B_IWL<37> B_IWL<36> B_IWL<35> B_IWL<34> B_IWL<33> B_IWL<32> B_IWL<31> B_IWL<30> B_IWL<29> B_IWL<28> B_IWL<27> B_IWL<26> B_IWL<25> B_IWL<24> B_IWL<23> B_IWL<22> B_IWL<21> B_IWL<20> B_IWL<19> B_IWL<18> B_IWL<17> B_IWL<16> B_IWL<15> B_IWL<14> B_IWL<13> B_IWL<12> B_IWL<11> B_IWL<10> B_IWL<9> B_IWL<8> B_IWL<7> B_IWL<6> B_IWL<5> B_IWL<4> B_IWL<3> B_IWL<2> B_IWL<1> B_IWL<0> B_IWL<127> B_IWL<126> B_IWL<125> B_IWL<124> B_IWL<123> B_IWL<122> B_IWL<121> B_IWL<120> B_IWL<119> B_IWL<118> B_IWL<117> B_IWL<116> B_IWL<115> B_IWL<114> B_IWL<113> B_IWL<112> B_IWL<111> B_IWL<110> B_IWL<109> B_IWL<108> B_IWL<107> B_IWL<106> B_IWL<105> B_IWL<104> B_IWL<103> B_IWL<102> B_IWL<101> B_IWL<100> B_IWL<99> B_IWL<98> B_IWL<97> B_IWL<96> B_IWL<95> B_IWL<94> B_IWL<93> B_IWL<92> B_IWL<91> B_IWL<90> B_IWL<89> B_IWL<88> B_IWL<87> B_IWL<86> B_IWL<85> B_IWL<84> B_IWL<83> B_IWL<82> B_IWL<81> B_IWL<80> B_IWL<79> B_IWL<78> B_IWL<77> B_IWL<76> B_IWL<75> B_IWL<74> B_IWL<73> B_IWL<72> B_IWL<71> B_IWL<70> B_IWL<69> B_IWL<68> B_IWL<67> B_IWL<66> B_IWL<65> B_IWL<64> VDD_CORE VSS / RM_IHPSG13_256x32_c2_2P_COLUMN_pcell_0 +XCOL<0> A_BLC<1> A_BLC<0> A_BLC_TOP<1> A_BLC_TOP<0> A_BLT<1> A_BLT<0> A_BLT_TOP<1> A_BLT_TOP<0> A_WL<63> A_WL<62> A_WL<61> A_WL<60> A_WL<59> A_WL<58> A_WL<57> A_WL<56> A_WL<55> A_WL<54> A_WL<53> A_WL<52> A_WL<51> A_WL<50> A_WL<49> A_WL<48> A_WL<47> A_WL<46> A_WL<45> A_WL<44> A_WL<43> A_WL<42> A_WL<41> A_WL<40> A_WL<39> A_WL<38> A_WL<37> A_WL<36> A_WL<35> A_WL<34> A_WL<33> A_WL<32> A_WL<31> A_WL<30> A_WL<29> A_WL<28> A_WL<27> A_WL<26> A_WL<25> A_WL<24> A_WL<23> A_WL<22> A_WL<21> A_WL<20> A_WL<19> A_WL<18> A_WL<17> A_WL<16> A_WL<15> A_WL<14> A_WL<13> A_WL<12> A_WL<11> A_WL<10> A_WL<9> A_WL<8> A_WL<7> A_WL<6> A_WL<5> A_WL<4> A_WL<3> A_WL<2> A_WL<1> A_WL<0> A_IWL<63> A_IWL<62> A_IWL<61> A_IWL<60> A_IWL<59> A_IWL<58> A_IWL<57> A_IWL<56> A_IWL<55> A_IWL<54> A_IWL<53> A_IWL<52> A_IWL<51> A_IWL<50> A_IWL<49> A_IWL<48> A_IWL<47> A_IWL<46> A_IWL<45> A_IWL<44> A_IWL<43> A_IWL<42> A_IWL<41> A_IWL<40> A_IWL<39> A_IWL<38> A_IWL<37> A_IWL<36> A_IWL<35> A_IWL<34> A_IWL<33> A_IWL<32> A_IWL<31> A_IWL<30> A_IWL<29> A_IWL<28> A_IWL<27> A_IWL<26> A_IWL<25> A_IWL<24> A_IWL<23> A_IWL<22> A_IWL<21> A_IWL<20> A_IWL<19> A_IWL<18> A_IWL<17> A_IWL<16> A_IWL<15> A_IWL<14> A_IWL<13> A_IWL<12> A_IWL<11> A_IWL<10> A_IWL<9> A_IWL<8> A_IWL<7> A_IWL<6> A_IWL<5> A_IWL<4> A_IWL<3> A_IWL<2> A_IWL<1> A_IWL<0> B_BLC<1> B_BLC<0> B_BLC_TOP<1> B_BLC_TOP<0> B_BLT<1> B_BLT<0> B_BLT_TOP<1> B_BLT_TOP<0> B_WL<63> B_WL<62> B_WL<61> B_WL<60> B_WL<59> B_WL<58> B_WL<57> B_WL<56> B_WL<55> B_WL<54> B_WL<53> B_WL<52> B_WL<51> B_WL<50> B_WL<49> B_WL<48> B_WL<47> B_WL<46> B_WL<45> B_WL<44> B_WL<43> B_WL<42> B_WL<41> B_WL<40> B_WL<39> B_WL<38> B_WL<37> B_WL<36> B_WL<35> B_WL<34> B_WL<33> B_WL<32> B_WL<31> B_WL<30> B_WL<29> B_WL<28> B_WL<27> B_WL<26> B_WL<25> B_WL<24> B_WL<23> B_WL<22> B_WL<21> B_WL<20> B_WL<19> B_WL<18> B_WL<17> B_WL<16> B_WL<15> B_WL<14> B_WL<13> B_WL<12> B_WL<11> B_WL<10> B_WL<9> B_WL<8> B_WL<7> B_WL<6> B_WL<5> B_WL<4> B_WL<3> B_WL<2> B_WL<1> B_WL<0> B_IWL<63> B_IWL<62> B_IWL<61> B_IWL<60> B_IWL<59> B_IWL<58> B_IWL<57> B_IWL<56> B_IWL<55> B_IWL<54> B_IWL<53> B_IWL<52> B_IWL<51> B_IWL<50> B_IWL<49> B_IWL<48> B_IWL<47> B_IWL<46> B_IWL<45> B_IWL<44> B_IWL<43> B_IWL<42> B_IWL<41> B_IWL<40> B_IWL<39> B_IWL<38> B_IWL<37> B_IWL<36> B_IWL<35> B_IWL<34> B_IWL<33> B_IWL<32> B_IWL<31> B_IWL<30> B_IWL<29> B_IWL<28> B_IWL<27> B_IWL<26> B_IWL<25> B_IWL<24> B_IWL<23> B_IWL<22> B_IWL<21> B_IWL<20> B_IWL<19> B_IWL<18> B_IWL<17> B_IWL<16> B_IWL<15> B_IWL<14> B_IWL<13> B_IWL<12> B_IWL<11> B_IWL<10> B_IWL<9> B_IWL<8> B_IWL<7> B_IWL<6> B_IWL<5> B_IWL<4> B_IWL<3> B_IWL<2> B_IWL<1> B_IWL<0> VDD_CORE VSS / RM_IHPSG13_256x32_c2_2P_COLUMN_pcell_0 +.ENDS + + + + +.SUBCKT RM_IHPSG13_256x32_c2_2P_DLY_pcell_2 A Z VDD VSS + XIDL D<9> Z VDD VSS / RSC_IHPSG13_CDLYX1 + XIDM<9> D<8> D<9> VDD VSS / RSC_IHPSG13_CDLYX1_DUMMY + XIDM<8> D<7> D<8> VDD VSS / RSC_IHPSG13_CDLYX1_DUMMY + XIDM<7> D<6> D<7> VDD VSS / RSC_IHPSG13_CDLYX1_DUMMY + XIDM<6> D<5> D<6> VDD VSS / RSC_IHPSG13_CDLYX1_DUMMY + XIDM<5> D<4> D<5> VDD VSS / RSC_IHPSG13_CDLYX1_DUMMY + XIDM<4> D<3> D<4> VDD VSS / RSC_IHPSG13_CDLYX1_DUMMY + XIDM<3> D<2> D<3> VDD VSS / RSC_IHPSG13_CDLYX1_DUMMY + XIDM<2> D<1> D<2> VDD VSS / RSC_IHPSG13_CDLYX1_DUMMY + XIDM<1> A D<1> VDD VSS / RSC_IHPSG13_CDLYX1_DUMMY +.ENDS + + +.SUBCKT RM_IHPSG13_256x32_c2_2P_DLY_pcell_3 A Z VDD VSS + XIDM<10> D<9> Z VDD VSS / RSC_IHPSG13_CDLYX1_DUMMY + XIDM<9> D<8> D<9> VDD VSS / RSC_IHPSG13_CDLYX1_DUMMY + XIDM<8> D<7> D<8> VDD VSS / RSC_IHPSG13_CDLYX1_DUMMY + XIDM<7> D<6> D<7> VDD VSS / RSC_IHPSG13_CDLYX1_DUMMY + XIDM<6> D<5> D<6> VDD VSS / RSC_IHPSG13_CDLYX1_DUMMY + XIDM<5> D<4> D<5> VDD VSS / RSC_IHPSG13_CDLYX1_DUMMY + XIDM<4> D<3> D<4> VDD VSS / RSC_IHPSG13_CDLYX1_DUMMY + XIDM<3> D<2> D<3> VDD VSS / RSC_IHPSG13_CDLYX1_DUMMY + XIDM<2> D<1> D<2> VDD VSS / RSC_IHPSG13_CDLYX1_DUMMY + XIDM<1> A D<1> VDD VSS / RSC_IHPSG13_CDLYX1_DUMMY +.ENDS + + + +.SUBCKT RM_IHPSG13_2P_256x32_c2_bm_bist A_ADDR<7> A_ADDR<6> A_ADDR<5> A_ADDR<4> A_ADDR<3> A_ADDR<2> A_ADDR<1> A_ADDR<0> A_BIST_ADDR<7> A_BIST_ADDR<6> A_BIST_ADDR<5> A_BIST_ADDR<4> A_BIST_ADDR<3> A_BIST_ADDR<2> A_BIST_ADDR<1> A_BIST_ADDR<0> A_BIST_BM<31> A_BIST_BM<30> A_BIST_BM<29> A_BIST_BM<28> A_BIST_BM<27> A_BIST_BM<26> A_BIST_BM<25> A_BIST_BM<24> A_BIST_BM<23> A_BIST_BM<22> A_BIST_BM<21> A_BIST_BM<20> A_BIST_BM<19> A_BIST_BM<18> A_BIST_BM<17> A_BIST_BM<16> A_BIST_BM<15> A_BIST_BM<14> A_BIST_BM<13> A_BIST_BM<12> A_BIST_BM<11> A_BIST_BM<10> A_BIST_BM<9> A_BIST_BM<8> A_BIST_BM<7> A_BIST_BM<6> A_BIST_BM<5> A_BIST_BM<4> A_BIST_BM<3> A_BIST_BM<2> A_BIST_BM<1> A_BIST_BM<0> A_BIST_CLK A_BIST_DIN<31> A_BIST_DIN<30> A_BIST_DIN<29> A_BIST_DIN<28> A_BIST_DIN<27> A_BIST_DIN<26> A_BIST_DIN<25> A_BIST_DIN<24> A_BIST_DIN<23> A_BIST_DIN<22> A_BIST_DIN<21> A_BIST_DIN<20> A_BIST_DIN<19> A_BIST_DIN<18> A_BIST_DIN<17> A_BIST_DIN<16> A_BIST_DIN<15> A_BIST_DIN<14> A_BIST_DIN<13> A_BIST_DIN<12> A_BIST_DIN<11> A_BIST_DIN<10> A_BIST_DIN<9> A_BIST_DIN<8> A_BIST_DIN<7> A_BIST_DIN<6> A_BIST_DIN<5> A_BIST_DIN<4> A_BIST_DIN<3> A_BIST_DIN<2> A_BIST_DIN<1> A_BIST_DIN<0> A_BIST_EN A_BIST_MEN A_BIST_REN A_BIST_WEN A_BM<31> A_BM<30> A_BM<29> A_BM<28> A_BM<27> A_BM<26> A_BM<25> A_BM<24> A_BM<23> A_BM<22> A_BM<21> A_BM<20> A_BM<19> A_BM<18> A_BM<17> A_BM<16> A_BM<15> A_BM<14> A_BM<13> A_BM<12> A_BM<11> A_BM<10> A_BM<9> A_BM<8> A_BM<7> A_BM<6> A_BM<5> A_BM<4> A_BM<3> A_BM<2> A_BM<1> A_BM<0> A_CLK A_DIN<31> A_DIN<30> A_DIN<29> A_DIN<28> A_DIN<27> A_DIN<26> A_DIN<25> A_DIN<24> A_DIN<23> A_DIN<22> A_DIN<21> A_DIN<20> A_DIN<19> A_DIN<18> A_DIN<17> A_DIN<16> A_DIN<15> A_DIN<14> A_DIN<13> A_DIN<12> A_DIN<11> A_DIN<10> A_DIN<9> A_DIN<8> A_DIN<7> A_DIN<6> A_DIN<5> A_DIN<4> A_DIN<3> A_DIN<2> A_DIN<1> A_DIN<0> A_DLY A_DOUT<31> A_DOUT<30> A_DOUT<29> A_DOUT<28> A_DOUT<27> A_DOUT<26> A_DOUT<25> A_DOUT<24> A_DOUT<23> A_DOUT<22> A_DOUT<21> A_DOUT<20> A_DOUT<19> A_DOUT<18> A_DOUT<17> A_DOUT<16> A_DOUT<15> A_DOUT<14> A_DOUT<13> A_DOUT<12> A_DOUT<11> A_DOUT<10> A_DOUT<9> A_DOUT<8> A_DOUT<7> A_DOUT<6> A_DOUT<5> A_DOUT<4> A_DOUT<3> A_DOUT<2> A_DOUT<1> A_DOUT<0> A_MEN A_REN A_WEN B_ADDR<7> B_ADDR<6> B_ADDR<5> B_ADDR<4> B_ADDR<3> B_ADDR<2> B_ADDR<1> B_ADDR<0> B_BIST_ADDR<7> B_BIST_ADDR<6> B_BIST_ADDR<5> B_BIST_ADDR<4> B_BIST_ADDR<3> B_BIST_ADDR<2> B_BIST_ADDR<1> B_BIST_ADDR<0> B_BIST_BM<31> B_BIST_BM<30> B_BIST_BM<29> B_BIST_BM<28> B_BIST_BM<27> B_BIST_BM<26> B_BIST_BM<25> B_BIST_BM<24> B_BIST_BM<23> B_BIST_BM<22> B_BIST_BM<21> B_BIST_BM<20> B_BIST_BM<19> B_BIST_BM<18> B_BIST_BM<17> B_BIST_BM<16> B_BIST_BM<15> B_BIST_BM<14> B_BIST_BM<13> B_BIST_BM<12> B_BIST_BM<11> B_BIST_BM<10> B_BIST_BM<9> B_BIST_BM<8> B_BIST_BM<7> B_BIST_BM<6> B_BIST_BM<5> B_BIST_BM<4> B_BIST_BM<3> B_BIST_BM<2> B_BIST_BM<1> B_BIST_BM<0> B_BIST_CLK B_BIST_DIN<31> B_BIST_DIN<30> B_BIST_DIN<29> B_BIST_DIN<28> B_BIST_DIN<27> B_BIST_DIN<26> B_BIST_DIN<25> B_BIST_DIN<24> B_BIST_DIN<23> B_BIST_DIN<22> B_BIST_DIN<21> B_BIST_DIN<20> B_BIST_DIN<19> B_BIST_DIN<18> B_BIST_DIN<17> B_BIST_DIN<16> B_BIST_DIN<15> B_BIST_DIN<14> B_BIST_DIN<13> B_BIST_DIN<12> B_BIST_DIN<11> B_BIST_DIN<10> B_BIST_DIN<9> B_BIST_DIN<8> B_BIST_DIN<7> B_BIST_DIN<6> B_BIST_DIN<5> B_BIST_DIN<4> B_BIST_DIN<3> B_BIST_DIN<2> B_BIST_DIN<1> B_BIST_DIN<0> B_BIST_EN B_BIST_MEN B_BIST_REN B_BIST_WEN B_BM<31> B_BM<30> B_BM<29> B_BM<28> B_BM<27> B_BM<26> B_BM<25> B_BM<24> B_BM<23> B_BM<22> B_BM<21> B_BM<20> B_BM<19> B_BM<18> B_BM<17> B_BM<16> B_BM<15> B_BM<14> B_BM<13> B_BM<12> B_BM<11> B_BM<10> B_BM<9> B_BM<8> B_BM<7> B_BM<6> B_BM<5> B_BM<4> B_BM<3> B_BM<2> B_BM<1> B_BM<0> B_CLK B_DIN<31> B_DIN<30> B_DIN<29> B_DIN<28> B_DIN<27> B_DIN<26> B_DIN<25> B_DIN<24> B_DIN<23> B_DIN<22> B_DIN<21> B_DIN<20> B_DIN<19> B_DIN<18> B_DIN<17> B_DIN<16> B_DIN<15> B_DIN<14> B_DIN<13> B_DIN<12> B_DIN<11> B_DIN<10> B_DIN<9> B_DIN<8> B_DIN<7> B_DIN<6> B_DIN<5> B_DIN<4> B_DIN<3> B_DIN<2> B_DIN<1> B_DIN<0> B_DLY B_DOUT<31> B_DOUT<30> B_DOUT<29> B_DOUT<28> B_DOUT<27> B_DOUT<26> B_DOUT<25> B_DOUT<24> B_DOUT<23> B_DOUT<22> B_DOUT<21> B_DOUT<20> B_DOUT<19> B_DOUT<18> B_DOUT<17> B_DOUT<16> B_DOUT<15> B_DOUT<14> B_DOUT<13> B_DOUT<12> B_DOUT<11> B_DOUT<10> B_DOUT<9> B_DOUT<8> B_DOUT<7> B_DOUT<6> B_DOUT<5> B_DOUT<4> B_DOUT<3> B_DOUT<2> B_DOUT<1> B_DOUT<0> B_MEN B_REN B_WEN VDD! VDDARRAY! VSS! + + +XRAM<1> a_blc_r<63> a_blc_r<62> a_blc_r<61> a_blc_r<60> a_blc_r<59> a_blc_r<58> a_blc_r<57> a_blc_r<56> a_blc_r<55> a_blc_r<54> a_blc_r<53> a_blc_r<52> a_blc_r<51> a_blc_r<50> a_blc_r<49> a_blc_r<48> a_blc_r<47> a_blc_r<46> a_blc_r<45> a_blc_r<44> a_blc_r<43> a_blc_r<42> a_blc_r<41> a_blc_r<40> a_blc_r<39> a_blc_r<38> a_blc_r<37> a_blc_r<36> a_blc_r<35> a_blc_r<34> a_blc_r<33> a_blc_r<32> a_blc_r<31> a_blc_r<30> a_blc_r<29> a_blc_r<28> a_blc_r<27> a_blc_r<26> a_blc_r<25> a_blc_r<24> a_blc_r<23> a_blc_r<22> a_blc_r<21> a_blc_r<20> a_blc_r<19> a_blc_r<18> a_blc_r<17> a_blc_r<16> a_blc_r<15> a_blc_r<14> a_blc_r<13> a_blc_r<12> a_blc_r<11> a_blc_r<10> a_blc_r<9> a_blc_r<8> a_blc_r<7> a_blc_r<6> a_blc_r<5> a_blc_r<4> a_blc_r<3> a_blc_r<2> a_blc_r<1> a_blc_r<0> a_blt_r<63> a_blt_r<62> a_blt_r<61> a_blt_r<60> a_blt_r<59> a_blt_r<58> a_blt_r<57> a_blt_r<56> a_blt_r<55> a_blt_r<54> a_blt_r<53> a_blt_r<52> a_blt_r<51> a_blt_r<50> a_blt_r<49> a_blt_r<48> a_blt_r<47> a_blt_r<46> a_blt_r<45> a_blt_r<44> a_blt_r<43> a_blt_r<42> a_blt_r<41> a_blt_r<40> a_blt_r<39> a_blt_r<38> a_blt_r<37> a_blt_r<36> a_blt_r<35> a_blt_r<34> a_blt_r<33> a_blt_r<32> a_blt_r<31> a_blt_r<30> a_blt_r<29> a_blt_r<28> a_blt_r<27> a_blt_r<26> a_blt_r<25> a_blt_r<24> a_blt_r<23> a_blt_r<22> a_blt_r<21> a_blt_r<20> a_blt_r<19> a_blt_r<18> a_blt_r<17> a_blt_r<16> a_blt_r<15> a_blt_r<14> a_blt_r<13> a_blt_r<12> a_blt_r<11> a_blt_r<10> a_blt_r<9> a_blt_r<8> a_blt_r<7> a_blt_r<6> a_blt_r<5> a_blt_r<4> a_blt_r<3> a_blt_r<2> a_blt_r<1> a_blt_r<0> a_wl_r<63> a_wl_r<62> a_wl_r<61> a_wl_r<60> a_wl_r<59> a_wl_r<58> a_wl_r<57> a_wl_r<56> a_wl_r<55> a_wl_r<54> a_wl_r<53> a_wl_r<52> a_wl_r<51> a_wl_r<50> a_wl_r<49> a_wl_r<48> a_wl_r<47> a_wl_r<46> a_wl_r<45> a_wl_r<44> a_wl_r<43> a_wl_r<42> a_wl_r<41> a_wl_r<40> a_wl_r<39> a_wl_r<38> a_wl_r<37> a_wl_r<36> a_wl_r<35> a_wl_r<34> a_wl_r<33> a_wl_r<32> a_wl_r<31> a_wl_r<30> a_wl_r<29> a_wl_r<28> a_wl_r<27> a_wl_r<26> a_wl_r<25> a_wl_r<24> a_wl_r<23> a_wl_r<22> a_wl_r<21> a_wl_r<20> a_wl_r<19> a_wl_r<18> a_wl_r<17> a_wl_r<16> a_wl_r<15> a_wl_r<14> a_wl_r<13> a_wl_r<12> a_wl_r<11> a_wl_r<10> a_wl_r<9> a_wl_r<8> a_wl_r<7> a_wl_r<6> a_wl_r<5> a_wl_r<4> a_wl_r<3> a_wl_r<2> a_wl_r<1> a_wl_r<0> b_blc_r<63> b_blc_r<62> b_blc_r<61> b_blc_r<60> b_blc_r<59> b_blc_r<58> b_blc_r<57> b_blc_r<56> b_blc_r<55> b_blc_r<54> b_blc_r<53> b_blc_r<52> b_blc_r<51> b_blc_r<50> b_blc_r<49> b_blc_r<48> b_blc_r<47> b_blc_r<46> b_blc_r<45> b_blc_r<44> b_blc_r<43> b_blc_r<42> b_blc_r<41> b_blc_r<40> b_blc_r<39> b_blc_r<38> b_blc_r<37> b_blc_r<36> b_blc_r<35> b_blc_r<34> b_blc_r<33> b_blc_r<32> b_blc_r<31> b_blc_r<30> b_blc_r<29> b_blc_r<28> b_blc_r<27> b_blc_r<26> b_blc_r<25> b_blc_r<24> b_blc_r<23> b_blc_r<22> b_blc_r<21> b_blc_r<20> b_blc_r<19> b_blc_r<18> b_blc_r<17> b_blc_r<16> b_blc_r<15> b_blc_r<14> b_blc_r<13> b_blc_r<12> b_blc_r<11> b_blc_r<10> b_blc_r<9> b_blc_r<8> b_blc_r<7> b_blc_r<6> b_blc_r<5> b_blc_r<4> b_blc_r<3> b_blc_r<2> b_blc_r<1> b_blc_r<0> b_blt_r<63> b_blt_r<62> b_blt_r<61> b_blt_r<60> b_blt_r<59> b_blt_r<58> b_blt_r<57> b_blt_r<56> b_blt_r<55> b_blt_r<54> b_blt_r<53> b_blt_r<52> b_blt_r<51> b_blt_r<50> b_blt_r<49> b_blt_r<48> b_blt_r<47> b_blt_r<46> b_blt_r<45> b_blt_r<44> b_blt_r<43> b_blt_r<42> b_blt_r<41> b_blt_r<40> b_blt_r<39> b_blt_r<38> b_blt_r<37> b_blt_r<36> b_blt_r<35> b_blt_r<34> b_blt_r<33> b_blt_r<32> b_blt_r<31> b_blt_r<30> b_blt_r<29> b_blt_r<28> b_blt_r<27> b_blt_r<26> b_blt_r<25> b_blt_r<24> b_blt_r<23> b_blt_r<22> b_blt_r<21> b_blt_r<20> b_blt_r<19> b_blt_r<18> b_blt_r<17> b_blt_r<16> b_blt_r<15> b_blt_r<14> b_blt_r<13> b_blt_r<12> b_blt_r<11> b_blt_r<10> b_blt_r<9> b_blt_r<8> b_blt_r<7> b_blt_r<6> b_blt_r<5> b_blt_r<4> b_blt_r<3> b_blt_r<2> b_blt_r<1> b_blt_r<0> b_wl_r<63> b_wl_r<62> b_wl_r<61> b_wl_r<60> b_wl_r<59> b_wl_r<58> b_wl_r<57> b_wl_r<56> b_wl_r<55> b_wl_r<54> b_wl_r<53> b_wl_r<52> b_wl_r<51> b_wl_r<50> b_wl_r<49> b_wl_r<48> b_wl_r<47> b_wl_r<46> b_wl_r<45> b_wl_r<44> b_wl_r<43> b_wl_r<42> b_wl_r<41> b_wl_r<40> b_wl_r<39> b_wl_r<38> b_wl_r<37> b_wl_r<36> b_wl_r<35> b_wl_r<34> b_wl_r<33> b_wl_r<32> b_wl_r<31> b_wl_r<30> b_wl_r<29> b_wl_r<28> b_wl_r<27> b_wl_r<26> b_wl_r<25> b_wl_r<24> b_wl_r<23> b_wl_r<22> b_wl_r<21> b_wl_r<20> b_wl_r<19> b_wl_r<18> b_wl_r<17> b_wl_r<16> b_wl_r<15> b_wl_r<14> b_wl_r<13> b_wl_r<12> b_wl_r<11> b_wl_r<10> b_wl_r<9> b_wl_r<8> b_wl_r<7> b_wl_r<6> b_wl_r<5> b_wl_r<4> b_wl_r<3> b_wl_r<2> b_wl_r<1> b_wl_r<0> VDDARRAY! VSS! / RM_IHPSG13_256x32_c2_2P_MATRIX_pcell_1 +XRAM<0> a_blc_l<63> a_blc_l<62> a_blc_l<61> a_blc_l<60> a_blc_l<59> a_blc_l<58> a_blc_l<57> a_blc_l<56> a_blc_l<55> a_blc_l<54> a_blc_l<53> a_blc_l<52> a_blc_l<51> a_blc_l<50> a_blc_l<49> a_blc_l<48> a_blc_l<47> a_blc_l<46> a_blc_l<45> a_blc_l<44> a_blc_l<43> a_blc_l<42> a_blc_l<41> a_blc_l<40> a_blc_l<39> a_blc_l<38> a_blc_l<37> a_blc_l<36> a_blc_l<35> a_blc_l<34> a_blc_l<33> a_blc_l<32> a_blc_l<31> a_blc_l<30> a_blc_l<29> a_blc_l<28> a_blc_l<27> a_blc_l<26> a_blc_l<25> a_blc_l<24> a_blc_l<23> a_blc_l<22> a_blc_l<21> a_blc_l<20> a_blc_l<19> a_blc_l<18> a_blc_l<17> a_blc_l<16> a_blc_l<15> a_blc_l<14> a_blc_l<13> a_blc_l<12> a_blc_l<11> a_blc_l<10> a_blc_l<9> a_blc_l<8> a_blc_l<7> a_blc_l<6> a_blc_l<5> a_blc_l<4> a_blc_l<3> a_blc_l<2> a_blc_l<1> a_blc_l<0> a_blt_l<63> a_blt_l<62> a_blt_l<61> a_blt_l<60> a_blt_l<59> a_blt_l<58> a_blt_l<57> a_blt_l<56> a_blt_l<55> a_blt_l<54> a_blt_l<53> a_blt_l<52> a_blt_l<51> a_blt_l<50> a_blt_l<49> a_blt_l<48> a_blt_l<47> a_blt_l<46> a_blt_l<45> a_blt_l<44> a_blt_l<43> a_blt_l<42> a_blt_l<41> a_blt_l<40> a_blt_l<39> a_blt_l<38> a_blt_l<37> a_blt_l<36> a_blt_l<35> a_blt_l<34> a_blt_l<33> a_blt_l<32> a_blt_l<31> a_blt_l<30> a_blt_l<29> a_blt_l<28> a_blt_l<27> a_blt_l<26> a_blt_l<25> a_blt_l<24> a_blt_l<23> a_blt_l<22> a_blt_l<21> a_blt_l<20> a_blt_l<19> a_blt_l<18> a_blt_l<17> a_blt_l<16> a_blt_l<15> a_blt_l<14> a_blt_l<13> a_blt_l<12> a_blt_l<11> a_blt_l<10> a_blt_l<9> a_blt_l<8> a_blt_l<7> a_blt_l<6> a_blt_l<5> a_blt_l<4> a_blt_l<3> a_blt_l<2> a_blt_l<1> a_blt_l<0> a_wl_l<63> a_wl_l<62> a_wl_l<61> a_wl_l<60> a_wl_l<59> a_wl_l<58> a_wl_l<57> a_wl_l<56> a_wl_l<55> a_wl_l<54> a_wl_l<53> a_wl_l<52> a_wl_l<51> a_wl_l<50> a_wl_l<49> a_wl_l<48> a_wl_l<47> a_wl_l<46> a_wl_l<45> a_wl_l<44> a_wl_l<43> a_wl_l<42> a_wl_l<41> a_wl_l<40> a_wl_l<39> a_wl_l<38> a_wl_l<37> a_wl_l<36> a_wl_l<35> a_wl_l<34> a_wl_l<33> a_wl_l<32> a_wl_l<31> a_wl_l<30> a_wl_l<29> a_wl_l<28> a_wl_l<27> a_wl_l<26> a_wl_l<25> a_wl_l<24> a_wl_l<23> a_wl_l<22> a_wl_l<21> a_wl_l<20> a_wl_l<19> a_wl_l<18> a_wl_l<17> a_wl_l<16> a_wl_l<15> a_wl_l<14> a_wl_l<13> a_wl_l<12> a_wl_l<11> a_wl_l<10> a_wl_l<9> a_wl_l<8> a_wl_l<7> a_wl_l<6> a_wl_l<5> a_wl_l<4> a_wl_l<3> a_wl_l<2> a_wl_l<1> a_wl_l<0> b_blc_l<63> b_blc_l<62> b_blc_l<61> b_blc_l<60> b_blc_l<59> b_blc_l<58> b_blc_l<57> b_blc_l<56> b_blc_l<55> b_blc_l<54> b_blc_l<53> b_blc_l<52> b_blc_l<51> b_blc_l<50> b_blc_l<49> b_blc_l<48> b_blc_l<47> b_blc_l<46> b_blc_l<45> b_blc_l<44> b_blc_l<43> b_blc_l<42> b_blc_l<41> b_blc_l<40> b_blc_l<39> b_blc_l<38> b_blc_l<37> b_blc_l<36> b_blc_l<35> b_blc_l<34> b_blc_l<33> b_blc_l<32> b_blc_l<31> b_blc_l<30> b_blc_l<29> b_blc_l<28> b_blc_l<27> b_blc_l<26> b_blc_l<25> b_blc_l<24> b_blc_l<23> b_blc_l<22> b_blc_l<21> b_blc_l<20> b_blc_l<19> b_blc_l<18> b_blc_l<17> b_blc_l<16> b_blc_l<15> b_blc_l<14> b_blc_l<13> b_blc_l<12> b_blc_l<11> b_blc_l<10> b_blc_l<9> b_blc_l<8> b_blc_l<7> b_blc_l<6> b_blc_l<5> b_blc_l<4> b_blc_l<3> b_blc_l<2> b_blc_l<1> b_blc_l<0> b_blt_l<63> b_blt_l<62> b_blt_l<61> b_blt_l<60> b_blt_l<59> b_blt_l<58> b_blt_l<57> b_blt_l<56> b_blt_l<55> b_blt_l<54> b_blt_l<53> b_blt_l<52> b_blt_l<51> b_blt_l<50> b_blt_l<49> b_blt_l<48> b_blt_l<47> b_blt_l<46> b_blt_l<45> b_blt_l<44> b_blt_l<43> b_blt_l<42> b_blt_l<41> b_blt_l<40> b_blt_l<39> b_blt_l<38> b_blt_l<37> b_blt_l<36> b_blt_l<35> b_blt_l<34> b_blt_l<33> b_blt_l<32> b_blt_l<31> b_blt_l<30> b_blt_l<29> b_blt_l<28> b_blt_l<27> b_blt_l<26> b_blt_l<25> b_blt_l<24> b_blt_l<23> b_blt_l<22> b_blt_l<21> b_blt_l<20> b_blt_l<19> b_blt_l<18> b_blt_l<17> b_blt_l<16> b_blt_l<15> b_blt_l<14> b_blt_l<13> b_blt_l<12> b_blt_l<11> b_blt_l<10> b_blt_l<9> b_blt_l<8> b_blt_l<7> b_blt_l<6> b_blt_l<5> b_blt_l<4> b_blt_l<3> b_blt_l<2> b_blt_l<1> b_blt_l<0> b_wl_l<63> b_wl_l<62> b_wl_l<61> b_wl_l<60> b_wl_l<59> b_wl_l<58> b_wl_l<57> b_wl_l<56> b_wl_l<55> b_wl_l<54> b_wl_l<53> b_wl_l<52> b_wl_l<51> b_wl_l<50> b_wl_l<49> b_wl_l<48> b_wl_l<47> b_wl_l<46> b_wl_l<45> b_wl_l<44> b_wl_l<43> b_wl_l<42> b_wl_l<41> b_wl_l<40> b_wl_l<39> b_wl_l<38> b_wl_l<37> b_wl_l<36> b_wl_l<35> b_wl_l<34> b_wl_l<33> b_wl_l<32> b_wl_l<31> b_wl_l<30> b_wl_l<29> b_wl_l<28> b_wl_l<27> b_wl_l<26> b_wl_l<25> b_wl_l<24> b_wl_l<23> b_wl_l<22> b_wl_l<21> b_wl_l<20> b_wl_l<19> b_wl_l<18> b_wl_l<17> b_wl_l<16> b_wl_l<15> b_wl_l<14> b_wl_l<13> b_wl_l<12> b_wl_l<11> b_wl_l<10> b_wl_l<9> b_wl_l<8> b_wl_l<7> b_wl_l<6> b_wl_l<5> b_wl_l<4> b_wl_l<3> b_wl_l<2> b_wl_l<1> b_wl_l<0> VDDARRAY! VSS! / RM_IHPSG13_256x32_c2_2P_MATRIX_pcell_1 + + +XB_COLDRV<1> b_addr_col<1> b_addr_col<0> b_addr_col_r<1> b_addr_col_r<0> b_addr_dec<7> b_addr_dec<6> b_addr_dec<5> b_addr_dec<4> b_addr_dec<3> b_addr_dec<2> b_addr_dec<1> b_addr_dec<0> b_addr_dec_r<7> b_addr_dec_r<6> b_addr_dec_r<5> b_addr_dec_r<4> b_addr_dec_r<3> b_addr_dec_r<2> b_addr_dec_r<1> b_addr_dec_r<0> b_dclk b_dclk_p_r<0> b_rclk b_rclk_p_r<0> b_wclk b_wclk_p_r<0> VDD! VSS! / RM_IHPSG13_256x32_c2_2P_COLDRV13X8 +XB_COLDRV<0> b_addr_col<1> b_addr_col<0> b_addr_col_l<1> b_addr_col_l<0> b_addr_dec<7> b_addr_dec<6> b_addr_dec<5> b_addr_dec<4> b_addr_dec<3> b_addr_dec<2> b_addr_dec<1> b_addr_dec<0> b_addr_dec_l<7> b_addr_dec_l<6> b_addr_dec_l<5> b_addr_dec_l<4> b_addr_dec_l<3> b_addr_dec_l<2> b_addr_dec_l<1> b_addr_dec_l<0> b_dclk b_dclk_p_l<0> b_rclk b_rclk_p_l<0> b_wclk b_wclk_p_l<0> VDD! VSS! / RM_IHPSG13_256x32_c2_2P_COLDRV13X8 +XA_COLDRV<1> a_addr_col<1> a_addr_col<0> a_addr_col_r<1> a_addr_col_r<0> a_addr_dec<7> a_addr_dec<6> a_addr_dec<5> a_addr_dec<4> a_addr_dec<3> a_addr_dec<2> a_addr_dec<1> a_addr_dec<0> a_addr_dec_r<7> a_addr_dec_r<6> a_addr_dec_r<5> a_addr_dec_r<4> a_addr_dec_r<3> a_addr_dec_r<2> a_addr_dec_r<1> a_addr_dec_r<0> a_dclk a_dclk_p_r<0> a_rclk a_rclk_p_r<0> a_wclk a_wclk_p_r<0> VDD! VSS! / RM_IHPSG13_256x32_c2_2P_COLDRV13X8 +XA_COLDRV<0> a_addr_col<1> a_addr_col<0> a_addr_col_l<1> a_addr_col_l<0> a_addr_dec<7> a_addr_dec<6> a_addr_dec<5> a_addr_dec<4> a_addr_dec<3> a_addr_dec<2> a_addr_dec<1> a_addr_dec<0> a_addr_dec_l<7> a_addr_dec_l<6> a_addr_dec_l<5> a_addr_dec_l<4> a_addr_dec_l<3> a_addr_dec_l<2> a_addr_dec_l<1> a_addr_dec_l<0> a_dclk a_dclk_p_l<0> a_rclk a_rclk_p_l<0> a_wclk a_wclk_p_l<0> VDD! VSS! / RM_IHPSG13_256x32_c2_2P_COLDRV13X8 + + +XB_WLDRV<7> b_wi<63> b_wi<62> b_wi<61> b_wi<60> b_wi<59> b_wi<58> b_wi<57> b_wi<56> b_wi<55> b_wi<54> b_wi<53> b_wi<52> b_wi<51> b_wi<50> b_wi<49> b_wi<48> b_wl_r<63> b_wl_r<62> b_wl_r<61> b_wl_r<60> b_wl_r<59> b_wl_r<58> b_wl_r<57> b_wl_r<56> b_wl_r<55> b_wl_r<54> b_wl_r<53> b_wl_r<52> b_wl_r<51> b_wl_r<50> b_wl_r<49> b_wl_r<48> VDD! VSS! / RM_IHPSG13_256x32_c2_2P_WLDRV16X8 +XB_WLDRV<6> b_wi<47> b_wi<46> b_wi<45> b_wi<44> b_wi<43> b_wi<42> b_wi<41> b_wi<40> b_wi<39> b_wi<38> b_wi<37> b_wi<36> b_wi<35> b_wi<34> b_wi<33> b_wi<32> b_wl_r<47> b_wl_r<46> b_wl_r<45> b_wl_r<44> b_wl_r<43> b_wl_r<42> b_wl_r<41> b_wl_r<40> b_wl_r<39> b_wl_r<38> b_wl_r<37> b_wl_r<36> b_wl_r<35> b_wl_r<34> b_wl_r<33> b_wl_r<32> VDD! VSS! / RM_IHPSG13_256x32_c2_2P_WLDRV16X8 +XB_WLDRV<5> b_wi<31> b_wi<30> b_wi<29> b_wi<28> b_wi<27> b_wi<26> b_wi<25> b_wi<24> b_wi<23> b_wi<22> b_wi<21> b_wi<20> b_wi<19> b_wi<18> b_wi<17> b_wi<16> b_wl_r<31> b_wl_r<30> b_wl_r<29> b_wl_r<28> b_wl_r<27> b_wl_r<26> b_wl_r<25> b_wl_r<24> b_wl_r<23> b_wl_r<22> b_wl_r<21> b_wl_r<20> b_wl_r<19> b_wl_r<18> b_wl_r<17> b_wl_r<16> VDD! VSS! / RM_IHPSG13_256x32_c2_2P_WLDRV16X8 +XB_WLDRV<4> b_wi<15> b_wi<14> b_wi<13> b_wi<12> b_wi<11> b_wi<10> b_wi<9> b_wi<8> b_wi<7> b_wi<6> b_wi<5> b_wi<4> b_wi<3> b_wi<2> b_wi<1> b_wi<0> b_wl_r<15> b_wl_r<14> b_wl_r<13> b_wl_r<12> b_wl_r<11> b_wl_r<10> b_wl_r<9> b_wl_r<8> b_wl_r<7> b_wl_r<6> b_wl_r<5> b_wl_r<4> b_wl_r<3> b_wl_r<2> b_wl_r<1> b_wl_r<0> VDD! VSS! / RM_IHPSG13_256x32_c2_2P_WLDRV16X8 +XB_WLDRV<3> b_wi<63> b_wi<62> b_wi<61> b_wi<60> b_wi<59> b_wi<58> b_wi<57> b_wi<56> b_wi<55> b_wi<54> b_wi<53> b_wi<52> b_wi<51> b_wi<50> b_wi<49> b_wi<48> b_wl_l<63> b_wl_l<62> b_wl_l<61> b_wl_l<60> b_wl_l<59> b_wl_l<58> b_wl_l<57> b_wl_l<56> b_wl_l<55> b_wl_l<54> b_wl_l<53> b_wl_l<52> b_wl_l<51> b_wl_l<50> b_wl_l<49> b_wl_l<48> VDD! VSS! / RM_IHPSG13_256x32_c2_2P_WLDRV16X8 +XB_WLDRV<2> b_wi<47> b_wi<46> b_wi<45> b_wi<44> b_wi<43> b_wi<42> b_wi<41> b_wi<40> b_wi<39> b_wi<38> b_wi<37> b_wi<36> b_wi<35> b_wi<34> b_wi<33> b_wi<32> b_wl_l<47> b_wl_l<46> b_wl_l<45> b_wl_l<44> b_wl_l<43> b_wl_l<42> b_wl_l<41> b_wl_l<40> b_wl_l<39> b_wl_l<38> b_wl_l<37> b_wl_l<36> b_wl_l<35> b_wl_l<34> b_wl_l<33> b_wl_l<32> VDD! VSS! / RM_IHPSG13_256x32_c2_2P_WLDRV16X8 +XB_WLDRV<1> b_wi<31> b_wi<30> b_wi<29> b_wi<28> b_wi<27> b_wi<26> b_wi<25> b_wi<24> b_wi<23> b_wi<22> b_wi<21> b_wi<20> b_wi<19> b_wi<18> b_wi<17> b_wi<16> b_wl_l<31> b_wl_l<30> b_wl_l<29> b_wl_l<28> b_wl_l<27> b_wl_l<26> b_wl_l<25> b_wl_l<24> b_wl_l<23> b_wl_l<22> b_wl_l<21> b_wl_l<20> b_wl_l<19> b_wl_l<18> b_wl_l<17> b_wl_l<16> VDD! VSS! / RM_IHPSG13_256x32_c2_2P_WLDRV16X8 +XB_WLDRV<0> b_wi<15> b_wi<14> b_wi<13> b_wi<12> b_wi<11> b_wi<10> b_wi<9> b_wi<8> b_wi<7> b_wi<6> b_wi<5> b_wi<4> b_wi<3> b_wi<2> b_wi<1> b_wi<0> b_wl_l<15> b_wl_l<14> b_wl_l<13> b_wl_l<12> b_wl_l<11> b_wl_l<10> b_wl_l<9> b_wl_l<8> b_wl_l<7> b_wl_l<6> b_wl_l<5> b_wl_l<4> b_wl_l<3> b_wl_l<2> b_wl_l<1> b_wl_l<0> VDD! VSS! / RM_IHPSG13_256x32_c2_2P_WLDRV16X8 +XA_WLDRV<7> a_wi<63> a_wi<62> a_wi<61> a_wi<60> a_wi<59> a_wi<58> a_wi<57> a_wi<56> a_wi<55> a_wi<54> a_wi<53> a_wi<52> a_wi<51> a_wi<50> a_wi<49> a_wi<48> a_wl_r<63> a_wl_r<62> a_wl_r<61> a_wl_r<60> a_wl_r<59> a_wl_r<58> a_wl_r<57> a_wl_r<56> a_wl_r<55> a_wl_r<54> a_wl_r<53> a_wl_r<52> a_wl_r<51> a_wl_r<50> a_wl_r<49> a_wl_r<48> VDD! VSS! / RM_IHPSG13_256x32_c2_2P_WLDRV16X8 +XA_WLDRV<6> a_wi<47> a_wi<46> a_wi<45> a_wi<44> a_wi<43> a_wi<42> a_wi<41> a_wi<40> a_wi<39> a_wi<38> a_wi<37> a_wi<36> a_wi<35> a_wi<34> a_wi<33> a_wi<32> a_wl_r<47> a_wl_r<46> a_wl_r<45> a_wl_r<44> a_wl_r<43> a_wl_r<42> a_wl_r<41> a_wl_r<40> a_wl_r<39> a_wl_r<38> a_wl_r<37> a_wl_r<36> a_wl_r<35> a_wl_r<34> a_wl_r<33> a_wl_r<32> VDD! VSS! / RM_IHPSG13_256x32_c2_2P_WLDRV16X8 +XA_WLDRV<5> a_wi<31> a_wi<30> a_wi<29> a_wi<28> a_wi<27> a_wi<26> a_wi<25> a_wi<24> a_wi<23> a_wi<22> a_wi<21> a_wi<20> a_wi<19> a_wi<18> a_wi<17> a_wi<16> a_wl_r<31> a_wl_r<30> a_wl_r<29> a_wl_r<28> a_wl_r<27> a_wl_r<26> a_wl_r<25> a_wl_r<24> a_wl_r<23> a_wl_r<22> a_wl_r<21> a_wl_r<20> a_wl_r<19> a_wl_r<18> a_wl_r<17> a_wl_r<16> VDD! VSS! / RM_IHPSG13_256x32_c2_2P_WLDRV16X8 +XA_WLDRV<4> a_wi<15> a_wi<14> a_wi<13> a_wi<12> a_wi<11> a_wi<10> a_wi<9> a_wi<8> a_wi<7> a_wi<6> a_wi<5> a_wi<4> a_wi<3> a_wi<2> a_wi<1> a_wi<0> a_wl_r<15> a_wl_r<14> a_wl_r<13> a_wl_r<12> a_wl_r<11> a_wl_r<10> a_wl_r<9> a_wl_r<8> a_wl_r<7> a_wl_r<6> a_wl_r<5> a_wl_r<4> a_wl_r<3> a_wl_r<2> a_wl_r<1> a_wl_r<0> VDD! VSS! / RM_IHPSG13_256x32_c2_2P_WLDRV16X8 +XA_WLDRV<3> a_wi<63> a_wi<62> a_wi<61> a_wi<60> a_wi<59> a_wi<58> a_wi<57> a_wi<56> a_wi<55> a_wi<54> a_wi<53> a_wi<52> a_wi<51> a_wi<50> a_wi<49> a_wi<48> a_wl_l<63> a_wl_l<62> a_wl_l<61> a_wl_l<60> a_wl_l<59> a_wl_l<58> a_wl_l<57> a_wl_l<56> a_wl_l<55> a_wl_l<54> a_wl_l<53> a_wl_l<52> a_wl_l<51> a_wl_l<50> a_wl_l<49> a_wl_l<48> VDD! VSS! / RM_IHPSG13_256x32_c2_2P_WLDRV16X8 +XA_WLDRV<2> a_wi<47> a_wi<46> a_wi<45> a_wi<44> a_wi<43> a_wi<42> a_wi<41> a_wi<40> a_wi<39> a_wi<38> a_wi<37> a_wi<36> a_wi<35> a_wi<34> a_wi<33> a_wi<32> a_wl_l<47> a_wl_l<46> a_wl_l<45> a_wl_l<44> a_wl_l<43> a_wl_l<42> a_wl_l<41> a_wl_l<40> a_wl_l<39> a_wl_l<38> a_wl_l<37> a_wl_l<36> a_wl_l<35> a_wl_l<34> a_wl_l<33> a_wl_l<32> VDD! VSS! / RM_IHPSG13_256x32_c2_2P_WLDRV16X8 +XA_WLDRV<1> a_wi<31> a_wi<30> a_wi<29> a_wi<28> a_wi<27> a_wi<26> a_wi<25> a_wi<24> a_wi<23> a_wi<22> a_wi<21> a_wi<20> a_wi<19> a_wi<18> a_wi<17> a_wi<16> a_wl_l<31> a_wl_l<30> a_wl_l<29> a_wl_l<28> a_wl_l<27> a_wl_l<26> a_wl_l<25> a_wl_l<24> a_wl_l<23> a_wl_l<22> a_wl_l<21> a_wl_l<20> a_wl_l<19> a_wl_l<18> a_wl_l<17> a_wl_l<16> VDD! VSS! / RM_IHPSG13_256x32_c2_2P_WLDRV16X8 +XA_WLDRV<0> a_wi<15> a_wi<14> a_wi<13> a_wi<12> a_wi<11> a_wi<10> a_wi<9> a_wi<8> a_wi<7> a_wi<6> a_wi<5> a_wi<4> a_wi<3> a_wi<2> a_wi<1> a_wi<0> a_wl_l<15> a_wl_l<14> a_wl_l<13> a_wl_l<12> a_wl_l<11> a_wl_l<10> a_wl_l<9> a_wl_l<8> a_wl_l<7> a_wl_l<6> a_wl_l<5> a_wl_l<4> a_wl_l<3> a_wl_l<2> a_wl_l<1> a_wl_l<0> VDD! VSS! / RM_IHPSG13_256x32_c2_2P_WLDRV16X8 + + +XB_CTRL b_aclk_n B_BIST_CLK B_BIST_MEN B_BIST_EN B_BIST_REN B_BIST_WEN b_tiel B_CLK B_MEN b_dclk b_eclk b_pulse_h b_pulse_l b_pulse b_rclk B_REN b_cs b_wclk B_WEN VDD! VSS! / RM_IHPSG13_256x32_c2_2P_CTRL +XA_CTRL a_aclk_n A_BIST_CLK A_BIST_MEN A_BIST_EN A_BIST_REN A_BIST_WEN a_tiel A_CLK A_MEN a_dclk a_eclk a_pulse_h a_pulse_l a_pulse a_rclk A_REN a_cs a_wclk A_WEN VDD! VSS! / RM_IHPSG13_256x32_c2_2P_CTRL + + +XB_ROWDEC b_addr_row<5> b_addr_row<4> b_addr_row<3> b_addr_row<2> b_addr_row<1> b_addr_row<0> b_cs b_eclk b_wi<63> b_wi<62> b_wi<61> b_wi<60> b_wi<59> b_wi<58> b_wi<57> b_wi<56> b_wi<55> b_wi<54> b_wi<53> b_wi<52> b_wi<51> b_wi<50> b_wi<49> b_wi<48> b_wi<47> b_wi<46> b_wi<45> b_wi<44> b_wi<43> b_wi<42> b_wi<41> b_wi<40> b_wi<39> b_wi<38> b_wi<37> b_wi<36> b_wi<35> b_wi<34> b_wi<33> b_wi<32> b_wi<31> b_wi<30> b_wi<29> b_wi<28> b_wi<27> b_wi<26> b_wi<25> b_wi<24> b_wi<23> b_wi<22> b_wi<21> b_wi<20> b_wi<19> b_wi<18> b_wi<17> b_wi<16> b_wi<15> b_wi<14> b_wi<13> b_wi<12> b_wi<11> b_wi<10> b_wi<9> b_wi<8> b_wi<7> b_wi<6> b_wi<5> b_wi<4> b_wi<3> b_wi<2> b_wi<1> b_wi<0> VDD! VSS! / RM_IHPSG13_256x32_c2_2P_ROWDEC6 +XA_ROWDEC a_addr_row<5> a_addr_row<4> a_addr_row<3> a_addr_row<2> a_addr_row<1> a_addr_row<0> a_cs a_eclk a_wi<63> a_wi<62> a_wi<61> a_wi<60> a_wi<59> a_wi<58> a_wi<57> a_wi<56> a_wi<55> a_wi<54> a_wi<53> a_wi<52> a_wi<51> a_wi<50> a_wi<49> a_wi<48> a_wi<47> a_wi<46> a_wi<45> a_wi<44> a_wi<43> a_wi<42> a_wi<41> a_wi<40> a_wi<39> a_wi<38> a_wi<37> a_wi<36> a_wi<35> a_wi<34> a_wi<33> a_wi<32> a_wi<31> a_wi<30> a_wi<29> a_wi<28> a_wi<27> a_wi<26> a_wi<25> a_wi<24> a_wi<23> a_wi<22> a_wi<21> a_wi<20> a_wi<19> a_wi<18> a_wi<17> a_wi<16> a_wi<15> a_wi<14> a_wi<13> a_wi<12> a_wi<11> a_wi<10> a_wi<9> a_wi<8> a_wi<7> a_wi<6> a_wi<5> a_wi<4> a_wi<3> a_wi<2> a_wi<1> a_wi<0> VDD! VSS! / RM_IHPSG13_256x32_c2_2P_ROWDEC6 +XB_ROWREG b_aclk_n B_ADDR<7> B_ADDR<6> B_ADDR<5> B_ADDR<4> B_ADDR<3> B_ADDR<2> b_addr_row<5> b_addr_row<4> b_addr_row<3> b_addr_row<2> b_addr_row<1> b_addr_row<0> B_BIST_ADDR<7> B_BIST_ADDR<6> B_BIST_ADDR<5> B_BIST_ADDR<4> B_BIST_ADDR<3> B_BIST_ADDR<2> B_BIST_EN VDD! VSS! / RM_IHPSG13_256x32_c2_2P_ROWREG6 +XA_ROWREG a_aclk_n A_ADDR<7> A_ADDR<6> A_ADDR<5> A_ADDR<4> A_ADDR<3> A_ADDR<2> a_addr_row<5> a_addr_row<4> a_addr_row<3> a_addr_row<2> a_addr_row<1> a_addr_row<0> A_BIST_ADDR<7> A_BIST_ADDR<6> A_BIST_ADDR<5> A_BIST_ADDR<4> A_BIST_ADDR<3> A_BIST_ADDR<2> A_BIST_EN VDD! VSS! / RM_IHPSG13_256x32_c2_2P_ROWREG6 +XB_COLDEC b_aclk_n B_ADDR<1> B_ADDR<0> b_addr_col<1> b_addr_col<0> b_addr_dec<7> b_addr_dec<6> b_addr_dec<5> b_addr_dec<4> b_addr_dec<3> b_addr_dec<2> b_addr_dec<1> b_addr_dec<0> B_BIST_ADDR<1> B_BIST_ADDR<0> B_BIST_EN VDD! VSS! / RM_IHPSG13_256x32_c2_2P_COLDEC2 +XA_COLDEC a_aclk_n A_ADDR<1> A_ADDR<0> a_addr_col<1> a_addr_col<0> a_addr_dec<7> a_addr_dec<6> a_addr_dec<5> a_addr_dec<4> a_addr_dec<3> a_addr_dec<2> a_addr_dec<1> a_addr_dec<0> A_BIST_ADDR<1> A_BIST_ADDR<0> A_BIST_EN VDD! VSS! / RM_IHPSG13_256x32_c2_2P_COLDEC2 + + +XB_DLYH b_pulse b_pulse_h VDD! VSS! / RM_IHPSG13_256x32_c2_2P_DLY_pcell_2 +XB_DLYL b_pulse_x b_pulse_l VDD! VSS! / RM_IHPSG13_256x32_c2_2P_DLY_pcell_3 +XA_DLYH a_pulse a_pulse_h VDD! VSS! / RM_IHPSG13_256x32_c2_2P_DLY_pcell_2 +XA_DLYL a_pulse_x a_pulse_l VDD! VSS! / RM_IHPSG13_256x32_c2_2P_DLY_pcell_3 +XB_DLYMUX b_pulse_h B_DLY b_pulse_x VDD! VSS! / RM_IHPSG13_256x32_c2_2P_DLY_MUX +XA_DLYMUX a_pulse_h A_DLY a_pulse_x VDD! VSS! / RM_IHPSG13_256x32_c2_2P_DLY_MUX + +XCOLCTRL<31> a_addr_dec_r<3> a_addr_dec_r<2> a_addr_dec_r<1> a_addr_dec_r<0> A_BIST_BM<31> A_BIST_DIN<31> A_BIST_EN a_blc_r<63> a_blc_r<62> a_blc_r<61> a_blc_r<60> a_blt_r<63> a_blt_r<62> a_blt_r<61> a_blt_r<60> A_BM<31> a_dclk_n_r<15> a_dclk_n_r<16> a_dclk_p_r<15> a_dclk_p_r<16> A_DOUT<31> A_DIN<31> a_rclk_n_r<15> a_rclk_n_r<16> a_rclk_p_r<15> a_rclk_p_r<16> a_tieh<31> a_wclk_n_r<15> a_wclk_n_r<16> a_wclk_p_r<15> a_wclk_p_r<16> b_addr_dec_r<3> b_addr_dec_r<2> b_addr_dec_r<1> b_addr_dec_r<0> B_BIST_BM<31> B_BIST_DIN<31> B_BIST_EN b_blc_r<63> b_blc_r<62> b_blc_r<61> b_blc_r<60> b_blt_r<63> b_blt_r<62> b_blt_r<61> b_blt_r<60> B_BM<31> b_dclk_n_r<15> b_dclk_n_r<16> b_dclk_p_r<15> b_dclk_p_r<16> B_DOUT<31> B_DIN<31> b_rclk_n_r<15> b_rclk_n_r<16> b_rclk_p_r<15> b_rclk_p_r<16> b_tieh<31> b_wclk_n_r<15> b_wclk_n_r<16> b_wclk_p_r<15> b_wclk_p_r<16> VDD! VSS! / RM_IHPSG13_256x32_c2_2P_COLCTRL2 +XCOLCTRL<30> a_addr_dec_r<3> a_addr_dec_r<2> a_addr_dec_r<1> a_addr_dec_r<0> A_BIST_BM<30> A_BIST_DIN<30> A_BIST_EN a_blc_r<59> a_blc_r<58> a_blc_r<57> a_blc_r<56> a_blt_r<59> a_blt_r<58> a_blt_r<57> a_blt_r<56> A_BM<30> a_dclk_n_r<14> a_dclk_n_r<15> a_dclk_p_r<14> a_dclk_p_r<15> A_DOUT<30> A_DIN<30> a_rclk_n_r<14> a_rclk_n_r<15> a_rclk_p_r<14> a_rclk_p_r<15> a_tieh<30> a_wclk_n_r<14> a_wclk_n_r<15> a_wclk_p_r<14> a_wclk_p_r<15> b_addr_dec_r<3> b_addr_dec_r<2> b_addr_dec_r<1> b_addr_dec_r<0> B_BIST_BM<30> B_BIST_DIN<30> B_BIST_EN b_blc_r<59> b_blc_r<58> b_blc_r<57> b_blc_r<56> b_blt_r<59> b_blt_r<58> b_blt_r<57> b_blt_r<56> B_BM<30> b_dclk_n_r<14> b_dclk_n_r<15> b_dclk_p_r<14> b_dclk_p_r<15> B_DOUT<30> B_DIN<30> b_rclk_n_r<14> b_rclk_n_r<15> b_rclk_p_r<14> b_rclk_p_r<15> b_tieh<30> b_wclk_n_r<14> b_wclk_n_r<15> b_wclk_p_r<14> b_wclk_p_r<15> VDD! VSS! / RM_IHPSG13_256x32_c2_2P_COLCTRL2 +XCOLCTRL<29> a_addr_dec_r<3> a_addr_dec_r<2> a_addr_dec_r<1> a_addr_dec_r<0> A_BIST_BM<29> A_BIST_DIN<29> A_BIST_EN a_blc_r<55> a_blc_r<54> a_blc_r<53> a_blc_r<52> a_blt_r<55> a_blt_r<54> a_blt_r<53> a_blt_r<52> A_BM<29> a_dclk_n_r<13> a_dclk_n_r<14> a_dclk_p_r<13> a_dclk_p_r<14> A_DOUT<29> A_DIN<29> a_rclk_n_r<13> a_rclk_n_r<14> a_rclk_p_r<13> a_rclk_p_r<14> a_tieh<29> a_wclk_n_r<13> a_wclk_n_r<14> a_wclk_p_r<13> a_wclk_p_r<14> b_addr_dec_r<3> b_addr_dec_r<2> b_addr_dec_r<1> b_addr_dec_r<0> B_BIST_BM<29> B_BIST_DIN<29> B_BIST_EN b_blc_r<55> b_blc_r<54> b_blc_r<53> b_blc_r<52> b_blt_r<55> b_blt_r<54> b_blt_r<53> b_blt_r<52> B_BM<29> b_dclk_n_r<13> b_dclk_n_r<14> b_dclk_p_r<13> b_dclk_p_r<14> B_DOUT<29> B_DIN<29> b_rclk_n_r<13> b_rclk_n_r<14> b_rclk_p_r<13> b_rclk_p_r<14> b_tieh<29> b_wclk_n_r<13> b_wclk_n_r<14> b_wclk_p_r<13> b_wclk_p_r<14> VDD! VSS! / RM_IHPSG13_256x32_c2_2P_COLCTRL2 +XCOLCTRL<28> a_addr_dec_r<3> a_addr_dec_r<2> a_addr_dec_r<1> a_addr_dec_r<0> A_BIST_BM<28> A_BIST_DIN<28> A_BIST_EN a_blc_r<51> a_blc_r<50> a_blc_r<49> a_blc_r<48> a_blt_r<51> a_blt_r<50> a_blt_r<49> a_blt_r<48> A_BM<28> a_dclk_n_r<12> a_dclk_n_r<13> a_dclk_p_r<12> a_dclk_p_r<13> A_DOUT<28> A_DIN<28> a_rclk_n_r<12> a_rclk_n_r<13> a_rclk_p_r<12> a_rclk_p_r<13> a_tieh<28> a_wclk_n_r<12> a_wclk_n_r<13> a_wclk_p_r<12> a_wclk_p_r<13> b_addr_dec_r<3> b_addr_dec_r<2> b_addr_dec_r<1> b_addr_dec_r<0> B_BIST_BM<28> B_BIST_DIN<28> B_BIST_EN b_blc_r<51> b_blc_r<50> b_blc_r<49> b_blc_r<48> b_blt_r<51> b_blt_r<50> b_blt_r<49> b_blt_r<48> B_BM<28> b_dclk_n_r<12> b_dclk_n_r<13> b_dclk_p_r<12> b_dclk_p_r<13> B_DOUT<28> B_DIN<28> b_rclk_n_r<12> b_rclk_n_r<13> b_rclk_p_r<12> b_rclk_p_r<13> b_tieh<28> b_wclk_n_r<12> b_wclk_n_r<13> b_wclk_p_r<12> b_wclk_p_r<13> VDD! VSS! / RM_IHPSG13_256x32_c2_2P_COLCTRL2 +XCOLCTRL<27> a_addr_dec_r<3> a_addr_dec_r<2> a_addr_dec_r<1> a_addr_dec_r<0> A_BIST_BM<27> A_BIST_DIN<27> A_BIST_EN a_blc_r<47> a_blc_r<46> a_blc_r<45> a_blc_r<44> a_blt_r<47> a_blt_r<46> a_blt_r<45> a_blt_r<44> A_BM<27> a_dclk_n_r<11> a_dclk_n_r<12> a_dclk_p_r<11> a_dclk_p_r<12> A_DOUT<27> A_DIN<27> a_rclk_n_r<11> a_rclk_n_r<12> a_rclk_p_r<11> a_rclk_p_r<12> a_tieh<27> a_wclk_n_r<11> a_wclk_n_r<12> a_wclk_p_r<11> a_wclk_p_r<12> b_addr_dec_r<3> b_addr_dec_r<2> b_addr_dec_r<1> b_addr_dec_r<0> B_BIST_BM<27> B_BIST_DIN<27> B_BIST_EN b_blc_r<47> b_blc_r<46> b_blc_r<45> b_blc_r<44> b_blt_r<47> b_blt_r<46> b_blt_r<45> b_blt_r<44> B_BM<27> b_dclk_n_r<11> b_dclk_n_r<12> b_dclk_p_r<11> b_dclk_p_r<12> B_DOUT<27> B_DIN<27> b_rclk_n_r<11> b_rclk_n_r<12> b_rclk_p_r<11> b_rclk_p_r<12> b_tieh<27> b_wclk_n_r<11> b_wclk_n_r<12> b_wclk_p_r<11> b_wclk_p_r<12> VDD! VSS! / RM_IHPSG13_256x32_c2_2P_COLCTRL2 +XCOLCTRL<26> a_addr_dec_r<3> a_addr_dec_r<2> a_addr_dec_r<1> a_addr_dec_r<0> A_BIST_BM<26> A_BIST_DIN<26> A_BIST_EN a_blc_r<43> a_blc_r<42> a_blc_r<41> a_blc_r<40> a_blt_r<43> a_blt_r<42> a_blt_r<41> a_blt_r<40> A_BM<26> a_dclk_n_r<10> a_dclk_n_r<11> a_dclk_p_r<10> a_dclk_p_r<11> A_DOUT<26> A_DIN<26> a_rclk_n_r<10> a_rclk_n_r<11> a_rclk_p_r<10> a_rclk_p_r<11> a_tieh<26> a_wclk_n_r<10> a_wclk_n_r<11> a_wclk_p_r<10> a_wclk_p_r<11> b_addr_dec_r<3> b_addr_dec_r<2> b_addr_dec_r<1> b_addr_dec_r<0> B_BIST_BM<26> B_BIST_DIN<26> B_BIST_EN b_blc_r<43> b_blc_r<42> b_blc_r<41> b_blc_r<40> b_blt_r<43> b_blt_r<42> b_blt_r<41> b_blt_r<40> B_BM<26> b_dclk_n_r<10> b_dclk_n_r<11> b_dclk_p_r<10> b_dclk_p_r<11> B_DOUT<26> B_DIN<26> b_rclk_n_r<10> b_rclk_n_r<11> b_rclk_p_r<10> b_rclk_p_r<11> b_tieh<26> b_wclk_n_r<10> b_wclk_n_r<11> b_wclk_p_r<10> b_wclk_p_r<11> VDD! VSS! / RM_IHPSG13_256x32_c2_2P_COLCTRL2 +XCOLCTRL<25> a_addr_dec_r<3> a_addr_dec_r<2> a_addr_dec_r<1> a_addr_dec_r<0> A_BIST_BM<25> A_BIST_DIN<25> A_BIST_EN a_blc_r<39> a_blc_r<38> a_blc_r<37> a_blc_r<36> a_blt_r<39> a_blt_r<38> a_blt_r<37> a_blt_r<36> A_BM<25> a_dclk_n_r<9> a_dclk_n_r<10> a_dclk_p_r<9> a_dclk_p_r<10> A_DOUT<25> A_DIN<25> a_rclk_n_r<9> a_rclk_n_r<10> a_rclk_p_r<9> a_rclk_p_r<10> a_tieh<25> a_wclk_n_r<9> a_wclk_n_r<10> a_wclk_p_r<9> a_wclk_p_r<10> b_addr_dec_r<3> b_addr_dec_r<2> b_addr_dec_r<1> b_addr_dec_r<0> B_BIST_BM<25> B_BIST_DIN<25> B_BIST_EN b_blc_r<39> b_blc_r<38> b_blc_r<37> b_blc_r<36> b_blt_r<39> b_blt_r<38> b_blt_r<37> b_blt_r<36> B_BM<25> b_dclk_n_r<9> b_dclk_n_r<10> b_dclk_p_r<9> b_dclk_p_r<10> B_DOUT<25> B_DIN<25> b_rclk_n_r<9> b_rclk_n_r<10> b_rclk_p_r<9> b_rclk_p_r<10> b_tieh<25> b_wclk_n_r<9> b_wclk_n_r<10> b_wclk_p_r<9> b_wclk_p_r<10> VDD! VSS! / RM_IHPSG13_256x32_c2_2P_COLCTRL2 +XCOLCTRL<24> a_addr_dec_r<3> a_addr_dec_r<2> a_addr_dec_r<1> a_addr_dec_r<0> A_BIST_BM<24> A_BIST_DIN<24> A_BIST_EN a_blc_r<35> a_blc_r<34> a_blc_r<33> a_blc_r<32> a_blt_r<35> a_blt_r<34> a_blt_r<33> a_blt_r<32> A_BM<24> a_dclk_n_r<8> a_dclk_n_r<9> a_dclk_p_r<8> a_dclk_p_r<9> A_DOUT<24> A_DIN<24> a_rclk_n_r<8> a_rclk_n_r<9> a_rclk_p_r<8> a_rclk_p_r<9> a_tieh<24> a_wclk_n_r<8> a_wclk_n_r<9> a_wclk_p_r<8> a_wclk_p_r<9> b_addr_dec_r<3> b_addr_dec_r<2> b_addr_dec_r<1> b_addr_dec_r<0> B_BIST_BM<24> B_BIST_DIN<24> B_BIST_EN b_blc_r<35> b_blc_r<34> b_blc_r<33> b_blc_r<32> b_blt_r<35> b_blt_r<34> b_blt_r<33> b_blt_r<32> B_BM<24> b_dclk_n_r<8> b_dclk_n_r<9> b_dclk_p_r<8> b_dclk_p_r<9> B_DOUT<24> B_DIN<24> b_rclk_n_r<8> b_rclk_n_r<9> b_rclk_p_r<8> b_rclk_p_r<9> b_tieh<24> b_wclk_n_r<8> b_wclk_n_r<9> b_wclk_p_r<8> b_wclk_p_r<9> VDD! VSS! / RM_IHPSG13_256x32_c2_2P_COLCTRL2 +XCOLCTRL<23> a_addr_dec_r<3> a_addr_dec_r<2> a_addr_dec_r<1> a_addr_dec_r<0> A_BIST_BM<23> A_BIST_DIN<23> A_BIST_EN a_blc_r<31> a_blc_r<30> a_blc_r<29> a_blc_r<28> a_blt_r<31> a_blt_r<30> a_blt_r<29> a_blt_r<28> A_BM<23> a_dclk_n_r<7> a_dclk_n_r<8> a_dclk_p_r<7> a_dclk_p_r<8> A_DOUT<23> A_DIN<23> a_rclk_n_r<7> a_rclk_n_r<8> a_rclk_p_r<7> a_rclk_p_r<8> a_tieh<23> a_wclk_n_r<7> a_wclk_n_r<8> a_wclk_p_r<7> a_wclk_p_r<8> b_addr_dec_r<3> b_addr_dec_r<2> b_addr_dec_r<1> b_addr_dec_r<0> B_BIST_BM<23> B_BIST_DIN<23> B_BIST_EN b_blc_r<31> b_blc_r<30> b_blc_r<29> b_blc_r<28> b_blt_r<31> b_blt_r<30> b_blt_r<29> b_blt_r<28> B_BM<23> b_dclk_n_r<7> b_dclk_n_r<8> b_dclk_p_r<7> b_dclk_p_r<8> B_DOUT<23> B_DIN<23> b_rclk_n_r<7> b_rclk_n_r<8> b_rclk_p_r<7> b_rclk_p_r<8> b_tieh<23> b_wclk_n_r<7> b_wclk_n_r<8> b_wclk_p_r<7> b_wclk_p_r<8> VDD! VSS! / RM_IHPSG13_256x32_c2_2P_COLCTRL2 +XCOLCTRL<22> a_addr_dec_r<3> a_addr_dec_r<2> a_addr_dec_r<1> a_addr_dec_r<0> A_BIST_BM<22> A_BIST_DIN<22> A_BIST_EN a_blc_r<27> a_blc_r<26> a_blc_r<25> a_blc_r<24> a_blt_r<27> a_blt_r<26> a_blt_r<25> a_blt_r<24> A_BM<22> a_dclk_n_r<6> a_dclk_n_r<7> a_dclk_p_r<6> a_dclk_p_r<7> A_DOUT<22> A_DIN<22> a_rclk_n_r<6> a_rclk_n_r<7> a_rclk_p_r<6> a_rclk_p_r<7> a_tieh<22> a_wclk_n_r<6> a_wclk_n_r<7> a_wclk_p_r<6> a_wclk_p_r<7> b_addr_dec_r<3> b_addr_dec_r<2> b_addr_dec_r<1> b_addr_dec_r<0> B_BIST_BM<22> B_BIST_DIN<22> B_BIST_EN b_blc_r<27> b_blc_r<26> b_blc_r<25> b_blc_r<24> b_blt_r<27> b_blt_r<26> b_blt_r<25> b_blt_r<24> B_BM<22> b_dclk_n_r<6> b_dclk_n_r<7> b_dclk_p_r<6> b_dclk_p_r<7> B_DOUT<22> B_DIN<22> b_rclk_n_r<6> b_rclk_n_r<7> b_rclk_p_r<6> b_rclk_p_r<7> b_tieh<22> b_wclk_n_r<6> b_wclk_n_r<7> b_wclk_p_r<6> b_wclk_p_r<7> VDD! VSS! / RM_IHPSG13_256x32_c2_2P_COLCTRL2 +XCOLCTRL<21> a_addr_dec_r<3> a_addr_dec_r<2> a_addr_dec_r<1> a_addr_dec_r<0> A_BIST_BM<21> A_BIST_DIN<21> A_BIST_EN a_blc_r<23> a_blc_r<22> a_blc_r<21> a_blc_r<20> a_blt_r<23> a_blt_r<22> a_blt_r<21> a_blt_r<20> A_BM<21> a_dclk_n_r<5> a_dclk_n_r<6> a_dclk_p_r<5> a_dclk_p_r<6> A_DOUT<21> A_DIN<21> a_rclk_n_r<5> a_rclk_n_r<6> a_rclk_p_r<5> a_rclk_p_r<6> a_tieh<21> a_wclk_n_r<5> a_wclk_n_r<6> a_wclk_p_r<5> a_wclk_p_r<6> b_addr_dec_r<3> b_addr_dec_r<2> b_addr_dec_r<1> b_addr_dec_r<0> B_BIST_BM<21> B_BIST_DIN<21> B_BIST_EN b_blc_r<23> b_blc_r<22> b_blc_r<21> b_blc_r<20> b_blt_r<23> b_blt_r<22> b_blt_r<21> b_blt_r<20> B_BM<21> b_dclk_n_r<5> b_dclk_n_r<6> b_dclk_p_r<5> b_dclk_p_r<6> B_DOUT<21> B_DIN<21> b_rclk_n_r<5> b_rclk_n_r<6> b_rclk_p_r<5> b_rclk_p_r<6> b_tieh<21> b_wclk_n_r<5> b_wclk_n_r<6> b_wclk_p_r<5> b_wclk_p_r<6> VDD! VSS! / RM_IHPSG13_256x32_c2_2P_COLCTRL2 +XCOLCTRL<20> a_addr_dec_r<3> a_addr_dec_r<2> a_addr_dec_r<1> a_addr_dec_r<0> A_BIST_BM<20> A_BIST_DIN<20> A_BIST_EN a_blc_r<19> a_blc_r<18> a_blc_r<17> a_blc_r<16> a_blt_r<19> a_blt_r<18> a_blt_r<17> a_blt_r<16> A_BM<20> a_dclk_n_r<4> a_dclk_n_r<5> a_dclk_p_r<4> a_dclk_p_r<5> A_DOUT<20> A_DIN<20> a_rclk_n_r<4> a_rclk_n_r<5> a_rclk_p_r<4> a_rclk_p_r<5> a_tieh<20> a_wclk_n_r<4> a_wclk_n_r<5> a_wclk_p_r<4> a_wclk_p_r<5> b_addr_dec_r<3> b_addr_dec_r<2> b_addr_dec_r<1> b_addr_dec_r<0> B_BIST_BM<20> B_BIST_DIN<20> B_BIST_EN b_blc_r<19> b_blc_r<18> b_blc_r<17> b_blc_r<16> b_blt_r<19> b_blt_r<18> b_blt_r<17> b_blt_r<16> B_BM<20> b_dclk_n_r<4> b_dclk_n_r<5> b_dclk_p_r<4> b_dclk_p_r<5> B_DOUT<20> B_DIN<20> b_rclk_n_r<4> b_rclk_n_r<5> b_rclk_p_r<4> b_rclk_p_r<5> b_tieh<20> b_wclk_n_r<4> b_wclk_n_r<5> b_wclk_p_r<4> b_wclk_p_r<5> VDD! VSS! / RM_IHPSG13_256x32_c2_2P_COLCTRL2 +XCOLCTRL<19> a_addr_dec_r<3> a_addr_dec_r<2> a_addr_dec_r<1> a_addr_dec_r<0> A_BIST_BM<19> A_BIST_DIN<19> A_BIST_EN a_blc_r<15> a_blc_r<14> a_blc_r<13> a_blc_r<12> a_blt_r<15> a_blt_r<14> a_blt_r<13> a_blt_r<12> A_BM<19> a_dclk_n_r<3> a_dclk_n_r<4> a_dclk_p_r<3> a_dclk_p_r<4> A_DOUT<19> A_DIN<19> a_rclk_n_r<3> a_rclk_n_r<4> a_rclk_p_r<3> a_rclk_p_r<4> a_tieh<19> a_wclk_n_r<3> a_wclk_n_r<4> a_wclk_p_r<3> a_wclk_p_r<4> b_addr_dec_r<3> b_addr_dec_r<2> b_addr_dec_r<1> b_addr_dec_r<0> B_BIST_BM<19> B_BIST_DIN<19> B_BIST_EN b_blc_r<15> b_blc_r<14> b_blc_r<13> b_blc_r<12> b_blt_r<15> b_blt_r<14> b_blt_r<13> b_blt_r<12> B_BM<19> b_dclk_n_r<3> b_dclk_n_r<4> b_dclk_p_r<3> b_dclk_p_r<4> B_DOUT<19> B_DIN<19> b_rclk_n_r<3> b_rclk_n_r<4> b_rclk_p_r<3> b_rclk_p_r<4> b_tieh<19> b_wclk_n_r<3> b_wclk_n_r<4> b_wclk_p_r<3> b_wclk_p_r<4> VDD! VSS! / RM_IHPSG13_256x32_c2_2P_COLCTRL2 +XCOLCTRL<18> a_addr_dec_r<3> a_addr_dec_r<2> a_addr_dec_r<1> a_addr_dec_r<0> A_BIST_BM<18> A_BIST_DIN<18> A_BIST_EN a_blc_r<11> a_blc_r<10> a_blc_r<9> a_blc_r<8> a_blt_r<11> a_blt_r<10> a_blt_r<9> a_blt_r<8> A_BM<18> a_dclk_n_r<2> a_dclk_n_r<3> a_dclk_p_r<2> a_dclk_p_r<3> A_DOUT<18> A_DIN<18> a_rclk_n_r<2> a_rclk_n_r<3> a_rclk_p_r<2> a_rclk_p_r<3> a_tieh<18> a_wclk_n_r<2> a_wclk_n_r<3> a_wclk_p_r<2> a_wclk_p_r<3> b_addr_dec_r<3> b_addr_dec_r<2> b_addr_dec_r<1> b_addr_dec_r<0> B_BIST_BM<18> B_BIST_DIN<18> B_BIST_EN b_blc_r<11> b_blc_r<10> b_blc_r<9> b_blc_r<8> b_blt_r<11> b_blt_r<10> b_blt_r<9> b_blt_r<8> B_BM<18> b_dclk_n_r<2> b_dclk_n_r<3> b_dclk_p_r<2> b_dclk_p_r<3> B_DOUT<18> B_DIN<18> b_rclk_n_r<2> b_rclk_n_r<3> b_rclk_p_r<2> b_rclk_p_r<3> b_tieh<18> b_wclk_n_r<2> b_wclk_n_r<3> b_wclk_p_r<2> b_wclk_p_r<3> VDD! VSS! / RM_IHPSG13_256x32_c2_2P_COLCTRL2 +XCOLCTRL<17> a_addr_dec_r<3> a_addr_dec_r<2> a_addr_dec_r<1> a_addr_dec_r<0> A_BIST_BM<17> A_BIST_DIN<17> A_BIST_EN a_blc_r<7> a_blc_r<6> a_blc_r<5> a_blc_r<4> a_blt_r<7> a_blt_r<6> a_blt_r<5> a_blt_r<4> A_BM<17> a_dclk_n_r<1> a_dclk_n_r<2> a_dclk_p_r<1> a_dclk_p_r<2> A_DOUT<17> A_DIN<17> a_rclk_n_r<1> a_rclk_n_r<2> a_rclk_p_r<1> a_rclk_p_r<2> a_tieh<17> a_wclk_n_r<1> a_wclk_n_r<2> a_wclk_p_r<1> a_wclk_p_r<2> b_addr_dec_r<3> b_addr_dec_r<2> b_addr_dec_r<1> b_addr_dec_r<0> B_BIST_BM<17> B_BIST_DIN<17> B_BIST_EN b_blc_r<7> b_blc_r<6> b_blc_r<5> b_blc_r<4> b_blt_r<7> b_blt_r<6> b_blt_r<5> b_blt_r<4> B_BM<17> b_dclk_n_r<1> b_dclk_n_r<2> b_dclk_p_r<1> b_dclk_p_r<2> B_DOUT<17> B_DIN<17> b_rclk_n_r<1> b_rclk_n_r<2> b_rclk_p_r<1> b_rclk_p_r<2> b_tieh<17> b_wclk_n_r<1> b_wclk_n_r<2> b_wclk_p_r<1> b_wclk_p_r<2> VDD! VSS! / RM_IHPSG13_256x32_c2_2P_COLCTRL2 +XCOLCTRL<16> a_addr_dec_r<3> a_addr_dec_r<2> a_addr_dec_r<1> a_addr_dec_r<0> A_BIST_BM<16> A_BIST_DIN<16> A_BIST_EN a_blc_r<3> a_blc_r<2> a_blc_r<1> a_blc_r<0> a_blt_r<3> a_blt_r<2> a_blt_r<1> a_blt_r<0> A_BM<16> a_dclk_n_r<0> a_dclk_n_r<1> a_dclk_p_r<0> a_dclk_p_r<1> A_DOUT<16> A_DIN<16> a_rclk_n_r<0> a_rclk_n_r<1> a_rclk_p_r<0> a_rclk_p_r<1> a_tieh<16> a_wclk_n_r<0> a_wclk_n_r<1> a_wclk_p_r<0> a_wclk_p_r<1> b_addr_dec_r<3> b_addr_dec_r<2> b_addr_dec_r<1> b_addr_dec_r<0> B_BIST_BM<16> B_BIST_DIN<16> B_BIST_EN b_blc_r<3> b_blc_r<2> b_blc_r<1> b_blc_r<0> b_blt_r<3> b_blt_r<2> b_blt_r<1> b_blt_r<0> B_BM<16> b_dclk_n_r<0> b_dclk_n_r<1> b_dclk_p_r<0> b_dclk_p_r<1> B_DOUT<16> B_DIN<16> b_rclk_n_r<0> b_rclk_n_r<1> b_rclk_p_r<0> b_rclk_p_r<1> b_tieh<16> b_wclk_n_r<0> b_wclk_n_r<1> b_wclk_p_r<0> b_wclk_p_r<1> VDD! VSS! / RM_IHPSG13_256x32_c2_2P_COLCTRL2 +XCOLCTRL<15> a_addr_dec_l<3> a_addr_dec_l<2> a_addr_dec_l<1> a_addr_dec_l<0> A_BIST_BM<0> A_BIST_DIN<0> A_BIST_EN a_blc_l<63> a_blc_l<62> a_blc_l<61> a_blc_l<60> a_blt_l<63> a_blt_l<62> a_blt_l<61> a_blt_l<60> A_BM<0> a_dclk_n_l<15> a_dclk_n_l<16> a_dclk_p_l<15> a_dclk_p_l<16> A_DOUT<0> A_DIN<0> a_rclk_n_l<15> a_rclk_n_l<16> a_rclk_p_l<15> a_rclk_p_l<16> a_tieh<0> a_wclk_n_l<15> a_wclk_n_l<16> a_wclk_p_l<15> a_wclk_p_l<16> b_addr_dec_l<3> b_addr_dec_l<2> b_addr_dec_l<1> b_addr_dec_l<0> B_BIST_BM<0> B_BIST_DIN<0> B_BIST_EN b_blc_l<63> b_blc_l<62> b_blc_l<61> b_blc_l<60> b_blt_l<63> b_blt_l<62> b_blt_l<61> b_blt_l<60> B_BM<0> b_dclk_n_l<15> b_dclk_n_l<16> b_dclk_p_l<15> b_dclk_p_l<16> B_DOUT<0> B_DIN<0> b_rclk_n_l<15> b_rclk_n_l<16> b_rclk_p_l<15> b_rclk_p_l<16> b_tieh<0> b_wclk_n_l<15> b_wclk_n_l<16> b_wclk_p_l<15> b_wclk_p_l<16> VDD! VSS! / RM_IHPSG13_256x32_c2_2P_COLCTRL2 +XCOLCTRL<14> a_addr_dec_l<3> a_addr_dec_l<2> a_addr_dec_l<1> a_addr_dec_l<0> A_BIST_BM<1> A_BIST_DIN<1> A_BIST_EN a_blc_l<59> a_blc_l<58> a_blc_l<57> a_blc_l<56> a_blt_l<59> a_blt_l<58> a_blt_l<57> a_blt_l<56> A_BM<1> a_dclk_n_l<14> a_dclk_n_l<15> a_dclk_p_l<14> a_dclk_p_l<15> A_DOUT<1> A_DIN<1> a_rclk_n_l<14> a_rclk_n_l<15> a_rclk_p_l<14> a_rclk_p_l<15> a_tieh<1> a_wclk_n_l<14> a_wclk_n_l<15> a_wclk_p_l<14> a_wclk_p_l<15> b_addr_dec_l<3> b_addr_dec_l<2> b_addr_dec_l<1> b_addr_dec_l<0> B_BIST_BM<1> B_BIST_DIN<1> B_BIST_EN b_blc_l<59> b_blc_l<58> b_blc_l<57> b_blc_l<56> b_blt_l<59> b_blt_l<58> b_blt_l<57> b_blt_l<56> B_BM<1> b_dclk_n_l<14> b_dclk_n_l<15> b_dclk_p_l<14> b_dclk_p_l<15> B_DOUT<1> B_DIN<1> b_rclk_n_l<14> b_rclk_n_l<15> b_rclk_p_l<14> b_rclk_p_l<15> b_tieh<1> b_wclk_n_l<14> b_wclk_n_l<15> b_wclk_p_l<14> b_wclk_p_l<15> VDD! VSS! / RM_IHPSG13_256x32_c2_2P_COLCTRL2 +XCOLCTRL<13> a_addr_dec_l<3> a_addr_dec_l<2> a_addr_dec_l<1> a_addr_dec_l<0> A_BIST_BM<2> A_BIST_DIN<2> A_BIST_EN a_blc_l<55> a_blc_l<54> a_blc_l<53> a_blc_l<52> a_blt_l<55> a_blt_l<54> a_blt_l<53> a_blt_l<52> A_BM<2> a_dclk_n_l<13> a_dclk_n_l<14> a_dclk_p_l<13> a_dclk_p_l<14> A_DOUT<2> A_DIN<2> a_rclk_n_l<13> a_rclk_n_l<14> a_rclk_p_l<13> a_rclk_p_l<14> a_tieh<2> a_wclk_n_l<13> a_wclk_n_l<14> a_wclk_p_l<13> a_wclk_p_l<14> b_addr_dec_l<3> b_addr_dec_l<2> b_addr_dec_l<1> b_addr_dec_l<0> B_BIST_BM<2> B_BIST_DIN<2> B_BIST_EN b_blc_l<55> b_blc_l<54> b_blc_l<53> b_blc_l<52> b_blt_l<55> b_blt_l<54> b_blt_l<53> b_blt_l<52> B_BM<2> b_dclk_n_l<13> b_dclk_n_l<14> b_dclk_p_l<13> b_dclk_p_l<14> B_DOUT<2> B_DIN<2> b_rclk_n_l<13> b_rclk_n_l<14> b_rclk_p_l<13> b_rclk_p_l<14> b_tieh<2> b_wclk_n_l<13> b_wclk_n_l<14> b_wclk_p_l<13> b_wclk_p_l<14> VDD! VSS! / RM_IHPSG13_256x32_c2_2P_COLCTRL2 +XCOLCTRL<12> a_addr_dec_l<3> a_addr_dec_l<2> a_addr_dec_l<1> a_addr_dec_l<0> A_BIST_BM<3> A_BIST_DIN<3> A_BIST_EN a_blc_l<51> a_blc_l<50> a_blc_l<49> a_blc_l<48> a_blt_l<51> a_blt_l<50> a_blt_l<49> a_blt_l<48> A_BM<3> a_dclk_n_l<12> a_dclk_n_l<13> a_dclk_p_l<12> a_dclk_p_l<13> A_DOUT<3> A_DIN<3> a_rclk_n_l<12> a_rclk_n_l<13> a_rclk_p_l<12> a_rclk_p_l<13> a_tieh<3> a_wclk_n_l<12> a_wclk_n_l<13> a_wclk_p_l<12> a_wclk_p_l<13> b_addr_dec_l<3> b_addr_dec_l<2> b_addr_dec_l<1> b_addr_dec_l<0> B_BIST_BM<3> B_BIST_DIN<3> B_BIST_EN b_blc_l<51> b_blc_l<50> b_blc_l<49> b_blc_l<48> b_blt_l<51> b_blt_l<50> b_blt_l<49> b_blt_l<48> B_BM<3> b_dclk_n_l<12> b_dclk_n_l<13> b_dclk_p_l<12> b_dclk_p_l<13> B_DOUT<3> B_DIN<3> b_rclk_n_l<12> b_rclk_n_l<13> b_rclk_p_l<12> b_rclk_p_l<13> b_tieh<3> b_wclk_n_l<12> b_wclk_n_l<13> b_wclk_p_l<12> b_wclk_p_l<13> VDD! VSS! / RM_IHPSG13_256x32_c2_2P_COLCTRL2 +XCOLCTRL<11> a_addr_dec_l<3> a_addr_dec_l<2> a_addr_dec_l<1> a_addr_dec_l<0> A_BIST_BM<4> A_BIST_DIN<4> A_BIST_EN a_blc_l<47> a_blc_l<46> a_blc_l<45> a_blc_l<44> a_blt_l<47> a_blt_l<46> a_blt_l<45> a_blt_l<44> A_BM<4> a_dclk_n_l<11> a_dclk_n_l<12> a_dclk_p_l<11> a_dclk_p_l<12> A_DOUT<4> A_DIN<4> a_rclk_n_l<11> a_rclk_n_l<12> a_rclk_p_l<11> a_rclk_p_l<12> a_tieh<4> a_wclk_n_l<11> a_wclk_n_l<12> a_wclk_p_l<11> a_wclk_p_l<12> b_addr_dec_l<3> b_addr_dec_l<2> b_addr_dec_l<1> b_addr_dec_l<0> B_BIST_BM<4> B_BIST_DIN<4> B_BIST_EN b_blc_l<47> b_blc_l<46> b_blc_l<45> b_blc_l<44> b_blt_l<47> b_blt_l<46> b_blt_l<45> b_blt_l<44> B_BM<4> b_dclk_n_l<11> b_dclk_n_l<12> b_dclk_p_l<11> b_dclk_p_l<12> B_DOUT<4> B_DIN<4> b_rclk_n_l<11> b_rclk_n_l<12> b_rclk_p_l<11> b_rclk_p_l<12> b_tieh<4> b_wclk_n_l<11> b_wclk_n_l<12> b_wclk_p_l<11> b_wclk_p_l<12> VDD! VSS! / RM_IHPSG13_256x32_c2_2P_COLCTRL2 +XCOLCTRL<10> a_addr_dec_l<3> a_addr_dec_l<2> a_addr_dec_l<1> a_addr_dec_l<0> A_BIST_BM<5> A_BIST_DIN<5> A_BIST_EN a_blc_l<43> a_blc_l<42> a_blc_l<41> a_blc_l<40> a_blt_l<43> a_blt_l<42> a_blt_l<41> a_blt_l<40> A_BM<5> a_dclk_n_l<10> a_dclk_n_l<11> a_dclk_p_l<10> a_dclk_p_l<11> A_DOUT<5> A_DIN<5> a_rclk_n_l<10> a_rclk_n_l<11> a_rclk_p_l<10> a_rclk_p_l<11> a_tieh<5> a_wclk_n_l<10> a_wclk_n_l<11> a_wclk_p_l<10> a_wclk_p_l<11> b_addr_dec_l<3> b_addr_dec_l<2> b_addr_dec_l<1> b_addr_dec_l<0> B_BIST_BM<5> B_BIST_DIN<5> B_BIST_EN b_blc_l<43> b_blc_l<42> b_blc_l<41> b_blc_l<40> b_blt_l<43> b_blt_l<42> b_blt_l<41> b_blt_l<40> B_BM<5> b_dclk_n_l<10> b_dclk_n_l<11> b_dclk_p_l<10> b_dclk_p_l<11> B_DOUT<5> B_DIN<5> b_rclk_n_l<10> b_rclk_n_l<11> b_rclk_p_l<10> b_rclk_p_l<11> b_tieh<5> b_wclk_n_l<10> b_wclk_n_l<11> b_wclk_p_l<10> b_wclk_p_l<11> VDD! VSS! / RM_IHPSG13_256x32_c2_2P_COLCTRL2 +XCOLCTRL<9> a_addr_dec_l<3> a_addr_dec_l<2> a_addr_dec_l<1> a_addr_dec_l<0> A_BIST_BM<6> A_BIST_DIN<6> A_BIST_EN a_blc_l<39> a_blc_l<38> a_blc_l<37> a_blc_l<36> a_blt_l<39> a_blt_l<38> a_blt_l<37> a_blt_l<36> A_BM<6> a_dclk_n_l<9> a_dclk_n_l<10> a_dclk_p_l<9> a_dclk_p_l<10> A_DOUT<6> A_DIN<6> a_rclk_n_l<9> a_rclk_n_l<10> a_rclk_p_l<9> a_rclk_p_l<10> a_tieh<6> a_wclk_n_l<9> a_wclk_n_l<10> a_wclk_p_l<9> a_wclk_p_l<10> b_addr_dec_l<3> b_addr_dec_l<2> b_addr_dec_l<1> b_addr_dec_l<0> B_BIST_BM<6> B_BIST_DIN<6> B_BIST_EN b_blc_l<39> b_blc_l<38> b_blc_l<37> b_blc_l<36> b_blt_l<39> b_blt_l<38> b_blt_l<37> b_blt_l<36> B_BM<6> b_dclk_n_l<9> b_dclk_n_l<10> b_dclk_p_l<9> b_dclk_p_l<10> B_DOUT<6> B_DIN<6> b_rclk_n_l<9> b_rclk_n_l<10> b_rclk_p_l<9> b_rclk_p_l<10> b_tieh<6> b_wclk_n_l<9> b_wclk_n_l<10> b_wclk_p_l<9> b_wclk_p_l<10> VDD! VSS! / RM_IHPSG13_256x32_c2_2P_COLCTRL2 +XCOLCTRL<8> a_addr_dec_l<3> a_addr_dec_l<2> a_addr_dec_l<1> a_addr_dec_l<0> A_BIST_BM<7> A_BIST_DIN<7> A_BIST_EN a_blc_l<35> a_blc_l<34> a_blc_l<33> a_blc_l<32> a_blt_l<35> a_blt_l<34> a_blt_l<33> a_blt_l<32> A_BM<7> a_dclk_n_l<8> a_dclk_n_l<9> a_dclk_p_l<8> a_dclk_p_l<9> A_DOUT<7> A_DIN<7> a_rclk_n_l<8> a_rclk_n_l<9> a_rclk_p_l<8> a_rclk_p_l<9> a_tieh<7> a_wclk_n_l<8> a_wclk_n_l<9> a_wclk_p_l<8> a_wclk_p_l<9> b_addr_dec_l<3> b_addr_dec_l<2> b_addr_dec_l<1> b_addr_dec_l<0> B_BIST_BM<7> B_BIST_DIN<7> B_BIST_EN b_blc_l<35> b_blc_l<34> b_blc_l<33> b_blc_l<32> b_blt_l<35> b_blt_l<34> b_blt_l<33> b_blt_l<32> B_BM<7> b_dclk_n_l<8> b_dclk_n_l<9> b_dclk_p_l<8> b_dclk_p_l<9> B_DOUT<7> B_DIN<7> b_rclk_n_l<8> b_rclk_n_l<9> b_rclk_p_l<8> b_rclk_p_l<9> b_tieh<7> b_wclk_n_l<8> b_wclk_n_l<9> b_wclk_p_l<8> b_wclk_p_l<9> VDD! VSS! / RM_IHPSG13_256x32_c2_2P_COLCTRL2 +XCOLCTRL<7> a_addr_dec_l<3> a_addr_dec_l<2> a_addr_dec_l<1> a_addr_dec_l<0> A_BIST_BM<8> A_BIST_DIN<8> A_BIST_EN a_blc_l<31> a_blc_l<30> a_blc_l<29> a_blc_l<28> a_blt_l<31> a_blt_l<30> a_blt_l<29> a_blt_l<28> A_BM<8> a_dclk_n_l<7> a_dclk_n_l<8> a_dclk_p_l<7> a_dclk_p_l<8> A_DOUT<8> A_DIN<8> a_rclk_n_l<7> a_rclk_n_l<8> a_rclk_p_l<7> a_rclk_p_l<8> a_tieh<8> a_wclk_n_l<7> a_wclk_n_l<8> a_wclk_p_l<7> a_wclk_p_l<8> b_addr_dec_l<3> b_addr_dec_l<2> b_addr_dec_l<1> b_addr_dec_l<0> B_BIST_BM<8> B_BIST_DIN<8> B_BIST_EN b_blc_l<31> b_blc_l<30> b_blc_l<29> b_blc_l<28> b_blt_l<31> b_blt_l<30> b_blt_l<29> b_blt_l<28> B_BM<8> b_dclk_n_l<7> b_dclk_n_l<8> b_dclk_p_l<7> b_dclk_p_l<8> B_DOUT<8> B_DIN<8> b_rclk_n_l<7> b_rclk_n_l<8> b_rclk_p_l<7> b_rclk_p_l<8> b_tieh<8> b_wclk_n_l<7> b_wclk_n_l<8> b_wclk_p_l<7> b_wclk_p_l<8> VDD! VSS! / RM_IHPSG13_256x32_c2_2P_COLCTRL2 +XCOLCTRL<6> a_addr_dec_l<3> a_addr_dec_l<2> a_addr_dec_l<1> a_addr_dec_l<0> A_BIST_BM<9> A_BIST_DIN<9> A_BIST_EN a_blc_l<27> a_blc_l<26> a_blc_l<25> a_blc_l<24> a_blt_l<27> a_blt_l<26> a_blt_l<25> a_blt_l<24> A_BM<9> a_dclk_n_l<6> a_dclk_n_l<7> a_dclk_p_l<6> a_dclk_p_l<7> A_DOUT<9> A_DIN<9> a_rclk_n_l<6> a_rclk_n_l<7> a_rclk_p_l<6> a_rclk_p_l<7> a_tieh<9> a_wclk_n_l<6> a_wclk_n_l<7> a_wclk_p_l<6> a_wclk_p_l<7> b_addr_dec_l<3> b_addr_dec_l<2> b_addr_dec_l<1> b_addr_dec_l<0> B_BIST_BM<9> B_BIST_DIN<9> B_BIST_EN b_blc_l<27> b_blc_l<26> b_blc_l<25> b_blc_l<24> b_blt_l<27> b_blt_l<26> b_blt_l<25> b_blt_l<24> B_BM<9> b_dclk_n_l<6> b_dclk_n_l<7> b_dclk_p_l<6> b_dclk_p_l<7> B_DOUT<9> B_DIN<9> b_rclk_n_l<6> b_rclk_n_l<7> b_rclk_p_l<6> b_rclk_p_l<7> b_tieh<9> b_wclk_n_l<6> b_wclk_n_l<7> b_wclk_p_l<6> b_wclk_p_l<7> VDD! VSS! / RM_IHPSG13_256x32_c2_2P_COLCTRL2 +XCOLCTRL<5> a_addr_dec_l<3> a_addr_dec_l<2> a_addr_dec_l<1> a_addr_dec_l<0> A_BIST_BM<10> A_BIST_DIN<10> A_BIST_EN a_blc_l<23> a_blc_l<22> a_blc_l<21> a_blc_l<20> a_blt_l<23> a_blt_l<22> a_blt_l<21> a_blt_l<20> A_BM<10> a_dclk_n_l<5> a_dclk_n_l<6> a_dclk_p_l<5> a_dclk_p_l<6> A_DOUT<10> A_DIN<10> a_rclk_n_l<5> a_rclk_n_l<6> a_rclk_p_l<5> a_rclk_p_l<6> a_tieh<10> a_wclk_n_l<5> a_wclk_n_l<6> a_wclk_p_l<5> a_wclk_p_l<6> b_addr_dec_l<3> b_addr_dec_l<2> b_addr_dec_l<1> b_addr_dec_l<0> B_BIST_BM<10> B_BIST_DIN<10> B_BIST_EN b_blc_l<23> b_blc_l<22> b_blc_l<21> b_blc_l<20> b_blt_l<23> b_blt_l<22> b_blt_l<21> b_blt_l<20> B_BM<10> b_dclk_n_l<5> b_dclk_n_l<6> b_dclk_p_l<5> b_dclk_p_l<6> B_DOUT<10> B_DIN<10> b_rclk_n_l<5> b_rclk_n_l<6> b_rclk_p_l<5> b_rclk_p_l<6> b_tieh<10> b_wclk_n_l<5> b_wclk_n_l<6> b_wclk_p_l<5> b_wclk_p_l<6> VDD! VSS! / RM_IHPSG13_256x32_c2_2P_COLCTRL2 +XCOLCTRL<4> a_addr_dec_l<3> a_addr_dec_l<2> a_addr_dec_l<1> a_addr_dec_l<0> A_BIST_BM<11> A_BIST_DIN<11> A_BIST_EN a_blc_l<19> a_blc_l<18> a_blc_l<17> a_blc_l<16> a_blt_l<19> a_blt_l<18> a_blt_l<17> a_blt_l<16> A_BM<11> a_dclk_n_l<4> a_dclk_n_l<5> a_dclk_p_l<4> a_dclk_p_l<5> A_DOUT<11> A_DIN<11> a_rclk_n_l<4> a_rclk_n_l<5> a_rclk_p_l<4> a_rclk_p_l<5> a_tieh<11> a_wclk_n_l<4> a_wclk_n_l<5> a_wclk_p_l<4> a_wclk_p_l<5> b_addr_dec_l<3> b_addr_dec_l<2> b_addr_dec_l<1> b_addr_dec_l<0> B_BIST_BM<11> B_BIST_DIN<11> B_BIST_EN b_blc_l<19> b_blc_l<18> b_blc_l<17> b_blc_l<16> b_blt_l<19> b_blt_l<18> b_blt_l<17> b_blt_l<16> B_BM<11> b_dclk_n_l<4> b_dclk_n_l<5> b_dclk_p_l<4> b_dclk_p_l<5> B_DOUT<11> B_DIN<11> b_rclk_n_l<4> b_rclk_n_l<5> b_rclk_p_l<4> b_rclk_p_l<5> b_tieh<11> b_wclk_n_l<4> b_wclk_n_l<5> b_wclk_p_l<4> b_wclk_p_l<5> VDD! VSS! / RM_IHPSG13_256x32_c2_2P_COLCTRL2 +XCOLCTRL<3> a_addr_dec_l<3> a_addr_dec_l<2> a_addr_dec_l<1> a_addr_dec_l<0> A_BIST_BM<12> A_BIST_DIN<12> A_BIST_EN a_blc_l<15> a_blc_l<14> a_blc_l<13> a_blc_l<12> a_blt_l<15> a_blt_l<14> a_blt_l<13> a_blt_l<12> A_BM<12> a_dclk_n_l<3> a_dclk_n_l<4> a_dclk_p_l<3> a_dclk_p_l<4> A_DOUT<12> A_DIN<12> a_rclk_n_l<3> a_rclk_n_l<4> a_rclk_p_l<3> a_rclk_p_l<4> a_tieh<12> a_wclk_n_l<3> a_wclk_n_l<4> a_wclk_p_l<3> a_wclk_p_l<4> b_addr_dec_l<3> b_addr_dec_l<2> b_addr_dec_l<1> b_addr_dec_l<0> B_BIST_BM<12> B_BIST_DIN<12> B_BIST_EN b_blc_l<15> b_blc_l<14> b_blc_l<13> b_blc_l<12> b_blt_l<15> b_blt_l<14> b_blt_l<13> b_blt_l<12> B_BM<12> b_dclk_n_l<3> b_dclk_n_l<4> b_dclk_p_l<3> b_dclk_p_l<4> B_DOUT<12> B_DIN<12> b_rclk_n_l<3> b_rclk_n_l<4> b_rclk_p_l<3> b_rclk_p_l<4> b_tieh<12> b_wclk_n_l<3> b_wclk_n_l<4> b_wclk_p_l<3> b_wclk_p_l<4> VDD! VSS! / RM_IHPSG13_256x32_c2_2P_COLCTRL2 +XCOLCTRL<2> a_addr_dec_l<3> a_addr_dec_l<2> a_addr_dec_l<1> a_addr_dec_l<0> A_BIST_BM<13> A_BIST_DIN<13> A_BIST_EN a_blc_l<11> a_blc_l<10> a_blc_l<9> a_blc_l<8> a_blt_l<11> a_blt_l<10> a_blt_l<9> a_blt_l<8> A_BM<13> a_dclk_n_l<2> a_dclk_n_l<3> a_dclk_p_l<2> a_dclk_p_l<3> A_DOUT<13> A_DIN<13> a_rclk_n_l<2> a_rclk_n_l<3> a_rclk_p_l<2> a_rclk_p_l<3> a_tieh<13> a_wclk_n_l<2> a_wclk_n_l<3> a_wclk_p_l<2> a_wclk_p_l<3> b_addr_dec_l<3> b_addr_dec_l<2> b_addr_dec_l<1> b_addr_dec_l<0> B_BIST_BM<13> B_BIST_DIN<13> B_BIST_EN b_blc_l<11> b_blc_l<10> b_blc_l<9> b_blc_l<8> b_blt_l<11> b_blt_l<10> b_blt_l<9> b_blt_l<8> B_BM<13> b_dclk_n_l<2> b_dclk_n_l<3> b_dclk_p_l<2> b_dclk_p_l<3> B_DOUT<13> B_DIN<13> b_rclk_n_l<2> b_rclk_n_l<3> b_rclk_p_l<2> b_rclk_p_l<3> b_tieh<13> b_wclk_n_l<2> b_wclk_n_l<3> b_wclk_p_l<2> b_wclk_p_l<3> VDD! VSS! / RM_IHPSG13_256x32_c2_2P_COLCTRL2 +XCOLCTRL<1> a_addr_dec_l<3> a_addr_dec_l<2> a_addr_dec_l<1> a_addr_dec_l<0> A_BIST_BM<14> A_BIST_DIN<14> A_BIST_EN a_blc_l<7> a_blc_l<6> a_blc_l<5> a_blc_l<4> a_blt_l<7> a_blt_l<6> a_blt_l<5> a_blt_l<4> A_BM<14> a_dclk_n_l<1> a_dclk_n_l<2> a_dclk_p_l<1> a_dclk_p_l<2> A_DOUT<14> A_DIN<14> a_rclk_n_l<1> a_rclk_n_l<2> a_rclk_p_l<1> a_rclk_p_l<2> a_tieh<14> a_wclk_n_l<1> a_wclk_n_l<2> a_wclk_p_l<1> a_wclk_p_l<2> b_addr_dec_l<3> b_addr_dec_l<2> b_addr_dec_l<1> b_addr_dec_l<0> B_BIST_BM<14> B_BIST_DIN<14> B_BIST_EN b_blc_l<7> b_blc_l<6> b_blc_l<5> b_blc_l<4> b_blt_l<7> b_blt_l<6> b_blt_l<5> b_blt_l<4> B_BM<14> b_dclk_n_l<1> b_dclk_n_l<2> b_dclk_p_l<1> b_dclk_p_l<2> B_DOUT<14> B_DIN<14> b_rclk_n_l<1> b_rclk_n_l<2> b_rclk_p_l<1> b_rclk_p_l<2> b_tieh<14> b_wclk_n_l<1> b_wclk_n_l<2> b_wclk_p_l<1> b_wclk_p_l<2> VDD! VSS! / RM_IHPSG13_256x32_c2_2P_COLCTRL2 +XCOLCTRL<0> a_addr_dec_l<3> a_addr_dec_l<2> a_addr_dec_l<1> a_addr_dec_l<0> A_BIST_BM<15> A_BIST_DIN<15> A_BIST_EN a_blc_l<3> a_blc_l<2> a_blc_l<1> a_blc_l<0> a_blt_l<3> a_blt_l<2> a_blt_l<1> a_blt_l<0> A_BM<15> a_dclk_n_l<0> a_dclk_n_l<1> a_dclk_p_l<0> a_dclk_p_l<1> A_DOUT<15> A_DIN<15> a_rclk_n_l<0> a_rclk_n_l<1> a_rclk_p_l<0> a_rclk_p_l<1> a_tieh<15> a_wclk_n_l<0> a_wclk_n_l<1> a_wclk_p_l<0> a_wclk_p_l<1> b_addr_dec_l<3> b_addr_dec_l<2> b_addr_dec_l<1> b_addr_dec_l<0> B_BIST_BM<15> B_BIST_DIN<15> B_BIST_EN b_blc_l<3> b_blc_l<2> b_blc_l<1> b_blc_l<0> b_blt_l<3> b_blt_l<2> b_blt_l<1> b_blt_l<0> B_BM<15> b_dclk_n_l<0> b_dclk_n_l<1> b_dclk_p_l<0> b_dclk_p_l<1> B_DOUT<15> B_DIN<15> b_rclk_n_l<0> b_rclk_n_l<1> b_rclk_p_l<0> b_rclk_p_l<1> b_tieh<15> b_wclk_n_l<0> b_wclk_n_l<1> b_wclk_p_l<0> b_wclk_p_l<1> VDD! VSS! / RM_IHPSG13_256x32_c2_2P_COLCTRL2 + + +XDRVFILL4<1> VDD! VSS! / RM_IHPSG13_256x32_c2_2P_COLDRV13_FILL4 +XDRVFILL4<2> VDD! VSS! / RM_IHPSG13_256x32_c2_2P_COLDRV13_FILL4 +XDRVFILL4<3> VDD! VSS! / RM_IHPSG13_256x32_c2_2P_COLDRV13_FILL4 +XDRVFILL4<4> VDD! VSS! / RM_IHPSG13_256x32_c2_2P_COLDRV13_FILL4 +XDRVFILL4<5> VDD! VSS! / RM_IHPSG13_256x32_c2_2P_COLDRV13_FILL4 +XDRVFILL4<6> VDD! VSS! / RM_IHPSG13_256x32_c2_2P_COLDRV13_FILL4 +XDRVFILL4<7> VDD! VSS! / RM_IHPSG13_256x32_c2_2P_COLDRV13_FILL4 +XDRVFILL4<8> VDD! VSS! / RM_IHPSG13_256x32_c2_2P_COLDRV13_FILL4 +XDRVFILL4<9> VDD! VSS! / RM_IHPSG13_256x32_c2_2P_COLDRV13_FILL4 +XDRVFILL4<10> VDD! VSS! / RM_IHPSG13_256x32_c2_2P_COLDRV13_FILL4 +XCOLFILL4<1> VDD! VSS! / RM_IHPSG13_256x32_c2_2P_COLDRV13_FILL4C2 +XCOLFILL4<2> VDD! VSS! / RM_IHPSG13_256x32_c2_2P_COLDRV13_FILL4C2 +XCOLFILL4<3> VDD! VSS! / RM_IHPSG13_256x32_c2_2P_COLDRV13_FILL4C2 +XCOLFILL4<4> VDD! VSS! / RM_IHPSG13_256x32_c2_2P_COLDRV13_FILL4C2 +XCOLFILL4<5> VDD! VSS! / RM_IHPSG13_256x32_c2_2P_COLDRV13_FILL4C2 +XCOLFILL4<6> VDD! VSS! / RM_IHPSG13_256x32_c2_2P_COLDRV13_FILL4C2 +XCOLFILL4<7> VDD! VSS! / RM_IHPSG13_256x32_c2_2P_COLDRV13_FILL4C2 +XCOLFILL4<8> VDD! VSS! / RM_IHPSG13_256x32_c2_2P_COLDRV13_FILL4C2 +XCOLFILL4<9> VDD! VSS! / RM_IHPSG13_256x32_c2_2P_COLDRV13_FILL4C2 +XCOLFILL4<10> VDD! VSS! / RM_IHPSG13_256x32_c2_2P_COLDRV13_FILL4C2 +XCOLFILL4<11> VDD! VSS! / RM_IHPSG13_256x32_c2_2P_COLDRV13_FILL4C2 +XCOLFILL4<12> VDD! VSS! / RM_IHPSG13_256x32_c2_2P_COLDRV13_FILL4C2 +XCOLFILL4<13> VDD! VSS! / RM_IHPSG13_256x32_c2_2P_COLDRV13_FILL4C2 +XCOLFILL4<14> VDD! VSS! / RM_IHPSG13_256x32_c2_2P_COLDRV13_FILL4C2 +XCOLFILL4<15> VDD! VSS! / RM_IHPSG13_256x32_c2_2P_COLDRV13_FILL4C2 +XCOLFILL4<16> VDD! VSS! / RM_IHPSG13_256x32_c2_2P_COLDRV13_FILL4C2 +XCOLFILL4<17> VDD! VSS! / RM_IHPSG13_256x32_c2_2P_COLDRV13_FILL4C2 +XCOLFILL4<18> VDD! VSS! / RM_IHPSG13_256x32_c2_2P_COLDRV13_FILL4C2 +XCOLFILL4<19> VDD! VSS! / RM_IHPSG13_256x32_c2_2P_COLDRV13_FILL4C2 +XCOLFILL4<20> VDD! VSS! / RM_IHPSG13_256x32_c2_2P_COLDRV13_FILL4C2 +XCOLFILL4<21> VDD! VSS! / RM_IHPSG13_256x32_c2_2P_COLDRV13_FILL4C2 +XCOLFILL4<22> VDD! VSS! / RM_IHPSG13_256x32_c2_2P_COLDRV13_FILL4C2 +XCOLFILL4<23> VDD! VSS! / RM_IHPSG13_256x32_c2_2P_COLDRV13_FILL4C2 +XCOLFILL4<24> VDD! VSS! / RM_IHPSG13_256x32_c2_2P_COLDRV13_FILL4C2 +.ENDS diff --git a/flow/platforms/ihp-sg13g2/cdl/RM_IHPSG13_2P_256x8_c2_bm_bist.cdl b/flow/platforms/ihp-sg13g2/cdl/RM_IHPSG13_2P_256x8_c2_bm_bist.cdl new file mode 100644 index 0000000000..85a7bafca7 --- /dev/null +++ b/flow/platforms/ihp-sg13g2/cdl/RM_IHPSG13_2P_256x8_c2_bm_bist.cdl @@ -0,0 +1,6362 @@ +* ------------------------------------------------------ +* +* Copyright 2025 IHP PDK Authors +* +* Licensed under the Apache License, Version 2.0 (the "License"); +* you may not use this file except in compliance with the License. +* You may obtain a copy of the License at +* +* https://www.apache.org/licenses/LICENSE-2.0 +* +* Unless required by applicable law or agreed to in writing, software +* distributed under the License is distributed on an "AS IS" BASIS, +* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +* See the License for the specific language governing permissions and +* limitations under the License. +* +* Generated on Wed Aug 27 13:36:37 2025 +* +* ------------------------------------------------------ + +.SUBCKT RM_IHPSG13_256x8_c2_1P_BITKIT_CORNER NW PW VDD VSS +.ENDS +.SUBCKT RM_IHPSG13_256x8_c2_1P_BITKIT_16x2_CORNER VDD_CORE VSS +XI16 VDD_CORE VSS VDD_CORE VSS / ++ RM_IHPSG13_256x8_c2_1P_BITKIT_CORNER +.ENDS +.SUBCKT RM_IHPSG13_256x8_c2_1P_BITKIT_EDGE_LR LWL NW PW VDD VSS +MN1 VSS LWL VSS VSS sg13_lv_nmos m=1 w=300.0n l=130.00n ng=1 nrd=0 nrs=0 +MN0 VSS net9 VSS VSS sg13_lv_nmos m=1 w=300.0n l=130.00n ng=1 nrd=0 nrs=0 +.ENDS +.SUBCKT RM_IHPSG13_256x8_c2_1P_BITKIT_16x2_EDGE_LR A_WL<15> A_WL<14> A_WL<13> A_WL<12> ++ A_WL<11> A_WL<10> A_WL<9> A_WL<8> A_WL<7> A_WL<6> A_WL<5> A_WL<4> A_WL<3> ++ A_WL<2> A_WL<1> A_WL<0> VDD_CORE VSS +XI0<15> A_WL<15> VDD_CORE VSS VDD_CORE VSS / ++ RM_IHPSG13_256x8_c2_1P_BITKIT_EDGE_LR +XI0<14> A_WL<14> VDD_CORE VSS VDD_CORE VSS / ++ RM_IHPSG13_256x8_c2_1P_BITKIT_EDGE_LR +XI0<13> A_WL<13> VDD_CORE VSS VDD_CORE VSS / ++ RM_IHPSG13_256x8_c2_1P_BITKIT_EDGE_LR +XI0<12> A_WL<12> VDD_CORE VSS VDD_CORE VSS / ++ RM_IHPSG13_256x8_c2_1P_BITKIT_EDGE_LR +XI0<11> A_WL<11> VDD_CORE VSS VDD_CORE VSS / ++ RM_IHPSG13_256x8_c2_1P_BITKIT_EDGE_LR +XI0<10> A_WL<10> VDD_CORE VSS VDD_CORE VSS / ++ RM_IHPSG13_256x8_c2_1P_BITKIT_EDGE_LR +XI0<9> A_WL<9> VDD_CORE VSS VDD_CORE VSS / ++ RM_IHPSG13_256x8_c2_1P_BITKIT_EDGE_LR +XI0<8> A_WL<8> VDD_CORE VSS VDD_CORE VSS / ++ RM_IHPSG13_256x8_c2_1P_BITKIT_EDGE_LR +XI0<7> A_WL<7> VDD_CORE VSS VDD_CORE VSS / ++ RM_IHPSG13_256x8_c2_1P_BITKIT_EDGE_LR +XI0<6> A_WL<6> VDD_CORE VSS VDD_CORE VSS / ++ RM_IHPSG13_256x8_c2_1P_BITKIT_EDGE_LR +XI0<5> A_WL<5> VDD_CORE VSS VDD_CORE VSS / ++ RM_IHPSG13_256x8_c2_1P_BITKIT_EDGE_LR +XI0<4> A_WL<4> VDD_CORE VSS VDD_CORE VSS / ++ RM_IHPSG13_256x8_c2_1P_BITKIT_EDGE_LR +XI0<3> A_WL<3> VDD_CORE VSS VDD_CORE VSS / ++ RM_IHPSG13_256x8_c2_1P_BITKIT_EDGE_LR +XI0<2> A_WL<2> VDD_CORE VSS VDD_CORE VSS / ++ RM_IHPSG13_256x8_c2_1P_BITKIT_EDGE_LR +XI0<1> A_WL<1> VDD_CORE VSS VDD_CORE VSS / ++ RM_IHPSG13_256x8_c2_1P_BITKIT_EDGE_LR +XI0<0> A_WL<0> VDD_CORE VSS VDD_CORE VSS / ++ RM_IHPSG13_256x8_c2_1P_BITKIT_EDGE_LR +.ENDS +.SUBCKT RM_IHPSG13_256x8_c2_1P_BITKIT_CELL BLC_BOT BLC_TOP BLT_BOT BLT_TOP LWL NW PW ++ RWL VDD VSS +MN0 NC NT VSS PW sg13_lv_nmos m=1 w=300.0n l=130.00n ng=1 nrd=0 nrs=0 +MN1 NT NC VSS PW sg13_lv_nmos m=1 w=300.0n l=130.00n ng=1 nrd=0 nrs=0 +MN3 NC RWL BLC_TOP PW sg13_lv_nmos m=1 w=300.0n l=130.00n ng=1 nrd=0 nrs=0 +MN2 BLT_BOT LWL NT PW sg13_lv_nmos m=1 w=300.0n l=130.00n ng=1 nrd=0 nrs=0 +MP1 NT NC VDD NW sg13_lv_pmos m=1 w=150.00n l=130.00n ng=1 nrd=0 nrs=0 +MP0 NC NT VDD NW sg13_lv_pmos m=1 w=150.00n l=130.00n ng=1 nrd=0 nrs=0 +R1 BLC_BOT BLC_TOP lvsres w=2.6e-07 l=6e-07 +R0 BLT_BOT BLT_TOP lvsres w=2.6e-07 l=6e-07 +R2 RWL LWL lvsres w=2.6e-07 l=6e-07 +.ENDS +.SUBCKT RM_IHPSG13_256x8_c2_1P_BITKIT_16x2_SRAM A_BLC_BOT<1> A_BLC_BOT<0> A_BLC_TOP<1> ++ A_BLC_TOP<0> A_BLT_BOT<1> A_BLT_BOT<0> A_BLT_TOP<1> A_BLT_TOP<0> A_LWL<15> ++ A_LWL<14> A_LWL<13> A_LWL<12> A_LWL<11> A_LWL<10> A_LWL<9> A_LWL<8> A_LWL<7> ++ A_LWL<6> A_LWL<5> A_LWL<4> A_LWL<3> A_LWL<2> A_LWL<1> A_LWL<0> A_RWL<15> ++ A_RWL<14> A_RWL<13> A_RWL<12> A_RWL<11> A_RWL<10> A_RWL<9> A_RWL<8> A_RWL<7> ++ A_RWL<6> A_RWL<5> A_RWL<4> A_RWL<3> A_RWL<2> A_RWL<1> A_RWL<0> VDD_CORE ++ VSS +XCELL<31> A_BLC_TOP<1> A_RBLC<15> A_BLT_TOP<1> A_RBLT<15> A_RWL<15> ++ VDD_CORE VSS A_XWL<15> VDD_CORE VSS / ++ RM_IHPSG13_256x8_c2_1P_BITKIT_CELL +XCELL<30> A_RBLC<14> A_RBLC<15> A_RBLT<14> A_RBLT<15> A_RWL<14> VDD_CORE ++ VSS A_XWL<14> VDD_CORE VSS / RM_IHPSG13_256x8_c2_1P_BITKIT_CELL +XCELL<29> A_RBLC<14> A_RBLC<13> A_RBLT<14> A_RBLT<13> A_RWL<13> VDD_CORE ++ VSS A_XWL<13> VDD_CORE VSS / RM_IHPSG13_256x8_c2_1P_BITKIT_CELL +XCELL<28> A_RBLC<12> A_RBLC<13> A_RBLT<12> A_RBLT<13> A_RWL<12> VDD_CORE ++ VSS A_XWL<12> VDD_CORE VSS / RM_IHPSG13_256x8_c2_1P_BITKIT_CELL +XCELL<27> A_RBLC<12> A_RBLC<11> A_RBLT<12> A_RBLT<11> A_RWL<11> VDD_CORE ++ VSS A_XWL<11> VDD_CORE VSS / RM_IHPSG13_256x8_c2_1P_BITKIT_CELL +XCELL<26> A_RBLC<10> A_RBLC<11> A_RBLT<10> A_RBLT<11> A_RWL<10> VDD_CORE ++ VSS A_XWL<10> VDD_CORE VSS / RM_IHPSG13_256x8_c2_1P_BITKIT_CELL +XCELL<25> A_RBLC<10> A_RBLC<9> A_RBLT<10> A_RBLT<9> A_RWL<9> VDD_CORE ++ VSS A_XWL<9> VDD_CORE VSS / RM_IHPSG13_256x8_c2_1P_BITKIT_CELL +XCELL<24> A_RBLC<8> A_RBLC<9> A_RBLT<8> A_RBLT<9> A_RWL<8> VDD_CORE ++ VSS A_XWL<8> VDD_CORE VSS / RM_IHPSG13_256x8_c2_1P_BITKIT_CELL +XCELL<23> A_RBLC<8> A_RBLC<7> A_RBLT<8> A_RBLT<7> A_RWL<7> VDD_CORE ++ VSS A_XWL<7> VDD_CORE VSS / RM_IHPSG13_256x8_c2_1P_BITKIT_CELL +XCELL<22> A_RBLC<6> A_RBLC<7> A_RBLT<6> A_RBLT<7> A_RWL<6> VDD_CORE ++ VSS A_XWL<6> VDD_CORE VSS / RM_IHPSG13_256x8_c2_1P_BITKIT_CELL +XCELL<21> A_RBLC<6> A_RBLC<5> A_RBLT<6> A_RBLT<5> A_RWL<5> VDD_CORE ++ VSS A_XWL<5> VDD_CORE VSS / RM_IHPSG13_256x8_c2_1P_BITKIT_CELL +XCELL<20> A_RBLC<4> A_RBLC<5> A_RBLT<4> A_RBLT<5> A_RWL<4> VDD_CORE ++ VSS A_XWL<4> VDD_CORE VSS / RM_IHPSG13_256x8_c2_1P_BITKIT_CELL +XCELL<19> A_RBLC<4> A_RBLC<3> A_RBLT<4> A_RBLT<3> A_RWL<3> VDD_CORE ++ VSS A_XWL<3> VDD_CORE VSS / RM_IHPSG13_256x8_c2_1P_BITKIT_CELL +XCELL<18> A_RBLC<2> A_RBLC<3> A_RBLT<2> A_RBLT<3> A_RWL<2> VDD_CORE ++ VSS A_XWL<2> VDD_CORE VSS / RM_IHPSG13_256x8_c2_1P_BITKIT_CELL +XCELL<17> A_RBLC<2> A_RBLC<1> A_RBLT<2> A_RBLT<1> A_RWL<1> VDD_CORE ++ VSS A_XWL<1> VDD_CORE VSS / RM_IHPSG13_256x8_c2_1P_BITKIT_CELL +XCELL<16> A_BLC_BOT<1> A_RBLC<1> A_BLT_BOT<1> A_RBLT<1> A_RWL<0> VDD_CORE ++ VSS A_XWL<0> VDD_CORE VSS / RM_IHPSG13_256x8_c2_1P_BITKIT_CELL +XCELL<15> A_BLC_TOP<0> A_LBLC<15> A_BLT_TOP<0> A_LBLT<15> A_LWL<15> ++ VDD_CORE VSS A_XWL<15> VDD_CORE VSS / ++ RM_IHPSG13_256x8_c2_1P_BITKIT_CELL +XCELL<14> A_LBLC<14> A_LBLC<15> A_LBLT<14> A_LBLT<15> A_LWL<14> VDD_CORE ++ VSS A_XWL<14> VDD_CORE VSS / RM_IHPSG13_256x8_c2_1P_BITKIT_CELL +XCELL<13> A_LBLC<14> A_LBLC<13> A_LBLT<14> A_LBLT<13> A_LWL<13> VDD_CORE ++ VSS A_XWL<13> VDD_CORE VSS / RM_IHPSG13_256x8_c2_1P_BITKIT_CELL +XCELL<12> A_LBLC<12> A_LBLC<13> A_LBLT<12> A_LBLT<13> A_LWL<12> VDD_CORE ++ VSS A_XWL<12> VDD_CORE VSS / RM_IHPSG13_256x8_c2_1P_BITKIT_CELL +XCELL<11> A_LBLC<12> A_LBLC<11> A_LBLT<12> A_LBLT<11> A_LWL<11> VDD_CORE ++ VSS A_XWL<11> VDD_CORE VSS / RM_IHPSG13_256x8_c2_1P_BITKIT_CELL +XCELL<10> A_LBLC<10> A_LBLC<11> A_LBLT<10> A_LBLT<11> A_LWL<10> VDD_CORE ++ VSS A_XWL<10> VDD_CORE VSS / RM_IHPSG13_256x8_c2_1P_BITKIT_CELL +XCELL<9> A_LBLC<10> A_LBLC<9> A_LBLT<10> A_LBLT<9> A_LWL<9> VDD_CORE ++ VSS A_XWL<9> VDD_CORE VSS / RM_IHPSG13_256x8_c2_1P_BITKIT_CELL +XCELL<8> A_LBLC<8> A_LBLC<9> A_LBLT<8> A_LBLT<9> A_LWL<8> VDD_CORE ++ VSS A_XWL<8> VDD_CORE VSS / RM_IHPSG13_256x8_c2_1P_BITKIT_CELL +XCELL<7> A_LBLC<8> A_LBLC<7> A_LBLT<8> A_LBLT<7> A_LWL<7> VDD_CORE ++ VSS A_XWL<7> VDD_CORE VSS / RM_IHPSG13_256x8_c2_1P_BITKIT_CELL +XCELL<6> A_LBLC<6> A_LBLC<7> A_LBLT<6> A_LBLT<7> A_LWL<6> VDD_CORE ++ VSS A_XWL<6> VDD_CORE VSS / RM_IHPSG13_256x8_c2_1P_BITKIT_CELL +XCELL<5> A_LBLC<6> A_LBLC<5> A_LBLT<6> A_LBLT<5> A_LWL<5> VDD_CORE ++ VSS A_XWL<5> VDD_CORE VSS / RM_IHPSG13_256x8_c2_1P_BITKIT_CELL +XCELL<4> A_LBLC<4> A_LBLC<5> A_LBLT<4> A_LBLT<5> A_LWL<4> VDD_CORE ++ VSS A_XWL<4> VDD_CORE VSS / RM_IHPSG13_256x8_c2_1P_BITKIT_CELL +XCELL<3> A_LBLC<4> A_LBLC<3> A_LBLT<4> A_LBLT<3> A_LWL<3> VDD_CORE ++ VSS A_XWL<3> VDD_CORE VSS / RM_IHPSG13_256x8_c2_1P_BITKIT_CELL +XCELL<2> A_LBLC<2> A_LBLC<3> A_LBLT<2> A_LBLT<3> A_LWL<2> VDD_CORE ++ VSS A_XWL<2> VDD_CORE VSS / RM_IHPSG13_256x8_c2_1P_BITKIT_CELL +XCELL<1> A_LBLC<2> A_LBLC<1> A_LBLT<2> A_LBLT<1> A_LWL<1> VDD_CORE ++ VSS A_XWL<1> VDD_CORE VSS / RM_IHPSG13_256x8_c2_1P_BITKIT_CELL +XCELL<0> A_BLC_BOT<0> A_LBLC<1> A_BLT_BOT<0> A_LBLT<1> A_LWL<0> VDD_CORE ++ VSS A_XWL<0> VDD_CORE VSS / RM_IHPSG13_256x8_c2_1P_BITKIT_CELL +.ENDS +.SUBCKT RM_IHPSG13_256x8_c2_1P_BITKIT_EDGE_TB BLC BLT NW PW VDD VSS +.ENDS +.SUBCKT RM_IHPSG13_256x8_c2_1P_BITKIT_16x2_EDGE_TB A_BLC<1> A_BLC<0> A_BLT<1> A_BLT<0> ++ VDD_CORE VSS +XEDGE<1> A_BLC<1> A_BLT<1> VDD_CORE VSS VDD_CORE VSS ++ / RM_IHPSG13_256x8_c2_1P_BITKIT_EDGE_TB +XEDGE<0> A_BLC<0> A_BLT<0> VDD_CORE VSS VDD_CORE VSS ++ / RM_IHPSG13_256x8_c2_1P_BITKIT_EDGE_TB +.ENDS + +.SUBCKT RSC_IHPSG13_CBUFX4 A Z VDD VSS +MN0 net9 A VSS VSS sg13_lv_nmos m=1 w=705.000n l=130.00n ng=1 nrd=0 ++ nrs=0 +MN1 Z net9 VSS VSS sg13_lv_nmos m=1 w=1.41u l=130.00n ng=2 nrd=0 nrs=0 +MP0 net9 A VDD VDD sg13_lv_pmos m=1 w=1.62u l=130.00n ng=1 nrd=0 nrs=0 +MP1 Z net9 VDD VDD sg13_lv_pmos m=1 w=3.24u l=130.00n ng=2 nrd=0 nrs=0 +.ENDS +.SUBCKT RM_IHPSG13_256x8_c2_1P_COLDRV13X4 ADDR_COL_I<1> ADDR_COL_I<0> ADDR_COL_O<1> ++ ADDR_COL_O<0> ADDR_DEC_I<7> ADDR_DEC_I<6> ADDR_DEC_I<5> ADDR_DEC_I<4> ++ ADDR_DEC_I<3> ADDR_DEC_I<2> ADDR_DEC_I<1> ADDR_DEC_I<0> ADDR_DEC_O<7> ++ ADDR_DEC_O<6> ADDR_DEC_O<5> ADDR_DEC_O<4> ADDR_DEC_O<3> ADDR_DEC_O<2> ++ ADDR_DEC_O<1> ADDR_DEC_O<0> DCLK_I DCLK_O RCLK_I RCLK_O WCLK_I WCLK_O ++ VDD VSS +XADDR_COL_DRV<1> ADDR_COL_I<1> ADDR_COL_O<1> VDD VSS / ++ RSC_IHPSG13_CBUFX4 +XADDR_COL_DRV<0> ADDR_COL_I<0> ADDR_COL_O<0> VDD VSS / ++ RSC_IHPSG13_CBUFX4 +XADDR_DEC_DRV<7> ADDR_DEC_I<7> ADDR_DEC_O<7> VDD VSS / ++ RSC_IHPSG13_CBUFX4 +XADDR_DEC_DRV<6> ADDR_DEC_I<6> ADDR_DEC_O<6> VDD VSS / ++ RSC_IHPSG13_CBUFX4 +XADDR_DEC_DRV<5> ADDR_DEC_I<5> ADDR_DEC_O<5> VDD VSS / ++ RSC_IHPSG13_CBUFX4 +XADDR_DEC_DRV<4> ADDR_DEC_I<4> ADDR_DEC_O<4> VDD VSS / ++ RSC_IHPSG13_CBUFX4 +XADDR_DEC_DRV<3> ADDR_DEC_I<3> ADDR_DEC_O<3> VDD VSS / ++ RSC_IHPSG13_CBUFX4 +XADDR_DEC_DRV<2> ADDR_DEC_I<2> ADDR_DEC_O<2> VDD VSS / ++ RSC_IHPSG13_CBUFX4 +XADDR_DEC_DRV<1> ADDR_DEC_I<1> ADDR_DEC_O<1> VDD VSS / ++ RSC_IHPSG13_CBUFX4 +XADDR_DEC_DRV<0> ADDR_DEC_I<0> ADDR_DEC_O<0> VDD VSS / ++ RSC_IHPSG13_CBUFX4 +XDCLK_DRV DCLK_I DCLK_O VDD VSS / RSC_IHPSG13_CBUFX4 +XRCLK_DRV RCLK_I RCLK_O VDD VSS / RSC_IHPSG13_CBUFX4 +XWCLK_DRV WCLK_I WCLK_O VDD VSS / RSC_IHPSG13_CBUFX4 +.ENDS +.SUBCKT RSC_IHPSG13_WLDRVX4 A Z VDD VSS +MN1 Z net6 VSS VSS sg13_lv_nmos m=1 w=705.000n l=130.00n ng=1 nrd=0 ++ nrs=0 +MN0 net6 A VSS VSS sg13_lv_nmos m=1 w=900.0n l=130.00n ng=1 nrd=0 nrs=0 +MP1 Z net6 VDD VDD sg13_lv_pmos m=1 w=3.24u l=130.00n ng=2 nrd=0 nrs=0 +MP0 net6 A VDD VDD sg13_lv_pmos m=1 w=900.0n l=130.00n ng=1 nrd=0 nrs=0 +.ENDS +.SUBCKT RM_IHPSG13_256x8_c2_1P_WLDRV16X4 A<15> A<14> A<13> A<12> A<11> A<10> A<9> A<8> ++ A<7> A<6> A<5> A<4> A<3> A<2> A<1> A<0> Z<15> Z<14> Z<13> Z<12> Z<11> Z<10> ++ Z<9> Z<8> Z<7> Z<6> Z<5> Z<4> Z<3> Z<2> Z<1> Z<0> VDD VSS +XBUF<15> A<15> Z<15> VDD VSS / RSC_IHPSG13_WLDRVX4 +XBUF<14> A<14> Z<14> VDD VSS / RSC_IHPSG13_WLDRVX4 +XBUF<13> A<13> Z<13> VDD VSS / RSC_IHPSG13_WLDRVX4 +XBUF<12> A<12> Z<12> VDD VSS / RSC_IHPSG13_WLDRVX4 +XBUF<11> A<11> Z<11> VDD VSS / RSC_IHPSG13_WLDRVX4 +XBUF<10> A<10> Z<10> VDD VSS / RSC_IHPSG13_WLDRVX4 +XBUF<9> A<9> Z<9> VDD VSS / RSC_IHPSG13_WLDRVX4 +XBUF<8> A<8> Z<8> VDD VSS / RSC_IHPSG13_WLDRVX4 +XBUF<7> A<7> Z<7> VDD VSS / RSC_IHPSG13_WLDRVX4 +XBUF<6> A<6> Z<6> VDD VSS / RSC_IHPSG13_WLDRVX4 +XBUF<5> A<5> Z<5> VDD VSS / RSC_IHPSG13_WLDRVX4 +XBUF<4> A<4> Z<4> VDD VSS / RSC_IHPSG13_WLDRVX4 +XBUF<3> A<3> Z<3> VDD VSS / RSC_IHPSG13_WLDRVX4 +XBUF<2> A<2> Z<2> VDD VSS / RSC_IHPSG13_WLDRVX4 +XBUF<1> A<1> Z<1> VDD VSS / RSC_IHPSG13_WLDRVX4 +XBUF<0> A<0> Z<0> VDD VSS / RSC_IHPSG13_WLDRVX4 +.ENDS +.SUBCKT RSC_IHPSG13_FILLCAP8 VDD VSS +MN0 vss_r vdd_r VSS VSS sg13_lv_nmos m=1 w=4.98u l=130.00n ng=6 nrd=0 ++ nrs=0 +MP0 vdd_r vss_r VDD VDD sg13_lv_pmos m=1 w=6.48u l=385.000n ng=4 nrd=0 ++ nrs=0 +.ENDS +.SUBCKT RSC_IHPSG13_LHPQX2 CP D Q VDD VSS +MN3 QIN CPN net14 VSS sg13_lv_nmos m=1 w=480.00n l=130.00n ng=1 nrd=0 nrs=0 +MN2 net14 net10 VSS VSS sg13_lv_nmos m=1 w=480.00n l=130.00n ng=1 ++ nrd=0 nrs=0 +MN5 net21 D VSS VSS sg13_lv_nmos m=1 w=870.00n l=130.00n ng=1 nrd=0 ++ nrs=0 +MN6 QIN CP net21 VSS sg13_lv_nmos m=1 w=870.00n l=130.00n ng=1 nrd=0 nrs=0 +MN1 net10 QIN VSS VSS sg13_lv_nmos m=1 w=480.00n l=130.00n ng=1 nrd=0 ++ nrs=0 +MN0 CPN CP VSS VSS sg13_lv_nmos m=1 w=480.00n l=130.00n ng=1 nrd=0 ++ nrs=0 +MN4 Q QIN VSS VSS sg13_lv_nmos m=1 w=980.00n l=130.00n ng=1 nrd=0 nrs=0 +MP2 QIN CP net16 VDD sg13_lv_pmos m=1 w=480.00n l=130.00n ng=1 nrd=0 nrs=0 +MP0 CPN CP VDD VDD sg13_lv_pmos m=1 w=480.00n l=130.00n ng=1 nrd=0 ++ nrs=0 +MP4 Q QIN VDD VDD sg13_lv_pmos m=1 w=1.62u l=130.00n ng=1 nrd=0 nrs=0 +MP3 net10 QIN VDD VDD sg13_lv_pmos m=1 w=480.00n l=130.00n ng=1 nrd=0 ++ nrs=0 +MP1 net16 net10 VDD VDD sg13_lv_pmos m=1 w=480.00n l=130.00n ng=1 ++ nrd=0 nrs=0 +MP6 QIN CPN net20 VDD sg13_lv_pmos m=1 w=975.000n l=130.00n ng=1 nrd=0 ++ nrs=0 +MP5 net20 D VDD VDD sg13_lv_pmos m=1 w=975.000n l=130.00n ng=1 nrd=0 ++ nrs=0 +.ENDS +.SUBCKT RSC_IHPSG13_NAND2X2 A B Z VDD VSS +MP1 Z B VDD VDD sg13_lv_pmos m=1 w=1.62u l=130.00n ng=1 nrd=0 nrs=0 +MP0 Z A VDD VDD sg13_lv_pmos m=1 w=1.62u l=130.00n ng=1 nrd=0 nrs=0 +MN0 Z B net7 VSS sg13_lv_nmos m=1 w=980.00n l=130.00n ng=1 nrd=0 nrs=0 +MN1 net7 A VSS VSS sg13_lv_nmos m=1 w=980.00n l=130.00n ng=1 nrd=0 ++ nrs=0 +.ENDS +.SUBCKT RSC_IHPSG13_CINVX4 A Z VDD VSS +MN0 Z A VSS VSS sg13_lv_nmos m=1 w=1.41u l=130.00n ng=2 nrd=0 nrs=0 +MP0 Z A VDD VDD sg13_lv_pmos m=1 w=3.24u l=130.00n ng=2 nrd=0 nrs=0 +.ENDS +.SUBCKT RSC_IHPSG13_CINVX2 A Z VDD VSS +MN0 Z A VSS VSS sg13_lv_nmos m=1 w=705.000n l=130.00n ng=1 nrd=0 nrs=0 +MP0 Z A VDD VDD sg13_lv_pmos m=1 w=1.62u l=130.00n ng=1 nrd=0 nrs=0 +.ENDS +.SUBCKT RSC_IHPSG13_INVX2 A Z VDD VSS +MN0 Z A VSS VSS sg13_lv_nmos m=1 w=980.00n l=130.00n ng=1 nrd=0 nrs=0 +MP0 Z A VDD VDD sg13_lv_pmos m=1 w=1.62u l=130.00n ng=1 nrd=0 nrs=0 +.ENDS +.SUBCKT RSC_IHPSG13_NAND3X2 A B C Z VDD VSS +MP2 Z A VDD VDD sg13_lv_pmos m=1 w=1.62u l=130.00n ng=1 nrd=0 nrs=0 +MP1 Z B VDD VDD sg13_lv_pmos m=1 w=1.62u l=130.00n ng=1 nrd=0 nrs=0 +MP0 Z C VDD VDD sg13_lv_pmos m=1 w=1.62u l=130.00n ng=1 nrd=0 nrs=0 +MN1 net12 B net16 VSS sg13_lv_nmos m=1 w=980.00n l=130.00n ng=1 nrd=0 nrs=0 +MN0 Z C net12 VSS sg13_lv_nmos m=1 w=980.00n l=130.00n ng=1 nrd=0 nrs=0 +MN2 net16 A VSS VSS sg13_lv_nmos m=1 w=980.00n l=130.00n ng=1 nrd=0 ++ nrs=0 +.ENDS +.SUBCKT RSC_IHPSG13_NOR3X2 A B C Z VDD VSS +MP0 net13 A VDD VDD sg13_lv_pmos m=1 w=1.62u l=130.00n ng=1 nrd=0 nrs=0 +MP2 Z C net10 VDD sg13_lv_pmos m=1 w=1.62u l=130.00n ng=1 nrd=0 nrs=0 +MP1 net10 B net13 VDD sg13_lv_pmos m=1 w=1.62u l=130.00n ng=1 nrd=0 nrs=0 +MN1 Z B VSS VSS sg13_lv_nmos m=1 w=875.000n l=130.00n ng=1 nrd=0 nrs=0 +MN0 Z C VSS VSS sg13_lv_nmos m=1 w=875.000n l=130.00n ng=1 nrd=0 nrs=0 +MN2 Z A VSS VSS sg13_lv_nmos m=1 w=875.000n l=130.00n ng=1 nrd=0 nrs=0 +.ENDS +.SUBCKT RSC_IHPSG13_FILLCAP4 VDD VSS +MN0 vss_r vdd_r VSS VSS sg13_lv_nmos m=1 w=2.49u l=130.00n ng=3 nrd=0 ++ nrs=0 +MP0 vdd_r vss_r VDD VDD sg13_lv_pmos m=1 w=3.24u l=385.000n ng=2 nrd=0 ++ nrs=0 +.ENDS +.SUBCKT RSC_IHPSG13_MET2RES A B +R0 B A lvsres w=2.6e-07 l=6e-07 +.ENDS +.SUBCKT RM_IHPSG13_256x8_c2_1P_DEC04 ADDR<3> ADDR<2> ADDR<1> ADDR<0> CS ECLK_H_BOT ++ ECLK_H_TOP ECLK_L_BOT ECLK_L_TOP WL<15> WL<14> WL<13> WL<12> WL<11> WL<10> ++ WL<9> WL<8> WL<7> WL<6> WL<5> WL<4> WL<3> WL<2> WL<1> WL<0> VDD VSS +XLATCH<3> CS ADDR<3> PADR<3> VDD VSS / RSC_IHPSG13_LHPQX2 +XLATCH<2> CS ADDR<2> PADR<2> VDD VSS / RSC_IHPSG13_LHPQX2 +XLATCH<1> CS ADDR<1> PADR<1> VDD VSS / RSC_IHPSG13_LHPQX2 +XLATCH<0> CS ADDR<0> PADR<0> VDD VSS / RSC_IHPSG13_LHPQX2 +XI0<3> PADR<1> PADR<0> sel01<3> VDD VSS / RSC_IHPSG13_NAND2X2 +XI0<2> PADR<1> NADR<0> sel01<2> VDD VSS / RSC_IHPSG13_NAND2X2 +XI0<1> NADR<1> PADR<0> sel01<1> VDD VSS / RSC_IHPSG13_NAND2X2 +XI0<0> NADR<1> NADR<0> sel01<0> VDD VSS / RSC_IHPSG13_NAND2X2 +XI4 ECLK_L_BOT EN VDD VSS / RSC_IHPSG13_CINVX4 +XI5 ECLK_H_BOT ECLK_L_BOT VDD VSS / RSC_IHPSG13_CINVX2 +XI3<3> PADR<3> NADR<3> VDD VSS / RSC_IHPSG13_INVX2 +XI3<2> PADR<2> NADR<2> VDD VSS / RSC_IHPSG13_INVX2 +XI3<1> PADR<1> NADR<1> VDD VSS / RSC_IHPSG13_INVX2 +XI3<0> PADR<0> NADR<0> VDD VSS / RSC_IHPSG13_INVX2 +XI1<3> PADR<2> PADR<3> CS sel23<3> VDD VSS / RSC_IHPSG13_NAND3X2 +XI1<2> NADR<2> PADR<3> CS sel23<2> VDD VSS / RSC_IHPSG13_NAND3X2 +XI1<1> PADR<2> NADR<3> CS sel23<1> VDD VSS / RSC_IHPSG13_NAND3X2 +XI1<0> NADR<2> NADR<3> CS sel23<0> VDD VSS / RSC_IHPSG13_NAND3X2 +XI2<15> sel23<3> sel01<3> EN WL<15> VDD VSS / RSC_IHPSG13_NOR3X2 +XI2<14> sel23<3> sel01<2> EN WL<14> VDD VSS / RSC_IHPSG13_NOR3X2 +XI2<13> sel23<3> sel01<1> EN WL<13> VDD VSS / RSC_IHPSG13_NOR3X2 +XI2<12> sel23<3> sel01<0> EN WL<12> VDD VSS / RSC_IHPSG13_NOR3X2 +XI2<11> sel23<2> sel01<3> EN WL<11> VDD VSS / RSC_IHPSG13_NOR3X2 +XI2<10> sel23<2> sel01<2> EN WL<10> VDD VSS / RSC_IHPSG13_NOR3X2 +XI2<9> sel23<2> sel01<1> EN WL<9> VDD VSS / RSC_IHPSG13_NOR3X2 +XI2<8> sel23<2> sel01<0> EN WL<8> VDD VSS / RSC_IHPSG13_NOR3X2 +XI2<7> sel23<1> sel01<3> EN WL<7> VDD VSS / RSC_IHPSG13_NOR3X2 +XI2<6> sel23<1> sel01<2> EN WL<6> VDD VSS / RSC_IHPSG13_NOR3X2 +XI2<5> sel23<1> sel01<1> EN WL<5> VDD VSS / RSC_IHPSG13_NOR3X2 +XI2<4> sel23<1> sel01<0> EN WL<4> VDD VSS / RSC_IHPSG13_NOR3X2 +XI2<3> sel23<0> sel01<3> EN WL<3> VDD VSS / RSC_IHPSG13_NOR3X2 +XI2<2> sel23<0> sel01<2> EN WL<2> VDD VSS / RSC_IHPSG13_NOR3X2 +XI2<1> sel23<0> sel01<1> EN WL<1> VDD VSS / RSC_IHPSG13_NOR3X2 +XI2<0> sel23<0> sel01<0> EN WL<0> VDD VSS / RSC_IHPSG13_NOR3X2 +XCAPS4 VDD VSS / RSC_IHPSG13_FILLCAP4 +XI11 ECLK_L_BOT ECLK_L_TOP / RSC_IHPSG13_MET2RES +XR0 ECLK_H_BOT ECLK_H_TOP / RSC_IHPSG13_MET2RES +.ENDS +.SUBCKT RM_IHPSG13_256x8_c2_1P_ROWDEC4 ADDR_N_I<3> ADDR_N_I<2> ADDR_N_I<1> ADDR_N_I<0> ++ CS_I ECLK_I WL_O<15> WL_O<14> WL_O<13> WL_O<12> WL_O<11> WL_O<10> WL_O<9> ++ WL_O<8> WL_O<7> WL_O<6> WL_O<5> WL_O<4> WL_O<3> WL_O<2> WL_O<1> WL_O<0> ++ VDD VSS +XL2<8> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<7> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<6> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<5> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<4> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<3> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<2> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<1> VDD VSS / RSC_IHPSG13_FILLCAP8 +XSEL ADDR_N_I<3> ADDR_N_I<2> ADDR_N_I<1> ADDR_N_I<0> CS_I ECLK_I ECLK_H<1> ++ ECLK_B<0> ECLK_B<1> WL_O<15> WL_O<14> WL_O<13> WL_O<12> WL_O<11> WL_O<10> ++ WL_O<9> WL_O<8> WL_O<7> WL_O<6> WL_O<5> WL_O<4> WL_O<3> WL_O<2> WL_O<1> ++ WL_O<0> VDD VSS / RM_IHPSG13_256x8_c2_1P_DEC04 +.ENDS +.SUBCKT RSC_IHPSG13_CINVX8 A Z VDD VSS +MN0 Z A VSS VSS sg13_lv_nmos m=1 w=2.82u l=130.00n ng=4 nrd=0 nrs=0 +MP0 Z A VDD VDD sg13_lv_pmos m=1 w=6.48u l=130.00n ng=4 nrd=0 nrs=0 +.ENDS +.SUBCKT RSC_IHPSG13_DFNQMX2IX1 BE BI CN D QI QIN VDD VSS +MN15 net026 BI VSS VSS sg13_lv_nmos m=1 w=560.00n l=130.00n ng=1 nrd=0 ++ nrs=0 +MN14 MXI_OUT BE net026 VSS sg13_lv_nmos m=1 w=560.00n l=130.00n ng=1 nrd=0 ++ nrs=0 +MN1 net025 D VSS VSS sg13_lv_nmos m=1 w=560.00n l=130.00n ng=1 nrd=0 ++ nrs=0 +MN0 MXI_OUT BEN net025 VSS sg13_lv_nmos m=1 w=560.00n l=130.00n ng=1 nrd=0 ++ nrs=0 +MN10 QI CNN net21 VSS sg13_lv_nmos m=1 w=850.00n l=130.00n ng=1 nrd=0 nrs=0 +MN11 net21 QI_MS VSS VSS sg13_lv_nmos m=1 w=850.00n l=130.00n ng=1 ++ nrd=0 nrs=0 +MN7 net30 QI_MS VSS VSS sg13_lv_nmos m=1 w=480.00n l=130.00n ng=1 ++ nrd=0 nrs=0 +MN6 QIN_MS CNN net30 VSS sg13_lv_nmos m=1 w=480.00n l=130.00n ng=1 nrd=0 ++ nrs=0 +MN3 QI_MS QIN_MS VSS VSS sg13_lv_nmos m=1 w=480.00n l=130.00n ng=1 ++ nrd=0 nrs=0 +MN12 CNN CN VSS VSS sg13_lv_nmos m=1 w=495.000n l=130.00n ng=1 nrd=0 ++ nrs=0 +MN9 net37 MXI_OUT VSS VSS sg13_lv_nmos m=1 w=870.00n l=130.00n ng=1 ++ nrd=0 nrs=0 +MN8 QIN_MS CN net37 VSS sg13_lv_nmos m=1 w=870.00n l=130.00n ng=1 nrd=0 ++ nrs=0 +MN5 QI CN net25 VSS sg13_lv_nmos m=1 w=480.00n l=130.00n ng=1 nrd=0 nrs=0 +MN4 net25 QIN VSS VSS sg13_lv_nmos m=1 w=480.00n l=130.00n ng=1 nrd=0 ++ nrs=0 +MN2 QIN QI VSS VSS sg13_lv_nmos m=1 w=480.00n l=130.00n ng=1 nrd=0 ++ nrs=0 +MN13 BEN BE VSS VSS sg13_lv_nmos m=1 w=560.00n l=130.00n ng=1 nrd=0 ++ nrs=0 +MP15 MXI_OUT BEN net027 VDD sg13_lv_pmos m=1 w=985.000n l=130.00n ng=1 ++ nrd=0 nrs=0 +MP14 net027 BI VDD VDD sg13_lv_pmos m=1 w=985.000n l=130.00n ng=1 ++ nrd=0 nrs=0 +MP1 MXI_OUT BE net024 VDD sg13_lv_pmos m=1 w=985.000n l=130.00n ng=1 nrd=0 ++ nrs=0 +MP0 net024 D VDD VDD sg13_lv_pmos m=1 w=985.000n l=130.00n ng=1 nrd=0 ++ nrs=0 +MP13 BEN BE VDD VDD sg13_lv_pmos m=1 w=645.000n l=130.00n ng=1 nrd=0 ++ nrs=0 +MP6 QI_MS QIN_MS VDD VDD sg13_lv_pmos m=1 w=480.00n l=130.00n ng=1 ++ nrd=0 nrs=0 +MP3 QI CNN net27 VDD sg13_lv_pmos m=1 w=480.00n l=130.00n ng=1 nrd=0 nrs=0 +MP2 net27 QIN VDD VDD sg13_lv_pmos m=1 w=480.00n l=130.00n ng=1 nrd=0 ++ nrs=0 +MP10 net36 MXI_OUT VDD VDD sg13_lv_pmos m=1 w=975.000n l=130.00n ng=1 ++ nrd=0 nrs=0 +MP11 QIN_MS CNN net36 VDD sg13_lv_pmos m=1 w=975.000n l=130.00n ng=1 nrd=0 ++ nrs=0 +MP4 net32 QI_MS VDD VDD sg13_lv_pmos m=1 w=480.00n l=130.00n ng=1 ++ nrd=0 nrs=0 +MP5 QIN_MS CN net32 VDD sg13_lv_pmos m=1 w=480.00n l=130.00n ng=1 nrd=0 ++ nrs=0 +MP7 QIN QI VDD VDD sg13_lv_pmos m=1 w=480.00n l=130.00n ng=1 nrd=0 ++ nrs=0 +MP12 CNN CN VDD VDD sg13_lv_pmos m=1 w=480.00n l=130.00n ng=1 nrd=0 ++ nrs=0 +MP9 QI CN net19 VDD sg13_lv_pmos m=1 w=990.00n l=130.00n ng=1 nrd=0 nrs=0 +MP8 net19 QI_MS VDD VDD sg13_lv_pmos m=1 w=990.00n l=130.00n ng=1 ++ nrd=0 nrs=0 +.ENDS +.SUBCKT RM_IHPSG13_256x8_c2_1P_ROWREG4 ACLK_N_I ADDR_I<3> ADDR_I<2> ADDR_I<1> ADDR_I<0> ++ ADDR_N_O<3> ADDR_N_O<2> ADDR_N_O<1> ADDR_N_O<0> BIST_ADDR_I<3> ++ BIST_ADDR_I<2> BIST_ADDR_I<1> BIST_ADDR_I<0> BIST_EN_I VDD VSS +XINV<3> q_int<3> qn_int<3> VDD VSS / RSC_IHPSG13_CINVX2 +XINV<2> q_int<2> qn_int<2> VDD VSS / RSC_IHPSG13_CINVX2 +XINV<1> q_int<1> qn_int<1> VDD VSS / RSC_IHPSG13_CINVX2 +XINV<0> q_int<0> qn_int<0> VDD VSS / RSC_IHPSG13_CINVX2 +XDRV<3> qn_int<3> ADDR_N_O<3> VDD VSS / RSC_IHPSG13_CINVX8 +XDRV<2> qn_int<2> ADDR_N_O<2> VDD VSS / RSC_IHPSG13_CINVX8 +XDRV<1> qn_int<1> ADDR_N_O<1> VDD VSS / RSC_IHPSG13_CINVX8 +XDRV<0> qn_int<0> ADDR_N_O<0> VDD VSS / RSC_IHPSG13_CINVX8 +XDFF<3> BIST_EN_I BIST_ADDR_I<3> ACLK_N_I ADDR_I<3> q_int<3> net2<0> VDD ++ VSS / RSC_IHPSG13_DFNQMX2IX1 +XDFF<2> BIST_EN_I BIST_ADDR_I<2> ACLK_N_I ADDR_I<2> q_int<2> net2<1> VDD ++ VSS / RSC_IHPSG13_DFNQMX2IX1 +XDFF<1> BIST_EN_I BIST_ADDR_I<1> ACLK_N_I ADDR_I<1> q_int<1> net2<2> VDD ++ VSS / RSC_IHPSG13_DFNQMX2IX1 +XDFF<0> BIST_EN_I BIST_ADDR_I<0> ACLK_N_I ADDR_I<0> q_int<0> net2<3> VDD ++ VSS / RSC_IHPSG13_DFNQMX2IX1 +XI11<20> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI11<19> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI11<18> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI11<17> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI11<16> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI11<15> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI11<14> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI11<13> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI11<12> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI11<11> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI11<10> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI11<9> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI11<8> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI11<7> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI11<6> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI11<5> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI11<4> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI11<3> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI11<2> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI11<1> VDD VSS / RSC_IHPSG13_FILLCAP8 +.ENDS +.SUBCKT RSC_IHPSG13_CDLYX1 A Z VDD VSS +MN1 net010 net032 VSS VSS sg13_lv_nmos m=1 w=300.0n l=160.00n ng=1 ++ nrd=0 nrs=0 +MN2 net032 A net014 VSS sg13_lv_nmos m=1 w=300.0n l=160.00n ng=1 nrd=0 ++ nrs=0 +MN0 Z net032 net010 VSS sg13_lv_nmos m=1 w=300.0n l=160.00n ng=1 nrd=0 ++ nrs=0 +MN3 net014 A VSS VSS sg13_lv_nmos m=1 w=300.0n l=160.00n ng=1 nrd=0 ++ nrs=0 +MP1 Z net032 net07 VDD sg13_lv_pmos m=1 w=720.00n l=160.00n ng=1 nrd=0 ++ nrs=0 +MP3 net011 A VDD VDD sg13_lv_pmos m=1 w=720.00n l=160.00n ng=1 nrd=0 ++ nrs=0 +MP0 net07 net032 VDD VDD sg13_lv_pmos m=1 w=720.00n l=160.00n ng=1 ++ nrd=0 nrs=0 +MP2 net032 A net011 VDD sg13_lv_pmos m=1 w=720.00n l=160.00n ng=1 nrd=0 ++ nrs=0 +.ENDS +.SUBCKT RSC_IHPSG13_CDLYX1_DUMMY A Z VDD VSS +MN0 vss_r vdd_r VSS VSS sg13_lv_nmos m=1 w=2.49u l=300.0n ng=3 nrd=0 ++ nrs=0 +MP0 vdd_r vss_r VDD VDD sg13_lv_pmos m=1 w=3.24u l=640.00n ng=2 nrd=0 ++ nrs=0 +R0 Z A lvsres w=2.6e-07 l=6e-07 +.ENDS + +.SUBCKT RSC_IHPSG13_MX2IX1 A0 A1 S ZN VDD VSS +MP4 SN S VDD VDD sg13_lv_pmos m=1 w=645.000n l=130.00n ng=1 nrd=0 nrs=0 +MP3 ZN SN net12 VDD sg13_lv_pmos m=1 w=985.000n l=130.00n ng=1 nrd=0 nrs=0 +MP2 net12 A1 VDD VDD sg13_lv_pmos m=1 w=985.000n l=130.00n ng=1 nrd=0 ++ nrs=0 +MP1 ZN S net17 VDD sg13_lv_pmos m=1 w=985.000n l=130.00n ng=1 nrd=0 nrs=0 +MP0 net17 A0 VDD VDD sg13_lv_pmos m=1 w=985.000n l=130.00n ng=1 nrd=0 ++ nrs=0 +MN5 SN S VSS VSS sg13_lv_nmos m=1 w=480.00n l=130.00n ng=1 nrd=0 nrs=0 +MN3 net13 A1 VSS VSS sg13_lv_nmos m=1 w=480.00n l=130.00n ng=1 nrd=0 ++ nrs=0 +MN2 ZN S net13 VSS sg13_lv_nmos m=1 w=480.00n l=130.00n ng=1 nrd=0 nrs=0 +MN1 net15 A0 VSS VSS sg13_lv_nmos m=1 w=480.00n l=130.00n ng=1 nrd=0 ++ nrs=0 +MN0 ZN SN net15 VSS sg13_lv_nmos m=1 w=480.00n l=130.00n ng=1 nrd=0 nrs=0 +.ENDS +.SUBCKT RM_IHPSG13_256x8_c2_1P_DLY_MUX A SEL Z VDD VSS +XI11 net4 Z VDD VSS / RSC_IHPSG13_CINVX2 +XI8 A D<3> SEL net4 VDD VSS / RSC_IHPSG13_MX2IX1 +XI20<3> D<2> D<3> VDD VSS / RSC_IHPSG13_CDLYX1 +XI20<2> D<1> D<2> VDD VSS / RSC_IHPSG13_CDLYX1 +XI20<1> A D<1> VDD VSS / RSC_IHPSG13_CDLYX1 +.ENDS +.SUBCKT RSC_IHPSG13_DFNQX2 CN D Q VDD VSS +MN0 Q QIN_SL VSS VSS sg13_lv_nmos m=1 w=980.00n l=130.00n ng=1 nrd=0 ++ nrs=0 +MN10 QIN_SL CNN net21 VSS sg13_lv_nmos m=1 w=850.00n l=130.00n ng=1 nrd=0 ++ nrs=0 +MN11 net21 QI_MS VSS VSS sg13_lv_nmos m=1 w=850.00n l=130.00n ng=1 ++ nrd=0 nrs=0 +MN7 net30 QI_MS VSS VSS sg13_lv_nmos m=1 w=480.00n l=130.00n ng=1 ++ nrd=0 nrs=0 +MN6 QIN_MS CNN net30 VSS sg13_lv_nmos m=1 w=480.00n l=130.00n ng=1 nrd=0 ++ nrs=0 +MN3 QI_MS QIN_MS VSS VSS sg13_lv_nmos m=1 w=480.00n l=130.00n ng=1 ++ nrd=0 nrs=0 +MN12 CNN CN VSS VSS sg13_lv_nmos m=1 w=495.000n l=130.00n ng=1 nrd=0 ++ nrs=0 +MN9 net37 D VSS VSS sg13_lv_nmos m=1 w=870.00n l=130.00n ng=1 nrd=0 ++ nrs=0 +MN8 QIN_MS CN net37 VSS sg13_lv_nmos m=1 w=870.00n l=130.00n ng=1 nrd=0 ++ nrs=0 +MN5 QIN_SL CN net25 VSS sg13_lv_nmos m=1 w=480.00n l=130.00n ng=1 nrd=0 ++ nrs=0 +MN4 net25 QI_SL VSS VSS sg13_lv_nmos m=1 w=480.00n l=130.00n ng=1 ++ nrd=0 nrs=0 +MN2 QI_SL QIN_SL VSS VSS sg13_lv_nmos m=1 w=480.00n l=130.00n ng=1 ++ nrd=0 nrs=0 +MP0 Q QIN_SL VDD VDD sg13_lv_pmos m=1 w=1.62u l=130.00n ng=1 nrd=0 ++ nrs=0 +MP6 QI_MS QIN_MS VDD VDD sg13_lv_pmos m=1 w=480.00n l=130.00n ng=1 ++ nrd=0 nrs=0 +MP3 QIN_SL CNN net27 VDD sg13_lv_pmos m=1 w=480.00n l=130.00n ng=1 nrd=0 ++ nrs=0 +MP2 net27 QI_SL VDD VDD sg13_lv_pmos m=1 w=480.00n l=130.00n ng=1 ++ nrd=0 nrs=0 +MP10 net36 D VDD VDD sg13_lv_pmos m=1 w=975.000n l=130.00n ng=1 nrd=0 ++ nrs=0 +MP11 QIN_MS CNN net36 VDD sg13_lv_pmos m=1 w=975.000n l=130.00n ng=1 nrd=0 ++ nrs=0 +MP4 net32 QI_MS VDD VDD sg13_lv_pmos m=1 w=480.00n l=130.00n ng=1 ++ nrd=0 nrs=0 +MP5 QIN_MS CN net32 VDD sg13_lv_pmos m=1 w=480.00n l=130.00n ng=1 nrd=0 ++ nrs=0 +MP7 QI_SL QIN_SL VDD VDD sg13_lv_pmos m=1 w=480.00n l=130.00n ng=1 ++ nrd=0 nrs=0 +MP12 CNN CN VDD VDD sg13_lv_pmos m=1 w=480.00n l=130.00n ng=1 nrd=0 ++ nrs=0 +MP9 QIN_SL CN net19 VDD sg13_lv_pmos m=1 w=990.00n l=130.00n ng=1 nrd=0 ++ nrs=0 +MP8 net19 QI_MS VDD VDD sg13_lv_pmos m=1 w=990.00n l=130.00n ng=1 ++ nrd=0 nrs=0 +.ENDS +.SUBCKT RSC_IHPSG13_CNAND2X2 A B Z VDD VSS +MN0 Z B net6 VSS sg13_lv_nmos m=1 w=980.00n l=130.00n ng=1 nrd=0 nrs=0 +MN1 net6 A VSS VSS sg13_lv_nmos m=1 w=980.00n l=130.00n ng=1 nrd=0 ++ nrs=0 +MP1 Z B VDD VDD sg13_lv_pmos m=1 w=1.62u l=130.00n ng=1 nrd=0 nrs=0 +MP0 Z A VDD VDD sg13_lv_pmos m=1 w=1.62u l=130.00n ng=1 nrd=0 nrs=0 +.ENDS +.SUBCKT RSC_IHPSG13_CGATEPX4 CP E Q VDD VSS +MN1 net08 QIN VSS VSS sg13_lv_nmos m=1 w=480.00n l=130.00n ng=1 nrd=0 ++ nrs=0 +MN2 net019 net08 VSS VSS sg13_lv_nmos m=1 w=480.00n l=130.00n ng=1 ++ nrd=0 nrs=0 +MN3 QIN CP net019 VSS sg13_lv_nmos m=1 w=480.00n l=130.00n ng=1 nrd=0 nrs=0 +MN6 Q net015 VSS VSS sg13_lv_nmos m=1 w=1.41u l=130.00n ng=2 nrd=0 ++ nrs=0 +MN5 net015 net08 net018 VSS sg13_lv_nmos m=1 w=980.00n l=130.00n ng=1 ++ nrd=0 nrs=0 +MN8 QIN CPN net023 VSS sg13_lv_nmos m=1 w=870.00n l=130.00n ng=1 nrd=0 ++ nrs=0 +MN7 net023 E VSS VSS sg13_lv_nmos m=1 w=870.00n l=130.00n ng=1 nrd=0 ++ nrs=0 +MN4 net018 CP VSS VSS sg13_lv_nmos m=1 w=980.00n l=130.00n ng=1 nrd=0 ++ nrs=0 +MN0 CPN CP VSS VSS sg13_lv_nmos m=1 w=500.0n l=130.00n ng=1 nrd=0 nrs=0 +MP3 net08 QIN VDD VDD sg13_lv_pmos m=1 w=480.00n l=130.00n ng=1 nrd=0 ++ nrs=0 +MP2 QIN CPN net017 VDD sg13_lv_pmos m=1 w=480.00n l=130.00n ng=1 nrd=0 ++ nrs=0 +MP1 net017 net08 VDD VDD sg13_lv_pmos m=1 w=480.00n l=130.00n ng=1 ++ nrd=0 nrs=0 +MP0 CPN CP VDD VDD sg13_lv_pmos m=1 w=500.0n l=130.00n ng=1 nrd=0 nrs=0 +MP8 QIN CP net024 VDD sg13_lv_pmos m=1 w=975.000n l=130.00n ng=1 nrd=0 ++ nrs=0 +MP7 net024 E VDD VDD sg13_lv_pmos m=1 w=975.000n l=130.00n ng=1 nrd=0 ++ nrs=0 +MP4 net015 CP VDD VDD sg13_lv_pmos m=1 w=1.27u l=130.00n ng=1 nrd=0 ++ nrs=0 +MP6 Q net015 VDD VDD sg13_lv_pmos m=1 w=3.24u l=130.00n ng=2 nrd=0 ++ nrs=0 +MP5 net015 net08 VDD VDD sg13_lv_pmos m=1 w=1.27u l=130.00n ng=1 nrd=0 ++ nrs=0 +.ENDS +.SUBCKT RSC_IHPSG13_CBUFX8 A Z VDD VSS +MP0 net4 A VDD VDD sg13_lv_pmos m=1 w=3.24u l=130.00n ng=2 nrd=0 nrs=0 +MP1 Z net4 VDD VDD sg13_lv_pmos m=1 w=6.48u l=130.00n ng=4 nrd=0 nrs=0 +MN1 Z net4 VSS VSS sg13_lv_nmos m=1 w=2.82u l=130.00n ng=4 nrd=0 nrs=0 +MN0 net4 A VSS VSS sg13_lv_nmos m=1 w=1.41u l=130.00n ng=2 nrd=0 nrs=0 +.ENDS +.SUBCKT RSC_IHPSG13_CDLYX2 A Z VDD VSS +MN2 net4 A net9 VSS sg13_lv_nmos m=1 w=320.00n l=200.0n ng=1 nrd=0 nrs=0 +MN0 Z net4 VSS VSS sg13_lv_nmos m=1 w=705.000n l=130.00n ng=1 nrd=0 ++ nrs=0 +MN1 net9 A VSS VSS sg13_lv_nmos m=1 w=320.00n l=200.0n ng=1 nrd=0 nrs=0 +MP2 net4 A net10 VDD sg13_lv_pmos m=1 w=1.2u l=200.0n ng=1 nrd=0 nrs=0 +MP1 net10 A VDD VDD sg13_lv_pmos m=1 w=1.2u l=200.0n ng=1 nrd=0 nrs=0 +MP0 Z net4 VDD VDD sg13_lv_pmos m=1 w=1.62u l=130.00n ng=1 nrd=0 nrs=0 +.ENDS +.SUBCKT RSC_IHPSG13_MX2X2 A0 A1 S Z VDD VSS +MP6 Z net010 VDD VDD sg13_lv_pmos m=1 w=1.62u l=130.00n ng=1 nrd=0 ++ nrs=0 +MP4 SN S VDD VDD sg13_lv_pmos m=1 w=645.000n l=130.00n ng=1 nrd=0 nrs=0 +MP3 net010 SN net12 VDD sg13_lv_pmos m=1 w=985.000n l=130.00n ng=1 nrd=0 ++ nrs=0 +MP2 net12 A1 VDD VDD sg13_lv_pmos m=1 w=985.000n l=130.00n ng=1 nrd=0 ++ nrs=0 +MP1 net010 S net17 VDD sg13_lv_pmos m=1 w=985.000n l=130.00n ng=1 nrd=0 ++ nrs=0 +MP0 net17 A0 VDD VDD sg13_lv_pmos m=1 w=985.000n l=130.00n ng=1 nrd=0 ++ nrs=0 +MN6 Z net010 VSS VSS sg13_lv_nmos m=1 w=705.000n l=130.00n ng=1 nrd=0 ++ nrs=0 +MN5 SN S VSS VSS sg13_lv_nmos m=1 w=560.00n l=130.00n ng=1 nrd=0 nrs=0 +MN3 net13 A1 VSS VSS sg13_lv_nmos m=1 w=560.00n l=130.00n ng=1 nrd=0 ++ nrs=0 +MN2 net010 S net13 VSS sg13_lv_nmos m=1 w=560.00n l=130.00n ng=1 nrd=0 ++ nrs=0 +MN1 net15 A0 VSS VSS sg13_lv_nmos m=1 w=560.00n l=130.00n ng=1 nrd=0 ++ nrs=0 +MN0 net010 SN net15 VSS sg13_lv_nmos m=1 w=560.00n l=130.00n ng=1 nrd=0 ++ nrs=0 +.ENDS +.SUBCKT RSC_IHPSG13_AND2X2 A B Z VDD VSS +MN3 Z net6 VSS VSS sg13_lv_nmos m=1 w=980.00n l=130.00n ng=1 nrd=0 ++ nrs=0 +MN4 net9 B VSS VSS sg13_lv_nmos m=1 w=500.0n l=130.00n ng=1 nrd=0 nrs=0 +MN6 net6 A net9 VSS sg13_lv_nmos m=1 w=500.0n l=130.00n ng=1 nrd=0 nrs=0 +MP2 Z net6 VDD VDD sg13_lv_pmos m=1 w=1.62u l=130.00n ng=1 nrd=0 nrs=0 +MP0 net6 B VDD VDD sg13_lv_pmos m=1 w=860.00n l=130.00n ng=1 nrd=0 ++ nrs=0 +MP1 net6 A VDD VDD sg13_lv_pmos m=1 w=860.00n l=130.00n ng=1 nrd=0 ++ nrs=0 +.ENDS +.SUBCKT RSC_IHPSG13_TIEL Z VDD VSS +MN0 Z net2 VSS VSS sg13_lv_nmos m=1 w=480.00n l=130.00n ng=1 nrd=0 ++ nrs=0 +MP0 net2 net2 VDD VDD sg13_lv_pmos m=1 w=480.00n l=130.00n ng=1 nrd=0 ++ nrs=0 +.ENDS +.SUBCKT RSC_IHPSG13_XOR2X2 A B Z VDD VSS +MP8 net012 B net7 VDD sg13_lv_pmos m=1 w=825.000n l=130.00n ng=1 nrd=0 ++ nrs=0 +MP7 net011 net3 net012 VDD sg13_lv_pmos m=1 w=825.000n l=130.00n ng=1 ++ nrd=0 nrs=0 +MP6 Z net012 VDD VDD sg13_lv_pmos m=1 w=1.535u l=130.00n ng=1 nrd=0 ++ nrs=0 +MP2 net7 A VDD VDD sg13_lv_pmos m=1 w=825.000n l=130.00n ng=1 nrd=0 ++ nrs=0 +MP4 net011 net7 VDD VDD sg13_lv_pmos m=1 w=825.000n l=130.00n ng=1 ++ nrd=0 nrs=0 +MP5 net3 B VDD VDD sg13_lv_pmos m=1 w=580.00n l=130.00n ng=1 nrd=0 ++ nrs=0 +MN7 net012 B net011 VSS sg13_lv_nmos m=1 w=555.000n l=130.00n ng=1 nrd=0 ++ nrs=0 +MN6 net7 net3 net012 VSS sg13_lv_nmos m=1 w=555.000n l=130.00n ng=1 nrd=0 ++ nrs=0 +MN5 Z net012 VSS VSS sg13_lv_nmos m=1 w=775.000n l=130.00n ng=1 nrd=0 ++ nrs=0 +MN2 net7 A VSS VSS sg13_lv_nmos m=1 w=555.000n l=130.00n ng=1 nrd=0 ++ nrs=0 +MN4 net3 B VSS VSS sg13_lv_nmos m=1 w=480.00n l=130.00n ng=1 nrd=0 ++ nrs=0 +MN3 net011 net7 VSS VSS sg13_lv_nmos m=1 w=555.000n l=130.00n ng=1 ++ nrd=0 nrs=0 +.ENDS +.SUBCKT RSC_IHPSG13_OA12X1 A B C Z VDD VSS +MN2 net7 C VSS VSS sg13_lv_nmos m=1 w=980.00n l=130.00n ng=1 nrd=0 ++ nrs=0 +MN3 Z net17 VSS VSS sg13_lv_nmos m=1 w=500.0n l=130.00n ng=1 nrd=0 ++ nrs=0 +MN1 net17 B net7 VSS sg13_lv_nmos m=1 w=980.00n l=130.00n ng=1 nrd=0 nrs=0 +MN0 net17 A net7 VSS sg13_lv_nmos m=1 w=980.00n l=130.00n ng=1 nrd=0 nrs=0 +MP0 net24 A VDD VDD sg13_lv_pmos m=1 w=1.62u l=130.00n ng=1 nrd=0 nrs=0 +MP3 Z net17 VDD VDD sg13_lv_pmos m=1 w=905.000n l=130.00n ng=1 nrd=0 ++ nrs=0 +MP1 net17 B net24 VDD sg13_lv_pmos m=1 w=1.62u l=130.00n ng=1 nrd=0 nrs=0 +MP2 net17 C VDD VDD sg13_lv_pmos m=1 w=905.000n l=130.00n ng=1 nrd=0 ++ nrs=0 +.ENDS +.SUBCKT RM_IHPSG13_256x8_c2_1P_CTRL ACLK_N BIST_CK_I BIST_CS_I BIST_EN BIST_RE_I ++ BIST_WE_I B_TIEL_O CK_I CS_I DCLK ECLK PULSE_H PULSE_L PULSE_O RCLK RE_I ++ ROW_CS WCLK WE_I VDD VSS +XI17 ck_regs we col_we VDD VSS / RSC_IHPSG13_DFNQX2 +XI16 ck_regs re col_re VDD VSS / RSC_IHPSG13_DFNQX2 +XI18 ck_regs cs net7 VDD VSS / RSC_IHPSG13_DFNQX2 +XI71 ACLK_N net012 PULSE_O VDD VSS / RSC_IHPSG13_DFNQX2 +XI77 col_we net9 net016 VDD VSS / RSC_IHPSG13_CNAND2X2 +XI76 col_re net9 net018 VDD VSS / RSC_IHPSG13_CNAND2X2 +XI15 ck_dly WEorREandCS aclk VDD VSS / RSC_IHPSG13_CGATEPX4 +XI14 ck WEandCS DCLK VDD VSS / RSC_IHPSG13_CGATEPX4 +XI60 net7 ROW_CS VDD VSS / RSC_IHPSG13_CBUFX8 +XI73 PULSE_O net012 VDD VSS / RSC_IHPSG13_CINVX2 +XI8 net9 net8 VDD VSS / RSC_IHPSG13_CINVX2 +XI64 ck ck_dly VDD VSS / RSC_IHPSG13_CDLYX2 +XI86 CS_I BIST_CS_I BIST_EN cs VDD VSS / RSC_IHPSG13_MX2X2 +XI87 CK_I BIST_CK_I BIST_EN ck VDD VSS / RSC_IHPSG13_MX2X2 +XI85 WE_I BIST_WE_I BIST_EN we VDD VSS / RSC_IHPSG13_MX2X2 +XI84 RE_I BIST_RE_I BIST_EN re VDD VSS / RSC_IHPSG13_MX2X2 +XI22 we cs WEandCS VDD VSS / RSC_IHPSG13_AND2X2 +XBM_TIEL B_TIEL_O VDD VSS / RSC_IHPSG13_TIEL +XI48 ck_dly ck_regs VDD VSS / RSC_IHPSG13_CINVX4 +XI81 net016 WCLK VDD VSS / RSC_IHPSG13_CINVX4 +XI80 net018 RCLK VDD VSS / RSC_IHPSG13_CINVX4 +XI78 net8 net020 VDD VSS / RSC_IHPSG13_CINVX4 +XI6 PULSE_L PULSE_H net9 VDD VSS / RSC_IHPSG13_XOR2X2 +XI79 net020 ECLK VDD VSS / RSC_IHPSG13_CINVX8 +XI63 aclk ACLK_N VDD VSS / RSC_IHPSG13_CINVX8 +XI21 re we cs WEorREandCS VDD VSS / RSC_IHPSG13_OA12X1 +.ENDS +.SUBCKT RM_IHPSG13_256x8_c2_1P_COLDEC2 ACLK_N ADDR<1> ADDR<0> ADDR_COL<1> ADDR_COL<0> ++ ADDR_DEC<7> ADDR_DEC<6> ADDR_DEC<5> ADDR_DEC<4> ADDR_DEC<3> ADDR_DEC<2> ++ ADDR_DEC<1> ADDR_DEC<0> BIST_ADDR<1> BIST_ADDR<0> BIST_EN_I VDD VSS +XI14<5> VDD VSS / RSC_IHPSG13_FILLCAP4 +XI14<4> VDD VSS / RSC_IHPSG13_FILLCAP4 +XI14<3> VDD VSS / RSC_IHPSG13_FILLCAP4 +XI14<2> VDD VSS / RSC_IHPSG13_FILLCAP4 +XI14<1> VDD VSS / RSC_IHPSG13_FILLCAP4 +XDFF<1> BIST_EN_I BIST_ADDR<1> ACLK_N ADDR<1> padr_int<1> net6<0> VDD ++ VSS / RSC_IHPSG13_DFNQMX2IX1 +XDFF<0> BIST_EN_I BIST_ADDR<0> ACLK_N ADDR<0> padr_int<0> net6<1> VDD ++ VSS / RSC_IHPSG13_DFNQMX2IX1 +XI1<3> PADR<1> PADR<0> addr_n<3> VDD VSS / RSC_IHPSG13_NAND2X2 +XI1<2> PADR<1> NADR<0> addr_n<2> VDD VSS / RSC_IHPSG13_NAND2X2 +XI1<1> NADR<1> PADR<0> addr_n<1> VDD VSS / RSC_IHPSG13_NAND2X2 +XI1<0> NADR<1> NADR<0> addr_n<0> VDD VSS / RSC_IHPSG13_NAND2X2 +XI16<37> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI16<36> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI16<35> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI16<34> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI16<33> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI16<32> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI16<31> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI16<30> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI16<29> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI16<28> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI16<27> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI16<26> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI16<25> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI16<24> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI16<23> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI16<22> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI16<21> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI16<20> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI16<19> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI16<18> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI16<17> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI16<16> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI16<15> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI16<14> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI16<13> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI16<12> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI16<11> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI16<10> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI16<9> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI16<8> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI16<7> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI16<6> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI16<5> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI16<4> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI16<3> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI16<2> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI16<1> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI3<1> padr_int<1> NADR<1> VDD VSS / RSC_IHPSG13_INVX2 +XI3<0> padr_int<0> NADR<0> VDD VSS / RSC_IHPSG13_INVX2 +XI13<1> NADR<1> PADR<1> VDD VSS / RSC_IHPSG13_INVX2 +XI13<0> NADR<0> PADR<0> VDD VSS / RSC_IHPSG13_INVX2 +XI2<3> addr_n<3> ADDR_DEC<3> VDD VSS / RSC_IHPSG13_INVX2 +XI2<2> addr_n<2> ADDR_DEC<2> VDD VSS / RSC_IHPSG13_INVX2 +XI2<1> addr_n<1> ADDR_DEC<1> VDD VSS / RSC_IHPSG13_INVX2 +XI2<0> addr_n<0> ADDR_DEC<0> VDD VSS / RSC_IHPSG13_INVX2 +XI15<1> ADDR_COL<1> VDD VSS / RSC_IHPSG13_TIEL +XI15<0> ADDR_COL<0> VDD VSS / RSC_IHPSG13_TIEL +XI17<3> ADDR_DEC<7> VDD VSS / RSC_IHPSG13_TIEL +XI17<2> ADDR_DEC<6> VDD VSS / RSC_IHPSG13_TIEL +XI17<1> ADDR_DEC<5> VDD VSS / RSC_IHPSG13_TIEL +XI17<0> ADDR_DEC<4> VDD VSS / RSC_IHPSG13_TIEL +.ENDS +.SUBCKT RSC_IHPSG13_NOR2X2 A B Z VDD VSS +MP1 Z B net9 VDD sg13_lv_pmos m=1 w=1.62u l=130.00n ng=1 nrd=0 nrs=0 +MP0 net9 A VDD VDD sg13_lv_pmos m=1 w=1.62u l=130.00n ng=1 nrd=0 nrs=0 +MN0 Z B VSS VSS sg13_lv_nmos m=1 w=980.00n l=130.00n ng=1 nrd=0 nrs=0 +MN1 Z A VSS VSS sg13_lv_nmos m=1 w=980.00n l=130.00n ng=1 nrd=0 nrs=0 +.ENDS +.SUBCKT RSC_IHPSG13_CINVX4_WN A Z VDD VSS +MN0 Z A VSS VSS sg13_lv_nmos m=1 w=705.000n l=130.00n ng=1 nrd=0 nrs=0 +MP0 Z A VDD VDD sg13_lv_pmos m=1 w=3.24u l=130.00n ng=2 nrd=0 nrs=0 +.ENDS +.SUBCKT RM_IHPSG13_256x8_c2_1P_BLDRV BLC BLC_SEL BLT BLT_SEL PRE_N SEL_P WR_ONE WR_ZERO ++ VDD VSS +XCDEC SEL_P WR_ZERO BLC_PMOS_DRIVE VDD VSS / RSC_IHPSG13_NAND2X2 +XTDEC SEL_P WR_ONE BLT_PMOS_DRIVE VDD VSS / RSC_IHPSG13_NAND2X2 +MTWN BLT BLT_NMOS_DRIVE VSS VSS sg13_lv_nmos m=1 w=4.82u l=130.00n ++ ng=2 nrd=0 nrs=0 +MCWN BLC BLC_NMOS_DRIVE VSS VSS sg13_lv_nmos m=1 w=4.82u l=130.00n ++ ng=2 nrd=0 nrs=0 +MCWP BLC BLC_PMOS_DRIVE VDD VDD sg13_lv_pmos m=1 w=1.5u l=130.00n ng=1 ++ nrd=0 nrs=0 +MTWP BLT BLT_PMOS_DRIVE VDD VDD sg13_lv_pmos m=1 w=1.5u l=130.00n ng=1 ++ nrd=0 nrs=0 +MTSP BLT_SEL SEL_N BLT VDD sg13_lv_pmos m=1 w=1.5u l=130.00n ng=1 nrd=0 ++ nrs=0 +MTPR BLT PRE_N VDD VDD sg13_lv_pmos m=1 w=3.000u l=130.00n ng=2 nrd=0 ++ nrs=0 +MCSP BLC_SEL SEL_N BLC VDD sg13_lv_pmos m=1 w=1.5u l=130.00n ng=1 nrd=0 ++ nrs=0 +MCPR BLC PRE_N VDD VDD sg13_lv_pmos m=1 w=3.000u l=130.00n ng=2 nrd=0 ++ nrs=0 +XI86 SEL_P SEL_N VDD VSS / RSC_IHPSG13_INVX2 +XTINV BLC_PMOS_DRIVE BLT_NMOS_DRIVE VDD VSS / RSC_IHPSG13_INVX2 +XCINV BLT_PMOS_DRIVE BLC_NMOS_DRIVE VDD VSS / RSC_IHPSG13_INVX2 +.ENDS +.SUBCKT RSC_IHPSG13_TIEH Z VDD VSS +MN0 net2 net2 VSS VSS sg13_lv_nmos m=1 w=480.00n l=130.00n ng=1 nrd=0 ++ nrs=0 +MP0 Z net2 VDD VDD sg13_lv_pmos m=1 w=480.00n l=130.00n ng=1 nrd=0 ++ nrs=0 +.ENDS +.SUBCKT RSC_IHPSG13_MET3RES A B +R0 B A lvsres w=2.6e-07 l=6e-07 +.ENDS +.SUBCKT RSC_IHPSG13_DFPQD_MSAFFX2 CP DN DP QN QP VDD VSS +MN12 SN RN DIFFP VSS sg13_lv_nmos m=1 w=2.4u l=200.0n ng=2 nrd=0 nrs=0 +MN13 TAIL CP VSS VSS sg13_lv_nmos m=1 w=2.4u l=130.00n ng=2 nrd=0 nrs=0 +MN9 DIFFP DP TAIL VSS sg13_lv_nmos m=1 w=2.4u l=200.0n ng=2 nrd=0 nrs=0 +MN10 DIFFN DN TAIL VSS sg13_lv_nmos m=1 w=2.4u l=200.0n ng=2 nrd=0 nrs=0 +MN11 RN SN DIFFN VSS sg13_lv_nmos m=1 w=2.4u l=200.0n ng=2 nrd=0 nrs=0 +MN19 net33 SN VSS VSS sg13_lv_nmos m=1 w=980.00n l=130.00n ng=1 nrd=0 ++ nrs=0 +MN20 QN QP net37 VSS sg13_lv_nmos m=1 w=980.00n l=130.00n ng=1 nrd=0 nrs=0 +MN18 net37 RN VSS VSS sg13_lv_nmos m=1 w=980.00n l=130.00n ng=1 nrd=0 ++ nrs=0 +MN17 QP QN net33 VSS sg13_lv_nmos m=1 w=980.00n l=130.00n ng=1 nrd=0 nrs=0 +MP15 SN RN VDD VDD sg13_lv_pmos m=1 w=800.0n l=130.00n ng=1 nrd=0 nrs=0 +MP16 RN CP VDD VDD sg13_lv_pmos m=1 w=800.0n l=130.00n ng=1 nrd=0 nrs=0 +MP14 DIFFP CP VDD VDD sg13_lv_pmos m=1 w=800.0n l=130.00n ng=1 nrd=0 ++ nrs=0 +MP12 RN SN VDD VDD sg13_lv_pmos m=1 w=800.0n l=130.00n ng=1 nrd=0 nrs=0 +MP13 DIFFN CP VDD VDD sg13_lv_pmos m=1 w=800.0n l=130.00n ng=1 nrd=0 ++ nrs=0 +MP11 SN CP VDD VDD sg13_lv_pmos m=1 w=800.0n l=130.00n ng=1 nrd=0 nrs=0 +MP19 QN QP VDD VDD sg13_lv_pmos m=1 w=900.0n l=130.00n ng=1 nrd=0 nrs=0 +MP20 QP SN VDD VDD sg13_lv_pmos m=1 w=1.8u l=130.00n ng=2 nrd=0 nrs=0 +MP18 QN RN VDD VDD sg13_lv_pmos m=1 w=1.8u l=130.00n ng=2 nrd=0 nrs=0 +MP17 QP QN VDD VDD sg13_lv_pmos m=1 w=900.0n l=130.00n ng=1 nrd=0 nrs=0 +.ENDS +.SUBCKT RSC_IHPSG13_CBUFX2 A Z VDD VSS +MN1 Z net4 VSS VSS sg13_lv_nmos m=1 w=705.000n l=130.00n ng=1 nrd=0 ++ nrs=0 +MN0 net4 A VSS VSS sg13_lv_nmos m=1 w=540.00n l=130.00n ng=1 nrd=0 ++ nrs=0 +MP1 Z net4 VDD VDD sg13_lv_pmos m=1 w=1.62u l=130.00n ng=1 nrd=0 nrs=0 +MP0 net4 A VDD VDD sg13_lv_pmos m=1 w=1.1u l=130.00n ng=1 nrd=0 nrs=0 +.ENDS +.SUBCKT RSC_IHPSG13_INVX4 A Z VDD VSS +MN0 Z A VSS VSS sg13_lv_nmos m=1 w=1.96u l=130.00n ng=2 nrd=0 nrs=0 +MP0 Z A VDD VDD sg13_lv_pmos m=1 w=3.24u l=130.00n ng=2 nrd=0 nrs=0 +.ENDS +.SUBCKT RM_IHPSG13_256x8_c2_1P_COLCTRL2 A_ADDR_DEC<3> A_ADDR_DEC<2> A_ADDR_DEC<1> ++ A_ADDR_DEC<0> A_BIST_BM_I A_BIST_DW_I A_BIST_EN_I A_BLC<3> A_BLC<2> A_BLC<1> ++ A_BLC<0> A_BLT<3> A_BLT<2> A_BLT<1> A_BLT<0> A_BM_I A_DCLK_B_L A_DCLK_B_R ++ A_DCLK_L A_DCLK_R A_DR_O A_DW_I A_RCLK_B_L A_RCLK_B_R A_RCLK_L A_RCLK_R ++ A_TIEH_O A_WCLK_B_L A_WCLK_B_R A_WCLK_L A_WCLK_R VDD VSS +XA_DREG A_BIST_EN_I A_BIST_DW_I A_DCLK_B_L A_DW_I A_DI_R net22 VDD VSS ++ / RSC_IHPSG13_DFNQMX2IX1 +XA_BREG A_BIST_EN_I A_BIST_BM_I A_DCLK_B_L A_BM_I A_BM_R net23 VDD VSS ++ / RSC_IHPSG13_DFNQMX2IX1 +XA_CAPS<5> VDD VSS / RSC_IHPSG13_FILLCAP4 +XA_CAPS<4> VDD VSS / RSC_IHPSG13_FILLCAP4 +XA_CAPS<3> VDD VSS / RSC_IHPSG13_FILLCAP4 +XA_CAPS<2> VDD VSS / RSC_IHPSG13_FILLCAP4 +XA_CAPS<1> VDD VSS / RSC_IHPSG13_FILLCAP4 +XA_I80 A_WCLK_B_R A_RCLK_B_R net21 VDD VSS / RSC_IHPSG13_AND2X2 +XA_I75 A_DI_R A_DO_WRITE_P A_WR_ONE VDD VSS / RSC_IHPSG13_AND2X2 +XA_I76 A_DI_N A_DO_WRITE_P A_WR_ZERO VDD VSS / RSC_IHPSG13_AND2X2 +XA_I44 A_WCLK_B_R A_BM_N A_DO_WRITE_P VDD VSS / RSC_IHPSG13_NOR2X2 +XA_I81 net21 A_PRE_N VDD VSS / RSC_IHPSG13_CINVX4_WN +XA_BLTMUX<3> A_BLC<3> A_BLC_SEL A_BLT<3> A_BLT_SEL A_PRE_N A_ADDR_DEC<3> ++ A_WR_ONE A_WR_ZERO VDD VSS / RM_IHPSG13_256x8_c2_1P_BLDRV +XA_BLTMUX<2> A_BLC<2> A_BLC_SEL A_BLT<2> A_BLT_SEL A_PRE_N A_ADDR_DEC<2> ++ A_WR_ONE A_WR_ZERO VDD VSS / RM_IHPSG13_256x8_c2_1P_BLDRV +XA_BLTMUX<1> A_BLC<1> A_BLC_SEL A_BLT<1> A_BLT_SEL A_PRE_N A_ADDR_DEC<1> ++ A_WR_ONE A_WR_ZERO VDD VSS / RM_IHPSG13_256x8_c2_1P_BLDRV +XA_BLTMUX<0> A_BLC<0> A_BLC_SEL A_BLT<0> A_BLT_SEL A_PRE_N A_ADDR_DEC<0> ++ A_WR_ONE A_WR_ZERO VDD VSS / RM_IHPSG13_256x8_c2_1P_BLDRV +XA_BM_TIEH A_TIEH_O VDD VSS / RSC_IHPSG13_TIEH +XA_I89 A_DCLK_B_L A_DCLK_B_R / RSC_IHPSG13_MET3RES +XA_I88 A_DCLK_L A_DCLK_R / RSC_IHPSG13_MET3RES +XA_I87 A_WCLK_L A_WCLK_R / RSC_IHPSG13_MET3RES +XA_I91 A_RCLK_B_R A_RCLK_B_L / RSC_IHPSG13_MET3RES +XA_R2 A_RCLK_R A_RCLK_L / RSC_IHPSG13_MET3RES +XA_I90 A_WCLK_B_R A_WCLK_B_L / RSC_IHPSG13_MET3RES +XA_ISENSE A_SAE A_BLC_SEL A_BLT_SEL net19 net20 VDD VSS / ++ RSC_IHPSG13_DFPQD_MSAFFX2 +XA_I78 A_RCLK_B_R A_SAE VDD VSS / RSC_IHPSG13_CBUFX2 +XA_I83 A_BM_R A_BM_N VDD VSS / RSC_IHPSG13_INVX2 +XA_I49 A_DI_R A_DI_N VDD VSS / RSC_IHPSG13_INVX2 +XA_I51 net19 A_DR_O VDD VSS / RSC_IHPSG13_INVX4 +XA_I69 A_DCLK_L A_DCLK_B_L VDD VSS / RSC_IHPSG13_CINVX2 +XA_I50 A_WCLK_L A_WCLK_B_R VDD VSS / RSC_IHPSG13_CINVX2 +XA_EBUF A_RCLK_R A_RCLK_B_R VDD VSS / RSC_IHPSG13_CINVX2 +.ENDS +.SUBCKT RM_IHPSG13_256x8_c2_1P_COLDRV13_FILL4 VDD VSS +XI0<9> VDD VSS / RSC_IHPSG13_FILLCAP4 +XI0<8> VDD VSS / RSC_IHPSG13_FILLCAP4 +XI0<7> VDD VSS / RSC_IHPSG13_FILLCAP4 +XI0<6> VDD VSS / RSC_IHPSG13_FILLCAP4 +XI0<5> VDD VSS / RSC_IHPSG13_FILLCAP4 +XI0<4> VDD VSS / RSC_IHPSG13_FILLCAP4 +XI0<3> VDD VSS / RSC_IHPSG13_FILLCAP4 +XI0<2> VDD VSS / RSC_IHPSG13_FILLCAP4 +XI0<1> VDD VSS / RSC_IHPSG13_FILLCAP4 +.ENDS +.SUBCKT RM_IHPSG13_256x8_c2_1P_COLDRV13_FILL4C2 VDD VSS +XI0<2> VDD VSS / RSC_IHPSG13_FILLCAP4 +XI0<1> VDD VSS / RSC_IHPSG13_FILLCAP4 +.ENDS + + +.SUBCKT RM_IHPSG13_256x8_c2_1P_COLDEC4 ACLK_N ADDR<3> ADDR<2> ADDR<1> ADDR<0> ++ ADDR_COL<1> ADDR_COL<0> ADDR_DEC<7> ADDR_DEC<6> ADDR_DEC<5> ADDR_DEC<4> ++ ADDR_DEC<3> ADDR_DEC<2> ADDR_DEC<1> ADDR_DEC<0> BIST_ADDR<3> BIST_ADDR<2> ++ BIST_ADDR<1> BIST_ADDR<0> BIST_EN_I VDD VSS +XI15 ADDR_COL<1> VDD VSS / RSC_IHPSG13_TIEL +XI14 addr_int ADDR_COL<0> VDD VSS / RSC_IHPSG13_CBUFX2 +XDFF<3> BIST_EN_I BIST_ADDR<3> ACLK_N ADDR<3> addr_int net7<0> VDD VSS ++ / RSC_IHPSG13_DFNQMX2IX1 +XDFF<2> BIST_EN_I BIST_ADDR<2> ACLK_N ADDR<2> padr_int<2> net7<1> VDD ++ VSS / RSC_IHPSG13_DFNQMX2IX1 +XDFF<1> BIST_EN_I BIST_ADDR<1> ACLK_N ADDR<1> padr_int<1> net7<2> VDD ++ VSS / RSC_IHPSG13_DFNQMX2IX1 +XDFF<0> BIST_EN_I BIST_ADDR<0> ACLK_N ADDR<0> padr_int<0> net7<3> VDD ++ VSS / RSC_IHPSG13_DFNQMX2IX1 +XI1<7> PADR<0> PADR<1> PADR<2> addr_n<7> VDD VSS / RSC_IHPSG13_NAND3X2 +XI1<6> NADR<0> PADR<1> PADR<2> addr_n<6> VDD VSS / RSC_IHPSG13_NAND3X2 +XI1<5> PADR<0> NADR<1> PADR<2> addr_n<5> VDD VSS / RSC_IHPSG13_NAND3X2 +XI1<4> NADR<0> NADR<1> PADR<2> addr_n<4> VDD VSS / RSC_IHPSG13_NAND3X2 +XI1<3> PADR<0> PADR<1> NADR<2> addr_n<3> VDD VSS / RSC_IHPSG13_NAND3X2 +XI1<2> NADR<0> PADR<1> NADR<2> addr_n<2> VDD VSS / RSC_IHPSG13_NAND3X2 +XI1<1> PADR<0> NADR<1> NADR<2> addr_n<1> VDD VSS / RSC_IHPSG13_NAND3X2 +XI1<0> NADR<0> NADR<1> NADR<2> addr_n<0> VDD VSS / RSC_IHPSG13_NAND3X2 +XI13<2> NADR<2> PADR<2> VDD VSS / RSC_IHPSG13_INVX2 +XI13<1> NADR<1> PADR<1> VDD VSS / RSC_IHPSG13_INVX2 +XI13<0> NADR<0> PADR<0> VDD VSS / RSC_IHPSG13_INVX2 +XI3<2> padr_int<2> NADR<2> VDD VSS / RSC_IHPSG13_INVX2 +XI3<1> padr_int<1> NADR<1> VDD VSS / RSC_IHPSG13_INVX2 +XI3<0> padr_int<0> NADR<0> VDD VSS / RSC_IHPSG13_INVX2 +XI2<7> addr_n<7> ADDR_DEC<7> VDD VSS / RSC_IHPSG13_INVX2 +XI2<6> addr_n<6> ADDR_DEC<6> VDD VSS / RSC_IHPSG13_INVX2 +XI2<5> addr_n<5> ADDR_DEC<5> VDD VSS / RSC_IHPSG13_INVX2 +XI2<4> addr_n<4> ADDR_DEC<4> VDD VSS / RSC_IHPSG13_INVX2 +XI2<3> addr_n<3> ADDR_DEC<3> VDD VSS / RSC_IHPSG13_INVX2 +XI2<2> addr_n<2> ADDR_DEC<2> VDD VSS / RSC_IHPSG13_INVX2 +XI2<1> addr_n<1> ADDR_DEC<1> VDD VSS / RSC_IHPSG13_INVX2 +XI2<0> addr_n<0> ADDR_DEC<0> VDD VSS / RSC_IHPSG13_INVX2 +XI16<3> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI16<2> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI16<1> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI17<2> VDD VSS / RSC_IHPSG13_FILLCAP4 +XI17<1> VDD VSS / RSC_IHPSG13_FILLCAP4 +.ENDS +.SUBCKT RSC_IHPSG13_AND2X4 A B Z VDD VSS +MN3 Z net6 VSS VSS sg13_lv_nmos m=1 w=1.96u l=130.00n ng=2 nrd=0 nrs=0 +MN4 net9 B VSS VSS sg13_lv_nmos m=1 w=500.0n l=130.00n ng=1 nrd=0 nrs=0 +MN6 net6 A net9 VSS sg13_lv_nmos m=1 w=500.0n l=130.00n ng=1 nrd=0 nrs=0 +MP2 Z net6 VDD VDD sg13_lv_pmos m=1 w=3.24u l=130.00n ng=2 nrd=0 nrs=0 +MP0 net6 B VDD VDD sg13_lv_pmos m=1 w=860.00n l=130.00n ng=1 nrd=0 ++ nrs=0 +MP1 net6 A VDD VDD sg13_lv_pmos m=1 w=860.00n l=130.00n ng=1 nrd=0 ++ nrs=0 +.ENDS +.SUBCKT RM_IHPSG13_256x8_c2_1P_COLCTRL4 A_ADDR_COL A_ADDR_DEC<7> A_ADDR_DEC<6> ++ A_ADDR_DEC<5> A_ADDR_DEC<4> A_ADDR_DEC<3> A_ADDR_DEC<2> A_ADDR_DEC<1> ++ A_ADDR_DEC<0> A_BIST_BM_I A_BIST_DW_I A_BIST_EN_I A_BLC<15> A_BLC<14> ++ A_BLC<13> A_BLC<12> A_BLC<11> A_BLC<10> A_BLC<9> A_BLC<8> A_BLC<7> A_BLC<6> ++ A_BLC<5> A_BLC<4> A_BLC<3> A_BLC<2> A_BLC<1> A_BLC<0> A_BLT<15> A_BLT<14> ++ A_BLT<13> A_BLT<12> A_BLT<11> A_BLT<10> A_BLT<9> A_BLT<8> A_BLT<7> A_BLT<6> ++ A_BLT<5> A_BLT<4> A_BLT<3> A_BLT<2> A_BLT<1> A_BLT<0> A_BM_I A_DCLK_B_L ++ A_DCLK_B_R A_DCLK_L A_DCLK_R A_DR_O A_DW_I A_RCLK_B_L A_RCLK_B_R A_RCLK_L ++ A_RCLK_R A_TIEH_O A_WCLK_B_L A_WCLK_B_R A_WCLK_L A_WCLK_R VDD VSS +XA_I80 A_WCLK_B_L A_RCLK_B_L net21 VDD VSS / RSC_IHPSG13_AND2X2 +XA_I76 A_DO_WRITE_P A_DI_N A_WR_ZERO VDD VSS / RSC_IHPSG13_AND2X4 +XA_I75 A_DI_R A_DO_WRITE_P A_WR_ONE VDD VSS / RSC_IHPSG13_AND2X4 +XA_CAPS<8> VDD VSS / RSC_IHPSG13_FILLCAP4 +XA_CAPS<7> VDD VSS / RSC_IHPSG13_FILLCAP4 +XA_CAPS<6> VDD VSS / RSC_IHPSG13_FILLCAP4 +XA_CAPS<5> VDD VSS / RSC_IHPSG13_FILLCAP4 +XA_CAPS<4> VDD VSS / RSC_IHPSG13_FILLCAP4 +XA_CAPS<3> VDD VSS / RSC_IHPSG13_FILLCAP4 +XA_CAPS<2> VDD VSS / RSC_IHPSG13_FILLCAP4 +XA_CAPS<1> VDD VSS / RSC_IHPSG13_FILLCAP4 +XA_I69 A_DCLK_L A_DCLK_B_L VDD VSS / RSC_IHPSG13_CINVX4 +XA_I50 A_WCLK_L A_WCLK_B_L VDD VSS / RSC_IHPSG13_CINVX4 +XA_EBUF A_RCLK_L A_RCLK_B_L VDD VSS / RSC_IHPSG13_CINVX4 +XA_INV<1> A_N0 A_P0 VDD VSS / RSC_IHPSG13_CINVX4 +XA_INV<0> A_ADDR_COL A_N0 VDD VSS / RSC_IHPSG13_CINVX4 +XA_I81<1> net21 A_PRE_N VDD VSS / RSC_IHPSG13_CINVX4_WN +XA_I81<0> net21 A_PRE_N VDD VSS / RSC_IHPSG13_CINVX4_WN +XA_BLTMUX<15> A_BLC<15> A_BLC_SEL A_BLT<15> A_BLT_SEL A_PRE_N A_SEL_P<15> ++ A_WR_ONE A_WR_ZERO VDD VSS / RM_IHPSG13_256x8_c2_1P_BLDRV +XA_BLTMUX<14> A_BLC<14> A_BLC_SEL A_BLT<14> A_BLT_SEL A_PRE_N A_SEL_P<14> ++ A_WR_ONE A_WR_ZERO VDD VSS / RM_IHPSG13_256x8_c2_1P_BLDRV +XA_BLTMUX<13> A_BLC<13> A_BLC_SEL A_BLT<13> A_BLT_SEL A_PRE_N A_SEL_P<13> ++ A_WR_ONE A_WR_ZERO VDD VSS / RM_IHPSG13_256x8_c2_1P_BLDRV +XA_BLTMUX<12> A_BLC<12> A_BLC_SEL A_BLT<12> A_BLT_SEL A_PRE_N A_SEL_P<12> ++ A_WR_ONE A_WR_ZERO VDD VSS / RM_IHPSG13_256x8_c2_1P_BLDRV +XA_BLTMUX<11> A_BLC<11> A_BLC_SEL A_BLT<11> A_BLT_SEL A_PRE_N A_SEL_P<11> ++ A_WR_ONE A_WR_ZERO VDD VSS / RM_IHPSG13_256x8_c2_1P_BLDRV +XA_BLTMUX<10> A_BLC<10> A_BLC_SEL A_BLT<10> A_BLT_SEL A_PRE_N A_SEL_P<10> ++ A_WR_ONE A_WR_ZERO VDD VSS / RM_IHPSG13_256x8_c2_1P_BLDRV +XA_BLTMUX<9> A_BLC<9> A_BLC_SEL A_BLT<9> A_BLT_SEL A_PRE_N A_SEL_P<9> A_WR_ONE ++ A_WR_ZERO VDD VSS / RM_IHPSG13_256x8_c2_1P_BLDRV +XA_BLTMUX<8> A_BLC<8> A_BLC_SEL A_BLT<8> A_BLT_SEL A_PRE_N A_SEL_P<8> A_WR_ONE ++ A_WR_ZERO VDD VSS / RM_IHPSG13_256x8_c2_1P_BLDRV +XA_BLTMUX<7> A_BLC<7> A_BLC_SEL A_BLT<7> A_BLT_SEL A_PRE_N A_SEL_P<7> A_WR_ONE ++ A_WR_ZERO VDD VSS / RM_IHPSG13_256x8_c2_1P_BLDRV +XA_BLTMUX<6> A_BLC<6> A_BLC_SEL A_BLT<6> A_BLT_SEL A_PRE_N A_SEL_P<6> A_WR_ONE ++ A_WR_ZERO VDD VSS / RM_IHPSG13_256x8_c2_1P_BLDRV +XA_BLTMUX<5> A_BLC<5> A_BLC_SEL A_BLT<5> A_BLT_SEL A_PRE_N A_SEL_P<5> A_WR_ONE ++ A_WR_ZERO VDD VSS / RM_IHPSG13_256x8_c2_1P_BLDRV +XA_BLTMUX<4> A_BLC<4> A_BLC_SEL A_BLT<4> A_BLT_SEL A_PRE_N A_SEL_P<4> A_WR_ONE ++ A_WR_ZERO VDD VSS / RM_IHPSG13_256x8_c2_1P_BLDRV +XA_BLTMUX<3> A_BLC<3> A_BLC_SEL A_BLT<3> A_BLT_SEL A_PRE_N A_SEL_P<3> A_WR_ONE ++ A_WR_ZERO VDD VSS / RM_IHPSG13_256x8_c2_1P_BLDRV +XA_BLTMUX<2> A_BLC<2> A_BLC_SEL A_BLT<2> A_BLT_SEL A_PRE_N A_SEL_P<2> A_WR_ONE ++ A_WR_ZERO VDD VSS / RM_IHPSG13_256x8_c2_1P_BLDRV +XA_BLTMUX<1> A_BLC<1> A_BLC_SEL A_BLT<1> A_BLT_SEL A_PRE_N A_SEL_P<1> A_WR_ONE ++ A_WR_ZERO VDD VSS / RM_IHPSG13_256x8_c2_1P_BLDRV +XA_BLTMUX<0> A_BLC<0> A_BLC_SEL A_BLT<0> A_BLT_SEL A_PRE_N A_SEL_P<0> A_WR_ONE ++ A_WR_ZERO VDD VSS / RM_IHPSG13_256x8_c2_1P_BLDRV +XA_R2 A_RCLK_L A_RCLK_R / RSC_IHPSG13_MET3RES +XA_I87 A_WCLK_L A_WCLK_R / RSC_IHPSG13_MET3RES +XA_I88 A_DCLK_L A_DCLK_R / RSC_IHPSG13_MET3RES +XA_I89 A_DCLK_B_L A_DCLK_B_R / RSC_IHPSG13_MET3RES +XA_I90 A_WCLK_B_L A_WCLK_B_R / RSC_IHPSG13_MET3RES +XA_I91 A_RCLK_B_L A_RCLK_B_R / RSC_IHPSG13_MET3RES +XA_ISENSE A_SAE A_BLC_SEL A_BLT_SEL net19 net20 VDD VSS / ++ RSC_IHPSG13_DFPQD_MSAFFX2 +XA_I51 net19 A_DR_O VDD VSS / RSC_IHPSG13_INVX4 +XA_I78 A_RCLK_B_L A_SAE VDD VSS / RSC_IHPSG13_CBUFX2 +XA_DREG A_BIST_EN_I A_BIST_DW_I A_DCLK_B_L A_DW_I A_DI_R net22 VDD VSS ++ / RSC_IHPSG13_DFNQMX2IX1 +XA_BREG A_BIST_EN_I A_BIST_BM_I A_DCLK_B_L A_BM_I A_BM_R net24 VDD VSS ++ / RSC_IHPSG13_DFNQMX2IX1 +XA_DEC3INV<15> net23<0> A_SEL_P<15> VDD VSS / RSC_IHPSG13_INVX2 +XA_DEC3INV<14> net23<1> A_SEL_P<14> VDD VSS / RSC_IHPSG13_INVX2 +XA_DEC3INV<13> net23<2> A_SEL_P<13> VDD VSS / RSC_IHPSG13_INVX2 +XA_DEC3INV<12> net23<3> A_SEL_P<12> VDD VSS / RSC_IHPSG13_INVX2 +XA_DEC3INV<11> net23<4> A_SEL_P<11> VDD VSS / RSC_IHPSG13_INVX2 +XA_DEC3INV<10> net23<5> A_SEL_P<10> VDD VSS / RSC_IHPSG13_INVX2 +XA_DEC3INV<9> net23<6> A_SEL_P<9> VDD VSS / RSC_IHPSG13_INVX2 +XA_DEC3INV<8> net23<7> A_SEL_P<8> VDD VSS / RSC_IHPSG13_INVX2 +XA_DEC3INV<7> net23<8> A_SEL_P<7> VDD VSS / RSC_IHPSG13_INVX2 +XA_DEC3INV<6> net23<9> A_SEL_P<6> VDD VSS / RSC_IHPSG13_INVX2 +XA_DEC3INV<5> net23<10> A_SEL_P<5> VDD VSS / RSC_IHPSG13_INVX2 +XA_DEC3INV<4> net23<11> A_SEL_P<4> VDD VSS / RSC_IHPSG13_INVX2 +XA_DEC3INV<3> net23<12> A_SEL_P<3> VDD VSS / RSC_IHPSG13_INVX2 +XA_DEC3INV<2> net23<13> A_SEL_P<2> VDD VSS / RSC_IHPSG13_INVX2 +XA_DEC3INV<1> net23<14> A_SEL_P<1> VDD VSS / RSC_IHPSG13_INVX2 +XA_DEC3INV<0> net23<15> A_SEL_P<0> VDD VSS / RSC_IHPSG13_INVX2 +XA_I83 A_BM_R A_BM_N VDD VSS / RSC_IHPSG13_INVX2 +XA_I49 A_DI_R A_DI_N VDD VSS / RSC_IHPSG13_INVX2 +XA_I70<4> VDD VSS / RSC_IHPSG13_FILLCAP8 +XA_I70<3> VDD VSS / RSC_IHPSG13_FILLCAP8 +XA_I70<2> VDD VSS / RSC_IHPSG13_FILLCAP8 +XA_I70<1> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI73<14> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI73<13> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI73<12> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI73<11> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI73<10> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI73<9> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI73<8> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI73<7> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI73<6> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI73<5> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI73<4> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI73<3> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI73<2> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI73<1> VDD VSS / RSC_IHPSG13_FILLCAP8 +XA_I44 A_BM_N A_WCLK_B_L A_DO_WRITE_P VDD VSS / RSC_IHPSG13_NOR2X2 +XA_DEC3<15> A_P0 A_ADDR_DEC<7> net23<0> VDD VSS / RSC_IHPSG13_NAND2X2 +XA_DEC3<14> A_P0 A_ADDR_DEC<6> net23<1> VDD VSS / RSC_IHPSG13_NAND2X2 +XA_DEC3<13> A_P0 A_ADDR_DEC<5> net23<2> VDD VSS / RSC_IHPSG13_NAND2X2 +XA_DEC3<12> A_P0 A_ADDR_DEC<4> net23<3> VDD VSS / RSC_IHPSG13_NAND2X2 +XA_DEC3<11> A_P0 A_ADDR_DEC<3> net23<4> VDD VSS / RSC_IHPSG13_NAND2X2 +XA_DEC3<10> A_P0 A_ADDR_DEC<2> net23<5> VDD VSS / RSC_IHPSG13_NAND2X2 +XA_DEC3<9> A_P0 A_ADDR_DEC<1> net23<6> VDD VSS / RSC_IHPSG13_NAND2X2 +XA_DEC3<8> A_P0 A_ADDR_DEC<0> net23<7> VDD VSS / RSC_IHPSG13_NAND2X2 +XA_DEC3<7> A_N0 A_ADDR_DEC<7> net23<8> VDD VSS / RSC_IHPSG13_NAND2X2 +XA_DEC3<6> A_N0 A_ADDR_DEC<6> net23<9> VDD VSS / RSC_IHPSG13_NAND2X2 +XA_DEC3<5> A_N0 A_ADDR_DEC<5> net23<10> VDD VSS / RSC_IHPSG13_NAND2X2 +XA_DEC3<4> A_N0 A_ADDR_DEC<4> net23<11> VDD VSS / RSC_IHPSG13_NAND2X2 +XA_DEC3<3> A_N0 A_ADDR_DEC<3> net23<12> VDD VSS / RSC_IHPSG13_NAND2X2 +XA_DEC3<2> A_N0 A_ADDR_DEC<2> net23<13> VDD VSS / RSC_IHPSG13_NAND2X2 +XA_DEC3<1> A_N0 A_ADDR_DEC<1> net23<14> VDD VSS / RSC_IHPSG13_NAND2X2 +XA_DEC3<0> A_N0 A_ADDR_DEC<0> net23<15> VDD VSS / RSC_IHPSG13_NAND2X2 +XA_BM_TIEH A_TIEH_O VDD VSS / RSC_IHPSG13_TIEH +.ENDS + + +.SUBCKT RM_IHPSG13_256x8_c2_1P_COLDEC3 ACLK_N ADDR<2> ADDR<1> ADDR<0> ADDR_COL<1> ++ ADDR_COL<0> ADDR_DEC<7> ADDR_DEC<6> ADDR_DEC<5> ADDR_DEC<4> ADDR_DEC<3> ++ ADDR_DEC<2> ADDR_DEC<1> ADDR_DEC<0> BIST_ADDR<2> BIST_ADDR<1> BIST_ADDR<0> ++ BIST_EN_I VDD VSS +XI15<1> ADDR_COL<1> VDD VSS / RSC_IHPSG13_TIEL +XI15<0> ADDR_COL<0> VDD VSS / RSC_IHPSG13_TIEL +XI1<7> PADR<0> PADR<1> PADR<2> addr_n<7> VDD VSS / RSC_IHPSG13_NAND3X2 +XI1<6> NADR<0> PADR<1> PADR<2> addr_n<6> VDD VSS / RSC_IHPSG13_NAND3X2 +XI1<5> PADR<0> NADR<1> PADR<2> addr_n<5> VDD VSS / RSC_IHPSG13_NAND3X2 +XI1<4> NADR<0> NADR<1> PADR<2> addr_n<4> VDD VSS / RSC_IHPSG13_NAND3X2 +XI1<3> PADR<0> PADR<1> NADR<2> addr_n<3> VDD VSS / RSC_IHPSG13_NAND3X2 +XI1<2> NADR<0> PADR<1> NADR<2> addr_n<2> VDD VSS / RSC_IHPSG13_NAND3X2 +XI1<1> PADR<0> NADR<1> NADR<2> addr_n<1> VDD VSS / RSC_IHPSG13_NAND3X2 +XI1<0> NADR<0> NADR<1> NADR<2> addr_n<0> VDD VSS / RSC_IHPSG13_NAND3X2 +XDFF<2> BIST_EN_I BIST_ADDR<2> ACLK_N ADDR<2> padr_int<2> net6<0> VDD ++ VSS / RSC_IHPSG13_DFNQMX2IX1 +XDFF<1> BIST_EN_I BIST_ADDR<1> ACLK_N ADDR<1> padr_int<1> net6<1> VDD ++ VSS / RSC_IHPSG13_DFNQMX2IX1 +XDFF<0> BIST_EN_I BIST_ADDR<0> ACLK_N ADDR<0> padr_int<0> net6<2> VDD ++ VSS / RSC_IHPSG13_DFNQMX2IX1 +XI17<2> VDD VSS / RSC_IHPSG13_FILLCAP4 +XI17<1> VDD VSS / RSC_IHPSG13_FILLCAP4 +XI13<2> NADR<2> PADR<2> VDD VSS / RSC_IHPSG13_INVX2 +XI13<1> NADR<1> PADR<1> VDD VSS / RSC_IHPSG13_INVX2 +XI13<0> NADR<0> PADR<0> VDD VSS / RSC_IHPSG13_INVX2 +XI3<2> padr_int<2> NADR<2> VDD VSS / RSC_IHPSG13_INVX2 +XI3<1> padr_int<1> NADR<1> VDD VSS / RSC_IHPSG13_INVX2 +XI3<0> padr_int<0> NADR<0> VDD VSS / RSC_IHPSG13_INVX2 +XI2<7> addr_n<7> ADDR_DEC<7> VDD VSS / RSC_IHPSG13_INVX2 +XI2<6> addr_n<6> ADDR_DEC<6> VDD VSS / RSC_IHPSG13_INVX2 +XI2<5> addr_n<5> ADDR_DEC<5> VDD VSS / RSC_IHPSG13_INVX2 +XI2<4> addr_n<4> ADDR_DEC<4> VDD VSS / RSC_IHPSG13_INVX2 +XI2<3> addr_n<3> ADDR_DEC<3> VDD VSS / RSC_IHPSG13_INVX2 +XI2<2> addr_n<2> ADDR_DEC<2> VDD VSS / RSC_IHPSG13_INVX2 +XI2<1> addr_n<1> ADDR_DEC<1> VDD VSS / RSC_IHPSG13_INVX2 +XI2<0> addr_n<0> ADDR_DEC<0> VDD VSS / RSC_IHPSG13_INVX2 +XI16<6> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI16<5> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI16<4> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI16<3> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI16<2> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI16<1> VDD VSS / RSC_IHPSG13_FILLCAP8 +.ENDS +.SUBCKT RM_IHPSG13_256x8_c2_1P_COLCTRL3 A_ADDR_DEC<7> A_ADDR_DEC<6> A_ADDR_DEC<5> ++ A_ADDR_DEC<4> A_ADDR_DEC<3> A_ADDR_DEC<2> A_ADDR_DEC<1> A_ADDR_DEC<0> ++ A_BIST_BM_I A_BIST_DW_I A_BIST_EN_I A_BLC<7> A_BLC<6> A_BLC<5> A_BLC<4> ++ A_BLC<3> A_BLC<2> A_BLC<1> A_BLC<0> A_BLT<7> A_BLT<6> A_BLT<5> A_BLT<4> ++ A_BLT<3> A_BLT<2> A_BLT<1> A_BLT<0> A_BM_I A_DCLK_B_L A_DCLK_B_R A_DCLK_L ++ A_DCLK_R A_DR_O A_DW_I A_RCLK_B_L A_RCLK_B_R A_RCLK_L A_RCLK_R A_TIEH_O ++ A_WCLK_B_L A_WCLK_B_R A_WCLK_L A_WCLK_R VDD VSS +XA_DREG A_BIST_EN_I A_BIST_DW_I A_DCLK_B_L A_DW_I A_DI_R net22 VDD VSS ++ / RSC_IHPSG13_DFNQMX2IX1 +XA_BREG A_BIST_EN_I A_BIST_BM_I A_DCLK_B_R A_BM_I A_BM_R net23 VDD VSS ++ / RSC_IHPSG13_DFNQMX2IX1 +XA_I70<8> VDD VSS / RSC_IHPSG13_FILLCAP8 +XA_I70<7> VDD VSS / RSC_IHPSG13_FILLCAP8 +XA_I70<6> VDD VSS / RSC_IHPSG13_FILLCAP8 +XA_I70<5> VDD VSS / RSC_IHPSG13_FILLCAP8 +XA_I70<4> VDD VSS / RSC_IHPSG13_FILLCAP8 +XA_I70<3> VDD VSS / RSC_IHPSG13_FILLCAP8 +XA_I70<2> VDD VSS / RSC_IHPSG13_FILLCAP8 +XA_I70<1> VDD VSS / RSC_IHPSG13_FILLCAP8 +XA_I51 net19 A_DR_O VDD VSS / RSC_IHPSG13_INVX4 +XA_I44 A_BM_N A_WCLK_B_R A_DO_WRITE_P VDD VSS / RSC_IHPSG13_NOR2X2 +XA_BM_TIEH A_TIEH_O VDD VSS / RSC_IHPSG13_TIEH +XA_BLTMUX<7> A_BLC<7> A_BLC_SEL A_BLT<7> A_BLT_SEL A_PRE_N A_ADDR_DEC<7> ++ A_WR_ONE A_WR_ZERO VDD VSS / RM_IHPSG13_256x8_c2_1P_BLDRV +XA_BLTMUX<6> A_BLC<6> A_BLC_SEL A_BLT<6> A_BLT_SEL A_PRE_N A_ADDR_DEC<6> ++ A_WR_ONE A_WR_ZERO VDD VSS / RM_IHPSG13_256x8_c2_1P_BLDRV +XA_BLTMUX<5> A_BLC<5> A_BLC_SEL A_BLT<5> A_BLT_SEL A_PRE_N A_ADDR_DEC<5> ++ A_WR_ONE A_WR_ZERO VDD VSS / RM_IHPSG13_256x8_c2_1P_BLDRV +XA_BLTMUX<4> A_BLC<4> A_BLC_SEL A_BLT<4> A_BLT_SEL A_PRE_N A_ADDR_DEC<4> ++ A_WR_ONE A_WR_ZERO VDD VSS / RM_IHPSG13_256x8_c2_1P_BLDRV +XA_BLTMUX<3> A_BLC<3> A_BLC_SEL A_BLT<3> A_BLT_SEL A_PRE_N A_ADDR_DEC<3> ++ A_WR_ONE A_WR_ZERO VDD VSS / RM_IHPSG13_256x8_c2_1P_BLDRV +XA_BLTMUX<2> A_BLC<2> A_BLC_SEL A_BLT<2> A_BLT_SEL A_PRE_N A_ADDR_DEC<2> ++ A_WR_ONE A_WR_ZERO VDD VSS / RM_IHPSG13_256x8_c2_1P_BLDRV +XA_BLTMUX<1> A_BLC<1> A_BLC_SEL A_BLT<1> A_BLT_SEL A_PRE_N A_ADDR_DEC<1> ++ A_WR_ONE A_WR_ZERO VDD VSS / RM_IHPSG13_256x8_c2_1P_BLDRV +XA_BLTMUX<0> A_BLC<0> A_BLC_SEL A_BLT<0> A_BLT_SEL A_PRE_N A_ADDR_DEC<0> ++ A_WR_ONE A_WR_ZERO VDD VSS / RM_IHPSG13_256x8_c2_1P_BLDRV +XA_I49 A_DI_R A_DI_N VDD VSS / RSC_IHPSG13_INVX2 +XA_I83 A_BM_R A_BM_N VDD VSS / RSC_IHPSG13_INVX2 +XA_I69 A_DCLK_L A_DCLK_B_L VDD VSS / RSC_IHPSG13_CINVX2 +XA_I50 A_WCLK_L A_WCLK_B_L VDD VSS / RSC_IHPSG13_CINVX2 +XA_EBUF A_RCLK_L A_RCLK_B_L VDD VSS / RSC_IHPSG13_CINVX2 +XA_I78 A_RCLK_B_L A_SAE VDD VSS / RSC_IHPSG13_CBUFX2 +XA_I88 A_DCLK_L A_DCLK_R / RSC_IHPSG13_MET3RES +XA_I87 A_WCLK_L A_WCLK_R / RSC_IHPSG13_MET3RES +XA_R2 A_RCLK_L A_RCLK_R / RSC_IHPSG13_MET3RES +XA_I91 A_RCLK_B_L A_RCLK_B_R / RSC_IHPSG13_MET3RES +XA_I90 A_WCLK_B_L A_WCLK_B_R / RSC_IHPSG13_MET3RES +XA_I89 A_DCLK_B_L A_DCLK_B_R / RSC_IHPSG13_MET3RES +XA_I80 A_WCLK_B_R A_RCLK_B_R net21 VDD VSS / RSC_IHPSG13_AND2X2 +XA_I76 A_DI_N A_DO_WRITE_P A_WR_ZERO VDD VSS / RSC_IHPSG13_AND2X2 +XA_I75 A_DI_R A_DO_WRITE_P A_WR_ONE VDD VSS / RSC_IHPSG13_AND2X2 +XA_ISENSE A_SAE A_BLC_SEL A_BLT_SEL net19 net20 VDD VSS / ++ RSC_IHPSG13_DFPQD_MSAFFX2 +XA_I81 net21 A_PRE_N VDD VSS / RSC_IHPSG13_CINVX4_WN +XA_CAPS<5> VDD VSS / RSC_IHPSG13_FILLCAP4 +XA_CAPS<4> VDD VSS / RSC_IHPSG13_FILLCAP4 +XA_CAPS<3> VDD VSS / RSC_IHPSG13_FILLCAP4 +XA_CAPS<2> VDD VSS / RSC_IHPSG13_FILLCAP4 +XA_CAPS<1> VDD VSS / RSC_IHPSG13_FILLCAP4 +.ENDS + +.SUBCKT RM_IHPSG13_256x8_c2_2P_BITKIT_16x2_CORNER VDD_CORE VSS +XI16 VDD_CORE VSS VDD_CORE VSS / ++ RM_IHPSG13_256x8_c2_1P_BITKIT_CORNER +.ENDS +.SUBCKT RM_IHPSG13_256x8_c2_2P_BITKIT_EDGE_LR A_WL B_WL NW PW VDD VSS +MN1 VSS A_WL VSS VSS sg13_lv_nmos m=1 w=300.0n l=130.00n ng=1 nrd=0 nrs=0 +MN0 VSS B_WL VSS VSS sg13_lv_nmos m=1 w=300.0n l=130.00n ng=1 nrd=0 nrs=0 +.ENDS +.SUBCKT RM_IHPSG13_256x8_c2_2P_BITKIT_16x2_EDGE_LR A_WL<15> A_WL<14> A_WL<13> A_WL<12> ++ A_WL<11> A_WL<10> A_WL<9> A_WL<8> A_WL<7> A_WL<6> A_WL<5> A_WL<4> A_WL<3> ++ A_WL<2> A_WL<1> A_WL<0> B_WL<15> B_WL<14> B_WL<13> B_WL<12> B_WL<11> ++ B_WL<10> B_WL<9> B_WL<8> B_WL<7> B_WL<6> B_WL<5> B_WL<4> B_WL<3> B_WL<2> ++ B_WL<1> B_WL<0> VDD_CORE VSS +XI0<15> A_WL<15> B_WL<15> VDD_CORE VSS VDD_CORE VSS ++ / RM_IHPSG13_256x8_c2_2P_BITKIT_EDGE_LR +XI0<14> A_WL<14> B_WL<14> VDD_CORE VSS VDD_CORE VSS ++ / RM_IHPSG13_256x8_c2_2P_BITKIT_EDGE_LR +XI0<13> A_WL<13> B_WL<13> VDD_CORE VSS VDD_CORE VSS ++ / RM_IHPSG13_256x8_c2_2P_BITKIT_EDGE_LR +XI0<12> A_WL<12> B_WL<12> VDD_CORE VSS VDD_CORE VSS ++ / RM_IHPSG13_256x8_c2_2P_BITKIT_EDGE_LR +XI0<11> A_WL<11> B_WL<11> VDD_CORE VSS VDD_CORE VSS ++ / RM_IHPSG13_256x8_c2_2P_BITKIT_EDGE_LR +XI0<10> A_WL<10> B_WL<10> VDD_CORE VSS VDD_CORE VSS ++ / RM_IHPSG13_256x8_c2_2P_BITKIT_EDGE_LR +XI0<9> A_WL<9> B_WL<9> VDD_CORE VSS VDD_CORE VSS / ++ RM_IHPSG13_256x8_c2_2P_BITKIT_EDGE_LR +XI0<8> A_WL<8> B_WL<8> VDD_CORE VSS VDD_CORE VSS / ++ RM_IHPSG13_256x8_c2_2P_BITKIT_EDGE_LR +XI0<7> A_WL<7> B_WL<7> VDD_CORE VSS VDD_CORE VSS / ++ RM_IHPSG13_256x8_c2_2P_BITKIT_EDGE_LR +XI0<6> A_WL<6> B_WL<6> VDD_CORE VSS VDD_CORE VSS / ++ RM_IHPSG13_256x8_c2_2P_BITKIT_EDGE_LR +XI0<5> A_WL<5> B_WL<5> VDD_CORE VSS VDD_CORE VSS / ++ RM_IHPSG13_256x8_c2_2P_BITKIT_EDGE_LR +XI0<4> A_WL<4> B_WL<4> VDD_CORE VSS VDD_CORE VSS / ++ RM_IHPSG13_256x8_c2_2P_BITKIT_EDGE_LR +XI0<3> A_WL<3> B_WL<3> VDD_CORE VSS VDD_CORE VSS / ++ RM_IHPSG13_256x8_c2_2P_BITKIT_EDGE_LR +XI0<2> A_WL<2> B_WL<2> VDD_CORE VSS VDD_CORE VSS / ++ RM_IHPSG13_256x8_c2_2P_BITKIT_EDGE_LR +XI0<1> A_WL<1> B_WL<1> VDD_CORE VSS VDD_CORE VSS / ++ RM_IHPSG13_256x8_c2_2P_BITKIT_EDGE_LR +XI0<0> A_WL<0> B_WL<0> VDD_CORE VSS VDD_CORE VSS / ++ RM_IHPSG13_256x8_c2_2P_BITKIT_EDGE_LR +.ENDS +.SUBCKT RM_IHPSG13_256x8_c2_2P_BITKIT_CELL A_BLC_BOT A_BLC_TOP A_BLT_BOT A_BLT_TOP ++ A_LWL A_RWL B_BLC_BOT B_BLC_TOP B_BLT_BOT B_BLT_TOP B_LWL B_RWL NW PW VDD VSS +MN5 NC B_RWL B_BLC_BOT PW sg13_lv_nmos m=1 w=300.0n l=130.00n ng=1 nrd=0 nrs=0 +MN4 B_BLT_BOT B_LWL NT PW sg13_lv_nmos m=1 w=300.0n l=130.00n ng=1 nrd=0 nrs=0 +MN0 NC NT VSS PW sg13_lv_nmos m=1 w=600.0n l=130.00n ng=2 nrd=0 nrs=0 +MN1 NT NC VSS PW sg13_lv_nmos m=1 w=600.0n l=130.00n ng=2 nrd=0 nrs=0 +MN3 NC A_RWL A_BLC_TOP PW sg13_lv_nmos m=1 w=300.0n l=130.00n ng=1 nrd=0 nrs=0 +MN2 A_BLT_TOP A_LWL NT PW sg13_lv_nmos m=1 w=300.0n l=130.00n ng=1 nrd=0 nrs=0 +MP1 NT NC VDD NW sg13_lv_pmos m=1 w=150.00n l=130.00n ng=1 nrd=0 nrs=0 +MP0 NC NT VDD NW sg13_lv_pmos m=1 w=150.00n l=130.00n ng=1 nrd=0 nrs=0 +R5 B_RWL B_LWL lvsres w=2.6e-07 l=6e-07 +R4 B_BLC_BOT B_BLC_TOP lvsres w=2.6e-07 l=6e-07 +R3 B_BLT_BOT B_BLT_TOP lvsres w=2.6e-07 l=6e-07 +R1 A_BLC_BOT A_BLC_TOP lvsres w=2.6e-07 l=6e-07 +R0 A_BLT_BOT A_BLT_TOP lvsres w=2.6e-07 l=6e-07 +R2 A_RWL A_LWL lvsres w=2.6e-07 l=6e-07 +.ENDS +.SUBCKT RM_IHPSG13_256x8_c2_2P_BITKIT_16x2_SRAM A_BLC_BOT<1> A_BLC_BOT<0> A_BLC_TOP<1> ++ A_BLC_TOP<0> A_BLT_BOT<1> A_BLT_BOT<0> A_BLT_TOP<1> A_BLT_TOP<0> A_LWL<15> ++ A_LWL<14> A_LWL<13> A_LWL<12> A_LWL<11> A_LWL<10> A_LWL<9> A_LWL<8> A_LWL<7> ++ A_LWL<6> A_LWL<5> A_LWL<4> A_LWL<3> A_LWL<2> A_LWL<1> A_LWL<0> A_RWL<15> ++ A_RWL<14> A_RWL<13> A_RWL<12> A_RWL<11> A_RWL<10> A_RWL<9> A_RWL<8> A_RWL<7> ++ A_RWL<6> A_RWL<5> A_RWL<4> A_RWL<3> A_RWL<2> A_RWL<1> A_RWL<0> B_BLC_BOT<1> ++ B_BLC_BOT<0> B_BLC_TOP<1> B_BLC_TOP<0> B_BLT_BOT<1> B_BLT_BOT<0> ++ B_BLT_TOP<1> B_BLT_TOP<0> B_LWL<15> B_LWL<14> B_LWL<13> B_LWL<12> B_LWL<11> ++ B_LWL<10> B_LWL<9> B_LWL<8> B_LWL<7> B_LWL<6> B_LWL<5> B_LWL<4> B_LWL<3> ++ B_LWL<2> B_LWL<1> B_LWL<0> B_RWL<15> B_RWL<14> B_RWL<13> B_RWL<12> B_RWL<11> ++ B_RWL<10> B_RWL<9> B_RWL<8> B_RWL<7> B_RWL<6> B_RWL<5> B_RWL<4> B_RWL<3> ++ B_RWL<2> B_RWL<1> B_RWL<0> VDD_CORE VSS +XCELL<31> A_BLC_TOP<1> A_RBLC<15> A_BLT_TOP<1> A_RBLT<15> A_XWL<15> A_RWL<15> ++ B_BLC_TOP<1> B_RBLC<15> B_BLT_TOP<1> B_RBLT<15> B_XWL<15> B_RWL<15> ++ VDD_CORE VSS VDD_CORE VSS / ++ RM_IHPSG13_256x8_c2_2P_BITKIT_CELL +XCELL<30> A_RBLC<14> A_RBLC<15> A_RBLT<14> A_RBLT<15> A_XWL<14> A_RWL<14> ++ B_RBLC<14> B_RBLC<15> B_RBLT<14> B_RBLT<15> B_XWL<14> B_RWL<14> VDD_CORE ++ VSS VDD_CORE VSS / RM_IHPSG13_256x8_c2_2P_BITKIT_CELL +XCELL<29> A_RBLC<14> A_RBLC<13> A_RBLT<14> A_RBLT<13> A_XWL<13> A_RWL<13> ++ B_RBLC<14> B_RBLC<13> B_RBLT<14> B_RBLT<13> B_XWL<13> B_RWL<13> VDD_CORE ++ VSS VDD_CORE VSS / RM_IHPSG13_256x8_c2_2P_BITKIT_CELL +XCELL<28> A_RBLC<12> A_RBLC<13> A_RBLT<12> A_RBLT<13> A_XWL<12> A_RWL<12> ++ B_RBLC<12> B_RBLC<13> B_RBLT<12> B_RBLT<13> B_XWL<12> B_RWL<12> VDD_CORE ++ VSS VDD_CORE VSS / RM_IHPSG13_256x8_c2_2P_BITKIT_CELL +XCELL<27> A_RBLC<12> A_RBLC<11> A_RBLT<12> A_RBLT<11> A_XWL<11> A_RWL<11> ++ B_RBLC<12> B_RBLC<11> B_RBLT<12> B_RBLT<11> B_XWL<11> B_RWL<11> VDD_CORE ++ VSS VDD_CORE VSS / RM_IHPSG13_256x8_c2_2P_BITKIT_CELL +XCELL<26> A_RBLC<10> A_RBLC<11> A_RBLT<10> A_RBLT<11> A_XWL<10> A_RWL<10> ++ B_RBLC<10> B_RBLC<11> B_RBLT<10> B_RBLT<11> B_XWL<10> B_RWL<10> VDD_CORE ++ VSS VDD_CORE VSS / RM_IHPSG13_256x8_c2_2P_BITKIT_CELL +XCELL<25> A_RBLC<10> A_RBLC<9> A_RBLT<10> A_RBLT<9> A_XWL<9> A_RWL<9> ++ B_RBLC<10> B_RBLC<9> B_RBLT<10> B_RBLT<9> B_XWL<9> B_RWL<9> VDD_CORE ++ VSS VDD_CORE VSS / RM_IHPSG13_256x8_c2_2P_BITKIT_CELL +XCELL<24> A_RBLC<8> A_RBLC<9> A_RBLT<8> A_RBLT<9> A_XWL<8> A_RWL<8> B_RBLC<8> ++ B_RBLC<9> B_RBLT<8> B_RBLT<9> B_XWL<8> B_RWL<8> VDD_CORE VSS ++ VDD_CORE VSS / RM_IHPSG13_256x8_c2_2P_BITKIT_CELL +XCELL<23> A_RBLC<8> A_RBLC<7> A_RBLT<8> A_RBLT<7> A_XWL<7> A_RWL<7> B_RBLC<8> ++ B_RBLC<7> B_RBLT<8> B_RBLT<7> B_XWL<7> B_RWL<7> VDD_CORE VSS ++ VDD_CORE VSS / RM_IHPSG13_256x8_c2_2P_BITKIT_CELL +XCELL<22> A_RBLC<6> A_RBLC<7> A_RBLT<6> A_RBLT<7> A_XWL<6> A_RWL<6> B_RBLC<6> ++ B_RBLC<7> B_RBLT<6> B_RBLT<7> B_XWL<6> B_RWL<6> VDD_CORE VSS ++ VDD_CORE VSS / RM_IHPSG13_256x8_c2_2P_BITKIT_CELL +XCELL<21> A_RBLC<6> A_RBLC<5> A_RBLT<6> A_RBLT<5> A_XWL<5> A_RWL<5> B_RBLC<6> ++ B_RBLC<5> B_RBLT<6> B_RBLT<5> B_XWL<5> B_RWL<5> VDD_CORE VSS ++ VDD_CORE VSS / RM_IHPSG13_256x8_c2_2P_BITKIT_CELL +XCELL<20> A_RBLC<4> A_RBLC<5> A_RBLT<4> A_RBLT<5> A_XWL<4> A_RWL<4> B_RBLC<4> ++ B_RBLC<5> B_RBLT<4> B_RBLT<5> B_XWL<4> B_RWL<4> VDD_CORE VSS ++ VDD_CORE VSS / RM_IHPSG13_256x8_c2_2P_BITKIT_CELL +XCELL<19> A_RBLC<4> A_RBLC<3> A_RBLT<4> A_RBLT<3> A_XWL<3> A_RWL<3> B_RBLC<4> ++ B_RBLC<3> B_RBLT<4> B_RBLT<3> B_XWL<3> B_RWL<3> VDD_CORE VSS ++ VDD_CORE VSS / RM_IHPSG13_256x8_c2_2P_BITKIT_CELL +XCELL<18> A_RBLC<2> A_RBLC<3> A_RBLT<2> A_RBLT<3> A_XWL<2> A_RWL<2> B_RBLC<2> ++ B_RBLC<3> B_RBLT<2> B_RBLT<3> B_XWL<2> B_RWL<2> VDD_CORE VSS ++ VDD_CORE VSS / RM_IHPSG13_256x8_c2_2P_BITKIT_CELL +XCELL<17> A_RBLC<2> A_RBLC<1> A_RBLT<2> A_RBLT<1> A_XWL<1> A_RWL<1> B_RBLC<2> ++ B_RBLC<1> B_RBLT<2> B_RBLT<1> B_XWL<1> B_RWL<1> VDD_CORE VSS ++ VDD_CORE VSS / RM_IHPSG13_256x8_c2_2P_BITKIT_CELL +XCELL<16> A_BLC_BOT<1> A_RBLC<1> A_BLT_BOT<1> A_RBLT<1> A_XWL<0> A_RWL<0> ++ B_BLC_BOT<1> B_RBLC<1> B_BLT_BOT<1> B_RBLT<1> B_XWL<0> B_RWL<0> VDD_CORE ++ VSS VDD_CORE VSS / RM_IHPSG13_256x8_c2_2P_BITKIT_CELL +XCELL<15> A_BLC_TOP<0> A_LBLC<15> A_BLT_TOP<0> A_LBLT<15> A_LWL<15> A_XWL<15> ++ B_BLC_TOP<0> B_LBLC<15> B_BLT_TOP<0> B_LBLT<15> B_LWL<15> B_XWL<15> ++ VDD_CORE VSS VDD_CORE VSS / ++ RM_IHPSG13_256x8_c2_2P_BITKIT_CELL +XCELL<14> A_LBLC<14> A_LBLC<15> A_LBLT<14> A_LBLT<15> A_LWL<14> A_XWL<14> ++ B_LBLC<14> B_LBLC<15> B_LBLT<14> B_LBLT<15> B_LWL<14> B_XWL<14> VDD_CORE ++ VSS VDD_CORE VSS / RM_IHPSG13_256x8_c2_2P_BITKIT_CELL +XCELL<13> A_LBLC<14> A_LBLC<13> A_LBLT<14> A_LBLT<13> A_LWL<13> A_XWL<13> ++ B_LBLC<14> B_LBLC<13> B_LBLT<14> B_LBLT<13> B_LWL<13> B_XWL<13> VDD_CORE ++ VSS VDD_CORE VSS / RM_IHPSG13_256x8_c2_2P_BITKIT_CELL +XCELL<12> A_LBLC<12> A_LBLC<13> A_LBLT<12> A_LBLT<13> A_LWL<12> A_XWL<12> ++ B_LBLC<12> B_LBLC<13> B_LBLT<12> B_LBLT<13> B_LWL<12> B_XWL<12> VDD_CORE ++ VSS VDD_CORE VSS / RM_IHPSG13_256x8_c2_2P_BITKIT_CELL +XCELL<11> A_LBLC<12> A_LBLC<11> A_LBLT<12> A_LBLT<11> A_LWL<11> A_XWL<11> ++ B_LBLC<12> B_LBLC<11> B_LBLT<12> B_LBLT<11> B_LWL<11> B_XWL<11> VDD_CORE ++ VSS VDD_CORE VSS / RM_IHPSG13_256x8_c2_2P_BITKIT_CELL +XCELL<10> A_LBLC<10> A_LBLC<11> A_LBLT<10> A_LBLT<11> A_LWL<10> A_XWL<10> ++ B_LBLC<10> B_LBLC<11> B_LBLT<10> B_LBLT<11> B_LWL<10> B_XWL<10> VDD_CORE ++ VSS VDD_CORE VSS / RM_IHPSG13_256x8_c2_2P_BITKIT_CELL +XCELL<9> A_LBLC<10> A_LBLC<9> A_LBLT<10> A_LBLT<9> A_LWL<9> A_XWL<9> ++ B_LBLC<10> B_LBLC<9> B_LBLT<10> B_LBLT<9> B_LWL<9> B_XWL<9> VDD_CORE ++ VSS VDD_CORE VSS / RM_IHPSG13_256x8_c2_2P_BITKIT_CELL +XCELL<8> A_LBLC<8> A_LBLC<9> A_LBLT<8> A_LBLT<9> A_LWL<8> A_XWL<8> B_LBLC<8> ++ B_LBLC<9> B_LBLT<8> B_LBLT<9> B_LWL<8> B_XWL<8> VDD_CORE VSS ++ VDD_CORE VSS / RM_IHPSG13_256x8_c2_2P_BITKIT_CELL +XCELL<7> A_LBLC<8> A_LBLC<7> A_LBLT<8> A_LBLT<7> A_LWL<7> A_XWL<7> B_LBLC<8> ++ B_LBLC<7> B_LBLT<8> B_LBLT<7> B_LWL<7> B_XWL<7> VDD_CORE VSS ++ VDD_CORE VSS / RM_IHPSG13_256x8_c2_2P_BITKIT_CELL +XCELL<6> A_LBLC<6> A_LBLC<7> A_LBLT<6> A_LBLT<7> A_LWL<6> A_XWL<6> B_LBLC<6> ++ B_LBLC<7> B_LBLT<6> B_LBLT<7> B_LWL<6> B_XWL<6> VDD_CORE VSS ++ VDD_CORE VSS / RM_IHPSG13_256x8_c2_2P_BITKIT_CELL +XCELL<5> A_LBLC<6> A_LBLC<5> A_LBLT<6> A_LBLT<5> A_LWL<5> A_XWL<5> B_LBLC<6> ++ B_LBLC<5> B_LBLT<6> B_LBLT<5> B_LWL<5> B_XWL<5> VDD_CORE VSS ++ VDD_CORE VSS / RM_IHPSG13_256x8_c2_2P_BITKIT_CELL +XCELL<4> A_LBLC<4> A_LBLC<5> A_LBLT<4> A_LBLT<5> A_LWL<4> A_XWL<4> B_LBLC<4> ++ B_LBLC<5> B_LBLT<4> B_LBLT<5> B_LWL<4> B_XWL<4> VDD_CORE VSS ++ VDD_CORE VSS / RM_IHPSG13_256x8_c2_2P_BITKIT_CELL +XCELL<3> A_LBLC<4> A_LBLC<3> A_LBLT<4> A_LBLT<3> A_LWL<3> A_XWL<3> B_LBLC<4> ++ B_LBLC<3> B_LBLT<4> B_LBLT<3> B_LWL<3> B_XWL<3> VDD_CORE VSS ++ VDD_CORE VSS / RM_IHPSG13_256x8_c2_2P_BITKIT_CELL +XCELL<2> A_LBLC<2> A_LBLC<3> A_LBLT<2> A_LBLT<3> A_LWL<2> A_XWL<2> B_LBLC<2> ++ B_LBLC<3> B_LBLT<2> B_LBLT<3> B_LWL<2> B_XWL<2> VDD_CORE VSS ++ VDD_CORE VSS / RM_IHPSG13_256x8_c2_2P_BITKIT_CELL +XCELL<1> A_LBLC<2> A_LBLC<1> A_LBLT<2> A_LBLT<1> A_LWL<1> A_XWL<1> B_LBLC<2> ++ B_LBLC<1> B_LBLT<2> B_LBLT<1> B_LWL<1> B_XWL<1> VDD_CORE VSS ++ VDD_CORE VSS / RM_IHPSG13_256x8_c2_2P_BITKIT_CELL +XCELL<0> A_BLC_BOT<0> A_LBLC<1> A_BLT_BOT<0> A_LBLT<1> A_LWL<0> A_XWL<0> ++ B_BLC_BOT<0> B_LBLC<1> B_BLT_BOT<0> B_LBLT<1> B_LWL<0> B_XWL<0> VDD_CORE ++ VSS VDD_CORE VSS / RM_IHPSG13_256x8_c2_2P_BITKIT_CELL +.ENDS +.SUBCKT RM_IHPSG13_256x8_c2_2P_BITKIT_EDGE_TB A_BLC A_BLT B_BLC B_BLT NW PW VDD VSS +.ENDS +.SUBCKT RM_IHPSG13_256x8_c2_2P_BITKIT_16x2_EDGE_TB A_BLC<1> A_BLC<0> A_BLT<1> A_BLT<0> ++ B_BLC<1> B_BLC<0> B_BLT<1> B_BLT<0> VDD_CORE VSS +XEDGE<1> A_BLC<1> A_BLT<1> B_BLC<1> B_BLT<1> VDD_CORE VSS ++ VDD_CORE VSS / RM_IHPSG13_256x8_c2_2P_BITKIT_EDGE_TB +XEDGE<0> A_BLC<0> A_BLT<0> B_BLC<0> B_BLT<0> VDD_CORE VSS ++ VDD_CORE VSS / RM_IHPSG13_256x8_c2_2P_BITKIT_EDGE_TB +.ENDS +.SUBCKT RM_IHPSG13_256x8_c2_2P_BITKIT_TAP A_BLC A_BLT B_BLC B_BLT NW PW VDD VSS +.ENDS +.SUBCKT RM_IHPSG13_256x8_c2_2P_BITKIT_16x2_TAP A_BLC<1> A_BLC<0> A_BLT<1> A_BLT<0> ++ B_BLC<1> B_BLC<0> B_BLT<1> B_BLT<0> VDD_CORE VSS +XIEDGEBP_COL1<1> A_BLC<1> A_BLT<1> B_BLC<1> B_BLT<1> VDD_CORE VSS ++ VDD_CORE VSS / RM_IHPSG13_256x8_c2_2P_BITKIT_EDGE_TB +XIEDGEBP_COL1<0> A_BLC<1> A_BLT<1> B_BLC<1> B_BLT<1> VDD_CORE VSS ++ VDD_CORE VSS / RM_IHPSG13_256x8_c2_2P_BITKIT_EDGE_TB +XIEDGEBP_COL2<1> A_BLC<0> A_BLT<0> B_BLC<0> B_BLT<0> VDD_CORE VSS ++ VDD_CORE VSS / RM_IHPSG13_256x8_c2_2P_BITKIT_EDGE_TB +XIEDGEBP_COL2<0> A_BLC<0> A_BLT<0> B_BLC<0> B_BLT<0> VDD_CORE VSS ++ VDD_CORE VSS / RM_IHPSG13_256x8_c2_2P_BITKIT_EDGE_TB +XITAP<1> A_BLC<1> A_BLT<1> B_BLC<1> B_BLT<1> VDD_CORE VSS ++ VDD_CORE VSS / RM_IHPSG13_256x8_c2_2P_BITKIT_TAP +XITAP<0> A_BLC<0> A_BLT<0> B_BLC<0> B_BLT<0> VDD_CORE VSS ++ VDD_CORE VSS / RM_IHPSG13_256x8_c2_2P_BITKIT_TAP +.ENDS + + +.SUBCKT RM_IHPSG13_256x8_c2_1P_BITKIT_TAP_LR NW PW VDD VSS +.ENDS +.SUBCKT RM_IHPSG13_256x8_c2_2P_BITKIT_16x2_TAP_LR VDD_CORE VSS +XCORNER<1> VDD_CORE VSS VDD_CORE VSS / ++ RM_IHPSG13_256x8_c2_1P_BITKIT_CORNER +XCORNER<0> VDD_CORE VSS VDD_CORE VSS / ++ RM_IHPSG13_256x8_c2_1P_BITKIT_CORNER +XTAP_BORDER VDD_CORE VSS VDD_CORE VSS / ++ RM_IHPSG13_256x8_c2_1P_BITKIT_TAP_LR +.ENDS + +.SUBCKT RSC_IHPSG13_CBUFX12 A Z VDD VSS +MN1 Z net6 VSS VSS sg13_lv_nmos m=1 w=4.23u l=130.00n ng=6 nrd=0 nrs=0 +MN0 net6 A VSS VSS sg13_lv_nmos m=1 w=1.41u l=130.00n ng=2 nrd=0 nrs=0 +MP1 Z net6 VDD VDD sg13_lv_pmos m=1 w=9.72u l=130.00n ng=6 nrd=0 nrs=0 +MP0 net6 A VDD VDD sg13_lv_pmos m=1 w=3.24u l=130.00n ng=2 nrd=0 nrs=0 +.ENDS +.SUBCKT RM_IHPSG13_256x8_c2_2P_COLDRV13X12 ADDR_COL_I<1> ADDR_COL_I<0> ADDR_COL_O<1> ++ ADDR_COL_O<0> ADDR_DEC_I<7> ADDR_DEC_I<6> ADDR_DEC_I<5> ADDR_DEC_I<4> ++ ADDR_DEC_I<3> ADDR_DEC_I<2> ADDR_DEC_I<1> ADDR_DEC_I<0> ADDR_DEC_O<7> ++ ADDR_DEC_O<6> ADDR_DEC_O<5> ADDR_DEC_O<4> ADDR_DEC_O<3> ADDR_DEC_O<2> ++ ADDR_DEC_O<1> ADDR_DEC_O<0> DCLK_I DCLK_O RCLK_I RCLK_O WCLK_I WCLK_O ++ VDD VSS +XI1<3> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI1<2> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI1<1> VDD VSS / RSC_IHPSG13_FILLCAP8 +XWCLK_DRV WCLK_I WCLK_O VDD VSS / RSC_IHPSG13_CBUFX12 +XRCLK_DRV RCLK_I RCLK_O VDD VSS / RSC_IHPSG13_CBUFX12 +XDCLK_DRV DCLK_I DCLK_O VDD VSS / RSC_IHPSG13_CBUFX12 +XADDR_COL_DRV<1> ADDR_COL_I<1> ADDR_COL_O<1> VDD VSS / ++ RSC_IHPSG13_CBUFX12 +XADDR_COL_DRV<0> ADDR_COL_I<0> ADDR_COL_O<0> VDD VSS / ++ RSC_IHPSG13_CBUFX12 +XADDR_DEC_DRV<7> ADDR_DEC_I<7> ADDR_DEC_O<7> VDD VSS / ++ RSC_IHPSG13_CBUFX12 +XADDR_DEC_DRV<6> ADDR_DEC_I<6> ADDR_DEC_O<6> VDD VSS / ++ RSC_IHPSG13_CBUFX12 +XADDR_DEC_DRV<5> ADDR_DEC_I<5> ADDR_DEC_O<5> VDD VSS / ++ RSC_IHPSG13_CBUFX12 +XADDR_DEC_DRV<4> ADDR_DEC_I<4> ADDR_DEC_O<4> VDD VSS / ++ RSC_IHPSG13_CBUFX12 +XADDR_DEC_DRV<3> ADDR_DEC_I<3> ADDR_DEC_O<3> VDD VSS / ++ RSC_IHPSG13_CBUFX12 +XADDR_DEC_DRV<2> ADDR_DEC_I<2> ADDR_DEC_O<2> VDD VSS / ++ RSC_IHPSG13_CBUFX12 +XADDR_DEC_DRV<1> ADDR_DEC_I<1> ADDR_DEC_O<1> VDD VSS / ++ RSC_IHPSG13_CBUFX12 +XADDR_DEC_DRV<0> ADDR_DEC_I<0> ADDR_DEC_O<0> VDD VSS / ++ RSC_IHPSG13_CBUFX12 +XI0<6> VDD VSS / RSC_IHPSG13_FILLCAP4 +XI0<5> VDD VSS / RSC_IHPSG13_FILLCAP4 +XI0<4> VDD VSS / RSC_IHPSG13_FILLCAP4 +XI0<3> VDD VSS / RSC_IHPSG13_FILLCAP4 +XI0<2> VDD VSS / RSC_IHPSG13_FILLCAP4 +XI0<1> VDD VSS / RSC_IHPSG13_FILLCAP4 +.ENDS +.SUBCKT RSC_IHPSG13_WLDRVX12 A Z VDD VSS +MN1 Z net6 VSS VSS sg13_lv_nmos m=1 w=1.41u l=130.00n ng=2 nrd=0 nrs=0 +MN0 net6 A VSS VSS sg13_lv_nmos m=1 w=1.8u l=130.00n ng=2 nrd=0 nrs=0 +MP1 Z net6 VDD VDD sg13_lv_pmos m=1 w=9.72u l=130.00n ng=6 nrd=0 nrs=0 +MP0 net6 A VDD VDD sg13_lv_pmos m=1 w=900.0n l=130.00n ng=1 nrd=0 nrs=0 +.ENDS +.SUBCKT RM_IHPSG13_256x8_c2_2P_WLDRV16X12 A<15> A<14> A<13> A<12> A<11> A<10> A<9> A<8> ++ A<7> A<6> A<5> A<4> A<3> A<2> A<1> A<0> Z<15> Z<14> Z<13> Z<12> Z<11> Z<10> ++ Z<9> Z<8> Z<7> Z<6> Z<5> Z<4> Z<3> Z<2> Z<1> Z<0> VDD VSS +XBUF<15> A<15> Z<15> VDD VSS / RSC_IHPSG13_WLDRVX12 +XBUF<14> A<14> Z<14> VDD VSS / RSC_IHPSG13_WLDRVX12 +XBUF<13> A<13> Z<13> VDD VSS / RSC_IHPSG13_WLDRVX12 +XBUF<12> A<12> Z<12> VDD VSS / RSC_IHPSG13_WLDRVX12 +XBUF<11> A<11> Z<11> VDD VSS / RSC_IHPSG13_WLDRVX12 +XBUF<10> A<10> Z<10> VDD VSS / RSC_IHPSG13_WLDRVX12 +XBUF<9> A<9> Z<9> VDD VSS / RSC_IHPSG13_WLDRVX12 +XBUF<8> A<8> Z<8> VDD VSS / RSC_IHPSG13_WLDRVX12 +XBUF<7> A<7> Z<7> VDD VSS / RSC_IHPSG13_WLDRVX12 +XBUF<6> A<6> Z<6> VDD VSS / RSC_IHPSG13_WLDRVX12 +XBUF<5> A<5> Z<5> VDD VSS / RSC_IHPSG13_WLDRVX12 +XBUF<4> A<4> Z<4> VDD VSS / RSC_IHPSG13_WLDRVX12 +XBUF<3> A<3> Z<3> VDD VSS / RSC_IHPSG13_WLDRVX12 +XBUF<2> A<2> Z<2> VDD VSS / RSC_IHPSG13_WLDRVX12 +XBUF<1> A<1> Z<1> VDD VSS / RSC_IHPSG13_WLDRVX12 +XBUF<0> A<0> Z<0> VDD VSS / RSC_IHPSG13_WLDRVX12 +.ENDS +.SUBCKT RM_IHPSG13_256x8_c2_2P_DEC04 ADDR<3> ADDR<2> ADDR<1> ADDR<0> CS ECLK_H_BOT ++ ECLK_H_TOP ECLK_L_BOT ECLK_L_TOP WL<15> WL<14> WL<13> WL<12> WL<11> WL<10> ++ WL<9> WL<8> WL<7> WL<6> WL<5> WL<4> WL<3> WL<2> WL<1> WL<0> VDD VSS +XI0<3> PADR<1> PADR<0> sel01<3> VDD VSS / RSC_IHPSG13_NAND2X2 +XI0<2> PADR<1> NADR<0> sel01<2> VDD VSS / RSC_IHPSG13_NAND2X2 +XI0<1> NADR<1> PADR<0> sel01<1> VDD VSS / RSC_IHPSG13_NAND2X2 +XI0<0> NADR<1> NADR<0> sel01<0> VDD VSS / RSC_IHPSG13_NAND2X2 +XI4 ECLK_L_BOT EN VDD VSS / RSC_IHPSG13_CINVX4 +XI5 ECLK_H_BOT ECLK_L_BOT VDD VSS / RSC_IHPSG13_CINVX2 +XI3<3> PADR<3> NADR<3> VDD VSS / RSC_IHPSG13_INVX2 +XI3<2> PADR<2> NADR<2> VDD VSS / RSC_IHPSG13_INVX2 +XI3<1> PADR<1> NADR<1> VDD VSS / RSC_IHPSG13_INVX2 +XI3<0> PADR<0> NADR<0> VDD VSS / RSC_IHPSG13_INVX2 +XR0 ECLK_H_BOT ECLK_H_TOP / RSC_IHPSG13_MET2RES +XI11 ECLK_L_BOT ECLK_L_TOP / RSC_IHPSG13_MET2RES +XI1<3> PADR<2> PADR<3> CS sel23<3> VDD VSS / RSC_IHPSG13_NAND3X2 +XI1<2> NADR<2> PADR<3> CS sel23<2> VDD VSS / RSC_IHPSG13_NAND3X2 +XI1<1> PADR<2> NADR<3> CS sel23<1> VDD VSS / RSC_IHPSG13_NAND3X2 +XI1<0> NADR<2> NADR<3> CS sel23<0> VDD VSS / RSC_IHPSG13_NAND3X2 +XI2<15> sel23<3> sel01<3> EN WL<15> VDD VSS / RSC_IHPSG13_NOR3X2 +XI2<14> sel23<3> sel01<2> EN WL<14> VDD VSS / RSC_IHPSG13_NOR3X2 +XI2<13> sel23<3> sel01<1> EN WL<13> VDD VSS / RSC_IHPSG13_NOR3X2 +XI2<12> sel23<3> sel01<0> EN WL<12> VDD VSS / RSC_IHPSG13_NOR3X2 +XI2<11> sel23<2> sel01<3> EN WL<11> VDD VSS / RSC_IHPSG13_NOR3X2 +XI2<10> sel23<2> sel01<2> EN WL<10> VDD VSS / RSC_IHPSG13_NOR3X2 +XI2<9> sel23<2> sel01<1> EN WL<9> VDD VSS / RSC_IHPSG13_NOR3X2 +XI2<8> sel23<2> sel01<0> EN WL<8> VDD VSS / RSC_IHPSG13_NOR3X2 +XI2<7> sel23<1> sel01<3> EN WL<7> VDD VSS / RSC_IHPSG13_NOR3X2 +XI2<6> sel23<1> sel01<2> EN WL<6> VDD VSS / RSC_IHPSG13_NOR3X2 +XI2<5> sel23<1> sel01<1> EN WL<5> VDD VSS / RSC_IHPSG13_NOR3X2 +XI2<4> sel23<1> sel01<0> EN WL<4> VDD VSS / RSC_IHPSG13_NOR3X2 +XI2<3> sel23<0> sel01<3> EN WL<3> VDD VSS / RSC_IHPSG13_NOR3X2 +XI2<2> sel23<0> sel01<2> EN WL<2> VDD VSS / RSC_IHPSG13_NOR3X2 +XI2<1> sel23<0> sel01<1> EN WL<1> VDD VSS / RSC_IHPSG13_NOR3X2 +XI2<0> sel23<0> sel01<0> EN WL<0> VDD VSS / RSC_IHPSG13_NOR3X2 +XCAPS4 VDD VSS / RSC_IHPSG13_FILLCAP4 +XLATCH<3> CS ADDR<3> PADR<3> VDD VSS / RSC_IHPSG13_LHPQX2 +XLATCH<2> CS ADDR<2> PADR<2> VDD VSS / RSC_IHPSG13_LHPQX2 +XLATCH<1> CS ADDR<1> PADR<1> VDD VSS / RSC_IHPSG13_LHPQX2 +XLATCH<0> CS ADDR<0> PADR<0> VDD VSS / RSC_IHPSG13_LHPQX2 +.ENDS +.SUBCKT RM_IHPSG13_256x8_c2_2P_DEC02 ADDR<1> ADDR<0> CS CS_OUT VDD VSS +XDEC ADDR<1> NADDR<0> CS net1 VDD VSS / RSC_IHPSG13_NAND3X2 +XADDRINV ADDR<0> NADDR<0> VDD VSS / RSC_IHPSG13_INVX2 +XDECINV net1 CS_OUT VDD VSS / RSC_IHPSG13_INVX4 +XI2<1> VDD VSS / RSC_IHPSG13_FILLCAP4 +XI2<0> VDD VSS / RSC_IHPSG13_FILLCAP4 +.ENDS +.SUBCKT RM_IHPSG13_256x8_c2_2P_DEC01 ADDR<1> ADDR<0> CS CS_OUT VDD VSS +XDEC NADDR<1> ADDR<0> CS net1 VDD VSS / RSC_IHPSG13_NAND3X2 +XADDRINV ADDR<1> NADDR<1> VDD VSS / RSC_IHPSG13_INVX2 +XDECINV net1 CS_OUT VDD VSS / RSC_IHPSG13_INVX4 +XI2<1> VDD VSS / RSC_IHPSG13_FILLCAP4 +XI2<0> VDD VSS / RSC_IHPSG13_FILLCAP4 +.ENDS +.SUBCKT RM_IHPSG13_256x8_c2_2P_DEC00 ADDR<1> ADDR<0> CS CS_OUT VDD VSS +XDEC NADDR<1> NADDR<0> CS net1 VDD VSS / RSC_IHPSG13_NAND3X2 +XADDRINV<1> ADDR<1> NADDR<1> VDD VSS / RSC_IHPSG13_INVX2 +XADDRINV<0> ADDR<0> NADDR<0> VDD VSS / RSC_IHPSG13_INVX2 +XI1<1> VDD VSS / RSC_IHPSG13_FILLCAP4 +XI1<0> VDD VSS / RSC_IHPSG13_FILLCAP4 +XDECINV net1 CS_OUT VDD VSS / RSC_IHPSG13_INVX4 +.ENDS +.SUBCKT RM_IHPSG13_256x8_c2_2P_DEC03 ADDR<1> ADDR<0> CS CS_OUT VDD VSS +XDEC ADDR<1> ADDR<0> CS net1 VDD VSS / RSC_IHPSG13_NAND3X2 +XDECINV net1 CS_OUT VDD VSS / RSC_IHPSG13_INVX4 +XI0<1> VDD VSS / RSC_IHPSG13_FILLCAP4 +XI0<0> VDD VSS / RSC_IHPSG13_FILLCAP4 +.ENDS +.SUBCKT RM_IHPSG13_256x8_c2_2P_ROWDEC9 ADDR_N_I<8> ADDR_N_I<7> ADDR_N_I<6> ADDR_N_I<5> ++ ADDR_N_I<4> ADDR_N_I<3> ADDR_N_I<2> ADDR_N_I<1> ADDR_N_I<0> CS_I ECLK_I ++ WL_O<511> WL_O<510> WL_O<509> WL_O<508> WL_O<507> WL_O<506> WL_O<505> ++ WL_O<504> WL_O<503> WL_O<502> WL_O<501> WL_O<500> WL_O<499> WL_O<498> ++ WL_O<497> WL_O<496> WL_O<495> WL_O<494> WL_O<493> WL_O<492> WL_O<491> ++ WL_O<490> WL_O<489> WL_O<488> WL_O<487> WL_O<486> WL_O<485> WL_O<484> ++ WL_O<483> WL_O<482> WL_O<481> WL_O<480> WL_O<479> WL_O<478> WL_O<477> ++ WL_O<476> WL_O<475> WL_O<474> WL_O<473> WL_O<472> WL_O<471> WL_O<470> ++ WL_O<469> WL_O<468> WL_O<467> WL_O<466> WL_O<465> WL_O<464> WL_O<463> ++ WL_O<462> WL_O<461> WL_O<460> WL_O<459> WL_O<458> WL_O<457> WL_O<456> ++ WL_O<455> WL_O<454> WL_O<453> WL_O<452> WL_O<451> WL_O<450> WL_O<449> ++ WL_O<448> WL_O<447> WL_O<446> WL_O<445> WL_O<444> WL_O<443> WL_O<442> ++ WL_O<441> WL_O<440> WL_O<439> WL_O<438> WL_O<437> WL_O<436> WL_O<435> ++ WL_O<434> WL_O<433> WL_O<432> WL_O<431> WL_O<430> WL_O<429> WL_O<428> ++ WL_O<427> WL_O<426> WL_O<425> WL_O<424> WL_O<423> WL_O<422> WL_O<421> ++ WL_O<420> WL_O<419> WL_O<418> WL_O<417> WL_O<416> WL_O<415> WL_O<414> ++ WL_O<413> WL_O<412> WL_O<411> WL_O<410> WL_O<409> WL_O<408> WL_O<407> ++ WL_O<406> WL_O<405> WL_O<404> WL_O<403> WL_O<402> WL_O<401> WL_O<400> ++ WL_O<399> WL_O<398> WL_O<397> WL_O<396> WL_O<395> WL_O<394> WL_O<393> ++ WL_O<392> WL_O<391> WL_O<390> WL_O<389> WL_O<388> WL_O<387> WL_O<386> ++ WL_O<385> WL_O<384> WL_O<383> WL_O<382> WL_O<381> WL_O<380> WL_O<379> ++ WL_O<378> WL_O<377> WL_O<376> WL_O<375> WL_O<374> WL_O<373> WL_O<372> ++ WL_O<371> WL_O<370> WL_O<369> WL_O<368> WL_O<367> WL_O<366> WL_O<365> ++ WL_O<364> WL_O<363> WL_O<362> WL_O<361> WL_O<360> WL_O<359> WL_O<358> ++ WL_O<357> WL_O<356> WL_O<355> WL_O<354> WL_O<353> WL_O<352> WL_O<351> ++ WL_O<350> WL_O<349> WL_O<348> WL_O<347> WL_O<346> WL_O<345> WL_O<344> ++ WL_O<343> WL_O<342> WL_O<341> WL_O<340> WL_O<339> WL_O<338> WL_O<337> ++ WL_O<336> WL_O<335> WL_O<334> WL_O<333> WL_O<332> WL_O<331> WL_O<330> ++ WL_O<329> WL_O<328> WL_O<327> WL_O<326> WL_O<325> WL_O<324> WL_O<323> ++ WL_O<322> WL_O<321> WL_O<320> WL_O<319> WL_O<318> WL_O<317> WL_O<316> ++ WL_O<315> WL_O<314> WL_O<313> WL_O<312> WL_O<311> WL_O<310> WL_O<309> ++ WL_O<308> WL_O<307> WL_O<306> WL_O<305> WL_O<304> WL_O<303> WL_O<302> ++ WL_O<301> WL_O<300> WL_O<299> WL_O<298> WL_O<297> WL_O<296> WL_O<295> ++ WL_O<294> WL_O<293> WL_O<292> WL_O<291> WL_O<290> WL_O<289> WL_O<288> ++ WL_O<287> WL_O<286> WL_O<285> WL_O<284> WL_O<283> WL_O<282> WL_O<281> ++ WL_O<280> WL_O<279> WL_O<278> WL_O<277> WL_O<276> WL_O<275> WL_O<274> ++ WL_O<273> WL_O<272> WL_O<271> WL_O<270> WL_O<269> WL_O<268> WL_O<267> ++ WL_O<266> WL_O<265> WL_O<264> WL_O<263> WL_O<262> WL_O<261> WL_O<260> ++ WL_O<259> WL_O<258> WL_O<257> WL_O<256> WL_O<255> WL_O<254> WL_O<253> ++ WL_O<252> WL_O<251> WL_O<250> WL_O<249> WL_O<248> WL_O<247> WL_O<246> ++ WL_O<245> WL_O<244> WL_O<243> WL_O<242> WL_O<241> WL_O<240> WL_O<239> ++ WL_O<238> WL_O<237> WL_O<236> WL_O<235> WL_O<234> WL_O<233> WL_O<232> ++ WL_O<231> WL_O<230> WL_O<229> WL_O<228> WL_O<227> WL_O<226> WL_O<225> ++ WL_O<224> WL_O<223> WL_O<222> WL_O<221> WL_O<220> WL_O<219> WL_O<218> ++ WL_O<217> WL_O<216> WL_O<215> WL_O<214> WL_O<213> WL_O<212> WL_O<211> ++ WL_O<210> WL_O<209> WL_O<208> WL_O<207> WL_O<206> WL_O<205> WL_O<204> ++ WL_O<203> WL_O<202> WL_O<201> WL_O<200> WL_O<199> WL_O<198> WL_O<197> ++ WL_O<196> WL_O<195> WL_O<194> WL_O<193> WL_O<192> WL_O<191> WL_O<190> ++ WL_O<189> WL_O<188> WL_O<187> WL_O<186> WL_O<185> WL_O<184> WL_O<183> ++ WL_O<182> WL_O<181> WL_O<180> WL_O<179> WL_O<178> WL_O<177> WL_O<176> ++ WL_O<175> WL_O<174> WL_O<173> WL_O<172> WL_O<171> WL_O<170> WL_O<169> ++ WL_O<168> WL_O<167> WL_O<166> WL_O<165> WL_O<164> WL_O<163> WL_O<162> ++ WL_O<161> WL_O<160> WL_O<159> WL_O<158> WL_O<157> WL_O<156> WL_O<155> ++ WL_O<154> WL_O<153> WL_O<152> WL_O<151> WL_O<150> WL_O<149> WL_O<148> ++ WL_O<147> WL_O<146> WL_O<145> WL_O<144> WL_O<143> WL_O<142> WL_O<141> ++ WL_O<140> WL_O<139> WL_O<138> WL_O<137> WL_O<136> WL_O<135> WL_O<134> ++ WL_O<133> WL_O<132> WL_O<131> WL_O<130> WL_O<129> WL_O<128> WL_O<127> ++ WL_O<126> WL_O<125> WL_O<124> WL_O<123> WL_O<122> WL_O<121> WL_O<120> ++ WL_O<119> WL_O<118> WL_O<117> WL_O<116> WL_O<115> WL_O<114> WL_O<113> ++ WL_O<112> WL_O<111> WL_O<110> WL_O<109> WL_O<108> WL_O<107> WL_O<106> ++ WL_O<105> WL_O<104> WL_O<103> WL_O<102> WL_O<101> WL_O<100> WL_O<99> ++ WL_O<98> WL_O<97> WL_O<96> WL_O<95> WL_O<94> WL_O<93> WL_O<92> WL_O<91> ++ WL_O<90> WL_O<89> WL_O<88> WL_O<87> WL_O<86> WL_O<85> WL_O<84> WL_O<83> ++ WL_O<82> WL_O<81> WL_O<80> WL_O<79> WL_O<78> WL_O<77> WL_O<76> WL_O<75> ++ WL_O<74> WL_O<73> WL_O<72> WL_O<71> WL_O<70> WL_O<69> WL_O<68> WL_O<67> ++ WL_O<66> WL_O<65> WL_O<64> WL_O<63> WL_O<62> WL_O<61> WL_O<60> WL_O<59> ++ WL_O<58> WL_O<57> WL_O<56> WL_O<55> WL_O<54> WL_O<53> WL_O<52> WL_O<51> ++ WL_O<50> WL_O<49> WL_O<48> WL_O<47> WL_O<46> WL_O<45> WL_O<44> WL_O<43> ++ WL_O<42> WL_O<41> WL_O<40> WL_O<39> WL_O<38> WL_O<37> WL_O<36> WL_O<35> ++ WL_O<34> WL_O<33> WL_O<32> WL_O<31> WL_O<30> WL_O<29> WL_O<28> WL_O<27> ++ WL_O<26> WL_O<25> WL_O<24> WL_O<23> WL_O<22> WL_O<21> WL_O<20> WL_O<19> ++ WL_O<18> WL_O<17> WL_O<16> WL_O<15> WL_O<14> WL_O<13> WL_O<12> WL_O<11> ++ WL_O<10> WL_O<9> WL_O<8> WL_O<7> WL_O<6> WL_O<5> WL_O<4> WL_O<3> WL_O<2> ++ WL_O<1> WL_O<0> VDD VSS +XSEL<31> ADDR_N_I<3> ADDR_N_I<2> ADDR_N_I<1> ADDR_N_I<0> CS00<31> ECLK_H<31> ++ ECLK_H<32> ECLK_B<31> ECLK_B<32> WL_O<511> WL_O<510> WL_O<509> WL_O<508> ++ WL_O<507> WL_O<506> WL_O<505> WL_O<504> WL_O<503> WL_O<502> WL_O<501> ++ WL_O<500> WL_O<499> WL_O<498> WL_O<497> WL_O<496> VDD VSS / ++ RM_IHPSG13_256x8_c2_2P_DEC04 +XSEL<30> ADDR_N_I<3> ADDR_N_I<2> ADDR_N_I<1> ADDR_N_I<0> CS00<30> ECLK_H<30> ++ ECLK_H<31> ECLK_B<30> ECLK_B<31> WL_O<495> WL_O<494> WL_O<493> WL_O<492> ++ WL_O<491> WL_O<490> WL_O<489> WL_O<488> WL_O<487> WL_O<486> WL_O<485> ++ WL_O<484> WL_O<483> WL_O<482> WL_O<481> WL_O<480> VDD VSS / ++ RM_IHPSG13_256x8_c2_2P_DEC04 +XSEL<29> ADDR_N_I<3> ADDR_N_I<2> ADDR_N_I<1> ADDR_N_I<0> CS00<29> ECLK_H<29> ++ ECLK_H<30> ECLK_B<29> ECLK_B<30> WL_O<479> WL_O<478> WL_O<477> WL_O<476> ++ WL_O<475> WL_O<474> WL_O<473> WL_O<472> WL_O<471> WL_O<470> WL_O<469> ++ WL_O<468> WL_O<467> WL_O<466> WL_O<465> WL_O<464> VDD VSS / ++ RM_IHPSG13_256x8_c2_2P_DEC04 +XSEL<28> ADDR_N_I<3> ADDR_N_I<2> ADDR_N_I<1> ADDR_N_I<0> CS00<28> ECLK_H<28> ++ ECLK_H<29> ECLK_B<28> ECLK_B<29> WL_O<463> WL_O<462> WL_O<461> WL_O<460> ++ WL_O<459> WL_O<458> WL_O<457> WL_O<456> WL_O<455> WL_O<454> WL_O<453> ++ WL_O<452> WL_O<451> WL_O<450> WL_O<449> WL_O<448> VDD VSS / ++ RM_IHPSG13_256x8_c2_2P_DEC04 +XSEL<27> ADDR_N_I<3> ADDR_N_I<2> ADDR_N_I<1> ADDR_N_I<0> CS00<27> ECLK_H<27> ++ ECLK_H<28> ECLK_B<27> ECLK_B<28> WL_O<447> WL_O<446> WL_O<445> WL_O<444> ++ WL_O<443> WL_O<442> WL_O<441> WL_O<440> WL_O<439> WL_O<438> WL_O<437> ++ WL_O<436> WL_O<435> WL_O<434> WL_O<433> WL_O<432> VDD VSS / ++ RM_IHPSG13_256x8_c2_2P_DEC04 +XSEL<26> ADDR_N_I<3> ADDR_N_I<2> ADDR_N_I<1> ADDR_N_I<0> CS00<26> ECLK_H<26> ++ ECLK_H<27> ECLK_B<26> ECLK_B<27> WL_O<431> WL_O<430> WL_O<429> WL_O<428> ++ WL_O<427> WL_O<426> WL_O<425> WL_O<424> WL_O<423> WL_O<422> WL_O<421> ++ WL_O<420> WL_O<419> WL_O<418> WL_O<417> WL_O<416> VDD VSS / ++ RM_IHPSG13_256x8_c2_2P_DEC04 +XSEL<25> ADDR_N_I<3> ADDR_N_I<2> ADDR_N_I<1> ADDR_N_I<0> CS00<25> ECLK_H<25> ++ ECLK_H<26> ECLK_B<25> ECLK_B<26> WL_O<415> WL_O<414> WL_O<413> WL_O<412> ++ WL_O<411> WL_O<410> WL_O<409> WL_O<408> WL_O<407> WL_O<406> WL_O<405> ++ WL_O<404> WL_O<403> WL_O<402> WL_O<401> WL_O<400> VDD VSS / ++ RM_IHPSG13_256x8_c2_2P_DEC04 +XSEL<24> ADDR_N_I<3> ADDR_N_I<2> ADDR_N_I<1> ADDR_N_I<0> CS00<24> ECLK_H<24> ++ ECLK_H<25> ECLK_B<24> ECLK_B<25> WL_O<399> WL_O<398> WL_O<397> WL_O<396> ++ WL_O<395> WL_O<394> WL_O<393> WL_O<392> WL_O<391> WL_O<390> WL_O<389> ++ WL_O<388> WL_O<387> WL_O<386> WL_O<385> WL_O<384> VDD VSS / ++ RM_IHPSG13_256x8_c2_2P_DEC04 +XSEL<23> ADDR_N_I<3> ADDR_N_I<2> ADDR_N_I<1> ADDR_N_I<0> CS00<23> ECLK_H<23> ++ ECLK_H<24> ECLK_B<23> ECLK_B<24> WL_O<383> WL_O<382> WL_O<381> WL_O<380> ++ WL_O<379> WL_O<378> WL_O<377> WL_O<376> WL_O<375> WL_O<374> WL_O<373> ++ WL_O<372> WL_O<371> WL_O<370> WL_O<369> WL_O<368> VDD VSS / ++ RM_IHPSG13_256x8_c2_2P_DEC04 +XSEL<22> ADDR_N_I<3> ADDR_N_I<2> ADDR_N_I<1> ADDR_N_I<0> CS00<22> ECLK_H<22> ++ ECLK_H<23> ECLK_B<22> ECLK_B<23> WL_O<367> WL_O<366> WL_O<365> WL_O<364> ++ WL_O<363> WL_O<362> WL_O<361> WL_O<360> WL_O<359> WL_O<358> WL_O<357> ++ WL_O<356> WL_O<355> WL_O<354> WL_O<353> WL_O<352> VDD VSS / ++ RM_IHPSG13_256x8_c2_2P_DEC04 +XSEL<21> ADDR_N_I<3> ADDR_N_I<2> ADDR_N_I<1> ADDR_N_I<0> CS00<21> ECLK_H<21> ++ ECLK_H<22> ECLK_B<21> ECLK_B<22> WL_O<351> WL_O<350> WL_O<349> WL_O<348> ++ WL_O<347> WL_O<346> WL_O<345> WL_O<344> WL_O<343> WL_O<342> WL_O<341> ++ WL_O<340> WL_O<339> WL_O<338> WL_O<337> WL_O<336> VDD VSS / ++ RM_IHPSG13_256x8_c2_2P_DEC04 +XSEL<20> ADDR_N_I<3> ADDR_N_I<2> ADDR_N_I<1> ADDR_N_I<0> CS00<20> ECLK_H<20> ++ ECLK_H<21> ECLK_B<20> ECLK_B<21> WL_O<335> WL_O<334> WL_O<333> WL_O<332> ++ WL_O<331> WL_O<330> WL_O<329> WL_O<328> WL_O<327> WL_O<326> WL_O<325> ++ WL_O<324> WL_O<323> WL_O<322> WL_O<321> WL_O<320> VDD VSS / ++ RM_IHPSG13_256x8_c2_2P_DEC04 +XSEL<19> ADDR_N_I<3> ADDR_N_I<2> ADDR_N_I<1> ADDR_N_I<0> CS00<19> ECLK_H<19> ++ ECLK_H<20> ECLK_B<19> ECLK_B<20> WL_O<319> WL_O<318> WL_O<317> WL_O<316> ++ WL_O<315> WL_O<314> WL_O<313> WL_O<312> WL_O<311> WL_O<310> WL_O<309> ++ WL_O<308> WL_O<307> WL_O<306> WL_O<305> WL_O<304> VDD VSS / ++ RM_IHPSG13_256x8_c2_2P_DEC04 +XSEL<18> ADDR_N_I<3> ADDR_N_I<2> ADDR_N_I<1> ADDR_N_I<0> CS00<18> ECLK_H<18> ++ ECLK_H<19> ECLK_B<18> ECLK_B<19> WL_O<303> WL_O<302> WL_O<301> WL_O<300> ++ WL_O<299> WL_O<298> WL_O<297> WL_O<296> WL_O<295> WL_O<294> WL_O<293> ++ WL_O<292> WL_O<291> WL_O<290> WL_O<289> WL_O<288> VDD VSS / ++ RM_IHPSG13_256x8_c2_2P_DEC04 +XSEL<17> ADDR_N_I<3> ADDR_N_I<2> ADDR_N_I<1> ADDR_N_I<0> CS00<17> ECLK_H<17> ++ ECLK_H<18> ECLK_B<17> ECLK_B<18> WL_O<287> WL_O<286> WL_O<285> WL_O<284> ++ WL_O<283> WL_O<282> WL_O<281> WL_O<280> WL_O<279> WL_O<278> WL_O<277> ++ WL_O<276> WL_O<275> WL_O<274> WL_O<273> WL_O<272> VDD VSS / ++ RM_IHPSG13_256x8_c2_2P_DEC04 +XSEL<16> ADDR_N_I<3> ADDR_N_I<2> ADDR_N_I<1> ADDR_N_I<0> CS00<16> ECLK_H<16> ++ ECLK_H<17> ECLK_B<16> ECLK_B<17> WL_O<271> WL_O<270> WL_O<269> WL_O<268> ++ WL_O<267> WL_O<266> WL_O<265> WL_O<264> WL_O<263> WL_O<262> WL_O<261> ++ WL_O<260> WL_O<259> WL_O<258> WL_O<257> WL_O<256> VDD VSS / ++ RM_IHPSG13_256x8_c2_2P_DEC04 +XSEL<15> ADDR_N_I<3> ADDR_N_I<2> ADDR_N_I<1> ADDR_N_I<0> CS00<15> ECLK_H<15> ++ ECLK_H<16> ECLK_B<15> ECLK_B<16> WL_O<255> WL_O<254> WL_O<253> WL_O<252> ++ WL_O<251> WL_O<250> WL_O<249> WL_O<248> WL_O<247> WL_O<246> WL_O<245> ++ WL_O<244> WL_O<243> WL_O<242> WL_O<241> WL_O<240> VDD VSS / ++ RM_IHPSG13_256x8_c2_2P_DEC04 +XSEL<14> ADDR_N_I<3> ADDR_N_I<2> ADDR_N_I<1> ADDR_N_I<0> CS00<14> ECLK_H<14> ++ ECLK_H<15> ECLK_B<14> ECLK_B<15> WL_O<239> WL_O<238> WL_O<237> WL_O<236> ++ WL_O<235> WL_O<234> WL_O<233> WL_O<232> WL_O<231> WL_O<230> WL_O<229> ++ WL_O<228> WL_O<227> WL_O<226> WL_O<225> WL_O<224> VDD VSS / ++ RM_IHPSG13_256x8_c2_2P_DEC04 +XSEL<13> ADDR_N_I<3> ADDR_N_I<2> ADDR_N_I<1> ADDR_N_I<0> CS00<13> ECLK_H<13> ++ ECLK_H<14> ECLK_B<13> ECLK_B<14> WL_O<223> WL_O<222> WL_O<221> WL_O<220> ++ WL_O<219> WL_O<218> WL_O<217> WL_O<216> WL_O<215> WL_O<214> WL_O<213> ++ WL_O<212> WL_O<211> WL_O<210> WL_O<209> WL_O<208> VDD VSS / ++ RM_IHPSG13_256x8_c2_2P_DEC04 +XSEL<12> ADDR_N_I<3> ADDR_N_I<2> ADDR_N_I<1> ADDR_N_I<0> CS00<12> ECLK_H<12> ++ ECLK_H<13> ECLK_B<12> ECLK_B<13> WL_O<207> WL_O<206> WL_O<205> WL_O<204> ++ WL_O<203> WL_O<202> WL_O<201> WL_O<200> WL_O<199> WL_O<198> WL_O<197> ++ WL_O<196> WL_O<195> WL_O<194> WL_O<193> WL_O<192> VDD VSS / ++ RM_IHPSG13_256x8_c2_2P_DEC04 +XSEL<11> ADDR_N_I<3> ADDR_N_I<2> ADDR_N_I<1> ADDR_N_I<0> CS00<11> ECLK_H<11> ++ ECLK_H<12> ECLK_B<11> ECLK_B<12> WL_O<191> WL_O<190> WL_O<189> WL_O<188> ++ WL_O<187> WL_O<186> WL_O<185> WL_O<184> WL_O<183> WL_O<182> WL_O<181> ++ WL_O<180> WL_O<179> WL_O<178> WL_O<177> WL_O<176> VDD VSS / ++ RM_IHPSG13_256x8_c2_2P_DEC04 +XSEL<10> ADDR_N_I<3> ADDR_N_I<2> ADDR_N_I<1> ADDR_N_I<0> CS00<10> ECLK_H<10> ++ ECLK_H<11> ECLK_B<10> ECLK_B<11> WL_O<175> WL_O<174> WL_O<173> WL_O<172> ++ WL_O<171> WL_O<170> WL_O<169> WL_O<168> WL_O<167> WL_O<166> WL_O<165> ++ WL_O<164> WL_O<163> WL_O<162> WL_O<161> WL_O<160> VDD VSS / ++ RM_IHPSG13_256x8_c2_2P_DEC04 +XSEL<9> ADDR_N_I<3> ADDR_N_I<2> ADDR_N_I<1> ADDR_N_I<0> CS00<9> ECLK_H<9> ++ ECLK_H<10> ECLK_B<9> ECLK_B<10> WL_O<159> WL_O<158> WL_O<157> WL_O<156> ++ WL_O<155> WL_O<154> WL_O<153> WL_O<152> WL_O<151> WL_O<150> WL_O<149> ++ WL_O<148> WL_O<147> WL_O<146> WL_O<145> WL_O<144> VDD VSS / ++ RM_IHPSG13_256x8_c2_2P_DEC04 +XSEL<8> ADDR_N_I<3> ADDR_N_I<2> ADDR_N_I<1> ADDR_N_I<0> CS00<8> ECLK_H<8> ++ ECLK_H<9> ECLK_B<8> ECLK_B<9> WL_O<143> WL_O<142> WL_O<141> WL_O<140> ++ WL_O<139> WL_O<138> WL_O<137> WL_O<136> WL_O<135> WL_O<134> WL_O<133> ++ WL_O<132> WL_O<131> WL_O<130> WL_O<129> WL_O<128> VDD VSS / ++ RM_IHPSG13_256x8_c2_2P_DEC04 +XSEL<7> ADDR_N_I<3> ADDR_N_I<2> ADDR_N_I<1> ADDR_N_I<0> CS00<7> ECLK_H<7> ++ ECLK_H<8> ECLK_B<7> ECLK_B<8> WL_O<127> WL_O<126> WL_O<125> WL_O<124> ++ WL_O<123> WL_O<122> WL_O<121> WL_O<120> WL_O<119> WL_O<118> WL_O<117> ++ WL_O<116> WL_O<115> WL_O<114> WL_O<113> WL_O<112> VDD VSS / ++ RM_IHPSG13_256x8_c2_2P_DEC04 +XSEL<6> ADDR_N_I<3> ADDR_N_I<2> ADDR_N_I<1> ADDR_N_I<0> CS00<6> ECLK_H<6> ++ ECLK_H<7> ECLK_B<6> ECLK_B<7> WL_O<111> WL_O<110> WL_O<109> WL_O<108> ++ WL_O<107> WL_O<106> WL_O<105> WL_O<104> WL_O<103> WL_O<102> WL_O<101> ++ WL_O<100> WL_O<99> WL_O<98> WL_O<97> WL_O<96> VDD VSS / ++ RM_IHPSG13_256x8_c2_2P_DEC04 +XSEL<5> ADDR_N_I<3> ADDR_N_I<2> ADDR_N_I<1> ADDR_N_I<0> CS00<5> ECLK_H<5> ++ ECLK_H<6> ECLK_B<5> ECLK_B<6> WL_O<95> WL_O<94> WL_O<93> WL_O<92> WL_O<91> ++ WL_O<90> WL_O<89> WL_O<88> WL_O<87> WL_O<86> WL_O<85> WL_O<84> WL_O<83> ++ WL_O<82> WL_O<81> WL_O<80> VDD VSS / RM_IHPSG13_256x8_c2_2P_DEC04 +XSEL<4> ADDR_N_I<3> ADDR_N_I<2> ADDR_N_I<1> ADDR_N_I<0> CS00<4> ECLK_H<4> ++ ECLK_H<5> ECLK_B<4> ECLK_B<5> WL_O<79> WL_O<78> WL_O<77> WL_O<76> WL_O<75> ++ WL_O<74> WL_O<73> WL_O<72> WL_O<71> WL_O<70> WL_O<69> WL_O<68> WL_O<67> ++ WL_O<66> WL_O<65> WL_O<64> VDD VSS / RM_IHPSG13_256x8_c2_2P_DEC04 +XSEL<3> ADDR_N_I<3> ADDR_N_I<2> ADDR_N_I<1> ADDR_N_I<0> CS00<3> ECLK_H<3> ++ ECLK_H<4> ECLK_B<3> ECLK_B<4> WL_O<63> WL_O<62> WL_O<61> WL_O<60> WL_O<59> ++ WL_O<58> WL_O<57> WL_O<56> WL_O<55> WL_O<54> WL_O<53> WL_O<52> WL_O<51> ++ WL_O<50> WL_O<49> WL_O<48> VDD VSS / RM_IHPSG13_256x8_c2_2P_DEC04 +XSEL<2> ADDR_N_I<3> ADDR_N_I<2> ADDR_N_I<1> ADDR_N_I<0> CS00<2> ECLK_H<2> ++ ECLK_H<3> ECLK_B<2> ECLK_B<3> WL_O<47> WL_O<46> WL_O<45> WL_O<44> WL_O<43> ++ WL_O<42> WL_O<41> WL_O<40> WL_O<39> WL_O<38> WL_O<37> WL_O<36> WL_O<35> ++ WL_O<34> WL_O<33> WL_O<32> VDD VSS / RM_IHPSG13_256x8_c2_2P_DEC04 +XSEL<1> ADDR_N_I<3> ADDR_N_I<2> ADDR_N_I<1> ADDR_N_I<0> CS00<1> ECLK_H<1> ++ ECLK_H<2> ECLK_B<1> ECLK_B<2> WL_O<31> WL_O<30> WL_O<29> WL_O<28> WL_O<27> ++ WL_O<26> WL_O<25> WL_O<24> WL_O<23> WL_O<22> WL_O<21> WL_O<20> WL_O<19> ++ WL_O<18> WL_O<17> WL_O<16> VDD VSS / RM_IHPSG13_256x8_c2_2P_DEC04 +XSEL<0> ADDR_N_I<3> ADDR_N_I<2> ADDR_N_I<1> ADDR_N_I<0> CS00<0> ECLK_I ++ ECLK_H<1> ECLK_B<0> ECLK_B<1> WL_O<15> WL_O<14> WL_O<13> WL_O<12> WL_O<11> ++ WL_O<10> WL_O<9> WL_O<8> WL_O<7> WL_O<6> WL_O<5> WL_O<4> WL_O<3> WL_O<2> ++ WL_O<1> WL_O<0> VDD VSS / RM_IHPSG13_256x8_c2_2P_DEC04 +XDEC10<9> ADDR_N_I<7> ADDR_N_I<6> CS04<1> CS02<6> VDD VSS / ++ RM_IHPSG13_256x8_c2_2P_DEC02 +XDEC10<8> ADDR_N_I<7> ADDR_N_I<6> CS04<0> CS02<2> VDD VSS / ++ RM_IHPSG13_256x8_c2_2P_DEC02 +XDEC10<7> ADDR_N_I<5> ADDR_N_I<4> CS02<7> CS00<30> VDD VSS / ++ RM_IHPSG13_256x8_c2_2P_DEC02 +XDEC10<6> ADDR_N_I<5> ADDR_N_I<4> CS02<6> CS00<26> VDD VSS / ++ RM_IHPSG13_256x8_c2_2P_DEC02 +XDEC10<5> ADDR_N_I<5> ADDR_N_I<4> CS02<5> CS00<22> VDD VSS / ++ RM_IHPSG13_256x8_c2_2P_DEC02 +XDEC10<4> ADDR_N_I<5> ADDR_N_I<4> CS02<4> CS00<18> VDD VSS / ++ RM_IHPSG13_256x8_c2_2P_DEC02 +XDEC10<3> ADDR_N_I<5> ADDR_N_I<4> CS02<3> CS00<14> VDD VSS / ++ RM_IHPSG13_256x8_c2_2P_DEC02 +XDEC10<2> ADDR_N_I<5> ADDR_N_I<4> CS02<2> CS00<10> VDD VSS / ++ RM_IHPSG13_256x8_c2_2P_DEC02 +XDEC10<1> ADDR_N_I<5> ADDR_N_I<4> CS02<1> CS00<6> VDD VSS / ++ RM_IHPSG13_256x8_c2_2P_DEC02 +XDEC10<0> ADDR_N_I<5> ADDR_N_I<4> CS02<0> CS00<2> VDD VSS / ++ RM_IHPSG13_256x8_c2_2P_DEC02 +XDEC01<10> ADDR_N_I<9> ADDR_N_I<8> CS_I CS04<1> VDD VSS / ++ RM_IHPSG13_256x8_c2_2P_DEC01 +XDEC01<9> ADDR_N_I<7> ADDR_N_I<6> CS04<1> CS02<5> VDD VSS / ++ RM_IHPSG13_256x8_c2_2P_DEC01 +XDEC01<8> ADDR_N_I<7> ADDR_N_I<6> CS04<0> CS02<1> VDD VSS / ++ RM_IHPSG13_256x8_c2_2P_DEC01 +XDEC01<7> ADDR_N_I<5> ADDR_N_I<4> CS02<7> CS00<29> VDD VSS / ++ RM_IHPSG13_256x8_c2_2P_DEC01 +XDEC01<6> ADDR_N_I<5> ADDR_N_I<4> CS02<6> CS00<25> VDD VSS / ++ RM_IHPSG13_256x8_c2_2P_DEC01 +XDEC01<5> ADDR_N_I<5> ADDR_N_I<4> CS02<5> CS00<21> VDD VSS / ++ RM_IHPSG13_256x8_c2_2P_DEC01 +XDEC01<4> ADDR_N_I<5> ADDR_N_I<4> CS02<4> CS00<17> VDD VSS / ++ RM_IHPSG13_256x8_c2_2P_DEC01 +XDEC01<3> ADDR_N_I<5> ADDR_N_I<4> CS02<3> CS00<13> VDD VSS / ++ RM_IHPSG13_256x8_c2_2P_DEC01 +XDEC01<2> ADDR_N_I<5> ADDR_N_I<4> CS02<2> CS00<9> VDD VSS / ++ RM_IHPSG13_256x8_c2_2P_DEC01 +XDEC01<1> ADDR_N_I<5> ADDR_N_I<4> CS02<1> CS00<5> VDD VSS / ++ RM_IHPSG13_256x8_c2_2P_DEC01 +XDEC01<0> ADDR_N_I<5> ADDR_N_I<4> CS02<0> CS00<1> VDD VSS / ++ RM_IHPSG13_256x8_c2_2P_DEC01 +XL2<258> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<257> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<256> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<255> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<254> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<253> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<252> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<251> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<250> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<249> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<248> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<247> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<246> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<245> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<244> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<243> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<242> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<241> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<240> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<239> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<238> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<237> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<236> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<235> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<234> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<233> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<232> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<231> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<230> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<229> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<228> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<227> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<226> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<225> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<224> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<223> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<222> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<221> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<220> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<219> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<218> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<217> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<216> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<215> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<214> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<213> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<212> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<211> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<210> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<209> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<208> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<207> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<206> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<205> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<204> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<203> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<202> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<201> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<200> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<199> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<198> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<197> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<196> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<195> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<194> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<193> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<192> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<191> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<190> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<189> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<188> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<187> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<186> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<185> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<184> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<183> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<182> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<181> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<180> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<179> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<178> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<177> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<176> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<175> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<174> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<173> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<172> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<171> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<170> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<169> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<168> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<167> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<166> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<165> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<164> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<163> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<162> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<161> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<160> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<159> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<158> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<157> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<156> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<155> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<154> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<153> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<152> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<151> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<150> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<149> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<148> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<147> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<146> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<145> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<144> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<143> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<142> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<141> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<140> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<139> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<138> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<137> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<136> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<135> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<134> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<133> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<132> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<131> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<130> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<129> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<128> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<127> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<126> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<125> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<124> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<123> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<122> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<121> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<120> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<119> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<118> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<117> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<116> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<115> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<114> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<113> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<112> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<111> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<110> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<109> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<108> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<107> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<106> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<105> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<104> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<103> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<102> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<101> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<100> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<99> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<98> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<97> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<96> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<95> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<94> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<93> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<92> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<91> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<90> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<89> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<88> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<87> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<86> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<85> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<84> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<83> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<82> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<81> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<80> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<79> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<78> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<77> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<76> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<75> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<74> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<73> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<72> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<71> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<70> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<69> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<68> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<67> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<66> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<65> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<64> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<63> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<62> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<61> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<60> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<59> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<58> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<57> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<56> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<55> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<54> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<53> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<52> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<51> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<50> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<49> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<48> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<47> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<46> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<45> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<44> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<43> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<42> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<41> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<40> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<39> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<38> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<37> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<36> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<35> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<34> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<33> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<32> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<31> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<30> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<29> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<28> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<27> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<26> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<25> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<24> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<23> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<22> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<21> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<20> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<19> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<18> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<17> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<16> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<15> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<14> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<13> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<12> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<11> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<10> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<9> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<8> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<7> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<6> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<5> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<4> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<3> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<2> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<1> VDD VSS / RSC_IHPSG13_FILLCAP8 +XDEC00<10> ADDR_N_I<9> ADDR_N_I<8> CS_I CS04<0> VDD VSS / ++ RM_IHPSG13_256x8_c2_2P_DEC00 +XDEC00<9> ADDR_N_I<7> ADDR_N_I<6> CS04<1> CS02<4> VDD VSS / ++ RM_IHPSG13_256x8_c2_2P_DEC00 +XDEC00<8> ADDR_N_I<7> ADDR_N_I<6> CS04<0> CS02<0> VDD VSS / ++ RM_IHPSG13_256x8_c2_2P_DEC00 +XDEC00<7> ADDR_N_I<5> ADDR_N_I<4> CS02<7> CS00<28> VDD VSS / ++ RM_IHPSG13_256x8_c2_2P_DEC00 +XDEC00<6> ADDR_N_I<5> ADDR_N_I<4> CS02<6> CS00<24> VDD VSS / ++ RM_IHPSG13_256x8_c2_2P_DEC00 +XDEC00<5> ADDR_N_I<5> ADDR_N_I<4> CS02<5> CS00<20> VDD VSS / ++ RM_IHPSG13_256x8_c2_2P_DEC00 +XDEC00<4> ADDR_N_I<5> ADDR_N_I<4> CS02<4> CS00<16> VDD VSS / ++ RM_IHPSG13_256x8_c2_2P_DEC00 +XDEC00<3> ADDR_N_I<5> ADDR_N_I<4> CS02<3> CS00<12> VDD VSS / ++ RM_IHPSG13_256x8_c2_2P_DEC00 +XDEC00<2> ADDR_N_I<5> ADDR_N_I<4> CS02<2> CS00<8> VDD VSS / ++ RM_IHPSG13_256x8_c2_2P_DEC00 +XDEC00<1> ADDR_N_I<5> ADDR_N_I<4> CS02<1> CS00<4> VDD VSS / ++ RM_IHPSG13_256x8_c2_2P_DEC00 +XDEC00<0> ADDR_N_I<5> ADDR_N_I<4> CS02<0> CS00<0> VDD VSS / ++ RM_IHPSG13_256x8_c2_2P_DEC00 +XDEC11<9> ADDR_N_I<7> ADDR_N_I<6> CS04<1> CS02<7> VDD VSS / ++ RM_IHPSG13_256x8_c2_2P_DEC03 +XDEC11<8> ADDR_N_I<7> ADDR_N_I<6> CS04<0> CS02<3> VDD VSS / ++ RM_IHPSG13_256x8_c2_2P_DEC03 +XDEC11<7> ADDR_N_I<5> ADDR_N_I<4> CS02<7> CS00<31> VDD VSS / ++ RM_IHPSG13_256x8_c2_2P_DEC03 +XDEC11<6> ADDR_N_I<5> ADDR_N_I<4> CS02<6> CS00<27> VDD VSS / ++ RM_IHPSG13_256x8_c2_2P_DEC03 +XDEC11<5> ADDR_N_I<5> ADDR_N_I<4> CS02<5> CS00<23> VDD VSS / ++ RM_IHPSG13_256x8_c2_2P_DEC03 +XDEC11<4> ADDR_N_I<5> ADDR_N_I<4> CS02<4> CS00<19> VDD VSS / ++ RM_IHPSG13_256x8_c2_2P_DEC03 +XDEC11<3> ADDR_N_I<5> ADDR_N_I<4> CS02<3> CS00<15> VDD VSS / ++ RM_IHPSG13_256x8_c2_2P_DEC03 +XDEC11<2> ADDR_N_I<5> ADDR_N_I<4> CS02<2> CS00<11> VDD VSS / ++ RM_IHPSG13_256x8_c2_2P_DEC03 +XDEC11<1> ADDR_N_I<5> ADDR_N_I<4> CS02<1> CS00<7> VDD VSS / ++ RM_IHPSG13_256x8_c2_2P_DEC03 +XDEC11<0> ADDR_N_I<5> ADDR_N_I<4> CS02<0> CS00<3> VDD VSS / ++ RM_IHPSG13_256x8_c2_2P_DEC03 +XI0 ADDR_N_I<9> VDD VSS / RSC_IHPSG13_TIEL +.ENDS +.SUBCKT RM_IHPSG13_256x8_c2_2P_ROWREG9 ACLK_N_I ADDR_I<8> ADDR_I<7> ADDR_I<6> ADDR_I<5> ++ ADDR_I<4> ADDR_I<3> ADDR_I<2> ADDR_I<1> ADDR_I<0> ADDR_N_O<8> ADDR_N_O<7> ++ ADDR_N_O<6> ADDR_N_O<5> ADDR_N_O<4> ADDR_N_O<3> ADDR_N_O<2> ADDR_N_O<1> ++ ADDR_N_O<0> BIST_ADDR_I<8> BIST_ADDR_I<7> BIST_ADDR_I<6> BIST_ADDR_I<5> ++ BIST_ADDR_I<4> BIST_ADDR_I<3> BIST_ADDR_I<2> BIST_ADDR_I<1> BIST_ADDR_I<0> ++ BIST_EN_I VDD VSS +XDFF<8> BIST_EN_I BIST_ADDR_I<8> ACLK_N_I ADDR_I<8> q_int<8> net04<0> VDD ++ VSS / RSC_IHPSG13_DFNQMX2IX1 +XDFF<7> BIST_EN_I BIST_ADDR_I<7> ACLK_N_I ADDR_I<7> q_int<7> net04<1> VDD ++ VSS / RSC_IHPSG13_DFNQMX2IX1 +XDFF<6> BIST_EN_I BIST_ADDR_I<6> ACLK_N_I ADDR_I<6> q_int<6> net04<2> VDD ++ VSS / RSC_IHPSG13_DFNQMX2IX1 +XDFF<5> BIST_EN_I BIST_ADDR_I<5> ACLK_N_I ADDR_I<5> q_int<5> net04<3> VDD ++ VSS / RSC_IHPSG13_DFNQMX2IX1 +XDFF<4> BIST_EN_I BIST_ADDR_I<4> ACLK_N_I ADDR_I<4> q_int<4> net04<4> VDD ++ VSS / RSC_IHPSG13_DFNQMX2IX1 +XDFF<3> BIST_EN_I BIST_ADDR_I<3> ACLK_N_I ADDR_I<3> q_int<3> net04<5> VDD ++ VSS / RSC_IHPSG13_DFNQMX2IX1 +XDFF<2> BIST_EN_I BIST_ADDR_I<2> ACLK_N_I ADDR_I<2> q_int<2> net04<6> VDD ++ VSS / RSC_IHPSG13_DFNQMX2IX1 +XDFF<1> BIST_EN_I BIST_ADDR_I<1> ACLK_N_I ADDR_I<1> q_int<1> net04<7> VDD ++ VSS / RSC_IHPSG13_DFNQMX2IX1 +XDFF<0> BIST_EN_I BIST_ADDR_I<0> ACLK_N_I ADDR_I<0> q_int<0> net04<8> VDD ++ VSS / RSC_IHPSG13_DFNQMX2IX1 +XDRV<8> qn_int<8> ADDR_N_O<8> VDD VSS / RSC_IHPSG13_CINVX8 +XDRV<7> qn_int<7> ADDR_N_O<7> VDD VSS / RSC_IHPSG13_CINVX8 +XDRV<6> qn_int<6> ADDR_N_O<6> VDD VSS / RSC_IHPSG13_CINVX8 +XDRV<5> qn_int<5> ADDR_N_O<5> VDD VSS / RSC_IHPSG13_CINVX8 +XDRV<4> qn_int<4> ADDR_N_O<4> VDD VSS / RSC_IHPSG13_CINVX8 +XDRV<3> qn_int<3> ADDR_N_O<3> VDD VSS / RSC_IHPSG13_CINVX8 +XDRV<2> qn_int<2> ADDR_N_O<2> VDD VSS / RSC_IHPSG13_CINVX8 +XDRV<1> qn_int<1> ADDR_N_O<1> VDD VSS / RSC_IHPSG13_CINVX8 +XDRV<0> qn_int<0> ADDR_N_O<0> VDD VSS / RSC_IHPSG13_CINVX8 +XINV<8> q_int<8> qn_int<8> VDD VSS / RSC_IHPSG13_CINVX2 +XINV<7> q_int<7> qn_int<7> VDD VSS / RSC_IHPSG13_CINVX2 +XINV<6> q_int<6> qn_int<6> VDD VSS / RSC_IHPSG13_CINVX2 +XINV<5> q_int<5> qn_int<5> VDD VSS / RSC_IHPSG13_CINVX2 +XINV<4> q_int<4> qn_int<4> VDD VSS / RSC_IHPSG13_CINVX2 +XINV<3> q_int<3> qn_int<3> VDD VSS / RSC_IHPSG13_CINVX2 +XINV<2> q_int<2> qn_int<2> VDD VSS / RSC_IHPSG13_CINVX2 +XINV<1> q_int<1> qn_int<1> VDD VSS / RSC_IHPSG13_CINVX2 +XINV<0> q_int<0> qn_int<0> VDD VSS / RSC_IHPSG13_CINVX2 +.ENDS + +.SUBCKT RM_IHPSG13_256x8_c2_2P_DLY_MUX A SEL Z VDD VSS +XI11 net4 Z VDD VSS / RSC_IHPSG13_CINVX2 +XI8 A D<3> SEL net4 VDD VSS / RSC_IHPSG13_MX2IX1 +XI20<3> D<2> D<3> VDD VSS / RSC_IHPSG13_CDLYX1 +XI20<2> D<1> D<2> VDD VSS / RSC_IHPSG13_CDLYX1 +XI20<1> A D<1> VDD VSS / RSC_IHPSG13_CDLYX1 +.ENDS +.SUBCKT RM_IHPSG13_256x8_c2_2P_CTRL ACLK_N BIST_CK_I BIST_CS_I BIST_EN BIST_RE_I ++ BIST_WE_I B_TIEL_O CK_I CS_I DCLK ECLK PULSE_H PULSE_L PULSE_O RCLK RE_I ++ ROW_CS WCLK WE_I VDD VSS +XI17 ck_regs we col_we VDD VSS / RSC_IHPSG13_DFNQX2 +XI16 ck_regs re col_re VDD VSS / RSC_IHPSG13_DFNQX2 +XI18 ck_regs cs net7 VDD VSS / RSC_IHPSG13_DFNQX2 +XI71 ACLK_N net012 PULSE_O VDD VSS / RSC_IHPSG13_DFNQX2 +XI77 col_we net017 net016 VDD VSS / RSC_IHPSG13_CNAND2X2 +XI76 col_re net017 net018 VDD VSS / RSC_IHPSG13_CNAND2X2 +XI15 ck_dly WEorREandCS aclk VDD VSS / RSC_IHPSG13_CGATEPX4 +XI14 ck WEandCS DCLK VDD VSS / RSC_IHPSG13_CGATEPX4 +XI60 net7 ROW_CS VDD VSS / RSC_IHPSG13_CBUFX8 +XI73 PULSE_O net012 VDD VSS / RSC_IHPSG13_CINVX2 +XI8 net017 net8 VDD VSS / RSC_IHPSG13_CINVX2 +XCAPS4<7> VDD VSS / RSC_IHPSG13_FILLCAP4 +XCAPS4<6> VDD VSS / RSC_IHPSG13_FILLCAP4 +XCAPS4<5> VDD VSS / RSC_IHPSG13_FILLCAP4 +XCAPS4<4> VDD VSS / RSC_IHPSG13_FILLCAP4 +XCAPS4<3> VDD VSS / RSC_IHPSG13_FILLCAP4 +XCAPS4<2> VDD VSS / RSC_IHPSG13_FILLCAP4 +XCAPS4<1> VDD VSS / RSC_IHPSG13_FILLCAP4 +XBM_TIEL B_TIEL_O VDD VSS / RSC_IHPSG13_TIEL +XI64 ck ck_dly VDD VSS / RSC_IHPSG13_CDLYX2 +XI86 CS_I BIST_CS_I BIST_EN cs VDD VSS / RSC_IHPSG13_MX2X2 +XI87 CK_I BIST_CK_I BIST_EN ck VDD VSS / RSC_IHPSG13_MX2X2 +XI85 WE_I BIST_WE_I BIST_EN we VDD VSS / RSC_IHPSG13_MX2X2 +XI84 RE_I BIST_RE_I BIST_EN re VDD VSS / RSC_IHPSG13_MX2X2 +XI48 ck_dly ck_regs VDD VSS / RSC_IHPSG13_CINVX4 +XI81 net016 WCLK VDD VSS / RSC_IHPSG13_CINVX4 +XI80 net018 RCLK VDD VSS / RSC_IHPSG13_CINVX4 +XI78 net8 net020 VDD VSS / RSC_IHPSG13_CINVX4 +XCAPS8<7> VDD VSS / RSC_IHPSG13_FILLCAP8 +XCAPS8<6> VDD VSS / RSC_IHPSG13_FILLCAP8 +XCAPS8<5> VDD VSS / RSC_IHPSG13_FILLCAP8 +XCAPS8<4> VDD VSS / RSC_IHPSG13_FILLCAP8 +XCAPS8<3> VDD VSS / RSC_IHPSG13_FILLCAP8 +XCAPS8<2> VDD VSS / RSC_IHPSG13_FILLCAP8 +XCAPS8<1> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI6 PULSE_L PULSE_H net017 VDD VSS / RSC_IHPSG13_XOR2X2 +XI22 we cs WEandCS VDD VSS / RSC_IHPSG13_AND2X2 +XI79 net020 ECLK VDD VSS / RSC_IHPSG13_CINVX8 +XI63 aclk ACLK_N VDD VSS / RSC_IHPSG13_CINVX8 +XI21 re we cs WEorREandCS VDD VSS / RSC_IHPSG13_OA12X1 +.ENDS +.SUBCKT RM_IHPSG13_256x8_c2_2P_COLDEC5 ACLK_N ADDR<4> ADDR<3> ADDR<2> ADDR<1> ADDR<0> ++ ADDR_COL<1> ADDR_COL<0> ADDR_DEC<7> ADDR_DEC<6> ADDR_DEC<5> ADDR_DEC<4> ++ ADDR_DEC<3> ADDR_DEC<2> ADDR_DEC<1> ADDR_DEC<0> BIST_ADDR<4> BIST_ADDR<3> ++ BIST_ADDR<2> BIST_ADDR<1> BIST_ADDR<0> BIST_EN_I VDD VSS +XI17<4> VDD VSS / RSC_IHPSG13_FILLCAP4 +XI17<3> VDD VSS / RSC_IHPSG13_FILLCAP4 +XI17<2> VDD VSS / RSC_IHPSG13_FILLCAP4 +XI17<1> VDD VSS / RSC_IHPSG13_FILLCAP4 +XI1<7> PADR<0> PADR<1> PADR<2> addr_n<7> VDD VSS / RSC_IHPSG13_NAND3X2 +XI1<6> NADR<0> PADR<1> PADR<2> addr_n<6> VDD VSS / RSC_IHPSG13_NAND3X2 +XI1<5> PADR<0> NADR<1> PADR<2> addr_n<5> VDD VSS / RSC_IHPSG13_NAND3X2 +XI1<4> NADR<0> NADR<1> PADR<2> addr_n<4> VDD VSS / RSC_IHPSG13_NAND3X2 +XI1<3> PADR<0> PADR<1> NADR<2> addr_n<3> VDD VSS / RSC_IHPSG13_NAND3X2 +XI1<2> NADR<0> PADR<1> NADR<2> addr_n<2> VDD VSS / RSC_IHPSG13_NAND3X2 +XI1<1> PADR<0> NADR<1> NADR<2> addr_n<1> VDD VSS / RSC_IHPSG13_NAND3X2 +XI1<0> NADR<0> NADR<1> NADR<2> addr_n<0> VDD VSS / RSC_IHPSG13_NAND3X2 +XDFF<4> BIST_EN_I BIST_ADDR<4> ACLK_N ADDR<4> addr_int<1> net13<0> VDD ++ VSS / RSC_IHPSG13_DFNQMX2IX1 +XDFF<3> BIST_EN_I BIST_ADDR<3> ACLK_N ADDR<3> addr_int<0> net13<1> VDD ++ VSS / RSC_IHPSG13_DFNQMX2IX1 +XDFF<2> BIST_EN_I BIST_ADDR<2> ACLK_N ADDR<2> padr_int<2> net13<2> VDD ++ VSS / RSC_IHPSG13_DFNQMX2IX1 +XDFF<1> BIST_EN_I BIST_ADDR<1> ACLK_N ADDR<1> padr_int<1> net13<3> VDD ++ VSS / RSC_IHPSG13_DFNQMX2IX1 +XDFF<0> BIST_EN_I BIST_ADDR<0> ACLK_N ADDR<0> padr_int<0> net13<4> VDD ++ VSS / RSC_IHPSG13_DFNQMX2IX1 +XI3<2> padr_int<2> NADR<2> VDD VSS / RSC_IHPSG13_INVX2 +XI3<1> padr_int<1> NADR<1> VDD VSS / RSC_IHPSG13_INVX2 +XI3<0> padr_int<0> NADR<0> VDD VSS / RSC_IHPSG13_INVX2 +XI2<7> addr_n<7> ADDR_DEC<7> VDD VSS / RSC_IHPSG13_INVX2 +XI2<6> addr_n<6> ADDR_DEC<6> VDD VSS / RSC_IHPSG13_INVX2 +XI2<5> addr_n<5> ADDR_DEC<5> VDD VSS / RSC_IHPSG13_INVX2 +XI2<4> addr_n<4> ADDR_DEC<4> VDD VSS / RSC_IHPSG13_INVX2 +XI2<3> addr_n<3> ADDR_DEC<3> VDD VSS / RSC_IHPSG13_INVX2 +XI2<2> addr_n<2> ADDR_DEC<2> VDD VSS / RSC_IHPSG13_INVX2 +XI2<1> addr_n<1> ADDR_DEC<1> VDD VSS / RSC_IHPSG13_INVX2 +XI2<0> addr_n<0> ADDR_DEC<0> VDD VSS / RSC_IHPSG13_INVX2 +XI15<2> NADR<2> PADR<2> VDD VSS / RSC_IHPSG13_INVX2 +XI15<1> NADR<1> PADR<1> VDD VSS / RSC_IHPSG13_INVX2 +XI15<0> NADR<0> PADR<0> VDD VSS / RSC_IHPSG13_INVX2 +XI13<1> addr_int<1> ADDR_COL<1> VDD VSS / RSC_IHPSG13_CBUFX2 +XI13<0> addr_int<0> ADDR_COL<0> VDD VSS / RSC_IHPSG13_CBUFX2 +XI14<5> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI14<4> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI14<3> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI14<2> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI14<1> VDD VSS / RSC_IHPSG13_FILLCAP8 +.ENDS +.SUBCKT RM_IHPSG13_256x8_c2_2P_BLDRV A_BLC<3> A_BLC<2> A_BLC<1> A_BLC<0> A_BLC_SEL ++ A_BLT<3> A_BLT<2> A_BLT<1> A_BLT<0> A_BLT_SEL A_PRE_N A_SEL_P<3> A_SEL_P<2> ++ A_SEL_P<1> A_SEL_P<0> A_WR_ONE A_WR_ZERO B_BLC<3> B_BLC<2> B_BLC<1> B_BLC<0> ++ B_BLC_SEL B_BLT<3> B_BLT<2> B_BLT<1> B_BLT<0> B_BLT_SEL B_PRE_N B_SEL_P<3> ++ B_SEL_P<2> B_SEL_P<1> B_SEL_P<0> B_WR_ONE B_WR_ZERO VDD VSS +MA_CWN<3> A_BLC<3> A_BLC_NMOS_DRIVE<3> VSS VSS sg13_lv_nmos m=1 ++ w=4.82u l=130.00n ng=2 nrd=0 nrs=0 +MA_CWN<2> A_BLC<2> A_BLC_NMOS_DRIVE<2> VSS VSS sg13_lv_nmos m=1 ++ w=4.82u l=130.00n ng=2 nrd=0 nrs=0 +MA_CWN<1> A_BLC<1> A_BLC_NMOS_DRIVE<1> VSS VSS sg13_lv_nmos m=1 ++ w=4.82u l=130.00n ng=2 nrd=0 nrs=0 +MA_CWN<0> A_BLC<0> A_BLC_NMOS_DRIVE<0> VSS VSS sg13_lv_nmos m=1 ++ w=4.82u l=130.00n ng=2 nrd=0 nrs=0 +MA_TWN<3> A_BLT<3> A_BLT_NMOS_DRIVE<3> VSS VSS sg13_lv_nmos m=1 ++ w=4.82u l=130.00n ng=2 nrd=0 nrs=0 +MA_TWN<2> A_BLT<2> A_BLT_NMOS_DRIVE<2> VSS VSS sg13_lv_nmos m=1 ++ w=4.82u l=130.00n ng=2 nrd=0 nrs=0 +MA_TWN<1> A_BLT<1> A_BLT_NMOS_DRIVE<1> VSS VSS sg13_lv_nmos m=1 ++ w=4.82u l=130.00n ng=2 nrd=0 nrs=0 +MA_TWN<0> A_BLT<0> A_BLT_NMOS_DRIVE<0> VSS VSS sg13_lv_nmos m=1 ++ w=4.82u l=130.00n ng=2 nrd=0 nrs=0 +MB_TWN<3> B_BLT<3> B_BLT_NMOS_DRIVE<3> VSS VSS sg13_lv_nmos m=1 ++ w=4.82u l=130.00n ng=2 nrd=0 nrs=0 +MB_TWN<2> B_BLT<2> B_BLT_NMOS_DRIVE<2> VSS VSS sg13_lv_nmos m=1 ++ w=4.82u l=130.00n ng=2 nrd=0 nrs=0 +MB_TWN<1> B_BLT<1> B_BLT_NMOS_DRIVE<1> VSS VSS sg13_lv_nmos m=1 ++ w=4.82u l=130.00n ng=2 nrd=0 nrs=0 +MB_TWN<0> B_BLT<0> B_BLT_NMOS_DRIVE<0> VSS VSS sg13_lv_nmos m=1 ++ w=4.82u l=130.00n ng=2 nrd=0 nrs=0 +MB_CWN<3> B_BLC<3> B_BLC_NMOS_DRIVE<3> VSS VSS sg13_lv_nmos m=1 ++ w=4.82u l=130.00n ng=2 nrd=0 nrs=0 +MB_CWN<2> B_BLC<2> B_BLC_NMOS_DRIVE<2> VSS VSS sg13_lv_nmos m=1 ++ w=4.82u l=130.00n ng=2 nrd=0 nrs=0 +MB_CWN<1> B_BLC<1> B_BLC_NMOS_DRIVE<1> VSS VSS sg13_lv_nmos m=1 ++ w=4.82u l=130.00n ng=2 nrd=0 nrs=0 +MB_CWN<0> B_BLC<0> B_BLC_NMOS_DRIVE<0> VSS VSS sg13_lv_nmos m=1 ++ w=4.82u l=130.00n ng=2 nrd=0 nrs=0 +MA_CPR<3> A_BLC<3> A_PRE_N VDD VDD sg13_lv_pmos m=1 w=3.000u l=130.00n ++ ng=2 nrd=0 nrs=0 +MA_CPR<2> A_BLC<2> A_PRE_N VDD VDD sg13_lv_pmos m=1 w=3.000u l=130.00n ++ ng=2 nrd=0 nrs=0 +MA_CPR<1> A_BLC<1> A_PRE_N VDD VDD sg13_lv_pmos m=1 w=3.000u l=130.00n ++ ng=2 nrd=0 nrs=0 +MA_CPR<0> A_BLC<0> A_PRE_N VDD VDD sg13_lv_pmos m=1 w=3.000u l=130.00n ++ ng=2 nrd=0 nrs=0 +MA_TWP<3> A_BLT<3> A_BLT_PMOS_DRIVE<3> VDD VDD sg13_lv_pmos m=1 w=1.5u ++ l=130.00n ng=1 nrd=0 nrs=0 +MA_TWP<2> A_BLT<2> A_BLT_PMOS_DRIVE<2> VDD VDD sg13_lv_pmos m=1 w=1.5u ++ l=130.00n ng=1 nrd=0 nrs=0 +MA_TWP<1> A_BLT<1> A_BLT_PMOS_DRIVE<1> VDD VDD sg13_lv_pmos m=1 w=1.5u ++ l=130.00n ng=1 nrd=0 nrs=0 +MA_TWP<0> A_BLT<0> A_BLT_PMOS_DRIVE<0> VDD VDD sg13_lv_pmos m=1 w=1.5u ++ l=130.00n ng=1 nrd=0 nrs=0 +MA_CWP<3> A_BLC<3> A_BLC_PMOS_DRIVE<3> VDD VDD sg13_lv_pmos m=1 w=1.5u ++ l=130.00n ng=1 nrd=0 nrs=0 +MA_CWP<2> A_BLC<2> A_BLC_PMOS_DRIVE<2> VDD VDD sg13_lv_pmos m=1 w=1.5u ++ l=130.00n ng=1 nrd=0 nrs=0 +MA_CWP<1> A_BLC<1> A_BLC_PMOS_DRIVE<1> VDD VDD sg13_lv_pmos m=1 w=1.5u ++ l=130.00n ng=1 nrd=0 nrs=0 +MA_CWP<0> A_BLC<0> A_BLC_PMOS_DRIVE<0> VDD VDD sg13_lv_pmos m=1 w=1.5u ++ l=130.00n ng=1 nrd=0 nrs=0 +MA_TPR<3> A_BLT<3> A_PRE_N VDD VDD sg13_lv_pmos m=1 w=3.000u l=130.00n ++ ng=2 nrd=0 nrs=0 +MA_TPR<2> A_BLT<2> A_PRE_N VDD VDD sg13_lv_pmos m=1 w=3.000u l=130.00n ++ ng=2 nrd=0 nrs=0 +MA_TPR<1> A_BLT<1> A_PRE_N VDD VDD sg13_lv_pmos m=1 w=3.000u l=130.00n ++ ng=2 nrd=0 nrs=0 +MA_TPR<0> A_BLT<0> A_PRE_N VDD VDD sg13_lv_pmos m=1 w=3.000u l=130.00n ++ ng=2 nrd=0 nrs=0 +MA_TSP<3> A_BLT_SEL A_SEL_N<3> A_BLT<3> VDD sg13_lv_pmos m=1 w=1.5u ++ l=130.00n ng=1 nrd=0 nrs=0 +MA_TSP<2> A_BLT_SEL A_SEL_N<2> A_BLT<2> VDD sg13_lv_pmos m=1 w=1.5u ++ l=130.00n ng=1 nrd=0 nrs=0 +MA_TSP<1> A_BLT_SEL A_SEL_N<1> A_BLT<1> VDD sg13_lv_pmos m=1 w=1.5u ++ l=130.00n ng=1 nrd=0 nrs=0 +MA_TSP<0> A_BLT_SEL A_SEL_N<0> A_BLT<0> VDD sg13_lv_pmos m=1 w=1.5u ++ l=130.00n ng=1 nrd=0 nrs=0 +MA_CSP<3> A_BLC_SEL A_SEL_N<3> A_BLC<3> VDD sg13_lv_pmos m=1 w=1.5u ++ l=130.00n ng=1 nrd=0 nrs=0 +MA_CSP<2> A_BLC_SEL A_SEL_N<2> A_BLC<2> VDD sg13_lv_pmos m=1 w=1.5u ++ l=130.00n ng=1 nrd=0 nrs=0 +MA_CSP<1> A_BLC_SEL A_SEL_N<1> A_BLC<1> VDD sg13_lv_pmos m=1 w=1.5u ++ l=130.00n ng=1 nrd=0 nrs=0 +MA_CSP<0> A_BLC_SEL A_SEL_N<0> A_BLC<0> VDD sg13_lv_pmos m=1 w=1.5u ++ l=130.00n ng=1 nrd=0 nrs=0 +MB_CWP<3> B_BLC<3> B_BLC_PMOS_DRIVE<3> VDD VDD sg13_lv_pmos m=1 w=1.5u ++ l=130.00n ng=1 nrd=0 nrs=0 +MB_CWP<2> B_BLC<2> B_BLC_PMOS_DRIVE<2> VDD VDD sg13_lv_pmos m=1 w=1.5u ++ l=130.00n ng=1 nrd=0 nrs=0 +MB_CWP<1> B_BLC<1> B_BLC_PMOS_DRIVE<1> VDD VDD sg13_lv_pmos m=1 w=1.5u ++ l=130.00n ng=1 nrd=0 nrs=0 +MB_CWP<0> B_BLC<0> B_BLC_PMOS_DRIVE<0> VDD VDD sg13_lv_pmos m=1 w=1.5u ++ l=130.00n ng=1 nrd=0 nrs=0 +MB_TWP<3> B_BLT<3> B_BLT_PMOS_DRIVE<3> VDD VDD sg13_lv_pmos m=1 w=1.5u ++ l=130.00n ng=1 nrd=0 nrs=0 +MB_TWP<2> B_BLT<2> B_BLT_PMOS_DRIVE<2> VDD VDD sg13_lv_pmos m=1 w=1.5u ++ l=130.00n ng=1 nrd=0 nrs=0 +MB_TWP<1> B_BLT<1> B_BLT_PMOS_DRIVE<1> VDD VDD sg13_lv_pmos m=1 w=1.5u ++ l=130.00n ng=1 nrd=0 nrs=0 +MB_TWP<0> B_BLT<0> B_BLT_PMOS_DRIVE<0> VDD VDD sg13_lv_pmos m=1 w=1.5u ++ l=130.00n ng=1 nrd=0 nrs=0 +MB_TSP<3> B_BLT_SEL B_SEL_N<3> B_BLT<3> VDD sg13_lv_pmos m=1 w=1.5u ++ l=130.00n ng=1 nrd=0 nrs=0 +MB_TSP<2> B_BLT_SEL B_SEL_N<2> B_BLT<2> VDD sg13_lv_pmos m=1 w=1.5u ++ l=130.00n ng=1 nrd=0 nrs=0 +MB_TSP<1> B_BLT_SEL B_SEL_N<1> B_BLT<1> VDD sg13_lv_pmos m=1 w=1.5u ++ l=130.00n ng=1 nrd=0 nrs=0 +MB_TSP<0> B_BLT_SEL B_SEL_N<0> B_BLT<0> VDD sg13_lv_pmos m=1 w=1.5u ++ l=130.00n ng=1 nrd=0 nrs=0 +MB_TPR<3> B_BLT<3> B_PRE_N VDD VDD sg13_lv_pmos m=1 w=3.000u l=130.00n ++ ng=2 nrd=0 nrs=0 +MB_TPR<2> B_BLT<2> B_PRE_N VDD VDD sg13_lv_pmos m=1 w=3.000u l=130.00n ++ ng=2 nrd=0 nrs=0 +MB_TPR<1> B_BLT<1> B_PRE_N VDD VDD sg13_lv_pmos m=1 w=3.000u l=130.00n ++ ng=2 nrd=0 nrs=0 +MB_TPR<0> B_BLT<0> B_PRE_N VDD VDD sg13_lv_pmos m=1 w=3.000u l=130.00n ++ ng=2 nrd=0 nrs=0 +MB_CSP<3> B_BLC_SEL B_SEL_N<3> B_BLC<3> VDD sg13_lv_pmos m=1 w=1.5u ++ l=130.00n ng=1 nrd=0 nrs=0 +MB_CSP<2> B_BLC_SEL B_SEL_N<2> B_BLC<2> VDD sg13_lv_pmos m=1 w=1.5u ++ l=130.00n ng=1 nrd=0 nrs=0 +MB_CSP<1> B_BLC_SEL B_SEL_N<1> B_BLC<1> VDD sg13_lv_pmos m=1 w=1.5u ++ l=130.00n ng=1 nrd=0 nrs=0 +MB_CSP<0> B_BLC_SEL B_SEL_N<0> B_BLC<0> VDD sg13_lv_pmos m=1 w=1.5u ++ l=130.00n ng=1 nrd=0 nrs=0 +MB_CPR<3> B_BLC<3> B_PRE_N VDD VDD sg13_lv_pmos m=1 w=3.000u l=130.00n ++ ng=2 nrd=0 nrs=0 +MB_CPR<2> B_BLC<2> B_PRE_N VDD VDD sg13_lv_pmos m=1 w=3.000u l=130.00n ++ ng=2 nrd=0 nrs=0 +MB_CPR<1> B_BLC<1> B_PRE_N VDD VDD sg13_lv_pmos m=1 w=3.000u l=130.00n ++ ng=2 nrd=0 nrs=0 +MB_CPR<0> B_BLC<0> B_PRE_N VDD VDD sg13_lv_pmos m=1 w=3.000u l=130.00n ++ ng=2 nrd=0 nrs=0 +XA_SEL<3> A_SEL_P<3> A_SEL_N<3> VDD VSS / RSC_IHPSG13_INVX2 +XA_SEL<2> A_SEL_P<2> A_SEL_N<2> VDD VSS / RSC_IHPSG13_INVX2 +XA_SEL<1> A_SEL_P<1> A_SEL_N<1> VDD VSS / RSC_IHPSG13_INVX2 +XA_SEL<0> A_SEL_P<0> A_SEL_N<0> VDD VSS / RSC_IHPSG13_INVX2 +XA_CINV<3> A_BLT_PMOS_DRIVE<3> A_BLC_NMOS_DRIVE<3> VDD VSS / ++ RSC_IHPSG13_INVX2 +XA_CINV<2> A_BLT_PMOS_DRIVE<2> A_BLC_NMOS_DRIVE<2> VDD VSS / ++ RSC_IHPSG13_INVX2 +XA_CINV<1> A_BLT_PMOS_DRIVE<1> A_BLC_NMOS_DRIVE<1> VDD VSS / ++ RSC_IHPSG13_INVX2 +XA_CINV<0> A_BLT_PMOS_DRIVE<0> A_BLC_NMOS_DRIVE<0> VDD VSS / ++ RSC_IHPSG13_INVX2 +XA_TINV<3> A_BLC_PMOS_DRIVE<3> A_BLT_NMOS_DRIVE<3> VDD VSS / ++ RSC_IHPSG13_INVX2 +XA_TINV<2> A_BLC_PMOS_DRIVE<2> A_BLT_NMOS_DRIVE<2> VDD VSS / ++ RSC_IHPSG13_INVX2 +XA_TINV<1> A_BLC_PMOS_DRIVE<1> A_BLT_NMOS_DRIVE<1> VDD VSS / ++ RSC_IHPSG13_INVX2 +XA_TINV<0> A_BLC_PMOS_DRIVE<0> A_BLT_NMOS_DRIVE<0> VDD VSS / ++ RSC_IHPSG13_INVX2 +XB_SEL<3> B_SEL_P<3> B_SEL_N<3> VDD VSS / RSC_IHPSG13_INVX2 +XB_SEL<2> B_SEL_P<2> B_SEL_N<2> VDD VSS / RSC_IHPSG13_INVX2 +XB_SEL<1> B_SEL_P<1> B_SEL_N<1> VDD VSS / RSC_IHPSG13_INVX2 +XB_SEL<0> B_SEL_P<0> B_SEL_N<0> VDD VSS / RSC_IHPSG13_INVX2 +XB_TINV<3> B_BLC_PMOS_DRIVE<3> B_BLT_NMOS_DRIVE<3> VDD VSS / ++ RSC_IHPSG13_INVX2 +XB_TINV<2> B_BLC_PMOS_DRIVE<2> B_BLT_NMOS_DRIVE<2> VDD VSS / ++ RSC_IHPSG13_INVX2 +XB_TINV<1> B_BLC_PMOS_DRIVE<1> B_BLT_NMOS_DRIVE<1> VDD VSS / ++ RSC_IHPSG13_INVX2 +XB_TINV<0> B_BLC_PMOS_DRIVE<0> B_BLT_NMOS_DRIVE<0> VDD VSS / ++ RSC_IHPSG13_INVX2 +XB_CINV<3> B_BLT_PMOS_DRIVE<3> B_BLC_NMOS_DRIVE<3> VDD VSS / ++ RSC_IHPSG13_INVX2 +XB_CINV<2> B_BLT_PMOS_DRIVE<2> B_BLC_NMOS_DRIVE<2> VDD VSS / ++ RSC_IHPSG13_INVX2 +XB_CINV<1> B_BLT_PMOS_DRIVE<1> B_BLC_NMOS_DRIVE<1> VDD VSS / ++ RSC_IHPSG13_INVX2 +XB_CINV<0> B_BLT_PMOS_DRIVE<0> B_BLC_NMOS_DRIVE<0> VDD VSS / ++ RSC_IHPSG13_INVX2 +XA_TDEC<3> A_SEL_P<3> A_WR_ONE A_BLT_PMOS_DRIVE<3> VDD VSS / ++ RSC_IHPSG13_NAND2X2 +XA_TDEC<2> A_SEL_P<2> A_WR_ONE A_BLT_PMOS_DRIVE<2> VDD VSS / ++ RSC_IHPSG13_NAND2X2 +XA_TDEC<1> A_SEL_P<1> A_WR_ONE A_BLT_PMOS_DRIVE<1> VDD VSS / ++ RSC_IHPSG13_NAND2X2 +XA_TDEC<0> A_SEL_P<0> A_WR_ONE A_BLT_PMOS_DRIVE<0> VDD VSS / ++ RSC_IHPSG13_NAND2X2 +XA_CDEC<3> A_SEL_P<3> A_WR_ZERO A_BLC_PMOS_DRIVE<3> VDD VSS / ++ RSC_IHPSG13_NAND2X2 +XA_CDEC<2> A_SEL_P<2> A_WR_ZERO A_BLC_PMOS_DRIVE<2> VDD VSS / ++ RSC_IHPSG13_NAND2X2 +XA_CDEC<1> A_SEL_P<1> A_WR_ZERO A_BLC_PMOS_DRIVE<1> VDD VSS / ++ RSC_IHPSG13_NAND2X2 +XA_CDEC<0> A_SEL_P<0> A_WR_ZERO A_BLC_PMOS_DRIVE<0> VDD VSS / ++ RSC_IHPSG13_NAND2X2 +XB_CDEC<3> B_SEL_P<3> B_WR_ZERO B_BLC_PMOS_DRIVE<3> VDD VSS / ++ RSC_IHPSG13_NAND2X2 +XB_CDEC<2> B_SEL_P<2> B_WR_ZERO B_BLC_PMOS_DRIVE<2> VDD VSS / ++ RSC_IHPSG13_NAND2X2 +XB_CDEC<1> B_SEL_P<1> B_WR_ZERO B_BLC_PMOS_DRIVE<1> VDD VSS / ++ RSC_IHPSG13_NAND2X2 +XB_CDEC<0> B_SEL_P<0> B_WR_ZERO B_BLC_PMOS_DRIVE<0> VDD VSS / ++ RSC_IHPSG13_NAND2X2 +XB_TDEC<3> B_SEL_P<3> B_WR_ONE B_BLT_PMOS_DRIVE<3> VDD VSS / ++ RSC_IHPSG13_NAND2X2 +XB_TDEC<2> B_SEL_P<2> B_WR_ONE B_BLT_PMOS_DRIVE<2> VDD VSS / ++ RSC_IHPSG13_NAND2X2 +XB_TDEC<1> B_SEL_P<1> B_WR_ONE B_BLT_PMOS_DRIVE<1> VDD VSS / ++ RSC_IHPSG13_NAND2X2 +XB_TDEC<0> B_SEL_P<0> B_WR_ONE B_BLT_PMOS_DRIVE<0> VDD VSS / ++ RSC_IHPSG13_NAND2X2 +.ENDS +.SUBCKT RSC_IHPSG13_AND2X6 A B Z VDD VSS +MN3 Z net6 VSS VSS sg13_lv_nmos m=1 w=2.94u l=130.00n ng=3 nrd=0 nrs=0 +MN4 net9 B VSS VSS sg13_lv_nmos m=1 w=500.0n l=130.00n ng=1 nrd=0 nrs=0 +MN6 net6 A net9 VSS sg13_lv_nmos m=1 w=500.0n l=130.00n ng=1 nrd=0 nrs=0 +MP2 Z net6 VDD VDD sg13_lv_pmos m=1 w=4.86u l=130.00n ng=3 nrd=0 nrs=0 +MP0 net6 B VDD VDD sg13_lv_pmos m=1 w=860.00n l=130.00n ng=1 nrd=0 ++ nrs=0 +MP1 net6 A VDD VDD sg13_lv_pmos m=1 w=860.00n l=130.00n ng=1 nrd=0 ++ nrs=0 +.ENDS +.SUBCKT RM_IHPSG13_256x8_c2_2P_COLCTRL5 A_ADDR_COL<1> A_ADDR_COL<0> A_ADDR_DEC<7> ++ A_ADDR_DEC<6> A_ADDR_DEC<5> A_ADDR_DEC<4> A_ADDR_DEC<3> A_ADDR_DEC<2> ++ A_ADDR_DEC<1> A_ADDR_DEC<0> A_BIST_BM_I A_BIST_DW_I A_BIST_EN_I A_BLC<31> ++ A_BLC<30> A_BLC<29> A_BLC<28> A_BLC<27> A_BLC<26> A_BLC<25> A_BLC<24> ++ A_BLC<23> A_BLC<22> A_BLC<21> A_BLC<20> A_BLC<19> A_BLC<18> A_BLC<17> ++ A_BLC<16> A_BLC<15> A_BLC<14> A_BLC<13> A_BLC<12> A_BLC<11> A_BLC<10> ++ A_BLC<9> A_BLC<8> A_BLC<7> A_BLC<6> A_BLC<5> A_BLC<4> A_BLC<3> A_BLC<2> ++ A_BLC<1> A_BLC<0> A_BLT<31> A_BLT<30> A_BLT<29> A_BLT<28> A_BLT<27> ++ A_BLT<26> A_BLT<25> A_BLT<24> A_BLT<23> A_BLT<22> A_BLT<21> A_BLT<20> ++ A_BLT<19> A_BLT<18> A_BLT<17> A_BLT<16> A_BLT<15> A_BLT<14> A_BLT<13> ++ A_BLT<12> A_BLT<11> A_BLT<10> A_BLT<9> A_BLT<8> A_BLT<7> A_BLT<6> A_BLT<5> ++ A_BLT<4> A_BLT<3> A_BLT<2> A_BLT<1> A_BLT<0> A_BM_I A_DCLK_B_L A_DCLK_B_R ++ A_DCLK_L A_DCLK_R A_DR_O A_DW_I A_RCLK_B_L A_RCLK_B_R A_RCLK_L A_RCLK_R ++ A_TIEH_O A_WCLK_B_L A_WCLK_B_R A_WCLK_L A_WCLK_R B_ADDR_COL<1> B_ADDR_COL<0> ++ B_ADDR_DEC<7> B_ADDR_DEC<6> B_ADDR_DEC<5> B_ADDR_DEC<4> B_ADDR_DEC<3> ++ B_ADDR_DEC<2> B_ADDR_DEC<1> B_ADDR_DEC<0> B_BIST_BM_I B_BIST_DW_I ++ B_BIST_EN_I B_BLC<31> B_BLC<30> B_BLC<29> B_BLC<28> B_BLC<27> B_BLC<26> ++ B_BLC<25> B_BLC<24> B_BLC<23> B_BLC<22> B_BLC<21> B_BLC<20> B_BLC<19> ++ B_BLC<18> B_BLC<17> B_BLC<16> B_BLC<15> B_BLC<14> B_BLC<13> B_BLC<12> ++ B_BLC<11> B_BLC<10> B_BLC<9> B_BLC<8> B_BLC<7> B_BLC<6> B_BLC<5> B_BLC<4> ++ B_BLC<3> B_BLC<2> B_BLC<1> B_BLC<0> B_BLT<31> B_BLT<30> B_BLT<29> B_BLT<28> ++ B_BLT<27> B_BLT<26> B_BLT<25> B_BLT<24> B_BLT<23> B_BLT<22> B_BLT<21> ++ B_BLT<20> B_BLT<19> B_BLT<18> B_BLT<17> B_BLT<16> B_BLT<15> B_BLT<14> ++ B_BLT<13> B_BLT<12> B_BLT<11> B_BLT<10> B_BLT<9> B_BLT<8> B_BLT<7> B_BLT<6> ++ B_BLT<5> B_BLT<4> B_BLT<3> B_BLT<2> B_BLT<1> B_BLT<0> B_BM_I B_DCLK_B_L ++ B_DCLK_B_R B_DCLK_L B_DCLK_R B_DR_O B_DW_I B_RCLK_B_L B_RCLK_B_R B_RCLK_L ++ B_RCLK_R B_TIEH_O B_WCLK_B_L B_WCLK_B_R B_WCLK_L B_WCLK_R VDD VSS +XB_I80<1> B_WCLK_B_L B_RCLK_B_L B_W_nor_R<1> VDD VSS / ++ RSC_IHPSG13_AND2X2 +XB_I80<0> B_WCLK_B_L B_RCLK_B_L B_W_nor_R<0> VDD VSS / ++ RSC_IHPSG13_AND2X2 +XA_I80<1> A_WCLK_B_L A_RCLK_B_L A_W_nor_R<1> VDD VSS / ++ RSC_IHPSG13_AND2X2 +XA_I80<0> A_WCLK_B_L A_RCLK_B_L A_W_nor_R<0> VDD VSS / ++ RSC_IHPSG13_AND2X2 +XB_I44 B_BM_N B_WCLK_B_L B_DO_WRITE_P VDD VSS / RSC_IHPSG13_NOR2X2 +XA_I44 A_BM_N A_WCLK_B_L A_DO_WRITE_P VDD VSS / RSC_IHPSG13_NOR2X2 +XI_FILL4<16> VDD VSS / RSC_IHPSG13_FILLCAP4 +XI_FILL4<15> VDD VSS / RSC_IHPSG13_FILLCAP4 +XI_FILL4<14> VDD VSS / RSC_IHPSG13_FILLCAP4 +XI_FILL4<13> VDD VSS / RSC_IHPSG13_FILLCAP4 +XI_FILL4<12> VDD VSS / RSC_IHPSG13_FILLCAP4 +XI_FILL4<11> VDD VSS / RSC_IHPSG13_FILLCAP4 +XI_FILL4<10> VDD VSS / RSC_IHPSG13_FILLCAP4 +XI_FILL4<9> VDD VSS / RSC_IHPSG13_FILLCAP4 +XI_FILL4<8> VDD VSS / RSC_IHPSG13_FILLCAP4 +XI_FILL4<7> VDD VSS / RSC_IHPSG13_FILLCAP4 +XI_FILL4<6> VDD VSS / RSC_IHPSG13_FILLCAP4 +XI_FILL4<5> VDD VSS / RSC_IHPSG13_FILLCAP4 +XI_FILL4<4> VDD VSS / RSC_IHPSG13_FILLCAP4 +XI_FILL4<3> VDD VSS / RSC_IHPSG13_FILLCAP4 +XI_FILL4<2> VDD VSS / RSC_IHPSG13_FILLCAP4 +XI_FILL4<1> VDD VSS / RSC_IHPSG13_FILLCAP4 +XB_INV<6> B_N1<1> B_P1<1> VDD VSS / RSC_IHPSG13_CINVX4 +XB_INV<5> B_N0<1> B_P0<1> VDD VSS / RSC_IHPSG13_CINVX4 +XB_INV<4> B_N0<0> B_P0<0> VDD VSS / RSC_IHPSG13_CINVX4 +XB_INV<3> B_ADDR_COL<1> B_N1<1> VDD VSS / RSC_IHPSG13_CINVX4 +XB_INV<2> B_ADDR_COL<1> B_N1<0> VDD VSS / RSC_IHPSG13_CINVX4 +XB_INV<1> B_ADDR_COL<0> B_N0<1> VDD VSS / RSC_IHPSG13_CINVX4 +XB_INV<0> B_ADDR_COL<0> B_N0<0> VDD VSS / RSC_IHPSG13_CINVX4 +XA_INV<6> A_N1<1> A_P1<1> VDD VSS / RSC_IHPSG13_CINVX4 +XA_INV<5> A_N0<1> A_P0<1> VDD VSS / RSC_IHPSG13_CINVX4 +XA_INV<4> A_N0<0> A_P0<0> VDD VSS / RSC_IHPSG13_CINVX4 +XA_INV<3> A_ADDR_COL<1> A_N1<1> VDD VSS / RSC_IHPSG13_CINVX4 +XA_INV<2> A_ADDR_COL<1> A_N1<0> VDD VSS / RSC_IHPSG13_CINVX4 +XA_INV<1> A_ADDR_COL<0> A_N0<1> VDD VSS / RSC_IHPSG13_CINVX4 +XA_INV<0> A_ADDR_COL<0> A_N0<0> VDD VSS / RSC_IHPSG13_CINVX4 +XB_I81<3> B_W_nor_R<1> B_PRE_N VDD VSS / RSC_IHPSG13_CINVX4_WN +XB_I81<2> B_W_nor_R<1> B_PRE_N VDD VSS / RSC_IHPSG13_CINVX4_WN +XB_I81<1> B_W_nor_R<0> B_PRE_N VDD VSS / RSC_IHPSG13_CINVX4_WN +XB_I81<0> B_W_nor_R<0> B_PRE_N VDD VSS / RSC_IHPSG13_CINVX4_WN +XA_I81<3> A_W_nor_R<1> A_PRE_N VDD VSS / RSC_IHPSG13_CINVX4_WN +XA_I81<2> A_W_nor_R<1> A_PRE_N VDD VSS / RSC_IHPSG13_CINVX4_WN +XA_I81<1> A_W_nor_R<0> A_PRE_N VDD VSS / RSC_IHPSG13_CINVX4_WN +XA_I81<0> A_W_nor_R<0> A_PRE_N VDD VSS / RSC_IHPSG13_CINVX4_WN +XI_FILL8<78> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI_FILL8<77> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI_FILL8<76> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI_FILL8<75> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI_FILL8<74> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI_FILL8<73> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI_FILL8<72> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI_FILL8<71> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI_FILL8<70> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI_FILL8<69> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI_FILL8<68> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI_FILL8<67> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI_FILL8<66> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI_FILL8<65> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI_FILL8<64> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI_FILL8<63> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI_FILL8<62> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI_FILL8<61> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI_FILL8<60> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI_FILL8<59> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI_FILL8<58> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI_FILL8<57> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI_FILL8<56> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI_FILL8<55> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI_FILL8<54> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI_FILL8<53> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI_FILL8<52> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI_FILL8<51> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI_FILL8<50> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI_FILL8<49> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI_FILL8<48> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI_FILL8<47> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI_FILL8<46> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI_FILL8<45> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI_FILL8<44> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI_FILL8<43> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI_FILL8<42> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI_FILL8<41> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI_FILL8<40> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI_FILL8<39> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI_FILL8<38> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI_FILL8<37> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI_FILL8<36> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI_FILL8<35> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI_FILL8<34> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI_FILL8<33> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI_FILL8<32> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI_FILL8<31> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI_FILL8<30> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI_FILL8<29> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI_FILL8<28> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI_FILL8<27> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI_FILL8<26> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI_FILL8<25> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI_FILL8<24> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI_FILL8<23> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI_FILL8<22> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI_FILL8<21> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI_FILL8<20> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI_FILL8<19> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI_FILL8<18> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI_FILL8<17> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI_FILL8<16> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI_FILL8<15> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI_FILL8<14> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI_FILL8<13> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI_FILL8<12> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI_FILL8<11> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI_FILL8<10> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI_FILL8<9> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI_FILL8<8> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI_FILL8<7> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI_FILL8<6> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI_FILL8<5> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI_FILL8<4> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI_FILL8<3> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI_FILL8<2> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI_FILL8<1> VDD VSS / RSC_IHPSG13_FILLCAP8 +XAB_BLMUX<7> A_BLC<31> A_BLC<30> A_BLC<29> A_BLC<28> A_BLC_SEL A_BLT<31> ++ A_BLT<30> A_BLT<29> A_BLT<28> A_BLT_SEL A_PRE_N A_SEL_P<31> A_SEL_P<30> ++ A_SEL_P<29> A_SEL_P<28> A_WR_ONE A_WR_ZERO B_BLC<31> B_BLC<30> B_BLC<29> ++ B_BLC<28> B_BLC_SEL B_BLT<31> B_BLT<30> B_BLT<29> B_BLT<28> B_BLT_SEL ++ B_PRE_N B_SEL_P<31> B_SEL_P<30> B_SEL_P<29> B_SEL_P<28> B_WR_ONE B_WR_ZERO ++ VDD VSS / RM_IHPSG13_256x8_c2_2P_BLDRV +XAB_BLMUX<6> A_BLC<27> A_BLC<26> A_BLC<25> A_BLC<24> A_BLC_SEL A_BLT<27> ++ A_BLT<26> A_BLT<25> A_BLT<24> A_BLT_SEL A_PRE_N A_SEL_P<27> A_SEL_P<26> ++ A_SEL_P<25> A_SEL_P<24> A_WR_ONE A_WR_ZERO B_BLC<27> B_BLC<26> B_BLC<25> ++ B_BLC<24> B_BLC_SEL B_BLT<27> B_BLT<26> B_BLT<25> B_BLT<24> B_BLT_SEL ++ B_PRE_N B_SEL_P<27> B_SEL_P<26> B_SEL_P<25> B_SEL_P<24> B_WR_ONE B_WR_ZERO ++ VDD VSS / RM_IHPSG13_256x8_c2_2P_BLDRV +XAB_BLMUX<5> A_BLC<23> A_BLC<22> A_BLC<21> A_BLC<20> A_BLC_SEL A_BLT<23> ++ A_BLT<22> A_BLT<21> A_BLT<20> A_BLT_SEL A_PRE_N A_SEL_P<23> A_SEL_P<22> ++ A_SEL_P<21> A_SEL_P<20> A_WR_ONE A_WR_ZERO B_BLC<23> B_BLC<22> B_BLC<21> ++ B_BLC<20> B_BLC_SEL B_BLT<23> B_BLT<22> B_BLT<21> B_BLT<20> B_BLT_SEL ++ B_PRE_N B_SEL_P<23> B_SEL_P<22> B_SEL_P<21> B_SEL_P<20> B_WR_ONE B_WR_ZERO ++ VDD VSS / RM_IHPSG13_256x8_c2_2P_BLDRV +XAB_BLMUX<4> A_BLC<19> A_BLC<18> A_BLC<17> A_BLC<16> A_BLC_SEL A_BLT<19> ++ A_BLT<18> A_BLT<17> A_BLT<16> A_BLT_SEL A_PRE_N A_SEL_P<19> A_SEL_P<18> ++ A_SEL_P<17> A_SEL_P<16> A_WR_ONE A_WR_ZERO B_BLC<19> B_BLC<18> B_BLC<17> ++ B_BLC<16> B_BLC_SEL B_BLT<19> B_BLT<18> B_BLT<17> B_BLT<16> B_BLT_SEL ++ B_PRE_N B_SEL_P<19> B_SEL_P<18> B_SEL_P<17> B_SEL_P<16> B_WR_ONE B_WR_ZERO ++ VDD VSS / RM_IHPSG13_256x8_c2_2P_BLDRV +XAB_BLMUX<3> A_BLC<15> A_BLC<14> A_BLC<13> A_BLC<12> A_BLC_SEL A_BLT<15> ++ A_BLT<14> A_BLT<13> A_BLT<12> A_BLT_SEL A_PRE_N A_SEL_P<15> A_SEL_P<14> ++ A_SEL_P<13> A_SEL_P<12> A_WR_ONE A_WR_ZERO B_BLC<15> B_BLC<14> B_BLC<13> ++ B_BLC<12> B_BLC_SEL B_BLT<15> B_BLT<14> B_BLT<13> B_BLT<12> B_BLT_SEL ++ B_PRE_N B_SEL_P<15> B_SEL_P<14> B_SEL_P<13> B_SEL_P<12> B_WR_ONE B_WR_ZERO ++ VDD VSS / RM_IHPSG13_256x8_c2_2P_BLDRV +XAB_BLMUX<2> A_BLC<11> A_BLC<10> A_BLC<9> A_BLC<8> A_BLC_SEL A_BLT<11> ++ A_BLT<10> A_BLT<9> A_BLT<8> A_BLT_SEL A_PRE_N A_SEL_P<11> A_SEL_P<10> ++ A_SEL_P<9> A_SEL_P<8> A_WR_ONE A_WR_ZERO B_BLC<11> B_BLC<10> B_BLC<9> ++ B_BLC<8> B_BLC_SEL B_BLT<11> B_BLT<10> B_BLT<9> B_BLT<8> B_BLT_SEL B_PRE_N ++ B_SEL_P<11> B_SEL_P<10> B_SEL_P<9> B_SEL_P<8> B_WR_ONE B_WR_ZERO VDD ++ VSS / RM_IHPSG13_256x8_c2_2P_BLDRV +XAB_BLMUX<1> A_BLC<7> A_BLC<6> A_BLC<5> A_BLC<4> A_BLC_SEL A_BLT<7> A_BLT<6> ++ A_BLT<5> A_BLT<4> A_BLT_SEL A_PRE_N A_SEL_P<7> A_SEL_P<6> A_SEL_P<5> ++ A_SEL_P<4> A_WR_ONE A_WR_ZERO B_BLC<7> B_BLC<6> B_BLC<5> B_BLC<4> B_BLC_SEL ++ B_BLT<7> B_BLT<6> B_BLT<5> B_BLT<4> B_BLT_SEL B_PRE_N B_SEL_P<7> B_SEL_P<6> ++ B_SEL_P<5> B_SEL_P<4> B_WR_ONE B_WR_ZERO VDD VSS / ++ RM_IHPSG13_256x8_c2_2P_BLDRV +XAB_BLMUX<0> A_BLC<3> A_BLC<2> A_BLC<1> A_BLC<0> A_BLC_SEL A_BLT<3> A_BLT<2> ++ A_BLT<1> A_BLT<0> A_BLT_SEL A_PRE_N A_SEL_P<3> A_SEL_P<2> A_SEL_P<1> ++ A_SEL_P<0> A_WR_ONE A_WR_ZERO B_BLC<3> B_BLC<2> B_BLC<1> B_BLC<0> B_BLC_SEL ++ B_BLT<3> B_BLT<2> B_BLT<1> B_BLT<0> B_BLT_SEL B_PRE_N B_SEL_P<3> B_SEL_P<2> ++ B_SEL_P<1> B_SEL_P<0> B_WR_ONE B_WR_ZERO VDD VSS / ++ RM_IHPSG13_256x8_c2_2P_BLDRV +XB_I51 net037 B_DR_O VDD VSS / RSC_IHPSG13_INVX4 +XA_I51 net19 A_DR_O VDD VSS / RSC_IHPSG13_INVX4 +XB_I78 B_RCLK_B_L B_SAE VDD VSS / RSC_IHPSG13_CBUFX2 +XA_I78 A_RCLK_B_L A_SAE VDD VSS / RSC_IHPSG13_CBUFX2 +XB_I69 B_DCLK_L B_DCLK_B_L VDD VSS / RSC_IHPSG13_CINVX8 +XB_I50 B_WCLK_L B_WCLK_B_L VDD VSS / RSC_IHPSG13_CINVX8 +XB_EBUF B_RCLK_L B_RCLK_B_L VDD VSS / RSC_IHPSG13_CINVX8 +XA_I69 A_DCLK_L A_DCLK_B_L VDD VSS / RSC_IHPSG13_CINVX8 +XA_I50 A_WCLK_L A_WCLK_B_L VDD VSS / RSC_IHPSG13_CINVX8 +XA_EBUF A_RCLK_L A_RCLK_B_L VDD VSS / RSC_IHPSG13_CINVX8 +XB_I76 B_DI_N B_DO_WRITE_P B_WR_ZERO VDD VSS / RSC_IHPSG13_AND2X6 +XB_I75 B_DI_R B_DO_WRITE_P B_WR_ONE VDD VSS / RSC_IHPSG13_AND2X6 +XA_I76 A_DI_N A_DO_WRITE_P A_WR_ZERO VDD VSS / RSC_IHPSG13_AND2X6 +XA_I75 A_DI_R A_DO_WRITE_P A_WR_ONE VDD VSS / RSC_IHPSG13_AND2X6 +XB_I83 B_BM_R B_BM_N VDD VSS / RSC_IHPSG13_INVX2 +XB_DEC3INV<31> net041<0> B_SEL_P<31> VDD VSS / RSC_IHPSG13_INVX2 +XB_DEC3INV<30> net041<1> B_SEL_P<30> VDD VSS / RSC_IHPSG13_INVX2 +XB_DEC3INV<29> net041<2> B_SEL_P<29> VDD VSS / RSC_IHPSG13_INVX2 +XB_DEC3INV<28> net041<3> B_SEL_P<28> VDD VSS / RSC_IHPSG13_INVX2 +XB_DEC3INV<27> net041<4> B_SEL_P<27> VDD VSS / RSC_IHPSG13_INVX2 +XB_DEC3INV<26> net041<5> B_SEL_P<26> VDD VSS / RSC_IHPSG13_INVX2 +XB_DEC3INV<25> net041<6> B_SEL_P<25> VDD VSS / RSC_IHPSG13_INVX2 +XB_DEC3INV<24> net041<7> B_SEL_P<24> VDD VSS / RSC_IHPSG13_INVX2 +XB_DEC3INV<23> net041<8> B_SEL_P<23> VDD VSS / RSC_IHPSG13_INVX2 +XB_DEC3INV<22> net041<9> B_SEL_P<22> VDD VSS / RSC_IHPSG13_INVX2 +XB_DEC3INV<21> net041<10> B_SEL_P<21> VDD VSS / RSC_IHPSG13_INVX2 +XB_DEC3INV<20> net041<11> B_SEL_P<20> VDD VSS / RSC_IHPSG13_INVX2 +XB_DEC3INV<19> net041<12> B_SEL_P<19> VDD VSS / RSC_IHPSG13_INVX2 +XB_DEC3INV<18> net041<13> B_SEL_P<18> VDD VSS / RSC_IHPSG13_INVX2 +XB_DEC3INV<17> net041<14> B_SEL_P<17> VDD VSS / RSC_IHPSG13_INVX2 +XB_DEC3INV<16> net041<15> B_SEL_P<16> VDD VSS / RSC_IHPSG13_INVX2 +XB_DEC3INV<15> net041<16> B_SEL_P<15> VDD VSS / RSC_IHPSG13_INVX2 +XB_DEC3INV<14> net041<17> B_SEL_P<14> VDD VSS / RSC_IHPSG13_INVX2 +XB_DEC3INV<13> net041<18> B_SEL_P<13> VDD VSS / RSC_IHPSG13_INVX2 +XB_DEC3INV<12> net041<19> B_SEL_P<12> VDD VSS / RSC_IHPSG13_INVX2 +XB_DEC3INV<11> net041<20> B_SEL_P<11> VDD VSS / RSC_IHPSG13_INVX2 +XB_DEC3INV<10> net041<21> B_SEL_P<10> VDD VSS / RSC_IHPSG13_INVX2 +XB_DEC3INV<9> net041<22> B_SEL_P<9> VDD VSS / RSC_IHPSG13_INVX2 +XB_DEC3INV<8> net041<23> B_SEL_P<8> VDD VSS / RSC_IHPSG13_INVX2 +XB_DEC3INV<7> net041<24> B_SEL_P<7> VDD VSS / RSC_IHPSG13_INVX2 +XB_DEC3INV<6> net041<25> B_SEL_P<6> VDD VSS / RSC_IHPSG13_INVX2 +XB_DEC3INV<5> net041<26> B_SEL_P<5> VDD VSS / RSC_IHPSG13_INVX2 +XB_DEC3INV<4> net041<27> B_SEL_P<4> VDD VSS / RSC_IHPSG13_INVX2 +XB_DEC3INV<3> net041<28> B_SEL_P<3> VDD VSS / RSC_IHPSG13_INVX2 +XB_DEC3INV<2> net041<29> B_SEL_P<2> VDD VSS / RSC_IHPSG13_INVX2 +XB_DEC3INV<1> net041<30> B_SEL_P<1> VDD VSS / RSC_IHPSG13_INVX2 +XB_DEC3INV<0> net041<31> B_SEL_P<0> VDD VSS / RSC_IHPSG13_INVX2 +XB_I49 B_DI_R B_DI_N VDD VSS / RSC_IHPSG13_INVX2 +XA_I83 A_BM_R A_BM_N VDD VSS / RSC_IHPSG13_INVX2 +XA_DEC3INV<31> net23<0> A_SEL_P<31> VDD VSS / RSC_IHPSG13_INVX2 +XA_DEC3INV<30> net23<1> A_SEL_P<30> VDD VSS / RSC_IHPSG13_INVX2 +XA_DEC3INV<29> net23<2> A_SEL_P<29> VDD VSS / RSC_IHPSG13_INVX2 +XA_DEC3INV<28> net23<3> A_SEL_P<28> VDD VSS / RSC_IHPSG13_INVX2 +XA_DEC3INV<27> net23<4> A_SEL_P<27> VDD VSS / RSC_IHPSG13_INVX2 +XA_DEC3INV<26> net23<5> A_SEL_P<26> VDD VSS / RSC_IHPSG13_INVX2 +XA_DEC3INV<25> net23<6> A_SEL_P<25> VDD VSS / RSC_IHPSG13_INVX2 +XA_DEC3INV<24> net23<7> A_SEL_P<24> VDD VSS / RSC_IHPSG13_INVX2 +XA_DEC3INV<23> net23<8> A_SEL_P<23> VDD VSS / RSC_IHPSG13_INVX2 +XA_DEC3INV<22> net23<9> A_SEL_P<22> VDD VSS / RSC_IHPSG13_INVX2 +XA_DEC3INV<21> net23<10> A_SEL_P<21> VDD VSS / RSC_IHPSG13_INVX2 +XA_DEC3INV<20> net23<11> A_SEL_P<20> VDD VSS / RSC_IHPSG13_INVX2 +XA_DEC3INV<19> net23<12> A_SEL_P<19> VDD VSS / RSC_IHPSG13_INVX2 +XA_DEC3INV<18> net23<13> A_SEL_P<18> VDD VSS / RSC_IHPSG13_INVX2 +XA_DEC3INV<17> net23<14> A_SEL_P<17> VDD VSS / RSC_IHPSG13_INVX2 +XA_DEC3INV<16> net23<15> A_SEL_P<16> VDD VSS / RSC_IHPSG13_INVX2 +XA_DEC3INV<15> net23<16> A_SEL_P<15> VDD VSS / RSC_IHPSG13_INVX2 +XA_DEC3INV<14> net23<17> A_SEL_P<14> VDD VSS / RSC_IHPSG13_INVX2 +XA_DEC3INV<13> net23<18> A_SEL_P<13> VDD VSS / RSC_IHPSG13_INVX2 +XA_DEC3INV<12> net23<19> A_SEL_P<12> VDD VSS / RSC_IHPSG13_INVX2 +XA_DEC3INV<11> net23<20> A_SEL_P<11> VDD VSS / RSC_IHPSG13_INVX2 +XA_DEC3INV<10> net23<21> A_SEL_P<10> VDD VSS / RSC_IHPSG13_INVX2 +XA_DEC3INV<9> net23<22> A_SEL_P<9> VDD VSS / RSC_IHPSG13_INVX2 +XA_DEC3INV<8> net23<23> A_SEL_P<8> VDD VSS / RSC_IHPSG13_INVX2 +XA_DEC3INV<7> net23<24> A_SEL_P<7> VDD VSS / RSC_IHPSG13_INVX2 +XA_DEC3INV<6> net23<25> A_SEL_P<6> VDD VSS / RSC_IHPSG13_INVX2 +XA_DEC3INV<5> net23<26> A_SEL_P<5> VDD VSS / RSC_IHPSG13_INVX2 +XA_DEC3INV<4> net23<27> A_SEL_P<4> VDD VSS / RSC_IHPSG13_INVX2 +XA_DEC3INV<3> net23<28> A_SEL_P<3> VDD VSS / RSC_IHPSG13_INVX2 +XA_DEC3INV<2> net23<29> A_SEL_P<2> VDD VSS / RSC_IHPSG13_INVX2 +XA_DEC3INV<1> net23<30> A_SEL_P<1> VDD VSS / RSC_IHPSG13_INVX2 +XA_DEC3INV<0> net23<31> A_SEL_P<0> VDD VSS / RSC_IHPSG13_INVX2 +XA_I49 A_DI_R A_DI_N VDD VSS / RSC_IHPSG13_INVX2 +XB_ISENSE B_SAE B_BLC_SEL B_BLT_SEL net037 net038 VDD VSS / ++ RSC_IHPSG13_DFPQD_MSAFFX2 +XA_ISENSE A_SAE A_BLC_SEL A_BLT_SEL net19 net20 VDD VSS / ++ RSC_IHPSG13_DFPQD_MSAFFX2 +XB_DREG B_BIST_EN_I B_BIST_DW_I B_DCLK_B_L B_DW_I B_DI_R net042 VDD ++ VSS / RSC_IHPSG13_DFNQMX2IX1 +XB_BREG B_BIST_EN_I B_BIST_BM_I B_DCLK_B_L B_BM_I B_BM_R net043 VDD ++ VSS / RSC_IHPSG13_DFNQMX2IX1 +XA_DREG A_BIST_EN_I A_BIST_DW_I A_DCLK_B_L A_DW_I A_DI_R net22 VDD VSS ++ / RSC_IHPSG13_DFNQMX2IX1 +XA_BREG A_BIST_EN_I A_BIST_BM_I A_DCLK_B_L A_BM_I A_BM_R net21 VDD VSS ++ / RSC_IHPSG13_DFNQMX2IX1 +XB_DEC3<31> B_P1<1> B_P0<1> B_ADDR_DEC<7> net041<0> VDD VSS / ++ RSC_IHPSG13_NAND3X2 +XB_DEC3<30> B_P1<1> B_P0<1> B_ADDR_DEC<6> net041<1> VDD VSS / ++ RSC_IHPSG13_NAND3X2 +XB_DEC3<29> B_P1<1> B_P0<1> B_ADDR_DEC<5> net041<2> VDD VSS / ++ RSC_IHPSG13_NAND3X2 +XB_DEC3<28> B_P1<1> B_P0<1> B_ADDR_DEC<4> net041<3> VDD VSS / ++ RSC_IHPSG13_NAND3X2 +XB_DEC3<27> B_P1<1> B_P0<1> B_ADDR_DEC<3> net041<4> VDD VSS / ++ RSC_IHPSG13_NAND3X2 +XB_DEC3<26> B_P1<1> B_P0<1> B_ADDR_DEC<2> net041<5> VDD VSS / ++ RSC_IHPSG13_NAND3X2 +XB_DEC3<25> B_P1<1> B_P0<1> B_ADDR_DEC<1> net041<6> VDD VSS / ++ RSC_IHPSG13_NAND3X2 +XB_DEC3<24> B_P1<1> B_P0<1> B_ADDR_DEC<0> net041<7> VDD VSS / ++ RSC_IHPSG13_NAND3X2 +XB_DEC3<23> B_P1<1> B_N0<1> B_ADDR_DEC<7> net041<8> VDD VSS / ++ RSC_IHPSG13_NAND3X2 +XB_DEC3<22> B_P1<1> B_N0<1> B_ADDR_DEC<6> net041<9> VDD VSS / ++ RSC_IHPSG13_NAND3X2 +XB_DEC3<21> B_P1<1> B_N0<1> B_ADDR_DEC<5> net041<10> VDD VSS / ++ RSC_IHPSG13_NAND3X2 +XB_DEC3<20> B_P1<1> B_N0<1> B_ADDR_DEC<4> net041<11> VDD VSS / ++ RSC_IHPSG13_NAND3X2 +XB_DEC3<19> B_P1<1> B_N0<1> B_ADDR_DEC<3> net041<12> VDD VSS / ++ RSC_IHPSG13_NAND3X2 +XB_DEC3<18> B_P1<1> B_N0<1> B_ADDR_DEC<2> net041<13> VDD VSS / ++ RSC_IHPSG13_NAND3X2 +XB_DEC3<17> B_P1<1> B_N0<1> B_ADDR_DEC<1> net041<14> VDD VSS / ++ RSC_IHPSG13_NAND3X2 +XB_DEC3<16> B_P1<1> B_N0<1> B_ADDR_DEC<0> net041<15> VDD VSS / ++ RSC_IHPSG13_NAND3X2 +XB_DEC3<15> B_N1<0> B_P0<0> B_ADDR_DEC<7> net041<16> VDD VSS / ++ RSC_IHPSG13_NAND3X2 +XB_DEC3<14> B_N1<0> B_P0<0> B_ADDR_DEC<6> net041<17> VDD VSS / ++ RSC_IHPSG13_NAND3X2 +XB_DEC3<13> B_N1<0> B_P0<0> B_ADDR_DEC<5> net041<18> VDD VSS / ++ RSC_IHPSG13_NAND3X2 +XB_DEC3<12> B_N1<0> B_P0<0> B_ADDR_DEC<4> net041<19> VDD VSS / ++ RSC_IHPSG13_NAND3X2 +XB_DEC3<11> B_N1<0> B_P0<0> B_ADDR_DEC<3> net041<20> VDD VSS / ++ RSC_IHPSG13_NAND3X2 +XB_DEC3<10> B_N1<0> B_P0<0> B_ADDR_DEC<2> net041<21> VDD VSS / ++ RSC_IHPSG13_NAND3X2 +XB_DEC3<9> B_N1<0> B_P0<0> B_ADDR_DEC<1> net041<22> VDD VSS / ++ RSC_IHPSG13_NAND3X2 +XB_DEC3<8> B_N1<0> B_P0<0> B_ADDR_DEC<0> net041<23> VDD VSS / ++ RSC_IHPSG13_NAND3X2 +XB_DEC3<7> B_N1<0> B_N0<0> B_ADDR_DEC<7> net041<24> VDD VSS / ++ RSC_IHPSG13_NAND3X2 +XB_DEC3<6> B_N1<0> B_N0<0> B_ADDR_DEC<6> net041<25> VDD VSS / ++ RSC_IHPSG13_NAND3X2 +XB_DEC3<5> B_N1<0> B_N0<0> B_ADDR_DEC<5> net041<26> VDD VSS / ++ RSC_IHPSG13_NAND3X2 +XB_DEC3<4> B_N1<0> B_N0<0> B_ADDR_DEC<4> net041<27> VDD VSS / ++ RSC_IHPSG13_NAND3X2 +XB_DEC3<3> B_N1<0> B_N0<0> B_ADDR_DEC<3> net041<28> VDD VSS / ++ RSC_IHPSG13_NAND3X2 +XB_DEC3<2> B_N1<0> B_N0<0> B_ADDR_DEC<2> net041<29> VDD VSS / ++ RSC_IHPSG13_NAND3X2 +XB_DEC3<1> B_N1<0> B_N0<0> B_ADDR_DEC<1> net041<30> VDD VSS / ++ RSC_IHPSG13_NAND3X2 +XB_DEC3<0> B_N1<0> B_N0<0> B_ADDR_DEC<0> net041<31> VDD VSS / ++ RSC_IHPSG13_NAND3X2 +XA_DEC3<31> A_P1<1> A_P0<1> A_ADDR_DEC<7> net23<0> VDD VSS / ++ RSC_IHPSG13_NAND3X2 +XA_DEC3<30> A_P1<1> A_P0<1> A_ADDR_DEC<6> net23<1> VDD VSS / ++ RSC_IHPSG13_NAND3X2 +XA_DEC3<29> A_P1<1> A_P0<1> A_ADDR_DEC<5> net23<2> VDD VSS / ++ RSC_IHPSG13_NAND3X2 +XA_DEC3<28> A_P1<1> A_P0<1> A_ADDR_DEC<4> net23<3> VDD VSS / ++ RSC_IHPSG13_NAND3X2 +XA_DEC3<27> A_P1<1> A_P0<1> A_ADDR_DEC<3> net23<4> VDD VSS / ++ RSC_IHPSG13_NAND3X2 +XA_DEC3<26> A_P1<1> A_P0<1> A_ADDR_DEC<2> net23<5> VDD VSS / ++ RSC_IHPSG13_NAND3X2 +XA_DEC3<25> A_P1<1> A_P0<1> A_ADDR_DEC<1> net23<6> VDD VSS / ++ RSC_IHPSG13_NAND3X2 +XA_DEC3<24> A_P1<1> A_P0<1> A_ADDR_DEC<0> net23<7> VDD VSS / ++ RSC_IHPSG13_NAND3X2 +XA_DEC3<23> A_P1<1> A_N0<1> A_ADDR_DEC<7> net23<8> VDD VSS / ++ RSC_IHPSG13_NAND3X2 +XA_DEC3<22> A_P1<1> A_N0<1> A_ADDR_DEC<6> net23<9> VDD VSS / ++ RSC_IHPSG13_NAND3X2 +XA_DEC3<21> A_P1<1> A_N0<1> A_ADDR_DEC<5> net23<10> VDD VSS / ++ RSC_IHPSG13_NAND3X2 +XA_DEC3<20> A_P1<1> A_N0<1> A_ADDR_DEC<4> net23<11> VDD VSS / ++ RSC_IHPSG13_NAND3X2 +XA_DEC3<19> A_P1<1> A_N0<1> A_ADDR_DEC<3> net23<12> VDD VSS / ++ RSC_IHPSG13_NAND3X2 +XA_DEC3<18> A_P1<1> A_N0<1> A_ADDR_DEC<2> net23<13> VDD VSS / ++ RSC_IHPSG13_NAND3X2 +XA_DEC3<17> A_P1<1> A_N0<1> A_ADDR_DEC<1> net23<14> VDD VSS / ++ RSC_IHPSG13_NAND3X2 +XA_DEC3<16> A_P1<1> A_N0<1> A_ADDR_DEC<0> net23<15> VDD VSS / ++ RSC_IHPSG13_NAND3X2 +XA_DEC3<15> A_N1<0> A_P0<0> A_ADDR_DEC<7> net23<16> VDD VSS / ++ RSC_IHPSG13_NAND3X2 +XA_DEC3<14> A_N1<0> A_P0<0> A_ADDR_DEC<6> net23<17> VDD VSS / ++ RSC_IHPSG13_NAND3X2 +XA_DEC3<13> A_N1<0> A_P0<0> A_ADDR_DEC<5> net23<18> VDD VSS / ++ RSC_IHPSG13_NAND3X2 +XA_DEC3<12> A_N1<0> A_P0<0> A_ADDR_DEC<4> net23<19> VDD VSS / ++ RSC_IHPSG13_NAND3X2 +XA_DEC3<11> A_N1<0> A_P0<0> A_ADDR_DEC<3> net23<20> VDD VSS / ++ RSC_IHPSG13_NAND3X2 +XA_DEC3<10> A_N1<0> A_P0<0> A_ADDR_DEC<2> net23<21> VDD VSS / ++ RSC_IHPSG13_NAND3X2 +XA_DEC3<9> A_N1<0> A_P0<0> A_ADDR_DEC<1> net23<22> VDD VSS / ++ RSC_IHPSG13_NAND3X2 +XA_DEC3<8> A_N1<0> A_P0<0> A_ADDR_DEC<0> net23<23> VDD VSS / ++ RSC_IHPSG13_NAND3X2 +XA_DEC3<7> A_N1<0> A_N0<0> A_ADDR_DEC<7> net23<24> VDD VSS / ++ RSC_IHPSG13_NAND3X2 +XA_DEC3<6> A_N1<0> A_N0<0> A_ADDR_DEC<6> net23<25> VDD VSS / ++ RSC_IHPSG13_NAND3X2 +XA_DEC3<5> A_N1<0> A_N0<0> A_ADDR_DEC<5> net23<26> VDD VSS / ++ RSC_IHPSG13_NAND3X2 +XA_DEC3<4> A_N1<0> A_N0<0> A_ADDR_DEC<4> net23<27> VDD VSS / ++ RSC_IHPSG13_NAND3X2 +XA_DEC3<3> A_N1<0> A_N0<0> A_ADDR_DEC<3> net23<28> VDD VSS / ++ RSC_IHPSG13_NAND3X2 +XA_DEC3<2> A_N1<0> A_N0<0> A_ADDR_DEC<2> net23<29> VDD VSS / ++ RSC_IHPSG13_NAND3X2 +XA_DEC3<1> A_N1<0> A_N0<0> A_ADDR_DEC<1> net23<30> VDD VSS / ++ RSC_IHPSG13_NAND3X2 +XA_DEC3<0> A_N1<0> A_N0<0> A_ADDR_DEC<0> net23<31> VDD VSS / ++ RSC_IHPSG13_NAND3X2 +XB_I89 B_DCLK_B_L B_DCLK_B_R / RSC_IHPSG13_MET3RES +XB_I91 B_RCLK_B_L B_RCLK_B_R / RSC_IHPSG13_MET3RES +XB_I90 B_WCLK_B_L B_WCLK_B_R / RSC_IHPSG13_MET3RES +XB_I88 B_DCLK_L B_DCLK_R / RSC_IHPSG13_MET3RES +XB_I87 B_WCLK_L B_WCLK_R / RSC_IHPSG13_MET3RES +XB_R2 B_RCLK_L B_RCLK_R / RSC_IHPSG13_MET3RES +XA_I89 A_DCLK_B_L A_DCLK_B_R / RSC_IHPSG13_MET3RES +XA_I91 A_RCLK_B_L A_RCLK_B_R / RSC_IHPSG13_MET3RES +XA_I90 A_WCLK_B_L A_WCLK_B_R / RSC_IHPSG13_MET3RES +XA_I88 A_DCLK_L A_DCLK_R / RSC_IHPSG13_MET3RES +XA_I87 A_WCLK_L A_WCLK_R / RSC_IHPSG13_MET3RES +XA_R2 A_RCLK_L A_RCLK_R / RSC_IHPSG13_MET3RES +XB_BM_TIEH B_TIEH_O VDD VSS / RSC_IHPSG13_TIEH +XA_BM_TIEH A_TIEH_O VDD VSS / RSC_IHPSG13_TIEH +.ENDS +.SUBCKT RM_IHPSG13_256x8_c2_2P_COLDRV13_FILL4 VDD VSS +XI0<11> VDD VSS / RSC_IHPSG13_FILLCAP4 +XI0<10> VDD VSS / RSC_IHPSG13_FILLCAP4 +XI0<9> VDD VSS / RSC_IHPSG13_FILLCAP4 +XI0<8> VDD VSS / RSC_IHPSG13_FILLCAP4 +XI0<7> VDD VSS / RSC_IHPSG13_FILLCAP4 +XI0<6> VDD VSS / RSC_IHPSG13_FILLCAP4 +XI0<5> VDD VSS / RSC_IHPSG13_FILLCAP4 +XI0<4> VDD VSS / RSC_IHPSG13_FILLCAP4 +XI0<3> VDD VSS / RSC_IHPSG13_FILLCAP4 +XI0<2> VDD VSS / RSC_IHPSG13_FILLCAP4 +XI0<1> VDD VSS / RSC_IHPSG13_FILLCAP4 +.ENDS + + +.SUBCKT RSC_IHPSG13_CBUFX16 A Z VDD VSS +MN0 net4 A VSS VSS sg13_lv_nmos m=1 w=2.115u l=130.00n ng=3 nrd=0 nrs=0 +MN1 Z net4 VSS VSS sg13_lv_nmos m=1 w=5.64u l=130.00n ng=8 nrd=0 nrs=0 +MP1 Z net4 VDD VDD sg13_lv_pmos m=1 w=13.000u l=130.00n ng=8 nrd=0 ++ nrs=0 +MP0 net4 A VDD VDD sg13_lv_pmos m=1 w=4.89u l=130.00n ng=3 nrd=0 nrs=0 +.ENDS +.SUBCKT RM_IHPSG13_256x8_c2_1P_COLDRV13X16 ADDR_COL_I<1> ADDR_COL_I<0> ADDR_COL_O<1> ++ ADDR_COL_O<0> ADDR_DEC_I<7> ADDR_DEC_I<6> ADDR_DEC_I<5> ADDR_DEC_I<4> ++ ADDR_DEC_I<3> ADDR_DEC_I<2> ADDR_DEC_I<1> ADDR_DEC_I<0> ADDR_DEC_O<7> ++ ADDR_DEC_O<6> ADDR_DEC_O<5> ADDR_DEC_O<4> ADDR_DEC_O<3> ADDR_DEC_O<2> ++ ADDR_DEC_O<1> ADDR_DEC_O<0> DCLK_I DCLK_O RCLK_I RCLK_O WCLK_I WCLK_O ++ VDD VSS +XI1<1> VDD VSS / RSC_IHPSG13_FILLCAP4 +XI1<0> VDD VSS / RSC_IHPSG13_FILLCAP4 +XI0<3> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI0<2> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI0<1> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI0<0> VDD VSS / RSC_IHPSG13_FILLCAP8 +XADDR_COL_DRV<1> ADDR_COL_I<1> ADDR_COL_O<1> VDD VSS / ++ RSC_IHPSG13_CBUFX16 +XADDR_COL_DRV<0> ADDR_COL_I<0> ADDR_COL_O<0> VDD VSS / ++ RSC_IHPSG13_CBUFX16 +XADDR_DEC_DRV<7> ADDR_DEC_I<7> ADDR_DEC_O<7> VDD VSS / ++ RSC_IHPSG13_CBUFX16 +XADDR_DEC_DRV<6> ADDR_DEC_I<6> ADDR_DEC_O<6> VDD VSS / ++ RSC_IHPSG13_CBUFX16 +XADDR_DEC_DRV<5> ADDR_DEC_I<5> ADDR_DEC_O<5> VDD VSS / ++ RSC_IHPSG13_CBUFX16 +XADDR_DEC_DRV<4> ADDR_DEC_I<4> ADDR_DEC_O<4> VDD VSS / ++ RSC_IHPSG13_CBUFX16 +XADDR_DEC_DRV<3> ADDR_DEC_I<3> ADDR_DEC_O<3> VDD VSS / ++ RSC_IHPSG13_CBUFX16 +XADDR_DEC_DRV<2> ADDR_DEC_I<2> ADDR_DEC_O<2> VDD VSS / ++ RSC_IHPSG13_CBUFX16 +XADDR_DEC_DRV<1> ADDR_DEC_I<1> ADDR_DEC_O<1> VDD VSS / ++ RSC_IHPSG13_CBUFX16 +XADDR_DEC_DRV<0> ADDR_DEC_I<0> ADDR_DEC_O<0> VDD VSS / ++ RSC_IHPSG13_CBUFX16 +XDCLK_DRV DCLK_I DCLK_O VDD VSS / RSC_IHPSG13_CBUFX16 +XRCLK_DRV RCLK_I RCLK_O VDD VSS / RSC_IHPSG13_CBUFX16 +XWCLK_DRV WCLK_I WCLK_O VDD VSS / RSC_IHPSG13_CBUFX16 +.ENDS +.SUBCKT RSC_IHPSG13_WLDRVX16 A Z VDD VSS +MN1 Z net6 VSS VSS sg13_lv_nmos m=1 w=1.41u l=130.00n ng=2 nrd=0 nrs=0 +MN0 net6 A VSS VSS sg13_lv_nmos m=1 w=1.8u l=130.00n ng=2 nrd=0 nrs=0 +MP1 Z net6 VDD VDD sg13_lv_pmos m=1 w=12.96u l=130.00n ng=8 nrd=0 nrs=0 +MP0 net6 A VDD VDD sg13_lv_pmos m=1 w=900.0n l=130.00n ng=1 nrd=0 nrs=0 +.ENDS +.SUBCKT RM_IHPSG13_256x8_c2_1P_WLDRV16X16 A<15> A<14> A<13> A<12> A<11> A<10> A<9> A<8> ++ A<7> A<6> A<5> A<4> A<3> A<2> A<1> A<0> Z<15> Z<14> Z<13> Z<12> Z<11> Z<10> ++ Z<9> Z<8> Z<7> Z<6> Z<5> Z<4> Z<3> Z<2> Z<1> Z<0> VDD VSS +XBUF<15> A<15> Z<15> VDD VSS / RSC_IHPSG13_WLDRVX16 +XBUF<14> A<14> Z<14> VDD VSS / RSC_IHPSG13_WLDRVX16 +XBUF<13> A<13> Z<13> VDD VSS / RSC_IHPSG13_WLDRVX16 +XBUF<12> A<12> Z<12> VDD VSS / RSC_IHPSG13_WLDRVX16 +XBUF<11> A<11> Z<11> VDD VSS / RSC_IHPSG13_WLDRVX16 +XBUF<10> A<10> Z<10> VDD VSS / RSC_IHPSG13_WLDRVX16 +XBUF<9> A<9> Z<9> VDD VSS / RSC_IHPSG13_WLDRVX16 +XBUF<8> A<8> Z<8> VDD VSS / RSC_IHPSG13_WLDRVX16 +XBUF<7> A<7> Z<7> VDD VSS / RSC_IHPSG13_WLDRVX16 +XBUF<6> A<6> Z<6> VDD VSS / RSC_IHPSG13_WLDRVX16 +XBUF<5> A<5> Z<5> VDD VSS / RSC_IHPSG13_WLDRVX16 +XBUF<4> A<4> Z<4> VDD VSS / RSC_IHPSG13_WLDRVX16 +XBUF<3> A<3> Z<3> VDD VSS / RSC_IHPSG13_WLDRVX16 +XBUF<2> A<2> Z<2> VDD VSS / RSC_IHPSG13_WLDRVX16 +XBUF<1> A<1> Z<1> VDD VSS / RSC_IHPSG13_WLDRVX16 +XBUF<0> A<0> Z<0> VDD VSS / RSC_IHPSG13_WLDRVX16 +.ENDS + + +.SUBCKT RM_IHPSG13_256x8_c2_2P_COLDRV13X4 ADDR_COL_I<1> ADDR_COL_I<0> ADDR_COL_O<1> ++ ADDR_COL_O<0> ADDR_DEC_I<7> ADDR_DEC_I<6> ADDR_DEC_I<5> ADDR_DEC_I<4> ++ ADDR_DEC_I<3> ADDR_DEC_I<2> ADDR_DEC_I<1> ADDR_DEC_I<0> ADDR_DEC_O<7> ++ ADDR_DEC_O<6> ADDR_DEC_O<5> ADDR_DEC_O<4> ADDR_DEC_O<3> ADDR_DEC_O<2> ++ ADDR_DEC_O<1> ADDR_DEC_O<0> DCLK_I DCLK_O RCLK_I RCLK_O WCLK_I WCLK_O ++ VDD VSS +XWCLK_DRV WCLK_I WCLK_O VDD VSS / RSC_IHPSG13_CBUFX4 +XRCLK_DRV RCLK_I RCLK_O VDD VSS / RSC_IHPSG13_CBUFX4 +XDCLK_DRV DCLK_I DCLK_O VDD VSS / RSC_IHPSG13_CBUFX4 +XADDR_COL_DRV<1> ADDR_COL_I<1> ADDR_COL_O<1> VDD VSS / ++ RSC_IHPSG13_CBUFX4 +XADDR_COL_DRV<0> ADDR_COL_I<0> ADDR_COL_O<0> VDD VSS / ++ RSC_IHPSG13_CBUFX4 +XADDR_DEC_DRV<7> ADDR_DEC_I<7> ADDR_DEC_O<7> VDD VSS / ++ RSC_IHPSG13_CBUFX4 +XADDR_DEC_DRV<6> ADDR_DEC_I<6> ADDR_DEC_O<6> VDD VSS / ++ RSC_IHPSG13_CBUFX4 +XADDR_DEC_DRV<5> ADDR_DEC_I<5> ADDR_DEC_O<5> VDD VSS / ++ RSC_IHPSG13_CBUFX4 +XADDR_DEC_DRV<4> ADDR_DEC_I<4> ADDR_DEC_O<4> VDD VSS / ++ RSC_IHPSG13_CBUFX4 +XADDR_DEC_DRV<3> ADDR_DEC_I<3> ADDR_DEC_O<3> VDD VSS / ++ RSC_IHPSG13_CBUFX4 +XADDR_DEC_DRV<2> ADDR_DEC_I<2> ADDR_DEC_O<2> VDD VSS / ++ RSC_IHPSG13_CBUFX4 +XADDR_DEC_DRV<1> ADDR_DEC_I<1> ADDR_DEC_O<1> VDD VSS / ++ RSC_IHPSG13_CBUFX4 +XADDR_DEC_DRV<0> ADDR_DEC_I<0> ADDR_DEC_O<0> VDD VSS / ++ RSC_IHPSG13_CBUFX4 +XI0<6> VDD VSS / RSC_IHPSG13_FILLCAP4 +XI0<5> VDD VSS / RSC_IHPSG13_FILLCAP4 +XI0<4> VDD VSS / RSC_IHPSG13_FILLCAP4 +XI0<3> VDD VSS / RSC_IHPSG13_FILLCAP4 +XI0<2> VDD VSS / RSC_IHPSG13_FILLCAP4 +XI0<1> VDD VSS / RSC_IHPSG13_FILLCAP4 +XI1 VDD VSS / RSC_IHPSG13_FILLCAP8 +.ENDS +.SUBCKT RM_IHPSG13_256x8_c2_2P_WLDRV16X4 A<15> A<14> A<13> A<12> A<11> A<10> A<9> A<8> ++ A<7> A<6> A<5> A<4> A<3> A<2> A<1> A<0> Z<15> Z<14> Z<13> Z<12> Z<11> Z<10> ++ Z<9> Z<8> Z<7> Z<6> Z<5> Z<4> Z<3> Z<2> Z<1> Z<0> VDD VSS +XBUF<15> A<15> Z<15> VDD VSS / RSC_IHPSG13_WLDRVX4 +XBUF<14> A<14> Z<14> VDD VSS / RSC_IHPSG13_WLDRVX4 +XBUF<13> A<13> Z<13> VDD VSS / RSC_IHPSG13_WLDRVX4 +XBUF<12> A<12> Z<12> VDD VSS / RSC_IHPSG13_WLDRVX4 +XBUF<11> A<11> Z<11> VDD VSS / RSC_IHPSG13_WLDRVX4 +XBUF<10> A<10> Z<10> VDD VSS / RSC_IHPSG13_WLDRVX4 +XBUF<9> A<9> Z<9> VDD VSS / RSC_IHPSG13_WLDRVX4 +XBUF<8> A<8> Z<8> VDD VSS / RSC_IHPSG13_WLDRVX4 +XBUF<7> A<7> Z<7> VDD VSS / RSC_IHPSG13_WLDRVX4 +XBUF<6> A<6> Z<6> VDD VSS / RSC_IHPSG13_WLDRVX4 +XBUF<5> A<5> Z<5> VDD VSS / RSC_IHPSG13_WLDRVX4 +XBUF<4> A<4> Z<4> VDD VSS / RSC_IHPSG13_WLDRVX4 +XBUF<3> A<3> Z<3> VDD VSS / RSC_IHPSG13_WLDRVX4 +XBUF<2> A<2> Z<2> VDD VSS / RSC_IHPSG13_WLDRVX4 +XBUF<1> A<1> Z<1> VDD VSS / RSC_IHPSG13_WLDRVX4 +XBUF<0> A<0> Z<0> VDD VSS / RSC_IHPSG13_WLDRVX4 +.ENDS +.SUBCKT RM_IHPSG13_256x8_c2_2P_ROWDEC8 ADDR_N_I<7> ADDR_N_I<6> ADDR_N_I<5> ADDR_N_I<4> ++ ADDR_N_I<3> ADDR_N_I<2> ADDR_N_I<1> ADDR_N_I<0> CS_I ECLK_I WL_O<255> ++ WL_O<254> WL_O<253> WL_O<252> WL_O<251> WL_O<250> WL_O<249> WL_O<248> ++ WL_O<247> WL_O<246> WL_O<245> WL_O<244> WL_O<243> WL_O<242> WL_O<241> ++ WL_O<240> WL_O<239> WL_O<238> WL_O<237> WL_O<236> WL_O<235> WL_O<234> ++ WL_O<233> WL_O<232> WL_O<231> WL_O<230> WL_O<229> WL_O<228> WL_O<227> ++ WL_O<226> WL_O<225> WL_O<224> WL_O<223> WL_O<222> WL_O<221> WL_O<220> ++ WL_O<219> WL_O<218> WL_O<217> WL_O<216> WL_O<215> WL_O<214> WL_O<213> ++ WL_O<212> WL_O<211> WL_O<210> WL_O<209> WL_O<208> WL_O<207> WL_O<206> ++ WL_O<205> WL_O<204> WL_O<203> WL_O<202> WL_O<201> WL_O<200> WL_O<199> ++ WL_O<198> WL_O<197> WL_O<196> WL_O<195> WL_O<194> WL_O<193> WL_O<192> ++ WL_O<191> WL_O<190> WL_O<189> WL_O<188> WL_O<187> WL_O<186> WL_O<185> ++ WL_O<184> WL_O<183> WL_O<182> WL_O<181> WL_O<180> WL_O<179> WL_O<178> ++ WL_O<177> WL_O<176> WL_O<175> WL_O<174> WL_O<173> WL_O<172> WL_O<171> ++ WL_O<170> WL_O<169> WL_O<168> WL_O<167> WL_O<166> WL_O<165> WL_O<164> ++ WL_O<163> WL_O<162> WL_O<161> WL_O<160> WL_O<159> WL_O<158> WL_O<157> ++ WL_O<156> WL_O<155> WL_O<154> WL_O<153> WL_O<152> WL_O<151> WL_O<150> ++ WL_O<149> WL_O<148> WL_O<147> WL_O<146> WL_O<145> WL_O<144> WL_O<143> ++ WL_O<142> WL_O<141> WL_O<140> WL_O<139> WL_O<138> WL_O<137> WL_O<136> ++ WL_O<135> WL_O<134> WL_O<133> WL_O<132> WL_O<131> WL_O<130> WL_O<129> ++ WL_O<128> WL_O<127> WL_O<126> WL_O<125> WL_O<124> WL_O<123> WL_O<122> ++ WL_O<121> WL_O<120> WL_O<119> WL_O<118> WL_O<117> WL_O<116> WL_O<115> ++ WL_O<114> WL_O<113> WL_O<112> WL_O<111> WL_O<110> WL_O<109> WL_O<108> ++ WL_O<107> WL_O<106> WL_O<105> WL_O<104> WL_O<103> WL_O<102> WL_O<101> ++ WL_O<100> WL_O<99> WL_O<98> WL_O<97> WL_O<96> WL_O<95> WL_O<94> WL_O<93> ++ WL_O<92> WL_O<91> WL_O<90> WL_O<89> WL_O<88> WL_O<87> WL_O<86> WL_O<85> ++ WL_O<84> WL_O<83> WL_O<82> WL_O<81> WL_O<80> WL_O<79> WL_O<78> WL_O<77> ++ WL_O<76> WL_O<75> WL_O<74> WL_O<73> WL_O<72> WL_O<71> WL_O<70> WL_O<69> ++ WL_O<68> WL_O<67> WL_O<66> WL_O<65> WL_O<64> WL_O<63> WL_O<62> WL_O<61> ++ WL_O<60> WL_O<59> WL_O<58> WL_O<57> WL_O<56> WL_O<55> WL_O<54> WL_O<53> ++ WL_O<52> WL_O<51> WL_O<50> WL_O<49> WL_O<48> WL_O<47> WL_O<46> WL_O<45> ++ WL_O<44> WL_O<43> WL_O<42> WL_O<41> WL_O<40> WL_O<39> WL_O<38> WL_O<37> ++ WL_O<36> WL_O<35> WL_O<34> WL_O<33> WL_O<32> WL_O<31> WL_O<30> WL_O<29> ++ WL_O<28> WL_O<27> WL_O<26> WL_O<25> WL_O<24> WL_O<23> WL_O<22> WL_O<21> ++ WL_O<20> WL_O<19> WL_O<18> WL_O<17> WL_O<16> WL_O<15> WL_O<14> WL_O<13> ++ WL_O<12> WL_O<11> WL_O<10> WL_O<9> WL_O<8> WL_O<7> WL_O<6> WL_O<5> WL_O<4> ++ WL_O<3> WL_O<2> WL_O<1> WL_O<0> VDD VSS +XDEC11<4> ADDR_N_I<7> ADDR_N_I<6> CS_I CS04<3> VDD VSS / ++ RM_IHPSG13_256x8_c2_2P_DEC03 +XDEC11<3> ADDR_N_I<5> ADDR_N_I<4> CS04<3> CS00<15> VDD VSS / ++ RM_IHPSG13_256x8_c2_2P_DEC03 +XDEC11<2> ADDR_N_I<5> ADDR_N_I<4> CS04<2> CS00<11> VDD VSS / ++ RM_IHPSG13_256x8_c2_2P_DEC03 +XDEC11<1> ADDR_N_I<5> ADDR_N_I<4> CS04<1> CS00<7> VDD VSS / ++ RM_IHPSG13_256x8_c2_2P_DEC03 +XDEC11<0> ADDR_N_I<5> ADDR_N_I<4> CS04<0> CS00<3> VDD VSS / ++ RM_IHPSG13_256x8_c2_2P_DEC03 +XSEL<15> ADDR_N_I<3> ADDR_N_I<2> ADDR_N_I<1> ADDR_N_I<0> CS00<15> ECLK_H<15> ++ ECLK_H<16> ECLK_B<15> ECLK_B<16> WL_O<255> WL_O<254> WL_O<253> WL_O<252> ++ WL_O<251> WL_O<250> WL_O<249> WL_O<248> WL_O<247> WL_O<246> WL_O<245> ++ WL_O<244> WL_O<243> WL_O<242> WL_O<241> WL_O<240> VDD VSS / ++ RM_IHPSG13_256x8_c2_2P_DEC04 +XSEL<14> ADDR_N_I<3> ADDR_N_I<2> ADDR_N_I<1> ADDR_N_I<0> CS00<14> ECLK_H<14> ++ ECLK_H<15> ECLK_B<14> ECLK_B<15> WL_O<239> WL_O<238> WL_O<237> WL_O<236> ++ WL_O<235> WL_O<234> WL_O<233> WL_O<232> WL_O<231> WL_O<230> WL_O<229> ++ WL_O<228> WL_O<227> WL_O<226> WL_O<225> WL_O<224> VDD VSS / ++ RM_IHPSG13_256x8_c2_2P_DEC04 +XSEL<13> ADDR_N_I<3> ADDR_N_I<2> ADDR_N_I<1> ADDR_N_I<0> CS00<13> ECLK_H<13> ++ ECLK_H<14> ECLK_B<13> ECLK_B<14> WL_O<223> WL_O<222> WL_O<221> WL_O<220> ++ WL_O<219> WL_O<218> WL_O<217> WL_O<216> WL_O<215> WL_O<214> WL_O<213> ++ WL_O<212> WL_O<211> WL_O<210> WL_O<209> WL_O<208> VDD VSS / ++ RM_IHPSG13_256x8_c2_2P_DEC04 +XSEL<12> ADDR_N_I<3> ADDR_N_I<2> ADDR_N_I<1> ADDR_N_I<0> CS00<12> ECLK_H<12> ++ ECLK_H<13> ECLK_B<12> ECLK_B<13> WL_O<207> WL_O<206> WL_O<205> WL_O<204> ++ WL_O<203> WL_O<202> WL_O<201> WL_O<200> WL_O<199> WL_O<198> WL_O<197> ++ WL_O<196> WL_O<195> WL_O<194> WL_O<193> WL_O<192> VDD VSS / ++ RM_IHPSG13_256x8_c2_2P_DEC04 +XSEL<11> ADDR_N_I<3> ADDR_N_I<2> ADDR_N_I<1> ADDR_N_I<0> CS00<11> ECLK_H<11> ++ ECLK_H<12> ECLK_B<11> ECLK_B<12> WL_O<191> WL_O<190> WL_O<189> WL_O<188> ++ WL_O<187> WL_O<186> WL_O<185> WL_O<184> WL_O<183> WL_O<182> WL_O<181> ++ WL_O<180> WL_O<179> WL_O<178> WL_O<177> WL_O<176> VDD VSS / ++ RM_IHPSG13_256x8_c2_2P_DEC04 +XSEL<10> ADDR_N_I<3> ADDR_N_I<2> ADDR_N_I<1> ADDR_N_I<0> CS00<10> ECLK_H<10> ++ ECLK_H<11> ECLK_B<10> ECLK_B<11> WL_O<175> WL_O<174> WL_O<173> WL_O<172> ++ WL_O<171> WL_O<170> WL_O<169> WL_O<168> WL_O<167> WL_O<166> WL_O<165> ++ WL_O<164> WL_O<163> WL_O<162> WL_O<161> WL_O<160> VDD VSS / ++ RM_IHPSG13_256x8_c2_2P_DEC04 +XSEL<9> ADDR_N_I<3> ADDR_N_I<2> ADDR_N_I<1> ADDR_N_I<0> CS00<9> ECLK_H<9> ++ ECLK_H<10> ECLK_B<9> ECLK_B<10> WL_O<159> WL_O<158> WL_O<157> WL_O<156> ++ WL_O<155> WL_O<154> WL_O<153> WL_O<152> WL_O<151> WL_O<150> WL_O<149> ++ WL_O<148> WL_O<147> WL_O<146> WL_O<145> WL_O<144> VDD VSS / ++ RM_IHPSG13_256x8_c2_2P_DEC04 +XSEL<8> ADDR_N_I<3> ADDR_N_I<2> ADDR_N_I<1> ADDR_N_I<0> CS00<8> ECLK_H<8> ++ ECLK_H<9> ECLK_B<8> ECLK_B<9> WL_O<143> WL_O<142> WL_O<141> WL_O<140> ++ WL_O<139> WL_O<138> WL_O<137> WL_O<136> WL_O<135> WL_O<134> WL_O<133> ++ WL_O<132> WL_O<131> WL_O<130> WL_O<129> WL_O<128> VDD VSS / ++ RM_IHPSG13_256x8_c2_2P_DEC04 +XSEL<7> ADDR_N_I<3> ADDR_N_I<2> ADDR_N_I<1> ADDR_N_I<0> CS00<7> ECLK_H<7> ++ ECLK_H<8> ECLK_B<7> ECLK_B<8> WL_O<127> WL_O<126> WL_O<125> WL_O<124> ++ WL_O<123> WL_O<122> WL_O<121> WL_O<120> WL_O<119> WL_O<118> WL_O<117> ++ WL_O<116> WL_O<115> WL_O<114> WL_O<113> WL_O<112> VDD VSS / ++ RM_IHPSG13_256x8_c2_2P_DEC04 +XSEL<6> ADDR_N_I<3> ADDR_N_I<2> ADDR_N_I<1> ADDR_N_I<0> CS00<6> ECLK_H<6> ++ ECLK_H<7> ECLK_B<6> ECLK_B<7> WL_O<111> WL_O<110> WL_O<109> WL_O<108> ++ WL_O<107> WL_O<106> WL_O<105> WL_O<104> WL_O<103> WL_O<102> WL_O<101> ++ WL_O<100> WL_O<99> WL_O<98> WL_O<97> WL_O<96> VDD VSS / ++ RM_IHPSG13_256x8_c2_2P_DEC04 +XSEL<5> ADDR_N_I<3> ADDR_N_I<2> ADDR_N_I<1> ADDR_N_I<0> CS00<5> ECLK_H<5> ++ ECLK_H<6> ECLK_B<5> ECLK_B<6> WL_O<95> WL_O<94> WL_O<93> WL_O<92> WL_O<91> ++ WL_O<90> WL_O<89> WL_O<88> WL_O<87> WL_O<86> WL_O<85> WL_O<84> WL_O<83> ++ WL_O<82> WL_O<81> WL_O<80> VDD VSS / RM_IHPSG13_256x8_c2_2P_DEC04 +XSEL<4> ADDR_N_I<3> ADDR_N_I<2> ADDR_N_I<1> ADDR_N_I<0> CS00<4> ECLK_H<4> ++ ECLK_H<5> ECLK_B<4> ECLK_B<5> WL_O<79> WL_O<78> WL_O<77> WL_O<76> WL_O<75> ++ WL_O<74> WL_O<73> WL_O<72> WL_O<71> WL_O<70> WL_O<69> WL_O<68> WL_O<67> ++ WL_O<66> WL_O<65> WL_O<64> VDD VSS / RM_IHPSG13_256x8_c2_2P_DEC04 +XSEL<3> ADDR_N_I<3> ADDR_N_I<2> ADDR_N_I<1> ADDR_N_I<0> CS00<3> ECLK_H<3> ++ ECLK_H<4> ECLK_B<3> ECLK_B<4> WL_O<63> WL_O<62> WL_O<61> WL_O<60> WL_O<59> ++ WL_O<58> WL_O<57> WL_O<56> WL_O<55> WL_O<54> WL_O<53> WL_O<52> WL_O<51> ++ WL_O<50> WL_O<49> WL_O<48> VDD VSS / RM_IHPSG13_256x8_c2_2P_DEC04 +XSEL<2> ADDR_N_I<3> ADDR_N_I<2> ADDR_N_I<1> ADDR_N_I<0> CS00<2> ECLK_H<2> ++ ECLK_H<3> ECLK_B<2> ECLK_B<3> WL_O<47> WL_O<46> WL_O<45> WL_O<44> WL_O<43> ++ WL_O<42> WL_O<41> WL_O<40> WL_O<39> WL_O<38> WL_O<37> WL_O<36> WL_O<35> ++ WL_O<34> WL_O<33> WL_O<32> VDD VSS / RM_IHPSG13_256x8_c2_2P_DEC04 +XSEL<1> ADDR_N_I<3> ADDR_N_I<2> ADDR_N_I<1> ADDR_N_I<0> CS00<1> ECLK_H<1> ++ ECLK_H<2> ECLK_B<1> ECLK_B<2> WL_O<31> WL_O<30> WL_O<29> WL_O<28> WL_O<27> ++ WL_O<26> WL_O<25> WL_O<24> WL_O<23> WL_O<22> WL_O<21> WL_O<20> WL_O<19> ++ WL_O<18> WL_O<17> WL_O<16> VDD VSS / RM_IHPSG13_256x8_c2_2P_DEC04 +XSEL<0> ADDR_N_I<3> ADDR_N_I<2> ADDR_N_I<1> ADDR_N_I<0> CS00<0> ECLK_I ++ ECLK_H<1> ECLK_B<0> ECLK_B<1> WL_O<15> WL_O<14> WL_O<13> WL_O<12> WL_O<11> ++ WL_O<10> WL_O<9> WL_O<8> WL_O<7> WL_O<6> WL_O<5> WL_O<4> WL_O<3> WL_O<2> ++ WL_O<1> WL_O<0> VDD VSS / RM_IHPSG13_256x8_c2_2P_DEC04 +XDEC10<4> ADDR_N_I<7> ADDR_N_I<6> CS_I CS04<2> VDD VSS / ++ RM_IHPSG13_256x8_c2_2P_DEC02 +XDEC10<3> ADDR_N_I<5> ADDR_N_I<4> CS04<3> CS00<14> VDD VSS / ++ RM_IHPSG13_256x8_c2_2P_DEC02 +XDEC10<2> ADDR_N_I<5> ADDR_N_I<4> CS04<2> CS00<10> VDD VSS / ++ RM_IHPSG13_256x8_c2_2P_DEC02 +XDEC10<1> ADDR_N_I<5> ADDR_N_I<4> CS04<1> CS00<6> VDD VSS / ++ RM_IHPSG13_256x8_c2_2P_DEC02 +XDEC10<0> ADDR_N_I<5> ADDR_N_I<4> CS04<0> CS00<2> VDD VSS / ++ RM_IHPSG13_256x8_c2_2P_DEC02 +XL2<132> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<131> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<130> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<129> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<128> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<127> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<126> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<125> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<124> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<123> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<122> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<121> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<120> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<119> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<118> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<117> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<116> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<115> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<114> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<113> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<112> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<111> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<110> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<109> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<108> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<107> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<106> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<105> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<104> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<103> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<102> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<101> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<100> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<99> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<98> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<97> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<96> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<95> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<94> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<93> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<92> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<91> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<90> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<89> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<88> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<87> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<86> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<85> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<84> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<83> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<82> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<81> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<80> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<79> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<78> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<77> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<76> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<75> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<74> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<73> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<72> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<71> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<70> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<69> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<68> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<67> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<66> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<65> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<64> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<63> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<62> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<61> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<60> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<59> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<58> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<57> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<56> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<55> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<54> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<53> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<52> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<51> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<50> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<49> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<48> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<47> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<46> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<45> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<44> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<43> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<42> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<41> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<40> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<39> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<38> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<37> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<36> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<35> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<34> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<33> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<32> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<31> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<30> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<29> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<28> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<27> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<26> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<25> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<24> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<23> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<22> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<21> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<20> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<19> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<18> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<17> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<16> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<15> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<14> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<13> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<12> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<11> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<10> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<9> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<8> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<7> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<6> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<5> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<4> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<3> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<2> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<1> VDD VSS / RSC_IHPSG13_FILLCAP8 +XDEC00<4> ADDR_N_I<7> ADDR_N_I<6> CS_I CS04<0> VDD VSS / ++ RM_IHPSG13_256x8_c2_2P_DEC00 +XDEC00<3> ADDR_N_I<5> ADDR_N_I<4> CS04<3> CS00<12> VDD VSS / ++ RM_IHPSG13_256x8_c2_2P_DEC00 +XDEC00<2> ADDR_N_I<5> ADDR_N_I<4> CS04<2> CS00<8> VDD VSS / ++ RM_IHPSG13_256x8_c2_2P_DEC00 +XDEC00<1> ADDR_N_I<5> ADDR_N_I<4> CS04<1> CS00<4> VDD VSS / ++ RM_IHPSG13_256x8_c2_2P_DEC00 +XDEC00<0> ADDR_N_I<5> ADDR_N_I<4> CS04<0> CS00<0> VDD VSS / ++ RM_IHPSG13_256x8_c2_2P_DEC00 +XDEC01<4> ADDR_N_I<7> ADDR_N_I<6> CS_I CS04<1> VDD VSS / ++ RM_IHPSG13_256x8_c2_2P_DEC01 +XDEC01<3> ADDR_N_I<5> ADDR_N_I<4> CS04<3> CS00<13> VDD VSS / ++ RM_IHPSG13_256x8_c2_2P_DEC01 +XDEC01<2> ADDR_N_I<5> ADDR_N_I<4> CS04<2> CS00<9> VDD VSS / ++ RM_IHPSG13_256x8_c2_2P_DEC01 +XDEC01<1> ADDR_N_I<5> ADDR_N_I<4> CS04<1> CS00<5> VDD VSS / ++ RM_IHPSG13_256x8_c2_2P_DEC01 +XDEC01<0> ADDR_N_I<5> ADDR_N_I<4> CS04<0> CS00<1> VDD VSS / ++ RM_IHPSG13_256x8_c2_2P_DEC01 +.ENDS +.SUBCKT RM_IHPSG13_256x8_c2_2P_ROWREG8 ACLK_N_I ADDR_I<7> ADDR_I<6> ADDR_I<5> ADDR_I<4> ++ ADDR_I<3> ADDR_I<2> ADDR_I<1> ADDR_I<0> ADDR_N_O<7> ADDR_N_O<6> ADDR_N_O<5> ++ ADDR_N_O<4> ADDR_N_O<3> ADDR_N_O<2> ADDR_N_O<1> ADDR_N_O<0> BIST_ADDR_I<7> ++ BIST_ADDR_I<6> BIST_ADDR_I<5> BIST_ADDR_I<4> BIST_ADDR_I<3> BIST_ADDR_I<2> ++ BIST_ADDR_I<1> BIST_ADDR_I<0> BIST_EN_I VDD VSS +XINV<7> q_int<7> qn_int<7> VDD VSS / RSC_IHPSG13_CINVX2 +XINV<6> q_int<6> qn_int<6> VDD VSS / RSC_IHPSG13_CINVX2 +XINV<5> q_int<5> qn_int<5> VDD VSS / RSC_IHPSG13_CINVX2 +XINV<4> q_int<4> qn_int<4> VDD VSS / RSC_IHPSG13_CINVX2 +XINV<3> q_int<3> qn_int<3> VDD VSS / RSC_IHPSG13_CINVX2 +XINV<2> q_int<2> qn_int<2> VDD VSS / RSC_IHPSG13_CINVX2 +XINV<1> q_int<1> qn_int<1> VDD VSS / RSC_IHPSG13_CINVX2 +XINV<0> q_int<0> qn_int<0> VDD VSS / RSC_IHPSG13_CINVX2 +XDRV<7> qn_int<7> ADDR_N_O<7> VDD VSS / RSC_IHPSG13_CINVX8 +XDRV<6> qn_int<6> ADDR_N_O<6> VDD VSS / RSC_IHPSG13_CINVX8 +XDRV<5> qn_int<5> ADDR_N_O<5> VDD VSS / RSC_IHPSG13_CINVX8 +XDRV<4> qn_int<4> ADDR_N_O<4> VDD VSS / RSC_IHPSG13_CINVX8 +XDRV<3> qn_int<3> ADDR_N_O<3> VDD VSS / RSC_IHPSG13_CINVX8 +XDRV<2> qn_int<2> ADDR_N_O<2> VDD VSS / RSC_IHPSG13_CINVX8 +XDRV<1> qn_int<1> ADDR_N_O<1> VDD VSS / RSC_IHPSG13_CINVX8 +XDRV<0> qn_int<0> ADDR_N_O<0> VDD VSS / RSC_IHPSG13_CINVX8 +XDFF<7> BIST_EN_I BIST_ADDR_I<7> ACLK_N_I ADDR_I<7> q_int<7> net2<0> VDD ++ VSS / RSC_IHPSG13_DFNQMX2IX1 +XDFF<6> BIST_EN_I BIST_ADDR_I<6> ACLK_N_I ADDR_I<6> q_int<6> net2<1> VDD ++ VSS / RSC_IHPSG13_DFNQMX2IX1 +XDFF<5> BIST_EN_I BIST_ADDR_I<5> ACLK_N_I ADDR_I<5> q_int<5> net2<2> VDD ++ VSS / RSC_IHPSG13_DFNQMX2IX1 +XDFF<4> BIST_EN_I BIST_ADDR_I<4> ACLK_N_I ADDR_I<4> q_int<4> net2<3> VDD ++ VSS / RSC_IHPSG13_DFNQMX2IX1 +XDFF<3> BIST_EN_I BIST_ADDR_I<3> ACLK_N_I ADDR_I<3> q_int<3> net2<4> VDD ++ VSS / RSC_IHPSG13_DFNQMX2IX1 +XDFF<2> BIST_EN_I BIST_ADDR_I<2> ACLK_N_I ADDR_I<2> q_int<2> net2<5> VDD ++ VSS / RSC_IHPSG13_DFNQMX2IX1 +XDFF<1> BIST_EN_I BIST_ADDR_I<1> ACLK_N_I ADDR_I<1> q_int<1> net2<6> VDD ++ VSS / RSC_IHPSG13_DFNQMX2IX1 +XDFF<0> BIST_EN_I BIST_ADDR_I<0> ACLK_N_I ADDR_I<0> q_int<0> net2<7> VDD ++ VSS / RSC_IHPSG13_DFNQMX2IX1 +XI11<4> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI11<3> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI11<2> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI11<1> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI10 VDD VSS / RSC_IHPSG13_FILLCAP4 +.ENDS +.SUBCKT RM_IHPSG13_256x8_c2_2P_COLDEC4 ACLK_N ADDR<3> ADDR<2> ADDR<1> ADDR<0> ++ ADDR_COL<1> ADDR_COL<0> ADDR_DEC<7> ADDR_DEC<6> ADDR_DEC<5> ADDR_DEC<4> ++ ADDR_DEC<3> ADDR_DEC<2> ADDR_DEC<1> ADDR_DEC<0> BIST_ADDR<3> BIST_ADDR<2> ++ BIST_ADDR<1> BIST_ADDR<0> BIST_EN_I VDD VSS +XI1<7> PADR<0> PADR<1> PADR<2> addr_n<7> VDD VSS / RSC_IHPSG13_NAND3X2 +XI1<6> NADR<0> PADR<1> PADR<2> addr_n<6> VDD VSS / RSC_IHPSG13_NAND3X2 +XI1<5> PADR<0> NADR<1> PADR<2> addr_n<5> VDD VSS / RSC_IHPSG13_NAND3X2 +XI1<4> NADR<0> NADR<1> PADR<2> addr_n<4> VDD VSS / RSC_IHPSG13_NAND3X2 +XI1<3> PADR<0> PADR<1> NADR<2> addr_n<3> VDD VSS / RSC_IHPSG13_NAND3X2 +XI1<2> NADR<0> PADR<1> NADR<2> addr_n<2> VDD VSS / RSC_IHPSG13_NAND3X2 +XI1<1> PADR<0> NADR<1> NADR<2> addr_n<1> VDD VSS / RSC_IHPSG13_NAND3X2 +XI1<0> NADR<0> NADR<1> NADR<2> addr_n<0> VDD VSS / RSC_IHPSG13_NAND3X2 +XDFF<3> BIST_EN_I BIST_ADDR<3> ACLK_N ADDR<3> addr_int net12<0> VDD ++ VSS / RSC_IHPSG13_DFNQMX2IX1 +XDFF<2> BIST_EN_I BIST_ADDR<2> ACLK_N ADDR<2> padr_int<2> net12<1> VDD ++ VSS / RSC_IHPSG13_DFNQMX2IX1 +XDFF<1> BIST_EN_I BIST_ADDR<1> ACLK_N ADDR<1> padr_int<1> net12<2> VDD ++ VSS / RSC_IHPSG13_DFNQMX2IX1 +XDFF<0> BIST_EN_I BIST_ADDR<0> ACLK_N ADDR<0> padr_int<0> net12<3> VDD ++ VSS / RSC_IHPSG13_DFNQMX2IX1 +XI17<4> VDD VSS / RSC_IHPSG13_FILLCAP4 +XI17<3> VDD VSS / RSC_IHPSG13_FILLCAP4 +XI17<2> VDD VSS / RSC_IHPSG13_FILLCAP4 +XI17<1> VDD VSS / RSC_IHPSG13_FILLCAP4 +XI13<2> NADR<2> PADR<2> VDD VSS / RSC_IHPSG13_INVX2 +XI13<1> NADR<1> PADR<1> VDD VSS / RSC_IHPSG13_INVX2 +XI13<0> NADR<0> PADR<0> VDD VSS / RSC_IHPSG13_INVX2 +XI2<7> addr_n<7> ADDR_DEC<7> VDD VSS / RSC_IHPSG13_INVX2 +XI2<6> addr_n<6> ADDR_DEC<6> VDD VSS / RSC_IHPSG13_INVX2 +XI2<5> addr_n<5> ADDR_DEC<5> VDD VSS / RSC_IHPSG13_INVX2 +XI2<4> addr_n<4> ADDR_DEC<4> VDD VSS / RSC_IHPSG13_INVX2 +XI2<3> addr_n<3> ADDR_DEC<3> VDD VSS / RSC_IHPSG13_INVX2 +XI2<2> addr_n<2> ADDR_DEC<2> VDD VSS / RSC_IHPSG13_INVX2 +XI2<1> addr_n<1> ADDR_DEC<1> VDD VSS / RSC_IHPSG13_INVX2 +XI2<0> addr_n<0> ADDR_DEC<0> VDD VSS / RSC_IHPSG13_INVX2 +XI3<2> padr_int<2> NADR<2> VDD VSS / RSC_IHPSG13_INVX2 +XI3<1> padr_int<1> NADR<1> VDD VSS / RSC_IHPSG13_INVX2 +XI3<0> padr_int<0> NADR<0> VDD VSS / RSC_IHPSG13_INVX2 +XI14 addr_int ADDR_COL<0> VDD VSS / RSC_IHPSG13_CBUFX2 +XI16<8> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI16<7> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI16<6> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI16<5> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI16<4> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI16<3> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI16<2> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI16<1> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI15 ADDR_COL<1> VDD VSS / RSC_IHPSG13_TIEL +.ENDS +.SUBCKT RM_IHPSG13_256x8_c2_2P_COLCTRL4 A_ADDR_COL A_ADDR_DEC<7> A_ADDR_DEC<6> ++ A_ADDR_DEC<5> A_ADDR_DEC<4> A_ADDR_DEC<3> A_ADDR_DEC<2> A_ADDR_DEC<1> ++ A_ADDR_DEC<0> A_BIST_BM_I A_BIST_DW_I A_BIST_EN_I A_BLC<15> A_BLC<14> ++ A_BLC<13> A_BLC<12> A_BLC<11> A_BLC<10> A_BLC<9> A_BLC<8> A_BLC<7> A_BLC<6> ++ A_BLC<5> A_BLC<4> A_BLC<3> A_BLC<2> A_BLC<1> A_BLC<0> A_BLT<15> A_BLT<14> ++ A_BLT<13> A_BLT<12> A_BLT<11> A_BLT<10> A_BLT<9> A_BLT<8> A_BLT<7> A_BLT<6> ++ A_BLT<5> A_BLT<4> A_BLT<3> A_BLT<2> A_BLT<1> A_BLT<0> A_BM_I A_DCLK_B_L ++ A_DCLK_B_R A_DCLK_L A_DCLK_R A_DR_O A_DW_I A_RCLK_B_L A_RCLK_B_R A_RCLK_L ++ A_RCLK_R A_TIEH_O A_WCLK_B_L A_WCLK_B_R A_WCLK_L A_WCLK_R B_ADDR_COL ++ B_ADDR_DEC<7> B_ADDR_DEC<6> B_ADDR_DEC<5> B_ADDR_DEC<4> B_ADDR_DEC<3> ++ B_ADDR_DEC<2> B_ADDR_DEC<1> B_ADDR_DEC<0> B_BIST_BM_I B_BIST_DW_I ++ B_BIST_EN_I B_BLC<15> B_BLC<14> B_BLC<13> B_BLC<12> B_BLC<11> B_BLC<10> ++ B_BLC<9> B_BLC<8> B_BLC<7> B_BLC<6> B_BLC<5> B_BLC<4> B_BLC<3> B_BLC<2> ++ B_BLC<1> B_BLC<0> B_BLT<15> B_BLT<14> B_BLT<13> B_BLT<12> B_BLT<11> ++ B_BLT<10> B_BLT<9> B_BLT<8> B_BLT<7> B_BLT<6> B_BLT<5> B_BLT<4> B_BLT<3> ++ B_BLT<2> B_BLT<1> B_BLT<0> B_BM_I B_DCLK_B_L B_DCLK_B_R B_DCLK_L B_DCLK_R ++ B_DR_O B_DW_I B_RCLK_B_L B_RCLK_B_R B_RCLK_L B_RCLK_R B_TIEH_O B_WCLK_B_L ++ B_WCLK_B_R B_WCLK_L B_WCLK_R VDD VSS +XB_I80 B_RCLK_B_L B_WCLK_B_L net041 VDD VSS / RSC_IHPSG13_AND2X2 +XA_I80 A_RCLK_B_L A_WCLK_B_L net21 VDD VSS / RSC_IHPSG13_AND2X2 +XB_I76 B_DI_N B_DO_WRITE_P B_WR_ZERO VDD VSS / RSC_IHPSG13_AND2X4 +XB_I75 B_DI_R B_DO_WRITE_P B_WR_ONE VDD VSS / RSC_IHPSG13_AND2X4 +XA_I76 A_DI_N A_DO_WRITE_P A_WR_ZERO VDD VSS / RSC_IHPSG13_AND2X4 +XA_I75 A_DI_R A_DO_WRITE_P A_WR_ONE VDD VSS / RSC_IHPSG13_AND2X4 +XI_FILL4<26> VDD VSS / RSC_IHPSG13_FILLCAP4 +XI_FILL4<25> VDD VSS / RSC_IHPSG13_FILLCAP4 +XI_FILL4<24> VDD VSS / RSC_IHPSG13_FILLCAP4 +XI_FILL4<23> VDD VSS / RSC_IHPSG13_FILLCAP4 +XI_FILL4<22> VDD VSS / RSC_IHPSG13_FILLCAP4 +XI_FILL4<21> VDD VSS / RSC_IHPSG13_FILLCAP4 +XI_FILL4<20> VDD VSS / RSC_IHPSG13_FILLCAP4 +XI_FILL4<19> VDD VSS / RSC_IHPSG13_FILLCAP4 +XI_FILL4<18> VDD VSS / RSC_IHPSG13_FILLCAP4 +XI_FILL4<17> VDD VSS / RSC_IHPSG13_FILLCAP4 +XI_FILL4<16> VDD VSS / RSC_IHPSG13_FILLCAP4 +XI_FILL4<15> VDD VSS / RSC_IHPSG13_FILLCAP4 +XI_FILL4<14> VDD VSS / RSC_IHPSG13_FILLCAP4 +XI_FILL4<13> VDD VSS / RSC_IHPSG13_FILLCAP4 +XI_FILL4<12> VDD VSS / RSC_IHPSG13_FILLCAP4 +XI_FILL4<11> VDD VSS / RSC_IHPSG13_FILLCAP4 +XI_FILL4<10> VDD VSS / RSC_IHPSG13_FILLCAP4 +XI_FILL4<9> VDD VSS / RSC_IHPSG13_FILLCAP4 +XI_FILL4<8> VDD VSS / RSC_IHPSG13_FILLCAP4 +XI_FILL4<7> VDD VSS / RSC_IHPSG13_FILLCAP4 +XI_FILL4<6> VDD VSS / RSC_IHPSG13_FILLCAP4 +XI_FILL4<5> VDD VSS / RSC_IHPSG13_FILLCAP4 +XI_FILL4<4> VDD VSS / RSC_IHPSG13_FILLCAP4 +XI_FILL4<3> VDD VSS / RSC_IHPSG13_FILLCAP4 +XI_FILL4<2> VDD VSS / RSC_IHPSG13_FILLCAP4 +XI_FILL4<1> VDD VSS / RSC_IHPSG13_FILLCAP4 +XB_I69 B_DCLK_L B_DCLK_B_L VDD VSS / RSC_IHPSG13_CINVX4 +XB_I50 B_WCLK_L B_WCLK_B_L VDD VSS / RSC_IHPSG13_CINVX4 +XB_EBUF B_RCLK_L B_RCLK_B_L VDD VSS / RSC_IHPSG13_CINVX4 +XB_INV<1> B_N0 B_P0 VDD VSS / RSC_IHPSG13_CINVX4 +XB_INV<0> B_ADDR_COL B_N0 VDD VSS / RSC_IHPSG13_CINVX4 +XA_I69 A_DCLK_L A_DCLK_B_L VDD VSS / RSC_IHPSG13_CINVX4 +XA_I50 A_WCLK_L A_WCLK_B_L VDD VSS / RSC_IHPSG13_CINVX4 +XA_EBUF A_RCLK_L A_RCLK_B_L VDD VSS / RSC_IHPSG13_CINVX4 +XA_INV<1> A_N0 A_P0 VDD VSS / RSC_IHPSG13_CINVX4 +XA_INV<0> A_ADDR_COL A_N0 VDD VSS / RSC_IHPSG13_CINVX4 +XB_I81<1> net041 B_PRE_N VDD VSS / RSC_IHPSG13_CINVX4_WN +XB_I81<0> net041 B_PRE_N VDD VSS / RSC_IHPSG13_CINVX4_WN +XA_I81<1> net21 A_PRE_N VDD VSS / RSC_IHPSG13_CINVX4_WN +XA_I81<0> net21 A_PRE_N VDD VSS / RSC_IHPSG13_CINVX4_WN +XA_R2 A_RCLK_L A_RCLK_R / RSC_IHPSG13_MET3RES +XA_I87 A_WCLK_L A_WCLK_R / RSC_IHPSG13_MET3RES +XA_I88 A_DCLK_L A_DCLK_R / RSC_IHPSG13_MET3RES +XA_I89 A_DCLK_B_L A_DCLK_B_R / RSC_IHPSG13_MET3RES +XA_I90 A_WCLK_B_L A_WCLK_B_R / RSC_IHPSG13_MET3RES +XA_I91 A_RCLK_B_L A_RCLK_B_R / RSC_IHPSG13_MET3RES +XB_R2 B_RCLK_L B_RCLK_R / RSC_IHPSG13_MET3RES +XB_I87 B_WCLK_L B_WCLK_R / RSC_IHPSG13_MET3RES +XB_I88 B_DCLK_L B_DCLK_R / RSC_IHPSG13_MET3RES +XB_I89 B_DCLK_B_L B_DCLK_B_R / RSC_IHPSG13_MET3RES +XB_I90 B_WCLK_B_L B_WCLK_B_R / RSC_IHPSG13_MET3RES +XB_I91 B_RCLK_B_L B_RCLK_B_R / RSC_IHPSG13_MET3RES +XA_ISENSE A_SAE A_BLC_SEL A_BLT_SEL net19 net20 VDD VSS / ++ RSC_IHPSG13_DFPQD_MSAFFX2 +XB_ISENSE B_SAE B_BLC_SEL B_BLT_SEL net037 net038 VDD VSS / ++ RSC_IHPSG13_DFPQD_MSAFFX2 +XAB_BLMUX<3> A_BLC<15> A_BLC<14> A_BLC<13> A_BLC<12> A_BLC_SEL A_BLT<15> ++ A_BLT<14> A_BLT<13> A_BLT<12> A_BLT_SEL A_PRE_N A_SEL_P<15> A_SEL_P<14> ++ A_SEL_P<13> A_SEL_P<12> A_WR_ONE A_WR_ZERO B_BLC<15> B_BLC<14> B_BLC<13> ++ B_BLC<12> B_BLC_SEL B_BLT<15> B_BLT<14> B_BLT<13> B_BLT<12> B_BLT_SEL ++ B_PRE_N B_SEL_P<15> B_SEL_P<14> B_SEL_P<13> B_SEL_P<12> B_WR_ONE B_WR_ZERO ++ VDD VSS / RM_IHPSG13_256x8_c2_2P_BLDRV +XAB_BLMUX<2> A_BLC<11> A_BLC<10> A_BLC<9> A_BLC<8> A_BLC_SEL A_BLT<11> ++ A_BLT<10> A_BLT<9> A_BLT<8> A_BLT_SEL A_PRE_N A_SEL_P<11> A_SEL_P<10> ++ A_SEL_P<9> A_SEL_P<8> A_WR_ONE A_WR_ZERO B_BLC<11> B_BLC<10> B_BLC<9> ++ B_BLC<8> B_BLC_SEL B_BLT<11> B_BLT<10> B_BLT<9> B_BLT<8> B_BLT_SEL B_PRE_N ++ B_SEL_P<11> B_SEL_P<10> B_SEL_P<9> B_SEL_P<8> B_WR_ONE B_WR_ZERO VDD ++ VSS / RM_IHPSG13_256x8_c2_2P_BLDRV +XAB_BLMUX<1> A_BLC<7> A_BLC<6> A_BLC<5> A_BLC<4> A_BLC_SEL A_BLT<7> A_BLT<6> ++ A_BLT<5> A_BLT<4> A_BLT_SEL A_PRE_N A_SEL_P<7> A_SEL_P<6> A_SEL_P<5> ++ A_SEL_P<4> A_WR_ONE A_WR_ZERO B_BLC<7> B_BLC<6> B_BLC<5> B_BLC<4> B_BLC_SEL ++ B_BLT<7> B_BLT<6> B_BLT<5> B_BLT<4> B_BLT_SEL B_PRE_N B_SEL_P<7> B_SEL_P<6> ++ B_SEL_P<5> B_SEL_P<4> B_WR_ONE B_WR_ZERO VDD VSS / ++ RM_IHPSG13_256x8_c2_2P_BLDRV +XAB_BLMUX<0> A_BLC<3> A_BLC<2> A_BLC<1> A_BLC<0> A_BLC_SEL A_BLT<3> A_BLT<2> ++ A_BLT<1> A_BLT<0> A_BLT_SEL A_PRE_N A_SEL_P<3> A_SEL_P<2> A_SEL_P<1> ++ A_SEL_P<0> A_WR_ONE A_WR_ZERO B_BLC<3> B_BLC<2> B_BLC<1> B_BLC<0> B_BLC_SEL ++ B_BLT<3> B_BLT<2> B_BLT<1> B_BLT<0> B_BLT_SEL B_PRE_N B_SEL_P<3> B_SEL_P<2> ++ B_SEL_P<1> B_SEL_P<0> B_WR_ONE B_WR_ZERO VDD VSS / ++ RM_IHPSG13_256x8_c2_2P_BLDRV +XA_I51 net19 A_DR_O VDD VSS / RSC_IHPSG13_INVX4 +XB_I51 net037 B_DR_O VDD VSS / RSC_IHPSG13_INVX4 +XA_I78 A_RCLK_B_L A_SAE VDD VSS / RSC_IHPSG13_CBUFX2 +XB_I78 B_RCLK_B_L B_SAE VDD VSS / RSC_IHPSG13_CBUFX2 +XA_DREG A_BIST_EN_I A_BIST_DW_I A_DCLK_B_L A_DW_I A_DI_R net22 VDD VSS ++ / RSC_IHPSG13_DFNQMX2IX1 +XB_DREG B_BIST_EN_I B_BIST_DW_I B_DCLK_B_L B_DW_I B_DI_R net046 VDD ++ VSS / RSC_IHPSG13_DFNQMX2IX1 +XB_BREG B_BIST_EN_I B_BIST_BM_I B_DCLK_B_L B_BM_I B_BM_R net045 VDD ++ VSS / RSC_IHPSG13_DFNQMX2IX1 +XA_BREG A_BIST_EN_I A_BIST_BM_I A_DCLK_B_L A_BM_I A_BM_R net24 VDD VSS ++ / RSC_IHPSG13_DFNQMX2IX1 +XA_DEC3INV<15> net23<0> A_SEL_P<15> VDD VSS / RSC_IHPSG13_INVX2 +XA_DEC3INV<14> net23<1> A_SEL_P<14> VDD VSS / RSC_IHPSG13_INVX2 +XA_DEC3INV<13> net23<2> A_SEL_P<13> VDD VSS / RSC_IHPSG13_INVX2 +XA_DEC3INV<12> net23<3> A_SEL_P<12> VDD VSS / RSC_IHPSG13_INVX2 +XA_DEC3INV<11> net23<4> A_SEL_P<11> VDD VSS / RSC_IHPSG13_INVX2 +XA_DEC3INV<10> net23<5> A_SEL_P<10> VDD VSS / RSC_IHPSG13_INVX2 +XA_DEC3INV<9> net23<6> A_SEL_P<9> VDD VSS / RSC_IHPSG13_INVX2 +XA_DEC3INV<8> net23<7> A_SEL_P<8> VDD VSS / RSC_IHPSG13_INVX2 +XA_DEC3INV<7> net23<8> A_SEL_P<7> VDD VSS / RSC_IHPSG13_INVX2 +XA_DEC3INV<6> net23<9> A_SEL_P<6> VDD VSS / RSC_IHPSG13_INVX2 +XA_DEC3INV<5> net23<10> A_SEL_P<5> VDD VSS / RSC_IHPSG13_INVX2 +XA_DEC3INV<4> net23<11> A_SEL_P<4> VDD VSS / RSC_IHPSG13_INVX2 +XA_DEC3INV<3> net23<12> A_SEL_P<3> VDD VSS / RSC_IHPSG13_INVX2 +XA_DEC3INV<2> net23<13> A_SEL_P<2> VDD VSS / RSC_IHPSG13_INVX2 +XA_DEC3INV<1> net23<14> A_SEL_P<1> VDD VSS / RSC_IHPSG13_INVX2 +XA_DEC3INV<0> net23<15> A_SEL_P<0> VDD VSS / RSC_IHPSG13_INVX2 +XA_I83 A_BM_R A_BM_N VDD VSS / RSC_IHPSG13_INVX2 +XA_I49 A_DI_R A_DI_N VDD VSS / RSC_IHPSG13_INVX2 +XB_DEC3INV<15> net044<0> B_SEL_P<15> VDD VSS / RSC_IHPSG13_INVX2 +XB_DEC3INV<14> net044<1> B_SEL_P<14> VDD VSS / RSC_IHPSG13_INVX2 +XB_DEC3INV<13> net044<2> B_SEL_P<13> VDD VSS / RSC_IHPSG13_INVX2 +XB_DEC3INV<12> net044<3> B_SEL_P<12> VDD VSS / RSC_IHPSG13_INVX2 +XB_DEC3INV<11> net044<4> B_SEL_P<11> VDD VSS / RSC_IHPSG13_INVX2 +XB_DEC3INV<10> net044<5> B_SEL_P<10> VDD VSS / RSC_IHPSG13_INVX2 +XB_DEC3INV<9> net044<6> B_SEL_P<9> VDD VSS / RSC_IHPSG13_INVX2 +XB_DEC3INV<8> net044<7> B_SEL_P<8> VDD VSS / RSC_IHPSG13_INVX2 +XB_DEC3INV<7> net044<8> B_SEL_P<7> VDD VSS / RSC_IHPSG13_INVX2 +XB_DEC3INV<6> net044<9> B_SEL_P<6> VDD VSS / RSC_IHPSG13_INVX2 +XB_DEC3INV<5> net044<10> B_SEL_P<5> VDD VSS / RSC_IHPSG13_INVX2 +XB_DEC3INV<4> net044<11> B_SEL_P<4> VDD VSS / RSC_IHPSG13_INVX2 +XB_DEC3INV<3> net044<12> B_SEL_P<3> VDD VSS / RSC_IHPSG13_INVX2 +XB_DEC3INV<2> net044<13> B_SEL_P<2> VDD VSS / RSC_IHPSG13_INVX2 +XB_DEC3INV<1> net044<14> B_SEL_P<1> VDD VSS / RSC_IHPSG13_INVX2 +XB_DEC3INV<0> net044<15> B_SEL_P<0> VDD VSS / RSC_IHPSG13_INVX2 +XB_I83 B_BM_R B_BM_N VDD VSS / RSC_IHPSG13_INVX2 +XB_I49 B_DI_R B_DI_N VDD VSS / RSC_IHPSG13_INVX2 +XI_FILL8<20> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI_FILL8<19> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI_FILL8<18> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI_FILL8<17> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI_FILL8<16> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI_FILL8<15> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI_FILL8<14> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI_FILL8<13> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI_FILL8<12> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI_FILL8<11> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI_FILL8<10> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI_FILL8<9> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI_FILL8<8> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI_FILL8<7> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI_FILL8<6> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI_FILL8<5> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI_FILL8<4> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI_FILL8<3> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI_FILL8<2> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI_FILL8<1> VDD VSS / RSC_IHPSG13_FILLCAP8 +XA_I44 A_BM_N A_WCLK_B_L A_DO_WRITE_P VDD VSS / RSC_IHPSG13_NOR2X2 +XB_I44 B_BM_N B_WCLK_B_L B_DO_WRITE_P VDD VSS / RSC_IHPSG13_NOR2X2 +XA_DEC3<15> A_P0 A_ADDR_DEC<7> net23<0> VDD VSS / RSC_IHPSG13_NAND2X2 +XA_DEC3<14> A_P0 A_ADDR_DEC<6> net23<1> VDD VSS / RSC_IHPSG13_NAND2X2 +XA_DEC3<13> A_P0 A_ADDR_DEC<5> net23<2> VDD VSS / RSC_IHPSG13_NAND2X2 +XA_DEC3<12> A_P0 A_ADDR_DEC<4> net23<3> VDD VSS / RSC_IHPSG13_NAND2X2 +XA_DEC3<11> A_P0 A_ADDR_DEC<3> net23<4> VDD VSS / RSC_IHPSG13_NAND2X2 +XA_DEC3<10> A_P0 A_ADDR_DEC<2> net23<5> VDD VSS / RSC_IHPSG13_NAND2X2 +XA_DEC3<9> A_P0 A_ADDR_DEC<1> net23<6> VDD VSS / RSC_IHPSG13_NAND2X2 +XA_DEC3<8> A_P0 A_ADDR_DEC<0> net23<7> VDD VSS / RSC_IHPSG13_NAND2X2 +XA_DEC3<7> A_N0 A_ADDR_DEC<7> net23<8> VDD VSS / RSC_IHPSG13_NAND2X2 +XA_DEC3<6> A_N0 A_ADDR_DEC<6> net23<9> VDD VSS / RSC_IHPSG13_NAND2X2 +XA_DEC3<5> A_N0 A_ADDR_DEC<5> net23<10> VDD VSS / RSC_IHPSG13_NAND2X2 +XA_DEC3<4> A_N0 A_ADDR_DEC<4> net23<11> VDD VSS / RSC_IHPSG13_NAND2X2 +XA_DEC3<3> A_N0 A_ADDR_DEC<3> net23<12> VDD VSS / RSC_IHPSG13_NAND2X2 +XA_DEC3<2> A_N0 A_ADDR_DEC<2> net23<13> VDD VSS / RSC_IHPSG13_NAND2X2 +XA_DEC3<1> A_N0 A_ADDR_DEC<1> net23<14> VDD VSS / RSC_IHPSG13_NAND2X2 +XA_DEC3<0> A_N0 A_ADDR_DEC<0> net23<15> VDD VSS / RSC_IHPSG13_NAND2X2 +XB_DEC3<15> B_P0 B_ADDR_DEC<7> net044<0> VDD VSS / RSC_IHPSG13_NAND2X2 +XB_DEC3<14> B_P0 B_ADDR_DEC<6> net044<1> VDD VSS / RSC_IHPSG13_NAND2X2 +XB_DEC3<13> B_P0 B_ADDR_DEC<5> net044<2> VDD VSS / RSC_IHPSG13_NAND2X2 +XB_DEC3<12> B_P0 B_ADDR_DEC<4> net044<3> VDD VSS / RSC_IHPSG13_NAND2X2 +XB_DEC3<11> B_P0 B_ADDR_DEC<3> net044<4> VDD VSS / RSC_IHPSG13_NAND2X2 +XB_DEC3<10> B_P0 B_ADDR_DEC<2> net044<5> VDD VSS / RSC_IHPSG13_NAND2X2 +XB_DEC3<9> B_P0 B_ADDR_DEC<1> net044<6> VDD VSS / RSC_IHPSG13_NAND2X2 +XB_DEC3<8> B_P0 B_ADDR_DEC<0> net044<7> VDD VSS / RSC_IHPSG13_NAND2X2 +XB_DEC3<7> B_N0 B_ADDR_DEC<7> net044<8> VDD VSS / RSC_IHPSG13_NAND2X2 +XB_DEC3<6> B_N0 B_ADDR_DEC<6> net044<9> VDD VSS / RSC_IHPSG13_NAND2X2 +XB_DEC3<5> B_N0 B_ADDR_DEC<5> net044<10> VDD VSS / RSC_IHPSG13_NAND2X2 +XB_DEC3<4> B_N0 B_ADDR_DEC<4> net044<11> VDD VSS / RSC_IHPSG13_NAND2X2 +XB_DEC3<3> B_N0 B_ADDR_DEC<3> net044<12> VDD VSS / RSC_IHPSG13_NAND2X2 +XB_DEC3<2> B_N0 B_ADDR_DEC<2> net044<13> VDD VSS / RSC_IHPSG13_NAND2X2 +XB_DEC3<1> B_N0 B_ADDR_DEC<1> net044<14> VDD VSS / RSC_IHPSG13_NAND2X2 +XB_DEC3<0> B_N0 B_ADDR_DEC<0> net044<15> VDD VSS / RSC_IHPSG13_NAND2X2 +XB_BM_TIEH B_TIEH_O VDD VSS / RSC_IHPSG13_TIEH +XA_BM_TIEH A_TIEH_O VDD VSS / RSC_IHPSG13_TIEH +.ENDS + + +.SUBCKT RM_IHPSG13_256x8_c2_2P_ROWDEC5 ADDR_N_I<4> ADDR_N_I<3> ADDR_N_I<2> ADDR_N_I<1> ++ ADDR_N_I<0> CS_I ECLK_I WL_O<31> WL_O<30> WL_O<29> WL_O<28> WL_O<27> ++ WL_O<26> WL_O<25> WL_O<24> WL_O<23> WL_O<22> WL_O<21> WL_O<20> WL_O<19> ++ WL_O<18> WL_O<17> WL_O<16> WL_O<15> WL_O<14> WL_O<13> WL_O<12> WL_O<11> ++ WL_O<10> WL_O<9> WL_O<8> WL_O<7> WL_O<6> WL_O<5> WL_O<4> WL_O<3> WL_O<2> ++ WL_O<1> WL_O<0> VDD VSS +XDEC00 ADDR_N_I<5> ADDR_N_I<4> CS_I CS00<0> VDD VSS / ++ RM_IHPSG13_256x8_c2_2P_DEC00 +XSEL<1> ADDR_N_I<3> ADDR_N_I<2> ADDR_N_I<1> ADDR_N_I<0> CS00<1> ECLK_H<1> ++ ECLK_H<2> ECLK_B<1> ECLK_B<2> WL_O<31> WL_O<30> WL_O<29> WL_O<28> WL_O<27> ++ WL_O<26> WL_O<25> WL_O<24> WL_O<23> WL_O<22> WL_O<21> WL_O<20> WL_O<19> ++ WL_O<18> WL_O<17> WL_O<16> VDD VSS / RM_IHPSG13_256x8_c2_2P_DEC04 +XSEL<0> ADDR_N_I<3> ADDR_N_I<2> ADDR_N_I<1> ADDR_N_I<0> CS00<0> ECLK_I ++ ECLK_H<1> ECLK_B<0> ECLK_B<1> WL_O<15> WL_O<14> WL_O<13> WL_O<12> WL_O<11> ++ WL_O<10> WL_O<9> WL_O<8> WL_O<7> WL_O<6> WL_O<5> WL_O<4> WL_O<3> WL_O<2> ++ WL_O<1> WL_O<0> VDD VSS / RM_IHPSG13_256x8_c2_2P_DEC04 +XDEC01 ADDR_N_I<5> ADDR_N_I<4> CS_I CS00<1> VDD VSS / ++ RM_IHPSG13_256x8_c2_2P_DEC01 +XL2<18> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<17> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<16> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<15> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<14> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<13> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<12> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<11> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<10> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<9> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<8> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<7> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<6> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<5> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<4> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<3> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<2> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<1> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI0 ADDR_N_I<5> VDD VSS / RSC_IHPSG13_TIEL +.ENDS +.SUBCKT RM_IHPSG13_256x8_c2_2P_ROWREG5 ACLK_N_I ADDR_I<4> ADDR_I<3> ADDR_I<2> ADDR_I<1> ++ ADDR_I<0> ADDR_N_O<4> ADDR_N_O<3> ADDR_N_O<2> ADDR_N_O<1> ADDR_N_O<0> ++ BIST_ADDR_I<4> BIST_ADDR_I<3> BIST_ADDR_I<2> BIST_ADDR_I<1> BIST_ADDR_I<0> ++ BIST_EN_I VDD VSS +XINV<4> q_int<4> qn_int<4> VDD VSS / RSC_IHPSG13_CINVX2 +XINV<3> q_int<3> qn_int<3> VDD VSS / RSC_IHPSG13_CINVX2 +XINV<2> q_int<2> qn_int<2> VDD VSS / RSC_IHPSG13_CINVX2 +XINV<1> q_int<1> qn_int<1> VDD VSS / RSC_IHPSG13_CINVX2 +XINV<0> q_int<0> qn_int<0> VDD VSS / RSC_IHPSG13_CINVX2 +XDRV<4> qn_int<4> ADDR_N_O<4> VDD VSS / RSC_IHPSG13_CINVX8 +XDRV<3> qn_int<3> ADDR_N_O<3> VDD VSS / RSC_IHPSG13_CINVX8 +XDRV<2> qn_int<2> ADDR_N_O<2> VDD VSS / RSC_IHPSG13_CINVX8 +XDRV<1> qn_int<1> ADDR_N_O<1> VDD VSS / RSC_IHPSG13_CINVX8 +XDRV<0> qn_int<0> ADDR_N_O<0> VDD VSS / RSC_IHPSG13_CINVX8 +XDFF<4> BIST_EN_I BIST_ADDR_I<4> ACLK_N_I ADDR_I<4> q_int<4> net2<0> VDD ++ VSS / RSC_IHPSG13_DFNQMX2IX1 +XDFF<3> BIST_EN_I BIST_ADDR_I<3> ACLK_N_I ADDR_I<3> q_int<3> net2<1> VDD ++ VSS / RSC_IHPSG13_DFNQMX2IX1 +XDFF<2> BIST_EN_I BIST_ADDR_I<2> ACLK_N_I ADDR_I<2> q_int<2> net2<2> VDD ++ VSS / RSC_IHPSG13_DFNQMX2IX1 +XDFF<1> BIST_EN_I BIST_ADDR_I<1> ACLK_N_I ADDR_I<1> q_int<1> net2<3> VDD ++ VSS / RSC_IHPSG13_DFNQMX2IX1 +XDFF<0> BIST_EN_I BIST_ADDR_I<0> ACLK_N_I ADDR_I<0> q_int<0> net2<4> VDD ++ VSS / RSC_IHPSG13_DFNQMX2IX1 +XI11<16> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI11<15> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI11<14> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI11<13> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI11<12> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI11<11> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI11<10> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI11<9> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI11<8> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI11<7> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI11<6> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI11<5> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI11<4> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI11<3> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI11<2> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI11<1> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI12<3> VDD VSS / RSC_IHPSG13_FILLCAP4 +XI12<2> VDD VSS / RSC_IHPSG13_FILLCAP4 +XI12<1> VDD VSS / RSC_IHPSG13_FILLCAP4 +XI12<0> VDD VSS / RSC_IHPSG13_FILLCAP4 +.ENDS + + +.SUBCKT RM_IHPSG13_256x8_c2_2P_COLDEC3 ACLK_N ADDR<2> ADDR<1> ADDR<0> ADDR_COL<1> ++ ADDR_COL<0> ADDR_DEC<7> ADDR_DEC<6> ADDR_DEC<5> ADDR_DEC<4> ADDR_DEC<3> ++ ADDR_DEC<2> ADDR_DEC<1> ADDR_DEC<0> BIST_ADDR<2> BIST_ADDR<1> BIST_ADDR<0> ++ BIST_EN_I VDD VSS +XI1<7> PADR<0> PADR<1> PADR<2> addr_n<7> VDD VSS / RSC_IHPSG13_NAND3X2 +XI1<6> NADR<0> PADR<1> PADR<2> addr_n<6> VDD VSS / RSC_IHPSG13_NAND3X2 +XI1<5> PADR<0> NADR<1> PADR<2> addr_n<5> VDD VSS / RSC_IHPSG13_NAND3X2 +XI1<4> NADR<0> NADR<1> PADR<2> addr_n<4> VDD VSS / RSC_IHPSG13_NAND3X2 +XI1<3> PADR<0> PADR<1> NADR<2> addr_n<3> VDD VSS / RSC_IHPSG13_NAND3X2 +XI1<2> NADR<0> PADR<1> NADR<2> addr_n<2> VDD VSS / RSC_IHPSG13_NAND3X2 +XI1<1> PADR<0> NADR<1> NADR<2> addr_n<1> VDD VSS / RSC_IHPSG13_NAND3X2 +XI1<0> NADR<0> NADR<1> NADR<2> addr_n<0> VDD VSS / RSC_IHPSG13_NAND3X2 +XDFF<2> BIST_EN_I BIST_ADDR<2> ACLK_N ADDR<2> padr_int<2> net13<0> VDD ++ VSS / RSC_IHPSG13_DFNQMX2IX1 +XDFF<1> BIST_EN_I BIST_ADDR<1> ACLK_N ADDR<1> padr_int<1> net13<1> VDD ++ VSS / RSC_IHPSG13_DFNQMX2IX1 +XDFF<0> BIST_EN_I BIST_ADDR<0> ACLK_N ADDR<0> padr_int<0> net13<2> VDD ++ VSS / RSC_IHPSG13_DFNQMX2IX1 +XI15<1> ADDR_COL<1> VDD VSS / RSC_IHPSG13_TIEL +XI15<0> ADDR_COL<0> VDD VSS / RSC_IHPSG13_TIEL +XI13<2> NADR<2> PADR<2> VDD VSS / RSC_IHPSG13_INVX2 +XI13<1> NADR<1> PADR<1> VDD VSS / RSC_IHPSG13_INVX2 +XI13<0> NADR<0> PADR<0> VDD VSS / RSC_IHPSG13_INVX2 +XI3<2> padr_int<2> NADR<2> VDD VSS / RSC_IHPSG13_INVX2 +XI3<1> padr_int<1> NADR<1> VDD VSS / RSC_IHPSG13_INVX2 +XI3<0> padr_int<0> NADR<0> VDD VSS / RSC_IHPSG13_INVX2 +XI2<7> addr_n<7> ADDR_DEC<7> VDD VSS / RSC_IHPSG13_INVX2 +XI2<6> addr_n<6> ADDR_DEC<6> VDD VSS / RSC_IHPSG13_INVX2 +XI2<5> addr_n<5> ADDR_DEC<5> VDD VSS / RSC_IHPSG13_INVX2 +XI2<4> addr_n<4> ADDR_DEC<4> VDD VSS / RSC_IHPSG13_INVX2 +XI2<3> addr_n<3> ADDR_DEC<3> VDD VSS / RSC_IHPSG13_INVX2 +XI2<2> addr_n<2> ADDR_DEC<2> VDD VSS / RSC_IHPSG13_INVX2 +XI2<1> addr_n<1> ADDR_DEC<1> VDD VSS / RSC_IHPSG13_INVX2 +XI2<0> addr_n<0> ADDR_DEC<0> VDD VSS / RSC_IHPSG13_INVX2 +XI17<4> VDD VSS / RSC_IHPSG13_FILLCAP4 +XI17<3> VDD VSS / RSC_IHPSG13_FILLCAP4 +XI17<2> VDD VSS / RSC_IHPSG13_FILLCAP4 +XI17<1> VDD VSS / RSC_IHPSG13_FILLCAP4 +XI16<11> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI16<10> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI16<9> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI16<8> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI16<7> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI16<6> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI16<5> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI16<4> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI16<3> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI16<2> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI16<1> VDD VSS / RSC_IHPSG13_FILLCAP8 +.ENDS +.SUBCKT RSC_IHPSG13_DFPQD_MSAFFX2P CP DN DP QN QP VDD VSS +XI_AMP CP DN DP QN QP VDD VSS / RSC_IHPSG13_DFPQD_MSAFFX2 +.ENDS +.SUBCKT RM_IHPSG13_256x8_c2_2P_COLCTRL3 A_ADDR_DEC<7> A_ADDR_DEC<6> A_ADDR_DEC<5> ++ A_ADDR_DEC<4> A_ADDR_DEC<3> A_ADDR_DEC<2> A_ADDR_DEC<1> A_ADDR_DEC<0> ++ A_BIST_BM_I A_BIST_DW_I A_BIST_EN_I A_BLC<7> A_BLC<6> A_BLC<5> A_BLC<4> ++ A_BLC<3> A_BLC<2> A_BLC<1> A_BLC<0> A_BLT<7> A_BLT<6> A_BLT<5> A_BLT<4> ++ A_BLT<3> A_BLT<2> A_BLT<1> A_BLT<0> A_BM_I A_DCLK_B_L A_DCLK_B_R A_DCLK_L ++ A_DCLK_R A_DR_O A_DW_I A_RCLK_B_L A_RCLK_B_R A_RCLK_L A_RCLK_R A_TIEH_O ++ A_WCLK_B_L A_WCLK_B_R A_WCLK_L A_WCLK_R B_ADDR_DEC<7> B_ADDR_DEC<6> ++ B_ADDR_DEC<5> B_ADDR_DEC<4> B_ADDR_DEC<3> B_ADDR_DEC<2> B_ADDR_DEC<1> ++ B_ADDR_DEC<0> B_BIST_BM_I B_BIST_DW_I B_BIST_EN_I B_BLC<7> B_BLC<6> B_BLC<5> ++ B_BLC<4> B_BLC<3> B_BLC<2> B_BLC<1> B_BLC<0> B_BLT<7> B_BLT<6> B_BLT<5> ++ B_BLT<4> B_BLT<3> B_BLT<2> B_BLT<1> B_BLT<0> B_BM_I B_DCLK_B_L B_DCLK_B_R ++ B_DCLK_L B_DCLK_R B_DR_O B_DW_I B_RCLK_B_L B_RCLK_B_R B_RCLK_L B_RCLK_R ++ B_TIEH_O B_WCLK_B_L B_WCLK_B_R B_WCLK_L B_WCLK_R VDD VSS +XB_DREG B_BIST_EN_I B_BIST_DW_I B_DCLK_B_L B_DW_I B_DI_R net044 VDD ++ VSS / RSC_IHPSG13_DFNQMX2IX1 +XB_BREG B_BIST_EN_I B_BIST_BM_I B_DCLK_B_L B_BM_I B_BM_R net043 VDD ++ VSS / RSC_IHPSG13_DFNQMX2IX1 +XA_DREG A_BIST_EN_I A_BIST_DW_I A_DCLK_B_L A_DW_I A_DI_R net22 VDD VSS ++ / RSC_IHPSG13_DFNQMX2IX1 +XA_BREG A_BIST_EN_I A_BIST_BM_I A_DCLK_B_L A_BM_I A_BM_R net23 VDD VSS ++ / RSC_IHPSG13_DFNQMX2IX1 +XI_FILL8<11> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI_FILL8<10> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI_FILL8<9> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI_FILL8<8> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI_FILL8<7> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI_FILL8<6> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI_FILL8<5> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI_FILL8<4> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI_FILL8<3> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI_FILL8<2> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI_FILL8<1> VDD VSS / RSC_IHPSG13_FILLCAP8 +XB_I51 net037 B_DR_O VDD VSS / RSC_IHPSG13_INVX4 +XA_I51 net19 A_DR_O VDD VSS / RSC_IHPSG13_INVX4 +XB_I44 B_BM_N B_WCLK_B_L B_DO_WRITE_P VDD VSS / RSC_IHPSG13_NOR2X2 +XA_I44 A_BM_N A_WCLK_B_L A_DO_WRITE_P VDD VSS / RSC_IHPSG13_NOR2X2 +XB_BM_TIEH B_TIEH_O VDD VSS / RSC_IHPSG13_TIEH +XA_BM_TIEH A_TIEH_O VDD VSS / RSC_IHPSG13_TIEH +XB_ISENSE B_SAE B_BLC_SEL B_BLT_SEL net037 net038 VDD VSS / ++ RSC_IHPSG13_DFPQD_MSAFFX2P +XA_ISENSE A_SAE A_BLC_SEL A_BLT_SEL net19 net20 VDD VSS / ++ RSC_IHPSG13_DFPQD_MSAFFX2P +XB_I49 B_DI_R B_DI_N VDD VSS / RSC_IHPSG13_INVX2 +XB_I83 B_BM_R B_BM_N VDD VSS / RSC_IHPSG13_INVX2 +XA_I49 A_DI_R A_DI_N VDD VSS / RSC_IHPSG13_INVX2 +XA_I83 A_BM_R A_BM_N VDD VSS / RSC_IHPSG13_INVX2 +XB_I69 B_DCLK_L B_DCLK_B_L VDD VSS / RSC_IHPSG13_CINVX2 +XB_I50 B_WCLK_L B_WCLK_B_L VDD VSS / RSC_IHPSG13_CINVX2 +XB_EBUF B_RCLK_L B_RCLK_B_L VDD VSS / RSC_IHPSG13_CINVX2 +XA_I69 A_DCLK_L A_DCLK_B_L VDD VSS / RSC_IHPSG13_CINVX2 +XA_I50 A_WCLK_L A_WCLK_B_L VDD VSS / RSC_IHPSG13_CINVX2 +XA_EBUF A_RCLK_L A_RCLK_B_L VDD VSS / RSC_IHPSG13_CINVX2 +XAB_BLMUX<1> A_BLC<7> A_BLC<6> A_BLC<5> A_BLC<4> A_BLC_SEL A_BLT<7> A_BLT<6> ++ A_BLT<5> A_BLT<4> A_BLT_SEL A_PRE_N A_ADDR_DEC<7> A_ADDR_DEC<6> ++ A_ADDR_DEC<5> A_ADDR_DEC<4> A_WR_ONE A_WR_ZERO B_BLC<7> B_BLC<6> B_BLC<5> ++ B_BLC<4> B_BLC_SEL B_BLT<7> B_BLT<6> B_BLT<5> B_BLT<4> B_BLT_SEL B_PRE_N ++ B_ADDR_DEC<7> B_ADDR_DEC<6> B_ADDR_DEC<5> B_ADDR_DEC<4> B_WR_ONE B_WR_ZERO ++ VDD VSS / RM_IHPSG13_256x8_c2_2P_BLDRV +XAB_BLMUX<0> A_BLC<3> A_BLC<2> A_BLC<1> A_BLC<0> A_BLC_SEL A_BLT<3> A_BLT<2> ++ A_BLT<1> A_BLT<0> A_BLT_SEL A_PRE_N A_ADDR_DEC<3> A_ADDR_DEC<2> ++ A_ADDR_DEC<1> A_ADDR_DEC<0> A_WR_ONE A_WR_ZERO B_BLC<3> B_BLC<2> B_BLC<1> ++ B_BLC<0> B_BLC_SEL B_BLT<3> B_BLT<2> B_BLT<1> B_BLT<0> B_BLT_SEL B_PRE_N ++ B_ADDR_DEC<3> B_ADDR_DEC<2> B_ADDR_DEC<1> B_ADDR_DEC<0> B_WR_ONE B_WR_ZERO ++ VDD VSS / RM_IHPSG13_256x8_c2_2P_BLDRV +XB_I78 B_RCLK_B_L B_SAE VDD VSS / RSC_IHPSG13_CBUFX2 +XA_I78 A_RCLK_B_L A_SAE VDD VSS / RSC_IHPSG13_CBUFX2 +XB_I88 B_DCLK_L B_DCLK_R / RSC_IHPSG13_MET3RES +XB_I87 B_WCLK_L B_WCLK_R / RSC_IHPSG13_MET3RES +XB_R2 B_RCLK_L B_RCLK_R / RSC_IHPSG13_MET3RES +XB_I91 B_RCLK_B_L B_RCLK_B_R / RSC_IHPSG13_MET3RES +XB_I90 B_WCLK_B_L B_WCLK_B_R / RSC_IHPSG13_MET3RES +XB_I89 B_DCLK_B_L B_DCLK_B_R / RSC_IHPSG13_MET3RES +XA_I88 A_DCLK_L A_DCLK_R / RSC_IHPSG13_MET3RES +XA_I87 A_WCLK_L A_WCLK_R / RSC_IHPSG13_MET3RES +XA_R2 A_RCLK_L A_RCLK_R / RSC_IHPSG13_MET3RES +XA_I91 A_RCLK_B_L A_RCLK_B_R / RSC_IHPSG13_MET3RES +XA_I90 A_WCLK_B_L A_WCLK_B_R / RSC_IHPSG13_MET3RES +XA_I89 A_DCLK_B_L A_DCLK_B_R / RSC_IHPSG13_MET3RES +XB_I80 B_WCLK_B_L B_RCLK_B_L net041 VDD VSS / RSC_IHPSG13_AND2X2 +XB_I76 B_DO_WRITE_P B_DI_N B_WR_ZERO VDD VSS / RSC_IHPSG13_AND2X2 +XB_I75 B_DO_WRITE_P B_DI_R B_WR_ONE VDD VSS / RSC_IHPSG13_AND2X2 +XA_I80 A_WCLK_B_L A_RCLK_B_L net21 VDD VSS / RSC_IHPSG13_AND2X2 +XA_I76 A_DI_N A_DO_WRITE_P A_WR_ZERO VDD VSS / RSC_IHPSG13_AND2X2 +XA_I75 A_DI_R A_DO_WRITE_P A_WR_ONE VDD VSS / RSC_IHPSG13_AND2X2 +XB_I81 net041 B_PRE_N VDD VSS / RSC_IHPSG13_CINVX4_WN +XA_I81 net21 A_PRE_N VDD VSS / RSC_IHPSG13_CINVX4_WN +XI_FILL4<10> VDD VSS / RSC_IHPSG13_FILLCAP4 +XI_FILL4<9> VDD VSS / RSC_IHPSG13_FILLCAP4 +XI_FILL4<8> VDD VSS / RSC_IHPSG13_FILLCAP4 +XI_FILL4<7> VDD VSS / RSC_IHPSG13_FILLCAP4 +XI_FILL4<6> VDD VSS / RSC_IHPSG13_FILLCAP4 +XI_FILL4<5> VDD VSS / RSC_IHPSG13_FILLCAP4 +XI_FILL4<4> VDD VSS / RSC_IHPSG13_FILLCAP4 +XI_FILL4<3> VDD VSS / RSC_IHPSG13_FILLCAP4 +XI_FILL4<2> VDD VSS / RSC_IHPSG13_FILLCAP4 +XI_FILL4<1> VDD VSS / RSC_IHPSG13_FILLCAP4 +.ENDS + +.SUBCKT RM_IHPSG13_256x8_c2_2P_ROWDEC6 ADDR_N_I<5> ADDR_N_I<4> ADDR_N_I<3> ADDR_N_I<2> ++ ADDR_N_I<1> ADDR_N_I<0> CS_I ECLK_I WL_O<63> WL_O<62> WL_O<61> WL_O<60> ++ WL_O<59> WL_O<58> WL_O<57> WL_O<56> WL_O<55> WL_O<54> WL_O<53> WL_O<52> ++ WL_O<51> WL_O<50> WL_O<49> WL_O<48> WL_O<47> WL_O<46> WL_O<45> WL_O<44> ++ WL_O<43> WL_O<42> WL_O<41> WL_O<40> WL_O<39> WL_O<38> WL_O<37> WL_O<36> ++ WL_O<35> WL_O<34> WL_O<33> WL_O<32> WL_O<31> WL_O<30> WL_O<29> WL_O<28> ++ WL_O<27> WL_O<26> WL_O<25> WL_O<24> WL_O<23> WL_O<22> WL_O<21> WL_O<20> ++ WL_O<19> WL_O<18> WL_O<17> WL_O<16> WL_O<15> WL_O<14> WL_O<13> WL_O<12> ++ WL_O<11> WL_O<10> WL_O<9> WL_O<8> WL_O<7> WL_O<6> WL_O<5> WL_O<4> WL_O<3> ++ WL_O<2> WL_O<1> WL_O<0> VDD VSS +XDEC10 ADDR_N_I<5> ADDR_N_I<4> CS_I CS00<2> VDD VSS / ++ RM_IHPSG13_256x8_c2_2P_DEC02 +XDEC00 ADDR_N_I<5> ADDR_N_I<4> CS_I CS00<0> VDD VSS / ++ RM_IHPSG13_256x8_c2_2P_DEC00 +XSEL<3> ADDR_N_I<3> ADDR_N_I<2> ADDR_N_I<1> ADDR_N_I<0> CS00<3> ECLK_H<3> ++ ECLK_H<4> ECLK_B<3> ECLK_B<4> WL_O<63> WL_O<62> WL_O<61> WL_O<60> WL_O<59> ++ WL_O<58> WL_O<57> WL_O<56> WL_O<55> WL_O<54> WL_O<53> WL_O<52> WL_O<51> ++ WL_O<50> WL_O<49> WL_O<48> VDD VSS / RM_IHPSG13_256x8_c2_2P_DEC04 +XSEL<2> ADDR_N_I<3> ADDR_N_I<2> ADDR_N_I<1> ADDR_N_I<0> CS00<2> ECLK_H<2> ++ ECLK_H<3> ECLK_B<2> ECLK_B<3> WL_O<47> WL_O<46> WL_O<45> WL_O<44> WL_O<43> ++ WL_O<42> WL_O<41> WL_O<40> WL_O<39> WL_O<38> WL_O<37> WL_O<36> WL_O<35> ++ WL_O<34> WL_O<33> WL_O<32> VDD VSS / RM_IHPSG13_256x8_c2_2P_DEC04 +XSEL<1> ADDR_N_I<3> ADDR_N_I<2> ADDR_N_I<1> ADDR_N_I<0> CS00<1> ECLK_H<1> ++ ECLK_H<2> ECLK_B<1> ECLK_B<2> WL_O<31> WL_O<30> WL_O<29> WL_O<28> WL_O<27> ++ WL_O<26> WL_O<25> WL_O<24> WL_O<23> WL_O<22> WL_O<21> WL_O<20> WL_O<19> ++ WL_O<18> WL_O<17> WL_O<16> VDD VSS / RM_IHPSG13_256x8_c2_2P_DEC04 +XSEL<0> ADDR_N_I<3> ADDR_N_I<2> ADDR_N_I<1> ADDR_N_I<0> CS00<0> ECLK_I ++ ECLK_H<1> ECLK_B<0> ECLK_B<1> WL_O<15> WL_O<14> WL_O<13> WL_O<12> WL_O<11> ++ WL_O<10> WL_O<9> WL_O<8> WL_O<7> WL_O<6> WL_O<5> WL_O<4> WL_O<3> WL_O<2> ++ WL_O<1> WL_O<0> VDD VSS / RM_IHPSG13_256x8_c2_2P_DEC04 +XDEC11 ADDR_N_I<5> ADDR_N_I<4> CS_I CS00<3> VDD VSS / ++ RM_IHPSG13_256x8_c2_2P_DEC03 +XL2<36> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<35> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<34> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<33> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<32> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<31> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<30> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<29> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<28> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<27> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<26> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<25> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<24> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<23> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<22> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<21> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<20> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<19> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<18> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<17> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<16> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<15> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<14> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<13> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<12> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<11> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<10> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<9> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<8> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<7> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<6> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<5> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<4> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<3> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<2> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<1> VDD VSS / RSC_IHPSG13_FILLCAP8 +XDEC01 ADDR_N_I<5> ADDR_N_I<4> CS_I CS00<1> VDD VSS / ++ RM_IHPSG13_256x8_c2_2P_DEC01 +.ENDS +.SUBCKT RM_IHPSG13_256x8_c2_2P_ROWREG6 ACLK_N_I ADDR_I<5> ADDR_I<4> ADDR_I<3> ADDR_I<2> ++ ADDR_I<1> ADDR_I<0> ADDR_N_O<5> ADDR_N_O<4> ADDR_N_O<3> ADDR_N_O<2> ++ ADDR_N_O<1> ADDR_N_O<0> BIST_ADDR_I<5> BIST_ADDR_I<4> BIST_ADDR_I<3> ++ BIST_ADDR_I<2> BIST_ADDR_I<1> BIST_ADDR_I<0> BIST_EN_I VDD VSS +XINV<5> q_int<5> qn_int<5> VDD VSS / RSC_IHPSG13_CINVX2 +XINV<4> q_int<4> qn_int<4> VDD VSS / RSC_IHPSG13_CINVX2 +XINV<3> q_int<3> qn_int<3> VDD VSS / RSC_IHPSG13_CINVX2 +XINV<2> q_int<2> qn_int<2> VDD VSS / RSC_IHPSG13_CINVX2 +XINV<1> q_int<1> qn_int<1> VDD VSS / RSC_IHPSG13_CINVX2 +XINV<0> q_int<0> qn_int<0> VDD VSS / RSC_IHPSG13_CINVX2 +XDRV<5> qn_int<5> ADDR_N_O<5> VDD VSS / RSC_IHPSG13_CINVX8 +XDRV<4> qn_int<4> ADDR_N_O<4> VDD VSS / RSC_IHPSG13_CINVX8 +XDRV<3> qn_int<3> ADDR_N_O<3> VDD VSS / RSC_IHPSG13_CINVX8 +XDRV<2> qn_int<2> ADDR_N_O<2> VDD VSS / RSC_IHPSG13_CINVX8 +XDRV<1> qn_int<1> ADDR_N_O<1> VDD VSS / RSC_IHPSG13_CINVX8 +XDRV<0> qn_int<0> ADDR_N_O<0> VDD VSS / RSC_IHPSG13_CINVX8 +XDFF<5> BIST_EN_I BIST_ADDR_I<5> ACLK_N_I ADDR_I<5> q_int<5> net2<0> VDD ++ VSS / RSC_IHPSG13_DFNQMX2IX1 +XDFF<4> BIST_EN_I BIST_ADDR_I<4> ACLK_N_I ADDR_I<4> q_int<4> net2<1> VDD ++ VSS / RSC_IHPSG13_DFNQMX2IX1 +XDFF<3> BIST_EN_I BIST_ADDR_I<3> ACLK_N_I ADDR_I<3> q_int<3> net2<2> VDD ++ VSS / RSC_IHPSG13_DFNQMX2IX1 +XDFF<2> BIST_EN_I BIST_ADDR_I<2> ACLK_N_I ADDR_I<2> q_int<2> net2<3> VDD ++ VSS / RSC_IHPSG13_DFNQMX2IX1 +XDFF<1> BIST_EN_I BIST_ADDR_I<1> ACLK_N_I ADDR_I<1> q_int<1> net2<4> VDD ++ VSS / RSC_IHPSG13_DFNQMX2IX1 +XDFF<0> BIST_EN_I BIST_ADDR_I<0> ACLK_N_I ADDR_I<0> q_int<0> net2<5> VDD ++ VSS / RSC_IHPSG13_DFNQMX2IX1 +XI11<12> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI11<11> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI11<10> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI11<9> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI11<8> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI11<7> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI11<6> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI11<5> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI11<4> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI11<3> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI11<2> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI11<1> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI12<2> VDD VSS / RSC_IHPSG13_FILLCAP4 +XI12<1> VDD VSS / RSC_IHPSG13_FILLCAP4 +XI12<0> VDD VSS / RSC_IHPSG13_FILLCAP4 +.ENDS + +.SUBCKT RM_IHPSG13_256x8_c2_2P_COLDRV13X16 ADDR_COL_I<1> ADDR_COL_I<0> ADDR_COL_O<1> ++ ADDR_COL_O<0> ADDR_DEC_I<7> ADDR_DEC_I<6> ADDR_DEC_I<5> ADDR_DEC_I<4> ++ ADDR_DEC_I<3> ADDR_DEC_I<2> ADDR_DEC_I<1> ADDR_DEC_I<0> ADDR_DEC_O<7> ++ ADDR_DEC_O<6> ADDR_DEC_O<5> ADDR_DEC_O<4> ADDR_DEC_O<3> ADDR_DEC_O<2> ++ ADDR_DEC_O<1> ADDR_DEC_O<0> DCLK_I DCLK_O RCLK_I RCLK_O WCLK_I WCLK_O ++ VDD VSS +XI0<7> VDD VSS / RSC_IHPSG13_FILLCAP4 +XI0<6> VDD VSS / RSC_IHPSG13_FILLCAP4 +XI0<5> VDD VSS / RSC_IHPSG13_FILLCAP4 +XI0<4> VDD VSS / RSC_IHPSG13_FILLCAP4 +XI0<3> VDD VSS / RSC_IHPSG13_FILLCAP4 +XI0<2> VDD VSS / RSC_IHPSG13_FILLCAP4 +XI0<1> VDD VSS / RSC_IHPSG13_FILLCAP4 +XWCLK_DRV WCLK_I WCLK_O VDD VSS / RSC_IHPSG13_CBUFX16 +XRCLK_DRV RCLK_I RCLK_O VDD VSS / RSC_IHPSG13_CBUFX16 +XDCLK_DRV DCLK_I DCLK_O VDD VSS / RSC_IHPSG13_CBUFX16 +XADDR_COL_DRV<1> ADDR_COL_I<1> ADDR_COL_O<1> VDD VSS / ++ RSC_IHPSG13_CBUFX16 +XADDR_COL_DRV<0> ADDR_COL_I<0> ADDR_COL_O<0> VDD VSS / ++ RSC_IHPSG13_CBUFX16 +XADDR_DEC_DRV<7> ADDR_DEC_I<7> ADDR_DEC_O<7> VDD VSS / ++ RSC_IHPSG13_CBUFX16 +XADDR_DEC_DRV<6> ADDR_DEC_I<6> ADDR_DEC_O<6> VDD VSS / ++ RSC_IHPSG13_CBUFX16 +XADDR_DEC_DRV<5> ADDR_DEC_I<5> ADDR_DEC_O<5> VDD VSS / ++ RSC_IHPSG13_CBUFX16 +XADDR_DEC_DRV<4> ADDR_DEC_I<4> ADDR_DEC_O<4> VDD VSS / ++ RSC_IHPSG13_CBUFX16 +XADDR_DEC_DRV<3> ADDR_DEC_I<3> ADDR_DEC_O<3> VDD VSS / ++ RSC_IHPSG13_CBUFX16 +XADDR_DEC_DRV<2> ADDR_DEC_I<2> ADDR_DEC_O<2> VDD VSS / ++ RSC_IHPSG13_CBUFX16 +XADDR_DEC_DRV<1> ADDR_DEC_I<1> ADDR_DEC_O<1> VDD VSS / ++ RSC_IHPSG13_CBUFX16 +XADDR_DEC_DRV<0> ADDR_DEC_I<0> ADDR_DEC_O<0> VDD VSS / ++ RSC_IHPSG13_CBUFX16 +XI1<5> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI1<4> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI1<3> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI1<2> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI1<1> VDD VSS / RSC_IHPSG13_FILLCAP8 +.ENDS +.SUBCKT RM_IHPSG13_256x8_c2_2P_WLDRV16X16 A<15> A<14> A<13> A<12> A<11> A<10> A<9> A<8> ++ A<7> A<6> A<5> A<4> A<3> A<2> A<1> A<0> Z<15> Z<14> Z<13> Z<12> Z<11> Z<10> ++ Z<9> Z<8> Z<7> Z<6> Z<5> Z<4> Z<3> Z<2> Z<1> Z<0> VDD VSS +XBUF<15> A<15> Z<15> VDD VSS / RSC_IHPSG13_WLDRVX16 +XBUF<14> A<14> Z<14> VDD VSS / RSC_IHPSG13_WLDRVX16 +XBUF<13> A<13> Z<13> VDD VSS / RSC_IHPSG13_WLDRVX16 +XBUF<12> A<12> Z<12> VDD VSS / RSC_IHPSG13_WLDRVX16 +XBUF<11> A<11> Z<11> VDD VSS / RSC_IHPSG13_WLDRVX16 +XBUF<10> A<10> Z<10> VDD VSS / RSC_IHPSG13_WLDRVX16 +XBUF<9> A<9> Z<9> VDD VSS / RSC_IHPSG13_WLDRVX16 +XBUF<8> A<8> Z<8> VDD VSS / RSC_IHPSG13_WLDRVX16 +XBUF<7> A<7> Z<7> VDD VSS / RSC_IHPSG13_WLDRVX16 +XBUF<6> A<6> Z<6> VDD VSS / RSC_IHPSG13_WLDRVX16 +XBUF<5> A<5> Z<5> VDD VSS / RSC_IHPSG13_WLDRVX16 +XBUF<4> A<4> Z<4> VDD VSS / RSC_IHPSG13_WLDRVX16 +XBUF<3> A<3> Z<3> VDD VSS / RSC_IHPSG13_WLDRVX16 +XBUF<2> A<2> Z<2> VDD VSS / RSC_IHPSG13_WLDRVX16 +XBUF<1> A<1> Z<1> VDD VSS / RSC_IHPSG13_WLDRVX16 +XBUF<0> A<0> Z<0> VDD VSS / RSC_IHPSG13_WLDRVX16 +.ENDS + + +.SUBCKT RM_IHPSG13_256x8_c2_1P_DEC01 ADDR<1> ADDR<0> CS CS_OUT VDD VSS +XDECINV net1 CS_OUT VDD VSS / RSC_IHPSG13_INVX4 +XDEC NADDR<1> ADDR<0> CS net1 VDD VSS / RSC_IHPSG13_NAND3X2 +XI2 VDD VSS / RSC_IHPSG13_FILLCAP4 +XADDRINV ADDR<1> NADDR<1> VDD VSS / RSC_IHPSG13_INVX2 +.ENDS +.SUBCKT RM_IHPSG13_256x8_c2_1P_DEC00 ADDR<1> ADDR<0> CS CS_OUT VDD VSS +XDECINV net1 CS_OUT VDD VSS / RSC_IHPSG13_INVX4 +XDEC NADDR<1> NADDR<0> CS net1 VDD VSS / RSC_IHPSG13_NAND3X2 +XADDRINV<1> ADDR<1> NADDR<1> VDD VSS / RSC_IHPSG13_INVX2 +XADDRINV<0> ADDR<0> NADDR<0> VDD VSS / RSC_IHPSG13_INVX2 +XI1 VDD VSS / RSC_IHPSG13_FILLCAP4 +.ENDS +.SUBCKT RM_IHPSG13_256x8_c2_1P_ROWDEC5 ADDR_N_I<4> ADDR_N_I<3> ADDR_N_I<2> ADDR_N_I<1> ++ ADDR_N_I<0> CS_I ECLK_I WL_O<31> WL_O<30> WL_O<29> WL_O<28> WL_O<27> ++ WL_O<26> WL_O<25> WL_O<24> WL_O<23> WL_O<22> WL_O<21> WL_O<20> WL_O<19> ++ WL_O<18> WL_O<17> WL_O<16> WL_O<15> WL_O<14> WL_O<13> WL_O<12> WL_O<11> ++ WL_O<10> WL_O<9> WL_O<8> WL_O<7> WL_O<6> WL_O<5> WL_O<4> WL_O<3> WL_O<2> ++ WL_O<1> WL_O<0> VDD VSS +XL2<12> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<11> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<10> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<9> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<8> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<7> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<6> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<5> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<4> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<3> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<2> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<1> VDD VSS / RSC_IHPSG13_FILLCAP8 +XDEC01 ADDR_N_I<5> ADDR_N_I<4> CS_I CS00<1> VDD VSS / ++ RM_IHPSG13_256x8_c2_1P_DEC01 +XDEC00 ADDR_N_I<5> ADDR_N_I<4> CS_I CS00<0> VDD VSS / ++ RM_IHPSG13_256x8_c2_1P_DEC00 +XSEL<1> ADDR_N_I<3> ADDR_N_I<2> ADDR_N_I<1> ADDR_N_I<0> CS00<1> ECLK_H<1> ++ ECLK_H<2> ECLK_B<1> ECLK_B<2> WL_O<31> WL_O<30> WL_O<29> WL_O<28> WL_O<27> ++ WL_O<26> WL_O<25> WL_O<24> WL_O<23> WL_O<22> WL_O<21> WL_O<20> WL_O<19> ++ WL_O<18> WL_O<17> WL_O<16> VDD VSS / RM_IHPSG13_256x8_c2_1P_DEC04 +XSEL<0> ADDR_N_I<3> ADDR_N_I<2> ADDR_N_I<1> ADDR_N_I<0> CS00<0> ECLK_I ++ ECLK_H<1> ECLK_B<0> ECLK_B<1> WL_O<15> WL_O<14> WL_O<13> WL_O<12> WL_O<11> ++ WL_O<10> WL_O<9> WL_O<8> WL_O<7> WL_O<6> WL_O<5> WL_O<4> WL_O<3> WL_O<2> ++ WL_O<1> WL_O<0> VDD VSS / RM_IHPSG13_256x8_c2_1P_DEC04 +XI0 ADDR_N_I<5> VDD VSS / RSC_IHPSG13_TIEL +.ENDS +.SUBCKT RM_IHPSG13_256x8_c2_1P_ROWREG5 ACLK_N_I ADDR_I<4> ADDR_I<3> ADDR_I<2> ADDR_I<1> ++ ADDR_I<0> ADDR_N_O<4> ADDR_N_O<3> ADDR_N_O<2> ADDR_N_O<1> ADDR_N_O<0> ++ BIST_ADDR_I<4> BIST_ADDR_I<3> BIST_ADDR_I<2> BIST_ADDR_I<1> BIST_ADDR_I<0> ++ BIST_EN_I VDD VSS +XINV<4> q_int<4> qn_int<4> VDD VSS / RSC_IHPSG13_CINVX2 +XINV<3> q_int<3> qn_int<3> VDD VSS / RSC_IHPSG13_CINVX2 +XINV<2> q_int<2> qn_int<2> VDD VSS / RSC_IHPSG13_CINVX2 +XINV<1> q_int<1> qn_int<1> VDD VSS / RSC_IHPSG13_CINVX2 +XINV<0> q_int<0> qn_int<0> VDD VSS / RSC_IHPSG13_CINVX2 +XDRV<4> qn_int<4> ADDR_N_O<4> VDD VSS / RSC_IHPSG13_CINVX8 +XDRV<3> qn_int<3> ADDR_N_O<3> VDD VSS / RSC_IHPSG13_CINVX8 +XDRV<2> qn_int<2> ADDR_N_O<2> VDD VSS / RSC_IHPSG13_CINVX8 +XDRV<1> qn_int<1> ADDR_N_O<1> VDD VSS / RSC_IHPSG13_CINVX8 +XDRV<0> qn_int<0> ADDR_N_O<0> VDD VSS / RSC_IHPSG13_CINVX8 +XDFF<4> BIST_EN_I BIST_ADDR_I<4> ACLK_N_I ADDR_I<4> q_int<4> net2<0> VDD ++ VSS / RSC_IHPSG13_DFNQMX2IX1 +XDFF<3> BIST_EN_I BIST_ADDR_I<3> ACLK_N_I ADDR_I<3> q_int<3> net2<1> VDD ++ VSS / RSC_IHPSG13_DFNQMX2IX1 +XDFF<2> BIST_EN_I BIST_ADDR_I<2> ACLK_N_I ADDR_I<2> q_int<2> net2<2> VDD ++ VSS / RSC_IHPSG13_DFNQMX2IX1 +XDFF<1> BIST_EN_I BIST_ADDR_I<1> ACLK_N_I ADDR_I<1> q_int<1> net2<3> VDD ++ VSS / RSC_IHPSG13_DFNQMX2IX1 +XDFF<0> BIST_EN_I BIST_ADDR_I<0> ACLK_N_I ADDR_I<0> q_int<0> net2<4> VDD ++ VSS / RSC_IHPSG13_DFNQMX2IX1 +XI11<16> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI11<15> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI11<14> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI11<13> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI11<12> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI11<11> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI11<10> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI11<9> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI11<8> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI11<7> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI11<6> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI11<5> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI11<4> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI11<3> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI11<2> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI11<1> VDD VSS / RSC_IHPSG13_FILLCAP8 +.ENDS + + +.SUBCKT RM_IHPSG13_256x8_c2_1P_COLDEC5 ACLK_N ADDR<4> ADDR<3> ADDR<2> ADDR<1> ADDR<0> ++ ADDR_COL<1> ADDR_COL<0> ADDR_DEC<7> ADDR_DEC<6> ADDR_DEC<5> ADDR_DEC<4> ++ ADDR_DEC<3> ADDR_DEC<2> ADDR_DEC<1> ADDR_DEC<0> BIST_ADDR<4> BIST_ADDR<3> ++ BIST_ADDR<2> BIST_ADDR<1> BIST_ADDR<0> BIST_EN_I VDD VSS +XI17<2> VDD VSS / RSC_IHPSG13_FILLCAP4 +XI17<1> VDD VSS / RSC_IHPSG13_FILLCAP4 +XI13<1> addr_int<1> ADDR_COL<1> VDD VSS / RSC_IHPSG13_CBUFX2 +XI13<0> addr_int<0> ADDR_COL<0> VDD VSS / RSC_IHPSG13_CBUFX2 +XDFF<4> BIST_EN_I BIST_ADDR<4> ACLK_N ADDR<4> addr_int<1> net7<0> VDD ++ VSS / RSC_IHPSG13_DFNQMX2IX1 +XDFF<3> BIST_EN_I BIST_ADDR<3> ACLK_N ADDR<3> addr_int<0> net7<1> VDD ++ VSS / RSC_IHPSG13_DFNQMX2IX1 +XDFF<2> BIST_EN_I BIST_ADDR<2> ACLK_N ADDR<2> padr_int<2> net7<2> VDD ++ VSS / RSC_IHPSG13_DFNQMX2IX1 +XDFF<1> BIST_EN_I BIST_ADDR<1> ACLK_N ADDR<1> padr_int<1> net7<3> VDD ++ VSS / RSC_IHPSG13_DFNQMX2IX1 +XDFF<0> BIST_EN_I BIST_ADDR<0> ACLK_N ADDR<0> padr_int<0> net7<4> VDD ++ VSS / RSC_IHPSG13_DFNQMX2IX1 +XI1<7> PADR<0> PADR<1> PADR<2> addr_n<7> VDD VSS / RSC_IHPSG13_NAND3X2 +XI1<6> NADR<0> PADR<1> PADR<2> addr_n<6> VDD VSS / RSC_IHPSG13_NAND3X2 +XI1<5> PADR<0> NADR<1> PADR<2> addr_n<5> VDD VSS / RSC_IHPSG13_NAND3X2 +XI1<4> NADR<0> NADR<1> PADR<2> addr_n<4> VDD VSS / RSC_IHPSG13_NAND3X2 +XI1<3> PADR<0> PADR<1> NADR<2> addr_n<3> VDD VSS / RSC_IHPSG13_NAND3X2 +XI1<2> NADR<0> PADR<1> NADR<2> addr_n<2> VDD VSS / RSC_IHPSG13_NAND3X2 +XI1<1> PADR<0> NADR<1> NADR<2> addr_n<1> VDD VSS / RSC_IHPSG13_NAND3X2 +XI1<0> NADR<0> NADR<1> NADR<2> addr_n<0> VDD VSS / RSC_IHPSG13_NAND3X2 +XI15<2> NADR<2> PADR<2> VDD VSS / RSC_IHPSG13_INVX2 +XI15<1> NADR<1> PADR<1> VDD VSS / RSC_IHPSG13_INVX2 +XI15<0> NADR<0> PADR<0> VDD VSS / RSC_IHPSG13_INVX2 +XI3<2> padr_int<2> NADR<2> VDD VSS / RSC_IHPSG13_INVX2 +XI3<1> padr_int<1> NADR<1> VDD VSS / RSC_IHPSG13_INVX2 +XI3<0> padr_int<0> NADR<0> VDD VSS / RSC_IHPSG13_INVX2 +XI2<7> addr_n<7> ADDR_DEC<7> VDD VSS / RSC_IHPSG13_INVX2 +XI2<6> addr_n<6> ADDR_DEC<6> VDD VSS / RSC_IHPSG13_INVX2 +XI2<5> addr_n<5> ADDR_DEC<5> VDD VSS / RSC_IHPSG13_INVX2 +XI2<4> addr_n<4> ADDR_DEC<4> VDD VSS / RSC_IHPSG13_INVX2 +XI2<3> addr_n<3> ADDR_DEC<3> VDD VSS / RSC_IHPSG13_INVX2 +XI2<2> addr_n<2> ADDR_DEC<2> VDD VSS / RSC_IHPSG13_INVX2 +XI2<1> addr_n<1> ADDR_DEC<1> VDD VSS / RSC_IHPSG13_INVX2 +XI2<0> addr_n<0> ADDR_DEC<0> VDD VSS / RSC_IHPSG13_INVX2 +.ENDS +.SUBCKT RM_IHPSG13_256x8_c2_1P_COLCTRL5 A_ADDR_COL<1> A_ADDR_COL<0> A_ADDR_DEC<7> ++ A_ADDR_DEC<6> A_ADDR_DEC<5> A_ADDR_DEC<4> A_ADDR_DEC<3> A_ADDR_DEC<2> ++ A_ADDR_DEC<1> A_ADDR_DEC<0> A_BIST_BM_I A_BIST_DW_I A_BIST_EN_I A_BLC<31> ++ A_BLC<30> A_BLC<29> A_BLC<28> A_BLC<27> A_BLC<26> A_BLC<25> A_BLC<24> ++ A_BLC<23> A_BLC<22> A_BLC<21> A_BLC<20> A_BLC<19> A_BLC<18> A_BLC<17> ++ A_BLC<16> A_BLC<15> A_BLC<14> A_BLC<13> A_BLC<12> A_BLC<11> A_BLC<10> ++ A_BLC<9> A_BLC<8> A_BLC<7> A_BLC<6> A_BLC<5> A_BLC<4> A_BLC<3> A_BLC<2> ++ A_BLC<1> A_BLC<0> A_BLT<31> A_BLT<30> A_BLT<29> A_BLT<28> A_BLT<27> ++ A_BLT<26> A_BLT<25> A_BLT<24> A_BLT<23> A_BLT<22> A_BLT<21> A_BLT<20> ++ A_BLT<19> A_BLT<18> A_BLT<17> A_BLT<16> A_BLT<15> A_BLT<14> A_BLT<13> ++ A_BLT<12> A_BLT<11> A_BLT<10> A_BLT<9> A_BLT<8> A_BLT<7> A_BLT<6> A_BLT<5> ++ A_BLT<4> A_BLT<3> A_BLT<2> A_BLT<1> A_BLT<0> A_BM_I A_DCLK_B_L A_DCLK_B_R ++ A_DCLK_L A_DCLK_R A_DR_O A_DW_I A_RCLK_B_L A_RCLK_B_R A_RCLK_L A_RCLK_R ++ A_TIEH_O A_WCLK_B_L A_WCLK_B_R A_WCLK_L A_WCLK_R VDD VSS +XA_I80<1> A_WCLK_B_L A_RCLK_B_L A_W_nor_R<1> VDD VSS / ++ RSC_IHPSG13_AND2X2 +XA_I80<0> A_WCLK_B_L A_RCLK_B_L A_W_nor_R<0> VDD VSS / ++ RSC_IHPSG13_AND2X2 +XA_I44 A_BM_N A_WCLK_B_L A_DO_WRITE_P VDD VSS / RSC_IHPSG13_NOR2X2 +XI80<29> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI80<28> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI80<27> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI80<26> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI80<25> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI80<24> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI80<23> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI80<22> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI80<21> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI80<20> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI80<19> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI80<18> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI80<17> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI80<16> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI80<15> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI80<14> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI80<13> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI80<12> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI80<11> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI80<10> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI80<9> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI80<8> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI80<7> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI80<6> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI80<5> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI80<4> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI80<3> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI80<2> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI80<1> VDD VSS / RSC_IHPSG13_FILLCAP8 +XA_I74<16> VDD VSS / RSC_IHPSG13_FILLCAP8 +XA_I74<15> VDD VSS / RSC_IHPSG13_FILLCAP8 +XA_I74<14> VDD VSS / RSC_IHPSG13_FILLCAP8 +XA_I74<13> VDD VSS / RSC_IHPSG13_FILLCAP8 +XA_I74<12> VDD VSS / RSC_IHPSG13_FILLCAP8 +XA_I74<11> VDD VSS / RSC_IHPSG13_FILLCAP8 +XA_I74<10> VDD VSS / RSC_IHPSG13_FILLCAP8 +XA_I74<9> VDD VSS / RSC_IHPSG13_FILLCAP8 +XA_I74<8> VDD VSS / RSC_IHPSG13_FILLCAP8 +XA_I74<7> VDD VSS / RSC_IHPSG13_FILLCAP8 +XA_I74<6> VDD VSS / RSC_IHPSG13_FILLCAP8 +XA_I74<5> VDD VSS / RSC_IHPSG13_FILLCAP8 +XA_I74<4> VDD VSS / RSC_IHPSG13_FILLCAP8 +XA_I74<3> VDD VSS / RSC_IHPSG13_FILLCAP8 +XA_I74<2> VDD VSS / RSC_IHPSG13_FILLCAP8 +XA_I74<1> VDD VSS / RSC_IHPSG13_FILLCAP8 +XA_INV<6> A_N1<1> A_P1<1> VDD VSS / RSC_IHPSG13_CINVX4 +XA_INV<5> A_N0<1> A_P0<1> VDD VSS / RSC_IHPSG13_CINVX4 +XA_INV<4> A_N0<0> A_P0<0> VDD VSS / RSC_IHPSG13_CINVX4 +XA_INV<3> A_ADDR_COL<1> A_N1<1> VDD VSS / RSC_IHPSG13_CINVX4 +XA_INV<2> A_ADDR_COL<1> A_N1<0> VDD VSS / RSC_IHPSG13_CINVX4 +XA_INV<1> A_ADDR_COL<0> A_N0<1> VDD VSS / RSC_IHPSG13_CINVX4 +XA_INV<0> A_ADDR_COL<0> A_N0<0> VDD VSS / RSC_IHPSG13_CINVX4 +XA_I81<3> A_W_nor_R<1> A_PRE_N VDD VSS / RSC_IHPSG13_CINVX4_WN +XA_I81<2> A_W_nor_R<1> A_PRE_N VDD VSS / RSC_IHPSG13_CINVX4_WN +XA_I81<1> A_W_nor_R<0> A_PRE_N VDD VSS / RSC_IHPSG13_CINVX4_WN +XA_I81<0> A_W_nor_R<0> A_PRE_N VDD VSS / RSC_IHPSG13_CINVX4_WN +XA_BLTMUX<31> A_BLC<31> A_BLC_SEL A_BLT<31> A_BLT_SEL A_PRE_N A_SEL_P<31> ++ A_WR_ONE A_WR_ZERO VDD VSS / RM_IHPSG13_256x8_c2_1P_BLDRV +XA_BLTMUX<30> A_BLC<30> A_BLC_SEL A_BLT<30> A_BLT_SEL A_PRE_N A_SEL_P<30> ++ A_WR_ONE A_WR_ZERO VDD VSS / RM_IHPSG13_256x8_c2_1P_BLDRV +XA_BLTMUX<29> A_BLC<29> A_BLC_SEL A_BLT<29> A_BLT_SEL A_PRE_N A_SEL_P<29> ++ A_WR_ONE A_WR_ZERO VDD VSS / RM_IHPSG13_256x8_c2_1P_BLDRV +XA_BLTMUX<28> A_BLC<28> A_BLC_SEL A_BLT<28> A_BLT_SEL A_PRE_N A_SEL_P<28> ++ A_WR_ONE A_WR_ZERO VDD VSS / RM_IHPSG13_256x8_c2_1P_BLDRV +XA_BLTMUX<27> A_BLC<27> A_BLC_SEL A_BLT<27> A_BLT_SEL A_PRE_N A_SEL_P<27> ++ A_WR_ONE A_WR_ZERO VDD VSS / RM_IHPSG13_256x8_c2_1P_BLDRV +XA_BLTMUX<26> A_BLC<26> A_BLC_SEL A_BLT<26> A_BLT_SEL A_PRE_N A_SEL_P<26> ++ A_WR_ONE A_WR_ZERO VDD VSS / RM_IHPSG13_256x8_c2_1P_BLDRV +XA_BLTMUX<25> A_BLC<25> A_BLC_SEL A_BLT<25> A_BLT_SEL A_PRE_N A_SEL_P<25> ++ A_WR_ONE A_WR_ZERO VDD VSS / RM_IHPSG13_256x8_c2_1P_BLDRV +XA_BLTMUX<24> A_BLC<24> A_BLC_SEL A_BLT<24> A_BLT_SEL A_PRE_N A_SEL_P<24> ++ A_WR_ONE A_WR_ZERO VDD VSS / RM_IHPSG13_256x8_c2_1P_BLDRV +XA_BLTMUX<23> A_BLC<23> A_BLC_SEL A_BLT<23> A_BLT_SEL A_PRE_N A_SEL_P<23> ++ A_WR_ONE A_WR_ZERO VDD VSS / RM_IHPSG13_256x8_c2_1P_BLDRV +XA_BLTMUX<22> A_BLC<22> A_BLC_SEL A_BLT<22> A_BLT_SEL A_PRE_N A_SEL_P<22> ++ A_WR_ONE A_WR_ZERO VDD VSS / RM_IHPSG13_256x8_c2_1P_BLDRV +XA_BLTMUX<21> A_BLC<21> A_BLC_SEL A_BLT<21> A_BLT_SEL A_PRE_N A_SEL_P<21> ++ A_WR_ONE A_WR_ZERO VDD VSS / RM_IHPSG13_256x8_c2_1P_BLDRV +XA_BLTMUX<20> A_BLC<20> A_BLC_SEL A_BLT<20> A_BLT_SEL A_PRE_N A_SEL_P<20> ++ A_WR_ONE A_WR_ZERO VDD VSS / RM_IHPSG13_256x8_c2_1P_BLDRV +XA_BLTMUX<19> A_BLC<19> A_BLC_SEL A_BLT<19> A_BLT_SEL A_PRE_N A_SEL_P<19> ++ A_WR_ONE A_WR_ZERO VDD VSS / RM_IHPSG13_256x8_c2_1P_BLDRV +XA_BLTMUX<18> A_BLC<18> A_BLC_SEL A_BLT<18> A_BLT_SEL A_PRE_N A_SEL_P<18> ++ A_WR_ONE A_WR_ZERO VDD VSS / RM_IHPSG13_256x8_c2_1P_BLDRV +XA_BLTMUX<17> A_BLC<17> A_BLC_SEL A_BLT<17> A_BLT_SEL A_PRE_N A_SEL_P<17> ++ A_WR_ONE A_WR_ZERO VDD VSS / RM_IHPSG13_256x8_c2_1P_BLDRV +XA_BLTMUX<16> A_BLC<16> A_BLC_SEL A_BLT<16> A_BLT_SEL A_PRE_N A_SEL_P<16> ++ A_WR_ONE A_WR_ZERO VDD VSS / RM_IHPSG13_256x8_c2_1P_BLDRV +XA_BLTMUX<15> A_BLC<15> A_BLC_SEL A_BLT<15> A_BLT_SEL A_PRE_N A_SEL_P<15> ++ A_WR_ONE A_WR_ZERO VDD VSS / RM_IHPSG13_256x8_c2_1P_BLDRV +XA_BLTMUX<14> A_BLC<14> A_BLC_SEL A_BLT<14> A_BLT_SEL A_PRE_N A_SEL_P<14> ++ A_WR_ONE A_WR_ZERO VDD VSS / RM_IHPSG13_256x8_c2_1P_BLDRV +XA_BLTMUX<13> A_BLC<13> A_BLC_SEL A_BLT<13> A_BLT_SEL A_PRE_N A_SEL_P<13> ++ A_WR_ONE A_WR_ZERO VDD VSS / RM_IHPSG13_256x8_c2_1P_BLDRV +XA_BLTMUX<12> A_BLC<12> A_BLC_SEL A_BLT<12> A_BLT_SEL A_PRE_N A_SEL_P<12> ++ A_WR_ONE A_WR_ZERO VDD VSS / RM_IHPSG13_256x8_c2_1P_BLDRV +XA_BLTMUX<11> A_BLC<11> A_BLC_SEL A_BLT<11> A_BLT_SEL A_PRE_N A_SEL_P<11> ++ A_WR_ONE A_WR_ZERO VDD VSS / RM_IHPSG13_256x8_c2_1P_BLDRV +XA_BLTMUX<10> A_BLC<10> A_BLC_SEL A_BLT<10> A_BLT_SEL A_PRE_N A_SEL_P<10> ++ A_WR_ONE A_WR_ZERO VDD VSS / RM_IHPSG13_256x8_c2_1P_BLDRV +XA_BLTMUX<9> A_BLC<9> A_BLC_SEL A_BLT<9> A_BLT_SEL A_PRE_N A_SEL_P<9> A_WR_ONE ++ A_WR_ZERO VDD VSS / RM_IHPSG13_256x8_c2_1P_BLDRV +XA_BLTMUX<8> A_BLC<8> A_BLC_SEL A_BLT<8> A_BLT_SEL A_PRE_N A_SEL_P<8> A_WR_ONE ++ A_WR_ZERO VDD VSS / RM_IHPSG13_256x8_c2_1P_BLDRV +XA_BLTMUX<7> A_BLC<7> A_BLC_SEL A_BLT<7> A_BLT_SEL A_PRE_N A_SEL_P<7> A_WR_ONE ++ A_WR_ZERO VDD VSS / RM_IHPSG13_256x8_c2_1P_BLDRV +XA_BLTMUX<6> A_BLC<6> A_BLC_SEL A_BLT<6> A_BLT_SEL A_PRE_N A_SEL_P<6> A_WR_ONE ++ A_WR_ZERO VDD VSS / RM_IHPSG13_256x8_c2_1P_BLDRV +XA_BLTMUX<5> A_BLC<5> A_BLC_SEL A_BLT<5> A_BLT_SEL A_PRE_N A_SEL_P<5> A_WR_ONE ++ A_WR_ZERO VDD VSS / RM_IHPSG13_256x8_c2_1P_BLDRV +XA_BLTMUX<4> A_BLC<4> A_BLC_SEL A_BLT<4> A_BLT_SEL A_PRE_N A_SEL_P<4> A_WR_ONE ++ A_WR_ZERO VDD VSS / RM_IHPSG13_256x8_c2_1P_BLDRV +XA_BLTMUX<3> A_BLC<3> A_BLC_SEL A_BLT<3> A_BLT_SEL A_PRE_N A_SEL_P<3> A_WR_ONE ++ A_WR_ZERO VDD VSS / RM_IHPSG13_256x8_c2_1P_BLDRV +XA_BLTMUX<2> A_BLC<2> A_BLC_SEL A_BLT<2> A_BLT_SEL A_PRE_N A_SEL_P<2> A_WR_ONE ++ A_WR_ZERO VDD VSS / RM_IHPSG13_256x8_c2_1P_BLDRV +XA_BLTMUX<1> A_BLC<1> A_BLC_SEL A_BLT<1> A_BLT_SEL A_PRE_N A_SEL_P<1> A_WR_ONE ++ A_WR_ZERO VDD VSS / RM_IHPSG13_256x8_c2_1P_BLDRV +XA_BLTMUX<0> A_BLC<0> A_BLC_SEL A_BLT<0> A_BLT_SEL A_PRE_N A_SEL_P<0> A_WR_ONE ++ A_WR_ZERO VDD VSS / RM_IHPSG13_256x8_c2_1P_BLDRV +XA_CAPS<17> VDD VSS / RSC_IHPSG13_FILLCAP4 +XA_CAPS<16> VDD VSS / RSC_IHPSG13_FILLCAP4 +XA_CAPS<15> VDD VSS / RSC_IHPSG13_FILLCAP4 +XA_CAPS<14> VDD VSS / RSC_IHPSG13_FILLCAP4 +XA_CAPS<13> VDD VSS / RSC_IHPSG13_FILLCAP4 +XA_CAPS<12> VDD VSS / RSC_IHPSG13_FILLCAP4 +XA_CAPS<11> VDD VSS / RSC_IHPSG13_FILLCAP4 +XA_CAPS<10> VDD VSS / RSC_IHPSG13_FILLCAP4 +XA_CAPS<9> VDD VSS / RSC_IHPSG13_FILLCAP4 +XA_CAPS<8> VDD VSS / RSC_IHPSG13_FILLCAP4 +XA_CAPS<7> VDD VSS / RSC_IHPSG13_FILLCAP4 +XA_CAPS<6> VDD VSS / RSC_IHPSG13_FILLCAP4 +XA_CAPS<5> VDD VSS / RSC_IHPSG13_FILLCAP4 +XA_CAPS<4> VDD VSS / RSC_IHPSG13_FILLCAP4 +XA_CAPS<3> VDD VSS / RSC_IHPSG13_FILLCAP4 +XA_CAPS<2> VDD VSS / RSC_IHPSG13_FILLCAP4 +XA_CAPS<1> VDD VSS / RSC_IHPSG13_FILLCAP4 +XA_I51 net19 A_DR_O VDD VSS / RSC_IHPSG13_INVX4 +XA_I78 A_RCLK_B_L A_SAE VDD VSS / RSC_IHPSG13_CBUFX2 +XA_I69 A_DCLK_L A_DCLK_B_L VDD VSS / RSC_IHPSG13_CINVX8 +XA_I50 A_WCLK_L A_WCLK_B_L VDD VSS / RSC_IHPSG13_CINVX8 +XA_EBUF A_RCLK_L A_RCLK_B_L VDD VSS / RSC_IHPSG13_CINVX8 +XA_I76 A_DI_N A_DO_WRITE_P A_WR_ZERO VDD VSS / RSC_IHPSG13_AND2X6 +XA_I75 A_DI_R A_DO_WRITE_P A_WR_ONE VDD VSS / RSC_IHPSG13_AND2X6 +XA_I83 A_BM_R A_BM_N VDD VSS / RSC_IHPSG13_INVX2 +XA_DEC3INV<31> net23<0> A_SEL_P<31> VDD VSS / RSC_IHPSG13_INVX2 +XA_DEC3INV<30> net23<1> A_SEL_P<30> VDD VSS / RSC_IHPSG13_INVX2 +XA_DEC3INV<29> net23<2> A_SEL_P<29> VDD VSS / RSC_IHPSG13_INVX2 +XA_DEC3INV<28> net23<3> A_SEL_P<28> VDD VSS / RSC_IHPSG13_INVX2 +XA_DEC3INV<27> net23<4> A_SEL_P<27> VDD VSS / RSC_IHPSG13_INVX2 +XA_DEC3INV<26> net23<5> A_SEL_P<26> VDD VSS / RSC_IHPSG13_INVX2 +XA_DEC3INV<25> net23<6> A_SEL_P<25> VDD VSS / RSC_IHPSG13_INVX2 +XA_DEC3INV<24> net23<7> A_SEL_P<24> VDD VSS / RSC_IHPSG13_INVX2 +XA_DEC3INV<23> net23<8> A_SEL_P<23> VDD VSS / RSC_IHPSG13_INVX2 +XA_DEC3INV<22> net23<9> A_SEL_P<22> VDD VSS / RSC_IHPSG13_INVX2 +XA_DEC3INV<21> net23<10> A_SEL_P<21> VDD VSS / RSC_IHPSG13_INVX2 +XA_DEC3INV<20> net23<11> A_SEL_P<20> VDD VSS / RSC_IHPSG13_INVX2 +XA_DEC3INV<19> net23<12> A_SEL_P<19> VDD VSS / RSC_IHPSG13_INVX2 +XA_DEC3INV<18> net23<13> A_SEL_P<18> VDD VSS / RSC_IHPSG13_INVX2 +XA_DEC3INV<17> net23<14> A_SEL_P<17> VDD VSS / RSC_IHPSG13_INVX2 +XA_DEC3INV<16> net23<15> A_SEL_P<16> VDD VSS / RSC_IHPSG13_INVX2 +XA_DEC3INV<15> net23<16> A_SEL_P<15> VDD VSS / RSC_IHPSG13_INVX2 +XA_DEC3INV<14> net23<17> A_SEL_P<14> VDD VSS / RSC_IHPSG13_INVX2 +XA_DEC3INV<13> net23<18> A_SEL_P<13> VDD VSS / RSC_IHPSG13_INVX2 +XA_DEC3INV<12> net23<19> A_SEL_P<12> VDD VSS / RSC_IHPSG13_INVX2 +XA_DEC3INV<11> net23<20> A_SEL_P<11> VDD VSS / RSC_IHPSG13_INVX2 +XA_DEC3INV<10> net23<21> A_SEL_P<10> VDD VSS / RSC_IHPSG13_INVX2 +XA_DEC3INV<9> net23<22> A_SEL_P<9> VDD VSS / RSC_IHPSG13_INVX2 +XA_DEC3INV<8> net23<23> A_SEL_P<8> VDD VSS / RSC_IHPSG13_INVX2 +XA_DEC3INV<7> net23<24> A_SEL_P<7> VDD VSS / RSC_IHPSG13_INVX2 +XA_DEC3INV<6> net23<25> A_SEL_P<6> VDD VSS / RSC_IHPSG13_INVX2 +XA_DEC3INV<5> net23<26> A_SEL_P<5> VDD VSS / RSC_IHPSG13_INVX2 +XA_DEC3INV<4> net23<27> A_SEL_P<4> VDD VSS / RSC_IHPSG13_INVX2 +XA_DEC3INV<3> net23<28> A_SEL_P<3> VDD VSS / RSC_IHPSG13_INVX2 +XA_DEC3INV<2> net23<29> A_SEL_P<2> VDD VSS / RSC_IHPSG13_INVX2 +XA_DEC3INV<1> net23<30> A_SEL_P<1> VDD VSS / RSC_IHPSG13_INVX2 +XA_DEC3INV<0> net23<31> A_SEL_P<0> VDD VSS / RSC_IHPSG13_INVX2 +XA_I49 A_DI_R A_DI_N VDD VSS / RSC_IHPSG13_INVX2 +XA_ISENSE A_SAE A_BLC_SEL A_BLT_SEL net19 net20 VDD VSS / ++ RSC_IHPSG13_DFPQD_MSAFFX2 +XA_DREG A_BIST_EN_I A_BIST_DW_I A_DCLK_B_L A_DW_I A_DI_R net22 VDD VSS ++ / RSC_IHPSG13_DFNQMX2IX1 +XA_BREG A_BIST_EN_I A_BIST_BM_I A_DCLK_B_L A_BM_I A_BM_R net21 VDD VSS ++ / RSC_IHPSG13_DFNQMX2IX1 +XA_DEC3<31> A_P1<1> A_P0<1> A_ADDR_DEC<7> net23<0> VDD VSS / ++ RSC_IHPSG13_NAND3X2 +XA_DEC3<30> A_P1<1> A_P0<1> A_ADDR_DEC<6> net23<1> VDD VSS / ++ RSC_IHPSG13_NAND3X2 +XA_DEC3<29> A_P1<1> A_P0<1> A_ADDR_DEC<5> net23<2> VDD VSS / ++ RSC_IHPSG13_NAND3X2 +XA_DEC3<28> A_P1<1> A_P0<1> A_ADDR_DEC<4> net23<3> VDD VSS / ++ RSC_IHPSG13_NAND3X2 +XA_DEC3<27> A_P1<1> A_P0<1> A_ADDR_DEC<3> net23<4> VDD VSS / ++ RSC_IHPSG13_NAND3X2 +XA_DEC3<26> A_P1<1> A_P0<1> A_ADDR_DEC<2> net23<5> VDD VSS / ++ RSC_IHPSG13_NAND3X2 +XA_DEC3<25> A_P1<1> A_P0<1> A_ADDR_DEC<1> net23<6> VDD VSS / ++ RSC_IHPSG13_NAND3X2 +XA_DEC3<24> A_P1<1> A_P0<1> A_ADDR_DEC<0> net23<7> VDD VSS / ++ RSC_IHPSG13_NAND3X2 +XA_DEC3<23> A_P1<1> A_N0<1> A_ADDR_DEC<7> net23<8> VDD VSS / ++ RSC_IHPSG13_NAND3X2 +XA_DEC3<22> A_P1<1> A_N0<1> A_ADDR_DEC<6> net23<9> VDD VSS / ++ RSC_IHPSG13_NAND3X2 +XA_DEC3<21> A_P1<1> A_N0<1> A_ADDR_DEC<5> net23<10> VDD VSS / ++ RSC_IHPSG13_NAND3X2 +XA_DEC3<20> A_P1<1> A_N0<1> A_ADDR_DEC<4> net23<11> VDD VSS / ++ RSC_IHPSG13_NAND3X2 +XA_DEC3<19> A_P1<1> A_N0<1> A_ADDR_DEC<3> net23<12> VDD VSS / ++ RSC_IHPSG13_NAND3X2 +XA_DEC3<18> A_P1<1> A_N0<1> A_ADDR_DEC<2> net23<13> VDD VSS / ++ RSC_IHPSG13_NAND3X2 +XA_DEC3<17> A_P1<1> A_N0<1> A_ADDR_DEC<1> net23<14> VDD VSS / ++ RSC_IHPSG13_NAND3X2 +XA_DEC3<16> A_P1<1> A_N0<1> A_ADDR_DEC<0> net23<15> VDD VSS / ++ RSC_IHPSG13_NAND3X2 +XA_DEC3<15> A_N1<0> A_P0<0> A_ADDR_DEC<7> net23<16> VDD VSS / ++ RSC_IHPSG13_NAND3X2 +XA_DEC3<14> A_N1<0> A_P0<0> A_ADDR_DEC<6> net23<17> VDD VSS / ++ RSC_IHPSG13_NAND3X2 +XA_DEC3<13> A_N1<0> A_P0<0> A_ADDR_DEC<5> net23<18> VDD VSS / ++ RSC_IHPSG13_NAND3X2 +XA_DEC3<12> A_N1<0> A_P0<0> A_ADDR_DEC<4> net23<19> VDD VSS / ++ RSC_IHPSG13_NAND3X2 +XA_DEC3<11> A_N1<0> A_P0<0> A_ADDR_DEC<3> net23<20> VDD VSS / ++ RSC_IHPSG13_NAND3X2 +XA_DEC3<10> A_N1<0> A_P0<0> A_ADDR_DEC<2> net23<21> VDD VSS / ++ RSC_IHPSG13_NAND3X2 +XA_DEC3<9> A_N1<0> A_P0<0> A_ADDR_DEC<1> net23<22> VDD VSS / ++ RSC_IHPSG13_NAND3X2 +XA_DEC3<8> A_N1<0> A_P0<0> A_ADDR_DEC<0> net23<23> VDD VSS / ++ RSC_IHPSG13_NAND3X2 +XA_DEC3<7> A_N1<0> A_N0<0> A_ADDR_DEC<7> net23<24> VDD VSS / ++ RSC_IHPSG13_NAND3X2 +XA_DEC3<6> A_N1<0> A_N0<0> A_ADDR_DEC<6> net23<25> VDD VSS / ++ RSC_IHPSG13_NAND3X2 +XA_DEC3<5> A_N1<0> A_N0<0> A_ADDR_DEC<5> net23<26> VDD VSS / ++ RSC_IHPSG13_NAND3X2 +XA_DEC3<4> A_N1<0> A_N0<0> A_ADDR_DEC<4> net23<27> VDD VSS / ++ RSC_IHPSG13_NAND3X2 +XA_DEC3<3> A_N1<0> A_N0<0> A_ADDR_DEC<3> net23<28> VDD VSS / ++ RSC_IHPSG13_NAND3X2 +XA_DEC3<2> A_N1<0> A_N0<0> A_ADDR_DEC<2> net23<29> VDD VSS / ++ RSC_IHPSG13_NAND3X2 +XA_DEC3<1> A_N1<0> A_N0<0> A_ADDR_DEC<1> net23<30> VDD VSS / ++ RSC_IHPSG13_NAND3X2 +XA_DEC3<0> A_N1<0> A_N0<0> A_ADDR_DEC<0> net23<31> VDD VSS / ++ RSC_IHPSG13_NAND3X2 +XA_I89 A_DCLK_B_L A_DCLK_B_R / RSC_IHPSG13_MET3RES +XA_I91 A_RCLK_B_L A_RCLK_B_R / RSC_IHPSG13_MET3RES +XA_I90 A_WCLK_B_L A_WCLK_B_R / RSC_IHPSG13_MET3RES +XA_I88 A_DCLK_L A_DCLK_R / RSC_IHPSG13_MET3RES +XA_I87 A_WCLK_L A_WCLK_R / RSC_IHPSG13_MET3RES +XA_R2 A_RCLK_L A_RCLK_R / RSC_IHPSG13_MET3RES +XA_BM_TIEH A_TIEH_O VDD VSS / RSC_IHPSG13_TIEH +.ENDS + +.SUBCKT RM_IHPSG13_256x8_c2_1P_COLDRV13X12 ADDR_COL_I<1> ADDR_COL_I<0> ADDR_COL_O<1> ++ ADDR_COL_O<0> ADDR_DEC_I<7> ADDR_DEC_I<6> ADDR_DEC_I<5> ADDR_DEC_I<4> ++ ADDR_DEC_I<3> ADDR_DEC_I<2> ADDR_DEC_I<1> ADDR_DEC_I<0> ADDR_DEC_O<7> ++ ADDR_DEC_O<6> ADDR_DEC_O<5> ADDR_DEC_O<4> ADDR_DEC_O<3> ADDR_DEC_O<2> ++ ADDR_DEC_O<1> ADDR_DEC_O<0> DCLK_I DCLK_O RCLK_I RCLK_O WCLK_I WCLK_O ++ VDD VSS +XI1<1> VDD VSS / RSC_IHPSG13_FILLCAP4 +XI1<0> VDD VSS / RSC_IHPSG13_FILLCAP4 +XI0<1> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI0<0> VDD VSS / RSC_IHPSG13_FILLCAP8 +XADDR_COL_DRV<1> ADDR_COL_I<1> ADDR_COL_O<1> VDD VSS / ++ RSC_IHPSG13_CBUFX12 +XADDR_COL_DRV<0> ADDR_COL_I<0> ADDR_COL_O<0> VDD VSS / ++ RSC_IHPSG13_CBUFX12 +XADDR_DEC_DRV<7> ADDR_DEC_I<7> ADDR_DEC_O<7> VDD VSS / ++ RSC_IHPSG13_CBUFX12 +XADDR_DEC_DRV<6> ADDR_DEC_I<6> ADDR_DEC_O<6> VDD VSS / ++ RSC_IHPSG13_CBUFX12 +XADDR_DEC_DRV<5> ADDR_DEC_I<5> ADDR_DEC_O<5> VDD VSS / ++ RSC_IHPSG13_CBUFX12 +XADDR_DEC_DRV<4> ADDR_DEC_I<4> ADDR_DEC_O<4> VDD VSS / ++ RSC_IHPSG13_CBUFX12 +XADDR_DEC_DRV<3> ADDR_DEC_I<3> ADDR_DEC_O<3> VDD VSS / ++ RSC_IHPSG13_CBUFX12 +XADDR_DEC_DRV<2> ADDR_DEC_I<2> ADDR_DEC_O<2> VDD VSS / ++ RSC_IHPSG13_CBUFX12 +XADDR_DEC_DRV<1> ADDR_DEC_I<1> ADDR_DEC_O<1> VDD VSS / ++ RSC_IHPSG13_CBUFX12 +XADDR_DEC_DRV<0> ADDR_DEC_I<0> ADDR_DEC_O<0> VDD VSS / ++ RSC_IHPSG13_CBUFX12 +XDCLK_DRV DCLK_I DCLK_O VDD VSS / RSC_IHPSG13_CBUFX12 +XRCLK_DRV RCLK_I RCLK_O VDD VSS / RSC_IHPSG13_CBUFX12 +XWCLK_DRV WCLK_I WCLK_O VDD VSS / RSC_IHPSG13_CBUFX12 +.ENDS +.SUBCKT RM_IHPSG13_256x8_c2_1P_WLDRV16X12 A<15> A<14> A<13> A<12> A<11> A<10> A<9> A<8> ++ A<7> A<6> A<5> A<4> A<3> A<2> A<1> A<0> Z<15> Z<14> Z<13> Z<12> Z<11> Z<10> ++ Z<9> Z<8> Z<7> Z<6> Z<5> Z<4> Z<3> Z<2> Z<1> Z<0> VDD VSS +XBUF<15> A<15> Z<15> VDD VSS / RSC_IHPSG13_WLDRVX12 +XBUF<14> A<14> Z<14> VDD VSS / RSC_IHPSG13_WLDRVX12 +XBUF<13> A<13> Z<13> VDD VSS / RSC_IHPSG13_WLDRVX12 +XBUF<12> A<12> Z<12> VDD VSS / RSC_IHPSG13_WLDRVX12 +XBUF<11> A<11> Z<11> VDD VSS / RSC_IHPSG13_WLDRVX12 +XBUF<10> A<10> Z<10> VDD VSS / RSC_IHPSG13_WLDRVX12 +XBUF<9> A<9> Z<9> VDD VSS / RSC_IHPSG13_WLDRVX12 +XBUF<8> A<8> Z<8> VDD VSS / RSC_IHPSG13_WLDRVX12 +XBUF<7> A<7> Z<7> VDD VSS / RSC_IHPSG13_WLDRVX12 +XBUF<6> A<6> Z<6> VDD VSS / RSC_IHPSG13_WLDRVX12 +XBUF<5> A<5> Z<5> VDD VSS / RSC_IHPSG13_WLDRVX12 +XBUF<4> A<4> Z<4> VDD VSS / RSC_IHPSG13_WLDRVX12 +XBUF<3> A<3> Z<3> VDD VSS / RSC_IHPSG13_WLDRVX12 +XBUF<2> A<2> Z<2> VDD VSS / RSC_IHPSG13_WLDRVX12 +XBUF<1> A<1> Z<1> VDD VSS / RSC_IHPSG13_WLDRVX12 +XBUF<0> A<0> Z<0> VDD VSS / RSC_IHPSG13_WLDRVX12 +.ENDS + + + +.SUBCKT RM_IHPSG13_256x8_c2_2P_COLDRV13X8 ADDR_COL_I<1> ADDR_COL_I<0> ADDR_COL_O<1> ++ ADDR_COL_O<0> ADDR_DEC_I<7> ADDR_DEC_I<6> ADDR_DEC_I<5> ADDR_DEC_I<4> ++ ADDR_DEC_I<3> ADDR_DEC_I<2> ADDR_DEC_I<1> ADDR_DEC_I<0> ADDR_DEC_O<7> ++ ADDR_DEC_O<6> ADDR_DEC_O<5> ADDR_DEC_O<4> ADDR_DEC_O<3> ADDR_DEC_O<2> ++ ADDR_DEC_O<1> ADDR_DEC_O<0> DCLK_I DCLK_O RCLK_I RCLK_O WCLK_I WCLK_O ++ VDD VSS +XI0<5> VDD VSS / RSC_IHPSG13_FILLCAP4 +XI0<4> VDD VSS / RSC_IHPSG13_FILLCAP4 +XI0<3> VDD VSS / RSC_IHPSG13_FILLCAP4 +XI0<2> VDD VSS / RSC_IHPSG13_FILLCAP4 +XI0<1> VDD VSS / RSC_IHPSG13_FILLCAP4 +XWCLK_DRV WCLK_I WCLK_O VDD VSS / RSC_IHPSG13_CBUFX8 +XRCLK_DRV RCLK_I RCLK_O VDD VSS / RSC_IHPSG13_CBUFX8 +XDCLK_DRV DCLK_I DCLK_O VDD VSS / RSC_IHPSG13_CBUFX8 +XADDR_COL_DRV<1> ADDR_COL_I<1> ADDR_COL_O<1> VDD VSS / ++ RSC_IHPSG13_CBUFX8 +XADDR_COL_DRV<0> ADDR_COL_I<0> ADDR_COL_O<0> VDD VSS / ++ RSC_IHPSG13_CBUFX8 +XADDR_DEC_DRV<7> ADDR_DEC_I<7> ADDR_DEC_O<7> VDD VSS / ++ RSC_IHPSG13_CBUFX8 +XADDR_DEC_DRV<6> ADDR_DEC_I<6> ADDR_DEC_O<6> VDD VSS / ++ RSC_IHPSG13_CBUFX8 +XADDR_DEC_DRV<5> ADDR_DEC_I<5> ADDR_DEC_O<5> VDD VSS / ++ RSC_IHPSG13_CBUFX8 +XADDR_DEC_DRV<4> ADDR_DEC_I<4> ADDR_DEC_O<4> VDD VSS / ++ RSC_IHPSG13_CBUFX8 +XADDR_DEC_DRV<3> ADDR_DEC_I<3> ADDR_DEC_O<3> VDD VSS / ++ RSC_IHPSG13_CBUFX8 +XADDR_DEC_DRV<2> ADDR_DEC_I<2> ADDR_DEC_O<2> VDD VSS / ++ RSC_IHPSG13_CBUFX8 +XADDR_DEC_DRV<1> ADDR_DEC_I<1> ADDR_DEC_O<1> VDD VSS / ++ RSC_IHPSG13_CBUFX8 +XADDR_DEC_DRV<0> ADDR_DEC_I<0> ADDR_DEC_O<0> VDD VSS / ++ RSC_IHPSG13_CBUFX8 +XI1<3> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI1<2> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI1<1> VDD VSS / RSC_IHPSG13_FILLCAP8 +.ENDS +.SUBCKT RSC_IHPSG13_WLDRVX8 A Z VDD VSS +MN1 Z net6 VSS VSS sg13_lv_nmos m=1 w=1.41u l=130.00n ng=2 nrd=0 nrs=0 +MN0 net6 A VSS VSS sg13_lv_nmos m=1 w=1.8u l=130.00n ng=2 nrd=0 nrs=0 +MP1 Z net6 VDD VDD sg13_lv_pmos m=1 w=6.48u l=130.00n ng=4 nrd=0 nrs=0 +MP0 net6 A VDD VDD sg13_lv_pmos m=1 w=900.0n l=130.00n ng=1 nrd=0 nrs=0 +.ENDS +.SUBCKT RM_IHPSG13_256x8_c2_2P_WLDRV16X8 A<15> A<14> A<13> A<12> A<11> A<10> A<9> A<8> ++ A<7> A<6> A<5> A<4> A<3> A<2> A<1> A<0> Z<15> Z<14> Z<13> Z<12> Z<11> Z<10> ++ Z<9> Z<8> Z<7> Z<6> Z<5> Z<4> Z<3> Z<2> Z<1> Z<0> VDD VSS +XBUF<15> A<15> Z<15> VDD VSS / RSC_IHPSG13_WLDRVX8 +XBUF<14> A<14> Z<14> VDD VSS / RSC_IHPSG13_WLDRVX8 +XBUF<13> A<13> Z<13> VDD VSS / RSC_IHPSG13_WLDRVX8 +XBUF<12> A<12> Z<12> VDD VSS / RSC_IHPSG13_WLDRVX8 +XBUF<11> A<11> Z<11> VDD VSS / RSC_IHPSG13_WLDRVX8 +XBUF<10> A<10> Z<10> VDD VSS / RSC_IHPSG13_WLDRVX8 +XBUF<9> A<9> Z<9> VDD VSS / RSC_IHPSG13_WLDRVX8 +XBUF<8> A<8> Z<8> VDD VSS / RSC_IHPSG13_WLDRVX8 +XBUF<7> A<7> Z<7> VDD VSS / RSC_IHPSG13_WLDRVX8 +XBUF<6> A<6> Z<6> VDD VSS / RSC_IHPSG13_WLDRVX8 +XBUF<5> A<5> Z<5> VDD VSS / RSC_IHPSG13_WLDRVX8 +XBUF<4> A<4> Z<4> VDD VSS / RSC_IHPSG13_WLDRVX8 +XBUF<3> A<3> Z<3> VDD VSS / RSC_IHPSG13_WLDRVX8 +XBUF<2> A<2> Z<2> VDD VSS / RSC_IHPSG13_WLDRVX8 +XBUF<1> A<1> Z<1> VDD VSS / RSC_IHPSG13_WLDRVX8 +XBUF<0> A<0> Z<0> VDD VSS / RSC_IHPSG13_WLDRVX8 +.ENDS + + + +.SUBCKT RM_IHPSG13_256x8_c2_2P_COLDEC2 ACLK_N ADDR<1> ADDR<0> ADDR_COL<1> ADDR_COL<0> ++ ADDR_DEC<7> ADDR_DEC<6> ADDR_DEC<5> ADDR_DEC<4> ADDR_DEC<3> ADDR_DEC<2> ++ ADDR_DEC<1> ADDR_DEC<0> BIST_ADDR<1> BIST_ADDR<0> BIST_EN_I VDD VSS +XI16<17> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI16<16> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI16<15> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI16<14> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI16<13> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI16<12> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI16<11> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI16<10> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI16<9> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI16<8> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI16<7> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI16<6> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI16<5> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI16<4> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI16<3> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI16<2> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI16<1> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI18<24> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI18<23> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI18<22> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI18<21> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI18<20> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI18<19> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI18<18> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI18<17> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI18<16> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI18<15> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI18<14> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI18<13> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI18<12> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI18<11> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI18<10> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI18<9> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI18<8> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI18<7> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI18<6> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI18<5> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI18<4> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI18<3> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI18<2> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI18<1> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI1<3> PADR<0> PADR<1> addr_n<3> VDD VSS / RSC_IHPSG13_NAND2X2 +XI1<2> NADR<0> PADR<1> addr_n<2> VDD VSS / RSC_IHPSG13_NAND2X2 +XI1<1> PADR<0> NADR<1> addr_n<1> VDD VSS / RSC_IHPSG13_NAND2X2 +XI1<0> NADR<0> NADR<1> addr_n<0> VDD VSS / RSC_IHPSG13_NAND2X2 +XI17<1> ADDR_COL<1> VDD VSS / RSC_IHPSG13_TIEL +XI17<0> ADDR_COL<0> VDD VSS / RSC_IHPSG13_TIEL +XI14<3> ADDR_DEC<7> VDD VSS / RSC_IHPSG13_TIEL +XI14<2> ADDR_DEC<6> VDD VSS / RSC_IHPSG13_TIEL +XI14<1> ADDR_DEC<5> VDD VSS / RSC_IHPSG13_TIEL +XI14<0> ADDR_DEC<4> VDD VSS / RSC_IHPSG13_TIEL +XI13<1> NADR<1> PADR<1> VDD VSS / RSC_IHPSG13_INVX2 +XI13<0> NADR<0> PADR<0> VDD VSS / RSC_IHPSG13_INVX2 +XI3<1> padr_int<1> NADR<1> VDD VSS / RSC_IHPSG13_INVX2 +XI3<0> padr_int<0> NADR<0> VDD VSS / RSC_IHPSG13_INVX2 +XI2<3> addr_n<3> ADDR_DEC<3> VDD VSS / RSC_IHPSG13_INVX2 +XI2<2> addr_n<2> ADDR_DEC<2> VDD VSS / RSC_IHPSG13_INVX2 +XI2<1> addr_n<1> ADDR_DEC<1> VDD VSS / RSC_IHPSG13_INVX2 +XI2<0> addr_n<0> ADDR_DEC<0> VDD VSS / RSC_IHPSG13_INVX2 +XDFF<1> BIST_EN_I BIST_ADDR<1> ACLK_N ADDR<1> padr_int<1> net12<0> VDD ++ VSS / RSC_IHPSG13_DFNQMX2IX1 +XDFF<0> BIST_EN_I BIST_ADDR<0> ACLK_N ADDR<0> padr_int<0> net12<1> VDD ++ VSS / RSC_IHPSG13_DFNQMX2IX1 +XI15<5> VDD VSS / RSC_IHPSG13_FILLCAP4 +XI15<4> VDD VSS / RSC_IHPSG13_FILLCAP4 +XI15<3> VDD VSS / RSC_IHPSG13_FILLCAP4 +XI15<2> VDD VSS / RSC_IHPSG13_FILLCAP4 +XI15<1> VDD VSS / RSC_IHPSG13_FILLCAP4 +XI19<4> VDD VSS / RSC_IHPSG13_FILLCAP4 +XI19<3> VDD VSS / RSC_IHPSG13_FILLCAP4 +XI19<2> VDD VSS / RSC_IHPSG13_FILLCAP4 +XI19<1> VDD VSS / RSC_IHPSG13_FILLCAP4 +.ENDS +.SUBCKT RM_IHPSG13_256x8_c2_2P_COLCTRL2 A_ADDR_DEC<3> A_ADDR_DEC<2> A_ADDR_DEC<1> ++ A_ADDR_DEC<0> A_BIST_BM_I A_BIST_DW_I A_BIST_EN_I A_BLC<3> A_BLC<2> A_BLC<1> ++ A_BLC<0> A_BLT<3> A_BLT<2> A_BLT<1> A_BLT<0> A_BM_I A_DCLK_B_L A_DCLK_B_R ++ A_DCLK_L A_DCLK_R A_DR_O A_DW_I A_RCLK_B_L A_RCLK_B_R A_RCLK_L A_RCLK_R ++ A_TIEH_O A_WCLK_B_L A_WCLK_B_R A_WCLK_L A_WCLK_R B_ADDR_DEC<3> B_ADDR_DEC<2> ++ B_ADDR_DEC<1> B_ADDR_DEC<0> B_BIST_BM_I B_BIST_DW_I B_BIST_EN_I B_BLC<3> ++ B_BLC<2> B_BLC<1> B_BLC<0> B_BLT<3> B_BLT<2> B_BLT<1> B_BLT<0> B_BM_I ++ B_DCLK_B_L B_DCLK_B_R B_DCLK_L B_DCLK_R B_DR_O B_DW_I B_RCLK_B_L B_RCLK_B_R ++ B_RCLK_L B_RCLK_R B_TIEH_O B_WCLK_B_L B_WCLK_B_R B_WCLK_L B_WCLK_R VDD ++ VSS +XB_DREG B_BIST_EN_I B_BIST_DW_I B_DCLK_B_L B_DW_I B_DI_R net046 VDD ++ VSS / RSC_IHPSG13_DFNQMX2IX1 +XB_BREG B_BIST_EN_I B_BIST_BM_I B_DCLK_B_L B_BM_I B_BM_R net045 VDD ++ VSS / RSC_IHPSG13_DFNQMX2IX1 +XA_DREG A_BIST_EN_I A_BIST_DW_I A_DCLK_B_L A_DW_I A_DI_R net22 VDD VSS ++ / RSC_IHPSG13_DFNQMX2IX1 +XA_BREG A_BIST_EN_I A_BIST_BM_I A_DCLK_B_L A_BM_I A_BM_R net23 VDD VSS ++ / RSC_IHPSG13_DFNQMX2IX1 +XB_CAPS VDD VSS / RSC_IHPSG13_FILLCAP4 +XA_CAPS VDD VSS / RSC_IHPSG13_FILLCAP4 +XB_I75 B_DI_R B_DO_WRITE_P B_WR_ONE VDD VSS / RSC_IHPSG13_AND2X2 +XB_I80 B_RCLK_B_L B_WCLK_B_L net041 VDD VSS / RSC_IHPSG13_AND2X2 +XB_I76 B_DI_N B_DO_WRITE_P B_WR_ZERO VDD VSS / RSC_IHPSG13_AND2X2 +XA_I80 A_RCLK_B_L A_WCLK_B_L net21 VDD VSS / RSC_IHPSG13_AND2X2 +XA_I75 A_DI_R A_DO_WRITE_P A_WR_ONE VDD VSS / RSC_IHPSG13_AND2X2 +XA_I76 A_DI_N A_DO_WRITE_P A_WR_ZERO VDD VSS / RSC_IHPSG13_AND2X2 +XB_I44 B_WCLK_B_L B_BM_N B_DO_WRITE_P VDD VSS / RSC_IHPSG13_NOR2X2 +XA_I44 A_WCLK_B_L A_BM_N A_DO_WRITE_P VDD VSS / RSC_IHPSG13_NOR2X2 +XB_I81 net041 B_PRE_N VDD VSS / RSC_IHPSG13_CINVX4_WN +XA_I81 net21 A_PRE_N VDD VSS / RSC_IHPSG13_CINVX4_WN +XB_BM_TIEH B_TIEH_O VDD VSS / RSC_IHPSG13_TIEH +XA_BM_TIEH A_TIEH_O VDD VSS / RSC_IHPSG13_TIEH +XA_I89 A_DCLK_B_L A_DCLK_B_R / RSC_IHPSG13_MET3RES +XA_I88 A_DCLK_L A_DCLK_R / RSC_IHPSG13_MET3RES +XA_I87 A_WCLK_L A_WCLK_R / RSC_IHPSG13_MET3RES +XA_I91 A_RCLK_B_L A_RCLK_B_R / RSC_IHPSG13_MET3RES +XB_I87 B_WCLK_L B_WCLK_R / RSC_IHPSG13_MET3RES +XB_I88 B_DCLK_L B_DCLK_R / RSC_IHPSG13_MET3RES +XB_I89 B_DCLK_B_L B_DCLK_B_R / RSC_IHPSG13_MET3RES +XB_I90 B_WCLK_B_L B_WCLK_B_R / RSC_IHPSG13_MET3RES +XB_R2 B_RCLK_L B_RCLK_R / RSC_IHPSG13_MET3RES +XB_I91 B_RCLK_B_L B_RCLK_B_R / RSC_IHPSG13_MET3RES +XA_R2 A_RCLK_L A_RCLK_R / RSC_IHPSG13_MET3RES +XA_I90 A_WCLK_B_L A_WCLK_B_R / RSC_IHPSG13_MET3RES +XAB_BLMUX A_BLC<3> A_BLC<2> A_BLC<1> A_BLC<0> A_BLC_SEL A_BLT<3> A_BLT<2> ++ A_BLT<1> A_BLT<0> A_BLT_SEL A_PRE_N A_ADDR_DEC<3> A_ADDR_DEC<2> ++ A_ADDR_DEC<1> A_ADDR_DEC<0> A_WR_ONE A_WR_ZERO B_BLC<3> B_BLC<2> B_BLC<1> ++ B_BLC<0> B_BLC_SEL B_BLT<3> B_BLT<2> B_BLT<1> B_BLT<0> B_BLT_SEL B_PRE_N ++ B_ADDR_DEC<3> B_ADDR_DEC<2> B_ADDR_DEC<1> B_ADDR_DEC<0> B_WR_ONE B_WR_ZERO ++ VDD VSS / RM_IHPSG13_256x8_c2_2P_BLDRV +XB_ISENSE B_SAE B_BLC_SEL B_BLT_SEL net039 net040 VDD VSS / ++ RSC_IHPSG13_DFPQD_MSAFFX2 +XA_ISENSE A_SAE A_BLC_SEL A_BLT_SEL net19 net20 VDD VSS / ++ RSC_IHPSG13_DFPQD_MSAFFX2 +XB_I78 B_RCLK_B_L B_SAE VDD VSS / RSC_IHPSG13_CBUFX2 +XA_I78 A_RCLK_B_L A_SAE VDD VSS / RSC_IHPSG13_CBUFX2 +XB_I83 B_BM_R B_BM_N VDD VSS / RSC_IHPSG13_INVX2 +XB_I49 B_DI_R B_DI_N VDD VSS / RSC_IHPSG13_INVX2 +XA_I83 A_BM_R A_BM_N VDD VSS / RSC_IHPSG13_INVX2 +XA_I49 A_DI_R A_DI_N VDD VSS / RSC_IHPSG13_INVX2 +XB_I51 net039 B_DR_O VDD VSS / RSC_IHPSG13_INVX4 +XA_I51 net19 A_DR_O VDD VSS / RSC_IHPSG13_INVX4 +XA_I69 A_DCLK_L A_DCLK_B_L VDD VSS / RSC_IHPSG13_CINVX2 +XA_I50 A_WCLK_L A_WCLK_B_L VDD VSS / RSC_IHPSG13_CINVX2 +XA_EBUF A_RCLK_L A_RCLK_B_L VDD VSS / RSC_IHPSG13_CINVX2 +XB_EBUF B_RCLK_L B_RCLK_B_L VDD VSS / RSC_IHPSG13_CINVX2 +XB_I50 B_WCLK_L B_WCLK_B_L VDD VSS / RSC_IHPSG13_CINVX2 +XB_I69 B_DCLK_L B_DCLK_B_L VDD VSS / RSC_IHPSG13_CINVX2 +.ENDS +.SUBCKT RM_IHPSG13_256x8_c2_2P_COLDRV13_FILL4C2 VDD VSS +XI0<2> VDD VSS / RSC_IHPSG13_FILLCAP4 +XI0<1> VDD VSS / RSC_IHPSG13_FILLCAP4 +.ENDS + + +.SUBCKT RM_IHPSG13_256x8_c2_2P_ROWDEC7 ADDR_N_I<6> ADDR_N_I<5> ADDR_N_I<4> ADDR_N_I<3> ++ ADDR_N_I<2> ADDR_N_I<1> ADDR_N_I<0> CS_I ECLK_I WL_O<127> WL_O<126> ++ WL_O<125> WL_O<124> WL_O<123> WL_O<122> WL_O<121> WL_O<120> WL_O<119> ++ WL_O<118> WL_O<117> WL_O<116> WL_O<115> WL_O<114> WL_O<113> WL_O<112> ++ WL_O<111> WL_O<110> WL_O<109> WL_O<108> WL_O<107> WL_O<106> WL_O<105> ++ WL_O<104> WL_O<103> WL_O<102> WL_O<101> WL_O<100> WL_O<99> WL_O<98> WL_O<97> ++ WL_O<96> WL_O<95> WL_O<94> WL_O<93> WL_O<92> WL_O<91> WL_O<90> WL_O<89> ++ WL_O<88> WL_O<87> WL_O<86> WL_O<85> WL_O<84> WL_O<83> WL_O<82> WL_O<81> ++ WL_O<80> WL_O<79> WL_O<78> WL_O<77> WL_O<76> WL_O<75> WL_O<74> WL_O<73> ++ WL_O<72> WL_O<71> WL_O<70> WL_O<69> WL_O<68> WL_O<67> WL_O<66> WL_O<65> ++ WL_O<64> WL_O<63> WL_O<62> WL_O<61> WL_O<60> WL_O<59> WL_O<58> WL_O<57> ++ WL_O<56> WL_O<55> WL_O<54> WL_O<53> WL_O<52> WL_O<51> WL_O<50> WL_O<49> ++ WL_O<48> WL_O<47> WL_O<46> WL_O<45> WL_O<44> WL_O<43> WL_O<42> WL_O<41> ++ WL_O<40> WL_O<39> WL_O<38> WL_O<37> WL_O<36> WL_O<35> WL_O<34> WL_O<33> ++ WL_O<32> WL_O<31> WL_O<30> WL_O<29> WL_O<28> WL_O<27> WL_O<26> WL_O<25> ++ WL_O<24> WL_O<23> WL_O<22> WL_O<21> WL_O<20> WL_O<19> WL_O<18> WL_O<17> ++ WL_O<16> WL_O<15> WL_O<14> WL_O<13> WL_O<12> WL_O<11> WL_O<10> WL_O<9> ++ WL_O<8> WL_O<7> WL_O<6> WL_O<5> WL_O<4> WL_O<3> WL_O<2> WL_O<1> WL_O<0> ++ VDD VSS +XSEL<7> ADDR_N_I<3> ADDR_N_I<2> ADDR_N_I<1> ADDR_N_I<0> CS00<7> ECLK_H<7> ++ ECLK_H<8> ECLK_B<7> ECLK_B<8> WL_O<127> WL_O<126> WL_O<125> WL_O<124> ++ WL_O<123> WL_O<122> WL_O<121> WL_O<120> WL_O<119> WL_O<118> WL_O<117> ++ WL_O<116> WL_O<115> WL_O<114> WL_O<113> WL_O<112> VDD VSS / ++ RM_IHPSG13_256x8_c2_2P_DEC04 +XSEL<6> ADDR_N_I<3> ADDR_N_I<2> ADDR_N_I<1> ADDR_N_I<0> CS00<6> ECLK_H<6> ++ ECLK_H<7> ECLK_B<6> ECLK_B<7> WL_O<111> WL_O<110> WL_O<109> WL_O<108> ++ WL_O<107> WL_O<106> WL_O<105> WL_O<104> WL_O<103> WL_O<102> WL_O<101> ++ WL_O<100> WL_O<99> WL_O<98> WL_O<97> WL_O<96> VDD VSS / ++ RM_IHPSG13_256x8_c2_2P_DEC04 +XSEL<5> ADDR_N_I<3> ADDR_N_I<2> ADDR_N_I<1> ADDR_N_I<0> CS00<5> ECLK_H<5> ++ ECLK_H<6> ECLK_B<5> ECLK_B<6> WL_O<95> WL_O<94> WL_O<93> WL_O<92> WL_O<91> ++ WL_O<90> WL_O<89> WL_O<88> WL_O<87> WL_O<86> WL_O<85> WL_O<84> WL_O<83> ++ WL_O<82> WL_O<81> WL_O<80> VDD VSS / RM_IHPSG13_256x8_c2_2P_DEC04 +XSEL<4> ADDR_N_I<3> ADDR_N_I<2> ADDR_N_I<1> ADDR_N_I<0> CS00<4> ECLK_H<4> ++ ECLK_H<5> ECLK_B<4> ECLK_B<5> WL_O<79> WL_O<78> WL_O<77> WL_O<76> WL_O<75> ++ WL_O<74> WL_O<73> WL_O<72> WL_O<71> WL_O<70> WL_O<69> WL_O<68> WL_O<67> ++ WL_O<66> WL_O<65> WL_O<64> VDD VSS / RM_IHPSG13_256x8_c2_2P_DEC04 +XSEL<3> ADDR_N_I<3> ADDR_N_I<2> ADDR_N_I<1> ADDR_N_I<0> CS00<3> ECLK_H<3> ++ ECLK_H<4> ECLK_B<3> ECLK_B<4> WL_O<63> WL_O<62> WL_O<61> WL_O<60> WL_O<59> ++ WL_O<58> WL_O<57> WL_O<56> WL_O<55> WL_O<54> WL_O<53> WL_O<52> WL_O<51> ++ WL_O<50> WL_O<49> WL_O<48> VDD VSS / RM_IHPSG13_256x8_c2_2P_DEC04 +XSEL<2> ADDR_N_I<3> ADDR_N_I<2> ADDR_N_I<1> ADDR_N_I<0> CS00<2> ECLK_H<2> ++ ECLK_H<3> ECLK_B<2> ECLK_B<3> WL_O<47> WL_O<46> WL_O<45> WL_O<44> WL_O<43> ++ WL_O<42> WL_O<41> WL_O<40> WL_O<39> WL_O<38> WL_O<37> WL_O<36> WL_O<35> ++ WL_O<34> WL_O<33> WL_O<32> VDD VSS / RM_IHPSG13_256x8_c2_2P_DEC04 +XSEL<1> ADDR_N_I<3> ADDR_N_I<2> ADDR_N_I<1> ADDR_N_I<0> CS00<1> ECLK_H<1> ++ ECLK_H<2> ECLK_B<1> ECLK_B<2> WL_O<31> WL_O<30> WL_O<29> WL_O<28> WL_O<27> ++ WL_O<26> WL_O<25> WL_O<24> WL_O<23> WL_O<22> WL_O<21> WL_O<20> WL_O<19> ++ WL_O<18> WL_O<17> WL_O<16> VDD VSS / RM_IHPSG13_256x8_c2_2P_DEC04 +XSEL<0> ADDR_N_I<3> ADDR_N_I<2> ADDR_N_I<1> ADDR_N_I<0> CS00<0> ECLK_I ++ ECLK_H<1> ECLK_B<0> ECLK_B<1> WL_O<15> WL_O<14> WL_O<13> WL_O<12> WL_O<11> ++ WL_O<10> WL_O<9> WL_O<8> WL_O<7> WL_O<6> WL_O<5> WL_O<4> WL_O<3> WL_O<2> ++ WL_O<1> WL_O<0> VDD VSS / RM_IHPSG13_256x8_c2_2P_DEC04 +XDEC11<1> ADDR_N_I<5> ADDR_N_I<4> CS04<1> CS00<7> VDD VSS / ++ RM_IHPSG13_256x8_c2_2P_DEC03 +XDEC11<0> ADDR_N_I<5> ADDR_N_I<4> CS04<0> CS00<3> VDD VSS / ++ RM_IHPSG13_256x8_c2_2P_DEC03 +XDEC01<2> ADDR_N_I<7> ADDR_N_I<6> CS_I CS04<1> VDD VSS / ++ RM_IHPSG13_256x8_c2_2P_DEC01 +XDEC01<1> ADDR_N_I<5> ADDR_N_I<4> CS04<1> CS00<5> VDD VSS / ++ RM_IHPSG13_256x8_c2_2P_DEC01 +XDEC01<0> ADDR_N_I<5> ADDR_N_I<4> CS04<0> CS00<1> VDD VSS / ++ RM_IHPSG13_256x8_c2_2P_DEC01 +XL2<66> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<65> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<64> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<63> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<62> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<61> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<60> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<59> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<58> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<57> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<56> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<55> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<54> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<53> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<52> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<51> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<50> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<49> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<48> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<47> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<46> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<45> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<44> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<43> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<42> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<41> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<40> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<39> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<38> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<37> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<36> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<35> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<34> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<33> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<32> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<31> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<30> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<29> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<28> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<27> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<26> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<25> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<24> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<23> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<22> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<21> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<20> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<19> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<18> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<17> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<16> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<15> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<14> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<13> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<12> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<11> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<10> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<9> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<8> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<7> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<6> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<5> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<4> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<3> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<2> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<1> VDD VSS / RSC_IHPSG13_FILLCAP8 +XDEC10<1> ADDR_N_I<5> ADDR_N_I<4> CS04<1> CS00<6> VDD VSS / ++ RM_IHPSG13_256x8_c2_2P_DEC02 +XDEC10<0> ADDR_N_I<5> ADDR_N_I<4> CS04<0> CS00<2> VDD VSS / ++ RM_IHPSG13_256x8_c2_2P_DEC02 +XDEC00<2> ADDR_N_I<7> ADDR_N_I<6> CS_I CS04<0> VDD VSS / ++ RM_IHPSG13_256x8_c2_2P_DEC00 +XDEC00<1> ADDR_N_I<5> ADDR_N_I<4> CS04<1> CS00<4> VDD VSS / ++ RM_IHPSG13_256x8_c2_2P_DEC00 +XDEC00<0> ADDR_N_I<5> ADDR_N_I<4> CS04<0> CS00<0> VDD VSS / ++ RM_IHPSG13_256x8_c2_2P_DEC00 +XI0 ADDR_N_I<7> VDD VSS / RSC_IHPSG13_TIEL +.ENDS +.SUBCKT RM_IHPSG13_256x8_c2_2P_ROWREG7 ACLK_N_I ADDR_I<6> ADDR_I<5> ADDR_I<4> ADDR_I<3> ++ ADDR_I<2> ADDR_I<1> ADDR_I<0> ADDR_N_O<6> ADDR_N_O<5> ADDR_N_O<4> ++ ADDR_N_O<3> ADDR_N_O<2> ADDR_N_O<1> ADDR_N_O<0> BIST_ADDR_I<6> ++ BIST_ADDR_I<5> BIST_ADDR_I<4> BIST_ADDR_I<3> BIST_ADDR_I<2> BIST_ADDR_I<1> ++ BIST_ADDR_I<0> BIST_EN_I VDD VSS +XINV<6> q_int<6> qn_int<6> VDD VSS / RSC_IHPSG13_CINVX2 +XINV<5> q_int<5> qn_int<5> VDD VSS / RSC_IHPSG13_CINVX2 +XINV<4> q_int<4> qn_int<4> VDD VSS / RSC_IHPSG13_CINVX2 +XINV<3> q_int<3> qn_int<3> VDD VSS / RSC_IHPSG13_CINVX2 +XINV<2> q_int<2> qn_int<2> VDD VSS / RSC_IHPSG13_CINVX2 +XINV<1> q_int<1> qn_int<1> VDD VSS / RSC_IHPSG13_CINVX2 +XINV<0> q_int<0> qn_int<0> VDD VSS / RSC_IHPSG13_CINVX2 +XDRV<6> qn_int<6> ADDR_N_O<6> VDD VSS / RSC_IHPSG13_CINVX8 +XDRV<5> qn_int<5> ADDR_N_O<5> VDD VSS / RSC_IHPSG13_CINVX8 +XDRV<4> qn_int<4> ADDR_N_O<4> VDD VSS / RSC_IHPSG13_CINVX8 +XDRV<3> qn_int<3> ADDR_N_O<3> VDD VSS / RSC_IHPSG13_CINVX8 +XDRV<2> qn_int<2> ADDR_N_O<2> VDD VSS / RSC_IHPSG13_CINVX8 +XDRV<1> qn_int<1> ADDR_N_O<1> VDD VSS / RSC_IHPSG13_CINVX8 +XDRV<0> qn_int<0> ADDR_N_O<0> VDD VSS / RSC_IHPSG13_CINVX8 +XDFF<6> BIST_EN_I BIST_ADDR_I<6> ACLK_N_I ADDR_I<6> q_int<6> net2<0> VDD ++ VSS / RSC_IHPSG13_DFNQMX2IX1 +XDFF<5> BIST_EN_I BIST_ADDR_I<5> ACLK_N_I ADDR_I<5> q_int<5> net2<1> VDD ++ VSS / RSC_IHPSG13_DFNQMX2IX1 +XDFF<4> BIST_EN_I BIST_ADDR_I<4> ACLK_N_I ADDR_I<4> q_int<4> net2<2> VDD ++ VSS / RSC_IHPSG13_DFNQMX2IX1 +XDFF<3> BIST_EN_I BIST_ADDR_I<3> ACLK_N_I ADDR_I<3> q_int<3> net2<3> VDD ++ VSS / RSC_IHPSG13_DFNQMX2IX1 +XDFF<2> BIST_EN_I BIST_ADDR_I<2> ACLK_N_I ADDR_I<2> q_int<2> net2<4> VDD ++ VSS / RSC_IHPSG13_DFNQMX2IX1 +XDFF<1> BIST_EN_I BIST_ADDR_I<1> ACLK_N_I ADDR_I<1> q_int<1> net2<5> VDD ++ VSS / RSC_IHPSG13_DFNQMX2IX1 +XDFF<0> BIST_EN_I BIST_ADDR_I<0> ACLK_N_I ADDR_I<0> q_int<0> net2<6> VDD ++ VSS / RSC_IHPSG13_DFNQMX2IX1 +XI11<7> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI11<6> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI11<5> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI11<4> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI11<3> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI11<2> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI11<1> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI11<0> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI12<1> VDD VSS / RSC_IHPSG13_FILLCAP4 +XI12<0> VDD VSS / RSC_IHPSG13_FILLCAP4 +.ENDS + +.SUBCKT RM_IHPSG13_256x8_c2_2P_ROWDEC4 ADDR_N_I<3> ADDR_N_I<2> ADDR_N_I<1> ADDR_N_I<0> ++ CS_I ECLK_I WL_O<15> WL_O<14> WL_O<13> WL_O<12> WL_O<11> WL_O<10> WL_O<9> ++ WL_O<8> WL_O<7> WL_O<6> WL_O<5> WL_O<4> WL_O<3> WL_O<2> WL_O<1> WL_O<0> ++ VDD VSS +XL2<12> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<11> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<10> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<9> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<8> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<7> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<6> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<5> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<4> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<3> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<2> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<1> VDD VSS / RSC_IHPSG13_FILLCAP8 +XSEL ADDR_N_I<3> ADDR_N_I<2> ADDR_N_I<1> ADDR_N_I<0> CS_I ECLK_I ECLK_H<1> ++ ECLK_B<0> ECLK_B<1> WL_O<15> WL_O<14> WL_O<13> WL_O<12> WL_O<11> WL_O<10> ++ WL_O<9> WL_O<8> WL_O<7> WL_O<6> WL_O<5> WL_O<4> WL_O<3> WL_O<2> WL_O<1> ++ WL_O<0> VDD VSS / RM_IHPSG13_256x8_c2_2P_DEC04 +.ENDS +.SUBCKT RM_IHPSG13_256x8_c2_2P_ROWREG4 ACLK_N_I ADDR_I<3> ADDR_I<2> ADDR_I<1> ADDR_I<0> ++ ADDR_N_O<3> ADDR_N_O<2> ADDR_N_O<1> ADDR_N_O<0> BIST_ADDR_I<3> ++ BIST_ADDR_I<2> BIST_ADDR_I<1> BIST_ADDR_I<0> BIST_EN_I VDD VSS +XINV<3> q_int<3> qn_int<3> VDD VSS / RSC_IHPSG13_CINVX2 +XINV<2> q_int<2> qn_int<2> VDD VSS / RSC_IHPSG13_CINVX2 +XINV<1> q_int<1> qn_int<1> VDD VSS / RSC_IHPSG13_CINVX2 +XINV<0> q_int<0> qn_int<0> VDD VSS / RSC_IHPSG13_CINVX2 +XDRV<3> qn_int<3> ADDR_N_O<3> VDD VSS / RSC_IHPSG13_CINVX8 +XDRV<2> qn_int<2> ADDR_N_O<2> VDD VSS / RSC_IHPSG13_CINVX8 +XDRV<1> qn_int<1> ADDR_N_O<1> VDD VSS / RSC_IHPSG13_CINVX8 +XDRV<0> qn_int<0> ADDR_N_O<0> VDD VSS / RSC_IHPSG13_CINVX8 +XDFF<3> BIST_EN_I BIST_ADDR_I<3> ACLK_N_I ADDR_I<3> q_int<3> net7<0> VDD ++ VSS / RSC_IHPSG13_DFNQMX2IX1 +XDFF<2> BIST_EN_I BIST_ADDR_I<2> ACLK_N_I ADDR_I<2> q_int<2> net7<1> VDD ++ VSS / RSC_IHPSG13_DFNQMX2IX1 +XDFF<1> BIST_EN_I BIST_ADDR_I<1> ACLK_N_I ADDR_I<1> q_int<1> net7<2> VDD ++ VSS / RSC_IHPSG13_DFNQMX2IX1 +XDFF<0> BIST_EN_I BIST_ADDR_I<0> ACLK_N_I ADDR_I<0> q_int<0> net7<3> VDD ++ VSS / RSC_IHPSG13_DFNQMX2IX1 +XI11<20> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI11<19> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI11<18> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI11<17> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI11<16> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI11<15> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI11<14> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI11<13> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI11<12> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI11<11> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI11<10> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI11<9> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI11<8> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI11<7> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI11<6> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI11<5> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI11<4> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI11<3> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI11<2> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI11<1> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI12<4> VDD VSS / RSC_IHPSG13_FILLCAP4 +XI12<3> VDD VSS / RSC_IHPSG13_FILLCAP4 +XI12<2> VDD VSS / RSC_IHPSG13_FILLCAP4 +XI12<1> VDD VSS / RSC_IHPSG13_FILLCAP4 +XI12<0> VDD VSS / RSC_IHPSG13_FILLCAP4 +.ENDS + + +.SUBCKT RM_IHPSG13_256x8_c2_1P_BITKIT_TAP BLC BLT NW PW VDD VSS +.ENDS +.SUBCKT RM_IHPSG13_256x8_c2_1P_BITKIT_16x2_TAP A_BLC<1> A_BLC<0> A_BLT<1> A_BLT<0> ++ VDD_CORE VSS +XITAP<1> A_BLC<1> A_BLT<1> VDD_CORE VSS VDD_CORE VSS ++ / RM_IHPSG13_256x8_c2_1P_BITKIT_TAP +XITAP<0> A_BLC<0> A_BLT<0> VDD_CORE VSS VDD_CORE VSS ++ / RM_IHPSG13_256x8_c2_1P_BITKIT_TAP +XIEDGEBP_COL1<1> BLC<1> BLT<1> VDD_CORE VSS VDD_CORE ++ VSS / RM_IHPSG13_256x8_c2_1P_BITKIT_EDGE_TB +XIEDGEBP_COL1<0> BLC<1> BLT<1> VDD_CORE VSS VDD_CORE ++ VSS / RM_IHPSG13_256x8_c2_1P_BITKIT_EDGE_TB +XIEDGEBP_COL2<1> BLC<0> BLT<0> VDD_CORE VSS VDD_CORE ++ VSS / RM_IHPSG13_256x8_c2_1P_BITKIT_EDGE_TB +XIEDGEBP_COL2<0> BLC<0> BLT<0> VDD_CORE VSS VDD_CORE ++ VSS / RM_IHPSG13_256x8_c2_1P_BITKIT_EDGE_TB +.ENDS +.SUBCKT RM_IHPSG13_256x8_c2_1P_BITKIT_16x2_TAP_LR VDD_CORE VSS +XCORNER<1> VDD_CORE VSS VDD_CORE VSS / ++ RM_IHPSG13_256x8_c2_1P_BITKIT_CORNER +XCORNER<0> VDD_CORE VSS VDD_CORE VSS / ++ RM_IHPSG13_256x8_c2_1P_BITKIT_CORNER +XTAP_BORDER VDD_CORE VSS VDD_CORE VSS / ++ RM_IHPSG13_256x8_c2_1P_BITKIT_TAP_LR +.ENDS +.SUBCKT RM_IHPSG13_256x8_c2_1P_DEC03 ADDR<1> ADDR<0> CS CS_OUT VDD VSS +XDECINV net1 CS_OUT VDD VSS / RSC_IHPSG13_INVX4 +XI0 VDD VSS / RSC_IHPSG13_FILLCAP4 +XDEC ADDR<1> ADDR<0> CS net1 VDD VSS / RSC_IHPSG13_NAND3X2 +.ENDS +.SUBCKT RM_IHPSG13_256x8_c2_1P_DEC02 ADDR<1> ADDR<0> CS CS_OUT VDD VSS +XDECINV net1 CS_OUT VDD VSS / RSC_IHPSG13_INVX4 +XDEC ADDR<1> NADDR<0> CS net1 VDD VSS / RSC_IHPSG13_NAND3X2 +XI2 VDD VSS / RSC_IHPSG13_FILLCAP4 +XADDRINV ADDR<0> NADDR<0> VDD VSS / RSC_IHPSG13_INVX2 +.ENDS +.SUBCKT RM_IHPSG13_256x8_c2_1P_ROWDEC8 ADDR_N_I<7> ADDR_N_I<6> ADDR_N_I<5> ADDR_N_I<4> ++ ADDR_N_I<3> ADDR_N_I<2> ADDR_N_I<1> ADDR_N_I<0> CS_I ECLK_I WL_O<255> ++ WL_O<254> WL_O<253> WL_O<252> WL_O<251> WL_O<250> WL_O<249> WL_O<248> ++ WL_O<247> WL_O<246> WL_O<245> WL_O<244> WL_O<243> WL_O<242> WL_O<241> ++ WL_O<240> WL_O<239> WL_O<238> WL_O<237> WL_O<236> WL_O<235> WL_O<234> ++ WL_O<233> WL_O<232> WL_O<231> WL_O<230> WL_O<229> WL_O<228> WL_O<227> ++ WL_O<226> WL_O<225> WL_O<224> WL_O<223> WL_O<222> WL_O<221> WL_O<220> ++ WL_O<219> WL_O<218> WL_O<217> WL_O<216> WL_O<215> WL_O<214> WL_O<213> ++ WL_O<212> WL_O<211> WL_O<210> WL_O<209> WL_O<208> WL_O<207> WL_O<206> ++ WL_O<205> WL_O<204> WL_O<203> WL_O<202> WL_O<201> WL_O<200> WL_O<199> ++ WL_O<198> WL_O<197> WL_O<196> WL_O<195> WL_O<194> WL_O<193> WL_O<192> ++ WL_O<191> WL_O<190> WL_O<189> WL_O<188> WL_O<187> WL_O<186> WL_O<185> ++ WL_O<184> WL_O<183> WL_O<182> WL_O<181> WL_O<180> WL_O<179> WL_O<178> ++ WL_O<177> WL_O<176> WL_O<175> WL_O<174> WL_O<173> WL_O<172> WL_O<171> ++ WL_O<170> WL_O<169> WL_O<168> WL_O<167> WL_O<166> WL_O<165> WL_O<164> ++ WL_O<163> WL_O<162> WL_O<161> WL_O<160> WL_O<159> WL_O<158> WL_O<157> ++ WL_O<156> WL_O<155> WL_O<154> WL_O<153> WL_O<152> WL_O<151> WL_O<150> ++ WL_O<149> WL_O<148> WL_O<147> WL_O<146> WL_O<145> WL_O<144> WL_O<143> ++ WL_O<142> WL_O<141> WL_O<140> WL_O<139> WL_O<138> WL_O<137> WL_O<136> ++ WL_O<135> WL_O<134> WL_O<133> WL_O<132> WL_O<131> WL_O<130> WL_O<129> ++ WL_O<128> WL_O<127> WL_O<126> WL_O<125> WL_O<124> WL_O<123> WL_O<122> ++ WL_O<121> WL_O<120> WL_O<119> WL_O<118> WL_O<117> WL_O<116> WL_O<115> ++ WL_O<114> WL_O<113> WL_O<112> WL_O<111> WL_O<110> WL_O<109> WL_O<108> ++ WL_O<107> WL_O<106> WL_O<105> WL_O<104> WL_O<103> WL_O<102> WL_O<101> ++ WL_O<100> WL_O<99> WL_O<98> WL_O<97> WL_O<96> WL_O<95> WL_O<94> WL_O<93> ++ WL_O<92> WL_O<91> WL_O<90> WL_O<89> WL_O<88> WL_O<87> WL_O<86> WL_O<85> ++ WL_O<84> WL_O<83> WL_O<82> WL_O<81> WL_O<80> WL_O<79> WL_O<78> WL_O<77> ++ WL_O<76> WL_O<75> WL_O<74> WL_O<73> WL_O<72> WL_O<71> WL_O<70> WL_O<69> ++ WL_O<68> WL_O<67> WL_O<66> WL_O<65> WL_O<64> WL_O<63> WL_O<62> WL_O<61> ++ WL_O<60> WL_O<59> WL_O<58> WL_O<57> WL_O<56> WL_O<55> WL_O<54> WL_O<53> ++ WL_O<52> WL_O<51> WL_O<50> WL_O<49> WL_O<48> WL_O<47> WL_O<46> WL_O<45> ++ WL_O<44> WL_O<43> WL_O<42> WL_O<41> WL_O<40> WL_O<39> WL_O<38> WL_O<37> ++ WL_O<36> WL_O<35> WL_O<34> WL_O<33> WL_O<32> WL_O<31> WL_O<30> WL_O<29> ++ WL_O<28> WL_O<27> WL_O<26> WL_O<25> WL_O<24> WL_O<23> WL_O<22> WL_O<21> ++ WL_O<20> WL_O<19> WL_O<18> WL_O<17> WL_O<16> WL_O<15> WL_O<14> WL_O<13> ++ WL_O<12> WL_O<11> WL_O<10> WL_O<9> WL_O<8> WL_O<7> WL_O<6> WL_O<5> WL_O<4> ++ WL_O<3> WL_O<2> WL_O<1> WL_O<0> VDD VSS +XDEC11<4> ADDR_N_I<7> ADDR_N_I<6> CS_I CS04<3> VDD VSS / ++ RM_IHPSG13_256x8_c2_1P_DEC03 +XDEC11<3> ADDR_N_I<5> ADDR_N_I<4> CS04<3> CS00<15> VDD VSS / ++ RM_IHPSG13_256x8_c2_1P_DEC03 +XDEC11<2> ADDR_N_I<5> ADDR_N_I<4> CS04<2> CS00<11> VDD VSS / ++ RM_IHPSG13_256x8_c2_1P_DEC03 +XDEC11<1> ADDR_N_I<5> ADDR_N_I<4> CS04<1> CS00<7> VDD VSS / ++ RM_IHPSG13_256x8_c2_1P_DEC03 +XDEC11<0> ADDR_N_I<5> ADDR_N_I<4> CS04<0> CS00<3> VDD VSS / ++ RM_IHPSG13_256x8_c2_1P_DEC03 +XL2<88> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<87> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<86> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<85> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<84> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<83> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<82> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<81> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<80> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<79> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<78> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<77> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<76> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<75> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<74> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<73> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<72> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<71> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<70> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<69> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<68> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<67> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<66> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<65> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<64> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<63> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<62> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<61> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<60> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<59> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<58> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<57> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<56> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<55> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<54> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<53> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<52> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<51> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<50> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<49> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<48> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<47> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<46> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<45> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<44> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<43> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<42> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<41> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<40> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<39> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<38> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<37> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<36> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<35> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<34> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<33> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<32> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<31> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<30> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<29> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<28> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<27> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<26> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<25> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<24> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<23> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<22> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<21> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<20> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<19> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<18> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<17> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<16> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<15> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<14> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<13> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<12> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<11> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<10> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<9> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<8> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<7> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<6> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<5> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<4> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<3> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<2> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<1> VDD VSS / RSC_IHPSG13_FILLCAP8 +XDEC10<4> ADDR_N_I<7> ADDR_N_I<6> CS_I CS04<2> VDD VSS / ++ RM_IHPSG13_256x8_c2_1P_DEC02 +XDEC10<3> ADDR_N_I<5> ADDR_N_I<4> CS04<3> CS00<14> VDD VSS / ++ RM_IHPSG13_256x8_c2_1P_DEC02 +XDEC10<2> ADDR_N_I<5> ADDR_N_I<4> CS04<2> CS00<10> VDD VSS / ++ RM_IHPSG13_256x8_c2_1P_DEC02 +XDEC10<1> ADDR_N_I<5> ADDR_N_I<4> CS04<1> CS00<6> VDD VSS / ++ RM_IHPSG13_256x8_c2_1P_DEC02 +XDEC10<0> ADDR_N_I<5> ADDR_N_I<4> CS04<0> CS00<2> VDD VSS / ++ RM_IHPSG13_256x8_c2_1P_DEC02 +XDEC00<4> ADDR_N_I<7> ADDR_N_I<6> CS_I CS04<0> VDD VSS / ++ RM_IHPSG13_256x8_c2_1P_DEC00 +XDEC00<3> ADDR_N_I<5> ADDR_N_I<4> CS04<3> CS00<12> VDD VSS / ++ RM_IHPSG13_256x8_c2_1P_DEC00 +XDEC00<2> ADDR_N_I<5> ADDR_N_I<4> CS04<2> CS00<8> VDD VSS / ++ RM_IHPSG13_256x8_c2_1P_DEC00 +XDEC00<1> ADDR_N_I<5> ADDR_N_I<4> CS04<1> CS00<4> VDD VSS / ++ RM_IHPSG13_256x8_c2_1P_DEC00 +XDEC00<0> ADDR_N_I<5> ADDR_N_I<4> CS04<0> CS00<0> VDD VSS / ++ RM_IHPSG13_256x8_c2_1P_DEC00 +XSEL<15> ADDR_N_I<3> ADDR_N_I<2> ADDR_N_I<1> ADDR_N_I<0> CS00<15> ECLK_H<15> ++ ECLK_H<16> ECLK_B<15> ECLK_B<16> WL_O<255> WL_O<254> WL_O<253> WL_O<252> ++ WL_O<251> WL_O<250> WL_O<249> WL_O<248> WL_O<247> WL_O<246> WL_O<245> ++ WL_O<244> WL_O<243> WL_O<242> WL_O<241> WL_O<240> VDD VSS / ++ RM_IHPSG13_256x8_c2_1P_DEC04 +XSEL<14> ADDR_N_I<3> ADDR_N_I<2> ADDR_N_I<1> ADDR_N_I<0> CS00<14> ECLK_H<14> ++ ECLK_H<15> ECLK_B<14> ECLK_B<15> WL_O<239> WL_O<238> WL_O<237> WL_O<236> ++ WL_O<235> WL_O<234> WL_O<233> WL_O<232> WL_O<231> WL_O<230> WL_O<229> ++ WL_O<228> WL_O<227> WL_O<226> WL_O<225> WL_O<224> VDD VSS / ++ RM_IHPSG13_256x8_c2_1P_DEC04 +XSEL<13> ADDR_N_I<3> ADDR_N_I<2> ADDR_N_I<1> ADDR_N_I<0> CS00<13> ECLK_H<13> ++ ECLK_H<14> ECLK_B<13> ECLK_B<14> WL_O<223> WL_O<222> WL_O<221> WL_O<220> ++ WL_O<219> WL_O<218> WL_O<217> WL_O<216> WL_O<215> WL_O<214> WL_O<213> ++ WL_O<212> WL_O<211> WL_O<210> WL_O<209> WL_O<208> VDD VSS / ++ RM_IHPSG13_256x8_c2_1P_DEC04 +XSEL<12> ADDR_N_I<3> ADDR_N_I<2> ADDR_N_I<1> ADDR_N_I<0> CS00<12> ECLK_H<12> ++ ECLK_H<13> ECLK_B<12> ECLK_B<13> WL_O<207> WL_O<206> WL_O<205> WL_O<204> ++ WL_O<203> WL_O<202> WL_O<201> WL_O<200> WL_O<199> WL_O<198> WL_O<197> ++ WL_O<196> WL_O<195> WL_O<194> WL_O<193> WL_O<192> VDD VSS / ++ RM_IHPSG13_256x8_c2_1P_DEC04 +XSEL<11> ADDR_N_I<3> ADDR_N_I<2> ADDR_N_I<1> ADDR_N_I<0> CS00<11> ECLK_H<11> ++ ECLK_H<12> ECLK_B<11> ECLK_B<12> WL_O<191> WL_O<190> WL_O<189> WL_O<188> ++ WL_O<187> WL_O<186> WL_O<185> WL_O<184> WL_O<183> WL_O<182> WL_O<181> ++ WL_O<180> WL_O<179> WL_O<178> WL_O<177> WL_O<176> VDD VSS / ++ RM_IHPSG13_256x8_c2_1P_DEC04 +XSEL<10> ADDR_N_I<3> ADDR_N_I<2> ADDR_N_I<1> ADDR_N_I<0> CS00<10> ECLK_H<10> ++ ECLK_H<11> ECLK_B<10> ECLK_B<11> WL_O<175> WL_O<174> WL_O<173> WL_O<172> ++ WL_O<171> WL_O<170> WL_O<169> WL_O<168> WL_O<167> WL_O<166> WL_O<165> ++ WL_O<164> WL_O<163> WL_O<162> WL_O<161> WL_O<160> VDD VSS / ++ RM_IHPSG13_256x8_c2_1P_DEC04 +XSEL<9> ADDR_N_I<3> ADDR_N_I<2> ADDR_N_I<1> ADDR_N_I<0> CS00<9> ECLK_H<9> ++ ECLK_H<10> ECLK_B<9> ECLK_B<10> WL_O<159> WL_O<158> WL_O<157> WL_O<156> ++ WL_O<155> WL_O<154> WL_O<153> WL_O<152> WL_O<151> WL_O<150> WL_O<149> ++ WL_O<148> WL_O<147> WL_O<146> WL_O<145> WL_O<144> VDD VSS / ++ RM_IHPSG13_256x8_c2_1P_DEC04 +XSEL<8> ADDR_N_I<3> ADDR_N_I<2> ADDR_N_I<1> ADDR_N_I<0> CS00<8> ECLK_H<8> ++ ECLK_H<9> ECLK_B<8> ECLK_B<9> WL_O<143> WL_O<142> WL_O<141> WL_O<140> ++ WL_O<139> WL_O<138> WL_O<137> WL_O<136> WL_O<135> WL_O<134> WL_O<133> ++ WL_O<132> WL_O<131> WL_O<130> WL_O<129> WL_O<128> VDD VSS / ++ RM_IHPSG13_256x8_c2_1P_DEC04 +XSEL<7> ADDR_N_I<3> ADDR_N_I<2> ADDR_N_I<1> ADDR_N_I<0> CS00<7> ECLK_H<7> ++ ECLK_H<8> ECLK_B<7> ECLK_B<8> WL_O<127> WL_O<126> WL_O<125> WL_O<124> ++ WL_O<123> WL_O<122> WL_O<121> WL_O<120> WL_O<119> WL_O<118> WL_O<117> ++ WL_O<116> WL_O<115> WL_O<114> WL_O<113> WL_O<112> VDD VSS / ++ RM_IHPSG13_256x8_c2_1P_DEC04 +XSEL<6> ADDR_N_I<3> ADDR_N_I<2> ADDR_N_I<1> ADDR_N_I<0> CS00<6> ECLK_H<6> ++ ECLK_H<7> ECLK_B<6> ECLK_B<7> WL_O<111> WL_O<110> WL_O<109> WL_O<108> ++ WL_O<107> WL_O<106> WL_O<105> WL_O<104> WL_O<103> WL_O<102> WL_O<101> ++ WL_O<100> WL_O<99> WL_O<98> WL_O<97> WL_O<96> VDD VSS / ++ RM_IHPSG13_256x8_c2_1P_DEC04 +XSEL<5> ADDR_N_I<3> ADDR_N_I<2> ADDR_N_I<1> ADDR_N_I<0> CS00<5> ECLK_H<5> ++ ECLK_H<6> ECLK_B<5> ECLK_B<6> WL_O<95> WL_O<94> WL_O<93> WL_O<92> WL_O<91> ++ WL_O<90> WL_O<89> WL_O<88> WL_O<87> WL_O<86> WL_O<85> WL_O<84> WL_O<83> ++ WL_O<82> WL_O<81> WL_O<80> VDD VSS / RM_IHPSG13_256x8_c2_1P_DEC04 +XSEL<4> ADDR_N_I<3> ADDR_N_I<2> ADDR_N_I<1> ADDR_N_I<0> CS00<4> ECLK_H<4> ++ ECLK_H<5> ECLK_B<4> ECLK_B<5> WL_O<79> WL_O<78> WL_O<77> WL_O<76> WL_O<75> ++ WL_O<74> WL_O<73> WL_O<72> WL_O<71> WL_O<70> WL_O<69> WL_O<68> WL_O<67> ++ WL_O<66> WL_O<65> WL_O<64> VDD VSS / RM_IHPSG13_256x8_c2_1P_DEC04 +XSEL<3> ADDR_N_I<3> ADDR_N_I<2> ADDR_N_I<1> ADDR_N_I<0> CS00<3> ECLK_H<3> ++ ECLK_H<4> ECLK_B<3> ECLK_B<4> WL_O<63> WL_O<62> WL_O<61> WL_O<60> WL_O<59> ++ WL_O<58> WL_O<57> WL_O<56> WL_O<55> WL_O<54> WL_O<53> WL_O<52> WL_O<51> ++ WL_O<50> WL_O<49> WL_O<48> VDD VSS / RM_IHPSG13_256x8_c2_1P_DEC04 +XSEL<2> ADDR_N_I<3> ADDR_N_I<2> ADDR_N_I<1> ADDR_N_I<0> CS00<2> ECLK_H<2> ++ ECLK_H<3> ECLK_B<2> ECLK_B<3> WL_O<47> WL_O<46> WL_O<45> WL_O<44> WL_O<43> ++ WL_O<42> WL_O<41> WL_O<40> WL_O<39> WL_O<38> WL_O<37> WL_O<36> WL_O<35> ++ WL_O<34> WL_O<33> WL_O<32> VDD VSS / RM_IHPSG13_256x8_c2_1P_DEC04 +XSEL<1> ADDR_N_I<3> ADDR_N_I<2> ADDR_N_I<1> ADDR_N_I<0> CS00<1> ECLK_H<1> ++ ECLK_H<2> ECLK_B<1> ECLK_B<2> WL_O<31> WL_O<30> WL_O<29> WL_O<28> WL_O<27> ++ WL_O<26> WL_O<25> WL_O<24> WL_O<23> WL_O<22> WL_O<21> WL_O<20> WL_O<19> ++ WL_O<18> WL_O<17> WL_O<16> VDD VSS / RM_IHPSG13_256x8_c2_1P_DEC04 +XSEL<0> ADDR_N_I<3> ADDR_N_I<2> ADDR_N_I<1> ADDR_N_I<0> CS00<0> ECLK_I ++ ECLK_H<1> ECLK_B<0> ECLK_B<1> WL_O<15> WL_O<14> WL_O<13> WL_O<12> WL_O<11> ++ WL_O<10> WL_O<9> WL_O<8> WL_O<7> WL_O<6> WL_O<5> WL_O<4> WL_O<3> WL_O<2> ++ WL_O<1> WL_O<0> VDD VSS / RM_IHPSG13_256x8_c2_1P_DEC04 +XDEC01<4> ADDR_N_I<7> ADDR_N_I<6> CS_I CS04<1> VDD VSS / ++ RM_IHPSG13_256x8_c2_1P_DEC01 +XDEC01<3> ADDR_N_I<5> ADDR_N_I<4> CS04<3> CS00<13> VDD VSS / ++ RM_IHPSG13_256x8_c2_1P_DEC01 +XDEC01<2> ADDR_N_I<5> ADDR_N_I<4> CS04<2> CS00<9> VDD VSS / ++ RM_IHPSG13_256x8_c2_1P_DEC01 +XDEC01<1> ADDR_N_I<5> ADDR_N_I<4> CS04<1> CS00<5> VDD VSS / ++ RM_IHPSG13_256x8_c2_1P_DEC01 +XDEC01<0> ADDR_N_I<5> ADDR_N_I<4> CS04<0> CS00<1> VDD VSS / ++ RM_IHPSG13_256x8_c2_1P_DEC01 +.ENDS +.SUBCKT RM_IHPSG13_256x8_c2_1P_ROWREG8 ACLK_N_I ADDR_I<7> ADDR_I<6> ADDR_I<5> ADDR_I<4> ++ ADDR_I<3> ADDR_I<2> ADDR_I<1> ADDR_I<0> ADDR_N_O<7> ADDR_N_O<6> ADDR_N_O<5> ++ ADDR_N_O<4> ADDR_N_O<3> ADDR_N_O<2> ADDR_N_O<1> ADDR_N_O<0> BIST_ADDR_I<7> ++ BIST_ADDR_I<6> BIST_ADDR_I<5> BIST_ADDR_I<4> BIST_ADDR_I<3> BIST_ADDR_I<2> ++ BIST_ADDR_I<1> BIST_ADDR_I<0> BIST_EN_I VDD VSS +XINV<7> q_int<7> qn_int<7> VDD VSS / RSC_IHPSG13_CINVX2 +XINV<6> q_int<6> qn_int<6> VDD VSS / RSC_IHPSG13_CINVX2 +XINV<5> q_int<5> qn_int<5> VDD VSS / RSC_IHPSG13_CINVX2 +XINV<4> q_int<4> qn_int<4> VDD VSS / RSC_IHPSG13_CINVX2 +XINV<3> q_int<3> qn_int<3> VDD VSS / RSC_IHPSG13_CINVX2 +XINV<2> q_int<2> qn_int<2> VDD VSS / RSC_IHPSG13_CINVX2 +XINV<1> q_int<1> qn_int<1> VDD VSS / RSC_IHPSG13_CINVX2 +XINV<0> q_int<0> qn_int<0> VDD VSS / RSC_IHPSG13_CINVX2 +XDRV<7> qn_int<7> ADDR_N_O<7> VDD VSS / RSC_IHPSG13_CINVX8 +XDRV<6> qn_int<6> ADDR_N_O<6> VDD VSS / RSC_IHPSG13_CINVX8 +XDRV<5> qn_int<5> ADDR_N_O<5> VDD VSS / RSC_IHPSG13_CINVX8 +XDRV<4> qn_int<4> ADDR_N_O<4> VDD VSS / RSC_IHPSG13_CINVX8 +XDRV<3> qn_int<3> ADDR_N_O<3> VDD VSS / RSC_IHPSG13_CINVX8 +XDRV<2> qn_int<2> ADDR_N_O<2> VDD VSS / RSC_IHPSG13_CINVX8 +XDRV<1> qn_int<1> ADDR_N_O<1> VDD VSS / RSC_IHPSG13_CINVX8 +XDRV<0> qn_int<0> ADDR_N_O<0> VDD VSS / RSC_IHPSG13_CINVX8 +XDFF<7> BIST_EN_I BIST_ADDR_I<7> ACLK_N_I ADDR_I<7> q_int<7> net2<0> VDD ++ VSS / RSC_IHPSG13_DFNQMX2IX1 +XDFF<6> BIST_EN_I BIST_ADDR_I<6> ACLK_N_I ADDR_I<6> q_int<6> net2<1> VDD ++ VSS / RSC_IHPSG13_DFNQMX2IX1 +XDFF<5> BIST_EN_I BIST_ADDR_I<5> ACLK_N_I ADDR_I<5> q_int<5> net2<2> VDD ++ VSS / RSC_IHPSG13_DFNQMX2IX1 +XDFF<4> BIST_EN_I BIST_ADDR_I<4> ACLK_N_I ADDR_I<4> q_int<4> net2<3> VDD ++ VSS / RSC_IHPSG13_DFNQMX2IX1 +XDFF<3> BIST_EN_I BIST_ADDR_I<3> ACLK_N_I ADDR_I<3> q_int<3> net2<4> VDD ++ VSS / RSC_IHPSG13_DFNQMX2IX1 +XDFF<2> BIST_EN_I BIST_ADDR_I<2> ACLK_N_I ADDR_I<2> q_int<2> net2<5> VDD ++ VSS / RSC_IHPSG13_DFNQMX2IX1 +XDFF<1> BIST_EN_I BIST_ADDR_I<1> ACLK_N_I ADDR_I<1> q_int<1> net2<6> VDD ++ VSS / RSC_IHPSG13_DFNQMX2IX1 +XDFF<0> BIST_EN_I BIST_ADDR_I<0> ACLK_N_I ADDR_I<0> q_int<0> net2<7> VDD ++ VSS / RSC_IHPSG13_DFNQMX2IX1 +XI11<4> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI11<3> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI11<2> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI11<1> VDD VSS / RSC_IHPSG13_FILLCAP8 +.ENDS + +.SUBCKT RM_IHPSG13_256x8_c2_1P_ROWDEC9 ADDR_N_I<8> ADDR_N_I<7> ADDR_N_I<6> ADDR_N_I<5> ++ ADDR_N_I<4> ADDR_N_I<3> ADDR_N_I<2> ADDR_N_I<1> ADDR_N_I<0> CS_I ECLK_I ++ WL_O<511> WL_O<510> WL_O<509> WL_O<508> WL_O<507> WL_O<506> WL_O<505> ++ WL_O<504> WL_O<503> WL_O<502> WL_O<501> WL_O<500> WL_O<499> WL_O<498> ++ WL_O<497> WL_O<496> WL_O<495> WL_O<494> WL_O<493> WL_O<492> WL_O<491> ++ WL_O<490> WL_O<489> WL_O<488> WL_O<487> WL_O<486> WL_O<485> WL_O<484> ++ WL_O<483> WL_O<482> WL_O<481> WL_O<480> WL_O<479> WL_O<478> WL_O<477> ++ WL_O<476> WL_O<475> WL_O<474> WL_O<473> WL_O<472> WL_O<471> WL_O<470> ++ WL_O<469> WL_O<468> WL_O<467> WL_O<466> WL_O<465> WL_O<464> WL_O<463> ++ WL_O<462> WL_O<461> WL_O<460> WL_O<459> WL_O<458> WL_O<457> WL_O<456> ++ WL_O<455> WL_O<454> WL_O<453> WL_O<452> WL_O<451> WL_O<450> WL_O<449> ++ WL_O<448> WL_O<447> WL_O<446> WL_O<445> WL_O<444> WL_O<443> WL_O<442> ++ WL_O<441> WL_O<440> WL_O<439> WL_O<438> WL_O<437> WL_O<436> WL_O<435> ++ WL_O<434> WL_O<433> WL_O<432> WL_O<431> WL_O<430> WL_O<429> WL_O<428> ++ WL_O<427> WL_O<426> WL_O<425> WL_O<424> WL_O<423> WL_O<422> WL_O<421> ++ WL_O<420> WL_O<419> WL_O<418> WL_O<417> WL_O<416> WL_O<415> WL_O<414> ++ WL_O<413> WL_O<412> WL_O<411> WL_O<410> WL_O<409> WL_O<408> WL_O<407> ++ WL_O<406> WL_O<405> WL_O<404> WL_O<403> WL_O<402> WL_O<401> WL_O<400> ++ WL_O<399> WL_O<398> WL_O<397> WL_O<396> WL_O<395> WL_O<394> WL_O<393> ++ WL_O<392> WL_O<391> WL_O<390> WL_O<389> WL_O<388> WL_O<387> WL_O<386> ++ WL_O<385> WL_O<384> WL_O<383> WL_O<382> WL_O<381> WL_O<380> WL_O<379> ++ WL_O<378> WL_O<377> WL_O<376> WL_O<375> WL_O<374> WL_O<373> WL_O<372> ++ WL_O<371> WL_O<370> WL_O<369> WL_O<368> WL_O<367> WL_O<366> WL_O<365> ++ WL_O<364> WL_O<363> WL_O<362> WL_O<361> WL_O<360> WL_O<359> WL_O<358> ++ WL_O<357> WL_O<356> WL_O<355> WL_O<354> WL_O<353> WL_O<352> WL_O<351> ++ WL_O<350> WL_O<349> WL_O<348> WL_O<347> WL_O<346> WL_O<345> WL_O<344> ++ WL_O<343> WL_O<342> WL_O<341> WL_O<340> WL_O<339> WL_O<338> WL_O<337> ++ WL_O<336> WL_O<335> WL_O<334> WL_O<333> WL_O<332> WL_O<331> WL_O<330> ++ WL_O<329> WL_O<328> WL_O<327> WL_O<326> WL_O<325> WL_O<324> WL_O<323> ++ WL_O<322> WL_O<321> WL_O<320> WL_O<319> WL_O<318> WL_O<317> WL_O<316> ++ WL_O<315> WL_O<314> WL_O<313> WL_O<312> WL_O<311> WL_O<310> WL_O<309> ++ WL_O<308> WL_O<307> WL_O<306> WL_O<305> WL_O<304> WL_O<303> WL_O<302> ++ WL_O<301> WL_O<300> WL_O<299> WL_O<298> WL_O<297> WL_O<296> WL_O<295> ++ WL_O<294> WL_O<293> WL_O<292> WL_O<291> WL_O<290> WL_O<289> WL_O<288> ++ WL_O<287> WL_O<286> WL_O<285> WL_O<284> WL_O<283> WL_O<282> WL_O<281> ++ WL_O<280> WL_O<279> WL_O<278> WL_O<277> WL_O<276> WL_O<275> WL_O<274> ++ WL_O<273> WL_O<272> WL_O<271> WL_O<270> WL_O<269> WL_O<268> WL_O<267> ++ WL_O<266> WL_O<265> WL_O<264> WL_O<263> WL_O<262> WL_O<261> WL_O<260> ++ WL_O<259> WL_O<258> WL_O<257> WL_O<256> WL_O<255> WL_O<254> WL_O<253> ++ WL_O<252> WL_O<251> WL_O<250> WL_O<249> WL_O<248> WL_O<247> WL_O<246> ++ WL_O<245> WL_O<244> WL_O<243> WL_O<242> WL_O<241> WL_O<240> WL_O<239> ++ WL_O<238> WL_O<237> WL_O<236> WL_O<235> WL_O<234> WL_O<233> WL_O<232> ++ WL_O<231> WL_O<230> WL_O<229> WL_O<228> WL_O<227> WL_O<226> WL_O<225> ++ WL_O<224> WL_O<223> WL_O<222> WL_O<221> WL_O<220> WL_O<219> WL_O<218> ++ WL_O<217> WL_O<216> WL_O<215> WL_O<214> WL_O<213> WL_O<212> WL_O<211> ++ WL_O<210> WL_O<209> WL_O<208> WL_O<207> WL_O<206> WL_O<205> WL_O<204> ++ WL_O<203> WL_O<202> WL_O<201> WL_O<200> WL_O<199> WL_O<198> WL_O<197> ++ WL_O<196> WL_O<195> WL_O<194> WL_O<193> WL_O<192> WL_O<191> WL_O<190> ++ WL_O<189> WL_O<188> WL_O<187> WL_O<186> WL_O<185> WL_O<184> WL_O<183> ++ WL_O<182> WL_O<181> WL_O<180> WL_O<179> WL_O<178> WL_O<177> WL_O<176> ++ WL_O<175> WL_O<174> WL_O<173> WL_O<172> WL_O<171> WL_O<170> WL_O<169> ++ WL_O<168> WL_O<167> WL_O<166> WL_O<165> WL_O<164> WL_O<163> WL_O<162> ++ WL_O<161> WL_O<160> WL_O<159> WL_O<158> WL_O<157> WL_O<156> WL_O<155> ++ WL_O<154> WL_O<153> WL_O<152> WL_O<151> WL_O<150> WL_O<149> WL_O<148> ++ WL_O<147> WL_O<146> WL_O<145> WL_O<144> WL_O<143> WL_O<142> WL_O<141> ++ WL_O<140> WL_O<139> WL_O<138> WL_O<137> WL_O<136> WL_O<135> WL_O<134> ++ WL_O<133> WL_O<132> WL_O<131> WL_O<130> WL_O<129> WL_O<128> WL_O<127> ++ WL_O<126> WL_O<125> WL_O<124> WL_O<123> WL_O<122> WL_O<121> WL_O<120> ++ WL_O<119> WL_O<118> WL_O<117> WL_O<116> WL_O<115> WL_O<114> WL_O<113> ++ WL_O<112> WL_O<111> WL_O<110> WL_O<109> WL_O<108> WL_O<107> WL_O<106> ++ WL_O<105> WL_O<104> WL_O<103> WL_O<102> WL_O<101> WL_O<100> WL_O<99> ++ WL_O<98> WL_O<97> WL_O<96> WL_O<95> WL_O<94> WL_O<93> WL_O<92> WL_O<91> ++ WL_O<90> WL_O<89> WL_O<88> WL_O<87> WL_O<86> WL_O<85> WL_O<84> WL_O<83> ++ WL_O<82> WL_O<81> WL_O<80> WL_O<79> WL_O<78> WL_O<77> WL_O<76> WL_O<75> ++ WL_O<74> WL_O<73> WL_O<72> WL_O<71> WL_O<70> WL_O<69> WL_O<68> WL_O<67> ++ WL_O<66> WL_O<65> WL_O<64> WL_O<63> WL_O<62> WL_O<61> WL_O<60> WL_O<59> ++ WL_O<58> WL_O<57> WL_O<56> WL_O<55> WL_O<54> WL_O<53> WL_O<52> WL_O<51> ++ WL_O<50> WL_O<49> WL_O<48> WL_O<47> WL_O<46> WL_O<45> WL_O<44> WL_O<43> ++ WL_O<42> WL_O<41> WL_O<40> WL_O<39> WL_O<38> WL_O<37> WL_O<36> WL_O<35> ++ WL_O<34> WL_O<33> WL_O<32> WL_O<31> WL_O<30> WL_O<29> WL_O<28> WL_O<27> ++ WL_O<26> WL_O<25> WL_O<24> WL_O<23> WL_O<22> WL_O<21> WL_O<20> WL_O<19> ++ WL_O<18> WL_O<17> WL_O<16> WL_O<15> WL_O<14> WL_O<13> WL_O<12> WL_O<11> ++ WL_O<10> WL_O<9> WL_O<8> WL_O<7> WL_O<6> WL_O<5> WL_O<4> WL_O<3> WL_O<2> ++ WL_O<1> WL_O<0> VDD VSS +XL2<172> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<171> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<170> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<169> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<168> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<167> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<166> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<165> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<164> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<163> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<162> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<161> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<160> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<159> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<158> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<157> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<156> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<155> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<154> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<153> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<152> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<151> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<150> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<149> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<148> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<147> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<146> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<145> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<144> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<143> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<142> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<141> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<140> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<139> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<138> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<137> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<136> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<135> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<134> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<133> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<132> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<131> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<130> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<129> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<128> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<127> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<126> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<125> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<124> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<123> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<122> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<121> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<120> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<119> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<118> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<117> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<116> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<115> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<114> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<113> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<112> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<111> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<110> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<109> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<108> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<107> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<106> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<105> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<104> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<103> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<102> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<101> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<100> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<99> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<98> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<97> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<96> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<95> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<94> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<93> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<92> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<91> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<90> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<89> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<88> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<87> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<86> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<85> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<84> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<83> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<82> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<81> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<80> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<79> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<78> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<77> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<76> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<75> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<74> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<73> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<72> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<71> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<70> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<69> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<68> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<67> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<66> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<65> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<64> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<63> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<62> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<61> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<60> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<59> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<58> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<57> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<56> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<55> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<54> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<53> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<52> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<51> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<50> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<49> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<48> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<47> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<46> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<45> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<44> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<43> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<42> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<41> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<40> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<39> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<38> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<37> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<36> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<35> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<34> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<33> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<32> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<31> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<30> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<29> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<28> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<27> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<26> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<25> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<24> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<23> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<22> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<21> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<20> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<19> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<18> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<17> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<16> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<15> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<14> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<13> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<12> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<11> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<10> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<9> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<8> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<7> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<6> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<5> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<4> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<3> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<2> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<1> VDD VSS / RSC_IHPSG13_FILLCAP8 +XDEC11<9> ADDR_N_I<7> ADDR_N_I<6> CS04<1> CS02<7> VDD VSS / ++ RM_IHPSG13_256x8_c2_1P_DEC03 +XDEC11<8> ADDR_N_I<7> ADDR_N_I<6> CS04<0> CS02<3> VDD VSS / ++ RM_IHPSG13_256x8_c2_1P_DEC03 +XDEC11<7> ADDR_N_I<5> ADDR_N_I<4> CS02<7> CS00<31> VDD VSS / ++ RM_IHPSG13_256x8_c2_1P_DEC03 +XDEC11<6> ADDR_N_I<5> ADDR_N_I<4> CS02<6> CS00<27> VDD VSS / ++ RM_IHPSG13_256x8_c2_1P_DEC03 +XDEC11<5> ADDR_N_I<5> ADDR_N_I<4> CS02<5> CS00<23> VDD VSS / ++ RM_IHPSG13_256x8_c2_1P_DEC03 +XDEC11<4> ADDR_N_I<5> ADDR_N_I<4> CS02<4> CS00<19> VDD VSS / ++ RM_IHPSG13_256x8_c2_1P_DEC03 +XDEC11<3> ADDR_N_I<5> ADDR_N_I<4> CS02<3> CS00<15> VDD VSS / ++ RM_IHPSG13_256x8_c2_1P_DEC03 +XDEC11<2> ADDR_N_I<5> ADDR_N_I<4> CS02<2> CS00<11> VDD VSS / ++ RM_IHPSG13_256x8_c2_1P_DEC03 +XDEC11<1> ADDR_N_I<5> ADDR_N_I<4> CS02<1> CS00<7> VDD VSS / ++ RM_IHPSG13_256x8_c2_1P_DEC03 +XDEC11<0> ADDR_N_I<5> ADDR_N_I<4> CS02<0> CS00<3> VDD VSS / ++ RM_IHPSG13_256x8_c2_1P_DEC03 +XDEC00<10> ADDR_N_I<9> ADDR_N_I<8> CS_I CS04<0> VDD VSS / ++ RM_IHPSG13_256x8_c2_1P_DEC00 +XDEC00<9> ADDR_N_I<7> ADDR_N_I<6> CS04<1> CS02<4> VDD VSS / ++ RM_IHPSG13_256x8_c2_1P_DEC00 +XDEC00<8> ADDR_N_I<7> ADDR_N_I<6> CS04<0> CS02<0> VDD VSS / ++ RM_IHPSG13_256x8_c2_1P_DEC00 +XDEC00<7> ADDR_N_I<5> ADDR_N_I<4> CS02<7> CS00<28> VDD VSS / ++ RM_IHPSG13_256x8_c2_1P_DEC00 +XDEC00<6> ADDR_N_I<5> ADDR_N_I<4> CS02<6> CS00<24> VDD VSS / ++ RM_IHPSG13_256x8_c2_1P_DEC00 +XDEC00<5> ADDR_N_I<5> ADDR_N_I<4> CS02<5> CS00<20> VDD VSS / ++ RM_IHPSG13_256x8_c2_1P_DEC00 +XDEC00<4> ADDR_N_I<5> ADDR_N_I<4> CS02<4> CS00<16> VDD VSS / ++ RM_IHPSG13_256x8_c2_1P_DEC00 +XDEC00<3> ADDR_N_I<5> ADDR_N_I<4> CS02<3> CS00<12> VDD VSS / ++ RM_IHPSG13_256x8_c2_1P_DEC00 +XDEC00<2> ADDR_N_I<5> ADDR_N_I<4> CS02<2> CS00<8> VDD VSS / ++ RM_IHPSG13_256x8_c2_1P_DEC00 +XDEC00<1> ADDR_N_I<5> ADDR_N_I<4> CS02<1> CS00<4> VDD VSS / ++ RM_IHPSG13_256x8_c2_1P_DEC00 +XDEC00<0> ADDR_N_I<5> ADDR_N_I<4> CS02<0> CS00<0> VDD VSS / ++ RM_IHPSG13_256x8_c2_1P_DEC00 +XSEL<31> ADDR_N_I<3> ADDR_N_I<2> ADDR_N_I<1> ADDR_N_I<0> CS00<31> ECLK_H<31> ++ ECLK_H<32> ECLK_B<31> ECLK_B<32> WL_O<511> WL_O<510> WL_O<509> WL_O<508> ++ WL_O<507> WL_O<506> WL_O<505> WL_O<504> WL_O<503> WL_O<502> WL_O<501> ++ WL_O<500> WL_O<499> WL_O<498> WL_O<497> WL_O<496> VDD VSS / ++ RM_IHPSG13_256x8_c2_1P_DEC04 +XSEL<30> ADDR_N_I<3> ADDR_N_I<2> ADDR_N_I<1> ADDR_N_I<0> CS00<30> ECLK_H<30> ++ ECLK_H<31> ECLK_B<30> ECLK_B<31> WL_O<495> WL_O<494> WL_O<493> WL_O<492> ++ WL_O<491> WL_O<490> WL_O<489> WL_O<488> WL_O<487> WL_O<486> WL_O<485> ++ WL_O<484> WL_O<483> WL_O<482> WL_O<481> WL_O<480> VDD VSS / ++ RM_IHPSG13_256x8_c2_1P_DEC04 +XSEL<29> ADDR_N_I<3> ADDR_N_I<2> ADDR_N_I<1> ADDR_N_I<0> CS00<29> ECLK_H<29> ++ ECLK_H<30> ECLK_B<29> ECLK_B<30> WL_O<479> WL_O<478> WL_O<477> WL_O<476> ++ WL_O<475> WL_O<474> WL_O<473> WL_O<472> WL_O<471> WL_O<470> WL_O<469> ++ WL_O<468> WL_O<467> WL_O<466> WL_O<465> WL_O<464> VDD VSS / ++ RM_IHPSG13_256x8_c2_1P_DEC04 +XSEL<28> ADDR_N_I<3> ADDR_N_I<2> ADDR_N_I<1> ADDR_N_I<0> CS00<28> ECLK_H<28> ++ ECLK_H<29> ECLK_B<28> ECLK_B<29> WL_O<463> WL_O<462> WL_O<461> WL_O<460> ++ WL_O<459> WL_O<458> WL_O<457> WL_O<456> WL_O<455> WL_O<454> WL_O<453> ++ WL_O<452> WL_O<451> WL_O<450> WL_O<449> WL_O<448> VDD VSS / ++ RM_IHPSG13_256x8_c2_1P_DEC04 +XSEL<27> ADDR_N_I<3> ADDR_N_I<2> ADDR_N_I<1> ADDR_N_I<0> CS00<27> ECLK_H<27> ++ ECLK_H<28> ECLK_B<27> ECLK_B<28> WL_O<447> WL_O<446> WL_O<445> WL_O<444> ++ WL_O<443> WL_O<442> WL_O<441> WL_O<440> WL_O<439> WL_O<438> WL_O<437> ++ WL_O<436> WL_O<435> WL_O<434> WL_O<433> WL_O<432> VDD VSS / ++ RM_IHPSG13_256x8_c2_1P_DEC04 +XSEL<26> ADDR_N_I<3> ADDR_N_I<2> ADDR_N_I<1> ADDR_N_I<0> CS00<26> ECLK_H<26> ++ ECLK_H<27> ECLK_B<26> ECLK_B<27> WL_O<431> WL_O<430> WL_O<429> WL_O<428> ++ WL_O<427> WL_O<426> WL_O<425> WL_O<424> WL_O<423> WL_O<422> WL_O<421> ++ WL_O<420> WL_O<419> WL_O<418> WL_O<417> WL_O<416> VDD VSS / ++ RM_IHPSG13_256x8_c2_1P_DEC04 +XSEL<25> ADDR_N_I<3> ADDR_N_I<2> ADDR_N_I<1> ADDR_N_I<0> CS00<25> ECLK_H<25> ++ ECLK_H<26> ECLK_B<25> ECLK_B<26> WL_O<415> WL_O<414> WL_O<413> WL_O<412> ++ WL_O<411> WL_O<410> WL_O<409> WL_O<408> WL_O<407> WL_O<406> WL_O<405> ++ WL_O<404> WL_O<403> WL_O<402> WL_O<401> WL_O<400> VDD VSS / ++ RM_IHPSG13_256x8_c2_1P_DEC04 +XSEL<24> ADDR_N_I<3> ADDR_N_I<2> ADDR_N_I<1> ADDR_N_I<0> CS00<24> ECLK_H<24> ++ ECLK_H<25> ECLK_B<24> ECLK_B<25> WL_O<399> WL_O<398> WL_O<397> WL_O<396> ++ WL_O<395> WL_O<394> WL_O<393> WL_O<392> WL_O<391> WL_O<390> WL_O<389> ++ WL_O<388> WL_O<387> WL_O<386> WL_O<385> WL_O<384> VDD VSS / ++ RM_IHPSG13_256x8_c2_1P_DEC04 +XSEL<23> ADDR_N_I<3> ADDR_N_I<2> ADDR_N_I<1> ADDR_N_I<0> CS00<23> ECLK_H<23> ++ ECLK_H<24> ECLK_B<23> ECLK_B<24> WL_O<383> WL_O<382> WL_O<381> WL_O<380> ++ WL_O<379> WL_O<378> WL_O<377> WL_O<376> WL_O<375> WL_O<374> WL_O<373> ++ WL_O<372> WL_O<371> WL_O<370> WL_O<369> WL_O<368> VDD VSS / ++ RM_IHPSG13_256x8_c2_1P_DEC04 +XSEL<22> ADDR_N_I<3> ADDR_N_I<2> ADDR_N_I<1> ADDR_N_I<0> CS00<22> ECLK_H<22> ++ ECLK_H<23> ECLK_B<22> ECLK_B<23> WL_O<367> WL_O<366> WL_O<365> WL_O<364> ++ WL_O<363> WL_O<362> WL_O<361> WL_O<360> WL_O<359> WL_O<358> WL_O<357> ++ WL_O<356> WL_O<355> WL_O<354> WL_O<353> WL_O<352> VDD VSS / ++ RM_IHPSG13_256x8_c2_1P_DEC04 +XSEL<21> ADDR_N_I<3> ADDR_N_I<2> ADDR_N_I<1> ADDR_N_I<0> CS00<21> ECLK_H<21> ++ ECLK_H<22> ECLK_B<21> ECLK_B<22> WL_O<351> WL_O<350> WL_O<349> WL_O<348> ++ WL_O<347> WL_O<346> WL_O<345> WL_O<344> WL_O<343> WL_O<342> WL_O<341> ++ WL_O<340> WL_O<339> WL_O<338> WL_O<337> WL_O<336> VDD VSS / ++ RM_IHPSG13_256x8_c2_1P_DEC04 +XSEL<20> ADDR_N_I<3> ADDR_N_I<2> ADDR_N_I<1> ADDR_N_I<0> CS00<20> ECLK_H<20> ++ ECLK_H<21> ECLK_B<20> ECLK_B<21> WL_O<335> WL_O<334> WL_O<333> WL_O<332> ++ WL_O<331> WL_O<330> WL_O<329> WL_O<328> WL_O<327> WL_O<326> WL_O<325> ++ WL_O<324> WL_O<323> WL_O<322> WL_O<321> WL_O<320> VDD VSS / ++ RM_IHPSG13_256x8_c2_1P_DEC04 +XSEL<19> ADDR_N_I<3> ADDR_N_I<2> ADDR_N_I<1> ADDR_N_I<0> CS00<19> ECLK_H<19> ++ ECLK_H<20> ECLK_B<19> ECLK_B<20> WL_O<319> WL_O<318> WL_O<317> WL_O<316> ++ WL_O<315> WL_O<314> WL_O<313> WL_O<312> WL_O<311> WL_O<310> WL_O<309> ++ WL_O<308> WL_O<307> WL_O<306> WL_O<305> WL_O<304> VDD VSS / ++ RM_IHPSG13_256x8_c2_1P_DEC04 +XSEL<18> ADDR_N_I<3> ADDR_N_I<2> ADDR_N_I<1> ADDR_N_I<0> CS00<18> ECLK_H<18> ++ ECLK_H<19> ECLK_B<18> ECLK_B<19> WL_O<303> WL_O<302> WL_O<301> WL_O<300> ++ WL_O<299> WL_O<298> WL_O<297> WL_O<296> WL_O<295> WL_O<294> WL_O<293> ++ WL_O<292> WL_O<291> WL_O<290> WL_O<289> WL_O<288> VDD VSS / ++ RM_IHPSG13_256x8_c2_1P_DEC04 +XSEL<17> ADDR_N_I<3> ADDR_N_I<2> ADDR_N_I<1> ADDR_N_I<0> CS00<17> ECLK_H<17> ++ ECLK_H<18> ECLK_B<17> ECLK_B<18> WL_O<287> WL_O<286> WL_O<285> WL_O<284> ++ WL_O<283> WL_O<282> WL_O<281> WL_O<280> WL_O<279> WL_O<278> WL_O<277> ++ WL_O<276> WL_O<275> WL_O<274> WL_O<273> WL_O<272> VDD VSS / ++ RM_IHPSG13_256x8_c2_1P_DEC04 +XSEL<16> ADDR_N_I<3> ADDR_N_I<2> ADDR_N_I<1> ADDR_N_I<0> CS00<16> ECLK_H<16> ++ ECLK_H<17> ECLK_B<16> ECLK_B<17> WL_O<271> WL_O<270> WL_O<269> WL_O<268> ++ WL_O<267> WL_O<266> WL_O<265> WL_O<264> WL_O<263> WL_O<262> WL_O<261> ++ WL_O<260> WL_O<259> WL_O<258> WL_O<257> WL_O<256> VDD VSS / ++ RM_IHPSG13_256x8_c2_1P_DEC04 +XSEL<15> ADDR_N_I<3> ADDR_N_I<2> ADDR_N_I<1> ADDR_N_I<0> CS00<15> ECLK_H<15> ++ ECLK_H<16> ECLK_B<15> ECLK_B<16> WL_O<255> WL_O<254> WL_O<253> WL_O<252> ++ WL_O<251> WL_O<250> WL_O<249> WL_O<248> WL_O<247> WL_O<246> WL_O<245> ++ WL_O<244> WL_O<243> WL_O<242> WL_O<241> WL_O<240> VDD VSS / ++ RM_IHPSG13_256x8_c2_1P_DEC04 +XSEL<14> ADDR_N_I<3> ADDR_N_I<2> ADDR_N_I<1> ADDR_N_I<0> CS00<14> ECLK_H<14> ++ ECLK_H<15> ECLK_B<14> ECLK_B<15> WL_O<239> WL_O<238> WL_O<237> WL_O<236> ++ WL_O<235> WL_O<234> WL_O<233> WL_O<232> WL_O<231> WL_O<230> WL_O<229> ++ WL_O<228> WL_O<227> WL_O<226> WL_O<225> WL_O<224> VDD VSS / ++ RM_IHPSG13_256x8_c2_1P_DEC04 +XSEL<13> ADDR_N_I<3> ADDR_N_I<2> ADDR_N_I<1> ADDR_N_I<0> CS00<13> ECLK_H<13> ++ ECLK_H<14> ECLK_B<13> ECLK_B<14> WL_O<223> WL_O<222> WL_O<221> WL_O<220> ++ WL_O<219> WL_O<218> WL_O<217> WL_O<216> WL_O<215> WL_O<214> WL_O<213> ++ WL_O<212> WL_O<211> WL_O<210> WL_O<209> WL_O<208> VDD VSS / ++ RM_IHPSG13_256x8_c2_1P_DEC04 +XSEL<12> ADDR_N_I<3> ADDR_N_I<2> ADDR_N_I<1> ADDR_N_I<0> CS00<12> ECLK_H<12> ++ ECLK_H<13> ECLK_B<12> ECLK_B<13> WL_O<207> WL_O<206> WL_O<205> WL_O<204> ++ WL_O<203> WL_O<202> WL_O<201> WL_O<200> WL_O<199> WL_O<198> WL_O<197> ++ WL_O<196> WL_O<195> WL_O<194> WL_O<193> WL_O<192> VDD VSS / ++ RM_IHPSG13_256x8_c2_1P_DEC04 +XSEL<11> ADDR_N_I<3> ADDR_N_I<2> ADDR_N_I<1> ADDR_N_I<0> CS00<11> ECLK_H<11> ++ ECLK_H<12> ECLK_B<11> ECLK_B<12> WL_O<191> WL_O<190> WL_O<189> WL_O<188> ++ WL_O<187> WL_O<186> WL_O<185> WL_O<184> WL_O<183> WL_O<182> WL_O<181> ++ WL_O<180> WL_O<179> WL_O<178> WL_O<177> WL_O<176> VDD VSS / ++ RM_IHPSG13_256x8_c2_1P_DEC04 +XSEL<10> ADDR_N_I<3> ADDR_N_I<2> ADDR_N_I<1> ADDR_N_I<0> CS00<10> ECLK_H<10> ++ ECLK_H<11> ECLK_B<10> ECLK_B<11> WL_O<175> WL_O<174> WL_O<173> WL_O<172> ++ WL_O<171> WL_O<170> WL_O<169> WL_O<168> WL_O<167> WL_O<166> WL_O<165> ++ WL_O<164> WL_O<163> WL_O<162> WL_O<161> WL_O<160> VDD VSS / ++ RM_IHPSG13_256x8_c2_1P_DEC04 +XSEL<9> ADDR_N_I<3> ADDR_N_I<2> ADDR_N_I<1> ADDR_N_I<0> CS00<9> ECLK_H<9> ++ ECLK_H<10> ECLK_B<9> ECLK_B<10> WL_O<159> WL_O<158> WL_O<157> WL_O<156> ++ WL_O<155> WL_O<154> WL_O<153> WL_O<152> WL_O<151> WL_O<150> WL_O<149> ++ WL_O<148> WL_O<147> WL_O<146> WL_O<145> WL_O<144> VDD VSS / ++ RM_IHPSG13_256x8_c2_1P_DEC04 +XSEL<8> ADDR_N_I<3> ADDR_N_I<2> ADDR_N_I<1> ADDR_N_I<0> CS00<8> ECLK_H<8> ++ ECLK_H<9> ECLK_B<8> ECLK_B<9> WL_O<143> WL_O<142> WL_O<141> WL_O<140> ++ WL_O<139> WL_O<138> WL_O<137> WL_O<136> WL_O<135> WL_O<134> WL_O<133> ++ WL_O<132> WL_O<131> WL_O<130> WL_O<129> WL_O<128> VDD VSS / ++ RM_IHPSG13_256x8_c2_1P_DEC04 +XSEL<7> ADDR_N_I<3> ADDR_N_I<2> ADDR_N_I<1> ADDR_N_I<0> CS00<7> ECLK_H<7> ++ ECLK_H<8> ECLK_B<7> ECLK_B<8> WL_O<127> WL_O<126> WL_O<125> WL_O<124> ++ WL_O<123> WL_O<122> WL_O<121> WL_O<120> WL_O<119> WL_O<118> WL_O<117> ++ WL_O<116> WL_O<115> WL_O<114> WL_O<113> WL_O<112> VDD VSS / ++ RM_IHPSG13_256x8_c2_1P_DEC04 +XSEL<6> ADDR_N_I<3> ADDR_N_I<2> ADDR_N_I<1> ADDR_N_I<0> CS00<6> ECLK_H<6> ++ ECLK_H<7> ECLK_B<6> ECLK_B<7> WL_O<111> WL_O<110> WL_O<109> WL_O<108> ++ WL_O<107> WL_O<106> WL_O<105> WL_O<104> WL_O<103> WL_O<102> WL_O<101> ++ WL_O<100> WL_O<99> WL_O<98> WL_O<97> WL_O<96> VDD VSS / ++ RM_IHPSG13_256x8_c2_1P_DEC04 +XSEL<5> ADDR_N_I<3> ADDR_N_I<2> ADDR_N_I<1> ADDR_N_I<0> CS00<5> ECLK_H<5> ++ ECLK_H<6> ECLK_B<5> ECLK_B<6> WL_O<95> WL_O<94> WL_O<93> WL_O<92> WL_O<91> ++ WL_O<90> WL_O<89> WL_O<88> WL_O<87> WL_O<86> WL_O<85> WL_O<84> WL_O<83> ++ WL_O<82> WL_O<81> WL_O<80> VDD VSS / RM_IHPSG13_256x8_c2_1P_DEC04 +XSEL<4> ADDR_N_I<3> ADDR_N_I<2> ADDR_N_I<1> ADDR_N_I<0> CS00<4> ECLK_H<4> ++ ECLK_H<5> ECLK_B<4> ECLK_B<5> WL_O<79> WL_O<78> WL_O<77> WL_O<76> WL_O<75> ++ WL_O<74> WL_O<73> WL_O<72> WL_O<71> WL_O<70> WL_O<69> WL_O<68> WL_O<67> ++ WL_O<66> WL_O<65> WL_O<64> VDD VSS / RM_IHPSG13_256x8_c2_1P_DEC04 +XSEL<3> ADDR_N_I<3> ADDR_N_I<2> ADDR_N_I<1> ADDR_N_I<0> CS00<3> ECLK_H<3> ++ ECLK_H<4> ECLK_B<3> ECLK_B<4> WL_O<63> WL_O<62> WL_O<61> WL_O<60> WL_O<59> ++ WL_O<58> WL_O<57> WL_O<56> WL_O<55> WL_O<54> WL_O<53> WL_O<52> WL_O<51> ++ WL_O<50> WL_O<49> WL_O<48> VDD VSS / RM_IHPSG13_256x8_c2_1P_DEC04 +XSEL<2> ADDR_N_I<3> ADDR_N_I<2> ADDR_N_I<1> ADDR_N_I<0> CS00<2> ECLK_H<2> ++ ECLK_H<3> ECLK_B<2> ECLK_B<3> WL_O<47> WL_O<46> WL_O<45> WL_O<44> WL_O<43> ++ WL_O<42> WL_O<41> WL_O<40> WL_O<39> WL_O<38> WL_O<37> WL_O<36> WL_O<35> ++ WL_O<34> WL_O<33> WL_O<32> VDD VSS / RM_IHPSG13_256x8_c2_1P_DEC04 +XSEL<1> ADDR_N_I<3> ADDR_N_I<2> ADDR_N_I<1> ADDR_N_I<0> CS00<1> ECLK_H<1> ++ ECLK_H<2> ECLK_B<1> ECLK_B<2> WL_O<31> WL_O<30> WL_O<29> WL_O<28> WL_O<27> ++ WL_O<26> WL_O<25> WL_O<24> WL_O<23> WL_O<22> WL_O<21> WL_O<20> WL_O<19> ++ WL_O<18> WL_O<17> WL_O<16> VDD VSS / RM_IHPSG13_256x8_c2_1P_DEC04 +XSEL<0> ADDR_N_I<3> ADDR_N_I<2> ADDR_N_I<1> ADDR_N_I<0> CS00<0> ECLK_I ++ ECLK_H<1> ECLK_B<0> ECLK_B<1> WL_O<15> WL_O<14> WL_O<13> WL_O<12> WL_O<11> ++ WL_O<10> WL_O<9> WL_O<8> WL_O<7> WL_O<6> WL_O<5> WL_O<4> WL_O<3> WL_O<2> ++ WL_O<1> WL_O<0> VDD VSS / RM_IHPSG13_256x8_c2_1P_DEC04 +XDEC01<10> ADDR_N_I<9> ADDR_N_I<8> CS_I CS04<1> VDD VSS / ++ RM_IHPSG13_256x8_c2_1P_DEC01 +XDEC01<9> ADDR_N_I<7> ADDR_N_I<6> CS04<1> CS02<5> VDD VSS / ++ RM_IHPSG13_256x8_c2_1P_DEC01 +XDEC01<8> ADDR_N_I<7> ADDR_N_I<6> CS04<0> CS02<1> VDD VSS / ++ RM_IHPSG13_256x8_c2_1P_DEC01 +XDEC01<7> ADDR_N_I<5> ADDR_N_I<4> CS02<7> CS00<29> VDD VSS / ++ RM_IHPSG13_256x8_c2_1P_DEC01 +XDEC01<6> ADDR_N_I<5> ADDR_N_I<4> CS02<6> CS00<25> VDD VSS / ++ RM_IHPSG13_256x8_c2_1P_DEC01 +XDEC01<5> ADDR_N_I<5> ADDR_N_I<4> CS02<5> CS00<21> VDD VSS / ++ RM_IHPSG13_256x8_c2_1P_DEC01 +XDEC01<4> ADDR_N_I<5> ADDR_N_I<4> CS02<4> CS00<17> VDD VSS / ++ RM_IHPSG13_256x8_c2_1P_DEC01 +XDEC01<3> ADDR_N_I<5> ADDR_N_I<4> CS02<3> CS00<13> VDD VSS / ++ RM_IHPSG13_256x8_c2_1P_DEC01 +XDEC01<2> ADDR_N_I<5> ADDR_N_I<4> CS02<2> CS00<9> VDD VSS / ++ RM_IHPSG13_256x8_c2_1P_DEC01 +XDEC01<1> ADDR_N_I<5> ADDR_N_I<4> CS02<1> CS00<5> VDD VSS / ++ RM_IHPSG13_256x8_c2_1P_DEC01 +XDEC01<0> ADDR_N_I<5> ADDR_N_I<4> CS02<0> CS00<1> VDD VSS / ++ RM_IHPSG13_256x8_c2_1P_DEC01 +XDEC10<9> ADDR_N_I<7> ADDR_N_I<6> CS04<1> CS02<6> VDD VSS / ++ RM_IHPSG13_256x8_c2_1P_DEC02 +XDEC10<8> ADDR_N_I<7> ADDR_N_I<6> CS04<0> CS02<2> VDD VSS / ++ RM_IHPSG13_256x8_c2_1P_DEC02 +XDEC10<7> ADDR_N_I<5> ADDR_N_I<4> CS02<7> CS00<30> VDD VSS / ++ RM_IHPSG13_256x8_c2_1P_DEC02 +XDEC10<6> ADDR_N_I<5> ADDR_N_I<4> CS02<6> CS00<26> VDD VSS / ++ RM_IHPSG13_256x8_c2_1P_DEC02 +XDEC10<5> ADDR_N_I<5> ADDR_N_I<4> CS02<5> CS00<22> VDD VSS / ++ RM_IHPSG13_256x8_c2_1P_DEC02 +XDEC10<4> ADDR_N_I<5> ADDR_N_I<4> CS02<4> CS00<18> VDD VSS / ++ RM_IHPSG13_256x8_c2_1P_DEC02 +XDEC10<3> ADDR_N_I<5> ADDR_N_I<4> CS02<3> CS00<14> VDD VSS / ++ RM_IHPSG13_256x8_c2_1P_DEC02 +XDEC10<2> ADDR_N_I<5> ADDR_N_I<4> CS02<2> CS00<10> VDD VSS / ++ RM_IHPSG13_256x8_c2_1P_DEC02 +XDEC10<1> ADDR_N_I<5> ADDR_N_I<4> CS02<1> CS00<6> VDD VSS / ++ RM_IHPSG13_256x8_c2_1P_DEC02 +XDEC10<0> ADDR_N_I<5> ADDR_N_I<4> CS02<0> CS00<2> VDD VSS / ++ RM_IHPSG13_256x8_c2_1P_DEC02 +XI0 ADDR_N_I<9> VDD VSS / RSC_IHPSG13_TIEL +.ENDS +.SUBCKT RM_IHPSG13_256x8_c2_1P_ROWREG9 ACLK_N_I ADDR_I<8> ADDR_I<7> ADDR_I<6> ADDR_I<5> ++ ADDR_I<4> ADDR_I<3> ADDR_I<2> ADDR_I<1> ADDR_I<0> ADDR_N_O<8> ADDR_N_O<7> ++ ADDR_N_O<6> ADDR_N_O<5> ADDR_N_O<4> ADDR_N_O<3> ADDR_N_O<2> ADDR_N_O<1> ++ ADDR_N_O<0> BIST_ADDR_I<8> BIST_ADDR_I<7> BIST_ADDR_I<6> BIST_ADDR_I<5> ++ BIST_ADDR_I<4> BIST_ADDR_I<3> BIST_ADDR_I<2> BIST_ADDR_I<1> BIST_ADDR_I<0> ++ BIST_EN_I VDD VSS +XINV<8> q_int<8> qn_int<8> VDD VSS / RSC_IHPSG13_CINVX2 +XINV<7> q_int<7> qn_int<7> VDD VSS / RSC_IHPSG13_CINVX2 +XINV<6> q_int<6> qn_int<6> VDD VSS / RSC_IHPSG13_CINVX2 +XINV<5> q_int<5> qn_int<5> VDD VSS / RSC_IHPSG13_CINVX2 +XINV<4> q_int<4> qn_int<4> VDD VSS / RSC_IHPSG13_CINVX2 +XINV<3> q_int<3> qn_int<3> VDD VSS / RSC_IHPSG13_CINVX2 +XINV<2> q_int<2> qn_int<2> VDD VSS / RSC_IHPSG13_CINVX2 +XINV<1> q_int<1> qn_int<1> VDD VSS / RSC_IHPSG13_CINVX2 +XINV<0> q_int<0> qn_int<0> VDD VSS / RSC_IHPSG13_CINVX2 +XDRV<8> qn_int<8> ADDR_N_O<8> VDD VSS / RSC_IHPSG13_CINVX8 +XDRV<7> qn_int<7> ADDR_N_O<7> VDD VSS / RSC_IHPSG13_CINVX8 +XDRV<6> qn_int<6> ADDR_N_O<6> VDD VSS / RSC_IHPSG13_CINVX8 +XDRV<5> qn_int<5> ADDR_N_O<5> VDD VSS / RSC_IHPSG13_CINVX8 +XDRV<4> qn_int<4> ADDR_N_O<4> VDD VSS / RSC_IHPSG13_CINVX8 +XDRV<3> qn_int<3> ADDR_N_O<3> VDD VSS / RSC_IHPSG13_CINVX8 +XDRV<2> qn_int<2> ADDR_N_O<2> VDD VSS / RSC_IHPSG13_CINVX8 +XDRV<1> qn_int<1> ADDR_N_O<1> VDD VSS / RSC_IHPSG13_CINVX8 +XDRV<0> qn_int<0> ADDR_N_O<0> VDD VSS / RSC_IHPSG13_CINVX8 +XDFF<8> BIST_EN_I BIST_ADDR_I<8> ACLK_N_I ADDR_I<8> q_int<8> net04<0> VDD ++ VSS / RSC_IHPSG13_DFNQMX2IX1 +XDFF<7> BIST_EN_I BIST_ADDR_I<7> ACLK_N_I ADDR_I<7> q_int<7> net04<1> VDD ++ VSS / RSC_IHPSG13_DFNQMX2IX1 +XDFF<6> BIST_EN_I BIST_ADDR_I<6> ACLK_N_I ADDR_I<6> q_int<6> net04<2> VDD ++ VSS / RSC_IHPSG13_DFNQMX2IX1 +XDFF<5> BIST_EN_I BIST_ADDR_I<5> ACLK_N_I ADDR_I<5> q_int<5> net04<3> VDD ++ VSS / RSC_IHPSG13_DFNQMX2IX1 +XDFF<4> BIST_EN_I BIST_ADDR_I<4> ACLK_N_I ADDR_I<4> q_int<4> net04<4> VDD ++ VSS / RSC_IHPSG13_DFNQMX2IX1 +XDFF<3> BIST_EN_I BIST_ADDR_I<3> ACLK_N_I ADDR_I<3> q_int<3> net04<5> VDD ++ VSS / RSC_IHPSG13_DFNQMX2IX1 +XDFF<2> BIST_EN_I BIST_ADDR_I<2> ACLK_N_I ADDR_I<2> q_int<2> net04<6> VDD ++ VSS / RSC_IHPSG13_DFNQMX2IX1 +XDFF<1> BIST_EN_I BIST_ADDR_I<1> ACLK_N_I ADDR_I<1> q_int<1> net04<7> VDD ++ VSS / RSC_IHPSG13_DFNQMX2IX1 +XDFF<0> BIST_EN_I BIST_ADDR_I<0> ACLK_N_I ADDR_I<0> q_int<0> net04<8> VDD ++ VSS / RSC_IHPSG13_DFNQMX2IX1 +.ENDS + +.SUBCKT RM_IHPSG13_256x8_c2_1P_ROWDEC7 ADDR_N_I<6> ADDR_N_I<5> ADDR_N_I<4> ADDR_N_I<3> ++ ADDR_N_I<2> ADDR_N_I<1> ADDR_N_I<0> CS_I ECLK_I WL_O<127> WL_O<126> ++ WL_O<125> WL_O<124> WL_O<123> WL_O<122> WL_O<121> WL_O<120> WL_O<119> ++ WL_O<118> WL_O<117> WL_O<116> WL_O<115> WL_O<114> WL_O<113> WL_O<112> ++ WL_O<111> WL_O<110> WL_O<109> WL_O<108> WL_O<107> WL_O<106> WL_O<105> ++ WL_O<104> WL_O<103> WL_O<102> WL_O<101> WL_O<100> WL_O<99> WL_O<98> WL_O<97> ++ WL_O<96> WL_O<95> WL_O<94> WL_O<93> WL_O<92> WL_O<91> WL_O<90> WL_O<89> ++ WL_O<88> WL_O<87> WL_O<86> WL_O<85> WL_O<84> WL_O<83> WL_O<82> WL_O<81> ++ WL_O<80> WL_O<79> WL_O<78> WL_O<77> WL_O<76> WL_O<75> WL_O<74> WL_O<73> ++ WL_O<72> WL_O<71> WL_O<70> WL_O<69> WL_O<68> WL_O<67> WL_O<66> WL_O<65> ++ WL_O<64> WL_O<63> WL_O<62> WL_O<61> WL_O<60> WL_O<59> WL_O<58> WL_O<57> ++ WL_O<56> WL_O<55> WL_O<54> WL_O<53> WL_O<52> WL_O<51> WL_O<50> WL_O<49> ++ WL_O<48> WL_O<47> WL_O<46> WL_O<45> WL_O<44> WL_O<43> WL_O<42> WL_O<41> ++ WL_O<40> WL_O<39> WL_O<38> WL_O<37> WL_O<36> WL_O<35> WL_O<34> WL_O<33> ++ WL_O<32> WL_O<31> WL_O<30> WL_O<29> WL_O<28> WL_O<27> WL_O<26> WL_O<25> ++ WL_O<24> WL_O<23> WL_O<22> WL_O<21> WL_O<20> WL_O<19> WL_O<18> WL_O<17> ++ WL_O<16> WL_O<15> WL_O<14> WL_O<13> WL_O<12> WL_O<11> WL_O<10> WL_O<9> ++ WL_O<8> WL_O<7> WL_O<6> WL_O<5> WL_O<4> WL_O<3> WL_O<2> WL_O<1> WL_O<0> ++ VDD VSS +XDEC11<1> ADDR_N_I<5> ADDR_N_I<4> CS04<1> CS00<7> VDD VSS / ++ RM_IHPSG13_256x8_c2_1P_DEC03 +XDEC11<0> ADDR_N_I<5> ADDR_N_I<4> CS04<0> CS00<3> VDD VSS / ++ RM_IHPSG13_256x8_c2_1P_DEC03 +XDEC10<1> ADDR_N_I<5> ADDR_N_I<4> CS04<1> CS00<6> VDD VSS / ++ RM_IHPSG13_256x8_c2_1P_DEC02 +XDEC10<0> ADDR_N_I<5> ADDR_N_I<4> CS04<0> CS00<2> VDD VSS / ++ RM_IHPSG13_256x8_c2_1P_DEC02 +XSEL<7> ADDR_N_I<3> ADDR_N_I<2> ADDR_N_I<1> ADDR_N_I<0> CS00<7> ECLK_H<7> ++ ECLK_H<8> ECLK_B<7> ECLK_B<8> WL_O<127> WL_O<126> WL_O<125> WL_O<124> ++ WL_O<123> WL_O<122> WL_O<121> WL_O<120> WL_O<119> WL_O<118> WL_O<117> ++ WL_O<116> WL_O<115> WL_O<114> WL_O<113> WL_O<112> VDD VSS / ++ RM_IHPSG13_256x8_c2_1P_DEC04 +XSEL<6> ADDR_N_I<3> ADDR_N_I<2> ADDR_N_I<1> ADDR_N_I<0> CS00<6> ECLK_H<6> ++ ECLK_H<7> ECLK_B<6> ECLK_B<7> WL_O<111> WL_O<110> WL_O<109> WL_O<108> ++ WL_O<107> WL_O<106> WL_O<105> WL_O<104> WL_O<103> WL_O<102> WL_O<101> ++ WL_O<100> WL_O<99> WL_O<98> WL_O<97> WL_O<96> VDD VSS / ++ RM_IHPSG13_256x8_c2_1P_DEC04 +XSEL<5> ADDR_N_I<3> ADDR_N_I<2> ADDR_N_I<1> ADDR_N_I<0> CS00<5> ECLK_H<5> ++ ECLK_H<6> ECLK_B<5> ECLK_B<6> WL_O<95> WL_O<94> WL_O<93> WL_O<92> WL_O<91> ++ WL_O<90> WL_O<89> WL_O<88> WL_O<87> WL_O<86> WL_O<85> WL_O<84> WL_O<83> ++ WL_O<82> WL_O<81> WL_O<80> VDD VSS / RM_IHPSG13_256x8_c2_1P_DEC04 +XSEL<4> ADDR_N_I<3> ADDR_N_I<2> ADDR_N_I<1> ADDR_N_I<0> CS00<4> ECLK_H<4> ++ ECLK_H<5> ECLK_B<4> ECLK_B<5> WL_O<79> WL_O<78> WL_O<77> WL_O<76> WL_O<75> ++ WL_O<74> WL_O<73> WL_O<72> WL_O<71> WL_O<70> WL_O<69> WL_O<68> WL_O<67> ++ WL_O<66> WL_O<65> WL_O<64> VDD VSS / RM_IHPSG13_256x8_c2_1P_DEC04 +XSEL<3> ADDR_N_I<3> ADDR_N_I<2> ADDR_N_I<1> ADDR_N_I<0> CS00<3> ECLK_H<3> ++ ECLK_H<4> ECLK_B<3> ECLK_B<4> WL_O<63> WL_O<62> WL_O<61> WL_O<60> WL_O<59> ++ WL_O<58> WL_O<57> WL_O<56> WL_O<55> WL_O<54> WL_O<53> WL_O<52> WL_O<51> ++ WL_O<50> WL_O<49> WL_O<48> VDD VSS / RM_IHPSG13_256x8_c2_1P_DEC04 +XSEL<2> ADDR_N_I<3> ADDR_N_I<2> ADDR_N_I<1> ADDR_N_I<0> CS00<2> ECLK_H<2> ++ ECLK_H<3> ECLK_B<2> ECLK_B<3> WL_O<47> WL_O<46> WL_O<45> WL_O<44> WL_O<43> ++ WL_O<42> WL_O<41> WL_O<40> WL_O<39> WL_O<38> WL_O<37> WL_O<36> WL_O<35> ++ WL_O<34> WL_O<33> WL_O<32> VDD VSS / RM_IHPSG13_256x8_c2_1P_DEC04 +XSEL<1> ADDR_N_I<3> ADDR_N_I<2> ADDR_N_I<1> ADDR_N_I<0> CS00<1> ECLK_H<1> ++ ECLK_H<2> ECLK_B<1> ECLK_B<2> WL_O<31> WL_O<30> WL_O<29> WL_O<28> WL_O<27> ++ WL_O<26> WL_O<25> WL_O<24> WL_O<23> WL_O<22> WL_O<21> WL_O<20> WL_O<19> ++ WL_O<18> WL_O<17> WL_O<16> VDD VSS / RM_IHPSG13_256x8_c2_1P_DEC04 +XSEL<0> ADDR_N_I<3> ADDR_N_I<2> ADDR_N_I<1> ADDR_N_I<0> CS00<0> ECLK_I ++ ECLK_H<1> ECLK_B<0> ECLK_B<1> WL_O<15> WL_O<14> WL_O<13> WL_O<12> WL_O<11> ++ WL_O<10> WL_O<9> WL_O<8> WL_O<7> WL_O<6> WL_O<5> WL_O<4> WL_O<3> WL_O<2> ++ WL_O<1> WL_O<0> VDD VSS / RM_IHPSG13_256x8_c2_1P_DEC04 +XDEC00<2> ADDR_N_I<7> ADDR_N_I<6> CS_I CS04<0> VDD VSS / ++ RM_IHPSG13_256x8_c2_1P_DEC00 +XDEC00<1> ADDR_N_I<5> ADDR_N_I<4> CS04<1> CS00<4> VDD VSS / ++ RM_IHPSG13_256x8_c2_1P_DEC00 +XDEC00<0> ADDR_N_I<5> ADDR_N_I<4> CS04<0> CS00<0> VDD VSS / ++ RM_IHPSG13_256x8_c2_1P_DEC00 +XDEC01<2> ADDR_N_I<7> ADDR_N_I<6> CS_I CS04<1> VDD VSS / ++ RM_IHPSG13_256x8_c2_1P_DEC01 +XDEC01<1> ADDR_N_I<5> ADDR_N_I<4> CS04<1> CS00<5> VDD VSS / ++ RM_IHPSG13_256x8_c2_1P_DEC01 +XDEC01<0> ADDR_N_I<5> ADDR_N_I<4> CS04<0> CS00<1> VDD VSS / ++ RM_IHPSG13_256x8_c2_1P_DEC01 +XL2<44> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<43> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<42> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<41> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<40> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<39> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<38> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<37> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<36> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<35> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<34> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<33> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<32> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<31> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<30> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<29> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<28> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<27> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<26> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<25> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<24> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<23> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<22> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<21> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<20> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<19> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<18> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<17> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<16> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<15> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<14> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<13> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<12> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<11> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<10> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<9> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<8> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<7> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<6> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<5> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<4> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<3> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<2> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<1> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI0 ADDR_N_I<7> VDD VSS / RSC_IHPSG13_TIEL +.ENDS +.SUBCKT RM_IHPSG13_256x8_c2_1P_ROWREG7 ACLK_N_I ADDR_I<6> ADDR_I<5> ADDR_I<4> ADDR_I<3> ++ ADDR_I<2> ADDR_I<1> ADDR_I<0> ADDR_N_O<6> ADDR_N_O<5> ADDR_N_O<4> ++ ADDR_N_O<3> ADDR_N_O<2> ADDR_N_O<1> ADDR_N_O<0> BIST_ADDR_I<6> ++ BIST_ADDR_I<5> BIST_ADDR_I<4> BIST_ADDR_I<3> BIST_ADDR_I<2> BIST_ADDR_I<1> ++ BIST_ADDR_I<0> BIST_EN_I VDD VSS +XINV<6> q_int<6> qn_int<6> VDD VSS / RSC_IHPSG13_CINVX2 +XINV<5> q_int<5> qn_int<5> VDD VSS / RSC_IHPSG13_CINVX2 +XINV<4> q_int<4> qn_int<4> VDD VSS / RSC_IHPSG13_CINVX2 +XINV<3> q_int<3> qn_int<3> VDD VSS / RSC_IHPSG13_CINVX2 +XINV<2> q_int<2> qn_int<2> VDD VSS / RSC_IHPSG13_CINVX2 +XINV<1> q_int<1> qn_int<1> VDD VSS / RSC_IHPSG13_CINVX2 +XINV<0> q_int<0> qn_int<0> VDD VSS / RSC_IHPSG13_CINVX2 +XDRV<6> qn_int<6> ADDR_N_O<6> VDD VSS / RSC_IHPSG13_CINVX8 +XDRV<5> qn_int<5> ADDR_N_O<5> VDD VSS / RSC_IHPSG13_CINVX8 +XDRV<4> qn_int<4> ADDR_N_O<4> VDD VSS / RSC_IHPSG13_CINVX8 +XDRV<3> qn_int<3> ADDR_N_O<3> VDD VSS / RSC_IHPSG13_CINVX8 +XDRV<2> qn_int<2> ADDR_N_O<2> VDD VSS / RSC_IHPSG13_CINVX8 +XDRV<1> qn_int<1> ADDR_N_O<1> VDD VSS / RSC_IHPSG13_CINVX8 +XDRV<0> qn_int<0> ADDR_N_O<0> VDD VSS / RSC_IHPSG13_CINVX8 +XDFF<6> BIST_EN_I BIST_ADDR_I<6> ACLK_N_I ADDR_I<6> q_int<6> net2<0> VDD ++ VSS / RSC_IHPSG13_DFNQMX2IX1 +XDFF<5> BIST_EN_I BIST_ADDR_I<5> ACLK_N_I ADDR_I<5> q_int<5> net2<1> VDD ++ VSS / RSC_IHPSG13_DFNQMX2IX1 +XDFF<4> BIST_EN_I BIST_ADDR_I<4> ACLK_N_I ADDR_I<4> q_int<4> net2<2> VDD ++ VSS / RSC_IHPSG13_DFNQMX2IX1 +XDFF<3> BIST_EN_I BIST_ADDR_I<3> ACLK_N_I ADDR_I<3> q_int<3> net2<3> VDD ++ VSS / RSC_IHPSG13_DFNQMX2IX1 +XDFF<2> BIST_EN_I BIST_ADDR_I<2> ACLK_N_I ADDR_I<2> q_int<2> net2<4> VDD ++ VSS / RSC_IHPSG13_DFNQMX2IX1 +XDFF<1> BIST_EN_I BIST_ADDR_I<1> ACLK_N_I ADDR_I<1> q_int<1> net2<5> VDD ++ VSS / RSC_IHPSG13_DFNQMX2IX1 +XDFF<0> BIST_EN_I BIST_ADDR_I<0> ACLK_N_I ADDR_I<0> q_int<0> net2<6> VDD ++ VSS / RSC_IHPSG13_DFNQMX2IX1 +XI11<8> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI11<7> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI11<6> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI11<5> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI11<4> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI11<3> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI11<2> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI11<1> VDD VSS / RSC_IHPSG13_FILLCAP8 +.ENDS + +.SUBCKT RM_IHPSG13_256x8_c2_1P_COLDRV13X8 ADDR_COL_I<1> ADDR_COL_I<0> ADDR_COL_O<1> ++ ADDR_COL_O<0> ADDR_DEC_I<7> ADDR_DEC_I<6> ADDR_DEC_I<5> ADDR_DEC_I<4> ++ ADDR_DEC_I<3> ADDR_DEC_I<2> ADDR_DEC_I<1> ADDR_DEC_I<0> ADDR_DEC_O<7> ++ ADDR_DEC_O<6> ADDR_DEC_O<5> ADDR_DEC_O<4> ADDR_DEC_O<3> ADDR_DEC_O<2> ++ ADDR_DEC_O<1> ADDR_DEC_O<0> DCLK_I DCLK_O RCLK_I RCLK_O WCLK_I WCLK_O ++ VDD VSS +XI0<1> VDD VSS / RSC_IHPSG13_FILLCAP4 +XI0<0> VDD VSS / RSC_IHPSG13_FILLCAP4 +XADDR_COL_DRV<1> ADDR_COL_I<1> ADDR_COL_O<1> VDD VSS / ++ RSC_IHPSG13_CBUFX8 +XADDR_COL_DRV<0> ADDR_COL_I<0> ADDR_COL_O<0> VDD VSS / ++ RSC_IHPSG13_CBUFX8 +XADDR_DEC_DRV<7> ADDR_DEC_I<7> ADDR_DEC_O<7> VDD VSS / ++ RSC_IHPSG13_CBUFX8 +XADDR_DEC_DRV<6> ADDR_DEC_I<6> ADDR_DEC_O<6> VDD VSS / ++ RSC_IHPSG13_CBUFX8 +XADDR_DEC_DRV<5> ADDR_DEC_I<5> ADDR_DEC_O<5> VDD VSS / ++ RSC_IHPSG13_CBUFX8 +XADDR_DEC_DRV<4> ADDR_DEC_I<4> ADDR_DEC_O<4> VDD VSS / ++ RSC_IHPSG13_CBUFX8 +XADDR_DEC_DRV<3> ADDR_DEC_I<3> ADDR_DEC_O<3> VDD VSS / ++ RSC_IHPSG13_CBUFX8 +XADDR_DEC_DRV<2> ADDR_DEC_I<2> ADDR_DEC_O<2> VDD VSS / ++ RSC_IHPSG13_CBUFX8 +XADDR_DEC_DRV<1> ADDR_DEC_I<1> ADDR_DEC_O<1> VDD VSS / ++ RSC_IHPSG13_CBUFX8 +XADDR_DEC_DRV<0> ADDR_DEC_I<0> ADDR_DEC_O<0> VDD VSS / ++ RSC_IHPSG13_CBUFX8 +XDCLK_DRV DCLK_I DCLK_O VDD VSS / RSC_IHPSG13_CBUFX8 +XRCLK_DRV RCLK_I RCLK_O VDD VSS / RSC_IHPSG13_CBUFX8 +XWCLK_DRV WCLK_I WCLK_O VDD VSS / RSC_IHPSG13_CBUFX8 +.ENDS +.SUBCKT RM_IHPSG13_256x8_c2_1P_WLDRV16X8 A<15> A<14> A<13> A<12> A<11> A<10> A<9> A<8> ++ A<7> A<6> A<5> A<4> A<3> A<2> A<1> A<0> Z<15> Z<14> Z<13> Z<12> Z<11> Z<10> ++ Z<9> Z<8> Z<7> Z<6> Z<5> Z<4> Z<3> Z<2> Z<1> Z<0> VDD VSS +XBUF<15> A<15> Z<15> VDD VSS / RSC_IHPSG13_WLDRVX8 +XBUF<14> A<14> Z<14> VDD VSS / RSC_IHPSG13_WLDRVX8 +XBUF<13> A<13> Z<13> VDD VSS / RSC_IHPSG13_WLDRVX8 +XBUF<12> A<12> Z<12> VDD VSS / RSC_IHPSG13_WLDRVX8 +XBUF<11> A<11> Z<11> VDD VSS / RSC_IHPSG13_WLDRVX8 +XBUF<10> A<10> Z<10> VDD VSS / RSC_IHPSG13_WLDRVX8 +XBUF<9> A<9> Z<9> VDD VSS / RSC_IHPSG13_WLDRVX8 +XBUF<8> A<8> Z<8> VDD VSS / RSC_IHPSG13_WLDRVX8 +XBUF<7> A<7> Z<7> VDD VSS / RSC_IHPSG13_WLDRVX8 +XBUF<6> A<6> Z<6> VDD VSS / RSC_IHPSG13_WLDRVX8 +XBUF<5> A<5> Z<5> VDD VSS / RSC_IHPSG13_WLDRVX8 +XBUF<4> A<4> Z<4> VDD VSS / RSC_IHPSG13_WLDRVX8 +XBUF<3> A<3> Z<3> VDD VSS / RSC_IHPSG13_WLDRVX8 +XBUF<2> A<2> Z<2> VDD VSS / RSC_IHPSG13_WLDRVX8 +XBUF<1> A<1> Z<1> VDD VSS / RSC_IHPSG13_WLDRVX8 +XBUF<0> A<0> Z<0> VDD VSS / RSC_IHPSG13_WLDRVX8 +.ENDS + + + +.SUBCKT RM_IHPSG13_256x8_c2_1P_ROWDEC6 ADDR_N_I<5> ADDR_N_I<4> ADDR_N_I<3> ADDR_N_I<2> ++ ADDR_N_I<1> ADDR_N_I<0> CS_I ECLK_I WL_O<63> WL_O<62> WL_O<61> WL_O<60> ++ WL_O<59> WL_O<58> WL_O<57> WL_O<56> WL_O<55> WL_O<54> WL_O<53> WL_O<52> ++ WL_O<51> WL_O<50> WL_O<49> WL_O<48> WL_O<47> WL_O<46> WL_O<45> WL_O<44> ++ WL_O<43> WL_O<42> WL_O<41> WL_O<40> WL_O<39> WL_O<38> WL_O<37> WL_O<36> ++ WL_O<35> WL_O<34> WL_O<33> WL_O<32> WL_O<31> WL_O<30> WL_O<29> WL_O<28> ++ WL_O<27> WL_O<26> WL_O<25> WL_O<24> WL_O<23> WL_O<22> WL_O<21> WL_O<20> ++ WL_O<19> WL_O<18> WL_O<17> WL_O<16> WL_O<15> WL_O<14> WL_O<13> WL_O<12> ++ WL_O<11> WL_O<10> WL_O<9> WL_O<8> WL_O<7> WL_O<6> WL_O<5> WL_O<4> WL_O<3> ++ WL_O<2> WL_O<1> WL_O<0> VDD VSS +XDEC11 ADDR_N_I<5> ADDR_N_I<4> CS_I CS00<3> VDD VSS / ++ RM_IHPSG13_256x8_c2_1P_DEC03 +XDEC00 ADDR_N_I<5> ADDR_N_I<4> CS_I CS00<0> VDD VSS / ++ RM_IHPSG13_256x8_c2_1P_DEC00 +XDEC01 ADDR_N_I<5> ADDR_N_I<4> CS_I CS00<1> VDD VSS / ++ RM_IHPSG13_256x8_c2_1P_DEC01 +XDEC10 ADDR_N_I<5> ADDR_N_I<4> CS_I CS00<2> VDD VSS / ++ RM_IHPSG13_256x8_c2_1P_DEC02 +XSEL<3> ADDR_N_I<3> ADDR_N_I<2> ADDR_N_I<1> ADDR_N_I<0> CS00<3> ECLK_H<3> ++ ECLK_H<4> ECLK_B<3> ECLK_B<4> WL_O<63> WL_O<62> WL_O<61> WL_O<60> WL_O<59> ++ WL_O<58> WL_O<57> WL_O<56> WL_O<55> WL_O<54> WL_O<53> WL_O<52> WL_O<51> ++ WL_O<50> WL_O<49> WL_O<48> VDD VSS / RM_IHPSG13_256x8_c2_1P_DEC04 +XSEL<2> ADDR_N_I<3> ADDR_N_I<2> ADDR_N_I<1> ADDR_N_I<0> CS00<2> ECLK_H<2> ++ ECLK_H<3> ECLK_B<2> ECLK_B<3> WL_O<47> WL_O<46> WL_O<45> WL_O<44> WL_O<43> ++ WL_O<42> WL_O<41> WL_O<40> WL_O<39> WL_O<38> WL_O<37> WL_O<36> WL_O<35> ++ WL_O<34> WL_O<33> WL_O<32> VDD VSS / RM_IHPSG13_256x8_c2_1P_DEC04 +XSEL<1> ADDR_N_I<3> ADDR_N_I<2> ADDR_N_I<1> ADDR_N_I<0> CS00<1> ECLK_H<1> ++ ECLK_H<2> ECLK_B<1> ECLK_B<2> WL_O<31> WL_O<30> WL_O<29> WL_O<28> WL_O<27> ++ WL_O<26> WL_O<25> WL_O<24> WL_O<23> WL_O<22> WL_O<21> WL_O<20> WL_O<19> ++ WL_O<18> WL_O<17> WL_O<16> VDD VSS / RM_IHPSG13_256x8_c2_1P_DEC04 +XSEL<0> ADDR_N_I<3> ADDR_N_I<2> ADDR_N_I<1> ADDR_N_I<0> CS00<0> ECLK_I ++ ECLK_H<1> ECLK_B<0> ECLK_B<1> WL_O<15> WL_O<14> WL_O<13> WL_O<12> WL_O<11> ++ WL_O<10> WL_O<9> WL_O<8> WL_O<7> WL_O<6> WL_O<5> WL_O<4> WL_O<3> WL_O<2> ++ WL_O<1> WL_O<0> VDD VSS / RM_IHPSG13_256x8_c2_1P_DEC04 +XL2<24> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<23> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<22> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<21> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<20> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<19> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<18> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<17> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<16> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<15> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<14> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<13> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<12> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<11> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<10> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<9> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<8> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<7> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<6> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<5> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<4> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<3> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<2> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<1> VDD VSS / RSC_IHPSG13_FILLCAP8 +.ENDS +.SUBCKT RM_IHPSG13_256x8_c2_1P_ROWREG6 ACLK_N_I ADDR_I<5> ADDR_I<4> ADDR_I<3> ADDR_I<2> ++ ADDR_I<1> ADDR_I<0> ADDR_N_O<5> ADDR_N_O<4> ADDR_N_O<3> ADDR_N_O<2> ++ ADDR_N_O<1> ADDR_N_O<0> BIST_ADDR_I<5> BIST_ADDR_I<4> BIST_ADDR_I<3> ++ BIST_ADDR_I<2> BIST_ADDR_I<1> BIST_ADDR_I<0> BIST_EN_I VDD VSS +XINV<5> q_int<5> qn_int<5> VDD VSS / RSC_IHPSG13_CINVX2 +XINV<4> q_int<4> qn_int<4> VDD VSS / RSC_IHPSG13_CINVX2 +XINV<3> q_int<3> qn_int<3> VDD VSS / RSC_IHPSG13_CINVX2 +XINV<2> q_int<2> qn_int<2> VDD VSS / RSC_IHPSG13_CINVX2 +XINV<1> q_int<1> qn_int<1> VDD VSS / RSC_IHPSG13_CINVX2 +XINV<0> q_int<0> qn_int<0> VDD VSS / RSC_IHPSG13_CINVX2 +XDRV<5> qn_int<5> ADDR_N_O<5> VDD VSS / RSC_IHPSG13_CINVX8 +XDRV<4> qn_int<4> ADDR_N_O<4> VDD VSS / RSC_IHPSG13_CINVX8 +XDRV<3> qn_int<3> ADDR_N_O<3> VDD VSS / RSC_IHPSG13_CINVX8 +XDRV<2> qn_int<2> ADDR_N_O<2> VDD VSS / RSC_IHPSG13_CINVX8 +XDRV<1> qn_int<1> ADDR_N_O<1> VDD VSS / RSC_IHPSG13_CINVX8 +XDRV<0> qn_int<0> ADDR_N_O<0> VDD VSS / RSC_IHPSG13_CINVX8 +XDFF<5> BIST_EN_I BIST_ADDR_I<5> ACLK_N_I ADDR_I<5> q_int<5> net2<0> VDD ++ VSS / RSC_IHPSG13_DFNQMX2IX1 +XDFF<4> BIST_EN_I BIST_ADDR_I<4> ACLK_N_I ADDR_I<4> q_int<4> net2<1> VDD ++ VSS / RSC_IHPSG13_DFNQMX2IX1 +XDFF<3> BIST_EN_I BIST_ADDR_I<3> ACLK_N_I ADDR_I<3> q_int<3> net2<2> VDD ++ VSS / RSC_IHPSG13_DFNQMX2IX1 +XDFF<2> BIST_EN_I BIST_ADDR_I<2> ACLK_N_I ADDR_I<2> q_int<2> net2<3> VDD ++ VSS / RSC_IHPSG13_DFNQMX2IX1 +XDFF<1> BIST_EN_I BIST_ADDR_I<1> ACLK_N_I ADDR_I<1> q_int<1> net2<4> VDD ++ VSS / RSC_IHPSG13_DFNQMX2IX1 +XDFF<0> BIST_EN_I BIST_ADDR_I<0> ACLK_N_I ADDR_I<0> q_int<0> net2<5> VDD ++ VSS / RSC_IHPSG13_DFNQMX2IX1 +XI11<12> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI11<11> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI11<10> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI11<9> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI11<8> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI11<7> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI11<6> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI11<5> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI11<4> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI11<3> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI11<2> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI11<1> VDD VSS / RSC_IHPSG13_FILLCAP8 +.ENDS + + +.SUBCKT RM_IHPSG13_256x8_c2_2P_COLUMN_pcell_0 A_BLC_BOT<1> A_BLC_BOT<0> A_BLC_TOP<1> A_BLC_TOP<0> A_BLT_BOT<1> A_BLT_BOT<0> A_BLT_TOP<1> A_BLT_TOP<0> A_LWL<63> A_LWL<62> A_LWL<61> A_LWL<60> A_LWL<59> A_LWL<58> A_LWL<57> A_LWL<56> A_LWL<55> A_LWL<54> A_LWL<53> A_LWL<52> A_LWL<51> A_LWL<50> A_LWL<49> A_LWL<48> A_LWL<47> A_LWL<46> A_LWL<45> A_LWL<44> A_LWL<43> A_LWL<42> A_LWL<41> A_LWL<40> A_LWL<39> A_LWL<38> A_LWL<37> A_LWL<36> A_LWL<35> A_LWL<34> A_LWL<33> A_LWL<32> A_LWL<31> A_LWL<30> A_LWL<29> A_LWL<28> A_LWL<27> A_LWL<26> A_LWL<25> A_LWL<24> A_LWL<23> A_LWL<22> A_LWL<21> A_LWL<20> A_LWL<19> A_LWL<18> A_LWL<17> A_LWL<16> A_LWL<15> A_LWL<14> A_LWL<13> A_LWL<12> A_LWL<11> A_LWL<10> A_LWL<9> A_LWL<8> A_LWL<7> A_LWL<6> A_LWL<5> A_LWL<4> A_LWL<3> A_LWL<2> A_LWL<1> A_LWL<0> A_RWL<63> A_RWL<62> A_RWL<61> A_RWL<60> A_RWL<59> A_RWL<58> A_RWL<57> A_RWL<56> A_RWL<55> A_RWL<54> A_RWL<53> A_RWL<52> A_RWL<51> A_RWL<50> A_RWL<49> A_RWL<48> A_RWL<47> A_RWL<46> A_RWL<45> A_RWL<44> A_RWL<43> A_RWL<42> A_RWL<41> A_RWL<40> A_RWL<39> A_RWL<38> A_RWL<37> A_RWL<36> A_RWL<35> A_RWL<34> A_RWL<33> A_RWL<32> A_RWL<31> A_RWL<30> A_RWL<29> A_RWL<28> A_RWL<27> A_RWL<26> A_RWL<25> A_RWL<24> A_RWL<23> A_RWL<22> A_RWL<21> A_RWL<20> A_RWL<19> A_RWL<18> A_RWL<17> A_RWL<16> A_RWL<15> A_RWL<14> A_RWL<13> A_RWL<12> A_RWL<11> A_RWL<10> A_RWL<9> A_RWL<8> A_RWL<7> A_RWL<6> A_RWL<5> A_RWL<4> A_RWL<3> A_RWL<2> A_RWL<1> A_RWL<0> B_BLC_BOT<1> B_BLC_BOT<0> B_BLC_TOP<1> B_BLC_TOP<0> B_BLT_BOT<1> B_BLT_BOT<0> B_BLT_TOP<1> B_BLT_TOP<0> B_LWL<63> B_LWL<62> B_LWL<61> B_LWL<60> B_LWL<59> B_LWL<58> B_LWL<57> B_LWL<56> B_LWL<55> B_LWL<54> B_LWL<53> B_LWL<52> B_LWL<51> B_LWL<50> B_LWL<49> B_LWL<48> B_LWL<47> B_LWL<46> B_LWL<45> B_LWL<44> B_LWL<43> B_LWL<42> B_LWL<41> B_LWL<40> B_LWL<39> B_LWL<38> B_LWL<37> B_LWL<36> B_LWL<35> B_LWL<34> B_LWL<33> B_LWL<32> B_LWL<31> B_LWL<30> B_LWL<29> B_LWL<28> B_LWL<27> B_LWL<26> B_LWL<25> B_LWL<24> B_LWL<23> B_LWL<22> B_LWL<21> B_LWL<20> B_LWL<19> B_LWL<18> B_LWL<17> B_LWL<16> B_LWL<15> B_LWL<14> B_LWL<13> B_LWL<12> B_LWL<11> B_LWL<10> B_LWL<9> B_LWL<8> B_LWL<7> B_LWL<6> B_LWL<5> B_LWL<4> B_LWL<3> B_LWL<2> B_LWL<1> B_LWL<0> B_RWL<63> B_RWL<62> B_RWL<61> B_RWL<60> B_RWL<59> B_RWL<58> B_RWL<57> B_RWL<56> B_RWL<55> B_RWL<54> B_RWL<53> B_RWL<52> B_RWL<51> B_RWL<50> B_RWL<49> B_RWL<48> B_RWL<47> B_RWL<46> B_RWL<45> B_RWL<44> B_RWL<43> B_RWL<42> B_RWL<41> B_RWL<40> B_RWL<39> B_RWL<38> B_RWL<37> B_RWL<36> B_RWL<35> B_RWL<34> B_RWL<33> B_RWL<32> B_RWL<31> B_RWL<30> B_RWL<29> B_RWL<28> B_RWL<27> B_RWL<26> B_RWL<25> B_RWL<24> B_RWL<23> B_RWL<22> B_RWL<21> B_RWL<20> B_RWL<19> B_RWL<18> B_RWL<17> B_RWL<16> B_RWL<15> B_RWL<14> B_RWL<13> B_RWL<12> B_RWL<11> B_RWL<10> B_RWL<9> B_RWL<8> B_RWL<7> B_RWL<6> B_RWL<5> B_RWL<4> B_RWL<3> B_RWL<2> B_RWL<1> B_RWL<0> VDD_CORE VSS +XRAM<4> A_BLC<5> A_BLC<4> A_BLC_TOP<1> A_BLC_TOP<0> A_BLT<5> A_BLT<4> A_BLT_TOP<1> A_BLT_TOP<0> A_LWL<63> A_LWL<62> A_LWL<61> A_LWL<60> A_LWL<59> A_LWL<58> A_LWL<57> A_LWL<56> A_LWL<55> A_LWL<54> A_LWL<53> A_LWL<52> A_LWL<51> A_LWL<50> A_LWL<49> A_LWL<48> A_RWL<63> A_RWL<62> A_RWL<61> A_RWL<60> A_RWL<59> A_RWL<58> A_RWL<57> A_RWL<56> A_RWL<55> A_RWL<54> A_RWL<53> A_RWL<52> A_RWL<51> A_RWL<50> A_RWL<49> A_RWL<48> B_BLC<5> B_BLC<4> B_BLC_TOP<1> B_BLC_TOP<0> B_BLT<5> B_BLT<4> B_BLT_TOP<1> B_BLT_TOP<0> B_LWL<63> B_LWL<62> B_LWL<61> B_LWL<60> B_LWL<59> B_LWL<58> B_LWL<57> B_LWL<56> B_LWL<55> B_LWL<54> B_LWL<53> B_LWL<52> B_LWL<51> B_LWL<50> B_LWL<49> B_LWL<48> B_RWL<63> B_RWL<62> B_RWL<61> B_RWL<60> B_RWL<59> B_RWL<58> B_RWL<57> B_RWL<56> B_RWL<55> B_RWL<54> B_RWL<53> B_RWL<52> B_RWL<51> B_RWL<50> B_RWL<49> B_RWL<48> VDD_CORE VSS / RM_IHPSG13_256x8_c2_2P_BITKIT_16x2_SRAM +XRAM<3> A_BLC<3> A_BLC<2> A_BLC<5> A_BLC<4> A_BLT<3> A_BLT<2> A_BLT<5> A_BLT<4> A_LWL<47> A_LWL<46> A_LWL<45> A_LWL<44> A_LWL<43> A_LWL<42> A_LWL<41> A_LWL<40> A_LWL<39> A_LWL<38> A_LWL<37> A_LWL<36> A_LWL<35> A_LWL<34> A_LWL<33> A_LWL<32> A_RWL<47> A_RWL<46> A_RWL<45> A_RWL<44> A_RWL<43> A_RWL<42> A_RWL<41> A_RWL<40> A_RWL<39> A_RWL<38> A_RWL<37> A_RWL<36> A_RWL<35> A_RWL<34> A_RWL<33> A_RWL<32> B_BLC<3> B_BLC<2> B_BLC<5> B_BLC<4> B_BLT<3> B_BLT<2> B_BLT<5> B_BLT<4> B_LWL<47> B_LWL<46> B_LWL<45> B_LWL<44> B_LWL<43> B_LWL<42> B_LWL<41> B_LWL<40> B_LWL<39> B_LWL<38> B_LWL<37> B_LWL<36> B_LWL<35> B_LWL<34> B_LWL<33> B_LWL<32> B_RWL<47> B_RWL<46> B_RWL<45> B_RWL<44> B_RWL<43> B_RWL<42> B_RWL<41> B_RWL<40> B_RWL<39> B_RWL<38> B_RWL<37> B_RWL<36> B_RWL<35> B_RWL<34> B_RWL<33> B_RWL<32> VDD_CORE VSS / RM_IHPSG13_256x8_c2_2P_BITKIT_16x2_SRAM +XRAM<2> A_BLC<1> A_BLC<0> A_BLC<3> A_BLC<2> A_BLT<1> A_BLT<0> A_BLT<3> A_BLT<2> A_LWL<31> A_LWL<30> A_LWL<29> A_LWL<28> A_LWL<27> A_LWL<26> A_LWL<25> A_LWL<24> A_LWL<23> A_LWL<22> A_LWL<21> A_LWL<20> A_LWL<19> A_LWL<18> A_LWL<17> A_LWL<16> A_RWL<31> A_RWL<30> A_RWL<29> A_RWL<28> A_RWL<27> A_RWL<26> A_RWL<25> A_RWL<24> A_RWL<23> A_RWL<22> A_RWL<21> A_RWL<20> A_RWL<19> A_RWL<18> A_RWL<17> A_RWL<16> B_BLC<1> B_BLC<0> B_BLC<3> B_BLC<2> B_BLT<1> B_BLT<0> B_BLT<3> B_BLT<2> B_LWL<31> B_LWL<30> B_LWL<29> B_LWL<28> B_LWL<27> B_LWL<26> B_LWL<25> B_LWL<24> B_LWL<23> B_LWL<22> B_LWL<21> B_LWL<20> B_LWL<19> B_LWL<18> B_LWL<17> B_LWL<16> B_RWL<31> B_RWL<30> B_RWL<29> B_RWL<28> B_RWL<27> B_RWL<26> B_RWL<25> B_RWL<24> B_RWL<23> B_RWL<22> B_RWL<21> B_RWL<20> B_RWL<19> B_RWL<18> B_RWL<17> B_RWL<16> VDD_CORE VSS / RM_IHPSG13_256x8_c2_2P_BITKIT_16x2_SRAM +XRAM<1> A_BLC_BOT<1> A_BLC_BOT<0> A_BLC<1> A_BLC<0> A_BLT_BOT<1> A_BLT_BOT<0> A_BLT<1> A_BLT<0> A_LWL<15> A_LWL<14> A_LWL<13> A_LWL<12> A_LWL<11> A_LWL<10> A_LWL<9> A_LWL<8> A_LWL<7> A_LWL<6> A_LWL<5> A_LWL<4> A_LWL<3> A_LWL<2> A_LWL<1> A_LWL<0> A_RWL<15> A_RWL<14> A_RWL<13> A_RWL<12> A_RWL<11> A_RWL<10> A_RWL<9> A_RWL<8> A_RWL<7> A_RWL<6> A_RWL<5> A_RWL<4> A_RWL<3> A_RWL<2> A_RWL<1> A_RWL<0> B_BLC_BOT<1> B_BLC_BOT<0> B_BLC<1> B_BLC<0> B_BLT_BOT<1> B_BLT_BOT<0> B_BLT<1> B_BLT<0> B_LWL<15> B_LWL<14> B_LWL<13> B_LWL<12> B_LWL<11> B_LWL<10> B_LWL<9> B_LWL<8> B_LWL<7> B_LWL<6> B_LWL<5> B_LWL<4> B_LWL<3> B_LWL<2> B_LWL<1> B_LWL<0> B_RWL<15> B_RWL<14> B_RWL<13> B_RWL<12> B_RWL<11> B_RWL<10> B_RWL<9> B_RWL<8> B_RWL<7> B_RWL<6> B_RWL<5> B_RWL<4> B_RWL<3> B_RWL<2> B_RWL<1> B_RWL<0> VDD_CORE VSS / RM_IHPSG13_256x8_c2_2P_BITKIT_16x2_SRAM +XEDGE<1> A_BLC_TOP<1> A_BLC_TOP<0> A_BLT_TOP<1> A_BLT_TOP<0> B_BLC_TOP<1> B_BLC_TOP<0> B_BLT_TOP<1> B_BLT_TOP<0> VDD_CORE VSS / RM_IHPSG13_256x8_c2_2P_BITKIT_16x2_EDGE_TB +XEDGE<0> A_BLC_BOT<1> A_BLC_BOT<0> A_BLT_BOT<1> A_BLT_BOT<0> B_BLC_BOT<1> B_BLC_BOT<0> B_BLT_BOT<1> B_BLT_BOT<0> VDD_CORE VSS / RM_IHPSG13_256x8_c2_2P_BITKIT_16x2_EDGE_TB +.ENDS + + + + +.SUBCKT RM_IHPSG13_256x8_c2_2P_MATRIX_pcell_1 A_BLC<15> A_BLC<14> A_BLC<13> A_BLC<12> A_BLC<11> A_BLC<10> A_BLC<9> A_BLC<8> A_BLC<7> A_BLC<6> A_BLC<5> A_BLC<4> A_BLC<3> A_BLC<2> A_BLC<1> A_BLC<0> A_BLT<15> A_BLT<14> A_BLT<13> A_BLT<12> A_BLT<11> A_BLT<10> A_BLT<9> A_BLT<8> A_BLT<7> A_BLT<6> A_BLT<5> A_BLT<4> A_BLT<3> A_BLT<2> A_BLT<1> A_BLT<0> A_WL<63> A_WL<62> A_WL<61> A_WL<60> A_WL<59> A_WL<58> A_WL<57> A_WL<56> A_WL<55> A_WL<54> A_WL<53> A_WL<52> A_WL<51> A_WL<50> A_WL<49> A_WL<48> A_WL<47> A_WL<46> A_WL<45> A_WL<44> A_WL<43> A_WL<42> A_WL<41> A_WL<40> A_WL<39> A_WL<38> A_WL<37> A_WL<36> A_WL<35> A_WL<34> A_WL<33> A_WL<32> A_WL<31> A_WL<30> A_WL<29> A_WL<28> A_WL<27> A_WL<26> A_WL<25> A_WL<24> A_WL<23> A_WL<22> A_WL<21> A_WL<20> A_WL<19> A_WL<18> A_WL<17> A_WL<16> A_WL<15> A_WL<14> A_WL<13> A_WL<12> A_WL<11> A_WL<10> A_WL<9> A_WL<8> A_WL<7> A_WL<6> A_WL<5> A_WL<4> A_WL<3> A_WL<2> A_WL<1> A_WL<0> B_BLC<15> B_BLC<14> B_BLC<13> B_BLC<12> B_BLC<11> B_BLC<10> B_BLC<9> B_BLC<8> B_BLC<7> B_BLC<6> B_BLC<5> B_BLC<4> B_BLC<3> B_BLC<2> B_BLC<1> B_BLC<0> B_BLT<15> B_BLT<14> B_BLT<13> B_BLT<12> B_BLT<11> B_BLT<10> B_BLT<9> B_BLT<8> B_BLT<7> B_BLT<6> B_BLT<5> B_BLT<4> B_BLT<3> B_BLT<2> B_BLT<1> B_BLT<0> B_WL<63> B_WL<62> B_WL<61> B_WL<60> B_WL<59> B_WL<58> B_WL<57> B_WL<56> B_WL<55> B_WL<54> B_WL<53> B_WL<52> B_WL<51> B_WL<50> B_WL<49> B_WL<48> B_WL<47> B_WL<46> B_WL<45> B_WL<44> B_WL<43> B_WL<42> B_WL<41> B_WL<40> B_WL<39> B_WL<38> B_WL<37> B_WL<36> B_WL<35> B_WL<34> B_WL<33> B_WL<32> B_WL<31> B_WL<30> B_WL<29> B_WL<28> B_WL<27> B_WL<26> B_WL<25> B_WL<24> B_WL<23> B_WL<22> B_WL<21> B_WL<20> B_WL<19> B_WL<18> B_WL<17> B_WL<16> B_WL<15> B_WL<14> B_WL<13> B_WL<12> B_WL<11> B_WL<10> B_WL<9> B_WL<8> B_WL<7> B_WL<6> B_WL<5> B_WL<4> B_WL<3> B_WL<2> B_WL<1> B_WL<0> VDD_CORE VSS +XCORNER<3> VDD_CORE VSS / RM_IHPSG13_256x8_c2_2P_BITKIT_16x2_CORNER +XCORNER<2> VDD_CORE VSS / RM_IHPSG13_256x8_c2_2P_BITKIT_16x2_CORNER +XCORNER<1> VDD_CORE VSS / RM_IHPSG13_256x8_c2_2P_BITKIT_16x2_CORNER +XCORNER<0> VDD_CORE VSS / RM_IHPSG13_256x8_c2_2P_BITKIT_16x2_CORNER +XRAMEDGE_L<3> A_WL<63> A_WL<62> A_WL<61> A_WL<60> A_WL<59> A_WL<58> A_WL<57> A_WL<56> A_WL<55> A_WL<54> A_WL<53> A_WL<52> A_WL<51> A_WL<50> A_WL<49> A_WL<48> B_WL<63> B_WL<62> B_WL<61> B_WL<60> B_WL<59> B_WL<58> B_WL<57> B_WL<56> B_WL<55> B_WL<54> B_WL<53> B_WL<52> B_WL<51> B_WL<50> B_WL<49> B_WL<48> VDD_CORE VSS / RM_IHPSG13_256x8_c2_2P_BITKIT_16x2_EDGE_LR +XRAMEDGE_L<2> A_WL<47> A_WL<46> A_WL<45> A_WL<44> A_WL<43> A_WL<42> A_WL<41> A_WL<40> A_WL<39> A_WL<38> A_WL<37> A_WL<36> A_WL<35> A_WL<34> A_WL<33> A_WL<32> B_WL<47> B_WL<46> B_WL<45> B_WL<44> B_WL<43> B_WL<42> B_WL<41> B_WL<40> B_WL<39> B_WL<38> B_WL<37> B_WL<36> B_WL<35> B_WL<34> B_WL<33> B_WL<32> VDD_CORE VSS / RM_IHPSG13_256x8_c2_2P_BITKIT_16x2_EDGE_LR +XRAMEDGE_L<1> A_WL<31> A_WL<30> A_WL<29> A_WL<28> A_WL<27> A_WL<26> A_WL<25> A_WL<24> A_WL<23> A_WL<22> A_WL<21> A_WL<20> A_WL<19> A_WL<18> A_WL<17> A_WL<16> B_WL<31> B_WL<30> B_WL<29> B_WL<28> B_WL<27> B_WL<26> B_WL<25> B_WL<24> B_WL<23> B_WL<22> B_WL<21> B_WL<20> B_WL<19> B_WL<18> B_WL<17> B_WL<16> VDD_CORE VSS / RM_IHPSG13_256x8_c2_2P_BITKIT_16x2_EDGE_LR +XRAMEDGE_L<0> A_WL<15> A_WL<14> A_WL<13> A_WL<12> A_WL<11> A_WL<10> A_WL<9> A_WL<8> A_WL<7> A_WL<6> A_WL<5> A_WL<4> A_WL<3> A_WL<2> A_WL<1> A_WL<0> B_WL<15> B_WL<14> B_WL<13> B_WL<12> B_WL<11> B_WL<10> B_WL<9> B_WL<8> B_WL<7> B_WL<6> B_WL<5> B_WL<4> B_WL<3> B_WL<2> B_WL<1> B_WL<0> VDD_CORE VSS / RM_IHPSG13_256x8_c2_2P_BITKIT_16x2_EDGE_LR +XRAMEDGE_R<3> A_IWL<511> A_IWL<510> A_IWL<509> A_IWL<508> A_IWL<507> A_IWL<506> A_IWL<505> A_IWL<504> A_IWL<503> A_IWL<502> A_IWL<501> A_IWL<500> A_IWL<499> A_IWL<498> A_IWL<497> A_IWL<496> B_IWL<511> B_IWL<510> B_IWL<509> B_IWL<508> B_IWL<507> B_IWL<506> B_IWL<505> B_IWL<504> B_IWL<503> B_IWL<502> B_IWL<501> B_IWL<500> B_IWL<499> B_IWL<498> B_IWL<497> B_IWL<496> VDD_CORE VSS / RM_IHPSG13_256x8_c2_2P_BITKIT_16x2_EDGE_LR +XRAMEDGE_R<2> A_IWL<495> A_IWL<494> A_IWL<493> A_IWL<492> A_IWL<491> A_IWL<490> A_IWL<489> A_IWL<488> A_IWL<487> A_IWL<486> A_IWL<485> A_IWL<484> A_IWL<483> A_IWL<482> A_IWL<481> A_IWL<480> B_IWL<495> B_IWL<494> B_IWL<493> B_IWL<492> B_IWL<491> B_IWL<490> B_IWL<489> B_IWL<488> B_IWL<487> B_IWL<486> B_IWL<485> B_IWL<484> B_IWL<483> B_IWL<482> B_IWL<481> B_IWL<480> VDD_CORE VSS / RM_IHPSG13_256x8_c2_2P_BITKIT_16x2_EDGE_LR +XRAMEDGE_R<1> A_IWL<479> A_IWL<478> A_IWL<477> A_IWL<476> A_IWL<475> A_IWL<474> A_IWL<473> A_IWL<472> A_IWL<471> A_IWL<470> A_IWL<469> A_IWL<468> A_IWL<467> A_IWL<466> A_IWL<465> A_IWL<464> B_IWL<479> B_IWL<478> B_IWL<477> B_IWL<476> B_IWL<475> B_IWL<474> B_IWL<473> B_IWL<472> B_IWL<471> B_IWL<470> B_IWL<469> B_IWL<468> B_IWL<467> B_IWL<466> B_IWL<465> B_IWL<464> VDD_CORE VSS / RM_IHPSG13_256x8_c2_2P_BITKIT_16x2_EDGE_LR +XRAMEDGE_R<0> A_IWL<463> A_IWL<462> A_IWL<461> A_IWL<460> A_IWL<459> A_IWL<458> A_IWL<457> A_IWL<456> A_IWL<455> A_IWL<454> A_IWL<453> A_IWL<452> A_IWL<451> A_IWL<450> A_IWL<449> A_IWL<448> B_IWL<463> B_IWL<462> B_IWL<461> B_IWL<460> B_IWL<459> B_IWL<458> B_IWL<457> B_IWL<456> B_IWL<455> B_IWL<454> B_IWL<453> B_IWL<452> B_IWL<451> B_IWL<450> B_IWL<449> B_IWL<448> VDD_CORE VSS / RM_IHPSG13_256x8_c2_2P_BITKIT_16x2_EDGE_LR +XCOL<7> A_BLC<15> A_BLC<14> A_BLC_TOP<15> A_BLC_TOP<14> A_BLT<15> A_BLT<14> A_BLT_TOP<15> A_BLT_TOP<14> A_IWL<447> A_IWL<446> A_IWL<445> A_IWL<444> A_IWL<443> A_IWL<442> A_IWL<441> A_IWL<440> A_IWL<439> A_IWL<438> A_IWL<437> A_IWL<436> A_IWL<435> A_IWL<434> A_IWL<433> A_IWL<432> A_IWL<431> A_IWL<430> A_IWL<429> A_IWL<428> A_IWL<427> A_IWL<426> A_IWL<425> A_IWL<424> A_IWL<423> A_IWL<422> A_IWL<421> A_IWL<420> A_IWL<419> A_IWL<418> A_IWL<417> A_IWL<416> A_IWL<415> A_IWL<414> A_IWL<413> A_IWL<412> A_IWL<411> A_IWL<410> A_IWL<409> A_IWL<408> A_IWL<407> A_IWL<406> A_IWL<405> A_IWL<404> A_IWL<403> A_IWL<402> A_IWL<401> A_IWL<400> A_IWL<399> A_IWL<398> A_IWL<397> A_IWL<396> A_IWL<395> A_IWL<394> A_IWL<393> A_IWL<392> A_IWL<391> A_IWL<390> A_IWL<389> A_IWL<388> A_IWL<387> A_IWL<386> A_IWL<385> A_IWL<384> A_IWL<511> A_IWL<510> A_IWL<509> A_IWL<508> A_IWL<507> A_IWL<506> A_IWL<505> A_IWL<504> A_IWL<503> A_IWL<502> A_IWL<501> A_IWL<500> A_IWL<499> A_IWL<498> A_IWL<497> A_IWL<496> A_IWL<495> A_IWL<494> A_IWL<493> A_IWL<492> A_IWL<491> A_IWL<490> A_IWL<489> A_IWL<488> A_IWL<487> A_IWL<486> A_IWL<485> A_IWL<484> A_IWL<483> A_IWL<482> A_IWL<481> A_IWL<480> A_IWL<479> A_IWL<478> A_IWL<477> A_IWL<476> A_IWL<475> A_IWL<474> A_IWL<473> A_IWL<472> A_IWL<471> A_IWL<470> A_IWL<469> A_IWL<468> A_IWL<467> A_IWL<466> A_IWL<465> A_IWL<464> A_IWL<463> A_IWL<462> A_IWL<461> A_IWL<460> A_IWL<459> A_IWL<458> A_IWL<457> A_IWL<456> A_IWL<455> A_IWL<454> A_IWL<453> A_IWL<452> A_IWL<451> A_IWL<450> A_IWL<449> A_IWL<448> B_BLC<15> B_BLC<14> B_BLC_TOP<15> B_BLC_TOP<14> B_BLT<15> B_BLT<14> B_BLT_TOP<15> B_BLT_TOP<14> B_IWL<447> B_IWL<446> B_IWL<445> B_IWL<444> B_IWL<443> B_IWL<442> B_IWL<441> B_IWL<440> B_IWL<439> B_IWL<438> B_IWL<437> B_IWL<436> B_IWL<435> B_IWL<434> B_IWL<433> B_IWL<432> B_IWL<431> B_IWL<430> B_IWL<429> B_IWL<428> B_IWL<427> B_IWL<426> B_IWL<425> B_IWL<424> B_IWL<423> B_IWL<422> B_IWL<421> B_IWL<420> B_IWL<419> B_IWL<418> B_IWL<417> B_IWL<416> B_IWL<415> B_IWL<414> B_IWL<413> B_IWL<412> B_IWL<411> B_IWL<410> B_IWL<409> B_IWL<408> B_IWL<407> B_IWL<406> B_IWL<405> B_IWL<404> B_IWL<403> B_IWL<402> B_IWL<401> B_IWL<400> B_IWL<399> B_IWL<398> B_IWL<397> B_IWL<396> B_IWL<395> B_IWL<394> B_IWL<393> B_IWL<392> B_IWL<391> B_IWL<390> B_IWL<389> B_IWL<388> B_IWL<387> B_IWL<386> B_IWL<385> B_IWL<384> B_IWL<511> B_IWL<510> B_IWL<509> B_IWL<508> B_IWL<507> B_IWL<506> B_IWL<505> B_IWL<504> B_IWL<503> B_IWL<502> B_IWL<501> B_IWL<500> B_IWL<499> B_IWL<498> B_IWL<497> B_IWL<496> B_IWL<495> B_IWL<494> B_IWL<493> B_IWL<492> B_IWL<491> B_IWL<490> B_IWL<489> B_IWL<488> B_IWL<487> B_IWL<486> B_IWL<485> B_IWL<484> B_IWL<483> B_IWL<482> B_IWL<481> B_IWL<480> B_IWL<479> B_IWL<478> B_IWL<477> B_IWL<476> B_IWL<475> B_IWL<474> B_IWL<473> B_IWL<472> B_IWL<471> B_IWL<470> B_IWL<469> B_IWL<468> B_IWL<467> B_IWL<466> B_IWL<465> B_IWL<464> B_IWL<463> B_IWL<462> B_IWL<461> B_IWL<460> B_IWL<459> B_IWL<458> B_IWL<457> B_IWL<456> B_IWL<455> B_IWL<454> B_IWL<453> B_IWL<452> B_IWL<451> B_IWL<450> B_IWL<449> B_IWL<448> VDD_CORE VSS / RM_IHPSG13_256x8_c2_2P_COLUMN_pcell_0 +XCOL<6> A_BLC<13> A_BLC<12> A_BLC_TOP<13> A_BLC_TOP<12> A_BLT<13> A_BLT<12> A_BLT_TOP<13> A_BLT_TOP<12> A_IWL<383> A_IWL<382> A_IWL<381> A_IWL<380> A_IWL<379> A_IWL<378> A_IWL<377> A_IWL<376> A_IWL<375> A_IWL<374> A_IWL<373> A_IWL<372> A_IWL<371> A_IWL<370> A_IWL<369> A_IWL<368> A_IWL<367> A_IWL<366> A_IWL<365> A_IWL<364> A_IWL<363> A_IWL<362> A_IWL<361> A_IWL<360> A_IWL<359> A_IWL<358> A_IWL<357> A_IWL<356> A_IWL<355> A_IWL<354> A_IWL<353> A_IWL<352> A_IWL<351> A_IWL<350> A_IWL<349> A_IWL<348> A_IWL<347> A_IWL<346> A_IWL<345> A_IWL<344> A_IWL<343> A_IWL<342> A_IWL<341> A_IWL<340> A_IWL<339> A_IWL<338> A_IWL<337> A_IWL<336> A_IWL<335> A_IWL<334> A_IWL<333> A_IWL<332> A_IWL<331> A_IWL<330> A_IWL<329> A_IWL<328> A_IWL<327> A_IWL<326> A_IWL<325> A_IWL<324> A_IWL<323> A_IWL<322> A_IWL<321> A_IWL<320> A_IWL<447> A_IWL<446> A_IWL<445> A_IWL<444> A_IWL<443> A_IWL<442> A_IWL<441> A_IWL<440> A_IWL<439> A_IWL<438> A_IWL<437> A_IWL<436> A_IWL<435> A_IWL<434> A_IWL<433> A_IWL<432> A_IWL<431> A_IWL<430> A_IWL<429> A_IWL<428> A_IWL<427> A_IWL<426> A_IWL<425> A_IWL<424> A_IWL<423> A_IWL<422> A_IWL<421> A_IWL<420> A_IWL<419> A_IWL<418> A_IWL<417> A_IWL<416> A_IWL<415> A_IWL<414> A_IWL<413> A_IWL<412> A_IWL<411> A_IWL<410> A_IWL<409> A_IWL<408> A_IWL<407> A_IWL<406> A_IWL<405> A_IWL<404> A_IWL<403> A_IWL<402> A_IWL<401> A_IWL<400> A_IWL<399> A_IWL<398> A_IWL<397> A_IWL<396> A_IWL<395> A_IWL<394> A_IWL<393> A_IWL<392> A_IWL<391> A_IWL<390> A_IWL<389> A_IWL<388> A_IWL<387> A_IWL<386> A_IWL<385> A_IWL<384> B_BLC<13> B_BLC<12> B_BLC_TOP<13> B_BLC_TOP<12> B_BLT<13> B_BLT<12> B_BLT_TOP<13> B_BLT_TOP<12> B_IWL<383> B_IWL<382> B_IWL<381> B_IWL<380> B_IWL<379> B_IWL<378> B_IWL<377> B_IWL<376> B_IWL<375> B_IWL<374> B_IWL<373> B_IWL<372> B_IWL<371> B_IWL<370> B_IWL<369> B_IWL<368> B_IWL<367> B_IWL<366> B_IWL<365> B_IWL<364> B_IWL<363> B_IWL<362> B_IWL<361> B_IWL<360> B_IWL<359> B_IWL<358> B_IWL<357> B_IWL<356> B_IWL<355> B_IWL<354> B_IWL<353> B_IWL<352> B_IWL<351> B_IWL<350> B_IWL<349> B_IWL<348> B_IWL<347> B_IWL<346> B_IWL<345> B_IWL<344> B_IWL<343> B_IWL<342> B_IWL<341> B_IWL<340> B_IWL<339> B_IWL<338> B_IWL<337> B_IWL<336> B_IWL<335> B_IWL<334> B_IWL<333> B_IWL<332> B_IWL<331> B_IWL<330> B_IWL<329> B_IWL<328> B_IWL<327> B_IWL<326> B_IWL<325> B_IWL<324> B_IWL<323> B_IWL<322> B_IWL<321> B_IWL<320> B_IWL<447> B_IWL<446> B_IWL<445> B_IWL<444> B_IWL<443> B_IWL<442> B_IWL<441> B_IWL<440> B_IWL<439> B_IWL<438> B_IWL<437> B_IWL<436> B_IWL<435> B_IWL<434> B_IWL<433> B_IWL<432> B_IWL<431> B_IWL<430> B_IWL<429> B_IWL<428> B_IWL<427> B_IWL<426> B_IWL<425> B_IWL<424> B_IWL<423> B_IWL<422> B_IWL<421> B_IWL<420> B_IWL<419> B_IWL<418> B_IWL<417> B_IWL<416> B_IWL<415> B_IWL<414> B_IWL<413> B_IWL<412> B_IWL<411> B_IWL<410> B_IWL<409> B_IWL<408> B_IWL<407> B_IWL<406> B_IWL<405> B_IWL<404> B_IWL<403> B_IWL<402> B_IWL<401> B_IWL<400> B_IWL<399> B_IWL<398> B_IWL<397> B_IWL<396> B_IWL<395> B_IWL<394> B_IWL<393> B_IWL<392> B_IWL<391> B_IWL<390> B_IWL<389> B_IWL<388> B_IWL<387> B_IWL<386> B_IWL<385> B_IWL<384> VDD_CORE VSS / RM_IHPSG13_256x8_c2_2P_COLUMN_pcell_0 +XCOL<5> A_BLC<11> A_BLC<10> A_BLC_TOP<11> A_BLC_TOP<10> A_BLT<11> A_BLT<10> A_BLT_TOP<11> A_BLT_TOP<10> A_IWL<319> A_IWL<318> A_IWL<317> A_IWL<316> A_IWL<315> A_IWL<314> A_IWL<313> A_IWL<312> A_IWL<311> A_IWL<310> A_IWL<309> A_IWL<308> A_IWL<307> A_IWL<306> A_IWL<305> A_IWL<304> A_IWL<303> A_IWL<302> A_IWL<301> A_IWL<300> A_IWL<299> A_IWL<298> A_IWL<297> A_IWL<296> A_IWL<295> A_IWL<294> A_IWL<293> A_IWL<292> A_IWL<291> A_IWL<290> A_IWL<289> A_IWL<288> A_IWL<287> A_IWL<286> A_IWL<285> A_IWL<284> A_IWL<283> A_IWL<282> A_IWL<281> A_IWL<280> A_IWL<279> A_IWL<278> A_IWL<277> A_IWL<276> A_IWL<275> A_IWL<274> A_IWL<273> A_IWL<272> A_IWL<271> A_IWL<270> A_IWL<269> A_IWL<268> A_IWL<267> A_IWL<266> A_IWL<265> A_IWL<264> A_IWL<263> A_IWL<262> A_IWL<261> A_IWL<260> A_IWL<259> A_IWL<258> A_IWL<257> A_IWL<256> A_IWL<383> A_IWL<382> A_IWL<381> A_IWL<380> A_IWL<379> A_IWL<378> A_IWL<377> A_IWL<376> A_IWL<375> A_IWL<374> A_IWL<373> A_IWL<372> A_IWL<371> A_IWL<370> A_IWL<369> A_IWL<368> A_IWL<367> A_IWL<366> A_IWL<365> A_IWL<364> A_IWL<363> A_IWL<362> A_IWL<361> A_IWL<360> A_IWL<359> A_IWL<358> A_IWL<357> A_IWL<356> A_IWL<355> A_IWL<354> A_IWL<353> A_IWL<352> A_IWL<351> A_IWL<350> A_IWL<349> A_IWL<348> A_IWL<347> A_IWL<346> A_IWL<345> A_IWL<344> A_IWL<343> A_IWL<342> A_IWL<341> A_IWL<340> A_IWL<339> A_IWL<338> A_IWL<337> A_IWL<336> A_IWL<335> A_IWL<334> A_IWL<333> A_IWL<332> A_IWL<331> A_IWL<330> A_IWL<329> A_IWL<328> A_IWL<327> A_IWL<326> A_IWL<325> A_IWL<324> A_IWL<323> A_IWL<322> A_IWL<321> A_IWL<320> B_BLC<11> B_BLC<10> B_BLC_TOP<11> B_BLC_TOP<10> B_BLT<11> B_BLT<10> B_BLT_TOP<11> B_BLT_TOP<10> B_IWL<319> B_IWL<318> B_IWL<317> B_IWL<316> B_IWL<315> B_IWL<314> B_IWL<313> B_IWL<312> B_IWL<311> B_IWL<310> B_IWL<309> B_IWL<308> B_IWL<307> B_IWL<306> B_IWL<305> B_IWL<304> B_IWL<303> B_IWL<302> B_IWL<301> B_IWL<300> B_IWL<299> B_IWL<298> B_IWL<297> B_IWL<296> B_IWL<295> B_IWL<294> B_IWL<293> B_IWL<292> B_IWL<291> B_IWL<290> B_IWL<289> B_IWL<288> B_IWL<287> B_IWL<286> B_IWL<285> B_IWL<284> B_IWL<283> B_IWL<282> B_IWL<281> B_IWL<280> B_IWL<279> B_IWL<278> B_IWL<277> B_IWL<276> B_IWL<275> B_IWL<274> B_IWL<273> B_IWL<272> B_IWL<271> B_IWL<270> B_IWL<269> B_IWL<268> B_IWL<267> B_IWL<266> B_IWL<265> B_IWL<264> B_IWL<263> B_IWL<262> B_IWL<261> B_IWL<260> B_IWL<259> B_IWL<258> B_IWL<257> B_IWL<256> B_IWL<383> B_IWL<382> B_IWL<381> B_IWL<380> B_IWL<379> B_IWL<378> B_IWL<377> B_IWL<376> B_IWL<375> B_IWL<374> B_IWL<373> B_IWL<372> B_IWL<371> B_IWL<370> B_IWL<369> B_IWL<368> B_IWL<367> B_IWL<366> B_IWL<365> B_IWL<364> B_IWL<363> B_IWL<362> B_IWL<361> B_IWL<360> B_IWL<359> B_IWL<358> B_IWL<357> B_IWL<356> B_IWL<355> B_IWL<354> B_IWL<353> B_IWL<352> B_IWL<351> B_IWL<350> B_IWL<349> B_IWL<348> B_IWL<347> B_IWL<346> B_IWL<345> B_IWL<344> B_IWL<343> B_IWL<342> B_IWL<341> B_IWL<340> B_IWL<339> B_IWL<338> B_IWL<337> B_IWL<336> B_IWL<335> B_IWL<334> B_IWL<333> B_IWL<332> B_IWL<331> B_IWL<330> B_IWL<329> B_IWL<328> B_IWL<327> B_IWL<326> B_IWL<325> B_IWL<324> B_IWL<323> B_IWL<322> B_IWL<321> B_IWL<320> VDD_CORE VSS / RM_IHPSG13_256x8_c2_2P_COLUMN_pcell_0 +XCOL<4> A_BLC<9> A_BLC<8> A_BLC_TOP<9> A_BLC_TOP<8> A_BLT<9> A_BLT<8> A_BLT_TOP<9> A_BLT_TOP<8> A_IWL<255> A_IWL<254> A_IWL<253> A_IWL<252> A_IWL<251> A_IWL<250> A_IWL<249> A_IWL<248> A_IWL<247> A_IWL<246> A_IWL<245> A_IWL<244> A_IWL<243> A_IWL<242> A_IWL<241> A_IWL<240> A_IWL<239> A_IWL<238> A_IWL<237> A_IWL<236> A_IWL<235> A_IWL<234> A_IWL<233> A_IWL<232> A_IWL<231> A_IWL<230> A_IWL<229> A_IWL<228> A_IWL<227> A_IWL<226> A_IWL<225> A_IWL<224> A_IWL<223> A_IWL<222> A_IWL<221> A_IWL<220> A_IWL<219> A_IWL<218> A_IWL<217> A_IWL<216> A_IWL<215> A_IWL<214> A_IWL<213> A_IWL<212> A_IWL<211> A_IWL<210> A_IWL<209> A_IWL<208> A_IWL<207> A_IWL<206> A_IWL<205> A_IWL<204> A_IWL<203> A_IWL<202> A_IWL<201> A_IWL<200> A_IWL<199> A_IWL<198> A_IWL<197> A_IWL<196> A_IWL<195> A_IWL<194> A_IWL<193> A_IWL<192> A_IWL<319> A_IWL<318> A_IWL<317> A_IWL<316> A_IWL<315> A_IWL<314> A_IWL<313> A_IWL<312> A_IWL<311> A_IWL<310> A_IWL<309> A_IWL<308> A_IWL<307> A_IWL<306> A_IWL<305> A_IWL<304> A_IWL<303> A_IWL<302> A_IWL<301> A_IWL<300> A_IWL<299> A_IWL<298> A_IWL<297> A_IWL<296> A_IWL<295> A_IWL<294> A_IWL<293> A_IWL<292> A_IWL<291> A_IWL<290> A_IWL<289> A_IWL<288> A_IWL<287> A_IWL<286> A_IWL<285> A_IWL<284> A_IWL<283> A_IWL<282> A_IWL<281> A_IWL<280> A_IWL<279> A_IWL<278> A_IWL<277> A_IWL<276> A_IWL<275> A_IWL<274> A_IWL<273> A_IWL<272> A_IWL<271> A_IWL<270> A_IWL<269> A_IWL<268> A_IWL<267> A_IWL<266> A_IWL<265> A_IWL<264> A_IWL<263> A_IWL<262> A_IWL<261> A_IWL<260> A_IWL<259> A_IWL<258> A_IWL<257> A_IWL<256> B_BLC<9> B_BLC<8> B_BLC_TOP<9> B_BLC_TOP<8> B_BLT<9> B_BLT<8> B_BLT_TOP<9> B_BLT_TOP<8> B_IWL<255> B_IWL<254> B_IWL<253> B_IWL<252> B_IWL<251> B_IWL<250> B_IWL<249> B_IWL<248> B_IWL<247> B_IWL<246> B_IWL<245> B_IWL<244> B_IWL<243> B_IWL<242> B_IWL<241> B_IWL<240> B_IWL<239> B_IWL<238> B_IWL<237> B_IWL<236> B_IWL<235> B_IWL<234> B_IWL<233> B_IWL<232> B_IWL<231> B_IWL<230> B_IWL<229> B_IWL<228> B_IWL<227> B_IWL<226> B_IWL<225> B_IWL<224> B_IWL<223> B_IWL<222> B_IWL<221> B_IWL<220> B_IWL<219> B_IWL<218> B_IWL<217> B_IWL<216> B_IWL<215> B_IWL<214> B_IWL<213> B_IWL<212> B_IWL<211> B_IWL<210> B_IWL<209> B_IWL<208> B_IWL<207> B_IWL<206> B_IWL<205> B_IWL<204> B_IWL<203> B_IWL<202> B_IWL<201> B_IWL<200> B_IWL<199> B_IWL<198> B_IWL<197> B_IWL<196> B_IWL<195> B_IWL<194> B_IWL<193> B_IWL<192> B_IWL<319> B_IWL<318> B_IWL<317> B_IWL<316> B_IWL<315> B_IWL<314> B_IWL<313> B_IWL<312> B_IWL<311> B_IWL<310> B_IWL<309> B_IWL<308> B_IWL<307> B_IWL<306> B_IWL<305> B_IWL<304> B_IWL<303> B_IWL<302> B_IWL<301> B_IWL<300> B_IWL<299> B_IWL<298> B_IWL<297> B_IWL<296> B_IWL<295> B_IWL<294> B_IWL<293> B_IWL<292> B_IWL<291> B_IWL<290> B_IWL<289> B_IWL<288> B_IWL<287> B_IWL<286> B_IWL<285> B_IWL<284> B_IWL<283> B_IWL<282> B_IWL<281> B_IWL<280> B_IWL<279> B_IWL<278> B_IWL<277> B_IWL<276> B_IWL<275> B_IWL<274> B_IWL<273> B_IWL<272> B_IWL<271> B_IWL<270> B_IWL<269> B_IWL<268> B_IWL<267> B_IWL<266> B_IWL<265> B_IWL<264> B_IWL<263> B_IWL<262> B_IWL<261> B_IWL<260> B_IWL<259> B_IWL<258> B_IWL<257> B_IWL<256> VDD_CORE VSS / RM_IHPSG13_256x8_c2_2P_COLUMN_pcell_0 +XCOL<3> A_BLC<7> A_BLC<6> A_BLC_TOP<7> A_BLC_TOP<6> A_BLT<7> A_BLT<6> A_BLT_TOP<7> A_BLT_TOP<6> A_IWL<191> A_IWL<190> A_IWL<189> A_IWL<188> A_IWL<187> A_IWL<186> A_IWL<185> A_IWL<184> A_IWL<183> A_IWL<182> A_IWL<181> A_IWL<180> A_IWL<179> A_IWL<178> A_IWL<177> A_IWL<176> A_IWL<175> A_IWL<174> A_IWL<173> A_IWL<172> A_IWL<171> A_IWL<170> A_IWL<169> A_IWL<168> A_IWL<167> A_IWL<166> A_IWL<165> A_IWL<164> A_IWL<163> A_IWL<162> A_IWL<161> A_IWL<160> A_IWL<159> A_IWL<158> A_IWL<157> A_IWL<156> A_IWL<155> A_IWL<154> A_IWL<153> A_IWL<152> A_IWL<151> A_IWL<150> A_IWL<149> A_IWL<148> A_IWL<147> A_IWL<146> A_IWL<145> A_IWL<144> A_IWL<143> A_IWL<142> A_IWL<141> A_IWL<140> A_IWL<139> A_IWL<138> A_IWL<137> A_IWL<136> A_IWL<135> A_IWL<134> A_IWL<133> A_IWL<132> A_IWL<131> A_IWL<130> A_IWL<129> A_IWL<128> A_IWL<255> A_IWL<254> A_IWL<253> A_IWL<252> A_IWL<251> A_IWL<250> A_IWL<249> A_IWL<248> A_IWL<247> A_IWL<246> A_IWL<245> A_IWL<244> A_IWL<243> A_IWL<242> A_IWL<241> A_IWL<240> A_IWL<239> A_IWL<238> A_IWL<237> A_IWL<236> A_IWL<235> A_IWL<234> A_IWL<233> A_IWL<232> A_IWL<231> A_IWL<230> A_IWL<229> A_IWL<228> A_IWL<227> A_IWL<226> A_IWL<225> A_IWL<224> A_IWL<223> A_IWL<222> A_IWL<221> A_IWL<220> A_IWL<219> A_IWL<218> A_IWL<217> A_IWL<216> A_IWL<215> A_IWL<214> A_IWL<213> A_IWL<212> A_IWL<211> A_IWL<210> A_IWL<209> A_IWL<208> A_IWL<207> A_IWL<206> A_IWL<205> A_IWL<204> A_IWL<203> A_IWL<202> A_IWL<201> A_IWL<200> A_IWL<199> A_IWL<198> A_IWL<197> A_IWL<196> A_IWL<195> A_IWL<194> A_IWL<193> A_IWL<192> B_BLC<7> B_BLC<6> B_BLC_TOP<7> B_BLC_TOP<6> B_BLT<7> B_BLT<6> B_BLT_TOP<7> B_BLT_TOP<6> B_IWL<191> B_IWL<190> B_IWL<189> B_IWL<188> B_IWL<187> B_IWL<186> B_IWL<185> B_IWL<184> B_IWL<183> B_IWL<182> B_IWL<181> B_IWL<180> B_IWL<179> B_IWL<178> B_IWL<177> B_IWL<176> B_IWL<175> B_IWL<174> B_IWL<173> B_IWL<172> B_IWL<171> B_IWL<170> B_IWL<169> B_IWL<168> B_IWL<167> B_IWL<166> B_IWL<165> B_IWL<164> B_IWL<163> B_IWL<162> B_IWL<161> B_IWL<160> B_IWL<159> B_IWL<158> B_IWL<157> B_IWL<156> B_IWL<155> B_IWL<154> B_IWL<153> B_IWL<152> B_IWL<151> B_IWL<150> B_IWL<149> B_IWL<148> B_IWL<147> B_IWL<146> B_IWL<145> B_IWL<144> B_IWL<143> B_IWL<142> B_IWL<141> B_IWL<140> B_IWL<139> B_IWL<138> B_IWL<137> B_IWL<136> B_IWL<135> B_IWL<134> B_IWL<133> B_IWL<132> B_IWL<131> B_IWL<130> B_IWL<129> B_IWL<128> B_IWL<255> B_IWL<254> B_IWL<253> B_IWL<252> B_IWL<251> B_IWL<250> B_IWL<249> B_IWL<248> B_IWL<247> B_IWL<246> B_IWL<245> B_IWL<244> B_IWL<243> B_IWL<242> B_IWL<241> B_IWL<240> B_IWL<239> B_IWL<238> B_IWL<237> B_IWL<236> B_IWL<235> B_IWL<234> B_IWL<233> B_IWL<232> B_IWL<231> B_IWL<230> B_IWL<229> B_IWL<228> B_IWL<227> B_IWL<226> B_IWL<225> B_IWL<224> B_IWL<223> B_IWL<222> B_IWL<221> B_IWL<220> B_IWL<219> B_IWL<218> B_IWL<217> B_IWL<216> B_IWL<215> B_IWL<214> B_IWL<213> B_IWL<212> B_IWL<211> B_IWL<210> B_IWL<209> B_IWL<208> B_IWL<207> B_IWL<206> B_IWL<205> B_IWL<204> B_IWL<203> B_IWL<202> B_IWL<201> B_IWL<200> B_IWL<199> B_IWL<198> B_IWL<197> B_IWL<196> B_IWL<195> B_IWL<194> B_IWL<193> B_IWL<192> VDD_CORE VSS / RM_IHPSG13_256x8_c2_2P_COLUMN_pcell_0 +XCOL<2> A_BLC<5> A_BLC<4> A_BLC_TOP<5> A_BLC_TOP<4> A_BLT<5> A_BLT<4> A_BLT_TOP<5> A_BLT_TOP<4> A_IWL<127> A_IWL<126> A_IWL<125> A_IWL<124> A_IWL<123> A_IWL<122> A_IWL<121> A_IWL<120> A_IWL<119> A_IWL<118> A_IWL<117> A_IWL<116> A_IWL<115> A_IWL<114> A_IWL<113> A_IWL<112> A_IWL<111> A_IWL<110> A_IWL<109> A_IWL<108> A_IWL<107> A_IWL<106> A_IWL<105> A_IWL<104> A_IWL<103> A_IWL<102> A_IWL<101> A_IWL<100> A_IWL<99> A_IWL<98> A_IWL<97> A_IWL<96> A_IWL<95> A_IWL<94> A_IWL<93> A_IWL<92> A_IWL<91> A_IWL<90> A_IWL<89> A_IWL<88> A_IWL<87> A_IWL<86> A_IWL<85> A_IWL<84> A_IWL<83> A_IWL<82> A_IWL<81> A_IWL<80> A_IWL<79> A_IWL<78> A_IWL<77> A_IWL<76> A_IWL<75> A_IWL<74> A_IWL<73> A_IWL<72> A_IWL<71> A_IWL<70> A_IWL<69> A_IWL<68> A_IWL<67> A_IWL<66> A_IWL<65> A_IWL<64> A_IWL<191> A_IWL<190> A_IWL<189> A_IWL<188> A_IWL<187> A_IWL<186> A_IWL<185> A_IWL<184> A_IWL<183> A_IWL<182> A_IWL<181> A_IWL<180> A_IWL<179> A_IWL<178> A_IWL<177> A_IWL<176> A_IWL<175> A_IWL<174> A_IWL<173> A_IWL<172> A_IWL<171> A_IWL<170> A_IWL<169> A_IWL<168> A_IWL<167> A_IWL<166> A_IWL<165> A_IWL<164> A_IWL<163> A_IWL<162> A_IWL<161> A_IWL<160> A_IWL<159> A_IWL<158> A_IWL<157> A_IWL<156> A_IWL<155> A_IWL<154> A_IWL<153> A_IWL<152> A_IWL<151> A_IWL<150> A_IWL<149> A_IWL<148> A_IWL<147> A_IWL<146> A_IWL<145> A_IWL<144> A_IWL<143> A_IWL<142> A_IWL<141> A_IWL<140> A_IWL<139> A_IWL<138> A_IWL<137> A_IWL<136> A_IWL<135> A_IWL<134> A_IWL<133> A_IWL<132> A_IWL<131> A_IWL<130> A_IWL<129> A_IWL<128> B_BLC<5> B_BLC<4> B_BLC_TOP<5> B_BLC_TOP<4> B_BLT<5> B_BLT<4> B_BLT_TOP<5> B_BLT_TOP<4> B_IWL<127> B_IWL<126> B_IWL<125> B_IWL<124> B_IWL<123> B_IWL<122> B_IWL<121> B_IWL<120> B_IWL<119> B_IWL<118> B_IWL<117> B_IWL<116> B_IWL<115> B_IWL<114> B_IWL<113> B_IWL<112> B_IWL<111> B_IWL<110> B_IWL<109> B_IWL<108> B_IWL<107> B_IWL<106> B_IWL<105> B_IWL<104> B_IWL<103> B_IWL<102> B_IWL<101> B_IWL<100> B_IWL<99> B_IWL<98> B_IWL<97> B_IWL<96> B_IWL<95> B_IWL<94> B_IWL<93> B_IWL<92> B_IWL<91> B_IWL<90> B_IWL<89> B_IWL<88> B_IWL<87> B_IWL<86> B_IWL<85> B_IWL<84> B_IWL<83> B_IWL<82> B_IWL<81> B_IWL<80> B_IWL<79> B_IWL<78> B_IWL<77> B_IWL<76> B_IWL<75> B_IWL<74> B_IWL<73> B_IWL<72> B_IWL<71> B_IWL<70> B_IWL<69> B_IWL<68> B_IWL<67> B_IWL<66> B_IWL<65> B_IWL<64> B_IWL<191> B_IWL<190> B_IWL<189> B_IWL<188> B_IWL<187> B_IWL<186> B_IWL<185> B_IWL<184> B_IWL<183> B_IWL<182> B_IWL<181> B_IWL<180> B_IWL<179> B_IWL<178> B_IWL<177> B_IWL<176> B_IWL<175> B_IWL<174> B_IWL<173> B_IWL<172> B_IWL<171> B_IWL<170> B_IWL<169> B_IWL<168> B_IWL<167> B_IWL<166> B_IWL<165> B_IWL<164> B_IWL<163> B_IWL<162> B_IWL<161> B_IWL<160> B_IWL<159> B_IWL<158> B_IWL<157> B_IWL<156> B_IWL<155> B_IWL<154> B_IWL<153> B_IWL<152> B_IWL<151> B_IWL<150> B_IWL<149> B_IWL<148> B_IWL<147> B_IWL<146> B_IWL<145> B_IWL<144> B_IWL<143> B_IWL<142> B_IWL<141> B_IWL<140> B_IWL<139> B_IWL<138> B_IWL<137> B_IWL<136> B_IWL<135> B_IWL<134> B_IWL<133> B_IWL<132> B_IWL<131> B_IWL<130> B_IWL<129> B_IWL<128> VDD_CORE VSS / RM_IHPSG13_256x8_c2_2P_COLUMN_pcell_0 +XCOL<1> A_BLC<3> A_BLC<2> A_BLC_TOP<3> A_BLC_TOP<2> A_BLT<3> A_BLT<2> A_BLT_TOP<3> A_BLT_TOP<2> A_IWL<63> A_IWL<62> A_IWL<61> A_IWL<60> A_IWL<59> A_IWL<58> A_IWL<57> A_IWL<56> A_IWL<55> A_IWL<54> A_IWL<53> A_IWL<52> A_IWL<51> A_IWL<50> A_IWL<49> A_IWL<48> A_IWL<47> A_IWL<46> A_IWL<45> A_IWL<44> A_IWL<43> A_IWL<42> A_IWL<41> A_IWL<40> A_IWL<39> A_IWL<38> A_IWL<37> A_IWL<36> A_IWL<35> A_IWL<34> A_IWL<33> A_IWL<32> A_IWL<31> A_IWL<30> A_IWL<29> A_IWL<28> A_IWL<27> A_IWL<26> A_IWL<25> A_IWL<24> A_IWL<23> A_IWL<22> A_IWL<21> A_IWL<20> A_IWL<19> A_IWL<18> A_IWL<17> A_IWL<16> A_IWL<15> A_IWL<14> A_IWL<13> A_IWL<12> A_IWL<11> A_IWL<10> A_IWL<9> A_IWL<8> A_IWL<7> A_IWL<6> A_IWL<5> A_IWL<4> A_IWL<3> A_IWL<2> A_IWL<1> A_IWL<0> A_IWL<127> A_IWL<126> A_IWL<125> A_IWL<124> A_IWL<123> A_IWL<122> A_IWL<121> A_IWL<120> A_IWL<119> A_IWL<118> A_IWL<117> A_IWL<116> A_IWL<115> A_IWL<114> A_IWL<113> A_IWL<112> A_IWL<111> A_IWL<110> A_IWL<109> A_IWL<108> A_IWL<107> A_IWL<106> A_IWL<105> A_IWL<104> A_IWL<103> A_IWL<102> A_IWL<101> A_IWL<100> A_IWL<99> A_IWL<98> A_IWL<97> A_IWL<96> A_IWL<95> A_IWL<94> A_IWL<93> A_IWL<92> A_IWL<91> A_IWL<90> A_IWL<89> A_IWL<88> A_IWL<87> A_IWL<86> A_IWL<85> A_IWL<84> A_IWL<83> A_IWL<82> A_IWL<81> A_IWL<80> A_IWL<79> A_IWL<78> A_IWL<77> A_IWL<76> A_IWL<75> A_IWL<74> A_IWL<73> A_IWL<72> A_IWL<71> A_IWL<70> A_IWL<69> A_IWL<68> A_IWL<67> A_IWL<66> A_IWL<65> A_IWL<64> B_BLC<3> B_BLC<2> B_BLC_TOP<3> B_BLC_TOP<2> B_BLT<3> B_BLT<2> B_BLT_TOP<3> B_BLT_TOP<2> B_IWL<63> B_IWL<62> B_IWL<61> B_IWL<60> B_IWL<59> B_IWL<58> B_IWL<57> B_IWL<56> B_IWL<55> B_IWL<54> B_IWL<53> B_IWL<52> B_IWL<51> B_IWL<50> B_IWL<49> B_IWL<48> B_IWL<47> B_IWL<46> B_IWL<45> B_IWL<44> B_IWL<43> B_IWL<42> B_IWL<41> B_IWL<40> B_IWL<39> B_IWL<38> B_IWL<37> B_IWL<36> B_IWL<35> B_IWL<34> B_IWL<33> B_IWL<32> B_IWL<31> B_IWL<30> B_IWL<29> B_IWL<28> B_IWL<27> B_IWL<26> B_IWL<25> B_IWL<24> B_IWL<23> B_IWL<22> B_IWL<21> B_IWL<20> B_IWL<19> B_IWL<18> B_IWL<17> B_IWL<16> B_IWL<15> B_IWL<14> B_IWL<13> B_IWL<12> B_IWL<11> B_IWL<10> B_IWL<9> B_IWL<8> B_IWL<7> B_IWL<6> B_IWL<5> B_IWL<4> B_IWL<3> B_IWL<2> B_IWL<1> B_IWL<0> B_IWL<127> B_IWL<126> B_IWL<125> B_IWL<124> B_IWL<123> B_IWL<122> B_IWL<121> B_IWL<120> B_IWL<119> B_IWL<118> B_IWL<117> B_IWL<116> B_IWL<115> B_IWL<114> B_IWL<113> B_IWL<112> B_IWL<111> B_IWL<110> B_IWL<109> B_IWL<108> B_IWL<107> B_IWL<106> B_IWL<105> B_IWL<104> B_IWL<103> B_IWL<102> B_IWL<101> B_IWL<100> B_IWL<99> B_IWL<98> B_IWL<97> B_IWL<96> B_IWL<95> B_IWL<94> B_IWL<93> B_IWL<92> B_IWL<91> B_IWL<90> B_IWL<89> B_IWL<88> B_IWL<87> B_IWL<86> B_IWL<85> B_IWL<84> B_IWL<83> B_IWL<82> B_IWL<81> B_IWL<80> B_IWL<79> B_IWL<78> B_IWL<77> B_IWL<76> B_IWL<75> B_IWL<74> B_IWL<73> B_IWL<72> B_IWL<71> B_IWL<70> B_IWL<69> B_IWL<68> B_IWL<67> B_IWL<66> B_IWL<65> B_IWL<64> VDD_CORE VSS / RM_IHPSG13_256x8_c2_2P_COLUMN_pcell_0 +XCOL<0> A_BLC<1> A_BLC<0> A_BLC_TOP<1> A_BLC_TOP<0> A_BLT<1> A_BLT<0> A_BLT_TOP<1> A_BLT_TOP<0> A_WL<63> A_WL<62> A_WL<61> A_WL<60> A_WL<59> A_WL<58> A_WL<57> A_WL<56> A_WL<55> A_WL<54> A_WL<53> A_WL<52> A_WL<51> A_WL<50> A_WL<49> A_WL<48> A_WL<47> A_WL<46> A_WL<45> A_WL<44> A_WL<43> A_WL<42> A_WL<41> A_WL<40> A_WL<39> A_WL<38> A_WL<37> A_WL<36> A_WL<35> A_WL<34> A_WL<33> A_WL<32> A_WL<31> A_WL<30> A_WL<29> A_WL<28> A_WL<27> A_WL<26> A_WL<25> A_WL<24> A_WL<23> A_WL<22> A_WL<21> A_WL<20> A_WL<19> A_WL<18> A_WL<17> A_WL<16> A_WL<15> A_WL<14> A_WL<13> A_WL<12> A_WL<11> A_WL<10> A_WL<9> A_WL<8> A_WL<7> A_WL<6> A_WL<5> A_WL<4> A_WL<3> A_WL<2> A_WL<1> A_WL<0> A_IWL<63> A_IWL<62> A_IWL<61> A_IWL<60> A_IWL<59> A_IWL<58> A_IWL<57> A_IWL<56> A_IWL<55> A_IWL<54> A_IWL<53> A_IWL<52> A_IWL<51> A_IWL<50> A_IWL<49> A_IWL<48> A_IWL<47> A_IWL<46> A_IWL<45> A_IWL<44> A_IWL<43> A_IWL<42> A_IWL<41> A_IWL<40> A_IWL<39> A_IWL<38> A_IWL<37> A_IWL<36> A_IWL<35> A_IWL<34> A_IWL<33> A_IWL<32> A_IWL<31> A_IWL<30> A_IWL<29> A_IWL<28> A_IWL<27> A_IWL<26> A_IWL<25> A_IWL<24> A_IWL<23> A_IWL<22> A_IWL<21> A_IWL<20> A_IWL<19> A_IWL<18> A_IWL<17> A_IWL<16> A_IWL<15> A_IWL<14> A_IWL<13> A_IWL<12> A_IWL<11> A_IWL<10> A_IWL<9> A_IWL<8> A_IWL<7> A_IWL<6> A_IWL<5> A_IWL<4> A_IWL<3> A_IWL<2> A_IWL<1> A_IWL<0> B_BLC<1> B_BLC<0> B_BLC_TOP<1> B_BLC_TOP<0> B_BLT<1> B_BLT<0> B_BLT_TOP<1> B_BLT_TOP<0> B_WL<63> B_WL<62> B_WL<61> B_WL<60> B_WL<59> B_WL<58> B_WL<57> B_WL<56> B_WL<55> B_WL<54> B_WL<53> B_WL<52> B_WL<51> B_WL<50> B_WL<49> B_WL<48> B_WL<47> B_WL<46> B_WL<45> B_WL<44> B_WL<43> B_WL<42> B_WL<41> B_WL<40> B_WL<39> B_WL<38> B_WL<37> B_WL<36> B_WL<35> B_WL<34> B_WL<33> B_WL<32> B_WL<31> B_WL<30> B_WL<29> B_WL<28> B_WL<27> B_WL<26> B_WL<25> B_WL<24> B_WL<23> B_WL<22> B_WL<21> B_WL<20> B_WL<19> B_WL<18> B_WL<17> B_WL<16> B_WL<15> B_WL<14> B_WL<13> B_WL<12> B_WL<11> B_WL<10> B_WL<9> B_WL<8> B_WL<7> B_WL<6> B_WL<5> B_WL<4> B_WL<3> B_WL<2> B_WL<1> B_WL<0> B_IWL<63> B_IWL<62> B_IWL<61> B_IWL<60> B_IWL<59> B_IWL<58> B_IWL<57> B_IWL<56> B_IWL<55> B_IWL<54> B_IWL<53> B_IWL<52> B_IWL<51> B_IWL<50> B_IWL<49> B_IWL<48> B_IWL<47> B_IWL<46> B_IWL<45> B_IWL<44> B_IWL<43> B_IWL<42> B_IWL<41> B_IWL<40> B_IWL<39> B_IWL<38> B_IWL<37> B_IWL<36> B_IWL<35> B_IWL<34> B_IWL<33> B_IWL<32> B_IWL<31> B_IWL<30> B_IWL<29> B_IWL<28> B_IWL<27> B_IWL<26> B_IWL<25> B_IWL<24> B_IWL<23> B_IWL<22> B_IWL<21> B_IWL<20> B_IWL<19> B_IWL<18> B_IWL<17> B_IWL<16> B_IWL<15> B_IWL<14> B_IWL<13> B_IWL<12> B_IWL<11> B_IWL<10> B_IWL<9> B_IWL<8> B_IWL<7> B_IWL<6> B_IWL<5> B_IWL<4> B_IWL<3> B_IWL<2> B_IWL<1> B_IWL<0> VDD_CORE VSS / RM_IHPSG13_256x8_c2_2P_COLUMN_pcell_0 +.ENDS + + + + +.SUBCKT RM_IHPSG13_256x8_c2_2P_DLY_pcell_2 A Z VDD VSS + XIDL D<9> Z VDD VSS / RSC_IHPSG13_CDLYX1 + XIDM<9> D<8> D<9> VDD VSS / RSC_IHPSG13_CDLYX1_DUMMY + XIDM<8> D<7> D<8> VDD VSS / RSC_IHPSG13_CDLYX1_DUMMY + XIDM<7> D<6> D<7> VDD VSS / RSC_IHPSG13_CDLYX1_DUMMY + XIDM<6> D<5> D<6> VDD VSS / RSC_IHPSG13_CDLYX1_DUMMY + XIDM<5> D<4> D<5> VDD VSS / RSC_IHPSG13_CDLYX1_DUMMY + XIDM<4> D<3> D<4> VDD VSS / RSC_IHPSG13_CDLYX1_DUMMY + XIDM<3> D<2> D<3> VDD VSS / RSC_IHPSG13_CDLYX1_DUMMY + XIDM<2> D<1> D<2> VDD VSS / RSC_IHPSG13_CDLYX1_DUMMY + XIDM<1> A D<1> VDD VSS / RSC_IHPSG13_CDLYX1_DUMMY +.ENDS + + +.SUBCKT RM_IHPSG13_256x8_c2_2P_DLY_pcell_3 A Z VDD VSS + XIDM<10> D<9> Z VDD VSS / RSC_IHPSG13_CDLYX1_DUMMY + XIDM<9> D<8> D<9> VDD VSS / RSC_IHPSG13_CDLYX1_DUMMY + XIDM<8> D<7> D<8> VDD VSS / RSC_IHPSG13_CDLYX1_DUMMY + XIDM<7> D<6> D<7> VDD VSS / RSC_IHPSG13_CDLYX1_DUMMY + XIDM<6> D<5> D<6> VDD VSS / RSC_IHPSG13_CDLYX1_DUMMY + XIDM<5> D<4> D<5> VDD VSS / RSC_IHPSG13_CDLYX1_DUMMY + XIDM<4> D<3> D<4> VDD VSS / RSC_IHPSG13_CDLYX1_DUMMY + XIDM<3> D<2> D<3> VDD VSS / RSC_IHPSG13_CDLYX1_DUMMY + XIDM<2> D<1> D<2> VDD VSS / RSC_IHPSG13_CDLYX1_DUMMY + XIDM<1> A D<1> VDD VSS / RSC_IHPSG13_CDLYX1_DUMMY +.ENDS + + + +.SUBCKT RM_IHPSG13_2P_256x8_c2_bm_bist A_ADDR<7> A_ADDR<6> A_ADDR<5> A_ADDR<4> A_ADDR<3> A_ADDR<2> A_ADDR<1> A_ADDR<0> A_BIST_ADDR<7> A_BIST_ADDR<6> A_BIST_ADDR<5> A_BIST_ADDR<4> A_BIST_ADDR<3> A_BIST_ADDR<2> A_BIST_ADDR<1> A_BIST_ADDR<0> A_BIST_BM<7> A_BIST_BM<6> A_BIST_BM<5> A_BIST_BM<4> A_BIST_BM<3> A_BIST_BM<2> A_BIST_BM<1> A_BIST_BM<0> A_BIST_CLK A_BIST_DIN<7> A_BIST_DIN<6> A_BIST_DIN<5> A_BIST_DIN<4> A_BIST_DIN<3> A_BIST_DIN<2> A_BIST_DIN<1> A_BIST_DIN<0> A_BIST_EN A_BIST_MEN A_BIST_REN A_BIST_WEN A_BM<7> A_BM<6> A_BM<5> A_BM<4> A_BM<3> A_BM<2> A_BM<1> A_BM<0> A_CLK A_DIN<7> A_DIN<6> A_DIN<5> A_DIN<4> A_DIN<3> A_DIN<2> A_DIN<1> A_DIN<0> A_DLY A_DOUT<7> A_DOUT<6> A_DOUT<5> A_DOUT<4> A_DOUT<3> A_DOUT<2> A_DOUT<1> A_DOUT<0> A_MEN A_REN A_WEN B_ADDR<7> B_ADDR<6> B_ADDR<5> B_ADDR<4> B_ADDR<3> B_ADDR<2> B_ADDR<1> B_ADDR<0> B_BIST_ADDR<7> B_BIST_ADDR<6> B_BIST_ADDR<5> B_BIST_ADDR<4> B_BIST_ADDR<3> B_BIST_ADDR<2> B_BIST_ADDR<1> B_BIST_ADDR<0> B_BIST_BM<7> B_BIST_BM<6> B_BIST_BM<5> B_BIST_BM<4> B_BIST_BM<3> B_BIST_BM<2> B_BIST_BM<1> B_BIST_BM<0> B_BIST_CLK B_BIST_DIN<7> B_BIST_DIN<6> B_BIST_DIN<5> B_BIST_DIN<4> B_BIST_DIN<3> B_BIST_DIN<2> B_BIST_DIN<1> B_BIST_DIN<0> B_BIST_EN B_BIST_MEN B_BIST_REN B_BIST_WEN B_BM<7> B_BM<6> B_BM<5> B_BM<4> B_BM<3> B_BM<2> B_BM<1> B_BM<0> B_CLK B_DIN<7> B_DIN<6> B_DIN<5> B_DIN<4> B_DIN<3> B_DIN<2> B_DIN<1> B_DIN<0> B_DLY B_DOUT<7> B_DOUT<6> B_DOUT<5> B_DOUT<4> B_DOUT<3> B_DOUT<2> B_DOUT<1> B_DOUT<0> B_MEN B_REN B_WEN VDD! VDDARRAY! VSS! + + +XRAM<1> a_blc_r<15> a_blc_r<14> a_blc_r<13> a_blc_r<12> a_blc_r<11> a_blc_r<10> a_blc_r<9> a_blc_r<8> a_blc_r<7> a_blc_r<6> a_blc_r<5> a_blc_r<4> a_blc_r<3> a_blc_r<2> a_blc_r<1> a_blc_r<0> a_blt_r<15> a_blt_r<14> a_blt_r<13> a_blt_r<12> a_blt_r<11> a_blt_r<10> a_blt_r<9> a_blt_r<8> a_blt_r<7> a_blt_r<6> a_blt_r<5> a_blt_r<4> a_blt_r<3> a_blt_r<2> a_blt_r<1> a_blt_r<0> a_wl_r<63> a_wl_r<62> a_wl_r<61> a_wl_r<60> a_wl_r<59> a_wl_r<58> a_wl_r<57> a_wl_r<56> a_wl_r<55> a_wl_r<54> a_wl_r<53> a_wl_r<52> a_wl_r<51> a_wl_r<50> a_wl_r<49> a_wl_r<48> a_wl_r<47> a_wl_r<46> a_wl_r<45> a_wl_r<44> a_wl_r<43> a_wl_r<42> a_wl_r<41> a_wl_r<40> a_wl_r<39> a_wl_r<38> a_wl_r<37> a_wl_r<36> a_wl_r<35> a_wl_r<34> a_wl_r<33> a_wl_r<32> a_wl_r<31> a_wl_r<30> a_wl_r<29> a_wl_r<28> a_wl_r<27> a_wl_r<26> a_wl_r<25> a_wl_r<24> a_wl_r<23> a_wl_r<22> a_wl_r<21> a_wl_r<20> a_wl_r<19> a_wl_r<18> a_wl_r<17> a_wl_r<16> a_wl_r<15> a_wl_r<14> a_wl_r<13> a_wl_r<12> a_wl_r<11> a_wl_r<10> a_wl_r<9> a_wl_r<8> a_wl_r<7> a_wl_r<6> a_wl_r<5> a_wl_r<4> a_wl_r<3> a_wl_r<2> a_wl_r<1> a_wl_r<0> b_blc_r<15> b_blc_r<14> b_blc_r<13> b_blc_r<12> b_blc_r<11> b_blc_r<10> b_blc_r<9> b_blc_r<8> b_blc_r<7> b_blc_r<6> b_blc_r<5> b_blc_r<4> b_blc_r<3> b_blc_r<2> b_blc_r<1> b_blc_r<0> b_blt_r<15> b_blt_r<14> b_blt_r<13> b_blt_r<12> b_blt_r<11> b_blt_r<10> b_blt_r<9> b_blt_r<8> b_blt_r<7> b_blt_r<6> b_blt_r<5> b_blt_r<4> b_blt_r<3> b_blt_r<2> b_blt_r<1> b_blt_r<0> b_wl_r<63> b_wl_r<62> b_wl_r<61> b_wl_r<60> b_wl_r<59> b_wl_r<58> b_wl_r<57> b_wl_r<56> b_wl_r<55> b_wl_r<54> b_wl_r<53> b_wl_r<52> b_wl_r<51> b_wl_r<50> b_wl_r<49> b_wl_r<48> b_wl_r<47> b_wl_r<46> b_wl_r<45> b_wl_r<44> b_wl_r<43> b_wl_r<42> b_wl_r<41> b_wl_r<40> b_wl_r<39> b_wl_r<38> b_wl_r<37> b_wl_r<36> b_wl_r<35> b_wl_r<34> b_wl_r<33> b_wl_r<32> b_wl_r<31> b_wl_r<30> b_wl_r<29> b_wl_r<28> b_wl_r<27> b_wl_r<26> b_wl_r<25> b_wl_r<24> b_wl_r<23> b_wl_r<22> b_wl_r<21> b_wl_r<20> b_wl_r<19> b_wl_r<18> b_wl_r<17> b_wl_r<16> b_wl_r<15> b_wl_r<14> b_wl_r<13> b_wl_r<12> b_wl_r<11> b_wl_r<10> b_wl_r<9> b_wl_r<8> b_wl_r<7> b_wl_r<6> b_wl_r<5> b_wl_r<4> b_wl_r<3> b_wl_r<2> b_wl_r<1> b_wl_r<0> VDDARRAY! VSS! / RM_IHPSG13_256x8_c2_2P_MATRIX_pcell_1 +XRAM<0> a_blc_l<15> a_blc_l<14> a_blc_l<13> a_blc_l<12> a_blc_l<11> a_blc_l<10> a_blc_l<9> a_blc_l<8> a_blc_l<7> a_blc_l<6> a_blc_l<5> a_blc_l<4> a_blc_l<3> a_blc_l<2> a_blc_l<1> a_blc_l<0> a_blt_l<15> a_blt_l<14> a_blt_l<13> a_blt_l<12> a_blt_l<11> a_blt_l<10> a_blt_l<9> a_blt_l<8> a_blt_l<7> a_blt_l<6> a_blt_l<5> a_blt_l<4> a_blt_l<3> a_blt_l<2> a_blt_l<1> a_blt_l<0> a_wl_l<63> a_wl_l<62> a_wl_l<61> a_wl_l<60> a_wl_l<59> a_wl_l<58> a_wl_l<57> a_wl_l<56> a_wl_l<55> a_wl_l<54> a_wl_l<53> a_wl_l<52> a_wl_l<51> a_wl_l<50> a_wl_l<49> a_wl_l<48> a_wl_l<47> a_wl_l<46> a_wl_l<45> a_wl_l<44> a_wl_l<43> a_wl_l<42> a_wl_l<41> a_wl_l<40> a_wl_l<39> a_wl_l<38> a_wl_l<37> a_wl_l<36> a_wl_l<35> a_wl_l<34> a_wl_l<33> a_wl_l<32> a_wl_l<31> a_wl_l<30> a_wl_l<29> a_wl_l<28> a_wl_l<27> a_wl_l<26> a_wl_l<25> a_wl_l<24> a_wl_l<23> a_wl_l<22> a_wl_l<21> a_wl_l<20> a_wl_l<19> a_wl_l<18> a_wl_l<17> a_wl_l<16> a_wl_l<15> a_wl_l<14> a_wl_l<13> a_wl_l<12> a_wl_l<11> a_wl_l<10> a_wl_l<9> a_wl_l<8> a_wl_l<7> a_wl_l<6> a_wl_l<5> a_wl_l<4> a_wl_l<3> a_wl_l<2> a_wl_l<1> a_wl_l<0> b_blc_l<15> b_blc_l<14> b_blc_l<13> b_blc_l<12> b_blc_l<11> b_blc_l<10> b_blc_l<9> b_blc_l<8> b_blc_l<7> b_blc_l<6> b_blc_l<5> b_blc_l<4> b_blc_l<3> b_blc_l<2> b_blc_l<1> b_blc_l<0> b_blt_l<15> b_blt_l<14> b_blt_l<13> b_blt_l<12> b_blt_l<11> b_blt_l<10> b_blt_l<9> b_blt_l<8> b_blt_l<7> b_blt_l<6> b_blt_l<5> b_blt_l<4> b_blt_l<3> b_blt_l<2> b_blt_l<1> b_blt_l<0> b_wl_l<63> b_wl_l<62> b_wl_l<61> b_wl_l<60> b_wl_l<59> b_wl_l<58> b_wl_l<57> b_wl_l<56> b_wl_l<55> b_wl_l<54> b_wl_l<53> b_wl_l<52> b_wl_l<51> b_wl_l<50> b_wl_l<49> b_wl_l<48> b_wl_l<47> b_wl_l<46> b_wl_l<45> b_wl_l<44> b_wl_l<43> b_wl_l<42> b_wl_l<41> b_wl_l<40> b_wl_l<39> b_wl_l<38> b_wl_l<37> b_wl_l<36> b_wl_l<35> b_wl_l<34> b_wl_l<33> b_wl_l<32> b_wl_l<31> b_wl_l<30> b_wl_l<29> b_wl_l<28> b_wl_l<27> b_wl_l<26> b_wl_l<25> b_wl_l<24> b_wl_l<23> b_wl_l<22> b_wl_l<21> b_wl_l<20> b_wl_l<19> b_wl_l<18> b_wl_l<17> b_wl_l<16> b_wl_l<15> b_wl_l<14> b_wl_l<13> b_wl_l<12> b_wl_l<11> b_wl_l<10> b_wl_l<9> b_wl_l<8> b_wl_l<7> b_wl_l<6> b_wl_l<5> b_wl_l<4> b_wl_l<3> b_wl_l<2> b_wl_l<1> b_wl_l<0> VDDARRAY! VSS! / RM_IHPSG13_256x8_c2_2P_MATRIX_pcell_1 + + +XB_COLDRV<1> b_addr_col<1> b_addr_col<0> b_addr_col_r<1> b_addr_col_r<0> b_addr_dec<7> b_addr_dec<6> b_addr_dec<5> b_addr_dec<4> b_addr_dec<3> b_addr_dec<2> b_addr_dec<1> b_addr_dec<0> b_addr_dec_r<7> b_addr_dec_r<6> b_addr_dec_r<5> b_addr_dec_r<4> b_addr_dec_r<3> b_addr_dec_r<2> b_addr_dec_r<1> b_addr_dec_r<0> b_dclk b_dclk_p_r<0> b_rclk b_rclk_p_r<0> b_wclk b_wclk_p_r<0> VDD! VSS! / RM_IHPSG13_256x8_c2_2P_COLDRV13X8 +XB_COLDRV<0> b_addr_col<1> b_addr_col<0> b_addr_col_l<1> b_addr_col_l<0> b_addr_dec<7> b_addr_dec<6> b_addr_dec<5> b_addr_dec<4> b_addr_dec<3> b_addr_dec<2> b_addr_dec<1> b_addr_dec<0> b_addr_dec_l<7> b_addr_dec_l<6> b_addr_dec_l<5> b_addr_dec_l<4> b_addr_dec_l<3> b_addr_dec_l<2> b_addr_dec_l<1> b_addr_dec_l<0> b_dclk b_dclk_p_l<0> b_rclk b_rclk_p_l<0> b_wclk b_wclk_p_l<0> VDD! VSS! / RM_IHPSG13_256x8_c2_2P_COLDRV13X8 +XA_COLDRV<1> a_addr_col<1> a_addr_col<0> a_addr_col_r<1> a_addr_col_r<0> a_addr_dec<7> a_addr_dec<6> a_addr_dec<5> a_addr_dec<4> a_addr_dec<3> a_addr_dec<2> a_addr_dec<1> a_addr_dec<0> a_addr_dec_r<7> a_addr_dec_r<6> a_addr_dec_r<5> a_addr_dec_r<4> a_addr_dec_r<3> a_addr_dec_r<2> a_addr_dec_r<1> a_addr_dec_r<0> a_dclk a_dclk_p_r<0> a_rclk a_rclk_p_r<0> a_wclk a_wclk_p_r<0> VDD! VSS! / RM_IHPSG13_256x8_c2_2P_COLDRV13X8 +XA_COLDRV<0> a_addr_col<1> a_addr_col<0> a_addr_col_l<1> a_addr_col_l<0> a_addr_dec<7> a_addr_dec<6> a_addr_dec<5> a_addr_dec<4> a_addr_dec<3> a_addr_dec<2> a_addr_dec<1> a_addr_dec<0> a_addr_dec_l<7> a_addr_dec_l<6> a_addr_dec_l<5> a_addr_dec_l<4> a_addr_dec_l<3> a_addr_dec_l<2> a_addr_dec_l<1> a_addr_dec_l<0> a_dclk a_dclk_p_l<0> a_rclk a_rclk_p_l<0> a_wclk a_wclk_p_l<0> VDD! VSS! / RM_IHPSG13_256x8_c2_2P_COLDRV13X8 + + +XB_WLDRV<7> b_wi<63> b_wi<62> b_wi<61> b_wi<60> b_wi<59> b_wi<58> b_wi<57> b_wi<56> b_wi<55> b_wi<54> b_wi<53> b_wi<52> b_wi<51> b_wi<50> b_wi<49> b_wi<48> b_wl_r<63> b_wl_r<62> b_wl_r<61> b_wl_r<60> b_wl_r<59> b_wl_r<58> b_wl_r<57> b_wl_r<56> b_wl_r<55> b_wl_r<54> b_wl_r<53> b_wl_r<52> b_wl_r<51> b_wl_r<50> b_wl_r<49> b_wl_r<48> VDD! VSS! / RM_IHPSG13_256x8_c2_2P_WLDRV16X8 +XB_WLDRV<6> b_wi<47> b_wi<46> b_wi<45> b_wi<44> b_wi<43> b_wi<42> b_wi<41> b_wi<40> b_wi<39> b_wi<38> b_wi<37> b_wi<36> b_wi<35> b_wi<34> b_wi<33> b_wi<32> b_wl_r<47> b_wl_r<46> b_wl_r<45> b_wl_r<44> b_wl_r<43> b_wl_r<42> b_wl_r<41> b_wl_r<40> b_wl_r<39> b_wl_r<38> b_wl_r<37> b_wl_r<36> b_wl_r<35> b_wl_r<34> b_wl_r<33> b_wl_r<32> VDD! VSS! / RM_IHPSG13_256x8_c2_2P_WLDRV16X8 +XB_WLDRV<5> b_wi<31> b_wi<30> b_wi<29> b_wi<28> b_wi<27> b_wi<26> b_wi<25> b_wi<24> b_wi<23> b_wi<22> b_wi<21> b_wi<20> b_wi<19> b_wi<18> b_wi<17> b_wi<16> b_wl_r<31> b_wl_r<30> b_wl_r<29> b_wl_r<28> b_wl_r<27> b_wl_r<26> b_wl_r<25> b_wl_r<24> b_wl_r<23> b_wl_r<22> b_wl_r<21> b_wl_r<20> b_wl_r<19> b_wl_r<18> b_wl_r<17> b_wl_r<16> VDD! VSS! / RM_IHPSG13_256x8_c2_2P_WLDRV16X8 +XB_WLDRV<4> b_wi<15> b_wi<14> b_wi<13> b_wi<12> b_wi<11> b_wi<10> b_wi<9> b_wi<8> b_wi<7> b_wi<6> b_wi<5> b_wi<4> b_wi<3> b_wi<2> b_wi<1> b_wi<0> b_wl_r<15> b_wl_r<14> b_wl_r<13> b_wl_r<12> b_wl_r<11> b_wl_r<10> b_wl_r<9> b_wl_r<8> b_wl_r<7> b_wl_r<6> b_wl_r<5> b_wl_r<4> b_wl_r<3> b_wl_r<2> b_wl_r<1> b_wl_r<0> VDD! VSS! / RM_IHPSG13_256x8_c2_2P_WLDRV16X8 +XB_WLDRV<3> b_wi<63> b_wi<62> b_wi<61> b_wi<60> b_wi<59> b_wi<58> b_wi<57> b_wi<56> b_wi<55> b_wi<54> b_wi<53> b_wi<52> b_wi<51> b_wi<50> b_wi<49> b_wi<48> b_wl_l<63> b_wl_l<62> b_wl_l<61> b_wl_l<60> b_wl_l<59> b_wl_l<58> b_wl_l<57> b_wl_l<56> b_wl_l<55> b_wl_l<54> b_wl_l<53> b_wl_l<52> b_wl_l<51> b_wl_l<50> b_wl_l<49> b_wl_l<48> VDD! VSS! / RM_IHPSG13_256x8_c2_2P_WLDRV16X8 +XB_WLDRV<2> b_wi<47> b_wi<46> b_wi<45> b_wi<44> b_wi<43> b_wi<42> b_wi<41> b_wi<40> b_wi<39> b_wi<38> b_wi<37> b_wi<36> b_wi<35> b_wi<34> b_wi<33> b_wi<32> b_wl_l<47> b_wl_l<46> b_wl_l<45> b_wl_l<44> b_wl_l<43> b_wl_l<42> b_wl_l<41> b_wl_l<40> b_wl_l<39> b_wl_l<38> b_wl_l<37> b_wl_l<36> b_wl_l<35> b_wl_l<34> b_wl_l<33> b_wl_l<32> VDD! VSS! / RM_IHPSG13_256x8_c2_2P_WLDRV16X8 +XB_WLDRV<1> b_wi<31> b_wi<30> b_wi<29> b_wi<28> b_wi<27> b_wi<26> b_wi<25> b_wi<24> b_wi<23> b_wi<22> b_wi<21> b_wi<20> b_wi<19> b_wi<18> b_wi<17> b_wi<16> b_wl_l<31> b_wl_l<30> b_wl_l<29> b_wl_l<28> b_wl_l<27> b_wl_l<26> b_wl_l<25> b_wl_l<24> b_wl_l<23> b_wl_l<22> b_wl_l<21> b_wl_l<20> b_wl_l<19> b_wl_l<18> b_wl_l<17> b_wl_l<16> VDD! VSS! / RM_IHPSG13_256x8_c2_2P_WLDRV16X8 +XB_WLDRV<0> b_wi<15> b_wi<14> b_wi<13> b_wi<12> b_wi<11> b_wi<10> b_wi<9> b_wi<8> b_wi<7> b_wi<6> b_wi<5> b_wi<4> b_wi<3> b_wi<2> b_wi<1> b_wi<0> b_wl_l<15> b_wl_l<14> b_wl_l<13> b_wl_l<12> b_wl_l<11> b_wl_l<10> b_wl_l<9> b_wl_l<8> b_wl_l<7> b_wl_l<6> b_wl_l<5> b_wl_l<4> b_wl_l<3> b_wl_l<2> b_wl_l<1> b_wl_l<0> VDD! VSS! / RM_IHPSG13_256x8_c2_2P_WLDRV16X8 +XA_WLDRV<7> a_wi<63> a_wi<62> a_wi<61> a_wi<60> a_wi<59> a_wi<58> a_wi<57> a_wi<56> a_wi<55> a_wi<54> a_wi<53> a_wi<52> a_wi<51> a_wi<50> a_wi<49> a_wi<48> a_wl_r<63> a_wl_r<62> a_wl_r<61> a_wl_r<60> a_wl_r<59> a_wl_r<58> a_wl_r<57> a_wl_r<56> a_wl_r<55> a_wl_r<54> a_wl_r<53> a_wl_r<52> a_wl_r<51> a_wl_r<50> a_wl_r<49> a_wl_r<48> VDD! VSS! / RM_IHPSG13_256x8_c2_2P_WLDRV16X8 +XA_WLDRV<6> a_wi<47> a_wi<46> a_wi<45> a_wi<44> a_wi<43> a_wi<42> a_wi<41> a_wi<40> a_wi<39> a_wi<38> a_wi<37> a_wi<36> a_wi<35> a_wi<34> a_wi<33> a_wi<32> a_wl_r<47> a_wl_r<46> a_wl_r<45> a_wl_r<44> a_wl_r<43> a_wl_r<42> a_wl_r<41> a_wl_r<40> a_wl_r<39> a_wl_r<38> a_wl_r<37> a_wl_r<36> a_wl_r<35> a_wl_r<34> a_wl_r<33> a_wl_r<32> VDD! VSS! / RM_IHPSG13_256x8_c2_2P_WLDRV16X8 +XA_WLDRV<5> a_wi<31> a_wi<30> a_wi<29> a_wi<28> a_wi<27> a_wi<26> a_wi<25> a_wi<24> a_wi<23> a_wi<22> a_wi<21> a_wi<20> a_wi<19> a_wi<18> a_wi<17> a_wi<16> a_wl_r<31> a_wl_r<30> a_wl_r<29> a_wl_r<28> a_wl_r<27> a_wl_r<26> a_wl_r<25> a_wl_r<24> a_wl_r<23> a_wl_r<22> a_wl_r<21> a_wl_r<20> a_wl_r<19> a_wl_r<18> a_wl_r<17> a_wl_r<16> VDD! VSS! / RM_IHPSG13_256x8_c2_2P_WLDRV16X8 +XA_WLDRV<4> a_wi<15> a_wi<14> a_wi<13> a_wi<12> a_wi<11> a_wi<10> a_wi<9> a_wi<8> a_wi<7> a_wi<6> a_wi<5> a_wi<4> a_wi<3> a_wi<2> a_wi<1> a_wi<0> a_wl_r<15> a_wl_r<14> a_wl_r<13> a_wl_r<12> a_wl_r<11> a_wl_r<10> a_wl_r<9> a_wl_r<8> a_wl_r<7> a_wl_r<6> a_wl_r<5> a_wl_r<4> a_wl_r<3> a_wl_r<2> a_wl_r<1> a_wl_r<0> VDD! VSS! / RM_IHPSG13_256x8_c2_2P_WLDRV16X8 +XA_WLDRV<3> a_wi<63> a_wi<62> a_wi<61> a_wi<60> a_wi<59> a_wi<58> a_wi<57> a_wi<56> a_wi<55> a_wi<54> a_wi<53> a_wi<52> a_wi<51> a_wi<50> a_wi<49> a_wi<48> a_wl_l<63> a_wl_l<62> a_wl_l<61> a_wl_l<60> a_wl_l<59> a_wl_l<58> a_wl_l<57> a_wl_l<56> a_wl_l<55> a_wl_l<54> a_wl_l<53> a_wl_l<52> a_wl_l<51> a_wl_l<50> a_wl_l<49> a_wl_l<48> VDD! VSS! / RM_IHPSG13_256x8_c2_2P_WLDRV16X8 +XA_WLDRV<2> a_wi<47> a_wi<46> a_wi<45> a_wi<44> a_wi<43> a_wi<42> a_wi<41> a_wi<40> a_wi<39> a_wi<38> a_wi<37> a_wi<36> a_wi<35> a_wi<34> a_wi<33> a_wi<32> a_wl_l<47> a_wl_l<46> a_wl_l<45> a_wl_l<44> a_wl_l<43> a_wl_l<42> a_wl_l<41> a_wl_l<40> a_wl_l<39> a_wl_l<38> a_wl_l<37> a_wl_l<36> a_wl_l<35> a_wl_l<34> a_wl_l<33> a_wl_l<32> VDD! VSS! / RM_IHPSG13_256x8_c2_2P_WLDRV16X8 +XA_WLDRV<1> a_wi<31> a_wi<30> a_wi<29> a_wi<28> a_wi<27> a_wi<26> a_wi<25> a_wi<24> a_wi<23> a_wi<22> a_wi<21> a_wi<20> a_wi<19> a_wi<18> a_wi<17> a_wi<16> a_wl_l<31> a_wl_l<30> a_wl_l<29> a_wl_l<28> a_wl_l<27> a_wl_l<26> a_wl_l<25> a_wl_l<24> a_wl_l<23> a_wl_l<22> a_wl_l<21> a_wl_l<20> a_wl_l<19> a_wl_l<18> a_wl_l<17> a_wl_l<16> VDD! VSS! / RM_IHPSG13_256x8_c2_2P_WLDRV16X8 +XA_WLDRV<0> a_wi<15> a_wi<14> a_wi<13> a_wi<12> a_wi<11> a_wi<10> a_wi<9> a_wi<8> a_wi<7> a_wi<6> a_wi<5> a_wi<4> a_wi<3> a_wi<2> a_wi<1> a_wi<0> a_wl_l<15> a_wl_l<14> a_wl_l<13> a_wl_l<12> a_wl_l<11> a_wl_l<10> a_wl_l<9> a_wl_l<8> a_wl_l<7> a_wl_l<6> a_wl_l<5> a_wl_l<4> a_wl_l<3> a_wl_l<2> a_wl_l<1> a_wl_l<0> VDD! VSS! / RM_IHPSG13_256x8_c2_2P_WLDRV16X8 + + +XB_CTRL b_aclk_n B_BIST_CLK B_BIST_MEN B_BIST_EN B_BIST_REN B_BIST_WEN b_tiel B_CLK B_MEN b_dclk b_eclk b_pulse_h b_pulse_l b_pulse b_rclk B_REN b_cs b_wclk B_WEN VDD! VSS! / RM_IHPSG13_256x8_c2_2P_CTRL +XA_CTRL a_aclk_n A_BIST_CLK A_BIST_MEN A_BIST_EN A_BIST_REN A_BIST_WEN a_tiel A_CLK A_MEN a_dclk a_eclk a_pulse_h a_pulse_l a_pulse a_rclk A_REN a_cs a_wclk A_WEN VDD! VSS! / RM_IHPSG13_256x8_c2_2P_CTRL + + +XB_ROWDEC b_addr_row<5> b_addr_row<4> b_addr_row<3> b_addr_row<2> b_addr_row<1> b_addr_row<0> b_cs b_eclk b_wi<63> b_wi<62> b_wi<61> b_wi<60> b_wi<59> b_wi<58> b_wi<57> b_wi<56> b_wi<55> b_wi<54> b_wi<53> b_wi<52> b_wi<51> b_wi<50> b_wi<49> b_wi<48> b_wi<47> b_wi<46> b_wi<45> b_wi<44> b_wi<43> b_wi<42> b_wi<41> b_wi<40> b_wi<39> b_wi<38> b_wi<37> b_wi<36> b_wi<35> b_wi<34> b_wi<33> b_wi<32> b_wi<31> b_wi<30> b_wi<29> b_wi<28> b_wi<27> b_wi<26> b_wi<25> b_wi<24> b_wi<23> b_wi<22> b_wi<21> b_wi<20> b_wi<19> b_wi<18> b_wi<17> b_wi<16> b_wi<15> b_wi<14> b_wi<13> b_wi<12> b_wi<11> b_wi<10> b_wi<9> b_wi<8> b_wi<7> b_wi<6> b_wi<5> b_wi<4> b_wi<3> b_wi<2> b_wi<1> b_wi<0> VDD! VSS! / RM_IHPSG13_256x8_c2_2P_ROWDEC6 +XA_ROWDEC a_addr_row<5> a_addr_row<4> a_addr_row<3> a_addr_row<2> a_addr_row<1> a_addr_row<0> a_cs a_eclk a_wi<63> a_wi<62> a_wi<61> a_wi<60> a_wi<59> a_wi<58> a_wi<57> a_wi<56> a_wi<55> a_wi<54> a_wi<53> a_wi<52> a_wi<51> a_wi<50> a_wi<49> a_wi<48> a_wi<47> a_wi<46> a_wi<45> a_wi<44> a_wi<43> a_wi<42> a_wi<41> a_wi<40> a_wi<39> a_wi<38> a_wi<37> a_wi<36> a_wi<35> a_wi<34> a_wi<33> a_wi<32> a_wi<31> a_wi<30> a_wi<29> a_wi<28> a_wi<27> a_wi<26> a_wi<25> a_wi<24> a_wi<23> a_wi<22> a_wi<21> a_wi<20> a_wi<19> a_wi<18> a_wi<17> a_wi<16> a_wi<15> a_wi<14> a_wi<13> a_wi<12> a_wi<11> a_wi<10> a_wi<9> a_wi<8> a_wi<7> a_wi<6> a_wi<5> a_wi<4> a_wi<3> a_wi<2> a_wi<1> a_wi<0> VDD! VSS! / RM_IHPSG13_256x8_c2_2P_ROWDEC6 +XB_ROWREG b_aclk_n B_ADDR<7> B_ADDR<6> B_ADDR<5> B_ADDR<4> B_ADDR<3> B_ADDR<2> b_addr_row<5> b_addr_row<4> b_addr_row<3> b_addr_row<2> b_addr_row<1> b_addr_row<0> B_BIST_ADDR<7> B_BIST_ADDR<6> B_BIST_ADDR<5> B_BIST_ADDR<4> B_BIST_ADDR<3> B_BIST_ADDR<2> B_BIST_EN VDD! VSS! / RM_IHPSG13_256x8_c2_2P_ROWREG6 +XA_ROWREG a_aclk_n A_ADDR<7> A_ADDR<6> A_ADDR<5> A_ADDR<4> A_ADDR<3> A_ADDR<2> a_addr_row<5> a_addr_row<4> a_addr_row<3> a_addr_row<2> a_addr_row<1> a_addr_row<0> A_BIST_ADDR<7> A_BIST_ADDR<6> A_BIST_ADDR<5> A_BIST_ADDR<4> A_BIST_ADDR<3> A_BIST_ADDR<2> A_BIST_EN VDD! VSS! / RM_IHPSG13_256x8_c2_2P_ROWREG6 +XB_COLDEC b_aclk_n B_ADDR<1> B_ADDR<0> b_addr_col<1> b_addr_col<0> b_addr_dec<7> b_addr_dec<6> b_addr_dec<5> b_addr_dec<4> b_addr_dec<3> b_addr_dec<2> b_addr_dec<1> b_addr_dec<0> B_BIST_ADDR<1> B_BIST_ADDR<0> B_BIST_EN VDD! VSS! / RM_IHPSG13_256x8_c2_2P_COLDEC2 +XA_COLDEC a_aclk_n A_ADDR<1> A_ADDR<0> a_addr_col<1> a_addr_col<0> a_addr_dec<7> a_addr_dec<6> a_addr_dec<5> a_addr_dec<4> a_addr_dec<3> a_addr_dec<2> a_addr_dec<1> a_addr_dec<0> A_BIST_ADDR<1> A_BIST_ADDR<0> A_BIST_EN VDD! VSS! / RM_IHPSG13_256x8_c2_2P_COLDEC2 + + +XB_DLYH b_pulse b_pulse_h VDD! VSS! / RM_IHPSG13_256x8_c2_2P_DLY_pcell_2 +XB_DLYL b_pulse_x b_pulse_l VDD! VSS! / RM_IHPSG13_256x8_c2_2P_DLY_pcell_3 +XA_DLYH a_pulse a_pulse_h VDD! VSS! / RM_IHPSG13_256x8_c2_2P_DLY_pcell_2 +XA_DLYL a_pulse_x a_pulse_l VDD! VSS! / RM_IHPSG13_256x8_c2_2P_DLY_pcell_3 +XB_DLYMUX b_pulse_h B_DLY b_pulse_x VDD! VSS! / RM_IHPSG13_256x8_c2_2P_DLY_MUX +XA_DLYMUX a_pulse_h A_DLY a_pulse_x VDD! VSS! / RM_IHPSG13_256x8_c2_2P_DLY_MUX + +XCOLCTRL<7> a_addr_dec_r<3> a_addr_dec_r<2> a_addr_dec_r<1> a_addr_dec_r<0> A_BIST_BM<7> A_BIST_DIN<7> A_BIST_EN a_blc_r<15> a_blc_r<14> a_blc_r<13> a_blc_r<12> a_blt_r<15> a_blt_r<14> a_blt_r<13> a_blt_r<12> A_BM<7> a_dclk_n_r<3> a_dclk_n_r<4> a_dclk_p_r<3> a_dclk_p_r<4> A_DOUT<7> A_DIN<7> a_rclk_n_r<3> a_rclk_n_r<4> a_rclk_p_r<3> a_rclk_p_r<4> a_tieh<7> a_wclk_n_r<3> a_wclk_n_r<4> a_wclk_p_r<3> a_wclk_p_r<4> b_addr_dec_r<3> b_addr_dec_r<2> b_addr_dec_r<1> b_addr_dec_r<0> B_BIST_BM<7> B_BIST_DIN<7> B_BIST_EN b_blc_r<15> b_blc_r<14> b_blc_r<13> b_blc_r<12> b_blt_r<15> b_blt_r<14> b_blt_r<13> b_blt_r<12> B_BM<7> b_dclk_n_r<3> b_dclk_n_r<4> b_dclk_p_r<3> b_dclk_p_r<4> B_DOUT<7> B_DIN<7> b_rclk_n_r<3> b_rclk_n_r<4> b_rclk_p_r<3> b_rclk_p_r<4> b_tieh<7> b_wclk_n_r<3> b_wclk_n_r<4> b_wclk_p_r<3> b_wclk_p_r<4> VDD! VSS! / RM_IHPSG13_256x8_c2_2P_COLCTRL2 +XCOLCTRL<6> a_addr_dec_r<3> a_addr_dec_r<2> a_addr_dec_r<1> a_addr_dec_r<0> A_BIST_BM<6> A_BIST_DIN<6> A_BIST_EN a_blc_r<11> a_blc_r<10> a_blc_r<9> a_blc_r<8> a_blt_r<11> a_blt_r<10> a_blt_r<9> a_blt_r<8> A_BM<6> a_dclk_n_r<2> a_dclk_n_r<3> a_dclk_p_r<2> a_dclk_p_r<3> A_DOUT<6> A_DIN<6> a_rclk_n_r<2> a_rclk_n_r<3> a_rclk_p_r<2> a_rclk_p_r<3> a_tieh<6> a_wclk_n_r<2> a_wclk_n_r<3> a_wclk_p_r<2> a_wclk_p_r<3> b_addr_dec_r<3> b_addr_dec_r<2> b_addr_dec_r<1> b_addr_dec_r<0> B_BIST_BM<6> B_BIST_DIN<6> B_BIST_EN b_blc_r<11> b_blc_r<10> b_blc_r<9> b_blc_r<8> b_blt_r<11> b_blt_r<10> b_blt_r<9> b_blt_r<8> B_BM<6> b_dclk_n_r<2> b_dclk_n_r<3> b_dclk_p_r<2> b_dclk_p_r<3> B_DOUT<6> B_DIN<6> b_rclk_n_r<2> b_rclk_n_r<3> b_rclk_p_r<2> b_rclk_p_r<3> b_tieh<6> b_wclk_n_r<2> b_wclk_n_r<3> b_wclk_p_r<2> b_wclk_p_r<3> VDD! VSS! / RM_IHPSG13_256x8_c2_2P_COLCTRL2 +XCOLCTRL<5> a_addr_dec_r<3> a_addr_dec_r<2> a_addr_dec_r<1> a_addr_dec_r<0> A_BIST_BM<5> A_BIST_DIN<5> A_BIST_EN a_blc_r<7> a_blc_r<6> a_blc_r<5> a_blc_r<4> a_blt_r<7> a_blt_r<6> a_blt_r<5> a_blt_r<4> A_BM<5> a_dclk_n_r<1> a_dclk_n_r<2> a_dclk_p_r<1> a_dclk_p_r<2> A_DOUT<5> A_DIN<5> a_rclk_n_r<1> a_rclk_n_r<2> a_rclk_p_r<1> a_rclk_p_r<2> a_tieh<5> a_wclk_n_r<1> a_wclk_n_r<2> a_wclk_p_r<1> a_wclk_p_r<2> b_addr_dec_r<3> b_addr_dec_r<2> b_addr_dec_r<1> b_addr_dec_r<0> B_BIST_BM<5> B_BIST_DIN<5> B_BIST_EN b_blc_r<7> b_blc_r<6> b_blc_r<5> b_blc_r<4> b_blt_r<7> b_blt_r<6> b_blt_r<5> b_blt_r<4> B_BM<5> b_dclk_n_r<1> b_dclk_n_r<2> b_dclk_p_r<1> b_dclk_p_r<2> B_DOUT<5> B_DIN<5> b_rclk_n_r<1> b_rclk_n_r<2> b_rclk_p_r<1> b_rclk_p_r<2> b_tieh<5> b_wclk_n_r<1> b_wclk_n_r<2> b_wclk_p_r<1> b_wclk_p_r<2> VDD! VSS! / RM_IHPSG13_256x8_c2_2P_COLCTRL2 +XCOLCTRL<4> a_addr_dec_r<3> a_addr_dec_r<2> a_addr_dec_r<1> a_addr_dec_r<0> A_BIST_BM<4> A_BIST_DIN<4> A_BIST_EN a_blc_r<3> a_blc_r<2> a_blc_r<1> a_blc_r<0> a_blt_r<3> a_blt_r<2> a_blt_r<1> a_blt_r<0> A_BM<4> a_dclk_n_r<0> a_dclk_n_r<1> a_dclk_p_r<0> a_dclk_p_r<1> A_DOUT<4> A_DIN<4> a_rclk_n_r<0> a_rclk_n_r<1> a_rclk_p_r<0> a_rclk_p_r<1> a_tieh<4> a_wclk_n_r<0> a_wclk_n_r<1> a_wclk_p_r<0> a_wclk_p_r<1> b_addr_dec_r<3> b_addr_dec_r<2> b_addr_dec_r<1> b_addr_dec_r<0> B_BIST_BM<4> B_BIST_DIN<4> B_BIST_EN b_blc_r<3> b_blc_r<2> b_blc_r<1> b_blc_r<0> b_blt_r<3> b_blt_r<2> b_blt_r<1> b_blt_r<0> B_BM<4> b_dclk_n_r<0> b_dclk_n_r<1> b_dclk_p_r<0> b_dclk_p_r<1> B_DOUT<4> B_DIN<4> b_rclk_n_r<0> b_rclk_n_r<1> b_rclk_p_r<0> b_rclk_p_r<1> b_tieh<4> b_wclk_n_r<0> b_wclk_n_r<1> b_wclk_p_r<0> b_wclk_p_r<1> VDD! VSS! / RM_IHPSG13_256x8_c2_2P_COLCTRL2 +XCOLCTRL<3> a_addr_dec_l<3> a_addr_dec_l<2> a_addr_dec_l<1> a_addr_dec_l<0> A_BIST_BM<0> A_BIST_DIN<0> A_BIST_EN a_blc_l<15> a_blc_l<14> a_blc_l<13> a_blc_l<12> a_blt_l<15> a_blt_l<14> a_blt_l<13> a_blt_l<12> A_BM<0> a_dclk_n_l<3> a_dclk_n_l<4> a_dclk_p_l<3> a_dclk_p_l<4> A_DOUT<0> A_DIN<0> a_rclk_n_l<3> a_rclk_n_l<4> a_rclk_p_l<3> a_rclk_p_l<4> a_tieh<0> a_wclk_n_l<3> a_wclk_n_l<4> a_wclk_p_l<3> a_wclk_p_l<4> b_addr_dec_l<3> b_addr_dec_l<2> b_addr_dec_l<1> b_addr_dec_l<0> B_BIST_BM<0> B_BIST_DIN<0> B_BIST_EN b_blc_l<15> b_blc_l<14> b_blc_l<13> b_blc_l<12> b_blt_l<15> b_blt_l<14> b_blt_l<13> b_blt_l<12> B_BM<0> b_dclk_n_l<3> b_dclk_n_l<4> b_dclk_p_l<3> b_dclk_p_l<4> B_DOUT<0> B_DIN<0> b_rclk_n_l<3> b_rclk_n_l<4> b_rclk_p_l<3> b_rclk_p_l<4> b_tieh<0> b_wclk_n_l<3> b_wclk_n_l<4> b_wclk_p_l<3> b_wclk_p_l<4> VDD! VSS! / RM_IHPSG13_256x8_c2_2P_COLCTRL2 +XCOLCTRL<2> a_addr_dec_l<3> a_addr_dec_l<2> a_addr_dec_l<1> a_addr_dec_l<0> A_BIST_BM<1> A_BIST_DIN<1> A_BIST_EN a_blc_l<11> a_blc_l<10> a_blc_l<9> a_blc_l<8> a_blt_l<11> a_blt_l<10> a_blt_l<9> a_blt_l<8> A_BM<1> a_dclk_n_l<2> a_dclk_n_l<3> a_dclk_p_l<2> a_dclk_p_l<3> A_DOUT<1> A_DIN<1> a_rclk_n_l<2> a_rclk_n_l<3> a_rclk_p_l<2> a_rclk_p_l<3> a_tieh<1> a_wclk_n_l<2> a_wclk_n_l<3> a_wclk_p_l<2> a_wclk_p_l<3> b_addr_dec_l<3> b_addr_dec_l<2> b_addr_dec_l<1> b_addr_dec_l<0> B_BIST_BM<1> B_BIST_DIN<1> B_BIST_EN b_blc_l<11> b_blc_l<10> b_blc_l<9> b_blc_l<8> b_blt_l<11> b_blt_l<10> b_blt_l<9> b_blt_l<8> B_BM<1> b_dclk_n_l<2> b_dclk_n_l<3> b_dclk_p_l<2> b_dclk_p_l<3> B_DOUT<1> B_DIN<1> b_rclk_n_l<2> b_rclk_n_l<3> b_rclk_p_l<2> b_rclk_p_l<3> b_tieh<1> b_wclk_n_l<2> b_wclk_n_l<3> b_wclk_p_l<2> b_wclk_p_l<3> VDD! VSS! / RM_IHPSG13_256x8_c2_2P_COLCTRL2 +XCOLCTRL<1> a_addr_dec_l<3> a_addr_dec_l<2> a_addr_dec_l<1> a_addr_dec_l<0> A_BIST_BM<2> A_BIST_DIN<2> A_BIST_EN a_blc_l<7> a_blc_l<6> a_blc_l<5> a_blc_l<4> a_blt_l<7> a_blt_l<6> a_blt_l<5> a_blt_l<4> A_BM<2> a_dclk_n_l<1> a_dclk_n_l<2> a_dclk_p_l<1> a_dclk_p_l<2> A_DOUT<2> A_DIN<2> a_rclk_n_l<1> a_rclk_n_l<2> a_rclk_p_l<1> a_rclk_p_l<2> a_tieh<2> a_wclk_n_l<1> a_wclk_n_l<2> a_wclk_p_l<1> a_wclk_p_l<2> b_addr_dec_l<3> b_addr_dec_l<2> b_addr_dec_l<1> b_addr_dec_l<0> B_BIST_BM<2> B_BIST_DIN<2> B_BIST_EN b_blc_l<7> b_blc_l<6> b_blc_l<5> b_blc_l<4> b_blt_l<7> b_blt_l<6> b_blt_l<5> b_blt_l<4> B_BM<2> b_dclk_n_l<1> b_dclk_n_l<2> b_dclk_p_l<1> b_dclk_p_l<2> B_DOUT<2> B_DIN<2> b_rclk_n_l<1> b_rclk_n_l<2> b_rclk_p_l<1> b_rclk_p_l<2> b_tieh<2> b_wclk_n_l<1> b_wclk_n_l<2> b_wclk_p_l<1> b_wclk_p_l<2> VDD! VSS! / RM_IHPSG13_256x8_c2_2P_COLCTRL2 +XCOLCTRL<0> a_addr_dec_l<3> a_addr_dec_l<2> a_addr_dec_l<1> a_addr_dec_l<0> A_BIST_BM<3> A_BIST_DIN<3> A_BIST_EN a_blc_l<3> a_blc_l<2> a_blc_l<1> a_blc_l<0> a_blt_l<3> a_blt_l<2> a_blt_l<1> a_blt_l<0> A_BM<3> a_dclk_n_l<0> a_dclk_n_l<1> a_dclk_p_l<0> a_dclk_p_l<1> A_DOUT<3> A_DIN<3> a_rclk_n_l<0> a_rclk_n_l<1> a_rclk_p_l<0> a_rclk_p_l<1> a_tieh<3> a_wclk_n_l<0> a_wclk_n_l<1> a_wclk_p_l<0> a_wclk_p_l<1> b_addr_dec_l<3> b_addr_dec_l<2> b_addr_dec_l<1> b_addr_dec_l<0> B_BIST_BM<3> B_BIST_DIN<3> B_BIST_EN b_blc_l<3> b_blc_l<2> b_blc_l<1> b_blc_l<0> b_blt_l<3> b_blt_l<2> b_blt_l<1> b_blt_l<0> B_BM<3> b_dclk_n_l<0> b_dclk_n_l<1> b_dclk_p_l<0> b_dclk_p_l<1> B_DOUT<3> B_DIN<3> b_rclk_n_l<0> b_rclk_n_l<1> b_rclk_p_l<0> b_rclk_p_l<1> b_tieh<3> b_wclk_n_l<0> b_wclk_n_l<1> b_wclk_p_l<0> b_wclk_p_l<1> VDD! VSS! / RM_IHPSG13_256x8_c2_2P_COLCTRL2 + + +XDRVFILL4<1> VDD! VSS! / RM_IHPSG13_256x8_c2_2P_COLDRV13_FILL4 +XDRVFILL4<2> VDD! VSS! / RM_IHPSG13_256x8_c2_2P_COLDRV13_FILL4 +XDRVFILL4<3> VDD! VSS! / RM_IHPSG13_256x8_c2_2P_COLDRV13_FILL4 +XDRVFILL4<4> VDD! VSS! / RM_IHPSG13_256x8_c2_2P_COLDRV13_FILL4 +XDRVFILL4<5> VDD! VSS! / RM_IHPSG13_256x8_c2_2P_COLDRV13_FILL4 +XDRVFILL4<6> VDD! VSS! / RM_IHPSG13_256x8_c2_2P_COLDRV13_FILL4 +XDRVFILL4<7> VDD! VSS! / RM_IHPSG13_256x8_c2_2P_COLDRV13_FILL4 +XDRVFILL4<8> VDD! VSS! / RM_IHPSG13_256x8_c2_2P_COLDRV13_FILL4 +XDRVFILL4<9> VDD! VSS! / RM_IHPSG13_256x8_c2_2P_COLDRV13_FILL4 +XDRVFILL4<10> VDD! VSS! / RM_IHPSG13_256x8_c2_2P_COLDRV13_FILL4 +XCOLFILL4<1> VDD! VSS! / RM_IHPSG13_256x8_c2_2P_COLDRV13_FILL4C2 +XCOLFILL4<2> VDD! VSS! / RM_IHPSG13_256x8_c2_2P_COLDRV13_FILL4C2 +XCOLFILL4<3> VDD! VSS! / RM_IHPSG13_256x8_c2_2P_COLDRV13_FILL4C2 +XCOLFILL4<4> VDD! VSS! / RM_IHPSG13_256x8_c2_2P_COLDRV13_FILL4C2 +XCOLFILL4<5> VDD! VSS! / RM_IHPSG13_256x8_c2_2P_COLDRV13_FILL4C2 +XCOLFILL4<6> VDD! VSS! / RM_IHPSG13_256x8_c2_2P_COLDRV13_FILL4C2 +XCOLFILL4<7> VDD! VSS! / RM_IHPSG13_256x8_c2_2P_COLDRV13_FILL4C2 +XCOLFILL4<8> VDD! VSS! / RM_IHPSG13_256x8_c2_2P_COLDRV13_FILL4C2 +XCOLFILL4<9> VDD! VSS! / RM_IHPSG13_256x8_c2_2P_COLDRV13_FILL4C2 +XCOLFILL4<10> VDD! VSS! / RM_IHPSG13_256x8_c2_2P_COLDRV13_FILL4C2 +XCOLFILL4<11> VDD! VSS! / RM_IHPSG13_256x8_c2_2P_COLDRV13_FILL4C2 +XCOLFILL4<12> VDD! VSS! / RM_IHPSG13_256x8_c2_2P_COLDRV13_FILL4C2 +XCOLFILL4<13> VDD! VSS! / RM_IHPSG13_256x8_c2_2P_COLDRV13_FILL4C2 +XCOLFILL4<14> VDD! VSS! / RM_IHPSG13_256x8_c2_2P_COLDRV13_FILL4C2 +XCOLFILL4<15> VDD! VSS! / RM_IHPSG13_256x8_c2_2P_COLDRV13_FILL4C2 +XCOLFILL4<16> VDD! VSS! / RM_IHPSG13_256x8_c2_2P_COLDRV13_FILL4C2 +XCOLFILL4<17> VDD! VSS! / RM_IHPSG13_256x8_c2_2P_COLDRV13_FILL4C2 +XCOLFILL4<18> VDD! VSS! / RM_IHPSG13_256x8_c2_2P_COLDRV13_FILL4C2 +XCOLFILL4<19> VDD! VSS! / RM_IHPSG13_256x8_c2_2P_COLDRV13_FILL4C2 +XCOLFILL4<20> VDD! VSS! / RM_IHPSG13_256x8_c2_2P_COLDRV13_FILL4C2 +XCOLFILL4<21> VDD! VSS! / RM_IHPSG13_256x8_c2_2P_COLDRV13_FILL4C2 +XCOLFILL4<22> VDD! VSS! / RM_IHPSG13_256x8_c2_2P_COLDRV13_FILL4C2 +XCOLFILL4<23> VDD! VSS! / RM_IHPSG13_256x8_c2_2P_COLDRV13_FILL4C2 +XCOLFILL4<24> VDD! VSS! / RM_IHPSG13_256x8_c2_2P_COLDRV13_FILL4C2 +.ENDS diff --git a/flow/platforms/ihp-sg13g2/cdl/RM_IHPSG13_2P_512x16_c2_bm_bist.cdl b/flow/platforms/ihp-sg13g2/cdl/RM_IHPSG13_2P_512x16_c2_bm_bist.cdl new file mode 100644 index 0000000000..3916da391e --- /dev/null +++ b/flow/platforms/ihp-sg13g2/cdl/RM_IHPSG13_2P_512x16_c2_bm_bist.cdl @@ -0,0 +1,6394 @@ +* ------------------------------------------------------ +* +* Copyright 2025 IHP PDK Authors +* +* Licensed under the Apache License, Version 2.0 (the "License"); +* you may not use this file except in compliance with the License. +* You may obtain a copy of the License at +* +* https://www.apache.org/licenses/LICENSE-2.0 +* +* Unless required by applicable law or agreed to in writing, software +* distributed under the License is distributed on an "AS IS" BASIS, +* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +* See the License for the specific language governing permissions and +* limitations under the License. +* +* Generated on Wed Aug 27 13:18:16 2025 +* +* ------------------------------------------------------ + +.SUBCKT RM_IHPSG13_512x16_c2_1P_BITKIT_CORNER NW PW VDD VSS +.ENDS +.SUBCKT RM_IHPSG13_512x16_c2_1P_BITKIT_16x2_CORNER VDD_CORE VSS +XI16 VDD_CORE VSS VDD_CORE VSS / ++ RM_IHPSG13_512x16_c2_1P_BITKIT_CORNER +.ENDS +.SUBCKT RM_IHPSG13_512x16_c2_1P_BITKIT_EDGE_LR LWL NW PW VDD VSS +MN1 VSS LWL VSS VSS sg13_lv_nmos m=1 w=300.0n l=130.00n ng=1 nrd=0 nrs=0 +MN0 VSS net9 VSS VSS sg13_lv_nmos m=1 w=300.0n l=130.00n ng=1 nrd=0 nrs=0 +.ENDS +.SUBCKT RM_IHPSG13_512x16_c2_1P_BITKIT_16x2_EDGE_LR A_WL<15> A_WL<14> A_WL<13> A_WL<12> ++ A_WL<11> A_WL<10> A_WL<9> A_WL<8> A_WL<7> A_WL<6> A_WL<5> A_WL<4> A_WL<3> ++ A_WL<2> A_WL<1> A_WL<0> VDD_CORE VSS +XI0<15> A_WL<15> VDD_CORE VSS VDD_CORE VSS / ++ RM_IHPSG13_512x16_c2_1P_BITKIT_EDGE_LR +XI0<14> A_WL<14> VDD_CORE VSS VDD_CORE VSS / ++ RM_IHPSG13_512x16_c2_1P_BITKIT_EDGE_LR +XI0<13> A_WL<13> VDD_CORE VSS VDD_CORE VSS / ++ RM_IHPSG13_512x16_c2_1P_BITKIT_EDGE_LR +XI0<12> A_WL<12> VDD_CORE VSS VDD_CORE VSS / ++ RM_IHPSG13_512x16_c2_1P_BITKIT_EDGE_LR +XI0<11> A_WL<11> VDD_CORE VSS VDD_CORE VSS / ++ RM_IHPSG13_512x16_c2_1P_BITKIT_EDGE_LR +XI0<10> A_WL<10> VDD_CORE VSS VDD_CORE VSS / ++ RM_IHPSG13_512x16_c2_1P_BITKIT_EDGE_LR +XI0<9> A_WL<9> VDD_CORE VSS VDD_CORE VSS / ++ RM_IHPSG13_512x16_c2_1P_BITKIT_EDGE_LR +XI0<8> A_WL<8> VDD_CORE VSS VDD_CORE VSS / ++ RM_IHPSG13_512x16_c2_1P_BITKIT_EDGE_LR +XI0<7> A_WL<7> VDD_CORE VSS VDD_CORE VSS / ++ RM_IHPSG13_512x16_c2_1P_BITKIT_EDGE_LR +XI0<6> A_WL<6> VDD_CORE VSS VDD_CORE VSS / ++ RM_IHPSG13_512x16_c2_1P_BITKIT_EDGE_LR +XI0<5> A_WL<5> VDD_CORE VSS VDD_CORE VSS / ++ RM_IHPSG13_512x16_c2_1P_BITKIT_EDGE_LR +XI0<4> A_WL<4> VDD_CORE VSS VDD_CORE VSS / ++ RM_IHPSG13_512x16_c2_1P_BITKIT_EDGE_LR +XI0<3> A_WL<3> VDD_CORE VSS VDD_CORE VSS / ++ RM_IHPSG13_512x16_c2_1P_BITKIT_EDGE_LR +XI0<2> A_WL<2> VDD_CORE VSS VDD_CORE VSS / ++ RM_IHPSG13_512x16_c2_1P_BITKIT_EDGE_LR +XI0<1> A_WL<1> VDD_CORE VSS VDD_CORE VSS / ++ RM_IHPSG13_512x16_c2_1P_BITKIT_EDGE_LR +XI0<0> A_WL<0> VDD_CORE VSS VDD_CORE VSS / ++ RM_IHPSG13_512x16_c2_1P_BITKIT_EDGE_LR +.ENDS +.SUBCKT RM_IHPSG13_512x16_c2_1P_BITKIT_CELL BLC_BOT BLC_TOP BLT_BOT BLT_TOP LWL NW PW ++ RWL VDD VSS +MN0 NC NT VSS PW sg13_lv_nmos m=1 w=300.0n l=130.00n ng=1 nrd=0 nrs=0 +MN1 NT NC VSS PW sg13_lv_nmos m=1 w=300.0n l=130.00n ng=1 nrd=0 nrs=0 +MN3 NC RWL BLC_TOP PW sg13_lv_nmos m=1 w=300.0n l=130.00n ng=1 nrd=0 nrs=0 +MN2 BLT_BOT LWL NT PW sg13_lv_nmos m=1 w=300.0n l=130.00n ng=1 nrd=0 nrs=0 +MP1 NT NC VDD NW sg13_lv_pmos m=1 w=150.00n l=130.00n ng=1 nrd=0 nrs=0 +MP0 NC NT VDD NW sg13_lv_pmos m=1 w=150.00n l=130.00n ng=1 nrd=0 nrs=0 +R1 BLC_BOT BLC_TOP lvsres w=2.6e-07 l=6e-07 +R0 BLT_BOT BLT_TOP lvsres w=2.6e-07 l=6e-07 +R2 RWL LWL lvsres w=2.6e-07 l=6e-07 +.ENDS +.SUBCKT RM_IHPSG13_512x16_c2_1P_BITKIT_16x2_SRAM A_BLC_BOT<1> A_BLC_BOT<0> A_BLC_TOP<1> ++ A_BLC_TOP<0> A_BLT_BOT<1> A_BLT_BOT<0> A_BLT_TOP<1> A_BLT_TOP<0> A_LWL<15> ++ A_LWL<14> A_LWL<13> A_LWL<12> A_LWL<11> A_LWL<10> A_LWL<9> A_LWL<8> A_LWL<7> ++ A_LWL<6> A_LWL<5> A_LWL<4> A_LWL<3> A_LWL<2> A_LWL<1> A_LWL<0> A_RWL<15> ++ A_RWL<14> A_RWL<13> A_RWL<12> A_RWL<11> A_RWL<10> A_RWL<9> A_RWL<8> A_RWL<7> ++ A_RWL<6> A_RWL<5> A_RWL<4> A_RWL<3> A_RWL<2> A_RWL<1> A_RWL<0> VDD_CORE ++ VSS +XCELL<31> A_BLC_TOP<1> A_RBLC<15> A_BLT_TOP<1> A_RBLT<15> A_RWL<15> ++ VDD_CORE VSS A_XWL<15> VDD_CORE VSS / ++ RM_IHPSG13_512x16_c2_1P_BITKIT_CELL +XCELL<30> A_RBLC<14> A_RBLC<15> A_RBLT<14> A_RBLT<15> A_RWL<14> VDD_CORE ++ VSS A_XWL<14> VDD_CORE VSS / RM_IHPSG13_512x16_c2_1P_BITKIT_CELL +XCELL<29> A_RBLC<14> A_RBLC<13> A_RBLT<14> A_RBLT<13> A_RWL<13> VDD_CORE ++ VSS A_XWL<13> VDD_CORE VSS / RM_IHPSG13_512x16_c2_1P_BITKIT_CELL +XCELL<28> A_RBLC<12> A_RBLC<13> A_RBLT<12> A_RBLT<13> A_RWL<12> VDD_CORE ++ VSS A_XWL<12> VDD_CORE VSS / RM_IHPSG13_512x16_c2_1P_BITKIT_CELL +XCELL<27> A_RBLC<12> A_RBLC<11> A_RBLT<12> A_RBLT<11> A_RWL<11> VDD_CORE ++ VSS A_XWL<11> VDD_CORE VSS / RM_IHPSG13_512x16_c2_1P_BITKIT_CELL +XCELL<26> A_RBLC<10> A_RBLC<11> A_RBLT<10> A_RBLT<11> A_RWL<10> VDD_CORE ++ VSS A_XWL<10> VDD_CORE VSS / RM_IHPSG13_512x16_c2_1P_BITKIT_CELL +XCELL<25> A_RBLC<10> A_RBLC<9> A_RBLT<10> A_RBLT<9> A_RWL<9> VDD_CORE ++ VSS A_XWL<9> VDD_CORE VSS / RM_IHPSG13_512x16_c2_1P_BITKIT_CELL +XCELL<24> A_RBLC<8> A_RBLC<9> A_RBLT<8> A_RBLT<9> A_RWL<8> VDD_CORE ++ VSS A_XWL<8> VDD_CORE VSS / RM_IHPSG13_512x16_c2_1P_BITKIT_CELL +XCELL<23> A_RBLC<8> A_RBLC<7> A_RBLT<8> A_RBLT<7> A_RWL<7> VDD_CORE ++ VSS A_XWL<7> VDD_CORE VSS / RM_IHPSG13_512x16_c2_1P_BITKIT_CELL +XCELL<22> A_RBLC<6> A_RBLC<7> A_RBLT<6> A_RBLT<7> A_RWL<6> VDD_CORE ++ VSS A_XWL<6> VDD_CORE VSS / RM_IHPSG13_512x16_c2_1P_BITKIT_CELL +XCELL<21> A_RBLC<6> A_RBLC<5> A_RBLT<6> A_RBLT<5> A_RWL<5> VDD_CORE ++ VSS A_XWL<5> VDD_CORE VSS / RM_IHPSG13_512x16_c2_1P_BITKIT_CELL +XCELL<20> A_RBLC<4> A_RBLC<5> A_RBLT<4> A_RBLT<5> A_RWL<4> VDD_CORE ++ VSS A_XWL<4> VDD_CORE VSS / RM_IHPSG13_512x16_c2_1P_BITKIT_CELL +XCELL<19> A_RBLC<4> A_RBLC<3> A_RBLT<4> A_RBLT<3> A_RWL<3> VDD_CORE ++ VSS A_XWL<3> VDD_CORE VSS / RM_IHPSG13_512x16_c2_1P_BITKIT_CELL +XCELL<18> A_RBLC<2> A_RBLC<3> A_RBLT<2> A_RBLT<3> A_RWL<2> VDD_CORE ++ VSS A_XWL<2> VDD_CORE VSS / RM_IHPSG13_512x16_c2_1P_BITKIT_CELL +XCELL<17> A_RBLC<2> A_RBLC<1> A_RBLT<2> A_RBLT<1> A_RWL<1> VDD_CORE ++ VSS A_XWL<1> VDD_CORE VSS / RM_IHPSG13_512x16_c2_1P_BITKIT_CELL +XCELL<16> A_BLC_BOT<1> A_RBLC<1> A_BLT_BOT<1> A_RBLT<1> A_RWL<0> VDD_CORE ++ VSS A_XWL<0> VDD_CORE VSS / RM_IHPSG13_512x16_c2_1P_BITKIT_CELL +XCELL<15> A_BLC_TOP<0> A_LBLC<15> A_BLT_TOP<0> A_LBLT<15> A_LWL<15> ++ VDD_CORE VSS A_XWL<15> VDD_CORE VSS / ++ RM_IHPSG13_512x16_c2_1P_BITKIT_CELL +XCELL<14> A_LBLC<14> A_LBLC<15> A_LBLT<14> A_LBLT<15> A_LWL<14> VDD_CORE ++ VSS A_XWL<14> VDD_CORE VSS / RM_IHPSG13_512x16_c2_1P_BITKIT_CELL +XCELL<13> A_LBLC<14> A_LBLC<13> A_LBLT<14> A_LBLT<13> A_LWL<13> VDD_CORE ++ VSS A_XWL<13> VDD_CORE VSS / RM_IHPSG13_512x16_c2_1P_BITKIT_CELL +XCELL<12> A_LBLC<12> A_LBLC<13> A_LBLT<12> A_LBLT<13> A_LWL<12> VDD_CORE ++ VSS A_XWL<12> VDD_CORE VSS / RM_IHPSG13_512x16_c2_1P_BITKIT_CELL +XCELL<11> A_LBLC<12> A_LBLC<11> A_LBLT<12> A_LBLT<11> A_LWL<11> VDD_CORE ++ VSS A_XWL<11> VDD_CORE VSS / RM_IHPSG13_512x16_c2_1P_BITKIT_CELL +XCELL<10> A_LBLC<10> A_LBLC<11> A_LBLT<10> A_LBLT<11> A_LWL<10> VDD_CORE ++ VSS A_XWL<10> VDD_CORE VSS / RM_IHPSG13_512x16_c2_1P_BITKIT_CELL +XCELL<9> A_LBLC<10> A_LBLC<9> A_LBLT<10> A_LBLT<9> A_LWL<9> VDD_CORE ++ VSS A_XWL<9> VDD_CORE VSS / RM_IHPSG13_512x16_c2_1P_BITKIT_CELL +XCELL<8> A_LBLC<8> A_LBLC<9> A_LBLT<8> A_LBLT<9> A_LWL<8> VDD_CORE ++ VSS A_XWL<8> VDD_CORE VSS / RM_IHPSG13_512x16_c2_1P_BITKIT_CELL +XCELL<7> A_LBLC<8> A_LBLC<7> A_LBLT<8> A_LBLT<7> A_LWL<7> VDD_CORE ++ VSS A_XWL<7> VDD_CORE VSS / RM_IHPSG13_512x16_c2_1P_BITKIT_CELL +XCELL<6> A_LBLC<6> A_LBLC<7> A_LBLT<6> A_LBLT<7> A_LWL<6> VDD_CORE ++ VSS A_XWL<6> VDD_CORE VSS / RM_IHPSG13_512x16_c2_1P_BITKIT_CELL +XCELL<5> A_LBLC<6> A_LBLC<5> A_LBLT<6> A_LBLT<5> A_LWL<5> VDD_CORE ++ VSS A_XWL<5> VDD_CORE VSS / RM_IHPSG13_512x16_c2_1P_BITKIT_CELL +XCELL<4> A_LBLC<4> A_LBLC<5> A_LBLT<4> A_LBLT<5> A_LWL<4> VDD_CORE ++ VSS A_XWL<4> VDD_CORE VSS / RM_IHPSG13_512x16_c2_1P_BITKIT_CELL +XCELL<3> A_LBLC<4> A_LBLC<3> A_LBLT<4> A_LBLT<3> A_LWL<3> VDD_CORE ++ VSS A_XWL<3> VDD_CORE VSS / RM_IHPSG13_512x16_c2_1P_BITKIT_CELL +XCELL<2> A_LBLC<2> A_LBLC<3> A_LBLT<2> A_LBLT<3> A_LWL<2> VDD_CORE ++ VSS A_XWL<2> VDD_CORE VSS / RM_IHPSG13_512x16_c2_1P_BITKIT_CELL +XCELL<1> A_LBLC<2> A_LBLC<1> A_LBLT<2> A_LBLT<1> A_LWL<1> VDD_CORE ++ VSS A_XWL<1> VDD_CORE VSS / RM_IHPSG13_512x16_c2_1P_BITKIT_CELL +XCELL<0> A_BLC_BOT<0> A_LBLC<1> A_BLT_BOT<0> A_LBLT<1> A_LWL<0> VDD_CORE ++ VSS A_XWL<0> VDD_CORE VSS / RM_IHPSG13_512x16_c2_1P_BITKIT_CELL +.ENDS +.SUBCKT RM_IHPSG13_512x16_c2_1P_BITKIT_EDGE_TB BLC BLT NW PW VDD VSS +.ENDS +.SUBCKT RM_IHPSG13_512x16_c2_1P_BITKIT_16x2_EDGE_TB A_BLC<1> A_BLC<0> A_BLT<1> A_BLT<0> ++ VDD_CORE VSS +XEDGE<1> A_BLC<1> A_BLT<1> VDD_CORE VSS VDD_CORE VSS ++ / RM_IHPSG13_512x16_c2_1P_BITKIT_EDGE_TB +XEDGE<0> A_BLC<0> A_BLT<0> VDD_CORE VSS VDD_CORE VSS ++ / RM_IHPSG13_512x16_c2_1P_BITKIT_EDGE_TB +.ENDS + +.SUBCKT RSC_IHPSG13_CBUFX4 A Z VDD VSS +MN0 net9 A VSS VSS sg13_lv_nmos m=1 w=705.000n l=130.00n ng=1 nrd=0 ++ nrs=0 +MN1 Z net9 VSS VSS sg13_lv_nmos m=1 w=1.41u l=130.00n ng=2 nrd=0 nrs=0 +MP0 net9 A VDD VDD sg13_lv_pmos m=1 w=1.62u l=130.00n ng=1 nrd=0 nrs=0 +MP1 Z net9 VDD VDD sg13_lv_pmos m=1 w=3.24u l=130.00n ng=2 nrd=0 nrs=0 +.ENDS +.SUBCKT RM_IHPSG13_512x16_c2_1P_COLDRV13X4 ADDR_COL_I<1> ADDR_COL_I<0> ADDR_COL_O<1> ++ ADDR_COL_O<0> ADDR_DEC_I<7> ADDR_DEC_I<6> ADDR_DEC_I<5> ADDR_DEC_I<4> ++ ADDR_DEC_I<3> ADDR_DEC_I<2> ADDR_DEC_I<1> ADDR_DEC_I<0> ADDR_DEC_O<7> ++ ADDR_DEC_O<6> ADDR_DEC_O<5> ADDR_DEC_O<4> ADDR_DEC_O<3> ADDR_DEC_O<2> ++ ADDR_DEC_O<1> ADDR_DEC_O<0> DCLK_I DCLK_O RCLK_I RCLK_O WCLK_I WCLK_O ++ VDD VSS +XADDR_COL_DRV<1> ADDR_COL_I<1> ADDR_COL_O<1> VDD VSS / ++ RSC_IHPSG13_CBUFX4 +XADDR_COL_DRV<0> ADDR_COL_I<0> ADDR_COL_O<0> VDD VSS / ++ RSC_IHPSG13_CBUFX4 +XADDR_DEC_DRV<7> ADDR_DEC_I<7> ADDR_DEC_O<7> VDD VSS / ++ RSC_IHPSG13_CBUFX4 +XADDR_DEC_DRV<6> ADDR_DEC_I<6> ADDR_DEC_O<6> VDD VSS / ++ RSC_IHPSG13_CBUFX4 +XADDR_DEC_DRV<5> ADDR_DEC_I<5> ADDR_DEC_O<5> VDD VSS / ++ RSC_IHPSG13_CBUFX4 +XADDR_DEC_DRV<4> ADDR_DEC_I<4> ADDR_DEC_O<4> VDD VSS / ++ RSC_IHPSG13_CBUFX4 +XADDR_DEC_DRV<3> ADDR_DEC_I<3> ADDR_DEC_O<3> VDD VSS / ++ RSC_IHPSG13_CBUFX4 +XADDR_DEC_DRV<2> ADDR_DEC_I<2> ADDR_DEC_O<2> VDD VSS / ++ RSC_IHPSG13_CBUFX4 +XADDR_DEC_DRV<1> ADDR_DEC_I<1> ADDR_DEC_O<1> VDD VSS / ++ RSC_IHPSG13_CBUFX4 +XADDR_DEC_DRV<0> ADDR_DEC_I<0> ADDR_DEC_O<0> VDD VSS / ++ RSC_IHPSG13_CBUFX4 +XDCLK_DRV DCLK_I DCLK_O VDD VSS / RSC_IHPSG13_CBUFX4 +XRCLK_DRV RCLK_I RCLK_O VDD VSS / RSC_IHPSG13_CBUFX4 +XWCLK_DRV WCLK_I WCLK_O VDD VSS / RSC_IHPSG13_CBUFX4 +.ENDS +.SUBCKT RSC_IHPSG13_WLDRVX4 A Z VDD VSS +MN1 Z net6 VSS VSS sg13_lv_nmos m=1 w=705.000n l=130.00n ng=1 nrd=0 ++ nrs=0 +MN0 net6 A VSS VSS sg13_lv_nmos m=1 w=900.0n l=130.00n ng=1 nrd=0 nrs=0 +MP1 Z net6 VDD VDD sg13_lv_pmos m=1 w=3.24u l=130.00n ng=2 nrd=0 nrs=0 +MP0 net6 A VDD VDD sg13_lv_pmos m=1 w=900.0n l=130.00n ng=1 nrd=0 nrs=0 +.ENDS +.SUBCKT RM_IHPSG13_512x16_c2_1P_WLDRV16X4 A<15> A<14> A<13> A<12> A<11> A<10> A<9> A<8> ++ A<7> A<6> A<5> A<4> A<3> A<2> A<1> A<0> Z<15> Z<14> Z<13> Z<12> Z<11> Z<10> ++ Z<9> Z<8> Z<7> Z<6> Z<5> Z<4> Z<3> Z<2> Z<1> Z<0> VDD VSS +XBUF<15> A<15> Z<15> VDD VSS / RSC_IHPSG13_WLDRVX4 +XBUF<14> A<14> Z<14> VDD VSS / RSC_IHPSG13_WLDRVX4 +XBUF<13> A<13> Z<13> VDD VSS / RSC_IHPSG13_WLDRVX4 +XBUF<12> A<12> Z<12> VDD VSS / RSC_IHPSG13_WLDRVX4 +XBUF<11> A<11> Z<11> VDD VSS / RSC_IHPSG13_WLDRVX4 +XBUF<10> A<10> Z<10> VDD VSS / RSC_IHPSG13_WLDRVX4 +XBUF<9> A<9> Z<9> VDD VSS / RSC_IHPSG13_WLDRVX4 +XBUF<8> A<8> Z<8> VDD VSS / RSC_IHPSG13_WLDRVX4 +XBUF<7> A<7> Z<7> VDD VSS / RSC_IHPSG13_WLDRVX4 +XBUF<6> A<6> Z<6> VDD VSS / RSC_IHPSG13_WLDRVX4 +XBUF<5> A<5> Z<5> VDD VSS / RSC_IHPSG13_WLDRVX4 +XBUF<4> A<4> Z<4> VDD VSS / RSC_IHPSG13_WLDRVX4 +XBUF<3> A<3> Z<3> VDD VSS / RSC_IHPSG13_WLDRVX4 +XBUF<2> A<2> Z<2> VDD VSS / RSC_IHPSG13_WLDRVX4 +XBUF<1> A<1> Z<1> VDD VSS / RSC_IHPSG13_WLDRVX4 +XBUF<0> A<0> Z<0> VDD VSS / RSC_IHPSG13_WLDRVX4 +.ENDS +.SUBCKT RSC_IHPSG13_FILLCAP8 VDD VSS +MN0 vss_r vdd_r VSS VSS sg13_lv_nmos m=1 w=4.98u l=130.00n ng=6 nrd=0 ++ nrs=0 +MP0 vdd_r vss_r VDD VDD sg13_lv_pmos m=1 w=6.48u l=385.000n ng=4 nrd=0 ++ nrs=0 +.ENDS +.SUBCKT RSC_IHPSG13_LHPQX2 CP D Q VDD VSS +MN3 QIN CPN net14 VSS sg13_lv_nmos m=1 w=480.00n l=130.00n ng=1 nrd=0 nrs=0 +MN2 net14 net10 VSS VSS sg13_lv_nmos m=1 w=480.00n l=130.00n ng=1 ++ nrd=0 nrs=0 +MN5 net21 D VSS VSS sg13_lv_nmos m=1 w=870.00n l=130.00n ng=1 nrd=0 ++ nrs=0 +MN6 QIN CP net21 VSS sg13_lv_nmos m=1 w=870.00n l=130.00n ng=1 nrd=0 nrs=0 +MN1 net10 QIN VSS VSS sg13_lv_nmos m=1 w=480.00n l=130.00n ng=1 nrd=0 ++ nrs=0 +MN0 CPN CP VSS VSS sg13_lv_nmos m=1 w=480.00n l=130.00n ng=1 nrd=0 ++ nrs=0 +MN4 Q QIN VSS VSS sg13_lv_nmos m=1 w=980.00n l=130.00n ng=1 nrd=0 nrs=0 +MP2 QIN CP net16 VDD sg13_lv_pmos m=1 w=480.00n l=130.00n ng=1 nrd=0 nrs=0 +MP0 CPN CP VDD VDD sg13_lv_pmos m=1 w=480.00n l=130.00n ng=1 nrd=0 ++ nrs=0 +MP4 Q QIN VDD VDD sg13_lv_pmos m=1 w=1.62u l=130.00n ng=1 nrd=0 nrs=0 +MP3 net10 QIN VDD VDD sg13_lv_pmos m=1 w=480.00n l=130.00n ng=1 nrd=0 ++ nrs=0 +MP1 net16 net10 VDD VDD sg13_lv_pmos m=1 w=480.00n l=130.00n ng=1 ++ nrd=0 nrs=0 +MP6 QIN CPN net20 VDD sg13_lv_pmos m=1 w=975.000n l=130.00n ng=1 nrd=0 ++ nrs=0 +MP5 net20 D VDD VDD sg13_lv_pmos m=1 w=975.000n l=130.00n ng=1 nrd=0 ++ nrs=0 +.ENDS +.SUBCKT RSC_IHPSG13_NAND2X2 A B Z VDD VSS +MP1 Z B VDD VDD sg13_lv_pmos m=1 w=1.62u l=130.00n ng=1 nrd=0 nrs=0 +MP0 Z A VDD VDD sg13_lv_pmos m=1 w=1.62u l=130.00n ng=1 nrd=0 nrs=0 +MN0 Z B net7 VSS sg13_lv_nmos m=1 w=980.00n l=130.00n ng=1 nrd=0 nrs=0 +MN1 net7 A VSS VSS sg13_lv_nmos m=1 w=980.00n l=130.00n ng=1 nrd=0 ++ nrs=0 +.ENDS +.SUBCKT RSC_IHPSG13_CINVX4 A Z VDD VSS +MN0 Z A VSS VSS sg13_lv_nmos m=1 w=1.41u l=130.00n ng=2 nrd=0 nrs=0 +MP0 Z A VDD VDD sg13_lv_pmos m=1 w=3.24u l=130.00n ng=2 nrd=0 nrs=0 +.ENDS +.SUBCKT RSC_IHPSG13_CINVX2 A Z VDD VSS +MN0 Z A VSS VSS sg13_lv_nmos m=1 w=705.000n l=130.00n ng=1 nrd=0 nrs=0 +MP0 Z A VDD VDD sg13_lv_pmos m=1 w=1.62u l=130.00n ng=1 nrd=0 nrs=0 +.ENDS +.SUBCKT RSC_IHPSG13_INVX2 A Z VDD VSS +MN0 Z A VSS VSS sg13_lv_nmos m=1 w=980.00n l=130.00n ng=1 nrd=0 nrs=0 +MP0 Z A VDD VDD sg13_lv_pmos m=1 w=1.62u l=130.00n ng=1 nrd=0 nrs=0 +.ENDS +.SUBCKT RSC_IHPSG13_NAND3X2 A B C Z VDD VSS +MP2 Z A VDD VDD sg13_lv_pmos m=1 w=1.62u l=130.00n ng=1 nrd=0 nrs=0 +MP1 Z B VDD VDD sg13_lv_pmos m=1 w=1.62u l=130.00n ng=1 nrd=0 nrs=0 +MP0 Z C VDD VDD sg13_lv_pmos m=1 w=1.62u l=130.00n ng=1 nrd=0 nrs=0 +MN1 net12 B net16 VSS sg13_lv_nmos m=1 w=980.00n l=130.00n ng=1 nrd=0 nrs=0 +MN0 Z C net12 VSS sg13_lv_nmos m=1 w=980.00n l=130.00n ng=1 nrd=0 nrs=0 +MN2 net16 A VSS VSS sg13_lv_nmos m=1 w=980.00n l=130.00n ng=1 nrd=0 ++ nrs=0 +.ENDS +.SUBCKT RSC_IHPSG13_NOR3X2 A B C Z VDD VSS +MP0 net13 A VDD VDD sg13_lv_pmos m=1 w=1.62u l=130.00n ng=1 nrd=0 nrs=0 +MP2 Z C net10 VDD sg13_lv_pmos m=1 w=1.62u l=130.00n ng=1 nrd=0 nrs=0 +MP1 net10 B net13 VDD sg13_lv_pmos m=1 w=1.62u l=130.00n ng=1 nrd=0 nrs=0 +MN1 Z B VSS VSS sg13_lv_nmos m=1 w=875.000n l=130.00n ng=1 nrd=0 nrs=0 +MN0 Z C VSS VSS sg13_lv_nmos m=1 w=875.000n l=130.00n ng=1 nrd=0 nrs=0 +MN2 Z A VSS VSS sg13_lv_nmos m=1 w=875.000n l=130.00n ng=1 nrd=0 nrs=0 +.ENDS +.SUBCKT RSC_IHPSG13_FILLCAP4 VDD VSS +MN0 vss_r vdd_r VSS VSS sg13_lv_nmos m=1 w=2.49u l=130.00n ng=3 nrd=0 ++ nrs=0 +MP0 vdd_r vss_r VDD VDD sg13_lv_pmos m=1 w=3.24u l=385.000n ng=2 nrd=0 ++ nrs=0 +.ENDS +.SUBCKT RSC_IHPSG13_MET2RES A B +R0 B A lvsres w=2.6e-07 l=6e-07 +.ENDS +.SUBCKT RM_IHPSG13_512x16_c2_1P_DEC04 ADDR<3> ADDR<2> ADDR<1> ADDR<0> CS ECLK_H_BOT ++ ECLK_H_TOP ECLK_L_BOT ECLK_L_TOP WL<15> WL<14> WL<13> WL<12> WL<11> WL<10> ++ WL<9> WL<8> WL<7> WL<6> WL<5> WL<4> WL<3> WL<2> WL<1> WL<0> VDD VSS +XLATCH<3> CS ADDR<3> PADR<3> VDD VSS / RSC_IHPSG13_LHPQX2 +XLATCH<2> CS ADDR<2> PADR<2> VDD VSS / RSC_IHPSG13_LHPQX2 +XLATCH<1> CS ADDR<1> PADR<1> VDD VSS / RSC_IHPSG13_LHPQX2 +XLATCH<0> CS ADDR<0> PADR<0> VDD VSS / RSC_IHPSG13_LHPQX2 +XI0<3> PADR<1> PADR<0> sel01<3> VDD VSS / RSC_IHPSG13_NAND2X2 +XI0<2> PADR<1> NADR<0> sel01<2> VDD VSS / RSC_IHPSG13_NAND2X2 +XI0<1> NADR<1> PADR<0> sel01<1> VDD VSS / RSC_IHPSG13_NAND2X2 +XI0<0> NADR<1> NADR<0> sel01<0> VDD VSS / RSC_IHPSG13_NAND2X2 +XI4 ECLK_L_BOT EN VDD VSS / RSC_IHPSG13_CINVX4 +XI5 ECLK_H_BOT ECLK_L_BOT VDD VSS / RSC_IHPSG13_CINVX2 +XI3<3> PADR<3> NADR<3> VDD VSS / RSC_IHPSG13_INVX2 +XI3<2> PADR<2> NADR<2> VDD VSS / RSC_IHPSG13_INVX2 +XI3<1> PADR<1> NADR<1> VDD VSS / RSC_IHPSG13_INVX2 +XI3<0> PADR<0> NADR<0> VDD VSS / RSC_IHPSG13_INVX2 +XI1<3> PADR<2> PADR<3> CS sel23<3> VDD VSS / RSC_IHPSG13_NAND3X2 +XI1<2> NADR<2> PADR<3> CS sel23<2> VDD VSS / RSC_IHPSG13_NAND3X2 +XI1<1> PADR<2> NADR<3> CS sel23<1> VDD VSS / RSC_IHPSG13_NAND3X2 +XI1<0> NADR<2> NADR<3> CS sel23<0> VDD VSS / RSC_IHPSG13_NAND3X2 +XI2<15> sel23<3> sel01<3> EN WL<15> VDD VSS / RSC_IHPSG13_NOR3X2 +XI2<14> sel23<3> sel01<2> EN WL<14> VDD VSS / RSC_IHPSG13_NOR3X2 +XI2<13> sel23<3> sel01<1> EN WL<13> VDD VSS / RSC_IHPSG13_NOR3X2 +XI2<12> sel23<3> sel01<0> EN WL<12> VDD VSS / RSC_IHPSG13_NOR3X2 +XI2<11> sel23<2> sel01<3> EN WL<11> VDD VSS / RSC_IHPSG13_NOR3X2 +XI2<10> sel23<2> sel01<2> EN WL<10> VDD VSS / RSC_IHPSG13_NOR3X2 +XI2<9> sel23<2> sel01<1> EN WL<9> VDD VSS / RSC_IHPSG13_NOR3X2 +XI2<8> sel23<2> sel01<0> EN WL<8> VDD VSS / RSC_IHPSG13_NOR3X2 +XI2<7> sel23<1> sel01<3> EN WL<7> VDD VSS / RSC_IHPSG13_NOR3X2 +XI2<6> sel23<1> sel01<2> EN WL<6> VDD VSS / RSC_IHPSG13_NOR3X2 +XI2<5> sel23<1> sel01<1> EN WL<5> VDD VSS / RSC_IHPSG13_NOR3X2 +XI2<4> sel23<1> sel01<0> EN WL<4> VDD VSS / RSC_IHPSG13_NOR3X2 +XI2<3> sel23<0> sel01<3> EN WL<3> VDD VSS / RSC_IHPSG13_NOR3X2 +XI2<2> sel23<0> sel01<2> EN WL<2> VDD VSS / RSC_IHPSG13_NOR3X2 +XI2<1> sel23<0> sel01<1> EN WL<1> VDD VSS / RSC_IHPSG13_NOR3X2 +XI2<0> sel23<0> sel01<0> EN WL<0> VDD VSS / RSC_IHPSG13_NOR3X2 +XCAPS4 VDD VSS / RSC_IHPSG13_FILLCAP4 +XI11 ECLK_L_BOT ECLK_L_TOP / RSC_IHPSG13_MET2RES +XR0 ECLK_H_BOT ECLK_H_TOP / RSC_IHPSG13_MET2RES +.ENDS +.SUBCKT RM_IHPSG13_512x16_c2_1P_ROWDEC4 ADDR_N_I<3> ADDR_N_I<2> ADDR_N_I<1> ADDR_N_I<0> ++ CS_I ECLK_I WL_O<15> WL_O<14> WL_O<13> WL_O<12> WL_O<11> WL_O<10> WL_O<9> ++ WL_O<8> WL_O<7> WL_O<6> WL_O<5> WL_O<4> WL_O<3> WL_O<2> WL_O<1> WL_O<0> ++ VDD VSS +XL2<8> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<7> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<6> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<5> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<4> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<3> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<2> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<1> VDD VSS / RSC_IHPSG13_FILLCAP8 +XSEL ADDR_N_I<3> ADDR_N_I<2> ADDR_N_I<1> ADDR_N_I<0> CS_I ECLK_I ECLK_H<1> ++ ECLK_B<0> ECLK_B<1> WL_O<15> WL_O<14> WL_O<13> WL_O<12> WL_O<11> WL_O<10> ++ WL_O<9> WL_O<8> WL_O<7> WL_O<6> WL_O<5> WL_O<4> WL_O<3> WL_O<2> WL_O<1> ++ WL_O<0> VDD VSS / RM_IHPSG13_512x16_c2_1P_DEC04 +.ENDS +.SUBCKT RSC_IHPSG13_CINVX8 A Z VDD VSS +MN0 Z A VSS VSS sg13_lv_nmos m=1 w=2.82u l=130.00n ng=4 nrd=0 nrs=0 +MP0 Z A VDD VDD sg13_lv_pmos m=1 w=6.48u l=130.00n ng=4 nrd=0 nrs=0 +.ENDS +.SUBCKT RSC_IHPSG13_DFNQMX2IX1 BE BI CN D QI QIN VDD VSS +MN15 net026 BI VSS VSS sg13_lv_nmos m=1 w=560.00n l=130.00n ng=1 nrd=0 ++ nrs=0 +MN14 MXI_OUT BE net026 VSS sg13_lv_nmos m=1 w=560.00n l=130.00n ng=1 nrd=0 ++ nrs=0 +MN1 net025 D VSS VSS sg13_lv_nmos m=1 w=560.00n l=130.00n ng=1 nrd=0 ++ nrs=0 +MN0 MXI_OUT BEN net025 VSS sg13_lv_nmos m=1 w=560.00n l=130.00n ng=1 nrd=0 ++ nrs=0 +MN10 QI CNN net21 VSS sg13_lv_nmos m=1 w=850.00n l=130.00n ng=1 nrd=0 nrs=0 +MN11 net21 QI_MS VSS VSS sg13_lv_nmos m=1 w=850.00n l=130.00n ng=1 ++ nrd=0 nrs=0 +MN7 net30 QI_MS VSS VSS sg13_lv_nmos m=1 w=480.00n l=130.00n ng=1 ++ nrd=0 nrs=0 +MN6 QIN_MS CNN net30 VSS sg13_lv_nmos m=1 w=480.00n l=130.00n ng=1 nrd=0 ++ nrs=0 +MN3 QI_MS QIN_MS VSS VSS sg13_lv_nmos m=1 w=480.00n l=130.00n ng=1 ++ nrd=0 nrs=0 +MN12 CNN CN VSS VSS sg13_lv_nmos m=1 w=495.000n l=130.00n ng=1 nrd=0 ++ nrs=0 +MN9 net37 MXI_OUT VSS VSS sg13_lv_nmos m=1 w=870.00n l=130.00n ng=1 ++ nrd=0 nrs=0 +MN8 QIN_MS CN net37 VSS sg13_lv_nmos m=1 w=870.00n l=130.00n ng=1 nrd=0 ++ nrs=0 +MN5 QI CN net25 VSS sg13_lv_nmos m=1 w=480.00n l=130.00n ng=1 nrd=0 nrs=0 +MN4 net25 QIN VSS VSS sg13_lv_nmos m=1 w=480.00n l=130.00n ng=1 nrd=0 ++ nrs=0 +MN2 QIN QI VSS VSS sg13_lv_nmos m=1 w=480.00n l=130.00n ng=1 nrd=0 ++ nrs=0 +MN13 BEN BE VSS VSS sg13_lv_nmos m=1 w=560.00n l=130.00n ng=1 nrd=0 ++ nrs=0 +MP15 MXI_OUT BEN net027 VDD sg13_lv_pmos m=1 w=985.000n l=130.00n ng=1 ++ nrd=0 nrs=0 +MP14 net027 BI VDD VDD sg13_lv_pmos m=1 w=985.000n l=130.00n ng=1 ++ nrd=0 nrs=0 +MP1 MXI_OUT BE net024 VDD sg13_lv_pmos m=1 w=985.000n l=130.00n ng=1 nrd=0 ++ nrs=0 +MP0 net024 D VDD VDD sg13_lv_pmos m=1 w=985.000n l=130.00n ng=1 nrd=0 ++ nrs=0 +MP13 BEN BE VDD VDD sg13_lv_pmos m=1 w=645.000n l=130.00n ng=1 nrd=0 ++ nrs=0 +MP6 QI_MS QIN_MS VDD VDD sg13_lv_pmos m=1 w=480.00n l=130.00n ng=1 ++ nrd=0 nrs=0 +MP3 QI CNN net27 VDD sg13_lv_pmos m=1 w=480.00n l=130.00n ng=1 nrd=0 nrs=0 +MP2 net27 QIN VDD VDD sg13_lv_pmos m=1 w=480.00n l=130.00n ng=1 nrd=0 ++ nrs=0 +MP10 net36 MXI_OUT VDD VDD sg13_lv_pmos m=1 w=975.000n l=130.00n ng=1 ++ nrd=0 nrs=0 +MP11 QIN_MS CNN net36 VDD sg13_lv_pmos m=1 w=975.000n l=130.00n ng=1 nrd=0 ++ nrs=0 +MP4 net32 QI_MS VDD VDD sg13_lv_pmos m=1 w=480.00n l=130.00n ng=1 ++ nrd=0 nrs=0 +MP5 QIN_MS CN net32 VDD sg13_lv_pmos m=1 w=480.00n l=130.00n ng=1 nrd=0 ++ nrs=0 +MP7 QIN QI VDD VDD sg13_lv_pmos m=1 w=480.00n l=130.00n ng=1 nrd=0 ++ nrs=0 +MP12 CNN CN VDD VDD sg13_lv_pmos m=1 w=480.00n l=130.00n ng=1 nrd=0 ++ nrs=0 +MP9 QI CN net19 VDD sg13_lv_pmos m=1 w=990.00n l=130.00n ng=1 nrd=0 nrs=0 +MP8 net19 QI_MS VDD VDD sg13_lv_pmos m=1 w=990.00n l=130.00n ng=1 ++ nrd=0 nrs=0 +.ENDS +.SUBCKT RM_IHPSG13_512x16_c2_1P_ROWREG4 ACLK_N_I ADDR_I<3> ADDR_I<2> ADDR_I<1> ADDR_I<0> ++ ADDR_N_O<3> ADDR_N_O<2> ADDR_N_O<1> ADDR_N_O<0> BIST_ADDR_I<3> ++ BIST_ADDR_I<2> BIST_ADDR_I<1> BIST_ADDR_I<0> BIST_EN_I VDD VSS +XINV<3> q_int<3> qn_int<3> VDD VSS / RSC_IHPSG13_CINVX2 +XINV<2> q_int<2> qn_int<2> VDD VSS / RSC_IHPSG13_CINVX2 +XINV<1> q_int<1> qn_int<1> VDD VSS / RSC_IHPSG13_CINVX2 +XINV<0> q_int<0> qn_int<0> VDD VSS / RSC_IHPSG13_CINVX2 +XDRV<3> qn_int<3> ADDR_N_O<3> VDD VSS / RSC_IHPSG13_CINVX8 +XDRV<2> qn_int<2> ADDR_N_O<2> VDD VSS / RSC_IHPSG13_CINVX8 +XDRV<1> qn_int<1> ADDR_N_O<1> VDD VSS / RSC_IHPSG13_CINVX8 +XDRV<0> qn_int<0> ADDR_N_O<0> VDD VSS / RSC_IHPSG13_CINVX8 +XDFF<3> BIST_EN_I BIST_ADDR_I<3> ACLK_N_I ADDR_I<3> q_int<3> net2<0> VDD ++ VSS / RSC_IHPSG13_DFNQMX2IX1 +XDFF<2> BIST_EN_I BIST_ADDR_I<2> ACLK_N_I ADDR_I<2> q_int<2> net2<1> VDD ++ VSS / RSC_IHPSG13_DFNQMX2IX1 +XDFF<1> BIST_EN_I BIST_ADDR_I<1> ACLK_N_I ADDR_I<1> q_int<1> net2<2> VDD ++ VSS / RSC_IHPSG13_DFNQMX2IX1 +XDFF<0> BIST_EN_I BIST_ADDR_I<0> ACLK_N_I ADDR_I<0> q_int<0> net2<3> VDD ++ VSS / RSC_IHPSG13_DFNQMX2IX1 +XI11<20> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI11<19> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI11<18> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI11<17> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI11<16> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI11<15> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI11<14> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI11<13> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI11<12> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI11<11> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI11<10> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI11<9> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI11<8> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI11<7> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI11<6> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI11<5> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI11<4> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI11<3> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI11<2> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI11<1> VDD VSS / RSC_IHPSG13_FILLCAP8 +.ENDS +.SUBCKT RSC_IHPSG13_CDLYX1 A Z VDD VSS +MN1 net010 net032 VSS VSS sg13_lv_nmos m=1 w=300.0n l=160.00n ng=1 ++ nrd=0 nrs=0 +MN2 net032 A net014 VSS sg13_lv_nmos m=1 w=300.0n l=160.00n ng=1 nrd=0 ++ nrs=0 +MN0 Z net032 net010 VSS sg13_lv_nmos m=1 w=300.0n l=160.00n ng=1 nrd=0 ++ nrs=0 +MN3 net014 A VSS VSS sg13_lv_nmos m=1 w=300.0n l=160.00n ng=1 nrd=0 ++ nrs=0 +MP1 Z net032 net07 VDD sg13_lv_pmos m=1 w=720.00n l=160.00n ng=1 nrd=0 ++ nrs=0 +MP3 net011 A VDD VDD sg13_lv_pmos m=1 w=720.00n l=160.00n ng=1 nrd=0 ++ nrs=0 +MP0 net07 net032 VDD VDD sg13_lv_pmos m=1 w=720.00n l=160.00n ng=1 ++ nrd=0 nrs=0 +MP2 net032 A net011 VDD sg13_lv_pmos m=1 w=720.00n l=160.00n ng=1 nrd=0 ++ nrs=0 +.ENDS +.SUBCKT RSC_IHPSG13_CDLYX1_DUMMY A Z VDD VSS +MN0 vss_r vdd_r VSS VSS sg13_lv_nmos m=1 w=2.49u l=300.0n ng=3 nrd=0 ++ nrs=0 +MP0 vdd_r vss_r VDD VDD sg13_lv_pmos m=1 w=3.24u l=640.00n ng=2 nrd=0 ++ nrs=0 +R0 Z A lvsres w=2.6e-07 l=6e-07 +.ENDS + +.SUBCKT RSC_IHPSG13_MX2IX1 A0 A1 S ZN VDD VSS +MP4 SN S VDD VDD sg13_lv_pmos m=1 w=645.000n l=130.00n ng=1 nrd=0 nrs=0 +MP3 ZN SN net12 VDD sg13_lv_pmos m=1 w=985.000n l=130.00n ng=1 nrd=0 nrs=0 +MP2 net12 A1 VDD VDD sg13_lv_pmos m=1 w=985.000n l=130.00n ng=1 nrd=0 ++ nrs=0 +MP1 ZN S net17 VDD sg13_lv_pmos m=1 w=985.000n l=130.00n ng=1 nrd=0 nrs=0 +MP0 net17 A0 VDD VDD sg13_lv_pmos m=1 w=985.000n l=130.00n ng=1 nrd=0 ++ nrs=0 +MN5 SN S VSS VSS sg13_lv_nmos m=1 w=480.00n l=130.00n ng=1 nrd=0 nrs=0 +MN3 net13 A1 VSS VSS sg13_lv_nmos m=1 w=480.00n l=130.00n ng=1 nrd=0 ++ nrs=0 +MN2 ZN S net13 VSS sg13_lv_nmos m=1 w=480.00n l=130.00n ng=1 nrd=0 nrs=0 +MN1 net15 A0 VSS VSS sg13_lv_nmos m=1 w=480.00n l=130.00n ng=1 nrd=0 ++ nrs=0 +MN0 ZN SN net15 VSS sg13_lv_nmos m=1 w=480.00n l=130.00n ng=1 nrd=0 nrs=0 +.ENDS +.SUBCKT RM_IHPSG13_512x16_c2_1P_DLY_MUX A SEL Z VDD VSS +XI11 net4 Z VDD VSS / RSC_IHPSG13_CINVX2 +XI8 A D<3> SEL net4 VDD VSS / RSC_IHPSG13_MX2IX1 +XI20<3> D<2> D<3> VDD VSS / RSC_IHPSG13_CDLYX1 +XI20<2> D<1> D<2> VDD VSS / RSC_IHPSG13_CDLYX1 +XI20<1> A D<1> VDD VSS / RSC_IHPSG13_CDLYX1 +.ENDS +.SUBCKT RSC_IHPSG13_DFNQX2 CN D Q VDD VSS +MN0 Q QIN_SL VSS VSS sg13_lv_nmos m=1 w=980.00n l=130.00n ng=1 nrd=0 ++ nrs=0 +MN10 QIN_SL CNN net21 VSS sg13_lv_nmos m=1 w=850.00n l=130.00n ng=1 nrd=0 ++ nrs=0 +MN11 net21 QI_MS VSS VSS sg13_lv_nmos m=1 w=850.00n l=130.00n ng=1 ++ nrd=0 nrs=0 +MN7 net30 QI_MS VSS VSS sg13_lv_nmos m=1 w=480.00n l=130.00n ng=1 ++ nrd=0 nrs=0 +MN6 QIN_MS CNN net30 VSS sg13_lv_nmos m=1 w=480.00n l=130.00n ng=1 nrd=0 ++ nrs=0 +MN3 QI_MS QIN_MS VSS VSS sg13_lv_nmos m=1 w=480.00n l=130.00n ng=1 ++ nrd=0 nrs=0 +MN12 CNN CN VSS VSS sg13_lv_nmos m=1 w=495.000n l=130.00n ng=1 nrd=0 ++ nrs=0 +MN9 net37 D VSS VSS sg13_lv_nmos m=1 w=870.00n l=130.00n ng=1 nrd=0 ++ nrs=0 +MN8 QIN_MS CN net37 VSS sg13_lv_nmos m=1 w=870.00n l=130.00n ng=1 nrd=0 ++ nrs=0 +MN5 QIN_SL CN net25 VSS sg13_lv_nmos m=1 w=480.00n l=130.00n ng=1 nrd=0 ++ nrs=0 +MN4 net25 QI_SL VSS VSS sg13_lv_nmos m=1 w=480.00n l=130.00n ng=1 ++ nrd=0 nrs=0 +MN2 QI_SL QIN_SL VSS VSS sg13_lv_nmos m=1 w=480.00n l=130.00n ng=1 ++ nrd=0 nrs=0 +MP0 Q QIN_SL VDD VDD sg13_lv_pmos m=1 w=1.62u l=130.00n ng=1 nrd=0 ++ nrs=0 +MP6 QI_MS QIN_MS VDD VDD sg13_lv_pmos m=1 w=480.00n l=130.00n ng=1 ++ nrd=0 nrs=0 +MP3 QIN_SL CNN net27 VDD sg13_lv_pmos m=1 w=480.00n l=130.00n ng=1 nrd=0 ++ nrs=0 +MP2 net27 QI_SL VDD VDD sg13_lv_pmos m=1 w=480.00n l=130.00n ng=1 ++ nrd=0 nrs=0 +MP10 net36 D VDD VDD sg13_lv_pmos m=1 w=975.000n l=130.00n ng=1 nrd=0 ++ nrs=0 +MP11 QIN_MS CNN net36 VDD sg13_lv_pmos m=1 w=975.000n l=130.00n ng=1 nrd=0 ++ nrs=0 +MP4 net32 QI_MS VDD VDD sg13_lv_pmos m=1 w=480.00n l=130.00n ng=1 ++ nrd=0 nrs=0 +MP5 QIN_MS CN net32 VDD sg13_lv_pmos m=1 w=480.00n l=130.00n ng=1 nrd=0 ++ nrs=0 +MP7 QI_SL QIN_SL VDD VDD sg13_lv_pmos m=1 w=480.00n l=130.00n ng=1 ++ nrd=0 nrs=0 +MP12 CNN CN VDD VDD sg13_lv_pmos m=1 w=480.00n l=130.00n ng=1 nrd=0 ++ nrs=0 +MP9 QIN_SL CN net19 VDD sg13_lv_pmos m=1 w=990.00n l=130.00n ng=1 nrd=0 ++ nrs=0 +MP8 net19 QI_MS VDD VDD sg13_lv_pmos m=1 w=990.00n l=130.00n ng=1 ++ nrd=0 nrs=0 +.ENDS +.SUBCKT RSC_IHPSG13_CNAND2X2 A B Z VDD VSS +MN0 Z B net6 VSS sg13_lv_nmos m=1 w=980.00n l=130.00n ng=1 nrd=0 nrs=0 +MN1 net6 A VSS VSS sg13_lv_nmos m=1 w=980.00n l=130.00n ng=1 nrd=0 ++ nrs=0 +MP1 Z B VDD VDD sg13_lv_pmos m=1 w=1.62u l=130.00n ng=1 nrd=0 nrs=0 +MP0 Z A VDD VDD sg13_lv_pmos m=1 w=1.62u l=130.00n ng=1 nrd=0 nrs=0 +.ENDS +.SUBCKT RSC_IHPSG13_CGATEPX4 CP E Q VDD VSS +MN1 net08 QIN VSS VSS sg13_lv_nmos m=1 w=480.00n l=130.00n ng=1 nrd=0 ++ nrs=0 +MN2 net019 net08 VSS VSS sg13_lv_nmos m=1 w=480.00n l=130.00n ng=1 ++ nrd=0 nrs=0 +MN3 QIN CP net019 VSS sg13_lv_nmos m=1 w=480.00n l=130.00n ng=1 nrd=0 nrs=0 +MN6 Q net015 VSS VSS sg13_lv_nmos m=1 w=1.41u l=130.00n ng=2 nrd=0 ++ nrs=0 +MN5 net015 net08 net018 VSS sg13_lv_nmos m=1 w=980.00n l=130.00n ng=1 ++ nrd=0 nrs=0 +MN8 QIN CPN net023 VSS sg13_lv_nmos m=1 w=870.00n l=130.00n ng=1 nrd=0 ++ nrs=0 +MN7 net023 E VSS VSS sg13_lv_nmos m=1 w=870.00n l=130.00n ng=1 nrd=0 ++ nrs=0 +MN4 net018 CP VSS VSS sg13_lv_nmos m=1 w=980.00n l=130.00n ng=1 nrd=0 ++ nrs=0 +MN0 CPN CP VSS VSS sg13_lv_nmos m=1 w=500.0n l=130.00n ng=1 nrd=0 nrs=0 +MP3 net08 QIN VDD VDD sg13_lv_pmos m=1 w=480.00n l=130.00n ng=1 nrd=0 ++ nrs=0 +MP2 QIN CPN net017 VDD sg13_lv_pmos m=1 w=480.00n l=130.00n ng=1 nrd=0 ++ nrs=0 +MP1 net017 net08 VDD VDD sg13_lv_pmos m=1 w=480.00n l=130.00n ng=1 ++ nrd=0 nrs=0 +MP0 CPN CP VDD VDD sg13_lv_pmos m=1 w=500.0n l=130.00n ng=1 nrd=0 nrs=0 +MP8 QIN CP net024 VDD sg13_lv_pmos m=1 w=975.000n l=130.00n ng=1 nrd=0 ++ nrs=0 +MP7 net024 E VDD VDD sg13_lv_pmos m=1 w=975.000n l=130.00n ng=1 nrd=0 ++ nrs=0 +MP4 net015 CP VDD VDD sg13_lv_pmos m=1 w=1.27u l=130.00n ng=1 nrd=0 ++ nrs=0 +MP6 Q net015 VDD VDD sg13_lv_pmos m=1 w=3.24u l=130.00n ng=2 nrd=0 ++ nrs=0 +MP5 net015 net08 VDD VDD sg13_lv_pmos m=1 w=1.27u l=130.00n ng=1 nrd=0 ++ nrs=0 +.ENDS +.SUBCKT RSC_IHPSG13_CBUFX8 A Z VDD VSS +MP0 net4 A VDD VDD sg13_lv_pmos m=1 w=3.24u l=130.00n ng=2 nrd=0 nrs=0 +MP1 Z net4 VDD VDD sg13_lv_pmos m=1 w=6.48u l=130.00n ng=4 nrd=0 nrs=0 +MN1 Z net4 VSS VSS sg13_lv_nmos m=1 w=2.82u l=130.00n ng=4 nrd=0 nrs=0 +MN0 net4 A VSS VSS sg13_lv_nmos m=1 w=1.41u l=130.00n ng=2 nrd=0 nrs=0 +.ENDS +.SUBCKT RSC_IHPSG13_CDLYX2 A Z VDD VSS +MN2 net4 A net9 VSS sg13_lv_nmos m=1 w=320.00n l=200.0n ng=1 nrd=0 nrs=0 +MN0 Z net4 VSS VSS sg13_lv_nmos m=1 w=705.000n l=130.00n ng=1 nrd=0 ++ nrs=0 +MN1 net9 A VSS VSS sg13_lv_nmos m=1 w=320.00n l=200.0n ng=1 nrd=0 nrs=0 +MP2 net4 A net10 VDD sg13_lv_pmos m=1 w=1.2u l=200.0n ng=1 nrd=0 nrs=0 +MP1 net10 A VDD VDD sg13_lv_pmos m=1 w=1.2u l=200.0n ng=1 nrd=0 nrs=0 +MP0 Z net4 VDD VDD sg13_lv_pmos m=1 w=1.62u l=130.00n ng=1 nrd=0 nrs=0 +.ENDS +.SUBCKT RSC_IHPSG13_MX2X2 A0 A1 S Z VDD VSS +MP6 Z net010 VDD VDD sg13_lv_pmos m=1 w=1.62u l=130.00n ng=1 nrd=0 ++ nrs=0 +MP4 SN S VDD VDD sg13_lv_pmos m=1 w=645.000n l=130.00n ng=1 nrd=0 nrs=0 +MP3 net010 SN net12 VDD sg13_lv_pmos m=1 w=985.000n l=130.00n ng=1 nrd=0 ++ nrs=0 +MP2 net12 A1 VDD VDD sg13_lv_pmos m=1 w=985.000n l=130.00n ng=1 nrd=0 ++ nrs=0 +MP1 net010 S net17 VDD sg13_lv_pmos m=1 w=985.000n l=130.00n ng=1 nrd=0 ++ nrs=0 +MP0 net17 A0 VDD VDD sg13_lv_pmos m=1 w=985.000n l=130.00n ng=1 nrd=0 ++ nrs=0 +MN6 Z net010 VSS VSS sg13_lv_nmos m=1 w=705.000n l=130.00n ng=1 nrd=0 ++ nrs=0 +MN5 SN S VSS VSS sg13_lv_nmos m=1 w=560.00n l=130.00n ng=1 nrd=0 nrs=0 +MN3 net13 A1 VSS VSS sg13_lv_nmos m=1 w=560.00n l=130.00n ng=1 nrd=0 ++ nrs=0 +MN2 net010 S net13 VSS sg13_lv_nmos m=1 w=560.00n l=130.00n ng=1 nrd=0 ++ nrs=0 +MN1 net15 A0 VSS VSS sg13_lv_nmos m=1 w=560.00n l=130.00n ng=1 nrd=0 ++ nrs=0 +MN0 net010 SN net15 VSS sg13_lv_nmos m=1 w=560.00n l=130.00n ng=1 nrd=0 ++ nrs=0 +.ENDS +.SUBCKT RSC_IHPSG13_AND2X2 A B Z VDD VSS +MN3 Z net6 VSS VSS sg13_lv_nmos m=1 w=980.00n l=130.00n ng=1 nrd=0 ++ nrs=0 +MN4 net9 B VSS VSS sg13_lv_nmos m=1 w=500.0n l=130.00n ng=1 nrd=0 nrs=0 +MN6 net6 A net9 VSS sg13_lv_nmos m=1 w=500.0n l=130.00n ng=1 nrd=0 nrs=0 +MP2 Z net6 VDD VDD sg13_lv_pmos m=1 w=1.62u l=130.00n ng=1 nrd=0 nrs=0 +MP0 net6 B VDD VDD sg13_lv_pmos m=1 w=860.00n l=130.00n ng=1 nrd=0 ++ nrs=0 +MP1 net6 A VDD VDD sg13_lv_pmos m=1 w=860.00n l=130.00n ng=1 nrd=0 ++ nrs=0 +.ENDS +.SUBCKT RSC_IHPSG13_TIEL Z VDD VSS +MN0 Z net2 VSS VSS sg13_lv_nmos m=1 w=480.00n l=130.00n ng=1 nrd=0 ++ nrs=0 +MP0 net2 net2 VDD VDD sg13_lv_pmos m=1 w=480.00n l=130.00n ng=1 nrd=0 ++ nrs=0 +.ENDS +.SUBCKT RSC_IHPSG13_XOR2X2 A B Z VDD VSS +MP8 net012 B net7 VDD sg13_lv_pmos m=1 w=825.000n l=130.00n ng=1 nrd=0 ++ nrs=0 +MP7 net011 net3 net012 VDD sg13_lv_pmos m=1 w=825.000n l=130.00n ng=1 ++ nrd=0 nrs=0 +MP6 Z net012 VDD VDD sg13_lv_pmos m=1 w=1.535u l=130.00n ng=1 nrd=0 ++ nrs=0 +MP2 net7 A VDD VDD sg13_lv_pmos m=1 w=825.000n l=130.00n ng=1 nrd=0 ++ nrs=0 +MP4 net011 net7 VDD VDD sg13_lv_pmos m=1 w=825.000n l=130.00n ng=1 ++ nrd=0 nrs=0 +MP5 net3 B VDD VDD sg13_lv_pmos m=1 w=580.00n l=130.00n ng=1 nrd=0 ++ nrs=0 +MN7 net012 B net011 VSS sg13_lv_nmos m=1 w=555.000n l=130.00n ng=1 nrd=0 ++ nrs=0 +MN6 net7 net3 net012 VSS sg13_lv_nmos m=1 w=555.000n l=130.00n ng=1 nrd=0 ++ nrs=0 +MN5 Z net012 VSS VSS sg13_lv_nmos m=1 w=775.000n l=130.00n ng=1 nrd=0 ++ nrs=0 +MN2 net7 A VSS VSS sg13_lv_nmos m=1 w=555.000n l=130.00n ng=1 nrd=0 ++ nrs=0 +MN4 net3 B VSS VSS sg13_lv_nmos m=1 w=480.00n l=130.00n ng=1 nrd=0 ++ nrs=0 +MN3 net011 net7 VSS VSS sg13_lv_nmos m=1 w=555.000n l=130.00n ng=1 ++ nrd=0 nrs=0 +.ENDS +.SUBCKT RSC_IHPSG13_OA12X1 A B C Z VDD VSS +MN2 net7 C VSS VSS sg13_lv_nmos m=1 w=980.00n l=130.00n ng=1 nrd=0 ++ nrs=0 +MN3 Z net17 VSS VSS sg13_lv_nmos m=1 w=500.0n l=130.00n ng=1 nrd=0 ++ nrs=0 +MN1 net17 B net7 VSS sg13_lv_nmos m=1 w=980.00n l=130.00n ng=1 nrd=0 nrs=0 +MN0 net17 A net7 VSS sg13_lv_nmos m=1 w=980.00n l=130.00n ng=1 nrd=0 nrs=0 +MP0 net24 A VDD VDD sg13_lv_pmos m=1 w=1.62u l=130.00n ng=1 nrd=0 nrs=0 +MP3 Z net17 VDD VDD sg13_lv_pmos m=1 w=905.000n l=130.00n ng=1 nrd=0 ++ nrs=0 +MP1 net17 B net24 VDD sg13_lv_pmos m=1 w=1.62u l=130.00n ng=1 nrd=0 nrs=0 +MP2 net17 C VDD VDD sg13_lv_pmos m=1 w=905.000n l=130.00n ng=1 nrd=0 ++ nrs=0 +.ENDS +.SUBCKT RM_IHPSG13_512x16_c2_1P_CTRL ACLK_N BIST_CK_I BIST_CS_I BIST_EN BIST_RE_I ++ BIST_WE_I B_TIEL_O CK_I CS_I DCLK ECLK PULSE_H PULSE_L PULSE_O RCLK RE_I ++ ROW_CS WCLK WE_I VDD VSS +XI17 ck_regs we col_we VDD VSS / RSC_IHPSG13_DFNQX2 +XI16 ck_regs re col_re VDD VSS / RSC_IHPSG13_DFNQX2 +XI18 ck_regs cs net7 VDD VSS / RSC_IHPSG13_DFNQX2 +XI71 ACLK_N net012 PULSE_O VDD VSS / RSC_IHPSG13_DFNQX2 +XI77 col_we net9 net016 VDD VSS / RSC_IHPSG13_CNAND2X2 +XI76 col_re net9 net018 VDD VSS / RSC_IHPSG13_CNAND2X2 +XI15 ck_dly WEorREandCS aclk VDD VSS / RSC_IHPSG13_CGATEPX4 +XI14 ck WEandCS DCLK VDD VSS / RSC_IHPSG13_CGATEPX4 +XI60 net7 ROW_CS VDD VSS / RSC_IHPSG13_CBUFX8 +XI73 PULSE_O net012 VDD VSS / RSC_IHPSG13_CINVX2 +XI8 net9 net8 VDD VSS / RSC_IHPSG13_CINVX2 +XI64 ck ck_dly VDD VSS / RSC_IHPSG13_CDLYX2 +XI86 CS_I BIST_CS_I BIST_EN cs VDD VSS / RSC_IHPSG13_MX2X2 +XI87 CK_I BIST_CK_I BIST_EN ck VDD VSS / RSC_IHPSG13_MX2X2 +XI85 WE_I BIST_WE_I BIST_EN we VDD VSS / RSC_IHPSG13_MX2X2 +XI84 RE_I BIST_RE_I BIST_EN re VDD VSS / RSC_IHPSG13_MX2X2 +XI22 we cs WEandCS VDD VSS / RSC_IHPSG13_AND2X2 +XBM_TIEL B_TIEL_O VDD VSS / RSC_IHPSG13_TIEL +XI48 ck_dly ck_regs VDD VSS / RSC_IHPSG13_CINVX4 +XI81 net016 WCLK VDD VSS / RSC_IHPSG13_CINVX4 +XI80 net018 RCLK VDD VSS / RSC_IHPSG13_CINVX4 +XI78 net8 net020 VDD VSS / RSC_IHPSG13_CINVX4 +XI6 PULSE_L PULSE_H net9 VDD VSS / RSC_IHPSG13_XOR2X2 +XI79 net020 ECLK VDD VSS / RSC_IHPSG13_CINVX8 +XI63 aclk ACLK_N VDD VSS / RSC_IHPSG13_CINVX8 +XI21 re we cs WEorREandCS VDD VSS / RSC_IHPSG13_OA12X1 +.ENDS +.SUBCKT RM_IHPSG13_512x16_c2_1P_COLDEC2 ACLK_N ADDR<1> ADDR<0> ADDR_COL<1> ADDR_COL<0> ++ ADDR_DEC<7> ADDR_DEC<6> ADDR_DEC<5> ADDR_DEC<4> ADDR_DEC<3> ADDR_DEC<2> ++ ADDR_DEC<1> ADDR_DEC<0> BIST_ADDR<1> BIST_ADDR<0> BIST_EN_I VDD VSS +XI14<5> VDD VSS / RSC_IHPSG13_FILLCAP4 +XI14<4> VDD VSS / RSC_IHPSG13_FILLCAP4 +XI14<3> VDD VSS / RSC_IHPSG13_FILLCAP4 +XI14<2> VDD VSS / RSC_IHPSG13_FILLCAP4 +XI14<1> VDD VSS / RSC_IHPSG13_FILLCAP4 +XDFF<1> BIST_EN_I BIST_ADDR<1> ACLK_N ADDR<1> padr_int<1> net6<0> VDD ++ VSS / RSC_IHPSG13_DFNQMX2IX1 +XDFF<0> BIST_EN_I BIST_ADDR<0> ACLK_N ADDR<0> padr_int<0> net6<1> VDD ++ VSS / RSC_IHPSG13_DFNQMX2IX1 +XI1<3> PADR<1> PADR<0> addr_n<3> VDD VSS / RSC_IHPSG13_NAND2X2 +XI1<2> PADR<1> NADR<0> addr_n<2> VDD VSS / RSC_IHPSG13_NAND2X2 +XI1<1> NADR<1> PADR<0> addr_n<1> VDD VSS / RSC_IHPSG13_NAND2X2 +XI1<0> NADR<1> NADR<0> addr_n<0> VDD VSS / RSC_IHPSG13_NAND2X2 +XI16<37> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI16<36> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI16<35> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI16<34> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI16<33> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI16<32> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI16<31> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI16<30> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI16<29> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI16<28> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI16<27> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI16<26> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI16<25> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI16<24> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI16<23> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI16<22> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI16<21> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI16<20> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI16<19> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI16<18> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI16<17> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI16<16> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI16<15> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI16<14> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI16<13> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI16<12> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI16<11> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI16<10> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI16<9> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI16<8> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI16<7> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI16<6> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI16<5> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI16<4> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI16<3> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI16<2> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI16<1> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI3<1> padr_int<1> NADR<1> VDD VSS / RSC_IHPSG13_INVX2 +XI3<0> padr_int<0> NADR<0> VDD VSS / RSC_IHPSG13_INVX2 +XI13<1> NADR<1> PADR<1> VDD VSS / RSC_IHPSG13_INVX2 +XI13<0> NADR<0> PADR<0> VDD VSS / RSC_IHPSG13_INVX2 +XI2<3> addr_n<3> ADDR_DEC<3> VDD VSS / RSC_IHPSG13_INVX2 +XI2<2> addr_n<2> ADDR_DEC<2> VDD VSS / RSC_IHPSG13_INVX2 +XI2<1> addr_n<1> ADDR_DEC<1> VDD VSS / RSC_IHPSG13_INVX2 +XI2<0> addr_n<0> ADDR_DEC<0> VDD VSS / RSC_IHPSG13_INVX2 +XI15<1> ADDR_COL<1> VDD VSS / RSC_IHPSG13_TIEL +XI15<0> ADDR_COL<0> VDD VSS / RSC_IHPSG13_TIEL +XI17<3> ADDR_DEC<7> VDD VSS / RSC_IHPSG13_TIEL +XI17<2> ADDR_DEC<6> VDD VSS / RSC_IHPSG13_TIEL +XI17<1> ADDR_DEC<5> VDD VSS / RSC_IHPSG13_TIEL +XI17<0> ADDR_DEC<4> VDD VSS / RSC_IHPSG13_TIEL +.ENDS +.SUBCKT RSC_IHPSG13_NOR2X2 A B Z VDD VSS +MP1 Z B net9 VDD sg13_lv_pmos m=1 w=1.62u l=130.00n ng=1 nrd=0 nrs=0 +MP0 net9 A VDD VDD sg13_lv_pmos m=1 w=1.62u l=130.00n ng=1 nrd=0 nrs=0 +MN0 Z B VSS VSS sg13_lv_nmos m=1 w=980.00n l=130.00n ng=1 nrd=0 nrs=0 +MN1 Z A VSS VSS sg13_lv_nmos m=1 w=980.00n l=130.00n ng=1 nrd=0 nrs=0 +.ENDS +.SUBCKT RSC_IHPSG13_CINVX4_WN A Z VDD VSS +MN0 Z A VSS VSS sg13_lv_nmos m=1 w=705.000n l=130.00n ng=1 nrd=0 nrs=0 +MP0 Z A VDD VDD sg13_lv_pmos m=1 w=3.24u l=130.00n ng=2 nrd=0 nrs=0 +.ENDS +.SUBCKT RM_IHPSG13_512x16_c2_1P_BLDRV BLC BLC_SEL BLT BLT_SEL PRE_N SEL_P WR_ONE WR_ZERO ++ VDD VSS +XCDEC SEL_P WR_ZERO BLC_PMOS_DRIVE VDD VSS / RSC_IHPSG13_NAND2X2 +XTDEC SEL_P WR_ONE BLT_PMOS_DRIVE VDD VSS / RSC_IHPSG13_NAND2X2 +MTWN BLT BLT_NMOS_DRIVE VSS VSS sg13_lv_nmos m=1 w=4.82u l=130.00n ++ ng=2 nrd=0 nrs=0 +MCWN BLC BLC_NMOS_DRIVE VSS VSS sg13_lv_nmos m=1 w=4.82u l=130.00n ++ ng=2 nrd=0 nrs=0 +MCWP BLC BLC_PMOS_DRIVE VDD VDD sg13_lv_pmos m=1 w=1.5u l=130.00n ng=1 ++ nrd=0 nrs=0 +MTWP BLT BLT_PMOS_DRIVE VDD VDD sg13_lv_pmos m=1 w=1.5u l=130.00n ng=1 ++ nrd=0 nrs=0 +MTSP BLT_SEL SEL_N BLT VDD sg13_lv_pmos m=1 w=1.5u l=130.00n ng=1 nrd=0 ++ nrs=0 +MTPR BLT PRE_N VDD VDD sg13_lv_pmos m=1 w=3.000u l=130.00n ng=2 nrd=0 ++ nrs=0 +MCSP BLC_SEL SEL_N BLC VDD sg13_lv_pmos m=1 w=1.5u l=130.00n ng=1 nrd=0 ++ nrs=0 +MCPR BLC PRE_N VDD VDD sg13_lv_pmos m=1 w=3.000u l=130.00n ng=2 nrd=0 ++ nrs=0 +XI86 SEL_P SEL_N VDD VSS / RSC_IHPSG13_INVX2 +XTINV BLC_PMOS_DRIVE BLT_NMOS_DRIVE VDD VSS / RSC_IHPSG13_INVX2 +XCINV BLT_PMOS_DRIVE BLC_NMOS_DRIVE VDD VSS / RSC_IHPSG13_INVX2 +.ENDS +.SUBCKT RSC_IHPSG13_TIEH Z VDD VSS +MN0 net2 net2 VSS VSS sg13_lv_nmos m=1 w=480.00n l=130.00n ng=1 nrd=0 ++ nrs=0 +MP0 Z net2 VDD VDD sg13_lv_pmos m=1 w=480.00n l=130.00n ng=1 nrd=0 ++ nrs=0 +.ENDS +.SUBCKT RSC_IHPSG13_MET3RES A B +R0 B A lvsres w=2.6e-07 l=6e-07 +.ENDS +.SUBCKT RSC_IHPSG13_DFPQD_MSAFFX2 CP DN DP QN QP VDD VSS +MN12 SN RN DIFFP VSS sg13_lv_nmos m=1 w=2.4u l=200.0n ng=2 nrd=0 nrs=0 +MN13 TAIL CP VSS VSS sg13_lv_nmos m=1 w=2.4u l=130.00n ng=2 nrd=0 nrs=0 +MN9 DIFFP DP TAIL VSS sg13_lv_nmos m=1 w=2.4u l=200.0n ng=2 nrd=0 nrs=0 +MN10 DIFFN DN TAIL VSS sg13_lv_nmos m=1 w=2.4u l=200.0n ng=2 nrd=0 nrs=0 +MN11 RN SN DIFFN VSS sg13_lv_nmos m=1 w=2.4u l=200.0n ng=2 nrd=0 nrs=0 +MN19 net33 SN VSS VSS sg13_lv_nmos m=1 w=980.00n l=130.00n ng=1 nrd=0 ++ nrs=0 +MN20 QN QP net37 VSS sg13_lv_nmos m=1 w=980.00n l=130.00n ng=1 nrd=0 nrs=0 +MN18 net37 RN VSS VSS sg13_lv_nmos m=1 w=980.00n l=130.00n ng=1 nrd=0 ++ nrs=0 +MN17 QP QN net33 VSS sg13_lv_nmos m=1 w=980.00n l=130.00n ng=1 nrd=0 nrs=0 +MP15 SN RN VDD VDD sg13_lv_pmos m=1 w=800.0n l=130.00n ng=1 nrd=0 nrs=0 +MP16 RN CP VDD VDD sg13_lv_pmos m=1 w=800.0n l=130.00n ng=1 nrd=0 nrs=0 +MP14 DIFFP CP VDD VDD sg13_lv_pmos m=1 w=800.0n l=130.00n ng=1 nrd=0 ++ nrs=0 +MP12 RN SN VDD VDD sg13_lv_pmos m=1 w=800.0n l=130.00n ng=1 nrd=0 nrs=0 +MP13 DIFFN CP VDD VDD sg13_lv_pmos m=1 w=800.0n l=130.00n ng=1 nrd=0 ++ nrs=0 +MP11 SN CP VDD VDD sg13_lv_pmos m=1 w=800.0n l=130.00n ng=1 nrd=0 nrs=0 +MP19 QN QP VDD VDD sg13_lv_pmos m=1 w=900.0n l=130.00n ng=1 nrd=0 nrs=0 +MP20 QP SN VDD VDD sg13_lv_pmos m=1 w=1.8u l=130.00n ng=2 nrd=0 nrs=0 +MP18 QN RN VDD VDD sg13_lv_pmos m=1 w=1.8u l=130.00n ng=2 nrd=0 nrs=0 +MP17 QP QN VDD VDD sg13_lv_pmos m=1 w=900.0n l=130.00n ng=1 nrd=0 nrs=0 +.ENDS +.SUBCKT RSC_IHPSG13_CBUFX2 A Z VDD VSS +MN1 Z net4 VSS VSS sg13_lv_nmos m=1 w=705.000n l=130.00n ng=1 nrd=0 ++ nrs=0 +MN0 net4 A VSS VSS sg13_lv_nmos m=1 w=540.00n l=130.00n ng=1 nrd=0 ++ nrs=0 +MP1 Z net4 VDD VDD sg13_lv_pmos m=1 w=1.62u l=130.00n ng=1 nrd=0 nrs=0 +MP0 net4 A VDD VDD sg13_lv_pmos m=1 w=1.1u l=130.00n ng=1 nrd=0 nrs=0 +.ENDS +.SUBCKT RSC_IHPSG13_INVX4 A Z VDD VSS +MN0 Z A VSS VSS sg13_lv_nmos m=1 w=1.96u l=130.00n ng=2 nrd=0 nrs=0 +MP0 Z A VDD VDD sg13_lv_pmos m=1 w=3.24u l=130.00n ng=2 nrd=0 nrs=0 +.ENDS +.SUBCKT RM_IHPSG13_512x16_c2_1P_COLCTRL2 A_ADDR_DEC<3> A_ADDR_DEC<2> A_ADDR_DEC<1> ++ A_ADDR_DEC<0> A_BIST_BM_I A_BIST_DW_I A_BIST_EN_I A_BLC<3> A_BLC<2> A_BLC<1> ++ A_BLC<0> A_BLT<3> A_BLT<2> A_BLT<1> A_BLT<0> A_BM_I A_DCLK_B_L A_DCLK_B_R ++ A_DCLK_L A_DCLK_R A_DR_O A_DW_I A_RCLK_B_L A_RCLK_B_R A_RCLK_L A_RCLK_R ++ A_TIEH_O A_WCLK_B_L A_WCLK_B_R A_WCLK_L A_WCLK_R VDD VSS +XA_DREG A_BIST_EN_I A_BIST_DW_I A_DCLK_B_L A_DW_I A_DI_R net22 VDD VSS ++ / RSC_IHPSG13_DFNQMX2IX1 +XA_BREG A_BIST_EN_I A_BIST_BM_I A_DCLK_B_L A_BM_I A_BM_R net23 VDD VSS ++ / RSC_IHPSG13_DFNQMX2IX1 +XA_CAPS<5> VDD VSS / RSC_IHPSG13_FILLCAP4 +XA_CAPS<4> VDD VSS / RSC_IHPSG13_FILLCAP4 +XA_CAPS<3> VDD VSS / RSC_IHPSG13_FILLCAP4 +XA_CAPS<2> VDD VSS / RSC_IHPSG13_FILLCAP4 +XA_CAPS<1> VDD VSS / RSC_IHPSG13_FILLCAP4 +XA_I80 A_WCLK_B_R A_RCLK_B_R net21 VDD VSS / RSC_IHPSG13_AND2X2 +XA_I75 A_DI_R A_DO_WRITE_P A_WR_ONE VDD VSS / RSC_IHPSG13_AND2X2 +XA_I76 A_DI_N A_DO_WRITE_P A_WR_ZERO VDD VSS / RSC_IHPSG13_AND2X2 +XA_I44 A_WCLK_B_R A_BM_N A_DO_WRITE_P VDD VSS / RSC_IHPSG13_NOR2X2 +XA_I81 net21 A_PRE_N VDD VSS / RSC_IHPSG13_CINVX4_WN +XA_BLTMUX<3> A_BLC<3> A_BLC_SEL A_BLT<3> A_BLT_SEL A_PRE_N A_ADDR_DEC<3> ++ A_WR_ONE A_WR_ZERO VDD VSS / RM_IHPSG13_512x16_c2_1P_BLDRV +XA_BLTMUX<2> A_BLC<2> A_BLC_SEL A_BLT<2> A_BLT_SEL A_PRE_N A_ADDR_DEC<2> ++ A_WR_ONE A_WR_ZERO VDD VSS / RM_IHPSG13_512x16_c2_1P_BLDRV +XA_BLTMUX<1> A_BLC<1> A_BLC_SEL A_BLT<1> A_BLT_SEL A_PRE_N A_ADDR_DEC<1> ++ A_WR_ONE A_WR_ZERO VDD VSS / RM_IHPSG13_512x16_c2_1P_BLDRV +XA_BLTMUX<0> A_BLC<0> A_BLC_SEL A_BLT<0> A_BLT_SEL A_PRE_N A_ADDR_DEC<0> ++ A_WR_ONE A_WR_ZERO VDD VSS / RM_IHPSG13_512x16_c2_1P_BLDRV +XA_BM_TIEH A_TIEH_O VDD VSS / RSC_IHPSG13_TIEH +XA_I89 A_DCLK_B_L A_DCLK_B_R / RSC_IHPSG13_MET3RES +XA_I88 A_DCLK_L A_DCLK_R / RSC_IHPSG13_MET3RES +XA_I87 A_WCLK_L A_WCLK_R / RSC_IHPSG13_MET3RES +XA_I91 A_RCLK_B_R A_RCLK_B_L / RSC_IHPSG13_MET3RES +XA_R2 A_RCLK_R A_RCLK_L / RSC_IHPSG13_MET3RES +XA_I90 A_WCLK_B_R A_WCLK_B_L / RSC_IHPSG13_MET3RES +XA_ISENSE A_SAE A_BLC_SEL A_BLT_SEL net19 net20 VDD VSS / ++ RSC_IHPSG13_DFPQD_MSAFFX2 +XA_I78 A_RCLK_B_R A_SAE VDD VSS / RSC_IHPSG13_CBUFX2 +XA_I83 A_BM_R A_BM_N VDD VSS / RSC_IHPSG13_INVX2 +XA_I49 A_DI_R A_DI_N VDD VSS / RSC_IHPSG13_INVX2 +XA_I51 net19 A_DR_O VDD VSS / RSC_IHPSG13_INVX4 +XA_I69 A_DCLK_L A_DCLK_B_L VDD VSS / RSC_IHPSG13_CINVX2 +XA_I50 A_WCLK_L A_WCLK_B_R VDD VSS / RSC_IHPSG13_CINVX2 +XA_EBUF A_RCLK_R A_RCLK_B_R VDD VSS / RSC_IHPSG13_CINVX2 +.ENDS +.SUBCKT RM_IHPSG13_512x16_c2_1P_COLDRV13_FILL4 VDD VSS +XI0<9> VDD VSS / RSC_IHPSG13_FILLCAP4 +XI0<8> VDD VSS / RSC_IHPSG13_FILLCAP4 +XI0<7> VDD VSS / RSC_IHPSG13_FILLCAP4 +XI0<6> VDD VSS / RSC_IHPSG13_FILLCAP4 +XI0<5> VDD VSS / RSC_IHPSG13_FILLCAP4 +XI0<4> VDD VSS / RSC_IHPSG13_FILLCAP4 +XI0<3> VDD VSS / RSC_IHPSG13_FILLCAP4 +XI0<2> VDD VSS / RSC_IHPSG13_FILLCAP4 +XI0<1> VDD VSS / RSC_IHPSG13_FILLCAP4 +.ENDS +.SUBCKT RM_IHPSG13_512x16_c2_1P_COLDRV13_FILL4C2 VDD VSS +XI0<2> VDD VSS / RSC_IHPSG13_FILLCAP4 +XI0<1> VDD VSS / RSC_IHPSG13_FILLCAP4 +.ENDS + + +.SUBCKT RM_IHPSG13_512x16_c2_1P_COLDEC4 ACLK_N ADDR<3> ADDR<2> ADDR<1> ADDR<0> ++ ADDR_COL<1> ADDR_COL<0> ADDR_DEC<7> ADDR_DEC<6> ADDR_DEC<5> ADDR_DEC<4> ++ ADDR_DEC<3> ADDR_DEC<2> ADDR_DEC<1> ADDR_DEC<0> BIST_ADDR<3> BIST_ADDR<2> ++ BIST_ADDR<1> BIST_ADDR<0> BIST_EN_I VDD VSS +XI15 ADDR_COL<1> VDD VSS / RSC_IHPSG13_TIEL +XI14 addr_int ADDR_COL<0> VDD VSS / RSC_IHPSG13_CBUFX2 +XDFF<3> BIST_EN_I BIST_ADDR<3> ACLK_N ADDR<3> addr_int net7<0> VDD VSS ++ / RSC_IHPSG13_DFNQMX2IX1 +XDFF<2> BIST_EN_I BIST_ADDR<2> ACLK_N ADDR<2> padr_int<2> net7<1> VDD ++ VSS / RSC_IHPSG13_DFNQMX2IX1 +XDFF<1> BIST_EN_I BIST_ADDR<1> ACLK_N ADDR<1> padr_int<1> net7<2> VDD ++ VSS / RSC_IHPSG13_DFNQMX2IX1 +XDFF<0> BIST_EN_I BIST_ADDR<0> ACLK_N ADDR<0> padr_int<0> net7<3> VDD ++ VSS / RSC_IHPSG13_DFNQMX2IX1 +XI1<7> PADR<0> PADR<1> PADR<2> addr_n<7> VDD VSS / RSC_IHPSG13_NAND3X2 +XI1<6> NADR<0> PADR<1> PADR<2> addr_n<6> VDD VSS / RSC_IHPSG13_NAND3X2 +XI1<5> PADR<0> NADR<1> PADR<2> addr_n<5> VDD VSS / RSC_IHPSG13_NAND3X2 +XI1<4> NADR<0> NADR<1> PADR<2> addr_n<4> VDD VSS / RSC_IHPSG13_NAND3X2 +XI1<3> PADR<0> PADR<1> NADR<2> addr_n<3> VDD VSS / RSC_IHPSG13_NAND3X2 +XI1<2> NADR<0> PADR<1> NADR<2> addr_n<2> VDD VSS / RSC_IHPSG13_NAND3X2 +XI1<1> PADR<0> NADR<1> NADR<2> addr_n<1> VDD VSS / RSC_IHPSG13_NAND3X2 +XI1<0> NADR<0> NADR<1> NADR<2> addr_n<0> VDD VSS / RSC_IHPSG13_NAND3X2 +XI13<2> NADR<2> PADR<2> VDD VSS / RSC_IHPSG13_INVX2 +XI13<1> NADR<1> PADR<1> VDD VSS / RSC_IHPSG13_INVX2 +XI13<0> NADR<0> PADR<0> VDD VSS / RSC_IHPSG13_INVX2 +XI3<2> padr_int<2> NADR<2> VDD VSS / RSC_IHPSG13_INVX2 +XI3<1> padr_int<1> NADR<1> VDD VSS / RSC_IHPSG13_INVX2 +XI3<0> padr_int<0> NADR<0> VDD VSS / RSC_IHPSG13_INVX2 +XI2<7> addr_n<7> ADDR_DEC<7> VDD VSS / RSC_IHPSG13_INVX2 +XI2<6> addr_n<6> ADDR_DEC<6> VDD VSS / RSC_IHPSG13_INVX2 +XI2<5> addr_n<5> ADDR_DEC<5> VDD VSS / RSC_IHPSG13_INVX2 +XI2<4> addr_n<4> ADDR_DEC<4> VDD VSS / RSC_IHPSG13_INVX2 +XI2<3> addr_n<3> ADDR_DEC<3> VDD VSS / RSC_IHPSG13_INVX2 +XI2<2> addr_n<2> ADDR_DEC<2> VDD VSS / RSC_IHPSG13_INVX2 +XI2<1> addr_n<1> ADDR_DEC<1> VDD VSS / RSC_IHPSG13_INVX2 +XI2<0> addr_n<0> ADDR_DEC<0> VDD VSS / RSC_IHPSG13_INVX2 +XI16<3> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI16<2> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI16<1> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI17<2> VDD VSS / RSC_IHPSG13_FILLCAP4 +XI17<1> VDD VSS / RSC_IHPSG13_FILLCAP4 +.ENDS +.SUBCKT RSC_IHPSG13_AND2X4 A B Z VDD VSS +MN3 Z net6 VSS VSS sg13_lv_nmos m=1 w=1.96u l=130.00n ng=2 nrd=0 nrs=0 +MN4 net9 B VSS VSS sg13_lv_nmos m=1 w=500.0n l=130.00n ng=1 nrd=0 nrs=0 +MN6 net6 A net9 VSS sg13_lv_nmos m=1 w=500.0n l=130.00n ng=1 nrd=0 nrs=0 +MP2 Z net6 VDD VDD sg13_lv_pmos m=1 w=3.24u l=130.00n ng=2 nrd=0 nrs=0 +MP0 net6 B VDD VDD sg13_lv_pmos m=1 w=860.00n l=130.00n ng=1 nrd=0 ++ nrs=0 +MP1 net6 A VDD VDD sg13_lv_pmos m=1 w=860.00n l=130.00n ng=1 nrd=0 ++ nrs=0 +.ENDS +.SUBCKT RM_IHPSG13_512x16_c2_1P_COLCTRL4 A_ADDR_COL A_ADDR_DEC<7> A_ADDR_DEC<6> ++ A_ADDR_DEC<5> A_ADDR_DEC<4> A_ADDR_DEC<3> A_ADDR_DEC<2> A_ADDR_DEC<1> ++ A_ADDR_DEC<0> A_BIST_BM_I A_BIST_DW_I A_BIST_EN_I A_BLC<15> A_BLC<14> ++ A_BLC<13> A_BLC<12> A_BLC<11> A_BLC<10> A_BLC<9> A_BLC<8> A_BLC<7> A_BLC<6> ++ A_BLC<5> A_BLC<4> A_BLC<3> A_BLC<2> A_BLC<1> A_BLC<0> A_BLT<15> A_BLT<14> ++ A_BLT<13> A_BLT<12> A_BLT<11> A_BLT<10> A_BLT<9> A_BLT<8> A_BLT<7> A_BLT<6> ++ A_BLT<5> A_BLT<4> A_BLT<3> A_BLT<2> A_BLT<1> A_BLT<0> A_BM_I A_DCLK_B_L ++ A_DCLK_B_R A_DCLK_L A_DCLK_R A_DR_O A_DW_I A_RCLK_B_L A_RCLK_B_R A_RCLK_L ++ A_RCLK_R A_TIEH_O A_WCLK_B_L A_WCLK_B_R A_WCLK_L A_WCLK_R VDD VSS +XA_I80 A_WCLK_B_L A_RCLK_B_L net21 VDD VSS / RSC_IHPSG13_AND2X2 +XA_I76 A_DO_WRITE_P A_DI_N A_WR_ZERO VDD VSS / RSC_IHPSG13_AND2X4 +XA_I75 A_DI_R A_DO_WRITE_P A_WR_ONE VDD VSS / RSC_IHPSG13_AND2X4 +XA_CAPS<8> VDD VSS / RSC_IHPSG13_FILLCAP4 +XA_CAPS<7> VDD VSS / RSC_IHPSG13_FILLCAP4 +XA_CAPS<6> VDD VSS / RSC_IHPSG13_FILLCAP4 +XA_CAPS<5> VDD VSS / RSC_IHPSG13_FILLCAP4 +XA_CAPS<4> VDD VSS / RSC_IHPSG13_FILLCAP4 +XA_CAPS<3> VDD VSS / RSC_IHPSG13_FILLCAP4 +XA_CAPS<2> VDD VSS / RSC_IHPSG13_FILLCAP4 +XA_CAPS<1> VDD VSS / RSC_IHPSG13_FILLCAP4 +XA_I69 A_DCLK_L A_DCLK_B_L VDD VSS / RSC_IHPSG13_CINVX4 +XA_I50 A_WCLK_L A_WCLK_B_L VDD VSS / RSC_IHPSG13_CINVX4 +XA_EBUF A_RCLK_L A_RCLK_B_L VDD VSS / RSC_IHPSG13_CINVX4 +XA_INV<1> A_N0 A_P0 VDD VSS / RSC_IHPSG13_CINVX4 +XA_INV<0> A_ADDR_COL A_N0 VDD VSS / RSC_IHPSG13_CINVX4 +XA_I81<1> net21 A_PRE_N VDD VSS / RSC_IHPSG13_CINVX4_WN +XA_I81<0> net21 A_PRE_N VDD VSS / RSC_IHPSG13_CINVX4_WN +XA_BLTMUX<15> A_BLC<15> A_BLC_SEL A_BLT<15> A_BLT_SEL A_PRE_N A_SEL_P<15> ++ A_WR_ONE A_WR_ZERO VDD VSS / RM_IHPSG13_512x16_c2_1P_BLDRV +XA_BLTMUX<14> A_BLC<14> A_BLC_SEL A_BLT<14> A_BLT_SEL A_PRE_N A_SEL_P<14> ++ A_WR_ONE A_WR_ZERO VDD VSS / RM_IHPSG13_512x16_c2_1P_BLDRV +XA_BLTMUX<13> A_BLC<13> A_BLC_SEL A_BLT<13> A_BLT_SEL A_PRE_N A_SEL_P<13> ++ A_WR_ONE A_WR_ZERO VDD VSS / RM_IHPSG13_512x16_c2_1P_BLDRV +XA_BLTMUX<12> A_BLC<12> A_BLC_SEL A_BLT<12> A_BLT_SEL A_PRE_N A_SEL_P<12> ++ A_WR_ONE A_WR_ZERO VDD VSS / RM_IHPSG13_512x16_c2_1P_BLDRV +XA_BLTMUX<11> A_BLC<11> A_BLC_SEL A_BLT<11> A_BLT_SEL A_PRE_N A_SEL_P<11> ++ A_WR_ONE A_WR_ZERO VDD VSS / RM_IHPSG13_512x16_c2_1P_BLDRV +XA_BLTMUX<10> A_BLC<10> A_BLC_SEL A_BLT<10> A_BLT_SEL A_PRE_N A_SEL_P<10> ++ A_WR_ONE A_WR_ZERO VDD VSS / RM_IHPSG13_512x16_c2_1P_BLDRV +XA_BLTMUX<9> A_BLC<9> A_BLC_SEL A_BLT<9> A_BLT_SEL A_PRE_N A_SEL_P<9> A_WR_ONE ++ A_WR_ZERO VDD VSS / RM_IHPSG13_512x16_c2_1P_BLDRV +XA_BLTMUX<8> A_BLC<8> A_BLC_SEL A_BLT<8> A_BLT_SEL A_PRE_N A_SEL_P<8> A_WR_ONE ++ A_WR_ZERO VDD VSS / RM_IHPSG13_512x16_c2_1P_BLDRV +XA_BLTMUX<7> A_BLC<7> A_BLC_SEL A_BLT<7> A_BLT_SEL A_PRE_N A_SEL_P<7> A_WR_ONE ++ A_WR_ZERO VDD VSS / RM_IHPSG13_512x16_c2_1P_BLDRV +XA_BLTMUX<6> A_BLC<6> A_BLC_SEL A_BLT<6> A_BLT_SEL A_PRE_N A_SEL_P<6> A_WR_ONE ++ A_WR_ZERO VDD VSS / RM_IHPSG13_512x16_c2_1P_BLDRV +XA_BLTMUX<5> A_BLC<5> A_BLC_SEL A_BLT<5> A_BLT_SEL A_PRE_N A_SEL_P<5> A_WR_ONE ++ A_WR_ZERO VDD VSS / RM_IHPSG13_512x16_c2_1P_BLDRV +XA_BLTMUX<4> A_BLC<4> A_BLC_SEL A_BLT<4> A_BLT_SEL A_PRE_N A_SEL_P<4> A_WR_ONE ++ A_WR_ZERO VDD VSS / RM_IHPSG13_512x16_c2_1P_BLDRV +XA_BLTMUX<3> A_BLC<3> A_BLC_SEL A_BLT<3> A_BLT_SEL A_PRE_N A_SEL_P<3> A_WR_ONE ++ A_WR_ZERO VDD VSS / RM_IHPSG13_512x16_c2_1P_BLDRV +XA_BLTMUX<2> A_BLC<2> A_BLC_SEL A_BLT<2> A_BLT_SEL A_PRE_N A_SEL_P<2> A_WR_ONE ++ A_WR_ZERO VDD VSS / RM_IHPSG13_512x16_c2_1P_BLDRV +XA_BLTMUX<1> A_BLC<1> A_BLC_SEL A_BLT<1> A_BLT_SEL A_PRE_N A_SEL_P<1> A_WR_ONE ++ A_WR_ZERO VDD VSS / RM_IHPSG13_512x16_c2_1P_BLDRV +XA_BLTMUX<0> A_BLC<0> A_BLC_SEL A_BLT<0> A_BLT_SEL A_PRE_N A_SEL_P<0> A_WR_ONE ++ A_WR_ZERO VDD VSS / RM_IHPSG13_512x16_c2_1P_BLDRV +XA_R2 A_RCLK_L A_RCLK_R / RSC_IHPSG13_MET3RES +XA_I87 A_WCLK_L A_WCLK_R / RSC_IHPSG13_MET3RES +XA_I88 A_DCLK_L A_DCLK_R / RSC_IHPSG13_MET3RES +XA_I89 A_DCLK_B_L A_DCLK_B_R / RSC_IHPSG13_MET3RES +XA_I90 A_WCLK_B_L A_WCLK_B_R / RSC_IHPSG13_MET3RES +XA_I91 A_RCLK_B_L A_RCLK_B_R / RSC_IHPSG13_MET3RES +XA_ISENSE A_SAE A_BLC_SEL A_BLT_SEL net19 net20 VDD VSS / ++ RSC_IHPSG13_DFPQD_MSAFFX2 +XA_I51 net19 A_DR_O VDD VSS / RSC_IHPSG13_INVX4 +XA_I78 A_RCLK_B_L A_SAE VDD VSS / RSC_IHPSG13_CBUFX2 +XA_DREG A_BIST_EN_I A_BIST_DW_I A_DCLK_B_L A_DW_I A_DI_R net22 VDD VSS ++ / RSC_IHPSG13_DFNQMX2IX1 +XA_BREG A_BIST_EN_I A_BIST_BM_I A_DCLK_B_L A_BM_I A_BM_R net24 VDD VSS ++ / RSC_IHPSG13_DFNQMX2IX1 +XA_DEC3INV<15> net23<0> A_SEL_P<15> VDD VSS / RSC_IHPSG13_INVX2 +XA_DEC3INV<14> net23<1> A_SEL_P<14> VDD VSS / RSC_IHPSG13_INVX2 +XA_DEC3INV<13> net23<2> A_SEL_P<13> VDD VSS / RSC_IHPSG13_INVX2 +XA_DEC3INV<12> net23<3> A_SEL_P<12> VDD VSS / RSC_IHPSG13_INVX2 +XA_DEC3INV<11> net23<4> A_SEL_P<11> VDD VSS / RSC_IHPSG13_INVX2 +XA_DEC3INV<10> net23<5> A_SEL_P<10> VDD VSS / RSC_IHPSG13_INVX2 +XA_DEC3INV<9> net23<6> A_SEL_P<9> VDD VSS / RSC_IHPSG13_INVX2 +XA_DEC3INV<8> net23<7> A_SEL_P<8> VDD VSS / RSC_IHPSG13_INVX2 +XA_DEC3INV<7> net23<8> A_SEL_P<7> VDD VSS / RSC_IHPSG13_INVX2 +XA_DEC3INV<6> net23<9> A_SEL_P<6> VDD VSS / RSC_IHPSG13_INVX2 +XA_DEC3INV<5> net23<10> A_SEL_P<5> VDD VSS / RSC_IHPSG13_INVX2 +XA_DEC3INV<4> net23<11> A_SEL_P<4> VDD VSS / RSC_IHPSG13_INVX2 +XA_DEC3INV<3> net23<12> A_SEL_P<3> VDD VSS / RSC_IHPSG13_INVX2 +XA_DEC3INV<2> net23<13> A_SEL_P<2> VDD VSS / RSC_IHPSG13_INVX2 +XA_DEC3INV<1> net23<14> A_SEL_P<1> VDD VSS / RSC_IHPSG13_INVX2 +XA_DEC3INV<0> net23<15> A_SEL_P<0> VDD VSS / RSC_IHPSG13_INVX2 +XA_I83 A_BM_R A_BM_N VDD VSS / RSC_IHPSG13_INVX2 +XA_I49 A_DI_R A_DI_N VDD VSS / RSC_IHPSG13_INVX2 +XA_I70<4> VDD VSS / RSC_IHPSG13_FILLCAP8 +XA_I70<3> VDD VSS / RSC_IHPSG13_FILLCAP8 +XA_I70<2> VDD VSS / RSC_IHPSG13_FILLCAP8 +XA_I70<1> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI73<14> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI73<13> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI73<12> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI73<11> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI73<10> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI73<9> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI73<8> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI73<7> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI73<6> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI73<5> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI73<4> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI73<3> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI73<2> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI73<1> VDD VSS / RSC_IHPSG13_FILLCAP8 +XA_I44 A_BM_N A_WCLK_B_L A_DO_WRITE_P VDD VSS / RSC_IHPSG13_NOR2X2 +XA_DEC3<15> A_P0 A_ADDR_DEC<7> net23<0> VDD VSS / RSC_IHPSG13_NAND2X2 +XA_DEC3<14> A_P0 A_ADDR_DEC<6> net23<1> VDD VSS / RSC_IHPSG13_NAND2X2 +XA_DEC3<13> A_P0 A_ADDR_DEC<5> net23<2> VDD VSS / RSC_IHPSG13_NAND2X2 +XA_DEC3<12> A_P0 A_ADDR_DEC<4> net23<3> VDD VSS / RSC_IHPSG13_NAND2X2 +XA_DEC3<11> A_P0 A_ADDR_DEC<3> net23<4> VDD VSS / RSC_IHPSG13_NAND2X2 +XA_DEC3<10> A_P0 A_ADDR_DEC<2> net23<5> VDD VSS / RSC_IHPSG13_NAND2X2 +XA_DEC3<9> A_P0 A_ADDR_DEC<1> net23<6> VDD VSS / RSC_IHPSG13_NAND2X2 +XA_DEC3<8> A_P0 A_ADDR_DEC<0> net23<7> VDD VSS / RSC_IHPSG13_NAND2X2 +XA_DEC3<7> A_N0 A_ADDR_DEC<7> net23<8> VDD VSS / RSC_IHPSG13_NAND2X2 +XA_DEC3<6> A_N0 A_ADDR_DEC<6> net23<9> VDD VSS / RSC_IHPSG13_NAND2X2 +XA_DEC3<5> A_N0 A_ADDR_DEC<5> net23<10> VDD VSS / RSC_IHPSG13_NAND2X2 +XA_DEC3<4> A_N0 A_ADDR_DEC<4> net23<11> VDD VSS / RSC_IHPSG13_NAND2X2 +XA_DEC3<3> A_N0 A_ADDR_DEC<3> net23<12> VDD VSS / RSC_IHPSG13_NAND2X2 +XA_DEC3<2> A_N0 A_ADDR_DEC<2> net23<13> VDD VSS / RSC_IHPSG13_NAND2X2 +XA_DEC3<1> A_N0 A_ADDR_DEC<1> net23<14> VDD VSS / RSC_IHPSG13_NAND2X2 +XA_DEC3<0> A_N0 A_ADDR_DEC<0> net23<15> VDD VSS / RSC_IHPSG13_NAND2X2 +XA_BM_TIEH A_TIEH_O VDD VSS / RSC_IHPSG13_TIEH +.ENDS + + +.SUBCKT RM_IHPSG13_512x16_c2_1P_COLDEC3 ACLK_N ADDR<2> ADDR<1> ADDR<0> ADDR_COL<1> ++ ADDR_COL<0> ADDR_DEC<7> ADDR_DEC<6> ADDR_DEC<5> ADDR_DEC<4> ADDR_DEC<3> ++ ADDR_DEC<2> ADDR_DEC<1> ADDR_DEC<0> BIST_ADDR<2> BIST_ADDR<1> BIST_ADDR<0> ++ BIST_EN_I VDD VSS +XI15<1> ADDR_COL<1> VDD VSS / RSC_IHPSG13_TIEL +XI15<0> ADDR_COL<0> VDD VSS / RSC_IHPSG13_TIEL +XI1<7> PADR<0> PADR<1> PADR<2> addr_n<7> VDD VSS / RSC_IHPSG13_NAND3X2 +XI1<6> NADR<0> PADR<1> PADR<2> addr_n<6> VDD VSS / RSC_IHPSG13_NAND3X2 +XI1<5> PADR<0> NADR<1> PADR<2> addr_n<5> VDD VSS / RSC_IHPSG13_NAND3X2 +XI1<4> NADR<0> NADR<1> PADR<2> addr_n<4> VDD VSS / RSC_IHPSG13_NAND3X2 +XI1<3> PADR<0> PADR<1> NADR<2> addr_n<3> VDD VSS / RSC_IHPSG13_NAND3X2 +XI1<2> NADR<0> PADR<1> NADR<2> addr_n<2> VDD VSS / RSC_IHPSG13_NAND3X2 +XI1<1> PADR<0> NADR<1> NADR<2> addr_n<1> VDD VSS / RSC_IHPSG13_NAND3X2 +XI1<0> NADR<0> NADR<1> NADR<2> addr_n<0> VDD VSS / RSC_IHPSG13_NAND3X2 +XDFF<2> BIST_EN_I BIST_ADDR<2> ACLK_N ADDR<2> padr_int<2> net6<0> VDD ++ VSS / RSC_IHPSG13_DFNQMX2IX1 +XDFF<1> BIST_EN_I BIST_ADDR<1> ACLK_N ADDR<1> padr_int<1> net6<1> VDD ++ VSS / RSC_IHPSG13_DFNQMX2IX1 +XDFF<0> BIST_EN_I BIST_ADDR<0> ACLK_N ADDR<0> padr_int<0> net6<2> VDD ++ VSS / RSC_IHPSG13_DFNQMX2IX1 +XI17<2> VDD VSS / RSC_IHPSG13_FILLCAP4 +XI17<1> VDD VSS / RSC_IHPSG13_FILLCAP4 +XI13<2> NADR<2> PADR<2> VDD VSS / RSC_IHPSG13_INVX2 +XI13<1> NADR<1> PADR<1> VDD VSS / RSC_IHPSG13_INVX2 +XI13<0> NADR<0> PADR<0> VDD VSS / RSC_IHPSG13_INVX2 +XI3<2> padr_int<2> NADR<2> VDD VSS / RSC_IHPSG13_INVX2 +XI3<1> padr_int<1> NADR<1> VDD VSS / RSC_IHPSG13_INVX2 +XI3<0> padr_int<0> NADR<0> VDD VSS / RSC_IHPSG13_INVX2 +XI2<7> addr_n<7> ADDR_DEC<7> VDD VSS / RSC_IHPSG13_INVX2 +XI2<6> addr_n<6> ADDR_DEC<6> VDD VSS / RSC_IHPSG13_INVX2 +XI2<5> addr_n<5> ADDR_DEC<5> VDD VSS / RSC_IHPSG13_INVX2 +XI2<4> addr_n<4> ADDR_DEC<4> VDD VSS / RSC_IHPSG13_INVX2 +XI2<3> addr_n<3> ADDR_DEC<3> VDD VSS / RSC_IHPSG13_INVX2 +XI2<2> addr_n<2> ADDR_DEC<2> VDD VSS / RSC_IHPSG13_INVX2 +XI2<1> addr_n<1> ADDR_DEC<1> VDD VSS / RSC_IHPSG13_INVX2 +XI2<0> addr_n<0> ADDR_DEC<0> VDD VSS / RSC_IHPSG13_INVX2 +XI16<6> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI16<5> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI16<4> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI16<3> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI16<2> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI16<1> VDD VSS / RSC_IHPSG13_FILLCAP8 +.ENDS +.SUBCKT RM_IHPSG13_512x16_c2_1P_COLCTRL3 A_ADDR_DEC<7> A_ADDR_DEC<6> A_ADDR_DEC<5> ++ A_ADDR_DEC<4> A_ADDR_DEC<3> A_ADDR_DEC<2> A_ADDR_DEC<1> A_ADDR_DEC<0> ++ A_BIST_BM_I A_BIST_DW_I A_BIST_EN_I A_BLC<7> A_BLC<6> A_BLC<5> A_BLC<4> ++ A_BLC<3> A_BLC<2> A_BLC<1> A_BLC<0> A_BLT<7> A_BLT<6> A_BLT<5> A_BLT<4> ++ A_BLT<3> A_BLT<2> A_BLT<1> A_BLT<0> A_BM_I A_DCLK_B_L A_DCLK_B_R A_DCLK_L ++ A_DCLK_R A_DR_O A_DW_I A_RCLK_B_L A_RCLK_B_R A_RCLK_L A_RCLK_R A_TIEH_O ++ A_WCLK_B_L A_WCLK_B_R A_WCLK_L A_WCLK_R VDD VSS +XA_DREG A_BIST_EN_I A_BIST_DW_I A_DCLK_B_L A_DW_I A_DI_R net22 VDD VSS ++ / RSC_IHPSG13_DFNQMX2IX1 +XA_BREG A_BIST_EN_I A_BIST_BM_I A_DCLK_B_R A_BM_I A_BM_R net23 VDD VSS ++ / RSC_IHPSG13_DFNQMX2IX1 +XA_I70<8> VDD VSS / RSC_IHPSG13_FILLCAP8 +XA_I70<7> VDD VSS / RSC_IHPSG13_FILLCAP8 +XA_I70<6> VDD VSS / RSC_IHPSG13_FILLCAP8 +XA_I70<5> VDD VSS / RSC_IHPSG13_FILLCAP8 +XA_I70<4> VDD VSS / RSC_IHPSG13_FILLCAP8 +XA_I70<3> VDD VSS / RSC_IHPSG13_FILLCAP8 +XA_I70<2> VDD VSS / RSC_IHPSG13_FILLCAP8 +XA_I70<1> VDD VSS / RSC_IHPSG13_FILLCAP8 +XA_I51 net19 A_DR_O VDD VSS / RSC_IHPSG13_INVX4 +XA_I44 A_BM_N A_WCLK_B_R A_DO_WRITE_P VDD VSS / RSC_IHPSG13_NOR2X2 +XA_BM_TIEH A_TIEH_O VDD VSS / RSC_IHPSG13_TIEH +XA_BLTMUX<7> A_BLC<7> A_BLC_SEL A_BLT<7> A_BLT_SEL A_PRE_N A_ADDR_DEC<7> ++ A_WR_ONE A_WR_ZERO VDD VSS / RM_IHPSG13_512x16_c2_1P_BLDRV +XA_BLTMUX<6> A_BLC<6> A_BLC_SEL A_BLT<6> A_BLT_SEL A_PRE_N A_ADDR_DEC<6> ++ A_WR_ONE A_WR_ZERO VDD VSS / RM_IHPSG13_512x16_c2_1P_BLDRV +XA_BLTMUX<5> A_BLC<5> A_BLC_SEL A_BLT<5> A_BLT_SEL A_PRE_N A_ADDR_DEC<5> ++ A_WR_ONE A_WR_ZERO VDD VSS / RM_IHPSG13_512x16_c2_1P_BLDRV +XA_BLTMUX<4> A_BLC<4> A_BLC_SEL A_BLT<4> A_BLT_SEL A_PRE_N A_ADDR_DEC<4> ++ A_WR_ONE A_WR_ZERO VDD VSS / RM_IHPSG13_512x16_c2_1P_BLDRV +XA_BLTMUX<3> A_BLC<3> A_BLC_SEL A_BLT<3> A_BLT_SEL A_PRE_N A_ADDR_DEC<3> ++ A_WR_ONE A_WR_ZERO VDD VSS / RM_IHPSG13_512x16_c2_1P_BLDRV +XA_BLTMUX<2> A_BLC<2> A_BLC_SEL A_BLT<2> A_BLT_SEL A_PRE_N A_ADDR_DEC<2> ++ A_WR_ONE A_WR_ZERO VDD VSS / RM_IHPSG13_512x16_c2_1P_BLDRV +XA_BLTMUX<1> A_BLC<1> A_BLC_SEL A_BLT<1> A_BLT_SEL A_PRE_N A_ADDR_DEC<1> ++ A_WR_ONE A_WR_ZERO VDD VSS / RM_IHPSG13_512x16_c2_1P_BLDRV +XA_BLTMUX<0> A_BLC<0> A_BLC_SEL A_BLT<0> A_BLT_SEL A_PRE_N A_ADDR_DEC<0> ++ A_WR_ONE A_WR_ZERO VDD VSS / RM_IHPSG13_512x16_c2_1P_BLDRV +XA_I49 A_DI_R A_DI_N VDD VSS / RSC_IHPSG13_INVX2 +XA_I83 A_BM_R A_BM_N VDD VSS / RSC_IHPSG13_INVX2 +XA_I69 A_DCLK_L A_DCLK_B_L VDD VSS / RSC_IHPSG13_CINVX2 +XA_I50 A_WCLK_L A_WCLK_B_L VDD VSS / RSC_IHPSG13_CINVX2 +XA_EBUF A_RCLK_L A_RCLK_B_L VDD VSS / RSC_IHPSG13_CINVX2 +XA_I78 A_RCLK_B_L A_SAE VDD VSS / RSC_IHPSG13_CBUFX2 +XA_I88 A_DCLK_L A_DCLK_R / RSC_IHPSG13_MET3RES +XA_I87 A_WCLK_L A_WCLK_R / RSC_IHPSG13_MET3RES +XA_R2 A_RCLK_L A_RCLK_R / RSC_IHPSG13_MET3RES +XA_I91 A_RCLK_B_L A_RCLK_B_R / RSC_IHPSG13_MET3RES +XA_I90 A_WCLK_B_L A_WCLK_B_R / RSC_IHPSG13_MET3RES +XA_I89 A_DCLK_B_L A_DCLK_B_R / RSC_IHPSG13_MET3RES +XA_I80 A_WCLK_B_R A_RCLK_B_R net21 VDD VSS / RSC_IHPSG13_AND2X2 +XA_I76 A_DI_N A_DO_WRITE_P A_WR_ZERO VDD VSS / RSC_IHPSG13_AND2X2 +XA_I75 A_DI_R A_DO_WRITE_P A_WR_ONE VDD VSS / RSC_IHPSG13_AND2X2 +XA_ISENSE A_SAE A_BLC_SEL A_BLT_SEL net19 net20 VDD VSS / ++ RSC_IHPSG13_DFPQD_MSAFFX2 +XA_I81 net21 A_PRE_N VDD VSS / RSC_IHPSG13_CINVX4_WN +XA_CAPS<5> VDD VSS / RSC_IHPSG13_FILLCAP4 +XA_CAPS<4> VDD VSS / RSC_IHPSG13_FILLCAP4 +XA_CAPS<3> VDD VSS / RSC_IHPSG13_FILLCAP4 +XA_CAPS<2> VDD VSS / RSC_IHPSG13_FILLCAP4 +XA_CAPS<1> VDD VSS / RSC_IHPSG13_FILLCAP4 +.ENDS + +.SUBCKT RM_IHPSG13_512x16_c2_2P_BITKIT_16x2_CORNER VDD_CORE VSS +XI16 VDD_CORE VSS VDD_CORE VSS / ++ RM_IHPSG13_512x16_c2_1P_BITKIT_CORNER +.ENDS +.SUBCKT RM_IHPSG13_512x16_c2_2P_BITKIT_EDGE_LR A_WL B_WL NW PW VDD VSS +MN1 VSS A_WL VSS VSS sg13_lv_nmos m=1 w=300.0n l=130.00n ng=1 nrd=0 nrs=0 +MN0 VSS B_WL VSS VSS sg13_lv_nmos m=1 w=300.0n l=130.00n ng=1 nrd=0 nrs=0 +.ENDS +.SUBCKT RM_IHPSG13_512x16_c2_2P_BITKIT_16x2_EDGE_LR A_WL<15> A_WL<14> A_WL<13> A_WL<12> ++ A_WL<11> A_WL<10> A_WL<9> A_WL<8> A_WL<7> A_WL<6> A_WL<5> A_WL<4> A_WL<3> ++ A_WL<2> A_WL<1> A_WL<0> B_WL<15> B_WL<14> B_WL<13> B_WL<12> B_WL<11> ++ B_WL<10> B_WL<9> B_WL<8> B_WL<7> B_WL<6> B_WL<5> B_WL<4> B_WL<3> B_WL<2> ++ B_WL<1> B_WL<0> VDD_CORE VSS +XI0<15> A_WL<15> B_WL<15> VDD_CORE VSS VDD_CORE VSS ++ / RM_IHPSG13_512x16_c2_2P_BITKIT_EDGE_LR +XI0<14> A_WL<14> B_WL<14> VDD_CORE VSS VDD_CORE VSS ++ / RM_IHPSG13_512x16_c2_2P_BITKIT_EDGE_LR +XI0<13> A_WL<13> B_WL<13> VDD_CORE VSS VDD_CORE VSS ++ / RM_IHPSG13_512x16_c2_2P_BITKIT_EDGE_LR +XI0<12> A_WL<12> B_WL<12> VDD_CORE VSS VDD_CORE VSS ++ / RM_IHPSG13_512x16_c2_2P_BITKIT_EDGE_LR +XI0<11> A_WL<11> B_WL<11> VDD_CORE VSS VDD_CORE VSS ++ / RM_IHPSG13_512x16_c2_2P_BITKIT_EDGE_LR +XI0<10> A_WL<10> B_WL<10> VDD_CORE VSS VDD_CORE VSS ++ / RM_IHPSG13_512x16_c2_2P_BITKIT_EDGE_LR +XI0<9> A_WL<9> B_WL<9> VDD_CORE VSS VDD_CORE VSS / ++ RM_IHPSG13_512x16_c2_2P_BITKIT_EDGE_LR +XI0<8> A_WL<8> B_WL<8> VDD_CORE VSS VDD_CORE VSS / ++ RM_IHPSG13_512x16_c2_2P_BITKIT_EDGE_LR +XI0<7> A_WL<7> B_WL<7> VDD_CORE VSS VDD_CORE VSS / ++ RM_IHPSG13_512x16_c2_2P_BITKIT_EDGE_LR +XI0<6> A_WL<6> B_WL<6> VDD_CORE VSS VDD_CORE VSS / ++ RM_IHPSG13_512x16_c2_2P_BITKIT_EDGE_LR +XI0<5> A_WL<5> B_WL<5> VDD_CORE VSS VDD_CORE VSS / ++ RM_IHPSG13_512x16_c2_2P_BITKIT_EDGE_LR +XI0<4> A_WL<4> B_WL<4> VDD_CORE VSS VDD_CORE VSS / ++ RM_IHPSG13_512x16_c2_2P_BITKIT_EDGE_LR +XI0<3> A_WL<3> B_WL<3> VDD_CORE VSS VDD_CORE VSS / ++ RM_IHPSG13_512x16_c2_2P_BITKIT_EDGE_LR +XI0<2> A_WL<2> B_WL<2> VDD_CORE VSS VDD_CORE VSS / ++ RM_IHPSG13_512x16_c2_2P_BITKIT_EDGE_LR +XI0<1> A_WL<1> B_WL<1> VDD_CORE VSS VDD_CORE VSS / ++ RM_IHPSG13_512x16_c2_2P_BITKIT_EDGE_LR +XI0<0> A_WL<0> B_WL<0> VDD_CORE VSS VDD_CORE VSS / ++ RM_IHPSG13_512x16_c2_2P_BITKIT_EDGE_LR +.ENDS +.SUBCKT RM_IHPSG13_512x16_c2_2P_BITKIT_CELL A_BLC_BOT A_BLC_TOP A_BLT_BOT A_BLT_TOP ++ A_LWL A_RWL B_BLC_BOT B_BLC_TOP B_BLT_BOT B_BLT_TOP B_LWL B_RWL NW PW VDD VSS +MN5 NC B_RWL B_BLC_BOT PW sg13_lv_nmos m=1 w=300.0n l=130.00n ng=1 nrd=0 nrs=0 +MN4 B_BLT_BOT B_LWL NT PW sg13_lv_nmos m=1 w=300.0n l=130.00n ng=1 nrd=0 nrs=0 +MN0 NC NT VSS PW sg13_lv_nmos m=1 w=600.0n l=130.00n ng=2 nrd=0 nrs=0 +MN1 NT NC VSS PW sg13_lv_nmos m=1 w=600.0n l=130.00n ng=2 nrd=0 nrs=0 +MN3 NC A_RWL A_BLC_TOP PW sg13_lv_nmos m=1 w=300.0n l=130.00n ng=1 nrd=0 nrs=0 +MN2 A_BLT_TOP A_LWL NT PW sg13_lv_nmos m=1 w=300.0n l=130.00n ng=1 nrd=0 nrs=0 +MP1 NT NC VDD NW sg13_lv_pmos m=1 w=150.00n l=130.00n ng=1 nrd=0 nrs=0 +MP0 NC NT VDD NW sg13_lv_pmos m=1 w=150.00n l=130.00n ng=1 nrd=0 nrs=0 +R5 B_RWL B_LWL lvsres w=2.6e-07 l=6e-07 +R4 B_BLC_BOT B_BLC_TOP lvsres w=2.6e-07 l=6e-07 +R3 B_BLT_BOT B_BLT_TOP lvsres w=2.6e-07 l=6e-07 +R1 A_BLC_BOT A_BLC_TOP lvsres w=2.6e-07 l=6e-07 +R0 A_BLT_BOT A_BLT_TOP lvsres w=2.6e-07 l=6e-07 +R2 A_RWL A_LWL lvsres w=2.6e-07 l=6e-07 +.ENDS +.SUBCKT RM_IHPSG13_512x16_c2_2P_BITKIT_16x2_SRAM A_BLC_BOT<1> A_BLC_BOT<0> A_BLC_TOP<1> ++ A_BLC_TOP<0> A_BLT_BOT<1> A_BLT_BOT<0> A_BLT_TOP<1> A_BLT_TOP<0> A_LWL<15> ++ A_LWL<14> A_LWL<13> A_LWL<12> A_LWL<11> A_LWL<10> A_LWL<9> A_LWL<8> A_LWL<7> ++ A_LWL<6> A_LWL<5> A_LWL<4> A_LWL<3> A_LWL<2> A_LWL<1> A_LWL<0> A_RWL<15> ++ A_RWL<14> A_RWL<13> A_RWL<12> A_RWL<11> A_RWL<10> A_RWL<9> A_RWL<8> A_RWL<7> ++ A_RWL<6> A_RWL<5> A_RWL<4> A_RWL<3> A_RWL<2> A_RWL<1> A_RWL<0> B_BLC_BOT<1> ++ B_BLC_BOT<0> B_BLC_TOP<1> B_BLC_TOP<0> B_BLT_BOT<1> B_BLT_BOT<0> ++ B_BLT_TOP<1> B_BLT_TOP<0> B_LWL<15> B_LWL<14> B_LWL<13> B_LWL<12> B_LWL<11> ++ B_LWL<10> B_LWL<9> B_LWL<8> B_LWL<7> B_LWL<6> B_LWL<5> B_LWL<4> B_LWL<3> ++ B_LWL<2> B_LWL<1> B_LWL<0> B_RWL<15> B_RWL<14> B_RWL<13> B_RWL<12> B_RWL<11> ++ B_RWL<10> B_RWL<9> B_RWL<8> B_RWL<7> B_RWL<6> B_RWL<5> B_RWL<4> B_RWL<3> ++ B_RWL<2> B_RWL<1> B_RWL<0> VDD_CORE VSS +XCELL<31> A_BLC_TOP<1> A_RBLC<15> A_BLT_TOP<1> A_RBLT<15> A_XWL<15> A_RWL<15> ++ B_BLC_TOP<1> B_RBLC<15> B_BLT_TOP<1> B_RBLT<15> B_XWL<15> B_RWL<15> ++ VDD_CORE VSS VDD_CORE VSS / ++ RM_IHPSG13_512x16_c2_2P_BITKIT_CELL +XCELL<30> A_RBLC<14> A_RBLC<15> A_RBLT<14> A_RBLT<15> A_XWL<14> A_RWL<14> ++ B_RBLC<14> B_RBLC<15> B_RBLT<14> B_RBLT<15> B_XWL<14> B_RWL<14> VDD_CORE ++ VSS VDD_CORE VSS / RM_IHPSG13_512x16_c2_2P_BITKIT_CELL +XCELL<29> A_RBLC<14> A_RBLC<13> A_RBLT<14> A_RBLT<13> A_XWL<13> A_RWL<13> ++ B_RBLC<14> B_RBLC<13> B_RBLT<14> B_RBLT<13> B_XWL<13> B_RWL<13> VDD_CORE ++ VSS VDD_CORE VSS / RM_IHPSG13_512x16_c2_2P_BITKIT_CELL +XCELL<28> A_RBLC<12> A_RBLC<13> A_RBLT<12> A_RBLT<13> A_XWL<12> A_RWL<12> ++ B_RBLC<12> B_RBLC<13> B_RBLT<12> B_RBLT<13> B_XWL<12> B_RWL<12> VDD_CORE ++ VSS VDD_CORE VSS / RM_IHPSG13_512x16_c2_2P_BITKIT_CELL +XCELL<27> A_RBLC<12> A_RBLC<11> A_RBLT<12> A_RBLT<11> A_XWL<11> A_RWL<11> ++ B_RBLC<12> B_RBLC<11> B_RBLT<12> B_RBLT<11> B_XWL<11> B_RWL<11> VDD_CORE ++ VSS VDD_CORE VSS / RM_IHPSG13_512x16_c2_2P_BITKIT_CELL +XCELL<26> A_RBLC<10> A_RBLC<11> A_RBLT<10> A_RBLT<11> A_XWL<10> A_RWL<10> ++ B_RBLC<10> B_RBLC<11> B_RBLT<10> B_RBLT<11> B_XWL<10> B_RWL<10> VDD_CORE ++ VSS VDD_CORE VSS / RM_IHPSG13_512x16_c2_2P_BITKIT_CELL +XCELL<25> A_RBLC<10> A_RBLC<9> A_RBLT<10> A_RBLT<9> A_XWL<9> A_RWL<9> ++ B_RBLC<10> B_RBLC<9> B_RBLT<10> B_RBLT<9> B_XWL<9> B_RWL<9> VDD_CORE ++ VSS VDD_CORE VSS / RM_IHPSG13_512x16_c2_2P_BITKIT_CELL +XCELL<24> A_RBLC<8> A_RBLC<9> A_RBLT<8> A_RBLT<9> A_XWL<8> A_RWL<8> B_RBLC<8> ++ B_RBLC<9> B_RBLT<8> B_RBLT<9> B_XWL<8> B_RWL<8> VDD_CORE VSS ++ VDD_CORE VSS / RM_IHPSG13_512x16_c2_2P_BITKIT_CELL +XCELL<23> A_RBLC<8> A_RBLC<7> A_RBLT<8> A_RBLT<7> A_XWL<7> A_RWL<7> B_RBLC<8> ++ B_RBLC<7> B_RBLT<8> B_RBLT<7> B_XWL<7> B_RWL<7> VDD_CORE VSS ++ VDD_CORE VSS / RM_IHPSG13_512x16_c2_2P_BITKIT_CELL +XCELL<22> A_RBLC<6> A_RBLC<7> A_RBLT<6> A_RBLT<7> A_XWL<6> A_RWL<6> B_RBLC<6> ++ B_RBLC<7> B_RBLT<6> B_RBLT<7> B_XWL<6> B_RWL<6> VDD_CORE VSS ++ VDD_CORE VSS / RM_IHPSG13_512x16_c2_2P_BITKIT_CELL +XCELL<21> A_RBLC<6> A_RBLC<5> A_RBLT<6> A_RBLT<5> A_XWL<5> A_RWL<5> B_RBLC<6> ++ B_RBLC<5> B_RBLT<6> B_RBLT<5> B_XWL<5> B_RWL<5> VDD_CORE VSS ++ VDD_CORE VSS / RM_IHPSG13_512x16_c2_2P_BITKIT_CELL +XCELL<20> A_RBLC<4> A_RBLC<5> A_RBLT<4> A_RBLT<5> A_XWL<4> A_RWL<4> B_RBLC<4> ++ B_RBLC<5> B_RBLT<4> B_RBLT<5> B_XWL<4> B_RWL<4> VDD_CORE VSS ++ VDD_CORE VSS / RM_IHPSG13_512x16_c2_2P_BITKIT_CELL +XCELL<19> A_RBLC<4> A_RBLC<3> A_RBLT<4> A_RBLT<3> A_XWL<3> A_RWL<3> B_RBLC<4> ++ B_RBLC<3> B_RBLT<4> B_RBLT<3> B_XWL<3> B_RWL<3> VDD_CORE VSS ++ VDD_CORE VSS / RM_IHPSG13_512x16_c2_2P_BITKIT_CELL +XCELL<18> A_RBLC<2> A_RBLC<3> A_RBLT<2> A_RBLT<3> A_XWL<2> A_RWL<2> B_RBLC<2> ++ B_RBLC<3> B_RBLT<2> B_RBLT<3> B_XWL<2> B_RWL<2> VDD_CORE VSS ++ VDD_CORE VSS / RM_IHPSG13_512x16_c2_2P_BITKIT_CELL +XCELL<17> A_RBLC<2> A_RBLC<1> A_RBLT<2> A_RBLT<1> A_XWL<1> A_RWL<1> B_RBLC<2> ++ B_RBLC<1> B_RBLT<2> B_RBLT<1> B_XWL<1> B_RWL<1> VDD_CORE VSS ++ VDD_CORE VSS / RM_IHPSG13_512x16_c2_2P_BITKIT_CELL +XCELL<16> A_BLC_BOT<1> A_RBLC<1> A_BLT_BOT<1> A_RBLT<1> A_XWL<0> A_RWL<0> ++ B_BLC_BOT<1> B_RBLC<1> B_BLT_BOT<1> B_RBLT<1> B_XWL<0> B_RWL<0> VDD_CORE ++ VSS VDD_CORE VSS / RM_IHPSG13_512x16_c2_2P_BITKIT_CELL +XCELL<15> A_BLC_TOP<0> A_LBLC<15> A_BLT_TOP<0> A_LBLT<15> A_LWL<15> A_XWL<15> ++ B_BLC_TOP<0> B_LBLC<15> B_BLT_TOP<0> B_LBLT<15> B_LWL<15> B_XWL<15> ++ VDD_CORE VSS VDD_CORE VSS / ++ RM_IHPSG13_512x16_c2_2P_BITKIT_CELL +XCELL<14> A_LBLC<14> A_LBLC<15> A_LBLT<14> A_LBLT<15> A_LWL<14> A_XWL<14> ++ B_LBLC<14> B_LBLC<15> B_LBLT<14> B_LBLT<15> B_LWL<14> B_XWL<14> VDD_CORE ++ VSS VDD_CORE VSS / RM_IHPSG13_512x16_c2_2P_BITKIT_CELL +XCELL<13> A_LBLC<14> A_LBLC<13> A_LBLT<14> A_LBLT<13> A_LWL<13> A_XWL<13> ++ B_LBLC<14> B_LBLC<13> B_LBLT<14> B_LBLT<13> B_LWL<13> B_XWL<13> VDD_CORE ++ VSS VDD_CORE VSS / RM_IHPSG13_512x16_c2_2P_BITKIT_CELL +XCELL<12> A_LBLC<12> A_LBLC<13> A_LBLT<12> A_LBLT<13> A_LWL<12> A_XWL<12> ++ B_LBLC<12> B_LBLC<13> B_LBLT<12> B_LBLT<13> B_LWL<12> B_XWL<12> VDD_CORE ++ VSS VDD_CORE VSS / RM_IHPSG13_512x16_c2_2P_BITKIT_CELL +XCELL<11> A_LBLC<12> A_LBLC<11> A_LBLT<12> A_LBLT<11> A_LWL<11> A_XWL<11> ++ B_LBLC<12> B_LBLC<11> B_LBLT<12> B_LBLT<11> B_LWL<11> B_XWL<11> VDD_CORE ++ VSS VDD_CORE VSS / RM_IHPSG13_512x16_c2_2P_BITKIT_CELL +XCELL<10> A_LBLC<10> A_LBLC<11> A_LBLT<10> A_LBLT<11> A_LWL<10> A_XWL<10> ++ B_LBLC<10> B_LBLC<11> B_LBLT<10> B_LBLT<11> B_LWL<10> B_XWL<10> VDD_CORE ++ VSS VDD_CORE VSS / RM_IHPSG13_512x16_c2_2P_BITKIT_CELL +XCELL<9> A_LBLC<10> A_LBLC<9> A_LBLT<10> A_LBLT<9> A_LWL<9> A_XWL<9> ++ B_LBLC<10> B_LBLC<9> B_LBLT<10> B_LBLT<9> B_LWL<9> B_XWL<9> VDD_CORE ++ VSS VDD_CORE VSS / RM_IHPSG13_512x16_c2_2P_BITKIT_CELL +XCELL<8> A_LBLC<8> A_LBLC<9> A_LBLT<8> A_LBLT<9> A_LWL<8> A_XWL<8> B_LBLC<8> ++ B_LBLC<9> B_LBLT<8> B_LBLT<9> B_LWL<8> B_XWL<8> VDD_CORE VSS ++ VDD_CORE VSS / RM_IHPSG13_512x16_c2_2P_BITKIT_CELL +XCELL<7> A_LBLC<8> A_LBLC<7> A_LBLT<8> A_LBLT<7> A_LWL<7> A_XWL<7> B_LBLC<8> ++ B_LBLC<7> B_LBLT<8> B_LBLT<7> B_LWL<7> B_XWL<7> VDD_CORE VSS ++ VDD_CORE VSS / RM_IHPSG13_512x16_c2_2P_BITKIT_CELL +XCELL<6> A_LBLC<6> A_LBLC<7> A_LBLT<6> A_LBLT<7> A_LWL<6> A_XWL<6> B_LBLC<6> ++ B_LBLC<7> B_LBLT<6> B_LBLT<7> B_LWL<6> B_XWL<6> VDD_CORE VSS ++ VDD_CORE VSS / RM_IHPSG13_512x16_c2_2P_BITKIT_CELL +XCELL<5> A_LBLC<6> A_LBLC<5> A_LBLT<6> A_LBLT<5> A_LWL<5> A_XWL<5> B_LBLC<6> ++ B_LBLC<5> B_LBLT<6> B_LBLT<5> B_LWL<5> B_XWL<5> VDD_CORE VSS ++ VDD_CORE VSS / RM_IHPSG13_512x16_c2_2P_BITKIT_CELL +XCELL<4> A_LBLC<4> A_LBLC<5> A_LBLT<4> A_LBLT<5> A_LWL<4> A_XWL<4> B_LBLC<4> ++ B_LBLC<5> B_LBLT<4> B_LBLT<5> B_LWL<4> B_XWL<4> VDD_CORE VSS ++ VDD_CORE VSS / RM_IHPSG13_512x16_c2_2P_BITKIT_CELL +XCELL<3> A_LBLC<4> A_LBLC<3> A_LBLT<4> A_LBLT<3> A_LWL<3> A_XWL<3> B_LBLC<4> ++ B_LBLC<3> B_LBLT<4> B_LBLT<3> B_LWL<3> B_XWL<3> VDD_CORE VSS ++ VDD_CORE VSS / RM_IHPSG13_512x16_c2_2P_BITKIT_CELL +XCELL<2> A_LBLC<2> A_LBLC<3> A_LBLT<2> A_LBLT<3> A_LWL<2> A_XWL<2> B_LBLC<2> ++ B_LBLC<3> B_LBLT<2> B_LBLT<3> B_LWL<2> B_XWL<2> VDD_CORE VSS ++ VDD_CORE VSS / RM_IHPSG13_512x16_c2_2P_BITKIT_CELL +XCELL<1> A_LBLC<2> A_LBLC<1> A_LBLT<2> A_LBLT<1> A_LWL<1> A_XWL<1> B_LBLC<2> ++ B_LBLC<1> B_LBLT<2> B_LBLT<1> B_LWL<1> B_XWL<1> VDD_CORE VSS ++ VDD_CORE VSS / RM_IHPSG13_512x16_c2_2P_BITKIT_CELL +XCELL<0> A_BLC_BOT<0> A_LBLC<1> A_BLT_BOT<0> A_LBLT<1> A_LWL<0> A_XWL<0> ++ B_BLC_BOT<0> B_LBLC<1> B_BLT_BOT<0> B_LBLT<1> B_LWL<0> B_XWL<0> VDD_CORE ++ VSS VDD_CORE VSS / RM_IHPSG13_512x16_c2_2P_BITKIT_CELL +.ENDS +.SUBCKT RM_IHPSG13_512x16_c2_2P_BITKIT_EDGE_TB A_BLC A_BLT B_BLC B_BLT NW PW VDD VSS +.ENDS +.SUBCKT RM_IHPSG13_512x16_c2_2P_BITKIT_16x2_EDGE_TB A_BLC<1> A_BLC<0> A_BLT<1> A_BLT<0> ++ B_BLC<1> B_BLC<0> B_BLT<1> B_BLT<0> VDD_CORE VSS +XEDGE<1> A_BLC<1> A_BLT<1> B_BLC<1> B_BLT<1> VDD_CORE VSS ++ VDD_CORE VSS / RM_IHPSG13_512x16_c2_2P_BITKIT_EDGE_TB +XEDGE<0> A_BLC<0> A_BLT<0> B_BLC<0> B_BLT<0> VDD_CORE VSS ++ VDD_CORE VSS / RM_IHPSG13_512x16_c2_2P_BITKIT_EDGE_TB +.ENDS +.SUBCKT RM_IHPSG13_512x16_c2_2P_BITKIT_TAP A_BLC A_BLT B_BLC B_BLT NW PW VDD VSS +.ENDS +.SUBCKT RM_IHPSG13_512x16_c2_2P_BITKIT_16x2_TAP A_BLC<1> A_BLC<0> A_BLT<1> A_BLT<0> ++ B_BLC<1> B_BLC<0> B_BLT<1> B_BLT<0> VDD_CORE VSS +XIEDGEBP_COL1<1> A_BLC<1> A_BLT<1> B_BLC<1> B_BLT<1> VDD_CORE VSS ++ VDD_CORE VSS / RM_IHPSG13_512x16_c2_2P_BITKIT_EDGE_TB +XIEDGEBP_COL1<0> A_BLC<1> A_BLT<1> B_BLC<1> B_BLT<1> VDD_CORE VSS ++ VDD_CORE VSS / RM_IHPSG13_512x16_c2_2P_BITKIT_EDGE_TB +XIEDGEBP_COL2<1> A_BLC<0> A_BLT<0> B_BLC<0> B_BLT<0> VDD_CORE VSS ++ VDD_CORE VSS / RM_IHPSG13_512x16_c2_2P_BITKIT_EDGE_TB +XIEDGEBP_COL2<0> A_BLC<0> A_BLT<0> B_BLC<0> B_BLT<0> VDD_CORE VSS ++ VDD_CORE VSS / RM_IHPSG13_512x16_c2_2P_BITKIT_EDGE_TB +XITAP<1> A_BLC<1> A_BLT<1> B_BLC<1> B_BLT<1> VDD_CORE VSS ++ VDD_CORE VSS / RM_IHPSG13_512x16_c2_2P_BITKIT_TAP +XITAP<0> A_BLC<0> A_BLT<0> B_BLC<0> B_BLT<0> VDD_CORE VSS ++ VDD_CORE VSS / RM_IHPSG13_512x16_c2_2P_BITKIT_TAP +.ENDS + + +.SUBCKT RM_IHPSG13_512x16_c2_1P_BITKIT_TAP_LR NW PW VDD VSS +.ENDS +.SUBCKT RM_IHPSG13_512x16_c2_2P_BITKIT_16x2_TAP_LR VDD_CORE VSS +XCORNER<1> VDD_CORE VSS VDD_CORE VSS / ++ RM_IHPSG13_512x16_c2_1P_BITKIT_CORNER +XCORNER<0> VDD_CORE VSS VDD_CORE VSS / ++ RM_IHPSG13_512x16_c2_1P_BITKIT_CORNER +XTAP_BORDER VDD_CORE VSS VDD_CORE VSS / ++ RM_IHPSG13_512x16_c2_1P_BITKIT_TAP_LR +.ENDS + +.SUBCKT RSC_IHPSG13_CBUFX12 A Z VDD VSS +MN1 Z net6 VSS VSS sg13_lv_nmos m=1 w=4.23u l=130.00n ng=6 nrd=0 nrs=0 +MN0 net6 A VSS VSS sg13_lv_nmos m=1 w=1.41u l=130.00n ng=2 nrd=0 nrs=0 +MP1 Z net6 VDD VDD sg13_lv_pmos m=1 w=9.72u l=130.00n ng=6 nrd=0 nrs=0 +MP0 net6 A VDD VDD sg13_lv_pmos m=1 w=3.24u l=130.00n ng=2 nrd=0 nrs=0 +.ENDS +.SUBCKT RM_IHPSG13_512x16_c2_2P_COLDRV13X12 ADDR_COL_I<1> ADDR_COL_I<0> ADDR_COL_O<1> ++ ADDR_COL_O<0> ADDR_DEC_I<7> ADDR_DEC_I<6> ADDR_DEC_I<5> ADDR_DEC_I<4> ++ ADDR_DEC_I<3> ADDR_DEC_I<2> ADDR_DEC_I<1> ADDR_DEC_I<0> ADDR_DEC_O<7> ++ ADDR_DEC_O<6> ADDR_DEC_O<5> ADDR_DEC_O<4> ADDR_DEC_O<3> ADDR_DEC_O<2> ++ ADDR_DEC_O<1> ADDR_DEC_O<0> DCLK_I DCLK_O RCLK_I RCLK_O WCLK_I WCLK_O ++ VDD VSS +XI1<3> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI1<2> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI1<1> VDD VSS / RSC_IHPSG13_FILLCAP8 +XWCLK_DRV WCLK_I WCLK_O VDD VSS / RSC_IHPSG13_CBUFX12 +XRCLK_DRV RCLK_I RCLK_O VDD VSS / RSC_IHPSG13_CBUFX12 +XDCLK_DRV DCLK_I DCLK_O VDD VSS / RSC_IHPSG13_CBUFX12 +XADDR_COL_DRV<1> ADDR_COL_I<1> ADDR_COL_O<1> VDD VSS / ++ RSC_IHPSG13_CBUFX12 +XADDR_COL_DRV<0> ADDR_COL_I<0> ADDR_COL_O<0> VDD VSS / ++ RSC_IHPSG13_CBUFX12 +XADDR_DEC_DRV<7> ADDR_DEC_I<7> ADDR_DEC_O<7> VDD VSS / ++ RSC_IHPSG13_CBUFX12 +XADDR_DEC_DRV<6> ADDR_DEC_I<6> ADDR_DEC_O<6> VDD VSS / ++ RSC_IHPSG13_CBUFX12 +XADDR_DEC_DRV<5> ADDR_DEC_I<5> ADDR_DEC_O<5> VDD VSS / ++ RSC_IHPSG13_CBUFX12 +XADDR_DEC_DRV<4> ADDR_DEC_I<4> ADDR_DEC_O<4> VDD VSS / ++ RSC_IHPSG13_CBUFX12 +XADDR_DEC_DRV<3> ADDR_DEC_I<3> ADDR_DEC_O<3> VDD VSS / ++ RSC_IHPSG13_CBUFX12 +XADDR_DEC_DRV<2> ADDR_DEC_I<2> ADDR_DEC_O<2> VDD VSS / ++ RSC_IHPSG13_CBUFX12 +XADDR_DEC_DRV<1> ADDR_DEC_I<1> ADDR_DEC_O<1> VDD VSS / ++ RSC_IHPSG13_CBUFX12 +XADDR_DEC_DRV<0> ADDR_DEC_I<0> ADDR_DEC_O<0> VDD VSS / ++ RSC_IHPSG13_CBUFX12 +XI0<6> VDD VSS / RSC_IHPSG13_FILLCAP4 +XI0<5> VDD VSS / RSC_IHPSG13_FILLCAP4 +XI0<4> VDD VSS / RSC_IHPSG13_FILLCAP4 +XI0<3> VDD VSS / RSC_IHPSG13_FILLCAP4 +XI0<2> VDD VSS / RSC_IHPSG13_FILLCAP4 +XI0<1> VDD VSS / RSC_IHPSG13_FILLCAP4 +.ENDS +.SUBCKT RSC_IHPSG13_WLDRVX12 A Z VDD VSS +MN1 Z net6 VSS VSS sg13_lv_nmos m=1 w=1.41u l=130.00n ng=2 nrd=0 nrs=0 +MN0 net6 A VSS VSS sg13_lv_nmos m=1 w=1.8u l=130.00n ng=2 nrd=0 nrs=0 +MP1 Z net6 VDD VDD sg13_lv_pmos m=1 w=9.72u l=130.00n ng=6 nrd=0 nrs=0 +MP0 net6 A VDD VDD sg13_lv_pmos m=1 w=900.0n l=130.00n ng=1 nrd=0 nrs=0 +.ENDS +.SUBCKT RM_IHPSG13_512x16_c2_2P_WLDRV16X12 A<15> A<14> A<13> A<12> A<11> A<10> A<9> A<8> ++ A<7> A<6> A<5> A<4> A<3> A<2> A<1> A<0> Z<15> Z<14> Z<13> Z<12> Z<11> Z<10> ++ Z<9> Z<8> Z<7> Z<6> Z<5> Z<4> Z<3> Z<2> Z<1> Z<0> VDD VSS +XBUF<15> A<15> Z<15> VDD VSS / RSC_IHPSG13_WLDRVX12 +XBUF<14> A<14> Z<14> VDD VSS / RSC_IHPSG13_WLDRVX12 +XBUF<13> A<13> Z<13> VDD VSS / RSC_IHPSG13_WLDRVX12 +XBUF<12> A<12> Z<12> VDD VSS / RSC_IHPSG13_WLDRVX12 +XBUF<11> A<11> Z<11> VDD VSS / RSC_IHPSG13_WLDRVX12 +XBUF<10> A<10> Z<10> VDD VSS / RSC_IHPSG13_WLDRVX12 +XBUF<9> A<9> Z<9> VDD VSS / RSC_IHPSG13_WLDRVX12 +XBUF<8> A<8> Z<8> VDD VSS / RSC_IHPSG13_WLDRVX12 +XBUF<7> A<7> Z<7> VDD VSS / RSC_IHPSG13_WLDRVX12 +XBUF<6> A<6> Z<6> VDD VSS / RSC_IHPSG13_WLDRVX12 +XBUF<5> A<5> Z<5> VDD VSS / RSC_IHPSG13_WLDRVX12 +XBUF<4> A<4> Z<4> VDD VSS / RSC_IHPSG13_WLDRVX12 +XBUF<3> A<3> Z<3> VDD VSS / RSC_IHPSG13_WLDRVX12 +XBUF<2> A<2> Z<2> VDD VSS / RSC_IHPSG13_WLDRVX12 +XBUF<1> A<1> Z<1> VDD VSS / RSC_IHPSG13_WLDRVX12 +XBUF<0> A<0> Z<0> VDD VSS / RSC_IHPSG13_WLDRVX12 +.ENDS +.SUBCKT RM_IHPSG13_512x16_c2_2P_DEC04 ADDR<3> ADDR<2> ADDR<1> ADDR<0> CS ECLK_H_BOT ++ ECLK_H_TOP ECLK_L_BOT ECLK_L_TOP WL<15> WL<14> WL<13> WL<12> WL<11> WL<10> ++ WL<9> WL<8> WL<7> WL<6> WL<5> WL<4> WL<3> WL<2> WL<1> WL<0> VDD VSS +XI0<3> PADR<1> PADR<0> sel01<3> VDD VSS / RSC_IHPSG13_NAND2X2 +XI0<2> PADR<1> NADR<0> sel01<2> VDD VSS / RSC_IHPSG13_NAND2X2 +XI0<1> NADR<1> PADR<0> sel01<1> VDD VSS / RSC_IHPSG13_NAND2X2 +XI0<0> NADR<1> NADR<0> sel01<0> VDD VSS / RSC_IHPSG13_NAND2X2 +XI4 ECLK_L_BOT EN VDD VSS / RSC_IHPSG13_CINVX4 +XI5 ECLK_H_BOT ECLK_L_BOT VDD VSS / RSC_IHPSG13_CINVX2 +XI3<3> PADR<3> NADR<3> VDD VSS / RSC_IHPSG13_INVX2 +XI3<2> PADR<2> NADR<2> VDD VSS / RSC_IHPSG13_INVX2 +XI3<1> PADR<1> NADR<1> VDD VSS / RSC_IHPSG13_INVX2 +XI3<0> PADR<0> NADR<0> VDD VSS / RSC_IHPSG13_INVX2 +XR0 ECLK_H_BOT ECLK_H_TOP / RSC_IHPSG13_MET2RES +XI11 ECLK_L_BOT ECLK_L_TOP / RSC_IHPSG13_MET2RES +XI1<3> PADR<2> PADR<3> CS sel23<3> VDD VSS / RSC_IHPSG13_NAND3X2 +XI1<2> NADR<2> PADR<3> CS sel23<2> VDD VSS / RSC_IHPSG13_NAND3X2 +XI1<1> PADR<2> NADR<3> CS sel23<1> VDD VSS / RSC_IHPSG13_NAND3X2 +XI1<0> NADR<2> NADR<3> CS sel23<0> VDD VSS / RSC_IHPSG13_NAND3X2 +XI2<15> sel23<3> sel01<3> EN WL<15> VDD VSS / RSC_IHPSG13_NOR3X2 +XI2<14> sel23<3> sel01<2> EN WL<14> VDD VSS / RSC_IHPSG13_NOR3X2 +XI2<13> sel23<3> sel01<1> EN WL<13> VDD VSS / RSC_IHPSG13_NOR3X2 +XI2<12> sel23<3> sel01<0> EN WL<12> VDD VSS / RSC_IHPSG13_NOR3X2 +XI2<11> sel23<2> sel01<3> EN WL<11> VDD VSS / RSC_IHPSG13_NOR3X2 +XI2<10> sel23<2> sel01<2> EN WL<10> VDD VSS / RSC_IHPSG13_NOR3X2 +XI2<9> sel23<2> sel01<1> EN WL<9> VDD VSS / RSC_IHPSG13_NOR3X2 +XI2<8> sel23<2> sel01<0> EN WL<8> VDD VSS / RSC_IHPSG13_NOR3X2 +XI2<7> sel23<1> sel01<3> EN WL<7> VDD VSS / RSC_IHPSG13_NOR3X2 +XI2<6> sel23<1> sel01<2> EN WL<6> VDD VSS / RSC_IHPSG13_NOR3X2 +XI2<5> sel23<1> sel01<1> EN WL<5> VDD VSS / RSC_IHPSG13_NOR3X2 +XI2<4> sel23<1> sel01<0> EN WL<4> VDD VSS / RSC_IHPSG13_NOR3X2 +XI2<3> sel23<0> sel01<3> EN WL<3> VDD VSS / RSC_IHPSG13_NOR3X2 +XI2<2> sel23<0> sel01<2> EN WL<2> VDD VSS / RSC_IHPSG13_NOR3X2 +XI2<1> sel23<0> sel01<1> EN WL<1> VDD VSS / RSC_IHPSG13_NOR3X2 +XI2<0> sel23<0> sel01<0> EN WL<0> VDD VSS / RSC_IHPSG13_NOR3X2 +XCAPS4 VDD VSS / RSC_IHPSG13_FILLCAP4 +XLATCH<3> CS ADDR<3> PADR<3> VDD VSS / RSC_IHPSG13_LHPQX2 +XLATCH<2> CS ADDR<2> PADR<2> VDD VSS / RSC_IHPSG13_LHPQX2 +XLATCH<1> CS ADDR<1> PADR<1> VDD VSS / RSC_IHPSG13_LHPQX2 +XLATCH<0> CS ADDR<0> PADR<0> VDD VSS / RSC_IHPSG13_LHPQX2 +.ENDS +.SUBCKT RM_IHPSG13_512x16_c2_2P_DEC02 ADDR<1> ADDR<0> CS CS_OUT VDD VSS +XDEC ADDR<1> NADDR<0> CS net1 VDD VSS / RSC_IHPSG13_NAND3X2 +XADDRINV ADDR<0> NADDR<0> VDD VSS / RSC_IHPSG13_INVX2 +XDECINV net1 CS_OUT VDD VSS / RSC_IHPSG13_INVX4 +XI2<1> VDD VSS / RSC_IHPSG13_FILLCAP4 +XI2<0> VDD VSS / RSC_IHPSG13_FILLCAP4 +.ENDS +.SUBCKT RM_IHPSG13_512x16_c2_2P_DEC01 ADDR<1> ADDR<0> CS CS_OUT VDD VSS +XDEC NADDR<1> ADDR<0> CS net1 VDD VSS / RSC_IHPSG13_NAND3X2 +XADDRINV ADDR<1> NADDR<1> VDD VSS / RSC_IHPSG13_INVX2 +XDECINV net1 CS_OUT VDD VSS / RSC_IHPSG13_INVX4 +XI2<1> VDD VSS / RSC_IHPSG13_FILLCAP4 +XI2<0> VDD VSS / RSC_IHPSG13_FILLCAP4 +.ENDS +.SUBCKT RM_IHPSG13_512x16_c2_2P_DEC00 ADDR<1> ADDR<0> CS CS_OUT VDD VSS +XDEC NADDR<1> NADDR<0> CS net1 VDD VSS / RSC_IHPSG13_NAND3X2 +XADDRINV<1> ADDR<1> NADDR<1> VDD VSS / RSC_IHPSG13_INVX2 +XADDRINV<0> ADDR<0> NADDR<0> VDD VSS / RSC_IHPSG13_INVX2 +XI1<1> VDD VSS / RSC_IHPSG13_FILLCAP4 +XI1<0> VDD VSS / RSC_IHPSG13_FILLCAP4 +XDECINV net1 CS_OUT VDD VSS / RSC_IHPSG13_INVX4 +.ENDS +.SUBCKT RM_IHPSG13_512x16_c2_2P_DEC03 ADDR<1> ADDR<0> CS CS_OUT VDD VSS +XDEC ADDR<1> ADDR<0> CS net1 VDD VSS / RSC_IHPSG13_NAND3X2 +XDECINV net1 CS_OUT VDD VSS / RSC_IHPSG13_INVX4 +XI0<1> VDD VSS / RSC_IHPSG13_FILLCAP4 +XI0<0> VDD VSS / RSC_IHPSG13_FILLCAP4 +.ENDS +.SUBCKT RM_IHPSG13_512x16_c2_2P_ROWDEC9 ADDR_N_I<8> ADDR_N_I<7> ADDR_N_I<6> ADDR_N_I<5> ++ ADDR_N_I<4> ADDR_N_I<3> ADDR_N_I<2> ADDR_N_I<1> ADDR_N_I<0> CS_I ECLK_I ++ WL_O<511> WL_O<510> WL_O<509> WL_O<508> WL_O<507> WL_O<506> WL_O<505> ++ WL_O<504> WL_O<503> WL_O<502> WL_O<501> WL_O<500> WL_O<499> WL_O<498> ++ WL_O<497> WL_O<496> WL_O<495> WL_O<494> WL_O<493> WL_O<492> WL_O<491> ++ WL_O<490> WL_O<489> WL_O<488> WL_O<487> WL_O<486> WL_O<485> WL_O<484> ++ WL_O<483> WL_O<482> WL_O<481> WL_O<480> WL_O<479> WL_O<478> WL_O<477> ++ WL_O<476> WL_O<475> WL_O<474> WL_O<473> WL_O<472> WL_O<471> WL_O<470> ++ WL_O<469> WL_O<468> WL_O<467> WL_O<466> WL_O<465> WL_O<464> WL_O<463> ++ WL_O<462> WL_O<461> WL_O<460> WL_O<459> WL_O<458> WL_O<457> WL_O<456> ++ WL_O<455> WL_O<454> WL_O<453> WL_O<452> WL_O<451> WL_O<450> WL_O<449> ++ WL_O<448> WL_O<447> WL_O<446> WL_O<445> WL_O<444> WL_O<443> WL_O<442> ++ WL_O<441> WL_O<440> WL_O<439> WL_O<438> WL_O<437> WL_O<436> WL_O<435> ++ WL_O<434> WL_O<433> WL_O<432> WL_O<431> WL_O<430> WL_O<429> WL_O<428> ++ WL_O<427> WL_O<426> WL_O<425> WL_O<424> WL_O<423> WL_O<422> WL_O<421> ++ WL_O<420> WL_O<419> WL_O<418> WL_O<417> WL_O<416> WL_O<415> WL_O<414> ++ WL_O<413> WL_O<412> WL_O<411> WL_O<410> WL_O<409> WL_O<408> WL_O<407> ++ WL_O<406> WL_O<405> WL_O<404> WL_O<403> WL_O<402> WL_O<401> WL_O<400> ++ WL_O<399> WL_O<398> WL_O<397> WL_O<396> WL_O<395> WL_O<394> WL_O<393> ++ WL_O<392> WL_O<391> WL_O<390> WL_O<389> WL_O<388> WL_O<387> WL_O<386> ++ WL_O<385> WL_O<384> WL_O<383> WL_O<382> WL_O<381> WL_O<380> WL_O<379> ++ WL_O<378> WL_O<377> WL_O<376> WL_O<375> WL_O<374> WL_O<373> WL_O<372> ++ WL_O<371> WL_O<370> WL_O<369> WL_O<368> WL_O<367> WL_O<366> WL_O<365> ++ WL_O<364> WL_O<363> WL_O<362> WL_O<361> WL_O<360> WL_O<359> WL_O<358> ++ WL_O<357> WL_O<356> WL_O<355> WL_O<354> WL_O<353> WL_O<352> WL_O<351> ++ WL_O<350> WL_O<349> WL_O<348> WL_O<347> WL_O<346> WL_O<345> WL_O<344> ++ WL_O<343> WL_O<342> WL_O<341> WL_O<340> WL_O<339> WL_O<338> WL_O<337> ++ WL_O<336> WL_O<335> WL_O<334> WL_O<333> WL_O<332> WL_O<331> WL_O<330> ++ WL_O<329> WL_O<328> WL_O<327> WL_O<326> WL_O<325> WL_O<324> WL_O<323> ++ WL_O<322> WL_O<321> WL_O<320> WL_O<319> WL_O<318> WL_O<317> WL_O<316> ++ WL_O<315> WL_O<314> WL_O<313> WL_O<312> WL_O<311> WL_O<310> WL_O<309> ++ WL_O<308> WL_O<307> WL_O<306> WL_O<305> WL_O<304> WL_O<303> WL_O<302> ++ WL_O<301> WL_O<300> WL_O<299> WL_O<298> WL_O<297> WL_O<296> WL_O<295> ++ WL_O<294> WL_O<293> WL_O<292> WL_O<291> WL_O<290> WL_O<289> WL_O<288> ++ WL_O<287> WL_O<286> WL_O<285> WL_O<284> WL_O<283> WL_O<282> WL_O<281> ++ WL_O<280> WL_O<279> WL_O<278> WL_O<277> WL_O<276> WL_O<275> WL_O<274> ++ WL_O<273> WL_O<272> WL_O<271> WL_O<270> WL_O<269> WL_O<268> WL_O<267> ++ WL_O<266> WL_O<265> WL_O<264> WL_O<263> WL_O<262> WL_O<261> WL_O<260> ++ WL_O<259> WL_O<258> WL_O<257> WL_O<256> WL_O<255> WL_O<254> WL_O<253> ++ WL_O<252> WL_O<251> WL_O<250> WL_O<249> WL_O<248> WL_O<247> WL_O<246> ++ WL_O<245> WL_O<244> WL_O<243> WL_O<242> WL_O<241> WL_O<240> WL_O<239> ++ WL_O<238> WL_O<237> WL_O<236> WL_O<235> WL_O<234> WL_O<233> WL_O<232> ++ WL_O<231> WL_O<230> WL_O<229> WL_O<228> WL_O<227> WL_O<226> WL_O<225> ++ WL_O<224> WL_O<223> WL_O<222> WL_O<221> WL_O<220> WL_O<219> WL_O<218> ++ WL_O<217> WL_O<216> WL_O<215> WL_O<214> WL_O<213> WL_O<212> WL_O<211> ++ WL_O<210> WL_O<209> WL_O<208> WL_O<207> WL_O<206> WL_O<205> WL_O<204> ++ WL_O<203> WL_O<202> WL_O<201> WL_O<200> WL_O<199> WL_O<198> WL_O<197> ++ WL_O<196> WL_O<195> WL_O<194> WL_O<193> WL_O<192> WL_O<191> WL_O<190> ++ WL_O<189> WL_O<188> WL_O<187> WL_O<186> WL_O<185> WL_O<184> WL_O<183> ++ WL_O<182> WL_O<181> WL_O<180> WL_O<179> WL_O<178> WL_O<177> WL_O<176> ++ WL_O<175> WL_O<174> WL_O<173> WL_O<172> WL_O<171> WL_O<170> WL_O<169> ++ WL_O<168> WL_O<167> WL_O<166> WL_O<165> WL_O<164> WL_O<163> WL_O<162> ++ WL_O<161> WL_O<160> WL_O<159> WL_O<158> WL_O<157> WL_O<156> WL_O<155> ++ WL_O<154> WL_O<153> WL_O<152> WL_O<151> WL_O<150> WL_O<149> WL_O<148> ++ WL_O<147> WL_O<146> WL_O<145> WL_O<144> WL_O<143> WL_O<142> WL_O<141> ++ WL_O<140> WL_O<139> WL_O<138> WL_O<137> WL_O<136> WL_O<135> WL_O<134> ++ WL_O<133> WL_O<132> WL_O<131> WL_O<130> WL_O<129> WL_O<128> WL_O<127> ++ WL_O<126> WL_O<125> WL_O<124> WL_O<123> WL_O<122> WL_O<121> WL_O<120> ++ WL_O<119> WL_O<118> WL_O<117> WL_O<116> WL_O<115> WL_O<114> WL_O<113> ++ WL_O<112> WL_O<111> WL_O<110> WL_O<109> WL_O<108> WL_O<107> WL_O<106> ++ WL_O<105> WL_O<104> WL_O<103> WL_O<102> WL_O<101> WL_O<100> WL_O<99> ++ WL_O<98> WL_O<97> WL_O<96> WL_O<95> WL_O<94> WL_O<93> WL_O<92> WL_O<91> ++ WL_O<90> WL_O<89> WL_O<88> WL_O<87> WL_O<86> WL_O<85> WL_O<84> WL_O<83> ++ WL_O<82> WL_O<81> WL_O<80> WL_O<79> WL_O<78> WL_O<77> WL_O<76> WL_O<75> ++ WL_O<74> WL_O<73> WL_O<72> WL_O<71> WL_O<70> WL_O<69> WL_O<68> WL_O<67> ++ WL_O<66> WL_O<65> WL_O<64> WL_O<63> WL_O<62> WL_O<61> WL_O<60> WL_O<59> ++ WL_O<58> WL_O<57> WL_O<56> WL_O<55> WL_O<54> WL_O<53> WL_O<52> WL_O<51> ++ WL_O<50> WL_O<49> WL_O<48> WL_O<47> WL_O<46> WL_O<45> WL_O<44> WL_O<43> ++ WL_O<42> WL_O<41> WL_O<40> WL_O<39> WL_O<38> WL_O<37> WL_O<36> WL_O<35> ++ WL_O<34> WL_O<33> WL_O<32> WL_O<31> WL_O<30> WL_O<29> WL_O<28> WL_O<27> ++ WL_O<26> WL_O<25> WL_O<24> WL_O<23> WL_O<22> WL_O<21> WL_O<20> WL_O<19> ++ WL_O<18> WL_O<17> WL_O<16> WL_O<15> WL_O<14> WL_O<13> WL_O<12> WL_O<11> ++ WL_O<10> WL_O<9> WL_O<8> WL_O<7> WL_O<6> WL_O<5> WL_O<4> WL_O<3> WL_O<2> ++ WL_O<1> WL_O<0> VDD VSS +XSEL<31> ADDR_N_I<3> ADDR_N_I<2> ADDR_N_I<1> ADDR_N_I<0> CS00<31> ECLK_H<31> ++ ECLK_H<32> ECLK_B<31> ECLK_B<32> WL_O<511> WL_O<510> WL_O<509> WL_O<508> ++ WL_O<507> WL_O<506> WL_O<505> WL_O<504> WL_O<503> WL_O<502> WL_O<501> ++ WL_O<500> WL_O<499> WL_O<498> WL_O<497> WL_O<496> VDD VSS / ++ RM_IHPSG13_512x16_c2_2P_DEC04 +XSEL<30> ADDR_N_I<3> ADDR_N_I<2> ADDR_N_I<1> ADDR_N_I<0> CS00<30> ECLK_H<30> ++ ECLK_H<31> ECLK_B<30> ECLK_B<31> WL_O<495> WL_O<494> WL_O<493> WL_O<492> ++ WL_O<491> WL_O<490> WL_O<489> WL_O<488> WL_O<487> WL_O<486> WL_O<485> ++ WL_O<484> WL_O<483> WL_O<482> WL_O<481> WL_O<480> VDD VSS / ++ RM_IHPSG13_512x16_c2_2P_DEC04 +XSEL<29> ADDR_N_I<3> ADDR_N_I<2> ADDR_N_I<1> ADDR_N_I<0> CS00<29> ECLK_H<29> ++ ECLK_H<30> ECLK_B<29> ECLK_B<30> WL_O<479> WL_O<478> WL_O<477> WL_O<476> ++ WL_O<475> WL_O<474> WL_O<473> WL_O<472> WL_O<471> WL_O<470> WL_O<469> ++ WL_O<468> WL_O<467> WL_O<466> WL_O<465> WL_O<464> VDD VSS / ++ RM_IHPSG13_512x16_c2_2P_DEC04 +XSEL<28> ADDR_N_I<3> ADDR_N_I<2> ADDR_N_I<1> ADDR_N_I<0> CS00<28> ECLK_H<28> ++ ECLK_H<29> ECLK_B<28> ECLK_B<29> WL_O<463> WL_O<462> WL_O<461> WL_O<460> ++ WL_O<459> WL_O<458> WL_O<457> WL_O<456> WL_O<455> WL_O<454> WL_O<453> ++ WL_O<452> WL_O<451> WL_O<450> WL_O<449> WL_O<448> VDD VSS / ++ RM_IHPSG13_512x16_c2_2P_DEC04 +XSEL<27> ADDR_N_I<3> ADDR_N_I<2> ADDR_N_I<1> ADDR_N_I<0> CS00<27> ECLK_H<27> ++ ECLK_H<28> ECLK_B<27> ECLK_B<28> WL_O<447> WL_O<446> WL_O<445> WL_O<444> ++ WL_O<443> WL_O<442> WL_O<441> WL_O<440> WL_O<439> WL_O<438> WL_O<437> ++ WL_O<436> WL_O<435> WL_O<434> WL_O<433> WL_O<432> VDD VSS / ++ RM_IHPSG13_512x16_c2_2P_DEC04 +XSEL<26> ADDR_N_I<3> ADDR_N_I<2> ADDR_N_I<1> ADDR_N_I<0> CS00<26> ECLK_H<26> ++ ECLK_H<27> ECLK_B<26> ECLK_B<27> WL_O<431> WL_O<430> WL_O<429> WL_O<428> ++ WL_O<427> WL_O<426> WL_O<425> WL_O<424> WL_O<423> WL_O<422> WL_O<421> ++ WL_O<420> WL_O<419> WL_O<418> WL_O<417> WL_O<416> VDD VSS / ++ RM_IHPSG13_512x16_c2_2P_DEC04 +XSEL<25> ADDR_N_I<3> ADDR_N_I<2> ADDR_N_I<1> ADDR_N_I<0> CS00<25> ECLK_H<25> ++ ECLK_H<26> ECLK_B<25> ECLK_B<26> WL_O<415> WL_O<414> WL_O<413> WL_O<412> ++ WL_O<411> WL_O<410> WL_O<409> WL_O<408> WL_O<407> WL_O<406> WL_O<405> ++ WL_O<404> WL_O<403> WL_O<402> WL_O<401> WL_O<400> VDD VSS / ++ RM_IHPSG13_512x16_c2_2P_DEC04 +XSEL<24> ADDR_N_I<3> ADDR_N_I<2> ADDR_N_I<1> ADDR_N_I<0> CS00<24> ECLK_H<24> ++ ECLK_H<25> ECLK_B<24> ECLK_B<25> WL_O<399> WL_O<398> WL_O<397> WL_O<396> ++ WL_O<395> WL_O<394> WL_O<393> WL_O<392> WL_O<391> WL_O<390> WL_O<389> ++ WL_O<388> WL_O<387> WL_O<386> WL_O<385> WL_O<384> VDD VSS / ++ RM_IHPSG13_512x16_c2_2P_DEC04 +XSEL<23> ADDR_N_I<3> ADDR_N_I<2> ADDR_N_I<1> ADDR_N_I<0> CS00<23> ECLK_H<23> ++ ECLK_H<24> ECLK_B<23> ECLK_B<24> WL_O<383> WL_O<382> WL_O<381> WL_O<380> ++ WL_O<379> WL_O<378> WL_O<377> WL_O<376> WL_O<375> WL_O<374> WL_O<373> ++ WL_O<372> WL_O<371> WL_O<370> WL_O<369> WL_O<368> VDD VSS / ++ RM_IHPSG13_512x16_c2_2P_DEC04 +XSEL<22> ADDR_N_I<3> ADDR_N_I<2> ADDR_N_I<1> ADDR_N_I<0> CS00<22> ECLK_H<22> ++ ECLK_H<23> ECLK_B<22> ECLK_B<23> WL_O<367> WL_O<366> WL_O<365> WL_O<364> ++ WL_O<363> WL_O<362> WL_O<361> WL_O<360> WL_O<359> WL_O<358> WL_O<357> ++ WL_O<356> WL_O<355> WL_O<354> WL_O<353> WL_O<352> VDD VSS / ++ RM_IHPSG13_512x16_c2_2P_DEC04 +XSEL<21> ADDR_N_I<3> ADDR_N_I<2> ADDR_N_I<1> ADDR_N_I<0> CS00<21> ECLK_H<21> ++ ECLK_H<22> ECLK_B<21> ECLK_B<22> WL_O<351> WL_O<350> WL_O<349> WL_O<348> ++ WL_O<347> WL_O<346> WL_O<345> WL_O<344> WL_O<343> WL_O<342> WL_O<341> ++ WL_O<340> WL_O<339> WL_O<338> WL_O<337> WL_O<336> VDD VSS / ++ RM_IHPSG13_512x16_c2_2P_DEC04 +XSEL<20> ADDR_N_I<3> ADDR_N_I<2> ADDR_N_I<1> ADDR_N_I<0> CS00<20> ECLK_H<20> ++ ECLK_H<21> ECLK_B<20> ECLK_B<21> WL_O<335> WL_O<334> WL_O<333> WL_O<332> ++ WL_O<331> WL_O<330> WL_O<329> WL_O<328> WL_O<327> WL_O<326> WL_O<325> ++ WL_O<324> WL_O<323> WL_O<322> WL_O<321> WL_O<320> VDD VSS / ++ RM_IHPSG13_512x16_c2_2P_DEC04 +XSEL<19> ADDR_N_I<3> ADDR_N_I<2> ADDR_N_I<1> ADDR_N_I<0> CS00<19> ECLK_H<19> ++ ECLK_H<20> ECLK_B<19> ECLK_B<20> WL_O<319> WL_O<318> WL_O<317> WL_O<316> ++ WL_O<315> WL_O<314> WL_O<313> WL_O<312> WL_O<311> WL_O<310> WL_O<309> ++ WL_O<308> WL_O<307> WL_O<306> WL_O<305> WL_O<304> VDD VSS / ++ RM_IHPSG13_512x16_c2_2P_DEC04 +XSEL<18> ADDR_N_I<3> ADDR_N_I<2> ADDR_N_I<1> ADDR_N_I<0> CS00<18> ECLK_H<18> ++ ECLK_H<19> ECLK_B<18> ECLK_B<19> WL_O<303> WL_O<302> WL_O<301> WL_O<300> ++ WL_O<299> WL_O<298> WL_O<297> WL_O<296> WL_O<295> WL_O<294> WL_O<293> ++ WL_O<292> WL_O<291> WL_O<290> WL_O<289> WL_O<288> VDD VSS / ++ RM_IHPSG13_512x16_c2_2P_DEC04 +XSEL<17> ADDR_N_I<3> ADDR_N_I<2> ADDR_N_I<1> ADDR_N_I<0> CS00<17> ECLK_H<17> ++ ECLK_H<18> ECLK_B<17> ECLK_B<18> WL_O<287> WL_O<286> WL_O<285> WL_O<284> ++ WL_O<283> WL_O<282> WL_O<281> WL_O<280> WL_O<279> WL_O<278> WL_O<277> ++ WL_O<276> WL_O<275> WL_O<274> WL_O<273> WL_O<272> VDD VSS / ++ RM_IHPSG13_512x16_c2_2P_DEC04 +XSEL<16> ADDR_N_I<3> ADDR_N_I<2> ADDR_N_I<1> ADDR_N_I<0> CS00<16> ECLK_H<16> ++ ECLK_H<17> ECLK_B<16> ECLK_B<17> WL_O<271> WL_O<270> WL_O<269> WL_O<268> ++ WL_O<267> WL_O<266> WL_O<265> WL_O<264> WL_O<263> WL_O<262> WL_O<261> ++ WL_O<260> WL_O<259> WL_O<258> WL_O<257> WL_O<256> VDD VSS / ++ RM_IHPSG13_512x16_c2_2P_DEC04 +XSEL<15> ADDR_N_I<3> ADDR_N_I<2> ADDR_N_I<1> ADDR_N_I<0> CS00<15> ECLK_H<15> ++ ECLK_H<16> ECLK_B<15> ECLK_B<16> WL_O<255> WL_O<254> WL_O<253> WL_O<252> ++ WL_O<251> WL_O<250> WL_O<249> WL_O<248> WL_O<247> WL_O<246> WL_O<245> ++ WL_O<244> WL_O<243> WL_O<242> WL_O<241> WL_O<240> VDD VSS / ++ RM_IHPSG13_512x16_c2_2P_DEC04 +XSEL<14> ADDR_N_I<3> ADDR_N_I<2> ADDR_N_I<1> ADDR_N_I<0> CS00<14> ECLK_H<14> ++ ECLK_H<15> ECLK_B<14> ECLK_B<15> WL_O<239> WL_O<238> WL_O<237> WL_O<236> ++ WL_O<235> WL_O<234> WL_O<233> WL_O<232> WL_O<231> WL_O<230> WL_O<229> ++ WL_O<228> WL_O<227> WL_O<226> WL_O<225> WL_O<224> VDD VSS / ++ RM_IHPSG13_512x16_c2_2P_DEC04 +XSEL<13> ADDR_N_I<3> ADDR_N_I<2> ADDR_N_I<1> ADDR_N_I<0> CS00<13> ECLK_H<13> ++ ECLK_H<14> ECLK_B<13> ECLK_B<14> WL_O<223> WL_O<222> WL_O<221> WL_O<220> ++ WL_O<219> WL_O<218> WL_O<217> WL_O<216> WL_O<215> WL_O<214> WL_O<213> ++ WL_O<212> WL_O<211> WL_O<210> WL_O<209> WL_O<208> VDD VSS / ++ RM_IHPSG13_512x16_c2_2P_DEC04 +XSEL<12> ADDR_N_I<3> ADDR_N_I<2> ADDR_N_I<1> ADDR_N_I<0> CS00<12> ECLK_H<12> ++ ECLK_H<13> ECLK_B<12> ECLK_B<13> WL_O<207> WL_O<206> WL_O<205> WL_O<204> ++ WL_O<203> WL_O<202> WL_O<201> WL_O<200> WL_O<199> WL_O<198> WL_O<197> ++ WL_O<196> WL_O<195> WL_O<194> WL_O<193> WL_O<192> VDD VSS / ++ RM_IHPSG13_512x16_c2_2P_DEC04 +XSEL<11> ADDR_N_I<3> ADDR_N_I<2> ADDR_N_I<1> ADDR_N_I<0> CS00<11> ECLK_H<11> ++ ECLK_H<12> ECLK_B<11> ECLK_B<12> WL_O<191> WL_O<190> WL_O<189> WL_O<188> ++ WL_O<187> WL_O<186> WL_O<185> WL_O<184> WL_O<183> WL_O<182> WL_O<181> ++ WL_O<180> WL_O<179> WL_O<178> WL_O<177> WL_O<176> VDD VSS / ++ RM_IHPSG13_512x16_c2_2P_DEC04 +XSEL<10> ADDR_N_I<3> ADDR_N_I<2> ADDR_N_I<1> ADDR_N_I<0> CS00<10> ECLK_H<10> ++ ECLK_H<11> ECLK_B<10> ECLK_B<11> WL_O<175> WL_O<174> WL_O<173> WL_O<172> ++ WL_O<171> WL_O<170> WL_O<169> WL_O<168> WL_O<167> WL_O<166> WL_O<165> ++ WL_O<164> WL_O<163> WL_O<162> WL_O<161> WL_O<160> VDD VSS / ++ RM_IHPSG13_512x16_c2_2P_DEC04 +XSEL<9> ADDR_N_I<3> ADDR_N_I<2> ADDR_N_I<1> ADDR_N_I<0> CS00<9> ECLK_H<9> ++ ECLK_H<10> ECLK_B<9> ECLK_B<10> WL_O<159> WL_O<158> WL_O<157> WL_O<156> ++ WL_O<155> WL_O<154> WL_O<153> WL_O<152> WL_O<151> WL_O<150> WL_O<149> ++ WL_O<148> WL_O<147> WL_O<146> WL_O<145> WL_O<144> VDD VSS / ++ RM_IHPSG13_512x16_c2_2P_DEC04 +XSEL<8> ADDR_N_I<3> ADDR_N_I<2> ADDR_N_I<1> ADDR_N_I<0> CS00<8> ECLK_H<8> ++ ECLK_H<9> ECLK_B<8> ECLK_B<9> WL_O<143> WL_O<142> WL_O<141> WL_O<140> ++ WL_O<139> WL_O<138> WL_O<137> WL_O<136> WL_O<135> WL_O<134> WL_O<133> ++ WL_O<132> WL_O<131> WL_O<130> WL_O<129> WL_O<128> VDD VSS / ++ RM_IHPSG13_512x16_c2_2P_DEC04 +XSEL<7> ADDR_N_I<3> ADDR_N_I<2> ADDR_N_I<1> ADDR_N_I<0> CS00<7> ECLK_H<7> ++ ECLK_H<8> ECLK_B<7> ECLK_B<8> WL_O<127> WL_O<126> WL_O<125> WL_O<124> ++ WL_O<123> WL_O<122> WL_O<121> WL_O<120> WL_O<119> WL_O<118> WL_O<117> ++ WL_O<116> WL_O<115> WL_O<114> WL_O<113> WL_O<112> VDD VSS / ++ RM_IHPSG13_512x16_c2_2P_DEC04 +XSEL<6> ADDR_N_I<3> ADDR_N_I<2> ADDR_N_I<1> ADDR_N_I<0> CS00<6> ECLK_H<6> ++ ECLK_H<7> ECLK_B<6> ECLK_B<7> WL_O<111> WL_O<110> WL_O<109> WL_O<108> ++ WL_O<107> WL_O<106> WL_O<105> WL_O<104> WL_O<103> WL_O<102> WL_O<101> ++ WL_O<100> WL_O<99> WL_O<98> WL_O<97> WL_O<96> VDD VSS / ++ RM_IHPSG13_512x16_c2_2P_DEC04 +XSEL<5> ADDR_N_I<3> ADDR_N_I<2> ADDR_N_I<1> ADDR_N_I<0> CS00<5> ECLK_H<5> ++ ECLK_H<6> ECLK_B<5> ECLK_B<6> WL_O<95> WL_O<94> WL_O<93> WL_O<92> WL_O<91> ++ WL_O<90> WL_O<89> WL_O<88> WL_O<87> WL_O<86> WL_O<85> WL_O<84> WL_O<83> ++ WL_O<82> WL_O<81> WL_O<80> VDD VSS / RM_IHPSG13_512x16_c2_2P_DEC04 +XSEL<4> ADDR_N_I<3> ADDR_N_I<2> ADDR_N_I<1> ADDR_N_I<0> CS00<4> ECLK_H<4> ++ ECLK_H<5> ECLK_B<4> ECLK_B<5> WL_O<79> WL_O<78> WL_O<77> WL_O<76> WL_O<75> ++ WL_O<74> WL_O<73> WL_O<72> WL_O<71> WL_O<70> WL_O<69> WL_O<68> WL_O<67> ++ WL_O<66> WL_O<65> WL_O<64> VDD VSS / RM_IHPSG13_512x16_c2_2P_DEC04 +XSEL<3> ADDR_N_I<3> ADDR_N_I<2> ADDR_N_I<1> ADDR_N_I<0> CS00<3> ECLK_H<3> ++ ECLK_H<4> ECLK_B<3> ECLK_B<4> WL_O<63> WL_O<62> WL_O<61> WL_O<60> WL_O<59> ++ WL_O<58> WL_O<57> WL_O<56> WL_O<55> WL_O<54> WL_O<53> WL_O<52> WL_O<51> ++ WL_O<50> WL_O<49> WL_O<48> VDD VSS / RM_IHPSG13_512x16_c2_2P_DEC04 +XSEL<2> ADDR_N_I<3> ADDR_N_I<2> ADDR_N_I<1> ADDR_N_I<0> CS00<2> ECLK_H<2> ++ ECLK_H<3> ECLK_B<2> ECLK_B<3> WL_O<47> WL_O<46> WL_O<45> WL_O<44> WL_O<43> ++ WL_O<42> WL_O<41> WL_O<40> WL_O<39> WL_O<38> WL_O<37> WL_O<36> WL_O<35> ++ WL_O<34> WL_O<33> WL_O<32> VDD VSS / RM_IHPSG13_512x16_c2_2P_DEC04 +XSEL<1> ADDR_N_I<3> ADDR_N_I<2> ADDR_N_I<1> ADDR_N_I<0> CS00<1> ECLK_H<1> ++ ECLK_H<2> ECLK_B<1> ECLK_B<2> WL_O<31> WL_O<30> WL_O<29> WL_O<28> WL_O<27> ++ WL_O<26> WL_O<25> WL_O<24> WL_O<23> WL_O<22> WL_O<21> WL_O<20> WL_O<19> ++ WL_O<18> WL_O<17> WL_O<16> VDD VSS / RM_IHPSG13_512x16_c2_2P_DEC04 +XSEL<0> ADDR_N_I<3> ADDR_N_I<2> ADDR_N_I<1> ADDR_N_I<0> CS00<0> ECLK_I ++ ECLK_H<1> ECLK_B<0> ECLK_B<1> WL_O<15> WL_O<14> WL_O<13> WL_O<12> WL_O<11> ++ WL_O<10> WL_O<9> WL_O<8> WL_O<7> WL_O<6> WL_O<5> WL_O<4> WL_O<3> WL_O<2> ++ WL_O<1> WL_O<0> VDD VSS / RM_IHPSG13_512x16_c2_2P_DEC04 +XDEC10<9> ADDR_N_I<7> ADDR_N_I<6> CS04<1> CS02<6> VDD VSS / ++ RM_IHPSG13_512x16_c2_2P_DEC02 +XDEC10<8> ADDR_N_I<7> ADDR_N_I<6> CS04<0> CS02<2> VDD VSS / ++ RM_IHPSG13_512x16_c2_2P_DEC02 +XDEC10<7> ADDR_N_I<5> ADDR_N_I<4> CS02<7> CS00<30> VDD VSS / ++ RM_IHPSG13_512x16_c2_2P_DEC02 +XDEC10<6> ADDR_N_I<5> ADDR_N_I<4> CS02<6> CS00<26> VDD VSS / ++ RM_IHPSG13_512x16_c2_2P_DEC02 +XDEC10<5> ADDR_N_I<5> ADDR_N_I<4> CS02<5> CS00<22> VDD VSS / ++ RM_IHPSG13_512x16_c2_2P_DEC02 +XDEC10<4> ADDR_N_I<5> ADDR_N_I<4> CS02<4> CS00<18> VDD VSS / ++ RM_IHPSG13_512x16_c2_2P_DEC02 +XDEC10<3> ADDR_N_I<5> ADDR_N_I<4> CS02<3> CS00<14> VDD VSS / ++ RM_IHPSG13_512x16_c2_2P_DEC02 +XDEC10<2> ADDR_N_I<5> ADDR_N_I<4> CS02<2> CS00<10> VDD VSS / ++ RM_IHPSG13_512x16_c2_2P_DEC02 +XDEC10<1> ADDR_N_I<5> ADDR_N_I<4> CS02<1> CS00<6> VDD VSS / ++ RM_IHPSG13_512x16_c2_2P_DEC02 +XDEC10<0> ADDR_N_I<5> ADDR_N_I<4> CS02<0> CS00<2> VDD VSS / ++ RM_IHPSG13_512x16_c2_2P_DEC02 +XDEC01<10> ADDR_N_I<9> ADDR_N_I<8> CS_I CS04<1> VDD VSS / ++ RM_IHPSG13_512x16_c2_2P_DEC01 +XDEC01<9> ADDR_N_I<7> ADDR_N_I<6> CS04<1> CS02<5> VDD VSS / ++ RM_IHPSG13_512x16_c2_2P_DEC01 +XDEC01<8> ADDR_N_I<7> ADDR_N_I<6> CS04<0> CS02<1> VDD VSS / ++ RM_IHPSG13_512x16_c2_2P_DEC01 +XDEC01<7> ADDR_N_I<5> ADDR_N_I<4> CS02<7> CS00<29> VDD VSS / ++ RM_IHPSG13_512x16_c2_2P_DEC01 +XDEC01<6> ADDR_N_I<5> ADDR_N_I<4> CS02<6> CS00<25> VDD VSS / ++ RM_IHPSG13_512x16_c2_2P_DEC01 +XDEC01<5> ADDR_N_I<5> ADDR_N_I<4> CS02<5> CS00<21> VDD VSS / ++ RM_IHPSG13_512x16_c2_2P_DEC01 +XDEC01<4> ADDR_N_I<5> ADDR_N_I<4> CS02<4> CS00<17> VDD VSS / ++ RM_IHPSG13_512x16_c2_2P_DEC01 +XDEC01<3> ADDR_N_I<5> ADDR_N_I<4> CS02<3> CS00<13> VDD VSS / ++ RM_IHPSG13_512x16_c2_2P_DEC01 +XDEC01<2> ADDR_N_I<5> ADDR_N_I<4> CS02<2> CS00<9> VDD VSS / ++ RM_IHPSG13_512x16_c2_2P_DEC01 +XDEC01<1> ADDR_N_I<5> ADDR_N_I<4> CS02<1> CS00<5> VDD VSS / ++ RM_IHPSG13_512x16_c2_2P_DEC01 +XDEC01<0> ADDR_N_I<5> ADDR_N_I<4> CS02<0> CS00<1> VDD VSS / ++ RM_IHPSG13_512x16_c2_2P_DEC01 +XL2<258> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<257> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<256> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<255> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<254> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<253> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<252> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<251> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<250> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<249> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<248> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<247> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<246> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<245> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<244> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<243> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<242> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<241> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<240> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<239> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<238> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<237> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<236> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<235> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<234> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<233> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<232> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<231> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<230> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<229> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<228> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<227> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<226> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<225> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<224> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<223> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<222> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<221> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<220> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<219> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<218> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<217> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<216> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<215> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<214> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<213> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<212> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<211> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<210> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<209> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<208> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<207> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<206> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<205> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<204> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<203> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<202> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<201> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<200> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<199> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<198> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<197> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<196> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<195> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<194> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<193> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<192> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<191> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<190> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<189> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<188> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<187> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<186> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<185> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<184> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<183> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<182> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<181> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<180> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<179> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<178> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<177> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<176> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<175> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<174> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<173> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<172> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<171> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<170> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<169> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<168> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<167> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<166> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<165> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<164> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<163> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<162> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<161> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<160> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<159> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<158> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<157> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<156> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<155> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<154> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<153> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<152> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<151> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<150> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<149> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<148> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<147> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<146> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<145> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<144> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<143> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<142> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<141> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<140> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<139> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<138> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<137> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<136> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<135> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<134> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<133> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<132> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<131> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<130> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<129> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<128> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<127> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<126> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<125> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<124> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<123> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<122> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<121> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<120> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<119> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<118> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<117> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<116> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<115> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<114> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<113> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<112> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<111> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<110> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<109> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<108> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<107> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<106> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<105> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<104> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<103> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<102> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<101> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<100> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<99> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<98> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<97> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<96> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<95> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<94> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<93> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<92> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<91> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<90> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<89> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<88> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<87> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<86> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<85> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<84> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<83> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<82> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<81> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<80> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<79> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<78> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<77> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<76> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<75> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<74> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<73> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<72> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<71> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<70> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<69> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<68> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<67> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<66> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<65> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<64> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<63> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<62> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<61> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<60> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<59> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<58> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<57> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<56> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<55> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<54> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<53> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<52> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<51> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<50> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<49> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<48> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<47> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<46> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<45> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<44> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<43> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<42> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<41> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<40> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<39> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<38> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<37> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<36> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<35> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<34> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<33> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<32> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<31> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<30> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<29> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<28> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<27> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<26> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<25> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<24> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<23> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<22> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<21> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<20> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<19> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<18> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<17> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<16> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<15> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<14> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<13> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<12> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<11> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<10> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<9> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<8> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<7> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<6> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<5> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<4> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<3> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<2> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<1> VDD VSS / RSC_IHPSG13_FILLCAP8 +XDEC00<10> ADDR_N_I<9> ADDR_N_I<8> CS_I CS04<0> VDD VSS / ++ RM_IHPSG13_512x16_c2_2P_DEC00 +XDEC00<9> ADDR_N_I<7> ADDR_N_I<6> CS04<1> CS02<4> VDD VSS / ++ RM_IHPSG13_512x16_c2_2P_DEC00 +XDEC00<8> ADDR_N_I<7> ADDR_N_I<6> CS04<0> CS02<0> VDD VSS / ++ RM_IHPSG13_512x16_c2_2P_DEC00 +XDEC00<7> ADDR_N_I<5> ADDR_N_I<4> CS02<7> CS00<28> VDD VSS / ++ RM_IHPSG13_512x16_c2_2P_DEC00 +XDEC00<6> ADDR_N_I<5> ADDR_N_I<4> CS02<6> CS00<24> VDD VSS / ++ RM_IHPSG13_512x16_c2_2P_DEC00 +XDEC00<5> ADDR_N_I<5> ADDR_N_I<4> CS02<5> CS00<20> VDD VSS / ++ RM_IHPSG13_512x16_c2_2P_DEC00 +XDEC00<4> ADDR_N_I<5> ADDR_N_I<4> CS02<4> CS00<16> VDD VSS / ++ RM_IHPSG13_512x16_c2_2P_DEC00 +XDEC00<3> ADDR_N_I<5> ADDR_N_I<4> CS02<3> CS00<12> VDD VSS / ++ RM_IHPSG13_512x16_c2_2P_DEC00 +XDEC00<2> ADDR_N_I<5> ADDR_N_I<4> CS02<2> CS00<8> VDD VSS / ++ RM_IHPSG13_512x16_c2_2P_DEC00 +XDEC00<1> ADDR_N_I<5> ADDR_N_I<4> CS02<1> CS00<4> VDD VSS / ++ RM_IHPSG13_512x16_c2_2P_DEC00 +XDEC00<0> ADDR_N_I<5> ADDR_N_I<4> CS02<0> CS00<0> VDD VSS / ++ RM_IHPSG13_512x16_c2_2P_DEC00 +XDEC11<9> ADDR_N_I<7> ADDR_N_I<6> CS04<1> CS02<7> VDD VSS / ++ RM_IHPSG13_512x16_c2_2P_DEC03 +XDEC11<8> ADDR_N_I<7> ADDR_N_I<6> CS04<0> CS02<3> VDD VSS / ++ RM_IHPSG13_512x16_c2_2P_DEC03 +XDEC11<7> ADDR_N_I<5> ADDR_N_I<4> CS02<7> CS00<31> VDD VSS / ++ RM_IHPSG13_512x16_c2_2P_DEC03 +XDEC11<6> ADDR_N_I<5> ADDR_N_I<4> CS02<6> CS00<27> VDD VSS / ++ RM_IHPSG13_512x16_c2_2P_DEC03 +XDEC11<5> ADDR_N_I<5> ADDR_N_I<4> CS02<5> CS00<23> VDD VSS / ++ RM_IHPSG13_512x16_c2_2P_DEC03 +XDEC11<4> ADDR_N_I<5> ADDR_N_I<4> CS02<4> CS00<19> VDD VSS / ++ RM_IHPSG13_512x16_c2_2P_DEC03 +XDEC11<3> ADDR_N_I<5> ADDR_N_I<4> CS02<3> CS00<15> VDD VSS / ++ RM_IHPSG13_512x16_c2_2P_DEC03 +XDEC11<2> ADDR_N_I<5> ADDR_N_I<4> CS02<2> CS00<11> VDD VSS / ++ RM_IHPSG13_512x16_c2_2P_DEC03 +XDEC11<1> ADDR_N_I<5> ADDR_N_I<4> CS02<1> CS00<7> VDD VSS / ++ RM_IHPSG13_512x16_c2_2P_DEC03 +XDEC11<0> ADDR_N_I<5> ADDR_N_I<4> CS02<0> CS00<3> VDD VSS / ++ RM_IHPSG13_512x16_c2_2P_DEC03 +XI0 ADDR_N_I<9> VDD VSS / RSC_IHPSG13_TIEL +.ENDS +.SUBCKT RM_IHPSG13_512x16_c2_2P_ROWREG9 ACLK_N_I ADDR_I<8> ADDR_I<7> ADDR_I<6> ADDR_I<5> ++ ADDR_I<4> ADDR_I<3> ADDR_I<2> ADDR_I<1> ADDR_I<0> ADDR_N_O<8> ADDR_N_O<7> ++ ADDR_N_O<6> ADDR_N_O<5> ADDR_N_O<4> ADDR_N_O<3> ADDR_N_O<2> ADDR_N_O<1> ++ ADDR_N_O<0> BIST_ADDR_I<8> BIST_ADDR_I<7> BIST_ADDR_I<6> BIST_ADDR_I<5> ++ BIST_ADDR_I<4> BIST_ADDR_I<3> BIST_ADDR_I<2> BIST_ADDR_I<1> BIST_ADDR_I<0> ++ BIST_EN_I VDD VSS +XDFF<8> BIST_EN_I BIST_ADDR_I<8> ACLK_N_I ADDR_I<8> q_int<8> net04<0> VDD ++ VSS / RSC_IHPSG13_DFNQMX2IX1 +XDFF<7> BIST_EN_I BIST_ADDR_I<7> ACLK_N_I ADDR_I<7> q_int<7> net04<1> VDD ++ VSS / RSC_IHPSG13_DFNQMX2IX1 +XDFF<6> BIST_EN_I BIST_ADDR_I<6> ACLK_N_I ADDR_I<6> q_int<6> net04<2> VDD ++ VSS / RSC_IHPSG13_DFNQMX2IX1 +XDFF<5> BIST_EN_I BIST_ADDR_I<5> ACLK_N_I ADDR_I<5> q_int<5> net04<3> VDD ++ VSS / RSC_IHPSG13_DFNQMX2IX1 +XDFF<4> BIST_EN_I BIST_ADDR_I<4> ACLK_N_I ADDR_I<4> q_int<4> net04<4> VDD ++ VSS / RSC_IHPSG13_DFNQMX2IX1 +XDFF<3> BIST_EN_I BIST_ADDR_I<3> ACLK_N_I ADDR_I<3> q_int<3> net04<5> VDD ++ VSS / RSC_IHPSG13_DFNQMX2IX1 +XDFF<2> BIST_EN_I BIST_ADDR_I<2> ACLK_N_I ADDR_I<2> q_int<2> net04<6> VDD ++ VSS / RSC_IHPSG13_DFNQMX2IX1 +XDFF<1> BIST_EN_I BIST_ADDR_I<1> ACLK_N_I ADDR_I<1> q_int<1> net04<7> VDD ++ VSS / RSC_IHPSG13_DFNQMX2IX1 +XDFF<0> BIST_EN_I BIST_ADDR_I<0> ACLK_N_I ADDR_I<0> q_int<0> net04<8> VDD ++ VSS / RSC_IHPSG13_DFNQMX2IX1 +XDRV<8> qn_int<8> ADDR_N_O<8> VDD VSS / RSC_IHPSG13_CINVX8 +XDRV<7> qn_int<7> ADDR_N_O<7> VDD VSS / RSC_IHPSG13_CINVX8 +XDRV<6> qn_int<6> ADDR_N_O<6> VDD VSS / RSC_IHPSG13_CINVX8 +XDRV<5> qn_int<5> ADDR_N_O<5> VDD VSS / RSC_IHPSG13_CINVX8 +XDRV<4> qn_int<4> ADDR_N_O<4> VDD VSS / RSC_IHPSG13_CINVX8 +XDRV<3> qn_int<3> ADDR_N_O<3> VDD VSS / RSC_IHPSG13_CINVX8 +XDRV<2> qn_int<2> ADDR_N_O<2> VDD VSS / RSC_IHPSG13_CINVX8 +XDRV<1> qn_int<1> ADDR_N_O<1> VDD VSS / RSC_IHPSG13_CINVX8 +XDRV<0> qn_int<0> ADDR_N_O<0> VDD VSS / RSC_IHPSG13_CINVX8 +XINV<8> q_int<8> qn_int<8> VDD VSS / RSC_IHPSG13_CINVX2 +XINV<7> q_int<7> qn_int<7> VDD VSS / RSC_IHPSG13_CINVX2 +XINV<6> q_int<6> qn_int<6> VDD VSS / RSC_IHPSG13_CINVX2 +XINV<5> q_int<5> qn_int<5> VDD VSS / RSC_IHPSG13_CINVX2 +XINV<4> q_int<4> qn_int<4> VDD VSS / RSC_IHPSG13_CINVX2 +XINV<3> q_int<3> qn_int<3> VDD VSS / RSC_IHPSG13_CINVX2 +XINV<2> q_int<2> qn_int<2> VDD VSS / RSC_IHPSG13_CINVX2 +XINV<1> q_int<1> qn_int<1> VDD VSS / RSC_IHPSG13_CINVX2 +XINV<0> q_int<0> qn_int<0> VDD VSS / RSC_IHPSG13_CINVX2 +.ENDS + +.SUBCKT RM_IHPSG13_512x16_c2_2P_DLY_MUX A SEL Z VDD VSS +XI11 net4 Z VDD VSS / RSC_IHPSG13_CINVX2 +XI8 A D<3> SEL net4 VDD VSS / RSC_IHPSG13_MX2IX1 +XI20<3> D<2> D<3> VDD VSS / RSC_IHPSG13_CDLYX1 +XI20<2> D<1> D<2> VDD VSS / RSC_IHPSG13_CDLYX1 +XI20<1> A D<1> VDD VSS / RSC_IHPSG13_CDLYX1 +.ENDS +.SUBCKT RM_IHPSG13_512x16_c2_2P_CTRL ACLK_N BIST_CK_I BIST_CS_I BIST_EN BIST_RE_I ++ BIST_WE_I B_TIEL_O CK_I CS_I DCLK ECLK PULSE_H PULSE_L PULSE_O RCLK RE_I ++ ROW_CS WCLK WE_I VDD VSS +XI17 ck_regs we col_we VDD VSS / RSC_IHPSG13_DFNQX2 +XI16 ck_regs re col_re VDD VSS / RSC_IHPSG13_DFNQX2 +XI18 ck_regs cs net7 VDD VSS / RSC_IHPSG13_DFNQX2 +XI71 ACLK_N net012 PULSE_O VDD VSS / RSC_IHPSG13_DFNQX2 +XI77 col_we net017 net016 VDD VSS / RSC_IHPSG13_CNAND2X2 +XI76 col_re net017 net018 VDD VSS / RSC_IHPSG13_CNAND2X2 +XI15 ck_dly WEorREandCS aclk VDD VSS / RSC_IHPSG13_CGATEPX4 +XI14 ck WEandCS DCLK VDD VSS / RSC_IHPSG13_CGATEPX4 +XI60 net7 ROW_CS VDD VSS / RSC_IHPSG13_CBUFX8 +XI73 PULSE_O net012 VDD VSS / RSC_IHPSG13_CINVX2 +XI8 net017 net8 VDD VSS / RSC_IHPSG13_CINVX2 +XCAPS4<7> VDD VSS / RSC_IHPSG13_FILLCAP4 +XCAPS4<6> VDD VSS / RSC_IHPSG13_FILLCAP4 +XCAPS4<5> VDD VSS / RSC_IHPSG13_FILLCAP4 +XCAPS4<4> VDD VSS / RSC_IHPSG13_FILLCAP4 +XCAPS4<3> VDD VSS / RSC_IHPSG13_FILLCAP4 +XCAPS4<2> VDD VSS / RSC_IHPSG13_FILLCAP4 +XCAPS4<1> VDD VSS / RSC_IHPSG13_FILLCAP4 +XBM_TIEL B_TIEL_O VDD VSS / RSC_IHPSG13_TIEL +XI64 ck ck_dly VDD VSS / RSC_IHPSG13_CDLYX2 +XI86 CS_I BIST_CS_I BIST_EN cs VDD VSS / RSC_IHPSG13_MX2X2 +XI87 CK_I BIST_CK_I BIST_EN ck VDD VSS / RSC_IHPSG13_MX2X2 +XI85 WE_I BIST_WE_I BIST_EN we VDD VSS / RSC_IHPSG13_MX2X2 +XI84 RE_I BIST_RE_I BIST_EN re VDD VSS / RSC_IHPSG13_MX2X2 +XI48 ck_dly ck_regs VDD VSS / RSC_IHPSG13_CINVX4 +XI81 net016 WCLK VDD VSS / RSC_IHPSG13_CINVX4 +XI80 net018 RCLK VDD VSS / RSC_IHPSG13_CINVX4 +XI78 net8 net020 VDD VSS / RSC_IHPSG13_CINVX4 +XCAPS8<7> VDD VSS / RSC_IHPSG13_FILLCAP8 +XCAPS8<6> VDD VSS / RSC_IHPSG13_FILLCAP8 +XCAPS8<5> VDD VSS / RSC_IHPSG13_FILLCAP8 +XCAPS8<4> VDD VSS / RSC_IHPSG13_FILLCAP8 +XCAPS8<3> VDD VSS / RSC_IHPSG13_FILLCAP8 +XCAPS8<2> VDD VSS / RSC_IHPSG13_FILLCAP8 +XCAPS8<1> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI6 PULSE_L PULSE_H net017 VDD VSS / RSC_IHPSG13_XOR2X2 +XI22 we cs WEandCS VDD VSS / RSC_IHPSG13_AND2X2 +XI79 net020 ECLK VDD VSS / RSC_IHPSG13_CINVX8 +XI63 aclk ACLK_N VDD VSS / RSC_IHPSG13_CINVX8 +XI21 re we cs WEorREandCS VDD VSS / RSC_IHPSG13_OA12X1 +.ENDS +.SUBCKT RM_IHPSG13_512x16_c2_2P_COLDEC5 ACLK_N ADDR<4> ADDR<3> ADDR<2> ADDR<1> ADDR<0> ++ ADDR_COL<1> ADDR_COL<0> ADDR_DEC<7> ADDR_DEC<6> ADDR_DEC<5> ADDR_DEC<4> ++ ADDR_DEC<3> ADDR_DEC<2> ADDR_DEC<1> ADDR_DEC<0> BIST_ADDR<4> BIST_ADDR<3> ++ BIST_ADDR<2> BIST_ADDR<1> BIST_ADDR<0> BIST_EN_I VDD VSS +XI17<4> VDD VSS / RSC_IHPSG13_FILLCAP4 +XI17<3> VDD VSS / RSC_IHPSG13_FILLCAP4 +XI17<2> VDD VSS / RSC_IHPSG13_FILLCAP4 +XI17<1> VDD VSS / RSC_IHPSG13_FILLCAP4 +XI1<7> PADR<0> PADR<1> PADR<2> addr_n<7> VDD VSS / RSC_IHPSG13_NAND3X2 +XI1<6> NADR<0> PADR<1> PADR<2> addr_n<6> VDD VSS / RSC_IHPSG13_NAND3X2 +XI1<5> PADR<0> NADR<1> PADR<2> addr_n<5> VDD VSS / RSC_IHPSG13_NAND3X2 +XI1<4> NADR<0> NADR<1> PADR<2> addr_n<4> VDD VSS / RSC_IHPSG13_NAND3X2 +XI1<3> PADR<0> PADR<1> NADR<2> addr_n<3> VDD VSS / RSC_IHPSG13_NAND3X2 +XI1<2> NADR<0> PADR<1> NADR<2> addr_n<2> VDD VSS / RSC_IHPSG13_NAND3X2 +XI1<1> PADR<0> NADR<1> NADR<2> addr_n<1> VDD VSS / RSC_IHPSG13_NAND3X2 +XI1<0> NADR<0> NADR<1> NADR<2> addr_n<0> VDD VSS / RSC_IHPSG13_NAND3X2 +XDFF<4> BIST_EN_I BIST_ADDR<4> ACLK_N ADDR<4> addr_int<1> net13<0> VDD ++ VSS / RSC_IHPSG13_DFNQMX2IX1 +XDFF<3> BIST_EN_I BIST_ADDR<3> ACLK_N ADDR<3> addr_int<0> net13<1> VDD ++ VSS / RSC_IHPSG13_DFNQMX2IX1 +XDFF<2> BIST_EN_I BIST_ADDR<2> ACLK_N ADDR<2> padr_int<2> net13<2> VDD ++ VSS / RSC_IHPSG13_DFNQMX2IX1 +XDFF<1> BIST_EN_I BIST_ADDR<1> ACLK_N ADDR<1> padr_int<1> net13<3> VDD ++ VSS / RSC_IHPSG13_DFNQMX2IX1 +XDFF<0> BIST_EN_I BIST_ADDR<0> ACLK_N ADDR<0> padr_int<0> net13<4> VDD ++ VSS / RSC_IHPSG13_DFNQMX2IX1 +XI3<2> padr_int<2> NADR<2> VDD VSS / RSC_IHPSG13_INVX2 +XI3<1> padr_int<1> NADR<1> VDD VSS / RSC_IHPSG13_INVX2 +XI3<0> padr_int<0> NADR<0> VDD VSS / RSC_IHPSG13_INVX2 +XI2<7> addr_n<7> ADDR_DEC<7> VDD VSS / RSC_IHPSG13_INVX2 +XI2<6> addr_n<6> ADDR_DEC<6> VDD VSS / RSC_IHPSG13_INVX2 +XI2<5> addr_n<5> ADDR_DEC<5> VDD VSS / RSC_IHPSG13_INVX2 +XI2<4> addr_n<4> ADDR_DEC<4> VDD VSS / RSC_IHPSG13_INVX2 +XI2<3> addr_n<3> ADDR_DEC<3> VDD VSS / RSC_IHPSG13_INVX2 +XI2<2> addr_n<2> ADDR_DEC<2> VDD VSS / RSC_IHPSG13_INVX2 +XI2<1> addr_n<1> ADDR_DEC<1> VDD VSS / RSC_IHPSG13_INVX2 +XI2<0> addr_n<0> ADDR_DEC<0> VDD VSS / RSC_IHPSG13_INVX2 +XI15<2> NADR<2> PADR<2> VDD VSS / RSC_IHPSG13_INVX2 +XI15<1> NADR<1> PADR<1> VDD VSS / RSC_IHPSG13_INVX2 +XI15<0> NADR<0> PADR<0> VDD VSS / RSC_IHPSG13_INVX2 +XI13<1> addr_int<1> ADDR_COL<1> VDD VSS / RSC_IHPSG13_CBUFX2 +XI13<0> addr_int<0> ADDR_COL<0> VDD VSS / RSC_IHPSG13_CBUFX2 +XI14<5> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI14<4> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI14<3> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI14<2> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI14<1> VDD VSS / RSC_IHPSG13_FILLCAP8 +.ENDS +.SUBCKT RM_IHPSG13_512x16_c2_2P_BLDRV A_BLC<3> A_BLC<2> A_BLC<1> A_BLC<0> A_BLC_SEL ++ A_BLT<3> A_BLT<2> A_BLT<1> A_BLT<0> A_BLT_SEL A_PRE_N A_SEL_P<3> A_SEL_P<2> ++ A_SEL_P<1> A_SEL_P<0> A_WR_ONE A_WR_ZERO B_BLC<3> B_BLC<2> B_BLC<1> B_BLC<0> ++ B_BLC_SEL B_BLT<3> B_BLT<2> B_BLT<1> B_BLT<0> B_BLT_SEL B_PRE_N B_SEL_P<3> ++ B_SEL_P<2> B_SEL_P<1> B_SEL_P<0> B_WR_ONE B_WR_ZERO VDD VSS +MA_CWN<3> A_BLC<3> A_BLC_NMOS_DRIVE<3> VSS VSS sg13_lv_nmos m=1 ++ w=4.82u l=130.00n ng=2 nrd=0 nrs=0 +MA_CWN<2> A_BLC<2> A_BLC_NMOS_DRIVE<2> VSS VSS sg13_lv_nmos m=1 ++ w=4.82u l=130.00n ng=2 nrd=0 nrs=0 +MA_CWN<1> A_BLC<1> A_BLC_NMOS_DRIVE<1> VSS VSS sg13_lv_nmos m=1 ++ w=4.82u l=130.00n ng=2 nrd=0 nrs=0 +MA_CWN<0> A_BLC<0> A_BLC_NMOS_DRIVE<0> VSS VSS sg13_lv_nmos m=1 ++ w=4.82u l=130.00n ng=2 nrd=0 nrs=0 +MA_TWN<3> A_BLT<3> A_BLT_NMOS_DRIVE<3> VSS VSS sg13_lv_nmos m=1 ++ w=4.82u l=130.00n ng=2 nrd=0 nrs=0 +MA_TWN<2> A_BLT<2> A_BLT_NMOS_DRIVE<2> VSS VSS sg13_lv_nmos m=1 ++ w=4.82u l=130.00n ng=2 nrd=0 nrs=0 +MA_TWN<1> A_BLT<1> A_BLT_NMOS_DRIVE<1> VSS VSS sg13_lv_nmos m=1 ++ w=4.82u l=130.00n ng=2 nrd=0 nrs=0 +MA_TWN<0> A_BLT<0> A_BLT_NMOS_DRIVE<0> VSS VSS sg13_lv_nmos m=1 ++ w=4.82u l=130.00n ng=2 nrd=0 nrs=0 +MB_TWN<3> B_BLT<3> B_BLT_NMOS_DRIVE<3> VSS VSS sg13_lv_nmos m=1 ++ w=4.82u l=130.00n ng=2 nrd=0 nrs=0 +MB_TWN<2> B_BLT<2> B_BLT_NMOS_DRIVE<2> VSS VSS sg13_lv_nmos m=1 ++ w=4.82u l=130.00n ng=2 nrd=0 nrs=0 +MB_TWN<1> B_BLT<1> B_BLT_NMOS_DRIVE<1> VSS VSS sg13_lv_nmos m=1 ++ w=4.82u l=130.00n ng=2 nrd=0 nrs=0 +MB_TWN<0> B_BLT<0> B_BLT_NMOS_DRIVE<0> VSS VSS sg13_lv_nmos m=1 ++ w=4.82u l=130.00n ng=2 nrd=0 nrs=0 +MB_CWN<3> B_BLC<3> B_BLC_NMOS_DRIVE<3> VSS VSS sg13_lv_nmos m=1 ++ w=4.82u l=130.00n ng=2 nrd=0 nrs=0 +MB_CWN<2> B_BLC<2> B_BLC_NMOS_DRIVE<2> VSS VSS sg13_lv_nmos m=1 ++ w=4.82u l=130.00n ng=2 nrd=0 nrs=0 +MB_CWN<1> B_BLC<1> B_BLC_NMOS_DRIVE<1> VSS VSS sg13_lv_nmos m=1 ++ w=4.82u l=130.00n ng=2 nrd=0 nrs=0 +MB_CWN<0> B_BLC<0> B_BLC_NMOS_DRIVE<0> VSS VSS sg13_lv_nmos m=1 ++ w=4.82u l=130.00n ng=2 nrd=0 nrs=0 +MA_CPR<3> A_BLC<3> A_PRE_N VDD VDD sg13_lv_pmos m=1 w=3.000u l=130.00n ++ ng=2 nrd=0 nrs=0 +MA_CPR<2> A_BLC<2> A_PRE_N VDD VDD sg13_lv_pmos m=1 w=3.000u l=130.00n ++ ng=2 nrd=0 nrs=0 +MA_CPR<1> A_BLC<1> A_PRE_N VDD VDD sg13_lv_pmos m=1 w=3.000u l=130.00n ++ ng=2 nrd=0 nrs=0 +MA_CPR<0> A_BLC<0> A_PRE_N VDD VDD sg13_lv_pmos m=1 w=3.000u l=130.00n ++ ng=2 nrd=0 nrs=0 +MA_TWP<3> A_BLT<3> A_BLT_PMOS_DRIVE<3> VDD VDD sg13_lv_pmos m=1 w=1.5u ++ l=130.00n ng=1 nrd=0 nrs=0 +MA_TWP<2> A_BLT<2> A_BLT_PMOS_DRIVE<2> VDD VDD sg13_lv_pmos m=1 w=1.5u ++ l=130.00n ng=1 nrd=0 nrs=0 +MA_TWP<1> A_BLT<1> A_BLT_PMOS_DRIVE<1> VDD VDD sg13_lv_pmos m=1 w=1.5u ++ l=130.00n ng=1 nrd=0 nrs=0 +MA_TWP<0> A_BLT<0> A_BLT_PMOS_DRIVE<0> VDD VDD sg13_lv_pmos m=1 w=1.5u ++ l=130.00n ng=1 nrd=0 nrs=0 +MA_CWP<3> A_BLC<3> A_BLC_PMOS_DRIVE<3> VDD VDD sg13_lv_pmos m=1 w=1.5u ++ l=130.00n ng=1 nrd=0 nrs=0 +MA_CWP<2> A_BLC<2> A_BLC_PMOS_DRIVE<2> VDD VDD sg13_lv_pmos m=1 w=1.5u ++ l=130.00n ng=1 nrd=0 nrs=0 +MA_CWP<1> A_BLC<1> A_BLC_PMOS_DRIVE<1> VDD VDD sg13_lv_pmos m=1 w=1.5u ++ l=130.00n ng=1 nrd=0 nrs=0 +MA_CWP<0> A_BLC<0> A_BLC_PMOS_DRIVE<0> VDD VDD sg13_lv_pmos m=1 w=1.5u ++ l=130.00n ng=1 nrd=0 nrs=0 +MA_TPR<3> A_BLT<3> A_PRE_N VDD VDD sg13_lv_pmos m=1 w=3.000u l=130.00n ++ ng=2 nrd=0 nrs=0 +MA_TPR<2> A_BLT<2> A_PRE_N VDD VDD sg13_lv_pmos m=1 w=3.000u l=130.00n ++ ng=2 nrd=0 nrs=0 +MA_TPR<1> A_BLT<1> A_PRE_N VDD VDD sg13_lv_pmos m=1 w=3.000u l=130.00n ++ ng=2 nrd=0 nrs=0 +MA_TPR<0> A_BLT<0> A_PRE_N VDD VDD sg13_lv_pmos m=1 w=3.000u l=130.00n ++ ng=2 nrd=0 nrs=0 +MA_TSP<3> A_BLT_SEL A_SEL_N<3> A_BLT<3> VDD sg13_lv_pmos m=1 w=1.5u ++ l=130.00n ng=1 nrd=0 nrs=0 +MA_TSP<2> A_BLT_SEL A_SEL_N<2> A_BLT<2> VDD sg13_lv_pmos m=1 w=1.5u ++ l=130.00n ng=1 nrd=0 nrs=0 +MA_TSP<1> A_BLT_SEL A_SEL_N<1> A_BLT<1> VDD sg13_lv_pmos m=1 w=1.5u ++ l=130.00n ng=1 nrd=0 nrs=0 +MA_TSP<0> A_BLT_SEL A_SEL_N<0> A_BLT<0> VDD sg13_lv_pmos m=1 w=1.5u ++ l=130.00n ng=1 nrd=0 nrs=0 +MA_CSP<3> A_BLC_SEL A_SEL_N<3> A_BLC<3> VDD sg13_lv_pmos m=1 w=1.5u ++ l=130.00n ng=1 nrd=0 nrs=0 +MA_CSP<2> A_BLC_SEL A_SEL_N<2> A_BLC<2> VDD sg13_lv_pmos m=1 w=1.5u ++ l=130.00n ng=1 nrd=0 nrs=0 +MA_CSP<1> A_BLC_SEL A_SEL_N<1> A_BLC<1> VDD sg13_lv_pmos m=1 w=1.5u ++ l=130.00n ng=1 nrd=0 nrs=0 +MA_CSP<0> A_BLC_SEL A_SEL_N<0> A_BLC<0> VDD sg13_lv_pmos m=1 w=1.5u ++ l=130.00n ng=1 nrd=0 nrs=0 +MB_CWP<3> B_BLC<3> B_BLC_PMOS_DRIVE<3> VDD VDD sg13_lv_pmos m=1 w=1.5u ++ l=130.00n ng=1 nrd=0 nrs=0 +MB_CWP<2> B_BLC<2> B_BLC_PMOS_DRIVE<2> VDD VDD sg13_lv_pmos m=1 w=1.5u ++ l=130.00n ng=1 nrd=0 nrs=0 +MB_CWP<1> B_BLC<1> B_BLC_PMOS_DRIVE<1> VDD VDD sg13_lv_pmos m=1 w=1.5u ++ l=130.00n ng=1 nrd=0 nrs=0 +MB_CWP<0> B_BLC<0> B_BLC_PMOS_DRIVE<0> VDD VDD sg13_lv_pmos m=1 w=1.5u ++ l=130.00n ng=1 nrd=0 nrs=0 +MB_TWP<3> B_BLT<3> B_BLT_PMOS_DRIVE<3> VDD VDD sg13_lv_pmos m=1 w=1.5u ++ l=130.00n ng=1 nrd=0 nrs=0 +MB_TWP<2> B_BLT<2> B_BLT_PMOS_DRIVE<2> VDD VDD sg13_lv_pmos m=1 w=1.5u ++ l=130.00n ng=1 nrd=0 nrs=0 +MB_TWP<1> B_BLT<1> B_BLT_PMOS_DRIVE<1> VDD VDD sg13_lv_pmos m=1 w=1.5u ++ l=130.00n ng=1 nrd=0 nrs=0 +MB_TWP<0> B_BLT<0> B_BLT_PMOS_DRIVE<0> VDD VDD sg13_lv_pmos m=1 w=1.5u ++ l=130.00n ng=1 nrd=0 nrs=0 +MB_TSP<3> B_BLT_SEL B_SEL_N<3> B_BLT<3> VDD sg13_lv_pmos m=1 w=1.5u ++ l=130.00n ng=1 nrd=0 nrs=0 +MB_TSP<2> B_BLT_SEL B_SEL_N<2> B_BLT<2> VDD sg13_lv_pmos m=1 w=1.5u ++ l=130.00n ng=1 nrd=0 nrs=0 +MB_TSP<1> B_BLT_SEL B_SEL_N<1> B_BLT<1> VDD sg13_lv_pmos m=1 w=1.5u ++ l=130.00n ng=1 nrd=0 nrs=0 +MB_TSP<0> B_BLT_SEL B_SEL_N<0> B_BLT<0> VDD sg13_lv_pmos m=1 w=1.5u ++ l=130.00n ng=1 nrd=0 nrs=0 +MB_TPR<3> B_BLT<3> B_PRE_N VDD VDD sg13_lv_pmos m=1 w=3.000u l=130.00n ++ ng=2 nrd=0 nrs=0 +MB_TPR<2> B_BLT<2> B_PRE_N VDD VDD sg13_lv_pmos m=1 w=3.000u l=130.00n ++ ng=2 nrd=0 nrs=0 +MB_TPR<1> B_BLT<1> B_PRE_N VDD VDD sg13_lv_pmos m=1 w=3.000u l=130.00n ++ ng=2 nrd=0 nrs=0 +MB_TPR<0> B_BLT<0> B_PRE_N VDD VDD sg13_lv_pmos m=1 w=3.000u l=130.00n ++ ng=2 nrd=0 nrs=0 +MB_CSP<3> B_BLC_SEL B_SEL_N<3> B_BLC<3> VDD sg13_lv_pmos m=1 w=1.5u ++ l=130.00n ng=1 nrd=0 nrs=0 +MB_CSP<2> B_BLC_SEL B_SEL_N<2> B_BLC<2> VDD sg13_lv_pmos m=1 w=1.5u ++ l=130.00n ng=1 nrd=0 nrs=0 +MB_CSP<1> B_BLC_SEL B_SEL_N<1> B_BLC<1> VDD sg13_lv_pmos m=1 w=1.5u ++ l=130.00n ng=1 nrd=0 nrs=0 +MB_CSP<0> B_BLC_SEL B_SEL_N<0> B_BLC<0> VDD sg13_lv_pmos m=1 w=1.5u ++ l=130.00n ng=1 nrd=0 nrs=0 +MB_CPR<3> B_BLC<3> B_PRE_N VDD VDD sg13_lv_pmos m=1 w=3.000u l=130.00n ++ ng=2 nrd=0 nrs=0 +MB_CPR<2> B_BLC<2> B_PRE_N VDD VDD sg13_lv_pmos m=1 w=3.000u l=130.00n ++ ng=2 nrd=0 nrs=0 +MB_CPR<1> B_BLC<1> B_PRE_N VDD VDD sg13_lv_pmos m=1 w=3.000u l=130.00n ++ ng=2 nrd=0 nrs=0 +MB_CPR<0> B_BLC<0> B_PRE_N VDD VDD sg13_lv_pmos m=1 w=3.000u l=130.00n ++ ng=2 nrd=0 nrs=0 +XA_SEL<3> A_SEL_P<3> A_SEL_N<3> VDD VSS / RSC_IHPSG13_INVX2 +XA_SEL<2> A_SEL_P<2> A_SEL_N<2> VDD VSS / RSC_IHPSG13_INVX2 +XA_SEL<1> A_SEL_P<1> A_SEL_N<1> VDD VSS / RSC_IHPSG13_INVX2 +XA_SEL<0> A_SEL_P<0> A_SEL_N<0> VDD VSS / RSC_IHPSG13_INVX2 +XA_CINV<3> A_BLT_PMOS_DRIVE<3> A_BLC_NMOS_DRIVE<3> VDD VSS / ++ RSC_IHPSG13_INVX2 +XA_CINV<2> A_BLT_PMOS_DRIVE<2> A_BLC_NMOS_DRIVE<2> VDD VSS / ++ RSC_IHPSG13_INVX2 +XA_CINV<1> A_BLT_PMOS_DRIVE<1> A_BLC_NMOS_DRIVE<1> VDD VSS / ++ RSC_IHPSG13_INVX2 +XA_CINV<0> A_BLT_PMOS_DRIVE<0> A_BLC_NMOS_DRIVE<0> VDD VSS / ++ RSC_IHPSG13_INVX2 +XA_TINV<3> A_BLC_PMOS_DRIVE<3> A_BLT_NMOS_DRIVE<3> VDD VSS / ++ RSC_IHPSG13_INVX2 +XA_TINV<2> A_BLC_PMOS_DRIVE<2> A_BLT_NMOS_DRIVE<2> VDD VSS / ++ RSC_IHPSG13_INVX2 +XA_TINV<1> A_BLC_PMOS_DRIVE<1> A_BLT_NMOS_DRIVE<1> VDD VSS / ++ RSC_IHPSG13_INVX2 +XA_TINV<0> A_BLC_PMOS_DRIVE<0> A_BLT_NMOS_DRIVE<0> VDD VSS / ++ RSC_IHPSG13_INVX2 +XB_SEL<3> B_SEL_P<3> B_SEL_N<3> VDD VSS / RSC_IHPSG13_INVX2 +XB_SEL<2> B_SEL_P<2> B_SEL_N<2> VDD VSS / RSC_IHPSG13_INVX2 +XB_SEL<1> B_SEL_P<1> B_SEL_N<1> VDD VSS / RSC_IHPSG13_INVX2 +XB_SEL<0> B_SEL_P<0> B_SEL_N<0> VDD VSS / RSC_IHPSG13_INVX2 +XB_TINV<3> B_BLC_PMOS_DRIVE<3> B_BLT_NMOS_DRIVE<3> VDD VSS / ++ RSC_IHPSG13_INVX2 +XB_TINV<2> B_BLC_PMOS_DRIVE<2> B_BLT_NMOS_DRIVE<2> VDD VSS / ++ RSC_IHPSG13_INVX2 +XB_TINV<1> B_BLC_PMOS_DRIVE<1> B_BLT_NMOS_DRIVE<1> VDD VSS / ++ RSC_IHPSG13_INVX2 +XB_TINV<0> B_BLC_PMOS_DRIVE<0> B_BLT_NMOS_DRIVE<0> VDD VSS / ++ RSC_IHPSG13_INVX2 +XB_CINV<3> B_BLT_PMOS_DRIVE<3> B_BLC_NMOS_DRIVE<3> VDD VSS / ++ RSC_IHPSG13_INVX2 +XB_CINV<2> B_BLT_PMOS_DRIVE<2> B_BLC_NMOS_DRIVE<2> VDD VSS / ++ RSC_IHPSG13_INVX2 +XB_CINV<1> B_BLT_PMOS_DRIVE<1> B_BLC_NMOS_DRIVE<1> VDD VSS / ++ RSC_IHPSG13_INVX2 +XB_CINV<0> B_BLT_PMOS_DRIVE<0> B_BLC_NMOS_DRIVE<0> VDD VSS / ++ RSC_IHPSG13_INVX2 +XA_TDEC<3> A_SEL_P<3> A_WR_ONE A_BLT_PMOS_DRIVE<3> VDD VSS / ++ RSC_IHPSG13_NAND2X2 +XA_TDEC<2> A_SEL_P<2> A_WR_ONE A_BLT_PMOS_DRIVE<2> VDD VSS / ++ RSC_IHPSG13_NAND2X2 +XA_TDEC<1> A_SEL_P<1> A_WR_ONE A_BLT_PMOS_DRIVE<1> VDD VSS / ++ RSC_IHPSG13_NAND2X2 +XA_TDEC<0> A_SEL_P<0> A_WR_ONE A_BLT_PMOS_DRIVE<0> VDD VSS / ++ RSC_IHPSG13_NAND2X2 +XA_CDEC<3> A_SEL_P<3> A_WR_ZERO A_BLC_PMOS_DRIVE<3> VDD VSS / ++ RSC_IHPSG13_NAND2X2 +XA_CDEC<2> A_SEL_P<2> A_WR_ZERO A_BLC_PMOS_DRIVE<2> VDD VSS / ++ RSC_IHPSG13_NAND2X2 +XA_CDEC<1> A_SEL_P<1> A_WR_ZERO A_BLC_PMOS_DRIVE<1> VDD VSS / ++ RSC_IHPSG13_NAND2X2 +XA_CDEC<0> A_SEL_P<0> A_WR_ZERO A_BLC_PMOS_DRIVE<0> VDD VSS / ++ RSC_IHPSG13_NAND2X2 +XB_CDEC<3> B_SEL_P<3> B_WR_ZERO B_BLC_PMOS_DRIVE<3> VDD VSS / ++ RSC_IHPSG13_NAND2X2 +XB_CDEC<2> B_SEL_P<2> B_WR_ZERO B_BLC_PMOS_DRIVE<2> VDD VSS / ++ RSC_IHPSG13_NAND2X2 +XB_CDEC<1> B_SEL_P<1> B_WR_ZERO B_BLC_PMOS_DRIVE<1> VDD VSS / ++ RSC_IHPSG13_NAND2X2 +XB_CDEC<0> B_SEL_P<0> B_WR_ZERO B_BLC_PMOS_DRIVE<0> VDD VSS / ++ RSC_IHPSG13_NAND2X2 +XB_TDEC<3> B_SEL_P<3> B_WR_ONE B_BLT_PMOS_DRIVE<3> VDD VSS / ++ RSC_IHPSG13_NAND2X2 +XB_TDEC<2> B_SEL_P<2> B_WR_ONE B_BLT_PMOS_DRIVE<2> VDD VSS / ++ RSC_IHPSG13_NAND2X2 +XB_TDEC<1> B_SEL_P<1> B_WR_ONE B_BLT_PMOS_DRIVE<1> VDD VSS / ++ RSC_IHPSG13_NAND2X2 +XB_TDEC<0> B_SEL_P<0> B_WR_ONE B_BLT_PMOS_DRIVE<0> VDD VSS / ++ RSC_IHPSG13_NAND2X2 +.ENDS +.SUBCKT RSC_IHPSG13_AND2X6 A B Z VDD VSS +MN3 Z net6 VSS VSS sg13_lv_nmos m=1 w=2.94u l=130.00n ng=3 nrd=0 nrs=0 +MN4 net9 B VSS VSS sg13_lv_nmos m=1 w=500.0n l=130.00n ng=1 nrd=0 nrs=0 +MN6 net6 A net9 VSS sg13_lv_nmos m=1 w=500.0n l=130.00n ng=1 nrd=0 nrs=0 +MP2 Z net6 VDD VDD sg13_lv_pmos m=1 w=4.86u l=130.00n ng=3 nrd=0 nrs=0 +MP0 net6 B VDD VDD sg13_lv_pmos m=1 w=860.00n l=130.00n ng=1 nrd=0 ++ nrs=0 +MP1 net6 A VDD VDD sg13_lv_pmos m=1 w=860.00n l=130.00n ng=1 nrd=0 ++ nrs=0 +.ENDS +.SUBCKT RM_IHPSG13_512x16_c2_2P_COLCTRL5 A_ADDR_COL<1> A_ADDR_COL<0> A_ADDR_DEC<7> ++ A_ADDR_DEC<6> A_ADDR_DEC<5> A_ADDR_DEC<4> A_ADDR_DEC<3> A_ADDR_DEC<2> ++ A_ADDR_DEC<1> A_ADDR_DEC<0> A_BIST_BM_I A_BIST_DW_I A_BIST_EN_I A_BLC<31> ++ A_BLC<30> A_BLC<29> A_BLC<28> A_BLC<27> A_BLC<26> A_BLC<25> A_BLC<24> ++ A_BLC<23> A_BLC<22> A_BLC<21> A_BLC<20> A_BLC<19> A_BLC<18> A_BLC<17> ++ A_BLC<16> A_BLC<15> A_BLC<14> A_BLC<13> A_BLC<12> A_BLC<11> A_BLC<10> ++ A_BLC<9> A_BLC<8> A_BLC<7> A_BLC<6> A_BLC<5> A_BLC<4> A_BLC<3> A_BLC<2> ++ A_BLC<1> A_BLC<0> A_BLT<31> A_BLT<30> A_BLT<29> A_BLT<28> A_BLT<27> ++ A_BLT<26> A_BLT<25> A_BLT<24> A_BLT<23> A_BLT<22> A_BLT<21> A_BLT<20> ++ A_BLT<19> A_BLT<18> A_BLT<17> A_BLT<16> A_BLT<15> A_BLT<14> A_BLT<13> ++ A_BLT<12> A_BLT<11> A_BLT<10> A_BLT<9> A_BLT<8> A_BLT<7> A_BLT<6> A_BLT<5> ++ A_BLT<4> A_BLT<3> A_BLT<2> A_BLT<1> A_BLT<0> A_BM_I A_DCLK_B_L A_DCLK_B_R ++ A_DCLK_L A_DCLK_R A_DR_O A_DW_I A_RCLK_B_L A_RCLK_B_R A_RCLK_L A_RCLK_R ++ A_TIEH_O A_WCLK_B_L A_WCLK_B_R A_WCLK_L A_WCLK_R B_ADDR_COL<1> B_ADDR_COL<0> ++ B_ADDR_DEC<7> B_ADDR_DEC<6> B_ADDR_DEC<5> B_ADDR_DEC<4> B_ADDR_DEC<3> ++ B_ADDR_DEC<2> B_ADDR_DEC<1> B_ADDR_DEC<0> B_BIST_BM_I B_BIST_DW_I ++ B_BIST_EN_I B_BLC<31> B_BLC<30> B_BLC<29> B_BLC<28> B_BLC<27> B_BLC<26> ++ B_BLC<25> B_BLC<24> B_BLC<23> B_BLC<22> B_BLC<21> B_BLC<20> B_BLC<19> ++ B_BLC<18> B_BLC<17> B_BLC<16> B_BLC<15> B_BLC<14> B_BLC<13> B_BLC<12> ++ B_BLC<11> B_BLC<10> B_BLC<9> B_BLC<8> B_BLC<7> B_BLC<6> B_BLC<5> B_BLC<4> ++ B_BLC<3> B_BLC<2> B_BLC<1> B_BLC<0> B_BLT<31> B_BLT<30> B_BLT<29> B_BLT<28> ++ B_BLT<27> B_BLT<26> B_BLT<25> B_BLT<24> B_BLT<23> B_BLT<22> B_BLT<21> ++ B_BLT<20> B_BLT<19> B_BLT<18> B_BLT<17> B_BLT<16> B_BLT<15> B_BLT<14> ++ B_BLT<13> B_BLT<12> B_BLT<11> B_BLT<10> B_BLT<9> B_BLT<8> B_BLT<7> B_BLT<6> ++ B_BLT<5> B_BLT<4> B_BLT<3> B_BLT<2> B_BLT<1> B_BLT<0> B_BM_I B_DCLK_B_L ++ B_DCLK_B_R B_DCLK_L B_DCLK_R B_DR_O B_DW_I B_RCLK_B_L B_RCLK_B_R B_RCLK_L ++ B_RCLK_R B_TIEH_O B_WCLK_B_L B_WCLK_B_R B_WCLK_L B_WCLK_R VDD VSS +XB_I80<1> B_WCLK_B_L B_RCLK_B_L B_W_nor_R<1> VDD VSS / ++ RSC_IHPSG13_AND2X2 +XB_I80<0> B_WCLK_B_L B_RCLK_B_L B_W_nor_R<0> VDD VSS / ++ RSC_IHPSG13_AND2X2 +XA_I80<1> A_WCLK_B_L A_RCLK_B_L A_W_nor_R<1> VDD VSS / ++ RSC_IHPSG13_AND2X2 +XA_I80<0> A_WCLK_B_L A_RCLK_B_L A_W_nor_R<0> VDD VSS / ++ RSC_IHPSG13_AND2X2 +XB_I44 B_BM_N B_WCLK_B_L B_DO_WRITE_P VDD VSS / RSC_IHPSG13_NOR2X2 +XA_I44 A_BM_N A_WCLK_B_L A_DO_WRITE_P VDD VSS / RSC_IHPSG13_NOR2X2 +XI_FILL4<16> VDD VSS / RSC_IHPSG13_FILLCAP4 +XI_FILL4<15> VDD VSS / RSC_IHPSG13_FILLCAP4 +XI_FILL4<14> VDD VSS / RSC_IHPSG13_FILLCAP4 +XI_FILL4<13> VDD VSS / RSC_IHPSG13_FILLCAP4 +XI_FILL4<12> VDD VSS / RSC_IHPSG13_FILLCAP4 +XI_FILL4<11> VDD VSS / RSC_IHPSG13_FILLCAP4 +XI_FILL4<10> VDD VSS / RSC_IHPSG13_FILLCAP4 +XI_FILL4<9> VDD VSS / RSC_IHPSG13_FILLCAP4 +XI_FILL4<8> VDD VSS / RSC_IHPSG13_FILLCAP4 +XI_FILL4<7> VDD VSS / RSC_IHPSG13_FILLCAP4 +XI_FILL4<6> VDD VSS / RSC_IHPSG13_FILLCAP4 +XI_FILL4<5> VDD VSS / RSC_IHPSG13_FILLCAP4 +XI_FILL4<4> VDD VSS / RSC_IHPSG13_FILLCAP4 +XI_FILL4<3> VDD VSS / RSC_IHPSG13_FILLCAP4 +XI_FILL4<2> VDD VSS / RSC_IHPSG13_FILLCAP4 +XI_FILL4<1> VDD VSS / RSC_IHPSG13_FILLCAP4 +XB_INV<6> B_N1<1> B_P1<1> VDD VSS / RSC_IHPSG13_CINVX4 +XB_INV<5> B_N0<1> B_P0<1> VDD VSS / RSC_IHPSG13_CINVX4 +XB_INV<4> B_N0<0> B_P0<0> VDD VSS / RSC_IHPSG13_CINVX4 +XB_INV<3> B_ADDR_COL<1> B_N1<1> VDD VSS / RSC_IHPSG13_CINVX4 +XB_INV<2> B_ADDR_COL<1> B_N1<0> VDD VSS / RSC_IHPSG13_CINVX4 +XB_INV<1> B_ADDR_COL<0> B_N0<1> VDD VSS / RSC_IHPSG13_CINVX4 +XB_INV<0> B_ADDR_COL<0> B_N0<0> VDD VSS / RSC_IHPSG13_CINVX4 +XA_INV<6> A_N1<1> A_P1<1> VDD VSS / RSC_IHPSG13_CINVX4 +XA_INV<5> A_N0<1> A_P0<1> VDD VSS / RSC_IHPSG13_CINVX4 +XA_INV<4> A_N0<0> A_P0<0> VDD VSS / RSC_IHPSG13_CINVX4 +XA_INV<3> A_ADDR_COL<1> A_N1<1> VDD VSS / RSC_IHPSG13_CINVX4 +XA_INV<2> A_ADDR_COL<1> A_N1<0> VDD VSS / RSC_IHPSG13_CINVX4 +XA_INV<1> A_ADDR_COL<0> A_N0<1> VDD VSS / RSC_IHPSG13_CINVX4 +XA_INV<0> A_ADDR_COL<0> A_N0<0> VDD VSS / RSC_IHPSG13_CINVX4 +XB_I81<3> B_W_nor_R<1> B_PRE_N VDD VSS / RSC_IHPSG13_CINVX4_WN +XB_I81<2> B_W_nor_R<1> B_PRE_N VDD VSS / RSC_IHPSG13_CINVX4_WN +XB_I81<1> B_W_nor_R<0> B_PRE_N VDD VSS / RSC_IHPSG13_CINVX4_WN +XB_I81<0> B_W_nor_R<0> B_PRE_N VDD VSS / RSC_IHPSG13_CINVX4_WN +XA_I81<3> A_W_nor_R<1> A_PRE_N VDD VSS / RSC_IHPSG13_CINVX4_WN +XA_I81<2> A_W_nor_R<1> A_PRE_N VDD VSS / RSC_IHPSG13_CINVX4_WN +XA_I81<1> A_W_nor_R<0> A_PRE_N VDD VSS / RSC_IHPSG13_CINVX4_WN +XA_I81<0> A_W_nor_R<0> A_PRE_N VDD VSS / RSC_IHPSG13_CINVX4_WN +XI_FILL8<78> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI_FILL8<77> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI_FILL8<76> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI_FILL8<75> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI_FILL8<74> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI_FILL8<73> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI_FILL8<72> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI_FILL8<71> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI_FILL8<70> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI_FILL8<69> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI_FILL8<68> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI_FILL8<67> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI_FILL8<66> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI_FILL8<65> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI_FILL8<64> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI_FILL8<63> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI_FILL8<62> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI_FILL8<61> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI_FILL8<60> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI_FILL8<59> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI_FILL8<58> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI_FILL8<57> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI_FILL8<56> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI_FILL8<55> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI_FILL8<54> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI_FILL8<53> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI_FILL8<52> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI_FILL8<51> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI_FILL8<50> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI_FILL8<49> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI_FILL8<48> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI_FILL8<47> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI_FILL8<46> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI_FILL8<45> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI_FILL8<44> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI_FILL8<43> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI_FILL8<42> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI_FILL8<41> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI_FILL8<40> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI_FILL8<39> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI_FILL8<38> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI_FILL8<37> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI_FILL8<36> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI_FILL8<35> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI_FILL8<34> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI_FILL8<33> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI_FILL8<32> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI_FILL8<31> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI_FILL8<30> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI_FILL8<29> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI_FILL8<28> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI_FILL8<27> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI_FILL8<26> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI_FILL8<25> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI_FILL8<24> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI_FILL8<23> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI_FILL8<22> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI_FILL8<21> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI_FILL8<20> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI_FILL8<19> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI_FILL8<18> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI_FILL8<17> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI_FILL8<16> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI_FILL8<15> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI_FILL8<14> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI_FILL8<13> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI_FILL8<12> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI_FILL8<11> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI_FILL8<10> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI_FILL8<9> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI_FILL8<8> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI_FILL8<7> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI_FILL8<6> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI_FILL8<5> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI_FILL8<4> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI_FILL8<3> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI_FILL8<2> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI_FILL8<1> VDD VSS / RSC_IHPSG13_FILLCAP8 +XAB_BLMUX<7> A_BLC<31> A_BLC<30> A_BLC<29> A_BLC<28> A_BLC_SEL A_BLT<31> ++ A_BLT<30> A_BLT<29> A_BLT<28> A_BLT_SEL A_PRE_N A_SEL_P<31> A_SEL_P<30> ++ A_SEL_P<29> A_SEL_P<28> A_WR_ONE A_WR_ZERO B_BLC<31> B_BLC<30> B_BLC<29> ++ B_BLC<28> B_BLC_SEL B_BLT<31> B_BLT<30> B_BLT<29> B_BLT<28> B_BLT_SEL ++ B_PRE_N B_SEL_P<31> B_SEL_P<30> B_SEL_P<29> B_SEL_P<28> B_WR_ONE B_WR_ZERO ++ VDD VSS / RM_IHPSG13_512x16_c2_2P_BLDRV +XAB_BLMUX<6> A_BLC<27> A_BLC<26> A_BLC<25> A_BLC<24> A_BLC_SEL A_BLT<27> ++ A_BLT<26> A_BLT<25> A_BLT<24> A_BLT_SEL A_PRE_N A_SEL_P<27> A_SEL_P<26> ++ A_SEL_P<25> A_SEL_P<24> A_WR_ONE A_WR_ZERO B_BLC<27> B_BLC<26> B_BLC<25> ++ B_BLC<24> B_BLC_SEL B_BLT<27> B_BLT<26> B_BLT<25> B_BLT<24> B_BLT_SEL ++ B_PRE_N B_SEL_P<27> B_SEL_P<26> B_SEL_P<25> B_SEL_P<24> B_WR_ONE B_WR_ZERO ++ VDD VSS / RM_IHPSG13_512x16_c2_2P_BLDRV +XAB_BLMUX<5> A_BLC<23> A_BLC<22> A_BLC<21> A_BLC<20> A_BLC_SEL A_BLT<23> ++ A_BLT<22> A_BLT<21> A_BLT<20> A_BLT_SEL A_PRE_N A_SEL_P<23> A_SEL_P<22> ++ A_SEL_P<21> A_SEL_P<20> A_WR_ONE A_WR_ZERO B_BLC<23> B_BLC<22> B_BLC<21> ++ B_BLC<20> B_BLC_SEL B_BLT<23> B_BLT<22> B_BLT<21> B_BLT<20> B_BLT_SEL ++ B_PRE_N B_SEL_P<23> B_SEL_P<22> B_SEL_P<21> B_SEL_P<20> B_WR_ONE B_WR_ZERO ++ VDD VSS / RM_IHPSG13_512x16_c2_2P_BLDRV +XAB_BLMUX<4> A_BLC<19> A_BLC<18> A_BLC<17> A_BLC<16> A_BLC_SEL A_BLT<19> ++ A_BLT<18> A_BLT<17> A_BLT<16> A_BLT_SEL A_PRE_N A_SEL_P<19> A_SEL_P<18> ++ A_SEL_P<17> A_SEL_P<16> A_WR_ONE A_WR_ZERO B_BLC<19> B_BLC<18> B_BLC<17> ++ B_BLC<16> B_BLC_SEL B_BLT<19> B_BLT<18> B_BLT<17> B_BLT<16> B_BLT_SEL ++ B_PRE_N B_SEL_P<19> B_SEL_P<18> B_SEL_P<17> B_SEL_P<16> B_WR_ONE B_WR_ZERO ++ VDD VSS / RM_IHPSG13_512x16_c2_2P_BLDRV +XAB_BLMUX<3> A_BLC<15> A_BLC<14> A_BLC<13> A_BLC<12> A_BLC_SEL A_BLT<15> ++ A_BLT<14> A_BLT<13> A_BLT<12> A_BLT_SEL A_PRE_N A_SEL_P<15> A_SEL_P<14> ++ A_SEL_P<13> A_SEL_P<12> A_WR_ONE A_WR_ZERO B_BLC<15> B_BLC<14> B_BLC<13> ++ B_BLC<12> B_BLC_SEL B_BLT<15> B_BLT<14> B_BLT<13> B_BLT<12> B_BLT_SEL ++ B_PRE_N B_SEL_P<15> B_SEL_P<14> B_SEL_P<13> B_SEL_P<12> B_WR_ONE B_WR_ZERO ++ VDD VSS / RM_IHPSG13_512x16_c2_2P_BLDRV +XAB_BLMUX<2> A_BLC<11> A_BLC<10> A_BLC<9> A_BLC<8> A_BLC_SEL A_BLT<11> ++ A_BLT<10> A_BLT<9> A_BLT<8> A_BLT_SEL A_PRE_N A_SEL_P<11> A_SEL_P<10> ++ A_SEL_P<9> A_SEL_P<8> A_WR_ONE A_WR_ZERO B_BLC<11> B_BLC<10> B_BLC<9> ++ B_BLC<8> B_BLC_SEL B_BLT<11> B_BLT<10> B_BLT<9> B_BLT<8> B_BLT_SEL B_PRE_N ++ B_SEL_P<11> B_SEL_P<10> B_SEL_P<9> B_SEL_P<8> B_WR_ONE B_WR_ZERO VDD ++ VSS / RM_IHPSG13_512x16_c2_2P_BLDRV +XAB_BLMUX<1> A_BLC<7> A_BLC<6> A_BLC<5> A_BLC<4> A_BLC_SEL A_BLT<7> A_BLT<6> ++ A_BLT<5> A_BLT<4> A_BLT_SEL A_PRE_N A_SEL_P<7> A_SEL_P<6> A_SEL_P<5> ++ A_SEL_P<4> A_WR_ONE A_WR_ZERO B_BLC<7> B_BLC<6> B_BLC<5> B_BLC<4> B_BLC_SEL ++ B_BLT<7> B_BLT<6> B_BLT<5> B_BLT<4> B_BLT_SEL B_PRE_N B_SEL_P<7> B_SEL_P<6> ++ B_SEL_P<5> B_SEL_P<4> B_WR_ONE B_WR_ZERO VDD VSS / ++ RM_IHPSG13_512x16_c2_2P_BLDRV +XAB_BLMUX<0> A_BLC<3> A_BLC<2> A_BLC<1> A_BLC<0> A_BLC_SEL A_BLT<3> A_BLT<2> ++ A_BLT<1> A_BLT<0> A_BLT_SEL A_PRE_N A_SEL_P<3> A_SEL_P<2> A_SEL_P<1> ++ A_SEL_P<0> A_WR_ONE A_WR_ZERO B_BLC<3> B_BLC<2> B_BLC<1> B_BLC<0> B_BLC_SEL ++ B_BLT<3> B_BLT<2> B_BLT<1> B_BLT<0> B_BLT_SEL B_PRE_N B_SEL_P<3> B_SEL_P<2> ++ B_SEL_P<1> B_SEL_P<0> B_WR_ONE B_WR_ZERO VDD VSS / ++ RM_IHPSG13_512x16_c2_2P_BLDRV +XB_I51 net037 B_DR_O VDD VSS / RSC_IHPSG13_INVX4 +XA_I51 net19 A_DR_O VDD VSS / RSC_IHPSG13_INVX4 +XB_I78 B_RCLK_B_L B_SAE VDD VSS / RSC_IHPSG13_CBUFX2 +XA_I78 A_RCLK_B_L A_SAE VDD VSS / RSC_IHPSG13_CBUFX2 +XB_I69 B_DCLK_L B_DCLK_B_L VDD VSS / RSC_IHPSG13_CINVX8 +XB_I50 B_WCLK_L B_WCLK_B_L VDD VSS / RSC_IHPSG13_CINVX8 +XB_EBUF B_RCLK_L B_RCLK_B_L VDD VSS / RSC_IHPSG13_CINVX8 +XA_I69 A_DCLK_L A_DCLK_B_L VDD VSS / RSC_IHPSG13_CINVX8 +XA_I50 A_WCLK_L A_WCLK_B_L VDD VSS / RSC_IHPSG13_CINVX8 +XA_EBUF A_RCLK_L A_RCLK_B_L VDD VSS / RSC_IHPSG13_CINVX8 +XB_I76 B_DI_N B_DO_WRITE_P B_WR_ZERO VDD VSS / RSC_IHPSG13_AND2X6 +XB_I75 B_DI_R B_DO_WRITE_P B_WR_ONE VDD VSS / RSC_IHPSG13_AND2X6 +XA_I76 A_DI_N A_DO_WRITE_P A_WR_ZERO VDD VSS / RSC_IHPSG13_AND2X6 +XA_I75 A_DI_R A_DO_WRITE_P A_WR_ONE VDD VSS / RSC_IHPSG13_AND2X6 +XB_I83 B_BM_R B_BM_N VDD VSS / RSC_IHPSG13_INVX2 +XB_DEC3INV<31> net041<0> B_SEL_P<31> VDD VSS / RSC_IHPSG13_INVX2 +XB_DEC3INV<30> net041<1> B_SEL_P<30> VDD VSS / RSC_IHPSG13_INVX2 +XB_DEC3INV<29> net041<2> B_SEL_P<29> VDD VSS / RSC_IHPSG13_INVX2 +XB_DEC3INV<28> net041<3> B_SEL_P<28> VDD VSS / RSC_IHPSG13_INVX2 +XB_DEC3INV<27> net041<4> B_SEL_P<27> VDD VSS / RSC_IHPSG13_INVX2 +XB_DEC3INV<26> net041<5> B_SEL_P<26> VDD VSS / RSC_IHPSG13_INVX2 +XB_DEC3INV<25> net041<6> B_SEL_P<25> VDD VSS / RSC_IHPSG13_INVX2 +XB_DEC3INV<24> net041<7> B_SEL_P<24> VDD VSS / RSC_IHPSG13_INVX2 +XB_DEC3INV<23> net041<8> B_SEL_P<23> VDD VSS / RSC_IHPSG13_INVX2 +XB_DEC3INV<22> net041<9> B_SEL_P<22> VDD VSS / RSC_IHPSG13_INVX2 +XB_DEC3INV<21> net041<10> B_SEL_P<21> VDD VSS / RSC_IHPSG13_INVX2 +XB_DEC3INV<20> net041<11> B_SEL_P<20> VDD VSS / RSC_IHPSG13_INVX2 +XB_DEC3INV<19> net041<12> B_SEL_P<19> VDD VSS / RSC_IHPSG13_INVX2 +XB_DEC3INV<18> net041<13> B_SEL_P<18> VDD VSS / RSC_IHPSG13_INVX2 +XB_DEC3INV<17> net041<14> B_SEL_P<17> VDD VSS / RSC_IHPSG13_INVX2 +XB_DEC3INV<16> net041<15> B_SEL_P<16> VDD VSS / RSC_IHPSG13_INVX2 +XB_DEC3INV<15> net041<16> B_SEL_P<15> VDD VSS / RSC_IHPSG13_INVX2 +XB_DEC3INV<14> net041<17> B_SEL_P<14> VDD VSS / RSC_IHPSG13_INVX2 +XB_DEC3INV<13> net041<18> B_SEL_P<13> VDD VSS / RSC_IHPSG13_INVX2 +XB_DEC3INV<12> net041<19> B_SEL_P<12> VDD VSS / RSC_IHPSG13_INVX2 +XB_DEC3INV<11> net041<20> B_SEL_P<11> VDD VSS / RSC_IHPSG13_INVX2 +XB_DEC3INV<10> net041<21> B_SEL_P<10> VDD VSS / RSC_IHPSG13_INVX2 +XB_DEC3INV<9> net041<22> B_SEL_P<9> VDD VSS / RSC_IHPSG13_INVX2 +XB_DEC3INV<8> net041<23> B_SEL_P<8> VDD VSS / RSC_IHPSG13_INVX2 +XB_DEC3INV<7> net041<24> B_SEL_P<7> VDD VSS / RSC_IHPSG13_INVX2 +XB_DEC3INV<6> net041<25> B_SEL_P<6> VDD VSS / RSC_IHPSG13_INVX2 +XB_DEC3INV<5> net041<26> B_SEL_P<5> VDD VSS / RSC_IHPSG13_INVX2 +XB_DEC3INV<4> net041<27> B_SEL_P<4> VDD VSS / RSC_IHPSG13_INVX2 +XB_DEC3INV<3> net041<28> B_SEL_P<3> VDD VSS / RSC_IHPSG13_INVX2 +XB_DEC3INV<2> net041<29> B_SEL_P<2> VDD VSS / RSC_IHPSG13_INVX2 +XB_DEC3INV<1> net041<30> B_SEL_P<1> VDD VSS / RSC_IHPSG13_INVX2 +XB_DEC3INV<0> net041<31> B_SEL_P<0> VDD VSS / RSC_IHPSG13_INVX2 +XB_I49 B_DI_R B_DI_N VDD VSS / RSC_IHPSG13_INVX2 +XA_I83 A_BM_R A_BM_N VDD VSS / RSC_IHPSG13_INVX2 +XA_DEC3INV<31> net23<0> A_SEL_P<31> VDD VSS / RSC_IHPSG13_INVX2 +XA_DEC3INV<30> net23<1> A_SEL_P<30> VDD VSS / RSC_IHPSG13_INVX2 +XA_DEC3INV<29> net23<2> A_SEL_P<29> VDD VSS / RSC_IHPSG13_INVX2 +XA_DEC3INV<28> net23<3> A_SEL_P<28> VDD VSS / RSC_IHPSG13_INVX2 +XA_DEC3INV<27> net23<4> A_SEL_P<27> VDD VSS / RSC_IHPSG13_INVX2 +XA_DEC3INV<26> net23<5> A_SEL_P<26> VDD VSS / RSC_IHPSG13_INVX2 +XA_DEC3INV<25> net23<6> A_SEL_P<25> VDD VSS / RSC_IHPSG13_INVX2 +XA_DEC3INV<24> net23<7> A_SEL_P<24> VDD VSS / RSC_IHPSG13_INVX2 +XA_DEC3INV<23> net23<8> A_SEL_P<23> VDD VSS / RSC_IHPSG13_INVX2 +XA_DEC3INV<22> net23<9> A_SEL_P<22> VDD VSS / RSC_IHPSG13_INVX2 +XA_DEC3INV<21> net23<10> A_SEL_P<21> VDD VSS / RSC_IHPSG13_INVX2 +XA_DEC3INV<20> net23<11> A_SEL_P<20> VDD VSS / RSC_IHPSG13_INVX2 +XA_DEC3INV<19> net23<12> A_SEL_P<19> VDD VSS / RSC_IHPSG13_INVX2 +XA_DEC3INV<18> net23<13> A_SEL_P<18> VDD VSS / RSC_IHPSG13_INVX2 +XA_DEC3INV<17> net23<14> A_SEL_P<17> VDD VSS / RSC_IHPSG13_INVX2 +XA_DEC3INV<16> net23<15> A_SEL_P<16> VDD VSS / RSC_IHPSG13_INVX2 +XA_DEC3INV<15> net23<16> A_SEL_P<15> VDD VSS / RSC_IHPSG13_INVX2 +XA_DEC3INV<14> net23<17> A_SEL_P<14> VDD VSS / RSC_IHPSG13_INVX2 +XA_DEC3INV<13> net23<18> A_SEL_P<13> VDD VSS / RSC_IHPSG13_INVX2 +XA_DEC3INV<12> net23<19> A_SEL_P<12> VDD VSS / RSC_IHPSG13_INVX2 +XA_DEC3INV<11> net23<20> A_SEL_P<11> VDD VSS / RSC_IHPSG13_INVX2 +XA_DEC3INV<10> net23<21> A_SEL_P<10> VDD VSS / RSC_IHPSG13_INVX2 +XA_DEC3INV<9> net23<22> A_SEL_P<9> VDD VSS / RSC_IHPSG13_INVX2 +XA_DEC3INV<8> net23<23> A_SEL_P<8> VDD VSS / RSC_IHPSG13_INVX2 +XA_DEC3INV<7> net23<24> A_SEL_P<7> VDD VSS / RSC_IHPSG13_INVX2 +XA_DEC3INV<6> net23<25> A_SEL_P<6> VDD VSS / RSC_IHPSG13_INVX2 +XA_DEC3INV<5> net23<26> A_SEL_P<5> VDD VSS / RSC_IHPSG13_INVX2 +XA_DEC3INV<4> net23<27> A_SEL_P<4> VDD VSS / RSC_IHPSG13_INVX2 +XA_DEC3INV<3> net23<28> A_SEL_P<3> VDD VSS / RSC_IHPSG13_INVX2 +XA_DEC3INV<2> net23<29> A_SEL_P<2> VDD VSS / RSC_IHPSG13_INVX2 +XA_DEC3INV<1> net23<30> A_SEL_P<1> VDD VSS / RSC_IHPSG13_INVX2 +XA_DEC3INV<0> net23<31> A_SEL_P<0> VDD VSS / RSC_IHPSG13_INVX2 +XA_I49 A_DI_R A_DI_N VDD VSS / RSC_IHPSG13_INVX2 +XB_ISENSE B_SAE B_BLC_SEL B_BLT_SEL net037 net038 VDD VSS / ++ RSC_IHPSG13_DFPQD_MSAFFX2 +XA_ISENSE A_SAE A_BLC_SEL A_BLT_SEL net19 net20 VDD VSS / ++ RSC_IHPSG13_DFPQD_MSAFFX2 +XB_DREG B_BIST_EN_I B_BIST_DW_I B_DCLK_B_L B_DW_I B_DI_R net042 VDD ++ VSS / RSC_IHPSG13_DFNQMX2IX1 +XB_BREG B_BIST_EN_I B_BIST_BM_I B_DCLK_B_L B_BM_I B_BM_R net043 VDD ++ VSS / RSC_IHPSG13_DFNQMX2IX1 +XA_DREG A_BIST_EN_I A_BIST_DW_I A_DCLK_B_L A_DW_I A_DI_R net22 VDD VSS ++ / RSC_IHPSG13_DFNQMX2IX1 +XA_BREG A_BIST_EN_I A_BIST_BM_I A_DCLK_B_L A_BM_I A_BM_R net21 VDD VSS ++ / RSC_IHPSG13_DFNQMX2IX1 +XB_DEC3<31> B_P1<1> B_P0<1> B_ADDR_DEC<7> net041<0> VDD VSS / ++ RSC_IHPSG13_NAND3X2 +XB_DEC3<30> B_P1<1> B_P0<1> B_ADDR_DEC<6> net041<1> VDD VSS / ++ RSC_IHPSG13_NAND3X2 +XB_DEC3<29> B_P1<1> B_P0<1> B_ADDR_DEC<5> net041<2> VDD VSS / ++ RSC_IHPSG13_NAND3X2 +XB_DEC3<28> B_P1<1> B_P0<1> B_ADDR_DEC<4> net041<3> VDD VSS / ++ RSC_IHPSG13_NAND3X2 +XB_DEC3<27> B_P1<1> B_P0<1> B_ADDR_DEC<3> net041<4> VDD VSS / ++ RSC_IHPSG13_NAND3X2 +XB_DEC3<26> B_P1<1> B_P0<1> B_ADDR_DEC<2> net041<5> VDD VSS / ++ RSC_IHPSG13_NAND3X2 +XB_DEC3<25> B_P1<1> B_P0<1> B_ADDR_DEC<1> net041<6> VDD VSS / ++ RSC_IHPSG13_NAND3X2 +XB_DEC3<24> B_P1<1> B_P0<1> B_ADDR_DEC<0> net041<7> VDD VSS / ++ RSC_IHPSG13_NAND3X2 +XB_DEC3<23> B_P1<1> B_N0<1> B_ADDR_DEC<7> net041<8> VDD VSS / ++ RSC_IHPSG13_NAND3X2 +XB_DEC3<22> B_P1<1> B_N0<1> B_ADDR_DEC<6> net041<9> VDD VSS / ++ RSC_IHPSG13_NAND3X2 +XB_DEC3<21> B_P1<1> B_N0<1> B_ADDR_DEC<5> net041<10> VDD VSS / ++ RSC_IHPSG13_NAND3X2 +XB_DEC3<20> B_P1<1> B_N0<1> B_ADDR_DEC<4> net041<11> VDD VSS / ++ RSC_IHPSG13_NAND3X2 +XB_DEC3<19> B_P1<1> B_N0<1> B_ADDR_DEC<3> net041<12> VDD VSS / ++ RSC_IHPSG13_NAND3X2 +XB_DEC3<18> B_P1<1> B_N0<1> B_ADDR_DEC<2> net041<13> VDD VSS / ++ RSC_IHPSG13_NAND3X2 +XB_DEC3<17> B_P1<1> B_N0<1> B_ADDR_DEC<1> net041<14> VDD VSS / ++ RSC_IHPSG13_NAND3X2 +XB_DEC3<16> B_P1<1> B_N0<1> B_ADDR_DEC<0> net041<15> VDD VSS / ++ RSC_IHPSG13_NAND3X2 +XB_DEC3<15> B_N1<0> B_P0<0> B_ADDR_DEC<7> net041<16> VDD VSS / ++ RSC_IHPSG13_NAND3X2 +XB_DEC3<14> B_N1<0> B_P0<0> B_ADDR_DEC<6> net041<17> VDD VSS / ++ RSC_IHPSG13_NAND3X2 +XB_DEC3<13> B_N1<0> B_P0<0> B_ADDR_DEC<5> net041<18> VDD VSS / ++ RSC_IHPSG13_NAND3X2 +XB_DEC3<12> B_N1<0> B_P0<0> B_ADDR_DEC<4> net041<19> VDD VSS / ++ RSC_IHPSG13_NAND3X2 +XB_DEC3<11> B_N1<0> B_P0<0> B_ADDR_DEC<3> net041<20> VDD VSS / ++ RSC_IHPSG13_NAND3X2 +XB_DEC3<10> B_N1<0> B_P0<0> B_ADDR_DEC<2> net041<21> VDD VSS / ++ RSC_IHPSG13_NAND3X2 +XB_DEC3<9> B_N1<0> B_P0<0> B_ADDR_DEC<1> net041<22> VDD VSS / ++ RSC_IHPSG13_NAND3X2 +XB_DEC3<8> B_N1<0> B_P0<0> B_ADDR_DEC<0> net041<23> VDD VSS / ++ RSC_IHPSG13_NAND3X2 +XB_DEC3<7> B_N1<0> B_N0<0> B_ADDR_DEC<7> net041<24> VDD VSS / ++ RSC_IHPSG13_NAND3X2 +XB_DEC3<6> B_N1<0> B_N0<0> B_ADDR_DEC<6> net041<25> VDD VSS / ++ RSC_IHPSG13_NAND3X2 +XB_DEC3<5> B_N1<0> B_N0<0> B_ADDR_DEC<5> net041<26> VDD VSS / ++ RSC_IHPSG13_NAND3X2 +XB_DEC3<4> B_N1<0> B_N0<0> B_ADDR_DEC<4> net041<27> VDD VSS / ++ RSC_IHPSG13_NAND3X2 +XB_DEC3<3> B_N1<0> B_N0<0> B_ADDR_DEC<3> net041<28> VDD VSS / ++ RSC_IHPSG13_NAND3X2 +XB_DEC3<2> B_N1<0> B_N0<0> B_ADDR_DEC<2> net041<29> VDD VSS / ++ RSC_IHPSG13_NAND3X2 +XB_DEC3<1> B_N1<0> B_N0<0> B_ADDR_DEC<1> net041<30> VDD VSS / ++ RSC_IHPSG13_NAND3X2 +XB_DEC3<0> B_N1<0> B_N0<0> B_ADDR_DEC<0> net041<31> VDD VSS / ++ RSC_IHPSG13_NAND3X2 +XA_DEC3<31> A_P1<1> A_P0<1> A_ADDR_DEC<7> net23<0> VDD VSS / ++ RSC_IHPSG13_NAND3X2 +XA_DEC3<30> A_P1<1> A_P0<1> A_ADDR_DEC<6> net23<1> VDD VSS / ++ RSC_IHPSG13_NAND3X2 +XA_DEC3<29> A_P1<1> A_P0<1> A_ADDR_DEC<5> net23<2> VDD VSS / ++ RSC_IHPSG13_NAND3X2 +XA_DEC3<28> A_P1<1> A_P0<1> A_ADDR_DEC<4> net23<3> VDD VSS / ++ RSC_IHPSG13_NAND3X2 +XA_DEC3<27> A_P1<1> A_P0<1> A_ADDR_DEC<3> net23<4> VDD VSS / ++ RSC_IHPSG13_NAND3X2 +XA_DEC3<26> A_P1<1> A_P0<1> A_ADDR_DEC<2> net23<5> VDD VSS / ++ RSC_IHPSG13_NAND3X2 +XA_DEC3<25> A_P1<1> A_P0<1> A_ADDR_DEC<1> net23<6> VDD VSS / ++ RSC_IHPSG13_NAND3X2 +XA_DEC3<24> A_P1<1> A_P0<1> A_ADDR_DEC<0> net23<7> VDD VSS / ++ RSC_IHPSG13_NAND3X2 +XA_DEC3<23> A_P1<1> A_N0<1> A_ADDR_DEC<7> net23<8> VDD VSS / ++ RSC_IHPSG13_NAND3X2 +XA_DEC3<22> A_P1<1> A_N0<1> A_ADDR_DEC<6> net23<9> VDD VSS / ++ RSC_IHPSG13_NAND3X2 +XA_DEC3<21> A_P1<1> A_N0<1> A_ADDR_DEC<5> net23<10> VDD VSS / ++ RSC_IHPSG13_NAND3X2 +XA_DEC3<20> A_P1<1> A_N0<1> A_ADDR_DEC<4> net23<11> VDD VSS / ++ RSC_IHPSG13_NAND3X2 +XA_DEC3<19> A_P1<1> A_N0<1> A_ADDR_DEC<3> net23<12> VDD VSS / ++ RSC_IHPSG13_NAND3X2 +XA_DEC3<18> A_P1<1> A_N0<1> A_ADDR_DEC<2> net23<13> VDD VSS / ++ RSC_IHPSG13_NAND3X2 +XA_DEC3<17> A_P1<1> A_N0<1> A_ADDR_DEC<1> net23<14> VDD VSS / ++ RSC_IHPSG13_NAND3X2 +XA_DEC3<16> A_P1<1> A_N0<1> A_ADDR_DEC<0> net23<15> VDD VSS / ++ RSC_IHPSG13_NAND3X2 +XA_DEC3<15> A_N1<0> A_P0<0> A_ADDR_DEC<7> net23<16> VDD VSS / ++ RSC_IHPSG13_NAND3X2 +XA_DEC3<14> A_N1<0> A_P0<0> A_ADDR_DEC<6> net23<17> VDD VSS / ++ RSC_IHPSG13_NAND3X2 +XA_DEC3<13> A_N1<0> A_P0<0> A_ADDR_DEC<5> net23<18> VDD VSS / ++ RSC_IHPSG13_NAND3X2 +XA_DEC3<12> A_N1<0> A_P0<0> A_ADDR_DEC<4> net23<19> VDD VSS / ++ RSC_IHPSG13_NAND3X2 +XA_DEC3<11> A_N1<0> A_P0<0> A_ADDR_DEC<3> net23<20> VDD VSS / ++ RSC_IHPSG13_NAND3X2 +XA_DEC3<10> A_N1<0> A_P0<0> A_ADDR_DEC<2> net23<21> VDD VSS / ++ RSC_IHPSG13_NAND3X2 +XA_DEC3<9> A_N1<0> A_P0<0> A_ADDR_DEC<1> net23<22> VDD VSS / ++ RSC_IHPSG13_NAND3X2 +XA_DEC3<8> A_N1<0> A_P0<0> A_ADDR_DEC<0> net23<23> VDD VSS / ++ RSC_IHPSG13_NAND3X2 +XA_DEC3<7> A_N1<0> A_N0<0> A_ADDR_DEC<7> net23<24> VDD VSS / ++ RSC_IHPSG13_NAND3X2 +XA_DEC3<6> A_N1<0> A_N0<0> A_ADDR_DEC<6> net23<25> VDD VSS / ++ RSC_IHPSG13_NAND3X2 +XA_DEC3<5> A_N1<0> A_N0<0> A_ADDR_DEC<5> net23<26> VDD VSS / ++ RSC_IHPSG13_NAND3X2 +XA_DEC3<4> A_N1<0> A_N0<0> A_ADDR_DEC<4> net23<27> VDD VSS / ++ RSC_IHPSG13_NAND3X2 +XA_DEC3<3> A_N1<0> A_N0<0> A_ADDR_DEC<3> net23<28> VDD VSS / ++ RSC_IHPSG13_NAND3X2 +XA_DEC3<2> A_N1<0> A_N0<0> A_ADDR_DEC<2> net23<29> VDD VSS / ++ RSC_IHPSG13_NAND3X2 +XA_DEC3<1> A_N1<0> A_N0<0> A_ADDR_DEC<1> net23<30> VDD VSS / ++ RSC_IHPSG13_NAND3X2 +XA_DEC3<0> A_N1<0> A_N0<0> A_ADDR_DEC<0> net23<31> VDD VSS / ++ RSC_IHPSG13_NAND3X2 +XB_I89 B_DCLK_B_L B_DCLK_B_R / RSC_IHPSG13_MET3RES +XB_I91 B_RCLK_B_L B_RCLK_B_R / RSC_IHPSG13_MET3RES +XB_I90 B_WCLK_B_L B_WCLK_B_R / RSC_IHPSG13_MET3RES +XB_I88 B_DCLK_L B_DCLK_R / RSC_IHPSG13_MET3RES +XB_I87 B_WCLK_L B_WCLK_R / RSC_IHPSG13_MET3RES +XB_R2 B_RCLK_L B_RCLK_R / RSC_IHPSG13_MET3RES +XA_I89 A_DCLK_B_L A_DCLK_B_R / RSC_IHPSG13_MET3RES +XA_I91 A_RCLK_B_L A_RCLK_B_R / RSC_IHPSG13_MET3RES +XA_I90 A_WCLK_B_L A_WCLK_B_R / RSC_IHPSG13_MET3RES +XA_I88 A_DCLK_L A_DCLK_R / RSC_IHPSG13_MET3RES +XA_I87 A_WCLK_L A_WCLK_R / RSC_IHPSG13_MET3RES +XA_R2 A_RCLK_L A_RCLK_R / RSC_IHPSG13_MET3RES +XB_BM_TIEH B_TIEH_O VDD VSS / RSC_IHPSG13_TIEH +XA_BM_TIEH A_TIEH_O VDD VSS / RSC_IHPSG13_TIEH +.ENDS +.SUBCKT RM_IHPSG13_512x16_c2_2P_COLDRV13_FILL4 VDD VSS +XI0<11> VDD VSS / RSC_IHPSG13_FILLCAP4 +XI0<10> VDD VSS / RSC_IHPSG13_FILLCAP4 +XI0<9> VDD VSS / RSC_IHPSG13_FILLCAP4 +XI0<8> VDD VSS / RSC_IHPSG13_FILLCAP4 +XI0<7> VDD VSS / RSC_IHPSG13_FILLCAP4 +XI0<6> VDD VSS / RSC_IHPSG13_FILLCAP4 +XI0<5> VDD VSS / RSC_IHPSG13_FILLCAP4 +XI0<4> VDD VSS / RSC_IHPSG13_FILLCAP4 +XI0<3> VDD VSS / RSC_IHPSG13_FILLCAP4 +XI0<2> VDD VSS / RSC_IHPSG13_FILLCAP4 +XI0<1> VDD VSS / RSC_IHPSG13_FILLCAP4 +.ENDS + + +.SUBCKT RSC_IHPSG13_CBUFX16 A Z VDD VSS +MN0 net4 A VSS VSS sg13_lv_nmos m=1 w=2.115u l=130.00n ng=3 nrd=0 nrs=0 +MN1 Z net4 VSS VSS sg13_lv_nmos m=1 w=5.64u l=130.00n ng=8 nrd=0 nrs=0 +MP1 Z net4 VDD VDD sg13_lv_pmos m=1 w=13.000u l=130.00n ng=8 nrd=0 ++ nrs=0 +MP0 net4 A VDD VDD sg13_lv_pmos m=1 w=4.89u l=130.00n ng=3 nrd=0 nrs=0 +.ENDS +.SUBCKT RM_IHPSG13_512x16_c2_1P_COLDRV13X16 ADDR_COL_I<1> ADDR_COL_I<0> ADDR_COL_O<1> ++ ADDR_COL_O<0> ADDR_DEC_I<7> ADDR_DEC_I<6> ADDR_DEC_I<5> ADDR_DEC_I<4> ++ ADDR_DEC_I<3> ADDR_DEC_I<2> ADDR_DEC_I<1> ADDR_DEC_I<0> ADDR_DEC_O<7> ++ ADDR_DEC_O<6> ADDR_DEC_O<5> ADDR_DEC_O<4> ADDR_DEC_O<3> ADDR_DEC_O<2> ++ ADDR_DEC_O<1> ADDR_DEC_O<0> DCLK_I DCLK_O RCLK_I RCLK_O WCLK_I WCLK_O ++ VDD VSS +XI1<1> VDD VSS / RSC_IHPSG13_FILLCAP4 +XI1<0> VDD VSS / RSC_IHPSG13_FILLCAP4 +XI0<3> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI0<2> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI0<1> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI0<0> VDD VSS / RSC_IHPSG13_FILLCAP8 +XADDR_COL_DRV<1> ADDR_COL_I<1> ADDR_COL_O<1> VDD VSS / ++ RSC_IHPSG13_CBUFX16 +XADDR_COL_DRV<0> ADDR_COL_I<0> ADDR_COL_O<0> VDD VSS / ++ RSC_IHPSG13_CBUFX16 +XADDR_DEC_DRV<7> ADDR_DEC_I<7> ADDR_DEC_O<7> VDD VSS / ++ RSC_IHPSG13_CBUFX16 +XADDR_DEC_DRV<6> ADDR_DEC_I<6> ADDR_DEC_O<6> VDD VSS / ++ RSC_IHPSG13_CBUFX16 +XADDR_DEC_DRV<5> ADDR_DEC_I<5> ADDR_DEC_O<5> VDD VSS / ++ RSC_IHPSG13_CBUFX16 +XADDR_DEC_DRV<4> ADDR_DEC_I<4> ADDR_DEC_O<4> VDD VSS / ++ RSC_IHPSG13_CBUFX16 +XADDR_DEC_DRV<3> ADDR_DEC_I<3> ADDR_DEC_O<3> VDD VSS / ++ RSC_IHPSG13_CBUFX16 +XADDR_DEC_DRV<2> ADDR_DEC_I<2> ADDR_DEC_O<2> VDD VSS / ++ RSC_IHPSG13_CBUFX16 +XADDR_DEC_DRV<1> ADDR_DEC_I<1> ADDR_DEC_O<1> VDD VSS / ++ RSC_IHPSG13_CBUFX16 +XADDR_DEC_DRV<0> ADDR_DEC_I<0> ADDR_DEC_O<0> VDD VSS / ++ RSC_IHPSG13_CBUFX16 +XDCLK_DRV DCLK_I DCLK_O VDD VSS / RSC_IHPSG13_CBUFX16 +XRCLK_DRV RCLK_I RCLK_O VDD VSS / RSC_IHPSG13_CBUFX16 +XWCLK_DRV WCLK_I WCLK_O VDD VSS / RSC_IHPSG13_CBUFX16 +.ENDS +.SUBCKT RSC_IHPSG13_WLDRVX16 A Z VDD VSS +MN1 Z net6 VSS VSS sg13_lv_nmos m=1 w=1.41u l=130.00n ng=2 nrd=0 nrs=0 +MN0 net6 A VSS VSS sg13_lv_nmos m=1 w=1.8u l=130.00n ng=2 nrd=0 nrs=0 +MP1 Z net6 VDD VDD sg13_lv_pmos m=1 w=12.96u l=130.00n ng=8 nrd=0 nrs=0 +MP0 net6 A VDD VDD sg13_lv_pmos m=1 w=900.0n l=130.00n ng=1 nrd=0 nrs=0 +.ENDS +.SUBCKT RM_IHPSG13_512x16_c2_1P_WLDRV16X16 A<15> A<14> A<13> A<12> A<11> A<10> A<9> A<8> ++ A<7> A<6> A<5> A<4> A<3> A<2> A<1> A<0> Z<15> Z<14> Z<13> Z<12> Z<11> Z<10> ++ Z<9> Z<8> Z<7> Z<6> Z<5> Z<4> Z<3> Z<2> Z<1> Z<0> VDD VSS +XBUF<15> A<15> Z<15> VDD VSS / RSC_IHPSG13_WLDRVX16 +XBUF<14> A<14> Z<14> VDD VSS / RSC_IHPSG13_WLDRVX16 +XBUF<13> A<13> Z<13> VDD VSS / RSC_IHPSG13_WLDRVX16 +XBUF<12> A<12> Z<12> VDD VSS / RSC_IHPSG13_WLDRVX16 +XBUF<11> A<11> Z<11> VDD VSS / RSC_IHPSG13_WLDRVX16 +XBUF<10> A<10> Z<10> VDD VSS / RSC_IHPSG13_WLDRVX16 +XBUF<9> A<9> Z<9> VDD VSS / RSC_IHPSG13_WLDRVX16 +XBUF<8> A<8> Z<8> VDD VSS / RSC_IHPSG13_WLDRVX16 +XBUF<7> A<7> Z<7> VDD VSS / RSC_IHPSG13_WLDRVX16 +XBUF<6> A<6> Z<6> VDD VSS / RSC_IHPSG13_WLDRVX16 +XBUF<5> A<5> Z<5> VDD VSS / RSC_IHPSG13_WLDRVX16 +XBUF<4> A<4> Z<4> VDD VSS / RSC_IHPSG13_WLDRVX16 +XBUF<3> A<3> Z<3> VDD VSS / RSC_IHPSG13_WLDRVX16 +XBUF<2> A<2> Z<2> VDD VSS / RSC_IHPSG13_WLDRVX16 +XBUF<1> A<1> Z<1> VDD VSS / RSC_IHPSG13_WLDRVX16 +XBUF<0> A<0> Z<0> VDD VSS / RSC_IHPSG13_WLDRVX16 +.ENDS + + +.SUBCKT RM_IHPSG13_512x16_c2_2P_COLDRV13X4 ADDR_COL_I<1> ADDR_COL_I<0> ADDR_COL_O<1> ++ ADDR_COL_O<0> ADDR_DEC_I<7> ADDR_DEC_I<6> ADDR_DEC_I<5> ADDR_DEC_I<4> ++ ADDR_DEC_I<3> ADDR_DEC_I<2> ADDR_DEC_I<1> ADDR_DEC_I<0> ADDR_DEC_O<7> ++ ADDR_DEC_O<6> ADDR_DEC_O<5> ADDR_DEC_O<4> ADDR_DEC_O<3> ADDR_DEC_O<2> ++ ADDR_DEC_O<1> ADDR_DEC_O<0> DCLK_I DCLK_O RCLK_I RCLK_O WCLK_I WCLK_O ++ VDD VSS +XWCLK_DRV WCLK_I WCLK_O VDD VSS / RSC_IHPSG13_CBUFX4 +XRCLK_DRV RCLK_I RCLK_O VDD VSS / RSC_IHPSG13_CBUFX4 +XDCLK_DRV DCLK_I DCLK_O VDD VSS / RSC_IHPSG13_CBUFX4 +XADDR_COL_DRV<1> ADDR_COL_I<1> ADDR_COL_O<1> VDD VSS / ++ RSC_IHPSG13_CBUFX4 +XADDR_COL_DRV<0> ADDR_COL_I<0> ADDR_COL_O<0> VDD VSS / ++ RSC_IHPSG13_CBUFX4 +XADDR_DEC_DRV<7> ADDR_DEC_I<7> ADDR_DEC_O<7> VDD VSS / ++ RSC_IHPSG13_CBUFX4 +XADDR_DEC_DRV<6> ADDR_DEC_I<6> ADDR_DEC_O<6> VDD VSS / ++ RSC_IHPSG13_CBUFX4 +XADDR_DEC_DRV<5> ADDR_DEC_I<5> ADDR_DEC_O<5> VDD VSS / ++ RSC_IHPSG13_CBUFX4 +XADDR_DEC_DRV<4> ADDR_DEC_I<4> ADDR_DEC_O<4> VDD VSS / ++ RSC_IHPSG13_CBUFX4 +XADDR_DEC_DRV<3> ADDR_DEC_I<3> ADDR_DEC_O<3> VDD VSS / ++ RSC_IHPSG13_CBUFX4 +XADDR_DEC_DRV<2> ADDR_DEC_I<2> ADDR_DEC_O<2> VDD VSS / ++ RSC_IHPSG13_CBUFX4 +XADDR_DEC_DRV<1> ADDR_DEC_I<1> ADDR_DEC_O<1> VDD VSS / ++ RSC_IHPSG13_CBUFX4 +XADDR_DEC_DRV<0> ADDR_DEC_I<0> ADDR_DEC_O<0> VDD VSS / ++ RSC_IHPSG13_CBUFX4 +XI0<6> VDD VSS / RSC_IHPSG13_FILLCAP4 +XI0<5> VDD VSS / RSC_IHPSG13_FILLCAP4 +XI0<4> VDD VSS / RSC_IHPSG13_FILLCAP4 +XI0<3> VDD VSS / RSC_IHPSG13_FILLCAP4 +XI0<2> VDD VSS / RSC_IHPSG13_FILLCAP4 +XI0<1> VDD VSS / RSC_IHPSG13_FILLCAP4 +XI1 VDD VSS / RSC_IHPSG13_FILLCAP8 +.ENDS +.SUBCKT RM_IHPSG13_512x16_c2_2P_WLDRV16X4 A<15> A<14> A<13> A<12> A<11> A<10> A<9> A<8> ++ A<7> A<6> A<5> A<4> A<3> A<2> A<1> A<0> Z<15> Z<14> Z<13> Z<12> Z<11> Z<10> ++ Z<9> Z<8> Z<7> Z<6> Z<5> Z<4> Z<3> Z<2> Z<1> Z<0> VDD VSS +XBUF<15> A<15> Z<15> VDD VSS / RSC_IHPSG13_WLDRVX4 +XBUF<14> A<14> Z<14> VDD VSS / RSC_IHPSG13_WLDRVX4 +XBUF<13> A<13> Z<13> VDD VSS / RSC_IHPSG13_WLDRVX4 +XBUF<12> A<12> Z<12> VDD VSS / RSC_IHPSG13_WLDRVX4 +XBUF<11> A<11> Z<11> VDD VSS / RSC_IHPSG13_WLDRVX4 +XBUF<10> A<10> Z<10> VDD VSS / RSC_IHPSG13_WLDRVX4 +XBUF<9> A<9> Z<9> VDD VSS / RSC_IHPSG13_WLDRVX4 +XBUF<8> A<8> Z<8> VDD VSS / RSC_IHPSG13_WLDRVX4 +XBUF<7> A<7> Z<7> VDD VSS / RSC_IHPSG13_WLDRVX4 +XBUF<6> A<6> Z<6> VDD VSS / RSC_IHPSG13_WLDRVX4 +XBUF<5> A<5> Z<5> VDD VSS / RSC_IHPSG13_WLDRVX4 +XBUF<4> A<4> Z<4> VDD VSS / RSC_IHPSG13_WLDRVX4 +XBUF<3> A<3> Z<3> VDD VSS / RSC_IHPSG13_WLDRVX4 +XBUF<2> A<2> Z<2> VDD VSS / RSC_IHPSG13_WLDRVX4 +XBUF<1> A<1> Z<1> VDD VSS / RSC_IHPSG13_WLDRVX4 +XBUF<0> A<0> Z<0> VDD VSS / RSC_IHPSG13_WLDRVX4 +.ENDS +.SUBCKT RM_IHPSG13_512x16_c2_2P_ROWDEC8 ADDR_N_I<7> ADDR_N_I<6> ADDR_N_I<5> ADDR_N_I<4> ++ ADDR_N_I<3> ADDR_N_I<2> ADDR_N_I<1> ADDR_N_I<0> CS_I ECLK_I WL_O<255> ++ WL_O<254> WL_O<253> WL_O<252> WL_O<251> WL_O<250> WL_O<249> WL_O<248> ++ WL_O<247> WL_O<246> WL_O<245> WL_O<244> WL_O<243> WL_O<242> WL_O<241> ++ WL_O<240> WL_O<239> WL_O<238> WL_O<237> WL_O<236> WL_O<235> WL_O<234> ++ WL_O<233> WL_O<232> WL_O<231> WL_O<230> WL_O<229> WL_O<228> WL_O<227> ++ WL_O<226> WL_O<225> WL_O<224> WL_O<223> WL_O<222> WL_O<221> WL_O<220> ++ WL_O<219> WL_O<218> WL_O<217> WL_O<216> WL_O<215> WL_O<214> WL_O<213> ++ WL_O<212> WL_O<211> WL_O<210> WL_O<209> WL_O<208> WL_O<207> WL_O<206> ++ WL_O<205> WL_O<204> WL_O<203> WL_O<202> WL_O<201> WL_O<200> WL_O<199> ++ WL_O<198> WL_O<197> WL_O<196> WL_O<195> WL_O<194> WL_O<193> WL_O<192> ++ WL_O<191> WL_O<190> WL_O<189> WL_O<188> WL_O<187> WL_O<186> WL_O<185> ++ WL_O<184> WL_O<183> WL_O<182> WL_O<181> WL_O<180> WL_O<179> WL_O<178> ++ WL_O<177> WL_O<176> WL_O<175> WL_O<174> WL_O<173> WL_O<172> WL_O<171> ++ WL_O<170> WL_O<169> WL_O<168> WL_O<167> WL_O<166> WL_O<165> WL_O<164> ++ WL_O<163> WL_O<162> WL_O<161> WL_O<160> WL_O<159> WL_O<158> WL_O<157> ++ WL_O<156> WL_O<155> WL_O<154> WL_O<153> WL_O<152> WL_O<151> WL_O<150> ++ WL_O<149> WL_O<148> WL_O<147> WL_O<146> WL_O<145> WL_O<144> WL_O<143> ++ WL_O<142> WL_O<141> WL_O<140> WL_O<139> WL_O<138> WL_O<137> WL_O<136> ++ WL_O<135> WL_O<134> WL_O<133> WL_O<132> WL_O<131> WL_O<130> WL_O<129> ++ WL_O<128> WL_O<127> WL_O<126> WL_O<125> WL_O<124> WL_O<123> WL_O<122> ++ WL_O<121> WL_O<120> WL_O<119> WL_O<118> WL_O<117> WL_O<116> WL_O<115> ++ WL_O<114> WL_O<113> WL_O<112> WL_O<111> WL_O<110> WL_O<109> WL_O<108> ++ WL_O<107> WL_O<106> WL_O<105> WL_O<104> WL_O<103> WL_O<102> WL_O<101> ++ WL_O<100> WL_O<99> WL_O<98> WL_O<97> WL_O<96> WL_O<95> WL_O<94> WL_O<93> ++ WL_O<92> WL_O<91> WL_O<90> WL_O<89> WL_O<88> WL_O<87> WL_O<86> WL_O<85> ++ WL_O<84> WL_O<83> WL_O<82> WL_O<81> WL_O<80> WL_O<79> WL_O<78> WL_O<77> ++ WL_O<76> WL_O<75> WL_O<74> WL_O<73> WL_O<72> WL_O<71> WL_O<70> WL_O<69> ++ WL_O<68> WL_O<67> WL_O<66> WL_O<65> WL_O<64> WL_O<63> WL_O<62> WL_O<61> ++ WL_O<60> WL_O<59> WL_O<58> WL_O<57> WL_O<56> WL_O<55> WL_O<54> WL_O<53> ++ WL_O<52> WL_O<51> WL_O<50> WL_O<49> WL_O<48> WL_O<47> WL_O<46> WL_O<45> ++ WL_O<44> WL_O<43> WL_O<42> WL_O<41> WL_O<40> WL_O<39> WL_O<38> WL_O<37> ++ WL_O<36> WL_O<35> WL_O<34> WL_O<33> WL_O<32> WL_O<31> WL_O<30> WL_O<29> ++ WL_O<28> WL_O<27> WL_O<26> WL_O<25> WL_O<24> WL_O<23> WL_O<22> WL_O<21> ++ WL_O<20> WL_O<19> WL_O<18> WL_O<17> WL_O<16> WL_O<15> WL_O<14> WL_O<13> ++ WL_O<12> WL_O<11> WL_O<10> WL_O<9> WL_O<8> WL_O<7> WL_O<6> WL_O<5> WL_O<4> ++ WL_O<3> WL_O<2> WL_O<1> WL_O<0> VDD VSS +XDEC11<4> ADDR_N_I<7> ADDR_N_I<6> CS_I CS04<3> VDD VSS / ++ RM_IHPSG13_512x16_c2_2P_DEC03 +XDEC11<3> ADDR_N_I<5> ADDR_N_I<4> CS04<3> CS00<15> VDD VSS / ++ RM_IHPSG13_512x16_c2_2P_DEC03 +XDEC11<2> ADDR_N_I<5> ADDR_N_I<4> CS04<2> CS00<11> VDD VSS / ++ RM_IHPSG13_512x16_c2_2P_DEC03 +XDEC11<1> ADDR_N_I<5> ADDR_N_I<4> CS04<1> CS00<7> VDD VSS / ++ RM_IHPSG13_512x16_c2_2P_DEC03 +XDEC11<0> ADDR_N_I<5> ADDR_N_I<4> CS04<0> CS00<3> VDD VSS / ++ RM_IHPSG13_512x16_c2_2P_DEC03 +XSEL<15> ADDR_N_I<3> ADDR_N_I<2> ADDR_N_I<1> ADDR_N_I<0> CS00<15> ECLK_H<15> ++ ECLK_H<16> ECLK_B<15> ECLK_B<16> WL_O<255> WL_O<254> WL_O<253> WL_O<252> ++ WL_O<251> WL_O<250> WL_O<249> WL_O<248> WL_O<247> WL_O<246> WL_O<245> ++ WL_O<244> WL_O<243> WL_O<242> WL_O<241> WL_O<240> VDD VSS / ++ RM_IHPSG13_512x16_c2_2P_DEC04 +XSEL<14> ADDR_N_I<3> ADDR_N_I<2> ADDR_N_I<1> ADDR_N_I<0> CS00<14> ECLK_H<14> ++ ECLK_H<15> ECLK_B<14> ECLK_B<15> WL_O<239> WL_O<238> WL_O<237> WL_O<236> ++ WL_O<235> WL_O<234> WL_O<233> WL_O<232> WL_O<231> WL_O<230> WL_O<229> ++ WL_O<228> WL_O<227> WL_O<226> WL_O<225> WL_O<224> VDD VSS / ++ RM_IHPSG13_512x16_c2_2P_DEC04 +XSEL<13> ADDR_N_I<3> ADDR_N_I<2> ADDR_N_I<1> ADDR_N_I<0> CS00<13> ECLK_H<13> ++ ECLK_H<14> ECLK_B<13> ECLK_B<14> WL_O<223> WL_O<222> WL_O<221> WL_O<220> ++ WL_O<219> WL_O<218> WL_O<217> WL_O<216> WL_O<215> WL_O<214> WL_O<213> ++ WL_O<212> WL_O<211> WL_O<210> WL_O<209> WL_O<208> VDD VSS / ++ RM_IHPSG13_512x16_c2_2P_DEC04 +XSEL<12> ADDR_N_I<3> ADDR_N_I<2> ADDR_N_I<1> ADDR_N_I<0> CS00<12> ECLK_H<12> ++ ECLK_H<13> ECLK_B<12> ECLK_B<13> WL_O<207> WL_O<206> WL_O<205> WL_O<204> ++ WL_O<203> WL_O<202> WL_O<201> WL_O<200> WL_O<199> WL_O<198> WL_O<197> ++ WL_O<196> WL_O<195> WL_O<194> WL_O<193> WL_O<192> VDD VSS / ++ RM_IHPSG13_512x16_c2_2P_DEC04 +XSEL<11> ADDR_N_I<3> ADDR_N_I<2> ADDR_N_I<1> ADDR_N_I<0> CS00<11> ECLK_H<11> ++ ECLK_H<12> ECLK_B<11> ECLK_B<12> WL_O<191> WL_O<190> WL_O<189> WL_O<188> ++ WL_O<187> WL_O<186> WL_O<185> WL_O<184> WL_O<183> WL_O<182> WL_O<181> ++ WL_O<180> WL_O<179> WL_O<178> WL_O<177> WL_O<176> VDD VSS / ++ RM_IHPSG13_512x16_c2_2P_DEC04 +XSEL<10> ADDR_N_I<3> ADDR_N_I<2> ADDR_N_I<1> ADDR_N_I<0> CS00<10> ECLK_H<10> ++ ECLK_H<11> ECLK_B<10> ECLK_B<11> WL_O<175> WL_O<174> WL_O<173> WL_O<172> ++ WL_O<171> WL_O<170> WL_O<169> WL_O<168> WL_O<167> WL_O<166> WL_O<165> ++ WL_O<164> WL_O<163> WL_O<162> WL_O<161> WL_O<160> VDD VSS / ++ RM_IHPSG13_512x16_c2_2P_DEC04 +XSEL<9> ADDR_N_I<3> ADDR_N_I<2> ADDR_N_I<1> ADDR_N_I<0> CS00<9> ECLK_H<9> ++ ECLK_H<10> ECLK_B<9> ECLK_B<10> WL_O<159> WL_O<158> WL_O<157> WL_O<156> ++ WL_O<155> WL_O<154> WL_O<153> WL_O<152> WL_O<151> WL_O<150> WL_O<149> ++ WL_O<148> WL_O<147> WL_O<146> WL_O<145> WL_O<144> VDD VSS / ++ RM_IHPSG13_512x16_c2_2P_DEC04 +XSEL<8> ADDR_N_I<3> ADDR_N_I<2> ADDR_N_I<1> ADDR_N_I<0> CS00<8> ECLK_H<8> ++ ECLK_H<9> ECLK_B<8> ECLK_B<9> WL_O<143> WL_O<142> WL_O<141> WL_O<140> ++ WL_O<139> WL_O<138> WL_O<137> WL_O<136> WL_O<135> WL_O<134> WL_O<133> ++ WL_O<132> WL_O<131> WL_O<130> WL_O<129> WL_O<128> VDD VSS / ++ RM_IHPSG13_512x16_c2_2P_DEC04 +XSEL<7> ADDR_N_I<3> ADDR_N_I<2> ADDR_N_I<1> ADDR_N_I<0> CS00<7> ECLK_H<7> ++ ECLK_H<8> ECLK_B<7> ECLK_B<8> WL_O<127> WL_O<126> WL_O<125> WL_O<124> ++ WL_O<123> WL_O<122> WL_O<121> WL_O<120> WL_O<119> WL_O<118> WL_O<117> ++ WL_O<116> WL_O<115> WL_O<114> WL_O<113> WL_O<112> VDD VSS / ++ RM_IHPSG13_512x16_c2_2P_DEC04 +XSEL<6> ADDR_N_I<3> ADDR_N_I<2> ADDR_N_I<1> ADDR_N_I<0> CS00<6> ECLK_H<6> ++ ECLK_H<7> ECLK_B<6> ECLK_B<7> WL_O<111> WL_O<110> WL_O<109> WL_O<108> ++ WL_O<107> WL_O<106> WL_O<105> WL_O<104> WL_O<103> WL_O<102> WL_O<101> ++ WL_O<100> WL_O<99> WL_O<98> WL_O<97> WL_O<96> VDD VSS / ++ RM_IHPSG13_512x16_c2_2P_DEC04 +XSEL<5> ADDR_N_I<3> ADDR_N_I<2> ADDR_N_I<1> ADDR_N_I<0> CS00<5> ECLK_H<5> ++ ECLK_H<6> ECLK_B<5> ECLK_B<6> WL_O<95> WL_O<94> WL_O<93> WL_O<92> WL_O<91> ++ WL_O<90> WL_O<89> WL_O<88> WL_O<87> WL_O<86> WL_O<85> WL_O<84> WL_O<83> ++ WL_O<82> WL_O<81> WL_O<80> VDD VSS / RM_IHPSG13_512x16_c2_2P_DEC04 +XSEL<4> ADDR_N_I<3> ADDR_N_I<2> ADDR_N_I<1> ADDR_N_I<0> CS00<4> ECLK_H<4> ++ ECLK_H<5> ECLK_B<4> ECLK_B<5> WL_O<79> WL_O<78> WL_O<77> WL_O<76> WL_O<75> ++ WL_O<74> WL_O<73> WL_O<72> WL_O<71> WL_O<70> WL_O<69> WL_O<68> WL_O<67> ++ WL_O<66> WL_O<65> WL_O<64> VDD VSS / RM_IHPSG13_512x16_c2_2P_DEC04 +XSEL<3> ADDR_N_I<3> ADDR_N_I<2> ADDR_N_I<1> ADDR_N_I<0> CS00<3> ECLK_H<3> ++ ECLK_H<4> ECLK_B<3> ECLK_B<4> WL_O<63> WL_O<62> WL_O<61> WL_O<60> WL_O<59> ++ WL_O<58> WL_O<57> WL_O<56> WL_O<55> WL_O<54> WL_O<53> WL_O<52> WL_O<51> ++ WL_O<50> WL_O<49> WL_O<48> VDD VSS / RM_IHPSG13_512x16_c2_2P_DEC04 +XSEL<2> ADDR_N_I<3> ADDR_N_I<2> ADDR_N_I<1> ADDR_N_I<0> CS00<2> ECLK_H<2> ++ ECLK_H<3> ECLK_B<2> ECLK_B<3> WL_O<47> WL_O<46> WL_O<45> WL_O<44> WL_O<43> ++ WL_O<42> WL_O<41> WL_O<40> WL_O<39> WL_O<38> WL_O<37> WL_O<36> WL_O<35> ++ WL_O<34> WL_O<33> WL_O<32> VDD VSS / RM_IHPSG13_512x16_c2_2P_DEC04 +XSEL<1> ADDR_N_I<3> ADDR_N_I<2> ADDR_N_I<1> ADDR_N_I<0> CS00<1> ECLK_H<1> ++ ECLK_H<2> ECLK_B<1> ECLK_B<2> WL_O<31> WL_O<30> WL_O<29> WL_O<28> WL_O<27> ++ WL_O<26> WL_O<25> WL_O<24> WL_O<23> WL_O<22> WL_O<21> WL_O<20> WL_O<19> ++ WL_O<18> WL_O<17> WL_O<16> VDD VSS / RM_IHPSG13_512x16_c2_2P_DEC04 +XSEL<0> ADDR_N_I<3> ADDR_N_I<2> ADDR_N_I<1> ADDR_N_I<0> CS00<0> ECLK_I ++ ECLK_H<1> ECLK_B<0> ECLK_B<1> WL_O<15> WL_O<14> WL_O<13> WL_O<12> WL_O<11> ++ WL_O<10> WL_O<9> WL_O<8> WL_O<7> WL_O<6> WL_O<5> WL_O<4> WL_O<3> WL_O<2> ++ WL_O<1> WL_O<0> VDD VSS / RM_IHPSG13_512x16_c2_2P_DEC04 +XDEC10<4> ADDR_N_I<7> ADDR_N_I<6> CS_I CS04<2> VDD VSS / ++ RM_IHPSG13_512x16_c2_2P_DEC02 +XDEC10<3> ADDR_N_I<5> ADDR_N_I<4> CS04<3> CS00<14> VDD VSS / ++ RM_IHPSG13_512x16_c2_2P_DEC02 +XDEC10<2> ADDR_N_I<5> ADDR_N_I<4> CS04<2> CS00<10> VDD VSS / ++ RM_IHPSG13_512x16_c2_2P_DEC02 +XDEC10<1> ADDR_N_I<5> ADDR_N_I<4> CS04<1> CS00<6> VDD VSS / ++ RM_IHPSG13_512x16_c2_2P_DEC02 +XDEC10<0> ADDR_N_I<5> ADDR_N_I<4> CS04<0> CS00<2> VDD VSS / ++ RM_IHPSG13_512x16_c2_2P_DEC02 +XL2<132> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<131> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<130> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<129> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<128> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<127> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<126> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<125> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<124> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<123> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<122> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<121> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<120> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<119> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<118> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<117> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<116> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<115> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<114> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<113> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<112> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<111> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<110> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<109> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<108> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<107> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<106> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<105> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<104> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<103> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<102> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<101> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<100> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<99> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<98> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<97> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<96> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<95> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<94> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<93> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<92> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<91> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<90> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<89> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<88> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<87> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<86> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<85> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<84> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<83> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<82> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<81> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<80> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<79> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<78> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<77> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<76> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<75> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<74> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<73> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<72> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<71> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<70> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<69> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<68> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<67> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<66> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<65> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<64> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<63> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<62> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<61> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<60> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<59> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<58> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<57> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<56> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<55> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<54> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<53> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<52> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<51> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<50> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<49> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<48> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<47> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<46> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<45> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<44> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<43> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<42> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<41> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<40> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<39> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<38> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<37> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<36> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<35> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<34> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<33> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<32> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<31> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<30> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<29> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<28> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<27> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<26> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<25> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<24> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<23> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<22> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<21> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<20> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<19> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<18> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<17> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<16> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<15> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<14> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<13> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<12> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<11> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<10> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<9> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<8> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<7> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<6> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<5> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<4> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<3> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<2> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<1> VDD VSS / RSC_IHPSG13_FILLCAP8 +XDEC00<4> ADDR_N_I<7> ADDR_N_I<6> CS_I CS04<0> VDD VSS / ++ RM_IHPSG13_512x16_c2_2P_DEC00 +XDEC00<3> ADDR_N_I<5> ADDR_N_I<4> CS04<3> CS00<12> VDD VSS / ++ RM_IHPSG13_512x16_c2_2P_DEC00 +XDEC00<2> ADDR_N_I<5> ADDR_N_I<4> CS04<2> CS00<8> VDD VSS / ++ RM_IHPSG13_512x16_c2_2P_DEC00 +XDEC00<1> ADDR_N_I<5> ADDR_N_I<4> CS04<1> CS00<4> VDD VSS / ++ RM_IHPSG13_512x16_c2_2P_DEC00 +XDEC00<0> ADDR_N_I<5> ADDR_N_I<4> CS04<0> CS00<0> VDD VSS / ++ RM_IHPSG13_512x16_c2_2P_DEC00 +XDEC01<4> ADDR_N_I<7> ADDR_N_I<6> CS_I CS04<1> VDD VSS / ++ RM_IHPSG13_512x16_c2_2P_DEC01 +XDEC01<3> ADDR_N_I<5> ADDR_N_I<4> CS04<3> CS00<13> VDD VSS / ++ RM_IHPSG13_512x16_c2_2P_DEC01 +XDEC01<2> ADDR_N_I<5> ADDR_N_I<4> CS04<2> CS00<9> VDD VSS / ++ RM_IHPSG13_512x16_c2_2P_DEC01 +XDEC01<1> ADDR_N_I<5> ADDR_N_I<4> CS04<1> CS00<5> VDD VSS / ++ RM_IHPSG13_512x16_c2_2P_DEC01 +XDEC01<0> ADDR_N_I<5> ADDR_N_I<4> CS04<0> CS00<1> VDD VSS / ++ RM_IHPSG13_512x16_c2_2P_DEC01 +.ENDS +.SUBCKT RM_IHPSG13_512x16_c2_2P_ROWREG8 ACLK_N_I ADDR_I<7> ADDR_I<6> ADDR_I<5> ADDR_I<4> ++ ADDR_I<3> ADDR_I<2> ADDR_I<1> ADDR_I<0> ADDR_N_O<7> ADDR_N_O<6> ADDR_N_O<5> ++ ADDR_N_O<4> ADDR_N_O<3> ADDR_N_O<2> ADDR_N_O<1> ADDR_N_O<0> BIST_ADDR_I<7> ++ BIST_ADDR_I<6> BIST_ADDR_I<5> BIST_ADDR_I<4> BIST_ADDR_I<3> BIST_ADDR_I<2> ++ BIST_ADDR_I<1> BIST_ADDR_I<0> BIST_EN_I VDD VSS +XINV<7> q_int<7> qn_int<7> VDD VSS / RSC_IHPSG13_CINVX2 +XINV<6> q_int<6> qn_int<6> VDD VSS / RSC_IHPSG13_CINVX2 +XINV<5> q_int<5> qn_int<5> VDD VSS / RSC_IHPSG13_CINVX2 +XINV<4> q_int<4> qn_int<4> VDD VSS / RSC_IHPSG13_CINVX2 +XINV<3> q_int<3> qn_int<3> VDD VSS / RSC_IHPSG13_CINVX2 +XINV<2> q_int<2> qn_int<2> VDD VSS / RSC_IHPSG13_CINVX2 +XINV<1> q_int<1> qn_int<1> VDD VSS / RSC_IHPSG13_CINVX2 +XINV<0> q_int<0> qn_int<0> VDD VSS / RSC_IHPSG13_CINVX2 +XDRV<7> qn_int<7> ADDR_N_O<7> VDD VSS / RSC_IHPSG13_CINVX8 +XDRV<6> qn_int<6> ADDR_N_O<6> VDD VSS / RSC_IHPSG13_CINVX8 +XDRV<5> qn_int<5> ADDR_N_O<5> VDD VSS / RSC_IHPSG13_CINVX8 +XDRV<4> qn_int<4> ADDR_N_O<4> VDD VSS / RSC_IHPSG13_CINVX8 +XDRV<3> qn_int<3> ADDR_N_O<3> VDD VSS / RSC_IHPSG13_CINVX8 +XDRV<2> qn_int<2> ADDR_N_O<2> VDD VSS / RSC_IHPSG13_CINVX8 +XDRV<1> qn_int<1> ADDR_N_O<1> VDD VSS / RSC_IHPSG13_CINVX8 +XDRV<0> qn_int<0> ADDR_N_O<0> VDD VSS / RSC_IHPSG13_CINVX8 +XDFF<7> BIST_EN_I BIST_ADDR_I<7> ACLK_N_I ADDR_I<7> q_int<7> net2<0> VDD ++ VSS / RSC_IHPSG13_DFNQMX2IX1 +XDFF<6> BIST_EN_I BIST_ADDR_I<6> ACLK_N_I ADDR_I<6> q_int<6> net2<1> VDD ++ VSS / RSC_IHPSG13_DFNQMX2IX1 +XDFF<5> BIST_EN_I BIST_ADDR_I<5> ACLK_N_I ADDR_I<5> q_int<5> net2<2> VDD ++ VSS / RSC_IHPSG13_DFNQMX2IX1 +XDFF<4> BIST_EN_I BIST_ADDR_I<4> ACLK_N_I ADDR_I<4> q_int<4> net2<3> VDD ++ VSS / RSC_IHPSG13_DFNQMX2IX1 +XDFF<3> BIST_EN_I BIST_ADDR_I<3> ACLK_N_I ADDR_I<3> q_int<3> net2<4> VDD ++ VSS / RSC_IHPSG13_DFNQMX2IX1 +XDFF<2> BIST_EN_I BIST_ADDR_I<2> ACLK_N_I ADDR_I<2> q_int<2> net2<5> VDD ++ VSS / RSC_IHPSG13_DFNQMX2IX1 +XDFF<1> BIST_EN_I BIST_ADDR_I<1> ACLK_N_I ADDR_I<1> q_int<1> net2<6> VDD ++ VSS / RSC_IHPSG13_DFNQMX2IX1 +XDFF<0> BIST_EN_I BIST_ADDR_I<0> ACLK_N_I ADDR_I<0> q_int<0> net2<7> VDD ++ VSS / RSC_IHPSG13_DFNQMX2IX1 +XI11<4> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI11<3> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI11<2> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI11<1> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI10 VDD VSS / RSC_IHPSG13_FILLCAP4 +.ENDS +.SUBCKT RM_IHPSG13_512x16_c2_2P_COLDEC4 ACLK_N ADDR<3> ADDR<2> ADDR<1> ADDR<0> ++ ADDR_COL<1> ADDR_COL<0> ADDR_DEC<7> ADDR_DEC<6> ADDR_DEC<5> ADDR_DEC<4> ++ ADDR_DEC<3> ADDR_DEC<2> ADDR_DEC<1> ADDR_DEC<0> BIST_ADDR<3> BIST_ADDR<2> ++ BIST_ADDR<1> BIST_ADDR<0> BIST_EN_I VDD VSS +XI1<7> PADR<0> PADR<1> PADR<2> addr_n<7> VDD VSS / RSC_IHPSG13_NAND3X2 +XI1<6> NADR<0> PADR<1> PADR<2> addr_n<6> VDD VSS / RSC_IHPSG13_NAND3X2 +XI1<5> PADR<0> NADR<1> PADR<2> addr_n<5> VDD VSS / RSC_IHPSG13_NAND3X2 +XI1<4> NADR<0> NADR<1> PADR<2> addr_n<4> VDD VSS / RSC_IHPSG13_NAND3X2 +XI1<3> PADR<0> PADR<1> NADR<2> addr_n<3> VDD VSS / RSC_IHPSG13_NAND3X2 +XI1<2> NADR<0> PADR<1> NADR<2> addr_n<2> VDD VSS / RSC_IHPSG13_NAND3X2 +XI1<1> PADR<0> NADR<1> NADR<2> addr_n<1> VDD VSS / RSC_IHPSG13_NAND3X2 +XI1<0> NADR<0> NADR<1> NADR<2> addr_n<0> VDD VSS / RSC_IHPSG13_NAND3X2 +XDFF<3> BIST_EN_I BIST_ADDR<3> ACLK_N ADDR<3> addr_int net12<0> VDD ++ VSS / RSC_IHPSG13_DFNQMX2IX1 +XDFF<2> BIST_EN_I BIST_ADDR<2> ACLK_N ADDR<2> padr_int<2> net12<1> VDD ++ VSS / RSC_IHPSG13_DFNQMX2IX1 +XDFF<1> BIST_EN_I BIST_ADDR<1> ACLK_N ADDR<1> padr_int<1> net12<2> VDD ++ VSS / RSC_IHPSG13_DFNQMX2IX1 +XDFF<0> BIST_EN_I BIST_ADDR<0> ACLK_N ADDR<0> padr_int<0> net12<3> VDD ++ VSS / RSC_IHPSG13_DFNQMX2IX1 +XI17<4> VDD VSS / RSC_IHPSG13_FILLCAP4 +XI17<3> VDD VSS / RSC_IHPSG13_FILLCAP4 +XI17<2> VDD VSS / RSC_IHPSG13_FILLCAP4 +XI17<1> VDD VSS / RSC_IHPSG13_FILLCAP4 +XI13<2> NADR<2> PADR<2> VDD VSS / RSC_IHPSG13_INVX2 +XI13<1> NADR<1> PADR<1> VDD VSS / RSC_IHPSG13_INVX2 +XI13<0> NADR<0> PADR<0> VDD VSS / RSC_IHPSG13_INVX2 +XI2<7> addr_n<7> ADDR_DEC<7> VDD VSS / RSC_IHPSG13_INVX2 +XI2<6> addr_n<6> ADDR_DEC<6> VDD VSS / RSC_IHPSG13_INVX2 +XI2<5> addr_n<5> ADDR_DEC<5> VDD VSS / RSC_IHPSG13_INVX2 +XI2<4> addr_n<4> ADDR_DEC<4> VDD VSS / RSC_IHPSG13_INVX2 +XI2<3> addr_n<3> ADDR_DEC<3> VDD VSS / RSC_IHPSG13_INVX2 +XI2<2> addr_n<2> ADDR_DEC<2> VDD VSS / RSC_IHPSG13_INVX2 +XI2<1> addr_n<1> ADDR_DEC<1> VDD VSS / RSC_IHPSG13_INVX2 +XI2<0> addr_n<0> ADDR_DEC<0> VDD VSS / RSC_IHPSG13_INVX2 +XI3<2> padr_int<2> NADR<2> VDD VSS / RSC_IHPSG13_INVX2 +XI3<1> padr_int<1> NADR<1> VDD VSS / RSC_IHPSG13_INVX2 +XI3<0> padr_int<0> NADR<0> VDD VSS / RSC_IHPSG13_INVX2 +XI14 addr_int ADDR_COL<0> VDD VSS / RSC_IHPSG13_CBUFX2 +XI16<8> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI16<7> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI16<6> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI16<5> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI16<4> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI16<3> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI16<2> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI16<1> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI15 ADDR_COL<1> VDD VSS / RSC_IHPSG13_TIEL +.ENDS +.SUBCKT RM_IHPSG13_512x16_c2_2P_COLCTRL4 A_ADDR_COL A_ADDR_DEC<7> A_ADDR_DEC<6> ++ A_ADDR_DEC<5> A_ADDR_DEC<4> A_ADDR_DEC<3> A_ADDR_DEC<2> A_ADDR_DEC<1> ++ A_ADDR_DEC<0> A_BIST_BM_I A_BIST_DW_I A_BIST_EN_I A_BLC<15> A_BLC<14> ++ A_BLC<13> A_BLC<12> A_BLC<11> A_BLC<10> A_BLC<9> A_BLC<8> A_BLC<7> A_BLC<6> ++ A_BLC<5> A_BLC<4> A_BLC<3> A_BLC<2> A_BLC<1> A_BLC<0> A_BLT<15> A_BLT<14> ++ A_BLT<13> A_BLT<12> A_BLT<11> A_BLT<10> A_BLT<9> A_BLT<8> A_BLT<7> A_BLT<6> ++ A_BLT<5> A_BLT<4> A_BLT<3> A_BLT<2> A_BLT<1> A_BLT<0> A_BM_I A_DCLK_B_L ++ A_DCLK_B_R A_DCLK_L A_DCLK_R A_DR_O A_DW_I A_RCLK_B_L A_RCLK_B_R A_RCLK_L ++ A_RCLK_R A_TIEH_O A_WCLK_B_L A_WCLK_B_R A_WCLK_L A_WCLK_R B_ADDR_COL ++ B_ADDR_DEC<7> B_ADDR_DEC<6> B_ADDR_DEC<5> B_ADDR_DEC<4> B_ADDR_DEC<3> ++ B_ADDR_DEC<2> B_ADDR_DEC<1> B_ADDR_DEC<0> B_BIST_BM_I B_BIST_DW_I ++ B_BIST_EN_I B_BLC<15> B_BLC<14> B_BLC<13> B_BLC<12> B_BLC<11> B_BLC<10> ++ B_BLC<9> B_BLC<8> B_BLC<7> B_BLC<6> B_BLC<5> B_BLC<4> B_BLC<3> B_BLC<2> ++ B_BLC<1> B_BLC<0> B_BLT<15> B_BLT<14> B_BLT<13> B_BLT<12> B_BLT<11> ++ B_BLT<10> B_BLT<9> B_BLT<8> B_BLT<7> B_BLT<6> B_BLT<5> B_BLT<4> B_BLT<3> ++ B_BLT<2> B_BLT<1> B_BLT<0> B_BM_I B_DCLK_B_L B_DCLK_B_R B_DCLK_L B_DCLK_R ++ B_DR_O B_DW_I B_RCLK_B_L B_RCLK_B_R B_RCLK_L B_RCLK_R B_TIEH_O B_WCLK_B_L ++ B_WCLK_B_R B_WCLK_L B_WCLK_R VDD VSS +XB_I80 B_RCLK_B_L B_WCLK_B_L net041 VDD VSS / RSC_IHPSG13_AND2X2 +XA_I80 A_RCLK_B_L A_WCLK_B_L net21 VDD VSS / RSC_IHPSG13_AND2X2 +XB_I76 B_DI_N B_DO_WRITE_P B_WR_ZERO VDD VSS / RSC_IHPSG13_AND2X4 +XB_I75 B_DI_R B_DO_WRITE_P B_WR_ONE VDD VSS / RSC_IHPSG13_AND2X4 +XA_I76 A_DI_N A_DO_WRITE_P A_WR_ZERO VDD VSS / RSC_IHPSG13_AND2X4 +XA_I75 A_DI_R A_DO_WRITE_P A_WR_ONE VDD VSS / RSC_IHPSG13_AND2X4 +XI_FILL4<26> VDD VSS / RSC_IHPSG13_FILLCAP4 +XI_FILL4<25> VDD VSS / RSC_IHPSG13_FILLCAP4 +XI_FILL4<24> VDD VSS / RSC_IHPSG13_FILLCAP4 +XI_FILL4<23> VDD VSS / RSC_IHPSG13_FILLCAP4 +XI_FILL4<22> VDD VSS / RSC_IHPSG13_FILLCAP4 +XI_FILL4<21> VDD VSS / RSC_IHPSG13_FILLCAP4 +XI_FILL4<20> VDD VSS / RSC_IHPSG13_FILLCAP4 +XI_FILL4<19> VDD VSS / RSC_IHPSG13_FILLCAP4 +XI_FILL4<18> VDD VSS / RSC_IHPSG13_FILLCAP4 +XI_FILL4<17> VDD VSS / RSC_IHPSG13_FILLCAP4 +XI_FILL4<16> VDD VSS / RSC_IHPSG13_FILLCAP4 +XI_FILL4<15> VDD VSS / RSC_IHPSG13_FILLCAP4 +XI_FILL4<14> VDD VSS / RSC_IHPSG13_FILLCAP4 +XI_FILL4<13> VDD VSS / RSC_IHPSG13_FILLCAP4 +XI_FILL4<12> VDD VSS / RSC_IHPSG13_FILLCAP4 +XI_FILL4<11> VDD VSS / RSC_IHPSG13_FILLCAP4 +XI_FILL4<10> VDD VSS / RSC_IHPSG13_FILLCAP4 +XI_FILL4<9> VDD VSS / RSC_IHPSG13_FILLCAP4 +XI_FILL4<8> VDD VSS / RSC_IHPSG13_FILLCAP4 +XI_FILL4<7> VDD VSS / RSC_IHPSG13_FILLCAP4 +XI_FILL4<6> VDD VSS / RSC_IHPSG13_FILLCAP4 +XI_FILL4<5> VDD VSS / RSC_IHPSG13_FILLCAP4 +XI_FILL4<4> VDD VSS / RSC_IHPSG13_FILLCAP4 +XI_FILL4<3> VDD VSS / RSC_IHPSG13_FILLCAP4 +XI_FILL4<2> VDD VSS / RSC_IHPSG13_FILLCAP4 +XI_FILL4<1> VDD VSS / RSC_IHPSG13_FILLCAP4 +XB_I69 B_DCLK_L B_DCLK_B_L VDD VSS / RSC_IHPSG13_CINVX4 +XB_I50 B_WCLK_L B_WCLK_B_L VDD VSS / RSC_IHPSG13_CINVX4 +XB_EBUF B_RCLK_L B_RCLK_B_L VDD VSS / RSC_IHPSG13_CINVX4 +XB_INV<1> B_N0 B_P0 VDD VSS / RSC_IHPSG13_CINVX4 +XB_INV<0> B_ADDR_COL B_N0 VDD VSS / RSC_IHPSG13_CINVX4 +XA_I69 A_DCLK_L A_DCLK_B_L VDD VSS / RSC_IHPSG13_CINVX4 +XA_I50 A_WCLK_L A_WCLK_B_L VDD VSS / RSC_IHPSG13_CINVX4 +XA_EBUF A_RCLK_L A_RCLK_B_L VDD VSS / RSC_IHPSG13_CINVX4 +XA_INV<1> A_N0 A_P0 VDD VSS / RSC_IHPSG13_CINVX4 +XA_INV<0> A_ADDR_COL A_N0 VDD VSS / RSC_IHPSG13_CINVX4 +XB_I81<1> net041 B_PRE_N VDD VSS / RSC_IHPSG13_CINVX4_WN +XB_I81<0> net041 B_PRE_N VDD VSS / RSC_IHPSG13_CINVX4_WN +XA_I81<1> net21 A_PRE_N VDD VSS / RSC_IHPSG13_CINVX4_WN +XA_I81<0> net21 A_PRE_N VDD VSS / RSC_IHPSG13_CINVX4_WN +XA_R2 A_RCLK_L A_RCLK_R / RSC_IHPSG13_MET3RES +XA_I87 A_WCLK_L A_WCLK_R / RSC_IHPSG13_MET3RES +XA_I88 A_DCLK_L A_DCLK_R / RSC_IHPSG13_MET3RES +XA_I89 A_DCLK_B_L A_DCLK_B_R / RSC_IHPSG13_MET3RES +XA_I90 A_WCLK_B_L A_WCLK_B_R / RSC_IHPSG13_MET3RES +XA_I91 A_RCLK_B_L A_RCLK_B_R / RSC_IHPSG13_MET3RES +XB_R2 B_RCLK_L B_RCLK_R / RSC_IHPSG13_MET3RES +XB_I87 B_WCLK_L B_WCLK_R / RSC_IHPSG13_MET3RES +XB_I88 B_DCLK_L B_DCLK_R / RSC_IHPSG13_MET3RES +XB_I89 B_DCLK_B_L B_DCLK_B_R / RSC_IHPSG13_MET3RES +XB_I90 B_WCLK_B_L B_WCLK_B_R / RSC_IHPSG13_MET3RES +XB_I91 B_RCLK_B_L B_RCLK_B_R / RSC_IHPSG13_MET3RES +XA_ISENSE A_SAE A_BLC_SEL A_BLT_SEL net19 net20 VDD VSS / ++ RSC_IHPSG13_DFPQD_MSAFFX2 +XB_ISENSE B_SAE B_BLC_SEL B_BLT_SEL net037 net038 VDD VSS / ++ RSC_IHPSG13_DFPQD_MSAFFX2 +XAB_BLMUX<3> A_BLC<15> A_BLC<14> A_BLC<13> A_BLC<12> A_BLC_SEL A_BLT<15> ++ A_BLT<14> A_BLT<13> A_BLT<12> A_BLT_SEL A_PRE_N A_SEL_P<15> A_SEL_P<14> ++ A_SEL_P<13> A_SEL_P<12> A_WR_ONE A_WR_ZERO B_BLC<15> B_BLC<14> B_BLC<13> ++ B_BLC<12> B_BLC_SEL B_BLT<15> B_BLT<14> B_BLT<13> B_BLT<12> B_BLT_SEL ++ B_PRE_N B_SEL_P<15> B_SEL_P<14> B_SEL_P<13> B_SEL_P<12> B_WR_ONE B_WR_ZERO ++ VDD VSS / RM_IHPSG13_512x16_c2_2P_BLDRV +XAB_BLMUX<2> A_BLC<11> A_BLC<10> A_BLC<9> A_BLC<8> A_BLC_SEL A_BLT<11> ++ A_BLT<10> A_BLT<9> A_BLT<8> A_BLT_SEL A_PRE_N A_SEL_P<11> A_SEL_P<10> ++ A_SEL_P<9> A_SEL_P<8> A_WR_ONE A_WR_ZERO B_BLC<11> B_BLC<10> B_BLC<9> ++ B_BLC<8> B_BLC_SEL B_BLT<11> B_BLT<10> B_BLT<9> B_BLT<8> B_BLT_SEL B_PRE_N ++ B_SEL_P<11> B_SEL_P<10> B_SEL_P<9> B_SEL_P<8> B_WR_ONE B_WR_ZERO VDD ++ VSS / RM_IHPSG13_512x16_c2_2P_BLDRV +XAB_BLMUX<1> A_BLC<7> A_BLC<6> A_BLC<5> A_BLC<4> A_BLC_SEL A_BLT<7> A_BLT<6> ++ A_BLT<5> A_BLT<4> A_BLT_SEL A_PRE_N A_SEL_P<7> A_SEL_P<6> A_SEL_P<5> ++ A_SEL_P<4> A_WR_ONE A_WR_ZERO B_BLC<7> B_BLC<6> B_BLC<5> B_BLC<4> B_BLC_SEL ++ B_BLT<7> B_BLT<6> B_BLT<5> B_BLT<4> B_BLT_SEL B_PRE_N B_SEL_P<7> B_SEL_P<6> ++ B_SEL_P<5> B_SEL_P<4> B_WR_ONE B_WR_ZERO VDD VSS / ++ RM_IHPSG13_512x16_c2_2P_BLDRV +XAB_BLMUX<0> A_BLC<3> A_BLC<2> A_BLC<1> A_BLC<0> A_BLC_SEL A_BLT<3> A_BLT<2> ++ A_BLT<1> A_BLT<0> A_BLT_SEL A_PRE_N A_SEL_P<3> A_SEL_P<2> A_SEL_P<1> ++ A_SEL_P<0> A_WR_ONE A_WR_ZERO B_BLC<3> B_BLC<2> B_BLC<1> B_BLC<0> B_BLC_SEL ++ B_BLT<3> B_BLT<2> B_BLT<1> B_BLT<0> B_BLT_SEL B_PRE_N B_SEL_P<3> B_SEL_P<2> ++ B_SEL_P<1> B_SEL_P<0> B_WR_ONE B_WR_ZERO VDD VSS / ++ RM_IHPSG13_512x16_c2_2P_BLDRV +XA_I51 net19 A_DR_O VDD VSS / RSC_IHPSG13_INVX4 +XB_I51 net037 B_DR_O VDD VSS / RSC_IHPSG13_INVX4 +XA_I78 A_RCLK_B_L A_SAE VDD VSS / RSC_IHPSG13_CBUFX2 +XB_I78 B_RCLK_B_L B_SAE VDD VSS / RSC_IHPSG13_CBUFX2 +XA_DREG A_BIST_EN_I A_BIST_DW_I A_DCLK_B_L A_DW_I A_DI_R net22 VDD VSS ++ / RSC_IHPSG13_DFNQMX2IX1 +XB_DREG B_BIST_EN_I B_BIST_DW_I B_DCLK_B_L B_DW_I B_DI_R net046 VDD ++ VSS / RSC_IHPSG13_DFNQMX2IX1 +XB_BREG B_BIST_EN_I B_BIST_BM_I B_DCLK_B_L B_BM_I B_BM_R net045 VDD ++ VSS / RSC_IHPSG13_DFNQMX2IX1 +XA_BREG A_BIST_EN_I A_BIST_BM_I A_DCLK_B_L A_BM_I A_BM_R net24 VDD VSS ++ / RSC_IHPSG13_DFNQMX2IX1 +XA_DEC3INV<15> net23<0> A_SEL_P<15> VDD VSS / RSC_IHPSG13_INVX2 +XA_DEC3INV<14> net23<1> A_SEL_P<14> VDD VSS / RSC_IHPSG13_INVX2 +XA_DEC3INV<13> net23<2> A_SEL_P<13> VDD VSS / RSC_IHPSG13_INVX2 +XA_DEC3INV<12> net23<3> A_SEL_P<12> VDD VSS / RSC_IHPSG13_INVX2 +XA_DEC3INV<11> net23<4> A_SEL_P<11> VDD VSS / RSC_IHPSG13_INVX2 +XA_DEC3INV<10> net23<5> A_SEL_P<10> VDD VSS / RSC_IHPSG13_INVX2 +XA_DEC3INV<9> net23<6> A_SEL_P<9> VDD VSS / RSC_IHPSG13_INVX2 +XA_DEC3INV<8> net23<7> A_SEL_P<8> VDD VSS / RSC_IHPSG13_INVX2 +XA_DEC3INV<7> net23<8> A_SEL_P<7> VDD VSS / RSC_IHPSG13_INVX2 +XA_DEC3INV<6> net23<9> A_SEL_P<6> VDD VSS / RSC_IHPSG13_INVX2 +XA_DEC3INV<5> net23<10> A_SEL_P<5> VDD VSS / RSC_IHPSG13_INVX2 +XA_DEC3INV<4> net23<11> A_SEL_P<4> VDD VSS / RSC_IHPSG13_INVX2 +XA_DEC3INV<3> net23<12> A_SEL_P<3> VDD VSS / RSC_IHPSG13_INVX2 +XA_DEC3INV<2> net23<13> A_SEL_P<2> VDD VSS / RSC_IHPSG13_INVX2 +XA_DEC3INV<1> net23<14> A_SEL_P<1> VDD VSS / RSC_IHPSG13_INVX2 +XA_DEC3INV<0> net23<15> A_SEL_P<0> VDD VSS / RSC_IHPSG13_INVX2 +XA_I83 A_BM_R A_BM_N VDD VSS / RSC_IHPSG13_INVX2 +XA_I49 A_DI_R A_DI_N VDD VSS / RSC_IHPSG13_INVX2 +XB_DEC3INV<15> net044<0> B_SEL_P<15> VDD VSS / RSC_IHPSG13_INVX2 +XB_DEC3INV<14> net044<1> B_SEL_P<14> VDD VSS / RSC_IHPSG13_INVX2 +XB_DEC3INV<13> net044<2> B_SEL_P<13> VDD VSS / RSC_IHPSG13_INVX2 +XB_DEC3INV<12> net044<3> B_SEL_P<12> VDD VSS / RSC_IHPSG13_INVX2 +XB_DEC3INV<11> net044<4> B_SEL_P<11> VDD VSS / RSC_IHPSG13_INVX2 +XB_DEC3INV<10> net044<5> B_SEL_P<10> VDD VSS / RSC_IHPSG13_INVX2 +XB_DEC3INV<9> net044<6> B_SEL_P<9> VDD VSS / RSC_IHPSG13_INVX2 +XB_DEC3INV<8> net044<7> B_SEL_P<8> VDD VSS / RSC_IHPSG13_INVX2 +XB_DEC3INV<7> net044<8> B_SEL_P<7> VDD VSS / RSC_IHPSG13_INVX2 +XB_DEC3INV<6> net044<9> B_SEL_P<6> VDD VSS / RSC_IHPSG13_INVX2 +XB_DEC3INV<5> net044<10> B_SEL_P<5> VDD VSS / RSC_IHPSG13_INVX2 +XB_DEC3INV<4> net044<11> B_SEL_P<4> VDD VSS / RSC_IHPSG13_INVX2 +XB_DEC3INV<3> net044<12> B_SEL_P<3> VDD VSS / RSC_IHPSG13_INVX2 +XB_DEC3INV<2> net044<13> B_SEL_P<2> VDD VSS / RSC_IHPSG13_INVX2 +XB_DEC3INV<1> net044<14> B_SEL_P<1> VDD VSS / RSC_IHPSG13_INVX2 +XB_DEC3INV<0> net044<15> B_SEL_P<0> VDD VSS / RSC_IHPSG13_INVX2 +XB_I83 B_BM_R B_BM_N VDD VSS / RSC_IHPSG13_INVX2 +XB_I49 B_DI_R B_DI_N VDD VSS / RSC_IHPSG13_INVX2 +XI_FILL8<20> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI_FILL8<19> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI_FILL8<18> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI_FILL8<17> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI_FILL8<16> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI_FILL8<15> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI_FILL8<14> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI_FILL8<13> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI_FILL8<12> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI_FILL8<11> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI_FILL8<10> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI_FILL8<9> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI_FILL8<8> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI_FILL8<7> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI_FILL8<6> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI_FILL8<5> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI_FILL8<4> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI_FILL8<3> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI_FILL8<2> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI_FILL8<1> VDD VSS / RSC_IHPSG13_FILLCAP8 +XA_I44 A_BM_N A_WCLK_B_L A_DO_WRITE_P VDD VSS / RSC_IHPSG13_NOR2X2 +XB_I44 B_BM_N B_WCLK_B_L B_DO_WRITE_P VDD VSS / RSC_IHPSG13_NOR2X2 +XA_DEC3<15> A_P0 A_ADDR_DEC<7> net23<0> VDD VSS / RSC_IHPSG13_NAND2X2 +XA_DEC3<14> A_P0 A_ADDR_DEC<6> net23<1> VDD VSS / RSC_IHPSG13_NAND2X2 +XA_DEC3<13> A_P0 A_ADDR_DEC<5> net23<2> VDD VSS / RSC_IHPSG13_NAND2X2 +XA_DEC3<12> A_P0 A_ADDR_DEC<4> net23<3> VDD VSS / RSC_IHPSG13_NAND2X2 +XA_DEC3<11> A_P0 A_ADDR_DEC<3> net23<4> VDD VSS / RSC_IHPSG13_NAND2X2 +XA_DEC3<10> A_P0 A_ADDR_DEC<2> net23<5> VDD VSS / RSC_IHPSG13_NAND2X2 +XA_DEC3<9> A_P0 A_ADDR_DEC<1> net23<6> VDD VSS / RSC_IHPSG13_NAND2X2 +XA_DEC3<8> A_P0 A_ADDR_DEC<0> net23<7> VDD VSS / RSC_IHPSG13_NAND2X2 +XA_DEC3<7> A_N0 A_ADDR_DEC<7> net23<8> VDD VSS / RSC_IHPSG13_NAND2X2 +XA_DEC3<6> A_N0 A_ADDR_DEC<6> net23<9> VDD VSS / RSC_IHPSG13_NAND2X2 +XA_DEC3<5> A_N0 A_ADDR_DEC<5> net23<10> VDD VSS / RSC_IHPSG13_NAND2X2 +XA_DEC3<4> A_N0 A_ADDR_DEC<4> net23<11> VDD VSS / RSC_IHPSG13_NAND2X2 +XA_DEC3<3> A_N0 A_ADDR_DEC<3> net23<12> VDD VSS / RSC_IHPSG13_NAND2X2 +XA_DEC3<2> A_N0 A_ADDR_DEC<2> net23<13> VDD VSS / RSC_IHPSG13_NAND2X2 +XA_DEC3<1> A_N0 A_ADDR_DEC<1> net23<14> VDD VSS / RSC_IHPSG13_NAND2X2 +XA_DEC3<0> A_N0 A_ADDR_DEC<0> net23<15> VDD VSS / RSC_IHPSG13_NAND2X2 +XB_DEC3<15> B_P0 B_ADDR_DEC<7> net044<0> VDD VSS / RSC_IHPSG13_NAND2X2 +XB_DEC3<14> B_P0 B_ADDR_DEC<6> net044<1> VDD VSS / RSC_IHPSG13_NAND2X2 +XB_DEC3<13> B_P0 B_ADDR_DEC<5> net044<2> VDD VSS / RSC_IHPSG13_NAND2X2 +XB_DEC3<12> B_P0 B_ADDR_DEC<4> net044<3> VDD VSS / RSC_IHPSG13_NAND2X2 +XB_DEC3<11> B_P0 B_ADDR_DEC<3> net044<4> VDD VSS / RSC_IHPSG13_NAND2X2 +XB_DEC3<10> B_P0 B_ADDR_DEC<2> net044<5> VDD VSS / RSC_IHPSG13_NAND2X2 +XB_DEC3<9> B_P0 B_ADDR_DEC<1> net044<6> VDD VSS / RSC_IHPSG13_NAND2X2 +XB_DEC3<8> B_P0 B_ADDR_DEC<0> net044<7> VDD VSS / RSC_IHPSG13_NAND2X2 +XB_DEC3<7> B_N0 B_ADDR_DEC<7> net044<8> VDD VSS / RSC_IHPSG13_NAND2X2 +XB_DEC3<6> B_N0 B_ADDR_DEC<6> net044<9> VDD VSS / RSC_IHPSG13_NAND2X2 +XB_DEC3<5> B_N0 B_ADDR_DEC<5> net044<10> VDD VSS / RSC_IHPSG13_NAND2X2 +XB_DEC3<4> B_N0 B_ADDR_DEC<4> net044<11> VDD VSS / RSC_IHPSG13_NAND2X2 +XB_DEC3<3> B_N0 B_ADDR_DEC<3> net044<12> VDD VSS / RSC_IHPSG13_NAND2X2 +XB_DEC3<2> B_N0 B_ADDR_DEC<2> net044<13> VDD VSS / RSC_IHPSG13_NAND2X2 +XB_DEC3<1> B_N0 B_ADDR_DEC<1> net044<14> VDD VSS / RSC_IHPSG13_NAND2X2 +XB_DEC3<0> B_N0 B_ADDR_DEC<0> net044<15> VDD VSS / RSC_IHPSG13_NAND2X2 +XB_BM_TIEH B_TIEH_O VDD VSS / RSC_IHPSG13_TIEH +XA_BM_TIEH A_TIEH_O VDD VSS / RSC_IHPSG13_TIEH +.ENDS + + +.SUBCKT RM_IHPSG13_512x16_c2_2P_ROWDEC5 ADDR_N_I<4> ADDR_N_I<3> ADDR_N_I<2> ADDR_N_I<1> ++ ADDR_N_I<0> CS_I ECLK_I WL_O<31> WL_O<30> WL_O<29> WL_O<28> WL_O<27> ++ WL_O<26> WL_O<25> WL_O<24> WL_O<23> WL_O<22> WL_O<21> WL_O<20> WL_O<19> ++ WL_O<18> WL_O<17> WL_O<16> WL_O<15> WL_O<14> WL_O<13> WL_O<12> WL_O<11> ++ WL_O<10> WL_O<9> WL_O<8> WL_O<7> WL_O<6> WL_O<5> WL_O<4> WL_O<3> WL_O<2> ++ WL_O<1> WL_O<0> VDD VSS +XDEC00 ADDR_N_I<5> ADDR_N_I<4> CS_I CS00<0> VDD VSS / ++ RM_IHPSG13_512x16_c2_2P_DEC00 +XSEL<1> ADDR_N_I<3> ADDR_N_I<2> ADDR_N_I<1> ADDR_N_I<0> CS00<1> ECLK_H<1> ++ ECLK_H<2> ECLK_B<1> ECLK_B<2> WL_O<31> WL_O<30> WL_O<29> WL_O<28> WL_O<27> ++ WL_O<26> WL_O<25> WL_O<24> WL_O<23> WL_O<22> WL_O<21> WL_O<20> WL_O<19> ++ WL_O<18> WL_O<17> WL_O<16> VDD VSS / RM_IHPSG13_512x16_c2_2P_DEC04 +XSEL<0> ADDR_N_I<3> ADDR_N_I<2> ADDR_N_I<1> ADDR_N_I<0> CS00<0> ECLK_I ++ ECLK_H<1> ECLK_B<0> ECLK_B<1> WL_O<15> WL_O<14> WL_O<13> WL_O<12> WL_O<11> ++ WL_O<10> WL_O<9> WL_O<8> WL_O<7> WL_O<6> WL_O<5> WL_O<4> WL_O<3> WL_O<2> ++ WL_O<1> WL_O<0> VDD VSS / RM_IHPSG13_512x16_c2_2P_DEC04 +XDEC01 ADDR_N_I<5> ADDR_N_I<4> CS_I CS00<1> VDD VSS / ++ RM_IHPSG13_512x16_c2_2P_DEC01 +XL2<18> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<17> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<16> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<15> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<14> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<13> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<12> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<11> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<10> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<9> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<8> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<7> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<6> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<5> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<4> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<3> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<2> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<1> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI0 ADDR_N_I<5> VDD VSS / RSC_IHPSG13_TIEL +.ENDS +.SUBCKT RM_IHPSG13_512x16_c2_2P_ROWREG5 ACLK_N_I ADDR_I<4> ADDR_I<3> ADDR_I<2> ADDR_I<1> ++ ADDR_I<0> ADDR_N_O<4> ADDR_N_O<3> ADDR_N_O<2> ADDR_N_O<1> ADDR_N_O<0> ++ BIST_ADDR_I<4> BIST_ADDR_I<3> BIST_ADDR_I<2> BIST_ADDR_I<1> BIST_ADDR_I<0> ++ BIST_EN_I VDD VSS +XINV<4> q_int<4> qn_int<4> VDD VSS / RSC_IHPSG13_CINVX2 +XINV<3> q_int<3> qn_int<3> VDD VSS / RSC_IHPSG13_CINVX2 +XINV<2> q_int<2> qn_int<2> VDD VSS / RSC_IHPSG13_CINVX2 +XINV<1> q_int<1> qn_int<1> VDD VSS / RSC_IHPSG13_CINVX2 +XINV<0> q_int<0> qn_int<0> VDD VSS / RSC_IHPSG13_CINVX2 +XDRV<4> qn_int<4> ADDR_N_O<4> VDD VSS / RSC_IHPSG13_CINVX8 +XDRV<3> qn_int<3> ADDR_N_O<3> VDD VSS / RSC_IHPSG13_CINVX8 +XDRV<2> qn_int<2> ADDR_N_O<2> VDD VSS / RSC_IHPSG13_CINVX8 +XDRV<1> qn_int<1> ADDR_N_O<1> VDD VSS / RSC_IHPSG13_CINVX8 +XDRV<0> qn_int<0> ADDR_N_O<0> VDD VSS / RSC_IHPSG13_CINVX8 +XDFF<4> BIST_EN_I BIST_ADDR_I<4> ACLK_N_I ADDR_I<4> q_int<4> net2<0> VDD ++ VSS / RSC_IHPSG13_DFNQMX2IX1 +XDFF<3> BIST_EN_I BIST_ADDR_I<3> ACLK_N_I ADDR_I<3> q_int<3> net2<1> VDD ++ VSS / RSC_IHPSG13_DFNQMX2IX1 +XDFF<2> BIST_EN_I BIST_ADDR_I<2> ACLK_N_I ADDR_I<2> q_int<2> net2<2> VDD ++ VSS / RSC_IHPSG13_DFNQMX2IX1 +XDFF<1> BIST_EN_I BIST_ADDR_I<1> ACLK_N_I ADDR_I<1> q_int<1> net2<3> VDD ++ VSS / RSC_IHPSG13_DFNQMX2IX1 +XDFF<0> BIST_EN_I BIST_ADDR_I<0> ACLK_N_I ADDR_I<0> q_int<0> net2<4> VDD ++ VSS / RSC_IHPSG13_DFNQMX2IX1 +XI11<16> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI11<15> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI11<14> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI11<13> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI11<12> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI11<11> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI11<10> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI11<9> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI11<8> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI11<7> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI11<6> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI11<5> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI11<4> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI11<3> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI11<2> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI11<1> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI12<3> VDD VSS / RSC_IHPSG13_FILLCAP4 +XI12<2> VDD VSS / RSC_IHPSG13_FILLCAP4 +XI12<1> VDD VSS / RSC_IHPSG13_FILLCAP4 +XI12<0> VDD VSS / RSC_IHPSG13_FILLCAP4 +.ENDS + + +.SUBCKT RM_IHPSG13_512x16_c2_2P_COLDEC3 ACLK_N ADDR<2> ADDR<1> ADDR<0> ADDR_COL<1> ++ ADDR_COL<0> ADDR_DEC<7> ADDR_DEC<6> ADDR_DEC<5> ADDR_DEC<4> ADDR_DEC<3> ++ ADDR_DEC<2> ADDR_DEC<1> ADDR_DEC<0> BIST_ADDR<2> BIST_ADDR<1> BIST_ADDR<0> ++ BIST_EN_I VDD VSS +XI1<7> PADR<0> PADR<1> PADR<2> addr_n<7> VDD VSS / RSC_IHPSG13_NAND3X2 +XI1<6> NADR<0> PADR<1> PADR<2> addr_n<6> VDD VSS / RSC_IHPSG13_NAND3X2 +XI1<5> PADR<0> NADR<1> PADR<2> addr_n<5> VDD VSS / RSC_IHPSG13_NAND3X2 +XI1<4> NADR<0> NADR<1> PADR<2> addr_n<4> VDD VSS / RSC_IHPSG13_NAND3X2 +XI1<3> PADR<0> PADR<1> NADR<2> addr_n<3> VDD VSS / RSC_IHPSG13_NAND3X2 +XI1<2> NADR<0> PADR<1> NADR<2> addr_n<2> VDD VSS / RSC_IHPSG13_NAND3X2 +XI1<1> PADR<0> NADR<1> NADR<2> addr_n<1> VDD VSS / RSC_IHPSG13_NAND3X2 +XI1<0> NADR<0> NADR<1> NADR<2> addr_n<0> VDD VSS / RSC_IHPSG13_NAND3X2 +XDFF<2> BIST_EN_I BIST_ADDR<2> ACLK_N ADDR<2> padr_int<2> net13<0> VDD ++ VSS / RSC_IHPSG13_DFNQMX2IX1 +XDFF<1> BIST_EN_I BIST_ADDR<1> ACLK_N ADDR<1> padr_int<1> net13<1> VDD ++ VSS / RSC_IHPSG13_DFNQMX2IX1 +XDFF<0> BIST_EN_I BIST_ADDR<0> ACLK_N ADDR<0> padr_int<0> net13<2> VDD ++ VSS / RSC_IHPSG13_DFNQMX2IX1 +XI15<1> ADDR_COL<1> VDD VSS / RSC_IHPSG13_TIEL +XI15<0> ADDR_COL<0> VDD VSS / RSC_IHPSG13_TIEL +XI13<2> NADR<2> PADR<2> VDD VSS / RSC_IHPSG13_INVX2 +XI13<1> NADR<1> PADR<1> VDD VSS / RSC_IHPSG13_INVX2 +XI13<0> NADR<0> PADR<0> VDD VSS / RSC_IHPSG13_INVX2 +XI3<2> padr_int<2> NADR<2> VDD VSS / RSC_IHPSG13_INVX2 +XI3<1> padr_int<1> NADR<1> VDD VSS / RSC_IHPSG13_INVX2 +XI3<0> padr_int<0> NADR<0> VDD VSS / RSC_IHPSG13_INVX2 +XI2<7> addr_n<7> ADDR_DEC<7> VDD VSS / RSC_IHPSG13_INVX2 +XI2<6> addr_n<6> ADDR_DEC<6> VDD VSS / RSC_IHPSG13_INVX2 +XI2<5> addr_n<5> ADDR_DEC<5> VDD VSS / RSC_IHPSG13_INVX2 +XI2<4> addr_n<4> ADDR_DEC<4> VDD VSS / RSC_IHPSG13_INVX2 +XI2<3> addr_n<3> ADDR_DEC<3> VDD VSS / RSC_IHPSG13_INVX2 +XI2<2> addr_n<2> ADDR_DEC<2> VDD VSS / RSC_IHPSG13_INVX2 +XI2<1> addr_n<1> ADDR_DEC<1> VDD VSS / RSC_IHPSG13_INVX2 +XI2<0> addr_n<0> ADDR_DEC<0> VDD VSS / RSC_IHPSG13_INVX2 +XI17<4> VDD VSS / RSC_IHPSG13_FILLCAP4 +XI17<3> VDD VSS / RSC_IHPSG13_FILLCAP4 +XI17<2> VDD VSS / RSC_IHPSG13_FILLCAP4 +XI17<1> VDD VSS / RSC_IHPSG13_FILLCAP4 +XI16<11> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI16<10> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI16<9> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI16<8> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI16<7> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI16<6> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI16<5> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI16<4> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI16<3> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI16<2> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI16<1> VDD VSS / RSC_IHPSG13_FILLCAP8 +.ENDS +.SUBCKT RSC_IHPSG13_DFPQD_MSAFFX2P CP DN DP QN QP VDD VSS +XI_AMP CP DN DP QN QP VDD VSS / RSC_IHPSG13_DFPQD_MSAFFX2 +.ENDS +.SUBCKT RM_IHPSG13_512x16_c2_2P_COLCTRL3 A_ADDR_DEC<7> A_ADDR_DEC<6> A_ADDR_DEC<5> ++ A_ADDR_DEC<4> A_ADDR_DEC<3> A_ADDR_DEC<2> A_ADDR_DEC<1> A_ADDR_DEC<0> ++ A_BIST_BM_I A_BIST_DW_I A_BIST_EN_I A_BLC<7> A_BLC<6> A_BLC<5> A_BLC<4> ++ A_BLC<3> A_BLC<2> A_BLC<1> A_BLC<0> A_BLT<7> A_BLT<6> A_BLT<5> A_BLT<4> ++ A_BLT<3> A_BLT<2> A_BLT<1> A_BLT<0> A_BM_I A_DCLK_B_L A_DCLK_B_R A_DCLK_L ++ A_DCLK_R A_DR_O A_DW_I A_RCLK_B_L A_RCLK_B_R A_RCLK_L A_RCLK_R A_TIEH_O ++ A_WCLK_B_L A_WCLK_B_R A_WCLK_L A_WCLK_R B_ADDR_DEC<7> B_ADDR_DEC<6> ++ B_ADDR_DEC<5> B_ADDR_DEC<4> B_ADDR_DEC<3> B_ADDR_DEC<2> B_ADDR_DEC<1> ++ B_ADDR_DEC<0> B_BIST_BM_I B_BIST_DW_I B_BIST_EN_I B_BLC<7> B_BLC<6> B_BLC<5> ++ B_BLC<4> B_BLC<3> B_BLC<2> B_BLC<1> B_BLC<0> B_BLT<7> B_BLT<6> B_BLT<5> ++ B_BLT<4> B_BLT<3> B_BLT<2> B_BLT<1> B_BLT<0> B_BM_I B_DCLK_B_L B_DCLK_B_R ++ B_DCLK_L B_DCLK_R B_DR_O B_DW_I B_RCLK_B_L B_RCLK_B_R B_RCLK_L B_RCLK_R ++ B_TIEH_O B_WCLK_B_L B_WCLK_B_R B_WCLK_L B_WCLK_R VDD VSS +XB_DREG B_BIST_EN_I B_BIST_DW_I B_DCLK_B_L B_DW_I B_DI_R net044 VDD ++ VSS / RSC_IHPSG13_DFNQMX2IX1 +XB_BREG B_BIST_EN_I B_BIST_BM_I B_DCLK_B_L B_BM_I B_BM_R net043 VDD ++ VSS / RSC_IHPSG13_DFNQMX2IX1 +XA_DREG A_BIST_EN_I A_BIST_DW_I A_DCLK_B_L A_DW_I A_DI_R net22 VDD VSS ++ / RSC_IHPSG13_DFNQMX2IX1 +XA_BREG A_BIST_EN_I A_BIST_BM_I A_DCLK_B_L A_BM_I A_BM_R net23 VDD VSS ++ / RSC_IHPSG13_DFNQMX2IX1 +XI_FILL8<11> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI_FILL8<10> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI_FILL8<9> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI_FILL8<8> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI_FILL8<7> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI_FILL8<6> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI_FILL8<5> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI_FILL8<4> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI_FILL8<3> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI_FILL8<2> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI_FILL8<1> VDD VSS / RSC_IHPSG13_FILLCAP8 +XB_I51 net037 B_DR_O VDD VSS / RSC_IHPSG13_INVX4 +XA_I51 net19 A_DR_O VDD VSS / RSC_IHPSG13_INVX4 +XB_I44 B_BM_N B_WCLK_B_L B_DO_WRITE_P VDD VSS / RSC_IHPSG13_NOR2X2 +XA_I44 A_BM_N A_WCLK_B_L A_DO_WRITE_P VDD VSS / RSC_IHPSG13_NOR2X2 +XB_BM_TIEH B_TIEH_O VDD VSS / RSC_IHPSG13_TIEH +XA_BM_TIEH A_TIEH_O VDD VSS / RSC_IHPSG13_TIEH +XB_ISENSE B_SAE B_BLC_SEL B_BLT_SEL net037 net038 VDD VSS / ++ RSC_IHPSG13_DFPQD_MSAFFX2P +XA_ISENSE A_SAE A_BLC_SEL A_BLT_SEL net19 net20 VDD VSS / ++ RSC_IHPSG13_DFPQD_MSAFFX2P +XB_I49 B_DI_R B_DI_N VDD VSS / RSC_IHPSG13_INVX2 +XB_I83 B_BM_R B_BM_N VDD VSS / RSC_IHPSG13_INVX2 +XA_I49 A_DI_R A_DI_N VDD VSS / RSC_IHPSG13_INVX2 +XA_I83 A_BM_R A_BM_N VDD VSS / RSC_IHPSG13_INVX2 +XB_I69 B_DCLK_L B_DCLK_B_L VDD VSS / RSC_IHPSG13_CINVX2 +XB_I50 B_WCLK_L B_WCLK_B_L VDD VSS / RSC_IHPSG13_CINVX2 +XB_EBUF B_RCLK_L B_RCLK_B_L VDD VSS / RSC_IHPSG13_CINVX2 +XA_I69 A_DCLK_L A_DCLK_B_L VDD VSS / RSC_IHPSG13_CINVX2 +XA_I50 A_WCLK_L A_WCLK_B_L VDD VSS / RSC_IHPSG13_CINVX2 +XA_EBUF A_RCLK_L A_RCLK_B_L VDD VSS / RSC_IHPSG13_CINVX2 +XAB_BLMUX<1> A_BLC<7> A_BLC<6> A_BLC<5> A_BLC<4> A_BLC_SEL A_BLT<7> A_BLT<6> ++ A_BLT<5> A_BLT<4> A_BLT_SEL A_PRE_N A_ADDR_DEC<7> A_ADDR_DEC<6> ++ A_ADDR_DEC<5> A_ADDR_DEC<4> A_WR_ONE A_WR_ZERO B_BLC<7> B_BLC<6> B_BLC<5> ++ B_BLC<4> B_BLC_SEL B_BLT<7> B_BLT<6> B_BLT<5> B_BLT<4> B_BLT_SEL B_PRE_N ++ B_ADDR_DEC<7> B_ADDR_DEC<6> B_ADDR_DEC<5> B_ADDR_DEC<4> B_WR_ONE B_WR_ZERO ++ VDD VSS / RM_IHPSG13_512x16_c2_2P_BLDRV +XAB_BLMUX<0> A_BLC<3> A_BLC<2> A_BLC<1> A_BLC<0> A_BLC_SEL A_BLT<3> A_BLT<2> ++ A_BLT<1> A_BLT<0> A_BLT_SEL A_PRE_N A_ADDR_DEC<3> A_ADDR_DEC<2> ++ A_ADDR_DEC<1> A_ADDR_DEC<0> A_WR_ONE A_WR_ZERO B_BLC<3> B_BLC<2> B_BLC<1> ++ B_BLC<0> B_BLC_SEL B_BLT<3> B_BLT<2> B_BLT<1> B_BLT<0> B_BLT_SEL B_PRE_N ++ B_ADDR_DEC<3> B_ADDR_DEC<2> B_ADDR_DEC<1> B_ADDR_DEC<0> B_WR_ONE B_WR_ZERO ++ VDD VSS / RM_IHPSG13_512x16_c2_2P_BLDRV +XB_I78 B_RCLK_B_L B_SAE VDD VSS / RSC_IHPSG13_CBUFX2 +XA_I78 A_RCLK_B_L A_SAE VDD VSS / RSC_IHPSG13_CBUFX2 +XB_I88 B_DCLK_L B_DCLK_R / RSC_IHPSG13_MET3RES +XB_I87 B_WCLK_L B_WCLK_R / RSC_IHPSG13_MET3RES +XB_R2 B_RCLK_L B_RCLK_R / RSC_IHPSG13_MET3RES +XB_I91 B_RCLK_B_L B_RCLK_B_R / RSC_IHPSG13_MET3RES +XB_I90 B_WCLK_B_L B_WCLK_B_R / RSC_IHPSG13_MET3RES +XB_I89 B_DCLK_B_L B_DCLK_B_R / RSC_IHPSG13_MET3RES +XA_I88 A_DCLK_L A_DCLK_R / RSC_IHPSG13_MET3RES +XA_I87 A_WCLK_L A_WCLK_R / RSC_IHPSG13_MET3RES +XA_R2 A_RCLK_L A_RCLK_R / RSC_IHPSG13_MET3RES +XA_I91 A_RCLK_B_L A_RCLK_B_R / RSC_IHPSG13_MET3RES +XA_I90 A_WCLK_B_L A_WCLK_B_R / RSC_IHPSG13_MET3RES +XA_I89 A_DCLK_B_L A_DCLK_B_R / RSC_IHPSG13_MET3RES +XB_I80 B_WCLK_B_L B_RCLK_B_L net041 VDD VSS / RSC_IHPSG13_AND2X2 +XB_I76 B_DO_WRITE_P B_DI_N B_WR_ZERO VDD VSS / RSC_IHPSG13_AND2X2 +XB_I75 B_DO_WRITE_P B_DI_R B_WR_ONE VDD VSS / RSC_IHPSG13_AND2X2 +XA_I80 A_WCLK_B_L A_RCLK_B_L net21 VDD VSS / RSC_IHPSG13_AND2X2 +XA_I76 A_DI_N A_DO_WRITE_P A_WR_ZERO VDD VSS / RSC_IHPSG13_AND2X2 +XA_I75 A_DI_R A_DO_WRITE_P A_WR_ONE VDD VSS / RSC_IHPSG13_AND2X2 +XB_I81 net041 B_PRE_N VDD VSS / RSC_IHPSG13_CINVX4_WN +XA_I81 net21 A_PRE_N VDD VSS / RSC_IHPSG13_CINVX4_WN +XI_FILL4<10> VDD VSS / RSC_IHPSG13_FILLCAP4 +XI_FILL4<9> VDD VSS / RSC_IHPSG13_FILLCAP4 +XI_FILL4<8> VDD VSS / RSC_IHPSG13_FILLCAP4 +XI_FILL4<7> VDD VSS / RSC_IHPSG13_FILLCAP4 +XI_FILL4<6> VDD VSS / RSC_IHPSG13_FILLCAP4 +XI_FILL4<5> VDD VSS / RSC_IHPSG13_FILLCAP4 +XI_FILL4<4> VDD VSS / RSC_IHPSG13_FILLCAP4 +XI_FILL4<3> VDD VSS / RSC_IHPSG13_FILLCAP4 +XI_FILL4<2> VDD VSS / RSC_IHPSG13_FILLCAP4 +XI_FILL4<1> VDD VSS / RSC_IHPSG13_FILLCAP4 +.ENDS + +.SUBCKT RM_IHPSG13_512x16_c2_2P_ROWDEC6 ADDR_N_I<5> ADDR_N_I<4> ADDR_N_I<3> ADDR_N_I<2> ++ ADDR_N_I<1> ADDR_N_I<0> CS_I ECLK_I WL_O<63> WL_O<62> WL_O<61> WL_O<60> ++ WL_O<59> WL_O<58> WL_O<57> WL_O<56> WL_O<55> WL_O<54> WL_O<53> WL_O<52> ++ WL_O<51> WL_O<50> WL_O<49> WL_O<48> WL_O<47> WL_O<46> WL_O<45> WL_O<44> ++ WL_O<43> WL_O<42> WL_O<41> WL_O<40> WL_O<39> WL_O<38> WL_O<37> WL_O<36> ++ WL_O<35> WL_O<34> WL_O<33> WL_O<32> WL_O<31> WL_O<30> WL_O<29> WL_O<28> ++ WL_O<27> WL_O<26> WL_O<25> WL_O<24> WL_O<23> WL_O<22> WL_O<21> WL_O<20> ++ WL_O<19> WL_O<18> WL_O<17> WL_O<16> WL_O<15> WL_O<14> WL_O<13> WL_O<12> ++ WL_O<11> WL_O<10> WL_O<9> WL_O<8> WL_O<7> WL_O<6> WL_O<5> WL_O<4> WL_O<3> ++ WL_O<2> WL_O<1> WL_O<0> VDD VSS +XDEC10 ADDR_N_I<5> ADDR_N_I<4> CS_I CS00<2> VDD VSS / ++ RM_IHPSG13_512x16_c2_2P_DEC02 +XDEC00 ADDR_N_I<5> ADDR_N_I<4> CS_I CS00<0> VDD VSS / ++ RM_IHPSG13_512x16_c2_2P_DEC00 +XSEL<3> ADDR_N_I<3> ADDR_N_I<2> ADDR_N_I<1> ADDR_N_I<0> CS00<3> ECLK_H<3> ++ ECLK_H<4> ECLK_B<3> ECLK_B<4> WL_O<63> WL_O<62> WL_O<61> WL_O<60> WL_O<59> ++ WL_O<58> WL_O<57> WL_O<56> WL_O<55> WL_O<54> WL_O<53> WL_O<52> WL_O<51> ++ WL_O<50> WL_O<49> WL_O<48> VDD VSS / RM_IHPSG13_512x16_c2_2P_DEC04 +XSEL<2> ADDR_N_I<3> ADDR_N_I<2> ADDR_N_I<1> ADDR_N_I<0> CS00<2> ECLK_H<2> ++ ECLK_H<3> ECLK_B<2> ECLK_B<3> WL_O<47> WL_O<46> WL_O<45> WL_O<44> WL_O<43> ++ WL_O<42> WL_O<41> WL_O<40> WL_O<39> WL_O<38> WL_O<37> WL_O<36> WL_O<35> ++ WL_O<34> WL_O<33> WL_O<32> VDD VSS / RM_IHPSG13_512x16_c2_2P_DEC04 +XSEL<1> ADDR_N_I<3> ADDR_N_I<2> ADDR_N_I<1> ADDR_N_I<0> CS00<1> ECLK_H<1> ++ ECLK_H<2> ECLK_B<1> ECLK_B<2> WL_O<31> WL_O<30> WL_O<29> WL_O<28> WL_O<27> ++ WL_O<26> WL_O<25> WL_O<24> WL_O<23> WL_O<22> WL_O<21> WL_O<20> WL_O<19> ++ WL_O<18> WL_O<17> WL_O<16> VDD VSS / RM_IHPSG13_512x16_c2_2P_DEC04 +XSEL<0> ADDR_N_I<3> ADDR_N_I<2> ADDR_N_I<1> ADDR_N_I<0> CS00<0> ECLK_I ++ ECLK_H<1> ECLK_B<0> ECLK_B<1> WL_O<15> WL_O<14> WL_O<13> WL_O<12> WL_O<11> ++ WL_O<10> WL_O<9> WL_O<8> WL_O<7> WL_O<6> WL_O<5> WL_O<4> WL_O<3> WL_O<2> ++ WL_O<1> WL_O<0> VDD VSS / RM_IHPSG13_512x16_c2_2P_DEC04 +XDEC11 ADDR_N_I<5> ADDR_N_I<4> CS_I CS00<3> VDD VSS / ++ RM_IHPSG13_512x16_c2_2P_DEC03 +XL2<36> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<35> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<34> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<33> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<32> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<31> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<30> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<29> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<28> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<27> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<26> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<25> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<24> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<23> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<22> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<21> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<20> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<19> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<18> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<17> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<16> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<15> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<14> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<13> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<12> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<11> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<10> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<9> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<8> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<7> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<6> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<5> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<4> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<3> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<2> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<1> VDD VSS / RSC_IHPSG13_FILLCAP8 +XDEC01 ADDR_N_I<5> ADDR_N_I<4> CS_I CS00<1> VDD VSS / ++ RM_IHPSG13_512x16_c2_2P_DEC01 +.ENDS +.SUBCKT RM_IHPSG13_512x16_c2_2P_ROWREG6 ACLK_N_I ADDR_I<5> ADDR_I<4> ADDR_I<3> ADDR_I<2> ++ ADDR_I<1> ADDR_I<0> ADDR_N_O<5> ADDR_N_O<4> ADDR_N_O<3> ADDR_N_O<2> ++ ADDR_N_O<1> ADDR_N_O<0> BIST_ADDR_I<5> BIST_ADDR_I<4> BIST_ADDR_I<3> ++ BIST_ADDR_I<2> BIST_ADDR_I<1> BIST_ADDR_I<0> BIST_EN_I VDD VSS +XINV<5> q_int<5> qn_int<5> VDD VSS / RSC_IHPSG13_CINVX2 +XINV<4> q_int<4> qn_int<4> VDD VSS / RSC_IHPSG13_CINVX2 +XINV<3> q_int<3> qn_int<3> VDD VSS / RSC_IHPSG13_CINVX2 +XINV<2> q_int<2> qn_int<2> VDD VSS / RSC_IHPSG13_CINVX2 +XINV<1> q_int<1> qn_int<1> VDD VSS / RSC_IHPSG13_CINVX2 +XINV<0> q_int<0> qn_int<0> VDD VSS / RSC_IHPSG13_CINVX2 +XDRV<5> qn_int<5> ADDR_N_O<5> VDD VSS / RSC_IHPSG13_CINVX8 +XDRV<4> qn_int<4> ADDR_N_O<4> VDD VSS / RSC_IHPSG13_CINVX8 +XDRV<3> qn_int<3> ADDR_N_O<3> VDD VSS / RSC_IHPSG13_CINVX8 +XDRV<2> qn_int<2> ADDR_N_O<2> VDD VSS / RSC_IHPSG13_CINVX8 +XDRV<1> qn_int<1> ADDR_N_O<1> VDD VSS / RSC_IHPSG13_CINVX8 +XDRV<0> qn_int<0> ADDR_N_O<0> VDD VSS / RSC_IHPSG13_CINVX8 +XDFF<5> BIST_EN_I BIST_ADDR_I<5> ACLK_N_I ADDR_I<5> q_int<5> net2<0> VDD ++ VSS / RSC_IHPSG13_DFNQMX2IX1 +XDFF<4> BIST_EN_I BIST_ADDR_I<4> ACLK_N_I ADDR_I<4> q_int<4> net2<1> VDD ++ VSS / RSC_IHPSG13_DFNQMX2IX1 +XDFF<3> BIST_EN_I BIST_ADDR_I<3> ACLK_N_I ADDR_I<3> q_int<3> net2<2> VDD ++ VSS / RSC_IHPSG13_DFNQMX2IX1 +XDFF<2> BIST_EN_I BIST_ADDR_I<2> ACLK_N_I ADDR_I<2> q_int<2> net2<3> VDD ++ VSS / RSC_IHPSG13_DFNQMX2IX1 +XDFF<1> BIST_EN_I BIST_ADDR_I<1> ACLK_N_I ADDR_I<1> q_int<1> net2<4> VDD ++ VSS / RSC_IHPSG13_DFNQMX2IX1 +XDFF<0> BIST_EN_I BIST_ADDR_I<0> ACLK_N_I ADDR_I<0> q_int<0> net2<5> VDD ++ VSS / RSC_IHPSG13_DFNQMX2IX1 +XI11<12> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI11<11> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI11<10> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI11<9> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI11<8> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI11<7> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI11<6> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI11<5> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI11<4> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI11<3> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI11<2> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI11<1> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI12<2> VDD VSS / RSC_IHPSG13_FILLCAP4 +XI12<1> VDD VSS / RSC_IHPSG13_FILLCAP4 +XI12<0> VDD VSS / RSC_IHPSG13_FILLCAP4 +.ENDS + +.SUBCKT RM_IHPSG13_512x16_c2_2P_COLDRV13X16 ADDR_COL_I<1> ADDR_COL_I<0> ADDR_COL_O<1> ++ ADDR_COL_O<0> ADDR_DEC_I<7> ADDR_DEC_I<6> ADDR_DEC_I<5> ADDR_DEC_I<4> ++ ADDR_DEC_I<3> ADDR_DEC_I<2> ADDR_DEC_I<1> ADDR_DEC_I<0> ADDR_DEC_O<7> ++ ADDR_DEC_O<6> ADDR_DEC_O<5> ADDR_DEC_O<4> ADDR_DEC_O<3> ADDR_DEC_O<2> ++ ADDR_DEC_O<1> ADDR_DEC_O<0> DCLK_I DCLK_O RCLK_I RCLK_O WCLK_I WCLK_O ++ VDD VSS +XI0<7> VDD VSS / RSC_IHPSG13_FILLCAP4 +XI0<6> VDD VSS / RSC_IHPSG13_FILLCAP4 +XI0<5> VDD VSS / RSC_IHPSG13_FILLCAP4 +XI0<4> VDD VSS / RSC_IHPSG13_FILLCAP4 +XI0<3> VDD VSS / RSC_IHPSG13_FILLCAP4 +XI0<2> VDD VSS / RSC_IHPSG13_FILLCAP4 +XI0<1> VDD VSS / RSC_IHPSG13_FILLCAP4 +XWCLK_DRV WCLK_I WCLK_O VDD VSS / RSC_IHPSG13_CBUFX16 +XRCLK_DRV RCLK_I RCLK_O VDD VSS / RSC_IHPSG13_CBUFX16 +XDCLK_DRV DCLK_I DCLK_O VDD VSS / RSC_IHPSG13_CBUFX16 +XADDR_COL_DRV<1> ADDR_COL_I<1> ADDR_COL_O<1> VDD VSS / ++ RSC_IHPSG13_CBUFX16 +XADDR_COL_DRV<0> ADDR_COL_I<0> ADDR_COL_O<0> VDD VSS / ++ RSC_IHPSG13_CBUFX16 +XADDR_DEC_DRV<7> ADDR_DEC_I<7> ADDR_DEC_O<7> VDD VSS / ++ RSC_IHPSG13_CBUFX16 +XADDR_DEC_DRV<6> ADDR_DEC_I<6> ADDR_DEC_O<6> VDD VSS / ++ RSC_IHPSG13_CBUFX16 +XADDR_DEC_DRV<5> ADDR_DEC_I<5> ADDR_DEC_O<5> VDD VSS / ++ RSC_IHPSG13_CBUFX16 +XADDR_DEC_DRV<4> ADDR_DEC_I<4> ADDR_DEC_O<4> VDD VSS / ++ RSC_IHPSG13_CBUFX16 +XADDR_DEC_DRV<3> ADDR_DEC_I<3> ADDR_DEC_O<3> VDD VSS / ++ RSC_IHPSG13_CBUFX16 +XADDR_DEC_DRV<2> ADDR_DEC_I<2> ADDR_DEC_O<2> VDD VSS / ++ RSC_IHPSG13_CBUFX16 +XADDR_DEC_DRV<1> ADDR_DEC_I<1> ADDR_DEC_O<1> VDD VSS / ++ RSC_IHPSG13_CBUFX16 +XADDR_DEC_DRV<0> ADDR_DEC_I<0> ADDR_DEC_O<0> VDD VSS / ++ RSC_IHPSG13_CBUFX16 +XI1<5> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI1<4> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI1<3> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI1<2> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI1<1> VDD VSS / RSC_IHPSG13_FILLCAP8 +.ENDS +.SUBCKT RM_IHPSG13_512x16_c2_2P_WLDRV16X16 A<15> A<14> A<13> A<12> A<11> A<10> A<9> A<8> ++ A<7> A<6> A<5> A<4> A<3> A<2> A<1> A<0> Z<15> Z<14> Z<13> Z<12> Z<11> Z<10> ++ Z<9> Z<8> Z<7> Z<6> Z<5> Z<4> Z<3> Z<2> Z<1> Z<0> VDD VSS +XBUF<15> A<15> Z<15> VDD VSS / RSC_IHPSG13_WLDRVX16 +XBUF<14> A<14> Z<14> VDD VSS / RSC_IHPSG13_WLDRVX16 +XBUF<13> A<13> Z<13> VDD VSS / RSC_IHPSG13_WLDRVX16 +XBUF<12> A<12> Z<12> VDD VSS / RSC_IHPSG13_WLDRVX16 +XBUF<11> A<11> Z<11> VDD VSS / RSC_IHPSG13_WLDRVX16 +XBUF<10> A<10> Z<10> VDD VSS / RSC_IHPSG13_WLDRVX16 +XBUF<9> A<9> Z<9> VDD VSS / RSC_IHPSG13_WLDRVX16 +XBUF<8> A<8> Z<8> VDD VSS / RSC_IHPSG13_WLDRVX16 +XBUF<7> A<7> Z<7> VDD VSS / RSC_IHPSG13_WLDRVX16 +XBUF<6> A<6> Z<6> VDD VSS / RSC_IHPSG13_WLDRVX16 +XBUF<5> A<5> Z<5> VDD VSS / RSC_IHPSG13_WLDRVX16 +XBUF<4> A<4> Z<4> VDD VSS / RSC_IHPSG13_WLDRVX16 +XBUF<3> A<3> Z<3> VDD VSS / RSC_IHPSG13_WLDRVX16 +XBUF<2> A<2> Z<2> VDD VSS / RSC_IHPSG13_WLDRVX16 +XBUF<1> A<1> Z<1> VDD VSS / RSC_IHPSG13_WLDRVX16 +XBUF<0> A<0> Z<0> VDD VSS / RSC_IHPSG13_WLDRVX16 +.ENDS + + +.SUBCKT RM_IHPSG13_512x16_c2_1P_DEC01 ADDR<1> ADDR<0> CS CS_OUT VDD VSS +XDECINV net1 CS_OUT VDD VSS / RSC_IHPSG13_INVX4 +XDEC NADDR<1> ADDR<0> CS net1 VDD VSS / RSC_IHPSG13_NAND3X2 +XI2 VDD VSS / RSC_IHPSG13_FILLCAP4 +XADDRINV ADDR<1> NADDR<1> VDD VSS / RSC_IHPSG13_INVX2 +.ENDS +.SUBCKT RM_IHPSG13_512x16_c2_1P_DEC00 ADDR<1> ADDR<0> CS CS_OUT VDD VSS +XDECINV net1 CS_OUT VDD VSS / RSC_IHPSG13_INVX4 +XDEC NADDR<1> NADDR<0> CS net1 VDD VSS / RSC_IHPSG13_NAND3X2 +XADDRINV<1> ADDR<1> NADDR<1> VDD VSS / RSC_IHPSG13_INVX2 +XADDRINV<0> ADDR<0> NADDR<0> VDD VSS / RSC_IHPSG13_INVX2 +XI1 VDD VSS / RSC_IHPSG13_FILLCAP4 +.ENDS +.SUBCKT RM_IHPSG13_512x16_c2_1P_ROWDEC5 ADDR_N_I<4> ADDR_N_I<3> ADDR_N_I<2> ADDR_N_I<1> ++ ADDR_N_I<0> CS_I ECLK_I WL_O<31> WL_O<30> WL_O<29> WL_O<28> WL_O<27> ++ WL_O<26> WL_O<25> WL_O<24> WL_O<23> WL_O<22> WL_O<21> WL_O<20> WL_O<19> ++ WL_O<18> WL_O<17> WL_O<16> WL_O<15> WL_O<14> WL_O<13> WL_O<12> WL_O<11> ++ WL_O<10> WL_O<9> WL_O<8> WL_O<7> WL_O<6> WL_O<5> WL_O<4> WL_O<3> WL_O<2> ++ WL_O<1> WL_O<0> VDD VSS +XL2<12> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<11> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<10> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<9> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<8> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<7> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<6> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<5> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<4> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<3> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<2> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<1> VDD VSS / RSC_IHPSG13_FILLCAP8 +XDEC01 ADDR_N_I<5> ADDR_N_I<4> CS_I CS00<1> VDD VSS / ++ RM_IHPSG13_512x16_c2_1P_DEC01 +XDEC00 ADDR_N_I<5> ADDR_N_I<4> CS_I CS00<0> VDD VSS / ++ RM_IHPSG13_512x16_c2_1P_DEC00 +XSEL<1> ADDR_N_I<3> ADDR_N_I<2> ADDR_N_I<1> ADDR_N_I<0> CS00<1> ECLK_H<1> ++ ECLK_H<2> ECLK_B<1> ECLK_B<2> WL_O<31> WL_O<30> WL_O<29> WL_O<28> WL_O<27> ++ WL_O<26> WL_O<25> WL_O<24> WL_O<23> WL_O<22> WL_O<21> WL_O<20> WL_O<19> ++ WL_O<18> WL_O<17> WL_O<16> VDD VSS / RM_IHPSG13_512x16_c2_1P_DEC04 +XSEL<0> ADDR_N_I<3> ADDR_N_I<2> ADDR_N_I<1> ADDR_N_I<0> CS00<0> ECLK_I ++ ECLK_H<1> ECLK_B<0> ECLK_B<1> WL_O<15> WL_O<14> WL_O<13> WL_O<12> WL_O<11> ++ WL_O<10> WL_O<9> WL_O<8> WL_O<7> WL_O<6> WL_O<5> WL_O<4> WL_O<3> WL_O<2> ++ WL_O<1> WL_O<0> VDD VSS / RM_IHPSG13_512x16_c2_1P_DEC04 +XI0 ADDR_N_I<5> VDD VSS / RSC_IHPSG13_TIEL +.ENDS +.SUBCKT RM_IHPSG13_512x16_c2_1P_ROWREG5 ACLK_N_I ADDR_I<4> ADDR_I<3> ADDR_I<2> ADDR_I<1> ++ ADDR_I<0> ADDR_N_O<4> ADDR_N_O<3> ADDR_N_O<2> ADDR_N_O<1> ADDR_N_O<0> ++ BIST_ADDR_I<4> BIST_ADDR_I<3> BIST_ADDR_I<2> BIST_ADDR_I<1> BIST_ADDR_I<0> ++ BIST_EN_I VDD VSS +XINV<4> q_int<4> qn_int<4> VDD VSS / RSC_IHPSG13_CINVX2 +XINV<3> q_int<3> qn_int<3> VDD VSS / RSC_IHPSG13_CINVX2 +XINV<2> q_int<2> qn_int<2> VDD VSS / RSC_IHPSG13_CINVX2 +XINV<1> q_int<1> qn_int<1> VDD VSS / RSC_IHPSG13_CINVX2 +XINV<0> q_int<0> qn_int<0> VDD VSS / RSC_IHPSG13_CINVX2 +XDRV<4> qn_int<4> ADDR_N_O<4> VDD VSS / RSC_IHPSG13_CINVX8 +XDRV<3> qn_int<3> ADDR_N_O<3> VDD VSS / RSC_IHPSG13_CINVX8 +XDRV<2> qn_int<2> ADDR_N_O<2> VDD VSS / RSC_IHPSG13_CINVX8 +XDRV<1> qn_int<1> ADDR_N_O<1> VDD VSS / RSC_IHPSG13_CINVX8 +XDRV<0> qn_int<0> ADDR_N_O<0> VDD VSS / RSC_IHPSG13_CINVX8 +XDFF<4> BIST_EN_I BIST_ADDR_I<4> ACLK_N_I ADDR_I<4> q_int<4> net2<0> VDD ++ VSS / RSC_IHPSG13_DFNQMX2IX1 +XDFF<3> BIST_EN_I BIST_ADDR_I<3> ACLK_N_I ADDR_I<3> q_int<3> net2<1> VDD ++ VSS / RSC_IHPSG13_DFNQMX2IX1 +XDFF<2> BIST_EN_I BIST_ADDR_I<2> ACLK_N_I ADDR_I<2> q_int<2> net2<2> VDD ++ VSS / RSC_IHPSG13_DFNQMX2IX1 +XDFF<1> BIST_EN_I BIST_ADDR_I<1> ACLK_N_I ADDR_I<1> q_int<1> net2<3> VDD ++ VSS / RSC_IHPSG13_DFNQMX2IX1 +XDFF<0> BIST_EN_I BIST_ADDR_I<0> ACLK_N_I ADDR_I<0> q_int<0> net2<4> VDD ++ VSS / RSC_IHPSG13_DFNQMX2IX1 +XI11<16> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI11<15> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI11<14> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI11<13> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI11<12> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI11<11> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI11<10> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI11<9> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI11<8> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI11<7> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI11<6> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI11<5> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI11<4> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI11<3> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI11<2> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI11<1> VDD VSS / RSC_IHPSG13_FILLCAP8 +.ENDS + + +.SUBCKT RM_IHPSG13_512x16_c2_1P_COLDEC5 ACLK_N ADDR<4> ADDR<3> ADDR<2> ADDR<1> ADDR<0> ++ ADDR_COL<1> ADDR_COL<0> ADDR_DEC<7> ADDR_DEC<6> ADDR_DEC<5> ADDR_DEC<4> ++ ADDR_DEC<3> ADDR_DEC<2> ADDR_DEC<1> ADDR_DEC<0> BIST_ADDR<4> BIST_ADDR<3> ++ BIST_ADDR<2> BIST_ADDR<1> BIST_ADDR<0> BIST_EN_I VDD VSS +XI17<2> VDD VSS / RSC_IHPSG13_FILLCAP4 +XI17<1> VDD VSS / RSC_IHPSG13_FILLCAP4 +XI13<1> addr_int<1> ADDR_COL<1> VDD VSS / RSC_IHPSG13_CBUFX2 +XI13<0> addr_int<0> ADDR_COL<0> VDD VSS / RSC_IHPSG13_CBUFX2 +XDFF<4> BIST_EN_I BIST_ADDR<4> ACLK_N ADDR<4> addr_int<1> net7<0> VDD ++ VSS / RSC_IHPSG13_DFNQMX2IX1 +XDFF<3> BIST_EN_I BIST_ADDR<3> ACLK_N ADDR<3> addr_int<0> net7<1> VDD ++ VSS / RSC_IHPSG13_DFNQMX2IX1 +XDFF<2> BIST_EN_I BIST_ADDR<2> ACLK_N ADDR<2> padr_int<2> net7<2> VDD ++ VSS / RSC_IHPSG13_DFNQMX2IX1 +XDFF<1> BIST_EN_I BIST_ADDR<1> ACLK_N ADDR<1> padr_int<1> net7<3> VDD ++ VSS / RSC_IHPSG13_DFNQMX2IX1 +XDFF<0> BIST_EN_I BIST_ADDR<0> ACLK_N ADDR<0> padr_int<0> net7<4> VDD ++ VSS / RSC_IHPSG13_DFNQMX2IX1 +XI1<7> PADR<0> PADR<1> PADR<2> addr_n<7> VDD VSS / RSC_IHPSG13_NAND3X2 +XI1<6> NADR<0> PADR<1> PADR<2> addr_n<6> VDD VSS / RSC_IHPSG13_NAND3X2 +XI1<5> PADR<0> NADR<1> PADR<2> addr_n<5> VDD VSS / RSC_IHPSG13_NAND3X2 +XI1<4> NADR<0> NADR<1> PADR<2> addr_n<4> VDD VSS / RSC_IHPSG13_NAND3X2 +XI1<3> PADR<0> PADR<1> NADR<2> addr_n<3> VDD VSS / RSC_IHPSG13_NAND3X2 +XI1<2> NADR<0> PADR<1> NADR<2> addr_n<2> VDD VSS / RSC_IHPSG13_NAND3X2 +XI1<1> PADR<0> NADR<1> NADR<2> addr_n<1> VDD VSS / RSC_IHPSG13_NAND3X2 +XI1<0> NADR<0> NADR<1> NADR<2> addr_n<0> VDD VSS / RSC_IHPSG13_NAND3X2 +XI15<2> NADR<2> PADR<2> VDD VSS / RSC_IHPSG13_INVX2 +XI15<1> NADR<1> PADR<1> VDD VSS / RSC_IHPSG13_INVX2 +XI15<0> NADR<0> PADR<0> VDD VSS / RSC_IHPSG13_INVX2 +XI3<2> padr_int<2> NADR<2> VDD VSS / RSC_IHPSG13_INVX2 +XI3<1> padr_int<1> NADR<1> VDD VSS / RSC_IHPSG13_INVX2 +XI3<0> padr_int<0> NADR<0> VDD VSS / RSC_IHPSG13_INVX2 +XI2<7> addr_n<7> ADDR_DEC<7> VDD VSS / RSC_IHPSG13_INVX2 +XI2<6> addr_n<6> ADDR_DEC<6> VDD VSS / RSC_IHPSG13_INVX2 +XI2<5> addr_n<5> ADDR_DEC<5> VDD VSS / RSC_IHPSG13_INVX2 +XI2<4> addr_n<4> ADDR_DEC<4> VDD VSS / RSC_IHPSG13_INVX2 +XI2<3> addr_n<3> ADDR_DEC<3> VDD VSS / RSC_IHPSG13_INVX2 +XI2<2> addr_n<2> ADDR_DEC<2> VDD VSS / RSC_IHPSG13_INVX2 +XI2<1> addr_n<1> ADDR_DEC<1> VDD VSS / RSC_IHPSG13_INVX2 +XI2<0> addr_n<0> ADDR_DEC<0> VDD VSS / RSC_IHPSG13_INVX2 +.ENDS +.SUBCKT RM_IHPSG13_512x16_c2_1P_COLCTRL5 A_ADDR_COL<1> A_ADDR_COL<0> A_ADDR_DEC<7> ++ A_ADDR_DEC<6> A_ADDR_DEC<5> A_ADDR_DEC<4> A_ADDR_DEC<3> A_ADDR_DEC<2> ++ A_ADDR_DEC<1> A_ADDR_DEC<0> A_BIST_BM_I A_BIST_DW_I A_BIST_EN_I A_BLC<31> ++ A_BLC<30> A_BLC<29> A_BLC<28> A_BLC<27> A_BLC<26> A_BLC<25> A_BLC<24> ++ A_BLC<23> A_BLC<22> A_BLC<21> A_BLC<20> A_BLC<19> A_BLC<18> A_BLC<17> ++ A_BLC<16> A_BLC<15> A_BLC<14> A_BLC<13> A_BLC<12> A_BLC<11> A_BLC<10> ++ A_BLC<9> A_BLC<8> A_BLC<7> A_BLC<6> A_BLC<5> A_BLC<4> A_BLC<3> A_BLC<2> ++ A_BLC<1> A_BLC<0> A_BLT<31> A_BLT<30> A_BLT<29> A_BLT<28> A_BLT<27> ++ A_BLT<26> A_BLT<25> A_BLT<24> A_BLT<23> A_BLT<22> A_BLT<21> A_BLT<20> ++ A_BLT<19> A_BLT<18> A_BLT<17> A_BLT<16> A_BLT<15> A_BLT<14> A_BLT<13> ++ A_BLT<12> A_BLT<11> A_BLT<10> A_BLT<9> A_BLT<8> A_BLT<7> A_BLT<6> A_BLT<5> ++ A_BLT<4> A_BLT<3> A_BLT<2> A_BLT<1> A_BLT<0> A_BM_I A_DCLK_B_L A_DCLK_B_R ++ A_DCLK_L A_DCLK_R A_DR_O A_DW_I A_RCLK_B_L A_RCLK_B_R A_RCLK_L A_RCLK_R ++ A_TIEH_O A_WCLK_B_L A_WCLK_B_R A_WCLK_L A_WCLK_R VDD VSS +XA_I80<1> A_WCLK_B_L A_RCLK_B_L A_W_nor_R<1> VDD VSS / ++ RSC_IHPSG13_AND2X2 +XA_I80<0> A_WCLK_B_L A_RCLK_B_L A_W_nor_R<0> VDD VSS / ++ RSC_IHPSG13_AND2X2 +XA_I44 A_BM_N A_WCLK_B_L A_DO_WRITE_P VDD VSS / RSC_IHPSG13_NOR2X2 +XI80<29> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI80<28> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI80<27> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI80<26> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI80<25> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI80<24> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI80<23> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI80<22> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI80<21> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI80<20> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI80<19> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI80<18> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI80<17> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI80<16> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI80<15> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI80<14> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI80<13> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI80<12> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI80<11> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI80<10> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI80<9> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI80<8> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI80<7> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI80<6> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI80<5> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI80<4> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI80<3> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI80<2> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI80<1> VDD VSS / RSC_IHPSG13_FILLCAP8 +XA_I74<16> VDD VSS / RSC_IHPSG13_FILLCAP8 +XA_I74<15> VDD VSS / RSC_IHPSG13_FILLCAP8 +XA_I74<14> VDD VSS / RSC_IHPSG13_FILLCAP8 +XA_I74<13> VDD VSS / RSC_IHPSG13_FILLCAP8 +XA_I74<12> VDD VSS / RSC_IHPSG13_FILLCAP8 +XA_I74<11> VDD VSS / RSC_IHPSG13_FILLCAP8 +XA_I74<10> VDD VSS / RSC_IHPSG13_FILLCAP8 +XA_I74<9> VDD VSS / RSC_IHPSG13_FILLCAP8 +XA_I74<8> VDD VSS / RSC_IHPSG13_FILLCAP8 +XA_I74<7> VDD VSS / RSC_IHPSG13_FILLCAP8 +XA_I74<6> VDD VSS / RSC_IHPSG13_FILLCAP8 +XA_I74<5> VDD VSS / RSC_IHPSG13_FILLCAP8 +XA_I74<4> VDD VSS / RSC_IHPSG13_FILLCAP8 +XA_I74<3> VDD VSS / RSC_IHPSG13_FILLCAP8 +XA_I74<2> VDD VSS / RSC_IHPSG13_FILLCAP8 +XA_I74<1> VDD VSS / RSC_IHPSG13_FILLCAP8 +XA_INV<6> A_N1<1> A_P1<1> VDD VSS / RSC_IHPSG13_CINVX4 +XA_INV<5> A_N0<1> A_P0<1> VDD VSS / RSC_IHPSG13_CINVX4 +XA_INV<4> A_N0<0> A_P0<0> VDD VSS / RSC_IHPSG13_CINVX4 +XA_INV<3> A_ADDR_COL<1> A_N1<1> VDD VSS / RSC_IHPSG13_CINVX4 +XA_INV<2> A_ADDR_COL<1> A_N1<0> VDD VSS / RSC_IHPSG13_CINVX4 +XA_INV<1> A_ADDR_COL<0> A_N0<1> VDD VSS / RSC_IHPSG13_CINVX4 +XA_INV<0> A_ADDR_COL<0> A_N0<0> VDD VSS / RSC_IHPSG13_CINVX4 +XA_I81<3> A_W_nor_R<1> A_PRE_N VDD VSS / RSC_IHPSG13_CINVX4_WN +XA_I81<2> A_W_nor_R<1> A_PRE_N VDD VSS / RSC_IHPSG13_CINVX4_WN +XA_I81<1> A_W_nor_R<0> A_PRE_N VDD VSS / RSC_IHPSG13_CINVX4_WN +XA_I81<0> A_W_nor_R<0> A_PRE_N VDD VSS / RSC_IHPSG13_CINVX4_WN +XA_BLTMUX<31> A_BLC<31> A_BLC_SEL A_BLT<31> A_BLT_SEL A_PRE_N A_SEL_P<31> ++ A_WR_ONE A_WR_ZERO VDD VSS / RM_IHPSG13_512x16_c2_1P_BLDRV +XA_BLTMUX<30> A_BLC<30> A_BLC_SEL A_BLT<30> A_BLT_SEL A_PRE_N A_SEL_P<30> ++ A_WR_ONE A_WR_ZERO VDD VSS / RM_IHPSG13_512x16_c2_1P_BLDRV +XA_BLTMUX<29> A_BLC<29> A_BLC_SEL A_BLT<29> A_BLT_SEL A_PRE_N A_SEL_P<29> ++ A_WR_ONE A_WR_ZERO VDD VSS / RM_IHPSG13_512x16_c2_1P_BLDRV +XA_BLTMUX<28> A_BLC<28> A_BLC_SEL A_BLT<28> A_BLT_SEL A_PRE_N A_SEL_P<28> ++ A_WR_ONE A_WR_ZERO VDD VSS / RM_IHPSG13_512x16_c2_1P_BLDRV +XA_BLTMUX<27> A_BLC<27> A_BLC_SEL A_BLT<27> A_BLT_SEL A_PRE_N A_SEL_P<27> ++ A_WR_ONE A_WR_ZERO VDD VSS / RM_IHPSG13_512x16_c2_1P_BLDRV +XA_BLTMUX<26> A_BLC<26> A_BLC_SEL A_BLT<26> A_BLT_SEL A_PRE_N A_SEL_P<26> ++ A_WR_ONE A_WR_ZERO VDD VSS / RM_IHPSG13_512x16_c2_1P_BLDRV +XA_BLTMUX<25> A_BLC<25> A_BLC_SEL A_BLT<25> A_BLT_SEL A_PRE_N A_SEL_P<25> ++ A_WR_ONE A_WR_ZERO VDD VSS / RM_IHPSG13_512x16_c2_1P_BLDRV +XA_BLTMUX<24> A_BLC<24> A_BLC_SEL A_BLT<24> A_BLT_SEL A_PRE_N A_SEL_P<24> ++ A_WR_ONE A_WR_ZERO VDD VSS / RM_IHPSG13_512x16_c2_1P_BLDRV +XA_BLTMUX<23> A_BLC<23> A_BLC_SEL A_BLT<23> A_BLT_SEL A_PRE_N A_SEL_P<23> ++ A_WR_ONE A_WR_ZERO VDD VSS / RM_IHPSG13_512x16_c2_1P_BLDRV +XA_BLTMUX<22> A_BLC<22> A_BLC_SEL A_BLT<22> A_BLT_SEL A_PRE_N A_SEL_P<22> ++ A_WR_ONE A_WR_ZERO VDD VSS / RM_IHPSG13_512x16_c2_1P_BLDRV +XA_BLTMUX<21> A_BLC<21> A_BLC_SEL A_BLT<21> A_BLT_SEL A_PRE_N A_SEL_P<21> ++ A_WR_ONE A_WR_ZERO VDD VSS / RM_IHPSG13_512x16_c2_1P_BLDRV +XA_BLTMUX<20> A_BLC<20> A_BLC_SEL A_BLT<20> A_BLT_SEL A_PRE_N A_SEL_P<20> ++ A_WR_ONE A_WR_ZERO VDD VSS / RM_IHPSG13_512x16_c2_1P_BLDRV +XA_BLTMUX<19> A_BLC<19> A_BLC_SEL A_BLT<19> A_BLT_SEL A_PRE_N A_SEL_P<19> ++ A_WR_ONE A_WR_ZERO VDD VSS / RM_IHPSG13_512x16_c2_1P_BLDRV +XA_BLTMUX<18> A_BLC<18> A_BLC_SEL A_BLT<18> A_BLT_SEL A_PRE_N A_SEL_P<18> ++ A_WR_ONE A_WR_ZERO VDD VSS / RM_IHPSG13_512x16_c2_1P_BLDRV +XA_BLTMUX<17> A_BLC<17> A_BLC_SEL A_BLT<17> A_BLT_SEL A_PRE_N A_SEL_P<17> ++ A_WR_ONE A_WR_ZERO VDD VSS / RM_IHPSG13_512x16_c2_1P_BLDRV +XA_BLTMUX<16> A_BLC<16> A_BLC_SEL A_BLT<16> A_BLT_SEL A_PRE_N A_SEL_P<16> ++ A_WR_ONE A_WR_ZERO VDD VSS / RM_IHPSG13_512x16_c2_1P_BLDRV +XA_BLTMUX<15> A_BLC<15> A_BLC_SEL A_BLT<15> A_BLT_SEL A_PRE_N A_SEL_P<15> ++ A_WR_ONE A_WR_ZERO VDD VSS / RM_IHPSG13_512x16_c2_1P_BLDRV +XA_BLTMUX<14> A_BLC<14> A_BLC_SEL A_BLT<14> A_BLT_SEL A_PRE_N A_SEL_P<14> ++ A_WR_ONE A_WR_ZERO VDD VSS / RM_IHPSG13_512x16_c2_1P_BLDRV +XA_BLTMUX<13> A_BLC<13> A_BLC_SEL A_BLT<13> A_BLT_SEL A_PRE_N A_SEL_P<13> ++ A_WR_ONE A_WR_ZERO VDD VSS / RM_IHPSG13_512x16_c2_1P_BLDRV +XA_BLTMUX<12> A_BLC<12> A_BLC_SEL A_BLT<12> A_BLT_SEL A_PRE_N A_SEL_P<12> ++ A_WR_ONE A_WR_ZERO VDD VSS / RM_IHPSG13_512x16_c2_1P_BLDRV +XA_BLTMUX<11> A_BLC<11> A_BLC_SEL A_BLT<11> A_BLT_SEL A_PRE_N A_SEL_P<11> ++ A_WR_ONE A_WR_ZERO VDD VSS / RM_IHPSG13_512x16_c2_1P_BLDRV +XA_BLTMUX<10> A_BLC<10> A_BLC_SEL A_BLT<10> A_BLT_SEL A_PRE_N A_SEL_P<10> ++ A_WR_ONE A_WR_ZERO VDD VSS / RM_IHPSG13_512x16_c2_1P_BLDRV +XA_BLTMUX<9> A_BLC<9> A_BLC_SEL A_BLT<9> A_BLT_SEL A_PRE_N A_SEL_P<9> A_WR_ONE ++ A_WR_ZERO VDD VSS / RM_IHPSG13_512x16_c2_1P_BLDRV +XA_BLTMUX<8> A_BLC<8> A_BLC_SEL A_BLT<8> A_BLT_SEL A_PRE_N A_SEL_P<8> A_WR_ONE ++ A_WR_ZERO VDD VSS / RM_IHPSG13_512x16_c2_1P_BLDRV +XA_BLTMUX<7> A_BLC<7> A_BLC_SEL A_BLT<7> A_BLT_SEL A_PRE_N A_SEL_P<7> A_WR_ONE ++ A_WR_ZERO VDD VSS / RM_IHPSG13_512x16_c2_1P_BLDRV +XA_BLTMUX<6> A_BLC<6> A_BLC_SEL A_BLT<6> A_BLT_SEL A_PRE_N A_SEL_P<6> A_WR_ONE ++ A_WR_ZERO VDD VSS / RM_IHPSG13_512x16_c2_1P_BLDRV +XA_BLTMUX<5> A_BLC<5> A_BLC_SEL A_BLT<5> A_BLT_SEL A_PRE_N A_SEL_P<5> A_WR_ONE ++ A_WR_ZERO VDD VSS / RM_IHPSG13_512x16_c2_1P_BLDRV +XA_BLTMUX<4> A_BLC<4> A_BLC_SEL A_BLT<4> A_BLT_SEL A_PRE_N A_SEL_P<4> A_WR_ONE ++ A_WR_ZERO VDD VSS / RM_IHPSG13_512x16_c2_1P_BLDRV +XA_BLTMUX<3> A_BLC<3> A_BLC_SEL A_BLT<3> A_BLT_SEL A_PRE_N A_SEL_P<3> A_WR_ONE ++ A_WR_ZERO VDD VSS / RM_IHPSG13_512x16_c2_1P_BLDRV +XA_BLTMUX<2> A_BLC<2> A_BLC_SEL A_BLT<2> A_BLT_SEL A_PRE_N A_SEL_P<2> A_WR_ONE ++ A_WR_ZERO VDD VSS / RM_IHPSG13_512x16_c2_1P_BLDRV +XA_BLTMUX<1> A_BLC<1> A_BLC_SEL A_BLT<1> A_BLT_SEL A_PRE_N A_SEL_P<1> A_WR_ONE ++ A_WR_ZERO VDD VSS / RM_IHPSG13_512x16_c2_1P_BLDRV +XA_BLTMUX<0> A_BLC<0> A_BLC_SEL A_BLT<0> A_BLT_SEL A_PRE_N A_SEL_P<0> A_WR_ONE ++ A_WR_ZERO VDD VSS / RM_IHPSG13_512x16_c2_1P_BLDRV +XA_CAPS<17> VDD VSS / RSC_IHPSG13_FILLCAP4 +XA_CAPS<16> VDD VSS / RSC_IHPSG13_FILLCAP4 +XA_CAPS<15> VDD VSS / RSC_IHPSG13_FILLCAP4 +XA_CAPS<14> VDD VSS / RSC_IHPSG13_FILLCAP4 +XA_CAPS<13> VDD VSS / RSC_IHPSG13_FILLCAP4 +XA_CAPS<12> VDD VSS / RSC_IHPSG13_FILLCAP4 +XA_CAPS<11> VDD VSS / RSC_IHPSG13_FILLCAP4 +XA_CAPS<10> VDD VSS / RSC_IHPSG13_FILLCAP4 +XA_CAPS<9> VDD VSS / RSC_IHPSG13_FILLCAP4 +XA_CAPS<8> VDD VSS / RSC_IHPSG13_FILLCAP4 +XA_CAPS<7> VDD VSS / RSC_IHPSG13_FILLCAP4 +XA_CAPS<6> VDD VSS / RSC_IHPSG13_FILLCAP4 +XA_CAPS<5> VDD VSS / RSC_IHPSG13_FILLCAP4 +XA_CAPS<4> VDD VSS / RSC_IHPSG13_FILLCAP4 +XA_CAPS<3> VDD VSS / RSC_IHPSG13_FILLCAP4 +XA_CAPS<2> VDD VSS / RSC_IHPSG13_FILLCAP4 +XA_CAPS<1> VDD VSS / RSC_IHPSG13_FILLCAP4 +XA_I51 net19 A_DR_O VDD VSS / RSC_IHPSG13_INVX4 +XA_I78 A_RCLK_B_L A_SAE VDD VSS / RSC_IHPSG13_CBUFX2 +XA_I69 A_DCLK_L A_DCLK_B_L VDD VSS / RSC_IHPSG13_CINVX8 +XA_I50 A_WCLK_L A_WCLK_B_L VDD VSS / RSC_IHPSG13_CINVX8 +XA_EBUF A_RCLK_L A_RCLK_B_L VDD VSS / RSC_IHPSG13_CINVX8 +XA_I76 A_DI_N A_DO_WRITE_P A_WR_ZERO VDD VSS / RSC_IHPSG13_AND2X6 +XA_I75 A_DI_R A_DO_WRITE_P A_WR_ONE VDD VSS / RSC_IHPSG13_AND2X6 +XA_I83 A_BM_R A_BM_N VDD VSS / RSC_IHPSG13_INVX2 +XA_DEC3INV<31> net23<0> A_SEL_P<31> VDD VSS / RSC_IHPSG13_INVX2 +XA_DEC3INV<30> net23<1> A_SEL_P<30> VDD VSS / RSC_IHPSG13_INVX2 +XA_DEC3INV<29> net23<2> A_SEL_P<29> VDD VSS / RSC_IHPSG13_INVX2 +XA_DEC3INV<28> net23<3> A_SEL_P<28> VDD VSS / RSC_IHPSG13_INVX2 +XA_DEC3INV<27> net23<4> A_SEL_P<27> VDD VSS / RSC_IHPSG13_INVX2 +XA_DEC3INV<26> net23<5> A_SEL_P<26> VDD VSS / RSC_IHPSG13_INVX2 +XA_DEC3INV<25> net23<6> A_SEL_P<25> VDD VSS / RSC_IHPSG13_INVX2 +XA_DEC3INV<24> net23<7> A_SEL_P<24> VDD VSS / RSC_IHPSG13_INVX2 +XA_DEC3INV<23> net23<8> A_SEL_P<23> VDD VSS / RSC_IHPSG13_INVX2 +XA_DEC3INV<22> net23<9> A_SEL_P<22> VDD VSS / RSC_IHPSG13_INVX2 +XA_DEC3INV<21> net23<10> A_SEL_P<21> VDD VSS / RSC_IHPSG13_INVX2 +XA_DEC3INV<20> net23<11> A_SEL_P<20> VDD VSS / RSC_IHPSG13_INVX2 +XA_DEC3INV<19> net23<12> A_SEL_P<19> VDD VSS / RSC_IHPSG13_INVX2 +XA_DEC3INV<18> net23<13> A_SEL_P<18> VDD VSS / RSC_IHPSG13_INVX2 +XA_DEC3INV<17> net23<14> A_SEL_P<17> VDD VSS / RSC_IHPSG13_INVX2 +XA_DEC3INV<16> net23<15> A_SEL_P<16> VDD VSS / RSC_IHPSG13_INVX2 +XA_DEC3INV<15> net23<16> A_SEL_P<15> VDD VSS / RSC_IHPSG13_INVX2 +XA_DEC3INV<14> net23<17> A_SEL_P<14> VDD VSS / RSC_IHPSG13_INVX2 +XA_DEC3INV<13> net23<18> A_SEL_P<13> VDD VSS / RSC_IHPSG13_INVX2 +XA_DEC3INV<12> net23<19> A_SEL_P<12> VDD VSS / RSC_IHPSG13_INVX2 +XA_DEC3INV<11> net23<20> A_SEL_P<11> VDD VSS / RSC_IHPSG13_INVX2 +XA_DEC3INV<10> net23<21> A_SEL_P<10> VDD VSS / RSC_IHPSG13_INVX2 +XA_DEC3INV<9> net23<22> A_SEL_P<9> VDD VSS / RSC_IHPSG13_INVX2 +XA_DEC3INV<8> net23<23> A_SEL_P<8> VDD VSS / RSC_IHPSG13_INVX2 +XA_DEC3INV<7> net23<24> A_SEL_P<7> VDD VSS / RSC_IHPSG13_INVX2 +XA_DEC3INV<6> net23<25> A_SEL_P<6> VDD VSS / RSC_IHPSG13_INVX2 +XA_DEC3INV<5> net23<26> A_SEL_P<5> VDD VSS / RSC_IHPSG13_INVX2 +XA_DEC3INV<4> net23<27> A_SEL_P<4> VDD VSS / RSC_IHPSG13_INVX2 +XA_DEC3INV<3> net23<28> A_SEL_P<3> VDD VSS / RSC_IHPSG13_INVX2 +XA_DEC3INV<2> net23<29> A_SEL_P<2> VDD VSS / RSC_IHPSG13_INVX2 +XA_DEC3INV<1> net23<30> A_SEL_P<1> VDD VSS / RSC_IHPSG13_INVX2 +XA_DEC3INV<0> net23<31> A_SEL_P<0> VDD VSS / RSC_IHPSG13_INVX2 +XA_I49 A_DI_R A_DI_N VDD VSS / RSC_IHPSG13_INVX2 +XA_ISENSE A_SAE A_BLC_SEL A_BLT_SEL net19 net20 VDD VSS / ++ RSC_IHPSG13_DFPQD_MSAFFX2 +XA_DREG A_BIST_EN_I A_BIST_DW_I A_DCLK_B_L A_DW_I A_DI_R net22 VDD VSS ++ / RSC_IHPSG13_DFNQMX2IX1 +XA_BREG A_BIST_EN_I A_BIST_BM_I A_DCLK_B_L A_BM_I A_BM_R net21 VDD VSS ++ / RSC_IHPSG13_DFNQMX2IX1 +XA_DEC3<31> A_P1<1> A_P0<1> A_ADDR_DEC<7> net23<0> VDD VSS / ++ RSC_IHPSG13_NAND3X2 +XA_DEC3<30> A_P1<1> A_P0<1> A_ADDR_DEC<6> net23<1> VDD VSS / ++ RSC_IHPSG13_NAND3X2 +XA_DEC3<29> A_P1<1> A_P0<1> A_ADDR_DEC<5> net23<2> VDD VSS / ++ RSC_IHPSG13_NAND3X2 +XA_DEC3<28> A_P1<1> A_P0<1> A_ADDR_DEC<4> net23<3> VDD VSS / ++ RSC_IHPSG13_NAND3X2 +XA_DEC3<27> A_P1<1> A_P0<1> A_ADDR_DEC<3> net23<4> VDD VSS / ++ RSC_IHPSG13_NAND3X2 +XA_DEC3<26> A_P1<1> A_P0<1> A_ADDR_DEC<2> net23<5> VDD VSS / ++ RSC_IHPSG13_NAND3X2 +XA_DEC3<25> A_P1<1> A_P0<1> A_ADDR_DEC<1> net23<6> VDD VSS / ++ RSC_IHPSG13_NAND3X2 +XA_DEC3<24> A_P1<1> A_P0<1> A_ADDR_DEC<0> net23<7> VDD VSS / ++ RSC_IHPSG13_NAND3X2 +XA_DEC3<23> A_P1<1> A_N0<1> A_ADDR_DEC<7> net23<8> VDD VSS / ++ RSC_IHPSG13_NAND3X2 +XA_DEC3<22> A_P1<1> A_N0<1> A_ADDR_DEC<6> net23<9> VDD VSS / ++ RSC_IHPSG13_NAND3X2 +XA_DEC3<21> A_P1<1> A_N0<1> A_ADDR_DEC<5> net23<10> VDD VSS / ++ RSC_IHPSG13_NAND3X2 +XA_DEC3<20> A_P1<1> A_N0<1> A_ADDR_DEC<4> net23<11> VDD VSS / ++ RSC_IHPSG13_NAND3X2 +XA_DEC3<19> A_P1<1> A_N0<1> A_ADDR_DEC<3> net23<12> VDD VSS / ++ RSC_IHPSG13_NAND3X2 +XA_DEC3<18> A_P1<1> A_N0<1> A_ADDR_DEC<2> net23<13> VDD VSS / ++ RSC_IHPSG13_NAND3X2 +XA_DEC3<17> A_P1<1> A_N0<1> A_ADDR_DEC<1> net23<14> VDD VSS / ++ RSC_IHPSG13_NAND3X2 +XA_DEC3<16> A_P1<1> A_N0<1> A_ADDR_DEC<0> net23<15> VDD VSS / ++ RSC_IHPSG13_NAND3X2 +XA_DEC3<15> A_N1<0> A_P0<0> A_ADDR_DEC<7> net23<16> VDD VSS / ++ RSC_IHPSG13_NAND3X2 +XA_DEC3<14> A_N1<0> A_P0<0> A_ADDR_DEC<6> net23<17> VDD VSS / ++ RSC_IHPSG13_NAND3X2 +XA_DEC3<13> A_N1<0> A_P0<0> A_ADDR_DEC<5> net23<18> VDD VSS / ++ RSC_IHPSG13_NAND3X2 +XA_DEC3<12> A_N1<0> A_P0<0> A_ADDR_DEC<4> net23<19> VDD VSS / ++ RSC_IHPSG13_NAND3X2 +XA_DEC3<11> A_N1<0> A_P0<0> A_ADDR_DEC<3> net23<20> VDD VSS / ++ RSC_IHPSG13_NAND3X2 +XA_DEC3<10> A_N1<0> A_P0<0> A_ADDR_DEC<2> net23<21> VDD VSS / ++ RSC_IHPSG13_NAND3X2 +XA_DEC3<9> A_N1<0> A_P0<0> A_ADDR_DEC<1> net23<22> VDD VSS / ++ RSC_IHPSG13_NAND3X2 +XA_DEC3<8> A_N1<0> A_P0<0> A_ADDR_DEC<0> net23<23> VDD VSS / ++ RSC_IHPSG13_NAND3X2 +XA_DEC3<7> A_N1<0> A_N0<0> A_ADDR_DEC<7> net23<24> VDD VSS / ++ RSC_IHPSG13_NAND3X2 +XA_DEC3<6> A_N1<0> A_N0<0> A_ADDR_DEC<6> net23<25> VDD VSS / ++ RSC_IHPSG13_NAND3X2 +XA_DEC3<5> A_N1<0> A_N0<0> A_ADDR_DEC<5> net23<26> VDD VSS / ++ RSC_IHPSG13_NAND3X2 +XA_DEC3<4> A_N1<0> A_N0<0> A_ADDR_DEC<4> net23<27> VDD VSS / ++ RSC_IHPSG13_NAND3X2 +XA_DEC3<3> A_N1<0> A_N0<0> A_ADDR_DEC<3> net23<28> VDD VSS / ++ RSC_IHPSG13_NAND3X2 +XA_DEC3<2> A_N1<0> A_N0<0> A_ADDR_DEC<2> net23<29> VDD VSS / ++ RSC_IHPSG13_NAND3X2 +XA_DEC3<1> A_N1<0> A_N0<0> A_ADDR_DEC<1> net23<30> VDD VSS / ++ RSC_IHPSG13_NAND3X2 +XA_DEC3<0> A_N1<0> A_N0<0> A_ADDR_DEC<0> net23<31> VDD VSS / ++ RSC_IHPSG13_NAND3X2 +XA_I89 A_DCLK_B_L A_DCLK_B_R / RSC_IHPSG13_MET3RES +XA_I91 A_RCLK_B_L A_RCLK_B_R / RSC_IHPSG13_MET3RES +XA_I90 A_WCLK_B_L A_WCLK_B_R / RSC_IHPSG13_MET3RES +XA_I88 A_DCLK_L A_DCLK_R / RSC_IHPSG13_MET3RES +XA_I87 A_WCLK_L A_WCLK_R / RSC_IHPSG13_MET3RES +XA_R2 A_RCLK_L A_RCLK_R / RSC_IHPSG13_MET3RES +XA_BM_TIEH A_TIEH_O VDD VSS / RSC_IHPSG13_TIEH +.ENDS + +.SUBCKT RM_IHPSG13_512x16_c2_1P_COLDRV13X12 ADDR_COL_I<1> ADDR_COL_I<0> ADDR_COL_O<1> ++ ADDR_COL_O<0> ADDR_DEC_I<7> ADDR_DEC_I<6> ADDR_DEC_I<5> ADDR_DEC_I<4> ++ ADDR_DEC_I<3> ADDR_DEC_I<2> ADDR_DEC_I<1> ADDR_DEC_I<0> ADDR_DEC_O<7> ++ ADDR_DEC_O<6> ADDR_DEC_O<5> ADDR_DEC_O<4> ADDR_DEC_O<3> ADDR_DEC_O<2> ++ ADDR_DEC_O<1> ADDR_DEC_O<0> DCLK_I DCLK_O RCLK_I RCLK_O WCLK_I WCLK_O ++ VDD VSS +XI1<1> VDD VSS / RSC_IHPSG13_FILLCAP4 +XI1<0> VDD VSS / RSC_IHPSG13_FILLCAP4 +XI0<1> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI0<0> VDD VSS / RSC_IHPSG13_FILLCAP8 +XADDR_COL_DRV<1> ADDR_COL_I<1> ADDR_COL_O<1> VDD VSS / ++ RSC_IHPSG13_CBUFX12 +XADDR_COL_DRV<0> ADDR_COL_I<0> ADDR_COL_O<0> VDD VSS / ++ RSC_IHPSG13_CBUFX12 +XADDR_DEC_DRV<7> ADDR_DEC_I<7> ADDR_DEC_O<7> VDD VSS / ++ RSC_IHPSG13_CBUFX12 +XADDR_DEC_DRV<6> ADDR_DEC_I<6> ADDR_DEC_O<6> VDD VSS / ++ RSC_IHPSG13_CBUFX12 +XADDR_DEC_DRV<5> ADDR_DEC_I<5> ADDR_DEC_O<5> VDD VSS / ++ RSC_IHPSG13_CBUFX12 +XADDR_DEC_DRV<4> ADDR_DEC_I<4> ADDR_DEC_O<4> VDD VSS / ++ RSC_IHPSG13_CBUFX12 +XADDR_DEC_DRV<3> ADDR_DEC_I<3> ADDR_DEC_O<3> VDD VSS / ++ RSC_IHPSG13_CBUFX12 +XADDR_DEC_DRV<2> ADDR_DEC_I<2> ADDR_DEC_O<2> VDD VSS / ++ RSC_IHPSG13_CBUFX12 +XADDR_DEC_DRV<1> ADDR_DEC_I<1> ADDR_DEC_O<1> VDD VSS / ++ RSC_IHPSG13_CBUFX12 +XADDR_DEC_DRV<0> ADDR_DEC_I<0> ADDR_DEC_O<0> VDD VSS / ++ RSC_IHPSG13_CBUFX12 +XDCLK_DRV DCLK_I DCLK_O VDD VSS / RSC_IHPSG13_CBUFX12 +XRCLK_DRV RCLK_I RCLK_O VDD VSS / RSC_IHPSG13_CBUFX12 +XWCLK_DRV WCLK_I WCLK_O VDD VSS / RSC_IHPSG13_CBUFX12 +.ENDS +.SUBCKT RM_IHPSG13_512x16_c2_1P_WLDRV16X12 A<15> A<14> A<13> A<12> A<11> A<10> A<9> A<8> ++ A<7> A<6> A<5> A<4> A<3> A<2> A<1> A<0> Z<15> Z<14> Z<13> Z<12> Z<11> Z<10> ++ Z<9> Z<8> Z<7> Z<6> Z<5> Z<4> Z<3> Z<2> Z<1> Z<0> VDD VSS +XBUF<15> A<15> Z<15> VDD VSS / RSC_IHPSG13_WLDRVX12 +XBUF<14> A<14> Z<14> VDD VSS / RSC_IHPSG13_WLDRVX12 +XBUF<13> A<13> Z<13> VDD VSS / RSC_IHPSG13_WLDRVX12 +XBUF<12> A<12> Z<12> VDD VSS / RSC_IHPSG13_WLDRVX12 +XBUF<11> A<11> Z<11> VDD VSS / RSC_IHPSG13_WLDRVX12 +XBUF<10> A<10> Z<10> VDD VSS / RSC_IHPSG13_WLDRVX12 +XBUF<9> A<9> Z<9> VDD VSS / RSC_IHPSG13_WLDRVX12 +XBUF<8> A<8> Z<8> VDD VSS / RSC_IHPSG13_WLDRVX12 +XBUF<7> A<7> Z<7> VDD VSS / RSC_IHPSG13_WLDRVX12 +XBUF<6> A<6> Z<6> VDD VSS / RSC_IHPSG13_WLDRVX12 +XBUF<5> A<5> Z<5> VDD VSS / RSC_IHPSG13_WLDRVX12 +XBUF<4> A<4> Z<4> VDD VSS / RSC_IHPSG13_WLDRVX12 +XBUF<3> A<3> Z<3> VDD VSS / RSC_IHPSG13_WLDRVX12 +XBUF<2> A<2> Z<2> VDD VSS / RSC_IHPSG13_WLDRVX12 +XBUF<1> A<1> Z<1> VDD VSS / RSC_IHPSG13_WLDRVX12 +XBUF<0> A<0> Z<0> VDD VSS / RSC_IHPSG13_WLDRVX12 +.ENDS + + + +.SUBCKT RM_IHPSG13_512x16_c2_2P_COLDRV13X8 ADDR_COL_I<1> ADDR_COL_I<0> ADDR_COL_O<1> ++ ADDR_COL_O<0> ADDR_DEC_I<7> ADDR_DEC_I<6> ADDR_DEC_I<5> ADDR_DEC_I<4> ++ ADDR_DEC_I<3> ADDR_DEC_I<2> ADDR_DEC_I<1> ADDR_DEC_I<0> ADDR_DEC_O<7> ++ ADDR_DEC_O<6> ADDR_DEC_O<5> ADDR_DEC_O<4> ADDR_DEC_O<3> ADDR_DEC_O<2> ++ ADDR_DEC_O<1> ADDR_DEC_O<0> DCLK_I DCLK_O RCLK_I RCLK_O WCLK_I WCLK_O ++ VDD VSS +XI0<5> VDD VSS / RSC_IHPSG13_FILLCAP4 +XI0<4> VDD VSS / RSC_IHPSG13_FILLCAP4 +XI0<3> VDD VSS / RSC_IHPSG13_FILLCAP4 +XI0<2> VDD VSS / RSC_IHPSG13_FILLCAP4 +XI0<1> VDD VSS / RSC_IHPSG13_FILLCAP4 +XWCLK_DRV WCLK_I WCLK_O VDD VSS / RSC_IHPSG13_CBUFX8 +XRCLK_DRV RCLK_I RCLK_O VDD VSS / RSC_IHPSG13_CBUFX8 +XDCLK_DRV DCLK_I DCLK_O VDD VSS / RSC_IHPSG13_CBUFX8 +XADDR_COL_DRV<1> ADDR_COL_I<1> ADDR_COL_O<1> VDD VSS / ++ RSC_IHPSG13_CBUFX8 +XADDR_COL_DRV<0> ADDR_COL_I<0> ADDR_COL_O<0> VDD VSS / ++ RSC_IHPSG13_CBUFX8 +XADDR_DEC_DRV<7> ADDR_DEC_I<7> ADDR_DEC_O<7> VDD VSS / ++ RSC_IHPSG13_CBUFX8 +XADDR_DEC_DRV<6> ADDR_DEC_I<6> ADDR_DEC_O<6> VDD VSS / ++ RSC_IHPSG13_CBUFX8 +XADDR_DEC_DRV<5> ADDR_DEC_I<5> ADDR_DEC_O<5> VDD VSS / ++ RSC_IHPSG13_CBUFX8 +XADDR_DEC_DRV<4> ADDR_DEC_I<4> ADDR_DEC_O<4> VDD VSS / ++ RSC_IHPSG13_CBUFX8 +XADDR_DEC_DRV<3> ADDR_DEC_I<3> ADDR_DEC_O<3> VDD VSS / ++ RSC_IHPSG13_CBUFX8 +XADDR_DEC_DRV<2> ADDR_DEC_I<2> ADDR_DEC_O<2> VDD VSS / ++ RSC_IHPSG13_CBUFX8 +XADDR_DEC_DRV<1> ADDR_DEC_I<1> ADDR_DEC_O<1> VDD VSS / ++ RSC_IHPSG13_CBUFX8 +XADDR_DEC_DRV<0> ADDR_DEC_I<0> ADDR_DEC_O<0> VDD VSS / ++ RSC_IHPSG13_CBUFX8 +XI1<3> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI1<2> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI1<1> VDD VSS / RSC_IHPSG13_FILLCAP8 +.ENDS +.SUBCKT RSC_IHPSG13_WLDRVX8 A Z VDD VSS +MN1 Z net6 VSS VSS sg13_lv_nmos m=1 w=1.41u l=130.00n ng=2 nrd=0 nrs=0 +MN0 net6 A VSS VSS sg13_lv_nmos m=1 w=1.8u l=130.00n ng=2 nrd=0 nrs=0 +MP1 Z net6 VDD VDD sg13_lv_pmos m=1 w=6.48u l=130.00n ng=4 nrd=0 nrs=0 +MP0 net6 A VDD VDD sg13_lv_pmos m=1 w=900.0n l=130.00n ng=1 nrd=0 nrs=0 +.ENDS +.SUBCKT RM_IHPSG13_512x16_c2_2P_WLDRV16X8 A<15> A<14> A<13> A<12> A<11> A<10> A<9> A<8> ++ A<7> A<6> A<5> A<4> A<3> A<2> A<1> A<0> Z<15> Z<14> Z<13> Z<12> Z<11> Z<10> ++ Z<9> Z<8> Z<7> Z<6> Z<5> Z<4> Z<3> Z<2> Z<1> Z<0> VDD VSS +XBUF<15> A<15> Z<15> VDD VSS / RSC_IHPSG13_WLDRVX8 +XBUF<14> A<14> Z<14> VDD VSS / RSC_IHPSG13_WLDRVX8 +XBUF<13> A<13> Z<13> VDD VSS / RSC_IHPSG13_WLDRVX8 +XBUF<12> A<12> Z<12> VDD VSS / RSC_IHPSG13_WLDRVX8 +XBUF<11> A<11> Z<11> VDD VSS / RSC_IHPSG13_WLDRVX8 +XBUF<10> A<10> Z<10> VDD VSS / RSC_IHPSG13_WLDRVX8 +XBUF<9> A<9> Z<9> VDD VSS / RSC_IHPSG13_WLDRVX8 +XBUF<8> A<8> Z<8> VDD VSS / RSC_IHPSG13_WLDRVX8 +XBUF<7> A<7> Z<7> VDD VSS / RSC_IHPSG13_WLDRVX8 +XBUF<6> A<6> Z<6> VDD VSS / RSC_IHPSG13_WLDRVX8 +XBUF<5> A<5> Z<5> VDD VSS / RSC_IHPSG13_WLDRVX8 +XBUF<4> A<4> Z<4> VDD VSS / RSC_IHPSG13_WLDRVX8 +XBUF<3> A<3> Z<3> VDD VSS / RSC_IHPSG13_WLDRVX8 +XBUF<2> A<2> Z<2> VDD VSS / RSC_IHPSG13_WLDRVX8 +XBUF<1> A<1> Z<1> VDD VSS / RSC_IHPSG13_WLDRVX8 +XBUF<0> A<0> Z<0> VDD VSS / RSC_IHPSG13_WLDRVX8 +.ENDS + + + +.SUBCKT RM_IHPSG13_512x16_c2_2P_COLDEC2 ACLK_N ADDR<1> ADDR<0> ADDR_COL<1> ADDR_COL<0> ++ ADDR_DEC<7> ADDR_DEC<6> ADDR_DEC<5> ADDR_DEC<4> ADDR_DEC<3> ADDR_DEC<2> ++ ADDR_DEC<1> ADDR_DEC<0> BIST_ADDR<1> BIST_ADDR<0> BIST_EN_I VDD VSS +XI16<17> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI16<16> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI16<15> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI16<14> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI16<13> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI16<12> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI16<11> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI16<10> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI16<9> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI16<8> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI16<7> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI16<6> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI16<5> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI16<4> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI16<3> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI16<2> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI16<1> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI18<24> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI18<23> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI18<22> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI18<21> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI18<20> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI18<19> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI18<18> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI18<17> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI18<16> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI18<15> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI18<14> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI18<13> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI18<12> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI18<11> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI18<10> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI18<9> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI18<8> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI18<7> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI18<6> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI18<5> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI18<4> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI18<3> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI18<2> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI18<1> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI1<3> PADR<0> PADR<1> addr_n<3> VDD VSS / RSC_IHPSG13_NAND2X2 +XI1<2> NADR<0> PADR<1> addr_n<2> VDD VSS / RSC_IHPSG13_NAND2X2 +XI1<1> PADR<0> NADR<1> addr_n<1> VDD VSS / RSC_IHPSG13_NAND2X2 +XI1<0> NADR<0> NADR<1> addr_n<0> VDD VSS / RSC_IHPSG13_NAND2X2 +XI17<1> ADDR_COL<1> VDD VSS / RSC_IHPSG13_TIEL +XI17<0> ADDR_COL<0> VDD VSS / RSC_IHPSG13_TIEL +XI14<3> ADDR_DEC<7> VDD VSS / RSC_IHPSG13_TIEL +XI14<2> ADDR_DEC<6> VDD VSS / RSC_IHPSG13_TIEL +XI14<1> ADDR_DEC<5> VDD VSS / RSC_IHPSG13_TIEL +XI14<0> ADDR_DEC<4> VDD VSS / RSC_IHPSG13_TIEL +XI13<1> NADR<1> PADR<1> VDD VSS / RSC_IHPSG13_INVX2 +XI13<0> NADR<0> PADR<0> VDD VSS / RSC_IHPSG13_INVX2 +XI3<1> padr_int<1> NADR<1> VDD VSS / RSC_IHPSG13_INVX2 +XI3<0> padr_int<0> NADR<0> VDD VSS / RSC_IHPSG13_INVX2 +XI2<3> addr_n<3> ADDR_DEC<3> VDD VSS / RSC_IHPSG13_INVX2 +XI2<2> addr_n<2> ADDR_DEC<2> VDD VSS / RSC_IHPSG13_INVX2 +XI2<1> addr_n<1> ADDR_DEC<1> VDD VSS / RSC_IHPSG13_INVX2 +XI2<0> addr_n<0> ADDR_DEC<0> VDD VSS / RSC_IHPSG13_INVX2 +XDFF<1> BIST_EN_I BIST_ADDR<1> ACLK_N ADDR<1> padr_int<1> net12<0> VDD ++ VSS / RSC_IHPSG13_DFNQMX2IX1 +XDFF<0> BIST_EN_I BIST_ADDR<0> ACLK_N ADDR<0> padr_int<0> net12<1> VDD ++ VSS / RSC_IHPSG13_DFNQMX2IX1 +XI15<5> VDD VSS / RSC_IHPSG13_FILLCAP4 +XI15<4> VDD VSS / RSC_IHPSG13_FILLCAP4 +XI15<3> VDD VSS / RSC_IHPSG13_FILLCAP4 +XI15<2> VDD VSS / RSC_IHPSG13_FILLCAP4 +XI15<1> VDD VSS / RSC_IHPSG13_FILLCAP4 +XI19<4> VDD VSS / RSC_IHPSG13_FILLCAP4 +XI19<3> VDD VSS / RSC_IHPSG13_FILLCAP4 +XI19<2> VDD VSS / RSC_IHPSG13_FILLCAP4 +XI19<1> VDD VSS / RSC_IHPSG13_FILLCAP4 +.ENDS +.SUBCKT RM_IHPSG13_512x16_c2_2P_COLCTRL2 A_ADDR_DEC<3> A_ADDR_DEC<2> A_ADDR_DEC<1> ++ A_ADDR_DEC<0> A_BIST_BM_I A_BIST_DW_I A_BIST_EN_I A_BLC<3> A_BLC<2> A_BLC<1> ++ A_BLC<0> A_BLT<3> A_BLT<2> A_BLT<1> A_BLT<0> A_BM_I A_DCLK_B_L A_DCLK_B_R ++ A_DCLK_L A_DCLK_R A_DR_O A_DW_I A_RCLK_B_L A_RCLK_B_R A_RCLK_L A_RCLK_R ++ A_TIEH_O A_WCLK_B_L A_WCLK_B_R A_WCLK_L A_WCLK_R B_ADDR_DEC<3> B_ADDR_DEC<2> ++ B_ADDR_DEC<1> B_ADDR_DEC<0> B_BIST_BM_I B_BIST_DW_I B_BIST_EN_I B_BLC<3> ++ B_BLC<2> B_BLC<1> B_BLC<0> B_BLT<3> B_BLT<2> B_BLT<1> B_BLT<0> B_BM_I ++ B_DCLK_B_L B_DCLK_B_R B_DCLK_L B_DCLK_R B_DR_O B_DW_I B_RCLK_B_L B_RCLK_B_R ++ B_RCLK_L B_RCLK_R B_TIEH_O B_WCLK_B_L B_WCLK_B_R B_WCLK_L B_WCLK_R VDD ++ VSS +XB_DREG B_BIST_EN_I B_BIST_DW_I B_DCLK_B_L B_DW_I B_DI_R net046 VDD ++ VSS / RSC_IHPSG13_DFNQMX2IX1 +XB_BREG B_BIST_EN_I B_BIST_BM_I B_DCLK_B_L B_BM_I B_BM_R net045 VDD ++ VSS / RSC_IHPSG13_DFNQMX2IX1 +XA_DREG A_BIST_EN_I A_BIST_DW_I A_DCLK_B_L A_DW_I A_DI_R net22 VDD VSS ++ / RSC_IHPSG13_DFNQMX2IX1 +XA_BREG A_BIST_EN_I A_BIST_BM_I A_DCLK_B_L A_BM_I A_BM_R net23 VDD VSS ++ / RSC_IHPSG13_DFNQMX2IX1 +XB_CAPS VDD VSS / RSC_IHPSG13_FILLCAP4 +XA_CAPS VDD VSS / RSC_IHPSG13_FILLCAP4 +XB_I75 B_DI_R B_DO_WRITE_P B_WR_ONE VDD VSS / RSC_IHPSG13_AND2X2 +XB_I80 B_RCLK_B_L B_WCLK_B_L net041 VDD VSS / RSC_IHPSG13_AND2X2 +XB_I76 B_DI_N B_DO_WRITE_P B_WR_ZERO VDD VSS / RSC_IHPSG13_AND2X2 +XA_I80 A_RCLK_B_L A_WCLK_B_L net21 VDD VSS / RSC_IHPSG13_AND2X2 +XA_I75 A_DI_R A_DO_WRITE_P A_WR_ONE VDD VSS / RSC_IHPSG13_AND2X2 +XA_I76 A_DI_N A_DO_WRITE_P A_WR_ZERO VDD VSS / RSC_IHPSG13_AND2X2 +XB_I44 B_WCLK_B_L B_BM_N B_DO_WRITE_P VDD VSS / RSC_IHPSG13_NOR2X2 +XA_I44 A_WCLK_B_L A_BM_N A_DO_WRITE_P VDD VSS / RSC_IHPSG13_NOR2X2 +XB_I81 net041 B_PRE_N VDD VSS / RSC_IHPSG13_CINVX4_WN +XA_I81 net21 A_PRE_N VDD VSS / RSC_IHPSG13_CINVX4_WN +XB_BM_TIEH B_TIEH_O VDD VSS / RSC_IHPSG13_TIEH +XA_BM_TIEH A_TIEH_O VDD VSS / RSC_IHPSG13_TIEH +XA_I89 A_DCLK_B_L A_DCLK_B_R / RSC_IHPSG13_MET3RES +XA_I88 A_DCLK_L A_DCLK_R / RSC_IHPSG13_MET3RES +XA_I87 A_WCLK_L A_WCLK_R / RSC_IHPSG13_MET3RES +XA_I91 A_RCLK_B_L A_RCLK_B_R / RSC_IHPSG13_MET3RES +XB_I87 B_WCLK_L B_WCLK_R / RSC_IHPSG13_MET3RES +XB_I88 B_DCLK_L B_DCLK_R / RSC_IHPSG13_MET3RES +XB_I89 B_DCLK_B_L B_DCLK_B_R / RSC_IHPSG13_MET3RES +XB_I90 B_WCLK_B_L B_WCLK_B_R / RSC_IHPSG13_MET3RES +XB_R2 B_RCLK_L B_RCLK_R / RSC_IHPSG13_MET3RES +XB_I91 B_RCLK_B_L B_RCLK_B_R / RSC_IHPSG13_MET3RES +XA_R2 A_RCLK_L A_RCLK_R / RSC_IHPSG13_MET3RES +XA_I90 A_WCLK_B_L A_WCLK_B_R / RSC_IHPSG13_MET3RES +XAB_BLMUX A_BLC<3> A_BLC<2> A_BLC<1> A_BLC<0> A_BLC_SEL A_BLT<3> A_BLT<2> ++ A_BLT<1> A_BLT<0> A_BLT_SEL A_PRE_N A_ADDR_DEC<3> A_ADDR_DEC<2> ++ A_ADDR_DEC<1> A_ADDR_DEC<0> A_WR_ONE A_WR_ZERO B_BLC<3> B_BLC<2> B_BLC<1> ++ B_BLC<0> B_BLC_SEL B_BLT<3> B_BLT<2> B_BLT<1> B_BLT<0> B_BLT_SEL B_PRE_N ++ B_ADDR_DEC<3> B_ADDR_DEC<2> B_ADDR_DEC<1> B_ADDR_DEC<0> B_WR_ONE B_WR_ZERO ++ VDD VSS / RM_IHPSG13_512x16_c2_2P_BLDRV +XB_ISENSE B_SAE B_BLC_SEL B_BLT_SEL net039 net040 VDD VSS / ++ RSC_IHPSG13_DFPQD_MSAFFX2 +XA_ISENSE A_SAE A_BLC_SEL A_BLT_SEL net19 net20 VDD VSS / ++ RSC_IHPSG13_DFPQD_MSAFFX2 +XB_I78 B_RCLK_B_L B_SAE VDD VSS / RSC_IHPSG13_CBUFX2 +XA_I78 A_RCLK_B_L A_SAE VDD VSS / RSC_IHPSG13_CBUFX2 +XB_I83 B_BM_R B_BM_N VDD VSS / RSC_IHPSG13_INVX2 +XB_I49 B_DI_R B_DI_N VDD VSS / RSC_IHPSG13_INVX2 +XA_I83 A_BM_R A_BM_N VDD VSS / RSC_IHPSG13_INVX2 +XA_I49 A_DI_R A_DI_N VDD VSS / RSC_IHPSG13_INVX2 +XB_I51 net039 B_DR_O VDD VSS / RSC_IHPSG13_INVX4 +XA_I51 net19 A_DR_O VDD VSS / RSC_IHPSG13_INVX4 +XA_I69 A_DCLK_L A_DCLK_B_L VDD VSS / RSC_IHPSG13_CINVX2 +XA_I50 A_WCLK_L A_WCLK_B_L VDD VSS / RSC_IHPSG13_CINVX2 +XA_EBUF A_RCLK_L A_RCLK_B_L VDD VSS / RSC_IHPSG13_CINVX2 +XB_EBUF B_RCLK_L B_RCLK_B_L VDD VSS / RSC_IHPSG13_CINVX2 +XB_I50 B_WCLK_L B_WCLK_B_L VDD VSS / RSC_IHPSG13_CINVX2 +XB_I69 B_DCLK_L B_DCLK_B_L VDD VSS / RSC_IHPSG13_CINVX2 +.ENDS +.SUBCKT RM_IHPSG13_512x16_c2_2P_COLDRV13_FILL4C2 VDD VSS +XI0<2> VDD VSS / RSC_IHPSG13_FILLCAP4 +XI0<1> VDD VSS / RSC_IHPSG13_FILLCAP4 +.ENDS + + +.SUBCKT RM_IHPSG13_512x16_c2_2P_ROWDEC7 ADDR_N_I<6> ADDR_N_I<5> ADDR_N_I<4> ADDR_N_I<3> ++ ADDR_N_I<2> ADDR_N_I<1> ADDR_N_I<0> CS_I ECLK_I WL_O<127> WL_O<126> ++ WL_O<125> WL_O<124> WL_O<123> WL_O<122> WL_O<121> WL_O<120> WL_O<119> ++ WL_O<118> WL_O<117> WL_O<116> WL_O<115> WL_O<114> WL_O<113> WL_O<112> ++ WL_O<111> WL_O<110> WL_O<109> WL_O<108> WL_O<107> WL_O<106> WL_O<105> ++ WL_O<104> WL_O<103> WL_O<102> WL_O<101> WL_O<100> WL_O<99> WL_O<98> WL_O<97> ++ WL_O<96> WL_O<95> WL_O<94> WL_O<93> WL_O<92> WL_O<91> WL_O<90> WL_O<89> ++ WL_O<88> WL_O<87> WL_O<86> WL_O<85> WL_O<84> WL_O<83> WL_O<82> WL_O<81> ++ WL_O<80> WL_O<79> WL_O<78> WL_O<77> WL_O<76> WL_O<75> WL_O<74> WL_O<73> ++ WL_O<72> WL_O<71> WL_O<70> WL_O<69> WL_O<68> WL_O<67> WL_O<66> WL_O<65> ++ WL_O<64> WL_O<63> WL_O<62> WL_O<61> WL_O<60> WL_O<59> WL_O<58> WL_O<57> ++ WL_O<56> WL_O<55> WL_O<54> WL_O<53> WL_O<52> WL_O<51> WL_O<50> WL_O<49> ++ WL_O<48> WL_O<47> WL_O<46> WL_O<45> WL_O<44> WL_O<43> WL_O<42> WL_O<41> ++ WL_O<40> WL_O<39> WL_O<38> WL_O<37> WL_O<36> WL_O<35> WL_O<34> WL_O<33> ++ WL_O<32> WL_O<31> WL_O<30> WL_O<29> WL_O<28> WL_O<27> WL_O<26> WL_O<25> ++ WL_O<24> WL_O<23> WL_O<22> WL_O<21> WL_O<20> WL_O<19> WL_O<18> WL_O<17> ++ WL_O<16> WL_O<15> WL_O<14> WL_O<13> WL_O<12> WL_O<11> WL_O<10> WL_O<9> ++ WL_O<8> WL_O<7> WL_O<6> WL_O<5> WL_O<4> WL_O<3> WL_O<2> WL_O<1> WL_O<0> ++ VDD VSS +XSEL<7> ADDR_N_I<3> ADDR_N_I<2> ADDR_N_I<1> ADDR_N_I<0> CS00<7> ECLK_H<7> ++ ECLK_H<8> ECLK_B<7> ECLK_B<8> WL_O<127> WL_O<126> WL_O<125> WL_O<124> ++ WL_O<123> WL_O<122> WL_O<121> WL_O<120> WL_O<119> WL_O<118> WL_O<117> ++ WL_O<116> WL_O<115> WL_O<114> WL_O<113> WL_O<112> VDD VSS / ++ RM_IHPSG13_512x16_c2_2P_DEC04 +XSEL<6> ADDR_N_I<3> ADDR_N_I<2> ADDR_N_I<1> ADDR_N_I<0> CS00<6> ECLK_H<6> ++ ECLK_H<7> ECLK_B<6> ECLK_B<7> WL_O<111> WL_O<110> WL_O<109> WL_O<108> ++ WL_O<107> WL_O<106> WL_O<105> WL_O<104> WL_O<103> WL_O<102> WL_O<101> ++ WL_O<100> WL_O<99> WL_O<98> WL_O<97> WL_O<96> VDD VSS / ++ RM_IHPSG13_512x16_c2_2P_DEC04 +XSEL<5> ADDR_N_I<3> ADDR_N_I<2> ADDR_N_I<1> ADDR_N_I<0> CS00<5> ECLK_H<5> ++ ECLK_H<6> ECLK_B<5> ECLK_B<6> WL_O<95> WL_O<94> WL_O<93> WL_O<92> WL_O<91> ++ WL_O<90> WL_O<89> WL_O<88> WL_O<87> WL_O<86> WL_O<85> WL_O<84> WL_O<83> ++ WL_O<82> WL_O<81> WL_O<80> VDD VSS / RM_IHPSG13_512x16_c2_2P_DEC04 +XSEL<4> ADDR_N_I<3> ADDR_N_I<2> ADDR_N_I<1> ADDR_N_I<0> CS00<4> ECLK_H<4> ++ ECLK_H<5> ECLK_B<4> ECLK_B<5> WL_O<79> WL_O<78> WL_O<77> WL_O<76> WL_O<75> ++ WL_O<74> WL_O<73> WL_O<72> WL_O<71> WL_O<70> WL_O<69> WL_O<68> WL_O<67> ++ WL_O<66> WL_O<65> WL_O<64> VDD VSS / RM_IHPSG13_512x16_c2_2P_DEC04 +XSEL<3> ADDR_N_I<3> ADDR_N_I<2> ADDR_N_I<1> ADDR_N_I<0> CS00<3> ECLK_H<3> ++ ECLK_H<4> ECLK_B<3> ECLK_B<4> WL_O<63> WL_O<62> WL_O<61> WL_O<60> WL_O<59> ++ WL_O<58> WL_O<57> WL_O<56> WL_O<55> WL_O<54> WL_O<53> WL_O<52> WL_O<51> ++ WL_O<50> WL_O<49> WL_O<48> VDD VSS / RM_IHPSG13_512x16_c2_2P_DEC04 +XSEL<2> ADDR_N_I<3> ADDR_N_I<2> ADDR_N_I<1> ADDR_N_I<0> CS00<2> ECLK_H<2> ++ ECLK_H<3> ECLK_B<2> ECLK_B<3> WL_O<47> WL_O<46> WL_O<45> WL_O<44> WL_O<43> ++ WL_O<42> WL_O<41> WL_O<40> WL_O<39> WL_O<38> WL_O<37> WL_O<36> WL_O<35> ++ WL_O<34> WL_O<33> WL_O<32> VDD VSS / RM_IHPSG13_512x16_c2_2P_DEC04 +XSEL<1> ADDR_N_I<3> ADDR_N_I<2> ADDR_N_I<1> ADDR_N_I<0> CS00<1> ECLK_H<1> ++ ECLK_H<2> ECLK_B<1> ECLK_B<2> WL_O<31> WL_O<30> WL_O<29> WL_O<28> WL_O<27> ++ WL_O<26> WL_O<25> WL_O<24> WL_O<23> WL_O<22> WL_O<21> WL_O<20> WL_O<19> ++ WL_O<18> WL_O<17> WL_O<16> VDD VSS / RM_IHPSG13_512x16_c2_2P_DEC04 +XSEL<0> ADDR_N_I<3> ADDR_N_I<2> ADDR_N_I<1> ADDR_N_I<0> CS00<0> ECLK_I ++ ECLK_H<1> ECLK_B<0> ECLK_B<1> WL_O<15> WL_O<14> WL_O<13> WL_O<12> WL_O<11> ++ WL_O<10> WL_O<9> WL_O<8> WL_O<7> WL_O<6> WL_O<5> WL_O<4> WL_O<3> WL_O<2> ++ WL_O<1> WL_O<0> VDD VSS / RM_IHPSG13_512x16_c2_2P_DEC04 +XDEC11<1> ADDR_N_I<5> ADDR_N_I<4> CS04<1> CS00<7> VDD VSS / ++ RM_IHPSG13_512x16_c2_2P_DEC03 +XDEC11<0> ADDR_N_I<5> ADDR_N_I<4> CS04<0> CS00<3> VDD VSS / ++ RM_IHPSG13_512x16_c2_2P_DEC03 +XDEC01<2> ADDR_N_I<7> ADDR_N_I<6> CS_I CS04<1> VDD VSS / ++ RM_IHPSG13_512x16_c2_2P_DEC01 +XDEC01<1> ADDR_N_I<5> ADDR_N_I<4> CS04<1> CS00<5> VDD VSS / ++ RM_IHPSG13_512x16_c2_2P_DEC01 +XDEC01<0> ADDR_N_I<5> ADDR_N_I<4> CS04<0> CS00<1> VDD VSS / ++ RM_IHPSG13_512x16_c2_2P_DEC01 +XL2<66> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<65> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<64> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<63> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<62> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<61> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<60> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<59> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<58> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<57> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<56> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<55> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<54> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<53> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<52> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<51> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<50> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<49> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<48> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<47> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<46> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<45> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<44> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<43> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<42> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<41> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<40> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<39> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<38> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<37> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<36> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<35> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<34> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<33> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<32> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<31> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<30> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<29> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<28> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<27> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<26> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<25> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<24> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<23> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<22> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<21> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<20> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<19> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<18> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<17> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<16> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<15> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<14> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<13> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<12> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<11> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<10> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<9> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<8> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<7> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<6> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<5> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<4> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<3> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<2> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<1> VDD VSS / RSC_IHPSG13_FILLCAP8 +XDEC10<1> ADDR_N_I<5> ADDR_N_I<4> CS04<1> CS00<6> VDD VSS / ++ RM_IHPSG13_512x16_c2_2P_DEC02 +XDEC10<0> ADDR_N_I<5> ADDR_N_I<4> CS04<0> CS00<2> VDD VSS / ++ RM_IHPSG13_512x16_c2_2P_DEC02 +XDEC00<2> ADDR_N_I<7> ADDR_N_I<6> CS_I CS04<0> VDD VSS / ++ RM_IHPSG13_512x16_c2_2P_DEC00 +XDEC00<1> ADDR_N_I<5> ADDR_N_I<4> CS04<1> CS00<4> VDD VSS / ++ RM_IHPSG13_512x16_c2_2P_DEC00 +XDEC00<0> ADDR_N_I<5> ADDR_N_I<4> CS04<0> CS00<0> VDD VSS / ++ RM_IHPSG13_512x16_c2_2P_DEC00 +XI0 ADDR_N_I<7> VDD VSS / RSC_IHPSG13_TIEL +.ENDS +.SUBCKT RM_IHPSG13_512x16_c2_2P_ROWREG7 ACLK_N_I ADDR_I<6> ADDR_I<5> ADDR_I<4> ADDR_I<3> ++ ADDR_I<2> ADDR_I<1> ADDR_I<0> ADDR_N_O<6> ADDR_N_O<5> ADDR_N_O<4> ++ ADDR_N_O<3> ADDR_N_O<2> ADDR_N_O<1> ADDR_N_O<0> BIST_ADDR_I<6> ++ BIST_ADDR_I<5> BIST_ADDR_I<4> BIST_ADDR_I<3> BIST_ADDR_I<2> BIST_ADDR_I<1> ++ BIST_ADDR_I<0> BIST_EN_I VDD VSS +XINV<6> q_int<6> qn_int<6> VDD VSS / RSC_IHPSG13_CINVX2 +XINV<5> q_int<5> qn_int<5> VDD VSS / RSC_IHPSG13_CINVX2 +XINV<4> q_int<4> qn_int<4> VDD VSS / RSC_IHPSG13_CINVX2 +XINV<3> q_int<3> qn_int<3> VDD VSS / RSC_IHPSG13_CINVX2 +XINV<2> q_int<2> qn_int<2> VDD VSS / RSC_IHPSG13_CINVX2 +XINV<1> q_int<1> qn_int<1> VDD VSS / RSC_IHPSG13_CINVX2 +XINV<0> q_int<0> qn_int<0> VDD VSS / RSC_IHPSG13_CINVX2 +XDRV<6> qn_int<6> ADDR_N_O<6> VDD VSS / RSC_IHPSG13_CINVX8 +XDRV<5> qn_int<5> ADDR_N_O<5> VDD VSS / RSC_IHPSG13_CINVX8 +XDRV<4> qn_int<4> ADDR_N_O<4> VDD VSS / RSC_IHPSG13_CINVX8 +XDRV<3> qn_int<3> ADDR_N_O<3> VDD VSS / RSC_IHPSG13_CINVX8 +XDRV<2> qn_int<2> ADDR_N_O<2> VDD VSS / RSC_IHPSG13_CINVX8 +XDRV<1> qn_int<1> ADDR_N_O<1> VDD VSS / RSC_IHPSG13_CINVX8 +XDRV<0> qn_int<0> ADDR_N_O<0> VDD VSS / RSC_IHPSG13_CINVX8 +XDFF<6> BIST_EN_I BIST_ADDR_I<6> ACLK_N_I ADDR_I<6> q_int<6> net2<0> VDD ++ VSS / RSC_IHPSG13_DFNQMX2IX1 +XDFF<5> BIST_EN_I BIST_ADDR_I<5> ACLK_N_I ADDR_I<5> q_int<5> net2<1> VDD ++ VSS / RSC_IHPSG13_DFNQMX2IX1 +XDFF<4> BIST_EN_I BIST_ADDR_I<4> ACLK_N_I ADDR_I<4> q_int<4> net2<2> VDD ++ VSS / RSC_IHPSG13_DFNQMX2IX1 +XDFF<3> BIST_EN_I BIST_ADDR_I<3> ACLK_N_I ADDR_I<3> q_int<3> net2<3> VDD ++ VSS / RSC_IHPSG13_DFNQMX2IX1 +XDFF<2> BIST_EN_I BIST_ADDR_I<2> ACLK_N_I ADDR_I<2> q_int<2> net2<4> VDD ++ VSS / RSC_IHPSG13_DFNQMX2IX1 +XDFF<1> BIST_EN_I BIST_ADDR_I<1> ACLK_N_I ADDR_I<1> q_int<1> net2<5> VDD ++ VSS / RSC_IHPSG13_DFNQMX2IX1 +XDFF<0> BIST_EN_I BIST_ADDR_I<0> ACLK_N_I ADDR_I<0> q_int<0> net2<6> VDD ++ VSS / RSC_IHPSG13_DFNQMX2IX1 +XI11<7> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI11<6> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI11<5> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI11<4> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI11<3> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI11<2> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI11<1> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI11<0> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI12<1> VDD VSS / RSC_IHPSG13_FILLCAP4 +XI12<0> VDD VSS / RSC_IHPSG13_FILLCAP4 +.ENDS + +.SUBCKT RM_IHPSG13_512x16_c2_2P_ROWDEC4 ADDR_N_I<3> ADDR_N_I<2> ADDR_N_I<1> ADDR_N_I<0> ++ CS_I ECLK_I WL_O<15> WL_O<14> WL_O<13> WL_O<12> WL_O<11> WL_O<10> WL_O<9> ++ WL_O<8> WL_O<7> WL_O<6> WL_O<5> WL_O<4> WL_O<3> WL_O<2> WL_O<1> WL_O<0> ++ VDD VSS +XL2<12> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<11> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<10> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<9> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<8> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<7> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<6> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<5> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<4> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<3> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<2> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<1> VDD VSS / RSC_IHPSG13_FILLCAP8 +XSEL ADDR_N_I<3> ADDR_N_I<2> ADDR_N_I<1> ADDR_N_I<0> CS_I ECLK_I ECLK_H<1> ++ ECLK_B<0> ECLK_B<1> WL_O<15> WL_O<14> WL_O<13> WL_O<12> WL_O<11> WL_O<10> ++ WL_O<9> WL_O<8> WL_O<7> WL_O<6> WL_O<5> WL_O<4> WL_O<3> WL_O<2> WL_O<1> ++ WL_O<0> VDD VSS / RM_IHPSG13_512x16_c2_2P_DEC04 +.ENDS +.SUBCKT RM_IHPSG13_512x16_c2_2P_ROWREG4 ACLK_N_I ADDR_I<3> ADDR_I<2> ADDR_I<1> ADDR_I<0> ++ ADDR_N_O<3> ADDR_N_O<2> ADDR_N_O<1> ADDR_N_O<0> BIST_ADDR_I<3> ++ BIST_ADDR_I<2> BIST_ADDR_I<1> BIST_ADDR_I<0> BIST_EN_I VDD VSS +XINV<3> q_int<3> qn_int<3> VDD VSS / RSC_IHPSG13_CINVX2 +XINV<2> q_int<2> qn_int<2> VDD VSS / RSC_IHPSG13_CINVX2 +XINV<1> q_int<1> qn_int<1> VDD VSS / RSC_IHPSG13_CINVX2 +XINV<0> q_int<0> qn_int<0> VDD VSS / RSC_IHPSG13_CINVX2 +XDRV<3> qn_int<3> ADDR_N_O<3> VDD VSS / RSC_IHPSG13_CINVX8 +XDRV<2> qn_int<2> ADDR_N_O<2> VDD VSS / RSC_IHPSG13_CINVX8 +XDRV<1> qn_int<1> ADDR_N_O<1> VDD VSS / RSC_IHPSG13_CINVX8 +XDRV<0> qn_int<0> ADDR_N_O<0> VDD VSS / RSC_IHPSG13_CINVX8 +XDFF<3> BIST_EN_I BIST_ADDR_I<3> ACLK_N_I ADDR_I<3> q_int<3> net7<0> VDD ++ VSS / RSC_IHPSG13_DFNQMX2IX1 +XDFF<2> BIST_EN_I BIST_ADDR_I<2> ACLK_N_I ADDR_I<2> q_int<2> net7<1> VDD ++ VSS / RSC_IHPSG13_DFNQMX2IX1 +XDFF<1> BIST_EN_I BIST_ADDR_I<1> ACLK_N_I ADDR_I<1> q_int<1> net7<2> VDD ++ VSS / RSC_IHPSG13_DFNQMX2IX1 +XDFF<0> BIST_EN_I BIST_ADDR_I<0> ACLK_N_I ADDR_I<0> q_int<0> net7<3> VDD ++ VSS / RSC_IHPSG13_DFNQMX2IX1 +XI11<20> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI11<19> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI11<18> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI11<17> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI11<16> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI11<15> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI11<14> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI11<13> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI11<12> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI11<11> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI11<10> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI11<9> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI11<8> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI11<7> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI11<6> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI11<5> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI11<4> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI11<3> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI11<2> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI11<1> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI12<4> VDD VSS / RSC_IHPSG13_FILLCAP4 +XI12<3> VDD VSS / RSC_IHPSG13_FILLCAP4 +XI12<2> VDD VSS / RSC_IHPSG13_FILLCAP4 +XI12<1> VDD VSS / RSC_IHPSG13_FILLCAP4 +XI12<0> VDD VSS / RSC_IHPSG13_FILLCAP4 +.ENDS + + +.SUBCKT RM_IHPSG13_512x16_c2_1P_BITKIT_TAP BLC BLT NW PW VDD VSS +.ENDS +.SUBCKT RM_IHPSG13_512x16_c2_1P_BITKIT_16x2_TAP A_BLC<1> A_BLC<0> A_BLT<1> A_BLT<0> ++ VDD_CORE VSS +XITAP<1> A_BLC<1> A_BLT<1> VDD_CORE VSS VDD_CORE VSS ++ / RM_IHPSG13_512x16_c2_1P_BITKIT_TAP +XITAP<0> A_BLC<0> A_BLT<0> VDD_CORE VSS VDD_CORE VSS ++ / RM_IHPSG13_512x16_c2_1P_BITKIT_TAP +XIEDGEBP_COL1<1> BLC<1> BLT<1> VDD_CORE VSS VDD_CORE ++ VSS / RM_IHPSG13_512x16_c2_1P_BITKIT_EDGE_TB +XIEDGEBP_COL1<0> BLC<1> BLT<1> VDD_CORE VSS VDD_CORE ++ VSS / RM_IHPSG13_512x16_c2_1P_BITKIT_EDGE_TB +XIEDGEBP_COL2<1> BLC<0> BLT<0> VDD_CORE VSS VDD_CORE ++ VSS / RM_IHPSG13_512x16_c2_1P_BITKIT_EDGE_TB +XIEDGEBP_COL2<0> BLC<0> BLT<0> VDD_CORE VSS VDD_CORE ++ VSS / RM_IHPSG13_512x16_c2_1P_BITKIT_EDGE_TB +.ENDS +.SUBCKT RM_IHPSG13_512x16_c2_1P_BITKIT_16x2_TAP_LR VDD_CORE VSS +XCORNER<1> VDD_CORE VSS VDD_CORE VSS / ++ RM_IHPSG13_512x16_c2_1P_BITKIT_CORNER +XCORNER<0> VDD_CORE VSS VDD_CORE VSS / ++ RM_IHPSG13_512x16_c2_1P_BITKIT_CORNER +XTAP_BORDER VDD_CORE VSS VDD_CORE VSS / ++ RM_IHPSG13_512x16_c2_1P_BITKIT_TAP_LR +.ENDS +.SUBCKT RM_IHPSG13_512x16_c2_1P_DEC03 ADDR<1> ADDR<0> CS CS_OUT VDD VSS +XDECINV net1 CS_OUT VDD VSS / RSC_IHPSG13_INVX4 +XI0 VDD VSS / RSC_IHPSG13_FILLCAP4 +XDEC ADDR<1> ADDR<0> CS net1 VDD VSS / RSC_IHPSG13_NAND3X2 +.ENDS +.SUBCKT RM_IHPSG13_512x16_c2_1P_DEC02 ADDR<1> ADDR<0> CS CS_OUT VDD VSS +XDECINV net1 CS_OUT VDD VSS / RSC_IHPSG13_INVX4 +XDEC ADDR<1> NADDR<0> CS net1 VDD VSS / RSC_IHPSG13_NAND3X2 +XI2 VDD VSS / RSC_IHPSG13_FILLCAP4 +XADDRINV ADDR<0> NADDR<0> VDD VSS / RSC_IHPSG13_INVX2 +.ENDS +.SUBCKT RM_IHPSG13_512x16_c2_1P_ROWDEC8 ADDR_N_I<7> ADDR_N_I<6> ADDR_N_I<5> ADDR_N_I<4> ++ ADDR_N_I<3> ADDR_N_I<2> ADDR_N_I<1> ADDR_N_I<0> CS_I ECLK_I WL_O<255> ++ WL_O<254> WL_O<253> WL_O<252> WL_O<251> WL_O<250> WL_O<249> WL_O<248> ++ WL_O<247> WL_O<246> WL_O<245> WL_O<244> WL_O<243> WL_O<242> WL_O<241> ++ WL_O<240> WL_O<239> WL_O<238> WL_O<237> WL_O<236> WL_O<235> WL_O<234> ++ WL_O<233> WL_O<232> WL_O<231> WL_O<230> WL_O<229> WL_O<228> WL_O<227> ++ WL_O<226> WL_O<225> WL_O<224> WL_O<223> WL_O<222> WL_O<221> WL_O<220> ++ WL_O<219> WL_O<218> WL_O<217> WL_O<216> WL_O<215> WL_O<214> WL_O<213> ++ WL_O<212> WL_O<211> WL_O<210> WL_O<209> WL_O<208> WL_O<207> WL_O<206> ++ WL_O<205> WL_O<204> WL_O<203> WL_O<202> WL_O<201> WL_O<200> WL_O<199> ++ WL_O<198> WL_O<197> WL_O<196> WL_O<195> WL_O<194> WL_O<193> WL_O<192> ++ WL_O<191> WL_O<190> WL_O<189> WL_O<188> WL_O<187> WL_O<186> WL_O<185> ++ WL_O<184> WL_O<183> WL_O<182> WL_O<181> WL_O<180> WL_O<179> WL_O<178> ++ WL_O<177> WL_O<176> WL_O<175> WL_O<174> WL_O<173> WL_O<172> WL_O<171> ++ WL_O<170> WL_O<169> WL_O<168> WL_O<167> WL_O<166> WL_O<165> WL_O<164> ++ WL_O<163> WL_O<162> WL_O<161> WL_O<160> WL_O<159> WL_O<158> WL_O<157> ++ WL_O<156> WL_O<155> WL_O<154> WL_O<153> WL_O<152> WL_O<151> WL_O<150> ++ WL_O<149> WL_O<148> WL_O<147> WL_O<146> WL_O<145> WL_O<144> WL_O<143> ++ WL_O<142> WL_O<141> WL_O<140> WL_O<139> WL_O<138> WL_O<137> WL_O<136> ++ WL_O<135> WL_O<134> WL_O<133> WL_O<132> WL_O<131> WL_O<130> WL_O<129> ++ WL_O<128> WL_O<127> WL_O<126> WL_O<125> WL_O<124> WL_O<123> WL_O<122> ++ WL_O<121> WL_O<120> WL_O<119> WL_O<118> WL_O<117> WL_O<116> WL_O<115> ++ WL_O<114> WL_O<113> WL_O<112> WL_O<111> WL_O<110> WL_O<109> WL_O<108> ++ WL_O<107> WL_O<106> WL_O<105> WL_O<104> WL_O<103> WL_O<102> WL_O<101> ++ WL_O<100> WL_O<99> WL_O<98> WL_O<97> WL_O<96> WL_O<95> WL_O<94> WL_O<93> ++ WL_O<92> WL_O<91> WL_O<90> WL_O<89> WL_O<88> WL_O<87> WL_O<86> WL_O<85> ++ WL_O<84> WL_O<83> WL_O<82> WL_O<81> WL_O<80> WL_O<79> WL_O<78> WL_O<77> ++ WL_O<76> WL_O<75> WL_O<74> WL_O<73> WL_O<72> WL_O<71> WL_O<70> WL_O<69> ++ WL_O<68> WL_O<67> WL_O<66> WL_O<65> WL_O<64> WL_O<63> WL_O<62> WL_O<61> ++ WL_O<60> WL_O<59> WL_O<58> WL_O<57> WL_O<56> WL_O<55> WL_O<54> WL_O<53> ++ WL_O<52> WL_O<51> WL_O<50> WL_O<49> WL_O<48> WL_O<47> WL_O<46> WL_O<45> ++ WL_O<44> WL_O<43> WL_O<42> WL_O<41> WL_O<40> WL_O<39> WL_O<38> WL_O<37> ++ WL_O<36> WL_O<35> WL_O<34> WL_O<33> WL_O<32> WL_O<31> WL_O<30> WL_O<29> ++ WL_O<28> WL_O<27> WL_O<26> WL_O<25> WL_O<24> WL_O<23> WL_O<22> WL_O<21> ++ WL_O<20> WL_O<19> WL_O<18> WL_O<17> WL_O<16> WL_O<15> WL_O<14> WL_O<13> ++ WL_O<12> WL_O<11> WL_O<10> WL_O<9> WL_O<8> WL_O<7> WL_O<6> WL_O<5> WL_O<4> ++ WL_O<3> WL_O<2> WL_O<1> WL_O<0> VDD VSS +XDEC11<4> ADDR_N_I<7> ADDR_N_I<6> CS_I CS04<3> VDD VSS / ++ RM_IHPSG13_512x16_c2_1P_DEC03 +XDEC11<3> ADDR_N_I<5> ADDR_N_I<4> CS04<3> CS00<15> VDD VSS / ++ RM_IHPSG13_512x16_c2_1P_DEC03 +XDEC11<2> ADDR_N_I<5> ADDR_N_I<4> CS04<2> CS00<11> VDD VSS / ++ RM_IHPSG13_512x16_c2_1P_DEC03 +XDEC11<1> ADDR_N_I<5> ADDR_N_I<4> CS04<1> CS00<7> VDD VSS / ++ RM_IHPSG13_512x16_c2_1P_DEC03 +XDEC11<0> ADDR_N_I<5> ADDR_N_I<4> CS04<0> CS00<3> VDD VSS / ++ RM_IHPSG13_512x16_c2_1P_DEC03 +XL2<88> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<87> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<86> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<85> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<84> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<83> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<82> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<81> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<80> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<79> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<78> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<77> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<76> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<75> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<74> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<73> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<72> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<71> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<70> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<69> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<68> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<67> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<66> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<65> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<64> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<63> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<62> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<61> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<60> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<59> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<58> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<57> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<56> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<55> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<54> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<53> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<52> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<51> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<50> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<49> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<48> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<47> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<46> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<45> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<44> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<43> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<42> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<41> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<40> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<39> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<38> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<37> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<36> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<35> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<34> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<33> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<32> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<31> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<30> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<29> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<28> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<27> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<26> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<25> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<24> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<23> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<22> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<21> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<20> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<19> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<18> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<17> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<16> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<15> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<14> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<13> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<12> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<11> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<10> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<9> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<8> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<7> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<6> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<5> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<4> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<3> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<2> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<1> VDD VSS / RSC_IHPSG13_FILLCAP8 +XDEC10<4> ADDR_N_I<7> ADDR_N_I<6> CS_I CS04<2> VDD VSS / ++ RM_IHPSG13_512x16_c2_1P_DEC02 +XDEC10<3> ADDR_N_I<5> ADDR_N_I<4> CS04<3> CS00<14> VDD VSS / ++ RM_IHPSG13_512x16_c2_1P_DEC02 +XDEC10<2> ADDR_N_I<5> ADDR_N_I<4> CS04<2> CS00<10> VDD VSS / ++ RM_IHPSG13_512x16_c2_1P_DEC02 +XDEC10<1> ADDR_N_I<5> ADDR_N_I<4> CS04<1> CS00<6> VDD VSS / ++ RM_IHPSG13_512x16_c2_1P_DEC02 +XDEC10<0> ADDR_N_I<5> ADDR_N_I<4> CS04<0> CS00<2> VDD VSS / ++ RM_IHPSG13_512x16_c2_1P_DEC02 +XDEC00<4> ADDR_N_I<7> ADDR_N_I<6> CS_I CS04<0> VDD VSS / ++ RM_IHPSG13_512x16_c2_1P_DEC00 +XDEC00<3> ADDR_N_I<5> ADDR_N_I<4> CS04<3> CS00<12> VDD VSS / ++ RM_IHPSG13_512x16_c2_1P_DEC00 +XDEC00<2> ADDR_N_I<5> ADDR_N_I<4> CS04<2> CS00<8> VDD VSS / ++ RM_IHPSG13_512x16_c2_1P_DEC00 +XDEC00<1> ADDR_N_I<5> ADDR_N_I<4> CS04<1> CS00<4> VDD VSS / ++ RM_IHPSG13_512x16_c2_1P_DEC00 +XDEC00<0> ADDR_N_I<5> ADDR_N_I<4> CS04<0> CS00<0> VDD VSS / ++ RM_IHPSG13_512x16_c2_1P_DEC00 +XSEL<15> ADDR_N_I<3> ADDR_N_I<2> ADDR_N_I<1> ADDR_N_I<0> CS00<15> ECLK_H<15> ++ ECLK_H<16> ECLK_B<15> ECLK_B<16> WL_O<255> WL_O<254> WL_O<253> WL_O<252> ++ WL_O<251> WL_O<250> WL_O<249> WL_O<248> WL_O<247> WL_O<246> WL_O<245> ++ WL_O<244> WL_O<243> WL_O<242> WL_O<241> WL_O<240> VDD VSS / ++ RM_IHPSG13_512x16_c2_1P_DEC04 +XSEL<14> ADDR_N_I<3> ADDR_N_I<2> ADDR_N_I<1> ADDR_N_I<0> CS00<14> ECLK_H<14> ++ ECLK_H<15> ECLK_B<14> ECLK_B<15> WL_O<239> WL_O<238> WL_O<237> WL_O<236> ++ WL_O<235> WL_O<234> WL_O<233> WL_O<232> WL_O<231> WL_O<230> WL_O<229> ++ WL_O<228> WL_O<227> WL_O<226> WL_O<225> WL_O<224> VDD VSS / ++ RM_IHPSG13_512x16_c2_1P_DEC04 +XSEL<13> ADDR_N_I<3> ADDR_N_I<2> ADDR_N_I<1> ADDR_N_I<0> CS00<13> ECLK_H<13> ++ ECLK_H<14> ECLK_B<13> ECLK_B<14> WL_O<223> WL_O<222> WL_O<221> WL_O<220> ++ WL_O<219> WL_O<218> WL_O<217> WL_O<216> WL_O<215> WL_O<214> WL_O<213> ++ WL_O<212> WL_O<211> WL_O<210> WL_O<209> WL_O<208> VDD VSS / ++ RM_IHPSG13_512x16_c2_1P_DEC04 +XSEL<12> ADDR_N_I<3> ADDR_N_I<2> ADDR_N_I<1> ADDR_N_I<0> CS00<12> ECLK_H<12> ++ ECLK_H<13> ECLK_B<12> ECLK_B<13> WL_O<207> WL_O<206> WL_O<205> WL_O<204> ++ WL_O<203> WL_O<202> WL_O<201> WL_O<200> WL_O<199> WL_O<198> WL_O<197> ++ WL_O<196> WL_O<195> WL_O<194> WL_O<193> WL_O<192> VDD VSS / ++ RM_IHPSG13_512x16_c2_1P_DEC04 +XSEL<11> ADDR_N_I<3> ADDR_N_I<2> ADDR_N_I<1> ADDR_N_I<0> CS00<11> ECLK_H<11> ++ ECLK_H<12> ECLK_B<11> ECLK_B<12> WL_O<191> WL_O<190> WL_O<189> WL_O<188> ++ WL_O<187> WL_O<186> WL_O<185> WL_O<184> WL_O<183> WL_O<182> WL_O<181> ++ WL_O<180> WL_O<179> WL_O<178> WL_O<177> WL_O<176> VDD VSS / ++ RM_IHPSG13_512x16_c2_1P_DEC04 +XSEL<10> ADDR_N_I<3> ADDR_N_I<2> ADDR_N_I<1> ADDR_N_I<0> CS00<10> ECLK_H<10> ++ ECLK_H<11> ECLK_B<10> ECLK_B<11> WL_O<175> WL_O<174> WL_O<173> WL_O<172> ++ WL_O<171> WL_O<170> WL_O<169> WL_O<168> WL_O<167> WL_O<166> WL_O<165> ++ WL_O<164> WL_O<163> WL_O<162> WL_O<161> WL_O<160> VDD VSS / ++ RM_IHPSG13_512x16_c2_1P_DEC04 +XSEL<9> ADDR_N_I<3> ADDR_N_I<2> ADDR_N_I<1> ADDR_N_I<0> CS00<9> ECLK_H<9> ++ ECLK_H<10> ECLK_B<9> ECLK_B<10> WL_O<159> WL_O<158> WL_O<157> WL_O<156> ++ WL_O<155> WL_O<154> WL_O<153> WL_O<152> WL_O<151> WL_O<150> WL_O<149> ++ WL_O<148> WL_O<147> WL_O<146> WL_O<145> WL_O<144> VDD VSS / ++ RM_IHPSG13_512x16_c2_1P_DEC04 +XSEL<8> ADDR_N_I<3> ADDR_N_I<2> ADDR_N_I<1> ADDR_N_I<0> CS00<8> ECLK_H<8> ++ ECLK_H<9> ECLK_B<8> ECLK_B<9> WL_O<143> WL_O<142> WL_O<141> WL_O<140> ++ WL_O<139> WL_O<138> WL_O<137> WL_O<136> WL_O<135> WL_O<134> WL_O<133> ++ WL_O<132> WL_O<131> WL_O<130> WL_O<129> WL_O<128> VDD VSS / ++ RM_IHPSG13_512x16_c2_1P_DEC04 +XSEL<7> ADDR_N_I<3> ADDR_N_I<2> ADDR_N_I<1> ADDR_N_I<0> CS00<7> ECLK_H<7> ++ ECLK_H<8> ECLK_B<7> ECLK_B<8> WL_O<127> WL_O<126> WL_O<125> WL_O<124> ++ WL_O<123> WL_O<122> WL_O<121> WL_O<120> WL_O<119> WL_O<118> WL_O<117> ++ WL_O<116> WL_O<115> WL_O<114> WL_O<113> WL_O<112> VDD VSS / ++ RM_IHPSG13_512x16_c2_1P_DEC04 +XSEL<6> ADDR_N_I<3> ADDR_N_I<2> ADDR_N_I<1> ADDR_N_I<0> CS00<6> ECLK_H<6> ++ ECLK_H<7> ECLK_B<6> ECLK_B<7> WL_O<111> WL_O<110> WL_O<109> WL_O<108> ++ WL_O<107> WL_O<106> WL_O<105> WL_O<104> WL_O<103> WL_O<102> WL_O<101> ++ WL_O<100> WL_O<99> WL_O<98> WL_O<97> WL_O<96> VDD VSS / ++ RM_IHPSG13_512x16_c2_1P_DEC04 +XSEL<5> ADDR_N_I<3> ADDR_N_I<2> ADDR_N_I<1> ADDR_N_I<0> CS00<5> ECLK_H<5> ++ ECLK_H<6> ECLK_B<5> ECLK_B<6> WL_O<95> WL_O<94> WL_O<93> WL_O<92> WL_O<91> ++ WL_O<90> WL_O<89> WL_O<88> WL_O<87> WL_O<86> WL_O<85> WL_O<84> WL_O<83> ++ WL_O<82> WL_O<81> WL_O<80> VDD VSS / RM_IHPSG13_512x16_c2_1P_DEC04 +XSEL<4> ADDR_N_I<3> ADDR_N_I<2> ADDR_N_I<1> ADDR_N_I<0> CS00<4> ECLK_H<4> ++ ECLK_H<5> ECLK_B<4> ECLK_B<5> WL_O<79> WL_O<78> WL_O<77> WL_O<76> WL_O<75> ++ WL_O<74> WL_O<73> WL_O<72> WL_O<71> WL_O<70> WL_O<69> WL_O<68> WL_O<67> ++ WL_O<66> WL_O<65> WL_O<64> VDD VSS / RM_IHPSG13_512x16_c2_1P_DEC04 +XSEL<3> ADDR_N_I<3> ADDR_N_I<2> ADDR_N_I<1> ADDR_N_I<0> CS00<3> ECLK_H<3> ++ ECLK_H<4> ECLK_B<3> ECLK_B<4> WL_O<63> WL_O<62> WL_O<61> WL_O<60> WL_O<59> ++ WL_O<58> WL_O<57> WL_O<56> WL_O<55> WL_O<54> WL_O<53> WL_O<52> WL_O<51> ++ WL_O<50> WL_O<49> WL_O<48> VDD VSS / RM_IHPSG13_512x16_c2_1P_DEC04 +XSEL<2> ADDR_N_I<3> ADDR_N_I<2> ADDR_N_I<1> ADDR_N_I<0> CS00<2> ECLK_H<2> ++ ECLK_H<3> ECLK_B<2> ECLK_B<3> WL_O<47> WL_O<46> WL_O<45> WL_O<44> WL_O<43> ++ WL_O<42> WL_O<41> WL_O<40> WL_O<39> WL_O<38> WL_O<37> WL_O<36> WL_O<35> ++ WL_O<34> WL_O<33> WL_O<32> VDD VSS / RM_IHPSG13_512x16_c2_1P_DEC04 +XSEL<1> ADDR_N_I<3> ADDR_N_I<2> ADDR_N_I<1> ADDR_N_I<0> CS00<1> ECLK_H<1> ++ ECLK_H<2> ECLK_B<1> ECLK_B<2> WL_O<31> WL_O<30> WL_O<29> WL_O<28> WL_O<27> ++ WL_O<26> WL_O<25> WL_O<24> WL_O<23> WL_O<22> WL_O<21> WL_O<20> WL_O<19> ++ WL_O<18> WL_O<17> WL_O<16> VDD VSS / RM_IHPSG13_512x16_c2_1P_DEC04 +XSEL<0> ADDR_N_I<3> ADDR_N_I<2> ADDR_N_I<1> ADDR_N_I<0> CS00<0> ECLK_I ++ ECLK_H<1> ECLK_B<0> ECLK_B<1> WL_O<15> WL_O<14> WL_O<13> WL_O<12> WL_O<11> ++ WL_O<10> WL_O<9> WL_O<8> WL_O<7> WL_O<6> WL_O<5> WL_O<4> WL_O<3> WL_O<2> ++ WL_O<1> WL_O<0> VDD VSS / RM_IHPSG13_512x16_c2_1P_DEC04 +XDEC01<4> ADDR_N_I<7> ADDR_N_I<6> CS_I CS04<1> VDD VSS / ++ RM_IHPSG13_512x16_c2_1P_DEC01 +XDEC01<3> ADDR_N_I<5> ADDR_N_I<4> CS04<3> CS00<13> VDD VSS / ++ RM_IHPSG13_512x16_c2_1P_DEC01 +XDEC01<2> ADDR_N_I<5> ADDR_N_I<4> CS04<2> CS00<9> VDD VSS / ++ RM_IHPSG13_512x16_c2_1P_DEC01 +XDEC01<1> ADDR_N_I<5> ADDR_N_I<4> CS04<1> CS00<5> VDD VSS / ++ RM_IHPSG13_512x16_c2_1P_DEC01 +XDEC01<0> ADDR_N_I<5> ADDR_N_I<4> CS04<0> CS00<1> VDD VSS / ++ RM_IHPSG13_512x16_c2_1P_DEC01 +.ENDS +.SUBCKT RM_IHPSG13_512x16_c2_1P_ROWREG8 ACLK_N_I ADDR_I<7> ADDR_I<6> ADDR_I<5> ADDR_I<4> ++ ADDR_I<3> ADDR_I<2> ADDR_I<1> ADDR_I<0> ADDR_N_O<7> ADDR_N_O<6> ADDR_N_O<5> ++ ADDR_N_O<4> ADDR_N_O<3> ADDR_N_O<2> ADDR_N_O<1> ADDR_N_O<0> BIST_ADDR_I<7> ++ BIST_ADDR_I<6> BIST_ADDR_I<5> BIST_ADDR_I<4> BIST_ADDR_I<3> BIST_ADDR_I<2> ++ BIST_ADDR_I<1> BIST_ADDR_I<0> BIST_EN_I VDD VSS +XINV<7> q_int<7> qn_int<7> VDD VSS / RSC_IHPSG13_CINVX2 +XINV<6> q_int<6> qn_int<6> VDD VSS / RSC_IHPSG13_CINVX2 +XINV<5> q_int<5> qn_int<5> VDD VSS / RSC_IHPSG13_CINVX2 +XINV<4> q_int<4> qn_int<4> VDD VSS / RSC_IHPSG13_CINVX2 +XINV<3> q_int<3> qn_int<3> VDD VSS / RSC_IHPSG13_CINVX2 +XINV<2> q_int<2> qn_int<2> VDD VSS / RSC_IHPSG13_CINVX2 +XINV<1> q_int<1> qn_int<1> VDD VSS / RSC_IHPSG13_CINVX2 +XINV<0> q_int<0> qn_int<0> VDD VSS / RSC_IHPSG13_CINVX2 +XDRV<7> qn_int<7> ADDR_N_O<7> VDD VSS / RSC_IHPSG13_CINVX8 +XDRV<6> qn_int<6> ADDR_N_O<6> VDD VSS / RSC_IHPSG13_CINVX8 +XDRV<5> qn_int<5> ADDR_N_O<5> VDD VSS / RSC_IHPSG13_CINVX8 +XDRV<4> qn_int<4> ADDR_N_O<4> VDD VSS / RSC_IHPSG13_CINVX8 +XDRV<3> qn_int<3> ADDR_N_O<3> VDD VSS / RSC_IHPSG13_CINVX8 +XDRV<2> qn_int<2> ADDR_N_O<2> VDD VSS / RSC_IHPSG13_CINVX8 +XDRV<1> qn_int<1> ADDR_N_O<1> VDD VSS / RSC_IHPSG13_CINVX8 +XDRV<0> qn_int<0> ADDR_N_O<0> VDD VSS / RSC_IHPSG13_CINVX8 +XDFF<7> BIST_EN_I BIST_ADDR_I<7> ACLK_N_I ADDR_I<7> q_int<7> net2<0> VDD ++ VSS / RSC_IHPSG13_DFNQMX2IX1 +XDFF<6> BIST_EN_I BIST_ADDR_I<6> ACLK_N_I ADDR_I<6> q_int<6> net2<1> VDD ++ VSS / RSC_IHPSG13_DFNQMX2IX1 +XDFF<5> BIST_EN_I BIST_ADDR_I<5> ACLK_N_I ADDR_I<5> q_int<5> net2<2> VDD ++ VSS / RSC_IHPSG13_DFNQMX2IX1 +XDFF<4> BIST_EN_I BIST_ADDR_I<4> ACLK_N_I ADDR_I<4> q_int<4> net2<3> VDD ++ VSS / RSC_IHPSG13_DFNQMX2IX1 +XDFF<3> BIST_EN_I BIST_ADDR_I<3> ACLK_N_I ADDR_I<3> q_int<3> net2<4> VDD ++ VSS / RSC_IHPSG13_DFNQMX2IX1 +XDFF<2> BIST_EN_I BIST_ADDR_I<2> ACLK_N_I ADDR_I<2> q_int<2> net2<5> VDD ++ VSS / RSC_IHPSG13_DFNQMX2IX1 +XDFF<1> BIST_EN_I BIST_ADDR_I<1> ACLK_N_I ADDR_I<1> q_int<1> net2<6> VDD ++ VSS / RSC_IHPSG13_DFNQMX2IX1 +XDFF<0> BIST_EN_I BIST_ADDR_I<0> ACLK_N_I ADDR_I<0> q_int<0> net2<7> VDD ++ VSS / RSC_IHPSG13_DFNQMX2IX1 +XI11<4> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI11<3> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI11<2> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI11<1> VDD VSS / RSC_IHPSG13_FILLCAP8 +.ENDS + +.SUBCKT RM_IHPSG13_512x16_c2_1P_ROWDEC9 ADDR_N_I<8> ADDR_N_I<7> ADDR_N_I<6> ADDR_N_I<5> ++ ADDR_N_I<4> ADDR_N_I<3> ADDR_N_I<2> ADDR_N_I<1> ADDR_N_I<0> CS_I ECLK_I ++ WL_O<511> WL_O<510> WL_O<509> WL_O<508> WL_O<507> WL_O<506> WL_O<505> ++ WL_O<504> WL_O<503> WL_O<502> WL_O<501> WL_O<500> WL_O<499> WL_O<498> ++ WL_O<497> WL_O<496> WL_O<495> WL_O<494> WL_O<493> WL_O<492> WL_O<491> ++ WL_O<490> WL_O<489> WL_O<488> WL_O<487> WL_O<486> WL_O<485> WL_O<484> ++ WL_O<483> WL_O<482> WL_O<481> WL_O<480> WL_O<479> WL_O<478> WL_O<477> ++ WL_O<476> WL_O<475> WL_O<474> WL_O<473> WL_O<472> WL_O<471> WL_O<470> ++ WL_O<469> WL_O<468> WL_O<467> WL_O<466> WL_O<465> WL_O<464> WL_O<463> ++ WL_O<462> WL_O<461> WL_O<460> WL_O<459> WL_O<458> WL_O<457> WL_O<456> ++ WL_O<455> WL_O<454> WL_O<453> WL_O<452> WL_O<451> WL_O<450> WL_O<449> ++ WL_O<448> WL_O<447> WL_O<446> WL_O<445> WL_O<444> WL_O<443> WL_O<442> ++ WL_O<441> WL_O<440> WL_O<439> WL_O<438> WL_O<437> WL_O<436> WL_O<435> ++ WL_O<434> WL_O<433> WL_O<432> WL_O<431> WL_O<430> WL_O<429> WL_O<428> ++ WL_O<427> WL_O<426> WL_O<425> WL_O<424> WL_O<423> WL_O<422> WL_O<421> ++ WL_O<420> WL_O<419> WL_O<418> WL_O<417> WL_O<416> WL_O<415> WL_O<414> ++ WL_O<413> WL_O<412> WL_O<411> WL_O<410> WL_O<409> WL_O<408> WL_O<407> ++ WL_O<406> WL_O<405> WL_O<404> WL_O<403> WL_O<402> WL_O<401> WL_O<400> ++ WL_O<399> WL_O<398> WL_O<397> WL_O<396> WL_O<395> WL_O<394> WL_O<393> ++ WL_O<392> WL_O<391> WL_O<390> WL_O<389> WL_O<388> WL_O<387> WL_O<386> ++ WL_O<385> WL_O<384> WL_O<383> WL_O<382> WL_O<381> WL_O<380> WL_O<379> ++ WL_O<378> WL_O<377> WL_O<376> WL_O<375> WL_O<374> WL_O<373> WL_O<372> ++ WL_O<371> WL_O<370> WL_O<369> WL_O<368> WL_O<367> WL_O<366> WL_O<365> ++ WL_O<364> WL_O<363> WL_O<362> WL_O<361> WL_O<360> WL_O<359> WL_O<358> ++ WL_O<357> WL_O<356> WL_O<355> WL_O<354> WL_O<353> WL_O<352> WL_O<351> ++ WL_O<350> WL_O<349> WL_O<348> WL_O<347> WL_O<346> WL_O<345> WL_O<344> ++ WL_O<343> WL_O<342> WL_O<341> WL_O<340> WL_O<339> WL_O<338> WL_O<337> ++ WL_O<336> WL_O<335> WL_O<334> WL_O<333> WL_O<332> WL_O<331> WL_O<330> ++ WL_O<329> WL_O<328> WL_O<327> WL_O<326> WL_O<325> WL_O<324> WL_O<323> ++ WL_O<322> WL_O<321> WL_O<320> WL_O<319> WL_O<318> WL_O<317> WL_O<316> ++ WL_O<315> WL_O<314> WL_O<313> WL_O<312> WL_O<311> WL_O<310> WL_O<309> ++ WL_O<308> WL_O<307> WL_O<306> WL_O<305> WL_O<304> WL_O<303> WL_O<302> ++ WL_O<301> WL_O<300> WL_O<299> WL_O<298> WL_O<297> WL_O<296> WL_O<295> ++ WL_O<294> WL_O<293> WL_O<292> WL_O<291> WL_O<290> WL_O<289> WL_O<288> ++ WL_O<287> WL_O<286> WL_O<285> WL_O<284> WL_O<283> WL_O<282> WL_O<281> ++ WL_O<280> WL_O<279> WL_O<278> WL_O<277> WL_O<276> WL_O<275> WL_O<274> ++ WL_O<273> WL_O<272> WL_O<271> WL_O<270> WL_O<269> WL_O<268> WL_O<267> ++ WL_O<266> WL_O<265> WL_O<264> WL_O<263> WL_O<262> WL_O<261> WL_O<260> ++ WL_O<259> WL_O<258> WL_O<257> WL_O<256> WL_O<255> WL_O<254> WL_O<253> ++ WL_O<252> WL_O<251> WL_O<250> WL_O<249> WL_O<248> WL_O<247> WL_O<246> ++ WL_O<245> WL_O<244> WL_O<243> WL_O<242> WL_O<241> WL_O<240> WL_O<239> ++ WL_O<238> WL_O<237> WL_O<236> WL_O<235> WL_O<234> WL_O<233> WL_O<232> ++ WL_O<231> WL_O<230> WL_O<229> WL_O<228> WL_O<227> WL_O<226> WL_O<225> ++ WL_O<224> WL_O<223> WL_O<222> WL_O<221> WL_O<220> WL_O<219> WL_O<218> ++ WL_O<217> WL_O<216> WL_O<215> WL_O<214> WL_O<213> WL_O<212> WL_O<211> ++ WL_O<210> WL_O<209> WL_O<208> WL_O<207> WL_O<206> WL_O<205> WL_O<204> ++ WL_O<203> WL_O<202> WL_O<201> WL_O<200> WL_O<199> WL_O<198> WL_O<197> ++ WL_O<196> WL_O<195> WL_O<194> WL_O<193> WL_O<192> WL_O<191> WL_O<190> ++ WL_O<189> WL_O<188> WL_O<187> WL_O<186> WL_O<185> WL_O<184> WL_O<183> ++ WL_O<182> WL_O<181> WL_O<180> WL_O<179> WL_O<178> WL_O<177> WL_O<176> ++ WL_O<175> WL_O<174> WL_O<173> WL_O<172> WL_O<171> WL_O<170> WL_O<169> ++ WL_O<168> WL_O<167> WL_O<166> WL_O<165> WL_O<164> WL_O<163> WL_O<162> ++ WL_O<161> WL_O<160> WL_O<159> WL_O<158> WL_O<157> WL_O<156> WL_O<155> ++ WL_O<154> WL_O<153> WL_O<152> WL_O<151> WL_O<150> WL_O<149> WL_O<148> ++ WL_O<147> WL_O<146> WL_O<145> WL_O<144> WL_O<143> WL_O<142> WL_O<141> ++ WL_O<140> WL_O<139> WL_O<138> WL_O<137> WL_O<136> WL_O<135> WL_O<134> ++ WL_O<133> WL_O<132> WL_O<131> WL_O<130> WL_O<129> WL_O<128> WL_O<127> ++ WL_O<126> WL_O<125> WL_O<124> WL_O<123> WL_O<122> WL_O<121> WL_O<120> ++ WL_O<119> WL_O<118> WL_O<117> WL_O<116> WL_O<115> WL_O<114> WL_O<113> ++ WL_O<112> WL_O<111> WL_O<110> WL_O<109> WL_O<108> WL_O<107> WL_O<106> ++ WL_O<105> WL_O<104> WL_O<103> WL_O<102> WL_O<101> WL_O<100> WL_O<99> ++ WL_O<98> WL_O<97> WL_O<96> WL_O<95> WL_O<94> WL_O<93> WL_O<92> WL_O<91> ++ WL_O<90> WL_O<89> WL_O<88> WL_O<87> WL_O<86> WL_O<85> WL_O<84> WL_O<83> ++ WL_O<82> WL_O<81> WL_O<80> WL_O<79> WL_O<78> WL_O<77> WL_O<76> WL_O<75> ++ WL_O<74> WL_O<73> WL_O<72> WL_O<71> WL_O<70> WL_O<69> WL_O<68> WL_O<67> ++ WL_O<66> WL_O<65> WL_O<64> WL_O<63> WL_O<62> WL_O<61> WL_O<60> WL_O<59> ++ WL_O<58> WL_O<57> WL_O<56> WL_O<55> WL_O<54> WL_O<53> WL_O<52> WL_O<51> ++ WL_O<50> WL_O<49> WL_O<48> WL_O<47> WL_O<46> WL_O<45> WL_O<44> WL_O<43> ++ WL_O<42> WL_O<41> WL_O<40> WL_O<39> WL_O<38> WL_O<37> WL_O<36> WL_O<35> ++ WL_O<34> WL_O<33> WL_O<32> WL_O<31> WL_O<30> WL_O<29> WL_O<28> WL_O<27> ++ WL_O<26> WL_O<25> WL_O<24> WL_O<23> WL_O<22> WL_O<21> WL_O<20> WL_O<19> ++ WL_O<18> WL_O<17> WL_O<16> WL_O<15> WL_O<14> WL_O<13> WL_O<12> WL_O<11> ++ WL_O<10> WL_O<9> WL_O<8> WL_O<7> WL_O<6> WL_O<5> WL_O<4> WL_O<3> WL_O<2> ++ WL_O<1> WL_O<0> VDD VSS +XL2<172> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<171> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<170> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<169> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<168> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<167> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<166> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<165> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<164> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<163> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<162> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<161> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<160> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<159> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<158> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<157> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<156> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<155> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<154> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<153> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<152> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<151> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<150> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<149> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<148> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<147> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<146> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<145> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<144> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<143> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<142> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<141> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<140> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<139> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<138> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<137> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<136> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<135> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<134> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<133> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<132> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<131> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<130> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<129> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<128> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<127> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<126> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<125> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<124> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<123> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<122> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<121> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<120> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<119> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<118> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<117> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<116> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<115> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<114> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<113> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<112> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<111> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<110> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<109> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<108> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<107> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<106> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<105> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<104> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<103> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<102> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<101> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<100> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<99> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<98> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<97> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<96> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<95> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<94> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<93> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<92> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<91> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<90> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<89> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<88> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<87> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<86> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<85> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<84> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<83> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<82> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<81> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<80> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<79> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<78> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<77> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<76> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<75> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<74> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<73> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<72> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<71> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<70> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<69> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<68> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<67> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<66> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<65> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<64> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<63> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<62> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<61> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<60> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<59> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<58> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<57> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<56> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<55> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<54> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<53> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<52> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<51> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<50> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<49> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<48> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<47> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<46> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<45> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<44> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<43> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<42> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<41> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<40> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<39> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<38> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<37> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<36> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<35> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<34> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<33> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<32> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<31> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<30> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<29> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<28> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<27> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<26> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<25> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<24> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<23> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<22> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<21> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<20> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<19> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<18> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<17> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<16> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<15> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<14> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<13> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<12> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<11> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<10> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<9> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<8> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<7> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<6> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<5> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<4> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<3> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<2> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<1> VDD VSS / RSC_IHPSG13_FILLCAP8 +XDEC11<9> ADDR_N_I<7> ADDR_N_I<6> CS04<1> CS02<7> VDD VSS / ++ RM_IHPSG13_512x16_c2_1P_DEC03 +XDEC11<8> ADDR_N_I<7> ADDR_N_I<6> CS04<0> CS02<3> VDD VSS / ++ RM_IHPSG13_512x16_c2_1P_DEC03 +XDEC11<7> ADDR_N_I<5> ADDR_N_I<4> CS02<7> CS00<31> VDD VSS / ++ RM_IHPSG13_512x16_c2_1P_DEC03 +XDEC11<6> ADDR_N_I<5> ADDR_N_I<4> CS02<6> CS00<27> VDD VSS / ++ RM_IHPSG13_512x16_c2_1P_DEC03 +XDEC11<5> ADDR_N_I<5> ADDR_N_I<4> CS02<5> CS00<23> VDD VSS / ++ RM_IHPSG13_512x16_c2_1P_DEC03 +XDEC11<4> ADDR_N_I<5> ADDR_N_I<4> CS02<4> CS00<19> VDD VSS / ++ RM_IHPSG13_512x16_c2_1P_DEC03 +XDEC11<3> ADDR_N_I<5> ADDR_N_I<4> CS02<3> CS00<15> VDD VSS / ++ RM_IHPSG13_512x16_c2_1P_DEC03 +XDEC11<2> ADDR_N_I<5> ADDR_N_I<4> CS02<2> CS00<11> VDD VSS / ++ RM_IHPSG13_512x16_c2_1P_DEC03 +XDEC11<1> ADDR_N_I<5> ADDR_N_I<4> CS02<1> CS00<7> VDD VSS / ++ RM_IHPSG13_512x16_c2_1P_DEC03 +XDEC11<0> ADDR_N_I<5> ADDR_N_I<4> CS02<0> CS00<3> VDD VSS / ++ RM_IHPSG13_512x16_c2_1P_DEC03 +XDEC00<10> ADDR_N_I<9> ADDR_N_I<8> CS_I CS04<0> VDD VSS / ++ RM_IHPSG13_512x16_c2_1P_DEC00 +XDEC00<9> ADDR_N_I<7> ADDR_N_I<6> CS04<1> CS02<4> VDD VSS / ++ RM_IHPSG13_512x16_c2_1P_DEC00 +XDEC00<8> ADDR_N_I<7> ADDR_N_I<6> CS04<0> CS02<0> VDD VSS / ++ RM_IHPSG13_512x16_c2_1P_DEC00 +XDEC00<7> ADDR_N_I<5> ADDR_N_I<4> CS02<7> CS00<28> VDD VSS / ++ RM_IHPSG13_512x16_c2_1P_DEC00 +XDEC00<6> ADDR_N_I<5> ADDR_N_I<4> CS02<6> CS00<24> VDD VSS / ++ RM_IHPSG13_512x16_c2_1P_DEC00 +XDEC00<5> ADDR_N_I<5> ADDR_N_I<4> CS02<5> CS00<20> VDD VSS / ++ RM_IHPSG13_512x16_c2_1P_DEC00 +XDEC00<4> ADDR_N_I<5> ADDR_N_I<4> CS02<4> CS00<16> VDD VSS / ++ RM_IHPSG13_512x16_c2_1P_DEC00 +XDEC00<3> ADDR_N_I<5> ADDR_N_I<4> CS02<3> CS00<12> VDD VSS / ++ RM_IHPSG13_512x16_c2_1P_DEC00 +XDEC00<2> ADDR_N_I<5> ADDR_N_I<4> CS02<2> CS00<8> VDD VSS / ++ RM_IHPSG13_512x16_c2_1P_DEC00 +XDEC00<1> ADDR_N_I<5> ADDR_N_I<4> CS02<1> CS00<4> VDD VSS / ++ RM_IHPSG13_512x16_c2_1P_DEC00 +XDEC00<0> ADDR_N_I<5> ADDR_N_I<4> CS02<0> CS00<0> VDD VSS / ++ RM_IHPSG13_512x16_c2_1P_DEC00 +XSEL<31> ADDR_N_I<3> ADDR_N_I<2> ADDR_N_I<1> ADDR_N_I<0> CS00<31> ECLK_H<31> ++ ECLK_H<32> ECLK_B<31> ECLK_B<32> WL_O<511> WL_O<510> WL_O<509> WL_O<508> ++ WL_O<507> WL_O<506> WL_O<505> WL_O<504> WL_O<503> WL_O<502> WL_O<501> ++ WL_O<500> WL_O<499> WL_O<498> WL_O<497> WL_O<496> VDD VSS / ++ RM_IHPSG13_512x16_c2_1P_DEC04 +XSEL<30> ADDR_N_I<3> ADDR_N_I<2> ADDR_N_I<1> ADDR_N_I<0> CS00<30> ECLK_H<30> ++ ECLK_H<31> ECLK_B<30> ECLK_B<31> WL_O<495> WL_O<494> WL_O<493> WL_O<492> ++ WL_O<491> WL_O<490> WL_O<489> WL_O<488> WL_O<487> WL_O<486> WL_O<485> ++ WL_O<484> WL_O<483> WL_O<482> WL_O<481> WL_O<480> VDD VSS / ++ RM_IHPSG13_512x16_c2_1P_DEC04 +XSEL<29> ADDR_N_I<3> ADDR_N_I<2> ADDR_N_I<1> ADDR_N_I<0> CS00<29> ECLK_H<29> ++ ECLK_H<30> ECLK_B<29> ECLK_B<30> WL_O<479> WL_O<478> WL_O<477> WL_O<476> ++ WL_O<475> WL_O<474> WL_O<473> WL_O<472> WL_O<471> WL_O<470> WL_O<469> ++ WL_O<468> WL_O<467> WL_O<466> WL_O<465> WL_O<464> VDD VSS / ++ RM_IHPSG13_512x16_c2_1P_DEC04 +XSEL<28> ADDR_N_I<3> ADDR_N_I<2> ADDR_N_I<1> ADDR_N_I<0> CS00<28> ECLK_H<28> ++ ECLK_H<29> ECLK_B<28> ECLK_B<29> WL_O<463> WL_O<462> WL_O<461> WL_O<460> ++ WL_O<459> WL_O<458> WL_O<457> WL_O<456> WL_O<455> WL_O<454> WL_O<453> ++ WL_O<452> WL_O<451> WL_O<450> WL_O<449> WL_O<448> VDD VSS / ++ RM_IHPSG13_512x16_c2_1P_DEC04 +XSEL<27> ADDR_N_I<3> ADDR_N_I<2> ADDR_N_I<1> ADDR_N_I<0> CS00<27> ECLK_H<27> ++ ECLK_H<28> ECLK_B<27> ECLK_B<28> WL_O<447> WL_O<446> WL_O<445> WL_O<444> ++ WL_O<443> WL_O<442> WL_O<441> WL_O<440> WL_O<439> WL_O<438> WL_O<437> ++ WL_O<436> WL_O<435> WL_O<434> WL_O<433> WL_O<432> VDD VSS / ++ RM_IHPSG13_512x16_c2_1P_DEC04 +XSEL<26> ADDR_N_I<3> ADDR_N_I<2> ADDR_N_I<1> ADDR_N_I<0> CS00<26> ECLK_H<26> ++ ECLK_H<27> ECLK_B<26> ECLK_B<27> WL_O<431> WL_O<430> WL_O<429> WL_O<428> ++ WL_O<427> WL_O<426> WL_O<425> WL_O<424> WL_O<423> WL_O<422> WL_O<421> ++ WL_O<420> WL_O<419> WL_O<418> WL_O<417> WL_O<416> VDD VSS / ++ RM_IHPSG13_512x16_c2_1P_DEC04 +XSEL<25> ADDR_N_I<3> ADDR_N_I<2> ADDR_N_I<1> ADDR_N_I<0> CS00<25> ECLK_H<25> ++ ECLK_H<26> ECLK_B<25> ECLK_B<26> WL_O<415> WL_O<414> WL_O<413> WL_O<412> ++ WL_O<411> WL_O<410> WL_O<409> WL_O<408> WL_O<407> WL_O<406> WL_O<405> ++ WL_O<404> WL_O<403> WL_O<402> WL_O<401> WL_O<400> VDD VSS / ++ RM_IHPSG13_512x16_c2_1P_DEC04 +XSEL<24> ADDR_N_I<3> ADDR_N_I<2> ADDR_N_I<1> ADDR_N_I<0> CS00<24> ECLK_H<24> ++ ECLK_H<25> ECLK_B<24> ECLK_B<25> WL_O<399> WL_O<398> WL_O<397> WL_O<396> ++ WL_O<395> WL_O<394> WL_O<393> WL_O<392> WL_O<391> WL_O<390> WL_O<389> ++ WL_O<388> WL_O<387> WL_O<386> WL_O<385> WL_O<384> VDD VSS / ++ RM_IHPSG13_512x16_c2_1P_DEC04 +XSEL<23> ADDR_N_I<3> ADDR_N_I<2> ADDR_N_I<1> ADDR_N_I<0> CS00<23> ECLK_H<23> ++ ECLK_H<24> ECLK_B<23> ECLK_B<24> WL_O<383> WL_O<382> WL_O<381> WL_O<380> ++ WL_O<379> WL_O<378> WL_O<377> WL_O<376> WL_O<375> WL_O<374> WL_O<373> ++ WL_O<372> WL_O<371> WL_O<370> WL_O<369> WL_O<368> VDD VSS / ++ RM_IHPSG13_512x16_c2_1P_DEC04 +XSEL<22> ADDR_N_I<3> ADDR_N_I<2> ADDR_N_I<1> ADDR_N_I<0> CS00<22> ECLK_H<22> ++ ECLK_H<23> ECLK_B<22> ECLK_B<23> WL_O<367> WL_O<366> WL_O<365> WL_O<364> ++ WL_O<363> WL_O<362> WL_O<361> WL_O<360> WL_O<359> WL_O<358> WL_O<357> ++ WL_O<356> WL_O<355> WL_O<354> WL_O<353> WL_O<352> VDD VSS / ++ RM_IHPSG13_512x16_c2_1P_DEC04 +XSEL<21> ADDR_N_I<3> ADDR_N_I<2> ADDR_N_I<1> ADDR_N_I<0> CS00<21> ECLK_H<21> ++ ECLK_H<22> ECLK_B<21> ECLK_B<22> WL_O<351> WL_O<350> WL_O<349> WL_O<348> ++ WL_O<347> WL_O<346> WL_O<345> WL_O<344> WL_O<343> WL_O<342> WL_O<341> ++ WL_O<340> WL_O<339> WL_O<338> WL_O<337> WL_O<336> VDD VSS / ++ RM_IHPSG13_512x16_c2_1P_DEC04 +XSEL<20> ADDR_N_I<3> ADDR_N_I<2> ADDR_N_I<1> ADDR_N_I<0> CS00<20> ECLK_H<20> ++ ECLK_H<21> ECLK_B<20> ECLK_B<21> WL_O<335> WL_O<334> WL_O<333> WL_O<332> ++ WL_O<331> WL_O<330> WL_O<329> WL_O<328> WL_O<327> WL_O<326> WL_O<325> ++ WL_O<324> WL_O<323> WL_O<322> WL_O<321> WL_O<320> VDD VSS / ++ RM_IHPSG13_512x16_c2_1P_DEC04 +XSEL<19> ADDR_N_I<3> ADDR_N_I<2> ADDR_N_I<1> ADDR_N_I<0> CS00<19> ECLK_H<19> ++ ECLK_H<20> ECLK_B<19> ECLK_B<20> WL_O<319> WL_O<318> WL_O<317> WL_O<316> ++ WL_O<315> WL_O<314> WL_O<313> WL_O<312> WL_O<311> WL_O<310> WL_O<309> ++ WL_O<308> WL_O<307> WL_O<306> WL_O<305> WL_O<304> VDD VSS / ++ RM_IHPSG13_512x16_c2_1P_DEC04 +XSEL<18> ADDR_N_I<3> ADDR_N_I<2> ADDR_N_I<1> ADDR_N_I<0> CS00<18> ECLK_H<18> ++ ECLK_H<19> ECLK_B<18> ECLK_B<19> WL_O<303> WL_O<302> WL_O<301> WL_O<300> ++ WL_O<299> WL_O<298> WL_O<297> WL_O<296> WL_O<295> WL_O<294> WL_O<293> ++ WL_O<292> WL_O<291> WL_O<290> WL_O<289> WL_O<288> VDD VSS / ++ RM_IHPSG13_512x16_c2_1P_DEC04 +XSEL<17> ADDR_N_I<3> ADDR_N_I<2> ADDR_N_I<1> ADDR_N_I<0> CS00<17> ECLK_H<17> ++ ECLK_H<18> ECLK_B<17> ECLK_B<18> WL_O<287> WL_O<286> WL_O<285> WL_O<284> ++ WL_O<283> WL_O<282> WL_O<281> WL_O<280> WL_O<279> WL_O<278> WL_O<277> ++ WL_O<276> WL_O<275> WL_O<274> WL_O<273> WL_O<272> VDD VSS / ++ RM_IHPSG13_512x16_c2_1P_DEC04 +XSEL<16> ADDR_N_I<3> ADDR_N_I<2> ADDR_N_I<1> ADDR_N_I<0> CS00<16> ECLK_H<16> ++ ECLK_H<17> ECLK_B<16> ECLK_B<17> WL_O<271> WL_O<270> WL_O<269> WL_O<268> ++ WL_O<267> WL_O<266> WL_O<265> WL_O<264> WL_O<263> WL_O<262> WL_O<261> ++ WL_O<260> WL_O<259> WL_O<258> WL_O<257> WL_O<256> VDD VSS / ++ RM_IHPSG13_512x16_c2_1P_DEC04 +XSEL<15> ADDR_N_I<3> ADDR_N_I<2> ADDR_N_I<1> ADDR_N_I<0> CS00<15> ECLK_H<15> ++ ECLK_H<16> ECLK_B<15> ECLK_B<16> WL_O<255> WL_O<254> WL_O<253> WL_O<252> ++ WL_O<251> WL_O<250> WL_O<249> WL_O<248> WL_O<247> WL_O<246> WL_O<245> ++ WL_O<244> WL_O<243> WL_O<242> WL_O<241> WL_O<240> VDD VSS / ++ RM_IHPSG13_512x16_c2_1P_DEC04 +XSEL<14> ADDR_N_I<3> ADDR_N_I<2> ADDR_N_I<1> ADDR_N_I<0> CS00<14> ECLK_H<14> ++ ECLK_H<15> ECLK_B<14> ECLK_B<15> WL_O<239> WL_O<238> WL_O<237> WL_O<236> ++ WL_O<235> WL_O<234> WL_O<233> WL_O<232> WL_O<231> WL_O<230> WL_O<229> ++ WL_O<228> WL_O<227> WL_O<226> WL_O<225> WL_O<224> VDD VSS / ++ RM_IHPSG13_512x16_c2_1P_DEC04 +XSEL<13> ADDR_N_I<3> ADDR_N_I<2> ADDR_N_I<1> ADDR_N_I<0> CS00<13> ECLK_H<13> ++ ECLK_H<14> ECLK_B<13> ECLK_B<14> WL_O<223> WL_O<222> WL_O<221> WL_O<220> ++ WL_O<219> WL_O<218> WL_O<217> WL_O<216> WL_O<215> WL_O<214> WL_O<213> ++ WL_O<212> WL_O<211> WL_O<210> WL_O<209> WL_O<208> VDD VSS / ++ RM_IHPSG13_512x16_c2_1P_DEC04 +XSEL<12> ADDR_N_I<3> ADDR_N_I<2> ADDR_N_I<1> ADDR_N_I<0> CS00<12> ECLK_H<12> ++ ECLK_H<13> ECLK_B<12> ECLK_B<13> WL_O<207> WL_O<206> WL_O<205> WL_O<204> ++ WL_O<203> WL_O<202> WL_O<201> WL_O<200> WL_O<199> WL_O<198> WL_O<197> ++ WL_O<196> WL_O<195> WL_O<194> WL_O<193> WL_O<192> VDD VSS / ++ RM_IHPSG13_512x16_c2_1P_DEC04 +XSEL<11> ADDR_N_I<3> ADDR_N_I<2> ADDR_N_I<1> ADDR_N_I<0> CS00<11> ECLK_H<11> ++ ECLK_H<12> ECLK_B<11> ECLK_B<12> WL_O<191> WL_O<190> WL_O<189> WL_O<188> ++ WL_O<187> WL_O<186> WL_O<185> WL_O<184> WL_O<183> WL_O<182> WL_O<181> ++ WL_O<180> WL_O<179> WL_O<178> WL_O<177> WL_O<176> VDD VSS / ++ RM_IHPSG13_512x16_c2_1P_DEC04 +XSEL<10> ADDR_N_I<3> ADDR_N_I<2> ADDR_N_I<1> ADDR_N_I<0> CS00<10> ECLK_H<10> ++ ECLK_H<11> ECLK_B<10> ECLK_B<11> WL_O<175> WL_O<174> WL_O<173> WL_O<172> ++ WL_O<171> WL_O<170> WL_O<169> WL_O<168> WL_O<167> WL_O<166> WL_O<165> ++ WL_O<164> WL_O<163> WL_O<162> WL_O<161> WL_O<160> VDD VSS / ++ RM_IHPSG13_512x16_c2_1P_DEC04 +XSEL<9> ADDR_N_I<3> ADDR_N_I<2> ADDR_N_I<1> ADDR_N_I<0> CS00<9> ECLK_H<9> ++ ECLK_H<10> ECLK_B<9> ECLK_B<10> WL_O<159> WL_O<158> WL_O<157> WL_O<156> ++ WL_O<155> WL_O<154> WL_O<153> WL_O<152> WL_O<151> WL_O<150> WL_O<149> ++ WL_O<148> WL_O<147> WL_O<146> WL_O<145> WL_O<144> VDD VSS / ++ RM_IHPSG13_512x16_c2_1P_DEC04 +XSEL<8> ADDR_N_I<3> ADDR_N_I<2> ADDR_N_I<1> ADDR_N_I<0> CS00<8> ECLK_H<8> ++ ECLK_H<9> ECLK_B<8> ECLK_B<9> WL_O<143> WL_O<142> WL_O<141> WL_O<140> ++ WL_O<139> WL_O<138> WL_O<137> WL_O<136> WL_O<135> WL_O<134> WL_O<133> ++ WL_O<132> WL_O<131> WL_O<130> WL_O<129> WL_O<128> VDD VSS / ++ RM_IHPSG13_512x16_c2_1P_DEC04 +XSEL<7> ADDR_N_I<3> ADDR_N_I<2> ADDR_N_I<1> ADDR_N_I<0> CS00<7> ECLK_H<7> ++ ECLK_H<8> ECLK_B<7> ECLK_B<8> WL_O<127> WL_O<126> WL_O<125> WL_O<124> ++ WL_O<123> WL_O<122> WL_O<121> WL_O<120> WL_O<119> WL_O<118> WL_O<117> ++ WL_O<116> WL_O<115> WL_O<114> WL_O<113> WL_O<112> VDD VSS / ++ RM_IHPSG13_512x16_c2_1P_DEC04 +XSEL<6> ADDR_N_I<3> ADDR_N_I<2> ADDR_N_I<1> ADDR_N_I<0> CS00<6> ECLK_H<6> ++ ECLK_H<7> ECLK_B<6> ECLK_B<7> WL_O<111> WL_O<110> WL_O<109> WL_O<108> ++ WL_O<107> WL_O<106> WL_O<105> WL_O<104> WL_O<103> WL_O<102> WL_O<101> ++ WL_O<100> WL_O<99> WL_O<98> WL_O<97> WL_O<96> VDD VSS / ++ RM_IHPSG13_512x16_c2_1P_DEC04 +XSEL<5> ADDR_N_I<3> ADDR_N_I<2> ADDR_N_I<1> ADDR_N_I<0> CS00<5> ECLK_H<5> ++ ECLK_H<6> ECLK_B<5> ECLK_B<6> WL_O<95> WL_O<94> WL_O<93> WL_O<92> WL_O<91> ++ WL_O<90> WL_O<89> WL_O<88> WL_O<87> WL_O<86> WL_O<85> WL_O<84> WL_O<83> ++ WL_O<82> WL_O<81> WL_O<80> VDD VSS / RM_IHPSG13_512x16_c2_1P_DEC04 +XSEL<4> ADDR_N_I<3> ADDR_N_I<2> ADDR_N_I<1> ADDR_N_I<0> CS00<4> ECLK_H<4> ++ ECLK_H<5> ECLK_B<4> ECLK_B<5> WL_O<79> WL_O<78> WL_O<77> WL_O<76> WL_O<75> ++ WL_O<74> WL_O<73> WL_O<72> WL_O<71> WL_O<70> WL_O<69> WL_O<68> WL_O<67> ++ WL_O<66> WL_O<65> WL_O<64> VDD VSS / RM_IHPSG13_512x16_c2_1P_DEC04 +XSEL<3> ADDR_N_I<3> ADDR_N_I<2> ADDR_N_I<1> ADDR_N_I<0> CS00<3> ECLK_H<3> ++ ECLK_H<4> ECLK_B<3> ECLK_B<4> WL_O<63> WL_O<62> WL_O<61> WL_O<60> WL_O<59> ++ WL_O<58> WL_O<57> WL_O<56> WL_O<55> WL_O<54> WL_O<53> WL_O<52> WL_O<51> ++ WL_O<50> WL_O<49> WL_O<48> VDD VSS / RM_IHPSG13_512x16_c2_1P_DEC04 +XSEL<2> ADDR_N_I<3> ADDR_N_I<2> ADDR_N_I<1> ADDR_N_I<0> CS00<2> ECLK_H<2> ++ ECLK_H<3> ECLK_B<2> ECLK_B<3> WL_O<47> WL_O<46> WL_O<45> WL_O<44> WL_O<43> ++ WL_O<42> WL_O<41> WL_O<40> WL_O<39> WL_O<38> WL_O<37> WL_O<36> WL_O<35> ++ WL_O<34> WL_O<33> WL_O<32> VDD VSS / RM_IHPSG13_512x16_c2_1P_DEC04 +XSEL<1> ADDR_N_I<3> ADDR_N_I<2> ADDR_N_I<1> ADDR_N_I<0> CS00<1> ECLK_H<1> ++ ECLK_H<2> ECLK_B<1> ECLK_B<2> WL_O<31> WL_O<30> WL_O<29> WL_O<28> WL_O<27> ++ WL_O<26> WL_O<25> WL_O<24> WL_O<23> WL_O<22> WL_O<21> WL_O<20> WL_O<19> ++ WL_O<18> WL_O<17> WL_O<16> VDD VSS / RM_IHPSG13_512x16_c2_1P_DEC04 +XSEL<0> ADDR_N_I<3> ADDR_N_I<2> ADDR_N_I<1> ADDR_N_I<0> CS00<0> ECLK_I ++ ECLK_H<1> ECLK_B<0> ECLK_B<1> WL_O<15> WL_O<14> WL_O<13> WL_O<12> WL_O<11> ++ WL_O<10> WL_O<9> WL_O<8> WL_O<7> WL_O<6> WL_O<5> WL_O<4> WL_O<3> WL_O<2> ++ WL_O<1> WL_O<0> VDD VSS / RM_IHPSG13_512x16_c2_1P_DEC04 +XDEC01<10> ADDR_N_I<9> ADDR_N_I<8> CS_I CS04<1> VDD VSS / ++ RM_IHPSG13_512x16_c2_1P_DEC01 +XDEC01<9> ADDR_N_I<7> ADDR_N_I<6> CS04<1> CS02<5> VDD VSS / ++ RM_IHPSG13_512x16_c2_1P_DEC01 +XDEC01<8> ADDR_N_I<7> ADDR_N_I<6> CS04<0> CS02<1> VDD VSS / ++ RM_IHPSG13_512x16_c2_1P_DEC01 +XDEC01<7> ADDR_N_I<5> ADDR_N_I<4> CS02<7> CS00<29> VDD VSS / ++ RM_IHPSG13_512x16_c2_1P_DEC01 +XDEC01<6> ADDR_N_I<5> ADDR_N_I<4> CS02<6> CS00<25> VDD VSS / ++ RM_IHPSG13_512x16_c2_1P_DEC01 +XDEC01<5> ADDR_N_I<5> ADDR_N_I<4> CS02<5> CS00<21> VDD VSS / ++ RM_IHPSG13_512x16_c2_1P_DEC01 +XDEC01<4> ADDR_N_I<5> ADDR_N_I<4> CS02<4> CS00<17> VDD VSS / ++ RM_IHPSG13_512x16_c2_1P_DEC01 +XDEC01<3> ADDR_N_I<5> ADDR_N_I<4> CS02<3> CS00<13> VDD VSS / ++ RM_IHPSG13_512x16_c2_1P_DEC01 +XDEC01<2> ADDR_N_I<5> ADDR_N_I<4> CS02<2> CS00<9> VDD VSS / ++ RM_IHPSG13_512x16_c2_1P_DEC01 +XDEC01<1> ADDR_N_I<5> ADDR_N_I<4> CS02<1> CS00<5> VDD VSS / ++ RM_IHPSG13_512x16_c2_1P_DEC01 +XDEC01<0> ADDR_N_I<5> ADDR_N_I<4> CS02<0> CS00<1> VDD VSS / ++ RM_IHPSG13_512x16_c2_1P_DEC01 +XDEC10<9> ADDR_N_I<7> ADDR_N_I<6> CS04<1> CS02<6> VDD VSS / ++ RM_IHPSG13_512x16_c2_1P_DEC02 +XDEC10<8> ADDR_N_I<7> ADDR_N_I<6> CS04<0> CS02<2> VDD VSS / ++ RM_IHPSG13_512x16_c2_1P_DEC02 +XDEC10<7> ADDR_N_I<5> ADDR_N_I<4> CS02<7> CS00<30> VDD VSS / ++ RM_IHPSG13_512x16_c2_1P_DEC02 +XDEC10<6> ADDR_N_I<5> ADDR_N_I<4> CS02<6> CS00<26> VDD VSS / ++ RM_IHPSG13_512x16_c2_1P_DEC02 +XDEC10<5> ADDR_N_I<5> ADDR_N_I<4> CS02<5> CS00<22> VDD VSS / ++ RM_IHPSG13_512x16_c2_1P_DEC02 +XDEC10<4> ADDR_N_I<5> ADDR_N_I<4> CS02<4> CS00<18> VDD VSS / ++ RM_IHPSG13_512x16_c2_1P_DEC02 +XDEC10<3> ADDR_N_I<5> ADDR_N_I<4> CS02<3> CS00<14> VDD VSS / ++ RM_IHPSG13_512x16_c2_1P_DEC02 +XDEC10<2> ADDR_N_I<5> ADDR_N_I<4> CS02<2> CS00<10> VDD VSS / ++ RM_IHPSG13_512x16_c2_1P_DEC02 +XDEC10<1> ADDR_N_I<5> ADDR_N_I<4> CS02<1> CS00<6> VDD VSS / ++ RM_IHPSG13_512x16_c2_1P_DEC02 +XDEC10<0> ADDR_N_I<5> ADDR_N_I<4> CS02<0> CS00<2> VDD VSS / ++ RM_IHPSG13_512x16_c2_1P_DEC02 +XI0 ADDR_N_I<9> VDD VSS / RSC_IHPSG13_TIEL +.ENDS +.SUBCKT RM_IHPSG13_512x16_c2_1P_ROWREG9 ACLK_N_I ADDR_I<8> ADDR_I<7> ADDR_I<6> ADDR_I<5> ++ ADDR_I<4> ADDR_I<3> ADDR_I<2> ADDR_I<1> ADDR_I<0> ADDR_N_O<8> ADDR_N_O<7> ++ ADDR_N_O<6> ADDR_N_O<5> ADDR_N_O<4> ADDR_N_O<3> ADDR_N_O<2> ADDR_N_O<1> ++ ADDR_N_O<0> BIST_ADDR_I<8> BIST_ADDR_I<7> BIST_ADDR_I<6> BIST_ADDR_I<5> ++ BIST_ADDR_I<4> BIST_ADDR_I<3> BIST_ADDR_I<2> BIST_ADDR_I<1> BIST_ADDR_I<0> ++ BIST_EN_I VDD VSS +XINV<8> q_int<8> qn_int<8> VDD VSS / RSC_IHPSG13_CINVX2 +XINV<7> q_int<7> qn_int<7> VDD VSS / RSC_IHPSG13_CINVX2 +XINV<6> q_int<6> qn_int<6> VDD VSS / RSC_IHPSG13_CINVX2 +XINV<5> q_int<5> qn_int<5> VDD VSS / RSC_IHPSG13_CINVX2 +XINV<4> q_int<4> qn_int<4> VDD VSS / RSC_IHPSG13_CINVX2 +XINV<3> q_int<3> qn_int<3> VDD VSS / RSC_IHPSG13_CINVX2 +XINV<2> q_int<2> qn_int<2> VDD VSS / RSC_IHPSG13_CINVX2 +XINV<1> q_int<1> qn_int<1> VDD VSS / RSC_IHPSG13_CINVX2 +XINV<0> q_int<0> qn_int<0> VDD VSS / RSC_IHPSG13_CINVX2 +XDRV<8> qn_int<8> ADDR_N_O<8> VDD VSS / RSC_IHPSG13_CINVX8 +XDRV<7> qn_int<7> ADDR_N_O<7> VDD VSS / RSC_IHPSG13_CINVX8 +XDRV<6> qn_int<6> ADDR_N_O<6> VDD VSS / RSC_IHPSG13_CINVX8 +XDRV<5> qn_int<5> ADDR_N_O<5> VDD VSS / RSC_IHPSG13_CINVX8 +XDRV<4> qn_int<4> ADDR_N_O<4> VDD VSS / RSC_IHPSG13_CINVX8 +XDRV<3> qn_int<3> ADDR_N_O<3> VDD VSS / RSC_IHPSG13_CINVX8 +XDRV<2> qn_int<2> ADDR_N_O<2> VDD VSS / RSC_IHPSG13_CINVX8 +XDRV<1> qn_int<1> ADDR_N_O<1> VDD VSS / RSC_IHPSG13_CINVX8 +XDRV<0> qn_int<0> ADDR_N_O<0> VDD VSS / RSC_IHPSG13_CINVX8 +XDFF<8> BIST_EN_I BIST_ADDR_I<8> ACLK_N_I ADDR_I<8> q_int<8> net04<0> VDD ++ VSS / RSC_IHPSG13_DFNQMX2IX1 +XDFF<7> BIST_EN_I BIST_ADDR_I<7> ACLK_N_I ADDR_I<7> q_int<7> net04<1> VDD ++ VSS / RSC_IHPSG13_DFNQMX2IX1 +XDFF<6> BIST_EN_I BIST_ADDR_I<6> ACLK_N_I ADDR_I<6> q_int<6> net04<2> VDD ++ VSS / RSC_IHPSG13_DFNQMX2IX1 +XDFF<5> BIST_EN_I BIST_ADDR_I<5> ACLK_N_I ADDR_I<5> q_int<5> net04<3> VDD ++ VSS / RSC_IHPSG13_DFNQMX2IX1 +XDFF<4> BIST_EN_I BIST_ADDR_I<4> ACLK_N_I ADDR_I<4> q_int<4> net04<4> VDD ++ VSS / RSC_IHPSG13_DFNQMX2IX1 +XDFF<3> BIST_EN_I BIST_ADDR_I<3> ACLK_N_I ADDR_I<3> q_int<3> net04<5> VDD ++ VSS / RSC_IHPSG13_DFNQMX2IX1 +XDFF<2> BIST_EN_I BIST_ADDR_I<2> ACLK_N_I ADDR_I<2> q_int<2> net04<6> VDD ++ VSS / RSC_IHPSG13_DFNQMX2IX1 +XDFF<1> BIST_EN_I BIST_ADDR_I<1> ACLK_N_I ADDR_I<1> q_int<1> net04<7> VDD ++ VSS / RSC_IHPSG13_DFNQMX2IX1 +XDFF<0> BIST_EN_I BIST_ADDR_I<0> ACLK_N_I ADDR_I<0> q_int<0> net04<8> VDD ++ VSS / RSC_IHPSG13_DFNQMX2IX1 +.ENDS + +.SUBCKT RM_IHPSG13_512x16_c2_1P_ROWDEC7 ADDR_N_I<6> ADDR_N_I<5> ADDR_N_I<4> ADDR_N_I<3> ++ ADDR_N_I<2> ADDR_N_I<1> ADDR_N_I<0> CS_I ECLK_I WL_O<127> WL_O<126> ++ WL_O<125> WL_O<124> WL_O<123> WL_O<122> WL_O<121> WL_O<120> WL_O<119> ++ WL_O<118> WL_O<117> WL_O<116> WL_O<115> WL_O<114> WL_O<113> WL_O<112> ++ WL_O<111> WL_O<110> WL_O<109> WL_O<108> WL_O<107> WL_O<106> WL_O<105> ++ WL_O<104> WL_O<103> WL_O<102> WL_O<101> WL_O<100> WL_O<99> WL_O<98> WL_O<97> ++ WL_O<96> WL_O<95> WL_O<94> WL_O<93> WL_O<92> WL_O<91> WL_O<90> WL_O<89> ++ WL_O<88> WL_O<87> WL_O<86> WL_O<85> WL_O<84> WL_O<83> WL_O<82> WL_O<81> ++ WL_O<80> WL_O<79> WL_O<78> WL_O<77> WL_O<76> WL_O<75> WL_O<74> WL_O<73> ++ WL_O<72> WL_O<71> WL_O<70> WL_O<69> WL_O<68> WL_O<67> WL_O<66> WL_O<65> ++ WL_O<64> WL_O<63> WL_O<62> WL_O<61> WL_O<60> WL_O<59> WL_O<58> WL_O<57> ++ WL_O<56> WL_O<55> WL_O<54> WL_O<53> WL_O<52> WL_O<51> WL_O<50> WL_O<49> ++ WL_O<48> WL_O<47> WL_O<46> WL_O<45> WL_O<44> WL_O<43> WL_O<42> WL_O<41> ++ WL_O<40> WL_O<39> WL_O<38> WL_O<37> WL_O<36> WL_O<35> WL_O<34> WL_O<33> ++ WL_O<32> WL_O<31> WL_O<30> WL_O<29> WL_O<28> WL_O<27> WL_O<26> WL_O<25> ++ WL_O<24> WL_O<23> WL_O<22> WL_O<21> WL_O<20> WL_O<19> WL_O<18> WL_O<17> ++ WL_O<16> WL_O<15> WL_O<14> WL_O<13> WL_O<12> WL_O<11> WL_O<10> WL_O<9> ++ WL_O<8> WL_O<7> WL_O<6> WL_O<5> WL_O<4> WL_O<3> WL_O<2> WL_O<1> WL_O<0> ++ VDD VSS +XDEC11<1> ADDR_N_I<5> ADDR_N_I<4> CS04<1> CS00<7> VDD VSS / ++ RM_IHPSG13_512x16_c2_1P_DEC03 +XDEC11<0> ADDR_N_I<5> ADDR_N_I<4> CS04<0> CS00<3> VDD VSS / ++ RM_IHPSG13_512x16_c2_1P_DEC03 +XDEC10<1> ADDR_N_I<5> ADDR_N_I<4> CS04<1> CS00<6> VDD VSS / ++ RM_IHPSG13_512x16_c2_1P_DEC02 +XDEC10<0> ADDR_N_I<5> ADDR_N_I<4> CS04<0> CS00<2> VDD VSS / ++ RM_IHPSG13_512x16_c2_1P_DEC02 +XSEL<7> ADDR_N_I<3> ADDR_N_I<2> ADDR_N_I<1> ADDR_N_I<0> CS00<7> ECLK_H<7> ++ ECLK_H<8> ECLK_B<7> ECLK_B<8> WL_O<127> WL_O<126> WL_O<125> WL_O<124> ++ WL_O<123> WL_O<122> WL_O<121> WL_O<120> WL_O<119> WL_O<118> WL_O<117> ++ WL_O<116> WL_O<115> WL_O<114> WL_O<113> WL_O<112> VDD VSS / ++ RM_IHPSG13_512x16_c2_1P_DEC04 +XSEL<6> ADDR_N_I<3> ADDR_N_I<2> ADDR_N_I<1> ADDR_N_I<0> CS00<6> ECLK_H<6> ++ ECLK_H<7> ECLK_B<6> ECLK_B<7> WL_O<111> WL_O<110> WL_O<109> WL_O<108> ++ WL_O<107> WL_O<106> WL_O<105> WL_O<104> WL_O<103> WL_O<102> WL_O<101> ++ WL_O<100> WL_O<99> WL_O<98> WL_O<97> WL_O<96> VDD VSS / ++ RM_IHPSG13_512x16_c2_1P_DEC04 +XSEL<5> ADDR_N_I<3> ADDR_N_I<2> ADDR_N_I<1> ADDR_N_I<0> CS00<5> ECLK_H<5> ++ ECLK_H<6> ECLK_B<5> ECLK_B<6> WL_O<95> WL_O<94> WL_O<93> WL_O<92> WL_O<91> ++ WL_O<90> WL_O<89> WL_O<88> WL_O<87> WL_O<86> WL_O<85> WL_O<84> WL_O<83> ++ WL_O<82> WL_O<81> WL_O<80> VDD VSS / RM_IHPSG13_512x16_c2_1P_DEC04 +XSEL<4> ADDR_N_I<3> ADDR_N_I<2> ADDR_N_I<1> ADDR_N_I<0> CS00<4> ECLK_H<4> ++ ECLK_H<5> ECLK_B<4> ECLK_B<5> WL_O<79> WL_O<78> WL_O<77> WL_O<76> WL_O<75> ++ WL_O<74> WL_O<73> WL_O<72> WL_O<71> WL_O<70> WL_O<69> WL_O<68> WL_O<67> ++ WL_O<66> WL_O<65> WL_O<64> VDD VSS / RM_IHPSG13_512x16_c2_1P_DEC04 +XSEL<3> ADDR_N_I<3> ADDR_N_I<2> ADDR_N_I<1> ADDR_N_I<0> CS00<3> ECLK_H<3> ++ ECLK_H<4> ECLK_B<3> ECLK_B<4> WL_O<63> WL_O<62> WL_O<61> WL_O<60> WL_O<59> ++ WL_O<58> WL_O<57> WL_O<56> WL_O<55> WL_O<54> WL_O<53> WL_O<52> WL_O<51> ++ WL_O<50> WL_O<49> WL_O<48> VDD VSS / RM_IHPSG13_512x16_c2_1P_DEC04 +XSEL<2> ADDR_N_I<3> ADDR_N_I<2> ADDR_N_I<1> ADDR_N_I<0> CS00<2> ECLK_H<2> ++ ECLK_H<3> ECLK_B<2> ECLK_B<3> WL_O<47> WL_O<46> WL_O<45> WL_O<44> WL_O<43> ++ WL_O<42> WL_O<41> WL_O<40> WL_O<39> WL_O<38> WL_O<37> WL_O<36> WL_O<35> ++ WL_O<34> WL_O<33> WL_O<32> VDD VSS / RM_IHPSG13_512x16_c2_1P_DEC04 +XSEL<1> ADDR_N_I<3> ADDR_N_I<2> ADDR_N_I<1> ADDR_N_I<0> CS00<1> ECLK_H<1> ++ ECLK_H<2> ECLK_B<1> ECLK_B<2> WL_O<31> WL_O<30> WL_O<29> WL_O<28> WL_O<27> ++ WL_O<26> WL_O<25> WL_O<24> WL_O<23> WL_O<22> WL_O<21> WL_O<20> WL_O<19> ++ WL_O<18> WL_O<17> WL_O<16> VDD VSS / RM_IHPSG13_512x16_c2_1P_DEC04 +XSEL<0> ADDR_N_I<3> ADDR_N_I<2> ADDR_N_I<1> ADDR_N_I<0> CS00<0> ECLK_I ++ ECLK_H<1> ECLK_B<0> ECLK_B<1> WL_O<15> WL_O<14> WL_O<13> WL_O<12> WL_O<11> ++ WL_O<10> WL_O<9> WL_O<8> WL_O<7> WL_O<6> WL_O<5> WL_O<4> WL_O<3> WL_O<2> ++ WL_O<1> WL_O<0> VDD VSS / RM_IHPSG13_512x16_c2_1P_DEC04 +XDEC00<2> ADDR_N_I<7> ADDR_N_I<6> CS_I CS04<0> VDD VSS / ++ RM_IHPSG13_512x16_c2_1P_DEC00 +XDEC00<1> ADDR_N_I<5> ADDR_N_I<4> CS04<1> CS00<4> VDD VSS / ++ RM_IHPSG13_512x16_c2_1P_DEC00 +XDEC00<0> ADDR_N_I<5> ADDR_N_I<4> CS04<0> CS00<0> VDD VSS / ++ RM_IHPSG13_512x16_c2_1P_DEC00 +XDEC01<2> ADDR_N_I<7> ADDR_N_I<6> CS_I CS04<1> VDD VSS / ++ RM_IHPSG13_512x16_c2_1P_DEC01 +XDEC01<1> ADDR_N_I<5> ADDR_N_I<4> CS04<1> CS00<5> VDD VSS / ++ RM_IHPSG13_512x16_c2_1P_DEC01 +XDEC01<0> ADDR_N_I<5> ADDR_N_I<4> CS04<0> CS00<1> VDD VSS / ++ RM_IHPSG13_512x16_c2_1P_DEC01 +XL2<44> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<43> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<42> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<41> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<40> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<39> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<38> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<37> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<36> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<35> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<34> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<33> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<32> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<31> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<30> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<29> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<28> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<27> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<26> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<25> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<24> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<23> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<22> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<21> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<20> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<19> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<18> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<17> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<16> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<15> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<14> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<13> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<12> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<11> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<10> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<9> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<8> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<7> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<6> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<5> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<4> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<3> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<2> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<1> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI0 ADDR_N_I<7> VDD VSS / RSC_IHPSG13_TIEL +.ENDS +.SUBCKT RM_IHPSG13_512x16_c2_1P_ROWREG7 ACLK_N_I ADDR_I<6> ADDR_I<5> ADDR_I<4> ADDR_I<3> ++ ADDR_I<2> ADDR_I<1> ADDR_I<0> ADDR_N_O<6> ADDR_N_O<5> ADDR_N_O<4> ++ ADDR_N_O<3> ADDR_N_O<2> ADDR_N_O<1> ADDR_N_O<0> BIST_ADDR_I<6> ++ BIST_ADDR_I<5> BIST_ADDR_I<4> BIST_ADDR_I<3> BIST_ADDR_I<2> BIST_ADDR_I<1> ++ BIST_ADDR_I<0> BIST_EN_I VDD VSS +XINV<6> q_int<6> qn_int<6> VDD VSS / RSC_IHPSG13_CINVX2 +XINV<5> q_int<5> qn_int<5> VDD VSS / RSC_IHPSG13_CINVX2 +XINV<4> q_int<4> qn_int<4> VDD VSS / RSC_IHPSG13_CINVX2 +XINV<3> q_int<3> qn_int<3> VDD VSS / RSC_IHPSG13_CINVX2 +XINV<2> q_int<2> qn_int<2> VDD VSS / RSC_IHPSG13_CINVX2 +XINV<1> q_int<1> qn_int<1> VDD VSS / RSC_IHPSG13_CINVX2 +XINV<0> q_int<0> qn_int<0> VDD VSS / RSC_IHPSG13_CINVX2 +XDRV<6> qn_int<6> ADDR_N_O<6> VDD VSS / RSC_IHPSG13_CINVX8 +XDRV<5> qn_int<5> ADDR_N_O<5> VDD VSS / RSC_IHPSG13_CINVX8 +XDRV<4> qn_int<4> ADDR_N_O<4> VDD VSS / RSC_IHPSG13_CINVX8 +XDRV<3> qn_int<3> ADDR_N_O<3> VDD VSS / RSC_IHPSG13_CINVX8 +XDRV<2> qn_int<2> ADDR_N_O<2> VDD VSS / RSC_IHPSG13_CINVX8 +XDRV<1> qn_int<1> ADDR_N_O<1> VDD VSS / RSC_IHPSG13_CINVX8 +XDRV<0> qn_int<0> ADDR_N_O<0> VDD VSS / RSC_IHPSG13_CINVX8 +XDFF<6> BIST_EN_I BIST_ADDR_I<6> ACLK_N_I ADDR_I<6> q_int<6> net2<0> VDD ++ VSS / RSC_IHPSG13_DFNQMX2IX1 +XDFF<5> BIST_EN_I BIST_ADDR_I<5> ACLK_N_I ADDR_I<5> q_int<5> net2<1> VDD ++ VSS / RSC_IHPSG13_DFNQMX2IX1 +XDFF<4> BIST_EN_I BIST_ADDR_I<4> ACLK_N_I ADDR_I<4> q_int<4> net2<2> VDD ++ VSS / RSC_IHPSG13_DFNQMX2IX1 +XDFF<3> BIST_EN_I BIST_ADDR_I<3> ACLK_N_I ADDR_I<3> q_int<3> net2<3> VDD ++ VSS / RSC_IHPSG13_DFNQMX2IX1 +XDFF<2> BIST_EN_I BIST_ADDR_I<2> ACLK_N_I ADDR_I<2> q_int<2> net2<4> VDD ++ VSS / RSC_IHPSG13_DFNQMX2IX1 +XDFF<1> BIST_EN_I BIST_ADDR_I<1> ACLK_N_I ADDR_I<1> q_int<1> net2<5> VDD ++ VSS / RSC_IHPSG13_DFNQMX2IX1 +XDFF<0> BIST_EN_I BIST_ADDR_I<0> ACLK_N_I ADDR_I<0> q_int<0> net2<6> VDD ++ VSS / RSC_IHPSG13_DFNQMX2IX1 +XI11<8> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI11<7> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI11<6> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI11<5> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI11<4> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI11<3> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI11<2> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI11<1> VDD VSS / RSC_IHPSG13_FILLCAP8 +.ENDS + +.SUBCKT RM_IHPSG13_512x16_c2_1P_COLDRV13X8 ADDR_COL_I<1> ADDR_COL_I<0> ADDR_COL_O<1> ++ ADDR_COL_O<0> ADDR_DEC_I<7> ADDR_DEC_I<6> ADDR_DEC_I<5> ADDR_DEC_I<4> ++ ADDR_DEC_I<3> ADDR_DEC_I<2> ADDR_DEC_I<1> ADDR_DEC_I<0> ADDR_DEC_O<7> ++ ADDR_DEC_O<6> ADDR_DEC_O<5> ADDR_DEC_O<4> ADDR_DEC_O<3> ADDR_DEC_O<2> ++ ADDR_DEC_O<1> ADDR_DEC_O<0> DCLK_I DCLK_O RCLK_I RCLK_O WCLK_I WCLK_O ++ VDD VSS +XI0<1> VDD VSS / RSC_IHPSG13_FILLCAP4 +XI0<0> VDD VSS / RSC_IHPSG13_FILLCAP4 +XADDR_COL_DRV<1> ADDR_COL_I<1> ADDR_COL_O<1> VDD VSS / ++ RSC_IHPSG13_CBUFX8 +XADDR_COL_DRV<0> ADDR_COL_I<0> ADDR_COL_O<0> VDD VSS / ++ RSC_IHPSG13_CBUFX8 +XADDR_DEC_DRV<7> ADDR_DEC_I<7> ADDR_DEC_O<7> VDD VSS / ++ RSC_IHPSG13_CBUFX8 +XADDR_DEC_DRV<6> ADDR_DEC_I<6> ADDR_DEC_O<6> VDD VSS / ++ RSC_IHPSG13_CBUFX8 +XADDR_DEC_DRV<5> ADDR_DEC_I<5> ADDR_DEC_O<5> VDD VSS / ++ RSC_IHPSG13_CBUFX8 +XADDR_DEC_DRV<4> ADDR_DEC_I<4> ADDR_DEC_O<4> VDD VSS / ++ RSC_IHPSG13_CBUFX8 +XADDR_DEC_DRV<3> ADDR_DEC_I<3> ADDR_DEC_O<3> VDD VSS / ++ RSC_IHPSG13_CBUFX8 +XADDR_DEC_DRV<2> ADDR_DEC_I<2> ADDR_DEC_O<2> VDD VSS / ++ RSC_IHPSG13_CBUFX8 +XADDR_DEC_DRV<1> ADDR_DEC_I<1> ADDR_DEC_O<1> VDD VSS / ++ RSC_IHPSG13_CBUFX8 +XADDR_DEC_DRV<0> ADDR_DEC_I<0> ADDR_DEC_O<0> VDD VSS / ++ RSC_IHPSG13_CBUFX8 +XDCLK_DRV DCLK_I DCLK_O VDD VSS / RSC_IHPSG13_CBUFX8 +XRCLK_DRV RCLK_I RCLK_O VDD VSS / RSC_IHPSG13_CBUFX8 +XWCLK_DRV WCLK_I WCLK_O VDD VSS / RSC_IHPSG13_CBUFX8 +.ENDS +.SUBCKT RM_IHPSG13_512x16_c2_1P_WLDRV16X8 A<15> A<14> A<13> A<12> A<11> A<10> A<9> A<8> ++ A<7> A<6> A<5> A<4> A<3> A<2> A<1> A<0> Z<15> Z<14> Z<13> Z<12> Z<11> Z<10> ++ Z<9> Z<8> Z<7> Z<6> Z<5> Z<4> Z<3> Z<2> Z<1> Z<0> VDD VSS +XBUF<15> A<15> Z<15> VDD VSS / RSC_IHPSG13_WLDRVX8 +XBUF<14> A<14> Z<14> VDD VSS / RSC_IHPSG13_WLDRVX8 +XBUF<13> A<13> Z<13> VDD VSS / RSC_IHPSG13_WLDRVX8 +XBUF<12> A<12> Z<12> VDD VSS / RSC_IHPSG13_WLDRVX8 +XBUF<11> A<11> Z<11> VDD VSS / RSC_IHPSG13_WLDRVX8 +XBUF<10> A<10> Z<10> VDD VSS / RSC_IHPSG13_WLDRVX8 +XBUF<9> A<9> Z<9> VDD VSS / RSC_IHPSG13_WLDRVX8 +XBUF<8> A<8> Z<8> VDD VSS / RSC_IHPSG13_WLDRVX8 +XBUF<7> A<7> Z<7> VDD VSS / RSC_IHPSG13_WLDRVX8 +XBUF<6> A<6> Z<6> VDD VSS / RSC_IHPSG13_WLDRVX8 +XBUF<5> A<5> Z<5> VDD VSS / RSC_IHPSG13_WLDRVX8 +XBUF<4> A<4> Z<4> VDD VSS / RSC_IHPSG13_WLDRVX8 +XBUF<3> A<3> Z<3> VDD VSS / RSC_IHPSG13_WLDRVX8 +XBUF<2> A<2> Z<2> VDD VSS / RSC_IHPSG13_WLDRVX8 +XBUF<1> A<1> Z<1> VDD VSS / RSC_IHPSG13_WLDRVX8 +XBUF<0> A<0> Z<0> VDD VSS / RSC_IHPSG13_WLDRVX8 +.ENDS + + + +.SUBCKT RM_IHPSG13_512x16_c2_1P_ROWDEC6 ADDR_N_I<5> ADDR_N_I<4> ADDR_N_I<3> ADDR_N_I<2> ++ ADDR_N_I<1> ADDR_N_I<0> CS_I ECLK_I WL_O<63> WL_O<62> WL_O<61> WL_O<60> ++ WL_O<59> WL_O<58> WL_O<57> WL_O<56> WL_O<55> WL_O<54> WL_O<53> WL_O<52> ++ WL_O<51> WL_O<50> WL_O<49> WL_O<48> WL_O<47> WL_O<46> WL_O<45> WL_O<44> ++ WL_O<43> WL_O<42> WL_O<41> WL_O<40> WL_O<39> WL_O<38> WL_O<37> WL_O<36> ++ WL_O<35> WL_O<34> WL_O<33> WL_O<32> WL_O<31> WL_O<30> WL_O<29> WL_O<28> ++ WL_O<27> WL_O<26> WL_O<25> WL_O<24> WL_O<23> WL_O<22> WL_O<21> WL_O<20> ++ WL_O<19> WL_O<18> WL_O<17> WL_O<16> WL_O<15> WL_O<14> WL_O<13> WL_O<12> ++ WL_O<11> WL_O<10> WL_O<9> WL_O<8> WL_O<7> WL_O<6> WL_O<5> WL_O<4> WL_O<3> ++ WL_O<2> WL_O<1> WL_O<0> VDD VSS +XDEC11 ADDR_N_I<5> ADDR_N_I<4> CS_I CS00<3> VDD VSS / ++ RM_IHPSG13_512x16_c2_1P_DEC03 +XDEC00 ADDR_N_I<5> ADDR_N_I<4> CS_I CS00<0> VDD VSS / ++ RM_IHPSG13_512x16_c2_1P_DEC00 +XDEC01 ADDR_N_I<5> ADDR_N_I<4> CS_I CS00<1> VDD VSS / ++ RM_IHPSG13_512x16_c2_1P_DEC01 +XDEC10 ADDR_N_I<5> ADDR_N_I<4> CS_I CS00<2> VDD VSS / ++ RM_IHPSG13_512x16_c2_1P_DEC02 +XSEL<3> ADDR_N_I<3> ADDR_N_I<2> ADDR_N_I<1> ADDR_N_I<0> CS00<3> ECLK_H<3> ++ ECLK_H<4> ECLK_B<3> ECLK_B<4> WL_O<63> WL_O<62> WL_O<61> WL_O<60> WL_O<59> ++ WL_O<58> WL_O<57> WL_O<56> WL_O<55> WL_O<54> WL_O<53> WL_O<52> WL_O<51> ++ WL_O<50> WL_O<49> WL_O<48> VDD VSS / RM_IHPSG13_512x16_c2_1P_DEC04 +XSEL<2> ADDR_N_I<3> ADDR_N_I<2> ADDR_N_I<1> ADDR_N_I<0> CS00<2> ECLK_H<2> ++ ECLK_H<3> ECLK_B<2> ECLK_B<3> WL_O<47> WL_O<46> WL_O<45> WL_O<44> WL_O<43> ++ WL_O<42> WL_O<41> WL_O<40> WL_O<39> WL_O<38> WL_O<37> WL_O<36> WL_O<35> ++ WL_O<34> WL_O<33> WL_O<32> VDD VSS / RM_IHPSG13_512x16_c2_1P_DEC04 +XSEL<1> ADDR_N_I<3> ADDR_N_I<2> ADDR_N_I<1> ADDR_N_I<0> CS00<1> ECLK_H<1> ++ ECLK_H<2> ECLK_B<1> ECLK_B<2> WL_O<31> WL_O<30> WL_O<29> WL_O<28> WL_O<27> ++ WL_O<26> WL_O<25> WL_O<24> WL_O<23> WL_O<22> WL_O<21> WL_O<20> WL_O<19> ++ WL_O<18> WL_O<17> WL_O<16> VDD VSS / RM_IHPSG13_512x16_c2_1P_DEC04 +XSEL<0> ADDR_N_I<3> ADDR_N_I<2> ADDR_N_I<1> ADDR_N_I<0> CS00<0> ECLK_I ++ ECLK_H<1> ECLK_B<0> ECLK_B<1> WL_O<15> WL_O<14> WL_O<13> WL_O<12> WL_O<11> ++ WL_O<10> WL_O<9> WL_O<8> WL_O<7> WL_O<6> WL_O<5> WL_O<4> WL_O<3> WL_O<2> ++ WL_O<1> WL_O<0> VDD VSS / RM_IHPSG13_512x16_c2_1P_DEC04 +XL2<24> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<23> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<22> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<21> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<20> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<19> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<18> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<17> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<16> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<15> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<14> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<13> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<12> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<11> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<10> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<9> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<8> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<7> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<6> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<5> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<4> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<3> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<2> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<1> VDD VSS / RSC_IHPSG13_FILLCAP8 +.ENDS +.SUBCKT RM_IHPSG13_512x16_c2_1P_ROWREG6 ACLK_N_I ADDR_I<5> ADDR_I<4> ADDR_I<3> ADDR_I<2> ++ ADDR_I<1> ADDR_I<0> ADDR_N_O<5> ADDR_N_O<4> ADDR_N_O<3> ADDR_N_O<2> ++ ADDR_N_O<1> ADDR_N_O<0> BIST_ADDR_I<5> BIST_ADDR_I<4> BIST_ADDR_I<3> ++ BIST_ADDR_I<2> BIST_ADDR_I<1> BIST_ADDR_I<0> BIST_EN_I VDD VSS +XINV<5> q_int<5> qn_int<5> VDD VSS / RSC_IHPSG13_CINVX2 +XINV<4> q_int<4> qn_int<4> VDD VSS / RSC_IHPSG13_CINVX2 +XINV<3> q_int<3> qn_int<3> VDD VSS / RSC_IHPSG13_CINVX2 +XINV<2> q_int<2> qn_int<2> VDD VSS / RSC_IHPSG13_CINVX2 +XINV<1> q_int<1> qn_int<1> VDD VSS / RSC_IHPSG13_CINVX2 +XINV<0> q_int<0> qn_int<0> VDD VSS / RSC_IHPSG13_CINVX2 +XDRV<5> qn_int<5> ADDR_N_O<5> VDD VSS / RSC_IHPSG13_CINVX8 +XDRV<4> qn_int<4> ADDR_N_O<4> VDD VSS / RSC_IHPSG13_CINVX8 +XDRV<3> qn_int<3> ADDR_N_O<3> VDD VSS / RSC_IHPSG13_CINVX8 +XDRV<2> qn_int<2> ADDR_N_O<2> VDD VSS / RSC_IHPSG13_CINVX8 +XDRV<1> qn_int<1> ADDR_N_O<1> VDD VSS / RSC_IHPSG13_CINVX8 +XDRV<0> qn_int<0> ADDR_N_O<0> VDD VSS / RSC_IHPSG13_CINVX8 +XDFF<5> BIST_EN_I BIST_ADDR_I<5> ACLK_N_I ADDR_I<5> q_int<5> net2<0> VDD ++ VSS / RSC_IHPSG13_DFNQMX2IX1 +XDFF<4> BIST_EN_I BIST_ADDR_I<4> ACLK_N_I ADDR_I<4> q_int<4> net2<1> VDD ++ VSS / RSC_IHPSG13_DFNQMX2IX1 +XDFF<3> BIST_EN_I BIST_ADDR_I<3> ACLK_N_I ADDR_I<3> q_int<3> net2<2> VDD ++ VSS / RSC_IHPSG13_DFNQMX2IX1 +XDFF<2> BIST_EN_I BIST_ADDR_I<2> ACLK_N_I ADDR_I<2> q_int<2> net2<3> VDD ++ VSS / RSC_IHPSG13_DFNQMX2IX1 +XDFF<1> BIST_EN_I BIST_ADDR_I<1> ACLK_N_I ADDR_I<1> q_int<1> net2<4> VDD ++ VSS / RSC_IHPSG13_DFNQMX2IX1 +XDFF<0> BIST_EN_I BIST_ADDR_I<0> ACLK_N_I ADDR_I<0> q_int<0> net2<5> VDD ++ VSS / RSC_IHPSG13_DFNQMX2IX1 +XI11<12> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI11<11> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI11<10> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI11<9> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI11<8> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI11<7> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI11<6> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI11<5> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI11<4> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI11<3> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI11<2> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI11<1> VDD VSS / RSC_IHPSG13_FILLCAP8 +.ENDS + + +.SUBCKT RM_IHPSG13_512x16_c2_2P_COLUMN_pcell_0 A_BLC_BOT<1> A_BLC_BOT<0> A_BLC_TOP<1> A_BLC_TOP<0> A_BLT_BOT<1> A_BLT_BOT<0> A_BLT_TOP<1> A_BLT_TOP<0> A_LWL<127> A_LWL<126> A_LWL<125> A_LWL<124> A_LWL<123> A_LWL<122> A_LWL<121> A_LWL<120> A_LWL<119> A_LWL<118> A_LWL<117> A_LWL<116> A_LWL<115> A_LWL<114> A_LWL<113> A_LWL<112> A_LWL<111> A_LWL<110> A_LWL<109> A_LWL<108> A_LWL<107> A_LWL<106> A_LWL<105> A_LWL<104> A_LWL<103> A_LWL<102> A_LWL<101> A_LWL<100> A_LWL<99> A_LWL<98> A_LWL<97> A_LWL<96> A_LWL<95> A_LWL<94> A_LWL<93> A_LWL<92> A_LWL<91> A_LWL<90> A_LWL<89> A_LWL<88> A_LWL<87> A_LWL<86> A_LWL<85> A_LWL<84> A_LWL<83> A_LWL<82> A_LWL<81> A_LWL<80> A_LWL<79> A_LWL<78> A_LWL<77> A_LWL<76> A_LWL<75> A_LWL<74> A_LWL<73> A_LWL<72> A_LWL<71> A_LWL<70> A_LWL<69> A_LWL<68> A_LWL<67> A_LWL<66> A_LWL<65> A_LWL<64> A_LWL<63> A_LWL<62> A_LWL<61> A_LWL<60> A_LWL<59> A_LWL<58> A_LWL<57> A_LWL<56> A_LWL<55> A_LWL<54> A_LWL<53> A_LWL<52> A_LWL<51> A_LWL<50> A_LWL<49> A_LWL<48> A_LWL<47> A_LWL<46> A_LWL<45> A_LWL<44> A_LWL<43> A_LWL<42> A_LWL<41> A_LWL<40> A_LWL<39> A_LWL<38> A_LWL<37> A_LWL<36> A_LWL<35> A_LWL<34> A_LWL<33> A_LWL<32> A_LWL<31> A_LWL<30> A_LWL<29> A_LWL<28> A_LWL<27> A_LWL<26> A_LWL<25> A_LWL<24> A_LWL<23> A_LWL<22> A_LWL<21> A_LWL<20> A_LWL<19> A_LWL<18> A_LWL<17> A_LWL<16> A_LWL<15> A_LWL<14> A_LWL<13> A_LWL<12> A_LWL<11> A_LWL<10> A_LWL<9> A_LWL<8> A_LWL<7> A_LWL<6> A_LWL<5> A_LWL<4> A_LWL<3> A_LWL<2> A_LWL<1> A_LWL<0> A_RWL<127> A_RWL<126> A_RWL<125> A_RWL<124> A_RWL<123> A_RWL<122> A_RWL<121> A_RWL<120> A_RWL<119> A_RWL<118> A_RWL<117> A_RWL<116> A_RWL<115> A_RWL<114> A_RWL<113> A_RWL<112> A_RWL<111> A_RWL<110> A_RWL<109> A_RWL<108> A_RWL<107> A_RWL<106> A_RWL<105> A_RWL<104> A_RWL<103> A_RWL<102> A_RWL<101> A_RWL<100> A_RWL<99> A_RWL<98> A_RWL<97> A_RWL<96> A_RWL<95> A_RWL<94> A_RWL<93> A_RWL<92> A_RWL<91> A_RWL<90> A_RWL<89> A_RWL<88> A_RWL<87> A_RWL<86> A_RWL<85> A_RWL<84> A_RWL<83> A_RWL<82> A_RWL<81> A_RWL<80> A_RWL<79> A_RWL<78> A_RWL<77> A_RWL<76> A_RWL<75> A_RWL<74> A_RWL<73> A_RWL<72> A_RWL<71> A_RWL<70> A_RWL<69> A_RWL<68> A_RWL<67> A_RWL<66> A_RWL<65> A_RWL<64> A_RWL<63> A_RWL<62> A_RWL<61> A_RWL<60> A_RWL<59> A_RWL<58> A_RWL<57> A_RWL<56> A_RWL<55> A_RWL<54> A_RWL<53> A_RWL<52> A_RWL<51> A_RWL<50> A_RWL<49> A_RWL<48> A_RWL<47> A_RWL<46> A_RWL<45> A_RWL<44> A_RWL<43> A_RWL<42> A_RWL<41> A_RWL<40> A_RWL<39> A_RWL<38> A_RWL<37> A_RWL<36> A_RWL<35> A_RWL<34> A_RWL<33> A_RWL<32> A_RWL<31> A_RWL<30> A_RWL<29> A_RWL<28> A_RWL<27> A_RWL<26> A_RWL<25> A_RWL<24> A_RWL<23> A_RWL<22> A_RWL<21> A_RWL<20> A_RWL<19> A_RWL<18> A_RWL<17> A_RWL<16> A_RWL<15> A_RWL<14> A_RWL<13> A_RWL<12> A_RWL<11> A_RWL<10> A_RWL<9> A_RWL<8> A_RWL<7> A_RWL<6> A_RWL<5> A_RWL<4> A_RWL<3> A_RWL<2> A_RWL<1> A_RWL<0> B_BLC_BOT<1> B_BLC_BOT<0> B_BLC_TOP<1> B_BLC_TOP<0> B_BLT_BOT<1> B_BLT_BOT<0> B_BLT_TOP<1> B_BLT_TOP<0> B_LWL<127> B_LWL<126> B_LWL<125> B_LWL<124> B_LWL<123> B_LWL<122> B_LWL<121> B_LWL<120> B_LWL<119> B_LWL<118> B_LWL<117> B_LWL<116> B_LWL<115> B_LWL<114> B_LWL<113> B_LWL<112> B_LWL<111> B_LWL<110> B_LWL<109> B_LWL<108> B_LWL<107> B_LWL<106> B_LWL<105> B_LWL<104> B_LWL<103> B_LWL<102> B_LWL<101> B_LWL<100> B_LWL<99> B_LWL<98> B_LWL<97> B_LWL<96> B_LWL<95> B_LWL<94> B_LWL<93> B_LWL<92> B_LWL<91> B_LWL<90> B_LWL<89> B_LWL<88> B_LWL<87> B_LWL<86> B_LWL<85> B_LWL<84> B_LWL<83> B_LWL<82> B_LWL<81> B_LWL<80> B_LWL<79> B_LWL<78> B_LWL<77> B_LWL<76> B_LWL<75> B_LWL<74> B_LWL<73> B_LWL<72> B_LWL<71> B_LWL<70> B_LWL<69> B_LWL<68> B_LWL<67> B_LWL<66> B_LWL<65> B_LWL<64> B_LWL<63> B_LWL<62> B_LWL<61> B_LWL<60> B_LWL<59> B_LWL<58> B_LWL<57> B_LWL<56> B_LWL<55> B_LWL<54> B_LWL<53> B_LWL<52> B_LWL<51> B_LWL<50> B_LWL<49> B_LWL<48> B_LWL<47> B_LWL<46> B_LWL<45> B_LWL<44> B_LWL<43> B_LWL<42> B_LWL<41> B_LWL<40> B_LWL<39> B_LWL<38> B_LWL<37> B_LWL<36> B_LWL<35> B_LWL<34> B_LWL<33> B_LWL<32> B_LWL<31> B_LWL<30> B_LWL<29> B_LWL<28> B_LWL<27> B_LWL<26> B_LWL<25> B_LWL<24> B_LWL<23> B_LWL<22> B_LWL<21> B_LWL<20> B_LWL<19> B_LWL<18> B_LWL<17> B_LWL<16> B_LWL<15> B_LWL<14> B_LWL<13> B_LWL<12> B_LWL<11> B_LWL<10> B_LWL<9> B_LWL<8> B_LWL<7> B_LWL<6> B_LWL<5> B_LWL<4> B_LWL<3> B_LWL<2> B_LWL<1> B_LWL<0> B_RWL<127> B_RWL<126> B_RWL<125> B_RWL<124> B_RWL<123> B_RWL<122> B_RWL<121> B_RWL<120> B_RWL<119> B_RWL<118> B_RWL<117> B_RWL<116> B_RWL<115> B_RWL<114> B_RWL<113> B_RWL<112> B_RWL<111> B_RWL<110> B_RWL<109> B_RWL<108> B_RWL<107> B_RWL<106> B_RWL<105> B_RWL<104> B_RWL<103> B_RWL<102> B_RWL<101> B_RWL<100> B_RWL<99> B_RWL<98> B_RWL<97> B_RWL<96> B_RWL<95> B_RWL<94> B_RWL<93> B_RWL<92> B_RWL<91> B_RWL<90> B_RWL<89> B_RWL<88> B_RWL<87> B_RWL<86> B_RWL<85> B_RWL<84> B_RWL<83> B_RWL<82> B_RWL<81> B_RWL<80> B_RWL<79> B_RWL<78> B_RWL<77> B_RWL<76> B_RWL<75> B_RWL<74> B_RWL<73> B_RWL<72> B_RWL<71> B_RWL<70> B_RWL<69> B_RWL<68> B_RWL<67> B_RWL<66> B_RWL<65> B_RWL<64> B_RWL<63> B_RWL<62> B_RWL<61> B_RWL<60> B_RWL<59> B_RWL<58> B_RWL<57> B_RWL<56> B_RWL<55> B_RWL<54> B_RWL<53> B_RWL<52> B_RWL<51> B_RWL<50> B_RWL<49> B_RWL<48> B_RWL<47> B_RWL<46> B_RWL<45> B_RWL<44> B_RWL<43> B_RWL<42> B_RWL<41> B_RWL<40> B_RWL<39> B_RWL<38> B_RWL<37> B_RWL<36> B_RWL<35> B_RWL<34> B_RWL<33> B_RWL<32> B_RWL<31> B_RWL<30> B_RWL<29> B_RWL<28> B_RWL<27> B_RWL<26> B_RWL<25> B_RWL<24> B_RWL<23> B_RWL<22> B_RWL<21> B_RWL<20> B_RWL<19> B_RWL<18> B_RWL<17> B_RWL<16> B_RWL<15> B_RWL<14> B_RWL<13> B_RWL<12> B_RWL<11> B_RWL<10> B_RWL<9> B_RWL<8> B_RWL<7> B_RWL<6> B_RWL<5> B_RWL<4> B_RWL<3> B_RWL<2> B_RWL<1> B_RWL<0> VDD_CORE VSS +XRAM<8> A_BLC<13> A_BLC<12> A_BLC_TOP<1> A_BLC_TOP<0> A_BLT<13> A_BLT<12> A_BLT_TOP<1> A_BLT_TOP<0> A_LWL<127> A_LWL<126> A_LWL<125> A_LWL<124> A_LWL<123> A_LWL<122> A_LWL<121> A_LWL<120> A_LWL<119> A_LWL<118> A_LWL<117> A_LWL<116> A_LWL<115> A_LWL<114> A_LWL<113> A_LWL<112> A_RWL<127> A_RWL<126> A_RWL<125> A_RWL<124> A_RWL<123> A_RWL<122> A_RWL<121> A_RWL<120> A_RWL<119> A_RWL<118> A_RWL<117> A_RWL<116> A_RWL<115> A_RWL<114> A_RWL<113> A_RWL<112> B_BLC<13> B_BLC<12> B_BLC_TOP<1> B_BLC_TOP<0> B_BLT<13> B_BLT<12> B_BLT_TOP<1> B_BLT_TOP<0> B_LWL<127> B_LWL<126> B_LWL<125> B_LWL<124> B_LWL<123> B_LWL<122> B_LWL<121> B_LWL<120> B_LWL<119> B_LWL<118> B_LWL<117> B_LWL<116> B_LWL<115> B_LWL<114> B_LWL<113> B_LWL<112> B_RWL<127> B_RWL<126> B_RWL<125> B_RWL<124> B_RWL<123> B_RWL<122> B_RWL<121> B_RWL<120> B_RWL<119> B_RWL<118> B_RWL<117> B_RWL<116> B_RWL<115> B_RWL<114> B_RWL<113> B_RWL<112> VDD_CORE VSS / RM_IHPSG13_512x16_c2_2P_BITKIT_16x2_SRAM +XRAM<7> A_BLC<11> A_BLC<10> A_BLC<13> A_BLC<12> A_BLT<11> A_BLT<10> A_BLT<13> A_BLT<12> A_LWL<111> A_LWL<110> A_LWL<109> A_LWL<108> A_LWL<107> A_LWL<106> A_LWL<105> A_LWL<104> A_LWL<103> A_LWL<102> A_LWL<101> A_LWL<100> A_LWL<99> A_LWL<98> A_LWL<97> A_LWL<96> A_RWL<111> A_RWL<110> A_RWL<109> A_RWL<108> A_RWL<107> A_RWL<106> A_RWL<105> A_RWL<104> A_RWL<103> A_RWL<102> A_RWL<101> A_RWL<100> A_RWL<99> A_RWL<98> A_RWL<97> A_RWL<96> B_BLC<11> B_BLC<10> B_BLC<13> B_BLC<12> B_BLT<11> B_BLT<10> B_BLT<13> B_BLT<12> B_LWL<111> B_LWL<110> B_LWL<109> B_LWL<108> B_LWL<107> B_LWL<106> B_LWL<105> B_LWL<104> B_LWL<103> B_LWL<102> B_LWL<101> B_LWL<100> B_LWL<99> B_LWL<98> B_LWL<97> B_LWL<96> B_RWL<111> B_RWL<110> B_RWL<109> B_RWL<108> B_RWL<107> B_RWL<106> B_RWL<105> B_RWL<104> B_RWL<103> B_RWL<102> B_RWL<101> B_RWL<100> B_RWL<99> B_RWL<98> B_RWL<97> B_RWL<96> VDD_CORE VSS / RM_IHPSG13_512x16_c2_2P_BITKIT_16x2_SRAM +XRAM<6> A_BLC<9> A_BLC<8> A_BLC<11> A_BLC<10> A_BLT<9> A_BLT<8> A_BLT<11> A_BLT<10> A_LWL<95> A_LWL<94> A_LWL<93> A_LWL<92> A_LWL<91> A_LWL<90> A_LWL<89> A_LWL<88> A_LWL<87> A_LWL<86> A_LWL<85> A_LWL<84> A_LWL<83> A_LWL<82> A_LWL<81> A_LWL<80> A_RWL<95> A_RWL<94> A_RWL<93> A_RWL<92> A_RWL<91> A_RWL<90> A_RWL<89> A_RWL<88> A_RWL<87> A_RWL<86> A_RWL<85> A_RWL<84> A_RWL<83> A_RWL<82> A_RWL<81> A_RWL<80> B_BLC<9> B_BLC<8> B_BLC<11> B_BLC<10> B_BLT<9> B_BLT<8> B_BLT<11> B_BLT<10> B_LWL<95> B_LWL<94> B_LWL<93> B_LWL<92> B_LWL<91> B_LWL<90> B_LWL<89> B_LWL<88> B_LWL<87> B_LWL<86> B_LWL<85> B_LWL<84> B_LWL<83> B_LWL<82> B_LWL<81> B_LWL<80> B_RWL<95> B_RWL<94> B_RWL<93> B_RWL<92> B_RWL<91> B_RWL<90> B_RWL<89> B_RWL<88> B_RWL<87> B_RWL<86> B_RWL<85> B_RWL<84> B_RWL<83> B_RWL<82> B_RWL<81> B_RWL<80> VDD_CORE VSS / RM_IHPSG13_512x16_c2_2P_BITKIT_16x2_SRAM +XRAM<5> A_BLC<7> A_BLC<6> A_BLC<9> A_BLC<8> A_BLT<7> A_BLT<6> A_BLT<9> A_BLT<8> A_LWL<79> A_LWL<78> A_LWL<77> A_LWL<76> A_LWL<75> A_LWL<74> A_LWL<73> A_LWL<72> A_LWL<71> A_LWL<70> A_LWL<69> A_LWL<68> A_LWL<67> A_LWL<66> A_LWL<65> A_LWL<64> A_RWL<79> A_RWL<78> A_RWL<77> A_RWL<76> A_RWL<75> A_RWL<74> A_RWL<73> A_RWL<72> A_RWL<71> A_RWL<70> A_RWL<69> A_RWL<68> A_RWL<67> A_RWL<66> A_RWL<65> A_RWL<64> B_BLC<7> B_BLC<6> B_BLC<9> B_BLC<8> B_BLT<7> B_BLT<6> B_BLT<9> B_BLT<8> B_LWL<79> B_LWL<78> B_LWL<77> B_LWL<76> B_LWL<75> B_LWL<74> B_LWL<73> B_LWL<72> B_LWL<71> B_LWL<70> B_LWL<69> B_LWL<68> B_LWL<67> B_LWL<66> B_LWL<65> B_LWL<64> B_RWL<79> B_RWL<78> B_RWL<77> B_RWL<76> B_RWL<75> B_RWL<74> B_RWL<73> B_RWL<72> B_RWL<71> B_RWL<70> B_RWL<69> B_RWL<68> B_RWL<67> B_RWL<66> B_RWL<65> B_RWL<64> VDD_CORE VSS / RM_IHPSG13_512x16_c2_2P_BITKIT_16x2_SRAM +XRAM<4> A_BLC<5> A_BLC<4> A_BLC<7> A_BLC<6> A_BLT<5> A_BLT<4> A_BLT<7> A_BLT<6> A_LWL<63> A_LWL<62> A_LWL<61> A_LWL<60> A_LWL<59> A_LWL<58> A_LWL<57> A_LWL<56> A_LWL<55> A_LWL<54> A_LWL<53> A_LWL<52> A_LWL<51> A_LWL<50> A_LWL<49> A_LWL<48> A_RWL<63> A_RWL<62> A_RWL<61> A_RWL<60> A_RWL<59> A_RWL<58> A_RWL<57> A_RWL<56> A_RWL<55> A_RWL<54> A_RWL<53> A_RWL<52> A_RWL<51> A_RWL<50> A_RWL<49> A_RWL<48> B_BLC<5> B_BLC<4> B_BLC<7> B_BLC<6> B_BLT<5> B_BLT<4> B_BLT<7> B_BLT<6> B_LWL<63> B_LWL<62> B_LWL<61> B_LWL<60> B_LWL<59> B_LWL<58> B_LWL<57> B_LWL<56> B_LWL<55> B_LWL<54> B_LWL<53> B_LWL<52> B_LWL<51> B_LWL<50> B_LWL<49> B_LWL<48> B_RWL<63> B_RWL<62> B_RWL<61> B_RWL<60> B_RWL<59> B_RWL<58> B_RWL<57> B_RWL<56> B_RWL<55> B_RWL<54> B_RWL<53> B_RWL<52> B_RWL<51> B_RWL<50> B_RWL<49> B_RWL<48> VDD_CORE VSS / RM_IHPSG13_512x16_c2_2P_BITKIT_16x2_SRAM +XRAM<3> A_BLC<3> A_BLC<2> A_BLC<5> A_BLC<4> A_BLT<3> A_BLT<2> A_BLT<5> A_BLT<4> A_LWL<47> A_LWL<46> A_LWL<45> A_LWL<44> A_LWL<43> A_LWL<42> A_LWL<41> A_LWL<40> A_LWL<39> A_LWL<38> A_LWL<37> A_LWL<36> A_LWL<35> A_LWL<34> A_LWL<33> A_LWL<32> A_RWL<47> A_RWL<46> A_RWL<45> A_RWL<44> A_RWL<43> A_RWL<42> A_RWL<41> A_RWL<40> A_RWL<39> A_RWL<38> A_RWL<37> A_RWL<36> A_RWL<35> A_RWL<34> A_RWL<33> A_RWL<32> B_BLC<3> B_BLC<2> B_BLC<5> B_BLC<4> B_BLT<3> B_BLT<2> B_BLT<5> B_BLT<4> B_LWL<47> B_LWL<46> B_LWL<45> B_LWL<44> B_LWL<43> B_LWL<42> B_LWL<41> B_LWL<40> B_LWL<39> B_LWL<38> B_LWL<37> B_LWL<36> B_LWL<35> B_LWL<34> B_LWL<33> B_LWL<32> B_RWL<47> B_RWL<46> B_RWL<45> B_RWL<44> B_RWL<43> B_RWL<42> B_RWL<41> B_RWL<40> B_RWL<39> B_RWL<38> B_RWL<37> B_RWL<36> B_RWL<35> B_RWL<34> B_RWL<33> B_RWL<32> VDD_CORE VSS / RM_IHPSG13_512x16_c2_2P_BITKIT_16x2_SRAM +XRAM<2> A_BLC<1> A_BLC<0> A_BLC<3> A_BLC<2> A_BLT<1> A_BLT<0> A_BLT<3> A_BLT<2> A_LWL<31> A_LWL<30> A_LWL<29> A_LWL<28> A_LWL<27> A_LWL<26> A_LWL<25> A_LWL<24> A_LWL<23> A_LWL<22> A_LWL<21> A_LWL<20> A_LWL<19> A_LWL<18> A_LWL<17> A_LWL<16> A_RWL<31> A_RWL<30> A_RWL<29> A_RWL<28> A_RWL<27> A_RWL<26> A_RWL<25> A_RWL<24> A_RWL<23> A_RWL<22> A_RWL<21> A_RWL<20> A_RWL<19> A_RWL<18> A_RWL<17> A_RWL<16> B_BLC<1> B_BLC<0> B_BLC<3> B_BLC<2> B_BLT<1> B_BLT<0> B_BLT<3> B_BLT<2> B_LWL<31> B_LWL<30> B_LWL<29> B_LWL<28> B_LWL<27> B_LWL<26> B_LWL<25> B_LWL<24> B_LWL<23> B_LWL<22> B_LWL<21> B_LWL<20> B_LWL<19> B_LWL<18> B_LWL<17> B_LWL<16> B_RWL<31> B_RWL<30> B_RWL<29> B_RWL<28> B_RWL<27> B_RWL<26> B_RWL<25> B_RWL<24> B_RWL<23> B_RWL<22> B_RWL<21> B_RWL<20> B_RWL<19> B_RWL<18> B_RWL<17> B_RWL<16> VDD_CORE VSS / RM_IHPSG13_512x16_c2_2P_BITKIT_16x2_SRAM +XRAM<1> A_BLC_BOT<1> A_BLC_BOT<0> A_BLC<1> A_BLC<0> A_BLT_BOT<1> A_BLT_BOT<0> A_BLT<1> A_BLT<0> A_LWL<15> A_LWL<14> A_LWL<13> A_LWL<12> A_LWL<11> A_LWL<10> A_LWL<9> A_LWL<8> A_LWL<7> A_LWL<6> A_LWL<5> A_LWL<4> A_LWL<3> A_LWL<2> A_LWL<1> A_LWL<0> A_RWL<15> A_RWL<14> A_RWL<13> A_RWL<12> A_RWL<11> A_RWL<10> A_RWL<9> A_RWL<8> A_RWL<7> A_RWL<6> A_RWL<5> A_RWL<4> A_RWL<3> A_RWL<2> A_RWL<1> A_RWL<0> B_BLC_BOT<1> B_BLC_BOT<0> B_BLC<1> B_BLC<0> B_BLT_BOT<1> B_BLT_BOT<0> B_BLT<1> B_BLT<0> B_LWL<15> B_LWL<14> B_LWL<13> B_LWL<12> B_LWL<11> B_LWL<10> B_LWL<9> B_LWL<8> B_LWL<7> B_LWL<6> B_LWL<5> B_LWL<4> B_LWL<3> B_LWL<2> B_LWL<1> B_LWL<0> B_RWL<15> B_RWL<14> B_RWL<13> B_RWL<12> B_RWL<11> B_RWL<10> B_RWL<9> B_RWL<8> B_RWL<7> B_RWL<6> B_RWL<5> B_RWL<4> B_RWL<3> B_RWL<2> B_RWL<1> B_RWL<0> VDD_CORE VSS / RM_IHPSG13_512x16_c2_2P_BITKIT_16x2_SRAM +XEDGE<1> A_BLC_TOP<1> A_BLC_TOP<0> A_BLT_TOP<1> A_BLT_TOP<0> B_BLC_TOP<1> B_BLC_TOP<0> B_BLT_TOP<1> B_BLT_TOP<0> VDD_CORE VSS / RM_IHPSG13_512x16_c2_2P_BITKIT_16x2_EDGE_TB +XEDGE<0> A_BLC_BOT<1> A_BLC_BOT<0> A_BLT_BOT<1> A_BLT_BOT<0> B_BLC_BOT<1> B_BLC_BOT<0> B_BLT_BOT<1> B_BLT_BOT<0> VDD_CORE VSS / RM_IHPSG13_512x16_c2_2P_BITKIT_16x2_EDGE_TB +.ENDS + + + + +.SUBCKT RM_IHPSG13_512x16_c2_2P_MATRIX_pcell_1 A_BLC<31> A_BLC<30> A_BLC<29> A_BLC<28> A_BLC<27> A_BLC<26> A_BLC<25> A_BLC<24> A_BLC<23> A_BLC<22> A_BLC<21> A_BLC<20> A_BLC<19> A_BLC<18> A_BLC<17> A_BLC<16> A_BLC<15> A_BLC<14> A_BLC<13> A_BLC<12> A_BLC<11> A_BLC<10> A_BLC<9> A_BLC<8> A_BLC<7> A_BLC<6> A_BLC<5> A_BLC<4> A_BLC<3> A_BLC<2> A_BLC<1> A_BLC<0> A_BLT<31> A_BLT<30> A_BLT<29> A_BLT<28> A_BLT<27> A_BLT<26> A_BLT<25> A_BLT<24> A_BLT<23> A_BLT<22> A_BLT<21> A_BLT<20> A_BLT<19> A_BLT<18> A_BLT<17> A_BLT<16> A_BLT<15> A_BLT<14> A_BLT<13> A_BLT<12> A_BLT<11> A_BLT<10> A_BLT<9> A_BLT<8> A_BLT<7> A_BLT<6> A_BLT<5> A_BLT<4> A_BLT<3> A_BLT<2> A_BLT<1> A_BLT<0> A_WL<127> A_WL<126> A_WL<125> A_WL<124> A_WL<123> A_WL<122> A_WL<121> A_WL<120> A_WL<119> A_WL<118> A_WL<117> A_WL<116> A_WL<115> A_WL<114> A_WL<113> A_WL<112> A_WL<111> A_WL<110> A_WL<109> A_WL<108> A_WL<107> A_WL<106> A_WL<105> A_WL<104> A_WL<103> A_WL<102> A_WL<101> A_WL<100> A_WL<99> A_WL<98> A_WL<97> A_WL<96> A_WL<95> A_WL<94> A_WL<93> A_WL<92> A_WL<91> A_WL<90> A_WL<89> A_WL<88> A_WL<87> A_WL<86> A_WL<85> A_WL<84> A_WL<83> A_WL<82> A_WL<81> A_WL<80> A_WL<79> A_WL<78> A_WL<77> A_WL<76> A_WL<75> A_WL<74> A_WL<73> A_WL<72> A_WL<71> A_WL<70> A_WL<69> A_WL<68> A_WL<67> A_WL<66> A_WL<65> A_WL<64> A_WL<63> A_WL<62> A_WL<61> A_WL<60> A_WL<59> A_WL<58> A_WL<57> A_WL<56> A_WL<55> A_WL<54> A_WL<53> A_WL<52> A_WL<51> A_WL<50> A_WL<49> A_WL<48> A_WL<47> A_WL<46> A_WL<45> A_WL<44> A_WL<43> A_WL<42> A_WL<41> A_WL<40> A_WL<39> A_WL<38> A_WL<37> A_WL<36> A_WL<35> A_WL<34> A_WL<33> A_WL<32> A_WL<31> A_WL<30> A_WL<29> A_WL<28> A_WL<27> A_WL<26> A_WL<25> A_WL<24> A_WL<23> A_WL<22> A_WL<21> A_WL<20> A_WL<19> A_WL<18> A_WL<17> A_WL<16> A_WL<15> A_WL<14> A_WL<13> A_WL<12> A_WL<11> A_WL<10> A_WL<9> A_WL<8> A_WL<7> A_WL<6> A_WL<5> A_WL<4> A_WL<3> A_WL<2> A_WL<1> A_WL<0> B_BLC<31> B_BLC<30> B_BLC<29> B_BLC<28> B_BLC<27> B_BLC<26> B_BLC<25> B_BLC<24> B_BLC<23> B_BLC<22> B_BLC<21> B_BLC<20> B_BLC<19> B_BLC<18> B_BLC<17> B_BLC<16> B_BLC<15> B_BLC<14> B_BLC<13> B_BLC<12> B_BLC<11> B_BLC<10> B_BLC<9> B_BLC<8> B_BLC<7> B_BLC<6> B_BLC<5> B_BLC<4> B_BLC<3> B_BLC<2> B_BLC<1> B_BLC<0> B_BLT<31> B_BLT<30> B_BLT<29> B_BLT<28> B_BLT<27> B_BLT<26> B_BLT<25> B_BLT<24> B_BLT<23> B_BLT<22> B_BLT<21> B_BLT<20> B_BLT<19> B_BLT<18> B_BLT<17> B_BLT<16> B_BLT<15> B_BLT<14> B_BLT<13> B_BLT<12> B_BLT<11> B_BLT<10> B_BLT<9> B_BLT<8> B_BLT<7> B_BLT<6> B_BLT<5> B_BLT<4> B_BLT<3> B_BLT<2> B_BLT<1> B_BLT<0> B_WL<127> B_WL<126> B_WL<125> B_WL<124> B_WL<123> B_WL<122> B_WL<121> B_WL<120> B_WL<119> B_WL<118> B_WL<117> B_WL<116> B_WL<115> B_WL<114> B_WL<113> B_WL<112> B_WL<111> B_WL<110> B_WL<109> B_WL<108> B_WL<107> B_WL<106> B_WL<105> B_WL<104> B_WL<103> B_WL<102> B_WL<101> B_WL<100> B_WL<99> B_WL<98> B_WL<97> B_WL<96> B_WL<95> B_WL<94> B_WL<93> B_WL<92> B_WL<91> B_WL<90> B_WL<89> B_WL<88> B_WL<87> B_WL<86> B_WL<85> B_WL<84> B_WL<83> B_WL<82> B_WL<81> B_WL<80> B_WL<79> B_WL<78> B_WL<77> B_WL<76> B_WL<75> B_WL<74> B_WL<73> B_WL<72> B_WL<71> B_WL<70> B_WL<69> B_WL<68> B_WL<67> B_WL<66> B_WL<65> B_WL<64> B_WL<63> B_WL<62> B_WL<61> B_WL<60> B_WL<59> B_WL<58> B_WL<57> B_WL<56> B_WL<55> B_WL<54> B_WL<53> B_WL<52> B_WL<51> B_WL<50> B_WL<49> B_WL<48> B_WL<47> B_WL<46> B_WL<45> B_WL<44> B_WL<43> B_WL<42> B_WL<41> B_WL<40> B_WL<39> B_WL<38> B_WL<37> B_WL<36> B_WL<35> B_WL<34> B_WL<33> B_WL<32> B_WL<31> B_WL<30> B_WL<29> B_WL<28> B_WL<27> B_WL<26> B_WL<25> B_WL<24> B_WL<23> B_WL<22> B_WL<21> B_WL<20> B_WL<19> B_WL<18> B_WL<17> B_WL<16> B_WL<15> B_WL<14> B_WL<13> B_WL<12> B_WL<11> B_WL<10> B_WL<9> B_WL<8> B_WL<7> B_WL<6> B_WL<5> B_WL<4> B_WL<3> B_WL<2> B_WL<1> B_WL<0> VDD_CORE VSS +XCORNER<3> VDD_CORE VSS / RM_IHPSG13_512x16_c2_2P_BITKIT_16x2_CORNER +XCORNER<2> VDD_CORE VSS / RM_IHPSG13_512x16_c2_2P_BITKIT_16x2_CORNER +XCORNER<1> VDD_CORE VSS / RM_IHPSG13_512x16_c2_2P_BITKIT_16x2_CORNER +XCORNER<0> VDD_CORE VSS / RM_IHPSG13_512x16_c2_2P_BITKIT_16x2_CORNER +XRAMEDGE_L<7> A_WL<127> A_WL<126> A_WL<125> A_WL<124> A_WL<123> A_WL<122> A_WL<121> A_WL<120> A_WL<119> A_WL<118> A_WL<117> A_WL<116> A_WL<115> A_WL<114> A_WL<113> A_WL<112> B_WL<127> B_WL<126> B_WL<125> B_WL<124> B_WL<123> B_WL<122> B_WL<121> B_WL<120> B_WL<119> B_WL<118> B_WL<117> B_WL<116> B_WL<115> B_WL<114> B_WL<113> B_WL<112> VDD_CORE VSS / RM_IHPSG13_512x16_c2_2P_BITKIT_16x2_EDGE_LR +XRAMEDGE_L<6> A_WL<111> A_WL<110> A_WL<109> A_WL<108> A_WL<107> A_WL<106> A_WL<105> A_WL<104> A_WL<103> A_WL<102> A_WL<101> A_WL<100> A_WL<99> A_WL<98> A_WL<97> A_WL<96> B_WL<111> B_WL<110> B_WL<109> B_WL<108> B_WL<107> B_WL<106> B_WL<105> B_WL<104> B_WL<103> B_WL<102> B_WL<101> B_WL<100> B_WL<99> B_WL<98> B_WL<97> B_WL<96> VDD_CORE VSS / RM_IHPSG13_512x16_c2_2P_BITKIT_16x2_EDGE_LR +XRAMEDGE_L<5> A_WL<95> A_WL<94> A_WL<93> A_WL<92> A_WL<91> A_WL<90> A_WL<89> A_WL<88> A_WL<87> A_WL<86> A_WL<85> A_WL<84> A_WL<83> A_WL<82> A_WL<81> A_WL<80> B_WL<95> B_WL<94> B_WL<93> B_WL<92> B_WL<91> B_WL<90> B_WL<89> B_WL<88> B_WL<87> B_WL<86> B_WL<85> B_WL<84> B_WL<83> B_WL<82> B_WL<81> B_WL<80> VDD_CORE VSS / RM_IHPSG13_512x16_c2_2P_BITKIT_16x2_EDGE_LR +XRAMEDGE_L<4> A_WL<79> A_WL<78> A_WL<77> A_WL<76> A_WL<75> A_WL<74> A_WL<73> A_WL<72> A_WL<71> A_WL<70> A_WL<69> A_WL<68> A_WL<67> A_WL<66> A_WL<65> A_WL<64> B_WL<79> B_WL<78> B_WL<77> B_WL<76> B_WL<75> B_WL<74> B_WL<73> B_WL<72> B_WL<71> B_WL<70> B_WL<69> B_WL<68> B_WL<67> B_WL<66> B_WL<65> B_WL<64> VDD_CORE VSS / RM_IHPSG13_512x16_c2_2P_BITKIT_16x2_EDGE_LR +XRAMEDGE_L<3> A_WL<63> A_WL<62> A_WL<61> A_WL<60> A_WL<59> A_WL<58> A_WL<57> A_WL<56> A_WL<55> A_WL<54> A_WL<53> A_WL<52> A_WL<51> A_WL<50> A_WL<49> A_WL<48> B_WL<63> B_WL<62> B_WL<61> B_WL<60> B_WL<59> B_WL<58> B_WL<57> B_WL<56> B_WL<55> B_WL<54> B_WL<53> B_WL<52> B_WL<51> B_WL<50> B_WL<49> B_WL<48> VDD_CORE VSS / RM_IHPSG13_512x16_c2_2P_BITKIT_16x2_EDGE_LR +XRAMEDGE_L<2> A_WL<47> A_WL<46> A_WL<45> A_WL<44> A_WL<43> A_WL<42> A_WL<41> A_WL<40> A_WL<39> A_WL<38> A_WL<37> A_WL<36> A_WL<35> A_WL<34> A_WL<33> A_WL<32> B_WL<47> B_WL<46> B_WL<45> B_WL<44> B_WL<43> B_WL<42> B_WL<41> B_WL<40> B_WL<39> B_WL<38> B_WL<37> B_WL<36> B_WL<35> B_WL<34> B_WL<33> B_WL<32> VDD_CORE VSS / RM_IHPSG13_512x16_c2_2P_BITKIT_16x2_EDGE_LR +XRAMEDGE_L<1> A_WL<31> A_WL<30> A_WL<29> A_WL<28> A_WL<27> A_WL<26> A_WL<25> A_WL<24> A_WL<23> A_WL<22> A_WL<21> A_WL<20> A_WL<19> A_WL<18> A_WL<17> A_WL<16> B_WL<31> B_WL<30> B_WL<29> B_WL<28> B_WL<27> B_WL<26> B_WL<25> B_WL<24> B_WL<23> B_WL<22> B_WL<21> B_WL<20> B_WL<19> B_WL<18> B_WL<17> B_WL<16> VDD_CORE VSS / RM_IHPSG13_512x16_c2_2P_BITKIT_16x2_EDGE_LR +XRAMEDGE_L<0> A_WL<15> A_WL<14> A_WL<13> A_WL<12> A_WL<11> A_WL<10> A_WL<9> A_WL<8> A_WL<7> A_WL<6> A_WL<5> A_WL<4> A_WL<3> A_WL<2> A_WL<1> A_WL<0> B_WL<15> B_WL<14> B_WL<13> B_WL<12> B_WL<11> B_WL<10> B_WL<9> B_WL<8> B_WL<7> B_WL<6> B_WL<5> B_WL<4> B_WL<3> B_WL<2> B_WL<1> B_WL<0> VDD_CORE VSS / RM_IHPSG13_512x16_c2_2P_BITKIT_16x2_EDGE_LR +XRAMEDGE_R<7> A_IWL<2047> A_IWL<2046> A_IWL<2045> A_IWL<2044> A_IWL<2043> A_IWL<2042> A_IWL<2041> A_IWL<2040> A_IWL<2039> A_IWL<2038> A_IWL<2037> A_IWL<2036> A_IWL<2035> A_IWL<2034> A_IWL<2033> A_IWL<2032> B_IWL<2047> B_IWL<2046> B_IWL<2045> B_IWL<2044> B_IWL<2043> B_IWL<2042> B_IWL<2041> B_IWL<2040> B_IWL<2039> B_IWL<2038> B_IWL<2037> B_IWL<2036> B_IWL<2035> B_IWL<2034> B_IWL<2033> B_IWL<2032> VDD_CORE VSS / RM_IHPSG13_512x16_c2_2P_BITKIT_16x2_EDGE_LR +XRAMEDGE_R<6> A_IWL<2031> A_IWL<2030> A_IWL<2029> A_IWL<2028> A_IWL<2027> A_IWL<2026> A_IWL<2025> A_IWL<2024> A_IWL<2023> A_IWL<2022> A_IWL<2021> A_IWL<2020> A_IWL<2019> A_IWL<2018> A_IWL<2017> A_IWL<2016> B_IWL<2031> B_IWL<2030> B_IWL<2029> B_IWL<2028> B_IWL<2027> B_IWL<2026> B_IWL<2025> B_IWL<2024> B_IWL<2023> B_IWL<2022> B_IWL<2021> B_IWL<2020> B_IWL<2019> B_IWL<2018> B_IWL<2017> B_IWL<2016> VDD_CORE VSS / RM_IHPSG13_512x16_c2_2P_BITKIT_16x2_EDGE_LR +XRAMEDGE_R<5> A_IWL<2015> A_IWL<2014> A_IWL<2013> A_IWL<2012> A_IWL<2011> A_IWL<2010> A_IWL<2009> A_IWL<2008> A_IWL<2007> A_IWL<2006> A_IWL<2005> A_IWL<2004> A_IWL<2003> A_IWL<2002> A_IWL<2001> A_IWL<2000> B_IWL<2015> B_IWL<2014> B_IWL<2013> B_IWL<2012> B_IWL<2011> B_IWL<2010> B_IWL<2009> B_IWL<2008> B_IWL<2007> B_IWL<2006> B_IWL<2005> B_IWL<2004> B_IWL<2003> B_IWL<2002> B_IWL<2001> B_IWL<2000> VDD_CORE VSS / RM_IHPSG13_512x16_c2_2P_BITKIT_16x2_EDGE_LR +XRAMEDGE_R<4> A_IWL<1999> A_IWL<1998> A_IWL<1997> A_IWL<1996> A_IWL<1995> A_IWL<1994> A_IWL<1993> A_IWL<1992> A_IWL<1991> A_IWL<1990> A_IWL<1989> A_IWL<1988> A_IWL<1987> A_IWL<1986> A_IWL<1985> A_IWL<1984> B_IWL<1999> B_IWL<1998> B_IWL<1997> B_IWL<1996> B_IWL<1995> B_IWL<1994> B_IWL<1993> B_IWL<1992> B_IWL<1991> B_IWL<1990> B_IWL<1989> B_IWL<1988> B_IWL<1987> B_IWL<1986> B_IWL<1985> B_IWL<1984> VDD_CORE VSS / RM_IHPSG13_512x16_c2_2P_BITKIT_16x2_EDGE_LR +XRAMEDGE_R<3> A_IWL<1983> A_IWL<1982> A_IWL<1981> A_IWL<1980> A_IWL<1979> A_IWL<1978> A_IWL<1977> A_IWL<1976> A_IWL<1975> A_IWL<1974> A_IWL<1973> A_IWL<1972> A_IWL<1971> A_IWL<1970> A_IWL<1969> A_IWL<1968> B_IWL<1983> B_IWL<1982> B_IWL<1981> B_IWL<1980> B_IWL<1979> B_IWL<1978> B_IWL<1977> B_IWL<1976> B_IWL<1975> B_IWL<1974> B_IWL<1973> B_IWL<1972> B_IWL<1971> B_IWL<1970> B_IWL<1969> B_IWL<1968> VDD_CORE VSS / RM_IHPSG13_512x16_c2_2P_BITKIT_16x2_EDGE_LR +XRAMEDGE_R<2> A_IWL<1967> A_IWL<1966> A_IWL<1965> A_IWL<1964> A_IWL<1963> A_IWL<1962> A_IWL<1961> A_IWL<1960> A_IWL<1959> A_IWL<1958> A_IWL<1957> A_IWL<1956> A_IWL<1955> A_IWL<1954> A_IWL<1953> A_IWL<1952> B_IWL<1967> B_IWL<1966> B_IWL<1965> B_IWL<1964> B_IWL<1963> B_IWL<1962> B_IWL<1961> B_IWL<1960> B_IWL<1959> B_IWL<1958> B_IWL<1957> B_IWL<1956> B_IWL<1955> B_IWL<1954> B_IWL<1953> B_IWL<1952> VDD_CORE VSS / RM_IHPSG13_512x16_c2_2P_BITKIT_16x2_EDGE_LR +XRAMEDGE_R<1> A_IWL<1951> A_IWL<1950> A_IWL<1949> A_IWL<1948> A_IWL<1947> A_IWL<1946> A_IWL<1945> A_IWL<1944> A_IWL<1943> A_IWL<1942> A_IWL<1941> A_IWL<1940> A_IWL<1939> A_IWL<1938> A_IWL<1937> A_IWL<1936> B_IWL<1951> B_IWL<1950> B_IWL<1949> B_IWL<1948> B_IWL<1947> B_IWL<1946> B_IWL<1945> B_IWL<1944> B_IWL<1943> B_IWL<1942> B_IWL<1941> B_IWL<1940> B_IWL<1939> B_IWL<1938> B_IWL<1937> B_IWL<1936> VDD_CORE VSS / RM_IHPSG13_512x16_c2_2P_BITKIT_16x2_EDGE_LR +XRAMEDGE_R<0> A_IWL<1935> A_IWL<1934> A_IWL<1933> A_IWL<1932> A_IWL<1931> A_IWL<1930> A_IWL<1929> A_IWL<1928> A_IWL<1927> A_IWL<1926> A_IWL<1925> A_IWL<1924> A_IWL<1923> A_IWL<1922> A_IWL<1921> A_IWL<1920> B_IWL<1935> B_IWL<1934> B_IWL<1933> B_IWL<1932> B_IWL<1931> B_IWL<1930> B_IWL<1929> B_IWL<1928> B_IWL<1927> B_IWL<1926> B_IWL<1925> B_IWL<1924> B_IWL<1923> B_IWL<1922> B_IWL<1921> B_IWL<1920> VDD_CORE VSS / RM_IHPSG13_512x16_c2_2P_BITKIT_16x2_EDGE_LR +XCOL<15> A_BLC<31> A_BLC<30> A_BLC_TOP<31> A_BLC_TOP<30> A_BLT<31> A_BLT<30> A_BLT_TOP<31> A_BLT_TOP<30> A_IWL<1919> A_IWL<1918> A_IWL<1917> A_IWL<1916> A_IWL<1915> A_IWL<1914> A_IWL<1913> A_IWL<1912> A_IWL<1911> A_IWL<1910> A_IWL<1909> A_IWL<1908> A_IWL<1907> A_IWL<1906> A_IWL<1905> A_IWL<1904> A_IWL<1903> A_IWL<1902> A_IWL<1901> A_IWL<1900> A_IWL<1899> A_IWL<1898> A_IWL<1897> A_IWL<1896> A_IWL<1895> A_IWL<1894> A_IWL<1893> A_IWL<1892> A_IWL<1891> A_IWL<1890> A_IWL<1889> A_IWL<1888> A_IWL<1887> A_IWL<1886> A_IWL<1885> A_IWL<1884> A_IWL<1883> A_IWL<1882> A_IWL<1881> A_IWL<1880> A_IWL<1879> A_IWL<1878> A_IWL<1877> A_IWL<1876> A_IWL<1875> A_IWL<1874> A_IWL<1873> A_IWL<1872> A_IWL<1871> A_IWL<1870> A_IWL<1869> A_IWL<1868> A_IWL<1867> A_IWL<1866> A_IWL<1865> A_IWL<1864> A_IWL<1863> A_IWL<1862> A_IWL<1861> A_IWL<1860> A_IWL<1859> A_IWL<1858> A_IWL<1857> A_IWL<1856> A_IWL<1855> A_IWL<1854> A_IWL<1853> A_IWL<1852> A_IWL<1851> A_IWL<1850> A_IWL<1849> A_IWL<1848> A_IWL<1847> A_IWL<1846> A_IWL<1845> A_IWL<1844> A_IWL<1843> A_IWL<1842> A_IWL<1841> A_IWL<1840> A_IWL<1839> A_IWL<1838> A_IWL<1837> A_IWL<1836> A_IWL<1835> A_IWL<1834> A_IWL<1833> A_IWL<1832> A_IWL<1831> A_IWL<1830> A_IWL<1829> A_IWL<1828> A_IWL<1827> A_IWL<1826> A_IWL<1825> A_IWL<1824> A_IWL<1823> A_IWL<1822> A_IWL<1821> A_IWL<1820> A_IWL<1819> A_IWL<1818> A_IWL<1817> A_IWL<1816> A_IWL<1815> A_IWL<1814> A_IWL<1813> A_IWL<1812> A_IWL<1811> A_IWL<1810> A_IWL<1809> A_IWL<1808> A_IWL<1807> A_IWL<1806> A_IWL<1805> A_IWL<1804> A_IWL<1803> A_IWL<1802> A_IWL<1801> A_IWL<1800> A_IWL<1799> A_IWL<1798> A_IWL<1797> A_IWL<1796> A_IWL<1795> A_IWL<1794> A_IWL<1793> A_IWL<1792> A_IWL<2047> A_IWL<2046> A_IWL<2045> A_IWL<2044> A_IWL<2043> A_IWL<2042> A_IWL<2041> A_IWL<2040> A_IWL<2039> A_IWL<2038> A_IWL<2037> A_IWL<2036> A_IWL<2035> A_IWL<2034> A_IWL<2033> A_IWL<2032> A_IWL<2031> A_IWL<2030> A_IWL<2029> A_IWL<2028> A_IWL<2027> A_IWL<2026> A_IWL<2025> A_IWL<2024> A_IWL<2023> A_IWL<2022> A_IWL<2021> A_IWL<2020> A_IWL<2019> A_IWL<2018> A_IWL<2017> A_IWL<2016> A_IWL<2015> A_IWL<2014> A_IWL<2013> A_IWL<2012> A_IWL<2011> A_IWL<2010> A_IWL<2009> A_IWL<2008> A_IWL<2007> A_IWL<2006> A_IWL<2005> A_IWL<2004> A_IWL<2003> A_IWL<2002> A_IWL<2001> A_IWL<2000> A_IWL<1999> A_IWL<1998> A_IWL<1997> A_IWL<1996> A_IWL<1995> A_IWL<1994> A_IWL<1993> A_IWL<1992> A_IWL<1991> A_IWL<1990> A_IWL<1989> A_IWL<1988> A_IWL<1987> A_IWL<1986> A_IWL<1985> A_IWL<1984> A_IWL<1983> A_IWL<1982> A_IWL<1981> A_IWL<1980> A_IWL<1979> A_IWL<1978> A_IWL<1977> A_IWL<1976> A_IWL<1975> A_IWL<1974> A_IWL<1973> A_IWL<1972> A_IWL<1971> A_IWL<1970> A_IWL<1969> A_IWL<1968> A_IWL<1967> A_IWL<1966> A_IWL<1965> A_IWL<1964> A_IWL<1963> A_IWL<1962> A_IWL<1961> A_IWL<1960> A_IWL<1959> A_IWL<1958> A_IWL<1957> A_IWL<1956> A_IWL<1955> A_IWL<1954> A_IWL<1953> A_IWL<1952> A_IWL<1951> A_IWL<1950> A_IWL<1949> A_IWL<1948> A_IWL<1947> A_IWL<1946> A_IWL<1945> A_IWL<1944> A_IWL<1943> A_IWL<1942> A_IWL<1941> A_IWL<1940> A_IWL<1939> A_IWL<1938> A_IWL<1937> A_IWL<1936> A_IWL<1935> A_IWL<1934> A_IWL<1933> A_IWL<1932> A_IWL<1931> A_IWL<1930> A_IWL<1929> A_IWL<1928> A_IWL<1927> A_IWL<1926> A_IWL<1925> A_IWL<1924> A_IWL<1923> A_IWL<1922> A_IWL<1921> A_IWL<1920> B_BLC<31> B_BLC<30> B_BLC_TOP<31> B_BLC_TOP<30> B_BLT<31> B_BLT<30> B_BLT_TOP<31> B_BLT_TOP<30> B_IWL<1919> B_IWL<1918> B_IWL<1917> B_IWL<1916> B_IWL<1915> B_IWL<1914> B_IWL<1913> B_IWL<1912> B_IWL<1911> B_IWL<1910> B_IWL<1909> B_IWL<1908> B_IWL<1907> B_IWL<1906> B_IWL<1905> B_IWL<1904> B_IWL<1903> B_IWL<1902> B_IWL<1901> B_IWL<1900> B_IWL<1899> B_IWL<1898> B_IWL<1897> B_IWL<1896> B_IWL<1895> B_IWL<1894> B_IWL<1893> B_IWL<1892> B_IWL<1891> B_IWL<1890> B_IWL<1889> B_IWL<1888> B_IWL<1887> B_IWL<1886> B_IWL<1885> B_IWL<1884> B_IWL<1883> B_IWL<1882> B_IWL<1881> B_IWL<1880> B_IWL<1879> B_IWL<1878> B_IWL<1877> B_IWL<1876> B_IWL<1875> B_IWL<1874> B_IWL<1873> B_IWL<1872> B_IWL<1871> B_IWL<1870> B_IWL<1869> B_IWL<1868> B_IWL<1867> B_IWL<1866> B_IWL<1865> B_IWL<1864> B_IWL<1863> B_IWL<1862> B_IWL<1861> B_IWL<1860> B_IWL<1859> B_IWL<1858> B_IWL<1857> B_IWL<1856> B_IWL<1855> B_IWL<1854> B_IWL<1853> B_IWL<1852> B_IWL<1851> B_IWL<1850> B_IWL<1849> B_IWL<1848> B_IWL<1847> B_IWL<1846> B_IWL<1845> B_IWL<1844> B_IWL<1843> B_IWL<1842> B_IWL<1841> B_IWL<1840> B_IWL<1839> B_IWL<1838> B_IWL<1837> B_IWL<1836> B_IWL<1835> B_IWL<1834> B_IWL<1833> B_IWL<1832> B_IWL<1831> B_IWL<1830> B_IWL<1829> B_IWL<1828> B_IWL<1827> B_IWL<1826> B_IWL<1825> B_IWL<1824> B_IWL<1823> B_IWL<1822> B_IWL<1821> B_IWL<1820> B_IWL<1819> B_IWL<1818> B_IWL<1817> B_IWL<1816> B_IWL<1815> B_IWL<1814> B_IWL<1813> B_IWL<1812> B_IWL<1811> B_IWL<1810> B_IWL<1809> B_IWL<1808> B_IWL<1807> B_IWL<1806> B_IWL<1805> B_IWL<1804> B_IWL<1803> B_IWL<1802> B_IWL<1801> B_IWL<1800> B_IWL<1799> B_IWL<1798> B_IWL<1797> B_IWL<1796> B_IWL<1795> B_IWL<1794> B_IWL<1793> B_IWL<1792> B_IWL<2047> B_IWL<2046> B_IWL<2045> B_IWL<2044> B_IWL<2043> B_IWL<2042> B_IWL<2041> B_IWL<2040> B_IWL<2039> B_IWL<2038> B_IWL<2037> B_IWL<2036> B_IWL<2035> B_IWL<2034> B_IWL<2033> B_IWL<2032> B_IWL<2031> B_IWL<2030> B_IWL<2029> B_IWL<2028> B_IWL<2027> B_IWL<2026> B_IWL<2025> B_IWL<2024> B_IWL<2023> B_IWL<2022> B_IWL<2021> B_IWL<2020> B_IWL<2019> B_IWL<2018> B_IWL<2017> B_IWL<2016> B_IWL<2015> B_IWL<2014> B_IWL<2013> B_IWL<2012> B_IWL<2011> B_IWL<2010> B_IWL<2009> B_IWL<2008> B_IWL<2007> B_IWL<2006> B_IWL<2005> B_IWL<2004> B_IWL<2003> B_IWL<2002> B_IWL<2001> B_IWL<2000> B_IWL<1999> B_IWL<1998> B_IWL<1997> B_IWL<1996> B_IWL<1995> B_IWL<1994> B_IWL<1993> B_IWL<1992> B_IWL<1991> B_IWL<1990> B_IWL<1989> B_IWL<1988> B_IWL<1987> B_IWL<1986> B_IWL<1985> B_IWL<1984> B_IWL<1983> B_IWL<1982> B_IWL<1981> B_IWL<1980> B_IWL<1979> B_IWL<1978> B_IWL<1977> B_IWL<1976> B_IWL<1975> B_IWL<1974> B_IWL<1973> B_IWL<1972> B_IWL<1971> B_IWL<1970> B_IWL<1969> B_IWL<1968> B_IWL<1967> B_IWL<1966> B_IWL<1965> B_IWL<1964> B_IWL<1963> B_IWL<1962> B_IWL<1961> B_IWL<1960> B_IWL<1959> B_IWL<1958> B_IWL<1957> B_IWL<1956> B_IWL<1955> B_IWL<1954> B_IWL<1953> B_IWL<1952> B_IWL<1951> B_IWL<1950> B_IWL<1949> B_IWL<1948> B_IWL<1947> B_IWL<1946> B_IWL<1945> B_IWL<1944> B_IWL<1943> B_IWL<1942> B_IWL<1941> B_IWL<1940> B_IWL<1939> B_IWL<1938> B_IWL<1937> B_IWL<1936> B_IWL<1935> B_IWL<1934> B_IWL<1933> B_IWL<1932> B_IWL<1931> B_IWL<1930> B_IWL<1929> B_IWL<1928> B_IWL<1927> B_IWL<1926> B_IWL<1925> B_IWL<1924> B_IWL<1923> B_IWL<1922> B_IWL<1921> B_IWL<1920> VDD_CORE VSS / RM_IHPSG13_512x16_c2_2P_COLUMN_pcell_0 +XCOL<14> A_BLC<29> A_BLC<28> A_BLC_TOP<29> A_BLC_TOP<28> A_BLT<29> A_BLT<28> A_BLT_TOP<29> A_BLT_TOP<28> A_IWL<1791> A_IWL<1790> A_IWL<1789> A_IWL<1788> A_IWL<1787> A_IWL<1786> A_IWL<1785> A_IWL<1784> A_IWL<1783> A_IWL<1782> A_IWL<1781> A_IWL<1780> A_IWL<1779> A_IWL<1778> A_IWL<1777> A_IWL<1776> A_IWL<1775> A_IWL<1774> A_IWL<1773> A_IWL<1772> A_IWL<1771> A_IWL<1770> A_IWL<1769> A_IWL<1768> A_IWL<1767> A_IWL<1766> A_IWL<1765> A_IWL<1764> A_IWL<1763> A_IWL<1762> A_IWL<1761> A_IWL<1760> A_IWL<1759> A_IWL<1758> A_IWL<1757> A_IWL<1756> A_IWL<1755> A_IWL<1754> A_IWL<1753> A_IWL<1752> A_IWL<1751> A_IWL<1750> A_IWL<1749> A_IWL<1748> A_IWL<1747> A_IWL<1746> A_IWL<1745> A_IWL<1744> A_IWL<1743> A_IWL<1742> A_IWL<1741> A_IWL<1740> A_IWL<1739> A_IWL<1738> A_IWL<1737> A_IWL<1736> A_IWL<1735> A_IWL<1734> A_IWL<1733> A_IWL<1732> A_IWL<1731> A_IWL<1730> A_IWL<1729> A_IWL<1728> A_IWL<1727> A_IWL<1726> A_IWL<1725> A_IWL<1724> A_IWL<1723> A_IWL<1722> A_IWL<1721> A_IWL<1720> A_IWL<1719> A_IWL<1718> A_IWL<1717> A_IWL<1716> A_IWL<1715> A_IWL<1714> A_IWL<1713> A_IWL<1712> A_IWL<1711> A_IWL<1710> A_IWL<1709> A_IWL<1708> A_IWL<1707> A_IWL<1706> A_IWL<1705> A_IWL<1704> A_IWL<1703> A_IWL<1702> A_IWL<1701> A_IWL<1700> A_IWL<1699> A_IWL<1698> A_IWL<1697> A_IWL<1696> A_IWL<1695> A_IWL<1694> A_IWL<1693> A_IWL<1692> A_IWL<1691> A_IWL<1690> A_IWL<1689> A_IWL<1688> A_IWL<1687> A_IWL<1686> A_IWL<1685> A_IWL<1684> A_IWL<1683> A_IWL<1682> A_IWL<1681> A_IWL<1680> A_IWL<1679> A_IWL<1678> A_IWL<1677> A_IWL<1676> A_IWL<1675> A_IWL<1674> A_IWL<1673> A_IWL<1672> A_IWL<1671> A_IWL<1670> A_IWL<1669> A_IWL<1668> A_IWL<1667> A_IWL<1666> A_IWL<1665> A_IWL<1664> A_IWL<1919> A_IWL<1918> A_IWL<1917> A_IWL<1916> A_IWL<1915> A_IWL<1914> A_IWL<1913> A_IWL<1912> A_IWL<1911> A_IWL<1910> A_IWL<1909> A_IWL<1908> A_IWL<1907> A_IWL<1906> A_IWL<1905> A_IWL<1904> A_IWL<1903> A_IWL<1902> A_IWL<1901> A_IWL<1900> A_IWL<1899> A_IWL<1898> A_IWL<1897> A_IWL<1896> A_IWL<1895> A_IWL<1894> A_IWL<1893> A_IWL<1892> A_IWL<1891> A_IWL<1890> A_IWL<1889> A_IWL<1888> A_IWL<1887> A_IWL<1886> A_IWL<1885> A_IWL<1884> A_IWL<1883> A_IWL<1882> A_IWL<1881> A_IWL<1880> A_IWL<1879> A_IWL<1878> A_IWL<1877> A_IWL<1876> A_IWL<1875> A_IWL<1874> A_IWL<1873> A_IWL<1872> A_IWL<1871> A_IWL<1870> A_IWL<1869> A_IWL<1868> A_IWL<1867> A_IWL<1866> A_IWL<1865> A_IWL<1864> A_IWL<1863> A_IWL<1862> A_IWL<1861> A_IWL<1860> A_IWL<1859> A_IWL<1858> A_IWL<1857> A_IWL<1856> A_IWL<1855> A_IWL<1854> A_IWL<1853> A_IWL<1852> A_IWL<1851> A_IWL<1850> A_IWL<1849> A_IWL<1848> A_IWL<1847> A_IWL<1846> A_IWL<1845> A_IWL<1844> A_IWL<1843> A_IWL<1842> A_IWL<1841> A_IWL<1840> A_IWL<1839> A_IWL<1838> A_IWL<1837> A_IWL<1836> A_IWL<1835> A_IWL<1834> A_IWL<1833> A_IWL<1832> A_IWL<1831> A_IWL<1830> A_IWL<1829> A_IWL<1828> A_IWL<1827> A_IWL<1826> A_IWL<1825> A_IWL<1824> A_IWL<1823> A_IWL<1822> A_IWL<1821> A_IWL<1820> A_IWL<1819> A_IWL<1818> A_IWL<1817> A_IWL<1816> A_IWL<1815> A_IWL<1814> A_IWL<1813> A_IWL<1812> A_IWL<1811> A_IWL<1810> A_IWL<1809> A_IWL<1808> A_IWL<1807> A_IWL<1806> A_IWL<1805> A_IWL<1804> A_IWL<1803> A_IWL<1802> A_IWL<1801> A_IWL<1800> A_IWL<1799> A_IWL<1798> A_IWL<1797> A_IWL<1796> A_IWL<1795> A_IWL<1794> A_IWL<1793> A_IWL<1792> B_BLC<29> B_BLC<28> B_BLC_TOP<29> B_BLC_TOP<28> B_BLT<29> B_BLT<28> B_BLT_TOP<29> B_BLT_TOP<28> B_IWL<1791> B_IWL<1790> B_IWL<1789> B_IWL<1788> B_IWL<1787> B_IWL<1786> B_IWL<1785> B_IWL<1784> B_IWL<1783> B_IWL<1782> B_IWL<1781> B_IWL<1780> B_IWL<1779> B_IWL<1778> B_IWL<1777> B_IWL<1776> B_IWL<1775> B_IWL<1774> B_IWL<1773> B_IWL<1772> B_IWL<1771> B_IWL<1770> B_IWL<1769> B_IWL<1768> B_IWL<1767> B_IWL<1766> B_IWL<1765> B_IWL<1764> B_IWL<1763> B_IWL<1762> B_IWL<1761> B_IWL<1760> B_IWL<1759> B_IWL<1758> B_IWL<1757> B_IWL<1756> B_IWL<1755> B_IWL<1754> B_IWL<1753> B_IWL<1752> B_IWL<1751> B_IWL<1750> B_IWL<1749> B_IWL<1748> B_IWL<1747> B_IWL<1746> B_IWL<1745> B_IWL<1744> B_IWL<1743> B_IWL<1742> B_IWL<1741> B_IWL<1740> B_IWL<1739> B_IWL<1738> B_IWL<1737> B_IWL<1736> B_IWL<1735> B_IWL<1734> B_IWL<1733> B_IWL<1732> B_IWL<1731> B_IWL<1730> B_IWL<1729> B_IWL<1728> B_IWL<1727> B_IWL<1726> B_IWL<1725> B_IWL<1724> B_IWL<1723> B_IWL<1722> B_IWL<1721> B_IWL<1720> B_IWL<1719> B_IWL<1718> B_IWL<1717> B_IWL<1716> B_IWL<1715> B_IWL<1714> B_IWL<1713> B_IWL<1712> B_IWL<1711> B_IWL<1710> B_IWL<1709> B_IWL<1708> B_IWL<1707> B_IWL<1706> B_IWL<1705> B_IWL<1704> B_IWL<1703> B_IWL<1702> B_IWL<1701> B_IWL<1700> B_IWL<1699> B_IWL<1698> B_IWL<1697> B_IWL<1696> B_IWL<1695> B_IWL<1694> B_IWL<1693> B_IWL<1692> B_IWL<1691> B_IWL<1690> B_IWL<1689> B_IWL<1688> B_IWL<1687> B_IWL<1686> B_IWL<1685> B_IWL<1684> B_IWL<1683> B_IWL<1682> B_IWL<1681> B_IWL<1680> B_IWL<1679> B_IWL<1678> B_IWL<1677> B_IWL<1676> B_IWL<1675> B_IWL<1674> B_IWL<1673> B_IWL<1672> B_IWL<1671> B_IWL<1670> B_IWL<1669> B_IWL<1668> B_IWL<1667> B_IWL<1666> B_IWL<1665> B_IWL<1664> B_IWL<1919> B_IWL<1918> B_IWL<1917> B_IWL<1916> B_IWL<1915> B_IWL<1914> B_IWL<1913> B_IWL<1912> B_IWL<1911> B_IWL<1910> B_IWL<1909> B_IWL<1908> B_IWL<1907> B_IWL<1906> B_IWL<1905> B_IWL<1904> B_IWL<1903> B_IWL<1902> B_IWL<1901> B_IWL<1900> B_IWL<1899> B_IWL<1898> B_IWL<1897> B_IWL<1896> B_IWL<1895> B_IWL<1894> B_IWL<1893> B_IWL<1892> B_IWL<1891> B_IWL<1890> B_IWL<1889> B_IWL<1888> B_IWL<1887> B_IWL<1886> B_IWL<1885> B_IWL<1884> B_IWL<1883> B_IWL<1882> B_IWL<1881> B_IWL<1880> B_IWL<1879> B_IWL<1878> B_IWL<1877> B_IWL<1876> B_IWL<1875> B_IWL<1874> B_IWL<1873> B_IWL<1872> B_IWL<1871> B_IWL<1870> B_IWL<1869> B_IWL<1868> B_IWL<1867> B_IWL<1866> B_IWL<1865> B_IWL<1864> B_IWL<1863> B_IWL<1862> B_IWL<1861> B_IWL<1860> B_IWL<1859> B_IWL<1858> B_IWL<1857> B_IWL<1856> B_IWL<1855> B_IWL<1854> B_IWL<1853> B_IWL<1852> B_IWL<1851> B_IWL<1850> B_IWL<1849> B_IWL<1848> B_IWL<1847> B_IWL<1846> B_IWL<1845> B_IWL<1844> B_IWL<1843> B_IWL<1842> B_IWL<1841> B_IWL<1840> B_IWL<1839> B_IWL<1838> B_IWL<1837> B_IWL<1836> B_IWL<1835> B_IWL<1834> B_IWL<1833> B_IWL<1832> B_IWL<1831> B_IWL<1830> B_IWL<1829> B_IWL<1828> B_IWL<1827> B_IWL<1826> B_IWL<1825> B_IWL<1824> B_IWL<1823> B_IWL<1822> B_IWL<1821> B_IWL<1820> B_IWL<1819> B_IWL<1818> B_IWL<1817> B_IWL<1816> B_IWL<1815> B_IWL<1814> B_IWL<1813> B_IWL<1812> B_IWL<1811> B_IWL<1810> B_IWL<1809> B_IWL<1808> B_IWL<1807> B_IWL<1806> B_IWL<1805> B_IWL<1804> B_IWL<1803> B_IWL<1802> B_IWL<1801> B_IWL<1800> B_IWL<1799> B_IWL<1798> B_IWL<1797> B_IWL<1796> B_IWL<1795> B_IWL<1794> B_IWL<1793> B_IWL<1792> VDD_CORE VSS / RM_IHPSG13_512x16_c2_2P_COLUMN_pcell_0 +XCOL<13> A_BLC<27> A_BLC<26> A_BLC_TOP<27> A_BLC_TOP<26> A_BLT<27> A_BLT<26> A_BLT_TOP<27> A_BLT_TOP<26> A_IWL<1663> A_IWL<1662> A_IWL<1661> A_IWL<1660> A_IWL<1659> A_IWL<1658> A_IWL<1657> A_IWL<1656> A_IWL<1655> A_IWL<1654> A_IWL<1653> A_IWL<1652> A_IWL<1651> A_IWL<1650> A_IWL<1649> A_IWL<1648> A_IWL<1647> A_IWL<1646> A_IWL<1645> A_IWL<1644> A_IWL<1643> A_IWL<1642> A_IWL<1641> A_IWL<1640> A_IWL<1639> A_IWL<1638> A_IWL<1637> A_IWL<1636> A_IWL<1635> A_IWL<1634> A_IWL<1633> A_IWL<1632> A_IWL<1631> A_IWL<1630> A_IWL<1629> A_IWL<1628> A_IWL<1627> A_IWL<1626> A_IWL<1625> A_IWL<1624> A_IWL<1623> A_IWL<1622> A_IWL<1621> A_IWL<1620> A_IWL<1619> A_IWL<1618> A_IWL<1617> A_IWL<1616> A_IWL<1615> A_IWL<1614> A_IWL<1613> A_IWL<1612> A_IWL<1611> A_IWL<1610> A_IWL<1609> A_IWL<1608> A_IWL<1607> A_IWL<1606> A_IWL<1605> A_IWL<1604> A_IWL<1603> A_IWL<1602> A_IWL<1601> A_IWL<1600> A_IWL<1599> A_IWL<1598> A_IWL<1597> A_IWL<1596> A_IWL<1595> A_IWL<1594> A_IWL<1593> A_IWL<1592> A_IWL<1591> A_IWL<1590> A_IWL<1589> A_IWL<1588> A_IWL<1587> A_IWL<1586> A_IWL<1585> A_IWL<1584> A_IWL<1583> A_IWL<1582> A_IWL<1581> A_IWL<1580> A_IWL<1579> A_IWL<1578> A_IWL<1577> A_IWL<1576> A_IWL<1575> A_IWL<1574> A_IWL<1573> A_IWL<1572> A_IWL<1571> A_IWL<1570> A_IWL<1569> A_IWL<1568> A_IWL<1567> A_IWL<1566> A_IWL<1565> A_IWL<1564> A_IWL<1563> A_IWL<1562> A_IWL<1561> A_IWL<1560> A_IWL<1559> A_IWL<1558> A_IWL<1557> A_IWL<1556> A_IWL<1555> A_IWL<1554> A_IWL<1553> A_IWL<1552> A_IWL<1551> A_IWL<1550> A_IWL<1549> A_IWL<1548> A_IWL<1547> A_IWL<1546> A_IWL<1545> A_IWL<1544> A_IWL<1543> A_IWL<1542> A_IWL<1541> A_IWL<1540> A_IWL<1539> A_IWL<1538> A_IWL<1537> A_IWL<1536> A_IWL<1791> A_IWL<1790> A_IWL<1789> A_IWL<1788> A_IWL<1787> A_IWL<1786> A_IWL<1785> A_IWL<1784> A_IWL<1783> A_IWL<1782> A_IWL<1781> A_IWL<1780> A_IWL<1779> A_IWL<1778> A_IWL<1777> A_IWL<1776> A_IWL<1775> A_IWL<1774> A_IWL<1773> A_IWL<1772> A_IWL<1771> A_IWL<1770> A_IWL<1769> A_IWL<1768> A_IWL<1767> A_IWL<1766> A_IWL<1765> A_IWL<1764> A_IWL<1763> A_IWL<1762> A_IWL<1761> A_IWL<1760> A_IWL<1759> A_IWL<1758> A_IWL<1757> A_IWL<1756> A_IWL<1755> A_IWL<1754> A_IWL<1753> A_IWL<1752> A_IWL<1751> A_IWL<1750> A_IWL<1749> A_IWL<1748> A_IWL<1747> A_IWL<1746> A_IWL<1745> A_IWL<1744> A_IWL<1743> A_IWL<1742> A_IWL<1741> A_IWL<1740> A_IWL<1739> A_IWL<1738> A_IWL<1737> A_IWL<1736> A_IWL<1735> A_IWL<1734> A_IWL<1733> A_IWL<1732> A_IWL<1731> A_IWL<1730> A_IWL<1729> A_IWL<1728> A_IWL<1727> A_IWL<1726> A_IWL<1725> A_IWL<1724> A_IWL<1723> A_IWL<1722> A_IWL<1721> A_IWL<1720> A_IWL<1719> A_IWL<1718> A_IWL<1717> A_IWL<1716> A_IWL<1715> A_IWL<1714> A_IWL<1713> A_IWL<1712> A_IWL<1711> A_IWL<1710> A_IWL<1709> A_IWL<1708> A_IWL<1707> A_IWL<1706> A_IWL<1705> A_IWL<1704> A_IWL<1703> A_IWL<1702> A_IWL<1701> A_IWL<1700> A_IWL<1699> A_IWL<1698> A_IWL<1697> A_IWL<1696> A_IWL<1695> A_IWL<1694> A_IWL<1693> A_IWL<1692> A_IWL<1691> A_IWL<1690> A_IWL<1689> A_IWL<1688> A_IWL<1687> A_IWL<1686> A_IWL<1685> A_IWL<1684> A_IWL<1683> A_IWL<1682> A_IWL<1681> A_IWL<1680> A_IWL<1679> A_IWL<1678> A_IWL<1677> A_IWL<1676> A_IWL<1675> A_IWL<1674> A_IWL<1673> A_IWL<1672> A_IWL<1671> A_IWL<1670> A_IWL<1669> A_IWL<1668> A_IWL<1667> A_IWL<1666> A_IWL<1665> A_IWL<1664> B_BLC<27> B_BLC<26> B_BLC_TOP<27> B_BLC_TOP<26> B_BLT<27> B_BLT<26> B_BLT_TOP<27> B_BLT_TOP<26> B_IWL<1663> B_IWL<1662> B_IWL<1661> B_IWL<1660> B_IWL<1659> B_IWL<1658> B_IWL<1657> B_IWL<1656> B_IWL<1655> B_IWL<1654> B_IWL<1653> B_IWL<1652> B_IWL<1651> B_IWL<1650> B_IWL<1649> B_IWL<1648> B_IWL<1647> B_IWL<1646> B_IWL<1645> B_IWL<1644> B_IWL<1643> B_IWL<1642> B_IWL<1641> B_IWL<1640> B_IWL<1639> B_IWL<1638> B_IWL<1637> B_IWL<1636> B_IWL<1635> B_IWL<1634> B_IWL<1633> B_IWL<1632> B_IWL<1631> B_IWL<1630> B_IWL<1629> B_IWL<1628> B_IWL<1627> B_IWL<1626> B_IWL<1625> B_IWL<1624> B_IWL<1623> B_IWL<1622> B_IWL<1621> B_IWL<1620> B_IWL<1619> B_IWL<1618> B_IWL<1617> B_IWL<1616> B_IWL<1615> B_IWL<1614> B_IWL<1613> B_IWL<1612> B_IWL<1611> B_IWL<1610> B_IWL<1609> B_IWL<1608> B_IWL<1607> B_IWL<1606> B_IWL<1605> B_IWL<1604> B_IWL<1603> B_IWL<1602> B_IWL<1601> B_IWL<1600> B_IWL<1599> B_IWL<1598> B_IWL<1597> B_IWL<1596> B_IWL<1595> B_IWL<1594> B_IWL<1593> B_IWL<1592> B_IWL<1591> B_IWL<1590> B_IWL<1589> B_IWL<1588> B_IWL<1587> B_IWL<1586> B_IWL<1585> B_IWL<1584> B_IWL<1583> B_IWL<1582> B_IWL<1581> B_IWL<1580> B_IWL<1579> B_IWL<1578> B_IWL<1577> B_IWL<1576> B_IWL<1575> B_IWL<1574> B_IWL<1573> B_IWL<1572> B_IWL<1571> B_IWL<1570> B_IWL<1569> B_IWL<1568> B_IWL<1567> B_IWL<1566> B_IWL<1565> B_IWL<1564> B_IWL<1563> B_IWL<1562> B_IWL<1561> B_IWL<1560> B_IWL<1559> B_IWL<1558> B_IWL<1557> B_IWL<1556> B_IWL<1555> B_IWL<1554> B_IWL<1553> B_IWL<1552> B_IWL<1551> B_IWL<1550> B_IWL<1549> B_IWL<1548> B_IWL<1547> B_IWL<1546> B_IWL<1545> B_IWL<1544> B_IWL<1543> B_IWL<1542> B_IWL<1541> B_IWL<1540> B_IWL<1539> B_IWL<1538> B_IWL<1537> B_IWL<1536> B_IWL<1791> B_IWL<1790> B_IWL<1789> B_IWL<1788> B_IWL<1787> B_IWL<1786> B_IWL<1785> B_IWL<1784> B_IWL<1783> B_IWL<1782> B_IWL<1781> B_IWL<1780> B_IWL<1779> B_IWL<1778> B_IWL<1777> B_IWL<1776> B_IWL<1775> B_IWL<1774> B_IWL<1773> B_IWL<1772> B_IWL<1771> B_IWL<1770> B_IWL<1769> B_IWL<1768> B_IWL<1767> B_IWL<1766> B_IWL<1765> B_IWL<1764> B_IWL<1763> B_IWL<1762> B_IWL<1761> B_IWL<1760> B_IWL<1759> B_IWL<1758> B_IWL<1757> B_IWL<1756> B_IWL<1755> B_IWL<1754> B_IWL<1753> B_IWL<1752> B_IWL<1751> B_IWL<1750> B_IWL<1749> B_IWL<1748> B_IWL<1747> B_IWL<1746> B_IWL<1745> B_IWL<1744> B_IWL<1743> B_IWL<1742> B_IWL<1741> B_IWL<1740> B_IWL<1739> B_IWL<1738> B_IWL<1737> B_IWL<1736> B_IWL<1735> B_IWL<1734> B_IWL<1733> B_IWL<1732> B_IWL<1731> B_IWL<1730> B_IWL<1729> B_IWL<1728> B_IWL<1727> B_IWL<1726> B_IWL<1725> B_IWL<1724> B_IWL<1723> B_IWL<1722> B_IWL<1721> B_IWL<1720> B_IWL<1719> B_IWL<1718> B_IWL<1717> B_IWL<1716> B_IWL<1715> B_IWL<1714> B_IWL<1713> B_IWL<1712> B_IWL<1711> B_IWL<1710> B_IWL<1709> B_IWL<1708> B_IWL<1707> B_IWL<1706> B_IWL<1705> B_IWL<1704> B_IWL<1703> B_IWL<1702> B_IWL<1701> B_IWL<1700> B_IWL<1699> B_IWL<1698> B_IWL<1697> B_IWL<1696> B_IWL<1695> B_IWL<1694> B_IWL<1693> B_IWL<1692> B_IWL<1691> B_IWL<1690> B_IWL<1689> B_IWL<1688> B_IWL<1687> B_IWL<1686> B_IWL<1685> B_IWL<1684> B_IWL<1683> B_IWL<1682> B_IWL<1681> B_IWL<1680> B_IWL<1679> B_IWL<1678> B_IWL<1677> B_IWL<1676> B_IWL<1675> B_IWL<1674> B_IWL<1673> B_IWL<1672> B_IWL<1671> B_IWL<1670> B_IWL<1669> B_IWL<1668> B_IWL<1667> B_IWL<1666> B_IWL<1665> B_IWL<1664> VDD_CORE VSS / RM_IHPSG13_512x16_c2_2P_COLUMN_pcell_0 +XCOL<12> A_BLC<25> A_BLC<24> A_BLC_TOP<25> A_BLC_TOP<24> A_BLT<25> A_BLT<24> A_BLT_TOP<25> A_BLT_TOP<24> A_IWL<1535> A_IWL<1534> A_IWL<1533> A_IWL<1532> A_IWL<1531> A_IWL<1530> A_IWL<1529> A_IWL<1528> A_IWL<1527> A_IWL<1526> A_IWL<1525> A_IWL<1524> A_IWL<1523> A_IWL<1522> A_IWL<1521> A_IWL<1520> A_IWL<1519> A_IWL<1518> A_IWL<1517> A_IWL<1516> A_IWL<1515> A_IWL<1514> A_IWL<1513> A_IWL<1512> A_IWL<1511> A_IWL<1510> A_IWL<1509> A_IWL<1508> A_IWL<1507> A_IWL<1506> A_IWL<1505> A_IWL<1504> A_IWL<1503> A_IWL<1502> A_IWL<1501> A_IWL<1500> A_IWL<1499> A_IWL<1498> A_IWL<1497> A_IWL<1496> A_IWL<1495> A_IWL<1494> A_IWL<1493> A_IWL<1492> A_IWL<1491> A_IWL<1490> A_IWL<1489> A_IWL<1488> A_IWL<1487> A_IWL<1486> A_IWL<1485> A_IWL<1484> A_IWL<1483> A_IWL<1482> A_IWL<1481> A_IWL<1480> A_IWL<1479> A_IWL<1478> A_IWL<1477> A_IWL<1476> A_IWL<1475> A_IWL<1474> A_IWL<1473> A_IWL<1472> A_IWL<1471> A_IWL<1470> A_IWL<1469> A_IWL<1468> A_IWL<1467> A_IWL<1466> A_IWL<1465> A_IWL<1464> A_IWL<1463> A_IWL<1462> A_IWL<1461> A_IWL<1460> A_IWL<1459> A_IWL<1458> A_IWL<1457> A_IWL<1456> A_IWL<1455> A_IWL<1454> A_IWL<1453> A_IWL<1452> A_IWL<1451> A_IWL<1450> A_IWL<1449> A_IWL<1448> A_IWL<1447> A_IWL<1446> A_IWL<1445> A_IWL<1444> A_IWL<1443> A_IWL<1442> A_IWL<1441> A_IWL<1440> A_IWL<1439> A_IWL<1438> A_IWL<1437> A_IWL<1436> A_IWL<1435> A_IWL<1434> A_IWL<1433> A_IWL<1432> A_IWL<1431> A_IWL<1430> A_IWL<1429> A_IWL<1428> A_IWL<1427> A_IWL<1426> A_IWL<1425> A_IWL<1424> A_IWL<1423> A_IWL<1422> A_IWL<1421> A_IWL<1420> A_IWL<1419> A_IWL<1418> A_IWL<1417> A_IWL<1416> A_IWL<1415> A_IWL<1414> A_IWL<1413> A_IWL<1412> A_IWL<1411> A_IWL<1410> A_IWL<1409> A_IWL<1408> A_IWL<1663> A_IWL<1662> A_IWL<1661> A_IWL<1660> A_IWL<1659> A_IWL<1658> A_IWL<1657> A_IWL<1656> A_IWL<1655> A_IWL<1654> A_IWL<1653> A_IWL<1652> A_IWL<1651> A_IWL<1650> A_IWL<1649> A_IWL<1648> A_IWL<1647> A_IWL<1646> A_IWL<1645> A_IWL<1644> A_IWL<1643> A_IWL<1642> A_IWL<1641> A_IWL<1640> A_IWL<1639> A_IWL<1638> A_IWL<1637> A_IWL<1636> A_IWL<1635> A_IWL<1634> A_IWL<1633> A_IWL<1632> A_IWL<1631> A_IWL<1630> A_IWL<1629> A_IWL<1628> A_IWL<1627> A_IWL<1626> A_IWL<1625> A_IWL<1624> A_IWL<1623> A_IWL<1622> A_IWL<1621> A_IWL<1620> A_IWL<1619> A_IWL<1618> A_IWL<1617> A_IWL<1616> A_IWL<1615> A_IWL<1614> A_IWL<1613> A_IWL<1612> A_IWL<1611> A_IWL<1610> A_IWL<1609> A_IWL<1608> A_IWL<1607> A_IWL<1606> A_IWL<1605> A_IWL<1604> A_IWL<1603> A_IWL<1602> A_IWL<1601> A_IWL<1600> A_IWL<1599> A_IWL<1598> A_IWL<1597> A_IWL<1596> A_IWL<1595> A_IWL<1594> A_IWL<1593> A_IWL<1592> A_IWL<1591> A_IWL<1590> A_IWL<1589> A_IWL<1588> A_IWL<1587> A_IWL<1586> A_IWL<1585> A_IWL<1584> A_IWL<1583> A_IWL<1582> A_IWL<1581> A_IWL<1580> A_IWL<1579> A_IWL<1578> A_IWL<1577> A_IWL<1576> A_IWL<1575> A_IWL<1574> A_IWL<1573> A_IWL<1572> A_IWL<1571> A_IWL<1570> A_IWL<1569> A_IWL<1568> A_IWL<1567> A_IWL<1566> A_IWL<1565> A_IWL<1564> A_IWL<1563> A_IWL<1562> A_IWL<1561> A_IWL<1560> A_IWL<1559> A_IWL<1558> A_IWL<1557> A_IWL<1556> A_IWL<1555> A_IWL<1554> A_IWL<1553> A_IWL<1552> A_IWL<1551> A_IWL<1550> A_IWL<1549> A_IWL<1548> A_IWL<1547> A_IWL<1546> A_IWL<1545> A_IWL<1544> A_IWL<1543> A_IWL<1542> A_IWL<1541> A_IWL<1540> A_IWL<1539> A_IWL<1538> A_IWL<1537> A_IWL<1536> B_BLC<25> B_BLC<24> B_BLC_TOP<25> B_BLC_TOP<24> B_BLT<25> B_BLT<24> B_BLT_TOP<25> B_BLT_TOP<24> B_IWL<1535> B_IWL<1534> B_IWL<1533> B_IWL<1532> B_IWL<1531> B_IWL<1530> B_IWL<1529> B_IWL<1528> B_IWL<1527> B_IWL<1526> B_IWL<1525> B_IWL<1524> B_IWL<1523> B_IWL<1522> B_IWL<1521> B_IWL<1520> B_IWL<1519> B_IWL<1518> B_IWL<1517> B_IWL<1516> B_IWL<1515> B_IWL<1514> B_IWL<1513> B_IWL<1512> B_IWL<1511> B_IWL<1510> B_IWL<1509> B_IWL<1508> B_IWL<1507> B_IWL<1506> B_IWL<1505> B_IWL<1504> B_IWL<1503> B_IWL<1502> B_IWL<1501> B_IWL<1500> B_IWL<1499> B_IWL<1498> B_IWL<1497> B_IWL<1496> B_IWL<1495> B_IWL<1494> B_IWL<1493> B_IWL<1492> B_IWL<1491> B_IWL<1490> B_IWL<1489> B_IWL<1488> B_IWL<1487> B_IWL<1486> B_IWL<1485> B_IWL<1484> B_IWL<1483> B_IWL<1482> B_IWL<1481> B_IWL<1480> B_IWL<1479> B_IWL<1478> B_IWL<1477> B_IWL<1476> B_IWL<1475> B_IWL<1474> B_IWL<1473> B_IWL<1472> B_IWL<1471> B_IWL<1470> B_IWL<1469> B_IWL<1468> B_IWL<1467> B_IWL<1466> B_IWL<1465> B_IWL<1464> B_IWL<1463> B_IWL<1462> B_IWL<1461> B_IWL<1460> B_IWL<1459> B_IWL<1458> B_IWL<1457> B_IWL<1456> B_IWL<1455> B_IWL<1454> B_IWL<1453> B_IWL<1452> B_IWL<1451> B_IWL<1450> B_IWL<1449> B_IWL<1448> B_IWL<1447> B_IWL<1446> B_IWL<1445> B_IWL<1444> B_IWL<1443> B_IWL<1442> B_IWL<1441> B_IWL<1440> B_IWL<1439> B_IWL<1438> B_IWL<1437> B_IWL<1436> B_IWL<1435> B_IWL<1434> B_IWL<1433> B_IWL<1432> B_IWL<1431> B_IWL<1430> B_IWL<1429> B_IWL<1428> B_IWL<1427> B_IWL<1426> B_IWL<1425> B_IWL<1424> B_IWL<1423> B_IWL<1422> B_IWL<1421> B_IWL<1420> B_IWL<1419> B_IWL<1418> B_IWL<1417> B_IWL<1416> B_IWL<1415> B_IWL<1414> B_IWL<1413> B_IWL<1412> B_IWL<1411> B_IWL<1410> B_IWL<1409> B_IWL<1408> B_IWL<1663> B_IWL<1662> B_IWL<1661> B_IWL<1660> B_IWL<1659> B_IWL<1658> B_IWL<1657> B_IWL<1656> B_IWL<1655> B_IWL<1654> B_IWL<1653> B_IWL<1652> B_IWL<1651> B_IWL<1650> B_IWL<1649> B_IWL<1648> B_IWL<1647> B_IWL<1646> B_IWL<1645> B_IWL<1644> B_IWL<1643> B_IWL<1642> B_IWL<1641> B_IWL<1640> B_IWL<1639> B_IWL<1638> B_IWL<1637> B_IWL<1636> B_IWL<1635> B_IWL<1634> B_IWL<1633> B_IWL<1632> B_IWL<1631> B_IWL<1630> B_IWL<1629> B_IWL<1628> B_IWL<1627> B_IWL<1626> B_IWL<1625> B_IWL<1624> B_IWL<1623> B_IWL<1622> B_IWL<1621> B_IWL<1620> B_IWL<1619> B_IWL<1618> B_IWL<1617> B_IWL<1616> B_IWL<1615> B_IWL<1614> B_IWL<1613> B_IWL<1612> B_IWL<1611> B_IWL<1610> B_IWL<1609> B_IWL<1608> B_IWL<1607> B_IWL<1606> B_IWL<1605> B_IWL<1604> B_IWL<1603> B_IWL<1602> B_IWL<1601> B_IWL<1600> B_IWL<1599> B_IWL<1598> B_IWL<1597> B_IWL<1596> B_IWL<1595> B_IWL<1594> B_IWL<1593> B_IWL<1592> B_IWL<1591> B_IWL<1590> B_IWL<1589> B_IWL<1588> B_IWL<1587> B_IWL<1586> B_IWL<1585> B_IWL<1584> B_IWL<1583> B_IWL<1582> B_IWL<1581> B_IWL<1580> B_IWL<1579> B_IWL<1578> B_IWL<1577> B_IWL<1576> B_IWL<1575> B_IWL<1574> B_IWL<1573> B_IWL<1572> B_IWL<1571> B_IWL<1570> B_IWL<1569> B_IWL<1568> B_IWL<1567> B_IWL<1566> B_IWL<1565> B_IWL<1564> B_IWL<1563> B_IWL<1562> B_IWL<1561> B_IWL<1560> B_IWL<1559> B_IWL<1558> B_IWL<1557> B_IWL<1556> B_IWL<1555> B_IWL<1554> B_IWL<1553> B_IWL<1552> B_IWL<1551> B_IWL<1550> B_IWL<1549> B_IWL<1548> B_IWL<1547> B_IWL<1546> B_IWL<1545> B_IWL<1544> B_IWL<1543> B_IWL<1542> B_IWL<1541> B_IWL<1540> B_IWL<1539> B_IWL<1538> B_IWL<1537> B_IWL<1536> VDD_CORE VSS / RM_IHPSG13_512x16_c2_2P_COLUMN_pcell_0 +XCOL<11> A_BLC<23> A_BLC<22> A_BLC_TOP<23> A_BLC_TOP<22> A_BLT<23> A_BLT<22> A_BLT_TOP<23> A_BLT_TOP<22> A_IWL<1407> A_IWL<1406> A_IWL<1405> A_IWL<1404> A_IWL<1403> A_IWL<1402> A_IWL<1401> A_IWL<1400> A_IWL<1399> A_IWL<1398> A_IWL<1397> A_IWL<1396> A_IWL<1395> A_IWL<1394> A_IWL<1393> A_IWL<1392> A_IWL<1391> A_IWL<1390> A_IWL<1389> A_IWL<1388> A_IWL<1387> A_IWL<1386> A_IWL<1385> A_IWL<1384> A_IWL<1383> A_IWL<1382> A_IWL<1381> A_IWL<1380> A_IWL<1379> A_IWL<1378> A_IWL<1377> A_IWL<1376> A_IWL<1375> A_IWL<1374> A_IWL<1373> A_IWL<1372> A_IWL<1371> A_IWL<1370> A_IWL<1369> A_IWL<1368> A_IWL<1367> A_IWL<1366> A_IWL<1365> A_IWL<1364> A_IWL<1363> A_IWL<1362> A_IWL<1361> A_IWL<1360> A_IWL<1359> A_IWL<1358> A_IWL<1357> A_IWL<1356> A_IWL<1355> A_IWL<1354> A_IWL<1353> A_IWL<1352> A_IWL<1351> A_IWL<1350> A_IWL<1349> A_IWL<1348> A_IWL<1347> A_IWL<1346> A_IWL<1345> A_IWL<1344> A_IWL<1343> A_IWL<1342> A_IWL<1341> A_IWL<1340> A_IWL<1339> A_IWL<1338> A_IWL<1337> A_IWL<1336> A_IWL<1335> A_IWL<1334> A_IWL<1333> A_IWL<1332> A_IWL<1331> A_IWL<1330> A_IWL<1329> A_IWL<1328> A_IWL<1327> A_IWL<1326> A_IWL<1325> A_IWL<1324> A_IWL<1323> A_IWL<1322> A_IWL<1321> A_IWL<1320> A_IWL<1319> A_IWL<1318> A_IWL<1317> A_IWL<1316> A_IWL<1315> A_IWL<1314> A_IWL<1313> A_IWL<1312> A_IWL<1311> A_IWL<1310> A_IWL<1309> A_IWL<1308> A_IWL<1307> A_IWL<1306> A_IWL<1305> A_IWL<1304> A_IWL<1303> A_IWL<1302> A_IWL<1301> A_IWL<1300> A_IWL<1299> A_IWL<1298> A_IWL<1297> A_IWL<1296> A_IWL<1295> A_IWL<1294> A_IWL<1293> A_IWL<1292> A_IWL<1291> A_IWL<1290> A_IWL<1289> A_IWL<1288> A_IWL<1287> A_IWL<1286> A_IWL<1285> A_IWL<1284> A_IWL<1283> A_IWL<1282> A_IWL<1281> A_IWL<1280> A_IWL<1535> A_IWL<1534> A_IWL<1533> A_IWL<1532> A_IWL<1531> A_IWL<1530> A_IWL<1529> A_IWL<1528> A_IWL<1527> A_IWL<1526> A_IWL<1525> A_IWL<1524> A_IWL<1523> A_IWL<1522> A_IWL<1521> A_IWL<1520> A_IWL<1519> A_IWL<1518> A_IWL<1517> A_IWL<1516> A_IWL<1515> A_IWL<1514> A_IWL<1513> A_IWL<1512> A_IWL<1511> A_IWL<1510> A_IWL<1509> A_IWL<1508> A_IWL<1507> A_IWL<1506> A_IWL<1505> A_IWL<1504> A_IWL<1503> A_IWL<1502> A_IWL<1501> A_IWL<1500> A_IWL<1499> A_IWL<1498> A_IWL<1497> A_IWL<1496> A_IWL<1495> A_IWL<1494> A_IWL<1493> A_IWL<1492> A_IWL<1491> A_IWL<1490> A_IWL<1489> A_IWL<1488> A_IWL<1487> A_IWL<1486> A_IWL<1485> A_IWL<1484> A_IWL<1483> A_IWL<1482> A_IWL<1481> A_IWL<1480> A_IWL<1479> A_IWL<1478> A_IWL<1477> A_IWL<1476> A_IWL<1475> A_IWL<1474> A_IWL<1473> A_IWL<1472> A_IWL<1471> A_IWL<1470> A_IWL<1469> A_IWL<1468> A_IWL<1467> A_IWL<1466> A_IWL<1465> A_IWL<1464> A_IWL<1463> A_IWL<1462> A_IWL<1461> A_IWL<1460> A_IWL<1459> A_IWL<1458> A_IWL<1457> A_IWL<1456> A_IWL<1455> A_IWL<1454> A_IWL<1453> A_IWL<1452> A_IWL<1451> A_IWL<1450> A_IWL<1449> A_IWL<1448> A_IWL<1447> A_IWL<1446> A_IWL<1445> A_IWL<1444> A_IWL<1443> A_IWL<1442> A_IWL<1441> A_IWL<1440> A_IWL<1439> A_IWL<1438> A_IWL<1437> A_IWL<1436> A_IWL<1435> A_IWL<1434> A_IWL<1433> A_IWL<1432> A_IWL<1431> A_IWL<1430> A_IWL<1429> A_IWL<1428> A_IWL<1427> A_IWL<1426> A_IWL<1425> A_IWL<1424> A_IWL<1423> A_IWL<1422> A_IWL<1421> A_IWL<1420> A_IWL<1419> A_IWL<1418> A_IWL<1417> A_IWL<1416> A_IWL<1415> A_IWL<1414> A_IWL<1413> A_IWL<1412> A_IWL<1411> A_IWL<1410> A_IWL<1409> A_IWL<1408> B_BLC<23> B_BLC<22> B_BLC_TOP<23> B_BLC_TOP<22> B_BLT<23> B_BLT<22> B_BLT_TOP<23> B_BLT_TOP<22> B_IWL<1407> B_IWL<1406> B_IWL<1405> B_IWL<1404> B_IWL<1403> B_IWL<1402> B_IWL<1401> B_IWL<1400> B_IWL<1399> B_IWL<1398> B_IWL<1397> B_IWL<1396> B_IWL<1395> B_IWL<1394> B_IWL<1393> B_IWL<1392> B_IWL<1391> B_IWL<1390> B_IWL<1389> B_IWL<1388> B_IWL<1387> B_IWL<1386> B_IWL<1385> B_IWL<1384> B_IWL<1383> B_IWL<1382> B_IWL<1381> B_IWL<1380> B_IWL<1379> B_IWL<1378> B_IWL<1377> B_IWL<1376> B_IWL<1375> B_IWL<1374> B_IWL<1373> B_IWL<1372> B_IWL<1371> B_IWL<1370> B_IWL<1369> B_IWL<1368> B_IWL<1367> B_IWL<1366> B_IWL<1365> B_IWL<1364> B_IWL<1363> B_IWL<1362> B_IWL<1361> B_IWL<1360> B_IWL<1359> B_IWL<1358> B_IWL<1357> B_IWL<1356> B_IWL<1355> B_IWL<1354> B_IWL<1353> B_IWL<1352> B_IWL<1351> B_IWL<1350> B_IWL<1349> B_IWL<1348> B_IWL<1347> B_IWL<1346> B_IWL<1345> B_IWL<1344> B_IWL<1343> B_IWL<1342> B_IWL<1341> B_IWL<1340> B_IWL<1339> B_IWL<1338> B_IWL<1337> B_IWL<1336> B_IWL<1335> B_IWL<1334> B_IWL<1333> B_IWL<1332> B_IWL<1331> B_IWL<1330> B_IWL<1329> B_IWL<1328> B_IWL<1327> B_IWL<1326> B_IWL<1325> B_IWL<1324> B_IWL<1323> B_IWL<1322> B_IWL<1321> B_IWL<1320> B_IWL<1319> B_IWL<1318> B_IWL<1317> B_IWL<1316> B_IWL<1315> B_IWL<1314> B_IWL<1313> B_IWL<1312> B_IWL<1311> B_IWL<1310> B_IWL<1309> B_IWL<1308> B_IWL<1307> B_IWL<1306> B_IWL<1305> B_IWL<1304> B_IWL<1303> B_IWL<1302> B_IWL<1301> B_IWL<1300> B_IWL<1299> B_IWL<1298> B_IWL<1297> B_IWL<1296> B_IWL<1295> B_IWL<1294> B_IWL<1293> B_IWL<1292> B_IWL<1291> B_IWL<1290> B_IWL<1289> B_IWL<1288> B_IWL<1287> B_IWL<1286> B_IWL<1285> B_IWL<1284> B_IWL<1283> B_IWL<1282> B_IWL<1281> B_IWL<1280> B_IWL<1535> B_IWL<1534> B_IWL<1533> B_IWL<1532> B_IWL<1531> B_IWL<1530> B_IWL<1529> B_IWL<1528> B_IWL<1527> B_IWL<1526> B_IWL<1525> B_IWL<1524> B_IWL<1523> B_IWL<1522> B_IWL<1521> B_IWL<1520> B_IWL<1519> B_IWL<1518> B_IWL<1517> B_IWL<1516> B_IWL<1515> B_IWL<1514> B_IWL<1513> B_IWL<1512> B_IWL<1511> B_IWL<1510> B_IWL<1509> B_IWL<1508> B_IWL<1507> B_IWL<1506> B_IWL<1505> B_IWL<1504> B_IWL<1503> B_IWL<1502> B_IWL<1501> B_IWL<1500> B_IWL<1499> B_IWL<1498> B_IWL<1497> B_IWL<1496> B_IWL<1495> B_IWL<1494> B_IWL<1493> B_IWL<1492> B_IWL<1491> B_IWL<1490> B_IWL<1489> B_IWL<1488> B_IWL<1487> B_IWL<1486> B_IWL<1485> B_IWL<1484> B_IWL<1483> B_IWL<1482> B_IWL<1481> B_IWL<1480> B_IWL<1479> B_IWL<1478> B_IWL<1477> B_IWL<1476> B_IWL<1475> B_IWL<1474> B_IWL<1473> B_IWL<1472> B_IWL<1471> B_IWL<1470> B_IWL<1469> B_IWL<1468> B_IWL<1467> B_IWL<1466> B_IWL<1465> B_IWL<1464> B_IWL<1463> B_IWL<1462> B_IWL<1461> B_IWL<1460> B_IWL<1459> B_IWL<1458> B_IWL<1457> B_IWL<1456> B_IWL<1455> B_IWL<1454> B_IWL<1453> B_IWL<1452> B_IWL<1451> B_IWL<1450> B_IWL<1449> B_IWL<1448> B_IWL<1447> B_IWL<1446> B_IWL<1445> B_IWL<1444> B_IWL<1443> B_IWL<1442> B_IWL<1441> B_IWL<1440> B_IWL<1439> B_IWL<1438> B_IWL<1437> B_IWL<1436> B_IWL<1435> B_IWL<1434> B_IWL<1433> B_IWL<1432> B_IWL<1431> B_IWL<1430> B_IWL<1429> B_IWL<1428> B_IWL<1427> B_IWL<1426> B_IWL<1425> B_IWL<1424> B_IWL<1423> B_IWL<1422> B_IWL<1421> B_IWL<1420> B_IWL<1419> B_IWL<1418> B_IWL<1417> B_IWL<1416> B_IWL<1415> B_IWL<1414> B_IWL<1413> B_IWL<1412> B_IWL<1411> B_IWL<1410> B_IWL<1409> B_IWL<1408> VDD_CORE VSS / RM_IHPSG13_512x16_c2_2P_COLUMN_pcell_0 +XCOL<10> A_BLC<21> A_BLC<20> A_BLC_TOP<21> A_BLC_TOP<20> A_BLT<21> A_BLT<20> A_BLT_TOP<21> A_BLT_TOP<20> A_IWL<1279> A_IWL<1278> A_IWL<1277> A_IWL<1276> A_IWL<1275> A_IWL<1274> A_IWL<1273> A_IWL<1272> A_IWL<1271> A_IWL<1270> A_IWL<1269> A_IWL<1268> A_IWL<1267> A_IWL<1266> A_IWL<1265> A_IWL<1264> A_IWL<1263> A_IWL<1262> A_IWL<1261> A_IWL<1260> A_IWL<1259> A_IWL<1258> A_IWL<1257> A_IWL<1256> A_IWL<1255> A_IWL<1254> A_IWL<1253> A_IWL<1252> A_IWL<1251> A_IWL<1250> A_IWL<1249> A_IWL<1248> A_IWL<1247> A_IWL<1246> A_IWL<1245> A_IWL<1244> A_IWL<1243> A_IWL<1242> A_IWL<1241> A_IWL<1240> A_IWL<1239> A_IWL<1238> A_IWL<1237> A_IWL<1236> A_IWL<1235> A_IWL<1234> A_IWL<1233> A_IWL<1232> A_IWL<1231> A_IWL<1230> A_IWL<1229> A_IWL<1228> A_IWL<1227> A_IWL<1226> A_IWL<1225> A_IWL<1224> A_IWL<1223> A_IWL<1222> A_IWL<1221> A_IWL<1220> A_IWL<1219> A_IWL<1218> A_IWL<1217> A_IWL<1216> A_IWL<1215> A_IWL<1214> A_IWL<1213> A_IWL<1212> A_IWL<1211> A_IWL<1210> A_IWL<1209> A_IWL<1208> A_IWL<1207> A_IWL<1206> A_IWL<1205> A_IWL<1204> A_IWL<1203> A_IWL<1202> A_IWL<1201> A_IWL<1200> A_IWL<1199> A_IWL<1198> A_IWL<1197> A_IWL<1196> A_IWL<1195> A_IWL<1194> A_IWL<1193> A_IWL<1192> A_IWL<1191> A_IWL<1190> A_IWL<1189> A_IWL<1188> A_IWL<1187> A_IWL<1186> A_IWL<1185> A_IWL<1184> A_IWL<1183> A_IWL<1182> A_IWL<1181> A_IWL<1180> A_IWL<1179> A_IWL<1178> A_IWL<1177> A_IWL<1176> A_IWL<1175> A_IWL<1174> A_IWL<1173> A_IWL<1172> A_IWL<1171> A_IWL<1170> A_IWL<1169> A_IWL<1168> A_IWL<1167> A_IWL<1166> A_IWL<1165> A_IWL<1164> A_IWL<1163> A_IWL<1162> A_IWL<1161> A_IWL<1160> A_IWL<1159> A_IWL<1158> A_IWL<1157> A_IWL<1156> A_IWL<1155> A_IWL<1154> A_IWL<1153> A_IWL<1152> A_IWL<1407> A_IWL<1406> A_IWL<1405> A_IWL<1404> A_IWL<1403> A_IWL<1402> A_IWL<1401> A_IWL<1400> A_IWL<1399> A_IWL<1398> A_IWL<1397> A_IWL<1396> A_IWL<1395> A_IWL<1394> A_IWL<1393> A_IWL<1392> A_IWL<1391> A_IWL<1390> A_IWL<1389> A_IWL<1388> A_IWL<1387> A_IWL<1386> A_IWL<1385> A_IWL<1384> A_IWL<1383> A_IWL<1382> A_IWL<1381> A_IWL<1380> A_IWL<1379> A_IWL<1378> A_IWL<1377> A_IWL<1376> A_IWL<1375> A_IWL<1374> A_IWL<1373> A_IWL<1372> A_IWL<1371> A_IWL<1370> A_IWL<1369> A_IWL<1368> A_IWL<1367> A_IWL<1366> A_IWL<1365> A_IWL<1364> A_IWL<1363> A_IWL<1362> A_IWL<1361> A_IWL<1360> A_IWL<1359> A_IWL<1358> A_IWL<1357> A_IWL<1356> A_IWL<1355> A_IWL<1354> A_IWL<1353> A_IWL<1352> A_IWL<1351> A_IWL<1350> A_IWL<1349> A_IWL<1348> A_IWL<1347> A_IWL<1346> A_IWL<1345> A_IWL<1344> A_IWL<1343> A_IWL<1342> A_IWL<1341> A_IWL<1340> A_IWL<1339> A_IWL<1338> A_IWL<1337> A_IWL<1336> A_IWL<1335> A_IWL<1334> A_IWL<1333> A_IWL<1332> A_IWL<1331> A_IWL<1330> A_IWL<1329> A_IWL<1328> A_IWL<1327> A_IWL<1326> A_IWL<1325> A_IWL<1324> A_IWL<1323> A_IWL<1322> A_IWL<1321> A_IWL<1320> A_IWL<1319> A_IWL<1318> A_IWL<1317> A_IWL<1316> A_IWL<1315> A_IWL<1314> A_IWL<1313> A_IWL<1312> A_IWL<1311> A_IWL<1310> A_IWL<1309> A_IWL<1308> A_IWL<1307> A_IWL<1306> A_IWL<1305> A_IWL<1304> A_IWL<1303> A_IWL<1302> A_IWL<1301> A_IWL<1300> A_IWL<1299> A_IWL<1298> A_IWL<1297> A_IWL<1296> A_IWL<1295> A_IWL<1294> A_IWL<1293> A_IWL<1292> A_IWL<1291> A_IWL<1290> A_IWL<1289> A_IWL<1288> A_IWL<1287> A_IWL<1286> A_IWL<1285> A_IWL<1284> A_IWL<1283> A_IWL<1282> A_IWL<1281> A_IWL<1280> B_BLC<21> B_BLC<20> B_BLC_TOP<21> B_BLC_TOP<20> B_BLT<21> B_BLT<20> B_BLT_TOP<21> B_BLT_TOP<20> B_IWL<1279> B_IWL<1278> B_IWL<1277> B_IWL<1276> B_IWL<1275> B_IWL<1274> B_IWL<1273> B_IWL<1272> B_IWL<1271> B_IWL<1270> B_IWL<1269> B_IWL<1268> B_IWL<1267> B_IWL<1266> B_IWL<1265> B_IWL<1264> B_IWL<1263> B_IWL<1262> B_IWL<1261> B_IWL<1260> B_IWL<1259> B_IWL<1258> B_IWL<1257> B_IWL<1256> B_IWL<1255> B_IWL<1254> B_IWL<1253> B_IWL<1252> B_IWL<1251> B_IWL<1250> B_IWL<1249> B_IWL<1248> B_IWL<1247> B_IWL<1246> B_IWL<1245> B_IWL<1244> B_IWL<1243> B_IWL<1242> B_IWL<1241> B_IWL<1240> B_IWL<1239> B_IWL<1238> B_IWL<1237> B_IWL<1236> B_IWL<1235> B_IWL<1234> B_IWL<1233> B_IWL<1232> B_IWL<1231> B_IWL<1230> B_IWL<1229> B_IWL<1228> B_IWL<1227> B_IWL<1226> B_IWL<1225> B_IWL<1224> B_IWL<1223> B_IWL<1222> B_IWL<1221> B_IWL<1220> B_IWL<1219> B_IWL<1218> B_IWL<1217> B_IWL<1216> B_IWL<1215> B_IWL<1214> B_IWL<1213> B_IWL<1212> B_IWL<1211> B_IWL<1210> B_IWL<1209> B_IWL<1208> B_IWL<1207> B_IWL<1206> B_IWL<1205> B_IWL<1204> B_IWL<1203> B_IWL<1202> B_IWL<1201> B_IWL<1200> B_IWL<1199> B_IWL<1198> B_IWL<1197> B_IWL<1196> B_IWL<1195> B_IWL<1194> B_IWL<1193> B_IWL<1192> B_IWL<1191> B_IWL<1190> B_IWL<1189> B_IWL<1188> B_IWL<1187> B_IWL<1186> B_IWL<1185> B_IWL<1184> B_IWL<1183> B_IWL<1182> B_IWL<1181> B_IWL<1180> B_IWL<1179> B_IWL<1178> B_IWL<1177> B_IWL<1176> B_IWL<1175> B_IWL<1174> B_IWL<1173> B_IWL<1172> B_IWL<1171> B_IWL<1170> B_IWL<1169> B_IWL<1168> B_IWL<1167> B_IWL<1166> B_IWL<1165> B_IWL<1164> B_IWL<1163> B_IWL<1162> B_IWL<1161> B_IWL<1160> B_IWL<1159> B_IWL<1158> B_IWL<1157> B_IWL<1156> B_IWL<1155> B_IWL<1154> B_IWL<1153> B_IWL<1152> B_IWL<1407> B_IWL<1406> B_IWL<1405> B_IWL<1404> B_IWL<1403> B_IWL<1402> B_IWL<1401> B_IWL<1400> B_IWL<1399> B_IWL<1398> B_IWL<1397> B_IWL<1396> B_IWL<1395> B_IWL<1394> B_IWL<1393> B_IWL<1392> B_IWL<1391> B_IWL<1390> B_IWL<1389> B_IWL<1388> B_IWL<1387> B_IWL<1386> B_IWL<1385> B_IWL<1384> B_IWL<1383> B_IWL<1382> B_IWL<1381> B_IWL<1380> B_IWL<1379> B_IWL<1378> B_IWL<1377> B_IWL<1376> B_IWL<1375> B_IWL<1374> B_IWL<1373> B_IWL<1372> B_IWL<1371> B_IWL<1370> B_IWL<1369> B_IWL<1368> B_IWL<1367> B_IWL<1366> B_IWL<1365> B_IWL<1364> B_IWL<1363> B_IWL<1362> B_IWL<1361> B_IWL<1360> B_IWL<1359> B_IWL<1358> B_IWL<1357> B_IWL<1356> B_IWL<1355> B_IWL<1354> B_IWL<1353> B_IWL<1352> B_IWL<1351> B_IWL<1350> B_IWL<1349> B_IWL<1348> B_IWL<1347> B_IWL<1346> B_IWL<1345> B_IWL<1344> B_IWL<1343> B_IWL<1342> B_IWL<1341> B_IWL<1340> B_IWL<1339> B_IWL<1338> B_IWL<1337> B_IWL<1336> B_IWL<1335> B_IWL<1334> B_IWL<1333> B_IWL<1332> B_IWL<1331> B_IWL<1330> B_IWL<1329> B_IWL<1328> B_IWL<1327> B_IWL<1326> B_IWL<1325> B_IWL<1324> B_IWL<1323> B_IWL<1322> B_IWL<1321> B_IWL<1320> B_IWL<1319> B_IWL<1318> B_IWL<1317> B_IWL<1316> B_IWL<1315> B_IWL<1314> B_IWL<1313> B_IWL<1312> B_IWL<1311> B_IWL<1310> B_IWL<1309> B_IWL<1308> B_IWL<1307> B_IWL<1306> B_IWL<1305> B_IWL<1304> B_IWL<1303> B_IWL<1302> B_IWL<1301> B_IWL<1300> B_IWL<1299> B_IWL<1298> B_IWL<1297> B_IWL<1296> B_IWL<1295> B_IWL<1294> B_IWL<1293> B_IWL<1292> B_IWL<1291> B_IWL<1290> B_IWL<1289> B_IWL<1288> B_IWL<1287> B_IWL<1286> B_IWL<1285> B_IWL<1284> B_IWL<1283> B_IWL<1282> B_IWL<1281> B_IWL<1280> VDD_CORE VSS / RM_IHPSG13_512x16_c2_2P_COLUMN_pcell_0 +XCOL<9> A_BLC<19> A_BLC<18> A_BLC_TOP<19> A_BLC_TOP<18> A_BLT<19> A_BLT<18> A_BLT_TOP<19> A_BLT_TOP<18> A_IWL<1151> A_IWL<1150> A_IWL<1149> A_IWL<1148> A_IWL<1147> A_IWL<1146> A_IWL<1145> A_IWL<1144> A_IWL<1143> A_IWL<1142> A_IWL<1141> A_IWL<1140> A_IWL<1139> A_IWL<1138> A_IWL<1137> A_IWL<1136> A_IWL<1135> A_IWL<1134> A_IWL<1133> A_IWL<1132> A_IWL<1131> A_IWL<1130> A_IWL<1129> A_IWL<1128> A_IWL<1127> A_IWL<1126> A_IWL<1125> A_IWL<1124> A_IWL<1123> A_IWL<1122> A_IWL<1121> A_IWL<1120> A_IWL<1119> A_IWL<1118> A_IWL<1117> A_IWL<1116> A_IWL<1115> A_IWL<1114> A_IWL<1113> A_IWL<1112> A_IWL<1111> A_IWL<1110> A_IWL<1109> A_IWL<1108> A_IWL<1107> A_IWL<1106> A_IWL<1105> A_IWL<1104> A_IWL<1103> A_IWL<1102> A_IWL<1101> A_IWL<1100> A_IWL<1099> A_IWL<1098> A_IWL<1097> A_IWL<1096> A_IWL<1095> A_IWL<1094> A_IWL<1093> A_IWL<1092> A_IWL<1091> A_IWL<1090> A_IWL<1089> A_IWL<1088> A_IWL<1087> A_IWL<1086> A_IWL<1085> A_IWL<1084> A_IWL<1083> A_IWL<1082> A_IWL<1081> A_IWL<1080> A_IWL<1079> A_IWL<1078> A_IWL<1077> A_IWL<1076> A_IWL<1075> A_IWL<1074> A_IWL<1073> A_IWL<1072> A_IWL<1071> A_IWL<1070> A_IWL<1069> A_IWL<1068> A_IWL<1067> A_IWL<1066> A_IWL<1065> A_IWL<1064> A_IWL<1063> A_IWL<1062> A_IWL<1061> A_IWL<1060> A_IWL<1059> A_IWL<1058> A_IWL<1057> A_IWL<1056> A_IWL<1055> A_IWL<1054> A_IWL<1053> A_IWL<1052> A_IWL<1051> A_IWL<1050> A_IWL<1049> A_IWL<1048> A_IWL<1047> A_IWL<1046> A_IWL<1045> A_IWL<1044> A_IWL<1043> A_IWL<1042> A_IWL<1041> A_IWL<1040> A_IWL<1039> A_IWL<1038> A_IWL<1037> A_IWL<1036> A_IWL<1035> A_IWL<1034> A_IWL<1033> A_IWL<1032> A_IWL<1031> A_IWL<1030> A_IWL<1029> A_IWL<1028> A_IWL<1027> A_IWL<1026> A_IWL<1025> A_IWL<1024> A_IWL<1279> A_IWL<1278> A_IWL<1277> A_IWL<1276> A_IWL<1275> A_IWL<1274> A_IWL<1273> A_IWL<1272> A_IWL<1271> A_IWL<1270> A_IWL<1269> A_IWL<1268> A_IWL<1267> A_IWL<1266> A_IWL<1265> A_IWL<1264> A_IWL<1263> A_IWL<1262> A_IWL<1261> A_IWL<1260> A_IWL<1259> A_IWL<1258> A_IWL<1257> A_IWL<1256> A_IWL<1255> A_IWL<1254> A_IWL<1253> A_IWL<1252> A_IWL<1251> A_IWL<1250> A_IWL<1249> A_IWL<1248> A_IWL<1247> A_IWL<1246> A_IWL<1245> A_IWL<1244> A_IWL<1243> A_IWL<1242> A_IWL<1241> A_IWL<1240> A_IWL<1239> A_IWL<1238> A_IWL<1237> A_IWL<1236> A_IWL<1235> A_IWL<1234> A_IWL<1233> A_IWL<1232> A_IWL<1231> A_IWL<1230> A_IWL<1229> A_IWL<1228> A_IWL<1227> A_IWL<1226> A_IWL<1225> A_IWL<1224> A_IWL<1223> A_IWL<1222> A_IWL<1221> A_IWL<1220> A_IWL<1219> A_IWL<1218> A_IWL<1217> A_IWL<1216> A_IWL<1215> A_IWL<1214> A_IWL<1213> A_IWL<1212> A_IWL<1211> A_IWL<1210> A_IWL<1209> A_IWL<1208> A_IWL<1207> A_IWL<1206> A_IWL<1205> A_IWL<1204> A_IWL<1203> A_IWL<1202> A_IWL<1201> A_IWL<1200> A_IWL<1199> A_IWL<1198> A_IWL<1197> A_IWL<1196> A_IWL<1195> A_IWL<1194> A_IWL<1193> A_IWL<1192> A_IWL<1191> A_IWL<1190> A_IWL<1189> A_IWL<1188> A_IWL<1187> A_IWL<1186> A_IWL<1185> A_IWL<1184> A_IWL<1183> A_IWL<1182> A_IWL<1181> A_IWL<1180> A_IWL<1179> A_IWL<1178> A_IWL<1177> A_IWL<1176> A_IWL<1175> A_IWL<1174> A_IWL<1173> A_IWL<1172> A_IWL<1171> A_IWL<1170> A_IWL<1169> A_IWL<1168> A_IWL<1167> A_IWL<1166> A_IWL<1165> A_IWL<1164> A_IWL<1163> A_IWL<1162> A_IWL<1161> A_IWL<1160> A_IWL<1159> A_IWL<1158> A_IWL<1157> A_IWL<1156> A_IWL<1155> A_IWL<1154> A_IWL<1153> A_IWL<1152> B_BLC<19> B_BLC<18> B_BLC_TOP<19> B_BLC_TOP<18> B_BLT<19> B_BLT<18> B_BLT_TOP<19> B_BLT_TOP<18> B_IWL<1151> B_IWL<1150> B_IWL<1149> B_IWL<1148> B_IWL<1147> B_IWL<1146> B_IWL<1145> B_IWL<1144> B_IWL<1143> B_IWL<1142> B_IWL<1141> B_IWL<1140> B_IWL<1139> B_IWL<1138> B_IWL<1137> B_IWL<1136> B_IWL<1135> B_IWL<1134> B_IWL<1133> B_IWL<1132> B_IWL<1131> B_IWL<1130> B_IWL<1129> B_IWL<1128> B_IWL<1127> B_IWL<1126> B_IWL<1125> B_IWL<1124> B_IWL<1123> B_IWL<1122> B_IWL<1121> B_IWL<1120> B_IWL<1119> B_IWL<1118> B_IWL<1117> B_IWL<1116> B_IWL<1115> B_IWL<1114> B_IWL<1113> B_IWL<1112> B_IWL<1111> B_IWL<1110> B_IWL<1109> B_IWL<1108> B_IWL<1107> B_IWL<1106> B_IWL<1105> B_IWL<1104> B_IWL<1103> B_IWL<1102> B_IWL<1101> B_IWL<1100> B_IWL<1099> B_IWL<1098> B_IWL<1097> B_IWL<1096> B_IWL<1095> B_IWL<1094> B_IWL<1093> B_IWL<1092> B_IWL<1091> B_IWL<1090> B_IWL<1089> B_IWL<1088> B_IWL<1087> B_IWL<1086> B_IWL<1085> B_IWL<1084> B_IWL<1083> B_IWL<1082> B_IWL<1081> B_IWL<1080> B_IWL<1079> B_IWL<1078> B_IWL<1077> B_IWL<1076> B_IWL<1075> B_IWL<1074> B_IWL<1073> B_IWL<1072> B_IWL<1071> B_IWL<1070> B_IWL<1069> B_IWL<1068> B_IWL<1067> B_IWL<1066> B_IWL<1065> B_IWL<1064> B_IWL<1063> B_IWL<1062> B_IWL<1061> B_IWL<1060> B_IWL<1059> B_IWL<1058> B_IWL<1057> B_IWL<1056> B_IWL<1055> B_IWL<1054> B_IWL<1053> B_IWL<1052> B_IWL<1051> B_IWL<1050> B_IWL<1049> B_IWL<1048> B_IWL<1047> B_IWL<1046> B_IWL<1045> B_IWL<1044> B_IWL<1043> B_IWL<1042> B_IWL<1041> B_IWL<1040> B_IWL<1039> B_IWL<1038> B_IWL<1037> B_IWL<1036> B_IWL<1035> B_IWL<1034> B_IWL<1033> B_IWL<1032> B_IWL<1031> B_IWL<1030> B_IWL<1029> B_IWL<1028> B_IWL<1027> B_IWL<1026> B_IWL<1025> B_IWL<1024> B_IWL<1279> B_IWL<1278> B_IWL<1277> B_IWL<1276> B_IWL<1275> B_IWL<1274> B_IWL<1273> B_IWL<1272> B_IWL<1271> B_IWL<1270> B_IWL<1269> B_IWL<1268> B_IWL<1267> B_IWL<1266> B_IWL<1265> B_IWL<1264> B_IWL<1263> B_IWL<1262> B_IWL<1261> B_IWL<1260> B_IWL<1259> B_IWL<1258> B_IWL<1257> B_IWL<1256> B_IWL<1255> B_IWL<1254> B_IWL<1253> B_IWL<1252> B_IWL<1251> B_IWL<1250> B_IWL<1249> B_IWL<1248> B_IWL<1247> B_IWL<1246> B_IWL<1245> B_IWL<1244> B_IWL<1243> B_IWL<1242> B_IWL<1241> B_IWL<1240> B_IWL<1239> B_IWL<1238> B_IWL<1237> B_IWL<1236> B_IWL<1235> B_IWL<1234> B_IWL<1233> B_IWL<1232> B_IWL<1231> B_IWL<1230> B_IWL<1229> B_IWL<1228> B_IWL<1227> B_IWL<1226> B_IWL<1225> B_IWL<1224> B_IWL<1223> B_IWL<1222> B_IWL<1221> B_IWL<1220> B_IWL<1219> B_IWL<1218> B_IWL<1217> B_IWL<1216> B_IWL<1215> B_IWL<1214> B_IWL<1213> B_IWL<1212> B_IWL<1211> B_IWL<1210> B_IWL<1209> B_IWL<1208> B_IWL<1207> B_IWL<1206> B_IWL<1205> B_IWL<1204> B_IWL<1203> B_IWL<1202> B_IWL<1201> B_IWL<1200> B_IWL<1199> B_IWL<1198> B_IWL<1197> B_IWL<1196> B_IWL<1195> B_IWL<1194> B_IWL<1193> B_IWL<1192> B_IWL<1191> B_IWL<1190> B_IWL<1189> B_IWL<1188> B_IWL<1187> B_IWL<1186> B_IWL<1185> B_IWL<1184> B_IWL<1183> B_IWL<1182> B_IWL<1181> B_IWL<1180> B_IWL<1179> B_IWL<1178> B_IWL<1177> B_IWL<1176> B_IWL<1175> B_IWL<1174> B_IWL<1173> B_IWL<1172> B_IWL<1171> B_IWL<1170> B_IWL<1169> B_IWL<1168> B_IWL<1167> B_IWL<1166> B_IWL<1165> B_IWL<1164> B_IWL<1163> B_IWL<1162> B_IWL<1161> B_IWL<1160> B_IWL<1159> B_IWL<1158> B_IWL<1157> B_IWL<1156> B_IWL<1155> B_IWL<1154> B_IWL<1153> B_IWL<1152> VDD_CORE VSS / RM_IHPSG13_512x16_c2_2P_COLUMN_pcell_0 +XCOL<8> A_BLC<17> A_BLC<16> A_BLC_TOP<17> A_BLC_TOP<16> A_BLT<17> A_BLT<16> A_BLT_TOP<17> A_BLT_TOP<16> A_IWL<1023> A_IWL<1022> A_IWL<1021> A_IWL<1020> A_IWL<1019> A_IWL<1018> A_IWL<1017> A_IWL<1016> A_IWL<1015> A_IWL<1014> A_IWL<1013> A_IWL<1012> A_IWL<1011> A_IWL<1010> A_IWL<1009> A_IWL<1008> A_IWL<1007> A_IWL<1006> A_IWL<1005> A_IWL<1004> A_IWL<1003> A_IWL<1002> A_IWL<1001> A_IWL<1000> A_IWL<999> A_IWL<998> A_IWL<997> A_IWL<996> A_IWL<995> A_IWL<994> A_IWL<993> A_IWL<992> A_IWL<991> A_IWL<990> A_IWL<989> A_IWL<988> A_IWL<987> A_IWL<986> A_IWL<985> A_IWL<984> A_IWL<983> A_IWL<982> A_IWL<981> A_IWL<980> A_IWL<979> A_IWL<978> A_IWL<977> A_IWL<976> A_IWL<975> A_IWL<974> A_IWL<973> A_IWL<972> A_IWL<971> A_IWL<970> A_IWL<969> A_IWL<968> A_IWL<967> A_IWL<966> A_IWL<965> A_IWL<964> A_IWL<963> A_IWL<962> A_IWL<961> A_IWL<960> A_IWL<959> A_IWL<958> A_IWL<957> A_IWL<956> A_IWL<955> A_IWL<954> A_IWL<953> A_IWL<952> A_IWL<951> A_IWL<950> A_IWL<949> A_IWL<948> A_IWL<947> A_IWL<946> A_IWL<945> A_IWL<944> A_IWL<943> A_IWL<942> A_IWL<941> A_IWL<940> A_IWL<939> A_IWL<938> A_IWL<937> A_IWL<936> A_IWL<935> A_IWL<934> A_IWL<933> A_IWL<932> A_IWL<931> A_IWL<930> A_IWL<929> A_IWL<928> A_IWL<927> A_IWL<926> A_IWL<925> A_IWL<924> A_IWL<923> A_IWL<922> A_IWL<921> A_IWL<920> A_IWL<919> A_IWL<918> A_IWL<917> A_IWL<916> A_IWL<915> A_IWL<914> A_IWL<913> A_IWL<912> A_IWL<911> A_IWL<910> A_IWL<909> A_IWL<908> A_IWL<907> A_IWL<906> A_IWL<905> A_IWL<904> A_IWL<903> A_IWL<902> A_IWL<901> A_IWL<900> A_IWL<899> A_IWL<898> A_IWL<897> A_IWL<896> A_IWL<1151> A_IWL<1150> A_IWL<1149> A_IWL<1148> A_IWL<1147> A_IWL<1146> A_IWL<1145> A_IWL<1144> A_IWL<1143> A_IWL<1142> A_IWL<1141> A_IWL<1140> A_IWL<1139> A_IWL<1138> A_IWL<1137> A_IWL<1136> A_IWL<1135> A_IWL<1134> A_IWL<1133> A_IWL<1132> A_IWL<1131> A_IWL<1130> A_IWL<1129> A_IWL<1128> A_IWL<1127> A_IWL<1126> A_IWL<1125> A_IWL<1124> A_IWL<1123> A_IWL<1122> A_IWL<1121> A_IWL<1120> A_IWL<1119> A_IWL<1118> A_IWL<1117> A_IWL<1116> A_IWL<1115> A_IWL<1114> A_IWL<1113> A_IWL<1112> A_IWL<1111> A_IWL<1110> A_IWL<1109> A_IWL<1108> A_IWL<1107> A_IWL<1106> A_IWL<1105> A_IWL<1104> A_IWL<1103> A_IWL<1102> A_IWL<1101> A_IWL<1100> A_IWL<1099> A_IWL<1098> A_IWL<1097> A_IWL<1096> A_IWL<1095> A_IWL<1094> A_IWL<1093> A_IWL<1092> A_IWL<1091> A_IWL<1090> A_IWL<1089> A_IWL<1088> A_IWL<1087> A_IWL<1086> A_IWL<1085> A_IWL<1084> A_IWL<1083> A_IWL<1082> A_IWL<1081> A_IWL<1080> A_IWL<1079> A_IWL<1078> A_IWL<1077> A_IWL<1076> A_IWL<1075> A_IWL<1074> A_IWL<1073> A_IWL<1072> A_IWL<1071> A_IWL<1070> A_IWL<1069> A_IWL<1068> A_IWL<1067> A_IWL<1066> A_IWL<1065> A_IWL<1064> A_IWL<1063> A_IWL<1062> A_IWL<1061> A_IWL<1060> A_IWL<1059> A_IWL<1058> A_IWL<1057> A_IWL<1056> A_IWL<1055> A_IWL<1054> A_IWL<1053> A_IWL<1052> A_IWL<1051> A_IWL<1050> A_IWL<1049> A_IWL<1048> A_IWL<1047> A_IWL<1046> A_IWL<1045> A_IWL<1044> A_IWL<1043> A_IWL<1042> A_IWL<1041> A_IWL<1040> A_IWL<1039> A_IWL<1038> A_IWL<1037> A_IWL<1036> A_IWL<1035> A_IWL<1034> A_IWL<1033> A_IWL<1032> A_IWL<1031> A_IWL<1030> A_IWL<1029> A_IWL<1028> A_IWL<1027> A_IWL<1026> A_IWL<1025> A_IWL<1024> B_BLC<17> B_BLC<16> B_BLC_TOP<17> B_BLC_TOP<16> B_BLT<17> B_BLT<16> B_BLT_TOP<17> B_BLT_TOP<16> B_IWL<1023> B_IWL<1022> B_IWL<1021> B_IWL<1020> B_IWL<1019> B_IWL<1018> B_IWL<1017> B_IWL<1016> B_IWL<1015> B_IWL<1014> B_IWL<1013> B_IWL<1012> B_IWL<1011> B_IWL<1010> B_IWL<1009> B_IWL<1008> B_IWL<1007> B_IWL<1006> B_IWL<1005> B_IWL<1004> B_IWL<1003> B_IWL<1002> B_IWL<1001> B_IWL<1000> B_IWL<999> B_IWL<998> B_IWL<997> B_IWL<996> B_IWL<995> B_IWL<994> B_IWL<993> B_IWL<992> B_IWL<991> B_IWL<990> B_IWL<989> B_IWL<988> B_IWL<987> B_IWL<986> B_IWL<985> B_IWL<984> B_IWL<983> B_IWL<982> B_IWL<981> B_IWL<980> B_IWL<979> B_IWL<978> B_IWL<977> B_IWL<976> B_IWL<975> B_IWL<974> B_IWL<973> B_IWL<972> B_IWL<971> B_IWL<970> B_IWL<969> B_IWL<968> B_IWL<967> B_IWL<966> B_IWL<965> B_IWL<964> B_IWL<963> B_IWL<962> B_IWL<961> B_IWL<960> B_IWL<959> B_IWL<958> B_IWL<957> B_IWL<956> B_IWL<955> B_IWL<954> B_IWL<953> B_IWL<952> B_IWL<951> B_IWL<950> B_IWL<949> B_IWL<948> B_IWL<947> B_IWL<946> B_IWL<945> B_IWL<944> B_IWL<943> B_IWL<942> B_IWL<941> B_IWL<940> B_IWL<939> B_IWL<938> B_IWL<937> B_IWL<936> B_IWL<935> B_IWL<934> B_IWL<933> B_IWL<932> B_IWL<931> B_IWL<930> B_IWL<929> B_IWL<928> B_IWL<927> B_IWL<926> B_IWL<925> B_IWL<924> B_IWL<923> B_IWL<922> B_IWL<921> B_IWL<920> B_IWL<919> B_IWL<918> B_IWL<917> B_IWL<916> B_IWL<915> B_IWL<914> B_IWL<913> B_IWL<912> B_IWL<911> B_IWL<910> B_IWL<909> B_IWL<908> B_IWL<907> B_IWL<906> B_IWL<905> B_IWL<904> B_IWL<903> B_IWL<902> B_IWL<901> B_IWL<900> B_IWL<899> B_IWL<898> B_IWL<897> B_IWL<896> B_IWL<1151> B_IWL<1150> B_IWL<1149> B_IWL<1148> B_IWL<1147> B_IWL<1146> B_IWL<1145> B_IWL<1144> B_IWL<1143> B_IWL<1142> B_IWL<1141> B_IWL<1140> B_IWL<1139> B_IWL<1138> B_IWL<1137> B_IWL<1136> B_IWL<1135> B_IWL<1134> B_IWL<1133> B_IWL<1132> B_IWL<1131> B_IWL<1130> B_IWL<1129> B_IWL<1128> B_IWL<1127> B_IWL<1126> B_IWL<1125> B_IWL<1124> B_IWL<1123> B_IWL<1122> B_IWL<1121> B_IWL<1120> B_IWL<1119> B_IWL<1118> B_IWL<1117> B_IWL<1116> B_IWL<1115> B_IWL<1114> B_IWL<1113> B_IWL<1112> B_IWL<1111> B_IWL<1110> B_IWL<1109> B_IWL<1108> B_IWL<1107> B_IWL<1106> B_IWL<1105> B_IWL<1104> B_IWL<1103> B_IWL<1102> B_IWL<1101> B_IWL<1100> B_IWL<1099> B_IWL<1098> B_IWL<1097> B_IWL<1096> B_IWL<1095> B_IWL<1094> B_IWL<1093> B_IWL<1092> B_IWL<1091> B_IWL<1090> B_IWL<1089> B_IWL<1088> B_IWL<1087> B_IWL<1086> B_IWL<1085> B_IWL<1084> B_IWL<1083> B_IWL<1082> B_IWL<1081> B_IWL<1080> B_IWL<1079> B_IWL<1078> B_IWL<1077> B_IWL<1076> B_IWL<1075> B_IWL<1074> B_IWL<1073> B_IWL<1072> B_IWL<1071> B_IWL<1070> B_IWL<1069> B_IWL<1068> B_IWL<1067> B_IWL<1066> B_IWL<1065> B_IWL<1064> B_IWL<1063> B_IWL<1062> B_IWL<1061> B_IWL<1060> B_IWL<1059> B_IWL<1058> B_IWL<1057> B_IWL<1056> B_IWL<1055> B_IWL<1054> B_IWL<1053> B_IWL<1052> B_IWL<1051> B_IWL<1050> B_IWL<1049> B_IWL<1048> B_IWL<1047> B_IWL<1046> B_IWL<1045> B_IWL<1044> B_IWL<1043> B_IWL<1042> B_IWL<1041> B_IWL<1040> B_IWL<1039> B_IWL<1038> B_IWL<1037> B_IWL<1036> B_IWL<1035> B_IWL<1034> B_IWL<1033> B_IWL<1032> B_IWL<1031> B_IWL<1030> B_IWL<1029> B_IWL<1028> B_IWL<1027> B_IWL<1026> B_IWL<1025> B_IWL<1024> VDD_CORE VSS / RM_IHPSG13_512x16_c2_2P_COLUMN_pcell_0 +XCOL<7> A_BLC<15> A_BLC<14> A_BLC_TOP<15> A_BLC_TOP<14> A_BLT<15> A_BLT<14> A_BLT_TOP<15> A_BLT_TOP<14> A_IWL<895> A_IWL<894> A_IWL<893> A_IWL<892> A_IWL<891> A_IWL<890> A_IWL<889> A_IWL<888> A_IWL<887> A_IWL<886> A_IWL<885> A_IWL<884> A_IWL<883> A_IWL<882> A_IWL<881> A_IWL<880> A_IWL<879> A_IWL<878> A_IWL<877> A_IWL<876> A_IWL<875> A_IWL<874> A_IWL<873> A_IWL<872> A_IWL<871> A_IWL<870> A_IWL<869> A_IWL<868> A_IWL<867> A_IWL<866> A_IWL<865> A_IWL<864> A_IWL<863> A_IWL<862> A_IWL<861> A_IWL<860> A_IWL<859> A_IWL<858> A_IWL<857> A_IWL<856> A_IWL<855> A_IWL<854> A_IWL<853> A_IWL<852> A_IWL<851> A_IWL<850> A_IWL<849> A_IWL<848> A_IWL<847> A_IWL<846> A_IWL<845> A_IWL<844> A_IWL<843> A_IWL<842> A_IWL<841> A_IWL<840> A_IWL<839> A_IWL<838> A_IWL<837> A_IWL<836> A_IWL<835> A_IWL<834> A_IWL<833> A_IWL<832> A_IWL<831> A_IWL<830> A_IWL<829> A_IWL<828> A_IWL<827> A_IWL<826> A_IWL<825> A_IWL<824> A_IWL<823> A_IWL<822> A_IWL<821> A_IWL<820> A_IWL<819> A_IWL<818> A_IWL<817> A_IWL<816> A_IWL<815> A_IWL<814> A_IWL<813> A_IWL<812> A_IWL<811> A_IWL<810> A_IWL<809> A_IWL<808> A_IWL<807> A_IWL<806> A_IWL<805> A_IWL<804> A_IWL<803> A_IWL<802> A_IWL<801> A_IWL<800> A_IWL<799> A_IWL<798> A_IWL<797> A_IWL<796> A_IWL<795> A_IWL<794> A_IWL<793> A_IWL<792> A_IWL<791> A_IWL<790> A_IWL<789> A_IWL<788> A_IWL<787> A_IWL<786> A_IWL<785> A_IWL<784> A_IWL<783> A_IWL<782> A_IWL<781> A_IWL<780> A_IWL<779> A_IWL<778> A_IWL<777> A_IWL<776> A_IWL<775> A_IWL<774> A_IWL<773> A_IWL<772> A_IWL<771> A_IWL<770> A_IWL<769> A_IWL<768> A_IWL<1023> A_IWL<1022> A_IWL<1021> A_IWL<1020> A_IWL<1019> A_IWL<1018> A_IWL<1017> A_IWL<1016> A_IWL<1015> A_IWL<1014> A_IWL<1013> A_IWL<1012> A_IWL<1011> A_IWL<1010> A_IWL<1009> A_IWL<1008> A_IWL<1007> A_IWL<1006> A_IWL<1005> A_IWL<1004> A_IWL<1003> A_IWL<1002> A_IWL<1001> A_IWL<1000> A_IWL<999> A_IWL<998> A_IWL<997> A_IWL<996> A_IWL<995> A_IWL<994> A_IWL<993> A_IWL<992> A_IWL<991> A_IWL<990> A_IWL<989> A_IWL<988> A_IWL<987> A_IWL<986> A_IWL<985> A_IWL<984> A_IWL<983> A_IWL<982> A_IWL<981> A_IWL<980> A_IWL<979> A_IWL<978> A_IWL<977> A_IWL<976> A_IWL<975> A_IWL<974> A_IWL<973> A_IWL<972> A_IWL<971> A_IWL<970> A_IWL<969> A_IWL<968> A_IWL<967> A_IWL<966> A_IWL<965> A_IWL<964> A_IWL<963> A_IWL<962> A_IWL<961> A_IWL<960> A_IWL<959> A_IWL<958> A_IWL<957> A_IWL<956> A_IWL<955> A_IWL<954> A_IWL<953> A_IWL<952> A_IWL<951> A_IWL<950> A_IWL<949> A_IWL<948> A_IWL<947> A_IWL<946> A_IWL<945> A_IWL<944> A_IWL<943> A_IWL<942> A_IWL<941> A_IWL<940> A_IWL<939> A_IWL<938> A_IWL<937> A_IWL<936> A_IWL<935> A_IWL<934> A_IWL<933> A_IWL<932> A_IWL<931> A_IWL<930> A_IWL<929> A_IWL<928> A_IWL<927> A_IWL<926> A_IWL<925> A_IWL<924> A_IWL<923> A_IWL<922> A_IWL<921> A_IWL<920> A_IWL<919> A_IWL<918> A_IWL<917> A_IWL<916> A_IWL<915> A_IWL<914> A_IWL<913> A_IWL<912> A_IWL<911> A_IWL<910> A_IWL<909> A_IWL<908> A_IWL<907> A_IWL<906> A_IWL<905> A_IWL<904> A_IWL<903> A_IWL<902> A_IWL<901> A_IWL<900> A_IWL<899> A_IWL<898> A_IWL<897> A_IWL<896> B_BLC<15> B_BLC<14> B_BLC_TOP<15> B_BLC_TOP<14> B_BLT<15> B_BLT<14> B_BLT_TOP<15> B_BLT_TOP<14> B_IWL<895> B_IWL<894> B_IWL<893> B_IWL<892> B_IWL<891> B_IWL<890> B_IWL<889> B_IWL<888> B_IWL<887> B_IWL<886> B_IWL<885> B_IWL<884> B_IWL<883> B_IWL<882> B_IWL<881> B_IWL<880> B_IWL<879> B_IWL<878> B_IWL<877> B_IWL<876> B_IWL<875> B_IWL<874> B_IWL<873> B_IWL<872> B_IWL<871> B_IWL<870> B_IWL<869> B_IWL<868> B_IWL<867> B_IWL<866> B_IWL<865> B_IWL<864> B_IWL<863> B_IWL<862> B_IWL<861> B_IWL<860> B_IWL<859> B_IWL<858> B_IWL<857> B_IWL<856> B_IWL<855> B_IWL<854> B_IWL<853> B_IWL<852> B_IWL<851> B_IWL<850> B_IWL<849> B_IWL<848> B_IWL<847> B_IWL<846> B_IWL<845> B_IWL<844> B_IWL<843> B_IWL<842> B_IWL<841> B_IWL<840> B_IWL<839> B_IWL<838> B_IWL<837> B_IWL<836> B_IWL<835> B_IWL<834> B_IWL<833> B_IWL<832> B_IWL<831> B_IWL<830> B_IWL<829> B_IWL<828> B_IWL<827> B_IWL<826> B_IWL<825> B_IWL<824> B_IWL<823> B_IWL<822> B_IWL<821> B_IWL<820> B_IWL<819> B_IWL<818> B_IWL<817> B_IWL<816> B_IWL<815> B_IWL<814> B_IWL<813> B_IWL<812> B_IWL<811> B_IWL<810> B_IWL<809> B_IWL<808> B_IWL<807> B_IWL<806> B_IWL<805> B_IWL<804> B_IWL<803> B_IWL<802> B_IWL<801> B_IWL<800> B_IWL<799> B_IWL<798> B_IWL<797> B_IWL<796> B_IWL<795> B_IWL<794> B_IWL<793> B_IWL<792> B_IWL<791> B_IWL<790> B_IWL<789> B_IWL<788> B_IWL<787> B_IWL<786> B_IWL<785> B_IWL<784> B_IWL<783> B_IWL<782> B_IWL<781> B_IWL<780> B_IWL<779> B_IWL<778> B_IWL<777> B_IWL<776> B_IWL<775> B_IWL<774> B_IWL<773> B_IWL<772> B_IWL<771> B_IWL<770> B_IWL<769> B_IWL<768> B_IWL<1023> B_IWL<1022> B_IWL<1021> B_IWL<1020> B_IWL<1019> B_IWL<1018> B_IWL<1017> B_IWL<1016> B_IWL<1015> B_IWL<1014> B_IWL<1013> B_IWL<1012> B_IWL<1011> B_IWL<1010> B_IWL<1009> B_IWL<1008> B_IWL<1007> B_IWL<1006> B_IWL<1005> B_IWL<1004> B_IWL<1003> B_IWL<1002> B_IWL<1001> B_IWL<1000> B_IWL<999> B_IWL<998> B_IWL<997> B_IWL<996> B_IWL<995> B_IWL<994> B_IWL<993> B_IWL<992> B_IWL<991> B_IWL<990> B_IWL<989> B_IWL<988> B_IWL<987> B_IWL<986> B_IWL<985> B_IWL<984> B_IWL<983> B_IWL<982> B_IWL<981> B_IWL<980> B_IWL<979> B_IWL<978> B_IWL<977> B_IWL<976> B_IWL<975> B_IWL<974> B_IWL<973> B_IWL<972> B_IWL<971> B_IWL<970> B_IWL<969> B_IWL<968> B_IWL<967> B_IWL<966> B_IWL<965> B_IWL<964> B_IWL<963> B_IWL<962> B_IWL<961> B_IWL<960> B_IWL<959> B_IWL<958> B_IWL<957> B_IWL<956> B_IWL<955> B_IWL<954> B_IWL<953> B_IWL<952> B_IWL<951> B_IWL<950> B_IWL<949> B_IWL<948> B_IWL<947> B_IWL<946> B_IWL<945> B_IWL<944> B_IWL<943> B_IWL<942> B_IWL<941> B_IWL<940> B_IWL<939> B_IWL<938> B_IWL<937> B_IWL<936> B_IWL<935> B_IWL<934> B_IWL<933> B_IWL<932> B_IWL<931> B_IWL<930> B_IWL<929> B_IWL<928> B_IWL<927> B_IWL<926> B_IWL<925> B_IWL<924> B_IWL<923> B_IWL<922> B_IWL<921> B_IWL<920> B_IWL<919> B_IWL<918> B_IWL<917> B_IWL<916> B_IWL<915> B_IWL<914> B_IWL<913> B_IWL<912> B_IWL<911> B_IWL<910> B_IWL<909> B_IWL<908> B_IWL<907> B_IWL<906> B_IWL<905> B_IWL<904> B_IWL<903> B_IWL<902> B_IWL<901> B_IWL<900> B_IWL<899> B_IWL<898> B_IWL<897> B_IWL<896> VDD_CORE VSS / RM_IHPSG13_512x16_c2_2P_COLUMN_pcell_0 +XCOL<6> A_BLC<13> A_BLC<12> A_BLC_TOP<13> A_BLC_TOP<12> A_BLT<13> A_BLT<12> A_BLT_TOP<13> A_BLT_TOP<12> A_IWL<767> A_IWL<766> A_IWL<765> A_IWL<764> A_IWL<763> A_IWL<762> A_IWL<761> A_IWL<760> A_IWL<759> A_IWL<758> A_IWL<757> A_IWL<756> A_IWL<755> A_IWL<754> A_IWL<753> A_IWL<752> A_IWL<751> A_IWL<750> A_IWL<749> A_IWL<748> A_IWL<747> A_IWL<746> A_IWL<745> A_IWL<744> A_IWL<743> A_IWL<742> A_IWL<741> A_IWL<740> A_IWL<739> A_IWL<738> A_IWL<737> A_IWL<736> A_IWL<735> A_IWL<734> A_IWL<733> A_IWL<732> A_IWL<731> A_IWL<730> A_IWL<729> A_IWL<728> A_IWL<727> A_IWL<726> A_IWL<725> A_IWL<724> A_IWL<723> A_IWL<722> A_IWL<721> A_IWL<720> A_IWL<719> A_IWL<718> A_IWL<717> A_IWL<716> A_IWL<715> A_IWL<714> A_IWL<713> A_IWL<712> A_IWL<711> A_IWL<710> A_IWL<709> A_IWL<708> A_IWL<707> A_IWL<706> A_IWL<705> A_IWL<704> A_IWL<703> A_IWL<702> A_IWL<701> A_IWL<700> A_IWL<699> A_IWL<698> A_IWL<697> A_IWL<696> A_IWL<695> A_IWL<694> A_IWL<693> A_IWL<692> A_IWL<691> A_IWL<690> A_IWL<689> A_IWL<688> A_IWL<687> A_IWL<686> A_IWL<685> A_IWL<684> A_IWL<683> A_IWL<682> A_IWL<681> A_IWL<680> A_IWL<679> A_IWL<678> A_IWL<677> A_IWL<676> A_IWL<675> A_IWL<674> A_IWL<673> A_IWL<672> A_IWL<671> A_IWL<670> A_IWL<669> A_IWL<668> A_IWL<667> A_IWL<666> A_IWL<665> A_IWL<664> A_IWL<663> A_IWL<662> A_IWL<661> A_IWL<660> A_IWL<659> A_IWL<658> A_IWL<657> A_IWL<656> A_IWL<655> A_IWL<654> A_IWL<653> A_IWL<652> A_IWL<651> A_IWL<650> A_IWL<649> A_IWL<648> A_IWL<647> A_IWL<646> A_IWL<645> A_IWL<644> A_IWL<643> A_IWL<642> A_IWL<641> A_IWL<640> A_IWL<895> A_IWL<894> A_IWL<893> A_IWL<892> A_IWL<891> A_IWL<890> A_IWL<889> A_IWL<888> A_IWL<887> A_IWL<886> A_IWL<885> A_IWL<884> A_IWL<883> A_IWL<882> A_IWL<881> A_IWL<880> A_IWL<879> A_IWL<878> A_IWL<877> A_IWL<876> A_IWL<875> A_IWL<874> A_IWL<873> A_IWL<872> A_IWL<871> A_IWL<870> A_IWL<869> A_IWL<868> A_IWL<867> A_IWL<866> A_IWL<865> A_IWL<864> A_IWL<863> A_IWL<862> A_IWL<861> A_IWL<860> A_IWL<859> A_IWL<858> A_IWL<857> A_IWL<856> A_IWL<855> A_IWL<854> A_IWL<853> A_IWL<852> A_IWL<851> A_IWL<850> A_IWL<849> A_IWL<848> A_IWL<847> A_IWL<846> A_IWL<845> A_IWL<844> A_IWL<843> A_IWL<842> A_IWL<841> A_IWL<840> A_IWL<839> A_IWL<838> A_IWL<837> A_IWL<836> A_IWL<835> A_IWL<834> A_IWL<833> A_IWL<832> A_IWL<831> A_IWL<830> A_IWL<829> A_IWL<828> A_IWL<827> A_IWL<826> A_IWL<825> A_IWL<824> A_IWL<823> A_IWL<822> A_IWL<821> A_IWL<820> A_IWL<819> A_IWL<818> A_IWL<817> A_IWL<816> A_IWL<815> A_IWL<814> A_IWL<813> A_IWL<812> A_IWL<811> A_IWL<810> A_IWL<809> A_IWL<808> A_IWL<807> A_IWL<806> A_IWL<805> A_IWL<804> A_IWL<803> A_IWL<802> A_IWL<801> A_IWL<800> A_IWL<799> A_IWL<798> A_IWL<797> A_IWL<796> A_IWL<795> A_IWL<794> A_IWL<793> A_IWL<792> A_IWL<791> A_IWL<790> A_IWL<789> A_IWL<788> A_IWL<787> A_IWL<786> A_IWL<785> A_IWL<784> A_IWL<783> A_IWL<782> A_IWL<781> A_IWL<780> A_IWL<779> A_IWL<778> A_IWL<777> A_IWL<776> A_IWL<775> A_IWL<774> A_IWL<773> A_IWL<772> A_IWL<771> A_IWL<770> A_IWL<769> A_IWL<768> B_BLC<13> B_BLC<12> B_BLC_TOP<13> B_BLC_TOP<12> B_BLT<13> B_BLT<12> B_BLT_TOP<13> B_BLT_TOP<12> B_IWL<767> B_IWL<766> B_IWL<765> B_IWL<764> B_IWL<763> B_IWL<762> B_IWL<761> B_IWL<760> B_IWL<759> B_IWL<758> B_IWL<757> B_IWL<756> B_IWL<755> B_IWL<754> B_IWL<753> B_IWL<752> B_IWL<751> B_IWL<750> B_IWL<749> B_IWL<748> B_IWL<747> B_IWL<746> B_IWL<745> B_IWL<744> B_IWL<743> B_IWL<742> B_IWL<741> B_IWL<740> B_IWL<739> B_IWL<738> B_IWL<737> B_IWL<736> B_IWL<735> B_IWL<734> B_IWL<733> B_IWL<732> B_IWL<731> B_IWL<730> B_IWL<729> B_IWL<728> B_IWL<727> B_IWL<726> B_IWL<725> B_IWL<724> B_IWL<723> B_IWL<722> B_IWL<721> B_IWL<720> B_IWL<719> B_IWL<718> B_IWL<717> B_IWL<716> B_IWL<715> B_IWL<714> B_IWL<713> B_IWL<712> B_IWL<711> B_IWL<710> B_IWL<709> B_IWL<708> B_IWL<707> B_IWL<706> B_IWL<705> B_IWL<704> B_IWL<703> B_IWL<702> B_IWL<701> B_IWL<700> B_IWL<699> B_IWL<698> B_IWL<697> B_IWL<696> B_IWL<695> B_IWL<694> B_IWL<693> B_IWL<692> B_IWL<691> B_IWL<690> B_IWL<689> B_IWL<688> B_IWL<687> B_IWL<686> B_IWL<685> B_IWL<684> B_IWL<683> B_IWL<682> B_IWL<681> B_IWL<680> B_IWL<679> B_IWL<678> B_IWL<677> B_IWL<676> B_IWL<675> B_IWL<674> B_IWL<673> B_IWL<672> B_IWL<671> B_IWL<670> B_IWL<669> B_IWL<668> B_IWL<667> B_IWL<666> B_IWL<665> B_IWL<664> B_IWL<663> B_IWL<662> B_IWL<661> B_IWL<660> B_IWL<659> B_IWL<658> B_IWL<657> B_IWL<656> B_IWL<655> B_IWL<654> B_IWL<653> B_IWL<652> B_IWL<651> B_IWL<650> B_IWL<649> B_IWL<648> B_IWL<647> B_IWL<646> B_IWL<645> B_IWL<644> B_IWL<643> B_IWL<642> B_IWL<641> B_IWL<640> B_IWL<895> B_IWL<894> B_IWL<893> B_IWL<892> B_IWL<891> B_IWL<890> B_IWL<889> B_IWL<888> B_IWL<887> B_IWL<886> B_IWL<885> B_IWL<884> B_IWL<883> B_IWL<882> B_IWL<881> B_IWL<880> B_IWL<879> B_IWL<878> B_IWL<877> B_IWL<876> B_IWL<875> B_IWL<874> B_IWL<873> B_IWL<872> B_IWL<871> B_IWL<870> B_IWL<869> B_IWL<868> B_IWL<867> B_IWL<866> B_IWL<865> B_IWL<864> B_IWL<863> B_IWL<862> B_IWL<861> B_IWL<860> B_IWL<859> B_IWL<858> B_IWL<857> B_IWL<856> B_IWL<855> B_IWL<854> B_IWL<853> B_IWL<852> B_IWL<851> B_IWL<850> B_IWL<849> B_IWL<848> B_IWL<847> B_IWL<846> B_IWL<845> B_IWL<844> B_IWL<843> B_IWL<842> B_IWL<841> B_IWL<840> B_IWL<839> B_IWL<838> B_IWL<837> B_IWL<836> B_IWL<835> B_IWL<834> B_IWL<833> B_IWL<832> B_IWL<831> B_IWL<830> B_IWL<829> B_IWL<828> B_IWL<827> B_IWL<826> B_IWL<825> B_IWL<824> B_IWL<823> B_IWL<822> B_IWL<821> B_IWL<820> B_IWL<819> B_IWL<818> B_IWL<817> B_IWL<816> B_IWL<815> B_IWL<814> B_IWL<813> B_IWL<812> B_IWL<811> B_IWL<810> B_IWL<809> B_IWL<808> B_IWL<807> B_IWL<806> B_IWL<805> B_IWL<804> B_IWL<803> B_IWL<802> B_IWL<801> B_IWL<800> B_IWL<799> B_IWL<798> B_IWL<797> B_IWL<796> B_IWL<795> B_IWL<794> B_IWL<793> B_IWL<792> B_IWL<791> B_IWL<790> B_IWL<789> B_IWL<788> B_IWL<787> B_IWL<786> B_IWL<785> B_IWL<784> B_IWL<783> B_IWL<782> B_IWL<781> B_IWL<780> B_IWL<779> B_IWL<778> B_IWL<777> B_IWL<776> B_IWL<775> B_IWL<774> B_IWL<773> B_IWL<772> B_IWL<771> B_IWL<770> B_IWL<769> B_IWL<768> VDD_CORE VSS / RM_IHPSG13_512x16_c2_2P_COLUMN_pcell_0 +XCOL<5> A_BLC<11> A_BLC<10> A_BLC_TOP<11> A_BLC_TOP<10> A_BLT<11> A_BLT<10> A_BLT_TOP<11> A_BLT_TOP<10> A_IWL<639> A_IWL<638> A_IWL<637> A_IWL<636> A_IWL<635> A_IWL<634> A_IWL<633> A_IWL<632> A_IWL<631> A_IWL<630> A_IWL<629> A_IWL<628> A_IWL<627> A_IWL<626> A_IWL<625> A_IWL<624> A_IWL<623> A_IWL<622> A_IWL<621> A_IWL<620> A_IWL<619> A_IWL<618> A_IWL<617> A_IWL<616> A_IWL<615> A_IWL<614> A_IWL<613> A_IWL<612> A_IWL<611> A_IWL<610> A_IWL<609> A_IWL<608> A_IWL<607> A_IWL<606> A_IWL<605> A_IWL<604> A_IWL<603> A_IWL<602> A_IWL<601> A_IWL<600> A_IWL<599> A_IWL<598> A_IWL<597> A_IWL<596> A_IWL<595> A_IWL<594> A_IWL<593> A_IWL<592> A_IWL<591> A_IWL<590> A_IWL<589> A_IWL<588> A_IWL<587> A_IWL<586> A_IWL<585> A_IWL<584> A_IWL<583> A_IWL<582> A_IWL<581> A_IWL<580> A_IWL<579> A_IWL<578> A_IWL<577> A_IWL<576> A_IWL<575> A_IWL<574> A_IWL<573> A_IWL<572> A_IWL<571> A_IWL<570> A_IWL<569> A_IWL<568> A_IWL<567> A_IWL<566> A_IWL<565> A_IWL<564> A_IWL<563> A_IWL<562> A_IWL<561> A_IWL<560> A_IWL<559> A_IWL<558> A_IWL<557> A_IWL<556> A_IWL<555> A_IWL<554> A_IWL<553> A_IWL<552> A_IWL<551> A_IWL<550> A_IWL<549> A_IWL<548> A_IWL<547> A_IWL<546> A_IWL<545> A_IWL<544> A_IWL<543> A_IWL<542> A_IWL<541> A_IWL<540> A_IWL<539> A_IWL<538> A_IWL<537> A_IWL<536> A_IWL<535> A_IWL<534> A_IWL<533> A_IWL<532> A_IWL<531> A_IWL<530> A_IWL<529> A_IWL<528> A_IWL<527> A_IWL<526> A_IWL<525> A_IWL<524> A_IWL<523> A_IWL<522> A_IWL<521> A_IWL<520> A_IWL<519> A_IWL<518> A_IWL<517> A_IWL<516> A_IWL<515> A_IWL<514> A_IWL<513> A_IWL<512> A_IWL<767> A_IWL<766> A_IWL<765> A_IWL<764> A_IWL<763> A_IWL<762> A_IWL<761> A_IWL<760> A_IWL<759> A_IWL<758> A_IWL<757> A_IWL<756> A_IWL<755> A_IWL<754> A_IWL<753> A_IWL<752> A_IWL<751> A_IWL<750> A_IWL<749> A_IWL<748> A_IWL<747> A_IWL<746> A_IWL<745> A_IWL<744> A_IWL<743> A_IWL<742> A_IWL<741> A_IWL<740> A_IWL<739> A_IWL<738> A_IWL<737> A_IWL<736> A_IWL<735> A_IWL<734> A_IWL<733> A_IWL<732> A_IWL<731> A_IWL<730> A_IWL<729> A_IWL<728> A_IWL<727> A_IWL<726> A_IWL<725> A_IWL<724> A_IWL<723> A_IWL<722> A_IWL<721> A_IWL<720> A_IWL<719> A_IWL<718> A_IWL<717> A_IWL<716> A_IWL<715> A_IWL<714> A_IWL<713> A_IWL<712> A_IWL<711> A_IWL<710> A_IWL<709> A_IWL<708> A_IWL<707> A_IWL<706> A_IWL<705> A_IWL<704> A_IWL<703> A_IWL<702> A_IWL<701> A_IWL<700> A_IWL<699> A_IWL<698> A_IWL<697> A_IWL<696> A_IWL<695> A_IWL<694> A_IWL<693> A_IWL<692> A_IWL<691> A_IWL<690> A_IWL<689> A_IWL<688> A_IWL<687> A_IWL<686> A_IWL<685> A_IWL<684> A_IWL<683> A_IWL<682> A_IWL<681> A_IWL<680> A_IWL<679> A_IWL<678> A_IWL<677> A_IWL<676> A_IWL<675> A_IWL<674> A_IWL<673> A_IWL<672> A_IWL<671> A_IWL<670> A_IWL<669> A_IWL<668> A_IWL<667> A_IWL<666> A_IWL<665> A_IWL<664> A_IWL<663> A_IWL<662> A_IWL<661> A_IWL<660> A_IWL<659> A_IWL<658> A_IWL<657> A_IWL<656> A_IWL<655> A_IWL<654> A_IWL<653> A_IWL<652> A_IWL<651> A_IWL<650> A_IWL<649> A_IWL<648> A_IWL<647> A_IWL<646> A_IWL<645> A_IWL<644> A_IWL<643> A_IWL<642> A_IWL<641> A_IWL<640> B_BLC<11> B_BLC<10> B_BLC_TOP<11> B_BLC_TOP<10> B_BLT<11> B_BLT<10> B_BLT_TOP<11> B_BLT_TOP<10> B_IWL<639> B_IWL<638> B_IWL<637> B_IWL<636> B_IWL<635> B_IWL<634> B_IWL<633> B_IWL<632> B_IWL<631> B_IWL<630> B_IWL<629> B_IWL<628> B_IWL<627> B_IWL<626> B_IWL<625> B_IWL<624> B_IWL<623> B_IWL<622> B_IWL<621> B_IWL<620> B_IWL<619> B_IWL<618> B_IWL<617> B_IWL<616> B_IWL<615> B_IWL<614> B_IWL<613> B_IWL<612> B_IWL<611> B_IWL<610> B_IWL<609> B_IWL<608> B_IWL<607> B_IWL<606> B_IWL<605> B_IWL<604> B_IWL<603> B_IWL<602> B_IWL<601> B_IWL<600> B_IWL<599> B_IWL<598> B_IWL<597> B_IWL<596> B_IWL<595> B_IWL<594> B_IWL<593> B_IWL<592> B_IWL<591> B_IWL<590> B_IWL<589> B_IWL<588> B_IWL<587> B_IWL<586> B_IWL<585> B_IWL<584> B_IWL<583> B_IWL<582> B_IWL<581> B_IWL<580> B_IWL<579> B_IWL<578> B_IWL<577> B_IWL<576> B_IWL<575> B_IWL<574> B_IWL<573> B_IWL<572> B_IWL<571> B_IWL<570> B_IWL<569> B_IWL<568> B_IWL<567> B_IWL<566> B_IWL<565> B_IWL<564> B_IWL<563> B_IWL<562> B_IWL<561> B_IWL<560> B_IWL<559> B_IWL<558> B_IWL<557> B_IWL<556> B_IWL<555> B_IWL<554> B_IWL<553> B_IWL<552> B_IWL<551> B_IWL<550> B_IWL<549> B_IWL<548> B_IWL<547> B_IWL<546> B_IWL<545> B_IWL<544> B_IWL<543> B_IWL<542> B_IWL<541> B_IWL<540> B_IWL<539> B_IWL<538> B_IWL<537> B_IWL<536> B_IWL<535> B_IWL<534> B_IWL<533> B_IWL<532> B_IWL<531> B_IWL<530> B_IWL<529> B_IWL<528> B_IWL<527> B_IWL<526> B_IWL<525> B_IWL<524> B_IWL<523> B_IWL<522> B_IWL<521> B_IWL<520> B_IWL<519> B_IWL<518> B_IWL<517> B_IWL<516> B_IWL<515> B_IWL<514> B_IWL<513> B_IWL<512> B_IWL<767> B_IWL<766> B_IWL<765> B_IWL<764> B_IWL<763> B_IWL<762> B_IWL<761> B_IWL<760> B_IWL<759> B_IWL<758> B_IWL<757> B_IWL<756> B_IWL<755> B_IWL<754> B_IWL<753> B_IWL<752> B_IWL<751> B_IWL<750> B_IWL<749> B_IWL<748> B_IWL<747> B_IWL<746> B_IWL<745> B_IWL<744> B_IWL<743> B_IWL<742> B_IWL<741> B_IWL<740> B_IWL<739> B_IWL<738> B_IWL<737> B_IWL<736> B_IWL<735> B_IWL<734> B_IWL<733> B_IWL<732> B_IWL<731> B_IWL<730> B_IWL<729> B_IWL<728> B_IWL<727> B_IWL<726> B_IWL<725> B_IWL<724> B_IWL<723> B_IWL<722> B_IWL<721> B_IWL<720> B_IWL<719> B_IWL<718> B_IWL<717> B_IWL<716> B_IWL<715> B_IWL<714> B_IWL<713> B_IWL<712> B_IWL<711> B_IWL<710> B_IWL<709> B_IWL<708> B_IWL<707> B_IWL<706> B_IWL<705> B_IWL<704> B_IWL<703> B_IWL<702> B_IWL<701> B_IWL<700> B_IWL<699> B_IWL<698> B_IWL<697> B_IWL<696> B_IWL<695> B_IWL<694> B_IWL<693> B_IWL<692> B_IWL<691> B_IWL<690> B_IWL<689> B_IWL<688> B_IWL<687> B_IWL<686> B_IWL<685> B_IWL<684> B_IWL<683> B_IWL<682> B_IWL<681> B_IWL<680> B_IWL<679> B_IWL<678> B_IWL<677> B_IWL<676> B_IWL<675> B_IWL<674> B_IWL<673> B_IWL<672> B_IWL<671> B_IWL<670> B_IWL<669> B_IWL<668> B_IWL<667> B_IWL<666> B_IWL<665> B_IWL<664> B_IWL<663> B_IWL<662> B_IWL<661> B_IWL<660> B_IWL<659> B_IWL<658> B_IWL<657> B_IWL<656> B_IWL<655> B_IWL<654> B_IWL<653> B_IWL<652> B_IWL<651> B_IWL<650> B_IWL<649> B_IWL<648> B_IWL<647> B_IWL<646> B_IWL<645> B_IWL<644> B_IWL<643> B_IWL<642> B_IWL<641> B_IWL<640> VDD_CORE VSS / RM_IHPSG13_512x16_c2_2P_COLUMN_pcell_0 +XCOL<4> A_BLC<9> A_BLC<8> A_BLC_TOP<9> A_BLC_TOP<8> A_BLT<9> A_BLT<8> A_BLT_TOP<9> A_BLT_TOP<8> A_IWL<511> A_IWL<510> A_IWL<509> A_IWL<508> A_IWL<507> A_IWL<506> A_IWL<505> A_IWL<504> A_IWL<503> A_IWL<502> A_IWL<501> A_IWL<500> A_IWL<499> A_IWL<498> A_IWL<497> A_IWL<496> A_IWL<495> A_IWL<494> A_IWL<493> A_IWL<492> A_IWL<491> A_IWL<490> A_IWL<489> A_IWL<488> A_IWL<487> A_IWL<486> A_IWL<485> A_IWL<484> A_IWL<483> A_IWL<482> A_IWL<481> A_IWL<480> A_IWL<479> A_IWL<478> A_IWL<477> A_IWL<476> A_IWL<475> A_IWL<474> A_IWL<473> A_IWL<472> A_IWL<471> A_IWL<470> A_IWL<469> A_IWL<468> A_IWL<467> A_IWL<466> A_IWL<465> A_IWL<464> A_IWL<463> A_IWL<462> A_IWL<461> A_IWL<460> A_IWL<459> A_IWL<458> A_IWL<457> A_IWL<456> A_IWL<455> A_IWL<454> A_IWL<453> A_IWL<452> A_IWL<451> A_IWL<450> A_IWL<449> A_IWL<448> A_IWL<447> A_IWL<446> A_IWL<445> A_IWL<444> A_IWL<443> A_IWL<442> A_IWL<441> A_IWL<440> A_IWL<439> A_IWL<438> A_IWL<437> A_IWL<436> A_IWL<435> A_IWL<434> A_IWL<433> A_IWL<432> A_IWL<431> A_IWL<430> A_IWL<429> A_IWL<428> A_IWL<427> A_IWL<426> A_IWL<425> A_IWL<424> A_IWL<423> A_IWL<422> A_IWL<421> A_IWL<420> A_IWL<419> A_IWL<418> A_IWL<417> A_IWL<416> A_IWL<415> A_IWL<414> A_IWL<413> A_IWL<412> A_IWL<411> A_IWL<410> A_IWL<409> A_IWL<408> A_IWL<407> A_IWL<406> A_IWL<405> A_IWL<404> A_IWL<403> A_IWL<402> A_IWL<401> A_IWL<400> A_IWL<399> A_IWL<398> A_IWL<397> A_IWL<396> A_IWL<395> A_IWL<394> A_IWL<393> A_IWL<392> A_IWL<391> A_IWL<390> A_IWL<389> A_IWL<388> A_IWL<387> A_IWL<386> A_IWL<385> A_IWL<384> A_IWL<639> A_IWL<638> A_IWL<637> A_IWL<636> A_IWL<635> A_IWL<634> A_IWL<633> A_IWL<632> A_IWL<631> A_IWL<630> A_IWL<629> A_IWL<628> A_IWL<627> A_IWL<626> A_IWL<625> A_IWL<624> A_IWL<623> A_IWL<622> A_IWL<621> A_IWL<620> A_IWL<619> A_IWL<618> A_IWL<617> A_IWL<616> A_IWL<615> A_IWL<614> A_IWL<613> A_IWL<612> A_IWL<611> A_IWL<610> A_IWL<609> A_IWL<608> A_IWL<607> A_IWL<606> A_IWL<605> A_IWL<604> A_IWL<603> A_IWL<602> A_IWL<601> A_IWL<600> A_IWL<599> A_IWL<598> A_IWL<597> A_IWL<596> A_IWL<595> A_IWL<594> A_IWL<593> A_IWL<592> A_IWL<591> A_IWL<590> A_IWL<589> A_IWL<588> A_IWL<587> A_IWL<586> A_IWL<585> A_IWL<584> A_IWL<583> A_IWL<582> A_IWL<581> A_IWL<580> A_IWL<579> A_IWL<578> A_IWL<577> A_IWL<576> A_IWL<575> A_IWL<574> A_IWL<573> A_IWL<572> A_IWL<571> A_IWL<570> A_IWL<569> A_IWL<568> A_IWL<567> A_IWL<566> A_IWL<565> A_IWL<564> A_IWL<563> A_IWL<562> A_IWL<561> A_IWL<560> A_IWL<559> A_IWL<558> A_IWL<557> A_IWL<556> A_IWL<555> A_IWL<554> A_IWL<553> A_IWL<552> A_IWL<551> A_IWL<550> A_IWL<549> A_IWL<548> A_IWL<547> A_IWL<546> A_IWL<545> A_IWL<544> A_IWL<543> A_IWL<542> A_IWL<541> A_IWL<540> A_IWL<539> A_IWL<538> A_IWL<537> A_IWL<536> A_IWL<535> A_IWL<534> A_IWL<533> A_IWL<532> A_IWL<531> A_IWL<530> A_IWL<529> A_IWL<528> A_IWL<527> A_IWL<526> A_IWL<525> A_IWL<524> A_IWL<523> A_IWL<522> A_IWL<521> A_IWL<520> A_IWL<519> A_IWL<518> A_IWL<517> A_IWL<516> A_IWL<515> A_IWL<514> A_IWL<513> A_IWL<512> B_BLC<9> B_BLC<8> B_BLC_TOP<9> B_BLC_TOP<8> B_BLT<9> B_BLT<8> B_BLT_TOP<9> B_BLT_TOP<8> B_IWL<511> B_IWL<510> B_IWL<509> B_IWL<508> B_IWL<507> B_IWL<506> B_IWL<505> B_IWL<504> B_IWL<503> B_IWL<502> B_IWL<501> B_IWL<500> B_IWL<499> B_IWL<498> B_IWL<497> B_IWL<496> B_IWL<495> B_IWL<494> B_IWL<493> B_IWL<492> B_IWL<491> B_IWL<490> B_IWL<489> B_IWL<488> B_IWL<487> B_IWL<486> B_IWL<485> B_IWL<484> B_IWL<483> B_IWL<482> B_IWL<481> B_IWL<480> B_IWL<479> B_IWL<478> B_IWL<477> B_IWL<476> B_IWL<475> B_IWL<474> B_IWL<473> B_IWL<472> B_IWL<471> B_IWL<470> B_IWL<469> B_IWL<468> B_IWL<467> B_IWL<466> B_IWL<465> B_IWL<464> B_IWL<463> B_IWL<462> B_IWL<461> B_IWL<460> B_IWL<459> B_IWL<458> B_IWL<457> B_IWL<456> B_IWL<455> B_IWL<454> B_IWL<453> B_IWL<452> B_IWL<451> B_IWL<450> B_IWL<449> B_IWL<448> B_IWL<447> B_IWL<446> B_IWL<445> B_IWL<444> B_IWL<443> B_IWL<442> B_IWL<441> B_IWL<440> B_IWL<439> B_IWL<438> B_IWL<437> B_IWL<436> B_IWL<435> B_IWL<434> B_IWL<433> B_IWL<432> B_IWL<431> B_IWL<430> B_IWL<429> B_IWL<428> B_IWL<427> B_IWL<426> B_IWL<425> B_IWL<424> B_IWL<423> B_IWL<422> B_IWL<421> B_IWL<420> B_IWL<419> B_IWL<418> B_IWL<417> B_IWL<416> B_IWL<415> B_IWL<414> B_IWL<413> B_IWL<412> B_IWL<411> B_IWL<410> B_IWL<409> B_IWL<408> B_IWL<407> B_IWL<406> B_IWL<405> B_IWL<404> B_IWL<403> B_IWL<402> B_IWL<401> B_IWL<400> B_IWL<399> B_IWL<398> B_IWL<397> B_IWL<396> B_IWL<395> B_IWL<394> B_IWL<393> B_IWL<392> B_IWL<391> B_IWL<390> B_IWL<389> B_IWL<388> B_IWL<387> B_IWL<386> B_IWL<385> B_IWL<384> B_IWL<639> B_IWL<638> B_IWL<637> B_IWL<636> B_IWL<635> B_IWL<634> B_IWL<633> B_IWL<632> B_IWL<631> B_IWL<630> B_IWL<629> B_IWL<628> B_IWL<627> B_IWL<626> B_IWL<625> B_IWL<624> B_IWL<623> B_IWL<622> B_IWL<621> B_IWL<620> B_IWL<619> B_IWL<618> B_IWL<617> B_IWL<616> B_IWL<615> B_IWL<614> B_IWL<613> B_IWL<612> B_IWL<611> B_IWL<610> B_IWL<609> B_IWL<608> B_IWL<607> B_IWL<606> B_IWL<605> B_IWL<604> B_IWL<603> B_IWL<602> B_IWL<601> B_IWL<600> B_IWL<599> B_IWL<598> B_IWL<597> B_IWL<596> B_IWL<595> B_IWL<594> B_IWL<593> B_IWL<592> B_IWL<591> B_IWL<590> B_IWL<589> B_IWL<588> B_IWL<587> B_IWL<586> B_IWL<585> B_IWL<584> B_IWL<583> B_IWL<582> B_IWL<581> B_IWL<580> B_IWL<579> B_IWL<578> B_IWL<577> B_IWL<576> B_IWL<575> B_IWL<574> B_IWL<573> B_IWL<572> B_IWL<571> B_IWL<570> B_IWL<569> B_IWL<568> B_IWL<567> B_IWL<566> B_IWL<565> B_IWL<564> B_IWL<563> B_IWL<562> B_IWL<561> B_IWL<560> B_IWL<559> B_IWL<558> B_IWL<557> B_IWL<556> B_IWL<555> B_IWL<554> B_IWL<553> B_IWL<552> B_IWL<551> B_IWL<550> B_IWL<549> B_IWL<548> B_IWL<547> B_IWL<546> B_IWL<545> B_IWL<544> B_IWL<543> B_IWL<542> B_IWL<541> B_IWL<540> B_IWL<539> B_IWL<538> B_IWL<537> B_IWL<536> B_IWL<535> B_IWL<534> B_IWL<533> B_IWL<532> B_IWL<531> B_IWL<530> B_IWL<529> B_IWL<528> B_IWL<527> B_IWL<526> B_IWL<525> B_IWL<524> B_IWL<523> B_IWL<522> B_IWL<521> B_IWL<520> B_IWL<519> B_IWL<518> B_IWL<517> B_IWL<516> B_IWL<515> B_IWL<514> B_IWL<513> B_IWL<512> VDD_CORE VSS / RM_IHPSG13_512x16_c2_2P_COLUMN_pcell_0 +XCOL<3> A_BLC<7> A_BLC<6> A_BLC_TOP<7> A_BLC_TOP<6> A_BLT<7> A_BLT<6> A_BLT_TOP<7> A_BLT_TOP<6> A_IWL<383> A_IWL<382> A_IWL<381> A_IWL<380> A_IWL<379> A_IWL<378> A_IWL<377> A_IWL<376> A_IWL<375> A_IWL<374> A_IWL<373> A_IWL<372> A_IWL<371> A_IWL<370> A_IWL<369> A_IWL<368> A_IWL<367> A_IWL<366> A_IWL<365> A_IWL<364> A_IWL<363> A_IWL<362> A_IWL<361> A_IWL<360> A_IWL<359> A_IWL<358> A_IWL<357> A_IWL<356> A_IWL<355> A_IWL<354> A_IWL<353> A_IWL<352> A_IWL<351> A_IWL<350> A_IWL<349> A_IWL<348> A_IWL<347> A_IWL<346> A_IWL<345> A_IWL<344> A_IWL<343> A_IWL<342> A_IWL<341> A_IWL<340> A_IWL<339> A_IWL<338> A_IWL<337> A_IWL<336> A_IWL<335> A_IWL<334> A_IWL<333> A_IWL<332> A_IWL<331> A_IWL<330> A_IWL<329> A_IWL<328> A_IWL<327> A_IWL<326> A_IWL<325> A_IWL<324> A_IWL<323> A_IWL<322> A_IWL<321> A_IWL<320> A_IWL<319> A_IWL<318> A_IWL<317> A_IWL<316> A_IWL<315> A_IWL<314> A_IWL<313> A_IWL<312> A_IWL<311> A_IWL<310> A_IWL<309> A_IWL<308> A_IWL<307> A_IWL<306> A_IWL<305> A_IWL<304> A_IWL<303> A_IWL<302> A_IWL<301> A_IWL<300> A_IWL<299> A_IWL<298> A_IWL<297> A_IWL<296> A_IWL<295> A_IWL<294> A_IWL<293> A_IWL<292> A_IWL<291> A_IWL<290> A_IWL<289> A_IWL<288> A_IWL<287> A_IWL<286> A_IWL<285> A_IWL<284> A_IWL<283> A_IWL<282> A_IWL<281> A_IWL<280> A_IWL<279> A_IWL<278> A_IWL<277> A_IWL<276> A_IWL<275> A_IWL<274> A_IWL<273> A_IWL<272> A_IWL<271> A_IWL<270> A_IWL<269> A_IWL<268> A_IWL<267> A_IWL<266> A_IWL<265> A_IWL<264> A_IWL<263> A_IWL<262> A_IWL<261> A_IWL<260> A_IWL<259> A_IWL<258> A_IWL<257> A_IWL<256> A_IWL<511> A_IWL<510> A_IWL<509> A_IWL<508> A_IWL<507> A_IWL<506> A_IWL<505> A_IWL<504> A_IWL<503> A_IWL<502> A_IWL<501> A_IWL<500> A_IWL<499> A_IWL<498> A_IWL<497> A_IWL<496> A_IWL<495> A_IWL<494> A_IWL<493> A_IWL<492> A_IWL<491> A_IWL<490> A_IWL<489> A_IWL<488> A_IWL<487> A_IWL<486> A_IWL<485> A_IWL<484> A_IWL<483> A_IWL<482> A_IWL<481> A_IWL<480> A_IWL<479> A_IWL<478> A_IWL<477> A_IWL<476> A_IWL<475> A_IWL<474> A_IWL<473> A_IWL<472> A_IWL<471> A_IWL<470> A_IWL<469> A_IWL<468> A_IWL<467> A_IWL<466> A_IWL<465> A_IWL<464> A_IWL<463> A_IWL<462> A_IWL<461> A_IWL<460> A_IWL<459> A_IWL<458> A_IWL<457> A_IWL<456> A_IWL<455> A_IWL<454> A_IWL<453> A_IWL<452> A_IWL<451> A_IWL<450> A_IWL<449> A_IWL<448> A_IWL<447> A_IWL<446> A_IWL<445> A_IWL<444> A_IWL<443> A_IWL<442> A_IWL<441> A_IWL<440> A_IWL<439> A_IWL<438> A_IWL<437> A_IWL<436> A_IWL<435> A_IWL<434> A_IWL<433> A_IWL<432> A_IWL<431> A_IWL<430> A_IWL<429> A_IWL<428> A_IWL<427> A_IWL<426> A_IWL<425> A_IWL<424> A_IWL<423> A_IWL<422> A_IWL<421> A_IWL<420> A_IWL<419> A_IWL<418> A_IWL<417> A_IWL<416> A_IWL<415> A_IWL<414> A_IWL<413> A_IWL<412> A_IWL<411> A_IWL<410> A_IWL<409> A_IWL<408> A_IWL<407> A_IWL<406> A_IWL<405> A_IWL<404> A_IWL<403> A_IWL<402> A_IWL<401> A_IWL<400> A_IWL<399> A_IWL<398> A_IWL<397> A_IWL<396> A_IWL<395> A_IWL<394> A_IWL<393> A_IWL<392> A_IWL<391> A_IWL<390> A_IWL<389> A_IWL<388> A_IWL<387> A_IWL<386> A_IWL<385> A_IWL<384> B_BLC<7> B_BLC<6> B_BLC_TOP<7> B_BLC_TOP<6> B_BLT<7> B_BLT<6> B_BLT_TOP<7> B_BLT_TOP<6> B_IWL<383> B_IWL<382> B_IWL<381> B_IWL<380> B_IWL<379> B_IWL<378> B_IWL<377> B_IWL<376> B_IWL<375> B_IWL<374> B_IWL<373> B_IWL<372> B_IWL<371> B_IWL<370> B_IWL<369> B_IWL<368> B_IWL<367> B_IWL<366> B_IWL<365> B_IWL<364> B_IWL<363> B_IWL<362> B_IWL<361> B_IWL<360> B_IWL<359> B_IWL<358> B_IWL<357> B_IWL<356> B_IWL<355> B_IWL<354> B_IWL<353> B_IWL<352> B_IWL<351> B_IWL<350> B_IWL<349> B_IWL<348> B_IWL<347> B_IWL<346> B_IWL<345> B_IWL<344> B_IWL<343> B_IWL<342> B_IWL<341> B_IWL<340> B_IWL<339> B_IWL<338> B_IWL<337> B_IWL<336> B_IWL<335> B_IWL<334> B_IWL<333> B_IWL<332> B_IWL<331> B_IWL<330> B_IWL<329> B_IWL<328> B_IWL<327> B_IWL<326> B_IWL<325> B_IWL<324> B_IWL<323> B_IWL<322> B_IWL<321> B_IWL<320> B_IWL<319> B_IWL<318> B_IWL<317> B_IWL<316> B_IWL<315> B_IWL<314> B_IWL<313> B_IWL<312> B_IWL<311> B_IWL<310> B_IWL<309> B_IWL<308> B_IWL<307> B_IWL<306> B_IWL<305> B_IWL<304> B_IWL<303> B_IWL<302> B_IWL<301> B_IWL<300> B_IWL<299> B_IWL<298> B_IWL<297> B_IWL<296> B_IWL<295> B_IWL<294> B_IWL<293> B_IWL<292> B_IWL<291> B_IWL<290> B_IWL<289> B_IWL<288> B_IWL<287> B_IWL<286> B_IWL<285> B_IWL<284> B_IWL<283> B_IWL<282> B_IWL<281> B_IWL<280> B_IWL<279> B_IWL<278> B_IWL<277> B_IWL<276> B_IWL<275> B_IWL<274> B_IWL<273> B_IWL<272> B_IWL<271> B_IWL<270> B_IWL<269> B_IWL<268> B_IWL<267> B_IWL<266> B_IWL<265> B_IWL<264> B_IWL<263> B_IWL<262> B_IWL<261> B_IWL<260> B_IWL<259> B_IWL<258> B_IWL<257> B_IWL<256> B_IWL<511> B_IWL<510> B_IWL<509> B_IWL<508> B_IWL<507> B_IWL<506> B_IWL<505> B_IWL<504> B_IWL<503> B_IWL<502> B_IWL<501> B_IWL<500> B_IWL<499> B_IWL<498> B_IWL<497> B_IWL<496> B_IWL<495> B_IWL<494> B_IWL<493> B_IWL<492> B_IWL<491> B_IWL<490> B_IWL<489> B_IWL<488> B_IWL<487> B_IWL<486> B_IWL<485> B_IWL<484> B_IWL<483> B_IWL<482> B_IWL<481> B_IWL<480> B_IWL<479> B_IWL<478> B_IWL<477> B_IWL<476> B_IWL<475> B_IWL<474> B_IWL<473> B_IWL<472> B_IWL<471> B_IWL<470> B_IWL<469> B_IWL<468> B_IWL<467> B_IWL<466> B_IWL<465> B_IWL<464> B_IWL<463> B_IWL<462> B_IWL<461> B_IWL<460> B_IWL<459> B_IWL<458> B_IWL<457> B_IWL<456> B_IWL<455> B_IWL<454> B_IWL<453> B_IWL<452> B_IWL<451> B_IWL<450> B_IWL<449> B_IWL<448> B_IWL<447> B_IWL<446> B_IWL<445> B_IWL<444> B_IWL<443> B_IWL<442> B_IWL<441> B_IWL<440> B_IWL<439> B_IWL<438> B_IWL<437> B_IWL<436> B_IWL<435> B_IWL<434> B_IWL<433> B_IWL<432> B_IWL<431> B_IWL<430> B_IWL<429> B_IWL<428> B_IWL<427> B_IWL<426> B_IWL<425> B_IWL<424> B_IWL<423> B_IWL<422> B_IWL<421> B_IWL<420> B_IWL<419> B_IWL<418> B_IWL<417> B_IWL<416> B_IWL<415> B_IWL<414> B_IWL<413> B_IWL<412> B_IWL<411> B_IWL<410> B_IWL<409> B_IWL<408> B_IWL<407> B_IWL<406> B_IWL<405> B_IWL<404> B_IWL<403> B_IWL<402> B_IWL<401> B_IWL<400> B_IWL<399> B_IWL<398> B_IWL<397> B_IWL<396> B_IWL<395> B_IWL<394> B_IWL<393> B_IWL<392> B_IWL<391> B_IWL<390> B_IWL<389> B_IWL<388> B_IWL<387> B_IWL<386> B_IWL<385> B_IWL<384> VDD_CORE VSS / RM_IHPSG13_512x16_c2_2P_COLUMN_pcell_0 +XCOL<2> A_BLC<5> A_BLC<4> A_BLC_TOP<5> A_BLC_TOP<4> A_BLT<5> A_BLT<4> A_BLT_TOP<5> A_BLT_TOP<4> A_IWL<255> A_IWL<254> A_IWL<253> A_IWL<252> A_IWL<251> A_IWL<250> A_IWL<249> A_IWL<248> A_IWL<247> A_IWL<246> A_IWL<245> A_IWL<244> A_IWL<243> A_IWL<242> A_IWL<241> A_IWL<240> A_IWL<239> A_IWL<238> A_IWL<237> A_IWL<236> A_IWL<235> A_IWL<234> A_IWL<233> A_IWL<232> A_IWL<231> A_IWL<230> A_IWL<229> A_IWL<228> A_IWL<227> A_IWL<226> A_IWL<225> A_IWL<224> A_IWL<223> A_IWL<222> A_IWL<221> A_IWL<220> A_IWL<219> A_IWL<218> A_IWL<217> A_IWL<216> A_IWL<215> A_IWL<214> A_IWL<213> A_IWL<212> A_IWL<211> A_IWL<210> A_IWL<209> A_IWL<208> A_IWL<207> A_IWL<206> A_IWL<205> A_IWL<204> A_IWL<203> A_IWL<202> A_IWL<201> A_IWL<200> A_IWL<199> A_IWL<198> A_IWL<197> A_IWL<196> A_IWL<195> A_IWL<194> A_IWL<193> A_IWL<192> A_IWL<191> A_IWL<190> A_IWL<189> A_IWL<188> A_IWL<187> A_IWL<186> A_IWL<185> A_IWL<184> A_IWL<183> A_IWL<182> A_IWL<181> A_IWL<180> A_IWL<179> A_IWL<178> A_IWL<177> A_IWL<176> A_IWL<175> A_IWL<174> A_IWL<173> A_IWL<172> A_IWL<171> A_IWL<170> A_IWL<169> A_IWL<168> A_IWL<167> A_IWL<166> A_IWL<165> A_IWL<164> A_IWL<163> A_IWL<162> A_IWL<161> A_IWL<160> A_IWL<159> A_IWL<158> A_IWL<157> A_IWL<156> A_IWL<155> A_IWL<154> A_IWL<153> A_IWL<152> A_IWL<151> A_IWL<150> A_IWL<149> A_IWL<148> A_IWL<147> A_IWL<146> A_IWL<145> A_IWL<144> A_IWL<143> A_IWL<142> A_IWL<141> A_IWL<140> A_IWL<139> A_IWL<138> A_IWL<137> A_IWL<136> A_IWL<135> A_IWL<134> A_IWL<133> A_IWL<132> A_IWL<131> A_IWL<130> A_IWL<129> A_IWL<128> A_IWL<383> A_IWL<382> A_IWL<381> A_IWL<380> A_IWL<379> A_IWL<378> A_IWL<377> A_IWL<376> A_IWL<375> A_IWL<374> A_IWL<373> A_IWL<372> A_IWL<371> A_IWL<370> A_IWL<369> A_IWL<368> A_IWL<367> A_IWL<366> A_IWL<365> A_IWL<364> A_IWL<363> A_IWL<362> A_IWL<361> A_IWL<360> A_IWL<359> A_IWL<358> A_IWL<357> A_IWL<356> A_IWL<355> A_IWL<354> A_IWL<353> A_IWL<352> A_IWL<351> A_IWL<350> A_IWL<349> A_IWL<348> A_IWL<347> A_IWL<346> A_IWL<345> A_IWL<344> A_IWL<343> A_IWL<342> A_IWL<341> A_IWL<340> A_IWL<339> A_IWL<338> A_IWL<337> A_IWL<336> A_IWL<335> A_IWL<334> A_IWL<333> A_IWL<332> A_IWL<331> A_IWL<330> A_IWL<329> A_IWL<328> A_IWL<327> A_IWL<326> A_IWL<325> A_IWL<324> A_IWL<323> A_IWL<322> A_IWL<321> A_IWL<320> A_IWL<319> A_IWL<318> A_IWL<317> A_IWL<316> A_IWL<315> A_IWL<314> A_IWL<313> A_IWL<312> A_IWL<311> A_IWL<310> A_IWL<309> A_IWL<308> A_IWL<307> A_IWL<306> A_IWL<305> A_IWL<304> A_IWL<303> A_IWL<302> A_IWL<301> A_IWL<300> A_IWL<299> A_IWL<298> A_IWL<297> A_IWL<296> A_IWL<295> A_IWL<294> A_IWL<293> A_IWL<292> A_IWL<291> A_IWL<290> A_IWL<289> A_IWL<288> A_IWL<287> A_IWL<286> A_IWL<285> A_IWL<284> A_IWL<283> A_IWL<282> A_IWL<281> A_IWL<280> A_IWL<279> A_IWL<278> A_IWL<277> A_IWL<276> A_IWL<275> A_IWL<274> A_IWL<273> A_IWL<272> A_IWL<271> A_IWL<270> A_IWL<269> A_IWL<268> A_IWL<267> A_IWL<266> A_IWL<265> A_IWL<264> A_IWL<263> A_IWL<262> A_IWL<261> A_IWL<260> A_IWL<259> A_IWL<258> A_IWL<257> A_IWL<256> B_BLC<5> B_BLC<4> B_BLC_TOP<5> B_BLC_TOP<4> B_BLT<5> B_BLT<4> B_BLT_TOP<5> B_BLT_TOP<4> B_IWL<255> B_IWL<254> B_IWL<253> B_IWL<252> B_IWL<251> B_IWL<250> B_IWL<249> B_IWL<248> B_IWL<247> B_IWL<246> B_IWL<245> B_IWL<244> B_IWL<243> B_IWL<242> B_IWL<241> B_IWL<240> B_IWL<239> B_IWL<238> B_IWL<237> B_IWL<236> B_IWL<235> B_IWL<234> B_IWL<233> B_IWL<232> B_IWL<231> B_IWL<230> B_IWL<229> B_IWL<228> B_IWL<227> B_IWL<226> B_IWL<225> B_IWL<224> B_IWL<223> B_IWL<222> B_IWL<221> B_IWL<220> B_IWL<219> B_IWL<218> B_IWL<217> B_IWL<216> B_IWL<215> B_IWL<214> B_IWL<213> B_IWL<212> B_IWL<211> B_IWL<210> B_IWL<209> B_IWL<208> B_IWL<207> B_IWL<206> B_IWL<205> B_IWL<204> B_IWL<203> B_IWL<202> B_IWL<201> B_IWL<200> B_IWL<199> B_IWL<198> B_IWL<197> B_IWL<196> B_IWL<195> B_IWL<194> B_IWL<193> B_IWL<192> B_IWL<191> B_IWL<190> B_IWL<189> B_IWL<188> B_IWL<187> B_IWL<186> B_IWL<185> B_IWL<184> B_IWL<183> B_IWL<182> B_IWL<181> B_IWL<180> B_IWL<179> B_IWL<178> B_IWL<177> B_IWL<176> B_IWL<175> B_IWL<174> B_IWL<173> B_IWL<172> B_IWL<171> B_IWL<170> B_IWL<169> B_IWL<168> B_IWL<167> B_IWL<166> B_IWL<165> B_IWL<164> B_IWL<163> B_IWL<162> B_IWL<161> B_IWL<160> B_IWL<159> B_IWL<158> B_IWL<157> B_IWL<156> B_IWL<155> B_IWL<154> B_IWL<153> B_IWL<152> B_IWL<151> B_IWL<150> B_IWL<149> B_IWL<148> B_IWL<147> B_IWL<146> B_IWL<145> B_IWL<144> B_IWL<143> B_IWL<142> B_IWL<141> B_IWL<140> B_IWL<139> B_IWL<138> B_IWL<137> B_IWL<136> B_IWL<135> B_IWL<134> B_IWL<133> B_IWL<132> B_IWL<131> B_IWL<130> B_IWL<129> B_IWL<128> B_IWL<383> B_IWL<382> B_IWL<381> B_IWL<380> B_IWL<379> B_IWL<378> B_IWL<377> B_IWL<376> B_IWL<375> B_IWL<374> B_IWL<373> B_IWL<372> B_IWL<371> B_IWL<370> B_IWL<369> B_IWL<368> B_IWL<367> B_IWL<366> B_IWL<365> B_IWL<364> B_IWL<363> B_IWL<362> B_IWL<361> B_IWL<360> B_IWL<359> B_IWL<358> B_IWL<357> B_IWL<356> B_IWL<355> B_IWL<354> B_IWL<353> B_IWL<352> B_IWL<351> B_IWL<350> B_IWL<349> B_IWL<348> B_IWL<347> B_IWL<346> B_IWL<345> B_IWL<344> B_IWL<343> B_IWL<342> B_IWL<341> B_IWL<340> B_IWL<339> B_IWL<338> B_IWL<337> B_IWL<336> B_IWL<335> B_IWL<334> B_IWL<333> B_IWL<332> B_IWL<331> B_IWL<330> B_IWL<329> B_IWL<328> B_IWL<327> B_IWL<326> B_IWL<325> B_IWL<324> B_IWL<323> B_IWL<322> B_IWL<321> B_IWL<320> B_IWL<319> B_IWL<318> B_IWL<317> B_IWL<316> B_IWL<315> B_IWL<314> B_IWL<313> B_IWL<312> B_IWL<311> B_IWL<310> B_IWL<309> B_IWL<308> B_IWL<307> B_IWL<306> B_IWL<305> B_IWL<304> B_IWL<303> B_IWL<302> B_IWL<301> B_IWL<300> B_IWL<299> B_IWL<298> B_IWL<297> B_IWL<296> B_IWL<295> B_IWL<294> B_IWL<293> B_IWL<292> B_IWL<291> B_IWL<290> B_IWL<289> B_IWL<288> B_IWL<287> B_IWL<286> B_IWL<285> B_IWL<284> B_IWL<283> B_IWL<282> B_IWL<281> B_IWL<280> B_IWL<279> B_IWL<278> B_IWL<277> B_IWL<276> B_IWL<275> B_IWL<274> B_IWL<273> B_IWL<272> B_IWL<271> B_IWL<270> B_IWL<269> B_IWL<268> B_IWL<267> B_IWL<266> B_IWL<265> B_IWL<264> B_IWL<263> B_IWL<262> B_IWL<261> B_IWL<260> B_IWL<259> B_IWL<258> B_IWL<257> B_IWL<256> VDD_CORE VSS / RM_IHPSG13_512x16_c2_2P_COLUMN_pcell_0 +XCOL<1> A_BLC<3> A_BLC<2> A_BLC_TOP<3> A_BLC_TOP<2> A_BLT<3> A_BLT<2> A_BLT_TOP<3> A_BLT_TOP<2> A_IWL<127> A_IWL<126> A_IWL<125> A_IWL<124> A_IWL<123> A_IWL<122> A_IWL<121> A_IWL<120> A_IWL<119> A_IWL<118> A_IWL<117> A_IWL<116> A_IWL<115> A_IWL<114> A_IWL<113> A_IWL<112> A_IWL<111> A_IWL<110> A_IWL<109> A_IWL<108> A_IWL<107> A_IWL<106> A_IWL<105> A_IWL<104> A_IWL<103> A_IWL<102> A_IWL<101> A_IWL<100> A_IWL<99> A_IWL<98> A_IWL<97> A_IWL<96> A_IWL<95> A_IWL<94> A_IWL<93> A_IWL<92> A_IWL<91> A_IWL<90> A_IWL<89> A_IWL<88> A_IWL<87> A_IWL<86> A_IWL<85> A_IWL<84> A_IWL<83> A_IWL<82> A_IWL<81> A_IWL<80> A_IWL<79> A_IWL<78> A_IWL<77> A_IWL<76> A_IWL<75> A_IWL<74> A_IWL<73> A_IWL<72> A_IWL<71> A_IWL<70> A_IWL<69> A_IWL<68> A_IWL<67> A_IWL<66> A_IWL<65> A_IWL<64> A_IWL<63> A_IWL<62> A_IWL<61> A_IWL<60> A_IWL<59> A_IWL<58> A_IWL<57> A_IWL<56> A_IWL<55> A_IWL<54> A_IWL<53> A_IWL<52> A_IWL<51> A_IWL<50> A_IWL<49> A_IWL<48> A_IWL<47> A_IWL<46> A_IWL<45> A_IWL<44> A_IWL<43> A_IWL<42> A_IWL<41> A_IWL<40> A_IWL<39> A_IWL<38> A_IWL<37> A_IWL<36> A_IWL<35> A_IWL<34> A_IWL<33> A_IWL<32> A_IWL<31> A_IWL<30> A_IWL<29> A_IWL<28> A_IWL<27> A_IWL<26> A_IWL<25> A_IWL<24> A_IWL<23> A_IWL<22> A_IWL<21> A_IWL<20> A_IWL<19> A_IWL<18> A_IWL<17> A_IWL<16> A_IWL<15> A_IWL<14> A_IWL<13> A_IWL<12> A_IWL<11> A_IWL<10> A_IWL<9> A_IWL<8> A_IWL<7> A_IWL<6> A_IWL<5> A_IWL<4> A_IWL<3> A_IWL<2> A_IWL<1> A_IWL<0> A_IWL<255> A_IWL<254> A_IWL<253> A_IWL<252> A_IWL<251> A_IWL<250> A_IWL<249> A_IWL<248> A_IWL<247> A_IWL<246> A_IWL<245> A_IWL<244> A_IWL<243> A_IWL<242> A_IWL<241> A_IWL<240> A_IWL<239> A_IWL<238> A_IWL<237> A_IWL<236> A_IWL<235> A_IWL<234> A_IWL<233> A_IWL<232> A_IWL<231> A_IWL<230> A_IWL<229> A_IWL<228> A_IWL<227> A_IWL<226> A_IWL<225> A_IWL<224> A_IWL<223> A_IWL<222> A_IWL<221> A_IWL<220> A_IWL<219> A_IWL<218> A_IWL<217> A_IWL<216> A_IWL<215> A_IWL<214> A_IWL<213> A_IWL<212> A_IWL<211> A_IWL<210> A_IWL<209> A_IWL<208> A_IWL<207> A_IWL<206> A_IWL<205> A_IWL<204> A_IWL<203> A_IWL<202> A_IWL<201> A_IWL<200> A_IWL<199> A_IWL<198> A_IWL<197> A_IWL<196> A_IWL<195> A_IWL<194> A_IWL<193> A_IWL<192> A_IWL<191> A_IWL<190> A_IWL<189> A_IWL<188> A_IWL<187> A_IWL<186> A_IWL<185> A_IWL<184> A_IWL<183> A_IWL<182> A_IWL<181> A_IWL<180> A_IWL<179> A_IWL<178> A_IWL<177> A_IWL<176> A_IWL<175> A_IWL<174> A_IWL<173> A_IWL<172> A_IWL<171> A_IWL<170> A_IWL<169> A_IWL<168> A_IWL<167> A_IWL<166> A_IWL<165> A_IWL<164> A_IWL<163> A_IWL<162> A_IWL<161> A_IWL<160> A_IWL<159> A_IWL<158> A_IWL<157> A_IWL<156> A_IWL<155> A_IWL<154> A_IWL<153> A_IWL<152> A_IWL<151> A_IWL<150> A_IWL<149> A_IWL<148> A_IWL<147> A_IWL<146> A_IWL<145> A_IWL<144> A_IWL<143> A_IWL<142> A_IWL<141> A_IWL<140> A_IWL<139> A_IWL<138> A_IWL<137> A_IWL<136> A_IWL<135> A_IWL<134> A_IWL<133> A_IWL<132> A_IWL<131> A_IWL<130> A_IWL<129> A_IWL<128> B_BLC<3> B_BLC<2> B_BLC_TOP<3> B_BLC_TOP<2> B_BLT<3> B_BLT<2> B_BLT_TOP<3> B_BLT_TOP<2> B_IWL<127> B_IWL<126> B_IWL<125> B_IWL<124> B_IWL<123> B_IWL<122> B_IWL<121> B_IWL<120> B_IWL<119> B_IWL<118> B_IWL<117> B_IWL<116> B_IWL<115> B_IWL<114> B_IWL<113> B_IWL<112> B_IWL<111> B_IWL<110> B_IWL<109> B_IWL<108> B_IWL<107> B_IWL<106> B_IWL<105> B_IWL<104> B_IWL<103> B_IWL<102> B_IWL<101> B_IWL<100> B_IWL<99> B_IWL<98> B_IWL<97> B_IWL<96> B_IWL<95> B_IWL<94> B_IWL<93> B_IWL<92> B_IWL<91> B_IWL<90> B_IWL<89> B_IWL<88> B_IWL<87> B_IWL<86> B_IWL<85> B_IWL<84> B_IWL<83> B_IWL<82> B_IWL<81> B_IWL<80> B_IWL<79> B_IWL<78> B_IWL<77> B_IWL<76> B_IWL<75> B_IWL<74> B_IWL<73> B_IWL<72> B_IWL<71> B_IWL<70> B_IWL<69> B_IWL<68> B_IWL<67> B_IWL<66> B_IWL<65> B_IWL<64> B_IWL<63> B_IWL<62> B_IWL<61> B_IWL<60> B_IWL<59> B_IWL<58> B_IWL<57> B_IWL<56> B_IWL<55> B_IWL<54> B_IWL<53> B_IWL<52> B_IWL<51> B_IWL<50> B_IWL<49> B_IWL<48> B_IWL<47> B_IWL<46> B_IWL<45> B_IWL<44> B_IWL<43> B_IWL<42> B_IWL<41> B_IWL<40> B_IWL<39> B_IWL<38> B_IWL<37> B_IWL<36> B_IWL<35> B_IWL<34> B_IWL<33> B_IWL<32> B_IWL<31> B_IWL<30> B_IWL<29> B_IWL<28> B_IWL<27> B_IWL<26> B_IWL<25> B_IWL<24> B_IWL<23> B_IWL<22> B_IWL<21> B_IWL<20> B_IWL<19> B_IWL<18> B_IWL<17> B_IWL<16> B_IWL<15> B_IWL<14> B_IWL<13> B_IWL<12> B_IWL<11> B_IWL<10> B_IWL<9> B_IWL<8> B_IWL<7> B_IWL<6> B_IWL<5> B_IWL<4> B_IWL<3> B_IWL<2> B_IWL<1> B_IWL<0> B_IWL<255> B_IWL<254> B_IWL<253> B_IWL<252> B_IWL<251> B_IWL<250> B_IWL<249> B_IWL<248> B_IWL<247> B_IWL<246> B_IWL<245> B_IWL<244> B_IWL<243> B_IWL<242> B_IWL<241> B_IWL<240> B_IWL<239> B_IWL<238> B_IWL<237> B_IWL<236> B_IWL<235> B_IWL<234> B_IWL<233> B_IWL<232> B_IWL<231> B_IWL<230> B_IWL<229> B_IWL<228> B_IWL<227> B_IWL<226> B_IWL<225> B_IWL<224> B_IWL<223> B_IWL<222> B_IWL<221> B_IWL<220> B_IWL<219> B_IWL<218> B_IWL<217> B_IWL<216> B_IWL<215> B_IWL<214> B_IWL<213> B_IWL<212> B_IWL<211> B_IWL<210> B_IWL<209> B_IWL<208> B_IWL<207> B_IWL<206> B_IWL<205> B_IWL<204> B_IWL<203> B_IWL<202> B_IWL<201> B_IWL<200> B_IWL<199> B_IWL<198> B_IWL<197> B_IWL<196> B_IWL<195> B_IWL<194> B_IWL<193> B_IWL<192> B_IWL<191> B_IWL<190> B_IWL<189> B_IWL<188> B_IWL<187> B_IWL<186> B_IWL<185> B_IWL<184> B_IWL<183> B_IWL<182> B_IWL<181> B_IWL<180> B_IWL<179> B_IWL<178> B_IWL<177> B_IWL<176> B_IWL<175> B_IWL<174> B_IWL<173> B_IWL<172> B_IWL<171> B_IWL<170> B_IWL<169> B_IWL<168> B_IWL<167> B_IWL<166> B_IWL<165> B_IWL<164> B_IWL<163> B_IWL<162> B_IWL<161> B_IWL<160> B_IWL<159> B_IWL<158> B_IWL<157> B_IWL<156> B_IWL<155> B_IWL<154> B_IWL<153> B_IWL<152> B_IWL<151> B_IWL<150> B_IWL<149> B_IWL<148> B_IWL<147> B_IWL<146> B_IWL<145> B_IWL<144> B_IWL<143> B_IWL<142> B_IWL<141> B_IWL<140> B_IWL<139> B_IWL<138> B_IWL<137> B_IWL<136> B_IWL<135> B_IWL<134> B_IWL<133> B_IWL<132> B_IWL<131> B_IWL<130> B_IWL<129> B_IWL<128> VDD_CORE VSS / RM_IHPSG13_512x16_c2_2P_COLUMN_pcell_0 +XCOL<0> A_BLC<1> A_BLC<0> A_BLC_TOP<1> A_BLC_TOP<0> A_BLT<1> A_BLT<0> A_BLT_TOP<1> A_BLT_TOP<0> A_WL<127> A_WL<126> A_WL<125> A_WL<124> A_WL<123> A_WL<122> A_WL<121> A_WL<120> A_WL<119> A_WL<118> A_WL<117> A_WL<116> A_WL<115> A_WL<114> A_WL<113> A_WL<112> A_WL<111> A_WL<110> A_WL<109> A_WL<108> A_WL<107> A_WL<106> A_WL<105> A_WL<104> A_WL<103> A_WL<102> A_WL<101> A_WL<100> A_WL<99> A_WL<98> A_WL<97> A_WL<96> A_WL<95> A_WL<94> A_WL<93> A_WL<92> A_WL<91> A_WL<90> A_WL<89> A_WL<88> A_WL<87> A_WL<86> A_WL<85> A_WL<84> A_WL<83> A_WL<82> A_WL<81> A_WL<80> A_WL<79> A_WL<78> A_WL<77> A_WL<76> A_WL<75> A_WL<74> A_WL<73> A_WL<72> A_WL<71> A_WL<70> A_WL<69> A_WL<68> A_WL<67> A_WL<66> A_WL<65> A_WL<64> A_WL<63> A_WL<62> A_WL<61> A_WL<60> A_WL<59> A_WL<58> A_WL<57> A_WL<56> A_WL<55> A_WL<54> A_WL<53> A_WL<52> A_WL<51> A_WL<50> A_WL<49> A_WL<48> A_WL<47> A_WL<46> A_WL<45> A_WL<44> A_WL<43> A_WL<42> A_WL<41> A_WL<40> A_WL<39> A_WL<38> A_WL<37> A_WL<36> A_WL<35> A_WL<34> A_WL<33> A_WL<32> A_WL<31> A_WL<30> A_WL<29> A_WL<28> A_WL<27> A_WL<26> A_WL<25> A_WL<24> A_WL<23> A_WL<22> A_WL<21> A_WL<20> A_WL<19> A_WL<18> A_WL<17> A_WL<16> A_WL<15> A_WL<14> A_WL<13> A_WL<12> A_WL<11> A_WL<10> A_WL<9> A_WL<8> A_WL<7> A_WL<6> A_WL<5> A_WL<4> A_WL<3> A_WL<2> A_WL<1> A_WL<0> A_IWL<127> A_IWL<126> A_IWL<125> A_IWL<124> A_IWL<123> A_IWL<122> A_IWL<121> A_IWL<120> A_IWL<119> A_IWL<118> A_IWL<117> A_IWL<116> A_IWL<115> A_IWL<114> A_IWL<113> A_IWL<112> A_IWL<111> A_IWL<110> A_IWL<109> A_IWL<108> A_IWL<107> A_IWL<106> A_IWL<105> A_IWL<104> A_IWL<103> A_IWL<102> A_IWL<101> A_IWL<100> A_IWL<99> A_IWL<98> A_IWL<97> A_IWL<96> A_IWL<95> A_IWL<94> A_IWL<93> A_IWL<92> A_IWL<91> A_IWL<90> A_IWL<89> A_IWL<88> A_IWL<87> A_IWL<86> A_IWL<85> A_IWL<84> A_IWL<83> A_IWL<82> A_IWL<81> A_IWL<80> A_IWL<79> A_IWL<78> A_IWL<77> A_IWL<76> A_IWL<75> A_IWL<74> A_IWL<73> A_IWL<72> A_IWL<71> A_IWL<70> A_IWL<69> A_IWL<68> A_IWL<67> A_IWL<66> A_IWL<65> A_IWL<64> A_IWL<63> A_IWL<62> A_IWL<61> A_IWL<60> A_IWL<59> A_IWL<58> A_IWL<57> A_IWL<56> A_IWL<55> A_IWL<54> A_IWL<53> A_IWL<52> A_IWL<51> A_IWL<50> A_IWL<49> A_IWL<48> A_IWL<47> A_IWL<46> A_IWL<45> A_IWL<44> A_IWL<43> A_IWL<42> A_IWL<41> A_IWL<40> A_IWL<39> A_IWL<38> A_IWL<37> A_IWL<36> A_IWL<35> A_IWL<34> A_IWL<33> A_IWL<32> A_IWL<31> A_IWL<30> A_IWL<29> A_IWL<28> A_IWL<27> A_IWL<26> A_IWL<25> A_IWL<24> A_IWL<23> A_IWL<22> A_IWL<21> A_IWL<20> A_IWL<19> A_IWL<18> A_IWL<17> A_IWL<16> A_IWL<15> A_IWL<14> A_IWL<13> A_IWL<12> A_IWL<11> A_IWL<10> A_IWL<9> A_IWL<8> A_IWL<7> A_IWL<6> A_IWL<5> A_IWL<4> A_IWL<3> A_IWL<2> A_IWL<1> A_IWL<0> B_BLC<1> B_BLC<0> B_BLC_TOP<1> B_BLC_TOP<0> B_BLT<1> B_BLT<0> B_BLT_TOP<1> B_BLT_TOP<0> B_WL<127> B_WL<126> B_WL<125> B_WL<124> B_WL<123> B_WL<122> B_WL<121> B_WL<120> B_WL<119> B_WL<118> B_WL<117> B_WL<116> B_WL<115> B_WL<114> B_WL<113> B_WL<112> B_WL<111> B_WL<110> B_WL<109> B_WL<108> B_WL<107> B_WL<106> B_WL<105> B_WL<104> B_WL<103> B_WL<102> B_WL<101> B_WL<100> B_WL<99> B_WL<98> B_WL<97> B_WL<96> B_WL<95> B_WL<94> B_WL<93> B_WL<92> B_WL<91> B_WL<90> B_WL<89> B_WL<88> B_WL<87> B_WL<86> B_WL<85> B_WL<84> B_WL<83> B_WL<82> B_WL<81> B_WL<80> B_WL<79> B_WL<78> B_WL<77> B_WL<76> B_WL<75> B_WL<74> B_WL<73> B_WL<72> B_WL<71> B_WL<70> B_WL<69> B_WL<68> B_WL<67> B_WL<66> B_WL<65> B_WL<64> B_WL<63> B_WL<62> B_WL<61> B_WL<60> B_WL<59> B_WL<58> B_WL<57> B_WL<56> B_WL<55> B_WL<54> B_WL<53> B_WL<52> B_WL<51> B_WL<50> B_WL<49> B_WL<48> B_WL<47> B_WL<46> B_WL<45> B_WL<44> B_WL<43> B_WL<42> B_WL<41> B_WL<40> B_WL<39> B_WL<38> B_WL<37> B_WL<36> B_WL<35> B_WL<34> B_WL<33> B_WL<32> B_WL<31> B_WL<30> B_WL<29> B_WL<28> B_WL<27> B_WL<26> B_WL<25> B_WL<24> B_WL<23> B_WL<22> B_WL<21> B_WL<20> B_WL<19> B_WL<18> B_WL<17> B_WL<16> B_WL<15> B_WL<14> B_WL<13> B_WL<12> B_WL<11> B_WL<10> B_WL<9> B_WL<8> B_WL<7> B_WL<6> B_WL<5> B_WL<4> B_WL<3> B_WL<2> B_WL<1> B_WL<0> B_IWL<127> B_IWL<126> B_IWL<125> B_IWL<124> B_IWL<123> B_IWL<122> B_IWL<121> B_IWL<120> B_IWL<119> B_IWL<118> B_IWL<117> B_IWL<116> B_IWL<115> B_IWL<114> B_IWL<113> B_IWL<112> B_IWL<111> B_IWL<110> B_IWL<109> B_IWL<108> B_IWL<107> B_IWL<106> B_IWL<105> B_IWL<104> B_IWL<103> B_IWL<102> B_IWL<101> B_IWL<100> B_IWL<99> B_IWL<98> B_IWL<97> B_IWL<96> B_IWL<95> B_IWL<94> B_IWL<93> B_IWL<92> B_IWL<91> B_IWL<90> B_IWL<89> B_IWL<88> B_IWL<87> B_IWL<86> B_IWL<85> B_IWL<84> B_IWL<83> B_IWL<82> B_IWL<81> B_IWL<80> B_IWL<79> B_IWL<78> B_IWL<77> B_IWL<76> B_IWL<75> B_IWL<74> B_IWL<73> B_IWL<72> B_IWL<71> B_IWL<70> B_IWL<69> B_IWL<68> B_IWL<67> B_IWL<66> B_IWL<65> B_IWL<64> B_IWL<63> B_IWL<62> B_IWL<61> B_IWL<60> B_IWL<59> B_IWL<58> B_IWL<57> B_IWL<56> B_IWL<55> B_IWL<54> B_IWL<53> B_IWL<52> B_IWL<51> B_IWL<50> B_IWL<49> B_IWL<48> B_IWL<47> B_IWL<46> B_IWL<45> B_IWL<44> B_IWL<43> B_IWL<42> B_IWL<41> B_IWL<40> B_IWL<39> B_IWL<38> B_IWL<37> B_IWL<36> B_IWL<35> B_IWL<34> B_IWL<33> B_IWL<32> B_IWL<31> B_IWL<30> B_IWL<29> B_IWL<28> B_IWL<27> B_IWL<26> B_IWL<25> B_IWL<24> B_IWL<23> B_IWL<22> B_IWL<21> B_IWL<20> B_IWL<19> B_IWL<18> B_IWL<17> B_IWL<16> B_IWL<15> B_IWL<14> B_IWL<13> B_IWL<12> B_IWL<11> B_IWL<10> B_IWL<9> B_IWL<8> B_IWL<7> B_IWL<6> B_IWL<5> B_IWL<4> B_IWL<3> B_IWL<2> B_IWL<1> B_IWL<0> VDD_CORE VSS / RM_IHPSG13_512x16_c2_2P_COLUMN_pcell_0 +.ENDS + + + + +.SUBCKT RM_IHPSG13_512x16_c2_2P_DLY_pcell_2 A Z VDD VSS + XIDL<2> D<9> Z VDD VSS / RSC_IHPSG13_CDLYX1 + XIDL<1> D<8> D<9> VDD VSS / RSC_IHPSG13_CDLYX1 + XIDM<8> D<7> D<8> VDD VSS / RSC_IHPSG13_CDLYX1_DUMMY + XIDM<7> D<6> D<7> VDD VSS / RSC_IHPSG13_CDLYX1_DUMMY + XIDM<6> D<5> D<6> VDD VSS / RSC_IHPSG13_CDLYX1_DUMMY + XIDM<5> D<4> D<5> VDD VSS / RSC_IHPSG13_CDLYX1_DUMMY + XIDM<4> D<3> D<4> VDD VSS / RSC_IHPSG13_CDLYX1_DUMMY + XIDM<3> D<2> D<3> VDD VSS / RSC_IHPSG13_CDLYX1_DUMMY + XIDM<2> D<1> D<2> VDD VSS / RSC_IHPSG13_CDLYX1_DUMMY + XIDM<1> A D<1> VDD VSS / RSC_IHPSG13_CDLYX1_DUMMY +.ENDS + + +.SUBCKT RM_IHPSG13_512x16_c2_2P_DLY_pcell_3 A Z VDD VSS + XIDL<2> D<9> Z VDD VSS / RSC_IHPSG13_CDLYX1 + XIDL<1> D<8> D<9> VDD VSS / RSC_IHPSG13_CDLYX1 + XIDM<8> D<7> D<8> VDD VSS / RSC_IHPSG13_CDLYX1_DUMMY + XIDM<7> D<6> D<7> VDD VSS / RSC_IHPSG13_CDLYX1_DUMMY + XIDM<6> D<5> D<6> VDD VSS / RSC_IHPSG13_CDLYX1_DUMMY + XIDM<5> D<4> D<5> VDD VSS / RSC_IHPSG13_CDLYX1_DUMMY + XIDM<4> D<3> D<4> VDD VSS / RSC_IHPSG13_CDLYX1_DUMMY + XIDM<3> D<2> D<3> VDD VSS / RSC_IHPSG13_CDLYX1_DUMMY + XIDM<2> D<1> D<2> VDD VSS / RSC_IHPSG13_CDLYX1_DUMMY + XIDM<1> A D<1> VDD VSS / RSC_IHPSG13_CDLYX1_DUMMY +.ENDS + + + +.SUBCKT RM_IHPSG13_2P_512x16_c2_bm_bist A_ADDR<8> A_ADDR<7> A_ADDR<6> A_ADDR<5> A_ADDR<4> A_ADDR<3> A_ADDR<2> A_ADDR<1> A_ADDR<0> A_BIST_ADDR<8> A_BIST_ADDR<7> A_BIST_ADDR<6> A_BIST_ADDR<5> A_BIST_ADDR<4> A_BIST_ADDR<3> A_BIST_ADDR<2> A_BIST_ADDR<1> A_BIST_ADDR<0> A_BIST_BM<15> A_BIST_BM<14> A_BIST_BM<13> A_BIST_BM<12> A_BIST_BM<11> A_BIST_BM<10> A_BIST_BM<9> A_BIST_BM<8> A_BIST_BM<7> A_BIST_BM<6> A_BIST_BM<5> A_BIST_BM<4> A_BIST_BM<3> A_BIST_BM<2> A_BIST_BM<1> A_BIST_BM<0> A_BIST_CLK A_BIST_DIN<15> A_BIST_DIN<14> A_BIST_DIN<13> A_BIST_DIN<12> A_BIST_DIN<11> A_BIST_DIN<10> A_BIST_DIN<9> A_BIST_DIN<8> A_BIST_DIN<7> A_BIST_DIN<6> A_BIST_DIN<5> A_BIST_DIN<4> A_BIST_DIN<3> A_BIST_DIN<2> A_BIST_DIN<1> A_BIST_DIN<0> A_BIST_EN A_BIST_MEN A_BIST_REN A_BIST_WEN A_BM<15> A_BM<14> A_BM<13> A_BM<12> A_BM<11> A_BM<10> A_BM<9> A_BM<8> A_BM<7> A_BM<6> A_BM<5> A_BM<4> A_BM<3> A_BM<2> A_BM<1> A_BM<0> A_CLK A_DIN<15> A_DIN<14> A_DIN<13> A_DIN<12> A_DIN<11> A_DIN<10> A_DIN<9> A_DIN<8> A_DIN<7> A_DIN<6> A_DIN<5> A_DIN<4> A_DIN<3> A_DIN<2> A_DIN<1> A_DIN<0> A_DLY A_DOUT<15> A_DOUT<14> A_DOUT<13> A_DOUT<12> A_DOUT<11> A_DOUT<10> A_DOUT<9> A_DOUT<8> A_DOUT<7> A_DOUT<6> A_DOUT<5> A_DOUT<4> A_DOUT<3> A_DOUT<2> A_DOUT<1> A_DOUT<0> A_MEN A_REN A_WEN B_ADDR<8> B_ADDR<7> B_ADDR<6> B_ADDR<5> B_ADDR<4> B_ADDR<3> B_ADDR<2> B_ADDR<1> B_ADDR<0> B_BIST_ADDR<8> B_BIST_ADDR<7> B_BIST_ADDR<6> B_BIST_ADDR<5> B_BIST_ADDR<4> B_BIST_ADDR<3> B_BIST_ADDR<2> B_BIST_ADDR<1> B_BIST_ADDR<0> B_BIST_BM<15> B_BIST_BM<14> B_BIST_BM<13> B_BIST_BM<12> B_BIST_BM<11> B_BIST_BM<10> B_BIST_BM<9> B_BIST_BM<8> B_BIST_BM<7> B_BIST_BM<6> B_BIST_BM<5> B_BIST_BM<4> B_BIST_BM<3> B_BIST_BM<2> B_BIST_BM<1> B_BIST_BM<0> B_BIST_CLK B_BIST_DIN<15> B_BIST_DIN<14> B_BIST_DIN<13> B_BIST_DIN<12> B_BIST_DIN<11> B_BIST_DIN<10> B_BIST_DIN<9> B_BIST_DIN<8> B_BIST_DIN<7> B_BIST_DIN<6> B_BIST_DIN<5> B_BIST_DIN<4> B_BIST_DIN<3> B_BIST_DIN<2> B_BIST_DIN<1> B_BIST_DIN<0> B_BIST_EN B_BIST_MEN B_BIST_REN B_BIST_WEN B_BM<15> B_BM<14> B_BM<13> B_BM<12> B_BM<11> B_BM<10> B_BM<9> B_BM<8> B_BM<7> B_BM<6> B_BM<5> B_BM<4> B_BM<3> B_BM<2> B_BM<1> B_BM<0> B_CLK B_DIN<15> B_DIN<14> B_DIN<13> B_DIN<12> B_DIN<11> B_DIN<10> B_DIN<9> B_DIN<8> B_DIN<7> B_DIN<6> B_DIN<5> B_DIN<4> B_DIN<3> B_DIN<2> B_DIN<1> B_DIN<0> B_DLY B_DOUT<15> B_DOUT<14> B_DOUT<13> B_DOUT<12> B_DOUT<11> B_DOUT<10> B_DOUT<9> B_DOUT<8> B_DOUT<7> B_DOUT<6> B_DOUT<5> B_DOUT<4> B_DOUT<3> B_DOUT<2> B_DOUT<1> B_DOUT<0> B_MEN B_REN B_WEN VDD! VDDARRAY! VSS! + + +XRAM<1> a_blc_r<31> a_blc_r<30> a_blc_r<29> a_blc_r<28> a_blc_r<27> a_blc_r<26> a_blc_r<25> a_blc_r<24> a_blc_r<23> a_blc_r<22> a_blc_r<21> a_blc_r<20> a_blc_r<19> a_blc_r<18> a_blc_r<17> a_blc_r<16> a_blc_r<15> a_blc_r<14> a_blc_r<13> a_blc_r<12> a_blc_r<11> a_blc_r<10> a_blc_r<9> a_blc_r<8> a_blc_r<7> a_blc_r<6> a_blc_r<5> a_blc_r<4> a_blc_r<3> a_blc_r<2> a_blc_r<1> a_blc_r<0> a_blt_r<31> a_blt_r<30> a_blt_r<29> a_blt_r<28> a_blt_r<27> a_blt_r<26> a_blt_r<25> a_blt_r<24> a_blt_r<23> a_blt_r<22> a_blt_r<21> a_blt_r<20> a_blt_r<19> a_blt_r<18> a_blt_r<17> a_blt_r<16> a_blt_r<15> a_blt_r<14> a_blt_r<13> a_blt_r<12> a_blt_r<11> a_blt_r<10> a_blt_r<9> a_blt_r<8> a_blt_r<7> a_blt_r<6> a_blt_r<5> a_blt_r<4> a_blt_r<3> a_blt_r<2> a_blt_r<1> a_blt_r<0> a_wl_r<127> a_wl_r<126> a_wl_r<125> a_wl_r<124> a_wl_r<123> a_wl_r<122> a_wl_r<121> a_wl_r<120> a_wl_r<119> a_wl_r<118> a_wl_r<117> a_wl_r<116> a_wl_r<115> a_wl_r<114> a_wl_r<113> a_wl_r<112> a_wl_r<111> a_wl_r<110> a_wl_r<109> a_wl_r<108> a_wl_r<107> a_wl_r<106> a_wl_r<105> a_wl_r<104> a_wl_r<103> a_wl_r<102> a_wl_r<101> a_wl_r<100> a_wl_r<99> a_wl_r<98> a_wl_r<97> a_wl_r<96> a_wl_r<95> a_wl_r<94> a_wl_r<93> a_wl_r<92> a_wl_r<91> a_wl_r<90> a_wl_r<89> a_wl_r<88> a_wl_r<87> a_wl_r<86> a_wl_r<85> a_wl_r<84> a_wl_r<83> a_wl_r<82> a_wl_r<81> a_wl_r<80> a_wl_r<79> a_wl_r<78> a_wl_r<77> a_wl_r<76> a_wl_r<75> a_wl_r<74> a_wl_r<73> a_wl_r<72> a_wl_r<71> a_wl_r<70> a_wl_r<69> a_wl_r<68> a_wl_r<67> a_wl_r<66> a_wl_r<65> a_wl_r<64> a_wl_r<63> a_wl_r<62> a_wl_r<61> a_wl_r<60> a_wl_r<59> a_wl_r<58> a_wl_r<57> a_wl_r<56> a_wl_r<55> a_wl_r<54> a_wl_r<53> a_wl_r<52> a_wl_r<51> a_wl_r<50> a_wl_r<49> a_wl_r<48> a_wl_r<47> a_wl_r<46> a_wl_r<45> a_wl_r<44> a_wl_r<43> a_wl_r<42> a_wl_r<41> a_wl_r<40> a_wl_r<39> a_wl_r<38> a_wl_r<37> a_wl_r<36> a_wl_r<35> a_wl_r<34> a_wl_r<33> a_wl_r<32> a_wl_r<31> a_wl_r<30> a_wl_r<29> a_wl_r<28> a_wl_r<27> a_wl_r<26> a_wl_r<25> a_wl_r<24> a_wl_r<23> a_wl_r<22> a_wl_r<21> a_wl_r<20> a_wl_r<19> a_wl_r<18> a_wl_r<17> a_wl_r<16> a_wl_r<15> a_wl_r<14> a_wl_r<13> a_wl_r<12> a_wl_r<11> a_wl_r<10> a_wl_r<9> a_wl_r<8> a_wl_r<7> a_wl_r<6> a_wl_r<5> a_wl_r<4> a_wl_r<3> a_wl_r<2> a_wl_r<1> a_wl_r<0> b_blc_r<31> b_blc_r<30> b_blc_r<29> b_blc_r<28> b_blc_r<27> b_blc_r<26> b_blc_r<25> b_blc_r<24> b_blc_r<23> b_blc_r<22> b_blc_r<21> b_blc_r<20> b_blc_r<19> b_blc_r<18> b_blc_r<17> b_blc_r<16> b_blc_r<15> b_blc_r<14> b_blc_r<13> b_blc_r<12> b_blc_r<11> b_blc_r<10> b_blc_r<9> b_blc_r<8> b_blc_r<7> b_blc_r<6> b_blc_r<5> b_blc_r<4> b_blc_r<3> b_blc_r<2> b_blc_r<1> b_blc_r<0> b_blt_r<31> b_blt_r<30> b_blt_r<29> b_blt_r<28> b_blt_r<27> b_blt_r<26> b_blt_r<25> b_blt_r<24> b_blt_r<23> b_blt_r<22> b_blt_r<21> b_blt_r<20> b_blt_r<19> b_blt_r<18> b_blt_r<17> b_blt_r<16> b_blt_r<15> b_blt_r<14> b_blt_r<13> b_blt_r<12> b_blt_r<11> b_blt_r<10> b_blt_r<9> b_blt_r<8> b_blt_r<7> b_blt_r<6> b_blt_r<5> b_blt_r<4> b_blt_r<3> b_blt_r<2> b_blt_r<1> b_blt_r<0> b_wl_r<127> b_wl_r<126> b_wl_r<125> b_wl_r<124> b_wl_r<123> b_wl_r<122> b_wl_r<121> b_wl_r<120> b_wl_r<119> b_wl_r<118> b_wl_r<117> b_wl_r<116> b_wl_r<115> b_wl_r<114> b_wl_r<113> b_wl_r<112> b_wl_r<111> b_wl_r<110> b_wl_r<109> b_wl_r<108> b_wl_r<107> b_wl_r<106> b_wl_r<105> b_wl_r<104> b_wl_r<103> b_wl_r<102> b_wl_r<101> b_wl_r<100> b_wl_r<99> b_wl_r<98> b_wl_r<97> b_wl_r<96> b_wl_r<95> b_wl_r<94> b_wl_r<93> b_wl_r<92> b_wl_r<91> b_wl_r<90> b_wl_r<89> b_wl_r<88> b_wl_r<87> b_wl_r<86> b_wl_r<85> b_wl_r<84> b_wl_r<83> b_wl_r<82> b_wl_r<81> b_wl_r<80> b_wl_r<79> b_wl_r<78> b_wl_r<77> b_wl_r<76> b_wl_r<75> b_wl_r<74> b_wl_r<73> b_wl_r<72> b_wl_r<71> b_wl_r<70> b_wl_r<69> b_wl_r<68> b_wl_r<67> b_wl_r<66> b_wl_r<65> b_wl_r<64> b_wl_r<63> b_wl_r<62> b_wl_r<61> b_wl_r<60> b_wl_r<59> b_wl_r<58> b_wl_r<57> b_wl_r<56> b_wl_r<55> b_wl_r<54> b_wl_r<53> b_wl_r<52> b_wl_r<51> b_wl_r<50> b_wl_r<49> b_wl_r<48> b_wl_r<47> b_wl_r<46> b_wl_r<45> b_wl_r<44> b_wl_r<43> b_wl_r<42> b_wl_r<41> b_wl_r<40> b_wl_r<39> b_wl_r<38> b_wl_r<37> b_wl_r<36> b_wl_r<35> b_wl_r<34> b_wl_r<33> b_wl_r<32> b_wl_r<31> b_wl_r<30> b_wl_r<29> b_wl_r<28> b_wl_r<27> b_wl_r<26> b_wl_r<25> b_wl_r<24> b_wl_r<23> b_wl_r<22> b_wl_r<21> b_wl_r<20> b_wl_r<19> b_wl_r<18> b_wl_r<17> b_wl_r<16> b_wl_r<15> b_wl_r<14> b_wl_r<13> b_wl_r<12> b_wl_r<11> b_wl_r<10> b_wl_r<9> b_wl_r<8> b_wl_r<7> b_wl_r<6> b_wl_r<5> b_wl_r<4> b_wl_r<3> b_wl_r<2> b_wl_r<1> b_wl_r<0> VDDARRAY! VSS! / RM_IHPSG13_512x16_c2_2P_MATRIX_pcell_1 +XRAM<0> a_blc_l<31> a_blc_l<30> a_blc_l<29> a_blc_l<28> a_blc_l<27> a_blc_l<26> a_blc_l<25> a_blc_l<24> a_blc_l<23> a_blc_l<22> a_blc_l<21> a_blc_l<20> a_blc_l<19> a_blc_l<18> a_blc_l<17> a_blc_l<16> a_blc_l<15> a_blc_l<14> a_blc_l<13> a_blc_l<12> a_blc_l<11> a_blc_l<10> a_blc_l<9> a_blc_l<8> a_blc_l<7> a_blc_l<6> a_blc_l<5> a_blc_l<4> a_blc_l<3> a_blc_l<2> a_blc_l<1> a_blc_l<0> a_blt_l<31> a_blt_l<30> a_blt_l<29> a_blt_l<28> a_blt_l<27> a_blt_l<26> a_blt_l<25> a_blt_l<24> a_blt_l<23> a_blt_l<22> a_blt_l<21> a_blt_l<20> a_blt_l<19> a_blt_l<18> a_blt_l<17> a_blt_l<16> a_blt_l<15> a_blt_l<14> a_blt_l<13> a_blt_l<12> a_blt_l<11> a_blt_l<10> a_blt_l<9> a_blt_l<8> a_blt_l<7> a_blt_l<6> a_blt_l<5> a_blt_l<4> a_blt_l<3> a_blt_l<2> a_blt_l<1> a_blt_l<0> a_wl_l<127> a_wl_l<126> a_wl_l<125> a_wl_l<124> a_wl_l<123> a_wl_l<122> a_wl_l<121> a_wl_l<120> a_wl_l<119> a_wl_l<118> a_wl_l<117> a_wl_l<116> a_wl_l<115> a_wl_l<114> a_wl_l<113> a_wl_l<112> a_wl_l<111> a_wl_l<110> a_wl_l<109> a_wl_l<108> a_wl_l<107> a_wl_l<106> a_wl_l<105> a_wl_l<104> a_wl_l<103> a_wl_l<102> a_wl_l<101> a_wl_l<100> a_wl_l<99> a_wl_l<98> a_wl_l<97> a_wl_l<96> a_wl_l<95> a_wl_l<94> a_wl_l<93> a_wl_l<92> a_wl_l<91> a_wl_l<90> a_wl_l<89> a_wl_l<88> a_wl_l<87> a_wl_l<86> a_wl_l<85> a_wl_l<84> a_wl_l<83> a_wl_l<82> a_wl_l<81> a_wl_l<80> a_wl_l<79> a_wl_l<78> a_wl_l<77> a_wl_l<76> a_wl_l<75> a_wl_l<74> a_wl_l<73> a_wl_l<72> a_wl_l<71> a_wl_l<70> a_wl_l<69> a_wl_l<68> a_wl_l<67> a_wl_l<66> a_wl_l<65> a_wl_l<64> a_wl_l<63> a_wl_l<62> a_wl_l<61> a_wl_l<60> a_wl_l<59> a_wl_l<58> a_wl_l<57> a_wl_l<56> a_wl_l<55> a_wl_l<54> a_wl_l<53> a_wl_l<52> a_wl_l<51> a_wl_l<50> a_wl_l<49> a_wl_l<48> a_wl_l<47> a_wl_l<46> a_wl_l<45> a_wl_l<44> a_wl_l<43> a_wl_l<42> a_wl_l<41> a_wl_l<40> a_wl_l<39> a_wl_l<38> a_wl_l<37> a_wl_l<36> a_wl_l<35> a_wl_l<34> a_wl_l<33> a_wl_l<32> a_wl_l<31> a_wl_l<30> a_wl_l<29> a_wl_l<28> a_wl_l<27> a_wl_l<26> a_wl_l<25> a_wl_l<24> a_wl_l<23> a_wl_l<22> a_wl_l<21> a_wl_l<20> a_wl_l<19> a_wl_l<18> a_wl_l<17> a_wl_l<16> a_wl_l<15> a_wl_l<14> a_wl_l<13> a_wl_l<12> a_wl_l<11> a_wl_l<10> a_wl_l<9> a_wl_l<8> a_wl_l<7> a_wl_l<6> a_wl_l<5> a_wl_l<4> a_wl_l<3> a_wl_l<2> a_wl_l<1> a_wl_l<0> b_blc_l<31> b_blc_l<30> b_blc_l<29> b_blc_l<28> b_blc_l<27> b_blc_l<26> b_blc_l<25> b_blc_l<24> b_blc_l<23> b_blc_l<22> b_blc_l<21> b_blc_l<20> b_blc_l<19> b_blc_l<18> b_blc_l<17> b_blc_l<16> b_blc_l<15> b_blc_l<14> b_blc_l<13> b_blc_l<12> b_blc_l<11> b_blc_l<10> b_blc_l<9> b_blc_l<8> b_blc_l<7> b_blc_l<6> b_blc_l<5> b_blc_l<4> b_blc_l<3> b_blc_l<2> b_blc_l<1> b_blc_l<0> b_blt_l<31> b_blt_l<30> b_blt_l<29> b_blt_l<28> b_blt_l<27> b_blt_l<26> b_blt_l<25> b_blt_l<24> b_blt_l<23> b_blt_l<22> b_blt_l<21> b_blt_l<20> b_blt_l<19> b_blt_l<18> b_blt_l<17> b_blt_l<16> b_blt_l<15> b_blt_l<14> b_blt_l<13> b_blt_l<12> b_blt_l<11> b_blt_l<10> b_blt_l<9> b_blt_l<8> b_blt_l<7> b_blt_l<6> b_blt_l<5> b_blt_l<4> b_blt_l<3> b_blt_l<2> b_blt_l<1> b_blt_l<0> b_wl_l<127> b_wl_l<126> b_wl_l<125> b_wl_l<124> b_wl_l<123> b_wl_l<122> b_wl_l<121> b_wl_l<120> b_wl_l<119> b_wl_l<118> b_wl_l<117> b_wl_l<116> b_wl_l<115> b_wl_l<114> b_wl_l<113> b_wl_l<112> b_wl_l<111> b_wl_l<110> b_wl_l<109> b_wl_l<108> b_wl_l<107> b_wl_l<106> b_wl_l<105> b_wl_l<104> b_wl_l<103> b_wl_l<102> b_wl_l<101> b_wl_l<100> b_wl_l<99> b_wl_l<98> b_wl_l<97> b_wl_l<96> b_wl_l<95> b_wl_l<94> b_wl_l<93> b_wl_l<92> b_wl_l<91> b_wl_l<90> b_wl_l<89> b_wl_l<88> b_wl_l<87> b_wl_l<86> b_wl_l<85> b_wl_l<84> b_wl_l<83> b_wl_l<82> b_wl_l<81> b_wl_l<80> b_wl_l<79> b_wl_l<78> b_wl_l<77> b_wl_l<76> b_wl_l<75> b_wl_l<74> b_wl_l<73> b_wl_l<72> b_wl_l<71> b_wl_l<70> b_wl_l<69> b_wl_l<68> b_wl_l<67> b_wl_l<66> b_wl_l<65> b_wl_l<64> b_wl_l<63> b_wl_l<62> b_wl_l<61> b_wl_l<60> b_wl_l<59> b_wl_l<58> b_wl_l<57> b_wl_l<56> b_wl_l<55> b_wl_l<54> b_wl_l<53> b_wl_l<52> b_wl_l<51> b_wl_l<50> b_wl_l<49> b_wl_l<48> b_wl_l<47> b_wl_l<46> b_wl_l<45> b_wl_l<44> b_wl_l<43> b_wl_l<42> b_wl_l<41> b_wl_l<40> b_wl_l<39> b_wl_l<38> b_wl_l<37> b_wl_l<36> b_wl_l<35> b_wl_l<34> b_wl_l<33> b_wl_l<32> b_wl_l<31> b_wl_l<30> b_wl_l<29> b_wl_l<28> b_wl_l<27> b_wl_l<26> b_wl_l<25> b_wl_l<24> b_wl_l<23> b_wl_l<22> b_wl_l<21> b_wl_l<20> b_wl_l<19> b_wl_l<18> b_wl_l<17> b_wl_l<16> b_wl_l<15> b_wl_l<14> b_wl_l<13> b_wl_l<12> b_wl_l<11> b_wl_l<10> b_wl_l<9> b_wl_l<8> b_wl_l<7> b_wl_l<6> b_wl_l<5> b_wl_l<4> b_wl_l<3> b_wl_l<2> b_wl_l<1> b_wl_l<0> VDDARRAY! VSS! / RM_IHPSG13_512x16_c2_2P_MATRIX_pcell_1 + + +XB_COLDRV<1> b_addr_col<1> b_addr_col<0> b_addr_col_r<1> b_addr_col_r<0> b_addr_dec<7> b_addr_dec<6> b_addr_dec<5> b_addr_dec<4> b_addr_dec<3> b_addr_dec<2> b_addr_dec<1> b_addr_dec<0> b_addr_dec_r<7> b_addr_dec_r<6> b_addr_dec_r<5> b_addr_dec_r<4> b_addr_dec_r<3> b_addr_dec_r<2> b_addr_dec_r<1> b_addr_dec_r<0> b_dclk b_dclk_p_r<0> b_rclk b_rclk_p_r<0> b_wclk b_wclk_p_r<0> VDD! VSS! / RM_IHPSG13_512x16_c2_2P_COLDRV13X4 +XB_COLDRV<0> b_addr_col<1> b_addr_col<0> b_addr_col_l<1> b_addr_col_l<0> b_addr_dec<7> b_addr_dec<6> b_addr_dec<5> b_addr_dec<4> b_addr_dec<3> b_addr_dec<2> b_addr_dec<1> b_addr_dec<0> b_addr_dec_l<7> b_addr_dec_l<6> b_addr_dec_l<5> b_addr_dec_l<4> b_addr_dec_l<3> b_addr_dec_l<2> b_addr_dec_l<1> b_addr_dec_l<0> b_dclk b_dclk_p_l<0> b_rclk b_rclk_p_l<0> b_wclk b_wclk_p_l<0> VDD! VSS! / RM_IHPSG13_512x16_c2_2P_COLDRV13X4 +XA_COLDRV<1> a_addr_col<1> a_addr_col<0> a_addr_col_r<1> a_addr_col_r<0> a_addr_dec<7> a_addr_dec<6> a_addr_dec<5> a_addr_dec<4> a_addr_dec<3> a_addr_dec<2> a_addr_dec<1> a_addr_dec<0> a_addr_dec_r<7> a_addr_dec_r<6> a_addr_dec_r<5> a_addr_dec_r<4> a_addr_dec_r<3> a_addr_dec_r<2> a_addr_dec_r<1> a_addr_dec_r<0> a_dclk a_dclk_p_r<0> a_rclk a_rclk_p_r<0> a_wclk a_wclk_p_r<0> VDD! VSS! / RM_IHPSG13_512x16_c2_2P_COLDRV13X4 +XA_COLDRV<0> a_addr_col<1> a_addr_col<0> a_addr_col_l<1> a_addr_col_l<0> a_addr_dec<7> a_addr_dec<6> a_addr_dec<5> a_addr_dec<4> a_addr_dec<3> a_addr_dec<2> a_addr_dec<1> a_addr_dec<0> a_addr_dec_l<7> a_addr_dec_l<6> a_addr_dec_l<5> a_addr_dec_l<4> a_addr_dec_l<3> a_addr_dec_l<2> a_addr_dec_l<1> a_addr_dec_l<0> a_dclk a_dclk_p_l<0> a_rclk a_rclk_p_l<0> a_wclk a_wclk_p_l<0> VDD! VSS! / RM_IHPSG13_512x16_c2_2P_COLDRV13X4 + + +XB_WLDRV<15> b_wi<127> b_wi<126> b_wi<125> b_wi<124> b_wi<123> b_wi<122> b_wi<121> b_wi<120> b_wi<119> b_wi<118> b_wi<117> b_wi<116> b_wi<115> b_wi<114> b_wi<113> b_wi<112> b_wl_r<127> b_wl_r<126> b_wl_r<125> b_wl_r<124> b_wl_r<123> b_wl_r<122> b_wl_r<121> b_wl_r<120> b_wl_r<119> b_wl_r<118> b_wl_r<117> b_wl_r<116> b_wl_r<115> b_wl_r<114> b_wl_r<113> b_wl_r<112> VDD! VSS! / RM_IHPSG13_512x16_c2_2P_WLDRV16X4 +XB_WLDRV<14> b_wi<111> b_wi<110> b_wi<109> b_wi<108> b_wi<107> b_wi<106> b_wi<105> b_wi<104> b_wi<103> b_wi<102> b_wi<101> b_wi<100> b_wi<99> b_wi<98> b_wi<97> b_wi<96> b_wl_r<111> b_wl_r<110> b_wl_r<109> b_wl_r<108> b_wl_r<107> b_wl_r<106> b_wl_r<105> b_wl_r<104> b_wl_r<103> b_wl_r<102> b_wl_r<101> b_wl_r<100> b_wl_r<99> b_wl_r<98> b_wl_r<97> b_wl_r<96> VDD! VSS! / RM_IHPSG13_512x16_c2_2P_WLDRV16X4 +XB_WLDRV<13> b_wi<95> b_wi<94> b_wi<93> b_wi<92> b_wi<91> b_wi<90> b_wi<89> b_wi<88> b_wi<87> b_wi<86> b_wi<85> b_wi<84> b_wi<83> b_wi<82> b_wi<81> b_wi<80> b_wl_r<95> b_wl_r<94> b_wl_r<93> b_wl_r<92> b_wl_r<91> b_wl_r<90> b_wl_r<89> b_wl_r<88> b_wl_r<87> b_wl_r<86> b_wl_r<85> b_wl_r<84> b_wl_r<83> b_wl_r<82> b_wl_r<81> b_wl_r<80> VDD! VSS! / RM_IHPSG13_512x16_c2_2P_WLDRV16X4 +XB_WLDRV<12> b_wi<79> b_wi<78> b_wi<77> b_wi<76> b_wi<75> b_wi<74> b_wi<73> b_wi<72> b_wi<71> b_wi<70> b_wi<69> b_wi<68> b_wi<67> b_wi<66> b_wi<65> b_wi<64> b_wl_r<79> b_wl_r<78> b_wl_r<77> b_wl_r<76> b_wl_r<75> b_wl_r<74> b_wl_r<73> b_wl_r<72> b_wl_r<71> b_wl_r<70> b_wl_r<69> b_wl_r<68> b_wl_r<67> b_wl_r<66> b_wl_r<65> b_wl_r<64> VDD! VSS! / RM_IHPSG13_512x16_c2_2P_WLDRV16X4 +XB_WLDRV<11> b_wi<63> b_wi<62> b_wi<61> b_wi<60> b_wi<59> b_wi<58> b_wi<57> b_wi<56> b_wi<55> b_wi<54> b_wi<53> b_wi<52> b_wi<51> b_wi<50> b_wi<49> b_wi<48> b_wl_r<63> b_wl_r<62> b_wl_r<61> b_wl_r<60> b_wl_r<59> b_wl_r<58> b_wl_r<57> b_wl_r<56> b_wl_r<55> b_wl_r<54> b_wl_r<53> b_wl_r<52> b_wl_r<51> b_wl_r<50> b_wl_r<49> b_wl_r<48> VDD! VSS! / RM_IHPSG13_512x16_c2_2P_WLDRV16X4 +XB_WLDRV<10> b_wi<47> b_wi<46> b_wi<45> b_wi<44> b_wi<43> b_wi<42> b_wi<41> b_wi<40> b_wi<39> b_wi<38> b_wi<37> b_wi<36> b_wi<35> b_wi<34> b_wi<33> b_wi<32> b_wl_r<47> b_wl_r<46> b_wl_r<45> b_wl_r<44> b_wl_r<43> b_wl_r<42> b_wl_r<41> b_wl_r<40> b_wl_r<39> b_wl_r<38> b_wl_r<37> b_wl_r<36> b_wl_r<35> b_wl_r<34> b_wl_r<33> b_wl_r<32> VDD! VSS! / RM_IHPSG13_512x16_c2_2P_WLDRV16X4 +XB_WLDRV<9> b_wi<31> b_wi<30> b_wi<29> b_wi<28> b_wi<27> b_wi<26> b_wi<25> b_wi<24> b_wi<23> b_wi<22> b_wi<21> b_wi<20> b_wi<19> b_wi<18> b_wi<17> b_wi<16> b_wl_r<31> b_wl_r<30> b_wl_r<29> b_wl_r<28> b_wl_r<27> b_wl_r<26> b_wl_r<25> b_wl_r<24> b_wl_r<23> b_wl_r<22> b_wl_r<21> b_wl_r<20> b_wl_r<19> b_wl_r<18> b_wl_r<17> b_wl_r<16> VDD! VSS! / RM_IHPSG13_512x16_c2_2P_WLDRV16X4 +XB_WLDRV<8> b_wi<15> b_wi<14> b_wi<13> b_wi<12> b_wi<11> b_wi<10> b_wi<9> b_wi<8> b_wi<7> b_wi<6> b_wi<5> b_wi<4> b_wi<3> b_wi<2> b_wi<1> b_wi<0> b_wl_r<15> b_wl_r<14> b_wl_r<13> b_wl_r<12> b_wl_r<11> b_wl_r<10> b_wl_r<9> b_wl_r<8> b_wl_r<7> b_wl_r<6> b_wl_r<5> b_wl_r<4> b_wl_r<3> b_wl_r<2> b_wl_r<1> b_wl_r<0> VDD! VSS! / RM_IHPSG13_512x16_c2_2P_WLDRV16X4 +XB_WLDRV<7> b_wi<127> b_wi<126> b_wi<125> b_wi<124> b_wi<123> b_wi<122> b_wi<121> b_wi<120> b_wi<119> b_wi<118> b_wi<117> b_wi<116> b_wi<115> b_wi<114> b_wi<113> b_wi<112> b_wl_l<127> b_wl_l<126> b_wl_l<125> b_wl_l<124> b_wl_l<123> b_wl_l<122> b_wl_l<121> b_wl_l<120> b_wl_l<119> b_wl_l<118> b_wl_l<117> b_wl_l<116> b_wl_l<115> b_wl_l<114> b_wl_l<113> b_wl_l<112> VDD! VSS! / RM_IHPSG13_512x16_c2_2P_WLDRV16X4 +XB_WLDRV<6> b_wi<111> b_wi<110> b_wi<109> b_wi<108> b_wi<107> b_wi<106> b_wi<105> b_wi<104> b_wi<103> b_wi<102> b_wi<101> b_wi<100> b_wi<99> b_wi<98> b_wi<97> b_wi<96> b_wl_l<111> b_wl_l<110> b_wl_l<109> b_wl_l<108> b_wl_l<107> b_wl_l<106> b_wl_l<105> b_wl_l<104> b_wl_l<103> b_wl_l<102> b_wl_l<101> b_wl_l<100> b_wl_l<99> b_wl_l<98> b_wl_l<97> b_wl_l<96> VDD! VSS! / RM_IHPSG13_512x16_c2_2P_WLDRV16X4 +XB_WLDRV<5> b_wi<95> b_wi<94> b_wi<93> b_wi<92> b_wi<91> b_wi<90> b_wi<89> b_wi<88> b_wi<87> b_wi<86> b_wi<85> b_wi<84> b_wi<83> b_wi<82> b_wi<81> b_wi<80> b_wl_l<95> b_wl_l<94> b_wl_l<93> b_wl_l<92> b_wl_l<91> b_wl_l<90> b_wl_l<89> b_wl_l<88> b_wl_l<87> b_wl_l<86> b_wl_l<85> b_wl_l<84> b_wl_l<83> b_wl_l<82> b_wl_l<81> b_wl_l<80> VDD! VSS! / RM_IHPSG13_512x16_c2_2P_WLDRV16X4 +XB_WLDRV<4> b_wi<79> b_wi<78> b_wi<77> b_wi<76> b_wi<75> b_wi<74> b_wi<73> b_wi<72> b_wi<71> b_wi<70> b_wi<69> b_wi<68> b_wi<67> b_wi<66> b_wi<65> b_wi<64> b_wl_l<79> b_wl_l<78> b_wl_l<77> b_wl_l<76> b_wl_l<75> b_wl_l<74> b_wl_l<73> b_wl_l<72> b_wl_l<71> b_wl_l<70> b_wl_l<69> b_wl_l<68> b_wl_l<67> b_wl_l<66> b_wl_l<65> b_wl_l<64> VDD! VSS! / RM_IHPSG13_512x16_c2_2P_WLDRV16X4 +XB_WLDRV<3> b_wi<63> b_wi<62> b_wi<61> b_wi<60> b_wi<59> b_wi<58> b_wi<57> b_wi<56> b_wi<55> b_wi<54> b_wi<53> b_wi<52> b_wi<51> b_wi<50> b_wi<49> b_wi<48> b_wl_l<63> b_wl_l<62> b_wl_l<61> b_wl_l<60> b_wl_l<59> b_wl_l<58> b_wl_l<57> b_wl_l<56> b_wl_l<55> b_wl_l<54> b_wl_l<53> b_wl_l<52> b_wl_l<51> b_wl_l<50> b_wl_l<49> b_wl_l<48> VDD! VSS! / RM_IHPSG13_512x16_c2_2P_WLDRV16X4 +XB_WLDRV<2> b_wi<47> b_wi<46> b_wi<45> b_wi<44> b_wi<43> b_wi<42> b_wi<41> b_wi<40> b_wi<39> b_wi<38> b_wi<37> b_wi<36> b_wi<35> b_wi<34> b_wi<33> b_wi<32> b_wl_l<47> b_wl_l<46> b_wl_l<45> b_wl_l<44> b_wl_l<43> b_wl_l<42> b_wl_l<41> b_wl_l<40> b_wl_l<39> b_wl_l<38> b_wl_l<37> b_wl_l<36> b_wl_l<35> b_wl_l<34> b_wl_l<33> b_wl_l<32> VDD! VSS! / RM_IHPSG13_512x16_c2_2P_WLDRV16X4 +XB_WLDRV<1> b_wi<31> b_wi<30> b_wi<29> b_wi<28> b_wi<27> b_wi<26> b_wi<25> b_wi<24> b_wi<23> b_wi<22> b_wi<21> b_wi<20> b_wi<19> b_wi<18> b_wi<17> b_wi<16> b_wl_l<31> b_wl_l<30> b_wl_l<29> b_wl_l<28> b_wl_l<27> b_wl_l<26> b_wl_l<25> b_wl_l<24> b_wl_l<23> b_wl_l<22> b_wl_l<21> b_wl_l<20> b_wl_l<19> b_wl_l<18> b_wl_l<17> b_wl_l<16> VDD! VSS! / RM_IHPSG13_512x16_c2_2P_WLDRV16X4 +XB_WLDRV<0> b_wi<15> b_wi<14> b_wi<13> b_wi<12> b_wi<11> b_wi<10> b_wi<9> b_wi<8> b_wi<7> b_wi<6> b_wi<5> b_wi<4> b_wi<3> b_wi<2> b_wi<1> b_wi<0> b_wl_l<15> b_wl_l<14> b_wl_l<13> b_wl_l<12> b_wl_l<11> b_wl_l<10> b_wl_l<9> b_wl_l<8> b_wl_l<7> b_wl_l<6> b_wl_l<5> b_wl_l<4> b_wl_l<3> b_wl_l<2> b_wl_l<1> b_wl_l<0> VDD! VSS! / RM_IHPSG13_512x16_c2_2P_WLDRV16X4 +XA_WLDRV<15> a_wi<127> a_wi<126> a_wi<125> a_wi<124> a_wi<123> a_wi<122> a_wi<121> a_wi<120> a_wi<119> a_wi<118> a_wi<117> a_wi<116> a_wi<115> a_wi<114> a_wi<113> a_wi<112> a_wl_r<127> a_wl_r<126> a_wl_r<125> a_wl_r<124> a_wl_r<123> a_wl_r<122> a_wl_r<121> a_wl_r<120> a_wl_r<119> a_wl_r<118> a_wl_r<117> a_wl_r<116> a_wl_r<115> a_wl_r<114> a_wl_r<113> a_wl_r<112> VDD! VSS! / RM_IHPSG13_512x16_c2_2P_WLDRV16X4 +XA_WLDRV<14> a_wi<111> a_wi<110> a_wi<109> a_wi<108> a_wi<107> a_wi<106> a_wi<105> a_wi<104> a_wi<103> a_wi<102> a_wi<101> a_wi<100> a_wi<99> a_wi<98> a_wi<97> a_wi<96> a_wl_r<111> a_wl_r<110> a_wl_r<109> a_wl_r<108> a_wl_r<107> a_wl_r<106> a_wl_r<105> a_wl_r<104> a_wl_r<103> a_wl_r<102> a_wl_r<101> a_wl_r<100> a_wl_r<99> a_wl_r<98> a_wl_r<97> a_wl_r<96> VDD! VSS! / RM_IHPSG13_512x16_c2_2P_WLDRV16X4 +XA_WLDRV<13> a_wi<95> a_wi<94> a_wi<93> a_wi<92> a_wi<91> a_wi<90> a_wi<89> a_wi<88> a_wi<87> a_wi<86> a_wi<85> a_wi<84> a_wi<83> a_wi<82> a_wi<81> a_wi<80> a_wl_r<95> a_wl_r<94> a_wl_r<93> a_wl_r<92> a_wl_r<91> a_wl_r<90> a_wl_r<89> a_wl_r<88> a_wl_r<87> a_wl_r<86> a_wl_r<85> a_wl_r<84> a_wl_r<83> a_wl_r<82> a_wl_r<81> a_wl_r<80> VDD! VSS! / RM_IHPSG13_512x16_c2_2P_WLDRV16X4 +XA_WLDRV<12> a_wi<79> a_wi<78> a_wi<77> a_wi<76> a_wi<75> a_wi<74> a_wi<73> a_wi<72> a_wi<71> a_wi<70> a_wi<69> a_wi<68> a_wi<67> a_wi<66> a_wi<65> a_wi<64> a_wl_r<79> a_wl_r<78> a_wl_r<77> a_wl_r<76> a_wl_r<75> a_wl_r<74> a_wl_r<73> a_wl_r<72> a_wl_r<71> a_wl_r<70> a_wl_r<69> a_wl_r<68> a_wl_r<67> a_wl_r<66> a_wl_r<65> a_wl_r<64> VDD! VSS! / RM_IHPSG13_512x16_c2_2P_WLDRV16X4 +XA_WLDRV<11> a_wi<63> a_wi<62> a_wi<61> a_wi<60> a_wi<59> a_wi<58> a_wi<57> a_wi<56> a_wi<55> a_wi<54> a_wi<53> a_wi<52> a_wi<51> a_wi<50> a_wi<49> a_wi<48> a_wl_r<63> a_wl_r<62> a_wl_r<61> a_wl_r<60> a_wl_r<59> a_wl_r<58> a_wl_r<57> a_wl_r<56> a_wl_r<55> a_wl_r<54> a_wl_r<53> a_wl_r<52> a_wl_r<51> a_wl_r<50> a_wl_r<49> a_wl_r<48> VDD! VSS! / RM_IHPSG13_512x16_c2_2P_WLDRV16X4 +XA_WLDRV<10> a_wi<47> a_wi<46> a_wi<45> a_wi<44> a_wi<43> a_wi<42> a_wi<41> a_wi<40> a_wi<39> a_wi<38> a_wi<37> a_wi<36> a_wi<35> a_wi<34> a_wi<33> a_wi<32> a_wl_r<47> a_wl_r<46> a_wl_r<45> a_wl_r<44> a_wl_r<43> a_wl_r<42> a_wl_r<41> a_wl_r<40> a_wl_r<39> a_wl_r<38> a_wl_r<37> a_wl_r<36> a_wl_r<35> a_wl_r<34> a_wl_r<33> a_wl_r<32> VDD! VSS! / RM_IHPSG13_512x16_c2_2P_WLDRV16X4 +XA_WLDRV<9> a_wi<31> a_wi<30> a_wi<29> a_wi<28> a_wi<27> a_wi<26> a_wi<25> a_wi<24> a_wi<23> a_wi<22> a_wi<21> a_wi<20> a_wi<19> a_wi<18> a_wi<17> a_wi<16> a_wl_r<31> a_wl_r<30> a_wl_r<29> a_wl_r<28> a_wl_r<27> a_wl_r<26> a_wl_r<25> a_wl_r<24> a_wl_r<23> a_wl_r<22> a_wl_r<21> a_wl_r<20> a_wl_r<19> a_wl_r<18> a_wl_r<17> a_wl_r<16> VDD! VSS! / RM_IHPSG13_512x16_c2_2P_WLDRV16X4 +XA_WLDRV<8> a_wi<15> a_wi<14> a_wi<13> a_wi<12> a_wi<11> a_wi<10> a_wi<9> a_wi<8> a_wi<7> a_wi<6> a_wi<5> a_wi<4> a_wi<3> a_wi<2> a_wi<1> a_wi<0> a_wl_r<15> a_wl_r<14> a_wl_r<13> a_wl_r<12> a_wl_r<11> a_wl_r<10> a_wl_r<9> a_wl_r<8> a_wl_r<7> a_wl_r<6> a_wl_r<5> a_wl_r<4> a_wl_r<3> a_wl_r<2> a_wl_r<1> a_wl_r<0> VDD! VSS! / RM_IHPSG13_512x16_c2_2P_WLDRV16X4 +XA_WLDRV<7> a_wi<127> a_wi<126> a_wi<125> a_wi<124> a_wi<123> a_wi<122> a_wi<121> a_wi<120> a_wi<119> a_wi<118> a_wi<117> a_wi<116> a_wi<115> a_wi<114> a_wi<113> a_wi<112> a_wl_l<127> a_wl_l<126> a_wl_l<125> a_wl_l<124> a_wl_l<123> a_wl_l<122> a_wl_l<121> a_wl_l<120> a_wl_l<119> a_wl_l<118> a_wl_l<117> a_wl_l<116> a_wl_l<115> a_wl_l<114> a_wl_l<113> a_wl_l<112> VDD! VSS! / RM_IHPSG13_512x16_c2_2P_WLDRV16X4 +XA_WLDRV<6> a_wi<111> a_wi<110> a_wi<109> a_wi<108> a_wi<107> a_wi<106> a_wi<105> a_wi<104> a_wi<103> a_wi<102> a_wi<101> a_wi<100> a_wi<99> a_wi<98> a_wi<97> a_wi<96> a_wl_l<111> a_wl_l<110> a_wl_l<109> a_wl_l<108> a_wl_l<107> a_wl_l<106> a_wl_l<105> a_wl_l<104> a_wl_l<103> a_wl_l<102> a_wl_l<101> a_wl_l<100> a_wl_l<99> a_wl_l<98> a_wl_l<97> a_wl_l<96> VDD! VSS! / RM_IHPSG13_512x16_c2_2P_WLDRV16X4 +XA_WLDRV<5> a_wi<95> a_wi<94> a_wi<93> a_wi<92> a_wi<91> a_wi<90> a_wi<89> a_wi<88> a_wi<87> a_wi<86> a_wi<85> a_wi<84> a_wi<83> a_wi<82> a_wi<81> a_wi<80> a_wl_l<95> a_wl_l<94> a_wl_l<93> a_wl_l<92> a_wl_l<91> a_wl_l<90> a_wl_l<89> a_wl_l<88> a_wl_l<87> a_wl_l<86> a_wl_l<85> a_wl_l<84> a_wl_l<83> a_wl_l<82> a_wl_l<81> a_wl_l<80> VDD! VSS! / RM_IHPSG13_512x16_c2_2P_WLDRV16X4 +XA_WLDRV<4> a_wi<79> a_wi<78> a_wi<77> a_wi<76> a_wi<75> a_wi<74> a_wi<73> a_wi<72> a_wi<71> a_wi<70> a_wi<69> a_wi<68> a_wi<67> a_wi<66> a_wi<65> a_wi<64> a_wl_l<79> a_wl_l<78> a_wl_l<77> a_wl_l<76> a_wl_l<75> a_wl_l<74> a_wl_l<73> a_wl_l<72> a_wl_l<71> a_wl_l<70> a_wl_l<69> a_wl_l<68> a_wl_l<67> a_wl_l<66> a_wl_l<65> a_wl_l<64> VDD! VSS! / RM_IHPSG13_512x16_c2_2P_WLDRV16X4 +XA_WLDRV<3> a_wi<63> a_wi<62> a_wi<61> a_wi<60> a_wi<59> a_wi<58> a_wi<57> a_wi<56> a_wi<55> a_wi<54> a_wi<53> a_wi<52> a_wi<51> a_wi<50> a_wi<49> a_wi<48> a_wl_l<63> a_wl_l<62> a_wl_l<61> a_wl_l<60> a_wl_l<59> a_wl_l<58> a_wl_l<57> a_wl_l<56> a_wl_l<55> a_wl_l<54> a_wl_l<53> a_wl_l<52> a_wl_l<51> a_wl_l<50> a_wl_l<49> a_wl_l<48> VDD! VSS! / RM_IHPSG13_512x16_c2_2P_WLDRV16X4 +XA_WLDRV<2> a_wi<47> a_wi<46> a_wi<45> a_wi<44> a_wi<43> a_wi<42> a_wi<41> a_wi<40> a_wi<39> a_wi<38> a_wi<37> a_wi<36> a_wi<35> a_wi<34> a_wi<33> a_wi<32> a_wl_l<47> a_wl_l<46> a_wl_l<45> a_wl_l<44> a_wl_l<43> a_wl_l<42> a_wl_l<41> a_wl_l<40> a_wl_l<39> a_wl_l<38> a_wl_l<37> a_wl_l<36> a_wl_l<35> a_wl_l<34> a_wl_l<33> a_wl_l<32> VDD! VSS! / RM_IHPSG13_512x16_c2_2P_WLDRV16X4 +XA_WLDRV<1> a_wi<31> a_wi<30> a_wi<29> a_wi<28> a_wi<27> a_wi<26> a_wi<25> a_wi<24> a_wi<23> a_wi<22> a_wi<21> a_wi<20> a_wi<19> a_wi<18> a_wi<17> a_wi<16> a_wl_l<31> a_wl_l<30> a_wl_l<29> a_wl_l<28> a_wl_l<27> a_wl_l<26> a_wl_l<25> a_wl_l<24> a_wl_l<23> a_wl_l<22> a_wl_l<21> a_wl_l<20> a_wl_l<19> a_wl_l<18> a_wl_l<17> a_wl_l<16> VDD! VSS! / RM_IHPSG13_512x16_c2_2P_WLDRV16X4 +XA_WLDRV<0> a_wi<15> a_wi<14> a_wi<13> a_wi<12> a_wi<11> a_wi<10> a_wi<9> a_wi<8> a_wi<7> a_wi<6> a_wi<5> a_wi<4> a_wi<3> a_wi<2> a_wi<1> a_wi<0> a_wl_l<15> a_wl_l<14> a_wl_l<13> a_wl_l<12> a_wl_l<11> a_wl_l<10> a_wl_l<9> a_wl_l<8> a_wl_l<7> a_wl_l<6> a_wl_l<5> a_wl_l<4> a_wl_l<3> a_wl_l<2> a_wl_l<1> a_wl_l<0> VDD! VSS! / RM_IHPSG13_512x16_c2_2P_WLDRV16X4 + + +XB_CTRL b_aclk_n B_BIST_CLK B_BIST_MEN B_BIST_EN B_BIST_REN B_BIST_WEN b_tiel B_CLK B_MEN b_dclk b_eclk b_pulse_h b_pulse_l b_pulse b_rclk B_REN b_cs b_wclk B_WEN VDD! VSS! / RM_IHPSG13_512x16_c2_2P_CTRL +XA_CTRL a_aclk_n A_BIST_CLK A_BIST_MEN A_BIST_EN A_BIST_REN A_BIST_WEN a_tiel A_CLK A_MEN a_dclk a_eclk a_pulse_h a_pulse_l a_pulse a_rclk A_REN a_cs a_wclk A_WEN VDD! VSS! / RM_IHPSG13_512x16_c2_2P_CTRL + + +XB_ROWDEC b_addr_row<6> b_addr_row<5> b_addr_row<4> b_addr_row<3> b_addr_row<2> b_addr_row<1> b_addr_row<0> b_cs b_eclk b_wi<127> b_wi<126> b_wi<125> b_wi<124> b_wi<123> b_wi<122> b_wi<121> b_wi<120> b_wi<119> b_wi<118> b_wi<117> b_wi<116> b_wi<115> b_wi<114> b_wi<113> b_wi<112> b_wi<111> b_wi<110> b_wi<109> b_wi<108> b_wi<107> b_wi<106> b_wi<105> b_wi<104> b_wi<103> b_wi<102> b_wi<101> b_wi<100> b_wi<99> b_wi<98> b_wi<97> b_wi<96> b_wi<95> b_wi<94> b_wi<93> b_wi<92> b_wi<91> b_wi<90> b_wi<89> b_wi<88> b_wi<87> b_wi<86> b_wi<85> b_wi<84> b_wi<83> b_wi<82> b_wi<81> b_wi<80> b_wi<79> b_wi<78> b_wi<77> b_wi<76> b_wi<75> b_wi<74> b_wi<73> b_wi<72> b_wi<71> b_wi<70> b_wi<69> b_wi<68> b_wi<67> b_wi<66> b_wi<65> b_wi<64> b_wi<63> b_wi<62> b_wi<61> b_wi<60> b_wi<59> b_wi<58> b_wi<57> b_wi<56> b_wi<55> b_wi<54> b_wi<53> b_wi<52> b_wi<51> b_wi<50> b_wi<49> b_wi<48> b_wi<47> b_wi<46> b_wi<45> b_wi<44> b_wi<43> b_wi<42> b_wi<41> b_wi<40> b_wi<39> b_wi<38> b_wi<37> b_wi<36> b_wi<35> b_wi<34> b_wi<33> b_wi<32> b_wi<31> b_wi<30> b_wi<29> b_wi<28> b_wi<27> b_wi<26> b_wi<25> b_wi<24> b_wi<23> b_wi<22> b_wi<21> b_wi<20> b_wi<19> b_wi<18> b_wi<17> b_wi<16> b_wi<15> b_wi<14> b_wi<13> b_wi<12> b_wi<11> b_wi<10> b_wi<9> b_wi<8> b_wi<7> b_wi<6> b_wi<5> b_wi<4> b_wi<3> b_wi<2> b_wi<1> b_wi<0> VDD! VSS! / RM_IHPSG13_512x16_c2_2P_ROWDEC7 +XA_ROWDEC a_addr_row<6> a_addr_row<5> a_addr_row<4> a_addr_row<3> a_addr_row<2> a_addr_row<1> a_addr_row<0> a_cs a_eclk a_wi<127> a_wi<126> a_wi<125> a_wi<124> a_wi<123> a_wi<122> a_wi<121> a_wi<120> a_wi<119> a_wi<118> a_wi<117> a_wi<116> a_wi<115> a_wi<114> a_wi<113> a_wi<112> a_wi<111> a_wi<110> a_wi<109> a_wi<108> a_wi<107> a_wi<106> a_wi<105> a_wi<104> a_wi<103> a_wi<102> a_wi<101> a_wi<100> a_wi<99> a_wi<98> a_wi<97> a_wi<96> a_wi<95> a_wi<94> a_wi<93> a_wi<92> a_wi<91> a_wi<90> a_wi<89> a_wi<88> a_wi<87> a_wi<86> a_wi<85> a_wi<84> a_wi<83> a_wi<82> a_wi<81> a_wi<80> a_wi<79> a_wi<78> a_wi<77> a_wi<76> a_wi<75> a_wi<74> a_wi<73> a_wi<72> a_wi<71> a_wi<70> a_wi<69> a_wi<68> a_wi<67> a_wi<66> a_wi<65> a_wi<64> a_wi<63> a_wi<62> a_wi<61> a_wi<60> a_wi<59> a_wi<58> a_wi<57> a_wi<56> a_wi<55> a_wi<54> a_wi<53> a_wi<52> a_wi<51> a_wi<50> a_wi<49> a_wi<48> a_wi<47> a_wi<46> a_wi<45> a_wi<44> a_wi<43> a_wi<42> a_wi<41> a_wi<40> a_wi<39> a_wi<38> a_wi<37> a_wi<36> a_wi<35> a_wi<34> a_wi<33> a_wi<32> a_wi<31> a_wi<30> a_wi<29> a_wi<28> a_wi<27> a_wi<26> a_wi<25> a_wi<24> a_wi<23> a_wi<22> a_wi<21> a_wi<20> a_wi<19> a_wi<18> a_wi<17> a_wi<16> a_wi<15> a_wi<14> a_wi<13> a_wi<12> a_wi<11> a_wi<10> a_wi<9> a_wi<8> a_wi<7> a_wi<6> a_wi<5> a_wi<4> a_wi<3> a_wi<2> a_wi<1> a_wi<0> VDD! VSS! / RM_IHPSG13_512x16_c2_2P_ROWDEC7 +XB_ROWREG b_aclk_n B_ADDR<8> B_ADDR<7> B_ADDR<6> B_ADDR<5> B_ADDR<4> B_ADDR<3> B_ADDR<2> b_addr_row<6> b_addr_row<5> b_addr_row<4> b_addr_row<3> b_addr_row<2> b_addr_row<1> b_addr_row<0> B_BIST_ADDR<8> B_BIST_ADDR<7> B_BIST_ADDR<6> B_BIST_ADDR<5> B_BIST_ADDR<4> B_BIST_ADDR<3> B_BIST_ADDR<2> B_BIST_EN VDD! VSS! / RM_IHPSG13_512x16_c2_2P_ROWREG7 +XA_ROWREG a_aclk_n A_ADDR<8> A_ADDR<7> A_ADDR<6> A_ADDR<5> A_ADDR<4> A_ADDR<3> A_ADDR<2> a_addr_row<6> a_addr_row<5> a_addr_row<4> a_addr_row<3> a_addr_row<2> a_addr_row<1> a_addr_row<0> A_BIST_ADDR<8> A_BIST_ADDR<7> A_BIST_ADDR<6> A_BIST_ADDR<5> A_BIST_ADDR<4> A_BIST_ADDR<3> A_BIST_ADDR<2> A_BIST_EN VDD! VSS! / RM_IHPSG13_512x16_c2_2P_ROWREG7 +XB_COLDEC b_aclk_n B_ADDR<1> B_ADDR<0> b_addr_col<1> b_addr_col<0> b_addr_dec<7> b_addr_dec<6> b_addr_dec<5> b_addr_dec<4> b_addr_dec<3> b_addr_dec<2> b_addr_dec<1> b_addr_dec<0> B_BIST_ADDR<1> B_BIST_ADDR<0> B_BIST_EN VDD! VSS! / RM_IHPSG13_512x16_c2_2P_COLDEC2 +XA_COLDEC a_aclk_n A_ADDR<1> A_ADDR<0> a_addr_col<1> a_addr_col<0> a_addr_dec<7> a_addr_dec<6> a_addr_dec<5> a_addr_dec<4> a_addr_dec<3> a_addr_dec<2> a_addr_dec<1> a_addr_dec<0> A_BIST_ADDR<1> A_BIST_ADDR<0> A_BIST_EN VDD! VSS! / RM_IHPSG13_512x16_c2_2P_COLDEC2 + + +XB_DLYH b_pulse b_pulse_h VDD! VSS! / RM_IHPSG13_512x16_c2_2P_DLY_pcell_2 +XB_DLYL b_pulse_x b_pulse_l VDD! VSS! / RM_IHPSG13_512x16_c2_2P_DLY_pcell_3 +XA_DLYH a_pulse a_pulse_h VDD! VSS! / RM_IHPSG13_512x16_c2_2P_DLY_pcell_2 +XA_DLYL a_pulse_x a_pulse_l VDD! VSS! / RM_IHPSG13_512x16_c2_2P_DLY_pcell_3 +XB_DLYMUX b_pulse_h B_DLY b_pulse_x VDD! VSS! / RM_IHPSG13_512x16_c2_2P_DLY_MUX +XA_DLYMUX a_pulse_h A_DLY a_pulse_x VDD! VSS! / RM_IHPSG13_512x16_c2_2P_DLY_MUX + +XCOLCTRL<15> a_addr_dec_r<3> a_addr_dec_r<2> a_addr_dec_r<1> a_addr_dec_r<0> A_BIST_BM<15> A_BIST_DIN<15> A_BIST_EN a_blc_r<31> a_blc_r<30> a_blc_r<29> a_blc_r<28> a_blt_r<31> a_blt_r<30> a_blt_r<29> a_blt_r<28> A_BM<15> a_dclk_n_r<7> a_dclk_n_r<8> a_dclk_p_r<7> a_dclk_p_r<8> A_DOUT<15> A_DIN<15> a_rclk_n_r<7> a_rclk_n_r<8> a_rclk_p_r<7> a_rclk_p_r<8> a_tieh<15> a_wclk_n_r<7> a_wclk_n_r<8> a_wclk_p_r<7> a_wclk_p_r<8> b_addr_dec_r<3> b_addr_dec_r<2> b_addr_dec_r<1> b_addr_dec_r<0> B_BIST_BM<15> B_BIST_DIN<15> B_BIST_EN b_blc_r<31> b_blc_r<30> b_blc_r<29> b_blc_r<28> b_blt_r<31> b_blt_r<30> b_blt_r<29> b_blt_r<28> B_BM<15> b_dclk_n_r<7> b_dclk_n_r<8> b_dclk_p_r<7> b_dclk_p_r<8> B_DOUT<15> B_DIN<15> b_rclk_n_r<7> b_rclk_n_r<8> b_rclk_p_r<7> b_rclk_p_r<8> b_tieh<15> b_wclk_n_r<7> b_wclk_n_r<8> b_wclk_p_r<7> b_wclk_p_r<8> VDD! VSS! / RM_IHPSG13_512x16_c2_2P_COLCTRL2 +XCOLCTRL<14> a_addr_dec_r<3> a_addr_dec_r<2> a_addr_dec_r<1> a_addr_dec_r<0> A_BIST_BM<14> A_BIST_DIN<14> A_BIST_EN a_blc_r<27> a_blc_r<26> a_blc_r<25> a_blc_r<24> a_blt_r<27> a_blt_r<26> a_blt_r<25> a_blt_r<24> A_BM<14> a_dclk_n_r<6> a_dclk_n_r<7> a_dclk_p_r<6> a_dclk_p_r<7> A_DOUT<14> A_DIN<14> a_rclk_n_r<6> a_rclk_n_r<7> a_rclk_p_r<6> a_rclk_p_r<7> a_tieh<14> a_wclk_n_r<6> a_wclk_n_r<7> a_wclk_p_r<6> a_wclk_p_r<7> b_addr_dec_r<3> b_addr_dec_r<2> b_addr_dec_r<1> b_addr_dec_r<0> B_BIST_BM<14> B_BIST_DIN<14> B_BIST_EN b_blc_r<27> b_blc_r<26> b_blc_r<25> b_blc_r<24> b_blt_r<27> b_blt_r<26> b_blt_r<25> b_blt_r<24> B_BM<14> b_dclk_n_r<6> b_dclk_n_r<7> b_dclk_p_r<6> b_dclk_p_r<7> B_DOUT<14> B_DIN<14> b_rclk_n_r<6> b_rclk_n_r<7> b_rclk_p_r<6> b_rclk_p_r<7> b_tieh<14> b_wclk_n_r<6> b_wclk_n_r<7> b_wclk_p_r<6> b_wclk_p_r<7> VDD! VSS! / RM_IHPSG13_512x16_c2_2P_COLCTRL2 +XCOLCTRL<13> a_addr_dec_r<3> a_addr_dec_r<2> a_addr_dec_r<1> a_addr_dec_r<0> A_BIST_BM<13> A_BIST_DIN<13> A_BIST_EN a_blc_r<23> a_blc_r<22> a_blc_r<21> a_blc_r<20> a_blt_r<23> a_blt_r<22> a_blt_r<21> a_blt_r<20> A_BM<13> a_dclk_n_r<5> a_dclk_n_r<6> a_dclk_p_r<5> a_dclk_p_r<6> A_DOUT<13> A_DIN<13> a_rclk_n_r<5> a_rclk_n_r<6> a_rclk_p_r<5> a_rclk_p_r<6> a_tieh<13> a_wclk_n_r<5> a_wclk_n_r<6> a_wclk_p_r<5> a_wclk_p_r<6> b_addr_dec_r<3> b_addr_dec_r<2> b_addr_dec_r<1> b_addr_dec_r<0> B_BIST_BM<13> B_BIST_DIN<13> B_BIST_EN b_blc_r<23> b_blc_r<22> b_blc_r<21> b_blc_r<20> b_blt_r<23> b_blt_r<22> b_blt_r<21> b_blt_r<20> B_BM<13> b_dclk_n_r<5> b_dclk_n_r<6> b_dclk_p_r<5> b_dclk_p_r<6> B_DOUT<13> B_DIN<13> b_rclk_n_r<5> b_rclk_n_r<6> b_rclk_p_r<5> b_rclk_p_r<6> b_tieh<13> b_wclk_n_r<5> b_wclk_n_r<6> b_wclk_p_r<5> b_wclk_p_r<6> VDD! VSS! / RM_IHPSG13_512x16_c2_2P_COLCTRL2 +XCOLCTRL<12> a_addr_dec_r<3> a_addr_dec_r<2> a_addr_dec_r<1> a_addr_dec_r<0> A_BIST_BM<12> A_BIST_DIN<12> A_BIST_EN a_blc_r<19> a_blc_r<18> a_blc_r<17> a_blc_r<16> a_blt_r<19> a_blt_r<18> a_blt_r<17> a_blt_r<16> A_BM<12> a_dclk_n_r<4> a_dclk_n_r<5> a_dclk_p_r<4> a_dclk_p_r<5> A_DOUT<12> A_DIN<12> a_rclk_n_r<4> a_rclk_n_r<5> a_rclk_p_r<4> a_rclk_p_r<5> a_tieh<12> a_wclk_n_r<4> a_wclk_n_r<5> a_wclk_p_r<4> a_wclk_p_r<5> b_addr_dec_r<3> b_addr_dec_r<2> b_addr_dec_r<1> b_addr_dec_r<0> B_BIST_BM<12> B_BIST_DIN<12> B_BIST_EN b_blc_r<19> b_blc_r<18> b_blc_r<17> b_blc_r<16> b_blt_r<19> b_blt_r<18> b_blt_r<17> b_blt_r<16> B_BM<12> b_dclk_n_r<4> b_dclk_n_r<5> b_dclk_p_r<4> b_dclk_p_r<5> B_DOUT<12> B_DIN<12> b_rclk_n_r<4> b_rclk_n_r<5> b_rclk_p_r<4> b_rclk_p_r<5> b_tieh<12> b_wclk_n_r<4> b_wclk_n_r<5> b_wclk_p_r<4> b_wclk_p_r<5> VDD! VSS! / RM_IHPSG13_512x16_c2_2P_COLCTRL2 +XCOLCTRL<11> a_addr_dec_r<3> a_addr_dec_r<2> a_addr_dec_r<1> a_addr_dec_r<0> A_BIST_BM<11> A_BIST_DIN<11> A_BIST_EN a_blc_r<15> a_blc_r<14> a_blc_r<13> a_blc_r<12> a_blt_r<15> a_blt_r<14> a_blt_r<13> a_blt_r<12> A_BM<11> a_dclk_n_r<3> a_dclk_n_r<4> a_dclk_p_r<3> a_dclk_p_r<4> A_DOUT<11> A_DIN<11> a_rclk_n_r<3> a_rclk_n_r<4> a_rclk_p_r<3> a_rclk_p_r<4> a_tieh<11> a_wclk_n_r<3> a_wclk_n_r<4> a_wclk_p_r<3> a_wclk_p_r<4> b_addr_dec_r<3> b_addr_dec_r<2> b_addr_dec_r<1> b_addr_dec_r<0> B_BIST_BM<11> B_BIST_DIN<11> B_BIST_EN b_blc_r<15> b_blc_r<14> b_blc_r<13> b_blc_r<12> b_blt_r<15> b_blt_r<14> b_blt_r<13> b_blt_r<12> B_BM<11> b_dclk_n_r<3> b_dclk_n_r<4> b_dclk_p_r<3> b_dclk_p_r<4> B_DOUT<11> B_DIN<11> b_rclk_n_r<3> b_rclk_n_r<4> b_rclk_p_r<3> b_rclk_p_r<4> b_tieh<11> b_wclk_n_r<3> b_wclk_n_r<4> b_wclk_p_r<3> b_wclk_p_r<4> VDD! VSS! / RM_IHPSG13_512x16_c2_2P_COLCTRL2 +XCOLCTRL<10> a_addr_dec_r<3> a_addr_dec_r<2> a_addr_dec_r<1> a_addr_dec_r<0> A_BIST_BM<10> A_BIST_DIN<10> A_BIST_EN a_blc_r<11> a_blc_r<10> a_blc_r<9> a_blc_r<8> a_blt_r<11> a_blt_r<10> a_blt_r<9> a_blt_r<8> A_BM<10> a_dclk_n_r<2> a_dclk_n_r<3> a_dclk_p_r<2> a_dclk_p_r<3> A_DOUT<10> A_DIN<10> a_rclk_n_r<2> a_rclk_n_r<3> a_rclk_p_r<2> a_rclk_p_r<3> a_tieh<10> a_wclk_n_r<2> a_wclk_n_r<3> a_wclk_p_r<2> a_wclk_p_r<3> b_addr_dec_r<3> b_addr_dec_r<2> b_addr_dec_r<1> b_addr_dec_r<0> B_BIST_BM<10> B_BIST_DIN<10> B_BIST_EN b_blc_r<11> b_blc_r<10> b_blc_r<9> b_blc_r<8> b_blt_r<11> b_blt_r<10> b_blt_r<9> b_blt_r<8> B_BM<10> b_dclk_n_r<2> b_dclk_n_r<3> b_dclk_p_r<2> b_dclk_p_r<3> B_DOUT<10> B_DIN<10> b_rclk_n_r<2> b_rclk_n_r<3> b_rclk_p_r<2> b_rclk_p_r<3> b_tieh<10> b_wclk_n_r<2> b_wclk_n_r<3> b_wclk_p_r<2> b_wclk_p_r<3> VDD! VSS! / RM_IHPSG13_512x16_c2_2P_COLCTRL2 +XCOLCTRL<9> a_addr_dec_r<3> a_addr_dec_r<2> a_addr_dec_r<1> a_addr_dec_r<0> A_BIST_BM<9> A_BIST_DIN<9> A_BIST_EN a_blc_r<7> a_blc_r<6> a_blc_r<5> a_blc_r<4> a_blt_r<7> a_blt_r<6> a_blt_r<5> a_blt_r<4> A_BM<9> a_dclk_n_r<1> a_dclk_n_r<2> a_dclk_p_r<1> a_dclk_p_r<2> A_DOUT<9> A_DIN<9> a_rclk_n_r<1> a_rclk_n_r<2> a_rclk_p_r<1> a_rclk_p_r<2> a_tieh<9> a_wclk_n_r<1> a_wclk_n_r<2> a_wclk_p_r<1> a_wclk_p_r<2> b_addr_dec_r<3> b_addr_dec_r<2> b_addr_dec_r<1> b_addr_dec_r<0> B_BIST_BM<9> B_BIST_DIN<9> B_BIST_EN b_blc_r<7> b_blc_r<6> b_blc_r<5> b_blc_r<4> b_blt_r<7> b_blt_r<6> b_blt_r<5> b_blt_r<4> B_BM<9> b_dclk_n_r<1> b_dclk_n_r<2> b_dclk_p_r<1> b_dclk_p_r<2> B_DOUT<9> B_DIN<9> b_rclk_n_r<1> b_rclk_n_r<2> b_rclk_p_r<1> b_rclk_p_r<2> b_tieh<9> b_wclk_n_r<1> b_wclk_n_r<2> b_wclk_p_r<1> b_wclk_p_r<2> VDD! VSS! / RM_IHPSG13_512x16_c2_2P_COLCTRL2 +XCOLCTRL<8> a_addr_dec_r<3> a_addr_dec_r<2> a_addr_dec_r<1> a_addr_dec_r<0> A_BIST_BM<8> A_BIST_DIN<8> A_BIST_EN a_blc_r<3> a_blc_r<2> a_blc_r<1> a_blc_r<0> a_blt_r<3> a_blt_r<2> a_blt_r<1> a_blt_r<0> A_BM<8> a_dclk_n_r<0> a_dclk_n_r<1> a_dclk_p_r<0> a_dclk_p_r<1> A_DOUT<8> A_DIN<8> a_rclk_n_r<0> a_rclk_n_r<1> a_rclk_p_r<0> a_rclk_p_r<1> a_tieh<8> a_wclk_n_r<0> a_wclk_n_r<1> a_wclk_p_r<0> a_wclk_p_r<1> b_addr_dec_r<3> b_addr_dec_r<2> b_addr_dec_r<1> b_addr_dec_r<0> B_BIST_BM<8> B_BIST_DIN<8> B_BIST_EN b_blc_r<3> b_blc_r<2> b_blc_r<1> b_blc_r<0> b_blt_r<3> b_blt_r<2> b_blt_r<1> b_blt_r<0> B_BM<8> b_dclk_n_r<0> b_dclk_n_r<1> b_dclk_p_r<0> b_dclk_p_r<1> B_DOUT<8> B_DIN<8> b_rclk_n_r<0> b_rclk_n_r<1> b_rclk_p_r<0> b_rclk_p_r<1> b_tieh<8> b_wclk_n_r<0> b_wclk_n_r<1> b_wclk_p_r<0> b_wclk_p_r<1> VDD! VSS! / RM_IHPSG13_512x16_c2_2P_COLCTRL2 +XCOLCTRL<7> a_addr_dec_l<3> a_addr_dec_l<2> a_addr_dec_l<1> a_addr_dec_l<0> A_BIST_BM<0> A_BIST_DIN<0> A_BIST_EN a_blc_l<31> a_blc_l<30> a_blc_l<29> a_blc_l<28> a_blt_l<31> a_blt_l<30> a_blt_l<29> a_blt_l<28> A_BM<0> a_dclk_n_l<7> a_dclk_n_l<8> a_dclk_p_l<7> a_dclk_p_l<8> A_DOUT<0> A_DIN<0> a_rclk_n_l<7> a_rclk_n_l<8> a_rclk_p_l<7> a_rclk_p_l<8> a_tieh<0> a_wclk_n_l<7> a_wclk_n_l<8> a_wclk_p_l<7> a_wclk_p_l<8> b_addr_dec_l<3> b_addr_dec_l<2> b_addr_dec_l<1> b_addr_dec_l<0> B_BIST_BM<0> B_BIST_DIN<0> B_BIST_EN b_blc_l<31> b_blc_l<30> b_blc_l<29> b_blc_l<28> b_blt_l<31> b_blt_l<30> b_blt_l<29> b_blt_l<28> B_BM<0> b_dclk_n_l<7> b_dclk_n_l<8> b_dclk_p_l<7> b_dclk_p_l<8> B_DOUT<0> B_DIN<0> b_rclk_n_l<7> b_rclk_n_l<8> b_rclk_p_l<7> b_rclk_p_l<8> b_tieh<0> b_wclk_n_l<7> b_wclk_n_l<8> b_wclk_p_l<7> b_wclk_p_l<8> VDD! VSS! / RM_IHPSG13_512x16_c2_2P_COLCTRL2 +XCOLCTRL<6> a_addr_dec_l<3> a_addr_dec_l<2> a_addr_dec_l<1> a_addr_dec_l<0> A_BIST_BM<1> A_BIST_DIN<1> A_BIST_EN a_blc_l<27> a_blc_l<26> a_blc_l<25> a_blc_l<24> a_blt_l<27> a_blt_l<26> a_blt_l<25> a_blt_l<24> A_BM<1> a_dclk_n_l<6> a_dclk_n_l<7> a_dclk_p_l<6> a_dclk_p_l<7> A_DOUT<1> A_DIN<1> a_rclk_n_l<6> a_rclk_n_l<7> a_rclk_p_l<6> a_rclk_p_l<7> a_tieh<1> a_wclk_n_l<6> a_wclk_n_l<7> a_wclk_p_l<6> a_wclk_p_l<7> b_addr_dec_l<3> b_addr_dec_l<2> b_addr_dec_l<1> b_addr_dec_l<0> B_BIST_BM<1> B_BIST_DIN<1> B_BIST_EN b_blc_l<27> b_blc_l<26> b_blc_l<25> b_blc_l<24> b_blt_l<27> b_blt_l<26> b_blt_l<25> b_blt_l<24> B_BM<1> b_dclk_n_l<6> b_dclk_n_l<7> b_dclk_p_l<6> b_dclk_p_l<7> B_DOUT<1> B_DIN<1> b_rclk_n_l<6> b_rclk_n_l<7> b_rclk_p_l<6> b_rclk_p_l<7> b_tieh<1> b_wclk_n_l<6> b_wclk_n_l<7> b_wclk_p_l<6> b_wclk_p_l<7> VDD! VSS! / RM_IHPSG13_512x16_c2_2P_COLCTRL2 +XCOLCTRL<5> a_addr_dec_l<3> a_addr_dec_l<2> a_addr_dec_l<1> a_addr_dec_l<0> A_BIST_BM<2> A_BIST_DIN<2> A_BIST_EN a_blc_l<23> a_blc_l<22> a_blc_l<21> a_blc_l<20> a_blt_l<23> a_blt_l<22> a_blt_l<21> a_blt_l<20> A_BM<2> a_dclk_n_l<5> a_dclk_n_l<6> a_dclk_p_l<5> a_dclk_p_l<6> A_DOUT<2> A_DIN<2> a_rclk_n_l<5> a_rclk_n_l<6> a_rclk_p_l<5> a_rclk_p_l<6> a_tieh<2> a_wclk_n_l<5> a_wclk_n_l<6> a_wclk_p_l<5> a_wclk_p_l<6> b_addr_dec_l<3> b_addr_dec_l<2> b_addr_dec_l<1> b_addr_dec_l<0> B_BIST_BM<2> B_BIST_DIN<2> B_BIST_EN b_blc_l<23> b_blc_l<22> b_blc_l<21> b_blc_l<20> b_blt_l<23> b_blt_l<22> b_blt_l<21> b_blt_l<20> B_BM<2> b_dclk_n_l<5> b_dclk_n_l<6> b_dclk_p_l<5> b_dclk_p_l<6> B_DOUT<2> B_DIN<2> b_rclk_n_l<5> b_rclk_n_l<6> b_rclk_p_l<5> b_rclk_p_l<6> b_tieh<2> b_wclk_n_l<5> b_wclk_n_l<6> b_wclk_p_l<5> b_wclk_p_l<6> VDD! VSS! / RM_IHPSG13_512x16_c2_2P_COLCTRL2 +XCOLCTRL<4> a_addr_dec_l<3> a_addr_dec_l<2> a_addr_dec_l<1> a_addr_dec_l<0> A_BIST_BM<3> A_BIST_DIN<3> A_BIST_EN a_blc_l<19> a_blc_l<18> a_blc_l<17> a_blc_l<16> a_blt_l<19> a_blt_l<18> a_blt_l<17> a_blt_l<16> A_BM<3> a_dclk_n_l<4> a_dclk_n_l<5> a_dclk_p_l<4> a_dclk_p_l<5> A_DOUT<3> A_DIN<3> a_rclk_n_l<4> a_rclk_n_l<5> a_rclk_p_l<4> a_rclk_p_l<5> a_tieh<3> a_wclk_n_l<4> a_wclk_n_l<5> a_wclk_p_l<4> a_wclk_p_l<5> b_addr_dec_l<3> b_addr_dec_l<2> b_addr_dec_l<1> b_addr_dec_l<0> B_BIST_BM<3> B_BIST_DIN<3> B_BIST_EN b_blc_l<19> b_blc_l<18> b_blc_l<17> b_blc_l<16> b_blt_l<19> b_blt_l<18> b_blt_l<17> b_blt_l<16> B_BM<3> b_dclk_n_l<4> b_dclk_n_l<5> b_dclk_p_l<4> b_dclk_p_l<5> B_DOUT<3> B_DIN<3> b_rclk_n_l<4> b_rclk_n_l<5> b_rclk_p_l<4> b_rclk_p_l<5> b_tieh<3> b_wclk_n_l<4> b_wclk_n_l<5> b_wclk_p_l<4> b_wclk_p_l<5> VDD! VSS! / RM_IHPSG13_512x16_c2_2P_COLCTRL2 +XCOLCTRL<3> a_addr_dec_l<3> a_addr_dec_l<2> a_addr_dec_l<1> a_addr_dec_l<0> A_BIST_BM<4> A_BIST_DIN<4> A_BIST_EN a_blc_l<15> a_blc_l<14> a_blc_l<13> a_blc_l<12> a_blt_l<15> a_blt_l<14> a_blt_l<13> a_blt_l<12> A_BM<4> a_dclk_n_l<3> a_dclk_n_l<4> a_dclk_p_l<3> a_dclk_p_l<4> A_DOUT<4> A_DIN<4> a_rclk_n_l<3> a_rclk_n_l<4> a_rclk_p_l<3> a_rclk_p_l<4> a_tieh<4> a_wclk_n_l<3> a_wclk_n_l<4> a_wclk_p_l<3> a_wclk_p_l<4> b_addr_dec_l<3> b_addr_dec_l<2> b_addr_dec_l<1> b_addr_dec_l<0> B_BIST_BM<4> B_BIST_DIN<4> B_BIST_EN b_blc_l<15> b_blc_l<14> b_blc_l<13> b_blc_l<12> b_blt_l<15> b_blt_l<14> b_blt_l<13> b_blt_l<12> B_BM<4> b_dclk_n_l<3> b_dclk_n_l<4> b_dclk_p_l<3> b_dclk_p_l<4> B_DOUT<4> B_DIN<4> b_rclk_n_l<3> b_rclk_n_l<4> b_rclk_p_l<3> b_rclk_p_l<4> b_tieh<4> b_wclk_n_l<3> b_wclk_n_l<4> b_wclk_p_l<3> b_wclk_p_l<4> VDD! VSS! / RM_IHPSG13_512x16_c2_2P_COLCTRL2 +XCOLCTRL<2> a_addr_dec_l<3> a_addr_dec_l<2> a_addr_dec_l<1> a_addr_dec_l<0> A_BIST_BM<5> A_BIST_DIN<5> A_BIST_EN a_blc_l<11> a_blc_l<10> a_blc_l<9> a_blc_l<8> a_blt_l<11> a_blt_l<10> a_blt_l<9> a_blt_l<8> A_BM<5> a_dclk_n_l<2> a_dclk_n_l<3> a_dclk_p_l<2> a_dclk_p_l<3> A_DOUT<5> A_DIN<5> a_rclk_n_l<2> a_rclk_n_l<3> a_rclk_p_l<2> a_rclk_p_l<3> a_tieh<5> a_wclk_n_l<2> a_wclk_n_l<3> a_wclk_p_l<2> a_wclk_p_l<3> b_addr_dec_l<3> b_addr_dec_l<2> b_addr_dec_l<1> b_addr_dec_l<0> B_BIST_BM<5> B_BIST_DIN<5> B_BIST_EN b_blc_l<11> b_blc_l<10> b_blc_l<9> b_blc_l<8> b_blt_l<11> b_blt_l<10> b_blt_l<9> b_blt_l<8> B_BM<5> b_dclk_n_l<2> b_dclk_n_l<3> b_dclk_p_l<2> b_dclk_p_l<3> B_DOUT<5> B_DIN<5> b_rclk_n_l<2> b_rclk_n_l<3> b_rclk_p_l<2> b_rclk_p_l<3> b_tieh<5> b_wclk_n_l<2> b_wclk_n_l<3> b_wclk_p_l<2> b_wclk_p_l<3> VDD! VSS! / RM_IHPSG13_512x16_c2_2P_COLCTRL2 +XCOLCTRL<1> a_addr_dec_l<3> a_addr_dec_l<2> a_addr_dec_l<1> a_addr_dec_l<0> A_BIST_BM<6> A_BIST_DIN<6> A_BIST_EN a_blc_l<7> a_blc_l<6> a_blc_l<5> a_blc_l<4> a_blt_l<7> a_blt_l<6> a_blt_l<5> a_blt_l<4> A_BM<6> a_dclk_n_l<1> a_dclk_n_l<2> a_dclk_p_l<1> a_dclk_p_l<2> A_DOUT<6> A_DIN<6> a_rclk_n_l<1> a_rclk_n_l<2> a_rclk_p_l<1> a_rclk_p_l<2> a_tieh<6> a_wclk_n_l<1> a_wclk_n_l<2> a_wclk_p_l<1> a_wclk_p_l<2> b_addr_dec_l<3> b_addr_dec_l<2> b_addr_dec_l<1> b_addr_dec_l<0> B_BIST_BM<6> B_BIST_DIN<6> B_BIST_EN b_blc_l<7> b_blc_l<6> b_blc_l<5> b_blc_l<4> b_blt_l<7> b_blt_l<6> b_blt_l<5> b_blt_l<4> B_BM<6> b_dclk_n_l<1> b_dclk_n_l<2> b_dclk_p_l<1> b_dclk_p_l<2> B_DOUT<6> B_DIN<6> b_rclk_n_l<1> b_rclk_n_l<2> b_rclk_p_l<1> b_rclk_p_l<2> b_tieh<6> b_wclk_n_l<1> b_wclk_n_l<2> b_wclk_p_l<1> b_wclk_p_l<2> VDD! VSS! / RM_IHPSG13_512x16_c2_2P_COLCTRL2 +XCOLCTRL<0> a_addr_dec_l<3> a_addr_dec_l<2> a_addr_dec_l<1> a_addr_dec_l<0> A_BIST_BM<7> A_BIST_DIN<7> A_BIST_EN a_blc_l<3> a_blc_l<2> a_blc_l<1> a_blc_l<0> a_blt_l<3> a_blt_l<2> a_blt_l<1> a_blt_l<0> A_BM<7> a_dclk_n_l<0> a_dclk_n_l<1> a_dclk_p_l<0> a_dclk_p_l<1> A_DOUT<7> A_DIN<7> a_rclk_n_l<0> a_rclk_n_l<1> a_rclk_p_l<0> a_rclk_p_l<1> a_tieh<7> a_wclk_n_l<0> a_wclk_n_l<1> a_wclk_p_l<0> a_wclk_p_l<1> b_addr_dec_l<3> b_addr_dec_l<2> b_addr_dec_l<1> b_addr_dec_l<0> B_BIST_BM<7> B_BIST_DIN<7> B_BIST_EN b_blc_l<3> b_blc_l<2> b_blc_l<1> b_blc_l<0> b_blt_l<3> b_blt_l<2> b_blt_l<1> b_blt_l<0> B_BM<7> b_dclk_n_l<0> b_dclk_n_l<1> b_dclk_p_l<0> b_dclk_p_l<1> B_DOUT<7> B_DIN<7> b_rclk_n_l<0> b_rclk_n_l<1> b_rclk_p_l<0> b_rclk_p_l<1> b_tieh<7> b_wclk_n_l<0> b_wclk_n_l<1> b_wclk_p_l<0> b_wclk_p_l<1> VDD! VSS! / RM_IHPSG13_512x16_c2_2P_COLCTRL2 + + +XDRVFILL4<1> VDD! VSS! / RM_IHPSG13_512x16_c2_2P_COLDRV13_FILL4 +XDRVFILL4<2> VDD! VSS! / RM_IHPSG13_512x16_c2_2P_COLDRV13_FILL4 +XDRVFILL4<3> VDD! VSS! / RM_IHPSG13_512x16_c2_2P_COLDRV13_FILL4 +XDRVFILL4<4> VDD! VSS! / RM_IHPSG13_512x16_c2_2P_COLDRV13_FILL4 +XDRVFILL4<5> VDD! VSS! / RM_IHPSG13_512x16_c2_2P_COLDRV13_FILL4 +XDRVFILL4<6> VDD! VSS! / RM_IHPSG13_512x16_c2_2P_COLDRV13_FILL4 +XCOLFILL4<1> VDD! VSS! / RM_IHPSG13_512x16_c2_2P_COLDRV13_FILL4C2 +XCOLFILL4<2> VDD! VSS! / RM_IHPSG13_512x16_c2_2P_COLDRV13_FILL4C2 +XCOLFILL4<3> VDD! VSS! / RM_IHPSG13_512x16_c2_2P_COLDRV13_FILL4C2 +XCOLFILL4<4> VDD! VSS! / RM_IHPSG13_512x16_c2_2P_COLDRV13_FILL4C2 +XCOLFILL4<5> VDD! VSS! / RM_IHPSG13_512x16_c2_2P_COLDRV13_FILL4C2 +XCOLFILL4<6> VDD! VSS! / RM_IHPSG13_512x16_c2_2P_COLDRV13_FILL4C2 +XCOLFILL4<7> VDD! VSS! / RM_IHPSG13_512x16_c2_2P_COLDRV13_FILL4C2 +XCOLFILL4<8> VDD! VSS! / RM_IHPSG13_512x16_c2_2P_COLDRV13_FILL4C2 +XCOLFILL4<9> VDD! VSS! / RM_IHPSG13_512x16_c2_2P_COLDRV13_FILL4C2 +XCOLFILL4<10> VDD! VSS! / RM_IHPSG13_512x16_c2_2P_COLDRV13_FILL4C2 +XCOLFILL4<11> VDD! VSS! / RM_IHPSG13_512x16_c2_2P_COLDRV13_FILL4C2 +XCOLFILL4<12> VDD! VSS! / RM_IHPSG13_512x16_c2_2P_COLDRV13_FILL4C2 +XCOLFILL4<13> VDD! VSS! / RM_IHPSG13_512x16_c2_2P_COLDRV13_FILL4C2 +XCOLFILL4<14> VDD! VSS! / RM_IHPSG13_512x16_c2_2P_COLDRV13_FILL4C2 +XCOLFILL4<15> VDD! VSS! / RM_IHPSG13_512x16_c2_2P_COLDRV13_FILL4C2 +XCOLFILL4<16> VDD! VSS! / RM_IHPSG13_512x16_c2_2P_COLDRV13_FILL4C2 +.ENDS diff --git a/flow/platforms/ihp-sg13g2/cdl/RM_IHPSG13_2P_512x32_c2_bm_bist.cdl b/flow/platforms/ihp-sg13g2/cdl/RM_IHPSG13_2P_512x32_c2_bm_bist.cdl new file mode 100644 index 0000000000..1e3ffe2f60 --- /dev/null +++ b/flow/platforms/ihp-sg13g2/cdl/RM_IHPSG13_2P_512x32_c2_bm_bist.cdl @@ -0,0 +1,6426 @@ +* ------------------------------------------------------ +* +* Copyright 2025 IHP PDK Authors +* +* Licensed under the Apache License, Version 2.0 (the "License"); +* you may not use this file except in compliance with the License. +* You may obtain a copy of the License at +* +* https://www.apache.org/licenses/LICENSE-2.0 +* +* Unless required by applicable law or agreed to in writing, software +* distributed under the License is distributed on an "AS IS" BASIS, +* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +* See the License for the specific language governing permissions and +* limitations under the License. +* +* Generated on Wed Aug 27 13:11:34 2025 +* +* ------------------------------------------------------ + +.SUBCKT RM_IHPSG13_512x32_c2_1P_BITKIT_CORNER NW PW VDD VSS +.ENDS +.SUBCKT RM_IHPSG13_512x32_c2_1P_BITKIT_16x2_CORNER VDD_CORE VSS +XI16 VDD_CORE VSS VDD_CORE VSS / ++ RM_IHPSG13_512x32_c2_1P_BITKIT_CORNER +.ENDS +.SUBCKT RM_IHPSG13_512x32_c2_1P_BITKIT_EDGE_LR LWL NW PW VDD VSS +MN1 VSS LWL VSS VSS sg13_lv_nmos m=1 w=300.0n l=130.00n ng=1 nrd=0 nrs=0 +MN0 VSS net9 VSS VSS sg13_lv_nmos m=1 w=300.0n l=130.00n ng=1 nrd=0 nrs=0 +.ENDS +.SUBCKT RM_IHPSG13_512x32_c2_1P_BITKIT_16x2_EDGE_LR A_WL<15> A_WL<14> A_WL<13> A_WL<12> ++ A_WL<11> A_WL<10> A_WL<9> A_WL<8> A_WL<7> A_WL<6> A_WL<5> A_WL<4> A_WL<3> ++ A_WL<2> A_WL<1> A_WL<0> VDD_CORE VSS +XI0<15> A_WL<15> VDD_CORE VSS VDD_CORE VSS / ++ RM_IHPSG13_512x32_c2_1P_BITKIT_EDGE_LR +XI0<14> A_WL<14> VDD_CORE VSS VDD_CORE VSS / ++ RM_IHPSG13_512x32_c2_1P_BITKIT_EDGE_LR +XI0<13> A_WL<13> VDD_CORE VSS VDD_CORE VSS / ++ RM_IHPSG13_512x32_c2_1P_BITKIT_EDGE_LR +XI0<12> A_WL<12> VDD_CORE VSS VDD_CORE VSS / ++ RM_IHPSG13_512x32_c2_1P_BITKIT_EDGE_LR +XI0<11> A_WL<11> VDD_CORE VSS VDD_CORE VSS / ++ RM_IHPSG13_512x32_c2_1P_BITKIT_EDGE_LR +XI0<10> A_WL<10> VDD_CORE VSS VDD_CORE VSS / ++ RM_IHPSG13_512x32_c2_1P_BITKIT_EDGE_LR +XI0<9> A_WL<9> VDD_CORE VSS VDD_CORE VSS / ++ RM_IHPSG13_512x32_c2_1P_BITKIT_EDGE_LR +XI0<8> A_WL<8> VDD_CORE VSS VDD_CORE VSS / ++ RM_IHPSG13_512x32_c2_1P_BITKIT_EDGE_LR +XI0<7> A_WL<7> VDD_CORE VSS VDD_CORE VSS / ++ RM_IHPSG13_512x32_c2_1P_BITKIT_EDGE_LR +XI0<6> A_WL<6> VDD_CORE VSS VDD_CORE VSS / ++ RM_IHPSG13_512x32_c2_1P_BITKIT_EDGE_LR +XI0<5> A_WL<5> VDD_CORE VSS VDD_CORE VSS / ++ RM_IHPSG13_512x32_c2_1P_BITKIT_EDGE_LR +XI0<4> A_WL<4> VDD_CORE VSS VDD_CORE VSS / ++ RM_IHPSG13_512x32_c2_1P_BITKIT_EDGE_LR +XI0<3> A_WL<3> VDD_CORE VSS VDD_CORE VSS / ++ RM_IHPSG13_512x32_c2_1P_BITKIT_EDGE_LR +XI0<2> A_WL<2> VDD_CORE VSS VDD_CORE VSS / ++ RM_IHPSG13_512x32_c2_1P_BITKIT_EDGE_LR +XI0<1> A_WL<1> VDD_CORE VSS VDD_CORE VSS / ++ RM_IHPSG13_512x32_c2_1P_BITKIT_EDGE_LR +XI0<0> A_WL<0> VDD_CORE VSS VDD_CORE VSS / ++ RM_IHPSG13_512x32_c2_1P_BITKIT_EDGE_LR +.ENDS +.SUBCKT RM_IHPSG13_512x32_c2_1P_BITKIT_CELL BLC_BOT BLC_TOP BLT_BOT BLT_TOP LWL NW PW ++ RWL VDD VSS +MN0 NC NT VSS PW sg13_lv_nmos m=1 w=300.0n l=130.00n ng=1 nrd=0 nrs=0 +MN1 NT NC VSS PW sg13_lv_nmos m=1 w=300.0n l=130.00n ng=1 nrd=0 nrs=0 +MN3 NC RWL BLC_TOP PW sg13_lv_nmos m=1 w=300.0n l=130.00n ng=1 nrd=0 nrs=0 +MN2 BLT_BOT LWL NT PW sg13_lv_nmos m=1 w=300.0n l=130.00n ng=1 nrd=0 nrs=0 +MP1 NT NC VDD NW sg13_lv_pmos m=1 w=150.00n l=130.00n ng=1 nrd=0 nrs=0 +MP0 NC NT VDD NW sg13_lv_pmos m=1 w=150.00n l=130.00n ng=1 nrd=0 nrs=0 +R1 BLC_BOT BLC_TOP lvsres w=2.6e-07 l=6e-07 +R0 BLT_BOT BLT_TOP lvsres w=2.6e-07 l=6e-07 +R2 RWL LWL lvsres w=2.6e-07 l=6e-07 +.ENDS +.SUBCKT RM_IHPSG13_512x32_c2_1P_BITKIT_16x2_SRAM A_BLC_BOT<1> A_BLC_BOT<0> A_BLC_TOP<1> ++ A_BLC_TOP<0> A_BLT_BOT<1> A_BLT_BOT<0> A_BLT_TOP<1> A_BLT_TOP<0> A_LWL<15> ++ A_LWL<14> A_LWL<13> A_LWL<12> A_LWL<11> A_LWL<10> A_LWL<9> A_LWL<8> A_LWL<7> ++ A_LWL<6> A_LWL<5> A_LWL<4> A_LWL<3> A_LWL<2> A_LWL<1> A_LWL<0> A_RWL<15> ++ A_RWL<14> A_RWL<13> A_RWL<12> A_RWL<11> A_RWL<10> A_RWL<9> A_RWL<8> A_RWL<7> ++ A_RWL<6> A_RWL<5> A_RWL<4> A_RWL<3> A_RWL<2> A_RWL<1> A_RWL<0> VDD_CORE ++ VSS +XCELL<31> A_BLC_TOP<1> A_RBLC<15> A_BLT_TOP<1> A_RBLT<15> A_RWL<15> ++ VDD_CORE VSS A_XWL<15> VDD_CORE VSS / ++ RM_IHPSG13_512x32_c2_1P_BITKIT_CELL +XCELL<30> A_RBLC<14> A_RBLC<15> A_RBLT<14> A_RBLT<15> A_RWL<14> VDD_CORE ++ VSS A_XWL<14> VDD_CORE VSS / RM_IHPSG13_512x32_c2_1P_BITKIT_CELL +XCELL<29> A_RBLC<14> A_RBLC<13> A_RBLT<14> A_RBLT<13> A_RWL<13> VDD_CORE ++ VSS A_XWL<13> VDD_CORE VSS / RM_IHPSG13_512x32_c2_1P_BITKIT_CELL +XCELL<28> A_RBLC<12> A_RBLC<13> A_RBLT<12> A_RBLT<13> A_RWL<12> VDD_CORE ++ VSS A_XWL<12> VDD_CORE VSS / RM_IHPSG13_512x32_c2_1P_BITKIT_CELL +XCELL<27> A_RBLC<12> A_RBLC<11> A_RBLT<12> A_RBLT<11> A_RWL<11> VDD_CORE ++ VSS A_XWL<11> VDD_CORE VSS / RM_IHPSG13_512x32_c2_1P_BITKIT_CELL +XCELL<26> A_RBLC<10> A_RBLC<11> A_RBLT<10> A_RBLT<11> A_RWL<10> VDD_CORE ++ VSS A_XWL<10> VDD_CORE VSS / RM_IHPSG13_512x32_c2_1P_BITKIT_CELL +XCELL<25> A_RBLC<10> A_RBLC<9> A_RBLT<10> A_RBLT<9> A_RWL<9> VDD_CORE ++ VSS A_XWL<9> VDD_CORE VSS / RM_IHPSG13_512x32_c2_1P_BITKIT_CELL +XCELL<24> A_RBLC<8> A_RBLC<9> A_RBLT<8> A_RBLT<9> A_RWL<8> VDD_CORE ++ VSS A_XWL<8> VDD_CORE VSS / RM_IHPSG13_512x32_c2_1P_BITKIT_CELL +XCELL<23> A_RBLC<8> A_RBLC<7> A_RBLT<8> A_RBLT<7> A_RWL<7> VDD_CORE ++ VSS A_XWL<7> VDD_CORE VSS / RM_IHPSG13_512x32_c2_1P_BITKIT_CELL +XCELL<22> A_RBLC<6> A_RBLC<7> A_RBLT<6> A_RBLT<7> A_RWL<6> VDD_CORE ++ VSS A_XWL<6> VDD_CORE VSS / RM_IHPSG13_512x32_c2_1P_BITKIT_CELL +XCELL<21> A_RBLC<6> A_RBLC<5> A_RBLT<6> A_RBLT<5> A_RWL<5> VDD_CORE ++ VSS A_XWL<5> VDD_CORE VSS / RM_IHPSG13_512x32_c2_1P_BITKIT_CELL +XCELL<20> A_RBLC<4> A_RBLC<5> A_RBLT<4> A_RBLT<5> A_RWL<4> VDD_CORE ++ VSS A_XWL<4> VDD_CORE VSS / RM_IHPSG13_512x32_c2_1P_BITKIT_CELL +XCELL<19> A_RBLC<4> A_RBLC<3> A_RBLT<4> A_RBLT<3> A_RWL<3> VDD_CORE ++ VSS A_XWL<3> VDD_CORE VSS / RM_IHPSG13_512x32_c2_1P_BITKIT_CELL +XCELL<18> A_RBLC<2> A_RBLC<3> A_RBLT<2> A_RBLT<3> A_RWL<2> VDD_CORE ++ VSS A_XWL<2> VDD_CORE VSS / RM_IHPSG13_512x32_c2_1P_BITKIT_CELL +XCELL<17> A_RBLC<2> A_RBLC<1> A_RBLT<2> A_RBLT<1> A_RWL<1> VDD_CORE ++ VSS A_XWL<1> VDD_CORE VSS / RM_IHPSG13_512x32_c2_1P_BITKIT_CELL +XCELL<16> A_BLC_BOT<1> A_RBLC<1> A_BLT_BOT<1> A_RBLT<1> A_RWL<0> VDD_CORE ++ VSS A_XWL<0> VDD_CORE VSS / RM_IHPSG13_512x32_c2_1P_BITKIT_CELL +XCELL<15> A_BLC_TOP<0> A_LBLC<15> A_BLT_TOP<0> A_LBLT<15> A_LWL<15> ++ VDD_CORE VSS A_XWL<15> VDD_CORE VSS / ++ RM_IHPSG13_512x32_c2_1P_BITKIT_CELL +XCELL<14> A_LBLC<14> A_LBLC<15> A_LBLT<14> A_LBLT<15> A_LWL<14> VDD_CORE ++ VSS A_XWL<14> VDD_CORE VSS / RM_IHPSG13_512x32_c2_1P_BITKIT_CELL +XCELL<13> A_LBLC<14> A_LBLC<13> A_LBLT<14> A_LBLT<13> A_LWL<13> VDD_CORE ++ VSS A_XWL<13> VDD_CORE VSS / RM_IHPSG13_512x32_c2_1P_BITKIT_CELL +XCELL<12> A_LBLC<12> A_LBLC<13> A_LBLT<12> A_LBLT<13> A_LWL<12> VDD_CORE ++ VSS A_XWL<12> VDD_CORE VSS / RM_IHPSG13_512x32_c2_1P_BITKIT_CELL +XCELL<11> A_LBLC<12> A_LBLC<11> A_LBLT<12> A_LBLT<11> A_LWL<11> VDD_CORE ++ VSS A_XWL<11> VDD_CORE VSS / RM_IHPSG13_512x32_c2_1P_BITKIT_CELL +XCELL<10> A_LBLC<10> A_LBLC<11> A_LBLT<10> A_LBLT<11> A_LWL<10> VDD_CORE ++ VSS A_XWL<10> VDD_CORE VSS / RM_IHPSG13_512x32_c2_1P_BITKIT_CELL +XCELL<9> A_LBLC<10> A_LBLC<9> A_LBLT<10> A_LBLT<9> A_LWL<9> VDD_CORE ++ VSS A_XWL<9> VDD_CORE VSS / RM_IHPSG13_512x32_c2_1P_BITKIT_CELL +XCELL<8> A_LBLC<8> A_LBLC<9> A_LBLT<8> A_LBLT<9> A_LWL<8> VDD_CORE ++ VSS A_XWL<8> VDD_CORE VSS / RM_IHPSG13_512x32_c2_1P_BITKIT_CELL +XCELL<7> A_LBLC<8> A_LBLC<7> A_LBLT<8> A_LBLT<7> A_LWL<7> VDD_CORE ++ VSS A_XWL<7> VDD_CORE VSS / RM_IHPSG13_512x32_c2_1P_BITKIT_CELL +XCELL<6> A_LBLC<6> A_LBLC<7> A_LBLT<6> A_LBLT<7> A_LWL<6> VDD_CORE ++ VSS A_XWL<6> VDD_CORE VSS / RM_IHPSG13_512x32_c2_1P_BITKIT_CELL +XCELL<5> A_LBLC<6> A_LBLC<5> A_LBLT<6> A_LBLT<5> A_LWL<5> VDD_CORE ++ VSS A_XWL<5> VDD_CORE VSS / RM_IHPSG13_512x32_c2_1P_BITKIT_CELL +XCELL<4> A_LBLC<4> A_LBLC<5> A_LBLT<4> A_LBLT<5> A_LWL<4> VDD_CORE ++ VSS A_XWL<4> VDD_CORE VSS / RM_IHPSG13_512x32_c2_1P_BITKIT_CELL +XCELL<3> A_LBLC<4> A_LBLC<3> A_LBLT<4> A_LBLT<3> A_LWL<3> VDD_CORE ++ VSS A_XWL<3> VDD_CORE VSS / RM_IHPSG13_512x32_c2_1P_BITKIT_CELL +XCELL<2> A_LBLC<2> A_LBLC<3> A_LBLT<2> A_LBLT<3> A_LWL<2> VDD_CORE ++ VSS A_XWL<2> VDD_CORE VSS / RM_IHPSG13_512x32_c2_1P_BITKIT_CELL +XCELL<1> A_LBLC<2> A_LBLC<1> A_LBLT<2> A_LBLT<1> A_LWL<1> VDD_CORE ++ VSS A_XWL<1> VDD_CORE VSS / RM_IHPSG13_512x32_c2_1P_BITKIT_CELL +XCELL<0> A_BLC_BOT<0> A_LBLC<1> A_BLT_BOT<0> A_LBLT<1> A_LWL<0> VDD_CORE ++ VSS A_XWL<0> VDD_CORE VSS / RM_IHPSG13_512x32_c2_1P_BITKIT_CELL +.ENDS +.SUBCKT RM_IHPSG13_512x32_c2_1P_BITKIT_EDGE_TB BLC BLT NW PW VDD VSS +.ENDS +.SUBCKT RM_IHPSG13_512x32_c2_1P_BITKIT_16x2_EDGE_TB A_BLC<1> A_BLC<0> A_BLT<1> A_BLT<0> ++ VDD_CORE VSS +XEDGE<1> A_BLC<1> A_BLT<1> VDD_CORE VSS VDD_CORE VSS ++ / RM_IHPSG13_512x32_c2_1P_BITKIT_EDGE_TB +XEDGE<0> A_BLC<0> A_BLT<0> VDD_CORE VSS VDD_CORE VSS ++ / RM_IHPSG13_512x32_c2_1P_BITKIT_EDGE_TB +.ENDS + +.SUBCKT RSC_IHPSG13_CBUFX4 A Z VDD VSS +MN0 net9 A VSS VSS sg13_lv_nmos m=1 w=705.000n l=130.00n ng=1 nrd=0 ++ nrs=0 +MN1 Z net9 VSS VSS sg13_lv_nmos m=1 w=1.41u l=130.00n ng=2 nrd=0 nrs=0 +MP0 net9 A VDD VDD sg13_lv_pmos m=1 w=1.62u l=130.00n ng=1 nrd=0 nrs=0 +MP1 Z net9 VDD VDD sg13_lv_pmos m=1 w=3.24u l=130.00n ng=2 nrd=0 nrs=0 +.ENDS +.SUBCKT RM_IHPSG13_512x32_c2_1P_COLDRV13X4 ADDR_COL_I<1> ADDR_COL_I<0> ADDR_COL_O<1> ++ ADDR_COL_O<0> ADDR_DEC_I<7> ADDR_DEC_I<6> ADDR_DEC_I<5> ADDR_DEC_I<4> ++ ADDR_DEC_I<3> ADDR_DEC_I<2> ADDR_DEC_I<1> ADDR_DEC_I<0> ADDR_DEC_O<7> ++ ADDR_DEC_O<6> ADDR_DEC_O<5> ADDR_DEC_O<4> ADDR_DEC_O<3> ADDR_DEC_O<2> ++ ADDR_DEC_O<1> ADDR_DEC_O<0> DCLK_I DCLK_O RCLK_I RCLK_O WCLK_I WCLK_O ++ VDD VSS +XADDR_COL_DRV<1> ADDR_COL_I<1> ADDR_COL_O<1> VDD VSS / ++ RSC_IHPSG13_CBUFX4 +XADDR_COL_DRV<0> ADDR_COL_I<0> ADDR_COL_O<0> VDD VSS / ++ RSC_IHPSG13_CBUFX4 +XADDR_DEC_DRV<7> ADDR_DEC_I<7> ADDR_DEC_O<7> VDD VSS / ++ RSC_IHPSG13_CBUFX4 +XADDR_DEC_DRV<6> ADDR_DEC_I<6> ADDR_DEC_O<6> VDD VSS / ++ RSC_IHPSG13_CBUFX4 +XADDR_DEC_DRV<5> ADDR_DEC_I<5> ADDR_DEC_O<5> VDD VSS / ++ RSC_IHPSG13_CBUFX4 +XADDR_DEC_DRV<4> ADDR_DEC_I<4> ADDR_DEC_O<4> VDD VSS / ++ RSC_IHPSG13_CBUFX4 +XADDR_DEC_DRV<3> ADDR_DEC_I<3> ADDR_DEC_O<3> VDD VSS / ++ RSC_IHPSG13_CBUFX4 +XADDR_DEC_DRV<2> ADDR_DEC_I<2> ADDR_DEC_O<2> VDD VSS / ++ RSC_IHPSG13_CBUFX4 +XADDR_DEC_DRV<1> ADDR_DEC_I<1> ADDR_DEC_O<1> VDD VSS / ++ RSC_IHPSG13_CBUFX4 +XADDR_DEC_DRV<0> ADDR_DEC_I<0> ADDR_DEC_O<0> VDD VSS / ++ RSC_IHPSG13_CBUFX4 +XDCLK_DRV DCLK_I DCLK_O VDD VSS / RSC_IHPSG13_CBUFX4 +XRCLK_DRV RCLK_I RCLK_O VDD VSS / RSC_IHPSG13_CBUFX4 +XWCLK_DRV WCLK_I WCLK_O VDD VSS / RSC_IHPSG13_CBUFX4 +.ENDS +.SUBCKT RSC_IHPSG13_WLDRVX4 A Z VDD VSS +MN1 Z net6 VSS VSS sg13_lv_nmos m=1 w=705.000n l=130.00n ng=1 nrd=0 ++ nrs=0 +MN0 net6 A VSS VSS sg13_lv_nmos m=1 w=900.0n l=130.00n ng=1 nrd=0 nrs=0 +MP1 Z net6 VDD VDD sg13_lv_pmos m=1 w=3.24u l=130.00n ng=2 nrd=0 nrs=0 +MP0 net6 A VDD VDD sg13_lv_pmos m=1 w=900.0n l=130.00n ng=1 nrd=0 nrs=0 +.ENDS +.SUBCKT RM_IHPSG13_512x32_c2_1P_WLDRV16X4 A<15> A<14> A<13> A<12> A<11> A<10> A<9> A<8> ++ A<7> A<6> A<5> A<4> A<3> A<2> A<1> A<0> Z<15> Z<14> Z<13> Z<12> Z<11> Z<10> ++ Z<9> Z<8> Z<7> Z<6> Z<5> Z<4> Z<3> Z<2> Z<1> Z<0> VDD VSS +XBUF<15> A<15> Z<15> VDD VSS / RSC_IHPSG13_WLDRVX4 +XBUF<14> A<14> Z<14> VDD VSS / RSC_IHPSG13_WLDRVX4 +XBUF<13> A<13> Z<13> VDD VSS / RSC_IHPSG13_WLDRVX4 +XBUF<12> A<12> Z<12> VDD VSS / RSC_IHPSG13_WLDRVX4 +XBUF<11> A<11> Z<11> VDD VSS / RSC_IHPSG13_WLDRVX4 +XBUF<10> A<10> Z<10> VDD VSS / RSC_IHPSG13_WLDRVX4 +XBUF<9> A<9> Z<9> VDD VSS / RSC_IHPSG13_WLDRVX4 +XBUF<8> A<8> Z<8> VDD VSS / RSC_IHPSG13_WLDRVX4 +XBUF<7> A<7> Z<7> VDD VSS / RSC_IHPSG13_WLDRVX4 +XBUF<6> A<6> Z<6> VDD VSS / RSC_IHPSG13_WLDRVX4 +XBUF<5> A<5> Z<5> VDD VSS / RSC_IHPSG13_WLDRVX4 +XBUF<4> A<4> Z<4> VDD VSS / RSC_IHPSG13_WLDRVX4 +XBUF<3> A<3> Z<3> VDD VSS / RSC_IHPSG13_WLDRVX4 +XBUF<2> A<2> Z<2> VDD VSS / RSC_IHPSG13_WLDRVX4 +XBUF<1> A<1> Z<1> VDD VSS / RSC_IHPSG13_WLDRVX4 +XBUF<0> A<0> Z<0> VDD VSS / RSC_IHPSG13_WLDRVX4 +.ENDS +.SUBCKT RSC_IHPSG13_FILLCAP8 VDD VSS +MN0 vss_r vdd_r VSS VSS sg13_lv_nmos m=1 w=4.98u l=130.00n ng=6 nrd=0 ++ nrs=0 +MP0 vdd_r vss_r VDD VDD sg13_lv_pmos m=1 w=6.48u l=385.000n ng=4 nrd=0 ++ nrs=0 +.ENDS +.SUBCKT RSC_IHPSG13_LHPQX2 CP D Q VDD VSS +MN3 QIN CPN net14 VSS sg13_lv_nmos m=1 w=480.00n l=130.00n ng=1 nrd=0 nrs=0 +MN2 net14 net10 VSS VSS sg13_lv_nmos m=1 w=480.00n l=130.00n ng=1 ++ nrd=0 nrs=0 +MN5 net21 D VSS VSS sg13_lv_nmos m=1 w=870.00n l=130.00n ng=1 nrd=0 ++ nrs=0 +MN6 QIN CP net21 VSS sg13_lv_nmos m=1 w=870.00n l=130.00n ng=1 nrd=0 nrs=0 +MN1 net10 QIN VSS VSS sg13_lv_nmos m=1 w=480.00n l=130.00n ng=1 nrd=0 ++ nrs=0 +MN0 CPN CP VSS VSS sg13_lv_nmos m=1 w=480.00n l=130.00n ng=1 nrd=0 ++ nrs=0 +MN4 Q QIN VSS VSS sg13_lv_nmos m=1 w=980.00n l=130.00n ng=1 nrd=0 nrs=0 +MP2 QIN CP net16 VDD sg13_lv_pmos m=1 w=480.00n l=130.00n ng=1 nrd=0 nrs=0 +MP0 CPN CP VDD VDD sg13_lv_pmos m=1 w=480.00n l=130.00n ng=1 nrd=0 ++ nrs=0 +MP4 Q QIN VDD VDD sg13_lv_pmos m=1 w=1.62u l=130.00n ng=1 nrd=0 nrs=0 +MP3 net10 QIN VDD VDD sg13_lv_pmos m=1 w=480.00n l=130.00n ng=1 nrd=0 ++ nrs=0 +MP1 net16 net10 VDD VDD sg13_lv_pmos m=1 w=480.00n l=130.00n ng=1 ++ nrd=0 nrs=0 +MP6 QIN CPN net20 VDD sg13_lv_pmos m=1 w=975.000n l=130.00n ng=1 nrd=0 ++ nrs=0 +MP5 net20 D VDD VDD sg13_lv_pmos m=1 w=975.000n l=130.00n ng=1 nrd=0 ++ nrs=0 +.ENDS +.SUBCKT RSC_IHPSG13_NAND2X2 A B Z VDD VSS +MP1 Z B VDD VDD sg13_lv_pmos m=1 w=1.62u l=130.00n ng=1 nrd=0 nrs=0 +MP0 Z A VDD VDD sg13_lv_pmos m=1 w=1.62u l=130.00n ng=1 nrd=0 nrs=0 +MN0 Z B net7 VSS sg13_lv_nmos m=1 w=980.00n l=130.00n ng=1 nrd=0 nrs=0 +MN1 net7 A VSS VSS sg13_lv_nmos m=1 w=980.00n l=130.00n ng=1 nrd=0 ++ nrs=0 +.ENDS +.SUBCKT RSC_IHPSG13_CINVX4 A Z VDD VSS +MN0 Z A VSS VSS sg13_lv_nmos m=1 w=1.41u l=130.00n ng=2 nrd=0 nrs=0 +MP0 Z A VDD VDD sg13_lv_pmos m=1 w=3.24u l=130.00n ng=2 nrd=0 nrs=0 +.ENDS +.SUBCKT RSC_IHPSG13_CINVX2 A Z VDD VSS +MN0 Z A VSS VSS sg13_lv_nmos m=1 w=705.000n l=130.00n ng=1 nrd=0 nrs=0 +MP0 Z A VDD VDD sg13_lv_pmos m=1 w=1.62u l=130.00n ng=1 nrd=0 nrs=0 +.ENDS +.SUBCKT RSC_IHPSG13_INVX2 A Z VDD VSS +MN0 Z A VSS VSS sg13_lv_nmos m=1 w=980.00n l=130.00n ng=1 nrd=0 nrs=0 +MP0 Z A VDD VDD sg13_lv_pmos m=1 w=1.62u l=130.00n ng=1 nrd=0 nrs=0 +.ENDS +.SUBCKT RSC_IHPSG13_NAND3X2 A B C Z VDD VSS +MP2 Z A VDD VDD sg13_lv_pmos m=1 w=1.62u l=130.00n ng=1 nrd=0 nrs=0 +MP1 Z B VDD VDD sg13_lv_pmos m=1 w=1.62u l=130.00n ng=1 nrd=0 nrs=0 +MP0 Z C VDD VDD sg13_lv_pmos m=1 w=1.62u l=130.00n ng=1 nrd=0 nrs=0 +MN1 net12 B net16 VSS sg13_lv_nmos m=1 w=980.00n l=130.00n ng=1 nrd=0 nrs=0 +MN0 Z C net12 VSS sg13_lv_nmos m=1 w=980.00n l=130.00n ng=1 nrd=0 nrs=0 +MN2 net16 A VSS VSS sg13_lv_nmos m=1 w=980.00n l=130.00n ng=1 nrd=0 ++ nrs=0 +.ENDS +.SUBCKT RSC_IHPSG13_NOR3X2 A B C Z VDD VSS +MP0 net13 A VDD VDD sg13_lv_pmos m=1 w=1.62u l=130.00n ng=1 nrd=0 nrs=0 +MP2 Z C net10 VDD sg13_lv_pmos m=1 w=1.62u l=130.00n ng=1 nrd=0 nrs=0 +MP1 net10 B net13 VDD sg13_lv_pmos m=1 w=1.62u l=130.00n ng=1 nrd=0 nrs=0 +MN1 Z B VSS VSS sg13_lv_nmos m=1 w=875.000n l=130.00n ng=1 nrd=0 nrs=0 +MN0 Z C VSS VSS sg13_lv_nmos m=1 w=875.000n l=130.00n ng=1 nrd=0 nrs=0 +MN2 Z A VSS VSS sg13_lv_nmos m=1 w=875.000n l=130.00n ng=1 nrd=0 nrs=0 +.ENDS +.SUBCKT RSC_IHPSG13_FILLCAP4 VDD VSS +MN0 vss_r vdd_r VSS VSS sg13_lv_nmos m=1 w=2.49u l=130.00n ng=3 nrd=0 ++ nrs=0 +MP0 vdd_r vss_r VDD VDD sg13_lv_pmos m=1 w=3.24u l=385.000n ng=2 nrd=0 ++ nrs=0 +.ENDS +.SUBCKT RSC_IHPSG13_MET2RES A B +R0 B A lvsres w=2.6e-07 l=6e-07 +.ENDS +.SUBCKT RM_IHPSG13_512x32_c2_1P_DEC04 ADDR<3> ADDR<2> ADDR<1> ADDR<0> CS ECLK_H_BOT ++ ECLK_H_TOP ECLK_L_BOT ECLK_L_TOP WL<15> WL<14> WL<13> WL<12> WL<11> WL<10> ++ WL<9> WL<8> WL<7> WL<6> WL<5> WL<4> WL<3> WL<2> WL<1> WL<0> VDD VSS +XLATCH<3> CS ADDR<3> PADR<3> VDD VSS / RSC_IHPSG13_LHPQX2 +XLATCH<2> CS ADDR<2> PADR<2> VDD VSS / RSC_IHPSG13_LHPQX2 +XLATCH<1> CS ADDR<1> PADR<1> VDD VSS / RSC_IHPSG13_LHPQX2 +XLATCH<0> CS ADDR<0> PADR<0> VDD VSS / RSC_IHPSG13_LHPQX2 +XI0<3> PADR<1> PADR<0> sel01<3> VDD VSS / RSC_IHPSG13_NAND2X2 +XI0<2> PADR<1> NADR<0> sel01<2> VDD VSS / RSC_IHPSG13_NAND2X2 +XI0<1> NADR<1> PADR<0> sel01<1> VDD VSS / RSC_IHPSG13_NAND2X2 +XI0<0> NADR<1> NADR<0> sel01<0> VDD VSS / RSC_IHPSG13_NAND2X2 +XI4 ECLK_L_BOT EN VDD VSS / RSC_IHPSG13_CINVX4 +XI5 ECLK_H_BOT ECLK_L_BOT VDD VSS / RSC_IHPSG13_CINVX2 +XI3<3> PADR<3> NADR<3> VDD VSS / RSC_IHPSG13_INVX2 +XI3<2> PADR<2> NADR<2> VDD VSS / RSC_IHPSG13_INVX2 +XI3<1> PADR<1> NADR<1> VDD VSS / RSC_IHPSG13_INVX2 +XI3<0> PADR<0> NADR<0> VDD VSS / RSC_IHPSG13_INVX2 +XI1<3> PADR<2> PADR<3> CS sel23<3> VDD VSS / RSC_IHPSG13_NAND3X2 +XI1<2> NADR<2> PADR<3> CS sel23<2> VDD VSS / RSC_IHPSG13_NAND3X2 +XI1<1> PADR<2> NADR<3> CS sel23<1> VDD VSS / RSC_IHPSG13_NAND3X2 +XI1<0> NADR<2> NADR<3> CS sel23<0> VDD VSS / RSC_IHPSG13_NAND3X2 +XI2<15> sel23<3> sel01<3> EN WL<15> VDD VSS / RSC_IHPSG13_NOR3X2 +XI2<14> sel23<3> sel01<2> EN WL<14> VDD VSS / RSC_IHPSG13_NOR3X2 +XI2<13> sel23<3> sel01<1> EN WL<13> VDD VSS / RSC_IHPSG13_NOR3X2 +XI2<12> sel23<3> sel01<0> EN WL<12> VDD VSS / RSC_IHPSG13_NOR3X2 +XI2<11> sel23<2> sel01<3> EN WL<11> VDD VSS / RSC_IHPSG13_NOR3X2 +XI2<10> sel23<2> sel01<2> EN WL<10> VDD VSS / RSC_IHPSG13_NOR3X2 +XI2<9> sel23<2> sel01<1> EN WL<9> VDD VSS / RSC_IHPSG13_NOR3X2 +XI2<8> sel23<2> sel01<0> EN WL<8> VDD VSS / RSC_IHPSG13_NOR3X2 +XI2<7> sel23<1> sel01<3> EN WL<7> VDD VSS / RSC_IHPSG13_NOR3X2 +XI2<6> sel23<1> sel01<2> EN WL<6> VDD VSS / RSC_IHPSG13_NOR3X2 +XI2<5> sel23<1> sel01<1> EN WL<5> VDD VSS / RSC_IHPSG13_NOR3X2 +XI2<4> sel23<1> sel01<0> EN WL<4> VDD VSS / RSC_IHPSG13_NOR3X2 +XI2<3> sel23<0> sel01<3> EN WL<3> VDD VSS / RSC_IHPSG13_NOR3X2 +XI2<2> sel23<0> sel01<2> EN WL<2> VDD VSS / RSC_IHPSG13_NOR3X2 +XI2<1> sel23<0> sel01<1> EN WL<1> VDD VSS / RSC_IHPSG13_NOR3X2 +XI2<0> sel23<0> sel01<0> EN WL<0> VDD VSS / RSC_IHPSG13_NOR3X2 +XCAPS4 VDD VSS / RSC_IHPSG13_FILLCAP4 +XI11 ECLK_L_BOT ECLK_L_TOP / RSC_IHPSG13_MET2RES +XR0 ECLK_H_BOT ECLK_H_TOP / RSC_IHPSG13_MET2RES +.ENDS +.SUBCKT RM_IHPSG13_512x32_c2_1P_ROWDEC4 ADDR_N_I<3> ADDR_N_I<2> ADDR_N_I<1> ADDR_N_I<0> ++ CS_I ECLK_I WL_O<15> WL_O<14> WL_O<13> WL_O<12> WL_O<11> WL_O<10> WL_O<9> ++ WL_O<8> WL_O<7> WL_O<6> WL_O<5> WL_O<4> WL_O<3> WL_O<2> WL_O<1> WL_O<0> ++ VDD VSS +XL2<8> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<7> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<6> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<5> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<4> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<3> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<2> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<1> VDD VSS / RSC_IHPSG13_FILLCAP8 +XSEL ADDR_N_I<3> ADDR_N_I<2> ADDR_N_I<1> ADDR_N_I<0> CS_I ECLK_I ECLK_H<1> ++ ECLK_B<0> ECLK_B<1> WL_O<15> WL_O<14> WL_O<13> WL_O<12> WL_O<11> WL_O<10> ++ WL_O<9> WL_O<8> WL_O<7> WL_O<6> WL_O<5> WL_O<4> WL_O<3> WL_O<2> WL_O<1> ++ WL_O<0> VDD VSS / RM_IHPSG13_512x32_c2_1P_DEC04 +.ENDS +.SUBCKT RSC_IHPSG13_CINVX8 A Z VDD VSS +MN0 Z A VSS VSS sg13_lv_nmos m=1 w=2.82u l=130.00n ng=4 nrd=0 nrs=0 +MP0 Z A VDD VDD sg13_lv_pmos m=1 w=6.48u l=130.00n ng=4 nrd=0 nrs=0 +.ENDS +.SUBCKT RSC_IHPSG13_DFNQMX2IX1 BE BI CN D QI QIN VDD VSS +MN15 net026 BI VSS VSS sg13_lv_nmos m=1 w=560.00n l=130.00n ng=1 nrd=0 ++ nrs=0 +MN14 MXI_OUT BE net026 VSS sg13_lv_nmos m=1 w=560.00n l=130.00n ng=1 nrd=0 ++ nrs=0 +MN1 net025 D VSS VSS sg13_lv_nmos m=1 w=560.00n l=130.00n ng=1 nrd=0 ++ nrs=0 +MN0 MXI_OUT BEN net025 VSS sg13_lv_nmos m=1 w=560.00n l=130.00n ng=1 nrd=0 ++ nrs=0 +MN10 QI CNN net21 VSS sg13_lv_nmos m=1 w=850.00n l=130.00n ng=1 nrd=0 nrs=0 +MN11 net21 QI_MS VSS VSS sg13_lv_nmos m=1 w=850.00n l=130.00n ng=1 ++ nrd=0 nrs=0 +MN7 net30 QI_MS VSS VSS sg13_lv_nmos m=1 w=480.00n l=130.00n ng=1 ++ nrd=0 nrs=0 +MN6 QIN_MS CNN net30 VSS sg13_lv_nmos m=1 w=480.00n l=130.00n ng=1 nrd=0 ++ nrs=0 +MN3 QI_MS QIN_MS VSS VSS sg13_lv_nmos m=1 w=480.00n l=130.00n ng=1 ++ nrd=0 nrs=0 +MN12 CNN CN VSS VSS sg13_lv_nmos m=1 w=495.000n l=130.00n ng=1 nrd=0 ++ nrs=0 +MN9 net37 MXI_OUT VSS VSS sg13_lv_nmos m=1 w=870.00n l=130.00n ng=1 ++ nrd=0 nrs=0 +MN8 QIN_MS CN net37 VSS sg13_lv_nmos m=1 w=870.00n l=130.00n ng=1 nrd=0 ++ nrs=0 +MN5 QI CN net25 VSS sg13_lv_nmos m=1 w=480.00n l=130.00n ng=1 nrd=0 nrs=0 +MN4 net25 QIN VSS VSS sg13_lv_nmos m=1 w=480.00n l=130.00n ng=1 nrd=0 ++ nrs=0 +MN2 QIN QI VSS VSS sg13_lv_nmos m=1 w=480.00n l=130.00n ng=1 nrd=0 ++ nrs=0 +MN13 BEN BE VSS VSS sg13_lv_nmos m=1 w=560.00n l=130.00n ng=1 nrd=0 ++ nrs=0 +MP15 MXI_OUT BEN net027 VDD sg13_lv_pmos m=1 w=985.000n l=130.00n ng=1 ++ nrd=0 nrs=0 +MP14 net027 BI VDD VDD sg13_lv_pmos m=1 w=985.000n l=130.00n ng=1 ++ nrd=0 nrs=0 +MP1 MXI_OUT BE net024 VDD sg13_lv_pmos m=1 w=985.000n l=130.00n ng=1 nrd=0 ++ nrs=0 +MP0 net024 D VDD VDD sg13_lv_pmos m=1 w=985.000n l=130.00n ng=1 nrd=0 ++ nrs=0 +MP13 BEN BE VDD VDD sg13_lv_pmos m=1 w=645.000n l=130.00n ng=1 nrd=0 ++ nrs=0 +MP6 QI_MS QIN_MS VDD VDD sg13_lv_pmos m=1 w=480.00n l=130.00n ng=1 ++ nrd=0 nrs=0 +MP3 QI CNN net27 VDD sg13_lv_pmos m=1 w=480.00n l=130.00n ng=1 nrd=0 nrs=0 +MP2 net27 QIN VDD VDD sg13_lv_pmos m=1 w=480.00n l=130.00n ng=1 nrd=0 ++ nrs=0 +MP10 net36 MXI_OUT VDD VDD sg13_lv_pmos m=1 w=975.000n l=130.00n ng=1 ++ nrd=0 nrs=0 +MP11 QIN_MS CNN net36 VDD sg13_lv_pmos m=1 w=975.000n l=130.00n ng=1 nrd=0 ++ nrs=0 +MP4 net32 QI_MS VDD VDD sg13_lv_pmos m=1 w=480.00n l=130.00n ng=1 ++ nrd=0 nrs=0 +MP5 QIN_MS CN net32 VDD sg13_lv_pmos m=1 w=480.00n l=130.00n ng=1 nrd=0 ++ nrs=0 +MP7 QIN QI VDD VDD sg13_lv_pmos m=1 w=480.00n l=130.00n ng=1 nrd=0 ++ nrs=0 +MP12 CNN CN VDD VDD sg13_lv_pmos m=1 w=480.00n l=130.00n ng=1 nrd=0 ++ nrs=0 +MP9 QI CN net19 VDD sg13_lv_pmos m=1 w=990.00n l=130.00n ng=1 nrd=0 nrs=0 +MP8 net19 QI_MS VDD VDD sg13_lv_pmos m=1 w=990.00n l=130.00n ng=1 ++ nrd=0 nrs=0 +.ENDS +.SUBCKT RM_IHPSG13_512x32_c2_1P_ROWREG4 ACLK_N_I ADDR_I<3> ADDR_I<2> ADDR_I<1> ADDR_I<0> ++ ADDR_N_O<3> ADDR_N_O<2> ADDR_N_O<1> ADDR_N_O<0> BIST_ADDR_I<3> ++ BIST_ADDR_I<2> BIST_ADDR_I<1> BIST_ADDR_I<0> BIST_EN_I VDD VSS +XINV<3> q_int<3> qn_int<3> VDD VSS / RSC_IHPSG13_CINVX2 +XINV<2> q_int<2> qn_int<2> VDD VSS / RSC_IHPSG13_CINVX2 +XINV<1> q_int<1> qn_int<1> VDD VSS / RSC_IHPSG13_CINVX2 +XINV<0> q_int<0> qn_int<0> VDD VSS / RSC_IHPSG13_CINVX2 +XDRV<3> qn_int<3> ADDR_N_O<3> VDD VSS / RSC_IHPSG13_CINVX8 +XDRV<2> qn_int<2> ADDR_N_O<2> VDD VSS / RSC_IHPSG13_CINVX8 +XDRV<1> qn_int<1> ADDR_N_O<1> VDD VSS / RSC_IHPSG13_CINVX8 +XDRV<0> qn_int<0> ADDR_N_O<0> VDD VSS / RSC_IHPSG13_CINVX8 +XDFF<3> BIST_EN_I BIST_ADDR_I<3> ACLK_N_I ADDR_I<3> q_int<3> net2<0> VDD ++ VSS / RSC_IHPSG13_DFNQMX2IX1 +XDFF<2> BIST_EN_I BIST_ADDR_I<2> ACLK_N_I ADDR_I<2> q_int<2> net2<1> VDD ++ VSS / RSC_IHPSG13_DFNQMX2IX1 +XDFF<1> BIST_EN_I BIST_ADDR_I<1> ACLK_N_I ADDR_I<1> q_int<1> net2<2> VDD ++ VSS / RSC_IHPSG13_DFNQMX2IX1 +XDFF<0> BIST_EN_I BIST_ADDR_I<0> ACLK_N_I ADDR_I<0> q_int<0> net2<3> VDD ++ VSS / RSC_IHPSG13_DFNQMX2IX1 +XI11<20> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI11<19> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI11<18> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI11<17> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI11<16> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI11<15> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI11<14> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI11<13> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI11<12> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI11<11> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI11<10> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI11<9> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI11<8> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI11<7> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI11<6> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI11<5> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI11<4> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI11<3> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI11<2> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI11<1> VDD VSS / RSC_IHPSG13_FILLCAP8 +.ENDS +.SUBCKT RSC_IHPSG13_CDLYX1 A Z VDD VSS +MN1 net010 net032 VSS VSS sg13_lv_nmos m=1 w=300.0n l=160.00n ng=1 ++ nrd=0 nrs=0 +MN2 net032 A net014 VSS sg13_lv_nmos m=1 w=300.0n l=160.00n ng=1 nrd=0 ++ nrs=0 +MN0 Z net032 net010 VSS sg13_lv_nmos m=1 w=300.0n l=160.00n ng=1 nrd=0 ++ nrs=0 +MN3 net014 A VSS VSS sg13_lv_nmos m=1 w=300.0n l=160.00n ng=1 nrd=0 ++ nrs=0 +MP1 Z net032 net07 VDD sg13_lv_pmos m=1 w=720.00n l=160.00n ng=1 nrd=0 ++ nrs=0 +MP3 net011 A VDD VDD sg13_lv_pmos m=1 w=720.00n l=160.00n ng=1 nrd=0 ++ nrs=0 +MP0 net07 net032 VDD VDD sg13_lv_pmos m=1 w=720.00n l=160.00n ng=1 ++ nrd=0 nrs=0 +MP2 net032 A net011 VDD sg13_lv_pmos m=1 w=720.00n l=160.00n ng=1 nrd=0 ++ nrs=0 +.ENDS +.SUBCKT RSC_IHPSG13_CDLYX1_DUMMY A Z VDD VSS +MN0 vss_r vdd_r VSS VSS sg13_lv_nmos m=1 w=2.49u l=300.0n ng=3 nrd=0 ++ nrs=0 +MP0 vdd_r vss_r VDD VDD sg13_lv_pmos m=1 w=3.24u l=640.00n ng=2 nrd=0 ++ nrs=0 +R0 Z A lvsres w=2.6e-07 l=6e-07 +.ENDS + +.SUBCKT RSC_IHPSG13_MX2IX1 A0 A1 S ZN VDD VSS +MP4 SN S VDD VDD sg13_lv_pmos m=1 w=645.000n l=130.00n ng=1 nrd=0 nrs=0 +MP3 ZN SN net12 VDD sg13_lv_pmos m=1 w=985.000n l=130.00n ng=1 nrd=0 nrs=0 +MP2 net12 A1 VDD VDD sg13_lv_pmos m=1 w=985.000n l=130.00n ng=1 nrd=0 ++ nrs=0 +MP1 ZN S net17 VDD sg13_lv_pmos m=1 w=985.000n l=130.00n ng=1 nrd=0 nrs=0 +MP0 net17 A0 VDD VDD sg13_lv_pmos m=1 w=985.000n l=130.00n ng=1 nrd=0 ++ nrs=0 +MN5 SN S VSS VSS sg13_lv_nmos m=1 w=480.00n l=130.00n ng=1 nrd=0 nrs=0 +MN3 net13 A1 VSS VSS sg13_lv_nmos m=1 w=480.00n l=130.00n ng=1 nrd=0 ++ nrs=0 +MN2 ZN S net13 VSS sg13_lv_nmos m=1 w=480.00n l=130.00n ng=1 nrd=0 nrs=0 +MN1 net15 A0 VSS VSS sg13_lv_nmos m=1 w=480.00n l=130.00n ng=1 nrd=0 ++ nrs=0 +MN0 ZN SN net15 VSS sg13_lv_nmos m=1 w=480.00n l=130.00n ng=1 nrd=0 nrs=0 +.ENDS +.SUBCKT RM_IHPSG13_512x32_c2_1P_DLY_MUX A SEL Z VDD VSS +XI11 net4 Z VDD VSS / RSC_IHPSG13_CINVX2 +XI8 A D<3> SEL net4 VDD VSS / RSC_IHPSG13_MX2IX1 +XI20<3> D<2> D<3> VDD VSS / RSC_IHPSG13_CDLYX1 +XI20<2> D<1> D<2> VDD VSS / RSC_IHPSG13_CDLYX1 +XI20<1> A D<1> VDD VSS / RSC_IHPSG13_CDLYX1 +.ENDS +.SUBCKT RSC_IHPSG13_DFNQX2 CN D Q VDD VSS +MN0 Q QIN_SL VSS VSS sg13_lv_nmos m=1 w=980.00n l=130.00n ng=1 nrd=0 ++ nrs=0 +MN10 QIN_SL CNN net21 VSS sg13_lv_nmos m=1 w=850.00n l=130.00n ng=1 nrd=0 ++ nrs=0 +MN11 net21 QI_MS VSS VSS sg13_lv_nmos m=1 w=850.00n l=130.00n ng=1 ++ nrd=0 nrs=0 +MN7 net30 QI_MS VSS VSS sg13_lv_nmos m=1 w=480.00n l=130.00n ng=1 ++ nrd=0 nrs=0 +MN6 QIN_MS CNN net30 VSS sg13_lv_nmos m=1 w=480.00n l=130.00n ng=1 nrd=0 ++ nrs=0 +MN3 QI_MS QIN_MS VSS VSS sg13_lv_nmos m=1 w=480.00n l=130.00n ng=1 ++ nrd=0 nrs=0 +MN12 CNN CN VSS VSS sg13_lv_nmos m=1 w=495.000n l=130.00n ng=1 nrd=0 ++ nrs=0 +MN9 net37 D VSS VSS sg13_lv_nmos m=1 w=870.00n l=130.00n ng=1 nrd=0 ++ nrs=0 +MN8 QIN_MS CN net37 VSS sg13_lv_nmos m=1 w=870.00n l=130.00n ng=1 nrd=0 ++ nrs=0 +MN5 QIN_SL CN net25 VSS sg13_lv_nmos m=1 w=480.00n l=130.00n ng=1 nrd=0 ++ nrs=0 +MN4 net25 QI_SL VSS VSS sg13_lv_nmos m=1 w=480.00n l=130.00n ng=1 ++ nrd=0 nrs=0 +MN2 QI_SL QIN_SL VSS VSS sg13_lv_nmos m=1 w=480.00n l=130.00n ng=1 ++ nrd=0 nrs=0 +MP0 Q QIN_SL VDD VDD sg13_lv_pmos m=1 w=1.62u l=130.00n ng=1 nrd=0 ++ nrs=0 +MP6 QI_MS QIN_MS VDD VDD sg13_lv_pmos m=1 w=480.00n l=130.00n ng=1 ++ nrd=0 nrs=0 +MP3 QIN_SL CNN net27 VDD sg13_lv_pmos m=1 w=480.00n l=130.00n ng=1 nrd=0 ++ nrs=0 +MP2 net27 QI_SL VDD VDD sg13_lv_pmos m=1 w=480.00n l=130.00n ng=1 ++ nrd=0 nrs=0 +MP10 net36 D VDD VDD sg13_lv_pmos m=1 w=975.000n l=130.00n ng=1 nrd=0 ++ nrs=0 +MP11 QIN_MS CNN net36 VDD sg13_lv_pmos m=1 w=975.000n l=130.00n ng=1 nrd=0 ++ nrs=0 +MP4 net32 QI_MS VDD VDD sg13_lv_pmos m=1 w=480.00n l=130.00n ng=1 ++ nrd=0 nrs=0 +MP5 QIN_MS CN net32 VDD sg13_lv_pmos m=1 w=480.00n l=130.00n ng=1 nrd=0 ++ nrs=0 +MP7 QI_SL QIN_SL VDD VDD sg13_lv_pmos m=1 w=480.00n l=130.00n ng=1 ++ nrd=0 nrs=0 +MP12 CNN CN VDD VDD sg13_lv_pmos m=1 w=480.00n l=130.00n ng=1 nrd=0 ++ nrs=0 +MP9 QIN_SL CN net19 VDD sg13_lv_pmos m=1 w=990.00n l=130.00n ng=1 nrd=0 ++ nrs=0 +MP8 net19 QI_MS VDD VDD sg13_lv_pmos m=1 w=990.00n l=130.00n ng=1 ++ nrd=0 nrs=0 +.ENDS +.SUBCKT RSC_IHPSG13_CNAND2X2 A B Z VDD VSS +MN0 Z B net6 VSS sg13_lv_nmos m=1 w=980.00n l=130.00n ng=1 nrd=0 nrs=0 +MN1 net6 A VSS VSS sg13_lv_nmos m=1 w=980.00n l=130.00n ng=1 nrd=0 ++ nrs=0 +MP1 Z B VDD VDD sg13_lv_pmos m=1 w=1.62u l=130.00n ng=1 nrd=0 nrs=0 +MP0 Z A VDD VDD sg13_lv_pmos m=1 w=1.62u l=130.00n ng=1 nrd=0 nrs=0 +.ENDS +.SUBCKT RSC_IHPSG13_CGATEPX4 CP E Q VDD VSS +MN1 net08 QIN VSS VSS sg13_lv_nmos m=1 w=480.00n l=130.00n ng=1 nrd=0 ++ nrs=0 +MN2 net019 net08 VSS VSS sg13_lv_nmos m=1 w=480.00n l=130.00n ng=1 ++ nrd=0 nrs=0 +MN3 QIN CP net019 VSS sg13_lv_nmos m=1 w=480.00n l=130.00n ng=1 nrd=0 nrs=0 +MN6 Q net015 VSS VSS sg13_lv_nmos m=1 w=1.41u l=130.00n ng=2 nrd=0 ++ nrs=0 +MN5 net015 net08 net018 VSS sg13_lv_nmos m=1 w=980.00n l=130.00n ng=1 ++ nrd=0 nrs=0 +MN8 QIN CPN net023 VSS sg13_lv_nmos m=1 w=870.00n l=130.00n ng=1 nrd=0 ++ nrs=0 +MN7 net023 E VSS VSS sg13_lv_nmos m=1 w=870.00n l=130.00n ng=1 nrd=0 ++ nrs=0 +MN4 net018 CP VSS VSS sg13_lv_nmos m=1 w=980.00n l=130.00n ng=1 nrd=0 ++ nrs=0 +MN0 CPN CP VSS VSS sg13_lv_nmos m=1 w=500.0n l=130.00n ng=1 nrd=0 nrs=0 +MP3 net08 QIN VDD VDD sg13_lv_pmos m=1 w=480.00n l=130.00n ng=1 nrd=0 ++ nrs=0 +MP2 QIN CPN net017 VDD sg13_lv_pmos m=1 w=480.00n l=130.00n ng=1 nrd=0 ++ nrs=0 +MP1 net017 net08 VDD VDD sg13_lv_pmos m=1 w=480.00n l=130.00n ng=1 ++ nrd=0 nrs=0 +MP0 CPN CP VDD VDD sg13_lv_pmos m=1 w=500.0n l=130.00n ng=1 nrd=0 nrs=0 +MP8 QIN CP net024 VDD sg13_lv_pmos m=1 w=975.000n l=130.00n ng=1 nrd=0 ++ nrs=0 +MP7 net024 E VDD VDD sg13_lv_pmos m=1 w=975.000n l=130.00n ng=1 nrd=0 ++ nrs=0 +MP4 net015 CP VDD VDD sg13_lv_pmos m=1 w=1.27u l=130.00n ng=1 nrd=0 ++ nrs=0 +MP6 Q net015 VDD VDD sg13_lv_pmos m=1 w=3.24u l=130.00n ng=2 nrd=0 ++ nrs=0 +MP5 net015 net08 VDD VDD sg13_lv_pmos m=1 w=1.27u l=130.00n ng=1 nrd=0 ++ nrs=0 +.ENDS +.SUBCKT RSC_IHPSG13_CBUFX8 A Z VDD VSS +MP0 net4 A VDD VDD sg13_lv_pmos m=1 w=3.24u l=130.00n ng=2 nrd=0 nrs=0 +MP1 Z net4 VDD VDD sg13_lv_pmos m=1 w=6.48u l=130.00n ng=4 nrd=0 nrs=0 +MN1 Z net4 VSS VSS sg13_lv_nmos m=1 w=2.82u l=130.00n ng=4 nrd=0 nrs=0 +MN0 net4 A VSS VSS sg13_lv_nmos m=1 w=1.41u l=130.00n ng=2 nrd=0 nrs=0 +.ENDS +.SUBCKT RSC_IHPSG13_CDLYX2 A Z VDD VSS +MN2 net4 A net9 VSS sg13_lv_nmos m=1 w=320.00n l=200.0n ng=1 nrd=0 nrs=0 +MN0 Z net4 VSS VSS sg13_lv_nmos m=1 w=705.000n l=130.00n ng=1 nrd=0 ++ nrs=0 +MN1 net9 A VSS VSS sg13_lv_nmos m=1 w=320.00n l=200.0n ng=1 nrd=0 nrs=0 +MP2 net4 A net10 VDD sg13_lv_pmos m=1 w=1.2u l=200.0n ng=1 nrd=0 nrs=0 +MP1 net10 A VDD VDD sg13_lv_pmos m=1 w=1.2u l=200.0n ng=1 nrd=0 nrs=0 +MP0 Z net4 VDD VDD sg13_lv_pmos m=1 w=1.62u l=130.00n ng=1 nrd=0 nrs=0 +.ENDS +.SUBCKT RSC_IHPSG13_MX2X2 A0 A1 S Z VDD VSS +MP6 Z net010 VDD VDD sg13_lv_pmos m=1 w=1.62u l=130.00n ng=1 nrd=0 ++ nrs=0 +MP4 SN S VDD VDD sg13_lv_pmos m=1 w=645.000n l=130.00n ng=1 nrd=0 nrs=0 +MP3 net010 SN net12 VDD sg13_lv_pmos m=1 w=985.000n l=130.00n ng=1 nrd=0 ++ nrs=0 +MP2 net12 A1 VDD VDD sg13_lv_pmos m=1 w=985.000n l=130.00n ng=1 nrd=0 ++ nrs=0 +MP1 net010 S net17 VDD sg13_lv_pmos m=1 w=985.000n l=130.00n ng=1 nrd=0 ++ nrs=0 +MP0 net17 A0 VDD VDD sg13_lv_pmos m=1 w=985.000n l=130.00n ng=1 nrd=0 ++ nrs=0 +MN6 Z net010 VSS VSS sg13_lv_nmos m=1 w=705.000n l=130.00n ng=1 nrd=0 ++ nrs=0 +MN5 SN S VSS VSS sg13_lv_nmos m=1 w=560.00n l=130.00n ng=1 nrd=0 nrs=0 +MN3 net13 A1 VSS VSS sg13_lv_nmos m=1 w=560.00n l=130.00n ng=1 nrd=0 ++ nrs=0 +MN2 net010 S net13 VSS sg13_lv_nmos m=1 w=560.00n l=130.00n ng=1 nrd=0 ++ nrs=0 +MN1 net15 A0 VSS VSS sg13_lv_nmos m=1 w=560.00n l=130.00n ng=1 nrd=0 ++ nrs=0 +MN0 net010 SN net15 VSS sg13_lv_nmos m=1 w=560.00n l=130.00n ng=1 nrd=0 ++ nrs=0 +.ENDS +.SUBCKT RSC_IHPSG13_AND2X2 A B Z VDD VSS +MN3 Z net6 VSS VSS sg13_lv_nmos m=1 w=980.00n l=130.00n ng=1 nrd=0 ++ nrs=0 +MN4 net9 B VSS VSS sg13_lv_nmos m=1 w=500.0n l=130.00n ng=1 nrd=0 nrs=0 +MN6 net6 A net9 VSS sg13_lv_nmos m=1 w=500.0n l=130.00n ng=1 nrd=0 nrs=0 +MP2 Z net6 VDD VDD sg13_lv_pmos m=1 w=1.62u l=130.00n ng=1 nrd=0 nrs=0 +MP0 net6 B VDD VDD sg13_lv_pmos m=1 w=860.00n l=130.00n ng=1 nrd=0 ++ nrs=0 +MP1 net6 A VDD VDD sg13_lv_pmos m=1 w=860.00n l=130.00n ng=1 nrd=0 ++ nrs=0 +.ENDS +.SUBCKT RSC_IHPSG13_TIEL Z VDD VSS +MN0 Z net2 VSS VSS sg13_lv_nmos m=1 w=480.00n l=130.00n ng=1 nrd=0 ++ nrs=0 +MP0 net2 net2 VDD VDD sg13_lv_pmos m=1 w=480.00n l=130.00n ng=1 nrd=0 ++ nrs=0 +.ENDS +.SUBCKT RSC_IHPSG13_XOR2X2 A B Z VDD VSS +MP8 net012 B net7 VDD sg13_lv_pmos m=1 w=825.000n l=130.00n ng=1 nrd=0 ++ nrs=0 +MP7 net011 net3 net012 VDD sg13_lv_pmos m=1 w=825.000n l=130.00n ng=1 ++ nrd=0 nrs=0 +MP6 Z net012 VDD VDD sg13_lv_pmos m=1 w=1.535u l=130.00n ng=1 nrd=0 ++ nrs=0 +MP2 net7 A VDD VDD sg13_lv_pmos m=1 w=825.000n l=130.00n ng=1 nrd=0 ++ nrs=0 +MP4 net011 net7 VDD VDD sg13_lv_pmos m=1 w=825.000n l=130.00n ng=1 ++ nrd=0 nrs=0 +MP5 net3 B VDD VDD sg13_lv_pmos m=1 w=580.00n l=130.00n ng=1 nrd=0 ++ nrs=0 +MN7 net012 B net011 VSS sg13_lv_nmos m=1 w=555.000n l=130.00n ng=1 nrd=0 ++ nrs=0 +MN6 net7 net3 net012 VSS sg13_lv_nmos m=1 w=555.000n l=130.00n ng=1 nrd=0 ++ nrs=0 +MN5 Z net012 VSS VSS sg13_lv_nmos m=1 w=775.000n l=130.00n ng=1 nrd=0 ++ nrs=0 +MN2 net7 A VSS VSS sg13_lv_nmos m=1 w=555.000n l=130.00n ng=1 nrd=0 ++ nrs=0 +MN4 net3 B VSS VSS sg13_lv_nmos m=1 w=480.00n l=130.00n ng=1 nrd=0 ++ nrs=0 +MN3 net011 net7 VSS VSS sg13_lv_nmos m=1 w=555.000n l=130.00n ng=1 ++ nrd=0 nrs=0 +.ENDS +.SUBCKT RSC_IHPSG13_OA12X1 A B C Z VDD VSS +MN2 net7 C VSS VSS sg13_lv_nmos m=1 w=980.00n l=130.00n ng=1 nrd=0 ++ nrs=0 +MN3 Z net17 VSS VSS sg13_lv_nmos m=1 w=500.0n l=130.00n ng=1 nrd=0 ++ nrs=0 +MN1 net17 B net7 VSS sg13_lv_nmos m=1 w=980.00n l=130.00n ng=1 nrd=0 nrs=0 +MN0 net17 A net7 VSS sg13_lv_nmos m=1 w=980.00n l=130.00n ng=1 nrd=0 nrs=0 +MP0 net24 A VDD VDD sg13_lv_pmos m=1 w=1.62u l=130.00n ng=1 nrd=0 nrs=0 +MP3 Z net17 VDD VDD sg13_lv_pmos m=1 w=905.000n l=130.00n ng=1 nrd=0 ++ nrs=0 +MP1 net17 B net24 VDD sg13_lv_pmos m=1 w=1.62u l=130.00n ng=1 nrd=0 nrs=0 +MP2 net17 C VDD VDD sg13_lv_pmos m=1 w=905.000n l=130.00n ng=1 nrd=0 ++ nrs=0 +.ENDS +.SUBCKT RM_IHPSG13_512x32_c2_1P_CTRL ACLK_N BIST_CK_I BIST_CS_I BIST_EN BIST_RE_I ++ BIST_WE_I B_TIEL_O CK_I CS_I DCLK ECLK PULSE_H PULSE_L PULSE_O RCLK RE_I ++ ROW_CS WCLK WE_I VDD VSS +XI17 ck_regs we col_we VDD VSS / RSC_IHPSG13_DFNQX2 +XI16 ck_regs re col_re VDD VSS / RSC_IHPSG13_DFNQX2 +XI18 ck_regs cs net7 VDD VSS / RSC_IHPSG13_DFNQX2 +XI71 ACLK_N net012 PULSE_O VDD VSS / RSC_IHPSG13_DFNQX2 +XI77 col_we net9 net016 VDD VSS / RSC_IHPSG13_CNAND2X2 +XI76 col_re net9 net018 VDD VSS / RSC_IHPSG13_CNAND2X2 +XI15 ck_dly WEorREandCS aclk VDD VSS / RSC_IHPSG13_CGATEPX4 +XI14 ck WEandCS DCLK VDD VSS / RSC_IHPSG13_CGATEPX4 +XI60 net7 ROW_CS VDD VSS / RSC_IHPSG13_CBUFX8 +XI73 PULSE_O net012 VDD VSS / RSC_IHPSG13_CINVX2 +XI8 net9 net8 VDD VSS / RSC_IHPSG13_CINVX2 +XI64 ck ck_dly VDD VSS / RSC_IHPSG13_CDLYX2 +XI86 CS_I BIST_CS_I BIST_EN cs VDD VSS / RSC_IHPSG13_MX2X2 +XI87 CK_I BIST_CK_I BIST_EN ck VDD VSS / RSC_IHPSG13_MX2X2 +XI85 WE_I BIST_WE_I BIST_EN we VDD VSS / RSC_IHPSG13_MX2X2 +XI84 RE_I BIST_RE_I BIST_EN re VDD VSS / RSC_IHPSG13_MX2X2 +XI22 we cs WEandCS VDD VSS / RSC_IHPSG13_AND2X2 +XBM_TIEL B_TIEL_O VDD VSS / RSC_IHPSG13_TIEL +XI48 ck_dly ck_regs VDD VSS / RSC_IHPSG13_CINVX4 +XI81 net016 WCLK VDD VSS / RSC_IHPSG13_CINVX4 +XI80 net018 RCLK VDD VSS / RSC_IHPSG13_CINVX4 +XI78 net8 net020 VDD VSS / RSC_IHPSG13_CINVX4 +XI6 PULSE_L PULSE_H net9 VDD VSS / RSC_IHPSG13_XOR2X2 +XI79 net020 ECLK VDD VSS / RSC_IHPSG13_CINVX8 +XI63 aclk ACLK_N VDD VSS / RSC_IHPSG13_CINVX8 +XI21 re we cs WEorREandCS VDD VSS / RSC_IHPSG13_OA12X1 +.ENDS +.SUBCKT RM_IHPSG13_512x32_c2_1P_COLDEC2 ACLK_N ADDR<1> ADDR<0> ADDR_COL<1> ADDR_COL<0> ++ ADDR_DEC<7> ADDR_DEC<6> ADDR_DEC<5> ADDR_DEC<4> ADDR_DEC<3> ADDR_DEC<2> ++ ADDR_DEC<1> ADDR_DEC<0> BIST_ADDR<1> BIST_ADDR<0> BIST_EN_I VDD VSS +XI14<5> VDD VSS / RSC_IHPSG13_FILLCAP4 +XI14<4> VDD VSS / RSC_IHPSG13_FILLCAP4 +XI14<3> VDD VSS / RSC_IHPSG13_FILLCAP4 +XI14<2> VDD VSS / RSC_IHPSG13_FILLCAP4 +XI14<1> VDD VSS / RSC_IHPSG13_FILLCAP4 +XDFF<1> BIST_EN_I BIST_ADDR<1> ACLK_N ADDR<1> padr_int<1> net6<0> VDD ++ VSS / RSC_IHPSG13_DFNQMX2IX1 +XDFF<0> BIST_EN_I BIST_ADDR<0> ACLK_N ADDR<0> padr_int<0> net6<1> VDD ++ VSS / RSC_IHPSG13_DFNQMX2IX1 +XI1<3> PADR<1> PADR<0> addr_n<3> VDD VSS / RSC_IHPSG13_NAND2X2 +XI1<2> PADR<1> NADR<0> addr_n<2> VDD VSS / RSC_IHPSG13_NAND2X2 +XI1<1> NADR<1> PADR<0> addr_n<1> VDD VSS / RSC_IHPSG13_NAND2X2 +XI1<0> NADR<1> NADR<0> addr_n<0> VDD VSS / RSC_IHPSG13_NAND2X2 +XI16<37> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI16<36> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI16<35> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI16<34> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI16<33> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI16<32> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI16<31> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI16<30> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI16<29> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI16<28> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI16<27> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI16<26> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI16<25> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI16<24> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI16<23> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI16<22> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI16<21> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI16<20> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI16<19> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI16<18> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI16<17> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI16<16> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI16<15> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI16<14> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI16<13> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI16<12> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI16<11> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI16<10> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI16<9> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI16<8> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI16<7> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI16<6> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI16<5> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI16<4> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI16<3> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI16<2> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI16<1> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI3<1> padr_int<1> NADR<1> VDD VSS / RSC_IHPSG13_INVX2 +XI3<0> padr_int<0> NADR<0> VDD VSS / RSC_IHPSG13_INVX2 +XI13<1> NADR<1> PADR<1> VDD VSS / RSC_IHPSG13_INVX2 +XI13<0> NADR<0> PADR<0> VDD VSS / RSC_IHPSG13_INVX2 +XI2<3> addr_n<3> ADDR_DEC<3> VDD VSS / RSC_IHPSG13_INVX2 +XI2<2> addr_n<2> ADDR_DEC<2> VDD VSS / RSC_IHPSG13_INVX2 +XI2<1> addr_n<1> ADDR_DEC<1> VDD VSS / RSC_IHPSG13_INVX2 +XI2<0> addr_n<0> ADDR_DEC<0> VDD VSS / RSC_IHPSG13_INVX2 +XI15<1> ADDR_COL<1> VDD VSS / RSC_IHPSG13_TIEL +XI15<0> ADDR_COL<0> VDD VSS / RSC_IHPSG13_TIEL +XI17<3> ADDR_DEC<7> VDD VSS / RSC_IHPSG13_TIEL +XI17<2> ADDR_DEC<6> VDD VSS / RSC_IHPSG13_TIEL +XI17<1> ADDR_DEC<5> VDD VSS / RSC_IHPSG13_TIEL +XI17<0> ADDR_DEC<4> VDD VSS / RSC_IHPSG13_TIEL +.ENDS +.SUBCKT RSC_IHPSG13_NOR2X2 A B Z VDD VSS +MP1 Z B net9 VDD sg13_lv_pmos m=1 w=1.62u l=130.00n ng=1 nrd=0 nrs=0 +MP0 net9 A VDD VDD sg13_lv_pmos m=1 w=1.62u l=130.00n ng=1 nrd=0 nrs=0 +MN0 Z B VSS VSS sg13_lv_nmos m=1 w=980.00n l=130.00n ng=1 nrd=0 nrs=0 +MN1 Z A VSS VSS sg13_lv_nmos m=1 w=980.00n l=130.00n ng=1 nrd=0 nrs=0 +.ENDS +.SUBCKT RSC_IHPSG13_CINVX4_WN A Z VDD VSS +MN0 Z A VSS VSS sg13_lv_nmos m=1 w=705.000n l=130.00n ng=1 nrd=0 nrs=0 +MP0 Z A VDD VDD sg13_lv_pmos m=1 w=3.24u l=130.00n ng=2 nrd=0 nrs=0 +.ENDS +.SUBCKT RM_IHPSG13_512x32_c2_1P_BLDRV BLC BLC_SEL BLT BLT_SEL PRE_N SEL_P WR_ONE WR_ZERO ++ VDD VSS +XCDEC SEL_P WR_ZERO BLC_PMOS_DRIVE VDD VSS / RSC_IHPSG13_NAND2X2 +XTDEC SEL_P WR_ONE BLT_PMOS_DRIVE VDD VSS / RSC_IHPSG13_NAND2X2 +MTWN BLT BLT_NMOS_DRIVE VSS VSS sg13_lv_nmos m=1 w=4.82u l=130.00n ++ ng=2 nrd=0 nrs=0 +MCWN BLC BLC_NMOS_DRIVE VSS VSS sg13_lv_nmos m=1 w=4.82u l=130.00n ++ ng=2 nrd=0 nrs=0 +MCWP BLC BLC_PMOS_DRIVE VDD VDD sg13_lv_pmos m=1 w=1.5u l=130.00n ng=1 ++ nrd=0 nrs=0 +MTWP BLT BLT_PMOS_DRIVE VDD VDD sg13_lv_pmos m=1 w=1.5u l=130.00n ng=1 ++ nrd=0 nrs=0 +MTSP BLT_SEL SEL_N BLT VDD sg13_lv_pmos m=1 w=1.5u l=130.00n ng=1 nrd=0 ++ nrs=0 +MTPR BLT PRE_N VDD VDD sg13_lv_pmos m=1 w=3.000u l=130.00n ng=2 nrd=0 ++ nrs=0 +MCSP BLC_SEL SEL_N BLC VDD sg13_lv_pmos m=1 w=1.5u l=130.00n ng=1 nrd=0 ++ nrs=0 +MCPR BLC PRE_N VDD VDD sg13_lv_pmos m=1 w=3.000u l=130.00n ng=2 nrd=0 ++ nrs=0 +XI86 SEL_P SEL_N VDD VSS / RSC_IHPSG13_INVX2 +XTINV BLC_PMOS_DRIVE BLT_NMOS_DRIVE VDD VSS / RSC_IHPSG13_INVX2 +XCINV BLT_PMOS_DRIVE BLC_NMOS_DRIVE VDD VSS / RSC_IHPSG13_INVX2 +.ENDS +.SUBCKT RSC_IHPSG13_TIEH Z VDD VSS +MN0 net2 net2 VSS VSS sg13_lv_nmos m=1 w=480.00n l=130.00n ng=1 nrd=0 ++ nrs=0 +MP0 Z net2 VDD VDD sg13_lv_pmos m=1 w=480.00n l=130.00n ng=1 nrd=0 ++ nrs=0 +.ENDS +.SUBCKT RSC_IHPSG13_MET3RES A B +R0 B A lvsres w=2.6e-07 l=6e-07 +.ENDS +.SUBCKT RSC_IHPSG13_DFPQD_MSAFFX2 CP DN DP QN QP VDD VSS +MN12 SN RN DIFFP VSS sg13_lv_nmos m=1 w=2.4u l=200.0n ng=2 nrd=0 nrs=0 +MN13 TAIL CP VSS VSS sg13_lv_nmos m=1 w=2.4u l=130.00n ng=2 nrd=0 nrs=0 +MN9 DIFFP DP TAIL VSS sg13_lv_nmos m=1 w=2.4u l=200.0n ng=2 nrd=0 nrs=0 +MN10 DIFFN DN TAIL VSS sg13_lv_nmos m=1 w=2.4u l=200.0n ng=2 nrd=0 nrs=0 +MN11 RN SN DIFFN VSS sg13_lv_nmos m=1 w=2.4u l=200.0n ng=2 nrd=0 nrs=0 +MN19 net33 SN VSS VSS sg13_lv_nmos m=1 w=980.00n l=130.00n ng=1 nrd=0 ++ nrs=0 +MN20 QN QP net37 VSS sg13_lv_nmos m=1 w=980.00n l=130.00n ng=1 nrd=0 nrs=0 +MN18 net37 RN VSS VSS sg13_lv_nmos m=1 w=980.00n l=130.00n ng=1 nrd=0 ++ nrs=0 +MN17 QP QN net33 VSS sg13_lv_nmos m=1 w=980.00n l=130.00n ng=1 nrd=0 nrs=0 +MP15 SN RN VDD VDD sg13_lv_pmos m=1 w=800.0n l=130.00n ng=1 nrd=0 nrs=0 +MP16 RN CP VDD VDD sg13_lv_pmos m=1 w=800.0n l=130.00n ng=1 nrd=0 nrs=0 +MP14 DIFFP CP VDD VDD sg13_lv_pmos m=1 w=800.0n l=130.00n ng=1 nrd=0 ++ nrs=0 +MP12 RN SN VDD VDD sg13_lv_pmos m=1 w=800.0n l=130.00n ng=1 nrd=0 nrs=0 +MP13 DIFFN CP VDD VDD sg13_lv_pmos m=1 w=800.0n l=130.00n ng=1 nrd=0 ++ nrs=0 +MP11 SN CP VDD VDD sg13_lv_pmos m=1 w=800.0n l=130.00n ng=1 nrd=0 nrs=0 +MP19 QN QP VDD VDD sg13_lv_pmos m=1 w=900.0n l=130.00n ng=1 nrd=0 nrs=0 +MP20 QP SN VDD VDD sg13_lv_pmos m=1 w=1.8u l=130.00n ng=2 nrd=0 nrs=0 +MP18 QN RN VDD VDD sg13_lv_pmos m=1 w=1.8u l=130.00n ng=2 nrd=0 nrs=0 +MP17 QP QN VDD VDD sg13_lv_pmos m=1 w=900.0n l=130.00n ng=1 nrd=0 nrs=0 +.ENDS +.SUBCKT RSC_IHPSG13_CBUFX2 A Z VDD VSS +MN1 Z net4 VSS VSS sg13_lv_nmos m=1 w=705.000n l=130.00n ng=1 nrd=0 ++ nrs=0 +MN0 net4 A VSS VSS sg13_lv_nmos m=1 w=540.00n l=130.00n ng=1 nrd=0 ++ nrs=0 +MP1 Z net4 VDD VDD sg13_lv_pmos m=1 w=1.62u l=130.00n ng=1 nrd=0 nrs=0 +MP0 net4 A VDD VDD sg13_lv_pmos m=1 w=1.1u l=130.00n ng=1 nrd=0 nrs=0 +.ENDS +.SUBCKT RSC_IHPSG13_INVX4 A Z VDD VSS +MN0 Z A VSS VSS sg13_lv_nmos m=1 w=1.96u l=130.00n ng=2 nrd=0 nrs=0 +MP0 Z A VDD VDD sg13_lv_pmos m=1 w=3.24u l=130.00n ng=2 nrd=0 nrs=0 +.ENDS +.SUBCKT RM_IHPSG13_512x32_c2_1P_COLCTRL2 A_ADDR_DEC<3> A_ADDR_DEC<2> A_ADDR_DEC<1> ++ A_ADDR_DEC<0> A_BIST_BM_I A_BIST_DW_I A_BIST_EN_I A_BLC<3> A_BLC<2> A_BLC<1> ++ A_BLC<0> A_BLT<3> A_BLT<2> A_BLT<1> A_BLT<0> A_BM_I A_DCLK_B_L A_DCLK_B_R ++ A_DCLK_L A_DCLK_R A_DR_O A_DW_I A_RCLK_B_L A_RCLK_B_R A_RCLK_L A_RCLK_R ++ A_TIEH_O A_WCLK_B_L A_WCLK_B_R A_WCLK_L A_WCLK_R VDD VSS +XA_DREG A_BIST_EN_I A_BIST_DW_I A_DCLK_B_L A_DW_I A_DI_R net22 VDD VSS ++ / RSC_IHPSG13_DFNQMX2IX1 +XA_BREG A_BIST_EN_I A_BIST_BM_I A_DCLK_B_L A_BM_I A_BM_R net23 VDD VSS ++ / RSC_IHPSG13_DFNQMX2IX1 +XA_CAPS<5> VDD VSS / RSC_IHPSG13_FILLCAP4 +XA_CAPS<4> VDD VSS / RSC_IHPSG13_FILLCAP4 +XA_CAPS<3> VDD VSS / RSC_IHPSG13_FILLCAP4 +XA_CAPS<2> VDD VSS / RSC_IHPSG13_FILLCAP4 +XA_CAPS<1> VDD VSS / RSC_IHPSG13_FILLCAP4 +XA_I80 A_WCLK_B_R A_RCLK_B_R net21 VDD VSS / RSC_IHPSG13_AND2X2 +XA_I75 A_DI_R A_DO_WRITE_P A_WR_ONE VDD VSS / RSC_IHPSG13_AND2X2 +XA_I76 A_DI_N A_DO_WRITE_P A_WR_ZERO VDD VSS / RSC_IHPSG13_AND2X2 +XA_I44 A_WCLK_B_R A_BM_N A_DO_WRITE_P VDD VSS / RSC_IHPSG13_NOR2X2 +XA_I81 net21 A_PRE_N VDD VSS / RSC_IHPSG13_CINVX4_WN +XA_BLTMUX<3> A_BLC<3> A_BLC_SEL A_BLT<3> A_BLT_SEL A_PRE_N A_ADDR_DEC<3> ++ A_WR_ONE A_WR_ZERO VDD VSS / RM_IHPSG13_512x32_c2_1P_BLDRV +XA_BLTMUX<2> A_BLC<2> A_BLC_SEL A_BLT<2> A_BLT_SEL A_PRE_N A_ADDR_DEC<2> ++ A_WR_ONE A_WR_ZERO VDD VSS / RM_IHPSG13_512x32_c2_1P_BLDRV +XA_BLTMUX<1> A_BLC<1> A_BLC_SEL A_BLT<1> A_BLT_SEL A_PRE_N A_ADDR_DEC<1> ++ A_WR_ONE A_WR_ZERO VDD VSS / RM_IHPSG13_512x32_c2_1P_BLDRV +XA_BLTMUX<0> A_BLC<0> A_BLC_SEL A_BLT<0> A_BLT_SEL A_PRE_N A_ADDR_DEC<0> ++ A_WR_ONE A_WR_ZERO VDD VSS / RM_IHPSG13_512x32_c2_1P_BLDRV +XA_BM_TIEH A_TIEH_O VDD VSS / RSC_IHPSG13_TIEH +XA_I89 A_DCLK_B_L A_DCLK_B_R / RSC_IHPSG13_MET3RES +XA_I88 A_DCLK_L A_DCLK_R / RSC_IHPSG13_MET3RES +XA_I87 A_WCLK_L A_WCLK_R / RSC_IHPSG13_MET3RES +XA_I91 A_RCLK_B_R A_RCLK_B_L / RSC_IHPSG13_MET3RES +XA_R2 A_RCLK_R A_RCLK_L / RSC_IHPSG13_MET3RES +XA_I90 A_WCLK_B_R A_WCLK_B_L / RSC_IHPSG13_MET3RES +XA_ISENSE A_SAE A_BLC_SEL A_BLT_SEL net19 net20 VDD VSS / ++ RSC_IHPSG13_DFPQD_MSAFFX2 +XA_I78 A_RCLK_B_R A_SAE VDD VSS / RSC_IHPSG13_CBUFX2 +XA_I83 A_BM_R A_BM_N VDD VSS / RSC_IHPSG13_INVX2 +XA_I49 A_DI_R A_DI_N VDD VSS / RSC_IHPSG13_INVX2 +XA_I51 net19 A_DR_O VDD VSS / RSC_IHPSG13_INVX4 +XA_I69 A_DCLK_L A_DCLK_B_L VDD VSS / RSC_IHPSG13_CINVX2 +XA_I50 A_WCLK_L A_WCLK_B_R VDD VSS / RSC_IHPSG13_CINVX2 +XA_EBUF A_RCLK_R A_RCLK_B_R VDD VSS / RSC_IHPSG13_CINVX2 +.ENDS +.SUBCKT RM_IHPSG13_512x32_c2_1P_COLDRV13_FILL4 VDD VSS +XI0<9> VDD VSS / RSC_IHPSG13_FILLCAP4 +XI0<8> VDD VSS / RSC_IHPSG13_FILLCAP4 +XI0<7> VDD VSS / RSC_IHPSG13_FILLCAP4 +XI0<6> VDD VSS / RSC_IHPSG13_FILLCAP4 +XI0<5> VDD VSS / RSC_IHPSG13_FILLCAP4 +XI0<4> VDD VSS / RSC_IHPSG13_FILLCAP4 +XI0<3> VDD VSS / RSC_IHPSG13_FILLCAP4 +XI0<2> VDD VSS / RSC_IHPSG13_FILLCAP4 +XI0<1> VDD VSS / RSC_IHPSG13_FILLCAP4 +.ENDS +.SUBCKT RM_IHPSG13_512x32_c2_1P_COLDRV13_FILL4C2 VDD VSS +XI0<2> VDD VSS / RSC_IHPSG13_FILLCAP4 +XI0<1> VDD VSS / RSC_IHPSG13_FILLCAP4 +.ENDS + + +.SUBCKT RM_IHPSG13_512x32_c2_1P_COLDEC4 ACLK_N ADDR<3> ADDR<2> ADDR<1> ADDR<0> ++ ADDR_COL<1> ADDR_COL<0> ADDR_DEC<7> ADDR_DEC<6> ADDR_DEC<5> ADDR_DEC<4> ++ ADDR_DEC<3> ADDR_DEC<2> ADDR_DEC<1> ADDR_DEC<0> BIST_ADDR<3> BIST_ADDR<2> ++ BIST_ADDR<1> BIST_ADDR<0> BIST_EN_I VDD VSS +XI15 ADDR_COL<1> VDD VSS / RSC_IHPSG13_TIEL +XI14 addr_int ADDR_COL<0> VDD VSS / RSC_IHPSG13_CBUFX2 +XDFF<3> BIST_EN_I BIST_ADDR<3> ACLK_N ADDR<3> addr_int net7<0> VDD VSS ++ / RSC_IHPSG13_DFNQMX2IX1 +XDFF<2> BIST_EN_I BIST_ADDR<2> ACLK_N ADDR<2> padr_int<2> net7<1> VDD ++ VSS / RSC_IHPSG13_DFNQMX2IX1 +XDFF<1> BIST_EN_I BIST_ADDR<1> ACLK_N ADDR<1> padr_int<1> net7<2> VDD ++ VSS / RSC_IHPSG13_DFNQMX2IX1 +XDFF<0> BIST_EN_I BIST_ADDR<0> ACLK_N ADDR<0> padr_int<0> net7<3> VDD ++ VSS / RSC_IHPSG13_DFNQMX2IX1 +XI1<7> PADR<0> PADR<1> PADR<2> addr_n<7> VDD VSS / RSC_IHPSG13_NAND3X2 +XI1<6> NADR<0> PADR<1> PADR<2> addr_n<6> VDD VSS / RSC_IHPSG13_NAND3X2 +XI1<5> PADR<0> NADR<1> PADR<2> addr_n<5> VDD VSS / RSC_IHPSG13_NAND3X2 +XI1<4> NADR<0> NADR<1> PADR<2> addr_n<4> VDD VSS / RSC_IHPSG13_NAND3X2 +XI1<3> PADR<0> PADR<1> NADR<2> addr_n<3> VDD VSS / RSC_IHPSG13_NAND3X2 +XI1<2> NADR<0> PADR<1> NADR<2> addr_n<2> VDD VSS / RSC_IHPSG13_NAND3X2 +XI1<1> PADR<0> NADR<1> NADR<2> addr_n<1> VDD VSS / RSC_IHPSG13_NAND3X2 +XI1<0> NADR<0> NADR<1> NADR<2> addr_n<0> VDD VSS / RSC_IHPSG13_NAND3X2 +XI13<2> NADR<2> PADR<2> VDD VSS / RSC_IHPSG13_INVX2 +XI13<1> NADR<1> PADR<1> VDD VSS / RSC_IHPSG13_INVX2 +XI13<0> NADR<0> PADR<0> VDD VSS / RSC_IHPSG13_INVX2 +XI3<2> padr_int<2> NADR<2> VDD VSS / RSC_IHPSG13_INVX2 +XI3<1> padr_int<1> NADR<1> VDD VSS / RSC_IHPSG13_INVX2 +XI3<0> padr_int<0> NADR<0> VDD VSS / RSC_IHPSG13_INVX2 +XI2<7> addr_n<7> ADDR_DEC<7> VDD VSS / RSC_IHPSG13_INVX2 +XI2<6> addr_n<6> ADDR_DEC<6> VDD VSS / RSC_IHPSG13_INVX2 +XI2<5> addr_n<5> ADDR_DEC<5> VDD VSS / RSC_IHPSG13_INVX2 +XI2<4> addr_n<4> ADDR_DEC<4> VDD VSS / RSC_IHPSG13_INVX2 +XI2<3> addr_n<3> ADDR_DEC<3> VDD VSS / RSC_IHPSG13_INVX2 +XI2<2> addr_n<2> ADDR_DEC<2> VDD VSS / RSC_IHPSG13_INVX2 +XI2<1> addr_n<1> ADDR_DEC<1> VDD VSS / RSC_IHPSG13_INVX2 +XI2<0> addr_n<0> ADDR_DEC<0> VDD VSS / RSC_IHPSG13_INVX2 +XI16<3> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI16<2> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI16<1> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI17<2> VDD VSS / RSC_IHPSG13_FILLCAP4 +XI17<1> VDD VSS / RSC_IHPSG13_FILLCAP4 +.ENDS +.SUBCKT RSC_IHPSG13_AND2X4 A B Z VDD VSS +MN3 Z net6 VSS VSS sg13_lv_nmos m=1 w=1.96u l=130.00n ng=2 nrd=0 nrs=0 +MN4 net9 B VSS VSS sg13_lv_nmos m=1 w=500.0n l=130.00n ng=1 nrd=0 nrs=0 +MN6 net6 A net9 VSS sg13_lv_nmos m=1 w=500.0n l=130.00n ng=1 nrd=0 nrs=0 +MP2 Z net6 VDD VDD sg13_lv_pmos m=1 w=3.24u l=130.00n ng=2 nrd=0 nrs=0 +MP0 net6 B VDD VDD sg13_lv_pmos m=1 w=860.00n l=130.00n ng=1 nrd=0 ++ nrs=0 +MP1 net6 A VDD VDD sg13_lv_pmos m=1 w=860.00n l=130.00n ng=1 nrd=0 ++ nrs=0 +.ENDS +.SUBCKT RM_IHPSG13_512x32_c2_1P_COLCTRL4 A_ADDR_COL A_ADDR_DEC<7> A_ADDR_DEC<6> ++ A_ADDR_DEC<5> A_ADDR_DEC<4> A_ADDR_DEC<3> A_ADDR_DEC<2> A_ADDR_DEC<1> ++ A_ADDR_DEC<0> A_BIST_BM_I A_BIST_DW_I A_BIST_EN_I A_BLC<15> A_BLC<14> ++ A_BLC<13> A_BLC<12> A_BLC<11> A_BLC<10> A_BLC<9> A_BLC<8> A_BLC<7> A_BLC<6> ++ A_BLC<5> A_BLC<4> A_BLC<3> A_BLC<2> A_BLC<1> A_BLC<0> A_BLT<15> A_BLT<14> ++ A_BLT<13> A_BLT<12> A_BLT<11> A_BLT<10> A_BLT<9> A_BLT<8> A_BLT<7> A_BLT<6> ++ A_BLT<5> A_BLT<4> A_BLT<3> A_BLT<2> A_BLT<1> A_BLT<0> A_BM_I A_DCLK_B_L ++ A_DCLK_B_R A_DCLK_L A_DCLK_R A_DR_O A_DW_I A_RCLK_B_L A_RCLK_B_R A_RCLK_L ++ A_RCLK_R A_TIEH_O A_WCLK_B_L A_WCLK_B_R A_WCLK_L A_WCLK_R VDD VSS +XA_I80 A_WCLK_B_L A_RCLK_B_L net21 VDD VSS / RSC_IHPSG13_AND2X2 +XA_I76 A_DO_WRITE_P A_DI_N A_WR_ZERO VDD VSS / RSC_IHPSG13_AND2X4 +XA_I75 A_DI_R A_DO_WRITE_P A_WR_ONE VDD VSS / RSC_IHPSG13_AND2X4 +XA_CAPS<8> VDD VSS / RSC_IHPSG13_FILLCAP4 +XA_CAPS<7> VDD VSS / RSC_IHPSG13_FILLCAP4 +XA_CAPS<6> VDD VSS / RSC_IHPSG13_FILLCAP4 +XA_CAPS<5> VDD VSS / RSC_IHPSG13_FILLCAP4 +XA_CAPS<4> VDD VSS / RSC_IHPSG13_FILLCAP4 +XA_CAPS<3> VDD VSS / RSC_IHPSG13_FILLCAP4 +XA_CAPS<2> VDD VSS / RSC_IHPSG13_FILLCAP4 +XA_CAPS<1> VDD VSS / RSC_IHPSG13_FILLCAP4 +XA_I69 A_DCLK_L A_DCLK_B_L VDD VSS / RSC_IHPSG13_CINVX4 +XA_I50 A_WCLK_L A_WCLK_B_L VDD VSS / RSC_IHPSG13_CINVX4 +XA_EBUF A_RCLK_L A_RCLK_B_L VDD VSS / RSC_IHPSG13_CINVX4 +XA_INV<1> A_N0 A_P0 VDD VSS / RSC_IHPSG13_CINVX4 +XA_INV<0> A_ADDR_COL A_N0 VDD VSS / RSC_IHPSG13_CINVX4 +XA_I81<1> net21 A_PRE_N VDD VSS / RSC_IHPSG13_CINVX4_WN +XA_I81<0> net21 A_PRE_N VDD VSS / RSC_IHPSG13_CINVX4_WN +XA_BLTMUX<15> A_BLC<15> A_BLC_SEL A_BLT<15> A_BLT_SEL A_PRE_N A_SEL_P<15> ++ A_WR_ONE A_WR_ZERO VDD VSS / RM_IHPSG13_512x32_c2_1P_BLDRV +XA_BLTMUX<14> A_BLC<14> A_BLC_SEL A_BLT<14> A_BLT_SEL A_PRE_N A_SEL_P<14> ++ A_WR_ONE A_WR_ZERO VDD VSS / RM_IHPSG13_512x32_c2_1P_BLDRV +XA_BLTMUX<13> A_BLC<13> A_BLC_SEL A_BLT<13> A_BLT_SEL A_PRE_N A_SEL_P<13> ++ A_WR_ONE A_WR_ZERO VDD VSS / RM_IHPSG13_512x32_c2_1P_BLDRV +XA_BLTMUX<12> A_BLC<12> A_BLC_SEL A_BLT<12> A_BLT_SEL A_PRE_N A_SEL_P<12> ++ A_WR_ONE A_WR_ZERO VDD VSS / RM_IHPSG13_512x32_c2_1P_BLDRV +XA_BLTMUX<11> A_BLC<11> A_BLC_SEL A_BLT<11> A_BLT_SEL A_PRE_N A_SEL_P<11> ++ A_WR_ONE A_WR_ZERO VDD VSS / RM_IHPSG13_512x32_c2_1P_BLDRV +XA_BLTMUX<10> A_BLC<10> A_BLC_SEL A_BLT<10> A_BLT_SEL A_PRE_N A_SEL_P<10> ++ A_WR_ONE A_WR_ZERO VDD VSS / RM_IHPSG13_512x32_c2_1P_BLDRV +XA_BLTMUX<9> A_BLC<9> A_BLC_SEL A_BLT<9> A_BLT_SEL A_PRE_N A_SEL_P<9> A_WR_ONE ++ A_WR_ZERO VDD VSS / RM_IHPSG13_512x32_c2_1P_BLDRV +XA_BLTMUX<8> A_BLC<8> A_BLC_SEL A_BLT<8> A_BLT_SEL A_PRE_N A_SEL_P<8> A_WR_ONE ++ A_WR_ZERO VDD VSS / RM_IHPSG13_512x32_c2_1P_BLDRV +XA_BLTMUX<7> A_BLC<7> A_BLC_SEL A_BLT<7> A_BLT_SEL A_PRE_N A_SEL_P<7> A_WR_ONE ++ A_WR_ZERO VDD VSS / RM_IHPSG13_512x32_c2_1P_BLDRV +XA_BLTMUX<6> A_BLC<6> A_BLC_SEL A_BLT<6> A_BLT_SEL A_PRE_N A_SEL_P<6> A_WR_ONE ++ A_WR_ZERO VDD VSS / RM_IHPSG13_512x32_c2_1P_BLDRV +XA_BLTMUX<5> A_BLC<5> A_BLC_SEL A_BLT<5> A_BLT_SEL A_PRE_N A_SEL_P<5> A_WR_ONE ++ A_WR_ZERO VDD VSS / RM_IHPSG13_512x32_c2_1P_BLDRV +XA_BLTMUX<4> A_BLC<4> A_BLC_SEL A_BLT<4> A_BLT_SEL A_PRE_N A_SEL_P<4> A_WR_ONE ++ A_WR_ZERO VDD VSS / RM_IHPSG13_512x32_c2_1P_BLDRV +XA_BLTMUX<3> A_BLC<3> A_BLC_SEL A_BLT<3> A_BLT_SEL A_PRE_N A_SEL_P<3> A_WR_ONE ++ A_WR_ZERO VDD VSS / RM_IHPSG13_512x32_c2_1P_BLDRV +XA_BLTMUX<2> A_BLC<2> A_BLC_SEL A_BLT<2> A_BLT_SEL A_PRE_N A_SEL_P<2> A_WR_ONE ++ A_WR_ZERO VDD VSS / RM_IHPSG13_512x32_c2_1P_BLDRV +XA_BLTMUX<1> A_BLC<1> A_BLC_SEL A_BLT<1> A_BLT_SEL A_PRE_N A_SEL_P<1> A_WR_ONE ++ A_WR_ZERO VDD VSS / RM_IHPSG13_512x32_c2_1P_BLDRV +XA_BLTMUX<0> A_BLC<0> A_BLC_SEL A_BLT<0> A_BLT_SEL A_PRE_N A_SEL_P<0> A_WR_ONE ++ A_WR_ZERO VDD VSS / RM_IHPSG13_512x32_c2_1P_BLDRV +XA_R2 A_RCLK_L A_RCLK_R / RSC_IHPSG13_MET3RES +XA_I87 A_WCLK_L A_WCLK_R / RSC_IHPSG13_MET3RES +XA_I88 A_DCLK_L A_DCLK_R / RSC_IHPSG13_MET3RES +XA_I89 A_DCLK_B_L A_DCLK_B_R / RSC_IHPSG13_MET3RES +XA_I90 A_WCLK_B_L A_WCLK_B_R / RSC_IHPSG13_MET3RES +XA_I91 A_RCLK_B_L A_RCLK_B_R / RSC_IHPSG13_MET3RES +XA_ISENSE A_SAE A_BLC_SEL A_BLT_SEL net19 net20 VDD VSS / ++ RSC_IHPSG13_DFPQD_MSAFFX2 +XA_I51 net19 A_DR_O VDD VSS / RSC_IHPSG13_INVX4 +XA_I78 A_RCLK_B_L A_SAE VDD VSS / RSC_IHPSG13_CBUFX2 +XA_DREG A_BIST_EN_I A_BIST_DW_I A_DCLK_B_L A_DW_I A_DI_R net22 VDD VSS ++ / RSC_IHPSG13_DFNQMX2IX1 +XA_BREG A_BIST_EN_I A_BIST_BM_I A_DCLK_B_L A_BM_I A_BM_R net24 VDD VSS ++ / RSC_IHPSG13_DFNQMX2IX1 +XA_DEC3INV<15> net23<0> A_SEL_P<15> VDD VSS / RSC_IHPSG13_INVX2 +XA_DEC3INV<14> net23<1> A_SEL_P<14> VDD VSS / RSC_IHPSG13_INVX2 +XA_DEC3INV<13> net23<2> A_SEL_P<13> VDD VSS / RSC_IHPSG13_INVX2 +XA_DEC3INV<12> net23<3> A_SEL_P<12> VDD VSS / RSC_IHPSG13_INVX2 +XA_DEC3INV<11> net23<4> A_SEL_P<11> VDD VSS / RSC_IHPSG13_INVX2 +XA_DEC3INV<10> net23<5> A_SEL_P<10> VDD VSS / RSC_IHPSG13_INVX2 +XA_DEC3INV<9> net23<6> A_SEL_P<9> VDD VSS / RSC_IHPSG13_INVX2 +XA_DEC3INV<8> net23<7> A_SEL_P<8> VDD VSS / RSC_IHPSG13_INVX2 +XA_DEC3INV<7> net23<8> A_SEL_P<7> VDD VSS / RSC_IHPSG13_INVX2 +XA_DEC3INV<6> net23<9> A_SEL_P<6> VDD VSS / RSC_IHPSG13_INVX2 +XA_DEC3INV<5> net23<10> A_SEL_P<5> VDD VSS / RSC_IHPSG13_INVX2 +XA_DEC3INV<4> net23<11> A_SEL_P<4> VDD VSS / RSC_IHPSG13_INVX2 +XA_DEC3INV<3> net23<12> A_SEL_P<3> VDD VSS / RSC_IHPSG13_INVX2 +XA_DEC3INV<2> net23<13> A_SEL_P<2> VDD VSS / RSC_IHPSG13_INVX2 +XA_DEC3INV<1> net23<14> A_SEL_P<1> VDD VSS / RSC_IHPSG13_INVX2 +XA_DEC3INV<0> net23<15> A_SEL_P<0> VDD VSS / RSC_IHPSG13_INVX2 +XA_I83 A_BM_R A_BM_N VDD VSS / RSC_IHPSG13_INVX2 +XA_I49 A_DI_R A_DI_N VDD VSS / RSC_IHPSG13_INVX2 +XA_I70<4> VDD VSS / RSC_IHPSG13_FILLCAP8 +XA_I70<3> VDD VSS / RSC_IHPSG13_FILLCAP8 +XA_I70<2> VDD VSS / RSC_IHPSG13_FILLCAP8 +XA_I70<1> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI73<14> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI73<13> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI73<12> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI73<11> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI73<10> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI73<9> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI73<8> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI73<7> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI73<6> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI73<5> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI73<4> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI73<3> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI73<2> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI73<1> VDD VSS / RSC_IHPSG13_FILLCAP8 +XA_I44 A_BM_N A_WCLK_B_L A_DO_WRITE_P VDD VSS / RSC_IHPSG13_NOR2X2 +XA_DEC3<15> A_P0 A_ADDR_DEC<7> net23<0> VDD VSS / RSC_IHPSG13_NAND2X2 +XA_DEC3<14> A_P0 A_ADDR_DEC<6> net23<1> VDD VSS / RSC_IHPSG13_NAND2X2 +XA_DEC3<13> A_P0 A_ADDR_DEC<5> net23<2> VDD VSS / RSC_IHPSG13_NAND2X2 +XA_DEC3<12> A_P0 A_ADDR_DEC<4> net23<3> VDD VSS / RSC_IHPSG13_NAND2X2 +XA_DEC3<11> A_P0 A_ADDR_DEC<3> net23<4> VDD VSS / RSC_IHPSG13_NAND2X2 +XA_DEC3<10> A_P0 A_ADDR_DEC<2> net23<5> VDD VSS / RSC_IHPSG13_NAND2X2 +XA_DEC3<9> A_P0 A_ADDR_DEC<1> net23<6> VDD VSS / RSC_IHPSG13_NAND2X2 +XA_DEC3<8> A_P0 A_ADDR_DEC<0> net23<7> VDD VSS / RSC_IHPSG13_NAND2X2 +XA_DEC3<7> A_N0 A_ADDR_DEC<7> net23<8> VDD VSS / RSC_IHPSG13_NAND2X2 +XA_DEC3<6> A_N0 A_ADDR_DEC<6> net23<9> VDD VSS / RSC_IHPSG13_NAND2X2 +XA_DEC3<5> A_N0 A_ADDR_DEC<5> net23<10> VDD VSS / RSC_IHPSG13_NAND2X2 +XA_DEC3<4> A_N0 A_ADDR_DEC<4> net23<11> VDD VSS / RSC_IHPSG13_NAND2X2 +XA_DEC3<3> A_N0 A_ADDR_DEC<3> net23<12> VDD VSS / RSC_IHPSG13_NAND2X2 +XA_DEC3<2> A_N0 A_ADDR_DEC<2> net23<13> VDD VSS / RSC_IHPSG13_NAND2X2 +XA_DEC3<1> A_N0 A_ADDR_DEC<1> net23<14> VDD VSS / RSC_IHPSG13_NAND2X2 +XA_DEC3<0> A_N0 A_ADDR_DEC<0> net23<15> VDD VSS / RSC_IHPSG13_NAND2X2 +XA_BM_TIEH A_TIEH_O VDD VSS / RSC_IHPSG13_TIEH +.ENDS + + +.SUBCKT RM_IHPSG13_512x32_c2_1P_COLDEC3 ACLK_N ADDR<2> ADDR<1> ADDR<0> ADDR_COL<1> ++ ADDR_COL<0> ADDR_DEC<7> ADDR_DEC<6> ADDR_DEC<5> ADDR_DEC<4> ADDR_DEC<3> ++ ADDR_DEC<2> ADDR_DEC<1> ADDR_DEC<0> BIST_ADDR<2> BIST_ADDR<1> BIST_ADDR<0> ++ BIST_EN_I VDD VSS +XI15<1> ADDR_COL<1> VDD VSS / RSC_IHPSG13_TIEL +XI15<0> ADDR_COL<0> VDD VSS / RSC_IHPSG13_TIEL +XI1<7> PADR<0> PADR<1> PADR<2> addr_n<7> VDD VSS / RSC_IHPSG13_NAND3X2 +XI1<6> NADR<0> PADR<1> PADR<2> addr_n<6> VDD VSS / RSC_IHPSG13_NAND3X2 +XI1<5> PADR<0> NADR<1> PADR<2> addr_n<5> VDD VSS / RSC_IHPSG13_NAND3X2 +XI1<4> NADR<0> NADR<1> PADR<2> addr_n<4> VDD VSS / RSC_IHPSG13_NAND3X2 +XI1<3> PADR<0> PADR<1> NADR<2> addr_n<3> VDD VSS / RSC_IHPSG13_NAND3X2 +XI1<2> NADR<0> PADR<1> NADR<2> addr_n<2> VDD VSS / RSC_IHPSG13_NAND3X2 +XI1<1> PADR<0> NADR<1> NADR<2> addr_n<1> VDD VSS / RSC_IHPSG13_NAND3X2 +XI1<0> NADR<0> NADR<1> NADR<2> addr_n<0> VDD VSS / RSC_IHPSG13_NAND3X2 +XDFF<2> BIST_EN_I BIST_ADDR<2> ACLK_N ADDR<2> padr_int<2> net6<0> VDD ++ VSS / RSC_IHPSG13_DFNQMX2IX1 +XDFF<1> BIST_EN_I BIST_ADDR<1> ACLK_N ADDR<1> padr_int<1> net6<1> VDD ++ VSS / RSC_IHPSG13_DFNQMX2IX1 +XDFF<0> BIST_EN_I BIST_ADDR<0> ACLK_N ADDR<0> padr_int<0> net6<2> VDD ++ VSS / RSC_IHPSG13_DFNQMX2IX1 +XI17<2> VDD VSS / RSC_IHPSG13_FILLCAP4 +XI17<1> VDD VSS / RSC_IHPSG13_FILLCAP4 +XI13<2> NADR<2> PADR<2> VDD VSS / RSC_IHPSG13_INVX2 +XI13<1> NADR<1> PADR<1> VDD VSS / RSC_IHPSG13_INVX2 +XI13<0> NADR<0> PADR<0> VDD VSS / RSC_IHPSG13_INVX2 +XI3<2> padr_int<2> NADR<2> VDD VSS / RSC_IHPSG13_INVX2 +XI3<1> padr_int<1> NADR<1> VDD VSS / RSC_IHPSG13_INVX2 +XI3<0> padr_int<0> NADR<0> VDD VSS / RSC_IHPSG13_INVX2 +XI2<7> addr_n<7> ADDR_DEC<7> VDD VSS / RSC_IHPSG13_INVX2 +XI2<6> addr_n<6> ADDR_DEC<6> VDD VSS / RSC_IHPSG13_INVX2 +XI2<5> addr_n<5> ADDR_DEC<5> VDD VSS / RSC_IHPSG13_INVX2 +XI2<4> addr_n<4> ADDR_DEC<4> VDD VSS / RSC_IHPSG13_INVX2 +XI2<3> addr_n<3> ADDR_DEC<3> VDD VSS / RSC_IHPSG13_INVX2 +XI2<2> addr_n<2> ADDR_DEC<2> VDD VSS / RSC_IHPSG13_INVX2 +XI2<1> addr_n<1> ADDR_DEC<1> VDD VSS / RSC_IHPSG13_INVX2 +XI2<0> addr_n<0> ADDR_DEC<0> VDD VSS / RSC_IHPSG13_INVX2 +XI16<6> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI16<5> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI16<4> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI16<3> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI16<2> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI16<1> VDD VSS / RSC_IHPSG13_FILLCAP8 +.ENDS +.SUBCKT RM_IHPSG13_512x32_c2_1P_COLCTRL3 A_ADDR_DEC<7> A_ADDR_DEC<6> A_ADDR_DEC<5> ++ A_ADDR_DEC<4> A_ADDR_DEC<3> A_ADDR_DEC<2> A_ADDR_DEC<1> A_ADDR_DEC<0> ++ A_BIST_BM_I A_BIST_DW_I A_BIST_EN_I A_BLC<7> A_BLC<6> A_BLC<5> A_BLC<4> ++ A_BLC<3> A_BLC<2> A_BLC<1> A_BLC<0> A_BLT<7> A_BLT<6> A_BLT<5> A_BLT<4> ++ A_BLT<3> A_BLT<2> A_BLT<1> A_BLT<0> A_BM_I A_DCLK_B_L A_DCLK_B_R A_DCLK_L ++ A_DCLK_R A_DR_O A_DW_I A_RCLK_B_L A_RCLK_B_R A_RCLK_L A_RCLK_R A_TIEH_O ++ A_WCLK_B_L A_WCLK_B_R A_WCLK_L A_WCLK_R VDD VSS +XA_DREG A_BIST_EN_I A_BIST_DW_I A_DCLK_B_L A_DW_I A_DI_R net22 VDD VSS ++ / RSC_IHPSG13_DFNQMX2IX1 +XA_BREG A_BIST_EN_I A_BIST_BM_I A_DCLK_B_R A_BM_I A_BM_R net23 VDD VSS ++ / RSC_IHPSG13_DFNQMX2IX1 +XA_I70<8> VDD VSS / RSC_IHPSG13_FILLCAP8 +XA_I70<7> VDD VSS / RSC_IHPSG13_FILLCAP8 +XA_I70<6> VDD VSS / RSC_IHPSG13_FILLCAP8 +XA_I70<5> VDD VSS / RSC_IHPSG13_FILLCAP8 +XA_I70<4> VDD VSS / RSC_IHPSG13_FILLCAP8 +XA_I70<3> VDD VSS / RSC_IHPSG13_FILLCAP8 +XA_I70<2> VDD VSS / RSC_IHPSG13_FILLCAP8 +XA_I70<1> VDD VSS / RSC_IHPSG13_FILLCAP8 +XA_I51 net19 A_DR_O VDD VSS / RSC_IHPSG13_INVX4 +XA_I44 A_BM_N A_WCLK_B_R A_DO_WRITE_P VDD VSS / RSC_IHPSG13_NOR2X2 +XA_BM_TIEH A_TIEH_O VDD VSS / RSC_IHPSG13_TIEH +XA_BLTMUX<7> A_BLC<7> A_BLC_SEL A_BLT<7> A_BLT_SEL A_PRE_N A_ADDR_DEC<7> ++ A_WR_ONE A_WR_ZERO VDD VSS / RM_IHPSG13_512x32_c2_1P_BLDRV +XA_BLTMUX<6> A_BLC<6> A_BLC_SEL A_BLT<6> A_BLT_SEL A_PRE_N A_ADDR_DEC<6> ++ A_WR_ONE A_WR_ZERO VDD VSS / RM_IHPSG13_512x32_c2_1P_BLDRV +XA_BLTMUX<5> A_BLC<5> A_BLC_SEL A_BLT<5> A_BLT_SEL A_PRE_N A_ADDR_DEC<5> ++ A_WR_ONE A_WR_ZERO VDD VSS / RM_IHPSG13_512x32_c2_1P_BLDRV +XA_BLTMUX<4> A_BLC<4> A_BLC_SEL A_BLT<4> A_BLT_SEL A_PRE_N A_ADDR_DEC<4> ++ A_WR_ONE A_WR_ZERO VDD VSS / RM_IHPSG13_512x32_c2_1P_BLDRV +XA_BLTMUX<3> A_BLC<3> A_BLC_SEL A_BLT<3> A_BLT_SEL A_PRE_N A_ADDR_DEC<3> ++ A_WR_ONE A_WR_ZERO VDD VSS / RM_IHPSG13_512x32_c2_1P_BLDRV +XA_BLTMUX<2> A_BLC<2> A_BLC_SEL A_BLT<2> A_BLT_SEL A_PRE_N A_ADDR_DEC<2> ++ A_WR_ONE A_WR_ZERO VDD VSS / RM_IHPSG13_512x32_c2_1P_BLDRV +XA_BLTMUX<1> A_BLC<1> A_BLC_SEL A_BLT<1> A_BLT_SEL A_PRE_N A_ADDR_DEC<1> ++ A_WR_ONE A_WR_ZERO VDD VSS / RM_IHPSG13_512x32_c2_1P_BLDRV +XA_BLTMUX<0> A_BLC<0> A_BLC_SEL A_BLT<0> A_BLT_SEL A_PRE_N A_ADDR_DEC<0> ++ A_WR_ONE A_WR_ZERO VDD VSS / RM_IHPSG13_512x32_c2_1P_BLDRV +XA_I49 A_DI_R A_DI_N VDD VSS / RSC_IHPSG13_INVX2 +XA_I83 A_BM_R A_BM_N VDD VSS / RSC_IHPSG13_INVX2 +XA_I69 A_DCLK_L A_DCLK_B_L VDD VSS / RSC_IHPSG13_CINVX2 +XA_I50 A_WCLK_L A_WCLK_B_L VDD VSS / RSC_IHPSG13_CINVX2 +XA_EBUF A_RCLK_L A_RCLK_B_L VDD VSS / RSC_IHPSG13_CINVX2 +XA_I78 A_RCLK_B_L A_SAE VDD VSS / RSC_IHPSG13_CBUFX2 +XA_I88 A_DCLK_L A_DCLK_R / RSC_IHPSG13_MET3RES +XA_I87 A_WCLK_L A_WCLK_R / RSC_IHPSG13_MET3RES +XA_R2 A_RCLK_L A_RCLK_R / RSC_IHPSG13_MET3RES +XA_I91 A_RCLK_B_L A_RCLK_B_R / RSC_IHPSG13_MET3RES +XA_I90 A_WCLK_B_L A_WCLK_B_R / RSC_IHPSG13_MET3RES +XA_I89 A_DCLK_B_L A_DCLK_B_R / RSC_IHPSG13_MET3RES +XA_I80 A_WCLK_B_R A_RCLK_B_R net21 VDD VSS / RSC_IHPSG13_AND2X2 +XA_I76 A_DI_N A_DO_WRITE_P A_WR_ZERO VDD VSS / RSC_IHPSG13_AND2X2 +XA_I75 A_DI_R A_DO_WRITE_P A_WR_ONE VDD VSS / RSC_IHPSG13_AND2X2 +XA_ISENSE A_SAE A_BLC_SEL A_BLT_SEL net19 net20 VDD VSS / ++ RSC_IHPSG13_DFPQD_MSAFFX2 +XA_I81 net21 A_PRE_N VDD VSS / RSC_IHPSG13_CINVX4_WN +XA_CAPS<5> VDD VSS / RSC_IHPSG13_FILLCAP4 +XA_CAPS<4> VDD VSS / RSC_IHPSG13_FILLCAP4 +XA_CAPS<3> VDD VSS / RSC_IHPSG13_FILLCAP4 +XA_CAPS<2> VDD VSS / RSC_IHPSG13_FILLCAP4 +XA_CAPS<1> VDD VSS / RSC_IHPSG13_FILLCAP4 +.ENDS + +.SUBCKT RM_IHPSG13_512x32_c2_2P_BITKIT_16x2_CORNER VDD_CORE VSS +XI16 VDD_CORE VSS VDD_CORE VSS / ++ RM_IHPSG13_512x32_c2_1P_BITKIT_CORNER +.ENDS +.SUBCKT RM_IHPSG13_512x32_c2_2P_BITKIT_EDGE_LR A_WL B_WL NW PW VDD VSS +MN1 VSS A_WL VSS VSS sg13_lv_nmos m=1 w=300.0n l=130.00n ng=1 nrd=0 nrs=0 +MN0 VSS B_WL VSS VSS sg13_lv_nmos m=1 w=300.0n l=130.00n ng=1 nrd=0 nrs=0 +.ENDS +.SUBCKT RM_IHPSG13_512x32_c2_2P_BITKIT_16x2_EDGE_LR A_WL<15> A_WL<14> A_WL<13> A_WL<12> ++ A_WL<11> A_WL<10> A_WL<9> A_WL<8> A_WL<7> A_WL<6> A_WL<5> A_WL<4> A_WL<3> ++ A_WL<2> A_WL<1> A_WL<0> B_WL<15> B_WL<14> B_WL<13> B_WL<12> B_WL<11> ++ B_WL<10> B_WL<9> B_WL<8> B_WL<7> B_WL<6> B_WL<5> B_WL<4> B_WL<3> B_WL<2> ++ B_WL<1> B_WL<0> VDD_CORE VSS +XI0<15> A_WL<15> B_WL<15> VDD_CORE VSS VDD_CORE VSS ++ / RM_IHPSG13_512x32_c2_2P_BITKIT_EDGE_LR +XI0<14> A_WL<14> B_WL<14> VDD_CORE VSS VDD_CORE VSS ++ / RM_IHPSG13_512x32_c2_2P_BITKIT_EDGE_LR +XI0<13> A_WL<13> B_WL<13> VDD_CORE VSS VDD_CORE VSS ++ / RM_IHPSG13_512x32_c2_2P_BITKIT_EDGE_LR +XI0<12> A_WL<12> B_WL<12> VDD_CORE VSS VDD_CORE VSS ++ / RM_IHPSG13_512x32_c2_2P_BITKIT_EDGE_LR +XI0<11> A_WL<11> B_WL<11> VDD_CORE VSS VDD_CORE VSS ++ / RM_IHPSG13_512x32_c2_2P_BITKIT_EDGE_LR +XI0<10> A_WL<10> B_WL<10> VDD_CORE VSS VDD_CORE VSS ++ / RM_IHPSG13_512x32_c2_2P_BITKIT_EDGE_LR +XI0<9> A_WL<9> B_WL<9> VDD_CORE VSS VDD_CORE VSS / ++ RM_IHPSG13_512x32_c2_2P_BITKIT_EDGE_LR +XI0<8> A_WL<8> B_WL<8> VDD_CORE VSS VDD_CORE VSS / ++ RM_IHPSG13_512x32_c2_2P_BITKIT_EDGE_LR +XI0<7> A_WL<7> B_WL<7> VDD_CORE VSS VDD_CORE VSS / ++ RM_IHPSG13_512x32_c2_2P_BITKIT_EDGE_LR +XI0<6> A_WL<6> B_WL<6> VDD_CORE VSS VDD_CORE VSS / ++ RM_IHPSG13_512x32_c2_2P_BITKIT_EDGE_LR +XI0<5> A_WL<5> B_WL<5> VDD_CORE VSS VDD_CORE VSS / ++ RM_IHPSG13_512x32_c2_2P_BITKIT_EDGE_LR +XI0<4> A_WL<4> B_WL<4> VDD_CORE VSS VDD_CORE VSS / ++ RM_IHPSG13_512x32_c2_2P_BITKIT_EDGE_LR +XI0<3> A_WL<3> B_WL<3> VDD_CORE VSS VDD_CORE VSS / ++ RM_IHPSG13_512x32_c2_2P_BITKIT_EDGE_LR +XI0<2> A_WL<2> B_WL<2> VDD_CORE VSS VDD_CORE VSS / ++ RM_IHPSG13_512x32_c2_2P_BITKIT_EDGE_LR +XI0<1> A_WL<1> B_WL<1> VDD_CORE VSS VDD_CORE VSS / ++ RM_IHPSG13_512x32_c2_2P_BITKIT_EDGE_LR +XI0<0> A_WL<0> B_WL<0> VDD_CORE VSS VDD_CORE VSS / ++ RM_IHPSG13_512x32_c2_2P_BITKIT_EDGE_LR +.ENDS +.SUBCKT RM_IHPSG13_512x32_c2_2P_BITKIT_CELL A_BLC_BOT A_BLC_TOP A_BLT_BOT A_BLT_TOP ++ A_LWL A_RWL B_BLC_BOT B_BLC_TOP B_BLT_BOT B_BLT_TOP B_LWL B_RWL NW PW VDD VSS +MN5 NC B_RWL B_BLC_BOT PW sg13_lv_nmos m=1 w=300.0n l=130.00n ng=1 nrd=0 nrs=0 +MN4 B_BLT_BOT B_LWL NT PW sg13_lv_nmos m=1 w=300.0n l=130.00n ng=1 nrd=0 nrs=0 +MN0 NC NT VSS PW sg13_lv_nmos m=1 w=600.0n l=130.00n ng=2 nrd=0 nrs=0 +MN1 NT NC VSS PW sg13_lv_nmos m=1 w=600.0n l=130.00n ng=2 nrd=0 nrs=0 +MN3 NC A_RWL A_BLC_TOP PW sg13_lv_nmos m=1 w=300.0n l=130.00n ng=1 nrd=0 nrs=0 +MN2 A_BLT_TOP A_LWL NT PW sg13_lv_nmos m=1 w=300.0n l=130.00n ng=1 nrd=0 nrs=0 +MP1 NT NC VDD NW sg13_lv_pmos m=1 w=150.00n l=130.00n ng=1 nrd=0 nrs=0 +MP0 NC NT VDD NW sg13_lv_pmos m=1 w=150.00n l=130.00n ng=1 nrd=0 nrs=0 +R5 B_RWL B_LWL lvsres w=2.6e-07 l=6e-07 +R4 B_BLC_BOT B_BLC_TOP lvsres w=2.6e-07 l=6e-07 +R3 B_BLT_BOT B_BLT_TOP lvsres w=2.6e-07 l=6e-07 +R1 A_BLC_BOT A_BLC_TOP lvsres w=2.6e-07 l=6e-07 +R0 A_BLT_BOT A_BLT_TOP lvsres w=2.6e-07 l=6e-07 +R2 A_RWL A_LWL lvsres w=2.6e-07 l=6e-07 +.ENDS +.SUBCKT RM_IHPSG13_512x32_c2_2P_BITKIT_16x2_SRAM A_BLC_BOT<1> A_BLC_BOT<0> A_BLC_TOP<1> ++ A_BLC_TOP<0> A_BLT_BOT<1> A_BLT_BOT<0> A_BLT_TOP<1> A_BLT_TOP<0> A_LWL<15> ++ A_LWL<14> A_LWL<13> A_LWL<12> A_LWL<11> A_LWL<10> A_LWL<9> A_LWL<8> A_LWL<7> ++ A_LWL<6> A_LWL<5> A_LWL<4> A_LWL<3> A_LWL<2> A_LWL<1> A_LWL<0> A_RWL<15> ++ A_RWL<14> A_RWL<13> A_RWL<12> A_RWL<11> A_RWL<10> A_RWL<9> A_RWL<8> A_RWL<7> ++ A_RWL<6> A_RWL<5> A_RWL<4> A_RWL<3> A_RWL<2> A_RWL<1> A_RWL<0> B_BLC_BOT<1> ++ B_BLC_BOT<0> B_BLC_TOP<1> B_BLC_TOP<0> B_BLT_BOT<1> B_BLT_BOT<0> ++ B_BLT_TOP<1> B_BLT_TOP<0> B_LWL<15> B_LWL<14> B_LWL<13> B_LWL<12> B_LWL<11> ++ B_LWL<10> B_LWL<9> B_LWL<8> B_LWL<7> B_LWL<6> B_LWL<5> B_LWL<4> B_LWL<3> ++ B_LWL<2> B_LWL<1> B_LWL<0> B_RWL<15> B_RWL<14> B_RWL<13> B_RWL<12> B_RWL<11> ++ B_RWL<10> B_RWL<9> B_RWL<8> B_RWL<7> B_RWL<6> B_RWL<5> B_RWL<4> B_RWL<3> ++ B_RWL<2> B_RWL<1> B_RWL<0> VDD_CORE VSS +XCELL<31> A_BLC_TOP<1> A_RBLC<15> A_BLT_TOP<1> A_RBLT<15> A_XWL<15> A_RWL<15> ++ B_BLC_TOP<1> B_RBLC<15> B_BLT_TOP<1> B_RBLT<15> B_XWL<15> B_RWL<15> ++ VDD_CORE VSS VDD_CORE VSS / ++ RM_IHPSG13_512x32_c2_2P_BITKIT_CELL +XCELL<30> A_RBLC<14> A_RBLC<15> A_RBLT<14> A_RBLT<15> A_XWL<14> A_RWL<14> ++ B_RBLC<14> B_RBLC<15> B_RBLT<14> B_RBLT<15> B_XWL<14> B_RWL<14> VDD_CORE ++ VSS VDD_CORE VSS / RM_IHPSG13_512x32_c2_2P_BITKIT_CELL +XCELL<29> A_RBLC<14> A_RBLC<13> A_RBLT<14> A_RBLT<13> A_XWL<13> A_RWL<13> ++ B_RBLC<14> B_RBLC<13> B_RBLT<14> B_RBLT<13> B_XWL<13> B_RWL<13> VDD_CORE ++ VSS VDD_CORE VSS / RM_IHPSG13_512x32_c2_2P_BITKIT_CELL +XCELL<28> A_RBLC<12> A_RBLC<13> A_RBLT<12> A_RBLT<13> A_XWL<12> A_RWL<12> ++ B_RBLC<12> B_RBLC<13> B_RBLT<12> B_RBLT<13> B_XWL<12> B_RWL<12> VDD_CORE ++ VSS VDD_CORE VSS / RM_IHPSG13_512x32_c2_2P_BITKIT_CELL +XCELL<27> A_RBLC<12> A_RBLC<11> A_RBLT<12> A_RBLT<11> A_XWL<11> A_RWL<11> ++ B_RBLC<12> B_RBLC<11> B_RBLT<12> B_RBLT<11> B_XWL<11> B_RWL<11> VDD_CORE ++ VSS VDD_CORE VSS / RM_IHPSG13_512x32_c2_2P_BITKIT_CELL +XCELL<26> A_RBLC<10> A_RBLC<11> A_RBLT<10> A_RBLT<11> A_XWL<10> A_RWL<10> ++ B_RBLC<10> B_RBLC<11> B_RBLT<10> B_RBLT<11> B_XWL<10> B_RWL<10> VDD_CORE ++ VSS VDD_CORE VSS / RM_IHPSG13_512x32_c2_2P_BITKIT_CELL +XCELL<25> A_RBLC<10> A_RBLC<9> A_RBLT<10> A_RBLT<9> A_XWL<9> A_RWL<9> ++ B_RBLC<10> B_RBLC<9> B_RBLT<10> B_RBLT<9> B_XWL<9> B_RWL<9> VDD_CORE ++ VSS VDD_CORE VSS / RM_IHPSG13_512x32_c2_2P_BITKIT_CELL +XCELL<24> A_RBLC<8> A_RBLC<9> A_RBLT<8> A_RBLT<9> A_XWL<8> A_RWL<8> B_RBLC<8> ++ B_RBLC<9> B_RBLT<8> B_RBLT<9> B_XWL<8> B_RWL<8> VDD_CORE VSS ++ VDD_CORE VSS / RM_IHPSG13_512x32_c2_2P_BITKIT_CELL +XCELL<23> A_RBLC<8> A_RBLC<7> A_RBLT<8> A_RBLT<7> A_XWL<7> A_RWL<7> B_RBLC<8> ++ B_RBLC<7> B_RBLT<8> B_RBLT<7> B_XWL<7> B_RWL<7> VDD_CORE VSS ++ VDD_CORE VSS / RM_IHPSG13_512x32_c2_2P_BITKIT_CELL +XCELL<22> A_RBLC<6> A_RBLC<7> A_RBLT<6> A_RBLT<7> A_XWL<6> A_RWL<6> B_RBLC<6> ++ B_RBLC<7> B_RBLT<6> B_RBLT<7> B_XWL<6> B_RWL<6> VDD_CORE VSS ++ VDD_CORE VSS / RM_IHPSG13_512x32_c2_2P_BITKIT_CELL +XCELL<21> A_RBLC<6> A_RBLC<5> A_RBLT<6> A_RBLT<5> A_XWL<5> A_RWL<5> B_RBLC<6> ++ B_RBLC<5> B_RBLT<6> B_RBLT<5> B_XWL<5> B_RWL<5> VDD_CORE VSS ++ VDD_CORE VSS / RM_IHPSG13_512x32_c2_2P_BITKIT_CELL +XCELL<20> A_RBLC<4> A_RBLC<5> A_RBLT<4> A_RBLT<5> A_XWL<4> A_RWL<4> B_RBLC<4> ++ B_RBLC<5> B_RBLT<4> B_RBLT<5> B_XWL<4> B_RWL<4> VDD_CORE VSS ++ VDD_CORE VSS / RM_IHPSG13_512x32_c2_2P_BITKIT_CELL +XCELL<19> A_RBLC<4> A_RBLC<3> A_RBLT<4> A_RBLT<3> A_XWL<3> A_RWL<3> B_RBLC<4> ++ B_RBLC<3> B_RBLT<4> B_RBLT<3> B_XWL<3> B_RWL<3> VDD_CORE VSS ++ VDD_CORE VSS / RM_IHPSG13_512x32_c2_2P_BITKIT_CELL +XCELL<18> A_RBLC<2> A_RBLC<3> A_RBLT<2> A_RBLT<3> A_XWL<2> A_RWL<2> B_RBLC<2> ++ B_RBLC<3> B_RBLT<2> B_RBLT<3> B_XWL<2> B_RWL<2> VDD_CORE VSS ++ VDD_CORE VSS / RM_IHPSG13_512x32_c2_2P_BITKIT_CELL +XCELL<17> A_RBLC<2> A_RBLC<1> A_RBLT<2> A_RBLT<1> A_XWL<1> A_RWL<1> B_RBLC<2> ++ B_RBLC<1> B_RBLT<2> B_RBLT<1> B_XWL<1> B_RWL<1> VDD_CORE VSS ++ VDD_CORE VSS / RM_IHPSG13_512x32_c2_2P_BITKIT_CELL +XCELL<16> A_BLC_BOT<1> A_RBLC<1> A_BLT_BOT<1> A_RBLT<1> A_XWL<0> A_RWL<0> ++ B_BLC_BOT<1> B_RBLC<1> B_BLT_BOT<1> B_RBLT<1> B_XWL<0> B_RWL<0> VDD_CORE ++ VSS VDD_CORE VSS / RM_IHPSG13_512x32_c2_2P_BITKIT_CELL +XCELL<15> A_BLC_TOP<0> A_LBLC<15> A_BLT_TOP<0> A_LBLT<15> A_LWL<15> A_XWL<15> ++ B_BLC_TOP<0> B_LBLC<15> B_BLT_TOP<0> B_LBLT<15> B_LWL<15> B_XWL<15> ++ VDD_CORE VSS VDD_CORE VSS / ++ RM_IHPSG13_512x32_c2_2P_BITKIT_CELL +XCELL<14> A_LBLC<14> A_LBLC<15> A_LBLT<14> A_LBLT<15> A_LWL<14> A_XWL<14> ++ B_LBLC<14> B_LBLC<15> B_LBLT<14> B_LBLT<15> B_LWL<14> B_XWL<14> VDD_CORE ++ VSS VDD_CORE VSS / RM_IHPSG13_512x32_c2_2P_BITKIT_CELL +XCELL<13> A_LBLC<14> A_LBLC<13> A_LBLT<14> A_LBLT<13> A_LWL<13> A_XWL<13> ++ B_LBLC<14> B_LBLC<13> B_LBLT<14> B_LBLT<13> B_LWL<13> B_XWL<13> VDD_CORE ++ VSS VDD_CORE VSS / RM_IHPSG13_512x32_c2_2P_BITKIT_CELL +XCELL<12> A_LBLC<12> A_LBLC<13> A_LBLT<12> A_LBLT<13> A_LWL<12> A_XWL<12> ++ B_LBLC<12> B_LBLC<13> B_LBLT<12> B_LBLT<13> B_LWL<12> B_XWL<12> VDD_CORE ++ VSS VDD_CORE VSS / RM_IHPSG13_512x32_c2_2P_BITKIT_CELL +XCELL<11> A_LBLC<12> A_LBLC<11> A_LBLT<12> A_LBLT<11> A_LWL<11> A_XWL<11> ++ B_LBLC<12> B_LBLC<11> B_LBLT<12> B_LBLT<11> B_LWL<11> B_XWL<11> VDD_CORE ++ VSS VDD_CORE VSS / RM_IHPSG13_512x32_c2_2P_BITKIT_CELL +XCELL<10> A_LBLC<10> A_LBLC<11> A_LBLT<10> A_LBLT<11> A_LWL<10> A_XWL<10> ++ B_LBLC<10> B_LBLC<11> B_LBLT<10> B_LBLT<11> B_LWL<10> B_XWL<10> VDD_CORE ++ VSS VDD_CORE VSS / RM_IHPSG13_512x32_c2_2P_BITKIT_CELL +XCELL<9> A_LBLC<10> A_LBLC<9> A_LBLT<10> A_LBLT<9> A_LWL<9> A_XWL<9> ++ B_LBLC<10> B_LBLC<9> B_LBLT<10> B_LBLT<9> B_LWL<9> B_XWL<9> VDD_CORE ++ VSS VDD_CORE VSS / RM_IHPSG13_512x32_c2_2P_BITKIT_CELL +XCELL<8> A_LBLC<8> A_LBLC<9> A_LBLT<8> A_LBLT<9> A_LWL<8> A_XWL<8> B_LBLC<8> ++ B_LBLC<9> B_LBLT<8> B_LBLT<9> B_LWL<8> B_XWL<8> VDD_CORE VSS ++ VDD_CORE VSS / RM_IHPSG13_512x32_c2_2P_BITKIT_CELL +XCELL<7> A_LBLC<8> A_LBLC<7> A_LBLT<8> A_LBLT<7> A_LWL<7> A_XWL<7> B_LBLC<8> ++ B_LBLC<7> B_LBLT<8> B_LBLT<7> B_LWL<7> B_XWL<7> VDD_CORE VSS ++ VDD_CORE VSS / RM_IHPSG13_512x32_c2_2P_BITKIT_CELL +XCELL<6> A_LBLC<6> A_LBLC<7> A_LBLT<6> A_LBLT<7> A_LWL<6> A_XWL<6> B_LBLC<6> ++ B_LBLC<7> B_LBLT<6> B_LBLT<7> B_LWL<6> B_XWL<6> VDD_CORE VSS ++ VDD_CORE VSS / RM_IHPSG13_512x32_c2_2P_BITKIT_CELL +XCELL<5> A_LBLC<6> A_LBLC<5> A_LBLT<6> A_LBLT<5> A_LWL<5> A_XWL<5> B_LBLC<6> ++ B_LBLC<5> B_LBLT<6> B_LBLT<5> B_LWL<5> B_XWL<5> VDD_CORE VSS ++ VDD_CORE VSS / RM_IHPSG13_512x32_c2_2P_BITKIT_CELL +XCELL<4> A_LBLC<4> A_LBLC<5> A_LBLT<4> A_LBLT<5> A_LWL<4> A_XWL<4> B_LBLC<4> ++ B_LBLC<5> B_LBLT<4> B_LBLT<5> B_LWL<4> B_XWL<4> VDD_CORE VSS ++ VDD_CORE VSS / RM_IHPSG13_512x32_c2_2P_BITKIT_CELL +XCELL<3> A_LBLC<4> A_LBLC<3> A_LBLT<4> A_LBLT<3> A_LWL<3> A_XWL<3> B_LBLC<4> ++ B_LBLC<3> B_LBLT<4> B_LBLT<3> B_LWL<3> B_XWL<3> VDD_CORE VSS ++ VDD_CORE VSS / RM_IHPSG13_512x32_c2_2P_BITKIT_CELL +XCELL<2> A_LBLC<2> A_LBLC<3> A_LBLT<2> A_LBLT<3> A_LWL<2> A_XWL<2> B_LBLC<2> ++ B_LBLC<3> B_LBLT<2> B_LBLT<3> B_LWL<2> B_XWL<2> VDD_CORE VSS ++ VDD_CORE VSS / RM_IHPSG13_512x32_c2_2P_BITKIT_CELL +XCELL<1> A_LBLC<2> A_LBLC<1> A_LBLT<2> A_LBLT<1> A_LWL<1> A_XWL<1> B_LBLC<2> ++ B_LBLC<1> B_LBLT<2> B_LBLT<1> B_LWL<1> B_XWL<1> VDD_CORE VSS ++ VDD_CORE VSS / RM_IHPSG13_512x32_c2_2P_BITKIT_CELL +XCELL<0> A_BLC_BOT<0> A_LBLC<1> A_BLT_BOT<0> A_LBLT<1> A_LWL<0> A_XWL<0> ++ B_BLC_BOT<0> B_LBLC<1> B_BLT_BOT<0> B_LBLT<1> B_LWL<0> B_XWL<0> VDD_CORE ++ VSS VDD_CORE VSS / RM_IHPSG13_512x32_c2_2P_BITKIT_CELL +.ENDS +.SUBCKT RM_IHPSG13_512x32_c2_2P_BITKIT_EDGE_TB A_BLC A_BLT B_BLC B_BLT NW PW VDD VSS +.ENDS +.SUBCKT RM_IHPSG13_512x32_c2_2P_BITKIT_16x2_EDGE_TB A_BLC<1> A_BLC<0> A_BLT<1> A_BLT<0> ++ B_BLC<1> B_BLC<0> B_BLT<1> B_BLT<0> VDD_CORE VSS +XEDGE<1> A_BLC<1> A_BLT<1> B_BLC<1> B_BLT<1> VDD_CORE VSS ++ VDD_CORE VSS / RM_IHPSG13_512x32_c2_2P_BITKIT_EDGE_TB +XEDGE<0> A_BLC<0> A_BLT<0> B_BLC<0> B_BLT<0> VDD_CORE VSS ++ VDD_CORE VSS / RM_IHPSG13_512x32_c2_2P_BITKIT_EDGE_TB +.ENDS +.SUBCKT RM_IHPSG13_512x32_c2_2P_BITKIT_TAP A_BLC A_BLT B_BLC B_BLT NW PW VDD VSS +.ENDS +.SUBCKT RM_IHPSG13_512x32_c2_2P_BITKIT_16x2_TAP A_BLC<1> A_BLC<0> A_BLT<1> A_BLT<0> ++ B_BLC<1> B_BLC<0> B_BLT<1> B_BLT<0> VDD_CORE VSS +XIEDGEBP_COL1<1> A_BLC<1> A_BLT<1> B_BLC<1> B_BLT<1> VDD_CORE VSS ++ VDD_CORE VSS / RM_IHPSG13_512x32_c2_2P_BITKIT_EDGE_TB +XIEDGEBP_COL1<0> A_BLC<1> A_BLT<1> B_BLC<1> B_BLT<1> VDD_CORE VSS ++ VDD_CORE VSS / RM_IHPSG13_512x32_c2_2P_BITKIT_EDGE_TB +XIEDGEBP_COL2<1> A_BLC<0> A_BLT<0> B_BLC<0> B_BLT<0> VDD_CORE VSS ++ VDD_CORE VSS / RM_IHPSG13_512x32_c2_2P_BITKIT_EDGE_TB +XIEDGEBP_COL2<0> A_BLC<0> A_BLT<0> B_BLC<0> B_BLT<0> VDD_CORE VSS ++ VDD_CORE VSS / RM_IHPSG13_512x32_c2_2P_BITKIT_EDGE_TB +XITAP<1> A_BLC<1> A_BLT<1> B_BLC<1> B_BLT<1> VDD_CORE VSS ++ VDD_CORE VSS / RM_IHPSG13_512x32_c2_2P_BITKIT_TAP +XITAP<0> A_BLC<0> A_BLT<0> B_BLC<0> B_BLT<0> VDD_CORE VSS ++ VDD_CORE VSS / RM_IHPSG13_512x32_c2_2P_BITKIT_TAP +.ENDS + + +.SUBCKT RM_IHPSG13_512x32_c2_1P_BITKIT_TAP_LR NW PW VDD VSS +.ENDS +.SUBCKT RM_IHPSG13_512x32_c2_2P_BITKIT_16x2_TAP_LR VDD_CORE VSS +XCORNER<1> VDD_CORE VSS VDD_CORE VSS / ++ RM_IHPSG13_512x32_c2_1P_BITKIT_CORNER +XCORNER<0> VDD_CORE VSS VDD_CORE VSS / ++ RM_IHPSG13_512x32_c2_1P_BITKIT_CORNER +XTAP_BORDER VDD_CORE VSS VDD_CORE VSS / ++ RM_IHPSG13_512x32_c2_1P_BITKIT_TAP_LR +.ENDS + +.SUBCKT RSC_IHPSG13_CBUFX12 A Z VDD VSS +MN1 Z net6 VSS VSS sg13_lv_nmos m=1 w=4.23u l=130.00n ng=6 nrd=0 nrs=0 +MN0 net6 A VSS VSS sg13_lv_nmos m=1 w=1.41u l=130.00n ng=2 nrd=0 nrs=0 +MP1 Z net6 VDD VDD sg13_lv_pmos m=1 w=9.72u l=130.00n ng=6 nrd=0 nrs=0 +MP0 net6 A VDD VDD sg13_lv_pmos m=1 w=3.24u l=130.00n ng=2 nrd=0 nrs=0 +.ENDS +.SUBCKT RM_IHPSG13_512x32_c2_2P_COLDRV13X12 ADDR_COL_I<1> ADDR_COL_I<0> ADDR_COL_O<1> ++ ADDR_COL_O<0> ADDR_DEC_I<7> ADDR_DEC_I<6> ADDR_DEC_I<5> ADDR_DEC_I<4> ++ ADDR_DEC_I<3> ADDR_DEC_I<2> ADDR_DEC_I<1> ADDR_DEC_I<0> ADDR_DEC_O<7> ++ ADDR_DEC_O<6> ADDR_DEC_O<5> ADDR_DEC_O<4> ADDR_DEC_O<3> ADDR_DEC_O<2> ++ ADDR_DEC_O<1> ADDR_DEC_O<0> DCLK_I DCLK_O RCLK_I RCLK_O WCLK_I WCLK_O ++ VDD VSS +XI1<3> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI1<2> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI1<1> VDD VSS / RSC_IHPSG13_FILLCAP8 +XWCLK_DRV WCLK_I WCLK_O VDD VSS / RSC_IHPSG13_CBUFX12 +XRCLK_DRV RCLK_I RCLK_O VDD VSS / RSC_IHPSG13_CBUFX12 +XDCLK_DRV DCLK_I DCLK_O VDD VSS / RSC_IHPSG13_CBUFX12 +XADDR_COL_DRV<1> ADDR_COL_I<1> ADDR_COL_O<1> VDD VSS / ++ RSC_IHPSG13_CBUFX12 +XADDR_COL_DRV<0> ADDR_COL_I<0> ADDR_COL_O<0> VDD VSS / ++ RSC_IHPSG13_CBUFX12 +XADDR_DEC_DRV<7> ADDR_DEC_I<7> ADDR_DEC_O<7> VDD VSS / ++ RSC_IHPSG13_CBUFX12 +XADDR_DEC_DRV<6> ADDR_DEC_I<6> ADDR_DEC_O<6> VDD VSS / ++ RSC_IHPSG13_CBUFX12 +XADDR_DEC_DRV<5> ADDR_DEC_I<5> ADDR_DEC_O<5> VDD VSS / ++ RSC_IHPSG13_CBUFX12 +XADDR_DEC_DRV<4> ADDR_DEC_I<4> ADDR_DEC_O<4> VDD VSS / ++ RSC_IHPSG13_CBUFX12 +XADDR_DEC_DRV<3> ADDR_DEC_I<3> ADDR_DEC_O<3> VDD VSS / ++ RSC_IHPSG13_CBUFX12 +XADDR_DEC_DRV<2> ADDR_DEC_I<2> ADDR_DEC_O<2> VDD VSS / ++ RSC_IHPSG13_CBUFX12 +XADDR_DEC_DRV<1> ADDR_DEC_I<1> ADDR_DEC_O<1> VDD VSS / ++ RSC_IHPSG13_CBUFX12 +XADDR_DEC_DRV<0> ADDR_DEC_I<0> ADDR_DEC_O<0> VDD VSS / ++ RSC_IHPSG13_CBUFX12 +XI0<6> VDD VSS / RSC_IHPSG13_FILLCAP4 +XI0<5> VDD VSS / RSC_IHPSG13_FILLCAP4 +XI0<4> VDD VSS / RSC_IHPSG13_FILLCAP4 +XI0<3> VDD VSS / RSC_IHPSG13_FILLCAP4 +XI0<2> VDD VSS / RSC_IHPSG13_FILLCAP4 +XI0<1> VDD VSS / RSC_IHPSG13_FILLCAP4 +.ENDS +.SUBCKT RSC_IHPSG13_WLDRVX12 A Z VDD VSS +MN1 Z net6 VSS VSS sg13_lv_nmos m=1 w=1.41u l=130.00n ng=2 nrd=0 nrs=0 +MN0 net6 A VSS VSS sg13_lv_nmos m=1 w=1.8u l=130.00n ng=2 nrd=0 nrs=0 +MP1 Z net6 VDD VDD sg13_lv_pmos m=1 w=9.72u l=130.00n ng=6 nrd=0 nrs=0 +MP0 net6 A VDD VDD sg13_lv_pmos m=1 w=900.0n l=130.00n ng=1 nrd=0 nrs=0 +.ENDS +.SUBCKT RM_IHPSG13_512x32_c2_2P_WLDRV16X12 A<15> A<14> A<13> A<12> A<11> A<10> A<9> A<8> ++ A<7> A<6> A<5> A<4> A<3> A<2> A<1> A<0> Z<15> Z<14> Z<13> Z<12> Z<11> Z<10> ++ Z<9> Z<8> Z<7> Z<6> Z<5> Z<4> Z<3> Z<2> Z<1> Z<0> VDD VSS +XBUF<15> A<15> Z<15> VDD VSS / RSC_IHPSG13_WLDRVX12 +XBUF<14> A<14> Z<14> VDD VSS / RSC_IHPSG13_WLDRVX12 +XBUF<13> A<13> Z<13> VDD VSS / RSC_IHPSG13_WLDRVX12 +XBUF<12> A<12> Z<12> VDD VSS / RSC_IHPSG13_WLDRVX12 +XBUF<11> A<11> Z<11> VDD VSS / RSC_IHPSG13_WLDRVX12 +XBUF<10> A<10> Z<10> VDD VSS / RSC_IHPSG13_WLDRVX12 +XBUF<9> A<9> Z<9> VDD VSS / RSC_IHPSG13_WLDRVX12 +XBUF<8> A<8> Z<8> VDD VSS / RSC_IHPSG13_WLDRVX12 +XBUF<7> A<7> Z<7> VDD VSS / RSC_IHPSG13_WLDRVX12 +XBUF<6> A<6> Z<6> VDD VSS / RSC_IHPSG13_WLDRVX12 +XBUF<5> A<5> Z<5> VDD VSS / RSC_IHPSG13_WLDRVX12 +XBUF<4> A<4> Z<4> VDD VSS / RSC_IHPSG13_WLDRVX12 +XBUF<3> A<3> Z<3> VDD VSS / RSC_IHPSG13_WLDRVX12 +XBUF<2> A<2> Z<2> VDD VSS / RSC_IHPSG13_WLDRVX12 +XBUF<1> A<1> Z<1> VDD VSS / RSC_IHPSG13_WLDRVX12 +XBUF<0> A<0> Z<0> VDD VSS / RSC_IHPSG13_WLDRVX12 +.ENDS +.SUBCKT RM_IHPSG13_512x32_c2_2P_DEC04 ADDR<3> ADDR<2> ADDR<1> ADDR<0> CS ECLK_H_BOT ++ ECLK_H_TOP ECLK_L_BOT ECLK_L_TOP WL<15> WL<14> WL<13> WL<12> WL<11> WL<10> ++ WL<9> WL<8> WL<7> WL<6> WL<5> WL<4> WL<3> WL<2> WL<1> WL<0> VDD VSS +XI0<3> PADR<1> PADR<0> sel01<3> VDD VSS / RSC_IHPSG13_NAND2X2 +XI0<2> PADR<1> NADR<0> sel01<2> VDD VSS / RSC_IHPSG13_NAND2X2 +XI0<1> NADR<1> PADR<0> sel01<1> VDD VSS / RSC_IHPSG13_NAND2X2 +XI0<0> NADR<1> NADR<0> sel01<0> VDD VSS / RSC_IHPSG13_NAND2X2 +XI4 ECLK_L_BOT EN VDD VSS / RSC_IHPSG13_CINVX4 +XI5 ECLK_H_BOT ECLK_L_BOT VDD VSS / RSC_IHPSG13_CINVX2 +XI3<3> PADR<3> NADR<3> VDD VSS / RSC_IHPSG13_INVX2 +XI3<2> PADR<2> NADR<2> VDD VSS / RSC_IHPSG13_INVX2 +XI3<1> PADR<1> NADR<1> VDD VSS / RSC_IHPSG13_INVX2 +XI3<0> PADR<0> NADR<0> VDD VSS / RSC_IHPSG13_INVX2 +XR0 ECLK_H_BOT ECLK_H_TOP / RSC_IHPSG13_MET2RES +XI11 ECLK_L_BOT ECLK_L_TOP / RSC_IHPSG13_MET2RES +XI1<3> PADR<2> PADR<3> CS sel23<3> VDD VSS / RSC_IHPSG13_NAND3X2 +XI1<2> NADR<2> PADR<3> CS sel23<2> VDD VSS / RSC_IHPSG13_NAND3X2 +XI1<1> PADR<2> NADR<3> CS sel23<1> VDD VSS / RSC_IHPSG13_NAND3X2 +XI1<0> NADR<2> NADR<3> CS sel23<0> VDD VSS / RSC_IHPSG13_NAND3X2 +XI2<15> sel23<3> sel01<3> EN WL<15> VDD VSS / RSC_IHPSG13_NOR3X2 +XI2<14> sel23<3> sel01<2> EN WL<14> VDD VSS / RSC_IHPSG13_NOR3X2 +XI2<13> sel23<3> sel01<1> EN WL<13> VDD VSS / RSC_IHPSG13_NOR3X2 +XI2<12> sel23<3> sel01<0> EN WL<12> VDD VSS / RSC_IHPSG13_NOR3X2 +XI2<11> sel23<2> sel01<3> EN WL<11> VDD VSS / RSC_IHPSG13_NOR3X2 +XI2<10> sel23<2> sel01<2> EN WL<10> VDD VSS / RSC_IHPSG13_NOR3X2 +XI2<9> sel23<2> sel01<1> EN WL<9> VDD VSS / RSC_IHPSG13_NOR3X2 +XI2<8> sel23<2> sel01<0> EN WL<8> VDD VSS / RSC_IHPSG13_NOR3X2 +XI2<7> sel23<1> sel01<3> EN WL<7> VDD VSS / RSC_IHPSG13_NOR3X2 +XI2<6> sel23<1> sel01<2> EN WL<6> VDD VSS / RSC_IHPSG13_NOR3X2 +XI2<5> sel23<1> sel01<1> EN WL<5> VDD VSS / RSC_IHPSG13_NOR3X2 +XI2<4> sel23<1> sel01<0> EN WL<4> VDD VSS / RSC_IHPSG13_NOR3X2 +XI2<3> sel23<0> sel01<3> EN WL<3> VDD VSS / RSC_IHPSG13_NOR3X2 +XI2<2> sel23<0> sel01<2> EN WL<2> VDD VSS / RSC_IHPSG13_NOR3X2 +XI2<1> sel23<0> sel01<1> EN WL<1> VDD VSS / RSC_IHPSG13_NOR3X2 +XI2<0> sel23<0> sel01<0> EN WL<0> VDD VSS / RSC_IHPSG13_NOR3X2 +XCAPS4 VDD VSS / RSC_IHPSG13_FILLCAP4 +XLATCH<3> CS ADDR<3> PADR<3> VDD VSS / RSC_IHPSG13_LHPQX2 +XLATCH<2> CS ADDR<2> PADR<2> VDD VSS / RSC_IHPSG13_LHPQX2 +XLATCH<1> CS ADDR<1> PADR<1> VDD VSS / RSC_IHPSG13_LHPQX2 +XLATCH<0> CS ADDR<0> PADR<0> VDD VSS / RSC_IHPSG13_LHPQX2 +.ENDS +.SUBCKT RM_IHPSG13_512x32_c2_2P_DEC02 ADDR<1> ADDR<0> CS CS_OUT VDD VSS +XDEC ADDR<1> NADDR<0> CS net1 VDD VSS / RSC_IHPSG13_NAND3X2 +XADDRINV ADDR<0> NADDR<0> VDD VSS / RSC_IHPSG13_INVX2 +XDECINV net1 CS_OUT VDD VSS / RSC_IHPSG13_INVX4 +XI2<1> VDD VSS / RSC_IHPSG13_FILLCAP4 +XI2<0> VDD VSS / RSC_IHPSG13_FILLCAP4 +.ENDS +.SUBCKT RM_IHPSG13_512x32_c2_2P_DEC01 ADDR<1> ADDR<0> CS CS_OUT VDD VSS +XDEC NADDR<1> ADDR<0> CS net1 VDD VSS / RSC_IHPSG13_NAND3X2 +XADDRINV ADDR<1> NADDR<1> VDD VSS / RSC_IHPSG13_INVX2 +XDECINV net1 CS_OUT VDD VSS / RSC_IHPSG13_INVX4 +XI2<1> VDD VSS / RSC_IHPSG13_FILLCAP4 +XI2<0> VDD VSS / RSC_IHPSG13_FILLCAP4 +.ENDS +.SUBCKT RM_IHPSG13_512x32_c2_2P_DEC00 ADDR<1> ADDR<0> CS CS_OUT VDD VSS +XDEC NADDR<1> NADDR<0> CS net1 VDD VSS / RSC_IHPSG13_NAND3X2 +XADDRINV<1> ADDR<1> NADDR<1> VDD VSS / RSC_IHPSG13_INVX2 +XADDRINV<0> ADDR<0> NADDR<0> VDD VSS / RSC_IHPSG13_INVX2 +XI1<1> VDD VSS / RSC_IHPSG13_FILLCAP4 +XI1<0> VDD VSS / RSC_IHPSG13_FILLCAP4 +XDECINV net1 CS_OUT VDD VSS / RSC_IHPSG13_INVX4 +.ENDS +.SUBCKT RM_IHPSG13_512x32_c2_2P_DEC03 ADDR<1> ADDR<0> CS CS_OUT VDD VSS +XDEC ADDR<1> ADDR<0> CS net1 VDD VSS / RSC_IHPSG13_NAND3X2 +XDECINV net1 CS_OUT VDD VSS / RSC_IHPSG13_INVX4 +XI0<1> VDD VSS / RSC_IHPSG13_FILLCAP4 +XI0<0> VDD VSS / RSC_IHPSG13_FILLCAP4 +.ENDS +.SUBCKT RM_IHPSG13_512x32_c2_2P_ROWDEC9 ADDR_N_I<8> ADDR_N_I<7> ADDR_N_I<6> ADDR_N_I<5> ++ ADDR_N_I<4> ADDR_N_I<3> ADDR_N_I<2> ADDR_N_I<1> ADDR_N_I<0> CS_I ECLK_I ++ WL_O<511> WL_O<510> WL_O<509> WL_O<508> WL_O<507> WL_O<506> WL_O<505> ++ WL_O<504> WL_O<503> WL_O<502> WL_O<501> WL_O<500> WL_O<499> WL_O<498> ++ WL_O<497> WL_O<496> WL_O<495> WL_O<494> WL_O<493> WL_O<492> WL_O<491> ++ WL_O<490> WL_O<489> WL_O<488> WL_O<487> WL_O<486> WL_O<485> WL_O<484> ++ WL_O<483> WL_O<482> WL_O<481> WL_O<480> WL_O<479> WL_O<478> WL_O<477> ++ WL_O<476> WL_O<475> WL_O<474> WL_O<473> WL_O<472> WL_O<471> WL_O<470> ++ WL_O<469> WL_O<468> WL_O<467> WL_O<466> WL_O<465> WL_O<464> WL_O<463> ++ WL_O<462> WL_O<461> WL_O<460> WL_O<459> WL_O<458> WL_O<457> WL_O<456> ++ WL_O<455> WL_O<454> WL_O<453> WL_O<452> WL_O<451> WL_O<450> WL_O<449> ++ WL_O<448> WL_O<447> WL_O<446> WL_O<445> WL_O<444> WL_O<443> WL_O<442> ++ WL_O<441> WL_O<440> WL_O<439> WL_O<438> WL_O<437> WL_O<436> WL_O<435> ++ WL_O<434> WL_O<433> WL_O<432> WL_O<431> WL_O<430> WL_O<429> WL_O<428> ++ WL_O<427> WL_O<426> WL_O<425> WL_O<424> WL_O<423> WL_O<422> WL_O<421> ++ WL_O<420> WL_O<419> WL_O<418> WL_O<417> WL_O<416> WL_O<415> WL_O<414> ++ WL_O<413> WL_O<412> WL_O<411> WL_O<410> WL_O<409> WL_O<408> WL_O<407> ++ WL_O<406> WL_O<405> WL_O<404> WL_O<403> WL_O<402> WL_O<401> WL_O<400> ++ WL_O<399> WL_O<398> WL_O<397> WL_O<396> WL_O<395> WL_O<394> WL_O<393> ++ WL_O<392> WL_O<391> WL_O<390> WL_O<389> WL_O<388> WL_O<387> WL_O<386> ++ WL_O<385> WL_O<384> WL_O<383> WL_O<382> WL_O<381> WL_O<380> WL_O<379> ++ WL_O<378> WL_O<377> WL_O<376> WL_O<375> WL_O<374> WL_O<373> WL_O<372> ++ WL_O<371> WL_O<370> WL_O<369> WL_O<368> WL_O<367> WL_O<366> WL_O<365> ++ WL_O<364> WL_O<363> WL_O<362> WL_O<361> WL_O<360> WL_O<359> WL_O<358> ++ WL_O<357> WL_O<356> WL_O<355> WL_O<354> WL_O<353> WL_O<352> WL_O<351> ++ WL_O<350> WL_O<349> WL_O<348> WL_O<347> WL_O<346> WL_O<345> WL_O<344> ++ WL_O<343> WL_O<342> WL_O<341> WL_O<340> WL_O<339> WL_O<338> WL_O<337> ++ WL_O<336> WL_O<335> WL_O<334> WL_O<333> WL_O<332> WL_O<331> WL_O<330> ++ WL_O<329> WL_O<328> WL_O<327> WL_O<326> WL_O<325> WL_O<324> WL_O<323> ++ WL_O<322> WL_O<321> WL_O<320> WL_O<319> WL_O<318> WL_O<317> WL_O<316> ++ WL_O<315> WL_O<314> WL_O<313> WL_O<312> WL_O<311> WL_O<310> WL_O<309> ++ WL_O<308> WL_O<307> WL_O<306> WL_O<305> WL_O<304> WL_O<303> WL_O<302> ++ WL_O<301> WL_O<300> WL_O<299> WL_O<298> WL_O<297> WL_O<296> WL_O<295> ++ WL_O<294> WL_O<293> WL_O<292> WL_O<291> WL_O<290> WL_O<289> WL_O<288> ++ WL_O<287> WL_O<286> WL_O<285> WL_O<284> WL_O<283> WL_O<282> WL_O<281> ++ WL_O<280> WL_O<279> WL_O<278> WL_O<277> WL_O<276> WL_O<275> WL_O<274> ++ WL_O<273> WL_O<272> WL_O<271> WL_O<270> WL_O<269> WL_O<268> WL_O<267> ++ WL_O<266> WL_O<265> WL_O<264> WL_O<263> WL_O<262> WL_O<261> WL_O<260> ++ WL_O<259> WL_O<258> WL_O<257> WL_O<256> WL_O<255> WL_O<254> WL_O<253> ++ WL_O<252> WL_O<251> WL_O<250> WL_O<249> WL_O<248> WL_O<247> WL_O<246> ++ WL_O<245> WL_O<244> WL_O<243> WL_O<242> WL_O<241> WL_O<240> WL_O<239> ++ WL_O<238> WL_O<237> WL_O<236> WL_O<235> WL_O<234> WL_O<233> WL_O<232> ++ WL_O<231> WL_O<230> WL_O<229> WL_O<228> WL_O<227> WL_O<226> WL_O<225> ++ WL_O<224> WL_O<223> WL_O<222> WL_O<221> WL_O<220> WL_O<219> WL_O<218> ++ WL_O<217> WL_O<216> WL_O<215> WL_O<214> WL_O<213> WL_O<212> WL_O<211> ++ WL_O<210> WL_O<209> WL_O<208> WL_O<207> WL_O<206> WL_O<205> WL_O<204> ++ WL_O<203> WL_O<202> WL_O<201> WL_O<200> WL_O<199> WL_O<198> WL_O<197> ++ WL_O<196> WL_O<195> WL_O<194> WL_O<193> WL_O<192> WL_O<191> WL_O<190> ++ WL_O<189> WL_O<188> WL_O<187> WL_O<186> WL_O<185> WL_O<184> WL_O<183> ++ WL_O<182> WL_O<181> WL_O<180> WL_O<179> WL_O<178> WL_O<177> WL_O<176> ++ WL_O<175> WL_O<174> WL_O<173> WL_O<172> WL_O<171> WL_O<170> WL_O<169> ++ WL_O<168> WL_O<167> WL_O<166> WL_O<165> WL_O<164> WL_O<163> WL_O<162> ++ WL_O<161> WL_O<160> WL_O<159> WL_O<158> WL_O<157> WL_O<156> WL_O<155> ++ WL_O<154> WL_O<153> WL_O<152> WL_O<151> WL_O<150> WL_O<149> WL_O<148> ++ WL_O<147> WL_O<146> WL_O<145> WL_O<144> WL_O<143> WL_O<142> WL_O<141> ++ WL_O<140> WL_O<139> WL_O<138> WL_O<137> WL_O<136> WL_O<135> WL_O<134> ++ WL_O<133> WL_O<132> WL_O<131> WL_O<130> WL_O<129> WL_O<128> WL_O<127> ++ WL_O<126> WL_O<125> WL_O<124> WL_O<123> WL_O<122> WL_O<121> WL_O<120> ++ WL_O<119> WL_O<118> WL_O<117> WL_O<116> WL_O<115> WL_O<114> WL_O<113> ++ WL_O<112> WL_O<111> WL_O<110> WL_O<109> WL_O<108> WL_O<107> WL_O<106> ++ WL_O<105> WL_O<104> WL_O<103> WL_O<102> WL_O<101> WL_O<100> WL_O<99> ++ WL_O<98> WL_O<97> WL_O<96> WL_O<95> WL_O<94> WL_O<93> WL_O<92> WL_O<91> ++ WL_O<90> WL_O<89> WL_O<88> WL_O<87> WL_O<86> WL_O<85> WL_O<84> WL_O<83> ++ WL_O<82> WL_O<81> WL_O<80> WL_O<79> WL_O<78> WL_O<77> WL_O<76> WL_O<75> ++ WL_O<74> WL_O<73> WL_O<72> WL_O<71> WL_O<70> WL_O<69> WL_O<68> WL_O<67> ++ WL_O<66> WL_O<65> WL_O<64> WL_O<63> WL_O<62> WL_O<61> WL_O<60> WL_O<59> ++ WL_O<58> WL_O<57> WL_O<56> WL_O<55> WL_O<54> WL_O<53> WL_O<52> WL_O<51> ++ WL_O<50> WL_O<49> WL_O<48> WL_O<47> WL_O<46> WL_O<45> WL_O<44> WL_O<43> ++ WL_O<42> WL_O<41> WL_O<40> WL_O<39> WL_O<38> WL_O<37> WL_O<36> WL_O<35> ++ WL_O<34> WL_O<33> WL_O<32> WL_O<31> WL_O<30> WL_O<29> WL_O<28> WL_O<27> ++ WL_O<26> WL_O<25> WL_O<24> WL_O<23> WL_O<22> WL_O<21> WL_O<20> WL_O<19> ++ WL_O<18> WL_O<17> WL_O<16> WL_O<15> WL_O<14> WL_O<13> WL_O<12> WL_O<11> ++ WL_O<10> WL_O<9> WL_O<8> WL_O<7> WL_O<6> WL_O<5> WL_O<4> WL_O<3> WL_O<2> ++ WL_O<1> WL_O<0> VDD VSS +XSEL<31> ADDR_N_I<3> ADDR_N_I<2> ADDR_N_I<1> ADDR_N_I<0> CS00<31> ECLK_H<31> ++ ECLK_H<32> ECLK_B<31> ECLK_B<32> WL_O<511> WL_O<510> WL_O<509> WL_O<508> ++ WL_O<507> WL_O<506> WL_O<505> WL_O<504> WL_O<503> WL_O<502> WL_O<501> ++ WL_O<500> WL_O<499> WL_O<498> WL_O<497> WL_O<496> VDD VSS / ++ RM_IHPSG13_512x32_c2_2P_DEC04 +XSEL<30> ADDR_N_I<3> ADDR_N_I<2> ADDR_N_I<1> ADDR_N_I<0> CS00<30> ECLK_H<30> ++ ECLK_H<31> ECLK_B<30> ECLK_B<31> WL_O<495> WL_O<494> WL_O<493> WL_O<492> ++ WL_O<491> WL_O<490> WL_O<489> WL_O<488> WL_O<487> WL_O<486> WL_O<485> ++ WL_O<484> WL_O<483> WL_O<482> WL_O<481> WL_O<480> VDD VSS / ++ RM_IHPSG13_512x32_c2_2P_DEC04 +XSEL<29> ADDR_N_I<3> ADDR_N_I<2> ADDR_N_I<1> ADDR_N_I<0> CS00<29> ECLK_H<29> ++ ECLK_H<30> ECLK_B<29> ECLK_B<30> WL_O<479> WL_O<478> WL_O<477> WL_O<476> ++ WL_O<475> WL_O<474> WL_O<473> WL_O<472> WL_O<471> WL_O<470> WL_O<469> ++ WL_O<468> WL_O<467> WL_O<466> WL_O<465> WL_O<464> VDD VSS / ++ RM_IHPSG13_512x32_c2_2P_DEC04 +XSEL<28> ADDR_N_I<3> ADDR_N_I<2> ADDR_N_I<1> ADDR_N_I<0> CS00<28> ECLK_H<28> ++ ECLK_H<29> ECLK_B<28> ECLK_B<29> WL_O<463> WL_O<462> WL_O<461> WL_O<460> ++ WL_O<459> WL_O<458> WL_O<457> WL_O<456> WL_O<455> WL_O<454> WL_O<453> ++ WL_O<452> WL_O<451> WL_O<450> WL_O<449> WL_O<448> VDD VSS / ++ RM_IHPSG13_512x32_c2_2P_DEC04 +XSEL<27> ADDR_N_I<3> ADDR_N_I<2> ADDR_N_I<1> ADDR_N_I<0> CS00<27> ECLK_H<27> ++ ECLK_H<28> ECLK_B<27> ECLK_B<28> WL_O<447> WL_O<446> WL_O<445> WL_O<444> ++ WL_O<443> WL_O<442> WL_O<441> WL_O<440> WL_O<439> WL_O<438> WL_O<437> ++ WL_O<436> WL_O<435> WL_O<434> WL_O<433> WL_O<432> VDD VSS / ++ RM_IHPSG13_512x32_c2_2P_DEC04 +XSEL<26> ADDR_N_I<3> ADDR_N_I<2> ADDR_N_I<1> ADDR_N_I<0> CS00<26> ECLK_H<26> ++ ECLK_H<27> ECLK_B<26> ECLK_B<27> WL_O<431> WL_O<430> WL_O<429> WL_O<428> ++ WL_O<427> WL_O<426> WL_O<425> WL_O<424> WL_O<423> WL_O<422> WL_O<421> ++ WL_O<420> WL_O<419> WL_O<418> WL_O<417> WL_O<416> VDD VSS / ++ RM_IHPSG13_512x32_c2_2P_DEC04 +XSEL<25> ADDR_N_I<3> ADDR_N_I<2> ADDR_N_I<1> ADDR_N_I<0> CS00<25> ECLK_H<25> ++ ECLK_H<26> ECLK_B<25> ECLK_B<26> WL_O<415> WL_O<414> WL_O<413> WL_O<412> ++ WL_O<411> WL_O<410> WL_O<409> WL_O<408> WL_O<407> WL_O<406> WL_O<405> ++ WL_O<404> WL_O<403> WL_O<402> WL_O<401> WL_O<400> VDD VSS / ++ RM_IHPSG13_512x32_c2_2P_DEC04 +XSEL<24> ADDR_N_I<3> ADDR_N_I<2> ADDR_N_I<1> ADDR_N_I<0> CS00<24> ECLK_H<24> ++ ECLK_H<25> ECLK_B<24> ECLK_B<25> WL_O<399> WL_O<398> WL_O<397> WL_O<396> ++ WL_O<395> WL_O<394> WL_O<393> WL_O<392> WL_O<391> WL_O<390> WL_O<389> ++ WL_O<388> WL_O<387> WL_O<386> WL_O<385> WL_O<384> VDD VSS / ++ RM_IHPSG13_512x32_c2_2P_DEC04 +XSEL<23> ADDR_N_I<3> ADDR_N_I<2> ADDR_N_I<1> ADDR_N_I<0> CS00<23> ECLK_H<23> ++ ECLK_H<24> ECLK_B<23> ECLK_B<24> WL_O<383> WL_O<382> WL_O<381> WL_O<380> ++ WL_O<379> WL_O<378> WL_O<377> WL_O<376> WL_O<375> WL_O<374> WL_O<373> ++ WL_O<372> WL_O<371> WL_O<370> WL_O<369> WL_O<368> VDD VSS / ++ RM_IHPSG13_512x32_c2_2P_DEC04 +XSEL<22> ADDR_N_I<3> ADDR_N_I<2> ADDR_N_I<1> ADDR_N_I<0> CS00<22> ECLK_H<22> ++ ECLK_H<23> ECLK_B<22> ECLK_B<23> WL_O<367> WL_O<366> WL_O<365> WL_O<364> ++ WL_O<363> WL_O<362> WL_O<361> WL_O<360> WL_O<359> WL_O<358> WL_O<357> ++ WL_O<356> WL_O<355> WL_O<354> WL_O<353> WL_O<352> VDD VSS / ++ RM_IHPSG13_512x32_c2_2P_DEC04 +XSEL<21> ADDR_N_I<3> ADDR_N_I<2> ADDR_N_I<1> ADDR_N_I<0> CS00<21> ECLK_H<21> ++ ECLK_H<22> ECLK_B<21> ECLK_B<22> WL_O<351> WL_O<350> WL_O<349> WL_O<348> ++ WL_O<347> WL_O<346> WL_O<345> WL_O<344> WL_O<343> WL_O<342> WL_O<341> ++ WL_O<340> WL_O<339> WL_O<338> WL_O<337> WL_O<336> VDD VSS / ++ RM_IHPSG13_512x32_c2_2P_DEC04 +XSEL<20> ADDR_N_I<3> ADDR_N_I<2> ADDR_N_I<1> ADDR_N_I<0> CS00<20> ECLK_H<20> ++ ECLK_H<21> ECLK_B<20> ECLK_B<21> WL_O<335> WL_O<334> WL_O<333> WL_O<332> ++ WL_O<331> WL_O<330> WL_O<329> WL_O<328> WL_O<327> WL_O<326> WL_O<325> ++ WL_O<324> WL_O<323> WL_O<322> WL_O<321> WL_O<320> VDD VSS / ++ RM_IHPSG13_512x32_c2_2P_DEC04 +XSEL<19> ADDR_N_I<3> ADDR_N_I<2> ADDR_N_I<1> ADDR_N_I<0> CS00<19> ECLK_H<19> ++ ECLK_H<20> ECLK_B<19> ECLK_B<20> WL_O<319> WL_O<318> WL_O<317> WL_O<316> ++ WL_O<315> WL_O<314> WL_O<313> WL_O<312> WL_O<311> WL_O<310> WL_O<309> ++ WL_O<308> WL_O<307> WL_O<306> WL_O<305> WL_O<304> VDD VSS / ++ RM_IHPSG13_512x32_c2_2P_DEC04 +XSEL<18> ADDR_N_I<3> ADDR_N_I<2> ADDR_N_I<1> ADDR_N_I<0> CS00<18> ECLK_H<18> ++ ECLK_H<19> ECLK_B<18> ECLK_B<19> WL_O<303> WL_O<302> WL_O<301> WL_O<300> ++ WL_O<299> WL_O<298> WL_O<297> WL_O<296> WL_O<295> WL_O<294> WL_O<293> ++ WL_O<292> WL_O<291> WL_O<290> WL_O<289> WL_O<288> VDD VSS / ++ RM_IHPSG13_512x32_c2_2P_DEC04 +XSEL<17> ADDR_N_I<3> ADDR_N_I<2> ADDR_N_I<1> ADDR_N_I<0> CS00<17> ECLK_H<17> ++ ECLK_H<18> ECLK_B<17> ECLK_B<18> WL_O<287> WL_O<286> WL_O<285> WL_O<284> ++ WL_O<283> WL_O<282> WL_O<281> WL_O<280> WL_O<279> WL_O<278> WL_O<277> ++ WL_O<276> WL_O<275> WL_O<274> WL_O<273> WL_O<272> VDD VSS / ++ RM_IHPSG13_512x32_c2_2P_DEC04 +XSEL<16> ADDR_N_I<3> ADDR_N_I<2> ADDR_N_I<1> ADDR_N_I<0> CS00<16> ECLK_H<16> ++ ECLK_H<17> ECLK_B<16> ECLK_B<17> WL_O<271> WL_O<270> WL_O<269> WL_O<268> ++ WL_O<267> WL_O<266> WL_O<265> WL_O<264> WL_O<263> WL_O<262> WL_O<261> ++ WL_O<260> WL_O<259> WL_O<258> WL_O<257> WL_O<256> VDD VSS / ++ RM_IHPSG13_512x32_c2_2P_DEC04 +XSEL<15> ADDR_N_I<3> ADDR_N_I<2> ADDR_N_I<1> ADDR_N_I<0> CS00<15> ECLK_H<15> ++ ECLK_H<16> ECLK_B<15> ECLK_B<16> WL_O<255> WL_O<254> WL_O<253> WL_O<252> ++ WL_O<251> WL_O<250> WL_O<249> WL_O<248> WL_O<247> WL_O<246> WL_O<245> ++ WL_O<244> WL_O<243> WL_O<242> WL_O<241> WL_O<240> VDD VSS / ++ RM_IHPSG13_512x32_c2_2P_DEC04 +XSEL<14> ADDR_N_I<3> ADDR_N_I<2> ADDR_N_I<1> ADDR_N_I<0> CS00<14> ECLK_H<14> ++ ECLK_H<15> ECLK_B<14> ECLK_B<15> WL_O<239> WL_O<238> WL_O<237> WL_O<236> ++ WL_O<235> WL_O<234> WL_O<233> WL_O<232> WL_O<231> WL_O<230> WL_O<229> ++ WL_O<228> WL_O<227> WL_O<226> WL_O<225> WL_O<224> VDD VSS / ++ RM_IHPSG13_512x32_c2_2P_DEC04 +XSEL<13> ADDR_N_I<3> ADDR_N_I<2> ADDR_N_I<1> ADDR_N_I<0> CS00<13> ECLK_H<13> ++ ECLK_H<14> ECLK_B<13> ECLK_B<14> WL_O<223> WL_O<222> WL_O<221> WL_O<220> ++ WL_O<219> WL_O<218> WL_O<217> WL_O<216> WL_O<215> WL_O<214> WL_O<213> ++ WL_O<212> WL_O<211> WL_O<210> WL_O<209> WL_O<208> VDD VSS / ++ RM_IHPSG13_512x32_c2_2P_DEC04 +XSEL<12> ADDR_N_I<3> ADDR_N_I<2> ADDR_N_I<1> ADDR_N_I<0> CS00<12> ECLK_H<12> ++ ECLK_H<13> ECLK_B<12> ECLK_B<13> WL_O<207> WL_O<206> WL_O<205> WL_O<204> ++ WL_O<203> WL_O<202> WL_O<201> WL_O<200> WL_O<199> WL_O<198> WL_O<197> ++ WL_O<196> WL_O<195> WL_O<194> WL_O<193> WL_O<192> VDD VSS / ++ RM_IHPSG13_512x32_c2_2P_DEC04 +XSEL<11> ADDR_N_I<3> ADDR_N_I<2> ADDR_N_I<1> ADDR_N_I<0> CS00<11> ECLK_H<11> ++ ECLK_H<12> ECLK_B<11> ECLK_B<12> WL_O<191> WL_O<190> WL_O<189> WL_O<188> ++ WL_O<187> WL_O<186> WL_O<185> WL_O<184> WL_O<183> WL_O<182> WL_O<181> ++ WL_O<180> WL_O<179> WL_O<178> WL_O<177> WL_O<176> VDD VSS / ++ RM_IHPSG13_512x32_c2_2P_DEC04 +XSEL<10> ADDR_N_I<3> ADDR_N_I<2> ADDR_N_I<1> ADDR_N_I<0> CS00<10> ECLK_H<10> ++ ECLK_H<11> ECLK_B<10> ECLK_B<11> WL_O<175> WL_O<174> WL_O<173> WL_O<172> ++ WL_O<171> WL_O<170> WL_O<169> WL_O<168> WL_O<167> WL_O<166> WL_O<165> ++ WL_O<164> WL_O<163> WL_O<162> WL_O<161> WL_O<160> VDD VSS / ++ RM_IHPSG13_512x32_c2_2P_DEC04 +XSEL<9> ADDR_N_I<3> ADDR_N_I<2> ADDR_N_I<1> ADDR_N_I<0> CS00<9> ECLK_H<9> ++ ECLK_H<10> ECLK_B<9> ECLK_B<10> WL_O<159> WL_O<158> WL_O<157> WL_O<156> ++ WL_O<155> WL_O<154> WL_O<153> WL_O<152> WL_O<151> WL_O<150> WL_O<149> ++ WL_O<148> WL_O<147> WL_O<146> WL_O<145> WL_O<144> VDD VSS / ++ RM_IHPSG13_512x32_c2_2P_DEC04 +XSEL<8> ADDR_N_I<3> ADDR_N_I<2> ADDR_N_I<1> ADDR_N_I<0> CS00<8> ECLK_H<8> ++ ECLK_H<9> ECLK_B<8> ECLK_B<9> WL_O<143> WL_O<142> WL_O<141> WL_O<140> ++ WL_O<139> WL_O<138> WL_O<137> WL_O<136> WL_O<135> WL_O<134> WL_O<133> ++ WL_O<132> WL_O<131> WL_O<130> WL_O<129> WL_O<128> VDD VSS / ++ RM_IHPSG13_512x32_c2_2P_DEC04 +XSEL<7> ADDR_N_I<3> ADDR_N_I<2> ADDR_N_I<1> ADDR_N_I<0> CS00<7> ECLK_H<7> ++ ECLK_H<8> ECLK_B<7> ECLK_B<8> WL_O<127> WL_O<126> WL_O<125> WL_O<124> ++ WL_O<123> WL_O<122> WL_O<121> WL_O<120> WL_O<119> WL_O<118> WL_O<117> ++ WL_O<116> WL_O<115> WL_O<114> WL_O<113> WL_O<112> VDD VSS / ++ RM_IHPSG13_512x32_c2_2P_DEC04 +XSEL<6> ADDR_N_I<3> ADDR_N_I<2> ADDR_N_I<1> ADDR_N_I<0> CS00<6> ECLK_H<6> ++ ECLK_H<7> ECLK_B<6> ECLK_B<7> WL_O<111> WL_O<110> WL_O<109> WL_O<108> ++ WL_O<107> WL_O<106> WL_O<105> WL_O<104> WL_O<103> WL_O<102> WL_O<101> ++ WL_O<100> WL_O<99> WL_O<98> WL_O<97> WL_O<96> VDD VSS / ++ RM_IHPSG13_512x32_c2_2P_DEC04 +XSEL<5> ADDR_N_I<3> ADDR_N_I<2> ADDR_N_I<1> ADDR_N_I<0> CS00<5> ECLK_H<5> ++ ECLK_H<6> ECLK_B<5> ECLK_B<6> WL_O<95> WL_O<94> WL_O<93> WL_O<92> WL_O<91> ++ WL_O<90> WL_O<89> WL_O<88> WL_O<87> WL_O<86> WL_O<85> WL_O<84> WL_O<83> ++ WL_O<82> WL_O<81> WL_O<80> VDD VSS / RM_IHPSG13_512x32_c2_2P_DEC04 +XSEL<4> ADDR_N_I<3> ADDR_N_I<2> ADDR_N_I<1> ADDR_N_I<0> CS00<4> ECLK_H<4> ++ ECLK_H<5> ECLK_B<4> ECLK_B<5> WL_O<79> WL_O<78> WL_O<77> WL_O<76> WL_O<75> ++ WL_O<74> WL_O<73> WL_O<72> WL_O<71> WL_O<70> WL_O<69> WL_O<68> WL_O<67> ++ WL_O<66> WL_O<65> WL_O<64> VDD VSS / RM_IHPSG13_512x32_c2_2P_DEC04 +XSEL<3> ADDR_N_I<3> ADDR_N_I<2> ADDR_N_I<1> ADDR_N_I<0> CS00<3> ECLK_H<3> ++ ECLK_H<4> ECLK_B<3> ECLK_B<4> WL_O<63> WL_O<62> WL_O<61> WL_O<60> WL_O<59> ++ WL_O<58> WL_O<57> WL_O<56> WL_O<55> WL_O<54> WL_O<53> WL_O<52> WL_O<51> ++ WL_O<50> WL_O<49> WL_O<48> VDD VSS / RM_IHPSG13_512x32_c2_2P_DEC04 +XSEL<2> ADDR_N_I<3> ADDR_N_I<2> ADDR_N_I<1> ADDR_N_I<0> CS00<2> ECLK_H<2> ++ ECLK_H<3> ECLK_B<2> ECLK_B<3> WL_O<47> WL_O<46> WL_O<45> WL_O<44> WL_O<43> ++ WL_O<42> WL_O<41> WL_O<40> WL_O<39> WL_O<38> WL_O<37> WL_O<36> WL_O<35> ++ WL_O<34> WL_O<33> WL_O<32> VDD VSS / RM_IHPSG13_512x32_c2_2P_DEC04 +XSEL<1> ADDR_N_I<3> ADDR_N_I<2> ADDR_N_I<1> ADDR_N_I<0> CS00<1> ECLK_H<1> ++ ECLK_H<2> ECLK_B<1> ECLK_B<2> WL_O<31> WL_O<30> WL_O<29> WL_O<28> WL_O<27> ++ WL_O<26> WL_O<25> WL_O<24> WL_O<23> WL_O<22> WL_O<21> WL_O<20> WL_O<19> ++ WL_O<18> WL_O<17> WL_O<16> VDD VSS / RM_IHPSG13_512x32_c2_2P_DEC04 +XSEL<0> ADDR_N_I<3> ADDR_N_I<2> ADDR_N_I<1> ADDR_N_I<0> CS00<0> ECLK_I ++ ECLK_H<1> ECLK_B<0> ECLK_B<1> WL_O<15> WL_O<14> WL_O<13> WL_O<12> WL_O<11> ++ WL_O<10> WL_O<9> WL_O<8> WL_O<7> WL_O<6> WL_O<5> WL_O<4> WL_O<3> WL_O<2> ++ WL_O<1> WL_O<0> VDD VSS / RM_IHPSG13_512x32_c2_2P_DEC04 +XDEC10<9> ADDR_N_I<7> ADDR_N_I<6> CS04<1> CS02<6> VDD VSS / ++ RM_IHPSG13_512x32_c2_2P_DEC02 +XDEC10<8> ADDR_N_I<7> ADDR_N_I<6> CS04<0> CS02<2> VDD VSS / ++ RM_IHPSG13_512x32_c2_2P_DEC02 +XDEC10<7> ADDR_N_I<5> ADDR_N_I<4> CS02<7> CS00<30> VDD VSS / ++ RM_IHPSG13_512x32_c2_2P_DEC02 +XDEC10<6> ADDR_N_I<5> ADDR_N_I<4> CS02<6> CS00<26> VDD VSS / ++ RM_IHPSG13_512x32_c2_2P_DEC02 +XDEC10<5> ADDR_N_I<5> ADDR_N_I<4> CS02<5> CS00<22> VDD VSS / ++ RM_IHPSG13_512x32_c2_2P_DEC02 +XDEC10<4> ADDR_N_I<5> ADDR_N_I<4> CS02<4> CS00<18> VDD VSS / ++ RM_IHPSG13_512x32_c2_2P_DEC02 +XDEC10<3> ADDR_N_I<5> ADDR_N_I<4> CS02<3> CS00<14> VDD VSS / ++ RM_IHPSG13_512x32_c2_2P_DEC02 +XDEC10<2> ADDR_N_I<5> ADDR_N_I<4> CS02<2> CS00<10> VDD VSS / ++ RM_IHPSG13_512x32_c2_2P_DEC02 +XDEC10<1> ADDR_N_I<5> ADDR_N_I<4> CS02<1> CS00<6> VDD VSS / ++ RM_IHPSG13_512x32_c2_2P_DEC02 +XDEC10<0> ADDR_N_I<5> ADDR_N_I<4> CS02<0> CS00<2> VDD VSS / ++ RM_IHPSG13_512x32_c2_2P_DEC02 +XDEC01<10> ADDR_N_I<9> ADDR_N_I<8> CS_I CS04<1> VDD VSS / ++ RM_IHPSG13_512x32_c2_2P_DEC01 +XDEC01<9> ADDR_N_I<7> ADDR_N_I<6> CS04<1> CS02<5> VDD VSS / ++ RM_IHPSG13_512x32_c2_2P_DEC01 +XDEC01<8> ADDR_N_I<7> ADDR_N_I<6> CS04<0> CS02<1> VDD VSS / ++ RM_IHPSG13_512x32_c2_2P_DEC01 +XDEC01<7> ADDR_N_I<5> ADDR_N_I<4> CS02<7> CS00<29> VDD VSS / ++ RM_IHPSG13_512x32_c2_2P_DEC01 +XDEC01<6> ADDR_N_I<5> ADDR_N_I<4> CS02<6> CS00<25> VDD VSS / ++ RM_IHPSG13_512x32_c2_2P_DEC01 +XDEC01<5> ADDR_N_I<5> ADDR_N_I<4> CS02<5> CS00<21> VDD VSS / ++ RM_IHPSG13_512x32_c2_2P_DEC01 +XDEC01<4> ADDR_N_I<5> ADDR_N_I<4> CS02<4> CS00<17> VDD VSS / ++ RM_IHPSG13_512x32_c2_2P_DEC01 +XDEC01<3> ADDR_N_I<5> ADDR_N_I<4> CS02<3> CS00<13> VDD VSS / ++ RM_IHPSG13_512x32_c2_2P_DEC01 +XDEC01<2> ADDR_N_I<5> ADDR_N_I<4> CS02<2> CS00<9> VDD VSS / ++ RM_IHPSG13_512x32_c2_2P_DEC01 +XDEC01<1> ADDR_N_I<5> ADDR_N_I<4> CS02<1> CS00<5> VDD VSS / ++ RM_IHPSG13_512x32_c2_2P_DEC01 +XDEC01<0> ADDR_N_I<5> ADDR_N_I<4> CS02<0> CS00<1> VDD VSS / ++ RM_IHPSG13_512x32_c2_2P_DEC01 +XL2<258> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<257> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<256> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<255> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<254> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<253> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<252> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<251> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<250> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<249> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<248> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<247> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<246> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<245> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<244> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<243> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<242> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<241> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<240> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<239> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<238> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<237> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<236> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<235> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<234> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<233> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<232> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<231> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<230> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<229> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<228> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<227> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<226> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<225> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<224> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<223> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<222> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<221> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<220> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<219> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<218> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<217> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<216> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<215> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<214> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<213> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<212> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<211> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<210> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<209> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<208> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<207> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<206> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<205> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<204> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<203> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<202> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<201> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<200> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<199> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<198> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<197> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<196> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<195> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<194> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<193> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<192> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<191> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<190> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<189> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<188> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<187> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<186> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<185> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<184> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<183> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<182> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<181> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<180> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<179> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<178> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<177> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<176> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<175> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<174> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<173> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<172> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<171> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<170> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<169> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<168> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<167> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<166> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<165> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<164> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<163> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<162> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<161> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<160> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<159> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<158> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<157> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<156> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<155> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<154> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<153> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<152> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<151> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<150> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<149> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<148> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<147> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<146> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<145> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<144> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<143> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<142> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<141> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<140> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<139> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<138> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<137> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<136> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<135> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<134> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<133> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<132> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<131> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<130> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<129> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<128> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<127> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<126> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<125> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<124> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<123> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<122> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<121> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<120> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<119> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<118> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<117> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<116> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<115> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<114> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<113> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<112> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<111> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<110> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<109> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<108> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<107> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<106> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<105> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<104> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<103> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<102> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<101> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<100> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<99> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<98> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<97> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<96> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<95> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<94> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<93> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<92> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<91> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<90> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<89> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<88> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<87> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<86> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<85> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<84> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<83> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<82> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<81> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<80> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<79> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<78> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<77> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<76> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<75> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<74> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<73> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<72> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<71> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<70> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<69> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<68> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<67> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<66> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<65> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<64> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<63> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<62> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<61> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<60> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<59> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<58> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<57> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<56> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<55> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<54> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<53> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<52> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<51> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<50> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<49> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<48> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<47> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<46> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<45> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<44> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<43> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<42> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<41> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<40> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<39> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<38> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<37> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<36> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<35> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<34> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<33> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<32> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<31> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<30> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<29> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<28> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<27> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<26> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<25> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<24> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<23> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<22> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<21> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<20> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<19> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<18> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<17> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<16> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<15> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<14> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<13> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<12> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<11> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<10> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<9> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<8> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<7> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<6> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<5> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<4> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<3> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<2> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<1> VDD VSS / RSC_IHPSG13_FILLCAP8 +XDEC00<10> ADDR_N_I<9> ADDR_N_I<8> CS_I CS04<0> VDD VSS / ++ RM_IHPSG13_512x32_c2_2P_DEC00 +XDEC00<9> ADDR_N_I<7> ADDR_N_I<6> CS04<1> CS02<4> VDD VSS / ++ RM_IHPSG13_512x32_c2_2P_DEC00 +XDEC00<8> ADDR_N_I<7> ADDR_N_I<6> CS04<0> CS02<0> VDD VSS / ++ RM_IHPSG13_512x32_c2_2P_DEC00 +XDEC00<7> ADDR_N_I<5> ADDR_N_I<4> CS02<7> CS00<28> VDD VSS / ++ RM_IHPSG13_512x32_c2_2P_DEC00 +XDEC00<6> ADDR_N_I<5> ADDR_N_I<4> CS02<6> CS00<24> VDD VSS / ++ RM_IHPSG13_512x32_c2_2P_DEC00 +XDEC00<5> ADDR_N_I<5> ADDR_N_I<4> CS02<5> CS00<20> VDD VSS / ++ RM_IHPSG13_512x32_c2_2P_DEC00 +XDEC00<4> ADDR_N_I<5> ADDR_N_I<4> CS02<4> CS00<16> VDD VSS / ++ RM_IHPSG13_512x32_c2_2P_DEC00 +XDEC00<3> ADDR_N_I<5> ADDR_N_I<4> CS02<3> CS00<12> VDD VSS / ++ RM_IHPSG13_512x32_c2_2P_DEC00 +XDEC00<2> ADDR_N_I<5> ADDR_N_I<4> CS02<2> CS00<8> VDD VSS / ++ RM_IHPSG13_512x32_c2_2P_DEC00 +XDEC00<1> ADDR_N_I<5> ADDR_N_I<4> CS02<1> CS00<4> VDD VSS / ++ RM_IHPSG13_512x32_c2_2P_DEC00 +XDEC00<0> ADDR_N_I<5> ADDR_N_I<4> CS02<0> CS00<0> VDD VSS / ++ RM_IHPSG13_512x32_c2_2P_DEC00 +XDEC11<9> ADDR_N_I<7> ADDR_N_I<6> CS04<1> CS02<7> VDD VSS / ++ RM_IHPSG13_512x32_c2_2P_DEC03 +XDEC11<8> ADDR_N_I<7> ADDR_N_I<6> CS04<0> CS02<3> VDD VSS / ++ RM_IHPSG13_512x32_c2_2P_DEC03 +XDEC11<7> ADDR_N_I<5> ADDR_N_I<4> CS02<7> CS00<31> VDD VSS / ++ RM_IHPSG13_512x32_c2_2P_DEC03 +XDEC11<6> ADDR_N_I<5> ADDR_N_I<4> CS02<6> CS00<27> VDD VSS / ++ RM_IHPSG13_512x32_c2_2P_DEC03 +XDEC11<5> ADDR_N_I<5> ADDR_N_I<4> CS02<5> CS00<23> VDD VSS / ++ RM_IHPSG13_512x32_c2_2P_DEC03 +XDEC11<4> ADDR_N_I<5> ADDR_N_I<4> CS02<4> CS00<19> VDD VSS / ++ RM_IHPSG13_512x32_c2_2P_DEC03 +XDEC11<3> ADDR_N_I<5> ADDR_N_I<4> CS02<3> CS00<15> VDD VSS / ++ RM_IHPSG13_512x32_c2_2P_DEC03 +XDEC11<2> ADDR_N_I<5> ADDR_N_I<4> CS02<2> CS00<11> VDD VSS / ++ RM_IHPSG13_512x32_c2_2P_DEC03 +XDEC11<1> ADDR_N_I<5> ADDR_N_I<4> CS02<1> CS00<7> VDD VSS / ++ RM_IHPSG13_512x32_c2_2P_DEC03 +XDEC11<0> ADDR_N_I<5> ADDR_N_I<4> CS02<0> CS00<3> VDD VSS / ++ RM_IHPSG13_512x32_c2_2P_DEC03 +XI0 ADDR_N_I<9> VDD VSS / RSC_IHPSG13_TIEL +.ENDS +.SUBCKT RM_IHPSG13_512x32_c2_2P_ROWREG9 ACLK_N_I ADDR_I<8> ADDR_I<7> ADDR_I<6> ADDR_I<5> ++ ADDR_I<4> ADDR_I<3> ADDR_I<2> ADDR_I<1> ADDR_I<0> ADDR_N_O<8> ADDR_N_O<7> ++ ADDR_N_O<6> ADDR_N_O<5> ADDR_N_O<4> ADDR_N_O<3> ADDR_N_O<2> ADDR_N_O<1> ++ ADDR_N_O<0> BIST_ADDR_I<8> BIST_ADDR_I<7> BIST_ADDR_I<6> BIST_ADDR_I<5> ++ BIST_ADDR_I<4> BIST_ADDR_I<3> BIST_ADDR_I<2> BIST_ADDR_I<1> BIST_ADDR_I<0> ++ BIST_EN_I VDD VSS +XDFF<8> BIST_EN_I BIST_ADDR_I<8> ACLK_N_I ADDR_I<8> q_int<8> net04<0> VDD ++ VSS / RSC_IHPSG13_DFNQMX2IX1 +XDFF<7> BIST_EN_I BIST_ADDR_I<7> ACLK_N_I ADDR_I<7> q_int<7> net04<1> VDD ++ VSS / RSC_IHPSG13_DFNQMX2IX1 +XDFF<6> BIST_EN_I BIST_ADDR_I<6> ACLK_N_I ADDR_I<6> q_int<6> net04<2> VDD ++ VSS / RSC_IHPSG13_DFNQMX2IX1 +XDFF<5> BIST_EN_I BIST_ADDR_I<5> ACLK_N_I ADDR_I<5> q_int<5> net04<3> VDD ++ VSS / RSC_IHPSG13_DFNQMX2IX1 +XDFF<4> BIST_EN_I BIST_ADDR_I<4> ACLK_N_I ADDR_I<4> q_int<4> net04<4> VDD ++ VSS / RSC_IHPSG13_DFNQMX2IX1 +XDFF<3> BIST_EN_I BIST_ADDR_I<3> ACLK_N_I ADDR_I<3> q_int<3> net04<5> VDD ++ VSS / RSC_IHPSG13_DFNQMX2IX1 +XDFF<2> BIST_EN_I BIST_ADDR_I<2> ACLK_N_I ADDR_I<2> q_int<2> net04<6> VDD ++ VSS / RSC_IHPSG13_DFNQMX2IX1 +XDFF<1> BIST_EN_I BIST_ADDR_I<1> ACLK_N_I ADDR_I<1> q_int<1> net04<7> VDD ++ VSS / RSC_IHPSG13_DFNQMX2IX1 +XDFF<0> BIST_EN_I BIST_ADDR_I<0> ACLK_N_I ADDR_I<0> q_int<0> net04<8> VDD ++ VSS / RSC_IHPSG13_DFNQMX2IX1 +XDRV<8> qn_int<8> ADDR_N_O<8> VDD VSS / RSC_IHPSG13_CINVX8 +XDRV<7> qn_int<7> ADDR_N_O<7> VDD VSS / RSC_IHPSG13_CINVX8 +XDRV<6> qn_int<6> ADDR_N_O<6> VDD VSS / RSC_IHPSG13_CINVX8 +XDRV<5> qn_int<5> ADDR_N_O<5> VDD VSS / RSC_IHPSG13_CINVX8 +XDRV<4> qn_int<4> ADDR_N_O<4> VDD VSS / RSC_IHPSG13_CINVX8 +XDRV<3> qn_int<3> ADDR_N_O<3> VDD VSS / RSC_IHPSG13_CINVX8 +XDRV<2> qn_int<2> ADDR_N_O<2> VDD VSS / RSC_IHPSG13_CINVX8 +XDRV<1> qn_int<1> ADDR_N_O<1> VDD VSS / RSC_IHPSG13_CINVX8 +XDRV<0> qn_int<0> ADDR_N_O<0> VDD VSS / RSC_IHPSG13_CINVX8 +XINV<8> q_int<8> qn_int<8> VDD VSS / RSC_IHPSG13_CINVX2 +XINV<7> q_int<7> qn_int<7> VDD VSS / RSC_IHPSG13_CINVX2 +XINV<6> q_int<6> qn_int<6> VDD VSS / RSC_IHPSG13_CINVX2 +XINV<5> q_int<5> qn_int<5> VDD VSS / RSC_IHPSG13_CINVX2 +XINV<4> q_int<4> qn_int<4> VDD VSS / RSC_IHPSG13_CINVX2 +XINV<3> q_int<3> qn_int<3> VDD VSS / RSC_IHPSG13_CINVX2 +XINV<2> q_int<2> qn_int<2> VDD VSS / RSC_IHPSG13_CINVX2 +XINV<1> q_int<1> qn_int<1> VDD VSS / RSC_IHPSG13_CINVX2 +XINV<0> q_int<0> qn_int<0> VDD VSS / RSC_IHPSG13_CINVX2 +.ENDS + +.SUBCKT RM_IHPSG13_512x32_c2_2P_DLY_MUX A SEL Z VDD VSS +XI11 net4 Z VDD VSS / RSC_IHPSG13_CINVX2 +XI8 A D<3> SEL net4 VDD VSS / RSC_IHPSG13_MX2IX1 +XI20<3> D<2> D<3> VDD VSS / RSC_IHPSG13_CDLYX1 +XI20<2> D<1> D<2> VDD VSS / RSC_IHPSG13_CDLYX1 +XI20<1> A D<1> VDD VSS / RSC_IHPSG13_CDLYX1 +.ENDS +.SUBCKT RM_IHPSG13_512x32_c2_2P_CTRL ACLK_N BIST_CK_I BIST_CS_I BIST_EN BIST_RE_I ++ BIST_WE_I B_TIEL_O CK_I CS_I DCLK ECLK PULSE_H PULSE_L PULSE_O RCLK RE_I ++ ROW_CS WCLK WE_I VDD VSS +XI17 ck_regs we col_we VDD VSS / RSC_IHPSG13_DFNQX2 +XI16 ck_regs re col_re VDD VSS / RSC_IHPSG13_DFNQX2 +XI18 ck_regs cs net7 VDD VSS / RSC_IHPSG13_DFNQX2 +XI71 ACLK_N net012 PULSE_O VDD VSS / RSC_IHPSG13_DFNQX2 +XI77 col_we net017 net016 VDD VSS / RSC_IHPSG13_CNAND2X2 +XI76 col_re net017 net018 VDD VSS / RSC_IHPSG13_CNAND2X2 +XI15 ck_dly WEorREandCS aclk VDD VSS / RSC_IHPSG13_CGATEPX4 +XI14 ck WEandCS DCLK VDD VSS / RSC_IHPSG13_CGATEPX4 +XI60 net7 ROW_CS VDD VSS / RSC_IHPSG13_CBUFX8 +XI73 PULSE_O net012 VDD VSS / RSC_IHPSG13_CINVX2 +XI8 net017 net8 VDD VSS / RSC_IHPSG13_CINVX2 +XCAPS4<7> VDD VSS / RSC_IHPSG13_FILLCAP4 +XCAPS4<6> VDD VSS / RSC_IHPSG13_FILLCAP4 +XCAPS4<5> VDD VSS / RSC_IHPSG13_FILLCAP4 +XCAPS4<4> VDD VSS / RSC_IHPSG13_FILLCAP4 +XCAPS4<3> VDD VSS / RSC_IHPSG13_FILLCAP4 +XCAPS4<2> VDD VSS / RSC_IHPSG13_FILLCAP4 +XCAPS4<1> VDD VSS / RSC_IHPSG13_FILLCAP4 +XBM_TIEL B_TIEL_O VDD VSS / RSC_IHPSG13_TIEL +XI64 ck ck_dly VDD VSS / RSC_IHPSG13_CDLYX2 +XI86 CS_I BIST_CS_I BIST_EN cs VDD VSS / RSC_IHPSG13_MX2X2 +XI87 CK_I BIST_CK_I BIST_EN ck VDD VSS / RSC_IHPSG13_MX2X2 +XI85 WE_I BIST_WE_I BIST_EN we VDD VSS / RSC_IHPSG13_MX2X2 +XI84 RE_I BIST_RE_I BIST_EN re VDD VSS / RSC_IHPSG13_MX2X2 +XI48 ck_dly ck_regs VDD VSS / RSC_IHPSG13_CINVX4 +XI81 net016 WCLK VDD VSS / RSC_IHPSG13_CINVX4 +XI80 net018 RCLK VDD VSS / RSC_IHPSG13_CINVX4 +XI78 net8 net020 VDD VSS / RSC_IHPSG13_CINVX4 +XCAPS8<7> VDD VSS / RSC_IHPSG13_FILLCAP8 +XCAPS8<6> VDD VSS / RSC_IHPSG13_FILLCAP8 +XCAPS8<5> VDD VSS / RSC_IHPSG13_FILLCAP8 +XCAPS8<4> VDD VSS / RSC_IHPSG13_FILLCAP8 +XCAPS8<3> VDD VSS / RSC_IHPSG13_FILLCAP8 +XCAPS8<2> VDD VSS / RSC_IHPSG13_FILLCAP8 +XCAPS8<1> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI6 PULSE_L PULSE_H net017 VDD VSS / RSC_IHPSG13_XOR2X2 +XI22 we cs WEandCS VDD VSS / RSC_IHPSG13_AND2X2 +XI79 net020 ECLK VDD VSS / RSC_IHPSG13_CINVX8 +XI63 aclk ACLK_N VDD VSS / RSC_IHPSG13_CINVX8 +XI21 re we cs WEorREandCS VDD VSS / RSC_IHPSG13_OA12X1 +.ENDS +.SUBCKT RM_IHPSG13_512x32_c2_2P_COLDEC5 ACLK_N ADDR<4> ADDR<3> ADDR<2> ADDR<1> ADDR<0> ++ ADDR_COL<1> ADDR_COL<0> ADDR_DEC<7> ADDR_DEC<6> ADDR_DEC<5> ADDR_DEC<4> ++ ADDR_DEC<3> ADDR_DEC<2> ADDR_DEC<1> ADDR_DEC<0> BIST_ADDR<4> BIST_ADDR<3> ++ BIST_ADDR<2> BIST_ADDR<1> BIST_ADDR<0> BIST_EN_I VDD VSS +XI17<4> VDD VSS / RSC_IHPSG13_FILLCAP4 +XI17<3> VDD VSS / RSC_IHPSG13_FILLCAP4 +XI17<2> VDD VSS / RSC_IHPSG13_FILLCAP4 +XI17<1> VDD VSS / RSC_IHPSG13_FILLCAP4 +XI1<7> PADR<0> PADR<1> PADR<2> addr_n<7> VDD VSS / RSC_IHPSG13_NAND3X2 +XI1<6> NADR<0> PADR<1> PADR<2> addr_n<6> VDD VSS / RSC_IHPSG13_NAND3X2 +XI1<5> PADR<0> NADR<1> PADR<2> addr_n<5> VDD VSS / RSC_IHPSG13_NAND3X2 +XI1<4> NADR<0> NADR<1> PADR<2> addr_n<4> VDD VSS / RSC_IHPSG13_NAND3X2 +XI1<3> PADR<0> PADR<1> NADR<2> addr_n<3> VDD VSS / RSC_IHPSG13_NAND3X2 +XI1<2> NADR<0> PADR<1> NADR<2> addr_n<2> VDD VSS / RSC_IHPSG13_NAND3X2 +XI1<1> PADR<0> NADR<1> NADR<2> addr_n<1> VDD VSS / RSC_IHPSG13_NAND3X2 +XI1<0> NADR<0> NADR<1> NADR<2> addr_n<0> VDD VSS / RSC_IHPSG13_NAND3X2 +XDFF<4> BIST_EN_I BIST_ADDR<4> ACLK_N ADDR<4> addr_int<1> net13<0> VDD ++ VSS / RSC_IHPSG13_DFNQMX2IX1 +XDFF<3> BIST_EN_I BIST_ADDR<3> ACLK_N ADDR<3> addr_int<0> net13<1> VDD ++ VSS / RSC_IHPSG13_DFNQMX2IX1 +XDFF<2> BIST_EN_I BIST_ADDR<2> ACLK_N ADDR<2> padr_int<2> net13<2> VDD ++ VSS / RSC_IHPSG13_DFNQMX2IX1 +XDFF<1> BIST_EN_I BIST_ADDR<1> ACLK_N ADDR<1> padr_int<1> net13<3> VDD ++ VSS / RSC_IHPSG13_DFNQMX2IX1 +XDFF<0> BIST_EN_I BIST_ADDR<0> ACLK_N ADDR<0> padr_int<0> net13<4> VDD ++ VSS / RSC_IHPSG13_DFNQMX2IX1 +XI3<2> padr_int<2> NADR<2> VDD VSS / RSC_IHPSG13_INVX2 +XI3<1> padr_int<1> NADR<1> VDD VSS / RSC_IHPSG13_INVX2 +XI3<0> padr_int<0> NADR<0> VDD VSS / RSC_IHPSG13_INVX2 +XI2<7> addr_n<7> ADDR_DEC<7> VDD VSS / RSC_IHPSG13_INVX2 +XI2<6> addr_n<6> ADDR_DEC<6> VDD VSS / RSC_IHPSG13_INVX2 +XI2<5> addr_n<5> ADDR_DEC<5> VDD VSS / RSC_IHPSG13_INVX2 +XI2<4> addr_n<4> ADDR_DEC<4> VDD VSS / RSC_IHPSG13_INVX2 +XI2<3> addr_n<3> ADDR_DEC<3> VDD VSS / RSC_IHPSG13_INVX2 +XI2<2> addr_n<2> ADDR_DEC<2> VDD VSS / RSC_IHPSG13_INVX2 +XI2<1> addr_n<1> ADDR_DEC<1> VDD VSS / RSC_IHPSG13_INVX2 +XI2<0> addr_n<0> ADDR_DEC<0> VDD VSS / RSC_IHPSG13_INVX2 +XI15<2> NADR<2> PADR<2> VDD VSS / RSC_IHPSG13_INVX2 +XI15<1> NADR<1> PADR<1> VDD VSS / RSC_IHPSG13_INVX2 +XI15<0> NADR<0> PADR<0> VDD VSS / RSC_IHPSG13_INVX2 +XI13<1> addr_int<1> ADDR_COL<1> VDD VSS / RSC_IHPSG13_CBUFX2 +XI13<0> addr_int<0> ADDR_COL<0> VDD VSS / RSC_IHPSG13_CBUFX2 +XI14<5> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI14<4> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI14<3> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI14<2> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI14<1> VDD VSS / RSC_IHPSG13_FILLCAP8 +.ENDS +.SUBCKT RM_IHPSG13_512x32_c2_2P_BLDRV A_BLC<3> A_BLC<2> A_BLC<1> A_BLC<0> A_BLC_SEL ++ A_BLT<3> A_BLT<2> A_BLT<1> A_BLT<0> A_BLT_SEL A_PRE_N A_SEL_P<3> A_SEL_P<2> ++ A_SEL_P<1> A_SEL_P<0> A_WR_ONE A_WR_ZERO B_BLC<3> B_BLC<2> B_BLC<1> B_BLC<0> ++ B_BLC_SEL B_BLT<3> B_BLT<2> B_BLT<1> B_BLT<0> B_BLT_SEL B_PRE_N B_SEL_P<3> ++ B_SEL_P<2> B_SEL_P<1> B_SEL_P<0> B_WR_ONE B_WR_ZERO VDD VSS +MA_CWN<3> A_BLC<3> A_BLC_NMOS_DRIVE<3> VSS VSS sg13_lv_nmos m=1 ++ w=4.82u l=130.00n ng=2 nrd=0 nrs=0 +MA_CWN<2> A_BLC<2> A_BLC_NMOS_DRIVE<2> VSS VSS sg13_lv_nmos m=1 ++ w=4.82u l=130.00n ng=2 nrd=0 nrs=0 +MA_CWN<1> A_BLC<1> A_BLC_NMOS_DRIVE<1> VSS VSS sg13_lv_nmos m=1 ++ w=4.82u l=130.00n ng=2 nrd=0 nrs=0 +MA_CWN<0> A_BLC<0> A_BLC_NMOS_DRIVE<0> VSS VSS sg13_lv_nmos m=1 ++ w=4.82u l=130.00n ng=2 nrd=0 nrs=0 +MA_TWN<3> A_BLT<3> A_BLT_NMOS_DRIVE<3> VSS VSS sg13_lv_nmos m=1 ++ w=4.82u l=130.00n ng=2 nrd=0 nrs=0 +MA_TWN<2> A_BLT<2> A_BLT_NMOS_DRIVE<2> VSS VSS sg13_lv_nmos m=1 ++ w=4.82u l=130.00n ng=2 nrd=0 nrs=0 +MA_TWN<1> A_BLT<1> A_BLT_NMOS_DRIVE<1> VSS VSS sg13_lv_nmos m=1 ++ w=4.82u l=130.00n ng=2 nrd=0 nrs=0 +MA_TWN<0> A_BLT<0> A_BLT_NMOS_DRIVE<0> VSS VSS sg13_lv_nmos m=1 ++ w=4.82u l=130.00n ng=2 nrd=0 nrs=0 +MB_TWN<3> B_BLT<3> B_BLT_NMOS_DRIVE<3> VSS VSS sg13_lv_nmos m=1 ++ w=4.82u l=130.00n ng=2 nrd=0 nrs=0 +MB_TWN<2> B_BLT<2> B_BLT_NMOS_DRIVE<2> VSS VSS sg13_lv_nmos m=1 ++ w=4.82u l=130.00n ng=2 nrd=0 nrs=0 +MB_TWN<1> B_BLT<1> B_BLT_NMOS_DRIVE<1> VSS VSS sg13_lv_nmos m=1 ++ w=4.82u l=130.00n ng=2 nrd=0 nrs=0 +MB_TWN<0> B_BLT<0> B_BLT_NMOS_DRIVE<0> VSS VSS sg13_lv_nmos m=1 ++ w=4.82u l=130.00n ng=2 nrd=0 nrs=0 +MB_CWN<3> B_BLC<3> B_BLC_NMOS_DRIVE<3> VSS VSS sg13_lv_nmos m=1 ++ w=4.82u l=130.00n ng=2 nrd=0 nrs=0 +MB_CWN<2> B_BLC<2> B_BLC_NMOS_DRIVE<2> VSS VSS sg13_lv_nmos m=1 ++ w=4.82u l=130.00n ng=2 nrd=0 nrs=0 +MB_CWN<1> B_BLC<1> B_BLC_NMOS_DRIVE<1> VSS VSS sg13_lv_nmos m=1 ++ w=4.82u l=130.00n ng=2 nrd=0 nrs=0 +MB_CWN<0> B_BLC<0> B_BLC_NMOS_DRIVE<0> VSS VSS sg13_lv_nmos m=1 ++ w=4.82u l=130.00n ng=2 nrd=0 nrs=0 +MA_CPR<3> A_BLC<3> A_PRE_N VDD VDD sg13_lv_pmos m=1 w=3.000u l=130.00n ++ ng=2 nrd=0 nrs=0 +MA_CPR<2> A_BLC<2> A_PRE_N VDD VDD sg13_lv_pmos m=1 w=3.000u l=130.00n ++ ng=2 nrd=0 nrs=0 +MA_CPR<1> A_BLC<1> A_PRE_N VDD VDD sg13_lv_pmos m=1 w=3.000u l=130.00n ++ ng=2 nrd=0 nrs=0 +MA_CPR<0> A_BLC<0> A_PRE_N VDD VDD sg13_lv_pmos m=1 w=3.000u l=130.00n ++ ng=2 nrd=0 nrs=0 +MA_TWP<3> A_BLT<3> A_BLT_PMOS_DRIVE<3> VDD VDD sg13_lv_pmos m=1 w=1.5u ++ l=130.00n ng=1 nrd=0 nrs=0 +MA_TWP<2> A_BLT<2> A_BLT_PMOS_DRIVE<2> VDD VDD sg13_lv_pmos m=1 w=1.5u ++ l=130.00n ng=1 nrd=0 nrs=0 +MA_TWP<1> A_BLT<1> A_BLT_PMOS_DRIVE<1> VDD VDD sg13_lv_pmos m=1 w=1.5u ++ l=130.00n ng=1 nrd=0 nrs=0 +MA_TWP<0> A_BLT<0> A_BLT_PMOS_DRIVE<0> VDD VDD sg13_lv_pmos m=1 w=1.5u ++ l=130.00n ng=1 nrd=0 nrs=0 +MA_CWP<3> A_BLC<3> A_BLC_PMOS_DRIVE<3> VDD VDD sg13_lv_pmos m=1 w=1.5u ++ l=130.00n ng=1 nrd=0 nrs=0 +MA_CWP<2> A_BLC<2> A_BLC_PMOS_DRIVE<2> VDD VDD sg13_lv_pmos m=1 w=1.5u ++ l=130.00n ng=1 nrd=0 nrs=0 +MA_CWP<1> A_BLC<1> A_BLC_PMOS_DRIVE<1> VDD VDD sg13_lv_pmos m=1 w=1.5u ++ l=130.00n ng=1 nrd=0 nrs=0 +MA_CWP<0> A_BLC<0> A_BLC_PMOS_DRIVE<0> VDD VDD sg13_lv_pmos m=1 w=1.5u ++ l=130.00n ng=1 nrd=0 nrs=0 +MA_TPR<3> A_BLT<3> A_PRE_N VDD VDD sg13_lv_pmos m=1 w=3.000u l=130.00n ++ ng=2 nrd=0 nrs=0 +MA_TPR<2> A_BLT<2> A_PRE_N VDD VDD sg13_lv_pmos m=1 w=3.000u l=130.00n ++ ng=2 nrd=0 nrs=0 +MA_TPR<1> A_BLT<1> A_PRE_N VDD VDD sg13_lv_pmos m=1 w=3.000u l=130.00n ++ ng=2 nrd=0 nrs=0 +MA_TPR<0> A_BLT<0> A_PRE_N VDD VDD sg13_lv_pmos m=1 w=3.000u l=130.00n ++ ng=2 nrd=0 nrs=0 +MA_TSP<3> A_BLT_SEL A_SEL_N<3> A_BLT<3> VDD sg13_lv_pmos m=1 w=1.5u ++ l=130.00n ng=1 nrd=0 nrs=0 +MA_TSP<2> A_BLT_SEL A_SEL_N<2> A_BLT<2> VDD sg13_lv_pmos m=1 w=1.5u ++ l=130.00n ng=1 nrd=0 nrs=0 +MA_TSP<1> A_BLT_SEL A_SEL_N<1> A_BLT<1> VDD sg13_lv_pmos m=1 w=1.5u ++ l=130.00n ng=1 nrd=0 nrs=0 +MA_TSP<0> A_BLT_SEL A_SEL_N<0> A_BLT<0> VDD sg13_lv_pmos m=1 w=1.5u ++ l=130.00n ng=1 nrd=0 nrs=0 +MA_CSP<3> A_BLC_SEL A_SEL_N<3> A_BLC<3> VDD sg13_lv_pmos m=1 w=1.5u ++ l=130.00n ng=1 nrd=0 nrs=0 +MA_CSP<2> A_BLC_SEL A_SEL_N<2> A_BLC<2> VDD sg13_lv_pmos m=1 w=1.5u ++ l=130.00n ng=1 nrd=0 nrs=0 +MA_CSP<1> A_BLC_SEL A_SEL_N<1> A_BLC<1> VDD sg13_lv_pmos m=1 w=1.5u ++ l=130.00n ng=1 nrd=0 nrs=0 +MA_CSP<0> A_BLC_SEL A_SEL_N<0> A_BLC<0> VDD sg13_lv_pmos m=1 w=1.5u ++ l=130.00n ng=1 nrd=0 nrs=0 +MB_CWP<3> B_BLC<3> B_BLC_PMOS_DRIVE<3> VDD VDD sg13_lv_pmos m=1 w=1.5u ++ l=130.00n ng=1 nrd=0 nrs=0 +MB_CWP<2> B_BLC<2> B_BLC_PMOS_DRIVE<2> VDD VDD sg13_lv_pmos m=1 w=1.5u ++ l=130.00n ng=1 nrd=0 nrs=0 +MB_CWP<1> B_BLC<1> B_BLC_PMOS_DRIVE<1> VDD VDD sg13_lv_pmos m=1 w=1.5u ++ l=130.00n ng=1 nrd=0 nrs=0 +MB_CWP<0> B_BLC<0> B_BLC_PMOS_DRIVE<0> VDD VDD sg13_lv_pmos m=1 w=1.5u ++ l=130.00n ng=1 nrd=0 nrs=0 +MB_TWP<3> B_BLT<3> B_BLT_PMOS_DRIVE<3> VDD VDD sg13_lv_pmos m=1 w=1.5u ++ l=130.00n ng=1 nrd=0 nrs=0 +MB_TWP<2> B_BLT<2> B_BLT_PMOS_DRIVE<2> VDD VDD sg13_lv_pmos m=1 w=1.5u ++ l=130.00n ng=1 nrd=0 nrs=0 +MB_TWP<1> B_BLT<1> B_BLT_PMOS_DRIVE<1> VDD VDD sg13_lv_pmos m=1 w=1.5u ++ l=130.00n ng=1 nrd=0 nrs=0 +MB_TWP<0> B_BLT<0> B_BLT_PMOS_DRIVE<0> VDD VDD sg13_lv_pmos m=1 w=1.5u ++ l=130.00n ng=1 nrd=0 nrs=0 +MB_TSP<3> B_BLT_SEL B_SEL_N<3> B_BLT<3> VDD sg13_lv_pmos m=1 w=1.5u ++ l=130.00n ng=1 nrd=0 nrs=0 +MB_TSP<2> B_BLT_SEL B_SEL_N<2> B_BLT<2> VDD sg13_lv_pmos m=1 w=1.5u ++ l=130.00n ng=1 nrd=0 nrs=0 +MB_TSP<1> B_BLT_SEL B_SEL_N<1> B_BLT<1> VDD sg13_lv_pmos m=1 w=1.5u ++ l=130.00n ng=1 nrd=0 nrs=0 +MB_TSP<0> B_BLT_SEL B_SEL_N<0> B_BLT<0> VDD sg13_lv_pmos m=1 w=1.5u ++ l=130.00n ng=1 nrd=0 nrs=0 +MB_TPR<3> B_BLT<3> B_PRE_N VDD VDD sg13_lv_pmos m=1 w=3.000u l=130.00n ++ ng=2 nrd=0 nrs=0 +MB_TPR<2> B_BLT<2> B_PRE_N VDD VDD sg13_lv_pmos m=1 w=3.000u l=130.00n ++ ng=2 nrd=0 nrs=0 +MB_TPR<1> B_BLT<1> B_PRE_N VDD VDD sg13_lv_pmos m=1 w=3.000u l=130.00n ++ ng=2 nrd=0 nrs=0 +MB_TPR<0> B_BLT<0> B_PRE_N VDD VDD sg13_lv_pmos m=1 w=3.000u l=130.00n ++ ng=2 nrd=0 nrs=0 +MB_CSP<3> B_BLC_SEL B_SEL_N<3> B_BLC<3> VDD sg13_lv_pmos m=1 w=1.5u ++ l=130.00n ng=1 nrd=0 nrs=0 +MB_CSP<2> B_BLC_SEL B_SEL_N<2> B_BLC<2> VDD sg13_lv_pmos m=1 w=1.5u ++ l=130.00n ng=1 nrd=0 nrs=0 +MB_CSP<1> B_BLC_SEL B_SEL_N<1> B_BLC<1> VDD sg13_lv_pmos m=1 w=1.5u ++ l=130.00n ng=1 nrd=0 nrs=0 +MB_CSP<0> B_BLC_SEL B_SEL_N<0> B_BLC<0> VDD sg13_lv_pmos m=1 w=1.5u ++ l=130.00n ng=1 nrd=0 nrs=0 +MB_CPR<3> B_BLC<3> B_PRE_N VDD VDD sg13_lv_pmos m=1 w=3.000u l=130.00n ++ ng=2 nrd=0 nrs=0 +MB_CPR<2> B_BLC<2> B_PRE_N VDD VDD sg13_lv_pmos m=1 w=3.000u l=130.00n ++ ng=2 nrd=0 nrs=0 +MB_CPR<1> B_BLC<1> B_PRE_N VDD VDD sg13_lv_pmos m=1 w=3.000u l=130.00n ++ ng=2 nrd=0 nrs=0 +MB_CPR<0> B_BLC<0> B_PRE_N VDD VDD sg13_lv_pmos m=1 w=3.000u l=130.00n ++ ng=2 nrd=0 nrs=0 +XA_SEL<3> A_SEL_P<3> A_SEL_N<3> VDD VSS / RSC_IHPSG13_INVX2 +XA_SEL<2> A_SEL_P<2> A_SEL_N<2> VDD VSS / RSC_IHPSG13_INVX2 +XA_SEL<1> A_SEL_P<1> A_SEL_N<1> VDD VSS / RSC_IHPSG13_INVX2 +XA_SEL<0> A_SEL_P<0> A_SEL_N<0> VDD VSS / RSC_IHPSG13_INVX2 +XA_CINV<3> A_BLT_PMOS_DRIVE<3> A_BLC_NMOS_DRIVE<3> VDD VSS / ++ RSC_IHPSG13_INVX2 +XA_CINV<2> A_BLT_PMOS_DRIVE<2> A_BLC_NMOS_DRIVE<2> VDD VSS / ++ RSC_IHPSG13_INVX2 +XA_CINV<1> A_BLT_PMOS_DRIVE<1> A_BLC_NMOS_DRIVE<1> VDD VSS / ++ RSC_IHPSG13_INVX2 +XA_CINV<0> A_BLT_PMOS_DRIVE<0> A_BLC_NMOS_DRIVE<0> VDD VSS / ++ RSC_IHPSG13_INVX2 +XA_TINV<3> A_BLC_PMOS_DRIVE<3> A_BLT_NMOS_DRIVE<3> VDD VSS / ++ RSC_IHPSG13_INVX2 +XA_TINV<2> A_BLC_PMOS_DRIVE<2> A_BLT_NMOS_DRIVE<2> VDD VSS / ++ RSC_IHPSG13_INVX2 +XA_TINV<1> A_BLC_PMOS_DRIVE<1> A_BLT_NMOS_DRIVE<1> VDD VSS / ++ RSC_IHPSG13_INVX2 +XA_TINV<0> A_BLC_PMOS_DRIVE<0> A_BLT_NMOS_DRIVE<0> VDD VSS / ++ RSC_IHPSG13_INVX2 +XB_SEL<3> B_SEL_P<3> B_SEL_N<3> VDD VSS / RSC_IHPSG13_INVX2 +XB_SEL<2> B_SEL_P<2> B_SEL_N<2> VDD VSS / RSC_IHPSG13_INVX2 +XB_SEL<1> B_SEL_P<1> B_SEL_N<1> VDD VSS / RSC_IHPSG13_INVX2 +XB_SEL<0> B_SEL_P<0> B_SEL_N<0> VDD VSS / RSC_IHPSG13_INVX2 +XB_TINV<3> B_BLC_PMOS_DRIVE<3> B_BLT_NMOS_DRIVE<3> VDD VSS / ++ RSC_IHPSG13_INVX2 +XB_TINV<2> B_BLC_PMOS_DRIVE<2> B_BLT_NMOS_DRIVE<2> VDD VSS / ++ RSC_IHPSG13_INVX2 +XB_TINV<1> B_BLC_PMOS_DRIVE<1> B_BLT_NMOS_DRIVE<1> VDD VSS / ++ RSC_IHPSG13_INVX2 +XB_TINV<0> B_BLC_PMOS_DRIVE<0> B_BLT_NMOS_DRIVE<0> VDD VSS / ++ RSC_IHPSG13_INVX2 +XB_CINV<3> B_BLT_PMOS_DRIVE<3> B_BLC_NMOS_DRIVE<3> VDD VSS / ++ RSC_IHPSG13_INVX2 +XB_CINV<2> B_BLT_PMOS_DRIVE<2> B_BLC_NMOS_DRIVE<2> VDD VSS / ++ RSC_IHPSG13_INVX2 +XB_CINV<1> B_BLT_PMOS_DRIVE<1> B_BLC_NMOS_DRIVE<1> VDD VSS / ++ RSC_IHPSG13_INVX2 +XB_CINV<0> B_BLT_PMOS_DRIVE<0> B_BLC_NMOS_DRIVE<0> VDD VSS / ++ RSC_IHPSG13_INVX2 +XA_TDEC<3> A_SEL_P<3> A_WR_ONE A_BLT_PMOS_DRIVE<3> VDD VSS / ++ RSC_IHPSG13_NAND2X2 +XA_TDEC<2> A_SEL_P<2> A_WR_ONE A_BLT_PMOS_DRIVE<2> VDD VSS / ++ RSC_IHPSG13_NAND2X2 +XA_TDEC<1> A_SEL_P<1> A_WR_ONE A_BLT_PMOS_DRIVE<1> VDD VSS / ++ RSC_IHPSG13_NAND2X2 +XA_TDEC<0> A_SEL_P<0> A_WR_ONE A_BLT_PMOS_DRIVE<0> VDD VSS / ++ RSC_IHPSG13_NAND2X2 +XA_CDEC<3> A_SEL_P<3> A_WR_ZERO A_BLC_PMOS_DRIVE<3> VDD VSS / ++ RSC_IHPSG13_NAND2X2 +XA_CDEC<2> A_SEL_P<2> A_WR_ZERO A_BLC_PMOS_DRIVE<2> VDD VSS / ++ RSC_IHPSG13_NAND2X2 +XA_CDEC<1> A_SEL_P<1> A_WR_ZERO A_BLC_PMOS_DRIVE<1> VDD VSS / ++ RSC_IHPSG13_NAND2X2 +XA_CDEC<0> A_SEL_P<0> A_WR_ZERO A_BLC_PMOS_DRIVE<0> VDD VSS / ++ RSC_IHPSG13_NAND2X2 +XB_CDEC<3> B_SEL_P<3> B_WR_ZERO B_BLC_PMOS_DRIVE<3> VDD VSS / ++ RSC_IHPSG13_NAND2X2 +XB_CDEC<2> B_SEL_P<2> B_WR_ZERO B_BLC_PMOS_DRIVE<2> VDD VSS / ++ RSC_IHPSG13_NAND2X2 +XB_CDEC<1> B_SEL_P<1> B_WR_ZERO B_BLC_PMOS_DRIVE<1> VDD VSS / ++ RSC_IHPSG13_NAND2X2 +XB_CDEC<0> B_SEL_P<0> B_WR_ZERO B_BLC_PMOS_DRIVE<0> VDD VSS / ++ RSC_IHPSG13_NAND2X2 +XB_TDEC<3> B_SEL_P<3> B_WR_ONE B_BLT_PMOS_DRIVE<3> VDD VSS / ++ RSC_IHPSG13_NAND2X2 +XB_TDEC<2> B_SEL_P<2> B_WR_ONE B_BLT_PMOS_DRIVE<2> VDD VSS / ++ RSC_IHPSG13_NAND2X2 +XB_TDEC<1> B_SEL_P<1> B_WR_ONE B_BLT_PMOS_DRIVE<1> VDD VSS / ++ RSC_IHPSG13_NAND2X2 +XB_TDEC<0> B_SEL_P<0> B_WR_ONE B_BLT_PMOS_DRIVE<0> VDD VSS / ++ RSC_IHPSG13_NAND2X2 +.ENDS +.SUBCKT RSC_IHPSG13_AND2X6 A B Z VDD VSS +MN3 Z net6 VSS VSS sg13_lv_nmos m=1 w=2.94u l=130.00n ng=3 nrd=0 nrs=0 +MN4 net9 B VSS VSS sg13_lv_nmos m=1 w=500.0n l=130.00n ng=1 nrd=0 nrs=0 +MN6 net6 A net9 VSS sg13_lv_nmos m=1 w=500.0n l=130.00n ng=1 nrd=0 nrs=0 +MP2 Z net6 VDD VDD sg13_lv_pmos m=1 w=4.86u l=130.00n ng=3 nrd=0 nrs=0 +MP0 net6 B VDD VDD sg13_lv_pmos m=1 w=860.00n l=130.00n ng=1 nrd=0 ++ nrs=0 +MP1 net6 A VDD VDD sg13_lv_pmos m=1 w=860.00n l=130.00n ng=1 nrd=0 ++ nrs=0 +.ENDS +.SUBCKT RM_IHPSG13_512x32_c2_2P_COLCTRL5 A_ADDR_COL<1> A_ADDR_COL<0> A_ADDR_DEC<7> ++ A_ADDR_DEC<6> A_ADDR_DEC<5> A_ADDR_DEC<4> A_ADDR_DEC<3> A_ADDR_DEC<2> ++ A_ADDR_DEC<1> A_ADDR_DEC<0> A_BIST_BM_I A_BIST_DW_I A_BIST_EN_I A_BLC<31> ++ A_BLC<30> A_BLC<29> A_BLC<28> A_BLC<27> A_BLC<26> A_BLC<25> A_BLC<24> ++ A_BLC<23> A_BLC<22> A_BLC<21> A_BLC<20> A_BLC<19> A_BLC<18> A_BLC<17> ++ A_BLC<16> A_BLC<15> A_BLC<14> A_BLC<13> A_BLC<12> A_BLC<11> A_BLC<10> ++ A_BLC<9> A_BLC<8> A_BLC<7> A_BLC<6> A_BLC<5> A_BLC<4> A_BLC<3> A_BLC<2> ++ A_BLC<1> A_BLC<0> A_BLT<31> A_BLT<30> A_BLT<29> A_BLT<28> A_BLT<27> ++ A_BLT<26> A_BLT<25> A_BLT<24> A_BLT<23> A_BLT<22> A_BLT<21> A_BLT<20> ++ A_BLT<19> A_BLT<18> A_BLT<17> A_BLT<16> A_BLT<15> A_BLT<14> A_BLT<13> ++ A_BLT<12> A_BLT<11> A_BLT<10> A_BLT<9> A_BLT<8> A_BLT<7> A_BLT<6> A_BLT<5> ++ A_BLT<4> A_BLT<3> A_BLT<2> A_BLT<1> A_BLT<0> A_BM_I A_DCLK_B_L A_DCLK_B_R ++ A_DCLK_L A_DCLK_R A_DR_O A_DW_I A_RCLK_B_L A_RCLK_B_R A_RCLK_L A_RCLK_R ++ A_TIEH_O A_WCLK_B_L A_WCLK_B_R A_WCLK_L A_WCLK_R B_ADDR_COL<1> B_ADDR_COL<0> ++ B_ADDR_DEC<7> B_ADDR_DEC<6> B_ADDR_DEC<5> B_ADDR_DEC<4> B_ADDR_DEC<3> ++ B_ADDR_DEC<2> B_ADDR_DEC<1> B_ADDR_DEC<0> B_BIST_BM_I B_BIST_DW_I ++ B_BIST_EN_I B_BLC<31> B_BLC<30> B_BLC<29> B_BLC<28> B_BLC<27> B_BLC<26> ++ B_BLC<25> B_BLC<24> B_BLC<23> B_BLC<22> B_BLC<21> B_BLC<20> B_BLC<19> ++ B_BLC<18> B_BLC<17> B_BLC<16> B_BLC<15> B_BLC<14> B_BLC<13> B_BLC<12> ++ B_BLC<11> B_BLC<10> B_BLC<9> B_BLC<8> B_BLC<7> B_BLC<6> B_BLC<5> B_BLC<4> ++ B_BLC<3> B_BLC<2> B_BLC<1> B_BLC<0> B_BLT<31> B_BLT<30> B_BLT<29> B_BLT<28> ++ B_BLT<27> B_BLT<26> B_BLT<25> B_BLT<24> B_BLT<23> B_BLT<22> B_BLT<21> ++ B_BLT<20> B_BLT<19> B_BLT<18> B_BLT<17> B_BLT<16> B_BLT<15> B_BLT<14> ++ B_BLT<13> B_BLT<12> B_BLT<11> B_BLT<10> B_BLT<9> B_BLT<8> B_BLT<7> B_BLT<6> ++ B_BLT<5> B_BLT<4> B_BLT<3> B_BLT<2> B_BLT<1> B_BLT<0> B_BM_I B_DCLK_B_L ++ B_DCLK_B_R B_DCLK_L B_DCLK_R B_DR_O B_DW_I B_RCLK_B_L B_RCLK_B_R B_RCLK_L ++ B_RCLK_R B_TIEH_O B_WCLK_B_L B_WCLK_B_R B_WCLK_L B_WCLK_R VDD VSS +XB_I80<1> B_WCLK_B_L B_RCLK_B_L B_W_nor_R<1> VDD VSS / ++ RSC_IHPSG13_AND2X2 +XB_I80<0> B_WCLK_B_L B_RCLK_B_L B_W_nor_R<0> VDD VSS / ++ RSC_IHPSG13_AND2X2 +XA_I80<1> A_WCLK_B_L A_RCLK_B_L A_W_nor_R<1> VDD VSS / ++ RSC_IHPSG13_AND2X2 +XA_I80<0> A_WCLK_B_L A_RCLK_B_L A_W_nor_R<0> VDD VSS / ++ RSC_IHPSG13_AND2X2 +XB_I44 B_BM_N B_WCLK_B_L B_DO_WRITE_P VDD VSS / RSC_IHPSG13_NOR2X2 +XA_I44 A_BM_N A_WCLK_B_L A_DO_WRITE_P VDD VSS / RSC_IHPSG13_NOR2X2 +XI_FILL4<16> VDD VSS / RSC_IHPSG13_FILLCAP4 +XI_FILL4<15> VDD VSS / RSC_IHPSG13_FILLCAP4 +XI_FILL4<14> VDD VSS / RSC_IHPSG13_FILLCAP4 +XI_FILL4<13> VDD VSS / RSC_IHPSG13_FILLCAP4 +XI_FILL4<12> VDD VSS / RSC_IHPSG13_FILLCAP4 +XI_FILL4<11> VDD VSS / RSC_IHPSG13_FILLCAP4 +XI_FILL4<10> VDD VSS / RSC_IHPSG13_FILLCAP4 +XI_FILL4<9> VDD VSS / RSC_IHPSG13_FILLCAP4 +XI_FILL4<8> VDD VSS / RSC_IHPSG13_FILLCAP4 +XI_FILL4<7> VDD VSS / RSC_IHPSG13_FILLCAP4 +XI_FILL4<6> VDD VSS / RSC_IHPSG13_FILLCAP4 +XI_FILL4<5> VDD VSS / RSC_IHPSG13_FILLCAP4 +XI_FILL4<4> VDD VSS / RSC_IHPSG13_FILLCAP4 +XI_FILL4<3> VDD VSS / RSC_IHPSG13_FILLCAP4 +XI_FILL4<2> VDD VSS / RSC_IHPSG13_FILLCAP4 +XI_FILL4<1> VDD VSS / RSC_IHPSG13_FILLCAP4 +XB_INV<6> B_N1<1> B_P1<1> VDD VSS / RSC_IHPSG13_CINVX4 +XB_INV<5> B_N0<1> B_P0<1> VDD VSS / RSC_IHPSG13_CINVX4 +XB_INV<4> B_N0<0> B_P0<0> VDD VSS / RSC_IHPSG13_CINVX4 +XB_INV<3> B_ADDR_COL<1> B_N1<1> VDD VSS / RSC_IHPSG13_CINVX4 +XB_INV<2> B_ADDR_COL<1> B_N1<0> VDD VSS / RSC_IHPSG13_CINVX4 +XB_INV<1> B_ADDR_COL<0> B_N0<1> VDD VSS / RSC_IHPSG13_CINVX4 +XB_INV<0> B_ADDR_COL<0> B_N0<0> VDD VSS / RSC_IHPSG13_CINVX4 +XA_INV<6> A_N1<1> A_P1<1> VDD VSS / RSC_IHPSG13_CINVX4 +XA_INV<5> A_N0<1> A_P0<1> VDD VSS / RSC_IHPSG13_CINVX4 +XA_INV<4> A_N0<0> A_P0<0> VDD VSS / RSC_IHPSG13_CINVX4 +XA_INV<3> A_ADDR_COL<1> A_N1<1> VDD VSS / RSC_IHPSG13_CINVX4 +XA_INV<2> A_ADDR_COL<1> A_N1<0> VDD VSS / RSC_IHPSG13_CINVX4 +XA_INV<1> A_ADDR_COL<0> A_N0<1> VDD VSS / RSC_IHPSG13_CINVX4 +XA_INV<0> A_ADDR_COL<0> A_N0<0> VDD VSS / RSC_IHPSG13_CINVX4 +XB_I81<3> B_W_nor_R<1> B_PRE_N VDD VSS / RSC_IHPSG13_CINVX4_WN +XB_I81<2> B_W_nor_R<1> B_PRE_N VDD VSS / RSC_IHPSG13_CINVX4_WN +XB_I81<1> B_W_nor_R<0> B_PRE_N VDD VSS / RSC_IHPSG13_CINVX4_WN +XB_I81<0> B_W_nor_R<0> B_PRE_N VDD VSS / RSC_IHPSG13_CINVX4_WN +XA_I81<3> A_W_nor_R<1> A_PRE_N VDD VSS / RSC_IHPSG13_CINVX4_WN +XA_I81<2> A_W_nor_R<1> A_PRE_N VDD VSS / RSC_IHPSG13_CINVX4_WN +XA_I81<1> A_W_nor_R<0> A_PRE_N VDD VSS / RSC_IHPSG13_CINVX4_WN +XA_I81<0> A_W_nor_R<0> A_PRE_N VDD VSS / RSC_IHPSG13_CINVX4_WN +XI_FILL8<78> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI_FILL8<77> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI_FILL8<76> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI_FILL8<75> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI_FILL8<74> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI_FILL8<73> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI_FILL8<72> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI_FILL8<71> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI_FILL8<70> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI_FILL8<69> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI_FILL8<68> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI_FILL8<67> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI_FILL8<66> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI_FILL8<65> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI_FILL8<64> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI_FILL8<63> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI_FILL8<62> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI_FILL8<61> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI_FILL8<60> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI_FILL8<59> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI_FILL8<58> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI_FILL8<57> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI_FILL8<56> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI_FILL8<55> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI_FILL8<54> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI_FILL8<53> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI_FILL8<52> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI_FILL8<51> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI_FILL8<50> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI_FILL8<49> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI_FILL8<48> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI_FILL8<47> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI_FILL8<46> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI_FILL8<45> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI_FILL8<44> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI_FILL8<43> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI_FILL8<42> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI_FILL8<41> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI_FILL8<40> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI_FILL8<39> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI_FILL8<38> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI_FILL8<37> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI_FILL8<36> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI_FILL8<35> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI_FILL8<34> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI_FILL8<33> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI_FILL8<32> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI_FILL8<31> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI_FILL8<30> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI_FILL8<29> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI_FILL8<28> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI_FILL8<27> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI_FILL8<26> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI_FILL8<25> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI_FILL8<24> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI_FILL8<23> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI_FILL8<22> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI_FILL8<21> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI_FILL8<20> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI_FILL8<19> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI_FILL8<18> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI_FILL8<17> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI_FILL8<16> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI_FILL8<15> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI_FILL8<14> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI_FILL8<13> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI_FILL8<12> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI_FILL8<11> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI_FILL8<10> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI_FILL8<9> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI_FILL8<8> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI_FILL8<7> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI_FILL8<6> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI_FILL8<5> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI_FILL8<4> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI_FILL8<3> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI_FILL8<2> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI_FILL8<1> VDD VSS / RSC_IHPSG13_FILLCAP8 +XAB_BLMUX<7> A_BLC<31> A_BLC<30> A_BLC<29> A_BLC<28> A_BLC_SEL A_BLT<31> ++ A_BLT<30> A_BLT<29> A_BLT<28> A_BLT_SEL A_PRE_N A_SEL_P<31> A_SEL_P<30> ++ A_SEL_P<29> A_SEL_P<28> A_WR_ONE A_WR_ZERO B_BLC<31> B_BLC<30> B_BLC<29> ++ B_BLC<28> B_BLC_SEL B_BLT<31> B_BLT<30> B_BLT<29> B_BLT<28> B_BLT_SEL ++ B_PRE_N B_SEL_P<31> B_SEL_P<30> B_SEL_P<29> B_SEL_P<28> B_WR_ONE B_WR_ZERO ++ VDD VSS / RM_IHPSG13_512x32_c2_2P_BLDRV +XAB_BLMUX<6> A_BLC<27> A_BLC<26> A_BLC<25> A_BLC<24> A_BLC_SEL A_BLT<27> ++ A_BLT<26> A_BLT<25> A_BLT<24> A_BLT_SEL A_PRE_N A_SEL_P<27> A_SEL_P<26> ++ A_SEL_P<25> A_SEL_P<24> A_WR_ONE A_WR_ZERO B_BLC<27> B_BLC<26> B_BLC<25> ++ B_BLC<24> B_BLC_SEL B_BLT<27> B_BLT<26> B_BLT<25> B_BLT<24> B_BLT_SEL ++ B_PRE_N B_SEL_P<27> B_SEL_P<26> B_SEL_P<25> B_SEL_P<24> B_WR_ONE B_WR_ZERO ++ VDD VSS / RM_IHPSG13_512x32_c2_2P_BLDRV +XAB_BLMUX<5> A_BLC<23> A_BLC<22> A_BLC<21> A_BLC<20> A_BLC_SEL A_BLT<23> ++ A_BLT<22> A_BLT<21> A_BLT<20> A_BLT_SEL A_PRE_N A_SEL_P<23> A_SEL_P<22> ++ A_SEL_P<21> A_SEL_P<20> A_WR_ONE A_WR_ZERO B_BLC<23> B_BLC<22> B_BLC<21> ++ B_BLC<20> B_BLC_SEL B_BLT<23> B_BLT<22> B_BLT<21> B_BLT<20> B_BLT_SEL ++ B_PRE_N B_SEL_P<23> B_SEL_P<22> B_SEL_P<21> B_SEL_P<20> B_WR_ONE B_WR_ZERO ++ VDD VSS / RM_IHPSG13_512x32_c2_2P_BLDRV +XAB_BLMUX<4> A_BLC<19> A_BLC<18> A_BLC<17> A_BLC<16> A_BLC_SEL A_BLT<19> ++ A_BLT<18> A_BLT<17> A_BLT<16> A_BLT_SEL A_PRE_N A_SEL_P<19> A_SEL_P<18> ++ A_SEL_P<17> A_SEL_P<16> A_WR_ONE A_WR_ZERO B_BLC<19> B_BLC<18> B_BLC<17> ++ B_BLC<16> B_BLC_SEL B_BLT<19> B_BLT<18> B_BLT<17> B_BLT<16> B_BLT_SEL ++ B_PRE_N B_SEL_P<19> B_SEL_P<18> B_SEL_P<17> B_SEL_P<16> B_WR_ONE B_WR_ZERO ++ VDD VSS / RM_IHPSG13_512x32_c2_2P_BLDRV +XAB_BLMUX<3> A_BLC<15> A_BLC<14> A_BLC<13> A_BLC<12> A_BLC_SEL A_BLT<15> ++ A_BLT<14> A_BLT<13> A_BLT<12> A_BLT_SEL A_PRE_N A_SEL_P<15> A_SEL_P<14> ++ A_SEL_P<13> A_SEL_P<12> A_WR_ONE A_WR_ZERO B_BLC<15> B_BLC<14> B_BLC<13> ++ B_BLC<12> B_BLC_SEL B_BLT<15> B_BLT<14> B_BLT<13> B_BLT<12> B_BLT_SEL ++ B_PRE_N B_SEL_P<15> B_SEL_P<14> B_SEL_P<13> B_SEL_P<12> B_WR_ONE B_WR_ZERO ++ VDD VSS / RM_IHPSG13_512x32_c2_2P_BLDRV +XAB_BLMUX<2> A_BLC<11> A_BLC<10> A_BLC<9> A_BLC<8> A_BLC_SEL A_BLT<11> ++ A_BLT<10> A_BLT<9> A_BLT<8> A_BLT_SEL A_PRE_N A_SEL_P<11> A_SEL_P<10> ++ A_SEL_P<9> A_SEL_P<8> A_WR_ONE A_WR_ZERO B_BLC<11> B_BLC<10> B_BLC<9> ++ B_BLC<8> B_BLC_SEL B_BLT<11> B_BLT<10> B_BLT<9> B_BLT<8> B_BLT_SEL B_PRE_N ++ B_SEL_P<11> B_SEL_P<10> B_SEL_P<9> B_SEL_P<8> B_WR_ONE B_WR_ZERO VDD ++ VSS / RM_IHPSG13_512x32_c2_2P_BLDRV +XAB_BLMUX<1> A_BLC<7> A_BLC<6> A_BLC<5> A_BLC<4> A_BLC_SEL A_BLT<7> A_BLT<6> ++ A_BLT<5> A_BLT<4> A_BLT_SEL A_PRE_N A_SEL_P<7> A_SEL_P<6> A_SEL_P<5> ++ A_SEL_P<4> A_WR_ONE A_WR_ZERO B_BLC<7> B_BLC<6> B_BLC<5> B_BLC<4> B_BLC_SEL ++ B_BLT<7> B_BLT<6> B_BLT<5> B_BLT<4> B_BLT_SEL B_PRE_N B_SEL_P<7> B_SEL_P<6> ++ B_SEL_P<5> B_SEL_P<4> B_WR_ONE B_WR_ZERO VDD VSS / ++ RM_IHPSG13_512x32_c2_2P_BLDRV +XAB_BLMUX<0> A_BLC<3> A_BLC<2> A_BLC<1> A_BLC<0> A_BLC_SEL A_BLT<3> A_BLT<2> ++ A_BLT<1> A_BLT<0> A_BLT_SEL A_PRE_N A_SEL_P<3> A_SEL_P<2> A_SEL_P<1> ++ A_SEL_P<0> A_WR_ONE A_WR_ZERO B_BLC<3> B_BLC<2> B_BLC<1> B_BLC<0> B_BLC_SEL ++ B_BLT<3> B_BLT<2> B_BLT<1> B_BLT<0> B_BLT_SEL B_PRE_N B_SEL_P<3> B_SEL_P<2> ++ B_SEL_P<1> B_SEL_P<0> B_WR_ONE B_WR_ZERO VDD VSS / ++ RM_IHPSG13_512x32_c2_2P_BLDRV +XB_I51 net037 B_DR_O VDD VSS / RSC_IHPSG13_INVX4 +XA_I51 net19 A_DR_O VDD VSS / RSC_IHPSG13_INVX4 +XB_I78 B_RCLK_B_L B_SAE VDD VSS / RSC_IHPSG13_CBUFX2 +XA_I78 A_RCLK_B_L A_SAE VDD VSS / RSC_IHPSG13_CBUFX2 +XB_I69 B_DCLK_L B_DCLK_B_L VDD VSS / RSC_IHPSG13_CINVX8 +XB_I50 B_WCLK_L B_WCLK_B_L VDD VSS / RSC_IHPSG13_CINVX8 +XB_EBUF B_RCLK_L B_RCLK_B_L VDD VSS / RSC_IHPSG13_CINVX8 +XA_I69 A_DCLK_L A_DCLK_B_L VDD VSS / RSC_IHPSG13_CINVX8 +XA_I50 A_WCLK_L A_WCLK_B_L VDD VSS / RSC_IHPSG13_CINVX8 +XA_EBUF A_RCLK_L A_RCLK_B_L VDD VSS / RSC_IHPSG13_CINVX8 +XB_I76 B_DI_N B_DO_WRITE_P B_WR_ZERO VDD VSS / RSC_IHPSG13_AND2X6 +XB_I75 B_DI_R B_DO_WRITE_P B_WR_ONE VDD VSS / RSC_IHPSG13_AND2X6 +XA_I76 A_DI_N A_DO_WRITE_P A_WR_ZERO VDD VSS / RSC_IHPSG13_AND2X6 +XA_I75 A_DI_R A_DO_WRITE_P A_WR_ONE VDD VSS / RSC_IHPSG13_AND2X6 +XB_I83 B_BM_R B_BM_N VDD VSS / RSC_IHPSG13_INVX2 +XB_DEC3INV<31> net041<0> B_SEL_P<31> VDD VSS / RSC_IHPSG13_INVX2 +XB_DEC3INV<30> net041<1> B_SEL_P<30> VDD VSS / RSC_IHPSG13_INVX2 +XB_DEC3INV<29> net041<2> B_SEL_P<29> VDD VSS / RSC_IHPSG13_INVX2 +XB_DEC3INV<28> net041<3> B_SEL_P<28> VDD VSS / RSC_IHPSG13_INVX2 +XB_DEC3INV<27> net041<4> B_SEL_P<27> VDD VSS / RSC_IHPSG13_INVX2 +XB_DEC3INV<26> net041<5> B_SEL_P<26> VDD VSS / RSC_IHPSG13_INVX2 +XB_DEC3INV<25> net041<6> B_SEL_P<25> VDD VSS / RSC_IHPSG13_INVX2 +XB_DEC3INV<24> net041<7> B_SEL_P<24> VDD VSS / RSC_IHPSG13_INVX2 +XB_DEC3INV<23> net041<8> B_SEL_P<23> VDD VSS / RSC_IHPSG13_INVX2 +XB_DEC3INV<22> net041<9> B_SEL_P<22> VDD VSS / RSC_IHPSG13_INVX2 +XB_DEC3INV<21> net041<10> B_SEL_P<21> VDD VSS / RSC_IHPSG13_INVX2 +XB_DEC3INV<20> net041<11> B_SEL_P<20> VDD VSS / RSC_IHPSG13_INVX2 +XB_DEC3INV<19> net041<12> B_SEL_P<19> VDD VSS / RSC_IHPSG13_INVX2 +XB_DEC3INV<18> net041<13> B_SEL_P<18> VDD VSS / RSC_IHPSG13_INVX2 +XB_DEC3INV<17> net041<14> B_SEL_P<17> VDD VSS / RSC_IHPSG13_INVX2 +XB_DEC3INV<16> net041<15> B_SEL_P<16> VDD VSS / RSC_IHPSG13_INVX2 +XB_DEC3INV<15> net041<16> B_SEL_P<15> VDD VSS / RSC_IHPSG13_INVX2 +XB_DEC3INV<14> net041<17> B_SEL_P<14> VDD VSS / RSC_IHPSG13_INVX2 +XB_DEC3INV<13> net041<18> B_SEL_P<13> VDD VSS / RSC_IHPSG13_INVX2 +XB_DEC3INV<12> net041<19> B_SEL_P<12> VDD VSS / RSC_IHPSG13_INVX2 +XB_DEC3INV<11> net041<20> B_SEL_P<11> VDD VSS / RSC_IHPSG13_INVX2 +XB_DEC3INV<10> net041<21> B_SEL_P<10> VDD VSS / RSC_IHPSG13_INVX2 +XB_DEC3INV<9> net041<22> B_SEL_P<9> VDD VSS / RSC_IHPSG13_INVX2 +XB_DEC3INV<8> net041<23> B_SEL_P<8> VDD VSS / RSC_IHPSG13_INVX2 +XB_DEC3INV<7> net041<24> B_SEL_P<7> VDD VSS / RSC_IHPSG13_INVX2 +XB_DEC3INV<6> net041<25> B_SEL_P<6> VDD VSS / RSC_IHPSG13_INVX2 +XB_DEC3INV<5> net041<26> B_SEL_P<5> VDD VSS / RSC_IHPSG13_INVX2 +XB_DEC3INV<4> net041<27> B_SEL_P<4> VDD VSS / RSC_IHPSG13_INVX2 +XB_DEC3INV<3> net041<28> B_SEL_P<3> VDD VSS / RSC_IHPSG13_INVX2 +XB_DEC3INV<2> net041<29> B_SEL_P<2> VDD VSS / RSC_IHPSG13_INVX2 +XB_DEC3INV<1> net041<30> B_SEL_P<1> VDD VSS / RSC_IHPSG13_INVX2 +XB_DEC3INV<0> net041<31> B_SEL_P<0> VDD VSS / RSC_IHPSG13_INVX2 +XB_I49 B_DI_R B_DI_N VDD VSS / RSC_IHPSG13_INVX2 +XA_I83 A_BM_R A_BM_N VDD VSS / RSC_IHPSG13_INVX2 +XA_DEC3INV<31> net23<0> A_SEL_P<31> VDD VSS / RSC_IHPSG13_INVX2 +XA_DEC3INV<30> net23<1> A_SEL_P<30> VDD VSS / RSC_IHPSG13_INVX2 +XA_DEC3INV<29> net23<2> A_SEL_P<29> VDD VSS / RSC_IHPSG13_INVX2 +XA_DEC3INV<28> net23<3> A_SEL_P<28> VDD VSS / RSC_IHPSG13_INVX2 +XA_DEC3INV<27> net23<4> A_SEL_P<27> VDD VSS / RSC_IHPSG13_INVX2 +XA_DEC3INV<26> net23<5> A_SEL_P<26> VDD VSS / RSC_IHPSG13_INVX2 +XA_DEC3INV<25> net23<6> A_SEL_P<25> VDD VSS / RSC_IHPSG13_INVX2 +XA_DEC3INV<24> net23<7> A_SEL_P<24> VDD VSS / RSC_IHPSG13_INVX2 +XA_DEC3INV<23> net23<8> A_SEL_P<23> VDD VSS / RSC_IHPSG13_INVX2 +XA_DEC3INV<22> net23<9> A_SEL_P<22> VDD VSS / RSC_IHPSG13_INVX2 +XA_DEC3INV<21> net23<10> A_SEL_P<21> VDD VSS / RSC_IHPSG13_INVX2 +XA_DEC3INV<20> net23<11> A_SEL_P<20> VDD VSS / RSC_IHPSG13_INVX2 +XA_DEC3INV<19> net23<12> A_SEL_P<19> VDD VSS / RSC_IHPSG13_INVX2 +XA_DEC3INV<18> net23<13> A_SEL_P<18> VDD VSS / RSC_IHPSG13_INVX2 +XA_DEC3INV<17> net23<14> A_SEL_P<17> VDD VSS / RSC_IHPSG13_INVX2 +XA_DEC3INV<16> net23<15> A_SEL_P<16> VDD VSS / RSC_IHPSG13_INVX2 +XA_DEC3INV<15> net23<16> A_SEL_P<15> VDD VSS / RSC_IHPSG13_INVX2 +XA_DEC3INV<14> net23<17> A_SEL_P<14> VDD VSS / RSC_IHPSG13_INVX2 +XA_DEC3INV<13> net23<18> A_SEL_P<13> VDD VSS / RSC_IHPSG13_INVX2 +XA_DEC3INV<12> net23<19> A_SEL_P<12> VDD VSS / RSC_IHPSG13_INVX2 +XA_DEC3INV<11> net23<20> A_SEL_P<11> VDD VSS / RSC_IHPSG13_INVX2 +XA_DEC3INV<10> net23<21> A_SEL_P<10> VDD VSS / RSC_IHPSG13_INVX2 +XA_DEC3INV<9> net23<22> A_SEL_P<9> VDD VSS / RSC_IHPSG13_INVX2 +XA_DEC3INV<8> net23<23> A_SEL_P<8> VDD VSS / RSC_IHPSG13_INVX2 +XA_DEC3INV<7> net23<24> A_SEL_P<7> VDD VSS / RSC_IHPSG13_INVX2 +XA_DEC3INV<6> net23<25> A_SEL_P<6> VDD VSS / RSC_IHPSG13_INVX2 +XA_DEC3INV<5> net23<26> A_SEL_P<5> VDD VSS / RSC_IHPSG13_INVX2 +XA_DEC3INV<4> net23<27> A_SEL_P<4> VDD VSS / RSC_IHPSG13_INVX2 +XA_DEC3INV<3> net23<28> A_SEL_P<3> VDD VSS / RSC_IHPSG13_INVX2 +XA_DEC3INV<2> net23<29> A_SEL_P<2> VDD VSS / RSC_IHPSG13_INVX2 +XA_DEC3INV<1> net23<30> A_SEL_P<1> VDD VSS / RSC_IHPSG13_INVX2 +XA_DEC3INV<0> net23<31> A_SEL_P<0> VDD VSS / RSC_IHPSG13_INVX2 +XA_I49 A_DI_R A_DI_N VDD VSS / RSC_IHPSG13_INVX2 +XB_ISENSE B_SAE B_BLC_SEL B_BLT_SEL net037 net038 VDD VSS / ++ RSC_IHPSG13_DFPQD_MSAFFX2 +XA_ISENSE A_SAE A_BLC_SEL A_BLT_SEL net19 net20 VDD VSS / ++ RSC_IHPSG13_DFPQD_MSAFFX2 +XB_DREG B_BIST_EN_I B_BIST_DW_I B_DCLK_B_L B_DW_I B_DI_R net042 VDD ++ VSS / RSC_IHPSG13_DFNQMX2IX1 +XB_BREG B_BIST_EN_I B_BIST_BM_I B_DCLK_B_L B_BM_I B_BM_R net043 VDD ++ VSS / RSC_IHPSG13_DFNQMX2IX1 +XA_DREG A_BIST_EN_I A_BIST_DW_I A_DCLK_B_L A_DW_I A_DI_R net22 VDD VSS ++ / RSC_IHPSG13_DFNQMX2IX1 +XA_BREG A_BIST_EN_I A_BIST_BM_I A_DCLK_B_L A_BM_I A_BM_R net21 VDD VSS ++ / RSC_IHPSG13_DFNQMX2IX1 +XB_DEC3<31> B_P1<1> B_P0<1> B_ADDR_DEC<7> net041<0> VDD VSS / ++ RSC_IHPSG13_NAND3X2 +XB_DEC3<30> B_P1<1> B_P0<1> B_ADDR_DEC<6> net041<1> VDD VSS / ++ RSC_IHPSG13_NAND3X2 +XB_DEC3<29> B_P1<1> B_P0<1> B_ADDR_DEC<5> net041<2> VDD VSS / ++ RSC_IHPSG13_NAND3X2 +XB_DEC3<28> B_P1<1> B_P0<1> B_ADDR_DEC<4> net041<3> VDD VSS / ++ RSC_IHPSG13_NAND3X2 +XB_DEC3<27> B_P1<1> B_P0<1> B_ADDR_DEC<3> net041<4> VDD VSS / ++ RSC_IHPSG13_NAND3X2 +XB_DEC3<26> B_P1<1> B_P0<1> B_ADDR_DEC<2> net041<5> VDD VSS / ++ RSC_IHPSG13_NAND3X2 +XB_DEC3<25> B_P1<1> B_P0<1> B_ADDR_DEC<1> net041<6> VDD VSS / ++ RSC_IHPSG13_NAND3X2 +XB_DEC3<24> B_P1<1> B_P0<1> B_ADDR_DEC<0> net041<7> VDD VSS / ++ RSC_IHPSG13_NAND3X2 +XB_DEC3<23> B_P1<1> B_N0<1> B_ADDR_DEC<7> net041<8> VDD VSS / ++ RSC_IHPSG13_NAND3X2 +XB_DEC3<22> B_P1<1> B_N0<1> B_ADDR_DEC<6> net041<9> VDD VSS / ++ RSC_IHPSG13_NAND3X2 +XB_DEC3<21> B_P1<1> B_N0<1> B_ADDR_DEC<5> net041<10> VDD VSS / ++ RSC_IHPSG13_NAND3X2 +XB_DEC3<20> B_P1<1> B_N0<1> B_ADDR_DEC<4> net041<11> VDD VSS / ++ RSC_IHPSG13_NAND3X2 +XB_DEC3<19> B_P1<1> B_N0<1> B_ADDR_DEC<3> net041<12> VDD VSS / ++ RSC_IHPSG13_NAND3X2 +XB_DEC3<18> B_P1<1> B_N0<1> B_ADDR_DEC<2> net041<13> VDD VSS / ++ RSC_IHPSG13_NAND3X2 +XB_DEC3<17> B_P1<1> B_N0<1> B_ADDR_DEC<1> net041<14> VDD VSS / ++ RSC_IHPSG13_NAND3X2 +XB_DEC3<16> B_P1<1> B_N0<1> B_ADDR_DEC<0> net041<15> VDD VSS / ++ RSC_IHPSG13_NAND3X2 +XB_DEC3<15> B_N1<0> B_P0<0> B_ADDR_DEC<7> net041<16> VDD VSS / ++ RSC_IHPSG13_NAND3X2 +XB_DEC3<14> B_N1<0> B_P0<0> B_ADDR_DEC<6> net041<17> VDD VSS / ++ RSC_IHPSG13_NAND3X2 +XB_DEC3<13> B_N1<0> B_P0<0> B_ADDR_DEC<5> net041<18> VDD VSS / ++ RSC_IHPSG13_NAND3X2 +XB_DEC3<12> B_N1<0> B_P0<0> B_ADDR_DEC<4> net041<19> VDD VSS / ++ RSC_IHPSG13_NAND3X2 +XB_DEC3<11> B_N1<0> B_P0<0> B_ADDR_DEC<3> net041<20> VDD VSS / ++ RSC_IHPSG13_NAND3X2 +XB_DEC3<10> B_N1<0> B_P0<0> B_ADDR_DEC<2> net041<21> VDD VSS / ++ RSC_IHPSG13_NAND3X2 +XB_DEC3<9> B_N1<0> B_P0<0> B_ADDR_DEC<1> net041<22> VDD VSS / ++ RSC_IHPSG13_NAND3X2 +XB_DEC3<8> B_N1<0> B_P0<0> B_ADDR_DEC<0> net041<23> VDD VSS / ++ RSC_IHPSG13_NAND3X2 +XB_DEC3<7> B_N1<0> B_N0<0> B_ADDR_DEC<7> net041<24> VDD VSS / ++ RSC_IHPSG13_NAND3X2 +XB_DEC3<6> B_N1<0> B_N0<0> B_ADDR_DEC<6> net041<25> VDD VSS / ++ RSC_IHPSG13_NAND3X2 +XB_DEC3<5> B_N1<0> B_N0<0> B_ADDR_DEC<5> net041<26> VDD VSS / ++ RSC_IHPSG13_NAND3X2 +XB_DEC3<4> B_N1<0> B_N0<0> B_ADDR_DEC<4> net041<27> VDD VSS / ++ RSC_IHPSG13_NAND3X2 +XB_DEC3<3> B_N1<0> B_N0<0> B_ADDR_DEC<3> net041<28> VDD VSS / ++ RSC_IHPSG13_NAND3X2 +XB_DEC3<2> B_N1<0> B_N0<0> B_ADDR_DEC<2> net041<29> VDD VSS / ++ RSC_IHPSG13_NAND3X2 +XB_DEC3<1> B_N1<0> B_N0<0> B_ADDR_DEC<1> net041<30> VDD VSS / ++ RSC_IHPSG13_NAND3X2 +XB_DEC3<0> B_N1<0> B_N0<0> B_ADDR_DEC<0> net041<31> VDD VSS / ++ RSC_IHPSG13_NAND3X2 +XA_DEC3<31> A_P1<1> A_P0<1> A_ADDR_DEC<7> net23<0> VDD VSS / ++ RSC_IHPSG13_NAND3X2 +XA_DEC3<30> A_P1<1> A_P0<1> A_ADDR_DEC<6> net23<1> VDD VSS / ++ RSC_IHPSG13_NAND3X2 +XA_DEC3<29> A_P1<1> A_P0<1> A_ADDR_DEC<5> net23<2> VDD VSS / ++ RSC_IHPSG13_NAND3X2 +XA_DEC3<28> A_P1<1> A_P0<1> A_ADDR_DEC<4> net23<3> VDD VSS / ++ RSC_IHPSG13_NAND3X2 +XA_DEC3<27> A_P1<1> A_P0<1> A_ADDR_DEC<3> net23<4> VDD VSS / ++ RSC_IHPSG13_NAND3X2 +XA_DEC3<26> A_P1<1> A_P0<1> A_ADDR_DEC<2> net23<5> VDD VSS / ++ RSC_IHPSG13_NAND3X2 +XA_DEC3<25> A_P1<1> A_P0<1> A_ADDR_DEC<1> net23<6> VDD VSS / ++ RSC_IHPSG13_NAND3X2 +XA_DEC3<24> A_P1<1> A_P0<1> A_ADDR_DEC<0> net23<7> VDD VSS / ++ RSC_IHPSG13_NAND3X2 +XA_DEC3<23> A_P1<1> A_N0<1> A_ADDR_DEC<7> net23<8> VDD VSS / ++ RSC_IHPSG13_NAND3X2 +XA_DEC3<22> A_P1<1> A_N0<1> A_ADDR_DEC<6> net23<9> VDD VSS / ++ RSC_IHPSG13_NAND3X2 +XA_DEC3<21> A_P1<1> A_N0<1> A_ADDR_DEC<5> net23<10> VDD VSS / ++ RSC_IHPSG13_NAND3X2 +XA_DEC3<20> A_P1<1> A_N0<1> A_ADDR_DEC<4> net23<11> VDD VSS / ++ RSC_IHPSG13_NAND3X2 +XA_DEC3<19> A_P1<1> A_N0<1> A_ADDR_DEC<3> net23<12> VDD VSS / ++ RSC_IHPSG13_NAND3X2 +XA_DEC3<18> A_P1<1> A_N0<1> A_ADDR_DEC<2> net23<13> VDD VSS / ++ RSC_IHPSG13_NAND3X2 +XA_DEC3<17> A_P1<1> A_N0<1> A_ADDR_DEC<1> net23<14> VDD VSS / ++ RSC_IHPSG13_NAND3X2 +XA_DEC3<16> A_P1<1> A_N0<1> A_ADDR_DEC<0> net23<15> VDD VSS / ++ RSC_IHPSG13_NAND3X2 +XA_DEC3<15> A_N1<0> A_P0<0> A_ADDR_DEC<7> net23<16> VDD VSS / ++ RSC_IHPSG13_NAND3X2 +XA_DEC3<14> A_N1<0> A_P0<0> A_ADDR_DEC<6> net23<17> VDD VSS / ++ RSC_IHPSG13_NAND3X2 +XA_DEC3<13> A_N1<0> A_P0<0> A_ADDR_DEC<5> net23<18> VDD VSS / ++ RSC_IHPSG13_NAND3X2 +XA_DEC3<12> A_N1<0> A_P0<0> A_ADDR_DEC<4> net23<19> VDD VSS / ++ RSC_IHPSG13_NAND3X2 +XA_DEC3<11> A_N1<0> A_P0<0> A_ADDR_DEC<3> net23<20> VDD VSS / ++ RSC_IHPSG13_NAND3X2 +XA_DEC3<10> A_N1<0> A_P0<0> A_ADDR_DEC<2> net23<21> VDD VSS / ++ RSC_IHPSG13_NAND3X2 +XA_DEC3<9> A_N1<0> A_P0<0> A_ADDR_DEC<1> net23<22> VDD VSS / ++ RSC_IHPSG13_NAND3X2 +XA_DEC3<8> A_N1<0> A_P0<0> A_ADDR_DEC<0> net23<23> VDD VSS / ++ RSC_IHPSG13_NAND3X2 +XA_DEC3<7> A_N1<0> A_N0<0> A_ADDR_DEC<7> net23<24> VDD VSS / ++ RSC_IHPSG13_NAND3X2 +XA_DEC3<6> A_N1<0> A_N0<0> A_ADDR_DEC<6> net23<25> VDD VSS / ++ RSC_IHPSG13_NAND3X2 +XA_DEC3<5> A_N1<0> A_N0<0> A_ADDR_DEC<5> net23<26> VDD VSS / ++ RSC_IHPSG13_NAND3X2 +XA_DEC3<4> A_N1<0> A_N0<0> A_ADDR_DEC<4> net23<27> VDD VSS / ++ RSC_IHPSG13_NAND3X2 +XA_DEC3<3> A_N1<0> A_N0<0> A_ADDR_DEC<3> net23<28> VDD VSS / ++ RSC_IHPSG13_NAND3X2 +XA_DEC3<2> A_N1<0> A_N0<0> A_ADDR_DEC<2> net23<29> VDD VSS / ++ RSC_IHPSG13_NAND3X2 +XA_DEC3<1> A_N1<0> A_N0<0> A_ADDR_DEC<1> net23<30> VDD VSS / ++ RSC_IHPSG13_NAND3X2 +XA_DEC3<0> A_N1<0> A_N0<0> A_ADDR_DEC<0> net23<31> VDD VSS / ++ RSC_IHPSG13_NAND3X2 +XB_I89 B_DCLK_B_L B_DCLK_B_R / RSC_IHPSG13_MET3RES +XB_I91 B_RCLK_B_L B_RCLK_B_R / RSC_IHPSG13_MET3RES +XB_I90 B_WCLK_B_L B_WCLK_B_R / RSC_IHPSG13_MET3RES +XB_I88 B_DCLK_L B_DCLK_R / RSC_IHPSG13_MET3RES +XB_I87 B_WCLK_L B_WCLK_R / RSC_IHPSG13_MET3RES +XB_R2 B_RCLK_L B_RCLK_R / RSC_IHPSG13_MET3RES +XA_I89 A_DCLK_B_L A_DCLK_B_R / RSC_IHPSG13_MET3RES +XA_I91 A_RCLK_B_L A_RCLK_B_R / RSC_IHPSG13_MET3RES +XA_I90 A_WCLK_B_L A_WCLK_B_R / RSC_IHPSG13_MET3RES +XA_I88 A_DCLK_L A_DCLK_R / RSC_IHPSG13_MET3RES +XA_I87 A_WCLK_L A_WCLK_R / RSC_IHPSG13_MET3RES +XA_R2 A_RCLK_L A_RCLK_R / RSC_IHPSG13_MET3RES +XB_BM_TIEH B_TIEH_O VDD VSS / RSC_IHPSG13_TIEH +XA_BM_TIEH A_TIEH_O VDD VSS / RSC_IHPSG13_TIEH +.ENDS +.SUBCKT RM_IHPSG13_512x32_c2_2P_COLDRV13_FILL4 VDD VSS +XI0<11> VDD VSS / RSC_IHPSG13_FILLCAP4 +XI0<10> VDD VSS / RSC_IHPSG13_FILLCAP4 +XI0<9> VDD VSS / RSC_IHPSG13_FILLCAP4 +XI0<8> VDD VSS / RSC_IHPSG13_FILLCAP4 +XI0<7> VDD VSS / RSC_IHPSG13_FILLCAP4 +XI0<6> VDD VSS / RSC_IHPSG13_FILLCAP4 +XI0<5> VDD VSS / RSC_IHPSG13_FILLCAP4 +XI0<4> VDD VSS / RSC_IHPSG13_FILLCAP4 +XI0<3> VDD VSS / RSC_IHPSG13_FILLCAP4 +XI0<2> VDD VSS / RSC_IHPSG13_FILLCAP4 +XI0<1> VDD VSS / RSC_IHPSG13_FILLCAP4 +.ENDS + + +.SUBCKT RSC_IHPSG13_CBUFX16 A Z VDD VSS +MN0 net4 A VSS VSS sg13_lv_nmos m=1 w=2.115u l=130.00n ng=3 nrd=0 nrs=0 +MN1 Z net4 VSS VSS sg13_lv_nmos m=1 w=5.64u l=130.00n ng=8 nrd=0 nrs=0 +MP1 Z net4 VDD VDD sg13_lv_pmos m=1 w=13.000u l=130.00n ng=8 nrd=0 ++ nrs=0 +MP0 net4 A VDD VDD sg13_lv_pmos m=1 w=4.89u l=130.00n ng=3 nrd=0 nrs=0 +.ENDS +.SUBCKT RM_IHPSG13_512x32_c2_1P_COLDRV13X16 ADDR_COL_I<1> ADDR_COL_I<0> ADDR_COL_O<1> ++ ADDR_COL_O<0> ADDR_DEC_I<7> ADDR_DEC_I<6> ADDR_DEC_I<5> ADDR_DEC_I<4> ++ ADDR_DEC_I<3> ADDR_DEC_I<2> ADDR_DEC_I<1> ADDR_DEC_I<0> ADDR_DEC_O<7> ++ ADDR_DEC_O<6> ADDR_DEC_O<5> ADDR_DEC_O<4> ADDR_DEC_O<3> ADDR_DEC_O<2> ++ ADDR_DEC_O<1> ADDR_DEC_O<0> DCLK_I DCLK_O RCLK_I RCLK_O WCLK_I WCLK_O ++ VDD VSS +XI1<1> VDD VSS / RSC_IHPSG13_FILLCAP4 +XI1<0> VDD VSS / RSC_IHPSG13_FILLCAP4 +XI0<3> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI0<2> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI0<1> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI0<0> VDD VSS / RSC_IHPSG13_FILLCAP8 +XADDR_COL_DRV<1> ADDR_COL_I<1> ADDR_COL_O<1> VDD VSS / ++ RSC_IHPSG13_CBUFX16 +XADDR_COL_DRV<0> ADDR_COL_I<0> ADDR_COL_O<0> VDD VSS / ++ RSC_IHPSG13_CBUFX16 +XADDR_DEC_DRV<7> ADDR_DEC_I<7> ADDR_DEC_O<7> VDD VSS / ++ RSC_IHPSG13_CBUFX16 +XADDR_DEC_DRV<6> ADDR_DEC_I<6> ADDR_DEC_O<6> VDD VSS / ++ RSC_IHPSG13_CBUFX16 +XADDR_DEC_DRV<5> ADDR_DEC_I<5> ADDR_DEC_O<5> VDD VSS / ++ RSC_IHPSG13_CBUFX16 +XADDR_DEC_DRV<4> ADDR_DEC_I<4> ADDR_DEC_O<4> VDD VSS / ++ RSC_IHPSG13_CBUFX16 +XADDR_DEC_DRV<3> ADDR_DEC_I<3> ADDR_DEC_O<3> VDD VSS / ++ RSC_IHPSG13_CBUFX16 +XADDR_DEC_DRV<2> ADDR_DEC_I<2> ADDR_DEC_O<2> VDD VSS / ++ RSC_IHPSG13_CBUFX16 +XADDR_DEC_DRV<1> ADDR_DEC_I<1> ADDR_DEC_O<1> VDD VSS / ++ RSC_IHPSG13_CBUFX16 +XADDR_DEC_DRV<0> ADDR_DEC_I<0> ADDR_DEC_O<0> VDD VSS / ++ RSC_IHPSG13_CBUFX16 +XDCLK_DRV DCLK_I DCLK_O VDD VSS / RSC_IHPSG13_CBUFX16 +XRCLK_DRV RCLK_I RCLK_O VDD VSS / RSC_IHPSG13_CBUFX16 +XWCLK_DRV WCLK_I WCLK_O VDD VSS / RSC_IHPSG13_CBUFX16 +.ENDS +.SUBCKT RSC_IHPSG13_WLDRVX16 A Z VDD VSS +MN1 Z net6 VSS VSS sg13_lv_nmos m=1 w=1.41u l=130.00n ng=2 nrd=0 nrs=0 +MN0 net6 A VSS VSS sg13_lv_nmos m=1 w=1.8u l=130.00n ng=2 nrd=0 nrs=0 +MP1 Z net6 VDD VDD sg13_lv_pmos m=1 w=12.96u l=130.00n ng=8 nrd=0 nrs=0 +MP0 net6 A VDD VDD sg13_lv_pmos m=1 w=900.0n l=130.00n ng=1 nrd=0 nrs=0 +.ENDS +.SUBCKT RM_IHPSG13_512x32_c2_1P_WLDRV16X16 A<15> A<14> A<13> A<12> A<11> A<10> A<9> A<8> ++ A<7> A<6> A<5> A<4> A<3> A<2> A<1> A<0> Z<15> Z<14> Z<13> Z<12> Z<11> Z<10> ++ Z<9> Z<8> Z<7> Z<6> Z<5> Z<4> Z<3> Z<2> Z<1> Z<0> VDD VSS +XBUF<15> A<15> Z<15> VDD VSS / RSC_IHPSG13_WLDRVX16 +XBUF<14> A<14> Z<14> VDD VSS / RSC_IHPSG13_WLDRVX16 +XBUF<13> A<13> Z<13> VDD VSS / RSC_IHPSG13_WLDRVX16 +XBUF<12> A<12> Z<12> VDD VSS / RSC_IHPSG13_WLDRVX16 +XBUF<11> A<11> Z<11> VDD VSS / RSC_IHPSG13_WLDRVX16 +XBUF<10> A<10> Z<10> VDD VSS / RSC_IHPSG13_WLDRVX16 +XBUF<9> A<9> Z<9> VDD VSS / RSC_IHPSG13_WLDRVX16 +XBUF<8> A<8> Z<8> VDD VSS / RSC_IHPSG13_WLDRVX16 +XBUF<7> A<7> Z<7> VDD VSS / RSC_IHPSG13_WLDRVX16 +XBUF<6> A<6> Z<6> VDD VSS / RSC_IHPSG13_WLDRVX16 +XBUF<5> A<5> Z<5> VDD VSS / RSC_IHPSG13_WLDRVX16 +XBUF<4> A<4> Z<4> VDD VSS / RSC_IHPSG13_WLDRVX16 +XBUF<3> A<3> Z<3> VDD VSS / RSC_IHPSG13_WLDRVX16 +XBUF<2> A<2> Z<2> VDD VSS / RSC_IHPSG13_WLDRVX16 +XBUF<1> A<1> Z<1> VDD VSS / RSC_IHPSG13_WLDRVX16 +XBUF<0> A<0> Z<0> VDD VSS / RSC_IHPSG13_WLDRVX16 +.ENDS + + +.SUBCKT RM_IHPSG13_512x32_c2_2P_COLDRV13X4 ADDR_COL_I<1> ADDR_COL_I<0> ADDR_COL_O<1> ++ ADDR_COL_O<0> ADDR_DEC_I<7> ADDR_DEC_I<6> ADDR_DEC_I<5> ADDR_DEC_I<4> ++ ADDR_DEC_I<3> ADDR_DEC_I<2> ADDR_DEC_I<1> ADDR_DEC_I<0> ADDR_DEC_O<7> ++ ADDR_DEC_O<6> ADDR_DEC_O<5> ADDR_DEC_O<4> ADDR_DEC_O<3> ADDR_DEC_O<2> ++ ADDR_DEC_O<1> ADDR_DEC_O<0> DCLK_I DCLK_O RCLK_I RCLK_O WCLK_I WCLK_O ++ VDD VSS +XWCLK_DRV WCLK_I WCLK_O VDD VSS / RSC_IHPSG13_CBUFX4 +XRCLK_DRV RCLK_I RCLK_O VDD VSS / RSC_IHPSG13_CBUFX4 +XDCLK_DRV DCLK_I DCLK_O VDD VSS / RSC_IHPSG13_CBUFX4 +XADDR_COL_DRV<1> ADDR_COL_I<1> ADDR_COL_O<1> VDD VSS / ++ RSC_IHPSG13_CBUFX4 +XADDR_COL_DRV<0> ADDR_COL_I<0> ADDR_COL_O<0> VDD VSS / ++ RSC_IHPSG13_CBUFX4 +XADDR_DEC_DRV<7> ADDR_DEC_I<7> ADDR_DEC_O<7> VDD VSS / ++ RSC_IHPSG13_CBUFX4 +XADDR_DEC_DRV<6> ADDR_DEC_I<6> ADDR_DEC_O<6> VDD VSS / ++ RSC_IHPSG13_CBUFX4 +XADDR_DEC_DRV<5> ADDR_DEC_I<5> ADDR_DEC_O<5> VDD VSS / ++ RSC_IHPSG13_CBUFX4 +XADDR_DEC_DRV<4> ADDR_DEC_I<4> ADDR_DEC_O<4> VDD VSS / ++ RSC_IHPSG13_CBUFX4 +XADDR_DEC_DRV<3> ADDR_DEC_I<3> ADDR_DEC_O<3> VDD VSS / ++ RSC_IHPSG13_CBUFX4 +XADDR_DEC_DRV<2> ADDR_DEC_I<2> ADDR_DEC_O<2> VDD VSS / ++ RSC_IHPSG13_CBUFX4 +XADDR_DEC_DRV<1> ADDR_DEC_I<1> ADDR_DEC_O<1> VDD VSS / ++ RSC_IHPSG13_CBUFX4 +XADDR_DEC_DRV<0> ADDR_DEC_I<0> ADDR_DEC_O<0> VDD VSS / ++ RSC_IHPSG13_CBUFX4 +XI0<6> VDD VSS / RSC_IHPSG13_FILLCAP4 +XI0<5> VDD VSS / RSC_IHPSG13_FILLCAP4 +XI0<4> VDD VSS / RSC_IHPSG13_FILLCAP4 +XI0<3> VDD VSS / RSC_IHPSG13_FILLCAP4 +XI0<2> VDD VSS / RSC_IHPSG13_FILLCAP4 +XI0<1> VDD VSS / RSC_IHPSG13_FILLCAP4 +XI1 VDD VSS / RSC_IHPSG13_FILLCAP8 +.ENDS +.SUBCKT RM_IHPSG13_512x32_c2_2P_WLDRV16X4 A<15> A<14> A<13> A<12> A<11> A<10> A<9> A<8> ++ A<7> A<6> A<5> A<4> A<3> A<2> A<1> A<0> Z<15> Z<14> Z<13> Z<12> Z<11> Z<10> ++ Z<9> Z<8> Z<7> Z<6> Z<5> Z<4> Z<3> Z<2> Z<1> Z<0> VDD VSS +XBUF<15> A<15> Z<15> VDD VSS / RSC_IHPSG13_WLDRVX4 +XBUF<14> A<14> Z<14> VDD VSS / RSC_IHPSG13_WLDRVX4 +XBUF<13> A<13> Z<13> VDD VSS / RSC_IHPSG13_WLDRVX4 +XBUF<12> A<12> Z<12> VDD VSS / RSC_IHPSG13_WLDRVX4 +XBUF<11> A<11> Z<11> VDD VSS / RSC_IHPSG13_WLDRVX4 +XBUF<10> A<10> Z<10> VDD VSS / RSC_IHPSG13_WLDRVX4 +XBUF<9> A<9> Z<9> VDD VSS / RSC_IHPSG13_WLDRVX4 +XBUF<8> A<8> Z<8> VDD VSS / RSC_IHPSG13_WLDRVX4 +XBUF<7> A<7> Z<7> VDD VSS / RSC_IHPSG13_WLDRVX4 +XBUF<6> A<6> Z<6> VDD VSS / RSC_IHPSG13_WLDRVX4 +XBUF<5> A<5> Z<5> VDD VSS / RSC_IHPSG13_WLDRVX4 +XBUF<4> A<4> Z<4> VDD VSS / RSC_IHPSG13_WLDRVX4 +XBUF<3> A<3> Z<3> VDD VSS / RSC_IHPSG13_WLDRVX4 +XBUF<2> A<2> Z<2> VDD VSS / RSC_IHPSG13_WLDRVX4 +XBUF<1> A<1> Z<1> VDD VSS / RSC_IHPSG13_WLDRVX4 +XBUF<0> A<0> Z<0> VDD VSS / RSC_IHPSG13_WLDRVX4 +.ENDS +.SUBCKT RM_IHPSG13_512x32_c2_2P_ROWDEC8 ADDR_N_I<7> ADDR_N_I<6> ADDR_N_I<5> ADDR_N_I<4> ++ ADDR_N_I<3> ADDR_N_I<2> ADDR_N_I<1> ADDR_N_I<0> CS_I ECLK_I WL_O<255> ++ WL_O<254> WL_O<253> WL_O<252> WL_O<251> WL_O<250> WL_O<249> WL_O<248> ++ WL_O<247> WL_O<246> WL_O<245> WL_O<244> WL_O<243> WL_O<242> WL_O<241> ++ WL_O<240> WL_O<239> WL_O<238> WL_O<237> WL_O<236> WL_O<235> WL_O<234> ++ WL_O<233> WL_O<232> WL_O<231> WL_O<230> WL_O<229> WL_O<228> WL_O<227> ++ WL_O<226> WL_O<225> WL_O<224> WL_O<223> WL_O<222> WL_O<221> WL_O<220> ++ WL_O<219> WL_O<218> WL_O<217> WL_O<216> WL_O<215> WL_O<214> WL_O<213> ++ WL_O<212> WL_O<211> WL_O<210> WL_O<209> WL_O<208> WL_O<207> WL_O<206> ++ WL_O<205> WL_O<204> WL_O<203> WL_O<202> WL_O<201> WL_O<200> WL_O<199> ++ WL_O<198> WL_O<197> WL_O<196> WL_O<195> WL_O<194> WL_O<193> WL_O<192> ++ WL_O<191> WL_O<190> WL_O<189> WL_O<188> WL_O<187> WL_O<186> WL_O<185> ++ WL_O<184> WL_O<183> WL_O<182> WL_O<181> WL_O<180> WL_O<179> WL_O<178> ++ WL_O<177> WL_O<176> WL_O<175> WL_O<174> WL_O<173> WL_O<172> WL_O<171> ++ WL_O<170> WL_O<169> WL_O<168> WL_O<167> WL_O<166> WL_O<165> WL_O<164> ++ WL_O<163> WL_O<162> WL_O<161> WL_O<160> WL_O<159> WL_O<158> WL_O<157> ++ WL_O<156> WL_O<155> WL_O<154> WL_O<153> WL_O<152> WL_O<151> WL_O<150> ++ WL_O<149> WL_O<148> WL_O<147> WL_O<146> WL_O<145> WL_O<144> WL_O<143> ++ WL_O<142> WL_O<141> WL_O<140> WL_O<139> WL_O<138> WL_O<137> WL_O<136> ++ WL_O<135> WL_O<134> WL_O<133> WL_O<132> WL_O<131> WL_O<130> WL_O<129> ++ WL_O<128> WL_O<127> WL_O<126> WL_O<125> WL_O<124> WL_O<123> WL_O<122> ++ WL_O<121> WL_O<120> WL_O<119> WL_O<118> WL_O<117> WL_O<116> WL_O<115> ++ WL_O<114> WL_O<113> WL_O<112> WL_O<111> WL_O<110> WL_O<109> WL_O<108> ++ WL_O<107> WL_O<106> WL_O<105> WL_O<104> WL_O<103> WL_O<102> WL_O<101> ++ WL_O<100> WL_O<99> WL_O<98> WL_O<97> WL_O<96> WL_O<95> WL_O<94> WL_O<93> ++ WL_O<92> WL_O<91> WL_O<90> WL_O<89> WL_O<88> WL_O<87> WL_O<86> WL_O<85> ++ WL_O<84> WL_O<83> WL_O<82> WL_O<81> WL_O<80> WL_O<79> WL_O<78> WL_O<77> ++ WL_O<76> WL_O<75> WL_O<74> WL_O<73> WL_O<72> WL_O<71> WL_O<70> WL_O<69> ++ WL_O<68> WL_O<67> WL_O<66> WL_O<65> WL_O<64> WL_O<63> WL_O<62> WL_O<61> ++ WL_O<60> WL_O<59> WL_O<58> WL_O<57> WL_O<56> WL_O<55> WL_O<54> WL_O<53> ++ WL_O<52> WL_O<51> WL_O<50> WL_O<49> WL_O<48> WL_O<47> WL_O<46> WL_O<45> ++ WL_O<44> WL_O<43> WL_O<42> WL_O<41> WL_O<40> WL_O<39> WL_O<38> WL_O<37> ++ WL_O<36> WL_O<35> WL_O<34> WL_O<33> WL_O<32> WL_O<31> WL_O<30> WL_O<29> ++ WL_O<28> WL_O<27> WL_O<26> WL_O<25> WL_O<24> WL_O<23> WL_O<22> WL_O<21> ++ WL_O<20> WL_O<19> WL_O<18> WL_O<17> WL_O<16> WL_O<15> WL_O<14> WL_O<13> ++ WL_O<12> WL_O<11> WL_O<10> WL_O<9> WL_O<8> WL_O<7> WL_O<6> WL_O<5> WL_O<4> ++ WL_O<3> WL_O<2> WL_O<1> WL_O<0> VDD VSS +XDEC11<4> ADDR_N_I<7> ADDR_N_I<6> CS_I CS04<3> VDD VSS / ++ RM_IHPSG13_512x32_c2_2P_DEC03 +XDEC11<3> ADDR_N_I<5> ADDR_N_I<4> CS04<3> CS00<15> VDD VSS / ++ RM_IHPSG13_512x32_c2_2P_DEC03 +XDEC11<2> ADDR_N_I<5> ADDR_N_I<4> CS04<2> CS00<11> VDD VSS / ++ RM_IHPSG13_512x32_c2_2P_DEC03 +XDEC11<1> ADDR_N_I<5> ADDR_N_I<4> CS04<1> CS00<7> VDD VSS / ++ RM_IHPSG13_512x32_c2_2P_DEC03 +XDEC11<0> ADDR_N_I<5> ADDR_N_I<4> CS04<0> CS00<3> VDD VSS / ++ RM_IHPSG13_512x32_c2_2P_DEC03 +XSEL<15> ADDR_N_I<3> ADDR_N_I<2> ADDR_N_I<1> ADDR_N_I<0> CS00<15> ECLK_H<15> ++ ECLK_H<16> ECLK_B<15> ECLK_B<16> WL_O<255> WL_O<254> WL_O<253> WL_O<252> ++ WL_O<251> WL_O<250> WL_O<249> WL_O<248> WL_O<247> WL_O<246> WL_O<245> ++ WL_O<244> WL_O<243> WL_O<242> WL_O<241> WL_O<240> VDD VSS / ++ RM_IHPSG13_512x32_c2_2P_DEC04 +XSEL<14> ADDR_N_I<3> ADDR_N_I<2> ADDR_N_I<1> ADDR_N_I<0> CS00<14> ECLK_H<14> ++ ECLK_H<15> ECLK_B<14> ECLK_B<15> WL_O<239> WL_O<238> WL_O<237> WL_O<236> ++ WL_O<235> WL_O<234> WL_O<233> WL_O<232> WL_O<231> WL_O<230> WL_O<229> ++ WL_O<228> WL_O<227> WL_O<226> WL_O<225> WL_O<224> VDD VSS / ++ RM_IHPSG13_512x32_c2_2P_DEC04 +XSEL<13> ADDR_N_I<3> ADDR_N_I<2> ADDR_N_I<1> ADDR_N_I<0> CS00<13> ECLK_H<13> ++ ECLK_H<14> ECLK_B<13> ECLK_B<14> WL_O<223> WL_O<222> WL_O<221> WL_O<220> ++ WL_O<219> WL_O<218> WL_O<217> WL_O<216> WL_O<215> WL_O<214> WL_O<213> ++ WL_O<212> WL_O<211> WL_O<210> WL_O<209> WL_O<208> VDD VSS / ++ RM_IHPSG13_512x32_c2_2P_DEC04 +XSEL<12> ADDR_N_I<3> ADDR_N_I<2> ADDR_N_I<1> ADDR_N_I<0> CS00<12> ECLK_H<12> ++ ECLK_H<13> ECLK_B<12> ECLK_B<13> WL_O<207> WL_O<206> WL_O<205> WL_O<204> ++ WL_O<203> WL_O<202> WL_O<201> WL_O<200> WL_O<199> WL_O<198> WL_O<197> ++ WL_O<196> WL_O<195> WL_O<194> WL_O<193> WL_O<192> VDD VSS / ++ RM_IHPSG13_512x32_c2_2P_DEC04 +XSEL<11> ADDR_N_I<3> ADDR_N_I<2> ADDR_N_I<1> ADDR_N_I<0> CS00<11> ECLK_H<11> ++ ECLK_H<12> ECLK_B<11> ECLK_B<12> WL_O<191> WL_O<190> WL_O<189> WL_O<188> ++ WL_O<187> WL_O<186> WL_O<185> WL_O<184> WL_O<183> WL_O<182> WL_O<181> ++ WL_O<180> WL_O<179> WL_O<178> WL_O<177> WL_O<176> VDD VSS / ++ RM_IHPSG13_512x32_c2_2P_DEC04 +XSEL<10> ADDR_N_I<3> ADDR_N_I<2> ADDR_N_I<1> ADDR_N_I<0> CS00<10> ECLK_H<10> ++ ECLK_H<11> ECLK_B<10> ECLK_B<11> WL_O<175> WL_O<174> WL_O<173> WL_O<172> ++ WL_O<171> WL_O<170> WL_O<169> WL_O<168> WL_O<167> WL_O<166> WL_O<165> ++ WL_O<164> WL_O<163> WL_O<162> WL_O<161> WL_O<160> VDD VSS / ++ RM_IHPSG13_512x32_c2_2P_DEC04 +XSEL<9> ADDR_N_I<3> ADDR_N_I<2> ADDR_N_I<1> ADDR_N_I<0> CS00<9> ECLK_H<9> ++ ECLK_H<10> ECLK_B<9> ECLK_B<10> WL_O<159> WL_O<158> WL_O<157> WL_O<156> ++ WL_O<155> WL_O<154> WL_O<153> WL_O<152> WL_O<151> WL_O<150> WL_O<149> ++ WL_O<148> WL_O<147> WL_O<146> WL_O<145> WL_O<144> VDD VSS / ++ RM_IHPSG13_512x32_c2_2P_DEC04 +XSEL<8> ADDR_N_I<3> ADDR_N_I<2> ADDR_N_I<1> ADDR_N_I<0> CS00<8> ECLK_H<8> ++ ECLK_H<9> ECLK_B<8> ECLK_B<9> WL_O<143> WL_O<142> WL_O<141> WL_O<140> ++ WL_O<139> WL_O<138> WL_O<137> WL_O<136> WL_O<135> WL_O<134> WL_O<133> ++ WL_O<132> WL_O<131> WL_O<130> WL_O<129> WL_O<128> VDD VSS / ++ RM_IHPSG13_512x32_c2_2P_DEC04 +XSEL<7> ADDR_N_I<3> ADDR_N_I<2> ADDR_N_I<1> ADDR_N_I<0> CS00<7> ECLK_H<7> ++ ECLK_H<8> ECLK_B<7> ECLK_B<8> WL_O<127> WL_O<126> WL_O<125> WL_O<124> ++ WL_O<123> WL_O<122> WL_O<121> WL_O<120> WL_O<119> WL_O<118> WL_O<117> ++ WL_O<116> WL_O<115> WL_O<114> WL_O<113> WL_O<112> VDD VSS / ++ RM_IHPSG13_512x32_c2_2P_DEC04 +XSEL<6> ADDR_N_I<3> ADDR_N_I<2> ADDR_N_I<1> ADDR_N_I<0> CS00<6> ECLK_H<6> ++ ECLK_H<7> ECLK_B<6> ECLK_B<7> WL_O<111> WL_O<110> WL_O<109> WL_O<108> ++ WL_O<107> WL_O<106> WL_O<105> WL_O<104> WL_O<103> WL_O<102> WL_O<101> ++ WL_O<100> WL_O<99> WL_O<98> WL_O<97> WL_O<96> VDD VSS / ++ RM_IHPSG13_512x32_c2_2P_DEC04 +XSEL<5> ADDR_N_I<3> ADDR_N_I<2> ADDR_N_I<1> ADDR_N_I<0> CS00<5> ECLK_H<5> ++ ECLK_H<6> ECLK_B<5> ECLK_B<6> WL_O<95> WL_O<94> WL_O<93> WL_O<92> WL_O<91> ++ WL_O<90> WL_O<89> WL_O<88> WL_O<87> WL_O<86> WL_O<85> WL_O<84> WL_O<83> ++ WL_O<82> WL_O<81> WL_O<80> VDD VSS / RM_IHPSG13_512x32_c2_2P_DEC04 +XSEL<4> ADDR_N_I<3> ADDR_N_I<2> ADDR_N_I<1> ADDR_N_I<0> CS00<4> ECLK_H<4> ++ ECLK_H<5> ECLK_B<4> ECLK_B<5> WL_O<79> WL_O<78> WL_O<77> WL_O<76> WL_O<75> ++ WL_O<74> WL_O<73> WL_O<72> WL_O<71> WL_O<70> WL_O<69> WL_O<68> WL_O<67> ++ WL_O<66> WL_O<65> WL_O<64> VDD VSS / RM_IHPSG13_512x32_c2_2P_DEC04 +XSEL<3> ADDR_N_I<3> ADDR_N_I<2> ADDR_N_I<1> ADDR_N_I<0> CS00<3> ECLK_H<3> ++ ECLK_H<4> ECLK_B<3> ECLK_B<4> WL_O<63> WL_O<62> WL_O<61> WL_O<60> WL_O<59> ++ WL_O<58> WL_O<57> WL_O<56> WL_O<55> WL_O<54> WL_O<53> WL_O<52> WL_O<51> ++ WL_O<50> WL_O<49> WL_O<48> VDD VSS / RM_IHPSG13_512x32_c2_2P_DEC04 +XSEL<2> ADDR_N_I<3> ADDR_N_I<2> ADDR_N_I<1> ADDR_N_I<0> CS00<2> ECLK_H<2> ++ ECLK_H<3> ECLK_B<2> ECLK_B<3> WL_O<47> WL_O<46> WL_O<45> WL_O<44> WL_O<43> ++ WL_O<42> WL_O<41> WL_O<40> WL_O<39> WL_O<38> WL_O<37> WL_O<36> WL_O<35> ++ WL_O<34> WL_O<33> WL_O<32> VDD VSS / RM_IHPSG13_512x32_c2_2P_DEC04 +XSEL<1> ADDR_N_I<3> ADDR_N_I<2> ADDR_N_I<1> ADDR_N_I<0> CS00<1> ECLK_H<1> ++ ECLK_H<2> ECLK_B<1> ECLK_B<2> WL_O<31> WL_O<30> WL_O<29> WL_O<28> WL_O<27> ++ WL_O<26> WL_O<25> WL_O<24> WL_O<23> WL_O<22> WL_O<21> WL_O<20> WL_O<19> ++ WL_O<18> WL_O<17> WL_O<16> VDD VSS / RM_IHPSG13_512x32_c2_2P_DEC04 +XSEL<0> ADDR_N_I<3> ADDR_N_I<2> ADDR_N_I<1> ADDR_N_I<0> CS00<0> ECLK_I ++ ECLK_H<1> ECLK_B<0> ECLK_B<1> WL_O<15> WL_O<14> WL_O<13> WL_O<12> WL_O<11> ++ WL_O<10> WL_O<9> WL_O<8> WL_O<7> WL_O<6> WL_O<5> WL_O<4> WL_O<3> WL_O<2> ++ WL_O<1> WL_O<0> VDD VSS / RM_IHPSG13_512x32_c2_2P_DEC04 +XDEC10<4> ADDR_N_I<7> ADDR_N_I<6> CS_I CS04<2> VDD VSS / ++ RM_IHPSG13_512x32_c2_2P_DEC02 +XDEC10<3> ADDR_N_I<5> ADDR_N_I<4> CS04<3> CS00<14> VDD VSS / ++ RM_IHPSG13_512x32_c2_2P_DEC02 +XDEC10<2> ADDR_N_I<5> ADDR_N_I<4> CS04<2> CS00<10> VDD VSS / ++ RM_IHPSG13_512x32_c2_2P_DEC02 +XDEC10<1> ADDR_N_I<5> ADDR_N_I<4> CS04<1> CS00<6> VDD VSS / ++ RM_IHPSG13_512x32_c2_2P_DEC02 +XDEC10<0> ADDR_N_I<5> ADDR_N_I<4> CS04<0> CS00<2> VDD VSS / ++ RM_IHPSG13_512x32_c2_2P_DEC02 +XL2<132> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<131> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<130> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<129> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<128> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<127> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<126> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<125> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<124> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<123> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<122> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<121> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<120> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<119> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<118> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<117> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<116> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<115> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<114> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<113> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<112> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<111> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<110> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<109> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<108> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<107> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<106> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<105> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<104> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<103> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<102> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<101> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<100> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<99> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<98> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<97> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<96> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<95> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<94> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<93> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<92> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<91> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<90> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<89> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<88> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<87> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<86> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<85> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<84> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<83> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<82> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<81> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<80> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<79> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<78> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<77> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<76> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<75> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<74> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<73> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<72> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<71> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<70> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<69> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<68> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<67> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<66> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<65> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<64> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<63> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<62> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<61> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<60> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<59> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<58> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<57> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<56> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<55> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<54> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<53> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<52> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<51> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<50> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<49> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<48> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<47> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<46> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<45> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<44> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<43> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<42> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<41> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<40> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<39> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<38> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<37> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<36> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<35> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<34> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<33> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<32> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<31> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<30> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<29> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<28> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<27> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<26> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<25> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<24> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<23> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<22> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<21> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<20> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<19> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<18> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<17> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<16> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<15> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<14> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<13> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<12> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<11> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<10> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<9> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<8> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<7> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<6> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<5> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<4> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<3> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<2> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<1> VDD VSS / RSC_IHPSG13_FILLCAP8 +XDEC00<4> ADDR_N_I<7> ADDR_N_I<6> CS_I CS04<0> VDD VSS / ++ RM_IHPSG13_512x32_c2_2P_DEC00 +XDEC00<3> ADDR_N_I<5> ADDR_N_I<4> CS04<3> CS00<12> VDD VSS / ++ RM_IHPSG13_512x32_c2_2P_DEC00 +XDEC00<2> ADDR_N_I<5> ADDR_N_I<4> CS04<2> CS00<8> VDD VSS / ++ RM_IHPSG13_512x32_c2_2P_DEC00 +XDEC00<1> ADDR_N_I<5> ADDR_N_I<4> CS04<1> CS00<4> VDD VSS / ++ RM_IHPSG13_512x32_c2_2P_DEC00 +XDEC00<0> ADDR_N_I<5> ADDR_N_I<4> CS04<0> CS00<0> VDD VSS / ++ RM_IHPSG13_512x32_c2_2P_DEC00 +XDEC01<4> ADDR_N_I<7> ADDR_N_I<6> CS_I CS04<1> VDD VSS / ++ RM_IHPSG13_512x32_c2_2P_DEC01 +XDEC01<3> ADDR_N_I<5> ADDR_N_I<4> CS04<3> CS00<13> VDD VSS / ++ RM_IHPSG13_512x32_c2_2P_DEC01 +XDEC01<2> ADDR_N_I<5> ADDR_N_I<4> CS04<2> CS00<9> VDD VSS / ++ RM_IHPSG13_512x32_c2_2P_DEC01 +XDEC01<1> ADDR_N_I<5> ADDR_N_I<4> CS04<1> CS00<5> VDD VSS / ++ RM_IHPSG13_512x32_c2_2P_DEC01 +XDEC01<0> ADDR_N_I<5> ADDR_N_I<4> CS04<0> CS00<1> VDD VSS / ++ RM_IHPSG13_512x32_c2_2P_DEC01 +.ENDS +.SUBCKT RM_IHPSG13_512x32_c2_2P_ROWREG8 ACLK_N_I ADDR_I<7> ADDR_I<6> ADDR_I<5> ADDR_I<4> ++ ADDR_I<3> ADDR_I<2> ADDR_I<1> ADDR_I<0> ADDR_N_O<7> ADDR_N_O<6> ADDR_N_O<5> ++ ADDR_N_O<4> ADDR_N_O<3> ADDR_N_O<2> ADDR_N_O<1> ADDR_N_O<0> BIST_ADDR_I<7> ++ BIST_ADDR_I<6> BIST_ADDR_I<5> BIST_ADDR_I<4> BIST_ADDR_I<3> BIST_ADDR_I<2> ++ BIST_ADDR_I<1> BIST_ADDR_I<0> BIST_EN_I VDD VSS +XINV<7> q_int<7> qn_int<7> VDD VSS / RSC_IHPSG13_CINVX2 +XINV<6> q_int<6> qn_int<6> VDD VSS / RSC_IHPSG13_CINVX2 +XINV<5> q_int<5> qn_int<5> VDD VSS / RSC_IHPSG13_CINVX2 +XINV<4> q_int<4> qn_int<4> VDD VSS / RSC_IHPSG13_CINVX2 +XINV<3> q_int<3> qn_int<3> VDD VSS / RSC_IHPSG13_CINVX2 +XINV<2> q_int<2> qn_int<2> VDD VSS / RSC_IHPSG13_CINVX2 +XINV<1> q_int<1> qn_int<1> VDD VSS / RSC_IHPSG13_CINVX2 +XINV<0> q_int<0> qn_int<0> VDD VSS / RSC_IHPSG13_CINVX2 +XDRV<7> qn_int<7> ADDR_N_O<7> VDD VSS / RSC_IHPSG13_CINVX8 +XDRV<6> qn_int<6> ADDR_N_O<6> VDD VSS / RSC_IHPSG13_CINVX8 +XDRV<5> qn_int<5> ADDR_N_O<5> VDD VSS / RSC_IHPSG13_CINVX8 +XDRV<4> qn_int<4> ADDR_N_O<4> VDD VSS / RSC_IHPSG13_CINVX8 +XDRV<3> qn_int<3> ADDR_N_O<3> VDD VSS / RSC_IHPSG13_CINVX8 +XDRV<2> qn_int<2> ADDR_N_O<2> VDD VSS / RSC_IHPSG13_CINVX8 +XDRV<1> qn_int<1> ADDR_N_O<1> VDD VSS / RSC_IHPSG13_CINVX8 +XDRV<0> qn_int<0> ADDR_N_O<0> VDD VSS / RSC_IHPSG13_CINVX8 +XDFF<7> BIST_EN_I BIST_ADDR_I<7> ACLK_N_I ADDR_I<7> q_int<7> net2<0> VDD ++ VSS / RSC_IHPSG13_DFNQMX2IX1 +XDFF<6> BIST_EN_I BIST_ADDR_I<6> ACLK_N_I ADDR_I<6> q_int<6> net2<1> VDD ++ VSS / RSC_IHPSG13_DFNQMX2IX1 +XDFF<5> BIST_EN_I BIST_ADDR_I<5> ACLK_N_I ADDR_I<5> q_int<5> net2<2> VDD ++ VSS / RSC_IHPSG13_DFNQMX2IX1 +XDFF<4> BIST_EN_I BIST_ADDR_I<4> ACLK_N_I ADDR_I<4> q_int<4> net2<3> VDD ++ VSS / RSC_IHPSG13_DFNQMX2IX1 +XDFF<3> BIST_EN_I BIST_ADDR_I<3> ACLK_N_I ADDR_I<3> q_int<3> net2<4> VDD ++ VSS / RSC_IHPSG13_DFNQMX2IX1 +XDFF<2> BIST_EN_I BIST_ADDR_I<2> ACLK_N_I ADDR_I<2> q_int<2> net2<5> VDD ++ VSS / RSC_IHPSG13_DFNQMX2IX1 +XDFF<1> BIST_EN_I BIST_ADDR_I<1> ACLK_N_I ADDR_I<1> q_int<1> net2<6> VDD ++ VSS / RSC_IHPSG13_DFNQMX2IX1 +XDFF<0> BIST_EN_I BIST_ADDR_I<0> ACLK_N_I ADDR_I<0> q_int<0> net2<7> VDD ++ VSS / RSC_IHPSG13_DFNQMX2IX1 +XI11<4> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI11<3> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI11<2> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI11<1> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI10 VDD VSS / RSC_IHPSG13_FILLCAP4 +.ENDS +.SUBCKT RM_IHPSG13_512x32_c2_2P_COLDEC4 ACLK_N ADDR<3> ADDR<2> ADDR<1> ADDR<0> ++ ADDR_COL<1> ADDR_COL<0> ADDR_DEC<7> ADDR_DEC<6> ADDR_DEC<5> ADDR_DEC<4> ++ ADDR_DEC<3> ADDR_DEC<2> ADDR_DEC<1> ADDR_DEC<0> BIST_ADDR<3> BIST_ADDR<2> ++ BIST_ADDR<1> BIST_ADDR<0> BIST_EN_I VDD VSS +XI1<7> PADR<0> PADR<1> PADR<2> addr_n<7> VDD VSS / RSC_IHPSG13_NAND3X2 +XI1<6> NADR<0> PADR<1> PADR<2> addr_n<6> VDD VSS / RSC_IHPSG13_NAND3X2 +XI1<5> PADR<0> NADR<1> PADR<2> addr_n<5> VDD VSS / RSC_IHPSG13_NAND3X2 +XI1<4> NADR<0> NADR<1> PADR<2> addr_n<4> VDD VSS / RSC_IHPSG13_NAND3X2 +XI1<3> PADR<0> PADR<1> NADR<2> addr_n<3> VDD VSS / RSC_IHPSG13_NAND3X2 +XI1<2> NADR<0> PADR<1> NADR<2> addr_n<2> VDD VSS / RSC_IHPSG13_NAND3X2 +XI1<1> PADR<0> NADR<1> NADR<2> addr_n<1> VDD VSS / RSC_IHPSG13_NAND3X2 +XI1<0> NADR<0> NADR<1> NADR<2> addr_n<0> VDD VSS / RSC_IHPSG13_NAND3X2 +XDFF<3> BIST_EN_I BIST_ADDR<3> ACLK_N ADDR<3> addr_int net12<0> VDD ++ VSS / RSC_IHPSG13_DFNQMX2IX1 +XDFF<2> BIST_EN_I BIST_ADDR<2> ACLK_N ADDR<2> padr_int<2> net12<1> VDD ++ VSS / RSC_IHPSG13_DFNQMX2IX1 +XDFF<1> BIST_EN_I BIST_ADDR<1> ACLK_N ADDR<1> padr_int<1> net12<2> VDD ++ VSS / RSC_IHPSG13_DFNQMX2IX1 +XDFF<0> BIST_EN_I BIST_ADDR<0> ACLK_N ADDR<0> padr_int<0> net12<3> VDD ++ VSS / RSC_IHPSG13_DFNQMX2IX1 +XI17<4> VDD VSS / RSC_IHPSG13_FILLCAP4 +XI17<3> VDD VSS / RSC_IHPSG13_FILLCAP4 +XI17<2> VDD VSS / RSC_IHPSG13_FILLCAP4 +XI17<1> VDD VSS / RSC_IHPSG13_FILLCAP4 +XI13<2> NADR<2> PADR<2> VDD VSS / RSC_IHPSG13_INVX2 +XI13<1> NADR<1> PADR<1> VDD VSS / RSC_IHPSG13_INVX2 +XI13<0> NADR<0> PADR<0> VDD VSS / RSC_IHPSG13_INVX2 +XI2<7> addr_n<7> ADDR_DEC<7> VDD VSS / RSC_IHPSG13_INVX2 +XI2<6> addr_n<6> ADDR_DEC<6> VDD VSS / RSC_IHPSG13_INVX2 +XI2<5> addr_n<5> ADDR_DEC<5> VDD VSS / RSC_IHPSG13_INVX2 +XI2<4> addr_n<4> ADDR_DEC<4> VDD VSS / RSC_IHPSG13_INVX2 +XI2<3> addr_n<3> ADDR_DEC<3> VDD VSS / RSC_IHPSG13_INVX2 +XI2<2> addr_n<2> ADDR_DEC<2> VDD VSS / RSC_IHPSG13_INVX2 +XI2<1> addr_n<1> ADDR_DEC<1> VDD VSS / RSC_IHPSG13_INVX2 +XI2<0> addr_n<0> ADDR_DEC<0> VDD VSS / RSC_IHPSG13_INVX2 +XI3<2> padr_int<2> NADR<2> VDD VSS / RSC_IHPSG13_INVX2 +XI3<1> padr_int<1> NADR<1> VDD VSS / RSC_IHPSG13_INVX2 +XI3<0> padr_int<0> NADR<0> VDD VSS / RSC_IHPSG13_INVX2 +XI14 addr_int ADDR_COL<0> VDD VSS / RSC_IHPSG13_CBUFX2 +XI16<8> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI16<7> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI16<6> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI16<5> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI16<4> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI16<3> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI16<2> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI16<1> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI15 ADDR_COL<1> VDD VSS / RSC_IHPSG13_TIEL +.ENDS +.SUBCKT RM_IHPSG13_512x32_c2_2P_COLCTRL4 A_ADDR_COL A_ADDR_DEC<7> A_ADDR_DEC<6> ++ A_ADDR_DEC<5> A_ADDR_DEC<4> A_ADDR_DEC<3> A_ADDR_DEC<2> A_ADDR_DEC<1> ++ A_ADDR_DEC<0> A_BIST_BM_I A_BIST_DW_I A_BIST_EN_I A_BLC<15> A_BLC<14> ++ A_BLC<13> A_BLC<12> A_BLC<11> A_BLC<10> A_BLC<9> A_BLC<8> A_BLC<7> A_BLC<6> ++ A_BLC<5> A_BLC<4> A_BLC<3> A_BLC<2> A_BLC<1> A_BLC<0> A_BLT<15> A_BLT<14> ++ A_BLT<13> A_BLT<12> A_BLT<11> A_BLT<10> A_BLT<9> A_BLT<8> A_BLT<7> A_BLT<6> ++ A_BLT<5> A_BLT<4> A_BLT<3> A_BLT<2> A_BLT<1> A_BLT<0> A_BM_I A_DCLK_B_L ++ A_DCLK_B_R A_DCLK_L A_DCLK_R A_DR_O A_DW_I A_RCLK_B_L A_RCLK_B_R A_RCLK_L ++ A_RCLK_R A_TIEH_O A_WCLK_B_L A_WCLK_B_R A_WCLK_L A_WCLK_R B_ADDR_COL ++ B_ADDR_DEC<7> B_ADDR_DEC<6> B_ADDR_DEC<5> B_ADDR_DEC<4> B_ADDR_DEC<3> ++ B_ADDR_DEC<2> B_ADDR_DEC<1> B_ADDR_DEC<0> B_BIST_BM_I B_BIST_DW_I ++ B_BIST_EN_I B_BLC<15> B_BLC<14> B_BLC<13> B_BLC<12> B_BLC<11> B_BLC<10> ++ B_BLC<9> B_BLC<8> B_BLC<7> B_BLC<6> B_BLC<5> B_BLC<4> B_BLC<3> B_BLC<2> ++ B_BLC<1> B_BLC<0> B_BLT<15> B_BLT<14> B_BLT<13> B_BLT<12> B_BLT<11> ++ B_BLT<10> B_BLT<9> B_BLT<8> B_BLT<7> B_BLT<6> B_BLT<5> B_BLT<4> B_BLT<3> ++ B_BLT<2> B_BLT<1> B_BLT<0> B_BM_I B_DCLK_B_L B_DCLK_B_R B_DCLK_L B_DCLK_R ++ B_DR_O B_DW_I B_RCLK_B_L B_RCLK_B_R B_RCLK_L B_RCLK_R B_TIEH_O B_WCLK_B_L ++ B_WCLK_B_R B_WCLK_L B_WCLK_R VDD VSS +XB_I80 B_RCLK_B_L B_WCLK_B_L net041 VDD VSS / RSC_IHPSG13_AND2X2 +XA_I80 A_RCLK_B_L A_WCLK_B_L net21 VDD VSS / RSC_IHPSG13_AND2X2 +XB_I76 B_DI_N B_DO_WRITE_P B_WR_ZERO VDD VSS / RSC_IHPSG13_AND2X4 +XB_I75 B_DI_R B_DO_WRITE_P B_WR_ONE VDD VSS / RSC_IHPSG13_AND2X4 +XA_I76 A_DI_N A_DO_WRITE_P A_WR_ZERO VDD VSS / RSC_IHPSG13_AND2X4 +XA_I75 A_DI_R A_DO_WRITE_P A_WR_ONE VDD VSS / RSC_IHPSG13_AND2X4 +XI_FILL4<26> VDD VSS / RSC_IHPSG13_FILLCAP4 +XI_FILL4<25> VDD VSS / RSC_IHPSG13_FILLCAP4 +XI_FILL4<24> VDD VSS / RSC_IHPSG13_FILLCAP4 +XI_FILL4<23> VDD VSS / RSC_IHPSG13_FILLCAP4 +XI_FILL4<22> VDD VSS / RSC_IHPSG13_FILLCAP4 +XI_FILL4<21> VDD VSS / RSC_IHPSG13_FILLCAP4 +XI_FILL4<20> VDD VSS / RSC_IHPSG13_FILLCAP4 +XI_FILL4<19> VDD VSS / RSC_IHPSG13_FILLCAP4 +XI_FILL4<18> VDD VSS / RSC_IHPSG13_FILLCAP4 +XI_FILL4<17> VDD VSS / RSC_IHPSG13_FILLCAP4 +XI_FILL4<16> VDD VSS / RSC_IHPSG13_FILLCAP4 +XI_FILL4<15> VDD VSS / RSC_IHPSG13_FILLCAP4 +XI_FILL4<14> VDD VSS / RSC_IHPSG13_FILLCAP4 +XI_FILL4<13> VDD VSS / RSC_IHPSG13_FILLCAP4 +XI_FILL4<12> VDD VSS / RSC_IHPSG13_FILLCAP4 +XI_FILL4<11> VDD VSS / RSC_IHPSG13_FILLCAP4 +XI_FILL4<10> VDD VSS / RSC_IHPSG13_FILLCAP4 +XI_FILL4<9> VDD VSS / RSC_IHPSG13_FILLCAP4 +XI_FILL4<8> VDD VSS / RSC_IHPSG13_FILLCAP4 +XI_FILL4<7> VDD VSS / RSC_IHPSG13_FILLCAP4 +XI_FILL4<6> VDD VSS / RSC_IHPSG13_FILLCAP4 +XI_FILL4<5> VDD VSS / RSC_IHPSG13_FILLCAP4 +XI_FILL4<4> VDD VSS / RSC_IHPSG13_FILLCAP4 +XI_FILL4<3> VDD VSS / RSC_IHPSG13_FILLCAP4 +XI_FILL4<2> VDD VSS / RSC_IHPSG13_FILLCAP4 +XI_FILL4<1> VDD VSS / RSC_IHPSG13_FILLCAP4 +XB_I69 B_DCLK_L B_DCLK_B_L VDD VSS / RSC_IHPSG13_CINVX4 +XB_I50 B_WCLK_L B_WCLK_B_L VDD VSS / RSC_IHPSG13_CINVX4 +XB_EBUF B_RCLK_L B_RCLK_B_L VDD VSS / RSC_IHPSG13_CINVX4 +XB_INV<1> B_N0 B_P0 VDD VSS / RSC_IHPSG13_CINVX4 +XB_INV<0> B_ADDR_COL B_N0 VDD VSS / RSC_IHPSG13_CINVX4 +XA_I69 A_DCLK_L A_DCLK_B_L VDD VSS / RSC_IHPSG13_CINVX4 +XA_I50 A_WCLK_L A_WCLK_B_L VDD VSS / RSC_IHPSG13_CINVX4 +XA_EBUF A_RCLK_L A_RCLK_B_L VDD VSS / RSC_IHPSG13_CINVX4 +XA_INV<1> A_N0 A_P0 VDD VSS / RSC_IHPSG13_CINVX4 +XA_INV<0> A_ADDR_COL A_N0 VDD VSS / RSC_IHPSG13_CINVX4 +XB_I81<1> net041 B_PRE_N VDD VSS / RSC_IHPSG13_CINVX4_WN +XB_I81<0> net041 B_PRE_N VDD VSS / RSC_IHPSG13_CINVX4_WN +XA_I81<1> net21 A_PRE_N VDD VSS / RSC_IHPSG13_CINVX4_WN +XA_I81<0> net21 A_PRE_N VDD VSS / RSC_IHPSG13_CINVX4_WN +XA_R2 A_RCLK_L A_RCLK_R / RSC_IHPSG13_MET3RES +XA_I87 A_WCLK_L A_WCLK_R / RSC_IHPSG13_MET3RES +XA_I88 A_DCLK_L A_DCLK_R / RSC_IHPSG13_MET3RES +XA_I89 A_DCLK_B_L A_DCLK_B_R / RSC_IHPSG13_MET3RES +XA_I90 A_WCLK_B_L A_WCLK_B_R / RSC_IHPSG13_MET3RES +XA_I91 A_RCLK_B_L A_RCLK_B_R / RSC_IHPSG13_MET3RES +XB_R2 B_RCLK_L B_RCLK_R / RSC_IHPSG13_MET3RES +XB_I87 B_WCLK_L B_WCLK_R / RSC_IHPSG13_MET3RES +XB_I88 B_DCLK_L B_DCLK_R / RSC_IHPSG13_MET3RES +XB_I89 B_DCLK_B_L B_DCLK_B_R / RSC_IHPSG13_MET3RES +XB_I90 B_WCLK_B_L B_WCLK_B_R / RSC_IHPSG13_MET3RES +XB_I91 B_RCLK_B_L B_RCLK_B_R / RSC_IHPSG13_MET3RES +XA_ISENSE A_SAE A_BLC_SEL A_BLT_SEL net19 net20 VDD VSS / ++ RSC_IHPSG13_DFPQD_MSAFFX2 +XB_ISENSE B_SAE B_BLC_SEL B_BLT_SEL net037 net038 VDD VSS / ++ RSC_IHPSG13_DFPQD_MSAFFX2 +XAB_BLMUX<3> A_BLC<15> A_BLC<14> A_BLC<13> A_BLC<12> A_BLC_SEL A_BLT<15> ++ A_BLT<14> A_BLT<13> A_BLT<12> A_BLT_SEL A_PRE_N A_SEL_P<15> A_SEL_P<14> ++ A_SEL_P<13> A_SEL_P<12> A_WR_ONE A_WR_ZERO B_BLC<15> B_BLC<14> B_BLC<13> ++ B_BLC<12> B_BLC_SEL B_BLT<15> B_BLT<14> B_BLT<13> B_BLT<12> B_BLT_SEL ++ B_PRE_N B_SEL_P<15> B_SEL_P<14> B_SEL_P<13> B_SEL_P<12> B_WR_ONE B_WR_ZERO ++ VDD VSS / RM_IHPSG13_512x32_c2_2P_BLDRV +XAB_BLMUX<2> A_BLC<11> A_BLC<10> A_BLC<9> A_BLC<8> A_BLC_SEL A_BLT<11> ++ A_BLT<10> A_BLT<9> A_BLT<8> A_BLT_SEL A_PRE_N A_SEL_P<11> A_SEL_P<10> ++ A_SEL_P<9> A_SEL_P<8> A_WR_ONE A_WR_ZERO B_BLC<11> B_BLC<10> B_BLC<9> ++ B_BLC<8> B_BLC_SEL B_BLT<11> B_BLT<10> B_BLT<9> B_BLT<8> B_BLT_SEL B_PRE_N ++ B_SEL_P<11> B_SEL_P<10> B_SEL_P<9> B_SEL_P<8> B_WR_ONE B_WR_ZERO VDD ++ VSS / RM_IHPSG13_512x32_c2_2P_BLDRV +XAB_BLMUX<1> A_BLC<7> A_BLC<6> A_BLC<5> A_BLC<4> A_BLC_SEL A_BLT<7> A_BLT<6> ++ A_BLT<5> A_BLT<4> A_BLT_SEL A_PRE_N A_SEL_P<7> A_SEL_P<6> A_SEL_P<5> ++ A_SEL_P<4> A_WR_ONE A_WR_ZERO B_BLC<7> B_BLC<6> B_BLC<5> B_BLC<4> B_BLC_SEL ++ B_BLT<7> B_BLT<6> B_BLT<5> B_BLT<4> B_BLT_SEL B_PRE_N B_SEL_P<7> B_SEL_P<6> ++ B_SEL_P<5> B_SEL_P<4> B_WR_ONE B_WR_ZERO VDD VSS / ++ RM_IHPSG13_512x32_c2_2P_BLDRV +XAB_BLMUX<0> A_BLC<3> A_BLC<2> A_BLC<1> A_BLC<0> A_BLC_SEL A_BLT<3> A_BLT<2> ++ A_BLT<1> A_BLT<0> A_BLT_SEL A_PRE_N A_SEL_P<3> A_SEL_P<2> A_SEL_P<1> ++ A_SEL_P<0> A_WR_ONE A_WR_ZERO B_BLC<3> B_BLC<2> B_BLC<1> B_BLC<0> B_BLC_SEL ++ B_BLT<3> B_BLT<2> B_BLT<1> B_BLT<0> B_BLT_SEL B_PRE_N B_SEL_P<3> B_SEL_P<2> ++ B_SEL_P<1> B_SEL_P<0> B_WR_ONE B_WR_ZERO VDD VSS / ++ RM_IHPSG13_512x32_c2_2P_BLDRV +XA_I51 net19 A_DR_O VDD VSS / RSC_IHPSG13_INVX4 +XB_I51 net037 B_DR_O VDD VSS / RSC_IHPSG13_INVX4 +XA_I78 A_RCLK_B_L A_SAE VDD VSS / RSC_IHPSG13_CBUFX2 +XB_I78 B_RCLK_B_L B_SAE VDD VSS / RSC_IHPSG13_CBUFX2 +XA_DREG A_BIST_EN_I A_BIST_DW_I A_DCLK_B_L A_DW_I A_DI_R net22 VDD VSS ++ / RSC_IHPSG13_DFNQMX2IX1 +XB_DREG B_BIST_EN_I B_BIST_DW_I B_DCLK_B_L B_DW_I B_DI_R net046 VDD ++ VSS / RSC_IHPSG13_DFNQMX2IX1 +XB_BREG B_BIST_EN_I B_BIST_BM_I B_DCLK_B_L B_BM_I B_BM_R net045 VDD ++ VSS / RSC_IHPSG13_DFNQMX2IX1 +XA_BREG A_BIST_EN_I A_BIST_BM_I A_DCLK_B_L A_BM_I A_BM_R net24 VDD VSS ++ / RSC_IHPSG13_DFNQMX2IX1 +XA_DEC3INV<15> net23<0> A_SEL_P<15> VDD VSS / RSC_IHPSG13_INVX2 +XA_DEC3INV<14> net23<1> A_SEL_P<14> VDD VSS / RSC_IHPSG13_INVX2 +XA_DEC3INV<13> net23<2> A_SEL_P<13> VDD VSS / RSC_IHPSG13_INVX2 +XA_DEC3INV<12> net23<3> A_SEL_P<12> VDD VSS / RSC_IHPSG13_INVX2 +XA_DEC3INV<11> net23<4> A_SEL_P<11> VDD VSS / RSC_IHPSG13_INVX2 +XA_DEC3INV<10> net23<5> A_SEL_P<10> VDD VSS / RSC_IHPSG13_INVX2 +XA_DEC3INV<9> net23<6> A_SEL_P<9> VDD VSS / RSC_IHPSG13_INVX2 +XA_DEC3INV<8> net23<7> A_SEL_P<8> VDD VSS / RSC_IHPSG13_INVX2 +XA_DEC3INV<7> net23<8> A_SEL_P<7> VDD VSS / RSC_IHPSG13_INVX2 +XA_DEC3INV<6> net23<9> A_SEL_P<6> VDD VSS / RSC_IHPSG13_INVX2 +XA_DEC3INV<5> net23<10> A_SEL_P<5> VDD VSS / RSC_IHPSG13_INVX2 +XA_DEC3INV<4> net23<11> A_SEL_P<4> VDD VSS / RSC_IHPSG13_INVX2 +XA_DEC3INV<3> net23<12> A_SEL_P<3> VDD VSS / RSC_IHPSG13_INVX2 +XA_DEC3INV<2> net23<13> A_SEL_P<2> VDD VSS / RSC_IHPSG13_INVX2 +XA_DEC3INV<1> net23<14> A_SEL_P<1> VDD VSS / RSC_IHPSG13_INVX2 +XA_DEC3INV<0> net23<15> A_SEL_P<0> VDD VSS / RSC_IHPSG13_INVX2 +XA_I83 A_BM_R A_BM_N VDD VSS / RSC_IHPSG13_INVX2 +XA_I49 A_DI_R A_DI_N VDD VSS / RSC_IHPSG13_INVX2 +XB_DEC3INV<15> net044<0> B_SEL_P<15> VDD VSS / RSC_IHPSG13_INVX2 +XB_DEC3INV<14> net044<1> B_SEL_P<14> VDD VSS / RSC_IHPSG13_INVX2 +XB_DEC3INV<13> net044<2> B_SEL_P<13> VDD VSS / RSC_IHPSG13_INVX2 +XB_DEC3INV<12> net044<3> B_SEL_P<12> VDD VSS / RSC_IHPSG13_INVX2 +XB_DEC3INV<11> net044<4> B_SEL_P<11> VDD VSS / RSC_IHPSG13_INVX2 +XB_DEC3INV<10> net044<5> B_SEL_P<10> VDD VSS / RSC_IHPSG13_INVX2 +XB_DEC3INV<9> net044<6> B_SEL_P<9> VDD VSS / RSC_IHPSG13_INVX2 +XB_DEC3INV<8> net044<7> B_SEL_P<8> VDD VSS / RSC_IHPSG13_INVX2 +XB_DEC3INV<7> net044<8> B_SEL_P<7> VDD VSS / RSC_IHPSG13_INVX2 +XB_DEC3INV<6> net044<9> B_SEL_P<6> VDD VSS / RSC_IHPSG13_INVX2 +XB_DEC3INV<5> net044<10> B_SEL_P<5> VDD VSS / RSC_IHPSG13_INVX2 +XB_DEC3INV<4> net044<11> B_SEL_P<4> VDD VSS / RSC_IHPSG13_INVX2 +XB_DEC3INV<3> net044<12> B_SEL_P<3> VDD VSS / RSC_IHPSG13_INVX2 +XB_DEC3INV<2> net044<13> B_SEL_P<2> VDD VSS / RSC_IHPSG13_INVX2 +XB_DEC3INV<1> net044<14> B_SEL_P<1> VDD VSS / RSC_IHPSG13_INVX2 +XB_DEC3INV<0> net044<15> B_SEL_P<0> VDD VSS / RSC_IHPSG13_INVX2 +XB_I83 B_BM_R B_BM_N VDD VSS / RSC_IHPSG13_INVX2 +XB_I49 B_DI_R B_DI_N VDD VSS / RSC_IHPSG13_INVX2 +XI_FILL8<20> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI_FILL8<19> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI_FILL8<18> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI_FILL8<17> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI_FILL8<16> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI_FILL8<15> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI_FILL8<14> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI_FILL8<13> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI_FILL8<12> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI_FILL8<11> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI_FILL8<10> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI_FILL8<9> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI_FILL8<8> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI_FILL8<7> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI_FILL8<6> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI_FILL8<5> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI_FILL8<4> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI_FILL8<3> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI_FILL8<2> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI_FILL8<1> VDD VSS / RSC_IHPSG13_FILLCAP8 +XA_I44 A_BM_N A_WCLK_B_L A_DO_WRITE_P VDD VSS / RSC_IHPSG13_NOR2X2 +XB_I44 B_BM_N B_WCLK_B_L B_DO_WRITE_P VDD VSS / RSC_IHPSG13_NOR2X2 +XA_DEC3<15> A_P0 A_ADDR_DEC<7> net23<0> VDD VSS / RSC_IHPSG13_NAND2X2 +XA_DEC3<14> A_P0 A_ADDR_DEC<6> net23<1> VDD VSS / RSC_IHPSG13_NAND2X2 +XA_DEC3<13> A_P0 A_ADDR_DEC<5> net23<2> VDD VSS / RSC_IHPSG13_NAND2X2 +XA_DEC3<12> A_P0 A_ADDR_DEC<4> net23<3> VDD VSS / RSC_IHPSG13_NAND2X2 +XA_DEC3<11> A_P0 A_ADDR_DEC<3> net23<4> VDD VSS / RSC_IHPSG13_NAND2X2 +XA_DEC3<10> A_P0 A_ADDR_DEC<2> net23<5> VDD VSS / RSC_IHPSG13_NAND2X2 +XA_DEC3<9> A_P0 A_ADDR_DEC<1> net23<6> VDD VSS / RSC_IHPSG13_NAND2X2 +XA_DEC3<8> A_P0 A_ADDR_DEC<0> net23<7> VDD VSS / RSC_IHPSG13_NAND2X2 +XA_DEC3<7> A_N0 A_ADDR_DEC<7> net23<8> VDD VSS / RSC_IHPSG13_NAND2X2 +XA_DEC3<6> A_N0 A_ADDR_DEC<6> net23<9> VDD VSS / RSC_IHPSG13_NAND2X2 +XA_DEC3<5> A_N0 A_ADDR_DEC<5> net23<10> VDD VSS / RSC_IHPSG13_NAND2X2 +XA_DEC3<4> A_N0 A_ADDR_DEC<4> net23<11> VDD VSS / RSC_IHPSG13_NAND2X2 +XA_DEC3<3> A_N0 A_ADDR_DEC<3> net23<12> VDD VSS / RSC_IHPSG13_NAND2X2 +XA_DEC3<2> A_N0 A_ADDR_DEC<2> net23<13> VDD VSS / RSC_IHPSG13_NAND2X2 +XA_DEC3<1> A_N0 A_ADDR_DEC<1> net23<14> VDD VSS / RSC_IHPSG13_NAND2X2 +XA_DEC3<0> A_N0 A_ADDR_DEC<0> net23<15> VDD VSS / RSC_IHPSG13_NAND2X2 +XB_DEC3<15> B_P0 B_ADDR_DEC<7> net044<0> VDD VSS / RSC_IHPSG13_NAND2X2 +XB_DEC3<14> B_P0 B_ADDR_DEC<6> net044<1> VDD VSS / RSC_IHPSG13_NAND2X2 +XB_DEC3<13> B_P0 B_ADDR_DEC<5> net044<2> VDD VSS / RSC_IHPSG13_NAND2X2 +XB_DEC3<12> B_P0 B_ADDR_DEC<4> net044<3> VDD VSS / RSC_IHPSG13_NAND2X2 +XB_DEC3<11> B_P0 B_ADDR_DEC<3> net044<4> VDD VSS / RSC_IHPSG13_NAND2X2 +XB_DEC3<10> B_P0 B_ADDR_DEC<2> net044<5> VDD VSS / RSC_IHPSG13_NAND2X2 +XB_DEC3<9> B_P0 B_ADDR_DEC<1> net044<6> VDD VSS / RSC_IHPSG13_NAND2X2 +XB_DEC3<8> B_P0 B_ADDR_DEC<0> net044<7> VDD VSS / RSC_IHPSG13_NAND2X2 +XB_DEC3<7> B_N0 B_ADDR_DEC<7> net044<8> VDD VSS / RSC_IHPSG13_NAND2X2 +XB_DEC3<6> B_N0 B_ADDR_DEC<6> net044<9> VDD VSS / RSC_IHPSG13_NAND2X2 +XB_DEC3<5> B_N0 B_ADDR_DEC<5> net044<10> VDD VSS / RSC_IHPSG13_NAND2X2 +XB_DEC3<4> B_N0 B_ADDR_DEC<4> net044<11> VDD VSS / RSC_IHPSG13_NAND2X2 +XB_DEC3<3> B_N0 B_ADDR_DEC<3> net044<12> VDD VSS / RSC_IHPSG13_NAND2X2 +XB_DEC3<2> B_N0 B_ADDR_DEC<2> net044<13> VDD VSS / RSC_IHPSG13_NAND2X2 +XB_DEC3<1> B_N0 B_ADDR_DEC<1> net044<14> VDD VSS / RSC_IHPSG13_NAND2X2 +XB_DEC3<0> B_N0 B_ADDR_DEC<0> net044<15> VDD VSS / RSC_IHPSG13_NAND2X2 +XB_BM_TIEH B_TIEH_O VDD VSS / RSC_IHPSG13_TIEH +XA_BM_TIEH A_TIEH_O VDD VSS / RSC_IHPSG13_TIEH +.ENDS + + +.SUBCKT RM_IHPSG13_512x32_c2_2P_ROWDEC5 ADDR_N_I<4> ADDR_N_I<3> ADDR_N_I<2> ADDR_N_I<1> ++ ADDR_N_I<0> CS_I ECLK_I WL_O<31> WL_O<30> WL_O<29> WL_O<28> WL_O<27> ++ WL_O<26> WL_O<25> WL_O<24> WL_O<23> WL_O<22> WL_O<21> WL_O<20> WL_O<19> ++ WL_O<18> WL_O<17> WL_O<16> WL_O<15> WL_O<14> WL_O<13> WL_O<12> WL_O<11> ++ WL_O<10> WL_O<9> WL_O<8> WL_O<7> WL_O<6> WL_O<5> WL_O<4> WL_O<3> WL_O<2> ++ WL_O<1> WL_O<0> VDD VSS +XDEC00 ADDR_N_I<5> ADDR_N_I<4> CS_I CS00<0> VDD VSS / ++ RM_IHPSG13_512x32_c2_2P_DEC00 +XSEL<1> ADDR_N_I<3> ADDR_N_I<2> ADDR_N_I<1> ADDR_N_I<0> CS00<1> ECLK_H<1> ++ ECLK_H<2> ECLK_B<1> ECLK_B<2> WL_O<31> WL_O<30> WL_O<29> WL_O<28> WL_O<27> ++ WL_O<26> WL_O<25> WL_O<24> WL_O<23> WL_O<22> WL_O<21> WL_O<20> WL_O<19> ++ WL_O<18> WL_O<17> WL_O<16> VDD VSS / RM_IHPSG13_512x32_c2_2P_DEC04 +XSEL<0> ADDR_N_I<3> ADDR_N_I<2> ADDR_N_I<1> ADDR_N_I<0> CS00<0> ECLK_I ++ ECLK_H<1> ECLK_B<0> ECLK_B<1> WL_O<15> WL_O<14> WL_O<13> WL_O<12> WL_O<11> ++ WL_O<10> WL_O<9> WL_O<8> WL_O<7> WL_O<6> WL_O<5> WL_O<4> WL_O<3> WL_O<2> ++ WL_O<1> WL_O<0> VDD VSS / RM_IHPSG13_512x32_c2_2P_DEC04 +XDEC01 ADDR_N_I<5> ADDR_N_I<4> CS_I CS00<1> VDD VSS / ++ RM_IHPSG13_512x32_c2_2P_DEC01 +XL2<18> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<17> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<16> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<15> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<14> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<13> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<12> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<11> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<10> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<9> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<8> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<7> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<6> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<5> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<4> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<3> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<2> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<1> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI0 ADDR_N_I<5> VDD VSS / RSC_IHPSG13_TIEL +.ENDS +.SUBCKT RM_IHPSG13_512x32_c2_2P_ROWREG5 ACLK_N_I ADDR_I<4> ADDR_I<3> ADDR_I<2> ADDR_I<1> ++ ADDR_I<0> ADDR_N_O<4> ADDR_N_O<3> ADDR_N_O<2> ADDR_N_O<1> ADDR_N_O<0> ++ BIST_ADDR_I<4> BIST_ADDR_I<3> BIST_ADDR_I<2> BIST_ADDR_I<1> BIST_ADDR_I<0> ++ BIST_EN_I VDD VSS +XINV<4> q_int<4> qn_int<4> VDD VSS / RSC_IHPSG13_CINVX2 +XINV<3> q_int<3> qn_int<3> VDD VSS / RSC_IHPSG13_CINVX2 +XINV<2> q_int<2> qn_int<2> VDD VSS / RSC_IHPSG13_CINVX2 +XINV<1> q_int<1> qn_int<1> VDD VSS / RSC_IHPSG13_CINVX2 +XINV<0> q_int<0> qn_int<0> VDD VSS / RSC_IHPSG13_CINVX2 +XDRV<4> qn_int<4> ADDR_N_O<4> VDD VSS / RSC_IHPSG13_CINVX8 +XDRV<3> qn_int<3> ADDR_N_O<3> VDD VSS / RSC_IHPSG13_CINVX8 +XDRV<2> qn_int<2> ADDR_N_O<2> VDD VSS / RSC_IHPSG13_CINVX8 +XDRV<1> qn_int<1> ADDR_N_O<1> VDD VSS / RSC_IHPSG13_CINVX8 +XDRV<0> qn_int<0> ADDR_N_O<0> VDD VSS / RSC_IHPSG13_CINVX8 +XDFF<4> BIST_EN_I BIST_ADDR_I<4> ACLK_N_I ADDR_I<4> q_int<4> net2<0> VDD ++ VSS / RSC_IHPSG13_DFNQMX2IX1 +XDFF<3> BIST_EN_I BIST_ADDR_I<3> ACLK_N_I ADDR_I<3> q_int<3> net2<1> VDD ++ VSS / RSC_IHPSG13_DFNQMX2IX1 +XDFF<2> BIST_EN_I BIST_ADDR_I<2> ACLK_N_I ADDR_I<2> q_int<2> net2<2> VDD ++ VSS / RSC_IHPSG13_DFNQMX2IX1 +XDFF<1> BIST_EN_I BIST_ADDR_I<1> ACLK_N_I ADDR_I<1> q_int<1> net2<3> VDD ++ VSS / RSC_IHPSG13_DFNQMX2IX1 +XDFF<0> BIST_EN_I BIST_ADDR_I<0> ACLK_N_I ADDR_I<0> q_int<0> net2<4> VDD ++ VSS / RSC_IHPSG13_DFNQMX2IX1 +XI11<16> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI11<15> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI11<14> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI11<13> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI11<12> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI11<11> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI11<10> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI11<9> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI11<8> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI11<7> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI11<6> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI11<5> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI11<4> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI11<3> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI11<2> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI11<1> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI12<3> VDD VSS / RSC_IHPSG13_FILLCAP4 +XI12<2> VDD VSS / RSC_IHPSG13_FILLCAP4 +XI12<1> VDD VSS / RSC_IHPSG13_FILLCAP4 +XI12<0> VDD VSS / RSC_IHPSG13_FILLCAP4 +.ENDS + + +.SUBCKT RM_IHPSG13_512x32_c2_2P_COLDEC3 ACLK_N ADDR<2> ADDR<1> ADDR<0> ADDR_COL<1> ++ ADDR_COL<0> ADDR_DEC<7> ADDR_DEC<6> ADDR_DEC<5> ADDR_DEC<4> ADDR_DEC<3> ++ ADDR_DEC<2> ADDR_DEC<1> ADDR_DEC<0> BIST_ADDR<2> BIST_ADDR<1> BIST_ADDR<0> ++ BIST_EN_I VDD VSS +XI1<7> PADR<0> PADR<1> PADR<2> addr_n<7> VDD VSS / RSC_IHPSG13_NAND3X2 +XI1<6> NADR<0> PADR<1> PADR<2> addr_n<6> VDD VSS / RSC_IHPSG13_NAND3X2 +XI1<5> PADR<0> NADR<1> PADR<2> addr_n<5> VDD VSS / RSC_IHPSG13_NAND3X2 +XI1<4> NADR<0> NADR<1> PADR<2> addr_n<4> VDD VSS / RSC_IHPSG13_NAND3X2 +XI1<3> PADR<0> PADR<1> NADR<2> addr_n<3> VDD VSS / RSC_IHPSG13_NAND3X2 +XI1<2> NADR<0> PADR<1> NADR<2> addr_n<2> VDD VSS / RSC_IHPSG13_NAND3X2 +XI1<1> PADR<0> NADR<1> NADR<2> addr_n<1> VDD VSS / RSC_IHPSG13_NAND3X2 +XI1<0> NADR<0> NADR<1> NADR<2> addr_n<0> VDD VSS / RSC_IHPSG13_NAND3X2 +XDFF<2> BIST_EN_I BIST_ADDR<2> ACLK_N ADDR<2> padr_int<2> net13<0> VDD ++ VSS / RSC_IHPSG13_DFNQMX2IX1 +XDFF<1> BIST_EN_I BIST_ADDR<1> ACLK_N ADDR<1> padr_int<1> net13<1> VDD ++ VSS / RSC_IHPSG13_DFNQMX2IX1 +XDFF<0> BIST_EN_I BIST_ADDR<0> ACLK_N ADDR<0> padr_int<0> net13<2> VDD ++ VSS / RSC_IHPSG13_DFNQMX2IX1 +XI15<1> ADDR_COL<1> VDD VSS / RSC_IHPSG13_TIEL +XI15<0> ADDR_COL<0> VDD VSS / RSC_IHPSG13_TIEL +XI13<2> NADR<2> PADR<2> VDD VSS / RSC_IHPSG13_INVX2 +XI13<1> NADR<1> PADR<1> VDD VSS / RSC_IHPSG13_INVX2 +XI13<0> NADR<0> PADR<0> VDD VSS / RSC_IHPSG13_INVX2 +XI3<2> padr_int<2> NADR<2> VDD VSS / RSC_IHPSG13_INVX2 +XI3<1> padr_int<1> NADR<1> VDD VSS / RSC_IHPSG13_INVX2 +XI3<0> padr_int<0> NADR<0> VDD VSS / RSC_IHPSG13_INVX2 +XI2<7> addr_n<7> ADDR_DEC<7> VDD VSS / RSC_IHPSG13_INVX2 +XI2<6> addr_n<6> ADDR_DEC<6> VDD VSS / RSC_IHPSG13_INVX2 +XI2<5> addr_n<5> ADDR_DEC<5> VDD VSS / RSC_IHPSG13_INVX2 +XI2<4> addr_n<4> ADDR_DEC<4> VDD VSS / RSC_IHPSG13_INVX2 +XI2<3> addr_n<3> ADDR_DEC<3> VDD VSS / RSC_IHPSG13_INVX2 +XI2<2> addr_n<2> ADDR_DEC<2> VDD VSS / RSC_IHPSG13_INVX2 +XI2<1> addr_n<1> ADDR_DEC<1> VDD VSS / RSC_IHPSG13_INVX2 +XI2<0> addr_n<0> ADDR_DEC<0> VDD VSS / RSC_IHPSG13_INVX2 +XI17<4> VDD VSS / RSC_IHPSG13_FILLCAP4 +XI17<3> VDD VSS / RSC_IHPSG13_FILLCAP4 +XI17<2> VDD VSS / RSC_IHPSG13_FILLCAP4 +XI17<1> VDD VSS / RSC_IHPSG13_FILLCAP4 +XI16<11> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI16<10> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI16<9> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI16<8> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI16<7> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI16<6> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI16<5> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI16<4> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI16<3> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI16<2> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI16<1> VDD VSS / RSC_IHPSG13_FILLCAP8 +.ENDS +.SUBCKT RSC_IHPSG13_DFPQD_MSAFFX2P CP DN DP QN QP VDD VSS +XI_AMP CP DN DP QN QP VDD VSS / RSC_IHPSG13_DFPQD_MSAFFX2 +.ENDS +.SUBCKT RM_IHPSG13_512x32_c2_2P_COLCTRL3 A_ADDR_DEC<7> A_ADDR_DEC<6> A_ADDR_DEC<5> ++ A_ADDR_DEC<4> A_ADDR_DEC<3> A_ADDR_DEC<2> A_ADDR_DEC<1> A_ADDR_DEC<0> ++ A_BIST_BM_I A_BIST_DW_I A_BIST_EN_I A_BLC<7> A_BLC<6> A_BLC<5> A_BLC<4> ++ A_BLC<3> A_BLC<2> A_BLC<1> A_BLC<0> A_BLT<7> A_BLT<6> A_BLT<5> A_BLT<4> ++ A_BLT<3> A_BLT<2> A_BLT<1> A_BLT<0> A_BM_I A_DCLK_B_L A_DCLK_B_R A_DCLK_L ++ A_DCLK_R A_DR_O A_DW_I A_RCLK_B_L A_RCLK_B_R A_RCLK_L A_RCLK_R A_TIEH_O ++ A_WCLK_B_L A_WCLK_B_R A_WCLK_L A_WCLK_R B_ADDR_DEC<7> B_ADDR_DEC<6> ++ B_ADDR_DEC<5> B_ADDR_DEC<4> B_ADDR_DEC<3> B_ADDR_DEC<2> B_ADDR_DEC<1> ++ B_ADDR_DEC<0> B_BIST_BM_I B_BIST_DW_I B_BIST_EN_I B_BLC<7> B_BLC<6> B_BLC<5> ++ B_BLC<4> B_BLC<3> B_BLC<2> B_BLC<1> B_BLC<0> B_BLT<7> B_BLT<6> B_BLT<5> ++ B_BLT<4> B_BLT<3> B_BLT<2> B_BLT<1> B_BLT<0> B_BM_I B_DCLK_B_L B_DCLK_B_R ++ B_DCLK_L B_DCLK_R B_DR_O B_DW_I B_RCLK_B_L B_RCLK_B_R B_RCLK_L B_RCLK_R ++ B_TIEH_O B_WCLK_B_L B_WCLK_B_R B_WCLK_L B_WCLK_R VDD VSS +XB_DREG B_BIST_EN_I B_BIST_DW_I B_DCLK_B_L B_DW_I B_DI_R net044 VDD ++ VSS / RSC_IHPSG13_DFNQMX2IX1 +XB_BREG B_BIST_EN_I B_BIST_BM_I B_DCLK_B_L B_BM_I B_BM_R net043 VDD ++ VSS / RSC_IHPSG13_DFNQMX2IX1 +XA_DREG A_BIST_EN_I A_BIST_DW_I A_DCLK_B_L A_DW_I A_DI_R net22 VDD VSS ++ / RSC_IHPSG13_DFNQMX2IX1 +XA_BREG A_BIST_EN_I A_BIST_BM_I A_DCLK_B_L A_BM_I A_BM_R net23 VDD VSS ++ / RSC_IHPSG13_DFNQMX2IX1 +XI_FILL8<11> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI_FILL8<10> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI_FILL8<9> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI_FILL8<8> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI_FILL8<7> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI_FILL8<6> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI_FILL8<5> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI_FILL8<4> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI_FILL8<3> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI_FILL8<2> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI_FILL8<1> VDD VSS / RSC_IHPSG13_FILLCAP8 +XB_I51 net037 B_DR_O VDD VSS / RSC_IHPSG13_INVX4 +XA_I51 net19 A_DR_O VDD VSS / RSC_IHPSG13_INVX4 +XB_I44 B_BM_N B_WCLK_B_L B_DO_WRITE_P VDD VSS / RSC_IHPSG13_NOR2X2 +XA_I44 A_BM_N A_WCLK_B_L A_DO_WRITE_P VDD VSS / RSC_IHPSG13_NOR2X2 +XB_BM_TIEH B_TIEH_O VDD VSS / RSC_IHPSG13_TIEH +XA_BM_TIEH A_TIEH_O VDD VSS / RSC_IHPSG13_TIEH +XB_ISENSE B_SAE B_BLC_SEL B_BLT_SEL net037 net038 VDD VSS / ++ RSC_IHPSG13_DFPQD_MSAFFX2P +XA_ISENSE A_SAE A_BLC_SEL A_BLT_SEL net19 net20 VDD VSS / ++ RSC_IHPSG13_DFPQD_MSAFFX2P +XB_I49 B_DI_R B_DI_N VDD VSS / RSC_IHPSG13_INVX2 +XB_I83 B_BM_R B_BM_N VDD VSS / RSC_IHPSG13_INVX2 +XA_I49 A_DI_R A_DI_N VDD VSS / RSC_IHPSG13_INVX2 +XA_I83 A_BM_R A_BM_N VDD VSS / RSC_IHPSG13_INVX2 +XB_I69 B_DCLK_L B_DCLK_B_L VDD VSS / RSC_IHPSG13_CINVX2 +XB_I50 B_WCLK_L B_WCLK_B_L VDD VSS / RSC_IHPSG13_CINVX2 +XB_EBUF B_RCLK_L B_RCLK_B_L VDD VSS / RSC_IHPSG13_CINVX2 +XA_I69 A_DCLK_L A_DCLK_B_L VDD VSS / RSC_IHPSG13_CINVX2 +XA_I50 A_WCLK_L A_WCLK_B_L VDD VSS / RSC_IHPSG13_CINVX2 +XA_EBUF A_RCLK_L A_RCLK_B_L VDD VSS / RSC_IHPSG13_CINVX2 +XAB_BLMUX<1> A_BLC<7> A_BLC<6> A_BLC<5> A_BLC<4> A_BLC_SEL A_BLT<7> A_BLT<6> ++ A_BLT<5> A_BLT<4> A_BLT_SEL A_PRE_N A_ADDR_DEC<7> A_ADDR_DEC<6> ++ A_ADDR_DEC<5> A_ADDR_DEC<4> A_WR_ONE A_WR_ZERO B_BLC<7> B_BLC<6> B_BLC<5> ++ B_BLC<4> B_BLC_SEL B_BLT<7> B_BLT<6> B_BLT<5> B_BLT<4> B_BLT_SEL B_PRE_N ++ B_ADDR_DEC<7> B_ADDR_DEC<6> B_ADDR_DEC<5> B_ADDR_DEC<4> B_WR_ONE B_WR_ZERO ++ VDD VSS / RM_IHPSG13_512x32_c2_2P_BLDRV +XAB_BLMUX<0> A_BLC<3> A_BLC<2> A_BLC<1> A_BLC<0> A_BLC_SEL A_BLT<3> A_BLT<2> ++ A_BLT<1> A_BLT<0> A_BLT_SEL A_PRE_N A_ADDR_DEC<3> A_ADDR_DEC<2> ++ A_ADDR_DEC<1> A_ADDR_DEC<0> A_WR_ONE A_WR_ZERO B_BLC<3> B_BLC<2> B_BLC<1> ++ B_BLC<0> B_BLC_SEL B_BLT<3> B_BLT<2> B_BLT<1> B_BLT<0> B_BLT_SEL B_PRE_N ++ B_ADDR_DEC<3> B_ADDR_DEC<2> B_ADDR_DEC<1> B_ADDR_DEC<0> B_WR_ONE B_WR_ZERO ++ VDD VSS / RM_IHPSG13_512x32_c2_2P_BLDRV +XB_I78 B_RCLK_B_L B_SAE VDD VSS / RSC_IHPSG13_CBUFX2 +XA_I78 A_RCLK_B_L A_SAE VDD VSS / RSC_IHPSG13_CBUFX2 +XB_I88 B_DCLK_L B_DCLK_R / RSC_IHPSG13_MET3RES +XB_I87 B_WCLK_L B_WCLK_R / RSC_IHPSG13_MET3RES +XB_R2 B_RCLK_L B_RCLK_R / RSC_IHPSG13_MET3RES +XB_I91 B_RCLK_B_L B_RCLK_B_R / RSC_IHPSG13_MET3RES +XB_I90 B_WCLK_B_L B_WCLK_B_R / RSC_IHPSG13_MET3RES +XB_I89 B_DCLK_B_L B_DCLK_B_R / RSC_IHPSG13_MET3RES +XA_I88 A_DCLK_L A_DCLK_R / RSC_IHPSG13_MET3RES +XA_I87 A_WCLK_L A_WCLK_R / RSC_IHPSG13_MET3RES +XA_R2 A_RCLK_L A_RCLK_R / RSC_IHPSG13_MET3RES +XA_I91 A_RCLK_B_L A_RCLK_B_R / RSC_IHPSG13_MET3RES +XA_I90 A_WCLK_B_L A_WCLK_B_R / RSC_IHPSG13_MET3RES +XA_I89 A_DCLK_B_L A_DCLK_B_R / RSC_IHPSG13_MET3RES +XB_I80 B_WCLK_B_L B_RCLK_B_L net041 VDD VSS / RSC_IHPSG13_AND2X2 +XB_I76 B_DO_WRITE_P B_DI_N B_WR_ZERO VDD VSS / RSC_IHPSG13_AND2X2 +XB_I75 B_DO_WRITE_P B_DI_R B_WR_ONE VDD VSS / RSC_IHPSG13_AND2X2 +XA_I80 A_WCLK_B_L A_RCLK_B_L net21 VDD VSS / RSC_IHPSG13_AND2X2 +XA_I76 A_DI_N A_DO_WRITE_P A_WR_ZERO VDD VSS / RSC_IHPSG13_AND2X2 +XA_I75 A_DI_R A_DO_WRITE_P A_WR_ONE VDD VSS / RSC_IHPSG13_AND2X2 +XB_I81 net041 B_PRE_N VDD VSS / RSC_IHPSG13_CINVX4_WN +XA_I81 net21 A_PRE_N VDD VSS / RSC_IHPSG13_CINVX4_WN +XI_FILL4<10> VDD VSS / RSC_IHPSG13_FILLCAP4 +XI_FILL4<9> VDD VSS / RSC_IHPSG13_FILLCAP4 +XI_FILL4<8> VDD VSS / RSC_IHPSG13_FILLCAP4 +XI_FILL4<7> VDD VSS / RSC_IHPSG13_FILLCAP4 +XI_FILL4<6> VDD VSS / RSC_IHPSG13_FILLCAP4 +XI_FILL4<5> VDD VSS / RSC_IHPSG13_FILLCAP4 +XI_FILL4<4> VDD VSS / RSC_IHPSG13_FILLCAP4 +XI_FILL4<3> VDD VSS / RSC_IHPSG13_FILLCAP4 +XI_FILL4<2> VDD VSS / RSC_IHPSG13_FILLCAP4 +XI_FILL4<1> VDD VSS / RSC_IHPSG13_FILLCAP4 +.ENDS + +.SUBCKT RM_IHPSG13_512x32_c2_2P_ROWDEC6 ADDR_N_I<5> ADDR_N_I<4> ADDR_N_I<3> ADDR_N_I<2> ++ ADDR_N_I<1> ADDR_N_I<0> CS_I ECLK_I WL_O<63> WL_O<62> WL_O<61> WL_O<60> ++ WL_O<59> WL_O<58> WL_O<57> WL_O<56> WL_O<55> WL_O<54> WL_O<53> WL_O<52> ++ WL_O<51> WL_O<50> WL_O<49> WL_O<48> WL_O<47> WL_O<46> WL_O<45> WL_O<44> ++ WL_O<43> WL_O<42> WL_O<41> WL_O<40> WL_O<39> WL_O<38> WL_O<37> WL_O<36> ++ WL_O<35> WL_O<34> WL_O<33> WL_O<32> WL_O<31> WL_O<30> WL_O<29> WL_O<28> ++ WL_O<27> WL_O<26> WL_O<25> WL_O<24> WL_O<23> WL_O<22> WL_O<21> WL_O<20> ++ WL_O<19> WL_O<18> WL_O<17> WL_O<16> WL_O<15> WL_O<14> WL_O<13> WL_O<12> ++ WL_O<11> WL_O<10> WL_O<9> WL_O<8> WL_O<7> WL_O<6> WL_O<5> WL_O<4> WL_O<3> ++ WL_O<2> WL_O<1> WL_O<0> VDD VSS +XDEC10 ADDR_N_I<5> ADDR_N_I<4> CS_I CS00<2> VDD VSS / ++ RM_IHPSG13_512x32_c2_2P_DEC02 +XDEC00 ADDR_N_I<5> ADDR_N_I<4> CS_I CS00<0> VDD VSS / ++ RM_IHPSG13_512x32_c2_2P_DEC00 +XSEL<3> ADDR_N_I<3> ADDR_N_I<2> ADDR_N_I<1> ADDR_N_I<0> CS00<3> ECLK_H<3> ++ ECLK_H<4> ECLK_B<3> ECLK_B<4> WL_O<63> WL_O<62> WL_O<61> WL_O<60> WL_O<59> ++ WL_O<58> WL_O<57> WL_O<56> WL_O<55> WL_O<54> WL_O<53> WL_O<52> WL_O<51> ++ WL_O<50> WL_O<49> WL_O<48> VDD VSS / RM_IHPSG13_512x32_c2_2P_DEC04 +XSEL<2> ADDR_N_I<3> ADDR_N_I<2> ADDR_N_I<1> ADDR_N_I<0> CS00<2> ECLK_H<2> ++ ECLK_H<3> ECLK_B<2> ECLK_B<3> WL_O<47> WL_O<46> WL_O<45> WL_O<44> WL_O<43> ++ WL_O<42> WL_O<41> WL_O<40> WL_O<39> WL_O<38> WL_O<37> WL_O<36> WL_O<35> ++ WL_O<34> WL_O<33> WL_O<32> VDD VSS / RM_IHPSG13_512x32_c2_2P_DEC04 +XSEL<1> ADDR_N_I<3> ADDR_N_I<2> ADDR_N_I<1> ADDR_N_I<0> CS00<1> ECLK_H<1> ++ ECLK_H<2> ECLK_B<1> ECLK_B<2> WL_O<31> WL_O<30> WL_O<29> WL_O<28> WL_O<27> ++ WL_O<26> WL_O<25> WL_O<24> WL_O<23> WL_O<22> WL_O<21> WL_O<20> WL_O<19> ++ WL_O<18> WL_O<17> WL_O<16> VDD VSS / RM_IHPSG13_512x32_c2_2P_DEC04 +XSEL<0> ADDR_N_I<3> ADDR_N_I<2> ADDR_N_I<1> ADDR_N_I<0> CS00<0> ECLK_I ++ ECLK_H<1> ECLK_B<0> ECLK_B<1> WL_O<15> WL_O<14> WL_O<13> WL_O<12> WL_O<11> ++ WL_O<10> WL_O<9> WL_O<8> WL_O<7> WL_O<6> WL_O<5> WL_O<4> WL_O<3> WL_O<2> ++ WL_O<1> WL_O<0> VDD VSS / RM_IHPSG13_512x32_c2_2P_DEC04 +XDEC11 ADDR_N_I<5> ADDR_N_I<4> CS_I CS00<3> VDD VSS / ++ RM_IHPSG13_512x32_c2_2P_DEC03 +XL2<36> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<35> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<34> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<33> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<32> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<31> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<30> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<29> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<28> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<27> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<26> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<25> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<24> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<23> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<22> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<21> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<20> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<19> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<18> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<17> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<16> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<15> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<14> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<13> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<12> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<11> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<10> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<9> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<8> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<7> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<6> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<5> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<4> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<3> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<2> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<1> VDD VSS / RSC_IHPSG13_FILLCAP8 +XDEC01 ADDR_N_I<5> ADDR_N_I<4> CS_I CS00<1> VDD VSS / ++ RM_IHPSG13_512x32_c2_2P_DEC01 +.ENDS +.SUBCKT RM_IHPSG13_512x32_c2_2P_ROWREG6 ACLK_N_I ADDR_I<5> ADDR_I<4> ADDR_I<3> ADDR_I<2> ++ ADDR_I<1> ADDR_I<0> ADDR_N_O<5> ADDR_N_O<4> ADDR_N_O<3> ADDR_N_O<2> ++ ADDR_N_O<1> ADDR_N_O<0> BIST_ADDR_I<5> BIST_ADDR_I<4> BIST_ADDR_I<3> ++ BIST_ADDR_I<2> BIST_ADDR_I<1> BIST_ADDR_I<0> BIST_EN_I VDD VSS +XINV<5> q_int<5> qn_int<5> VDD VSS / RSC_IHPSG13_CINVX2 +XINV<4> q_int<4> qn_int<4> VDD VSS / RSC_IHPSG13_CINVX2 +XINV<3> q_int<3> qn_int<3> VDD VSS / RSC_IHPSG13_CINVX2 +XINV<2> q_int<2> qn_int<2> VDD VSS / RSC_IHPSG13_CINVX2 +XINV<1> q_int<1> qn_int<1> VDD VSS / RSC_IHPSG13_CINVX2 +XINV<0> q_int<0> qn_int<0> VDD VSS / RSC_IHPSG13_CINVX2 +XDRV<5> qn_int<5> ADDR_N_O<5> VDD VSS / RSC_IHPSG13_CINVX8 +XDRV<4> qn_int<4> ADDR_N_O<4> VDD VSS / RSC_IHPSG13_CINVX8 +XDRV<3> qn_int<3> ADDR_N_O<3> VDD VSS / RSC_IHPSG13_CINVX8 +XDRV<2> qn_int<2> ADDR_N_O<2> VDD VSS / RSC_IHPSG13_CINVX8 +XDRV<1> qn_int<1> ADDR_N_O<1> VDD VSS / RSC_IHPSG13_CINVX8 +XDRV<0> qn_int<0> ADDR_N_O<0> VDD VSS / RSC_IHPSG13_CINVX8 +XDFF<5> BIST_EN_I BIST_ADDR_I<5> ACLK_N_I ADDR_I<5> q_int<5> net2<0> VDD ++ VSS / RSC_IHPSG13_DFNQMX2IX1 +XDFF<4> BIST_EN_I BIST_ADDR_I<4> ACLK_N_I ADDR_I<4> q_int<4> net2<1> VDD ++ VSS / RSC_IHPSG13_DFNQMX2IX1 +XDFF<3> BIST_EN_I BIST_ADDR_I<3> ACLK_N_I ADDR_I<3> q_int<3> net2<2> VDD ++ VSS / RSC_IHPSG13_DFNQMX2IX1 +XDFF<2> BIST_EN_I BIST_ADDR_I<2> ACLK_N_I ADDR_I<2> q_int<2> net2<3> VDD ++ VSS / RSC_IHPSG13_DFNQMX2IX1 +XDFF<1> BIST_EN_I BIST_ADDR_I<1> ACLK_N_I ADDR_I<1> q_int<1> net2<4> VDD ++ VSS / RSC_IHPSG13_DFNQMX2IX1 +XDFF<0> BIST_EN_I BIST_ADDR_I<0> ACLK_N_I ADDR_I<0> q_int<0> net2<5> VDD ++ VSS / RSC_IHPSG13_DFNQMX2IX1 +XI11<12> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI11<11> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI11<10> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI11<9> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI11<8> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI11<7> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI11<6> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI11<5> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI11<4> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI11<3> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI11<2> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI11<1> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI12<2> VDD VSS / RSC_IHPSG13_FILLCAP4 +XI12<1> VDD VSS / RSC_IHPSG13_FILLCAP4 +XI12<0> VDD VSS / RSC_IHPSG13_FILLCAP4 +.ENDS + +.SUBCKT RM_IHPSG13_512x32_c2_2P_COLDRV13X16 ADDR_COL_I<1> ADDR_COL_I<0> ADDR_COL_O<1> ++ ADDR_COL_O<0> ADDR_DEC_I<7> ADDR_DEC_I<6> ADDR_DEC_I<5> ADDR_DEC_I<4> ++ ADDR_DEC_I<3> ADDR_DEC_I<2> ADDR_DEC_I<1> ADDR_DEC_I<0> ADDR_DEC_O<7> ++ ADDR_DEC_O<6> ADDR_DEC_O<5> ADDR_DEC_O<4> ADDR_DEC_O<3> ADDR_DEC_O<2> ++ ADDR_DEC_O<1> ADDR_DEC_O<0> DCLK_I DCLK_O RCLK_I RCLK_O WCLK_I WCLK_O ++ VDD VSS +XI0<7> VDD VSS / RSC_IHPSG13_FILLCAP4 +XI0<6> VDD VSS / RSC_IHPSG13_FILLCAP4 +XI0<5> VDD VSS / RSC_IHPSG13_FILLCAP4 +XI0<4> VDD VSS / RSC_IHPSG13_FILLCAP4 +XI0<3> VDD VSS / RSC_IHPSG13_FILLCAP4 +XI0<2> VDD VSS / RSC_IHPSG13_FILLCAP4 +XI0<1> VDD VSS / RSC_IHPSG13_FILLCAP4 +XWCLK_DRV WCLK_I WCLK_O VDD VSS / RSC_IHPSG13_CBUFX16 +XRCLK_DRV RCLK_I RCLK_O VDD VSS / RSC_IHPSG13_CBUFX16 +XDCLK_DRV DCLK_I DCLK_O VDD VSS / RSC_IHPSG13_CBUFX16 +XADDR_COL_DRV<1> ADDR_COL_I<1> ADDR_COL_O<1> VDD VSS / ++ RSC_IHPSG13_CBUFX16 +XADDR_COL_DRV<0> ADDR_COL_I<0> ADDR_COL_O<0> VDD VSS / ++ RSC_IHPSG13_CBUFX16 +XADDR_DEC_DRV<7> ADDR_DEC_I<7> ADDR_DEC_O<7> VDD VSS / ++ RSC_IHPSG13_CBUFX16 +XADDR_DEC_DRV<6> ADDR_DEC_I<6> ADDR_DEC_O<6> VDD VSS / ++ RSC_IHPSG13_CBUFX16 +XADDR_DEC_DRV<5> ADDR_DEC_I<5> ADDR_DEC_O<5> VDD VSS / ++ RSC_IHPSG13_CBUFX16 +XADDR_DEC_DRV<4> ADDR_DEC_I<4> ADDR_DEC_O<4> VDD VSS / ++ RSC_IHPSG13_CBUFX16 +XADDR_DEC_DRV<3> ADDR_DEC_I<3> ADDR_DEC_O<3> VDD VSS / ++ RSC_IHPSG13_CBUFX16 +XADDR_DEC_DRV<2> ADDR_DEC_I<2> ADDR_DEC_O<2> VDD VSS / ++ RSC_IHPSG13_CBUFX16 +XADDR_DEC_DRV<1> ADDR_DEC_I<1> ADDR_DEC_O<1> VDD VSS / ++ RSC_IHPSG13_CBUFX16 +XADDR_DEC_DRV<0> ADDR_DEC_I<0> ADDR_DEC_O<0> VDD VSS / ++ RSC_IHPSG13_CBUFX16 +XI1<5> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI1<4> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI1<3> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI1<2> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI1<1> VDD VSS / RSC_IHPSG13_FILLCAP8 +.ENDS +.SUBCKT RM_IHPSG13_512x32_c2_2P_WLDRV16X16 A<15> A<14> A<13> A<12> A<11> A<10> A<9> A<8> ++ A<7> A<6> A<5> A<4> A<3> A<2> A<1> A<0> Z<15> Z<14> Z<13> Z<12> Z<11> Z<10> ++ Z<9> Z<8> Z<7> Z<6> Z<5> Z<4> Z<3> Z<2> Z<1> Z<0> VDD VSS +XBUF<15> A<15> Z<15> VDD VSS / RSC_IHPSG13_WLDRVX16 +XBUF<14> A<14> Z<14> VDD VSS / RSC_IHPSG13_WLDRVX16 +XBUF<13> A<13> Z<13> VDD VSS / RSC_IHPSG13_WLDRVX16 +XBUF<12> A<12> Z<12> VDD VSS / RSC_IHPSG13_WLDRVX16 +XBUF<11> A<11> Z<11> VDD VSS / RSC_IHPSG13_WLDRVX16 +XBUF<10> A<10> Z<10> VDD VSS / RSC_IHPSG13_WLDRVX16 +XBUF<9> A<9> Z<9> VDD VSS / RSC_IHPSG13_WLDRVX16 +XBUF<8> A<8> Z<8> VDD VSS / RSC_IHPSG13_WLDRVX16 +XBUF<7> A<7> Z<7> VDD VSS / RSC_IHPSG13_WLDRVX16 +XBUF<6> A<6> Z<6> VDD VSS / RSC_IHPSG13_WLDRVX16 +XBUF<5> A<5> Z<5> VDD VSS / RSC_IHPSG13_WLDRVX16 +XBUF<4> A<4> Z<4> VDD VSS / RSC_IHPSG13_WLDRVX16 +XBUF<3> A<3> Z<3> VDD VSS / RSC_IHPSG13_WLDRVX16 +XBUF<2> A<2> Z<2> VDD VSS / RSC_IHPSG13_WLDRVX16 +XBUF<1> A<1> Z<1> VDD VSS / RSC_IHPSG13_WLDRVX16 +XBUF<0> A<0> Z<0> VDD VSS / RSC_IHPSG13_WLDRVX16 +.ENDS + + +.SUBCKT RM_IHPSG13_512x32_c2_1P_DEC01 ADDR<1> ADDR<0> CS CS_OUT VDD VSS +XDECINV net1 CS_OUT VDD VSS / RSC_IHPSG13_INVX4 +XDEC NADDR<1> ADDR<0> CS net1 VDD VSS / RSC_IHPSG13_NAND3X2 +XI2 VDD VSS / RSC_IHPSG13_FILLCAP4 +XADDRINV ADDR<1> NADDR<1> VDD VSS / RSC_IHPSG13_INVX2 +.ENDS +.SUBCKT RM_IHPSG13_512x32_c2_1P_DEC00 ADDR<1> ADDR<0> CS CS_OUT VDD VSS +XDECINV net1 CS_OUT VDD VSS / RSC_IHPSG13_INVX4 +XDEC NADDR<1> NADDR<0> CS net1 VDD VSS / RSC_IHPSG13_NAND3X2 +XADDRINV<1> ADDR<1> NADDR<1> VDD VSS / RSC_IHPSG13_INVX2 +XADDRINV<0> ADDR<0> NADDR<0> VDD VSS / RSC_IHPSG13_INVX2 +XI1 VDD VSS / RSC_IHPSG13_FILLCAP4 +.ENDS +.SUBCKT RM_IHPSG13_512x32_c2_1P_ROWDEC5 ADDR_N_I<4> ADDR_N_I<3> ADDR_N_I<2> ADDR_N_I<1> ++ ADDR_N_I<0> CS_I ECLK_I WL_O<31> WL_O<30> WL_O<29> WL_O<28> WL_O<27> ++ WL_O<26> WL_O<25> WL_O<24> WL_O<23> WL_O<22> WL_O<21> WL_O<20> WL_O<19> ++ WL_O<18> WL_O<17> WL_O<16> WL_O<15> WL_O<14> WL_O<13> WL_O<12> WL_O<11> ++ WL_O<10> WL_O<9> WL_O<8> WL_O<7> WL_O<6> WL_O<5> WL_O<4> WL_O<3> WL_O<2> ++ WL_O<1> WL_O<0> VDD VSS +XL2<12> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<11> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<10> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<9> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<8> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<7> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<6> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<5> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<4> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<3> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<2> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<1> VDD VSS / RSC_IHPSG13_FILLCAP8 +XDEC01 ADDR_N_I<5> ADDR_N_I<4> CS_I CS00<1> VDD VSS / ++ RM_IHPSG13_512x32_c2_1P_DEC01 +XDEC00 ADDR_N_I<5> ADDR_N_I<4> CS_I CS00<0> VDD VSS / ++ RM_IHPSG13_512x32_c2_1P_DEC00 +XSEL<1> ADDR_N_I<3> ADDR_N_I<2> ADDR_N_I<1> ADDR_N_I<0> CS00<1> ECLK_H<1> ++ ECLK_H<2> ECLK_B<1> ECLK_B<2> WL_O<31> WL_O<30> WL_O<29> WL_O<28> WL_O<27> ++ WL_O<26> WL_O<25> WL_O<24> WL_O<23> WL_O<22> WL_O<21> WL_O<20> WL_O<19> ++ WL_O<18> WL_O<17> WL_O<16> VDD VSS / RM_IHPSG13_512x32_c2_1P_DEC04 +XSEL<0> ADDR_N_I<3> ADDR_N_I<2> ADDR_N_I<1> ADDR_N_I<0> CS00<0> ECLK_I ++ ECLK_H<1> ECLK_B<0> ECLK_B<1> WL_O<15> WL_O<14> WL_O<13> WL_O<12> WL_O<11> ++ WL_O<10> WL_O<9> WL_O<8> WL_O<7> WL_O<6> WL_O<5> WL_O<4> WL_O<3> WL_O<2> ++ WL_O<1> WL_O<0> VDD VSS / RM_IHPSG13_512x32_c2_1P_DEC04 +XI0 ADDR_N_I<5> VDD VSS / RSC_IHPSG13_TIEL +.ENDS +.SUBCKT RM_IHPSG13_512x32_c2_1P_ROWREG5 ACLK_N_I ADDR_I<4> ADDR_I<3> ADDR_I<2> ADDR_I<1> ++ ADDR_I<0> ADDR_N_O<4> ADDR_N_O<3> ADDR_N_O<2> ADDR_N_O<1> ADDR_N_O<0> ++ BIST_ADDR_I<4> BIST_ADDR_I<3> BIST_ADDR_I<2> BIST_ADDR_I<1> BIST_ADDR_I<0> ++ BIST_EN_I VDD VSS +XINV<4> q_int<4> qn_int<4> VDD VSS / RSC_IHPSG13_CINVX2 +XINV<3> q_int<3> qn_int<3> VDD VSS / RSC_IHPSG13_CINVX2 +XINV<2> q_int<2> qn_int<2> VDD VSS / RSC_IHPSG13_CINVX2 +XINV<1> q_int<1> qn_int<1> VDD VSS / RSC_IHPSG13_CINVX2 +XINV<0> q_int<0> qn_int<0> VDD VSS / RSC_IHPSG13_CINVX2 +XDRV<4> qn_int<4> ADDR_N_O<4> VDD VSS / RSC_IHPSG13_CINVX8 +XDRV<3> qn_int<3> ADDR_N_O<3> VDD VSS / RSC_IHPSG13_CINVX8 +XDRV<2> qn_int<2> ADDR_N_O<2> VDD VSS / RSC_IHPSG13_CINVX8 +XDRV<1> qn_int<1> ADDR_N_O<1> VDD VSS / RSC_IHPSG13_CINVX8 +XDRV<0> qn_int<0> ADDR_N_O<0> VDD VSS / RSC_IHPSG13_CINVX8 +XDFF<4> BIST_EN_I BIST_ADDR_I<4> ACLK_N_I ADDR_I<4> q_int<4> net2<0> VDD ++ VSS / RSC_IHPSG13_DFNQMX2IX1 +XDFF<3> BIST_EN_I BIST_ADDR_I<3> ACLK_N_I ADDR_I<3> q_int<3> net2<1> VDD ++ VSS / RSC_IHPSG13_DFNQMX2IX1 +XDFF<2> BIST_EN_I BIST_ADDR_I<2> ACLK_N_I ADDR_I<2> q_int<2> net2<2> VDD ++ VSS / RSC_IHPSG13_DFNQMX2IX1 +XDFF<1> BIST_EN_I BIST_ADDR_I<1> ACLK_N_I ADDR_I<1> q_int<1> net2<3> VDD ++ VSS / RSC_IHPSG13_DFNQMX2IX1 +XDFF<0> BIST_EN_I BIST_ADDR_I<0> ACLK_N_I ADDR_I<0> q_int<0> net2<4> VDD ++ VSS / RSC_IHPSG13_DFNQMX2IX1 +XI11<16> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI11<15> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI11<14> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI11<13> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI11<12> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI11<11> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI11<10> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI11<9> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI11<8> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI11<7> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI11<6> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI11<5> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI11<4> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI11<3> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI11<2> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI11<1> VDD VSS / RSC_IHPSG13_FILLCAP8 +.ENDS + + +.SUBCKT RM_IHPSG13_512x32_c2_1P_COLDEC5 ACLK_N ADDR<4> ADDR<3> ADDR<2> ADDR<1> ADDR<0> ++ ADDR_COL<1> ADDR_COL<0> ADDR_DEC<7> ADDR_DEC<6> ADDR_DEC<5> ADDR_DEC<4> ++ ADDR_DEC<3> ADDR_DEC<2> ADDR_DEC<1> ADDR_DEC<0> BIST_ADDR<4> BIST_ADDR<3> ++ BIST_ADDR<2> BIST_ADDR<1> BIST_ADDR<0> BIST_EN_I VDD VSS +XI17<2> VDD VSS / RSC_IHPSG13_FILLCAP4 +XI17<1> VDD VSS / RSC_IHPSG13_FILLCAP4 +XI13<1> addr_int<1> ADDR_COL<1> VDD VSS / RSC_IHPSG13_CBUFX2 +XI13<0> addr_int<0> ADDR_COL<0> VDD VSS / RSC_IHPSG13_CBUFX2 +XDFF<4> BIST_EN_I BIST_ADDR<4> ACLK_N ADDR<4> addr_int<1> net7<0> VDD ++ VSS / RSC_IHPSG13_DFNQMX2IX1 +XDFF<3> BIST_EN_I BIST_ADDR<3> ACLK_N ADDR<3> addr_int<0> net7<1> VDD ++ VSS / RSC_IHPSG13_DFNQMX2IX1 +XDFF<2> BIST_EN_I BIST_ADDR<2> ACLK_N ADDR<2> padr_int<2> net7<2> VDD ++ VSS / RSC_IHPSG13_DFNQMX2IX1 +XDFF<1> BIST_EN_I BIST_ADDR<1> ACLK_N ADDR<1> padr_int<1> net7<3> VDD ++ VSS / RSC_IHPSG13_DFNQMX2IX1 +XDFF<0> BIST_EN_I BIST_ADDR<0> ACLK_N ADDR<0> padr_int<0> net7<4> VDD ++ VSS / RSC_IHPSG13_DFNQMX2IX1 +XI1<7> PADR<0> PADR<1> PADR<2> addr_n<7> VDD VSS / RSC_IHPSG13_NAND3X2 +XI1<6> NADR<0> PADR<1> PADR<2> addr_n<6> VDD VSS / RSC_IHPSG13_NAND3X2 +XI1<5> PADR<0> NADR<1> PADR<2> addr_n<5> VDD VSS / RSC_IHPSG13_NAND3X2 +XI1<4> NADR<0> NADR<1> PADR<2> addr_n<4> VDD VSS / RSC_IHPSG13_NAND3X2 +XI1<3> PADR<0> PADR<1> NADR<2> addr_n<3> VDD VSS / RSC_IHPSG13_NAND3X2 +XI1<2> NADR<0> PADR<1> NADR<2> addr_n<2> VDD VSS / RSC_IHPSG13_NAND3X2 +XI1<1> PADR<0> NADR<1> NADR<2> addr_n<1> VDD VSS / RSC_IHPSG13_NAND3X2 +XI1<0> NADR<0> NADR<1> NADR<2> addr_n<0> VDD VSS / RSC_IHPSG13_NAND3X2 +XI15<2> NADR<2> PADR<2> VDD VSS / RSC_IHPSG13_INVX2 +XI15<1> NADR<1> PADR<1> VDD VSS / RSC_IHPSG13_INVX2 +XI15<0> NADR<0> PADR<0> VDD VSS / RSC_IHPSG13_INVX2 +XI3<2> padr_int<2> NADR<2> VDD VSS / RSC_IHPSG13_INVX2 +XI3<1> padr_int<1> NADR<1> VDD VSS / RSC_IHPSG13_INVX2 +XI3<0> padr_int<0> NADR<0> VDD VSS / RSC_IHPSG13_INVX2 +XI2<7> addr_n<7> ADDR_DEC<7> VDD VSS / RSC_IHPSG13_INVX2 +XI2<6> addr_n<6> ADDR_DEC<6> VDD VSS / RSC_IHPSG13_INVX2 +XI2<5> addr_n<5> ADDR_DEC<5> VDD VSS / RSC_IHPSG13_INVX2 +XI2<4> addr_n<4> ADDR_DEC<4> VDD VSS / RSC_IHPSG13_INVX2 +XI2<3> addr_n<3> ADDR_DEC<3> VDD VSS / RSC_IHPSG13_INVX2 +XI2<2> addr_n<2> ADDR_DEC<2> VDD VSS / RSC_IHPSG13_INVX2 +XI2<1> addr_n<1> ADDR_DEC<1> VDD VSS / RSC_IHPSG13_INVX2 +XI2<0> addr_n<0> ADDR_DEC<0> VDD VSS / RSC_IHPSG13_INVX2 +.ENDS +.SUBCKT RM_IHPSG13_512x32_c2_1P_COLCTRL5 A_ADDR_COL<1> A_ADDR_COL<0> A_ADDR_DEC<7> ++ A_ADDR_DEC<6> A_ADDR_DEC<5> A_ADDR_DEC<4> A_ADDR_DEC<3> A_ADDR_DEC<2> ++ A_ADDR_DEC<1> A_ADDR_DEC<0> A_BIST_BM_I A_BIST_DW_I A_BIST_EN_I A_BLC<31> ++ A_BLC<30> A_BLC<29> A_BLC<28> A_BLC<27> A_BLC<26> A_BLC<25> A_BLC<24> ++ A_BLC<23> A_BLC<22> A_BLC<21> A_BLC<20> A_BLC<19> A_BLC<18> A_BLC<17> ++ A_BLC<16> A_BLC<15> A_BLC<14> A_BLC<13> A_BLC<12> A_BLC<11> A_BLC<10> ++ A_BLC<9> A_BLC<8> A_BLC<7> A_BLC<6> A_BLC<5> A_BLC<4> A_BLC<3> A_BLC<2> ++ A_BLC<1> A_BLC<0> A_BLT<31> A_BLT<30> A_BLT<29> A_BLT<28> A_BLT<27> ++ A_BLT<26> A_BLT<25> A_BLT<24> A_BLT<23> A_BLT<22> A_BLT<21> A_BLT<20> ++ A_BLT<19> A_BLT<18> A_BLT<17> A_BLT<16> A_BLT<15> A_BLT<14> A_BLT<13> ++ A_BLT<12> A_BLT<11> A_BLT<10> A_BLT<9> A_BLT<8> A_BLT<7> A_BLT<6> A_BLT<5> ++ A_BLT<4> A_BLT<3> A_BLT<2> A_BLT<1> A_BLT<0> A_BM_I A_DCLK_B_L A_DCLK_B_R ++ A_DCLK_L A_DCLK_R A_DR_O A_DW_I A_RCLK_B_L A_RCLK_B_R A_RCLK_L A_RCLK_R ++ A_TIEH_O A_WCLK_B_L A_WCLK_B_R A_WCLK_L A_WCLK_R VDD VSS +XA_I80<1> A_WCLK_B_L A_RCLK_B_L A_W_nor_R<1> VDD VSS / ++ RSC_IHPSG13_AND2X2 +XA_I80<0> A_WCLK_B_L A_RCLK_B_L A_W_nor_R<0> VDD VSS / ++ RSC_IHPSG13_AND2X2 +XA_I44 A_BM_N A_WCLK_B_L A_DO_WRITE_P VDD VSS / RSC_IHPSG13_NOR2X2 +XI80<29> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI80<28> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI80<27> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI80<26> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI80<25> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI80<24> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI80<23> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI80<22> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI80<21> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI80<20> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI80<19> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI80<18> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI80<17> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI80<16> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI80<15> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI80<14> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI80<13> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI80<12> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI80<11> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI80<10> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI80<9> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI80<8> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI80<7> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI80<6> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI80<5> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI80<4> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI80<3> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI80<2> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI80<1> VDD VSS / RSC_IHPSG13_FILLCAP8 +XA_I74<16> VDD VSS / RSC_IHPSG13_FILLCAP8 +XA_I74<15> VDD VSS / RSC_IHPSG13_FILLCAP8 +XA_I74<14> VDD VSS / RSC_IHPSG13_FILLCAP8 +XA_I74<13> VDD VSS / RSC_IHPSG13_FILLCAP8 +XA_I74<12> VDD VSS / RSC_IHPSG13_FILLCAP8 +XA_I74<11> VDD VSS / RSC_IHPSG13_FILLCAP8 +XA_I74<10> VDD VSS / RSC_IHPSG13_FILLCAP8 +XA_I74<9> VDD VSS / RSC_IHPSG13_FILLCAP8 +XA_I74<8> VDD VSS / RSC_IHPSG13_FILLCAP8 +XA_I74<7> VDD VSS / RSC_IHPSG13_FILLCAP8 +XA_I74<6> VDD VSS / RSC_IHPSG13_FILLCAP8 +XA_I74<5> VDD VSS / RSC_IHPSG13_FILLCAP8 +XA_I74<4> VDD VSS / RSC_IHPSG13_FILLCAP8 +XA_I74<3> VDD VSS / RSC_IHPSG13_FILLCAP8 +XA_I74<2> VDD VSS / RSC_IHPSG13_FILLCAP8 +XA_I74<1> VDD VSS / RSC_IHPSG13_FILLCAP8 +XA_INV<6> A_N1<1> A_P1<1> VDD VSS / RSC_IHPSG13_CINVX4 +XA_INV<5> A_N0<1> A_P0<1> VDD VSS / RSC_IHPSG13_CINVX4 +XA_INV<4> A_N0<0> A_P0<0> VDD VSS / RSC_IHPSG13_CINVX4 +XA_INV<3> A_ADDR_COL<1> A_N1<1> VDD VSS / RSC_IHPSG13_CINVX4 +XA_INV<2> A_ADDR_COL<1> A_N1<0> VDD VSS / RSC_IHPSG13_CINVX4 +XA_INV<1> A_ADDR_COL<0> A_N0<1> VDD VSS / RSC_IHPSG13_CINVX4 +XA_INV<0> A_ADDR_COL<0> A_N0<0> VDD VSS / RSC_IHPSG13_CINVX4 +XA_I81<3> A_W_nor_R<1> A_PRE_N VDD VSS / RSC_IHPSG13_CINVX4_WN +XA_I81<2> A_W_nor_R<1> A_PRE_N VDD VSS / RSC_IHPSG13_CINVX4_WN +XA_I81<1> A_W_nor_R<0> A_PRE_N VDD VSS / RSC_IHPSG13_CINVX4_WN +XA_I81<0> A_W_nor_R<0> A_PRE_N VDD VSS / RSC_IHPSG13_CINVX4_WN +XA_BLTMUX<31> A_BLC<31> A_BLC_SEL A_BLT<31> A_BLT_SEL A_PRE_N A_SEL_P<31> ++ A_WR_ONE A_WR_ZERO VDD VSS / RM_IHPSG13_512x32_c2_1P_BLDRV +XA_BLTMUX<30> A_BLC<30> A_BLC_SEL A_BLT<30> A_BLT_SEL A_PRE_N A_SEL_P<30> ++ A_WR_ONE A_WR_ZERO VDD VSS / RM_IHPSG13_512x32_c2_1P_BLDRV +XA_BLTMUX<29> A_BLC<29> A_BLC_SEL A_BLT<29> A_BLT_SEL A_PRE_N A_SEL_P<29> ++ A_WR_ONE A_WR_ZERO VDD VSS / RM_IHPSG13_512x32_c2_1P_BLDRV +XA_BLTMUX<28> A_BLC<28> A_BLC_SEL A_BLT<28> A_BLT_SEL A_PRE_N A_SEL_P<28> ++ A_WR_ONE A_WR_ZERO VDD VSS / RM_IHPSG13_512x32_c2_1P_BLDRV +XA_BLTMUX<27> A_BLC<27> A_BLC_SEL A_BLT<27> A_BLT_SEL A_PRE_N A_SEL_P<27> ++ A_WR_ONE A_WR_ZERO VDD VSS / RM_IHPSG13_512x32_c2_1P_BLDRV +XA_BLTMUX<26> A_BLC<26> A_BLC_SEL A_BLT<26> A_BLT_SEL A_PRE_N A_SEL_P<26> ++ A_WR_ONE A_WR_ZERO VDD VSS / RM_IHPSG13_512x32_c2_1P_BLDRV +XA_BLTMUX<25> A_BLC<25> A_BLC_SEL A_BLT<25> A_BLT_SEL A_PRE_N A_SEL_P<25> ++ A_WR_ONE A_WR_ZERO VDD VSS / RM_IHPSG13_512x32_c2_1P_BLDRV +XA_BLTMUX<24> A_BLC<24> A_BLC_SEL A_BLT<24> A_BLT_SEL A_PRE_N A_SEL_P<24> ++ A_WR_ONE A_WR_ZERO VDD VSS / RM_IHPSG13_512x32_c2_1P_BLDRV +XA_BLTMUX<23> A_BLC<23> A_BLC_SEL A_BLT<23> A_BLT_SEL A_PRE_N A_SEL_P<23> ++ A_WR_ONE A_WR_ZERO VDD VSS / RM_IHPSG13_512x32_c2_1P_BLDRV +XA_BLTMUX<22> A_BLC<22> A_BLC_SEL A_BLT<22> A_BLT_SEL A_PRE_N A_SEL_P<22> ++ A_WR_ONE A_WR_ZERO VDD VSS / RM_IHPSG13_512x32_c2_1P_BLDRV +XA_BLTMUX<21> A_BLC<21> A_BLC_SEL A_BLT<21> A_BLT_SEL A_PRE_N A_SEL_P<21> ++ A_WR_ONE A_WR_ZERO VDD VSS / RM_IHPSG13_512x32_c2_1P_BLDRV +XA_BLTMUX<20> A_BLC<20> A_BLC_SEL A_BLT<20> A_BLT_SEL A_PRE_N A_SEL_P<20> ++ A_WR_ONE A_WR_ZERO VDD VSS / RM_IHPSG13_512x32_c2_1P_BLDRV +XA_BLTMUX<19> A_BLC<19> A_BLC_SEL A_BLT<19> A_BLT_SEL A_PRE_N A_SEL_P<19> ++ A_WR_ONE A_WR_ZERO VDD VSS / RM_IHPSG13_512x32_c2_1P_BLDRV +XA_BLTMUX<18> A_BLC<18> A_BLC_SEL A_BLT<18> A_BLT_SEL A_PRE_N A_SEL_P<18> ++ A_WR_ONE A_WR_ZERO VDD VSS / RM_IHPSG13_512x32_c2_1P_BLDRV +XA_BLTMUX<17> A_BLC<17> A_BLC_SEL A_BLT<17> A_BLT_SEL A_PRE_N A_SEL_P<17> ++ A_WR_ONE A_WR_ZERO VDD VSS / RM_IHPSG13_512x32_c2_1P_BLDRV +XA_BLTMUX<16> A_BLC<16> A_BLC_SEL A_BLT<16> A_BLT_SEL A_PRE_N A_SEL_P<16> ++ A_WR_ONE A_WR_ZERO VDD VSS / RM_IHPSG13_512x32_c2_1P_BLDRV +XA_BLTMUX<15> A_BLC<15> A_BLC_SEL A_BLT<15> A_BLT_SEL A_PRE_N A_SEL_P<15> ++ A_WR_ONE A_WR_ZERO VDD VSS / RM_IHPSG13_512x32_c2_1P_BLDRV +XA_BLTMUX<14> A_BLC<14> A_BLC_SEL A_BLT<14> A_BLT_SEL A_PRE_N A_SEL_P<14> ++ A_WR_ONE A_WR_ZERO VDD VSS / RM_IHPSG13_512x32_c2_1P_BLDRV +XA_BLTMUX<13> A_BLC<13> A_BLC_SEL A_BLT<13> A_BLT_SEL A_PRE_N A_SEL_P<13> ++ A_WR_ONE A_WR_ZERO VDD VSS / RM_IHPSG13_512x32_c2_1P_BLDRV +XA_BLTMUX<12> A_BLC<12> A_BLC_SEL A_BLT<12> A_BLT_SEL A_PRE_N A_SEL_P<12> ++ A_WR_ONE A_WR_ZERO VDD VSS / RM_IHPSG13_512x32_c2_1P_BLDRV +XA_BLTMUX<11> A_BLC<11> A_BLC_SEL A_BLT<11> A_BLT_SEL A_PRE_N A_SEL_P<11> ++ A_WR_ONE A_WR_ZERO VDD VSS / RM_IHPSG13_512x32_c2_1P_BLDRV +XA_BLTMUX<10> A_BLC<10> A_BLC_SEL A_BLT<10> A_BLT_SEL A_PRE_N A_SEL_P<10> ++ A_WR_ONE A_WR_ZERO VDD VSS / RM_IHPSG13_512x32_c2_1P_BLDRV +XA_BLTMUX<9> A_BLC<9> A_BLC_SEL A_BLT<9> A_BLT_SEL A_PRE_N A_SEL_P<9> A_WR_ONE ++ A_WR_ZERO VDD VSS / RM_IHPSG13_512x32_c2_1P_BLDRV +XA_BLTMUX<8> A_BLC<8> A_BLC_SEL A_BLT<8> A_BLT_SEL A_PRE_N A_SEL_P<8> A_WR_ONE ++ A_WR_ZERO VDD VSS / RM_IHPSG13_512x32_c2_1P_BLDRV +XA_BLTMUX<7> A_BLC<7> A_BLC_SEL A_BLT<7> A_BLT_SEL A_PRE_N A_SEL_P<7> A_WR_ONE ++ A_WR_ZERO VDD VSS / RM_IHPSG13_512x32_c2_1P_BLDRV +XA_BLTMUX<6> A_BLC<6> A_BLC_SEL A_BLT<6> A_BLT_SEL A_PRE_N A_SEL_P<6> A_WR_ONE ++ A_WR_ZERO VDD VSS / RM_IHPSG13_512x32_c2_1P_BLDRV +XA_BLTMUX<5> A_BLC<5> A_BLC_SEL A_BLT<5> A_BLT_SEL A_PRE_N A_SEL_P<5> A_WR_ONE ++ A_WR_ZERO VDD VSS / RM_IHPSG13_512x32_c2_1P_BLDRV +XA_BLTMUX<4> A_BLC<4> A_BLC_SEL A_BLT<4> A_BLT_SEL A_PRE_N A_SEL_P<4> A_WR_ONE ++ A_WR_ZERO VDD VSS / RM_IHPSG13_512x32_c2_1P_BLDRV +XA_BLTMUX<3> A_BLC<3> A_BLC_SEL A_BLT<3> A_BLT_SEL A_PRE_N A_SEL_P<3> A_WR_ONE ++ A_WR_ZERO VDD VSS / RM_IHPSG13_512x32_c2_1P_BLDRV +XA_BLTMUX<2> A_BLC<2> A_BLC_SEL A_BLT<2> A_BLT_SEL A_PRE_N A_SEL_P<2> A_WR_ONE ++ A_WR_ZERO VDD VSS / RM_IHPSG13_512x32_c2_1P_BLDRV +XA_BLTMUX<1> A_BLC<1> A_BLC_SEL A_BLT<1> A_BLT_SEL A_PRE_N A_SEL_P<1> A_WR_ONE ++ A_WR_ZERO VDD VSS / RM_IHPSG13_512x32_c2_1P_BLDRV +XA_BLTMUX<0> A_BLC<0> A_BLC_SEL A_BLT<0> A_BLT_SEL A_PRE_N A_SEL_P<0> A_WR_ONE ++ A_WR_ZERO VDD VSS / RM_IHPSG13_512x32_c2_1P_BLDRV +XA_CAPS<17> VDD VSS / RSC_IHPSG13_FILLCAP4 +XA_CAPS<16> VDD VSS / RSC_IHPSG13_FILLCAP4 +XA_CAPS<15> VDD VSS / RSC_IHPSG13_FILLCAP4 +XA_CAPS<14> VDD VSS / RSC_IHPSG13_FILLCAP4 +XA_CAPS<13> VDD VSS / RSC_IHPSG13_FILLCAP4 +XA_CAPS<12> VDD VSS / RSC_IHPSG13_FILLCAP4 +XA_CAPS<11> VDD VSS / RSC_IHPSG13_FILLCAP4 +XA_CAPS<10> VDD VSS / RSC_IHPSG13_FILLCAP4 +XA_CAPS<9> VDD VSS / RSC_IHPSG13_FILLCAP4 +XA_CAPS<8> VDD VSS / RSC_IHPSG13_FILLCAP4 +XA_CAPS<7> VDD VSS / RSC_IHPSG13_FILLCAP4 +XA_CAPS<6> VDD VSS / RSC_IHPSG13_FILLCAP4 +XA_CAPS<5> VDD VSS / RSC_IHPSG13_FILLCAP4 +XA_CAPS<4> VDD VSS / RSC_IHPSG13_FILLCAP4 +XA_CAPS<3> VDD VSS / RSC_IHPSG13_FILLCAP4 +XA_CAPS<2> VDD VSS / RSC_IHPSG13_FILLCAP4 +XA_CAPS<1> VDD VSS / RSC_IHPSG13_FILLCAP4 +XA_I51 net19 A_DR_O VDD VSS / RSC_IHPSG13_INVX4 +XA_I78 A_RCLK_B_L A_SAE VDD VSS / RSC_IHPSG13_CBUFX2 +XA_I69 A_DCLK_L A_DCLK_B_L VDD VSS / RSC_IHPSG13_CINVX8 +XA_I50 A_WCLK_L A_WCLK_B_L VDD VSS / RSC_IHPSG13_CINVX8 +XA_EBUF A_RCLK_L A_RCLK_B_L VDD VSS / RSC_IHPSG13_CINVX8 +XA_I76 A_DI_N A_DO_WRITE_P A_WR_ZERO VDD VSS / RSC_IHPSG13_AND2X6 +XA_I75 A_DI_R A_DO_WRITE_P A_WR_ONE VDD VSS / RSC_IHPSG13_AND2X6 +XA_I83 A_BM_R A_BM_N VDD VSS / RSC_IHPSG13_INVX2 +XA_DEC3INV<31> net23<0> A_SEL_P<31> VDD VSS / RSC_IHPSG13_INVX2 +XA_DEC3INV<30> net23<1> A_SEL_P<30> VDD VSS / RSC_IHPSG13_INVX2 +XA_DEC3INV<29> net23<2> A_SEL_P<29> VDD VSS / RSC_IHPSG13_INVX2 +XA_DEC3INV<28> net23<3> A_SEL_P<28> VDD VSS / RSC_IHPSG13_INVX2 +XA_DEC3INV<27> net23<4> A_SEL_P<27> VDD VSS / RSC_IHPSG13_INVX2 +XA_DEC3INV<26> net23<5> A_SEL_P<26> VDD VSS / RSC_IHPSG13_INVX2 +XA_DEC3INV<25> net23<6> A_SEL_P<25> VDD VSS / RSC_IHPSG13_INVX2 +XA_DEC3INV<24> net23<7> A_SEL_P<24> VDD VSS / RSC_IHPSG13_INVX2 +XA_DEC3INV<23> net23<8> A_SEL_P<23> VDD VSS / RSC_IHPSG13_INVX2 +XA_DEC3INV<22> net23<9> A_SEL_P<22> VDD VSS / RSC_IHPSG13_INVX2 +XA_DEC3INV<21> net23<10> A_SEL_P<21> VDD VSS / RSC_IHPSG13_INVX2 +XA_DEC3INV<20> net23<11> A_SEL_P<20> VDD VSS / RSC_IHPSG13_INVX2 +XA_DEC3INV<19> net23<12> A_SEL_P<19> VDD VSS / RSC_IHPSG13_INVX2 +XA_DEC3INV<18> net23<13> A_SEL_P<18> VDD VSS / RSC_IHPSG13_INVX2 +XA_DEC3INV<17> net23<14> A_SEL_P<17> VDD VSS / RSC_IHPSG13_INVX2 +XA_DEC3INV<16> net23<15> A_SEL_P<16> VDD VSS / RSC_IHPSG13_INVX2 +XA_DEC3INV<15> net23<16> A_SEL_P<15> VDD VSS / RSC_IHPSG13_INVX2 +XA_DEC3INV<14> net23<17> A_SEL_P<14> VDD VSS / RSC_IHPSG13_INVX2 +XA_DEC3INV<13> net23<18> A_SEL_P<13> VDD VSS / RSC_IHPSG13_INVX2 +XA_DEC3INV<12> net23<19> A_SEL_P<12> VDD VSS / RSC_IHPSG13_INVX2 +XA_DEC3INV<11> net23<20> A_SEL_P<11> VDD VSS / RSC_IHPSG13_INVX2 +XA_DEC3INV<10> net23<21> A_SEL_P<10> VDD VSS / RSC_IHPSG13_INVX2 +XA_DEC3INV<9> net23<22> A_SEL_P<9> VDD VSS / RSC_IHPSG13_INVX2 +XA_DEC3INV<8> net23<23> A_SEL_P<8> VDD VSS / RSC_IHPSG13_INVX2 +XA_DEC3INV<7> net23<24> A_SEL_P<7> VDD VSS / RSC_IHPSG13_INVX2 +XA_DEC3INV<6> net23<25> A_SEL_P<6> VDD VSS / RSC_IHPSG13_INVX2 +XA_DEC3INV<5> net23<26> A_SEL_P<5> VDD VSS / RSC_IHPSG13_INVX2 +XA_DEC3INV<4> net23<27> A_SEL_P<4> VDD VSS / RSC_IHPSG13_INVX2 +XA_DEC3INV<3> net23<28> A_SEL_P<3> VDD VSS / RSC_IHPSG13_INVX2 +XA_DEC3INV<2> net23<29> A_SEL_P<2> VDD VSS / RSC_IHPSG13_INVX2 +XA_DEC3INV<1> net23<30> A_SEL_P<1> VDD VSS / RSC_IHPSG13_INVX2 +XA_DEC3INV<0> net23<31> A_SEL_P<0> VDD VSS / RSC_IHPSG13_INVX2 +XA_I49 A_DI_R A_DI_N VDD VSS / RSC_IHPSG13_INVX2 +XA_ISENSE A_SAE A_BLC_SEL A_BLT_SEL net19 net20 VDD VSS / ++ RSC_IHPSG13_DFPQD_MSAFFX2 +XA_DREG A_BIST_EN_I A_BIST_DW_I A_DCLK_B_L A_DW_I A_DI_R net22 VDD VSS ++ / RSC_IHPSG13_DFNQMX2IX1 +XA_BREG A_BIST_EN_I A_BIST_BM_I A_DCLK_B_L A_BM_I A_BM_R net21 VDD VSS ++ / RSC_IHPSG13_DFNQMX2IX1 +XA_DEC3<31> A_P1<1> A_P0<1> A_ADDR_DEC<7> net23<0> VDD VSS / ++ RSC_IHPSG13_NAND3X2 +XA_DEC3<30> A_P1<1> A_P0<1> A_ADDR_DEC<6> net23<1> VDD VSS / ++ RSC_IHPSG13_NAND3X2 +XA_DEC3<29> A_P1<1> A_P0<1> A_ADDR_DEC<5> net23<2> VDD VSS / ++ RSC_IHPSG13_NAND3X2 +XA_DEC3<28> A_P1<1> A_P0<1> A_ADDR_DEC<4> net23<3> VDD VSS / ++ RSC_IHPSG13_NAND3X2 +XA_DEC3<27> A_P1<1> A_P0<1> A_ADDR_DEC<3> net23<4> VDD VSS / ++ RSC_IHPSG13_NAND3X2 +XA_DEC3<26> A_P1<1> A_P0<1> A_ADDR_DEC<2> net23<5> VDD VSS / ++ RSC_IHPSG13_NAND3X2 +XA_DEC3<25> A_P1<1> A_P0<1> A_ADDR_DEC<1> net23<6> VDD VSS / ++ RSC_IHPSG13_NAND3X2 +XA_DEC3<24> A_P1<1> A_P0<1> A_ADDR_DEC<0> net23<7> VDD VSS / ++ RSC_IHPSG13_NAND3X2 +XA_DEC3<23> A_P1<1> A_N0<1> A_ADDR_DEC<7> net23<8> VDD VSS / ++ RSC_IHPSG13_NAND3X2 +XA_DEC3<22> A_P1<1> A_N0<1> A_ADDR_DEC<6> net23<9> VDD VSS / ++ RSC_IHPSG13_NAND3X2 +XA_DEC3<21> A_P1<1> A_N0<1> A_ADDR_DEC<5> net23<10> VDD VSS / ++ RSC_IHPSG13_NAND3X2 +XA_DEC3<20> A_P1<1> A_N0<1> A_ADDR_DEC<4> net23<11> VDD VSS / ++ RSC_IHPSG13_NAND3X2 +XA_DEC3<19> A_P1<1> A_N0<1> A_ADDR_DEC<3> net23<12> VDD VSS / ++ RSC_IHPSG13_NAND3X2 +XA_DEC3<18> A_P1<1> A_N0<1> A_ADDR_DEC<2> net23<13> VDD VSS / ++ RSC_IHPSG13_NAND3X2 +XA_DEC3<17> A_P1<1> A_N0<1> A_ADDR_DEC<1> net23<14> VDD VSS / ++ RSC_IHPSG13_NAND3X2 +XA_DEC3<16> A_P1<1> A_N0<1> A_ADDR_DEC<0> net23<15> VDD VSS / ++ RSC_IHPSG13_NAND3X2 +XA_DEC3<15> A_N1<0> A_P0<0> A_ADDR_DEC<7> net23<16> VDD VSS / ++ RSC_IHPSG13_NAND3X2 +XA_DEC3<14> A_N1<0> A_P0<0> A_ADDR_DEC<6> net23<17> VDD VSS / ++ RSC_IHPSG13_NAND3X2 +XA_DEC3<13> A_N1<0> A_P0<0> A_ADDR_DEC<5> net23<18> VDD VSS / ++ RSC_IHPSG13_NAND3X2 +XA_DEC3<12> A_N1<0> A_P0<0> A_ADDR_DEC<4> net23<19> VDD VSS / ++ RSC_IHPSG13_NAND3X2 +XA_DEC3<11> A_N1<0> A_P0<0> A_ADDR_DEC<3> net23<20> VDD VSS / ++ RSC_IHPSG13_NAND3X2 +XA_DEC3<10> A_N1<0> A_P0<0> A_ADDR_DEC<2> net23<21> VDD VSS / ++ RSC_IHPSG13_NAND3X2 +XA_DEC3<9> A_N1<0> A_P0<0> A_ADDR_DEC<1> net23<22> VDD VSS / ++ RSC_IHPSG13_NAND3X2 +XA_DEC3<8> A_N1<0> A_P0<0> A_ADDR_DEC<0> net23<23> VDD VSS / ++ RSC_IHPSG13_NAND3X2 +XA_DEC3<7> A_N1<0> A_N0<0> A_ADDR_DEC<7> net23<24> VDD VSS / ++ RSC_IHPSG13_NAND3X2 +XA_DEC3<6> A_N1<0> A_N0<0> A_ADDR_DEC<6> net23<25> VDD VSS / ++ RSC_IHPSG13_NAND3X2 +XA_DEC3<5> A_N1<0> A_N0<0> A_ADDR_DEC<5> net23<26> VDD VSS / ++ RSC_IHPSG13_NAND3X2 +XA_DEC3<4> A_N1<0> A_N0<0> A_ADDR_DEC<4> net23<27> VDD VSS / ++ RSC_IHPSG13_NAND3X2 +XA_DEC3<3> A_N1<0> A_N0<0> A_ADDR_DEC<3> net23<28> VDD VSS / ++ RSC_IHPSG13_NAND3X2 +XA_DEC3<2> A_N1<0> A_N0<0> A_ADDR_DEC<2> net23<29> VDD VSS / ++ RSC_IHPSG13_NAND3X2 +XA_DEC3<1> A_N1<0> A_N0<0> A_ADDR_DEC<1> net23<30> VDD VSS / ++ RSC_IHPSG13_NAND3X2 +XA_DEC3<0> A_N1<0> A_N0<0> A_ADDR_DEC<0> net23<31> VDD VSS / ++ RSC_IHPSG13_NAND3X2 +XA_I89 A_DCLK_B_L A_DCLK_B_R / RSC_IHPSG13_MET3RES +XA_I91 A_RCLK_B_L A_RCLK_B_R / RSC_IHPSG13_MET3RES +XA_I90 A_WCLK_B_L A_WCLK_B_R / RSC_IHPSG13_MET3RES +XA_I88 A_DCLK_L A_DCLK_R / RSC_IHPSG13_MET3RES +XA_I87 A_WCLK_L A_WCLK_R / RSC_IHPSG13_MET3RES +XA_R2 A_RCLK_L A_RCLK_R / RSC_IHPSG13_MET3RES +XA_BM_TIEH A_TIEH_O VDD VSS / RSC_IHPSG13_TIEH +.ENDS + +.SUBCKT RM_IHPSG13_512x32_c2_1P_COLDRV13X12 ADDR_COL_I<1> ADDR_COL_I<0> ADDR_COL_O<1> ++ ADDR_COL_O<0> ADDR_DEC_I<7> ADDR_DEC_I<6> ADDR_DEC_I<5> ADDR_DEC_I<4> ++ ADDR_DEC_I<3> ADDR_DEC_I<2> ADDR_DEC_I<1> ADDR_DEC_I<0> ADDR_DEC_O<7> ++ ADDR_DEC_O<6> ADDR_DEC_O<5> ADDR_DEC_O<4> ADDR_DEC_O<3> ADDR_DEC_O<2> ++ ADDR_DEC_O<1> ADDR_DEC_O<0> DCLK_I DCLK_O RCLK_I RCLK_O WCLK_I WCLK_O ++ VDD VSS +XI1<1> VDD VSS / RSC_IHPSG13_FILLCAP4 +XI1<0> VDD VSS / RSC_IHPSG13_FILLCAP4 +XI0<1> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI0<0> VDD VSS / RSC_IHPSG13_FILLCAP8 +XADDR_COL_DRV<1> ADDR_COL_I<1> ADDR_COL_O<1> VDD VSS / ++ RSC_IHPSG13_CBUFX12 +XADDR_COL_DRV<0> ADDR_COL_I<0> ADDR_COL_O<0> VDD VSS / ++ RSC_IHPSG13_CBUFX12 +XADDR_DEC_DRV<7> ADDR_DEC_I<7> ADDR_DEC_O<7> VDD VSS / ++ RSC_IHPSG13_CBUFX12 +XADDR_DEC_DRV<6> ADDR_DEC_I<6> ADDR_DEC_O<6> VDD VSS / ++ RSC_IHPSG13_CBUFX12 +XADDR_DEC_DRV<5> ADDR_DEC_I<5> ADDR_DEC_O<5> VDD VSS / ++ RSC_IHPSG13_CBUFX12 +XADDR_DEC_DRV<4> ADDR_DEC_I<4> ADDR_DEC_O<4> VDD VSS / ++ RSC_IHPSG13_CBUFX12 +XADDR_DEC_DRV<3> ADDR_DEC_I<3> ADDR_DEC_O<3> VDD VSS / ++ RSC_IHPSG13_CBUFX12 +XADDR_DEC_DRV<2> ADDR_DEC_I<2> ADDR_DEC_O<2> VDD VSS / ++ RSC_IHPSG13_CBUFX12 +XADDR_DEC_DRV<1> ADDR_DEC_I<1> ADDR_DEC_O<1> VDD VSS / ++ RSC_IHPSG13_CBUFX12 +XADDR_DEC_DRV<0> ADDR_DEC_I<0> ADDR_DEC_O<0> VDD VSS / ++ RSC_IHPSG13_CBUFX12 +XDCLK_DRV DCLK_I DCLK_O VDD VSS / RSC_IHPSG13_CBUFX12 +XRCLK_DRV RCLK_I RCLK_O VDD VSS / RSC_IHPSG13_CBUFX12 +XWCLK_DRV WCLK_I WCLK_O VDD VSS / RSC_IHPSG13_CBUFX12 +.ENDS +.SUBCKT RM_IHPSG13_512x32_c2_1P_WLDRV16X12 A<15> A<14> A<13> A<12> A<11> A<10> A<9> A<8> ++ A<7> A<6> A<5> A<4> A<3> A<2> A<1> A<0> Z<15> Z<14> Z<13> Z<12> Z<11> Z<10> ++ Z<9> Z<8> Z<7> Z<6> Z<5> Z<4> Z<3> Z<2> Z<1> Z<0> VDD VSS +XBUF<15> A<15> Z<15> VDD VSS / RSC_IHPSG13_WLDRVX12 +XBUF<14> A<14> Z<14> VDD VSS / RSC_IHPSG13_WLDRVX12 +XBUF<13> A<13> Z<13> VDD VSS / RSC_IHPSG13_WLDRVX12 +XBUF<12> A<12> Z<12> VDD VSS / RSC_IHPSG13_WLDRVX12 +XBUF<11> A<11> Z<11> VDD VSS / RSC_IHPSG13_WLDRVX12 +XBUF<10> A<10> Z<10> VDD VSS / RSC_IHPSG13_WLDRVX12 +XBUF<9> A<9> Z<9> VDD VSS / RSC_IHPSG13_WLDRVX12 +XBUF<8> A<8> Z<8> VDD VSS / RSC_IHPSG13_WLDRVX12 +XBUF<7> A<7> Z<7> VDD VSS / RSC_IHPSG13_WLDRVX12 +XBUF<6> A<6> Z<6> VDD VSS / RSC_IHPSG13_WLDRVX12 +XBUF<5> A<5> Z<5> VDD VSS / RSC_IHPSG13_WLDRVX12 +XBUF<4> A<4> Z<4> VDD VSS / RSC_IHPSG13_WLDRVX12 +XBUF<3> A<3> Z<3> VDD VSS / RSC_IHPSG13_WLDRVX12 +XBUF<2> A<2> Z<2> VDD VSS / RSC_IHPSG13_WLDRVX12 +XBUF<1> A<1> Z<1> VDD VSS / RSC_IHPSG13_WLDRVX12 +XBUF<0> A<0> Z<0> VDD VSS / RSC_IHPSG13_WLDRVX12 +.ENDS + + + +.SUBCKT RM_IHPSG13_512x32_c2_2P_COLDRV13X8 ADDR_COL_I<1> ADDR_COL_I<0> ADDR_COL_O<1> ++ ADDR_COL_O<0> ADDR_DEC_I<7> ADDR_DEC_I<6> ADDR_DEC_I<5> ADDR_DEC_I<4> ++ ADDR_DEC_I<3> ADDR_DEC_I<2> ADDR_DEC_I<1> ADDR_DEC_I<0> ADDR_DEC_O<7> ++ ADDR_DEC_O<6> ADDR_DEC_O<5> ADDR_DEC_O<4> ADDR_DEC_O<3> ADDR_DEC_O<2> ++ ADDR_DEC_O<1> ADDR_DEC_O<0> DCLK_I DCLK_O RCLK_I RCLK_O WCLK_I WCLK_O ++ VDD VSS +XI0<5> VDD VSS / RSC_IHPSG13_FILLCAP4 +XI0<4> VDD VSS / RSC_IHPSG13_FILLCAP4 +XI0<3> VDD VSS / RSC_IHPSG13_FILLCAP4 +XI0<2> VDD VSS / RSC_IHPSG13_FILLCAP4 +XI0<1> VDD VSS / RSC_IHPSG13_FILLCAP4 +XWCLK_DRV WCLK_I WCLK_O VDD VSS / RSC_IHPSG13_CBUFX8 +XRCLK_DRV RCLK_I RCLK_O VDD VSS / RSC_IHPSG13_CBUFX8 +XDCLK_DRV DCLK_I DCLK_O VDD VSS / RSC_IHPSG13_CBUFX8 +XADDR_COL_DRV<1> ADDR_COL_I<1> ADDR_COL_O<1> VDD VSS / ++ RSC_IHPSG13_CBUFX8 +XADDR_COL_DRV<0> ADDR_COL_I<0> ADDR_COL_O<0> VDD VSS / ++ RSC_IHPSG13_CBUFX8 +XADDR_DEC_DRV<7> ADDR_DEC_I<7> ADDR_DEC_O<7> VDD VSS / ++ RSC_IHPSG13_CBUFX8 +XADDR_DEC_DRV<6> ADDR_DEC_I<6> ADDR_DEC_O<6> VDD VSS / ++ RSC_IHPSG13_CBUFX8 +XADDR_DEC_DRV<5> ADDR_DEC_I<5> ADDR_DEC_O<5> VDD VSS / ++ RSC_IHPSG13_CBUFX8 +XADDR_DEC_DRV<4> ADDR_DEC_I<4> ADDR_DEC_O<4> VDD VSS / ++ RSC_IHPSG13_CBUFX8 +XADDR_DEC_DRV<3> ADDR_DEC_I<3> ADDR_DEC_O<3> VDD VSS / ++ RSC_IHPSG13_CBUFX8 +XADDR_DEC_DRV<2> ADDR_DEC_I<2> ADDR_DEC_O<2> VDD VSS / ++ RSC_IHPSG13_CBUFX8 +XADDR_DEC_DRV<1> ADDR_DEC_I<1> ADDR_DEC_O<1> VDD VSS / ++ RSC_IHPSG13_CBUFX8 +XADDR_DEC_DRV<0> ADDR_DEC_I<0> ADDR_DEC_O<0> VDD VSS / ++ RSC_IHPSG13_CBUFX8 +XI1<3> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI1<2> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI1<1> VDD VSS / RSC_IHPSG13_FILLCAP8 +.ENDS +.SUBCKT RSC_IHPSG13_WLDRVX8 A Z VDD VSS +MN1 Z net6 VSS VSS sg13_lv_nmos m=1 w=1.41u l=130.00n ng=2 nrd=0 nrs=0 +MN0 net6 A VSS VSS sg13_lv_nmos m=1 w=1.8u l=130.00n ng=2 nrd=0 nrs=0 +MP1 Z net6 VDD VDD sg13_lv_pmos m=1 w=6.48u l=130.00n ng=4 nrd=0 nrs=0 +MP0 net6 A VDD VDD sg13_lv_pmos m=1 w=900.0n l=130.00n ng=1 nrd=0 nrs=0 +.ENDS +.SUBCKT RM_IHPSG13_512x32_c2_2P_WLDRV16X8 A<15> A<14> A<13> A<12> A<11> A<10> A<9> A<8> ++ A<7> A<6> A<5> A<4> A<3> A<2> A<1> A<0> Z<15> Z<14> Z<13> Z<12> Z<11> Z<10> ++ Z<9> Z<8> Z<7> Z<6> Z<5> Z<4> Z<3> Z<2> Z<1> Z<0> VDD VSS +XBUF<15> A<15> Z<15> VDD VSS / RSC_IHPSG13_WLDRVX8 +XBUF<14> A<14> Z<14> VDD VSS / RSC_IHPSG13_WLDRVX8 +XBUF<13> A<13> Z<13> VDD VSS / RSC_IHPSG13_WLDRVX8 +XBUF<12> A<12> Z<12> VDD VSS / RSC_IHPSG13_WLDRVX8 +XBUF<11> A<11> Z<11> VDD VSS / RSC_IHPSG13_WLDRVX8 +XBUF<10> A<10> Z<10> VDD VSS / RSC_IHPSG13_WLDRVX8 +XBUF<9> A<9> Z<9> VDD VSS / RSC_IHPSG13_WLDRVX8 +XBUF<8> A<8> Z<8> VDD VSS / RSC_IHPSG13_WLDRVX8 +XBUF<7> A<7> Z<7> VDD VSS / RSC_IHPSG13_WLDRVX8 +XBUF<6> A<6> Z<6> VDD VSS / RSC_IHPSG13_WLDRVX8 +XBUF<5> A<5> Z<5> VDD VSS / RSC_IHPSG13_WLDRVX8 +XBUF<4> A<4> Z<4> VDD VSS / RSC_IHPSG13_WLDRVX8 +XBUF<3> A<3> Z<3> VDD VSS / RSC_IHPSG13_WLDRVX8 +XBUF<2> A<2> Z<2> VDD VSS / RSC_IHPSG13_WLDRVX8 +XBUF<1> A<1> Z<1> VDD VSS / RSC_IHPSG13_WLDRVX8 +XBUF<0> A<0> Z<0> VDD VSS / RSC_IHPSG13_WLDRVX8 +.ENDS + + + +.SUBCKT RM_IHPSG13_512x32_c2_2P_COLDEC2 ACLK_N ADDR<1> ADDR<0> ADDR_COL<1> ADDR_COL<0> ++ ADDR_DEC<7> ADDR_DEC<6> ADDR_DEC<5> ADDR_DEC<4> ADDR_DEC<3> ADDR_DEC<2> ++ ADDR_DEC<1> ADDR_DEC<0> BIST_ADDR<1> BIST_ADDR<0> BIST_EN_I VDD VSS +XI16<17> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI16<16> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI16<15> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI16<14> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI16<13> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI16<12> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI16<11> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI16<10> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI16<9> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI16<8> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI16<7> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI16<6> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI16<5> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI16<4> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI16<3> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI16<2> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI16<1> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI18<24> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI18<23> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI18<22> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI18<21> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI18<20> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI18<19> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI18<18> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI18<17> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI18<16> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI18<15> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI18<14> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI18<13> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI18<12> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI18<11> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI18<10> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI18<9> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI18<8> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI18<7> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI18<6> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI18<5> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI18<4> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI18<3> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI18<2> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI18<1> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI1<3> PADR<0> PADR<1> addr_n<3> VDD VSS / RSC_IHPSG13_NAND2X2 +XI1<2> NADR<0> PADR<1> addr_n<2> VDD VSS / RSC_IHPSG13_NAND2X2 +XI1<1> PADR<0> NADR<1> addr_n<1> VDD VSS / RSC_IHPSG13_NAND2X2 +XI1<0> NADR<0> NADR<1> addr_n<0> VDD VSS / RSC_IHPSG13_NAND2X2 +XI17<1> ADDR_COL<1> VDD VSS / RSC_IHPSG13_TIEL +XI17<0> ADDR_COL<0> VDD VSS / RSC_IHPSG13_TIEL +XI14<3> ADDR_DEC<7> VDD VSS / RSC_IHPSG13_TIEL +XI14<2> ADDR_DEC<6> VDD VSS / RSC_IHPSG13_TIEL +XI14<1> ADDR_DEC<5> VDD VSS / RSC_IHPSG13_TIEL +XI14<0> ADDR_DEC<4> VDD VSS / RSC_IHPSG13_TIEL +XI13<1> NADR<1> PADR<1> VDD VSS / RSC_IHPSG13_INVX2 +XI13<0> NADR<0> PADR<0> VDD VSS / RSC_IHPSG13_INVX2 +XI3<1> padr_int<1> NADR<1> VDD VSS / RSC_IHPSG13_INVX2 +XI3<0> padr_int<0> NADR<0> VDD VSS / RSC_IHPSG13_INVX2 +XI2<3> addr_n<3> ADDR_DEC<3> VDD VSS / RSC_IHPSG13_INVX2 +XI2<2> addr_n<2> ADDR_DEC<2> VDD VSS / RSC_IHPSG13_INVX2 +XI2<1> addr_n<1> ADDR_DEC<1> VDD VSS / RSC_IHPSG13_INVX2 +XI2<0> addr_n<0> ADDR_DEC<0> VDD VSS / RSC_IHPSG13_INVX2 +XDFF<1> BIST_EN_I BIST_ADDR<1> ACLK_N ADDR<1> padr_int<1> net12<0> VDD ++ VSS / RSC_IHPSG13_DFNQMX2IX1 +XDFF<0> BIST_EN_I BIST_ADDR<0> ACLK_N ADDR<0> padr_int<0> net12<1> VDD ++ VSS / RSC_IHPSG13_DFNQMX2IX1 +XI15<5> VDD VSS / RSC_IHPSG13_FILLCAP4 +XI15<4> VDD VSS / RSC_IHPSG13_FILLCAP4 +XI15<3> VDD VSS / RSC_IHPSG13_FILLCAP4 +XI15<2> VDD VSS / RSC_IHPSG13_FILLCAP4 +XI15<1> VDD VSS / RSC_IHPSG13_FILLCAP4 +XI19<4> VDD VSS / RSC_IHPSG13_FILLCAP4 +XI19<3> VDD VSS / RSC_IHPSG13_FILLCAP4 +XI19<2> VDD VSS / RSC_IHPSG13_FILLCAP4 +XI19<1> VDD VSS / RSC_IHPSG13_FILLCAP4 +.ENDS +.SUBCKT RM_IHPSG13_512x32_c2_2P_COLCTRL2 A_ADDR_DEC<3> A_ADDR_DEC<2> A_ADDR_DEC<1> ++ A_ADDR_DEC<0> A_BIST_BM_I A_BIST_DW_I A_BIST_EN_I A_BLC<3> A_BLC<2> A_BLC<1> ++ A_BLC<0> A_BLT<3> A_BLT<2> A_BLT<1> A_BLT<0> A_BM_I A_DCLK_B_L A_DCLK_B_R ++ A_DCLK_L A_DCLK_R A_DR_O A_DW_I A_RCLK_B_L A_RCLK_B_R A_RCLK_L A_RCLK_R ++ A_TIEH_O A_WCLK_B_L A_WCLK_B_R A_WCLK_L A_WCLK_R B_ADDR_DEC<3> B_ADDR_DEC<2> ++ B_ADDR_DEC<1> B_ADDR_DEC<0> B_BIST_BM_I B_BIST_DW_I B_BIST_EN_I B_BLC<3> ++ B_BLC<2> B_BLC<1> B_BLC<0> B_BLT<3> B_BLT<2> B_BLT<1> B_BLT<0> B_BM_I ++ B_DCLK_B_L B_DCLK_B_R B_DCLK_L B_DCLK_R B_DR_O B_DW_I B_RCLK_B_L B_RCLK_B_R ++ B_RCLK_L B_RCLK_R B_TIEH_O B_WCLK_B_L B_WCLK_B_R B_WCLK_L B_WCLK_R VDD ++ VSS +XB_DREG B_BIST_EN_I B_BIST_DW_I B_DCLK_B_L B_DW_I B_DI_R net046 VDD ++ VSS / RSC_IHPSG13_DFNQMX2IX1 +XB_BREG B_BIST_EN_I B_BIST_BM_I B_DCLK_B_L B_BM_I B_BM_R net045 VDD ++ VSS / RSC_IHPSG13_DFNQMX2IX1 +XA_DREG A_BIST_EN_I A_BIST_DW_I A_DCLK_B_L A_DW_I A_DI_R net22 VDD VSS ++ / RSC_IHPSG13_DFNQMX2IX1 +XA_BREG A_BIST_EN_I A_BIST_BM_I A_DCLK_B_L A_BM_I A_BM_R net23 VDD VSS ++ / RSC_IHPSG13_DFNQMX2IX1 +XB_CAPS VDD VSS / RSC_IHPSG13_FILLCAP4 +XA_CAPS VDD VSS / RSC_IHPSG13_FILLCAP4 +XB_I75 B_DI_R B_DO_WRITE_P B_WR_ONE VDD VSS / RSC_IHPSG13_AND2X2 +XB_I80 B_RCLK_B_L B_WCLK_B_L net041 VDD VSS / RSC_IHPSG13_AND2X2 +XB_I76 B_DI_N B_DO_WRITE_P B_WR_ZERO VDD VSS / RSC_IHPSG13_AND2X2 +XA_I80 A_RCLK_B_L A_WCLK_B_L net21 VDD VSS / RSC_IHPSG13_AND2X2 +XA_I75 A_DI_R A_DO_WRITE_P A_WR_ONE VDD VSS / RSC_IHPSG13_AND2X2 +XA_I76 A_DI_N A_DO_WRITE_P A_WR_ZERO VDD VSS / RSC_IHPSG13_AND2X2 +XB_I44 B_WCLK_B_L B_BM_N B_DO_WRITE_P VDD VSS / RSC_IHPSG13_NOR2X2 +XA_I44 A_WCLK_B_L A_BM_N A_DO_WRITE_P VDD VSS / RSC_IHPSG13_NOR2X2 +XB_I81 net041 B_PRE_N VDD VSS / RSC_IHPSG13_CINVX4_WN +XA_I81 net21 A_PRE_N VDD VSS / RSC_IHPSG13_CINVX4_WN +XB_BM_TIEH B_TIEH_O VDD VSS / RSC_IHPSG13_TIEH +XA_BM_TIEH A_TIEH_O VDD VSS / RSC_IHPSG13_TIEH +XA_I89 A_DCLK_B_L A_DCLK_B_R / RSC_IHPSG13_MET3RES +XA_I88 A_DCLK_L A_DCLK_R / RSC_IHPSG13_MET3RES +XA_I87 A_WCLK_L A_WCLK_R / RSC_IHPSG13_MET3RES +XA_I91 A_RCLK_B_L A_RCLK_B_R / RSC_IHPSG13_MET3RES +XB_I87 B_WCLK_L B_WCLK_R / RSC_IHPSG13_MET3RES +XB_I88 B_DCLK_L B_DCLK_R / RSC_IHPSG13_MET3RES +XB_I89 B_DCLK_B_L B_DCLK_B_R / RSC_IHPSG13_MET3RES +XB_I90 B_WCLK_B_L B_WCLK_B_R / RSC_IHPSG13_MET3RES +XB_R2 B_RCLK_L B_RCLK_R / RSC_IHPSG13_MET3RES +XB_I91 B_RCLK_B_L B_RCLK_B_R / RSC_IHPSG13_MET3RES +XA_R2 A_RCLK_L A_RCLK_R / RSC_IHPSG13_MET3RES +XA_I90 A_WCLK_B_L A_WCLK_B_R / RSC_IHPSG13_MET3RES +XAB_BLMUX A_BLC<3> A_BLC<2> A_BLC<1> A_BLC<0> A_BLC_SEL A_BLT<3> A_BLT<2> ++ A_BLT<1> A_BLT<0> A_BLT_SEL A_PRE_N A_ADDR_DEC<3> A_ADDR_DEC<2> ++ A_ADDR_DEC<1> A_ADDR_DEC<0> A_WR_ONE A_WR_ZERO B_BLC<3> B_BLC<2> B_BLC<1> ++ B_BLC<0> B_BLC_SEL B_BLT<3> B_BLT<2> B_BLT<1> B_BLT<0> B_BLT_SEL B_PRE_N ++ B_ADDR_DEC<3> B_ADDR_DEC<2> B_ADDR_DEC<1> B_ADDR_DEC<0> B_WR_ONE B_WR_ZERO ++ VDD VSS / RM_IHPSG13_512x32_c2_2P_BLDRV +XB_ISENSE B_SAE B_BLC_SEL B_BLT_SEL net039 net040 VDD VSS / ++ RSC_IHPSG13_DFPQD_MSAFFX2 +XA_ISENSE A_SAE A_BLC_SEL A_BLT_SEL net19 net20 VDD VSS / ++ RSC_IHPSG13_DFPQD_MSAFFX2 +XB_I78 B_RCLK_B_L B_SAE VDD VSS / RSC_IHPSG13_CBUFX2 +XA_I78 A_RCLK_B_L A_SAE VDD VSS / RSC_IHPSG13_CBUFX2 +XB_I83 B_BM_R B_BM_N VDD VSS / RSC_IHPSG13_INVX2 +XB_I49 B_DI_R B_DI_N VDD VSS / RSC_IHPSG13_INVX2 +XA_I83 A_BM_R A_BM_N VDD VSS / RSC_IHPSG13_INVX2 +XA_I49 A_DI_R A_DI_N VDD VSS / RSC_IHPSG13_INVX2 +XB_I51 net039 B_DR_O VDD VSS / RSC_IHPSG13_INVX4 +XA_I51 net19 A_DR_O VDD VSS / RSC_IHPSG13_INVX4 +XA_I69 A_DCLK_L A_DCLK_B_L VDD VSS / RSC_IHPSG13_CINVX2 +XA_I50 A_WCLK_L A_WCLK_B_L VDD VSS / RSC_IHPSG13_CINVX2 +XA_EBUF A_RCLK_L A_RCLK_B_L VDD VSS / RSC_IHPSG13_CINVX2 +XB_EBUF B_RCLK_L B_RCLK_B_L VDD VSS / RSC_IHPSG13_CINVX2 +XB_I50 B_WCLK_L B_WCLK_B_L VDD VSS / RSC_IHPSG13_CINVX2 +XB_I69 B_DCLK_L B_DCLK_B_L VDD VSS / RSC_IHPSG13_CINVX2 +.ENDS +.SUBCKT RM_IHPSG13_512x32_c2_2P_COLDRV13_FILL4C2 VDD VSS +XI0<2> VDD VSS / RSC_IHPSG13_FILLCAP4 +XI0<1> VDD VSS / RSC_IHPSG13_FILLCAP4 +.ENDS + + +.SUBCKT RM_IHPSG13_512x32_c2_2P_ROWDEC7 ADDR_N_I<6> ADDR_N_I<5> ADDR_N_I<4> ADDR_N_I<3> ++ ADDR_N_I<2> ADDR_N_I<1> ADDR_N_I<0> CS_I ECLK_I WL_O<127> WL_O<126> ++ WL_O<125> WL_O<124> WL_O<123> WL_O<122> WL_O<121> WL_O<120> WL_O<119> ++ WL_O<118> WL_O<117> WL_O<116> WL_O<115> WL_O<114> WL_O<113> WL_O<112> ++ WL_O<111> WL_O<110> WL_O<109> WL_O<108> WL_O<107> WL_O<106> WL_O<105> ++ WL_O<104> WL_O<103> WL_O<102> WL_O<101> WL_O<100> WL_O<99> WL_O<98> WL_O<97> ++ WL_O<96> WL_O<95> WL_O<94> WL_O<93> WL_O<92> WL_O<91> WL_O<90> WL_O<89> ++ WL_O<88> WL_O<87> WL_O<86> WL_O<85> WL_O<84> WL_O<83> WL_O<82> WL_O<81> ++ WL_O<80> WL_O<79> WL_O<78> WL_O<77> WL_O<76> WL_O<75> WL_O<74> WL_O<73> ++ WL_O<72> WL_O<71> WL_O<70> WL_O<69> WL_O<68> WL_O<67> WL_O<66> WL_O<65> ++ WL_O<64> WL_O<63> WL_O<62> WL_O<61> WL_O<60> WL_O<59> WL_O<58> WL_O<57> ++ WL_O<56> WL_O<55> WL_O<54> WL_O<53> WL_O<52> WL_O<51> WL_O<50> WL_O<49> ++ WL_O<48> WL_O<47> WL_O<46> WL_O<45> WL_O<44> WL_O<43> WL_O<42> WL_O<41> ++ WL_O<40> WL_O<39> WL_O<38> WL_O<37> WL_O<36> WL_O<35> WL_O<34> WL_O<33> ++ WL_O<32> WL_O<31> WL_O<30> WL_O<29> WL_O<28> WL_O<27> WL_O<26> WL_O<25> ++ WL_O<24> WL_O<23> WL_O<22> WL_O<21> WL_O<20> WL_O<19> WL_O<18> WL_O<17> ++ WL_O<16> WL_O<15> WL_O<14> WL_O<13> WL_O<12> WL_O<11> WL_O<10> WL_O<9> ++ WL_O<8> WL_O<7> WL_O<6> WL_O<5> WL_O<4> WL_O<3> WL_O<2> WL_O<1> WL_O<0> ++ VDD VSS +XSEL<7> ADDR_N_I<3> ADDR_N_I<2> ADDR_N_I<1> ADDR_N_I<0> CS00<7> ECLK_H<7> ++ ECLK_H<8> ECLK_B<7> ECLK_B<8> WL_O<127> WL_O<126> WL_O<125> WL_O<124> ++ WL_O<123> WL_O<122> WL_O<121> WL_O<120> WL_O<119> WL_O<118> WL_O<117> ++ WL_O<116> WL_O<115> WL_O<114> WL_O<113> WL_O<112> VDD VSS / ++ RM_IHPSG13_512x32_c2_2P_DEC04 +XSEL<6> ADDR_N_I<3> ADDR_N_I<2> ADDR_N_I<1> ADDR_N_I<0> CS00<6> ECLK_H<6> ++ ECLK_H<7> ECLK_B<6> ECLK_B<7> WL_O<111> WL_O<110> WL_O<109> WL_O<108> ++ WL_O<107> WL_O<106> WL_O<105> WL_O<104> WL_O<103> WL_O<102> WL_O<101> ++ WL_O<100> WL_O<99> WL_O<98> WL_O<97> WL_O<96> VDD VSS / ++ RM_IHPSG13_512x32_c2_2P_DEC04 +XSEL<5> ADDR_N_I<3> ADDR_N_I<2> ADDR_N_I<1> ADDR_N_I<0> CS00<5> ECLK_H<5> ++ ECLK_H<6> ECLK_B<5> ECLK_B<6> WL_O<95> WL_O<94> WL_O<93> WL_O<92> WL_O<91> ++ WL_O<90> WL_O<89> WL_O<88> WL_O<87> WL_O<86> WL_O<85> WL_O<84> WL_O<83> ++ WL_O<82> WL_O<81> WL_O<80> VDD VSS / RM_IHPSG13_512x32_c2_2P_DEC04 +XSEL<4> ADDR_N_I<3> ADDR_N_I<2> ADDR_N_I<1> ADDR_N_I<0> CS00<4> ECLK_H<4> ++ ECLK_H<5> ECLK_B<4> ECLK_B<5> WL_O<79> WL_O<78> WL_O<77> WL_O<76> WL_O<75> ++ WL_O<74> WL_O<73> WL_O<72> WL_O<71> WL_O<70> WL_O<69> WL_O<68> WL_O<67> ++ WL_O<66> WL_O<65> WL_O<64> VDD VSS / RM_IHPSG13_512x32_c2_2P_DEC04 +XSEL<3> ADDR_N_I<3> ADDR_N_I<2> ADDR_N_I<1> ADDR_N_I<0> CS00<3> ECLK_H<3> ++ ECLK_H<4> ECLK_B<3> ECLK_B<4> WL_O<63> WL_O<62> WL_O<61> WL_O<60> WL_O<59> ++ WL_O<58> WL_O<57> WL_O<56> WL_O<55> WL_O<54> WL_O<53> WL_O<52> WL_O<51> ++ WL_O<50> WL_O<49> WL_O<48> VDD VSS / RM_IHPSG13_512x32_c2_2P_DEC04 +XSEL<2> ADDR_N_I<3> ADDR_N_I<2> ADDR_N_I<1> ADDR_N_I<0> CS00<2> ECLK_H<2> ++ ECLK_H<3> ECLK_B<2> ECLK_B<3> WL_O<47> WL_O<46> WL_O<45> WL_O<44> WL_O<43> ++ WL_O<42> WL_O<41> WL_O<40> WL_O<39> WL_O<38> WL_O<37> WL_O<36> WL_O<35> ++ WL_O<34> WL_O<33> WL_O<32> VDD VSS / RM_IHPSG13_512x32_c2_2P_DEC04 +XSEL<1> ADDR_N_I<3> ADDR_N_I<2> ADDR_N_I<1> ADDR_N_I<0> CS00<1> ECLK_H<1> ++ ECLK_H<2> ECLK_B<1> ECLK_B<2> WL_O<31> WL_O<30> WL_O<29> WL_O<28> WL_O<27> ++ WL_O<26> WL_O<25> WL_O<24> WL_O<23> WL_O<22> WL_O<21> WL_O<20> WL_O<19> ++ WL_O<18> WL_O<17> WL_O<16> VDD VSS / RM_IHPSG13_512x32_c2_2P_DEC04 +XSEL<0> ADDR_N_I<3> ADDR_N_I<2> ADDR_N_I<1> ADDR_N_I<0> CS00<0> ECLK_I ++ ECLK_H<1> ECLK_B<0> ECLK_B<1> WL_O<15> WL_O<14> WL_O<13> WL_O<12> WL_O<11> ++ WL_O<10> WL_O<9> WL_O<8> WL_O<7> WL_O<6> WL_O<5> WL_O<4> WL_O<3> WL_O<2> ++ WL_O<1> WL_O<0> VDD VSS / RM_IHPSG13_512x32_c2_2P_DEC04 +XDEC11<1> ADDR_N_I<5> ADDR_N_I<4> CS04<1> CS00<7> VDD VSS / ++ RM_IHPSG13_512x32_c2_2P_DEC03 +XDEC11<0> ADDR_N_I<5> ADDR_N_I<4> CS04<0> CS00<3> VDD VSS / ++ RM_IHPSG13_512x32_c2_2P_DEC03 +XDEC01<2> ADDR_N_I<7> ADDR_N_I<6> CS_I CS04<1> VDD VSS / ++ RM_IHPSG13_512x32_c2_2P_DEC01 +XDEC01<1> ADDR_N_I<5> ADDR_N_I<4> CS04<1> CS00<5> VDD VSS / ++ RM_IHPSG13_512x32_c2_2P_DEC01 +XDEC01<0> ADDR_N_I<5> ADDR_N_I<4> CS04<0> CS00<1> VDD VSS / ++ RM_IHPSG13_512x32_c2_2P_DEC01 +XL2<66> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<65> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<64> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<63> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<62> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<61> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<60> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<59> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<58> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<57> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<56> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<55> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<54> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<53> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<52> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<51> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<50> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<49> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<48> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<47> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<46> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<45> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<44> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<43> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<42> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<41> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<40> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<39> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<38> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<37> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<36> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<35> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<34> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<33> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<32> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<31> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<30> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<29> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<28> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<27> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<26> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<25> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<24> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<23> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<22> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<21> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<20> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<19> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<18> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<17> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<16> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<15> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<14> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<13> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<12> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<11> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<10> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<9> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<8> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<7> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<6> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<5> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<4> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<3> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<2> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<1> VDD VSS / RSC_IHPSG13_FILLCAP8 +XDEC10<1> ADDR_N_I<5> ADDR_N_I<4> CS04<1> CS00<6> VDD VSS / ++ RM_IHPSG13_512x32_c2_2P_DEC02 +XDEC10<0> ADDR_N_I<5> ADDR_N_I<4> CS04<0> CS00<2> VDD VSS / ++ RM_IHPSG13_512x32_c2_2P_DEC02 +XDEC00<2> ADDR_N_I<7> ADDR_N_I<6> CS_I CS04<0> VDD VSS / ++ RM_IHPSG13_512x32_c2_2P_DEC00 +XDEC00<1> ADDR_N_I<5> ADDR_N_I<4> CS04<1> CS00<4> VDD VSS / ++ RM_IHPSG13_512x32_c2_2P_DEC00 +XDEC00<0> ADDR_N_I<5> ADDR_N_I<4> CS04<0> CS00<0> VDD VSS / ++ RM_IHPSG13_512x32_c2_2P_DEC00 +XI0 ADDR_N_I<7> VDD VSS / RSC_IHPSG13_TIEL +.ENDS +.SUBCKT RM_IHPSG13_512x32_c2_2P_ROWREG7 ACLK_N_I ADDR_I<6> ADDR_I<5> ADDR_I<4> ADDR_I<3> ++ ADDR_I<2> ADDR_I<1> ADDR_I<0> ADDR_N_O<6> ADDR_N_O<5> ADDR_N_O<4> ++ ADDR_N_O<3> ADDR_N_O<2> ADDR_N_O<1> ADDR_N_O<0> BIST_ADDR_I<6> ++ BIST_ADDR_I<5> BIST_ADDR_I<4> BIST_ADDR_I<3> BIST_ADDR_I<2> BIST_ADDR_I<1> ++ BIST_ADDR_I<0> BIST_EN_I VDD VSS +XINV<6> q_int<6> qn_int<6> VDD VSS / RSC_IHPSG13_CINVX2 +XINV<5> q_int<5> qn_int<5> VDD VSS / RSC_IHPSG13_CINVX2 +XINV<4> q_int<4> qn_int<4> VDD VSS / RSC_IHPSG13_CINVX2 +XINV<3> q_int<3> qn_int<3> VDD VSS / RSC_IHPSG13_CINVX2 +XINV<2> q_int<2> qn_int<2> VDD VSS / RSC_IHPSG13_CINVX2 +XINV<1> q_int<1> qn_int<1> VDD VSS / RSC_IHPSG13_CINVX2 +XINV<0> q_int<0> qn_int<0> VDD VSS / RSC_IHPSG13_CINVX2 +XDRV<6> qn_int<6> ADDR_N_O<6> VDD VSS / RSC_IHPSG13_CINVX8 +XDRV<5> qn_int<5> ADDR_N_O<5> VDD VSS / RSC_IHPSG13_CINVX8 +XDRV<4> qn_int<4> ADDR_N_O<4> VDD VSS / RSC_IHPSG13_CINVX8 +XDRV<3> qn_int<3> ADDR_N_O<3> VDD VSS / RSC_IHPSG13_CINVX8 +XDRV<2> qn_int<2> ADDR_N_O<2> VDD VSS / RSC_IHPSG13_CINVX8 +XDRV<1> qn_int<1> ADDR_N_O<1> VDD VSS / RSC_IHPSG13_CINVX8 +XDRV<0> qn_int<0> ADDR_N_O<0> VDD VSS / RSC_IHPSG13_CINVX8 +XDFF<6> BIST_EN_I BIST_ADDR_I<6> ACLK_N_I ADDR_I<6> q_int<6> net2<0> VDD ++ VSS / RSC_IHPSG13_DFNQMX2IX1 +XDFF<5> BIST_EN_I BIST_ADDR_I<5> ACLK_N_I ADDR_I<5> q_int<5> net2<1> VDD ++ VSS / RSC_IHPSG13_DFNQMX2IX1 +XDFF<4> BIST_EN_I BIST_ADDR_I<4> ACLK_N_I ADDR_I<4> q_int<4> net2<2> VDD ++ VSS / RSC_IHPSG13_DFNQMX2IX1 +XDFF<3> BIST_EN_I BIST_ADDR_I<3> ACLK_N_I ADDR_I<3> q_int<3> net2<3> VDD ++ VSS / RSC_IHPSG13_DFNQMX2IX1 +XDFF<2> BIST_EN_I BIST_ADDR_I<2> ACLK_N_I ADDR_I<2> q_int<2> net2<4> VDD ++ VSS / RSC_IHPSG13_DFNQMX2IX1 +XDFF<1> BIST_EN_I BIST_ADDR_I<1> ACLK_N_I ADDR_I<1> q_int<1> net2<5> VDD ++ VSS / RSC_IHPSG13_DFNQMX2IX1 +XDFF<0> BIST_EN_I BIST_ADDR_I<0> ACLK_N_I ADDR_I<0> q_int<0> net2<6> VDD ++ VSS / RSC_IHPSG13_DFNQMX2IX1 +XI11<7> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI11<6> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI11<5> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI11<4> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI11<3> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI11<2> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI11<1> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI11<0> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI12<1> VDD VSS / RSC_IHPSG13_FILLCAP4 +XI12<0> VDD VSS / RSC_IHPSG13_FILLCAP4 +.ENDS + +.SUBCKT RM_IHPSG13_512x32_c2_2P_ROWDEC4 ADDR_N_I<3> ADDR_N_I<2> ADDR_N_I<1> ADDR_N_I<0> ++ CS_I ECLK_I WL_O<15> WL_O<14> WL_O<13> WL_O<12> WL_O<11> WL_O<10> WL_O<9> ++ WL_O<8> WL_O<7> WL_O<6> WL_O<5> WL_O<4> WL_O<3> WL_O<2> WL_O<1> WL_O<0> ++ VDD VSS +XL2<12> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<11> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<10> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<9> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<8> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<7> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<6> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<5> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<4> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<3> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<2> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<1> VDD VSS / RSC_IHPSG13_FILLCAP8 +XSEL ADDR_N_I<3> ADDR_N_I<2> ADDR_N_I<1> ADDR_N_I<0> CS_I ECLK_I ECLK_H<1> ++ ECLK_B<0> ECLK_B<1> WL_O<15> WL_O<14> WL_O<13> WL_O<12> WL_O<11> WL_O<10> ++ WL_O<9> WL_O<8> WL_O<7> WL_O<6> WL_O<5> WL_O<4> WL_O<3> WL_O<2> WL_O<1> ++ WL_O<0> VDD VSS / RM_IHPSG13_512x32_c2_2P_DEC04 +.ENDS +.SUBCKT RM_IHPSG13_512x32_c2_2P_ROWREG4 ACLK_N_I ADDR_I<3> ADDR_I<2> ADDR_I<1> ADDR_I<0> ++ ADDR_N_O<3> ADDR_N_O<2> ADDR_N_O<1> ADDR_N_O<0> BIST_ADDR_I<3> ++ BIST_ADDR_I<2> BIST_ADDR_I<1> BIST_ADDR_I<0> BIST_EN_I VDD VSS +XINV<3> q_int<3> qn_int<3> VDD VSS / RSC_IHPSG13_CINVX2 +XINV<2> q_int<2> qn_int<2> VDD VSS / RSC_IHPSG13_CINVX2 +XINV<1> q_int<1> qn_int<1> VDD VSS / RSC_IHPSG13_CINVX2 +XINV<0> q_int<0> qn_int<0> VDD VSS / RSC_IHPSG13_CINVX2 +XDRV<3> qn_int<3> ADDR_N_O<3> VDD VSS / RSC_IHPSG13_CINVX8 +XDRV<2> qn_int<2> ADDR_N_O<2> VDD VSS / RSC_IHPSG13_CINVX8 +XDRV<1> qn_int<1> ADDR_N_O<1> VDD VSS / RSC_IHPSG13_CINVX8 +XDRV<0> qn_int<0> ADDR_N_O<0> VDD VSS / RSC_IHPSG13_CINVX8 +XDFF<3> BIST_EN_I BIST_ADDR_I<3> ACLK_N_I ADDR_I<3> q_int<3> net7<0> VDD ++ VSS / RSC_IHPSG13_DFNQMX2IX1 +XDFF<2> BIST_EN_I BIST_ADDR_I<2> ACLK_N_I ADDR_I<2> q_int<2> net7<1> VDD ++ VSS / RSC_IHPSG13_DFNQMX2IX1 +XDFF<1> BIST_EN_I BIST_ADDR_I<1> ACLK_N_I ADDR_I<1> q_int<1> net7<2> VDD ++ VSS / RSC_IHPSG13_DFNQMX2IX1 +XDFF<0> BIST_EN_I BIST_ADDR_I<0> ACLK_N_I ADDR_I<0> q_int<0> net7<3> VDD ++ VSS / RSC_IHPSG13_DFNQMX2IX1 +XI11<20> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI11<19> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI11<18> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI11<17> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI11<16> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI11<15> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI11<14> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI11<13> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI11<12> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI11<11> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI11<10> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI11<9> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI11<8> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI11<7> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI11<6> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI11<5> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI11<4> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI11<3> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI11<2> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI11<1> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI12<4> VDD VSS / RSC_IHPSG13_FILLCAP4 +XI12<3> VDD VSS / RSC_IHPSG13_FILLCAP4 +XI12<2> VDD VSS / RSC_IHPSG13_FILLCAP4 +XI12<1> VDD VSS / RSC_IHPSG13_FILLCAP4 +XI12<0> VDD VSS / RSC_IHPSG13_FILLCAP4 +.ENDS + + +.SUBCKT RM_IHPSG13_512x32_c2_1P_BITKIT_TAP BLC BLT NW PW VDD VSS +.ENDS +.SUBCKT RM_IHPSG13_512x32_c2_1P_BITKIT_16x2_TAP A_BLC<1> A_BLC<0> A_BLT<1> A_BLT<0> ++ VDD_CORE VSS +XITAP<1> A_BLC<1> A_BLT<1> VDD_CORE VSS VDD_CORE VSS ++ / RM_IHPSG13_512x32_c2_1P_BITKIT_TAP +XITAP<0> A_BLC<0> A_BLT<0> VDD_CORE VSS VDD_CORE VSS ++ / RM_IHPSG13_512x32_c2_1P_BITKIT_TAP +XIEDGEBP_COL1<1> BLC<1> BLT<1> VDD_CORE VSS VDD_CORE ++ VSS / RM_IHPSG13_512x32_c2_1P_BITKIT_EDGE_TB +XIEDGEBP_COL1<0> BLC<1> BLT<1> VDD_CORE VSS VDD_CORE ++ VSS / RM_IHPSG13_512x32_c2_1P_BITKIT_EDGE_TB +XIEDGEBP_COL2<1> BLC<0> BLT<0> VDD_CORE VSS VDD_CORE ++ VSS / RM_IHPSG13_512x32_c2_1P_BITKIT_EDGE_TB +XIEDGEBP_COL2<0> BLC<0> BLT<0> VDD_CORE VSS VDD_CORE ++ VSS / RM_IHPSG13_512x32_c2_1P_BITKIT_EDGE_TB +.ENDS +.SUBCKT RM_IHPSG13_512x32_c2_1P_BITKIT_16x2_TAP_LR VDD_CORE VSS +XCORNER<1> VDD_CORE VSS VDD_CORE VSS / ++ RM_IHPSG13_512x32_c2_1P_BITKIT_CORNER +XCORNER<0> VDD_CORE VSS VDD_CORE VSS / ++ RM_IHPSG13_512x32_c2_1P_BITKIT_CORNER +XTAP_BORDER VDD_CORE VSS VDD_CORE VSS / ++ RM_IHPSG13_512x32_c2_1P_BITKIT_TAP_LR +.ENDS +.SUBCKT RM_IHPSG13_512x32_c2_1P_DEC03 ADDR<1> ADDR<0> CS CS_OUT VDD VSS +XDECINV net1 CS_OUT VDD VSS / RSC_IHPSG13_INVX4 +XI0 VDD VSS / RSC_IHPSG13_FILLCAP4 +XDEC ADDR<1> ADDR<0> CS net1 VDD VSS / RSC_IHPSG13_NAND3X2 +.ENDS +.SUBCKT RM_IHPSG13_512x32_c2_1P_DEC02 ADDR<1> ADDR<0> CS CS_OUT VDD VSS +XDECINV net1 CS_OUT VDD VSS / RSC_IHPSG13_INVX4 +XDEC ADDR<1> NADDR<0> CS net1 VDD VSS / RSC_IHPSG13_NAND3X2 +XI2 VDD VSS / RSC_IHPSG13_FILLCAP4 +XADDRINV ADDR<0> NADDR<0> VDD VSS / RSC_IHPSG13_INVX2 +.ENDS +.SUBCKT RM_IHPSG13_512x32_c2_1P_ROWDEC8 ADDR_N_I<7> ADDR_N_I<6> ADDR_N_I<5> ADDR_N_I<4> ++ ADDR_N_I<3> ADDR_N_I<2> ADDR_N_I<1> ADDR_N_I<0> CS_I ECLK_I WL_O<255> ++ WL_O<254> WL_O<253> WL_O<252> WL_O<251> WL_O<250> WL_O<249> WL_O<248> ++ WL_O<247> WL_O<246> WL_O<245> WL_O<244> WL_O<243> WL_O<242> WL_O<241> ++ WL_O<240> WL_O<239> WL_O<238> WL_O<237> WL_O<236> WL_O<235> WL_O<234> ++ WL_O<233> WL_O<232> WL_O<231> WL_O<230> WL_O<229> WL_O<228> WL_O<227> ++ WL_O<226> WL_O<225> WL_O<224> WL_O<223> WL_O<222> WL_O<221> WL_O<220> ++ WL_O<219> WL_O<218> WL_O<217> WL_O<216> WL_O<215> WL_O<214> WL_O<213> ++ WL_O<212> WL_O<211> WL_O<210> WL_O<209> WL_O<208> WL_O<207> WL_O<206> ++ WL_O<205> WL_O<204> WL_O<203> WL_O<202> WL_O<201> WL_O<200> WL_O<199> ++ WL_O<198> WL_O<197> WL_O<196> WL_O<195> WL_O<194> WL_O<193> WL_O<192> ++ WL_O<191> WL_O<190> WL_O<189> WL_O<188> WL_O<187> WL_O<186> WL_O<185> ++ WL_O<184> WL_O<183> WL_O<182> WL_O<181> WL_O<180> WL_O<179> WL_O<178> ++ WL_O<177> WL_O<176> WL_O<175> WL_O<174> WL_O<173> WL_O<172> WL_O<171> ++ WL_O<170> WL_O<169> WL_O<168> WL_O<167> WL_O<166> WL_O<165> WL_O<164> ++ WL_O<163> WL_O<162> WL_O<161> WL_O<160> WL_O<159> WL_O<158> WL_O<157> ++ WL_O<156> WL_O<155> WL_O<154> WL_O<153> WL_O<152> WL_O<151> WL_O<150> ++ WL_O<149> WL_O<148> WL_O<147> WL_O<146> WL_O<145> WL_O<144> WL_O<143> ++ WL_O<142> WL_O<141> WL_O<140> WL_O<139> WL_O<138> WL_O<137> WL_O<136> ++ WL_O<135> WL_O<134> WL_O<133> WL_O<132> WL_O<131> WL_O<130> WL_O<129> ++ WL_O<128> WL_O<127> WL_O<126> WL_O<125> WL_O<124> WL_O<123> WL_O<122> ++ WL_O<121> WL_O<120> WL_O<119> WL_O<118> WL_O<117> WL_O<116> WL_O<115> ++ WL_O<114> WL_O<113> WL_O<112> WL_O<111> WL_O<110> WL_O<109> WL_O<108> ++ WL_O<107> WL_O<106> WL_O<105> WL_O<104> WL_O<103> WL_O<102> WL_O<101> ++ WL_O<100> WL_O<99> WL_O<98> WL_O<97> WL_O<96> WL_O<95> WL_O<94> WL_O<93> ++ WL_O<92> WL_O<91> WL_O<90> WL_O<89> WL_O<88> WL_O<87> WL_O<86> WL_O<85> ++ WL_O<84> WL_O<83> WL_O<82> WL_O<81> WL_O<80> WL_O<79> WL_O<78> WL_O<77> ++ WL_O<76> WL_O<75> WL_O<74> WL_O<73> WL_O<72> WL_O<71> WL_O<70> WL_O<69> ++ WL_O<68> WL_O<67> WL_O<66> WL_O<65> WL_O<64> WL_O<63> WL_O<62> WL_O<61> ++ WL_O<60> WL_O<59> WL_O<58> WL_O<57> WL_O<56> WL_O<55> WL_O<54> WL_O<53> ++ WL_O<52> WL_O<51> WL_O<50> WL_O<49> WL_O<48> WL_O<47> WL_O<46> WL_O<45> ++ WL_O<44> WL_O<43> WL_O<42> WL_O<41> WL_O<40> WL_O<39> WL_O<38> WL_O<37> ++ WL_O<36> WL_O<35> WL_O<34> WL_O<33> WL_O<32> WL_O<31> WL_O<30> WL_O<29> ++ WL_O<28> WL_O<27> WL_O<26> WL_O<25> WL_O<24> WL_O<23> WL_O<22> WL_O<21> ++ WL_O<20> WL_O<19> WL_O<18> WL_O<17> WL_O<16> WL_O<15> WL_O<14> WL_O<13> ++ WL_O<12> WL_O<11> WL_O<10> WL_O<9> WL_O<8> WL_O<7> WL_O<6> WL_O<5> WL_O<4> ++ WL_O<3> WL_O<2> WL_O<1> WL_O<0> VDD VSS +XDEC11<4> ADDR_N_I<7> ADDR_N_I<6> CS_I CS04<3> VDD VSS / ++ RM_IHPSG13_512x32_c2_1P_DEC03 +XDEC11<3> ADDR_N_I<5> ADDR_N_I<4> CS04<3> CS00<15> VDD VSS / ++ RM_IHPSG13_512x32_c2_1P_DEC03 +XDEC11<2> ADDR_N_I<5> ADDR_N_I<4> CS04<2> CS00<11> VDD VSS / ++ RM_IHPSG13_512x32_c2_1P_DEC03 +XDEC11<1> ADDR_N_I<5> ADDR_N_I<4> CS04<1> CS00<7> VDD VSS / ++ RM_IHPSG13_512x32_c2_1P_DEC03 +XDEC11<0> ADDR_N_I<5> ADDR_N_I<4> CS04<0> CS00<3> VDD VSS / ++ RM_IHPSG13_512x32_c2_1P_DEC03 +XL2<88> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<87> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<86> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<85> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<84> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<83> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<82> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<81> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<80> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<79> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<78> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<77> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<76> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<75> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<74> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<73> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<72> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<71> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<70> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<69> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<68> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<67> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<66> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<65> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<64> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<63> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<62> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<61> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<60> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<59> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<58> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<57> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<56> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<55> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<54> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<53> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<52> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<51> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<50> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<49> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<48> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<47> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<46> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<45> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<44> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<43> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<42> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<41> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<40> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<39> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<38> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<37> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<36> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<35> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<34> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<33> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<32> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<31> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<30> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<29> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<28> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<27> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<26> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<25> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<24> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<23> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<22> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<21> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<20> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<19> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<18> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<17> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<16> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<15> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<14> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<13> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<12> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<11> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<10> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<9> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<8> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<7> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<6> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<5> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<4> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<3> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<2> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<1> VDD VSS / RSC_IHPSG13_FILLCAP8 +XDEC10<4> ADDR_N_I<7> ADDR_N_I<6> CS_I CS04<2> VDD VSS / ++ RM_IHPSG13_512x32_c2_1P_DEC02 +XDEC10<3> ADDR_N_I<5> ADDR_N_I<4> CS04<3> CS00<14> VDD VSS / ++ RM_IHPSG13_512x32_c2_1P_DEC02 +XDEC10<2> ADDR_N_I<5> ADDR_N_I<4> CS04<2> CS00<10> VDD VSS / ++ RM_IHPSG13_512x32_c2_1P_DEC02 +XDEC10<1> ADDR_N_I<5> ADDR_N_I<4> CS04<1> CS00<6> VDD VSS / ++ RM_IHPSG13_512x32_c2_1P_DEC02 +XDEC10<0> ADDR_N_I<5> ADDR_N_I<4> CS04<0> CS00<2> VDD VSS / ++ RM_IHPSG13_512x32_c2_1P_DEC02 +XDEC00<4> ADDR_N_I<7> ADDR_N_I<6> CS_I CS04<0> VDD VSS / ++ RM_IHPSG13_512x32_c2_1P_DEC00 +XDEC00<3> ADDR_N_I<5> ADDR_N_I<4> CS04<3> CS00<12> VDD VSS / ++ RM_IHPSG13_512x32_c2_1P_DEC00 +XDEC00<2> ADDR_N_I<5> ADDR_N_I<4> CS04<2> CS00<8> VDD VSS / ++ RM_IHPSG13_512x32_c2_1P_DEC00 +XDEC00<1> ADDR_N_I<5> ADDR_N_I<4> CS04<1> CS00<4> VDD VSS / ++ RM_IHPSG13_512x32_c2_1P_DEC00 +XDEC00<0> ADDR_N_I<5> ADDR_N_I<4> CS04<0> CS00<0> VDD VSS / ++ RM_IHPSG13_512x32_c2_1P_DEC00 +XSEL<15> ADDR_N_I<3> ADDR_N_I<2> ADDR_N_I<1> ADDR_N_I<0> CS00<15> ECLK_H<15> ++ ECLK_H<16> ECLK_B<15> ECLK_B<16> WL_O<255> WL_O<254> WL_O<253> WL_O<252> ++ WL_O<251> WL_O<250> WL_O<249> WL_O<248> WL_O<247> WL_O<246> WL_O<245> ++ WL_O<244> WL_O<243> WL_O<242> WL_O<241> WL_O<240> VDD VSS / ++ RM_IHPSG13_512x32_c2_1P_DEC04 +XSEL<14> ADDR_N_I<3> ADDR_N_I<2> ADDR_N_I<1> ADDR_N_I<0> CS00<14> ECLK_H<14> ++ ECLK_H<15> ECLK_B<14> ECLK_B<15> WL_O<239> WL_O<238> WL_O<237> WL_O<236> ++ WL_O<235> WL_O<234> WL_O<233> WL_O<232> WL_O<231> WL_O<230> WL_O<229> ++ WL_O<228> WL_O<227> WL_O<226> WL_O<225> WL_O<224> VDD VSS / ++ RM_IHPSG13_512x32_c2_1P_DEC04 +XSEL<13> ADDR_N_I<3> ADDR_N_I<2> ADDR_N_I<1> ADDR_N_I<0> CS00<13> ECLK_H<13> ++ ECLK_H<14> ECLK_B<13> ECLK_B<14> WL_O<223> WL_O<222> WL_O<221> WL_O<220> ++ WL_O<219> WL_O<218> WL_O<217> WL_O<216> WL_O<215> WL_O<214> WL_O<213> ++ WL_O<212> WL_O<211> WL_O<210> WL_O<209> WL_O<208> VDD VSS / ++ RM_IHPSG13_512x32_c2_1P_DEC04 +XSEL<12> ADDR_N_I<3> ADDR_N_I<2> ADDR_N_I<1> ADDR_N_I<0> CS00<12> ECLK_H<12> ++ ECLK_H<13> ECLK_B<12> ECLK_B<13> WL_O<207> WL_O<206> WL_O<205> WL_O<204> ++ WL_O<203> WL_O<202> WL_O<201> WL_O<200> WL_O<199> WL_O<198> WL_O<197> ++ WL_O<196> WL_O<195> WL_O<194> WL_O<193> WL_O<192> VDD VSS / ++ RM_IHPSG13_512x32_c2_1P_DEC04 +XSEL<11> ADDR_N_I<3> ADDR_N_I<2> ADDR_N_I<1> ADDR_N_I<0> CS00<11> ECLK_H<11> ++ ECLK_H<12> ECLK_B<11> ECLK_B<12> WL_O<191> WL_O<190> WL_O<189> WL_O<188> ++ WL_O<187> WL_O<186> WL_O<185> WL_O<184> WL_O<183> WL_O<182> WL_O<181> ++ WL_O<180> WL_O<179> WL_O<178> WL_O<177> WL_O<176> VDD VSS / ++ RM_IHPSG13_512x32_c2_1P_DEC04 +XSEL<10> ADDR_N_I<3> ADDR_N_I<2> ADDR_N_I<1> ADDR_N_I<0> CS00<10> ECLK_H<10> ++ ECLK_H<11> ECLK_B<10> ECLK_B<11> WL_O<175> WL_O<174> WL_O<173> WL_O<172> ++ WL_O<171> WL_O<170> WL_O<169> WL_O<168> WL_O<167> WL_O<166> WL_O<165> ++ WL_O<164> WL_O<163> WL_O<162> WL_O<161> WL_O<160> VDD VSS / ++ RM_IHPSG13_512x32_c2_1P_DEC04 +XSEL<9> ADDR_N_I<3> ADDR_N_I<2> ADDR_N_I<1> ADDR_N_I<0> CS00<9> ECLK_H<9> ++ ECLK_H<10> ECLK_B<9> ECLK_B<10> WL_O<159> WL_O<158> WL_O<157> WL_O<156> ++ WL_O<155> WL_O<154> WL_O<153> WL_O<152> WL_O<151> WL_O<150> WL_O<149> ++ WL_O<148> WL_O<147> WL_O<146> WL_O<145> WL_O<144> VDD VSS / ++ RM_IHPSG13_512x32_c2_1P_DEC04 +XSEL<8> ADDR_N_I<3> ADDR_N_I<2> ADDR_N_I<1> ADDR_N_I<0> CS00<8> ECLK_H<8> ++ ECLK_H<9> ECLK_B<8> ECLK_B<9> WL_O<143> WL_O<142> WL_O<141> WL_O<140> ++ WL_O<139> WL_O<138> WL_O<137> WL_O<136> WL_O<135> WL_O<134> WL_O<133> ++ WL_O<132> WL_O<131> WL_O<130> WL_O<129> WL_O<128> VDD VSS / ++ RM_IHPSG13_512x32_c2_1P_DEC04 +XSEL<7> ADDR_N_I<3> ADDR_N_I<2> ADDR_N_I<1> ADDR_N_I<0> CS00<7> ECLK_H<7> ++ ECLK_H<8> ECLK_B<7> ECLK_B<8> WL_O<127> WL_O<126> WL_O<125> WL_O<124> ++ WL_O<123> WL_O<122> WL_O<121> WL_O<120> WL_O<119> WL_O<118> WL_O<117> ++ WL_O<116> WL_O<115> WL_O<114> WL_O<113> WL_O<112> VDD VSS / ++ RM_IHPSG13_512x32_c2_1P_DEC04 +XSEL<6> ADDR_N_I<3> ADDR_N_I<2> ADDR_N_I<1> ADDR_N_I<0> CS00<6> ECLK_H<6> ++ ECLK_H<7> ECLK_B<6> ECLK_B<7> WL_O<111> WL_O<110> WL_O<109> WL_O<108> ++ WL_O<107> WL_O<106> WL_O<105> WL_O<104> WL_O<103> WL_O<102> WL_O<101> ++ WL_O<100> WL_O<99> WL_O<98> WL_O<97> WL_O<96> VDD VSS / ++ RM_IHPSG13_512x32_c2_1P_DEC04 +XSEL<5> ADDR_N_I<3> ADDR_N_I<2> ADDR_N_I<1> ADDR_N_I<0> CS00<5> ECLK_H<5> ++ ECLK_H<6> ECLK_B<5> ECLK_B<6> WL_O<95> WL_O<94> WL_O<93> WL_O<92> WL_O<91> ++ WL_O<90> WL_O<89> WL_O<88> WL_O<87> WL_O<86> WL_O<85> WL_O<84> WL_O<83> ++ WL_O<82> WL_O<81> WL_O<80> VDD VSS / RM_IHPSG13_512x32_c2_1P_DEC04 +XSEL<4> ADDR_N_I<3> ADDR_N_I<2> ADDR_N_I<1> ADDR_N_I<0> CS00<4> ECLK_H<4> ++ ECLK_H<5> ECLK_B<4> ECLK_B<5> WL_O<79> WL_O<78> WL_O<77> WL_O<76> WL_O<75> ++ WL_O<74> WL_O<73> WL_O<72> WL_O<71> WL_O<70> WL_O<69> WL_O<68> WL_O<67> ++ WL_O<66> WL_O<65> WL_O<64> VDD VSS / RM_IHPSG13_512x32_c2_1P_DEC04 +XSEL<3> ADDR_N_I<3> ADDR_N_I<2> ADDR_N_I<1> ADDR_N_I<0> CS00<3> ECLK_H<3> ++ ECLK_H<4> ECLK_B<3> ECLK_B<4> WL_O<63> WL_O<62> WL_O<61> WL_O<60> WL_O<59> ++ WL_O<58> WL_O<57> WL_O<56> WL_O<55> WL_O<54> WL_O<53> WL_O<52> WL_O<51> ++ WL_O<50> WL_O<49> WL_O<48> VDD VSS / RM_IHPSG13_512x32_c2_1P_DEC04 +XSEL<2> ADDR_N_I<3> ADDR_N_I<2> ADDR_N_I<1> ADDR_N_I<0> CS00<2> ECLK_H<2> ++ ECLK_H<3> ECLK_B<2> ECLK_B<3> WL_O<47> WL_O<46> WL_O<45> WL_O<44> WL_O<43> ++ WL_O<42> WL_O<41> WL_O<40> WL_O<39> WL_O<38> WL_O<37> WL_O<36> WL_O<35> ++ WL_O<34> WL_O<33> WL_O<32> VDD VSS / RM_IHPSG13_512x32_c2_1P_DEC04 +XSEL<1> ADDR_N_I<3> ADDR_N_I<2> ADDR_N_I<1> ADDR_N_I<0> CS00<1> ECLK_H<1> ++ ECLK_H<2> ECLK_B<1> ECLK_B<2> WL_O<31> WL_O<30> WL_O<29> WL_O<28> WL_O<27> ++ WL_O<26> WL_O<25> WL_O<24> WL_O<23> WL_O<22> WL_O<21> WL_O<20> WL_O<19> ++ WL_O<18> WL_O<17> WL_O<16> VDD VSS / RM_IHPSG13_512x32_c2_1P_DEC04 +XSEL<0> ADDR_N_I<3> ADDR_N_I<2> ADDR_N_I<1> ADDR_N_I<0> CS00<0> ECLK_I ++ ECLK_H<1> ECLK_B<0> ECLK_B<1> WL_O<15> WL_O<14> WL_O<13> WL_O<12> WL_O<11> ++ WL_O<10> WL_O<9> WL_O<8> WL_O<7> WL_O<6> WL_O<5> WL_O<4> WL_O<3> WL_O<2> ++ WL_O<1> WL_O<0> VDD VSS / RM_IHPSG13_512x32_c2_1P_DEC04 +XDEC01<4> ADDR_N_I<7> ADDR_N_I<6> CS_I CS04<1> VDD VSS / ++ RM_IHPSG13_512x32_c2_1P_DEC01 +XDEC01<3> ADDR_N_I<5> ADDR_N_I<4> CS04<3> CS00<13> VDD VSS / ++ RM_IHPSG13_512x32_c2_1P_DEC01 +XDEC01<2> ADDR_N_I<5> ADDR_N_I<4> CS04<2> CS00<9> VDD VSS / ++ RM_IHPSG13_512x32_c2_1P_DEC01 +XDEC01<1> ADDR_N_I<5> ADDR_N_I<4> CS04<1> CS00<5> VDD VSS / ++ RM_IHPSG13_512x32_c2_1P_DEC01 +XDEC01<0> ADDR_N_I<5> ADDR_N_I<4> CS04<0> CS00<1> VDD VSS / ++ RM_IHPSG13_512x32_c2_1P_DEC01 +.ENDS +.SUBCKT RM_IHPSG13_512x32_c2_1P_ROWREG8 ACLK_N_I ADDR_I<7> ADDR_I<6> ADDR_I<5> ADDR_I<4> ++ ADDR_I<3> ADDR_I<2> ADDR_I<1> ADDR_I<0> ADDR_N_O<7> ADDR_N_O<6> ADDR_N_O<5> ++ ADDR_N_O<4> ADDR_N_O<3> ADDR_N_O<2> ADDR_N_O<1> ADDR_N_O<0> BIST_ADDR_I<7> ++ BIST_ADDR_I<6> BIST_ADDR_I<5> BIST_ADDR_I<4> BIST_ADDR_I<3> BIST_ADDR_I<2> ++ BIST_ADDR_I<1> BIST_ADDR_I<0> BIST_EN_I VDD VSS +XINV<7> q_int<7> qn_int<7> VDD VSS / RSC_IHPSG13_CINVX2 +XINV<6> q_int<6> qn_int<6> VDD VSS / RSC_IHPSG13_CINVX2 +XINV<5> q_int<5> qn_int<5> VDD VSS / RSC_IHPSG13_CINVX2 +XINV<4> q_int<4> qn_int<4> VDD VSS / RSC_IHPSG13_CINVX2 +XINV<3> q_int<3> qn_int<3> VDD VSS / RSC_IHPSG13_CINVX2 +XINV<2> q_int<2> qn_int<2> VDD VSS / RSC_IHPSG13_CINVX2 +XINV<1> q_int<1> qn_int<1> VDD VSS / RSC_IHPSG13_CINVX2 +XINV<0> q_int<0> qn_int<0> VDD VSS / RSC_IHPSG13_CINVX2 +XDRV<7> qn_int<7> ADDR_N_O<7> VDD VSS / RSC_IHPSG13_CINVX8 +XDRV<6> qn_int<6> ADDR_N_O<6> VDD VSS / RSC_IHPSG13_CINVX8 +XDRV<5> qn_int<5> ADDR_N_O<5> VDD VSS / RSC_IHPSG13_CINVX8 +XDRV<4> qn_int<4> ADDR_N_O<4> VDD VSS / RSC_IHPSG13_CINVX8 +XDRV<3> qn_int<3> ADDR_N_O<3> VDD VSS / RSC_IHPSG13_CINVX8 +XDRV<2> qn_int<2> ADDR_N_O<2> VDD VSS / RSC_IHPSG13_CINVX8 +XDRV<1> qn_int<1> ADDR_N_O<1> VDD VSS / RSC_IHPSG13_CINVX8 +XDRV<0> qn_int<0> ADDR_N_O<0> VDD VSS / RSC_IHPSG13_CINVX8 +XDFF<7> BIST_EN_I BIST_ADDR_I<7> ACLK_N_I ADDR_I<7> q_int<7> net2<0> VDD ++ VSS / RSC_IHPSG13_DFNQMX2IX1 +XDFF<6> BIST_EN_I BIST_ADDR_I<6> ACLK_N_I ADDR_I<6> q_int<6> net2<1> VDD ++ VSS / RSC_IHPSG13_DFNQMX2IX1 +XDFF<5> BIST_EN_I BIST_ADDR_I<5> ACLK_N_I ADDR_I<5> q_int<5> net2<2> VDD ++ VSS / RSC_IHPSG13_DFNQMX2IX1 +XDFF<4> BIST_EN_I BIST_ADDR_I<4> ACLK_N_I ADDR_I<4> q_int<4> net2<3> VDD ++ VSS / RSC_IHPSG13_DFNQMX2IX1 +XDFF<3> BIST_EN_I BIST_ADDR_I<3> ACLK_N_I ADDR_I<3> q_int<3> net2<4> VDD ++ VSS / RSC_IHPSG13_DFNQMX2IX1 +XDFF<2> BIST_EN_I BIST_ADDR_I<2> ACLK_N_I ADDR_I<2> q_int<2> net2<5> VDD ++ VSS / RSC_IHPSG13_DFNQMX2IX1 +XDFF<1> BIST_EN_I BIST_ADDR_I<1> ACLK_N_I ADDR_I<1> q_int<1> net2<6> VDD ++ VSS / RSC_IHPSG13_DFNQMX2IX1 +XDFF<0> BIST_EN_I BIST_ADDR_I<0> ACLK_N_I ADDR_I<0> q_int<0> net2<7> VDD ++ VSS / RSC_IHPSG13_DFNQMX2IX1 +XI11<4> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI11<3> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI11<2> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI11<1> VDD VSS / RSC_IHPSG13_FILLCAP8 +.ENDS + +.SUBCKT RM_IHPSG13_512x32_c2_1P_ROWDEC9 ADDR_N_I<8> ADDR_N_I<7> ADDR_N_I<6> ADDR_N_I<5> ++ ADDR_N_I<4> ADDR_N_I<3> ADDR_N_I<2> ADDR_N_I<1> ADDR_N_I<0> CS_I ECLK_I ++ WL_O<511> WL_O<510> WL_O<509> WL_O<508> WL_O<507> WL_O<506> WL_O<505> ++ WL_O<504> WL_O<503> WL_O<502> WL_O<501> WL_O<500> WL_O<499> WL_O<498> ++ WL_O<497> WL_O<496> WL_O<495> WL_O<494> WL_O<493> WL_O<492> WL_O<491> ++ WL_O<490> WL_O<489> WL_O<488> WL_O<487> WL_O<486> WL_O<485> WL_O<484> ++ WL_O<483> WL_O<482> WL_O<481> WL_O<480> WL_O<479> WL_O<478> WL_O<477> ++ WL_O<476> WL_O<475> WL_O<474> WL_O<473> WL_O<472> WL_O<471> WL_O<470> ++ WL_O<469> WL_O<468> WL_O<467> WL_O<466> WL_O<465> WL_O<464> WL_O<463> ++ WL_O<462> WL_O<461> WL_O<460> WL_O<459> WL_O<458> WL_O<457> WL_O<456> ++ WL_O<455> WL_O<454> WL_O<453> WL_O<452> WL_O<451> WL_O<450> WL_O<449> ++ WL_O<448> WL_O<447> WL_O<446> WL_O<445> WL_O<444> WL_O<443> WL_O<442> ++ WL_O<441> WL_O<440> WL_O<439> WL_O<438> WL_O<437> WL_O<436> WL_O<435> ++ WL_O<434> WL_O<433> WL_O<432> WL_O<431> WL_O<430> WL_O<429> WL_O<428> ++ WL_O<427> WL_O<426> WL_O<425> WL_O<424> WL_O<423> WL_O<422> WL_O<421> ++ WL_O<420> WL_O<419> WL_O<418> WL_O<417> WL_O<416> WL_O<415> WL_O<414> ++ WL_O<413> WL_O<412> WL_O<411> WL_O<410> WL_O<409> WL_O<408> WL_O<407> ++ WL_O<406> WL_O<405> WL_O<404> WL_O<403> WL_O<402> WL_O<401> WL_O<400> ++ WL_O<399> WL_O<398> WL_O<397> WL_O<396> WL_O<395> WL_O<394> WL_O<393> ++ WL_O<392> WL_O<391> WL_O<390> WL_O<389> WL_O<388> WL_O<387> WL_O<386> ++ WL_O<385> WL_O<384> WL_O<383> WL_O<382> WL_O<381> WL_O<380> WL_O<379> ++ WL_O<378> WL_O<377> WL_O<376> WL_O<375> WL_O<374> WL_O<373> WL_O<372> ++ WL_O<371> WL_O<370> WL_O<369> WL_O<368> WL_O<367> WL_O<366> WL_O<365> ++ WL_O<364> WL_O<363> WL_O<362> WL_O<361> WL_O<360> WL_O<359> WL_O<358> ++ WL_O<357> WL_O<356> WL_O<355> WL_O<354> WL_O<353> WL_O<352> WL_O<351> ++ WL_O<350> WL_O<349> WL_O<348> WL_O<347> WL_O<346> WL_O<345> WL_O<344> ++ WL_O<343> WL_O<342> WL_O<341> WL_O<340> WL_O<339> WL_O<338> WL_O<337> ++ WL_O<336> WL_O<335> WL_O<334> WL_O<333> WL_O<332> WL_O<331> WL_O<330> ++ WL_O<329> WL_O<328> WL_O<327> WL_O<326> WL_O<325> WL_O<324> WL_O<323> ++ WL_O<322> WL_O<321> WL_O<320> WL_O<319> WL_O<318> WL_O<317> WL_O<316> ++ WL_O<315> WL_O<314> WL_O<313> WL_O<312> WL_O<311> WL_O<310> WL_O<309> ++ WL_O<308> WL_O<307> WL_O<306> WL_O<305> WL_O<304> WL_O<303> WL_O<302> ++ WL_O<301> WL_O<300> WL_O<299> WL_O<298> WL_O<297> WL_O<296> WL_O<295> ++ WL_O<294> WL_O<293> WL_O<292> WL_O<291> WL_O<290> WL_O<289> WL_O<288> ++ WL_O<287> WL_O<286> WL_O<285> WL_O<284> WL_O<283> WL_O<282> WL_O<281> ++ WL_O<280> WL_O<279> WL_O<278> WL_O<277> WL_O<276> WL_O<275> WL_O<274> ++ WL_O<273> WL_O<272> WL_O<271> WL_O<270> WL_O<269> WL_O<268> WL_O<267> ++ WL_O<266> WL_O<265> WL_O<264> WL_O<263> WL_O<262> WL_O<261> WL_O<260> ++ WL_O<259> WL_O<258> WL_O<257> WL_O<256> WL_O<255> WL_O<254> WL_O<253> ++ WL_O<252> WL_O<251> WL_O<250> WL_O<249> WL_O<248> WL_O<247> WL_O<246> ++ WL_O<245> WL_O<244> WL_O<243> WL_O<242> WL_O<241> WL_O<240> WL_O<239> ++ WL_O<238> WL_O<237> WL_O<236> WL_O<235> WL_O<234> WL_O<233> WL_O<232> ++ WL_O<231> WL_O<230> WL_O<229> WL_O<228> WL_O<227> WL_O<226> WL_O<225> ++ WL_O<224> WL_O<223> WL_O<222> WL_O<221> WL_O<220> WL_O<219> WL_O<218> ++ WL_O<217> WL_O<216> WL_O<215> WL_O<214> WL_O<213> WL_O<212> WL_O<211> ++ WL_O<210> WL_O<209> WL_O<208> WL_O<207> WL_O<206> WL_O<205> WL_O<204> ++ WL_O<203> WL_O<202> WL_O<201> WL_O<200> WL_O<199> WL_O<198> WL_O<197> ++ WL_O<196> WL_O<195> WL_O<194> WL_O<193> WL_O<192> WL_O<191> WL_O<190> ++ WL_O<189> WL_O<188> WL_O<187> WL_O<186> WL_O<185> WL_O<184> WL_O<183> ++ WL_O<182> WL_O<181> WL_O<180> WL_O<179> WL_O<178> WL_O<177> WL_O<176> ++ WL_O<175> WL_O<174> WL_O<173> WL_O<172> WL_O<171> WL_O<170> WL_O<169> ++ WL_O<168> WL_O<167> WL_O<166> WL_O<165> WL_O<164> WL_O<163> WL_O<162> ++ WL_O<161> WL_O<160> WL_O<159> WL_O<158> WL_O<157> WL_O<156> WL_O<155> ++ WL_O<154> WL_O<153> WL_O<152> WL_O<151> WL_O<150> WL_O<149> WL_O<148> ++ WL_O<147> WL_O<146> WL_O<145> WL_O<144> WL_O<143> WL_O<142> WL_O<141> ++ WL_O<140> WL_O<139> WL_O<138> WL_O<137> WL_O<136> WL_O<135> WL_O<134> ++ WL_O<133> WL_O<132> WL_O<131> WL_O<130> WL_O<129> WL_O<128> WL_O<127> ++ WL_O<126> WL_O<125> WL_O<124> WL_O<123> WL_O<122> WL_O<121> WL_O<120> ++ WL_O<119> WL_O<118> WL_O<117> WL_O<116> WL_O<115> WL_O<114> WL_O<113> ++ WL_O<112> WL_O<111> WL_O<110> WL_O<109> WL_O<108> WL_O<107> WL_O<106> ++ WL_O<105> WL_O<104> WL_O<103> WL_O<102> WL_O<101> WL_O<100> WL_O<99> ++ WL_O<98> WL_O<97> WL_O<96> WL_O<95> WL_O<94> WL_O<93> WL_O<92> WL_O<91> ++ WL_O<90> WL_O<89> WL_O<88> WL_O<87> WL_O<86> WL_O<85> WL_O<84> WL_O<83> ++ WL_O<82> WL_O<81> WL_O<80> WL_O<79> WL_O<78> WL_O<77> WL_O<76> WL_O<75> ++ WL_O<74> WL_O<73> WL_O<72> WL_O<71> WL_O<70> WL_O<69> WL_O<68> WL_O<67> ++ WL_O<66> WL_O<65> WL_O<64> WL_O<63> WL_O<62> WL_O<61> WL_O<60> WL_O<59> ++ WL_O<58> WL_O<57> WL_O<56> WL_O<55> WL_O<54> WL_O<53> WL_O<52> WL_O<51> ++ WL_O<50> WL_O<49> WL_O<48> WL_O<47> WL_O<46> WL_O<45> WL_O<44> WL_O<43> ++ WL_O<42> WL_O<41> WL_O<40> WL_O<39> WL_O<38> WL_O<37> WL_O<36> WL_O<35> ++ WL_O<34> WL_O<33> WL_O<32> WL_O<31> WL_O<30> WL_O<29> WL_O<28> WL_O<27> ++ WL_O<26> WL_O<25> WL_O<24> WL_O<23> WL_O<22> WL_O<21> WL_O<20> WL_O<19> ++ WL_O<18> WL_O<17> WL_O<16> WL_O<15> WL_O<14> WL_O<13> WL_O<12> WL_O<11> ++ WL_O<10> WL_O<9> WL_O<8> WL_O<7> WL_O<6> WL_O<5> WL_O<4> WL_O<3> WL_O<2> ++ WL_O<1> WL_O<0> VDD VSS +XL2<172> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<171> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<170> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<169> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<168> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<167> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<166> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<165> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<164> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<163> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<162> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<161> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<160> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<159> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<158> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<157> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<156> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<155> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<154> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<153> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<152> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<151> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<150> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<149> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<148> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<147> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<146> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<145> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<144> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<143> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<142> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<141> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<140> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<139> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<138> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<137> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<136> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<135> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<134> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<133> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<132> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<131> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<130> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<129> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<128> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<127> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<126> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<125> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<124> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<123> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<122> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<121> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<120> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<119> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<118> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<117> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<116> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<115> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<114> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<113> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<112> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<111> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<110> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<109> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<108> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<107> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<106> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<105> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<104> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<103> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<102> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<101> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<100> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<99> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<98> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<97> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<96> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<95> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<94> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<93> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<92> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<91> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<90> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<89> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<88> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<87> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<86> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<85> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<84> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<83> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<82> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<81> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<80> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<79> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<78> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<77> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<76> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<75> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<74> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<73> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<72> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<71> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<70> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<69> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<68> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<67> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<66> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<65> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<64> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<63> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<62> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<61> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<60> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<59> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<58> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<57> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<56> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<55> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<54> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<53> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<52> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<51> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<50> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<49> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<48> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<47> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<46> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<45> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<44> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<43> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<42> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<41> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<40> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<39> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<38> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<37> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<36> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<35> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<34> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<33> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<32> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<31> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<30> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<29> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<28> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<27> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<26> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<25> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<24> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<23> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<22> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<21> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<20> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<19> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<18> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<17> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<16> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<15> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<14> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<13> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<12> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<11> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<10> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<9> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<8> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<7> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<6> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<5> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<4> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<3> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<2> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<1> VDD VSS / RSC_IHPSG13_FILLCAP8 +XDEC11<9> ADDR_N_I<7> ADDR_N_I<6> CS04<1> CS02<7> VDD VSS / ++ RM_IHPSG13_512x32_c2_1P_DEC03 +XDEC11<8> ADDR_N_I<7> ADDR_N_I<6> CS04<0> CS02<3> VDD VSS / ++ RM_IHPSG13_512x32_c2_1P_DEC03 +XDEC11<7> ADDR_N_I<5> ADDR_N_I<4> CS02<7> CS00<31> VDD VSS / ++ RM_IHPSG13_512x32_c2_1P_DEC03 +XDEC11<6> ADDR_N_I<5> ADDR_N_I<4> CS02<6> CS00<27> VDD VSS / ++ RM_IHPSG13_512x32_c2_1P_DEC03 +XDEC11<5> ADDR_N_I<5> ADDR_N_I<4> CS02<5> CS00<23> VDD VSS / ++ RM_IHPSG13_512x32_c2_1P_DEC03 +XDEC11<4> ADDR_N_I<5> ADDR_N_I<4> CS02<4> CS00<19> VDD VSS / ++ RM_IHPSG13_512x32_c2_1P_DEC03 +XDEC11<3> ADDR_N_I<5> ADDR_N_I<4> CS02<3> CS00<15> VDD VSS / ++ RM_IHPSG13_512x32_c2_1P_DEC03 +XDEC11<2> ADDR_N_I<5> ADDR_N_I<4> CS02<2> CS00<11> VDD VSS / ++ RM_IHPSG13_512x32_c2_1P_DEC03 +XDEC11<1> ADDR_N_I<5> ADDR_N_I<4> CS02<1> CS00<7> VDD VSS / ++ RM_IHPSG13_512x32_c2_1P_DEC03 +XDEC11<0> ADDR_N_I<5> ADDR_N_I<4> CS02<0> CS00<3> VDD VSS / ++ RM_IHPSG13_512x32_c2_1P_DEC03 +XDEC00<10> ADDR_N_I<9> ADDR_N_I<8> CS_I CS04<0> VDD VSS / ++ RM_IHPSG13_512x32_c2_1P_DEC00 +XDEC00<9> ADDR_N_I<7> ADDR_N_I<6> CS04<1> CS02<4> VDD VSS / ++ RM_IHPSG13_512x32_c2_1P_DEC00 +XDEC00<8> ADDR_N_I<7> ADDR_N_I<6> CS04<0> CS02<0> VDD VSS / ++ RM_IHPSG13_512x32_c2_1P_DEC00 +XDEC00<7> ADDR_N_I<5> ADDR_N_I<4> CS02<7> CS00<28> VDD VSS / ++ RM_IHPSG13_512x32_c2_1P_DEC00 +XDEC00<6> ADDR_N_I<5> ADDR_N_I<4> CS02<6> CS00<24> VDD VSS / ++ RM_IHPSG13_512x32_c2_1P_DEC00 +XDEC00<5> ADDR_N_I<5> ADDR_N_I<4> CS02<5> CS00<20> VDD VSS / ++ RM_IHPSG13_512x32_c2_1P_DEC00 +XDEC00<4> ADDR_N_I<5> ADDR_N_I<4> CS02<4> CS00<16> VDD VSS / ++ RM_IHPSG13_512x32_c2_1P_DEC00 +XDEC00<3> ADDR_N_I<5> ADDR_N_I<4> CS02<3> CS00<12> VDD VSS / ++ RM_IHPSG13_512x32_c2_1P_DEC00 +XDEC00<2> ADDR_N_I<5> ADDR_N_I<4> CS02<2> CS00<8> VDD VSS / ++ RM_IHPSG13_512x32_c2_1P_DEC00 +XDEC00<1> ADDR_N_I<5> ADDR_N_I<4> CS02<1> CS00<4> VDD VSS / ++ RM_IHPSG13_512x32_c2_1P_DEC00 +XDEC00<0> ADDR_N_I<5> ADDR_N_I<4> CS02<0> CS00<0> VDD VSS / ++ RM_IHPSG13_512x32_c2_1P_DEC00 +XSEL<31> ADDR_N_I<3> ADDR_N_I<2> ADDR_N_I<1> ADDR_N_I<0> CS00<31> ECLK_H<31> ++ ECLK_H<32> ECLK_B<31> ECLK_B<32> WL_O<511> WL_O<510> WL_O<509> WL_O<508> ++ WL_O<507> WL_O<506> WL_O<505> WL_O<504> WL_O<503> WL_O<502> WL_O<501> ++ WL_O<500> WL_O<499> WL_O<498> WL_O<497> WL_O<496> VDD VSS / ++ RM_IHPSG13_512x32_c2_1P_DEC04 +XSEL<30> ADDR_N_I<3> ADDR_N_I<2> ADDR_N_I<1> ADDR_N_I<0> CS00<30> ECLK_H<30> ++ ECLK_H<31> ECLK_B<30> ECLK_B<31> WL_O<495> WL_O<494> WL_O<493> WL_O<492> ++ WL_O<491> WL_O<490> WL_O<489> WL_O<488> WL_O<487> WL_O<486> WL_O<485> ++ WL_O<484> WL_O<483> WL_O<482> WL_O<481> WL_O<480> VDD VSS / ++ RM_IHPSG13_512x32_c2_1P_DEC04 +XSEL<29> ADDR_N_I<3> ADDR_N_I<2> ADDR_N_I<1> ADDR_N_I<0> CS00<29> ECLK_H<29> ++ ECLK_H<30> ECLK_B<29> ECLK_B<30> WL_O<479> WL_O<478> WL_O<477> WL_O<476> ++ WL_O<475> WL_O<474> WL_O<473> WL_O<472> WL_O<471> WL_O<470> WL_O<469> ++ WL_O<468> WL_O<467> WL_O<466> WL_O<465> WL_O<464> VDD VSS / ++ RM_IHPSG13_512x32_c2_1P_DEC04 +XSEL<28> ADDR_N_I<3> ADDR_N_I<2> ADDR_N_I<1> ADDR_N_I<0> CS00<28> ECLK_H<28> ++ ECLK_H<29> ECLK_B<28> ECLK_B<29> WL_O<463> WL_O<462> WL_O<461> WL_O<460> ++ WL_O<459> WL_O<458> WL_O<457> WL_O<456> WL_O<455> WL_O<454> WL_O<453> ++ WL_O<452> WL_O<451> WL_O<450> WL_O<449> WL_O<448> VDD VSS / ++ RM_IHPSG13_512x32_c2_1P_DEC04 +XSEL<27> ADDR_N_I<3> ADDR_N_I<2> ADDR_N_I<1> ADDR_N_I<0> CS00<27> ECLK_H<27> ++ ECLK_H<28> ECLK_B<27> ECLK_B<28> WL_O<447> WL_O<446> WL_O<445> WL_O<444> ++ WL_O<443> WL_O<442> WL_O<441> WL_O<440> WL_O<439> WL_O<438> WL_O<437> ++ WL_O<436> WL_O<435> WL_O<434> WL_O<433> WL_O<432> VDD VSS / ++ RM_IHPSG13_512x32_c2_1P_DEC04 +XSEL<26> ADDR_N_I<3> ADDR_N_I<2> ADDR_N_I<1> ADDR_N_I<0> CS00<26> ECLK_H<26> ++ ECLK_H<27> ECLK_B<26> ECLK_B<27> WL_O<431> WL_O<430> WL_O<429> WL_O<428> ++ WL_O<427> WL_O<426> WL_O<425> WL_O<424> WL_O<423> WL_O<422> WL_O<421> ++ WL_O<420> WL_O<419> WL_O<418> WL_O<417> WL_O<416> VDD VSS / ++ RM_IHPSG13_512x32_c2_1P_DEC04 +XSEL<25> ADDR_N_I<3> ADDR_N_I<2> ADDR_N_I<1> ADDR_N_I<0> CS00<25> ECLK_H<25> ++ ECLK_H<26> ECLK_B<25> ECLK_B<26> WL_O<415> WL_O<414> WL_O<413> WL_O<412> ++ WL_O<411> WL_O<410> WL_O<409> WL_O<408> WL_O<407> WL_O<406> WL_O<405> ++ WL_O<404> WL_O<403> WL_O<402> WL_O<401> WL_O<400> VDD VSS / ++ RM_IHPSG13_512x32_c2_1P_DEC04 +XSEL<24> ADDR_N_I<3> ADDR_N_I<2> ADDR_N_I<1> ADDR_N_I<0> CS00<24> ECLK_H<24> ++ ECLK_H<25> ECLK_B<24> ECLK_B<25> WL_O<399> WL_O<398> WL_O<397> WL_O<396> ++ WL_O<395> WL_O<394> WL_O<393> WL_O<392> WL_O<391> WL_O<390> WL_O<389> ++ WL_O<388> WL_O<387> WL_O<386> WL_O<385> WL_O<384> VDD VSS / ++ RM_IHPSG13_512x32_c2_1P_DEC04 +XSEL<23> ADDR_N_I<3> ADDR_N_I<2> ADDR_N_I<1> ADDR_N_I<0> CS00<23> ECLK_H<23> ++ ECLK_H<24> ECLK_B<23> ECLK_B<24> WL_O<383> WL_O<382> WL_O<381> WL_O<380> ++ WL_O<379> WL_O<378> WL_O<377> WL_O<376> WL_O<375> WL_O<374> WL_O<373> ++ WL_O<372> WL_O<371> WL_O<370> WL_O<369> WL_O<368> VDD VSS / ++ RM_IHPSG13_512x32_c2_1P_DEC04 +XSEL<22> ADDR_N_I<3> ADDR_N_I<2> ADDR_N_I<1> ADDR_N_I<0> CS00<22> ECLK_H<22> ++ ECLK_H<23> ECLK_B<22> ECLK_B<23> WL_O<367> WL_O<366> WL_O<365> WL_O<364> ++ WL_O<363> WL_O<362> WL_O<361> WL_O<360> WL_O<359> WL_O<358> WL_O<357> ++ WL_O<356> WL_O<355> WL_O<354> WL_O<353> WL_O<352> VDD VSS / ++ RM_IHPSG13_512x32_c2_1P_DEC04 +XSEL<21> ADDR_N_I<3> ADDR_N_I<2> ADDR_N_I<1> ADDR_N_I<0> CS00<21> ECLK_H<21> ++ ECLK_H<22> ECLK_B<21> ECLK_B<22> WL_O<351> WL_O<350> WL_O<349> WL_O<348> ++ WL_O<347> WL_O<346> WL_O<345> WL_O<344> WL_O<343> WL_O<342> WL_O<341> ++ WL_O<340> WL_O<339> WL_O<338> WL_O<337> WL_O<336> VDD VSS / ++ RM_IHPSG13_512x32_c2_1P_DEC04 +XSEL<20> ADDR_N_I<3> ADDR_N_I<2> ADDR_N_I<1> ADDR_N_I<0> CS00<20> ECLK_H<20> ++ ECLK_H<21> ECLK_B<20> ECLK_B<21> WL_O<335> WL_O<334> WL_O<333> WL_O<332> ++ WL_O<331> WL_O<330> WL_O<329> WL_O<328> WL_O<327> WL_O<326> WL_O<325> ++ WL_O<324> WL_O<323> WL_O<322> WL_O<321> WL_O<320> VDD VSS / ++ RM_IHPSG13_512x32_c2_1P_DEC04 +XSEL<19> ADDR_N_I<3> ADDR_N_I<2> ADDR_N_I<1> ADDR_N_I<0> CS00<19> ECLK_H<19> ++ ECLK_H<20> ECLK_B<19> ECLK_B<20> WL_O<319> WL_O<318> WL_O<317> WL_O<316> ++ WL_O<315> WL_O<314> WL_O<313> WL_O<312> WL_O<311> WL_O<310> WL_O<309> ++ WL_O<308> WL_O<307> WL_O<306> WL_O<305> WL_O<304> VDD VSS / ++ RM_IHPSG13_512x32_c2_1P_DEC04 +XSEL<18> ADDR_N_I<3> ADDR_N_I<2> ADDR_N_I<1> ADDR_N_I<0> CS00<18> ECLK_H<18> ++ ECLK_H<19> ECLK_B<18> ECLK_B<19> WL_O<303> WL_O<302> WL_O<301> WL_O<300> ++ WL_O<299> WL_O<298> WL_O<297> WL_O<296> WL_O<295> WL_O<294> WL_O<293> ++ WL_O<292> WL_O<291> WL_O<290> WL_O<289> WL_O<288> VDD VSS / ++ RM_IHPSG13_512x32_c2_1P_DEC04 +XSEL<17> ADDR_N_I<3> ADDR_N_I<2> ADDR_N_I<1> ADDR_N_I<0> CS00<17> ECLK_H<17> ++ ECLK_H<18> ECLK_B<17> ECLK_B<18> WL_O<287> WL_O<286> WL_O<285> WL_O<284> ++ WL_O<283> WL_O<282> WL_O<281> WL_O<280> WL_O<279> WL_O<278> WL_O<277> ++ WL_O<276> WL_O<275> WL_O<274> WL_O<273> WL_O<272> VDD VSS / ++ RM_IHPSG13_512x32_c2_1P_DEC04 +XSEL<16> ADDR_N_I<3> ADDR_N_I<2> ADDR_N_I<1> ADDR_N_I<0> CS00<16> ECLK_H<16> ++ ECLK_H<17> ECLK_B<16> ECLK_B<17> WL_O<271> WL_O<270> WL_O<269> WL_O<268> ++ WL_O<267> WL_O<266> WL_O<265> WL_O<264> WL_O<263> WL_O<262> WL_O<261> ++ WL_O<260> WL_O<259> WL_O<258> WL_O<257> WL_O<256> VDD VSS / ++ RM_IHPSG13_512x32_c2_1P_DEC04 +XSEL<15> ADDR_N_I<3> ADDR_N_I<2> ADDR_N_I<1> ADDR_N_I<0> CS00<15> ECLK_H<15> ++ ECLK_H<16> ECLK_B<15> ECLK_B<16> WL_O<255> WL_O<254> WL_O<253> WL_O<252> ++ WL_O<251> WL_O<250> WL_O<249> WL_O<248> WL_O<247> WL_O<246> WL_O<245> ++ WL_O<244> WL_O<243> WL_O<242> WL_O<241> WL_O<240> VDD VSS / ++ RM_IHPSG13_512x32_c2_1P_DEC04 +XSEL<14> ADDR_N_I<3> ADDR_N_I<2> ADDR_N_I<1> ADDR_N_I<0> CS00<14> ECLK_H<14> ++ ECLK_H<15> ECLK_B<14> ECLK_B<15> WL_O<239> WL_O<238> WL_O<237> WL_O<236> ++ WL_O<235> WL_O<234> WL_O<233> WL_O<232> WL_O<231> WL_O<230> WL_O<229> ++ WL_O<228> WL_O<227> WL_O<226> WL_O<225> WL_O<224> VDD VSS / ++ RM_IHPSG13_512x32_c2_1P_DEC04 +XSEL<13> ADDR_N_I<3> ADDR_N_I<2> ADDR_N_I<1> ADDR_N_I<0> CS00<13> ECLK_H<13> ++ ECLK_H<14> ECLK_B<13> ECLK_B<14> WL_O<223> WL_O<222> WL_O<221> WL_O<220> ++ WL_O<219> WL_O<218> WL_O<217> WL_O<216> WL_O<215> WL_O<214> WL_O<213> ++ WL_O<212> WL_O<211> WL_O<210> WL_O<209> WL_O<208> VDD VSS / ++ RM_IHPSG13_512x32_c2_1P_DEC04 +XSEL<12> ADDR_N_I<3> ADDR_N_I<2> ADDR_N_I<1> ADDR_N_I<0> CS00<12> ECLK_H<12> ++ ECLK_H<13> ECLK_B<12> ECLK_B<13> WL_O<207> WL_O<206> WL_O<205> WL_O<204> ++ WL_O<203> WL_O<202> WL_O<201> WL_O<200> WL_O<199> WL_O<198> WL_O<197> ++ WL_O<196> WL_O<195> WL_O<194> WL_O<193> WL_O<192> VDD VSS / ++ RM_IHPSG13_512x32_c2_1P_DEC04 +XSEL<11> ADDR_N_I<3> ADDR_N_I<2> ADDR_N_I<1> ADDR_N_I<0> CS00<11> ECLK_H<11> ++ ECLK_H<12> ECLK_B<11> ECLK_B<12> WL_O<191> WL_O<190> WL_O<189> WL_O<188> ++ WL_O<187> WL_O<186> WL_O<185> WL_O<184> WL_O<183> WL_O<182> WL_O<181> ++ WL_O<180> WL_O<179> WL_O<178> WL_O<177> WL_O<176> VDD VSS / ++ RM_IHPSG13_512x32_c2_1P_DEC04 +XSEL<10> ADDR_N_I<3> ADDR_N_I<2> ADDR_N_I<1> ADDR_N_I<0> CS00<10> ECLK_H<10> ++ ECLK_H<11> ECLK_B<10> ECLK_B<11> WL_O<175> WL_O<174> WL_O<173> WL_O<172> ++ WL_O<171> WL_O<170> WL_O<169> WL_O<168> WL_O<167> WL_O<166> WL_O<165> ++ WL_O<164> WL_O<163> WL_O<162> WL_O<161> WL_O<160> VDD VSS / ++ RM_IHPSG13_512x32_c2_1P_DEC04 +XSEL<9> ADDR_N_I<3> ADDR_N_I<2> ADDR_N_I<1> ADDR_N_I<0> CS00<9> ECLK_H<9> ++ ECLK_H<10> ECLK_B<9> ECLK_B<10> WL_O<159> WL_O<158> WL_O<157> WL_O<156> ++ WL_O<155> WL_O<154> WL_O<153> WL_O<152> WL_O<151> WL_O<150> WL_O<149> ++ WL_O<148> WL_O<147> WL_O<146> WL_O<145> WL_O<144> VDD VSS / ++ RM_IHPSG13_512x32_c2_1P_DEC04 +XSEL<8> ADDR_N_I<3> ADDR_N_I<2> ADDR_N_I<1> ADDR_N_I<0> CS00<8> ECLK_H<8> ++ ECLK_H<9> ECLK_B<8> ECLK_B<9> WL_O<143> WL_O<142> WL_O<141> WL_O<140> ++ WL_O<139> WL_O<138> WL_O<137> WL_O<136> WL_O<135> WL_O<134> WL_O<133> ++ WL_O<132> WL_O<131> WL_O<130> WL_O<129> WL_O<128> VDD VSS / ++ RM_IHPSG13_512x32_c2_1P_DEC04 +XSEL<7> ADDR_N_I<3> ADDR_N_I<2> ADDR_N_I<1> ADDR_N_I<0> CS00<7> ECLK_H<7> ++ ECLK_H<8> ECLK_B<7> ECLK_B<8> WL_O<127> WL_O<126> WL_O<125> WL_O<124> ++ WL_O<123> WL_O<122> WL_O<121> WL_O<120> WL_O<119> WL_O<118> WL_O<117> ++ WL_O<116> WL_O<115> WL_O<114> WL_O<113> WL_O<112> VDD VSS / ++ RM_IHPSG13_512x32_c2_1P_DEC04 +XSEL<6> ADDR_N_I<3> ADDR_N_I<2> ADDR_N_I<1> ADDR_N_I<0> CS00<6> ECLK_H<6> ++ ECLK_H<7> ECLK_B<6> ECLK_B<7> WL_O<111> WL_O<110> WL_O<109> WL_O<108> ++ WL_O<107> WL_O<106> WL_O<105> WL_O<104> WL_O<103> WL_O<102> WL_O<101> ++ WL_O<100> WL_O<99> WL_O<98> WL_O<97> WL_O<96> VDD VSS / ++ RM_IHPSG13_512x32_c2_1P_DEC04 +XSEL<5> ADDR_N_I<3> ADDR_N_I<2> ADDR_N_I<1> ADDR_N_I<0> CS00<5> ECLK_H<5> ++ ECLK_H<6> ECLK_B<5> ECLK_B<6> WL_O<95> WL_O<94> WL_O<93> WL_O<92> WL_O<91> ++ WL_O<90> WL_O<89> WL_O<88> WL_O<87> WL_O<86> WL_O<85> WL_O<84> WL_O<83> ++ WL_O<82> WL_O<81> WL_O<80> VDD VSS / RM_IHPSG13_512x32_c2_1P_DEC04 +XSEL<4> ADDR_N_I<3> ADDR_N_I<2> ADDR_N_I<1> ADDR_N_I<0> CS00<4> ECLK_H<4> ++ ECLK_H<5> ECLK_B<4> ECLK_B<5> WL_O<79> WL_O<78> WL_O<77> WL_O<76> WL_O<75> ++ WL_O<74> WL_O<73> WL_O<72> WL_O<71> WL_O<70> WL_O<69> WL_O<68> WL_O<67> ++ WL_O<66> WL_O<65> WL_O<64> VDD VSS / RM_IHPSG13_512x32_c2_1P_DEC04 +XSEL<3> ADDR_N_I<3> ADDR_N_I<2> ADDR_N_I<1> ADDR_N_I<0> CS00<3> ECLK_H<3> ++ ECLK_H<4> ECLK_B<3> ECLK_B<4> WL_O<63> WL_O<62> WL_O<61> WL_O<60> WL_O<59> ++ WL_O<58> WL_O<57> WL_O<56> WL_O<55> WL_O<54> WL_O<53> WL_O<52> WL_O<51> ++ WL_O<50> WL_O<49> WL_O<48> VDD VSS / RM_IHPSG13_512x32_c2_1P_DEC04 +XSEL<2> ADDR_N_I<3> ADDR_N_I<2> ADDR_N_I<1> ADDR_N_I<0> CS00<2> ECLK_H<2> ++ ECLK_H<3> ECLK_B<2> ECLK_B<3> WL_O<47> WL_O<46> WL_O<45> WL_O<44> WL_O<43> ++ WL_O<42> WL_O<41> WL_O<40> WL_O<39> WL_O<38> WL_O<37> WL_O<36> WL_O<35> ++ WL_O<34> WL_O<33> WL_O<32> VDD VSS / RM_IHPSG13_512x32_c2_1P_DEC04 +XSEL<1> ADDR_N_I<3> ADDR_N_I<2> ADDR_N_I<1> ADDR_N_I<0> CS00<1> ECLK_H<1> ++ ECLK_H<2> ECLK_B<1> ECLK_B<2> WL_O<31> WL_O<30> WL_O<29> WL_O<28> WL_O<27> ++ WL_O<26> WL_O<25> WL_O<24> WL_O<23> WL_O<22> WL_O<21> WL_O<20> WL_O<19> ++ WL_O<18> WL_O<17> WL_O<16> VDD VSS / RM_IHPSG13_512x32_c2_1P_DEC04 +XSEL<0> ADDR_N_I<3> ADDR_N_I<2> ADDR_N_I<1> ADDR_N_I<0> CS00<0> ECLK_I ++ ECLK_H<1> ECLK_B<0> ECLK_B<1> WL_O<15> WL_O<14> WL_O<13> WL_O<12> WL_O<11> ++ WL_O<10> WL_O<9> WL_O<8> WL_O<7> WL_O<6> WL_O<5> WL_O<4> WL_O<3> WL_O<2> ++ WL_O<1> WL_O<0> VDD VSS / RM_IHPSG13_512x32_c2_1P_DEC04 +XDEC01<10> ADDR_N_I<9> ADDR_N_I<8> CS_I CS04<1> VDD VSS / ++ RM_IHPSG13_512x32_c2_1P_DEC01 +XDEC01<9> ADDR_N_I<7> ADDR_N_I<6> CS04<1> CS02<5> VDD VSS / ++ RM_IHPSG13_512x32_c2_1P_DEC01 +XDEC01<8> ADDR_N_I<7> ADDR_N_I<6> CS04<0> CS02<1> VDD VSS / ++ RM_IHPSG13_512x32_c2_1P_DEC01 +XDEC01<7> ADDR_N_I<5> ADDR_N_I<4> CS02<7> CS00<29> VDD VSS / ++ RM_IHPSG13_512x32_c2_1P_DEC01 +XDEC01<6> ADDR_N_I<5> ADDR_N_I<4> CS02<6> CS00<25> VDD VSS / ++ RM_IHPSG13_512x32_c2_1P_DEC01 +XDEC01<5> ADDR_N_I<5> ADDR_N_I<4> CS02<5> CS00<21> VDD VSS / ++ RM_IHPSG13_512x32_c2_1P_DEC01 +XDEC01<4> ADDR_N_I<5> ADDR_N_I<4> CS02<4> CS00<17> VDD VSS / ++ RM_IHPSG13_512x32_c2_1P_DEC01 +XDEC01<3> ADDR_N_I<5> ADDR_N_I<4> CS02<3> CS00<13> VDD VSS / ++ RM_IHPSG13_512x32_c2_1P_DEC01 +XDEC01<2> ADDR_N_I<5> ADDR_N_I<4> CS02<2> CS00<9> VDD VSS / ++ RM_IHPSG13_512x32_c2_1P_DEC01 +XDEC01<1> ADDR_N_I<5> ADDR_N_I<4> CS02<1> CS00<5> VDD VSS / ++ RM_IHPSG13_512x32_c2_1P_DEC01 +XDEC01<0> ADDR_N_I<5> ADDR_N_I<4> CS02<0> CS00<1> VDD VSS / ++ RM_IHPSG13_512x32_c2_1P_DEC01 +XDEC10<9> ADDR_N_I<7> ADDR_N_I<6> CS04<1> CS02<6> VDD VSS / ++ RM_IHPSG13_512x32_c2_1P_DEC02 +XDEC10<8> ADDR_N_I<7> ADDR_N_I<6> CS04<0> CS02<2> VDD VSS / ++ RM_IHPSG13_512x32_c2_1P_DEC02 +XDEC10<7> ADDR_N_I<5> ADDR_N_I<4> CS02<7> CS00<30> VDD VSS / ++ RM_IHPSG13_512x32_c2_1P_DEC02 +XDEC10<6> ADDR_N_I<5> ADDR_N_I<4> CS02<6> CS00<26> VDD VSS / ++ RM_IHPSG13_512x32_c2_1P_DEC02 +XDEC10<5> ADDR_N_I<5> ADDR_N_I<4> CS02<5> CS00<22> VDD VSS / ++ RM_IHPSG13_512x32_c2_1P_DEC02 +XDEC10<4> ADDR_N_I<5> ADDR_N_I<4> CS02<4> CS00<18> VDD VSS / ++ RM_IHPSG13_512x32_c2_1P_DEC02 +XDEC10<3> ADDR_N_I<5> ADDR_N_I<4> CS02<3> CS00<14> VDD VSS / ++ RM_IHPSG13_512x32_c2_1P_DEC02 +XDEC10<2> ADDR_N_I<5> ADDR_N_I<4> CS02<2> CS00<10> VDD VSS / ++ RM_IHPSG13_512x32_c2_1P_DEC02 +XDEC10<1> ADDR_N_I<5> ADDR_N_I<4> CS02<1> CS00<6> VDD VSS / ++ RM_IHPSG13_512x32_c2_1P_DEC02 +XDEC10<0> ADDR_N_I<5> ADDR_N_I<4> CS02<0> CS00<2> VDD VSS / ++ RM_IHPSG13_512x32_c2_1P_DEC02 +XI0 ADDR_N_I<9> VDD VSS / RSC_IHPSG13_TIEL +.ENDS +.SUBCKT RM_IHPSG13_512x32_c2_1P_ROWREG9 ACLK_N_I ADDR_I<8> ADDR_I<7> ADDR_I<6> ADDR_I<5> ++ ADDR_I<4> ADDR_I<3> ADDR_I<2> ADDR_I<1> ADDR_I<0> ADDR_N_O<8> ADDR_N_O<7> ++ ADDR_N_O<6> ADDR_N_O<5> ADDR_N_O<4> ADDR_N_O<3> ADDR_N_O<2> ADDR_N_O<1> ++ ADDR_N_O<0> BIST_ADDR_I<8> BIST_ADDR_I<7> BIST_ADDR_I<6> BIST_ADDR_I<5> ++ BIST_ADDR_I<4> BIST_ADDR_I<3> BIST_ADDR_I<2> BIST_ADDR_I<1> BIST_ADDR_I<0> ++ BIST_EN_I VDD VSS +XINV<8> q_int<8> qn_int<8> VDD VSS / RSC_IHPSG13_CINVX2 +XINV<7> q_int<7> qn_int<7> VDD VSS / RSC_IHPSG13_CINVX2 +XINV<6> q_int<6> qn_int<6> VDD VSS / RSC_IHPSG13_CINVX2 +XINV<5> q_int<5> qn_int<5> VDD VSS / RSC_IHPSG13_CINVX2 +XINV<4> q_int<4> qn_int<4> VDD VSS / RSC_IHPSG13_CINVX2 +XINV<3> q_int<3> qn_int<3> VDD VSS / RSC_IHPSG13_CINVX2 +XINV<2> q_int<2> qn_int<2> VDD VSS / RSC_IHPSG13_CINVX2 +XINV<1> q_int<1> qn_int<1> VDD VSS / RSC_IHPSG13_CINVX2 +XINV<0> q_int<0> qn_int<0> VDD VSS / RSC_IHPSG13_CINVX2 +XDRV<8> qn_int<8> ADDR_N_O<8> VDD VSS / RSC_IHPSG13_CINVX8 +XDRV<7> qn_int<7> ADDR_N_O<7> VDD VSS / RSC_IHPSG13_CINVX8 +XDRV<6> qn_int<6> ADDR_N_O<6> VDD VSS / RSC_IHPSG13_CINVX8 +XDRV<5> qn_int<5> ADDR_N_O<5> VDD VSS / RSC_IHPSG13_CINVX8 +XDRV<4> qn_int<4> ADDR_N_O<4> VDD VSS / RSC_IHPSG13_CINVX8 +XDRV<3> qn_int<3> ADDR_N_O<3> VDD VSS / RSC_IHPSG13_CINVX8 +XDRV<2> qn_int<2> ADDR_N_O<2> VDD VSS / RSC_IHPSG13_CINVX8 +XDRV<1> qn_int<1> ADDR_N_O<1> VDD VSS / RSC_IHPSG13_CINVX8 +XDRV<0> qn_int<0> ADDR_N_O<0> VDD VSS / RSC_IHPSG13_CINVX8 +XDFF<8> BIST_EN_I BIST_ADDR_I<8> ACLK_N_I ADDR_I<8> q_int<8> net04<0> VDD ++ VSS / RSC_IHPSG13_DFNQMX2IX1 +XDFF<7> BIST_EN_I BIST_ADDR_I<7> ACLK_N_I ADDR_I<7> q_int<7> net04<1> VDD ++ VSS / RSC_IHPSG13_DFNQMX2IX1 +XDFF<6> BIST_EN_I BIST_ADDR_I<6> ACLK_N_I ADDR_I<6> q_int<6> net04<2> VDD ++ VSS / RSC_IHPSG13_DFNQMX2IX1 +XDFF<5> BIST_EN_I BIST_ADDR_I<5> ACLK_N_I ADDR_I<5> q_int<5> net04<3> VDD ++ VSS / RSC_IHPSG13_DFNQMX2IX1 +XDFF<4> BIST_EN_I BIST_ADDR_I<4> ACLK_N_I ADDR_I<4> q_int<4> net04<4> VDD ++ VSS / RSC_IHPSG13_DFNQMX2IX1 +XDFF<3> BIST_EN_I BIST_ADDR_I<3> ACLK_N_I ADDR_I<3> q_int<3> net04<5> VDD ++ VSS / RSC_IHPSG13_DFNQMX2IX1 +XDFF<2> BIST_EN_I BIST_ADDR_I<2> ACLK_N_I ADDR_I<2> q_int<2> net04<6> VDD ++ VSS / RSC_IHPSG13_DFNQMX2IX1 +XDFF<1> BIST_EN_I BIST_ADDR_I<1> ACLK_N_I ADDR_I<1> q_int<1> net04<7> VDD ++ VSS / RSC_IHPSG13_DFNQMX2IX1 +XDFF<0> BIST_EN_I BIST_ADDR_I<0> ACLK_N_I ADDR_I<0> q_int<0> net04<8> VDD ++ VSS / RSC_IHPSG13_DFNQMX2IX1 +.ENDS + +.SUBCKT RM_IHPSG13_512x32_c2_1P_ROWDEC7 ADDR_N_I<6> ADDR_N_I<5> ADDR_N_I<4> ADDR_N_I<3> ++ ADDR_N_I<2> ADDR_N_I<1> ADDR_N_I<0> CS_I ECLK_I WL_O<127> WL_O<126> ++ WL_O<125> WL_O<124> WL_O<123> WL_O<122> WL_O<121> WL_O<120> WL_O<119> ++ WL_O<118> WL_O<117> WL_O<116> WL_O<115> WL_O<114> WL_O<113> WL_O<112> ++ WL_O<111> WL_O<110> WL_O<109> WL_O<108> WL_O<107> WL_O<106> WL_O<105> ++ WL_O<104> WL_O<103> WL_O<102> WL_O<101> WL_O<100> WL_O<99> WL_O<98> WL_O<97> ++ WL_O<96> WL_O<95> WL_O<94> WL_O<93> WL_O<92> WL_O<91> WL_O<90> WL_O<89> ++ WL_O<88> WL_O<87> WL_O<86> WL_O<85> WL_O<84> WL_O<83> WL_O<82> WL_O<81> ++ WL_O<80> WL_O<79> WL_O<78> WL_O<77> WL_O<76> WL_O<75> WL_O<74> WL_O<73> ++ WL_O<72> WL_O<71> WL_O<70> WL_O<69> WL_O<68> WL_O<67> WL_O<66> WL_O<65> ++ WL_O<64> WL_O<63> WL_O<62> WL_O<61> WL_O<60> WL_O<59> WL_O<58> WL_O<57> ++ WL_O<56> WL_O<55> WL_O<54> WL_O<53> WL_O<52> WL_O<51> WL_O<50> WL_O<49> ++ WL_O<48> WL_O<47> WL_O<46> WL_O<45> WL_O<44> WL_O<43> WL_O<42> WL_O<41> ++ WL_O<40> WL_O<39> WL_O<38> WL_O<37> WL_O<36> WL_O<35> WL_O<34> WL_O<33> ++ WL_O<32> WL_O<31> WL_O<30> WL_O<29> WL_O<28> WL_O<27> WL_O<26> WL_O<25> ++ WL_O<24> WL_O<23> WL_O<22> WL_O<21> WL_O<20> WL_O<19> WL_O<18> WL_O<17> ++ WL_O<16> WL_O<15> WL_O<14> WL_O<13> WL_O<12> WL_O<11> WL_O<10> WL_O<9> ++ WL_O<8> WL_O<7> WL_O<6> WL_O<5> WL_O<4> WL_O<3> WL_O<2> WL_O<1> WL_O<0> ++ VDD VSS +XDEC11<1> ADDR_N_I<5> ADDR_N_I<4> CS04<1> CS00<7> VDD VSS / ++ RM_IHPSG13_512x32_c2_1P_DEC03 +XDEC11<0> ADDR_N_I<5> ADDR_N_I<4> CS04<0> CS00<3> VDD VSS / ++ RM_IHPSG13_512x32_c2_1P_DEC03 +XDEC10<1> ADDR_N_I<5> ADDR_N_I<4> CS04<1> CS00<6> VDD VSS / ++ RM_IHPSG13_512x32_c2_1P_DEC02 +XDEC10<0> ADDR_N_I<5> ADDR_N_I<4> CS04<0> CS00<2> VDD VSS / ++ RM_IHPSG13_512x32_c2_1P_DEC02 +XSEL<7> ADDR_N_I<3> ADDR_N_I<2> ADDR_N_I<1> ADDR_N_I<0> CS00<7> ECLK_H<7> ++ ECLK_H<8> ECLK_B<7> ECLK_B<8> WL_O<127> WL_O<126> WL_O<125> WL_O<124> ++ WL_O<123> WL_O<122> WL_O<121> WL_O<120> WL_O<119> WL_O<118> WL_O<117> ++ WL_O<116> WL_O<115> WL_O<114> WL_O<113> WL_O<112> VDD VSS / ++ RM_IHPSG13_512x32_c2_1P_DEC04 +XSEL<6> ADDR_N_I<3> ADDR_N_I<2> ADDR_N_I<1> ADDR_N_I<0> CS00<6> ECLK_H<6> ++ ECLK_H<7> ECLK_B<6> ECLK_B<7> WL_O<111> WL_O<110> WL_O<109> WL_O<108> ++ WL_O<107> WL_O<106> WL_O<105> WL_O<104> WL_O<103> WL_O<102> WL_O<101> ++ WL_O<100> WL_O<99> WL_O<98> WL_O<97> WL_O<96> VDD VSS / ++ RM_IHPSG13_512x32_c2_1P_DEC04 +XSEL<5> ADDR_N_I<3> ADDR_N_I<2> ADDR_N_I<1> ADDR_N_I<0> CS00<5> ECLK_H<5> ++ ECLK_H<6> ECLK_B<5> ECLK_B<6> WL_O<95> WL_O<94> WL_O<93> WL_O<92> WL_O<91> ++ WL_O<90> WL_O<89> WL_O<88> WL_O<87> WL_O<86> WL_O<85> WL_O<84> WL_O<83> ++ WL_O<82> WL_O<81> WL_O<80> VDD VSS / RM_IHPSG13_512x32_c2_1P_DEC04 +XSEL<4> ADDR_N_I<3> ADDR_N_I<2> ADDR_N_I<1> ADDR_N_I<0> CS00<4> ECLK_H<4> ++ ECLK_H<5> ECLK_B<4> ECLK_B<5> WL_O<79> WL_O<78> WL_O<77> WL_O<76> WL_O<75> ++ WL_O<74> WL_O<73> WL_O<72> WL_O<71> WL_O<70> WL_O<69> WL_O<68> WL_O<67> ++ WL_O<66> WL_O<65> WL_O<64> VDD VSS / RM_IHPSG13_512x32_c2_1P_DEC04 +XSEL<3> ADDR_N_I<3> ADDR_N_I<2> ADDR_N_I<1> ADDR_N_I<0> CS00<3> ECLK_H<3> ++ ECLK_H<4> ECLK_B<3> ECLK_B<4> WL_O<63> WL_O<62> WL_O<61> WL_O<60> WL_O<59> ++ WL_O<58> WL_O<57> WL_O<56> WL_O<55> WL_O<54> WL_O<53> WL_O<52> WL_O<51> ++ WL_O<50> WL_O<49> WL_O<48> VDD VSS / RM_IHPSG13_512x32_c2_1P_DEC04 +XSEL<2> ADDR_N_I<3> ADDR_N_I<2> ADDR_N_I<1> ADDR_N_I<0> CS00<2> ECLK_H<2> ++ ECLK_H<3> ECLK_B<2> ECLK_B<3> WL_O<47> WL_O<46> WL_O<45> WL_O<44> WL_O<43> ++ WL_O<42> WL_O<41> WL_O<40> WL_O<39> WL_O<38> WL_O<37> WL_O<36> WL_O<35> ++ WL_O<34> WL_O<33> WL_O<32> VDD VSS / RM_IHPSG13_512x32_c2_1P_DEC04 +XSEL<1> ADDR_N_I<3> ADDR_N_I<2> ADDR_N_I<1> ADDR_N_I<0> CS00<1> ECLK_H<1> ++ ECLK_H<2> ECLK_B<1> ECLK_B<2> WL_O<31> WL_O<30> WL_O<29> WL_O<28> WL_O<27> ++ WL_O<26> WL_O<25> WL_O<24> WL_O<23> WL_O<22> WL_O<21> WL_O<20> WL_O<19> ++ WL_O<18> WL_O<17> WL_O<16> VDD VSS / RM_IHPSG13_512x32_c2_1P_DEC04 +XSEL<0> ADDR_N_I<3> ADDR_N_I<2> ADDR_N_I<1> ADDR_N_I<0> CS00<0> ECLK_I ++ ECLK_H<1> ECLK_B<0> ECLK_B<1> WL_O<15> WL_O<14> WL_O<13> WL_O<12> WL_O<11> ++ WL_O<10> WL_O<9> WL_O<8> WL_O<7> WL_O<6> WL_O<5> WL_O<4> WL_O<3> WL_O<2> ++ WL_O<1> WL_O<0> VDD VSS / RM_IHPSG13_512x32_c2_1P_DEC04 +XDEC00<2> ADDR_N_I<7> ADDR_N_I<6> CS_I CS04<0> VDD VSS / ++ RM_IHPSG13_512x32_c2_1P_DEC00 +XDEC00<1> ADDR_N_I<5> ADDR_N_I<4> CS04<1> CS00<4> VDD VSS / ++ RM_IHPSG13_512x32_c2_1P_DEC00 +XDEC00<0> ADDR_N_I<5> ADDR_N_I<4> CS04<0> CS00<0> VDD VSS / ++ RM_IHPSG13_512x32_c2_1P_DEC00 +XDEC01<2> ADDR_N_I<7> ADDR_N_I<6> CS_I CS04<1> VDD VSS / ++ RM_IHPSG13_512x32_c2_1P_DEC01 +XDEC01<1> ADDR_N_I<5> ADDR_N_I<4> CS04<1> CS00<5> VDD VSS / ++ RM_IHPSG13_512x32_c2_1P_DEC01 +XDEC01<0> ADDR_N_I<5> ADDR_N_I<4> CS04<0> CS00<1> VDD VSS / ++ RM_IHPSG13_512x32_c2_1P_DEC01 +XL2<44> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<43> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<42> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<41> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<40> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<39> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<38> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<37> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<36> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<35> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<34> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<33> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<32> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<31> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<30> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<29> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<28> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<27> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<26> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<25> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<24> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<23> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<22> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<21> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<20> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<19> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<18> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<17> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<16> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<15> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<14> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<13> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<12> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<11> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<10> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<9> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<8> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<7> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<6> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<5> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<4> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<3> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<2> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<1> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI0 ADDR_N_I<7> VDD VSS / RSC_IHPSG13_TIEL +.ENDS +.SUBCKT RM_IHPSG13_512x32_c2_1P_ROWREG7 ACLK_N_I ADDR_I<6> ADDR_I<5> ADDR_I<4> ADDR_I<3> ++ ADDR_I<2> ADDR_I<1> ADDR_I<0> ADDR_N_O<6> ADDR_N_O<5> ADDR_N_O<4> ++ ADDR_N_O<3> ADDR_N_O<2> ADDR_N_O<1> ADDR_N_O<0> BIST_ADDR_I<6> ++ BIST_ADDR_I<5> BIST_ADDR_I<4> BIST_ADDR_I<3> BIST_ADDR_I<2> BIST_ADDR_I<1> ++ BIST_ADDR_I<0> BIST_EN_I VDD VSS +XINV<6> q_int<6> qn_int<6> VDD VSS / RSC_IHPSG13_CINVX2 +XINV<5> q_int<5> qn_int<5> VDD VSS / RSC_IHPSG13_CINVX2 +XINV<4> q_int<4> qn_int<4> VDD VSS / RSC_IHPSG13_CINVX2 +XINV<3> q_int<3> qn_int<3> VDD VSS / RSC_IHPSG13_CINVX2 +XINV<2> q_int<2> qn_int<2> VDD VSS / RSC_IHPSG13_CINVX2 +XINV<1> q_int<1> qn_int<1> VDD VSS / RSC_IHPSG13_CINVX2 +XINV<0> q_int<0> qn_int<0> VDD VSS / RSC_IHPSG13_CINVX2 +XDRV<6> qn_int<6> ADDR_N_O<6> VDD VSS / RSC_IHPSG13_CINVX8 +XDRV<5> qn_int<5> ADDR_N_O<5> VDD VSS / RSC_IHPSG13_CINVX8 +XDRV<4> qn_int<4> ADDR_N_O<4> VDD VSS / RSC_IHPSG13_CINVX8 +XDRV<3> qn_int<3> ADDR_N_O<3> VDD VSS / RSC_IHPSG13_CINVX8 +XDRV<2> qn_int<2> ADDR_N_O<2> VDD VSS / RSC_IHPSG13_CINVX8 +XDRV<1> qn_int<1> ADDR_N_O<1> VDD VSS / RSC_IHPSG13_CINVX8 +XDRV<0> qn_int<0> ADDR_N_O<0> VDD VSS / RSC_IHPSG13_CINVX8 +XDFF<6> BIST_EN_I BIST_ADDR_I<6> ACLK_N_I ADDR_I<6> q_int<6> net2<0> VDD ++ VSS / RSC_IHPSG13_DFNQMX2IX1 +XDFF<5> BIST_EN_I BIST_ADDR_I<5> ACLK_N_I ADDR_I<5> q_int<5> net2<1> VDD ++ VSS / RSC_IHPSG13_DFNQMX2IX1 +XDFF<4> BIST_EN_I BIST_ADDR_I<4> ACLK_N_I ADDR_I<4> q_int<4> net2<2> VDD ++ VSS / RSC_IHPSG13_DFNQMX2IX1 +XDFF<3> BIST_EN_I BIST_ADDR_I<3> ACLK_N_I ADDR_I<3> q_int<3> net2<3> VDD ++ VSS / RSC_IHPSG13_DFNQMX2IX1 +XDFF<2> BIST_EN_I BIST_ADDR_I<2> ACLK_N_I ADDR_I<2> q_int<2> net2<4> VDD ++ VSS / RSC_IHPSG13_DFNQMX2IX1 +XDFF<1> BIST_EN_I BIST_ADDR_I<1> ACLK_N_I ADDR_I<1> q_int<1> net2<5> VDD ++ VSS / RSC_IHPSG13_DFNQMX2IX1 +XDFF<0> BIST_EN_I BIST_ADDR_I<0> ACLK_N_I ADDR_I<0> q_int<0> net2<6> VDD ++ VSS / RSC_IHPSG13_DFNQMX2IX1 +XI11<8> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI11<7> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI11<6> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI11<5> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI11<4> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI11<3> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI11<2> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI11<1> VDD VSS / RSC_IHPSG13_FILLCAP8 +.ENDS + +.SUBCKT RM_IHPSG13_512x32_c2_1P_COLDRV13X8 ADDR_COL_I<1> ADDR_COL_I<0> ADDR_COL_O<1> ++ ADDR_COL_O<0> ADDR_DEC_I<7> ADDR_DEC_I<6> ADDR_DEC_I<5> ADDR_DEC_I<4> ++ ADDR_DEC_I<3> ADDR_DEC_I<2> ADDR_DEC_I<1> ADDR_DEC_I<0> ADDR_DEC_O<7> ++ ADDR_DEC_O<6> ADDR_DEC_O<5> ADDR_DEC_O<4> ADDR_DEC_O<3> ADDR_DEC_O<2> ++ ADDR_DEC_O<1> ADDR_DEC_O<0> DCLK_I DCLK_O RCLK_I RCLK_O WCLK_I WCLK_O ++ VDD VSS +XI0<1> VDD VSS / RSC_IHPSG13_FILLCAP4 +XI0<0> VDD VSS / RSC_IHPSG13_FILLCAP4 +XADDR_COL_DRV<1> ADDR_COL_I<1> ADDR_COL_O<1> VDD VSS / ++ RSC_IHPSG13_CBUFX8 +XADDR_COL_DRV<0> ADDR_COL_I<0> ADDR_COL_O<0> VDD VSS / ++ RSC_IHPSG13_CBUFX8 +XADDR_DEC_DRV<7> ADDR_DEC_I<7> ADDR_DEC_O<7> VDD VSS / ++ RSC_IHPSG13_CBUFX8 +XADDR_DEC_DRV<6> ADDR_DEC_I<6> ADDR_DEC_O<6> VDD VSS / ++ RSC_IHPSG13_CBUFX8 +XADDR_DEC_DRV<5> ADDR_DEC_I<5> ADDR_DEC_O<5> VDD VSS / ++ RSC_IHPSG13_CBUFX8 +XADDR_DEC_DRV<4> ADDR_DEC_I<4> ADDR_DEC_O<4> VDD VSS / ++ RSC_IHPSG13_CBUFX8 +XADDR_DEC_DRV<3> ADDR_DEC_I<3> ADDR_DEC_O<3> VDD VSS / ++ RSC_IHPSG13_CBUFX8 +XADDR_DEC_DRV<2> ADDR_DEC_I<2> ADDR_DEC_O<2> VDD VSS / ++ RSC_IHPSG13_CBUFX8 +XADDR_DEC_DRV<1> ADDR_DEC_I<1> ADDR_DEC_O<1> VDD VSS / ++ RSC_IHPSG13_CBUFX8 +XADDR_DEC_DRV<0> ADDR_DEC_I<0> ADDR_DEC_O<0> VDD VSS / ++ RSC_IHPSG13_CBUFX8 +XDCLK_DRV DCLK_I DCLK_O VDD VSS / RSC_IHPSG13_CBUFX8 +XRCLK_DRV RCLK_I RCLK_O VDD VSS / RSC_IHPSG13_CBUFX8 +XWCLK_DRV WCLK_I WCLK_O VDD VSS / RSC_IHPSG13_CBUFX8 +.ENDS +.SUBCKT RM_IHPSG13_512x32_c2_1P_WLDRV16X8 A<15> A<14> A<13> A<12> A<11> A<10> A<9> A<8> ++ A<7> A<6> A<5> A<4> A<3> A<2> A<1> A<0> Z<15> Z<14> Z<13> Z<12> Z<11> Z<10> ++ Z<9> Z<8> Z<7> Z<6> Z<5> Z<4> Z<3> Z<2> Z<1> Z<0> VDD VSS +XBUF<15> A<15> Z<15> VDD VSS / RSC_IHPSG13_WLDRVX8 +XBUF<14> A<14> Z<14> VDD VSS / RSC_IHPSG13_WLDRVX8 +XBUF<13> A<13> Z<13> VDD VSS / RSC_IHPSG13_WLDRVX8 +XBUF<12> A<12> Z<12> VDD VSS / RSC_IHPSG13_WLDRVX8 +XBUF<11> A<11> Z<11> VDD VSS / RSC_IHPSG13_WLDRVX8 +XBUF<10> A<10> Z<10> VDD VSS / RSC_IHPSG13_WLDRVX8 +XBUF<9> A<9> Z<9> VDD VSS / RSC_IHPSG13_WLDRVX8 +XBUF<8> A<8> Z<8> VDD VSS / RSC_IHPSG13_WLDRVX8 +XBUF<7> A<7> Z<7> VDD VSS / RSC_IHPSG13_WLDRVX8 +XBUF<6> A<6> Z<6> VDD VSS / RSC_IHPSG13_WLDRVX8 +XBUF<5> A<5> Z<5> VDD VSS / RSC_IHPSG13_WLDRVX8 +XBUF<4> A<4> Z<4> VDD VSS / RSC_IHPSG13_WLDRVX8 +XBUF<3> A<3> Z<3> VDD VSS / RSC_IHPSG13_WLDRVX8 +XBUF<2> A<2> Z<2> VDD VSS / RSC_IHPSG13_WLDRVX8 +XBUF<1> A<1> Z<1> VDD VSS / RSC_IHPSG13_WLDRVX8 +XBUF<0> A<0> Z<0> VDD VSS / RSC_IHPSG13_WLDRVX8 +.ENDS + + + +.SUBCKT RM_IHPSG13_512x32_c2_1P_ROWDEC6 ADDR_N_I<5> ADDR_N_I<4> ADDR_N_I<3> ADDR_N_I<2> ++ ADDR_N_I<1> ADDR_N_I<0> CS_I ECLK_I WL_O<63> WL_O<62> WL_O<61> WL_O<60> ++ WL_O<59> WL_O<58> WL_O<57> WL_O<56> WL_O<55> WL_O<54> WL_O<53> WL_O<52> ++ WL_O<51> WL_O<50> WL_O<49> WL_O<48> WL_O<47> WL_O<46> WL_O<45> WL_O<44> ++ WL_O<43> WL_O<42> WL_O<41> WL_O<40> WL_O<39> WL_O<38> WL_O<37> WL_O<36> ++ WL_O<35> WL_O<34> WL_O<33> WL_O<32> WL_O<31> WL_O<30> WL_O<29> WL_O<28> ++ WL_O<27> WL_O<26> WL_O<25> WL_O<24> WL_O<23> WL_O<22> WL_O<21> WL_O<20> ++ WL_O<19> WL_O<18> WL_O<17> WL_O<16> WL_O<15> WL_O<14> WL_O<13> WL_O<12> ++ WL_O<11> WL_O<10> WL_O<9> WL_O<8> WL_O<7> WL_O<6> WL_O<5> WL_O<4> WL_O<3> ++ WL_O<2> WL_O<1> WL_O<0> VDD VSS +XDEC11 ADDR_N_I<5> ADDR_N_I<4> CS_I CS00<3> VDD VSS / ++ RM_IHPSG13_512x32_c2_1P_DEC03 +XDEC00 ADDR_N_I<5> ADDR_N_I<4> CS_I CS00<0> VDD VSS / ++ RM_IHPSG13_512x32_c2_1P_DEC00 +XDEC01 ADDR_N_I<5> ADDR_N_I<4> CS_I CS00<1> VDD VSS / ++ RM_IHPSG13_512x32_c2_1P_DEC01 +XDEC10 ADDR_N_I<5> ADDR_N_I<4> CS_I CS00<2> VDD VSS / ++ RM_IHPSG13_512x32_c2_1P_DEC02 +XSEL<3> ADDR_N_I<3> ADDR_N_I<2> ADDR_N_I<1> ADDR_N_I<0> CS00<3> ECLK_H<3> ++ ECLK_H<4> ECLK_B<3> ECLK_B<4> WL_O<63> WL_O<62> WL_O<61> WL_O<60> WL_O<59> ++ WL_O<58> WL_O<57> WL_O<56> WL_O<55> WL_O<54> WL_O<53> WL_O<52> WL_O<51> ++ WL_O<50> WL_O<49> WL_O<48> VDD VSS / RM_IHPSG13_512x32_c2_1P_DEC04 +XSEL<2> ADDR_N_I<3> ADDR_N_I<2> ADDR_N_I<1> ADDR_N_I<0> CS00<2> ECLK_H<2> ++ ECLK_H<3> ECLK_B<2> ECLK_B<3> WL_O<47> WL_O<46> WL_O<45> WL_O<44> WL_O<43> ++ WL_O<42> WL_O<41> WL_O<40> WL_O<39> WL_O<38> WL_O<37> WL_O<36> WL_O<35> ++ WL_O<34> WL_O<33> WL_O<32> VDD VSS / RM_IHPSG13_512x32_c2_1P_DEC04 +XSEL<1> ADDR_N_I<3> ADDR_N_I<2> ADDR_N_I<1> ADDR_N_I<0> CS00<1> ECLK_H<1> ++ ECLK_H<2> ECLK_B<1> ECLK_B<2> WL_O<31> WL_O<30> WL_O<29> WL_O<28> WL_O<27> ++ WL_O<26> WL_O<25> WL_O<24> WL_O<23> WL_O<22> WL_O<21> WL_O<20> WL_O<19> ++ WL_O<18> WL_O<17> WL_O<16> VDD VSS / RM_IHPSG13_512x32_c2_1P_DEC04 +XSEL<0> ADDR_N_I<3> ADDR_N_I<2> ADDR_N_I<1> ADDR_N_I<0> CS00<0> ECLK_I ++ ECLK_H<1> ECLK_B<0> ECLK_B<1> WL_O<15> WL_O<14> WL_O<13> WL_O<12> WL_O<11> ++ WL_O<10> WL_O<9> WL_O<8> WL_O<7> WL_O<6> WL_O<5> WL_O<4> WL_O<3> WL_O<2> ++ WL_O<1> WL_O<0> VDD VSS / RM_IHPSG13_512x32_c2_1P_DEC04 +XL2<24> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<23> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<22> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<21> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<20> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<19> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<18> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<17> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<16> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<15> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<14> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<13> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<12> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<11> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<10> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<9> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<8> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<7> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<6> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<5> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<4> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<3> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<2> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<1> VDD VSS / RSC_IHPSG13_FILLCAP8 +.ENDS +.SUBCKT RM_IHPSG13_512x32_c2_1P_ROWREG6 ACLK_N_I ADDR_I<5> ADDR_I<4> ADDR_I<3> ADDR_I<2> ++ ADDR_I<1> ADDR_I<0> ADDR_N_O<5> ADDR_N_O<4> ADDR_N_O<3> ADDR_N_O<2> ++ ADDR_N_O<1> ADDR_N_O<0> BIST_ADDR_I<5> BIST_ADDR_I<4> BIST_ADDR_I<3> ++ BIST_ADDR_I<2> BIST_ADDR_I<1> BIST_ADDR_I<0> BIST_EN_I VDD VSS +XINV<5> q_int<5> qn_int<5> VDD VSS / RSC_IHPSG13_CINVX2 +XINV<4> q_int<4> qn_int<4> VDD VSS / RSC_IHPSG13_CINVX2 +XINV<3> q_int<3> qn_int<3> VDD VSS / RSC_IHPSG13_CINVX2 +XINV<2> q_int<2> qn_int<2> VDD VSS / RSC_IHPSG13_CINVX2 +XINV<1> q_int<1> qn_int<1> VDD VSS / RSC_IHPSG13_CINVX2 +XINV<0> q_int<0> qn_int<0> VDD VSS / RSC_IHPSG13_CINVX2 +XDRV<5> qn_int<5> ADDR_N_O<5> VDD VSS / RSC_IHPSG13_CINVX8 +XDRV<4> qn_int<4> ADDR_N_O<4> VDD VSS / RSC_IHPSG13_CINVX8 +XDRV<3> qn_int<3> ADDR_N_O<3> VDD VSS / RSC_IHPSG13_CINVX8 +XDRV<2> qn_int<2> ADDR_N_O<2> VDD VSS / RSC_IHPSG13_CINVX8 +XDRV<1> qn_int<1> ADDR_N_O<1> VDD VSS / RSC_IHPSG13_CINVX8 +XDRV<0> qn_int<0> ADDR_N_O<0> VDD VSS / RSC_IHPSG13_CINVX8 +XDFF<5> BIST_EN_I BIST_ADDR_I<5> ACLK_N_I ADDR_I<5> q_int<5> net2<0> VDD ++ VSS / RSC_IHPSG13_DFNQMX2IX1 +XDFF<4> BIST_EN_I BIST_ADDR_I<4> ACLK_N_I ADDR_I<4> q_int<4> net2<1> VDD ++ VSS / RSC_IHPSG13_DFNQMX2IX1 +XDFF<3> BIST_EN_I BIST_ADDR_I<3> ACLK_N_I ADDR_I<3> q_int<3> net2<2> VDD ++ VSS / RSC_IHPSG13_DFNQMX2IX1 +XDFF<2> BIST_EN_I BIST_ADDR_I<2> ACLK_N_I ADDR_I<2> q_int<2> net2<3> VDD ++ VSS / RSC_IHPSG13_DFNQMX2IX1 +XDFF<1> BIST_EN_I BIST_ADDR_I<1> ACLK_N_I ADDR_I<1> q_int<1> net2<4> VDD ++ VSS / RSC_IHPSG13_DFNQMX2IX1 +XDFF<0> BIST_EN_I BIST_ADDR_I<0> ACLK_N_I ADDR_I<0> q_int<0> net2<5> VDD ++ VSS / RSC_IHPSG13_DFNQMX2IX1 +XI11<12> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI11<11> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI11<10> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI11<9> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI11<8> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI11<7> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI11<6> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI11<5> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI11<4> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI11<3> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI11<2> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI11<1> VDD VSS / RSC_IHPSG13_FILLCAP8 +.ENDS + + +.SUBCKT RM_IHPSG13_512x32_c2_2P_COLUMN_pcell_0 A_BLC_BOT<1> A_BLC_BOT<0> A_BLC_TOP<1> A_BLC_TOP<0> A_BLT_BOT<1> A_BLT_BOT<0> A_BLT_TOP<1> A_BLT_TOP<0> A_LWL<127> A_LWL<126> A_LWL<125> A_LWL<124> A_LWL<123> A_LWL<122> A_LWL<121> A_LWL<120> A_LWL<119> A_LWL<118> A_LWL<117> A_LWL<116> A_LWL<115> A_LWL<114> A_LWL<113> A_LWL<112> A_LWL<111> A_LWL<110> A_LWL<109> A_LWL<108> A_LWL<107> A_LWL<106> A_LWL<105> A_LWL<104> A_LWL<103> A_LWL<102> A_LWL<101> A_LWL<100> A_LWL<99> A_LWL<98> A_LWL<97> A_LWL<96> A_LWL<95> A_LWL<94> A_LWL<93> A_LWL<92> A_LWL<91> A_LWL<90> A_LWL<89> A_LWL<88> A_LWL<87> A_LWL<86> A_LWL<85> A_LWL<84> A_LWL<83> A_LWL<82> A_LWL<81> A_LWL<80> A_LWL<79> A_LWL<78> A_LWL<77> A_LWL<76> A_LWL<75> A_LWL<74> A_LWL<73> A_LWL<72> A_LWL<71> A_LWL<70> A_LWL<69> A_LWL<68> A_LWL<67> A_LWL<66> A_LWL<65> A_LWL<64> A_LWL<63> A_LWL<62> A_LWL<61> A_LWL<60> A_LWL<59> A_LWL<58> A_LWL<57> A_LWL<56> A_LWL<55> A_LWL<54> A_LWL<53> A_LWL<52> A_LWL<51> A_LWL<50> A_LWL<49> A_LWL<48> A_LWL<47> A_LWL<46> A_LWL<45> A_LWL<44> A_LWL<43> A_LWL<42> A_LWL<41> A_LWL<40> A_LWL<39> A_LWL<38> A_LWL<37> A_LWL<36> A_LWL<35> A_LWL<34> A_LWL<33> A_LWL<32> A_LWL<31> A_LWL<30> A_LWL<29> A_LWL<28> A_LWL<27> A_LWL<26> A_LWL<25> A_LWL<24> A_LWL<23> A_LWL<22> A_LWL<21> A_LWL<20> A_LWL<19> A_LWL<18> A_LWL<17> A_LWL<16> A_LWL<15> A_LWL<14> A_LWL<13> A_LWL<12> A_LWL<11> A_LWL<10> A_LWL<9> A_LWL<8> A_LWL<7> A_LWL<6> A_LWL<5> A_LWL<4> A_LWL<3> A_LWL<2> A_LWL<1> A_LWL<0> A_RWL<127> A_RWL<126> A_RWL<125> A_RWL<124> A_RWL<123> A_RWL<122> A_RWL<121> A_RWL<120> A_RWL<119> A_RWL<118> A_RWL<117> A_RWL<116> A_RWL<115> A_RWL<114> A_RWL<113> A_RWL<112> A_RWL<111> A_RWL<110> A_RWL<109> A_RWL<108> A_RWL<107> A_RWL<106> A_RWL<105> A_RWL<104> A_RWL<103> A_RWL<102> A_RWL<101> A_RWL<100> A_RWL<99> A_RWL<98> A_RWL<97> A_RWL<96> A_RWL<95> A_RWL<94> A_RWL<93> A_RWL<92> A_RWL<91> A_RWL<90> A_RWL<89> A_RWL<88> A_RWL<87> A_RWL<86> A_RWL<85> A_RWL<84> A_RWL<83> A_RWL<82> A_RWL<81> A_RWL<80> A_RWL<79> A_RWL<78> A_RWL<77> A_RWL<76> A_RWL<75> A_RWL<74> A_RWL<73> A_RWL<72> A_RWL<71> A_RWL<70> A_RWL<69> A_RWL<68> A_RWL<67> A_RWL<66> A_RWL<65> A_RWL<64> A_RWL<63> A_RWL<62> A_RWL<61> A_RWL<60> A_RWL<59> A_RWL<58> A_RWL<57> A_RWL<56> A_RWL<55> A_RWL<54> A_RWL<53> A_RWL<52> A_RWL<51> A_RWL<50> A_RWL<49> A_RWL<48> A_RWL<47> A_RWL<46> A_RWL<45> A_RWL<44> A_RWL<43> A_RWL<42> A_RWL<41> A_RWL<40> A_RWL<39> A_RWL<38> A_RWL<37> A_RWL<36> A_RWL<35> A_RWL<34> A_RWL<33> A_RWL<32> A_RWL<31> A_RWL<30> A_RWL<29> A_RWL<28> A_RWL<27> A_RWL<26> A_RWL<25> A_RWL<24> A_RWL<23> A_RWL<22> A_RWL<21> A_RWL<20> A_RWL<19> A_RWL<18> A_RWL<17> A_RWL<16> A_RWL<15> A_RWL<14> A_RWL<13> A_RWL<12> A_RWL<11> A_RWL<10> A_RWL<9> A_RWL<8> A_RWL<7> A_RWL<6> A_RWL<5> A_RWL<4> A_RWL<3> A_RWL<2> A_RWL<1> A_RWL<0> B_BLC_BOT<1> B_BLC_BOT<0> B_BLC_TOP<1> B_BLC_TOP<0> B_BLT_BOT<1> B_BLT_BOT<0> B_BLT_TOP<1> B_BLT_TOP<0> B_LWL<127> B_LWL<126> B_LWL<125> B_LWL<124> B_LWL<123> B_LWL<122> B_LWL<121> B_LWL<120> B_LWL<119> B_LWL<118> B_LWL<117> B_LWL<116> B_LWL<115> B_LWL<114> B_LWL<113> B_LWL<112> B_LWL<111> B_LWL<110> B_LWL<109> B_LWL<108> B_LWL<107> B_LWL<106> B_LWL<105> B_LWL<104> B_LWL<103> B_LWL<102> B_LWL<101> B_LWL<100> B_LWL<99> B_LWL<98> B_LWL<97> B_LWL<96> B_LWL<95> B_LWL<94> B_LWL<93> B_LWL<92> B_LWL<91> B_LWL<90> B_LWL<89> B_LWL<88> B_LWL<87> B_LWL<86> B_LWL<85> B_LWL<84> B_LWL<83> B_LWL<82> B_LWL<81> B_LWL<80> B_LWL<79> B_LWL<78> B_LWL<77> B_LWL<76> B_LWL<75> B_LWL<74> B_LWL<73> B_LWL<72> B_LWL<71> B_LWL<70> B_LWL<69> B_LWL<68> B_LWL<67> B_LWL<66> B_LWL<65> B_LWL<64> B_LWL<63> B_LWL<62> B_LWL<61> B_LWL<60> B_LWL<59> B_LWL<58> B_LWL<57> B_LWL<56> B_LWL<55> B_LWL<54> B_LWL<53> B_LWL<52> B_LWL<51> B_LWL<50> B_LWL<49> B_LWL<48> B_LWL<47> B_LWL<46> B_LWL<45> B_LWL<44> B_LWL<43> B_LWL<42> B_LWL<41> B_LWL<40> B_LWL<39> B_LWL<38> B_LWL<37> B_LWL<36> B_LWL<35> B_LWL<34> B_LWL<33> B_LWL<32> B_LWL<31> B_LWL<30> B_LWL<29> B_LWL<28> B_LWL<27> B_LWL<26> B_LWL<25> B_LWL<24> B_LWL<23> B_LWL<22> B_LWL<21> B_LWL<20> B_LWL<19> B_LWL<18> B_LWL<17> B_LWL<16> B_LWL<15> B_LWL<14> B_LWL<13> B_LWL<12> B_LWL<11> B_LWL<10> B_LWL<9> B_LWL<8> B_LWL<7> B_LWL<6> B_LWL<5> B_LWL<4> B_LWL<3> B_LWL<2> B_LWL<1> B_LWL<0> B_RWL<127> B_RWL<126> B_RWL<125> B_RWL<124> B_RWL<123> B_RWL<122> B_RWL<121> B_RWL<120> B_RWL<119> B_RWL<118> B_RWL<117> B_RWL<116> B_RWL<115> B_RWL<114> B_RWL<113> B_RWL<112> B_RWL<111> B_RWL<110> B_RWL<109> B_RWL<108> B_RWL<107> B_RWL<106> B_RWL<105> B_RWL<104> B_RWL<103> B_RWL<102> B_RWL<101> B_RWL<100> B_RWL<99> B_RWL<98> B_RWL<97> B_RWL<96> B_RWL<95> B_RWL<94> B_RWL<93> B_RWL<92> B_RWL<91> B_RWL<90> B_RWL<89> B_RWL<88> B_RWL<87> B_RWL<86> B_RWL<85> B_RWL<84> B_RWL<83> B_RWL<82> B_RWL<81> B_RWL<80> B_RWL<79> B_RWL<78> B_RWL<77> B_RWL<76> B_RWL<75> B_RWL<74> B_RWL<73> B_RWL<72> B_RWL<71> B_RWL<70> B_RWL<69> B_RWL<68> B_RWL<67> B_RWL<66> B_RWL<65> B_RWL<64> B_RWL<63> B_RWL<62> B_RWL<61> B_RWL<60> B_RWL<59> B_RWL<58> B_RWL<57> B_RWL<56> B_RWL<55> B_RWL<54> B_RWL<53> B_RWL<52> B_RWL<51> B_RWL<50> B_RWL<49> B_RWL<48> B_RWL<47> B_RWL<46> B_RWL<45> B_RWL<44> B_RWL<43> B_RWL<42> B_RWL<41> B_RWL<40> B_RWL<39> B_RWL<38> B_RWL<37> B_RWL<36> B_RWL<35> B_RWL<34> B_RWL<33> B_RWL<32> B_RWL<31> B_RWL<30> B_RWL<29> B_RWL<28> B_RWL<27> B_RWL<26> B_RWL<25> B_RWL<24> B_RWL<23> B_RWL<22> B_RWL<21> B_RWL<20> B_RWL<19> B_RWL<18> B_RWL<17> B_RWL<16> B_RWL<15> B_RWL<14> B_RWL<13> B_RWL<12> B_RWL<11> B_RWL<10> B_RWL<9> B_RWL<8> B_RWL<7> B_RWL<6> B_RWL<5> B_RWL<4> B_RWL<3> B_RWL<2> B_RWL<1> B_RWL<0> VDD_CORE VSS +XRAM<8> A_BLC<13> A_BLC<12> A_BLC_TOP<1> A_BLC_TOP<0> A_BLT<13> A_BLT<12> A_BLT_TOP<1> A_BLT_TOP<0> A_LWL<127> A_LWL<126> A_LWL<125> A_LWL<124> A_LWL<123> A_LWL<122> A_LWL<121> A_LWL<120> A_LWL<119> A_LWL<118> A_LWL<117> A_LWL<116> A_LWL<115> A_LWL<114> A_LWL<113> A_LWL<112> A_RWL<127> A_RWL<126> A_RWL<125> A_RWL<124> A_RWL<123> A_RWL<122> A_RWL<121> A_RWL<120> A_RWL<119> A_RWL<118> A_RWL<117> A_RWL<116> A_RWL<115> A_RWL<114> A_RWL<113> A_RWL<112> B_BLC<13> B_BLC<12> B_BLC_TOP<1> B_BLC_TOP<0> B_BLT<13> B_BLT<12> B_BLT_TOP<1> B_BLT_TOP<0> B_LWL<127> B_LWL<126> B_LWL<125> B_LWL<124> B_LWL<123> B_LWL<122> B_LWL<121> B_LWL<120> B_LWL<119> B_LWL<118> B_LWL<117> B_LWL<116> B_LWL<115> B_LWL<114> B_LWL<113> B_LWL<112> B_RWL<127> B_RWL<126> B_RWL<125> B_RWL<124> B_RWL<123> B_RWL<122> B_RWL<121> B_RWL<120> B_RWL<119> B_RWL<118> B_RWL<117> B_RWL<116> B_RWL<115> B_RWL<114> B_RWL<113> B_RWL<112> VDD_CORE VSS / RM_IHPSG13_512x32_c2_2P_BITKIT_16x2_SRAM +XRAM<7> A_BLC<11> A_BLC<10> A_BLC<13> A_BLC<12> A_BLT<11> A_BLT<10> A_BLT<13> A_BLT<12> A_LWL<111> A_LWL<110> A_LWL<109> A_LWL<108> A_LWL<107> A_LWL<106> A_LWL<105> A_LWL<104> A_LWL<103> A_LWL<102> A_LWL<101> A_LWL<100> A_LWL<99> A_LWL<98> A_LWL<97> A_LWL<96> A_RWL<111> A_RWL<110> A_RWL<109> A_RWL<108> A_RWL<107> A_RWL<106> A_RWL<105> A_RWL<104> A_RWL<103> A_RWL<102> A_RWL<101> A_RWL<100> A_RWL<99> A_RWL<98> A_RWL<97> A_RWL<96> B_BLC<11> B_BLC<10> B_BLC<13> B_BLC<12> B_BLT<11> B_BLT<10> B_BLT<13> B_BLT<12> B_LWL<111> B_LWL<110> B_LWL<109> B_LWL<108> B_LWL<107> B_LWL<106> B_LWL<105> B_LWL<104> B_LWL<103> B_LWL<102> B_LWL<101> B_LWL<100> B_LWL<99> B_LWL<98> B_LWL<97> B_LWL<96> B_RWL<111> B_RWL<110> B_RWL<109> B_RWL<108> B_RWL<107> B_RWL<106> B_RWL<105> B_RWL<104> B_RWL<103> B_RWL<102> B_RWL<101> B_RWL<100> B_RWL<99> B_RWL<98> B_RWL<97> B_RWL<96> VDD_CORE VSS / RM_IHPSG13_512x32_c2_2P_BITKIT_16x2_SRAM +XRAM<6> A_BLC<9> A_BLC<8> A_BLC<11> A_BLC<10> A_BLT<9> A_BLT<8> A_BLT<11> A_BLT<10> A_LWL<95> A_LWL<94> A_LWL<93> A_LWL<92> A_LWL<91> A_LWL<90> A_LWL<89> A_LWL<88> A_LWL<87> A_LWL<86> A_LWL<85> A_LWL<84> A_LWL<83> A_LWL<82> A_LWL<81> A_LWL<80> A_RWL<95> A_RWL<94> A_RWL<93> A_RWL<92> A_RWL<91> A_RWL<90> A_RWL<89> A_RWL<88> A_RWL<87> A_RWL<86> A_RWL<85> A_RWL<84> A_RWL<83> A_RWL<82> A_RWL<81> A_RWL<80> B_BLC<9> B_BLC<8> B_BLC<11> B_BLC<10> B_BLT<9> B_BLT<8> B_BLT<11> B_BLT<10> B_LWL<95> B_LWL<94> B_LWL<93> B_LWL<92> B_LWL<91> B_LWL<90> B_LWL<89> B_LWL<88> B_LWL<87> B_LWL<86> B_LWL<85> B_LWL<84> B_LWL<83> B_LWL<82> B_LWL<81> B_LWL<80> B_RWL<95> B_RWL<94> B_RWL<93> B_RWL<92> B_RWL<91> B_RWL<90> B_RWL<89> B_RWL<88> B_RWL<87> B_RWL<86> B_RWL<85> B_RWL<84> B_RWL<83> B_RWL<82> B_RWL<81> B_RWL<80> VDD_CORE VSS / RM_IHPSG13_512x32_c2_2P_BITKIT_16x2_SRAM +XRAM<5> A_BLC<7> A_BLC<6> A_BLC<9> A_BLC<8> A_BLT<7> A_BLT<6> A_BLT<9> A_BLT<8> A_LWL<79> A_LWL<78> A_LWL<77> A_LWL<76> A_LWL<75> A_LWL<74> A_LWL<73> A_LWL<72> A_LWL<71> A_LWL<70> A_LWL<69> A_LWL<68> A_LWL<67> A_LWL<66> A_LWL<65> A_LWL<64> A_RWL<79> A_RWL<78> A_RWL<77> A_RWL<76> A_RWL<75> A_RWL<74> A_RWL<73> A_RWL<72> A_RWL<71> A_RWL<70> A_RWL<69> A_RWL<68> A_RWL<67> A_RWL<66> A_RWL<65> A_RWL<64> B_BLC<7> B_BLC<6> B_BLC<9> B_BLC<8> B_BLT<7> B_BLT<6> B_BLT<9> B_BLT<8> B_LWL<79> B_LWL<78> B_LWL<77> B_LWL<76> B_LWL<75> B_LWL<74> B_LWL<73> B_LWL<72> B_LWL<71> B_LWL<70> B_LWL<69> B_LWL<68> B_LWL<67> B_LWL<66> B_LWL<65> B_LWL<64> B_RWL<79> B_RWL<78> B_RWL<77> B_RWL<76> B_RWL<75> B_RWL<74> B_RWL<73> B_RWL<72> B_RWL<71> B_RWL<70> B_RWL<69> B_RWL<68> B_RWL<67> B_RWL<66> B_RWL<65> B_RWL<64> VDD_CORE VSS / RM_IHPSG13_512x32_c2_2P_BITKIT_16x2_SRAM +XRAM<4> A_BLC<5> A_BLC<4> A_BLC<7> A_BLC<6> A_BLT<5> A_BLT<4> A_BLT<7> A_BLT<6> A_LWL<63> A_LWL<62> A_LWL<61> A_LWL<60> A_LWL<59> A_LWL<58> A_LWL<57> A_LWL<56> A_LWL<55> A_LWL<54> A_LWL<53> A_LWL<52> A_LWL<51> A_LWL<50> A_LWL<49> A_LWL<48> A_RWL<63> A_RWL<62> A_RWL<61> A_RWL<60> A_RWL<59> A_RWL<58> A_RWL<57> A_RWL<56> A_RWL<55> A_RWL<54> A_RWL<53> A_RWL<52> A_RWL<51> A_RWL<50> A_RWL<49> A_RWL<48> B_BLC<5> B_BLC<4> B_BLC<7> B_BLC<6> B_BLT<5> B_BLT<4> B_BLT<7> B_BLT<6> B_LWL<63> B_LWL<62> B_LWL<61> B_LWL<60> B_LWL<59> B_LWL<58> B_LWL<57> B_LWL<56> B_LWL<55> B_LWL<54> B_LWL<53> B_LWL<52> B_LWL<51> B_LWL<50> B_LWL<49> B_LWL<48> B_RWL<63> B_RWL<62> B_RWL<61> B_RWL<60> B_RWL<59> B_RWL<58> B_RWL<57> B_RWL<56> B_RWL<55> B_RWL<54> B_RWL<53> B_RWL<52> B_RWL<51> B_RWL<50> B_RWL<49> B_RWL<48> VDD_CORE VSS / RM_IHPSG13_512x32_c2_2P_BITKIT_16x2_SRAM +XRAM<3> A_BLC<3> A_BLC<2> A_BLC<5> A_BLC<4> A_BLT<3> A_BLT<2> A_BLT<5> A_BLT<4> A_LWL<47> A_LWL<46> A_LWL<45> A_LWL<44> A_LWL<43> A_LWL<42> A_LWL<41> A_LWL<40> A_LWL<39> A_LWL<38> A_LWL<37> A_LWL<36> A_LWL<35> A_LWL<34> A_LWL<33> A_LWL<32> A_RWL<47> A_RWL<46> A_RWL<45> A_RWL<44> A_RWL<43> A_RWL<42> A_RWL<41> A_RWL<40> A_RWL<39> A_RWL<38> A_RWL<37> A_RWL<36> A_RWL<35> A_RWL<34> A_RWL<33> A_RWL<32> B_BLC<3> B_BLC<2> B_BLC<5> B_BLC<4> B_BLT<3> B_BLT<2> B_BLT<5> B_BLT<4> B_LWL<47> B_LWL<46> B_LWL<45> B_LWL<44> B_LWL<43> B_LWL<42> B_LWL<41> B_LWL<40> B_LWL<39> B_LWL<38> B_LWL<37> B_LWL<36> B_LWL<35> B_LWL<34> B_LWL<33> B_LWL<32> B_RWL<47> B_RWL<46> B_RWL<45> B_RWL<44> B_RWL<43> B_RWL<42> B_RWL<41> B_RWL<40> B_RWL<39> B_RWL<38> B_RWL<37> B_RWL<36> B_RWL<35> B_RWL<34> B_RWL<33> B_RWL<32> VDD_CORE VSS / RM_IHPSG13_512x32_c2_2P_BITKIT_16x2_SRAM +XRAM<2> A_BLC<1> A_BLC<0> A_BLC<3> A_BLC<2> A_BLT<1> A_BLT<0> A_BLT<3> A_BLT<2> A_LWL<31> A_LWL<30> A_LWL<29> A_LWL<28> A_LWL<27> A_LWL<26> A_LWL<25> A_LWL<24> A_LWL<23> A_LWL<22> A_LWL<21> A_LWL<20> A_LWL<19> A_LWL<18> A_LWL<17> A_LWL<16> A_RWL<31> A_RWL<30> A_RWL<29> A_RWL<28> A_RWL<27> A_RWL<26> A_RWL<25> A_RWL<24> A_RWL<23> A_RWL<22> A_RWL<21> A_RWL<20> A_RWL<19> A_RWL<18> A_RWL<17> A_RWL<16> B_BLC<1> B_BLC<0> B_BLC<3> B_BLC<2> B_BLT<1> B_BLT<0> B_BLT<3> B_BLT<2> B_LWL<31> B_LWL<30> B_LWL<29> B_LWL<28> B_LWL<27> B_LWL<26> B_LWL<25> B_LWL<24> B_LWL<23> B_LWL<22> B_LWL<21> B_LWL<20> B_LWL<19> B_LWL<18> B_LWL<17> B_LWL<16> B_RWL<31> B_RWL<30> B_RWL<29> B_RWL<28> B_RWL<27> B_RWL<26> B_RWL<25> B_RWL<24> B_RWL<23> B_RWL<22> B_RWL<21> B_RWL<20> B_RWL<19> B_RWL<18> B_RWL<17> B_RWL<16> VDD_CORE VSS / RM_IHPSG13_512x32_c2_2P_BITKIT_16x2_SRAM +XRAM<1> A_BLC_BOT<1> A_BLC_BOT<0> A_BLC<1> A_BLC<0> A_BLT_BOT<1> A_BLT_BOT<0> A_BLT<1> A_BLT<0> A_LWL<15> A_LWL<14> A_LWL<13> A_LWL<12> A_LWL<11> A_LWL<10> A_LWL<9> A_LWL<8> A_LWL<7> A_LWL<6> A_LWL<5> A_LWL<4> A_LWL<3> A_LWL<2> A_LWL<1> A_LWL<0> A_RWL<15> A_RWL<14> A_RWL<13> A_RWL<12> A_RWL<11> A_RWL<10> A_RWL<9> A_RWL<8> A_RWL<7> A_RWL<6> A_RWL<5> A_RWL<4> A_RWL<3> A_RWL<2> A_RWL<1> A_RWL<0> B_BLC_BOT<1> B_BLC_BOT<0> B_BLC<1> B_BLC<0> B_BLT_BOT<1> B_BLT_BOT<0> B_BLT<1> B_BLT<0> B_LWL<15> B_LWL<14> B_LWL<13> B_LWL<12> B_LWL<11> B_LWL<10> B_LWL<9> B_LWL<8> B_LWL<7> B_LWL<6> B_LWL<5> B_LWL<4> B_LWL<3> B_LWL<2> B_LWL<1> B_LWL<0> B_RWL<15> B_RWL<14> B_RWL<13> B_RWL<12> B_RWL<11> B_RWL<10> B_RWL<9> B_RWL<8> B_RWL<7> B_RWL<6> B_RWL<5> B_RWL<4> B_RWL<3> B_RWL<2> B_RWL<1> B_RWL<0> VDD_CORE VSS / RM_IHPSG13_512x32_c2_2P_BITKIT_16x2_SRAM +XEDGE<1> A_BLC_TOP<1> A_BLC_TOP<0> A_BLT_TOP<1> A_BLT_TOP<0> B_BLC_TOP<1> B_BLC_TOP<0> B_BLT_TOP<1> B_BLT_TOP<0> VDD_CORE VSS / RM_IHPSG13_512x32_c2_2P_BITKIT_16x2_EDGE_TB +XEDGE<0> A_BLC_BOT<1> A_BLC_BOT<0> A_BLT_BOT<1> A_BLT_BOT<0> B_BLC_BOT<1> B_BLC_BOT<0> B_BLT_BOT<1> B_BLT_BOT<0> VDD_CORE VSS / RM_IHPSG13_512x32_c2_2P_BITKIT_16x2_EDGE_TB +.ENDS + + + + +.SUBCKT RM_IHPSG13_512x32_c2_2P_MATRIX_pcell_1 A_BLC<63> A_BLC<62> A_BLC<61> A_BLC<60> A_BLC<59> A_BLC<58> A_BLC<57> A_BLC<56> A_BLC<55> A_BLC<54> A_BLC<53> A_BLC<52> A_BLC<51> A_BLC<50> A_BLC<49> A_BLC<48> A_BLC<47> A_BLC<46> A_BLC<45> A_BLC<44> A_BLC<43> A_BLC<42> A_BLC<41> A_BLC<40> A_BLC<39> A_BLC<38> A_BLC<37> A_BLC<36> A_BLC<35> A_BLC<34> A_BLC<33> A_BLC<32> A_BLC<31> A_BLC<30> A_BLC<29> A_BLC<28> A_BLC<27> A_BLC<26> A_BLC<25> A_BLC<24> A_BLC<23> A_BLC<22> A_BLC<21> A_BLC<20> A_BLC<19> A_BLC<18> A_BLC<17> A_BLC<16> A_BLC<15> A_BLC<14> A_BLC<13> A_BLC<12> A_BLC<11> A_BLC<10> A_BLC<9> A_BLC<8> A_BLC<7> A_BLC<6> A_BLC<5> A_BLC<4> A_BLC<3> A_BLC<2> A_BLC<1> A_BLC<0> A_BLT<63> A_BLT<62> A_BLT<61> A_BLT<60> A_BLT<59> A_BLT<58> A_BLT<57> A_BLT<56> A_BLT<55> A_BLT<54> A_BLT<53> A_BLT<52> A_BLT<51> A_BLT<50> A_BLT<49> A_BLT<48> A_BLT<47> A_BLT<46> A_BLT<45> A_BLT<44> A_BLT<43> A_BLT<42> A_BLT<41> A_BLT<40> A_BLT<39> A_BLT<38> A_BLT<37> A_BLT<36> A_BLT<35> A_BLT<34> A_BLT<33> A_BLT<32> A_BLT<31> A_BLT<30> A_BLT<29> A_BLT<28> A_BLT<27> A_BLT<26> A_BLT<25> A_BLT<24> A_BLT<23> A_BLT<22> A_BLT<21> A_BLT<20> A_BLT<19> A_BLT<18> A_BLT<17> A_BLT<16> A_BLT<15> A_BLT<14> A_BLT<13> A_BLT<12> A_BLT<11> A_BLT<10> A_BLT<9> A_BLT<8> A_BLT<7> A_BLT<6> A_BLT<5> A_BLT<4> A_BLT<3> A_BLT<2> A_BLT<1> A_BLT<0> A_WL<127> A_WL<126> A_WL<125> A_WL<124> A_WL<123> A_WL<122> A_WL<121> A_WL<120> A_WL<119> A_WL<118> A_WL<117> A_WL<116> A_WL<115> A_WL<114> A_WL<113> A_WL<112> A_WL<111> A_WL<110> A_WL<109> A_WL<108> A_WL<107> A_WL<106> A_WL<105> A_WL<104> A_WL<103> A_WL<102> A_WL<101> A_WL<100> A_WL<99> A_WL<98> A_WL<97> A_WL<96> A_WL<95> A_WL<94> A_WL<93> A_WL<92> A_WL<91> A_WL<90> A_WL<89> A_WL<88> A_WL<87> A_WL<86> A_WL<85> A_WL<84> A_WL<83> A_WL<82> A_WL<81> A_WL<80> A_WL<79> A_WL<78> A_WL<77> A_WL<76> A_WL<75> A_WL<74> A_WL<73> A_WL<72> A_WL<71> A_WL<70> A_WL<69> A_WL<68> A_WL<67> A_WL<66> A_WL<65> A_WL<64> A_WL<63> A_WL<62> A_WL<61> A_WL<60> A_WL<59> A_WL<58> A_WL<57> A_WL<56> A_WL<55> A_WL<54> A_WL<53> A_WL<52> A_WL<51> A_WL<50> A_WL<49> A_WL<48> A_WL<47> A_WL<46> A_WL<45> A_WL<44> A_WL<43> A_WL<42> A_WL<41> A_WL<40> A_WL<39> A_WL<38> A_WL<37> A_WL<36> A_WL<35> A_WL<34> A_WL<33> A_WL<32> A_WL<31> A_WL<30> A_WL<29> A_WL<28> A_WL<27> A_WL<26> A_WL<25> A_WL<24> A_WL<23> A_WL<22> A_WL<21> A_WL<20> A_WL<19> A_WL<18> A_WL<17> A_WL<16> A_WL<15> A_WL<14> A_WL<13> A_WL<12> A_WL<11> A_WL<10> A_WL<9> A_WL<8> A_WL<7> A_WL<6> A_WL<5> A_WL<4> A_WL<3> A_WL<2> A_WL<1> A_WL<0> B_BLC<63> B_BLC<62> B_BLC<61> B_BLC<60> B_BLC<59> B_BLC<58> B_BLC<57> B_BLC<56> B_BLC<55> B_BLC<54> B_BLC<53> B_BLC<52> B_BLC<51> B_BLC<50> B_BLC<49> B_BLC<48> B_BLC<47> B_BLC<46> B_BLC<45> B_BLC<44> B_BLC<43> B_BLC<42> B_BLC<41> B_BLC<40> B_BLC<39> B_BLC<38> B_BLC<37> B_BLC<36> B_BLC<35> B_BLC<34> B_BLC<33> B_BLC<32> B_BLC<31> B_BLC<30> B_BLC<29> B_BLC<28> B_BLC<27> B_BLC<26> B_BLC<25> B_BLC<24> B_BLC<23> B_BLC<22> B_BLC<21> B_BLC<20> B_BLC<19> B_BLC<18> B_BLC<17> B_BLC<16> B_BLC<15> B_BLC<14> B_BLC<13> B_BLC<12> B_BLC<11> B_BLC<10> B_BLC<9> B_BLC<8> B_BLC<7> B_BLC<6> B_BLC<5> B_BLC<4> B_BLC<3> B_BLC<2> B_BLC<1> B_BLC<0> B_BLT<63> B_BLT<62> B_BLT<61> B_BLT<60> B_BLT<59> B_BLT<58> B_BLT<57> B_BLT<56> B_BLT<55> B_BLT<54> B_BLT<53> B_BLT<52> B_BLT<51> B_BLT<50> B_BLT<49> B_BLT<48> B_BLT<47> B_BLT<46> B_BLT<45> B_BLT<44> B_BLT<43> B_BLT<42> B_BLT<41> B_BLT<40> B_BLT<39> B_BLT<38> B_BLT<37> B_BLT<36> B_BLT<35> B_BLT<34> B_BLT<33> B_BLT<32> B_BLT<31> B_BLT<30> B_BLT<29> B_BLT<28> B_BLT<27> B_BLT<26> B_BLT<25> B_BLT<24> B_BLT<23> B_BLT<22> B_BLT<21> B_BLT<20> B_BLT<19> B_BLT<18> B_BLT<17> B_BLT<16> B_BLT<15> B_BLT<14> B_BLT<13> B_BLT<12> B_BLT<11> B_BLT<10> B_BLT<9> B_BLT<8> B_BLT<7> B_BLT<6> B_BLT<5> B_BLT<4> B_BLT<3> B_BLT<2> B_BLT<1> B_BLT<0> B_WL<127> B_WL<126> B_WL<125> B_WL<124> B_WL<123> B_WL<122> B_WL<121> B_WL<120> B_WL<119> B_WL<118> B_WL<117> B_WL<116> B_WL<115> B_WL<114> B_WL<113> B_WL<112> B_WL<111> B_WL<110> B_WL<109> B_WL<108> B_WL<107> B_WL<106> B_WL<105> B_WL<104> B_WL<103> B_WL<102> B_WL<101> B_WL<100> B_WL<99> B_WL<98> B_WL<97> B_WL<96> B_WL<95> B_WL<94> B_WL<93> B_WL<92> B_WL<91> B_WL<90> B_WL<89> B_WL<88> B_WL<87> B_WL<86> B_WL<85> B_WL<84> B_WL<83> B_WL<82> B_WL<81> B_WL<80> B_WL<79> B_WL<78> B_WL<77> B_WL<76> B_WL<75> B_WL<74> B_WL<73> B_WL<72> B_WL<71> B_WL<70> B_WL<69> B_WL<68> B_WL<67> B_WL<66> B_WL<65> B_WL<64> B_WL<63> B_WL<62> B_WL<61> B_WL<60> B_WL<59> B_WL<58> B_WL<57> B_WL<56> B_WL<55> B_WL<54> B_WL<53> B_WL<52> B_WL<51> B_WL<50> B_WL<49> B_WL<48> B_WL<47> B_WL<46> B_WL<45> B_WL<44> B_WL<43> B_WL<42> B_WL<41> B_WL<40> B_WL<39> B_WL<38> B_WL<37> B_WL<36> B_WL<35> B_WL<34> B_WL<33> B_WL<32> B_WL<31> B_WL<30> B_WL<29> B_WL<28> B_WL<27> B_WL<26> B_WL<25> B_WL<24> B_WL<23> B_WL<22> B_WL<21> B_WL<20> B_WL<19> B_WL<18> B_WL<17> B_WL<16> B_WL<15> B_WL<14> B_WL<13> B_WL<12> B_WL<11> B_WL<10> B_WL<9> B_WL<8> B_WL<7> B_WL<6> B_WL<5> B_WL<4> B_WL<3> B_WL<2> B_WL<1> B_WL<0> VDD_CORE VSS +XCORNER<3> VDD_CORE VSS / RM_IHPSG13_512x32_c2_2P_BITKIT_16x2_CORNER +XCORNER<2> VDD_CORE VSS / RM_IHPSG13_512x32_c2_2P_BITKIT_16x2_CORNER +XCORNER<1> VDD_CORE VSS / RM_IHPSG13_512x32_c2_2P_BITKIT_16x2_CORNER +XCORNER<0> VDD_CORE VSS / RM_IHPSG13_512x32_c2_2P_BITKIT_16x2_CORNER +XRAMEDGE_L<7> A_WL<127> A_WL<126> A_WL<125> A_WL<124> A_WL<123> A_WL<122> A_WL<121> A_WL<120> A_WL<119> A_WL<118> A_WL<117> A_WL<116> A_WL<115> A_WL<114> A_WL<113> A_WL<112> B_WL<127> B_WL<126> B_WL<125> B_WL<124> B_WL<123> B_WL<122> B_WL<121> B_WL<120> B_WL<119> B_WL<118> B_WL<117> B_WL<116> B_WL<115> B_WL<114> B_WL<113> B_WL<112> VDD_CORE VSS / RM_IHPSG13_512x32_c2_2P_BITKIT_16x2_EDGE_LR +XRAMEDGE_L<6> A_WL<111> A_WL<110> A_WL<109> A_WL<108> A_WL<107> A_WL<106> A_WL<105> A_WL<104> A_WL<103> A_WL<102> A_WL<101> A_WL<100> A_WL<99> A_WL<98> A_WL<97> A_WL<96> B_WL<111> B_WL<110> B_WL<109> B_WL<108> B_WL<107> B_WL<106> B_WL<105> B_WL<104> B_WL<103> B_WL<102> B_WL<101> B_WL<100> B_WL<99> B_WL<98> B_WL<97> B_WL<96> VDD_CORE VSS / RM_IHPSG13_512x32_c2_2P_BITKIT_16x2_EDGE_LR +XRAMEDGE_L<5> A_WL<95> A_WL<94> A_WL<93> A_WL<92> A_WL<91> A_WL<90> A_WL<89> A_WL<88> A_WL<87> A_WL<86> A_WL<85> A_WL<84> A_WL<83> A_WL<82> A_WL<81> A_WL<80> B_WL<95> B_WL<94> B_WL<93> B_WL<92> B_WL<91> B_WL<90> B_WL<89> B_WL<88> B_WL<87> B_WL<86> B_WL<85> B_WL<84> B_WL<83> B_WL<82> B_WL<81> B_WL<80> VDD_CORE VSS / RM_IHPSG13_512x32_c2_2P_BITKIT_16x2_EDGE_LR +XRAMEDGE_L<4> A_WL<79> A_WL<78> A_WL<77> A_WL<76> A_WL<75> A_WL<74> A_WL<73> A_WL<72> A_WL<71> A_WL<70> A_WL<69> A_WL<68> A_WL<67> A_WL<66> A_WL<65> A_WL<64> B_WL<79> B_WL<78> B_WL<77> B_WL<76> B_WL<75> B_WL<74> B_WL<73> B_WL<72> B_WL<71> B_WL<70> B_WL<69> B_WL<68> B_WL<67> B_WL<66> B_WL<65> B_WL<64> VDD_CORE VSS / RM_IHPSG13_512x32_c2_2P_BITKIT_16x2_EDGE_LR +XRAMEDGE_L<3> A_WL<63> A_WL<62> A_WL<61> A_WL<60> A_WL<59> A_WL<58> A_WL<57> A_WL<56> A_WL<55> A_WL<54> A_WL<53> A_WL<52> A_WL<51> A_WL<50> A_WL<49> A_WL<48> B_WL<63> B_WL<62> B_WL<61> B_WL<60> B_WL<59> B_WL<58> B_WL<57> B_WL<56> B_WL<55> B_WL<54> B_WL<53> B_WL<52> B_WL<51> B_WL<50> B_WL<49> B_WL<48> VDD_CORE VSS / RM_IHPSG13_512x32_c2_2P_BITKIT_16x2_EDGE_LR +XRAMEDGE_L<2> A_WL<47> A_WL<46> A_WL<45> A_WL<44> A_WL<43> A_WL<42> A_WL<41> A_WL<40> A_WL<39> A_WL<38> A_WL<37> A_WL<36> A_WL<35> A_WL<34> A_WL<33> A_WL<32> B_WL<47> B_WL<46> B_WL<45> B_WL<44> B_WL<43> B_WL<42> B_WL<41> B_WL<40> B_WL<39> B_WL<38> B_WL<37> B_WL<36> B_WL<35> B_WL<34> B_WL<33> B_WL<32> VDD_CORE VSS / RM_IHPSG13_512x32_c2_2P_BITKIT_16x2_EDGE_LR +XRAMEDGE_L<1> A_WL<31> A_WL<30> A_WL<29> A_WL<28> A_WL<27> A_WL<26> A_WL<25> A_WL<24> A_WL<23> A_WL<22> A_WL<21> A_WL<20> A_WL<19> A_WL<18> A_WL<17> A_WL<16> B_WL<31> B_WL<30> B_WL<29> B_WL<28> B_WL<27> B_WL<26> B_WL<25> B_WL<24> B_WL<23> B_WL<22> B_WL<21> B_WL<20> B_WL<19> B_WL<18> B_WL<17> B_WL<16> VDD_CORE VSS / RM_IHPSG13_512x32_c2_2P_BITKIT_16x2_EDGE_LR +XRAMEDGE_L<0> A_WL<15> A_WL<14> A_WL<13> A_WL<12> A_WL<11> A_WL<10> A_WL<9> A_WL<8> A_WL<7> A_WL<6> A_WL<5> A_WL<4> A_WL<3> A_WL<2> A_WL<1> A_WL<0> B_WL<15> B_WL<14> B_WL<13> B_WL<12> B_WL<11> B_WL<10> B_WL<9> B_WL<8> B_WL<7> B_WL<6> B_WL<5> B_WL<4> B_WL<3> B_WL<2> B_WL<1> B_WL<0> VDD_CORE VSS / RM_IHPSG13_512x32_c2_2P_BITKIT_16x2_EDGE_LR +XRAMEDGE_R<7> A_IWL<4095> A_IWL<4094> A_IWL<4093> A_IWL<4092> A_IWL<4091> A_IWL<4090> A_IWL<4089> A_IWL<4088> A_IWL<4087> A_IWL<4086> A_IWL<4085> A_IWL<4084> A_IWL<4083> A_IWL<4082> A_IWL<4081> A_IWL<4080> B_IWL<4095> B_IWL<4094> B_IWL<4093> B_IWL<4092> B_IWL<4091> B_IWL<4090> B_IWL<4089> B_IWL<4088> B_IWL<4087> B_IWL<4086> B_IWL<4085> B_IWL<4084> B_IWL<4083> B_IWL<4082> B_IWL<4081> B_IWL<4080> VDD_CORE VSS / RM_IHPSG13_512x32_c2_2P_BITKIT_16x2_EDGE_LR +XRAMEDGE_R<6> A_IWL<4079> A_IWL<4078> A_IWL<4077> A_IWL<4076> A_IWL<4075> A_IWL<4074> A_IWL<4073> A_IWL<4072> A_IWL<4071> A_IWL<4070> A_IWL<4069> A_IWL<4068> A_IWL<4067> A_IWL<4066> A_IWL<4065> A_IWL<4064> B_IWL<4079> B_IWL<4078> B_IWL<4077> B_IWL<4076> B_IWL<4075> B_IWL<4074> B_IWL<4073> B_IWL<4072> B_IWL<4071> B_IWL<4070> B_IWL<4069> B_IWL<4068> B_IWL<4067> B_IWL<4066> B_IWL<4065> B_IWL<4064> VDD_CORE VSS / RM_IHPSG13_512x32_c2_2P_BITKIT_16x2_EDGE_LR +XRAMEDGE_R<5> A_IWL<4063> A_IWL<4062> A_IWL<4061> A_IWL<4060> A_IWL<4059> A_IWL<4058> A_IWL<4057> A_IWL<4056> A_IWL<4055> A_IWL<4054> A_IWL<4053> A_IWL<4052> A_IWL<4051> A_IWL<4050> A_IWL<4049> A_IWL<4048> B_IWL<4063> B_IWL<4062> B_IWL<4061> B_IWL<4060> B_IWL<4059> B_IWL<4058> B_IWL<4057> B_IWL<4056> B_IWL<4055> B_IWL<4054> B_IWL<4053> B_IWL<4052> B_IWL<4051> B_IWL<4050> B_IWL<4049> B_IWL<4048> VDD_CORE VSS / RM_IHPSG13_512x32_c2_2P_BITKIT_16x2_EDGE_LR +XRAMEDGE_R<4> A_IWL<4047> A_IWL<4046> A_IWL<4045> A_IWL<4044> A_IWL<4043> A_IWL<4042> A_IWL<4041> A_IWL<4040> A_IWL<4039> A_IWL<4038> A_IWL<4037> A_IWL<4036> A_IWL<4035> A_IWL<4034> A_IWL<4033> A_IWL<4032> B_IWL<4047> B_IWL<4046> B_IWL<4045> B_IWL<4044> B_IWL<4043> B_IWL<4042> B_IWL<4041> B_IWL<4040> B_IWL<4039> B_IWL<4038> B_IWL<4037> B_IWL<4036> B_IWL<4035> B_IWL<4034> B_IWL<4033> B_IWL<4032> VDD_CORE VSS / RM_IHPSG13_512x32_c2_2P_BITKIT_16x2_EDGE_LR +XRAMEDGE_R<3> A_IWL<4031> A_IWL<4030> A_IWL<4029> A_IWL<4028> A_IWL<4027> A_IWL<4026> A_IWL<4025> A_IWL<4024> A_IWL<4023> A_IWL<4022> A_IWL<4021> A_IWL<4020> A_IWL<4019> A_IWL<4018> A_IWL<4017> A_IWL<4016> B_IWL<4031> B_IWL<4030> B_IWL<4029> B_IWL<4028> B_IWL<4027> B_IWL<4026> B_IWL<4025> B_IWL<4024> B_IWL<4023> B_IWL<4022> B_IWL<4021> B_IWL<4020> B_IWL<4019> B_IWL<4018> B_IWL<4017> B_IWL<4016> VDD_CORE VSS / RM_IHPSG13_512x32_c2_2P_BITKIT_16x2_EDGE_LR +XRAMEDGE_R<2> A_IWL<4015> A_IWL<4014> A_IWL<4013> A_IWL<4012> A_IWL<4011> A_IWL<4010> A_IWL<4009> A_IWL<4008> A_IWL<4007> A_IWL<4006> A_IWL<4005> A_IWL<4004> A_IWL<4003> A_IWL<4002> A_IWL<4001> A_IWL<4000> B_IWL<4015> B_IWL<4014> B_IWL<4013> B_IWL<4012> B_IWL<4011> B_IWL<4010> B_IWL<4009> B_IWL<4008> B_IWL<4007> B_IWL<4006> B_IWL<4005> B_IWL<4004> B_IWL<4003> B_IWL<4002> B_IWL<4001> B_IWL<4000> VDD_CORE VSS / RM_IHPSG13_512x32_c2_2P_BITKIT_16x2_EDGE_LR +XRAMEDGE_R<1> A_IWL<3999> A_IWL<3998> A_IWL<3997> A_IWL<3996> A_IWL<3995> A_IWL<3994> A_IWL<3993> A_IWL<3992> A_IWL<3991> A_IWL<3990> A_IWL<3989> A_IWL<3988> A_IWL<3987> A_IWL<3986> A_IWL<3985> A_IWL<3984> B_IWL<3999> B_IWL<3998> B_IWL<3997> B_IWL<3996> B_IWL<3995> B_IWL<3994> B_IWL<3993> B_IWL<3992> B_IWL<3991> B_IWL<3990> B_IWL<3989> B_IWL<3988> B_IWL<3987> B_IWL<3986> B_IWL<3985> B_IWL<3984> VDD_CORE VSS / RM_IHPSG13_512x32_c2_2P_BITKIT_16x2_EDGE_LR +XRAMEDGE_R<0> A_IWL<3983> A_IWL<3982> A_IWL<3981> A_IWL<3980> A_IWL<3979> A_IWL<3978> A_IWL<3977> A_IWL<3976> A_IWL<3975> A_IWL<3974> A_IWL<3973> A_IWL<3972> A_IWL<3971> A_IWL<3970> A_IWL<3969> A_IWL<3968> B_IWL<3983> B_IWL<3982> B_IWL<3981> B_IWL<3980> B_IWL<3979> B_IWL<3978> B_IWL<3977> B_IWL<3976> B_IWL<3975> B_IWL<3974> B_IWL<3973> B_IWL<3972> B_IWL<3971> B_IWL<3970> B_IWL<3969> B_IWL<3968> VDD_CORE VSS / RM_IHPSG13_512x32_c2_2P_BITKIT_16x2_EDGE_LR +XCOL<31> A_BLC<63> A_BLC<62> A_BLC_TOP<63> A_BLC_TOP<62> A_BLT<63> A_BLT<62> A_BLT_TOP<63> A_BLT_TOP<62> A_IWL<3967> A_IWL<3966> A_IWL<3965> A_IWL<3964> A_IWL<3963> A_IWL<3962> A_IWL<3961> A_IWL<3960> A_IWL<3959> A_IWL<3958> A_IWL<3957> A_IWL<3956> A_IWL<3955> A_IWL<3954> A_IWL<3953> A_IWL<3952> A_IWL<3951> A_IWL<3950> A_IWL<3949> A_IWL<3948> A_IWL<3947> A_IWL<3946> A_IWL<3945> A_IWL<3944> A_IWL<3943> A_IWL<3942> A_IWL<3941> A_IWL<3940> A_IWL<3939> A_IWL<3938> A_IWL<3937> A_IWL<3936> A_IWL<3935> A_IWL<3934> A_IWL<3933> A_IWL<3932> A_IWL<3931> A_IWL<3930> A_IWL<3929> A_IWL<3928> A_IWL<3927> A_IWL<3926> A_IWL<3925> A_IWL<3924> A_IWL<3923> A_IWL<3922> A_IWL<3921> A_IWL<3920> A_IWL<3919> A_IWL<3918> A_IWL<3917> A_IWL<3916> A_IWL<3915> A_IWL<3914> A_IWL<3913> A_IWL<3912> A_IWL<3911> A_IWL<3910> A_IWL<3909> A_IWL<3908> A_IWL<3907> A_IWL<3906> A_IWL<3905> A_IWL<3904> A_IWL<3903> A_IWL<3902> A_IWL<3901> A_IWL<3900> A_IWL<3899> A_IWL<3898> A_IWL<3897> A_IWL<3896> A_IWL<3895> A_IWL<3894> A_IWL<3893> A_IWL<3892> A_IWL<3891> A_IWL<3890> A_IWL<3889> A_IWL<3888> A_IWL<3887> A_IWL<3886> A_IWL<3885> A_IWL<3884> A_IWL<3883> A_IWL<3882> A_IWL<3881> A_IWL<3880> A_IWL<3879> A_IWL<3878> A_IWL<3877> A_IWL<3876> A_IWL<3875> A_IWL<3874> A_IWL<3873> A_IWL<3872> A_IWL<3871> A_IWL<3870> A_IWL<3869> A_IWL<3868> A_IWL<3867> A_IWL<3866> A_IWL<3865> A_IWL<3864> A_IWL<3863> A_IWL<3862> A_IWL<3861> A_IWL<3860> A_IWL<3859> A_IWL<3858> A_IWL<3857> A_IWL<3856> A_IWL<3855> A_IWL<3854> A_IWL<3853> A_IWL<3852> A_IWL<3851> A_IWL<3850> A_IWL<3849> A_IWL<3848> A_IWL<3847> A_IWL<3846> A_IWL<3845> A_IWL<3844> A_IWL<3843> A_IWL<3842> A_IWL<3841> A_IWL<3840> A_IWL<4095> A_IWL<4094> A_IWL<4093> A_IWL<4092> A_IWL<4091> A_IWL<4090> A_IWL<4089> A_IWL<4088> A_IWL<4087> A_IWL<4086> A_IWL<4085> A_IWL<4084> A_IWL<4083> A_IWL<4082> A_IWL<4081> A_IWL<4080> A_IWL<4079> A_IWL<4078> A_IWL<4077> A_IWL<4076> A_IWL<4075> A_IWL<4074> A_IWL<4073> A_IWL<4072> A_IWL<4071> A_IWL<4070> A_IWL<4069> A_IWL<4068> A_IWL<4067> A_IWL<4066> A_IWL<4065> A_IWL<4064> A_IWL<4063> A_IWL<4062> A_IWL<4061> A_IWL<4060> A_IWL<4059> A_IWL<4058> A_IWL<4057> A_IWL<4056> A_IWL<4055> A_IWL<4054> A_IWL<4053> A_IWL<4052> A_IWL<4051> A_IWL<4050> A_IWL<4049> A_IWL<4048> A_IWL<4047> A_IWL<4046> A_IWL<4045> A_IWL<4044> A_IWL<4043> A_IWL<4042> A_IWL<4041> A_IWL<4040> A_IWL<4039> A_IWL<4038> A_IWL<4037> A_IWL<4036> A_IWL<4035> A_IWL<4034> A_IWL<4033> A_IWL<4032> A_IWL<4031> A_IWL<4030> A_IWL<4029> A_IWL<4028> A_IWL<4027> A_IWL<4026> A_IWL<4025> A_IWL<4024> A_IWL<4023> A_IWL<4022> A_IWL<4021> A_IWL<4020> A_IWL<4019> A_IWL<4018> A_IWL<4017> A_IWL<4016> A_IWL<4015> A_IWL<4014> A_IWL<4013> A_IWL<4012> A_IWL<4011> A_IWL<4010> A_IWL<4009> A_IWL<4008> A_IWL<4007> A_IWL<4006> A_IWL<4005> A_IWL<4004> A_IWL<4003> A_IWL<4002> A_IWL<4001> A_IWL<4000> A_IWL<3999> A_IWL<3998> A_IWL<3997> A_IWL<3996> A_IWL<3995> A_IWL<3994> A_IWL<3993> A_IWL<3992> A_IWL<3991> A_IWL<3990> A_IWL<3989> A_IWL<3988> A_IWL<3987> A_IWL<3986> A_IWL<3985> A_IWL<3984> A_IWL<3983> A_IWL<3982> A_IWL<3981> A_IWL<3980> A_IWL<3979> A_IWL<3978> A_IWL<3977> A_IWL<3976> A_IWL<3975> A_IWL<3974> A_IWL<3973> A_IWL<3972> A_IWL<3971> A_IWL<3970> A_IWL<3969> A_IWL<3968> B_BLC<63> B_BLC<62> B_BLC_TOP<63> B_BLC_TOP<62> B_BLT<63> B_BLT<62> B_BLT_TOP<63> B_BLT_TOP<62> B_IWL<3967> B_IWL<3966> B_IWL<3965> B_IWL<3964> B_IWL<3963> B_IWL<3962> B_IWL<3961> B_IWL<3960> B_IWL<3959> B_IWL<3958> B_IWL<3957> B_IWL<3956> B_IWL<3955> B_IWL<3954> B_IWL<3953> B_IWL<3952> B_IWL<3951> B_IWL<3950> B_IWL<3949> B_IWL<3948> B_IWL<3947> B_IWL<3946> B_IWL<3945> B_IWL<3944> B_IWL<3943> B_IWL<3942> B_IWL<3941> B_IWL<3940> B_IWL<3939> B_IWL<3938> B_IWL<3937> B_IWL<3936> B_IWL<3935> B_IWL<3934> B_IWL<3933> B_IWL<3932> B_IWL<3931> B_IWL<3930> B_IWL<3929> B_IWL<3928> B_IWL<3927> B_IWL<3926> B_IWL<3925> B_IWL<3924> B_IWL<3923> B_IWL<3922> B_IWL<3921> B_IWL<3920> B_IWL<3919> B_IWL<3918> B_IWL<3917> B_IWL<3916> B_IWL<3915> B_IWL<3914> B_IWL<3913> B_IWL<3912> B_IWL<3911> B_IWL<3910> B_IWL<3909> B_IWL<3908> B_IWL<3907> B_IWL<3906> B_IWL<3905> B_IWL<3904> B_IWL<3903> B_IWL<3902> B_IWL<3901> B_IWL<3900> B_IWL<3899> B_IWL<3898> B_IWL<3897> B_IWL<3896> B_IWL<3895> B_IWL<3894> B_IWL<3893> B_IWL<3892> B_IWL<3891> B_IWL<3890> B_IWL<3889> B_IWL<3888> B_IWL<3887> B_IWL<3886> B_IWL<3885> B_IWL<3884> B_IWL<3883> B_IWL<3882> B_IWL<3881> B_IWL<3880> B_IWL<3879> B_IWL<3878> B_IWL<3877> B_IWL<3876> B_IWL<3875> B_IWL<3874> B_IWL<3873> B_IWL<3872> B_IWL<3871> B_IWL<3870> B_IWL<3869> B_IWL<3868> B_IWL<3867> B_IWL<3866> B_IWL<3865> B_IWL<3864> B_IWL<3863> B_IWL<3862> B_IWL<3861> B_IWL<3860> B_IWL<3859> B_IWL<3858> B_IWL<3857> B_IWL<3856> B_IWL<3855> B_IWL<3854> B_IWL<3853> B_IWL<3852> B_IWL<3851> B_IWL<3850> B_IWL<3849> B_IWL<3848> B_IWL<3847> B_IWL<3846> B_IWL<3845> B_IWL<3844> B_IWL<3843> B_IWL<3842> B_IWL<3841> B_IWL<3840> B_IWL<4095> B_IWL<4094> B_IWL<4093> B_IWL<4092> B_IWL<4091> B_IWL<4090> B_IWL<4089> B_IWL<4088> B_IWL<4087> B_IWL<4086> B_IWL<4085> B_IWL<4084> B_IWL<4083> B_IWL<4082> B_IWL<4081> B_IWL<4080> B_IWL<4079> B_IWL<4078> B_IWL<4077> B_IWL<4076> B_IWL<4075> B_IWL<4074> B_IWL<4073> B_IWL<4072> B_IWL<4071> B_IWL<4070> B_IWL<4069> B_IWL<4068> B_IWL<4067> B_IWL<4066> B_IWL<4065> B_IWL<4064> B_IWL<4063> B_IWL<4062> B_IWL<4061> B_IWL<4060> B_IWL<4059> B_IWL<4058> B_IWL<4057> B_IWL<4056> B_IWL<4055> B_IWL<4054> B_IWL<4053> B_IWL<4052> B_IWL<4051> B_IWL<4050> B_IWL<4049> B_IWL<4048> B_IWL<4047> B_IWL<4046> B_IWL<4045> B_IWL<4044> B_IWL<4043> B_IWL<4042> B_IWL<4041> B_IWL<4040> B_IWL<4039> B_IWL<4038> B_IWL<4037> B_IWL<4036> B_IWL<4035> B_IWL<4034> B_IWL<4033> B_IWL<4032> B_IWL<4031> B_IWL<4030> B_IWL<4029> B_IWL<4028> B_IWL<4027> B_IWL<4026> B_IWL<4025> B_IWL<4024> B_IWL<4023> B_IWL<4022> B_IWL<4021> B_IWL<4020> B_IWL<4019> B_IWL<4018> B_IWL<4017> B_IWL<4016> B_IWL<4015> B_IWL<4014> B_IWL<4013> B_IWL<4012> B_IWL<4011> B_IWL<4010> B_IWL<4009> B_IWL<4008> B_IWL<4007> B_IWL<4006> B_IWL<4005> B_IWL<4004> B_IWL<4003> B_IWL<4002> B_IWL<4001> B_IWL<4000> B_IWL<3999> B_IWL<3998> B_IWL<3997> B_IWL<3996> B_IWL<3995> B_IWL<3994> B_IWL<3993> B_IWL<3992> B_IWL<3991> B_IWL<3990> B_IWL<3989> B_IWL<3988> B_IWL<3987> B_IWL<3986> B_IWL<3985> B_IWL<3984> B_IWL<3983> B_IWL<3982> B_IWL<3981> B_IWL<3980> B_IWL<3979> B_IWL<3978> B_IWL<3977> B_IWL<3976> B_IWL<3975> B_IWL<3974> B_IWL<3973> B_IWL<3972> B_IWL<3971> B_IWL<3970> B_IWL<3969> B_IWL<3968> VDD_CORE VSS / RM_IHPSG13_512x32_c2_2P_COLUMN_pcell_0 +XCOL<30> A_BLC<61> A_BLC<60> A_BLC_TOP<61> A_BLC_TOP<60> A_BLT<61> A_BLT<60> A_BLT_TOP<61> A_BLT_TOP<60> A_IWL<3839> A_IWL<3838> A_IWL<3837> A_IWL<3836> A_IWL<3835> A_IWL<3834> A_IWL<3833> A_IWL<3832> A_IWL<3831> A_IWL<3830> A_IWL<3829> A_IWL<3828> A_IWL<3827> A_IWL<3826> A_IWL<3825> A_IWL<3824> A_IWL<3823> A_IWL<3822> A_IWL<3821> A_IWL<3820> A_IWL<3819> A_IWL<3818> A_IWL<3817> A_IWL<3816> A_IWL<3815> A_IWL<3814> A_IWL<3813> A_IWL<3812> A_IWL<3811> A_IWL<3810> A_IWL<3809> A_IWL<3808> A_IWL<3807> A_IWL<3806> A_IWL<3805> A_IWL<3804> A_IWL<3803> A_IWL<3802> A_IWL<3801> A_IWL<3800> A_IWL<3799> A_IWL<3798> A_IWL<3797> A_IWL<3796> A_IWL<3795> A_IWL<3794> A_IWL<3793> A_IWL<3792> A_IWL<3791> A_IWL<3790> A_IWL<3789> A_IWL<3788> A_IWL<3787> A_IWL<3786> A_IWL<3785> A_IWL<3784> A_IWL<3783> A_IWL<3782> A_IWL<3781> A_IWL<3780> A_IWL<3779> A_IWL<3778> A_IWL<3777> A_IWL<3776> A_IWL<3775> A_IWL<3774> A_IWL<3773> A_IWL<3772> A_IWL<3771> A_IWL<3770> A_IWL<3769> A_IWL<3768> A_IWL<3767> A_IWL<3766> A_IWL<3765> A_IWL<3764> A_IWL<3763> A_IWL<3762> A_IWL<3761> A_IWL<3760> A_IWL<3759> A_IWL<3758> A_IWL<3757> A_IWL<3756> A_IWL<3755> A_IWL<3754> A_IWL<3753> A_IWL<3752> A_IWL<3751> A_IWL<3750> A_IWL<3749> A_IWL<3748> A_IWL<3747> A_IWL<3746> A_IWL<3745> A_IWL<3744> A_IWL<3743> A_IWL<3742> A_IWL<3741> A_IWL<3740> A_IWL<3739> A_IWL<3738> A_IWL<3737> A_IWL<3736> A_IWL<3735> A_IWL<3734> A_IWL<3733> A_IWL<3732> A_IWL<3731> A_IWL<3730> A_IWL<3729> A_IWL<3728> A_IWL<3727> A_IWL<3726> A_IWL<3725> A_IWL<3724> A_IWL<3723> A_IWL<3722> A_IWL<3721> A_IWL<3720> A_IWL<3719> A_IWL<3718> A_IWL<3717> A_IWL<3716> A_IWL<3715> A_IWL<3714> A_IWL<3713> A_IWL<3712> A_IWL<3967> A_IWL<3966> A_IWL<3965> A_IWL<3964> A_IWL<3963> A_IWL<3962> A_IWL<3961> A_IWL<3960> A_IWL<3959> A_IWL<3958> A_IWL<3957> A_IWL<3956> A_IWL<3955> A_IWL<3954> A_IWL<3953> A_IWL<3952> A_IWL<3951> A_IWL<3950> A_IWL<3949> A_IWL<3948> A_IWL<3947> A_IWL<3946> A_IWL<3945> A_IWL<3944> A_IWL<3943> A_IWL<3942> A_IWL<3941> A_IWL<3940> A_IWL<3939> A_IWL<3938> A_IWL<3937> A_IWL<3936> A_IWL<3935> A_IWL<3934> A_IWL<3933> A_IWL<3932> A_IWL<3931> A_IWL<3930> A_IWL<3929> A_IWL<3928> A_IWL<3927> A_IWL<3926> A_IWL<3925> A_IWL<3924> A_IWL<3923> A_IWL<3922> A_IWL<3921> A_IWL<3920> A_IWL<3919> A_IWL<3918> A_IWL<3917> A_IWL<3916> A_IWL<3915> A_IWL<3914> A_IWL<3913> A_IWL<3912> A_IWL<3911> A_IWL<3910> A_IWL<3909> A_IWL<3908> A_IWL<3907> A_IWL<3906> A_IWL<3905> A_IWL<3904> A_IWL<3903> A_IWL<3902> A_IWL<3901> A_IWL<3900> A_IWL<3899> A_IWL<3898> A_IWL<3897> A_IWL<3896> A_IWL<3895> A_IWL<3894> A_IWL<3893> A_IWL<3892> A_IWL<3891> A_IWL<3890> A_IWL<3889> A_IWL<3888> A_IWL<3887> A_IWL<3886> A_IWL<3885> A_IWL<3884> A_IWL<3883> A_IWL<3882> A_IWL<3881> A_IWL<3880> A_IWL<3879> A_IWL<3878> A_IWL<3877> A_IWL<3876> A_IWL<3875> A_IWL<3874> A_IWL<3873> A_IWL<3872> A_IWL<3871> A_IWL<3870> A_IWL<3869> A_IWL<3868> A_IWL<3867> A_IWL<3866> A_IWL<3865> A_IWL<3864> A_IWL<3863> A_IWL<3862> A_IWL<3861> A_IWL<3860> A_IWL<3859> A_IWL<3858> A_IWL<3857> A_IWL<3856> A_IWL<3855> A_IWL<3854> A_IWL<3853> A_IWL<3852> A_IWL<3851> A_IWL<3850> A_IWL<3849> A_IWL<3848> A_IWL<3847> A_IWL<3846> A_IWL<3845> A_IWL<3844> A_IWL<3843> A_IWL<3842> A_IWL<3841> A_IWL<3840> B_BLC<61> B_BLC<60> B_BLC_TOP<61> B_BLC_TOP<60> B_BLT<61> B_BLT<60> B_BLT_TOP<61> B_BLT_TOP<60> B_IWL<3839> B_IWL<3838> B_IWL<3837> B_IWL<3836> B_IWL<3835> B_IWL<3834> B_IWL<3833> B_IWL<3832> B_IWL<3831> B_IWL<3830> B_IWL<3829> B_IWL<3828> B_IWL<3827> B_IWL<3826> B_IWL<3825> B_IWL<3824> B_IWL<3823> B_IWL<3822> B_IWL<3821> B_IWL<3820> B_IWL<3819> B_IWL<3818> B_IWL<3817> B_IWL<3816> B_IWL<3815> B_IWL<3814> B_IWL<3813> B_IWL<3812> B_IWL<3811> B_IWL<3810> B_IWL<3809> B_IWL<3808> B_IWL<3807> B_IWL<3806> B_IWL<3805> B_IWL<3804> B_IWL<3803> B_IWL<3802> B_IWL<3801> B_IWL<3800> B_IWL<3799> B_IWL<3798> B_IWL<3797> B_IWL<3796> B_IWL<3795> B_IWL<3794> B_IWL<3793> B_IWL<3792> B_IWL<3791> B_IWL<3790> B_IWL<3789> B_IWL<3788> B_IWL<3787> B_IWL<3786> B_IWL<3785> B_IWL<3784> B_IWL<3783> B_IWL<3782> B_IWL<3781> B_IWL<3780> B_IWL<3779> B_IWL<3778> B_IWL<3777> B_IWL<3776> B_IWL<3775> B_IWL<3774> B_IWL<3773> B_IWL<3772> B_IWL<3771> B_IWL<3770> B_IWL<3769> B_IWL<3768> B_IWL<3767> B_IWL<3766> B_IWL<3765> B_IWL<3764> B_IWL<3763> B_IWL<3762> B_IWL<3761> B_IWL<3760> B_IWL<3759> B_IWL<3758> B_IWL<3757> B_IWL<3756> B_IWL<3755> B_IWL<3754> B_IWL<3753> B_IWL<3752> B_IWL<3751> B_IWL<3750> B_IWL<3749> B_IWL<3748> B_IWL<3747> B_IWL<3746> B_IWL<3745> B_IWL<3744> B_IWL<3743> B_IWL<3742> B_IWL<3741> B_IWL<3740> B_IWL<3739> B_IWL<3738> B_IWL<3737> B_IWL<3736> B_IWL<3735> B_IWL<3734> B_IWL<3733> B_IWL<3732> B_IWL<3731> B_IWL<3730> B_IWL<3729> B_IWL<3728> B_IWL<3727> B_IWL<3726> B_IWL<3725> B_IWL<3724> B_IWL<3723> B_IWL<3722> B_IWL<3721> B_IWL<3720> B_IWL<3719> B_IWL<3718> B_IWL<3717> B_IWL<3716> B_IWL<3715> B_IWL<3714> B_IWL<3713> B_IWL<3712> B_IWL<3967> B_IWL<3966> B_IWL<3965> B_IWL<3964> B_IWL<3963> B_IWL<3962> B_IWL<3961> B_IWL<3960> B_IWL<3959> B_IWL<3958> B_IWL<3957> B_IWL<3956> B_IWL<3955> B_IWL<3954> B_IWL<3953> B_IWL<3952> B_IWL<3951> B_IWL<3950> B_IWL<3949> B_IWL<3948> B_IWL<3947> B_IWL<3946> B_IWL<3945> B_IWL<3944> B_IWL<3943> B_IWL<3942> B_IWL<3941> B_IWL<3940> B_IWL<3939> B_IWL<3938> B_IWL<3937> B_IWL<3936> B_IWL<3935> B_IWL<3934> B_IWL<3933> B_IWL<3932> B_IWL<3931> B_IWL<3930> B_IWL<3929> B_IWL<3928> B_IWL<3927> B_IWL<3926> B_IWL<3925> B_IWL<3924> B_IWL<3923> B_IWL<3922> B_IWL<3921> B_IWL<3920> B_IWL<3919> B_IWL<3918> B_IWL<3917> B_IWL<3916> B_IWL<3915> B_IWL<3914> B_IWL<3913> B_IWL<3912> B_IWL<3911> B_IWL<3910> B_IWL<3909> B_IWL<3908> B_IWL<3907> B_IWL<3906> B_IWL<3905> B_IWL<3904> B_IWL<3903> B_IWL<3902> B_IWL<3901> B_IWL<3900> B_IWL<3899> B_IWL<3898> B_IWL<3897> B_IWL<3896> B_IWL<3895> B_IWL<3894> B_IWL<3893> B_IWL<3892> B_IWL<3891> B_IWL<3890> B_IWL<3889> B_IWL<3888> B_IWL<3887> B_IWL<3886> B_IWL<3885> B_IWL<3884> B_IWL<3883> B_IWL<3882> B_IWL<3881> B_IWL<3880> B_IWL<3879> B_IWL<3878> B_IWL<3877> B_IWL<3876> B_IWL<3875> B_IWL<3874> B_IWL<3873> B_IWL<3872> B_IWL<3871> B_IWL<3870> B_IWL<3869> B_IWL<3868> B_IWL<3867> B_IWL<3866> B_IWL<3865> B_IWL<3864> B_IWL<3863> B_IWL<3862> B_IWL<3861> B_IWL<3860> B_IWL<3859> B_IWL<3858> B_IWL<3857> B_IWL<3856> B_IWL<3855> B_IWL<3854> B_IWL<3853> B_IWL<3852> B_IWL<3851> B_IWL<3850> B_IWL<3849> B_IWL<3848> B_IWL<3847> B_IWL<3846> B_IWL<3845> B_IWL<3844> B_IWL<3843> B_IWL<3842> B_IWL<3841> B_IWL<3840> VDD_CORE VSS / RM_IHPSG13_512x32_c2_2P_COLUMN_pcell_0 +XCOL<29> A_BLC<59> A_BLC<58> A_BLC_TOP<59> A_BLC_TOP<58> A_BLT<59> A_BLT<58> A_BLT_TOP<59> A_BLT_TOP<58> A_IWL<3711> A_IWL<3710> A_IWL<3709> A_IWL<3708> A_IWL<3707> A_IWL<3706> A_IWL<3705> A_IWL<3704> A_IWL<3703> A_IWL<3702> A_IWL<3701> A_IWL<3700> A_IWL<3699> A_IWL<3698> A_IWL<3697> A_IWL<3696> A_IWL<3695> A_IWL<3694> A_IWL<3693> A_IWL<3692> A_IWL<3691> A_IWL<3690> A_IWL<3689> A_IWL<3688> A_IWL<3687> A_IWL<3686> A_IWL<3685> A_IWL<3684> A_IWL<3683> A_IWL<3682> A_IWL<3681> A_IWL<3680> A_IWL<3679> A_IWL<3678> A_IWL<3677> A_IWL<3676> A_IWL<3675> A_IWL<3674> A_IWL<3673> A_IWL<3672> A_IWL<3671> A_IWL<3670> A_IWL<3669> A_IWL<3668> A_IWL<3667> A_IWL<3666> A_IWL<3665> A_IWL<3664> A_IWL<3663> A_IWL<3662> A_IWL<3661> A_IWL<3660> A_IWL<3659> A_IWL<3658> A_IWL<3657> A_IWL<3656> A_IWL<3655> A_IWL<3654> A_IWL<3653> A_IWL<3652> A_IWL<3651> A_IWL<3650> A_IWL<3649> A_IWL<3648> A_IWL<3647> A_IWL<3646> A_IWL<3645> A_IWL<3644> A_IWL<3643> A_IWL<3642> A_IWL<3641> A_IWL<3640> A_IWL<3639> A_IWL<3638> A_IWL<3637> A_IWL<3636> A_IWL<3635> A_IWL<3634> A_IWL<3633> A_IWL<3632> A_IWL<3631> A_IWL<3630> A_IWL<3629> A_IWL<3628> A_IWL<3627> A_IWL<3626> A_IWL<3625> A_IWL<3624> A_IWL<3623> A_IWL<3622> A_IWL<3621> A_IWL<3620> A_IWL<3619> A_IWL<3618> A_IWL<3617> A_IWL<3616> A_IWL<3615> A_IWL<3614> A_IWL<3613> A_IWL<3612> A_IWL<3611> A_IWL<3610> A_IWL<3609> A_IWL<3608> A_IWL<3607> A_IWL<3606> A_IWL<3605> A_IWL<3604> A_IWL<3603> A_IWL<3602> A_IWL<3601> A_IWL<3600> A_IWL<3599> A_IWL<3598> A_IWL<3597> A_IWL<3596> A_IWL<3595> A_IWL<3594> A_IWL<3593> A_IWL<3592> A_IWL<3591> A_IWL<3590> A_IWL<3589> A_IWL<3588> A_IWL<3587> A_IWL<3586> A_IWL<3585> A_IWL<3584> A_IWL<3839> A_IWL<3838> A_IWL<3837> A_IWL<3836> A_IWL<3835> A_IWL<3834> A_IWL<3833> A_IWL<3832> A_IWL<3831> A_IWL<3830> A_IWL<3829> A_IWL<3828> A_IWL<3827> A_IWL<3826> A_IWL<3825> A_IWL<3824> A_IWL<3823> A_IWL<3822> A_IWL<3821> A_IWL<3820> A_IWL<3819> A_IWL<3818> A_IWL<3817> A_IWL<3816> A_IWL<3815> A_IWL<3814> A_IWL<3813> A_IWL<3812> A_IWL<3811> A_IWL<3810> A_IWL<3809> A_IWL<3808> A_IWL<3807> A_IWL<3806> A_IWL<3805> A_IWL<3804> A_IWL<3803> A_IWL<3802> A_IWL<3801> A_IWL<3800> A_IWL<3799> A_IWL<3798> A_IWL<3797> A_IWL<3796> A_IWL<3795> A_IWL<3794> A_IWL<3793> A_IWL<3792> A_IWL<3791> A_IWL<3790> A_IWL<3789> A_IWL<3788> A_IWL<3787> A_IWL<3786> A_IWL<3785> A_IWL<3784> A_IWL<3783> A_IWL<3782> A_IWL<3781> A_IWL<3780> A_IWL<3779> A_IWL<3778> A_IWL<3777> A_IWL<3776> A_IWL<3775> A_IWL<3774> A_IWL<3773> A_IWL<3772> A_IWL<3771> A_IWL<3770> A_IWL<3769> A_IWL<3768> A_IWL<3767> A_IWL<3766> A_IWL<3765> A_IWL<3764> A_IWL<3763> A_IWL<3762> A_IWL<3761> A_IWL<3760> A_IWL<3759> A_IWL<3758> A_IWL<3757> A_IWL<3756> A_IWL<3755> A_IWL<3754> A_IWL<3753> A_IWL<3752> A_IWL<3751> A_IWL<3750> A_IWL<3749> A_IWL<3748> A_IWL<3747> A_IWL<3746> A_IWL<3745> A_IWL<3744> A_IWL<3743> A_IWL<3742> A_IWL<3741> A_IWL<3740> A_IWL<3739> A_IWL<3738> A_IWL<3737> A_IWL<3736> A_IWL<3735> A_IWL<3734> A_IWL<3733> A_IWL<3732> A_IWL<3731> A_IWL<3730> A_IWL<3729> A_IWL<3728> A_IWL<3727> A_IWL<3726> A_IWL<3725> A_IWL<3724> A_IWL<3723> A_IWL<3722> A_IWL<3721> A_IWL<3720> A_IWL<3719> A_IWL<3718> A_IWL<3717> A_IWL<3716> A_IWL<3715> A_IWL<3714> A_IWL<3713> A_IWL<3712> B_BLC<59> B_BLC<58> B_BLC_TOP<59> B_BLC_TOP<58> B_BLT<59> B_BLT<58> B_BLT_TOP<59> B_BLT_TOP<58> B_IWL<3711> B_IWL<3710> B_IWL<3709> B_IWL<3708> B_IWL<3707> B_IWL<3706> B_IWL<3705> B_IWL<3704> B_IWL<3703> B_IWL<3702> B_IWL<3701> B_IWL<3700> B_IWL<3699> B_IWL<3698> B_IWL<3697> B_IWL<3696> B_IWL<3695> B_IWL<3694> B_IWL<3693> B_IWL<3692> B_IWL<3691> B_IWL<3690> B_IWL<3689> B_IWL<3688> B_IWL<3687> B_IWL<3686> B_IWL<3685> B_IWL<3684> B_IWL<3683> B_IWL<3682> B_IWL<3681> B_IWL<3680> B_IWL<3679> B_IWL<3678> B_IWL<3677> B_IWL<3676> B_IWL<3675> B_IWL<3674> B_IWL<3673> B_IWL<3672> B_IWL<3671> B_IWL<3670> B_IWL<3669> B_IWL<3668> B_IWL<3667> B_IWL<3666> B_IWL<3665> B_IWL<3664> B_IWL<3663> B_IWL<3662> B_IWL<3661> B_IWL<3660> B_IWL<3659> B_IWL<3658> B_IWL<3657> B_IWL<3656> B_IWL<3655> B_IWL<3654> B_IWL<3653> B_IWL<3652> B_IWL<3651> B_IWL<3650> B_IWL<3649> B_IWL<3648> B_IWL<3647> B_IWL<3646> B_IWL<3645> B_IWL<3644> B_IWL<3643> B_IWL<3642> B_IWL<3641> B_IWL<3640> B_IWL<3639> B_IWL<3638> B_IWL<3637> B_IWL<3636> B_IWL<3635> B_IWL<3634> B_IWL<3633> B_IWL<3632> B_IWL<3631> B_IWL<3630> B_IWL<3629> B_IWL<3628> B_IWL<3627> B_IWL<3626> B_IWL<3625> B_IWL<3624> B_IWL<3623> B_IWL<3622> B_IWL<3621> B_IWL<3620> B_IWL<3619> B_IWL<3618> B_IWL<3617> B_IWL<3616> B_IWL<3615> B_IWL<3614> B_IWL<3613> B_IWL<3612> B_IWL<3611> B_IWL<3610> B_IWL<3609> B_IWL<3608> B_IWL<3607> B_IWL<3606> B_IWL<3605> B_IWL<3604> B_IWL<3603> B_IWL<3602> B_IWL<3601> B_IWL<3600> B_IWL<3599> B_IWL<3598> B_IWL<3597> B_IWL<3596> B_IWL<3595> B_IWL<3594> B_IWL<3593> B_IWL<3592> B_IWL<3591> B_IWL<3590> B_IWL<3589> B_IWL<3588> B_IWL<3587> B_IWL<3586> B_IWL<3585> B_IWL<3584> B_IWL<3839> B_IWL<3838> B_IWL<3837> B_IWL<3836> B_IWL<3835> B_IWL<3834> B_IWL<3833> B_IWL<3832> B_IWL<3831> B_IWL<3830> B_IWL<3829> B_IWL<3828> B_IWL<3827> B_IWL<3826> B_IWL<3825> B_IWL<3824> B_IWL<3823> B_IWL<3822> B_IWL<3821> B_IWL<3820> B_IWL<3819> B_IWL<3818> B_IWL<3817> B_IWL<3816> B_IWL<3815> B_IWL<3814> B_IWL<3813> B_IWL<3812> B_IWL<3811> B_IWL<3810> B_IWL<3809> B_IWL<3808> B_IWL<3807> B_IWL<3806> B_IWL<3805> B_IWL<3804> B_IWL<3803> B_IWL<3802> B_IWL<3801> B_IWL<3800> B_IWL<3799> B_IWL<3798> B_IWL<3797> B_IWL<3796> B_IWL<3795> B_IWL<3794> B_IWL<3793> B_IWL<3792> B_IWL<3791> B_IWL<3790> B_IWL<3789> B_IWL<3788> B_IWL<3787> B_IWL<3786> B_IWL<3785> B_IWL<3784> B_IWL<3783> B_IWL<3782> B_IWL<3781> B_IWL<3780> B_IWL<3779> B_IWL<3778> B_IWL<3777> B_IWL<3776> B_IWL<3775> B_IWL<3774> B_IWL<3773> B_IWL<3772> B_IWL<3771> B_IWL<3770> B_IWL<3769> B_IWL<3768> B_IWL<3767> B_IWL<3766> B_IWL<3765> B_IWL<3764> B_IWL<3763> B_IWL<3762> B_IWL<3761> B_IWL<3760> B_IWL<3759> B_IWL<3758> B_IWL<3757> B_IWL<3756> B_IWL<3755> B_IWL<3754> B_IWL<3753> B_IWL<3752> B_IWL<3751> B_IWL<3750> B_IWL<3749> B_IWL<3748> B_IWL<3747> B_IWL<3746> B_IWL<3745> B_IWL<3744> B_IWL<3743> B_IWL<3742> B_IWL<3741> B_IWL<3740> B_IWL<3739> B_IWL<3738> B_IWL<3737> B_IWL<3736> B_IWL<3735> B_IWL<3734> B_IWL<3733> B_IWL<3732> B_IWL<3731> B_IWL<3730> B_IWL<3729> B_IWL<3728> B_IWL<3727> B_IWL<3726> B_IWL<3725> B_IWL<3724> B_IWL<3723> B_IWL<3722> B_IWL<3721> B_IWL<3720> B_IWL<3719> B_IWL<3718> B_IWL<3717> B_IWL<3716> B_IWL<3715> B_IWL<3714> B_IWL<3713> B_IWL<3712> VDD_CORE VSS / RM_IHPSG13_512x32_c2_2P_COLUMN_pcell_0 +XCOL<28> A_BLC<57> A_BLC<56> A_BLC_TOP<57> A_BLC_TOP<56> A_BLT<57> A_BLT<56> A_BLT_TOP<57> A_BLT_TOP<56> A_IWL<3583> A_IWL<3582> A_IWL<3581> A_IWL<3580> A_IWL<3579> A_IWL<3578> A_IWL<3577> A_IWL<3576> A_IWL<3575> A_IWL<3574> A_IWL<3573> A_IWL<3572> A_IWL<3571> A_IWL<3570> A_IWL<3569> A_IWL<3568> A_IWL<3567> A_IWL<3566> A_IWL<3565> A_IWL<3564> A_IWL<3563> A_IWL<3562> A_IWL<3561> A_IWL<3560> A_IWL<3559> A_IWL<3558> A_IWL<3557> A_IWL<3556> A_IWL<3555> A_IWL<3554> A_IWL<3553> A_IWL<3552> A_IWL<3551> A_IWL<3550> A_IWL<3549> A_IWL<3548> A_IWL<3547> A_IWL<3546> A_IWL<3545> A_IWL<3544> A_IWL<3543> A_IWL<3542> A_IWL<3541> A_IWL<3540> A_IWL<3539> A_IWL<3538> A_IWL<3537> A_IWL<3536> A_IWL<3535> A_IWL<3534> A_IWL<3533> A_IWL<3532> A_IWL<3531> A_IWL<3530> A_IWL<3529> A_IWL<3528> A_IWL<3527> A_IWL<3526> A_IWL<3525> A_IWL<3524> A_IWL<3523> A_IWL<3522> A_IWL<3521> A_IWL<3520> A_IWL<3519> A_IWL<3518> A_IWL<3517> A_IWL<3516> A_IWL<3515> A_IWL<3514> A_IWL<3513> A_IWL<3512> A_IWL<3511> A_IWL<3510> A_IWL<3509> A_IWL<3508> A_IWL<3507> A_IWL<3506> A_IWL<3505> A_IWL<3504> A_IWL<3503> A_IWL<3502> A_IWL<3501> A_IWL<3500> A_IWL<3499> A_IWL<3498> A_IWL<3497> A_IWL<3496> A_IWL<3495> A_IWL<3494> A_IWL<3493> A_IWL<3492> A_IWL<3491> A_IWL<3490> A_IWL<3489> A_IWL<3488> A_IWL<3487> A_IWL<3486> A_IWL<3485> A_IWL<3484> A_IWL<3483> A_IWL<3482> A_IWL<3481> A_IWL<3480> A_IWL<3479> A_IWL<3478> A_IWL<3477> A_IWL<3476> A_IWL<3475> A_IWL<3474> A_IWL<3473> A_IWL<3472> A_IWL<3471> A_IWL<3470> A_IWL<3469> A_IWL<3468> A_IWL<3467> A_IWL<3466> A_IWL<3465> A_IWL<3464> A_IWL<3463> A_IWL<3462> A_IWL<3461> A_IWL<3460> A_IWL<3459> A_IWL<3458> A_IWL<3457> A_IWL<3456> A_IWL<3711> A_IWL<3710> A_IWL<3709> A_IWL<3708> A_IWL<3707> A_IWL<3706> A_IWL<3705> A_IWL<3704> A_IWL<3703> A_IWL<3702> A_IWL<3701> A_IWL<3700> A_IWL<3699> A_IWL<3698> A_IWL<3697> A_IWL<3696> A_IWL<3695> A_IWL<3694> A_IWL<3693> A_IWL<3692> A_IWL<3691> A_IWL<3690> A_IWL<3689> A_IWL<3688> A_IWL<3687> A_IWL<3686> A_IWL<3685> A_IWL<3684> A_IWL<3683> A_IWL<3682> A_IWL<3681> A_IWL<3680> A_IWL<3679> A_IWL<3678> A_IWL<3677> A_IWL<3676> A_IWL<3675> A_IWL<3674> A_IWL<3673> A_IWL<3672> A_IWL<3671> A_IWL<3670> A_IWL<3669> A_IWL<3668> A_IWL<3667> A_IWL<3666> A_IWL<3665> A_IWL<3664> A_IWL<3663> A_IWL<3662> A_IWL<3661> A_IWL<3660> A_IWL<3659> A_IWL<3658> A_IWL<3657> A_IWL<3656> A_IWL<3655> A_IWL<3654> A_IWL<3653> A_IWL<3652> A_IWL<3651> A_IWL<3650> A_IWL<3649> A_IWL<3648> A_IWL<3647> A_IWL<3646> A_IWL<3645> A_IWL<3644> A_IWL<3643> A_IWL<3642> A_IWL<3641> A_IWL<3640> A_IWL<3639> A_IWL<3638> A_IWL<3637> A_IWL<3636> A_IWL<3635> A_IWL<3634> A_IWL<3633> A_IWL<3632> A_IWL<3631> A_IWL<3630> A_IWL<3629> A_IWL<3628> A_IWL<3627> A_IWL<3626> A_IWL<3625> A_IWL<3624> A_IWL<3623> A_IWL<3622> A_IWL<3621> A_IWL<3620> A_IWL<3619> A_IWL<3618> A_IWL<3617> A_IWL<3616> A_IWL<3615> A_IWL<3614> A_IWL<3613> A_IWL<3612> A_IWL<3611> A_IWL<3610> A_IWL<3609> A_IWL<3608> A_IWL<3607> A_IWL<3606> A_IWL<3605> A_IWL<3604> A_IWL<3603> A_IWL<3602> A_IWL<3601> A_IWL<3600> A_IWL<3599> A_IWL<3598> A_IWL<3597> A_IWL<3596> A_IWL<3595> A_IWL<3594> A_IWL<3593> A_IWL<3592> A_IWL<3591> A_IWL<3590> A_IWL<3589> A_IWL<3588> A_IWL<3587> A_IWL<3586> A_IWL<3585> A_IWL<3584> B_BLC<57> B_BLC<56> B_BLC_TOP<57> B_BLC_TOP<56> B_BLT<57> B_BLT<56> B_BLT_TOP<57> B_BLT_TOP<56> B_IWL<3583> B_IWL<3582> B_IWL<3581> B_IWL<3580> B_IWL<3579> B_IWL<3578> B_IWL<3577> B_IWL<3576> B_IWL<3575> B_IWL<3574> B_IWL<3573> B_IWL<3572> B_IWL<3571> B_IWL<3570> B_IWL<3569> B_IWL<3568> B_IWL<3567> B_IWL<3566> B_IWL<3565> B_IWL<3564> B_IWL<3563> B_IWL<3562> B_IWL<3561> B_IWL<3560> B_IWL<3559> B_IWL<3558> B_IWL<3557> B_IWL<3556> B_IWL<3555> B_IWL<3554> B_IWL<3553> B_IWL<3552> B_IWL<3551> B_IWL<3550> B_IWL<3549> B_IWL<3548> B_IWL<3547> B_IWL<3546> B_IWL<3545> B_IWL<3544> B_IWL<3543> B_IWL<3542> B_IWL<3541> B_IWL<3540> B_IWL<3539> B_IWL<3538> B_IWL<3537> B_IWL<3536> B_IWL<3535> B_IWL<3534> B_IWL<3533> B_IWL<3532> B_IWL<3531> B_IWL<3530> B_IWL<3529> B_IWL<3528> B_IWL<3527> B_IWL<3526> B_IWL<3525> B_IWL<3524> B_IWL<3523> B_IWL<3522> B_IWL<3521> B_IWL<3520> B_IWL<3519> B_IWL<3518> B_IWL<3517> B_IWL<3516> B_IWL<3515> B_IWL<3514> B_IWL<3513> B_IWL<3512> B_IWL<3511> B_IWL<3510> B_IWL<3509> B_IWL<3508> B_IWL<3507> B_IWL<3506> B_IWL<3505> B_IWL<3504> B_IWL<3503> B_IWL<3502> B_IWL<3501> B_IWL<3500> B_IWL<3499> B_IWL<3498> B_IWL<3497> B_IWL<3496> B_IWL<3495> B_IWL<3494> B_IWL<3493> B_IWL<3492> B_IWL<3491> B_IWL<3490> B_IWL<3489> B_IWL<3488> B_IWL<3487> B_IWL<3486> B_IWL<3485> B_IWL<3484> B_IWL<3483> B_IWL<3482> B_IWL<3481> B_IWL<3480> B_IWL<3479> B_IWL<3478> B_IWL<3477> B_IWL<3476> B_IWL<3475> B_IWL<3474> B_IWL<3473> B_IWL<3472> B_IWL<3471> B_IWL<3470> B_IWL<3469> B_IWL<3468> B_IWL<3467> B_IWL<3466> B_IWL<3465> B_IWL<3464> B_IWL<3463> B_IWL<3462> B_IWL<3461> B_IWL<3460> B_IWL<3459> B_IWL<3458> B_IWL<3457> B_IWL<3456> B_IWL<3711> B_IWL<3710> B_IWL<3709> B_IWL<3708> B_IWL<3707> B_IWL<3706> B_IWL<3705> B_IWL<3704> B_IWL<3703> B_IWL<3702> B_IWL<3701> B_IWL<3700> B_IWL<3699> B_IWL<3698> B_IWL<3697> B_IWL<3696> B_IWL<3695> B_IWL<3694> B_IWL<3693> B_IWL<3692> B_IWL<3691> B_IWL<3690> B_IWL<3689> B_IWL<3688> B_IWL<3687> B_IWL<3686> B_IWL<3685> B_IWL<3684> B_IWL<3683> B_IWL<3682> B_IWL<3681> B_IWL<3680> B_IWL<3679> B_IWL<3678> B_IWL<3677> B_IWL<3676> B_IWL<3675> B_IWL<3674> B_IWL<3673> B_IWL<3672> B_IWL<3671> B_IWL<3670> B_IWL<3669> B_IWL<3668> B_IWL<3667> B_IWL<3666> B_IWL<3665> B_IWL<3664> B_IWL<3663> B_IWL<3662> B_IWL<3661> B_IWL<3660> B_IWL<3659> B_IWL<3658> B_IWL<3657> B_IWL<3656> B_IWL<3655> B_IWL<3654> B_IWL<3653> B_IWL<3652> B_IWL<3651> B_IWL<3650> B_IWL<3649> B_IWL<3648> B_IWL<3647> B_IWL<3646> B_IWL<3645> B_IWL<3644> B_IWL<3643> B_IWL<3642> B_IWL<3641> B_IWL<3640> B_IWL<3639> B_IWL<3638> B_IWL<3637> B_IWL<3636> B_IWL<3635> B_IWL<3634> B_IWL<3633> B_IWL<3632> B_IWL<3631> B_IWL<3630> B_IWL<3629> B_IWL<3628> B_IWL<3627> B_IWL<3626> B_IWL<3625> B_IWL<3624> B_IWL<3623> B_IWL<3622> B_IWL<3621> B_IWL<3620> B_IWL<3619> B_IWL<3618> B_IWL<3617> B_IWL<3616> B_IWL<3615> B_IWL<3614> B_IWL<3613> B_IWL<3612> B_IWL<3611> B_IWL<3610> B_IWL<3609> B_IWL<3608> B_IWL<3607> B_IWL<3606> B_IWL<3605> B_IWL<3604> B_IWL<3603> B_IWL<3602> B_IWL<3601> B_IWL<3600> B_IWL<3599> B_IWL<3598> B_IWL<3597> B_IWL<3596> B_IWL<3595> B_IWL<3594> B_IWL<3593> B_IWL<3592> B_IWL<3591> B_IWL<3590> B_IWL<3589> B_IWL<3588> B_IWL<3587> B_IWL<3586> B_IWL<3585> B_IWL<3584> VDD_CORE VSS / RM_IHPSG13_512x32_c2_2P_COLUMN_pcell_0 +XCOL<27> A_BLC<55> A_BLC<54> A_BLC_TOP<55> A_BLC_TOP<54> A_BLT<55> A_BLT<54> A_BLT_TOP<55> A_BLT_TOP<54> A_IWL<3455> A_IWL<3454> A_IWL<3453> A_IWL<3452> A_IWL<3451> A_IWL<3450> A_IWL<3449> A_IWL<3448> A_IWL<3447> A_IWL<3446> A_IWL<3445> A_IWL<3444> A_IWL<3443> A_IWL<3442> A_IWL<3441> A_IWL<3440> A_IWL<3439> A_IWL<3438> A_IWL<3437> A_IWL<3436> A_IWL<3435> A_IWL<3434> A_IWL<3433> A_IWL<3432> A_IWL<3431> A_IWL<3430> A_IWL<3429> A_IWL<3428> A_IWL<3427> A_IWL<3426> A_IWL<3425> A_IWL<3424> A_IWL<3423> A_IWL<3422> A_IWL<3421> A_IWL<3420> A_IWL<3419> A_IWL<3418> A_IWL<3417> A_IWL<3416> A_IWL<3415> A_IWL<3414> A_IWL<3413> A_IWL<3412> A_IWL<3411> A_IWL<3410> A_IWL<3409> A_IWL<3408> A_IWL<3407> A_IWL<3406> A_IWL<3405> A_IWL<3404> A_IWL<3403> A_IWL<3402> A_IWL<3401> A_IWL<3400> A_IWL<3399> A_IWL<3398> A_IWL<3397> A_IWL<3396> A_IWL<3395> A_IWL<3394> A_IWL<3393> A_IWL<3392> A_IWL<3391> A_IWL<3390> A_IWL<3389> A_IWL<3388> A_IWL<3387> A_IWL<3386> A_IWL<3385> A_IWL<3384> A_IWL<3383> A_IWL<3382> A_IWL<3381> A_IWL<3380> A_IWL<3379> A_IWL<3378> A_IWL<3377> A_IWL<3376> A_IWL<3375> A_IWL<3374> A_IWL<3373> A_IWL<3372> A_IWL<3371> A_IWL<3370> A_IWL<3369> A_IWL<3368> A_IWL<3367> A_IWL<3366> A_IWL<3365> A_IWL<3364> A_IWL<3363> A_IWL<3362> A_IWL<3361> A_IWL<3360> A_IWL<3359> A_IWL<3358> A_IWL<3357> A_IWL<3356> A_IWL<3355> A_IWL<3354> A_IWL<3353> A_IWL<3352> A_IWL<3351> A_IWL<3350> A_IWL<3349> A_IWL<3348> A_IWL<3347> A_IWL<3346> A_IWL<3345> A_IWL<3344> A_IWL<3343> A_IWL<3342> A_IWL<3341> A_IWL<3340> A_IWL<3339> A_IWL<3338> A_IWL<3337> A_IWL<3336> A_IWL<3335> A_IWL<3334> A_IWL<3333> A_IWL<3332> A_IWL<3331> A_IWL<3330> A_IWL<3329> A_IWL<3328> A_IWL<3583> A_IWL<3582> A_IWL<3581> A_IWL<3580> A_IWL<3579> A_IWL<3578> A_IWL<3577> A_IWL<3576> A_IWL<3575> A_IWL<3574> A_IWL<3573> A_IWL<3572> A_IWL<3571> A_IWL<3570> A_IWL<3569> A_IWL<3568> A_IWL<3567> A_IWL<3566> A_IWL<3565> A_IWL<3564> A_IWL<3563> A_IWL<3562> A_IWL<3561> A_IWL<3560> A_IWL<3559> A_IWL<3558> A_IWL<3557> A_IWL<3556> A_IWL<3555> A_IWL<3554> A_IWL<3553> A_IWL<3552> A_IWL<3551> A_IWL<3550> A_IWL<3549> A_IWL<3548> A_IWL<3547> A_IWL<3546> A_IWL<3545> A_IWL<3544> A_IWL<3543> A_IWL<3542> A_IWL<3541> A_IWL<3540> A_IWL<3539> A_IWL<3538> A_IWL<3537> A_IWL<3536> A_IWL<3535> A_IWL<3534> A_IWL<3533> A_IWL<3532> A_IWL<3531> A_IWL<3530> A_IWL<3529> A_IWL<3528> A_IWL<3527> A_IWL<3526> A_IWL<3525> A_IWL<3524> A_IWL<3523> A_IWL<3522> A_IWL<3521> A_IWL<3520> A_IWL<3519> A_IWL<3518> A_IWL<3517> A_IWL<3516> A_IWL<3515> A_IWL<3514> A_IWL<3513> A_IWL<3512> A_IWL<3511> A_IWL<3510> A_IWL<3509> A_IWL<3508> A_IWL<3507> A_IWL<3506> A_IWL<3505> A_IWL<3504> A_IWL<3503> A_IWL<3502> A_IWL<3501> A_IWL<3500> A_IWL<3499> A_IWL<3498> A_IWL<3497> A_IWL<3496> A_IWL<3495> A_IWL<3494> A_IWL<3493> A_IWL<3492> A_IWL<3491> A_IWL<3490> A_IWL<3489> A_IWL<3488> A_IWL<3487> A_IWL<3486> A_IWL<3485> A_IWL<3484> A_IWL<3483> A_IWL<3482> A_IWL<3481> A_IWL<3480> A_IWL<3479> A_IWL<3478> A_IWL<3477> A_IWL<3476> A_IWL<3475> A_IWL<3474> A_IWL<3473> A_IWL<3472> A_IWL<3471> A_IWL<3470> A_IWL<3469> A_IWL<3468> A_IWL<3467> A_IWL<3466> A_IWL<3465> A_IWL<3464> A_IWL<3463> A_IWL<3462> A_IWL<3461> A_IWL<3460> A_IWL<3459> A_IWL<3458> A_IWL<3457> A_IWL<3456> B_BLC<55> B_BLC<54> B_BLC_TOP<55> B_BLC_TOP<54> B_BLT<55> B_BLT<54> B_BLT_TOP<55> B_BLT_TOP<54> B_IWL<3455> B_IWL<3454> B_IWL<3453> B_IWL<3452> B_IWL<3451> B_IWL<3450> B_IWL<3449> B_IWL<3448> B_IWL<3447> B_IWL<3446> B_IWL<3445> B_IWL<3444> B_IWL<3443> B_IWL<3442> B_IWL<3441> B_IWL<3440> B_IWL<3439> B_IWL<3438> B_IWL<3437> B_IWL<3436> B_IWL<3435> B_IWL<3434> B_IWL<3433> B_IWL<3432> B_IWL<3431> B_IWL<3430> B_IWL<3429> B_IWL<3428> B_IWL<3427> B_IWL<3426> B_IWL<3425> B_IWL<3424> B_IWL<3423> B_IWL<3422> B_IWL<3421> B_IWL<3420> B_IWL<3419> B_IWL<3418> B_IWL<3417> B_IWL<3416> B_IWL<3415> B_IWL<3414> B_IWL<3413> B_IWL<3412> B_IWL<3411> B_IWL<3410> B_IWL<3409> B_IWL<3408> B_IWL<3407> B_IWL<3406> B_IWL<3405> B_IWL<3404> B_IWL<3403> B_IWL<3402> B_IWL<3401> B_IWL<3400> B_IWL<3399> B_IWL<3398> B_IWL<3397> B_IWL<3396> B_IWL<3395> B_IWL<3394> B_IWL<3393> B_IWL<3392> B_IWL<3391> B_IWL<3390> B_IWL<3389> B_IWL<3388> B_IWL<3387> B_IWL<3386> B_IWL<3385> B_IWL<3384> B_IWL<3383> B_IWL<3382> B_IWL<3381> B_IWL<3380> B_IWL<3379> B_IWL<3378> B_IWL<3377> B_IWL<3376> B_IWL<3375> B_IWL<3374> B_IWL<3373> B_IWL<3372> B_IWL<3371> B_IWL<3370> B_IWL<3369> B_IWL<3368> B_IWL<3367> B_IWL<3366> B_IWL<3365> B_IWL<3364> B_IWL<3363> B_IWL<3362> B_IWL<3361> B_IWL<3360> B_IWL<3359> B_IWL<3358> B_IWL<3357> B_IWL<3356> B_IWL<3355> B_IWL<3354> B_IWL<3353> B_IWL<3352> B_IWL<3351> B_IWL<3350> B_IWL<3349> B_IWL<3348> B_IWL<3347> B_IWL<3346> B_IWL<3345> B_IWL<3344> B_IWL<3343> B_IWL<3342> B_IWL<3341> B_IWL<3340> B_IWL<3339> B_IWL<3338> B_IWL<3337> B_IWL<3336> B_IWL<3335> B_IWL<3334> B_IWL<3333> B_IWL<3332> B_IWL<3331> B_IWL<3330> B_IWL<3329> B_IWL<3328> B_IWL<3583> B_IWL<3582> B_IWL<3581> B_IWL<3580> B_IWL<3579> B_IWL<3578> B_IWL<3577> B_IWL<3576> B_IWL<3575> B_IWL<3574> B_IWL<3573> B_IWL<3572> B_IWL<3571> B_IWL<3570> B_IWL<3569> B_IWL<3568> B_IWL<3567> B_IWL<3566> B_IWL<3565> B_IWL<3564> B_IWL<3563> B_IWL<3562> B_IWL<3561> B_IWL<3560> B_IWL<3559> B_IWL<3558> B_IWL<3557> B_IWL<3556> B_IWL<3555> B_IWL<3554> B_IWL<3553> B_IWL<3552> B_IWL<3551> B_IWL<3550> B_IWL<3549> B_IWL<3548> B_IWL<3547> B_IWL<3546> B_IWL<3545> B_IWL<3544> B_IWL<3543> B_IWL<3542> B_IWL<3541> B_IWL<3540> B_IWL<3539> B_IWL<3538> B_IWL<3537> B_IWL<3536> B_IWL<3535> B_IWL<3534> B_IWL<3533> B_IWL<3532> B_IWL<3531> B_IWL<3530> B_IWL<3529> B_IWL<3528> B_IWL<3527> B_IWL<3526> B_IWL<3525> B_IWL<3524> B_IWL<3523> B_IWL<3522> B_IWL<3521> B_IWL<3520> B_IWL<3519> B_IWL<3518> B_IWL<3517> B_IWL<3516> B_IWL<3515> B_IWL<3514> B_IWL<3513> B_IWL<3512> B_IWL<3511> B_IWL<3510> B_IWL<3509> B_IWL<3508> B_IWL<3507> B_IWL<3506> B_IWL<3505> B_IWL<3504> B_IWL<3503> B_IWL<3502> B_IWL<3501> B_IWL<3500> B_IWL<3499> B_IWL<3498> B_IWL<3497> B_IWL<3496> B_IWL<3495> B_IWL<3494> B_IWL<3493> B_IWL<3492> B_IWL<3491> B_IWL<3490> B_IWL<3489> B_IWL<3488> B_IWL<3487> B_IWL<3486> B_IWL<3485> B_IWL<3484> B_IWL<3483> B_IWL<3482> B_IWL<3481> B_IWL<3480> B_IWL<3479> B_IWL<3478> B_IWL<3477> B_IWL<3476> B_IWL<3475> B_IWL<3474> B_IWL<3473> B_IWL<3472> B_IWL<3471> B_IWL<3470> B_IWL<3469> B_IWL<3468> B_IWL<3467> B_IWL<3466> B_IWL<3465> B_IWL<3464> B_IWL<3463> B_IWL<3462> B_IWL<3461> B_IWL<3460> B_IWL<3459> B_IWL<3458> B_IWL<3457> B_IWL<3456> VDD_CORE VSS / RM_IHPSG13_512x32_c2_2P_COLUMN_pcell_0 +XCOL<26> A_BLC<53> A_BLC<52> A_BLC_TOP<53> A_BLC_TOP<52> A_BLT<53> A_BLT<52> A_BLT_TOP<53> A_BLT_TOP<52> A_IWL<3327> A_IWL<3326> A_IWL<3325> A_IWL<3324> A_IWL<3323> A_IWL<3322> A_IWL<3321> A_IWL<3320> A_IWL<3319> A_IWL<3318> A_IWL<3317> A_IWL<3316> A_IWL<3315> A_IWL<3314> A_IWL<3313> A_IWL<3312> A_IWL<3311> A_IWL<3310> A_IWL<3309> A_IWL<3308> A_IWL<3307> A_IWL<3306> A_IWL<3305> A_IWL<3304> A_IWL<3303> A_IWL<3302> A_IWL<3301> A_IWL<3300> A_IWL<3299> A_IWL<3298> A_IWL<3297> A_IWL<3296> A_IWL<3295> A_IWL<3294> A_IWL<3293> A_IWL<3292> A_IWL<3291> A_IWL<3290> A_IWL<3289> A_IWL<3288> A_IWL<3287> A_IWL<3286> A_IWL<3285> A_IWL<3284> A_IWL<3283> A_IWL<3282> A_IWL<3281> A_IWL<3280> A_IWL<3279> A_IWL<3278> A_IWL<3277> A_IWL<3276> A_IWL<3275> A_IWL<3274> A_IWL<3273> A_IWL<3272> A_IWL<3271> A_IWL<3270> A_IWL<3269> A_IWL<3268> A_IWL<3267> A_IWL<3266> A_IWL<3265> A_IWL<3264> A_IWL<3263> A_IWL<3262> A_IWL<3261> A_IWL<3260> A_IWL<3259> A_IWL<3258> A_IWL<3257> A_IWL<3256> A_IWL<3255> A_IWL<3254> A_IWL<3253> A_IWL<3252> A_IWL<3251> A_IWL<3250> A_IWL<3249> A_IWL<3248> A_IWL<3247> A_IWL<3246> A_IWL<3245> A_IWL<3244> A_IWL<3243> A_IWL<3242> A_IWL<3241> A_IWL<3240> A_IWL<3239> A_IWL<3238> A_IWL<3237> A_IWL<3236> A_IWL<3235> A_IWL<3234> A_IWL<3233> A_IWL<3232> A_IWL<3231> A_IWL<3230> A_IWL<3229> A_IWL<3228> A_IWL<3227> A_IWL<3226> A_IWL<3225> A_IWL<3224> A_IWL<3223> A_IWL<3222> A_IWL<3221> A_IWL<3220> A_IWL<3219> A_IWL<3218> A_IWL<3217> A_IWL<3216> A_IWL<3215> A_IWL<3214> A_IWL<3213> A_IWL<3212> A_IWL<3211> A_IWL<3210> A_IWL<3209> A_IWL<3208> A_IWL<3207> A_IWL<3206> A_IWL<3205> A_IWL<3204> A_IWL<3203> A_IWL<3202> A_IWL<3201> A_IWL<3200> A_IWL<3455> A_IWL<3454> A_IWL<3453> A_IWL<3452> A_IWL<3451> A_IWL<3450> A_IWL<3449> A_IWL<3448> A_IWL<3447> A_IWL<3446> A_IWL<3445> A_IWL<3444> A_IWL<3443> A_IWL<3442> A_IWL<3441> A_IWL<3440> A_IWL<3439> A_IWL<3438> A_IWL<3437> A_IWL<3436> A_IWL<3435> A_IWL<3434> A_IWL<3433> A_IWL<3432> A_IWL<3431> A_IWL<3430> A_IWL<3429> A_IWL<3428> A_IWL<3427> A_IWL<3426> A_IWL<3425> A_IWL<3424> A_IWL<3423> A_IWL<3422> A_IWL<3421> A_IWL<3420> A_IWL<3419> A_IWL<3418> A_IWL<3417> A_IWL<3416> A_IWL<3415> A_IWL<3414> A_IWL<3413> A_IWL<3412> A_IWL<3411> A_IWL<3410> A_IWL<3409> A_IWL<3408> A_IWL<3407> A_IWL<3406> A_IWL<3405> A_IWL<3404> A_IWL<3403> A_IWL<3402> A_IWL<3401> A_IWL<3400> A_IWL<3399> A_IWL<3398> A_IWL<3397> A_IWL<3396> A_IWL<3395> A_IWL<3394> A_IWL<3393> A_IWL<3392> A_IWL<3391> A_IWL<3390> A_IWL<3389> A_IWL<3388> A_IWL<3387> A_IWL<3386> A_IWL<3385> A_IWL<3384> A_IWL<3383> A_IWL<3382> A_IWL<3381> A_IWL<3380> A_IWL<3379> A_IWL<3378> A_IWL<3377> A_IWL<3376> A_IWL<3375> A_IWL<3374> A_IWL<3373> A_IWL<3372> A_IWL<3371> A_IWL<3370> A_IWL<3369> A_IWL<3368> A_IWL<3367> A_IWL<3366> A_IWL<3365> A_IWL<3364> A_IWL<3363> A_IWL<3362> A_IWL<3361> A_IWL<3360> A_IWL<3359> A_IWL<3358> A_IWL<3357> A_IWL<3356> A_IWL<3355> A_IWL<3354> A_IWL<3353> A_IWL<3352> A_IWL<3351> A_IWL<3350> A_IWL<3349> A_IWL<3348> A_IWL<3347> A_IWL<3346> A_IWL<3345> A_IWL<3344> A_IWL<3343> A_IWL<3342> A_IWL<3341> A_IWL<3340> A_IWL<3339> A_IWL<3338> A_IWL<3337> A_IWL<3336> A_IWL<3335> A_IWL<3334> A_IWL<3333> A_IWL<3332> A_IWL<3331> A_IWL<3330> A_IWL<3329> A_IWL<3328> B_BLC<53> B_BLC<52> B_BLC_TOP<53> B_BLC_TOP<52> B_BLT<53> B_BLT<52> B_BLT_TOP<53> B_BLT_TOP<52> B_IWL<3327> B_IWL<3326> B_IWL<3325> B_IWL<3324> B_IWL<3323> B_IWL<3322> B_IWL<3321> B_IWL<3320> B_IWL<3319> B_IWL<3318> B_IWL<3317> B_IWL<3316> B_IWL<3315> B_IWL<3314> B_IWL<3313> B_IWL<3312> B_IWL<3311> B_IWL<3310> B_IWL<3309> B_IWL<3308> B_IWL<3307> B_IWL<3306> B_IWL<3305> B_IWL<3304> B_IWL<3303> B_IWL<3302> B_IWL<3301> B_IWL<3300> B_IWL<3299> B_IWL<3298> B_IWL<3297> B_IWL<3296> B_IWL<3295> B_IWL<3294> B_IWL<3293> B_IWL<3292> B_IWL<3291> B_IWL<3290> B_IWL<3289> B_IWL<3288> B_IWL<3287> B_IWL<3286> B_IWL<3285> B_IWL<3284> B_IWL<3283> B_IWL<3282> B_IWL<3281> B_IWL<3280> B_IWL<3279> B_IWL<3278> B_IWL<3277> B_IWL<3276> B_IWL<3275> B_IWL<3274> B_IWL<3273> B_IWL<3272> B_IWL<3271> B_IWL<3270> B_IWL<3269> B_IWL<3268> B_IWL<3267> B_IWL<3266> B_IWL<3265> B_IWL<3264> B_IWL<3263> B_IWL<3262> B_IWL<3261> B_IWL<3260> B_IWL<3259> B_IWL<3258> B_IWL<3257> B_IWL<3256> B_IWL<3255> B_IWL<3254> B_IWL<3253> B_IWL<3252> B_IWL<3251> B_IWL<3250> B_IWL<3249> B_IWL<3248> B_IWL<3247> B_IWL<3246> B_IWL<3245> B_IWL<3244> B_IWL<3243> B_IWL<3242> B_IWL<3241> B_IWL<3240> B_IWL<3239> B_IWL<3238> B_IWL<3237> B_IWL<3236> B_IWL<3235> B_IWL<3234> B_IWL<3233> B_IWL<3232> B_IWL<3231> B_IWL<3230> B_IWL<3229> B_IWL<3228> B_IWL<3227> B_IWL<3226> B_IWL<3225> B_IWL<3224> B_IWL<3223> B_IWL<3222> B_IWL<3221> B_IWL<3220> B_IWL<3219> B_IWL<3218> B_IWL<3217> B_IWL<3216> B_IWL<3215> B_IWL<3214> B_IWL<3213> B_IWL<3212> B_IWL<3211> B_IWL<3210> B_IWL<3209> B_IWL<3208> B_IWL<3207> B_IWL<3206> B_IWL<3205> B_IWL<3204> B_IWL<3203> B_IWL<3202> B_IWL<3201> B_IWL<3200> B_IWL<3455> B_IWL<3454> B_IWL<3453> B_IWL<3452> B_IWL<3451> B_IWL<3450> B_IWL<3449> B_IWL<3448> B_IWL<3447> B_IWL<3446> B_IWL<3445> B_IWL<3444> B_IWL<3443> B_IWL<3442> B_IWL<3441> B_IWL<3440> B_IWL<3439> B_IWL<3438> B_IWL<3437> B_IWL<3436> B_IWL<3435> B_IWL<3434> B_IWL<3433> B_IWL<3432> B_IWL<3431> B_IWL<3430> B_IWL<3429> B_IWL<3428> B_IWL<3427> B_IWL<3426> B_IWL<3425> B_IWL<3424> B_IWL<3423> B_IWL<3422> B_IWL<3421> B_IWL<3420> B_IWL<3419> B_IWL<3418> B_IWL<3417> B_IWL<3416> B_IWL<3415> B_IWL<3414> B_IWL<3413> B_IWL<3412> B_IWL<3411> B_IWL<3410> B_IWL<3409> B_IWL<3408> B_IWL<3407> B_IWL<3406> B_IWL<3405> B_IWL<3404> B_IWL<3403> B_IWL<3402> B_IWL<3401> B_IWL<3400> B_IWL<3399> B_IWL<3398> B_IWL<3397> B_IWL<3396> B_IWL<3395> B_IWL<3394> B_IWL<3393> B_IWL<3392> B_IWL<3391> B_IWL<3390> B_IWL<3389> B_IWL<3388> B_IWL<3387> B_IWL<3386> B_IWL<3385> B_IWL<3384> B_IWL<3383> B_IWL<3382> B_IWL<3381> B_IWL<3380> B_IWL<3379> B_IWL<3378> B_IWL<3377> B_IWL<3376> B_IWL<3375> B_IWL<3374> B_IWL<3373> B_IWL<3372> B_IWL<3371> B_IWL<3370> B_IWL<3369> B_IWL<3368> B_IWL<3367> B_IWL<3366> B_IWL<3365> B_IWL<3364> B_IWL<3363> B_IWL<3362> B_IWL<3361> B_IWL<3360> B_IWL<3359> B_IWL<3358> B_IWL<3357> B_IWL<3356> B_IWL<3355> B_IWL<3354> B_IWL<3353> B_IWL<3352> B_IWL<3351> B_IWL<3350> B_IWL<3349> B_IWL<3348> B_IWL<3347> B_IWL<3346> B_IWL<3345> B_IWL<3344> B_IWL<3343> B_IWL<3342> B_IWL<3341> B_IWL<3340> B_IWL<3339> B_IWL<3338> B_IWL<3337> B_IWL<3336> B_IWL<3335> B_IWL<3334> B_IWL<3333> B_IWL<3332> B_IWL<3331> B_IWL<3330> B_IWL<3329> B_IWL<3328> VDD_CORE VSS / RM_IHPSG13_512x32_c2_2P_COLUMN_pcell_0 +XCOL<25> A_BLC<51> A_BLC<50> A_BLC_TOP<51> A_BLC_TOP<50> A_BLT<51> A_BLT<50> A_BLT_TOP<51> A_BLT_TOP<50> A_IWL<3199> A_IWL<3198> A_IWL<3197> A_IWL<3196> A_IWL<3195> A_IWL<3194> A_IWL<3193> A_IWL<3192> A_IWL<3191> A_IWL<3190> A_IWL<3189> A_IWL<3188> A_IWL<3187> A_IWL<3186> A_IWL<3185> A_IWL<3184> A_IWL<3183> A_IWL<3182> A_IWL<3181> A_IWL<3180> A_IWL<3179> A_IWL<3178> A_IWL<3177> A_IWL<3176> A_IWL<3175> A_IWL<3174> A_IWL<3173> A_IWL<3172> A_IWL<3171> A_IWL<3170> A_IWL<3169> A_IWL<3168> A_IWL<3167> A_IWL<3166> A_IWL<3165> A_IWL<3164> A_IWL<3163> A_IWL<3162> A_IWL<3161> A_IWL<3160> A_IWL<3159> A_IWL<3158> A_IWL<3157> A_IWL<3156> A_IWL<3155> A_IWL<3154> A_IWL<3153> A_IWL<3152> A_IWL<3151> A_IWL<3150> A_IWL<3149> A_IWL<3148> A_IWL<3147> A_IWL<3146> A_IWL<3145> A_IWL<3144> A_IWL<3143> A_IWL<3142> A_IWL<3141> A_IWL<3140> A_IWL<3139> A_IWL<3138> A_IWL<3137> A_IWL<3136> A_IWL<3135> A_IWL<3134> A_IWL<3133> A_IWL<3132> A_IWL<3131> A_IWL<3130> A_IWL<3129> A_IWL<3128> A_IWL<3127> A_IWL<3126> A_IWL<3125> A_IWL<3124> A_IWL<3123> A_IWL<3122> A_IWL<3121> A_IWL<3120> A_IWL<3119> A_IWL<3118> A_IWL<3117> A_IWL<3116> A_IWL<3115> A_IWL<3114> A_IWL<3113> A_IWL<3112> A_IWL<3111> A_IWL<3110> A_IWL<3109> A_IWL<3108> A_IWL<3107> A_IWL<3106> A_IWL<3105> A_IWL<3104> A_IWL<3103> A_IWL<3102> A_IWL<3101> A_IWL<3100> A_IWL<3099> A_IWL<3098> A_IWL<3097> A_IWL<3096> A_IWL<3095> A_IWL<3094> A_IWL<3093> A_IWL<3092> A_IWL<3091> A_IWL<3090> A_IWL<3089> A_IWL<3088> A_IWL<3087> A_IWL<3086> A_IWL<3085> A_IWL<3084> A_IWL<3083> A_IWL<3082> A_IWL<3081> A_IWL<3080> A_IWL<3079> A_IWL<3078> A_IWL<3077> A_IWL<3076> A_IWL<3075> A_IWL<3074> A_IWL<3073> A_IWL<3072> A_IWL<3327> A_IWL<3326> A_IWL<3325> A_IWL<3324> A_IWL<3323> A_IWL<3322> A_IWL<3321> A_IWL<3320> A_IWL<3319> A_IWL<3318> A_IWL<3317> A_IWL<3316> A_IWL<3315> A_IWL<3314> A_IWL<3313> A_IWL<3312> A_IWL<3311> A_IWL<3310> A_IWL<3309> A_IWL<3308> A_IWL<3307> A_IWL<3306> A_IWL<3305> A_IWL<3304> A_IWL<3303> A_IWL<3302> A_IWL<3301> A_IWL<3300> A_IWL<3299> A_IWL<3298> A_IWL<3297> A_IWL<3296> A_IWL<3295> A_IWL<3294> A_IWL<3293> A_IWL<3292> A_IWL<3291> A_IWL<3290> A_IWL<3289> A_IWL<3288> A_IWL<3287> A_IWL<3286> A_IWL<3285> A_IWL<3284> A_IWL<3283> A_IWL<3282> A_IWL<3281> A_IWL<3280> A_IWL<3279> A_IWL<3278> A_IWL<3277> A_IWL<3276> A_IWL<3275> A_IWL<3274> A_IWL<3273> A_IWL<3272> A_IWL<3271> A_IWL<3270> A_IWL<3269> A_IWL<3268> A_IWL<3267> A_IWL<3266> A_IWL<3265> A_IWL<3264> A_IWL<3263> A_IWL<3262> A_IWL<3261> A_IWL<3260> A_IWL<3259> A_IWL<3258> A_IWL<3257> A_IWL<3256> A_IWL<3255> A_IWL<3254> A_IWL<3253> A_IWL<3252> A_IWL<3251> A_IWL<3250> A_IWL<3249> A_IWL<3248> A_IWL<3247> A_IWL<3246> A_IWL<3245> A_IWL<3244> A_IWL<3243> A_IWL<3242> A_IWL<3241> A_IWL<3240> A_IWL<3239> A_IWL<3238> A_IWL<3237> A_IWL<3236> A_IWL<3235> A_IWL<3234> A_IWL<3233> A_IWL<3232> A_IWL<3231> A_IWL<3230> A_IWL<3229> A_IWL<3228> A_IWL<3227> A_IWL<3226> A_IWL<3225> A_IWL<3224> A_IWL<3223> A_IWL<3222> A_IWL<3221> A_IWL<3220> A_IWL<3219> A_IWL<3218> A_IWL<3217> A_IWL<3216> A_IWL<3215> A_IWL<3214> A_IWL<3213> A_IWL<3212> A_IWL<3211> A_IWL<3210> A_IWL<3209> A_IWL<3208> A_IWL<3207> A_IWL<3206> A_IWL<3205> A_IWL<3204> A_IWL<3203> A_IWL<3202> A_IWL<3201> A_IWL<3200> B_BLC<51> B_BLC<50> B_BLC_TOP<51> B_BLC_TOP<50> B_BLT<51> B_BLT<50> B_BLT_TOP<51> B_BLT_TOP<50> B_IWL<3199> B_IWL<3198> B_IWL<3197> B_IWL<3196> B_IWL<3195> B_IWL<3194> B_IWL<3193> B_IWL<3192> B_IWL<3191> B_IWL<3190> B_IWL<3189> B_IWL<3188> B_IWL<3187> B_IWL<3186> B_IWL<3185> B_IWL<3184> B_IWL<3183> B_IWL<3182> B_IWL<3181> B_IWL<3180> B_IWL<3179> B_IWL<3178> B_IWL<3177> B_IWL<3176> B_IWL<3175> B_IWL<3174> B_IWL<3173> B_IWL<3172> B_IWL<3171> B_IWL<3170> B_IWL<3169> B_IWL<3168> B_IWL<3167> B_IWL<3166> B_IWL<3165> B_IWL<3164> B_IWL<3163> B_IWL<3162> B_IWL<3161> B_IWL<3160> B_IWL<3159> B_IWL<3158> B_IWL<3157> B_IWL<3156> B_IWL<3155> B_IWL<3154> B_IWL<3153> B_IWL<3152> B_IWL<3151> B_IWL<3150> B_IWL<3149> B_IWL<3148> B_IWL<3147> B_IWL<3146> B_IWL<3145> B_IWL<3144> B_IWL<3143> B_IWL<3142> B_IWL<3141> B_IWL<3140> B_IWL<3139> B_IWL<3138> B_IWL<3137> B_IWL<3136> B_IWL<3135> B_IWL<3134> B_IWL<3133> B_IWL<3132> B_IWL<3131> B_IWL<3130> B_IWL<3129> B_IWL<3128> B_IWL<3127> B_IWL<3126> B_IWL<3125> B_IWL<3124> B_IWL<3123> B_IWL<3122> B_IWL<3121> B_IWL<3120> B_IWL<3119> B_IWL<3118> B_IWL<3117> B_IWL<3116> B_IWL<3115> B_IWL<3114> B_IWL<3113> B_IWL<3112> B_IWL<3111> B_IWL<3110> B_IWL<3109> B_IWL<3108> B_IWL<3107> B_IWL<3106> B_IWL<3105> B_IWL<3104> B_IWL<3103> B_IWL<3102> B_IWL<3101> B_IWL<3100> B_IWL<3099> B_IWL<3098> B_IWL<3097> B_IWL<3096> B_IWL<3095> B_IWL<3094> B_IWL<3093> B_IWL<3092> B_IWL<3091> B_IWL<3090> B_IWL<3089> B_IWL<3088> B_IWL<3087> B_IWL<3086> B_IWL<3085> B_IWL<3084> B_IWL<3083> B_IWL<3082> B_IWL<3081> B_IWL<3080> B_IWL<3079> B_IWL<3078> B_IWL<3077> B_IWL<3076> B_IWL<3075> B_IWL<3074> B_IWL<3073> B_IWL<3072> B_IWL<3327> B_IWL<3326> B_IWL<3325> B_IWL<3324> B_IWL<3323> B_IWL<3322> B_IWL<3321> B_IWL<3320> B_IWL<3319> B_IWL<3318> B_IWL<3317> B_IWL<3316> B_IWL<3315> B_IWL<3314> B_IWL<3313> B_IWL<3312> B_IWL<3311> B_IWL<3310> B_IWL<3309> B_IWL<3308> B_IWL<3307> B_IWL<3306> B_IWL<3305> B_IWL<3304> B_IWL<3303> B_IWL<3302> B_IWL<3301> B_IWL<3300> B_IWL<3299> B_IWL<3298> B_IWL<3297> B_IWL<3296> B_IWL<3295> B_IWL<3294> B_IWL<3293> B_IWL<3292> B_IWL<3291> B_IWL<3290> B_IWL<3289> B_IWL<3288> B_IWL<3287> B_IWL<3286> B_IWL<3285> B_IWL<3284> B_IWL<3283> B_IWL<3282> B_IWL<3281> B_IWL<3280> B_IWL<3279> B_IWL<3278> B_IWL<3277> B_IWL<3276> B_IWL<3275> B_IWL<3274> B_IWL<3273> B_IWL<3272> B_IWL<3271> B_IWL<3270> B_IWL<3269> B_IWL<3268> B_IWL<3267> B_IWL<3266> B_IWL<3265> B_IWL<3264> B_IWL<3263> B_IWL<3262> B_IWL<3261> B_IWL<3260> B_IWL<3259> B_IWL<3258> B_IWL<3257> B_IWL<3256> B_IWL<3255> B_IWL<3254> B_IWL<3253> B_IWL<3252> B_IWL<3251> B_IWL<3250> B_IWL<3249> B_IWL<3248> B_IWL<3247> B_IWL<3246> B_IWL<3245> B_IWL<3244> B_IWL<3243> B_IWL<3242> B_IWL<3241> B_IWL<3240> B_IWL<3239> B_IWL<3238> B_IWL<3237> B_IWL<3236> B_IWL<3235> B_IWL<3234> B_IWL<3233> B_IWL<3232> B_IWL<3231> B_IWL<3230> B_IWL<3229> B_IWL<3228> B_IWL<3227> B_IWL<3226> B_IWL<3225> B_IWL<3224> B_IWL<3223> B_IWL<3222> B_IWL<3221> B_IWL<3220> B_IWL<3219> B_IWL<3218> B_IWL<3217> B_IWL<3216> B_IWL<3215> B_IWL<3214> B_IWL<3213> B_IWL<3212> B_IWL<3211> B_IWL<3210> B_IWL<3209> B_IWL<3208> B_IWL<3207> B_IWL<3206> B_IWL<3205> B_IWL<3204> B_IWL<3203> B_IWL<3202> B_IWL<3201> B_IWL<3200> VDD_CORE VSS / RM_IHPSG13_512x32_c2_2P_COLUMN_pcell_0 +XCOL<24> A_BLC<49> A_BLC<48> A_BLC_TOP<49> A_BLC_TOP<48> A_BLT<49> A_BLT<48> A_BLT_TOP<49> A_BLT_TOP<48> A_IWL<3071> A_IWL<3070> A_IWL<3069> A_IWL<3068> A_IWL<3067> A_IWL<3066> A_IWL<3065> A_IWL<3064> A_IWL<3063> A_IWL<3062> A_IWL<3061> A_IWL<3060> A_IWL<3059> A_IWL<3058> A_IWL<3057> A_IWL<3056> A_IWL<3055> A_IWL<3054> A_IWL<3053> A_IWL<3052> A_IWL<3051> A_IWL<3050> A_IWL<3049> A_IWL<3048> A_IWL<3047> A_IWL<3046> A_IWL<3045> A_IWL<3044> A_IWL<3043> A_IWL<3042> A_IWL<3041> A_IWL<3040> A_IWL<3039> A_IWL<3038> A_IWL<3037> A_IWL<3036> A_IWL<3035> A_IWL<3034> A_IWL<3033> A_IWL<3032> A_IWL<3031> A_IWL<3030> A_IWL<3029> A_IWL<3028> A_IWL<3027> A_IWL<3026> A_IWL<3025> A_IWL<3024> A_IWL<3023> A_IWL<3022> A_IWL<3021> A_IWL<3020> A_IWL<3019> A_IWL<3018> A_IWL<3017> A_IWL<3016> A_IWL<3015> A_IWL<3014> A_IWL<3013> A_IWL<3012> A_IWL<3011> A_IWL<3010> A_IWL<3009> A_IWL<3008> A_IWL<3007> A_IWL<3006> A_IWL<3005> A_IWL<3004> A_IWL<3003> A_IWL<3002> A_IWL<3001> A_IWL<3000> A_IWL<2999> A_IWL<2998> A_IWL<2997> A_IWL<2996> A_IWL<2995> A_IWL<2994> A_IWL<2993> A_IWL<2992> A_IWL<2991> A_IWL<2990> A_IWL<2989> A_IWL<2988> A_IWL<2987> A_IWL<2986> A_IWL<2985> A_IWL<2984> A_IWL<2983> A_IWL<2982> A_IWL<2981> A_IWL<2980> A_IWL<2979> A_IWL<2978> A_IWL<2977> A_IWL<2976> A_IWL<2975> A_IWL<2974> A_IWL<2973> A_IWL<2972> A_IWL<2971> A_IWL<2970> A_IWL<2969> A_IWL<2968> A_IWL<2967> A_IWL<2966> A_IWL<2965> A_IWL<2964> A_IWL<2963> A_IWL<2962> A_IWL<2961> A_IWL<2960> A_IWL<2959> A_IWL<2958> A_IWL<2957> A_IWL<2956> A_IWL<2955> A_IWL<2954> A_IWL<2953> A_IWL<2952> A_IWL<2951> A_IWL<2950> A_IWL<2949> A_IWL<2948> A_IWL<2947> A_IWL<2946> A_IWL<2945> A_IWL<2944> A_IWL<3199> A_IWL<3198> A_IWL<3197> A_IWL<3196> A_IWL<3195> A_IWL<3194> A_IWL<3193> A_IWL<3192> A_IWL<3191> A_IWL<3190> A_IWL<3189> A_IWL<3188> A_IWL<3187> A_IWL<3186> A_IWL<3185> A_IWL<3184> A_IWL<3183> A_IWL<3182> A_IWL<3181> A_IWL<3180> A_IWL<3179> A_IWL<3178> A_IWL<3177> A_IWL<3176> A_IWL<3175> A_IWL<3174> A_IWL<3173> A_IWL<3172> A_IWL<3171> A_IWL<3170> A_IWL<3169> A_IWL<3168> A_IWL<3167> A_IWL<3166> A_IWL<3165> A_IWL<3164> A_IWL<3163> A_IWL<3162> A_IWL<3161> A_IWL<3160> A_IWL<3159> A_IWL<3158> A_IWL<3157> A_IWL<3156> A_IWL<3155> A_IWL<3154> A_IWL<3153> A_IWL<3152> A_IWL<3151> A_IWL<3150> A_IWL<3149> A_IWL<3148> A_IWL<3147> A_IWL<3146> A_IWL<3145> A_IWL<3144> A_IWL<3143> A_IWL<3142> A_IWL<3141> A_IWL<3140> A_IWL<3139> A_IWL<3138> A_IWL<3137> A_IWL<3136> A_IWL<3135> A_IWL<3134> A_IWL<3133> A_IWL<3132> A_IWL<3131> A_IWL<3130> A_IWL<3129> A_IWL<3128> A_IWL<3127> A_IWL<3126> A_IWL<3125> A_IWL<3124> A_IWL<3123> A_IWL<3122> A_IWL<3121> A_IWL<3120> A_IWL<3119> A_IWL<3118> A_IWL<3117> A_IWL<3116> A_IWL<3115> A_IWL<3114> A_IWL<3113> A_IWL<3112> A_IWL<3111> A_IWL<3110> A_IWL<3109> A_IWL<3108> A_IWL<3107> A_IWL<3106> A_IWL<3105> A_IWL<3104> A_IWL<3103> A_IWL<3102> A_IWL<3101> A_IWL<3100> A_IWL<3099> A_IWL<3098> A_IWL<3097> A_IWL<3096> A_IWL<3095> A_IWL<3094> A_IWL<3093> A_IWL<3092> A_IWL<3091> A_IWL<3090> A_IWL<3089> A_IWL<3088> A_IWL<3087> A_IWL<3086> A_IWL<3085> A_IWL<3084> A_IWL<3083> A_IWL<3082> A_IWL<3081> A_IWL<3080> A_IWL<3079> A_IWL<3078> A_IWL<3077> A_IWL<3076> A_IWL<3075> A_IWL<3074> A_IWL<3073> A_IWL<3072> B_BLC<49> B_BLC<48> B_BLC_TOP<49> B_BLC_TOP<48> B_BLT<49> B_BLT<48> B_BLT_TOP<49> B_BLT_TOP<48> B_IWL<3071> B_IWL<3070> B_IWL<3069> B_IWL<3068> B_IWL<3067> B_IWL<3066> B_IWL<3065> B_IWL<3064> B_IWL<3063> B_IWL<3062> B_IWL<3061> B_IWL<3060> B_IWL<3059> B_IWL<3058> B_IWL<3057> B_IWL<3056> B_IWL<3055> B_IWL<3054> B_IWL<3053> B_IWL<3052> B_IWL<3051> B_IWL<3050> B_IWL<3049> B_IWL<3048> B_IWL<3047> B_IWL<3046> B_IWL<3045> B_IWL<3044> B_IWL<3043> B_IWL<3042> B_IWL<3041> B_IWL<3040> B_IWL<3039> B_IWL<3038> B_IWL<3037> B_IWL<3036> B_IWL<3035> B_IWL<3034> B_IWL<3033> B_IWL<3032> B_IWL<3031> B_IWL<3030> B_IWL<3029> B_IWL<3028> B_IWL<3027> B_IWL<3026> B_IWL<3025> B_IWL<3024> B_IWL<3023> B_IWL<3022> B_IWL<3021> B_IWL<3020> B_IWL<3019> B_IWL<3018> B_IWL<3017> B_IWL<3016> B_IWL<3015> B_IWL<3014> B_IWL<3013> B_IWL<3012> B_IWL<3011> B_IWL<3010> B_IWL<3009> B_IWL<3008> B_IWL<3007> B_IWL<3006> B_IWL<3005> B_IWL<3004> B_IWL<3003> B_IWL<3002> B_IWL<3001> B_IWL<3000> B_IWL<2999> B_IWL<2998> B_IWL<2997> B_IWL<2996> B_IWL<2995> B_IWL<2994> B_IWL<2993> B_IWL<2992> B_IWL<2991> B_IWL<2990> B_IWL<2989> B_IWL<2988> B_IWL<2987> B_IWL<2986> B_IWL<2985> B_IWL<2984> B_IWL<2983> B_IWL<2982> B_IWL<2981> B_IWL<2980> B_IWL<2979> B_IWL<2978> B_IWL<2977> B_IWL<2976> B_IWL<2975> B_IWL<2974> B_IWL<2973> B_IWL<2972> B_IWL<2971> B_IWL<2970> B_IWL<2969> B_IWL<2968> B_IWL<2967> B_IWL<2966> B_IWL<2965> B_IWL<2964> B_IWL<2963> B_IWL<2962> B_IWL<2961> B_IWL<2960> B_IWL<2959> B_IWL<2958> B_IWL<2957> B_IWL<2956> B_IWL<2955> B_IWL<2954> B_IWL<2953> B_IWL<2952> B_IWL<2951> B_IWL<2950> B_IWL<2949> B_IWL<2948> B_IWL<2947> B_IWL<2946> B_IWL<2945> B_IWL<2944> B_IWL<3199> B_IWL<3198> B_IWL<3197> B_IWL<3196> B_IWL<3195> B_IWL<3194> B_IWL<3193> B_IWL<3192> B_IWL<3191> B_IWL<3190> B_IWL<3189> B_IWL<3188> B_IWL<3187> B_IWL<3186> B_IWL<3185> B_IWL<3184> B_IWL<3183> B_IWL<3182> B_IWL<3181> B_IWL<3180> B_IWL<3179> B_IWL<3178> B_IWL<3177> B_IWL<3176> B_IWL<3175> B_IWL<3174> B_IWL<3173> B_IWL<3172> B_IWL<3171> B_IWL<3170> B_IWL<3169> B_IWL<3168> B_IWL<3167> B_IWL<3166> B_IWL<3165> B_IWL<3164> B_IWL<3163> B_IWL<3162> B_IWL<3161> B_IWL<3160> B_IWL<3159> B_IWL<3158> B_IWL<3157> B_IWL<3156> B_IWL<3155> B_IWL<3154> B_IWL<3153> B_IWL<3152> B_IWL<3151> B_IWL<3150> B_IWL<3149> B_IWL<3148> B_IWL<3147> B_IWL<3146> B_IWL<3145> B_IWL<3144> B_IWL<3143> B_IWL<3142> B_IWL<3141> B_IWL<3140> B_IWL<3139> B_IWL<3138> B_IWL<3137> B_IWL<3136> B_IWL<3135> B_IWL<3134> B_IWL<3133> B_IWL<3132> B_IWL<3131> B_IWL<3130> B_IWL<3129> B_IWL<3128> B_IWL<3127> B_IWL<3126> B_IWL<3125> B_IWL<3124> B_IWL<3123> B_IWL<3122> B_IWL<3121> B_IWL<3120> B_IWL<3119> B_IWL<3118> B_IWL<3117> B_IWL<3116> B_IWL<3115> B_IWL<3114> B_IWL<3113> B_IWL<3112> B_IWL<3111> B_IWL<3110> B_IWL<3109> B_IWL<3108> B_IWL<3107> B_IWL<3106> B_IWL<3105> B_IWL<3104> B_IWL<3103> B_IWL<3102> B_IWL<3101> B_IWL<3100> B_IWL<3099> B_IWL<3098> B_IWL<3097> B_IWL<3096> B_IWL<3095> B_IWL<3094> B_IWL<3093> B_IWL<3092> B_IWL<3091> B_IWL<3090> B_IWL<3089> B_IWL<3088> B_IWL<3087> B_IWL<3086> B_IWL<3085> B_IWL<3084> B_IWL<3083> B_IWL<3082> B_IWL<3081> B_IWL<3080> B_IWL<3079> B_IWL<3078> B_IWL<3077> B_IWL<3076> B_IWL<3075> B_IWL<3074> B_IWL<3073> B_IWL<3072> VDD_CORE VSS / RM_IHPSG13_512x32_c2_2P_COLUMN_pcell_0 +XCOL<23> A_BLC<47> A_BLC<46> A_BLC_TOP<47> A_BLC_TOP<46> A_BLT<47> A_BLT<46> A_BLT_TOP<47> A_BLT_TOP<46> A_IWL<2943> A_IWL<2942> A_IWL<2941> A_IWL<2940> A_IWL<2939> A_IWL<2938> A_IWL<2937> A_IWL<2936> A_IWL<2935> A_IWL<2934> A_IWL<2933> A_IWL<2932> A_IWL<2931> A_IWL<2930> A_IWL<2929> A_IWL<2928> A_IWL<2927> A_IWL<2926> A_IWL<2925> A_IWL<2924> A_IWL<2923> A_IWL<2922> A_IWL<2921> A_IWL<2920> A_IWL<2919> A_IWL<2918> A_IWL<2917> A_IWL<2916> A_IWL<2915> A_IWL<2914> A_IWL<2913> A_IWL<2912> A_IWL<2911> A_IWL<2910> A_IWL<2909> A_IWL<2908> A_IWL<2907> A_IWL<2906> A_IWL<2905> A_IWL<2904> A_IWL<2903> A_IWL<2902> A_IWL<2901> A_IWL<2900> A_IWL<2899> A_IWL<2898> A_IWL<2897> A_IWL<2896> A_IWL<2895> A_IWL<2894> A_IWL<2893> A_IWL<2892> A_IWL<2891> A_IWL<2890> A_IWL<2889> A_IWL<2888> A_IWL<2887> A_IWL<2886> A_IWL<2885> A_IWL<2884> A_IWL<2883> A_IWL<2882> A_IWL<2881> A_IWL<2880> A_IWL<2879> A_IWL<2878> A_IWL<2877> A_IWL<2876> A_IWL<2875> A_IWL<2874> A_IWL<2873> A_IWL<2872> A_IWL<2871> A_IWL<2870> A_IWL<2869> A_IWL<2868> A_IWL<2867> A_IWL<2866> A_IWL<2865> A_IWL<2864> A_IWL<2863> A_IWL<2862> A_IWL<2861> A_IWL<2860> A_IWL<2859> A_IWL<2858> A_IWL<2857> A_IWL<2856> A_IWL<2855> A_IWL<2854> A_IWL<2853> A_IWL<2852> A_IWL<2851> A_IWL<2850> A_IWL<2849> A_IWL<2848> A_IWL<2847> A_IWL<2846> A_IWL<2845> A_IWL<2844> A_IWL<2843> A_IWL<2842> A_IWL<2841> A_IWL<2840> A_IWL<2839> A_IWL<2838> A_IWL<2837> A_IWL<2836> A_IWL<2835> A_IWL<2834> A_IWL<2833> A_IWL<2832> A_IWL<2831> A_IWL<2830> A_IWL<2829> A_IWL<2828> A_IWL<2827> A_IWL<2826> A_IWL<2825> A_IWL<2824> A_IWL<2823> A_IWL<2822> A_IWL<2821> A_IWL<2820> A_IWL<2819> A_IWL<2818> A_IWL<2817> A_IWL<2816> A_IWL<3071> A_IWL<3070> A_IWL<3069> A_IWL<3068> A_IWL<3067> A_IWL<3066> A_IWL<3065> A_IWL<3064> A_IWL<3063> A_IWL<3062> A_IWL<3061> A_IWL<3060> A_IWL<3059> A_IWL<3058> A_IWL<3057> A_IWL<3056> A_IWL<3055> A_IWL<3054> A_IWL<3053> A_IWL<3052> A_IWL<3051> A_IWL<3050> A_IWL<3049> A_IWL<3048> A_IWL<3047> A_IWL<3046> A_IWL<3045> A_IWL<3044> A_IWL<3043> A_IWL<3042> A_IWL<3041> A_IWL<3040> A_IWL<3039> A_IWL<3038> A_IWL<3037> A_IWL<3036> A_IWL<3035> A_IWL<3034> A_IWL<3033> A_IWL<3032> A_IWL<3031> A_IWL<3030> A_IWL<3029> A_IWL<3028> A_IWL<3027> A_IWL<3026> A_IWL<3025> A_IWL<3024> A_IWL<3023> A_IWL<3022> A_IWL<3021> A_IWL<3020> A_IWL<3019> A_IWL<3018> A_IWL<3017> A_IWL<3016> A_IWL<3015> A_IWL<3014> A_IWL<3013> A_IWL<3012> A_IWL<3011> A_IWL<3010> A_IWL<3009> A_IWL<3008> A_IWL<3007> A_IWL<3006> A_IWL<3005> A_IWL<3004> A_IWL<3003> A_IWL<3002> A_IWL<3001> A_IWL<3000> A_IWL<2999> A_IWL<2998> A_IWL<2997> A_IWL<2996> A_IWL<2995> A_IWL<2994> A_IWL<2993> A_IWL<2992> A_IWL<2991> A_IWL<2990> A_IWL<2989> A_IWL<2988> A_IWL<2987> A_IWL<2986> A_IWL<2985> A_IWL<2984> A_IWL<2983> A_IWL<2982> A_IWL<2981> A_IWL<2980> A_IWL<2979> A_IWL<2978> A_IWL<2977> A_IWL<2976> A_IWL<2975> A_IWL<2974> A_IWL<2973> A_IWL<2972> A_IWL<2971> A_IWL<2970> A_IWL<2969> A_IWL<2968> A_IWL<2967> A_IWL<2966> A_IWL<2965> A_IWL<2964> A_IWL<2963> A_IWL<2962> A_IWL<2961> A_IWL<2960> A_IWL<2959> A_IWL<2958> A_IWL<2957> A_IWL<2956> A_IWL<2955> A_IWL<2954> A_IWL<2953> A_IWL<2952> A_IWL<2951> A_IWL<2950> A_IWL<2949> A_IWL<2948> A_IWL<2947> A_IWL<2946> A_IWL<2945> A_IWL<2944> B_BLC<47> B_BLC<46> B_BLC_TOP<47> B_BLC_TOP<46> B_BLT<47> B_BLT<46> B_BLT_TOP<47> B_BLT_TOP<46> B_IWL<2943> B_IWL<2942> B_IWL<2941> B_IWL<2940> B_IWL<2939> B_IWL<2938> B_IWL<2937> B_IWL<2936> B_IWL<2935> B_IWL<2934> B_IWL<2933> B_IWL<2932> B_IWL<2931> B_IWL<2930> B_IWL<2929> B_IWL<2928> B_IWL<2927> B_IWL<2926> B_IWL<2925> B_IWL<2924> B_IWL<2923> B_IWL<2922> B_IWL<2921> B_IWL<2920> B_IWL<2919> B_IWL<2918> B_IWL<2917> B_IWL<2916> B_IWL<2915> B_IWL<2914> B_IWL<2913> B_IWL<2912> B_IWL<2911> B_IWL<2910> B_IWL<2909> B_IWL<2908> B_IWL<2907> B_IWL<2906> B_IWL<2905> B_IWL<2904> B_IWL<2903> B_IWL<2902> B_IWL<2901> B_IWL<2900> B_IWL<2899> B_IWL<2898> B_IWL<2897> B_IWL<2896> B_IWL<2895> B_IWL<2894> B_IWL<2893> B_IWL<2892> B_IWL<2891> B_IWL<2890> B_IWL<2889> B_IWL<2888> B_IWL<2887> B_IWL<2886> B_IWL<2885> B_IWL<2884> B_IWL<2883> B_IWL<2882> B_IWL<2881> B_IWL<2880> B_IWL<2879> B_IWL<2878> B_IWL<2877> B_IWL<2876> B_IWL<2875> B_IWL<2874> B_IWL<2873> B_IWL<2872> B_IWL<2871> B_IWL<2870> B_IWL<2869> B_IWL<2868> B_IWL<2867> B_IWL<2866> B_IWL<2865> B_IWL<2864> B_IWL<2863> B_IWL<2862> B_IWL<2861> B_IWL<2860> B_IWL<2859> B_IWL<2858> B_IWL<2857> B_IWL<2856> B_IWL<2855> B_IWL<2854> B_IWL<2853> B_IWL<2852> B_IWL<2851> B_IWL<2850> B_IWL<2849> B_IWL<2848> B_IWL<2847> B_IWL<2846> B_IWL<2845> B_IWL<2844> B_IWL<2843> B_IWL<2842> B_IWL<2841> B_IWL<2840> B_IWL<2839> B_IWL<2838> B_IWL<2837> B_IWL<2836> B_IWL<2835> B_IWL<2834> B_IWL<2833> B_IWL<2832> B_IWL<2831> B_IWL<2830> B_IWL<2829> B_IWL<2828> B_IWL<2827> B_IWL<2826> B_IWL<2825> B_IWL<2824> B_IWL<2823> B_IWL<2822> B_IWL<2821> B_IWL<2820> B_IWL<2819> B_IWL<2818> B_IWL<2817> B_IWL<2816> B_IWL<3071> B_IWL<3070> B_IWL<3069> B_IWL<3068> B_IWL<3067> B_IWL<3066> B_IWL<3065> B_IWL<3064> B_IWL<3063> B_IWL<3062> B_IWL<3061> B_IWL<3060> B_IWL<3059> B_IWL<3058> B_IWL<3057> B_IWL<3056> B_IWL<3055> B_IWL<3054> B_IWL<3053> B_IWL<3052> B_IWL<3051> B_IWL<3050> B_IWL<3049> B_IWL<3048> B_IWL<3047> B_IWL<3046> B_IWL<3045> B_IWL<3044> B_IWL<3043> B_IWL<3042> B_IWL<3041> B_IWL<3040> B_IWL<3039> B_IWL<3038> B_IWL<3037> B_IWL<3036> B_IWL<3035> B_IWL<3034> B_IWL<3033> B_IWL<3032> B_IWL<3031> B_IWL<3030> B_IWL<3029> B_IWL<3028> B_IWL<3027> B_IWL<3026> B_IWL<3025> B_IWL<3024> B_IWL<3023> B_IWL<3022> B_IWL<3021> B_IWL<3020> B_IWL<3019> B_IWL<3018> B_IWL<3017> B_IWL<3016> B_IWL<3015> B_IWL<3014> B_IWL<3013> B_IWL<3012> B_IWL<3011> B_IWL<3010> B_IWL<3009> B_IWL<3008> B_IWL<3007> B_IWL<3006> B_IWL<3005> B_IWL<3004> B_IWL<3003> B_IWL<3002> B_IWL<3001> B_IWL<3000> B_IWL<2999> B_IWL<2998> B_IWL<2997> B_IWL<2996> B_IWL<2995> B_IWL<2994> B_IWL<2993> B_IWL<2992> B_IWL<2991> B_IWL<2990> B_IWL<2989> B_IWL<2988> B_IWL<2987> B_IWL<2986> B_IWL<2985> B_IWL<2984> B_IWL<2983> B_IWL<2982> B_IWL<2981> B_IWL<2980> B_IWL<2979> B_IWL<2978> B_IWL<2977> B_IWL<2976> B_IWL<2975> B_IWL<2974> B_IWL<2973> B_IWL<2972> B_IWL<2971> B_IWL<2970> B_IWL<2969> B_IWL<2968> B_IWL<2967> B_IWL<2966> B_IWL<2965> B_IWL<2964> B_IWL<2963> B_IWL<2962> B_IWL<2961> B_IWL<2960> B_IWL<2959> B_IWL<2958> B_IWL<2957> B_IWL<2956> B_IWL<2955> B_IWL<2954> B_IWL<2953> B_IWL<2952> B_IWL<2951> B_IWL<2950> B_IWL<2949> B_IWL<2948> B_IWL<2947> B_IWL<2946> B_IWL<2945> B_IWL<2944> VDD_CORE VSS / RM_IHPSG13_512x32_c2_2P_COLUMN_pcell_0 +XCOL<22> A_BLC<45> A_BLC<44> A_BLC_TOP<45> A_BLC_TOP<44> A_BLT<45> A_BLT<44> A_BLT_TOP<45> A_BLT_TOP<44> A_IWL<2815> A_IWL<2814> A_IWL<2813> A_IWL<2812> A_IWL<2811> A_IWL<2810> A_IWL<2809> A_IWL<2808> A_IWL<2807> A_IWL<2806> A_IWL<2805> A_IWL<2804> A_IWL<2803> A_IWL<2802> A_IWL<2801> A_IWL<2800> A_IWL<2799> A_IWL<2798> A_IWL<2797> A_IWL<2796> A_IWL<2795> A_IWL<2794> A_IWL<2793> A_IWL<2792> A_IWL<2791> A_IWL<2790> A_IWL<2789> A_IWL<2788> A_IWL<2787> A_IWL<2786> A_IWL<2785> A_IWL<2784> A_IWL<2783> A_IWL<2782> A_IWL<2781> A_IWL<2780> A_IWL<2779> A_IWL<2778> A_IWL<2777> A_IWL<2776> A_IWL<2775> A_IWL<2774> A_IWL<2773> A_IWL<2772> A_IWL<2771> A_IWL<2770> A_IWL<2769> A_IWL<2768> A_IWL<2767> A_IWL<2766> A_IWL<2765> A_IWL<2764> A_IWL<2763> A_IWL<2762> A_IWL<2761> A_IWL<2760> A_IWL<2759> A_IWL<2758> A_IWL<2757> A_IWL<2756> A_IWL<2755> A_IWL<2754> A_IWL<2753> A_IWL<2752> A_IWL<2751> A_IWL<2750> A_IWL<2749> A_IWL<2748> A_IWL<2747> A_IWL<2746> A_IWL<2745> A_IWL<2744> A_IWL<2743> A_IWL<2742> A_IWL<2741> A_IWL<2740> A_IWL<2739> A_IWL<2738> A_IWL<2737> A_IWL<2736> A_IWL<2735> A_IWL<2734> A_IWL<2733> A_IWL<2732> A_IWL<2731> A_IWL<2730> A_IWL<2729> A_IWL<2728> A_IWL<2727> A_IWL<2726> A_IWL<2725> A_IWL<2724> A_IWL<2723> A_IWL<2722> A_IWL<2721> A_IWL<2720> A_IWL<2719> A_IWL<2718> A_IWL<2717> A_IWL<2716> A_IWL<2715> A_IWL<2714> A_IWL<2713> A_IWL<2712> A_IWL<2711> A_IWL<2710> A_IWL<2709> A_IWL<2708> A_IWL<2707> A_IWL<2706> A_IWL<2705> A_IWL<2704> A_IWL<2703> A_IWL<2702> A_IWL<2701> A_IWL<2700> A_IWL<2699> A_IWL<2698> A_IWL<2697> A_IWL<2696> A_IWL<2695> A_IWL<2694> A_IWL<2693> A_IWL<2692> A_IWL<2691> A_IWL<2690> A_IWL<2689> A_IWL<2688> A_IWL<2943> A_IWL<2942> A_IWL<2941> A_IWL<2940> A_IWL<2939> A_IWL<2938> A_IWL<2937> A_IWL<2936> A_IWL<2935> A_IWL<2934> A_IWL<2933> A_IWL<2932> A_IWL<2931> A_IWL<2930> A_IWL<2929> A_IWL<2928> A_IWL<2927> A_IWL<2926> A_IWL<2925> A_IWL<2924> A_IWL<2923> A_IWL<2922> A_IWL<2921> A_IWL<2920> A_IWL<2919> A_IWL<2918> A_IWL<2917> A_IWL<2916> A_IWL<2915> A_IWL<2914> A_IWL<2913> A_IWL<2912> A_IWL<2911> A_IWL<2910> A_IWL<2909> A_IWL<2908> A_IWL<2907> A_IWL<2906> A_IWL<2905> A_IWL<2904> A_IWL<2903> A_IWL<2902> A_IWL<2901> A_IWL<2900> A_IWL<2899> A_IWL<2898> A_IWL<2897> A_IWL<2896> A_IWL<2895> A_IWL<2894> A_IWL<2893> A_IWL<2892> A_IWL<2891> A_IWL<2890> A_IWL<2889> A_IWL<2888> A_IWL<2887> A_IWL<2886> A_IWL<2885> A_IWL<2884> A_IWL<2883> A_IWL<2882> A_IWL<2881> A_IWL<2880> A_IWL<2879> A_IWL<2878> A_IWL<2877> A_IWL<2876> A_IWL<2875> A_IWL<2874> A_IWL<2873> A_IWL<2872> A_IWL<2871> A_IWL<2870> A_IWL<2869> A_IWL<2868> A_IWL<2867> A_IWL<2866> A_IWL<2865> A_IWL<2864> A_IWL<2863> A_IWL<2862> A_IWL<2861> A_IWL<2860> A_IWL<2859> A_IWL<2858> A_IWL<2857> A_IWL<2856> A_IWL<2855> A_IWL<2854> A_IWL<2853> A_IWL<2852> A_IWL<2851> A_IWL<2850> A_IWL<2849> A_IWL<2848> A_IWL<2847> A_IWL<2846> A_IWL<2845> A_IWL<2844> A_IWL<2843> A_IWL<2842> A_IWL<2841> A_IWL<2840> A_IWL<2839> A_IWL<2838> A_IWL<2837> A_IWL<2836> A_IWL<2835> A_IWL<2834> A_IWL<2833> A_IWL<2832> A_IWL<2831> A_IWL<2830> A_IWL<2829> A_IWL<2828> A_IWL<2827> A_IWL<2826> A_IWL<2825> A_IWL<2824> A_IWL<2823> A_IWL<2822> A_IWL<2821> A_IWL<2820> A_IWL<2819> A_IWL<2818> A_IWL<2817> A_IWL<2816> B_BLC<45> B_BLC<44> B_BLC_TOP<45> B_BLC_TOP<44> B_BLT<45> B_BLT<44> B_BLT_TOP<45> B_BLT_TOP<44> B_IWL<2815> B_IWL<2814> B_IWL<2813> B_IWL<2812> B_IWL<2811> B_IWL<2810> B_IWL<2809> B_IWL<2808> B_IWL<2807> B_IWL<2806> B_IWL<2805> B_IWL<2804> B_IWL<2803> B_IWL<2802> B_IWL<2801> B_IWL<2800> B_IWL<2799> B_IWL<2798> B_IWL<2797> B_IWL<2796> B_IWL<2795> B_IWL<2794> B_IWL<2793> B_IWL<2792> B_IWL<2791> B_IWL<2790> B_IWL<2789> B_IWL<2788> B_IWL<2787> B_IWL<2786> B_IWL<2785> B_IWL<2784> B_IWL<2783> B_IWL<2782> B_IWL<2781> B_IWL<2780> B_IWL<2779> B_IWL<2778> B_IWL<2777> B_IWL<2776> B_IWL<2775> B_IWL<2774> B_IWL<2773> B_IWL<2772> B_IWL<2771> B_IWL<2770> B_IWL<2769> B_IWL<2768> B_IWL<2767> B_IWL<2766> B_IWL<2765> B_IWL<2764> B_IWL<2763> B_IWL<2762> B_IWL<2761> B_IWL<2760> B_IWL<2759> B_IWL<2758> B_IWL<2757> B_IWL<2756> B_IWL<2755> B_IWL<2754> B_IWL<2753> B_IWL<2752> B_IWL<2751> B_IWL<2750> B_IWL<2749> B_IWL<2748> B_IWL<2747> B_IWL<2746> B_IWL<2745> B_IWL<2744> B_IWL<2743> B_IWL<2742> B_IWL<2741> B_IWL<2740> B_IWL<2739> B_IWL<2738> B_IWL<2737> B_IWL<2736> B_IWL<2735> B_IWL<2734> B_IWL<2733> B_IWL<2732> B_IWL<2731> B_IWL<2730> B_IWL<2729> B_IWL<2728> B_IWL<2727> B_IWL<2726> B_IWL<2725> B_IWL<2724> B_IWL<2723> B_IWL<2722> B_IWL<2721> B_IWL<2720> B_IWL<2719> B_IWL<2718> B_IWL<2717> B_IWL<2716> B_IWL<2715> B_IWL<2714> B_IWL<2713> B_IWL<2712> B_IWL<2711> B_IWL<2710> B_IWL<2709> B_IWL<2708> B_IWL<2707> B_IWL<2706> B_IWL<2705> B_IWL<2704> B_IWL<2703> B_IWL<2702> B_IWL<2701> B_IWL<2700> B_IWL<2699> B_IWL<2698> B_IWL<2697> B_IWL<2696> B_IWL<2695> B_IWL<2694> B_IWL<2693> B_IWL<2692> B_IWL<2691> B_IWL<2690> B_IWL<2689> B_IWL<2688> B_IWL<2943> B_IWL<2942> B_IWL<2941> B_IWL<2940> B_IWL<2939> B_IWL<2938> B_IWL<2937> B_IWL<2936> B_IWL<2935> B_IWL<2934> B_IWL<2933> B_IWL<2932> B_IWL<2931> B_IWL<2930> B_IWL<2929> B_IWL<2928> B_IWL<2927> B_IWL<2926> B_IWL<2925> B_IWL<2924> B_IWL<2923> B_IWL<2922> B_IWL<2921> B_IWL<2920> B_IWL<2919> B_IWL<2918> B_IWL<2917> B_IWL<2916> B_IWL<2915> B_IWL<2914> B_IWL<2913> B_IWL<2912> B_IWL<2911> B_IWL<2910> B_IWL<2909> B_IWL<2908> B_IWL<2907> B_IWL<2906> B_IWL<2905> B_IWL<2904> B_IWL<2903> B_IWL<2902> B_IWL<2901> B_IWL<2900> B_IWL<2899> B_IWL<2898> B_IWL<2897> B_IWL<2896> B_IWL<2895> B_IWL<2894> B_IWL<2893> B_IWL<2892> B_IWL<2891> B_IWL<2890> B_IWL<2889> B_IWL<2888> B_IWL<2887> B_IWL<2886> B_IWL<2885> B_IWL<2884> B_IWL<2883> B_IWL<2882> B_IWL<2881> B_IWL<2880> B_IWL<2879> B_IWL<2878> B_IWL<2877> B_IWL<2876> B_IWL<2875> B_IWL<2874> B_IWL<2873> B_IWL<2872> B_IWL<2871> B_IWL<2870> B_IWL<2869> B_IWL<2868> B_IWL<2867> B_IWL<2866> B_IWL<2865> B_IWL<2864> B_IWL<2863> B_IWL<2862> B_IWL<2861> B_IWL<2860> B_IWL<2859> B_IWL<2858> B_IWL<2857> B_IWL<2856> B_IWL<2855> B_IWL<2854> B_IWL<2853> B_IWL<2852> B_IWL<2851> B_IWL<2850> B_IWL<2849> B_IWL<2848> B_IWL<2847> B_IWL<2846> B_IWL<2845> B_IWL<2844> B_IWL<2843> B_IWL<2842> B_IWL<2841> B_IWL<2840> B_IWL<2839> B_IWL<2838> B_IWL<2837> B_IWL<2836> B_IWL<2835> B_IWL<2834> B_IWL<2833> B_IWL<2832> B_IWL<2831> B_IWL<2830> B_IWL<2829> B_IWL<2828> B_IWL<2827> B_IWL<2826> B_IWL<2825> B_IWL<2824> B_IWL<2823> B_IWL<2822> B_IWL<2821> B_IWL<2820> B_IWL<2819> B_IWL<2818> B_IWL<2817> B_IWL<2816> VDD_CORE VSS / RM_IHPSG13_512x32_c2_2P_COLUMN_pcell_0 +XCOL<21> A_BLC<43> A_BLC<42> A_BLC_TOP<43> A_BLC_TOP<42> A_BLT<43> A_BLT<42> A_BLT_TOP<43> A_BLT_TOP<42> A_IWL<2687> A_IWL<2686> A_IWL<2685> A_IWL<2684> A_IWL<2683> A_IWL<2682> A_IWL<2681> A_IWL<2680> A_IWL<2679> A_IWL<2678> A_IWL<2677> A_IWL<2676> A_IWL<2675> A_IWL<2674> A_IWL<2673> A_IWL<2672> A_IWL<2671> A_IWL<2670> A_IWL<2669> A_IWL<2668> A_IWL<2667> A_IWL<2666> A_IWL<2665> A_IWL<2664> A_IWL<2663> A_IWL<2662> A_IWL<2661> A_IWL<2660> A_IWL<2659> A_IWL<2658> A_IWL<2657> A_IWL<2656> A_IWL<2655> A_IWL<2654> A_IWL<2653> A_IWL<2652> A_IWL<2651> A_IWL<2650> A_IWL<2649> A_IWL<2648> A_IWL<2647> A_IWL<2646> A_IWL<2645> A_IWL<2644> A_IWL<2643> A_IWL<2642> A_IWL<2641> A_IWL<2640> A_IWL<2639> A_IWL<2638> A_IWL<2637> A_IWL<2636> A_IWL<2635> A_IWL<2634> A_IWL<2633> A_IWL<2632> A_IWL<2631> A_IWL<2630> A_IWL<2629> A_IWL<2628> A_IWL<2627> A_IWL<2626> A_IWL<2625> A_IWL<2624> A_IWL<2623> A_IWL<2622> A_IWL<2621> A_IWL<2620> A_IWL<2619> A_IWL<2618> A_IWL<2617> A_IWL<2616> A_IWL<2615> A_IWL<2614> A_IWL<2613> A_IWL<2612> A_IWL<2611> A_IWL<2610> A_IWL<2609> A_IWL<2608> A_IWL<2607> A_IWL<2606> A_IWL<2605> A_IWL<2604> A_IWL<2603> A_IWL<2602> A_IWL<2601> A_IWL<2600> A_IWL<2599> A_IWL<2598> A_IWL<2597> A_IWL<2596> A_IWL<2595> A_IWL<2594> A_IWL<2593> A_IWL<2592> A_IWL<2591> A_IWL<2590> A_IWL<2589> A_IWL<2588> A_IWL<2587> A_IWL<2586> A_IWL<2585> A_IWL<2584> A_IWL<2583> A_IWL<2582> A_IWL<2581> A_IWL<2580> A_IWL<2579> A_IWL<2578> A_IWL<2577> A_IWL<2576> A_IWL<2575> A_IWL<2574> A_IWL<2573> A_IWL<2572> A_IWL<2571> A_IWL<2570> A_IWL<2569> A_IWL<2568> A_IWL<2567> A_IWL<2566> A_IWL<2565> A_IWL<2564> A_IWL<2563> A_IWL<2562> A_IWL<2561> A_IWL<2560> A_IWL<2815> A_IWL<2814> A_IWL<2813> A_IWL<2812> A_IWL<2811> A_IWL<2810> A_IWL<2809> A_IWL<2808> A_IWL<2807> A_IWL<2806> A_IWL<2805> A_IWL<2804> A_IWL<2803> A_IWL<2802> A_IWL<2801> A_IWL<2800> A_IWL<2799> A_IWL<2798> A_IWL<2797> A_IWL<2796> A_IWL<2795> A_IWL<2794> A_IWL<2793> A_IWL<2792> A_IWL<2791> A_IWL<2790> A_IWL<2789> A_IWL<2788> A_IWL<2787> A_IWL<2786> A_IWL<2785> A_IWL<2784> A_IWL<2783> A_IWL<2782> A_IWL<2781> A_IWL<2780> A_IWL<2779> A_IWL<2778> A_IWL<2777> A_IWL<2776> A_IWL<2775> A_IWL<2774> A_IWL<2773> A_IWL<2772> A_IWL<2771> A_IWL<2770> A_IWL<2769> A_IWL<2768> A_IWL<2767> A_IWL<2766> A_IWL<2765> A_IWL<2764> A_IWL<2763> A_IWL<2762> A_IWL<2761> A_IWL<2760> A_IWL<2759> A_IWL<2758> A_IWL<2757> A_IWL<2756> A_IWL<2755> A_IWL<2754> A_IWL<2753> A_IWL<2752> A_IWL<2751> A_IWL<2750> A_IWL<2749> A_IWL<2748> A_IWL<2747> A_IWL<2746> A_IWL<2745> A_IWL<2744> A_IWL<2743> A_IWL<2742> A_IWL<2741> A_IWL<2740> A_IWL<2739> A_IWL<2738> A_IWL<2737> A_IWL<2736> A_IWL<2735> A_IWL<2734> A_IWL<2733> A_IWL<2732> A_IWL<2731> A_IWL<2730> A_IWL<2729> A_IWL<2728> A_IWL<2727> A_IWL<2726> A_IWL<2725> A_IWL<2724> A_IWL<2723> A_IWL<2722> A_IWL<2721> A_IWL<2720> A_IWL<2719> A_IWL<2718> A_IWL<2717> A_IWL<2716> A_IWL<2715> A_IWL<2714> A_IWL<2713> A_IWL<2712> A_IWL<2711> A_IWL<2710> A_IWL<2709> A_IWL<2708> A_IWL<2707> A_IWL<2706> A_IWL<2705> A_IWL<2704> A_IWL<2703> A_IWL<2702> A_IWL<2701> A_IWL<2700> A_IWL<2699> A_IWL<2698> A_IWL<2697> A_IWL<2696> A_IWL<2695> A_IWL<2694> A_IWL<2693> A_IWL<2692> A_IWL<2691> A_IWL<2690> A_IWL<2689> A_IWL<2688> B_BLC<43> B_BLC<42> B_BLC_TOP<43> B_BLC_TOP<42> B_BLT<43> B_BLT<42> B_BLT_TOP<43> B_BLT_TOP<42> B_IWL<2687> B_IWL<2686> B_IWL<2685> B_IWL<2684> B_IWL<2683> B_IWL<2682> B_IWL<2681> B_IWL<2680> B_IWL<2679> B_IWL<2678> B_IWL<2677> B_IWL<2676> B_IWL<2675> B_IWL<2674> B_IWL<2673> B_IWL<2672> B_IWL<2671> B_IWL<2670> B_IWL<2669> B_IWL<2668> B_IWL<2667> B_IWL<2666> B_IWL<2665> B_IWL<2664> B_IWL<2663> B_IWL<2662> B_IWL<2661> B_IWL<2660> B_IWL<2659> B_IWL<2658> B_IWL<2657> B_IWL<2656> B_IWL<2655> B_IWL<2654> B_IWL<2653> B_IWL<2652> B_IWL<2651> B_IWL<2650> B_IWL<2649> B_IWL<2648> B_IWL<2647> B_IWL<2646> B_IWL<2645> B_IWL<2644> B_IWL<2643> B_IWL<2642> B_IWL<2641> B_IWL<2640> B_IWL<2639> B_IWL<2638> B_IWL<2637> B_IWL<2636> B_IWL<2635> B_IWL<2634> B_IWL<2633> B_IWL<2632> B_IWL<2631> B_IWL<2630> B_IWL<2629> B_IWL<2628> B_IWL<2627> B_IWL<2626> B_IWL<2625> B_IWL<2624> B_IWL<2623> B_IWL<2622> B_IWL<2621> B_IWL<2620> B_IWL<2619> B_IWL<2618> B_IWL<2617> B_IWL<2616> B_IWL<2615> B_IWL<2614> B_IWL<2613> B_IWL<2612> B_IWL<2611> B_IWL<2610> B_IWL<2609> B_IWL<2608> B_IWL<2607> B_IWL<2606> B_IWL<2605> B_IWL<2604> B_IWL<2603> B_IWL<2602> B_IWL<2601> B_IWL<2600> B_IWL<2599> B_IWL<2598> B_IWL<2597> B_IWL<2596> B_IWL<2595> B_IWL<2594> B_IWL<2593> B_IWL<2592> B_IWL<2591> B_IWL<2590> B_IWL<2589> B_IWL<2588> B_IWL<2587> B_IWL<2586> B_IWL<2585> B_IWL<2584> B_IWL<2583> B_IWL<2582> B_IWL<2581> B_IWL<2580> B_IWL<2579> B_IWL<2578> B_IWL<2577> B_IWL<2576> B_IWL<2575> B_IWL<2574> B_IWL<2573> B_IWL<2572> B_IWL<2571> B_IWL<2570> B_IWL<2569> B_IWL<2568> B_IWL<2567> B_IWL<2566> B_IWL<2565> B_IWL<2564> B_IWL<2563> B_IWL<2562> B_IWL<2561> B_IWL<2560> B_IWL<2815> B_IWL<2814> B_IWL<2813> B_IWL<2812> B_IWL<2811> B_IWL<2810> B_IWL<2809> B_IWL<2808> B_IWL<2807> B_IWL<2806> B_IWL<2805> B_IWL<2804> B_IWL<2803> B_IWL<2802> B_IWL<2801> B_IWL<2800> B_IWL<2799> B_IWL<2798> B_IWL<2797> B_IWL<2796> B_IWL<2795> B_IWL<2794> B_IWL<2793> B_IWL<2792> B_IWL<2791> B_IWL<2790> B_IWL<2789> B_IWL<2788> B_IWL<2787> B_IWL<2786> B_IWL<2785> B_IWL<2784> B_IWL<2783> B_IWL<2782> B_IWL<2781> B_IWL<2780> B_IWL<2779> B_IWL<2778> B_IWL<2777> B_IWL<2776> B_IWL<2775> B_IWL<2774> B_IWL<2773> B_IWL<2772> B_IWL<2771> B_IWL<2770> B_IWL<2769> B_IWL<2768> B_IWL<2767> B_IWL<2766> B_IWL<2765> B_IWL<2764> B_IWL<2763> B_IWL<2762> B_IWL<2761> B_IWL<2760> B_IWL<2759> B_IWL<2758> B_IWL<2757> B_IWL<2756> B_IWL<2755> B_IWL<2754> B_IWL<2753> B_IWL<2752> B_IWL<2751> B_IWL<2750> B_IWL<2749> B_IWL<2748> B_IWL<2747> B_IWL<2746> B_IWL<2745> B_IWL<2744> B_IWL<2743> B_IWL<2742> B_IWL<2741> B_IWL<2740> B_IWL<2739> B_IWL<2738> B_IWL<2737> B_IWL<2736> B_IWL<2735> B_IWL<2734> B_IWL<2733> B_IWL<2732> B_IWL<2731> B_IWL<2730> B_IWL<2729> B_IWL<2728> B_IWL<2727> B_IWL<2726> B_IWL<2725> B_IWL<2724> B_IWL<2723> B_IWL<2722> B_IWL<2721> B_IWL<2720> B_IWL<2719> B_IWL<2718> B_IWL<2717> B_IWL<2716> B_IWL<2715> B_IWL<2714> B_IWL<2713> B_IWL<2712> B_IWL<2711> B_IWL<2710> B_IWL<2709> B_IWL<2708> B_IWL<2707> B_IWL<2706> B_IWL<2705> B_IWL<2704> B_IWL<2703> B_IWL<2702> B_IWL<2701> B_IWL<2700> B_IWL<2699> B_IWL<2698> B_IWL<2697> B_IWL<2696> B_IWL<2695> B_IWL<2694> B_IWL<2693> B_IWL<2692> B_IWL<2691> B_IWL<2690> B_IWL<2689> B_IWL<2688> VDD_CORE VSS / RM_IHPSG13_512x32_c2_2P_COLUMN_pcell_0 +XCOL<20> A_BLC<41> A_BLC<40> A_BLC_TOP<41> A_BLC_TOP<40> A_BLT<41> A_BLT<40> A_BLT_TOP<41> A_BLT_TOP<40> A_IWL<2559> A_IWL<2558> A_IWL<2557> A_IWL<2556> A_IWL<2555> A_IWL<2554> A_IWL<2553> A_IWL<2552> A_IWL<2551> A_IWL<2550> A_IWL<2549> A_IWL<2548> A_IWL<2547> A_IWL<2546> A_IWL<2545> A_IWL<2544> A_IWL<2543> A_IWL<2542> A_IWL<2541> A_IWL<2540> A_IWL<2539> A_IWL<2538> A_IWL<2537> A_IWL<2536> A_IWL<2535> A_IWL<2534> A_IWL<2533> A_IWL<2532> A_IWL<2531> A_IWL<2530> A_IWL<2529> A_IWL<2528> A_IWL<2527> A_IWL<2526> A_IWL<2525> A_IWL<2524> A_IWL<2523> A_IWL<2522> A_IWL<2521> A_IWL<2520> A_IWL<2519> A_IWL<2518> A_IWL<2517> A_IWL<2516> A_IWL<2515> A_IWL<2514> A_IWL<2513> A_IWL<2512> A_IWL<2511> A_IWL<2510> A_IWL<2509> A_IWL<2508> A_IWL<2507> A_IWL<2506> A_IWL<2505> A_IWL<2504> A_IWL<2503> A_IWL<2502> A_IWL<2501> A_IWL<2500> A_IWL<2499> A_IWL<2498> A_IWL<2497> A_IWL<2496> A_IWL<2495> A_IWL<2494> A_IWL<2493> A_IWL<2492> A_IWL<2491> A_IWL<2490> A_IWL<2489> A_IWL<2488> A_IWL<2487> A_IWL<2486> A_IWL<2485> A_IWL<2484> A_IWL<2483> A_IWL<2482> A_IWL<2481> A_IWL<2480> A_IWL<2479> A_IWL<2478> A_IWL<2477> A_IWL<2476> A_IWL<2475> A_IWL<2474> A_IWL<2473> A_IWL<2472> A_IWL<2471> A_IWL<2470> A_IWL<2469> A_IWL<2468> A_IWL<2467> A_IWL<2466> A_IWL<2465> A_IWL<2464> A_IWL<2463> A_IWL<2462> A_IWL<2461> A_IWL<2460> A_IWL<2459> A_IWL<2458> A_IWL<2457> A_IWL<2456> A_IWL<2455> A_IWL<2454> A_IWL<2453> A_IWL<2452> A_IWL<2451> A_IWL<2450> A_IWL<2449> A_IWL<2448> A_IWL<2447> A_IWL<2446> A_IWL<2445> A_IWL<2444> A_IWL<2443> A_IWL<2442> A_IWL<2441> A_IWL<2440> A_IWL<2439> A_IWL<2438> A_IWL<2437> A_IWL<2436> A_IWL<2435> A_IWL<2434> A_IWL<2433> A_IWL<2432> A_IWL<2687> A_IWL<2686> A_IWL<2685> A_IWL<2684> A_IWL<2683> A_IWL<2682> A_IWL<2681> A_IWL<2680> A_IWL<2679> A_IWL<2678> A_IWL<2677> A_IWL<2676> A_IWL<2675> A_IWL<2674> A_IWL<2673> A_IWL<2672> A_IWL<2671> A_IWL<2670> A_IWL<2669> A_IWL<2668> A_IWL<2667> A_IWL<2666> A_IWL<2665> A_IWL<2664> A_IWL<2663> A_IWL<2662> A_IWL<2661> A_IWL<2660> A_IWL<2659> A_IWL<2658> A_IWL<2657> A_IWL<2656> A_IWL<2655> A_IWL<2654> A_IWL<2653> A_IWL<2652> A_IWL<2651> A_IWL<2650> A_IWL<2649> A_IWL<2648> A_IWL<2647> A_IWL<2646> A_IWL<2645> A_IWL<2644> A_IWL<2643> A_IWL<2642> A_IWL<2641> A_IWL<2640> A_IWL<2639> A_IWL<2638> A_IWL<2637> A_IWL<2636> A_IWL<2635> A_IWL<2634> A_IWL<2633> A_IWL<2632> A_IWL<2631> A_IWL<2630> A_IWL<2629> A_IWL<2628> A_IWL<2627> A_IWL<2626> A_IWL<2625> A_IWL<2624> A_IWL<2623> A_IWL<2622> A_IWL<2621> A_IWL<2620> A_IWL<2619> A_IWL<2618> A_IWL<2617> A_IWL<2616> A_IWL<2615> A_IWL<2614> A_IWL<2613> A_IWL<2612> A_IWL<2611> A_IWL<2610> A_IWL<2609> A_IWL<2608> A_IWL<2607> A_IWL<2606> A_IWL<2605> A_IWL<2604> A_IWL<2603> A_IWL<2602> A_IWL<2601> A_IWL<2600> A_IWL<2599> A_IWL<2598> A_IWL<2597> A_IWL<2596> A_IWL<2595> A_IWL<2594> A_IWL<2593> A_IWL<2592> A_IWL<2591> A_IWL<2590> A_IWL<2589> A_IWL<2588> A_IWL<2587> A_IWL<2586> A_IWL<2585> A_IWL<2584> A_IWL<2583> A_IWL<2582> A_IWL<2581> A_IWL<2580> A_IWL<2579> A_IWL<2578> A_IWL<2577> A_IWL<2576> A_IWL<2575> A_IWL<2574> A_IWL<2573> A_IWL<2572> A_IWL<2571> A_IWL<2570> A_IWL<2569> A_IWL<2568> A_IWL<2567> A_IWL<2566> A_IWL<2565> A_IWL<2564> A_IWL<2563> A_IWL<2562> A_IWL<2561> A_IWL<2560> B_BLC<41> B_BLC<40> B_BLC_TOP<41> B_BLC_TOP<40> B_BLT<41> B_BLT<40> B_BLT_TOP<41> B_BLT_TOP<40> B_IWL<2559> B_IWL<2558> B_IWL<2557> B_IWL<2556> B_IWL<2555> B_IWL<2554> B_IWL<2553> B_IWL<2552> B_IWL<2551> B_IWL<2550> B_IWL<2549> B_IWL<2548> B_IWL<2547> B_IWL<2546> B_IWL<2545> B_IWL<2544> B_IWL<2543> B_IWL<2542> B_IWL<2541> B_IWL<2540> B_IWL<2539> B_IWL<2538> B_IWL<2537> B_IWL<2536> B_IWL<2535> B_IWL<2534> B_IWL<2533> B_IWL<2532> B_IWL<2531> B_IWL<2530> B_IWL<2529> B_IWL<2528> B_IWL<2527> B_IWL<2526> B_IWL<2525> B_IWL<2524> B_IWL<2523> B_IWL<2522> B_IWL<2521> B_IWL<2520> B_IWL<2519> B_IWL<2518> B_IWL<2517> B_IWL<2516> B_IWL<2515> B_IWL<2514> B_IWL<2513> B_IWL<2512> B_IWL<2511> B_IWL<2510> B_IWL<2509> B_IWL<2508> B_IWL<2507> B_IWL<2506> B_IWL<2505> B_IWL<2504> B_IWL<2503> B_IWL<2502> B_IWL<2501> B_IWL<2500> B_IWL<2499> B_IWL<2498> B_IWL<2497> B_IWL<2496> B_IWL<2495> B_IWL<2494> B_IWL<2493> B_IWL<2492> B_IWL<2491> B_IWL<2490> B_IWL<2489> B_IWL<2488> B_IWL<2487> B_IWL<2486> B_IWL<2485> B_IWL<2484> B_IWL<2483> B_IWL<2482> B_IWL<2481> B_IWL<2480> B_IWL<2479> B_IWL<2478> B_IWL<2477> B_IWL<2476> B_IWL<2475> B_IWL<2474> B_IWL<2473> B_IWL<2472> B_IWL<2471> B_IWL<2470> B_IWL<2469> B_IWL<2468> B_IWL<2467> B_IWL<2466> B_IWL<2465> B_IWL<2464> B_IWL<2463> B_IWL<2462> B_IWL<2461> B_IWL<2460> B_IWL<2459> B_IWL<2458> B_IWL<2457> B_IWL<2456> B_IWL<2455> B_IWL<2454> B_IWL<2453> B_IWL<2452> B_IWL<2451> B_IWL<2450> B_IWL<2449> B_IWL<2448> B_IWL<2447> B_IWL<2446> B_IWL<2445> B_IWL<2444> B_IWL<2443> B_IWL<2442> B_IWL<2441> B_IWL<2440> B_IWL<2439> B_IWL<2438> B_IWL<2437> B_IWL<2436> B_IWL<2435> B_IWL<2434> B_IWL<2433> B_IWL<2432> B_IWL<2687> B_IWL<2686> B_IWL<2685> B_IWL<2684> B_IWL<2683> B_IWL<2682> B_IWL<2681> B_IWL<2680> B_IWL<2679> B_IWL<2678> B_IWL<2677> B_IWL<2676> B_IWL<2675> B_IWL<2674> B_IWL<2673> B_IWL<2672> B_IWL<2671> B_IWL<2670> B_IWL<2669> B_IWL<2668> B_IWL<2667> B_IWL<2666> B_IWL<2665> B_IWL<2664> B_IWL<2663> B_IWL<2662> B_IWL<2661> B_IWL<2660> B_IWL<2659> B_IWL<2658> B_IWL<2657> B_IWL<2656> B_IWL<2655> B_IWL<2654> B_IWL<2653> B_IWL<2652> B_IWL<2651> B_IWL<2650> B_IWL<2649> B_IWL<2648> B_IWL<2647> B_IWL<2646> B_IWL<2645> B_IWL<2644> B_IWL<2643> B_IWL<2642> B_IWL<2641> B_IWL<2640> B_IWL<2639> B_IWL<2638> B_IWL<2637> B_IWL<2636> B_IWL<2635> B_IWL<2634> B_IWL<2633> B_IWL<2632> B_IWL<2631> B_IWL<2630> B_IWL<2629> B_IWL<2628> B_IWL<2627> B_IWL<2626> B_IWL<2625> B_IWL<2624> B_IWL<2623> B_IWL<2622> B_IWL<2621> B_IWL<2620> B_IWL<2619> B_IWL<2618> B_IWL<2617> B_IWL<2616> B_IWL<2615> B_IWL<2614> B_IWL<2613> B_IWL<2612> B_IWL<2611> B_IWL<2610> B_IWL<2609> B_IWL<2608> B_IWL<2607> B_IWL<2606> B_IWL<2605> B_IWL<2604> B_IWL<2603> B_IWL<2602> B_IWL<2601> B_IWL<2600> B_IWL<2599> B_IWL<2598> B_IWL<2597> B_IWL<2596> B_IWL<2595> B_IWL<2594> B_IWL<2593> B_IWL<2592> B_IWL<2591> B_IWL<2590> B_IWL<2589> B_IWL<2588> B_IWL<2587> B_IWL<2586> B_IWL<2585> B_IWL<2584> B_IWL<2583> B_IWL<2582> B_IWL<2581> B_IWL<2580> B_IWL<2579> B_IWL<2578> B_IWL<2577> B_IWL<2576> B_IWL<2575> B_IWL<2574> B_IWL<2573> B_IWL<2572> B_IWL<2571> B_IWL<2570> B_IWL<2569> B_IWL<2568> B_IWL<2567> B_IWL<2566> B_IWL<2565> B_IWL<2564> B_IWL<2563> B_IWL<2562> B_IWL<2561> B_IWL<2560> VDD_CORE VSS / RM_IHPSG13_512x32_c2_2P_COLUMN_pcell_0 +XCOL<19> A_BLC<39> A_BLC<38> A_BLC_TOP<39> A_BLC_TOP<38> A_BLT<39> A_BLT<38> A_BLT_TOP<39> A_BLT_TOP<38> A_IWL<2431> A_IWL<2430> A_IWL<2429> A_IWL<2428> A_IWL<2427> A_IWL<2426> A_IWL<2425> A_IWL<2424> A_IWL<2423> A_IWL<2422> A_IWL<2421> A_IWL<2420> A_IWL<2419> A_IWL<2418> A_IWL<2417> A_IWL<2416> A_IWL<2415> A_IWL<2414> A_IWL<2413> A_IWL<2412> A_IWL<2411> A_IWL<2410> A_IWL<2409> A_IWL<2408> A_IWL<2407> A_IWL<2406> A_IWL<2405> A_IWL<2404> A_IWL<2403> A_IWL<2402> A_IWL<2401> A_IWL<2400> A_IWL<2399> A_IWL<2398> A_IWL<2397> A_IWL<2396> A_IWL<2395> A_IWL<2394> A_IWL<2393> A_IWL<2392> A_IWL<2391> A_IWL<2390> A_IWL<2389> A_IWL<2388> A_IWL<2387> A_IWL<2386> A_IWL<2385> A_IWL<2384> A_IWL<2383> A_IWL<2382> A_IWL<2381> A_IWL<2380> A_IWL<2379> A_IWL<2378> A_IWL<2377> A_IWL<2376> A_IWL<2375> A_IWL<2374> A_IWL<2373> A_IWL<2372> A_IWL<2371> A_IWL<2370> A_IWL<2369> A_IWL<2368> A_IWL<2367> A_IWL<2366> A_IWL<2365> A_IWL<2364> A_IWL<2363> A_IWL<2362> A_IWL<2361> A_IWL<2360> A_IWL<2359> A_IWL<2358> A_IWL<2357> A_IWL<2356> A_IWL<2355> A_IWL<2354> A_IWL<2353> A_IWL<2352> A_IWL<2351> A_IWL<2350> A_IWL<2349> A_IWL<2348> A_IWL<2347> A_IWL<2346> A_IWL<2345> A_IWL<2344> A_IWL<2343> A_IWL<2342> A_IWL<2341> A_IWL<2340> A_IWL<2339> A_IWL<2338> A_IWL<2337> A_IWL<2336> A_IWL<2335> A_IWL<2334> A_IWL<2333> A_IWL<2332> A_IWL<2331> A_IWL<2330> A_IWL<2329> A_IWL<2328> A_IWL<2327> A_IWL<2326> A_IWL<2325> A_IWL<2324> A_IWL<2323> A_IWL<2322> A_IWL<2321> A_IWL<2320> A_IWL<2319> A_IWL<2318> A_IWL<2317> A_IWL<2316> A_IWL<2315> A_IWL<2314> A_IWL<2313> A_IWL<2312> A_IWL<2311> A_IWL<2310> A_IWL<2309> A_IWL<2308> A_IWL<2307> A_IWL<2306> A_IWL<2305> A_IWL<2304> A_IWL<2559> A_IWL<2558> A_IWL<2557> A_IWL<2556> A_IWL<2555> A_IWL<2554> A_IWL<2553> A_IWL<2552> A_IWL<2551> A_IWL<2550> A_IWL<2549> A_IWL<2548> A_IWL<2547> A_IWL<2546> A_IWL<2545> A_IWL<2544> A_IWL<2543> A_IWL<2542> A_IWL<2541> A_IWL<2540> A_IWL<2539> A_IWL<2538> A_IWL<2537> A_IWL<2536> A_IWL<2535> A_IWL<2534> A_IWL<2533> A_IWL<2532> A_IWL<2531> A_IWL<2530> A_IWL<2529> A_IWL<2528> A_IWL<2527> A_IWL<2526> A_IWL<2525> A_IWL<2524> A_IWL<2523> A_IWL<2522> A_IWL<2521> A_IWL<2520> A_IWL<2519> A_IWL<2518> A_IWL<2517> A_IWL<2516> A_IWL<2515> A_IWL<2514> A_IWL<2513> A_IWL<2512> A_IWL<2511> A_IWL<2510> A_IWL<2509> A_IWL<2508> A_IWL<2507> A_IWL<2506> A_IWL<2505> A_IWL<2504> A_IWL<2503> A_IWL<2502> A_IWL<2501> A_IWL<2500> A_IWL<2499> A_IWL<2498> A_IWL<2497> A_IWL<2496> A_IWL<2495> A_IWL<2494> A_IWL<2493> A_IWL<2492> A_IWL<2491> A_IWL<2490> A_IWL<2489> A_IWL<2488> A_IWL<2487> A_IWL<2486> A_IWL<2485> A_IWL<2484> A_IWL<2483> A_IWL<2482> A_IWL<2481> A_IWL<2480> A_IWL<2479> A_IWL<2478> A_IWL<2477> A_IWL<2476> A_IWL<2475> A_IWL<2474> A_IWL<2473> A_IWL<2472> A_IWL<2471> A_IWL<2470> A_IWL<2469> A_IWL<2468> A_IWL<2467> A_IWL<2466> A_IWL<2465> A_IWL<2464> A_IWL<2463> A_IWL<2462> A_IWL<2461> A_IWL<2460> A_IWL<2459> A_IWL<2458> A_IWL<2457> A_IWL<2456> A_IWL<2455> A_IWL<2454> A_IWL<2453> A_IWL<2452> A_IWL<2451> A_IWL<2450> A_IWL<2449> A_IWL<2448> A_IWL<2447> A_IWL<2446> A_IWL<2445> A_IWL<2444> A_IWL<2443> A_IWL<2442> A_IWL<2441> A_IWL<2440> A_IWL<2439> A_IWL<2438> A_IWL<2437> A_IWL<2436> A_IWL<2435> A_IWL<2434> A_IWL<2433> A_IWL<2432> B_BLC<39> B_BLC<38> B_BLC_TOP<39> B_BLC_TOP<38> B_BLT<39> B_BLT<38> B_BLT_TOP<39> B_BLT_TOP<38> B_IWL<2431> B_IWL<2430> B_IWL<2429> B_IWL<2428> B_IWL<2427> B_IWL<2426> B_IWL<2425> B_IWL<2424> B_IWL<2423> B_IWL<2422> B_IWL<2421> B_IWL<2420> B_IWL<2419> B_IWL<2418> B_IWL<2417> B_IWL<2416> B_IWL<2415> B_IWL<2414> B_IWL<2413> B_IWL<2412> B_IWL<2411> B_IWL<2410> B_IWL<2409> B_IWL<2408> B_IWL<2407> B_IWL<2406> B_IWL<2405> B_IWL<2404> B_IWL<2403> B_IWL<2402> B_IWL<2401> B_IWL<2400> B_IWL<2399> B_IWL<2398> B_IWL<2397> B_IWL<2396> B_IWL<2395> B_IWL<2394> B_IWL<2393> B_IWL<2392> B_IWL<2391> B_IWL<2390> B_IWL<2389> B_IWL<2388> B_IWL<2387> B_IWL<2386> B_IWL<2385> B_IWL<2384> B_IWL<2383> B_IWL<2382> B_IWL<2381> B_IWL<2380> B_IWL<2379> B_IWL<2378> B_IWL<2377> B_IWL<2376> B_IWL<2375> B_IWL<2374> B_IWL<2373> B_IWL<2372> B_IWL<2371> B_IWL<2370> B_IWL<2369> B_IWL<2368> B_IWL<2367> B_IWL<2366> B_IWL<2365> B_IWL<2364> B_IWL<2363> B_IWL<2362> B_IWL<2361> B_IWL<2360> B_IWL<2359> B_IWL<2358> B_IWL<2357> B_IWL<2356> B_IWL<2355> B_IWL<2354> B_IWL<2353> B_IWL<2352> B_IWL<2351> B_IWL<2350> B_IWL<2349> B_IWL<2348> B_IWL<2347> B_IWL<2346> B_IWL<2345> B_IWL<2344> B_IWL<2343> B_IWL<2342> B_IWL<2341> B_IWL<2340> B_IWL<2339> B_IWL<2338> B_IWL<2337> B_IWL<2336> B_IWL<2335> B_IWL<2334> B_IWL<2333> B_IWL<2332> B_IWL<2331> B_IWL<2330> B_IWL<2329> B_IWL<2328> B_IWL<2327> B_IWL<2326> B_IWL<2325> B_IWL<2324> B_IWL<2323> B_IWL<2322> B_IWL<2321> B_IWL<2320> B_IWL<2319> B_IWL<2318> B_IWL<2317> B_IWL<2316> B_IWL<2315> B_IWL<2314> B_IWL<2313> B_IWL<2312> B_IWL<2311> B_IWL<2310> B_IWL<2309> B_IWL<2308> B_IWL<2307> B_IWL<2306> B_IWL<2305> B_IWL<2304> B_IWL<2559> B_IWL<2558> B_IWL<2557> B_IWL<2556> B_IWL<2555> B_IWL<2554> B_IWL<2553> B_IWL<2552> B_IWL<2551> B_IWL<2550> B_IWL<2549> B_IWL<2548> B_IWL<2547> B_IWL<2546> B_IWL<2545> B_IWL<2544> B_IWL<2543> B_IWL<2542> B_IWL<2541> B_IWL<2540> B_IWL<2539> B_IWL<2538> B_IWL<2537> B_IWL<2536> B_IWL<2535> B_IWL<2534> B_IWL<2533> B_IWL<2532> B_IWL<2531> B_IWL<2530> B_IWL<2529> B_IWL<2528> B_IWL<2527> B_IWL<2526> B_IWL<2525> B_IWL<2524> B_IWL<2523> B_IWL<2522> B_IWL<2521> B_IWL<2520> B_IWL<2519> B_IWL<2518> B_IWL<2517> B_IWL<2516> B_IWL<2515> B_IWL<2514> B_IWL<2513> B_IWL<2512> B_IWL<2511> B_IWL<2510> B_IWL<2509> B_IWL<2508> B_IWL<2507> B_IWL<2506> B_IWL<2505> B_IWL<2504> B_IWL<2503> B_IWL<2502> B_IWL<2501> B_IWL<2500> B_IWL<2499> B_IWL<2498> B_IWL<2497> B_IWL<2496> B_IWL<2495> B_IWL<2494> B_IWL<2493> B_IWL<2492> B_IWL<2491> B_IWL<2490> B_IWL<2489> B_IWL<2488> B_IWL<2487> B_IWL<2486> B_IWL<2485> B_IWL<2484> B_IWL<2483> B_IWL<2482> B_IWL<2481> B_IWL<2480> B_IWL<2479> B_IWL<2478> B_IWL<2477> B_IWL<2476> B_IWL<2475> B_IWL<2474> B_IWL<2473> B_IWL<2472> B_IWL<2471> B_IWL<2470> B_IWL<2469> B_IWL<2468> B_IWL<2467> B_IWL<2466> B_IWL<2465> B_IWL<2464> B_IWL<2463> B_IWL<2462> B_IWL<2461> B_IWL<2460> B_IWL<2459> B_IWL<2458> B_IWL<2457> B_IWL<2456> B_IWL<2455> B_IWL<2454> B_IWL<2453> B_IWL<2452> B_IWL<2451> B_IWL<2450> B_IWL<2449> B_IWL<2448> B_IWL<2447> B_IWL<2446> B_IWL<2445> B_IWL<2444> B_IWL<2443> B_IWL<2442> B_IWL<2441> B_IWL<2440> B_IWL<2439> B_IWL<2438> B_IWL<2437> B_IWL<2436> B_IWL<2435> B_IWL<2434> B_IWL<2433> B_IWL<2432> VDD_CORE VSS / RM_IHPSG13_512x32_c2_2P_COLUMN_pcell_0 +XCOL<18> A_BLC<37> A_BLC<36> A_BLC_TOP<37> A_BLC_TOP<36> A_BLT<37> A_BLT<36> A_BLT_TOP<37> A_BLT_TOP<36> A_IWL<2303> A_IWL<2302> A_IWL<2301> A_IWL<2300> A_IWL<2299> A_IWL<2298> A_IWL<2297> A_IWL<2296> A_IWL<2295> A_IWL<2294> A_IWL<2293> A_IWL<2292> A_IWL<2291> A_IWL<2290> A_IWL<2289> A_IWL<2288> A_IWL<2287> A_IWL<2286> A_IWL<2285> A_IWL<2284> A_IWL<2283> A_IWL<2282> A_IWL<2281> A_IWL<2280> A_IWL<2279> A_IWL<2278> A_IWL<2277> A_IWL<2276> A_IWL<2275> A_IWL<2274> A_IWL<2273> A_IWL<2272> A_IWL<2271> A_IWL<2270> A_IWL<2269> A_IWL<2268> A_IWL<2267> A_IWL<2266> A_IWL<2265> A_IWL<2264> A_IWL<2263> A_IWL<2262> A_IWL<2261> A_IWL<2260> A_IWL<2259> A_IWL<2258> A_IWL<2257> A_IWL<2256> A_IWL<2255> A_IWL<2254> A_IWL<2253> A_IWL<2252> A_IWL<2251> A_IWL<2250> A_IWL<2249> A_IWL<2248> A_IWL<2247> A_IWL<2246> A_IWL<2245> A_IWL<2244> A_IWL<2243> A_IWL<2242> A_IWL<2241> A_IWL<2240> A_IWL<2239> A_IWL<2238> A_IWL<2237> A_IWL<2236> A_IWL<2235> A_IWL<2234> A_IWL<2233> A_IWL<2232> A_IWL<2231> A_IWL<2230> A_IWL<2229> A_IWL<2228> A_IWL<2227> A_IWL<2226> A_IWL<2225> A_IWL<2224> A_IWL<2223> A_IWL<2222> A_IWL<2221> A_IWL<2220> A_IWL<2219> A_IWL<2218> A_IWL<2217> A_IWL<2216> A_IWL<2215> A_IWL<2214> A_IWL<2213> A_IWL<2212> A_IWL<2211> A_IWL<2210> A_IWL<2209> A_IWL<2208> A_IWL<2207> A_IWL<2206> A_IWL<2205> A_IWL<2204> A_IWL<2203> A_IWL<2202> A_IWL<2201> A_IWL<2200> A_IWL<2199> A_IWL<2198> A_IWL<2197> A_IWL<2196> A_IWL<2195> A_IWL<2194> A_IWL<2193> A_IWL<2192> A_IWL<2191> A_IWL<2190> A_IWL<2189> A_IWL<2188> A_IWL<2187> A_IWL<2186> A_IWL<2185> A_IWL<2184> A_IWL<2183> A_IWL<2182> A_IWL<2181> A_IWL<2180> A_IWL<2179> A_IWL<2178> A_IWL<2177> A_IWL<2176> A_IWL<2431> A_IWL<2430> A_IWL<2429> A_IWL<2428> A_IWL<2427> A_IWL<2426> A_IWL<2425> A_IWL<2424> A_IWL<2423> A_IWL<2422> A_IWL<2421> A_IWL<2420> A_IWL<2419> A_IWL<2418> A_IWL<2417> A_IWL<2416> A_IWL<2415> A_IWL<2414> A_IWL<2413> A_IWL<2412> A_IWL<2411> A_IWL<2410> A_IWL<2409> A_IWL<2408> A_IWL<2407> A_IWL<2406> A_IWL<2405> A_IWL<2404> A_IWL<2403> A_IWL<2402> A_IWL<2401> A_IWL<2400> A_IWL<2399> A_IWL<2398> A_IWL<2397> A_IWL<2396> A_IWL<2395> A_IWL<2394> A_IWL<2393> A_IWL<2392> A_IWL<2391> A_IWL<2390> A_IWL<2389> A_IWL<2388> A_IWL<2387> A_IWL<2386> A_IWL<2385> A_IWL<2384> A_IWL<2383> A_IWL<2382> A_IWL<2381> A_IWL<2380> A_IWL<2379> A_IWL<2378> A_IWL<2377> A_IWL<2376> A_IWL<2375> A_IWL<2374> A_IWL<2373> A_IWL<2372> A_IWL<2371> A_IWL<2370> A_IWL<2369> A_IWL<2368> A_IWL<2367> A_IWL<2366> A_IWL<2365> A_IWL<2364> A_IWL<2363> A_IWL<2362> A_IWL<2361> A_IWL<2360> A_IWL<2359> A_IWL<2358> A_IWL<2357> A_IWL<2356> A_IWL<2355> A_IWL<2354> A_IWL<2353> A_IWL<2352> A_IWL<2351> A_IWL<2350> A_IWL<2349> A_IWL<2348> A_IWL<2347> A_IWL<2346> A_IWL<2345> A_IWL<2344> A_IWL<2343> A_IWL<2342> A_IWL<2341> A_IWL<2340> A_IWL<2339> A_IWL<2338> A_IWL<2337> A_IWL<2336> A_IWL<2335> A_IWL<2334> A_IWL<2333> A_IWL<2332> A_IWL<2331> A_IWL<2330> A_IWL<2329> A_IWL<2328> A_IWL<2327> A_IWL<2326> A_IWL<2325> A_IWL<2324> A_IWL<2323> A_IWL<2322> A_IWL<2321> A_IWL<2320> A_IWL<2319> A_IWL<2318> A_IWL<2317> A_IWL<2316> A_IWL<2315> A_IWL<2314> A_IWL<2313> A_IWL<2312> A_IWL<2311> A_IWL<2310> A_IWL<2309> A_IWL<2308> A_IWL<2307> A_IWL<2306> A_IWL<2305> A_IWL<2304> B_BLC<37> B_BLC<36> B_BLC_TOP<37> B_BLC_TOP<36> B_BLT<37> B_BLT<36> B_BLT_TOP<37> B_BLT_TOP<36> B_IWL<2303> B_IWL<2302> B_IWL<2301> B_IWL<2300> B_IWL<2299> B_IWL<2298> B_IWL<2297> B_IWL<2296> B_IWL<2295> B_IWL<2294> B_IWL<2293> B_IWL<2292> B_IWL<2291> B_IWL<2290> B_IWL<2289> B_IWL<2288> B_IWL<2287> B_IWL<2286> B_IWL<2285> B_IWL<2284> B_IWL<2283> B_IWL<2282> B_IWL<2281> B_IWL<2280> B_IWL<2279> B_IWL<2278> B_IWL<2277> B_IWL<2276> B_IWL<2275> B_IWL<2274> B_IWL<2273> B_IWL<2272> B_IWL<2271> B_IWL<2270> B_IWL<2269> B_IWL<2268> B_IWL<2267> B_IWL<2266> B_IWL<2265> B_IWL<2264> B_IWL<2263> B_IWL<2262> B_IWL<2261> B_IWL<2260> B_IWL<2259> B_IWL<2258> B_IWL<2257> B_IWL<2256> B_IWL<2255> B_IWL<2254> B_IWL<2253> B_IWL<2252> B_IWL<2251> B_IWL<2250> B_IWL<2249> B_IWL<2248> B_IWL<2247> B_IWL<2246> B_IWL<2245> B_IWL<2244> B_IWL<2243> B_IWL<2242> B_IWL<2241> B_IWL<2240> B_IWL<2239> B_IWL<2238> B_IWL<2237> B_IWL<2236> B_IWL<2235> B_IWL<2234> B_IWL<2233> B_IWL<2232> B_IWL<2231> B_IWL<2230> B_IWL<2229> B_IWL<2228> B_IWL<2227> B_IWL<2226> B_IWL<2225> B_IWL<2224> B_IWL<2223> B_IWL<2222> B_IWL<2221> B_IWL<2220> B_IWL<2219> B_IWL<2218> B_IWL<2217> B_IWL<2216> B_IWL<2215> B_IWL<2214> B_IWL<2213> B_IWL<2212> B_IWL<2211> B_IWL<2210> B_IWL<2209> B_IWL<2208> B_IWL<2207> B_IWL<2206> B_IWL<2205> B_IWL<2204> B_IWL<2203> B_IWL<2202> B_IWL<2201> B_IWL<2200> B_IWL<2199> B_IWL<2198> B_IWL<2197> B_IWL<2196> B_IWL<2195> B_IWL<2194> B_IWL<2193> B_IWL<2192> B_IWL<2191> B_IWL<2190> B_IWL<2189> B_IWL<2188> B_IWL<2187> B_IWL<2186> B_IWL<2185> B_IWL<2184> B_IWL<2183> B_IWL<2182> B_IWL<2181> B_IWL<2180> B_IWL<2179> B_IWL<2178> B_IWL<2177> B_IWL<2176> B_IWL<2431> B_IWL<2430> B_IWL<2429> B_IWL<2428> B_IWL<2427> B_IWL<2426> B_IWL<2425> B_IWL<2424> B_IWL<2423> B_IWL<2422> B_IWL<2421> B_IWL<2420> B_IWL<2419> B_IWL<2418> B_IWL<2417> B_IWL<2416> B_IWL<2415> B_IWL<2414> B_IWL<2413> B_IWL<2412> B_IWL<2411> B_IWL<2410> B_IWL<2409> B_IWL<2408> B_IWL<2407> B_IWL<2406> B_IWL<2405> B_IWL<2404> B_IWL<2403> B_IWL<2402> B_IWL<2401> B_IWL<2400> B_IWL<2399> B_IWL<2398> B_IWL<2397> B_IWL<2396> B_IWL<2395> B_IWL<2394> B_IWL<2393> B_IWL<2392> B_IWL<2391> B_IWL<2390> B_IWL<2389> B_IWL<2388> B_IWL<2387> B_IWL<2386> B_IWL<2385> B_IWL<2384> B_IWL<2383> B_IWL<2382> B_IWL<2381> B_IWL<2380> B_IWL<2379> B_IWL<2378> B_IWL<2377> B_IWL<2376> B_IWL<2375> B_IWL<2374> B_IWL<2373> B_IWL<2372> B_IWL<2371> B_IWL<2370> B_IWL<2369> B_IWL<2368> B_IWL<2367> B_IWL<2366> B_IWL<2365> B_IWL<2364> B_IWL<2363> B_IWL<2362> B_IWL<2361> B_IWL<2360> B_IWL<2359> B_IWL<2358> B_IWL<2357> B_IWL<2356> B_IWL<2355> B_IWL<2354> B_IWL<2353> B_IWL<2352> B_IWL<2351> B_IWL<2350> B_IWL<2349> B_IWL<2348> B_IWL<2347> B_IWL<2346> B_IWL<2345> B_IWL<2344> B_IWL<2343> B_IWL<2342> B_IWL<2341> B_IWL<2340> B_IWL<2339> B_IWL<2338> B_IWL<2337> B_IWL<2336> B_IWL<2335> B_IWL<2334> B_IWL<2333> B_IWL<2332> B_IWL<2331> B_IWL<2330> B_IWL<2329> B_IWL<2328> B_IWL<2327> B_IWL<2326> B_IWL<2325> B_IWL<2324> B_IWL<2323> B_IWL<2322> B_IWL<2321> B_IWL<2320> B_IWL<2319> B_IWL<2318> B_IWL<2317> B_IWL<2316> B_IWL<2315> B_IWL<2314> B_IWL<2313> B_IWL<2312> B_IWL<2311> B_IWL<2310> B_IWL<2309> B_IWL<2308> B_IWL<2307> B_IWL<2306> B_IWL<2305> B_IWL<2304> VDD_CORE VSS / RM_IHPSG13_512x32_c2_2P_COLUMN_pcell_0 +XCOL<17> A_BLC<35> A_BLC<34> A_BLC_TOP<35> A_BLC_TOP<34> A_BLT<35> A_BLT<34> A_BLT_TOP<35> A_BLT_TOP<34> A_IWL<2175> A_IWL<2174> A_IWL<2173> A_IWL<2172> A_IWL<2171> A_IWL<2170> A_IWL<2169> A_IWL<2168> A_IWL<2167> A_IWL<2166> A_IWL<2165> A_IWL<2164> A_IWL<2163> A_IWL<2162> A_IWL<2161> A_IWL<2160> A_IWL<2159> A_IWL<2158> A_IWL<2157> A_IWL<2156> A_IWL<2155> A_IWL<2154> A_IWL<2153> A_IWL<2152> A_IWL<2151> A_IWL<2150> A_IWL<2149> A_IWL<2148> A_IWL<2147> A_IWL<2146> A_IWL<2145> A_IWL<2144> A_IWL<2143> A_IWL<2142> A_IWL<2141> A_IWL<2140> A_IWL<2139> A_IWL<2138> A_IWL<2137> A_IWL<2136> A_IWL<2135> A_IWL<2134> A_IWL<2133> A_IWL<2132> A_IWL<2131> A_IWL<2130> A_IWL<2129> A_IWL<2128> A_IWL<2127> A_IWL<2126> A_IWL<2125> A_IWL<2124> A_IWL<2123> A_IWL<2122> A_IWL<2121> A_IWL<2120> A_IWL<2119> A_IWL<2118> A_IWL<2117> A_IWL<2116> A_IWL<2115> A_IWL<2114> A_IWL<2113> A_IWL<2112> A_IWL<2111> A_IWL<2110> A_IWL<2109> A_IWL<2108> A_IWL<2107> A_IWL<2106> A_IWL<2105> A_IWL<2104> A_IWL<2103> A_IWL<2102> A_IWL<2101> A_IWL<2100> A_IWL<2099> A_IWL<2098> A_IWL<2097> A_IWL<2096> A_IWL<2095> A_IWL<2094> A_IWL<2093> A_IWL<2092> A_IWL<2091> A_IWL<2090> A_IWL<2089> A_IWL<2088> A_IWL<2087> A_IWL<2086> A_IWL<2085> A_IWL<2084> A_IWL<2083> A_IWL<2082> A_IWL<2081> A_IWL<2080> A_IWL<2079> A_IWL<2078> A_IWL<2077> A_IWL<2076> A_IWL<2075> A_IWL<2074> A_IWL<2073> A_IWL<2072> A_IWL<2071> A_IWL<2070> A_IWL<2069> A_IWL<2068> A_IWL<2067> A_IWL<2066> A_IWL<2065> A_IWL<2064> A_IWL<2063> A_IWL<2062> A_IWL<2061> A_IWL<2060> A_IWL<2059> A_IWL<2058> A_IWL<2057> A_IWL<2056> A_IWL<2055> A_IWL<2054> A_IWL<2053> A_IWL<2052> A_IWL<2051> A_IWL<2050> A_IWL<2049> A_IWL<2048> A_IWL<2303> A_IWL<2302> A_IWL<2301> A_IWL<2300> A_IWL<2299> A_IWL<2298> A_IWL<2297> A_IWL<2296> A_IWL<2295> A_IWL<2294> A_IWL<2293> A_IWL<2292> A_IWL<2291> A_IWL<2290> A_IWL<2289> A_IWL<2288> A_IWL<2287> A_IWL<2286> A_IWL<2285> A_IWL<2284> A_IWL<2283> A_IWL<2282> A_IWL<2281> A_IWL<2280> A_IWL<2279> A_IWL<2278> A_IWL<2277> A_IWL<2276> A_IWL<2275> A_IWL<2274> A_IWL<2273> A_IWL<2272> A_IWL<2271> A_IWL<2270> A_IWL<2269> A_IWL<2268> A_IWL<2267> A_IWL<2266> A_IWL<2265> A_IWL<2264> A_IWL<2263> A_IWL<2262> A_IWL<2261> A_IWL<2260> A_IWL<2259> A_IWL<2258> A_IWL<2257> A_IWL<2256> A_IWL<2255> A_IWL<2254> A_IWL<2253> A_IWL<2252> A_IWL<2251> A_IWL<2250> A_IWL<2249> A_IWL<2248> A_IWL<2247> A_IWL<2246> A_IWL<2245> A_IWL<2244> A_IWL<2243> A_IWL<2242> A_IWL<2241> A_IWL<2240> A_IWL<2239> A_IWL<2238> A_IWL<2237> A_IWL<2236> A_IWL<2235> A_IWL<2234> A_IWL<2233> A_IWL<2232> A_IWL<2231> A_IWL<2230> A_IWL<2229> A_IWL<2228> A_IWL<2227> A_IWL<2226> A_IWL<2225> A_IWL<2224> A_IWL<2223> A_IWL<2222> A_IWL<2221> A_IWL<2220> A_IWL<2219> A_IWL<2218> A_IWL<2217> A_IWL<2216> A_IWL<2215> A_IWL<2214> A_IWL<2213> A_IWL<2212> A_IWL<2211> A_IWL<2210> A_IWL<2209> A_IWL<2208> A_IWL<2207> A_IWL<2206> A_IWL<2205> A_IWL<2204> A_IWL<2203> A_IWL<2202> A_IWL<2201> A_IWL<2200> A_IWL<2199> A_IWL<2198> A_IWL<2197> A_IWL<2196> A_IWL<2195> A_IWL<2194> A_IWL<2193> A_IWL<2192> A_IWL<2191> A_IWL<2190> A_IWL<2189> A_IWL<2188> A_IWL<2187> A_IWL<2186> A_IWL<2185> A_IWL<2184> A_IWL<2183> A_IWL<2182> A_IWL<2181> A_IWL<2180> A_IWL<2179> A_IWL<2178> A_IWL<2177> A_IWL<2176> B_BLC<35> B_BLC<34> B_BLC_TOP<35> B_BLC_TOP<34> B_BLT<35> B_BLT<34> B_BLT_TOP<35> B_BLT_TOP<34> B_IWL<2175> B_IWL<2174> B_IWL<2173> B_IWL<2172> B_IWL<2171> B_IWL<2170> B_IWL<2169> B_IWL<2168> B_IWL<2167> B_IWL<2166> B_IWL<2165> B_IWL<2164> B_IWL<2163> B_IWL<2162> B_IWL<2161> B_IWL<2160> B_IWL<2159> B_IWL<2158> B_IWL<2157> B_IWL<2156> B_IWL<2155> B_IWL<2154> B_IWL<2153> B_IWL<2152> B_IWL<2151> B_IWL<2150> B_IWL<2149> B_IWL<2148> B_IWL<2147> B_IWL<2146> B_IWL<2145> B_IWL<2144> B_IWL<2143> B_IWL<2142> B_IWL<2141> B_IWL<2140> B_IWL<2139> B_IWL<2138> B_IWL<2137> B_IWL<2136> B_IWL<2135> B_IWL<2134> B_IWL<2133> B_IWL<2132> B_IWL<2131> B_IWL<2130> B_IWL<2129> B_IWL<2128> B_IWL<2127> B_IWL<2126> B_IWL<2125> B_IWL<2124> B_IWL<2123> B_IWL<2122> B_IWL<2121> B_IWL<2120> B_IWL<2119> B_IWL<2118> B_IWL<2117> B_IWL<2116> B_IWL<2115> B_IWL<2114> B_IWL<2113> B_IWL<2112> B_IWL<2111> B_IWL<2110> B_IWL<2109> B_IWL<2108> B_IWL<2107> B_IWL<2106> B_IWL<2105> B_IWL<2104> B_IWL<2103> B_IWL<2102> B_IWL<2101> B_IWL<2100> B_IWL<2099> B_IWL<2098> B_IWL<2097> B_IWL<2096> B_IWL<2095> B_IWL<2094> B_IWL<2093> B_IWL<2092> B_IWL<2091> B_IWL<2090> B_IWL<2089> B_IWL<2088> B_IWL<2087> B_IWL<2086> B_IWL<2085> B_IWL<2084> B_IWL<2083> B_IWL<2082> B_IWL<2081> B_IWL<2080> B_IWL<2079> B_IWL<2078> B_IWL<2077> B_IWL<2076> B_IWL<2075> B_IWL<2074> B_IWL<2073> B_IWL<2072> B_IWL<2071> B_IWL<2070> B_IWL<2069> B_IWL<2068> B_IWL<2067> B_IWL<2066> B_IWL<2065> B_IWL<2064> B_IWL<2063> B_IWL<2062> B_IWL<2061> B_IWL<2060> B_IWL<2059> B_IWL<2058> B_IWL<2057> B_IWL<2056> B_IWL<2055> B_IWL<2054> B_IWL<2053> B_IWL<2052> B_IWL<2051> B_IWL<2050> B_IWL<2049> B_IWL<2048> B_IWL<2303> B_IWL<2302> B_IWL<2301> B_IWL<2300> B_IWL<2299> B_IWL<2298> B_IWL<2297> B_IWL<2296> B_IWL<2295> B_IWL<2294> B_IWL<2293> B_IWL<2292> B_IWL<2291> B_IWL<2290> B_IWL<2289> B_IWL<2288> B_IWL<2287> B_IWL<2286> B_IWL<2285> B_IWL<2284> B_IWL<2283> B_IWL<2282> B_IWL<2281> B_IWL<2280> B_IWL<2279> B_IWL<2278> B_IWL<2277> B_IWL<2276> B_IWL<2275> B_IWL<2274> B_IWL<2273> B_IWL<2272> B_IWL<2271> B_IWL<2270> B_IWL<2269> B_IWL<2268> B_IWL<2267> B_IWL<2266> B_IWL<2265> B_IWL<2264> B_IWL<2263> B_IWL<2262> B_IWL<2261> B_IWL<2260> B_IWL<2259> B_IWL<2258> B_IWL<2257> B_IWL<2256> B_IWL<2255> B_IWL<2254> B_IWL<2253> B_IWL<2252> B_IWL<2251> B_IWL<2250> B_IWL<2249> B_IWL<2248> B_IWL<2247> B_IWL<2246> B_IWL<2245> B_IWL<2244> B_IWL<2243> B_IWL<2242> B_IWL<2241> B_IWL<2240> B_IWL<2239> B_IWL<2238> B_IWL<2237> B_IWL<2236> B_IWL<2235> B_IWL<2234> B_IWL<2233> B_IWL<2232> B_IWL<2231> B_IWL<2230> B_IWL<2229> B_IWL<2228> B_IWL<2227> B_IWL<2226> B_IWL<2225> B_IWL<2224> B_IWL<2223> B_IWL<2222> B_IWL<2221> B_IWL<2220> B_IWL<2219> B_IWL<2218> B_IWL<2217> B_IWL<2216> B_IWL<2215> B_IWL<2214> B_IWL<2213> B_IWL<2212> B_IWL<2211> B_IWL<2210> B_IWL<2209> B_IWL<2208> B_IWL<2207> B_IWL<2206> B_IWL<2205> B_IWL<2204> B_IWL<2203> B_IWL<2202> B_IWL<2201> B_IWL<2200> B_IWL<2199> B_IWL<2198> B_IWL<2197> B_IWL<2196> B_IWL<2195> B_IWL<2194> B_IWL<2193> B_IWL<2192> B_IWL<2191> B_IWL<2190> B_IWL<2189> B_IWL<2188> B_IWL<2187> B_IWL<2186> B_IWL<2185> B_IWL<2184> B_IWL<2183> B_IWL<2182> B_IWL<2181> B_IWL<2180> B_IWL<2179> B_IWL<2178> B_IWL<2177> B_IWL<2176> VDD_CORE VSS / RM_IHPSG13_512x32_c2_2P_COLUMN_pcell_0 +XCOL<16> A_BLC<33> A_BLC<32> A_BLC_TOP<33> A_BLC_TOP<32> A_BLT<33> A_BLT<32> A_BLT_TOP<33> A_BLT_TOP<32> A_IWL<2047> A_IWL<2046> A_IWL<2045> A_IWL<2044> A_IWL<2043> A_IWL<2042> A_IWL<2041> A_IWL<2040> A_IWL<2039> A_IWL<2038> A_IWL<2037> A_IWL<2036> A_IWL<2035> A_IWL<2034> A_IWL<2033> A_IWL<2032> A_IWL<2031> A_IWL<2030> A_IWL<2029> A_IWL<2028> A_IWL<2027> A_IWL<2026> A_IWL<2025> A_IWL<2024> A_IWL<2023> A_IWL<2022> A_IWL<2021> A_IWL<2020> A_IWL<2019> A_IWL<2018> A_IWL<2017> A_IWL<2016> A_IWL<2015> A_IWL<2014> A_IWL<2013> A_IWL<2012> A_IWL<2011> A_IWL<2010> A_IWL<2009> A_IWL<2008> A_IWL<2007> A_IWL<2006> A_IWL<2005> A_IWL<2004> A_IWL<2003> A_IWL<2002> A_IWL<2001> A_IWL<2000> A_IWL<1999> A_IWL<1998> A_IWL<1997> A_IWL<1996> A_IWL<1995> A_IWL<1994> A_IWL<1993> A_IWL<1992> A_IWL<1991> A_IWL<1990> A_IWL<1989> A_IWL<1988> A_IWL<1987> A_IWL<1986> A_IWL<1985> A_IWL<1984> A_IWL<1983> A_IWL<1982> A_IWL<1981> A_IWL<1980> A_IWL<1979> A_IWL<1978> A_IWL<1977> A_IWL<1976> A_IWL<1975> A_IWL<1974> A_IWL<1973> A_IWL<1972> A_IWL<1971> A_IWL<1970> A_IWL<1969> A_IWL<1968> A_IWL<1967> A_IWL<1966> A_IWL<1965> A_IWL<1964> A_IWL<1963> A_IWL<1962> A_IWL<1961> A_IWL<1960> A_IWL<1959> A_IWL<1958> A_IWL<1957> A_IWL<1956> A_IWL<1955> A_IWL<1954> A_IWL<1953> A_IWL<1952> A_IWL<1951> A_IWL<1950> A_IWL<1949> A_IWL<1948> A_IWL<1947> A_IWL<1946> A_IWL<1945> A_IWL<1944> A_IWL<1943> A_IWL<1942> A_IWL<1941> A_IWL<1940> A_IWL<1939> A_IWL<1938> A_IWL<1937> A_IWL<1936> A_IWL<1935> A_IWL<1934> A_IWL<1933> A_IWL<1932> A_IWL<1931> A_IWL<1930> A_IWL<1929> A_IWL<1928> A_IWL<1927> A_IWL<1926> A_IWL<1925> A_IWL<1924> A_IWL<1923> A_IWL<1922> A_IWL<1921> A_IWL<1920> A_IWL<2175> A_IWL<2174> A_IWL<2173> A_IWL<2172> A_IWL<2171> A_IWL<2170> A_IWL<2169> A_IWL<2168> A_IWL<2167> A_IWL<2166> A_IWL<2165> A_IWL<2164> A_IWL<2163> A_IWL<2162> A_IWL<2161> A_IWL<2160> A_IWL<2159> A_IWL<2158> A_IWL<2157> A_IWL<2156> A_IWL<2155> A_IWL<2154> A_IWL<2153> A_IWL<2152> A_IWL<2151> A_IWL<2150> A_IWL<2149> A_IWL<2148> A_IWL<2147> A_IWL<2146> A_IWL<2145> A_IWL<2144> A_IWL<2143> A_IWL<2142> A_IWL<2141> A_IWL<2140> A_IWL<2139> A_IWL<2138> A_IWL<2137> A_IWL<2136> A_IWL<2135> A_IWL<2134> A_IWL<2133> A_IWL<2132> A_IWL<2131> A_IWL<2130> A_IWL<2129> A_IWL<2128> A_IWL<2127> A_IWL<2126> A_IWL<2125> A_IWL<2124> A_IWL<2123> A_IWL<2122> A_IWL<2121> A_IWL<2120> A_IWL<2119> A_IWL<2118> A_IWL<2117> A_IWL<2116> A_IWL<2115> A_IWL<2114> A_IWL<2113> A_IWL<2112> A_IWL<2111> A_IWL<2110> A_IWL<2109> A_IWL<2108> A_IWL<2107> A_IWL<2106> A_IWL<2105> A_IWL<2104> A_IWL<2103> A_IWL<2102> A_IWL<2101> A_IWL<2100> A_IWL<2099> A_IWL<2098> A_IWL<2097> A_IWL<2096> A_IWL<2095> A_IWL<2094> A_IWL<2093> A_IWL<2092> A_IWL<2091> A_IWL<2090> A_IWL<2089> A_IWL<2088> A_IWL<2087> A_IWL<2086> A_IWL<2085> A_IWL<2084> A_IWL<2083> A_IWL<2082> A_IWL<2081> A_IWL<2080> A_IWL<2079> A_IWL<2078> A_IWL<2077> A_IWL<2076> A_IWL<2075> A_IWL<2074> A_IWL<2073> A_IWL<2072> A_IWL<2071> A_IWL<2070> A_IWL<2069> A_IWL<2068> A_IWL<2067> A_IWL<2066> A_IWL<2065> A_IWL<2064> A_IWL<2063> A_IWL<2062> A_IWL<2061> A_IWL<2060> A_IWL<2059> A_IWL<2058> A_IWL<2057> A_IWL<2056> A_IWL<2055> A_IWL<2054> A_IWL<2053> A_IWL<2052> A_IWL<2051> A_IWL<2050> A_IWL<2049> A_IWL<2048> B_BLC<33> B_BLC<32> B_BLC_TOP<33> B_BLC_TOP<32> B_BLT<33> B_BLT<32> B_BLT_TOP<33> B_BLT_TOP<32> B_IWL<2047> B_IWL<2046> B_IWL<2045> B_IWL<2044> B_IWL<2043> B_IWL<2042> B_IWL<2041> B_IWL<2040> B_IWL<2039> B_IWL<2038> B_IWL<2037> B_IWL<2036> B_IWL<2035> B_IWL<2034> B_IWL<2033> B_IWL<2032> B_IWL<2031> B_IWL<2030> B_IWL<2029> B_IWL<2028> B_IWL<2027> B_IWL<2026> B_IWL<2025> B_IWL<2024> B_IWL<2023> B_IWL<2022> B_IWL<2021> B_IWL<2020> B_IWL<2019> B_IWL<2018> B_IWL<2017> B_IWL<2016> B_IWL<2015> B_IWL<2014> B_IWL<2013> B_IWL<2012> B_IWL<2011> B_IWL<2010> B_IWL<2009> B_IWL<2008> B_IWL<2007> B_IWL<2006> B_IWL<2005> B_IWL<2004> B_IWL<2003> B_IWL<2002> B_IWL<2001> B_IWL<2000> B_IWL<1999> B_IWL<1998> B_IWL<1997> B_IWL<1996> B_IWL<1995> B_IWL<1994> B_IWL<1993> B_IWL<1992> B_IWL<1991> B_IWL<1990> B_IWL<1989> B_IWL<1988> B_IWL<1987> B_IWL<1986> B_IWL<1985> B_IWL<1984> B_IWL<1983> B_IWL<1982> B_IWL<1981> B_IWL<1980> B_IWL<1979> B_IWL<1978> B_IWL<1977> B_IWL<1976> B_IWL<1975> B_IWL<1974> B_IWL<1973> B_IWL<1972> B_IWL<1971> B_IWL<1970> B_IWL<1969> B_IWL<1968> B_IWL<1967> B_IWL<1966> B_IWL<1965> B_IWL<1964> B_IWL<1963> B_IWL<1962> B_IWL<1961> B_IWL<1960> B_IWL<1959> B_IWL<1958> B_IWL<1957> B_IWL<1956> B_IWL<1955> B_IWL<1954> B_IWL<1953> B_IWL<1952> B_IWL<1951> B_IWL<1950> B_IWL<1949> B_IWL<1948> B_IWL<1947> B_IWL<1946> B_IWL<1945> B_IWL<1944> B_IWL<1943> B_IWL<1942> B_IWL<1941> B_IWL<1940> B_IWL<1939> B_IWL<1938> B_IWL<1937> B_IWL<1936> B_IWL<1935> B_IWL<1934> B_IWL<1933> B_IWL<1932> B_IWL<1931> B_IWL<1930> B_IWL<1929> B_IWL<1928> B_IWL<1927> B_IWL<1926> B_IWL<1925> B_IWL<1924> B_IWL<1923> B_IWL<1922> B_IWL<1921> B_IWL<1920> B_IWL<2175> B_IWL<2174> B_IWL<2173> B_IWL<2172> B_IWL<2171> B_IWL<2170> B_IWL<2169> B_IWL<2168> B_IWL<2167> B_IWL<2166> B_IWL<2165> B_IWL<2164> B_IWL<2163> B_IWL<2162> B_IWL<2161> B_IWL<2160> B_IWL<2159> B_IWL<2158> B_IWL<2157> B_IWL<2156> B_IWL<2155> B_IWL<2154> B_IWL<2153> B_IWL<2152> B_IWL<2151> B_IWL<2150> B_IWL<2149> B_IWL<2148> B_IWL<2147> B_IWL<2146> B_IWL<2145> B_IWL<2144> B_IWL<2143> B_IWL<2142> B_IWL<2141> B_IWL<2140> B_IWL<2139> B_IWL<2138> B_IWL<2137> B_IWL<2136> B_IWL<2135> B_IWL<2134> B_IWL<2133> B_IWL<2132> B_IWL<2131> B_IWL<2130> B_IWL<2129> B_IWL<2128> B_IWL<2127> B_IWL<2126> B_IWL<2125> B_IWL<2124> B_IWL<2123> B_IWL<2122> B_IWL<2121> B_IWL<2120> B_IWL<2119> B_IWL<2118> B_IWL<2117> B_IWL<2116> B_IWL<2115> B_IWL<2114> B_IWL<2113> B_IWL<2112> B_IWL<2111> B_IWL<2110> B_IWL<2109> B_IWL<2108> B_IWL<2107> B_IWL<2106> B_IWL<2105> B_IWL<2104> B_IWL<2103> B_IWL<2102> B_IWL<2101> B_IWL<2100> B_IWL<2099> B_IWL<2098> B_IWL<2097> B_IWL<2096> B_IWL<2095> B_IWL<2094> B_IWL<2093> B_IWL<2092> B_IWL<2091> B_IWL<2090> B_IWL<2089> B_IWL<2088> B_IWL<2087> B_IWL<2086> B_IWL<2085> B_IWL<2084> B_IWL<2083> B_IWL<2082> B_IWL<2081> B_IWL<2080> B_IWL<2079> B_IWL<2078> B_IWL<2077> B_IWL<2076> B_IWL<2075> B_IWL<2074> B_IWL<2073> B_IWL<2072> B_IWL<2071> B_IWL<2070> B_IWL<2069> B_IWL<2068> B_IWL<2067> B_IWL<2066> B_IWL<2065> B_IWL<2064> B_IWL<2063> B_IWL<2062> B_IWL<2061> B_IWL<2060> B_IWL<2059> B_IWL<2058> B_IWL<2057> B_IWL<2056> B_IWL<2055> B_IWL<2054> B_IWL<2053> B_IWL<2052> B_IWL<2051> B_IWL<2050> B_IWL<2049> B_IWL<2048> VDD_CORE VSS / RM_IHPSG13_512x32_c2_2P_COLUMN_pcell_0 +XCOL<15> A_BLC<31> A_BLC<30> A_BLC_TOP<31> A_BLC_TOP<30> A_BLT<31> A_BLT<30> A_BLT_TOP<31> A_BLT_TOP<30> A_IWL<1919> A_IWL<1918> A_IWL<1917> A_IWL<1916> A_IWL<1915> A_IWL<1914> A_IWL<1913> A_IWL<1912> A_IWL<1911> A_IWL<1910> A_IWL<1909> A_IWL<1908> A_IWL<1907> A_IWL<1906> A_IWL<1905> A_IWL<1904> A_IWL<1903> A_IWL<1902> A_IWL<1901> A_IWL<1900> A_IWL<1899> A_IWL<1898> A_IWL<1897> A_IWL<1896> A_IWL<1895> A_IWL<1894> A_IWL<1893> A_IWL<1892> A_IWL<1891> A_IWL<1890> A_IWL<1889> A_IWL<1888> A_IWL<1887> A_IWL<1886> A_IWL<1885> A_IWL<1884> A_IWL<1883> A_IWL<1882> A_IWL<1881> A_IWL<1880> A_IWL<1879> A_IWL<1878> A_IWL<1877> A_IWL<1876> A_IWL<1875> A_IWL<1874> A_IWL<1873> A_IWL<1872> A_IWL<1871> A_IWL<1870> A_IWL<1869> A_IWL<1868> A_IWL<1867> A_IWL<1866> A_IWL<1865> A_IWL<1864> A_IWL<1863> A_IWL<1862> A_IWL<1861> A_IWL<1860> A_IWL<1859> A_IWL<1858> A_IWL<1857> A_IWL<1856> A_IWL<1855> A_IWL<1854> A_IWL<1853> A_IWL<1852> A_IWL<1851> A_IWL<1850> A_IWL<1849> A_IWL<1848> A_IWL<1847> A_IWL<1846> A_IWL<1845> A_IWL<1844> A_IWL<1843> A_IWL<1842> A_IWL<1841> A_IWL<1840> A_IWL<1839> A_IWL<1838> A_IWL<1837> A_IWL<1836> A_IWL<1835> A_IWL<1834> A_IWL<1833> A_IWL<1832> A_IWL<1831> A_IWL<1830> A_IWL<1829> A_IWL<1828> A_IWL<1827> A_IWL<1826> A_IWL<1825> A_IWL<1824> A_IWL<1823> A_IWL<1822> A_IWL<1821> A_IWL<1820> A_IWL<1819> A_IWL<1818> A_IWL<1817> A_IWL<1816> A_IWL<1815> A_IWL<1814> A_IWL<1813> A_IWL<1812> A_IWL<1811> A_IWL<1810> A_IWL<1809> A_IWL<1808> A_IWL<1807> A_IWL<1806> A_IWL<1805> A_IWL<1804> A_IWL<1803> A_IWL<1802> A_IWL<1801> A_IWL<1800> A_IWL<1799> A_IWL<1798> A_IWL<1797> A_IWL<1796> A_IWL<1795> A_IWL<1794> A_IWL<1793> A_IWL<1792> A_IWL<2047> A_IWL<2046> A_IWL<2045> A_IWL<2044> A_IWL<2043> A_IWL<2042> A_IWL<2041> A_IWL<2040> A_IWL<2039> A_IWL<2038> A_IWL<2037> A_IWL<2036> A_IWL<2035> A_IWL<2034> A_IWL<2033> A_IWL<2032> A_IWL<2031> A_IWL<2030> A_IWL<2029> A_IWL<2028> A_IWL<2027> A_IWL<2026> A_IWL<2025> A_IWL<2024> A_IWL<2023> A_IWL<2022> A_IWL<2021> A_IWL<2020> A_IWL<2019> A_IWL<2018> A_IWL<2017> A_IWL<2016> A_IWL<2015> A_IWL<2014> A_IWL<2013> A_IWL<2012> A_IWL<2011> A_IWL<2010> A_IWL<2009> A_IWL<2008> A_IWL<2007> A_IWL<2006> A_IWL<2005> A_IWL<2004> A_IWL<2003> A_IWL<2002> A_IWL<2001> A_IWL<2000> A_IWL<1999> A_IWL<1998> A_IWL<1997> A_IWL<1996> A_IWL<1995> A_IWL<1994> A_IWL<1993> A_IWL<1992> A_IWL<1991> A_IWL<1990> A_IWL<1989> A_IWL<1988> A_IWL<1987> A_IWL<1986> A_IWL<1985> A_IWL<1984> A_IWL<1983> A_IWL<1982> A_IWL<1981> A_IWL<1980> A_IWL<1979> A_IWL<1978> A_IWL<1977> A_IWL<1976> A_IWL<1975> A_IWL<1974> A_IWL<1973> A_IWL<1972> A_IWL<1971> A_IWL<1970> A_IWL<1969> A_IWL<1968> A_IWL<1967> A_IWL<1966> A_IWL<1965> A_IWL<1964> A_IWL<1963> A_IWL<1962> A_IWL<1961> A_IWL<1960> A_IWL<1959> A_IWL<1958> A_IWL<1957> A_IWL<1956> A_IWL<1955> A_IWL<1954> A_IWL<1953> A_IWL<1952> A_IWL<1951> A_IWL<1950> A_IWL<1949> A_IWL<1948> A_IWL<1947> A_IWL<1946> A_IWL<1945> A_IWL<1944> A_IWL<1943> A_IWL<1942> A_IWL<1941> A_IWL<1940> A_IWL<1939> A_IWL<1938> A_IWL<1937> A_IWL<1936> A_IWL<1935> A_IWL<1934> A_IWL<1933> A_IWL<1932> A_IWL<1931> A_IWL<1930> A_IWL<1929> A_IWL<1928> A_IWL<1927> A_IWL<1926> A_IWL<1925> A_IWL<1924> A_IWL<1923> A_IWL<1922> A_IWL<1921> A_IWL<1920> B_BLC<31> B_BLC<30> B_BLC_TOP<31> B_BLC_TOP<30> B_BLT<31> B_BLT<30> B_BLT_TOP<31> B_BLT_TOP<30> B_IWL<1919> B_IWL<1918> B_IWL<1917> B_IWL<1916> B_IWL<1915> B_IWL<1914> B_IWL<1913> B_IWL<1912> B_IWL<1911> B_IWL<1910> B_IWL<1909> B_IWL<1908> B_IWL<1907> B_IWL<1906> B_IWL<1905> B_IWL<1904> B_IWL<1903> B_IWL<1902> B_IWL<1901> B_IWL<1900> B_IWL<1899> B_IWL<1898> B_IWL<1897> B_IWL<1896> B_IWL<1895> B_IWL<1894> B_IWL<1893> B_IWL<1892> B_IWL<1891> B_IWL<1890> B_IWL<1889> B_IWL<1888> B_IWL<1887> B_IWL<1886> B_IWL<1885> B_IWL<1884> B_IWL<1883> B_IWL<1882> B_IWL<1881> B_IWL<1880> B_IWL<1879> B_IWL<1878> B_IWL<1877> B_IWL<1876> B_IWL<1875> B_IWL<1874> B_IWL<1873> B_IWL<1872> B_IWL<1871> B_IWL<1870> B_IWL<1869> B_IWL<1868> B_IWL<1867> B_IWL<1866> B_IWL<1865> B_IWL<1864> B_IWL<1863> B_IWL<1862> B_IWL<1861> B_IWL<1860> B_IWL<1859> B_IWL<1858> B_IWL<1857> B_IWL<1856> B_IWL<1855> B_IWL<1854> B_IWL<1853> B_IWL<1852> B_IWL<1851> B_IWL<1850> B_IWL<1849> B_IWL<1848> B_IWL<1847> B_IWL<1846> B_IWL<1845> B_IWL<1844> B_IWL<1843> B_IWL<1842> B_IWL<1841> B_IWL<1840> B_IWL<1839> B_IWL<1838> B_IWL<1837> B_IWL<1836> B_IWL<1835> B_IWL<1834> B_IWL<1833> B_IWL<1832> B_IWL<1831> B_IWL<1830> B_IWL<1829> B_IWL<1828> B_IWL<1827> B_IWL<1826> B_IWL<1825> B_IWL<1824> B_IWL<1823> B_IWL<1822> B_IWL<1821> B_IWL<1820> B_IWL<1819> B_IWL<1818> B_IWL<1817> B_IWL<1816> B_IWL<1815> B_IWL<1814> B_IWL<1813> B_IWL<1812> B_IWL<1811> B_IWL<1810> B_IWL<1809> B_IWL<1808> B_IWL<1807> B_IWL<1806> B_IWL<1805> B_IWL<1804> B_IWL<1803> B_IWL<1802> B_IWL<1801> B_IWL<1800> B_IWL<1799> B_IWL<1798> B_IWL<1797> B_IWL<1796> B_IWL<1795> B_IWL<1794> B_IWL<1793> B_IWL<1792> B_IWL<2047> B_IWL<2046> B_IWL<2045> B_IWL<2044> B_IWL<2043> B_IWL<2042> B_IWL<2041> B_IWL<2040> B_IWL<2039> B_IWL<2038> B_IWL<2037> B_IWL<2036> B_IWL<2035> B_IWL<2034> B_IWL<2033> B_IWL<2032> B_IWL<2031> B_IWL<2030> B_IWL<2029> B_IWL<2028> B_IWL<2027> B_IWL<2026> B_IWL<2025> B_IWL<2024> B_IWL<2023> B_IWL<2022> B_IWL<2021> B_IWL<2020> B_IWL<2019> B_IWL<2018> B_IWL<2017> B_IWL<2016> B_IWL<2015> B_IWL<2014> B_IWL<2013> B_IWL<2012> B_IWL<2011> B_IWL<2010> B_IWL<2009> B_IWL<2008> B_IWL<2007> B_IWL<2006> B_IWL<2005> B_IWL<2004> B_IWL<2003> B_IWL<2002> B_IWL<2001> B_IWL<2000> B_IWL<1999> B_IWL<1998> B_IWL<1997> B_IWL<1996> B_IWL<1995> B_IWL<1994> B_IWL<1993> B_IWL<1992> B_IWL<1991> B_IWL<1990> B_IWL<1989> B_IWL<1988> B_IWL<1987> B_IWL<1986> B_IWL<1985> B_IWL<1984> B_IWL<1983> B_IWL<1982> B_IWL<1981> B_IWL<1980> B_IWL<1979> B_IWL<1978> B_IWL<1977> B_IWL<1976> B_IWL<1975> B_IWL<1974> B_IWL<1973> B_IWL<1972> B_IWL<1971> B_IWL<1970> B_IWL<1969> B_IWL<1968> B_IWL<1967> B_IWL<1966> B_IWL<1965> B_IWL<1964> B_IWL<1963> B_IWL<1962> B_IWL<1961> B_IWL<1960> B_IWL<1959> B_IWL<1958> B_IWL<1957> B_IWL<1956> B_IWL<1955> B_IWL<1954> B_IWL<1953> B_IWL<1952> B_IWL<1951> B_IWL<1950> B_IWL<1949> B_IWL<1948> B_IWL<1947> B_IWL<1946> B_IWL<1945> B_IWL<1944> B_IWL<1943> B_IWL<1942> B_IWL<1941> B_IWL<1940> B_IWL<1939> B_IWL<1938> B_IWL<1937> B_IWL<1936> B_IWL<1935> B_IWL<1934> B_IWL<1933> B_IWL<1932> B_IWL<1931> B_IWL<1930> B_IWL<1929> B_IWL<1928> B_IWL<1927> B_IWL<1926> B_IWL<1925> B_IWL<1924> B_IWL<1923> B_IWL<1922> B_IWL<1921> B_IWL<1920> VDD_CORE VSS / RM_IHPSG13_512x32_c2_2P_COLUMN_pcell_0 +XCOL<14> A_BLC<29> A_BLC<28> A_BLC_TOP<29> A_BLC_TOP<28> A_BLT<29> A_BLT<28> A_BLT_TOP<29> A_BLT_TOP<28> A_IWL<1791> A_IWL<1790> A_IWL<1789> A_IWL<1788> A_IWL<1787> A_IWL<1786> A_IWL<1785> A_IWL<1784> A_IWL<1783> A_IWL<1782> A_IWL<1781> A_IWL<1780> A_IWL<1779> A_IWL<1778> A_IWL<1777> A_IWL<1776> A_IWL<1775> A_IWL<1774> A_IWL<1773> A_IWL<1772> A_IWL<1771> A_IWL<1770> A_IWL<1769> A_IWL<1768> A_IWL<1767> A_IWL<1766> A_IWL<1765> A_IWL<1764> A_IWL<1763> A_IWL<1762> A_IWL<1761> A_IWL<1760> A_IWL<1759> A_IWL<1758> A_IWL<1757> A_IWL<1756> A_IWL<1755> A_IWL<1754> A_IWL<1753> A_IWL<1752> A_IWL<1751> A_IWL<1750> A_IWL<1749> A_IWL<1748> A_IWL<1747> A_IWL<1746> A_IWL<1745> A_IWL<1744> A_IWL<1743> A_IWL<1742> A_IWL<1741> A_IWL<1740> A_IWL<1739> A_IWL<1738> A_IWL<1737> A_IWL<1736> A_IWL<1735> A_IWL<1734> A_IWL<1733> A_IWL<1732> A_IWL<1731> A_IWL<1730> A_IWL<1729> A_IWL<1728> A_IWL<1727> A_IWL<1726> A_IWL<1725> A_IWL<1724> A_IWL<1723> A_IWL<1722> A_IWL<1721> A_IWL<1720> A_IWL<1719> A_IWL<1718> A_IWL<1717> A_IWL<1716> A_IWL<1715> A_IWL<1714> A_IWL<1713> A_IWL<1712> A_IWL<1711> A_IWL<1710> A_IWL<1709> A_IWL<1708> A_IWL<1707> A_IWL<1706> A_IWL<1705> A_IWL<1704> A_IWL<1703> A_IWL<1702> A_IWL<1701> A_IWL<1700> A_IWL<1699> A_IWL<1698> A_IWL<1697> A_IWL<1696> A_IWL<1695> A_IWL<1694> A_IWL<1693> A_IWL<1692> A_IWL<1691> A_IWL<1690> A_IWL<1689> A_IWL<1688> A_IWL<1687> A_IWL<1686> A_IWL<1685> A_IWL<1684> A_IWL<1683> A_IWL<1682> A_IWL<1681> A_IWL<1680> A_IWL<1679> A_IWL<1678> A_IWL<1677> A_IWL<1676> A_IWL<1675> A_IWL<1674> A_IWL<1673> A_IWL<1672> A_IWL<1671> A_IWL<1670> A_IWL<1669> A_IWL<1668> A_IWL<1667> A_IWL<1666> A_IWL<1665> A_IWL<1664> A_IWL<1919> A_IWL<1918> A_IWL<1917> A_IWL<1916> A_IWL<1915> A_IWL<1914> A_IWL<1913> A_IWL<1912> A_IWL<1911> A_IWL<1910> A_IWL<1909> A_IWL<1908> A_IWL<1907> A_IWL<1906> A_IWL<1905> A_IWL<1904> A_IWL<1903> A_IWL<1902> A_IWL<1901> A_IWL<1900> A_IWL<1899> A_IWL<1898> A_IWL<1897> A_IWL<1896> A_IWL<1895> A_IWL<1894> A_IWL<1893> A_IWL<1892> A_IWL<1891> A_IWL<1890> A_IWL<1889> A_IWL<1888> A_IWL<1887> A_IWL<1886> A_IWL<1885> A_IWL<1884> A_IWL<1883> A_IWL<1882> A_IWL<1881> A_IWL<1880> A_IWL<1879> A_IWL<1878> A_IWL<1877> A_IWL<1876> A_IWL<1875> A_IWL<1874> A_IWL<1873> A_IWL<1872> A_IWL<1871> A_IWL<1870> A_IWL<1869> A_IWL<1868> A_IWL<1867> A_IWL<1866> A_IWL<1865> A_IWL<1864> A_IWL<1863> A_IWL<1862> A_IWL<1861> A_IWL<1860> A_IWL<1859> A_IWL<1858> A_IWL<1857> A_IWL<1856> A_IWL<1855> A_IWL<1854> A_IWL<1853> A_IWL<1852> A_IWL<1851> A_IWL<1850> A_IWL<1849> A_IWL<1848> A_IWL<1847> A_IWL<1846> A_IWL<1845> A_IWL<1844> A_IWL<1843> A_IWL<1842> A_IWL<1841> A_IWL<1840> A_IWL<1839> A_IWL<1838> A_IWL<1837> A_IWL<1836> A_IWL<1835> A_IWL<1834> A_IWL<1833> A_IWL<1832> A_IWL<1831> A_IWL<1830> A_IWL<1829> A_IWL<1828> A_IWL<1827> A_IWL<1826> A_IWL<1825> A_IWL<1824> A_IWL<1823> A_IWL<1822> A_IWL<1821> A_IWL<1820> A_IWL<1819> A_IWL<1818> A_IWL<1817> A_IWL<1816> A_IWL<1815> A_IWL<1814> A_IWL<1813> A_IWL<1812> A_IWL<1811> A_IWL<1810> A_IWL<1809> A_IWL<1808> A_IWL<1807> A_IWL<1806> A_IWL<1805> A_IWL<1804> A_IWL<1803> A_IWL<1802> A_IWL<1801> A_IWL<1800> A_IWL<1799> A_IWL<1798> A_IWL<1797> A_IWL<1796> A_IWL<1795> A_IWL<1794> A_IWL<1793> A_IWL<1792> B_BLC<29> B_BLC<28> B_BLC_TOP<29> B_BLC_TOP<28> B_BLT<29> B_BLT<28> B_BLT_TOP<29> B_BLT_TOP<28> B_IWL<1791> B_IWL<1790> B_IWL<1789> B_IWL<1788> B_IWL<1787> B_IWL<1786> B_IWL<1785> B_IWL<1784> B_IWL<1783> B_IWL<1782> B_IWL<1781> B_IWL<1780> B_IWL<1779> B_IWL<1778> B_IWL<1777> B_IWL<1776> B_IWL<1775> B_IWL<1774> B_IWL<1773> B_IWL<1772> B_IWL<1771> B_IWL<1770> B_IWL<1769> B_IWL<1768> B_IWL<1767> B_IWL<1766> B_IWL<1765> B_IWL<1764> B_IWL<1763> B_IWL<1762> B_IWL<1761> B_IWL<1760> B_IWL<1759> B_IWL<1758> B_IWL<1757> B_IWL<1756> B_IWL<1755> B_IWL<1754> B_IWL<1753> B_IWL<1752> B_IWL<1751> B_IWL<1750> B_IWL<1749> B_IWL<1748> B_IWL<1747> B_IWL<1746> B_IWL<1745> B_IWL<1744> B_IWL<1743> B_IWL<1742> B_IWL<1741> B_IWL<1740> B_IWL<1739> B_IWL<1738> B_IWL<1737> B_IWL<1736> B_IWL<1735> B_IWL<1734> B_IWL<1733> B_IWL<1732> B_IWL<1731> B_IWL<1730> B_IWL<1729> B_IWL<1728> B_IWL<1727> B_IWL<1726> B_IWL<1725> B_IWL<1724> B_IWL<1723> B_IWL<1722> B_IWL<1721> B_IWL<1720> B_IWL<1719> B_IWL<1718> B_IWL<1717> B_IWL<1716> B_IWL<1715> B_IWL<1714> B_IWL<1713> B_IWL<1712> B_IWL<1711> B_IWL<1710> B_IWL<1709> B_IWL<1708> B_IWL<1707> B_IWL<1706> B_IWL<1705> B_IWL<1704> B_IWL<1703> B_IWL<1702> B_IWL<1701> B_IWL<1700> B_IWL<1699> B_IWL<1698> B_IWL<1697> B_IWL<1696> B_IWL<1695> B_IWL<1694> B_IWL<1693> B_IWL<1692> B_IWL<1691> B_IWL<1690> B_IWL<1689> B_IWL<1688> B_IWL<1687> B_IWL<1686> B_IWL<1685> B_IWL<1684> B_IWL<1683> B_IWL<1682> B_IWL<1681> B_IWL<1680> B_IWL<1679> B_IWL<1678> B_IWL<1677> B_IWL<1676> B_IWL<1675> B_IWL<1674> B_IWL<1673> B_IWL<1672> B_IWL<1671> B_IWL<1670> B_IWL<1669> B_IWL<1668> B_IWL<1667> B_IWL<1666> B_IWL<1665> B_IWL<1664> B_IWL<1919> B_IWL<1918> B_IWL<1917> B_IWL<1916> B_IWL<1915> B_IWL<1914> B_IWL<1913> B_IWL<1912> B_IWL<1911> B_IWL<1910> B_IWL<1909> B_IWL<1908> B_IWL<1907> B_IWL<1906> B_IWL<1905> B_IWL<1904> B_IWL<1903> B_IWL<1902> B_IWL<1901> B_IWL<1900> B_IWL<1899> B_IWL<1898> B_IWL<1897> B_IWL<1896> B_IWL<1895> B_IWL<1894> B_IWL<1893> B_IWL<1892> B_IWL<1891> B_IWL<1890> B_IWL<1889> B_IWL<1888> B_IWL<1887> B_IWL<1886> B_IWL<1885> B_IWL<1884> B_IWL<1883> B_IWL<1882> B_IWL<1881> B_IWL<1880> B_IWL<1879> B_IWL<1878> B_IWL<1877> B_IWL<1876> B_IWL<1875> B_IWL<1874> B_IWL<1873> B_IWL<1872> B_IWL<1871> B_IWL<1870> B_IWL<1869> B_IWL<1868> B_IWL<1867> B_IWL<1866> B_IWL<1865> B_IWL<1864> B_IWL<1863> B_IWL<1862> B_IWL<1861> B_IWL<1860> B_IWL<1859> B_IWL<1858> B_IWL<1857> B_IWL<1856> B_IWL<1855> B_IWL<1854> B_IWL<1853> B_IWL<1852> B_IWL<1851> B_IWL<1850> B_IWL<1849> B_IWL<1848> B_IWL<1847> B_IWL<1846> B_IWL<1845> B_IWL<1844> B_IWL<1843> B_IWL<1842> B_IWL<1841> B_IWL<1840> B_IWL<1839> B_IWL<1838> B_IWL<1837> B_IWL<1836> B_IWL<1835> B_IWL<1834> B_IWL<1833> B_IWL<1832> B_IWL<1831> B_IWL<1830> B_IWL<1829> B_IWL<1828> B_IWL<1827> B_IWL<1826> B_IWL<1825> B_IWL<1824> B_IWL<1823> B_IWL<1822> B_IWL<1821> B_IWL<1820> B_IWL<1819> B_IWL<1818> B_IWL<1817> B_IWL<1816> B_IWL<1815> B_IWL<1814> B_IWL<1813> B_IWL<1812> B_IWL<1811> B_IWL<1810> B_IWL<1809> B_IWL<1808> B_IWL<1807> B_IWL<1806> B_IWL<1805> B_IWL<1804> B_IWL<1803> B_IWL<1802> B_IWL<1801> B_IWL<1800> B_IWL<1799> B_IWL<1798> B_IWL<1797> B_IWL<1796> B_IWL<1795> B_IWL<1794> B_IWL<1793> B_IWL<1792> VDD_CORE VSS / RM_IHPSG13_512x32_c2_2P_COLUMN_pcell_0 +XCOL<13> A_BLC<27> A_BLC<26> A_BLC_TOP<27> A_BLC_TOP<26> A_BLT<27> A_BLT<26> A_BLT_TOP<27> A_BLT_TOP<26> A_IWL<1663> A_IWL<1662> A_IWL<1661> A_IWL<1660> A_IWL<1659> A_IWL<1658> A_IWL<1657> A_IWL<1656> A_IWL<1655> A_IWL<1654> A_IWL<1653> A_IWL<1652> A_IWL<1651> A_IWL<1650> A_IWL<1649> A_IWL<1648> A_IWL<1647> A_IWL<1646> A_IWL<1645> A_IWL<1644> A_IWL<1643> A_IWL<1642> A_IWL<1641> A_IWL<1640> A_IWL<1639> A_IWL<1638> A_IWL<1637> A_IWL<1636> A_IWL<1635> A_IWL<1634> A_IWL<1633> A_IWL<1632> A_IWL<1631> A_IWL<1630> A_IWL<1629> A_IWL<1628> A_IWL<1627> A_IWL<1626> A_IWL<1625> A_IWL<1624> A_IWL<1623> A_IWL<1622> A_IWL<1621> A_IWL<1620> A_IWL<1619> A_IWL<1618> A_IWL<1617> A_IWL<1616> A_IWL<1615> A_IWL<1614> A_IWL<1613> A_IWL<1612> A_IWL<1611> A_IWL<1610> A_IWL<1609> A_IWL<1608> A_IWL<1607> A_IWL<1606> A_IWL<1605> A_IWL<1604> A_IWL<1603> A_IWL<1602> A_IWL<1601> A_IWL<1600> A_IWL<1599> A_IWL<1598> A_IWL<1597> A_IWL<1596> A_IWL<1595> A_IWL<1594> A_IWL<1593> A_IWL<1592> A_IWL<1591> A_IWL<1590> A_IWL<1589> A_IWL<1588> A_IWL<1587> A_IWL<1586> A_IWL<1585> A_IWL<1584> A_IWL<1583> A_IWL<1582> A_IWL<1581> A_IWL<1580> A_IWL<1579> A_IWL<1578> A_IWL<1577> A_IWL<1576> A_IWL<1575> A_IWL<1574> A_IWL<1573> A_IWL<1572> A_IWL<1571> A_IWL<1570> A_IWL<1569> A_IWL<1568> A_IWL<1567> A_IWL<1566> A_IWL<1565> A_IWL<1564> A_IWL<1563> A_IWL<1562> A_IWL<1561> A_IWL<1560> A_IWL<1559> A_IWL<1558> A_IWL<1557> A_IWL<1556> A_IWL<1555> A_IWL<1554> A_IWL<1553> A_IWL<1552> A_IWL<1551> A_IWL<1550> A_IWL<1549> A_IWL<1548> A_IWL<1547> A_IWL<1546> A_IWL<1545> A_IWL<1544> A_IWL<1543> A_IWL<1542> A_IWL<1541> A_IWL<1540> A_IWL<1539> A_IWL<1538> A_IWL<1537> A_IWL<1536> A_IWL<1791> A_IWL<1790> A_IWL<1789> A_IWL<1788> A_IWL<1787> A_IWL<1786> A_IWL<1785> A_IWL<1784> A_IWL<1783> A_IWL<1782> A_IWL<1781> A_IWL<1780> A_IWL<1779> A_IWL<1778> A_IWL<1777> A_IWL<1776> A_IWL<1775> A_IWL<1774> A_IWL<1773> A_IWL<1772> A_IWL<1771> A_IWL<1770> A_IWL<1769> A_IWL<1768> A_IWL<1767> A_IWL<1766> A_IWL<1765> A_IWL<1764> A_IWL<1763> A_IWL<1762> A_IWL<1761> A_IWL<1760> A_IWL<1759> A_IWL<1758> A_IWL<1757> A_IWL<1756> A_IWL<1755> A_IWL<1754> A_IWL<1753> A_IWL<1752> A_IWL<1751> A_IWL<1750> A_IWL<1749> A_IWL<1748> A_IWL<1747> A_IWL<1746> A_IWL<1745> A_IWL<1744> A_IWL<1743> A_IWL<1742> A_IWL<1741> A_IWL<1740> A_IWL<1739> A_IWL<1738> A_IWL<1737> A_IWL<1736> A_IWL<1735> A_IWL<1734> A_IWL<1733> A_IWL<1732> A_IWL<1731> A_IWL<1730> A_IWL<1729> A_IWL<1728> A_IWL<1727> A_IWL<1726> A_IWL<1725> A_IWL<1724> A_IWL<1723> A_IWL<1722> A_IWL<1721> A_IWL<1720> A_IWL<1719> A_IWL<1718> A_IWL<1717> A_IWL<1716> A_IWL<1715> A_IWL<1714> A_IWL<1713> A_IWL<1712> A_IWL<1711> A_IWL<1710> A_IWL<1709> A_IWL<1708> A_IWL<1707> A_IWL<1706> A_IWL<1705> A_IWL<1704> A_IWL<1703> A_IWL<1702> A_IWL<1701> A_IWL<1700> A_IWL<1699> A_IWL<1698> A_IWL<1697> A_IWL<1696> A_IWL<1695> A_IWL<1694> A_IWL<1693> A_IWL<1692> A_IWL<1691> A_IWL<1690> A_IWL<1689> A_IWL<1688> A_IWL<1687> A_IWL<1686> A_IWL<1685> A_IWL<1684> A_IWL<1683> A_IWL<1682> A_IWL<1681> A_IWL<1680> A_IWL<1679> A_IWL<1678> A_IWL<1677> A_IWL<1676> A_IWL<1675> A_IWL<1674> A_IWL<1673> A_IWL<1672> A_IWL<1671> A_IWL<1670> A_IWL<1669> A_IWL<1668> A_IWL<1667> A_IWL<1666> A_IWL<1665> A_IWL<1664> B_BLC<27> B_BLC<26> B_BLC_TOP<27> B_BLC_TOP<26> B_BLT<27> B_BLT<26> B_BLT_TOP<27> B_BLT_TOP<26> B_IWL<1663> B_IWL<1662> B_IWL<1661> B_IWL<1660> B_IWL<1659> B_IWL<1658> B_IWL<1657> B_IWL<1656> B_IWL<1655> B_IWL<1654> B_IWL<1653> B_IWL<1652> B_IWL<1651> B_IWL<1650> B_IWL<1649> B_IWL<1648> B_IWL<1647> B_IWL<1646> B_IWL<1645> B_IWL<1644> B_IWL<1643> B_IWL<1642> B_IWL<1641> B_IWL<1640> B_IWL<1639> B_IWL<1638> B_IWL<1637> B_IWL<1636> B_IWL<1635> B_IWL<1634> B_IWL<1633> B_IWL<1632> B_IWL<1631> B_IWL<1630> B_IWL<1629> B_IWL<1628> B_IWL<1627> B_IWL<1626> B_IWL<1625> B_IWL<1624> B_IWL<1623> B_IWL<1622> B_IWL<1621> B_IWL<1620> B_IWL<1619> B_IWL<1618> B_IWL<1617> B_IWL<1616> B_IWL<1615> B_IWL<1614> B_IWL<1613> B_IWL<1612> B_IWL<1611> B_IWL<1610> B_IWL<1609> B_IWL<1608> B_IWL<1607> B_IWL<1606> B_IWL<1605> B_IWL<1604> B_IWL<1603> B_IWL<1602> B_IWL<1601> B_IWL<1600> B_IWL<1599> B_IWL<1598> B_IWL<1597> B_IWL<1596> B_IWL<1595> B_IWL<1594> B_IWL<1593> B_IWL<1592> B_IWL<1591> B_IWL<1590> B_IWL<1589> B_IWL<1588> B_IWL<1587> B_IWL<1586> B_IWL<1585> B_IWL<1584> B_IWL<1583> B_IWL<1582> B_IWL<1581> B_IWL<1580> B_IWL<1579> B_IWL<1578> B_IWL<1577> B_IWL<1576> B_IWL<1575> B_IWL<1574> B_IWL<1573> B_IWL<1572> B_IWL<1571> B_IWL<1570> B_IWL<1569> B_IWL<1568> B_IWL<1567> B_IWL<1566> B_IWL<1565> B_IWL<1564> B_IWL<1563> B_IWL<1562> B_IWL<1561> B_IWL<1560> B_IWL<1559> B_IWL<1558> B_IWL<1557> B_IWL<1556> B_IWL<1555> B_IWL<1554> B_IWL<1553> B_IWL<1552> B_IWL<1551> B_IWL<1550> B_IWL<1549> B_IWL<1548> B_IWL<1547> B_IWL<1546> B_IWL<1545> B_IWL<1544> B_IWL<1543> B_IWL<1542> B_IWL<1541> B_IWL<1540> B_IWL<1539> B_IWL<1538> B_IWL<1537> B_IWL<1536> B_IWL<1791> B_IWL<1790> B_IWL<1789> B_IWL<1788> B_IWL<1787> B_IWL<1786> B_IWL<1785> B_IWL<1784> B_IWL<1783> B_IWL<1782> B_IWL<1781> B_IWL<1780> B_IWL<1779> B_IWL<1778> B_IWL<1777> B_IWL<1776> B_IWL<1775> B_IWL<1774> B_IWL<1773> B_IWL<1772> B_IWL<1771> B_IWL<1770> B_IWL<1769> B_IWL<1768> B_IWL<1767> B_IWL<1766> B_IWL<1765> B_IWL<1764> B_IWL<1763> B_IWL<1762> B_IWL<1761> B_IWL<1760> B_IWL<1759> B_IWL<1758> B_IWL<1757> B_IWL<1756> B_IWL<1755> B_IWL<1754> B_IWL<1753> B_IWL<1752> B_IWL<1751> B_IWL<1750> B_IWL<1749> B_IWL<1748> B_IWL<1747> B_IWL<1746> B_IWL<1745> B_IWL<1744> B_IWL<1743> B_IWL<1742> B_IWL<1741> B_IWL<1740> B_IWL<1739> B_IWL<1738> B_IWL<1737> B_IWL<1736> B_IWL<1735> B_IWL<1734> B_IWL<1733> B_IWL<1732> B_IWL<1731> B_IWL<1730> B_IWL<1729> B_IWL<1728> B_IWL<1727> B_IWL<1726> B_IWL<1725> B_IWL<1724> B_IWL<1723> B_IWL<1722> B_IWL<1721> B_IWL<1720> B_IWL<1719> B_IWL<1718> B_IWL<1717> B_IWL<1716> B_IWL<1715> B_IWL<1714> B_IWL<1713> B_IWL<1712> B_IWL<1711> B_IWL<1710> B_IWL<1709> B_IWL<1708> B_IWL<1707> B_IWL<1706> B_IWL<1705> B_IWL<1704> B_IWL<1703> B_IWL<1702> B_IWL<1701> B_IWL<1700> B_IWL<1699> B_IWL<1698> B_IWL<1697> B_IWL<1696> B_IWL<1695> B_IWL<1694> B_IWL<1693> B_IWL<1692> B_IWL<1691> B_IWL<1690> B_IWL<1689> B_IWL<1688> B_IWL<1687> B_IWL<1686> B_IWL<1685> B_IWL<1684> B_IWL<1683> B_IWL<1682> B_IWL<1681> B_IWL<1680> B_IWL<1679> B_IWL<1678> B_IWL<1677> B_IWL<1676> B_IWL<1675> B_IWL<1674> B_IWL<1673> B_IWL<1672> B_IWL<1671> B_IWL<1670> B_IWL<1669> B_IWL<1668> B_IWL<1667> B_IWL<1666> B_IWL<1665> B_IWL<1664> VDD_CORE VSS / RM_IHPSG13_512x32_c2_2P_COLUMN_pcell_0 +XCOL<12> A_BLC<25> A_BLC<24> A_BLC_TOP<25> A_BLC_TOP<24> A_BLT<25> A_BLT<24> A_BLT_TOP<25> A_BLT_TOP<24> A_IWL<1535> A_IWL<1534> A_IWL<1533> A_IWL<1532> A_IWL<1531> A_IWL<1530> A_IWL<1529> A_IWL<1528> A_IWL<1527> A_IWL<1526> A_IWL<1525> A_IWL<1524> A_IWL<1523> A_IWL<1522> A_IWL<1521> A_IWL<1520> A_IWL<1519> A_IWL<1518> A_IWL<1517> A_IWL<1516> A_IWL<1515> A_IWL<1514> A_IWL<1513> A_IWL<1512> A_IWL<1511> A_IWL<1510> A_IWL<1509> A_IWL<1508> A_IWL<1507> A_IWL<1506> A_IWL<1505> A_IWL<1504> A_IWL<1503> A_IWL<1502> A_IWL<1501> A_IWL<1500> A_IWL<1499> A_IWL<1498> A_IWL<1497> A_IWL<1496> A_IWL<1495> A_IWL<1494> A_IWL<1493> A_IWL<1492> A_IWL<1491> A_IWL<1490> A_IWL<1489> A_IWL<1488> A_IWL<1487> A_IWL<1486> A_IWL<1485> A_IWL<1484> A_IWL<1483> A_IWL<1482> A_IWL<1481> A_IWL<1480> A_IWL<1479> A_IWL<1478> A_IWL<1477> A_IWL<1476> A_IWL<1475> A_IWL<1474> A_IWL<1473> A_IWL<1472> A_IWL<1471> A_IWL<1470> A_IWL<1469> A_IWL<1468> A_IWL<1467> A_IWL<1466> A_IWL<1465> A_IWL<1464> A_IWL<1463> A_IWL<1462> A_IWL<1461> A_IWL<1460> A_IWL<1459> A_IWL<1458> A_IWL<1457> A_IWL<1456> A_IWL<1455> A_IWL<1454> A_IWL<1453> A_IWL<1452> A_IWL<1451> A_IWL<1450> A_IWL<1449> A_IWL<1448> A_IWL<1447> A_IWL<1446> A_IWL<1445> A_IWL<1444> A_IWL<1443> A_IWL<1442> A_IWL<1441> A_IWL<1440> A_IWL<1439> A_IWL<1438> A_IWL<1437> A_IWL<1436> A_IWL<1435> A_IWL<1434> A_IWL<1433> A_IWL<1432> A_IWL<1431> A_IWL<1430> A_IWL<1429> A_IWL<1428> A_IWL<1427> A_IWL<1426> A_IWL<1425> A_IWL<1424> A_IWL<1423> A_IWL<1422> A_IWL<1421> A_IWL<1420> A_IWL<1419> A_IWL<1418> A_IWL<1417> A_IWL<1416> A_IWL<1415> A_IWL<1414> A_IWL<1413> A_IWL<1412> A_IWL<1411> A_IWL<1410> A_IWL<1409> A_IWL<1408> A_IWL<1663> A_IWL<1662> A_IWL<1661> A_IWL<1660> A_IWL<1659> A_IWL<1658> A_IWL<1657> A_IWL<1656> A_IWL<1655> A_IWL<1654> A_IWL<1653> A_IWL<1652> A_IWL<1651> A_IWL<1650> A_IWL<1649> A_IWL<1648> A_IWL<1647> A_IWL<1646> A_IWL<1645> A_IWL<1644> A_IWL<1643> A_IWL<1642> A_IWL<1641> A_IWL<1640> A_IWL<1639> A_IWL<1638> A_IWL<1637> A_IWL<1636> A_IWL<1635> A_IWL<1634> A_IWL<1633> A_IWL<1632> A_IWL<1631> A_IWL<1630> A_IWL<1629> A_IWL<1628> A_IWL<1627> A_IWL<1626> A_IWL<1625> A_IWL<1624> A_IWL<1623> A_IWL<1622> A_IWL<1621> A_IWL<1620> A_IWL<1619> A_IWL<1618> A_IWL<1617> A_IWL<1616> A_IWL<1615> A_IWL<1614> A_IWL<1613> A_IWL<1612> A_IWL<1611> A_IWL<1610> A_IWL<1609> A_IWL<1608> A_IWL<1607> A_IWL<1606> A_IWL<1605> A_IWL<1604> A_IWL<1603> A_IWL<1602> A_IWL<1601> A_IWL<1600> A_IWL<1599> A_IWL<1598> A_IWL<1597> A_IWL<1596> A_IWL<1595> A_IWL<1594> A_IWL<1593> A_IWL<1592> A_IWL<1591> A_IWL<1590> A_IWL<1589> A_IWL<1588> A_IWL<1587> A_IWL<1586> A_IWL<1585> A_IWL<1584> A_IWL<1583> A_IWL<1582> A_IWL<1581> A_IWL<1580> A_IWL<1579> A_IWL<1578> A_IWL<1577> A_IWL<1576> A_IWL<1575> A_IWL<1574> A_IWL<1573> A_IWL<1572> A_IWL<1571> A_IWL<1570> A_IWL<1569> A_IWL<1568> A_IWL<1567> A_IWL<1566> A_IWL<1565> A_IWL<1564> A_IWL<1563> A_IWL<1562> A_IWL<1561> A_IWL<1560> A_IWL<1559> A_IWL<1558> A_IWL<1557> A_IWL<1556> A_IWL<1555> A_IWL<1554> A_IWL<1553> A_IWL<1552> A_IWL<1551> A_IWL<1550> A_IWL<1549> A_IWL<1548> A_IWL<1547> A_IWL<1546> A_IWL<1545> A_IWL<1544> A_IWL<1543> A_IWL<1542> A_IWL<1541> A_IWL<1540> A_IWL<1539> A_IWL<1538> A_IWL<1537> A_IWL<1536> B_BLC<25> B_BLC<24> B_BLC_TOP<25> B_BLC_TOP<24> B_BLT<25> B_BLT<24> B_BLT_TOP<25> B_BLT_TOP<24> B_IWL<1535> B_IWL<1534> B_IWL<1533> B_IWL<1532> B_IWL<1531> B_IWL<1530> B_IWL<1529> B_IWL<1528> B_IWL<1527> B_IWL<1526> B_IWL<1525> B_IWL<1524> B_IWL<1523> B_IWL<1522> B_IWL<1521> B_IWL<1520> B_IWL<1519> B_IWL<1518> B_IWL<1517> B_IWL<1516> B_IWL<1515> B_IWL<1514> B_IWL<1513> B_IWL<1512> B_IWL<1511> B_IWL<1510> B_IWL<1509> B_IWL<1508> B_IWL<1507> B_IWL<1506> B_IWL<1505> B_IWL<1504> B_IWL<1503> B_IWL<1502> B_IWL<1501> B_IWL<1500> B_IWL<1499> B_IWL<1498> B_IWL<1497> B_IWL<1496> B_IWL<1495> B_IWL<1494> B_IWL<1493> B_IWL<1492> B_IWL<1491> B_IWL<1490> B_IWL<1489> B_IWL<1488> B_IWL<1487> B_IWL<1486> B_IWL<1485> B_IWL<1484> B_IWL<1483> B_IWL<1482> B_IWL<1481> B_IWL<1480> B_IWL<1479> B_IWL<1478> B_IWL<1477> B_IWL<1476> B_IWL<1475> B_IWL<1474> B_IWL<1473> B_IWL<1472> B_IWL<1471> B_IWL<1470> B_IWL<1469> B_IWL<1468> B_IWL<1467> B_IWL<1466> B_IWL<1465> B_IWL<1464> B_IWL<1463> B_IWL<1462> B_IWL<1461> B_IWL<1460> B_IWL<1459> B_IWL<1458> B_IWL<1457> B_IWL<1456> B_IWL<1455> B_IWL<1454> B_IWL<1453> B_IWL<1452> B_IWL<1451> B_IWL<1450> B_IWL<1449> B_IWL<1448> B_IWL<1447> B_IWL<1446> B_IWL<1445> B_IWL<1444> B_IWL<1443> B_IWL<1442> B_IWL<1441> B_IWL<1440> B_IWL<1439> B_IWL<1438> B_IWL<1437> B_IWL<1436> B_IWL<1435> B_IWL<1434> B_IWL<1433> B_IWL<1432> B_IWL<1431> B_IWL<1430> B_IWL<1429> B_IWL<1428> B_IWL<1427> B_IWL<1426> B_IWL<1425> B_IWL<1424> B_IWL<1423> B_IWL<1422> B_IWL<1421> B_IWL<1420> B_IWL<1419> B_IWL<1418> B_IWL<1417> B_IWL<1416> B_IWL<1415> B_IWL<1414> B_IWL<1413> B_IWL<1412> B_IWL<1411> B_IWL<1410> B_IWL<1409> B_IWL<1408> B_IWL<1663> B_IWL<1662> B_IWL<1661> B_IWL<1660> B_IWL<1659> B_IWL<1658> B_IWL<1657> B_IWL<1656> B_IWL<1655> B_IWL<1654> B_IWL<1653> B_IWL<1652> B_IWL<1651> B_IWL<1650> B_IWL<1649> B_IWL<1648> B_IWL<1647> B_IWL<1646> B_IWL<1645> B_IWL<1644> B_IWL<1643> B_IWL<1642> B_IWL<1641> B_IWL<1640> B_IWL<1639> B_IWL<1638> B_IWL<1637> B_IWL<1636> B_IWL<1635> B_IWL<1634> B_IWL<1633> B_IWL<1632> B_IWL<1631> B_IWL<1630> B_IWL<1629> B_IWL<1628> B_IWL<1627> B_IWL<1626> B_IWL<1625> B_IWL<1624> B_IWL<1623> B_IWL<1622> B_IWL<1621> B_IWL<1620> B_IWL<1619> B_IWL<1618> B_IWL<1617> B_IWL<1616> B_IWL<1615> B_IWL<1614> B_IWL<1613> B_IWL<1612> B_IWL<1611> B_IWL<1610> B_IWL<1609> B_IWL<1608> B_IWL<1607> B_IWL<1606> B_IWL<1605> B_IWL<1604> B_IWL<1603> B_IWL<1602> B_IWL<1601> B_IWL<1600> B_IWL<1599> B_IWL<1598> B_IWL<1597> B_IWL<1596> B_IWL<1595> B_IWL<1594> B_IWL<1593> B_IWL<1592> B_IWL<1591> B_IWL<1590> B_IWL<1589> B_IWL<1588> B_IWL<1587> B_IWL<1586> B_IWL<1585> B_IWL<1584> B_IWL<1583> B_IWL<1582> B_IWL<1581> B_IWL<1580> B_IWL<1579> B_IWL<1578> B_IWL<1577> B_IWL<1576> B_IWL<1575> B_IWL<1574> B_IWL<1573> B_IWL<1572> B_IWL<1571> B_IWL<1570> B_IWL<1569> B_IWL<1568> B_IWL<1567> B_IWL<1566> B_IWL<1565> B_IWL<1564> B_IWL<1563> B_IWL<1562> B_IWL<1561> B_IWL<1560> B_IWL<1559> B_IWL<1558> B_IWL<1557> B_IWL<1556> B_IWL<1555> B_IWL<1554> B_IWL<1553> B_IWL<1552> B_IWL<1551> B_IWL<1550> B_IWL<1549> B_IWL<1548> B_IWL<1547> B_IWL<1546> B_IWL<1545> B_IWL<1544> B_IWL<1543> B_IWL<1542> B_IWL<1541> B_IWL<1540> B_IWL<1539> B_IWL<1538> B_IWL<1537> B_IWL<1536> VDD_CORE VSS / RM_IHPSG13_512x32_c2_2P_COLUMN_pcell_0 +XCOL<11> A_BLC<23> A_BLC<22> A_BLC_TOP<23> A_BLC_TOP<22> A_BLT<23> A_BLT<22> A_BLT_TOP<23> A_BLT_TOP<22> A_IWL<1407> A_IWL<1406> A_IWL<1405> A_IWL<1404> A_IWL<1403> A_IWL<1402> A_IWL<1401> A_IWL<1400> A_IWL<1399> A_IWL<1398> A_IWL<1397> A_IWL<1396> A_IWL<1395> A_IWL<1394> A_IWL<1393> A_IWL<1392> A_IWL<1391> A_IWL<1390> A_IWL<1389> A_IWL<1388> A_IWL<1387> A_IWL<1386> A_IWL<1385> A_IWL<1384> A_IWL<1383> A_IWL<1382> A_IWL<1381> A_IWL<1380> A_IWL<1379> A_IWL<1378> A_IWL<1377> A_IWL<1376> A_IWL<1375> A_IWL<1374> A_IWL<1373> A_IWL<1372> A_IWL<1371> A_IWL<1370> A_IWL<1369> A_IWL<1368> A_IWL<1367> A_IWL<1366> A_IWL<1365> A_IWL<1364> A_IWL<1363> A_IWL<1362> A_IWL<1361> A_IWL<1360> A_IWL<1359> A_IWL<1358> A_IWL<1357> A_IWL<1356> A_IWL<1355> A_IWL<1354> A_IWL<1353> A_IWL<1352> A_IWL<1351> A_IWL<1350> A_IWL<1349> A_IWL<1348> A_IWL<1347> A_IWL<1346> A_IWL<1345> A_IWL<1344> A_IWL<1343> A_IWL<1342> A_IWL<1341> A_IWL<1340> A_IWL<1339> A_IWL<1338> A_IWL<1337> A_IWL<1336> A_IWL<1335> A_IWL<1334> A_IWL<1333> A_IWL<1332> A_IWL<1331> A_IWL<1330> A_IWL<1329> A_IWL<1328> A_IWL<1327> A_IWL<1326> A_IWL<1325> A_IWL<1324> A_IWL<1323> A_IWL<1322> A_IWL<1321> A_IWL<1320> A_IWL<1319> A_IWL<1318> A_IWL<1317> A_IWL<1316> A_IWL<1315> A_IWL<1314> A_IWL<1313> A_IWL<1312> A_IWL<1311> A_IWL<1310> A_IWL<1309> A_IWL<1308> A_IWL<1307> A_IWL<1306> A_IWL<1305> A_IWL<1304> A_IWL<1303> A_IWL<1302> A_IWL<1301> A_IWL<1300> A_IWL<1299> A_IWL<1298> A_IWL<1297> A_IWL<1296> A_IWL<1295> A_IWL<1294> A_IWL<1293> A_IWL<1292> A_IWL<1291> A_IWL<1290> A_IWL<1289> A_IWL<1288> A_IWL<1287> A_IWL<1286> A_IWL<1285> A_IWL<1284> A_IWL<1283> A_IWL<1282> A_IWL<1281> A_IWL<1280> A_IWL<1535> A_IWL<1534> A_IWL<1533> A_IWL<1532> A_IWL<1531> A_IWL<1530> A_IWL<1529> A_IWL<1528> A_IWL<1527> A_IWL<1526> A_IWL<1525> A_IWL<1524> A_IWL<1523> A_IWL<1522> A_IWL<1521> A_IWL<1520> A_IWL<1519> A_IWL<1518> A_IWL<1517> A_IWL<1516> A_IWL<1515> A_IWL<1514> A_IWL<1513> A_IWL<1512> A_IWL<1511> A_IWL<1510> A_IWL<1509> A_IWL<1508> A_IWL<1507> A_IWL<1506> A_IWL<1505> A_IWL<1504> A_IWL<1503> A_IWL<1502> A_IWL<1501> A_IWL<1500> A_IWL<1499> A_IWL<1498> A_IWL<1497> A_IWL<1496> A_IWL<1495> A_IWL<1494> A_IWL<1493> A_IWL<1492> A_IWL<1491> A_IWL<1490> A_IWL<1489> A_IWL<1488> A_IWL<1487> A_IWL<1486> A_IWL<1485> A_IWL<1484> A_IWL<1483> A_IWL<1482> A_IWL<1481> A_IWL<1480> A_IWL<1479> A_IWL<1478> A_IWL<1477> A_IWL<1476> A_IWL<1475> A_IWL<1474> A_IWL<1473> A_IWL<1472> A_IWL<1471> A_IWL<1470> A_IWL<1469> A_IWL<1468> A_IWL<1467> A_IWL<1466> A_IWL<1465> A_IWL<1464> A_IWL<1463> A_IWL<1462> A_IWL<1461> A_IWL<1460> A_IWL<1459> A_IWL<1458> A_IWL<1457> A_IWL<1456> A_IWL<1455> A_IWL<1454> A_IWL<1453> A_IWL<1452> A_IWL<1451> A_IWL<1450> A_IWL<1449> A_IWL<1448> A_IWL<1447> A_IWL<1446> A_IWL<1445> A_IWL<1444> A_IWL<1443> A_IWL<1442> A_IWL<1441> A_IWL<1440> A_IWL<1439> A_IWL<1438> A_IWL<1437> A_IWL<1436> A_IWL<1435> A_IWL<1434> A_IWL<1433> A_IWL<1432> A_IWL<1431> A_IWL<1430> A_IWL<1429> A_IWL<1428> A_IWL<1427> A_IWL<1426> A_IWL<1425> A_IWL<1424> A_IWL<1423> A_IWL<1422> A_IWL<1421> A_IWL<1420> A_IWL<1419> A_IWL<1418> A_IWL<1417> A_IWL<1416> A_IWL<1415> A_IWL<1414> A_IWL<1413> A_IWL<1412> A_IWL<1411> A_IWL<1410> A_IWL<1409> A_IWL<1408> B_BLC<23> B_BLC<22> B_BLC_TOP<23> B_BLC_TOP<22> B_BLT<23> B_BLT<22> B_BLT_TOP<23> B_BLT_TOP<22> B_IWL<1407> B_IWL<1406> B_IWL<1405> B_IWL<1404> B_IWL<1403> B_IWL<1402> B_IWL<1401> B_IWL<1400> B_IWL<1399> B_IWL<1398> B_IWL<1397> B_IWL<1396> B_IWL<1395> B_IWL<1394> B_IWL<1393> B_IWL<1392> B_IWL<1391> B_IWL<1390> B_IWL<1389> B_IWL<1388> B_IWL<1387> B_IWL<1386> B_IWL<1385> B_IWL<1384> B_IWL<1383> B_IWL<1382> B_IWL<1381> B_IWL<1380> B_IWL<1379> B_IWL<1378> B_IWL<1377> B_IWL<1376> B_IWL<1375> B_IWL<1374> B_IWL<1373> B_IWL<1372> B_IWL<1371> B_IWL<1370> B_IWL<1369> B_IWL<1368> B_IWL<1367> B_IWL<1366> B_IWL<1365> B_IWL<1364> B_IWL<1363> B_IWL<1362> B_IWL<1361> B_IWL<1360> B_IWL<1359> B_IWL<1358> B_IWL<1357> B_IWL<1356> B_IWL<1355> B_IWL<1354> B_IWL<1353> B_IWL<1352> B_IWL<1351> B_IWL<1350> B_IWL<1349> B_IWL<1348> B_IWL<1347> B_IWL<1346> B_IWL<1345> B_IWL<1344> B_IWL<1343> B_IWL<1342> B_IWL<1341> B_IWL<1340> B_IWL<1339> B_IWL<1338> B_IWL<1337> B_IWL<1336> B_IWL<1335> B_IWL<1334> B_IWL<1333> B_IWL<1332> B_IWL<1331> B_IWL<1330> B_IWL<1329> B_IWL<1328> B_IWL<1327> B_IWL<1326> B_IWL<1325> B_IWL<1324> B_IWL<1323> B_IWL<1322> B_IWL<1321> B_IWL<1320> B_IWL<1319> B_IWL<1318> B_IWL<1317> B_IWL<1316> B_IWL<1315> B_IWL<1314> B_IWL<1313> B_IWL<1312> B_IWL<1311> B_IWL<1310> B_IWL<1309> B_IWL<1308> B_IWL<1307> B_IWL<1306> B_IWL<1305> B_IWL<1304> B_IWL<1303> B_IWL<1302> B_IWL<1301> B_IWL<1300> B_IWL<1299> B_IWL<1298> B_IWL<1297> B_IWL<1296> B_IWL<1295> B_IWL<1294> B_IWL<1293> B_IWL<1292> B_IWL<1291> B_IWL<1290> B_IWL<1289> B_IWL<1288> B_IWL<1287> B_IWL<1286> B_IWL<1285> B_IWL<1284> B_IWL<1283> B_IWL<1282> B_IWL<1281> B_IWL<1280> B_IWL<1535> B_IWL<1534> B_IWL<1533> B_IWL<1532> B_IWL<1531> B_IWL<1530> B_IWL<1529> B_IWL<1528> B_IWL<1527> B_IWL<1526> B_IWL<1525> B_IWL<1524> B_IWL<1523> B_IWL<1522> B_IWL<1521> B_IWL<1520> B_IWL<1519> B_IWL<1518> B_IWL<1517> B_IWL<1516> B_IWL<1515> B_IWL<1514> B_IWL<1513> B_IWL<1512> B_IWL<1511> B_IWL<1510> B_IWL<1509> B_IWL<1508> B_IWL<1507> B_IWL<1506> B_IWL<1505> B_IWL<1504> B_IWL<1503> B_IWL<1502> B_IWL<1501> B_IWL<1500> B_IWL<1499> B_IWL<1498> B_IWL<1497> B_IWL<1496> B_IWL<1495> B_IWL<1494> B_IWL<1493> B_IWL<1492> B_IWL<1491> B_IWL<1490> B_IWL<1489> B_IWL<1488> B_IWL<1487> B_IWL<1486> B_IWL<1485> B_IWL<1484> B_IWL<1483> B_IWL<1482> B_IWL<1481> B_IWL<1480> B_IWL<1479> B_IWL<1478> B_IWL<1477> B_IWL<1476> B_IWL<1475> B_IWL<1474> B_IWL<1473> B_IWL<1472> B_IWL<1471> B_IWL<1470> B_IWL<1469> B_IWL<1468> B_IWL<1467> B_IWL<1466> B_IWL<1465> B_IWL<1464> B_IWL<1463> B_IWL<1462> B_IWL<1461> B_IWL<1460> B_IWL<1459> B_IWL<1458> B_IWL<1457> B_IWL<1456> B_IWL<1455> B_IWL<1454> B_IWL<1453> B_IWL<1452> B_IWL<1451> B_IWL<1450> B_IWL<1449> B_IWL<1448> B_IWL<1447> B_IWL<1446> B_IWL<1445> B_IWL<1444> B_IWL<1443> B_IWL<1442> B_IWL<1441> B_IWL<1440> B_IWL<1439> B_IWL<1438> B_IWL<1437> B_IWL<1436> B_IWL<1435> B_IWL<1434> B_IWL<1433> B_IWL<1432> B_IWL<1431> B_IWL<1430> B_IWL<1429> B_IWL<1428> B_IWL<1427> B_IWL<1426> B_IWL<1425> B_IWL<1424> B_IWL<1423> B_IWL<1422> B_IWL<1421> B_IWL<1420> B_IWL<1419> B_IWL<1418> B_IWL<1417> B_IWL<1416> B_IWL<1415> B_IWL<1414> B_IWL<1413> B_IWL<1412> B_IWL<1411> B_IWL<1410> B_IWL<1409> B_IWL<1408> VDD_CORE VSS / RM_IHPSG13_512x32_c2_2P_COLUMN_pcell_0 +XCOL<10> A_BLC<21> A_BLC<20> A_BLC_TOP<21> A_BLC_TOP<20> A_BLT<21> A_BLT<20> A_BLT_TOP<21> A_BLT_TOP<20> A_IWL<1279> A_IWL<1278> A_IWL<1277> A_IWL<1276> A_IWL<1275> A_IWL<1274> A_IWL<1273> A_IWL<1272> A_IWL<1271> A_IWL<1270> A_IWL<1269> A_IWL<1268> A_IWL<1267> A_IWL<1266> A_IWL<1265> A_IWL<1264> A_IWL<1263> A_IWL<1262> A_IWL<1261> A_IWL<1260> A_IWL<1259> A_IWL<1258> A_IWL<1257> A_IWL<1256> A_IWL<1255> A_IWL<1254> A_IWL<1253> A_IWL<1252> A_IWL<1251> A_IWL<1250> A_IWL<1249> A_IWL<1248> A_IWL<1247> A_IWL<1246> A_IWL<1245> A_IWL<1244> A_IWL<1243> A_IWL<1242> A_IWL<1241> A_IWL<1240> A_IWL<1239> A_IWL<1238> A_IWL<1237> A_IWL<1236> A_IWL<1235> A_IWL<1234> A_IWL<1233> A_IWL<1232> A_IWL<1231> A_IWL<1230> A_IWL<1229> A_IWL<1228> A_IWL<1227> A_IWL<1226> A_IWL<1225> A_IWL<1224> A_IWL<1223> A_IWL<1222> A_IWL<1221> A_IWL<1220> A_IWL<1219> A_IWL<1218> A_IWL<1217> A_IWL<1216> A_IWL<1215> A_IWL<1214> A_IWL<1213> A_IWL<1212> A_IWL<1211> A_IWL<1210> A_IWL<1209> A_IWL<1208> A_IWL<1207> A_IWL<1206> A_IWL<1205> A_IWL<1204> A_IWL<1203> A_IWL<1202> A_IWL<1201> A_IWL<1200> A_IWL<1199> A_IWL<1198> A_IWL<1197> A_IWL<1196> A_IWL<1195> A_IWL<1194> A_IWL<1193> A_IWL<1192> A_IWL<1191> A_IWL<1190> A_IWL<1189> A_IWL<1188> A_IWL<1187> A_IWL<1186> A_IWL<1185> A_IWL<1184> A_IWL<1183> A_IWL<1182> A_IWL<1181> A_IWL<1180> A_IWL<1179> A_IWL<1178> A_IWL<1177> A_IWL<1176> A_IWL<1175> A_IWL<1174> A_IWL<1173> A_IWL<1172> A_IWL<1171> A_IWL<1170> A_IWL<1169> A_IWL<1168> A_IWL<1167> A_IWL<1166> A_IWL<1165> A_IWL<1164> A_IWL<1163> A_IWL<1162> A_IWL<1161> A_IWL<1160> A_IWL<1159> A_IWL<1158> A_IWL<1157> A_IWL<1156> A_IWL<1155> A_IWL<1154> A_IWL<1153> A_IWL<1152> A_IWL<1407> A_IWL<1406> A_IWL<1405> A_IWL<1404> A_IWL<1403> A_IWL<1402> A_IWL<1401> A_IWL<1400> A_IWL<1399> A_IWL<1398> A_IWL<1397> A_IWL<1396> A_IWL<1395> A_IWL<1394> A_IWL<1393> A_IWL<1392> A_IWL<1391> A_IWL<1390> A_IWL<1389> A_IWL<1388> A_IWL<1387> A_IWL<1386> A_IWL<1385> A_IWL<1384> A_IWL<1383> A_IWL<1382> A_IWL<1381> A_IWL<1380> A_IWL<1379> A_IWL<1378> A_IWL<1377> A_IWL<1376> A_IWL<1375> A_IWL<1374> A_IWL<1373> A_IWL<1372> A_IWL<1371> A_IWL<1370> A_IWL<1369> A_IWL<1368> A_IWL<1367> A_IWL<1366> A_IWL<1365> A_IWL<1364> A_IWL<1363> A_IWL<1362> A_IWL<1361> A_IWL<1360> A_IWL<1359> A_IWL<1358> A_IWL<1357> A_IWL<1356> A_IWL<1355> A_IWL<1354> A_IWL<1353> A_IWL<1352> A_IWL<1351> A_IWL<1350> A_IWL<1349> A_IWL<1348> A_IWL<1347> A_IWL<1346> A_IWL<1345> A_IWL<1344> A_IWL<1343> A_IWL<1342> A_IWL<1341> A_IWL<1340> A_IWL<1339> A_IWL<1338> A_IWL<1337> A_IWL<1336> A_IWL<1335> A_IWL<1334> A_IWL<1333> A_IWL<1332> A_IWL<1331> A_IWL<1330> A_IWL<1329> A_IWL<1328> A_IWL<1327> A_IWL<1326> A_IWL<1325> A_IWL<1324> A_IWL<1323> A_IWL<1322> A_IWL<1321> A_IWL<1320> A_IWL<1319> A_IWL<1318> A_IWL<1317> A_IWL<1316> A_IWL<1315> A_IWL<1314> A_IWL<1313> A_IWL<1312> A_IWL<1311> A_IWL<1310> A_IWL<1309> A_IWL<1308> A_IWL<1307> A_IWL<1306> A_IWL<1305> A_IWL<1304> A_IWL<1303> A_IWL<1302> A_IWL<1301> A_IWL<1300> A_IWL<1299> A_IWL<1298> A_IWL<1297> A_IWL<1296> A_IWL<1295> A_IWL<1294> A_IWL<1293> A_IWL<1292> A_IWL<1291> A_IWL<1290> A_IWL<1289> A_IWL<1288> A_IWL<1287> A_IWL<1286> A_IWL<1285> A_IWL<1284> A_IWL<1283> A_IWL<1282> A_IWL<1281> A_IWL<1280> B_BLC<21> B_BLC<20> B_BLC_TOP<21> B_BLC_TOP<20> B_BLT<21> B_BLT<20> B_BLT_TOP<21> B_BLT_TOP<20> B_IWL<1279> B_IWL<1278> B_IWL<1277> B_IWL<1276> B_IWL<1275> B_IWL<1274> B_IWL<1273> B_IWL<1272> B_IWL<1271> B_IWL<1270> B_IWL<1269> B_IWL<1268> B_IWL<1267> B_IWL<1266> B_IWL<1265> B_IWL<1264> B_IWL<1263> B_IWL<1262> B_IWL<1261> B_IWL<1260> B_IWL<1259> B_IWL<1258> B_IWL<1257> B_IWL<1256> B_IWL<1255> B_IWL<1254> B_IWL<1253> B_IWL<1252> B_IWL<1251> B_IWL<1250> B_IWL<1249> B_IWL<1248> B_IWL<1247> B_IWL<1246> B_IWL<1245> B_IWL<1244> B_IWL<1243> B_IWL<1242> B_IWL<1241> B_IWL<1240> B_IWL<1239> B_IWL<1238> B_IWL<1237> B_IWL<1236> B_IWL<1235> B_IWL<1234> B_IWL<1233> B_IWL<1232> B_IWL<1231> B_IWL<1230> B_IWL<1229> B_IWL<1228> B_IWL<1227> B_IWL<1226> B_IWL<1225> B_IWL<1224> B_IWL<1223> B_IWL<1222> B_IWL<1221> B_IWL<1220> B_IWL<1219> B_IWL<1218> B_IWL<1217> B_IWL<1216> B_IWL<1215> B_IWL<1214> B_IWL<1213> B_IWL<1212> B_IWL<1211> B_IWL<1210> B_IWL<1209> B_IWL<1208> B_IWL<1207> B_IWL<1206> B_IWL<1205> B_IWL<1204> B_IWL<1203> B_IWL<1202> B_IWL<1201> B_IWL<1200> B_IWL<1199> B_IWL<1198> B_IWL<1197> B_IWL<1196> B_IWL<1195> B_IWL<1194> B_IWL<1193> B_IWL<1192> B_IWL<1191> B_IWL<1190> B_IWL<1189> B_IWL<1188> B_IWL<1187> B_IWL<1186> B_IWL<1185> B_IWL<1184> B_IWL<1183> B_IWL<1182> B_IWL<1181> B_IWL<1180> B_IWL<1179> B_IWL<1178> B_IWL<1177> B_IWL<1176> B_IWL<1175> B_IWL<1174> B_IWL<1173> B_IWL<1172> B_IWL<1171> B_IWL<1170> B_IWL<1169> B_IWL<1168> B_IWL<1167> B_IWL<1166> B_IWL<1165> B_IWL<1164> B_IWL<1163> B_IWL<1162> B_IWL<1161> B_IWL<1160> B_IWL<1159> B_IWL<1158> B_IWL<1157> B_IWL<1156> B_IWL<1155> B_IWL<1154> B_IWL<1153> B_IWL<1152> B_IWL<1407> B_IWL<1406> B_IWL<1405> B_IWL<1404> B_IWL<1403> B_IWL<1402> B_IWL<1401> B_IWL<1400> B_IWL<1399> B_IWL<1398> B_IWL<1397> B_IWL<1396> B_IWL<1395> B_IWL<1394> B_IWL<1393> B_IWL<1392> B_IWL<1391> B_IWL<1390> B_IWL<1389> B_IWL<1388> B_IWL<1387> B_IWL<1386> B_IWL<1385> B_IWL<1384> B_IWL<1383> B_IWL<1382> B_IWL<1381> B_IWL<1380> B_IWL<1379> B_IWL<1378> B_IWL<1377> B_IWL<1376> B_IWL<1375> B_IWL<1374> B_IWL<1373> B_IWL<1372> B_IWL<1371> B_IWL<1370> B_IWL<1369> B_IWL<1368> B_IWL<1367> B_IWL<1366> B_IWL<1365> B_IWL<1364> B_IWL<1363> B_IWL<1362> B_IWL<1361> B_IWL<1360> B_IWL<1359> B_IWL<1358> B_IWL<1357> B_IWL<1356> B_IWL<1355> B_IWL<1354> B_IWL<1353> B_IWL<1352> B_IWL<1351> B_IWL<1350> B_IWL<1349> B_IWL<1348> B_IWL<1347> B_IWL<1346> B_IWL<1345> B_IWL<1344> B_IWL<1343> B_IWL<1342> B_IWL<1341> B_IWL<1340> B_IWL<1339> B_IWL<1338> B_IWL<1337> B_IWL<1336> B_IWL<1335> B_IWL<1334> B_IWL<1333> B_IWL<1332> B_IWL<1331> B_IWL<1330> B_IWL<1329> B_IWL<1328> B_IWL<1327> B_IWL<1326> B_IWL<1325> B_IWL<1324> B_IWL<1323> B_IWL<1322> B_IWL<1321> B_IWL<1320> B_IWL<1319> B_IWL<1318> B_IWL<1317> B_IWL<1316> B_IWL<1315> B_IWL<1314> B_IWL<1313> B_IWL<1312> B_IWL<1311> B_IWL<1310> B_IWL<1309> B_IWL<1308> B_IWL<1307> B_IWL<1306> B_IWL<1305> B_IWL<1304> B_IWL<1303> B_IWL<1302> B_IWL<1301> B_IWL<1300> B_IWL<1299> B_IWL<1298> B_IWL<1297> B_IWL<1296> B_IWL<1295> B_IWL<1294> B_IWL<1293> B_IWL<1292> B_IWL<1291> B_IWL<1290> B_IWL<1289> B_IWL<1288> B_IWL<1287> B_IWL<1286> B_IWL<1285> B_IWL<1284> B_IWL<1283> B_IWL<1282> B_IWL<1281> B_IWL<1280> VDD_CORE VSS / RM_IHPSG13_512x32_c2_2P_COLUMN_pcell_0 +XCOL<9> A_BLC<19> A_BLC<18> A_BLC_TOP<19> A_BLC_TOP<18> A_BLT<19> A_BLT<18> A_BLT_TOP<19> A_BLT_TOP<18> A_IWL<1151> A_IWL<1150> A_IWL<1149> A_IWL<1148> A_IWL<1147> A_IWL<1146> A_IWL<1145> A_IWL<1144> A_IWL<1143> A_IWL<1142> A_IWL<1141> A_IWL<1140> A_IWL<1139> A_IWL<1138> A_IWL<1137> A_IWL<1136> A_IWL<1135> A_IWL<1134> A_IWL<1133> A_IWL<1132> A_IWL<1131> A_IWL<1130> A_IWL<1129> A_IWL<1128> A_IWL<1127> A_IWL<1126> A_IWL<1125> A_IWL<1124> A_IWL<1123> A_IWL<1122> A_IWL<1121> A_IWL<1120> A_IWL<1119> A_IWL<1118> A_IWL<1117> A_IWL<1116> A_IWL<1115> A_IWL<1114> A_IWL<1113> A_IWL<1112> A_IWL<1111> A_IWL<1110> A_IWL<1109> A_IWL<1108> A_IWL<1107> A_IWL<1106> A_IWL<1105> A_IWL<1104> A_IWL<1103> A_IWL<1102> A_IWL<1101> A_IWL<1100> A_IWL<1099> A_IWL<1098> A_IWL<1097> A_IWL<1096> A_IWL<1095> A_IWL<1094> A_IWL<1093> A_IWL<1092> A_IWL<1091> A_IWL<1090> A_IWL<1089> A_IWL<1088> A_IWL<1087> A_IWL<1086> A_IWL<1085> A_IWL<1084> A_IWL<1083> A_IWL<1082> A_IWL<1081> A_IWL<1080> A_IWL<1079> A_IWL<1078> A_IWL<1077> A_IWL<1076> A_IWL<1075> A_IWL<1074> A_IWL<1073> A_IWL<1072> A_IWL<1071> A_IWL<1070> A_IWL<1069> A_IWL<1068> A_IWL<1067> A_IWL<1066> A_IWL<1065> A_IWL<1064> A_IWL<1063> A_IWL<1062> A_IWL<1061> A_IWL<1060> A_IWL<1059> A_IWL<1058> A_IWL<1057> A_IWL<1056> A_IWL<1055> A_IWL<1054> A_IWL<1053> A_IWL<1052> A_IWL<1051> A_IWL<1050> A_IWL<1049> A_IWL<1048> A_IWL<1047> A_IWL<1046> A_IWL<1045> A_IWL<1044> A_IWL<1043> A_IWL<1042> A_IWL<1041> A_IWL<1040> A_IWL<1039> A_IWL<1038> A_IWL<1037> A_IWL<1036> A_IWL<1035> A_IWL<1034> A_IWL<1033> A_IWL<1032> A_IWL<1031> A_IWL<1030> A_IWL<1029> A_IWL<1028> A_IWL<1027> A_IWL<1026> A_IWL<1025> A_IWL<1024> A_IWL<1279> A_IWL<1278> A_IWL<1277> A_IWL<1276> A_IWL<1275> A_IWL<1274> A_IWL<1273> A_IWL<1272> A_IWL<1271> A_IWL<1270> A_IWL<1269> A_IWL<1268> A_IWL<1267> A_IWL<1266> A_IWL<1265> A_IWL<1264> A_IWL<1263> A_IWL<1262> A_IWL<1261> A_IWL<1260> A_IWL<1259> A_IWL<1258> A_IWL<1257> A_IWL<1256> A_IWL<1255> A_IWL<1254> A_IWL<1253> A_IWL<1252> A_IWL<1251> A_IWL<1250> A_IWL<1249> A_IWL<1248> A_IWL<1247> A_IWL<1246> A_IWL<1245> A_IWL<1244> A_IWL<1243> A_IWL<1242> A_IWL<1241> A_IWL<1240> A_IWL<1239> A_IWL<1238> A_IWL<1237> A_IWL<1236> A_IWL<1235> A_IWL<1234> A_IWL<1233> A_IWL<1232> A_IWL<1231> A_IWL<1230> A_IWL<1229> A_IWL<1228> A_IWL<1227> A_IWL<1226> A_IWL<1225> A_IWL<1224> A_IWL<1223> A_IWL<1222> A_IWL<1221> A_IWL<1220> A_IWL<1219> A_IWL<1218> A_IWL<1217> A_IWL<1216> A_IWL<1215> A_IWL<1214> A_IWL<1213> A_IWL<1212> A_IWL<1211> A_IWL<1210> A_IWL<1209> A_IWL<1208> A_IWL<1207> A_IWL<1206> A_IWL<1205> A_IWL<1204> A_IWL<1203> A_IWL<1202> A_IWL<1201> A_IWL<1200> A_IWL<1199> A_IWL<1198> A_IWL<1197> A_IWL<1196> A_IWL<1195> A_IWL<1194> A_IWL<1193> A_IWL<1192> A_IWL<1191> A_IWL<1190> A_IWL<1189> A_IWL<1188> A_IWL<1187> A_IWL<1186> A_IWL<1185> A_IWL<1184> A_IWL<1183> A_IWL<1182> A_IWL<1181> A_IWL<1180> A_IWL<1179> A_IWL<1178> A_IWL<1177> A_IWL<1176> A_IWL<1175> A_IWL<1174> A_IWL<1173> A_IWL<1172> A_IWL<1171> A_IWL<1170> A_IWL<1169> A_IWL<1168> A_IWL<1167> A_IWL<1166> A_IWL<1165> A_IWL<1164> A_IWL<1163> A_IWL<1162> A_IWL<1161> A_IWL<1160> A_IWL<1159> A_IWL<1158> A_IWL<1157> A_IWL<1156> A_IWL<1155> A_IWL<1154> A_IWL<1153> A_IWL<1152> B_BLC<19> B_BLC<18> B_BLC_TOP<19> B_BLC_TOP<18> B_BLT<19> B_BLT<18> B_BLT_TOP<19> B_BLT_TOP<18> B_IWL<1151> B_IWL<1150> B_IWL<1149> B_IWL<1148> B_IWL<1147> B_IWL<1146> B_IWL<1145> B_IWL<1144> B_IWL<1143> B_IWL<1142> B_IWL<1141> B_IWL<1140> B_IWL<1139> B_IWL<1138> B_IWL<1137> B_IWL<1136> B_IWL<1135> B_IWL<1134> B_IWL<1133> B_IWL<1132> B_IWL<1131> B_IWL<1130> B_IWL<1129> B_IWL<1128> B_IWL<1127> B_IWL<1126> B_IWL<1125> B_IWL<1124> B_IWL<1123> B_IWL<1122> B_IWL<1121> B_IWL<1120> B_IWL<1119> B_IWL<1118> B_IWL<1117> B_IWL<1116> B_IWL<1115> B_IWL<1114> B_IWL<1113> B_IWL<1112> B_IWL<1111> B_IWL<1110> B_IWL<1109> B_IWL<1108> B_IWL<1107> B_IWL<1106> B_IWL<1105> B_IWL<1104> B_IWL<1103> B_IWL<1102> B_IWL<1101> B_IWL<1100> B_IWL<1099> B_IWL<1098> B_IWL<1097> B_IWL<1096> B_IWL<1095> B_IWL<1094> B_IWL<1093> B_IWL<1092> B_IWL<1091> B_IWL<1090> B_IWL<1089> B_IWL<1088> B_IWL<1087> B_IWL<1086> B_IWL<1085> B_IWL<1084> B_IWL<1083> B_IWL<1082> B_IWL<1081> B_IWL<1080> B_IWL<1079> B_IWL<1078> B_IWL<1077> B_IWL<1076> B_IWL<1075> B_IWL<1074> B_IWL<1073> B_IWL<1072> B_IWL<1071> B_IWL<1070> B_IWL<1069> B_IWL<1068> B_IWL<1067> B_IWL<1066> B_IWL<1065> B_IWL<1064> B_IWL<1063> B_IWL<1062> B_IWL<1061> B_IWL<1060> B_IWL<1059> B_IWL<1058> B_IWL<1057> B_IWL<1056> B_IWL<1055> B_IWL<1054> B_IWL<1053> B_IWL<1052> B_IWL<1051> B_IWL<1050> B_IWL<1049> B_IWL<1048> B_IWL<1047> B_IWL<1046> B_IWL<1045> B_IWL<1044> B_IWL<1043> B_IWL<1042> B_IWL<1041> B_IWL<1040> B_IWL<1039> B_IWL<1038> B_IWL<1037> B_IWL<1036> B_IWL<1035> B_IWL<1034> B_IWL<1033> B_IWL<1032> B_IWL<1031> B_IWL<1030> B_IWL<1029> B_IWL<1028> B_IWL<1027> B_IWL<1026> B_IWL<1025> B_IWL<1024> B_IWL<1279> B_IWL<1278> B_IWL<1277> B_IWL<1276> B_IWL<1275> B_IWL<1274> B_IWL<1273> B_IWL<1272> B_IWL<1271> B_IWL<1270> B_IWL<1269> B_IWL<1268> B_IWL<1267> B_IWL<1266> B_IWL<1265> B_IWL<1264> B_IWL<1263> B_IWL<1262> B_IWL<1261> B_IWL<1260> B_IWL<1259> B_IWL<1258> B_IWL<1257> B_IWL<1256> B_IWL<1255> B_IWL<1254> B_IWL<1253> B_IWL<1252> B_IWL<1251> B_IWL<1250> B_IWL<1249> B_IWL<1248> B_IWL<1247> B_IWL<1246> B_IWL<1245> B_IWL<1244> B_IWL<1243> B_IWL<1242> B_IWL<1241> B_IWL<1240> B_IWL<1239> B_IWL<1238> B_IWL<1237> B_IWL<1236> B_IWL<1235> B_IWL<1234> B_IWL<1233> B_IWL<1232> B_IWL<1231> B_IWL<1230> B_IWL<1229> B_IWL<1228> B_IWL<1227> B_IWL<1226> B_IWL<1225> B_IWL<1224> B_IWL<1223> B_IWL<1222> B_IWL<1221> B_IWL<1220> B_IWL<1219> B_IWL<1218> B_IWL<1217> B_IWL<1216> B_IWL<1215> B_IWL<1214> B_IWL<1213> B_IWL<1212> B_IWL<1211> B_IWL<1210> B_IWL<1209> B_IWL<1208> B_IWL<1207> B_IWL<1206> B_IWL<1205> B_IWL<1204> B_IWL<1203> B_IWL<1202> B_IWL<1201> B_IWL<1200> B_IWL<1199> B_IWL<1198> B_IWL<1197> B_IWL<1196> B_IWL<1195> B_IWL<1194> B_IWL<1193> B_IWL<1192> B_IWL<1191> B_IWL<1190> B_IWL<1189> B_IWL<1188> B_IWL<1187> B_IWL<1186> B_IWL<1185> B_IWL<1184> B_IWL<1183> B_IWL<1182> B_IWL<1181> B_IWL<1180> B_IWL<1179> B_IWL<1178> B_IWL<1177> B_IWL<1176> B_IWL<1175> B_IWL<1174> B_IWL<1173> B_IWL<1172> B_IWL<1171> B_IWL<1170> B_IWL<1169> B_IWL<1168> B_IWL<1167> B_IWL<1166> B_IWL<1165> B_IWL<1164> B_IWL<1163> B_IWL<1162> B_IWL<1161> B_IWL<1160> B_IWL<1159> B_IWL<1158> B_IWL<1157> B_IWL<1156> B_IWL<1155> B_IWL<1154> B_IWL<1153> B_IWL<1152> VDD_CORE VSS / RM_IHPSG13_512x32_c2_2P_COLUMN_pcell_0 +XCOL<8> A_BLC<17> A_BLC<16> A_BLC_TOP<17> A_BLC_TOP<16> A_BLT<17> A_BLT<16> A_BLT_TOP<17> A_BLT_TOP<16> A_IWL<1023> A_IWL<1022> A_IWL<1021> A_IWL<1020> A_IWL<1019> A_IWL<1018> A_IWL<1017> A_IWL<1016> A_IWL<1015> A_IWL<1014> A_IWL<1013> A_IWL<1012> A_IWL<1011> A_IWL<1010> A_IWL<1009> A_IWL<1008> A_IWL<1007> A_IWL<1006> A_IWL<1005> A_IWL<1004> A_IWL<1003> A_IWL<1002> A_IWL<1001> A_IWL<1000> A_IWL<999> A_IWL<998> A_IWL<997> A_IWL<996> A_IWL<995> A_IWL<994> A_IWL<993> A_IWL<992> A_IWL<991> A_IWL<990> A_IWL<989> A_IWL<988> A_IWL<987> A_IWL<986> A_IWL<985> A_IWL<984> A_IWL<983> A_IWL<982> A_IWL<981> A_IWL<980> A_IWL<979> A_IWL<978> A_IWL<977> A_IWL<976> A_IWL<975> A_IWL<974> A_IWL<973> A_IWL<972> A_IWL<971> A_IWL<970> A_IWL<969> A_IWL<968> A_IWL<967> A_IWL<966> A_IWL<965> A_IWL<964> A_IWL<963> A_IWL<962> A_IWL<961> A_IWL<960> A_IWL<959> A_IWL<958> A_IWL<957> A_IWL<956> A_IWL<955> A_IWL<954> A_IWL<953> A_IWL<952> A_IWL<951> A_IWL<950> A_IWL<949> A_IWL<948> A_IWL<947> A_IWL<946> A_IWL<945> A_IWL<944> A_IWL<943> A_IWL<942> A_IWL<941> A_IWL<940> A_IWL<939> A_IWL<938> A_IWL<937> A_IWL<936> A_IWL<935> A_IWL<934> A_IWL<933> A_IWL<932> A_IWL<931> A_IWL<930> A_IWL<929> A_IWL<928> A_IWL<927> A_IWL<926> A_IWL<925> A_IWL<924> A_IWL<923> A_IWL<922> A_IWL<921> A_IWL<920> A_IWL<919> A_IWL<918> A_IWL<917> A_IWL<916> A_IWL<915> A_IWL<914> A_IWL<913> A_IWL<912> A_IWL<911> A_IWL<910> A_IWL<909> A_IWL<908> A_IWL<907> A_IWL<906> A_IWL<905> A_IWL<904> A_IWL<903> A_IWL<902> A_IWL<901> A_IWL<900> A_IWL<899> A_IWL<898> A_IWL<897> A_IWL<896> A_IWL<1151> A_IWL<1150> A_IWL<1149> A_IWL<1148> A_IWL<1147> A_IWL<1146> A_IWL<1145> A_IWL<1144> A_IWL<1143> A_IWL<1142> A_IWL<1141> A_IWL<1140> A_IWL<1139> A_IWL<1138> A_IWL<1137> A_IWL<1136> A_IWL<1135> A_IWL<1134> A_IWL<1133> A_IWL<1132> A_IWL<1131> A_IWL<1130> A_IWL<1129> A_IWL<1128> A_IWL<1127> A_IWL<1126> A_IWL<1125> A_IWL<1124> A_IWL<1123> A_IWL<1122> A_IWL<1121> A_IWL<1120> A_IWL<1119> A_IWL<1118> A_IWL<1117> A_IWL<1116> A_IWL<1115> A_IWL<1114> A_IWL<1113> A_IWL<1112> A_IWL<1111> A_IWL<1110> A_IWL<1109> A_IWL<1108> A_IWL<1107> A_IWL<1106> A_IWL<1105> A_IWL<1104> A_IWL<1103> A_IWL<1102> A_IWL<1101> A_IWL<1100> A_IWL<1099> A_IWL<1098> A_IWL<1097> A_IWL<1096> A_IWL<1095> A_IWL<1094> A_IWL<1093> A_IWL<1092> A_IWL<1091> A_IWL<1090> A_IWL<1089> A_IWL<1088> A_IWL<1087> A_IWL<1086> A_IWL<1085> A_IWL<1084> A_IWL<1083> A_IWL<1082> A_IWL<1081> A_IWL<1080> A_IWL<1079> A_IWL<1078> A_IWL<1077> A_IWL<1076> A_IWL<1075> A_IWL<1074> A_IWL<1073> A_IWL<1072> A_IWL<1071> A_IWL<1070> A_IWL<1069> A_IWL<1068> A_IWL<1067> A_IWL<1066> A_IWL<1065> A_IWL<1064> A_IWL<1063> A_IWL<1062> A_IWL<1061> A_IWL<1060> A_IWL<1059> A_IWL<1058> A_IWL<1057> A_IWL<1056> A_IWL<1055> A_IWL<1054> A_IWL<1053> A_IWL<1052> A_IWL<1051> A_IWL<1050> A_IWL<1049> A_IWL<1048> A_IWL<1047> A_IWL<1046> A_IWL<1045> A_IWL<1044> A_IWL<1043> A_IWL<1042> A_IWL<1041> A_IWL<1040> A_IWL<1039> A_IWL<1038> A_IWL<1037> A_IWL<1036> A_IWL<1035> A_IWL<1034> A_IWL<1033> A_IWL<1032> A_IWL<1031> A_IWL<1030> A_IWL<1029> A_IWL<1028> A_IWL<1027> A_IWL<1026> A_IWL<1025> A_IWL<1024> B_BLC<17> B_BLC<16> B_BLC_TOP<17> B_BLC_TOP<16> B_BLT<17> B_BLT<16> B_BLT_TOP<17> B_BLT_TOP<16> B_IWL<1023> B_IWL<1022> B_IWL<1021> B_IWL<1020> B_IWL<1019> B_IWL<1018> B_IWL<1017> B_IWL<1016> B_IWL<1015> B_IWL<1014> B_IWL<1013> B_IWL<1012> B_IWL<1011> B_IWL<1010> B_IWL<1009> B_IWL<1008> B_IWL<1007> B_IWL<1006> B_IWL<1005> B_IWL<1004> B_IWL<1003> B_IWL<1002> B_IWL<1001> B_IWL<1000> B_IWL<999> B_IWL<998> B_IWL<997> B_IWL<996> B_IWL<995> B_IWL<994> B_IWL<993> B_IWL<992> B_IWL<991> B_IWL<990> B_IWL<989> B_IWL<988> B_IWL<987> B_IWL<986> B_IWL<985> B_IWL<984> B_IWL<983> B_IWL<982> B_IWL<981> B_IWL<980> B_IWL<979> B_IWL<978> B_IWL<977> B_IWL<976> B_IWL<975> B_IWL<974> B_IWL<973> B_IWL<972> B_IWL<971> B_IWL<970> B_IWL<969> B_IWL<968> B_IWL<967> B_IWL<966> B_IWL<965> B_IWL<964> B_IWL<963> B_IWL<962> B_IWL<961> B_IWL<960> B_IWL<959> B_IWL<958> B_IWL<957> B_IWL<956> B_IWL<955> B_IWL<954> B_IWL<953> B_IWL<952> B_IWL<951> B_IWL<950> B_IWL<949> B_IWL<948> B_IWL<947> B_IWL<946> B_IWL<945> B_IWL<944> B_IWL<943> B_IWL<942> B_IWL<941> B_IWL<940> B_IWL<939> B_IWL<938> B_IWL<937> B_IWL<936> B_IWL<935> B_IWL<934> B_IWL<933> B_IWL<932> B_IWL<931> B_IWL<930> B_IWL<929> B_IWL<928> B_IWL<927> B_IWL<926> B_IWL<925> B_IWL<924> B_IWL<923> B_IWL<922> B_IWL<921> B_IWL<920> B_IWL<919> B_IWL<918> B_IWL<917> B_IWL<916> B_IWL<915> B_IWL<914> B_IWL<913> B_IWL<912> B_IWL<911> B_IWL<910> B_IWL<909> B_IWL<908> B_IWL<907> B_IWL<906> B_IWL<905> B_IWL<904> B_IWL<903> B_IWL<902> B_IWL<901> B_IWL<900> B_IWL<899> B_IWL<898> B_IWL<897> B_IWL<896> B_IWL<1151> B_IWL<1150> B_IWL<1149> B_IWL<1148> B_IWL<1147> B_IWL<1146> B_IWL<1145> B_IWL<1144> B_IWL<1143> B_IWL<1142> B_IWL<1141> B_IWL<1140> B_IWL<1139> B_IWL<1138> B_IWL<1137> B_IWL<1136> B_IWL<1135> B_IWL<1134> B_IWL<1133> B_IWL<1132> B_IWL<1131> B_IWL<1130> B_IWL<1129> B_IWL<1128> B_IWL<1127> B_IWL<1126> B_IWL<1125> B_IWL<1124> B_IWL<1123> B_IWL<1122> B_IWL<1121> B_IWL<1120> B_IWL<1119> B_IWL<1118> B_IWL<1117> B_IWL<1116> B_IWL<1115> B_IWL<1114> B_IWL<1113> B_IWL<1112> B_IWL<1111> B_IWL<1110> B_IWL<1109> B_IWL<1108> B_IWL<1107> B_IWL<1106> B_IWL<1105> B_IWL<1104> B_IWL<1103> B_IWL<1102> B_IWL<1101> B_IWL<1100> B_IWL<1099> B_IWL<1098> B_IWL<1097> B_IWL<1096> B_IWL<1095> B_IWL<1094> B_IWL<1093> B_IWL<1092> B_IWL<1091> B_IWL<1090> B_IWL<1089> B_IWL<1088> B_IWL<1087> B_IWL<1086> B_IWL<1085> B_IWL<1084> B_IWL<1083> B_IWL<1082> B_IWL<1081> B_IWL<1080> B_IWL<1079> B_IWL<1078> B_IWL<1077> B_IWL<1076> B_IWL<1075> B_IWL<1074> B_IWL<1073> B_IWL<1072> B_IWL<1071> B_IWL<1070> B_IWL<1069> B_IWL<1068> B_IWL<1067> B_IWL<1066> B_IWL<1065> B_IWL<1064> B_IWL<1063> B_IWL<1062> B_IWL<1061> B_IWL<1060> B_IWL<1059> B_IWL<1058> B_IWL<1057> B_IWL<1056> B_IWL<1055> B_IWL<1054> B_IWL<1053> B_IWL<1052> B_IWL<1051> B_IWL<1050> B_IWL<1049> B_IWL<1048> B_IWL<1047> B_IWL<1046> B_IWL<1045> B_IWL<1044> B_IWL<1043> B_IWL<1042> B_IWL<1041> B_IWL<1040> B_IWL<1039> B_IWL<1038> B_IWL<1037> B_IWL<1036> B_IWL<1035> B_IWL<1034> B_IWL<1033> B_IWL<1032> B_IWL<1031> B_IWL<1030> B_IWL<1029> B_IWL<1028> B_IWL<1027> B_IWL<1026> B_IWL<1025> B_IWL<1024> VDD_CORE VSS / RM_IHPSG13_512x32_c2_2P_COLUMN_pcell_0 +XCOL<7> A_BLC<15> A_BLC<14> A_BLC_TOP<15> A_BLC_TOP<14> A_BLT<15> A_BLT<14> A_BLT_TOP<15> A_BLT_TOP<14> A_IWL<895> A_IWL<894> A_IWL<893> A_IWL<892> A_IWL<891> A_IWL<890> A_IWL<889> A_IWL<888> A_IWL<887> A_IWL<886> A_IWL<885> A_IWL<884> A_IWL<883> A_IWL<882> A_IWL<881> A_IWL<880> A_IWL<879> A_IWL<878> A_IWL<877> A_IWL<876> A_IWL<875> A_IWL<874> A_IWL<873> A_IWL<872> A_IWL<871> A_IWL<870> A_IWL<869> A_IWL<868> A_IWL<867> A_IWL<866> A_IWL<865> A_IWL<864> A_IWL<863> A_IWL<862> A_IWL<861> A_IWL<860> A_IWL<859> A_IWL<858> A_IWL<857> A_IWL<856> A_IWL<855> A_IWL<854> A_IWL<853> A_IWL<852> A_IWL<851> A_IWL<850> A_IWL<849> A_IWL<848> A_IWL<847> A_IWL<846> A_IWL<845> A_IWL<844> A_IWL<843> A_IWL<842> A_IWL<841> A_IWL<840> A_IWL<839> A_IWL<838> A_IWL<837> A_IWL<836> A_IWL<835> A_IWL<834> A_IWL<833> A_IWL<832> A_IWL<831> A_IWL<830> A_IWL<829> A_IWL<828> A_IWL<827> A_IWL<826> A_IWL<825> A_IWL<824> A_IWL<823> A_IWL<822> A_IWL<821> A_IWL<820> A_IWL<819> A_IWL<818> A_IWL<817> A_IWL<816> A_IWL<815> A_IWL<814> A_IWL<813> A_IWL<812> A_IWL<811> A_IWL<810> A_IWL<809> A_IWL<808> A_IWL<807> A_IWL<806> A_IWL<805> A_IWL<804> A_IWL<803> A_IWL<802> A_IWL<801> A_IWL<800> A_IWL<799> A_IWL<798> A_IWL<797> A_IWL<796> A_IWL<795> A_IWL<794> A_IWL<793> A_IWL<792> A_IWL<791> A_IWL<790> A_IWL<789> A_IWL<788> A_IWL<787> A_IWL<786> A_IWL<785> A_IWL<784> A_IWL<783> A_IWL<782> A_IWL<781> A_IWL<780> A_IWL<779> A_IWL<778> A_IWL<777> A_IWL<776> A_IWL<775> A_IWL<774> A_IWL<773> A_IWL<772> A_IWL<771> A_IWL<770> A_IWL<769> A_IWL<768> A_IWL<1023> A_IWL<1022> A_IWL<1021> A_IWL<1020> A_IWL<1019> A_IWL<1018> A_IWL<1017> A_IWL<1016> A_IWL<1015> A_IWL<1014> A_IWL<1013> A_IWL<1012> A_IWL<1011> A_IWL<1010> A_IWL<1009> A_IWL<1008> A_IWL<1007> A_IWL<1006> A_IWL<1005> A_IWL<1004> A_IWL<1003> A_IWL<1002> A_IWL<1001> A_IWL<1000> A_IWL<999> A_IWL<998> A_IWL<997> A_IWL<996> A_IWL<995> A_IWL<994> A_IWL<993> A_IWL<992> A_IWL<991> A_IWL<990> A_IWL<989> A_IWL<988> A_IWL<987> A_IWL<986> A_IWL<985> A_IWL<984> A_IWL<983> A_IWL<982> A_IWL<981> A_IWL<980> A_IWL<979> A_IWL<978> A_IWL<977> A_IWL<976> A_IWL<975> A_IWL<974> A_IWL<973> A_IWL<972> A_IWL<971> A_IWL<970> A_IWL<969> A_IWL<968> A_IWL<967> A_IWL<966> A_IWL<965> A_IWL<964> A_IWL<963> A_IWL<962> A_IWL<961> A_IWL<960> A_IWL<959> A_IWL<958> A_IWL<957> A_IWL<956> A_IWL<955> A_IWL<954> A_IWL<953> A_IWL<952> A_IWL<951> A_IWL<950> A_IWL<949> A_IWL<948> A_IWL<947> A_IWL<946> A_IWL<945> A_IWL<944> A_IWL<943> A_IWL<942> A_IWL<941> A_IWL<940> A_IWL<939> A_IWL<938> A_IWL<937> A_IWL<936> A_IWL<935> A_IWL<934> A_IWL<933> A_IWL<932> A_IWL<931> A_IWL<930> A_IWL<929> A_IWL<928> A_IWL<927> A_IWL<926> A_IWL<925> A_IWL<924> A_IWL<923> A_IWL<922> A_IWL<921> A_IWL<920> A_IWL<919> A_IWL<918> A_IWL<917> A_IWL<916> A_IWL<915> A_IWL<914> A_IWL<913> A_IWL<912> A_IWL<911> A_IWL<910> A_IWL<909> A_IWL<908> A_IWL<907> A_IWL<906> A_IWL<905> A_IWL<904> A_IWL<903> A_IWL<902> A_IWL<901> A_IWL<900> A_IWL<899> A_IWL<898> A_IWL<897> A_IWL<896> B_BLC<15> B_BLC<14> B_BLC_TOP<15> B_BLC_TOP<14> B_BLT<15> B_BLT<14> B_BLT_TOP<15> B_BLT_TOP<14> B_IWL<895> B_IWL<894> B_IWL<893> B_IWL<892> B_IWL<891> B_IWL<890> B_IWL<889> B_IWL<888> B_IWL<887> B_IWL<886> B_IWL<885> B_IWL<884> B_IWL<883> B_IWL<882> B_IWL<881> B_IWL<880> B_IWL<879> B_IWL<878> B_IWL<877> B_IWL<876> B_IWL<875> B_IWL<874> B_IWL<873> B_IWL<872> B_IWL<871> B_IWL<870> B_IWL<869> B_IWL<868> B_IWL<867> B_IWL<866> B_IWL<865> B_IWL<864> B_IWL<863> B_IWL<862> B_IWL<861> B_IWL<860> B_IWL<859> B_IWL<858> B_IWL<857> B_IWL<856> B_IWL<855> B_IWL<854> B_IWL<853> B_IWL<852> B_IWL<851> B_IWL<850> B_IWL<849> B_IWL<848> B_IWL<847> B_IWL<846> B_IWL<845> B_IWL<844> B_IWL<843> B_IWL<842> B_IWL<841> B_IWL<840> B_IWL<839> B_IWL<838> B_IWL<837> B_IWL<836> B_IWL<835> B_IWL<834> B_IWL<833> B_IWL<832> B_IWL<831> B_IWL<830> B_IWL<829> B_IWL<828> B_IWL<827> B_IWL<826> B_IWL<825> B_IWL<824> B_IWL<823> B_IWL<822> B_IWL<821> B_IWL<820> B_IWL<819> B_IWL<818> B_IWL<817> B_IWL<816> B_IWL<815> B_IWL<814> B_IWL<813> B_IWL<812> B_IWL<811> B_IWL<810> B_IWL<809> B_IWL<808> B_IWL<807> B_IWL<806> B_IWL<805> B_IWL<804> B_IWL<803> B_IWL<802> B_IWL<801> B_IWL<800> B_IWL<799> B_IWL<798> B_IWL<797> B_IWL<796> B_IWL<795> B_IWL<794> B_IWL<793> B_IWL<792> B_IWL<791> B_IWL<790> B_IWL<789> B_IWL<788> B_IWL<787> B_IWL<786> B_IWL<785> B_IWL<784> B_IWL<783> B_IWL<782> B_IWL<781> B_IWL<780> B_IWL<779> B_IWL<778> B_IWL<777> B_IWL<776> B_IWL<775> B_IWL<774> B_IWL<773> B_IWL<772> B_IWL<771> B_IWL<770> B_IWL<769> B_IWL<768> B_IWL<1023> B_IWL<1022> B_IWL<1021> B_IWL<1020> B_IWL<1019> B_IWL<1018> B_IWL<1017> B_IWL<1016> B_IWL<1015> B_IWL<1014> B_IWL<1013> B_IWL<1012> B_IWL<1011> B_IWL<1010> B_IWL<1009> B_IWL<1008> B_IWL<1007> B_IWL<1006> B_IWL<1005> B_IWL<1004> B_IWL<1003> B_IWL<1002> B_IWL<1001> B_IWL<1000> B_IWL<999> B_IWL<998> B_IWL<997> B_IWL<996> B_IWL<995> B_IWL<994> B_IWL<993> B_IWL<992> B_IWL<991> B_IWL<990> B_IWL<989> B_IWL<988> B_IWL<987> B_IWL<986> B_IWL<985> B_IWL<984> B_IWL<983> B_IWL<982> B_IWL<981> B_IWL<980> B_IWL<979> B_IWL<978> B_IWL<977> B_IWL<976> B_IWL<975> B_IWL<974> B_IWL<973> B_IWL<972> B_IWL<971> B_IWL<970> B_IWL<969> B_IWL<968> B_IWL<967> B_IWL<966> B_IWL<965> B_IWL<964> B_IWL<963> B_IWL<962> B_IWL<961> B_IWL<960> B_IWL<959> B_IWL<958> B_IWL<957> B_IWL<956> B_IWL<955> B_IWL<954> B_IWL<953> B_IWL<952> B_IWL<951> B_IWL<950> B_IWL<949> B_IWL<948> B_IWL<947> B_IWL<946> B_IWL<945> B_IWL<944> B_IWL<943> B_IWL<942> B_IWL<941> B_IWL<940> B_IWL<939> B_IWL<938> B_IWL<937> B_IWL<936> B_IWL<935> B_IWL<934> B_IWL<933> B_IWL<932> B_IWL<931> B_IWL<930> B_IWL<929> B_IWL<928> B_IWL<927> B_IWL<926> B_IWL<925> B_IWL<924> B_IWL<923> B_IWL<922> B_IWL<921> B_IWL<920> B_IWL<919> B_IWL<918> B_IWL<917> B_IWL<916> B_IWL<915> B_IWL<914> B_IWL<913> B_IWL<912> B_IWL<911> B_IWL<910> B_IWL<909> B_IWL<908> B_IWL<907> B_IWL<906> B_IWL<905> B_IWL<904> B_IWL<903> B_IWL<902> B_IWL<901> B_IWL<900> B_IWL<899> B_IWL<898> B_IWL<897> B_IWL<896> VDD_CORE VSS / RM_IHPSG13_512x32_c2_2P_COLUMN_pcell_0 +XCOL<6> A_BLC<13> A_BLC<12> A_BLC_TOP<13> A_BLC_TOP<12> A_BLT<13> A_BLT<12> A_BLT_TOP<13> A_BLT_TOP<12> A_IWL<767> A_IWL<766> A_IWL<765> A_IWL<764> A_IWL<763> A_IWL<762> A_IWL<761> A_IWL<760> A_IWL<759> A_IWL<758> A_IWL<757> A_IWL<756> A_IWL<755> A_IWL<754> A_IWL<753> A_IWL<752> A_IWL<751> A_IWL<750> A_IWL<749> A_IWL<748> A_IWL<747> A_IWL<746> A_IWL<745> A_IWL<744> A_IWL<743> A_IWL<742> A_IWL<741> A_IWL<740> A_IWL<739> A_IWL<738> A_IWL<737> A_IWL<736> A_IWL<735> A_IWL<734> A_IWL<733> A_IWL<732> A_IWL<731> A_IWL<730> A_IWL<729> A_IWL<728> A_IWL<727> A_IWL<726> A_IWL<725> A_IWL<724> A_IWL<723> A_IWL<722> A_IWL<721> A_IWL<720> A_IWL<719> A_IWL<718> A_IWL<717> A_IWL<716> A_IWL<715> A_IWL<714> A_IWL<713> A_IWL<712> A_IWL<711> A_IWL<710> A_IWL<709> A_IWL<708> A_IWL<707> A_IWL<706> A_IWL<705> A_IWL<704> A_IWL<703> A_IWL<702> A_IWL<701> A_IWL<700> A_IWL<699> A_IWL<698> A_IWL<697> A_IWL<696> A_IWL<695> A_IWL<694> A_IWL<693> A_IWL<692> A_IWL<691> A_IWL<690> A_IWL<689> A_IWL<688> A_IWL<687> A_IWL<686> A_IWL<685> A_IWL<684> A_IWL<683> A_IWL<682> A_IWL<681> A_IWL<680> A_IWL<679> A_IWL<678> A_IWL<677> A_IWL<676> A_IWL<675> A_IWL<674> A_IWL<673> A_IWL<672> A_IWL<671> A_IWL<670> A_IWL<669> A_IWL<668> A_IWL<667> A_IWL<666> A_IWL<665> A_IWL<664> A_IWL<663> A_IWL<662> A_IWL<661> A_IWL<660> A_IWL<659> A_IWL<658> A_IWL<657> A_IWL<656> A_IWL<655> A_IWL<654> A_IWL<653> A_IWL<652> A_IWL<651> A_IWL<650> A_IWL<649> A_IWL<648> A_IWL<647> A_IWL<646> A_IWL<645> A_IWL<644> A_IWL<643> A_IWL<642> A_IWL<641> A_IWL<640> A_IWL<895> A_IWL<894> A_IWL<893> A_IWL<892> A_IWL<891> A_IWL<890> A_IWL<889> A_IWL<888> A_IWL<887> A_IWL<886> A_IWL<885> A_IWL<884> A_IWL<883> A_IWL<882> A_IWL<881> A_IWL<880> A_IWL<879> A_IWL<878> A_IWL<877> A_IWL<876> A_IWL<875> A_IWL<874> A_IWL<873> A_IWL<872> A_IWL<871> A_IWL<870> A_IWL<869> A_IWL<868> A_IWL<867> A_IWL<866> A_IWL<865> A_IWL<864> A_IWL<863> A_IWL<862> A_IWL<861> A_IWL<860> A_IWL<859> A_IWL<858> A_IWL<857> A_IWL<856> A_IWL<855> A_IWL<854> A_IWL<853> A_IWL<852> A_IWL<851> A_IWL<850> A_IWL<849> A_IWL<848> A_IWL<847> A_IWL<846> A_IWL<845> A_IWL<844> A_IWL<843> A_IWL<842> A_IWL<841> A_IWL<840> A_IWL<839> A_IWL<838> A_IWL<837> A_IWL<836> A_IWL<835> A_IWL<834> A_IWL<833> A_IWL<832> A_IWL<831> A_IWL<830> A_IWL<829> A_IWL<828> A_IWL<827> A_IWL<826> A_IWL<825> A_IWL<824> A_IWL<823> A_IWL<822> A_IWL<821> A_IWL<820> A_IWL<819> A_IWL<818> A_IWL<817> A_IWL<816> A_IWL<815> A_IWL<814> A_IWL<813> A_IWL<812> A_IWL<811> A_IWL<810> A_IWL<809> A_IWL<808> A_IWL<807> A_IWL<806> A_IWL<805> A_IWL<804> A_IWL<803> A_IWL<802> A_IWL<801> A_IWL<800> A_IWL<799> A_IWL<798> A_IWL<797> A_IWL<796> A_IWL<795> A_IWL<794> A_IWL<793> A_IWL<792> A_IWL<791> A_IWL<790> A_IWL<789> A_IWL<788> A_IWL<787> A_IWL<786> A_IWL<785> A_IWL<784> A_IWL<783> A_IWL<782> A_IWL<781> A_IWL<780> A_IWL<779> A_IWL<778> A_IWL<777> A_IWL<776> A_IWL<775> A_IWL<774> A_IWL<773> A_IWL<772> A_IWL<771> A_IWL<770> A_IWL<769> A_IWL<768> B_BLC<13> B_BLC<12> B_BLC_TOP<13> B_BLC_TOP<12> B_BLT<13> B_BLT<12> B_BLT_TOP<13> B_BLT_TOP<12> B_IWL<767> B_IWL<766> B_IWL<765> B_IWL<764> B_IWL<763> B_IWL<762> B_IWL<761> B_IWL<760> B_IWL<759> B_IWL<758> B_IWL<757> B_IWL<756> B_IWL<755> B_IWL<754> B_IWL<753> B_IWL<752> B_IWL<751> B_IWL<750> B_IWL<749> B_IWL<748> B_IWL<747> B_IWL<746> B_IWL<745> B_IWL<744> B_IWL<743> B_IWL<742> B_IWL<741> B_IWL<740> B_IWL<739> B_IWL<738> B_IWL<737> B_IWL<736> B_IWL<735> B_IWL<734> B_IWL<733> B_IWL<732> B_IWL<731> B_IWL<730> B_IWL<729> B_IWL<728> B_IWL<727> B_IWL<726> B_IWL<725> B_IWL<724> B_IWL<723> B_IWL<722> B_IWL<721> B_IWL<720> B_IWL<719> B_IWL<718> B_IWL<717> B_IWL<716> B_IWL<715> B_IWL<714> B_IWL<713> B_IWL<712> B_IWL<711> B_IWL<710> B_IWL<709> B_IWL<708> B_IWL<707> B_IWL<706> B_IWL<705> B_IWL<704> B_IWL<703> B_IWL<702> B_IWL<701> B_IWL<700> B_IWL<699> B_IWL<698> B_IWL<697> B_IWL<696> B_IWL<695> B_IWL<694> B_IWL<693> B_IWL<692> B_IWL<691> B_IWL<690> B_IWL<689> B_IWL<688> B_IWL<687> B_IWL<686> B_IWL<685> B_IWL<684> B_IWL<683> B_IWL<682> B_IWL<681> B_IWL<680> B_IWL<679> B_IWL<678> B_IWL<677> B_IWL<676> B_IWL<675> B_IWL<674> B_IWL<673> B_IWL<672> B_IWL<671> B_IWL<670> B_IWL<669> B_IWL<668> B_IWL<667> B_IWL<666> B_IWL<665> B_IWL<664> B_IWL<663> B_IWL<662> B_IWL<661> B_IWL<660> B_IWL<659> B_IWL<658> B_IWL<657> B_IWL<656> B_IWL<655> B_IWL<654> B_IWL<653> B_IWL<652> B_IWL<651> B_IWL<650> B_IWL<649> B_IWL<648> B_IWL<647> B_IWL<646> B_IWL<645> B_IWL<644> B_IWL<643> B_IWL<642> B_IWL<641> B_IWL<640> B_IWL<895> B_IWL<894> B_IWL<893> B_IWL<892> B_IWL<891> B_IWL<890> B_IWL<889> B_IWL<888> B_IWL<887> B_IWL<886> B_IWL<885> B_IWL<884> B_IWL<883> B_IWL<882> B_IWL<881> B_IWL<880> B_IWL<879> B_IWL<878> B_IWL<877> B_IWL<876> B_IWL<875> B_IWL<874> B_IWL<873> B_IWL<872> B_IWL<871> B_IWL<870> B_IWL<869> B_IWL<868> B_IWL<867> B_IWL<866> B_IWL<865> B_IWL<864> B_IWL<863> B_IWL<862> B_IWL<861> B_IWL<860> B_IWL<859> B_IWL<858> B_IWL<857> B_IWL<856> B_IWL<855> B_IWL<854> B_IWL<853> B_IWL<852> B_IWL<851> B_IWL<850> B_IWL<849> B_IWL<848> B_IWL<847> B_IWL<846> B_IWL<845> B_IWL<844> B_IWL<843> B_IWL<842> B_IWL<841> B_IWL<840> B_IWL<839> B_IWL<838> B_IWL<837> B_IWL<836> B_IWL<835> B_IWL<834> B_IWL<833> B_IWL<832> B_IWL<831> B_IWL<830> B_IWL<829> B_IWL<828> B_IWL<827> B_IWL<826> B_IWL<825> B_IWL<824> B_IWL<823> B_IWL<822> B_IWL<821> B_IWL<820> B_IWL<819> B_IWL<818> B_IWL<817> B_IWL<816> B_IWL<815> B_IWL<814> B_IWL<813> B_IWL<812> B_IWL<811> B_IWL<810> B_IWL<809> B_IWL<808> B_IWL<807> B_IWL<806> B_IWL<805> B_IWL<804> B_IWL<803> B_IWL<802> B_IWL<801> B_IWL<800> B_IWL<799> B_IWL<798> B_IWL<797> B_IWL<796> B_IWL<795> B_IWL<794> B_IWL<793> B_IWL<792> B_IWL<791> B_IWL<790> B_IWL<789> B_IWL<788> B_IWL<787> B_IWL<786> B_IWL<785> B_IWL<784> B_IWL<783> B_IWL<782> B_IWL<781> B_IWL<780> B_IWL<779> B_IWL<778> B_IWL<777> B_IWL<776> B_IWL<775> B_IWL<774> B_IWL<773> B_IWL<772> B_IWL<771> B_IWL<770> B_IWL<769> B_IWL<768> VDD_CORE VSS / RM_IHPSG13_512x32_c2_2P_COLUMN_pcell_0 +XCOL<5> A_BLC<11> A_BLC<10> A_BLC_TOP<11> A_BLC_TOP<10> A_BLT<11> A_BLT<10> A_BLT_TOP<11> A_BLT_TOP<10> A_IWL<639> A_IWL<638> A_IWL<637> A_IWL<636> A_IWL<635> A_IWL<634> A_IWL<633> A_IWL<632> A_IWL<631> A_IWL<630> A_IWL<629> A_IWL<628> A_IWL<627> A_IWL<626> A_IWL<625> A_IWL<624> A_IWL<623> A_IWL<622> A_IWL<621> A_IWL<620> A_IWL<619> A_IWL<618> A_IWL<617> A_IWL<616> A_IWL<615> A_IWL<614> A_IWL<613> A_IWL<612> A_IWL<611> A_IWL<610> A_IWL<609> A_IWL<608> A_IWL<607> A_IWL<606> A_IWL<605> A_IWL<604> A_IWL<603> A_IWL<602> A_IWL<601> A_IWL<600> A_IWL<599> A_IWL<598> A_IWL<597> A_IWL<596> A_IWL<595> A_IWL<594> A_IWL<593> A_IWL<592> A_IWL<591> A_IWL<590> A_IWL<589> A_IWL<588> A_IWL<587> A_IWL<586> A_IWL<585> A_IWL<584> A_IWL<583> A_IWL<582> A_IWL<581> A_IWL<580> A_IWL<579> A_IWL<578> A_IWL<577> A_IWL<576> A_IWL<575> A_IWL<574> A_IWL<573> A_IWL<572> A_IWL<571> A_IWL<570> A_IWL<569> A_IWL<568> A_IWL<567> A_IWL<566> A_IWL<565> A_IWL<564> A_IWL<563> A_IWL<562> A_IWL<561> A_IWL<560> A_IWL<559> A_IWL<558> A_IWL<557> A_IWL<556> A_IWL<555> A_IWL<554> A_IWL<553> A_IWL<552> A_IWL<551> A_IWL<550> A_IWL<549> A_IWL<548> A_IWL<547> A_IWL<546> A_IWL<545> A_IWL<544> A_IWL<543> A_IWL<542> A_IWL<541> A_IWL<540> A_IWL<539> A_IWL<538> A_IWL<537> A_IWL<536> A_IWL<535> A_IWL<534> A_IWL<533> A_IWL<532> A_IWL<531> A_IWL<530> A_IWL<529> A_IWL<528> A_IWL<527> A_IWL<526> A_IWL<525> A_IWL<524> A_IWL<523> A_IWL<522> A_IWL<521> A_IWL<520> A_IWL<519> A_IWL<518> A_IWL<517> A_IWL<516> A_IWL<515> A_IWL<514> A_IWL<513> A_IWL<512> A_IWL<767> A_IWL<766> A_IWL<765> A_IWL<764> A_IWL<763> A_IWL<762> A_IWL<761> A_IWL<760> A_IWL<759> A_IWL<758> A_IWL<757> A_IWL<756> A_IWL<755> A_IWL<754> A_IWL<753> A_IWL<752> A_IWL<751> A_IWL<750> A_IWL<749> A_IWL<748> A_IWL<747> A_IWL<746> A_IWL<745> A_IWL<744> A_IWL<743> A_IWL<742> A_IWL<741> A_IWL<740> A_IWL<739> A_IWL<738> A_IWL<737> A_IWL<736> A_IWL<735> A_IWL<734> A_IWL<733> A_IWL<732> A_IWL<731> A_IWL<730> A_IWL<729> A_IWL<728> A_IWL<727> A_IWL<726> A_IWL<725> A_IWL<724> A_IWL<723> A_IWL<722> A_IWL<721> A_IWL<720> A_IWL<719> A_IWL<718> A_IWL<717> A_IWL<716> A_IWL<715> A_IWL<714> A_IWL<713> A_IWL<712> A_IWL<711> A_IWL<710> A_IWL<709> A_IWL<708> A_IWL<707> A_IWL<706> A_IWL<705> A_IWL<704> A_IWL<703> A_IWL<702> A_IWL<701> A_IWL<700> A_IWL<699> A_IWL<698> A_IWL<697> A_IWL<696> A_IWL<695> A_IWL<694> A_IWL<693> A_IWL<692> A_IWL<691> A_IWL<690> A_IWL<689> A_IWL<688> A_IWL<687> A_IWL<686> A_IWL<685> A_IWL<684> A_IWL<683> A_IWL<682> A_IWL<681> A_IWL<680> A_IWL<679> A_IWL<678> A_IWL<677> A_IWL<676> A_IWL<675> A_IWL<674> A_IWL<673> A_IWL<672> A_IWL<671> A_IWL<670> A_IWL<669> A_IWL<668> A_IWL<667> A_IWL<666> A_IWL<665> A_IWL<664> A_IWL<663> A_IWL<662> A_IWL<661> A_IWL<660> A_IWL<659> A_IWL<658> A_IWL<657> A_IWL<656> A_IWL<655> A_IWL<654> A_IWL<653> A_IWL<652> A_IWL<651> A_IWL<650> A_IWL<649> A_IWL<648> A_IWL<647> A_IWL<646> A_IWL<645> A_IWL<644> A_IWL<643> A_IWL<642> A_IWL<641> A_IWL<640> B_BLC<11> B_BLC<10> B_BLC_TOP<11> B_BLC_TOP<10> B_BLT<11> B_BLT<10> B_BLT_TOP<11> B_BLT_TOP<10> B_IWL<639> B_IWL<638> B_IWL<637> B_IWL<636> B_IWL<635> B_IWL<634> B_IWL<633> B_IWL<632> B_IWL<631> B_IWL<630> B_IWL<629> B_IWL<628> B_IWL<627> B_IWL<626> B_IWL<625> B_IWL<624> B_IWL<623> B_IWL<622> B_IWL<621> B_IWL<620> B_IWL<619> B_IWL<618> B_IWL<617> B_IWL<616> B_IWL<615> B_IWL<614> B_IWL<613> B_IWL<612> B_IWL<611> B_IWL<610> B_IWL<609> B_IWL<608> B_IWL<607> B_IWL<606> B_IWL<605> B_IWL<604> B_IWL<603> B_IWL<602> B_IWL<601> B_IWL<600> B_IWL<599> B_IWL<598> B_IWL<597> B_IWL<596> B_IWL<595> B_IWL<594> B_IWL<593> B_IWL<592> B_IWL<591> B_IWL<590> B_IWL<589> B_IWL<588> B_IWL<587> B_IWL<586> B_IWL<585> B_IWL<584> B_IWL<583> B_IWL<582> B_IWL<581> B_IWL<580> B_IWL<579> B_IWL<578> B_IWL<577> B_IWL<576> B_IWL<575> B_IWL<574> B_IWL<573> B_IWL<572> B_IWL<571> B_IWL<570> B_IWL<569> B_IWL<568> B_IWL<567> B_IWL<566> B_IWL<565> B_IWL<564> B_IWL<563> B_IWL<562> B_IWL<561> B_IWL<560> B_IWL<559> B_IWL<558> B_IWL<557> B_IWL<556> B_IWL<555> B_IWL<554> B_IWL<553> B_IWL<552> B_IWL<551> B_IWL<550> B_IWL<549> B_IWL<548> B_IWL<547> B_IWL<546> B_IWL<545> B_IWL<544> B_IWL<543> B_IWL<542> B_IWL<541> B_IWL<540> B_IWL<539> B_IWL<538> B_IWL<537> B_IWL<536> B_IWL<535> B_IWL<534> B_IWL<533> B_IWL<532> B_IWL<531> B_IWL<530> B_IWL<529> B_IWL<528> B_IWL<527> B_IWL<526> B_IWL<525> B_IWL<524> B_IWL<523> B_IWL<522> B_IWL<521> B_IWL<520> B_IWL<519> B_IWL<518> B_IWL<517> B_IWL<516> B_IWL<515> B_IWL<514> B_IWL<513> B_IWL<512> B_IWL<767> B_IWL<766> B_IWL<765> B_IWL<764> B_IWL<763> B_IWL<762> B_IWL<761> B_IWL<760> B_IWL<759> B_IWL<758> B_IWL<757> B_IWL<756> B_IWL<755> B_IWL<754> B_IWL<753> B_IWL<752> B_IWL<751> B_IWL<750> B_IWL<749> B_IWL<748> B_IWL<747> B_IWL<746> B_IWL<745> B_IWL<744> B_IWL<743> B_IWL<742> B_IWL<741> B_IWL<740> B_IWL<739> B_IWL<738> B_IWL<737> B_IWL<736> B_IWL<735> B_IWL<734> B_IWL<733> B_IWL<732> B_IWL<731> B_IWL<730> B_IWL<729> B_IWL<728> B_IWL<727> B_IWL<726> B_IWL<725> B_IWL<724> B_IWL<723> B_IWL<722> B_IWL<721> B_IWL<720> B_IWL<719> B_IWL<718> B_IWL<717> B_IWL<716> B_IWL<715> B_IWL<714> B_IWL<713> B_IWL<712> B_IWL<711> B_IWL<710> B_IWL<709> B_IWL<708> B_IWL<707> B_IWL<706> B_IWL<705> B_IWL<704> B_IWL<703> B_IWL<702> B_IWL<701> B_IWL<700> B_IWL<699> B_IWL<698> B_IWL<697> B_IWL<696> B_IWL<695> B_IWL<694> B_IWL<693> B_IWL<692> B_IWL<691> B_IWL<690> B_IWL<689> B_IWL<688> B_IWL<687> B_IWL<686> B_IWL<685> B_IWL<684> B_IWL<683> B_IWL<682> B_IWL<681> B_IWL<680> B_IWL<679> B_IWL<678> B_IWL<677> B_IWL<676> B_IWL<675> B_IWL<674> B_IWL<673> B_IWL<672> B_IWL<671> B_IWL<670> B_IWL<669> B_IWL<668> B_IWL<667> B_IWL<666> B_IWL<665> B_IWL<664> B_IWL<663> B_IWL<662> B_IWL<661> B_IWL<660> B_IWL<659> B_IWL<658> B_IWL<657> B_IWL<656> B_IWL<655> B_IWL<654> B_IWL<653> B_IWL<652> B_IWL<651> B_IWL<650> B_IWL<649> B_IWL<648> B_IWL<647> B_IWL<646> B_IWL<645> B_IWL<644> B_IWL<643> B_IWL<642> B_IWL<641> B_IWL<640> VDD_CORE VSS / RM_IHPSG13_512x32_c2_2P_COLUMN_pcell_0 +XCOL<4> A_BLC<9> A_BLC<8> A_BLC_TOP<9> A_BLC_TOP<8> A_BLT<9> A_BLT<8> A_BLT_TOP<9> A_BLT_TOP<8> A_IWL<511> A_IWL<510> A_IWL<509> A_IWL<508> A_IWL<507> A_IWL<506> A_IWL<505> A_IWL<504> A_IWL<503> A_IWL<502> A_IWL<501> A_IWL<500> A_IWL<499> A_IWL<498> A_IWL<497> A_IWL<496> A_IWL<495> A_IWL<494> A_IWL<493> A_IWL<492> A_IWL<491> A_IWL<490> A_IWL<489> A_IWL<488> A_IWL<487> A_IWL<486> A_IWL<485> A_IWL<484> A_IWL<483> A_IWL<482> A_IWL<481> A_IWL<480> A_IWL<479> A_IWL<478> A_IWL<477> A_IWL<476> A_IWL<475> A_IWL<474> A_IWL<473> A_IWL<472> A_IWL<471> A_IWL<470> A_IWL<469> A_IWL<468> A_IWL<467> A_IWL<466> A_IWL<465> A_IWL<464> A_IWL<463> A_IWL<462> A_IWL<461> A_IWL<460> A_IWL<459> A_IWL<458> A_IWL<457> A_IWL<456> A_IWL<455> A_IWL<454> A_IWL<453> A_IWL<452> A_IWL<451> A_IWL<450> A_IWL<449> A_IWL<448> A_IWL<447> A_IWL<446> A_IWL<445> A_IWL<444> A_IWL<443> A_IWL<442> A_IWL<441> A_IWL<440> A_IWL<439> A_IWL<438> A_IWL<437> A_IWL<436> A_IWL<435> A_IWL<434> A_IWL<433> A_IWL<432> A_IWL<431> A_IWL<430> A_IWL<429> A_IWL<428> A_IWL<427> A_IWL<426> A_IWL<425> A_IWL<424> A_IWL<423> A_IWL<422> A_IWL<421> A_IWL<420> A_IWL<419> A_IWL<418> A_IWL<417> A_IWL<416> A_IWL<415> A_IWL<414> A_IWL<413> A_IWL<412> A_IWL<411> A_IWL<410> A_IWL<409> A_IWL<408> A_IWL<407> A_IWL<406> A_IWL<405> A_IWL<404> A_IWL<403> A_IWL<402> A_IWL<401> A_IWL<400> A_IWL<399> A_IWL<398> A_IWL<397> A_IWL<396> A_IWL<395> A_IWL<394> A_IWL<393> A_IWL<392> A_IWL<391> A_IWL<390> A_IWL<389> A_IWL<388> A_IWL<387> A_IWL<386> A_IWL<385> A_IWL<384> A_IWL<639> A_IWL<638> A_IWL<637> A_IWL<636> A_IWL<635> A_IWL<634> A_IWL<633> A_IWL<632> A_IWL<631> A_IWL<630> A_IWL<629> A_IWL<628> A_IWL<627> A_IWL<626> A_IWL<625> A_IWL<624> A_IWL<623> A_IWL<622> A_IWL<621> A_IWL<620> A_IWL<619> A_IWL<618> A_IWL<617> A_IWL<616> A_IWL<615> A_IWL<614> A_IWL<613> A_IWL<612> A_IWL<611> A_IWL<610> A_IWL<609> A_IWL<608> A_IWL<607> A_IWL<606> A_IWL<605> A_IWL<604> A_IWL<603> A_IWL<602> A_IWL<601> A_IWL<600> A_IWL<599> A_IWL<598> A_IWL<597> A_IWL<596> A_IWL<595> A_IWL<594> A_IWL<593> A_IWL<592> A_IWL<591> A_IWL<590> A_IWL<589> A_IWL<588> A_IWL<587> A_IWL<586> A_IWL<585> A_IWL<584> A_IWL<583> A_IWL<582> A_IWL<581> A_IWL<580> A_IWL<579> A_IWL<578> A_IWL<577> A_IWL<576> A_IWL<575> A_IWL<574> A_IWL<573> A_IWL<572> A_IWL<571> A_IWL<570> A_IWL<569> A_IWL<568> A_IWL<567> A_IWL<566> A_IWL<565> A_IWL<564> A_IWL<563> A_IWL<562> A_IWL<561> A_IWL<560> A_IWL<559> A_IWL<558> A_IWL<557> A_IWL<556> A_IWL<555> A_IWL<554> A_IWL<553> A_IWL<552> A_IWL<551> A_IWL<550> A_IWL<549> A_IWL<548> A_IWL<547> A_IWL<546> A_IWL<545> A_IWL<544> A_IWL<543> A_IWL<542> A_IWL<541> A_IWL<540> A_IWL<539> A_IWL<538> A_IWL<537> A_IWL<536> A_IWL<535> A_IWL<534> A_IWL<533> A_IWL<532> A_IWL<531> A_IWL<530> A_IWL<529> A_IWL<528> A_IWL<527> A_IWL<526> A_IWL<525> A_IWL<524> A_IWL<523> A_IWL<522> A_IWL<521> A_IWL<520> A_IWL<519> A_IWL<518> A_IWL<517> A_IWL<516> A_IWL<515> A_IWL<514> A_IWL<513> A_IWL<512> B_BLC<9> B_BLC<8> B_BLC_TOP<9> B_BLC_TOP<8> B_BLT<9> B_BLT<8> B_BLT_TOP<9> B_BLT_TOP<8> B_IWL<511> B_IWL<510> B_IWL<509> B_IWL<508> B_IWL<507> B_IWL<506> B_IWL<505> B_IWL<504> B_IWL<503> B_IWL<502> B_IWL<501> B_IWL<500> B_IWL<499> B_IWL<498> B_IWL<497> B_IWL<496> B_IWL<495> B_IWL<494> B_IWL<493> B_IWL<492> B_IWL<491> B_IWL<490> B_IWL<489> B_IWL<488> B_IWL<487> B_IWL<486> B_IWL<485> B_IWL<484> B_IWL<483> B_IWL<482> B_IWL<481> B_IWL<480> B_IWL<479> B_IWL<478> B_IWL<477> B_IWL<476> B_IWL<475> B_IWL<474> B_IWL<473> B_IWL<472> B_IWL<471> B_IWL<470> B_IWL<469> B_IWL<468> B_IWL<467> B_IWL<466> B_IWL<465> B_IWL<464> B_IWL<463> B_IWL<462> B_IWL<461> B_IWL<460> B_IWL<459> B_IWL<458> B_IWL<457> B_IWL<456> B_IWL<455> B_IWL<454> B_IWL<453> B_IWL<452> B_IWL<451> B_IWL<450> B_IWL<449> B_IWL<448> B_IWL<447> B_IWL<446> B_IWL<445> B_IWL<444> B_IWL<443> B_IWL<442> B_IWL<441> B_IWL<440> B_IWL<439> B_IWL<438> B_IWL<437> B_IWL<436> B_IWL<435> B_IWL<434> B_IWL<433> B_IWL<432> B_IWL<431> B_IWL<430> B_IWL<429> B_IWL<428> B_IWL<427> B_IWL<426> B_IWL<425> B_IWL<424> B_IWL<423> B_IWL<422> B_IWL<421> B_IWL<420> B_IWL<419> B_IWL<418> B_IWL<417> B_IWL<416> B_IWL<415> B_IWL<414> B_IWL<413> B_IWL<412> B_IWL<411> B_IWL<410> B_IWL<409> B_IWL<408> B_IWL<407> B_IWL<406> B_IWL<405> B_IWL<404> B_IWL<403> B_IWL<402> B_IWL<401> B_IWL<400> B_IWL<399> B_IWL<398> B_IWL<397> B_IWL<396> B_IWL<395> B_IWL<394> B_IWL<393> B_IWL<392> B_IWL<391> B_IWL<390> B_IWL<389> B_IWL<388> B_IWL<387> B_IWL<386> B_IWL<385> B_IWL<384> B_IWL<639> B_IWL<638> B_IWL<637> B_IWL<636> B_IWL<635> B_IWL<634> B_IWL<633> B_IWL<632> B_IWL<631> B_IWL<630> B_IWL<629> B_IWL<628> B_IWL<627> B_IWL<626> B_IWL<625> B_IWL<624> B_IWL<623> B_IWL<622> B_IWL<621> B_IWL<620> B_IWL<619> B_IWL<618> B_IWL<617> B_IWL<616> B_IWL<615> B_IWL<614> B_IWL<613> B_IWL<612> B_IWL<611> B_IWL<610> B_IWL<609> B_IWL<608> B_IWL<607> B_IWL<606> B_IWL<605> B_IWL<604> B_IWL<603> B_IWL<602> B_IWL<601> B_IWL<600> B_IWL<599> B_IWL<598> B_IWL<597> B_IWL<596> B_IWL<595> B_IWL<594> B_IWL<593> B_IWL<592> B_IWL<591> B_IWL<590> B_IWL<589> B_IWL<588> B_IWL<587> B_IWL<586> B_IWL<585> B_IWL<584> B_IWL<583> B_IWL<582> B_IWL<581> B_IWL<580> B_IWL<579> B_IWL<578> B_IWL<577> B_IWL<576> B_IWL<575> B_IWL<574> B_IWL<573> B_IWL<572> B_IWL<571> B_IWL<570> B_IWL<569> B_IWL<568> B_IWL<567> B_IWL<566> B_IWL<565> B_IWL<564> B_IWL<563> B_IWL<562> B_IWL<561> B_IWL<560> B_IWL<559> B_IWL<558> B_IWL<557> B_IWL<556> B_IWL<555> B_IWL<554> B_IWL<553> B_IWL<552> B_IWL<551> B_IWL<550> B_IWL<549> B_IWL<548> B_IWL<547> B_IWL<546> B_IWL<545> B_IWL<544> B_IWL<543> B_IWL<542> B_IWL<541> B_IWL<540> B_IWL<539> B_IWL<538> B_IWL<537> B_IWL<536> B_IWL<535> B_IWL<534> B_IWL<533> B_IWL<532> B_IWL<531> B_IWL<530> B_IWL<529> B_IWL<528> B_IWL<527> B_IWL<526> B_IWL<525> B_IWL<524> B_IWL<523> B_IWL<522> B_IWL<521> B_IWL<520> B_IWL<519> B_IWL<518> B_IWL<517> B_IWL<516> B_IWL<515> B_IWL<514> B_IWL<513> B_IWL<512> VDD_CORE VSS / RM_IHPSG13_512x32_c2_2P_COLUMN_pcell_0 +XCOL<3> A_BLC<7> A_BLC<6> A_BLC_TOP<7> A_BLC_TOP<6> A_BLT<7> A_BLT<6> A_BLT_TOP<7> A_BLT_TOP<6> A_IWL<383> A_IWL<382> A_IWL<381> A_IWL<380> A_IWL<379> A_IWL<378> A_IWL<377> A_IWL<376> A_IWL<375> A_IWL<374> A_IWL<373> A_IWL<372> A_IWL<371> A_IWL<370> A_IWL<369> A_IWL<368> A_IWL<367> A_IWL<366> A_IWL<365> A_IWL<364> A_IWL<363> A_IWL<362> A_IWL<361> A_IWL<360> A_IWL<359> A_IWL<358> A_IWL<357> A_IWL<356> A_IWL<355> A_IWL<354> A_IWL<353> A_IWL<352> A_IWL<351> A_IWL<350> A_IWL<349> A_IWL<348> A_IWL<347> A_IWL<346> A_IWL<345> A_IWL<344> A_IWL<343> A_IWL<342> A_IWL<341> A_IWL<340> A_IWL<339> A_IWL<338> A_IWL<337> A_IWL<336> A_IWL<335> A_IWL<334> A_IWL<333> A_IWL<332> A_IWL<331> A_IWL<330> A_IWL<329> A_IWL<328> A_IWL<327> A_IWL<326> A_IWL<325> A_IWL<324> A_IWL<323> A_IWL<322> A_IWL<321> A_IWL<320> A_IWL<319> A_IWL<318> A_IWL<317> A_IWL<316> A_IWL<315> A_IWL<314> A_IWL<313> A_IWL<312> A_IWL<311> A_IWL<310> A_IWL<309> A_IWL<308> A_IWL<307> A_IWL<306> A_IWL<305> A_IWL<304> A_IWL<303> A_IWL<302> A_IWL<301> A_IWL<300> A_IWL<299> A_IWL<298> A_IWL<297> A_IWL<296> A_IWL<295> A_IWL<294> A_IWL<293> A_IWL<292> A_IWL<291> A_IWL<290> A_IWL<289> A_IWL<288> A_IWL<287> A_IWL<286> A_IWL<285> A_IWL<284> A_IWL<283> A_IWL<282> A_IWL<281> A_IWL<280> A_IWL<279> A_IWL<278> A_IWL<277> A_IWL<276> A_IWL<275> A_IWL<274> A_IWL<273> A_IWL<272> A_IWL<271> A_IWL<270> A_IWL<269> A_IWL<268> A_IWL<267> A_IWL<266> A_IWL<265> A_IWL<264> A_IWL<263> A_IWL<262> A_IWL<261> A_IWL<260> A_IWL<259> A_IWL<258> A_IWL<257> A_IWL<256> A_IWL<511> A_IWL<510> A_IWL<509> A_IWL<508> A_IWL<507> A_IWL<506> A_IWL<505> A_IWL<504> A_IWL<503> A_IWL<502> A_IWL<501> A_IWL<500> A_IWL<499> A_IWL<498> A_IWL<497> A_IWL<496> A_IWL<495> A_IWL<494> A_IWL<493> A_IWL<492> A_IWL<491> A_IWL<490> A_IWL<489> A_IWL<488> A_IWL<487> A_IWL<486> A_IWL<485> A_IWL<484> A_IWL<483> A_IWL<482> A_IWL<481> A_IWL<480> A_IWL<479> A_IWL<478> A_IWL<477> A_IWL<476> A_IWL<475> A_IWL<474> A_IWL<473> A_IWL<472> A_IWL<471> A_IWL<470> A_IWL<469> A_IWL<468> A_IWL<467> A_IWL<466> A_IWL<465> A_IWL<464> A_IWL<463> A_IWL<462> A_IWL<461> A_IWL<460> A_IWL<459> A_IWL<458> A_IWL<457> A_IWL<456> A_IWL<455> A_IWL<454> A_IWL<453> A_IWL<452> A_IWL<451> A_IWL<450> A_IWL<449> A_IWL<448> A_IWL<447> A_IWL<446> A_IWL<445> A_IWL<444> A_IWL<443> A_IWL<442> A_IWL<441> A_IWL<440> A_IWL<439> A_IWL<438> A_IWL<437> A_IWL<436> A_IWL<435> A_IWL<434> A_IWL<433> A_IWL<432> A_IWL<431> A_IWL<430> A_IWL<429> A_IWL<428> A_IWL<427> A_IWL<426> A_IWL<425> A_IWL<424> A_IWL<423> A_IWL<422> A_IWL<421> A_IWL<420> A_IWL<419> A_IWL<418> A_IWL<417> A_IWL<416> A_IWL<415> A_IWL<414> A_IWL<413> A_IWL<412> A_IWL<411> A_IWL<410> A_IWL<409> A_IWL<408> A_IWL<407> A_IWL<406> A_IWL<405> A_IWL<404> A_IWL<403> A_IWL<402> A_IWL<401> A_IWL<400> A_IWL<399> A_IWL<398> A_IWL<397> A_IWL<396> A_IWL<395> A_IWL<394> A_IWL<393> A_IWL<392> A_IWL<391> A_IWL<390> A_IWL<389> A_IWL<388> A_IWL<387> A_IWL<386> A_IWL<385> A_IWL<384> B_BLC<7> B_BLC<6> B_BLC_TOP<7> B_BLC_TOP<6> B_BLT<7> B_BLT<6> B_BLT_TOP<7> B_BLT_TOP<6> B_IWL<383> B_IWL<382> B_IWL<381> B_IWL<380> B_IWL<379> B_IWL<378> B_IWL<377> B_IWL<376> B_IWL<375> B_IWL<374> B_IWL<373> B_IWL<372> B_IWL<371> B_IWL<370> B_IWL<369> B_IWL<368> B_IWL<367> B_IWL<366> B_IWL<365> B_IWL<364> B_IWL<363> B_IWL<362> B_IWL<361> B_IWL<360> B_IWL<359> B_IWL<358> B_IWL<357> B_IWL<356> B_IWL<355> B_IWL<354> B_IWL<353> B_IWL<352> B_IWL<351> B_IWL<350> B_IWL<349> B_IWL<348> B_IWL<347> B_IWL<346> B_IWL<345> B_IWL<344> B_IWL<343> B_IWL<342> B_IWL<341> B_IWL<340> B_IWL<339> B_IWL<338> B_IWL<337> B_IWL<336> B_IWL<335> B_IWL<334> B_IWL<333> B_IWL<332> B_IWL<331> B_IWL<330> B_IWL<329> B_IWL<328> B_IWL<327> B_IWL<326> B_IWL<325> B_IWL<324> B_IWL<323> B_IWL<322> B_IWL<321> B_IWL<320> B_IWL<319> B_IWL<318> B_IWL<317> B_IWL<316> B_IWL<315> B_IWL<314> B_IWL<313> B_IWL<312> B_IWL<311> B_IWL<310> B_IWL<309> B_IWL<308> B_IWL<307> B_IWL<306> B_IWL<305> B_IWL<304> B_IWL<303> B_IWL<302> B_IWL<301> B_IWL<300> B_IWL<299> B_IWL<298> B_IWL<297> B_IWL<296> B_IWL<295> B_IWL<294> B_IWL<293> B_IWL<292> B_IWL<291> B_IWL<290> B_IWL<289> B_IWL<288> B_IWL<287> B_IWL<286> B_IWL<285> B_IWL<284> B_IWL<283> B_IWL<282> B_IWL<281> B_IWL<280> B_IWL<279> B_IWL<278> B_IWL<277> B_IWL<276> B_IWL<275> B_IWL<274> B_IWL<273> B_IWL<272> B_IWL<271> B_IWL<270> B_IWL<269> B_IWL<268> B_IWL<267> B_IWL<266> B_IWL<265> B_IWL<264> B_IWL<263> B_IWL<262> B_IWL<261> B_IWL<260> B_IWL<259> B_IWL<258> B_IWL<257> B_IWL<256> B_IWL<511> B_IWL<510> B_IWL<509> B_IWL<508> B_IWL<507> B_IWL<506> B_IWL<505> B_IWL<504> B_IWL<503> B_IWL<502> B_IWL<501> B_IWL<500> B_IWL<499> B_IWL<498> B_IWL<497> B_IWL<496> B_IWL<495> B_IWL<494> B_IWL<493> B_IWL<492> B_IWL<491> B_IWL<490> B_IWL<489> B_IWL<488> B_IWL<487> B_IWL<486> B_IWL<485> B_IWL<484> B_IWL<483> B_IWL<482> B_IWL<481> B_IWL<480> B_IWL<479> B_IWL<478> B_IWL<477> B_IWL<476> B_IWL<475> B_IWL<474> B_IWL<473> B_IWL<472> B_IWL<471> B_IWL<470> B_IWL<469> B_IWL<468> B_IWL<467> B_IWL<466> B_IWL<465> B_IWL<464> B_IWL<463> B_IWL<462> B_IWL<461> B_IWL<460> B_IWL<459> B_IWL<458> B_IWL<457> B_IWL<456> B_IWL<455> B_IWL<454> B_IWL<453> B_IWL<452> B_IWL<451> B_IWL<450> B_IWL<449> B_IWL<448> B_IWL<447> B_IWL<446> B_IWL<445> B_IWL<444> B_IWL<443> B_IWL<442> B_IWL<441> B_IWL<440> B_IWL<439> B_IWL<438> B_IWL<437> B_IWL<436> B_IWL<435> B_IWL<434> B_IWL<433> B_IWL<432> B_IWL<431> B_IWL<430> B_IWL<429> B_IWL<428> B_IWL<427> B_IWL<426> B_IWL<425> B_IWL<424> B_IWL<423> B_IWL<422> B_IWL<421> B_IWL<420> B_IWL<419> B_IWL<418> B_IWL<417> B_IWL<416> B_IWL<415> B_IWL<414> B_IWL<413> B_IWL<412> B_IWL<411> B_IWL<410> B_IWL<409> B_IWL<408> B_IWL<407> B_IWL<406> B_IWL<405> B_IWL<404> B_IWL<403> B_IWL<402> B_IWL<401> B_IWL<400> B_IWL<399> B_IWL<398> B_IWL<397> B_IWL<396> B_IWL<395> B_IWL<394> B_IWL<393> B_IWL<392> B_IWL<391> B_IWL<390> B_IWL<389> B_IWL<388> B_IWL<387> B_IWL<386> B_IWL<385> B_IWL<384> VDD_CORE VSS / RM_IHPSG13_512x32_c2_2P_COLUMN_pcell_0 +XCOL<2> A_BLC<5> A_BLC<4> A_BLC_TOP<5> A_BLC_TOP<4> A_BLT<5> A_BLT<4> A_BLT_TOP<5> A_BLT_TOP<4> A_IWL<255> A_IWL<254> A_IWL<253> A_IWL<252> A_IWL<251> A_IWL<250> A_IWL<249> A_IWL<248> A_IWL<247> A_IWL<246> A_IWL<245> A_IWL<244> A_IWL<243> A_IWL<242> A_IWL<241> A_IWL<240> A_IWL<239> A_IWL<238> A_IWL<237> A_IWL<236> A_IWL<235> A_IWL<234> A_IWL<233> A_IWL<232> A_IWL<231> A_IWL<230> A_IWL<229> A_IWL<228> A_IWL<227> A_IWL<226> A_IWL<225> A_IWL<224> A_IWL<223> A_IWL<222> A_IWL<221> A_IWL<220> A_IWL<219> A_IWL<218> A_IWL<217> A_IWL<216> A_IWL<215> A_IWL<214> A_IWL<213> A_IWL<212> A_IWL<211> A_IWL<210> A_IWL<209> A_IWL<208> A_IWL<207> A_IWL<206> A_IWL<205> A_IWL<204> A_IWL<203> A_IWL<202> A_IWL<201> A_IWL<200> A_IWL<199> A_IWL<198> A_IWL<197> A_IWL<196> A_IWL<195> A_IWL<194> A_IWL<193> A_IWL<192> A_IWL<191> A_IWL<190> A_IWL<189> A_IWL<188> A_IWL<187> A_IWL<186> A_IWL<185> A_IWL<184> A_IWL<183> A_IWL<182> A_IWL<181> A_IWL<180> A_IWL<179> A_IWL<178> A_IWL<177> A_IWL<176> A_IWL<175> A_IWL<174> A_IWL<173> A_IWL<172> A_IWL<171> A_IWL<170> A_IWL<169> A_IWL<168> A_IWL<167> A_IWL<166> A_IWL<165> A_IWL<164> A_IWL<163> A_IWL<162> A_IWL<161> A_IWL<160> A_IWL<159> A_IWL<158> A_IWL<157> A_IWL<156> A_IWL<155> A_IWL<154> A_IWL<153> A_IWL<152> A_IWL<151> A_IWL<150> A_IWL<149> A_IWL<148> A_IWL<147> A_IWL<146> A_IWL<145> A_IWL<144> A_IWL<143> A_IWL<142> A_IWL<141> A_IWL<140> A_IWL<139> A_IWL<138> A_IWL<137> A_IWL<136> A_IWL<135> A_IWL<134> A_IWL<133> A_IWL<132> A_IWL<131> A_IWL<130> A_IWL<129> A_IWL<128> A_IWL<383> A_IWL<382> A_IWL<381> A_IWL<380> A_IWL<379> A_IWL<378> A_IWL<377> A_IWL<376> A_IWL<375> A_IWL<374> A_IWL<373> A_IWL<372> A_IWL<371> A_IWL<370> A_IWL<369> A_IWL<368> A_IWL<367> A_IWL<366> A_IWL<365> A_IWL<364> A_IWL<363> A_IWL<362> A_IWL<361> A_IWL<360> A_IWL<359> A_IWL<358> A_IWL<357> A_IWL<356> A_IWL<355> A_IWL<354> A_IWL<353> A_IWL<352> A_IWL<351> A_IWL<350> A_IWL<349> A_IWL<348> A_IWL<347> A_IWL<346> A_IWL<345> A_IWL<344> A_IWL<343> A_IWL<342> A_IWL<341> A_IWL<340> A_IWL<339> A_IWL<338> A_IWL<337> A_IWL<336> A_IWL<335> A_IWL<334> A_IWL<333> A_IWL<332> A_IWL<331> A_IWL<330> A_IWL<329> A_IWL<328> A_IWL<327> A_IWL<326> A_IWL<325> A_IWL<324> A_IWL<323> A_IWL<322> A_IWL<321> A_IWL<320> A_IWL<319> A_IWL<318> A_IWL<317> A_IWL<316> A_IWL<315> A_IWL<314> A_IWL<313> A_IWL<312> A_IWL<311> A_IWL<310> A_IWL<309> A_IWL<308> A_IWL<307> A_IWL<306> A_IWL<305> A_IWL<304> A_IWL<303> A_IWL<302> A_IWL<301> A_IWL<300> A_IWL<299> A_IWL<298> A_IWL<297> A_IWL<296> A_IWL<295> A_IWL<294> A_IWL<293> A_IWL<292> A_IWL<291> A_IWL<290> A_IWL<289> A_IWL<288> A_IWL<287> A_IWL<286> A_IWL<285> A_IWL<284> A_IWL<283> A_IWL<282> A_IWL<281> A_IWL<280> A_IWL<279> A_IWL<278> A_IWL<277> A_IWL<276> A_IWL<275> A_IWL<274> A_IWL<273> A_IWL<272> A_IWL<271> A_IWL<270> A_IWL<269> A_IWL<268> A_IWL<267> A_IWL<266> A_IWL<265> A_IWL<264> A_IWL<263> A_IWL<262> A_IWL<261> A_IWL<260> A_IWL<259> A_IWL<258> A_IWL<257> A_IWL<256> B_BLC<5> B_BLC<4> B_BLC_TOP<5> B_BLC_TOP<4> B_BLT<5> B_BLT<4> B_BLT_TOP<5> B_BLT_TOP<4> B_IWL<255> B_IWL<254> B_IWL<253> B_IWL<252> B_IWL<251> B_IWL<250> B_IWL<249> B_IWL<248> B_IWL<247> B_IWL<246> B_IWL<245> B_IWL<244> B_IWL<243> B_IWL<242> B_IWL<241> B_IWL<240> B_IWL<239> B_IWL<238> B_IWL<237> B_IWL<236> B_IWL<235> B_IWL<234> B_IWL<233> B_IWL<232> B_IWL<231> B_IWL<230> B_IWL<229> B_IWL<228> B_IWL<227> B_IWL<226> B_IWL<225> B_IWL<224> B_IWL<223> B_IWL<222> B_IWL<221> B_IWL<220> B_IWL<219> B_IWL<218> B_IWL<217> B_IWL<216> B_IWL<215> B_IWL<214> B_IWL<213> B_IWL<212> B_IWL<211> B_IWL<210> B_IWL<209> B_IWL<208> B_IWL<207> B_IWL<206> B_IWL<205> B_IWL<204> B_IWL<203> B_IWL<202> B_IWL<201> B_IWL<200> B_IWL<199> B_IWL<198> B_IWL<197> B_IWL<196> B_IWL<195> B_IWL<194> B_IWL<193> B_IWL<192> B_IWL<191> B_IWL<190> B_IWL<189> B_IWL<188> B_IWL<187> B_IWL<186> B_IWL<185> B_IWL<184> B_IWL<183> B_IWL<182> B_IWL<181> B_IWL<180> B_IWL<179> B_IWL<178> B_IWL<177> B_IWL<176> B_IWL<175> B_IWL<174> B_IWL<173> B_IWL<172> B_IWL<171> B_IWL<170> B_IWL<169> B_IWL<168> B_IWL<167> B_IWL<166> B_IWL<165> B_IWL<164> B_IWL<163> B_IWL<162> B_IWL<161> B_IWL<160> B_IWL<159> B_IWL<158> B_IWL<157> B_IWL<156> B_IWL<155> B_IWL<154> B_IWL<153> B_IWL<152> B_IWL<151> B_IWL<150> B_IWL<149> B_IWL<148> B_IWL<147> B_IWL<146> B_IWL<145> B_IWL<144> B_IWL<143> B_IWL<142> B_IWL<141> B_IWL<140> B_IWL<139> B_IWL<138> B_IWL<137> B_IWL<136> B_IWL<135> B_IWL<134> B_IWL<133> B_IWL<132> B_IWL<131> B_IWL<130> B_IWL<129> B_IWL<128> B_IWL<383> B_IWL<382> B_IWL<381> B_IWL<380> B_IWL<379> B_IWL<378> B_IWL<377> B_IWL<376> B_IWL<375> B_IWL<374> B_IWL<373> B_IWL<372> B_IWL<371> B_IWL<370> B_IWL<369> B_IWL<368> B_IWL<367> B_IWL<366> B_IWL<365> B_IWL<364> B_IWL<363> B_IWL<362> B_IWL<361> B_IWL<360> B_IWL<359> B_IWL<358> B_IWL<357> B_IWL<356> B_IWL<355> B_IWL<354> B_IWL<353> B_IWL<352> B_IWL<351> B_IWL<350> B_IWL<349> B_IWL<348> B_IWL<347> B_IWL<346> B_IWL<345> B_IWL<344> B_IWL<343> B_IWL<342> B_IWL<341> B_IWL<340> B_IWL<339> B_IWL<338> B_IWL<337> B_IWL<336> B_IWL<335> B_IWL<334> B_IWL<333> B_IWL<332> B_IWL<331> B_IWL<330> B_IWL<329> B_IWL<328> B_IWL<327> B_IWL<326> B_IWL<325> B_IWL<324> B_IWL<323> B_IWL<322> B_IWL<321> B_IWL<320> B_IWL<319> B_IWL<318> B_IWL<317> B_IWL<316> B_IWL<315> B_IWL<314> B_IWL<313> B_IWL<312> B_IWL<311> B_IWL<310> B_IWL<309> B_IWL<308> B_IWL<307> B_IWL<306> B_IWL<305> B_IWL<304> B_IWL<303> B_IWL<302> B_IWL<301> B_IWL<300> B_IWL<299> B_IWL<298> B_IWL<297> B_IWL<296> B_IWL<295> B_IWL<294> B_IWL<293> B_IWL<292> B_IWL<291> B_IWL<290> B_IWL<289> B_IWL<288> B_IWL<287> B_IWL<286> B_IWL<285> B_IWL<284> B_IWL<283> B_IWL<282> B_IWL<281> B_IWL<280> B_IWL<279> B_IWL<278> B_IWL<277> B_IWL<276> B_IWL<275> B_IWL<274> B_IWL<273> B_IWL<272> B_IWL<271> B_IWL<270> B_IWL<269> B_IWL<268> B_IWL<267> B_IWL<266> B_IWL<265> B_IWL<264> B_IWL<263> B_IWL<262> B_IWL<261> B_IWL<260> B_IWL<259> B_IWL<258> B_IWL<257> B_IWL<256> VDD_CORE VSS / RM_IHPSG13_512x32_c2_2P_COLUMN_pcell_0 +XCOL<1> A_BLC<3> A_BLC<2> A_BLC_TOP<3> A_BLC_TOP<2> A_BLT<3> A_BLT<2> A_BLT_TOP<3> A_BLT_TOP<2> A_IWL<127> A_IWL<126> A_IWL<125> A_IWL<124> A_IWL<123> A_IWL<122> A_IWL<121> A_IWL<120> A_IWL<119> A_IWL<118> A_IWL<117> A_IWL<116> A_IWL<115> A_IWL<114> A_IWL<113> A_IWL<112> A_IWL<111> A_IWL<110> A_IWL<109> A_IWL<108> A_IWL<107> A_IWL<106> A_IWL<105> A_IWL<104> A_IWL<103> A_IWL<102> A_IWL<101> A_IWL<100> A_IWL<99> A_IWL<98> A_IWL<97> A_IWL<96> A_IWL<95> A_IWL<94> A_IWL<93> A_IWL<92> A_IWL<91> A_IWL<90> A_IWL<89> A_IWL<88> A_IWL<87> A_IWL<86> A_IWL<85> A_IWL<84> A_IWL<83> A_IWL<82> A_IWL<81> A_IWL<80> A_IWL<79> A_IWL<78> A_IWL<77> A_IWL<76> A_IWL<75> A_IWL<74> A_IWL<73> A_IWL<72> A_IWL<71> A_IWL<70> A_IWL<69> A_IWL<68> A_IWL<67> A_IWL<66> A_IWL<65> A_IWL<64> A_IWL<63> A_IWL<62> A_IWL<61> A_IWL<60> A_IWL<59> A_IWL<58> A_IWL<57> A_IWL<56> A_IWL<55> A_IWL<54> A_IWL<53> A_IWL<52> A_IWL<51> A_IWL<50> A_IWL<49> A_IWL<48> A_IWL<47> A_IWL<46> A_IWL<45> A_IWL<44> A_IWL<43> A_IWL<42> A_IWL<41> A_IWL<40> A_IWL<39> A_IWL<38> A_IWL<37> A_IWL<36> A_IWL<35> A_IWL<34> A_IWL<33> A_IWL<32> A_IWL<31> A_IWL<30> A_IWL<29> A_IWL<28> A_IWL<27> A_IWL<26> A_IWL<25> A_IWL<24> A_IWL<23> A_IWL<22> A_IWL<21> A_IWL<20> A_IWL<19> A_IWL<18> A_IWL<17> A_IWL<16> A_IWL<15> A_IWL<14> A_IWL<13> A_IWL<12> A_IWL<11> A_IWL<10> A_IWL<9> A_IWL<8> A_IWL<7> A_IWL<6> A_IWL<5> A_IWL<4> A_IWL<3> A_IWL<2> A_IWL<1> A_IWL<0> A_IWL<255> A_IWL<254> A_IWL<253> A_IWL<252> A_IWL<251> A_IWL<250> A_IWL<249> A_IWL<248> A_IWL<247> A_IWL<246> A_IWL<245> A_IWL<244> A_IWL<243> A_IWL<242> A_IWL<241> A_IWL<240> A_IWL<239> A_IWL<238> A_IWL<237> A_IWL<236> A_IWL<235> A_IWL<234> A_IWL<233> A_IWL<232> A_IWL<231> A_IWL<230> A_IWL<229> A_IWL<228> A_IWL<227> A_IWL<226> A_IWL<225> A_IWL<224> A_IWL<223> A_IWL<222> A_IWL<221> A_IWL<220> A_IWL<219> A_IWL<218> A_IWL<217> A_IWL<216> A_IWL<215> A_IWL<214> A_IWL<213> A_IWL<212> A_IWL<211> A_IWL<210> A_IWL<209> A_IWL<208> A_IWL<207> A_IWL<206> A_IWL<205> A_IWL<204> A_IWL<203> A_IWL<202> A_IWL<201> A_IWL<200> A_IWL<199> A_IWL<198> A_IWL<197> A_IWL<196> A_IWL<195> A_IWL<194> A_IWL<193> A_IWL<192> A_IWL<191> A_IWL<190> A_IWL<189> A_IWL<188> A_IWL<187> A_IWL<186> A_IWL<185> A_IWL<184> A_IWL<183> A_IWL<182> A_IWL<181> A_IWL<180> A_IWL<179> A_IWL<178> A_IWL<177> A_IWL<176> A_IWL<175> A_IWL<174> A_IWL<173> A_IWL<172> A_IWL<171> A_IWL<170> A_IWL<169> A_IWL<168> A_IWL<167> A_IWL<166> A_IWL<165> A_IWL<164> A_IWL<163> A_IWL<162> A_IWL<161> A_IWL<160> A_IWL<159> A_IWL<158> A_IWL<157> A_IWL<156> A_IWL<155> A_IWL<154> A_IWL<153> A_IWL<152> A_IWL<151> A_IWL<150> A_IWL<149> A_IWL<148> A_IWL<147> A_IWL<146> A_IWL<145> A_IWL<144> A_IWL<143> A_IWL<142> A_IWL<141> A_IWL<140> A_IWL<139> A_IWL<138> A_IWL<137> A_IWL<136> A_IWL<135> A_IWL<134> A_IWL<133> A_IWL<132> A_IWL<131> A_IWL<130> A_IWL<129> A_IWL<128> B_BLC<3> B_BLC<2> B_BLC_TOP<3> B_BLC_TOP<2> B_BLT<3> B_BLT<2> B_BLT_TOP<3> B_BLT_TOP<2> B_IWL<127> B_IWL<126> B_IWL<125> B_IWL<124> B_IWL<123> B_IWL<122> B_IWL<121> B_IWL<120> B_IWL<119> B_IWL<118> B_IWL<117> B_IWL<116> B_IWL<115> B_IWL<114> B_IWL<113> B_IWL<112> B_IWL<111> B_IWL<110> B_IWL<109> B_IWL<108> B_IWL<107> B_IWL<106> B_IWL<105> B_IWL<104> B_IWL<103> B_IWL<102> B_IWL<101> B_IWL<100> B_IWL<99> B_IWL<98> B_IWL<97> B_IWL<96> B_IWL<95> B_IWL<94> B_IWL<93> B_IWL<92> B_IWL<91> B_IWL<90> B_IWL<89> B_IWL<88> B_IWL<87> B_IWL<86> B_IWL<85> B_IWL<84> B_IWL<83> B_IWL<82> B_IWL<81> B_IWL<80> B_IWL<79> B_IWL<78> B_IWL<77> B_IWL<76> B_IWL<75> B_IWL<74> B_IWL<73> B_IWL<72> B_IWL<71> B_IWL<70> B_IWL<69> B_IWL<68> B_IWL<67> B_IWL<66> B_IWL<65> B_IWL<64> B_IWL<63> B_IWL<62> B_IWL<61> B_IWL<60> B_IWL<59> B_IWL<58> B_IWL<57> B_IWL<56> B_IWL<55> B_IWL<54> B_IWL<53> B_IWL<52> B_IWL<51> B_IWL<50> B_IWL<49> B_IWL<48> B_IWL<47> B_IWL<46> B_IWL<45> B_IWL<44> B_IWL<43> B_IWL<42> B_IWL<41> B_IWL<40> B_IWL<39> B_IWL<38> B_IWL<37> B_IWL<36> B_IWL<35> B_IWL<34> B_IWL<33> B_IWL<32> B_IWL<31> B_IWL<30> B_IWL<29> B_IWL<28> B_IWL<27> B_IWL<26> B_IWL<25> B_IWL<24> B_IWL<23> B_IWL<22> B_IWL<21> B_IWL<20> B_IWL<19> B_IWL<18> B_IWL<17> B_IWL<16> B_IWL<15> B_IWL<14> B_IWL<13> B_IWL<12> B_IWL<11> B_IWL<10> B_IWL<9> B_IWL<8> B_IWL<7> B_IWL<6> B_IWL<5> B_IWL<4> B_IWL<3> B_IWL<2> B_IWL<1> B_IWL<0> B_IWL<255> B_IWL<254> B_IWL<253> B_IWL<252> B_IWL<251> B_IWL<250> B_IWL<249> B_IWL<248> B_IWL<247> B_IWL<246> B_IWL<245> B_IWL<244> B_IWL<243> B_IWL<242> B_IWL<241> B_IWL<240> B_IWL<239> B_IWL<238> B_IWL<237> B_IWL<236> B_IWL<235> B_IWL<234> B_IWL<233> B_IWL<232> B_IWL<231> B_IWL<230> B_IWL<229> B_IWL<228> B_IWL<227> B_IWL<226> B_IWL<225> B_IWL<224> B_IWL<223> B_IWL<222> B_IWL<221> B_IWL<220> B_IWL<219> B_IWL<218> B_IWL<217> B_IWL<216> B_IWL<215> B_IWL<214> B_IWL<213> B_IWL<212> B_IWL<211> B_IWL<210> B_IWL<209> B_IWL<208> B_IWL<207> B_IWL<206> B_IWL<205> B_IWL<204> B_IWL<203> B_IWL<202> B_IWL<201> B_IWL<200> B_IWL<199> B_IWL<198> B_IWL<197> B_IWL<196> B_IWL<195> B_IWL<194> B_IWL<193> B_IWL<192> B_IWL<191> B_IWL<190> B_IWL<189> B_IWL<188> B_IWL<187> B_IWL<186> B_IWL<185> B_IWL<184> B_IWL<183> B_IWL<182> B_IWL<181> B_IWL<180> B_IWL<179> B_IWL<178> B_IWL<177> B_IWL<176> B_IWL<175> B_IWL<174> B_IWL<173> B_IWL<172> B_IWL<171> B_IWL<170> B_IWL<169> B_IWL<168> B_IWL<167> B_IWL<166> B_IWL<165> B_IWL<164> B_IWL<163> B_IWL<162> B_IWL<161> B_IWL<160> B_IWL<159> B_IWL<158> B_IWL<157> B_IWL<156> B_IWL<155> B_IWL<154> B_IWL<153> B_IWL<152> B_IWL<151> B_IWL<150> B_IWL<149> B_IWL<148> B_IWL<147> B_IWL<146> B_IWL<145> B_IWL<144> B_IWL<143> B_IWL<142> B_IWL<141> B_IWL<140> B_IWL<139> B_IWL<138> B_IWL<137> B_IWL<136> B_IWL<135> B_IWL<134> B_IWL<133> B_IWL<132> B_IWL<131> B_IWL<130> B_IWL<129> B_IWL<128> VDD_CORE VSS / RM_IHPSG13_512x32_c2_2P_COLUMN_pcell_0 +XCOL<0> A_BLC<1> A_BLC<0> A_BLC_TOP<1> A_BLC_TOP<0> A_BLT<1> A_BLT<0> A_BLT_TOP<1> A_BLT_TOP<0> A_WL<127> A_WL<126> A_WL<125> A_WL<124> A_WL<123> A_WL<122> A_WL<121> A_WL<120> A_WL<119> A_WL<118> A_WL<117> A_WL<116> A_WL<115> A_WL<114> A_WL<113> A_WL<112> A_WL<111> A_WL<110> A_WL<109> A_WL<108> A_WL<107> A_WL<106> A_WL<105> A_WL<104> A_WL<103> A_WL<102> A_WL<101> A_WL<100> A_WL<99> A_WL<98> A_WL<97> A_WL<96> A_WL<95> A_WL<94> A_WL<93> A_WL<92> A_WL<91> A_WL<90> A_WL<89> A_WL<88> A_WL<87> A_WL<86> A_WL<85> A_WL<84> A_WL<83> A_WL<82> A_WL<81> A_WL<80> A_WL<79> A_WL<78> A_WL<77> A_WL<76> A_WL<75> A_WL<74> A_WL<73> A_WL<72> A_WL<71> A_WL<70> A_WL<69> A_WL<68> A_WL<67> A_WL<66> A_WL<65> A_WL<64> A_WL<63> A_WL<62> A_WL<61> A_WL<60> A_WL<59> A_WL<58> A_WL<57> A_WL<56> A_WL<55> A_WL<54> A_WL<53> A_WL<52> A_WL<51> A_WL<50> A_WL<49> A_WL<48> A_WL<47> A_WL<46> A_WL<45> A_WL<44> A_WL<43> A_WL<42> A_WL<41> A_WL<40> A_WL<39> A_WL<38> A_WL<37> A_WL<36> A_WL<35> A_WL<34> A_WL<33> A_WL<32> A_WL<31> A_WL<30> A_WL<29> A_WL<28> A_WL<27> A_WL<26> A_WL<25> A_WL<24> A_WL<23> A_WL<22> A_WL<21> A_WL<20> A_WL<19> A_WL<18> A_WL<17> A_WL<16> A_WL<15> A_WL<14> A_WL<13> A_WL<12> A_WL<11> A_WL<10> A_WL<9> A_WL<8> A_WL<7> A_WL<6> A_WL<5> A_WL<4> A_WL<3> A_WL<2> A_WL<1> A_WL<0> A_IWL<127> A_IWL<126> A_IWL<125> A_IWL<124> A_IWL<123> A_IWL<122> A_IWL<121> A_IWL<120> A_IWL<119> A_IWL<118> A_IWL<117> A_IWL<116> A_IWL<115> A_IWL<114> A_IWL<113> A_IWL<112> A_IWL<111> A_IWL<110> A_IWL<109> A_IWL<108> A_IWL<107> A_IWL<106> A_IWL<105> A_IWL<104> A_IWL<103> A_IWL<102> A_IWL<101> A_IWL<100> A_IWL<99> A_IWL<98> A_IWL<97> A_IWL<96> A_IWL<95> A_IWL<94> A_IWL<93> A_IWL<92> A_IWL<91> A_IWL<90> A_IWL<89> A_IWL<88> A_IWL<87> A_IWL<86> A_IWL<85> A_IWL<84> A_IWL<83> A_IWL<82> A_IWL<81> A_IWL<80> A_IWL<79> A_IWL<78> A_IWL<77> A_IWL<76> A_IWL<75> A_IWL<74> A_IWL<73> A_IWL<72> A_IWL<71> A_IWL<70> A_IWL<69> A_IWL<68> A_IWL<67> A_IWL<66> A_IWL<65> A_IWL<64> A_IWL<63> A_IWL<62> A_IWL<61> A_IWL<60> A_IWL<59> A_IWL<58> A_IWL<57> A_IWL<56> A_IWL<55> A_IWL<54> A_IWL<53> A_IWL<52> A_IWL<51> A_IWL<50> A_IWL<49> A_IWL<48> A_IWL<47> A_IWL<46> A_IWL<45> A_IWL<44> A_IWL<43> A_IWL<42> A_IWL<41> A_IWL<40> A_IWL<39> A_IWL<38> A_IWL<37> A_IWL<36> A_IWL<35> A_IWL<34> A_IWL<33> A_IWL<32> A_IWL<31> A_IWL<30> A_IWL<29> A_IWL<28> A_IWL<27> A_IWL<26> A_IWL<25> A_IWL<24> A_IWL<23> A_IWL<22> A_IWL<21> A_IWL<20> A_IWL<19> A_IWL<18> A_IWL<17> A_IWL<16> A_IWL<15> A_IWL<14> A_IWL<13> A_IWL<12> A_IWL<11> A_IWL<10> A_IWL<9> A_IWL<8> A_IWL<7> A_IWL<6> A_IWL<5> A_IWL<4> A_IWL<3> A_IWL<2> A_IWL<1> A_IWL<0> B_BLC<1> B_BLC<0> B_BLC_TOP<1> B_BLC_TOP<0> B_BLT<1> B_BLT<0> B_BLT_TOP<1> B_BLT_TOP<0> B_WL<127> B_WL<126> B_WL<125> B_WL<124> B_WL<123> B_WL<122> B_WL<121> B_WL<120> B_WL<119> B_WL<118> B_WL<117> B_WL<116> B_WL<115> B_WL<114> B_WL<113> B_WL<112> B_WL<111> B_WL<110> B_WL<109> B_WL<108> B_WL<107> B_WL<106> B_WL<105> B_WL<104> B_WL<103> B_WL<102> B_WL<101> B_WL<100> B_WL<99> B_WL<98> B_WL<97> B_WL<96> B_WL<95> B_WL<94> B_WL<93> B_WL<92> B_WL<91> B_WL<90> B_WL<89> B_WL<88> B_WL<87> B_WL<86> B_WL<85> B_WL<84> B_WL<83> B_WL<82> B_WL<81> B_WL<80> B_WL<79> B_WL<78> B_WL<77> B_WL<76> B_WL<75> B_WL<74> B_WL<73> B_WL<72> B_WL<71> B_WL<70> B_WL<69> B_WL<68> B_WL<67> B_WL<66> B_WL<65> B_WL<64> B_WL<63> B_WL<62> B_WL<61> B_WL<60> B_WL<59> B_WL<58> B_WL<57> B_WL<56> B_WL<55> B_WL<54> B_WL<53> B_WL<52> B_WL<51> B_WL<50> B_WL<49> B_WL<48> B_WL<47> B_WL<46> B_WL<45> B_WL<44> B_WL<43> B_WL<42> B_WL<41> B_WL<40> B_WL<39> B_WL<38> B_WL<37> B_WL<36> B_WL<35> B_WL<34> B_WL<33> B_WL<32> B_WL<31> B_WL<30> B_WL<29> B_WL<28> B_WL<27> B_WL<26> B_WL<25> B_WL<24> B_WL<23> B_WL<22> B_WL<21> B_WL<20> B_WL<19> B_WL<18> B_WL<17> B_WL<16> B_WL<15> B_WL<14> B_WL<13> B_WL<12> B_WL<11> B_WL<10> B_WL<9> B_WL<8> B_WL<7> B_WL<6> B_WL<5> B_WL<4> B_WL<3> B_WL<2> B_WL<1> B_WL<0> B_IWL<127> B_IWL<126> B_IWL<125> B_IWL<124> B_IWL<123> B_IWL<122> B_IWL<121> B_IWL<120> B_IWL<119> B_IWL<118> B_IWL<117> B_IWL<116> B_IWL<115> B_IWL<114> B_IWL<113> B_IWL<112> B_IWL<111> B_IWL<110> B_IWL<109> B_IWL<108> B_IWL<107> B_IWL<106> B_IWL<105> B_IWL<104> B_IWL<103> B_IWL<102> B_IWL<101> B_IWL<100> B_IWL<99> B_IWL<98> B_IWL<97> B_IWL<96> B_IWL<95> B_IWL<94> B_IWL<93> B_IWL<92> B_IWL<91> B_IWL<90> B_IWL<89> B_IWL<88> B_IWL<87> B_IWL<86> B_IWL<85> B_IWL<84> B_IWL<83> B_IWL<82> B_IWL<81> B_IWL<80> B_IWL<79> B_IWL<78> B_IWL<77> B_IWL<76> B_IWL<75> B_IWL<74> B_IWL<73> B_IWL<72> B_IWL<71> B_IWL<70> B_IWL<69> B_IWL<68> B_IWL<67> B_IWL<66> B_IWL<65> B_IWL<64> B_IWL<63> B_IWL<62> B_IWL<61> B_IWL<60> B_IWL<59> B_IWL<58> B_IWL<57> B_IWL<56> B_IWL<55> B_IWL<54> B_IWL<53> B_IWL<52> B_IWL<51> B_IWL<50> B_IWL<49> B_IWL<48> B_IWL<47> B_IWL<46> B_IWL<45> B_IWL<44> B_IWL<43> B_IWL<42> B_IWL<41> B_IWL<40> B_IWL<39> B_IWL<38> B_IWL<37> B_IWL<36> B_IWL<35> B_IWL<34> B_IWL<33> B_IWL<32> B_IWL<31> B_IWL<30> B_IWL<29> B_IWL<28> B_IWL<27> B_IWL<26> B_IWL<25> B_IWL<24> B_IWL<23> B_IWL<22> B_IWL<21> B_IWL<20> B_IWL<19> B_IWL<18> B_IWL<17> B_IWL<16> B_IWL<15> B_IWL<14> B_IWL<13> B_IWL<12> B_IWL<11> B_IWL<10> B_IWL<9> B_IWL<8> B_IWL<7> B_IWL<6> B_IWL<5> B_IWL<4> B_IWL<3> B_IWL<2> B_IWL<1> B_IWL<0> VDD_CORE VSS / RM_IHPSG13_512x32_c2_2P_COLUMN_pcell_0 +.ENDS + + + + +.SUBCKT RM_IHPSG13_512x32_c2_2P_DLY_pcell_2 A Z VDD VSS + XIDL<2> D<9> Z VDD VSS / RSC_IHPSG13_CDLYX1 + XIDL<1> D<8> D<9> VDD VSS / RSC_IHPSG13_CDLYX1 + XIDM<8> D<7> D<8> VDD VSS / RSC_IHPSG13_CDLYX1_DUMMY + XIDM<7> D<6> D<7> VDD VSS / RSC_IHPSG13_CDLYX1_DUMMY + XIDM<6> D<5> D<6> VDD VSS / RSC_IHPSG13_CDLYX1_DUMMY + XIDM<5> D<4> D<5> VDD VSS / RSC_IHPSG13_CDLYX1_DUMMY + XIDM<4> D<3> D<4> VDD VSS / RSC_IHPSG13_CDLYX1_DUMMY + XIDM<3> D<2> D<3> VDD VSS / RSC_IHPSG13_CDLYX1_DUMMY + XIDM<2> D<1> D<2> VDD VSS / RSC_IHPSG13_CDLYX1_DUMMY + XIDM<1> A D<1> VDD VSS / RSC_IHPSG13_CDLYX1_DUMMY +.ENDS + + +.SUBCKT RM_IHPSG13_512x32_c2_2P_DLY_pcell_3 A Z VDD VSS + XIDL<2> D<9> Z VDD VSS / RSC_IHPSG13_CDLYX1 + XIDL<1> D<8> D<9> VDD VSS / RSC_IHPSG13_CDLYX1 + XIDM<8> D<7> D<8> VDD VSS / RSC_IHPSG13_CDLYX1_DUMMY + XIDM<7> D<6> D<7> VDD VSS / RSC_IHPSG13_CDLYX1_DUMMY + XIDM<6> D<5> D<6> VDD VSS / RSC_IHPSG13_CDLYX1_DUMMY + XIDM<5> D<4> D<5> VDD VSS / RSC_IHPSG13_CDLYX1_DUMMY + XIDM<4> D<3> D<4> VDD VSS / RSC_IHPSG13_CDLYX1_DUMMY + XIDM<3> D<2> D<3> VDD VSS / RSC_IHPSG13_CDLYX1_DUMMY + XIDM<2> D<1> D<2> VDD VSS / RSC_IHPSG13_CDLYX1_DUMMY + XIDM<1> A D<1> VDD VSS / RSC_IHPSG13_CDLYX1_DUMMY +.ENDS + + + +.SUBCKT RM_IHPSG13_2P_512x32_c2_bm_bist A_ADDR<8> A_ADDR<7> A_ADDR<6> A_ADDR<5> A_ADDR<4> A_ADDR<3> A_ADDR<2> A_ADDR<1> A_ADDR<0> A_BIST_ADDR<8> A_BIST_ADDR<7> A_BIST_ADDR<6> A_BIST_ADDR<5> A_BIST_ADDR<4> A_BIST_ADDR<3> A_BIST_ADDR<2> A_BIST_ADDR<1> A_BIST_ADDR<0> A_BIST_BM<31> A_BIST_BM<30> A_BIST_BM<29> A_BIST_BM<28> A_BIST_BM<27> A_BIST_BM<26> A_BIST_BM<25> A_BIST_BM<24> A_BIST_BM<23> A_BIST_BM<22> A_BIST_BM<21> A_BIST_BM<20> A_BIST_BM<19> A_BIST_BM<18> A_BIST_BM<17> A_BIST_BM<16> A_BIST_BM<15> A_BIST_BM<14> A_BIST_BM<13> A_BIST_BM<12> A_BIST_BM<11> A_BIST_BM<10> A_BIST_BM<9> A_BIST_BM<8> A_BIST_BM<7> A_BIST_BM<6> A_BIST_BM<5> A_BIST_BM<4> A_BIST_BM<3> A_BIST_BM<2> A_BIST_BM<1> A_BIST_BM<0> A_BIST_CLK A_BIST_DIN<31> A_BIST_DIN<30> A_BIST_DIN<29> A_BIST_DIN<28> A_BIST_DIN<27> A_BIST_DIN<26> A_BIST_DIN<25> A_BIST_DIN<24> A_BIST_DIN<23> A_BIST_DIN<22> A_BIST_DIN<21> A_BIST_DIN<20> A_BIST_DIN<19> A_BIST_DIN<18> A_BIST_DIN<17> A_BIST_DIN<16> A_BIST_DIN<15> A_BIST_DIN<14> A_BIST_DIN<13> A_BIST_DIN<12> A_BIST_DIN<11> A_BIST_DIN<10> A_BIST_DIN<9> A_BIST_DIN<8> A_BIST_DIN<7> A_BIST_DIN<6> A_BIST_DIN<5> A_BIST_DIN<4> A_BIST_DIN<3> A_BIST_DIN<2> A_BIST_DIN<1> A_BIST_DIN<0> A_BIST_EN A_BIST_MEN A_BIST_REN A_BIST_WEN A_BM<31> A_BM<30> A_BM<29> A_BM<28> A_BM<27> A_BM<26> A_BM<25> A_BM<24> A_BM<23> A_BM<22> A_BM<21> A_BM<20> A_BM<19> A_BM<18> A_BM<17> A_BM<16> A_BM<15> A_BM<14> A_BM<13> A_BM<12> A_BM<11> A_BM<10> A_BM<9> A_BM<8> A_BM<7> A_BM<6> A_BM<5> A_BM<4> A_BM<3> A_BM<2> A_BM<1> A_BM<0> A_CLK A_DIN<31> A_DIN<30> A_DIN<29> A_DIN<28> A_DIN<27> A_DIN<26> A_DIN<25> A_DIN<24> A_DIN<23> A_DIN<22> A_DIN<21> A_DIN<20> A_DIN<19> A_DIN<18> A_DIN<17> A_DIN<16> A_DIN<15> A_DIN<14> A_DIN<13> A_DIN<12> A_DIN<11> A_DIN<10> A_DIN<9> A_DIN<8> A_DIN<7> A_DIN<6> A_DIN<5> A_DIN<4> A_DIN<3> A_DIN<2> A_DIN<1> A_DIN<0> A_DLY A_DOUT<31> A_DOUT<30> A_DOUT<29> A_DOUT<28> A_DOUT<27> A_DOUT<26> A_DOUT<25> A_DOUT<24> A_DOUT<23> A_DOUT<22> A_DOUT<21> A_DOUT<20> A_DOUT<19> A_DOUT<18> A_DOUT<17> A_DOUT<16> A_DOUT<15> A_DOUT<14> A_DOUT<13> A_DOUT<12> A_DOUT<11> A_DOUT<10> A_DOUT<9> A_DOUT<8> A_DOUT<7> A_DOUT<6> A_DOUT<5> A_DOUT<4> A_DOUT<3> A_DOUT<2> A_DOUT<1> A_DOUT<0> A_MEN A_REN A_WEN B_ADDR<8> B_ADDR<7> B_ADDR<6> B_ADDR<5> B_ADDR<4> B_ADDR<3> B_ADDR<2> B_ADDR<1> B_ADDR<0> B_BIST_ADDR<8> B_BIST_ADDR<7> B_BIST_ADDR<6> B_BIST_ADDR<5> B_BIST_ADDR<4> B_BIST_ADDR<3> B_BIST_ADDR<2> B_BIST_ADDR<1> B_BIST_ADDR<0> B_BIST_BM<31> B_BIST_BM<30> B_BIST_BM<29> B_BIST_BM<28> B_BIST_BM<27> B_BIST_BM<26> B_BIST_BM<25> B_BIST_BM<24> B_BIST_BM<23> B_BIST_BM<22> B_BIST_BM<21> B_BIST_BM<20> B_BIST_BM<19> B_BIST_BM<18> B_BIST_BM<17> B_BIST_BM<16> B_BIST_BM<15> B_BIST_BM<14> B_BIST_BM<13> B_BIST_BM<12> B_BIST_BM<11> B_BIST_BM<10> B_BIST_BM<9> B_BIST_BM<8> B_BIST_BM<7> B_BIST_BM<6> B_BIST_BM<5> B_BIST_BM<4> B_BIST_BM<3> B_BIST_BM<2> B_BIST_BM<1> B_BIST_BM<0> B_BIST_CLK B_BIST_DIN<31> B_BIST_DIN<30> B_BIST_DIN<29> B_BIST_DIN<28> B_BIST_DIN<27> B_BIST_DIN<26> B_BIST_DIN<25> B_BIST_DIN<24> B_BIST_DIN<23> B_BIST_DIN<22> B_BIST_DIN<21> B_BIST_DIN<20> B_BIST_DIN<19> B_BIST_DIN<18> B_BIST_DIN<17> B_BIST_DIN<16> B_BIST_DIN<15> B_BIST_DIN<14> B_BIST_DIN<13> B_BIST_DIN<12> B_BIST_DIN<11> B_BIST_DIN<10> B_BIST_DIN<9> B_BIST_DIN<8> B_BIST_DIN<7> B_BIST_DIN<6> B_BIST_DIN<5> B_BIST_DIN<4> B_BIST_DIN<3> B_BIST_DIN<2> B_BIST_DIN<1> B_BIST_DIN<0> B_BIST_EN B_BIST_MEN B_BIST_REN B_BIST_WEN B_BM<31> B_BM<30> B_BM<29> B_BM<28> B_BM<27> B_BM<26> B_BM<25> B_BM<24> B_BM<23> B_BM<22> B_BM<21> B_BM<20> B_BM<19> B_BM<18> B_BM<17> B_BM<16> B_BM<15> B_BM<14> B_BM<13> B_BM<12> B_BM<11> B_BM<10> B_BM<9> B_BM<8> B_BM<7> B_BM<6> B_BM<5> B_BM<4> B_BM<3> B_BM<2> B_BM<1> B_BM<0> B_CLK B_DIN<31> B_DIN<30> B_DIN<29> B_DIN<28> B_DIN<27> B_DIN<26> B_DIN<25> B_DIN<24> B_DIN<23> B_DIN<22> B_DIN<21> B_DIN<20> B_DIN<19> B_DIN<18> B_DIN<17> B_DIN<16> B_DIN<15> B_DIN<14> B_DIN<13> B_DIN<12> B_DIN<11> B_DIN<10> B_DIN<9> B_DIN<8> B_DIN<7> B_DIN<6> B_DIN<5> B_DIN<4> B_DIN<3> B_DIN<2> B_DIN<1> B_DIN<0> B_DLY B_DOUT<31> B_DOUT<30> B_DOUT<29> B_DOUT<28> B_DOUT<27> B_DOUT<26> B_DOUT<25> B_DOUT<24> B_DOUT<23> B_DOUT<22> B_DOUT<21> B_DOUT<20> B_DOUT<19> B_DOUT<18> B_DOUT<17> B_DOUT<16> B_DOUT<15> B_DOUT<14> B_DOUT<13> B_DOUT<12> B_DOUT<11> B_DOUT<10> B_DOUT<9> B_DOUT<8> B_DOUT<7> B_DOUT<6> B_DOUT<5> B_DOUT<4> B_DOUT<3> B_DOUT<2> B_DOUT<1> B_DOUT<0> B_MEN B_REN B_WEN VDD! VDDARRAY! VSS! + + +XRAM<1> a_blc_r<63> a_blc_r<62> a_blc_r<61> a_blc_r<60> a_blc_r<59> a_blc_r<58> a_blc_r<57> a_blc_r<56> a_blc_r<55> a_blc_r<54> a_blc_r<53> a_blc_r<52> a_blc_r<51> a_blc_r<50> a_blc_r<49> a_blc_r<48> a_blc_r<47> a_blc_r<46> a_blc_r<45> a_blc_r<44> a_blc_r<43> a_blc_r<42> a_blc_r<41> a_blc_r<40> a_blc_r<39> a_blc_r<38> a_blc_r<37> a_blc_r<36> a_blc_r<35> a_blc_r<34> a_blc_r<33> a_blc_r<32> a_blc_r<31> a_blc_r<30> a_blc_r<29> a_blc_r<28> a_blc_r<27> a_blc_r<26> a_blc_r<25> a_blc_r<24> a_blc_r<23> a_blc_r<22> a_blc_r<21> a_blc_r<20> a_blc_r<19> a_blc_r<18> a_blc_r<17> a_blc_r<16> a_blc_r<15> a_blc_r<14> a_blc_r<13> a_blc_r<12> a_blc_r<11> a_blc_r<10> a_blc_r<9> a_blc_r<8> a_blc_r<7> a_blc_r<6> a_blc_r<5> a_blc_r<4> a_blc_r<3> a_blc_r<2> a_blc_r<1> a_blc_r<0> a_blt_r<63> a_blt_r<62> a_blt_r<61> a_blt_r<60> a_blt_r<59> a_blt_r<58> a_blt_r<57> a_blt_r<56> a_blt_r<55> a_blt_r<54> a_blt_r<53> a_blt_r<52> a_blt_r<51> a_blt_r<50> a_blt_r<49> a_blt_r<48> a_blt_r<47> a_blt_r<46> a_blt_r<45> a_blt_r<44> a_blt_r<43> a_blt_r<42> a_blt_r<41> a_blt_r<40> a_blt_r<39> a_blt_r<38> a_blt_r<37> a_blt_r<36> a_blt_r<35> a_blt_r<34> a_blt_r<33> a_blt_r<32> a_blt_r<31> a_blt_r<30> a_blt_r<29> a_blt_r<28> a_blt_r<27> a_blt_r<26> a_blt_r<25> a_blt_r<24> a_blt_r<23> a_blt_r<22> a_blt_r<21> a_blt_r<20> a_blt_r<19> a_blt_r<18> a_blt_r<17> a_blt_r<16> a_blt_r<15> a_blt_r<14> a_blt_r<13> a_blt_r<12> a_blt_r<11> a_blt_r<10> a_blt_r<9> a_blt_r<8> a_blt_r<7> a_blt_r<6> a_blt_r<5> a_blt_r<4> a_blt_r<3> a_blt_r<2> a_blt_r<1> a_blt_r<0> a_wl_r<127> a_wl_r<126> a_wl_r<125> a_wl_r<124> a_wl_r<123> a_wl_r<122> a_wl_r<121> a_wl_r<120> a_wl_r<119> a_wl_r<118> a_wl_r<117> a_wl_r<116> a_wl_r<115> a_wl_r<114> a_wl_r<113> a_wl_r<112> a_wl_r<111> a_wl_r<110> a_wl_r<109> a_wl_r<108> a_wl_r<107> a_wl_r<106> a_wl_r<105> a_wl_r<104> a_wl_r<103> a_wl_r<102> a_wl_r<101> a_wl_r<100> a_wl_r<99> a_wl_r<98> a_wl_r<97> a_wl_r<96> a_wl_r<95> a_wl_r<94> a_wl_r<93> a_wl_r<92> a_wl_r<91> a_wl_r<90> a_wl_r<89> a_wl_r<88> a_wl_r<87> a_wl_r<86> a_wl_r<85> a_wl_r<84> a_wl_r<83> a_wl_r<82> a_wl_r<81> a_wl_r<80> a_wl_r<79> a_wl_r<78> a_wl_r<77> a_wl_r<76> a_wl_r<75> a_wl_r<74> a_wl_r<73> a_wl_r<72> a_wl_r<71> a_wl_r<70> a_wl_r<69> a_wl_r<68> a_wl_r<67> a_wl_r<66> a_wl_r<65> a_wl_r<64> a_wl_r<63> a_wl_r<62> a_wl_r<61> a_wl_r<60> a_wl_r<59> a_wl_r<58> a_wl_r<57> a_wl_r<56> a_wl_r<55> a_wl_r<54> a_wl_r<53> a_wl_r<52> a_wl_r<51> a_wl_r<50> a_wl_r<49> a_wl_r<48> a_wl_r<47> a_wl_r<46> a_wl_r<45> a_wl_r<44> a_wl_r<43> a_wl_r<42> a_wl_r<41> a_wl_r<40> a_wl_r<39> a_wl_r<38> a_wl_r<37> a_wl_r<36> a_wl_r<35> a_wl_r<34> a_wl_r<33> a_wl_r<32> a_wl_r<31> a_wl_r<30> a_wl_r<29> a_wl_r<28> a_wl_r<27> a_wl_r<26> a_wl_r<25> a_wl_r<24> a_wl_r<23> a_wl_r<22> a_wl_r<21> a_wl_r<20> a_wl_r<19> a_wl_r<18> a_wl_r<17> a_wl_r<16> a_wl_r<15> a_wl_r<14> a_wl_r<13> a_wl_r<12> a_wl_r<11> a_wl_r<10> a_wl_r<9> a_wl_r<8> a_wl_r<7> a_wl_r<6> a_wl_r<5> a_wl_r<4> a_wl_r<3> a_wl_r<2> a_wl_r<1> a_wl_r<0> b_blc_r<63> b_blc_r<62> b_blc_r<61> b_blc_r<60> b_blc_r<59> b_blc_r<58> b_blc_r<57> b_blc_r<56> b_blc_r<55> b_blc_r<54> b_blc_r<53> b_blc_r<52> b_blc_r<51> b_blc_r<50> b_blc_r<49> b_blc_r<48> b_blc_r<47> b_blc_r<46> b_blc_r<45> b_blc_r<44> b_blc_r<43> b_blc_r<42> b_blc_r<41> b_blc_r<40> b_blc_r<39> b_blc_r<38> b_blc_r<37> b_blc_r<36> b_blc_r<35> b_blc_r<34> b_blc_r<33> b_blc_r<32> b_blc_r<31> b_blc_r<30> b_blc_r<29> b_blc_r<28> b_blc_r<27> b_blc_r<26> b_blc_r<25> b_blc_r<24> b_blc_r<23> b_blc_r<22> b_blc_r<21> b_blc_r<20> b_blc_r<19> b_blc_r<18> b_blc_r<17> b_blc_r<16> b_blc_r<15> b_blc_r<14> b_blc_r<13> b_blc_r<12> b_blc_r<11> b_blc_r<10> b_blc_r<9> b_blc_r<8> b_blc_r<7> b_blc_r<6> b_blc_r<5> b_blc_r<4> b_blc_r<3> b_blc_r<2> b_blc_r<1> b_blc_r<0> b_blt_r<63> b_blt_r<62> b_blt_r<61> b_blt_r<60> b_blt_r<59> b_blt_r<58> b_blt_r<57> b_blt_r<56> b_blt_r<55> b_blt_r<54> b_blt_r<53> b_blt_r<52> b_blt_r<51> b_blt_r<50> b_blt_r<49> b_blt_r<48> b_blt_r<47> b_blt_r<46> b_blt_r<45> b_blt_r<44> b_blt_r<43> b_blt_r<42> b_blt_r<41> b_blt_r<40> b_blt_r<39> b_blt_r<38> b_blt_r<37> b_blt_r<36> b_blt_r<35> b_blt_r<34> b_blt_r<33> b_blt_r<32> b_blt_r<31> b_blt_r<30> b_blt_r<29> b_blt_r<28> b_blt_r<27> b_blt_r<26> b_blt_r<25> b_blt_r<24> b_blt_r<23> b_blt_r<22> b_blt_r<21> b_blt_r<20> b_blt_r<19> b_blt_r<18> b_blt_r<17> b_blt_r<16> b_blt_r<15> b_blt_r<14> b_blt_r<13> b_blt_r<12> b_blt_r<11> b_blt_r<10> b_blt_r<9> b_blt_r<8> b_blt_r<7> b_blt_r<6> b_blt_r<5> b_blt_r<4> b_blt_r<3> b_blt_r<2> b_blt_r<1> b_blt_r<0> b_wl_r<127> b_wl_r<126> b_wl_r<125> b_wl_r<124> b_wl_r<123> b_wl_r<122> b_wl_r<121> b_wl_r<120> b_wl_r<119> b_wl_r<118> b_wl_r<117> b_wl_r<116> b_wl_r<115> b_wl_r<114> b_wl_r<113> b_wl_r<112> b_wl_r<111> b_wl_r<110> b_wl_r<109> b_wl_r<108> b_wl_r<107> b_wl_r<106> b_wl_r<105> b_wl_r<104> b_wl_r<103> b_wl_r<102> b_wl_r<101> b_wl_r<100> b_wl_r<99> b_wl_r<98> b_wl_r<97> b_wl_r<96> b_wl_r<95> b_wl_r<94> b_wl_r<93> b_wl_r<92> b_wl_r<91> b_wl_r<90> b_wl_r<89> b_wl_r<88> b_wl_r<87> b_wl_r<86> b_wl_r<85> b_wl_r<84> b_wl_r<83> b_wl_r<82> b_wl_r<81> b_wl_r<80> b_wl_r<79> b_wl_r<78> b_wl_r<77> b_wl_r<76> b_wl_r<75> b_wl_r<74> b_wl_r<73> b_wl_r<72> b_wl_r<71> b_wl_r<70> b_wl_r<69> b_wl_r<68> b_wl_r<67> b_wl_r<66> b_wl_r<65> b_wl_r<64> b_wl_r<63> b_wl_r<62> b_wl_r<61> b_wl_r<60> b_wl_r<59> b_wl_r<58> b_wl_r<57> b_wl_r<56> b_wl_r<55> b_wl_r<54> b_wl_r<53> b_wl_r<52> b_wl_r<51> b_wl_r<50> b_wl_r<49> b_wl_r<48> b_wl_r<47> b_wl_r<46> b_wl_r<45> b_wl_r<44> b_wl_r<43> b_wl_r<42> b_wl_r<41> b_wl_r<40> b_wl_r<39> b_wl_r<38> b_wl_r<37> b_wl_r<36> b_wl_r<35> b_wl_r<34> b_wl_r<33> b_wl_r<32> b_wl_r<31> b_wl_r<30> b_wl_r<29> b_wl_r<28> b_wl_r<27> b_wl_r<26> b_wl_r<25> b_wl_r<24> b_wl_r<23> b_wl_r<22> b_wl_r<21> b_wl_r<20> b_wl_r<19> b_wl_r<18> b_wl_r<17> b_wl_r<16> b_wl_r<15> b_wl_r<14> b_wl_r<13> b_wl_r<12> b_wl_r<11> b_wl_r<10> b_wl_r<9> b_wl_r<8> b_wl_r<7> b_wl_r<6> b_wl_r<5> b_wl_r<4> b_wl_r<3> b_wl_r<2> b_wl_r<1> b_wl_r<0> VDDARRAY! VSS! / RM_IHPSG13_512x32_c2_2P_MATRIX_pcell_1 +XRAM<0> a_blc_l<63> a_blc_l<62> a_blc_l<61> a_blc_l<60> a_blc_l<59> a_blc_l<58> a_blc_l<57> a_blc_l<56> a_blc_l<55> a_blc_l<54> a_blc_l<53> a_blc_l<52> a_blc_l<51> a_blc_l<50> a_blc_l<49> a_blc_l<48> a_blc_l<47> a_blc_l<46> a_blc_l<45> a_blc_l<44> a_blc_l<43> a_blc_l<42> a_blc_l<41> a_blc_l<40> a_blc_l<39> a_blc_l<38> a_blc_l<37> a_blc_l<36> a_blc_l<35> a_blc_l<34> a_blc_l<33> a_blc_l<32> a_blc_l<31> a_blc_l<30> a_blc_l<29> a_blc_l<28> a_blc_l<27> a_blc_l<26> a_blc_l<25> a_blc_l<24> a_blc_l<23> a_blc_l<22> a_blc_l<21> a_blc_l<20> a_blc_l<19> a_blc_l<18> a_blc_l<17> a_blc_l<16> a_blc_l<15> a_blc_l<14> a_blc_l<13> a_blc_l<12> a_blc_l<11> a_blc_l<10> a_blc_l<9> a_blc_l<8> a_blc_l<7> a_blc_l<6> a_blc_l<5> a_blc_l<4> a_blc_l<3> a_blc_l<2> a_blc_l<1> a_blc_l<0> a_blt_l<63> a_blt_l<62> a_blt_l<61> a_blt_l<60> a_blt_l<59> a_blt_l<58> a_blt_l<57> a_blt_l<56> a_blt_l<55> a_blt_l<54> a_blt_l<53> a_blt_l<52> a_blt_l<51> a_blt_l<50> a_blt_l<49> a_blt_l<48> a_blt_l<47> a_blt_l<46> a_blt_l<45> a_blt_l<44> a_blt_l<43> a_blt_l<42> a_blt_l<41> a_blt_l<40> a_blt_l<39> a_blt_l<38> a_blt_l<37> a_blt_l<36> a_blt_l<35> a_blt_l<34> a_blt_l<33> a_blt_l<32> a_blt_l<31> a_blt_l<30> a_blt_l<29> a_blt_l<28> a_blt_l<27> a_blt_l<26> a_blt_l<25> a_blt_l<24> a_blt_l<23> a_blt_l<22> a_blt_l<21> a_blt_l<20> a_blt_l<19> a_blt_l<18> a_blt_l<17> a_blt_l<16> a_blt_l<15> a_blt_l<14> a_blt_l<13> a_blt_l<12> a_blt_l<11> a_blt_l<10> a_blt_l<9> a_blt_l<8> a_blt_l<7> a_blt_l<6> a_blt_l<5> a_blt_l<4> a_blt_l<3> a_blt_l<2> a_blt_l<1> a_blt_l<0> a_wl_l<127> a_wl_l<126> a_wl_l<125> a_wl_l<124> a_wl_l<123> a_wl_l<122> a_wl_l<121> a_wl_l<120> a_wl_l<119> a_wl_l<118> a_wl_l<117> a_wl_l<116> a_wl_l<115> a_wl_l<114> a_wl_l<113> a_wl_l<112> a_wl_l<111> a_wl_l<110> a_wl_l<109> a_wl_l<108> a_wl_l<107> a_wl_l<106> a_wl_l<105> a_wl_l<104> a_wl_l<103> a_wl_l<102> a_wl_l<101> a_wl_l<100> a_wl_l<99> a_wl_l<98> a_wl_l<97> a_wl_l<96> a_wl_l<95> a_wl_l<94> a_wl_l<93> a_wl_l<92> a_wl_l<91> a_wl_l<90> a_wl_l<89> a_wl_l<88> a_wl_l<87> a_wl_l<86> a_wl_l<85> a_wl_l<84> a_wl_l<83> a_wl_l<82> a_wl_l<81> a_wl_l<80> a_wl_l<79> a_wl_l<78> a_wl_l<77> a_wl_l<76> a_wl_l<75> a_wl_l<74> a_wl_l<73> a_wl_l<72> a_wl_l<71> a_wl_l<70> a_wl_l<69> a_wl_l<68> a_wl_l<67> a_wl_l<66> a_wl_l<65> a_wl_l<64> a_wl_l<63> a_wl_l<62> a_wl_l<61> a_wl_l<60> a_wl_l<59> a_wl_l<58> a_wl_l<57> a_wl_l<56> a_wl_l<55> a_wl_l<54> a_wl_l<53> a_wl_l<52> a_wl_l<51> a_wl_l<50> a_wl_l<49> a_wl_l<48> a_wl_l<47> a_wl_l<46> a_wl_l<45> a_wl_l<44> a_wl_l<43> a_wl_l<42> a_wl_l<41> a_wl_l<40> a_wl_l<39> a_wl_l<38> a_wl_l<37> a_wl_l<36> a_wl_l<35> a_wl_l<34> a_wl_l<33> a_wl_l<32> a_wl_l<31> a_wl_l<30> a_wl_l<29> a_wl_l<28> a_wl_l<27> a_wl_l<26> a_wl_l<25> a_wl_l<24> a_wl_l<23> a_wl_l<22> a_wl_l<21> a_wl_l<20> a_wl_l<19> a_wl_l<18> a_wl_l<17> a_wl_l<16> a_wl_l<15> a_wl_l<14> a_wl_l<13> a_wl_l<12> a_wl_l<11> a_wl_l<10> a_wl_l<9> a_wl_l<8> a_wl_l<7> a_wl_l<6> a_wl_l<5> a_wl_l<4> a_wl_l<3> a_wl_l<2> a_wl_l<1> a_wl_l<0> b_blc_l<63> b_blc_l<62> b_blc_l<61> b_blc_l<60> b_blc_l<59> b_blc_l<58> b_blc_l<57> b_blc_l<56> b_blc_l<55> b_blc_l<54> b_blc_l<53> b_blc_l<52> b_blc_l<51> b_blc_l<50> b_blc_l<49> b_blc_l<48> b_blc_l<47> b_blc_l<46> b_blc_l<45> b_blc_l<44> b_blc_l<43> b_blc_l<42> b_blc_l<41> b_blc_l<40> b_blc_l<39> b_blc_l<38> b_blc_l<37> b_blc_l<36> b_blc_l<35> b_blc_l<34> b_blc_l<33> b_blc_l<32> b_blc_l<31> b_blc_l<30> b_blc_l<29> b_blc_l<28> b_blc_l<27> b_blc_l<26> b_blc_l<25> b_blc_l<24> b_blc_l<23> b_blc_l<22> b_blc_l<21> b_blc_l<20> b_blc_l<19> b_blc_l<18> b_blc_l<17> b_blc_l<16> b_blc_l<15> b_blc_l<14> b_blc_l<13> b_blc_l<12> b_blc_l<11> b_blc_l<10> b_blc_l<9> b_blc_l<8> b_blc_l<7> b_blc_l<6> b_blc_l<5> b_blc_l<4> b_blc_l<3> b_blc_l<2> b_blc_l<1> b_blc_l<0> b_blt_l<63> b_blt_l<62> b_blt_l<61> b_blt_l<60> b_blt_l<59> b_blt_l<58> b_blt_l<57> b_blt_l<56> b_blt_l<55> b_blt_l<54> b_blt_l<53> b_blt_l<52> b_blt_l<51> b_blt_l<50> b_blt_l<49> b_blt_l<48> b_blt_l<47> b_blt_l<46> b_blt_l<45> b_blt_l<44> b_blt_l<43> b_blt_l<42> b_blt_l<41> b_blt_l<40> b_blt_l<39> b_blt_l<38> b_blt_l<37> b_blt_l<36> b_blt_l<35> b_blt_l<34> b_blt_l<33> b_blt_l<32> b_blt_l<31> b_blt_l<30> b_blt_l<29> b_blt_l<28> b_blt_l<27> b_blt_l<26> b_blt_l<25> b_blt_l<24> b_blt_l<23> b_blt_l<22> b_blt_l<21> b_blt_l<20> b_blt_l<19> b_blt_l<18> b_blt_l<17> b_blt_l<16> b_blt_l<15> b_blt_l<14> b_blt_l<13> b_blt_l<12> b_blt_l<11> b_blt_l<10> b_blt_l<9> b_blt_l<8> b_blt_l<7> b_blt_l<6> b_blt_l<5> b_blt_l<4> b_blt_l<3> b_blt_l<2> b_blt_l<1> b_blt_l<0> b_wl_l<127> b_wl_l<126> b_wl_l<125> b_wl_l<124> b_wl_l<123> b_wl_l<122> b_wl_l<121> b_wl_l<120> b_wl_l<119> b_wl_l<118> b_wl_l<117> b_wl_l<116> b_wl_l<115> b_wl_l<114> b_wl_l<113> b_wl_l<112> b_wl_l<111> b_wl_l<110> b_wl_l<109> b_wl_l<108> b_wl_l<107> b_wl_l<106> b_wl_l<105> b_wl_l<104> b_wl_l<103> b_wl_l<102> b_wl_l<101> b_wl_l<100> b_wl_l<99> b_wl_l<98> b_wl_l<97> b_wl_l<96> b_wl_l<95> b_wl_l<94> b_wl_l<93> b_wl_l<92> b_wl_l<91> b_wl_l<90> b_wl_l<89> b_wl_l<88> b_wl_l<87> b_wl_l<86> b_wl_l<85> b_wl_l<84> b_wl_l<83> b_wl_l<82> b_wl_l<81> b_wl_l<80> b_wl_l<79> b_wl_l<78> b_wl_l<77> b_wl_l<76> b_wl_l<75> b_wl_l<74> b_wl_l<73> b_wl_l<72> b_wl_l<71> b_wl_l<70> b_wl_l<69> b_wl_l<68> b_wl_l<67> b_wl_l<66> b_wl_l<65> b_wl_l<64> b_wl_l<63> b_wl_l<62> b_wl_l<61> b_wl_l<60> b_wl_l<59> b_wl_l<58> b_wl_l<57> b_wl_l<56> b_wl_l<55> b_wl_l<54> b_wl_l<53> b_wl_l<52> b_wl_l<51> b_wl_l<50> b_wl_l<49> b_wl_l<48> b_wl_l<47> b_wl_l<46> b_wl_l<45> b_wl_l<44> b_wl_l<43> b_wl_l<42> b_wl_l<41> b_wl_l<40> b_wl_l<39> b_wl_l<38> b_wl_l<37> b_wl_l<36> b_wl_l<35> b_wl_l<34> b_wl_l<33> b_wl_l<32> b_wl_l<31> b_wl_l<30> b_wl_l<29> b_wl_l<28> b_wl_l<27> b_wl_l<26> b_wl_l<25> b_wl_l<24> b_wl_l<23> b_wl_l<22> b_wl_l<21> b_wl_l<20> b_wl_l<19> b_wl_l<18> b_wl_l<17> b_wl_l<16> b_wl_l<15> b_wl_l<14> b_wl_l<13> b_wl_l<12> b_wl_l<11> b_wl_l<10> b_wl_l<9> b_wl_l<8> b_wl_l<7> b_wl_l<6> b_wl_l<5> b_wl_l<4> b_wl_l<3> b_wl_l<2> b_wl_l<1> b_wl_l<0> VDDARRAY! VSS! / RM_IHPSG13_512x32_c2_2P_MATRIX_pcell_1 + + +XB_COLDRV<1> b_addr_col<1> b_addr_col<0> b_addr_col_r<1> b_addr_col_r<0> b_addr_dec<7> b_addr_dec<6> b_addr_dec<5> b_addr_dec<4> b_addr_dec<3> b_addr_dec<2> b_addr_dec<1> b_addr_dec<0> b_addr_dec_r<7> b_addr_dec_r<6> b_addr_dec_r<5> b_addr_dec_r<4> b_addr_dec_r<3> b_addr_dec_r<2> b_addr_dec_r<1> b_addr_dec_r<0> b_dclk b_dclk_p_r<0> b_rclk b_rclk_p_r<0> b_wclk b_wclk_p_r<0> VDD! VSS! / RM_IHPSG13_512x32_c2_2P_COLDRV13X4 +XB_COLDRV<0> b_addr_col<1> b_addr_col<0> b_addr_col_l<1> b_addr_col_l<0> b_addr_dec<7> b_addr_dec<6> b_addr_dec<5> b_addr_dec<4> b_addr_dec<3> b_addr_dec<2> b_addr_dec<1> b_addr_dec<0> b_addr_dec_l<7> b_addr_dec_l<6> b_addr_dec_l<5> b_addr_dec_l<4> b_addr_dec_l<3> b_addr_dec_l<2> b_addr_dec_l<1> b_addr_dec_l<0> b_dclk b_dclk_p_l<0> b_rclk b_rclk_p_l<0> b_wclk b_wclk_p_l<0> VDD! VSS! / RM_IHPSG13_512x32_c2_2P_COLDRV13X4 +XA_COLDRV<1> a_addr_col<1> a_addr_col<0> a_addr_col_r<1> a_addr_col_r<0> a_addr_dec<7> a_addr_dec<6> a_addr_dec<5> a_addr_dec<4> a_addr_dec<3> a_addr_dec<2> a_addr_dec<1> a_addr_dec<0> a_addr_dec_r<7> a_addr_dec_r<6> a_addr_dec_r<5> a_addr_dec_r<4> a_addr_dec_r<3> a_addr_dec_r<2> a_addr_dec_r<1> a_addr_dec_r<0> a_dclk a_dclk_p_r<0> a_rclk a_rclk_p_r<0> a_wclk a_wclk_p_r<0> VDD! VSS! / RM_IHPSG13_512x32_c2_2P_COLDRV13X4 +XA_COLDRV<0> a_addr_col<1> a_addr_col<0> a_addr_col_l<1> a_addr_col_l<0> a_addr_dec<7> a_addr_dec<6> a_addr_dec<5> a_addr_dec<4> a_addr_dec<3> a_addr_dec<2> a_addr_dec<1> a_addr_dec<0> a_addr_dec_l<7> a_addr_dec_l<6> a_addr_dec_l<5> a_addr_dec_l<4> a_addr_dec_l<3> a_addr_dec_l<2> a_addr_dec_l<1> a_addr_dec_l<0> a_dclk a_dclk_p_l<0> a_rclk a_rclk_p_l<0> a_wclk a_wclk_p_l<0> VDD! VSS! / RM_IHPSG13_512x32_c2_2P_COLDRV13X4 + + +XB_WLDRV<15> b_wi<127> b_wi<126> b_wi<125> b_wi<124> b_wi<123> b_wi<122> b_wi<121> b_wi<120> b_wi<119> b_wi<118> b_wi<117> b_wi<116> b_wi<115> b_wi<114> b_wi<113> b_wi<112> b_wl_r<127> b_wl_r<126> b_wl_r<125> b_wl_r<124> b_wl_r<123> b_wl_r<122> b_wl_r<121> b_wl_r<120> b_wl_r<119> b_wl_r<118> b_wl_r<117> b_wl_r<116> b_wl_r<115> b_wl_r<114> b_wl_r<113> b_wl_r<112> VDD! VSS! / RM_IHPSG13_512x32_c2_2P_WLDRV16X4 +XB_WLDRV<14> b_wi<111> b_wi<110> b_wi<109> b_wi<108> b_wi<107> b_wi<106> b_wi<105> b_wi<104> b_wi<103> b_wi<102> b_wi<101> b_wi<100> b_wi<99> b_wi<98> b_wi<97> b_wi<96> b_wl_r<111> b_wl_r<110> b_wl_r<109> b_wl_r<108> b_wl_r<107> b_wl_r<106> b_wl_r<105> b_wl_r<104> b_wl_r<103> b_wl_r<102> b_wl_r<101> b_wl_r<100> b_wl_r<99> b_wl_r<98> b_wl_r<97> b_wl_r<96> VDD! VSS! / RM_IHPSG13_512x32_c2_2P_WLDRV16X4 +XB_WLDRV<13> b_wi<95> b_wi<94> b_wi<93> b_wi<92> b_wi<91> b_wi<90> b_wi<89> b_wi<88> b_wi<87> b_wi<86> b_wi<85> b_wi<84> b_wi<83> b_wi<82> b_wi<81> b_wi<80> b_wl_r<95> b_wl_r<94> b_wl_r<93> b_wl_r<92> b_wl_r<91> b_wl_r<90> b_wl_r<89> b_wl_r<88> b_wl_r<87> b_wl_r<86> b_wl_r<85> b_wl_r<84> b_wl_r<83> b_wl_r<82> b_wl_r<81> b_wl_r<80> VDD! VSS! / RM_IHPSG13_512x32_c2_2P_WLDRV16X4 +XB_WLDRV<12> b_wi<79> b_wi<78> b_wi<77> b_wi<76> b_wi<75> b_wi<74> b_wi<73> b_wi<72> b_wi<71> b_wi<70> b_wi<69> b_wi<68> b_wi<67> b_wi<66> b_wi<65> b_wi<64> b_wl_r<79> b_wl_r<78> b_wl_r<77> b_wl_r<76> b_wl_r<75> b_wl_r<74> b_wl_r<73> b_wl_r<72> b_wl_r<71> b_wl_r<70> b_wl_r<69> b_wl_r<68> b_wl_r<67> b_wl_r<66> b_wl_r<65> b_wl_r<64> VDD! VSS! / RM_IHPSG13_512x32_c2_2P_WLDRV16X4 +XB_WLDRV<11> b_wi<63> b_wi<62> b_wi<61> b_wi<60> b_wi<59> b_wi<58> b_wi<57> b_wi<56> b_wi<55> b_wi<54> b_wi<53> b_wi<52> b_wi<51> b_wi<50> b_wi<49> b_wi<48> b_wl_r<63> b_wl_r<62> b_wl_r<61> b_wl_r<60> b_wl_r<59> b_wl_r<58> b_wl_r<57> b_wl_r<56> b_wl_r<55> b_wl_r<54> b_wl_r<53> b_wl_r<52> b_wl_r<51> b_wl_r<50> b_wl_r<49> b_wl_r<48> VDD! VSS! / RM_IHPSG13_512x32_c2_2P_WLDRV16X4 +XB_WLDRV<10> b_wi<47> b_wi<46> b_wi<45> b_wi<44> b_wi<43> b_wi<42> b_wi<41> b_wi<40> b_wi<39> b_wi<38> b_wi<37> b_wi<36> b_wi<35> b_wi<34> b_wi<33> b_wi<32> b_wl_r<47> b_wl_r<46> b_wl_r<45> b_wl_r<44> b_wl_r<43> b_wl_r<42> b_wl_r<41> b_wl_r<40> b_wl_r<39> b_wl_r<38> b_wl_r<37> b_wl_r<36> b_wl_r<35> b_wl_r<34> b_wl_r<33> b_wl_r<32> VDD! VSS! / RM_IHPSG13_512x32_c2_2P_WLDRV16X4 +XB_WLDRV<9> b_wi<31> b_wi<30> b_wi<29> b_wi<28> b_wi<27> b_wi<26> b_wi<25> b_wi<24> b_wi<23> b_wi<22> b_wi<21> b_wi<20> b_wi<19> b_wi<18> b_wi<17> b_wi<16> b_wl_r<31> b_wl_r<30> b_wl_r<29> b_wl_r<28> b_wl_r<27> b_wl_r<26> b_wl_r<25> b_wl_r<24> b_wl_r<23> b_wl_r<22> b_wl_r<21> b_wl_r<20> b_wl_r<19> b_wl_r<18> b_wl_r<17> b_wl_r<16> VDD! VSS! / RM_IHPSG13_512x32_c2_2P_WLDRV16X4 +XB_WLDRV<8> b_wi<15> b_wi<14> b_wi<13> b_wi<12> b_wi<11> b_wi<10> b_wi<9> b_wi<8> b_wi<7> b_wi<6> b_wi<5> b_wi<4> b_wi<3> b_wi<2> b_wi<1> b_wi<0> b_wl_r<15> b_wl_r<14> b_wl_r<13> b_wl_r<12> b_wl_r<11> b_wl_r<10> b_wl_r<9> b_wl_r<8> b_wl_r<7> b_wl_r<6> b_wl_r<5> b_wl_r<4> b_wl_r<3> b_wl_r<2> b_wl_r<1> b_wl_r<0> VDD! VSS! / RM_IHPSG13_512x32_c2_2P_WLDRV16X4 +XB_WLDRV<7> b_wi<127> b_wi<126> b_wi<125> b_wi<124> b_wi<123> b_wi<122> b_wi<121> b_wi<120> b_wi<119> b_wi<118> b_wi<117> b_wi<116> b_wi<115> b_wi<114> b_wi<113> b_wi<112> b_wl_l<127> b_wl_l<126> b_wl_l<125> b_wl_l<124> b_wl_l<123> b_wl_l<122> b_wl_l<121> b_wl_l<120> b_wl_l<119> b_wl_l<118> b_wl_l<117> b_wl_l<116> b_wl_l<115> b_wl_l<114> b_wl_l<113> b_wl_l<112> VDD! VSS! / RM_IHPSG13_512x32_c2_2P_WLDRV16X4 +XB_WLDRV<6> b_wi<111> b_wi<110> b_wi<109> b_wi<108> b_wi<107> b_wi<106> b_wi<105> b_wi<104> b_wi<103> b_wi<102> b_wi<101> b_wi<100> b_wi<99> b_wi<98> b_wi<97> b_wi<96> b_wl_l<111> b_wl_l<110> b_wl_l<109> b_wl_l<108> b_wl_l<107> b_wl_l<106> b_wl_l<105> b_wl_l<104> b_wl_l<103> b_wl_l<102> b_wl_l<101> b_wl_l<100> b_wl_l<99> b_wl_l<98> b_wl_l<97> b_wl_l<96> VDD! VSS! / RM_IHPSG13_512x32_c2_2P_WLDRV16X4 +XB_WLDRV<5> b_wi<95> b_wi<94> b_wi<93> b_wi<92> b_wi<91> b_wi<90> b_wi<89> b_wi<88> b_wi<87> b_wi<86> b_wi<85> b_wi<84> b_wi<83> b_wi<82> b_wi<81> b_wi<80> b_wl_l<95> b_wl_l<94> b_wl_l<93> b_wl_l<92> b_wl_l<91> b_wl_l<90> b_wl_l<89> b_wl_l<88> b_wl_l<87> b_wl_l<86> b_wl_l<85> b_wl_l<84> b_wl_l<83> b_wl_l<82> b_wl_l<81> b_wl_l<80> VDD! VSS! / RM_IHPSG13_512x32_c2_2P_WLDRV16X4 +XB_WLDRV<4> b_wi<79> b_wi<78> b_wi<77> b_wi<76> b_wi<75> b_wi<74> b_wi<73> b_wi<72> b_wi<71> b_wi<70> b_wi<69> b_wi<68> b_wi<67> b_wi<66> b_wi<65> b_wi<64> b_wl_l<79> b_wl_l<78> b_wl_l<77> b_wl_l<76> b_wl_l<75> b_wl_l<74> b_wl_l<73> b_wl_l<72> b_wl_l<71> b_wl_l<70> b_wl_l<69> b_wl_l<68> b_wl_l<67> b_wl_l<66> b_wl_l<65> b_wl_l<64> VDD! VSS! / RM_IHPSG13_512x32_c2_2P_WLDRV16X4 +XB_WLDRV<3> b_wi<63> b_wi<62> b_wi<61> b_wi<60> b_wi<59> b_wi<58> b_wi<57> b_wi<56> b_wi<55> b_wi<54> b_wi<53> b_wi<52> b_wi<51> b_wi<50> b_wi<49> b_wi<48> b_wl_l<63> b_wl_l<62> b_wl_l<61> b_wl_l<60> b_wl_l<59> b_wl_l<58> b_wl_l<57> b_wl_l<56> b_wl_l<55> b_wl_l<54> b_wl_l<53> b_wl_l<52> b_wl_l<51> b_wl_l<50> b_wl_l<49> b_wl_l<48> VDD! VSS! / RM_IHPSG13_512x32_c2_2P_WLDRV16X4 +XB_WLDRV<2> b_wi<47> b_wi<46> b_wi<45> b_wi<44> b_wi<43> b_wi<42> b_wi<41> b_wi<40> b_wi<39> b_wi<38> b_wi<37> b_wi<36> b_wi<35> b_wi<34> b_wi<33> b_wi<32> b_wl_l<47> b_wl_l<46> b_wl_l<45> b_wl_l<44> b_wl_l<43> b_wl_l<42> b_wl_l<41> b_wl_l<40> b_wl_l<39> b_wl_l<38> b_wl_l<37> b_wl_l<36> b_wl_l<35> b_wl_l<34> b_wl_l<33> b_wl_l<32> VDD! VSS! / RM_IHPSG13_512x32_c2_2P_WLDRV16X4 +XB_WLDRV<1> b_wi<31> b_wi<30> b_wi<29> b_wi<28> b_wi<27> b_wi<26> b_wi<25> b_wi<24> b_wi<23> b_wi<22> b_wi<21> b_wi<20> b_wi<19> b_wi<18> b_wi<17> b_wi<16> b_wl_l<31> b_wl_l<30> b_wl_l<29> b_wl_l<28> b_wl_l<27> b_wl_l<26> b_wl_l<25> b_wl_l<24> b_wl_l<23> b_wl_l<22> b_wl_l<21> b_wl_l<20> b_wl_l<19> b_wl_l<18> b_wl_l<17> b_wl_l<16> VDD! VSS! / RM_IHPSG13_512x32_c2_2P_WLDRV16X4 +XB_WLDRV<0> b_wi<15> b_wi<14> b_wi<13> b_wi<12> b_wi<11> b_wi<10> b_wi<9> b_wi<8> b_wi<7> b_wi<6> b_wi<5> b_wi<4> b_wi<3> b_wi<2> b_wi<1> b_wi<0> b_wl_l<15> b_wl_l<14> b_wl_l<13> b_wl_l<12> b_wl_l<11> b_wl_l<10> b_wl_l<9> b_wl_l<8> b_wl_l<7> b_wl_l<6> b_wl_l<5> b_wl_l<4> b_wl_l<3> b_wl_l<2> b_wl_l<1> b_wl_l<0> VDD! VSS! / RM_IHPSG13_512x32_c2_2P_WLDRV16X4 +XA_WLDRV<15> a_wi<127> a_wi<126> a_wi<125> a_wi<124> a_wi<123> a_wi<122> a_wi<121> a_wi<120> a_wi<119> a_wi<118> a_wi<117> a_wi<116> a_wi<115> a_wi<114> a_wi<113> a_wi<112> a_wl_r<127> a_wl_r<126> a_wl_r<125> a_wl_r<124> a_wl_r<123> a_wl_r<122> a_wl_r<121> a_wl_r<120> a_wl_r<119> a_wl_r<118> a_wl_r<117> a_wl_r<116> a_wl_r<115> a_wl_r<114> a_wl_r<113> a_wl_r<112> VDD! VSS! / RM_IHPSG13_512x32_c2_2P_WLDRV16X4 +XA_WLDRV<14> a_wi<111> a_wi<110> a_wi<109> a_wi<108> a_wi<107> a_wi<106> a_wi<105> a_wi<104> a_wi<103> a_wi<102> a_wi<101> a_wi<100> a_wi<99> a_wi<98> a_wi<97> a_wi<96> a_wl_r<111> a_wl_r<110> a_wl_r<109> a_wl_r<108> a_wl_r<107> a_wl_r<106> a_wl_r<105> a_wl_r<104> a_wl_r<103> a_wl_r<102> a_wl_r<101> a_wl_r<100> a_wl_r<99> a_wl_r<98> a_wl_r<97> a_wl_r<96> VDD! VSS! / RM_IHPSG13_512x32_c2_2P_WLDRV16X4 +XA_WLDRV<13> a_wi<95> a_wi<94> a_wi<93> a_wi<92> a_wi<91> a_wi<90> a_wi<89> a_wi<88> a_wi<87> a_wi<86> a_wi<85> a_wi<84> a_wi<83> a_wi<82> a_wi<81> a_wi<80> a_wl_r<95> a_wl_r<94> a_wl_r<93> a_wl_r<92> a_wl_r<91> a_wl_r<90> a_wl_r<89> a_wl_r<88> a_wl_r<87> a_wl_r<86> a_wl_r<85> a_wl_r<84> a_wl_r<83> a_wl_r<82> a_wl_r<81> a_wl_r<80> VDD! VSS! / RM_IHPSG13_512x32_c2_2P_WLDRV16X4 +XA_WLDRV<12> a_wi<79> a_wi<78> a_wi<77> a_wi<76> a_wi<75> a_wi<74> a_wi<73> a_wi<72> a_wi<71> a_wi<70> a_wi<69> a_wi<68> a_wi<67> a_wi<66> a_wi<65> a_wi<64> a_wl_r<79> a_wl_r<78> a_wl_r<77> a_wl_r<76> a_wl_r<75> a_wl_r<74> a_wl_r<73> a_wl_r<72> a_wl_r<71> a_wl_r<70> a_wl_r<69> a_wl_r<68> a_wl_r<67> a_wl_r<66> a_wl_r<65> a_wl_r<64> VDD! VSS! / RM_IHPSG13_512x32_c2_2P_WLDRV16X4 +XA_WLDRV<11> a_wi<63> a_wi<62> a_wi<61> a_wi<60> a_wi<59> a_wi<58> a_wi<57> a_wi<56> a_wi<55> a_wi<54> a_wi<53> a_wi<52> a_wi<51> a_wi<50> a_wi<49> a_wi<48> a_wl_r<63> a_wl_r<62> a_wl_r<61> a_wl_r<60> a_wl_r<59> a_wl_r<58> a_wl_r<57> a_wl_r<56> a_wl_r<55> a_wl_r<54> a_wl_r<53> a_wl_r<52> a_wl_r<51> a_wl_r<50> a_wl_r<49> a_wl_r<48> VDD! VSS! / RM_IHPSG13_512x32_c2_2P_WLDRV16X4 +XA_WLDRV<10> a_wi<47> a_wi<46> a_wi<45> a_wi<44> a_wi<43> a_wi<42> a_wi<41> a_wi<40> a_wi<39> a_wi<38> a_wi<37> a_wi<36> a_wi<35> a_wi<34> a_wi<33> a_wi<32> a_wl_r<47> a_wl_r<46> a_wl_r<45> a_wl_r<44> a_wl_r<43> a_wl_r<42> a_wl_r<41> a_wl_r<40> a_wl_r<39> a_wl_r<38> a_wl_r<37> a_wl_r<36> a_wl_r<35> a_wl_r<34> a_wl_r<33> a_wl_r<32> VDD! VSS! / RM_IHPSG13_512x32_c2_2P_WLDRV16X4 +XA_WLDRV<9> a_wi<31> a_wi<30> a_wi<29> a_wi<28> a_wi<27> a_wi<26> a_wi<25> a_wi<24> a_wi<23> a_wi<22> a_wi<21> a_wi<20> a_wi<19> a_wi<18> a_wi<17> a_wi<16> a_wl_r<31> a_wl_r<30> a_wl_r<29> a_wl_r<28> a_wl_r<27> a_wl_r<26> a_wl_r<25> a_wl_r<24> a_wl_r<23> a_wl_r<22> a_wl_r<21> a_wl_r<20> a_wl_r<19> a_wl_r<18> a_wl_r<17> a_wl_r<16> VDD! VSS! / RM_IHPSG13_512x32_c2_2P_WLDRV16X4 +XA_WLDRV<8> a_wi<15> a_wi<14> a_wi<13> a_wi<12> a_wi<11> a_wi<10> a_wi<9> a_wi<8> a_wi<7> a_wi<6> a_wi<5> a_wi<4> a_wi<3> a_wi<2> a_wi<1> a_wi<0> a_wl_r<15> a_wl_r<14> a_wl_r<13> a_wl_r<12> a_wl_r<11> a_wl_r<10> a_wl_r<9> a_wl_r<8> a_wl_r<7> a_wl_r<6> a_wl_r<5> a_wl_r<4> a_wl_r<3> a_wl_r<2> a_wl_r<1> a_wl_r<0> VDD! VSS! / RM_IHPSG13_512x32_c2_2P_WLDRV16X4 +XA_WLDRV<7> a_wi<127> a_wi<126> a_wi<125> a_wi<124> a_wi<123> a_wi<122> a_wi<121> a_wi<120> a_wi<119> a_wi<118> a_wi<117> a_wi<116> a_wi<115> a_wi<114> a_wi<113> a_wi<112> a_wl_l<127> a_wl_l<126> a_wl_l<125> a_wl_l<124> a_wl_l<123> a_wl_l<122> a_wl_l<121> a_wl_l<120> a_wl_l<119> a_wl_l<118> a_wl_l<117> a_wl_l<116> a_wl_l<115> a_wl_l<114> a_wl_l<113> a_wl_l<112> VDD! VSS! / RM_IHPSG13_512x32_c2_2P_WLDRV16X4 +XA_WLDRV<6> a_wi<111> a_wi<110> a_wi<109> a_wi<108> a_wi<107> a_wi<106> a_wi<105> a_wi<104> a_wi<103> a_wi<102> a_wi<101> a_wi<100> a_wi<99> a_wi<98> a_wi<97> a_wi<96> a_wl_l<111> a_wl_l<110> a_wl_l<109> a_wl_l<108> a_wl_l<107> a_wl_l<106> a_wl_l<105> a_wl_l<104> a_wl_l<103> a_wl_l<102> a_wl_l<101> a_wl_l<100> a_wl_l<99> a_wl_l<98> a_wl_l<97> a_wl_l<96> VDD! VSS! / RM_IHPSG13_512x32_c2_2P_WLDRV16X4 +XA_WLDRV<5> a_wi<95> a_wi<94> a_wi<93> a_wi<92> a_wi<91> a_wi<90> a_wi<89> a_wi<88> a_wi<87> a_wi<86> a_wi<85> a_wi<84> a_wi<83> a_wi<82> a_wi<81> a_wi<80> a_wl_l<95> a_wl_l<94> a_wl_l<93> a_wl_l<92> a_wl_l<91> a_wl_l<90> a_wl_l<89> a_wl_l<88> a_wl_l<87> a_wl_l<86> a_wl_l<85> a_wl_l<84> a_wl_l<83> a_wl_l<82> a_wl_l<81> a_wl_l<80> VDD! VSS! / RM_IHPSG13_512x32_c2_2P_WLDRV16X4 +XA_WLDRV<4> a_wi<79> a_wi<78> a_wi<77> a_wi<76> a_wi<75> a_wi<74> a_wi<73> a_wi<72> a_wi<71> a_wi<70> a_wi<69> a_wi<68> a_wi<67> a_wi<66> a_wi<65> a_wi<64> a_wl_l<79> a_wl_l<78> a_wl_l<77> a_wl_l<76> a_wl_l<75> a_wl_l<74> a_wl_l<73> a_wl_l<72> a_wl_l<71> a_wl_l<70> a_wl_l<69> a_wl_l<68> a_wl_l<67> a_wl_l<66> a_wl_l<65> a_wl_l<64> VDD! VSS! / RM_IHPSG13_512x32_c2_2P_WLDRV16X4 +XA_WLDRV<3> a_wi<63> a_wi<62> a_wi<61> a_wi<60> a_wi<59> a_wi<58> a_wi<57> a_wi<56> a_wi<55> a_wi<54> a_wi<53> a_wi<52> a_wi<51> a_wi<50> a_wi<49> a_wi<48> a_wl_l<63> a_wl_l<62> a_wl_l<61> a_wl_l<60> a_wl_l<59> a_wl_l<58> a_wl_l<57> a_wl_l<56> a_wl_l<55> a_wl_l<54> a_wl_l<53> a_wl_l<52> a_wl_l<51> a_wl_l<50> a_wl_l<49> a_wl_l<48> VDD! VSS! / RM_IHPSG13_512x32_c2_2P_WLDRV16X4 +XA_WLDRV<2> a_wi<47> a_wi<46> a_wi<45> a_wi<44> a_wi<43> a_wi<42> a_wi<41> a_wi<40> a_wi<39> a_wi<38> a_wi<37> a_wi<36> a_wi<35> a_wi<34> a_wi<33> a_wi<32> a_wl_l<47> a_wl_l<46> a_wl_l<45> a_wl_l<44> a_wl_l<43> a_wl_l<42> a_wl_l<41> a_wl_l<40> a_wl_l<39> a_wl_l<38> a_wl_l<37> a_wl_l<36> a_wl_l<35> a_wl_l<34> a_wl_l<33> a_wl_l<32> VDD! VSS! / RM_IHPSG13_512x32_c2_2P_WLDRV16X4 +XA_WLDRV<1> a_wi<31> a_wi<30> a_wi<29> a_wi<28> a_wi<27> a_wi<26> a_wi<25> a_wi<24> a_wi<23> a_wi<22> a_wi<21> a_wi<20> a_wi<19> a_wi<18> a_wi<17> a_wi<16> a_wl_l<31> a_wl_l<30> a_wl_l<29> a_wl_l<28> a_wl_l<27> a_wl_l<26> a_wl_l<25> a_wl_l<24> a_wl_l<23> a_wl_l<22> a_wl_l<21> a_wl_l<20> a_wl_l<19> a_wl_l<18> a_wl_l<17> a_wl_l<16> VDD! VSS! / RM_IHPSG13_512x32_c2_2P_WLDRV16X4 +XA_WLDRV<0> a_wi<15> a_wi<14> a_wi<13> a_wi<12> a_wi<11> a_wi<10> a_wi<9> a_wi<8> a_wi<7> a_wi<6> a_wi<5> a_wi<4> a_wi<3> a_wi<2> a_wi<1> a_wi<0> a_wl_l<15> a_wl_l<14> a_wl_l<13> a_wl_l<12> a_wl_l<11> a_wl_l<10> a_wl_l<9> a_wl_l<8> a_wl_l<7> a_wl_l<6> a_wl_l<5> a_wl_l<4> a_wl_l<3> a_wl_l<2> a_wl_l<1> a_wl_l<0> VDD! VSS! / RM_IHPSG13_512x32_c2_2P_WLDRV16X4 + + +XB_CTRL b_aclk_n B_BIST_CLK B_BIST_MEN B_BIST_EN B_BIST_REN B_BIST_WEN b_tiel B_CLK B_MEN b_dclk b_eclk b_pulse_h b_pulse_l b_pulse b_rclk B_REN b_cs b_wclk B_WEN VDD! VSS! / RM_IHPSG13_512x32_c2_2P_CTRL +XA_CTRL a_aclk_n A_BIST_CLK A_BIST_MEN A_BIST_EN A_BIST_REN A_BIST_WEN a_tiel A_CLK A_MEN a_dclk a_eclk a_pulse_h a_pulse_l a_pulse a_rclk A_REN a_cs a_wclk A_WEN VDD! VSS! / RM_IHPSG13_512x32_c2_2P_CTRL + + +XB_ROWDEC b_addr_row<6> b_addr_row<5> b_addr_row<4> b_addr_row<3> b_addr_row<2> b_addr_row<1> b_addr_row<0> b_cs b_eclk b_wi<127> b_wi<126> b_wi<125> b_wi<124> b_wi<123> b_wi<122> b_wi<121> b_wi<120> b_wi<119> b_wi<118> b_wi<117> b_wi<116> b_wi<115> b_wi<114> b_wi<113> b_wi<112> b_wi<111> b_wi<110> b_wi<109> b_wi<108> b_wi<107> b_wi<106> b_wi<105> b_wi<104> b_wi<103> b_wi<102> b_wi<101> b_wi<100> b_wi<99> b_wi<98> b_wi<97> b_wi<96> b_wi<95> b_wi<94> b_wi<93> b_wi<92> b_wi<91> b_wi<90> b_wi<89> b_wi<88> b_wi<87> b_wi<86> b_wi<85> b_wi<84> b_wi<83> b_wi<82> b_wi<81> b_wi<80> b_wi<79> b_wi<78> b_wi<77> b_wi<76> b_wi<75> b_wi<74> b_wi<73> b_wi<72> b_wi<71> b_wi<70> b_wi<69> b_wi<68> b_wi<67> b_wi<66> b_wi<65> b_wi<64> b_wi<63> b_wi<62> b_wi<61> b_wi<60> b_wi<59> b_wi<58> b_wi<57> b_wi<56> b_wi<55> b_wi<54> b_wi<53> b_wi<52> b_wi<51> b_wi<50> b_wi<49> b_wi<48> b_wi<47> b_wi<46> b_wi<45> b_wi<44> b_wi<43> b_wi<42> b_wi<41> b_wi<40> b_wi<39> b_wi<38> b_wi<37> b_wi<36> b_wi<35> b_wi<34> b_wi<33> b_wi<32> b_wi<31> b_wi<30> b_wi<29> b_wi<28> b_wi<27> b_wi<26> b_wi<25> b_wi<24> b_wi<23> b_wi<22> b_wi<21> b_wi<20> b_wi<19> b_wi<18> b_wi<17> b_wi<16> b_wi<15> b_wi<14> b_wi<13> b_wi<12> b_wi<11> b_wi<10> b_wi<9> b_wi<8> b_wi<7> b_wi<6> b_wi<5> b_wi<4> b_wi<3> b_wi<2> b_wi<1> b_wi<0> VDD! VSS! / RM_IHPSG13_512x32_c2_2P_ROWDEC7 +XA_ROWDEC a_addr_row<6> a_addr_row<5> a_addr_row<4> a_addr_row<3> a_addr_row<2> a_addr_row<1> a_addr_row<0> a_cs a_eclk a_wi<127> a_wi<126> a_wi<125> a_wi<124> a_wi<123> a_wi<122> a_wi<121> a_wi<120> a_wi<119> a_wi<118> a_wi<117> a_wi<116> a_wi<115> a_wi<114> a_wi<113> a_wi<112> a_wi<111> a_wi<110> a_wi<109> a_wi<108> a_wi<107> a_wi<106> a_wi<105> a_wi<104> a_wi<103> a_wi<102> a_wi<101> a_wi<100> a_wi<99> a_wi<98> a_wi<97> a_wi<96> a_wi<95> a_wi<94> a_wi<93> a_wi<92> a_wi<91> a_wi<90> a_wi<89> a_wi<88> a_wi<87> a_wi<86> a_wi<85> a_wi<84> a_wi<83> a_wi<82> a_wi<81> a_wi<80> a_wi<79> a_wi<78> a_wi<77> a_wi<76> a_wi<75> a_wi<74> a_wi<73> a_wi<72> a_wi<71> a_wi<70> a_wi<69> a_wi<68> a_wi<67> a_wi<66> a_wi<65> a_wi<64> a_wi<63> a_wi<62> a_wi<61> a_wi<60> a_wi<59> a_wi<58> a_wi<57> a_wi<56> a_wi<55> a_wi<54> a_wi<53> a_wi<52> a_wi<51> a_wi<50> a_wi<49> a_wi<48> a_wi<47> a_wi<46> a_wi<45> a_wi<44> a_wi<43> a_wi<42> a_wi<41> a_wi<40> a_wi<39> a_wi<38> a_wi<37> a_wi<36> a_wi<35> a_wi<34> a_wi<33> a_wi<32> a_wi<31> a_wi<30> a_wi<29> a_wi<28> a_wi<27> a_wi<26> a_wi<25> a_wi<24> a_wi<23> a_wi<22> a_wi<21> a_wi<20> a_wi<19> a_wi<18> a_wi<17> a_wi<16> a_wi<15> a_wi<14> a_wi<13> a_wi<12> a_wi<11> a_wi<10> a_wi<9> a_wi<8> a_wi<7> a_wi<6> a_wi<5> a_wi<4> a_wi<3> a_wi<2> a_wi<1> a_wi<0> VDD! VSS! / RM_IHPSG13_512x32_c2_2P_ROWDEC7 +XB_ROWREG b_aclk_n B_ADDR<8> B_ADDR<7> B_ADDR<6> B_ADDR<5> B_ADDR<4> B_ADDR<3> B_ADDR<2> b_addr_row<6> b_addr_row<5> b_addr_row<4> b_addr_row<3> b_addr_row<2> b_addr_row<1> b_addr_row<0> B_BIST_ADDR<8> B_BIST_ADDR<7> B_BIST_ADDR<6> B_BIST_ADDR<5> B_BIST_ADDR<4> B_BIST_ADDR<3> B_BIST_ADDR<2> B_BIST_EN VDD! VSS! / RM_IHPSG13_512x32_c2_2P_ROWREG7 +XA_ROWREG a_aclk_n A_ADDR<8> A_ADDR<7> A_ADDR<6> A_ADDR<5> A_ADDR<4> A_ADDR<3> A_ADDR<2> a_addr_row<6> a_addr_row<5> a_addr_row<4> a_addr_row<3> a_addr_row<2> a_addr_row<1> a_addr_row<0> A_BIST_ADDR<8> A_BIST_ADDR<7> A_BIST_ADDR<6> A_BIST_ADDR<5> A_BIST_ADDR<4> A_BIST_ADDR<3> A_BIST_ADDR<2> A_BIST_EN VDD! VSS! / RM_IHPSG13_512x32_c2_2P_ROWREG7 +XB_COLDEC b_aclk_n B_ADDR<1> B_ADDR<0> b_addr_col<1> b_addr_col<0> b_addr_dec<7> b_addr_dec<6> b_addr_dec<5> b_addr_dec<4> b_addr_dec<3> b_addr_dec<2> b_addr_dec<1> b_addr_dec<0> B_BIST_ADDR<1> B_BIST_ADDR<0> B_BIST_EN VDD! VSS! / RM_IHPSG13_512x32_c2_2P_COLDEC2 +XA_COLDEC a_aclk_n A_ADDR<1> A_ADDR<0> a_addr_col<1> a_addr_col<0> a_addr_dec<7> a_addr_dec<6> a_addr_dec<5> a_addr_dec<4> a_addr_dec<3> a_addr_dec<2> a_addr_dec<1> a_addr_dec<0> A_BIST_ADDR<1> A_BIST_ADDR<0> A_BIST_EN VDD! VSS! / RM_IHPSG13_512x32_c2_2P_COLDEC2 + + +XB_DLYH b_pulse b_pulse_h VDD! VSS! / RM_IHPSG13_512x32_c2_2P_DLY_pcell_2 +XB_DLYL b_pulse_x b_pulse_l VDD! VSS! / RM_IHPSG13_512x32_c2_2P_DLY_pcell_3 +XA_DLYH a_pulse a_pulse_h VDD! VSS! / RM_IHPSG13_512x32_c2_2P_DLY_pcell_2 +XA_DLYL a_pulse_x a_pulse_l VDD! VSS! / RM_IHPSG13_512x32_c2_2P_DLY_pcell_3 +XB_DLYMUX b_pulse_h B_DLY b_pulse_x VDD! VSS! / RM_IHPSG13_512x32_c2_2P_DLY_MUX +XA_DLYMUX a_pulse_h A_DLY a_pulse_x VDD! VSS! / RM_IHPSG13_512x32_c2_2P_DLY_MUX + +XCOLCTRL<31> a_addr_dec_r<3> a_addr_dec_r<2> a_addr_dec_r<1> a_addr_dec_r<0> A_BIST_BM<31> A_BIST_DIN<31> A_BIST_EN a_blc_r<63> a_blc_r<62> a_blc_r<61> a_blc_r<60> a_blt_r<63> a_blt_r<62> a_blt_r<61> a_blt_r<60> A_BM<31> a_dclk_n_r<15> a_dclk_n_r<16> a_dclk_p_r<15> a_dclk_p_r<16> A_DOUT<31> A_DIN<31> a_rclk_n_r<15> a_rclk_n_r<16> a_rclk_p_r<15> a_rclk_p_r<16> a_tieh<31> a_wclk_n_r<15> a_wclk_n_r<16> a_wclk_p_r<15> a_wclk_p_r<16> b_addr_dec_r<3> b_addr_dec_r<2> b_addr_dec_r<1> b_addr_dec_r<0> B_BIST_BM<31> B_BIST_DIN<31> B_BIST_EN b_blc_r<63> b_blc_r<62> b_blc_r<61> b_blc_r<60> b_blt_r<63> b_blt_r<62> b_blt_r<61> b_blt_r<60> B_BM<31> b_dclk_n_r<15> b_dclk_n_r<16> b_dclk_p_r<15> b_dclk_p_r<16> B_DOUT<31> B_DIN<31> b_rclk_n_r<15> b_rclk_n_r<16> b_rclk_p_r<15> b_rclk_p_r<16> b_tieh<31> b_wclk_n_r<15> b_wclk_n_r<16> b_wclk_p_r<15> b_wclk_p_r<16> VDD! VSS! / RM_IHPSG13_512x32_c2_2P_COLCTRL2 +XCOLCTRL<30> a_addr_dec_r<3> a_addr_dec_r<2> a_addr_dec_r<1> a_addr_dec_r<0> A_BIST_BM<30> A_BIST_DIN<30> A_BIST_EN a_blc_r<59> a_blc_r<58> a_blc_r<57> a_blc_r<56> a_blt_r<59> a_blt_r<58> a_blt_r<57> a_blt_r<56> A_BM<30> a_dclk_n_r<14> a_dclk_n_r<15> a_dclk_p_r<14> a_dclk_p_r<15> A_DOUT<30> A_DIN<30> a_rclk_n_r<14> a_rclk_n_r<15> a_rclk_p_r<14> a_rclk_p_r<15> a_tieh<30> a_wclk_n_r<14> a_wclk_n_r<15> a_wclk_p_r<14> a_wclk_p_r<15> b_addr_dec_r<3> b_addr_dec_r<2> b_addr_dec_r<1> b_addr_dec_r<0> B_BIST_BM<30> B_BIST_DIN<30> B_BIST_EN b_blc_r<59> b_blc_r<58> b_blc_r<57> b_blc_r<56> b_blt_r<59> b_blt_r<58> b_blt_r<57> b_blt_r<56> B_BM<30> b_dclk_n_r<14> b_dclk_n_r<15> b_dclk_p_r<14> b_dclk_p_r<15> B_DOUT<30> B_DIN<30> b_rclk_n_r<14> b_rclk_n_r<15> b_rclk_p_r<14> b_rclk_p_r<15> b_tieh<30> b_wclk_n_r<14> b_wclk_n_r<15> b_wclk_p_r<14> b_wclk_p_r<15> VDD! VSS! / RM_IHPSG13_512x32_c2_2P_COLCTRL2 +XCOLCTRL<29> a_addr_dec_r<3> a_addr_dec_r<2> a_addr_dec_r<1> a_addr_dec_r<0> A_BIST_BM<29> A_BIST_DIN<29> A_BIST_EN a_blc_r<55> a_blc_r<54> a_blc_r<53> a_blc_r<52> a_blt_r<55> a_blt_r<54> a_blt_r<53> a_blt_r<52> A_BM<29> a_dclk_n_r<13> a_dclk_n_r<14> a_dclk_p_r<13> a_dclk_p_r<14> A_DOUT<29> A_DIN<29> a_rclk_n_r<13> a_rclk_n_r<14> a_rclk_p_r<13> a_rclk_p_r<14> a_tieh<29> a_wclk_n_r<13> a_wclk_n_r<14> a_wclk_p_r<13> a_wclk_p_r<14> b_addr_dec_r<3> b_addr_dec_r<2> b_addr_dec_r<1> b_addr_dec_r<0> B_BIST_BM<29> B_BIST_DIN<29> B_BIST_EN b_blc_r<55> b_blc_r<54> b_blc_r<53> b_blc_r<52> b_blt_r<55> b_blt_r<54> b_blt_r<53> b_blt_r<52> B_BM<29> b_dclk_n_r<13> b_dclk_n_r<14> b_dclk_p_r<13> b_dclk_p_r<14> B_DOUT<29> B_DIN<29> b_rclk_n_r<13> b_rclk_n_r<14> b_rclk_p_r<13> b_rclk_p_r<14> b_tieh<29> b_wclk_n_r<13> b_wclk_n_r<14> b_wclk_p_r<13> b_wclk_p_r<14> VDD! VSS! / RM_IHPSG13_512x32_c2_2P_COLCTRL2 +XCOLCTRL<28> a_addr_dec_r<3> a_addr_dec_r<2> a_addr_dec_r<1> a_addr_dec_r<0> A_BIST_BM<28> A_BIST_DIN<28> A_BIST_EN a_blc_r<51> a_blc_r<50> a_blc_r<49> a_blc_r<48> a_blt_r<51> a_blt_r<50> a_blt_r<49> a_blt_r<48> A_BM<28> a_dclk_n_r<12> a_dclk_n_r<13> a_dclk_p_r<12> a_dclk_p_r<13> A_DOUT<28> A_DIN<28> a_rclk_n_r<12> a_rclk_n_r<13> a_rclk_p_r<12> a_rclk_p_r<13> a_tieh<28> a_wclk_n_r<12> a_wclk_n_r<13> a_wclk_p_r<12> a_wclk_p_r<13> b_addr_dec_r<3> b_addr_dec_r<2> b_addr_dec_r<1> b_addr_dec_r<0> B_BIST_BM<28> B_BIST_DIN<28> B_BIST_EN b_blc_r<51> b_blc_r<50> b_blc_r<49> b_blc_r<48> b_blt_r<51> b_blt_r<50> b_blt_r<49> b_blt_r<48> B_BM<28> b_dclk_n_r<12> b_dclk_n_r<13> b_dclk_p_r<12> b_dclk_p_r<13> B_DOUT<28> B_DIN<28> b_rclk_n_r<12> b_rclk_n_r<13> b_rclk_p_r<12> b_rclk_p_r<13> b_tieh<28> b_wclk_n_r<12> b_wclk_n_r<13> b_wclk_p_r<12> b_wclk_p_r<13> VDD! VSS! / RM_IHPSG13_512x32_c2_2P_COLCTRL2 +XCOLCTRL<27> a_addr_dec_r<3> a_addr_dec_r<2> a_addr_dec_r<1> a_addr_dec_r<0> A_BIST_BM<27> A_BIST_DIN<27> A_BIST_EN a_blc_r<47> a_blc_r<46> a_blc_r<45> a_blc_r<44> a_blt_r<47> a_blt_r<46> a_blt_r<45> a_blt_r<44> A_BM<27> a_dclk_n_r<11> a_dclk_n_r<12> a_dclk_p_r<11> a_dclk_p_r<12> A_DOUT<27> A_DIN<27> a_rclk_n_r<11> a_rclk_n_r<12> a_rclk_p_r<11> a_rclk_p_r<12> a_tieh<27> a_wclk_n_r<11> a_wclk_n_r<12> a_wclk_p_r<11> a_wclk_p_r<12> b_addr_dec_r<3> b_addr_dec_r<2> b_addr_dec_r<1> b_addr_dec_r<0> B_BIST_BM<27> B_BIST_DIN<27> B_BIST_EN b_blc_r<47> b_blc_r<46> b_blc_r<45> b_blc_r<44> b_blt_r<47> b_blt_r<46> b_blt_r<45> b_blt_r<44> B_BM<27> b_dclk_n_r<11> b_dclk_n_r<12> b_dclk_p_r<11> b_dclk_p_r<12> B_DOUT<27> B_DIN<27> b_rclk_n_r<11> b_rclk_n_r<12> b_rclk_p_r<11> b_rclk_p_r<12> b_tieh<27> b_wclk_n_r<11> b_wclk_n_r<12> b_wclk_p_r<11> b_wclk_p_r<12> VDD! VSS! / RM_IHPSG13_512x32_c2_2P_COLCTRL2 +XCOLCTRL<26> a_addr_dec_r<3> a_addr_dec_r<2> a_addr_dec_r<1> a_addr_dec_r<0> A_BIST_BM<26> A_BIST_DIN<26> A_BIST_EN a_blc_r<43> a_blc_r<42> a_blc_r<41> a_blc_r<40> a_blt_r<43> a_blt_r<42> a_blt_r<41> a_blt_r<40> A_BM<26> a_dclk_n_r<10> a_dclk_n_r<11> a_dclk_p_r<10> a_dclk_p_r<11> A_DOUT<26> A_DIN<26> a_rclk_n_r<10> a_rclk_n_r<11> a_rclk_p_r<10> a_rclk_p_r<11> a_tieh<26> a_wclk_n_r<10> a_wclk_n_r<11> a_wclk_p_r<10> a_wclk_p_r<11> b_addr_dec_r<3> b_addr_dec_r<2> b_addr_dec_r<1> b_addr_dec_r<0> B_BIST_BM<26> B_BIST_DIN<26> B_BIST_EN b_blc_r<43> b_blc_r<42> b_blc_r<41> b_blc_r<40> b_blt_r<43> b_blt_r<42> b_blt_r<41> b_blt_r<40> B_BM<26> b_dclk_n_r<10> b_dclk_n_r<11> b_dclk_p_r<10> b_dclk_p_r<11> B_DOUT<26> B_DIN<26> b_rclk_n_r<10> b_rclk_n_r<11> b_rclk_p_r<10> b_rclk_p_r<11> b_tieh<26> b_wclk_n_r<10> b_wclk_n_r<11> b_wclk_p_r<10> b_wclk_p_r<11> VDD! VSS! / RM_IHPSG13_512x32_c2_2P_COLCTRL2 +XCOLCTRL<25> a_addr_dec_r<3> a_addr_dec_r<2> a_addr_dec_r<1> a_addr_dec_r<0> A_BIST_BM<25> A_BIST_DIN<25> A_BIST_EN a_blc_r<39> a_blc_r<38> a_blc_r<37> a_blc_r<36> a_blt_r<39> a_blt_r<38> a_blt_r<37> a_blt_r<36> A_BM<25> a_dclk_n_r<9> a_dclk_n_r<10> a_dclk_p_r<9> a_dclk_p_r<10> A_DOUT<25> A_DIN<25> a_rclk_n_r<9> a_rclk_n_r<10> a_rclk_p_r<9> a_rclk_p_r<10> a_tieh<25> a_wclk_n_r<9> a_wclk_n_r<10> a_wclk_p_r<9> a_wclk_p_r<10> b_addr_dec_r<3> b_addr_dec_r<2> b_addr_dec_r<1> b_addr_dec_r<0> B_BIST_BM<25> B_BIST_DIN<25> B_BIST_EN b_blc_r<39> b_blc_r<38> b_blc_r<37> b_blc_r<36> b_blt_r<39> b_blt_r<38> b_blt_r<37> b_blt_r<36> B_BM<25> b_dclk_n_r<9> b_dclk_n_r<10> b_dclk_p_r<9> b_dclk_p_r<10> B_DOUT<25> B_DIN<25> b_rclk_n_r<9> b_rclk_n_r<10> b_rclk_p_r<9> b_rclk_p_r<10> b_tieh<25> b_wclk_n_r<9> b_wclk_n_r<10> b_wclk_p_r<9> b_wclk_p_r<10> VDD! VSS! / RM_IHPSG13_512x32_c2_2P_COLCTRL2 +XCOLCTRL<24> a_addr_dec_r<3> a_addr_dec_r<2> a_addr_dec_r<1> a_addr_dec_r<0> A_BIST_BM<24> A_BIST_DIN<24> A_BIST_EN a_blc_r<35> a_blc_r<34> a_blc_r<33> a_blc_r<32> a_blt_r<35> a_blt_r<34> a_blt_r<33> a_blt_r<32> A_BM<24> a_dclk_n_r<8> a_dclk_n_r<9> a_dclk_p_r<8> a_dclk_p_r<9> A_DOUT<24> A_DIN<24> a_rclk_n_r<8> a_rclk_n_r<9> a_rclk_p_r<8> a_rclk_p_r<9> a_tieh<24> a_wclk_n_r<8> a_wclk_n_r<9> a_wclk_p_r<8> a_wclk_p_r<9> b_addr_dec_r<3> b_addr_dec_r<2> b_addr_dec_r<1> b_addr_dec_r<0> B_BIST_BM<24> B_BIST_DIN<24> B_BIST_EN b_blc_r<35> b_blc_r<34> b_blc_r<33> b_blc_r<32> b_blt_r<35> b_blt_r<34> b_blt_r<33> b_blt_r<32> B_BM<24> b_dclk_n_r<8> b_dclk_n_r<9> b_dclk_p_r<8> b_dclk_p_r<9> B_DOUT<24> B_DIN<24> b_rclk_n_r<8> b_rclk_n_r<9> b_rclk_p_r<8> b_rclk_p_r<9> b_tieh<24> b_wclk_n_r<8> b_wclk_n_r<9> b_wclk_p_r<8> b_wclk_p_r<9> VDD! VSS! / RM_IHPSG13_512x32_c2_2P_COLCTRL2 +XCOLCTRL<23> a_addr_dec_r<3> a_addr_dec_r<2> a_addr_dec_r<1> a_addr_dec_r<0> A_BIST_BM<23> A_BIST_DIN<23> A_BIST_EN a_blc_r<31> a_blc_r<30> a_blc_r<29> a_blc_r<28> a_blt_r<31> a_blt_r<30> a_blt_r<29> a_blt_r<28> A_BM<23> a_dclk_n_r<7> a_dclk_n_r<8> a_dclk_p_r<7> a_dclk_p_r<8> A_DOUT<23> A_DIN<23> a_rclk_n_r<7> a_rclk_n_r<8> a_rclk_p_r<7> a_rclk_p_r<8> a_tieh<23> a_wclk_n_r<7> a_wclk_n_r<8> a_wclk_p_r<7> a_wclk_p_r<8> b_addr_dec_r<3> b_addr_dec_r<2> b_addr_dec_r<1> b_addr_dec_r<0> B_BIST_BM<23> B_BIST_DIN<23> B_BIST_EN b_blc_r<31> b_blc_r<30> b_blc_r<29> b_blc_r<28> b_blt_r<31> b_blt_r<30> b_blt_r<29> b_blt_r<28> B_BM<23> b_dclk_n_r<7> b_dclk_n_r<8> b_dclk_p_r<7> b_dclk_p_r<8> B_DOUT<23> B_DIN<23> b_rclk_n_r<7> b_rclk_n_r<8> b_rclk_p_r<7> b_rclk_p_r<8> b_tieh<23> b_wclk_n_r<7> b_wclk_n_r<8> b_wclk_p_r<7> b_wclk_p_r<8> VDD! VSS! / RM_IHPSG13_512x32_c2_2P_COLCTRL2 +XCOLCTRL<22> a_addr_dec_r<3> a_addr_dec_r<2> a_addr_dec_r<1> a_addr_dec_r<0> A_BIST_BM<22> A_BIST_DIN<22> A_BIST_EN a_blc_r<27> a_blc_r<26> a_blc_r<25> a_blc_r<24> a_blt_r<27> a_blt_r<26> a_blt_r<25> a_blt_r<24> A_BM<22> a_dclk_n_r<6> a_dclk_n_r<7> a_dclk_p_r<6> a_dclk_p_r<7> A_DOUT<22> A_DIN<22> a_rclk_n_r<6> a_rclk_n_r<7> a_rclk_p_r<6> a_rclk_p_r<7> a_tieh<22> a_wclk_n_r<6> a_wclk_n_r<7> a_wclk_p_r<6> a_wclk_p_r<7> b_addr_dec_r<3> b_addr_dec_r<2> b_addr_dec_r<1> b_addr_dec_r<0> B_BIST_BM<22> B_BIST_DIN<22> B_BIST_EN b_blc_r<27> b_blc_r<26> b_blc_r<25> b_blc_r<24> b_blt_r<27> b_blt_r<26> b_blt_r<25> b_blt_r<24> B_BM<22> b_dclk_n_r<6> b_dclk_n_r<7> b_dclk_p_r<6> b_dclk_p_r<7> B_DOUT<22> B_DIN<22> b_rclk_n_r<6> b_rclk_n_r<7> b_rclk_p_r<6> b_rclk_p_r<7> b_tieh<22> b_wclk_n_r<6> b_wclk_n_r<7> b_wclk_p_r<6> b_wclk_p_r<7> VDD! VSS! / RM_IHPSG13_512x32_c2_2P_COLCTRL2 +XCOLCTRL<21> a_addr_dec_r<3> a_addr_dec_r<2> a_addr_dec_r<1> a_addr_dec_r<0> A_BIST_BM<21> A_BIST_DIN<21> A_BIST_EN a_blc_r<23> a_blc_r<22> a_blc_r<21> a_blc_r<20> a_blt_r<23> a_blt_r<22> a_blt_r<21> a_blt_r<20> A_BM<21> a_dclk_n_r<5> a_dclk_n_r<6> a_dclk_p_r<5> a_dclk_p_r<6> A_DOUT<21> A_DIN<21> a_rclk_n_r<5> a_rclk_n_r<6> a_rclk_p_r<5> a_rclk_p_r<6> a_tieh<21> a_wclk_n_r<5> a_wclk_n_r<6> a_wclk_p_r<5> a_wclk_p_r<6> b_addr_dec_r<3> b_addr_dec_r<2> b_addr_dec_r<1> b_addr_dec_r<0> B_BIST_BM<21> B_BIST_DIN<21> B_BIST_EN b_blc_r<23> b_blc_r<22> b_blc_r<21> b_blc_r<20> b_blt_r<23> b_blt_r<22> b_blt_r<21> b_blt_r<20> B_BM<21> b_dclk_n_r<5> b_dclk_n_r<6> b_dclk_p_r<5> b_dclk_p_r<6> B_DOUT<21> B_DIN<21> b_rclk_n_r<5> b_rclk_n_r<6> b_rclk_p_r<5> b_rclk_p_r<6> b_tieh<21> b_wclk_n_r<5> b_wclk_n_r<6> b_wclk_p_r<5> b_wclk_p_r<6> VDD! VSS! / RM_IHPSG13_512x32_c2_2P_COLCTRL2 +XCOLCTRL<20> a_addr_dec_r<3> a_addr_dec_r<2> a_addr_dec_r<1> a_addr_dec_r<0> A_BIST_BM<20> A_BIST_DIN<20> A_BIST_EN a_blc_r<19> a_blc_r<18> a_blc_r<17> a_blc_r<16> a_blt_r<19> a_blt_r<18> a_blt_r<17> a_blt_r<16> A_BM<20> a_dclk_n_r<4> a_dclk_n_r<5> a_dclk_p_r<4> a_dclk_p_r<5> A_DOUT<20> A_DIN<20> a_rclk_n_r<4> a_rclk_n_r<5> a_rclk_p_r<4> a_rclk_p_r<5> a_tieh<20> a_wclk_n_r<4> a_wclk_n_r<5> a_wclk_p_r<4> a_wclk_p_r<5> b_addr_dec_r<3> b_addr_dec_r<2> b_addr_dec_r<1> b_addr_dec_r<0> B_BIST_BM<20> B_BIST_DIN<20> B_BIST_EN b_blc_r<19> b_blc_r<18> b_blc_r<17> b_blc_r<16> b_blt_r<19> b_blt_r<18> b_blt_r<17> b_blt_r<16> B_BM<20> b_dclk_n_r<4> b_dclk_n_r<5> b_dclk_p_r<4> b_dclk_p_r<5> B_DOUT<20> B_DIN<20> b_rclk_n_r<4> b_rclk_n_r<5> b_rclk_p_r<4> b_rclk_p_r<5> b_tieh<20> b_wclk_n_r<4> b_wclk_n_r<5> b_wclk_p_r<4> b_wclk_p_r<5> VDD! VSS! / RM_IHPSG13_512x32_c2_2P_COLCTRL2 +XCOLCTRL<19> a_addr_dec_r<3> a_addr_dec_r<2> a_addr_dec_r<1> a_addr_dec_r<0> A_BIST_BM<19> A_BIST_DIN<19> A_BIST_EN a_blc_r<15> a_blc_r<14> a_blc_r<13> a_blc_r<12> a_blt_r<15> a_blt_r<14> a_blt_r<13> a_blt_r<12> A_BM<19> a_dclk_n_r<3> a_dclk_n_r<4> a_dclk_p_r<3> a_dclk_p_r<4> A_DOUT<19> A_DIN<19> a_rclk_n_r<3> a_rclk_n_r<4> a_rclk_p_r<3> a_rclk_p_r<4> a_tieh<19> a_wclk_n_r<3> a_wclk_n_r<4> a_wclk_p_r<3> a_wclk_p_r<4> b_addr_dec_r<3> b_addr_dec_r<2> b_addr_dec_r<1> b_addr_dec_r<0> B_BIST_BM<19> B_BIST_DIN<19> B_BIST_EN b_blc_r<15> b_blc_r<14> b_blc_r<13> b_blc_r<12> b_blt_r<15> b_blt_r<14> b_blt_r<13> b_blt_r<12> B_BM<19> b_dclk_n_r<3> b_dclk_n_r<4> b_dclk_p_r<3> b_dclk_p_r<4> B_DOUT<19> B_DIN<19> b_rclk_n_r<3> b_rclk_n_r<4> b_rclk_p_r<3> b_rclk_p_r<4> b_tieh<19> b_wclk_n_r<3> b_wclk_n_r<4> b_wclk_p_r<3> b_wclk_p_r<4> VDD! VSS! / RM_IHPSG13_512x32_c2_2P_COLCTRL2 +XCOLCTRL<18> a_addr_dec_r<3> a_addr_dec_r<2> a_addr_dec_r<1> a_addr_dec_r<0> A_BIST_BM<18> A_BIST_DIN<18> A_BIST_EN a_blc_r<11> a_blc_r<10> a_blc_r<9> a_blc_r<8> a_blt_r<11> a_blt_r<10> a_blt_r<9> a_blt_r<8> A_BM<18> a_dclk_n_r<2> a_dclk_n_r<3> a_dclk_p_r<2> a_dclk_p_r<3> A_DOUT<18> A_DIN<18> a_rclk_n_r<2> a_rclk_n_r<3> a_rclk_p_r<2> a_rclk_p_r<3> a_tieh<18> a_wclk_n_r<2> a_wclk_n_r<3> a_wclk_p_r<2> a_wclk_p_r<3> b_addr_dec_r<3> b_addr_dec_r<2> b_addr_dec_r<1> b_addr_dec_r<0> B_BIST_BM<18> B_BIST_DIN<18> B_BIST_EN b_blc_r<11> b_blc_r<10> b_blc_r<9> b_blc_r<8> b_blt_r<11> b_blt_r<10> b_blt_r<9> b_blt_r<8> B_BM<18> b_dclk_n_r<2> b_dclk_n_r<3> b_dclk_p_r<2> b_dclk_p_r<3> B_DOUT<18> B_DIN<18> b_rclk_n_r<2> b_rclk_n_r<3> b_rclk_p_r<2> b_rclk_p_r<3> b_tieh<18> b_wclk_n_r<2> b_wclk_n_r<3> b_wclk_p_r<2> b_wclk_p_r<3> VDD! VSS! / RM_IHPSG13_512x32_c2_2P_COLCTRL2 +XCOLCTRL<17> a_addr_dec_r<3> a_addr_dec_r<2> a_addr_dec_r<1> a_addr_dec_r<0> A_BIST_BM<17> A_BIST_DIN<17> A_BIST_EN a_blc_r<7> a_blc_r<6> a_blc_r<5> a_blc_r<4> a_blt_r<7> a_blt_r<6> a_blt_r<5> a_blt_r<4> A_BM<17> a_dclk_n_r<1> a_dclk_n_r<2> a_dclk_p_r<1> a_dclk_p_r<2> A_DOUT<17> A_DIN<17> a_rclk_n_r<1> a_rclk_n_r<2> a_rclk_p_r<1> a_rclk_p_r<2> a_tieh<17> a_wclk_n_r<1> a_wclk_n_r<2> a_wclk_p_r<1> a_wclk_p_r<2> b_addr_dec_r<3> b_addr_dec_r<2> b_addr_dec_r<1> b_addr_dec_r<0> B_BIST_BM<17> B_BIST_DIN<17> B_BIST_EN b_blc_r<7> b_blc_r<6> b_blc_r<5> b_blc_r<4> b_blt_r<7> b_blt_r<6> b_blt_r<5> b_blt_r<4> B_BM<17> b_dclk_n_r<1> b_dclk_n_r<2> b_dclk_p_r<1> b_dclk_p_r<2> B_DOUT<17> B_DIN<17> b_rclk_n_r<1> b_rclk_n_r<2> b_rclk_p_r<1> b_rclk_p_r<2> b_tieh<17> b_wclk_n_r<1> b_wclk_n_r<2> b_wclk_p_r<1> b_wclk_p_r<2> VDD! VSS! / RM_IHPSG13_512x32_c2_2P_COLCTRL2 +XCOLCTRL<16> a_addr_dec_r<3> a_addr_dec_r<2> a_addr_dec_r<1> a_addr_dec_r<0> A_BIST_BM<16> A_BIST_DIN<16> A_BIST_EN a_blc_r<3> a_blc_r<2> a_blc_r<1> a_blc_r<0> a_blt_r<3> a_blt_r<2> a_blt_r<1> a_blt_r<0> A_BM<16> a_dclk_n_r<0> a_dclk_n_r<1> a_dclk_p_r<0> a_dclk_p_r<1> A_DOUT<16> A_DIN<16> a_rclk_n_r<0> a_rclk_n_r<1> a_rclk_p_r<0> a_rclk_p_r<1> a_tieh<16> a_wclk_n_r<0> a_wclk_n_r<1> a_wclk_p_r<0> a_wclk_p_r<1> b_addr_dec_r<3> b_addr_dec_r<2> b_addr_dec_r<1> b_addr_dec_r<0> B_BIST_BM<16> B_BIST_DIN<16> B_BIST_EN b_blc_r<3> b_blc_r<2> b_blc_r<1> b_blc_r<0> b_blt_r<3> b_blt_r<2> b_blt_r<1> b_blt_r<0> B_BM<16> b_dclk_n_r<0> b_dclk_n_r<1> b_dclk_p_r<0> b_dclk_p_r<1> B_DOUT<16> B_DIN<16> b_rclk_n_r<0> b_rclk_n_r<1> b_rclk_p_r<0> b_rclk_p_r<1> b_tieh<16> b_wclk_n_r<0> b_wclk_n_r<1> b_wclk_p_r<0> b_wclk_p_r<1> VDD! VSS! / RM_IHPSG13_512x32_c2_2P_COLCTRL2 +XCOLCTRL<15> a_addr_dec_l<3> a_addr_dec_l<2> a_addr_dec_l<1> a_addr_dec_l<0> A_BIST_BM<0> A_BIST_DIN<0> A_BIST_EN a_blc_l<63> a_blc_l<62> a_blc_l<61> a_blc_l<60> a_blt_l<63> a_blt_l<62> a_blt_l<61> a_blt_l<60> A_BM<0> a_dclk_n_l<15> a_dclk_n_l<16> a_dclk_p_l<15> a_dclk_p_l<16> A_DOUT<0> A_DIN<0> a_rclk_n_l<15> a_rclk_n_l<16> a_rclk_p_l<15> a_rclk_p_l<16> a_tieh<0> a_wclk_n_l<15> a_wclk_n_l<16> a_wclk_p_l<15> a_wclk_p_l<16> b_addr_dec_l<3> b_addr_dec_l<2> b_addr_dec_l<1> b_addr_dec_l<0> B_BIST_BM<0> B_BIST_DIN<0> B_BIST_EN b_blc_l<63> b_blc_l<62> b_blc_l<61> b_blc_l<60> b_blt_l<63> b_blt_l<62> b_blt_l<61> b_blt_l<60> B_BM<0> b_dclk_n_l<15> b_dclk_n_l<16> b_dclk_p_l<15> b_dclk_p_l<16> B_DOUT<0> B_DIN<0> b_rclk_n_l<15> b_rclk_n_l<16> b_rclk_p_l<15> b_rclk_p_l<16> b_tieh<0> b_wclk_n_l<15> b_wclk_n_l<16> b_wclk_p_l<15> b_wclk_p_l<16> VDD! VSS! / RM_IHPSG13_512x32_c2_2P_COLCTRL2 +XCOLCTRL<14> a_addr_dec_l<3> a_addr_dec_l<2> a_addr_dec_l<1> a_addr_dec_l<0> A_BIST_BM<1> A_BIST_DIN<1> A_BIST_EN a_blc_l<59> a_blc_l<58> a_blc_l<57> a_blc_l<56> a_blt_l<59> a_blt_l<58> a_blt_l<57> a_blt_l<56> A_BM<1> a_dclk_n_l<14> a_dclk_n_l<15> a_dclk_p_l<14> a_dclk_p_l<15> A_DOUT<1> A_DIN<1> a_rclk_n_l<14> a_rclk_n_l<15> a_rclk_p_l<14> a_rclk_p_l<15> a_tieh<1> a_wclk_n_l<14> a_wclk_n_l<15> a_wclk_p_l<14> a_wclk_p_l<15> b_addr_dec_l<3> b_addr_dec_l<2> b_addr_dec_l<1> b_addr_dec_l<0> B_BIST_BM<1> B_BIST_DIN<1> B_BIST_EN b_blc_l<59> b_blc_l<58> b_blc_l<57> b_blc_l<56> b_blt_l<59> b_blt_l<58> b_blt_l<57> b_blt_l<56> B_BM<1> b_dclk_n_l<14> b_dclk_n_l<15> b_dclk_p_l<14> b_dclk_p_l<15> B_DOUT<1> B_DIN<1> b_rclk_n_l<14> b_rclk_n_l<15> b_rclk_p_l<14> b_rclk_p_l<15> b_tieh<1> b_wclk_n_l<14> b_wclk_n_l<15> b_wclk_p_l<14> b_wclk_p_l<15> VDD! VSS! / RM_IHPSG13_512x32_c2_2P_COLCTRL2 +XCOLCTRL<13> a_addr_dec_l<3> a_addr_dec_l<2> a_addr_dec_l<1> a_addr_dec_l<0> A_BIST_BM<2> A_BIST_DIN<2> A_BIST_EN a_blc_l<55> a_blc_l<54> a_blc_l<53> a_blc_l<52> a_blt_l<55> a_blt_l<54> a_blt_l<53> a_blt_l<52> A_BM<2> a_dclk_n_l<13> a_dclk_n_l<14> a_dclk_p_l<13> a_dclk_p_l<14> A_DOUT<2> A_DIN<2> a_rclk_n_l<13> a_rclk_n_l<14> a_rclk_p_l<13> a_rclk_p_l<14> a_tieh<2> a_wclk_n_l<13> a_wclk_n_l<14> a_wclk_p_l<13> a_wclk_p_l<14> b_addr_dec_l<3> b_addr_dec_l<2> b_addr_dec_l<1> b_addr_dec_l<0> B_BIST_BM<2> B_BIST_DIN<2> B_BIST_EN b_blc_l<55> b_blc_l<54> b_blc_l<53> b_blc_l<52> b_blt_l<55> b_blt_l<54> b_blt_l<53> b_blt_l<52> B_BM<2> b_dclk_n_l<13> b_dclk_n_l<14> b_dclk_p_l<13> b_dclk_p_l<14> B_DOUT<2> B_DIN<2> b_rclk_n_l<13> b_rclk_n_l<14> b_rclk_p_l<13> b_rclk_p_l<14> b_tieh<2> b_wclk_n_l<13> b_wclk_n_l<14> b_wclk_p_l<13> b_wclk_p_l<14> VDD! VSS! / RM_IHPSG13_512x32_c2_2P_COLCTRL2 +XCOLCTRL<12> a_addr_dec_l<3> a_addr_dec_l<2> a_addr_dec_l<1> a_addr_dec_l<0> A_BIST_BM<3> A_BIST_DIN<3> A_BIST_EN a_blc_l<51> a_blc_l<50> a_blc_l<49> a_blc_l<48> a_blt_l<51> a_blt_l<50> a_blt_l<49> a_blt_l<48> A_BM<3> a_dclk_n_l<12> a_dclk_n_l<13> a_dclk_p_l<12> a_dclk_p_l<13> A_DOUT<3> A_DIN<3> a_rclk_n_l<12> a_rclk_n_l<13> a_rclk_p_l<12> a_rclk_p_l<13> a_tieh<3> a_wclk_n_l<12> a_wclk_n_l<13> a_wclk_p_l<12> a_wclk_p_l<13> b_addr_dec_l<3> b_addr_dec_l<2> b_addr_dec_l<1> b_addr_dec_l<0> B_BIST_BM<3> B_BIST_DIN<3> B_BIST_EN b_blc_l<51> b_blc_l<50> b_blc_l<49> b_blc_l<48> b_blt_l<51> b_blt_l<50> b_blt_l<49> b_blt_l<48> B_BM<3> b_dclk_n_l<12> b_dclk_n_l<13> b_dclk_p_l<12> b_dclk_p_l<13> B_DOUT<3> B_DIN<3> b_rclk_n_l<12> b_rclk_n_l<13> b_rclk_p_l<12> b_rclk_p_l<13> b_tieh<3> b_wclk_n_l<12> b_wclk_n_l<13> b_wclk_p_l<12> b_wclk_p_l<13> VDD! VSS! / RM_IHPSG13_512x32_c2_2P_COLCTRL2 +XCOLCTRL<11> a_addr_dec_l<3> a_addr_dec_l<2> a_addr_dec_l<1> a_addr_dec_l<0> A_BIST_BM<4> A_BIST_DIN<4> A_BIST_EN a_blc_l<47> a_blc_l<46> a_blc_l<45> a_blc_l<44> a_blt_l<47> a_blt_l<46> a_blt_l<45> a_blt_l<44> A_BM<4> a_dclk_n_l<11> a_dclk_n_l<12> a_dclk_p_l<11> a_dclk_p_l<12> A_DOUT<4> A_DIN<4> a_rclk_n_l<11> a_rclk_n_l<12> a_rclk_p_l<11> a_rclk_p_l<12> a_tieh<4> a_wclk_n_l<11> a_wclk_n_l<12> a_wclk_p_l<11> a_wclk_p_l<12> b_addr_dec_l<3> b_addr_dec_l<2> b_addr_dec_l<1> b_addr_dec_l<0> B_BIST_BM<4> B_BIST_DIN<4> B_BIST_EN b_blc_l<47> b_blc_l<46> b_blc_l<45> b_blc_l<44> b_blt_l<47> b_blt_l<46> b_blt_l<45> b_blt_l<44> B_BM<4> b_dclk_n_l<11> b_dclk_n_l<12> b_dclk_p_l<11> b_dclk_p_l<12> B_DOUT<4> B_DIN<4> b_rclk_n_l<11> b_rclk_n_l<12> b_rclk_p_l<11> b_rclk_p_l<12> b_tieh<4> b_wclk_n_l<11> b_wclk_n_l<12> b_wclk_p_l<11> b_wclk_p_l<12> VDD! VSS! / RM_IHPSG13_512x32_c2_2P_COLCTRL2 +XCOLCTRL<10> a_addr_dec_l<3> a_addr_dec_l<2> a_addr_dec_l<1> a_addr_dec_l<0> A_BIST_BM<5> A_BIST_DIN<5> A_BIST_EN a_blc_l<43> a_blc_l<42> a_blc_l<41> a_blc_l<40> a_blt_l<43> a_blt_l<42> a_blt_l<41> a_blt_l<40> A_BM<5> a_dclk_n_l<10> a_dclk_n_l<11> a_dclk_p_l<10> a_dclk_p_l<11> A_DOUT<5> A_DIN<5> a_rclk_n_l<10> a_rclk_n_l<11> a_rclk_p_l<10> a_rclk_p_l<11> a_tieh<5> a_wclk_n_l<10> a_wclk_n_l<11> a_wclk_p_l<10> a_wclk_p_l<11> b_addr_dec_l<3> b_addr_dec_l<2> b_addr_dec_l<1> b_addr_dec_l<0> B_BIST_BM<5> B_BIST_DIN<5> B_BIST_EN b_blc_l<43> b_blc_l<42> b_blc_l<41> b_blc_l<40> b_blt_l<43> b_blt_l<42> b_blt_l<41> b_blt_l<40> B_BM<5> b_dclk_n_l<10> b_dclk_n_l<11> b_dclk_p_l<10> b_dclk_p_l<11> B_DOUT<5> B_DIN<5> b_rclk_n_l<10> b_rclk_n_l<11> b_rclk_p_l<10> b_rclk_p_l<11> b_tieh<5> b_wclk_n_l<10> b_wclk_n_l<11> b_wclk_p_l<10> b_wclk_p_l<11> VDD! VSS! / RM_IHPSG13_512x32_c2_2P_COLCTRL2 +XCOLCTRL<9> a_addr_dec_l<3> a_addr_dec_l<2> a_addr_dec_l<1> a_addr_dec_l<0> A_BIST_BM<6> A_BIST_DIN<6> A_BIST_EN a_blc_l<39> a_blc_l<38> a_blc_l<37> a_blc_l<36> a_blt_l<39> a_blt_l<38> a_blt_l<37> a_blt_l<36> A_BM<6> a_dclk_n_l<9> a_dclk_n_l<10> a_dclk_p_l<9> a_dclk_p_l<10> A_DOUT<6> A_DIN<6> a_rclk_n_l<9> a_rclk_n_l<10> a_rclk_p_l<9> a_rclk_p_l<10> a_tieh<6> a_wclk_n_l<9> a_wclk_n_l<10> a_wclk_p_l<9> a_wclk_p_l<10> b_addr_dec_l<3> b_addr_dec_l<2> b_addr_dec_l<1> b_addr_dec_l<0> B_BIST_BM<6> B_BIST_DIN<6> B_BIST_EN b_blc_l<39> b_blc_l<38> b_blc_l<37> b_blc_l<36> b_blt_l<39> b_blt_l<38> b_blt_l<37> b_blt_l<36> B_BM<6> b_dclk_n_l<9> b_dclk_n_l<10> b_dclk_p_l<9> b_dclk_p_l<10> B_DOUT<6> B_DIN<6> b_rclk_n_l<9> b_rclk_n_l<10> b_rclk_p_l<9> b_rclk_p_l<10> b_tieh<6> b_wclk_n_l<9> b_wclk_n_l<10> b_wclk_p_l<9> b_wclk_p_l<10> VDD! VSS! / RM_IHPSG13_512x32_c2_2P_COLCTRL2 +XCOLCTRL<8> a_addr_dec_l<3> a_addr_dec_l<2> a_addr_dec_l<1> a_addr_dec_l<0> A_BIST_BM<7> A_BIST_DIN<7> A_BIST_EN a_blc_l<35> a_blc_l<34> a_blc_l<33> a_blc_l<32> a_blt_l<35> a_blt_l<34> a_blt_l<33> a_blt_l<32> A_BM<7> a_dclk_n_l<8> a_dclk_n_l<9> a_dclk_p_l<8> a_dclk_p_l<9> A_DOUT<7> A_DIN<7> a_rclk_n_l<8> a_rclk_n_l<9> a_rclk_p_l<8> a_rclk_p_l<9> a_tieh<7> a_wclk_n_l<8> a_wclk_n_l<9> a_wclk_p_l<8> a_wclk_p_l<9> b_addr_dec_l<3> b_addr_dec_l<2> b_addr_dec_l<1> b_addr_dec_l<0> B_BIST_BM<7> B_BIST_DIN<7> B_BIST_EN b_blc_l<35> b_blc_l<34> b_blc_l<33> b_blc_l<32> b_blt_l<35> b_blt_l<34> b_blt_l<33> b_blt_l<32> B_BM<7> b_dclk_n_l<8> b_dclk_n_l<9> b_dclk_p_l<8> b_dclk_p_l<9> B_DOUT<7> B_DIN<7> b_rclk_n_l<8> b_rclk_n_l<9> b_rclk_p_l<8> b_rclk_p_l<9> b_tieh<7> b_wclk_n_l<8> b_wclk_n_l<9> b_wclk_p_l<8> b_wclk_p_l<9> VDD! VSS! / RM_IHPSG13_512x32_c2_2P_COLCTRL2 +XCOLCTRL<7> a_addr_dec_l<3> a_addr_dec_l<2> a_addr_dec_l<1> a_addr_dec_l<0> A_BIST_BM<8> A_BIST_DIN<8> A_BIST_EN a_blc_l<31> a_blc_l<30> a_blc_l<29> a_blc_l<28> a_blt_l<31> a_blt_l<30> a_blt_l<29> a_blt_l<28> A_BM<8> a_dclk_n_l<7> a_dclk_n_l<8> a_dclk_p_l<7> a_dclk_p_l<8> A_DOUT<8> A_DIN<8> a_rclk_n_l<7> a_rclk_n_l<8> a_rclk_p_l<7> a_rclk_p_l<8> a_tieh<8> a_wclk_n_l<7> a_wclk_n_l<8> a_wclk_p_l<7> a_wclk_p_l<8> b_addr_dec_l<3> b_addr_dec_l<2> b_addr_dec_l<1> b_addr_dec_l<0> B_BIST_BM<8> B_BIST_DIN<8> B_BIST_EN b_blc_l<31> b_blc_l<30> b_blc_l<29> b_blc_l<28> b_blt_l<31> b_blt_l<30> b_blt_l<29> b_blt_l<28> B_BM<8> b_dclk_n_l<7> b_dclk_n_l<8> b_dclk_p_l<7> b_dclk_p_l<8> B_DOUT<8> B_DIN<8> b_rclk_n_l<7> b_rclk_n_l<8> b_rclk_p_l<7> b_rclk_p_l<8> b_tieh<8> b_wclk_n_l<7> b_wclk_n_l<8> b_wclk_p_l<7> b_wclk_p_l<8> VDD! VSS! / RM_IHPSG13_512x32_c2_2P_COLCTRL2 +XCOLCTRL<6> a_addr_dec_l<3> a_addr_dec_l<2> a_addr_dec_l<1> a_addr_dec_l<0> A_BIST_BM<9> A_BIST_DIN<9> A_BIST_EN a_blc_l<27> a_blc_l<26> a_blc_l<25> a_blc_l<24> a_blt_l<27> a_blt_l<26> a_blt_l<25> a_blt_l<24> A_BM<9> a_dclk_n_l<6> a_dclk_n_l<7> a_dclk_p_l<6> a_dclk_p_l<7> A_DOUT<9> A_DIN<9> a_rclk_n_l<6> a_rclk_n_l<7> a_rclk_p_l<6> a_rclk_p_l<7> a_tieh<9> a_wclk_n_l<6> a_wclk_n_l<7> a_wclk_p_l<6> a_wclk_p_l<7> b_addr_dec_l<3> b_addr_dec_l<2> b_addr_dec_l<1> b_addr_dec_l<0> B_BIST_BM<9> B_BIST_DIN<9> B_BIST_EN b_blc_l<27> b_blc_l<26> b_blc_l<25> b_blc_l<24> b_blt_l<27> b_blt_l<26> b_blt_l<25> b_blt_l<24> B_BM<9> b_dclk_n_l<6> b_dclk_n_l<7> b_dclk_p_l<6> b_dclk_p_l<7> B_DOUT<9> B_DIN<9> b_rclk_n_l<6> b_rclk_n_l<7> b_rclk_p_l<6> b_rclk_p_l<7> b_tieh<9> b_wclk_n_l<6> b_wclk_n_l<7> b_wclk_p_l<6> b_wclk_p_l<7> VDD! VSS! / RM_IHPSG13_512x32_c2_2P_COLCTRL2 +XCOLCTRL<5> a_addr_dec_l<3> a_addr_dec_l<2> a_addr_dec_l<1> a_addr_dec_l<0> A_BIST_BM<10> A_BIST_DIN<10> A_BIST_EN a_blc_l<23> a_blc_l<22> a_blc_l<21> a_blc_l<20> a_blt_l<23> a_blt_l<22> a_blt_l<21> a_blt_l<20> A_BM<10> a_dclk_n_l<5> a_dclk_n_l<6> a_dclk_p_l<5> a_dclk_p_l<6> A_DOUT<10> A_DIN<10> a_rclk_n_l<5> a_rclk_n_l<6> a_rclk_p_l<5> a_rclk_p_l<6> a_tieh<10> a_wclk_n_l<5> a_wclk_n_l<6> a_wclk_p_l<5> a_wclk_p_l<6> b_addr_dec_l<3> b_addr_dec_l<2> b_addr_dec_l<1> b_addr_dec_l<0> B_BIST_BM<10> B_BIST_DIN<10> B_BIST_EN b_blc_l<23> b_blc_l<22> b_blc_l<21> b_blc_l<20> b_blt_l<23> b_blt_l<22> b_blt_l<21> b_blt_l<20> B_BM<10> b_dclk_n_l<5> b_dclk_n_l<6> b_dclk_p_l<5> b_dclk_p_l<6> B_DOUT<10> B_DIN<10> b_rclk_n_l<5> b_rclk_n_l<6> b_rclk_p_l<5> b_rclk_p_l<6> b_tieh<10> b_wclk_n_l<5> b_wclk_n_l<6> b_wclk_p_l<5> b_wclk_p_l<6> VDD! VSS! / RM_IHPSG13_512x32_c2_2P_COLCTRL2 +XCOLCTRL<4> a_addr_dec_l<3> a_addr_dec_l<2> a_addr_dec_l<1> a_addr_dec_l<0> A_BIST_BM<11> A_BIST_DIN<11> A_BIST_EN a_blc_l<19> a_blc_l<18> a_blc_l<17> a_blc_l<16> a_blt_l<19> a_blt_l<18> a_blt_l<17> a_blt_l<16> A_BM<11> a_dclk_n_l<4> a_dclk_n_l<5> a_dclk_p_l<4> a_dclk_p_l<5> A_DOUT<11> A_DIN<11> a_rclk_n_l<4> a_rclk_n_l<5> a_rclk_p_l<4> a_rclk_p_l<5> a_tieh<11> a_wclk_n_l<4> a_wclk_n_l<5> a_wclk_p_l<4> a_wclk_p_l<5> b_addr_dec_l<3> b_addr_dec_l<2> b_addr_dec_l<1> b_addr_dec_l<0> B_BIST_BM<11> B_BIST_DIN<11> B_BIST_EN b_blc_l<19> b_blc_l<18> b_blc_l<17> b_blc_l<16> b_blt_l<19> b_blt_l<18> b_blt_l<17> b_blt_l<16> B_BM<11> b_dclk_n_l<4> b_dclk_n_l<5> b_dclk_p_l<4> b_dclk_p_l<5> B_DOUT<11> B_DIN<11> b_rclk_n_l<4> b_rclk_n_l<5> b_rclk_p_l<4> b_rclk_p_l<5> b_tieh<11> b_wclk_n_l<4> b_wclk_n_l<5> b_wclk_p_l<4> b_wclk_p_l<5> VDD! VSS! / RM_IHPSG13_512x32_c2_2P_COLCTRL2 +XCOLCTRL<3> a_addr_dec_l<3> a_addr_dec_l<2> a_addr_dec_l<1> a_addr_dec_l<0> A_BIST_BM<12> A_BIST_DIN<12> A_BIST_EN a_blc_l<15> a_blc_l<14> a_blc_l<13> a_blc_l<12> a_blt_l<15> a_blt_l<14> a_blt_l<13> a_blt_l<12> A_BM<12> a_dclk_n_l<3> a_dclk_n_l<4> a_dclk_p_l<3> a_dclk_p_l<4> A_DOUT<12> A_DIN<12> a_rclk_n_l<3> a_rclk_n_l<4> a_rclk_p_l<3> a_rclk_p_l<4> a_tieh<12> a_wclk_n_l<3> a_wclk_n_l<4> a_wclk_p_l<3> a_wclk_p_l<4> b_addr_dec_l<3> b_addr_dec_l<2> b_addr_dec_l<1> b_addr_dec_l<0> B_BIST_BM<12> B_BIST_DIN<12> B_BIST_EN b_blc_l<15> b_blc_l<14> b_blc_l<13> b_blc_l<12> b_blt_l<15> b_blt_l<14> b_blt_l<13> b_blt_l<12> B_BM<12> b_dclk_n_l<3> b_dclk_n_l<4> b_dclk_p_l<3> b_dclk_p_l<4> B_DOUT<12> B_DIN<12> b_rclk_n_l<3> b_rclk_n_l<4> b_rclk_p_l<3> b_rclk_p_l<4> b_tieh<12> b_wclk_n_l<3> b_wclk_n_l<4> b_wclk_p_l<3> b_wclk_p_l<4> VDD! VSS! / RM_IHPSG13_512x32_c2_2P_COLCTRL2 +XCOLCTRL<2> a_addr_dec_l<3> a_addr_dec_l<2> a_addr_dec_l<1> a_addr_dec_l<0> A_BIST_BM<13> A_BIST_DIN<13> A_BIST_EN a_blc_l<11> a_blc_l<10> a_blc_l<9> a_blc_l<8> a_blt_l<11> a_blt_l<10> a_blt_l<9> a_blt_l<8> A_BM<13> a_dclk_n_l<2> a_dclk_n_l<3> a_dclk_p_l<2> a_dclk_p_l<3> A_DOUT<13> A_DIN<13> a_rclk_n_l<2> a_rclk_n_l<3> a_rclk_p_l<2> a_rclk_p_l<3> a_tieh<13> a_wclk_n_l<2> a_wclk_n_l<3> a_wclk_p_l<2> a_wclk_p_l<3> b_addr_dec_l<3> b_addr_dec_l<2> b_addr_dec_l<1> b_addr_dec_l<0> B_BIST_BM<13> B_BIST_DIN<13> B_BIST_EN b_blc_l<11> b_blc_l<10> b_blc_l<9> b_blc_l<8> b_blt_l<11> b_blt_l<10> b_blt_l<9> b_blt_l<8> B_BM<13> b_dclk_n_l<2> b_dclk_n_l<3> b_dclk_p_l<2> b_dclk_p_l<3> B_DOUT<13> B_DIN<13> b_rclk_n_l<2> b_rclk_n_l<3> b_rclk_p_l<2> b_rclk_p_l<3> b_tieh<13> b_wclk_n_l<2> b_wclk_n_l<3> b_wclk_p_l<2> b_wclk_p_l<3> VDD! VSS! / RM_IHPSG13_512x32_c2_2P_COLCTRL2 +XCOLCTRL<1> a_addr_dec_l<3> a_addr_dec_l<2> a_addr_dec_l<1> a_addr_dec_l<0> A_BIST_BM<14> A_BIST_DIN<14> A_BIST_EN a_blc_l<7> a_blc_l<6> a_blc_l<5> a_blc_l<4> a_blt_l<7> a_blt_l<6> a_blt_l<5> a_blt_l<4> A_BM<14> a_dclk_n_l<1> a_dclk_n_l<2> a_dclk_p_l<1> a_dclk_p_l<2> A_DOUT<14> A_DIN<14> a_rclk_n_l<1> a_rclk_n_l<2> a_rclk_p_l<1> a_rclk_p_l<2> a_tieh<14> a_wclk_n_l<1> a_wclk_n_l<2> a_wclk_p_l<1> a_wclk_p_l<2> b_addr_dec_l<3> b_addr_dec_l<2> b_addr_dec_l<1> b_addr_dec_l<0> B_BIST_BM<14> B_BIST_DIN<14> B_BIST_EN b_blc_l<7> b_blc_l<6> b_blc_l<5> b_blc_l<4> b_blt_l<7> b_blt_l<6> b_blt_l<5> b_blt_l<4> B_BM<14> b_dclk_n_l<1> b_dclk_n_l<2> b_dclk_p_l<1> b_dclk_p_l<2> B_DOUT<14> B_DIN<14> b_rclk_n_l<1> b_rclk_n_l<2> b_rclk_p_l<1> b_rclk_p_l<2> b_tieh<14> b_wclk_n_l<1> b_wclk_n_l<2> b_wclk_p_l<1> b_wclk_p_l<2> VDD! VSS! / RM_IHPSG13_512x32_c2_2P_COLCTRL2 +XCOLCTRL<0> a_addr_dec_l<3> a_addr_dec_l<2> a_addr_dec_l<1> a_addr_dec_l<0> A_BIST_BM<15> A_BIST_DIN<15> A_BIST_EN a_blc_l<3> a_blc_l<2> a_blc_l<1> a_blc_l<0> a_blt_l<3> a_blt_l<2> a_blt_l<1> a_blt_l<0> A_BM<15> a_dclk_n_l<0> a_dclk_n_l<1> a_dclk_p_l<0> a_dclk_p_l<1> A_DOUT<15> A_DIN<15> a_rclk_n_l<0> a_rclk_n_l<1> a_rclk_p_l<0> a_rclk_p_l<1> a_tieh<15> a_wclk_n_l<0> a_wclk_n_l<1> a_wclk_p_l<0> a_wclk_p_l<1> b_addr_dec_l<3> b_addr_dec_l<2> b_addr_dec_l<1> b_addr_dec_l<0> B_BIST_BM<15> B_BIST_DIN<15> B_BIST_EN b_blc_l<3> b_blc_l<2> b_blc_l<1> b_blc_l<0> b_blt_l<3> b_blt_l<2> b_blt_l<1> b_blt_l<0> B_BM<15> b_dclk_n_l<0> b_dclk_n_l<1> b_dclk_p_l<0> b_dclk_p_l<1> B_DOUT<15> B_DIN<15> b_rclk_n_l<0> b_rclk_n_l<1> b_rclk_p_l<0> b_rclk_p_l<1> b_tieh<15> b_wclk_n_l<0> b_wclk_n_l<1> b_wclk_p_l<0> b_wclk_p_l<1> VDD! VSS! / RM_IHPSG13_512x32_c2_2P_COLCTRL2 + + +XDRVFILL4<1> VDD! VSS! / RM_IHPSG13_512x32_c2_2P_COLDRV13_FILL4 +XDRVFILL4<2> VDD! VSS! / RM_IHPSG13_512x32_c2_2P_COLDRV13_FILL4 +XDRVFILL4<3> VDD! VSS! / RM_IHPSG13_512x32_c2_2P_COLDRV13_FILL4 +XDRVFILL4<4> VDD! VSS! / RM_IHPSG13_512x32_c2_2P_COLDRV13_FILL4 +XDRVFILL4<5> VDD! VSS! / RM_IHPSG13_512x32_c2_2P_COLDRV13_FILL4 +XDRVFILL4<6> VDD! VSS! / RM_IHPSG13_512x32_c2_2P_COLDRV13_FILL4 +XCOLFILL4<1> VDD! VSS! / RM_IHPSG13_512x32_c2_2P_COLDRV13_FILL4C2 +XCOLFILL4<2> VDD! VSS! / RM_IHPSG13_512x32_c2_2P_COLDRV13_FILL4C2 +XCOLFILL4<3> VDD! VSS! / RM_IHPSG13_512x32_c2_2P_COLDRV13_FILL4C2 +XCOLFILL4<4> VDD! VSS! / RM_IHPSG13_512x32_c2_2P_COLDRV13_FILL4C2 +XCOLFILL4<5> VDD! VSS! / RM_IHPSG13_512x32_c2_2P_COLDRV13_FILL4C2 +XCOLFILL4<6> VDD! VSS! / RM_IHPSG13_512x32_c2_2P_COLDRV13_FILL4C2 +XCOLFILL4<7> VDD! VSS! / RM_IHPSG13_512x32_c2_2P_COLDRV13_FILL4C2 +XCOLFILL4<8> VDD! VSS! / RM_IHPSG13_512x32_c2_2P_COLDRV13_FILL4C2 +XCOLFILL4<9> VDD! VSS! / RM_IHPSG13_512x32_c2_2P_COLDRV13_FILL4C2 +XCOLFILL4<10> VDD! VSS! / RM_IHPSG13_512x32_c2_2P_COLDRV13_FILL4C2 +XCOLFILL4<11> VDD! VSS! / RM_IHPSG13_512x32_c2_2P_COLDRV13_FILL4C2 +XCOLFILL4<12> VDD! VSS! / RM_IHPSG13_512x32_c2_2P_COLDRV13_FILL4C2 +XCOLFILL4<13> VDD! VSS! / RM_IHPSG13_512x32_c2_2P_COLDRV13_FILL4C2 +XCOLFILL4<14> VDD! VSS! / RM_IHPSG13_512x32_c2_2P_COLDRV13_FILL4C2 +XCOLFILL4<15> VDD! VSS! / RM_IHPSG13_512x32_c2_2P_COLDRV13_FILL4C2 +XCOLFILL4<16> VDD! VSS! / RM_IHPSG13_512x32_c2_2P_COLDRV13_FILL4C2 +.ENDS diff --git a/flow/platforms/ihp-sg13g2/cdl/RM_IHPSG13_2P_512x8_c2_bm_bist.cdl b/flow/platforms/ihp-sg13g2/cdl/RM_IHPSG13_2P_512x8_c2_bm_bist.cdl new file mode 100644 index 0000000000..7ce52542f3 --- /dev/null +++ b/flow/platforms/ihp-sg13g2/cdl/RM_IHPSG13_2P_512x8_c2_bm_bist.cdl @@ -0,0 +1,6378 @@ +* ------------------------------------------------------ +* +* Copyright 2025 IHP PDK Authors +* +* Licensed under the Apache License, Version 2.0 (the "License"); +* you may not use this file except in compliance with the License. +* You may obtain a copy of the License at +* +* https://www.apache.org/licenses/LICENSE-2.0 +* +* Unless required by applicable law or agreed to in writing, software +* distributed under the License is distributed on an "AS IS" BASIS, +* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +* See the License for the specific language governing permissions and +* limitations under the License. +* +* Generated on Wed Aug 27 13:34:43 2025 +* +* ------------------------------------------------------ + +.SUBCKT RM_IHPSG13_512x8_c2_1P_BITKIT_CORNER NW PW VDD VSS +.ENDS +.SUBCKT RM_IHPSG13_512x8_c2_1P_BITKIT_16x2_CORNER VDD_CORE VSS +XI16 VDD_CORE VSS VDD_CORE VSS / ++ RM_IHPSG13_512x8_c2_1P_BITKIT_CORNER +.ENDS +.SUBCKT RM_IHPSG13_512x8_c2_1P_BITKIT_EDGE_LR LWL NW PW VDD VSS +MN1 VSS LWL VSS VSS sg13_lv_nmos m=1 w=300.0n l=130.00n ng=1 nrd=0 nrs=0 +MN0 VSS net9 VSS VSS sg13_lv_nmos m=1 w=300.0n l=130.00n ng=1 nrd=0 nrs=0 +.ENDS +.SUBCKT RM_IHPSG13_512x8_c2_1P_BITKIT_16x2_EDGE_LR A_WL<15> A_WL<14> A_WL<13> A_WL<12> ++ A_WL<11> A_WL<10> A_WL<9> A_WL<8> A_WL<7> A_WL<6> A_WL<5> A_WL<4> A_WL<3> ++ A_WL<2> A_WL<1> A_WL<0> VDD_CORE VSS +XI0<15> A_WL<15> VDD_CORE VSS VDD_CORE VSS / ++ RM_IHPSG13_512x8_c2_1P_BITKIT_EDGE_LR +XI0<14> A_WL<14> VDD_CORE VSS VDD_CORE VSS / ++ RM_IHPSG13_512x8_c2_1P_BITKIT_EDGE_LR +XI0<13> A_WL<13> VDD_CORE VSS VDD_CORE VSS / ++ RM_IHPSG13_512x8_c2_1P_BITKIT_EDGE_LR +XI0<12> A_WL<12> VDD_CORE VSS VDD_CORE VSS / ++ RM_IHPSG13_512x8_c2_1P_BITKIT_EDGE_LR +XI0<11> A_WL<11> VDD_CORE VSS VDD_CORE VSS / ++ RM_IHPSG13_512x8_c2_1P_BITKIT_EDGE_LR +XI0<10> A_WL<10> VDD_CORE VSS VDD_CORE VSS / ++ RM_IHPSG13_512x8_c2_1P_BITKIT_EDGE_LR +XI0<9> A_WL<9> VDD_CORE VSS VDD_CORE VSS / ++ RM_IHPSG13_512x8_c2_1P_BITKIT_EDGE_LR +XI0<8> A_WL<8> VDD_CORE VSS VDD_CORE VSS / ++ RM_IHPSG13_512x8_c2_1P_BITKIT_EDGE_LR +XI0<7> A_WL<7> VDD_CORE VSS VDD_CORE VSS / ++ RM_IHPSG13_512x8_c2_1P_BITKIT_EDGE_LR +XI0<6> A_WL<6> VDD_CORE VSS VDD_CORE VSS / ++ RM_IHPSG13_512x8_c2_1P_BITKIT_EDGE_LR +XI0<5> A_WL<5> VDD_CORE VSS VDD_CORE VSS / ++ RM_IHPSG13_512x8_c2_1P_BITKIT_EDGE_LR +XI0<4> A_WL<4> VDD_CORE VSS VDD_CORE VSS / ++ RM_IHPSG13_512x8_c2_1P_BITKIT_EDGE_LR +XI0<3> A_WL<3> VDD_CORE VSS VDD_CORE VSS / ++ RM_IHPSG13_512x8_c2_1P_BITKIT_EDGE_LR +XI0<2> A_WL<2> VDD_CORE VSS VDD_CORE VSS / ++ RM_IHPSG13_512x8_c2_1P_BITKIT_EDGE_LR +XI0<1> A_WL<1> VDD_CORE VSS VDD_CORE VSS / ++ RM_IHPSG13_512x8_c2_1P_BITKIT_EDGE_LR +XI0<0> A_WL<0> VDD_CORE VSS VDD_CORE VSS / ++ RM_IHPSG13_512x8_c2_1P_BITKIT_EDGE_LR +.ENDS +.SUBCKT RM_IHPSG13_512x8_c2_1P_BITKIT_CELL BLC_BOT BLC_TOP BLT_BOT BLT_TOP LWL NW PW ++ RWL VDD VSS +MN0 NC NT VSS PW sg13_lv_nmos m=1 w=300.0n l=130.00n ng=1 nrd=0 nrs=0 +MN1 NT NC VSS PW sg13_lv_nmos m=1 w=300.0n l=130.00n ng=1 nrd=0 nrs=0 +MN3 NC RWL BLC_TOP PW sg13_lv_nmos m=1 w=300.0n l=130.00n ng=1 nrd=0 nrs=0 +MN2 BLT_BOT LWL NT PW sg13_lv_nmos m=1 w=300.0n l=130.00n ng=1 nrd=0 nrs=0 +MP1 NT NC VDD NW sg13_lv_pmos m=1 w=150.00n l=130.00n ng=1 nrd=0 nrs=0 +MP0 NC NT VDD NW sg13_lv_pmos m=1 w=150.00n l=130.00n ng=1 nrd=0 nrs=0 +R1 BLC_BOT BLC_TOP lvsres w=2.6e-07 l=6e-07 +R0 BLT_BOT BLT_TOP lvsres w=2.6e-07 l=6e-07 +R2 RWL LWL lvsres w=2.6e-07 l=6e-07 +.ENDS +.SUBCKT RM_IHPSG13_512x8_c2_1P_BITKIT_16x2_SRAM A_BLC_BOT<1> A_BLC_BOT<0> A_BLC_TOP<1> ++ A_BLC_TOP<0> A_BLT_BOT<1> A_BLT_BOT<0> A_BLT_TOP<1> A_BLT_TOP<0> A_LWL<15> ++ A_LWL<14> A_LWL<13> A_LWL<12> A_LWL<11> A_LWL<10> A_LWL<9> A_LWL<8> A_LWL<7> ++ A_LWL<6> A_LWL<5> A_LWL<4> A_LWL<3> A_LWL<2> A_LWL<1> A_LWL<0> A_RWL<15> ++ A_RWL<14> A_RWL<13> A_RWL<12> A_RWL<11> A_RWL<10> A_RWL<9> A_RWL<8> A_RWL<7> ++ A_RWL<6> A_RWL<5> A_RWL<4> A_RWL<3> A_RWL<2> A_RWL<1> A_RWL<0> VDD_CORE ++ VSS +XCELL<31> A_BLC_TOP<1> A_RBLC<15> A_BLT_TOP<1> A_RBLT<15> A_RWL<15> ++ VDD_CORE VSS A_XWL<15> VDD_CORE VSS / ++ RM_IHPSG13_512x8_c2_1P_BITKIT_CELL +XCELL<30> A_RBLC<14> A_RBLC<15> A_RBLT<14> A_RBLT<15> A_RWL<14> VDD_CORE ++ VSS A_XWL<14> VDD_CORE VSS / RM_IHPSG13_512x8_c2_1P_BITKIT_CELL +XCELL<29> A_RBLC<14> A_RBLC<13> A_RBLT<14> A_RBLT<13> A_RWL<13> VDD_CORE ++ VSS A_XWL<13> VDD_CORE VSS / RM_IHPSG13_512x8_c2_1P_BITKIT_CELL +XCELL<28> A_RBLC<12> A_RBLC<13> A_RBLT<12> A_RBLT<13> A_RWL<12> VDD_CORE ++ VSS A_XWL<12> VDD_CORE VSS / RM_IHPSG13_512x8_c2_1P_BITKIT_CELL +XCELL<27> A_RBLC<12> A_RBLC<11> A_RBLT<12> A_RBLT<11> A_RWL<11> VDD_CORE ++ VSS A_XWL<11> VDD_CORE VSS / RM_IHPSG13_512x8_c2_1P_BITKIT_CELL +XCELL<26> A_RBLC<10> A_RBLC<11> A_RBLT<10> A_RBLT<11> A_RWL<10> VDD_CORE ++ VSS A_XWL<10> VDD_CORE VSS / RM_IHPSG13_512x8_c2_1P_BITKIT_CELL +XCELL<25> A_RBLC<10> A_RBLC<9> A_RBLT<10> A_RBLT<9> A_RWL<9> VDD_CORE ++ VSS A_XWL<9> VDD_CORE VSS / RM_IHPSG13_512x8_c2_1P_BITKIT_CELL +XCELL<24> A_RBLC<8> A_RBLC<9> A_RBLT<8> A_RBLT<9> A_RWL<8> VDD_CORE ++ VSS A_XWL<8> VDD_CORE VSS / RM_IHPSG13_512x8_c2_1P_BITKIT_CELL +XCELL<23> A_RBLC<8> A_RBLC<7> A_RBLT<8> A_RBLT<7> A_RWL<7> VDD_CORE ++ VSS A_XWL<7> VDD_CORE VSS / RM_IHPSG13_512x8_c2_1P_BITKIT_CELL +XCELL<22> A_RBLC<6> A_RBLC<7> A_RBLT<6> A_RBLT<7> A_RWL<6> VDD_CORE ++ VSS A_XWL<6> VDD_CORE VSS / RM_IHPSG13_512x8_c2_1P_BITKIT_CELL +XCELL<21> A_RBLC<6> A_RBLC<5> A_RBLT<6> A_RBLT<5> A_RWL<5> VDD_CORE ++ VSS A_XWL<5> VDD_CORE VSS / RM_IHPSG13_512x8_c2_1P_BITKIT_CELL +XCELL<20> A_RBLC<4> A_RBLC<5> A_RBLT<4> A_RBLT<5> A_RWL<4> VDD_CORE ++ VSS A_XWL<4> VDD_CORE VSS / RM_IHPSG13_512x8_c2_1P_BITKIT_CELL +XCELL<19> A_RBLC<4> A_RBLC<3> A_RBLT<4> A_RBLT<3> A_RWL<3> VDD_CORE ++ VSS A_XWL<3> VDD_CORE VSS / RM_IHPSG13_512x8_c2_1P_BITKIT_CELL +XCELL<18> A_RBLC<2> A_RBLC<3> A_RBLT<2> A_RBLT<3> A_RWL<2> VDD_CORE ++ VSS A_XWL<2> VDD_CORE VSS / RM_IHPSG13_512x8_c2_1P_BITKIT_CELL +XCELL<17> A_RBLC<2> A_RBLC<1> A_RBLT<2> A_RBLT<1> A_RWL<1> VDD_CORE ++ VSS A_XWL<1> VDD_CORE VSS / RM_IHPSG13_512x8_c2_1P_BITKIT_CELL +XCELL<16> A_BLC_BOT<1> A_RBLC<1> A_BLT_BOT<1> A_RBLT<1> A_RWL<0> VDD_CORE ++ VSS A_XWL<0> VDD_CORE VSS / RM_IHPSG13_512x8_c2_1P_BITKIT_CELL +XCELL<15> A_BLC_TOP<0> A_LBLC<15> A_BLT_TOP<0> A_LBLT<15> A_LWL<15> ++ VDD_CORE VSS A_XWL<15> VDD_CORE VSS / ++ RM_IHPSG13_512x8_c2_1P_BITKIT_CELL +XCELL<14> A_LBLC<14> A_LBLC<15> A_LBLT<14> A_LBLT<15> A_LWL<14> VDD_CORE ++ VSS A_XWL<14> VDD_CORE VSS / RM_IHPSG13_512x8_c2_1P_BITKIT_CELL +XCELL<13> A_LBLC<14> A_LBLC<13> A_LBLT<14> A_LBLT<13> A_LWL<13> VDD_CORE ++ VSS A_XWL<13> VDD_CORE VSS / RM_IHPSG13_512x8_c2_1P_BITKIT_CELL +XCELL<12> A_LBLC<12> A_LBLC<13> A_LBLT<12> A_LBLT<13> A_LWL<12> VDD_CORE ++ VSS A_XWL<12> VDD_CORE VSS / RM_IHPSG13_512x8_c2_1P_BITKIT_CELL +XCELL<11> A_LBLC<12> A_LBLC<11> A_LBLT<12> A_LBLT<11> A_LWL<11> VDD_CORE ++ VSS A_XWL<11> VDD_CORE VSS / RM_IHPSG13_512x8_c2_1P_BITKIT_CELL +XCELL<10> A_LBLC<10> A_LBLC<11> A_LBLT<10> A_LBLT<11> A_LWL<10> VDD_CORE ++ VSS A_XWL<10> VDD_CORE VSS / RM_IHPSG13_512x8_c2_1P_BITKIT_CELL +XCELL<9> A_LBLC<10> A_LBLC<9> A_LBLT<10> A_LBLT<9> A_LWL<9> VDD_CORE ++ VSS A_XWL<9> VDD_CORE VSS / RM_IHPSG13_512x8_c2_1P_BITKIT_CELL +XCELL<8> A_LBLC<8> A_LBLC<9> A_LBLT<8> A_LBLT<9> A_LWL<8> VDD_CORE ++ VSS A_XWL<8> VDD_CORE VSS / RM_IHPSG13_512x8_c2_1P_BITKIT_CELL +XCELL<7> A_LBLC<8> A_LBLC<7> A_LBLT<8> A_LBLT<7> A_LWL<7> VDD_CORE ++ VSS A_XWL<7> VDD_CORE VSS / RM_IHPSG13_512x8_c2_1P_BITKIT_CELL +XCELL<6> A_LBLC<6> A_LBLC<7> A_LBLT<6> A_LBLT<7> A_LWL<6> VDD_CORE ++ VSS A_XWL<6> VDD_CORE VSS / RM_IHPSG13_512x8_c2_1P_BITKIT_CELL +XCELL<5> A_LBLC<6> A_LBLC<5> A_LBLT<6> A_LBLT<5> A_LWL<5> VDD_CORE ++ VSS A_XWL<5> VDD_CORE VSS / RM_IHPSG13_512x8_c2_1P_BITKIT_CELL +XCELL<4> A_LBLC<4> A_LBLC<5> A_LBLT<4> A_LBLT<5> A_LWL<4> VDD_CORE ++ VSS A_XWL<4> VDD_CORE VSS / RM_IHPSG13_512x8_c2_1P_BITKIT_CELL +XCELL<3> A_LBLC<4> A_LBLC<3> A_LBLT<4> A_LBLT<3> A_LWL<3> VDD_CORE ++ VSS A_XWL<3> VDD_CORE VSS / RM_IHPSG13_512x8_c2_1P_BITKIT_CELL +XCELL<2> A_LBLC<2> A_LBLC<3> A_LBLT<2> A_LBLT<3> A_LWL<2> VDD_CORE ++ VSS A_XWL<2> VDD_CORE VSS / RM_IHPSG13_512x8_c2_1P_BITKIT_CELL +XCELL<1> A_LBLC<2> A_LBLC<1> A_LBLT<2> A_LBLT<1> A_LWL<1> VDD_CORE ++ VSS A_XWL<1> VDD_CORE VSS / RM_IHPSG13_512x8_c2_1P_BITKIT_CELL +XCELL<0> A_BLC_BOT<0> A_LBLC<1> A_BLT_BOT<0> A_LBLT<1> A_LWL<0> VDD_CORE ++ VSS A_XWL<0> VDD_CORE VSS / RM_IHPSG13_512x8_c2_1P_BITKIT_CELL +.ENDS +.SUBCKT RM_IHPSG13_512x8_c2_1P_BITKIT_EDGE_TB BLC BLT NW PW VDD VSS +.ENDS +.SUBCKT RM_IHPSG13_512x8_c2_1P_BITKIT_16x2_EDGE_TB A_BLC<1> A_BLC<0> A_BLT<1> A_BLT<0> ++ VDD_CORE VSS +XEDGE<1> A_BLC<1> A_BLT<1> VDD_CORE VSS VDD_CORE VSS ++ / RM_IHPSG13_512x8_c2_1P_BITKIT_EDGE_TB +XEDGE<0> A_BLC<0> A_BLT<0> VDD_CORE VSS VDD_CORE VSS ++ / RM_IHPSG13_512x8_c2_1P_BITKIT_EDGE_TB +.ENDS + +.SUBCKT RSC_IHPSG13_CBUFX4 A Z VDD VSS +MN0 net9 A VSS VSS sg13_lv_nmos m=1 w=705.000n l=130.00n ng=1 nrd=0 ++ nrs=0 +MN1 Z net9 VSS VSS sg13_lv_nmos m=1 w=1.41u l=130.00n ng=2 nrd=0 nrs=0 +MP0 net9 A VDD VDD sg13_lv_pmos m=1 w=1.62u l=130.00n ng=1 nrd=0 nrs=0 +MP1 Z net9 VDD VDD sg13_lv_pmos m=1 w=3.24u l=130.00n ng=2 nrd=0 nrs=0 +.ENDS +.SUBCKT RM_IHPSG13_512x8_c2_1P_COLDRV13X4 ADDR_COL_I<1> ADDR_COL_I<0> ADDR_COL_O<1> ++ ADDR_COL_O<0> ADDR_DEC_I<7> ADDR_DEC_I<6> ADDR_DEC_I<5> ADDR_DEC_I<4> ++ ADDR_DEC_I<3> ADDR_DEC_I<2> ADDR_DEC_I<1> ADDR_DEC_I<0> ADDR_DEC_O<7> ++ ADDR_DEC_O<6> ADDR_DEC_O<5> ADDR_DEC_O<4> ADDR_DEC_O<3> ADDR_DEC_O<2> ++ ADDR_DEC_O<1> ADDR_DEC_O<0> DCLK_I DCLK_O RCLK_I RCLK_O WCLK_I WCLK_O ++ VDD VSS +XADDR_COL_DRV<1> ADDR_COL_I<1> ADDR_COL_O<1> VDD VSS / ++ RSC_IHPSG13_CBUFX4 +XADDR_COL_DRV<0> ADDR_COL_I<0> ADDR_COL_O<0> VDD VSS / ++ RSC_IHPSG13_CBUFX4 +XADDR_DEC_DRV<7> ADDR_DEC_I<7> ADDR_DEC_O<7> VDD VSS / ++ RSC_IHPSG13_CBUFX4 +XADDR_DEC_DRV<6> ADDR_DEC_I<6> ADDR_DEC_O<6> VDD VSS / ++ RSC_IHPSG13_CBUFX4 +XADDR_DEC_DRV<5> ADDR_DEC_I<5> ADDR_DEC_O<5> VDD VSS / ++ RSC_IHPSG13_CBUFX4 +XADDR_DEC_DRV<4> ADDR_DEC_I<4> ADDR_DEC_O<4> VDD VSS / ++ RSC_IHPSG13_CBUFX4 +XADDR_DEC_DRV<3> ADDR_DEC_I<3> ADDR_DEC_O<3> VDD VSS / ++ RSC_IHPSG13_CBUFX4 +XADDR_DEC_DRV<2> ADDR_DEC_I<2> ADDR_DEC_O<2> VDD VSS / ++ RSC_IHPSG13_CBUFX4 +XADDR_DEC_DRV<1> ADDR_DEC_I<1> ADDR_DEC_O<1> VDD VSS / ++ RSC_IHPSG13_CBUFX4 +XADDR_DEC_DRV<0> ADDR_DEC_I<0> ADDR_DEC_O<0> VDD VSS / ++ RSC_IHPSG13_CBUFX4 +XDCLK_DRV DCLK_I DCLK_O VDD VSS / RSC_IHPSG13_CBUFX4 +XRCLK_DRV RCLK_I RCLK_O VDD VSS / RSC_IHPSG13_CBUFX4 +XWCLK_DRV WCLK_I WCLK_O VDD VSS / RSC_IHPSG13_CBUFX4 +.ENDS +.SUBCKT RSC_IHPSG13_WLDRVX4 A Z VDD VSS +MN1 Z net6 VSS VSS sg13_lv_nmos m=1 w=705.000n l=130.00n ng=1 nrd=0 ++ nrs=0 +MN0 net6 A VSS VSS sg13_lv_nmos m=1 w=900.0n l=130.00n ng=1 nrd=0 nrs=0 +MP1 Z net6 VDD VDD sg13_lv_pmos m=1 w=3.24u l=130.00n ng=2 nrd=0 nrs=0 +MP0 net6 A VDD VDD sg13_lv_pmos m=1 w=900.0n l=130.00n ng=1 nrd=0 nrs=0 +.ENDS +.SUBCKT RM_IHPSG13_512x8_c2_1P_WLDRV16X4 A<15> A<14> A<13> A<12> A<11> A<10> A<9> A<8> ++ A<7> A<6> A<5> A<4> A<3> A<2> A<1> A<0> Z<15> Z<14> Z<13> Z<12> Z<11> Z<10> ++ Z<9> Z<8> Z<7> Z<6> Z<5> Z<4> Z<3> Z<2> Z<1> Z<0> VDD VSS +XBUF<15> A<15> Z<15> VDD VSS / RSC_IHPSG13_WLDRVX4 +XBUF<14> A<14> Z<14> VDD VSS / RSC_IHPSG13_WLDRVX4 +XBUF<13> A<13> Z<13> VDD VSS / RSC_IHPSG13_WLDRVX4 +XBUF<12> A<12> Z<12> VDD VSS / RSC_IHPSG13_WLDRVX4 +XBUF<11> A<11> Z<11> VDD VSS / RSC_IHPSG13_WLDRVX4 +XBUF<10> A<10> Z<10> VDD VSS / RSC_IHPSG13_WLDRVX4 +XBUF<9> A<9> Z<9> VDD VSS / RSC_IHPSG13_WLDRVX4 +XBUF<8> A<8> Z<8> VDD VSS / RSC_IHPSG13_WLDRVX4 +XBUF<7> A<7> Z<7> VDD VSS / RSC_IHPSG13_WLDRVX4 +XBUF<6> A<6> Z<6> VDD VSS / RSC_IHPSG13_WLDRVX4 +XBUF<5> A<5> Z<5> VDD VSS / RSC_IHPSG13_WLDRVX4 +XBUF<4> A<4> Z<4> VDD VSS / RSC_IHPSG13_WLDRVX4 +XBUF<3> A<3> Z<3> VDD VSS / RSC_IHPSG13_WLDRVX4 +XBUF<2> A<2> Z<2> VDD VSS / RSC_IHPSG13_WLDRVX4 +XBUF<1> A<1> Z<1> VDD VSS / RSC_IHPSG13_WLDRVX4 +XBUF<0> A<0> Z<0> VDD VSS / RSC_IHPSG13_WLDRVX4 +.ENDS +.SUBCKT RSC_IHPSG13_FILLCAP8 VDD VSS +MN0 vss_r vdd_r VSS VSS sg13_lv_nmos m=1 w=4.98u l=130.00n ng=6 nrd=0 ++ nrs=0 +MP0 vdd_r vss_r VDD VDD sg13_lv_pmos m=1 w=6.48u l=385.000n ng=4 nrd=0 ++ nrs=0 +.ENDS +.SUBCKT RSC_IHPSG13_LHPQX2 CP D Q VDD VSS +MN3 QIN CPN net14 VSS sg13_lv_nmos m=1 w=480.00n l=130.00n ng=1 nrd=0 nrs=0 +MN2 net14 net10 VSS VSS sg13_lv_nmos m=1 w=480.00n l=130.00n ng=1 ++ nrd=0 nrs=0 +MN5 net21 D VSS VSS sg13_lv_nmos m=1 w=870.00n l=130.00n ng=1 nrd=0 ++ nrs=0 +MN6 QIN CP net21 VSS sg13_lv_nmos m=1 w=870.00n l=130.00n ng=1 nrd=0 nrs=0 +MN1 net10 QIN VSS VSS sg13_lv_nmos m=1 w=480.00n l=130.00n ng=1 nrd=0 ++ nrs=0 +MN0 CPN CP VSS VSS sg13_lv_nmos m=1 w=480.00n l=130.00n ng=1 nrd=0 ++ nrs=0 +MN4 Q QIN VSS VSS sg13_lv_nmos m=1 w=980.00n l=130.00n ng=1 nrd=0 nrs=0 +MP2 QIN CP net16 VDD sg13_lv_pmos m=1 w=480.00n l=130.00n ng=1 nrd=0 nrs=0 +MP0 CPN CP VDD VDD sg13_lv_pmos m=1 w=480.00n l=130.00n ng=1 nrd=0 ++ nrs=0 +MP4 Q QIN VDD VDD sg13_lv_pmos m=1 w=1.62u l=130.00n ng=1 nrd=0 nrs=0 +MP3 net10 QIN VDD VDD sg13_lv_pmos m=1 w=480.00n l=130.00n ng=1 nrd=0 ++ nrs=0 +MP1 net16 net10 VDD VDD sg13_lv_pmos m=1 w=480.00n l=130.00n ng=1 ++ nrd=0 nrs=0 +MP6 QIN CPN net20 VDD sg13_lv_pmos m=1 w=975.000n l=130.00n ng=1 nrd=0 ++ nrs=0 +MP5 net20 D VDD VDD sg13_lv_pmos m=1 w=975.000n l=130.00n ng=1 nrd=0 ++ nrs=0 +.ENDS +.SUBCKT RSC_IHPSG13_NAND2X2 A B Z VDD VSS +MP1 Z B VDD VDD sg13_lv_pmos m=1 w=1.62u l=130.00n ng=1 nrd=0 nrs=0 +MP0 Z A VDD VDD sg13_lv_pmos m=1 w=1.62u l=130.00n ng=1 nrd=0 nrs=0 +MN0 Z B net7 VSS sg13_lv_nmos m=1 w=980.00n l=130.00n ng=1 nrd=0 nrs=0 +MN1 net7 A VSS VSS sg13_lv_nmos m=1 w=980.00n l=130.00n ng=1 nrd=0 ++ nrs=0 +.ENDS +.SUBCKT RSC_IHPSG13_CINVX4 A Z VDD VSS +MN0 Z A VSS VSS sg13_lv_nmos m=1 w=1.41u l=130.00n ng=2 nrd=0 nrs=0 +MP0 Z A VDD VDD sg13_lv_pmos m=1 w=3.24u l=130.00n ng=2 nrd=0 nrs=0 +.ENDS +.SUBCKT RSC_IHPSG13_CINVX2 A Z VDD VSS +MN0 Z A VSS VSS sg13_lv_nmos m=1 w=705.000n l=130.00n ng=1 nrd=0 nrs=0 +MP0 Z A VDD VDD sg13_lv_pmos m=1 w=1.62u l=130.00n ng=1 nrd=0 nrs=0 +.ENDS +.SUBCKT RSC_IHPSG13_INVX2 A Z VDD VSS +MN0 Z A VSS VSS sg13_lv_nmos m=1 w=980.00n l=130.00n ng=1 nrd=0 nrs=0 +MP0 Z A VDD VDD sg13_lv_pmos m=1 w=1.62u l=130.00n ng=1 nrd=0 nrs=0 +.ENDS +.SUBCKT RSC_IHPSG13_NAND3X2 A B C Z VDD VSS +MP2 Z A VDD VDD sg13_lv_pmos m=1 w=1.62u l=130.00n ng=1 nrd=0 nrs=0 +MP1 Z B VDD VDD sg13_lv_pmos m=1 w=1.62u l=130.00n ng=1 nrd=0 nrs=0 +MP0 Z C VDD VDD sg13_lv_pmos m=1 w=1.62u l=130.00n ng=1 nrd=0 nrs=0 +MN1 net12 B net16 VSS sg13_lv_nmos m=1 w=980.00n l=130.00n ng=1 nrd=0 nrs=0 +MN0 Z C net12 VSS sg13_lv_nmos m=1 w=980.00n l=130.00n ng=1 nrd=0 nrs=0 +MN2 net16 A VSS VSS sg13_lv_nmos m=1 w=980.00n l=130.00n ng=1 nrd=0 ++ nrs=0 +.ENDS +.SUBCKT RSC_IHPSG13_NOR3X2 A B C Z VDD VSS +MP0 net13 A VDD VDD sg13_lv_pmos m=1 w=1.62u l=130.00n ng=1 nrd=0 nrs=0 +MP2 Z C net10 VDD sg13_lv_pmos m=1 w=1.62u l=130.00n ng=1 nrd=0 nrs=0 +MP1 net10 B net13 VDD sg13_lv_pmos m=1 w=1.62u l=130.00n ng=1 nrd=0 nrs=0 +MN1 Z B VSS VSS sg13_lv_nmos m=1 w=875.000n l=130.00n ng=1 nrd=0 nrs=0 +MN0 Z C VSS VSS sg13_lv_nmos m=1 w=875.000n l=130.00n ng=1 nrd=0 nrs=0 +MN2 Z A VSS VSS sg13_lv_nmos m=1 w=875.000n l=130.00n ng=1 nrd=0 nrs=0 +.ENDS +.SUBCKT RSC_IHPSG13_FILLCAP4 VDD VSS +MN0 vss_r vdd_r VSS VSS sg13_lv_nmos m=1 w=2.49u l=130.00n ng=3 nrd=0 ++ nrs=0 +MP0 vdd_r vss_r VDD VDD sg13_lv_pmos m=1 w=3.24u l=385.000n ng=2 nrd=0 ++ nrs=0 +.ENDS +.SUBCKT RSC_IHPSG13_MET2RES A B +R0 B A lvsres w=2.6e-07 l=6e-07 +.ENDS +.SUBCKT RM_IHPSG13_512x8_c2_1P_DEC04 ADDR<3> ADDR<2> ADDR<1> ADDR<0> CS ECLK_H_BOT ++ ECLK_H_TOP ECLK_L_BOT ECLK_L_TOP WL<15> WL<14> WL<13> WL<12> WL<11> WL<10> ++ WL<9> WL<8> WL<7> WL<6> WL<5> WL<4> WL<3> WL<2> WL<1> WL<0> VDD VSS +XLATCH<3> CS ADDR<3> PADR<3> VDD VSS / RSC_IHPSG13_LHPQX2 +XLATCH<2> CS ADDR<2> PADR<2> VDD VSS / RSC_IHPSG13_LHPQX2 +XLATCH<1> CS ADDR<1> PADR<1> VDD VSS / RSC_IHPSG13_LHPQX2 +XLATCH<0> CS ADDR<0> PADR<0> VDD VSS / RSC_IHPSG13_LHPQX2 +XI0<3> PADR<1> PADR<0> sel01<3> VDD VSS / RSC_IHPSG13_NAND2X2 +XI0<2> PADR<1> NADR<0> sel01<2> VDD VSS / RSC_IHPSG13_NAND2X2 +XI0<1> NADR<1> PADR<0> sel01<1> VDD VSS / RSC_IHPSG13_NAND2X2 +XI0<0> NADR<1> NADR<0> sel01<0> VDD VSS / RSC_IHPSG13_NAND2X2 +XI4 ECLK_L_BOT EN VDD VSS / RSC_IHPSG13_CINVX4 +XI5 ECLK_H_BOT ECLK_L_BOT VDD VSS / RSC_IHPSG13_CINVX2 +XI3<3> PADR<3> NADR<3> VDD VSS / RSC_IHPSG13_INVX2 +XI3<2> PADR<2> NADR<2> VDD VSS / RSC_IHPSG13_INVX2 +XI3<1> PADR<1> NADR<1> VDD VSS / RSC_IHPSG13_INVX2 +XI3<0> PADR<0> NADR<0> VDD VSS / RSC_IHPSG13_INVX2 +XI1<3> PADR<2> PADR<3> CS sel23<3> VDD VSS / RSC_IHPSG13_NAND3X2 +XI1<2> NADR<2> PADR<3> CS sel23<2> VDD VSS / RSC_IHPSG13_NAND3X2 +XI1<1> PADR<2> NADR<3> CS sel23<1> VDD VSS / RSC_IHPSG13_NAND3X2 +XI1<0> NADR<2> NADR<3> CS sel23<0> VDD VSS / RSC_IHPSG13_NAND3X2 +XI2<15> sel23<3> sel01<3> EN WL<15> VDD VSS / RSC_IHPSG13_NOR3X2 +XI2<14> sel23<3> sel01<2> EN WL<14> VDD VSS / RSC_IHPSG13_NOR3X2 +XI2<13> sel23<3> sel01<1> EN WL<13> VDD VSS / RSC_IHPSG13_NOR3X2 +XI2<12> sel23<3> sel01<0> EN WL<12> VDD VSS / RSC_IHPSG13_NOR3X2 +XI2<11> sel23<2> sel01<3> EN WL<11> VDD VSS / RSC_IHPSG13_NOR3X2 +XI2<10> sel23<2> sel01<2> EN WL<10> VDD VSS / RSC_IHPSG13_NOR3X2 +XI2<9> sel23<2> sel01<1> EN WL<9> VDD VSS / RSC_IHPSG13_NOR3X2 +XI2<8> sel23<2> sel01<0> EN WL<8> VDD VSS / RSC_IHPSG13_NOR3X2 +XI2<7> sel23<1> sel01<3> EN WL<7> VDD VSS / RSC_IHPSG13_NOR3X2 +XI2<6> sel23<1> sel01<2> EN WL<6> VDD VSS / RSC_IHPSG13_NOR3X2 +XI2<5> sel23<1> sel01<1> EN WL<5> VDD VSS / RSC_IHPSG13_NOR3X2 +XI2<4> sel23<1> sel01<0> EN WL<4> VDD VSS / RSC_IHPSG13_NOR3X2 +XI2<3> sel23<0> sel01<3> EN WL<3> VDD VSS / RSC_IHPSG13_NOR3X2 +XI2<2> sel23<0> sel01<2> EN WL<2> VDD VSS / RSC_IHPSG13_NOR3X2 +XI2<1> sel23<0> sel01<1> EN WL<1> VDD VSS / RSC_IHPSG13_NOR3X2 +XI2<0> sel23<0> sel01<0> EN WL<0> VDD VSS / RSC_IHPSG13_NOR3X2 +XCAPS4 VDD VSS / RSC_IHPSG13_FILLCAP4 +XI11 ECLK_L_BOT ECLK_L_TOP / RSC_IHPSG13_MET2RES +XR0 ECLK_H_BOT ECLK_H_TOP / RSC_IHPSG13_MET2RES +.ENDS +.SUBCKT RM_IHPSG13_512x8_c2_1P_ROWDEC4 ADDR_N_I<3> ADDR_N_I<2> ADDR_N_I<1> ADDR_N_I<0> ++ CS_I ECLK_I WL_O<15> WL_O<14> WL_O<13> WL_O<12> WL_O<11> WL_O<10> WL_O<9> ++ WL_O<8> WL_O<7> WL_O<6> WL_O<5> WL_O<4> WL_O<3> WL_O<2> WL_O<1> WL_O<0> ++ VDD VSS +XL2<8> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<7> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<6> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<5> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<4> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<3> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<2> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<1> VDD VSS / RSC_IHPSG13_FILLCAP8 +XSEL ADDR_N_I<3> ADDR_N_I<2> ADDR_N_I<1> ADDR_N_I<0> CS_I ECLK_I ECLK_H<1> ++ ECLK_B<0> ECLK_B<1> WL_O<15> WL_O<14> WL_O<13> WL_O<12> WL_O<11> WL_O<10> ++ WL_O<9> WL_O<8> WL_O<7> WL_O<6> WL_O<5> WL_O<4> WL_O<3> WL_O<2> WL_O<1> ++ WL_O<0> VDD VSS / RM_IHPSG13_512x8_c2_1P_DEC04 +.ENDS +.SUBCKT RSC_IHPSG13_CINVX8 A Z VDD VSS +MN0 Z A VSS VSS sg13_lv_nmos m=1 w=2.82u l=130.00n ng=4 nrd=0 nrs=0 +MP0 Z A VDD VDD sg13_lv_pmos m=1 w=6.48u l=130.00n ng=4 nrd=0 nrs=0 +.ENDS +.SUBCKT RSC_IHPSG13_DFNQMX2IX1 BE BI CN D QI QIN VDD VSS +MN15 net026 BI VSS VSS sg13_lv_nmos m=1 w=560.00n l=130.00n ng=1 nrd=0 ++ nrs=0 +MN14 MXI_OUT BE net026 VSS sg13_lv_nmos m=1 w=560.00n l=130.00n ng=1 nrd=0 ++ nrs=0 +MN1 net025 D VSS VSS sg13_lv_nmos m=1 w=560.00n l=130.00n ng=1 nrd=0 ++ nrs=0 +MN0 MXI_OUT BEN net025 VSS sg13_lv_nmos m=1 w=560.00n l=130.00n ng=1 nrd=0 ++ nrs=0 +MN10 QI CNN net21 VSS sg13_lv_nmos m=1 w=850.00n l=130.00n ng=1 nrd=0 nrs=0 +MN11 net21 QI_MS VSS VSS sg13_lv_nmos m=1 w=850.00n l=130.00n ng=1 ++ nrd=0 nrs=0 +MN7 net30 QI_MS VSS VSS sg13_lv_nmos m=1 w=480.00n l=130.00n ng=1 ++ nrd=0 nrs=0 +MN6 QIN_MS CNN net30 VSS sg13_lv_nmos m=1 w=480.00n l=130.00n ng=1 nrd=0 ++ nrs=0 +MN3 QI_MS QIN_MS VSS VSS sg13_lv_nmos m=1 w=480.00n l=130.00n ng=1 ++ nrd=0 nrs=0 +MN12 CNN CN VSS VSS sg13_lv_nmos m=1 w=495.000n l=130.00n ng=1 nrd=0 ++ nrs=0 +MN9 net37 MXI_OUT VSS VSS sg13_lv_nmos m=1 w=870.00n l=130.00n ng=1 ++ nrd=0 nrs=0 +MN8 QIN_MS CN net37 VSS sg13_lv_nmos m=1 w=870.00n l=130.00n ng=1 nrd=0 ++ nrs=0 +MN5 QI CN net25 VSS sg13_lv_nmos m=1 w=480.00n l=130.00n ng=1 nrd=0 nrs=0 +MN4 net25 QIN VSS VSS sg13_lv_nmos m=1 w=480.00n l=130.00n ng=1 nrd=0 ++ nrs=0 +MN2 QIN QI VSS VSS sg13_lv_nmos m=1 w=480.00n l=130.00n ng=1 nrd=0 ++ nrs=0 +MN13 BEN BE VSS VSS sg13_lv_nmos m=1 w=560.00n l=130.00n ng=1 nrd=0 ++ nrs=0 +MP15 MXI_OUT BEN net027 VDD sg13_lv_pmos m=1 w=985.000n l=130.00n ng=1 ++ nrd=0 nrs=0 +MP14 net027 BI VDD VDD sg13_lv_pmos m=1 w=985.000n l=130.00n ng=1 ++ nrd=0 nrs=0 +MP1 MXI_OUT BE net024 VDD sg13_lv_pmos m=1 w=985.000n l=130.00n ng=1 nrd=0 ++ nrs=0 +MP0 net024 D VDD VDD sg13_lv_pmos m=1 w=985.000n l=130.00n ng=1 nrd=0 ++ nrs=0 +MP13 BEN BE VDD VDD sg13_lv_pmos m=1 w=645.000n l=130.00n ng=1 nrd=0 ++ nrs=0 +MP6 QI_MS QIN_MS VDD VDD sg13_lv_pmos m=1 w=480.00n l=130.00n ng=1 ++ nrd=0 nrs=0 +MP3 QI CNN net27 VDD sg13_lv_pmos m=1 w=480.00n l=130.00n ng=1 nrd=0 nrs=0 +MP2 net27 QIN VDD VDD sg13_lv_pmos m=1 w=480.00n l=130.00n ng=1 nrd=0 ++ nrs=0 +MP10 net36 MXI_OUT VDD VDD sg13_lv_pmos m=1 w=975.000n l=130.00n ng=1 ++ nrd=0 nrs=0 +MP11 QIN_MS CNN net36 VDD sg13_lv_pmos m=1 w=975.000n l=130.00n ng=1 nrd=0 ++ nrs=0 +MP4 net32 QI_MS VDD VDD sg13_lv_pmos m=1 w=480.00n l=130.00n ng=1 ++ nrd=0 nrs=0 +MP5 QIN_MS CN net32 VDD sg13_lv_pmos m=1 w=480.00n l=130.00n ng=1 nrd=0 ++ nrs=0 +MP7 QIN QI VDD VDD sg13_lv_pmos m=1 w=480.00n l=130.00n ng=1 nrd=0 ++ nrs=0 +MP12 CNN CN VDD VDD sg13_lv_pmos m=1 w=480.00n l=130.00n ng=1 nrd=0 ++ nrs=0 +MP9 QI CN net19 VDD sg13_lv_pmos m=1 w=990.00n l=130.00n ng=1 nrd=0 nrs=0 +MP8 net19 QI_MS VDD VDD sg13_lv_pmos m=1 w=990.00n l=130.00n ng=1 ++ nrd=0 nrs=0 +.ENDS +.SUBCKT RM_IHPSG13_512x8_c2_1P_ROWREG4 ACLK_N_I ADDR_I<3> ADDR_I<2> ADDR_I<1> ADDR_I<0> ++ ADDR_N_O<3> ADDR_N_O<2> ADDR_N_O<1> ADDR_N_O<0> BIST_ADDR_I<3> ++ BIST_ADDR_I<2> BIST_ADDR_I<1> BIST_ADDR_I<0> BIST_EN_I VDD VSS +XINV<3> q_int<3> qn_int<3> VDD VSS / RSC_IHPSG13_CINVX2 +XINV<2> q_int<2> qn_int<2> VDD VSS / RSC_IHPSG13_CINVX2 +XINV<1> q_int<1> qn_int<1> VDD VSS / RSC_IHPSG13_CINVX2 +XINV<0> q_int<0> qn_int<0> VDD VSS / RSC_IHPSG13_CINVX2 +XDRV<3> qn_int<3> ADDR_N_O<3> VDD VSS / RSC_IHPSG13_CINVX8 +XDRV<2> qn_int<2> ADDR_N_O<2> VDD VSS / RSC_IHPSG13_CINVX8 +XDRV<1> qn_int<1> ADDR_N_O<1> VDD VSS / RSC_IHPSG13_CINVX8 +XDRV<0> qn_int<0> ADDR_N_O<0> VDD VSS / RSC_IHPSG13_CINVX8 +XDFF<3> BIST_EN_I BIST_ADDR_I<3> ACLK_N_I ADDR_I<3> q_int<3> net2<0> VDD ++ VSS / RSC_IHPSG13_DFNQMX2IX1 +XDFF<2> BIST_EN_I BIST_ADDR_I<2> ACLK_N_I ADDR_I<2> q_int<2> net2<1> VDD ++ VSS / RSC_IHPSG13_DFNQMX2IX1 +XDFF<1> BIST_EN_I BIST_ADDR_I<1> ACLK_N_I ADDR_I<1> q_int<1> net2<2> VDD ++ VSS / RSC_IHPSG13_DFNQMX2IX1 +XDFF<0> BIST_EN_I BIST_ADDR_I<0> ACLK_N_I ADDR_I<0> q_int<0> net2<3> VDD ++ VSS / RSC_IHPSG13_DFNQMX2IX1 +XI11<20> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI11<19> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI11<18> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI11<17> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI11<16> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI11<15> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI11<14> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI11<13> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI11<12> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI11<11> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI11<10> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI11<9> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI11<8> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI11<7> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI11<6> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI11<5> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI11<4> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI11<3> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI11<2> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI11<1> VDD VSS / RSC_IHPSG13_FILLCAP8 +.ENDS +.SUBCKT RSC_IHPSG13_CDLYX1 A Z VDD VSS +MN1 net010 net032 VSS VSS sg13_lv_nmos m=1 w=300.0n l=160.00n ng=1 ++ nrd=0 nrs=0 +MN2 net032 A net014 VSS sg13_lv_nmos m=1 w=300.0n l=160.00n ng=1 nrd=0 ++ nrs=0 +MN0 Z net032 net010 VSS sg13_lv_nmos m=1 w=300.0n l=160.00n ng=1 nrd=0 ++ nrs=0 +MN3 net014 A VSS VSS sg13_lv_nmos m=1 w=300.0n l=160.00n ng=1 nrd=0 ++ nrs=0 +MP1 Z net032 net07 VDD sg13_lv_pmos m=1 w=720.00n l=160.00n ng=1 nrd=0 ++ nrs=0 +MP3 net011 A VDD VDD sg13_lv_pmos m=1 w=720.00n l=160.00n ng=1 nrd=0 ++ nrs=0 +MP0 net07 net032 VDD VDD sg13_lv_pmos m=1 w=720.00n l=160.00n ng=1 ++ nrd=0 nrs=0 +MP2 net032 A net011 VDD sg13_lv_pmos m=1 w=720.00n l=160.00n ng=1 nrd=0 ++ nrs=0 +.ENDS +.SUBCKT RSC_IHPSG13_CDLYX1_DUMMY A Z VDD VSS +MN0 vss_r vdd_r VSS VSS sg13_lv_nmos m=1 w=2.49u l=300.0n ng=3 nrd=0 ++ nrs=0 +MP0 vdd_r vss_r VDD VDD sg13_lv_pmos m=1 w=3.24u l=640.00n ng=2 nrd=0 ++ nrs=0 +R0 Z A lvsres w=2.6e-07 l=6e-07 +.ENDS + +.SUBCKT RSC_IHPSG13_MX2IX1 A0 A1 S ZN VDD VSS +MP4 SN S VDD VDD sg13_lv_pmos m=1 w=645.000n l=130.00n ng=1 nrd=0 nrs=0 +MP3 ZN SN net12 VDD sg13_lv_pmos m=1 w=985.000n l=130.00n ng=1 nrd=0 nrs=0 +MP2 net12 A1 VDD VDD sg13_lv_pmos m=1 w=985.000n l=130.00n ng=1 nrd=0 ++ nrs=0 +MP1 ZN S net17 VDD sg13_lv_pmos m=1 w=985.000n l=130.00n ng=1 nrd=0 nrs=0 +MP0 net17 A0 VDD VDD sg13_lv_pmos m=1 w=985.000n l=130.00n ng=1 nrd=0 ++ nrs=0 +MN5 SN S VSS VSS sg13_lv_nmos m=1 w=480.00n l=130.00n ng=1 nrd=0 nrs=0 +MN3 net13 A1 VSS VSS sg13_lv_nmos m=1 w=480.00n l=130.00n ng=1 nrd=0 ++ nrs=0 +MN2 ZN S net13 VSS sg13_lv_nmos m=1 w=480.00n l=130.00n ng=1 nrd=0 nrs=0 +MN1 net15 A0 VSS VSS sg13_lv_nmos m=1 w=480.00n l=130.00n ng=1 nrd=0 ++ nrs=0 +MN0 ZN SN net15 VSS sg13_lv_nmos m=1 w=480.00n l=130.00n ng=1 nrd=0 nrs=0 +.ENDS +.SUBCKT RM_IHPSG13_512x8_c2_1P_DLY_MUX A SEL Z VDD VSS +XI11 net4 Z VDD VSS / RSC_IHPSG13_CINVX2 +XI8 A D<3> SEL net4 VDD VSS / RSC_IHPSG13_MX2IX1 +XI20<3> D<2> D<3> VDD VSS / RSC_IHPSG13_CDLYX1 +XI20<2> D<1> D<2> VDD VSS / RSC_IHPSG13_CDLYX1 +XI20<1> A D<1> VDD VSS / RSC_IHPSG13_CDLYX1 +.ENDS +.SUBCKT RSC_IHPSG13_DFNQX2 CN D Q VDD VSS +MN0 Q QIN_SL VSS VSS sg13_lv_nmos m=1 w=980.00n l=130.00n ng=1 nrd=0 ++ nrs=0 +MN10 QIN_SL CNN net21 VSS sg13_lv_nmos m=1 w=850.00n l=130.00n ng=1 nrd=0 ++ nrs=0 +MN11 net21 QI_MS VSS VSS sg13_lv_nmos m=1 w=850.00n l=130.00n ng=1 ++ nrd=0 nrs=0 +MN7 net30 QI_MS VSS VSS sg13_lv_nmos m=1 w=480.00n l=130.00n ng=1 ++ nrd=0 nrs=0 +MN6 QIN_MS CNN net30 VSS sg13_lv_nmos m=1 w=480.00n l=130.00n ng=1 nrd=0 ++ nrs=0 +MN3 QI_MS QIN_MS VSS VSS sg13_lv_nmos m=1 w=480.00n l=130.00n ng=1 ++ nrd=0 nrs=0 +MN12 CNN CN VSS VSS sg13_lv_nmos m=1 w=495.000n l=130.00n ng=1 nrd=0 ++ nrs=0 +MN9 net37 D VSS VSS sg13_lv_nmos m=1 w=870.00n l=130.00n ng=1 nrd=0 ++ nrs=0 +MN8 QIN_MS CN net37 VSS sg13_lv_nmos m=1 w=870.00n l=130.00n ng=1 nrd=0 ++ nrs=0 +MN5 QIN_SL CN net25 VSS sg13_lv_nmos m=1 w=480.00n l=130.00n ng=1 nrd=0 ++ nrs=0 +MN4 net25 QI_SL VSS VSS sg13_lv_nmos m=1 w=480.00n l=130.00n ng=1 ++ nrd=0 nrs=0 +MN2 QI_SL QIN_SL VSS VSS sg13_lv_nmos m=1 w=480.00n l=130.00n ng=1 ++ nrd=0 nrs=0 +MP0 Q QIN_SL VDD VDD sg13_lv_pmos m=1 w=1.62u l=130.00n ng=1 nrd=0 ++ nrs=0 +MP6 QI_MS QIN_MS VDD VDD sg13_lv_pmos m=1 w=480.00n l=130.00n ng=1 ++ nrd=0 nrs=0 +MP3 QIN_SL CNN net27 VDD sg13_lv_pmos m=1 w=480.00n l=130.00n ng=1 nrd=0 ++ nrs=0 +MP2 net27 QI_SL VDD VDD sg13_lv_pmos m=1 w=480.00n l=130.00n ng=1 ++ nrd=0 nrs=0 +MP10 net36 D VDD VDD sg13_lv_pmos m=1 w=975.000n l=130.00n ng=1 nrd=0 ++ nrs=0 +MP11 QIN_MS CNN net36 VDD sg13_lv_pmos m=1 w=975.000n l=130.00n ng=1 nrd=0 ++ nrs=0 +MP4 net32 QI_MS VDD VDD sg13_lv_pmos m=1 w=480.00n l=130.00n ng=1 ++ nrd=0 nrs=0 +MP5 QIN_MS CN net32 VDD sg13_lv_pmos m=1 w=480.00n l=130.00n ng=1 nrd=0 ++ nrs=0 +MP7 QI_SL QIN_SL VDD VDD sg13_lv_pmos m=1 w=480.00n l=130.00n ng=1 ++ nrd=0 nrs=0 +MP12 CNN CN VDD VDD sg13_lv_pmos m=1 w=480.00n l=130.00n ng=1 nrd=0 ++ nrs=0 +MP9 QIN_SL CN net19 VDD sg13_lv_pmos m=1 w=990.00n l=130.00n ng=1 nrd=0 ++ nrs=0 +MP8 net19 QI_MS VDD VDD sg13_lv_pmos m=1 w=990.00n l=130.00n ng=1 ++ nrd=0 nrs=0 +.ENDS +.SUBCKT RSC_IHPSG13_CNAND2X2 A B Z VDD VSS +MN0 Z B net6 VSS sg13_lv_nmos m=1 w=980.00n l=130.00n ng=1 nrd=0 nrs=0 +MN1 net6 A VSS VSS sg13_lv_nmos m=1 w=980.00n l=130.00n ng=1 nrd=0 ++ nrs=0 +MP1 Z B VDD VDD sg13_lv_pmos m=1 w=1.62u l=130.00n ng=1 nrd=0 nrs=0 +MP0 Z A VDD VDD sg13_lv_pmos m=1 w=1.62u l=130.00n ng=1 nrd=0 nrs=0 +.ENDS +.SUBCKT RSC_IHPSG13_CGATEPX4 CP E Q VDD VSS +MN1 net08 QIN VSS VSS sg13_lv_nmos m=1 w=480.00n l=130.00n ng=1 nrd=0 ++ nrs=0 +MN2 net019 net08 VSS VSS sg13_lv_nmos m=1 w=480.00n l=130.00n ng=1 ++ nrd=0 nrs=0 +MN3 QIN CP net019 VSS sg13_lv_nmos m=1 w=480.00n l=130.00n ng=1 nrd=0 nrs=0 +MN6 Q net015 VSS VSS sg13_lv_nmos m=1 w=1.41u l=130.00n ng=2 nrd=0 ++ nrs=0 +MN5 net015 net08 net018 VSS sg13_lv_nmos m=1 w=980.00n l=130.00n ng=1 ++ nrd=0 nrs=0 +MN8 QIN CPN net023 VSS sg13_lv_nmos m=1 w=870.00n l=130.00n ng=1 nrd=0 ++ nrs=0 +MN7 net023 E VSS VSS sg13_lv_nmos m=1 w=870.00n l=130.00n ng=1 nrd=0 ++ nrs=0 +MN4 net018 CP VSS VSS sg13_lv_nmos m=1 w=980.00n l=130.00n ng=1 nrd=0 ++ nrs=0 +MN0 CPN CP VSS VSS sg13_lv_nmos m=1 w=500.0n l=130.00n ng=1 nrd=0 nrs=0 +MP3 net08 QIN VDD VDD sg13_lv_pmos m=1 w=480.00n l=130.00n ng=1 nrd=0 ++ nrs=0 +MP2 QIN CPN net017 VDD sg13_lv_pmos m=1 w=480.00n l=130.00n ng=1 nrd=0 ++ nrs=0 +MP1 net017 net08 VDD VDD sg13_lv_pmos m=1 w=480.00n l=130.00n ng=1 ++ nrd=0 nrs=0 +MP0 CPN CP VDD VDD sg13_lv_pmos m=1 w=500.0n l=130.00n ng=1 nrd=0 nrs=0 +MP8 QIN CP net024 VDD sg13_lv_pmos m=1 w=975.000n l=130.00n ng=1 nrd=0 ++ nrs=0 +MP7 net024 E VDD VDD sg13_lv_pmos m=1 w=975.000n l=130.00n ng=1 nrd=0 ++ nrs=0 +MP4 net015 CP VDD VDD sg13_lv_pmos m=1 w=1.27u l=130.00n ng=1 nrd=0 ++ nrs=0 +MP6 Q net015 VDD VDD sg13_lv_pmos m=1 w=3.24u l=130.00n ng=2 nrd=0 ++ nrs=0 +MP5 net015 net08 VDD VDD sg13_lv_pmos m=1 w=1.27u l=130.00n ng=1 nrd=0 ++ nrs=0 +.ENDS +.SUBCKT RSC_IHPSG13_CBUFX8 A Z VDD VSS +MP0 net4 A VDD VDD sg13_lv_pmos m=1 w=3.24u l=130.00n ng=2 nrd=0 nrs=0 +MP1 Z net4 VDD VDD sg13_lv_pmos m=1 w=6.48u l=130.00n ng=4 nrd=0 nrs=0 +MN1 Z net4 VSS VSS sg13_lv_nmos m=1 w=2.82u l=130.00n ng=4 nrd=0 nrs=0 +MN0 net4 A VSS VSS sg13_lv_nmos m=1 w=1.41u l=130.00n ng=2 nrd=0 nrs=0 +.ENDS +.SUBCKT RSC_IHPSG13_CDLYX2 A Z VDD VSS +MN2 net4 A net9 VSS sg13_lv_nmos m=1 w=320.00n l=200.0n ng=1 nrd=0 nrs=0 +MN0 Z net4 VSS VSS sg13_lv_nmos m=1 w=705.000n l=130.00n ng=1 nrd=0 ++ nrs=0 +MN1 net9 A VSS VSS sg13_lv_nmos m=1 w=320.00n l=200.0n ng=1 nrd=0 nrs=0 +MP2 net4 A net10 VDD sg13_lv_pmos m=1 w=1.2u l=200.0n ng=1 nrd=0 nrs=0 +MP1 net10 A VDD VDD sg13_lv_pmos m=1 w=1.2u l=200.0n ng=1 nrd=0 nrs=0 +MP0 Z net4 VDD VDD sg13_lv_pmos m=1 w=1.62u l=130.00n ng=1 nrd=0 nrs=0 +.ENDS +.SUBCKT RSC_IHPSG13_MX2X2 A0 A1 S Z VDD VSS +MP6 Z net010 VDD VDD sg13_lv_pmos m=1 w=1.62u l=130.00n ng=1 nrd=0 ++ nrs=0 +MP4 SN S VDD VDD sg13_lv_pmos m=1 w=645.000n l=130.00n ng=1 nrd=0 nrs=0 +MP3 net010 SN net12 VDD sg13_lv_pmos m=1 w=985.000n l=130.00n ng=1 nrd=0 ++ nrs=0 +MP2 net12 A1 VDD VDD sg13_lv_pmos m=1 w=985.000n l=130.00n ng=1 nrd=0 ++ nrs=0 +MP1 net010 S net17 VDD sg13_lv_pmos m=1 w=985.000n l=130.00n ng=1 nrd=0 ++ nrs=0 +MP0 net17 A0 VDD VDD sg13_lv_pmos m=1 w=985.000n l=130.00n ng=1 nrd=0 ++ nrs=0 +MN6 Z net010 VSS VSS sg13_lv_nmos m=1 w=705.000n l=130.00n ng=1 nrd=0 ++ nrs=0 +MN5 SN S VSS VSS sg13_lv_nmos m=1 w=560.00n l=130.00n ng=1 nrd=0 nrs=0 +MN3 net13 A1 VSS VSS sg13_lv_nmos m=1 w=560.00n l=130.00n ng=1 nrd=0 ++ nrs=0 +MN2 net010 S net13 VSS sg13_lv_nmos m=1 w=560.00n l=130.00n ng=1 nrd=0 ++ nrs=0 +MN1 net15 A0 VSS VSS sg13_lv_nmos m=1 w=560.00n l=130.00n ng=1 nrd=0 ++ nrs=0 +MN0 net010 SN net15 VSS sg13_lv_nmos m=1 w=560.00n l=130.00n ng=1 nrd=0 ++ nrs=0 +.ENDS +.SUBCKT RSC_IHPSG13_AND2X2 A B Z VDD VSS +MN3 Z net6 VSS VSS sg13_lv_nmos m=1 w=980.00n l=130.00n ng=1 nrd=0 ++ nrs=0 +MN4 net9 B VSS VSS sg13_lv_nmos m=1 w=500.0n l=130.00n ng=1 nrd=0 nrs=0 +MN6 net6 A net9 VSS sg13_lv_nmos m=1 w=500.0n l=130.00n ng=1 nrd=0 nrs=0 +MP2 Z net6 VDD VDD sg13_lv_pmos m=1 w=1.62u l=130.00n ng=1 nrd=0 nrs=0 +MP0 net6 B VDD VDD sg13_lv_pmos m=1 w=860.00n l=130.00n ng=1 nrd=0 ++ nrs=0 +MP1 net6 A VDD VDD sg13_lv_pmos m=1 w=860.00n l=130.00n ng=1 nrd=0 ++ nrs=0 +.ENDS +.SUBCKT RSC_IHPSG13_TIEL Z VDD VSS +MN0 Z net2 VSS VSS sg13_lv_nmos m=1 w=480.00n l=130.00n ng=1 nrd=0 ++ nrs=0 +MP0 net2 net2 VDD VDD sg13_lv_pmos m=1 w=480.00n l=130.00n ng=1 nrd=0 ++ nrs=0 +.ENDS +.SUBCKT RSC_IHPSG13_XOR2X2 A B Z VDD VSS +MP8 net012 B net7 VDD sg13_lv_pmos m=1 w=825.000n l=130.00n ng=1 nrd=0 ++ nrs=0 +MP7 net011 net3 net012 VDD sg13_lv_pmos m=1 w=825.000n l=130.00n ng=1 ++ nrd=0 nrs=0 +MP6 Z net012 VDD VDD sg13_lv_pmos m=1 w=1.535u l=130.00n ng=1 nrd=0 ++ nrs=0 +MP2 net7 A VDD VDD sg13_lv_pmos m=1 w=825.000n l=130.00n ng=1 nrd=0 ++ nrs=0 +MP4 net011 net7 VDD VDD sg13_lv_pmos m=1 w=825.000n l=130.00n ng=1 ++ nrd=0 nrs=0 +MP5 net3 B VDD VDD sg13_lv_pmos m=1 w=580.00n l=130.00n ng=1 nrd=0 ++ nrs=0 +MN7 net012 B net011 VSS sg13_lv_nmos m=1 w=555.000n l=130.00n ng=1 nrd=0 ++ nrs=0 +MN6 net7 net3 net012 VSS sg13_lv_nmos m=1 w=555.000n l=130.00n ng=1 nrd=0 ++ nrs=0 +MN5 Z net012 VSS VSS sg13_lv_nmos m=1 w=775.000n l=130.00n ng=1 nrd=0 ++ nrs=0 +MN2 net7 A VSS VSS sg13_lv_nmos m=1 w=555.000n l=130.00n ng=1 nrd=0 ++ nrs=0 +MN4 net3 B VSS VSS sg13_lv_nmos m=1 w=480.00n l=130.00n ng=1 nrd=0 ++ nrs=0 +MN3 net011 net7 VSS VSS sg13_lv_nmos m=1 w=555.000n l=130.00n ng=1 ++ nrd=0 nrs=0 +.ENDS +.SUBCKT RSC_IHPSG13_OA12X1 A B C Z VDD VSS +MN2 net7 C VSS VSS sg13_lv_nmos m=1 w=980.00n l=130.00n ng=1 nrd=0 ++ nrs=0 +MN3 Z net17 VSS VSS sg13_lv_nmos m=1 w=500.0n l=130.00n ng=1 nrd=0 ++ nrs=0 +MN1 net17 B net7 VSS sg13_lv_nmos m=1 w=980.00n l=130.00n ng=1 nrd=0 nrs=0 +MN0 net17 A net7 VSS sg13_lv_nmos m=1 w=980.00n l=130.00n ng=1 nrd=0 nrs=0 +MP0 net24 A VDD VDD sg13_lv_pmos m=1 w=1.62u l=130.00n ng=1 nrd=0 nrs=0 +MP3 Z net17 VDD VDD sg13_lv_pmos m=1 w=905.000n l=130.00n ng=1 nrd=0 ++ nrs=0 +MP1 net17 B net24 VDD sg13_lv_pmos m=1 w=1.62u l=130.00n ng=1 nrd=0 nrs=0 +MP2 net17 C VDD VDD sg13_lv_pmos m=1 w=905.000n l=130.00n ng=1 nrd=0 ++ nrs=0 +.ENDS +.SUBCKT RM_IHPSG13_512x8_c2_1P_CTRL ACLK_N BIST_CK_I BIST_CS_I BIST_EN BIST_RE_I ++ BIST_WE_I B_TIEL_O CK_I CS_I DCLK ECLK PULSE_H PULSE_L PULSE_O RCLK RE_I ++ ROW_CS WCLK WE_I VDD VSS +XI17 ck_regs we col_we VDD VSS / RSC_IHPSG13_DFNQX2 +XI16 ck_regs re col_re VDD VSS / RSC_IHPSG13_DFNQX2 +XI18 ck_regs cs net7 VDD VSS / RSC_IHPSG13_DFNQX2 +XI71 ACLK_N net012 PULSE_O VDD VSS / RSC_IHPSG13_DFNQX2 +XI77 col_we net9 net016 VDD VSS / RSC_IHPSG13_CNAND2X2 +XI76 col_re net9 net018 VDD VSS / RSC_IHPSG13_CNAND2X2 +XI15 ck_dly WEorREandCS aclk VDD VSS / RSC_IHPSG13_CGATEPX4 +XI14 ck WEandCS DCLK VDD VSS / RSC_IHPSG13_CGATEPX4 +XI60 net7 ROW_CS VDD VSS / RSC_IHPSG13_CBUFX8 +XI73 PULSE_O net012 VDD VSS / RSC_IHPSG13_CINVX2 +XI8 net9 net8 VDD VSS / RSC_IHPSG13_CINVX2 +XI64 ck ck_dly VDD VSS / RSC_IHPSG13_CDLYX2 +XI86 CS_I BIST_CS_I BIST_EN cs VDD VSS / RSC_IHPSG13_MX2X2 +XI87 CK_I BIST_CK_I BIST_EN ck VDD VSS / RSC_IHPSG13_MX2X2 +XI85 WE_I BIST_WE_I BIST_EN we VDD VSS / RSC_IHPSG13_MX2X2 +XI84 RE_I BIST_RE_I BIST_EN re VDD VSS / RSC_IHPSG13_MX2X2 +XI22 we cs WEandCS VDD VSS / RSC_IHPSG13_AND2X2 +XBM_TIEL B_TIEL_O VDD VSS / RSC_IHPSG13_TIEL +XI48 ck_dly ck_regs VDD VSS / RSC_IHPSG13_CINVX4 +XI81 net016 WCLK VDD VSS / RSC_IHPSG13_CINVX4 +XI80 net018 RCLK VDD VSS / RSC_IHPSG13_CINVX4 +XI78 net8 net020 VDD VSS / RSC_IHPSG13_CINVX4 +XI6 PULSE_L PULSE_H net9 VDD VSS / RSC_IHPSG13_XOR2X2 +XI79 net020 ECLK VDD VSS / RSC_IHPSG13_CINVX8 +XI63 aclk ACLK_N VDD VSS / RSC_IHPSG13_CINVX8 +XI21 re we cs WEorREandCS VDD VSS / RSC_IHPSG13_OA12X1 +.ENDS +.SUBCKT RM_IHPSG13_512x8_c2_1P_COLDEC2 ACLK_N ADDR<1> ADDR<0> ADDR_COL<1> ADDR_COL<0> ++ ADDR_DEC<7> ADDR_DEC<6> ADDR_DEC<5> ADDR_DEC<4> ADDR_DEC<3> ADDR_DEC<2> ++ ADDR_DEC<1> ADDR_DEC<0> BIST_ADDR<1> BIST_ADDR<0> BIST_EN_I VDD VSS +XI14<5> VDD VSS / RSC_IHPSG13_FILLCAP4 +XI14<4> VDD VSS / RSC_IHPSG13_FILLCAP4 +XI14<3> VDD VSS / RSC_IHPSG13_FILLCAP4 +XI14<2> VDD VSS / RSC_IHPSG13_FILLCAP4 +XI14<1> VDD VSS / RSC_IHPSG13_FILLCAP4 +XDFF<1> BIST_EN_I BIST_ADDR<1> ACLK_N ADDR<1> padr_int<1> net6<0> VDD ++ VSS / RSC_IHPSG13_DFNQMX2IX1 +XDFF<0> BIST_EN_I BIST_ADDR<0> ACLK_N ADDR<0> padr_int<0> net6<1> VDD ++ VSS / RSC_IHPSG13_DFNQMX2IX1 +XI1<3> PADR<1> PADR<0> addr_n<3> VDD VSS / RSC_IHPSG13_NAND2X2 +XI1<2> PADR<1> NADR<0> addr_n<2> VDD VSS / RSC_IHPSG13_NAND2X2 +XI1<1> NADR<1> PADR<0> addr_n<1> VDD VSS / RSC_IHPSG13_NAND2X2 +XI1<0> NADR<1> NADR<0> addr_n<0> VDD VSS / RSC_IHPSG13_NAND2X2 +XI16<37> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI16<36> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI16<35> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI16<34> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI16<33> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI16<32> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI16<31> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI16<30> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI16<29> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI16<28> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI16<27> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI16<26> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI16<25> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI16<24> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI16<23> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI16<22> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI16<21> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI16<20> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI16<19> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI16<18> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI16<17> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI16<16> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI16<15> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI16<14> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI16<13> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI16<12> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI16<11> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI16<10> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI16<9> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI16<8> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI16<7> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI16<6> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI16<5> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI16<4> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI16<3> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI16<2> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI16<1> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI3<1> padr_int<1> NADR<1> VDD VSS / RSC_IHPSG13_INVX2 +XI3<0> padr_int<0> NADR<0> VDD VSS / RSC_IHPSG13_INVX2 +XI13<1> NADR<1> PADR<1> VDD VSS / RSC_IHPSG13_INVX2 +XI13<0> NADR<0> PADR<0> VDD VSS / RSC_IHPSG13_INVX2 +XI2<3> addr_n<3> ADDR_DEC<3> VDD VSS / RSC_IHPSG13_INVX2 +XI2<2> addr_n<2> ADDR_DEC<2> VDD VSS / RSC_IHPSG13_INVX2 +XI2<1> addr_n<1> ADDR_DEC<1> VDD VSS / RSC_IHPSG13_INVX2 +XI2<0> addr_n<0> ADDR_DEC<0> VDD VSS / RSC_IHPSG13_INVX2 +XI15<1> ADDR_COL<1> VDD VSS / RSC_IHPSG13_TIEL +XI15<0> ADDR_COL<0> VDD VSS / RSC_IHPSG13_TIEL +XI17<3> ADDR_DEC<7> VDD VSS / RSC_IHPSG13_TIEL +XI17<2> ADDR_DEC<6> VDD VSS / RSC_IHPSG13_TIEL +XI17<1> ADDR_DEC<5> VDD VSS / RSC_IHPSG13_TIEL +XI17<0> ADDR_DEC<4> VDD VSS / RSC_IHPSG13_TIEL +.ENDS +.SUBCKT RSC_IHPSG13_NOR2X2 A B Z VDD VSS +MP1 Z B net9 VDD sg13_lv_pmos m=1 w=1.62u l=130.00n ng=1 nrd=0 nrs=0 +MP0 net9 A VDD VDD sg13_lv_pmos m=1 w=1.62u l=130.00n ng=1 nrd=0 nrs=0 +MN0 Z B VSS VSS sg13_lv_nmos m=1 w=980.00n l=130.00n ng=1 nrd=0 nrs=0 +MN1 Z A VSS VSS sg13_lv_nmos m=1 w=980.00n l=130.00n ng=1 nrd=0 nrs=0 +.ENDS +.SUBCKT RSC_IHPSG13_CINVX4_WN A Z VDD VSS +MN0 Z A VSS VSS sg13_lv_nmos m=1 w=705.000n l=130.00n ng=1 nrd=0 nrs=0 +MP0 Z A VDD VDD sg13_lv_pmos m=1 w=3.24u l=130.00n ng=2 nrd=0 nrs=0 +.ENDS +.SUBCKT RM_IHPSG13_512x8_c2_1P_BLDRV BLC BLC_SEL BLT BLT_SEL PRE_N SEL_P WR_ONE WR_ZERO ++ VDD VSS +XCDEC SEL_P WR_ZERO BLC_PMOS_DRIVE VDD VSS / RSC_IHPSG13_NAND2X2 +XTDEC SEL_P WR_ONE BLT_PMOS_DRIVE VDD VSS / RSC_IHPSG13_NAND2X2 +MTWN BLT BLT_NMOS_DRIVE VSS VSS sg13_lv_nmos m=1 w=4.82u l=130.00n ++ ng=2 nrd=0 nrs=0 +MCWN BLC BLC_NMOS_DRIVE VSS VSS sg13_lv_nmos m=1 w=4.82u l=130.00n ++ ng=2 nrd=0 nrs=0 +MCWP BLC BLC_PMOS_DRIVE VDD VDD sg13_lv_pmos m=1 w=1.5u l=130.00n ng=1 ++ nrd=0 nrs=0 +MTWP BLT BLT_PMOS_DRIVE VDD VDD sg13_lv_pmos m=1 w=1.5u l=130.00n ng=1 ++ nrd=0 nrs=0 +MTSP BLT_SEL SEL_N BLT VDD sg13_lv_pmos m=1 w=1.5u l=130.00n ng=1 nrd=0 ++ nrs=0 +MTPR BLT PRE_N VDD VDD sg13_lv_pmos m=1 w=3.000u l=130.00n ng=2 nrd=0 ++ nrs=0 +MCSP BLC_SEL SEL_N BLC VDD sg13_lv_pmos m=1 w=1.5u l=130.00n ng=1 nrd=0 ++ nrs=0 +MCPR BLC PRE_N VDD VDD sg13_lv_pmos m=1 w=3.000u l=130.00n ng=2 nrd=0 ++ nrs=0 +XI86 SEL_P SEL_N VDD VSS / RSC_IHPSG13_INVX2 +XTINV BLC_PMOS_DRIVE BLT_NMOS_DRIVE VDD VSS / RSC_IHPSG13_INVX2 +XCINV BLT_PMOS_DRIVE BLC_NMOS_DRIVE VDD VSS / RSC_IHPSG13_INVX2 +.ENDS +.SUBCKT RSC_IHPSG13_TIEH Z VDD VSS +MN0 net2 net2 VSS VSS sg13_lv_nmos m=1 w=480.00n l=130.00n ng=1 nrd=0 ++ nrs=0 +MP0 Z net2 VDD VDD sg13_lv_pmos m=1 w=480.00n l=130.00n ng=1 nrd=0 ++ nrs=0 +.ENDS +.SUBCKT RSC_IHPSG13_MET3RES A B +R0 B A lvsres w=2.6e-07 l=6e-07 +.ENDS +.SUBCKT RSC_IHPSG13_DFPQD_MSAFFX2 CP DN DP QN QP VDD VSS +MN12 SN RN DIFFP VSS sg13_lv_nmos m=1 w=2.4u l=200.0n ng=2 nrd=0 nrs=0 +MN13 TAIL CP VSS VSS sg13_lv_nmos m=1 w=2.4u l=130.00n ng=2 nrd=0 nrs=0 +MN9 DIFFP DP TAIL VSS sg13_lv_nmos m=1 w=2.4u l=200.0n ng=2 nrd=0 nrs=0 +MN10 DIFFN DN TAIL VSS sg13_lv_nmos m=1 w=2.4u l=200.0n ng=2 nrd=0 nrs=0 +MN11 RN SN DIFFN VSS sg13_lv_nmos m=1 w=2.4u l=200.0n ng=2 nrd=0 nrs=0 +MN19 net33 SN VSS VSS sg13_lv_nmos m=1 w=980.00n l=130.00n ng=1 nrd=0 ++ nrs=0 +MN20 QN QP net37 VSS sg13_lv_nmos m=1 w=980.00n l=130.00n ng=1 nrd=0 nrs=0 +MN18 net37 RN VSS VSS sg13_lv_nmos m=1 w=980.00n l=130.00n ng=1 nrd=0 ++ nrs=0 +MN17 QP QN net33 VSS sg13_lv_nmos m=1 w=980.00n l=130.00n ng=1 nrd=0 nrs=0 +MP15 SN RN VDD VDD sg13_lv_pmos m=1 w=800.0n l=130.00n ng=1 nrd=0 nrs=0 +MP16 RN CP VDD VDD sg13_lv_pmos m=1 w=800.0n l=130.00n ng=1 nrd=0 nrs=0 +MP14 DIFFP CP VDD VDD sg13_lv_pmos m=1 w=800.0n l=130.00n ng=1 nrd=0 ++ nrs=0 +MP12 RN SN VDD VDD sg13_lv_pmos m=1 w=800.0n l=130.00n ng=1 nrd=0 nrs=0 +MP13 DIFFN CP VDD VDD sg13_lv_pmos m=1 w=800.0n l=130.00n ng=1 nrd=0 ++ nrs=0 +MP11 SN CP VDD VDD sg13_lv_pmos m=1 w=800.0n l=130.00n ng=1 nrd=0 nrs=0 +MP19 QN QP VDD VDD sg13_lv_pmos m=1 w=900.0n l=130.00n ng=1 nrd=0 nrs=0 +MP20 QP SN VDD VDD sg13_lv_pmos m=1 w=1.8u l=130.00n ng=2 nrd=0 nrs=0 +MP18 QN RN VDD VDD sg13_lv_pmos m=1 w=1.8u l=130.00n ng=2 nrd=0 nrs=0 +MP17 QP QN VDD VDD sg13_lv_pmos m=1 w=900.0n l=130.00n ng=1 nrd=0 nrs=0 +.ENDS +.SUBCKT RSC_IHPSG13_CBUFX2 A Z VDD VSS +MN1 Z net4 VSS VSS sg13_lv_nmos m=1 w=705.000n l=130.00n ng=1 nrd=0 ++ nrs=0 +MN0 net4 A VSS VSS sg13_lv_nmos m=1 w=540.00n l=130.00n ng=1 nrd=0 ++ nrs=0 +MP1 Z net4 VDD VDD sg13_lv_pmos m=1 w=1.62u l=130.00n ng=1 nrd=0 nrs=0 +MP0 net4 A VDD VDD sg13_lv_pmos m=1 w=1.1u l=130.00n ng=1 nrd=0 nrs=0 +.ENDS +.SUBCKT RSC_IHPSG13_INVX4 A Z VDD VSS +MN0 Z A VSS VSS sg13_lv_nmos m=1 w=1.96u l=130.00n ng=2 nrd=0 nrs=0 +MP0 Z A VDD VDD sg13_lv_pmos m=1 w=3.24u l=130.00n ng=2 nrd=0 nrs=0 +.ENDS +.SUBCKT RM_IHPSG13_512x8_c2_1P_COLCTRL2 A_ADDR_DEC<3> A_ADDR_DEC<2> A_ADDR_DEC<1> ++ A_ADDR_DEC<0> A_BIST_BM_I A_BIST_DW_I A_BIST_EN_I A_BLC<3> A_BLC<2> A_BLC<1> ++ A_BLC<0> A_BLT<3> A_BLT<2> A_BLT<1> A_BLT<0> A_BM_I A_DCLK_B_L A_DCLK_B_R ++ A_DCLK_L A_DCLK_R A_DR_O A_DW_I A_RCLK_B_L A_RCLK_B_R A_RCLK_L A_RCLK_R ++ A_TIEH_O A_WCLK_B_L A_WCLK_B_R A_WCLK_L A_WCLK_R VDD VSS +XA_DREG A_BIST_EN_I A_BIST_DW_I A_DCLK_B_L A_DW_I A_DI_R net22 VDD VSS ++ / RSC_IHPSG13_DFNQMX2IX1 +XA_BREG A_BIST_EN_I A_BIST_BM_I A_DCLK_B_L A_BM_I A_BM_R net23 VDD VSS ++ / RSC_IHPSG13_DFNQMX2IX1 +XA_CAPS<5> VDD VSS / RSC_IHPSG13_FILLCAP4 +XA_CAPS<4> VDD VSS / RSC_IHPSG13_FILLCAP4 +XA_CAPS<3> VDD VSS / RSC_IHPSG13_FILLCAP4 +XA_CAPS<2> VDD VSS / RSC_IHPSG13_FILLCAP4 +XA_CAPS<1> VDD VSS / RSC_IHPSG13_FILLCAP4 +XA_I80 A_WCLK_B_R A_RCLK_B_R net21 VDD VSS / RSC_IHPSG13_AND2X2 +XA_I75 A_DI_R A_DO_WRITE_P A_WR_ONE VDD VSS / RSC_IHPSG13_AND2X2 +XA_I76 A_DI_N A_DO_WRITE_P A_WR_ZERO VDD VSS / RSC_IHPSG13_AND2X2 +XA_I44 A_WCLK_B_R A_BM_N A_DO_WRITE_P VDD VSS / RSC_IHPSG13_NOR2X2 +XA_I81 net21 A_PRE_N VDD VSS / RSC_IHPSG13_CINVX4_WN +XA_BLTMUX<3> A_BLC<3> A_BLC_SEL A_BLT<3> A_BLT_SEL A_PRE_N A_ADDR_DEC<3> ++ A_WR_ONE A_WR_ZERO VDD VSS / RM_IHPSG13_512x8_c2_1P_BLDRV +XA_BLTMUX<2> A_BLC<2> A_BLC_SEL A_BLT<2> A_BLT_SEL A_PRE_N A_ADDR_DEC<2> ++ A_WR_ONE A_WR_ZERO VDD VSS / RM_IHPSG13_512x8_c2_1P_BLDRV +XA_BLTMUX<1> A_BLC<1> A_BLC_SEL A_BLT<1> A_BLT_SEL A_PRE_N A_ADDR_DEC<1> ++ A_WR_ONE A_WR_ZERO VDD VSS / RM_IHPSG13_512x8_c2_1P_BLDRV +XA_BLTMUX<0> A_BLC<0> A_BLC_SEL A_BLT<0> A_BLT_SEL A_PRE_N A_ADDR_DEC<0> ++ A_WR_ONE A_WR_ZERO VDD VSS / RM_IHPSG13_512x8_c2_1P_BLDRV +XA_BM_TIEH A_TIEH_O VDD VSS / RSC_IHPSG13_TIEH +XA_I89 A_DCLK_B_L A_DCLK_B_R / RSC_IHPSG13_MET3RES +XA_I88 A_DCLK_L A_DCLK_R / RSC_IHPSG13_MET3RES +XA_I87 A_WCLK_L A_WCLK_R / RSC_IHPSG13_MET3RES +XA_I91 A_RCLK_B_R A_RCLK_B_L / RSC_IHPSG13_MET3RES +XA_R2 A_RCLK_R A_RCLK_L / RSC_IHPSG13_MET3RES +XA_I90 A_WCLK_B_R A_WCLK_B_L / RSC_IHPSG13_MET3RES +XA_ISENSE A_SAE A_BLC_SEL A_BLT_SEL net19 net20 VDD VSS / ++ RSC_IHPSG13_DFPQD_MSAFFX2 +XA_I78 A_RCLK_B_R A_SAE VDD VSS / RSC_IHPSG13_CBUFX2 +XA_I83 A_BM_R A_BM_N VDD VSS / RSC_IHPSG13_INVX2 +XA_I49 A_DI_R A_DI_N VDD VSS / RSC_IHPSG13_INVX2 +XA_I51 net19 A_DR_O VDD VSS / RSC_IHPSG13_INVX4 +XA_I69 A_DCLK_L A_DCLK_B_L VDD VSS / RSC_IHPSG13_CINVX2 +XA_I50 A_WCLK_L A_WCLK_B_R VDD VSS / RSC_IHPSG13_CINVX2 +XA_EBUF A_RCLK_R A_RCLK_B_R VDD VSS / RSC_IHPSG13_CINVX2 +.ENDS +.SUBCKT RM_IHPSG13_512x8_c2_1P_COLDRV13_FILL4 VDD VSS +XI0<9> VDD VSS / RSC_IHPSG13_FILLCAP4 +XI0<8> VDD VSS / RSC_IHPSG13_FILLCAP4 +XI0<7> VDD VSS / RSC_IHPSG13_FILLCAP4 +XI0<6> VDD VSS / RSC_IHPSG13_FILLCAP4 +XI0<5> VDD VSS / RSC_IHPSG13_FILLCAP4 +XI0<4> VDD VSS / RSC_IHPSG13_FILLCAP4 +XI0<3> VDD VSS / RSC_IHPSG13_FILLCAP4 +XI0<2> VDD VSS / RSC_IHPSG13_FILLCAP4 +XI0<1> VDD VSS / RSC_IHPSG13_FILLCAP4 +.ENDS +.SUBCKT RM_IHPSG13_512x8_c2_1P_COLDRV13_FILL4C2 VDD VSS +XI0<2> VDD VSS / RSC_IHPSG13_FILLCAP4 +XI0<1> VDD VSS / RSC_IHPSG13_FILLCAP4 +.ENDS + + +.SUBCKT RM_IHPSG13_512x8_c2_1P_COLDEC4 ACLK_N ADDR<3> ADDR<2> ADDR<1> ADDR<0> ++ ADDR_COL<1> ADDR_COL<0> ADDR_DEC<7> ADDR_DEC<6> ADDR_DEC<5> ADDR_DEC<4> ++ ADDR_DEC<3> ADDR_DEC<2> ADDR_DEC<1> ADDR_DEC<0> BIST_ADDR<3> BIST_ADDR<2> ++ BIST_ADDR<1> BIST_ADDR<0> BIST_EN_I VDD VSS +XI15 ADDR_COL<1> VDD VSS / RSC_IHPSG13_TIEL +XI14 addr_int ADDR_COL<0> VDD VSS / RSC_IHPSG13_CBUFX2 +XDFF<3> BIST_EN_I BIST_ADDR<3> ACLK_N ADDR<3> addr_int net7<0> VDD VSS ++ / RSC_IHPSG13_DFNQMX2IX1 +XDFF<2> BIST_EN_I BIST_ADDR<2> ACLK_N ADDR<2> padr_int<2> net7<1> VDD ++ VSS / RSC_IHPSG13_DFNQMX2IX1 +XDFF<1> BIST_EN_I BIST_ADDR<1> ACLK_N ADDR<1> padr_int<1> net7<2> VDD ++ VSS / RSC_IHPSG13_DFNQMX2IX1 +XDFF<0> BIST_EN_I BIST_ADDR<0> ACLK_N ADDR<0> padr_int<0> net7<3> VDD ++ VSS / RSC_IHPSG13_DFNQMX2IX1 +XI1<7> PADR<0> PADR<1> PADR<2> addr_n<7> VDD VSS / RSC_IHPSG13_NAND3X2 +XI1<6> NADR<0> PADR<1> PADR<2> addr_n<6> VDD VSS / RSC_IHPSG13_NAND3X2 +XI1<5> PADR<0> NADR<1> PADR<2> addr_n<5> VDD VSS / RSC_IHPSG13_NAND3X2 +XI1<4> NADR<0> NADR<1> PADR<2> addr_n<4> VDD VSS / RSC_IHPSG13_NAND3X2 +XI1<3> PADR<0> PADR<1> NADR<2> addr_n<3> VDD VSS / RSC_IHPSG13_NAND3X2 +XI1<2> NADR<0> PADR<1> NADR<2> addr_n<2> VDD VSS / RSC_IHPSG13_NAND3X2 +XI1<1> PADR<0> NADR<1> NADR<2> addr_n<1> VDD VSS / RSC_IHPSG13_NAND3X2 +XI1<0> NADR<0> NADR<1> NADR<2> addr_n<0> VDD VSS / RSC_IHPSG13_NAND3X2 +XI13<2> NADR<2> PADR<2> VDD VSS / RSC_IHPSG13_INVX2 +XI13<1> NADR<1> PADR<1> VDD VSS / RSC_IHPSG13_INVX2 +XI13<0> NADR<0> PADR<0> VDD VSS / RSC_IHPSG13_INVX2 +XI3<2> padr_int<2> NADR<2> VDD VSS / RSC_IHPSG13_INVX2 +XI3<1> padr_int<1> NADR<1> VDD VSS / RSC_IHPSG13_INVX2 +XI3<0> padr_int<0> NADR<0> VDD VSS / RSC_IHPSG13_INVX2 +XI2<7> addr_n<7> ADDR_DEC<7> VDD VSS / RSC_IHPSG13_INVX2 +XI2<6> addr_n<6> ADDR_DEC<6> VDD VSS / RSC_IHPSG13_INVX2 +XI2<5> addr_n<5> ADDR_DEC<5> VDD VSS / RSC_IHPSG13_INVX2 +XI2<4> addr_n<4> ADDR_DEC<4> VDD VSS / RSC_IHPSG13_INVX2 +XI2<3> addr_n<3> ADDR_DEC<3> VDD VSS / RSC_IHPSG13_INVX2 +XI2<2> addr_n<2> ADDR_DEC<2> VDD VSS / RSC_IHPSG13_INVX2 +XI2<1> addr_n<1> ADDR_DEC<1> VDD VSS / RSC_IHPSG13_INVX2 +XI2<0> addr_n<0> ADDR_DEC<0> VDD VSS / RSC_IHPSG13_INVX2 +XI16<3> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI16<2> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI16<1> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI17<2> VDD VSS / RSC_IHPSG13_FILLCAP4 +XI17<1> VDD VSS / RSC_IHPSG13_FILLCAP4 +.ENDS +.SUBCKT RSC_IHPSG13_AND2X4 A B Z VDD VSS +MN3 Z net6 VSS VSS sg13_lv_nmos m=1 w=1.96u l=130.00n ng=2 nrd=0 nrs=0 +MN4 net9 B VSS VSS sg13_lv_nmos m=1 w=500.0n l=130.00n ng=1 nrd=0 nrs=0 +MN6 net6 A net9 VSS sg13_lv_nmos m=1 w=500.0n l=130.00n ng=1 nrd=0 nrs=0 +MP2 Z net6 VDD VDD sg13_lv_pmos m=1 w=3.24u l=130.00n ng=2 nrd=0 nrs=0 +MP0 net6 B VDD VDD sg13_lv_pmos m=1 w=860.00n l=130.00n ng=1 nrd=0 ++ nrs=0 +MP1 net6 A VDD VDD sg13_lv_pmos m=1 w=860.00n l=130.00n ng=1 nrd=0 ++ nrs=0 +.ENDS +.SUBCKT RM_IHPSG13_512x8_c2_1P_COLCTRL4 A_ADDR_COL A_ADDR_DEC<7> A_ADDR_DEC<6> ++ A_ADDR_DEC<5> A_ADDR_DEC<4> A_ADDR_DEC<3> A_ADDR_DEC<2> A_ADDR_DEC<1> ++ A_ADDR_DEC<0> A_BIST_BM_I A_BIST_DW_I A_BIST_EN_I A_BLC<15> A_BLC<14> ++ A_BLC<13> A_BLC<12> A_BLC<11> A_BLC<10> A_BLC<9> A_BLC<8> A_BLC<7> A_BLC<6> ++ A_BLC<5> A_BLC<4> A_BLC<3> A_BLC<2> A_BLC<1> A_BLC<0> A_BLT<15> A_BLT<14> ++ A_BLT<13> A_BLT<12> A_BLT<11> A_BLT<10> A_BLT<9> A_BLT<8> A_BLT<7> A_BLT<6> ++ A_BLT<5> A_BLT<4> A_BLT<3> A_BLT<2> A_BLT<1> A_BLT<0> A_BM_I A_DCLK_B_L ++ A_DCLK_B_R A_DCLK_L A_DCLK_R A_DR_O A_DW_I A_RCLK_B_L A_RCLK_B_R A_RCLK_L ++ A_RCLK_R A_TIEH_O A_WCLK_B_L A_WCLK_B_R A_WCLK_L A_WCLK_R VDD VSS +XA_I80 A_WCLK_B_L A_RCLK_B_L net21 VDD VSS / RSC_IHPSG13_AND2X2 +XA_I76 A_DO_WRITE_P A_DI_N A_WR_ZERO VDD VSS / RSC_IHPSG13_AND2X4 +XA_I75 A_DI_R A_DO_WRITE_P A_WR_ONE VDD VSS / RSC_IHPSG13_AND2X4 +XA_CAPS<8> VDD VSS / RSC_IHPSG13_FILLCAP4 +XA_CAPS<7> VDD VSS / RSC_IHPSG13_FILLCAP4 +XA_CAPS<6> VDD VSS / RSC_IHPSG13_FILLCAP4 +XA_CAPS<5> VDD VSS / RSC_IHPSG13_FILLCAP4 +XA_CAPS<4> VDD VSS / RSC_IHPSG13_FILLCAP4 +XA_CAPS<3> VDD VSS / RSC_IHPSG13_FILLCAP4 +XA_CAPS<2> VDD VSS / RSC_IHPSG13_FILLCAP4 +XA_CAPS<1> VDD VSS / RSC_IHPSG13_FILLCAP4 +XA_I69 A_DCLK_L A_DCLK_B_L VDD VSS / RSC_IHPSG13_CINVX4 +XA_I50 A_WCLK_L A_WCLK_B_L VDD VSS / RSC_IHPSG13_CINVX4 +XA_EBUF A_RCLK_L A_RCLK_B_L VDD VSS / RSC_IHPSG13_CINVX4 +XA_INV<1> A_N0 A_P0 VDD VSS / RSC_IHPSG13_CINVX4 +XA_INV<0> A_ADDR_COL A_N0 VDD VSS / RSC_IHPSG13_CINVX4 +XA_I81<1> net21 A_PRE_N VDD VSS / RSC_IHPSG13_CINVX4_WN +XA_I81<0> net21 A_PRE_N VDD VSS / RSC_IHPSG13_CINVX4_WN +XA_BLTMUX<15> A_BLC<15> A_BLC_SEL A_BLT<15> A_BLT_SEL A_PRE_N A_SEL_P<15> ++ A_WR_ONE A_WR_ZERO VDD VSS / RM_IHPSG13_512x8_c2_1P_BLDRV +XA_BLTMUX<14> A_BLC<14> A_BLC_SEL A_BLT<14> A_BLT_SEL A_PRE_N A_SEL_P<14> ++ A_WR_ONE A_WR_ZERO VDD VSS / RM_IHPSG13_512x8_c2_1P_BLDRV +XA_BLTMUX<13> A_BLC<13> A_BLC_SEL A_BLT<13> A_BLT_SEL A_PRE_N A_SEL_P<13> ++ A_WR_ONE A_WR_ZERO VDD VSS / RM_IHPSG13_512x8_c2_1P_BLDRV +XA_BLTMUX<12> A_BLC<12> A_BLC_SEL A_BLT<12> A_BLT_SEL A_PRE_N A_SEL_P<12> ++ A_WR_ONE A_WR_ZERO VDD VSS / RM_IHPSG13_512x8_c2_1P_BLDRV +XA_BLTMUX<11> A_BLC<11> A_BLC_SEL A_BLT<11> A_BLT_SEL A_PRE_N A_SEL_P<11> ++ A_WR_ONE A_WR_ZERO VDD VSS / RM_IHPSG13_512x8_c2_1P_BLDRV +XA_BLTMUX<10> A_BLC<10> A_BLC_SEL A_BLT<10> A_BLT_SEL A_PRE_N A_SEL_P<10> ++ A_WR_ONE A_WR_ZERO VDD VSS / RM_IHPSG13_512x8_c2_1P_BLDRV +XA_BLTMUX<9> A_BLC<9> A_BLC_SEL A_BLT<9> A_BLT_SEL A_PRE_N A_SEL_P<9> A_WR_ONE ++ A_WR_ZERO VDD VSS / RM_IHPSG13_512x8_c2_1P_BLDRV +XA_BLTMUX<8> A_BLC<8> A_BLC_SEL A_BLT<8> A_BLT_SEL A_PRE_N A_SEL_P<8> A_WR_ONE ++ A_WR_ZERO VDD VSS / RM_IHPSG13_512x8_c2_1P_BLDRV +XA_BLTMUX<7> A_BLC<7> A_BLC_SEL A_BLT<7> A_BLT_SEL A_PRE_N A_SEL_P<7> A_WR_ONE ++ A_WR_ZERO VDD VSS / RM_IHPSG13_512x8_c2_1P_BLDRV +XA_BLTMUX<6> A_BLC<6> A_BLC_SEL A_BLT<6> A_BLT_SEL A_PRE_N A_SEL_P<6> A_WR_ONE ++ A_WR_ZERO VDD VSS / RM_IHPSG13_512x8_c2_1P_BLDRV +XA_BLTMUX<5> A_BLC<5> A_BLC_SEL A_BLT<5> A_BLT_SEL A_PRE_N A_SEL_P<5> A_WR_ONE ++ A_WR_ZERO VDD VSS / RM_IHPSG13_512x8_c2_1P_BLDRV +XA_BLTMUX<4> A_BLC<4> A_BLC_SEL A_BLT<4> A_BLT_SEL A_PRE_N A_SEL_P<4> A_WR_ONE ++ A_WR_ZERO VDD VSS / RM_IHPSG13_512x8_c2_1P_BLDRV +XA_BLTMUX<3> A_BLC<3> A_BLC_SEL A_BLT<3> A_BLT_SEL A_PRE_N A_SEL_P<3> A_WR_ONE ++ A_WR_ZERO VDD VSS / RM_IHPSG13_512x8_c2_1P_BLDRV +XA_BLTMUX<2> A_BLC<2> A_BLC_SEL A_BLT<2> A_BLT_SEL A_PRE_N A_SEL_P<2> A_WR_ONE ++ A_WR_ZERO VDD VSS / RM_IHPSG13_512x8_c2_1P_BLDRV +XA_BLTMUX<1> A_BLC<1> A_BLC_SEL A_BLT<1> A_BLT_SEL A_PRE_N A_SEL_P<1> A_WR_ONE ++ A_WR_ZERO VDD VSS / RM_IHPSG13_512x8_c2_1P_BLDRV +XA_BLTMUX<0> A_BLC<0> A_BLC_SEL A_BLT<0> A_BLT_SEL A_PRE_N A_SEL_P<0> A_WR_ONE ++ A_WR_ZERO VDD VSS / RM_IHPSG13_512x8_c2_1P_BLDRV +XA_R2 A_RCLK_L A_RCLK_R / RSC_IHPSG13_MET3RES +XA_I87 A_WCLK_L A_WCLK_R / RSC_IHPSG13_MET3RES +XA_I88 A_DCLK_L A_DCLK_R / RSC_IHPSG13_MET3RES +XA_I89 A_DCLK_B_L A_DCLK_B_R / RSC_IHPSG13_MET3RES +XA_I90 A_WCLK_B_L A_WCLK_B_R / RSC_IHPSG13_MET3RES +XA_I91 A_RCLK_B_L A_RCLK_B_R / RSC_IHPSG13_MET3RES +XA_ISENSE A_SAE A_BLC_SEL A_BLT_SEL net19 net20 VDD VSS / ++ RSC_IHPSG13_DFPQD_MSAFFX2 +XA_I51 net19 A_DR_O VDD VSS / RSC_IHPSG13_INVX4 +XA_I78 A_RCLK_B_L A_SAE VDD VSS / RSC_IHPSG13_CBUFX2 +XA_DREG A_BIST_EN_I A_BIST_DW_I A_DCLK_B_L A_DW_I A_DI_R net22 VDD VSS ++ / RSC_IHPSG13_DFNQMX2IX1 +XA_BREG A_BIST_EN_I A_BIST_BM_I A_DCLK_B_L A_BM_I A_BM_R net24 VDD VSS ++ / RSC_IHPSG13_DFNQMX2IX1 +XA_DEC3INV<15> net23<0> A_SEL_P<15> VDD VSS / RSC_IHPSG13_INVX2 +XA_DEC3INV<14> net23<1> A_SEL_P<14> VDD VSS / RSC_IHPSG13_INVX2 +XA_DEC3INV<13> net23<2> A_SEL_P<13> VDD VSS / RSC_IHPSG13_INVX2 +XA_DEC3INV<12> net23<3> A_SEL_P<12> VDD VSS / RSC_IHPSG13_INVX2 +XA_DEC3INV<11> net23<4> A_SEL_P<11> VDD VSS / RSC_IHPSG13_INVX2 +XA_DEC3INV<10> net23<5> A_SEL_P<10> VDD VSS / RSC_IHPSG13_INVX2 +XA_DEC3INV<9> net23<6> A_SEL_P<9> VDD VSS / RSC_IHPSG13_INVX2 +XA_DEC3INV<8> net23<7> A_SEL_P<8> VDD VSS / RSC_IHPSG13_INVX2 +XA_DEC3INV<7> net23<8> A_SEL_P<7> VDD VSS / RSC_IHPSG13_INVX2 +XA_DEC3INV<6> net23<9> A_SEL_P<6> VDD VSS / RSC_IHPSG13_INVX2 +XA_DEC3INV<5> net23<10> A_SEL_P<5> VDD VSS / RSC_IHPSG13_INVX2 +XA_DEC3INV<4> net23<11> A_SEL_P<4> VDD VSS / RSC_IHPSG13_INVX2 +XA_DEC3INV<3> net23<12> A_SEL_P<3> VDD VSS / RSC_IHPSG13_INVX2 +XA_DEC3INV<2> net23<13> A_SEL_P<2> VDD VSS / RSC_IHPSG13_INVX2 +XA_DEC3INV<1> net23<14> A_SEL_P<1> VDD VSS / RSC_IHPSG13_INVX2 +XA_DEC3INV<0> net23<15> A_SEL_P<0> VDD VSS / RSC_IHPSG13_INVX2 +XA_I83 A_BM_R A_BM_N VDD VSS / RSC_IHPSG13_INVX2 +XA_I49 A_DI_R A_DI_N VDD VSS / RSC_IHPSG13_INVX2 +XA_I70<4> VDD VSS / RSC_IHPSG13_FILLCAP8 +XA_I70<3> VDD VSS / RSC_IHPSG13_FILLCAP8 +XA_I70<2> VDD VSS / RSC_IHPSG13_FILLCAP8 +XA_I70<1> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI73<14> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI73<13> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI73<12> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI73<11> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI73<10> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI73<9> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI73<8> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI73<7> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI73<6> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI73<5> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI73<4> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI73<3> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI73<2> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI73<1> VDD VSS / RSC_IHPSG13_FILLCAP8 +XA_I44 A_BM_N A_WCLK_B_L A_DO_WRITE_P VDD VSS / RSC_IHPSG13_NOR2X2 +XA_DEC3<15> A_P0 A_ADDR_DEC<7> net23<0> VDD VSS / RSC_IHPSG13_NAND2X2 +XA_DEC3<14> A_P0 A_ADDR_DEC<6> net23<1> VDD VSS / RSC_IHPSG13_NAND2X2 +XA_DEC3<13> A_P0 A_ADDR_DEC<5> net23<2> VDD VSS / RSC_IHPSG13_NAND2X2 +XA_DEC3<12> A_P0 A_ADDR_DEC<4> net23<3> VDD VSS / RSC_IHPSG13_NAND2X2 +XA_DEC3<11> A_P0 A_ADDR_DEC<3> net23<4> VDD VSS / RSC_IHPSG13_NAND2X2 +XA_DEC3<10> A_P0 A_ADDR_DEC<2> net23<5> VDD VSS / RSC_IHPSG13_NAND2X2 +XA_DEC3<9> A_P0 A_ADDR_DEC<1> net23<6> VDD VSS / RSC_IHPSG13_NAND2X2 +XA_DEC3<8> A_P0 A_ADDR_DEC<0> net23<7> VDD VSS / RSC_IHPSG13_NAND2X2 +XA_DEC3<7> A_N0 A_ADDR_DEC<7> net23<8> VDD VSS / RSC_IHPSG13_NAND2X2 +XA_DEC3<6> A_N0 A_ADDR_DEC<6> net23<9> VDD VSS / RSC_IHPSG13_NAND2X2 +XA_DEC3<5> A_N0 A_ADDR_DEC<5> net23<10> VDD VSS / RSC_IHPSG13_NAND2X2 +XA_DEC3<4> A_N0 A_ADDR_DEC<4> net23<11> VDD VSS / RSC_IHPSG13_NAND2X2 +XA_DEC3<3> A_N0 A_ADDR_DEC<3> net23<12> VDD VSS / RSC_IHPSG13_NAND2X2 +XA_DEC3<2> A_N0 A_ADDR_DEC<2> net23<13> VDD VSS / RSC_IHPSG13_NAND2X2 +XA_DEC3<1> A_N0 A_ADDR_DEC<1> net23<14> VDD VSS / RSC_IHPSG13_NAND2X2 +XA_DEC3<0> A_N0 A_ADDR_DEC<0> net23<15> VDD VSS / RSC_IHPSG13_NAND2X2 +XA_BM_TIEH A_TIEH_O VDD VSS / RSC_IHPSG13_TIEH +.ENDS + + +.SUBCKT RM_IHPSG13_512x8_c2_1P_COLDEC3 ACLK_N ADDR<2> ADDR<1> ADDR<0> ADDR_COL<1> ++ ADDR_COL<0> ADDR_DEC<7> ADDR_DEC<6> ADDR_DEC<5> ADDR_DEC<4> ADDR_DEC<3> ++ ADDR_DEC<2> ADDR_DEC<1> ADDR_DEC<0> BIST_ADDR<2> BIST_ADDR<1> BIST_ADDR<0> ++ BIST_EN_I VDD VSS +XI15<1> ADDR_COL<1> VDD VSS / RSC_IHPSG13_TIEL +XI15<0> ADDR_COL<0> VDD VSS / RSC_IHPSG13_TIEL +XI1<7> PADR<0> PADR<1> PADR<2> addr_n<7> VDD VSS / RSC_IHPSG13_NAND3X2 +XI1<6> NADR<0> PADR<1> PADR<2> addr_n<6> VDD VSS / RSC_IHPSG13_NAND3X2 +XI1<5> PADR<0> NADR<1> PADR<2> addr_n<5> VDD VSS / RSC_IHPSG13_NAND3X2 +XI1<4> NADR<0> NADR<1> PADR<2> addr_n<4> VDD VSS / RSC_IHPSG13_NAND3X2 +XI1<3> PADR<0> PADR<1> NADR<2> addr_n<3> VDD VSS / RSC_IHPSG13_NAND3X2 +XI1<2> NADR<0> PADR<1> NADR<2> addr_n<2> VDD VSS / RSC_IHPSG13_NAND3X2 +XI1<1> PADR<0> NADR<1> NADR<2> addr_n<1> VDD VSS / RSC_IHPSG13_NAND3X2 +XI1<0> NADR<0> NADR<1> NADR<2> addr_n<0> VDD VSS / RSC_IHPSG13_NAND3X2 +XDFF<2> BIST_EN_I BIST_ADDR<2> ACLK_N ADDR<2> padr_int<2> net6<0> VDD ++ VSS / RSC_IHPSG13_DFNQMX2IX1 +XDFF<1> BIST_EN_I BIST_ADDR<1> ACLK_N ADDR<1> padr_int<1> net6<1> VDD ++ VSS / RSC_IHPSG13_DFNQMX2IX1 +XDFF<0> BIST_EN_I BIST_ADDR<0> ACLK_N ADDR<0> padr_int<0> net6<2> VDD ++ VSS / RSC_IHPSG13_DFNQMX2IX1 +XI17<2> VDD VSS / RSC_IHPSG13_FILLCAP4 +XI17<1> VDD VSS / RSC_IHPSG13_FILLCAP4 +XI13<2> NADR<2> PADR<2> VDD VSS / RSC_IHPSG13_INVX2 +XI13<1> NADR<1> PADR<1> VDD VSS / RSC_IHPSG13_INVX2 +XI13<0> NADR<0> PADR<0> VDD VSS / RSC_IHPSG13_INVX2 +XI3<2> padr_int<2> NADR<2> VDD VSS / RSC_IHPSG13_INVX2 +XI3<1> padr_int<1> NADR<1> VDD VSS / RSC_IHPSG13_INVX2 +XI3<0> padr_int<0> NADR<0> VDD VSS / RSC_IHPSG13_INVX2 +XI2<7> addr_n<7> ADDR_DEC<7> VDD VSS / RSC_IHPSG13_INVX2 +XI2<6> addr_n<6> ADDR_DEC<6> VDD VSS / RSC_IHPSG13_INVX2 +XI2<5> addr_n<5> ADDR_DEC<5> VDD VSS / RSC_IHPSG13_INVX2 +XI2<4> addr_n<4> ADDR_DEC<4> VDD VSS / RSC_IHPSG13_INVX2 +XI2<3> addr_n<3> ADDR_DEC<3> VDD VSS / RSC_IHPSG13_INVX2 +XI2<2> addr_n<2> ADDR_DEC<2> VDD VSS / RSC_IHPSG13_INVX2 +XI2<1> addr_n<1> ADDR_DEC<1> VDD VSS / RSC_IHPSG13_INVX2 +XI2<0> addr_n<0> ADDR_DEC<0> VDD VSS / RSC_IHPSG13_INVX2 +XI16<6> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI16<5> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI16<4> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI16<3> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI16<2> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI16<1> VDD VSS / RSC_IHPSG13_FILLCAP8 +.ENDS +.SUBCKT RM_IHPSG13_512x8_c2_1P_COLCTRL3 A_ADDR_DEC<7> A_ADDR_DEC<6> A_ADDR_DEC<5> ++ A_ADDR_DEC<4> A_ADDR_DEC<3> A_ADDR_DEC<2> A_ADDR_DEC<1> A_ADDR_DEC<0> ++ A_BIST_BM_I A_BIST_DW_I A_BIST_EN_I A_BLC<7> A_BLC<6> A_BLC<5> A_BLC<4> ++ A_BLC<3> A_BLC<2> A_BLC<1> A_BLC<0> A_BLT<7> A_BLT<6> A_BLT<5> A_BLT<4> ++ A_BLT<3> A_BLT<2> A_BLT<1> A_BLT<0> A_BM_I A_DCLK_B_L A_DCLK_B_R A_DCLK_L ++ A_DCLK_R A_DR_O A_DW_I A_RCLK_B_L A_RCLK_B_R A_RCLK_L A_RCLK_R A_TIEH_O ++ A_WCLK_B_L A_WCLK_B_R A_WCLK_L A_WCLK_R VDD VSS +XA_DREG A_BIST_EN_I A_BIST_DW_I A_DCLK_B_L A_DW_I A_DI_R net22 VDD VSS ++ / RSC_IHPSG13_DFNQMX2IX1 +XA_BREG A_BIST_EN_I A_BIST_BM_I A_DCLK_B_R A_BM_I A_BM_R net23 VDD VSS ++ / RSC_IHPSG13_DFNQMX2IX1 +XA_I70<8> VDD VSS / RSC_IHPSG13_FILLCAP8 +XA_I70<7> VDD VSS / RSC_IHPSG13_FILLCAP8 +XA_I70<6> VDD VSS / RSC_IHPSG13_FILLCAP8 +XA_I70<5> VDD VSS / RSC_IHPSG13_FILLCAP8 +XA_I70<4> VDD VSS / RSC_IHPSG13_FILLCAP8 +XA_I70<3> VDD VSS / RSC_IHPSG13_FILLCAP8 +XA_I70<2> VDD VSS / RSC_IHPSG13_FILLCAP8 +XA_I70<1> VDD VSS / RSC_IHPSG13_FILLCAP8 +XA_I51 net19 A_DR_O VDD VSS / RSC_IHPSG13_INVX4 +XA_I44 A_BM_N A_WCLK_B_R A_DO_WRITE_P VDD VSS / RSC_IHPSG13_NOR2X2 +XA_BM_TIEH A_TIEH_O VDD VSS / RSC_IHPSG13_TIEH +XA_BLTMUX<7> A_BLC<7> A_BLC_SEL A_BLT<7> A_BLT_SEL A_PRE_N A_ADDR_DEC<7> ++ A_WR_ONE A_WR_ZERO VDD VSS / RM_IHPSG13_512x8_c2_1P_BLDRV +XA_BLTMUX<6> A_BLC<6> A_BLC_SEL A_BLT<6> A_BLT_SEL A_PRE_N A_ADDR_DEC<6> ++ A_WR_ONE A_WR_ZERO VDD VSS / RM_IHPSG13_512x8_c2_1P_BLDRV +XA_BLTMUX<5> A_BLC<5> A_BLC_SEL A_BLT<5> A_BLT_SEL A_PRE_N A_ADDR_DEC<5> ++ A_WR_ONE A_WR_ZERO VDD VSS / RM_IHPSG13_512x8_c2_1P_BLDRV +XA_BLTMUX<4> A_BLC<4> A_BLC_SEL A_BLT<4> A_BLT_SEL A_PRE_N A_ADDR_DEC<4> ++ A_WR_ONE A_WR_ZERO VDD VSS / RM_IHPSG13_512x8_c2_1P_BLDRV +XA_BLTMUX<3> A_BLC<3> A_BLC_SEL A_BLT<3> A_BLT_SEL A_PRE_N A_ADDR_DEC<3> ++ A_WR_ONE A_WR_ZERO VDD VSS / RM_IHPSG13_512x8_c2_1P_BLDRV +XA_BLTMUX<2> A_BLC<2> A_BLC_SEL A_BLT<2> A_BLT_SEL A_PRE_N A_ADDR_DEC<2> ++ A_WR_ONE A_WR_ZERO VDD VSS / RM_IHPSG13_512x8_c2_1P_BLDRV +XA_BLTMUX<1> A_BLC<1> A_BLC_SEL A_BLT<1> A_BLT_SEL A_PRE_N A_ADDR_DEC<1> ++ A_WR_ONE A_WR_ZERO VDD VSS / RM_IHPSG13_512x8_c2_1P_BLDRV +XA_BLTMUX<0> A_BLC<0> A_BLC_SEL A_BLT<0> A_BLT_SEL A_PRE_N A_ADDR_DEC<0> ++ A_WR_ONE A_WR_ZERO VDD VSS / RM_IHPSG13_512x8_c2_1P_BLDRV +XA_I49 A_DI_R A_DI_N VDD VSS / RSC_IHPSG13_INVX2 +XA_I83 A_BM_R A_BM_N VDD VSS / RSC_IHPSG13_INVX2 +XA_I69 A_DCLK_L A_DCLK_B_L VDD VSS / RSC_IHPSG13_CINVX2 +XA_I50 A_WCLK_L A_WCLK_B_L VDD VSS / RSC_IHPSG13_CINVX2 +XA_EBUF A_RCLK_L A_RCLK_B_L VDD VSS / RSC_IHPSG13_CINVX2 +XA_I78 A_RCLK_B_L A_SAE VDD VSS / RSC_IHPSG13_CBUFX2 +XA_I88 A_DCLK_L A_DCLK_R / RSC_IHPSG13_MET3RES +XA_I87 A_WCLK_L A_WCLK_R / RSC_IHPSG13_MET3RES +XA_R2 A_RCLK_L A_RCLK_R / RSC_IHPSG13_MET3RES +XA_I91 A_RCLK_B_L A_RCLK_B_R / RSC_IHPSG13_MET3RES +XA_I90 A_WCLK_B_L A_WCLK_B_R / RSC_IHPSG13_MET3RES +XA_I89 A_DCLK_B_L A_DCLK_B_R / RSC_IHPSG13_MET3RES +XA_I80 A_WCLK_B_R A_RCLK_B_R net21 VDD VSS / RSC_IHPSG13_AND2X2 +XA_I76 A_DI_N A_DO_WRITE_P A_WR_ZERO VDD VSS / RSC_IHPSG13_AND2X2 +XA_I75 A_DI_R A_DO_WRITE_P A_WR_ONE VDD VSS / RSC_IHPSG13_AND2X2 +XA_ISENSE A_SAE A_BLC_SEL A_BLT_SEL net19 net20 VDD VSS / ++ RSC_IHPSG13_DFPQD_MSAFFX2 +XA_I81 net21 A_PRE_N VDD VSS / RSC_IHPSG13_CINVX4_WN +XA_CAPS<5> VDD VSS / RSC_IHPSG13_FILLCAP4 +XA_CAPS<4> VDD VSS / RSC_IHPSG13_FILLCAP4 +XA_CAPS<3> VDD VSS / RSC_IHPSG13_FILLCAP4 +XA_CAPS<2> VDD VSS / RSC_IHPSG13_FILLCAP4 +XA_CAPS<1> VDD VSS / RSC_IHPSG13_FILLCAP4 +.ENDS + +.SUBCKT RM_IHPSG13_512x8_c2_2P_BITKIT_16x2_CORNER VDD_CORE VSS +XI16 VDD_CORE VSS VDD_CORE VSS / ++ RM_IHPSG13_512x8_c2_1P_BITKIT_CORNER +.ENDS +.SUBCKT RM_IHPSG13_512x8_c2_2P_BITKIT_EDGE_LR A_WL B_WL NW PW VDD VSS +MN1 VSS A_WL VSS VSS sg13_lv_nmos m=1 w=300.0n l=130.00n ng=1 nrd=0 nrs=0 +MN0 VSS B_WL VSS VSS sg13_lv_nmos m=1 w=300.0n l=130.00n ng=1 nrd=0 nrs=0 +.ENDS +.SUBCKT RM_IHPSG13_512x8_c2_2P_BITKIT_16x2_EDGE_LR A_WL<15> A_WL<14> A_WL<13> A_WL<12> ++ A_WL<11> A_WL<10> A_WL<9> A_WL<8> A_WL<7> A_WL<6> A_WL<5> A_WL<4> A_WL<3> ++ A_WL<2> A_WL<1> A_WL<0> B_WL<15> B_WL<14> B_WL<13> B_WL<12> B_WL<11> ++ B_WL<10> B_WL<9> B_WL<8> B_WL<7> B_WL<6> B_WL<5> B_WL<4> B_WL<3> B_WL<2> ++ B_WL<1> B_WL<0> VDD_CORE VSS +XI0<15> A_WL<15> B_WL<15> VDD_CORE VSS VDD_CORE VSS ++ / RM_IHPSG13_512x8_c2_2P_BITKIT_EDGE_LR +XI0<14> A_WL<14> B_WL<14> VDD_CORE VSS VDD_CORE VSS ++ / RM_IHPSG13_512x8_c2_2P_BITKIT_EDGE_LR +XI0<13> A_WL<13> B_WL<13> VDD_CORE VSS VDD_CORE VSS ++ / RM_IHPSG13_512x8_c2_2P_BITKIT_EDGE_LR +XI0<12> A_WL<12> B_WL<12> VDD_CORE VSS VDD_CORE VSS ++ / RM_IHPSG13_512x8_c2_2P_BITKIT_EDGE_LR +XI0<11> A_WL<11> B_WL<11> VDD_CORE VSS VDD_CORE VSS ++ / RM_IHPSG13_512x8_c2_2P_BITKIT_EDGE_LR +XI0<10> A_WL<10> B_WL<10> VDD_CORE VSS VDD_CORE VSS ++ / RM_IHPSG13_512x8_c2_2P_BITKIT_EDGE_LR +XI0<9> A_WL<9> B_WL<9> VDD_CORE VSS VDD_CORE VSS / ++ RM_IHPSG13_512x8_c2_2P_BITKIT_EDGE_LR +XI0<8> A_WL<8> B_WL<8> VDD_CORE VSS VDD_CORE VSS / ++ RM_IHPSG13_512x8_c2_2P_BITKIT_EDGE_LR +XI0<7> A_WL<7> B_WL<7> VDD_CORE VSS VDD_CORE VSS / ++ RM_IHPSG13_512x8_c2_2P_BITKIT_EDGE_LR +XI0<6> A_WL<6> B_WL<6> VDD_CORE VSS VDD_CORE VSS / ++ RM_IHPSG13_512x8_c2_2P_BITKIT_EDGE_LR +XI0<5> A_WL<5> B_WL<5> VDD_CORE VSS VDD_CORE VSS / ++ RM_IHPSG13_512x8_c2_2P_BITKIT_EDGE_LR +XI0<4> A_WL<4> B_WL<4> VDD_CORE VSS VDD_CORE VSS / ++ RM_IHPSG13_512x8_c2_2P_BITKIT_EDGE_LR +XI0<3> A_WL<3> B_WL<3> VDD_CORE VSS VDD_CORE VSS / ++ RM_IHPSG13_512x8_c2_2P_BITKIT_EDGE_LR +XI0<2> A_WL<2> B_WL<2> VDD_CORE VSS VDD_CORE VSS / ++ RM_IHPSG13_512x8_c2_2P_BITKIT_EDGE_LR +XI0<1> A_WL<1> B_WL<1> VDD_CORE VSS VDD_CORE VSS / ++ RM_IHPSG13_512x8_c2_2P_BITKIT_EDGE_LR +XI0<0> A_WL<0> B_WL<0> VDD_CORE VSS VDD_CORE VSS / ++ RM_IHPSG13_512x8_c2_2P_BITKIT_EDGE_LR +.ENDS +.SUBCKT RM_IHPSG13_512x8_c2_2P_BITKIT_CELL A_BLC_BOT A_BLC_TOP A_BLT_BOT A_BLT_TOP ++ A_LWL A_RWL B_BLC_BOT B_BLC_TOP B_BLT_BOT B_BLT_TOP B_LWL B_RWL NW PW VDD VSS +MN5 NC B_RWL B_BLC_BOT PW sg13_lv_nmos m=1 w=300.0n l=130.00n ng=1 nrd=0 nrs=0 +MN4 B_BLT_BOT B_LWL NT PW sg13_lv_nmos m=1 w=300.0n l=130.00n ng=1 nrd=0 nrs=0 +MN0 NC NT VSS PW sg13_lv_nmos m=1 w=600.0n l=130.00n ng=2 nrd=0 nrs=0 +MN1 NT NC VSS PW sg13_lv_nmos m=1 w=600.0n l=130.00n ng=2 nrd=0 nrs=0 +MN3 NC A_RWL A_BLC_TOP PW sg13_lv_nmos m=1 w=300.0n l=130.00n ng=1 nrd=0 nrs=0 +MN2 A_BLT_TOP A_LWL NT PW sg13_lv_nmos m=1 w=300.0n l=130.00n ng=1 nrd=0 nrs=0 +MP1 NT NC VDD NW sg13_lv_pmos m=1 w=150.00n l=130.00n ng=1 nrd=0 nrs=0 +MP0 NC NT VDD NW sg13_lv_pmos m=1 w=150.00n l=130.00n ng=1 nrd=0 nrs=0 +R5 B_RWL B_LWL lvsres w=2.6e-07 l=6e-07 +R4 B_BLC_BOT B_BLC_TOP lvsres w=2.6e-07 l=6e-07 +R3 B_BLT_BOT B_BLT_TOP lvsres w=2.6e-07 l=6e-07 +R1 A_BLC_BOT A_BLC_TOP lvsres w=2.6e-07 l=6e-07 +R0 A_BLT_BOT A_BLT_TOP lvsres w=2.6e-07 l=6e-07 +R2 A_RWL A_LWL lvsres w=2.6e-07 l=6e-07 +.ENDS +.SUBCKT RM_IHPSG13_512x8_c2_2P_BITKIT_16x2_SRAM A_BLC_BOT<1> A_BLC_BOT<0> A_BLC_TOP<1> ++ A_BLC_TOP<0> A_BLT_BOT<1> A_BLT_BOT<0> A_BLT_TOP<1> A_BLT_TOP<0> A_LWL<15> ++ A_LWL<14> A_LWL<13> A_LWL<12> A_LWL<11> A_LWL<10> A_LWL<9> A_LWL<8> A_LWL<7> ++ A_LWL<6> A_LWL<5> A_LWL<4> A_LWL<3> A_LWL<2> A_LWL<1> A_LWL<0> A_RWL<15> ++ A_RWL<14> A_RWL<13> A_RWL<12> A_RWL<11> A_RWL<10> A_RWL<9> A_RWL<8> A_RWL<7> ++ A_RWL<6> A_RWL<5> A_RWL<4> A_RWL<3> A_RWL<2> A_RWL<1> A_RWL<0> B_BLC_BOT<1> ++ B_BLC_BOT<0> B_BLC_TOP<1> B_BLC_TOP<0> B_BLT_BOT<1> B_BLT_BOT<0> ++ B_BLT_TOP<1> B_BLT_TOP<0> B_LWL<15> B_LWL<14> B_LWL<13> B_LWL<12> B_LWL<11> ++ B_LWL<10> B_LWL<9> B_LWL<8> B_LWL<7> B_LWL<6> B_LWL<5> B_LWL<4> B_LWL<3> ++ B_LWL<2> B_LWL<1> B_LWL<0> B_RWL<15> B_RWL<14> B_RWL<13> B_RWL<12> B_RWL<11> ++ B_RWL<10> B_RWL<9> B_RWL<8> B_RWL<7> B_RWL<6> B_RWL<5> B_RWL<4> B_RWL<3> ++ B_RWL<2> B_RWL<1> B_RWL<0> VDD_CORE VSS +XCELL<31> A_BLC_TOP<1> A_RBLC<15> A_BLT_TOP<1> A_RBLT<15> A_XWL<15> A_RWL<15> ++ B_BLC_TOP<1> B_RBLC<15> B_BLT_TOP<1> B_RBLT<15> B_XWL<15> B_RWL<15> ++ VDD_CORE VSS VDD_CORE VSS / ++ RM_IHPSG13_512x8_c2_2P_BITKIT_CELL +XCELL<30> A_RBLC<14> A_RBLC<15> A_RBLT<14> A_RBLT<15> A_XWL<14> A_RWL<14> ++ B_RBLC<14> B_RBLC<15> B_RBLT<14> B_RBLT<15> B_XWL<14> B_RWL<14> VDD_CORE ++ VSS VDD_CORE VSS / RM_IHPSG13_512x8_c2_2P_BITKIT_CELL +XCELL<29> A_RBLC<14> A_RBLC<13> A_RBLT<14> A_RBLT<13> A_XWL<13> A_RWL<13> ++ B_RBLC<14> B_RBLC<13> B_RBLT<14> B_RBLT<13> B_XWL<13> B_RWL<13> VDD_CORE ++ VSS VDD_CORE VSS / RM_IHPSG13_512x8_c2_2P_BITKIT_CELL +XCELL<28> A_RBLC<12> A_RBLC<13> A_RBLT<12> A_RBLT<13> A_XWL<12> A_RWL<12> ++ B_RBLC<12> B_RBLC<13> B_RBLT<12> B_RBLT<13> B_XWL<12> B_RWL<12> VDD_CORE ++ VSS VDD_CORE VSS / RM_IHPSG13_512x8_c2_2P_BITKIT_CELL +XCELL<27> A_RBLC<12> A_RBLC<11> A_RBLT<12> A_RBLT<11> A_XWL<11> A_RWL<11> ++ B_RBLC<12> B_RBLC<11> B_RBLT<12> B_RBLT<11> B_XWL<11> B_RWL<11> VDD_CORE ++ VSS VDD_CORE VSS / RM_IHPSG13_512x8_c2_2P_BITKIT_CELL +XCELL<26> A_RBLC<10> A_RBLC<11> A_RBLT<10> A_RBLT<11> A_XWL<10> A_RWL<10> ++ B_RBLC<10> B_RBLC<11> B_RBLT<10> B_RBLT<11> B_XWL<10> B_RWL<10> VDD_CORE ++ VSS VDD_CORE VSS / RM_IHPSG13_512x8_c2_2P_BITKIT_CELL +XCELL<25> A_RBLC<10> A_RBLC<9> A_RBLT<10> A_RBLT<9> A_XWL<9> A_RWL<9> ++ B_RBLC<10> B_RBLC<9> B_RBLT<10> B_RBLT<9> B_XWL<9> B_RWL<9> VDD_CORE ++ VSS VDD_CORE VSS / RM_IHPSG13_512x8_c2_2P_BITKIT_CELL +XCELL<24> A_RBLC<8> A_RBLC<9> A_RBLT<8> A_RBLT<9> A_XWL<8> A_RWL<8> B_RBLC<8> ++ B_RBLC<9> B_RBLT<8> B_RBLT<9> B_XWL<8> B_RWL<8> VDD_CORE VSS ++ VDD_CORE VSS / RM_IHPSG13_512x8_c2_2P_BITKIT_CELL +XCELL<23> A_RBLC<8> A_RBLC<7> A_RBLT<8> A_RBLT<7> A_XWL<7> A_RWL<7> B_RBLC<8> ++ B_RBLC<7> B_RBLT<8> B_RBLT<7> B_XWL<7> B_RWL<7> VDD_CORE VSS ++ VDD_CORE VSS / RM_IHPSG13_512x8_c2_2P_BITKIT_CELL +XCELL<22> A_RBLC<6> A_RBLC<7> A_RBLT<6> A_RBLT<7> A_XWL<6> A_RWL<6> B_RBLC<6> ++ B_RBLC<7> B_RBLT<6> B_RBLT<7> B_XWL<6> B_RWL<6> VDD_CORE VSS ++ VDD_CORE VSS / RM_IHPSG13_512x8_c2_2P_BITKIT_CELL +XCELL<21> A_RBLC<6> A_RBLC<5> A_RBLT<6> A_RBLT<5> A_XWL<5> A_RWL<5> B_RBLC<6> ++ B_RBLC<5> B_RBLT<6> B_RBLT<5> B_XWL<5> B_RWL<5> VDD_CORE VSS ++ VDD_CORE VSS / RM_IHPSG13_512x8_c2_2P_BITKIT_CELL +XCELL<20> A_RBLC<4> A_RBLC<5> A_RBLT<4> A_RBLT<5> A_XWL<4> A_RWL<4> B_RBLC<4> ++ B_RBLC<5> B_RBLT<4> B_RBLT<5> B_XWL<4> B_RWL<4> VDD_CORE VSS ++ VDD_CORE VSS / RM_IHPSG13_512x8_c2_2P_BITKIT_CELL +XCELL<19> A_RBLC<4> A_RBLC<3> A_RBLT<4> A_RBLT<3> A_XWL<3> A_RWL<3> B_RBLC<4> ++ B_RBLC<3> B_RBLT<4> B_RBLT<3> B_XWL<3> B_RWL<3> VDD_CORE VSS ++ VDD_CORE VSS / RM_IHPSG13_512x8_c2_2P_BITKIT_CELL +XCELL<18> A_RBLC<2> A_RBLC<3> A_RBLT<2> A_RBLT<3> A_XWL<2> A_RWL<2> B_RBLC<2> ++ B_RBLC<3> B_RBLT<2> B_RBLT<3> B_XWL<2> B_RWL<2> VDD_CORE VSS ++ VDD_CORE VSS / RM_IHPSG13_512x8_c2_2P_BITKIT_CELL +XCELL<17> A_RBLC<2> A_RBLC<1> A_RBLT<2> A_RBLT<1> A_XWL<1> A_RWL<1> B_RBLC<2> ++ B_RBLC<1> B_RBLT<2> B_RBLT<1> B_XWL<1> B_RWL<1> VDD_CORE VSS ++ VDD_CORE VSS / RM_IHPSG13_512x8_c2_2P_BITKIT_CELL +XCELL<16> A_BLC_BOT<1> A_RBLC<1> A_BLT_BOT<1> A_RBLT<1> A_XWL<0> A_RWL<0> ++ B_BLC_BOT<1> B_RBLC<1> B_BLT_BOT<1> B_RBLT<1> B_XWL<0> B_RWL<0> VDD_CORE ++ VSS VDD_CORE VSS / RM_IHPSG13_512x8_c2_2P_BITKIT_CELL +XCELL<15> A_BLC_TOP<0> A_LBLC<15> A_BLT_TOP<0> A_LBLT<15> A_LWL<15> A_XWL<15> ++ B_BLC_TOP<0> B_LBLC<15> B_BLT_TOP<0> B_LBLT<15> B_LWL<15> B_XWL<15> ++ VDD_CORE VSS VDD_CORE VSS / ++ RM_IHPSG13_512x8_c2_2P_BITKIT_CELL +XCELL<14> A_LBLC<14> A_LBLC<15> A_LBLT<14> A_LBLT<15> A_LWL<14> A_XWL<14> ++ B_LBLC<14> B_LBLC<15> B_LBLT<14> B_LBLT<15> B_LWL<14> B_XWL<14> VDD_CORE ++ VSS VDD_CORE VSS / RM_IHPSG13_512x8_c2_2P_BITKIT_CELL +XCELL<13> A_LBLC<14> A_LBLC<13> A_LBLT<14> A_LBLT<13> A_LWL<13> A_XWL<13> ++ B_LBLC<14> B_LBLC<13> B_LBLT<14> B_LBLT<13> B_LWL<13> B_XWL<13> VDD_CORE ++ VSS VDD_CORE VSS / RM_IHPSG13_512x8_c2_2P_BITKIT_CELL +XCELL<12> A_LBLC<12> A_LBLC<13> A_LBLT<12> A_LBLT<13> A_LWL<12> A_XWL<12> ++ B_LBLC<12> B_LBLC<13> B_LBLT<12> B_LBLT<13> B_LWL<12> B_XWL<12> VDD_CORE ++ VSS VDD_CORE VSS / RM_IHPSG13_512x8_c2_2P_BITKIT_CELL +XCELL<11> A_LBLC<12> A_LBLC<11> A_LBLT<12> A_LBLT<11> A_LWL<11> A_XWL<11> ++ B_LBLC<12> B_LBLC<11> B_LBLT<12> B_LBLT<11> B_LWL<11> B_XWL<11> VDD_CORE ++ VSS VDD_CORE VSS / RM_IHPSG13_512x8_c2_2P_BITKIT_CELL +XCELL<10> A_LBLC<10> A_LBLC<11> A_LBLT<10> A_LBLT<11> A_LWL<10> A_XWL<10> ++ B_LBLC<10> B_LBLC<11> B_LBLT<10> B_LBLT<11> B_LWL<10> B_XWL<10> VDD_CORE ++ VSS VDD_CORE VSS / RM_IHPSG13_512x8_c2_2P_BITKIT_CELL +XCELL<9> A_LBLC<10> A_LBLC<9> A_LBLT<10> A_LBLT<9> A_LWL<9> A_XWL<9> ++ B_LBLC<10> B_LBLC<9> B_LBLT<10> B_LBLT<9> B_LWL<9> B_XWL<9> VDD_CORE ++ VSS VDD_CORE VSS / RM_IHPSG13_512x8_c2_2P_BITKIT_CELL +XCELL<8> A_LBLC<8> A_LBLC<9> A_LBLT<8> A_LBLT<9> A_LWL<8> A_XWL<8> B_LBLC<8> ++ B_LBLC<9> B_LBLT<8> B_LBLT<9> B_LWL<8> B_XWL<8> VDD_CORE VSS ++ VDD_CORE VSS / RM_IHPSG13_512x8_c2_2P_BITKIT_CELL +XCELL<7> A_LBLC<8> A_LBLC<7> A_LBLT<8> A_LBLT<7> A_LWL<7> A_XWL<7> B_LBLC<8> ++ B_LBLC<7> B_LBLT<8> B_LBLT<7> B_LWL<7> B_XWL<7> VDD_CORE VSS ++ VDD_CORE VSS / RM_IHPSG13_512x8_c2_2P_BITKIT_CELL +XCELL<6> A_LBLC<6> A_LBLC<7> A_LBLT<6> A_LBLT<7> A_LWL<6> A_XWL<6> B_LBLC<6> ++ B_LBLC<7> B_LBLT<6> B_LBLT<7> B_LWL<6> B_XWL<6> VDD_CORE VSS ++ VDD_CORE VSS / RM_IHPSG13_512x8_c2_2P_BITKIT_CELL +XCELL<5> A_LBLC<6> A_LBLC<5> A_LBLT<6> A_LBLT<5> A_LWL<5> A_XWL<5> B_LBLC<6> ++ B_LBLC<5> B_LBLT<6> B_LBLT<5> B_LWL<5> B_XWL<5> VDD_CORE VSS ++ VDD_CORE VSS / RM_IHPSG13_512x8_c2_2P_BITKIT_CELL +XCELL<4> A_LBLC<4> A_LBLC<5> A_LBLT<4> A_LBLT<5> A_LWL<4> A_XWL<4> B_LBLC<4> ++ B_LBLC<5> B_LBLT<4> B_LBLT<5> B_LWL<4> B_XWL<4> VDD_CORE VSS ++ VDD_CORE VSS / RM_IHPSG13_512x8_c2_2P_BITKIT_CELL +XCELL<3> A_LBLC<4> A_LBLC<3> A_LBLT<4> A_LBLT<3> A_LWL<3> A_XWL<3> B_LBLC<4> ++ B_LBLC<3> B_LBLT<4> B_LBLT<3> B_LWL<3> B_XWL<3> VDD_CORE VSS ++ VDD_CORE VSS / RM_IHPSG13_512x8_c2_2P_BITKIT_CELL +XCELL<2> A_LBLC<2> A_LBLC<3> A_LBLT<2> A_LBLT<3> A_LWL<2> A_XWL<2> B_LBLC<2> ++ B_LBLC<3> B_LBLT<2> B_LBLT<3> B_LWL<2> B_XWL<2> VDD_CORE VSS ++ VDD_CORE VSS / RM_IHPSG13_512x8_c2_2P_BITKIT_CELL +XCELL<1> A_LBLC<2> A_LBLC<1> A_LBLT<2> A_LBLT<1> A_LWL<1> A_XWL<1> B_LBLC<2> ++ B_LBLC<1> B_LBLT<2> B_LBLT<1> B_LWL<1> B_XWL<1> VDD_CORE VSS ++ VDD_CORE VSS / RM_IHPSG13_512x8_c2_2P_BITKIT_CELL +XCELL<0> A_BLC_BOT<0> A_LBLC<1> A_BLT_BOT<0> A_LBLT<1> A_LWL<0> A_XWL<0> ++ B_BLC_BOT<0> B_LBLC<1> B_BLT_BOT<0> B_LBLT<1> B_LWL<0> B_XWL<0> VDD_CORE ++ VSS VDD_CORE VSS / RM_IHPSG13_512x8_c2_2P_BITKIT_CELL +.ENDS +.SUBCKT RM_IHPSG13_512x8_c2_2P_BITKIT_EDGE_TB A_BLC A_BLT B_BLC B_BLT NW PW VDD VSS +.ENDS +.SUBCKT RM_IHPSG13_512x8_c2_2P_BITKIT_16x2_EDGE_TB A_BLC<1> A_BLC<0> A_BLT<1> A_BLT<0> ++ B_BLC<1> B_BLC<0> B_BLT<1> B_BLT<0> VDD_CORE VSS +XEDGE<1> A_BLC<1> A_BLT<1> B_BLC<1> B_BLT<1> VDD_CORE VSS ++ VDD_CORE VSS / RM_IHPSG13_512x8_c2_2P_BITKIT_EDGE_TB +XEDGE<0> A_BLC<0> A_BLT<0> B_BLC<0> B_BLT<0> VDD_CORE VSS ++ VDD_CORE VSS / RM_IHPSG13_512x8_c2_2P_BITKIT_EDGE_TB +.ENDS +.SUBCKT RM_IHPSG13_512x8_c2_2P_BITKIT_TAP A_BLC A_BLT B_BLC B_BLT NW PW VDD VSS +.ENDS +.SUBCKT RM_IHPSG13_512x8_c2_2P_BITKIT_16x2_TAP A_BLC<1> A_BLC<0> A_BLT<1> A_BLT<0> ++ B_BLC<1> B_BLC<0> B_BLT<1> B_BLT<0> VDD_CORE VSS +XIEDGEBP_COL1<1> A_BLC<1> A_BLT<1> B_BLC<1> B_BLT<1> VDD_CORE VSS ++ VDD_CORE VSS / RM_IHPSG13_512x8_c2_2P_BITKIT_EDGE_TB +XIEDGEBP_COL1<0> A_BLC<1> A_BLT<1> B_BLC<1> B_BLT<1> VDD_CORE VSS ++ VDD_CORE VSS / RM_IHPSG13_512x8_c2_2P_BITKIT_EDGE_TB +XIEDGEBP_COL2<1> A_BLC<0> A_BLT<0> B_BLC<0> B_BLT<0> VDD_CORE VSS ++ VDD_CORE VSS / RM_IHPSG13_512x8_c2_2P_BITKIT_EDGE_TB +XIEDGEBP_COL2<0> A_BLC<0> A_BLT<0> B_BLC<0> B_BLT<0> VDD_CORE VSS ++ VDD_CORE VSS / RM_IHPSG13_512x8_c2_2P_BITKIT_EDGE_TB +XITAP<1> A_BLC<1> A_BLT<1> B_BLC<1> B_BLT<1> VDD_CORE VSS ++ VDD_CORE VSS / RM_IHPSG13_512x8_c2_2P_BITKIT_TAP +XITAP<0> A_BLC<0> A_BLT<0> B_BLC<0> B_BLT<0> VDD_CORE VSS ++ VDD_CORE VSS / RM_IHPSG13_512x8_c2_2P_BITKIT_TAP +.ENDS + + +.SUBCKT RM_IHPSG13_512x8_c2_1P_BITKIT_TAP_LR NW PW VDD VSS +.ENDS +.SUBCKT RM_IHPSG13_512x8_c2_2P_BITKIT_16x2_TAP_LR VDD_CORE VSS +XCORNER<1> VDD_CORE VSS VDD_CORE VSS / ++ RM_IHPSG13_512x8_c2_1P_BITKIT_CORNER +XCORNER<0> VDD_CORE VSS VDD_CORE VSS / ++ RM_IHPSG13_512x8_c2_1P_BITKIT_CORNER +XTAP_BORDER VDD_CORE VSS VDD_CORE VSS / ++ RM_IHPSG13_512x8_c2_1P_BITKIT_TAP_LR +.ENDS + +.SUBCKT RSC_IHPSG13_CBUFX12 A Z VDD VSS +MN1 Z net6 VSS VSS sg13_lv_nmos m=1 w=4.23u l=130.00n ng=6 nrd=0 nrs=0 +MN0 net6 A VSS VSS sg13_lv_nmos m=1 w=1.41u l=130.00n ng=2 nrd=0 nrs=0 +MP1 Z net6 VDD VDD sg13_lv_pmos m=1 w=9.72u l=130.00n ng=6 nrd=0 nrs=0 +MP0 net6 A VDD VDD sg13_lv_pmos m=1 w=3.24u l=130.00n ng=2 nrd=0 nrs=0 +.ENDS +.SUBCKT RM_IHPSG13_512x8_c2_2P_COLDRV13X12 ADDR_COL_I<1> ADDR_COL_I<0> ADDR_COL_O<1> ++ ADDR_COL_O<0> ADDR_DEC_I<7> ADDR_DEC_I<6> ADDR_DEC_I<5> ADDR_DEC_I<4> ++ ADDR_DEC_I<3> ADDR_DEC_I<2> ADDR_DEC_I<1> ADDR_DEC_I<0> ADDR_DEC_O<7> ++ ADDR_DEC_O<6> ADDR_DEC_O<5> ADDR_DEC_O<4> ADDR_DEC_O<3> ADDR_DEC_O<2> ++ ADDR_DEC_O<1> ADDR_DEC_O<0> DCLK_I DCLK_O RCLK_I RCLK_O WCLK_I WCLK_O ++ VDD VSS +XI1<3> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI1<2> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI1<1> VDD VSS / RSC_IHPSG13_FILLCAP8 +XWCLK_DRV WCLK_I WCLK_O VDD VSS / RSC_IHPSG13_CBUFX12 +XRCLK_DRV RCLK_I RCLK_O VDD VSS / RSC_IHPSG13_CBUFX12 +XDCLK_DRV DCLK_I DCLK_O VDD VSS / RSC_IHPSG13_CBUFX12 +XADDR_COL_DRV<1> ADDR_COL_I<1> ADDR_COL_O<1> VDD VSS / ++ RSC_IHPSG13_CBUFX12 +XADDR_COL_DRV<0> ADDR_COL_I<0> ADDR_COL_O<0> VDD VSS / ++ RSC_IHPSG13_CBUFX12 +XADDR_DEC_DRV<7> ADDR_DEC_I<7> ADDR_DEC_O<7> VDD VSS / ++ RSC_IHPSG13_CBUFX12 +XADDR_DEC_DRV<6> ADDR_DEC_I<6> ADDR_DEC_O<6> VDD VSS / ++ RSC_IHPSG13_CBUFX12 +XADDR_DEC_DRV<5> ADDR_DEC_I<5> ADDR_DEC_O<5> VDD VSS / ++ RSC_IHPSG13_CBUFX12 +XADDR_DEC_DRV<4> ADDR_DEC_I<4> ADDR_DEC_O<4> VDD VSS / ++ RSC_IHPSG13_CBUFX12 +XADDR_DEC_DRV<3> ADDR_DEC_I<3> ADDR_DEC_O<3> VDD VSS / ++ RSC_IHPSG13_CBUFX12 +XADDR_DEC_DRV<2> ADDR_DEC_I<2> ADDR_DEC_O<2> VDD VSS / ++ RSC_IHPSG13_CBUFX12 +XADDR_DEC_DRV<1> ADDR_DEC_I<1> ADDR_DEC_O<1> VDD VSS / ++ RSC_IHPSG13_CBUFX12 +XADDR_DEC_DRV<0> ADDR_DEC_I<0> ADDR_DEC_O<0> VDD VSS / ++ RSC_IHPSG13_CBUFX12 +XI0<6> VDD VSS / RSC_IHPSG13_FILLCAP4 +XI0<5> VDD VSS / RSC_IHPSG13_FILLCAP4 +XI0<4> VDD VSS / RSC_IHPSG13_FILLCAP4 +XI0<3> VDD VSS / RSC_IHPSG13_FILLCAP4 +XI0<2> VDD VSS / RSC_IHPSG13_FILLCAP4 +XI0<1> VDD VSS / RSC_IHPSG13_FILLCAP4 +.ENDS +.SUBCKT RSC_IHPSG13_WLDRVX12 A Z VDD VSS +MN1 Z net6 VSS VSS sg13_lv_nmos m=1 w=1.41u l=130.00n ng=2 nrd=0 nrs=0 +MN0 net6 A VSS VSS sg13_lv_nmos m=1 w=1.8u l=130.00n ng=2 nrd=0 nrs=0 +MP1 Z net6 VDD VDD sg13_lv_pmos m=1 w=9.72u l=130.00n ng=6 nrd=0 nrs=0 +MP0 net6 A VDD VDD sg13_lv_pmos m=1 w=900.0n l=130.00n ng=1 nrd=0 nrs=0 +.ENDS +.SUBCKT RM_IHPSG13_512x8_c2_2P_WLDRV16X12 A<15> A<14> A<13> A<12> A<11> A<10> A<9> A<8> ++ A<7> A<6> A<5> A<4> A<3> A<2> A<1> A<0> Z<15> Z<14> Z<13> Z<12> Z<11> Z<10> ++ Z<9> Z<8> Z<7> Z<6> Z<5> Z<4> Z<3> Z<2> Z<1> Z<0> VDD VSS +XBUF<15> A<15> Z<15> VDD VSS / RSC_IHPSG13_WLDRVX12 +XBUF<14> A<14> Z<14> VDD VSS / RSC_IHPSG13_WLDRVX12 +XBUF<13> A<13> Z<13> VDD VSS / RSC_IHPSG13_WLDRVX12 +XBUF<12> A<12> Z<12> VDD VSS / RSC_IHPSG13_WLDRVX12 +XBUF<11> A<11> Z<11> VDD VSS / RSC_IHPSG13_WLDRVX12 +XBUF<10> A<10> Z<10> VDD VSS / RSC_IHPSG13_WLDRVX12 +XBUF<9> A<9> Z<9> VDD VSS / RSC_IHPSG13_WLDRVX12 +XBUF<8> A<8> Z<8> VDD VSS / RSC_IHPSG13_WLDRVX12 +XBUF<7> A<7> Z<7> VDD VSS / RSC_IHPSG13_WLDRVX12 +XBUF<6> A<6> Z<6> VDD VSS / RSC_IHPSG13_WLDRVX12 +XBUF<5> A<5> Z<5> VDD VSS / RSC_IHPSG13_WLDRVX12 +XBUF<4> A<4> Z<4> VDD VSS / RSC_IHPSG13_WLDRVX12 +XBUF<3> A<3> Z<3> VDD VSS / RSC_IHPSG13_WLDRVX12 +XBUF<2> A<2> Z<2> VDD VSS / RSC_IHPSG13_WLDRVX12 +XBUF<1> A<1> Z<1> VDD VSS / RSC_IHPSG13_WLDRVX12 +XBUF<0> A<0> Z<0> VDD VSS / RSC_IHPSG13_WLDRVX12 +.ENDS +.SUBCKT RM_IHPSG13_512x8_c2_2P_DEC04 ADDR<3> ADDR<2> ADDR<1> ADDR<0> CS ECLK_H_BOT ++ ECLK_H_TOP ECLK_L_BOT ECLK_L_TOP WL<15> WL<14> WL<13> WL<12> WL<11> WL<10> ++ WL<9> WL<8> WL<7> WL<6> WL<5> WL<4> WL<3> WL<2> WL<1> WL<0> VDD VSS +XI0<3> PADR<1> PADR<0> sel01<3> VDD VSS / RSC_IHPSG13_NAND2X2 +XI0<2> PADR<1> NADR<0> sel01<2> VDD VSS / RSC_IHPSG13_NAND2X2 +XI0<1> NADR<1> PADR<0> sel01<1> VDD VSS / RSC_IHPSG13_NAND2X2 +XI0<0> NADR<1> NADR<0> sel01<0> VDD VSS / RSC_IHPSG13_NAND2X2 +XI4 ECLK_L_BOT EN VDD VSS / RSC_IHPSG13_CINVX4 +XI5 ECLK_H_BOT ECLK_L_BOT VDD VSS / RSC_IHPSG13_CINVX2 +XI3<3> PADR<3> NADR<3> VDD VSS / RSC_IHPSG13_INVX2 +XI3<2> PADR<2> NADR<2> VDD VSS / RSC_IHPSG13_INVX2 +XI3<1> PADR<1> NADR<1> VDD VSS / RSC_IHPSG13_INVX2 +XI3<0> PADR<0> NADR<0> VDD VSS / RSC_IHPSG13_INVX2 +XR0 ECLK_H_BOT ECLK_H_TOP / RSC_IHPSG13_MET2RES +XI11 ECLK_L_BOT ECLK_L_TOP / RSC_IHPSG13_MET2RES +XI1<3> PADR<2> PADR<3> CS sel23<3> VDD VSS / RSC_IHPSG13_NAND3X2 +XI1<2> NADR<2> PADR<3> CS sel23<2> VDD VSS / RSC_IHPSG13_NAND3X2 +XI1<1> PADR<2> NADR<3> CS sel23<1> VDD VSS / RSC_IHPSG13_NAND3X2 +XI1<0> NADR<2> NADR<3> CS sel23<0> VDD VSS / RSC_IHPSG13_NAND3X2 +XI2<15> sel23<3> sel01<3> EN WL<15> VDD VSS / RSC_IHPSG13_NOR3X2 +XI2<14> sel23<3> sel01<2> EN WL<14> VDD VSS / RSC_IHPSG13_NOR3X2 +XI2<13> sel23<3> sel01<1> EN WL<13> VDD VSS / RSC_IHPSG13_NOR3X2 +XI2<12> sel23<3> sel01<0> EN WL<12> VDD VSS / RSC_IHPSG13_NOR3X2 +XI2<11> sel23<2> sel01<3> EN WL<11> VDD VSS / RSC_IHPSG13_NOR3X2 +XI2<10> sel23<2> sel01<2> EN WL<10> VDD VSS / RSC_IHPSG13_NOR3X2 +XI2<9> sel23<2> sel01<1> EN WL<9> VDD VSS / RSC_IHPSG13_NOR3X2 +XI2<8> sel23<2> sel01<0> EN WL<8> VDD VSS / RSC_IHPSG13_NOR3X2 +XI2<7> sel23<1> sel01<3> EN WL<7> VDD VSS / RSC_IHPSG13_NOR3X2 +XI2<6> sel23<1> sel01<2> EN WL<6> VDD VSS / RSC_IHPSG13_NOR3X2 +XI2<5> sel23<1> sel01<1> EN WL<5> VDD VSS / RSC_IHPSG13_NOR3X2 +XI2<4> sel23<1> sel01<0> EN WL<4> VDD VSS / RSC_IHPSG13_NOR3X2 +XI2<3> sel23<0> sel01<3> EN WL<3> VDD VSS / RSC_IHPSG13_NOR3X2 +XI2<2> sel23<0> sel01<2> EN WL<2> VDD VSS / RSC_IHPSG13_NOR3X2 +XI2<1> sel23<0> sel01<1> EN WL<1> VDD VSS / RSC_IHPSG13_NOR3X2 +XI2<0> sel23<0> sel01<0> EN WL<0> VDD VSS / RSC_IHPSG13_NOR3X2 +XCAPS4 VDD VSS / RSC_IHPSG13_FILLCAP4 +XLATCH<3> CS ADDR<3> PADR<3> VDD VSS / RSC_IHPSG13_LHPQX2 +XLATCH<2> CS ADDR<2> PADR<2> VDD VSS / RSC_IHPSG13_LHPQX2 +XLATCH<1> CS ADDR<1> PADR<1> VDD VSS / RSC_IHPSG13_LHPQX2 +XLATCH<0> CS ADDR<0> PADR<0> VDD VSS / RSC_IHPSG13_LHPQX2 +.ENDS +.SUBCKT RM_IHPSG13_512x8_c2_2P_DEC02 ADDR<1> ADDR<0> CS CS_OUT VDD VSS +XDEC ADDR<1> NADDR<0> CS net1 VDD VSS / RSC_IHPSG13_NAND3X2 +XADDRINV ADDR<0> NADDR<0> VDD VSS / RSC_IHPSG13_INVX2 +XDECINV net1 CS_OUT VDD VSS / RSC_IHPSG13_INVX4 +XI2<1> VDD VSS / RSC_IHPSG13_FILLCAP4 +XI2<0> VDD VSS / RSC_IHPSG13_FILLCAP4 +.ENDS +.SUBCKT RM_IHPSG13_512x8_c2_2P_DEC01 ADDR<1> ADDR<0> CS CS_OUT VDD VSS +XDEC NADDR<1> ADDR<0> CS net1 VDD VSS / RSC_IHPSG13_NAND3X2 +XADDRINV ADDR<1> NADDR<1> VDD VSS / RSC_IHPSG13_INVX2 +XDECINV net1 CS_OUT VDD VSS / RSC_IHPSG13_INVX4 +XI2<1> VDD VSS / RSC_IHPSG13_FILLCAP4 +XI2<0> VDD VSS / RSC_IHPSG13_FILLCAP4 +.ENDS +.SUBCKT RM_IHPSG13_512x8_c2_2P_DEC00 ADDR<1> ADDR<0> CS CS_OUT VDD VSS +XDEC NADDR<1> NADDR<0> CS net1 VDD VSS / RSC_IHPSG13_NAND3X2 +XADDRINV<1> ADDR<1> NADDR<1> VDD VSS / RSC_IHPSG13_INVX2 +XADDRINV<0> ADDR<0> NADDR<0> VDD VSS / RSC_IHPSG13_INVX2 +XI1<1> VDD VSS / RSC_IHPSG13_FILLCAP4 +XI1<0> VDD VSS / RSC_IHPSG13_FILLCAP4 +XDECINV net1 CS_OUT VDD VSS / RSC_IHPSG13_INVX4 +.ENDS +.SUBCKT RM_IHPSG13_512x8_c2_2P_DEC03 ADDR<1> ADDR<0> CS CS_OUT VDD VSS +XDEC ADDR<1> ADDR<0> CS net1 VDD VSS / RSC_IHPSG13_NAND3X2 +XDECINV net1 CS_OUT VDD VSS / RSC_IHPSG13_INVX4 +XI0<1> VDD VSS / RSC_IHPSG13_FILLCAP4 +XI0<0> VDD VSS / RSC_IHPSG13_FILLCAP4 +.ENDS +.SUBCKT RM_IHPSG13_512x8_c2_2P_ROWDEC9 ADDR_N_I<8> ADDR_N_I<7> ADDR_N_I<6> ADDR_N_I<5> ++ ADDR_N_I<4> ADDR_N_I<3> ADDR_N_I<2> ADDR_N_I<1> ADDR_N_I<0> CS_I ECLK_I ++ WL_O<511> WL_O<510> WL_O<509> WL_O<508> WL_O<507> WL_O<506> WL_O<505> ++ WL_O<504> WL_O<503> WL_O<502> WL_O<501> WL_O<500> WL_O<499> WL_O<498> ++ WL_O<497> WL_O<496> WL_O<495> WL_O<494> WL_O<493> WL_O<492> WL_O<491> ++ WL_O<490> WL_O<489> WL_O<488> WL_O<487> WL_O<486> WL_O<485> WL_O<484> ++ WL_O<483> WL_O<482> WL_O<481> WL_O<480> WL_O<479> WL_O<478> WL_O<477> ++ WL_O<476> WL_O<475> WL_O<474> WL_O<473> WL_O<472> WL_O<471> WL_O<470> ++ WL_O<469> WL_O<468> WL_O<467> WL_O<466> WL_O<465> WL_O<464> WL_O<463> ++ WL_O<462> WL_O<461> WL_O<460> WL_O<459> WL_O<458> WL_O<457> WL_O<456> ++ WL_O<455> WL_O<454> WL_O<453> WL_O<452> WL_O<451> WL_O<450> WL_O<449> ++ WL_O<448> WL_O<447> WL_O<446> WL_O<445> WL_O<444> WL_O<443> WL_O<442> ++ WL_O<441> WL_O<440> WL_O<439> WL_O<438> WL_O<437> WL_O<436> WL_O<435> ++ WL_O<434> WL_O<433> WL_O<432> WL_O<431> WL_O<430> WL_O<429> WL_O<428> ++ WL_O<427> WL_O<426> WL_O<425> WL_O<424> WL_O<423> WL_O<422> WL_O<421> ++ WL_O<420> WL_O<419> WL_O<418> WL_O<417> WL_O<416> WL_O<415> WL_O<414> ++ WL_O<413> WL_O<412> WL_O<411> WL_O<410> WL_O<409> WL_O<408> WL_O<407> ++ WL_O<406> WL_O<405> WL_O<404> WL_O<403> WL_O<402> WL_O<401> WL_O<400> ++ WL_O<399> WL_O<398> WL_O<397> WL_O<396> WL_O<395> WL_O<394> WL_O<393> ++ WL_O<392> WL_O<391> WL_O<390> WL_O<389> WL_O<388> WL_O<387> WL_O<386> ++ WL_O<385> WL_O<384> WL_O<383> WL_O<382> WL_O<381> WL_O<380> WL_O<379> ++ WL_O<378> WL_O<377> WL_O<376> WL_O<375> WL_O<374> WL_O<373> WL_O<372> ++ WL_O<371> WL_O<370> WL_O<369> WL_O<368> WL_O<367> WL_O<366> WL_O<365> ++ WL_O<364> WL_O<363> WL_O<362> WL_O<361> WL_O<360> WL_O<359> WL_O<358> ++ WL_O<357> WL_O<356> WL_O<355> WL_O<354> WL_O<353> WL_O<352> WL_O<351> ++ WL_O<350> WL_O<349> WL_O<348> WL_O<347> WL_O<346> WL_O<345> WL_O<344> ++ WL_O<343> WL_O<342> WL_O<341> WL_O<340> WL_O<339> WL_O<338> WL_O<337> ++ WL_O<336> WL_O<335> WL_O<334> WL_O<333> WL_O<332> WL_O<331> WL_O<330> ++ WL_O<329> WL_O<328> WL_O<327> WL_O<326> WL_O<325> WL_O<324> WL_O<323> ++ WL_O<322> WL_O<321> WL_O<320> WL_O<319> WL_O<318> WL_O<317> WL_O<316> ++ WL_O<315> WL_O<314> WL_O<313> WL_O<312> WL_O<311> WL_O<310> WL_O<309> ++ WL_O<308> WL_O<307> WL_O<306> WL_O<305> WL_O<304> WL_O<303> WL_O<302> ++ WL_O<301> WL_O<300> WL_O<299> WL_O<298> WL_O<297> WL_O<296> WL_O<295> ++ WL_O<294> WL_O<293> WL_O<292> WL_O<291> WL_O<290> WL_O<289> WL_O<288> ++ WL_O<287> WL_O<286> WL_O<285> WL_O<284> WL_O<283> WL_O<282> WL_O<281> ++ WL_O<280> WL_O<279> WL_O<278> WL_O<277> WL_O<276> WL_O<275> WL_O<274> ++ WL_O<273> WL_O<272> WL_O<271> WL_O<270> WL_O<269> WL_O<268> WL_O<267> ++ WL_O<266> WL_O<265> WL_O<264> WL_O<263> WL_O<262> WL_O<261> WL_O<260> ++ WL_O<259> WL_O<258> WL_O<257> WL_O<256> WL_O<255> WL_O<254> WL_O<253> ++ WL_O<252> WL_O<251> WL_O<250> WL_O<249> WL_O<248> WL_O<247> WL_O<246> ++ WL_O<245> WL_O<244> WL_O<243> WL_O<242> WL_O<241> WL_O<240> WL_O<239> ++ WL_O<238> WL_O<237> WL_O<236> WL_O<235> WL_O<234> WL_O<233> WL_O<232> ++ WL_O<231> WL_O<230> WL_O<229> WL_O<228> WL_O<227> WL_O<226> WL_O<225> ++ WL_O<224> WL_O<223> WL_O<222> WL_O<221> WL_O<220> WL_O<219> WL_O<218> ++ WL_O<217> WL_O<216> WL_O<215> WL_O<214> WL_O<213> WL_O<212> WL_O<211> ++ WL_O<210> WL_O<209> WL_O<208> WL_O<207> WL_O<206> WL_O<205> WL_O<204> ++ WL_O<203> WL_O<202> WL_O<201> WL_O<200> WL_O<199> WL_O<198> WL_O<197> ++ WL_O<196> WL_O<195> WL_O<194> WL_O<193> WL_O<192> WL_O<191> WL_O<190> ++ WL_O<189> WL_O<188> WL_O<187> WL_O<186> WL_O<185> WL_O<184> WL_O<183> ++ WL_O<182> WL_O<181> WL_O<180> WL_O<179> WL_O<178> WL_O<177> WL_O<176> ++ WL_O<175> WL_O<174> WL_O<173> WL_O<172> WL_O<171> WL_O<170> WL_O<169> ++ WL_O<168> WL_O<167> WL_O<166> WL_O<165> WL_O<164> WL_O<163> WL_O<162> ++ WL_O<161> WL_O<160> WL_O<159> WL_O<158> WL_O<157> WL_O<156> WL_O<155> ++ WL_O<154> WL_O<153> WL_O<152> WL_O<151> WL_O<150> WL_O<149> WL_O<148> ++ WL_O<147> WL_O<146> WL_O<145> WL_O<144> WL_O<143> WL_O<142> WL_O<141> ++ WL_O<140> WL_O<139> WL_O<138> WL_O<137> WL_O<136> WL_O<135> WL_O<134> ++ WL_O<133> WL_O<132> WL_O<131> WL_O<130> WL_O<129> WL_O<128> WL_O<127> ++ WL_O<126> WL_O<125> WL_O<124> WL_O<123> WL_O<122> WL_O<121> WL_O<120> ++ WL_O<119> WL_O<118> WL_O<117> WL_O<116> WL_O<115> WL_O<114> WL_O<113> ++ WL_O<112> WL_O<111> WL_O<110> WL_O<109> WL_O<108> WL_O<107> WL_O<106> ++ WL_O<105> WL_O<104> WL_O<103> WL_O<102> WL_O<101> WL_O<100> WL_O<99> ++ WL_O<98> WL_O<97> WL_O<96> WL_O<95> WL_O<94> WL_O<93> WL_O<92> WL_O<91> ++ WL_O<90> WL_O<89> WL_O<88> WL_O<87> WL_O<86> WL_O<85> WL_O<84> WL_O<83> ++ WL_O<82> WL_O<81> WL_O<80> WL_O<79> WL_O<78> WL_O<77> WL_O<76> WL_O<75> ++ WL_O<74> WL_O<73> WL_O<72> WL_O<71> WL_O<70> WL_O<69> WL_O<68> WL_O<67> ++ WL_O<66> WL_O<65> WL_O<64> WL_O<63> WL_O<62> WL_O<61> WL_O<60> WL_O<59> ++ WL_O<58> WL_O<57> WL_O<56> WL_O<55> WL_O<54> WL_O<53> WL_O<52> WL_O<51> ++ WL_O<50> WL_O<49> WL_O<48> WL_O<47> WL_O<46> WL_O<45> WL_O<44> WL_O<43> ++ WL_O<42> WL_O<41> WL_O<40> WL_O<39> WL_O<38> WL_O<37> WL_O<36> WL_O<35> ++ WL_O<34> WL_O<33> WL_O<32> WL_O<31> WL_O<30> WL_O<29> WL_O<28> WL_O<27> ++ WL_O<26> WL_O<25> WL_O<24> WL_O<23> WL_O<22> WL_O<21> WL_O<20> WL_O<19> ++ WL_O<18> WL_O<17> WL_O<16> WL_O<15> WL_O<14> WL_O<13> WL_O<12> WL_O<11> ++ WL_O<10> WL_O<9> WL_O<8> WL_O<7> WL_O<6> WL_O<5> WL_O<4> WL_O<3> WL_O<2> ++ WL_O<1> WL_O<0> VDD VSS +XSEL<31> ADDR_N_I<3> ADDR_N_I<2> ADDR_N_I<1> ADDR_N_I<0> CS00<31> ECLK_H<31> ++ ECLK_H<32> ECLK_B<31> ECLK_B<32> WL_O<511> WL_O<510> WL_O<509> WL_O<508> ++ WL_O<507> WL_O<506> WL_O<505> WL_O<504> WL_O<503> WL_O<502> WL_O<501> ++ WL_O<500> WL_O<499> WL_O<498> WL_O<497> WL_O<496> VDD VSS / ++ RM_IHPSG13_512x8_c2_2P_DEC04 +XSEL<30> ADDR_N_I<3> ADDR_N_I<2> ADDR_N_I<1> ADDR_N_I<0> CS00<30> ECLK_H<30> ++ ECLK_H<31> ECLK_B<30> ECLK_B<31> WL_O<495> WL_O<494> WL_O<493> WL_O<492> ++ WL_O<491> WL_O<490> WL_O<489> WL_O<488> WL_O<487> WL_O<486> WL_O<485> ++ WL_O<484> WL_O<483> WL_O<482> WL_O<481> WL_O<480> VDD VSS / ++ RM_IHPSG13_512x8_c2_2P_DEC04 +XSEL<29> ADDR_N_I<3> ADDR_N_I<2> ADDR_N_I<1> ADDR_N_I<0> CS00<29> ECLK_H<29> ++ ECLK_H<30> ECLK_B<29> ECLK_B<30> WL_O<479> WL_O<478> WL_O<477> WL_O<476> ++ WL_O<475> WL_O<474> WL_O<473> WL_O<472> WL_O<471> WL_O<470> WL_O<469> ++ WL_O<468> WL_O<467> WL_O<466> WL_O<465> WL_O<464> VDD VSS / ++ RM_IHPSG13_512x8_c2_2P_DEC04 +XSEL<28> ADDR_N_I<3> ADDR_N_I<2> ADDR_N_I<1> ADDR_N_I<0> CS00<28> ECLK_H<28> ++ ECLK_H<29> ECLK_B<28> ECLK_B<29> WL_O<463> WL_O<462> WL_O<461> WL_O<460> ++ WL_O<459> WL_O<458> WL_O<457> WL_O<456> WL_O<455> WL_O<454> WL_O<453> ++ WL_O<452> WL_O<451> WL_O<450> WL_O<449> WL_O<448> VDD VSS / ++ RM_IHPSG13_512x8_c2_2P_DEC04 +XSEL<27> ADDR_N_I<3> ADDR_N_I<2> ADDR_N_I<1> ADDR_N_I<0> CS00<27> ECLK_H<27> ++ ECLK_H<28> ECLK_B<27> ECLK_B<28> WL_O<447> WL_O<446> WL_O<445> WL_O<444> ++ WL_O<443> WL_O<442> WL_O<441> WL_O<440> WL_O<439> WL_O<438> WL_O<437> ++ WL_O<436> WL_O<435> WL_O<434> WL_O<433> WL_O<432> VDD VSS / ++ RM_IHPSG13_512x8_c2_2P_DEC04 +XSEL<26> ADDR_N_I<3> ADDR_N_I<2> ADDR_N_I<1> ADDR_N_I<0> CS00<26> ECLK_H<26> ++ ECLK_H<27> ECLK_B<26> ECLK_B<27> WL_O<431> WL_O<430> WL_O<429> WL_O<428> ++ WL_O<427> WL_O<426> WL_O<425> WL_O<424> WL_O<423> WL_O<422> WL_O<421> ++ WL_O<420> WL_O<419> WL_O<418> WL_O<417> WL_O<416> VDD VSS / ++ RM_IHPSG13_512x8_c2_2P_DEC04 +XSEL<25> ADDR_N_I<3> ADDR_N_I<2> ADDR_N_I<1> ADDR_N_I<0> CS00<25> ECLK_H<25> ++ ECLK_H<26> ECLK_B<25> ECLK_B<26> WL_O<415> WL_O<414> WL_O<413> WL_O<412> ++ WL_O<411> WL_O<410> WL_O<409> WL_O<408> WL_O<407> WL_O<406> WL_O<405> ++ WL_O<404> WL_O<403> WL_O<402> WL_O<401> WL_O<400> VDD VSS / ++ RM_IHPSG13_512x8_c2_2P_DEC04 +XSEL<24> ADDR_N_I<3> ADDR_N_I<2> ADDR_N_I<1> ADDR_N_I<0> CS00<24> ECLK_H<24> ++ ECLK_H<25> ECLK_B<24> ECLK_B<25> WL_O<399> WL_O<398> WL_O<397> WL_O<396> ++ WL_O<395> WL_O<394> WL_O<393> WL_O<392> WL_O<391> WL_O<390> WL_O<389> ++ WL_O<388> WL_O<387> WL_O<386> WL_O<385> WL_O<384> VDD VSS / ++ RM_IHPSG13_512x8_c2_2P_DEC04 +XSEL<23> ADDR_N_I<3> ADDR_N_I<2> ADDR_N_I<1> ADDR_N_I<0> CS00<23> ECLK_H<23> ++ ECLK_H<24> ECLK_B<23> ECLK_B<24> WL_O<383> WL_O<382> WL_O<381> WL_O<380> ++ WL_O<379> WL_O<378> WL_O<377> WL_O<376> WL_O<375> WL_O<374> WL_O<373> ++ WL_O<372> WL_O<371> WL_O<370> WL_O<369> WL_O<368> VDD VSS / ++ RM_IHPSG13_512x8_c2_2P_DEC04 +XSEL<22> ADDR_N_I<3> ADDR_N_I<2> ADDR_N_I<1> ADDR_N_I<0> CS00<22> ECLK_H<22> ++ ECLK_H<23> ECLK_B<22> ECLK_B<23> WL_O<367> WL_O<366> WL_O<365> WL_O<364> ++ WL_O<363> WL_O<362> WL_O<361> WL_O<360> WL_O<359> WL_O<358> WL_O<357> ++ WL_O<356> WL_O<355> WL_O<354> WL_O<353> WL_O<352> VDD VSS / ++ RM_IHPSG13_512x8_c2_2P_DEC04 +XSEL<21> ADDR_N_I<3> ADDR_N_I<2> ADDR_N_I<1> ADDR_N_I<0> CS00<21> ECLK_H<21> ++ ECLK_H<22> ECLK_B<21> ECLK_B<22> WL_O<351> WL_O<350> WL_O<349> WL_O<348> ++ WL_O<347> WL_O<346> WL_O<345> WL_O<344> WL_O<343> WL_O<342> WL_O<341> ++ WL_O<340> WL_O<339> WL_O<338> WL_O<337> WL_O<336> VDD VSS / ++ RM_IHPSG13_512x8_c2_2P_DEC04 +XSEL<20> ADDR_N_I<3> ADDR_N_I<2> ADDR_N_I<1> ADDR_N_I<0> CS00<20> ECLK_H<20> ++ ECLK_H<21> ECLK_B<20> ECLK_B<21> WL_O<335> WL_O<334> WL_O<333> WL_O<332> ++ WL_O<331> WL_O<330> WL_O<329> WL_O<328> WL_O<327> WL_O<326> WL_O<325> ++ WL_O<324> WL_O<323> WL_O<322> WL_O<321> WL_O<320> VDD VSS / ++ RM_IHPSG13_512x8_c2_2P_DEC04 +XSEL<19> ADDR_N_I<3> ADDR_N_I<2> ADDR_N_I<1> ADDR_N_I<0> CS00<19> ECLK_H<19> ++ ECLK_H<20> ECLK_B<19> ECLK_B<20> WL_O<319> WL_O<318> WL_O<317> WL_O<316> ++ WL_O<315> WL_O<314> WL_O<313> WL_O<312> WL_O<311> WL_O<310> WL_O<309> ++ WL_O<308> WL_O<307> WL_O<306> WL_O<305> WL_O<304> VDD VSS / ++ RM_IHPSG13_512x8_c2_2P_DEC04 +XSEL<18> ADDR_N_I<3> ADDR_N_I<2> ADDR_N_I<1> ADDR_N_I<0> CS00<18> ECLK_H<18> ++ ECLK_H<19> ECLK_B<18> ECLK_B<19> WL_O<303> WL_O<302> WL_O<301> WL_O<300> ++ WL_O<299> WL_O<298> WL_O<297> WL_O<296> WL_O<295> WL_O<294> WL_O<293> ++ WL_O<292> WL_O<291> WL_O<290> WL_O<289> WL_O<288> VDD VSS / ++ RM_IHPSG13_512x8_c2_2P_DEC04 +XSEL<17> ADDR_N_I<3> ADDR_N_I<2> ADDR_N_I<1> ADDR_N_I<0> CS00<17> ECLK_H<17> ++ ECLK_H<18> ECLK_B<17> ECLK_B<18> WL_O<287> WL_O<286> WL_O<285> WL_O<284> ++ WL_O<283> WL_O<282> WL_O<281> WL_O<280> WL_O<279> WL_O<278> WL_O<277> ++ WL_O<276> WL_O<275> WL_O<274> WL_O<273> WL_O<272> VDD VSS / ++ RM_IHPSG13_512x8_c2_2P_DEC04 +XSEL<16> ADDR_N_I<3> ADDR_N_I<2> ADDR_N_I<1> ADDR_N_I<0> CS00<16> ECLK_H<16> ++ ECLK_H<17> ECLK_B<16> ECLK_B<17> WL_O<271> WL_O<270> WL_O<269> WL_O<268> ++ WL_O<267> WL_O<266> WL_O<265> WL_O<264> WL_O<263> WL_O<262> WL_O<261> ++ WL_O<260> WL_O<259> WL_O<258> WL_O<257> WL_O<256> VDD VSS / ++ RM_IHPSG13_512x8_c2_2P_DEC04 +XSEL<15> ADDR_N_I<3> ADDR_N_I<2> ADDR_N_I<1> ADDR_N_I<0> CS00<15> ECLK_H<15> ++ ECLK_H<16> ECLK_B<15> ECLK_B<16> WL_O<255> WL_O<254> WL_O<253> WL_O<252> ++ WL_O<251> WL_O<250> WL_O<249> WL_O<248> WL_O<247> WL_O<246> WL_O<245> ++ WL_O<244> WL_O<243> WL_O<242> WL_O<241> WL_O<240> VDD VSS / ++ RM_IHPSG13_512x8_c2_2P_DEC04 +XSEL<14> ADDR_N_I<3> ADDR_N_I<2> ADDR_N_I<1> ADDR_N_I<0> CS00<14> ECLK_H<14> ++ ECLK_H<15> ECLK_B<14> ECLK_B<15> WL_O<239> WL_O<238> WL_O<237> WL_O<236> ++ WL_O<235> WL_O<234> WL_O<233> WL_O<232> WL_O<231> WL_O<230> WL_O<229> ++ WL_O<228> WL_O<227> WL_O<226> WL_O<225> WL_O<224> VDD VSS / ++ RM_IHPSG13_512x8_c2_2P_DEC04 +XSEL<13> ADDR_N_I<3> ADDR_N_I<2> ADDR_N_I<1> ADDR_N_I<0> CS00<13> ECLK_H<13> ++ ECLK_H<14> ECLK_B<13> ECLK_B<14> WL_O<223> WL_O<222> WL_O<221> WL_O<220> ++ WL_O<219> WL_O<218> WL_O<217> WL_O<216> WL_O<215> WL_O<214> WL_O<213> ++ WL_O<212> WL_O<211> WL_O<210> WL_O<209> WL_O<208> VDD VSS / ++ RM_IHPSG13_512x8_c2_2P_DEC04 +XSEL<12> ADDR_N_I<3> ADDR_N_I<2> ADDR_N_I<1> ADDR_N_I<0> CS00<12> ECLK_H<12> ++ ECLK_H<13> ECLK_B<12> ECLK_B<13> WL_O<207> WL_O<206> WL_O<205> WL_O<204> ++ WL_O<203> WL_O<202> WL_O<201> WL_O<200> WL_O<199> WL_O<198> WL_O<197> ++ WL_O<196> WL_O<195> WL_O<194> WL_O<193> WL_O<192> VDD VSS / ++ RM_IHPSG13_512x8_c2_2P_DEC04 +XSEL<11> ADDR_N_I<3> ADDR_N_I<2> ADDR_N_I<1> ADDR_N_I<0> CS00<11> ECLK_H<11> ++ ECLK_H<12> ECLK_B<11> ECLK_B<12> WL_O<191> WL_O<190> WL_O<189> WL_O<188> ++ WL_O<187> WL_O<186> WL_O<185> WL_O<184> WL_O<183> WL_O<182> WL_O<181> ++ WL_O<180> WL_O<179> WL_O<178> WL_O<177> WL_O<176> VDD VSS / ++ RM_IHPSG13_512x8_c2_2P_DEC04 +XSEL<10> ADDR_N_I<3> ADDR_N_I<2> ADDR_N_I<1> ADDR_N_I<0> CS00<10> ECLK_H<10> ++ ECLK_H<11> ECLK_B<10> ECLK_B<11> WL_O<175> WL_O<174> WL_O<173> WL_O<172> ++ WL_O<171> WL_O<170> WL_O<169> WL_O<168> WL_O<167> WL_O<166> WL_O<165> ++ WL_O<164> WL_O<163> WL_O<162> WL_O<161> WL_O<160> VDD VSS / ++ RM_IHPSG13_512x8_c2_2P_DEC04 +XSEL<9> ADDR_N_I<3> ADDR_N_I<2> ADDR_N_I<1> ADDR_N_I<0> CS00<9> ECLK_H<9> ++ ECLK_H<10> ECLK_B<9> ECLK_B<10> WL_O<159> WL_O<158> WL_O<157> WL_O<156> ++ WL_O<155> WL_O<154> WL_O<153> WL_O<152> WL_O<151> WL_O<150> WL_O<149> ++ WL_O<148> WL_O<147> WL_O<146> WL_O<145> WL_O<144> VDD VSS / ++ RM_IHPSG13_512x8_c2_2P_DEC04 +XSEL<8> ADDR_N_I<3> ADDR_N_I<2> ADDR_N_I<1> ADDR_N_I<0> CS00<8> ECLK_H<8> ++ ECLK_H<9> ECLK_B<8> ECLK_B<9> WL_O<143> WL_O<142> WL_O<141> WL_O<140> ++ WL_O<139> WL_O<138> WL_O<137> WL_O<136> WL_O<135> WL_O<134> WL_O<133> ++ WL_O<132> WL_O<131> WL_O<130> WL_O<129> WL_O<128> VDD VSS / ++ RM_IHPSG13_512x8_c2_2P_DEC04 +XSEL<7> ADDR_N_I<3> ADDR_N_I<2> ADDR_N_I<1> ADDR_N_I<0> CS00<7> ECLK_H<7> ++ ECLK_H<8> ECLK_B<7> ECLK_B<8> WL_O<127> WL_O<126> WL_O<125> WL_O<124> ++ WL_O<123> WL_O<122> WL_O<121> WL_O<120> WL_O<119> WL_O<118> WL_O<117> ++ WL_O<116> WL_O<115> WL_O<114> WL_O<113> WL_O<112> VDD VSS / ++ RM_IHPSG13_512x8_c2_2P_DEC04 +XSEL<6> ADDR_N_I<3> ADDR_N_I<2> ADDR_N_I<1> ADDR_N_I<0> CS00<6> ECLK_H<6> ++ ECLK_H<7> ECLK_B<6> ECLK_B<7> WL_O<111> WL_O<110> WL_O<109> WL_O<108> ++ WL_O<107> WL_O<106> WL_O<105> WL_O<104> WL_O<103> WL_O<102> WL_O<101> ++ WL_O<100> WL_O<99> WL_O<98> WL_O<97> WL_O<96> VDD VSS / ++ RM_IHPSG13_512x8_c2_2P_DEC04 +XSEL<5> ADDR_N_I<3> ADDR_N_I<2> ADDR_N_I<1> ADDR_N_I<0> CS00<5> ECLK_H<5> ++ ECLK_H<6> ECLK_B<5> ECLK_B<6> WL_O<95> WL_O<94> WL_O<93> WL_O<92> WL_O<91> ++ WL_O<90> WL_O<89> WL_O<88> WL_O<87> WL_O<86> WL_O<85> WL_O<84> WL_O<83> ++ WL_O<82> WL_O<81> WL_O<80> VDD VSS / RM_IHPSG13_512x8_c2_2P_DEC04 +XSEL<4> ADDR_N_I<3> ADDR_N_I<2> ADDR_N_I<1> ADDR_N_I<0> CS00<4> ECLK_H<4> ++ ECLK_H<5> ECLK_B<4> ECLK_B<5> WL_O<79> WL_O<78> WL_O<77> WL_O<76> WL_O<75> ++ WL_O<74> WL_O<73> WL_O<72> WL_O<71> WL_O<70> WL_O<69> WL_O<68> WL_O<67> ++ WL_O<66> WL_O<65> WL_O<64> VDD VSS / RM_IHPSG13_512x8_c2_2P_DEC04 +XSEL<3> ADDR_N_I<3> ADDR_N_I<2> ADDR_N_I<1> ADDR_N_I<0> CS00<3> ECLK_H<3> ++ ECLK_H<4> ECLK_B<3> ECLK_B<4> WL_O<63> WL_O<62> WL_O<61> WL_O<60> WL_O<59> ++ WL_O<58> WL_O<57> WL_O<56> WL_O<55> WL_O<54> WL_O<53> WL_O<52> WL_O<51> ++ WL_O<50> WL_O<49> WL_O<48> VDD VSS / RM_IHPSG13_512x8_c2_2P_DEC04 +XSEL<2> ADDR_N_I<3> ADDR_N_I<2> ADDR_N_I<1> ADDR_N_I<0> CS00<2> ECLK_H<2> ++ ECLK_H<3> ECLK_B<2> ECLK_B<3> WL_O<47> WL_O<46> WL_O<45> WL_O<44> WL_O<43> ++ WL_O<42> WL_O<41> WL_O<40> WL_O<39> WL_O<38> WL_O<37> WL_O<36> WL_O<35> ++ WL_O<34> WL_O<33> WL_O<32> VDD VSS / RM_IHPSG13_512x8_c2_2P_DEC04 +XSEL<1> ADDR_N_I<3> ADDR_N_I<2> ADDR_N_I<1> ADDR_N_I<0> CS00<1> ECLK_H<1> ++ ECLK_H<2> ECLK_B<1> ECLK_B<2> WL_O<31> WL_O<30> WL_O<29> WL_O<28> WL_O<27> ++ WL_O<26> WL_O<25> WL_O<24> WL_O<23> WL_O<22> WL_O<21> WL_O<20> WL_O<19> ++ WL_O<18> WL_O<17> WL_O<16> VDD VSS / RM_IHPSG13_512x8_c2_2P_DEC04 +XSEL<0> ADDR_N_I<3> ADDR_N_I<2> ADDR_N_I<1> ADDR_N_I<0> CS00<0> ECLK_I ++ ECLK_H<1> ECLK_B<0> ECLK_B<1> WL_O<15> WL_O<14> WL_O<13> WL_O<12> WL_O<11> ++ WL_O<10> WL_O<9> WL_O<8> WL_O<7> WL_O<6> WL_O<5> WL_O<4> WL_O<3> WL_O<2> ++ WL_O<1> WL_O<0> VDD VSS / RM_IHPSG13_512x8_c2_2P_DEC04 +XDEC10<9> ADDR_N_I<7> ADDR_N_I<6> CS04<1> CS02<6> VDD VSS / ++ RM_IHPSG13_512x8_c2_2P_DEC02 +XDEC10<8> ADDR_N_I<7> ADDR_N_I<6> CS04<0> CS02<2> VDD VSS / ++ RM_IHPSG13_512x8_c2_2P_DEC02 +XDEC10<7> ADDR_N_I<5> ADDR_N_I<4> CS02<7> CS00<30> VDD VSS / ++ RM_IHPSG13_512x8_c2_2P_DEC02 +XDEC10<6> ADDR_N_I<5> ADDR_N_I<4> CS02<6> CS00<26> VDD VSS / ++ RM_IHPSG13_512x8_c2_2P_DEC02 +XDEC10<5> ADDR_N_I<5> ADDR_N_I<4> CS02<5> CS00<22> VDD VSS / ++ RM_IHPSG13_512x8_c2_2P_DEC02 +XDEC10<4> ADDR_N_I<5> ADDR_N_I<4> CS02<4> CS00<18> VDD VSS / ++ RM_IHPSG13_512x8_c2_2P_DEC02 +XDEC10<3> ADDR_N_I<5> ADDR_N_I<4> CS02<3> CS00<14> VDD VSS / ++ RM_IHPSG13_512x8_c2_2P_DEC02 +XDEC10<2> ADDR_N_I<5> ADDR_N_I<4> CS02<2> CS00<10> VDD VSS / ++ RM_IHPSG13_512x8_c2_2P_DEC02 +XDEC10<1> ADDR_N_I<5> ADDR_N_I<4> CS02<1> CS00<6> VDD VSS / ++ RM_IHPSG13_512x8_c2_2P_DEC02 +XDEC10<0> ADDR_N_I<5> ADDR_N_I<4> CS02<0> CS00<2> VDD VSS / ++ RM_IHPSG13_512x8_c2_2P_DEC02 +XDEC01<10> ADDR_N_I<9> ADDR_N_I<8> CS_I CS04<1> VDD VSS / ++ RM_IHPSG13_512x8_c2_2P_DEC01 +XDEC01<9> ADDR_N_I<7> ADDR_N_I<6> CS04<1> CS02<5> VDD VSS / ++ RM_IHPSG13_512x8_c2_2P_DEC01 +XDEC01<8> ADDR_N_I<7> ADDR_N_I<6> CS04<0> CS02<1> VDD VSS / ++ RM_IHPSG13_512x8_c2_2P_DEC01 +XDEC01<7> ADDR_N_I<5> ADDR_N_I<4> CS02<7> CS00<29> VDD VSS / ++ RM_IHPSG13_512x8_c2_2P_DEC01 +XDEC01<6> ADDR_N_I<5> ADDR_N_I<4> CS02<6> CS00<25> VDD VSS / ++ RM_IHPSG13_512x8_c2_2P_DEC01 +XDEC01<5> ADDR_N_I<5> ADDR_N_I<4> CS02<5> CS00<21> VDD VSS / ++ RM_IHPSG13_512x8_c2_2P_DEC01 +XDEC01<4> ADDR_N_I<5> ADDR_N_I<4> CS02<4> CS00<17> VDD VSS / ++ RM_IHPSG13_512x8_c2_2P_DEC01 +XDEC01<3> ADDR_N_I<5> ADDR_N_I<4> CS02<3> CS00<13> VDD VSS / ++ RM_IHPSG13_512x8_c2_2P_DEC01 +XDEC01<2> ADDR_N_I<5> ADDR_N_I<4> CS02<2> CS00<9> VDD VSS / ++ RM_IHPSG13_512x8_c2_2P_DEC01 +XDEC01<1> ADDR_N_I<5> ADDR_N_I<4> CS02<1> CS00<5> VDD VSS / ++ RM_IHPSG13_512x8_c2_2P_DEC01 +XDEC01<0> ADDR_N_I<5> ADDR_N_I<4> CS02<0> CS00<1> VDD VSS / ++ RM_IHPSG13_512x8_c2_2P_DEC01 +XL2<258> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<257> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<256> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<255> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<254> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<253> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<252> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<251> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<250> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<249> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<248> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<247> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<246> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<245> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<244> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<243> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<242> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<241> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<240> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<239> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<238> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<237> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<236> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<235> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<234> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<233> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<232> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<231> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<230> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<229> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<228> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<227> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<226> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<225> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<224> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<223> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<222> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<221> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<220> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<219> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<218> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<217> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<216> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<215> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<214> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<213> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<212> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<211> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<210> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<209> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<208> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<207> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<206> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<205> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<204> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<203> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<202> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<201> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<200> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<199> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<198> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<197> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<196> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<195> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<194> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<193> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<192> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<191> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<190> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<189> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<188> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<187> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<186> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<185> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<184> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<183> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<182> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<181> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<180> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<179> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<178> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<177> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<176> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<175> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<174> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<173> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<172> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<171> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<170> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<169> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<168> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<167> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<166> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<165> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<164> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<163> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<162> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<161> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<160> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<159> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<158> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<157> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<156> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<155> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<154> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<153> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<152> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<151> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<150> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<149> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<148> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<147> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<146> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<145> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<144> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<143> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<142> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<141> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<140> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<139> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<138> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<137> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<136> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<135> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<134> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<133> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<132> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<131> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<130> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<129> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<128> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<127> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<126> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<125> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<124> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<123> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<122> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<121> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<120> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<119> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<118> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<117> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<116> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<115> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<114> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<113> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<112> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<111> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<110> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<109> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<108> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<107> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<106> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<105> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<104> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<103> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<102> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<101> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<100> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<99> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<98> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<97> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<96> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<95> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<94> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<93> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<92> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<91> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<90> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<89> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<88> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<87> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<86> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<85> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<84> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<83> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<82> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<81> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<80> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<79> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<78> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<77> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<76> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<75> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<74> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<73> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<72> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<71> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<70> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<69> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<68> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<67> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<66> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<65> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<64> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<63> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<62> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<61> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<60> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<59> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<58> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<57> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<56> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<55> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<54> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<53> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<52> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<51> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<50> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<49> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<48> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<47> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<46> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<45> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<44> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<43> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<42> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<41> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<40> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<39> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<38> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<37> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<36> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<35> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<34> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<33> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<32> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<31> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<30> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<29> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<28> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<27> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<26> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<25> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<24> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<23> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<22> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<21> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<20> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<19> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<18> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<17> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<16> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<15> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<14> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<13> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<12> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<11> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<10> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<9> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<8> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<7> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<6> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<5> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<4> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<3> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<2> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<1> VDD VSS / RSC_IHPSG13_FILLCAP8 +XDEC00<10> ADDR_N_I<9> ADDR_N_I<8> CS_I CS04<0> VDD VSS / ++ RM_IHPSG13_512x8_c2_2P_DEC00 +XDEC00<9> ADDR_N_I<7> ADDR_N_I<6> CS04<1> CS02<4> VDD VSS / ++ RM_IHPSG13_512x8_c2_2P_DEC00 +XDEC00<8> ADDR_N_I<7> ADDR_N_I<6> CS04<0> CS02<0> VDD VSS / ++ RM_IHPSG13_512x8_c2_2P_DEC00 +XDEC00<7> ADDR_N_I<5> ADDR_N_I<4> CS02<7> CS00<28> VDD VSS / ++ RM_IHPSG13_512x8_c2_2P_DEC00 +XDEC00<6> ADDR_N_I<5> ADDR_N_I<4> CS02<6> CS00<24> VDD VSS / ++ RM_IHPSG13_512x8_c2_2P_DEC00 +XDEC00<5> ADDR_N_I<5> ADDR_N_I<4> CS02<5> CS00<20> VDD VSS / ++ RM_IHPSG13_512x8_c2_2P_DEC00 +XDEC00<4> ADDR_N_I<5> ADDR_N_I<4> CS02<4> CS00<16> VDD VSS / ++ RM_IHPSG13_512x8_c2_2P_DEC00 +XDEC00<3> ADDR_N_I<5> ADDR_N_I<4> CS02<3> CS00<12> VDD VSS / ++ RM_IHPSG13_512x8_c2_2P_DEC00 +XDEC00<2> ADDR_N_I<5> ADDR_N_I<4> CS02<2> CS00<8> VDD VSS / ++ RM_IHPSG13_512x8_c2_2P_DEC00 +XDEC00<1> ADDR_N_I<5> ADDR_N_I<4> CS02<1> CS00<4> VDD VSS / ++ RM_IHPSG13_512x8_c2_2P_DEC00 +XDEC00<0> ADDR_N_I<5> ADDR_N_I<4> CS02<0> CS00<0> VDD VSS / ++ RM_IHPSG13_512x8_c2_2P_DEC00 +XDEC11<9> ADDR_N_I<7> ADDR_N_I<6> CS04<1> CS02<7> VDD VSS / ++ RM_IHPSG13_512x8_c2_2P_DEC03 +XDEC11<8> ADDR_N_I<7> ADDR_N_I<6> CS04<0> CS02<3> VDD VSS / ++ RM_IHPSG13_512x8_c2_2P_DEC03 +XDEC11<7> ADDR_N_I<5> ADDR_N_I<4> CS02<7> CS00<31> VDD VSS / ++ RM_IHPSG13_512x8_c2_2P_DEC03 +XDEC11<6> ADDR_N_I<5> ADDR_N_I<4> CS02<6> CS00<27> VDD VSS / ++ RM_IHPSG13_512x8_c2_2P_DEC03 +XDEC11<5> ADDR_N_I<5> ADDR_N_I<4> CS02<5> CS00<23> VDD VSS / ++ RM_IHPSG13_512x8_c2_2P_DEC03 +XDEC11<4> ADDR_N_I<5> ADDR_N_I<4> CS02<4> CS00<19> VDD VSS / ++ RM_IHPSG13_512x8_c2_2P_DEC03 +XDEC11<3> ADDR_N_I<5> ADDR_N_I<4> CS02<3> CS00<15> VDD VSS / ++ RM_IHPSG13_512x8_c2_2P_DEC03 +XDEC11<2> ADDR_N_I<5> ADDR_N_I<4> CS02<2> CS00<11> VDD VSS / ++ RM_IHPSG13_512x8_c2_2P_DEC03 +XDEC11<1> ADDR_N_I<5> ADDR_N_I<4> CS02<1> CS00<7> VDD VSS / ++ RM_IHPSG13_512x8_c2_2P_DEC03 +XDEC11<0> ADDR_N_I<5> ADDR_N_I<4> CS02<0> CS00<3> VDD VSS / ++ RM_IHPSG13_512x8_c2_2P_DEC03 +XI0 ADDR_N_I<9> VDD VSS / RSC_IHPSG13_TIEL +.ENDS +.SUBCKT RM_IHPSG13_512x8_c2_2P_ROWREG9 ACLK_N_I ADDR_I<8> ADDR_I<7> ADDR_I<6> ADDR_I<5> ++ ADDR_I<4> ADDR_I<3> ADDR_I<2> ADDR_I<1> ADDR_I<0> ADDR_N_O<8> ADDR_N_O<7> ++ ADDR_N_O<6> ADDR_N_O<5> ADDR_N_O<4> ADDR_N_O<3> ADDR_N_O<2> ADDR_N_O<1> ++ ADDR_N_O<0> BIST_ADDR_I<8> BIST_ADDR_I<7> BIST_ADDR_I<6> BIST_ADDR_I<5> ++ BIST_ADDR_I<4> BIST_ADDR_I<3> BIST_ADDR_I<2> BIST_ADDR_I<1> BIST_ADDR_I<0> ++ BIST_EN_I VDD VSS +XDFF<8> BIST_EN_I BIST_ADDR_I<8> ACLK_N_I ADDR_I<8> q_int<8> net04<0> VDD ++ VSS / RSC_IHPSG13_DFNQMX2IX1 +XDFF<7> BIST_EN_I BIST_ADDR_I<7> ACLK_N_I ADDR_I<7> q_int<7> net04<1> VDD ++ VSS / RSC_IHPSG13_DFNQMX2IX1 +XDFF<6> BIST_EN_I BIST_ADDR_I<6> ACLK_N_I ADDR_I<6> q_int<6> net04<2> VDD ++ VSS / RSC_IHPSG13_DFNQMX2IX1 +XDFF<5> BIST_EN_I BIST_ADDR_I<5> ACLK_N_I ADDR_I<5> q_int<5> net04<3> VDD ++ VSS / RSC_IHPSG13_DFNQMX2IX1 +XDFF<4> BIST_EN_I BIST_ADDR_I<4> ACLK_N_I ADDR_I<4> q_int<4> net04<4> VDD ++ VSS / RSC_IHPSG13_DFNQMX2IX1 +XDFF<3> BIST_EN_I BIST_ADDR_I<3> ACLK_N_I ADDR_I<3> q_int<3> net04<5> VDD ++ VSS / RSC_IHPSG13_DFNQMX2IX1 +XDFF<2> BIST_EN_I BIST_ADDR_I<2> ACLK_N_I ADDR_I<2> q_int<2> net04<6> VDD ++ VSS / RSC_IHPSG13_DFNQMX2IX1 +XDFF<1> BIST_EN_I BIST_ADDR_I<1> ACLK_N_I ADDR_I<1> q_int<1> net04<7> VDD ++ VSS / RSC_IHPSG13_DFNQMX2IX1 +XDFF<0> BIST_EN_I BIST_ADDR_I<0> ACLK_N_I ADDR_I<0> q_int<0> net04<8> VDD ++ VSS / RSC_IHPSG13_DFNQMX2IX1 +XDRV<8> qn_int<8> ADDR_N_O<8> VDD VSS / RSC_IHPSG13_CINVX8 +XDRV<7> qn_int<7> ADDR_N_O<7> VDD VSS / RSC_IHPSG13_CINVX8 +XDRV<6> qn_int<6> ADDR_N_O<6> VDD VSS / RSC_IHPSG13_CINVX8 +XDRV<5> qn_int<5> ADDR_N_O<5> VDD VSS / RSC_IHPSG13_CINVX8 +XDRV<4> qn_int<4> ADDR_N_O<4> VDD VSS / RSC_IHPSG13_CINVX8 +XDRV<3> qn_int<3> ADDR_N_O<3> VDD VSS / RSC_IHPSG13_CINVX8 +XDRV<2> qn_int<2> ADDR_N_O<2> VDD VSS / RSC_IHPSG13_CINVX8 +XDRV<1> qn_int<1> ADDR_N_O<1> VDD VSS / RSC_IHPSG13_CINVX8 +XDRV<0> qn_int<0> ADDR_N_O<0> VDD VSS / RSC_IHPSG13_CINVX8 +XINV<8> q_int<8> qn_int<8> VDD VSS / RSC_IHPSG13_CINVX2 +XINV<7> q_int<7> qn_int<7> VDD VSS / RSC_IHPSG13_CINVX2 +XINV<6> q_int<6> qn_int<6> VDD VSS / RSC_IHPSG13_CINVX2 +XINV<5> q_int<5> qn_int<5> VDD VSS / RSC_IHPSG13_CINVX2 +XINV<4> q_int<4> qn_int<4> VDD VSS / RSC_IHPSG13_CINVX2 +XINV<3> q_int<3> qn_int<3> VDD VSS / RSC_IHPSG13_CINVX2 +XINV<2> q_int<2> qn_int<2> VDD VSS / RSC_IHPSG13_CINVX2 +XINV<1> q_int<1> qn_int<1> VDD VSS / RSC_IHPSG13_CINVX2 +XINV<0> q_int<0> qn_int<0> VDD VSS / RSC_IHPSG13_CINVX2 +.ENDS + +.SUBCKT RM_IHPSG13_512x8_c2_2P_DLY_MUX A SEL Z VDD VSS +XI11 net4 Z VDD VSS / RSC_IHPSG13_CINVX2 +XI8 A D<3> SEL net4 VDD VSS / RSC_IHPSG13_MX2IX1 +XI20<3> D<2> D<3> VDD VSS / RSC_IHPSG13_CDLYX1 +XI20<2> D<1> D<2> VDD VSS / RSC_IHPSG13_CDLYX1 +XI20<1> A D<1> VDD VSS / RSC_IHPSG13_CDLYX1 +.ENDS +.SUBCKT RM_IHPSG13_512x8_c2_2P_CTRL ACLK_N BIST_CK_I BIST_CS_I BIST_EN BIST_RE_I ++ BIST_WE_I B_TIEL_O CK_I CS_I DCLK ECLK PULSE_H PULSE_L PULSE_O RCLK RE_I ++ ROW_CS WCLK WE_I VDD VSS +XI17 ck_regs we col_we VDD VSS / RSC_IHPSG13_DFNQX2 +XI16 ck_regs re col_re VDD VSS / RSC_IHPSG13_DFNQX2 +XI18 ck_regs cs net7 VDD VSS / RSC_IHPSG13_DFNQX2 +XI71 ACLK_N net012 PULSE_O VDD VSS / RSC_IHPSG13_DFNQX2 +XI77 col_we net017 net016 VDD VSS / RSC_IHPSG13_CNAND2X2 +XI76 col_re net017 net018 VDD VSS / RSC_IHPSG13_CNAND2X2 +XI15 ck_dly WEorREandCS aclk VDD VSS / RSC_IHPSG13_CGATEPX4 +XI14 ck WEandCS DCLK VDD VSS / RSC_IHPSG13_CGATEPX4 +XI60 net7 ROW_CS VDD VSS / RSC_IHPSG13_CBUFX8 +XI73 PULSE_O net012 VDD VSS / RSC_IHPSG13_CINVX2 +XI8 net017 net8 VDD VSS / RSC_IHPSG13_CINVX2 +XCAPS4<7> VDD VSS / RSC_IHPSG13_FILLCAP4 +XCAPS4<6> VDD VSS / RSC_IHPSG13_FILLCAP4 +XCAPS4<5> VDD VSS / RSC_IHPSG13_FILLCAP4 +XCAPS4<4> VDD VSS / RSC_IHPSG13_FILLCAP4 +XCAPS4<3> VDD VSS / RSC_IHPSG13_FILLCAP4 +XCAPS4<2> VDD VSS / RSC_IHPSG13_FILLCAP4 +XCAPS4<1> VDD VSS / RSC_IHPSG13_FILLCAP4 +XBM_TIEL B_TIEL_O VDD VSS / RSC_IHPSG13_TIEL +XI64 ck ck_dly VDD VSS / RSC_IHPSG13_CDLYX2 +XI86 CS_I BIST_CS_I BIST_EN cs VDD VSS / RSC_IHPSG13_MX2X2 +XI87 CK_I BIST_CK_I BIST_EN ck VDD VSS / RSC_IHPSG13_MX2X2 +XI85 WE_I BIST_WE_I BIST_EN we VDD VSS / RSC_IHPSG13_MX2X2 +XI84 RE_I BIST_RE_I BIST_EN re VDD VSS / RSC_IHPSG13_MX2X2 +XI48 ck_dly ck_regs VDD VSS / RSC_IHPSG13_CINVX4 +XI81 net016 WCLK VDD VSS / RSC_IHPSG13_CINVX4 +XI80 net018 RCLK VDD VSS / RSC_IHPSG13_CINVX4 +XI78 net8 net020 VDD VSS / RSC_IHPSG13_CINVX4 +XCAPS8<7> VDD VSS / RSC_IHPSG13_FILLCAP8 +XCAPS8<6> VDD VSS / RSC_IHPSG13_FILLCAP8 +XCAPS8<5> VDD VSS / RSC_IHPSG13_FILLCAP8 +XCAPS8<4> VDD VSS / RSC_IHPSG13_FILLCAP8 +XCAPS8<3> VDD VSS / RSC_IHPSG13_FILLCAP8 +XCAPS8<2> VDD VSS / RSC_IHPSG13_FILLCAP8 +XCAPS8<1> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI6 PULSE_L PULSE_H net017 VDD VSS / RSC_IHPSG13_XOR2X2 +XI22 we cs WEandCS VDD VSS / RSC_IHPSG13_AND2X2 +XI79 net020 ECLK VDD VSS / RSC_IHPSG13_CINVX8 +XI63 aclk ACLK_N VDD VSS / RSC_IHPSG13_CINVX8 +XI21 re we cs WEorREandCS VDD VSS / RSC_IHPSG13_OA12X1 +.ENDS +.SUBCKT RM_IHPSG13_512x8_c2_2P_COLDEC5 ACLK_N ADDR<4> ADDR<3> ADDR<2> ADDR<1> ADDR<0> ++ ADDR_COL<1> ADDR_COL<0> ADDR_DEC<7> ADDR_DEC<6> ADDR_DEC<5> ADDR_DEC<4> ++ ADDR_DEC<3> ADDR_DEC<2> ADDR_DEC<1> ADDR_DEC<0> BIST_ADDR<4> BIST_ADDR<3> ++ BIST_ADDR<2> BIST_ADDR<1> BIST_ADDR<0> BIST_EN_I VDD VSS +XI17<4> VDD VSS / RSC_IHPSG13_FILLCAP4 +XI17<3> VDD VSS / RSC_IHPSG13_FILLCAP4 +XI17<2> VDD VSS / RSC_IHPSG13_FILLCAP4 +XI17<1> VDD VSS / RSC_IHPSG13_FILLCAP4 +XI1<7> PADR<0> PADR<1> PADR<2> addr_n<7> VDD VSS / RSC_IHPSG13_NAND3X2 +XI1<6> NADR<0> PADR<1> PADR<2> addr_n<6> VDD VSS / RSC_IHPSG13_NAND3X2 +XI1<5> PADR<0> NADR<1> PADR<2> addr_n<5> VDD VSS / RSC_IHPSG13_NAND3X2 +XI1<4> NADR<0> NADR<1> PADR<2> addr_n<4> VDD VSS / RSC_IHPSG13_NAND3X2 +XI1<3> PADR<0> PADR<1> NADR<2> addr_n<3> VDD VSS / RSC_IHPSG13_NAND3X2 +XI1<2> NADR<0> PADR<1> NADR<2> addr_n<2> VDD VSS / RSC_IHPSG13_NAND3X2 +XI1<1> PADR<0> NADR<1> NADR<2> addr_n<1> VDD VSS / RSC_IHPSG13_NAND3X2 +XI1<0> NADR<0> NADR<1> NADR<2> addr_n<0> VDD VSS / RSC_IHPSG13_NAND3X2 +XDFF<4> BIST_EN_I BIST_ADDR<4> ACLK_N ADDR<4> addr_int<1> net13<0> VDD ++ VSS / RSC_IHPSG13_DFNQMX2IX1 +XDFF<3> BIST_EN_I BIST_ADDR<3> ACLK_N ADDR<3> addr_int<0> net13<1> VDD ++ VSS / RSC_IHPSG13_DFNQMX2IX1 +XDFF<2> BIST_EN_I BIST_ADDR<2> ACLK_N ADDR<2> padr_int<2> net13<2> VDD ++ VSS / RSC_IHPSG13_DFNQMX2IX1 +XDFF<1> BIST_EN_I BIST_ADDR<1> ACLK_N ADDR<1> padr_int<1> net13<3> VDD ++ VSS / RSC_IHPSG13_DFNQMX2IX1 +XDFF<0> BIST_EN_I BIST_ADDR<0> ACLK_N ADDR<0> padr_int<0> net13<4> VDD ++ VSS / RSC_IHPSG13_DFNQMX2IX1 +XI3<2> padr_int<2> NADR<2> VDD VSS / RSC_IHPSG13_INVX2 +XI3<1> padr_int<1> NADR<1> VDD VSS / RSC_IHPSG13_INVX2 +XI3<0> padr_int<0> NADR<0> VDD VSS / RSC_IHPSG13_INVX2 +XI2<7> addr_n<7> ADDR_DEC<7> VDD VSS / RSC_IHPSG13_INVX2 +XI2<6> addr_n<6> ADDR_DEC<6> VDD VSS / RSC_IHPSG13_INVX2 +XI2<5> addr_n<5> ADDR_DEC<5> VDD VSS / RSC_IHPSG13_INVX2 +XI2<4> addr_n<4> ADDR_DEC<4> VDD VSS / RSC_IHPSG13_INVX2 +XI2<3> addr_n<3> ADDR_DEC<3> VDD VSS / RSC_IHPSG13_INVX2 +XI2<2> addr_n<2> ADDR_DEC<2> VDD VSS / RSC_IHPSG13_INVX2 +XI2<1> addr_n<1> ADDR_DEC<1> VDD VSS / RSC_IHPSG13_INVX2 +XI2<0> addr_n<0> ADDR_DEC<0> VDD VSS / RSC_IHPSG13_INVX2 +XI15<2> NADR<2> PADR<2> VDD VSS / RSC_IHPSG13_INVX2 +XI15<1> NADR<1> PADR<1> VDD VSS / RSC_IHPSG13_INVX2 +XI15<0> NADR<0> PADR<0> VDD VSS / RSC_IHPSG13_INVX2 +XI13<1> addr_int<1> ADDR_COL<1> VDD VSS / RSC_IHPSG13_CBUFX2 +XI13<0> addr_int<0> ADDR_COL<0> VDD VSS / RSC_IHPSG13_CBUFX2 +XI14<5> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI14<4> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI14<3> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI14<2> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI14<1> VDD VSS / RSC_IHPSG13_FILLCAP8 +.ENDS +.SUBCKT RM_IHPSG13_512x8_c2_2P_BLDRV A_BLC<3> A_BLC<2> A_BLC<1> A_BLC<0> A_BLC_SEL ++ A_BLT<3> A_BLT<2> A_BLT<1> A_BLT<0> A_BLT_SEL A_PRE_N A_SEL_P<3> A_SEL_P<2> ++ A_SEL_P<1> A_SEL_P<0> A_WR_ONE A_WR_ZERO B_BLC<3> B_BLC<2> B_BLC<1> B_BLC<0> ++ B_BLC_SEL B_BLT<3> B_BLT<2> B_BLT<1> B_BLT<0> B_BLT_SEL B_PRE_N B_SEL_P<3> ++ B_SEL_P<2> B_SEL_P<1> B_SEL_P<0> B_WR_ONE B_WR_ZERO VDD VSS +MA_CWN<3> A_BLC<3> A_BLC_NMOS_DRIVE<3> VSS VSS sg13_lv_nmos m=1 ++ w=4.82u l=130.00n ng=2 nrd=0 nrs=0 +MA_CWN<2> A_BLC<2> A_BLC_NMOS_DRIVE<2> VSS VSS sg13_lv_nmos m=1 ++ w=4.82u l=130.00n ng=2 nrd=0 nrs=0 +MA_CWN<1> A_BLC<1> A_BLC_NMOS_DRIVE<1> VSS VSS sg13_lv_nmos m=1 ++ w=4.82u l=130.00n ng=2 nrd=0 nrs=0 +MA_CWN<0> A_BLC<0> A_BLC_NMOS_DRIVE<0> VSS VSS sg13_lv_nmos m=1 ++ w=4.82u l=130.00n ng=2 nrd=0 nrs=0 +MA_TWN<3> A_BLT<3> A_BLT_NMOS_DRIVE<3> VSS VSS sg13_lv_nmos m=1 ++ w=4.82u l=130.00n ng=2 nrd=0 nrs=0 +MA_TWN<2> A_BLT<2> A_BLT_NMOS_DRIVE<2> VSS VSS sg13_lv_nmos m=1 ++ w=4.82u l=130.00n ng=2 nrd=0 nrs=0 +MA_TWN<1> A_BLT<1> A_BLT_NMOS_DRIVE<1> VSS VSS sg13_lv_nmos m=1 ++ w=4.82u l=130.00n ng=2 nrd=0 nrs=0 +MA_TWN<0> A_BLT<0> A_BLT_NMOS_DRIVE<0> VSS VSS sg13_lv_nmos m=1 ++ w=4.82u l=130.00n ng=2 nrd=0 nrs=0 +MB_TWN<3> B_BLT<3> B_BLT_NMOS_DRIVE<3> VSS VSS sg13_lv_nmos m=1 ++ w=4.82u l=130.00n ng=2 nrd=0 nrs=0 +MB_TWN<2> B_BLT<2> B_BLT_NMOS_DRIVE<2> VSS VSS sg13_lv_nmos m=1 ++ w=4.82u l=130.00n ng=2 nrd=0 nrs=0 +MB_TWN<1> B_BLT<1> B_BLT_NMOS_DRIVE<1> VSS VSS sg13_lv_nmos m=1 ++ w=4.82u l=130.00n ng=2 nrd=0 nrs=0 +MB_TWN<0> B_BLT<0> B_BLT_NMOS_DRIVE<0> VSS VSS sg13_lv_nmos m=1 ++ w=4.82u l=130.00n ng=2 nrd=0 nrs=0 +MB_CWN<3> B_BLC<3> B_BLC_NMOS_DRIVE<3> VSS VSS sg13_lv_nmos m=1 ++ w=4.82u l=130.00n ng=2 nrd=0 nrs=0 +MB_CWN<2> B_BLC<2> B_BLC_NMOS_DRIVE<2> VSS VSS sg13_lv_nmos m=1 ++ w=4.82u l=130.00n ng=2 nrd=0 nrs=0 +MB_CWN<1> B_BLC<1> B_BLC_NMOS_DRIVE<1> VSS VSS sg13_lv_nmos m=1 ++ w=4.82u l=130.00n ng=2 nrd=0 nrs=0 +MB_CWN<0> B_BLC<0> B_BLC_NMOS_DRIVE<0> VSS VSS sg13_lv_nmos m=1 ++ w=4.82u l=130.00n ng=2 nrd=0 nrs=0 +MA_CPR<3> A_BLC<3> A_PRE_N VDD VDD sg13_lv_pmos m=1 w=3.000u l=130.00n ++ ng=2 nrd=0 nrs=0 +MA_CPR<2> A_BLC<2> A_PRE_N VDD VDD sg13_lv_pmos m=1 w=3.000u l=130.00n ++ ng=2 nrd=0 nrs=0 +MA_CPR<1> A_BLC<1> A_PRE_N VDD VDD sg13_lv_pmos m=1 w=3.000u l=130.00n ++ ng=2 nrd=0 nrs=0 +MA_CPR<0> A_BLC<0> A_PRE_N VDD VDD sg13_lv_pmos m=1 w=3.000u l=130.00n ++ ng=2 nrd=0 nrs=0 +MA_TWP<3> A_BLT<3> A_BLT_PMOS_DRIVE<3> VDD VDD sg13_lv_pmos m=1 w=1.5u ++ l=130.00n ng=1 nrd=0 nrs=0 +MA_TWP<2> A_BLT<2> A_BLT_PMOS_DRIVE<2> VDD VDD sg13_lv_pmos m=1 w=1.5u ++ l=130.00n ng=1 nrd=0 nrs=0 +MA_TWP<1> A_BLT<1> A_BLT_PMOS_DRIVE<1> VDD VDD sg13_lv_pmos m=1 w=1.5u ++ l=130.00n ng=1 nrd=0 nrs=0 +MA_TWP<0> A_BLT<0> A_BLT_PMOS_DRIVE<0> VDD VDD sg13_lv_pmos m=1 w=1.5u ++ l=130.00n ng=1 nrd=0 nrs=0 +MA_CWP<3> A_BLC<3> A_BLC_PMOS_DRIVE<3> VDD VDD sg13_lv_pmos m=1 w=1.5u ++ l=130.00n ng=1 nrd=0 nrs=0 +MA_CWP<2> A_BLC<2> A_BLC_PMOS_DRIVE<2> VDD VDD sg13_lv_pmos m=1 w=1.5u ++ l=130.00n ng=1 nrd=0 nrs=0 +MA_CWP<1> A_BLC<1> A_BLC_PMOS_DRIVE<1> VDD VDD sg13_lv_pmos m=1 w=1.5u ++ l=130.00n ng=1 nrd=0 nrs=0 +MA_CWP<0> A_BLC<0> A_BLC_PMOS_DRIVE<0> VDD VDD sg13_lv_pmos m=1 w=1.5u ++ l=130.00n ng=1 nrd=0 nrs=0 +MA_TPR<3> A_BLT<3> A_PRE_N VDD VDD sg13_lv_pmos m=1 w=3.000u l=130.00n ++ ng=2 nrd=0 nrs=0 +MA_TPR<2> A_BLT<2> A_PRE_N VDD VDD sg13_lv_pmos m=1 w=3.000u l=130.00n ++ ng=2 nrd=0 nrs=0 +MA_TPR<1> A_BLT<1> A_PRE_N VDD VDD sg13_lv_pmos m=1 w=3.000u l=130.00n ++ ng=2 nrd=0 nrs=0 +MA_TPR<0> A_BLT<0> A_PRE_N VDD VDD sg13_lv_pmos m=1 w=3.000u l=130.00n ++ ng=2 nrd=0 nrs=0 +MA_TSP<3> A_BLT_SEL A_SEL_N<3> A_BLT<3> VDD sg13_lv_pmos m=1 w=1.5u ++ l=130.00n ng=1 nrd=0 nrs=0 +MA_TSP<2> A_BLT_SEL A_SEL_N<2> A_BLT<2> VDD sg13_lv_pmos m=1 w=1.5u ++ l=130.00n ng=1 nrd=0 nrs=0 +MA_TSP<1> A_BLT_SEL A_SEL_N<1> A_BLT<1> VDD sg13_lv_pmos m=1 w=1.5u ++ l=130.00n ng=1 nrd=0 nrs=0 +MA_TSP<0> A_BLT_SEL A_SEL_N<0> A_BLT<0> VDD sg13_lv_pmos m=1 w=1.5u ++ l=130.00n ng=1 nrd=0 nrs=0 +MA_CSP<3> A_BLC_SEL A_SEL_N<3> A_BLC<3> VDD sg13_lv_pmos m=1 w=1.5u ++ l=130.00n ng=1 nrd=0 nrs=0 +MA_CSP<2> A_BLC_SEL A_SEL_N<2> A_BLC<2> VDD sg13_lv_pmos m=1 w=1.5u ++ l=130.00n ng=1 nrd=0 nrs=0 +MA_CSP<1> A_BLC_SEL A_SEL_N<1> A_BLC<1> VDD sg13_lv_pmos m=1 w=1.5u ++ l=130.00n ng=1 nrd=0 nrs=0 +MA_CSP<0> A_BLC_SEL A_SEL_N<0> A_BLC<0> VDD sg13_lv_pmos m=1 w=1.5u ++ l=130.00n ng=1 nrd=0 nrs=0 +MB_CWP<3> B_BLC<3> B_BLC_PMOS_DRIVE<3> VDD VDD sg13_lv_pmos m=1 w=1.5u ++ l=130.00n ng=1 nrd=0 nrs=0 +MB_CWP<2> B_BLC<2> B_BLC_PMOS_DRIVE<2> VDD VDD sg13_lv_pmos m=1 w=1.5u ++ l=130.00n ng=1 nrd=0 nrs=0 +MB_CWP<1> B_BLC<1> B_BLC_PMOS_DRIVE<1> VDD VDD sg13_lv_pmos m=1 w=1.5u ++ l=130.00n ng=1 nrd=0 nrs=0 +MB_CWP<0> B_BLC<0> B_BLC_PMOS_DRIVE<0> VDD VDD sg13_lv_pmos m=1 w=1.5u ++ l=130.00n ng=1 nrd=0 nrs=0 +MB_TWP<3> B_BLT<3> B_BLT_PMOS_DRIVE<3> VDD VDD sg13_lv_pmos m=1 w=1.5u ++ l=130.00n ng=1 nrd=0 nrs=0 +MB_TWP<2> B_BLT<2> B_BLT_PMOS_DRIVE<2> VDD VDD sg13_lv_pmos m=1 w=1.5u ++ l=130.00n ng=1 nrd=0 nrs=0 +MB_TWP<1> B_BLT<1> B_BLT_PMOS_DRIVE<1> VDD VDD sg13_lv_pmos m=1 w=1.5u ++ l=130.00n ng=1 nrd=0 nrs=0 +MB_TWP<0> B_BLT<0> B_BLT_PMOS_DRIVE<0> VDD VDD sg13_lv_pmos m=1 w=1.5u ++ l=130.00n ng=1 nrd=0 nrs=0 +MB_TSP<3> B_BLT_SEL B_SEL_N<3> B_BLT<3> VDD sg13_lv_pmos m=1 w=1.5u ++ l=130.00n ng=1 nrd=0 nrs=0 +MB_TSP<2> B_BLT_SEL B_SEL_N<2> B_BLT<2> VDD sg13_lv_pmos m=1 w=1.5u ++ l=130.00n ng=1 nrd=0 nrs=0 +MB_TSP<1> B_BLT_SEL B_SEL_N<1> B_BLT<1> VDD sg13_lv_pmos m=1 w=1.5u ++ l=130.00n ng=1 nrd=0 nrs=0 +MB_TSP<0> B_BLT_SEL B_SEL_N<0> B_BLT<0> VDD sg13_lv_pmos m=1 w=1.5u ++ l=130.00n ng=1 nrd=0 nrs=0 +MB_TPR<3> B_BLT<3> B_PRE_N VDD VDD sg13_lv_pmos m=1 w=3.000u l=130.00n ++ ng=2 nrd=0 nrs=0 +MB_TPR<2> B_BLT<2> B_PRE_N VDD VDD sg13_lv_pmos m=1 w=3.000u l=130.00n ++ ng=2 nrd=0 nrs=0 +MB_TPR<1> B_BLT<1> B_PRE_N VDD VDD sg13_lv_pmos m=1 w=3.000u l=130.00n ++ ng=2 nrd=0 nrs=0 +MB_TPR<0> B_BLT<0> B_PRE_N VDD VDD sg13_lv_pmos m=1 w=3.000u l=130.00n ++ ng=2 nrd=0 nrs=0 +MB_CSP<3> B_BLC_SEL B_SEL_N<3> B_BLC<3> VDD sg13_lv_pmos m=1 w=1.5u ++ l=130.00n ng=1 nrd=0 nrs=0 +MB_CSP<2> B_BLC_SEL B_SEL_N<2> B_BLC<2> VDD sg13_lv_pmos m=1 w=1.5u ++ l=130.00n ng=1 nrd=0 nrs=0 +MB_CSP<1> B_BLC_SEL B_SEL_N<1> B_BLC<1> VDD sg13_lv_pmos m=1 w=1.5u ++ l=130.00n ng=1 nrd=0 nrs=0 +MB_CSP<0> B_BLC_SEL B_SEL_N<0> B_BLC<0> VDD sg13_lv_pmos m=1 w=1.5u ++ l=130.00n ng=1 nrd=0 nrs=0 +MB_CPR<3> B_BLC<3> B_PRE_N VDD VDD sg13_lv_pmos m=1 w=3.000u l=130.00n ++ ng=2 nrd=0 nrs=0 +MB_CPR<2> B_BLC<2> B_PRE_N VDD VDD sg13_lv_pmos m=1 w=3.000u l=130.00n ++ ng=2 nrd=0 nrs=0 +MB_CPR<1> B_BLC<1> B_PRE_N VDD VDD sg13_lv_pmos m=1 w=3.000u l=130.00n ++ ng=2 nrd=0 nrs=0 +MB_CPR<0> B_BLC<0> B_PRE_N VDD VDD sg13_lv_pmos m=1 w=3.000u l=130.00n ++ ng=2 nrd=0 nrs=0 +XA_SEL<3> A_SEL_P<3> A_SEL_N<3> VDD VSS / RSC_IHPSG13_INVX2 +XA_SEL<2> A_SEL_P<2> A_SEL_N<2> VDD VSS / RSC_IHPSG13_INVX2 +XA_SEL<1> A_SEL_P<1> A_SEL_N<1> VDD VSS / RSC_IHPSG13_INVX2 +XA_SEL<0> A_SEL_P<0> A_SEL_N<0> VDD VSS / RSC_IHPSG13_INVX2 +XA_CINV<3> A_BLT_PMOS_DRIVE<3> A_BLC_NMOS_DRIVE<3> VDD VSS / ++ RSC_IHPSG13_INVX2 +XA_CINV<2> A_BLT_PMOS_DRIVE<2> A_BLC_NMOS_DRIVE<2> VDD VSS / ++ RSC_IHPSG13_INVX2 +XA_CINV<1> A_BLT_PMOS_DRIVE<1> A_BLC_NMOS_DRIVE<1> VDD VSS / ++ RSC_IHPSG13_INVX2 +XA_CINV<0> A_BLT_PMOS_DRIVE<0> A_BLC_NMOS_DRIVE<0> VDD VSS / ++ RSC_IHPSG13_INVX2 +XA_TINV<3> A_BLC_PMOS_DRIVE<3> A_BLT_NMOS_DRIVE<3> VDD VSS / ++ RSC_IHPSG13_INVX2 +XA_TINV<2> A_BLC_PMOS_DRIVE<2> A_BLT_NMOS_DRIVE<2> VDD VSS / ++ RSC_IHPSG13_INVX2 +XA_TINV<1> A_BLC_PMOS_DRIVE<1> A_BLT_NMOS_DRIVE<1> VDD VSS / ++ RSC_IHPSG13_INVX2 +XA_TINV<0> A_BLC_PMOS_DRIVE<0> A_BLT_NMOS_DRIVE<0> VDD VSS / ++ RSC_IHPSG13_INVX2 +XB_SEL<3> B_SEL_P<3> B_SEL_N<3> VDD VSS / RSC_IHPSG13_INVX2 +XB_SEL<2> B_SEL_P<2> B_SEL_N<2> VDD VSS / RSC_IHPSG13_INVX2 +XB_SEL<1> B_SEL_P<1> B_SEL_N<1> VDD VSS / RSC_IHPSG13_INVX2 +XB_SEL<0> B_SEL_P<0> B_SEL_N<0> VDD VSS / RSC_IHPSG13_INVX2 +XB_TINV<3> B_BLC_PMOS_DRIVE<3> B_BLT_NMOS_DRIVE<3> VDD VSS / ++ RSC_IHPSG13_INVX2 +XB_TINV<2> B_BLC_PMOS_DRIVE<2> B_BLT_NMOS_DRIVE<2> VDD VSS / ++ RSC_IHPSG13_INVX2 +XB_TINV<1> B_BLC_PMOS_DRIVE<1> B_BLT_NMOS_DRIVE<1> VDD VSS / ++ RSC_IHPSG13_INVX2 +XB_TINV<0> B_BLC_PMOS_DRIVE<0> B_BLT_NMOS_DRIVE<0> VDD VSS / ++ RSC_IHPSG13_INVX2 +XB_CINV<3> B_BLT_PMOS_DRIVE<3> B_BLC_NMOS_DRIVE<3> VDD VSS / ++ RSC_IHPSG13_INVX2 +XB_CINV<2> B_BLT_PMOS_DRIVE<2> B_BLC_NMOS_DRIVE<2> VDD VSS / ++ RSC_IHPSG13_INVX2 +XB_CINV<1> B_BLT_PMOS_DRIVE<1> B_BLC_NMOS_DRIVE<1> VDD VSS / ++ RSC_IHPSG13_INVX2 +XB_CINV<0> B_BLT_PMOS_DRIVE<0> B_BLC_NMOS_DRIVE<0> VDD VSS / ++ RSC_IHPSG13_INVX2 +XA_TDEC<3> A_SEL_P<3> A_WR_ONE A_BLT_PMOS_DRIVE<3> VDD VSS / ++ RSC_IHPSG13_NAND2X2 +XA_TDEC<2> A_SEL_P<2> A_WR_ONE A_BLT_PMOS_DRIVE<2> VDD VSS / ++ RSC_IHPSG13_NAND2X2 +XA_TDEC<1> A_SEL_P<1> A_WR_ONE A_BLT_PMOS_DRIVE<1> VDD VSS / ++ RSC_IHPSG13_NAND2X2 +XA_TDEC<0> A_SEL_P<0> A_WR_ONE A_BLT_PMOS_DRIVE<0> VDD VSS / ++ RSC_IHPSG13_NAND2X2 +XA_CDEC<3> A_SEL_P<3> A_WR_ZERO A_BLC_PMOS_DRIVE<3> VDD VSS / ++ RSC_IHPSG13_NAND2X2 +XA_CDEC<2> A_SEL_P<2> A_WR_ZERO A_BLC_PMOS_DRIVE<2> VDD VSS / ++ RSC_IHPSG13_NAND2X2 +XA_CDEC<1> A_SEL_P<1> A_WR_ZERO A_BLC_PMOS_DRIVE<1> VDD VSS / ++ RSC_IHPSG13_NAND2X2 +XA_CDEC<0> A_SEL_P<0> A_WR_ZERO A_BLC_PMOS_DRIVE<0> VDD VSS / ++ RSC_IHPSG13_NAND2X2 +XB_CDEC<3> B_SEL_P<3> B_WR_ZERO B_BLC_PMOS_DRIVE<3> VDD VSS / ++ RSC_IHPSG13_NAND2X2 +XB_CDEC<2> B_SEL_P<2> B_WR_ZERO B_BLC_PMOS_DRIVE<2> VDD VSS / ++ RSC_IHPSG13_NAND2X2 +XB_CDEC<1> B_SEL_P<1> B_WR_ZERO B_BLC_PMOS_DRIVE<1> VDD VSS / ++ RSC_IHPSG13_NAND2X2 +XB_CDEC<0> B_SEL_P<0> B_WR_ZERO B_BLC_PMOS_DRIVE<0> VDD VSS / ++ RSC_IHPSG13_NAND2X2 +XB_TDEC<3> B_SEL_P<3> B_WR_ONE B_BLT_PMOS_DRIVE<3> VDD VSS / ++ RSC_IHPSG13_NAND2X2 +XB_TDEC<2> B_SEL_P<2> B_WR_ONE B_BLT_PMOS_DRIVE<2> VDD VSS / ++ RSC_IHPSG13_NAND2X2 +XB_TDEC<1> B_SEL_P<1> B_WR_ONE B_BLT_PMOS_DRIVE<1> VDD VSS / ++ RSC_IHPSG13_NAND2X2 +XB_TDEC<0> B_SEL_P<0> B_WR_ONE B_BLT_PMOS_DRIVE<0> VDD VSS / ++ RSC_IHPSG13_NAND2X2 +.ENDS +.SUBCKT RSC_IHPSG13_AND2X6 A B Z VDD VSS +MN3 Z net6 VSS VSS sg13_lv_nmos m=1 w=2.94u l=130.00n ng=3 nrd=0 nrs=0 +MN4 net9 B VSS VSS sg13_lv_nmos m=1 w=500.0n l=130.00n ng=1 nrd=0 nrs=0 +MN6 net6 A net9 VSS sg13_lv_nmos m=1 w=500.0n l=130.00n ng=1 nrd=0 nrs=0 +MP2 Z net6 VDD VDD sg13_lv_pmos m=1 w=4.86u l=130.00n ng=3 nrd=0 nrs=0 +MP0 net6 B VDD VDD sg13_lv_pmos m=1 w=860.00n l=130.00n ng=1 nrd=0 ++ nrs=0 +MP1 net6 A VDD VDD sg13_lv_pmos m=1 w=860.00n l=130.00n ng=1 nrd=0 ++ nrs=0 +.ENDS +.SUBCKT RM_IHPSG13_512x8_c2_2P_COLCTRL5 A_ADDR_COL<1> A_ADDR_COL<0> A_ADDR_DEC<7> ++ A_ADDR_DEC<6> A_ADDR_DEC<5> A_ADDR_DEC<4> A_ADDR_DEC<3> A_ADDR_DEC<2> ++ A_ADDR_DEC<1> A_ADDR_DEC<0> A_BIST_BM_I A_BIST_DW_I A_BIST_EN_I A_BLC<31> ++ A_BLC<30> A_BLC<29> A_BLC<28> A_BLC<27> A_BLC<26> A_BLC<25> A_BLC<24> ++ A_BLC<23> A_BLC<22> A_BLC<21> A_BLC<20> A_BLC<19> A_BLC<18> A_BLC<17> ++ A_BLC<16> A_BLC<15> A_BLC<14> A_BLC<13> A_BLC<12> A_BLC<11> A_BLC<10> ++ A_BLC<9> A_BLC<8> A_BLC<7> A_BLC<6> A_BLC<5> A_BLC<4> A_BLC<3> A_BLC<2> ++ A_BLC<1> A_BLC<0> A_BLT<31> A_BLT<30> A_BLT<29> A_BLT<28> A_BLT<27> ++ A_BLT<26> A_BLT<25> A_BLT<24> A_BLT<23> A_BLT<22> A_BLT<21> A_BLT<20> ++ A_BLT<19> A_BLT<18> A_BLT<17> A_BLT<16> A_BLT<15> A_BLT<14> A_BLT<13> ++ A_BLT<12> A_BLT<11> A_BLT<10> A_BLT<9> A_BLT<8> A_BLT<7> A_BLT<6> A_BLT<5> ++ A_BLT<4> A_BLT<3> A_BLT<2> A_BLT<1> A_BLT<0> A_BM_I A_DCLK_B_L A_DCLK_B_R ++ A_DCLK_L A_DCLK_R A_DR_O A_DW_I A_RCLK_B_L A_RCLK_B_R A_RCLK_L A_RCLK_R ++ A_TIEH_O A_WCLK_B_L A_WCLK_B_R A_WCLK_L A_WCLK_R B_ADDR_COL<1> B_ADDR_COL<0> ++ B_ADDR_DEC<7> B_ADDR_DEC<6> B_ADDR_DEC<5> B_ADDR_DEC<4> B_ADDR_DEC<3> ++ B_ADDR_DEC<2> B_ADDR_DEC<1> B_ADDR_DEC<0> B_BIST_BM_I B_BIST_DW_I ++ B_BIST_EN_I B_BLC<31> B_BLC<30> B_BLC<29> B_BLC<28> B_BLC<27> B_BLC<26> ++ B_BLC<25> B_BLC<24> B_BLC<23> B_BLC<22> B_BLC<21> B_BLC<20> B_BLC<19> ++ B_BLC<18> B_BLC<17> B_BLC<16> B_BLC<15> B_BLC<14> B_BLC<13> B_BLC<12> ++ B_BLC<11> B_BLC<10> B_BLC<9> B_BLC<8> B_BLC<7> B_BLC<6> B_BLC<5> B_BLC<4> ++ B_BLC<3> B_BLC<2> B_BLC<1> B_BLC<0> B_BLT<31> B_BLT<30> B_BLT<29> B_BLT<28> ++ B_BLT<27> B_BLT<26> B_BLT<25> B_BLT<24> B_BLT<23> B_BLT<22> B_BLT<21> ++ B_BLT<20> B_BLT<19> B_BLT<18> B_BLT<17> B_BLT<16> B_BLT<15> B_BLT<14> ++ B_BLT<13> B_BLT<12> B_BLT<11> B_BLT<10> B_BLT<9> B_BLT<8> B_BLT<7> B_BLT<6> ++ B_BLT<5> B_BLT<4> B_BLT<3> B_BLT<2> B_BLT<1> B_BLT<0> B_BM_I B_DCLK_B_L ++ B_DCLK_B_R B_DCLK_L B_DCLK_R B_DR_O B_DW_I B_RCLK_B_L B_RCLK_B_R B_RCLK_L ++ B_RCLK_R B_TIEH_O B_WCLK_B_L B_WCLK_B_R B_WCLK_L B_WCLK_R VDD VSS +XB_I80<1> B_WCLK_B_L B_RCLK_B_L B_W_nor_R<1> VDD VSS / ++ RSC_IHPSG13_AND2X2 +XB_I80<0> B_WCLK_B_L B_RCLK_B_L B_W_nor_R<0> VDD VSS / ++ RSC_IHPSG13_AND2X2 +XA_I80<1> A_WCLK_B_L A_RCLK_B_L A_W_nor_R<1> VDD VSS / ++ RSC_IHPSG13_AND2X2 +XA_I80<0> A_WCLK_B_L A_RCLK_B_L A_W_nor_R<0> VDD VSS / ++ RSC_IHPSG13_AND2X2 +XB_I44 B_BM_N B_WCLK_B_L B_DO_WRITE_P VDD VSS / RSC_IHPSG13_NOR2X2 +XA_I44 A_BM_N A_WCLK_B_L A_DO_WRITE_P VDD VSS / RSC_IHPSG13_NOR2X2 +XI_FILL4<16> VDD VSS / RSC_IHPSG13_FILLCAP4 +XI_FILL4<15> VDD VSS / RSC_IHPSG13_FILLCAP4 +XI_FILL4<14> VDD VSS / RSC_IHPSG13_FILLCAP4 +XI_FILL4<13> VDD VSS / RSC_IHPSG13_FILLCAP4 +XI_FILL4<12> VDD VSS / RSC_IHPSG13_FILLCAP4 +XI_FILL4<11> VDD VSS / RSC_IHPSG13_FILLCAP4 +XI_FILL4<10> VDD VSS / RSC_IHPSG13_FILLCAP4 +XI_FILL4<9> VDD VSS / RSC_IHPSG13_FILLCAP4 +XI_FILL4<8> VDD VSS / RSC_IHPSG13_FILLCAP4 +XI_FILL4<7> VDD VSS / RSC_IHPSG13_FILLCAP4 +XI_FILL4<6> VDD VSS / RSC_IHPSG13_FILLCAP4 +XI_FILL4<5> VDD VSS / RSC_IHPSG13_FILLCAP4 +XI_FILL4<4> VDD VSS / RSC_IHPSG13_FILLCAP4 +XI_FILL4<3> VDD VSS / RSC_IHPSG13_FILLCAP4 +XI_FILL4<2> VDD VSS / RSC_IHPSG13_FILLCAP4 +XI_FILL4<1> VDD VSS / RSC_IHPSG13_FILLCAP4 +XB_INV<6> B_N1<1> B_P1<1> VDD VSS / RSC_IHPSG13_CINVX4 +XB_INV<5> B_N0<1> B_P0<1> VDD VSS / RSC_IHPSG13_CINVX4 +XB_INV<4> B_N0<0> B_P0<0> VDD VSS / RSC_IHPSG13_CINVX4 +XB_INV<3> B_ADDR_COL<1> B_N1<1> VDD VSS / RSC_IHPSG13_CINVX4 +XB_INV<2> B_ADDR_COL<1> B_N1<0> VDD VSS / RSC_IHPSG13_CINVX4 +XB_INV<1> B_ADDR_COL<0> B_N0<1> VDD VSS / RSC_IHPSG13_CINVX4 +XB_INV<0> B_ADDR_COL<0> B_N0<0> VDD VSS / RSC_IHPSG13_CINVX4 +XA_INV<6> A_N1<1> A_P1<1> VDD VSS / RSC_IHPSG13_CINVX4 +XA_INV<5> A_N0<1> A_P0<1> VDD VSS / RSC_IHPSG13_CINVX4 +XA_INV<4> A_N0<0> A_P0<0> VDD VSS / RSC_IHPSG13_CINVX4 +XA_INV<3> A_ADDR_COL<1> A_N1<1> VDD VSS / RSC_IHPSG13_CINVX4 +XA_INV<2> A_ADDR_COL<1> A_N1<0> VDD VSS / RSC_IHPSG13_CINVX4 +XA_INV<1> A_ADDR_COL<0> A_N0<1> VDD VSS / RSC_IHPSG13_CINVX4 +XA_INV<0> A_ADDR_COL<0> A_N0<0> VDD VSS / RSC_IHPSG13_CINVX4 +XB_I81<3> B_W_nor_R<1> B_PRE_N VDD VSS / RSC_IHPSG13_CINVX4_WN +XB_I81<2> B_W_nor_R<1> B_PRE_N VDD VSS / RSC_IHPSG13_CINVX4_WN +XB_I81<1> B_W_nor_R<0> B_PRE_N VDD VSS / RSC_IHPSG13_CINVX4_WN +XB_I81<0> B_W_nor_R<0> B_PRE_N VDD VSS / RSC_IHPSG13_CINVX4_WN +XA_I81<3> A_W_nor_R<1> A_PRE_N VDD VSS / RSC_IHPSG13_CINVX4_WN +XA_I81<2> A_W_nor_R<1> A_PRE_N VDD VSS / RSC_IHPSG13_CINVX4_WN +XA_I81<1> A_W_nor_R<0> A_PRE_N VDD VSS / RSC_IHPSG13_CINVX4_WN +XA_I81<0> A_W_nor_R<0> A_PRE_N VDD VSS / RSC_IHPSG13_CINVX4_WN +XI_FILL8<78> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI_FILL8<77> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI_FILL8<76> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI_FILL8<75> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI_FILL8<74> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI_FILL8<73> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI_FILL8<72> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI_FILL8<71> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI_FILL8<70> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI_FILL8<69> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI_FILL8<68> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI_FILL8<67> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI_FILL8<66> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI_FILL8<65> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI_FILL8<64> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI_FILL8<63> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI_FILL8<62> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI_FILL8<61> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI_FILL8<60> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI_FILL8<59> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI_FILL8<58> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI_FILL8<57> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI_FILL8<56> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI_FILL8<55> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI_FILL8<54> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI_FILL8<53> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI_FILL8<52> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI_FILL8<51> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI_FILL8<50> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI_FILL8<49> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI_FILL8<48> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI_FILL8<47> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI_FILL8<46> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI_FILL8<45> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI_FILL8<44> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI_FILL8<43> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI_FILL8<42> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI_FILL8<41> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI_FILL8<40> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI_FILL8<39> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI_FILL8<38> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI_FILL8<37> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI_FILL8<36> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI_FILL8<35> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI_FILL8<34> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI_FILL8<33> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI_FILL8<32> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI_FILL8<31> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI_FILL8<30> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI_FILL8<29> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI_FILL8<28> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI_FILL8<27> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI_FILL8<26> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI_FILL8<25> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI_FILL8<24> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI_FILL8<23> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI_FILL8<22> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI_FILL8<21> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI_FILL8<20> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI_FILL8<19> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI_FILL8<18> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI_FILL8<17> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI_FILL8<16> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI_FILL8<15> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI_FILL8<14> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI_FILL8<13> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI_FILL8<12> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI_FILL8<11> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI_FILL8<10> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI_FILL8<9> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI_FILL8<8> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI_FILL8<7> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI_FILL8<6> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI_FILL8<5> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI_FILL8<4> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI_FILL8<3> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI_FILL8<2> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI_FILL8<1> VDD VSS / RSC_IHPSG13_FILLCAP8 +XAB_BLMUX<7> A_BLC<31> A_BLC<30> A_BLC<29> A_BLC<28> A_BLC_SEL A_BLT<31> ++ A_BLT<30> A_BLT<29> A_BLT<28> A_BLT_SEL A_PRE_N A_SEL_P<31> A_SEL_P<30> ++ A_SEL_P<29> A_SEL_P<28> A_WR_ONE A_WR_ZERO B_BLC<31> B_BLC<30> B_BLC<29> ++ B_BLC<28> B_BLC_SEL B_BLT<31> B_BLT<30> B_BLT<29> B_BLT<28> B_BLT_SEL ++ B_PRE_N B_SEL_P<31> B_SEL_P<30> B_SEL_P<29> B_SEL_P<28> B_WR_ONE B_WR_ZERO ++ VDD VSS / RM_IHPSG13_512x8_c2_2P_BLDRV +XAB_BLMUX<6> A_BLC<27> A_BLC<26> A_BLC<25> A_BLC<24> A_BLC_SEL A_BLT<27> ++ A_BLT<26> A_BLT<25> A_BLT<24> A_BLT_SEL A_PRE_N A_SEL_P<27> A_SEL_P<26> ++ A_SEL_P<25> A_SEL_P<24> A_WR_ONE A_WR_ZERO B_BLC<27> B_BLC<26> B_BLC<25> ++ B_BLC<24> B_BLC_SEL B_BLT<27> B_BLT<26> B_BLT<25> B_BLT<24> B_BLT_SEL ++ B_PRE_N B_SEL_P<27> B_SEL_P<26> B_SEL_P<25> B_SEL_P<24> B_WR_ONE B_WR_ZERO ++ VDD VSS / RM_IHPSG13_512x8_c2_2P_BLDRV +XAB_BLMUX<5> A_BLC<23> A_BLC<22> A_BLC<21> A_BLC<20> A_BLC_SEL A_BLT<23> ++ A_BLT<22> A_BLT<21> A_BLT<20> A_BLT_SEL A_PRE_N A_SEL_P<23> A_SEL_P<22> ++ A_SEL_P<21> A_SEL_P<20> A_WR_ONE A_WR_ZERO B_BLC<23> B_BLC<22> B_BLC<21> ++ B_BLC<20> B_BLC_SEL B_BLT<23> B_BLT<22> B_BLT<21> B_BLT<20> B_BLT_SEL ++ B_PRE_N B_SEL_P<23> B_SEL_P<22> B_SEL_P<21> B_SEL_P<20> B_WR_ONE B_WR_ZERO ++ VDD VSS / RM_IHPSG13_512x8_c2_2P_BLDRV +XAB_BLMUX<4> A_BLC<19> A_BLC<18> A_BLC<17> A_BLC<16> A_BLC_SEL A_BLT<19> ++ A_BLT<18> A_BLT<17> A_BLT<16> A_BLT_SEL A_PRE_N A_SEL_P<19> A_SEL_P<18> ++ A_SEL_P<17> A_SEL_P<16> A_WR_ONE A_WR_ZERO B_BLC<19> B_BLC<18> B_BLC<17> ++ B_BLC<16> B_BLC_SEL B_BLT<19> B_BLT<18> B_BLT<17> B_BLT<16> B_BLT_SEL ++ B_PRE_N B_SEL_P<19> B_SEL_P<18> B_SEL_P<17> B_SEL_P<16> B_WR_ONE B_WR_ZERO ++ VDD VSS / RM_IHPSG13_512x8_c2_2P_BLDRV +XAB_BLMUX<3> A_BLC<15> A_BLC<14> A_BLC<13> A_BLC<12> A_BLC_SEL A_BLT<15> ++ A_BLT<14> A_BLT<13> A_BLT<12> A_BLT_SEL A_PRE_N A_SEL_P<15> A_SEL_P<14> ++ A_SEL_P<13> A_SEL_P<12> A_WR_ONE A_WR_ZERO B_BLC<15> B_BLC<14> B_BLC<13> ++ B_BLC<12> B_BLC_SEL B_BLT<15> B_BLT<14> B_BLT<13> B_BLT<12> B_BLT_SEL ++ B_PRE_N B_SEL_P<15> B_SEL_P<14> B_SEL_P<13> B_SEL_P<12> B_WR_ONE B_WR_ZERO ++ VDD VSS / RM_IHPSG13_512x8_c2_2P_BLDRV +XAB_BLMUX<2> A_BLC<11> A_BLC<10> A_BLC<9> A_BLC<8> A_BLC_SEL A_BLT<11> ++ A_BLT<10> A_BLT<9> A_BLT<8> A_BLT_SEL A_PRE_N A_SEL_P<11> A_SEL_P<10> ++ A_SEL_P<9> A_SEL_P<8> A_WR_ONE A_WR_ZERO B_BLC<11> B_BLC<10> B_BLC<9> ++ B_BLC<8> B_BLC_SEL B_BLT<11> B_BLT<10> B_BLT<9> B_BLT<8> B_BLT_SEL B_PRE_N ++ B_SEL_P<11> B_SEL_P<10> B_SEL_P<9> B_SEL_P<8> B_WR_ONE B_WR_ZERO VDD ++ VSS / RM_IHPSG13_512x8_c2_2P_BLDRV +XAB_BLMUX<1> A_BLC<7> A_BLC<6> A_BLC<5> A_BLC<4> A_BLC_SEL A_BLT<7> A_BLT<6> ++ A_BLT<5> A_BLT<4> A_BLT_SEL A_PRE_N A_SEL_P<7> A_SEL_P<6> A_SEL_P<5> ++ A_SEL_P<4> A_WR_ONE A_WR_ZERO B_BLC<7> B_BLC<6> B_BLC<5> B_BLC<4> B_BLC_SEL ++ B_BLT<7> B_BLT<6> B_BLT<5> B_BLT<4> B_BLT_SEL B_PRE_N B_SEL_P<7> B_SEL_P<6> ++ B_SEL_P<5> B_SEL_P<4> B_WR_ONE B_WR_ZERO VDD VSS / ++ RM_IHPSG13_512x8_c2_2P_BLDRV +XAB_BLMUX<0> A_BLC<3> A_BLC<2> A_BLC<1> A_BLC<0> A_BLC_SEL A_BLT<3> A_BLT<2> ++ A_BLT<1> A_BLT<0> A_BLT_SEL A_PRE_N A_SEL_P<3> A_SEL_P<2> A_SEL_P<1> ++ A_SEL_P<0> A_WR_ONE A_WR_ZERO B_BLC<3> B_BLC<2> B_BLC<1> B_BLC<0> B_BLC_SEL ++ B_BLT<3> B_BLT<2> B_BLT<1> B_BLT<0> B_BLT_SEL B_PRE_N B_SEL_P<3> B_SEL_P<2> ++ B_SEL_P<1> B_SEL_P<0> B_WR_ONE B_WR_ZERO VDD VSS / ++ RM_IHPSG13_512x8_c2_2P_BLDRV +XB_I51 net037 B_DR_O VDD VSS / RSC_IHPSG13_INVX4 +XA_I51 net19 A_DR_O VDD VSS / RSC_IHPSG13_INVX4 +XB_I78 B_RCLK_B_L B_SAE VDD VSS / RSC_IHPSG13_CBUFX2 +XA_I78 A_RCLK_B_L A_SAE VDD VSS / RSC_IHPSG13_CBUFX2 +XB_I69 B_DCLK_L B_DCLK_B_L VDD VSS / RSC_IHPSG13_CINVX8 +XB_I50 B_WCLK_L B_WCLK_B_L VDD VSS / RSC_IHPSG13_CINVX8 +XB_EBUF B_RCLK_L B_RCLK_B_L VDD VSS / RSC_IHPSG13_CINVX8 +XA_I69 A_DCLK_L A_DCLK_B_L VDD VSS / RSC_IHPSG13_CINVX8 +XA_I50 A_WCLK_L A_WCLK_B_L VDD VSS / RSC_IHPSG13_CINVX8 +XA_EBUF A_RCLK_L A_RCLK_B_L VDD VSS / RSC_IHPSG13_CINVX8 +XB_I76 B_DI_N B_DO_WRITE_P B_WR_ZERO VDD VSS / RSC_IHPSG13_AND2X6 +XB_I75 B_DI_R B_DO_WRITE_P B_WR_ONE VDD VSS / RSC_IHPSG13_AND2X6 +XA_I76 A_DI_N A_DO_WRITE_P A_WR_ZERO VDD VSS / RSC_IHPSG13_AND2X6 +XA_I75 A_DI_R A_DO_WRITE_P A_WR_ONE VDD VSS / RSC_IHPSG13_AND2X6 +XB_I83 B_BM_R B_BM_N VDD VSS / RSC_IHPSG13_INVX2 +XB_DEC3INV<31> net041<0> B_SEL_P<31> VDD VSS / RSC_IHPSG13_INVX2 +XB_DEC3INV<30> net041<1> B_SEL_P<30> VDD VSS / RSC_IHPSG13_INVX2 +XB_DEC3INV<29> net041<2> B_SEL_P<29> VDD VSS / RSC_IHPSG13_INVX2 +XB_DEC3INV<28> net041<3> B_SEL_P<28> VDD VSS / RSC_IHPSG13_INVX2 +XB_DEC3INV<27> net041<4> B_SEL_P<27> VDD VSS / RSC_IHPSG13_INVX2 +XB_DEC3INV<26> net041<5> B_SEL_P<26> VDD VSS / RSC_IHPSG13_INVX2 +XB_DEC3INV<25> net041<6> B_SEL_P<25> VDD VSS / RSC_IHPSG13_INVX2 +XB_DEC3INV<24> net041<7> B_SEL_P<24> VDD VSS / RSC_IHPSG13_INVX2 +XB_DEC3INV<23> net041<8> B_SEL_P<23> VDD VSS / RSC_IHPSG13_INVX2 +XB_DEC3INV<22> net041<9> B_SEL_P<22> VDD VSS / RSC_IHPSG13_INVX2 +XB_DEC3INV<21> net041<10> B_SEL_P<21> VDD VSS / RSC_IHPSG13_INVX2 +XB_DEC3INV<20> net041<11> B_SEL_P<20> VDD VSS / RSC_IHPSG13_INVX2 +XB_DEC3INV<19> net041<12> B_SEL_P<19> VDD VSS / RSC_IHPSG13_INVX2 +XB_DEC3INV<18> net041<13> B_SEL_P<18> VDD VSS / RSC_IHPSG13_INVX2 +XB_DEC3INV<17> net041<14> B_SEL_P<17> VDD VSS / RSC_IHPSG13_INVX2 +XB_DEC3INV<16> net041<15> B_SEL_P<16> VDD VSS / RSC_IHPSG13_INVX2 +XB_DEC3INV<15> net041<16> B_SEL_P<15> VDD VSS / RSC_IHPSG13_INVX2 +XB_DEC3INV<14> net041<17> B_SEL_P<14> VDD VSS / RSC_IHPSG13_INVX2 +XB_DEC3INV<13> net041<18> B_SEL_P<13> VDD VSS / RSC_IHPSG13_INVX2 +XB_DEC3INV<12> net041<19> B_SEL_P<12> VDD VSS / RSC_IHPSG13_INVX2 +XB_DEC3INV<11> net041<20> B_SEL_P<11> VDD VSS / RSC_IHPSG13_INVX2 +XB_DEC3INV<10> net041<21> B_SEL_P<10> VDD VSS / RSC_IHPSG13_INVX2 +XB_DEC3INV<9> net041<22> B_SEL_P<9> VDD VSS / RSC_IHPSG13_INVX2 +XB_DEC3INV<8> net041<23> B_SEL_P<8> VDD VSS / RSC_IHPSG13_INVX2 +XB_DEC3INV<7> net041<24> B_SEL_P<7> VDD VSS / RSC_IHPSG13_INVX2 +XB_DEC3INV<6> net041<25> B_SEL_P<6> VDD VSS / RSC_IHPSG13_INVX2 +XB_DEC3INV<5> net041<26> B_SEL_P<5> VDD VSS / RSC_IHPSG13_INVX2 +XB_DEC3INV<4> net041<27> B_SEL_P<4> VDD VSS / RSC_IHPSG13_INVX2 +XB_DEC3INV<3> net041<28> B_SEL_P<3> VDD VSS / RSC_IHPSG13_INVX2 +XB_DEC3INV<2> net041<29> B_SEL_P<2> VDD VSS / RSC_IHPSG13_INVX2 +XB_DEC3INV<1> net041<30> B_SEL_P<1> VDD VSS / RSC_IHPSG13_INVX2 +XB_DEC3INV<0> net041<31> B_SEL_P<0> VDD VSS / RSC_IHPSG13_INVX2 +XB_I49 B_DI_R B_DI_N VDD VSS / RSC_IHPSG13_INVX2 +XA_I83 A_BM_R A_BM_N VDD VSS / RSC_IHPSG13_INVX2 +XA_DEC3INV<31> net23<0> A_SEL_P<31> VDD VSS / RSC_IHPSG13_INVX2 +XA_DEC3INV<30> net23<1> A_SEL_P<30> VDD VSS / RSC_IHPSG13_INVX2 +XA_DEC3INV<29> net23<2> A_SEL_P<29> VDD VSS / RSC_IHPSG13_INVX2 +XA_DEC3INV<28> net23<3> A_SEL_P<28> VDD VSS / RSC_IHPSG13_INVX2 +XA_DEC3INV<27> net23<4> A_SEL_P<27> VDD VSS / RSC_IHPSG13_INVX2 +XA_DEC3INV<26> net23<5> A_SEL_P<26> VDD VSS / RSC_IHPSG13_INVX2 +XA_DEC3INV<25> net23<6> A_SEL_P<25> VDD VSS / RSC_IHPSG13_INVX2 +XA_DEC3INV<24> net23<7> A_SEL_P<24> VDD VSS / RSC_IHPSG13_INVX2 +XA_DEC3INV<23> net23<8> A_SEL_P<23> VDD VSS / RSC_IHPSG13_INVX2 +XA_DEC3INV<22> net23<9> A_SEL_P<22> VDD VSS / RSC_IHPSG13_INVX2 +XA_DEC3INV<21> net23<10> A_SEL_P<21> VDD VSS / RSC_IHPSG13_INVX2 +XA_DEC3INV<20> net23<11> A_SEL_P<20> VDD VSS / RSC_IHPSG13_INVX2 +XA_DEC3INV<19> net23<12> A_SEL_P<19> VDD VSS / RSC_IHPSG13_INVX2 +XA_DEC3INV<18> net23<13> A_SEL_P<18> VDD VSS / RSC_IHPSG13_INVX2 +XA_DEC3INV<17> net23<14> A_SEL_P<17> VDD VSS / RSC_IHPSG13_INVX2 +XA_DEC3INV<16> net23<15> A_SEL_P<16> VDD VSS / RSC_IHPSG13_INVX2 +XA_DEC3INV<15> net23<16> A_SEL_P<15> VDD VSS / RSC_IHPSG13_INVX2 +XA_DEC3INV<14> net23<17> A_SEL_P<14> VDD VSS / RSC_IHPSG13_INVX2 +XA_DEC3INV<13> net23<18> A_SEL_P<13> VDD VSS / RSC_IHPSG13_INVX2 +XA_DEC3INV<12> net23<19> A_SEL_P<12> VDD VSS / RSC_IHPSG13_INVX2 +XA_DEC3INV<11> net23<20> A_SEL_P<11> VDD VSS / RSC_IHPSG13_INVX2 +XA_DEC3INV<10> net23<21> A_SEL_P<10> VDD VSS / RSC_IHPSG13_INVX2 +XA_DEC3INV<9> net23<22> A_SEL_P<9> VDD VSS / RSC_IHPSG13_INVX2 +XA_DEC3INV<8> net23<23> A_SEL_P<8> VDD VSS / RSC_IHPSG13_INVX2 +XA_DEC3INV<7> net23<24> A_SEL_P<7> VDD VSS / RSC_IHPSG13_INVX2 +XA_DEC3INV<6> net23<25> A_SEL_P<6> VDD VSS / RSC_IHPSG13_INVX2 +XA_DEC3INV<5> net23<26> A_SEL_P<5> VDD VSS / RSC_IHPSG13_INVX2 +XA_DEC3INV<4> net23<27> A_SEL_P<4> VDD VSS / RSC_IHPSG13_INVX2 +XA_DEC3INV<3> net23<28> A_SEL_P<3> VDD VSS / RSC_IHPSG13_INVX2 +XA_DEC3INV<2> net23<29> A_SEL_P<2> VDD VSS / RSC_IHPSG13_INVX2 +XA_DEC3INV<1> net23<30> A_SEL_P<1> VDD VSS / RSC_IHPSG13_INVX2 +XA_DEC3INV<0> net23<31> A_SEL_P<0> VDD VSS / RSC_IHPSG13_INVX2 +XA_I49 A_DI_R A_DI_N VDD VSS / RSC_IHPSG13_INVX2 +XB_ISENSE B_SAE B_BLC_SEL B_BLT_SEL net037 net038 VDD VSS / ++ RSC_IHPSG13_DFPQD_MSAFFX2 +XA_ISENSE A_SAE A_BLC_SEL A_BLT_SEL net19 net20 VDD VSS / ++ RSC_IHPSG13_DFPQD_MSAFFX2 +XB_DREG B_BIST_EN_I B_BIST_DW_I B_DCLK_B_L B_DW_I B_DI_R net042 VDD ++ VSS / RSC_IHPSG13_DFNQMX2IX1 +XB_BREG B_BIST_EN_I B_BIST_BM_I B_DCLK_B_L B_BM_I B_BM_R net043 VDD ++ VSS / RSC_IHPSG13_DFNQMX2IX1 +XA_DREG A_BIST_EN_I A_BIST_DW_I A_DCLK_B_L A_DW_I A_DI_R net22 VDD VSS ++ / RSC_IHPSG13_DFNQMX2IX1 +XA_BREG A_BIST_EN_I A_BIST_BM_I A_DCLK_B_L A_BM_I A_BM_R net21 VDD VSS ++ / RSC_IHPSG13_DFNQMX2IX1 +XB_DEC3<31> B_P1<1> B_P0<1> B_ADDR_DEC<7> net041<0> VDD VSS / ++ RSC_IHPSG13_NAND3X2 +XB_DEC3<30> B_P1<1> B_P0<1> B_ADDR_DEC<6> net041<1> VDD VSS / ++ RSC_IHPSG13_NAND3X2 +XB_DEC3<29> B_P1<1> B_P0<1> B_ADDR_DEC<5> net041<2> VDD VSS / ++ RSC_IHPSG13_NAND3X2 +XB_DEC3<28> B_P1<1> B_P0<1> B_ADDR_DEC<4> net041<3> VDD VSS / ++ RSC_IHPSG13_NAND3X2 +XB_DEC3<27> B_P1<1> B_P0<1> B_ADDR_DEC<3> net041<4> VDD VSS / ++ RSC_IHPSG13_NAND3X2 +XB_DEC3<26> B_P1<1> B_P0<1> B_ADDR_DEC<2> net041<5> VDD VSS / ++ RSC_IHPSG13_NAND3X2 +XB_DEC3<25> B_P1<1> B_P0<1> B_ADDR_DEC<1> net041<6> VDD VSS / ++ RSC_IHPSG13_NAND3X2 +XB_DEC3<24> B_P1<1> B_P0<1> B_ADDR_DEC<0> net041<7> VDD VSS / ++ RSC_IHPSG13_NAND3X2 +XB_DEC3<23> B_P1<1> B_N0<1> B_ADDR_DEC<7> net041<8> VDD VSS / ++ RSC_IHPSG13_NAND3X2 +XB_DEC3<22> B_P1<1> B_N0<1> B_ADDR_DEC<6> net041<9> VDD VSS / ++ RSC_IHPSG13_NAND3X2 +XB_DEC3<21> B_P1<1> B_N0<1> B_ADDR_DEC<5> net041<10> VDD VSS / ++ RSC_IHPSG13_NAND3X2 +XB_DEC3<20> B_P1<1> B_N0<1> B_ADDR_DEC<4> net041<11> VDD VSS / ++ RSC_IHPSG13_NAND3X2 +XB_DEC3<19> B_P1<1> B_N0<1> B_ADDR_DEC<3> net041<12> VDD VSS / ++ RSC_IHPSG13_NAND3X2 +XB_DEC3<18> B_P1<1> B_N0<1> B_ADDR_DEC<2> net041<13> VDD VSS / ++ RSC_IHPSG13_NAND3X2 +XB_DEC3<17> B_P1<1> B_N0<1> B_ADDR_DEC<1> net041<14> VDD VSS / ++ RSC_IHPSG13_NAND3X2 +XB_DEC3<16> B_P1<1> B_N0<1> B_ADDR_DEC<0> net041<15> VDD VSS / ++ RSC_IHPSG13_NAND3X2 +XB_DEC3<15> B_N1<0> B_P0<0> B_ADDR_DEC<7> net041<16> VDD VSS / ++ RSC_IHPSG13_NAND3X2 +XB_DEC3<14> B_N1<0> B_P0<0> B_ADDR_DEC<6> net041<17> VDD VSS / ++ RSC_IHPSG13_NAND3X2 +XB_DEC3<13> B_N1<0> B_P0<0> B_ADDR_DEC<5> net041<18> VDD VSS / ++ RSC_IHPSG13_NAND3X2 +XB_DEC3<12> B_N1<0> B_P0<0> B_ADDR_DEC<4> net041<19> VDD VSS / ++ RSC_IHPSG13_NAND3X2 +XB_DEC3<11> B_N1<0> B_P0<0> B_ADDR_DEC<3> net041<20> VDD VSS / ++ RSC_IHPSG13_NAND3X2 +XB_DEC3<10> B_N1<0> B_P0<0> B_ADDR_DEC<2> net041<21> VDD VSS / ++ RSC_IHPSG13_NAND3X2 +XB_DEC3<9> B_N1<0> B_P0<0> B_ADDR_DEC<1> net041<22> VDD VSS / ++ RSC_IHPSG13_NAND3X2 +XB_DEC3<8> B_N1<0> B_P0<0> B_ADDR_DEC<0> net041<23> VDD VSS / ++ RSC_IHPSG13_NAND3X2 +XB_DEC3<7> B_N1<0> B_N0<0> B_ADDR_DEC<7> net041<24> VDD VSS / ++ RSC_IHPSG13_NAND3X2 +XB_DEC3<6> B_N1<0> B_N0<0> B_ADDR_DEC<6> net041<25> VDD VSS / ++ RSC_IHPSG13_NAND3X2 +XB_DEC3<5> B_N1<0> B_N0<0> B_ADDR_DEC<5> net041<26> VDD VSS / ++ RSC_IHPSG13_NAND3X2 +XB_DEC3<4> B_N1<0> B_N0<0> B_ADDR_DEC<4> net041<27> VDD VSS / ++ RSC_IHPSG13_NAND3X2 +XB_DEC3<3> B_N1<0> B_N0<0> B_ADDR_DEC<3> net041<28> VDD VSS / ++ RSC_IHPSG13_NAND3X2 +XB_DEC3<2> B_N1<0> B_N0<0> B_ADDR_DEC<2> net041<29> VDD VSS / ++ RSC_IHPSG13_NAND3X2 +XB_DEC3<1> B_N1<0> B_N0<0> B_ADDR_DEC<1> net041<30> VDD VSS / ++ RSC_IHPSG13_NAND3X2 +XB_DEC3<0> B_N1<0> B_N0<0> B_ADDR_DEC<0> net041<31> VDD VSS / ++ RSC_IHPSG13_NAND3X2 +XA_DEC3<31> A_P1<1> A_P0<1> A_ADDR_DEC<7> net23<0> VDD VSS / ++ RSC_IHPSG13_NAND3X2 +XA_DEC3<30> A_P1<1> A_P0<1> A_ADDR_DEC<6> net23<1> VDD VSS / ++ RSC_IHPSG13_NAND3X2 +XA_DEC3<29> A_P1<1> A_P0<1> A_ADDR_DEC<5> net23<2> VDD VSS / ++ RSC_IHPSG13_NAND3X2 +XA_DEC3<28> A_P1<1> A_P0<1> A_ADDR_DEC<4> net23<3> VDD VSS / ++ RSC_IHPSG13_NAND3X2 +XA_DEC3<27> A_P1<1> A_P0<1> A_ADDR_DEC<3> net23<4> VDD VSS / ++ RSC_IHPSG13_NAND3X2 +XA_DEC3<26> A_P1<1> A_P0<1> A_ADDR_DEC<2> net23<5> VDD VSS / ++ RSC_IHPSG13_NAND3X2 +XA_DEC3<25> A_P1<1> A_P0<1> A_ADDR_DEC<1> net23<6> VDD VSS / ++ RSC_IHPSG13_NAND3X2 +XA_DEC3<24> A_P1<1> A_P0<1> A_ADDR_DEC<0> net23<7> VDD VSS / ++ RSC_IHPSG13_NAND3X2 +XA_DEC3<23> A_P1<1> A_N0<1> A_ADDR_DEC<7> net23<8> VDD VSS / ++ RSC_IHPSG13_NAND3X2 +XA_DEC3<22> A_P1<1> A_N0<1> A_ADDR_DEC<6> net23<9> VDD VSS / ++ RSC_IHPSG13_NAND3X2 +XA_DEC3<21> A_P1<1> A_N0<1> A_ADDR_DEC<5> net23<10> VDD VSS / ++ RSC_IHPSG13_NAND3X2 +XA_DEC3<20> A_P1<1> A_N0<1> A_ADDR_DEC<4> net23<11> VDD VSS / ++ RSC_IHPSG13_NAND3X2 +XA_DEC3<19> A_P1<1> A_N0<1> A_ADDR_DEC<3> net23<12> VDD VSS / ++ RSC_IHPSG13_NAND3X2 +XA_DEC3<18> A_P1<1> A_N0<1> A_ADDR_DEC<2> net23<13> VDD VSS / ++ RSC_IHPSG13_NAND3X2 +XA_DEC3<17> A_P1<1> A_N0<1> A_ADDR_DEC<1> net23<14> VDD VSS / ++ RSC_IHPSG13_NAND3X2 +XA_DEC3<16> A_P1<1> A_N0<1> A_ADDR_DEC<0> net23<15> VDD VSS / ++ RSC_IHPSG13_NAND3X2 +XA_DEC3<15> A_N1<0> A_P0<0> A_ADDR_DEC<7> net23<16> VDD VSS / ++ RSC_IHPSG13_NAND3X2 +XA_DEC3<14> A_N1<0> A_P0<0> A_ADDR_DEC<6> net23<17> VDD VSS / ++ RSC_IHPSG13_NAND3X2 +XA_DEC3<13> A_N1<0> A_P0<0> A_ADDR_DEC<5> net23<18> VDD VSS / ++ RSC_IHPSG13_NAND3X2 +XA_DEC3<12> A_N1<0> A_P0<0> A_ADDR_DEC<4> net23<19> VDD VSS / ++ RSC_IHPSG13_NAND3X2 +XA_DEC3<11> A_N1<0> A_P0<0> A_ADDR_DEC<3> net23<20> VDD VSS / ++ RSC_IHPSG13_NAND3X2 +XA_DEC3<10> A_N1<0> A_P0<0> A_ADDR_DEC<2> net23<21> VDD VSS / ++ RSC_IHPSG13_NAND3X2 +XA_DEC3<9> A_N1<0> A_P0<0> A_ADDR_DEC<1> net23<22> VDD VSS / ++ RSC_IHPSG13_NAND3X2 +XA_DEC3<8> A_N1<0> A_P0<0> A_ADDR_DEC<0> net23<23> VDD VSS / ++ RSC_IHPSG13_NAND3X2 +XA_DEC3<7> A_N1<0> A_N0<0> A_ADDR_DEC<7> net23<24> VDD VSS / ++ RSC_IHPSG13_NAND3X2 +XA_DEC3<6> A_N1<0> A_N0<0> A_ADDR_DEC<6> net23<25> VDD VSS / ++ RSC_IHPSG13_NAND3X2 +XA_DEC3<5> A_N1<0> A_N0<0> A_ADDR_DEC<5> net23<26> VDD VSS / ++ RSC_IHPSG13_NAND3X2 +XA_DEC3<4> A_N1<0> A_N0<0> A_ADDR_DEC<4> net23<27> VDD VSS / ++ RSC_IHPSG13_NAND3X2 +XA_DEC3<3> A_N1<0> A_N0<0> A_ADDR_DEC<3> net23<28> VDD VSS / ++ RSC_IHPSG13_NAND3X2 +XA_DEC3<2> A_N1<0> A_N0<0> A_ADDR_DEC<2> net23<29> VDD VSS / ++ RSC_IHPSG13_NAND3X2 +XA_DEC3<1> A_N1<0> A_N0<0> A_ADDR_DEC<1> net23<30> VDD VSS / ++ RSC_IHPSG13_NAND3X2 +XA_DEC3<0> A_N1<0> A_N0<0> A_ADDR_DEC<0> net23<31> VDD VSS / ++ RSC_IHPSG13_NAND3X2 +XB_I89 B_DCLK_B_L B_DCLK_B_R / RSC_IHPSG13_MET3RES +XB_I91 B_RCLK_B_L B_RCLK_B_R / RSC_IHPSG13_MET3RES +XB_I90 B_WCLK_B_L B_WCLK_B_R / RSC_IHPSG13_MET3RES +XB_I88 B_DCLK_L B_DCLK_R / RSC_IHPSG13_MET3RES +XB_I87 B_WCLK_L B_WCLK_R / RSC_IHPSG13_MET3RES +XB_R2 B_RCLK_L B_RCLK_R / RSC_IHPSG13_MET3RES +XA_I89 A_DCLK_B_L A_DCLK_B_R / RSC_IHPSG13_MET3RES +XA_I91 A_RCLK_B_L A_RCLK_B_R / RSC_IHPSG13_MET3RES +XA_I90 A_WCLK_B_L A_WCLK_B_R / RSC_IHPSG13_MET3RES +XA_I88 A_DCLK_L A_DCLK_R / RSC_IHPSG13_MET3RES +XA_I87 A_WCLK_L A_WCLK_R / RSC_IHPSG13_MET3RES +XA_R2 A_RCLK_L A_RCLK_R / RSC_IHPSG13_MET3RES +XB_BM_TIEH B_TIEH_O VDD VSS / RSC_IHPSG13_TIEH +XA_BM_TIEH A_TIEH_O VDD VSS / RSC_IHPSG13_TIEH +.ENDS +.SUBCKT RM_IHPSG13_512x8_c2_2P_COLDRV13_FILL4 VDD VSS +XI0<11> VDD VSS / RSC_IHPSG13_FILLCAP4 +XI0<10> VDD VSS / RSC_IHPSG13_FILLCAP4 +XI0<9> VDD VSS / RSC_IHPSG13_FILLCAP4 +XI0<8> VDD VSS / RSC_IHPSG13_FILLCAP4 +XI0<7> VDD VSS / RSC_IHPSG13_FILLCAP4 +XI0<6> VDD VSS / RSC_IHPSG13_FILLCAP4 +XI0<5> VDD VSS / RSC_IHPSG13_FILLCAP4 +XI0<4> VDD VSS / RSC_IHPSG13_FILLCAP4 +XI0<3> VDD VSS / RSC_IHPSG13_FILLCAP4 +XI0<2> VDD VSS / RSC_IHPSG13_FILLCAP4 +XI0<1> VDD VSS / RSC_IHPSG13_FILLCAP4 +.ENDS + + +.SUBCKT RSC_IHPSG13_CBUFX16 A Z VDD VSS +MN0 net4 A VSS VSS sg13_lv_nmos m=1 w=2.115u l=130.00n ng=3 nrd=0 nrs=0 +MN1 Z net4 VSS VSS sg13_lv_nmos m=1 w=5.64u l=130.00n ng=8 nrd=0 nrs=0 +MP1 Z net4 VDD VDD sg13_lv_pmos m=1 w=13.000u l=130.00n ng=8 nrd=0 ++ nrs=0 +MP0 net4 A VDD VDD sg13_lv_pmos m=1 w=4.89u l=130.00n ng=3 nrd=0 nrs=0 +.ENDS +.SUBCKT RM_IHPSG13_512x8_c2_1P_COLDRV13X16 ADDR_COL_I<1> ADDR_COL_I<0> ADDR_COL_O<1> ++ ADDR_COL_O<0> ADDR_DEC_I<7> ADDR_DEC_I<6> ADDR_DEC_I<5> ADDR_DEC_I<4> ++ ADDR_DEC_I<3> ADDR_DEC_I<2> ADDR_DEC_I<1> ADDR_DEC_I<0> ADDR_DEC_O<7> ++ ADDR_DEC_O<6> ADDR_DEC_O<5> ADDR_DEC_O<4> ADDR_DEC_O<3> ADDR_DEC_O<2> ++ ADDR_DEC_O<1> ADDR_DEC_O<0> DCLK_I DCLK_O RCLK_I RCLK_O WCLK_I WCLK_O ++ VDD VSS +XI1<1> VDD VSS / RSC_IHPSG13_FILLCAP4 +XI1<0> VDD VSS / RSC_IHPSG13_FILLCAP4 +XI0<3> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI0<2> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI0<1> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI0<0> VDD VSS / RSC_IHPSG13_FILLCAP8 +XADDR_COL_DRV<1> ADDR_COL_I<1> ADDR_COL_O<1> VDD VSS / ++ RSC_IHPSG13_CBUFX16 +XADDR_COL_DRV<0> ADDR_COL_I<0> ADDR_COL_O<0> VDD VSS / ++ RSC_IHPSG13_CBUFX16 +XADDR_DEC_DRV<7> ADDR_DEC_I<7> ADDR_DEC_O<7> VDD VSS / ++ RSC_IHPSG13_CBUFX16 +XADDR_DEC_DRV<6> ADDR_DEC_I<6> ADDR_DEC_O<6> VDD VSS / ++ RSC_IHPSG13_CBUFX16 +XADDR_DEC_DRV<5> ADDR_DEC_I<5> ADDR_DEC_O<5> VDD VSS / ++ RSC_IHPSG13_CBUFX16 +XADDR_DEC_DRV<4> ADDR_DEC_I<4> ADDR_DEC_O<4> VDD VSS / ++ RSC_IHPSG13_CBUFX16 +XADDR_DEC_DRV<3> ADDR_DEC_I<3> ADDR_DEC_O<3> VDD VSS / ++ RSC_IHPSG13_CBUFX16 +XADDR_DEC_DRV<2> ADDR_DEC_I<2> ADDR_DEC_O<2> VDD VSS / ++ RSC_IHPSG13_CBUFX16 +XADDR_DEC_DRV<1> ADDR_DEC_I<1> ADDR_DEC_O<1> VDD VSS / ++ RSC_IHPSG13_CBUFX16 +XADDR_DEC_DRV<0> ADDR_DEC_I<0> ADDR_DEC_O<0> VDD VSS / ++ RSC_IHPSG13_CBUFX16 +XDCLK_DRV DCLK_I DCLK_O VDD VSS / RSC_IHPSG13_CBUFX16 +XRCLK_DRV RCLK_I RCLK_O VDD VSS / RSC_IHPSG13_CBUFX16 +XWCLK_DRV WCLK_I WCLK_O VDD VSS / RSC_IHPSG13_CBUFX16 +.ENDS +.SUBCKT RSC_IHPSG13_WLDRVX16 A Z VDD VSS +MN1 Z net6 VSS VSS sg13_lv_nmos m=1 w=1.41u l=130.00n ng=2 nrd=0 nrs=0 +MN0 net6 A VSS VSS sg13_lv_nmos m=1 w=1.8u l=130.00n ng=2 nrd=0 nrs=0 +MP1 Z net6 VDD VDD sg13_lv_pmos m=1 w=12.96u l=130.00n ng=8 nrd=0 nrs=0 +MP0 net6 A VDD VDD sg13_lv_pmos m=1 w=900.0n l=130.00n ng=1 nrd=0 nrs=0 +.ENDS +.SUBCKT RM_IHPSG13_512x8_c2_1P_WLDRV16X16 A<15> A<14> A<13> A<12> A<11> A<10> A<9> A<8> ++ A<7> A<6> A<5> A<4> A<3> A<2> A<1> A<0> Z<15> Z<14> Z<13> Z<12> Z<11> Z<10> ++ Z<9> Z<8> Z<7> Z<6> Z<5> Z<4> Z<3> Z<2> Z<1> Z<0> VDD VSS +XBUF<15> A<15> Z<15> VDD VSS / RSC_IHPSG13_WLDRVX16 +XBUF<14> A<14> Z<14> VDD VSS / RSC_IHPSG13_WLDRVX16 +XBUF<13> A<13> Z<13> VDD VSS / RSC_IHPSG13_WLDRVX16 +XBUF<12> A<12> Z<12> VDD VSS / RSC_IHPSG13_WLDRVX16 +XBUF<11> A<11> Z<11> VDD VSS / RSC_IHPSG13_WLDRVX16 +XBUF<10> A<10> Z<10> VDD VSS / RSC_IHPSG13_WLDRVX16 +XBUF<9> A<9> Z<9> VDD VSS / RSC_IHPSG13_WLDRVX16 +XBUF<8> A<8> Z<8> VDD VSS / RSC_IHPSG13_WLDRVX16 +XBUF<7> A<7> Z<7> VDD VSS / RSC_IHPSG13_WLDRVX16 +XBUF<6> A<6> Z<6> VDD VSS / RSC_IHPSG13_WLDRVX16 +XBUF<5> A<5> Z<5> VDD VSS / RSC_IHPSG13_WLDRVX16 +XBUF<4> A<4> Z<4> VDD VSS / RSC_IHPSG13_WLDRVX16 +XBUF<3> A<3> Z<3> VDD VSS / RSC_IHPSG13_WLDRVX16 +XBUF<2> A<2> Z<2> VDD VSS / RSC_IHPSG13_WLDRVX16 +XBUF<1> A<1> Z<1> VDD VSS / RSC_IHPSG13_WLDRVX16 +XBUF<0> A<0> Z<0> VDD VSS / RSC_IHPSG13_WLDRVX16 +.ENDS + + +.SUBCKT RM_IHPSG13_512x8_c2_2P_COLDRV13X4 ADDR_COL_I<1> ADDR_COL_I<0> ADDR_COL_O<1> ++ ADDR_COL_O<0> ADDR_DEC_I<7> ADDR_DEC_I<6> ADDR_DEC_I<5> ADDR_DEC_I<4> ++ ADDR_DEC_I<3> ADDR_DEC_I<2> ADDR_DEC_I<1> ADDR_DEC_I<0> ADDR_DEC_O<7> ++ ADDR_DEC_O<6> ADDR_DEC_O<5> ADDR_DEC_O<4> ADDR_DEC_O<3> ADDR_DEC_O<2> ++ ADDR_DEC_O<1> ADDR_DEC_O<0> DCLK_I DCLK_O RCLK_I RCLK_O WCLK_I WCLK_O ++ VDD VSS +XWCLK_DRV WCLK_I WCLK_O VDD VSS / RSC_IHPSG13_CBUFX4 +XRCLK_DRV RCLK_I RCLK_O VDD VSS / RSC_IHPSG13_CBUFX4 +XDCLK_DRV DCLK_I DCLK_O VDD VSS / RSC_IHPSG13_CBUFX4 +XADDR_COL_DRV<1> ADDR_COL_I<1> ADDR_COL_O<1> VDD VSS / ++ RSC_IHPSG13_CBUFX4 +XADDR_COL_DRV<0> ADDR_COL_I<0> ADDR_COL_O<0> VDD VSS / ++ RSC_IHPSG13_CBUFX4 +XADDR_DEC_DRV<7> ADDR_DEC_I<7> ADDR_DEC_O<7> VDD VSS / ++ RSC_IHPSG13_CBUFX4 +XADDR_DEC_DRV<6> ADDR_DEC_I<6> ADDR_DEC_O<6> VDD VSS / ++ RSC_IHPSG13_CBUFX4 +XADDR_DEC_DRV<5> ADDR_DEC_I<5> ADDR_DEC_O<5> VDD VSS / ++ RSC_IHPSG13_CBUFX4 +XADDR_DEC_DRV<4> ADDR_DEC_I<4> ADDR_DEC_O<4> VDD VSS / ++ RSC_IHPSG13_CBUFX4 +XADDR_DEC_DRV<3> ADDR_DEC_I<3> ADDR_DEC_O<3> VDD VSS / ++ RSC_IHPSG13_CBUFX4 +XADDR_DEC_DRV<2> ADDR_DEC_I<2> ADDR_DEC_O<2> VDD VSS / ++ RSC_IHPSG13_CBUFX4 +XADDR_DEC_DRV<1> ADDR_DEC_I<1> ADDR_DEC_O<1> VDD VSS / ++ RSC_IHPSG13_CBUFX4 +XADDR_DEC_DRV<0> ADDR_DEC_I<0> ADDR_DEC_O<0> VDD VSS / ++ RSC_IHPSG13_CBUFX4 +XI0<6> VDD VSS / RSC_IHPSG13_FILLCAP4 +XI0<5> VDD VSS / RSC_IHPSG13_FILLCAP4 +XI0<4> VDD VSS / RSC_IHPSG13_FILLCAP4 +XI0<3> VDD VSS / RSC_IHPSG13_FILLCAP4 +XI0<2> VDD VSS / RSC_IHPSG13_FILLCAP4 +XI0<1> VDD VSS / RSC_IHPSG13_FILLCAP4 +XI1 VDD VSS / RSC_IHPSG13_FILLCAP8 +.ENDS +.SUBCKT RM_IHPSG13_512x8_c2_2P_WLDRV16X4 A<15> A<14> A<13> A<12> A<11> A<10> A<9> A<8> ++ A<7> A<6> A<5> A<4> A<3> A<2> A<1> A<0> Z<15> Z<14> Z<13> Z<12> Z<11> Z<10> ++ Z<9> Z<8> Z<7> Z<6> Z<5> Z<4> Z<3> Z<2> Z<1> Z<0> VDD VSS +XBUF<15> A<15> Z<15> VDD VSS / RSC_IHPSG13_WLDRVX4 +XBUF<14> A<14> Z<14> VDD VSS / RSC_IHPSG13_WLDRVX4 +XBUF<13> A<13> Z<13> VDD VSS / RSC_IHPSG13_WLDRVX4 +XBUF<12> A<12> Z<12> VDD VSS / RSC_IHPSG13_WLDRVX4 +XBUF<11> A<11> Z<11> VDD VSS / RSC_IHPSG13_WLDRVX4 +XBUF<10> A<10> Z<10> VDD VSS / RSC_IHPSG13_WLDRVX4 +XBUF<9> A<9> Z<9> VDD VSS / RSC_IHPSG13_WLDRVX4 +XBUF<8> A<8> Z<8> VDD VSS / RSC_IHPSG13_WLDRVX4 +XBUF<7> A<7> Z<7> VDD VSS / RSC_IHPSG13_WLDRVX4 +XBUF<6> A<6> Z<6> VDD VSS / RSC_IHPSG13_WLDRVX4 +XBUF<5> A<5> Z<5> VDD VSS / RSC_IHPSG13_WLDRVX4 +XBUF<4> A<4> Z<4> VDD VSS / RSC_IHPSG13_WLDRVX4 +XBUF<3> A<3> Z<3> VDD VSS / RSC_IHPSG13_WLDRVX4 +XBUF<2> A<2> Z<2> VDD VSS / RSC_IHPSG13_WLDRVX4 +XBUF<1> A<1> Z<1> VDD VSS / RSC_IHPSG13_WLDRVX4 +XBUF<0> A<0> Z<0> VDD VSS / RSC_IHPSG13_WLDRVX4 +.ENDS +.SUBCKT RM_IHPSG13_512x8_c2_2P_ROWDEC8 ADDR_N_I<7> ADDR_N_I<6> ADDR_N_I<5> ADDR_N_I<4> ++ ADDR_N_I<3> ADDR_N_I<2> ADDR_N_I<1> ADDR_N_I<0> CS_I ECLK_I WL_O<255> ++ WL_O<254> WL_O<253> WL_O<252> WL_O<251> WL_O<250> WL_O<249> WL_O<248> ++ WL_O<247> WL_O<246> WL_O<245> WL_O<244> WL_O<243> WL_O<242> WL_O<241> ++ WL_O<240> WL_O<239> WL_O<238> WL_O<237> WL_O<236> WL_O<235> WL_O<234> ++ WL_O<233> WL_O<232> WL_O<231> WL_O<230> WL_O<229> WL_O<228> WL_O<227> ++ WL_O<226> WL_O<225> WL_O<224> WL_O<223> WL_O<222> WL_O<221> WL_O<220> ++ WL_O<219> WL_O<218> WL_O<217> WL_O<216> WL_O<215> WL_O<214> WL_O<213> ++ WL_O<212> WL_O<211> WL_O<210> WL_O<209> WL_O<208> WL_O<207> WL_O<206> ++ WL_O<205> WL_O<204> WL_O<203> WL_O<202> WL_O<201> WL_O<200> WL_O<199> ++ WL_O<198> WL_O<197> WL_O<196> WL_O<195> WL_O<194> WL_O<193> WL_O<192> ++ WL_O<191> WL_O<190> WL_O<189> WL_O<188> WL_O<187> WL_O<186> WL_O<185> ++ WL_O<184> WL_O<183> WL_O<182> WL_O<181> WL_O<180> WL_O<179> WL_O<178> ++ WL_O<177> WL_O<176> WL_O<175> WL_O<174> WL_O<173> WL_O<172> WL_O<171> ++ WL_O<170> WL_O<169> WL_O<168> WL_O<167> WL_O<166> WL_O<165> WL_O<164> ++ WL_O<163> WL_O<162> WL_O<161> WL_O<160> WL_O<159> WL_O<158> WL_O<157> ++ WL_O<156> WL_O<155> WL_O<154> WL_O<153> WL_O<152> WL_O<151> WL_O<150> ++ WL_O<149> WL_O<148> WL_O<147> WL_O<146> WL_O<145> WL_O<144> WL_O<143> ++ WL_O<142> WL_O<141> WL_O<140> WL_O<139> WL_O<138> WL_O<137> WL_O<136> ++ WL_O<135> WL_O<134> WL_O<133> WL_O<132> WL_O<131> WL_O<130> WL_O<129> ++ WL_O<128> WL_O<127> WL_O<126> WL_O<125> WL_O<124> WL_O<123> WL_O<122> ++ WL_O<121> WL_O<120> WL_O<119> WL_O<118> WL_O<117> WL_O<116> WL_O<115> ++ WL_O<114> WL_O<113> WL_O<112> WL_O<111> WL_O<110> WL_O<109> WL_O<108> ++ WL_O<107> WL_O<106> WL_O<105> WL_O<104> WL_O<103> WL_O<102> WL_O<101> ++ WL_O<100> WL_O<99> WL_O<98> WL_O<97> WL_O<96> WL_O<95> WL_O<94> WL_O<93> ++ WL_O<92> WL_O<91> WL_O<90> WL_O<89> WL_O<88> WL_O<87> WL_O<86> WL_O<85> ++ WL_O<84> WL_O<83> WL_O<82> WL_O<81> WL_O<80> WL_O<79> WL_O<78> WL_O<77> ++ WL_O<76> WL_O<75> WL_O<74> WL_O<73> WL_O<72> WL_O<71> WL_O<70> WL_O<69> ++ WL_O<68> WL_O<67> WL_O<66> WL_O<65> WL_O<64> WL_O<63> WL_O<62> WL_O<61> ++ WL_O<60> WL_O<59> WL_O<58> WL_O<57> WL_O<56> WL_O<55> WL_O<54> WL_O<53> ++ WL_O<52> WL_O<51> WL_O<50> WL_O<49> WL_O<48> WL_O<47> WL_O<46> WL_O<45> ++ WL_O<44> WL_O<43> WL_O<42> WL_O<41> WL_O<40> WL_O<39> WL_O<38> WL_O<37> ++ WL_O<36> WL_O<35> WL_O<34> WL_O<33> WL_O<32> WL_O<31> WL_O<30> WL_O<29> ++ WL_O<28> WL_O<27> WL_O<26> WL_O<25> WL_O<24> WL_O<23> WL_O<22> WL_O<21> ++ WL_O<20> WL_O<19> WL_O<18> WL_O<17> WL_O<16> WL_O<15> WL_O<14> WL_O<13> ++ WL_O<12> WL_O<11> WL_O<10> WL_O<9> WL_O<8> WL_O<7> WL_O<6> WL_O<5> WL_O<4> ++ WL_O<3> WL_O<2> WL_O<1> WL_O<0> VDD VSS +XDEC11<4> ADDR_N_I<7> ADDR_N_I<6> CS_I CS04<3> VDD VSS / ++ RM_IHPSG13_512x8_c2_2P_DEC03 +XDEC11<3> ADDR_N_I<5> ADDR_N_I<4> CS04<3> CS00<15> VDD VSS / ++ RM_IHPSG13_512x8_c2_2P_DEC03 +XDEC11<2> ADDR_N_I<5> ADDR_N_I<4> CS04<2> CS00<11> VDD VSS / ++ RM_IHPSG13_512x8_c2_2P_DEC03 +XDEC11<1> ADDR_N_I<5> ADDR_N_I<4> CS04<1> CS00<7> VDD VSS / ++ RM_IHPSG13_512x8_c2_2P_DEC03 +XDEC11<0> ADDR_N_I<5> ADDR_N_I<4> CS04<0> CS00<3> VDD VSS / ++ RM_IHPSG13_512x8_c2_2P_DEC03 +XSEL<15> ADDR_N_I<3> ADDR_N_I<2> ADDR_N_I<1> ADDR_N_I<0> CS00<15> ECLK_H<15> ++ ECLK_H<16> ECLK_B<15> ECLK_B<16> WL_O<255> WL_O<254> WL_O<253> WL_O<252> ++ WL_O<251> WL_O<250> WL_O<249> WL_O<248> WL_O<247> WL_O<246> WL_O<245> ++ WL_O<244> WL_O<243> WL_O<242> WL_O<241> WL_O<240> VDD VSS / ++ RM_IHPSG13_512x8_c2_2P_DEC04 +XSEL<14> ADDR_N_I<3> ADDR_N_I<2> ADDR_N_I<1> ADDR_N_I<0> CS00<14> ECLK_H<14> ++ ECLK_H<15> ECLK_B<14> ECLK_B<15> WL_O<239> WL_O<238> WL_O<237> WL_O<236> ++ WL_O<235> WL_O<234> WL_O<233> WL_O<232> WL_O<231> WL_O<230> WL_O<229> ++ WL_O<228> WL_O<227> WL_O<226> WL_O<225> WL_O<224> VDD VSS / ++ RM_IHPSG13_512x8_c2_2P_DEC04 +XSEL<13> ADDR_N_I<3> ADDR_N_I<2> ADDR_N_I<1> ADDR_N_I<0> CS00<13> ECLK_H<13> ++ ECLK_H<14> ECLK_B<13> ECLK_B<14> WL_O<223> WL_O<222> WL_O<221> WL_O<220> ++ WL_O<219> WL_O<218> WL_O<217> WL_O<216> WL_O<215> WL_O<214> WL_O<213> ++ WL_O<212> WL_O<211> WL_O<210> WL_O<209> WL_O<208> VDD VSS / ++ RM_IHPSG13_512x8_c2_2P_DEC04 +XSEL<12> ADDR_N_I<3> ADDR_N_I<2> ADDR_N_I<1> ADDR_N_I<0> CS00<12> ECLK_H<12> ++ ECLK_H<13> ECLK_B<12> ECLK_B<13> WL_O<207> WL_O<206> WL_O<205> WL_O<204> ++ WL_O<203> WL_O<202> WL_O<201> WL_O<200> WL_O<199> WL_O<198> WL_O<197> ++ WL_O<196> WL_O<195> WL_O<194> WL_O<193> WL_O<192> VDD VSS / ++ RM_IHPSG13_512x8_c2_2P_DEC04 +XSEL<11> ADDR_N_I<3> ADDR_N_I<2> ADDR_N_I<1> ADDR_N_I<0> CS00<11> ECLK_H<11> ++ ECLK_H<12> ECLK_B<11> ECLK_B<12> WL_O<191> WL_O<190> WL_O<189> WL_O<188> ++ WL_O<187> WL_O<186> WL_O<185> WL_O<184> WL_O<183> WL_O<182> WL_O<181> ++ WL_O<180> WL_O<179> WL_O<178> WL_O<177> WL_O<176> VDD VSS / ++ RM_IHPSG13_512x8_c2_2P_DEC04 +XSEL<10> ADDR_N_I<3> ADDR_N_I<2> ADDR_N_I<1> ADDR_N_I<0> CS00<10> ECLK_H<10> ++ ECLK_H<11> ECLK_B<10> ECLK_B<11> WL_O<175> WL_O<174> WL_O<173> WL_O<172> ++ WL_O<171> WL_O<170> WL_O<169> WL_O<168> WL_O<167> WL_O<166> WL_O<165> ++ WL_O<164> WL_O<163> WL_O<162> WL_O<161> WL_O<160> VDD VSS / ++ RM_IHPSG13_512x8_c2_2P_DEC04 +XSEL<9> ADDR_N_I<3> ADDR_N_I<2> ADDR_N_I<1> ADDR_N_I<0> CS00<9> ECLK_H<9> ++ ECLK_H<10> ECLK_B<9> ECLK_B<10> WL_O<159> WL_O<158> WL_O<157> WL_O<156> ++ WL_O<155> WL_O<154> WL_O<153> WL_O<152> WL_O<151> WL_O<150> WL_O<149> ++ WL_O<148> WL_O<147> WL_O<146> WL_O<145> WL_O<144> VDD VSS / ++ RM_IHPSG13_512x8_c2_2P_DEC04 +XSEL<8> ADDR_N_I<3> ADDR_N_I<2> ADDR_N_I<1> ADDR_N_I<0> CS00<8> ECLK_H<8> ++ ECLK_H<9> ECLK_B<8> ECLK_B<9> WL_O<143> WL_O<142> WL_O<141> WL_O<140> ++ WL_O<139> WL_O<138> WL_O<137> WL_O<136> WL_O<135> WL_O<134> WL_O<133> ++ WL_O<132> WL_O<131> WL_O<130> WL_O<129> WL_O<128> VDD VSS / ++ RM_IHPSG13_512x8_c2_2P_DEC04 +XSEL<7> ADDR_N_I<3> ADDR_N_I<2> ADDR_N_I<1> ADDR_N_I<0> CS00<7> ECLK_H<7> ++ ECLK_H<8> ECLK_B<7> ECLK_B<8> WL_O<127> WL_O<126> WL_O<125> WL_O<124> ++ WL_O<123> WL_O<122> WL_O<121> WL_O<120> WL_O<119> WL_O<118> WL_O<117> ++ WL_O<116> WL_O<115> WL_O<114> WL_O<113> WL_O<112> VDD VSS / ++ RM_IHPSG13_512x8_c2_2P_DEC04 +XSEL<6> ADDR_N_I<3> ADDR_N_I<2> ADDR_N_I<1> ADDR_N_I<0> CS00<6> ECLK_H<6> ++ ECLK_H<7> ECLK_B<6> ECLK_B<7> WL_O<111> WL_O<110> WL_O<109> WL_O<108> ++ WL_O<107> WL_O<106> WL_O<105> WL_O<104> WL_O<103> WL_O<102> WL_O<101> ++ WL_O<100> WL_O<99> WL_O<98> WL_O<97> WL_O<96> VDD VSS / ++ RM_IHPSG13_512x8_c2_2P_DEC04 +XSEL<5> ADDR_N_I<3> ADDR_N_I<2> ADDR_N_I<1> ADDR_N_I<0> CS00<5> ECLK_H<5> ++ ECLK_H<6> ECLK_B<5> ECLK_B<6> WL_O<95> WL_O<94> WL_O<93> WL_O<92> WL_O<91> ++ WL_O<90> WL_O<89> WL_O<88> WL_O<87> WL_O<86> WL_O<85> WL_O<84> WL_O<83> ++ WL_O<82> WL_O<81> WL_O<80> VDD VSS / RM_IHPSG13_512x8_c2_2P_DEC04 +XSEL<4> ADDR_N_I<3> ADDR_N_I<2> ADDR_N_I<1> ADDR_N_I<0> CS00<4> ECLK_H<4> ++ ECLK_H<5> ECLK_B<4> ECLK_B<5> WL_O<79> WL_O<78> WL_O<77> WL_O<76> WL_O<75> ++ WL_O<74> WL_O<73> WL_O<72> WL_O<71> WL_O<70> WL_O<69> WL_O<68> WL_O<67> ++ WL_O<66> WL_O<65> WL_O<64> VDD VSS / RM_IHPSG13_512x8_c2_2P_DEC04 +XSEL<3> ADDR_N_I<3> ADDR_N_I<2> ADDR_N_I<1> ADDR_N_I<0> CS00<3> ECLK_H<3> ++ ECLK_H<4> ECLK_B<3> ECLK_B<4> WL_O<63> WL_O<62> WL_O<61> WL_O<60> WL_O<59> ++ WL_O<58> WL_O<57> WL_O<56> WL_O<55> WL_O<54> WL_O<53> WL_O<52> WL_O<51> ++ WL_O<50> WL_O<49> WL_O<48> VDD VSS / RM_IHPSG13_512x8_c2_2P_DEC04 +XSEL<2> ADDR_N_I<3> ADDR_N_I<2> ADDR_N_I<1> ADDR_N_I<0> CS00<2> ECLK_H<2> ++ ECLK_H<3> ECLK_B<2> ECLK_B<3> WL_O<47> WL_O<46> WL_O<45> WL_O<44> WL_O<43> ++ WL_O<42> WL_O<41> WL_O<40> WL_O<39> WL_O<38> WL_O<37> WL_O<36> WL_O<35> ++ WL_O<34> WL_O<33> WL_O<32> VDD VSS / RM_IHPSG13_512x8_c2_2P_DEC04 +XSEL<1> ADDR_N_I<3> ADDR_N_I<2> ADDR_N_I<1> ADDR_N_I<0> CS00<1> ECLK_H<1> ++ ECLK_H<2> ECLK_B<1> ECLK_B<2> WL_O<31> WL_O<30> WL_O<29> WL_O<28> WL_O<27> ++ WL_O<26> WL_O<25> WL_O<24> WL_O<23> WL_O<22> WL_O<21> WL_O<20> WL_O<19> ++ WL_O<18> WL_O<17> WL_O<16> VDD VSS / RM_IHPSG13_512x8_c2_2P_DEC04 +XSEL<0> ADDR_N_I<3> ADDR_N_I<2> ADDR_N_I<1> ADDR_N_I<0> CS00<0> ECLK_I ++ ECLK_H<1> ECLK_B<0> ECLK_B<1> WL_O<15> WL_O<14> WL_O<13> WL_O<12> WL_O<11> ++ WL_O<10> WL_O<9> WL_O<8> WL_O<7> WL_O<6> WL_O<5> WL_O<4> WL_O<3> WL_O<2> ++ WL_O<1> WL_O<0> VDD VSS / RM_IHPSG13_512x8_c2_2P_DEC04 +XDEC10<4> ADDR_N_I<7> ADDR_N_I<6> CS_I CS04<2> VDD VSS / ++ RM_IHPSG13_512x8_c2_2P_DEC02 +XDEC10<3> ADDR_N_I<5> ADDR_N_I<4> CS04<3> CS00<14> VDD VSS / ++ RM_IHPSG13_512x8_c2_2P_DEC02 +XDEC10<2> ADDR_N_I<5> ADDR_N_I<4> CS04<2> CS00<10> VDD VSS / ++ RM_IHPSG13_512x8_c2_2P_DEC02 +XDEC10<1> ADDR_N_I<5> ADDR_N_I<4> CS04<1> CS00<6> VDD VSS / ++ RM_IHPSG13_512x8_c2_2P_DEC02 +XDEC10<0> ADDR_N_I<5> ADDR_N_I<4> CS04<0> CS00<2> VDD VSS / ++ RM_IHPSG13_512x8_c2_2P_DEC02 +XL2<132> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<131> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<130> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<129> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<128> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<127> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<126> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<125> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<124> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<123> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<122> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<121> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<120> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<119> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<118> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<117> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<116> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<115> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<114> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<113> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<112> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<111> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<110> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<109> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<108> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<107> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<106> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<105> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<104> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<103> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<102> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<101> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<100> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<99> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<98> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<97> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<96> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<95> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<94> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<93> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<92> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<91> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<90> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<89> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<88> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<87> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<86> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<85> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<84> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<83> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<82> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<81> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<80> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<79> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<78> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<77> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<76> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<75> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<74> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<73> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<72> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<71> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<70> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<69> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<68> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<67> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<66> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<65> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<64> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<63> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<62> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<61> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<60> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<59> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<58> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<57> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<56> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<55> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<54> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<53> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<52> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<51> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<50> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<49> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<48> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<47> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<46> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<45> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<44> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<43> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<42> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<41> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<40> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<39> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<38> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<37> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<36> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<35> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<34> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<33> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<32> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<31> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<30> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<29> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<28> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<27> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<26> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<25> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<24> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<23> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<22> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<21> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<20> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<19> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<18> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<17> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<16> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<15> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<14> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<13> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<12> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<11> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<10> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<9> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<8> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<7> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<6> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<5> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<4> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<3> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<2> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<1> VDD VSS / RSC_IHPSG13_FILLCAP8 +XDEC00<4> ADDR_N_I<7> ADDR_N_I<6> CS_I CS04<0> VDD VSS / ++ RM_IHPSG13_512x8_c2_2P_DEC00 +XDEC00<3> ADDR_N_I<5> ADDR_N_I<4> CS04<3> CS00<12> VDD VSS / ++ RM_IHPSG13_512x8_c2_2P_DEC00 +XDEC00<2> ADDR_N_I<5> ADDR_N_I<4> CS04<2> CS00<8> VDD VSS / ++ RM_IHPSG13_512x8_c2_2P_DEC00 +XDEC00<1> ADDR_N_I<5> ADDR_N_I<4> CS04<1> CS00<4> VDD VSS / ++ RM_IHPSG13_512x8_c2_2P_DEC00 +XDEC00<0> ADDR_N_I<5> ADDR_N_I<4> CS04<0> CS00<0> VDD VSS / ++ RM_IHPSG13_512x8_c2_2P_DEC00 +XDEC01<4> ADDR_N_I<7> ADDR_N_I<6> CS_I CS04<1> VDD VSS / ++ RM_IHPSG13_512x8_c2_2P_DEC01 +XDEC01<3> ADDR_N_I<5> ADDR_N_I<4> CS04<3> CS00<13> VDD VSS / ++ RM_IHPSG13_512x8_c2_2P_DEC01 +XDEC01<2> ADDR_N_I<5> ADDR_N_I<4> CS04<2> CS00<9> VDD VSS / ++ RM_IHPSG13_512x8_c2_2P_DEC01 +XDEC01<1> ADDR_N_I<5> ADDR_N_I<4> CS04<1> CS00<5> VDD VSS / ++ RM_IHPSG13_512x8_c2_2P_DEC01 +XDEC01<0> ADDR_N_I<5> ADDR_N_I<4> CS04<0> CS00<1> VDD VSS / ++ RM_IHPSG13_512x8_c2_2P_DEC01 +.ENDS +.SUBCKT RM_IHPSG13_512x8_c2_2P_ROWREG8 ACLK_N_I ADDR_I<7> ADDR_I<6> ADDR_I<5> ADDR_I<4> ++ ADDR_I<3> ADDR_I<2> ADDR_I<1> ADDR_I<0> ADDR_N_O<7> ADDR_N_O<6> ADDR_N_O<5> ++ ADDR_N_O<4> ADDR_N_O<3> ADDR_N_O<2> ADDR_N_O<1> ADDR_N_O<0> BIST_ADDR_I<7> ++ BIST_ADDR_I<6> BIST_ADDR_I<5> BIST_ADDR_I<4> BIST_ADDR_I<3> BIST_ADDR_I<2> ++ BIST_ADDR_I<1> BIST_ADDR_I<0> BIST_EN_I VDD VSS +XINV<7> q_int<7> qn_int<7> VDD VSS / RSC_IHPSG13_CINVX2 +XINV<6> q_int<6> qn_int<6> VDD VSS / RSC_IHPSG13_CINVX2 +XINV<5> q_int<5> qn_int<5> VDD VSS / RSC_IHPSG13_CINVX2 +XINV<4> q_int<4> qn_int<4> VDD VSS / RSC_IHPSG13_CINVX2 +XINV<3> q_int<3> qn_int<3> VDD VSS / RSC_IHPSG13_CINVX2 +XINV<2> q_int<2> qn_int<2> VDD VSS / RSC_IHPSG13_CINVX2 +XINV<1> q_int<1> qn_int<1> VDD VSS / RSC_IHPSG13_CINVX2 +XINV<0> q_int<0> qn_int<0> VDD VSS / RSC_IHPSG13_CINVX2 +XDRV<7> qn_int<7> ADDR_N_O<7> VDD VSS / RSC_IHPSG13_CINVX8 +XDRV<6> qn_int<6> ADDR_N_O<6> VDD VSS / RSC_IHPSG13_CINVX8 +XDRV<5> qn_int<5> ADDR_N_O<5> VDD VSS / RSC_IHPSG13_CINVX8 +XDRV<4> qn_int<4> ADDR_N_O<4> VDD VSS / RSC_IHPSG13_CINVX8 +XDRV<3> qn_int<3> ADDR_N_O<3> VDD VSS / RSC_IHPSG13_CINVX8 +XDRV<2> qn_int<2> ADDR_N_O<2> VDD VSS / RSC_IHPSG13_CINVX8 +XDRV<1> qn_int<1> ADDR_N_O<1> VDD VSS / RSC_IHPSG13_CINVX8 +XDRV<0> qn_int<0> ADDR_N_O<0> VDD VSS / RSC_IHPSG13_CINVX8 +XDFF<7> BIST_EN_I BIST_ADDR_I<7> ACLK_N_I ADDR_I<7> q_int<7> net2<0> VDD ++ VSS / RSC_IHPSG13_DFNQMX2IX1 +XDFF<6> BIST_EN_I BIST_ADDR_I<6> ACLK_N_I ADDR_I<6> q_int<6> net2<1> VDD ++ VSS / RSC_IHPSG13_DFNQMX2IX1 +XDFF<5> BIST_EN_I BIST_ADDR_I<5> ACLK_N_I ADDR_I<5> q_int<5> net2<2> VDD ++ VSS / RSC_IHPSG13_DFNQMX2IX1 +XDFF<4> BIST_EN_I BIST_ADDR_I<4> ACLK_N_I ADDR_I<4> q_int<4> net2<3> VDD ++ VSS / RSC_IHPSG13_DFNQMX2IX1 +XDFF<3> BIST_EN_I BIST_ADDR_I<3> ACLK_N_I ADDR_I<3> q_int<3> net2<4> VDD ++ VSS / RSC_IHPSG13_DFNQMX2IX1 +XDFF<2> BIST_EN_I BIST_ADDR_I<2> ACLK_N_I ADDR_I<2> q_int<2> net2<5> VDD ++ VSS / RSC_IHPSG13_DFNQMX2IX1 +XDFF<1> BIST_EN_I BIST_ADDR_I<1> ACLK_N_I ADDR_I<1> q_int<1> net2<6> VDD ++ VSS / RSC_IHPSG13_DFNQMX2IX1 +XDFF<0> BIST_EN_I BIST_ADDR_I<0> ACLK_N_I ADDR_I<0> q_int<0> net2<7> VDD ++ VSS / RSC_IHPSG13_DFNQMX2IX1 +XI11<4> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI11<3> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI11<2> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI11<1> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI10 VDD VSS / RSC_IHPSG13_FILLCAP4 +.ENDS +.SUBCKT RM_IHPSG13_512x8_c2_2P_COLDEC4 ACLK_N ADDR<3> ADDR<2> ADDR<1> ADDR<0> ++ ADDR_COL<1> ADDR_COL<0> ADDR_DEC<7> ADDR_DEC<6> ADDR_DEC<5> ADDR_DEC<4> ++ ADDR_DEC<3> ADDR_DEC<2> ADDR_DEC<1> ADDR_DEC<0> BIST_ADDR<3> BIST_ADDR<2> ++ BIST_ADDR<1> BIST_ADDR<0> BIST_EN_I VDD VSS +XI1<7> PADR<0> PADR<1> PADR<2> addr_n<7> VDD VSS / RSC_IHPSG13_NAND3X2 +XI1<6> NADR<0> PADR<1> PADR<2> addr_n<6> VDD VSS / RSC_IHPSG13_NAND3X2 +XI1<5> PADR<0> NADR<1> PADR<2> addr_n<5> VDD VSS / RSC_IHPSG13_NAND3X2 +XI1<4> NADR<0> NADR<1> PADR<2> addr_n<4> VDD VSS / RSC_IHPSG13_NAND3X2 +XI1<3> PADR<0> PADR<1> NADR<2> addr_n<3> VDD VSS / RSC_IHPSG13_NAND3X2 +XI1<2> NADR<0> PADR<1> NADR<2> addr_n<2> VDD VSS / RSC_IHPSG13_NAND3X2 +XI1<1> PADR<0> NADR<1> NADR<2> addr_n<1> VDD VSS / RSC_IHPSG13_NAND3X2 +XI1<0> NADR<0> NADR<1> NADR<2> addr_n<0> VDD VSS / RSC_IHPSG13_NAND3X2 +XDFF<3> BIST_EN_I BIST_ADDR<3> ACLK_N ADDR<3> addr_int net12<0> VDD ++ VSS / RSC_IHPSG13_DFNQMX2IX1 +XDFF<2> BIST_EN_I BIST_ADDR<2> ACLK_N ADDR<2> padr_int<2> net12<1> VDD ++ VSS / RSC_IHPSG13_DFNQMX2IX1 +XDFF<1> BIST_EN_I BIST_ADDR<1> ACLK_N ADDR<1> padr_int<1> net12<2> VDD ++ VSS / RSC_IHPSG13_DFNQMX2IX1 +XDFF<0> BIST_EN_I BIST_ADDR<0> ACLK_N ADDR<0> padr_int<0> net12<3> VDD ++ VSS / RSC_IHPSG13_DFNQMX2IX1 +XI17<4> VDD VSS / RSC_IHPSG13_FILLCAP4 +XI17<3> VDD VSS / RSC_IHPSG13_FILLCAP4 +XI17<2> VDD VSS / RSC_IHPSG13_FILLCAP4 +XI17<1> VDD VSS / RSC_IHPSG13_FILLCAP4 +XI13<2> NADR<2> PADR<2> VDD VSS / RSC_IHPSG13_INVX2 +XI13<1> NADR<1> PADR<1> VDD VSS / RSC_IHPSG13_INVX2 +XI13<0> NADR<0> PADR<0> VDD VSS / RSC_IHPSG13_INVX2 +XI2<7> addr_n<7> ADDR_DEC<7> VDD VSS / RSC_IHPSG13_INVX2 +XI2<6> addr_n<6> ADDR_DEC<6> VDD VSS / RSC_IHPSG13_INVX2 +XI2<5> addr_n<5> ADDR_DEC<5> VDD VSS / RSC_IHPSG13_INVX2 +XI2<4> addr_n<4> ADDR_DEC<4> VDD VSS / RSC_IHPSG13_INVX2 +XI2<3> addr_n<3> ADDR_DEC<3> VDD VSS / RSC_IHPSG13_INVX2 +XI2<2> addr_n<2> ADDR_DEC<2> VDD VSS / RSC_IHPSG13_INVX2 +XI2<1> addr_n<1> ADDR_DEC<1> VDD VSS / RSC_IHPSG13_INVX2 +XI2<0> addr_n<0> ADDR_DEC<0> VDD VSS / RSC_IHPSG13_INVX2 +XI3<2> padr_int<2> NADR<2> VDD VSS / RSC_IHPSG13_INVX2 +XI3<1> padr_int<1> NADR<1> VDD VSS / RSC_IHPSG13_INVX2 +XI3<0> padr_int<0> NADR<0> VDD VSS / RSC_IHPSG13_INVX2 +XI14 addr_int ADDR_COL<0> VDD VSS / RSC_IHPSG13_CBUFX2 +XI16<8> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI16<7> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI16<6> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI16<5> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI16<4> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI16<3> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI16<2> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI16<1> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI15 ADDR_COL<1> VDD VSS / RSC_IHPSG13_TIEL +.ENDS +.SUBCKT RM_IHPSG13_512x8_c2_2P_COLCTRL4 A_ADDR_COL A_ADDR_DEC<7> A_ADDR_DEC<6> ++ A_ADDR_DEC<5> A_ADDR_DEC<4> A_ADDR_DEC<3> A_ADDR_DEC<2> A_ADDR_DEC<1> ++ A_ADDR_DEC<0> A_BIST_BM_I A_BIST_DW_I A_BIST_EN_I A_BLC<15> A_BLC<14> ++ A_BLC<13> A_BLC<12> A_BLC<11> A_BLC<10> A_BLC<9> A_BLC<8> A_BLC<7> A_BLC<6> ++ A_BLC<5> A_BLC<4> A_BLC<3> A_BLC<2> A_BLC<1> A_BLC<0> A_BLT<15> A_BLT<14> ++ A_BLT<13> A_BLT<12> A_BLT<11> A_BLT<10> A_BLT<9> A_BLT<8> A_BLT<7> A_BLT<6> ++ A_BLT<5> A_BLT<4> A_BLT<3> A_BLT<2> A_BLT<1> A_BLT<0> A_BM_I A_DCLK_B_L ++ A_DCLK_B_R A_DCLK_L A_DCLK_R A_DR_O A_DW_I A_RCLK_B_L A_RCLK_B_R A_RCLK_L ++ A_RCLK_R A_TIEH_O A_WCLK_B_L A_WCLK_B_R A_WCLK_L A_WCLK_R B_ADDR_COL ++ B_ADDR_DEC<7> B_ADDR_DEC<6> B_ADDR_DEC<5> B_ADDR_DEC<4> B_ADDR_DEC<3> ++ B_ADDR_DEC<2> B_ADDR_DEC<1> B_ADDR_DEC<0> B_BIST_BM_I B_BIST_DW_I ++ B_BIST_EN_I B_BLC<15> B_BLC<14> B_BLC<13> B_BLC<12> B_BLC<11> B_BLC<10> ++ B_BLC<9> B_BLC<8> B_BLC<7> B_BLC<6> B_BLC<5> B_BLC<4> B_BLC<3> B_BLC<2> ++ B_BLC<1> B_BLC<0> B_BLT<15> B_BLT<14> B_BLT<13> B_BLT<12> B_BLT<11> ++ B_BLT<10> B_BLT<9> B_BLT<8> B_BLT<7> B_BLT<6> B_BLT<5> B_BLT<4> B_BLT<3> ++ B_BLT<2> B_BLT<1> B_BLT<0> B_BM_I B_DCLK_B_L B_DCLK_B_R B_DCLK_L B_DCLK_R ++ B_DR_O B_DW_I B_RCLK_B_L B_RCLK_B_R B_RCLK_L B_RCLK_R B_TIEH_O B_WCLK_B_L ++ B_WCLK_B_R B_WCLK_L B_WCLK_R VDD VSS +XB_I80 B_RCLK_B_L B_WCLK_B_L net041 VDD VSS / RSC_IHPSG13_AND2X2 +XA_I80 A_RCLK_B_L A_WCLK_B_L net21 VDD VSS / RSC_IHPSG13_AND2X2 +XB_I76 B_DI_N B_DO_WRITE_P B_WR_ZERO VDD VSS / RSC_IHPSG13_AND2X4 +XB_I75 B_DI_R B_DO_WRITE_P B_WR_ONE VDD VSS / RSC_IHPSG13_AND2X4 +XA_I76 A_DI_N A_DO_WRITE_P A_WR_ZERO VDD VSS / RSC_IHPSG13_AND2X4 +XA_I75 A_DI_R A_DO_WRITE_P A_WR_ONE VDD VSS / RSC_IHPSG13_AND2X4 +XI_FILL4<26> VDD VSS / RSC_IHPSG13_FILLCAP4 +XI_FILL4<25> VDD VSS / RSC_IHPSG13_FILLCAP4 +XI_FILL4<24> VDD VSS / RSC_IHPSG13_FILLCAP4 +XI_FILL4<23> VDD VSS / RSC_IHPSG13_FILLCAP4 +XI_FILL4<22> VDD VSS / RSC_IHPSG13_FILLCAP4 +XI_FILL4<21> VDD VSS / RSC_IHPSG13_FILLCAP4 +XI_FILL4<20> VDD VSS / RSC_IHPSG13_FILLCAP4 +XI_FILL4<19> VDD VSS / RSC_IHPSG13_FILLCAP4 +XI_FILL4<18> VDD VSS / RSC_IHPSG13_FILLCAP4 +XI_FILL4<17> VDD VSS / RSC_IHPSG13_FILLCAP4 +XI_FILL4<16> VDD VSS / RSC_IHPSG13_FILLCAP4 +XI_FILL4<15> VDD VSS / RSC_IHPSG13_FILLCAP4 +XI_FILL4<14> VDD VSS / RSC_IHPSG13_FILLCAP4 +XI_FILL4<13> VDD VSS / RSC_IHPSG13_FILLCAP4 +XI_FILL4<12> VDD VSS / RSC_IHPSG13_FILLCAP4 +XI_FILL4<11> VDD VSS / RSC_IHPSG13_FILLCAP4 +XI_FILL4<10> VDD VSS / RSC_IHPSG13_FILLCAP4 +XI_FILL4<9> VDD VSS / RSC_IHPSG13_FILLCAP4 +XI_FILL4<8> VDD VSS / RSC_IHPSG13_FILLCAP4 +XI_FILL4<7> VDD VSS / RSC_IHPSG13_FILLCAP4 +XI_FILL4<6> VDD VSS / RSC_IHPSG13_FILLCAP4 +XI_FILL4<5> VDD VSS / RSC_IHPSG13_FILLCAP4 +XI_FILL4<4> VDD VSS / RSC_IHPSG13_FILLCAP4 +XI_FILL4<3> VDD VSS / RSC_IHPSG13_FILLCAP4 +XI_FILL4<2> VDD VSS / RSC_IHPSG13_FILLCAP4 +XI_FILL4<1> VDD VSS / RSC_IHPSG13_FILLCAP4 +XB_I69 B_DCLK_L B_DCLK_B_L VDD VSS / RSC_IHPSG13_CINVX4 +XB_I50 B_WCLK_L B_WCLK_B_L VDD VSS / RSC_IHPSG13_CINVX4 +XB_EBUF B_RCLK_L B_RCLK_B_L VDD VSS / RSC_IHPSG13_CINVX4 +XB_INV<1> B_N0 B_P0 VDD VSS / RSC_IHPSG13_CINVX4 +XB_INV<0> B_ADDR_COL B_N0 VDD VSS / RSC_IHPSG13_CINVX4 +XA_I69 A_DCLK_L A_DCLK_B_L VDD VSS / RSC_IHPSG13_CINVX4 +XA_I50 A_WCLK_L A_WCLK_B_L VDD VSS / RSC_IHPSG13_CINVX4 +XA_EBUF A_RCLK_L A_RCLK_B_L VDD VSS / RSC_IHPSG13_CINVX4 +XA_INV<1> A_N0 A_P0 VDD VSS / RSC_IHPSG13_CINVX4 +XA_INV<0> A_ADDR_COL A_N0 VDD VSS / RSC_IHPSG13_CINVX4 +XB_I81<1> net041 B_PRE_N VDD VSS / RSC_IHPSG13_CINVX4_WN +XB_I81<0> net041 B_PRE_N VDD VSS / RSC_IHPSG13_CINVX4_WN +XA_I81<1> net21 A_PRE_N VDD VSS / RSC_IHPSG13_CINVX4_WN +XA_I81<0> net21 A_PRE_N VDD VSS / RSC_IHPSG13_CINVX4_WN +XA_R2 A_RCLK_L A_RCLK_R / RSC_IHPSG13_MET3RES +XA_I87 A_WCLK_L A_WCLK_R / RSC_IHPSG13_MET3RES +XA_I88 A_DCLK_L A_DCLK_R / RSC_IHPSG13_MET3RES +XA_I89 A_DCLK_B_L A_DCLK_B_R / RSC_IHPSG13_MET3RES +XA_I90 A_WCLK_B_L A_WCLK_B_R / RSC_IHPSG13_MET3RES +XA_I91 A_RCLK_B_L A_RCLK_B_R / RSC_IHPSG13_MET3RES +XB_R2 B_RCLK_L B_RCLK_R / RSC_IHPSG13_MET3RES +XB_I87 B_WCLK_L B_WCLK_R / RSC_IHPSG13_MET3RES +XB_I88 B_DCLK_L B_DCLK_R / RSC_IHPSG13_MET3RES +XB_I89 B_DCLK_B_L B_DCLK_B_R / RSC_IHPSG13_MET3RES +XB_I90 B_WCLK_B_L B_WCLK_B_R / RSC_IHPSG13_MET3RES +XB_I91 B_RCLK_B_L B_RCLK_B_R / RSC_IHPSG13_MET3RES +XA_ISENSE A_SAE A_BLC_SEL A_BLT_SEL net19 net20 VDD VSS / ++ RSC_IHPSG13_DFPQD_MSAFFX2 +XB_ISENSE B_SAE B_BLC_SEL B_BLT_SEL net037 net038 VDD VSS / ++ RSC_IHPSG13_DFPQD_MSAFFX2 +XAB_BLMUX<3> A_BLC<15> A_BLC<14> A_BLC<13> A_BLC<12> A_BLC_SEL A_BLT<15> ++ A_BLT<14> A_BLT<13> A_BLT<12> A_BLT_SEL A_PRE_N A_SEL_P<15> A_SEL_P<14> ++ A_SEL_P<13> A_SEL_P<12> A_WR_ONE A_WR_ZERO B_BLC<15> B_BLC<14> B_BLC<13> ++ B_BLC<12> B_BLC_SEL B_BLT<15> B_BLT<14> B_BLT<13> B_BLT<12> B_BLT_SEL ++ B_PRE_N B_SEL_P<15> B_SEL_P<14> B_SEL_P<13> B_SEL_P<12> B_WR_ONE B_WR_ZERO ++ VDD VSS / RM_IHPSG13_512x8_c2_2P_BLDRV +XAB_BLMUX<2> A_BLC<11> A_BLC<10> A_BLC<9> A_BLC<8> A_BLC_SEL A_BLT<11> ++ A_BLT<10> A_BLT<9> A_BLT<8> A_BLT_SEL A_PRE_N A_SEL_P<11> A_SEL_P<10> ++ A_SEL_P<9> A_SEL_P<8> A_WR_ONE A_WR_ZERO B_BLC<11> B_BLC<10> B_BLC<9> ++ B_BLC<8> B_BLC_SEL B_BLT<11> B_BLT<10> B_BLT<9> B_BLT<8> B_BLT_SEL B_PRE_N ++ B_SEL_P<11> B_SEL_P<10> B_SEL_P<9> B_SEL_P<8> B_WR_ONE B_WR_ZERO VDD ++ VSS / RM_IHPSG13_512x8_c2_2P_BLDRV +XAB_BLMUX<1> A_BLC<7> A_BLC<6> A_BLC<5> A_BLC<4> A_BLC_SEL A_BLT<7> A_BLT<6> ++ A_BLT<5> A_BLT<4> A_BLT_SEL A_PRE_N A_SEL_P<7> A_SEL_P<6> A_SEL_P<5> ++ A_SEL_P<4> A_WR_ONE A_WR_ZERO B_BLC<7> B_BLC<6> B_BLC<5> B_BLC<4> B_BLC_SEL ++ B_BLT<7> B_BLT<6> B_BLT<5> B_BLT<4> B_BLT_SEL B_PRE_N B_SEL_P<7> B_SEL_P<6> ++ B_SEL_P<5> B_SEL_P<4> B_WR_ONE B_WR_ZERO VDD VSS / ++ RM_IHPSG13_512x8_c2_2P_BLDRV +XAB_BLMUX<0> A_BLC<3> A_BLC<2> A_BLC<1> A_BLC<0> A_BLC_SEL A_BLT<3> A_BLT<2> ++ A_BLT<1> A_BLT<0> A_BLT_SEL A_PRE_N A_SEL_P<3> A_SEL_P<2> A_SEL_P<1> ++ A_SEL_P<0> A_WR_ONE A_WR_ZERO B_BLC<3> B_BLC<2> B_BLC<1> B_BLC<0> B_BLC_SEL ++ B_BLT<3> B_BLT<2> B_BLT<1> B_BLT<0> B_BLT_SEL B_PRE_N B_SEL_P<3> B_SEL_P<2> ++ B_SEL_P<1> B_SEL_P<0> B_WR_ONE B_WR_ZERO VDD VSS / ++ RM_IHPSG13_512x8_c2_2P_BLDRV +XA_I51 net19 A_DR_O VDD VSS / RSC_IHPSG13_INVX4 +XB_I51 net037 B_DR_O VDD VSS / RSC_IHPSG13_INVX4 +XA_I78 A_RCLK_B_L A_SAE VDD VSS / RSC_IHPSG13_CBUFX2 +XB_I78 B_RCLK_B_L B_SAE VDD VSS / RSC_IHPSG13_CBUFX2 +XA_DREG A_BIST_EN_I A_BIST_DW_I A_DCLK_B_L A_DW_I A_DI_R net22 VDD VSS ++ / RSC_IHPSG13_DFNQMX2IX1 +XB_DREG B_BIST_EN_I B_BIST_DW_I B_DCLK_B_L B_DW_I B_DI_R net046 VDD ++ VSS / RSC_IHPSG13_DFNQMX2IX1 +XB_BREG B_BIST_EN_I B_BIST_BM_I B_DCLK_B_L B_BM_I B_BM_R net045 VDD ++ VSS / RSC_IHPSG13_DFNQMX2IX1 +XA_BREG A_BIST_EN_I A_BIST_BM_I A_DCLK_B_L A_BM_I A_BM_R net24 VDD VSS ++ / RSC_IHPSG13_DFNQMX2IX1 +XA_DEC3INV<15> net23<0> A_SEL_P<15> VDD VSS / RSC_IHPSG13_INVX2 +XA_DEC3INV<14> net23<1> A_SEL_P<14> VDD VSS / RSC_IHPSG13_INVX2 +XA_DEC3INV<13> net23<2> A_SEL_P<13> VDD VSS / RSC_IHPSG13_INVX2 +XA_DEC3INV<12> net23<3> A_SEL_P<12> VDD VSS / RSC_IHPSG13_INVX2 +XA_DEC3INV<11> net23<4> A_SEL_P<11> VDD VSS / RSC_IHPSG13_INVX2 +XA_DEC3INV<10> net23<5> A_SEL_P<10> VDD VSS / RSC_IHPSG13_INVX2 +XA_DEC3INV<9> net23<6> A_SEL_P<9> VDD VSS / RSC_IHPSG13_INVX2 +XA_DEC3INV<8> net23<7> A_SEL_P<8> VDD VSS / RSC_IHPSG13_INVX2 +XA_DEC3INV<7> net23<8> A_SEL_P<7> VDD VSS / RSC_IHPSG13_INVX2 +XA_DEC3INV<6> net23<9> A_SEL_P<6> VDD VSS / RSC_IHPSG13_INVX2 +XA_DEC3INV<5> net23<10> A_SEL_P<5> VDD VSS / RSC_IHPSG13_INVX2 +XA_DEC3INV<4> net23<11> A_SEL_P<4> VDD VSS / RSC_IHPSG13_INVX2 +XA_DEC3INV<3> net23<12> A_SEL_P<3> VDD VSS / RSC_IHPSG13_INVX2 +XA_DEC3INV<2> net23<13> A_SEL_P<2> VDD VSS / RSC_IHPSG13_INVX2 +XA_DEC3INV<1> net23<14> A_SEL_P<1> VDD VSS / RSC_IHPSG13_INVX2 +XA_DEC3INV<0> net23<15> A_SEL_P<0> VDD VSS / RSC_IHPSG13_INVX2 +XA_I83 A_BM_R A_BM_N VDD VSS / RSC_IHPSG13_INVX2 +XA_I49 A_DI_R A_DI_N VDD VSS / RSC_IHPSG13_INVX2 +XB_DEC3INV<15> net044<0> B_SEL_P<15> VDD VSS / RSC_IHPSG13_INVX2 +XB_DEC3INV<14> net044<1> B_SEL_P<14> VDD VSS / RSC_IHPSG13_INVX2 +XB_DEC3INV<13> net044<2> B_SEL_P<13> VDD VSS / RSC_IHPSG13_INVX2 +XB_DEC3INV<12> net044<3> B_SEL_P<12> VDD VSS / RSC_IHPSG13_INVX2 +XB_DEC3INV<11> net044<4> B_SEL_P<11> VDD VSS / RSC_IHPSG13_INVX2 +XB_DEC3INV<10> net044<5> B_SEL_P<10> VDD VSS / RSC_IHPSG13_INVX2 +XB_DEC3INV<9> net044<6> B_SEL_P<9> VDD VSS / RSC_IHPSG13_INVX2 +XB_DEC3INV<8> net044<7> B_SEL_P<8> VDD VSS / RSC_IHPSG13_INVX2 +XB_DEC3INV<7> net044<8> B_SEL_P<7> VDD VSS / RSC_IHPSG13_INVX2 +XB_DEC3INV<6> net044<9> B_SEL_P<6> VDD VSS / RSC_IHPSG13_INVX2 +XB_DEC3INV<5> net044<10> B_SEL_P<5> VDD VSS / RSC_IHPSG13_INVX2 +XB_DEC3INV<4> net044<11> B_SEL_P<4> VDD VSS / RSC_IHPSG13_INVX2 +XB_DEC3INV<3> net044<12> B_SEL_P<3> VDD VSS / RSC_IHPSG13_INVX2 +XB_DEC3INV<2> net044<13> B_SEL_P<2> VDD VSS / RSC_IHPSG13_INVX2 +XB_DEC3INV<1> net044<14> B_SEL_P<1> VDD VSS / RSC_IHPSG13_INVX2 +XB_DEC3INV<0> net044<15> B_SEL_P<0> VDD VSS / RSC_IHPSG13_INVX2 +XB_I83 B_BM_R B_BM_N VDD VSS / RSC_IHPSG13_INVX2 +XB_I49 B_DI_R B_DI_N VDD VSS / RSC_IHPSG13_INVX2 +XI_FILL8<20> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI_FILL8<19> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI_FILL8<18> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI_FILL8<17> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI_FILL8<16> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI_FILL8<15> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI_FILL8<14> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI_FILL8<13> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI_FILL8<12> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI_FILL8<11> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI_FILL8<10> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI_FILL8<9> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI_FILL8<8> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI_FILL8<7> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI_FILL8<6> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI_FILL8<5> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI_FILL8<4> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI_FILL8<3> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI_FILL8<2> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI_FILL8<1> VDD VSS / RSC_IHPSG13_FILLCAP8 +XA_I44 A_BM_N A_WCLK_B_L A_DO_WRITE_P VDD VSS / RSC_IHPSG13_NOR2X2 +XB_I44 B_BM_N B_WCLK_B_L B_DO_WRITE_P VDD VSS / RSC_IHPSG13_NOR2X2 +XA_DEC3<15> A_P0 A_ADDR_DEC<7> net23<0> VDD VSS / RSC_IHPSG13_NAND2X2 +XA_DEC3<14> A_P0 A_ADDR_DEC<6> net23<1> VDD VSS / RSC_IHPSG13_NAND2X2 +XA_DEC3<13> A_P0 A_ADDR_DEC<5> net23<2> VDD VSS / RSC_IHPSG13_NAND2X2 +XA_DEC3<12> A_P0 A_ADDR_DEC<4> net23<3> VDD VSS / RSC_IHPSG13_NAND2X2 +XA_DEC3<11> A_P0 A_ADDR_DEC<3> net23<4> VDD VSS / RSC_IHPSG13_NAND2X2 +XA_DEC3<10> A_P0 A_ADDR_DEC<2> net23<5> VDD VSS / RSC_IHPSG13_NAND2X2 +XA_DEC3<9> A_P0 A_ADDR_DEC<1> net23<6> VDD VSS / RSC_IHPSG13_NAND2X2 +XA_DEC3<8> A_P0 A_ADDR_DEC<0> net23<7> VDD VSS / RSC_IHPSG13_NAND2X2 +XA_DEC3<7> A_N0 A_ADDR_DEC<7> net23<8> VDD VSS / RSC_IHPSG13_NAND2X2 +XA_DEC3<6> A_N0 A_ADDR_DEC<6> net23<9> VDD VSS / RSC_IHPSG13_NAND2X2 +XA_DEC3<5> A_N0 A_ADDR_DEC<5> net23<10> VDD VSS / RSC_IHPSG13_NAND2X2 +XA_DEC3<4> A_N0 A_ADDR_DEC<4> net23<11> VDD VSS / RSC_IHPSG13_NAND2X2 +XA_DEC3<3> A_N0 A_ADDR_DEC<3> net23<12> VDD VSS / RSC_IHPSG13_NAND2X2 +XA_DEC3<2> A_N0 A_ADDR_DEC<2> net23<13> VDD VSS / RSC_IHPSG13_NAND2X2 +XA_DEC3<1> A_N0 A_ADDR_DEC<1> net23<14> VDD VSS / RSC_IHPSG13_NAND2X2 +XA_DEC3<0> A_N0 A_ADDR_DEC<0> net23<15> VDD VSS / RSC_IHPSG13_NAND2X2 +XB_DEC3<15> B_P0 B_ADDR_DEC<7> net044<0> VDD VSS / RSC_IHPSG13_NAND2X2 +XB_DEC3<14> B_P0 B_ADDR_DEC<6> net044<1> VDD VSS / RSC_IHPSG13_NAND2X2 +XB_DEC3<13> B_P0 B_ADDR_DEC<5> net044<2> VDD VSS / RSC_IHPSG13_NAND2X2 +XB_DEC3<12> B_P0 B_ADDR_DEC<4> net044<3> VDD VSS / RSC_IHPSG13_NAND2X2 +XB_DEC3<11> B_P0 B_ADDR_DEC<3> net044<4> VDD VSS / RSC_IHPSG13_NAND2X2 +XB_DEC3<10> B_P0 B_ADDR_DEC<2> net044<5> VDD VSS / RSC_IHPSG13_NAND2X2 +XB_DEC3<9> B_P0 B_ADDR_DEC<1> net044<6> VDD VSS / RSC_IHPSG13_NAND2X2 +XB_DEC3<8> B_P0 B_ADDR_DEC<0> net044<7> VDD VSS / RSC_IHPSG13_NAND2X2 +XB_DEC3<7> B_N0 B_ADDR_DEC<7> net044<8> VDD VSS / RSC_IHPSG13_NAND2X2 +XB_DEC3<6> B_N0 B_ADDR_DEC<6> net044<9> VDD VSS / RSC_IHPSG13_NAND2X2 +XB_DEC3<5> B_N0 B_ADDR_DEC<5> net044<10> VDD VSS / RSC_IHPSG13_NAND2X2 +XB_DEC3<4> B_N0 B_ADDR_DEC<4> net044<11> VDD VSS / RSC_IHPSG13_NAND2X2 +XB_DEC3<3> B_N0 B_ADDR_DEC<3> net044<12> VDD VSS / RSC_IHPSG13_NAND2X2 +XB_DEC3<2> B_N0 B_ADDR_DEC<2> net044<13> VDD VSS / RSC_IHPSG13_NAND2X2 +XB_DEC3<1> B_N0 B_ADDR_DEC<1> net044<14> VDD VSS / RSC_IHPSG13_NAND2X2 +XB_DEC3<0> B_N0 B_ADDR_DEC<0> net044<15> VDD VSS / RSC_IHPSG13_NAND2X2 +XB_BM_TIEH B_TIEH_O VDD VSS / RSC_IHPSG13_TIEH +XA_BM_TIEH A_TIEH_O VDD VSS / RSC_IHPSG13_TIEH +.ENDS + + +.SUBCKT RM_IHPSG13_512x8_c2_2P_ROWDEC5 ADDR_N_I<4> ADDR_N_I<3> ADDR_N_I<2> ADDR_N_I<1> ++ ADDR_N_I<0> CS_I ECLK_I WL_O<31> WL_O<30> WL_O<29> WL_O<28> WL_O<27> ++ WL_O<26> WL_O<25> WL_O<24> WL_O<23> WL_O<22> WL_O<21> WL_O<20> WL_O<19> ++ WL_O<18> WL_O<17> WL_O<16> WL_O<15> WL_O<14> WL_O<13> WL_O<12> WL_O<11> ++ WL_O<10> WL_O<9> WL_O<8> WL_O<7> WL_O<6> WL_O<5> WL_O<4> WL_O<3> WL_O<2> ++ WL_O<1> WL_O<0> VDD VSS +XDEC00 ADDR_N_I<5> ADDR_N_I<4> CS_I CS00<0> VDD VSS / ++ RM_IHPSG13_512x8_c2_2P_DEC00 +XSEL<1> ADDR_N_I<3> ADDR_N_I<2> ADDR_N_I<1> ADDR_N_I<0> CS00<1> ECLK_H<1> ++ ECLK_H<2> ECLK_B<1> ECLK_B<2> WL_O<31> WL_O<30> WL_O<29> WL_O<28> WL_O<27> ++ WL_O<26> WL_O<25> WL_O<24> WL_O<23> WL_O<22> WL_O<21> WL_O<20> WL_O<19> ++ WL_O<18> WL_O<17> WL_O<16> VDD VSS / RM_IHPSG13_512x8_c2_2P_DEC04 +XSEL<0> ADDR_N_I<3> ADDR_N_I<2> ADDR_N_I<1> ADDR_N_I<0> CS00<0> ECLK_I ++ ECLK_H<1> ECLK_B<0> ECLK_B<1> WL_O<15> WL_O<14> WL_O<13> WL_O<12> WL_O<11> ++ WL_O<10> WL_O<9> WL_O<8> WL_O<7> WL_O<6> WL_O<5> WL_O<4> WL_O<3> WL_O<2> ++ WL_O<1> WL_O<0> VDD VSS / RM_IHPSG13_512x8_c2_2P_DEC04 +XDEC01 ADDR_N_I<5> ADDR_N_I<4> CS_I CS00<1> VDD VSS / ++ RM_IHPSG13_512x8_c2_2P_DEC01 +XL2<18> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<17> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<16> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<15> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<14> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<13> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<12> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<11> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<10> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<9> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<8> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<7> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<6> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<5> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<4> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<3> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<2> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<1> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI0 ADDR_N_I<5> VDD VSS / RSC_IHPSG13_TIEL +.ENDS +.SUBCKT RM_IHPSG13_512x8_c2_2P_ROWREG5 ACLK_N_I ADDR_I<4> ADDR_I<3> ADDR_I<2> ADDR_I<1> ++ ADDR_I<0> ADDR_N_O<4> ADDR_N_O<3> ADDR_N_O<2> ADDR_N_O<1> ADDR_N_O<0> ++ BIST_ADDR_I<4> BIST_ADDR_I<3> BIST_ADDR_I<2> BIST_ADDR_I<1> BIST_ADDR_I<0> ++ BIST_EN_I VDD VSS +XINV<4> q_int<4> qn_int<4> VDD VSS / RSC_IHPSG13_CINVX2 +XINV<3> q_int<3> qn_int<3> VDD VSS / RSC_IHPSG13_CINVX2 +XINV<2> q_int<2> qn_int<2> VDD VSS / RSC_IHPSG13_CINVX2 +XINV<1> q_int<1> qn_int<1> VDD VSS / RSC_IHPSG13_CINVX2 +XINV<0> q_int<0> qn_int<0> VDD VSS / RSC_IHPSG13_CINVX2 +XDRV<4> qn_int<4> ADDR_N_O<4> VDD VSS / RSC_IHPSG13_CINVX8 +XDRV<3> qn_int<3> ADDR_N_O<3> VDD VSS / RSC_IHPSG13_CINVX8 +XDRV<2> qn_int<2> ADDR_N_O<2> VDD VSS / RSC_IHPSG13_CINVX8 +XDRV<1> qn_int<1> ADDR_N_O<1> VDD VSS / RSC_IHPSG13_CINVX8 +XDRV<0> qn_int<0> ADDR_N_O<0> VDD VSS / RSC_IHPSG13_CINVX8 +XDFF<4> BIST_EN_I BIST_ADDR_I<4> ACLK_N_I ADDR_I<4> q_int<4> net2<0> VDD ++ VSS / RSC_IHPSG13_DFNQMX2IX1 +XDFF<3> BIST_EN_I BIST_ADDR_I<3> ACLK_N_I ADDR_I<3> q_int<3> net2<1> VDD ++ VSS / RSC_IHPSG13_DFNQMX2IX1 +XDFF<2> BIST_EN_I BIST_ADDR_I<2> ACLK_N_I ADDR_I<2> q_int<2> net2<2> VDD ++ VSS / RSC_IHPSG13_DFNQMX2IX1 +XDFF<1> BIST_EN_I BIST_ADDR_I<1> ACLK_N_I ADDR_I<1> q_int<1> net2<3> VDD ++ VSS / RSC_IHPSG13_DFNQMX2IX1 +XDFF<0> BIST_EN_I BIST_ADDR_I<0> ACLK_N_I ADDR_I<0> q_int<0> net2<4> VDD ++ VSS / RSC_IHPSG13_DFNQMX2IX1 +XI11<16> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI11<15> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI11<14> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI11<13> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI11<12> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI11<11> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI11<10> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI11<9> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI11<8> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI11<7> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI11<6> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI11<5> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI11<4> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI11<3> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI11<2> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI11<1> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI12<3> VDD VSS / RSC_IHPSG13_FILLCAP4 +XI12<2> VDD VSS / RSC_IHPSG13_FILLCAP4 +XI12<1> VDD VSS / RSC_IHPSG13_FILLCAP4 +XI12<0> VDD VSS / RSC_IHPSG13_FILLCAP4 +.ENDS + + +.SUBCKT RM_IHPSG13_512x8_c2_2P_COLDEC3 ACLK_N ADDR<2> ADDR<1> ADDR<0> ADDR_COL<1> ++ ADDR_COL<0> ADDR_DEC<7> ADDR_DEC<6> ADDR_DEC<5> ADDR_DEC<4> ADDR_DEC<3> ++ ADDR_DEC<2> ADDR_DEC<1> ADDR_DEC<0> BIST_ADDR<2> BIST_ADDR<1> BIST_ADDR<0> ++ BIST_EN_I VDD VSS +XI1<7> PADR<0> PADR<1> PADR<2> addr_n<7> VDD VSS / RSC_IHPSG13_NAND3X2 +XI1<6> NADR<0> PADR<1> PADR<2> addr_n<6> VDD VSS / RSC_IHPSG13_NAND3X2 +XI1<5> PADR<0> NADR<1> PADR<2> addr_n<5> VDD VSS / RSC_IHPSG13_NAND3X2 +XI1<4> NADR<0> NADR<1> PADR<2> addr_n<4> VDD VSS / RSC_IHPSG13_NAND3X2 +XI1<3> PADR<0> PADR<1> NADR<2> addr_n<3> VDD VSS / RSC_IHPSG13_NAND3X2 +XI1<2> NADR<0> PADR<1> NADR<2> addr_n<2> VDD VSS / RSC_IHPSG13_NAND3X2 +XI1<1> PADR<0> NADR<1> NADR<2> addr_n<1> VDD VSS / RSC_IHPSG13_NAND3X2 +XI1<0> NADR<0> NADR<1> NADR<2> addr_n<0> VDD VSS / RSC_IHPSG13_NAND3X2 +XDFF<2> BIST_EN_I BIST_ADDR<2> ACLK_N ADDR<2> padr_int<2> net13<0> VDD ++ VSS / RSC_IHPSG13_DFNQMX2IX1 +XDFF<1> BIST_EN_I BIST_ADDR<1> ACLK_N ADDR<1> padr_int<1> net13<1> VDD ++ VSS / RSC_IHPSG13_DFNQMX2IX1 +XDFF<0> BIST_EN_I BIST_ADDR<0> ACLK_N ADDR<0> padr_int<0> net13<2> VDD ++ VSS / RSC_IHPSG13_DFNQMX2IX1 +XI15<1> ADDR_COL<1> VDD VSS / RSC_IHPSG13_TIEL +XI15<0> ADDR_COL<0> VDD VSS / RSC_IHPSG13_TIEL +XI13<2> NADR<2> PADR<2> VDD VSS / RSC_IHPSG13_INVX2 +XI13<1> NADR<1> PADR<1> VDD VSS / RSC_IHPSG13_INVX2 +XI13<0> NADR<0> PADR<0> VDD VSS / RSC_IHPSG13_INVX2 +XI3<2> padr_int<2> NADR<2> VDD VSS / RSC_IHPSG13_INVX2 +XI3<1> padr_int<1> NADR<1> VDD VSS / RSC_IHPSG13_INVX2 +XI3<0> padr_int<0> NADR<0> VDD VSS / RSC_IHPSG13_INVX2 +XI2<7> addr_n<7> ADDR_DEC<7> VDD VSS / RSC_IHPSG13_INVX2 +XI2<6> addr_n<6> ADDR_DEC<6> VDD VSS / RSC_IHPSG13_INVX2 +XI2<5> addr_n<5> ADDR_DEC<5> VDD VSS / RSC_IHPSG13_INVX2 +XI2<4> addr_n<4> ADDR_DEC<4> VDD VSS / RSC_IHPSG13_INVX2 +XI2<3> addr_n<3> ADDR_DEC<3> VDD VSS / RSC_IHPSG13_INVX2 +XI2<2> addr_n<2> ADDR_DEC<2> VDD VSS / RSC_IHPSG13_INVX2 +XI2<1> addr_n<1> ADDR_DEC<1> VDD VSS / RSC_IHPSG13_INVX2 +XI2<0> addr_n<0> ADDR_DEC<0> VDD VSS / RSC_IHPSG13_INVX2 +XI17<4> VDD VSS / RSC_IHPSG13_FILLCAP4 +XI17<3> VDD VSS / RSC_IHPSG13_FILLCAP4 +XI17<2> VDD VSS / RSC_IHPSG13_FILLCAP4 +XI17<1> VDD VSS / RSC_IHPSG13_FILLCAP4 +XI16<11> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI16<10> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI16<9> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI16<8> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI16<7> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI16<6> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI16<5> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI16<4> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI16<3> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI16<2> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI16<1> VDD VSS / RSC_IHPSG13_FILLCAP8 +.ENDS +.SUBCKT RSC_IHPSG13_DFPQD_MSAFFX2P CP DN DP QN QP VDD VSS +XI_AMP CP DN DP QN QP VDD VSS / RSC_IHPSG13_DFPQD_MSAFFX2 +.ENDS +.SUBCKT RM_IHPSG13_512x8_c2_2P_COLCTRL3 A_ADDR_DEC<7> A_ADDR_DEC<6> A_ADDR_DEC<5> ++ A_ADDR_DEC<4> A_ADDR_DEC<3> A_ADDR_DEC<2> A_ADDR_DEC<1> A_ADDR_DEC<0> ++ A_BIST_BM_I A_BIST_DW_I A_BIST_EN_I A_BLC<7> A_BLC<6> A_BLC<5> A_BLC<4> ++ A_BLC<3> A_BLC<2> A_BLC<1> A_BLC<0> A_BLT<7> A_BLT<6> A_BLT<5> A_BLT<4> ++ A_BLT<3> A_BLT<2> A_BLT<1> A_BLT<0> A_BM_I A_DCLK_B_L A_DCLK_B_R A_DCLK_L ++ A_DCLK_R A_DR_O A_DW_I A_RCLK_B_L A_RCLK_B_R A_RCLK_L A_RCLK_R A_TIEH_O ++ A_WCLK_B_L A_WCLK_B_R A_WCLK_L A_WCLK_R B_ADDR_DEC<7> B_ADDR_DEC<6> ++ B_ADDR_DEC<5> B_ADDR_DEC<4> B_ADDR_DEC<3> B_ADDR_DEC<2> B_ADDR_DEC<1> ++ B_ADDR_DEC<0> B_BIST_BM_I B_BIST_DW_I B_BIST_EN_I B_BLC<7> B_BLC<6> B_BLC<5> ++ B_BLC<4> B_BLC<3> B_BLC<2> B_BLC<1> B_BLC<0> B_BLT<7> B_BLT<6> B_BLT<5> ++ B_BLT<4> B_BLT<3> B_BLT<2> B_BLT<1> B_BLT<0> B_BM_I B_DCLK_B_L B_DCLK_B_R ++ B_DCLK_L B_DCLK_R B_DR_O B_DW_I B_RCLK_B_L B_RCLK_B_R B_RCLK_L B_RCLK_R ++ B_TIEH_O B_WCLK_B_L B_WCLK_B_R B_WCLK_L B_WCLK_R VDD VSS +XB_DREG B_BIST_EN_I B_BIST_DW_I B_DCLK_B_L B_DW_I B_DI_R net044 VDD ++ VSS / RSC_IHPSG13_DFNQMX2IX1 +XB_BREG B_BIST_EN_I B_BIST_BM_I B_DCLK_B_L B_BM_I B_BM_R net043 VDD ++ VSS / RSC_IHPSG13_DFNQMX2IX1 +XA_DREG A_BIST_EN_I A_BIST_DW_I A_DCLK_B_L A_DW_I A_DI_R net22 VDD VSS ++ / RSC_IHPSG13_DFNQMX2IX1 +XA_BREG A_BIST_EN_I A_BIST_BM_I A_DCLK_B_L A_BM_I A_BM_R net23 VDD VSS ++ / RSC_IHPSG13_DFNQMX2IX1 +XI_FILL8<11> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI_FILL8<10> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI_FILL8<9> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI_FILL8<8> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI_FILL8<7> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI_FILL8<6> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI_FILL8<5> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI_FILL8<4> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI_FILL8<3> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI_FILL8<2> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI_FILL8<1> VDD VSS / RSC_IHPSG13_FILLCAP8 +XB_I51 net037 B_DR_O VDD VSS / RSC_IHPSG13_INVX4 +XA_I51 net19 A_DR_O VDD VSS / RSC_IHPSG13_INVX4 +XB_I44 B_BM_N B_WCLK_B_L B_DO_WRITE_P VDD VSS / RSC_IHPSG13_NOR2X2 +XA_I44 A_BM_N A_WCLK_B_L A_DO_WRITE_P VDD VSS / RSC_IHPSG13_NOR2X2 +XB_BM_TIEH B_TIEH_O VDD VSS / RSC_IHPSG13_TIEH +XA_BM_TIEH A_TIEH_O VDD VSS / RSC_IHPSG13_TIEH +XB_ISENSE B_SAE B_BLC_SEL B_BLT_SEL net037 net038 VDD VSS / ++ RSC_IHPSG13_DFPQD_MSAFFX2P +XA_ISENSE A_SAE A_BLC_SEL A_BLT_SEL net19 net20 VDD VSS / ++ RSC_IHPSG13_DFPQD_MSAFFX2P +XB_I49 B_DI_R B_DI_N VDD VSS / RSC_IHPSG13_INVX2 +XB_I83 B_BM_R B_BM_N VDD VSS / RSC_IHPSG13_INVX2 +XA_I49 A_DI_R A_DI_N VDD VSS / RSC_IHPSG13_INVX2 +XA_I83 A_BM_R A_BM_N VDD VSS / RSC_IHPSG13_INVX2 +XB_I69 B_DCLK_L B_DCLK_B_L VDD VSS / RSC_IHPSG13_CINVX2 +XB_I50 B_WCLK_L B_WCLK_B_L VDD VSS / RSC_IHPSG13_CINVX2 +XB_EBUF B_RCLK_L B_RCLK_B_L VDD VSS / RSC_IHPSG13_CINVX2 +XA_I69 A_DCLK_L A_DCLK_B_L VDD VSS / RSC_IHPSG13_CINVX2 +XA_I50 A_WCLK_L A_WCLK_B_L VDD VSS / RSC_IHPSG13_CINVX2 +XA_EBUF A_RCLK_L A_RCLK_B_L VDD VSS / RSC_IHPSG13_CINVX2 +XAB_BLMUX<1> A_BLC<7> A_BLC<6> A_BLC<5> A_BLC<4> A_BLC_SEL A_BLT<7> A_BLT<6> ++ A_BLT<5> A_BLT<4> A_BLT_SEL A_PRE_N A_ADDR_DEC<7> A_ADDR_DEC<6> ++ A_ADDR_DEC<5> A_ADDR_DEC<4> A_WR_ONE A_WR_ZERO B_BLC<7> B_BLC<6> B_BLC<5> ++ B_BLC<4> B_BLC_SEL B_BLT<7> B_BLT<6> B_BLT<5> B_BLT<4> B_BLT_SEL B_PRE_N ++ B_ADDR_DEC<7> B_ADDR_DEC<6> B_ADDR_DEC<5> B_ADDR_DEC<4> B_WR_ONE B_WR_ZERO ++ VDD VSS / RM_IHPSG13_512x8_c2_2P_BLDRV +XAB_BLMUX<0> A_BLC<3> A_BLC<2> A_BLC<1> A_BLC<0> A_BLC_SEL A_BLT<3> A_BLT<2> ++ A_BLT<1> A_BLT<0> A_BLT_SEL A_PRE_N A_ADDR_DEC<3> A_ADDR_DEC<2> ++ A_ADDR_DEC<1> A_ADDR_DEC<0> A_WR_ONE A_WR_ZERO B_BLC<3> B_BLC<2> B_BLC<1> ++ B_BLC<0> B_BLC_SEL B_BLT<3> B_BLT<2> B_BLT<1> B_BLT<0> B_BLT_SEL B_PRE_N ++ B_ADDR_DEC<3> B_ADDR_DEC<2> B_ADDR_DEC<1> B_ADDR_DEC<0> B_WR_ONE B_WR_ZERO ++ VDD VSS / RM_IHPSG13_512x8_c2_2P_BLDRV +XB_I78 B_RCLK_B_L B_SAE VDD VSS / RSC_IHPSG13_CBUFX2 +XA_I78 A_RCLK_B_L A_SAE VDD VSS / RSC_IHPSG13_CBUFX2 +XB_I88 B_DCLK_L B_DCLK_R / RSC_IHPSG13_MET3RES +XB_I87 B_WCLK_L B_WCLK_R / RSC_IHPSG13_MET3RES +XB_R2 B_RCLK_L B_RCLK_R / RSC_IHPSG13_MET3RES +XB_I91 B_RCLK_B_L B_RCLK_B_R / RSC_IHPSG13_MET3RES +XB_I90 B_WCLK_B_L B_WCLK_B_R / RSC_IHPSG13_MET3RES +XB_I89 B_DCLK_B_L B_DCLK_B_R / RSC_IHPSG13_MET3RES +XA_I88 A_DCLK_L A_DCLK_R / RSC_IHPSG13_MET3RES +XA_I87 A_WCLK_L A_WCLK_R / RSC_IHPSG13_MET3RES +XA_R2 A_RCLK_L A_RCLK_R / RSC_IHPSG13_MET3RES +XA_I91 A_RCLK_B_L A_RCLK_B_R / RSC_IHPSG13_MET3RES +XA_I90 A_WCLK_B_L A_WCLK_B_R / RSC_IHPSG13_MET3RES +XA_I89 A_DCLK_B_L A_DCLK_B_R / RSC_IHPSG13_MET3RES +XB_I80 B_WCLK_B_L B_RCLK_B_L net041 VDD VSS / RSC_IHPSG13_AND2X2 +XB_I76 B_DO_WRITE_P B_DI_N B_WR_ZERO VDD VSS / RSC_IHPSG13_AND2X2 +XB_I75 B_DO_WRITE_P B_DI_R B_WR_ONE VDD VSS / RSC_IHPSG13_AND2X2 +XA_I80 A_WCLK_B_L A_RCLK_B_L net21 VDD VSS / RSC_IHPSG13_AND2X2 +XA_I76 A_DI_N A_DO_WRITE_P A_WR_ZERO VDD VSS / RSC_IHPSG13_AND2X2 +XA_I75 A_DI_R A_DO_WRITE_P A_WR_ONE VDD VSS / RSC_IHPSG13_AND2X2 +XB_I81 net041 B_PRE_N VDD VSS / RSC_IHPSG13_CINVX4_WN +XA_I81 net21 A_PRE_N VDD VSS / RSC_IHPSG13_CINVX4_WN +XI_FILL4<10> VDD VSS / RSC_IHPSG13_FILLCAP4 +XI_FILL4<9> VDD VSS / RSC_IHPSG13_FILLCAP4 +XI_FILL4<8> VDD VSS / RSC_IHPSG13_FILLCAP4 +XI_FILL4<7> VDD VSS / RSC_IHPSG13_FILLCAP4 +XI_FILL4<6> VDD VSS / RSC_IHPSG13_FILLCAP4 +XI_FILL4<5> VDD VSS / RSC_IHPSG13_FILLCAP4 +XI_FILL4<4> VDD VSS / RSC_IHPSG13_FILLCAP4 +XI_FILL4<3> VDD VSS / RSC_IHPSG13_FILLCAP4 +XI_FILL4<2> VDD VSS / RSC_IHPSG13_FILLCAP4 +XI_FILL4<1> VDD VSS / RSC_IHPSG13_FILLCAP4 +.ENDS + +.SUBCKT RM_IHPSG13_512x8_c2_2P_ROWDEC6 ADDR_N_I<5> ADDR_N_I<4> ADDR_N_I<3> ADDR_N_I<2> ++ ADDR_N_I<1> ADDR_N_I<0> CS_I ECLK_I WL_O<63> WL_O<62> WL_O<61> WL_O<60> ++ WL_O<59> WL_O<58> WL_O<57> WL_O<56> WL_O<55> WL_O<54> WL_O<53> WL_O<52> ++ WL_O<51> WL_O<50> WL_O<49> WL_O<48> WL_O<47> WL_O<46> WL_O<45> WL_O<44> ++ WL_O<43> WL_O<42> WL_O<41> WL_O<40> WL_O<39> WL_O<38> WL_O<37> WL_O<36> ++ WL_O<35> WL_O<34> WL_O<33> WL_O<32> WL_O<31> WL_O<30> WL_O<29> WL_O<28> ++ WL_O<27> WL_O<26> WL_O<25> WL_O<24> WL_O<23> WL_O<22> WL_O<21> WL_O<20> ++ WL_O<19> WL_O<18> WL_O<17> WL_O<16> WL_O<15> WL_O<14> WL_O<13> WL_O<12> ++ WL_O<11> WL_O<10> WL_O<9> WL_O<8> WL_O<7> WL_O<6> WL_O<5> WL_O<4> WL_O<3> ++ WL_O<2> WL_O<1> WL_O<0> VDD VSS +XDEC10 ADDR_N_I<5> ADDR_N_I<4> CS_I CS00<2> VDD VSS / ++ RM_IHPSG13_512x8_c2_2P_DEC02 +XDEC00 ADDR_N_I<5> ADDR_N_I<4> CS_I CS00<0> VDD VSS / ++ RM_IHPSG13_512x8_c2_2P_DEC00 +XSEL<3> ADDR_N_I<3> ADDR_N_I<2> ADDR_N_I<1> ADDR_N_I<0> CS00<3> ECLK_H<3> ++ ECLK_H<4> ECLK_B<3> ECLK_B<4> WL_O<63> WL_O<62> WL_O<61> WL_O<60> WL_O<59> ++ WL_O<58> WL_O<57> WL_O<56> WL_O<55> WL_O<54> WL_O<53> WL_O<52> WL_O<51> ++ WL_O<50> WL_O<49> WL_O<48> VDD VSS / RM_IHPSG13_512x8_c2_2P_DEC04 +XSEL<2> ADDR_N_I<3> ADDR_N_I<2> ADDR_N_I<1> ADDR_N_I<0> CS00<2> ECLK_H<2> ++ ECLK_H<3> ECLK_B<2> ECLK_B<3> WL_O<47> WL_O<46> WL_O<45> WL_O<44> WL_O<43> ++ WL_O<42> WL_O<41> WL_O<40> WL_O<39> WL_O<38> WL_O<37> WL_O<36> WL_O<35> ++ WL_O<34> WL_O<33> WL_O<32> VDD VSS / RM_IHPSG13_512x8_c2_2P_DEC04 +XSEL<1> ADDR_N_I<3> ADDR_N_I<2> ADDR_N_I<1> ADDR_N_I<0> CS00<1> ECLK_H<1> ++ ECLK_H<2> ECLK_B<1> ECLK_B<2> WL_O<31> WL_O<30> WL_O<29> WL_O<28> WL_O<27> ++ WL_O<26> WL_O<25> WL_O<24> WL_O<23> WL_O<22> WL_O<21> WL_O<20> WL_O<19> ++ WL_O<18> WL_O<17> WL_O<16> VDD VSS / RM_IHPSG13_512x8_c2_2P_DEC04 +XSEL<0> ADDR_N_I<3> ADDR_N_I<2> ADDR_N_I<1> ADDR_N_I<0> CS00<0> ECLK_I ++ ECLK_H<1> ECLK_B<0> ECLK_B<1> WL_O<15> WL_O<14> WL_O<13> WL_O<12> WL_O<11> ++ WL_O<10> WL_O<9> WL_O<8> WL_O<7> WL_O<6> WL_O<5> WL_O<4> WL_O<3> WL_O<2> ++ WL_O<1> WL_O<0> VDD VSS / RM_IHPSG13_512x8_c2_2P_DEC04 +XDEC11 ADDR_N_I<5> ADDR_N_I<4> CS_I CS00<3> VDD VSS / ++ RM_IHPSG13_512x8_c2_2P_DEC03 +XL2<36> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<35> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<34> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<33> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<32> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<31> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<30> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<29> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<28> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<27> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<26> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<25> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<24> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<23> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<22> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<21> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<20> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<19> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<18> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<17> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<16> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<15> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<14> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<13> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<12> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<11> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<10> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<9> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<8> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<7> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<6> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<5> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<4> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<3> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<2> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<1> VDD VSS / RSC_IHPSG13_FILLCAP8 +XDEC01 ADDR_N_I<5> ADDR_N_I<4> CS_I CS00<1> VDD VSS / ++ RM_IHPSG13_512x8_c2_2P_DEC01 +.ENDS +.SUBCKT RM_IHPSG13_512x8_c2_2P_ROWREG6 ACLK_N_I ADDR_I<5> ADDR_I<4> ADDR_I<3> ADDR_I<2> ++ ADDR_I<1> ADDR_I<0> ADDR_N_O<5> ADDR_N_O<4> ADDR_N_O<3> ADDR_N_O<2> ++ ADDR_N_O<1> ADDR_N_O<0> BIST_ADDR_I<5> BIST_ADDR_I<4> BIST_ADDR_I<3> ++ BIST_ADDR_I<2> BIST_ADDR_I<1> BIST_ADDR_I<0> BIST_EN_I VDD VSS +XINV<5> q_int<5> qn_int<5> VDD VSS / RSC_IHPSG13_CINVX2 +XINV<4> q_int<4> qn_int<4> VDD VSS / RSC_IHPSG13_CINVX2 +XINV<3> q_int<3> qn_int<3> VDD VSS / RSC_IHPSG13_CINVX2 +XINV<2> q_int<2> qn_int<2> VDD VSS / RSC_IHPSG13_CINVX2 +XINV<1> q_int<1> qn_int<1> VDD VSS / RSC_IHPSG13_CINVX2 +XINV<0> q_int<0> qn_int<0> VDD VSS / RSC_IHPSG13_CINVX2 +XDRV<5> qn_int<5> ADDR_N_O<5> VDD VSS / RSC_IHPSG13_CINVX8 +XDRV<4> qn_int<4> ADDR_N_O<4> VDD VSS / RSC_IHPSG13_CINVX8 +XDRV<3> qn_int<3> ADDR_N_O<3> VDD VSS / RSC_IHPSG13_CINVX8 +XDRV<2> qn_int<2> ADDR_N_O<2> VDD VSS / RSC_IHPSG13_CINVX8 +XDRV<1> qn_int<1> ADDR_N_O<1> VDD VSS / RSC_IHPSG13_CINVX8 +XDRV<0> qn_int<0> ADDR_N_O<0> VDD VSS / RSC_IHPSG13_CINVX8 +XDFF<5> BIST_EN_I BIST_ADDR_I<5> ACLK_N_I ADDR_I<5> q_int<5> net2<0> VDD ++ VSS / RSC_IHPSG13_DFNQMX2IX1 +XDFF<4> BIST_EN_I BIST_ADDR_I<4> ACLK_N_I ADDR_I<4> q_int<4> net2<1> VDD ++ VSS / RSC_IHPSG13_DFNQMX2IX1 +XDFF<3> BIST_EN_I BIST_ADDR_I<3> ACLK_N_I ADDR_I<3> q_int<3> net2<2> VDD ++ VSS / RSC_IHPSG13_DFNQMX2IX1 +XDFF<2> BIST_EN_I BIST_ADDR_I<2> ACLK_N_I ADDR_I<2> q_int<2> net2<3> VDD ++ VSS / RSC_IHPSG13_DFNQMX2IX1 +XDFF<1> BIST_EN_I BIST_ADDR_I<1> ACLK_N_I ADDR_I<1> q_int<1> net2<4> VDD ++ VSS / RSC_IHPSG13_DFNQMX2IX1 +XDFF<0> BIST_EN_I BIST_ADDR_I<0> ACLK_N_I ADDR_I<0> q_int<0> net2<5> VDD ++ VSS / RSC_IHPSG13_DFNQMX2IX1 +XI11<12> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI11<11> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI11<10> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI11<9> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI11<8> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI11<7> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI11<6> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI11<5> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI11<4> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI11<3> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI11<2> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI11<1> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI12<2> VDD VSS / RSC_IHPSG13_FILLCAP4 +XI12<1> VDD VSS / RSC_IHPSG13_FILLCAP4 +XI12<0> VDD VSS / RSC_IHPSG13_FILLCAP4 +.ENDS + +.SUBCKT RM_IHPSG13_512x8_c2_2P_COLDRV13X16 ADDR_COL_I<1> ADDR_COL_I<0> ADDR_COL_O<1> ++ ADDR_COL_O<0> ADDR_DEC_I<7> ADDR_DEC_I<6> ADDR_DEC_I<5> ADDR_DEC_I<4> ++ ADDR_DEC_I<3> ADDR_DEC_I<2> ADDR_DEC_I<1> ADDR_DEC_I<0> ADDR_DEC_O<7> ++ ADDR_DEC_O<6> ADDR_DEC_O<5> ADDR_DEC_O<4> ADDR_DEC_O<3> ADDR_DEC_O<2> ++ ADDR_DEC_O<1> ADDR_DEC_O<0> DCLK_I DCLK_O RCLK_I RCLK_O WCLK_I WCLK_O ++ VDD VSS +XI0<7> VDD VSS / RSC_IHPSG13_FILLCAP4 +XI0<6> VDD VSS / RSC_IHPSG13_FILLCAP4 +XI0<5> VDD VSS / RSC_IHPSG13_FILLCAP4 +XI0<4> VDD VSS / RSC_IHPSG13_FILLCAP4 +XI0<3> VDD VSS / RSC_IHPSG13_FILLCAP4 +XI0<2> VDD VSS / RSC_IHPSG13_FILLCAP4 +XI0<1> VDD VSS / RSC_IHPSG13_FILLCAP4 +XWCLK_DRV WCLK_I WCLK_O VDD VSS / RSC_IHPSG13_CBUFX16 +XRCLK_DRV RCLK_I RCLK_O VDD VSS / RSC_IHPSG13_CBUFX16 +XDCLK_DRV DCLK_I DCLK_O VDD VSS / RSC_IHPSG13_CBUFX16 +XADDR_COL_DRV<1> ADDR_COL_I<1> ADDR_COL_O<1> VDD VSS / ++ RSC_IHPSG13_CBUFX16 +XADDR_COL_DRV<0> ADDR_COL_I<0> ADDR_COL_O<0> VDD VSS / ++ RSC_IHPSG13_CBUFX16 +XADDR_DEC_DRV<7> ADDR_DEC_I<7> ADDR_DEC_O<7> VDD VSS / ++ RSC_IHPSG13_CBUFX16 +XADDR_DEC_DRV<6> ADDR_DEC_I<6> ADDR_DEC_O<6> VDD VSS / ++ RSC_IHPSG13_CBUFX16 +XADDR_DEC_DRV<5> ADDR_DEC_I<5> ADDR_DEC_O<5> VDD VSS / ++ RSC_IHPSG13_CBUFX16 +XADDR_DEC_DRV<4> ADDR_DEC_I<4> ADDR_DEC_O<4> VDD VSS / ++ RSC_IHPSG13_CBUFX16 +XADDR_DEC_DRV<3> ADDR_DEC_I<3> ADDR_DEC_O<3> VDD VSS / ++ RSC_IHPSG13_CBUFX16 +XADDR_DEC_DRV<2> ADDR_DEC_I<2> ADDR_DEC_O<2> VDD VSS / ++ RSC_IHPSG13_CBUFX16 +XADDR_DEC_DRV<1> ADDR_DEC_I<1> ADDR_DEC_O<1> VDD VSS / ++ RSC_IHPSG13_CBUFX16 +XADDR_DEC_DRV<0> ADDR_DEC_I<0> ADDR_DEC_O<0> VDD VSS / ++ RSC_IHPSG13_CBUFX16 +XI1<5> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI1<4> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI1<3> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI1<2> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI1<1> VDD VSS / RSC_IHPSG13_FILLCAP8 +.ENDS +.SUBCKT RM_IHPSG13_512x8_c2_2P_WLDRV16X16 A<15> A<14> A<13> A<12> A<11> A<10> A<9> A<8> ++ A<7> A<6> A<5> A<4> A<3> A<2> A<1> A<0> Z<15> Z<14> Z<13> Z<12> Z<11> Z<10> ++ Z<9> Z<8> Z<7> Z<6> Z<5> Z<4> Z<3> Z<2> Z<1> Z<0> VDD VSS +XBUF<15> A<15> Z<15> VDD VSS / RSC_IHPSG13_WLDRVX16 +XBUF<14> A<14> Z<14> VDD VSS / RSC_IHPSG13_WLDRVX16 +XBUF<13> A<13> Z<13> VDD VSS / RSC_IHPSG13_WLDRVX16 +XBUF<12> A<12> Z<12> VDD VSS / RSC_IHPSG13_WLDRVX16 +XBUF<11> A<11> Z<11> VDD VSS / RSC_IHPSG13_WLDRVX16 +XBUF<10> A<10> Z<10> VDD VSS / RSC_IHPSG13_WLDRVX16 +XBUF<9> A<9> Z<9> VDD VSS / RSC_IHPSG13_WLDRVX16 +XBUF<8> A<8> Z<8> VDD VSS / RSC_IHPSG13_WLDRVX16 +XBUF<7> A<7> Z<7> VDD VSS / RSC_IHPSG13_WLDRVX16 +XBUF<6> A<6> Z<6> VDD VSS / RSC_IHPSG13_WLDRVX16 +XBUF<5> A<5> Z<5> VDD VSS / RSC_IHPSG13_WLDRVX16 +XBUF<4> A<4> Z<4> VDD VSS / RSC_IHPSG13_WLDRVX16 +XBUF<3> A<3> Z<3> VDD VSS / RSC_IHPSG13_WLDRVX16 +XBUF<2> A<2> Z<2> VDD VSS / RSC_IHPSG13_WLDRVX16 +XBUF<1> A<1> Z<1> VDD VSS / RSC_IHPSG13_WLDRVX16 +XBUF<0> A<0> Z<0> VDD VSS / RSC_IHPSG13_WLDRVX16 +.ENDS + + +.SUBCKT RM_IHPSG13_512x8_c2_1P_DEC01 ADDR<1> ADDR<0> CS CS_OUT VDD VSS +XDECINV net1 CS_OUT VDD VSS / RSC_IHPSG13_INVX4 +XDEC NADDR<1> ADDR<0> CS net1 VDD VSS / RSC_IHPSG13_NAND3X2 +XI2 VDD VSS / RSC_IHPSG13_FILLCAP4 +XADDRINV ADDR<1> NADDR<1> VDD VSS / RSC_IHPSG13_INVX2 +.ENDS +.SUBCKT RM_IHPSG13_512x8_c2_1P_DEC00 ADDR<1> ADDR<0> CS CS_OUT VDD VSS +XDECINV net1 CS_OUT VDD VSS / RSC_IHPSG13_INVX4 +XDEC NADDR<1> NADDR<0> CS net1 VDD VSS / RSC_IHPSG13_NAND3X2 +XADDRINV<1> ADDR<1> NADDR<1> VDD VSS / RSC_IHPSG13_INVX2 +XADDRINV<0> ADDR<0> NADDR<0> VDD VSS / RSC_IHPSG13_INVX2 +XI1 VDD VSS / RSC_IHPSG13_FILLCAP4 +.ENDS +.SUBCKT RM_IHPSG13_512x8_c2_1P_ROWDEC5 ADDR_N_I<4> ADDR_N_I<3> ADDR_N_I<2> ADDR_N_I<1> ++ ADDR_N_I<0> CS_I ECLK_I WL_O<31> WL_O<30> WL_O<29> WL_O<28> WL_O<27> ++ WL_O<26> WL_O<25> WL_O<24> WL_O<23> WL_O<22> WL_O<21> WL_O<20> WL_O<19> ++ WL_O<18> WL_O<17> WL_O<16> WL_O<15> WL_O<14> WL_O<13> WL_O<12> WL_O<11> ++ WL_O<10> WL_O<9> WL_O<8> WL_O<7> WL_O<6> WL_O<5> WL_O<4> WL_O<3> WL_O<2> ++ WL_O<1> WL_O<0> VDD VSS +XL2<12> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<11> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<10> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<9> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<8> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<7> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<6> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<5> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<4> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<3> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<2> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<1> VDD VSS / RSC_IHPSG13_FILLCAP8 +XDEC01 ADDR_N_I<5> ADDR_N_I<4> CS_I CS00<1> VDD VSS / ++ RM_IHPSG13_512x8_c2_1P_DEC01 +XDEC00 ADDR_N_I<5> ADDR_N_I<4> CS_I CS00<0> VDD VSS / ++ RM_IHPSG13_512x8_c2_1P_DEC00 +XSEL<1> ADDR_N_I<3> ADDR_N_I<2> ADDR_N_I<1> ADDR_N_I<0> CS00<1> ECLK_H<1> ++ ECLK_H<2> ECLK_B<1> ECLK_B<2> WL_O<31> WL_O<30> WL_O<29> WL_O<28> WL_O<27> ++ WL_O<26> WL_O<25> WL_O<24> WL_O<23> WL_O<22> WL_O<21> WL_O<20> WL_O<19> ++ WL_O<18> WL_O<17> WL_O<16> VDD VSS / RM_IHPSG13_512x8_c2_1P_DEC04 +XSEL<0> ADDR_N_I<3> ADDR_N_I<2> ADDR_N_I<1> ADDR_N_I<0> CS00<0> ECLK_I ++ ECLK_H<1> ECLK_B<0> ECLK_B<1> WL_O<15> WL_O<14> WL_O<13> WL_O<12> WL_O<11> ++ WL_O<10> WL_O<9> WL_O<8> WL_O<7> WL_O<6> WL_O<5> WL_O<4> WL_O<3> WL_O<2> ++ WL_O<1> WL_O<0> VDD VSS / RM_IHPSG13_512x8_c2_1P_DEC04 +XI0 ADDR_N_I<5> VDD VSS / RSC_IHPSG13_TIEL +.ENDS +.SUBCKT RM_IHPSG13_512x8_c2_1P_ROWREG5 ACLK_N_I ADDR_I<4> ADDR_I<3> ADDR_I<2> ADDR_I<1> ++ ADDR_I<0> ADDR_N_O<4> ADDR_N_O<3> ADDR_N_O<2> ADDR_N_O<1> ADDR_N_O<0> ++ BIST_ADDR_I<4> BIST_ADDR_I<3> BIST_ADDR_I<2> BIST_ADDR_I<1> BIST_ADDR_I<0> ++ BIST_EN_I VDD VSS +XINV<4> q_int<4> qn_int<4> VDD VSS / RSC_IHPSG13_CINVX2 +XINV<3> q_int<3> qn_int<3> VDD VSS / RSC_IHPSG13_CINVX2 +XINV<2> q_int<2> qn_int<2> VDD VSS / RSC_IHPSG13_CINVX2 +XINV<1> q_int<1> qn_int<1> VDD VSS / RSC_IHPSG13_CINVX2 +XINV<0> q_int<0> qn_int<0> VDD VSS / RSC_IHPSG13_CINVX2 +XDRV<4> qn_int<4> ADDR_N_O<4> VDD VSS / RSC_IHPSG13_CINVX8 +XDRV<3> qn_int<3> ADDR_N_O<3> VDD VSS / RSC_IHPSG13_CINVX8 +XDRV<2> qn_int<2> ADDR_N_O<2> VDD VSS / RSC_IHPSG13_CINVX8 +XDRV<1> qn_int<1> ADDR_N_O<1> VDD VSS / RSC_IHPSG13_CINVX8 +XDRV<0> qn_int<0> ADDR_N_O<0> VDD VSS / RSC_IHPSG13_CINVX8 +XDFF<4> BIST_EN_I BIST_ADDR_I<4> ACLK_N_I ADDR_I<4> q_int<4> net2<0> VDD ++ VSS / RSC_IHPSG13_DFNQMX2IX1 +XDFF<3> BIST_EN_I BIST_ADDR_I<3> ACLK_N_I ADDR_I<3> q_int<3> net2<1> VDD ++ VSS / RSC_IHPSG13_DFNQMX2IX1 +XDFF<2> BIST_EN_I BIST_ADDR_I<2> ACLK_N_I ADDR_I<2> q_int<2> net2<2> VDD ++ VSS / RSC_IHPSG13_DFNQMX2IX1 +XDFF<1> BIST_EN_I BIST_ADDR_I<1> ACLK_N_I ADDR_I<1> q_int<1> net2<3> VDD ++ VSS / RSC_IHPSG13_DFNQMX2IX1 +XDFF<0> BIST_EN_I BIST_ADDR_I<0> ACLK_N_I ADDR_I<0> q_int<0> net2<4> VDD ++ VSS / RSC_IHPSG13_DFNQMX2IX1 +XI11<16> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI11<15> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI11<14> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI11<13> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI11<12> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI11<11> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI11<10> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI11<9> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI11<8> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI11<7> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI11<6> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI11<5> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI11<4> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI11<3> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI11<2> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI11<1> VDD VSS / RSC_IHPSG13_FILLCAP8 +.ENDS + + +.SUBCKT RM_IHPSG13_512x8_c2_1P_COLDEC5 ACLK_N ADDR<4> ADDR<3> ADDR<2> ADDR<1> ADDR<0> ++ ADDR_COL<1> ADDR_COL<0> ADDR_DEC<7> ADDR_DEC<6> ADDR_DEC<5> ADDR_DEC<4> ++ ADDR_DEC<3> ADDR_DEC<2> ADDR_DEC<1> ADDR_DEC<0> BIST_ADDR<4> BIST_ADDR<3> ++ BIST_ADDR<2> BIST_ADDR<1> BIST_ADDR<0> BIST_EN_I VDD VSS +XI17<2> VDD VSS / RSC_IHPSG13_FILLCAP4 +XI17<1> VDD VSS / RSC_IHPSG13_FILLCAP4 +XI13<1> addr_int<1> ADDR_COL<1> VDD VSS / RSC_IHPSG13_CBUFX2 +XI13<0> addr_int<0> ADDR_COL<0> VDD VSS / RSC_IHPSG13_CBUFX2 +XDFF<4> BIST_EN_I BIST_ADDR<4> ACLK_N ADDR<4> addr_int<1> net7<0> VDD ++ VSS / RSC_IHPSG13_DFNQMX2IX1 +XDFF<3> BIST_EN_I BIST_ADDR<3> ACLK_N ADDR<3> addr_int<0> net7<1> VDD ++ VSS / RSC_IHPSG13_DFNQMX2IX1 +XDFF<2> BIST_EN_I BIST_ADDR<2> ACLK_N ADDR<2> padr_int<2> net7<2> VDD ++ VSS / RSC_IHPSG13_DFNQMX2IX1 +XDFF<1> BIST_EN_I BIST_ADDR<1> ACLK_N ADDR<1> padr_int<1> net7<3> VDD ++ VSS / RSC_IHPSG13_DFNQMX2IX1 +XDFF<0> BIST_EN_I BIST_ADDR<0> ACLK_N ADDR<0> padr_int<0> net7<4> VDD ++ VSS / RSC_IHPSG13_DFNQMX2IX1 +XI1<7> PADR<0> PADR<1> PADR<2> addr_n<7> VDD VSS / RSC_IHPSG13_NAND3X2 +XI1<6> NADR<0> PADR<1> PADR<2> addr_n<6> VDD VSS / RSC_IHPSG13_NAND3X2 +XI1<5> PADR<0> NADR<1> PADR<2> addr_n<5> VDD VSS / RSC_IHPSG13_NAND3X2 +XI1<4> NADR<0> NADR<1> PADR<2> addr_n<4> VDD VSS / RSC_IHPSG13_NAND3X2 +XI1<3> PADR<0> PADR<1> NADR<2> addr_n<3> VDD VSS / RSC_IHPSG13_NAND3X2 +XI1<2> NADR<0> PADR<1> NADR<2> addr_n<2> VDD VSS / RSC_IHPSG13_NAND3X2 +XI1<1> PADR<0> NADR<1> NADR<2> addr_n<1> VDD VSS / RSC_IHPSG13_NAND3X2 +XI1<0> NADR<0> NADR<1> NADR<2> addr_n<0> VDD VSS / RSC_IHPSG13_NAND3X2 +XI15<2> NADR<2> PADR<2> VDD VSS / RSC_IHPSG13_INVX2 +XI15<1> NADR<1> PADR<1> VDD VSS / RSC_IHPSG13_INVX2 +XI15<0> NADR<0> PADR<0> VDD VSS / RSC_IHPSG13_INVX2 +XI3<2> padr_int<2> NADR<2> VDD VSS / RSC_IHPSG13_INVX2 +XI3<1> padr_int<1> NADR<1> VDD VSS / RSC_IHPSG13_INVX2 +XI3<0> padr_int<0> NADR<0> VDD VSS / RSC_IHPSG13_INVX2 +XI2<7> addr_n<7> ADDR_DEC<7> VDD VSS / RSC_IHPSG13_INVX2 +XI2<6> addr_n<6> ADDR_DEC<6> VDD VSS / RSC_IHPSG13_INVX2 +XI2<5> addr_n<5> ADDR_DEC<5> VDD VSS / RSC_IHPSG13_INVX2 +XI2<4> addr_n<4> ADDR_DEC<4> VDD VSS / RSC_IHPSG13_INVX2 +XI2<3> addr_n<3> ADDR_DEC<3> VDD VSS / RSC_IHPSG13_INVX2 +XI2<2> addr_n<2> ADDR_DEC<2> VDD VSS / RSC_IHPSG13_INVX2 +XI2<1> addr_n<1> ADDR_DEC<1> VDD VSS / RSC_IHPSG13_INVX2 +XI2<0> addr_n<0> ADDR_DEC<0> VDD VSS / RSC_IHPSG13_INVX2 +.ENDS +.SUBCKT RM_IHPSG13_512x8_c2_1P_COLCTRL5 A_ADDR_COL<1> A_ADDR_COL<0> A_ADDR_DEC<7> ++ A_ADDR_DEC<6> A_ADDR_DEC<5> A_ADDR_DEC<4> A_ADDR_DEC<3> A_ADDR_DEC<2> ++ A_ADDR_DEC<1> A_ADDR_DEC<0> A_BIST_BM_I A_BIST_DW_I A_BIST_EN_I A_BLC<31> ++ A_BLC<30> A_BLC<29> A_BLC<28> A_BLC<27> A_BLC<26> A_BLC<25> A_BLC<24> ++ A_BLC<23> A_BLC<22> A_BLC<21> A_BLC<20> A_BLC<19> A_BLC<18> A_BLC<17> ++ A_BLC<16> A_BLC<15> A_BLC<14> A_BLC<13> A_BLC<12> A_BLC<11> A_BLC<10> ++ A_BLC<9> A_BLC<8> A_BLC<7> A_BLC<6> A_BLC<5> A_BLC<4> A_BLC<3> A_BLC<2> ++ A_BLC<1> A_BLC<0> A_BLT<31> A_BLT<30> A_BLT<29> A_BLT<28> A_BLT<27> ++ A_BLT<26> A_BLT<25> A_BLT<24> A_BLT<23> A_BLT<22> A_BLT<21> A_BLT<20> ++ A_BLT<19> A_BLT<18> A_BLT<17> A_BLT<16> A_BLT<15> A_BLT<14> A_BLT<13> ++ A_BLT<12> A_BLT<11> A_BLT<10> A_BLT<9> A_BLT<8> A_BLT<7> A_BLT<6> A_BLT<5> ++ A_BLT<4> A_BLT<3> A_BLT<2> A_BLT<1> A_BLT<0> A_BM_I A_DCLK_B_L A_DCLK_B_R ++ A_DCLK_L A_DCLK_R A_DR_O A_DW_I A_RCLK_B_L A_RCLK_B_R A_RCLK_L A_RCLK_R ++ A_TIEH_O A_WCLK_B_L A_WCLK_B_R A_WCLK_L A_WCLK_R VDD VSS +XA_I80<1> A_WCLK_B_L A_RCLK_B_L A_W_nor_R<1> VDD VSS / ++ RSC_IHPSG13_AND2X2 +XA_I80<0> A_WCLK_B_L A_RCLK_B_L A_W_nor_R<0> VDD VSS / ++ RSC_IHPSG13_AND2X2 +XA_I44 A_BM_N A_WCLK_B_L A_DO_WRITE_P VDD VSS / RSC_IHPSG13_NOR2X2 +XI80<29> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI80<28> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI80<27> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI80<26> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI80<25> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI80<24> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI80<23> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI80<22> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI80<21> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI80<20> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI80<19> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI80<18> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI80<17> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI80<16> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI80<15> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI80<14> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI80<13> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI80<12> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI80<11> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI80<10> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI80<9> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI80<8> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI80<7> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI80<6> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI80<5> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI80<4> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI80<3> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI80<2> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI80<1> VDD VSS / RSC_IHPSG13_FILLCAP8 +XA_I74<16> VDD VSS / RSC_IHPSG13_FILLCAP8 +XA_I74<15> VDD VSS / RSC_IHPSG13_FILLCAP8 +XA_I74<14> VDD VSS / RSC_IHPSG13_FILLCAP8 +XA_I74<13> VDD VSS / RSC_IHPSG13_FILLCAP8 +XA_I74<12> VDD VSS / RSC_IHPSG13_FILLCAP8 +XA_I74<11> VDD VSS / RSC_IHPSG13_FILLCAP8 +XA_I74<10> VDD VSS / RSC_IHPSG13_FILLCAP8 +XA_I74<9> VDD VSS / RSC_IHPSG13_FILLCAP8 +XA_I74<8> VDD VSS / RSC_IHPSG13_FILLCAP8 +XA_I74<7> VDD VSS / RSC_IHPSG13_FILLCAP8 +XA_I74<6> VDD VSS / RSC_IHPSG13_FILLCAP8 +XA_I74<5> VDD VSS / RSC_IHPSG13_FILLCAP8 +XA_I74<4> VDD VSS / RSC_IHPSG13_FILLCAP8 +XA_I74<3> VDD VSS / RSC_IHPSG13_FILLCAP8 +XA_I74<2> VDD VSS / RSC_IHPSG13_FILLCAP8 +XA_I74<1> VDD VSS / RSC_IHPSG13_FILLCAP8 +XA_INV<6> A_N1<1> A_P1<1> VDD VSS / RSC_IHPSG13_CINVX4 +XA_INV<5> A_N0<1> A_P0<1> VDD VSS / RSC_IHPSG13_CINVX4 +XA_INV<4> A_N0<0> A_P0<0> VDD VSS / RSC_IHPSG13_CINVX4 +XA_INV<3> A_ADDR_COL<1> A_N1<1> VDD VSS / RSC_IHPSG13_CINVX4 +XA_INV<2> A_ADDR_COL<1> A_N1<0> VDD VSS / RSC_IHPSG13_CINVX4 +XA_INV<1> A_ADDR_COL<0> A_N0<1> VDD VSS / RSC_IHPSG13_CINVX4 +XA_INV<0> A_ADDR_COL<0> A_N0<0> VDD VSS / RSC_IHPSG13_CINVX4 +XA_I81<3> A_W_nor_R<1> A_PRE_N VDD VSS / RSC_IHPSG13_CINVX4_WN +XA_I81<2> A_W_nor_R<1> A_PRE_N VDD VSS / RSC_IHPSG13_CINVX4_WN +XA_I81<1> A_W_nor_R<0> A_PRE_N VDD VSS / RSC_IHPSG13_CINVX4_WN +XA_I81<0> A_W_nor_R<0> A_PRE_N VDD VSS / RSC_IHPSG13_CINVX4_WN +XA_BLTMUX<31> A_BLC<31> A_BLC_SEL A_BLT<31> A_BLT_SEL A_PRE_N A_SEL_P<31> ++ A_WR_ONE A_WR_ZERO VDD VSS / RM_IHPSG13_512x8_c2_1P_BLDRV +XA_BLTMUX<30> A_BLC<30> A_BLC_SEL A_BLT<30> A_BLT_SEL A_PRE_N A_SEL_P<30> ++ A_WR_ONE A_WR_ZERO VDD VSS / RM_IHPSG13_512x8_c2_1P_BLDRV +XA_BLTMUX<29> A_BLC<29> A_BLC_SEL A_BLT<29> A_BLT_SEL A_PRE_N A_SEL_P<29> ++ A_WR_ONE A_WR_ZERO VDD VSS / RM_IHPSG13_512x8_c2_1P_BLDRV +XA_BLTMUX<28> A_BLC<28> A_BLC_SEL A_BLT<28> A_BLT_SEL A_PRE_N A_SEL_P<28> ++ A_WR_ONE A_WR_ZERO VDD VSS / RM_IHPSG13_512x8_c2_1P_BLDRV +XA_BLTMUX<27> A_BLC<27> A_BLC_SEL A_BLT<27> A_BLT_SEL A_PRE_N A_SEL_P<27> ++ A_WR_ONE A_WR_ZERO VDD VSS / RM_IHPSG13_512x8_c2_1P_BLDRV +XA_BLTMUX<26> A_BLC<26> A_BLC_SEL A_BLT<26> A_BLT_SEL A_PRE_N A_SEL_P<26> ++ A_WR_ONE A_WR_ZERO VDD VSS / RM_IHPSG13_512x8_c2_1P_BLDRV +XA_BLTMUX<25> A_BLC<25> A_BLC_SEL A_BLT<25> A_BLT_SEL A_PRE_N A_SEL_P<25> ++ A_WR_ONE A_WR_ZERO VDD VSS / RM_IHPSG13_512x8_c2_1P_BLDRV +XA_BLTMUX<24> A_BLC<24> A_BLC_SEL A_BLT<24> A_BLT_SEL A_PRE_N A_SEL_P<24> ++ A_WR_ONE A_WR_ZERO VDD VSS / RM_IHPSG13_512x8_c2_1P_BLDRV +XA_BLTMUX<23> A_BLC<23> A_BLC_SEL A_BLT<23> A_BLT_SEL A_PRE_N A_SEL_P<23> ++ A_WR_ONE A_WR_ZERO VDD VSS / RM_IHPSG13_512x8_c2_1P_BLDRV +XA_BLTMUX<22> A_BLC<22> A_BLC_SEL A_BLT<22> A_BLT_SEL A_PRE_N A_SEL_P<22> ++ A_WR_ONE A_WR_ZERO VDD VSS / RM_IHPSG13_512x8_c2_1P_BLDRV +XA_BLTMUX<21> A_BLC<21> A_BLC_SEL A_BLT<21> A_BLT_SEL A_PRE_N A_SEL_P<21> ++ A_WR_ONE A_WR_ZERO VDD VSS / RM_IHPSG13_512x8_c2_1P_BLDRV +XA_BLTMUX<20> A_BLC<20> A_BLC_SEL A_BLT<20> A_BLT_SEL A_PRE_N A_SEL_P<20> ++ A_WR_ONE A_WR_ZERO VDD VSS / RM_IHPSG13_512x8_c2_1P_BLDRV +XA_BLTMUX<19> A_BLC<19> A_BLC_SEL A_BLT<19> A_BLT_SEL A_PRE_N A_SEL_P<19> ++ A_WR_ONE A_WR_ZERO VDD VSS / RM_IHPSG13_512x8_c2_1P_BLDRV +XA_BLTMUX<18> A_BLC<18> A_BLC_SEL A_BLT<18> A_BLT_SEL A_PRE_N A_SEL_P<18> ++ A_WR_ONE A_WR_ZERO VDD VSS / RM_IHPSG13_512x8_c2_1P_BLDRV +XA_BLTMUX<17> A_BLC<17> A_BLC_SEL A_BLT<17> A_BLT_SEL A_PRE_N A_SEL_P<17> ++ A_WR_ONE A_WR_ZERO VDD VSS / RM_IHPSG13_512x8_c2_1P_BLDRV +XA_BLTMUX<16> A_BLC<16> A_BLC_SEL A_BLT<16> A_BLT_SEL A_PRE_N A_SEL_P<16> ++ A_WR_ONE A_WR_ZERO VDD VSS / RM_IHPSG13_512x8_c2_1P_BLDRV +XA_BLTMUX<15> A_BLC<15> A_BLC_SEL A_BLT<15> A_BLT_SEL A_PRE_N A_SEL_P<15> ++ A_WR_ONE A_WR_ZERO VDD VSS / RM_IHPSG13_512x8_c2_1P_BLDRV +XA_BLTMUX<14> A_BLC<14> A_BLC_SEL A_BLT<14> A_BLT_SEL A_PRE_N A_SEL_P<14> ++ A_WR_ONE A_WR_ZERO VDD VSS / RM_IHPSG13_512x8_c2_1P_BLDRV +XA_BLTMUX<13> A_BLC<13> A_BLC_SEL A_BLT<13> A_BLT_SEL A_PRE_N A_SEL_P<13> ++ A_WR_ONE A_WR_ZERO VDD VSS / RM_IHPSG13_512x8_c2_1P_BLDRV +XA_BLTMUX<12> A_BLC<12> A_BLC_SEL A_BLT<12> A_BLT_SEL A_PRE_N A_SEL_P<12> ++ A_WR_ONE A_WR_ZERO VDD VSS / RM_IHPSG13_512x8_c2_1P_BLDRV +XA_BLTMUX<11> A_BLC<11> A_BLC_SEL A_BLT<11> A_BLT_SEL A_PRE_N A_SEL_P<11> ++ A_WR_ONE A_WR_ZERO VDD VSS / RM_IHPSG13_512x8_c2_1P_BLDRV +XA_BLTMUX<10> A_BLC<10> A_BLC_SEL A_BLT<10> A_BLT_SEL A_PRE_N A_SEL_P<10> ++ A_WR_ONE A_WR_ZERO VDD VSS / RM_IHPSG13_512x8_c2_1P_BLDRV +XA_BLTMUX<9> A_BLC<9> A_BLC_SEL A_BLT<9> A_BLT_SEL A_PRE_N A_SEL_P<9> A_WR_ONE ++ A_WR_ZERO VDD VSS / RM_IHPSG13_512x8_c2_1P_BLDRV +XA_BLTMUX<8> A_BLC<8> A_BLC_SEL A_BLT<8> A_BLT_SEL A_PRE_N A_SEL_P<8> A_WR_ONE ++ A_WR_ZERO VDD VSS / RM_IHPSG13_512x8_c2_1P_BLDRV +XA_BLTMUX<7> A_BLC<7> A_BLC_SEL A_BLT<7> A_BLT_SEL A_PRE_N A_SEL_P<7> A_WR_ONE ++ A_WR_ZERO VDD VSS / RM_IHPSG13_512x8_c2_1P_BLDRV +XA_BLTMUX<6> A_BLC<6> A_BLC_SEL A_BLT<6> A_BLT_SEL A_PRE_N A_SEL_P<6> A_WR_ONE ++ A_WR_ZERO VDD VSS / RM_IHPSG13_512x8_c2_1P_BLDRV +XA_BLTMUX<5> A_BLC<5> A_BLC_SEL A_BLT<5> A_BLT_SEL A_PRE_N A_SEL_P<5> A_WR_ONE ++ A_WR_ZERO VDD VSS / RM_IHPSG13_512x8_c2_1P_BLDRV +XA_BLTMUX<4> A_BLC<4> A_BLC_SEL A_BLT<4> A_BLT_SEL A_PRE_N A_SEL_P<4> A_WR_ONE ++ A_WR_ZERO VDD VSS / RM_IHPSG13_512x8_c2_1P_BLDRV +XA_BLTMUX<3> A_BLC<3> A_BLC_SEL A_BLT<3> A_BLT_SEL A_PRE_N A_SEL_P<3> A_WR_ONE ++ A_WR_ZERO VDD VSS / RM_IHPSG13_512x8_c2_1P_BLDRV +XA_BLTMUX<2> A_BLC<2> A_BLC_SEL A_BLT<2> A_BLT_SEL A_PRE_N A_SEL_P<2> A_WR_ONE ++ A_WR_ZERO VDD VSS / RM_IHPSG13_512x8_c2_1P_BLDRV +XA_BLTMUX<1> A_BLC<1> A_BLC_SEL A_BLT<1> A_BLT_SEL A_PRE_N A_SEL_P<1> A_WR_ONE ++ A_WR_ZERO VDD VSS / RM_IHPSG13_512x8_c2_1P_BLDRV +XA_BLTMUX<0> A_BLC<0> A_BLC_SEL A_BLT<0> A_BLT_SEL A_PRE_N A_SEL_P<0> A_WR_ONE ++ A_WR_ZERO VDD VSS / RM_IHPSG13_512x8_c2_1P_BLDRV +XA_CAPS<17> VDD VSS / RSC_IHPSG13_FILLCAP4 +XA_CAPS<16> VDD VSS / RSC_IHPSG13_FILLCAP4 +XA_CAPS<15> VDD VSS / RSC_IHPSG13_FILLCAP4 +XA_CAPS<14> VDD VSS / RSC_IHPSG13_FILLCAP4 +XA_CAPS<13> VDD VSS / RSC_IHPSG13_FILLCAP4 +XA_CAPS<12> VDD VSS / RSC_IHPSG13_FILLCAP4 +XA_CAPS<11> VDD VSS / RSC_IHPSG13_FILLCAP4 +XA_CAPS<10> VDD VSS / RSC_IHPSG13_FILLCAP4 +XA_CAPS<9> VDD VSS / RSC_IHPSG13_FILLCAP4 +XA_CAPS<8> VDD VSS / RSC_IHPSG13_FILLCAP4 +XA_CAPS<7> VDD VSS / RSC_IHPSG13_FILLCAP4 +XA_CAPS<6> VDD VSS / RSC_IHPSG13_FILLCAP4 +XA_CAPS<5> VDD VSS / RSC_IHPSG13_FILLCAP4 +XA_CAPS<4> VDD VSS / RSC_IHPSG13_FILLCAP4 +XA_CAPS<3> VDD VSS / RSC_IHPSG13_FILLCAP4 +XA_CAPS<2> VDD VSS / RSC_IHPSG13_FILLCAP4 +XA_CAPS<1> VDD VSS / RSC_IHPSG13_FILLCAP4 +XA_I51 net19 A_DR_O VDD VSS / RSC_IHPSG13_INVX4 +XA_I78 A_RCLK_B_L A_SAE VDD VSS / RSC_IHPSG13_CBUFX2 +XA_I69 A_DCLK_L A_DCLK_B_L VDD VSS / RSC_IHPSG13_CINVX8 +XA_I50 A_WCLK_L A_WCLK_B_L VDD VSS / RSC_IHPSG13_CINVX8 +XA_EBUF A_RCLK_L A_RCLK_B_L VDD VSS / RSC_IHPSG13_CINVX8 +XA_I76 A_DI_N A_DO_WRITE_P A_WR_ZERO VDD VSS / RSC_IHPSG13_AND2X6 +XA_I75 A_DI_R A_DO_WRITE_P A_WR_ONE VDD VSS / RSC_IHPSG13_AND2X6 +XA_I83 A_BM_R A_BM_N VDD VSS / RSC_IHPSG13_INVX2 +XA_DEC3INV<31> net23<0> A_SEL_P<31> VDD VSS / RSC_IHPSG13_INVX2 +XA_DEC3INV<30> net23<1> A_SEL_P<30> VDD VSS / RSC_IHPSG13_INVX2 +XA_DEC3INV<29> net23<2> A_SEL_P<29> VDD VSS / RSC_IHPSG13_INVX2 +XA_DEC3INV<28> net23<3> A_SEL_P<28> VDD VSS / RSC_IHPSG13_INVX2 +XA_DEC3INV<27> net23<4> A_SEL_P<27> VDD VSS / RSC_IHPSG13_INVX2 +XA_DEC3INV<26> net23<5> A_SEL_P<26> VDD VSS / RSC_IHPSG13_INVX2 +XA_DEC3INV<25> net23<6> A_SEL_P<25> VDD VSS / RSC_IHPSG13_INVX2 +XA_DEC3INV<24> net23<7> A_SEL_P<24> VDD VSS / RSC_IHPSG13_INVX2 +XA_DEC3INV<23> net23<8> A_SEL_P<23> VDD VSS / RSC_IHPSG13_INVX2 +XA_DEC3INV<22> net23<9> A_SEL_P<22> VDD VSS / RSC_IHPSG13_INVX2 +XA_DEC3INV<21> net23<10> A_SEL_P<21> VDD VSS / RSC_IHPSG13_INVX2 +XA_DEC3INV<20> net23<11> A_SEL_P<20> VDD VSS / RSC_IHPSG13_INVX2 +XA_DEC3INV<19> net23<12> A_SEL_P<19> VDD VSS / RSC_IHPSG13_INVX2 +XA_DEC3INV<18> net23<13> A_SEL_P<18> VDD VSS / RSC_IHPSG13_INVX2 +XA_DEC3INV<17> net23<14> A_SEL_P<17> VDD VSS / RSC_IHPSG13_INVX2 +XA_DEC3INV<16> net23<15> A_SEL_P<16> VDD VSS / RSC_IHPSG13_INVX2 +XA_DEC3INV<15> net23<16> A_SEL_P<15> VDD VSS / RSC_IHPSG13_INVX2 +XA_DEC3INV<14> net23<17> A_SEL_P<14> VDD VSS / RSC_IHPSG13_INVX2 +XA_DEC3INV<13> net23<18> A_SEL_P<13> VDD VSS / RSC_IHPSG13_INVX2 +XA_DEC3INV<12> net23<19> A_SEL_P<12> VDD VSS / RSC_IHPSG13_INVX2 +XA_DEC3INV<11> net23<20> A_SEL_P<11> VDD VSS / RSC_IHPSG13_INVX2 +XA_DEC3INV<10> net23<21> A_SEL_P<10> VDD VSS / RSC_IHPSG13_INVX2 +XA_DEC3INV<9> net23<22> A_SEL_P<9> VDD VSS / RSC_IHPSG13_INVX2 +XA_DEC3INV<8> net23<23> A_SEL_P<8> VDD VSS / RSC_IHPSG13_INVX2 +XA_DEC3INV<7> net23<24> A_SEL_P<7> VDD VSS / RSC_IHPSG13_INVX2 +XA_DEC3INV<6> net23<25> A_SEL_P<6> VDD VSS / RSC_IHPSG13_INVX2 +XA_DEC3INV<5> net23<26> A_SEL_P<5> VDD VSS / RSC_IHPSG13_INVX2 +XA_DEC3INV<4> net23<27> A_SEL_P<4> VDD VSS / RSC_IHPSG13_INVX2 +XA_DEC3INV<3> net23<28> A_SEL_P<3> VDD VSS / RSC_IHPSG13_INVX2 +XA_DEC3INV<2> net23<29> A_SEL_P<2> VDD VSS / RSC_IHPSG13_INVX2 +XA_DEC3INV<1> net23<30> A_SEL_P<1> VDD VSS / RSC_IHPSG13_INVX2 +XA_DEC3INV<0> net23<31> A_SEL_P<0> VDD VSS / RSC_IHPSG13_INVX2 +XA_I49 A_DI_R A_DI_N VDD VSS / RSC_IHPSG13_INVX2 +XA_ISENSE A_SAE A_BLC_SEL A_BLT_SEL net19 net20 VDD VSS / ++ RSC_IHPSG13_DFPQD_MSAFFX2 +XA_DREG A_BIST_EN_I A_BIST_DW_I A_DCLK_B_L A_DW_I A_DI_R net22 VDD VSS ++ / RSC_IHPSG13_DFNQMX2IX1 +XA_BREG A_BIST_EN_I A_BIST_BM_I A_DCLK_B_L A_BM_I A_BM_R net21 VDD VSS ++ / RSC_IHPSG13_DFNQMX2IX1 +XA_DEC3<31> A_P1<1> A_P0<1> A_ADDR_DEC<7> net23<0> VDD VSS / ++ RSC_IHPSG13_NAND3X2 +XA_DEC3<30> A_P1<1> A_P0<1> A_ADDR_DEC<6> net23<1> VDD VSS / ++ RSC_IHPSG13_NAND3X2 +XA_DEC3<29> A_P1<1> A_P0<1> A_ADDR_DEC<5> net23<2> VDD VSS / ++ RSC_IHPSG13_NAND3X2 +XA_DEC3<28> A_P1<1> A_P0<1> A_ADDR_DEC<4> net23<3> VDD VSS / ++ RSC_IHPSG13_NAND3X2 +XA_DEC3<27> A_P1<1> A_P0<1> A_ADDR_DEC<3> net23<4> VDD VSS / ++ RSC_IHPSG13_NAND3X2 +XA_DEC3<26> A_P1<1> A_P0<1> A_ADDR_DEC<2> net23<5> VDD VSS / ++ RSC_IHPSG13_NAND3X2 +XA_DEC3<25> A_P1<1> A_P0<1> A_ADDR_DEC<1> net23<6> VDD VSS / ++ RSC_IHPSG13_NAND3X2 +XA_DEC3<24> A_P1<1> A_P0<1> A_ADDR_DEC<0> net23<7> VDD VSS / ++ RSC_IHPSG13_NAND3X2 +XA_DEC3<23> A_P1<1> A_N0<1> A_ADDR_DEC<7> net23<8> VDD VSS / ++ RSC_IHPSG13_NAND3X2 +XA_DEC3<22> A_P1<1> A_N0<1> A_ADDR_DEC<6> net23<9> VDD VSS / ++ RSC_IHPSG13_NAND3X2 +XA_DEC3<21> A_P1<1> A_N0<1> A_ADDR_DEC<5> net23<10> VDD VSS / ++ RSC_IHPSG13_NAND3X2 +XA_DEC3<20> A_P1<1> A_N0<1> A_ADDR_DEC<4> net23<11> VDD VSS / ++ RSC_IHPSG13_NAND3X2 +XA_DEC3<19> A_P1<1> A_N0<1> A_ADDR_DEC<3> net23<12> VDD VSS / ++ RSC_IHPSG13_NAND3X2 +XA_DEC3<18> A_P1<1> A_N0<1> A_ADDR_DEC<2> net23<13> VDD VSS / ++ RSC_IHPSG13_NAND3X2 +XA_DEC3<17> A_P1<1> A_N0<1> A_ADDR_DEC<1> net23<14> VDD VSS / ++ RSC_IHPSG13_NAND3X2 +XA_DEC3<16> A_P1<1> A_N0<1> A_ADDR_DEC<0> net23<15> VDD VSS / ++ RSC_IHPSG13_NAND3X2 +XA_DEC3<15> A_N1<0> A_P0<0> A_ADDR_DEC<7> net23<16> VDD VSS / ++ RSC_IHPSG13_NAND3X2 +XA_DEC3<14> A_N1<0> A_P0<0> A_ADDR_DEC<6> net23<17> VDD VSS / ++ RSC_IHPSG13_NAND3X2 +XA_DEC3<13> A_N1<0> A_P0<0> A_ADDR_DEC<5> net23<18> VDD VSS / ++ RSC_IHPSG13_NAND3X2 +XA_DEC3<12> A_N1<0> A_P0<0> A_ADDR_DEC<4> net23<19> VDD VSS / ++ RSC_IHPSG13_NAND3X2 +XA_DEC3<11> A_N1<0> A_P0<0> A_ADDR_DEC<3> net23<20> VDD VSS / ++ RSC_IHPSG13_NAND3X2 +XA_DEC3<10> A_N1<0> A_P0<0> A_ADDR_DEC<2> net23<21> VDD VSS / ++ RSC_IHPSG13_NAND3X2 +XA_DEC3<9> A_N1<0> A_P0<0> A_ADDR_DEC<1> net23<22> VDD VSS / ++ RSC_IHPSG13_NAND3X2 +XA_DEC3<8> A_N1<0> A_P0<0> A_ADDR_DEC<0> net23<23> VDD VSS / ++ RSC_IHPSG13_NAND3X2 +XA_DEC3<7> A_N1<0> A_N0<0> A_ADDR_DEC<7> net23<24> VDD VSS / ++ RSC_IHPSG13_NAND3X2 +XA_DEC3<6> A_N1<0> A_N0<0> A_ADDR_DEC<6> net23<25> VDD VSS / ++ RSC_IHPSG13_NAND3X2 +XA_DEC3<5> A_N1<0> A_N0<0> A_ADDR_DEC<5> net23<26> VDD VSS / ++ RSC_IHPSG13_NAND3X2 +XA_DEC3<4> A_N1<0> A_N0<0> A_ADDR_DEC<4> net23<27> VDD VSS / ++ RSC_IHPSG13_NAND3X2 +XA_DEC3<3> A_N1<0> A_N0<0> A_ADDR_DEC<3> net23<28> VDD VSS / ++ RSC_IHPSG13_NAND3X2 +XA_DEC3<2> A_N1<0> A_N0<0> A_ADDR_DEC<2> net23<29> VDD VSS / ++ RSC_IHPSG13_NAND3X2 +XA_DEC3<1> A_N1<0> A_N0<0> A_ADDR_DEC<1> net23<30> VDD VSS / ++ RSC_IHPSG13_NAND3X2 +XA_DEC3<0> A_N1<0> A_N0<0> A_ADDR_DEC<0> net23<31> VDD VSS / ++ RSC_IHPSG13_NAND3X2 +XA_I89 A_DCLK_B_L A_DCLK_B_R / RSC_IHPSG13_MET3RES +XA_I91 A_RCLK_B_L A_RCLK_B_R / RSC_IHPSG13_MET3RES +XA_I90 A_WCLK_B_L A_WCLK_B_R / RSC_IHPSG13_MET3RES +XA_I88 A_DCLK_L A_DCLK_R / RSC_IHPSG13_MET3RES +XA_I87 A_WCLK_L A_WCLK_R / RSC_IHPSG13_MET3RES +XA_R2 A_RCLK_L A_RCLK_R / RSC_IHPSG13_MET3RES +XA_BM_TIEH A_TIEH_O VDD VSS / RSC_IHPSG13_TIEH +.ENDS + +.SUBCKT RM_IHPSG13_512x8_c2_1P_COLDRV13X12 ADDR_COL_I<1> ADDR_COL_I<0> ADDR_COL_O<1> ++ ADDR_COL_O<0> ADDR_DEC_I<7> ADDR_DEC_I<6> ADDR_DEC_I<5> ADDR_DEC_I<4> ++ ADDR_DEC_I<3> ADDR_DEC_I<2> ADDR_DEC_I<1> ADDR_DEC_I<0> ADDR_DEC_O<7> ++ ADDR_DEC_O<6> ADDR_DEC_O<5> ADDR_DEC_O<4> ADDR_DEC_O<3> ADDR_DEC_O<2> ++ ADDR_DEC_O<1> ADDR_DEC_O<0> DCLK_I DCLK_O RCLK_I RCLK_O WCLK_I WCLK_O ++ VDD VSS +XI1<1> VDD VSS / RSC_IHPSG13_FILLCAP4 +XI1<0> VDD VSS / RSC_IHPSG13_FILLCAP4 +XI0<1> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI0<0> VDD VSS / RSC_IHPSG13_FILLCAP8 +XADDR_COL_DRV<1> ADDR_COL_I<1> ADDR_COL_O<1> VDD VSS / ++ RSC_IHPSG13_CBUFX12 +XADDR_COL_DRV<0> ADDR_COL_I<0> ADDR_COL_O<0> VDD VSS / ++ RSC_IHPSG13_CBUFX12 +XADDR_DEC_DRV<7> ADDR_DEC_I<7> ADDR_DEC_O<7> VDD VSS / ++ RSC_IHPSG13_CBUFX12 +XADDR_DEC_DRV<6> ADDR_DEC_I<6> ADDR_DEC_O<6> VDD VSS / ++ RSC_IHPSG13_CBUFX12 +XADDR_DEC_DRV<5> ADDR_DEC_I<5> ADDR_DEC_O<5> VDD VSS / ++ RSC_IHPSG13_CBUFX12 +XADDR_DEC_DRV<4> ADDR_DEC_I<4> ADDR_DEC_O<4> VDD VSS / ++ RSC_IHPSG13_CBUFX12 +XADDR_DEC_DRV<3> ADDR_DEC_I<3> ADDR_DEC_O<3> VDD VSS / ++ RSC_IHPSG13_CBUFX12 +XADDR_DEC_DRV<2> ADDR_DEC_I<2> ADDR_DEC_O<2> VDD VSS / ++ RSC_IHPSG13_CBUFX12 +XADDR_DEC_DRV<1> ADDR_DEC_I<1> ADDR_DEC_O<1> VDD VSS / ++ RSC_IHPSG13_CBUFX12 +XADDR_DEC_DRV<0> ADDR_DEC_I<0> ADDR_DEC_O<0> VDD VSS / ++ RSC_IHPSG13_CBUFX12 +XDCLK_DRV DCLK_I DCLK_O VDD VSS / RSC_IHPSG13_CBUFX12 +XRCLK_DRV RCLK_I RCLK_O VDD VSS / RSC_IHPSG13_CBUFX12 +XWCLK_DRV WCLK_I WCLK_O VDD VSS / RSC_IHPSG13_CBUFX12 +.ENDS +.SUBCKT RM_IHPSG13_512x8_c2_1P_WLDRV16X12 A<15> A<14> A<13> A<12> A<11> A<10> A<9> A<8> ++ A<7> A<6> A<5> A<4> A<3> A<2> A<1> A<0> Z<15> Z<14> Z<13> Z<12> Z<11> Z<10> ++ Z<9> Z<8> Z<7> Z<6> Z<5> Z<4> Z<3> Z<2> Z<1> Z<0> VDD VSS +XBUF<15> A<15> Z<15> VDD VSS / RSC_IHPSG13_WLDRVX12 +XBUF<14> A<14> Z<14> VDD VSS / RSC_IHPSG13_WLDRVX12 +XBUF<13> A<13> Z<13> VDD VSS / RSC_IHPSG13_WLDRVX12 +XBUF<12> A<12> Z<12> VDD VSS / RSC_IHPSG13_WLDRVX12 +XBUF<11> A<11> Z<11> VDD VSS / RSC_IHPSG13_WLDRVX12 +XBUF<10> A<10> Z<10> VDD VSS / RSC_IHPSG13_WLDRVX12 +XBUF<9> A<9> Z<9> VDD VSS / RSC_IHPSG13_WLDRVX12 +XBUF<8> A<8> Z<8> VDD VSS / RSC_IHPSG13_WLDRVX12 +XBUF<7> A<7> Z<7> VDD VSS / RSC_IHPSG13_WLDRVX12 +XBUF<6> A<6> Z<6> VDD VSS / RSC_IHPSG13_WLDRVX12 +XBUF<5> A<5> Z<5> VDD VSS / RSC_IHPSG13_WLDRVX12 +XBUF<4> A<4> Z<4> VDD VSS / RSC_IHPSG13_WLDRVX12 +XBUF<3> A<3> Z<3> VDD VSS / RSC_IHPSG13_WLDRVX12 +XBUF<2> A<2> Z<2> VDD VSS / RSC_IHPSG13_WLDRVX12 +XBUF<1> A<1> Z<1> VDD VSS / RSC_IHPSG13_WLDRVX12 +XBUF<0> A<0> Z<0> VDD VSS / RSC_IHPSG13_WLDRVX12 +.ENDS + + + +.SUBCKT RM_IHPSG13_512x8_c2_2P_COLDRV13X8 ADDR_COL_I<1> ADDR_COL_I<0> ADDR_COL_O<1> ++ ADDR_COL_O<0> ADDR_DEC_I<7> ADDR_DEC_I<6> ADDR_DEC_I<5> ADDR_DEC_I<4> ++ ADDR_DEC_I<3> ADDR_DEC_I<2> ADDR_DEC_I<1> ADDR_DEC_I<0> ADDR_DEC_O<7> ++ ADDR_DEC_O<6> ADDR_DEC_O<5> ADDR_DEC_O<4> ADDR_DEC_O<3> ADDR_DEC_O<2> ++ ADDR_DEC_O<1> ADDR_DEC_O<0> DCLK_I DCLK_O RCLK_I RCLK_O WCLK_I WCLK_O ++ VDD VSS +XI0<5> VDD VSS / RSC_IHPSG13_FILLCAP4 +XI0<4> VDD VSS / RSC_IHPSG13_FILLCAP4 +XI0<3> VDD VSS / RSC_IHPSG13_FILLCAP4 +XI0<2> VDD VSS / RSC_IHPSG13_FILLCAP4 +XI0<1> VDD VSS / RSC_IHPSG13_FILLCAP4 +XWCLK_DRV WCLK_I WCLK_O VDD VSS / RSC_IHPSG13_CBUFX8 +XRCLK_DRV RCLK_I RCLK_O VDD VSS / RSC_IHPSG13_CBUFX8 +XDCLK_DRV DCLK_I DCLK_O VDD VSS / RSC_IHPSG13_CBUFX8 +XADDR_COL_DRV<1> ADDR_COL_I<1> ADDR_COL_O<1> VDD VSS / ++ RSC_IHPSG13_CBUFX8 +XADDR_COL_DRV<0> ADDR_COL_I<0> ADDR_COL_O<0> VDD VSS / ++ RSC_IHPSG13_CBUFX8 +XADDR_DEC_DRV<7> ADDR_DEC_I<7> ADDR_DEC_O<7> VDD VSS / ++ RSC_IHPSG13_CBUFX8 +XADDR_DEC_DRV<6> ADDR_DEC_I<6> ADDR_DEC_O<6> VDD VSS / ++ RSC_IHPSG13_CBUFX8 +XADDR_DEC_DRV<5> ADDR_DEC_I<5> ADDR_DEC_O<5> VDD VSS / ++ RSC_IHPSG13_CBUFX8 +XADDR_DEC_DRV<4> ADDR_DEC_I<4> ADDR_DEC_O<4> VDD VSS / ++ RSC_IHPSG13_CBUFX8 +XADDR_DEC_DRV<3> ADDR_DEC_I<3> ADDR_DEC_O<3> VDD VSS / ++ RSC_IHPSG13_CBUFX8 +XADDR_DEC_DRV<2> ADDR_DEC_I<2> ADDR_DEC_O<2> VDD VSS / ++ RSC_IHPSG13_CBUFX8 +XADDR_DEC_DRV<1> ADDR_DEC_I<1> ADDR_DEC_O<1> VDD VSS / ++ RSC_IHPSG13_CBUFX8 +XADDR_DEC_DRV<0> ADDR_DEC_I<0> ADDR_DEC_O<0> VDD VSS / ++ RSC_IHPSG13_CBUFX8 +XI1<3> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI1<2> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI1<1> VDD VSS / RSC_IHPSG13_FILLCAP8 +.ENDS +.SUBCKT RSC_IHPSG13_WLDRVX8 A Z VDD VSS +MN1 Z net6 VSS VSS sg13_lv_nmos m=1 w=1.41u l=130.00n ng=2 nrd=0 nrs=0 +MN0 net6 A VSS VSS sg13_lv_nmos m=1 w=1.8u l=130.00n ng=2 nrd=0 nrs=0 +MP1 Z net6 VDD VDD sg13_lv_pmos m=1 w=6.48u l=130.00n ng=4 nrd=0 nrs=0 +MP0 net6 A VDD VDD sg13_lv_pmos m=1 w=900.0n l=130.00n ng=1 nrd=0 nrs=0 +.ENDS +.SUBCKT RM_IHPSG13_512x8_c2_2P_WLDRV16X8 A<15> A<14> A<13> A<12> A<11> A<10> A<9> A<8> ++ A<7> A<6> A<5> A<4> A<3> A<2> A<1> A<0> Z<15> Z<14> Z<13> Z<12> Z<11> Z<10> ++ Z<9> Z<8> Z<7> Z<6> Z<5> Z<4> Z<3> Z<2> Z<1> Z<0> VDD VSS +XBUF<15> A<15> Z<15> VDD VSS / RSC_IHPSG13_WLDRVX8 +XBUF<14> A<14> Z<14> VDD VSS / RSC_IHPSG13_WLDRVX8 +XBUF<13> A<13> Z<13> VDD VSS / RSC_IHPSG13_WLDRVX8 +XBUF<12> A<12> Z<12> VDD VSS / RSC_IHPSG13_WLDRVX8 +XBUF<11> A<11> Z<11> VDD VSS / RSC_IHPSG13_WLDRVX8 +XBUF<10> A<10> Z<10> VDD VSS / RSC_IHPSG13_WLDRVX8 +XBUF<9> A<9> Z<9> VDD VSS / RSC_IHPSG13_WLDRVX8 +XBUF<8> A<8> Z<8> VDD VSS / RSC_IHPSG13_WLDRVX8 +XBUF<7> A<7> Z<7> VDD VSS / RSC_IHPSG13_WLDRVX8 +XBUF<6> A<6> Z<6> VDD VSS / RSC_IHPSG13_WLDRVX8 +XBUF<5> A<5> Z<5> VDD VSS / RSC_IHPSG13_WLDRVX8 +XBUF<4> A<4> Z<4> VDD VSS / RSC_IHPSG13_WLDRVX8 +XBUF<3> A<3> Z<3> VDD VSS / RSC_IHPSG13_WLDRVX8 +XBUF<2> A<2> Z<2> VDD VSS / RSC_IHPSG13_WLDRVX8 +XBUF<1> A<1> Z<1> VDD VSS / RSC_IHPSG13_WLDRVX8 +XBUF<0> A<0> Z<0> VDD VSS / RSC_IHPSG13_WLDRVX8 +.ENDS + + + +.SUBCKT RM_IHPSG13_512x8_c2_2P_COLDEC2 ACLK_N ADDR<1> ADDR<0> ADDR_COL<1> ADDR_COL<0> ++ ADDR_DEC<7> ADDR_DEC<6> ADDR_DEC<5> ADDR_DEC<4> ADDR_DEC<3> ADDR_DEC<2> ++ ADDR_DEC<1> ADDR_DEC<0> BIST_ADDR<1> BIST_ADDR<0> BIST_EN_I VDD VSS +XI16<17> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI16<16> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI16<15> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI16<14> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI16<13> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI16<12> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI16<11> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI16<10> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI16<9> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI16<8> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI16<7> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI16<6> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI16<5> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI16<4> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI16<3> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI16<2> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI16<1> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI18<24> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI18<23> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI18<22> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI18<21> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI18<20> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI18<19> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI18<18> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI18<17> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI18<16> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI18<15> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI18<14> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI18<13> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI18<12> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI18<11> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI18<10> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI18<9> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI18<8> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI18<7> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI18<6> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI18<5> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI18<4> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI18<3> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI18<2> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI18<1> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI1<3> PADR<0> PADR<1> addr_n<3> VDD VSS / RSC_IHPSG13_NAND2X2 +XI1<2> NADR<0> PADR<1> addr_n<2> VDD VSS / RSC_IHPSG13_NAND2X2 +XI1<1> PADR<0> NADR<1> addr_n<1> VDD VSS / RSC_IHPSG13_NAND2X2 +XI1<0> NADR<0> NADR<1> addr_n<0> VDD VSS / RSC_IHPSG13_NAND2X2 +XI17<1> ADDR_COL<1> VDD VSS / RSC_IHPSG13_TIEL +XI17<0> ADDR_COL<0> VDD VSS / RSC_IHPSG13_TIEL +XI14<3> ADDR_DEC<7> VDD VSS / RSC_IHPSG13_TIEL +XI14<2> ADDR_DEC<6> VDD VSS / RSC_IHPSG13_TIEL +XI14<1> ADDR_DEC<5> VDD VSS / RSC_IHPSG13_TIEL +XI14<0> ADDR_DEC<4> VDD VSS / RSC_IHPSG13_TIEL +XI13<1> NADR<1> PADR<1> VDD VSS / RSC_IHPSG13_INVX2 +XI13<0> NADR<0> PADR<0> VDD VSS / RSC_IHPSG13_INVX2 +XI3<1> padr_int<1> NADR<1> VDD VSS / RSC_IHPSG13_INVX2 +XI3<0> padr_int<0> NADR<0> VDD VSS / RSC_IHPSG13_INVX2 +XI2<3> addr_n<3> ADDR_DEC<3> VDD VSS / RSC_IHPSG13_INVX2 +XI2<2> addr_n<2> ADDR_DEC<2> VDD VSS / RSC_IHPSG13_INVX2 +XI2<1> addr_n<1> ADDR_DEC<1> VDD VSS / RSC_IHPSG13_INVX2 +XI2<0> addr_n<0> ADDR_DEC<0> VDD VSS / RSC_IHPSG13_INVX2 +XDFF<1> BIST_EN_I BIST_ADDR<1> ACLK_N ADDR<1> padr_int<1> net12<0> VDD ++ VSS / RSC_IHPSG13_DFNQMX2IX1 +XDFF<0> BIST_EN_I BIST_ADDR<0> ACLK_N ADDR<0> padr_int<0> net12<1> VDD ++ VSS / RSC_IHPSG13_DFNQMX2IX1 +XI15<5> VDD VSS / RSC_IHPSG13_FILLCAP4 +XI15<4> VDD VSS / RSC_IHPSG13_FILLCAP4 +XI15<3> VDD VSS / RSC_IHPSG13_FILLCAP4 +XI15<2> VDD VSS / RSC_IHPSG13_FILLCAP4 +XI15<1> VDD VSS / RSC_IHPSG13_FILLCAP4 +XI19<4> VDD VSS / RSC_IHPSG13_FILLCAP4 +XI19<3> VDD VSS / RSC_IHPSG13_FILLCAP4 +XI19<2> VDD VSS / RSC_IHPSG13_FILLCAP4 +XI19<1> VDD VSS / RSC_IHPSG13_FILLCAP4 +.ENDS +.SUBCKT RM_IHPSG13_512x8_c2_2P_COLCTRL2 A_ADDR_DEC<3> A_ADDR_DEC<2> A_ADDR_DEC<1> ++ A_ADDR_DEC<0> A_BIST_BM_I A_BIST_DW_I A_BIST_EN_I A_BLC<3> A_BLC<2> A_BLC<1> ++ A_BLC<0> A_BLT<3> A_BLT<2> A_BLT<1> A_BLT<0> A_BM_I A_DCLK_B_L A_DCLK_B_R ++ A_DCLK_L A_DCLK_R A_DR_O A_DW_I A_RCLK_B_L A_RCLK_B_R A_RCLK_L A_RCLK_R ++ A_TIEH_O A_WCLK_B_L A_WCLK_B_R A_WCLK_L A_WCLK_R B_ADDR_DEC<3> B_ADDR_DEC<2> ++ B_ADDR_DEC<1> B_ADDR_DEC<0> B_BIST_BM_I B_BIST_DW_I B_BIST_EN_I B_BLC<3> ++ B_BLC<2> B_BLC<1> B_BLC<0> B_BLT<3> B_BLT<2> B_BLT<1> B_BLT<0> B_BM_I ++ B_DCLK_B_L B_DCLK_B_R B_DCLK_L B_DCLK_R B_DR_O B_DW_I B_RCLK_B_L B_RCLK_B_R ++ B_RCLK_L B_RCLK_R B_TIEH_O B_WCLK_B_L B_WCLK_B_R B_WCLK_L B_WCLK_R VDD ++ VSS +XB_DREG B_BIST_EN_I B_BIST_DW_I B_DCLK_B_L B_DW_I B_DI_R net046 VDD ++ VSS / RSC_IHPSG13_DFNQMX2IX1 +XB_BREG B_BIST_EN_I B_BIST_BM_I B_DCLK_B_L B_BM_I B_BM_R net045 VDD ++ VSS / RSC_IHPSG13_DFNQMX2IX1 +XA_DREG A_BIST_EN_I A_BIST_DW_I A_DCLK_B_L A_DW_I A_DI_R net22 VDD VSS ++ / RSC_IHPSG13_DFNQMX2IX1 +XA_BREG A_BIST_EN_I A_BIST_BM_I A_DCLK_B_L A_BM_I A_BM_R net23 VDD VSS ++ / RSC_IHPSG13_DFNQMX2IX1 +XB_CAPS VDD VSS / RSC_IHPSG13_FILLCAP4 +XA_CAPS VDD VSS / RSC_IHPSG13_FILLCAP4 +XB_I75 B_DI_R B_DO_WRITE_P B_WR_ONE VDD VSS / RSC_IHPSG13_AND2X2 +XB_I80 B_RCLK_B_L B_WCLK_B_L net041 VDD VSS / RSC_IHPSG13_AND2X2 +XB_I76 B_DI_N B_DO_WRITE_P B_WR_ZERO VDD VSS / RSC_IHPSG13_AND2X2 +XA_I80 A_RCLK_B_L A_WCLK_B_L net21 VDD VSS / RSC_IHPSG13_AND2X2 +XA_I75 A_DI_R A_DO_WRITE_P A_WR_ONE VDD VSS / RSC_IHPSG13_AND2X2 +XA_I76 A_DI_N A_DO_WRITE_P A_WR_ZERO VDD VSS / RSC_IHPSG13_AND2X2 +XB_I44 B_WCLK_B_L B_BM_N B_DO_WRITE_P VDD VSS / RSC_IHPSG13_NOR2X2 +XA_I44 A_WCLK_B_L A_BM_N A_DO_WRITE_P VDD VSS / RSC_IHPSG13_NOR2X2 +XB_I81 net041 B_PRE_N VDD VSS / RSC_IHPSG13_CINVX4_WN +XA_I81 net21 A_PRE_N VDD VSS / RSC_IHPSG13_CINVX4_WN +XB_BM_TIEH B_TIEH_O VDD VSS / RSC_IHPSG13_TIEH +XA_BM_TIEH A_TIEH_O VDD VSS / RSC_IHPSG13_TIEH +XA_I89 A_DCLK_B_L A_DCLK_B_R / RSC_IHPSG13_MET3RES +XA_I88 A_DCLK_L A_DCLK_R / RSC_IHPSG13_MET3RES +XA_I87 A_WCLK_L A_WCLK_R / RSC_IHPSG13_MET3RES +XA_I91 A_RCLK_B_L A_RCLK_B_R / RSC_IHPSG13_MET3RES +XB_I87 B_WCLK_L B_WCLK_R / RSC_IHPSG13_MET3RES +XB_I88 B_DCLK_L B_DCLK_R / RSC_IHPSG13_MET3RES +XB_I89 B_DCLK_B_L B_DCLK_B_R / RSC_IHPSG13_MET3RES +XB_I90 B_WCLK_B_L B_WCLK_B_R / RSC_IHPSG13_MET3RES +XB_R2 B_RCLK_L B_RCLK_R / RSC_IHPSG13_MET3RES +XB_I91 B_RCLK_B_L B_RCLK_B_R / RSC_IHPSG13_MET3RES +XA_R2 A_RCLK_L A_RCLK_R / RSC_IHPSG13_MET3RES +XA_I90 A_WCLK_B_L A_WCLK_B_R / RSC_IHPSG13_MET3RES +XAB_BLMUX A_BLC<3> A_BLC<2> A_BLC<1> A_BLC<0> A_BLC_SEL A_BLT<3> A_BLT<2> ++ A_BLT<1> A_BLT<0> A_BLT_SEL A_PRE_N A_ADDR_DEC<3> A_ADDR_DEC<2> ++ A_ADDR_DEC<1> A_ADDR_DEC<0> A_WR_ONE A_WR_ZERO B_BLC<3> B_BLC<2> B_BLC<1> ++ B_BLC<0> B_BLC_SEL B_BLT<3> B_BLT<2> B_BLT<1> B_BLT<0> B_BLT_SEL B_PRE_N ++ B_ADDR_DEC<3> B_ADDR_DEC<2> B_ADDR_DEC<1> B_ADDR_DEC<0> B_WR_ONE B_WR_ZERO ++ VDD VSS / RM_IHPSG13_512x8_c2_2P_BLDRV +XB_ISENSE B_SAE B_BLC_SEL B_BLT_SEL net039 net040 VDD VSS / ++ RSC_IHPSG13_DFPQD_MSAFFX2 +XA_ISENSE A_SAE A_BLC_SEL A_BLT_SEL net19 net20 VDD VSS / ++ RSC_IHPSG13_DFPQD_MSAFFX2 +XB_I78 B_RCLK_B_L B_SAE VDD VSS / RSC_IHPSG13_CBUFX2 +XA_I78 A_RCLK_B_L A_SAE VDD VSS / RSC_IHPSG13_CBUFX2 +XB_I83 B_BM_R B_BM_N VDD VSS / RSC_IHPSG13_INVX2 +XB_I49 B_DI_R B_DI_N VDD VSS / RSC_IHPSG13_INVX2 +XA_I83 A_BM_R A_BM_N VDD VSS / RSC_IHPSG13_INVX2 +XA_I49 A_DI_R A_DI_N VDD VSS / RSC_IHPSG13_INVX2 +XB_I51 net039 B_DR_O VDD VSS / RSC_IHPSG13_INVX4 +XA_I51 net19 A_DR_O VDD VSS / RSC_IHPSG13_INVX4 +XA_I69 A_DCLK_L A_DCLK_B_L VDD VSS / RSC_IHPSG13_CINVX2 +XA_I50 A_WCLK_L A_WCLK_B_L VDD VSS / RSC_IHPSG13_CINVX2 +XA_EBUF A_RCLK_L A_RCLK_B_L VDD VSS / RSC_IHPSG13_CINVX2 +XB_EBUF B_RCLK_L B_RCLK_B_L VDD VSS / RSC_IHPSG13_CINVX2 +XB_I50 B_WCLK_L B_WCLK_B_L VDD VSS / RSC_IHPSG13_CINVX2 +XB_I69 B_DCLK_L B_DCLK_B_L VDD VSS / RSC_IHPSG13_CINVX2 +.ENDS +.SUBCKT RM_IHPSG13_512x8_c2_2P_COLDRV13_FILL4C2 VDD VSS +XI0<2> VDD VSS / RSC_IHPSG13_FILLCAP4 +XI0<1> VDD VSS / RSC_IHPSG13_FILLCAP4 +.ENDS + + +.SUBCKT RM_IHPSG13_512x8_c2_2P_ROWDEC7 ADDR_N_I<6> ADDR_N_I<5> ADDR_N_I<4> ADDR_N_I<3> ++ ADDR_N_I<2> ADDR_N_I<1> ADDR_N_I<0> CS_I ECLK_I WL_O<127> WL_O<126> ++ WL_O<125> WL_O<124> WL_O<123> WL_O<122> WL_O<121> WL_O<120> WL_O<119> ++ WL_O<118> WL_O<117> WL_O<116> WL_O<115> WL_O<114> WL_O<113> WL_O<112> ++ WL_O<111> WL_O<110> WL_O<109> WL_O<108> WL_O<107> WL_O<106> WL_O<105> ++ WL_O<104> WL_O<103> WL_O<102> WL_O<101> WL_O<100> WL_O<99> WL_O<98> WL_O<97> ++ WL_O<96> WL_O<95> WL_O<94> WL_O<93> WL_O<92> WL_O<91> WL_O<90> WL_O<89> ++ WL_O<88> WL_O<87> WL_O<86> WL_O<85> WL_O<84> WL_O<83> WL_O<82> WL_O<81> ++ WL_O<80> WL_O<79> WL_O<78> WL_O<77> WL_O<76> WL_O<75> WL_O<74> WL_O<73> ++ WL_O<72> WL_O<71> WL_O<70> WL_O<69> WL_O<68> WL_O<67> WL_O<66> WL_O<65> ++ WL_O<64> WL_O<63> WL_O<62> WL_O<61> WL_O<60> WL_O<59> WL_O<58> WL_O<57> ++ WL_O<56> WL_O<55> WL_O<54> WL_O<53> WL_O<52> WL_O<51> WL_O<50> WL_O<49> ++ WL_O<48> WL_O<47> WL_O<46> WL_O<45> WL_O<44> WL_O<43> WL_O<42> WL_O<41> ++ WL_O<40> WL_O<39> WL_O<38> WL_O<37> WL_O<36> WL_O<35> WL_O<34> WL_O<33> ++ WL_O<32> WL_O<31> WL_O<30> WL_O<29> WL_O<28> WL_O<27> WL_O<26> WL_O<25> ++ WL_O<24> WL_O<23> WL_O<22> WL_O<21> WL_O<20> WL_O<19> WL_O<18> WL_O<17> ++ WL_O<16> WL_O<15> WL_O<14> WL_O<13> WL_O<12> WL_O<11> WL_O<10> WL_O<9> ++ WL_O<8> WL_O<7> WL_O<6> WL_O<5> WL_O<4> WL_O<3> WL_O<2> WL_O<1> WL_O<0> ++ VDD VSS +XSEL<7> ADDR_N_I<3> ADDR_N_I<2> ADDR_N_I<1> ADDR_N_I<0> CS00<7> ECLK_H<7> ++ ECLK_H<8> ECLK_B<7> ECLK_B<8> WL_O<127> WL_O<126> WL_O<125> WL_O<124> ++ WL_O<123> WL_O<122> WL_O<121> WL_O<120> WL_O<119> WL_O<118> WL_O<117> ++ WL_O<116> WL_O<115> WL_O<114> WL_O<113> WL_O<112> VDD VSS / ++ RM_IHPSG13_512x8_c2_2P_DEC04 +XSEL<6> ADDR_N_I<3> ADDR_N_I<2> ADDR_N_I<1> ADDR_N_I<0> CS00<6> ECLK_H<6> ++ ECLK_H<7> ECLK_B<6> ECLK_B<7> WL_O<111> WL_O<110> WL_O<109> WL_O<108> ++ WL_O<107> WL_O<106> WL_O<105> WL_O<104> WL_O<103> WL_O<102> WL_O<101> ++ WL_O<100> WL_O<99> WL_O<98> WL_O<97> WL_O<96> VDD VSS / ++ RM_IHPSG13_512x8_c2_2P_DEC04 +XSEL<5> ADDR_N_I<3> ADDR_N_I<2> ADDR_N_I<1> ADDR_N_I<0> CS00<5> ECLK_H<5> ++ ECLK_H<6> ECLK_B<5> ECLK_B<6> WL_O<95> WL_O<94> WL_O<93> WL_O<92> WL_O<91> ++ WL_O<90> WL_O<89> WL_O<88> WL_O<87> WL_O<86> WL_O<85> WL_O<84> WL_O<83> ++ WL_O<82> WL_O<81> WL_O<80> VDD VSS / RM_IHPSG13_512x8_c2_2P_DEC04 +XSEL<4> ADDR_N_I<3> ADDR_N_I<2> ADDR_N_I<1> ADDR_N_I<0> CS00<4> ECLK_H<4> ++ ECLK_H<5> ECLK_B<4> ECLK_B<5> WL_O<79> WL_O<78> WL_O<77> WL_O<76> WL_O<75> ++ WL_O<74> WL_O<73> WL_O<72> WL_O<71> WL_O<70> WL_O<69> WL_O<68> WL_O<67> ++ WL_O<66> WL_O<65> WL_O<64> VDD VSS / RM_IHPSG13_512x8_c2_2P_DEC04 +XSEL<3> ADDR_N_I<3> ADDR_N_I<2> ADDR_N_I<1> ADDR_N_I<0> CS00<3> ECLK_H<3> ++ ECLK_H<4> ECLK_B<3> ECLK_B<4> WL_O<63> WL_O<62> WL_O<61> WL_O<60> WL_O<59> ++ WL_O<58> WL_O<57> WL_O<56> WL_O<55> WL_O<54> WL_O<53> WL_O<52> WL_O<51> ++ WL_O<50> WL_O<49> WL_O<48> VDD VSS / RM_IHPSG13_512x8_c2_2P_DEC04 +XSEL<2> ADDR_N_I<3> ADDR_N_I<2> ADDR_N_I<1> ADDR_N_I<0> CS00<2> ECLK_H<2> ++ ECLK_H<3> ECLK_B<2> ECLK_B<3> WL_O<47> WL_O<46> WL_O<45> WL_O<44> WL_O<43> ++ WL_O<42> WL_O<41> WL_O<40> WL_O<39> WL_O<38> WL_O<37> WL_O<36> WL_O<35> ++ WL_O<34> WL_O<33> WL_O<32> VDD VSS / RM_IHPSG13_512x8_c2_2P_DEC04 +XSEL<1> ADDR_N_I<3> ADDR_N_I<2> ADDR_N_I<1> ADDR_N_I<0> CS00<1> ECLK_H<1> ++ ECLK_H<2> ECLK_B<1> ECLK_B<2> WL_O<31> WL_O<30> WL_O<29> WL_O<28> WL_O<27> ++ WL_O<26> WL_O<25> WL_O<24> WL_O<23> WL_O<22> WL_O<21> WL_O<20> WL_O<19> ++ WL_O<18> WL_O<17> WL_O<16> VDD VSS / RM_IHPSG13_512x8_c2_2P_DEC04 +XSEL<0> ADDR_N_I<3> ADDR_N_I<2> ADDR_N_I<1> ADDR_N_I<0> CS00<0> ECLK_I ++ ECLK_H<1> ECLK_B<0> ECLK_B<1> WL_O<15> WL_O<14> WL_O<13> WL_O<12> WL_O<11> ++ WL_O<10> WL_O<9> WL_O<8> WL_O<7> WL_O<6> WL_O<5> WL_O<4> WL_O<3> WL_O<2> ++ WL_O<1> WL_O<0> VDD VSS / RM_IHPSG13_512x8_c2_2P_DEC04 +XDEC11<1> ADDR_N_I<5> ADDR_N_I<4> CS04<1> CS00<7> VDD VSS / ++ RM_IHPSG13_512x8_c2_2P_DEC03 +XDEC11<0> ADDR_N_I<5> ADDR_N_I<4> CS04<0> CS00<3> VDD VSS / ++ RM_IHPSG13_512x8_c2_2P_DEC03 +XDEC01<2> ADDR_N_I<7> ADDR_N_I<6> CS_I CS04<1> VDD VSS / ++ RM_IHPSG13_512x8_c2_2P_DEC01 +XDEC01<1> ADDR_N_I<5> ADDR_N_I<4> CS04<1> CS00<5> VDD VSS / ++ RM_IHPSG13_512x8_c2_2P_DEC01 +XDEC01<0> ADDR_N_I<5> ADDR_N_I<4> CS04<0> CS00<1> VDD VSS / ++ RM_IHPSG13_512x8_c2_2P_DEC01 +XL2<66> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<65> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<64> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<63> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<62> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<61> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<60> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<59> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<58> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<57> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<56> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<55> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<54> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<53> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<52> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<51> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<50> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<49> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<48> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<47> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<46> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<45> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<44> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<43> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<42> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<41> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<40> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<39> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<38> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<37> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<36> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<35> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<34> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<33> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<32> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<31> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<30> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<29> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<28> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<27> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<26> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<25> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<24> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<23> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<22> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<21> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<20> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<19> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<18> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<17> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<16> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<15> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<14> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<13> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<12> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<11> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<10> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<9> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<8> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<7> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<6> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<5> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<4> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<3> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<2> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<1> VDD VSS / RSC_IHPSG13_FILLCAP8 +XDEC10<1> ADDR_N_I<5> ADDR_N_I<4> CS04<1> CS00<6> VDD VSS / ++ RM_IHPSG13_512x8_c2_2P_DEC02 +XDEC10<0> ADDR_N_I<5> ADDR_N_I<4> CS04<0> CS00<2> VDD VSS / ++ RM_IHPSG13_512x8_c2_2P_DEC02 +XDEC00<2> ADDR_N_I<7> ADDR_N_I<6> CS_I CS04<0> VDD VSS / ++ RM_IHPSG13_512x8_c2_2P_DEC00 +XDEC00<1> ADDR_N_I<5> ADDR_N_I<4> CS04<1> CS00<4> VDD VSS / ++ RM_IHPSG13_512x8_c2_2P_DEC00 +XDEC00<0> ADDR_N_I<5> ADDR_N_I<4> CS04<0> CS00<0> VDD VSS / ++ RM_IHPSG13_512x8_c2_2P_DEC00 +XI0 ADDR_N_I<7> VDD VSS / RSC_IHPSG13_TIEL +.ENDS +.SUBCKT RM_IHPSG13_512x8_c2_2P_ROWREG7 ACLK_N_I ADDR_I<6> ADDR_I<5> ADDR_I<4> ADDR_I<3> ++ ADDR_I<2> ADDR_I<1> ADDR_I<0> ADDR_N_O<6> ADDR_N_O<5> ADDR_N_O<4> ++ ADDR_N_O<3> ADDR_N_O<2> ADDR_N_O<1> ADDR_N_O<0> BIST_ADDR_I<6> ++ BIST_ADDR_I<5> BIST_ADDR_I<4> BIST_ADDR_I<3> BIST_ADDR_I<2> BIST_ADDR_I<1> ++ BIST_ADDR_I<0> BIST_EN_I VDD VSS +XINV<6> q_int<6> qn_int<6> VDD VSS / RSC_IHPSG13_CINVX2 +XINV<5> q_int<5> qn_int<5> VDD VSS / RSC_IHPSG13_CINVX2 +XINV<4> q_int<4> qn_int<4> VDD VSS / RSC_IHPSG13_CINVX2 +XINV<3> q_int<3> qn_int<3> VDD VSS / RSC_IHPSG13_CINVX2 +XINV<2> q_int<2> qn_int<2> VDD VSS / RSC_IHPSG13_CINVX2 +XINV<1> q_int<1> qn_int<1> VDD VSS / RSC_IHPSG13_CINVX2 +XINV<0> q_int<0> qn_int<0> VDD VSS / RSC_IHPSG13_CINVX2 +XDRV<6> qn_int<6> ADDR_N_O<6> VDD VSS / RSC_IHPSG13_CINVX8 +XDRV<5> qn_int<5> ADDR_N_O<5> VDD VSS / RSC_IHPSG13_CINVX8 +XDRV<4> qn_int<4> ADDR_N_O<4> VDD VSS / RSC_IHPSG13_CINVX8 +XDRV<3> qn_int<3> ADDR_N_O<3> VDD VSS / RSC_IHPSG13_CINVX8 +XDRV<2> qn_int<2> ADDR_N_O<2> VDD VSS / RSC_IHPSG13_CINVX8 +XDRV<1> qn_int<1> ADDR_N_O<1> VDD VSS / RSC_IHPSG13_CINVX8 +XDRV<0> qn_int<0> ADDR_N_O<0> VDD VSS / RSC_IHPSG13_CINVX8 +XDFF<6> BIST_EN_I BIST_ADDR_I<6> ACLK_N_I ADDR_I<6> q_int<6> net2<0> VDD ++ VSS / RSC_IHPSG13_DFNQMX2IX1 +XDFF<5> BIST_EN_I BIST_ADDR_I<5> ACLK_N_I ADDR_I<5> q_int<5> net2<1> VDD ++ VSS / RSC_IHPSG13_DFNQMX2IX1 +XDFF<4> BIST_EN_I BIST_ADDR_I<4> ACLK_N_I ADDR_I<4> q_int<4> net2<2> VDD ++ VSS / RSC_IHPSG13_DFNQMX2IX1 +XDFF<3> BIST_EN_I BIST_ADDR_I<3> ACLK_N_I ADDR_I<3> q_int<3> net2<3> VDD ++ VSS / RSC_IHPSG13_DFNQMX2IX1 +XDFF<2> BIST_EN_I BIST_ADDR_I<2> ACLK_N_I ADDR_I<2> q_int<2> net2<4> VDD ++ VSS / RSC_IHPSG13_DFNQMX2IX1 +XDFF<1> BIST_EN_I BIST_ADDR_I<1> ACLK_N_I ADDR_I<1> q_int<1> net2<5> VDD ++ VSS / RSC_IHPSG13_DFNQMX2IX1 +XDFF<0> BIST_EN_I BIST_ADDR_I<0> ACLK_N_I ADDR_I<0> q_int<0> net2<6> VDD ++ VSS / RSC_IHPSG13_DFNQMX2IX1 +XI11<7> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI11<6> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI11<5> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI11<4> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI11<3> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI11<2> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI11<1> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI11<0> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI12<1> VDD VSS / RSC_IHPSG13_FILLCAP4 +XI12<0> VDD VSS / RSC_IHPSG13_FILLCAP4 +.ENDS + +.SUBCKT RM_IHPSG13_512x8_c2_2P_ROWDEC4 ADDR_N_I<3> ADDR_N_I<2> ADDR_N_I<1> ADDR_N_I<0> ++ CS_I ECLK_I WL_O<15> WL_O<14> WL_O<13> WL_O<12> WL_O<11> WL_O<10> WL_O<9> ++ WL_O<8> WL_O<7> WL_O<6> WL_O<5> WL_O<4> WL_O<3> WL_O<2> WL_O<1> WL_O<0> ++ VDD VSS +XL2<12> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<11> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<10> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<9> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<8> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<7> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<6> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<5> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<4> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<3> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<2> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<1> VDD VSS / RSC_IHPSG13_FILLCAP8 +XSEL ADDR_N_I<3> ADDR_N_I<2> ADDR_N_I<1> ADDR_N_I<0> CS_I ECLK_I ECLK_H<1> ++ ECLK_B<0> ECLK_B<1> WL_O<15> WL_O<14> WL_O<13> WL_O<12> WL_O<11> WL_O<10> ++ WL_O<9> WL_O<8> WL_O<7> WL_O<6> WL_O<5> WL_O<4> WL_O<3> WL_O<2> WL_O<1> ++ WL_O<0> VDD VSS / RM_IHPSG13_512x8_c2_2P_DEC04 +.ENDS +.SUBCKT RM_IHPSG13_512x8_c2_2P_ROWREG4 ACLK_N_I ADDR_I<3> ADDR_I<2> ADDR_I<1> ADDR_I<0> ++ ADDR_N_O<3> ADDR_N_O<2> ADDR_N_O<1> ADDR_N_O<0> BIST_ADDR_I<3> ++ BIST_ADDR_I<2> BIST_ADDR_I<1> BIST_ADDR_I<0> BIST_EN_I VDD VSS +XINV<3> q_int<3> qn_int<3> VDD VSS / RSC_IHPSG13_CINVX2 +XINV<2> q_int<2> qn_int<2> VDD VSS / RSC_IHPSG13_CINVX2 +XINV<1> q_int<1> qn_int<1> VDD VSS / RSC_IHPSG13_CINVX2 +XINV<0> q_int<0> qn_int<0> VDD VSS / RSC_IHPSG13_CINVX2 +XDRV<3> qn_int<3> ADDR_N_O<3> VDD VSS / RSC_IHPSG13_CINVX8 +XDRV<2> qn_int<2> ADDR_N_O<2> VDD VSS / RSC_IHPSG13_CINVX8 +XDRV<1> qn_int<1> ADDR_N_O<1> VDD VSS / RSC_IHPSG13_CINVX8 +XDRV<0> qn_int<0> ADDR_N_O<0> VDD VSS / RSC_IHPSG13_CINVX8 +XDFF<3> BIST_EN_I BIST_ADDR_I<3> ACLK_N_I ADDR_I<3> q_int<3> net7<0> VDD ++ VSS / RSC_IHPSG13_DFNQMX2IX1 +XDFF<2> BIST_EN_I BIST_ADDR_I<2> ACLK_N_I ADDR_I<2> q_int<2> net7<1> VDD ++ VSS / RSC_IHPSG13_DFNQMX2IX1 +XDFF<1> BIST_EN_I BIST_ADDR_I<1> ACLK_N_I ADDR_I<1> q_int<1> net7<2> VDD ++ VSS / RSC_IHPSG13_DFNQMX2IX1 +XDFF<0> BIST_EN_I BIST_ADDR_I<0> ACLK_N_I ADDR_I<0> q_int<0> net7<3> VDD ++ VSS / RSC_IHPSG13_DFNQMX2IX1 +XI11<20> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI11<19> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI11<18> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI11<17> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI11<16> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI11<15> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI11<14> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI11<13> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI11<12> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI11<11> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI11<10> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI11<9> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI11<8> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI11<7> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI11<6> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI11<5> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI11<4> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI11<3> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI11<2> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI11<1> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI12<4> VDD VSS / RSC_IHPSG13_FILLCAP4 +XI12<3> VDD VSS / RSC_IHPSG13_FILLCAP4 +XI12<2> VDD VSS / RSC_IHPSG13_FILLCAP4 +XI12<1> VDD VSS / RSC_IHPSG13_FILLCAP4 +XI12<0> VDD VSS / RSC_IHPSG13_FILLCAP4 +.ENDS + + +.SUBCKT RM_IHPSG13_512x8_c2_1P_BITKIT_TAP BLC BLT NW PW VDD VSS +.ENDS +.SUBCKT RM_IHPSG13_512x8_c2_1P_BITKIT_16x2_TAP A_BLC<1> A_BLC<0> A_BLT<1> A_BLT<0> ++ VDD_CORE VSS +XITAP<1> A_BLC<1> A_BLT<1> VDD_CORE VSS VDD_CORE VSS ++ / RM_IHPSG13_512x8_c2_1P_BITKIT_TAP +XITAP<0> A_BLC<0> A_BLT<0> VDD_CORE VSS VDD_CORE VSS ++ / RM_IHPSG13_512x8_c2_1P_BITKIT_TAP +XIEDGEBP_COL1<1> BLC<1> BLT<1> VDD_CORE VSS VDD_CORE ++ VSS / RM_IHPSG13_512x8_c2_1P_BITKIT_EDGE_TB +XIEDGEBP_COL1<0> BLC<1> BLT<1> VDD_CORE VSS VDD_CORE ++ VSS / RM_IHPSG13_512x8_c2_1P_BITKIT_EDGE_TB +XIEDGEBP_COL2<1> BLC<0> BLT<0> VDD_CORE VSS VDD_CORE ++ VSS / RM_IHPSG13_512x8_c2_1P_BITKIT_EDGE_TB +XIEDGEBP_COL2<0> BLC<0> BLT<0> VDD_CORE VSS VDD_CORE ++ VSS / RM_IHPSG13_512x8_c2_1P_BITKIT_EDGE_TB +.ENDS +.SUBCKT RM_IHPSG13_512x8_c2_1P_BITKIT_16x2_TAP_LR VDD_CORE VSS +XCORNER<1> VDD_CORE VSS VDD_CORE VSS / ++ RM_IHPSG13_512x8_c2_1P_BITKIT_CORNER +XCORNER<0> VDD_CORE VSS VDD_CORE VSS / ++ RM_IHPSG13_512x8_c2_1P_BITKIT_CORNER +XTAP_BORDER VDD_CORE VSS VDD_CORE VSS / ++ RM_IHPSG13_512x8_c2_1P_BITKIT_TAP_LR +.ENDS +.SUBCKT RM_IHPSG13_512x8_c2_1P_DEC03 ADDR<1> ADDR<0> CS CS_OUT VDD VSS +XDECINV net1 CS_OUT VDD VSS / RSC_IHPSG13_INVX4 +XI0 VDD VSS / RSC_IHPSG13_FILLCAP4 +XDEC ADDR<1> ADDR<0> CS net1 VDD VSS / RSC_IHPSG13_NAND3X2 +.ENDS +.SUBCKT RM_IHPSG13_512x8_c2_1P_DEC02 ADDR<1> ADDR<0> CS CS_OUT VDD VSS +XDECINV net1 CS_OUT VDD VSS / RSC_IHPSG13_INVX4 +XDEC ADDR<1> NADDR<0> CS net1 VDD VSS / RSC_IHPSG13_NAND3X2 +XI2 VDD VSS / RSC_IHPSG13_FILLCAP4 +XADDRINV ADDR<0> NADDR<0> VDD VSS / RSC_IHPSG13_INVX2 +.ENDS +.SUBCKT RM_IHPSG13_512x8_c2_1P_ROWDEC8 ADDR_N_I<7> ADDR_N_I<6> ADDR_N_I<5> ADDR_N_I<4> ++ ADDR_N_I<3> ADDR_N_I<2> ADDR_N_I<1> ADDR_N_I<0> CS_I ECLK_I WL_O<255> ++ WL_O<254> WL_O<253> WL_O<252> WL_O<251> WL_O<250> WL_O<249> WL_O<248> ++ WL_O<247> WL_O<246> WL_O<245> WL_O<244> WL_O<243> WL_O<242> WL_O<241> ++ WL_O<240> WL_O<239> WL_O<238> WL_O<237> WL_O<236> WL_O<235> WL_O<234> ++ WL_O<233> WL_O<232> WL_O<231> WL_O<230> WL_O<229> WL_O<228> WL_O<227> ++ WL_O<226> WL_O<225> WL_O<224> WL_O<223> WL_O<222> WL_O<221> WL_O<220> ++ WL_O<219> WL_O<218> WL_O<217> WL_O<216> WL_O<215> WL_O<214> WL_O<213> ++ WL_O<212> WL_O<211> WL_O<210> WL_O<209> WL_O<208> WL_O<207> WL_O<206> ++ WL_O<205> WL_O<204> WL_O<203> WL_O<202> WL_O<201> WL_O<200> WL_O<199> ++ WL_O<198> WL_O<197> WL_O<196> WL_O<195> WL_O<194> WL_O<193> WL_O<192> ++ WL_O<191> WL_O<190> WL_O<189> WL_O<188> WL_O<187> WL_O<186> WL_O<185> ++ WL_O<184> WL_O<183> WL_O<182> WL_O<181> WL_O<180> WL_O<179> WL_O<178> ++ WL_O<177> WL_O<176> WL_O<175> WL_O<174> WL_O<173> WL_O<172> WL_O<171> ++ WL_O<170> WL_O<169> WL_O<168> WL_O<167> WL_O<166> WL_O<165> WL_O<164> ++ WL_O<163> WL_O<162> WL_O<161> WL_O<160> WL_O<159> WL_O<158> WL_O<157> ++ WL_O<156> WL_O<155> WL_O<154> WL_O<153> WL_O<152> WL_O<151> WL_O<150> ++ WL_O<149> WL_O<148> WL_O<147> WL_O<146> WL_O<145> WL_O<144> WL_O<143> ++ WL_O<142> WL_O<141> WL_O<140> WL_O<139> WL_O<138> WL_O<137> WL_O<136> ++ WL_O<135> WL_O<134> WL_O<133> WL_O<132> WL_O<131> WL_O<130> WL_O<129> ++ WL_O<128> WL_O<127> WL_O<126> WL_O<125> WL_O<124> WL_O<123> WL_O<122> ++ WL_O<121> WL_O<120> WL_O<119> WL_O<118> WL_O<117> WL_O<116> WL_O<115> ++ WL_O<114> WL_O<113> WL_O<112> WL_O<111> WL_O<110> WL_O<109> WL_O<108> ++ WL_O<107> WL_O<106> WL_O<105> WL_O<104> WL_O<103> WL_O<102> WL_O<101> ++ WL_O<100> WL_O<99> WL_O<98> WL_O<97> WL_O<96> WL_O<95> WL_O<94> WL_O<93> ++ WL_O<92> WL_O<91> WL_O<90> WL_O<89> WL_O<88> WL_O<87> WL_O<86> WL_O<85> ++ WL_O<84> WL_O<83> WL_O<82> WL_O<81> WL_O<80> WL_O<79> WL_O<78> WL_O<77> ++ WL_O<76> WL_O<75> WL_O<74> WL_O<73> WL_O<72> WL_O<71> WL_O<70> WL_O<69> ++ WL_O<68> WL_O<67> WL_O<66> WL_O<65> WL_O<64> WL_O<63> WL_O<62> WL_O<61> ++ WL_O<60> WL_O<59> WL_O<58> WL_O<57> WL_O<56> WL_O<55> WL_O<54> WL_O<53> ++ WL_O<52> WL_O<51> WL_O<50> WL_O<49> WL_O<48> WL_O<47> WL_O<46> WL_O<45> ++ WL_O<44> WL_O<43> WL_O<42> WL_O<41> WL_O<40> WL_O<39> WL_O<38> WL_O<37> ++ WL_O<36> WL_O<35> WL_O<34> WL_O<33> WL_O<32> WL_O<31> WL_O<30> WL_O<29> ++ WL_O<28> WL_O<27> WL_O<26> WL_O<25> WL_O<24> WL_O<23> WL_O<22> WL_O<21> ++ WL_O<20> WL_O<19> WL_O<18> WL_O<17> WL_O<16> WL_O<15> WL_O<14> WL_O<13> ++ WL_O<12> WL_O<11> WL_O<10> WL_O<9> WL_O<8> WL_O<7> WL_O<6> WL_O<5> WL_O<4> ++ WL_O<3> WL_O<2> WL_O<1> WL_O<0> VDD VSS +XDEC11<4> ADDR_N_I<7> ADDR_N_I<6> CS_I CS04<3> VDD VSS / ++ RM_IHPSG13_512x8_c2_1P_DEC03 +XDEC11<3> ADDR_N_I<5> ADDR_N_I<4> CS04<3> CS00<15> VDD VSS / ++ RM_IHPSG13_512x8_c2_1P_DEC03 +XDEC11<2> ADDR_N_I<5> ADDR_N_I<4> CS04<2> CS00<11> VDD VSS / ++ RM_IHPSG13_512x8_c2_1P_DEC03 +XDEC11<1> ADDR_N_I<5> ADDR_N_I<4> CS04<1> CS00<7> VDD VSS / ++ RM_IHPSG13_512x8_c2_1P_DEC03 +XDEC11<0> ADDR_N_I<5> ADDR_N_I<4> CS04<0> CS00<3> VDD VSS / ++ RM_IHPSG13_512x8_c2_1P_DEC03 +XL2<88> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<87> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<86> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<85> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<84> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<83> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<82> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<81> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<80> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<79> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<78> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<77> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<76> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<75> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<74> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<73> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<72> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<71> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<70> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<69> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<68> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<67> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<66> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<65> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<64> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<63> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<62> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<61> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<60> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<59> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<58> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<57> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<56> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<55> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<54> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<53> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<52> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<51> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<50> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<49> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<48> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<47> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<46> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<45> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<44> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<43> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<42> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<41> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<40> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<39> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<38> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<37> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<36> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<35> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<34> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<33> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<32> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<31> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<30> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<29> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<28> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<27> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<26> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<25> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<24> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<23> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<22> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<21> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<20> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<19> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<18> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<17> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<16> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<15> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<14> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<13> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<12> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<11> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<10> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<9> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<8> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<7> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<6> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<5> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<4> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<3> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<2> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<1> VDD VSS / RSC_IHPSG13_FILLCAP8 +XDEC10<4> ADDR_N_I<7> ADDR_N_I<6> CS_I CS04<2> VDD VSS / ++ RM_IHPSG13_512x8_c2_1P_DEC02 +XDEC10<3> ADDR_N_I<5> ADDR_N_I<4> CS04<3> CS00<14> VDD VSS / ++ RM_IHPSG13_512x8_c2_1P_DEC02 +XDEC10<2> ADDR_N_I<5> ADDR_N_I<4> CS04<2> CS00<10> VDD VSS / ++ RM_IHPSG13_512x8_c2_1P_DEC02 +XDEC10<1> ADDR_N_I<5> ADDR_N_I<4> CS04<1> CS00<6> VDD VSS / ++ RM_IHPSG13_512x8_c2_1P_DEC02 +XDEC10<0> ADDR_N_I<5> ADDR_N_I<4> CS04<0> CS00<2> VDD VSS / ++ RM_IHPSG13_512x8_c2_1P_DEC02 +XDEC00<4> ADDR_N_I<7> ADDR_N_I<6> CS_I CS04<0> VDD VSS / ++ RM_IHPSG13_512x8_c2_1P_DEC00 +XDEC00<3> ADDR_N_I<5> ADDR_N_I<4> CS04<3> CS00<12> VDD VSS / ++ RM_IHPSG13_512x8_c2_1P_DEC00 +XDEC00<2> ADDR_N_I<5> ADDR_N_I<4> CS04<2> CS00<8> VDD VSS / ++ RM_IHPSG13_512x8_c2_1P_DEC00 +XDEC00<1> ADDR_N_I<5> ADDR_N_I<4> CS04<1> CS00<4> VDD VSS / ++ RM_IHPSG13_512x8_c2_1P_DEC00 +XDEC00<0> ADDR_N_I<5> ADDR_N_I<4> CS04<0> CS00<0> VDD VSS / ++ RM_IHPSG13_512x8_c2_1P_DEC00 +XSEL<15> ADDR_N_I<3> ADDR_N_I<2> ADDR_N_I<1> ADDR_N_I<0> CS00<15> ECLK_H<15> ++ ECLK_H<16> ECLK_B<15> ECLK_B<16> WL_O<255> WL_O<254> WL_O<253> WL_O<252> ++ WL_O<251> WL_O<250> WL_O<249> WL_O<248> WL_O<247> WL_O<246> WL_O<245> ++ WL_O<244> WL_O<243> WL_O<242> WL_O<241> WL_O<240> VDD VSS / ++ RM_IHPSG13_512x8_c2_1P_DEC04 +XSEL<14> ADDR_N_I<3> ADDR_N_I<2> ADDR_N_I<1> ADDR_N_I<0> CS00<14> ECLK_H<14> ++ ECLK_H<15> ECLK_B<14> ECLK_B<15> WL_O<239> WL_O<238> WL_O<237> WL_O<236> ++ WL_O<235> WL_O<234> WL_O<233> WL_O<232> WL_O<231> WL_O<230> WL_O<229> ++ WL_O<228> WL_O<227> WL_O<226> WL_O<225> WL_O<224> VDD VSS / ++ RM_IHPSG13_512x8_c2_1P_DEC04 +XSEL<13> ADDR_N_I<3> ADDR_N_I<2> ADDR_N_I<1> ADDR_N_I<0> CS00<13> ECLK_H<13> ++ ECLK_H<14> ECLK_B<13> ECLK_B<14> WL_O<223> WL_O<222> WL_O<221> WL_O<220> ++ WL_O<219> WL_O<218> WL_O<217> WL_O<216> WL_O<215> WL_O<214> WL_O<213> ++ WL_O<212> WL_O<211> WL_O<210> WL_O<209> WL_O<208> VDD VSS / ++ RM_IHPSG13_512x8_c2_1P_DEC04 +XSEL<12> ADDR_N_I<3> ADDR_N_I<2> ADDR_N_I<1> ADDR_N_I<0> CS00<12> ECLK_H<12> ++ ECLK_H<13> ECLK_B<12> ECLK_B<13> WL_O<207> WL_O<206> WL_O<205> WL_O<204> ++ WL_O<203> WL_O<202> WL_O<201> WL_O<200> WL_O<199> WL_O<198> WL_O<197> ++ WL_O<196> WL_O<195> WL_O<194> WL_O<193> WL_O<192> VDD VSS / ++ RM_IHPSG13_512x8_c2_1P_DEC04 +XSEL<11> ADDR_N_I<3> ADDR_N_I<2> ADDR_N_I<1> ADDR_N_I<0> CS00<11> ECLK_H<11> ++ ECLK_H<12> ECLK_B<11> ECLK_B<12> WL_O<191> WL_O<190> WL_O<189> WL_O<188> ++ WL_O<187> WL_O<186> WL_O<185> WL_O<184> WL_O<183> WL_O<182> WL_O<181> ++ WL_O<180> WL_O<179> WL_O<178> WL_O<177> WL_O<176> VDD VSS / ++ RM_IHPSG13_512x8_c2_1P_DEC04 +XSEL<10> ADDR_N_I<3> ADDR_N_I<2> ADDR_N_I<1> ADDR_N_I<0> CS00<10> ECLK_H<10> ++ ECLK_H<11> ECLK_B<10> ECLK_B<11> WL_O<175> WL_O<174> WL_O<173> WL_O<172> ++ WL_O<171> WL_O<170> WL_O<169> WL_O<168> WL_O<167> WL_O<166> WL_O<165> ++ WL_O<164> WL_O<163> WL_O<162> WL_O<161> WL_O<160> VDD VSS / ++ RM_IHPSG13_512x8_c2_1P_DEC04 +XSEL<9> ADDR_N_I<3> ADDR_N_I<2> ADDR_N_I<1> ADDR_N_I<0> CS00<9> ECLK_H<9> ++ ECLK_H<10> ECLK_B<9> ECLK_B<10> WL_O<159> WL_O<158> WL_O<157> WL_O<156> ++ WL_O<155> WL_O<154> WL_O<153> WL_O<152> WL_O<151> WL_O<150> WL_O<149> ++ WL_O<148> WL_O<147> WL_O<146> WL_O<145> WL_O<144> VDD VSS / ++ RM_IHPSG13_512x8_c2_1P_DEC04 +XSEL<8> ADDR_N_I<3> ADDR_N_I<2> ADDR_N_I<1> ADDR_N_I<0> CS00<8> ECLK_H<8> ++ ECLK_H<9> ECLK_B<8> ECLK_B<9> WL_O<143> WL_O<142> WL_O<141> WL_O<140> ++ WL_O<139> WL_O<138> WL_O<137> WL_O<136> WL_O<135> WL_O<134> WL_O<133> ++ WL_O<132> WL_O<131> WL_O<130> WL_O<129> WL_O<128> VDD VSS / ++ RM_IHPSG13_512x8_c2_1P_DEC04 +XSEL<7> ADDR_N_I<3> ADDR_N_I<2> ADDR_N_I<1> ADDR_N_I<0> CS00<7> ECLK_H<7> ++ ECLK_H<8> ECLK_B<7> ECLK_B<8> WL_O<127> WL_O<126> WL_O<125> WL_O<124> ++ WL_O<123> WL_O<122> WL_O<121> WL_O<120> WL_O<119> WL_O<118> WL_O<117> ++ WL_O<116> WL_O<115> WL_O<114> WL_O<113> WL_O<112> VDD VSS / ++ RM_IHPSG13_512x8_c2_1P_DEC04 +XSEL<6> ADDR_N_I<3> ADDR_N_I<2> ADDR_N_I<1> ADDR_N_I<0> CS00<6> ECLK_H<6> ++ ECLK_H<7> ECLK_B<6> ECLK_B<7> WL_O<111> WL_O<110> WL_O<109> WL_O<108> ++ WL_O<107> WL_O<106> WL_O<105> WL_O<104> WL_O<103> WL_O<102> WL_O<101> ++ WL_O<100> WL_O<99> WL_O<98> WL_O<97> WL_O<96> VDD VSS / ++ RM_IHPSG13_512x8_c2_1P_DEC04 +XSEL<5> ADDR_N_I<3> ADDR_N_I<2> ADDR_N_I<1> ADDR_N_I<0> CS00<5> ECLK_H<5> ++ ECLK_H<6> ECLK_B<5> ECLK_B<6> WL_O<95> WL_O<94> WL_O<93> WL_O<92> WL_O<91> ++ WL_O<90> WL_O<89> WL_O<88> WL_O<87> WL_O<86> WL_O<85> WL_O<84> WL_O<83> ++ WL_O<82> WL_O<81> WL_O<80> VDD VSS / RM_IHPSG13_512x8_c2_1P_DEC04 +XSEL<4> ADDR_N_I<3> ADDR_N_I<2> ADDR_N_I<1> ADDR_N_I<0> CS00<4> ECLK_H<4> ++ ECLK_H<5> ECLK_B<4> ECLK_B<5> WL_O<79> WL_O<78> WL_O<77> WL_O<76> WL_O<75> ++ WL_O<74> WL_O<73> WL_O<72> WL_O<71> WL_O<70> WL_O<69> WL_O<68> WL_O<67> ++ WL_O<66> WL_O<65> WL_O<64> VDD VSS / RM_IHPSG13_512x8_c2_1P_DEC04 +XSEL<3> ADDR_N_I<3> ADDR_N_I<2> ADDR_N_I<1> ADDR_N_I<0> CS00<3> ECLK_H<3> ++ ECLK_H<4> ECLK_B<3> ECLK_B<4> WL_O<63> WL_O<62> WL_O<61> WL_O<60> WL_O<59> ++ WL_O<58> WL_O<57> WL_O<56> WL_O<55> WL_O<54> WL_O<53> WL_O<52> WL_O<51> ++ WL_O<50> WL_O<49> WL_O<48> VDD VSS / RM_IHPSG13_512x8_c2_1P_DEC04 +XSEL<2> ADDR_N_I<3> ADDR_N_I<2> ADDR_N_I<1> ADDR_N_I<0> CS00<2> ECLK_H<2> ++ ECLK_H<3> ECLK_B<2> ECLK_B<3> WL_O<47> WL_O<46> WL_O<45> WL_O<44> WL_O<43> ++ WL_O<42> WL_O<41> WL_O<40> WL_O<39> WL_O<38> WL_O<37> WL_O<36> WL_O<35> ++ WL_O<34> WL_O<33> WL_O<32> VDD VSS / RM_IHPSG13_512x8_c2_1P_DEC04 +XSEL<1> ADDR_N_I<3> ADDR_N_I<2> ADDR_N_I<1> ADDR_N_I<0> CS00<1> ECLK_H<1> ++ ECLK_H<2> ECLK_B<1> ECLK_B<2> WL_O<31> WL_O<30> WL_O<29> WL_O<28> WL_O<27> ++ WL_O<26> WL_O<25> WL_O<24> WL_O<23> WL_O<22> WL_O<21> WL_O<20> WL_O<19> ++ WL_O<18> WL_O<17> WL_O<16> VDD VSS / RM_IHPSG13_512x8_c2_1P_DEC04 +XSEL<0> ADDR_N_I<3> ADDR_N_I<2> ADDR_N_I<1> ADDR_N_I<0> CS00<0> ECLK_I ++ ECLK_H<1> ECLK_B<0> ECLK_B<1> WL_O<15> WL_O<14> WL_O<13> WL_O<12> WL_O<11> ++ WL_O<10> WL_O<9> WL_O<8> WL_O<7> WL_O<6> WL_O<5> WL_O<4> WL_O<3> WL_O<2> ++ WL_O<1> WL_O<0> VDD VSS / RM_IHPSG13_512x8_c2_1P_DEC04 +XDEC01<4> ADDR_N_I<7> ADDR_N_I<6> CS_I CS04<1> VDD VSS / ++ RM_IHPSG13_512x8_c2_1P_DEC01 +XDEC01<3> ADDR_N_I<5> ADDR_N_I<4> CS04<3> CS00<13> VDD VSS / ++ RM_IHPSG13_512x8_c2_1P_DEC01 +XDEC01<2> ADDR_N_I<5> ADDR_N_I<4> CS04<2> CS00<9> VDD VSS / ++ RM_IHPSG13_512x8_c2_1P_DEC01 +XDEC01<1> ADDR_N_I<5> ADDR_N_I<4> CS04<1> CS00<5> VDD VSS / ++ RM_IHPSG13_512x8_c2_1P_DEC01 +XDEC01<0> ADDR_N_I<5> ADDR_N_I<4> CS04<0> CS00<1> VDD VSS / ++ RM_IHPSG13_512x8_c2_1P_DEC01 +.ENDS +.SUBCKT RM_IHPSG13_512x8_c2_1P_ROWREG8 ACLK_N_I ADDR_I<7> ADDR_I<6> ADDR_I<5> ADDR_I<4> ++ ADDR_I<3> ADDR_I<2> ADDR_I<1> ADDR_I<0> ADDR_N_O<7> ADDR_N_O<6> ADDR_N_O<5> ++ ADDR_N_O<4> ADDR_N_O<3> ADDR_N_O<2> ADDR_N_O<1> ADDR_N_O<0> BIST_ADDR_I<7> ++ BIST_ADDR_I<6> BIST_ADDR_I<5> BIST_ADDR_I<4> BIST_ADDR_I<3> BIST_ADDR_I<2> ++ BIST_ADDR_I<1> BIST_ADDR_I<0> BIST_EN_I VDD VSS +XINV<7> q_int<7> qn_int<7> VDD VSS / RSC_IHPSG13_CINVX2 +XINV<6> q_int<6> qn_int<6> VDD VSS / RSC_IHPSG13_CINVX2 +XINV<5> q_int<5> qn_int<5> VDD VSS / RSC_IHPSG13_CINVX2 +XINV<4> q_int<4> qn_int<4> VDD VSS / RSC_IHPSG13_CINVX2 +XINV<3> q_int<3> qn_int<3> VDD VSS / RSC_IHPSG13_CINVX2 +XINV<2> q_int<2> qn_int<2> VDD VSS / RSC_IHPSG13_CINVX2 +XINV<1> q_int<1> qn_int<1> VDD VSS / RSC_IHPSG13_CINVX2 +XINV<0> q_int<0> qn_int<0> VDD VSS / RSC_IHPSG13_CINVX2 +XDRV<7> qn_int<7> ADDR_N_O<7> VDD VSS / RSC_IHPSG13_CINVX8 +XDRV<6> qn_int<6> ADDR_N_O<6> VDD VSS / RSC_IHPSG13_CINVX8 +XDRV<5> qn_int<5> ADDR_N_O<5> VDD VSS / RSC_IHPSG13_CINVX8 +XDRV<4> qn_int<4> ADDR_N_O<4> VDD VSS / RSC_IHPSG13_CINVX8 +XDRV<3> qn_int<3> ADDR_N_O<3> VDD VSS / RSC_IHPSG13_CINVX8 +XDRV<2> qn_int<2> ADDR_N_O<2> VDD VSS / RSC_IHPSG13_CINVX8 +XDRV<1> qn_int<1> ADDR_N_O<1> VDD VSS / RSC_IHPSG13_CINVX8 +XDRV<0> qn_int<0> ADDR_N_O<0> VDD VSS / RSC_IHPSG13_CINVX8 +XDFF<7> BIST_EN_I BIST_ADDR_I<7> ACLK_N_I ADDR_I<7> q_int<7> net2<0> VDD ++ VSS / RSC_IHPSG13_DFNQMX2IX1 +XDFF<6> BIST_EN_I BIST_ADDR_I<6> ACLK_N_I ADDR_I<6> q_int<6> net2<1> VDD ++ VSS / RSC_IHPSG13_DFNQMX2IX1 +XDFF<5> BIST_EN_I BIST_ADDR_I<5> ACLK_N_I ADDR_I<5> q_int<5> net2<2> VDD ++ VSS / RSC_IHPSG13_DFNQMX2IX1 +XDFF<4> BIST_EN_I BIST_ADDR_I<4> ACLK_N_I ADDR_I<4> q_int<4> net2<3> VDD ++ VSS / RSC_IHPSG13_DFNQMX2IX1 +XDFF<3> BIST_EN_I BIST_ADDR_I<3> ACLK_N_I ADDR_I<3> q_int<3> net2<4> VDD ++ VSS / RSC_IHPSG13_DFNQMX2IX1 +XDFF<2> BIST_EN_I BIST_ADDR_I<2> ACLK_N_I ADDR_I<2> q_int<2> net2<5> VDD ++ VSS / RSC_IHPSG13_DFNQMX2IX1 +XDFF<1> BIST_EN_I BIST_ADDR_I<1> ACLK_N_I ADDR_I<1> q_int<1> net2<6> VDD ++ VSS / RSC_IHPSG13_DFNQMX2IX1 +XDFF<0> BIST_EN_I BIST_ADDR_I<0> ACLK_N_I ADDR_I<0> q_int<0> net2<7> VDD ++ VSS / RSC_IHPSG13_DFNQMX2IX1 +XI11<4> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI11<3> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI11<2> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI11<1> VDD VSS / RSC_IHPSG13_FILLCAP8 +.ENDS + +.SUBCKT RM_IHPSG13_512x8_c2_1P_ROWDEC9 ADDR_N_I<8> ADDR_N_I<7> ADDR_N_I<6> ADDR_N_I<5> ++ ADDR_N_I<4> ADDR_N_I<3> ADDR_N_I<2> ADDR_N_I<1> ADDR_N_I<0> CS_I ECLK_I ++ WL_O<511> WL_O<510> WL_O<509> WL_O<508> WL_O<507> WL_O<506> WL_O<505> ++ WL_O<504> WL_O<503> WL_O<502> WL_O<501> WL_O<500> WL_O<499> WL_O<498> ++ WL_O<497> WL_O<496> WL_O<495> WL_O<494> WL_O<493> WL_O<492> WL_O<491> ++ WL_O<490> WL_O<489> WL_O<488> WL_O<487> WL_O<486> WL_O<485> WL_O<484> ++ WL_O<483> WL_O<482> WL_O<481> WL_O<480> WL_O<479> WL_O<478> WL_O<477> ++ WL_O<476> WL_O<475> WL_O<474> WL_O<473> WL_O<472> WL_O<471> WL_O<470> ++ WL_O<469> WL_O<468> WL_O<467> WL_O<466> WL_O<465> WL_O<464> WL_O<463> ++ WL_O<462> WL_O<461> WL_O<460> WL_O<459> WL_O<458> WL_O<457> WL_O<456> ++ WL_O<455> WL_O<454> WL_O<453> WL_O<452> WL_O<451> WL_O<450> WL_O<449> ++ WL_O<448> WL_O<447> WL_O<446> WL_O<445> WL_O<444> WL_O<443> WL_O<442> ++ WL_O<441> WL_O<440> WL_O<439> WL_O<438> WL_O<437> WL_O<436> WL_O<435> ++ WL_O<434> WL_O<433> WL_O<432> WL_O<431> WL_O<430> WL_O<429> WL_O<428> ++ WL_O<427> WL_O<426> WL_O<425> WL_O<424> WL_O<423> WL_O<422> WL_O<421> ++ WL_O<420> WL_O<419> WL_O<418> WL_O<417> WL_O<416> WL_O<415> WL_O<414> ++ WL_O<413> WL_O<412> WL_O<411> WL_O<410> WL_O<409> WL_O<408> WL_O<407> ++ WL_O<406> WL_O<405> WL_O<404> WL_O<403> WL_O<402> WL_O<401> WL_O<400> ++ WL_O<399> WL_O<398> WL_O<397> WL_O<396> WL_O<395> WL_O<394> WL_O<393> ++ WL_O<392> WL_O<391> WL_O<390> WL_O<389> WL_O<388> WL_O<387> WL_O<386> ++ WL_O<385> WL_O<384> WL_O<383> WL_O<382> WL_O<381> WL_O<380> WL_O<379> ++ WL_O<378> WL_O<377> WL_O<376> WL_O<375> WL_O<374> WL_O<373> WL_O<372> ++ WL_O<371> WL_O<370> WL_O<369> WL_O<368> WL_O<367> WL_O<366> WL_O<365> ++ WL_O<364> WL_O<363> WL_O<362> WL_O<361> WL_O<360> WL_O<359> WL_O<358> ++ WL_O<357> WL_O<356> WL_O<355> WL_O<354> WL_O<353> WL_O<352> WL_O<351> ++ WL_O<350> WL_O<349> WL_O<348> WL_O<347> WL_O<346> WL_O<345> WL_O<344> ++ WL_O<343> WL_O<342> WL_O<341> WL_O<340> WL_O<339> WL_O<338> WL_O<337> ++ WL_O<336> WL_O<335> WL_O<334> WL_O<333> WL_O<332> WL_O<331> WL_O<330> ++ WL_O<329> WL_O<328> WL_O<327> WL_O<326> WL_O<325> WL_O<324> WL_O<323> ++ WL_O<322> WL_O<321> WL_O<320> WL_O<319> WL_O<318> WL_O<317> WL_O<316> ++ WL_O<315> WL_O<314> WL_O<313> WL_O<312> WL_O<311> WL_O<310> WL_O<309> ++ WL_O<308> WL_O<307> WL_O<306> WL_O<305> WL_O<304> WL_O<303> WL_O<302> ++ WL_O<301> WL_O<300> WL_O<299> WL_O<298> WL_O<297> WL_O<296> WL_O<295> ++ WL_O<294> WL_O<293> WL_O<292> WL_O<291> WL_O<290> WL_O<289> WL_O<288> ++ WL_O<287> WL_O<286> WL_O<285> WL_O<284> WL_O<283> WL_O<282> WL_O<281> ++ WL_O<280> WL_O<279> WL_O<278> WL_O<277> WL_O<276> WL_O<275> WL_O<274> ++ WL_O<273> WL_O<272> WL_O<271> WL_O<270> WL_O<269> WL_O<268> WL_O<267> ++ WL_O<266> WL_O<265> WL_O<264> WL_O<263> WL_O<262> WL_O<261> WL_O<260> ++ WL_O<259> WL_O<258> WL_O<257> WL_O<256> WL_O<255> WL_O<254> WL_O<253> ++ WL_O<252> WL_O<251> WL_O<250> WL_O<249> WL_O<248> WL_O<247> WL_O<246> ++ WL_O<245> WL_O<244> WL_O<243> WL_O<242> WL_O<241> WL_O<240> WL_O<239> ++ WL_O<238> WL_O<237> WL_O<236> WL_O<235> WL_O<234> WL_O<233> WL_O<232> ++ WL_O<231> WL_O<230> WL_O<229> WL_O<228> WL_O<227> WL_O<226> WL_O<225> ++ WL_O<224> WL_O<223> WL_O<222> WL_O<221> WL_O<220> WL_O<219> WL_O<218> ++ WL_O<217> WL_O<216> WL_O<215> WL_O<214> WL_O<213> WL_O<212> WL_O<211> ++ WL_O<210> WL_O<209> WL_O<208> WL_O<207> WL_O<206> WL_O<205> WL_O<204> ++ WL_O<203> WL_O<202> WL_O<201> WL_O<200> WL_O<199> WL_O<198> WL_O<197> ++ WL_O<196> WL_O<195> WL_O<194> WL_O<193> WL_O<192> WL_O<191> WL_O<190> ++ WL_O<189> WL_O<188> WL_O<187> WL_O<186> WL_O<185> WL_O<184> WL_O<183> ++ WL_O<182> WL_O<181> WL_O<180> WL_O<179> WL_O<178> WL_O<177> WL_O<176> ++ WL_O<175> WL_O<174> WL_O<173> WL_O<172> WL_O<171> WL_O<170> WL_O<169> ++ WL_O<168> WL_O<167> WL_O<166> WL_O<165> WL_O<164> WL_O<163> WL_O<162> ++ WL_O<161> WL_O<160> WL_O<159> WL_O<158> WL_O<157> WL_O<156> WL_O<155> ++ WL_O<154> WL_O<153> WL_O<152> WL_O<151> WL_O<150> WL_O<149> WL_O<148> ++ WL_O<147> WL_O<146> WL_O<145> WL_O<144> WL_O<143> WL_O<142> WL_O<141> ++ WL_O<140> WL_O<139> WL_O<138> WL_O<137> WL_O<136> WL_O<135> WL_O<134> ++ WL_O<133> WL_O<132> WL_O<131> WL_O<130> WL_O<129> WL_O<128> WL_O<127> ++ WL_O<126> WL_O<125> WL_O<124> WL_O<123> WL_O<122> WL_O<121> WL_O<120> ++ WL_O<119> WL_O<118> WL_O<117> WL_O<116> WL_O<115> WL_O<114> WL_O<113> ++ WL_O<112> WL_O<111> WL_O<110> WL_O<109> WL_O<108> WL_O<107> WL_O<106> ++ WL_O<105> WL_O<104> WL_O<103> WL_O<102> WL_O<101> WL_O<100> WL_O<99> ++ WL_O<98> WL_O<97> WL_O<96> WL_O<95> WL_O<94> WL_O<93> WL_O<92> WL_O<91> ++ WL_O<90> WL_O<89> WL_O<88> WL_O<87> WL_O<86> WL_O<85> WL_O<84> WL_O<83> ++ WL_O<82> WL_O<81> WL_O<80> WL_O<79> WL_O<78> WL_O<77> WL_O<76> WL_O<75> ++ WL_O<74> WL_O<73> WL_O<72> WL_O<71> WL_O<70> WL_O<69> WL_O<68> WL_O<67> ++ WL_O<66> WL_O<65> WL_O<64> WL_O<63> WL_O<62> WL_O<61> WL_O<60> WL_O<59> ++ WL_O<58> WL_O<57> WL_O<56> WL_O<55> WL_O<54> WL_O<53> WL_O<52> WL_O<51> ++ WL_O<50> WL_O<49> WL_O<48> WL_O<47> WL_O<46> WL_O<45> WL_O<44> WL_O<43> ++ WL_O<42> WL_O<41> WL_O<40> WL_O<39> WL_O<38> WL_O<37> WL_O<36> WL_O<35> ++ WL_O<34> WL_O<33> WL_O<32> WL_O<31> WL_O<30> WL_O<29> WL_O<28> WL_O<27> ++ WL_O<26> WL_O<25> WL_O<24> WL_O<23> WL_O<22> WL_O<21> WL_O<20> WL_O<19> ++ WL_O<18> WL_O<17> WL_O<16> WL_O<15> WL_O<14> WL_O<13> WL_O<12> WL_O<11> ++ WL_O<10> WL_O<9> WL_O<8> WL_O<7> WL_O<6> WL_O<5> WL_O<4> WL_O<3> WL_O<2> ++ WL_O<1> WL_O<0> VDD VSS +XL2<172> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<171> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<170> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<169> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<168> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<167> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<166> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<165> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<164> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<163> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<162> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<161> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<160> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<159> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<158> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<157> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<156> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<155> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<154> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<153> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<152> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<151> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<150> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<149> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<148> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<147> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<146> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<145> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<144> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<143> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<142> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<141> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<140> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<139> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<138> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<137> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<136> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<135> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<134> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<133> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<132> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<131> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<130> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<129> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<128> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<127> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<126> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<125> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<124> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<123> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<122> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<121> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<120> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<119> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<118> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<117> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<116> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<115> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<114> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<113> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<112> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<111> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<110> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<109> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<108> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<107> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<106> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<105> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<104> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<103> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<102> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<101> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<100> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<99> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<98> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<97> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<96> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<95> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<94> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<93> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<92> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<91> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<90> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<89> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<88> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<87> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<86> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<85> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<84> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<83> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<82> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<81> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<80> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<79> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<78> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<77> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<76> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<75> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<74> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<73> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<72> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<71> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<70> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<69> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<68> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<67> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<66> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<65> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<64> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<63> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<62> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<61> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<60> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<59> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<58> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<57> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<56> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<55> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<54> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<53> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<52> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<51> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<50> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<49> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<48> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<47> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<46> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<45> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<44> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<43> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<42> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<41> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<40> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<39> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<38> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<37> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<36> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<35> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<34> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<33> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<32> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<31> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<30> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<29> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<28> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<27> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<26> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<25> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<24> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<23> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<22> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<21> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<20> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<19> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<18> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<17> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<16> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<15> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<14> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<13> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<12> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<11> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<10> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<9> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<8> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<7> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<6> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<5> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<4> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<3> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<2> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<1> VDD VSS / RSC_IHPSG13_FILLCAP8 +XDEC11<9> ADDR_N_I<7> ADDR_N_I<6> CS04<1> CS02<7> VDD VSS / ++ RM_IHPSG13_512x8_c2_1P_DEC03 +XDEC11<8> ADDR_N_I<7> ADDR_N_I<6> CS04<0> CS02<3> VDD VSS / ++ RM_IHPSG13_512x8_c2_1P_DEC03 +XDEC11<7> ADDR_N_I<5> ADDR_N_I<4> CS02<7> CS00<31> VDD VSS / ++ RM_IHPSG13_512x8_c2_1P_DEC03 +XDEC11<6> ADDR_N_I<5> ADDR_N_I<4> CS02<6> CS00<27> VDD VSS / ++ RM_IHPSG13_512x8_c2_1P_DEC03 +XDEC11<5> ADDR_N_I<5> ADDR_N_I<4> CS02<5> CS00<23> VDD VSS / ++ RM_IHPSG13_512x8_c2_1P_DEC03 +XDEC11<4> ADDR_N_I<5> ADDR_N_I<4> CS02<4> CS00<19> VDD VSS / ++ RM_IHPSG13_512x8_c2_1P_DEC03 +XDEC11<3> ADDR_N_I<5> ADDR_N_I<4> CS02<3> CS00<15> VDD VSS / ++ RM_IHPSG13_512x8_c2_1P_DEC03 +XDEC11<2> ADDR_N_I<5> ADDR_N_I<4> CS02<2> CS00<11> VDD VSS / ++ RM_IHPSG13_512x8_c2_1P_DEC03 +XDEC11<1> ADDR_N_I<5> ADDR_N_I<4> CS02<1> CS00<7> VDD VSS / ++ RM_IHPSG13_512x8_c2_1P_DEC03 +XDEC11<0> ADDR_N_I<5> ADDR_N_I<4> CS02<0> CS00<3> VDD VSS / ++ RM_IHPSG13_512x8_c2_1P_DEC03 +XDEC00<10> ADDR_N_I<9> ADDR_N_I<8> CS_I CS04<0> VDD VSS / ++ RM_IHPSG13_512x8_c2_1P_DEC00 +XDEC00<9> ADDR_N_I<7> ADDR_N_I<6> CS04<1> CS02<4> VDD VSS / ++ RM_IHPSG13_512x8_c2_1P_DEC00 +XDEC00<8> ADDR_N_I<7> ADDR_N_I<6> CS04<0> CS02<0> VDD VSS / ++ RM_IHPSG13_512x8_c2_1P_DEC00 +XDEC00<7> ADDR_N_I<5> ADDR_N_I<4> CS02<7> CS00<28> VDD VSS / ++ RM_IHPSG13_512x8_c2_1P_DEC00 +XDEC00<6> ADDR_N_I<5> ADDR_N_I<4> CS02<6> CS00<24> VDD VSS / ++ RM_IHPSG13_512x8_c2_1P_DEC00 +XDEC00<5> ADDR_N_I<5> ADDR_N_I<4> CS02<5> CS00<20> VDD VSS / ++ RM_IHPSG13_512x8_c2_1P_DEC00 +XDEC00<4> ADDR_N_I<5> ADDR_N_I<4> CS02<4> CS00<16> VDD VSS / ++ RM_IHPSG13_512x8_c2_1P_DEC00 +XDEC00<3> ADDR_N_I<5> ADDR_N_I<4> CS02<3> CS00<12> VDD VSS / ++ RM_IHPSG13_512x8_c2_1P_DEC00 +XDEC00<2> ADDR_N_I<5> ADDR_N_I<4> CS02<2> CS00<8> VDD VSS / ++ RM_IHPSG13_512x8_c2_1P_DEC00 +XDEC00<1> ADDR_N_I<5> ADDR_N_I<4> CS02<1> CS00<4> VDD VSS / ++ RM_IHPSG13_512x8_c2_1P_DEC00 +XDEC00<0> ADDR_N_I<5> ADDR_N_I<4> CS02<0> CS00<0> VDD VSS / ++ RM_IHPSG13_512x8_c2_1P_DEC00 +XSEL<31> ADDR_N_I<3> ADDR_N_I<2> ADDR_N_I<1> ADDR_N_I<0> CS00<31> ECLK_H<31> ++ ECLK_H<32> ECLK_B<31> ECLK_B<32> WL_O<511> WL_O<510> WL_O<509> WL_O<508> ++ WL_O<507> WL_O<506> WL_O<505> WL_O<504> WL_O<503> WL_O<502> WL_O<501> ++ WL_O<500> WL_O<499> WL_O<498> WL_O<497> WL_O<496> VDD VSS / ++ RM_IHPSG13_512x8_c2_1P_DEC04 +XSEL<30> ADDR_N_I<3> ADDR_N_I<2> ADDR_N_I<1> ADDR_N_I<0> CS00<30> ECLK_H<30> ++ ECLK_H<31> ECLK_B<30> ECLK_B<31> WL_O<495> WL_O<494> WL_O<493> WL_O<492> ++ WL_O<491> WL_O<490> WL_O<489> WL_O<488> WL_O<487> WL_O<486> WL_O<485> ++ WL_O<484> WL_O<483> WL_O<482> WL_O<481> WL_O<480> VDD VSS / ++ RM_IHPSG13_512x8_c2_1P_DEC04 +XSEL<29> ADDR_N_I<3> ADDR_N_I<2> ADDR_N_I<1> ADDR_N_I<0> CS00<29> ECLK_H<29> ++ ECLK_H<30> ECLK_B<29> ECLK_B<30> WL_O<479> WL_O<478> WL_O<477> WL_O<476> ++ WL_O<475> WL_O<474> WL_O<473> WL_O<472> WL_O<471> WL_O<470> WL_O<469> ++ WL_O<468> WL_O<467> WL_O<466> WL_O<465> WL_O<464> VDD VSS / ++ RM_IHPSG13_512x8_c2_1P_DEC04 +XSEL<28> ADDR_N_I<3> ADDR_N_I<2> ADDR_N_I<1> ADDR_N_I<0> CS00<28> ECLK_H<28> ++ ECLK_H<29> ECLK_B<28> ECLK_B<29> WL_O<463> WL_O<462> WL_O<461> WL_O<460> ++ WL_O<459> WL_O<458> WL_O<457> WL_O<456> WL_O<455> WL_O<454> WL_O<453> ++ WL_O<452> WL_O<451> WL_O<450> WL_O<449> WL_O<448> VDD VSS / ++ RM_IHPSG13_512x8_c2_1P_DEC04 +XSEL<27> ADDR_N_I<3> ADDR_N_I<2> ADDR_N_I<1> ADDR_N_I<0> CS00<27> ECLK_H<27> ++ ECLK_H<28> ECLK_B<27> ECLK_B<28> WL_O<447> WL_O<446> WL_O<445> WL_O<444> ++ WL_O<443> WL_O<442> WL_O<441> WL_O<440> WL_O<439> WL_O<438> WL_O<437> ++ WL_O<436> WL_O<435> WL_O<434> WL_O<433> WL_O<432> VDD VSS / ++ RM_IHPSG13_512x8_c2_1P_DEC04 +XSEL<26> ADDR_N_I<3> ADDR_N_I<2> ADDR_N_I<1> ADDR_N_I<0> CS00<26> ECLK_H<26> ++ ECLK_H<27> ECLK_B<26> ECLK_B<27> WL_O<431> WL_O<430> WL_O<429> WL_O<428> ++ WL_O<427> WL_O<426> WL_O<425> WL_O<424> WL_O<423> WL_O<422> WL_O<421> ++ WL_O<420> WL_O<419> WL_O<418> WL_O<417> WL_O<416> VDD VSS / ++ RM_IHPSG13_512x8_c2_1P_DEC04 +XSEL<25> ADDR_N_I<3> ADDR_N_I<2> ADDR_N_I<1> ADDR_N_I<0> CS00<25> ECLK_H<25> ++ ECLK_H<26> ECLK_B<25> ECLK_B<26> WL_O<415> WL_O<414> WL_O<413> WL_O<412> ++ WL_O<411> WL_O<410> WL_O<409> WL_O<408> WL_O<407> WL_O<406> WL_O<405> ++ WL_O<404> WL_O<403> WL_O<402> WL_O<401> WL_O<400> VDD VSS / ++ RM_IHPSG13_512x8_c2_1P_DEC04 +XSEL<24> ADDR_N_I<3> ADDR_N_I<2> ADDR_N_I<1> ADDR_N_I<0> CS00<24> ECLK_H<24> ++ ECLK_H<25> ECLK_B<24> ECLK_B<25> WL_O<399> WL_O<398> WL_O<397> WL_O<396> ++ WL_O<395> WL_O<394> WL_O<393> WL_O<392> WL_O<391> WL_O<390> WL_O<389> ++ WL_O<388> WL_O<387> WL_O<386> WL_O<385> WL_O<384> VDD VSS / ++ RM_IHPSG13_512x8_c2_1P_DEC04 +XSEL<23> ADDR_N_I<3> ADDR_N_I<2> ADDR_N_I<1> ADDR_N_I<0> CS00<23> ECLK_H<23> ++ ECLK_H<24> ECLK_B<23> ECLK_B<24> WL_O<383> WL_O<382> WL_O<381> WL_O<380> ++ WL_O<379> WL_O<378> WL_O<377> WL_O<376> WL_O<375> WL_O<374> WL_O<373> ++ WL_O<372> WL_O<371> WL_O<370> WL_O<369> WL_O<368> VDD VSS / ++ RM_IHPSG13_512x8_c2_1P_DEC04 +XSEL<22> ADDR_N_I<3> ADDR_N_I<2> ADDR_N_I<1> ADDR_N_I<0> CS00<22> ECLK_H<22> ++ ECLK_H<23> ECLK_B<22> ECLK_B<23> WL_O<367> WL_O<366> WL_O<365> WL_O<364> ++ WL_O<363> WL_O<362> WL_O<361> WL_O<360> WL_O<359> WL_O<358> WL_O<357> ++ WL_O<356> WL_O<355> WL_O<354> WL_O<353> WL_O<352> VDD VSS / ++ RM_IHPSG13_512x8_c2_1P_DEC04 +XSEL<21> ADDR_N_I<3> ADDR_N_I<2> ADDR_N_I<1> ADDR_N_I<0> CS00<21> ECLK_H<21> ++ ECLK_H<22> ECLK_B<21> ECLK_B<22> WL_O<351> WL_O<350> WL_O<349> WL_O<348> ++ WL_O<347> WL_O<346> WL_O<345> WL_O<344> WL_O<343> WL_O<342> WL_O<341> ++ WL_O<340> WL_O<339> WL_O<338> WL_O<337> WL_O<336> VDD VSS / ++ RM_IHPSG13_512x8_c2_1P_DEC04 +XSEL<20> ADDR_N_I<3> ADDR_N_I<2> ADDR_N_I<1> ADDR_N_I<0> CS00<20> ECLK_H<20> ++ ECLK_H<21> ECLK_B<20> ECLK_B<21> WL_O<335> WL_O<334> WL_O<333> WL_O<332> ++ WL_O<331> WL_O<330> WL_O<329> WL_O<328> WL_O<327> WL_O<326> WL_O<325> ++ WL_O<324> WL_O<323> WL_O<322> WL_O<321> WL_O<320> VDD VSS / ++ RM_IHPSG13_512x8_c2_1P_DEC04 +XSEL<19> ADDR_N_I<3> ADDR_N_I<2> ADDR_N_I<1> ADDR_N_I<0> CS00<19> ECLK_H<19> ++ ECLK_H<20> ECLK_B<19> ECLK_B<20> WL_O<319> WL_O<318> WL_O<317> WL_O<316> ++ WL_O<315> WL_O<314> WL_O<313> WL_O<312> WL_O<311> WL_O<310> WL_O<309> ++ WL_O<308> WL_O<307> WL_O<306> WL_O<305> WL_O<304> VDD VSS / ++ RM_IHPSG13_512x8_c2_1P_DEC04 +XSEL<18> ADDR_N_I<3> ADDR_N_I<2> ADDR_N_I<1> ADDR_N_I<0> CS00<18> ECLK_H<18> ++ ECLK_H<19> ECLK_B<18> ECLK_B<19> WL_O<303> WL_O<302> WL_O<301> WL_O<300> ++ WL_O<299> WL_O<298> WL_O<297> WL_O<296> WL_O<295> WL_O<294> WL_O<293> ++ WL_O<292> WL_O<291> WL_O<290> WL_O<289> WL_O<288> VDD VSS / ++ RM_IHPSG13_512x8_c2_1P_DEC04 +XSEL<17> ADDR_N_I<3> ADDR_N_I<2> ADDR_N_I<1> ADDR_N_I<0> CS00<17> ECLK_H<17> ++ ECLK_H<18> ECLK_B<17> ECLK_B<18> WL_O<287> WL_O<286> WL_O<285> WL_O<284> ++ WL_O<283> WL_O<282> WL_O<281> WL_O<280> WL_O<279> WL_O<278> WL_O<277> ++ WL_O<276> WL_O<275> WL_O<274> WL_O<273> WL_O<272> VDD VSS / ++ RM_IHPSG13_512x8_c2_1P_DEC04 +XSEL<16> ADDR_N_I<3> ADDR_N_I<2> ADDR_N_I<1> ADDR_N_I<0> CS00<16> ECLK_H<16> ++ ECLK_H<17> ECLK_B<16> ECLK_B<17> WL_O<271> WL_O<270> WL_O<269> WL_O<268> ++ WL_O<267> WL_O<266> WL_O<265> WL_O<264> WL_O<263> WL_O<262> WL_O<261> ++ WL_O<260> WL_O<259> WL_O<258> WL_O<257> WL_O<256> VDD VSS / ++ RM_IHPSG13_512x8_c2_1P_DEC04 +XSEL<15> ADDR_N_I<3> ADDR_N_I<2> ADDR_N_I<1> ADDR_N_I<0> CS00<15> ECLK_H<15> ++ ECLK_H<16> ECLK_B<15> ECLK_B<16> WL_O<255> WL_O<254> WL_O<253> WL_O<252> ++ WL_O<251> WL_O<250> WL_O<249> WL_O<248> WL_O<247> WL_O<246> WL_O<245> ++ WL_O<244> WL_O<243> WL_O<242> WL_O<241> WL_O<240> VDD VSS / ++ RM_IHPSG13_512x8_c2_1P_DEC04 +XSEL<14> ADDR_N_I<3> ADDR_N_I<2> ADDR_N_I<1> ADDR_N_I<0> CS00<14> ECLK_H<14> ++ ECLK_H<15> ECLK_B<14> ECLK_B<15> WL_O<239> WL_O<238> WL_O<237> WL_O<236> ++ WL_O<235> WL_O<234> WL_O<233> WL_O<232> WL_O<231> WL_O<230> WL_O<229> ++ WL_O<228> WL_O<227> WL_O<226> WL_O<225> WL_O<224> VDD VSS / ++ RM_IHPSG13_512x8_c2_1P_DEC04 +XSEL<13> ADDR_N_I<3> ADDR_N_I<2> ADDR_N_I<1> ADDR_N_I<0> CS00<13> ECLK_H<13> ++ ECLK_H<14> ECLK_B<13> ECLK_B<14> WL_O<223> WL_O<222> WL_O<221> WL_O<220> ++ WL_O<219> WL_O<218> WL_O<217> WL_O<216> WL_O<215> WL_O<214> WL_O<213> ++ WL_O<212> WL_O<211> WL_O<210> WL_O<209> WL_O<208> VDD VSS / ++ RM_IHPSG13_512x8_c2_1P_DEC04 +XSEL<12> ADDR_N_I<3> ADDR_N_I<2> ADDR_N_I<1> ADDR_N_I<0> CS00<12> ECLK_H<12> ++ ECLK_H<13> ECLK_B<12> ECLK_B<13> WL_O<207> WL_O<206> WL_O<205> WL_O<204> ++ WL_O<203> WL_O<202> WL_O<201> WL_O<200> WL_O<199> WL_O<198> WL_O<197> ++ WL_O<196> WL_O<195> WL_O<194> WL_O<193> WL_O<192> VDD VSS / ++ RM_IHPSG13_512x8_c2_1P_DEC04 +XSEL<11> ADDR_N_I<3> ADDR_N_I<2> ADDR_N_I<1> ADDR_N_I<0> CS00<11> ECLK_H<11> ++ ECLK_H<12> ECLK_B<11> ECLK_B<12> WL_O<191> WL_O<190> WL_O<189> WL_O<188> ++ WL_O<187> WL_O<186> WL_O<185> WL_O<184> WL_O<183> WL_O<182> WL_O<181> ++ WL_O<180> WL_O<179> WL_O<178> WL_O<177> WL_O<176> VDD VSS / ++ RM_IHPSG13_512x8_c2_1P_DEC04 +XSEL<10> ADDR_N_I<3> ADDR_N_I<2> ADDR_N_I<1> ADDR_N_I<0> CS00<10> ECLK_H<10> ++ ECLK_H<11> ECLK_B<10> ECLK_B<11> WL_O<175> WL_O<174> WL_O<173> WL_O<172> ++ WL_O<171> WL_O<170> WL_O<169> WL_O<168> WL_O<167> WL_O<166> WL_O<165> ++ WL_O<164> WL_O<163> WL_O<162> WL_O<161> WL_O<160> VDD VSS / ++ RM_IHPSG13_512x8_c2_1P_DEC04 +XSEL<9> ADDR_N_I<3> ADDR_N_I<2> ADDR_N_I<1> ADDR_N_I<0> CS00<9> ECLK_H<9> ++ ECLK_H<10> ECLK_B<9> ECLK_B<10> WL_O<159> WL_O<158> WL_O<157> WL_O<156> ++ WL_O<155> WL_O<154> WL_O<153> WL_O<152> WL_O<151> WL_O<150> WL_O<149> ++ WL_O<148> WL_O<147> WL_O<146> WL_O<145> WL_O<144> VDD VSS / ++ RM_IHPSG13_512x8_c2_1P_DEC04 +XSEL<8> ADDR_N_I<3> ADDR_N_I<2> ADDR_N_I<1> ADDR_N_I<0> CS00<8> ECLK_H<8> ++ ECLK_H<9> ECLK_B<8> ECLK_B<9> WL_O<143> WL_O<142> WL_O<141> WL_O<140> ++ WL_O<139> WL_O<138> WL_O<137> WL_O<136> WL_O<135> WL_O<134> WL_O<133> ++ WL_O<132> WL_O<131> WL_O<130> WL_O<129> WL_O<128> VDD VSS / ++ RM_IHPSG13_512x8_c2_1P_DEC04 +XSEL<7> ADDR_N_I<3> ADDR_N_I<2> ADDR_N_I<1> ADDR_N_I<0> CS00<7> ECLK_H<7> ++ ECLK_H<8> ECLK_B<7> ECLK_B<8> WL_O<127> WL_O<126> WL_O<125> WL_O<124> ++ WL_O<123> WL_O<122> WL_O<121> WL_O<120> WL_O<119> WL_O<118> WL_O<117> ++ WL_O<116> WL_O<115> WL_O<114> WL_O<113> WL_O<112> VDD VSS / ++ RM_IHPSG13_512x8_c2_1P_DEC04 +XSEL<6> ADDR_N_I<3> ADDR_N_I<2> ADDR_N_I<1> ADDR_N_I<0> CS00<6> ECLK_H<6> ++ ECLK_H<7> ECLK_B<6> ECLK_B<7> WL_O<111> WL_O<110> WL_O<109> WL_O<108> ++ WL_O<107> WL_O<106> WL_O<105> WL_O<104> WL_O<103> WL_O<102> WL_O<101> ++ WL_O<100> WL_O<99> WL_O<98> WL_O<97> WL_O<96> VDD VSS / ++ RM_IHPSG13_512x8_c2_1P_DEC04 +XSEL<5> ADDR_N_I<3> ADDR_N_I<2> ADDR_N_I<1> ADDR_N_I<0> CS00<5> ECLK_H<5> ++ ECLK_H<6> ECLK_B<5> ECLK_B<6> WL_O<95> WL_O<94> WL_O<93> WL_O<92> WL_O<91> ++ WL_O<90> WL_O<89> WL_O<88> WL_O<87> WL_O<86> WL_O<85> WL_O<84> WL_O<83> ++ WL_O<82> WL_O<81> WL_O<80> VDD VSS / RM_IHPSG13_512x8_c2_1P_DEC04 +XSEL<4> ADDR_N_I<3> ADDR_N_I<2> ADDR_N_I<1> ADDR_N_I<0> CS00<4> ECLK_H<4> ++ ECLK_H<5> ECLK_B<4> ECLK_B<5> WL_O<79> WL_O<78> WL_O<77> WL_O<76> WL_O<75> ++ WL_O<74> WL_O<73> WL_O<72> WL_O<71> WL_O<70> WL_O<69> WL_O<68> WL_O<67> ++ WL_O<66> WL_O<65> WL_O<64> VDD VSS / RM_IHPSG13_512x8_c2_1P_DEC04 +XSEL<3> ADDR_N_I<3> ADDR_N_I<2> ADDR_N_I<1> ADDR_N_I<0> CS00<3> ECLK_H<3> ++ ECLK_H<4> ECLK_B<3> ECLK_B<4> WL_O<63> WL_O<62> WL_O<61> WL_O<60> WL_O<59> ++ WL_O<58> WL_O<57> WL_O<56> WL_O<55> WL_O<54> WL_O<53> WL_O<52> WL_O<51> ++ WL_O<50> WL_O<49> WL_O<48> VDD VSS / RM_IHPSG13_512x8_c2_1P_DEC04 +XSEL<2> ADDR_N_I<3> ADDR_N_I<2> ADDR_N_I<1> ADDR_N_I<0> CS00<2> ECLK_H<2> ++ ECLK_H<3> ECLK_B<2> ECLK_B<3> WL_O<47> WL_O<46> WL_O<45> WL_O<44> WL_O<43> ++ WL_O<42> WL_O<41> WL_O<40> WL_O<39> WL_O<38> WL_O<37> WL_O<36> WL_O<35> ++ WL_O<34> WL_O<33> WL_O<32> VDD VSS / RM_IHPSG13_512x8_c2_1P_DEC04 +XSEL<1> ADDR_N_I<3> ADDR_N_I<2> ADDR_N_I<1> ADDR_N_I<0> CS00<1> ECLK_H<1> ++ ECLK_H<2> ECLK_B<1> ECLK_B<2> WL_O<31> WL_O<30> WL_O<29> WL_O<28> WL_O<27> ++ WL_O<26> WL_O<25> WL_O<24> WL_O<23> WL_O<22> WL_O<21> WL_O<20> WL_O<19> ++ WL_O<18> WL_O<17> WL_O<16> VDD VSS / RM_IHPSG13_512x8_c2_1P_DEC04 +XSEL<0> ADDR_N_I<3> ADDR_N_I<2> ADDR_N_I<1> ADDR_N_I<0> CS00<0> ECLK_I ++ ECLK_H<1> ECLK_B<0> ECLK_B<1> WL_O<15> WL_O<14> WL_O<13> WL_O<12> WL_O<11> ++ WL_O<10> WL_O<9> WL_O<8> WL_O<7> WL_O<6> WL_O<5> WL_O<4> WL_O<3> WL_O<2> ++ WL_O<1> WL_O<0> VDD VSS / RM_IHPSG13_512x8_c2_1P_DEC04 +XDEC01<10> ADDR_N_I<9> ADDR_N_I<8> CS_I CS04<1> VDD VSS / ++ RM_IHPSG13_512x8_c2_1P_DEC01 +XDEC01<9> ADDR_N_I<7> ADDR_N_I<6> CS04<1> CS02<5> VDD VSS / ++ RM_IHPSG13_512x8_c2_1P_DEC01 +XDEC01<8> ADDR_N_I<7> ADDR_N_I<6> CS04<0> CS02<1> VDD VSS / ++ RM_IHPSG13_512x8_c2_1P_DEC01 +XDEC01<7> ADDR_N_I<5> ADDR_N_I<4> CS02<7> CS00<29> VDD VSS / ++ RM_IHPSG13_512x8_c2_1P_DEC01 +XDEC01<6> ADDR_N_I<5> ADDR_N_I<4> CS02<6> CS00<25> VDD VSS / ++ RM_IHPSG13_512x8_c2_1P_DEC01 +XDEC01<5> ADDR_N_I<5> ADDR_N_I<4> CS02<5> CS00<21> VDD VSS / ++ RM_IHPSG13_512x8_c2_1P_DEC01 +XDEC01<4> ADDR_N_I<5> ADDR_N_I<4> CS02<4> CS00<17> VDD VSS / ++ RM_IHPSG13_512x8_c2_1P_DEC01 +XDEC01<3> ADDR_N_I<5> ADDR_N_I<4> CS02<3> CS00<13> VDD VSS / ++ RM_IHPSG13_512x8_c2_1P_DEC01 +XDEC01<2> ADDR_N_I<5> ADDR_N_I<4> CS02<2> CS00<9> VDD VSS / ++ RM_IHPSG13_512x8_c2_1P_DEC01 +XDEC01<1> ADDR_N_I<5> ADDR_N_I<4> CS02<1> CS00<5> VDD VSS / ++ RM_IHPSG13_512x8_c2_1P_DEC01 +XDEC01<0> ADDR_N_I<5> ADDR_N_I<4> CS02<0> CS00<1> VDD VSS / ++ RM_IHPSG13_512x8_c2_1P_DEC01 +XDEC10<9> ADDR_N_I<7> ADDR_N_I<6> CS04<1> CS02<6> VDD VSS / ++ RM_IHPSG13_512x8_c2_1P_DEC02 +XDEC10<8> ADDR_N_I<7> ADDR_N_I<6> CS04<0> CS02<2> VDD VSS / ++ RM_IHPSG13_512x8_c2_1P_DEC02 +XDEC10<7> ADDR_N_I<5> ADDR_N_I<4> CS02<7> CS00<30> VDD VSS / ++ RM_IHPSG13_512x8_c2_1P_DEC02 +XDEC10<6> ADDR_N_I<5> ADDR_N_I<4> CS02<6> CS00<26> VDD VSS / ++ RM_IHPSG13_512x8_c2_1P_DEC02 +XDEC10<5> ADDR_N_I<5> ADDR_N_I<4> CS02<5> CS00<22> VDD VSS / ++ RM_IHPSG13_512x8_c2_1P_DEC02 +XDEC10<4> ADDR_N_I<5> ADDR_N_I<4> CS02<4> CS00<18> VDD VSS / ++ RM_IHPSG13_512x8_c2_1P_DEC02 +XDEC10<3> ADDR_N_I<5> ADDR_N_I<4> CS02<3> CS00<14> VDD VSS / ++ RM_IHPSG13_512x8_c2_1P_DEC02 +XDEC10<2> ADDR_N_I<5> ADDR_N_I<4> CS02<2> CS00<10> VDD VSS / ++ RM_IHPSG13_512x8_c2_1P_DEC02 +XDEC10<1> ADDR_N_I<5> ADDR_N_I<4> CS02<1> CS00<6> VDD VSS / ++ RM_IHPSG13_512x8_c2_1P_DEC02 +XDEC10<0> ADDR_N_I<5> ADDR_N_I<4> CS02<0> CS00<2> VDD VSS / ++ RM_IHPSG13_512x8_c2_1P_DEC02 +XI0 ADDR_N_I<9> VDD VSS / RSC_IHPSG13_TIEL +.ENDS +.SUBCKT RM_IHPSG13_512x8_c2_1P_ROWREG9 ACLK_N_I ADDR_I<8> ADDR_I<7> ADDR_I<6> ADDR_I<5> ++ ADDR_I<4> ADDR_I<3> ADDR_I<2> ADDR_I<1> ADDR_I<0> ADDR_N_O<8> ADDR_N_O<7> ++ ADDR_N_O<6> ADDR_N_O<5> ADDR_N_O<4> ADDR_N_O<3> ADDR_N_O<2> ADDR_N_O<1> ++ ADDR_N_O<0> BIST_ADDR_I<8> BIST_ADDR_I<7> BIST_ADDR_I<6> BIST_ADDR_I<5> ++ BIST_ADDR_I<4> BIST_ADDR_I<3> BIST_ADDR_I<2> BIST_ADDR_I<1> BIST_ADDR_I<0> ++ BIST_EN_I VDD VSS +XINV<8> q_int<8> qn_int<8> VDD VSS / RSC_IHPSG13_CINVX2 +XINV<7> q_int<7> qn_int<7> VDD VSS / RSC_IHPSG13_CINVX2 +XINV<6> q_int<6> qn_int<6> VDD VSS / RSC_IHPSG13_CINVX2 +XINV<5> q_int<5> qn_int<5> VDD VSS / RSC_IHPSG13_CINVX2 +XINV<4> q_int<4> qn_int<4> VDD VSS / RSC_IHPSG13_CINVX2 +XINV<3> q_int<3> qn_int<3> VDD VSS / RSC_IHPSG13_CINVX2 +XINV<2> q_int<2> qn_int<2> VDD VSS / RSC_IHPSG13_CINVX2 +XINV<1> q_int<1> qn_int<1> VDD VSS / RSC_IHPSG13_CINVX2 +XINV<0> q_int<0> qn_int<0> VDD VSS / RSC_IHPSG13_CINVX2 +XDRV<8> qn_int<8> ADDR_N_O<8> VDD VSS / RSC_IHPSG13_CINVX8 +XDRV<7> qn_int<7> ADDR_N_O<7> VDD VSS / RSC_IHPSG13_CINVX8 +XDRV<6> qn_int<6> ADDR_N_O<6> VDD VSS / RSC_IHPSG13_CINVX8 +XDRV<5> qn_int<5> ADDR_N_O<5> VDD VSS / RSC_IHPSG13_CINVX8 +XDRV<4> qn_int<4> ADDR_N_O<4> VDD VSS / RSC_IHPSG13_CINVX8 +XDRV<3> qn_int<3> ADDR_N_O<3> VDD VSS / RSC_IHPSG13_CINVX8 +XDRV<2> qn_int<2> ADDR_N_O<2> VDD VSS / RSC_IHPSG13_CINVX8 +XDRV<1> qn_int<1> ADDR_N_O<1> VDD VSS / RSC_IHPSG13_CINVX8 +XDRV<0> qn_int<0> ADDR_N_O<0> VDD VSS / RSC_IHPSG13_CINVX8 +XDFF<8> BIST_EN_I BIST_ADDR_I<8> ACLK_N_I ADDR_I<8> q_int<8> net04<0> VDD ++ VSS / RSC_IHPSG13_DFNQMX2IX1 +XDFF<7> BIST_EN_I BIST_ADDR_I<7> ACLK_N_I ADDR_I<7> q_int<7> net04<1> VDD ++ VSS / RSC_IHPSG13_DFNQMX2IX1 +XDFF<6> BIST_EN_I BIST_ADDR_I<6> ACLK_N_I ADDR_I<6> q_int<6> net04<2> VDD ++ VSS / RSC_IHPSG13_DFNQMX2IX1 +XDFF<5> BIST_EN_I BIST_ADDR_I<5> ACLK_N_I ADDR_I<5> q_int<5> net04<3> VDD ++ VSS / RSC_IHPSG13_DFNQMX2IX1 +XDFF<4> BIST_EN_I BIST_ADDR_I<4> ACLK_N_I ADDR_I<4> q_int<4> net04<4> VDD ++ VSS / RSC_IHPSG13_DFNQMX2IX1 +XDFF<3> BIST_EN_I BIST_ADDR_I<3> ACLK_N_I ADDR_I<3> q_int<3> net04<5> VDD ++ VSS / RSC_IHPSG13_DFNQMX2IX1 +XDFF<2> BIST_EN_I BIST_ADDR_I<2> ACLK_N_I ADDR_I<2> q_int<2> net04<6> VDD ++ VSS / RSC_IHPSG13_DFNQMX2IX1 +XDFF<1> BIST_EN_I BIST_ADDR_I<1> ACLK_N_I ADDR_I<1> q_int<1> net04<7> VDD ++ VSS / RSC_IHPSG13_DFNQMX2IX1 +XDFF<0> BIST_EN_I BIST_ADDR_I<0> ACLK_N_I ADDR_I<0> q_int<0> net04<8> VDD ++ VSS / RSC_IHPSG13_DFNQMX2IX1 +.ENDS + +.SUBCKT RM_IHPSG13_512x8_c2_1P_ROWDEC7 ADDR_N_I<6> ADDR_N_I<5> ADDR_N_I<4> ADDR_N_I<3> ++ ADDR_N_I<2> ADDR_N_I<1> ADDR_N_I<0> CS_I ECLK_I WL_O<127> WL_O<126> ++ WL_O<125> WL_O<124> WL_O<123> WL_O<122> WL_O<121> WL_O<120> WL_O<119> ++ WL_O<118> WL_O<117> WL_O<116> WL_O<115> WL_O<114> WL_O<113> WL_O<112> ++ WL_O<111> WL_O<110> WL_O<109> WL_O<108> WL_O<107> WL_O<106> WL_O<105> ++ WL_O<104> WL_O<103> WL_O<102> WL_O<101> WL_O<100> WL_O<99> WL_O<98> WL_O<97> ++ WL_O<96> WL_O<95> WL_O<94> WL_O<93> WL_O<92> WL_O<91> WL_O<90> WL_O<89> ++ WL_O<88> WL_O<87> WL_O<86> WL_O<85> WL_O<84> WL_O<83> WL_O<82> WL_O<81> ++ WL_O<80> WL_O<79> WL_O<78> WL_O<77> WL_O<76> WL_O<75> WL_O<74> WL_O<73> ++ WL_O<72> WL_O<71> WL_O<70> WL_O<69> WL_O<68> WL_O<67> WL_O<66> WL_O<65> ++ WL_O<64> WL_O<63> WL_O<62> WL_O<61> WL_O<60> WL_O<59> WL_O<58> WL_O<57> ++ WL_O<56> WL_O<55> WL_O<54> WL_O<53> WL_O<52> WL_O<51> WL_O<50> WL_O<49> ++ WL_O<48> WL_O<47> WL_O<46> WL_O<45> WL_O<44> WL_O<43> WL_O<42> WL_O<41> ++ WL_O<40> WL_O<39> WL_O<38> WL_O<37> WL_O<36> WL_O<35> WL_O<34> WL_O<33> ++ WL_O<32> WL_O<31> WL_O<30> WL_O<29> WL_O<28> WL_O<27> WL_O<26> WL_O<25> ++ WL_O<24> WL_O<23> WL_O<22> WL_O<21> WL_O<20> WL_O<19> WL_O<18> WL_O<17> ++ WL_O<16> WL_O<15> WL_O<14> WL_O<13> WL_O<12> WL_O<11> WL_O<10> WL_O<9> ++ WL_O<8> WL_O<7> WL_O<6> WL_O<5> WL_O<4> WL_O<3> WL_O<2> WL_O<1> WL_O<0> ++ VDD VSS +XDEC11<1> ADDR_N_I<5> ADDR_N_I<4> CS04<1> CS00<7> VDD VSS / ++ RM_IHPSG13_512x8_c2_1P_DEC03 +XDEC11<0> ADDR_N_I<5> ADDR_N_I<4> CS04<0> CS00<3> VDD VSS / ++ RM_IHPSG13_512x8_c2_1P_DEC03 +XDEC10<1> ADDR_N_I<5> ADDR_N_I<4> CS04<1> CS00<6> VDD VSS / ++ RM_IHPSG13_512x8_c2_1P_DEC02 +XDEC10<0> ADDR_N_I<5> ADDR_N_I<4> CS04<0> CS00<2> VDD VSS / ++ RM_IHPSG13_512x8_c2_1P_DEC02 +XSEL<7> ADDR_N_I<3> ADDR_N_I<2> ADDR_N_I<1> ADDR_N_I<0> CS00<7> ECLK_H<7> ++ ECLK_H<8> ECLK_B<7> ECLK_B<8> WL_O<127> WL_O<126> WL_O<125> WL_O<124> ++ WL_O<123> WL_O<122> WL_O<121> WL_O<120> WL_O<119> WL_O<118> WL_O<117> ++ WL_O<116> WL_O<115> WL_O<114> WL_O<113> WL_O<112> VDD VSS / ++ RM_IHPSG13_512x8_c2_1P_DEC04 +XSEL<6> ADDR_N_I<3> ADDR_N_I<2> ADDR_N_I<1> ADDR_N_I<0> CS00<6> ECLK_H<6> ++ ECLK_H<7> ECLK_B<6> ECLK_B<7> WL_O<111> WL_O<110> WL_O<109> WL_O<108> ++ WL_O<107> WL_O<106> WL_O<105> WL_O<104> WL_O<103> WL_O<102> WL_O<101> ++ WL_O<100> WL_O<99> WL_O<98> WL_O<97> WL_O<96> VDD VSS / ++ RM_IHPSG13_512x8_c2_1P_DEC04 +XSEL<5> ADDR_N_I<3> ADDR_N_I<2> ADDR_N_I<1> ADDR_N_I<0> CS00<5> ECLK_H<5> ++ ECLK_H<6> ECLK_B<5> ECLK_B<6> WL_O<95> WL_O<94> WL_O<93> WL_O<92> WL_O<91> ++ WL_O<90> WL_O<89> WL_O<88> WL_O<87> WL_O<86> WL_O<85> WL_O<84> WL_O<83> ++ WL_O<82> WL_O<81> WL_O<80> VDD VSS / RM_IHPSG13_512x8_c2_1P_DEC04 +XSEL<4> ADDR_N_I<3> ADDR_N_I<2> ADDR_N_I<1> ADDR_N_I<0> CS00<4> ECLK_H<4> ++ ECLK_H<5> ECLK_B<4> ECLK_B<5> WL_O<79> WL_O<78> WL_O<77> WL_O<76> WL_O<75> ++ WL_O<74> WL_O<73> WL_O<72> WL_O<71> WL_O<70> WL_O<69> WL_O<68> WL_O<67> ++ WL_O<66> WL_O<65> WL_O<64> VDD VSS / RM_IHPSG13_512x8_c2_1P_DEC04 +XSEL<3> ADDR_N_I<3> ADDR_N_I<2> ADDR_N_I<1> ADDR_N_I<0> CS00<3> ECLK_H<3> ++ ECLK_H<4> ECLK_B<3> ECLK_B<4> WL_O<63> WL_O<62> WL_O<61> WL_O<60> WL_O<59> ++ WL_O<58> WL_O<57> WL_O<56> WL_O<55> WL_O<54> WL_O<53> WL_O<52> WL_O<51> ++ WL_O<50> WL_O<49> WL_O<48> VDD VSS / RM_IHPSG13_512x8_c2_1P_DEC04 +XSEL<2> ADDR_N_I<3> ADDR_N_I<2> ADDR_N_I<1> ADDR_N_I<0> CS00<2> ECLK_H<2> ++ ECLK_H<3> ECLK_B<2> ECLK_B<3> WL_O<47> WL_O<46> WL_O<45> WL_O<44> WL_O<43> ++ WL_O<42> WL_O<41> WL_O<40> WL_O<39> WL_O<38> WL_O<37> WL_O<36> WL_O<35> ++ WL_O<34> WL_O<33> WL_O<32> VDD VSS / RM_IHPSG13_512x8_c2_1P_DEC04 +XSEL<1> ADDR_N_I<3> ADDR_N_I<2> ADDR_N_I<1> ADDR_N_I<0> CS00<1> ECLK_H<1> ++ ECLK_H<2> ECLK_B<1> ECLK_B<2> WL_O<31> WL_O<30> WL_O<29> WL_O<28> WL_O<27> ++ WL_O<26> WL_O<25> WL_O<24> WL_O<23> WL_O<22> WL_O<21> WL_O<20> WL_O<19> ++ WL_O<18> WL_O<17> WL_O<16> VDD VSS / RM_IHPSG13_512x8_c2_1P_DEC04 +XSEL<0> ADDR_N_I<3> ADDR_N_I<2> ADDR_N_I<1> ADDR_N_I<0> CS00<0> ECLK_I ++ ECLK_H<1> ECLK_B<0> ECLK_B<1> WL_O<15> WL_O<14> WL_O<13> WL_O<12> WL_O<11> ++ WL_O<10> WL_O<9> WL_O<8> WL_O<7> WL_O<6> WL_O<5> WL_O<4> WL_O<3> WL_O<2> ++ WL_O<1> WL_O<0> VDD VSS / RM_IHPSG13_512x8_c2_1P_DEC04 +XDEC00<2> ADDR_N_I<7> ADDR_N_I<6> CS_I CS04<0> VDD VSS / ++ RM_IHPSG13_512x8_c2_1P_DEC00 +XDEC00<1> ADDR_N_I<5> ADDR_N_I<4> CS04<1> CS00<4> VDD VSS / ++ RM_IHPSG13_512x8_c2_1P_DEC00 +XDEC00<0> ADDR_N_I<5> ADDR_N_I<4> CS04<0> CS00<0> VDD VSS / ++ RM_IHPSG13_512x8_c2_1P_DEC00 +XDEC01<2> ADDR_N_I<7> ADDR_N_I<6> CS_I CS04<1> VDD VSS / ++ RM_IHPSG13_512x8_c2_1P_DEC01 +XDEC01<1> ADDR_N_I<5> ADDR_N_I<4> CS04<1> CS00<5> VDD VSS / ++ RM_IHPSG13_512x8_c2_1P_DEC01 +XDEC01<0> ADDR_N_I<5> ADDR_N_I<4> CS04<0> CS00<1> VDD VSS / ++ RM_IHPSG13_512x8_c2_1P_DEC01 +XL2<44> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<43> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<42> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<41> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<40> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<39> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<38> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<37> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<36> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<35> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<34> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<33> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<32> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<31> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<30> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<29> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<28> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<27> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<26> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<25> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<24> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<23> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<22> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<21> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<20> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<19> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<18> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<17> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<16> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<15> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<14> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<13> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<12> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<11> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<10> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<9> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<8> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<7> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<6> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<5> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<4> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<3> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<2> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<1> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI0 ADDR_N_I<7> VDD VSS / RSC_IHPSG13_TIEL +.ENDS +.SUBCKT RM_IHPSG13_512x8_c2_1P_ROWREG7 ACLK_N_I ADDR_I<6> ADDR_I<5> ADDR_I<4> ADDR_I<3> ++ ADDR_I<2> ADDR_I<1> ADDR_I<0> ADDR_N_O<6> ADDR_N_O<5> ADDR_N_O<4> ++ ADDR_N_O<3> ADDR_N_O<2> ADDR_N_O<1> ADDR_N_O<0> BIST_ADDR_I<6> ++ BIST_ADDR_I<5> BIST_ADDR_I<4> BIST_ADDR_I<3> BIST_ADDR_I<2> BIST_ADDR_I<1> ++ BIST_ADDR_I<0> BIST_EN_I VDD VSS +XINV<6> q_int<6> qn_int<6> VDD VSS / RSC_IHPSG13_CINVX2 +XINV<5> q_int<5> qn_int<5> VDD VSS / RSC_IHPSG13_CINVX2 +XINV<4> q_int<4> qn_int<4> VDD VSS / RSC_IHPSG13_CINVX2 +XINV<3> q_int<3> qn_int<3> VDD VSS / RSC_IHPSG13_CINVX2 +XINV<2> q_int<2> qn_int<2> VDD VSS / RSC_IHPSG13_CINVX2 +XINV<1> q_int<1> qn_int<1> VDD VSS / RSC_IHPSG13_CINVX2 +XINV<0> q_int<0> qn_int<0> VDD VSS / RSC_IHPSG13_CINVX2 +XDRV<6> qn_int<6> ADDR_N_O<6> VDD VSS / RSC_IHPSG13_CINVX8 +XDRV<5> qn_int<5> ADDR_N_O<5> VDD VSS / RSC_IHPSG13_CINVX8 +XDRV<4> qn_int<4> ADDR_N_O<4> VDD VSS / RSC_IHPSG13_CINVX8 +XDRV<3> qn_int<3> ADDR_N_O<3> VDD VSS / RSC_IHPSG13_CINVX8 +XDRV<2> qn_int<2> ADDR_N_O<2> VDD VSS / RSC_IHPSG13_CINVX8 +XDRV<1> qn_int<1> ADDR_N_O<1> VDD VSS / RSC_IHPSG13_CINVX8 +XDRV<0> qn_int<0> ADDR_N_O<0> VDD VSS / RSC_IHPSG13_CINVX8 +XDFF<6> BIST_EN_I BIST_ADDR_I<6> ACLK_N_I ADDR_I<6> q_int<6> net2<0> VDD ++ VSS / RSC_IHPSG13_DFNQMX2IX1 +XDFF<5> BIST_EN_I BIST_ADDR_I<5> ACLK_N_I ADDR_I<5> q_int<5> net2<1> VDD ++ VSS / RSC_IHPSG13_DFNQMX2IX1 +XDFF<4> BIST_EN_I BIST_ADDR_I<4> ACLK_N_I ADDR_I<4> q_int<4> net2<2> VDD ++ VSS / RSC_IHPSG13_DFNQMX2IX1 +XDFF<3> BIST_EN_I BIST_ADDR_I<3> ACLK_N_I ADDR_I<3> q_int<3> net2<3> VDD ++ VSS / RSC_IHPSG13_DFNQMX2IX1 +XDFF<2> BIST_EN_I BIST_ADDR_I<2> ACLK_N_I ADDR_I<2> q_int<2> net2<4> VDD ++ VSS / RSC_IHPSG13_DFNQMX2IX1 +XDFF<1> BIST_EN_I BIST_ADDR_I<1> ACLK_N_I ADDR_I<1> q_int<1> net2<5> VDD ++ VSS / RSC_IHPSG13_DFNQMX2IX1 +XDFF<0> BIST_EN_I BIST_ADDR_I<0> ACLK_N_I ADDR_I<0> q_int<0> net2<6> VDD ++ VSS / RSC_IHPSG13_DFNQMX2IX1 +XI11<8> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI11<7> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI11<6> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI11<5> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI11<4> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI11<3> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI11<2> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI11<1> VDD VSS / RSC_IHPSG13_FILLCAP8 +.ENDS + +.SUBCKT RM_IHPSG13_512x8_c2_1P_COLDRV13X8 ADDR_COL_I<1> ADDR_COL_I<0> ADDR_COL_O<1> ++ ADDR_COL_O<0> ADDR_DEC_I<7> ADDR_DEC_I<6> ADDR_DEC_I<5> ADDR_DEC_I<4> ++ ADDR_DEC_I<3> ADDR_DEC_I<2> ADDR_DEC_I<1> ADDR_DEC_I<0> ADDR_DEC_O<7> ++ ADDR_DEC_O<6> ADDR_DEC_O<5> ADDR_DEC_O<4> ADDR_DEC_O<3> ADDR_DEC_O<2> ++ ADDR_DEC_O<1> ADDR_DEC_O<0> DCLK_I DCLK_O RCLK_I RCLK_O WCLK_I WCLK_O ++ VDD VSS +XI0<1> VDD VSS / RSC_IHPSG13_FILLCAP4 +XI0<0> VDD VSS / RSC_IHPSG13_FILLCAP4 +XADDR_COL_DRV<1> ADDR_COL_I<1> ADDR_COL_O<1> VDD VSS / ++ RSC_IHPSG13_CBUFX8 +XADDR_COL_DRV<0> ADDR_COL_I<0> ADDR_COL_O<0> VDD VSS / ++ RSC_IHPSG13_CBUFX8 +XADDR_DEC_DRV<7> ADDR_DEC_I<7> ADDR_DEC_O<7> VDD VSS / ++ RSC_IHPSG13_CBUFX8 +XADDR_DEC_DRV<6> ADDR_DEC_I<6> ADDR_DEC_O<6> VDD VSS / ++ RSC_IHPSG13_CBUFX8 +XADDR_DEC_DRV<5> ADDR_DEC_I<5> ADDR_DEC_O<5> VDD VSS / ++ RSC_IHPSG13_CBUFX8 +XADDR_DEC_DRV<4> ADDR_DEC_I<4> ADDR_DEC_O<4> VDD VSS / ++ RSC_IHPSG13_CBUFX8 +XADDR_DEC_DRV<3> ADDR_DEC_I<3> ADDR_DEC_O<3> VDD VSS / ++ RSC_IHPSG13_CBUFX8 +XADDR_DEC_DRV<2> ADDR_DEC_I<2> ADDR_DEC_O<2> VDD VSS / ++ RSC_IHPSG13_CBUFX8 +XADDR_DEC_DRV<1> ADDR_DEC_I<1> ADDR_DEC_O<1> VDD VSS / ++ RSC_IHPSG13_CBUFX8 +XADDR_DEC_DRV<0> ADDR_DEC_I<0> ADDR_DEC_O<0> VDD VSS / ++ RSC_IHPSG13_CBUFX8 +XDCLK_DRV DCLK_I DCLK_O VDD VSS / RSC_IHPSG13_CBUFX8 +XRCLK_DRV RCLK_I RCLK_O VDD VSS / RSC_IHPSG13_CBUFX8 +XWCLK_DRV WCLK_I WCLK_O VDD VSS / RSC_IHPSG13_CBUFX8 +.ENDS +.SUBCKT RM_IHPSG13_512x8_c2_1P_WLDRV16X8 A<15> A<14> A<13> A<12> A<11> A<10> A<9> A<8> ++ A<7> A<6> A<5> A<4> A<3> A<2> A<1> A<0> Z<15> Z<14> Z<13> Z<12> Z<11> Z<10> ++ Z<9> Z<8> Z<7> Z<6> Z<5> Z<4> Z<3> Z<2> Z<1> Z<0> VDD VSS +XBUF<15> A<15> Z<15> VDD VSS / RSC_IHPSG13_WLDRVX8 +XBUF<14> A<14> Z<14> VDD VSS / RSC_IHPSG13_WLDRVX8 +XBUF<13> A<13> Z<13> VDD VSS / RSC_IHPSG13_WLDRVX8 +XBUF<12> A<12> Z<12> VDD VSS / RSC_IHPSG13_WLDRVX8 +XBUF<11> A<11> Z<11> VDD VSS / RSC_IHPSG13_WLDRVX8 +XBUF<10> A<10> Z<10> VDD VSS / RSC_IHPSG13_WLDRVX8 +XBUF<9> A<9> Z<9> VDD VSS / RSC_IHPSG13_WLDRVX8 +XBUF<8> A<8> Z<8> VDD VSS / RSC_IHPSG13_WLDRVX8 +XBUF<7> A<7> Z<7> VDD VSS / RSC_IHPSG13_WLDRVX8 +XBUF<6> A<6> Z<6> VDD VSS / RSC_IHPSG13_WLDRVX8 +XBUF<5> A<5> Z<5> VDD VSS / RSC_IHPSG13_WLDRVX8 +XBUF<4> A<4> Z<4> VDD VSS / RSC_IHPSG13_WLDRVX8 +XBUF<3> A<3> Z<3> VDD VSS / RSC_IHPSG13_WLDRVX8 +XBUF<2> A<2> Z<2> VDD VSS / RSC_IHPSG13_WLDRVX8 +XBUF<1> A<1> Z<1> VDD VSS / RSC_IHPSG13_WLDRVX8 +XBUF<0> A<0> Z<0> VDD VSS / RSC_IHPSG13_WLDRVX8 +.ENDS + + + +.SUBCKT RM_IHPSG13_512x8_c2_1P_ROWDEC6 ADDR_N_I<5> ADDR_N_I<4> ADDR_N_I<3> ADDR_N_I<2> ++ ADDR_N_I<1> ADDR_N_I<0> CS_I ECLK_I WL_O<63> WL_O<62> WL_O<61> WL_O<60> ++ WL_O<59> WL_O<58> WL_O<57> WL_O<56> WL_O<55> WL_O<54> WL_O<53> WL_O<52> ++ WL_O<51> WL_O<50> WL_O<49> WL_O<48> WL_O<47> WL_O<46> WL_O<45> WL_O<44> ++ WL_O<43> WL_O<42> WL_O<41> WL_O<40> WL_O<39> WL_O<38> WL_O<37> WL_O<36> ++ WL_O<35> WL_O<34> WL_O<33> WL_O<32> WL_O<31> WL_O<30> WL_O<29> WL_O<28> ++ WL_O<27> WL_O<26> WL_O<25> WL_O<24> WL_O<23> WL_O<22> WL_O<21> WL_O<20> ++ WL_O<19> WL_O<18> WL_O<17> WL_O<16> WL_O<15> WL_O<14> WL_O<13> WL_O<12> ++ WL_O<11> WL_O<10> WL_O<9> WL_O<8> WL_O<7> WL_O<6> WL_O<5> WL_O<4> WL_O<3> ++ WL_O<2> WL_O<1> WL_O<0> VDD VSS +XDEC11 ADDR_N_I<5> ADDR_N_I<4> CS_I CS00<3> VDD VSS / ++ RM_IHPSG13_512x8_c2_1P_DEC03 +XDEC00 ADDR_N_I<5> ADDR_N_I<4> CS_I CS00<0> VDD VSS / ++ RM_IHPSG13_512x8_c2_1P_DEC00 +XDEC01 ADDR_N_I<5> ADDR_N_I<4> CS_I CS00<1> VDD VSS / ++ RM_IHPSG13_512x8_c2_1P_DEC01 +XDEC10 ADDR_N_I<5> ADDR_N_I<4> CS_I CS00<2> VDD VSS / ++ RM_IHPSG13_512x8_c2_1P_DEC02 +XSEL<3> ADDR_N_I<3> ADDR_N_I<2> ADDR_N_I<1> ADDR_N_I<0> CS00<3> ECLK_H<3> ++ ECLK_H<4> ECLK_B<3> ECLK_B<4> WL_O<63> WL_O<62> WL_O<61> WL_O<60> WL_O<59> ++ WL_O<58> WL_O<57> WL_O<56> WL_O<55> WL_O<54> WL_O<53> WL_O<52> WL_O<51> ++ WL_O<50> WL_O<49> WL_O<48> VDD VSS / RM_IHPSG13_512x8_c2_1P_DEC04 +XSEL<2> ADDR_N_I<3> ADDR_N_I<2> ADDR_N_I<1> ADDR_N_I<0> CS00<2> ECLK_H<2> ++ ECLK_H<3> ECLK_B<2> ECLK_B<3> WL_O<47> WL_O<46> WL_O<45> WL_O<44> WL_O<43> ++ WL_O<42> WL_O<41> WL_O<40> WL_O<39> WL_O<38> WL_O<37> WL_O<36> WL_O<35> ++ WL_O<34> WL_O<33> WL_O<32> VDD VSS / RM_IHPSG13_512x8_c2_1P_DEC04 +XSEL<1> ADDR_N_I<3> ADDR_N_I<2> ADDR_N_I<1> ADDR_N_I<0> CS00<1> ECLK_H<1> ++ ECLK_H<2> ECLK_B<1> ECLK_B<2> WL_O<31> WL_O<30> WL_O<29> WL_O<28> WL_O<27> ++ WL_O<26> WL_O<25> WL_O<24> WL_O<23> WL_O<22> WL_O<21> WL_O<20> WL_O<19> ++ WL_O<18> WL_O<17> WL_O<16> VDD VSS / RM_IHPSG13_512x8_c2_1P_DEC04 +XSEL<0> ADDR_N_I<3> ADDR_N_I<2> ADDR_N_I<1> ADDR_N_I<0> CS00<0> ECLK_I ++ ECLK_H<1> ECLK_B<0> ECLK_B<1> WL_O<15> WL_O<14> WL_O<13> WL_O<12> WL_O<11> ++ WL_O<10> WL_O<9> WL_O<8> WL_O<7> WL_O<6> WL_O<5> WL_O<4> WL_O<3> WL_O<2> ++ WL_O<1> WL_O<0> VDD VSS / RM_IHPSG13_512x8_c2_1P_DEC04 +XL2<24> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<23> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<22> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<21> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<20> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<19> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<18> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<17> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<16> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<15> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<14> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<13> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<12> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<11> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<10> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<9> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<8> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<7> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<6> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<5> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<4> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<3> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<2> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<1> VDD VSS / RSC_IHPSG13_FILLCAP8 +.ENDS +.SUBCKT RM_IHPSG13_512x8_c2_1P_ROWREG6 ACLK_N_I ADDR_I<5> ADDR_I<4> ADDR_I<3> ADDR_I<2> ++ ADDR_I<1> ADDR_I<0> ADDR_N_O<5> ADDR_N_O<4> ADDR_N_O<3> ADDR_N_O<2> ++ ADDR_N_O<1> ADDR_N_O<0> BIST_ADDR_I<5> BIST_ADDR_I<4> BIST_ADDR_I<3> ++ BIST_ADDR_I<2> BIST_ADDR_I<1> BIST_ADDR_I<0> BIST_EN_I VDD VSS +XINV<5> q_int<5> qn_int<5> VDD VSS / RSC_IHPSG13_CINVX2 +XINV<4> q_int<4> qn_int<4> VDD VSS / RSC_IHPSG13_CINVX2 +XINV<3> q_int<3> qn_int<3> VDD VSS / RSC_IHPSG13_CINVX2 +XINV<2> q_int<2> qn_int<2> VDD VSS / RSC_IHPSG13_CINVX2 +XINV<1> q_int<1> qn_int<1> VDD VSS / RSC_IHPSG13_CINVX2 +XINV<0> q_int<0> qn_int<0> VDD VSS / RSC_IHPSG13_CINVX2 +XDRV<5> qn_int<5> ADDR_N_O<5> VDD VSS / RSC_IHPSG13_CINVX8 +XDRV<4> qn_int<4> ADDR_N_O<4> VDD VSS / RSC_IHPSG13_CINVX8 +XDRV<3> qn_int<3> ADDR_N_O<3> VDD VSS / RSC_IHPSG13_CINVX8 +XDRV<2> qn_int<2> ADDR_N_O<2> VDD VSS / RSC_IHPSG13_CINVX8 +XDRV<1> qn_int<1> ADDR_N_O<1> VDD VSS / RSC_IHPSG13_CINVX8 +XDRV<0> qn_int<0> ADDR_N_O<0> VDD VSS / RSC_IHPSG13_CINVX8 +XDFF<5> BIST_EN_I BIST_ADDR_I<5> ACLK_N_I ADDR_I<5> q_int<5> net2<0> VDD ++ VSS / RSC_IHPSG13_DFNQMX2IX1 +XDFF<4> BIST_EN_I BIST_ADDR_I<4> ACLK_N_I ADDR_I<4> q_int<4> net2<1> VDD ++ VSS / RSC_IHPSG13_DFNQMX2IX1 +XDFF<3> BIST_EN_I BIST_ADDR_I<3> ACLK_N_I ADDR_I<3> q_int<3> net2<2> VDD ++ VSS / RSC_IHPSG13_DFNQMX2IX1 +XDFF<2> BIST_EN_I BIST_ADDR_I<2> ACLK_N_I ADDR_I<2> q_int<2> net2<3> VDD ++ VSS / RSC_IHPSG13_DFNQMX2IX1 +XDFF<1> BIST_EN_I BIST_ADDR_I<1> ACLK_N_I ADDR_I<1> q_int<1> net2<4> VDD ++ VSS / RSC_IHPSG13_DFNQMX2IX1 +XDFF<0> BIST_EN_I BIST_ADDR_I<0> ACLK_N_I ADDR_I<0> q_int<0> net2<5> VDD ++ VSS / RSC_IHPSG13_DFNQMX2IX1 +XI11<12> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI11<11> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI11<10> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI11<9> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI11<8> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI11<7> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI11<6> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI11<5> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI11<4> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI11<3> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI11<2> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI11<1> VDD VSS / RSC_IHPSG13_FILLCAP8 +.ENDS + + +.SUBCKT RM_IHPSG13_512x8_c2_2P_COLUMN_pcell_0 A_BLC_BOT<1> A_BLC_BOT<0> A_BLC_TOP<1> A_BLC_TOP<0> A_BLT_BOT<1> A_BLT_BOT<0> A_BLT_TOP<1> A_BLT_TOP<0> A_LWL<127> A_LWL<126> A_LWL<125> A_LWL<124> A_LWL<123> A_LWL<122> A_LWL<121> A_LWL<120> A_LWL<119> A_LWL<118> A_LWL<117> A_LWL<116> A_LWL<115> A_LWL<114> A_LWL<113> A_LWL<112> A_LWL<111> A_LWL<110> A_LWL<109> A_LWL<108> A_LWL<107> A_LWL<106> A_LWL<105> A_LWL<104> A_LWL<103> A_LWL<102> A_LWL<101> A_LWL<100> A_LWL<99> A_LWL<98> A_LWL<97> A_LWL<96> A_LWL<95> A_LWL<94> A_LWL<93> A_LWL<92> A_LWL<91> A_LWL<90> A_LWL<89> A_LWL<88> A_LWL<87> A_LWL<86> A_LWL<85> A_LWL<84> A_LWL<83> A_LWL<82> A_LWL<81> A_LWL<80> A_LWL<79> A_LWL<78> A_LWL<77> A_LWL<76> A_LWL<75> A_LWL<74> A_LWL<73> A_LWL<72> A_LWL<71> A_LWL<70> A_LWL<69> A_LWL<68> A_LWL<67> A_LWL<66> A_LWL<65> A_LWL<64> A_LWL<63> A_LWL<62> A_LWL<61> A_LWL<60> A_LWL<59> A_LWL<58> A_LWL<57> A_LWL<56> A_LWL<55> A_LWL<54> A_LWL<53> A_LWL<52> A_LWL<51> A_LWL<50> A_LWL<49> A_LWL<48> A_LWL<47> A_LWL<46> A_LWL<45> A_LWL<44> A_LWL<43> A_LWL<42> A_LWL<41> A_LWL<40> A_LWL<39> A_LWL<38> A_LWL<37> A_LWL<36> A_LWL<35> A_LWL<34> A_LWL<33> A_LWL<32> A_LWL<31> A_LWL<30> A_LWL<29> A_LWL<28> A_LWL<27> A_LWL<26> A_LWL<25> A_LWL<24> A_LWL<23> A_LWL<22> A_LWL<21> A_LWL<20> A_LWL<19> A_LWL<18> A_LWL<17> A_LWL<16> A_LWL<15> A_LWL<14> A_LWL<13> A_LWL<12> A_LWL<11> A_LWL<10> A_LWL<9> A_LWL<8> A_LWL<7> A_LWL<6> A_LWL<5> A_LWL<4> A_LWL<3> A_LWL<2> A_LWL<1> A_LWL<0> A_RWL<127> A_RWL<126> A_RWL<125> A_RWL<124> A_RWL<123> A_RWL<122> A_RWL<121> A_RWL<120> A_RWL<119> A_RWL<118> A_RWL<117> A_RWL<116> A_RWL<115> A_RWL<114> A_RWL<113> A_RWL<112> A_RWL<111> A_RWL<110> A_RWL<109> A_RWL<108> A_RWL<107> A_RWL<106> A_RWL<105> A_RWL<104> A_RWL<103> A_RWL<102> A_RWL<101> A_RWL<100> A_RWL<99> A_RWL<98> A_RWL<97> A_RWL<96> A_RWL<95> A_RWL<94> A_RWL<93> A_RWL<92> A_RWL<91> A_RWL<90> A_RWL<89> A_RWL<88> A_RWL<87> A_RWL<86> A_RWL<85> A_RWL<84> A_RWL<83> A_RWL<82> A_RWL<81> A_RWL<80> A_RWL<79> A_RWL<78> A_RWL<77> A_RWL<76> A_RWL<75> A_RWL<74> A_RWL<73> A_RWL<72> A_RWL<71> A_RWL<70> A_RWL<69> A_RWL<68> A_RWL<67> A_RWL<66> A_RWL<65> A_RWL<64> A_RWL<63> A_RWL<62> A_RWL<61> A_RWL<60> A_RWL<59> A_RWL<58> A_RWL<57> A_RWL<56> A_RWL<55> A_RWL<54> A_RWL<53> A_RWL<52> A_RWL<51> A_RWL<50> A_RWL<49> A_RWL<48> A_RWL<47> A_RWL<46> A_RWL<45> A_RWL<44> A_RWL<43> A_RWL<42> A_RWL<41> A_RWL<40> A_RWL<39> A_RWL<38> A_RWL<37> A_RWL<36> A_RWL<35> A_RWL<34> A_RWL<33> A_RWL<32> A_RWL<31> A_RWL<30> A_RWL<29> A_RWL<28> A_RWL<27> A_RWL<26> A_RWL<25> A_RWL<24> A_RWL<23> A_RWL<22> A_RWL<21> A_RWL<20> A_RWL<19> A_RWL<18> A_RWL<17> A_RWL<16> A_RWL<15> A_RWL<14> A_RWL<13> A_RWL<12> A_RWL<11> A_RWL<10> A_RWL<9> A_RWL<8> A_RWL<7> A_RWL<6> A_RWL<5> A_RWL<4> A_RWL<3> A_RWL<2> A_RWL<1> A_RWL<0> B_BLC_BOT<1> B_BLC_BOT<0> B_BLC_TOP<1> B_BLC_TOP<0> B_BLT_BOT<1> B_BLT_BOT<0> B_BLT_TOP<1> B_BLT_TOP<0> B_LWL<127> B_LWL<126> B_LWL<125> B_LWL<124> B_LWL<123> B_LWL<122> B_LWL<121> B_LWL<120> B_LWL<119> B_LWL<118> B_LWL<117> B_LWL<116> B_LWL<115> B_LWL<114> B_LWL<113> B_LWL<112> B_LWL<111> B_LWL<110> B_LWL<109> B_LWL<108> B_LWL<107> B_LWL<106> B_LWL<105> B_LWL<104> B_LWL<103> B_LWL<102> B_LWL<101> B_LWL<100> B_LWL<99> B_LWL<98> B_LWL<97> B_LWL<96> B_LWL<95> B_LWL<94> B_LWL<93> B_LWL<92> B_LWL<91> B_LWL<90> B_LWL<89> B_LWL<88> B_LWL<87> B_LWL<86> B_LWL<85> B_LWL<84> B_LWL<83> B_LWL<82> B_LWL<81> B_LWL<80> B_LWL<79> B_LWL<78> B_LWL<77> B_LWL<76> B_LWL<75> B_LWL<74> B_LWL<73> B_LWL<72> B_LWL<71> B_LWL<70> B_LWL<69> B_LWL<68> B_LWL<67> B_LWL<66> B_LWL<65> B_LWL<64> B_LWL<63> B_LWL<62> B_LWL<61> B_LWL<60> B_LWL<59> B_LWL<58> B_LWL<57> B_LWL<56> B_LWL<55> B_LWL<54> B_LWL<53> B_LWL<52> B_LWL<51> B_LWL<50> B_LWL<49> B_LWL<48> B_LWL<47> B_LWL<46> B_LWL<45> B_LWL<44> B_LWL<43> B_LWL<42> B_LWL<41> B_LWL<40> B_LWL<39> B_LWL<38> B_LWL<37> B_LWL<36> B_LWL<35> B_LWL<34> B_LWL<33> B_LWL<32> B_LWL<31> B_LWL<30> B_LWL<29> B_LWL<28> B_LWL<27> B_LWL<26> B_LWL<25> B_LWL<24> B_LWL<23> B_LWL<22> B_LWL<21> B_LWL<20> B_LWL<19> B_LWL<18> B_LWL<17> B_LWL<16> B_LWL<15> B_LWL<14> B_LWL<13> B_LWL<12> B_LWL<11> B_LWL<10> B_LWL<9> B_LWL<8> B_LWL<7> B_LWL<6> B_LWL<5> B_LWL<4> B_LWL<3> B_LWL<2> B_LWL<1> B_LWL<0> B_RWL<127> B_RWL<126> B_RWL<125> B_RWL<124> B_RWL<123> B_RWL<122> B_RWL<121> B_RWL<120> B_RWL<119> B_RWL<118> B_RWL<117> B_RWL<116> B_RWL<115> B_RWL<114> B_RWL<113> B_RWL<112> B_RWL<111> B_RWL<110> B_RWL<109> B_RWL<108> B_RWL<107> B_RWL<106> B_RWL<105> B_RWL<104> B_RWL<103> B_RWL<102> B_RWL<101> B_RWL<100> B_RWL<99> B_RWL<98> B_RWL<97> B_RWL<96> B_RWL<95> B_RWL<94> B_RWL<93> B_RWL<92> B_RWL<91> B_RWL<90> B_RWL<89> B_RWL<88> B_RWL<87> B_RWL<86> B_RWL<85> B_RWL<84> B_RWL<83> B_RWL<82> B_RWL<81> B_RWL<80> B_RWL<79> B_RWL<78> B_RWL<77> B_RWL<76> B_RWL<75> B_RWL<74> B_RWL<73> B_RWL<72> B_RWL<71> B_RWL<70> B_RWL<69> B_RWL<68> B_RWL<67> B_RWL<66> B_RWL<65> B_RWL<64> B_RWL<63> B_RWL<62> B_RWL<61> B_RWL<60> B_RWL<59> B_RWL<58> B_RWL<57> B_RWL<56> B_RWL<55> B_RWL<54> B_RWL<53> B_RWL<52> B_RWL<51> B_RWL<50> B_RWL<49> B_RWL<48> B_RWL<47> B_RWL<46> B_RWL<45> B_RWL<44> B_RWL<43> B_RWL<42> B_RWL<41> B_RWL<40> B_RWL<39> B_RWL<38> B_RWL<37> B_RWL<36> B_RWL<35> B_RWL<34> B_RWL<33> B_RWL<32> B_RWL<31> B_RWL<30> B_RWL<29> B_RWL<28> B_RWL<27> B_RWL<26> B_RWL<25> B_RWL<24> B_RWL<23> B_RWL<22> B_RWL<21> B_RWL<20> B_RWL<19> B_RWL<18> B_RWL<17> B_RWL<16> B_RWL<15> B_RWL<14> B_RWL<13> B_RWL<12> B_RWL<11> B_RWL<10> B_RWL<9> B_RWL<8> B_RWL<7> B_RWL<6> B_RWL<5> B_RWL<4> B_RWL<3> B_RWL<2> B_RWL<1> B_RWL<0> VDD_CORE VSS +XRAM<8> A_BLC<13> A_BLC<12> A_BLC_TOP<1> A_BLC_TOP<0> A_BLT<13> A_BLT<12> A_BLT_TOP<1> A_BLT_TOP<0> A_LWL<127> A_LWL<126> A_LWL<125> A_LWL<124> A_LWL<123> A_LWL<122> A_LWL<121> A_LWL<120> A_LWL<119> A_LWL<118> A_LWL<117> A_LWL<116> A_LWL<115> A_LWL<114> A_LWL<113> A_LWL<112> A_RWL<127> A_RWL<126> A_RWL<125> A_RWL<124> A_RWL<123> A_RWL<122> A_RWL<121> A_RWL<120> A_RWL<119> A_RWL<118> A_RWL<117> A_RWL<116> A_RWL<115> A_RWL<114> A_RWL<113> A_RWL<112> B_BLC<13> B_BLC<12> B_BLC_TOP<1> B_BLC_TOP<0> B_BLT<13> B_BLT<12> B_BLT_TOP<1> B_BLT_TOP<0> B_LWL<127> B_LWL<126> B_LWL<125> B_LWL<124> B_LWL<123> B_LWL<122> B_LWL<121> B_LWL<120> B_LWL<119> B_LWL<118> B_LWL<117> B_LWL<116> B_LWL<115> B_LWL<114> B_LWL<113> B_LWL<112> B_RWL<127> B_RWL<126> B_RWL<125> B_RWL<124> B_RWL<123> B_RWL<122> B_RWL<121> B_RWL<120> B_RWL<119> B_RWL<118> B_RWL<117> B_RWL<116> B_RWL<115> B_RWL<114> B_RWL<113> B_RWL<112> VDD_CORE VSS / RM_IHPSG13_512x8_c2_2P_BITKIT_16x2_SRAM +XRAM<7> A_BLC<11> A_BLC<10> A_BLC<13> A_BLC<12> A_BLT<11> A_BLT<10> A_BLT<13> A_BLT<12> A_LWL<111> A_LWL<110> A_LWL<109> A_LWL<108> A_LWL<107> A_LWL<106> A_LWL<105> A_LWL<104> A_LWL<103> A_LWL<102> A_LWL<101> A_LWL<100> A_LWL<99> A_LWL<98> A_LWL<97> A_LWL<96> A_RWL<111> A_RWL<110> A_RWL<109> A_RWL<108> A_RWL<107> A_RWL<106> A_RWL<105> A_RWL<104> A_RWL<103> A_RWL<102> A_RWL<101> A_RWL<100> A_RWL<99> A_RWL<98> A_RWL<97> A_RWL<96> B_BLC<11> B_BLC<10> B_BLC<13> B_BLC<12> B_BLT<11> B_BLT<10> B_BLT<13> B_BLT<12> B_LWL<111> B_LWL<110> B_LWL<109> B_LWL<108> B_LWL<107> B_LWL<106> B_LWL<105> B_LWL<104> B_LWL<103> B_LWL<102> B_LWL<101> B_LWL<100> B_LWL<99> B_LWL<98> B_LWL<97> B_LWL<96> B_RWL<111> B_RWL<110> B_RWL<109> B_RWL<108> B_RWL<107> B_RWL<106> B_RWL<105> B_RWL<104> B_RWL<103> B_RWL<102> B_RWL<101> B_RWL<100> B_RWL<99> B_RWL<98> B_RWL<97> B_RWL<96> VDD_CORE VSS / RM_IHPSG13_512x8_c2_2P_BITKIT_16x2_SRAM +XRAM<6> A_BLC<9> A_BLC<8> A_BLC<11> A_BLC<10> A_BLT<9> A_BLT<8> A_BLT<11> A_BLT<10> A_LWL<95> A_LWL<94> A_LWL<93> A_LWL<92> A_LWL<91> A_LWL<90> A_LWL<89> A_LWL<88> A_LWL<87> A_LWL<86> A_LWL<85> A_LWL<84> A_LWL<83> A_LWL<82> A_LWL<81> A_LWL<80> A_RWL<95> A_RWL<94> A_RWL<93> A_RWL<92> A_RWL<91> A_RWL<90> A_RWL<89> A_RWL<88> A_RWL<87> A_RWL<86> A_RWL<85> A_RWL<84> A_RWL<83> A_RWL<82> A_RWL<81> A_RWL<80> B_BLC<9> B_BLC<8> B_BLC<11> B_BLC<10> B_BLT<9> B_BLT<8> B_BLT<11> B_BLT<10> B_LWL<95> B_LWL<94> B_LWL<93> B_LWL<92> B_LWL<91> B_LWL<90> B_LWL<89> B_LWL<88> B_LWL<87> B_LWL<86> B_LWL<85> B_LWL<84> B_LWL<83> B_LWL<82> B_LWL<81> B_LWL<80> B_RWL<95> B_RWL<94> B_RWL<93> B_RWL<92> B_RWL<91> B_RWL<90> B_RWL<89> B_RWL<88> B_RWL<87> B_RWL<86> B_RWL<85> B_RWL<84> B_RWL<83> B_RWL<82> B_RWL<81> B_RWL<80> VDD_CORE VSS / RM_IHPSG13_512x8_c2_2P_BITKIT_16x2_SRAM +XRAM<5> A_BLC<7> A_BLC<6> A_BLC<9> A_BLC<8> A_BLT<7> A_BLT<6> A_BLT<9> A_BLT<8> A_LWL<79> A_LWL<78> A_LWL<77> A_LWL<76> A_LWL<75> A_LWL<74> A_LWL<73> A_LWL<72> A_LWL<71> A_LWL<70> A_LWL<69> A_LWL<68> A_LWL<67> A_LWL<66> A_LWL<65> A_LWL<64> A_RWL<79> A_RWL<78> A_RWL<77> A_RWL<76> A_RWL<75> A_RWL<74> A_RWL<73> A_RWL<72> A_RWL<71> A_RWL<70> A_RWL<69> A_RWL<68> A_RWL<67> A_RWL<66> A_RWL<65> A_RWL<64> B_BLC<7> B_BLC<6> B_BLC<9> B_BLC<8> B_BLT<7> B_BLT<6> B_BLT<9> B_BLT<8> B_LWL<79> B_LWL<78> B_LWL<77> B_LWL<76> B_LWL<75> B_LWL<74> B_LWL<73> B_LWL<72> B_LWL<71> B_LWL<70> B_LWL<69> B_LWL<68> B_LWL<67> B_LWL<66> B_LWL<65> B_LWL<64> B_RWL<79> B_RWL<78> B_RWL<77> B_RWL<76> B_RWL<75> B_RWL<74> B_RWL<73> B_RWL<72> B_RWL<71> B_RWL<70> B_RWL<69> B_RWL<68> B_RWL<67> B_RWL<66> B_RWL<65> B_RWL<64> VDD_CORE VSS / RM_IHPSG13_512x8_c2_2P_BITKIT_16x2_SRAM +XRAM<4> A_BLC<5> A_BLC<4> A_BLC<7> A_BLC<6> A_BLT<5> A_BLT<4> A_BLT<7> A_BLT<6> A_LWL<63> A_LWL<62> A_LWL<61> A_LWL<60> A_LWL<59> A_LWL<58> A_LWL<57> A_LWL<56> A_LWL<55> A_LWL<54> A_LWL<53> A_LWL<52> A_LWL<51> A_LWL<50> A_LWL<49> A_LWL<48> A_RWL<63> A_RWL<62> A_RWL<61> A_RWL<60> A_RWL<59> A_RWL<58> A_RWL<57> A_RWL<56> A_RWL<55> A_RWL<54> A_RWL<53> A_RWL<52> A_RWL<51> A_RWL<50> A_RWL<49> A_RWL<48> B_BLC<5> B_BLC<4> B_BLC<7> B_BLC<6> B_BLT<5> B_BLT<4> B_BLT<7> B_BLT<6> B_LWL<63> B_LWL<62> B_LWL<61> B_LWL<60> B_LWL<59> B_LWL<58> B_LWL<57> B_LWL<56> B_LWL<55> B_LWL<54> B_LWL<53> B_LWL<52> B_LWL<51> B_LWL<50> B_LWL<49> B_LWL<48> B_RWL<63> B_RWL<62> B_RWL<61> B_RWL<60> B_RWL<59> B_RWL<58> B_RWL<57> B_RWL<56> B_RWL<55> B_RWL<54> B_RWL<53> B_RWL<52> B_RWL<51> B_RWL<50> B_RWL<49> B_RWL<48> VDD_CORE VSS / RM_IHPSG13_512x8_c2_2P_BITKIT_16x2_SRAM +XRAM<3> A_BLC<3> A_BLC<2> A_BLC<5> A_BLC<4> A_BLT<3> A_BLT<2> A_BLT<5> A_BLT<4> A_LWL<47> A_LWL<46> A_LWL<45> A_LWL<44> A_LWL<43> A_LWL<42> A_LWL<41> A_LWL<40> A_LWL<39> A_LWL<38> A_LWL<37> A_LWL<36> A_LWL<35> A_LWL<34> A_LWL<33> A_LWL<32> A_RWL<47> A_RWL<46> A_RWL<45> A_RWL<44> A_RWL<43> A_RWL<42> A_RWL<41> A_RWL<40> A_RWL<39> A_RWL<38> A_RWL<37> A_RWL<36> A_RWL<35> A_RWL<34> A_RWL<33> A_RWL<32> B_BLC<3> B_BLC<2> B_BLC<5> B_BLC<4> B_BLT<3> B_BLT<2> B_BLT<5> B_BLT<4> B_LWL<47> B_LWL<46> B_LWL<45> B_LWL<44> B_LWL<43> B_LWL<42> B_LWL<41> B_LWL<40> B_LWL<39> B_LWL<38> B_LWL<37> B_LWL<36> B_LWL<35> B_LWL<34> B_LWL<33> B_LWL<32> B_RWL<47> B_RWL<46> B_RWL<45> B_RWL<44> B_RWL<43> B_RWL<42> B_RWL<41> B_RWL<40> B_RWL<39> B_RWL<38> B_RWL<37> B_RWL<36> B_RWL<35> B_RWL<34> B_RWL<33> B_RWL<32> VDD_CORE VSS / RM_IHPSG13_512x8_c2_2P_BITKIT_16x2_SRAM +XRAM<2> A_BLC<1> A_BLC<0> A_BLC<3> A_BLC<2> A_BLT<1> A_BLT<0> A_BLT<3> A_BLT<2> A_LWL<31> A_LWL<30> A_LWL<29> A_LWL<28> A_LWL<27> A_LWL<26> A_LWL<25> A_LWL<24> A_LWL<23> A_LWL<22> A_LWL<21> A_LWL<20> A_LWL<19> A_LWL<18> A_LWL<17> A_LWL<16> A_RWL<31> A_RWL<30> A_RWL<29> A_RWL<28> A_RWL<27> A_RWL<26> A_RWL<25> A_RWL<24> A_RWL<23> A_RWL<22> A_RWL<21> A_RWL<20> A_RWL<19> A_RWL<18> A_RWL<17> A_RWL<16> B_BLC<1> B_BLC<0> B_BLC<3> B_BLC<2> B_BLT<1> B_BLT<0> B_BLT<3> B_BLT<2> B_LWL<31> B_LWL<30> B_LWL<29> B_LWL<28> B_LWL<27> B_LWL<26> B_LWL<25> B_LWL<24> B_LWL<23> B_LWL<22> B_LWL<21> B_LWL<20> B_LWL<19> B_LWL<18> B_LWL<17> B_LWL<16> B_RWL<31> B_RWL<30> B_RWL<29> B_RWL<28> B_RWL<27> B_RWL<26> B_RWL<25> B_RWL<24> B_RWL<23> B_RWL<22> B_RWL<21> B_RWL<20> B_RWL<19> B_RWL<18> B_RWL<17> B_RWL<16> VDD_CORE VSS / RM_IHPSG13_512x8_c2_2P_BITKIT_16x2_SRAM +XRAM<1> A_BLC_BOT<1> A_BLC_BOT<0> A_BLC<1> A_BLC<0> A_BLT_BOT<1> A_BLT_BOT<0> A_BLT<1> A_BLT<0> A_LWL<15> A_LWL<14> A_LWL<13> A_LWL<12> A_LWL<11> A_LWL<10> A_LWL<9> A_LWL<8> A_LWL<7> A_LWL<6> A_LWL<5> A_LWL<4> A_LWL<3> A_LWL<2> A_LWL<1> A_LWL<0> A_RWL<15> A_RWL<14> A_RWL<13> A_RWL<12> A_RWL<11> A_RWL<10> A_RWL<9> A_RWL<8> A_RWL<7> A_RWL<6> A_RWL<5> A_RWL<4> A_RWL<3> A_RWL<2> A_RWL<1> A_RWL<0> B_BLC_BOT<1> B_BLC_BOT<0> B_BLC<1> B_BLC<0> B_BLT_BOT<1> B_BLT_BOT<0> B_BLT<1> B_BLT<0> B_LWL<15> B_LWL<14> B_LWL<13> B_LWL<12> B_LWL<11> B_LWL<10> B_LWL<9> B_LWL<8> B_LWL<7> B_LWL<6> B_LWL<5> B_LWL<4> B_LWL<3> B_LWL<2> B_LWL<1> B_LWL<0> B_RWL<15> B_RWL<14> B_RWL<13> B_RWL<12> B_RWL<11> B_RWL<10> B_RWL<9> B_RWL<8> B_RWL<7> B_RWL<6> B_RWL<5> B_RWL<4> B_RWL<3> B_RWL<2> B_RWL<1> B_RWL<0> VDD_CORE VSS / RM_IHPSG13_512x8_c2_2P_BITKIT_16x2_SRAM +XEDGE<1> A_BLC_TOP<1> A_BLC_TOP<0> A_BLT_TOP<1> A_BLT_TOP<0> B_BLC_TOP<1> B_BLC_TOP<0> B_BLT_TOP<1> B_BLT_TOP<0> VDD_CORE VSS / RM_IHPSG13_512x8_c2_2P_BITKIT_16x2_EDGE_TB +XEDGE<0> A_BLC_BOT<1> A_BLC_BOT<0> A_BLT_BOT<1> A_BLT_BOT<0> B_BLC_BOT<1> B_BLC_BOT<0> B_BLT_BOT<1> B_BLT_BOT<0> VDD_CORE VSS / RM_IHPSG13_512x8_c2_2P_BITKIT_16x2_EDGE_TB +.ENDS + + + + +.SUBCKT RM_IHPSG13_512x8_c2_2P_MATRIX_pcell_1 A_BLC<15> A_BLC<14> A_BLC<13> A_BLC<12> A_BLC<11> A_BLC<10> A_BLC<9> A_BLC<8> A_BLC<7> A_BLC<6> A_BLC<5> A_BLC<4> A_BLC<3> A_BLC<2> A_BLC<1> A_BLC<0> A_BLT<15> A_BLT<14> A_BLT<13> A_BLT<12> A_BLT<11> A_BLT<10> A_BLT<9> A_BLT<8> A_BLT<7> A_BLT<6> A_BLT<5> A_BLT<4> A_BLT<3> A_BLT<2> A_BLT<1> A_BLT<0> A_WL<127> A_WL<126> A_WL<125> A_WL<124> A_WL<123> A_WL<122> A_WL<121> A_WL<120> A_WL<119> A_WL<118> A_WL<117> A_WL<116> A_WL<115> A_WL<114> A_WL<113> A_WL<112> A_WL<111> A_WL<110> A_WL<109> A_WL<108> A_WL<107> A_WL<106> A_WL<105> A_WL<104> A_WL<103> A_WL<102> A_WL<101> A_WL<100> A_WL<99> A_WL<98> A_WL<97> A_WL<96> A_WL<95> A_WL<94> A_WL<93> A_WL<92> A_WL<91> A_WL<90> A_WL<89> A_WL<88> A_WL<87> A_WL<86> A_WL<85> A_WL<84> A_WL<83> A_WL<82> A_WL<81> A_WL<80> A_WL<79> A_WL<78> A_WL<77> A_WL<76> A_WL<75> A_WL<74> A_WL<73> A_WL<72> A_WL<71> A_WL<70> A_WL<69> A_WL<68> A_WL<67> A_WL<66> A_WL<65> A_WL<64> A_WL<63> A_WL<62> A_WL<61> A_WL<60> A_WL<59> A_WL<58> A_WL<57> A_WL<56> A_WL<55> A_WL<54> A_WL<53> A_WL<52> A_WL<51> A_WL<50> A_WL<49> A_WL<48> A_WL<47> A_WL<46> A_WL<45> A_WL<44> A_WL<43> A_WL<42> A_WL<41> A_WL<40> A_WL<39> A_WL<38> A_WL<37> A_WL<36> A_WL<35> A_WL<34> A_WL<33> A_WL<32> A_WL<31> A_WL<30> A_WL<29> A_WL<28> A_WL<27> A_WL<26> A_WL<25> A_WL<24> A_WL<23> A_WL<22> A_WL<21> A_WL<20> A_WL<19> A_WL<18> A_WL<17> A_WL<16> A_WL<15> A_WL<14> A_WL<13> A_WL<12> A_WL<11> A_WL<10> A_WL<9> A_WL<8> A_WL<7> A_WL<6> A_WL<5> A_WL<4> A_WL<3> A_WL<2> A_WL<1> A_WL<0> B_BLC<15> B_BLC<14> B_BLC<13> B_BLC<12> B_BLC<11> B_BLC<10> B_BLC<9> B_BLC<8> B_BLC<7> B_BLC<6> B_BLC<5> B_BLC<4> B_BLC<3> B_BLC<2> B_BLC<1> B_BLC<0> B_BLT<15> B_BLT<14> B_BLT<13> B_BLT<12> B_BLT<11> B_BLT<10> B_BLT<9> B_BLT<8> B_BLT<7> B_BLT<6> B_BLT<5> B_BLT<4> B_BLT<3> B_BLT<2> B_BLT<1> B_BLT<0> B_WL<127> B_WL<126> B_WL<125> B_WL<124> B_WL<123> B_WL<122> B_WL<121> B_WL<120> B_WL<119> B_WL<118> B_WL<117> B_WL<116> B_WL<115> B_WL<114> B_WL<113> B_WL<112> B_WL<111> B_WL<110> B_WL<109> B_WL<108> B_WL<107> B_WL<106> B_WL<105> B_WL<104> B_WL<103> B_WL<102> B_WL<101> B_WL<100> B_WL<99> B_WL<98> B_WL<97> B_WL<96> B_WL<95> B_WL<94> B_WL<93> B_WL<92> B_WL<91> B_WL<90> B_WL<89> B_WL<88> B_WL<87> B_WL<86> B_WL<85> B_WL<84> B_WL<83> B_WL<82> B_WL<81> B_WL<80> B_WL<79> B_WL<78> B_WL<77> B_WL<76> B_WL<75> B_WL<74> B_WL<73> B_WL<72> B_WL<71> B_WL<70> B_WL<69> B_WL<68> B_WL<67> B_WL<66> B_WL<65> B_WL<64> B_WL<63> B_WL<62> B_WL<61> B_WL<60> B_WL<59> B_WL<58> B_WL<57> B_WL<56> B_WL<55> B_WL<54> B_WL<53> B_WL<52> B_WL<51> B_WL<50> B_WL<49> B_WL<48> B_WL<47> B_WL<46> B_WL<45> B_WL<44> B_WL<43> B_WL<42> B_WL<41> B_WL<40> B_WL<39> B_WL<38> B_WL<37> B_WL<36> B_WL<35> B_WL<34> B_WL<33> B_WL<32> B_WL<31> B_WL<30> B_WL<29> B_WL<28> B_WL<27> B_WL<26> B_WL<25> B_WL<24> B_WL<23> B_WL<22> B_WL<21> B_WL<20> B_WL<19> B_WL<18> B_WL<17> B_WL<16> B_WL<15> B_WL<14> B_WL<13> B_WL<12> B_WL<11> B_WL<10> B_WL<9> B_WL<8> B_WL<7> B_WL<6> B_WL<5> B_WL<4> B_WL<3> B_WL<2> B_WL<1> B_WL<0> VDD_CORE VSS +XCORNER<3> VDD_CORE VSS / RM_IHPSG13_512x8_c2_2P_BITKIT_16x2_CORNER +XCORNER<2> VDD_CORE VSS / RM_IHPSG13_512x8_c2_2P_BITKIT_16x2_CORNER +XCORNER<1> VDD_CORE VSS / RM_IHPSG13_512x8_c2_2P_BITKIT_16x2_CORNER +XCORNER<0> VDD_CORE VSS / RM_IHPSG13_512x8_c2_2P_BITKIT_16x2_CORNER +XRAMEDGE_L<7> A_WL<127> A_WL<126> A_WL<125> A_WL<124> A_WL<123> A_WL<122> A_WL<121> A_WL<120> A_WL<119> A_WL<118> A_WL<117> A_WL<116> A_WL<115> A_WL<114> A_WL<113> A_WL<112> B_WL<127> B_WL<126> B_WL<125> B_WL<124> B_WL<123> B_WL<122> B_WL<121> B_WL<120> B_WL<119> B_WL<118> B_WL<117> B_WL<116> B_WL<115> B_WL<114> B_WL<113> B_WL<112> VDD_CORE VSS / RM_IHPSG13_512x8_c2_2P_BITKIT_16x2_EDGE_LR +XRAMEDGE_L<6> A_WL<111> A_WL<110> A_WL<109> A_WL<108> A_WL<107> A_WL<106> A_WL<105> A_WL<104> A_WL<103> A_WL<102> A_WL<101> A_WL<100> A_WL<99> A_WL<98> A_WL<97> A_WL<96> B_WL<111> B_WL<110> B_WL<109> B_WL<108> B_WL<107> B_WL<106> B_WL<105> B_WL<104> B_WL<103> B_WL<102> B_WL<101> B_WL<100> B_WL<99> B_WL<98> B_WL<97> B_WL<96> VDD_CORE VSS / RM_IHPSG13_512x8_c2_2P_BITKIT_16x2_EDGE_LR +XRAMEDGE_L<5> A_WL<95> A_WL<94> A_WL<93> A_WL<92> A_WL<91> A_WL<90> A_WL<89> A_WL<88> A_WL<87> A_WL<86> A_WL<85> A_WL<84> A_WL<83> A_WL<82> A_WL<81> A_WL<80> B_WL<95> B_WL<94> B_WL<93> B_WL<92> B_WL<91> B_WL<90> B_WL<89> B_WL<88> B_WL<87> B_WL<86> B_WL<85> B_WL<84> B_WL<83> B_WL<82> B_WL<81> B_WL<80> VDD_CORE VSS / RM_IHPSG13_512x8_c2_2P_BITKIT_16x2_EDGE_LR +XRAMEDGE_L<4> A_WL<79> A_WL<78> A_WL<77> A_WL<76> A_WL<75> A_WL<74> A_WL<73> A_WL<72> A_WL<71> A_WL<70> A_WL<69> A_WL<68> A_WL<67> A_WL<66> A_WL<65> A_WL<64> B_WL<79> B_WL<78> B_WL<77> B_WL<76> B_WL<75> B_WL<74> B_WL<73> B_WL<72> B_WL<71> B_WL<70> B_WL<69> B_WL<68> B_WL<67> B_WL<66> B_WL<65> B_WL<64> VDD_CORE VSS / RM_IHPSG13_512x8_c2_2P_BITKIT_16x2_EDGE_LR +XRAMEDGE_L<3> A_WL<63> A_WL<62> A_WL<61> A_WL<60> A_WL<59> A_WL<58> A_WL<57> A_WL<56> A_WL<55> A_WL<54> A_WL<53> A_WL<52> A_WL<51> A_WL<50> A_WL<49> A_WL<48> B_WL<63> B_WL<62> B_WL<61> B_WL<60> B_WL<59> B_WL<58> B_WL<57> B_WL<56> B_WL<55> B_WL<54> B_WL<53> B_WL<52> B_WL<51> B_WL<50> B_WL<49> B_WL<48> VDD_CORE VSS / RM_IHPSG13_512x8_c2_2P_BITKIT_16x2_EDGE_LR +XRAMEDGE_L<2> A_WL<47> A_WL<46> A_WL<45> A_WL<44> A_WL<43> A_WL<42> A_WL<41> A_WL<40> A_WL<39> A_WL<38> A_WL<37> A_WL<36> A_WL<35> A_WL<34> A_WL<33> A_WL<32> B_WL<47> B_WL<46> B_WL<45> B_WL<44> B_WL<43> B_WL<42> B_WL<41> B_WL<40> B_WL<39> B_WL<38> B_WL<37> B_WL<36> B_WL<35> B_WL<34> B_WL<33> B_WL<32> VDD_CORE VSS / RM_IHPSG13_512x8_c2_2P_BITKIT_16x2_EDGE_LR +XRAMEDGE_L<1> A_WL<31> A_WL<30> A_WL<29> A_WL<28> A_WL<27> A_WL<26> A_WL<25> A_WL<24> A_WL<23> A_WL<22> A_WL<21> A_WL<20> A_WL<19> A_WL<18> A_WL<17> A_WL<16> B_WL<31> B_WL<30> B_WL<29> B_WL<28> B_WL<27> B_WL<26> B_WL<25> B_WL<24> B_WL<23> B_WL<22> B_WL<21> B_WL<20> B_WL<19> B_WL<18> B_WL<17> B_WL<16> VDD_CORE VSS / RM_IHPSG13_512x8_c2_2P_BITKIT_16x2_EDGE_LR +XRAMEDGE_L<0> A_WL<15> A_WL<14> A_WL<13> A_WL<12> A_WL<11> A_WL<10> A_WL<9> A_WL<8> A_WL<7> A_WL<6> A_WL<5> A_WL<4> A_WL<3> A_WL<2> A_WL<1> A_WL<0> B_WL<15> B_WL<14> B_WL<13> B_WL<12> B_WL<11> B_WL<10> B_WL<9> B_WL<8> B_WL<7> B_WL<6> B_WL<5> B_WL<4> B_WL<3> B_WL<2> B_WL<1> B_WL<0> VDD_CORE VSS / RM_IHPSG13_512x8_c2_2P_BITKIT_16x2_EDGE_LR +XRAMEDGE_R<7> A_IWL<1023> A_IWL<1022> A_IWL<1021> A_IWL<1020> A_IWL<1019> A_IWL<1018> A_IWL<1017> A_IWL<1016> A_IWL<1015> A_IWL<1014> A_IWL<1013> A_IWL<1012> A_IWL<1011> A_IWL<1010> A_IWL<1009> A_IWL<1008> B_IWL<1023> B_IWL<1022> B_IWL<1021> B_IWL<1020> B_IWL<1019> B_IWL<1018> B_IWL<1017> B_IWL<1016> B_IWL<1015> B_IWL<1014> B_IWL<1013> B_IWL<1012> B_IWL<1011> B_IWL<1010> B_IWL<1009> B_IWL<1008> VDD_CORE VSS / RM_IHPSG13_512x8_c2_2P_BITKIT_16x2_EDGE_LR +XRAMEDGE_R<6> A_IWL<1007> A_IWL<1006> A_IWL<1005> A_IWL<1004> A_IWL<1003> A_IWL<1002> A_IWL<1001> A_IWL<1000> A_IWL<999> A_IWL<998> A_IWL<997> A_IWL<996> A_IWL<995> A_IWL<994> A_IWL<993> A_IWL<992> B_IWL<1007> B_IWL<1006> B_IWL<1005> B_IWL<1004> B_IWL<1003> B_IWL<1002> B_IWL<1001> B_IWL<1000> B_IWL<999> B_IWL<998> B_IWL<997> B_IWL<996> B_IWL<995> B_IWL<994> B_IWL<993> B_IWL<992> VDD_CORE VSS / RM_IHPSG13_512x8_c2_2P_BITKIT_16x2_EDGE_LR +XRAMEDGE_R<5> A_IWL<991> A_IWL<990> A_IWL<989> A_IWL<988> A_IWL<987> A_IWL<986> A_IWL<985> A_IWL<984> A_IWL<983> A_IWL<982> A_IWL<981> A_IWL<980> A_IWL<979> A_IWL<978> A_IWL<977> A_IWL<976> B_IWL<991> B_IWL<990> B_IWL<989> B_IWL<988> B_IWL<987> B_IWL<986> B_IWL<985> B_IWL<984> B_IWL<983> B_IWL<982> B_IWL<981> B_IWL<980> B_IWL<979> B_IWL<978> B_IWL<977> B_IWL<976> VDD_CORE VSS / RM_IHPSG13_512x8_c2_2P_BITKIT_16x2_EDGE_LR +XRAMEDGE_R<4> A_IWL<975> A_IWL<974> A_IWL<973> A_IWL<972> A_IWL<971> A_IWL<970> A_IWL<969> A_IWL<968> A_IWL<967> A_IWL<966> A_IWL<965> A_IWL<964> A_IWL<963> A_IWL<962> A_IWL<961> A_IWL<960> B_IWL<975> B_IWL<974> B_IWL<973> B_IWL<972> B_IWL<971> B_IWL<970> B_IWL<969> B_IWL<968> B_IWL<967> B_IWL<966> B_IWL<965> B_IWL<964> B_IWL<963> B_IWL<962> B_IWL<961> B_IWL<960> VDD_CORE VSS / RM_IHPSG13_512x8_c2_2P_BITKIT_16x2_EDGE_LR +XRAMEDGE_R<3> A_IWL<959> A_IWL<958> A_IWL<957> A_IWL<956> A_IWL<955> A_IWL<954> A_IWL<953> A_IWL<952> A_IWL<951> A_IWL<950> A_IWL<949> A_IWL<948> A_IWL<947> A_IWL<946> A_IWL<945> A_IWL<944> B_IWL<959> B_IWL<958> B_IWL<957> B_IWL<956> B_IWL<955> B_IWL<954> B_IWL<953> B_IWL<952> B_IWL<951> B_IWL<950> B_IWL<949> B_IWL<948> B_IWL<947> B_IWL<946> B_IWL<945> B_IWL<944> VDD_CORE VSS / RM_IHPSG13_512x8_c2_2P_BITKIT_16x2_EDGE_LR +XRAMEDGE_R<2> A_IWL<943> A_IWL<942> A_IWL<941> A_IWL<940> A_IWL<939> A_IWL<938> A_IWL<937> A_IWL<936> A_IWL<935> A_IWL<934> A_IWL<933> A_IWL<932> A_IWL<931> A_IWL<930> A_IWL<929> A_IWL<928> B_IWL<943> B_IWL<942> B_IWL<941> B_IWL<940> B_IWL<939> B_IWL<938> B_IWL<937> B_IWL<936> B_IWL<935> B_IWL<934> B_IWL<933> B_IWL<932> B_IWL<931> B_IWL<930> B_IWL<929> B_IWL<928> VDD_CORE VSS / RM_IHPSG13_512x8_c2_2P_BITKIT_16x2_EDGE_LR +XRAMEDGE_R<1> A_IWL<927> A_IWL<926> A_IWL<925> A_IWL<924> A_IWL<923> A_IWL<922> A_IWL<921> A_IWL<920> A_IWL<919> A_IWL<918> A_IWL<917> A_IWL<916> A_IWL<915> A_IWL<914> A_IWL<913> A_IWL<912> B_IWL<927> B_IWL<926> B_IWL<925> B_IWL<924> B_IWL<923> B_IWL<922> B_IWL<921> B_IWL<920> B_IWL<919> B_IWL<918> B_IWL<917> B_IWL<916> B_IWL<915> B_IWL<914> B_IWL<913> B_IWL<912> VDD_CORE VSS / RM_IHPSG13_512x8_c2_2P_BITKIT_16x2_EDGE_LR +XRAMEDGE_R<0> A_IWL<911> A_IWL<910> A_IWL<909> A_IWL<908> A_IWL<907> A_IWL<906> A_IWL<905> A_IWL<904> A_IWL<903> A_IWL<902> A_IWL<901> A_IWL<900> A_IWL<899> A_IWL<898> A_IWL<897> A_IWL<896> B_IWL<911> B_IWL<910> B_IWL<909> B_IWL<908> B_IWL<907> B_IWL<906> B_IWL<905> B_IWL<904> B_IWL<903> B_IWL<902> B_IWL<901> B_IWL<900> B_IWL<899> B_IWL<898> B_IWL<897> B_IWL<896> VDD_CORE VSS / RM_IHPSG13_512x8_c2_2P_BITKIT_16x2_EDGE_LR +XCOL<7> A_BLC<15> A_BLC<14> A_BLC_TOP<15> A_BLC_TOP<14> A_BLT<15> A_BLT<14> A_BLT_TOP<15> A_BLT_TOP<14> A_IWL<895> A_IWL<894> A_IWL<893> A_IWL<892> A_IWL<891> A_IWL<890> A_IWL<889> A_IWL<888> A_IWL<887> A_IWL<886> A_IWL<885> A_IWL<884> A_IWL<883> A_IWL<882> A_IWL<881> A_IWL<880> A_IWL<879> A_IWL<878> A_IWL<877> A_IWL<876> A_IWL<875> A_IWL<874> A_IWL<873> A_IWL<872> A_IWL<871> A_IWL<870> A_IWL<869> A_IWL<868> A_IWL<867> A_IWL<866> A_IWL<865> A_IWL<864> A_IWL<863> A_IWL<862> A_IWL<861> A_IWL<860> A_IWL<859> A_IWL<858> A_IWL<857> A_IWL<856> A_IWL<855> A_IWL<854> A_IWL<853> A_IWL<852> A_IWL<851> A_IWL<850> A_IWL<849> A_IWL<848> A_IWL<847> A_IWL<846> A_IWL<845> A_IWL<844> A_IWL<843> A_IWL<842> A_IWL<841> A_IWL<840> A_IWL<839> A_IWL<838> A_IWL<837> A_IWL<836> A_IWL<835> A_IWL<834> A_IWL<833> A_IWL<832> A_IWL<831> A_IWL<830> A_IWL<829> A_IWL<828> A_IWL<827> A_IWL<826> A_IWL<825> A_IWL<824> A_IWL<823> A_IWL<822> A_IWL<821> A_IWL<820> A_IWL<819> A_IWL<818> A_IWL<817> A_IWL<816> A_IWL<815> A_IWL<814> A_IWL<813> A_IWL<812> A_IWL<811> A_IWL<810> A_IWL<809> A_IWL<808> A_IWL<807> A_IWL<806> A_IWL<805> A_IWL<804> A_IWL<803> A_IWL<802> A_IWL<801> A_IWL<800> A_IWL<799> A_IWL<798> A_IWL<797> A_IWL<796> A_IWL<795> A_IWL<794> A_IWL<793> A_IWL<792> A_IWL<791> A_IWL<790> A_IWL<789> A_IWL<788> A_IWL<787> A_IWL<786> A_IWL<785> A_IWL<784> A_IWL<783> A_IWL<782> A_IWL<781> A_IWL<780> A_IWL<779> A_IWL<778> A_IWL<777> A_IWL<776> A_IWL<775> A_IWL<774> A_IWL<773> A_IWL<772> A_IWL<771> A_IWL<770> A_IWL<769> A_IWL<768> A_IWL<1023> A_IWL<1022> A_IWL<1021> A_IWL<1020> A_IWL<1019> A_IWL<1018> A_IWL<1017> A_IWL<1016> A_IWL<1015> A_IWL<1014> A_IWL<1013> A_IWL<1012> A_IWL<1011> A_IWL<1010> A_IWL<1009> A_IWL<1008> A_IWL<1007> A_IWL<1006> A_IWL<1005> A_IWL<1004> A_IWL<1003> A_IWL<1002> A_IWL<1001> A_IWL<1000> A_IWL<999> A_IWL<998> A_IWL<997> A_IWL<996> A_IWL<995> A_IWL<994> A_IWL<993> A_IWL<992> A_IWL<991> A_IWL<990> A_IWL<989> A_IWL<988> A_IWL<987> A_IWL<986> A_IWL<985> A_IWL<984> A_IWL<983> A_IWL<982> A_IWL<981> A_IWL<980> A_IWL<979> A_IWL<978> A_IWL<977> A_IWL<976> A_IWL<975> A_IWL<974> A_IWL<973> A_IWL<972> A_IWL<971> A_IWL<970> A_IWL<969> A_IWL<968> A_IWL<967> A_IWL<966> A_IWL<965> A_IWL<964> A_IWL<963> A_IWL<962> A_IWL<961> A_IWL<960> A_IWL<959> A_IWL<958> A_IWL<957> A_IWL<956> A_IWL<955> A_IWL<954> A_IWL<953> A_IWL<952> A_IWL<951> A_IWL<950> A_IWL<949> A_IWL<948> A_IWL<947> A_IWL<946> A_IWL<945> A_IWL<944> A_IWL<943> A_IWL<942> A_IWL<941> A_IWL<940> A_IWL<939> A_IWL<938> A_IWL<937> A_IWL<936> A_IWL<935> A_IWL<934> A_IWL<933> A_IWL<932> A_IWL<931> A_IWL<930> A_IWL<929> A_IWL<928> A_IWL<927> A_IWL<926> A_IWL<925> A_IWL<924> A_IWL<923> A_IWL<922> A_IWL<921> A_IWL<920> A_IWL<919> A_IWL<918> A_IWL<917> A_IWL<916> A_IWL<915> A_IWL<914> A_IWL<913> A_IWL<912> A_IWL<911> A_IWL<910> A_IWL<909> A_IWL<908> A_IWL<907> A_IWL<906> A_IWL<905> A_IWL<904> A_IWL<903> A_IWL<902> A_IWL<901> A_IWL<900> A_IWL<899> A_IWL<898> A_IWL<897> A_IWL<896> B_BLC<15> B_BLC<14> B_BLC_TOP<15> B_BLC_TOP<14> B_BLT<15> B_BLT<14> B_BLT_TOP<15> B_BLT_TOP<14> B_IWL<895> B_IWL<894> B_IWL<893> B_IWL<892> B_IWL<891> B_IWL<890> B_IWL<889> B_IWL<888> B_IWL<887> B_IWL<886> B_IWL<885> B_IWL<884> B_IWL<883> B_IWL<882> B_IWL<881> B_IWL<880> B_IWL<879> B_IWL<878> B_IWL<877> B_IWL<876> B_IWL<875> B_IWL<874> B_IWL<873> B_IWL<872> B_IWL<871> B_IWL<870> B_IWL<869> B_IWL<868> B_IWL<867> B_IWL<866> B_IWL<865> B_IWL<864> B_IWL<863> B_IWL<862> B_IWL<861> B_IWL<860> B_IWL<859> B_IWL<858> B_IWL<857> B_IWL<856> B_IWL<855> B_IWL<854> B_IWL<853> B_IWL<852> B_IWL<851> B_IWL<850> B_IWL<849> B_IWL<848> B_IWL<847> B_IWL<846> B_IWL<845> B_IWL<844> B_IWL<843> B_IWL<842> B_IWL<841> B_IWL<840> B_IWL<839> B_IWL<838> B_IWL<837> B_IWL<836> B_IWL<835> B_IWL<834> B_IWL<833> B_IWL<832> B_IWL<831> B_IWL<830> B_IWL<829> B_IWL<828> B_IWL<827> B_IWL<826> B_IWL<825> B_IWL<824> B_IWL<823> B_IWL<822> B_IWL<821> B_IWL<820> B_IWL<819> B_IWL<818> B_IWL<817> B_IWL<816> B_IWL<815> B_IWL<814> B_IWL<813> B_IWL<812> B_IWL<811> B_IWL<810> B_IWL<809> B_IWL<808> B_IWL<807> B_IWL<806> B_IWL<805> B_IWL<804> B_IWL<803> B_IWL<802> B_IWL<801> B_IWL<800> B_IWL<799> B_IWL<798> B_IWL<797> B_IWL<796> B_IWL<795> B_IWL<794> B_IWL<793> B_IWL<792> B_IWL<791> B_IWL<790> B_IWL<789> B_IWL<788> B_IWL<787> B_IWL<786> B_IWL<785> B_IWL<784> B_IWL<783> B_IWL<782> B_IWL<781> B_IWL<780> B_IWL<779> B_IWL<778> B_IWL<777> B_IWL<776> B_IWL<775> B_IWL<774> B_IWL<773> B_IWL<772> B_IWL<771> B_IWL<770> B_IWL<769> B_IWL<768> B_IWL<1023> B_IWL<1022> B_IWL<1021> B_IWL<1020> B_IWL<1019> B_IWL<1018> B_IWL<1017> B_IWL<1016> B_IWL<1015> B_IWL<1014> B_IWL<1013> B_IWL<1012> B_IWL<1011> B_IWL<1010> B_IWL<1009> B_IWL<1008> B_IWL<1007> B_IWL<1006> B_IWL<1005> B_IWL<1004> B_IWL<1003> B_IWL<1002> B_IWL<1001> B_IWL<1000> B_IWL<999> B_IWL<998> B_IWL<997> B_IWL<996> B_IWL<995> B_IWL<994> B_IWL<993> B_IWL<992> B_IWL<991> B_IWL<990> B_IWL<989> B_IWL<988> B_IWL<987> B_IWL<986> B_IWL<985> B_IWL<984> B_IWL<983> B_IWL<982> B_IWL<981> B_IWL<980> B_IWL<979> B_IWL<978> B_IWL<977> B_IWL<976> B_IWL<975> B_IWL<974> B_IWL<973> B_IWL<972> B_IWL<971> B_IWL<970> B_IWL<969> B_IWL<968> B_IWL<967> B_IWL<966> B_IWL<965> B_IWL<964> B_IWL<963> B_IWL<962> B_IWL<961> B_IWL<960> B_IWL<959> B_IWL<958> B_IWL<957> B_IWL<956> B_IWL<955> B_IWL<954> B_IWL<953> B_IWL<952> B_IWL<951> B_IWL<950> B_IWL<949> B_IWL<948> B_IWL<947> B_IWL<946> B_IWL<945> B_IWL<944> B_IWL<943> B_IWL<942> B_IWL<941> B_IWL<940> B_IWL<939> B_IWL<938> B_IWL<937> B_IWL<936> B_IWL<935> B_IWL<934> B_IWL<933> B_IWL<932> B_IWL<931> B_IWL<930> B_IWL<929> B_IWL<928> B_IWL<927> B_IWL<926> B_IWL<925> B_IWL<924> B_IWL<923> B_IWL<922> B_IWL<921> B_IWL<920> B_IWL<919> B_IWL<918> B_IWL<917> B_IWL<916> B_IWL<915> B_IWL<914> B_IWL<913> B_IWL<912> B_IWL<911> B_IWL<910> B_IWL<909> B_IWL<908> B_IWL<907> B_IWL<906> B_IWL<905> B_IWL<904> B_IWL<903> B_IWL<902> B_IWL<901> B_IWL<900> B_IWL<899> B_IWL<898> B_IWL<897> B_IWL<896> VDD_CORE VSS / RM_IHPSG13_512x8_c2_2P_COLUMN_pcell_0 +XCOL<6> A_BLC<13> A_BLC<12> A_BLC_TOP<13> A_BLC_TOP<12> A_BLT<13> A_BLT<12> A_BLT_TOP<13> A_BLT_TOP<12> A_IWL<767> A_IWL<766> A_IWL<765> A_IWL<764> A_IWL<763> A_IWL<762> A_IWL<761> A_IWL<760> A_IWL<759> A_IWL<758> A_IWL<757> A_IWL<756> A_IWL<755> A_IWL<754> A_IWL<753> A_IWL<752> A_IWL<751> A_IWL<750> A_IWL<749> A_IWL<748> A_IWL<747> A_IWL<746> A_IWL<745> A_IWL<744> A_IWL<743> A_IWL<742> A_IWL<741> A_IWL<740> A_IWL<739> A_IWL<738> A_IWL<737> A_IWL<736> A_IWL<735> A_IWL<734> A_IWL<733> A_IWL<732> A_IWL<731> A_IWL<730> A_IWL<729> A_IWL<728> A_IWL<727> A_IWL<726> A_IWL<725> A_IWL<724> A_IWL<723> A_IWL<722> A_IWL<721> A_IWL<720> A_IWL<719> A_IWL<718> A_IWL<717> A_IWL<716> A_IWL<715> A_IWL<714> A_IWL<713> A_IWL<712> A_IWL<711> A_IWL<710> A_IWL<709> A_IWL<708> A_IWL<707> A_IWL<706> A_IWL<705> A_IWL<704> A_IWL<703> A_IWL<702> A_IWL<701> A_IWL<700> A_IWL<699> A_IWL<698> A_IWL<697> A_IWL<696> A_IWL<695> A_IWL<694> A_IWL<693> A_IWL<692> A_IWL<691> A_IWL<690> A_IWL<689> A_IWL<688> A_IWL<687> A_IWL<686> A_IWL<685> A_IWL<684> A_IWL<683> A_IWL<682> A_IWL<681> A_IWL<680> A_IWL<679> A_IWL<678> A_IWL<677> A_IWL<676> A_IWL<675> A_IWL<674> A_IWL<673> A_IWL<672> A_IWL<671> A_IWL<670> A_IWL<669> A_IWL<668> A_IWL<667> A_IWL<666> A_IWL<665> A_IWL<664> A_IWL<663> A_IWL<662> A_IWL<661> A_IWL<660> A_IWL<659> A_IWL<658> A_IWL<657> A_IWL<656> A_IWL<655> A_IWL<654> A_IWL<653> A_IWL<652> A_IWL<651> A_IWL<650> A_IWL<649> A_IWL<648> A_IWL<647> A_IWL<646> A_IWL<645> A_IWL<644> A_IWL<643> A_IWL<642> A_IWL<641> A_IWL<640> A_IWL<895> A_IWL<894> A_IWL<893> A_IWL<892> A_IWL<891> A_IWL<890> A_IWL<889> A_IWL<888> A_IWL<887> A_IWL<886> A_IWL<885> A_IWL<884> A_IWL<883> A_IWL<882> A_IWL<881> A_IWL<880> A_IWL<879> A_IWL<878> A_IWL<877> A_IWL<876> A_IWL<875> A_IWL<874> A_IWL<873> A_IWL<872> A_IWL<871> A_IWL<870> A_IWL<869> A_IWL<868> A_IWL<867> A_IWL<866> A_IWL<865> A_IWL<864> A_IWL<863> A_IWL<862> A_IWL<861> A_IWL<860> A_IWL<859> A_IWL<858> A_IWL<857> A_IWL<856> A_IWL<855> A_IWL<854> A_IWL<853> A_IWL<852> A_IWL<851> A_IWL<850> A_IWL<849> A_IWL<848> A_IWL<847> A_IWL<846> A_IWL<845> A_IWL<844> A_IWL<843> A_IWL<842> A_IWL<841> A_IWL<840> A_IWL<839> A_IWL<838> A_IWL<837> A_IWL<836> A_IWL<835> A_IWL<834> A_IWL<833> A_IWL<832> A_IWL<831> A_IWL<830> A_IWL<829> A_IWL<828> A_IWL<827> A_IWL<826> A_IWL<825> A_IWL<824> A_IWL<823> A_IWL<822> A_IWL<821> A_IWL<820> A_IWL<819> A_IWL<818> A_IWL<817> A_IWL<816> A_IWL<815> A_IWL<814> A_IWL<813> A_IWL<812> A_IWL<811> A_IWL<810> A_IWL<809> A_IWL<808> A_IWL<807> A_IWL<806> A_IWL<805> A_IWL<804> A_IWL<803> A_IWL<802> A_IWL<801> A_IWL<800> A_IWL<799> A_IWL<798> A_IWL<797> A_IWL<796> A_IWL<795> A_IWL<794> A_IWL<793> A_IWL<792> A_IWL<791> A_IWL<790> A_IWL<789> A_IWL<788> A_IWL<787> A_IWL<786> A_IWL<785> A_IWL<784> A_IWL<783> A_IWL<782> A_IWL<781> A_IWL<780> A_IWL<779> A_IWL<778> A_IWL<777> A_IWL<776> A_IWL<775> A_IWL<774> A_IWL<773> A_IWL<772> A_IWL<771> A_IWL<770> A_IWL<769> A_IWL<768> B_BLC<13> B_BLC<12> B_BLC_TOP<13> B_BLC_TOP<12> B_BLT<13> B_BLT<12> B_BLT_TOP<13> B_BLT_TOP<12> B_IWL<767> B_IWL<766> B_IWL<765> B_IWL<764> B_IWL<763> B_IWL<762> B_IWL<761> B_IWL<760> B_IWL<759> B_IWL<758> B_IWL<757> B_IWL<756> B_IWL<755> B_IWL<754> B_IWL<753> B_IWL<752> B_IWL<751> B_IWL<750> B_IWL<749> B_IWL<748> B_IWL<747> B_IWL<746> B_IWL<745> B_IWL<744> B_IWL<743> B_IWL<742> B_IWL<741> B_IWL<740> B_IWL<739> B_IWL<738> B_IWL<737> B_IWL<736> B_IWL<735> B_IWL<734> B_IWL<733> B_IWL<732> B_IWL<731> B_IWL<730> B_IWL<729> B_IWL<728> B_IWL<727> B_IWL<726> B_IWL<725> B_IWL<724> B_IWL<723> B_IWL<722> B_IWL<721> B_IWL<720> B_IWL<719> B_IWL<718> B_IWL<717> B_IWL<716> B_IWL<715> B_IWL<714> B_IWL<713> B_IWL<712> B_IWL<711> B_IWL<710> B_IWL<709> B_IWL<708> B_IWL<707> B_IWL<706> B_IWL<705> B_IWL<704> B_IWL<703> B_IWL<702> B_IWL<701> B_IWL<700> B_IWL<699> B_IWL<698> B_IWL<697> B_IWL<696> B_IWL<695> B_IWL<694> B_IWL<693> B_IWL<692> B_IWL<691> B_IWL<690> B_IWL<689> B_IWL<688> B_IWL<687> B_IWL<686> B_IWL<685> B_IWL<684> B_IWL<683> B_IWL<682> B_IWL<681> B_IWL<680> B_IWL<679> B_IWL<678> B_IWL<677> B_IWL<676> B_IWL<675> B_IWL<674> B_IWL<673> B_IWL<672> B_IWL<671> B_IWL<670> B_IWL<669> B_IWL<668> B_IWL<667> B_IWL<666> B_IWL<665> B_IWL<664> B_IWL<663> B_IWL<662> B_IWL<661> B_IWL<660> B_IWL<659> B_IWL<658> B_IWL<657> B_IWL<656> B_IWL<655> B_IWL<654> B_IWL<653> B_IWL<652> B_IWL<651> B_IWL<650> B_IWL<649> B_IWL<648> B_IWL<647> B_IWL<646> B_IWL<645> B_IWL<644> B_IWL<643> B_IWL<642> B_IWL<641> B_IWL<640> B_IWL<895> B_IWL<894> B_IWL<893> B_IWL<892> B_IWL<891> B_IWL<890> B_IWL<889> B_IWL<888> B_IWL<887> B_IWL<886> B_IWL<885> B_IWL<884> B_IWL<883> B_IWL<882> B_IWL<881> B_IWL<880> B_IWL<879> B_IWL<878> B_IWL<877> B_IWL<876> B_IWL<875> B_IWL<874> B_IWL<873> B_IWL<872> B_IWL<871> B_IWL<870> B_IWL<869> B_IWL<868> B_IWL<867> B_IWL<866> B_IWL<865> B_IWL<864> B_IWL<863> B_IWL<862> B_IWL<861> B_IWL<860> B_IWL<859> B_IWL<858> B_IWL<857> B_IWL<856> B_IWL<855> B_IWL<854> B_IWL<853> B_IWL<852> B_IWL<851> B_IWL<850> B_IWL<849> B_IWL<848> B_IWL<847> B_IWL<846> B_IWL<845> B_IWL<844> B_IWL<843> B_IWL<842> B_IWL<841> B_IWL<840> B_IWL<839> B_IWL<838> B_IWL<837> B_IWL<836> B_IWL<835> B_IWL<834> B_IWL<833> B_IWL<832> B_IWL<831> B_IWL<830> B_IWL<829> B_IWL<828> B_IWL<827> B_IWL<826> B_IWL<825> B_IWL<824> B_IWL<823> B_IWL<822> B_IWL<821> B_IWL<820> B_IWL<819> B_IWL<818> B_IWL<817> B_IWL<816> B_IWL<815> B_IWL<814> B_IWL<813> B_IWL<812> B_IWL<811> B_IWL<810> B_IWL<809> B_IWL<808> B_IWL<807> B_IWL<806> B_IWL<805> B_IWL<804> B_IWL<803> B_IWL<802> B_IWL<801> B_IWL<800> B_IWL<799> B_IWL<798> B_IWL<797> B_IWL<796> B_IWL<795> B_IWL<794> B_IWL<793> B_IWL<792> B_IWL<791> B_IWL<790> B_IWL<789> B_IWL<788> B_IWL<787> B_IWL<786> B_IWL<785> B_IWL<784> B_IWL<783> B_IWL<782> B_IWL<781> B_IWL<780> B_IWL<779> B_IWL<778> B_IWL<777> B_IWL<776> B_IWL<775> B_IWL<774> B_IWL<773> B_IWL<772> B_IWL<771> B_IWL<770> B_IWL<769> B_IWL<768> VDD_CORE VSS / RM_IHPSG13_512x8_c2_2P_COLUMN_pcell_0 +XCOL<5> A_BLC<11> A_BLC<10> A_BLC_TOP<11> A_BLC_TOP<10> A_BLT<11> A_BLT<10> A_BLT_TOP<11> A_BLT_TOP<10> A_IWL<639> A_IWL<638> A_IWL<637> A_IWL<636> A_IWL<635> A_IWL<634> A_IWL<633> A_IWL<632> A_IWL<631> A_IWL<630> A_IWL<629> A_IWL<628> A_IWL<627> A_IWL<626> A_IWL<625> A_IWL<624> A_IWL<623> A_IWL<622> A_IWL<621> A_IWL<620> A_IWL<619> A_IWL<618> A_IWL<617> A_IWL<616> A_IWL<615> A_IWL<614> A_IWL<613> A_IWL<612> A_IWL<611> A_IWL<610> A_IWL<609> A_IWL<608> A_IWL<607> A_IWL<606> A_IWL<605> A_IWL<604> A_IWL<603> A_IWL<602> A_IWL<601> A_IWL<600> A_IWL<599> A_IWL<598> A_IWL<597> A_IWL<596> A_IWL<595> A_IWL<594> A_IWL<593> A_IWL<592> A_IWL<591> A_IWL<590> A_IWL<589> A_IWL<588> A_IWL<587> A_IWL<586> A_IWL<585> A_IWL<584> A_IWL<583> A_IWL<582> A_IWL<581> A_IWL<580> A_IWL<579> A_IWL<578> A_IWL<577> A_IWL<576> A_IWL<575> A_IWL<574> A_IWL<573> A_IWL<572> A_IWL<571> A_IWL<570> A_IWL<569> A_IWL<568> A_IWL<567> A_IWL<566> A_IWL<565> A_IWL<564> A_IWL<563> A_IWL<562> A_IWL<561> A_IWL<560> A_IWL<559> A_IWL<558> A_IWL<557> A_IWL<556> A_IWL<555> A_IWL<554> A_IWL<553> A_IWL<552> A_IWL<551> A_IWL<550> A_IWL<549> A_IWL<548> A_IWL<547> A_IWL<546> A_IWL<545> A_IWL<544> A_IWL<543> A_IWL<542> A_IWL<541> A_IWL<540> A_IWL<539> A_IWL<538> A_IWL<537> A_IWL<536> A_IWL<535> A_IWL<534> A_IWL<533> A_IWL<532> A_IWL<531> A_IWL<530> A_IWL<529> A_IWL<528> A_IWL<527> A_IWL<526> A_IWL<525> A_IWL<524> A_IWL<523> A_IWL<522> A_IWL<521> A_IWL<520> A_IWL<519> A_IWL<518> A_IWL<517> A_IWL<516> A_IWL<515> A_IWL<514> A_IWL<513> A_IWL<512> A_IWL<767> A_IWL<766> A_IWL<765> A_IWL<764> A_IWL<763> A_IWL<762> A_IWL<761> A_IWL<760> A_IWL<759> A_IWL<758> A_IWL<757> A_IWL<756> A_IWL<755> A_IWL<754> A_IWL<753> A_IWL<752> A_IWL<751> A_IWL<750> A_IWL<749> A_IWL<748> A_IWL<747> A_IWL<746> A_IWL<745> A_IWL<744> A_IWL<743> A_IWL<742> A_IWL<741> A_IWL<740> A_IWL<739> A_IWL<738> A_IWL<737> A_IWL<736> A_IWL<735> A_IWL<734> A_IWL<733> A_IWL<732> A_IWL<731> A_IWL<730> A_IWL<729> A_IWL<728> A_IWL<727> A_IWL<726> A_IWL<725> A_IWL<724> A_IWL<723> A_IWL<722> A_IWL<721> A_IWL<720> A_IWL<719> A_IWL<718> A_IWL<717> A_IWL<716> A_IWL<715> A_IWL<714> A_IWL<713> A_IWL<712> A_IWL<711> A_IWL<710> A_IWL<709> A_IWL<708> A_IWL<707> A_IWL<706> A_IWL<705> A_IWL<704> A_IWL<703> A_IWL<702> A_IWL<701> A_IWL<700> A_IWL<699> A_IWL<698> A_IWL<697> A_IWL<696> A_IWL<695> A_IWL<694> A_IWL<693> A_IWL<692> A_IWL<691> A_IWL<690> A_IWL<689> A_IWL<688> A_IWL<687> A_IWL<686> A_IWL<685> A_IWL<684> A_IWL<683> A_IWL<682> A_IWL<681> A_IWL<680> A_IWL<679> A_IWL<678> A_IWL<677> A_IWL<676> A_IWL<675> A_IWL<674> A_IWL<673> A_IWL<672> A_IWL<671> A_IWL<670> A_IWL<669> A_IWL<668> A_IWL<667> A_IWL<666> A_IWL<665> A_IWL<664> A_IWL<663> A_IWL<662> A_IWL<661> A_IWL<660> A_IWL<659> A_IWL<658> A_IWL<657> A_IWL<656> A_IWL<655> A_IWL<654> A_IWL<653> A_IWL<652> A_IWL<651> A_IWL<650> A_IWL<649> A_IWL<648> A_IWL<647> A_IWL<646> A_IWL<645> A_IWL<644> A_IWL<643> A_IWL<642> A_IWL<641> A_IWL<640> B_BLC<11> B_BLC<10> B_BLC_TOP<11> B_BLC_TOP<10> B_BLT<11> B_BLT<10> B_BLT_TOP<11> B_BLT_TOP<10> B_IWL<639> B_IWL<638> B_IWL<637> B_IWL<636> B_IWL<635> B_IWL<634> B_IWL<633> B_IWL<632> B_IWL<631> B_IWL<630> B_IWL<629> B_IWL<628> B_IWL<627> B_IWL<626> B_IWL<625> B_IWL<624> B_IWL<623> B_IWL<622> B_IWL<621> B_IWL<620> B_IWL<619> B_IWL<618> B_IWL<617> B_IWL<616> B_IWL<615> B_IWL<614> B_IWL<613> B_IWL<612> B_IWL<611> B_IWL<610> B_IWL<609> B_IWL<608> B_IWL<607> B_IWL<606> B_IWL<605> B_IWL<604> B_IWL<603> B_IWL<602> B_IWL<601> B_IWL<600> B_IWL<599> B_IWL<598> B_IWL<597> B_IWL<596> B_IWL<595> B_IWL<594> B_IWL<593> B_IWL<592> B_IWL<591> B_IWL<590> B_IWL<589> B_IWL<588> B_IWL<587> B_IWL<586> B_IWL<585> B_IWL<584> B_IWL<583> B_IWL<582> B_IWL<581> B_IWL<580> B_IWL<579> B_IWL<578> B_IWL<577> B_IWL<576> B_IWL<575> B_IWL<574> B_IWL<573> B_IWL<572> B_IWL<571> B_IWL<570> B_IWL<569> B_IWL<568> B_IWL<567> B_IWL<566> B_IWL<565> B_IWL<564> B_IWL<563> B_IWL<562> B_IWL<561> B_IWL<560> B_IWL<559> B_IWL<558> B_IWL<557> B_IWL<556> B_IWL<555> B_IWL<554> B_IWL<553> B_IWL<552> B_IWL<551> B_IWL<550> B_IWL<549> B_IWL<548> B_IWL<547> B_IWL<546> B_IWL<545> B_IWL<544> B_IWL<543> B_IWL<542> B_IWL<541> B_IWL<540> B_IWL<539> B_IWL<538> B_IWL<537> B_IWL<536> B_IWL<535> B_IWL<534> B_IWL<533> B_IWL<532> B_IWL<531> B_IWL<530> B_IWL<529> B_IWL<528> B_IWL<527> B_IWL<526> B_IWL<525> B_IWL<524> B_IWL<523> B_IWL<522> B_IWL<521> B_IWL<520> B_IWL<519> B_IWL<518> B_IWL<517> B_IWL<516> B_IWL<515> B_IWL<514> B_IWL<513> B_IWL<512> B_IWL<767> B_IWL<766> B_IWL<765> B_IWL<764> B_IWL<763> B_IWL<762> B_IWL<761> B_IWL<760> B_IWL<759> B_IWL<758> B_IWL<757> B_IWL<756> B_IWL<755> B_IWL<754> B_IWL<753> B_IWL<752> B_IWL<751> B_IWL<750> B_IWL<749> B_IWL<748> B_IWL<747> B_IWL<746> B_IWL<745> B_IWL<744> B_IWL<743> B_IWL<742> B_IWL<741> B_IWL<740> B_IWL<739> B_IWL<738> B_IWL<737> B_IWL<736> B_IWL<735> B_IWL<734> B_IWL<733> B_IWL<732> B_IWL<731> B_IWL<730> B_IWL<729> B_IWL<728> B_IWL<727> B_IWL<726> B_IWL<725> B_IWL<724> B_IWL<723> B_IWL<722> B_IWL<721> B_IWL<720> B_IWL<719> B_IWL<718> B_IWL<717> B_IWL<716> B_IWL<715> B_IWL<714> B_IWL<713> B_IWL<712> B_IWL<711> B_IWL<710> B_IWL<709> B_IWL<708> B_IWL<707> B_IWL<706> B_IWL<705> B_IWL<704> B_IWL<703> B_IWL<702> B_IWL<701> B_IWL<700> B_IWL<699> B_IWL<698> B_IWL<697> B_IWL<696> B_IWL<695> B_IWL<694> B_IWL<693> B_IWL<692> B_IWL<691> B_IWL<690> B_IWL<689> B_IWL<688> B_IWL<687> B_IWL<686> B_IWL<685> B_IWL<684> B_IWL<683> B_IWL<682> B_IWL<681> B_IWL<680> B_IWL<679> B_IWL<678> B_IWL<677> B_IWL<676> B_IWL<675> B_IWL<674> B_IWL<673> B_IWL<672> B_IWL<671> B_IWL<670> B_IWL<669> B_IWL<668> B_IWL<667> B_IWL<666> B_IWL<665> B_IWL<664> B_IWL<663> B_IWL<662> B_IWL<661> B_IWL<660> B_IWL<659> B_IWL<658> B_IWL<657> B_IWL<656> B_IWL<655> B_IWL<654> B_IWL<653> B_IWL<652> B_IWL<651> B_IWL<650> B_IWL<649> B_IWL<648> B_IWL<647> B_IWL<646> B_IWL<645> B_IWL<644> B_IWL<643> B_IWL<642> B_IWL<641> B_IWL<640> VDD_CORE VSS / RM_IHPSG13_512x8_c2_2P_COLUMN_pcell_0 +XCOL<4> A_BLC<9> A_BLC<8> A_BLC_TOP<9> A_BLC_TOP<8> A_BLT<9> A_BLT<8> A_BLT_TOP<9> A_BLT_TOP<8> A_IWL<511> A_IWL<510> A_IWL<509> A_IWL<508> A_IWL<507> A_IWL<506> A_IWL<505> A_IWL<504> A_IWL<503> A_IWL<502> A_IWL<501> A_IWL<500> A_IWL<499> A_IWL<498> A_IWL<497> A_IWL<496> A_IWL<495> A_IWL<494> A_IWL<493> A_IWL<492> A_IWL<491> A_IWL<490> A_IWL<489> A_IWL<488> A_IWL<487> A_IWL<486> A_IWL<485> A_IWL<484> A_IWL<483> A_IWL<482> A_IWL<481> A_IWL<480> A_IWL<479> A_IWL<478> A_IWL<477> A_IWL<476> A_IWL<475> A_IWL<474> A_IWL<473> A_IWL<472> A_IWL<471> A_IWL<470> A_IWL<469> A_IWL<468> A_IWL<467> A_IWL<466> A_IWL<465> A_IWL<464> A_IWL<463> A_IWL<462> A_IWL<461> A_IWL<460> A_IWL<459> A_IWL<458> A_IWL<457> A_IWL<456> A_IWL<455> A_IWL<454> A_IWL<453> A_IWL<452> A_IWL<451> A_IWL<450> A_IWL<449> A_IWL<448> A_IWL<447> A_IWL<446> A_IWL<445> A_IWL<444> A_IWL<443> A_IWL<442> A_IWL<441> A_IWL<440> A_IWL<439> A_IWL<438> A_IWL<437> A_IWL<436> A_IWL<435> A_IWL<434> A_IWL<433> A_IWL<432> A_IWL<431> A_IWL<430> A_IWL<429> A_IWL<428> A_IWL<427> A_IWL<426> A_IWL<425> A_IWL<424> A_IWL<423> A_IWL<422> A_IWL<421> A_IWL<420> A_IWL<419> A_IWL<418> A_IWL<417> A_IWL<416> A_IWL<415> A_IWL<414> A_IWL<413> A_IWL<412> A_IWL<411> A_IWL<410> A_IWL<409> A_IWL<408> A_IWL<407> A_IWL<406> A_IWL<405> A_IWL<404> A_IWL<403> A_IWL<402> A_IWL<401> A_IWL<400> A_IWL<399> A_IWL<398> A_IWL<397> A_IWL<396> A_IWL<395> A_IWL<394> A_IWL<393> A_IWL<392> A_IWL<391> A_IWL<390> A_IWL<389> A_IWL<388> A_IWL<387> A_IWL<386> A_IWL<385> A_IWL<384> A_IWL<639> A_IWL<638> A_IWL<637> A_IWL<636> A_IWL<635> A_IWL<634> A_IWL<633> A_IWL<632> A_IWL<631> A_IWL<630> A_IWL<629> A_IWL<628> A_IWL<627> A_IWL<626> A_IWL<625> A_IWL<624> A_IWL<623> A_IWL<622> A_IWL<621> A_IWL<620> A_IWL<619> A_IWL<618> A_IWL<617> A_IWL<616> A_IWL<615> A_IWL<614> A_IWL<613> A_IWL<612> A_IWL<611> A_IWL<610> A_IWL<609> A_IWL<608> A_IWL<607> A_IWL<606> A_IWL<605> A_IWL<604> A_IWL<603> A_IWL<602> A_IWL<601> A_IWL<600> A_IWL<599> A_IWL<598> A_IWL<597> A_IWL<596> A_IWL<595> A_IWL<594> A_IWL<593> A_IWL<592> A_IWL<591> A_IWL<590> A_IWL<589> A_IWL<588> A_IWL<587> A_IWL<586> A_IWL<585> A_IWL<584> A_IWL<583> A_IWL<582> A_IWL<581> A_IWL<580> A_IWL<579> A_IWL<578> A_IWL<577> A_IWL<576> A_IWL<575> A_IWL<574> A_IWL<573> A_IWL<572> A_IWL<571> A_IWL<570> A_IWL<569> A_IWL<568> A_IWL<567> A_IWL<566> A_IWL<565> A_IWL<564> A_IWL<563> A_IWL<562> A_IWL<561> A_IWL<560> A_IWL<559> A_IWL<558> A_IWL<557> A_IWL<556> A_IWL<555> A_IWL<554> A_IWL<553> A_IWL<552> A_IWL<551> A_IWL<550> A_IWL<549> A_IWL<548> A_IWL<547> A_IWL<546> A_IWL<545> A_IWL<544> A_IWL<543> A_IWL<542> A_IWL<541> A_IWL<540> A_IWL<539> A_IWL<538> A_IWL<537> A_IWL<536> A_IWL<535> A_IWL<534> A_IWL<533> A_IWL<532> A_IWL<531> A_IWL<530> A_IWL<529> A_IWL<528> A_IWL<527> A_IWL<526> A_IWL<525> A_IWL<524> A_IWL<523> A_IWL<522> A_IWL<521> A_IWL<520> A_IWL<519> A_IWL<518> A_IWL<517> A_IWL<516> A_IWL<515> A_IWL<514> A_IWL<513> A_IWL<512> B_BLC<9> B_BLC<8> B_BLC_TOP<9> B_BLC_TOP<8> B_BLT<9> B_BLT<8> B_BLT_TOP<9> B_BLT_TOP<8> B_IWL<511> B_IWL<510> B_IWL<509> B_IWL<508> B_IWL<507> B_IWL<506> B_IWL<505> B_IWL<504> B_IWL<503> B_IWL<502> B_IWL<501> B_IWL<500> B_IWL<499> B_IWL<498> B_IWL<497> B_IWL<496> B_IWL<495> B_IWL<494> B_IWL<493> B_IWL<492> B_IWL<491> B_IWL<490> B_IWL<489> B_IWL<488> B_IWL<487> B_IWL<486> B_IWL<485> B_IWL<484> B_IWL<483> B_IWL<482> B_IWL<481> B_IWL<480> B_IWL<479> B_IWL<478> B_IWL<477> B_IWL<476> B_IWL<475> B_IWL<474> B_IWL<473> B_IWL<472> B_IWL<471> B_IWL<470> B_IWL<469> B_IWL<468> B_IWL<467> B_IWL<466> B_IWL<465> B_IWL<464> B_IWL<463> B_IWL<462> B_IWL<461> B_IWL<460> B_IWL<459> B_IWL<458> B_IWL<457> B_IWL<456> B_IWL<455> B_IWL<454> B_IWL<453> B_IWL<452> B_IWL<451> B_IWL<450> B_IWL<449> B_IWL<448> B_IWL<447> B_IWL<446> B_IWL<445> B_IWL<444> B_IWL<443> B_IWL<442> B_IWL<441> B_IWL<440> B_IWL<439> B_IWL<438> B_IWL<437> B_IWL<436> B_IWL<435> B_IWL<434> B_IWL<433> B_IWL<432> B_IWL<431> B_IWL<430> B_IWL<429> B_IWL<428> B_IWL<427> B_IWL<426> B_IWL<425> B_IWL<424> B_IWL<423> B_IWL<422> B_IWL<421> B_IWL<420> B_IWL<419> B_IWL<418> B_IWL<417> B_IWL<416> B_IWL<415> B_IWL<414> B_IWL<413> B_IWL<412> B_IWL<411> B_IWL<410> B_IWL<409> B_IWL<408> B_IWL<407> B_IWL<406> B_IWL<405> B_IWL<404> B_IWL<403> B_IWL<402> B_IWL<401> B_IWL<400> B_IWL<399> B_IWL<398> B_IWL<397> B_IWL<396> B_IWL<395> B_IWL<394> B_IWL<393> B_IWL<392> B_IWL<391> B_IWL<390> B_IWL<389> B_IWL<388> B_IWL<387> B_IWL<386> B_IWL<385> B_IWL<384> B_IWL<639> B_IWL<638> B_IWL<637> B_IWL<636> B_IWL<635> B_IWL<634> B_IWL<633> B_IWL<632> B_IWL<631> B_IWL<630> B_IWL<629> B_IWL<628> B_IWL<627> B_IWL<626> B_IWL<625> B_IWL<624> B_IWL<623> B_IWL<622> B_IWL<621> B_IWL<620> B_IWL<619> B_IWL<618> B_IWL<617> B_IWL<616> B_IWL<615> B_IWL<614> B_IWL<613> B_IWL<612> B_IWL<611> B_IWL<610> B_IWL<609> B_IWL<608> B_IWL<607> B_IWL<606> B_IWL<605> B_IWL<604> B_IWL<603> B_IWL<602> B_IWL<601> B_IWL<600> B_IWL<599> B_IWL<598> B_IWL<597> B_IWL<596> B_IWL<595> B_IWL<594> B_IWL<593> B_IWL<592> B_IWL<591> B_IWL<590> B_IWL<589> B_IWL<588> B_IWL<587> B_IWL<586> B_IWL<585> B_IWL<584> B_IWL<583> B_IWL<582> B_IWL<581> B_IWL<580> B_IWL<579> B_IWL<578> B_IWL<577> B_IWL<576> B_IWL<575> B_IWL<574> B_IWL<573> B_IWL<572> B_IWL<571> B_IWL<570> B_IWL<569> B_IWL<568> B_IWL<567> B_IWL<566> B_IWL<565> B_IWL<564> B_IWL<563> B_IWL<562> B_IWL<561> B_IWL<560> B_IWL<559> B_IWL<558> B_IWL<557> B_IWL<556> B_IWL<555> B_IWL<554> B_IWL<553> B_IWL<552> B_IWL<551> B_IWL<550> B_IWL<549> B_IWL<548> B_IWL<547> B_IWL<546> B_IWL<545> B_IWL<544> B_IWL<543> B_IWL<542> B_IWL<541> B_IWL<540> B_IWL<539> B_IWL<538> B_IWL<537> B_IWL<536> B_IWL<535> B_IWL<534> B_IWL<533> B_IWL<532> B_IWL<531> B_IWL<530> B_IWL<529> B_IWL<528> B_IWL<527> B_IWL<526> B_IWL<525> B_IWL<524> B_IWL<523> B_IWL<522> B_IWL<521> B_IWL<520> B_IWL<519> B_IWL<518> B_IWL<517> B_IWL<516> B_IWL<515> B_IWL<514> B_IWL<513> B_IWL<512> VDD_CORE VSS / RM_IHPSG13_512x8_c2_2P_COLUMN_pcell_0 +XCOL<3> A_BLC<7> A_BLC<6> A_BLC_TOP<7> A_BLC_TOP<6> A_BLT<7> A_BLT<6> A_BLT_TOP<7> A_BLT_TOP<6> A_IWL<383> A_IWL<382> A_IWL<381> A_IWL<380> A_IWL<379> A_IWL<378> A_IWL<377> A_IWL<376> A_IWL<375> A_IWL<374> A_IWL<373> A_IWL<372> A_IWL<371> A_IWL<370> A_IWL<369> A_IWL<368> A_IWL<367> A_IWL<366> A_IWL<365> A_IWL<364> A_IWL<363> A_IWL<362> A_IWL<361> A_IWL<360> A_IWL<359> A_IWL<358> A_IWL<357> A_IWL<356> A_IWL<355> A_IWL<354> A_IWL<353> A_IWL<352> A_IWL<351> A_IWL<350> A_IWL<349> A_IWL<348> A_IWL<347> A_IWL<346> A_IWL<345> A_IWL<344> A_IWL<343> A_IWL<342> A_IWL<341> A_IWL<340> A_IWL<339> A_IWL<338> A_IWL<337> A_IWL<336> A_IWL<335> A_IWL<334> A_IWL<333> A_IWL<332> A_IWL<331> A_IWL<330> A_IWL<329> A_IWL<328> A_IWL<327> A_IWL<326> A_IWL<325> A_IWL<324> A_IWL<323> A_IWL<322> A_IWL<321> A_IWL<320> A_IWL<319> A_IWL<318> A_IWL<317> A_IWL<316> A_IWL<315> A_IWL<314> A_IWL<313> A_IWL<312> A_IWL<311> A_IWL<310> A_IWL<309> A_IWL<308> A_IWL<307> A_IWL<306> A_IWL<305> A_IWL<304> A_IWL<303> A_IWL<302> A_IWL<301> A_IWL<300> A_IWL<299> A_IWL<298> A_IWL<297> A_IWL<296> A_IWL<295> A_IWL<294> A_IWL<293> A_IWL<292> A_IWL<291> A_IWL<290> A_IWL<289> A_IWL<288> A_IWL<287> A_IWL<286> A_IWL<285> A_IWL<284> A_IWL<283> A_IWL<282> A_IWL<281> A_IWL<280> A_IWL<279> A_IWL<278> A_IWL<277> A_IWL<276> A_IWL<275> A_IWL<274> A_IWL<273> A_IWL<272> A_IWL<271> A_IWL<270> A_IWL<269> A_IWL<268> A_IWL<267> A_IWL<266> A_IWL<265> A_IWL<264> A_IWL<263> A_IWL<262> A_IWL<261> A_IWL<260> A_IWL<259> A_IWL<258> A_IWL<257> A_IWL<256> A_IWL<511> A_IWL<510> A_IWL<509> A_IWL<508> A_IWL<507> A_IWL<506> A_IWL<505> A_IWL<504> A_IWL<503> A_IWL<502> A_IWL<501> A_IWL<500> A_IWL<499> A_IWL<498> A_IWL<497> A_IWL<496> A_IWL<495> A_IWL<494> A_IWL<493> A_IWL<492> A_IWL<491> A_IWL<490> A_IWL<489> A_IWL<488> A_IWL<487> A_IWL<486> A_IWL<485> A_IWL<484> A_IWL<483> A_IWL<482> A_IWL<481> A_IWL<480> A_IWL<479> A_IWL<478> A_IWL<477> A_IWL<476> A_IWL<475> A_IWL<474> A_IWL<473> A_IWL<472> A_IWL<471> A_IWL<470> A_IWL<469> A_IWL<468> A_IWL<467> A_IWL<466> A_IWL<465> A_IWL<464> A_IWL<463> A_IWL<462> A_IWL<461> A_IWL<460> A_IWL<459> A_IWL<458> A_IWL<457> A_IWL<456> A_IWL<455> A_IWL<454> A_IWL<453> A_IWL<452> A_IWL<451> A_IWL<450> A_IWL<449> A_IWL<448> A_IWL<447> A_IWL<446> A_IWL<445> A_IWL<444> A_IWL<443> A_IWL<442> A_IWL<441> A_IWL<440> A_IWL<439> A_IWL<438> A_IWL<437> A_IWL<436> A_IWL<435> A_IWL<434> A_IWL<433> A_IWL<432> A_IWL<431> A_IWL<430> A_IWL<429> A_IWL<428> A_IWL<427> A_IWL<426> A_IWL<425> A_IWL<424> A_IWL<423> A_IWL<422> A_IWL<421> A_IWL<420> A_IWL<419> A_IWL<418> A_IWL<417> A_IWL<416> A_IWL<415> A_IWL<414> A_IWL<413> A_IWL<412> A_IWL<411> A_IWL<410> A_IWL<409> A_IWL<408> A_IWL<407> A_IWL<406> A_IWL<405> A_IWL<404> A_IWL<403> A_IWL<402> A_IWL<401> A_IWL<400> A_IWL<399> A_IWL<398> A_IWL<397> A_IWL<396> A_IWL<395> A_IWL<394> A_IWL<393> A_IWL<392> A_IWL<391> A_IWL<390> A_IWL<389> A_IWL<388> A_IWL<387> A_IWL<386> A_IWL<385> A_IWL<384> B_BLC<7> B_BLC<6> B_BLC_TOP<7> B_BLC_TOP<6> B_BLT<7> B_BLT<6> B_BLT_TOP<7> B_BLT_TOP<6> B_IWL<383> B_IWL<382> B_IWL<381> B_IWL<380> B_IWL<379> B_IWL<378> B_IWL<377> B_IWL<376> B_IWL<375> B_IWL<374> B_IWL<373> B_IWL<372> B_IWL<371> B_IWL<370> B_IWL<369> B_IWL<368> B_IWL<367> B_IWL<366> B_IWL<365> B_IWL<364> B_IWL<363> B_IWL<362> B_IWL<361> B_IWL<360> B_IWL<359> B_IWL<358> B_IWL<357> B_IWL<356> B_IWL<355> B_IWL<354> B_IWL<353> B_IWL<352> B_IWL<351> B_IWL<350> B_IWL<349> B_IWL<348> B_IWL<347> B_IWL<346> B_IWL<345> B_IWL<344> B_IWL<343> B_IWL<342> B_IWL<341> B_IWL<340> B_IWL<339> B_IWL<338> B_IWL<337> B_IWL<336> B_IWL<335> B_IWL<334> B_IWL<333> B_IWL<332> B_IWL<331> B_IWL<330> B_IWL<329> B_IWL<328> B_IWL<327> B_IWL<326> B_IWL<325> B_IWL<324> B_IWL<323> B_IWL<322> B_IWL<321> B_IWL<320> B_IWL<319> B_IWL<318> B_IWL<317> B_IWL<316> B_IWL<315> B_IWL<314> B_IWL<313> B_IWL<312> B_IWL<311> B_IWL<310> B_IWL<309> B_IWL<308> B_IWL<307> B_IWL<306> B_IWL<305> B_IWL<304> B_IWL<303> B_IWL<302> B_IWL<301> B_IWL<300> B_IWL<299> B_IWL<298> B_IWL<297> B_IWL<296> B_IWL<295> B_IWL<294> B_IWL<293> B_IWL<292> B_IWL<291> B_IWL<290> B_IWL<289> B_IWL<288> B_IWL<287> B_IWL<286> B_IWL<285> B_IWL<284> B_IWL<283> B_IWL<282> B_IWL<281> B_IWL<280> B_IWL<279> B_IWL<278> B_IWL<277> B_IWL<276> B_IWL<275> B_IWL<274> B_IWL<273> B_IWL<272> B_IWL<271> B_IWL<270> B_IWL<269> B_IWL<268> B_IWL<267> B_IWL<266> B_IWL<265> B_IWL<264> B_IWL<263> B_IWL<262> B_IWL<261> B_IWL<260> B_IWL<259> B_IWL<258> B_IWL<257> B_IWL<256> B_IWL<511> B_IWL<510> B_IWL<509> B_IWL<508> B_IWL<507> B_IWL<506> B_IWL<505> B_IWL<504> B_IWL<503> B_IWL<502> B_IWL<501> B_IWL<500> B_IWL<499> B_IWL<498> B_IWL<497> B_IWL<496> B_IWL<495> B_IWL<494> B_IWL<493> B_IWL<492> B_IWL<491> B_IWL<490> B_IWL<489> B_IWL<488> B_IWL<487> B_IWL<486> B_IWL<485> B_IWL<484> B_IWL<483> B_IWL<482> B_IWL<481> B_IWL<480> B_IWL<479> B_IWL<478> B_IWL<477> B_IWL<476> B_IWL<475> B_IWL<474> B_IWL<473> B_IWL<472> B_IWL<471> B_IWL<470> B_IWL<469> B_IWL<468> B_IWL<467> B_IWL<466> B_IWL<465> B_IWL<464> B_IWL<463> B_IWL<462> B_IWL<461> B_IWL<460> B_IWL<459> B_IWL<458> B_IWL<457> B_IWL<456> B_IWL<455> B_IWL<454> B_IWL<453> B_IWL<452> B_IWL<451> B_IWL<450> B_IWL<449> B_IWL<448> B_IWL<447> B_IWL<446> B_IWL<445> B_IWL<444> B_IWL<443> B_IWL<442> B_IWL<441> B_IWL<440> B_IWL<439> B_IWL<438> B_IWL<437> B_IWL<436> B_IWL<435> B_IWL<434> B_IWL<433> B_IWL<432> B_IWL<431> B_IWL<430> B_IWL<429> B_IWL<428> B_IWL<427> B_IWL<426> B_IWL<425> B_IWL<424> B_IWL<423> B_IWL<422> B_IWL<421> B_IWL<420> B_IWL<419> B_IWL<418> B_IWL<417> B_IWL<416> B_IWL<415> B_IWL<414> B_IWL<413> B_IWL<412> B_IWL<411> B_IWL<410> B_IWL<409> B_IWL<408> B_IWL<407> B_IWL<406> B_IWL<405> B_IWL<404> B_IWL<403> B_IWL<402> B_IWL<401> B_IWL<400> B_IWL<399> B_IWL<398> B_IWL<397> B_IWL<396> B_IWL<395> B_IWL<394> B_IWL<393> B_IWL<392> B_IWL<391> B_IWL<390> B_IWL<389> B_IWL<388> B_IWL<387> B_IWL<386> B_IWL<385> B_IWL<384> VDD_CORE VSS / RM_IHPSG13_512x8_c2_2P_COLUMN_pcell_0 +XCOL<2> A_BLC<5> A_BLC<4> A_BLC_TOP<5> A_BLC_TOP<4> A_BLT<5> A_BLT<4> A_BLT_TOP<5> A_BLT_TOP<4> A_IWL<255> A_IWL<254> A_IWL<253> A_IWL<252> A_IWL<251> A_IWL<250> A_IWL<249> A_IWL<248> A_IWL<247> A_IWL<246> A_IWL<245> A_IWL<244> A_IWL<243> A_IWL<242> A_IWL<241> A_IWL<240> A_IWL<239> A_IWL<238> A_IWL<237> A_IWL<236> A_IWL<235> A_IWL<234> A_IWL<233> A_IWL<232> A_IWL<231> A_IWL<230> A_IWL<229> A_IWL<228> A_IWL<227> A_IWL<226> A_IWL<225> A_IWL<224> A_IWL<223> A_IWL<222> A_IWL<221> A_IWL<220> A_IWL<219> A_IWL<218> A_IWL<217> A_IWL<216> A_IWL<215> A_IWL<214> A_IWL<213> A_IWL<212> A_IWL<211> A_IWL<210> A_IWL<209> A_IWL<208> A_IWL<207> A_IWL<206> A_IWL<205> A_IWL<204> A_IWL<203> A_IWL<202> A_IWL<201> A_IWL<200> A_IWL<199> A_IWL<198> A_IWL<197> A_IWL<196> A_IWL<195> A_IWL<194> A_IWL<193> A_IWL<192> A_IWL<191> A_IWL<190> A_IWL<189> A_IWL<188> A_IWL<187> A_IWL<186> A_IWL<185> A_IWL<184> A_IWL<183> A_IWL<182> A_IWL<181> A_IWL<180> A_IWL<179> A_IWL<178> A_IWL<177> A_IWL<176> A_IWL<175> A_IWL<174> A_IWL<173> A_IWL<172> A_IWL<171> A_IWL<170> A_IWL<169> A_IWL<168> A_IWL<167> A_IWL<166> A_IWL<165> A_IWL<164> A_IWL<163> A_IWL<162> A_IWL<161> A_IWL<160> A_IWL<159> A_IWL<158> A_IWL<157> A_IWL<156> A_IWL<155> A_IWL<154> A_IWL<153> A_IWL<152> A_IWL<151> A_IWL<150> A_IWL<149> A_IWL<148> A_IWL<147> A_IWL<146> A_IWL<145> A_IWL<144> A_IWL<143> A_IWL<142> A_IWL<141> A_IWL<140> A_IWL<139> A_IWL<138> A_IWL<137> A_IWL<136> A_IWL<135> A_IWL<134> A_IWL<133> A_IWL<132> A_IWL<131> A_IWL<130> A_IWL<129> A_IWL<128> A_IWL<383> A_IWL<382> A_IWL<381> A_IWL<380> A_IWL<379> A_IWL<378> A_IWL<377> A_IWL<376> A_IWL<375> A_IWL<374> A_IWL<373> A_IWL<372> A_IWL<371> A_IWL<370> A_IWL<369> A_IWL<368> A_IWL<367> A_IWL<366> A_IWL<365> A_IWL<364> A_IWL<363> A_IWL<362> A_IWL<361> A_IWL<360> A_IWL<359> A_IWL<358> A_IWL<357> A_IWL<356> A_IWL<355> A_IWL<354> A_IWL<353> A_IWL<352> A_IWL<351> A_IWL<350> A_IWL<349> A_IWL<348> A_IWL<347> A_IWL<346> A_IWL<345> A_IWL<344> A_IWL<343> A_IWL<342> A_IWL<341> A_IWL<340> A_IWL<339> A_IWL<338> A_IWL<337> A_IWL<336> A_IWL<335> A_IWL<334> A_IWL<333> A_IWL<332> A_IWL<331> A_IWL<330> A_IWL<329> A_IWL<328> A_IWL<327> A_IWL<326> A_IWL<325> A_IWL<324> A_IWL<323> A_IWL<322> A_IWL<321> A_IWL<320> A_IWL<319> A_IWL<318> A_IWL<317> A_IWL<316> A_IWL<315> A_IWL<314> A_IWL<313> A_IWL<312> A_IWL<311> A_IWL<310> A_IWL<309> A_IWL<308> A_IWL<307> A_IWL<306> A_IWL<305> A_IWL<304> A_IWL<303> A_IWL<302> A_IWL<301> A_IWL<300> A_IWL<299> A_IWL<298> A_IWL<297> A_IWL<296> A_IWL<295> A_IWL<294> A_IWL<293> A_IWL<292> A_IWL<291> A_IWL<290> A_IWL<289> A_IWL<288> A_IWL<287> A_IWL<286> A_IWL<285> A_IWL<284> A_IWL<283> A_IWL<282> A_IWL<281> A_IWL<280> A_IWL<279> A_IWL<278> A_IWL<277> A_IWL<276> A_IWL<275> A_IWL<274> A_IWL<273> A_IWL<272> A_IWL<271> A_IWL<270> A_IWL<269> A_IWL<268> A_IWL<267> A_IWL<266> A_IWL<265> A_IWL<264> A_IWL<263> A_IWL<262> A_IWL<261> A_IWL<260> A_IWL<259> A_IWL<258> A_IWL<257> A_IWL<256> B_BLC<5> B_BLC<4> B_BLC_TOP<5> B_BLC_TOP<4> B_BLT<5> B_BLT<4> B_BLT_TOP<5> B_BLT_TOP<4> B_IWL<255> B_IWL<254> B_IWL<253> B_IWL<252> B_IWL<251> B_IWL<250> B_IWL<249> B_IWL<248> B_IWL<247> B_IWL<246> B_IWL<245> B_IWL<244> B_IWL<243> B_IWL<242> B_IWL<241> B_IWL<240> B_IWL<239> B_IWL<238> B_IWL<237> B_IWL<236> B_IWL<235> B_IWL<234> B_IWL<233> B_IWL<232> B_IWL<231> B_IWL<230> B_IWL<229> B_IWL<228> B_IWL<227> B_IWL<226> B_IWL<225> B_IWL<224> B_IWL<223> B_IWL<222> B_IWL<221> B_IWL<220> B_IWL<219> B_IWL<218> B_IWL<217> B_IWL<216> B_IWL<215> B_IWL<214> B_IWL<213> B_IWL<212> B_IWL<211> B_IWL<210> B_IWL<209> B_IWL<208> B_IWL<207> B_IWL<206> B_IWL<205> B_IWL<204> B_IWL<203> B_IWL<202> B_IWL<201> B_IWL<200> B_IWL<199> B_IWL<198> B_IWL<197> B_IWL<196> B_IWL<195> B_IWL<194> B_IWL<193> B_IWL<192> B_IWL<191> B_IWL<190> B_IWL<189> B_IWL<188> B_IWL<187> B_IWL<186> B_IWL<185> B_IWL<184> B_IWL<183> B_IWL<182> B_IWL<181> B_IWL<180> B_IWL<179> B_IWL<178> B_IWL<177> B_IWL<176> B_IWL<175> B_IWL<174> B_IWL<173> B_IWL<172> B_IWL<171> B_IWL<170> B_IWL<169> B_IWL<168> B_IWL<167> B_IWL<166> B_IWL<165> B_IWL<164> B_IWL<163> B_IWL<162> B_IWL<161> B_IWL<160> B_IWL<159> B_IWL<158> B_IWL<157> B_IWL<156> B_IWL<155> B_IWL<154> B_IWL<153> B_IWL<152> B_IWL<151> B_IWL<150> B_IWL<149> B_IWL<148> B_IWL<147> B_IWL<146> B_IWL<145> B_IWL<144> B_IWL<143> B_IWL<142> B_IWL<141> B_IWL<140> B_IWL<139> B_IWL<138> B_IWL<137> B_IWL<136> B_IWL<135> B_IWL<134> B_IWL<133> B_IWL<132> B_IWL<131> B_IWL<130> B_IWL<129> B_IWL<128> B_IWL<383> B_IWL<382> B_IWL<381> B_IWL<380> B_IWL<379> B_IWL<378> B_IWL<377> B_IWL<376> B_IWL<375> B_IWL<374> B_IWL<373> B_IWL<372> B_IWL<371> B_IWL<370> B_IWL<369> B_IWL<368> B_IWL<367> B_IWL<366> B_IWL<365> B_IWL<364> B_IWL<363> B_IWL<362> B_IWL<361> B_IWL<360> B_IWL<359> B_IWL<358> B_IWL<357> B_IWL<356> B_IWL<355> B_IWL<354> B_IWL<353> B_IWL<352> B_IWL<351> B_IWL<350> B_IWL<349> B_IWL<348> B_IWL<347> B_IWL<346> B_IWL<345> B_IWL<344> B_IWL<343> B_IWL<342> B_IWL<341> B_IWL<340> B_IWL<339> B_IWL<338> B_IWL<337> B_IWL<336> B_IWL<335> B_IWL<334> B_IWL<333> B_IWL<332> B_IWL<331> B_IWL<330> B_IWL<329> B_IWL<328> B_IWL<327> B_IWL<326> B_IWL<325> B_IWL<324> B_IWL<323> B_IWL<322> B_IWL<321> B_IWL<320> B_IWL<319> B_IWL<318> B_IWL<317> B_IWL<316> B_IWL<315> B_IWL<314> B_IWL<313> B_IWL<312> B_IWL<311> B_IWL<310> B_IWL<309> B_IWL<308> B_IWL<307> B_IWL<306> B_IWL<305> B_IWL<304> B_IWL<303> B_IWL<302> B_IWL<301> B_IWL<300> B_IWL<299> B_IWL<298> B_IWL<297> B_IWL<296> B_IWL<295> B_IWL<294> B_IWL<293> B_IWL<292> B_IWL<291> B_IWL<290> B_IWL<289> B_IWL<288> B_IWL<287> B_IWL<286> B_IWL<285> B_IWL<284> B_IWL<283> B_IWL<282> B_IWL<281> B_IWL<280> B_IWL<279> B_IWL<278> B_IWL<277> B_IWL<276> B_IWL<275> B_IWL<274> B_IWL<273> B_IWL<272> B_IWL<271> B_IWL<270> B_IWL<269> B_IWL<268> B_IWL<267> B_IWL<266> B_IWL<265> B_IWL<264> B_IWL<263> B_IWL<262> B_IWL<261> B_IWL<260> B_IWL<259> B_IWL<258> B_IWL<257> B_IWL<256> VDD_CORE VSS / RM_IHPSG13_512x8_c2_2P_COLUMN_pcell_0 +XCOL<1> A_BLC<3> A_BLC<2> A_BLC_TOP<3> A_BLC_TOP<2> A_BLT<3> A_BLT<2> A_BLT_TOP<3> A_BLT_TOP<2> A_IWL<127> A_IWL<126> A_IWL<125> A_IWL<124> A_IWL<123> A_IWL<122> A_IWL<121> A_IWL<120> A_IWL<119> A_IWL<118> A_IWL<117> A_IWL<116> A_IWL<115> A_IWL<114> A_IWL<113> A_IWL<112> A_IWL<111> A_IWL<110> A_IWL<109> A_IWL<108> A_IWL<107> A_IWL<106> A_IWL<105> A_IWL<104> A_IWL<103> A_IWL<102> A_IWL<101> A_IWL<100> A_IWL<99> A_IWL<98> A_IWL<97> A_IWL<96> A_IWL<95> A_IWL<94> A_IWL<93> A_IWL<92> A_IWL<91> A_IWL<90> A_IWL<89> A_IWL<88> A_IWL<87> A_IWL<86> A_IWL<85> A_IWL<84> A_IWL<83> A_IWL<82> A_IWL<81> A_IWL<80> A_IWL<79> A_IWL<78> A_IWL<77> A_IWL<76> A_IWL<75> A_IWL<74> A_IWL<73> A_IWL<72> A_IWL<71> A_IWL<70> A_IWL<69> A_IWL<68> A_IWL<67> A_IWL<66> A_IWL<65> A_IWL<64> A_IWL<63> A_IWL<62> A_IWL<61> A_IWL<60> A_IWL<59> A_IWL<58> A_IWL<57> A_IWL<56> A_IWL<55> A_IWL<54> A_IWL<53> A_IWL<52> A_IWL<51> A_IWL<50> A_IWL<49> A_IWL<48> A_IWL<47> A_IWL<46> A_IWL<45> A_IWL<44> A_IWL<43> A_IWL<42> A_IWL<41> A_IWL<40> A_IWL<39> A_IWL<38> A_IWL<37> A_IWL<36> A_IWL<35> A_IWL<34> A_IWL<33> A_IWL<32> A_IWL<31> A_IWL<30> A_IWL<29> A_IWL<28> A_IWL<27> A_IWL<26> A_IWL<25> A_IWL<24> A_IWL<23> A_IWL<22> A_IWL<21> A_IWL<20> A_IWL<19> A_IWL<18> A_IWL<17> A_IWL<16> A_IWL<15> A_IWL<14> A_IWL<13> A_IWL<12> A_IWL<11> A_IWL<10> A_IWL<9> A_IWL<8> A_IWL<7> A_IWL<6> A_IWL<5> A_IWL<4> A_IWL<3> A_IWL<2> A_IWL<1> A_IWL<0> A_IWL<255> A_IWL<254> A_IWL<253> A_IWL<252> A_IWL<251> A_IWL<250> A_IWL<249> A_IWL<248> A_IWL<247> A_IWL<246> A_IWL<245> A_IWL<244> A_IWL<243> A_IWL<242> A_IWL<241> A_IWL<240> A_IWL<239> A_IWL<238> A_IWL<237> A_IWL<236> A_IWL<235> A_IWL<234> A_IWL<233> A_IWL<232> A_IWL<231> A_IWL<230> A_IWL<229> A_IWL<228> A_IWL<227> A_IWL<226> A_IWL<225> A_IWL<224> A_IWL<223> A_IWL<222> A_IWL<221> A_IWL<220> A_IWL<219> A_IWL<218> A_IWL<217> A_IWL<216> A_IWL<215> A_IWL<214> A_IWL<213> A_IWL<212> A_IWL<211> A_IWL<210> A_IWL<209> A_IWL<208> A_IWL<207> A_IWL<206> A_IWL<205> A_IWL<204> A_IWL<203> A_IWL<202> A_IWL<201> A_IWL<200> A_IWL<199> A_IWL<198> A_IWL<197> A_IWL<196> A_IWL<195> A_IWL<194> A_IWL<193> A_IWL<192> A_IWL<191> A_IWL<190> A_IWL<189> A_IWL<188> A_IWL<187> A_IWL<186> A_IWL<185> A_IWL<184> A_IWL<183> A_IWL<182> A_IWL<181> A_IWL<180> A_IWL<179> A_IWL<178> A_IWL<177> A_IWL<176> A_IWL<175> A_IWL<174> A_IWL<173> A_IWL<172> A_IWL<171> A_IWL<170> A_IWL<169> A_IWL<168> A_IWL<167> A_IWL<166> A_IWL<165> A_IWL<164> A_IWL<163> A_IWL<162> A_IWL<161> A_IWL<160> A_IWL<159> A_IWL<158> A_IWL<157> A_IWL<156> A_IWL<155> A_IWL<154> A_IWL<153> A_IWL<152> A_IWL<151> A_IWL<150> A_IWL<149> A_IWL<148> A_IWL<147> A_IWL<146> A_IWL<145> A_IWL<144> A_IWL<143> A_IWL<142> A_IWL<141> A_IWL<140> A_IWL<139> A_IWL<138> A_IWL<137> A_IWL<136> A_IWL<135> A_IWL<134> A_IWL<133> A_IWL<132> A_IWL<131> A_IWL<130> A_IWL<129> A_IWL<128> B_BLC<3> B_BLC<2> B_BLC_TOP<3> B_BLC_TOP<2> B_BLT<3> B_BLT<2> B_BLT_TOP<3> B_BLT_TOP<2> B_IWL<127> B_IWL<126> B_IWL<125> B_IWL<124> B_IWL<123> B_IWL<122> B_IWL<121> B_IWL<120> B_IWL<119> B_IWL<118> B_IWL<117> B_IWL<116> B_IWL<115> B_IWL<114> B_IWL<113> B_IWL<112> B_IWL<111> B_IWL<110> B_IWL<109> B_IWL<108> B_IWL<107> B_IWL<106> B_IWL<105> B_IWL<104> B_IWL<103> B_IWL<102> B_IWL<101> B_IWL<100> B_IWL<99> B_IWL<98> B_IWL<97> B_IWL<96> B_IWL<95> B_IWL<94> B_IWL<93> B_IWL<92> B_IWL<91> B_IWL<90> B_IWL<89> B_IWL<88> B_IWL<87> B_IWL<86> B_IWL<85> B_IWL<84> B_IWL<83> B_IWL<82> B_IWL<81> B_IWL<80> B_IWL<79> B_IWL<78> B_IWL<77> B_IWL<76> B_IWL<75> B_IWL<74> B_IWL<73> B_IWL<72> B_IWL<71> B_IWL<70> B_IWL<69> B_IWL<68> B_IWL<67> B_IWL<66> B_IWL<65> B_IWL<64> B_IWL<63> B_IWL<62> B_IWL<61> B_IWL<60> B_IWL<59> B_IWL<58> B_IWL<57> B_IWL<56> B_IWL<55> B_IWL<54> B_IWL<53> B_IWL<52> B_IWL<51> B_IWL<50> B_IWL<49> B_IWL<48> B_IWL<47> B_IWL<46> B_IWL<45> B_IWL<44> B_IWL<43> B_IWL<42> B_IWL<41> B_IWL<40> B_IWL<39> B_IWL<38> B_IWL<37> B_IWL<36> B_IWL<35> B_IWL<34> B_IWL<33> B_IWL<32> B_IWL<31> B_IWL<30> B_IWL<29> B_IWL<28> B_IWL<27> B_IWL<26> B_IWL<25> B_IWL<24> B_IWL<23> B_IWL<22> B_IWL<21> B_IWL<20> B_IWL<19> B_IWL<18> B_IWL<17> B_IWL<16> B_IWL<15> B_IWL<14> B_IWL<13> B_IWL<12> B_IWL<11> B_IWL<10> B_IWL<9> B_IWL<8> B_IWL<7> B_IWL<6> B_IWL<5> B_IWL<4> B_IWL<3> B_IWL<2> B_IWL<1> B_IWL<0> B_IWL<255> B_IWL<254> B_IWL<253> B_IWL<252> B_IWL<251> B_IWL<250> B_IWL<249> B_IWL<248> B_IWL<247> B_IWL<246> B_IWL<245> B_IWL<244> B_IWL<243> B_IWL<242> B_IWL<241> B_IWL<240> B_IWL<239> B_IWL<238> B_IWL<237> B_IWL<236> B_IWL<235> B_IWL<234> B_IWL<233> B_IWL<232> B_IWL<231> B_IWL<230> B_IWL<229> B_IWL<228> B_IWL<227> B_IWL<226> B_IWL<225> B_IWL<224> B_IWL<223> B_IWL<222> B_IWL<221> B_IWL<220> B_IWL<219> B_IWL<218> B_IWL<217> B_IWL<216> B_IWL<215> B_IWL<214> B_IWL<213> B_IWL<212> B_IWL<211> B_IWL<210> B_IWL<209> B_IWL<208> B_IWL<207> B_IWL<206> B_IWL<205> B_IWL<204> B_IWL<203> B_IWL<202> B_IWL<201> B_IWL<200> B_IWL<199> B_IWL<198> B_IWL<197> B_IWL<196> B_IWL<195> B_IWL<194> B_IWL<193> B_IWL<192> B_IWL<191> B_IWL<190> B_IWL<189> B_IWL<188> B_IWL<187> B_IWL<186> B_IWL<185> B_IWL<184> B_IWL<183> B_IWL<182> B_IWL<181> B_IWL<180> B_IWL<179> B_IWL<178> B_IWL<177> B_IWL<176> B_IWL<175> B_IWL<174> B_IWL<173> B_IWL<172> B_IWL<171> B_IWL<170> B_IWL<169> B_IWL<168> B_IWL<167> B_IWL<166> B_IWL<165> B_IWL<164> B_IWL<163> B_IWL<162> B_IWL<161> B_IWL<160> B_IWL<159> B_IWL<158> B_IWL<157> B_IWL<156> B_IWL<155> B_IWL<154> B_IWL<153> B_IWL<152> B_IWL<151> B_IWL<150> B_IWL<149> B_IWL<148> B_IWL<147> B_IWL<146> B_IWL<145> B_IWL<144> B_IWL<143> B_IWL<142> B_IWL<141> B_IWL<140> B_IWL<139> B_IWL<138> B_IWL<137> B_IWL<136> B_IWL<135> B_IWL<134> B_IWL<133> B_IWL<132> B_IWL<131> B_IWL<130> B_IWL<129> B_IWL<128> VDD_CORE VSS / RM_IHPSG13_512x8_c2_2P_COLUMN_pcell_0 +XCOL<0> A_BLC<1> A_BLC<0> A_BLC_TOP<1> A_BLC_TOP<0> A_BLT<1> A_BLT<0> A_BLT_TOP<1> A_BLT_TOP<0> A_WL<127> A_WL<126> A_WL<125> A_WL<124> A_WL<123> A_WL<122> A_WL<121> A_WL<120> A_WL<119> A_WL<118> A_WL<117> A_WL<116> A_WL<115> A_WL<114> A_WL<113> A_WL<112> A_WL<111> A_WL<110> A_WL<109> A_WL<108> A_WL<107> A_WL<106> A_WL<105> A_WL<104> A_WL<103> A_WL<102> A_WL<101> A_WL<100> A_WL<99> A_WL<98> A_WL<97> A_WL<96> A_WL<95> A_WL<94> A_WL<93> A_WL<92> A_WL<91> A_WL<90> A_WL<89> A_WL<88> A_WL<87> A_WL<86> A_WL<85> A_WL<84> A_WL<83> A_WL<82> A_WL<81> A_WL<80> A_WL<79> A_WL<78> A_WL<77> A_WL<76> A_WL<75> A_WL<74> A_WL<73> A_WL<72> A_WL<71> A_WL<70> A_WL<69> A_WL<68> A_WL<67> A_WL<66> A_WL<65> A_WL<64> A_WL<63> A_WL<62> A_WL<61> A_WL<60> A_WL<59> A_WL<58> A_WL<57> A_WL<56> A_WL<55> A_WL<54> A_WL<53> A_WL<52> A_WL<51> A_WL<50> A_WL<49> A_WL<48> A_WL<47> A_WL<46> A_WL<45> A_WL<44> A_WL<43> A_WL<42> A_WL<41> A_WL<40> A_WL<39> A_WL<38> A_WL<37> A_WL<36> A_WL<35> A_WL<34> A_WL<33> A_WL<32> A_WL<31> A_WL<30> A_WL<29> A_WL<28> A_WL<27> A_WL<26> A_WL<25> A_WL<24> A_WL<23> A_WL<22> A_WL<21> A_WL<20> A_WL<19> A_WL<18> A_WL<17> A_WL<16> A_WL<15> A_WL<14> A_WL<13> A_WL<12> A_WL<11> A_WL<10> A_WL<9> A_WL<8> A_WL<7> A_WL<6> A_WL<5> A_WL<4> A_WL<3> A_WL<2> A_WL<1> A_WL<0> A_IWL<127> A_IWL<126> A_IWL<125> A_IWL<124> A_IWL<123> A_IWL<122> A_IWL<121> A_IWL<120> A_IWL<119> A_IWL<118> A_IWL<117> A_IWL<116> A_IWL<115> A_IWL<114> A_IWL<113> A_IWL<112> A_IWL<111> A_IWL<110> A_IWL<109> A_IWL<108> A_IWL<107> A_IWL<106> A_IWL<105> A_IWL<104> A_IWL<103> A_IWL<102> A_IWL<101> A_IWL<100> A_IWL<99> A_IWL<98> A_IWL<97> A_IWL<96> A_IWL<95> A_IWL<94> A_IWL<93> A_IWL<92> A_IWL<91> A_IWL<90> A_IWL<89> A_IWL<88> A_IWL<87> A_IWL<86> A_IWL<85> A_IWL<84> A_IWL<83> A_IWL<82> A_IWL<81> A_IWL<80> A_IWL<79> A_IWL<78> A_IWL<77> A_IWL<76> A_IWL<75> A_IWL<74> A_IWL<73> A_IWL<72> A_IWL<71> A_IWL<70> A_IWL<69> A_IWL<68> A_IWL<67> A_IWL<66> A_IWL<65> A_IWL<64> A_IWL<63> A_IWL<62> A_IWL<61> A_IWL<60> A_IWL<59> A_IWL<58> A_IWL<57> A_IWL<56> A_IWL<55> A_IWL<54> A_IWL<53> A_IWL<52> A_IWL<51> A_IWL<50> A_IWL<49> A_IWL<48> A_IWL<47> A_IWL<46> A_IWL<45> A_IWL<44> A_IWL<43> A_IWL<42> A_IWL<41> A_IWL<40> A_IWL<39> A_IWL<38> A_IWL<37> A_IWL<36> A_IWL<35> A_IWL<34> A_IWL<33> A_IWL<32> A_IWL<31> A_IWL<30> A_IWL<29> A_IWL<28> A_IWL<27> A_IWL<26> A_IWL<25> A_IWL<24> A_IWL<23> A_IWL<22> A_IWL<21> A_IWL<20> A_IWL<19> A_IWL<18> A_IWL<17> A_IWL<16> A_IWL<15> A_IWL<14> A_IWL<13> A_IWL<12> A_IWL<11> A_IWL<10> A_IWL<9> A_IWL<8> A_IWL<7> A_IWL<6> A_IWL<5> A_IWL<4> A_IWL<3> A_IWL<2> A_IWL<1> A_IWL<0> B_BLC<1> B_BLC<0> B_BLC_TOP<1> B_BLC_TOP<0> B_BLT<1> B_BLT<0> B_BLT_TOP<1> B_BLT_TOP<0> B_WL<127> B_WL<126> B_WL<125> B_WL<124> B_WL<123> B_WL<122> B_WL<121> B_WL<120> B_WL<119> B_WL<118> B_WL<117> B_WL<116> B_WL<115> B_WL<114> B_WL<113> B_WL<112> B_WL<111> B_WL<110> B_WL<109> B_WL<108> B_WL<107> B_WL<106> B_WL<105> B_WL<104> B_WL<103> B_WL<102> B_WL<101> B_WL<100> B_WL<99> B_WL<98> B_WL<97> B_WL<96> B_WL<95> B_WL<94> B_WL<93> B_WL<92> B_WL<91> B_WL<90> B_WL<89> B_WL<88> B_WL<87> B_WL<86> B_WL<85> B_WL<84> B_WL<83> B_WL<82> B_WL<81> B_WL<80> B_WL<79> B_WL<78> B_WL<77> B_WL<76> B_WL<75> B_WL<74> B_WL<73> B_WL<72> B_WL<71> B_WL<70> B_WL<69> B_WL<68> B_WL<67> B_WL<66> B_WL<65> B_WL<64> B_WL<63> B_WL<62> B_WL<61> B_WL<60> B_WL<59> B_WL<58> B_WL<57> B_WL<56> B_WL<55> B_WL<54> B_WL<53> B_WL<52> B_WL<51> B_WL<50> B_WL<49> B_WL<48> B_WL<47> B_WL<46> B_WL<45> B_WL<44> B_WL<43> B_WL<42> B_WL<41> B_WL<40> B_WL<39> B_WL<38> B_WL<37> B_WL<36> B_WL<35> B_WL<34> B_WL<33> B_WL<32> B_WL<31> B_WL<30> B_WL<29> B_WL<28> B_WL<27> B_WL<26> B_WL<25> B_WL<24> B_WL<23> B_WL<22> B_WL<21> B_WL<20> B_WL<19> B_WL<18> B_WL<17> B_WL<16> B_WL<15> B_WL<14> B_WL<13> B_WL<12> B_WL<11> B_WL<10> B_WL<9> B_WL<8> B_WL<7> B_WL<6> B_WL<5> B_WL<4> B_WL<3> B_WL<2> B_WL<1> B_WL<0> B_IWL<127> B_IWL<126> B_IWL<125> B_IWL<124> B_IWL<123> B_IWL<122> B_IWL<121> B_IWL<120> B_IWL<119> B_IWL<118> B_IWL<117> B_IWL<116> B_IWL<115> B_IWL<114> B_IWL<113> B_IWL<112> B_IWL<111> B_IWL<110> B_IWL<109> B_IWL<108> B_IWL<107> B_IWL<106> B_IWL<105> B_IWL<104> B_IWL<103> B_IWL<102> B_IWL<101> B_IWL<100> B_IWL<99> B_IWL<98> B_IWL<97> B_IWL<96> B_IWL<95> B_IWL<94> B_IWL<93> B_IWL<92> B_IWL<91> B_IWL<90> B_IWL<89> B_IWL<88> B_IWL<87> B_IWL<86> B_IWL<85> B_IWL<84> B_IWL<83> B_IWL<82> B_IWL<81> B_IWL<80> B_IWL<79> B_IWL<78> B_IWL<77> B_IWL<76> B_IWL<75> B_IWL<74> B_IWL<73> B_IWL<72> B_IWL<71> B_IWL<70> B_IWL<69> B_IWL<68> B_IWL<67> B_IWL<66> B_IWL<65> B_IWL<64> B_IWL<63> B_IWL<62> B_IWL<61> B_IWL<60> B_IWL<59> B_IWL<58> B_IWL<57> B_IWL<56> B_IWL<55> B_IWL<54> B_IWL<53> B_IWL<52> B_IWL<51> B_IWL<50> B_IWL<49> B_IWL<48> B_IWL<47> B_IWL<46> B_IWL<45> B_IWL<44> B_IWL<43> B_IWL<42> B_IWL<41> B_IWL<40> B_IWL<39> B_IWL<38> B_IWL<37> B_IWL<36> B_IWL<35> B_IWL<34> B_IWL<33> B_IWL<32> B_IWL<31> B_IWL<30> B_IWL<29> B_IWL<28> B_IWL<27> B_IWL<26> B_IWL<25> B_IWL<24> B_IWL<23> B_IWL<22> B_IWL<21> B_IWL<20> B_IWL<19> B_IWL<18> B_IWL<17> B_IWL<16> B_IWL<15> B_IWL<14> B_IWL<13> B_IWL<12> B_IWL<11> B_IWL<10> B_IWL<9> B_IWL<8> B_IWL<7> B_IWL<6> B_IWL<5> B_IWL<4> B_IWL<3> B_IWL<2> B_IWL<1> B_IWL<0> VDD_CORE VSS / RM_IHPSG13_512x8_c2_2P_COLUMN_pcell_0 +.ENDS + + + + +.SUBCKT RM_IHPSG13_512x8_c2_2P_DLY_pcell_2 A Z VDD VSS + XIDL<2> D<9> Z VDD VSS / RSC_IHPSG13_CDLYX1 + XIDL<1> D<8> D<9> VDD VSS / RSC_IHPSG13_CDLYX1 + XIDM<8> D<7> D<8> VDD VSS / RSC_IHPSG13_CDLYX1_DUMMY + XIDM<7> D<6> D<7> VDD VSS / RSC_IHPSG13_CDLYX1_DUMMY + XIDM<6> D<5> D<6> VDD VSS / RSC_IHPSG13_CDLYX1_DUMMY + XIDM<5> D<4> D<5> VDD VSS / RSC_IHPSG13_CDLYX1_DUMMY + XIDM<4> D<3> D<4> VDD VSS / RSC_IHPSG13_CDLYX1_DUMMY + XIDM<3> D<2> D<3> VDD VSS / RSC_IHPSG13_CDLYX1_DUMMY + XIDM<2> D<1> D<2> VDD VSS / RSC_IHPSG13_CDLYX1_DUMMY + XIDM<1> A D<1> VDD VSS / RSC_IHPSG13_CDLYX1_DUMMY +.ENDS + + +.SUBCKT RM_IHPSG13_512x8_c2_2P_DLY_pcell_3 A Z VDD VSS + XIDL<2> D<9> Z VDD VSS / RSC_IHPSG13_CDLYX1 + XIDL<1> D<8> D<9> VDD VSS / RSC_IHPSG13_CDLYX1 + XIDM<8> D<7> D<8> VDD VSS / RSC_IHPSG13_CDLYX1_DUMMY + XIDM<7> D<6> D<7> VDD VSS / RSC_IHPSG13_CDLYX1_DUMMY + XIDM<6> D<5> D<6> VDD VSS / RSC_IHPSG13_CDLYX1_DUMMY + XIDM<5> D<4> D<5> VDD VSS / RSC_IHPSG13_CDLYX1_DUMMY + XIDM<4> D<3> D<4> VDD VSS / RSC_IHPSG13_CDLYX1_DUMMY + XIDM<3> D<2> D<3> VDD VSS / RSC_IHPSG13_CDLYX1_DUMMY + XIDM<2> D<1> D<2> VDD VSS / RSC_IHPSG13_CDLYX1_DUMMY + XIDM<1> A D<1> VDD VSS / RSC_IHPSG13_CDLYX1_DUMMY +.ENDS + + + +.SUBCKT RM_IHPSG13_2P_512x8_c2_bm_bist A_ADDR<8> A_ADDR<7> A_ADDR<6> A_ADDR<5> A_ADDR<4> A_ADDR<3> A_ADDR<2> A_ADDR<1> A_ADDR<0> A_BIST_ADDR<8> A_BIST_ADDR<7> A_BIST_ADDR<6> A_BIST_ADDR<5> A_BIST_ADDR<4> A_BIST_ADDR<3> A_BIST_ADDR<2> A_BIST_ADDR<1> A_BIST_ADDR<0> A_BIST_BM<7> A_BIST_BM<6> A_BIST_BM<5> A_BIST_BM<4> A_BIST_BM<3> A_BIST_BM<2> A_BIST_BM<1> A_BIST_BM<0> A_BIST_CLK A_BIST_DIN<7> A_BIST_DIN<6> A_BIST_DIN<5> A_BIST_DIN<4> A_BIST_DIN<3> A_BIST_DIN<2> A_BIST_DIN<1> A_BIST_DIN<0> A_BIST_EN A_BIST_MEN A_BIST_REN A_BIST_WEN A_BM<7> A_BM<6> A_BM<5> A_BM<4> A_BM<3> A_BM<2> A_BM<1> A_BM<0> A_CLK A_DIN<7> A_DIN<6> A_DIN<5> A_DIN<4> A_DIN<3> A_DIN<2> A_DIN<1> A_DIN<0> A_DLY A_DOUT<7> A_DOUT<6> A_DOUT<5> A_DOUT<4> A_DOUT<3> A_DOUT<2> A_DOUT<1> A_DOUT<0> A_MEN A_REN A_WEN B_ADDR<8> B_ADDR<7> B_ADDR<6> B_ADDR<5> B_ADDR<4> B_ADDR<3> B_ADDR<2> B_ADDR<1> B_ADDR<0> B_BIST_ADDR<8> B_BIST_ADDR<7> B_BIST_ADDR<6> B_BIST_ADDR<5> B_BIST_ADDR<4> B_BIST_ADDR<3> B_BIST_ADDR<2> B_BIST_ADDR<1> B_BIST_ADDR<0> B_BIST_BM<7> B_BIST_BM<6> B_BIST_BM<5> B_BIST_BM<4> B_BIST_BM<3> B_BIST_BM<2> B_BIST_BM<1> B_BIST_BM<0> B_BIST_CLK B_BIST_DIN<7> B_BIST_DIN<6> B_BIST_DIN<5> B_BIST_DIN<4> B_BIST_DIN<3> B_BIST_DIN<2> B_BIST_DIN<1> B_BIST_DIN<0> B_BIST_EN B_BIST_MEN B_BIST_REN B_BIST_WEN B_BM<7> B_BM<6> B_BM<5> B_BM<4> B_BM<3> B_BM<2> B_BM<1> B_BM<0> B_CLK B_DIN<7> B_DIN<6> B_DIN<5> B_DIN<4> B_DIN<3> B_DIN<2> B_DIN<1> B_DIN<0> B_DLY B_DOUT<7> B_DOUT<6> B_DOUT<5> B_DOUT<4> B_DOUT<3> B_DOUT<2> B_DOUT<1> B_DOUT<0> B_MEN B_REN B_WEN VDD! VDDARRAY! VSS! + + +XRAM<1> a_blc_r<15> a_blc_r<14> a_blc_r<13> a_blc_r<12> a_blc_r<11> a_blc_r<10> a_blc_r<9> a_blc_r<8> a_blc_r<7> a_blc_r<6> a_blc_r<5> a_blc_r<4> a_blc_r<3> a_blc_r<2> a_blc_r<1> a_blc_r<0> a_blt_r<15> a_blt_r<14> a_blt_r<13> a_blt_r<12> a_blt_r<11> a_blt_r<10> a_blt_r<9> a_blt_r<8> a_blt_r<7> a_blt_r<6> a_blt_r<5> a_blt_r<4> a_blt_r<3> a_blt_r<2> a_blt_r<1> a_blt_r<0> a_wl_r<127> a_wl_r<126> a_wl_r<125> a_wl_r<124> a_wl_r<123> a_wl_r<122> a_wl_r<121> a_wl_r<120> a_wl_r<119> a_wl_r<118> a_wl_r<117> a_wl_r<116> a_wl_r<115> a_wl_r<114> a_wl_r<113> a_wl_r<112> a_wl_r<111> a_wl_r<110> a_wl_r<109> a_wl_r<108> a_wl_r<107> a_wl_r<106> a_wl_r<105> a_wl_r<104> a_wl_r<103> a_wl_r<102> a_wl_r<101> a_wl_r<100> a_wl_r<99> a_wl_r<98> a_wl_r<97> a_wl_r<96> a_wl_r<95> a_wl_r<94> a_wl_r<93> a_wl_r<92> a_wl_r<91> a_wl_r<90> a_wl_r<89> a_wl_r<88> a_wl_r<87> a_wl_r<86> a_wl_r<85> a_wl_r<84> a_wl_r<83> a_wl_r<82> a_wl_r<81> a_wl_r<80> a_wl_r<79> a_wl_r<78> a_wl_r<77> a_wl_r<76> a_wl_r<75> a_wl_r<74> a_wl_r<73> a_wl_r<72> a_wl_r<71> a_wl_r<70> a_wl_r<69> a_wl_r<68> a_wl_r<67> a_wl_r<66> a_wl_r<65> a_wl_r<64> a_wl_r<63> a_wl_r<62> a_wl_r<61> a_wl_r<60> a_wl_r<59> a_wl_r<58> a_wl_r<57> a_wl_r<56> a_wl_r<55> a_wl_r<54> a_wl_r<53> a_wl_r<52> a_wl_r<51> a_wl_r<50> a_wl_r<49> a_wl_r<48> a_wl_r<47> a_wl_r<46> a_wl_r<45> a_wl_r<44> a_wl_r<43> a_wl_r<42> a_wl_r<41> a_wl_r<40> a_wl_r<39> a_wl_r<38> a_wl_r<37> a_wl_r<36> a_wl_r<35> a_wl_r<34> a_wl_r<33> a_wl_r<32> a_wl_r<31> a_wl_r<30> a_wl_r<29> a_wl_r<28> a_wl_r<27> a_wl_r<26> a_wl_r<25> a_wl_r<24> a_wl_r<23> a_wl_r<22> a_wl_r<21> a_wl_r<20> a_wl_r<19> a_wl_r<18> a_wl_r<17> a_wl_r<16> a_wl_r<15> a_wl_r<14> a_wl_r<13> a_wl_r<12> a_wl_r<11> a_wl_r<10> a_wl_r<9> a_wl_r<8> a_wl_r<7> a_wl_r<6> a_wl_r<5> a_wl_r<4> a_wl_r<3> a_wl_r<2> a_wl_r<1> a_wl_r<0> b_blc_r<15> b_blc_r<14> b_blc_r<13> b_blc_r<12> b_blc_r<11> b_blc_r<10> b_blc_r<9> b_blc_r<8> b_blc_r<7> b_blc_r<6> b_blc_r<5> b_blc_r<4> b_blc_r<3> b_blc_r<2> b_blc_r<1> b_blc_r<0> b_blt_r<15> b_blt_r<14> b_blt_r<13> b_blt_r<12> b_blt_r<11> b_blt_r<10> b_blt_r<9> b_blt_r<8> b_blt_r<7> b_blt_r<6> b_blt_r<5> b_blt_r<4> b_blt_r<3> b_blt_r<2> b_blt_r<1> b_blt_r<0> b_wl_r<127> b_wl_r<126> b_wl_r<125> b_wl_r<124> b_wl_r<123> b_wl_r<122> b_wl_r<121> b_wl_r<120> b_wl_r<119> b_wl_r<118> b_wl_r<117> b_wl_r<116> b_wl_r<115> b_wl_r<114> b_wl_r<113> b_wl_r<112> b_wl_r<111> b_wl_r<110> b_wl_r<109> b_wl_r<108> b_wl_r<107> b_wl_r<106> b_wl_r<105> b_wl_r<104> b_wl_r<103> b_wl_r<102> b_wl_r<101> b_wl_r<100> b_wl_r<99> b_wl_r<98> b_wl_r<97> b_wl_r<96> b_wl_r<95> b_wl_r<94> b_wl_r<93> b_wl_r<92> b_wl_r<91> b_wl_r<90> b_wl_r<89> b_wl_r<88> b_wl_r<87> b_wl_r<86> b_wl_r<85> b_wl_r<84> b_wl_r<83> b_wl_r<82> b_wl_r<81> b_wl_r<80> b_wl_r<79> b_wl_r<78> b_wl_r<77> b_wl_r<76> b_wl_r<75> b_wl_r<74> b_wl_r<73> b_wl_r<72> b_wl_r<71> b_wl_r<70> b_wl_r<69> b_wl_r<68> b_wl_r<67> b_wl_r<66> b_wl_r<65> b_wl_r<64> b_wl_r<63> b_wl_r<62> b_wl_r<61> b_wl_r<60> b_wl_r<59> b_wl_r<58> b_wl_r<57> b_wl_r<56> b_wl_r<55> b_wl_r<54> b_wl_r<53> b_wl_r<52> b_wl_r<51> b_wl_r<50> b_wl_r<49> b_wl_r<48> b_wl_r<47> b_wl_r<46> b_wl_r<45> b_wl_r<44> b_wl_r<43> b_wl_r<42> b_wl_r<41> b_wl_r<40> b_wl_r<39> b_wl_r<38> b_wl_r<37> b_wl_r<36> b_wl_r<35> b_wl_r<34> b_wl_r<33> b_wl_r<32> b_wl_r<31> b_wl_r<30> b_wl_r<29> b_wl_r<28> b_wl_r<27> b_wl_r<26> b_wl_r<25> b_wl_r<24> b_wl_r<23> b_wl_r<22> b_wl_r<21> b_wl_r<20> b_wl_r<19> b_wl_r<18> b_wl_r<17> b_wl_r<16> b_wl_r<15> b_wl_r<14> b_wl_r<13> b_wl_r<12> b_wl_r<11> b_wl_r<10> b_wl_r<9> b_wl_r<8> b_wl_r<7> b_wl_r<6> b_wl_r<5> b_wl_r<4> b_wl_r<3> b_wl_r<2> b_wl_r<1> b_wl_r<0> VDDARRAY! VSS! / RM_IHPSG13_512x8_c2_2P_MATRIX_pcell_1 +XRAM<0> a_blc_l<15> a_blc_l<14> a_blc_l<13> a_blc_l<12> a_blc_l<11> a_blc_l<10> a_blc_l<9> a_blc_l<8> a_blc_l<7> a_blc_l<6> a_blc_l<5> a_blc_l<4> a_blc_l<3> a_blc_l<2> a_blc_l<1> a_blc_l<0> a_blt_l<15> a_blt_l<14> a_blt_l<13> a_blt_l<12> a_blt_l<11> a_blt_l<10> a_blt_l<9> a_blt_l<8> a_blt_l<7> a_blt_l<6> a_blt_l<5> a_blt_l<4> a_blt_l<3> a_blt_l<2> a_blt_l<1> a_blt_l<0> a_wl_l<127> a_wl_l<126> a_wl_l<125> a_wl_l<124> a_wl_l<123> a_wl_l<122> a_wl_l<121> a_wl_l<120> a_wl_l<119> a_wl_l<118> a_wl_l<117> a_wl_l<116> a_wl_l<115> a_wl_l<114> a_wl_l<113> a_wl_l<112> a_wl_l<111> a_wl_l<110> a_wl_l<109> a_wl_l<108> a_wl_l<107> a_wl_l<106> a_wl_l<105> a_wl_l<104> a_wl_l<103> a_wl_l<102> a_wl_l<101> a_wl_l<100> a_wl_l<99> a_wl_l<98> a_wl_l<97> a_wl_l<96> a_wl_l<95> a_wl_l<94> a_wl_l<93> a_wl_l<92> a_wl_l<91> a_wl_l<90> a_wl_l<89> a_wl_l<88> a_wl_l<87> a_wl_l<86> a_wl_l<85> a_wl_l<84> a_wl_l<83> a_wl_l<82> a_wl_l<81> a_wl_l<80> a_wl_l<79> a_wl_l<78> a_wl_l<77> a_wl_l<76> a_wl_l<75> a_wl_l<74> a_wl_l<73> a_wl_l<72> a_wl_l<71> a_wl_l<70> a_wl_l<69> a_wl_l<68> a_wl_l<67> a_wl_l<66> a_wl_l<65> a_wl_l<64> a_wl_l<63> a_wl_l<62> a_wl_l<61> a_wl_l<60> a_wl_l<59> a_wl_l<58> a_wl_l<57> a_wl_l<56> a_wl_l<55> a_wl_l<54> a_wl_l<53> a_wl_l<52> a_wl_l<51> a_wl_l<50> a_wl_l<49> a_wl_l<48> a_wl_l<47> a_wl_l<46> a_wl_l<45> a_wl_l<44> a_wl_l<43> a_wl_l<42> a_wl_l<41> a_wl_l<40> a_wl_l<39> a_wl_l<38> a_wl_l<37> a_wl_l<36> a_wl_l<35> a_wl_l<34> a_wl_l<33> a_wl_l<32> a_wl_l<31> a_wl_l<30> a_wl_l<29> a_wl_l<28> a_wl_l<27> a_wl_l<26> a_wl_l<25> a_wl_l<24> a_wl_l<23> a_wl_l<22> a_wl_l<21> a_wl_l<20> a_wl_l<19> a_wl_l<18> a_wl_l<17> a_wl_l<16> a_wl_l<15> a_wl_l<14> a_wl_l<13> a_wl_l<12> a_wl_l<11> a_wl_l<10> a_wl_l<9> a_wl_l<8> a_wl_l<7> a_wl_l<6> a_wl_l<5> a_wl_l<4> a_wl_l<3> a_wl_l<2> a_wl_l<1> a_wl_l<0> b_blc_l<15> b_blc_l<14> b_blc_l<13> b_blc_l<12> b_blc_l<11> b_blc_l<10> b_blc_l<9> b_blc_l<8> b_blc_l<7> b_blc_l<6> b_blc_l<5> b_blc_l<4> b_blc_l<3> b_blc_l<2> b_blc_l<1> b_blc_l<0> b_blt_l<15> b_blt_l<14> b_blt_l<13> b_blt_l<12> b_blt_l<11> b_blt_l<10> b_blt_l<9> b_blt_l<8> b_blt_l<7> b_blt_l<6> b_blt_l<5> b_blt_l<4> b_blt_l<3> b_blt_l<2> b_blt_l<1> b_blt_l<0> b_wl_l<127> b_wl_l<126> b_wl_l<125> b_wl_l<124> b_wl_l<123> b_wl_l<122> b_wl_l<121> b_wl_l<120> b_wl_l<119> b_wl_l<118> b_wl_l<117> b_wl_l<116> b_wl_l<115> b_wl_l<114> b_wl_l<113> b_wl_l<112> b_wl_l<111> b_wl_l<110> b_wl_l<109> b_wl_l<108> b_wl_l<107> b_wl_l<106> b_wl_l<105> b_wl_l<104> b_wl_l<103> b_wl_l<102> b_wl_l<101> b_wl_l<100> b_wl_l<99> b_wl_l<98> b_wl_l<97> b_wl_l<96> b_wl_l<95> b_wl_l<94> b_wl_l<93> b_wl_l<92> b_wl_l<91> b_wl_l<90> b_wl_l<89> b_wl_l<88> b_wl_l<87> b_wl_l<86> b_wl_l<85> b_wl_l<84> b_wl_l<83> b_wl_l<82> b_wl_l<81> b_wl_l<80> b_wl_l<79> b_wl_l<78> b_wl_l<77> b_wl_l<76> b_wl_l<75> b_wl_l<74> b_wl_l<73> b_wl_l<72> b_wl_l<71> b_wl_l<70> b_wl_l<69> b_wl_l<68> b_wl_l<67> b_wl_l<66> b_wl_l<65> b_wl_l<64> b_wl_l<63> b_wl_l<62> b_wl_l<61> b_wl_l<60> b_wl_l<59> b_wl_l<58> b_wl_l<57> b_wl_l<56> b_wl_l<55> b_wl_l<54> b_wl_l<53> b_wl_l<52> b_wl_l<51> b_wl_l<50> b_wl_l<49> b_wl_l<48> b_wl_l<47> b_wl_l<46> b_wl_l<45> b_wl_l<44> b_wl_l<43> b_wl_l<42> b_wl_l<41> b_wl_l<40> b_wl_l<39> b_wl_l<38> b_wl_l<37> b_wl_l<36> b_wl_l<35> b_wl_l<34> b_wl_l<33> b_wl_l<32> b_wl_l<31> b_wl_l<30> b_wl_l<29> b_wl_l<28> b_wl_l<27> b_wl_l<26> b_wl_l<25> b_wl_l<24> b_wl_l<23> b_wl_l<22> b_wl_l<21> b_wl_l<20> b_wl_l<19> b_wl_l<18> b_wl_l<17> b_wl_l<16> b_wl_l<15> b_wl_l<14> b_wl_l<13> b_wl_l<12> b_wl_l<11> b_wl_l<10> b_wl_l<9> b_wl_l<8> b_wl_l<7> b_wl_l<6> b_wl_l<5> b_wl_l<4> b_wl_l<3> b_wl_l<2> b_wl_l<1> b_wl_l<0> VDDARRAY! VSS! / RM_IHPSG13_512x8_c2_2P_MATRIX_pcell_1 + + +XB_COLDRV<1> b_addr_col<1> b_addr_col<0> b_addr_col_r<1> b_addr_col_r<0> b_addr_dec<7> b_addr_dec<6> b_addr_dec<5> b_addr_dec<4> b_addr_dec<3> b_addr_dec<2> b_addr_dec<1> b_addr_dec<0> b_addr_dec_r<7> b_addr_dec_r<6> b_addr_dec_r<5> b_addr_dec_r<4> b_addr_dec_r<3> b_addr_dec_r<2> b_addr_dec_r<1> b_addr_dec_r<0> b_dclk b_dclk_p_r<0> b_rclk b_rclk_p_r<0> b_wclk b_wclk_p_r<0> VDD! VSS! / RM_IHPSG13_512x8_c2_2P_COLDRV13X4 +XB_COLDRV<0> b_addr_col<1> b_addr_col<0> b_addr_col_l<1> b_addr_col_l<0> b_addr_dec<7> b_addr_dec<6> b_addr_dec<5> b_addr_dec<4> b_addr_dec<3> b_addr_dec<2> b_addr_dec<1> b_addr_dec<0> b_addr_dec_l<7> b_addr_dec_l<6> b_addr_dec_l<5> b_addr_dec_l<4> b_addr_dec_l<3> b_addr_dec_l<2> b_addr_dec_l<1> b_addr_dec_l<0> b_dclk b_dclk_p_l<0> b_rclk b_rclk_p_l<0> b_wclk b_wclk_p_l<0> VDD! VSS! / RM_IHPSG13_512x8_c2_2P_COLDRV13X4 +XA_COLDRV<1> a_addr_col<1> a_addr_col<0> a_addr_col_r<1> a_addr_col_r<0> a_addr_dec<7> a_addr_dec<6> a_addr_dec<5> a_addr_dec<4> a_addr_dec<3> a_addr_dec<2> a_addr_dec<1> a_addr_dec<0> a_addr_dec_r<7> a_addr_dec_r<6> a_addr_dec_r<5> a_addr_dec_r<4> a_addr_dec_r<3> a_addr_dec_r<2> a_addr_dec_r<1> a_addr_dec_r<0> a_dclk a_dclk_p_r<0> a_rclk a_rclk_p_r<0> a_wclk a_wclk_p_r<0> VDD! VSS! / RM_IHPSG13_512x8_c2_2P_COLDRV13X4 +XA_COLDRV<0> a_addr_col<1> a_addr_col<0> a_addr_col_l<1> a_addr_col_l<0> a_addr_dec<7> a_addr_dec<6> a_addr_dec<5> a_addr_dec<4> a_addr_dec<3> a_addr_dec<2> a_addr_dec<1> a_addr_dec<0> a_addr_dec_l<7> a_addr_dec_l<6> a_addr_dec_l<5> a_addr_dec_l<4> a_addr_dec_l<3> a_addr_dec_l<2> a_addr_dec_l<1> a_addr_dec_l<0> a_dclk a_dclk_p_l<0> a_rclk a_rclk_p_l<0> a_wclk a_wclk_p_l<0> VDD! VSS! / RM_IHPSG13_512x8_c2_2P_COLDRV13X4 + + +XB_WLDRV<15> b_wi<127> b_wi<126> b_wi<125> b_wi<124> b_wi<123> b_wi<122> b_wi<121> b_wi<120> b_wi<119> b_wi<118> b_wi<117> b_wi<116> b_wi<115> b_wi<114> b_wi<113> b_wi<112> b_wl_r<127> b_wl_r<126> b_wl_r<125> b_wl_r<124> b_wl_r<123> b_wl_r<122> b_wl_r<121> b_wl_r<120> b_wl_r<119> b_wl_r<118> b_wl_r<117> b_wl_r<116> b_wl_r<115> b_wl_r<114> b_wl_r<113> b_wl_r<112> VDD! VSS! / RM_IHPSG13_512x8_c2_2P_WLDRV16X4 +XB_WLDRV<14> b_wi<111> b_wi<110> b_wi<109> b_wi<108> b_wi<107> b_wi<106> b_wi<105> b_wi<104> b_wi<103> b_wi<102> b_wi<101> b_wi<100> b_wi<99> b_wi<98> b_wi<97> b_wi<96> b_wl_r<111> b_wl_r<110> b_wl_r<109> b_wl_r<108> b_wl_r<107> b_wl_r<106> b_wl_r<105> b_wl_r<104> b_wl_r<103> b_wl_r<102> b_wl_r<101> b_wl_r<100> b_wl_r<99> b_wl_r<98> b_wl_r<97> b_wl_r<96> VDD! VSS! / RM_IHPSG13_512x8_c2_2P_WLDRV16X4 +XB_WLDRV<13> b_wi<95> b_wi<94> b_wi<93> b_wi<92> b_wi<91> b_wi<90> b_wi<89> b_wi<88> b_wi<87> b_wi<86> b_wi<85> b_wi<84> b_wi<83> b_wi<82> b_wi<81> b_wi<80> b_wl_r<95> b_wl_r<94> b_wl_r<93> b_wl_r<92> b_wl_r<91> b_wl_r<90> b_wl_r<89> b_wl_r<88> b_wl_r<87> b_wl_r<86> b_wl_r<85> b_wl_r<84> b_wl_r<83> b_wl_r<82> b_wl_r<81> b_wl_r<80> VDD! VSS! / RM_IHPSG13_512x8_c2_2P_WLDRV16X4 +XB_WLDRV<12> b_wi<79> b_wi<78> b_wi<77> b_wi<76> b_wi<75> b_wi<74> b_wi<73> b_wi<72> b_wi<71> b_wi<70> b_wi<69> b_wi<68> b_wi<67> b_wi<66> b_wi<65> b_wi<64> b_wl_r<79> b_wl_r<78> b_wl_r<77> b_wl_r<76> b_wl_r<75> b_wl_r<74> b_wl_r<73> b_wl_r<72> b_wl_r<71> b_wl_r<70> b_wl_r<69> b_wl_r<68> b_wl_r<67> b_wl_r<66> b_wl_r<65> b_wl_r<64> VDD! VSS! / RM_IHPSG13_512x8_c2_2P_WLDRV16X4 +XB_WLDRV<11> b_wi<63> b_wi<62> b_wi<61> b_wi<60> b_wi<59> b_wi<58> b_wi<57> b_wi<56> b_wi<55> b_wi<54> b_wi<53> b_wi<52> b_wi<51> b_wi<50> b_wi<49> b_wi<48> b_wl_r<63> b_wl_r<62> b_wl_r<61> b_wl_r<60> b_wl_r<59> b_wl_r<58> b_wl_r<57> b_wl_r<56> b_wl_r<55> b_wl_r<54> b_wl_r<53> b_wl_r<52> b_wl_r<51> b_wl_r<50> b_wl_r<49> b_wl_r<48> VDD! VSS! / RM_IHPSG13_512x8_c2_2P_WLDRV16X4 +XB_WLDRV<10> b_wi<47> b_wi<46> b_wi<45> b_wi<44> b_wi<43> b_wi<42> b_wi<41> b_wi<40> b_wi<39> b_wi<38> b_wi<37> b_wi<36> b_wi<35> b_wi<34> b_wi<33> b_wi<32> b_wl_r<47> b_wl_r<46> b_wl_r<45> b_wl_r<44> b_wl_r<43> b_wl_r<42> b_wl_r<41> b_wl_r<40> b_wl_r<39> b_wl_r<38> b_wl_r<37> b_wl_r<36> b_wl_r<35> b_wl_r<34> b_wl_r<33> b_wl_r<32> VDD! VSS! / RM_IHPSG13_512x8_c2_2P_WLDRV16X4 +XB_WLDRV<9> b_wi<31> b_wi<30> b_wi<29> b_wi<28> b_wi<27> b_wi<26> b_wi<25> b_wi<24> b_wi<23> b_wi<22> b_wi<21> b_wi<20> b_wi<19> b_wi<18> b_wi<17> b_wi<16> b_wl_r<31> b_wl_r<30> b_wl_r<29> b_wl_r<28> b_wl_r<27> b_wl_r<26> b_wl_r<25> b_wl_r<24> b_wl_r<23> b_wl_r<22> b_wl_r<21> b_wl_r<20> b_wl_r<19> b_wl_r<18> b_wl_r<17> b_wl_r<16> VDD! VSS! / RM_IHPSG13_512x8_c2_2P_WLDRV16X4 +XB_WLDRV<8> b_wi<15> b_wi<14> b_wi<13> b_wi<12> b_wi<11> b_wi<10> b_wi<9> b_wi<8> b_wi<7> b_wi<6> b_wi<5> b_wi<4> b_wi<3> b_wi<2> b_wi<1> b_wi<0> b_wl_r<15> b_wl_r<14> b_wl_r<13> b_wl_r<12> b_wl_r<11> b_wl_r<10> b_wl_r<9> b_wl_r<8> b_wl_r<7> b_wl_r<6> b_wl_r<5> b_wl_r<4> b_wl_r<3> b_wl_r<2> b_wl_r<1> b_wl_r<0> VDD! VSS! / RM_IHPSG13_512x8_c2_2P_WLDRV16X4 +XB_WLDRV<7> b_wi<127> b_wi<126> b_wi<125> b_wi<124> b_wi<123> b_wi<122> b_wi<121> b_wi<120> b_wi<119> b_wi<118> b_wi<117> b_wi<116> b_wi<115> b_wi<114> b_wi<113> b_wi<112> b_wl_l<127> b_wl_l<126> b_wl_l<125> b_wl_l<124> b_wl_l<123> b_wl_l<122> b_wl_l<121> b_wl_l<120> b_wl_l<119> b_wl_l<118> b_wl_l<117> b_wl_l<116> b_wl_l<115> b_wl_l<114> b_wl_l<113> b_wl_l<112> VDD! VSS! / RM_IHPSG13_512x8_c2_2P_WLDRV16X4 +XB_WLDRV<6> b_wi<111> b_wi<110> b_wi<109> b_wi<108> b_wi<107> b_wi<106> b_wi<105> b_wi<104> b_wi<103> b_wi<102> b_wi<101> b_wi<100> b_wi<99> b_wi<98> b_wi<97> b_wi<96> b_wl_l<111> b_wl_l<110> b_wl_l<109> b_wl_l<108> b_wl_l<107> b_wl_l<106> b_wl_l<105> b_wl_l<104> b_wl_l<103> b_wl_l<102> b_wl_l<101> b_wl_l<100> b_wl_l<99> b_wl_l<98> b_wl_l<97> b_wl_l<96> VDD! VSS! / RM_IHPSG13_512x8_c2_2P_WLDRV16X4 +XB_WLDRV<5> b_wi<95> b_wi<94> b_wi<93> b_wi<92> b_wi<91> b_wi<90> b_wi<89> b_wi<88> b_wi<87> b_wi<86> b_wi<85> b_wi<84> b_wi<83> b_wi<82> b_wi<81> b_wi<80> b_wl_l<95> b_wl_l<94> b_wl_l<93> b_wl_l<92> b_wl_l<91> b_wl_l<90> b_wl_l<89> b_wl_l<88> b_wl_l<87> b_wl_l<86> b_wl_l<85> b_wl_l<84> b_wl_l<83> b_wl_l<82> b_wl_l<81> b_wl_l<80> VDD! VSS! / RM_IHPSG13_512x8_c2_2P_WLDRV16X4 +XB_WLDRV<4> b_wi<79> b_wi<78> b_wi<77> b_wi<76> b_wi<75> b_wi<74> b_wi<73> b_wi<72> b_wi<71> b_wi<70> b_wi<69> b_wi<68> b_wi<67> b_wi<66> b_wi<65> b_wi<64> b_wl_l<79> b_wl_l<78> b_wl_l<77> b_wl_l<76> b_wl_l<75> b_wl_l<74> b_wl_l<73> b_wl_l<72> b_wl_l<71> b_wl_l<70> b_wl_l<69> b_wl_l<68> b_wl_l<67> b_wl_l<66> b_wl_l<65> b_wl_l<64> VDD! VSS! / RM_IHPSG13_512x8_c2_2P_WLDRV16X4 +XB_WLDRV<3> b_wi<63> b_wi<62> b_wi<61> b_wi<60> b_wi<59> b_wi<58> b_wi<57> b_wi<56> b_wi<55> b_wi<54> b_wi<53> b_wi<52> b_wi<51> b_wi<50> b_wi<49> b_wi<48> b_wl_l<63> b_wl_l<62> b_wl_l<61> b_wl_l<60> b_wl_l<59> b_wl_l<58> b_wl_l<57> b_wl_l<56> b_wl_l<55> b_wl_l<54> b_wl_l<53> b_wl_l<52> b_wl_l<51> b_wl_l<50> b_wl_l<49> b_wl_l<48> VDD! VSS! / RM_IHPSG13_512x8_c2_2P_WLDRV16X4 +XB_WLDRV<2> b_wi<47> b_wi<46> b_wi<45> b_wi<44> b_wi<43> b_wi<42> b_wi<41> b_wi<40> b_wi<39> b_wi<38> b_wi<37> b_wi<36> b_wi<35> b_wi<34> b_wi<33> b_wi<32> b_wl_l<47> b_wl_l<46> b_wl_l<45> b_wl_l<44> b_wl_l<43> b_wl_l<42> b_wl_l<41> b_wl_l<40> b_wl_l<39> b_wl_l<38> b_wl_l<37> b_wl_l<36> b_wl_l<35> b_wl_l<34> b_wl_l<33> b_wl_l<32> VDD! VSS! / RM_IHPSG13_512x8_c2_2P_WLDRV16X4 +XB_WLDRV<1> b_wi<31> b_wi<30> b_wi<29> b_wi<28> b_wi<27> b_wi<26> b_wi<25> b_wi<24> b_wi<23> b_wi<22> b_wi<21> b_wi<20> b_wi<19> b_wi<18> b_wi<17> b_wi<16> b_wl_l<31> b_wl_l<30> b_wl_l<29> b_wl_l<28> b_wl_l<27> b_wl_l<26> b_wl_l<25> b_wl_l<24> b_wl_l<23> b_wl_l<22> b_wl_l<21> b_wl_l<20> b_wl_l<19> b_wl_l<18> b_wl_l<17> b_wl_l<16> VDD! VSS! / RM_IHPSG13_512x8_c2_2P_WLDRV16X4 +XB_WLDRV<0> b_wi<15> b_wi<14> b_wi<13> b_wi<12> b_wi<11> b_wi<10> b_wi<9> b_wi<8> b_wi<7> b_wi<6> b_wi<5> b_wi<4> b_wi<3> b_wi<2> b_wi<1> b_wi<0> b_wl_l<15> b_wl_l<14> b_wl_l<13> b_wl_l<12> b_wl_l<11> b_wl_l<10> b_wl_l<9> b_wl_l<8> b_wl_l<7> b_wl_l<6> b_wl_l<5> b_wl_l<4> b_wl_l<3> b_wl_l<2> b_wl_l<1> b_wl_l<0> VDD! VSS! / RM_IHPSG13_512x8_c2_2P_WLDRV16X4 +XA_WLDRV<15> a_wi<127> a_wi<126> a_wi<125> a_wi<124> a_wi<123> a_wi<122> a_wi<121> a_wi<120> a_wi<119> a_wi<118> a_wi<117> a_wi<116> a_wi<115> a_wi<114> a_wi<113> a_wi<112> a_wl_r<127> a_wl_r<126> a_wl_r<125> a_wl_r<124> a_wl_r<123> a_wl_r<122> a_wl_r<121> a_wl_r<120> a_wl_r<119> a_wl_r<118> a_wl_r<117> a_wl_r<116> a_wl_r<115> a_wl_r<114> a_wl_r<113> a_wl_r<112> VDD! VSS! / RM_IHPSG13_512x8_c2_2P_WLDRV16X4 +XA_WLDRV<14> a_wi<111> a_wi<110> a_wi<109> a_wi<108> a_wi<107> a_wi<106> a_wi<105> a_wi<104> a_wi<103> a_wi<102> a_wi<101> a_wi<100> a_wi<99> a_wi<98> a_wi<97> a_wi<96> a_wl_r<111> a_wl_r<110> a_wl_r<109> a_wl_r<108> a_wl_r<107> a_wl_r<106> a_wl_r<105> a_wl_r<104> a_wl_r<103> a_wl_r<102> a_wl_r<101> a_wl_r<100> a_wl_r<99> a_wl_r<98> a_wl_r<97> a_wl_r<96> VDD! VSS! / RM_IHPSG13_512x8_c2_2P_WLDRV16X4 +XA_WLDRV<13> a_wi<95> a_wi<94> a_wi<93> a_wi<92> a_wi<91> a_wi<90> a_wi<89> a_wi<88> a_wi<87> a_wi<86> a_wi<85> a_wi<84> a_wi<83> a_wi<82> a_wi<81> a_wi<80> a_wl_r<95> a_wl_r<94> a_wl_r<93> a_wl_r<92> a_wl_r<91> a_wl_r<90> a_wl_r<89> a_wl_r<88> a_wl_r<87> a_wl_r<86> a_wl_r<85> a_wl_r<84> a_wl_r<83> a_wl_r<82> a_wl_r<81> a_wl_r<80> VDD! VSS! / RM_IHPSG13_512x8_c2_2P_WLDRV16X4 +XA_WLDRV<12> a_wi<79> a_wi<78> a_wi<77> a_wi<76> a_wi<75> a_wi<74> a_wi<73> a_wi<72> a_wi<71> a_wi<70> a_wi<69> a_wi<68> a_wi<67> a_wi<66> a_wi<65> a_wi<64> a_wl_r<79> a_wl_r<78> a_wl_r<77> a_wl_r<76> a_wl_r<75> a_wl_r<74> a_wl_r<73> a_wl_r<72> a_wl_r<71> a_wl_r<70> a_wl_r<69> a_wl_r<68> a_wl_r<67> a_wl_r<66> a_wl_r<65> a_wl_r<64> VDD! VSS! / RM_IHPSG13_512x8_c2_2P_WLDRV16X4 +XA_WLDRV<11> a_wi<63> a_wi<62> a_wi<61> a_wi<60> a_wi<59> a_wi<58> a_wi<57> a_wi<56> a_wi<55> a_wi<54> a_wi<53> a_wi<52> a_wi<51> a_wi<50> a_wi<49> a_wi<48> a_wl_r<63> a_wl_r<62> a_wl_r<61> a_wl_r<60> a_wl_r<59> a_wl_r<58> a_wl_r<57> a_wl_r<56> a_wl_r<55> a_wl_r<54> a_wl_r<53> a_wl_r<52> a_wl_r<51> a_wl_r<50> a_wl_r<49> a_wl_r<48> VDD! VSS! / RM_IHPSG13_512x8_c2_2P_WLDRV16X4 +XA_WLDRV<10> a_wi<47> a_wi<46> a_wi<45> a_wi<44> a_wi<43> a_wi<42> a_wi<41> a_wi<40> a_wi<39> a_wi<38> a_wi<37> a_wi<36> a_wi<35> a_wi<34> a_wi<33> a_wi<32> a_wl_r<47> a_wl_r<46> a_wl_r<45> a_wl_r<44> a_wl_r<43> a_wl_r<42> a_wl_r<41> a_wl_r<40> a_wl_r<39> a_wl_r<38> a_wl_r<37> a_wl_r<36> a_wl_r<35> a_wl_r<34> a_wl_r<33> a_wl_r<32> VDD! VSS! / RM_IHPSG13_512x8_c2_2P_WLDRV16X4 +XA_WLDRV<9> a_wi<31> a_wi<30> a_wi<29> a_wi<28> a_wi<27> a_wi<26> a_wi<25> a_wi<24> a_wi<23> a_wi<22> a_wi<21> a_wi<20> a_wi<19> a_wi<18> a_wi<17> a_wi<16> a_wl_r<31> a_wl_r<30> a_wl_r<29> a_wl_r<28> a_wl_r<27> a_wl_r<26> a_wl_r<25> a_wl_r<24> a_wl_r<23> a_wl_r<22> a_wl_r<21> a_wl_r<20> a_wl_r<19> a_wl_r<18> a_wl_r<17> a_wl_r<16> VDD! VSS! / RM_IHPSG13_512x8_c2_2P_WLDRV16X4 +XA_WLDRV<8> a_wi<15> a_wi<14> a_wi<13> a_wi<12> a_wi<11> a_wi<10> a_wi<9> a_wi<8> a_wi<7> a_wi<6> a_wi<5> a_wi<4> a_wi<3> a_wi<2> a_wi<1> a_wi<0> a_wl_r<15> a_wl_r<14> a_wl_r<13> a_wl_r<12> a_wl_r<11> a_wl_r<10> a_wl_r<9> a_wl_r<8> a_wl_r<7> a_wl_r<6> a_wl_r<5> a_wl_r<4> a_wl_r<3> a_wl_r<2> a_wl_r<1> a_wl_r<0> VDD! VSS! / RM_IHPSG13_512x8_c2_2P_WLDRV16X4 +XA_WLDRV<7> a_wi<127> a_wi<126> a_wi<125> a_wi<124> a_wi<123> a_wi<122> a_wi<121> a_wi<120> a_wi<119> a_wi<118> a_wi<117> a_wi<116> a_wi<115> a_wi<114> a_wi<113> a_wi<112> a_wl_l<127> a_wl_l<126> a_wl_l<125> a_wl_l<124> a_wl_l<123> a_wl_l<122> a_wl_l<121> a_wl_l<120> a_wl_l<119> a_wl_l<118> a_wl_l<117> a_wl_l<116> a_wl_l<115> a_wl_l<114> a_wl_l<113> a_wl_l<112> VDD! VSS! / RM_IHPSG13_512x8_c2_2P_WLDRV16X4 +XA_WLDRV<6> a_wi<111> a_wi<110> a_wi<109> a_wi<108> a_wi<107> a_wi<106> a_wi<105> a_wi<104> a_wi<103> a_wi<102> a_wi<101> a_wi<100> a_wi<99> a_wi<98> a_wi<97> a_wi<96> a_wl_l<111> a_wl_l<110> a_wl_l<109> a_wl_l<108> a_wl_l<107> a_wl_l<106> a_wl_l<105> a_wl_l<104> a_wl_l<103> a_wl_l<102> a_wl_l<101> a_wl_l<100> a_wl_l<99> a_wl_l<98> a_wl_l<97> a_wl_l<96> VDD! VSS! / RM_IHPSG13_512x8_c2_2P_WLDRV16X4 +XA_WLDRV<5> a_wi<95> a_wi<94> a_wi<93> a_wi<92> a_wi<91> a_wi<90> a_wi<89> a_wi<88> a_wi<87> a_wi<86> a_wi<85> a_wi<84> a_wi<83> a_wi<82> a_wi<81> a_wi<80> a_wl_l<95> a_wl_l<94> a_wl_l<93> a_wl_l<92> a_wl_l<91> a_wl_l<90> a_wl_l<89> a_wl_l<88> a_wl_l<87> a_wl_l<86> a_wl_l<85> a_wl_l<84> a_wl_l<83> a_wl_l<82> a_wl_l<81> a_wl_l<80> VDD! VSS! / RM_IHPSG13_512x8_c2_2P_WLDRV16X4 +XA_WLDRV<4> a_wi<79> a_wi<78> a_wi<77> a_wi<76> a_wi<75> a_wi<74> a_wi<73> a_wi<72> a_wi<71> a_wi<70> a_wi<69> a_wi<68> a_wi<67> a_wi<66> a_wi<65> a_wi<64> a_wl_l<79> a_wl_l<78> a_wl_l<77> a_wl_l<76> a_wl_l<75> a_wl_l<74> a_wl_l<73> a_wl_l<72> a_wl_l<71> a_wl_l<70> a_wl_l<69> a_wl_l<68> a_wl_l<67> a_wl_l<66> a_wl_l<65> a_wl_l<64> VDD! VSS! / RM_IHPSG13_512x8_c2_2P_WLDRV16X4 +XA_WLDRV<3> a_wi<63> a_wi<62> a_wi<61> a_wi<60> a_wi<59> a_wi<58> a_wi<57> a_wi<56> a_wi<55> a_wi<54> a_wi<53> a_wi<52> a_wi<51> a_wi<50> a_wi<49> a_wi<48> a_wl_l<63> a_wl_l<62> a_wl_l<61> a_wl_l<60> a_wl_l<59> a_wl_l<58> a_wl_l<57> a_wl_l<56> a_wl_l<55> a_wl_l<54> a_wl_l<53> a_wl_l<52> a_wl_l<51> a_wl_l<50> a_wl_l<49> a_wl_l<48> VDD! VSS! / RM_IHPSG13_512x8_c2_2P_WLDRV16X4 +XA_WLDRV<2> a_wi<47> a_wi<46> a_wi<45> a_wi<44> a_wi<43> a_wi<42> a_wi<41> a_wi<40> a_wi<39> a_wi<38> a_wi<37> a_wi<36> a_wi<35> a_wi<34> a_wi<33> a_wi<32> a_wl_l<47> a_wl_l<46> a_wl_l<45> a_wl_l<44> a_wl_l<43> a_wl_l<42> a_wl_l<41> a_wl_l<40> a_wl_l<39> a_wl_l<38> a_wl_l<37> a_wl_l<36> a_wl_l<35> a_wl_l<34> a_wl_l<33> a_wl_l<32> VDD! VSS! / RM_IHPSG13_512x8_c2_2P_WLDRV16X4 +XA_WLDRV<1> a_wi<31> a_wi<30> a_wi<29> a_wi<28> a_wi<27> a_wi<26> a_wi<25> a_wi<24> a_wi<23> a_wi<22> a_wi<21> a_wi<20> a_wi<19> a_wi<18> a_wi<17> a_wi<16> a_wl_l<31> a_wl_l<30> a_wl_l<29> a_wl_l<28> a_wl_l<27> a_wl_l<26> a_wl_l<25> a_wl_l<24> a_wl_l<23> a_wl_l<22> a_wl_l<21> a_wl_l<20> a_wl_l<19> a_wl_l<18> a_wl_l<17> a_wl_l<16> VDD! VSS! / RM_IHPSG13_512x8_c2_2P_WLDRV16X4 +XA_WLDRV<0> a_wi<15> a_wi<14> a_wi<13> a_wi<12> a_wi<11> a_wi<10> a_wi<9> a_wi<8> a_wi<7> a_wi<6> a_wi<5> a_wi<4> a_wi<3> a_wi<2> a_wi<1> a_wi<0> a_wl_l<15> a_wl_l<14> a_wl_l<13> a_wl_l<12> a_wl_l<11> a_wl_l<10> a_wl_l<9> a_wl_l<8> a_wl_l<7> a_wl_l<6> a_wl_l<5> a_wl_l<4> a_wl_l<3> a_wl_l<2> a_wl_l<1> a_wl_l<0> VDD! VSS! / RM_IHPSG13_512x8_c2_2P_WLDRV16X4 + + +XB_CTRL b_aclk_n B_BIST_CLK B_BIST_MEN B_BIST_EN B_BIST_REN B_BIST_WEN b_tiel B_CLK B_MEN b_dclk b_eclk b_pulse_h b_pulse_l b_pulse b_rclk B_REN b_cs b_wclk B_WEN VDD! VSS! / RM_IHPSG13_512x8_c2_2P_CTRL +XA_CTRL a_aclk_n A_BIST_CLK A_BIST_MEN A_BIST_EN A_BIST_REN A_BIST_WEN a_tiel A_CLK A_MEN a_dclk a_eclk a_pulse_h a_pulse_l a_pulse a_rclk A_REN a_cs a_wclk A_WEN VDD! VSS! / RM_IHPSG13_512x8_c2_2P_CTRL + + +XB_ROWDEC b_addr_row<6> b_addr_row<5> b_addr_row<4> b_addr_row<3> b_addr_row<2> b_addr_row<1> b_addr_row<0> b_cs b_eclk b_wi<127> b_wi<126> b_wi<125> b_wi<124> b_wi<123> b_wi<122> b_wi<121> b_wi<120> b_wi<119> b_wi<118> b_wi<117> b_wi<116> b_wi<115> b_wi<114> b_wi<113> b_wi<112> b_wi<111> b_wi<110> b_wi<109> b_wi<108> b_wi<107> b_wi<106> b_wi<105> b_wi<104> b_wi<103> b_wi<102> b_wi<101> b_wi<100> b_wi<99> b_wi<98> b_wi<97> b_wi<96> b_wi<95> b_wi<94> b_wi<93> b_wi<92> b_wi<91> b_wi<90> b_wi<89> b_wi<88> b_wi<87> b_wi<86> b_wi<85> b_wi<84> b_wi<83> b_wi<82> b_wi<81> b_wi<80> b_wi<79> b_wi<78> b_wi<77> b_wi<76> b_wi<75> b_wi<74> b_wi<73> b_wi<72> b_wi<71> b_wi<70> b_wi<69> b_wi<68> b_wi<67> b_wi<66> b_wi<65> b_wi<64> b_wi<63> b_wi<62> b_wi<61> b_wi<60> b_wi<59> b_wi<58> b_wi<57> b_wi<56> b_wi<55> b_wi<54> b_wi<53> b_wi<52> b_wi<51> b_wi<50> b_wi<49> b_wi<48> b_wi<47> b_wi<46> b_wi<45> b_wi<44> b_wi<43> b_wi<42> b_wi<41> b_wi<40> b_wi<39> b_wi<38> b_wi<37> b_wi<36> b_wi<35> b_wi<34> b_wi<33> b_wi<32> b_wi<31> b_wi<30> b_wi<29> b_wi<28> b_wi<27> b_wi<26> b_wi<25> b_wi<24> b_wi<23> b_wi<22> b_wi<21> b_wi<20> b_wi<19> b_wi<18> b_wi<17> b_wi<16> b_wi<15> b_wi<14> b_wi<13> b_wi<12> b_wi<11> b_wi<10> b_wi<9> b_wi<8> b_wi<7> b_wi<6> b_wi<5> b_wi<4> b_wi<3> b_wi<2> b_wi<1> b_wi<0> VDD! VSS! / RM_IHPSG13_512x8_c2_2P_ROWDEC7 +XA_ROWDEC a_addr_row<6> a_addr_row<5> a_addr_row<4> a_addr_row<3> a_addr_row<2> a_addr_row<1> a_addr_row<0> a_cs a_eclk a_wi<127> a_wi<126> a_wi<125> a_wi<124> a_wi<123> a_wi<122> a_wi<121> a_wi<120> a_wi<119> a_wi<118> a_wi<117> a_wi<116> a_wi<115> a_wi<114> a_wi<113> a_wi<112> a_wi<111> a_wi<110> a_wi<109> a_wi<108> a_wi<107> a_wi<106> a_wi<105> a_wi<104> a_wi<103> a_wi<102> a_wi<101> a_wi<100> a_wi<99> a_wi<98> a_wi<97> a_wi<96> a_wi<95> a_wi<94> a_wi<93> a_wi<92> a_wi<91> a_wi<90> a_wi<89> a_wi<88> a_wi<87> a_wi<86> a_wi<85> a_wi<84> a_wi<83> a_wi<82> a_wi<81> a_wi<80> a_wi<79> a_wi<78> a_wi<77> a_wi<76> a_wi<75> a_wi<74> a_wi<73> a_wi<72> a_wi<71> a_wi<70> a_wi<69> a_wi<68> a_wi<67> a_wi<66> a_wi<65> a_wi<64> a_wi<63> a_wi<62> a_wi<61> a_wi<60> a_wi<59> a_wi<58> a_wi<57> a_wi<56> a_wi<55> a_wi<54> a_wi<53> a_wi<52> a_wi<51> a_wi<50> a_wi<49> a_wi<48> a_wi<47> a_wi<46> a_wi<45> a_wi<44> a_wi<43> a_wi<42> a_wi<41> a_wi<40> a_wi<39> a_wi<38> a_wi<37> a_wi<36> a_wi<35> a_wi<34> a_wi<33> a_wi<32> a_wi<31> a_wi<30> a_wi<29> a_wi<28> a_wi<27> a_wi<26> a_wi<25> a_wi<24> a_wi<23> a_wi<22> a_wi<21> a_wi<20> a_wi<19> a_wi<18> a_wi<17> a_wi<16> a_wi<15> a_wi<14> a_wi<13> a_wi<12> a_wi<11> a_wi<10> a_wi<9> a_wi<8> a_wi<7> a_wi<6> a_wi<5> a_wi<4> a_wi<3> a_wi<2> a_wi<1> a_wi<0> VDD! VSS! / RM_IHPSG13_512x8_c2_2P_ROWDEC7 +XB_ROWREG b_aclk_n B_ADDR<8> B_ADDR<7> B_ADDR<6> B_ADDR<5> B_ADDR<4> B_ADDR<3> B_ADDR<2> b_addr_row<6> b_addr_row<5> b_addr_row<4> b_addr_row<3> b_addr_row<2> b_addr_row<1> b_addr_row<0> B_BIST_ADDR<8> B_BIST_ADDR<7> B_BIST_ADDR<6> B_BIST_ADDR<5> B_BIST_ADDR<4> B_BIST_ADDR<3> B_BIST_ADDR<2> B_BIST_EN VDD! VSS! / RM_IHPSG13_512x8_c2_2P_ROWREG7 +XA_ROWREG a_aclk_n A_ADDR<8> A_ADDR<7> A_ADDR<6> A_ADDR<5> A_ADDR<4> A_ADDR<3> A_ADDR<2> a_addr_row<6> a_addr_row<5> a_addr_row<4> a_addr_row<3> a_addr_row<2> a_addr_row<1> a_addr_row<0> A_BIST_ADDR<8> A_BIST_ADDR<7> A_BIST_ADDR<6> A_BIST_ADDR<5> A_BIST_ADDR<4> A_BIST_ADDR<3> A_BIST_ADDR<2> A_BIST_EN VDD! VSS! / RM_IHPSG13_512x8_c2_2P_ROWREG7 +XB_COLDEC b_aclk_n B_ADDR<1> B_ADDR<0> b_addr_col<1> b_addr_col<0> b_addr_dec<7> b_addr_dec<6> b_addr_dec<5> b_addr_dec<4> b_addr_dec<3> b_addr_dec<2> b_addr_dec<1> b_addr_dec<0> B_BIST_ADDR<1> B_BIST_ADDR<0> B_BIST_EN VDD! VSS! / RM_IHPSG13_512x8_c2_2P_COLDEC2 +XA_COLDEC a_aclk_n A_ADDR<1> A_ADDR<0> a_addr_col<1> a_addr_col<0> a_addr_dec<7> a_addr_dec<6> a_addr_dec<5> a_addr_dec<4> a_addr_dec<3> a_addr_dec<2> a_addr_dec<1> a_addr_dec<0> A_BIST_ADDR<1> A_BIST_ADDR<0> A_BIST_EN VDD! VSS! / RM_IHPSG13_512x8_c2_2P_COLDEC2 + + +XB_DLYH b_pulse b_pulse_h VDD! VSS! / RM_IHPSG13_512x8_c2_2P_DLY_pcell_2 +XB_DLYL b_pulse_x b_pulse_l VDD! VSS! / RM_IHPSG13_512x8_c2_2P_DLY_pcell_3 +XA_DLYH a_pulse a_pulse_h VDD! VSS! / RM_IHPSG13_512x8_c2_2P_DLY_pcell_2 +XA_DLYL a_pulse_x a_pulse_l VDD! VSS! / RM_IHPSG13_512x8_c2_2P_DLY_pcell_3 +XB_DLYMUX b_pulse_h B_DLY b_pulse_x VDD! VSS! / RM_IHPSG13_512x8_c2_2P_DLY_MUX +XA_DLYMUX a_pulse_h A_DLY a_pulse_x VDD! VSS! / RM_IHPSG13_512x8_c2_2P_DLY_MUX + +XCOLCTRL<7> a_addr_dec_r<3> a_addr_dec_r<2> a_addr_dec_r<1> a_addr_dec_r<0> A_BIST_BM<7> A_BIST_DIN<7> A_BIST_EN a_blc_r<15> a_blc_r<14> a_blc_r<13> a_blc_r<12> a_blt_r<15> a_blt_r<14> a_blt_r<13> a_blt_r<12> A_BM<7> a_dclk_n_r<3> a_dclk_n_r<4> a_dclk_p_r<3> a_dclk_p_r<4> A_DOUT<7> A_DIN<7> a_rclk_n_r<3> a_rclk_n_r<4> a_rclk_p_r<3> a_rclk_p_r<4> a_tieh<7> a_wclk_n_r<3> a_wclk_n_r<4> a_wclk_p_r<3> a_wclk_p_r<4> b_addr_dec_r<3> b_addr_dec_r<2> b_addr_dec_r<1> b_addr_dec_r<0> B_BIST_BM<7> B_BIST_DIN<7> B_BIST_EN b_blc_r<15> b_blc_r<14> b_blc_r<13> b_blc_r<12> b_blt_r<15> b_blt_r<14> b_blt_r<13> b_blt_r<12> B_BM<7> b_dclk_n_r<3> b_dclk_n_r<4> b_dclk_p_r<3> b_dclk_p_r<4> B_DOUT<7> B_DIN<7> b_rclk_n_r<3> b_rclk_n_r<4> b_rclk_p_r<3> b_rclk_p_r<4> b_tieh<7> b_wclk_n_r<3> b_wclk_n_r<4> b_wclk_p_r<3> b_wclk_p_r<4> VDD! VSS! / RM_IHPSG13_512x8_c2_2P_COLCTRL2 +XCOLCTRL<6> a_addr_dec_r<3> a_addr_dec_r<2> a_addr_dec_r<1> a_addr_dec_r<0> A_BIST_BM<6> A_BIST_DIN<6> A_BIST_EN a_blc_r<11> a_blc_r<10> a_blc_r<9> a_blc_r<8> a_blt_r<11> a_blt_r<10> a_blt_r<9> a_blt_r<8> A_BM<6> a_dclk_n_r<2> a_dclk_n_r<3> a_dclk_p_r<2> a_dclk_p_r<3> A_DOUT<6> A_DIN<6> a_rclk_n_r<2> a_rclk_n_r<3> a_rclk_p_r<2> a_rclk_p_r<3> a_tieh<6> a_wclk_n_r<2> a_wclk_n_r<3> a_wclk_p_r<2> a_wclk_p_r<3> b_addr_dec_r<3> b_addr_dec_r<2> b_addr_dec_r<1> b_addr_dec_r<0> B_BIST_BM<6> B_BIST_DIN<6> B_BIST_EN b_blc_r<11> b_blc_r<10> b_blc_r<9> b_blc_r<8> b_blt_r<11> b_blt_r<10> b_blt_r<9> b_blt_r<8> B_BM<6> b_dclk_n_r<2> b_dclk_n_r<3> b_dclk_p_r<2> b_dclk_p_r<3> B_DOUT<6> B_DIN<6> b_rclk_n_r<2> b_rclk_n_r<3> b_rclk_p_r<2> b_rclk_p_r<3> b_tieh<6> b_wclk_n_r<2> b_wclk_n_r<3> b_wclk_p_r<2> b_wclk_p_r<3> VDD! VSS! / RM_IHPSG13_512x8_c2_2P_COLCTRL2 +XCOLCTRL<5> a_addr_dec_r<3> a_addr_dec_r<2> a_addr_dec_r<1> a_addr_dec_r<0> A_BIST_BM<5> A_BIST_DIN<5> A_BIST_EN a_blc_r<7> a_blc_r<6> a_blc_r<5> a_blc_r<4> a_blt_r<7> a_blt_r<6> a_blt_r<5> a_blt_r<4> A_BM<5> a_dclk_n_r<1> a_dclk_n_r<2> a_dclk_p_r<1> a_dclk_p_r<2> A_DOUT<5> A_DIN<5> a_rclk_n_r<1> a_rclk_n_r<2> a_rclk_p_r<1> a_rclk_p_r<2> a_tieh<5> a_wclk_n_r<1> a_wclk_n_r<2> a_wclk_p_r<1> a_wclk_p_r<2> b_addr_dec_r<3> b_addr_dec_r<2> b_addr_dec_r<1> b_addr_dec_r<0> B_BIST_BM<5> B_BIST_DIN<5> B_BIST_EN b_blc_r<7> b_blc_r<6> b_blc_r<5> b_blc_r<4> b_blt_r<7> b_blt_r<6> b_blt_r<5> b_blt_r<4> B_BM<5> b_dclk_n_r<1> b_dclk_n_r<2> b_dclk_p_r<1> b_dclk_p_r<2> B_DOUT<5> B_DIN<5> b_rclk_n_r<1> b_rclk_n_r<2> b_rclk_p_r<1> b_rclk_p_r<2> b_tieh<5> b_wclk_n_r<1> b_wclk_n_r<2> b_wclk_p_r<1> b_wclk_p_r<2> VDD! VSS! / RM_IHPSG13_512x8_c2_2P_COLCTRL2 +XCOLCTRL<4> a_addr_dec_r<3> a_addr_dec_r<2> a_addr_dec_r<1> a_addr_dec_r<0> A_BIST_BM<4> A_BIST_DIN<4> A_BIST_EN a_blc_r<3> a_blc_r<2> a_blc_r<1> a_blc_r<0> a_blt_r<3> a_blt_r<2> a_blt_r<1> a_blt_r<0> A_BM<4> a_dclk_n_r<0> a_dclk_n_r<1> a_dclk_p_r<0> a_dclk_p_r<1> A_DOUT<4> A_DIN<4> a_rclk_n_r<0> a_rclk_n_r<1> a_rclk_p_r<0> a_rclk_p_r<1> a_tieh<4> a_wclk_n_r<0> a_wclk_n_r<1> a_wclk_p_r<0> a_wclk_p_r<1> b_addr_dec_r<3> b_addr_dec_r<2> b_addr_dec_r<1> b_addr_dec_r<0> B_BIST_BM<4> B_BIST_DIN<4> B_BIST_EN b_blc_r<3> b_blc_r<2> b_blc_r<1> b_blc_r<0> b_blt_r<3> b_blt_r<2> b_blt_r<1> b_blt_r<0> B_BM<4> b_dclk_n_r<0> b_dclk_n_r<1> b_dclk_p_r<0> b_dclk_p_r<1> B_DOUT<4> B_DIN<4> b_rclk_n_r<0> b_rclk_n_r<1> b_rclk_p_r<0> b_rclk_p_r<1> b_tieh<4> b_wclk_n_r<0> b_wclk_n_r<1> b_wclk_p_r<0> b_wclk_p_r<1> VDD! VSS! / RM_IHPSG13_512x8_c2_2P_COLCTRL2 +XCOLCTRL<3> a_addr_dec_l<3> a_addr_dec_l<2> a_addr_dec_l<1> a_addr_dec_l<0> A_BIST_BM<0> A_BIST_DIN<0> A_BIST_EN a_blc_l<15> a_blc_l<14> a_blc_l<13> a_blc_l<12> a_blt_l<15> a_blt_l<14> a_blt_l<13> a_blt_l<12> A_BM<0> a_dclk_n_l<3> a_dclk_n_l<4> a_dclk_p_l<3> a_dclk_p_l<4> A_DOUT<0> A_DIN<0> a_rclk_n_l<3> a_rclk_n_l<4> a_rclk_p_l<3> a_rclk_p_l<4> a_tieh<0> a_wclk_n_l<3> a_wclk_n_l<4> a_wclk_p_l<3> a_wclk_p_l<4> b_addr_dec_l<3> b_addr_dec_l<2> b_addr_dec_l<1> b_addr_dec_l<0> B_BIST_BM<0> B_BIST_DIN<0> B_BIST_EN b_blc_l<15> b_blc_l<14> b_blc_l<13> b_blc_l<12> b_blt_l<15> b_blt_l<14> b_blt_l<13> b_blt_l<12> B_BM<0> b_dclk_n_l<3> b_dclk_n_l<4> b_dclk_p_l<3> b_dclk_p_l<4> B_DOUT<0> B_DIN<0> b_rclk_n_l<3> b_rclk_n_l<4> b_rclk_p_l<3> b_rclk_p_l<4> b_tieh<0> b_wclk_n_l<3> b_wclk_n_l<4> b_wclk_p_l<3> b_wclk_p_l<4> VDD! VSS! / RM_IHPSG13_512x8_c2_2P_COLCTRL2 +XCOLCTRL<2> a_addr_dec_l<3> a_addr_dec_l<2> a_addr_dec_l<1> a_addr_dec_l<0> A_BIST_BM<1> A_BIST_DIN<1> A_BIST_EN a_blc_l<11> a_blc_l<10> a_blc_l<9> a_blc_l<8> a_blt_l<11> a_blt_l<10> a_blt_l<9> a_blt_l<8> A_BM<1> a_dclk_n_l<2> a_dclk_n_l<3> a_dclk_p_l<2> a_dclk_p_l<3> A_DOUT<1> A_DIN<1> a_rclk_n_l<2> a_rclk_n_l<3> a_rclk_p_l<2> a_rclk_p_l<3> a_tieh<1> a_wclk_n_l<2> a_wclk_n_l<3> a_wclk_p_l<2> a_wclk_p_l<3> b_addr_dec_l<3> b_addr_dec_l<2> b_addr_dec_l<1> b_addr_dec_l<0> B_BIST_BM<1> B_BIST_DIN<1> B_BIST_EN b_blc_l<11> b_blc_l<10> b_blc_l<9> b_blc_l<8> b_blt_l<11> b_blt_l<10> b_blt_l<9> b_blt_l<8> B_BM<1> b_dclk_n_l<2> b_dclk_n_l<3> b_dclk_p_l<2> b_dclk_p_l<3> B_DOUT<1> B_DIN<1> b_rclk_n_l<2> b_rclk_n_l<3> b_rclk_p_l<2> b_rclk_p_l<3> b_tieh<1> b_wclk_n_l<2> b_wclk_n_l<3> b_wclk_p_l<2> b_wclk_p_l<3> VDD! VSS! / RM_IHPSG13_512x8_c2_2P_COLCTRL2 +XCOLCTRL<1> a_addr_dec_l<3> a_addr_dec_l<2> a_addr_dec_l<1> a_addr_dec_l<0> A_BIST_BM<2> A_BIST_DIN<2> A_BIST_EN a_blc_l<7> a_blc_l<6> a_blc_l<5> a_blc_l<4> a_blt_l<7> a_blt_l<6> a_blt_l<5> a_blt_l<4> A_BM<2> a_dclk_n_l<1> a_dclk_n_l<2> a_dclk_p_l<1> a_dclk_p_l<2> A_DOUT<2> A_DIN<2> a_rclk_n_l<1> a_rclk_n_l<2> a_rclk_p_l<1> a_rclk_p_l<2> a_tieh<2> a_wclk_n_l<1> a_wclk_n_l<2> a_wclk_p_l<1> a_wclk_p_l<2> b_addr_dec_l<3> b_addr_dec_l<2> b_addr_dec_l<1> b_addr_dec_l<0> B_BIST_BM<2> B_BIST_DIN<2> B_BIST_EN b_blc_l<7> b_blc_l<6> b_blc_l<5> b_blc_l<4> b_blt_l<7> b_blt_l<6> b_blt_l<5> b_blt_l<4> B_BM<2> b_dclk_n_l<1> b_dclk_n_l<2> b_dclk_p_l<1> b_dclk_p_l<2> B_DOUT<2> B_DIN<2> b_rclk_n_l<1> b_rclk_n_l<2> b_rclk_p_l<1> b_rclk_p_l<2> b_tieh<2> b_wclk_n_l<1> b_wclk_n_l<2> b_wclk_p_l<1> b_wclk_p_l<2> VDD! VSS! / RM_IHPSG13_512x8_c2_2P_COLCTRL2 +XCOLCTRL<0> a_addr_dec_l<3> a_addr_dec_l<2> a_addr_dec_l<1> a_addr_dec_l<0> A_BIST_BM<3> A_BIST_DIN<3> A_BIST_EN a_blc_l<3> a_blc_l<2> a_blc_l<1> a_blc_l<0> a_blt_l<3> a_blt_l<2> a_blt_l<1> a_blt_l<0> A_BM<3> a_dclk_n_l<0> a_dclk_n_l<1> a_dclk_p_l<0> a_dclk_p_l<1> A_DOUT<3> A_DIN<3> a_rclk_n_l<0> a_rclk_n_l<1> a_rclk_p_l<0> a_rclk_p_l<1> a_tieh<3> a_wclk_n_l<0> a_wclk_n_l<1> a_wclk_p_l<0> a_wclk_p_l<1> b_addr_dec_l<3> b_addr_dec_l<2> b_addr_dec_l<1> b_addr_dec_l<0> B_BIST_BM<3> B_BIST_DIN<3> B_BIST_EN b_blc_l<3> b_blc_l<2> b_blc_l<1> b_blc_l<0> b_blt_l<3> b_blt_l<2> b_blt_l<1> b_blt_l<0> B_BM<3> b_dclk_n_l<0> b_dclk_n_l<1> b_dclk_p_l<0> b_dclk_p_l<1> B_DOUT<3> B_DIN<3> b_rclk_n_l<0> b_rclk_n_l<1> b_rclk_p_l<0> b_rclk_p_l<1> b_tieh<3> b_wclk_n_l<0> b_wclk_n_l<1> b_wclk_p_l<0> b_wclk_p_l<1> VDD! VSS! / RM_IHPSG13_512x8_c2_2P_COLCTRL2 + + +XDRVFILL4<1> VDD! VSS! / RM_IHPSG13_512x8_c2_2P_COLDRV13_FILL4 +XDRVFILL4<2> VDD! VSS! / RM_IHPSG13_512x8_c2_2P_COLDRV13_FILL4 +XDRVFILL4<3> VDD! VSS! / RM_IHPSG13_512x8_c2_2P_COLDRV13_FILL4 +XDRVFILL4<4> VDD! VSS! / RM_IHPSG13_512x8_c2_2P_COLDRV13_FILL4 +XDRVFILL4<5> VDD! VSS! / RM_IHPSG13_512x8_c2_2P_COLDRV13_FILL4 +XDRVFILL4<6> VDD! VSS! / RM_IHPSG13_512x8_c2_2P_COLDRV13_FILL4 +XCOLFILL4<1> VDD! VSS! / RM_IHPSG13_512x8_c2_2P_COLDRV13_FILL4C2 +XCOLFILL4<2> VDD! VSS! / RM_IHPSG13_512x8_c2_2P_COLDRV13_FILL4C2 +XCOLFILL4<3> VDD! VSS! / RM_IHPSG13_512x8_c2_2P_COLDRV13_FILL4C2 +XCOLFILL4<4> VDD! VSS! / RM_IHPSG13_512x8_c2_2P_COLDRV13_FILL4C2 +XCOLFILL4<5> VDD! VSS! / RM_IHPSG13_512x8_c2_2P_COLDRV13_FILL4C2 +XCOLFILL4<6> VDD! VSS! / RM_IHPSG13_512x8_c2_2P_COLDRV13_FILL4C2 +XCOLFILL4<7> VDD! VSS! / RM_IHPSG13_512x8_c2_2P_COLDRV13_FILL4C2 +XCOLFILL4<8> VDD! VSS! / RM_IHPSG13_512x8_c2_2P_COLDRV13_FILL4C2 +XCOLFILL4<9> VDD! VSS! / RM_IHPSG13_512x8_c2_2P_COLDRV13_FILL4C2 +XCOLFILL4<10> VDD! VSS! / RM_IHPSG13_512x8_c2_2P_COLDRV13_FILL4C2 +XCOLFILL4<11> VDD! VSS! / RM_IHPSG13_512x8_c2_2P_COLDRV13_FILL4C2 +XCOLFILL4<12> VDD! VSS! / RM_IHPSG13_512x8_c2_2P_COLDRV13_FILL4C2 +XCOLFILL4<13> VDD! VSS! / RM_IHPSG13_512x8_c2_2P_COLDRV13_FILL4C2 +XCOLFILL4<14> VDD! VSS! / RM_IHPSG13_512x8_c2_2P_COLDRV13_FILL4C2 +XCOLFILL4<15> VDD! VSS! / RM_IHPSG13_512x8_c2_2P_COLDRV13_FILL4C2 +XCOLFILL4<16> VDD! VSS! / RM_IHPSG13_512x8_c2_2P_COLDRV13_FILL4C2 +.ENDS diff --git a/flow/platforms/ihp-sg13g2/cdl/RM_IHPSG13_2P_64x32_c2.cdl b/flow/platforms/ihp-sg13g2/cdl/RM_IHPSG13_2P_64x32_c2.cdl new file mode 100644 index 0000000000..5cace98b85 --- /dev/null +++ b/flow/platforms/ihp-sg13g2/cdl/RM_IHPSG13_2P_64x32_c2.cdl @@ -0,0 +1,6389 @@ +* ------------------------------------------------------ +* +* Copyright 2023 IHP PDK Authors +* +* Licensed under the Apache License, Version 2.0 (the "License"); +* you may not use this file except in compliance with the License. +* You may obtain a copy of the License at +* +* https://www.apache.org/licenses/LICENSE-2.0 +* +* Unless required by applicable law or agreed to in writing, software +* distributed under the License is distributed on an "AS IS" BASIS, +* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +* See the License for the specific language governing permissions and +* limitations under the License. +* +* Generated on Thu Jun 12 11:08:49 2025 +* +* ------------------------------------------------------ + +.SUBCKT RM_IHPSG13_64x32_c2_1P_BITKIT_CORNER NW PW VDD VSS +.ENDS +.SUBCKT RM_IHPSG13_64x32_c2_1P_BITKIT_16x2_CORNER VDD_CORE VSS +XI16 VDD_CORE VSS VDD_CORE VSS / ++ RM_IHPSG13_64x32_c2_1P_BITKIT_CORNER +.ENDS +.SUBCKT RM_IHPSG13_64x32_c2_1P_BITKIT_EDGE_LR LWL NW PW VDD VSS +MN1 VSS LWL VSS VSS sg13_lv_nmos m=1 w=300.0n l=130.00n ng=1 nrd=0 nrs=0 +MN0 VSS net9 VSS VSS sg13_lv_nmos m=1 w=300.0n l=130.00n ng=1 nrd=0 nrs=0 +.ENDS +.SUBCKT RM_IHPSG13_64x32_c2_1P_BITKIT_16x2_EDGE_LR A_WL<15> A_WL<14> A_WL<13> A_WL<12> ++ A_WL<11> A_WL<10> A_WL<9> A_WL<8> A_WL<7> A_WL<6> A_WL<5> A_WL<4> A_WL<3> ++ A_WL<2> A_WL<1> A_WL<0> VDD_CORE VSS +XI0<15> A_WL<15> VDD_CORE VSS VDD_CORE VSS / ++ RM_IHPSG13_64x32_c2_1P_BITKIT_EDGE_LR +XI0<14> A_WL<14> VDD_CORE VSS VDD_CORE VSS / ++ RM_IHPSG13_64x32_c2_1P_BITKIT_EDGE_LR +XI0<13> A_WL<13> VDD_CORE VSS VDD_CORE VSS / ++ RM_IHPSG13_64x32_c2_1P_BITKIT_EDGE_LR +XI0<12> A_WL<12> VDD_CORE VSS VDD_CORE VSS / ++ RM_IHPSG13_64x32_c2_1P_BITKIT_EDGE_LR +XI0<11> A_WL<11> VDD_CORE VSS VDD_CORE VSS / ++ RM_IHPSG13_64x32_c2_1P_BITKIT_EDGE_LR +XI0<10> A_WL<10> VDD_CORE VSS VDD_CORE VSS / ++ RM_IHPSG13_64x32_c2_1P_BITKIT_EDGE_LR +XI0<9> A_WL<9> VDD_CORE VSS VDD_CORE VSS / ++ RM_IHPSG13_64x32_c2_1P_BITKIT_EDGE_LR +XI0<8> A_WL<8> VDD_CORE VSS VDD_CORE VSS / ++ RM_IHPSG13_64x32_c2_1P_BITKIT_EDGE_LR +XI0<7> A_WL<7> VDD_CORE VSS VDD_CORE VSS / ++ RM_IHPSG13_64x32_c2_1P_BITKIT_EDGE_LR +XI0<6> A_WL<6> VDD_CORE VSS VDD_CORE VSS / ++ RM_IHPSG13_64x32_c2_1P_BITKIT_EDGE_LR +XI0<5> A_WL<5> VDD_CORE VSS VDD_CORE VSS / ++ RM_IHPSG13_64x32_c2_1P_BITKIT_EDGE_LR +XI0<4> A_WL<4> VDD_CORE VSS VDD_CORE VSS / ++ RM_IHPSG13_64x32_c2_1P_BITKIT_EDGE_LR +XI0<3> A_WL<3> VDD_CORE VSS VDD_CORE VSS / ++ RM_IHPSG13_64x32_c2_1P_BITKIT_EDGE_LR +XI0<2> A_WL<2> VDD_CORE VSS VDD_CORE VSS / ++ RM_IHPSG13_64x32_c2_1P_BITKIT_EDGE_LR +XI0<1> A_WL<1> VDD_CORE VSS VDD_CORE VSS / ++ RM_IHPSG13_64x32_c2_1P_BITKIT_EDGE_LR +XI0<0> A_WL<0> VDD_CORE VSS VDD_CORE VSS / ++ RM_IHPSG13_64x32_c2_1P_BITKIT_EDGE_LR +.ENDS +.SUBCKT RM_IHPSG13_64x32_c2_1P_BITKIT_CELL BLC_BOT BLC_TOP BLT_BOT BLT_TOP LWL NW PW ++ RWL VDD VSS +MN0 NC NT VSS PW sg13_lv_nmos m=1 w=300.0n l=130.00n ng=1 nrd=0 nrs=0 +MN1 NT NC VSS PW sg13_lv_nmos m=1 w=300.0n l=130.00n ng=1 nrd=0 nrs=0 +MN3 NC RWL BLC_TOP PW sg13_lv_nmos m=1 w=300.0n l=130.00n ng=1 nrd=0 nrs=0 +MN2 BLT_BOT LWL NT PW sg13_lv_nmos m=1 w=300.0n l=130.00n ng=1 nrd=0 nrs=0 +MP1 NT NC VDD NW sg13_lv_pmos m=1 w=150.00n l=130.00n ng=1 nrd=0 nrs=0 +MP0 NC NT VDD NW sg13_lv_pmos m=1 w=150.00n l=130.00n ng=1 nrd=0 nrs=0 +R1 BLC_BOT BLC_TOP lvsres w=2.6e-07 l=6e-07 +R0 BLT_BOT BLT_TOP lvsres w=2.6e-07 l=6e-07 +R2 RWL LWL lvsres w=2.6e-07 l=6e-07 +.ENDS +.SUBCKT RM_IHPSG13_64x32_c2_1P_BITKIT_16x2_SRAM A_BLC_BOT<1> A_BLC_BOT<0> A_BLC_TOP<1> ++ A_BLC_TOP<0> A_BLT_BOT<1> A_BLT_BOT<0> A_BLT_TOP<1> A_BLT_TOP<0> A_LWL<15> ++ A_LWL<14> A_LWL<13> A_LWL<12> A_LWL<11> A_LWL<10> A_LWL<9> A_LWL<8> A_LWL<7> ++ A_LWL<6> A_LWL<5> A_LWL<4> A_LWL<3> A_LWL<2> A_LWL<1> A_LWL<0> A_RWL<15> ++ A_RWL<14> A_RWL<13> A_RWL<12> A_RWL<11> A_RWL<10> A_RWL<9> A_RWL<8> A_RWL<7> ++ A_RWL<6> A_RWL<5> A_RWL<4> A_RWL<3> A_RWL<2> A_RWL<1> A_RWL<0> VDD_CORE ++ VSS +XCELL<31> A_BLC_TOP<1> A_RBLC<15> A_BLT_TOP<1> A_RBLT<15> A_RWL<15> ++ VDD_CORE VSS A_XWL<15> VDD_CORE VSS / ++ RM_IHPSG13_64x32_c2_1P_BITKIT_CELL +XCELL<30> A_RBLC<14> A_RBLC<15> A_RBLT<14> A_RBLT<15> A_RWL<14> VDD_CORE ++ VSS A_XWL<14> VDD_CORE VSS / RM_IHPSG13_64x32_c2_1P_BITKIT_CELL +XCELL<29> A_RBLC<14> A_RBLC<13> A_RBLT<14> A_RBLT<13> A_RWL<13> VDD_CORE ++ VSS A_XWL<13> VDD_CORE VSS / RM_IHPSG13_64x32_c2_1P_BITKIT_CELL +XCELL<28> A_RBLC<12> A_RBLC<13> A_RBLT<12> A_RBLT<13> A_RWL<12> VDD_CORE ++ VSS A_XWL<12> VDD_CORE VSS / RM_IHPSG13_64x32_c2_1P_BITKIT_CELL +XCELL<27> A_RBLC<12> A_RBLC<11> A_RBLT<12> A_RBLT<11> A_RWL<11> VDD_CORE ++ VSS A_XWL<11> VDD_CORE VSS / RM_IHPSG13_64x32_c2_1P_BITKIT_CELL +XCELL<26> A_RBLC<10> A_RBLC<11> A_RBLT<10> A_RBLT<11> A_RWL<10> VDD_CORE ++ VSS A_XWL<10> VDD_CORE VSS / RM_IHPSG13_64x32_c2_1P_BITKIT_CELL +XCELL<25> A_RBLC<10> A_RBLC<9> A_RBLT<10> A_RBLT<9> A_RWL<9> VDD_CORE ++ VSS A_XWL<9> VDD_CORE VSS / RM_IHPSG13_64x32_c2_1P_BITKIT_CELL +XCELL<24> A_RBLC<8> A_RBLC<9> A_RBLT<8> A_RBLT<9> A_RWL<8> VDD_CORE ++ VSS A_XWL<8> VDD_CORE VSS / RM_IHPSG13_64x32_c2_1P_BITKIT_CELL +XCELL<23> A_RBLC<8> A_RBLC<7> A_RBLT<8> A_RBLT<7> A_RWL<7> VDD_CORE ++ VSS A_XWL<7> VDD_CORE VSS / RM_IHPSG13_64x32_c2_1P_BITKIT_CELL +XCELL<22> A_RBLC<6> A_RBLC<7> A_RBLT<6> A_RBLT<7> A_RWL<6> VDD_CORE ++ VSS A_XWL<6> VDD_CORE VSS / RM_IHPSG13_64x32_c2_1P_BITKIT_CELL +XCELL<21> A_RBLC<6> A_RBLC<5> A_RBLT<6> A_RBLT<5> A_RWL<5> VDD_CORE ++ VSS A_XWL<5> VDD_CORE VSS / RM_IHPSG13_64x32_c2_1P_BITKIT_CELL +XCELL<20> A_RBLC<4> A_RBLC<5> A_RBLT<4> A_RBLT<5> A_RWL<4> VDD_CORE ++ VSS A_XWL<4> VDD_CORE VSS / RM_IHPSG13_64x32_c2_1P_BITKIT_CELL +XCELL<19> A_RBLC<4> A_RBLC<3> A_RBLT<4> A_RBLT<3> A_RWL<3> VDD_CORE ++ VSS A_XWL<3> VDD_CORE VSS / RM_IHPSG13_64x32_c2_1P_BITKIT_CELL +XCELL<18> A_RBLC<2> A_RBLC<3> A_RBLT<2> A_RBLT<3> A_RWL<2> VDD_CORE ++ VSS A_XWL<2> VDD_CORE VSS / RM_IHPSG13_64x32_c2_1P_BITKIT_CELL +XCELL<17> A_RBLC<2> A_RBLC<1> A_RBLT<2> A_RBLT<1> A_RWL<1> VDD_CORE ++ VSS A_XWL<1> VDD_CORE VSS / RM_IHPSG13_64x32_c2_1P_BITKIT_CELL +XCELL<16> A_BLC_BOT<1> A_RBLC<1> A_BLT_BOT<1> A_RBLT<1> A_RWL<0> VDD_CORE ++ VSS A_XWL<0> VDD_CORE VSS / RM_IHPSG13_64x32_c2_1P_BITKIT_CELL +XCELL<15> A_BLC_TOP<0> A_LBLC<15> A_BLT_TOP<0> A_LBLT<15> A_LWL<15> ++ VDD_CORE VSS A_XWL<15> VDD_CORE VSS / ++ RM_IHPSG13_64x32_c2_1P_BITKIT_CELL +XCELL<14> A_LBLC<14> A_LBLC<15> A_LBLT<14> A_LBLT<15> A_LWL<14> VDD_CORE ++ VSS A_XWL<14> VDD_CORE VSS / RM_IHPSG13_64x32_c2_1P_BITKIT_CELL +XCELL<13> A_LBLC<14> A_LBLC<13> A_LBLT<14> A_LBLT<13> A_LWL<13> VDD_CORE ++ VSS A_XWL<13> VDD_CORE VSS / RM_IHPSG13_64x32_c2_1P_BITKIT_CELL +XCELL<12> A_LBLC<12> A_LBLC<13> A_LBLT<12> A_LBLT<13> A_LWL<12> VDD_CORE ++ VSS A_XWL<12> VDD_CORE VSS / RM_IHPSG13_64x32_c2_1P_BITKIT_CELL +XCELL<11> A_LBLC<12> A_LBLC<11> A_LBLT<12> A_LBLT<11> A_LWL<11> VDD_CORE ++ VSS A_XWL<11> VDD_CORE VSS / RM_IHPSG13_64x32_c2_1P_BITKIT_CELL +XCELL<10> A_LBLC<10> A_LBLC<11> A_LBLT<10> A_LBLT<11> A_LWL<10> VDD_CORE ++ VSS A_XWL<10> VDD_CORE VSS / RM_IHPSG13_64x32_c2_1P_BITKIT_CELL +XCELL<9> A_LBLC<10> A_LBLC<9> A_LBLT<10> A_LBLT<9> A_LWL<9> VDD_CORE ++ VSS A_XWL<9> VDD_CORE VSS / RM_IHPSG13_64x32_c2_1P_BITKIT_CELL +XCELL<8> A_LBLC<8> A_LBLC<9> A_LBLT<8> A_LBLT<9> A_LWL<8> VDD_CORE ++ VSS A_XWL<8> VDD_CORE VSS / RM_IHPSG13_64x32_c2_1P_BITKIT_CELL +XCELL<7> A_LBLC<8> A_LBLC<7> A_LBLT<8> A_LBLT<7> A_LWL<7> VDD_CORE ++ VSS A_XWL<7> VDD_CORE VSS / RM_IHPSG13_64x32_c2_1P_BITKIT_CELL +XCELL<6> A_LBLC<6> A_LBLC<7> A_LBLT<6> A_LBLT<7> A_LWL<6> VDD_CORE ++ VSS A_XWL<6> VDD_CORE VSS / RM_IHPSG13_64x32_c2_1P_BITKIT_CELL +XCELL<5> A_LBLC<6> A_LBLC<5> A_LBLT<6> A_LBLT<5> A_LWL<5> VDD_CORE ++ VSS A_XWL<5> VDD_CORE VSS / RM_IHPSG13_64x32_c2_1P_BITKIT_CELL +XCELL<4> A_LBLC<4> A_LBLC<5> A_LBLT<4> A_LBLT<5> A_LWL<4> VDD_CORE ++ VSS A_XWL<4> VDD_CORE VSS / RM_IHPSG13_64x32_c2_1P_BITKIT_CELL +XCELL<3> A_LBLC<4> A_LBLC<3> A_LBLT<4> A_LBLT<3> A_LWL<3> VDD_CORE ++ VSS A_XWL<3> VDD_CORE VSS / RM_IHPSG13_64x32_c2_1P_BITKIT_CELL +XCELL<2> A_LBLC<2> A_LBLC<3> A_LBLT<2> A_LBLT<3> A_LWL<2> VDD_CORE ++ VSS A_XWL<2> VDD_CORE VSS / RM_IHPSG13_64x32_c2_1P_BITKIT_CELL +XCELL<1> A_LBLC<2> A_LBLC<1> A_LBLT<2> A_LBLT<1> A_LWL<1> VDD_CORE ++ VSS A_XWL<1> VDD_CORE VSS / RM_IHPSG13_64x32_c2_1P_BITKIT_CELL +XCELL<0> A_BLC_BOT<0> A_LBLC<1> A_BLT_BOT<0> A_LBLT<1> A_LWL<0> VDD_CORE ++ VSS A_XWL<0> VDD_CORE VSS / RM_IHPSG13_64x32_c2_1P_BITKIT_CELL +.ENDS +.SUBCKT RM_IHPSG13_64x32_c2_1P_BITKIT_EDGE_TB BLC BLT NW PW VDD VSS +.ENDS +.SUBCKT RM_IHPSG13_64x32_c2_1P_BITKIT_16x2_EDGE_TB A_BLC<1> A_BLC<0> A_BLT<1> A_BLT<0> ++ VDD_CORE VSS +XEDGE<1> A_BLC<1> A_BLT<1> VDD_CORE VSS VDD_CORE VSS ++ / RM_IHPSG13_64x32_c2_1P_BITKIT_EDGE_TB +XEDGE<0> A_BLC<0> A_BLT<0> VDD_CORE VSS VDD_CORE VSS ++ / RM_IHPSG13_64x32_c2_1P_BITKIT_EDGE_TB +.ENDS + +.SUBCKT RSC_IHPSG13_CBUFX4 A Z VDD VSS +MN0 net9 A VSS VSS sg13_lv_nmos m=1 w=705.000n l=130.00n ng=1 nrd=0 ++ nrs=0 +MN1 Z net9 VSS VSS sg13_lv_nmos m=1 w=1.41u l=130.00n ng=2 nrd=0 nrs=0 +MP0 net9 A VDD VDD sg13_lv_pmos m=1 w=1.62u l=130.00n ng=1 nrd=0 nrs=0 +MP1 Z net9 VDD VDD sg13_lv_pmos m=1 w=3.24u l=130.00n ng=2 nrd=0 nrs=0 +.ENDS +.SUBCKT RM_IHPSG13_64x32_c2_1P_COLDRV13X4 ADDR_COL_I<1> ADDR_COL_I<0> ADDR_COL_O<1> ++ ADDR_COL_O<0> ADDR_DEC_I<7> ADDR_DEC_I<6> ADDR_DEC_I<5> ADDR_DEC_I<4> ++ ADDR_DEC_I<3> ADDR_DEC_I<2> ADDR_DEC_I<1> ADDR_DEC_I<0> ADDR_DEC_O<7> ++ ADDR_DEC_O<6> ADDR_DEC_O<5> ADDR_DEC_O<4> ADDR_DEC_O<3> ADDR_DEC_O<2> ++ ADDR_DEC_O<1> ADDR_DEC_O<0> DCLK_I DCLK_O RCLK_I RCLK_O WCLK_I WCLK_O ++ VDD VSS +XADDR_COL_DRV<1> ADDR_COL_I<1> ADDR_COL_O<1> VDD VSS / ++ RSC_IHPSG13_CBUFX4 +XADDR_COL_DRV<0> ADDR_COL_I<0> ADDR_COL_O<0> VDD VSS / ++ RSC_IHPSG13_CBUFX4 +XADDR_DEC_DRV<7> ADDR_DEC_I<7> ADDR_DEC_O<7> VDD VSS / ++ RSC_IHPSG13_CBUFX4 +XADDR_DEC_DRV<6> ADDR_DEC_I<6> ADDR_DEC_O<6> VDD VSS / ++ RSC_IHPSG13_CBUFX4 +XADDR_DEC_DRV<5> ADDR_DEC_I<5> ADDR_DEC_O<5> VDD VSS / ++ RSC_IHPSG13_CBUFX4 +XADDR_DEC_DRV<4> ADDR_DEC_I<4> ADDR_DEC_O<4> VDD VSS / ++ RSC_IHPSG13_CBUFX4 +XADDR_DEC_DRV<3> ADDR_DEC_I<3> ADDR_DEC_O<3> VDD VSS / ++ RSC_IHPSG13_CBUFX4 +XADDR_DEC_DRV<2> ADDR_DEC_I<2> ADDR_DEC_O<2> VDD VSS / ++ RSC_IHPSG13_CBUFX4 +XADDR_DEC_DRV<1> ADDR_DEC_I<1> ADDR_DEC_O<1> VDD VSS / ++ RSC_IHPSG13_CBUFX4 +XADDR_DEC_DRV<0> ADDR_DEC_I<0> ADDR_DEC_O<0> VDD VSS / ++ RSC_IHPSG13_CBUFX4 +XDCLK_DRV DCLK_I DCLK_O VDD VSS / RSC_IHPSG13_CBUFX4 +XRCLK_DRV RCLK_I RCLK_O VDD VSS / RSC_IHPSG13_CBUFX4 +XWCLK_DRV WCLK_I WCLK_O VDD VSS / RSC_IHPSG13_CBUFX4 +.ENDS +.SUBCKT RSC_IHPSG13_WLDRVX4 A Z VDD VSS +MN1 Z net6 VSS VSS sg13_lv_nmos m=1 w=705.000n l=130.00n ng=1 nrd=0 ++ nrs=0 +MN0 net6 A VSS VSS sg13_lv_nmos m=1 w=900.0n l=130.00n ng=1 nrd=0 nrs=0 +MP1 Z net6 VDD VDD sg13_lv_pmos m=1 w=3.24u l=130.00n ng=2 nrd=0 nrs=0 +MP0 net6 A VDD VDD sg13_lv_pmos m=1 w=900.0n l=130.00n ng=1 nrd=0 nrs=0 +.ENDS +.SUBCKT RM_IHPSG13_64x32_c2_1P_WLDRV16X4 A<15> A<14> A<13> A<12> A<11> A<10> A<9> A<8> ++ A<7> A<6> A<5> A<4> A<3> A<2> A<1> A<0> Z<15> Z<14> Z<13> Z<12> Z<11> Z<10> ++ Z<9> Z<8> Z<7> Z<6> Z<5> Z<4> Z<3> Z<2> Z<1> Z<0> VDD VSS +XBUF<15> A<15> Z<15> VDD VSS / RSC_IHPSG13_WLDRVX4 +XBUF<14> A<14> Z<14> VDD VSS / RSC_IHPSG13_WLDRVX4 +XBUF<13> A<13> Z<13> VDD VSS / RSC_IHPSG13_WLDRVX4 +XBUF<12> A<12> Z<12> VDD VSS / RSC_IHPSG13_WLDRVX4 +XBUF<11> A<11> Z<11> VDD VSS / RSC_IHPSG13_WLDRVX4 +XBUF<10> A<10> Z<10> VDD VSS / RSC_IHPSG13_WLDRVX4 +XBUF<9> A<9> Z<9> VDD VSS / RSC_IHPSG13_WLDRVX4 +XBUF<8> A<8> Z<8> VDD VSS / RSC_IHPSG13_WLDRVX4 +XBUF<7> A<7> Z<7> VDD VSS / RSC_IHPSG13_WLDRVX4 +XBUF<6> A<6> Z<6> VDD VSS / RSC_IHPSG13_WLDRVX4 +XBUF<5> A<5> Z<5> VDD VSS / RSC_IHPSG13_WLDRVX4 +XBUF<4> A<4> Z<4> VDD VSS / RSC_IHPSG13_WLDRVX4 +XBUF<3> A<3> Z<3> VDD VSS / RSC_IHPSG13_WLDRVX4 +XBUF<2> A<2> Z<2> VDD VSS / RSC_IHPSG13_WLDRVX4 +XBUF<1> A<1> Z<1> VDD VSS / RSC_IHPSG13_WLDRVX4 +XBUF<0> A<0> Z<0> VDD VSS / RSC_IHPSG13_WLDRVX4 +.ENDS +.SUBCKT RSC_IHPSG13_FILLCAP8 VDD VSS +MN0 vss_r vdd_r VSS VSS sg13_lv_nmos m=1 w=4.98u l=130.00n ng=6 nrd=0 ++ nrs=0 +MP0 vdd_r vss_r VDD VDD sg13_lv_pmos m=1 w=6.48u l=385.000n ng=4 nrd=0 ++ nrs=0 +.ENDS +.SUBCKT RSC_IHPSG13_LHPQX2 CP D Q VDD VSS +MN3 QIN CPN net14 VSS sg13_lv_nmos m=1 w=480.00n l=130.00n ng=1 nrd=0 nrs=0 +MN2 net14 net10 VSS VSS sg13_lv_nmos m=1 w=480.00n l=130.00n ng=1 ++ nrd=0 nrs=0 +MN5 net21 D VSS VSS sg13_lv_nmos m=1 w=870.00n l=130.00n ng=1 nrd=0 ++ nrs=0 +MN6 QIN CP net21 VSS sg13_lv_nmos m=1 w=870.00n l=130.00n ng=1 nrd=0 nrs=0 +MN1 net10 QIN VSS VSS sg13_lv_nmos m=1 w=480.00n l=130.00n ng=1 nrd=0 ++ nrs=0 +MN0 CPN CP VSS VSS sg13_lv_nmos m=1 w=480.00n l=130.00n ng=1 nrd=0 ++ nrs=0 +MN4 Q QIN VSS VSS sg13_lv_nmos m=1 w=980.00n l=130.00n ng=1 nrd=0 nrs=0 +MP2 QIN CP net16 VDD sg13_lv_pmos m=1 w=480.00n l=130.00n ng=1 nrd=0 nrs=0 +MP0 CPN CP VDD VDD sg13_lv_pmos m=1 w=480.00n l=130.00n ng=1 nrd=0 ++ nrs=0 +MP4 Q QIN VDD VDD sg13_lv_pmos m=1 w=1.62u l=130.00n ng=1 nrd=0 nrs=0 +MP3 net10 QIN VDD VDD sg13_lv_pmos m=1 w=480.00n l=130.00n ng=1 nrd=0 ++ nrs=0 +MP1 net16 net10 VDD VDD sg13_lv_pmos m=1 w=480.00n l=130.00n ng=1 ++ nrd=0 nrs=0 +MP6 QIN CPN net20 VDD sg13_lv_pmos m=1 w=975.000n l=130.00n ng=1 nrd=0 ++ nrs=0 +MP5 net20 D VDD VDD sg13_lv_pmos m=1 w=975.000n l=130.00n ng=1 nrd=0 ++ nrs=0 +.ENDS +.SUBCKT RSC_IHPSG13_NAND2X2 A B Z VDD VSS +MP1 Z B VDD VDD sg13_lv_pmos m=1 w=1.62u l=130.00n ng=1 nrd=0 nrs=0 +MP0 Z A VDD VDD sg13_lv_pmos m=1 w=1.62u l=130.00n ng=1 nrd=0 nrs=0 +MN0 Z B net7 VSS sg13_lv_nmos m=1 w=980.00n l=130.00n ng=1 nrd=0 nrs=0 +MN1 net7 A VSS VSS sg13_lv_nmos m=1 w=980.00n l=130.00n ng=1 nrd=0 ++ nrs=0 +.ENDS +.SUBCKT RSC_IHPSG13_CINVX4 A Z VDD VSS +MN0 Z A VSS VSS sg13_lv_nmos m=1 w=1.41u l=130.00n ng=2 nrd=0 nrs=0 +MP0 Z A VDD VDD sg13_lv_pmos m=1 w=3.24u l=130.00n ng=2 nrd=0 nrs=0 +.ENDS +.SUBCKT RSC_IHPSG13_CINVX2 A Z VDD VSS +MN0 Z A VSS VSS sg13_lv_nmos m=1 w=705.000n l=130.00n ng=1 nrd=0 nrs=0 +MP0 Z A VDD VDD sg13_lv_pmos m=1 w=1.62u l=130.00n ng=1 nrd=0 nrs=0 +.ENDS +.SUBCKT RSC_IHPSG13_INVX2 A Z VDD VSS +MN0 Z A VSS VSS sg13_lv_nmos m=1 w=980.00n l=130.00n ng=1 nrd=0 nrs=0 +MP0 Z A VDD VDD sg13_lv_pmos m=1 w=1.62u l=130.00n ng=1 nrd=0 nrs=0 +.ENDS +.SUBCKT RSC_IHPSG13_NAND3X2 A B C Z VDD VSS +MP2 Z A VDD VDD sg13_lv_pmos m=1 w=1.62u l=130.00n ng=1 nrd=0 nrs=0 +MP1 Z B VDD VDD sg13_lv_pmos m=1 w=1.62u l=130.00n ng=1 nrd=0 nrs=0 +MP0 Z C VDD VDD sg13_lv_pmos m=1 w=1.62u l=130.00n ng=1 nrd=0 nrs=0 +MN1 net12 B net16 VSS sg13_lv_nmos m=1 w=980.00n l=130.00n ng=1 nrd=0 nrs=0 +MN0 Z C net12 VSS sg13_lv_nmos m=1 w=980.00n l=130.00n ng=1 nrd=0 nrs=0 +MN2 net16 A VSS VSS sg13_lv_nmos m=1 w=980.00n l=130.00n ng=1 nrd=0 ++ nrs=0 +.ENDS +.SUBCKT RSC_IHPSG13_NOR3X2 A B C Z VDD VSS +MP0 net13 A VDD VDD sg13_lv_pmos m=1 w=1.62u l=130.00n ng=1 nrd=0 nrs=0 +MP2 Z C net10 VDD sg13_lv_pmos m=1 w=1.62u l=130.00n ng=1 nrd=0 nrs=0 +MP1 net10 B net13 VDD sg13_lv_pmos m=1 w=1.62u l=130.00n ng=1 nrd=0 nrs=0 +MN1 Z B VSS VSS sg13_lv_nmos m=1 w=875.000n l=130.00n ng=1 nrd=0 nrs=0 +MN0 Z C VSS VSS sg13_lv_nmos m=1 w=875.000n l=130.00n ng=1 nrd=0 nrs=0 +MN2 Z A VSS VSS sg13_lv_nmos m=1 w=875.000n l=130.00n ng=1 nrd=0 nrs=0 +.ENDS +.SUBCKT RSC_IHPSG13_FILLCAP4 VDD VSS +MN0 vss_r vdd_r VSS VSS sg13_lv_nmos m=1 w=2.49u l=130.00n ng=3 nrd=0 ++ nrs=0 +MP0 vdd_r vss_r VDD VDD sg13_lv_pmos m=1 w=3.24u l=385.000n ng=2 nrd=0 ++ nrs=0 +.ENDS +.SUBCKT RSC_IHPSG13_MET2RES A B +R0 B A lvsres w=2.6e-07 l=6e-07 +.ENDS +.SUBCKT RM_IHPSG13_64x32_c2_1P_DEC04 ADDR<3> ADDR<2> ADDR<1> ADDR<0> CS ECLK_H_BOT ++ ECLK_H_TOP ECLK_L_BOT ECLK_L_TOP WL<15> WL<14> WL<13> WL<12> WL<11> WL<10> ++ WL<9> WL<8> WL<7> WL<6> WL<5> WL<4> WL<3> WL<2> WL<1> WL<0> VDD VSS +XLATCH<3> CS ADDR<3> PADR<3> VDD VSS / RSC_IHPSG13_LHPQX2 +XLATCH<2> CS ADDR<2> PADR<2> VDD VSS / RSC_IHPSG13_LHPQX2 +XLATCH<1> CS ADDR<1> PADR<1> VDD VSS / RSC_IHPSG13_LHPQX2 +XLATCH<0> CS ADDR<0> PADR<0> VDD VSS / RSC_IHPSG13_LHPQX2 +XI0<3> PADR<1> PADR<0> sel01<3> VDD VSS / RSC_IHPSG13_NAND2X2 +XI0<2> PADR<1> NADR<0> sel01<2> VDD VSS / RSC_IHPSG13_NAND2X2 +XI0<1> NADR<1> PADR<0> sel01<1> VDD VSS / RSC_IHPSG13_NAND2X2 +XI0<0> NADR<1> NADR<0> sel01<0> VDD VSS / RSC_IHPSG13_NAND2X2 +XI4 ECLK_L_BOT EN VDD VSS / RSC_IHPSG13_CINVX4 +XI5 ECLK_H_BOT ECLK_L_BOT VDD VSS / RSC_IHPSG13_CINVX2 +XI3<3> PADR<3> NADR<3> VDD VSS / RSC_IHPSG13_INVX2 +XI3<2> PADR<2> NADR<2> VDD VSS / RSC_IHPSG13_INVX2 +XI3<1> PADR<1> NADR<1> VDD VSS / RSC_IHPSG13_INVX2 +XI3<0> PADR<0> NADR<0> VDD VSS / RSC_IHPSG13_INVX2 +XI1<3> PADR<2> PADR<3> CS sel23<3> VDD VSS / RSC_IHPSG13_NAND3X2 +XI1<2> NADR<2> PADR<3> CS sel23<2> VDD VSS / RSC_IHPSG13_NAND3X2 +XI1<1> PADR<2> NADR<3> CS sel23<1> VDD VSS / RSC_IHPSG13_NAND3X2 +XI1<0> NADR<2> NADR<3> CS sel23<0> VDD VSS / RSC_IHPSG13_NAND3X2 +XI2<15> sel23<3> sel01<3> EN WL<15> VDD VSS / RSC_IHPSG13_NOR3X2 +XI2<14> sel23<3> sel01<2> EN WL<14> VDD VSS / RSC_IHPSG13_NOR3X2 +XI2<13> sel23<3> sel01<1> EN WL<13> VDD VSS / RSC_IHPSG13_NOR3X2 +XI2<12> sel23<3> sel01<0> EN WL<12> VDD VSS / RSC_IHPSG13_NOR3X2 +XI2<11> sel23<2> sel01<3> EN WL<11> VDD VSS / RSC_IHPSG13_NOR3X2 +XI2<10> sel23<2> sel01<2> EN WL<10> VDD VSS / RSC_IHPSG13_NOR3X2 +XI2<9> sel23<2> sel01<1> EN WL<9> VDD VSS / RSC_IHPSG13_NOR3X2 +XI2<8> sel23<2> sel01<0> EN WL<8> VDD VSS / RSC_IHPSG13_NOR3X2 +XI2<7> sel23<1> sel01<3> EN WL<7> VDD VSS / RSC_IHPSG13_NOR3X2 +XI2<6> sel23<1> sel01<2> EN WL<6> VDD VSS / RSC_IHPSG13_NOR3X2 +XI2<5> sel23<1> sel01<1> EN WL<5> VDD VSS / RSC_IHPSG13_NOR3X2 +XI2<4> sel23<1> sel01<0> EN WL<4> VDD VSS / RSC_IHPSG13_NOR3X2 +XI2<3> sel23<0> sel01<3> EN WL<3> VDD VSS / RSC_IHPSG13_NOR3X2 +XI2<2> sel23<0> sel01<2> EN WL<2> VDD VSS / RSC_IHPSG13_NOR3X2 +XI2<1> sel23<0> sel01<1> EN WL<1> VDD VSS / RSC_IHPSG13_NOR3X2 +XI2<0> sel23<0> sel01<0> EN WL<0> VDD VSS / RSC_IHPSG13_NOR3X2 +XCAPS4 VDD VSS / RSC_IHPSG13_FILLCAP4 +XI11 ECLK_L_BOT ECLK_L_TOP / RSC_IHPSG13_MET2RES +XR0 ECLK_H_BOT ECLK_H_TOP / RSC_IHPSG13_MET2RES +.ENDS +.SUBCKT RM_IHPSG13_64x32_c2_1P_ROWDEC4 ADDR_N_I<3> ADDR_N_I<2> ADDR_N_I<1> ADDR_N_I<0> ++ CS_I ECLK_I WL_O<15> WL_O<14> WL_O<13> WL_O<12> WL_O<11> WL_O<10> WL_O<9> ++ WL_O<8> WL_O<7> WL_O<6> WL_O<5> WL_O<4> WL_O<3> WL_O<2> WL_O<1> WL_O<0> ++ VDD VSS +XL2<8> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<7> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<6> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<5> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<4> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<3> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<2> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<1> VDD VSS / RSC_IHPSG13_FILLCAP8 +XSEL ADDR_N_I<3> ADDR_N_I<2> ADDR_N_I<1> ADDR_N_I<0> CS_I ECLK_I ECLK_H<1> ++ ECLK_B<0> ECLK_B<1> WL_O<15> WL_O<14> WL_O<13> WL_O<12> WL_O<11> WL_O<10> ++ WL_O<9> WL_O<8> WL_O<7> WL_O<6> WL_O<5> WL_O<4> WL_O<3> WL_O<2> WL_O<1> ++ WL_O<0> VDD VSS / RM_IHPSG13_64x32_c2_1P_DEC04 +.ENDS +.SUBCKT RSC_IHPSG13_CINVX8 A Z VDD VSS +MN0 Z A VSS VSS sg13_lv_nmos m=1 w=2.82u l=130.00n ng=4 nrd=0 nrs=0 +MP0 Z A VDD VDD sg13_lv_pmos m=1 w=6.48u l=130.00n ng=4 nrd=0 nrs=0 +.ENDS +.SUBCKT RSC_IHPSG13_DFNQMX2IX1 BE BI CN D QI QIN VDD VSS +MN15 net026 BI VSS VSS sg13_lv_nmos m=1 w=560.00n l=130.00n ng=1 nrd=0 ++ nrs=0 +MN14 MXI_OUT BE net026 VSS sg13_lv_nmos m=1 w=560.00n l=130.00n ng=1 nrd=0 ++ nrs=0 +MN1 net025 D VSS VSS sg13_lv_nmos m=1 w=560.00n l=130.00n ng=1 nrd=0 ++ nrs=0 +MN0 MXI_OUT BEN net025 VSS sg13_lv_nmos m=1 w=560.00n l=130.00n ng=1 nrd=0 ++ nrs=0 +MN10 QI CNN net21 VSS sg13_lv_nmos m=1 w=850.00n l=130.00n ng=1 nrd=0 nrs=0 +MN11 net21 QI_MS VSS VSS sg13_lv_nmos m=1 w=850.00n l=130.00n ng=1 ++ nrd=0 nrs=0 +MN7 net30 QI_MS VSS VSS sg13_lv_nmos m=1 w=480.00n l=130.00n ng=1 ++ nrd=0 nrs=0 +MN6 QIN_MS CNN net30 VSS sg13_lv_nmos m=1 w=480.00n l=130.00n ng=1 nrd=0 ++ nrs=0 +MN3 QI_MS QIN_MS VSS VSS sg13_lv_nmos m=1 w=480.00n l=130.00n ng=1 ++ nrd=0 nrs=0 +MN12 CNN CN VSS VSS sg13_lv_nmos m=1 w=495.000n l=130.00n ng=1 nrd=0 ++ nrs=0 +MN9 net37 MXI_OUT VSS VSS sg13_lv_nmos m=1 w=870.00n l=130.00n ng=1 ++ nrd=0 nrs=0 +MN8 QIN_MS CN net37 VSS sg13_lv_nmos m=1 w=870.00n l=130.00n ng=1 nrd=0 ++ nrs=0 +MN5 QI CN net25 VSS sg13_lv_nmos m=1 w=480.00n l=130.00n ng=1 nrd=0 nrs=0 +MN4 net25 QIN VSS VSS sg13_lv_nmos m=1 w=480.00n l=130.00n ng=1 nrd=0 ++ nrs=0 +MN2 QIN QI VSS VSS sg13_lv_nmos m=1 w=480.00n l=130.00n ng=1 nrd=0 ++ nrs=0 +MN13 BEN BE VSS VSS sg13_lv_nmos m=1 w=560.00n l=130.00n ng=1 nrd=0 ++ nrs=0 +MP15 MXI_OUT BEN net027 VDD sg13_lv_pmos m=1 w=985.000n l=130.00n ng=1 ++ nrd=0 nrs=0 +MP14 net027 BI VDD VDD sg13_lv_pmos m=1 w=985.000n l=130.00n ng=1 ++ nrd=0 nrs=0 +MP1 MXI_OUT BE net024 VDD sg13_lv_pmos m=1 w=985.000n l=130.00n ng=1 nrd=0 ++ nrs=0 +MP0 net024 D VDD VDD sg13_lv_pmos m=1 w=985.000n l=130.00n ng=1 nrd=0 ++ nrs=0 +MP13 BEN BE VDD VDD sg13_lv_pmos m=1 w=645.000n l=130.00n ng=1 nrd=0 ++ nrs=0 +MP6 QI_MS QIN_MS VDD VDD sg13_lv_pmos m=1 w=480.00n l=130.00n ng=1 ++ nrd=0 nrs=0 +MP3 QI CNN net27 VDD sg13_lv_pmos m=1 w=480.00n l=130.00n ng=1 nrd=0 nrs=0 +MP2 net27 QIN VDD VDD sg13_lv_pmos m=1 w=480.00n l=130.00n ng=1 nrd=0 ++ nrs=0 +MP10 net36 MXI_OUT VDD VDD sg13_lv_pmos m=1 w=975.000n l=130.00n ng=1 ++ nrd=0 nrs=0 +MP11 QIN_MS CNN net36 VDD sg13_lv_pmos m=1 w=975.000n l=130.00n ng=1 nrd=0 ++ nrs=0 +MP4 net32 QI_MS VDD VDD sg13_lv_pmos m=1 w=480.00n l=130.00n ng=1 ++ nrd=0 nrs=0 +MP5 QIN_MS CN net32 VDD sg13_lv_pmos m=1 w=480.00n l=130.00n ng=1 nrd=0 ++ nrs=0 +MP7 QIN QI VDD VDD sg13_lv_pmos m=1 w=480.00n l=130.00n ng=1 nrd=0 ++ nrs=0 +MP12 CNN CN VDD VDD sg13_lv_pmos m=1 w=480.00n l=130.00n ng=1 nrd=0 ++ nrs=0 +MP9 QI CN net19 VDD sg13_lv_pmos m=1 w=990.00n l=130.00n ng=1 nrd=0 nrs=0 +MP8 net19 QI_MS VDD VDD sg13_lv_pmos m=1 w=990.00n l=130.00n ng=1 ++ nrd=0 nrs=0 +.ENDS +.SUBCKT RM_IHPSG13_64x32_c2_1P_ROWREG4 ACLK_N_I ADDR_I<3> ADDR_I<2> ADDR_I<1> ADDR_I<0> ++ ADDR_N_O<3> ADDR_N_O<2> ADDR_N_O<1> ADDR_N_O<0> BIST_ADDR_I<3> ++ BIST_ADDR_I<2> BIST_ADDR_I<1> BIST_ADDR_I<0> BIST_EN_I VDD VSS +XINV<3> q_int<3> qn_int<3> VDD VSS / RSC_IHPSG13_CINVX2 +XINV<2> q_int<2> qn_int<2> VDD VSS / RSC_IHPSG13_CINVX2 +XINV<1> q_int<1> qn_int<1> VDD VSS / RSC_IHPSG13_CINVX2 +XINV<0> q_int<0> qn_int<0> VDD VSS / RSC_IHPSG13_CINVX2 +XDRV<3> qn_int<3> ADDR_N_O<3> VDD VSS / RSC_IHPSG13_CINVX8 +XDRV<2> qn_int<2> ADDR_N_O<2> VDD VSS / RSC_IHPSG13_CINVX8 +XDRV<1> qn_int<1> ADDR_N_O<1> VDD VSS / RSC_IHPSG13_CINVX8 +XDRV<0> qn_int<0> ADDR_N_O<0> VDD VSS / RSC_IHPSG13_CINVX8 +XDFF<3> BIST_EN_I BIST_ADDR_I<3> ACLK_N_I ADDR_I<3> q_int<3> net2<0> VDD ++ VSS / RSC_IHPSG13_DFNQMX2IX1 +XDFF<2> BIST_EN_I BIST_ADDR_I<2> ACLK_N_I ADDR_I<2> q_int<2> net2<1> VDD ++ VSS / RSC_IHPSG13_DFNQMX2IX1 +XDFF<1> BIST_EN_I BIST_ADDR_I<1> ACLK_N_I ADDR_I<1> q_int<1> net2<2> VDD ++ VSS / RSC_IHPSG13_DFNQMX2IX1 +XDFF<0> BIST_EN_I BIST_ADDR_I<0> ACLK_N_I ADDR_I<0> q_int<0> net2<3> VDD ++ VSS / RSC_IHPSG13_DFNQMX2IX1 +XI11<20> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI11<19> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI11<18> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI11<17> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI11<16> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI11<15> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI11<14> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI11<13> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI11<12> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI11<11> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI11<10> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI11<9> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI11<8> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI11<7> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI11<6> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI11<5> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI11<4> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI11<3> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI11<2> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI11<1> VDD VSS / RSC_IHPSG13_FILLCAP8 +.ENDS +.SUBCKT RSC_IHPSG13_CDLYX1 A Z VDD VSS +MN1 net010 net032 VSS VSS sg13_lv_nmos m=1 w=300.0n l=160.00n ng=1 ++ nrd=0 nrs=0 +MN2 net032 A net014 VSS sg13_lv_nmos m=1 w=300.0n l=160.00n ng=1 nrd=0 ++ nrs=0 +MN0 Z net032 net010 VSS sg13_lv_nmos m=1 w=300.0n l=160.00n ng=1 nrd=0 ++ nrs=0 +MN3 net014 A VSS VSS sg13_lv_nmos m=1 w=300.0n l=160.00n ng=1 nrd=0 ++ nrs=0 +MP1 Z net032 net07 VDD sg13_lv_pmos m=1 w=720.00n l=160.00n ng=1 nrd=0 ++ nrs=0 +MP3 net011 A VDD VDD sg13_lv_pmos m=1 w=720.00n l=160.00n ng=1 nrd=0 ++ nrs=0 +MP0 net07 net032 VDD VDD sg13_lv_pmos m=1 w=720.00n l=160.00n ng=1 ++ nrd=0 nrs=0 +MP2 net032 A net011 VDD sg13_lv_pmos m=1 w=720.00n l=160.00n ng=1 nrd=0 ++ nrs=0 +.ENDS +.SUBCKT RSC_IHPSG13_CDLYX1_DUMMY A Z VDD VSS +MN0 vss_r vdd_r VSS VSS sg13_lv_nmos m=1 w=2.49u l=300.0n ng=3 nrd=0 ++ nrs=0 +MP0 vdd_r vss_r VDD VDD sg13_lv_pmos m=1 w=3.24u l=640.00n ng=2 nrd=0 ++ nrs=0 +R0 Z A lvsres w=2.6e-07 l=6e-07 +.ENDS + +.SUBCKT RSC_IHPSG13_MX2IX1 A0 A1 S ZN VDD VSS +MP4 SN S VDD VDD sg13_lv_pmos m=1 w=645.000n l=130.00n ng=1 nrd=0 nrs=0 +MP3 ZN SN net12 VDD sg13_lv_pmos m=1 w=985.000n l=130.00n ng=1 nrd=0 nrs=0 +MP2 net12 A1 VDD VDD sg13_lv_pmos m=1 w=985.000n l=130.00n ng=1 nrd=0 ++ nrs=0 +MP1 ZN S net17 VDD sg13_lv_pmos m=1 w=985.000n l=130.00n ng=1 nrd=0 nrs=0 +MP0 net17 A0 VDD VDD sg13_lv_pmos m=1 w=985.000n l=130.00n ng=1 nrd=0 ++ nrs=0 +MN5 SN S VSS VSS sg13_lv_nmos m=1 w=480.00n l=130.00n ng=1 nrd=0 nrs=0 +MN3 net13 A1 VSS VSS sg13_lv_nmos m=1 w=480.00n l=130.00n ng=1 nrd=0 ++ nrs=0 +MN2 ZN S net13 VSS sg13_lv_nmos m=1 w=480.00n l=130.00n ng=1 nrd=0 nrs=0 +MN1 net15 A0 VSS VSS sg13_lv_nmos m=1 w=480.00n l=130.00n ng=1 nrd=0 ++ nrs=0 +MN0 ZN SN net15 VSS sg13_lv_nmos m=1 w=480.00n l=130.00n ng=1 nrd=0 nrs=0 +.ENDS +.SUBCKT RM_IHPSG13_64x32_c2_1P_DLY_MUX A SEL Z VDD VSS +XI11 net4 Z VDD VSS / RSC_IHPSG13_CINVX2 +XI8 A D<3> SEL net4 VDD VSS / RSC_IHPSG13_MX2IX1 +XI20<3> D<2> D<3> VDD VSS / RSC_IHPSG13_CDLYX1 +XI20<2> D<1> D<2> VDD VSS / RSC_IHPSG13_CDLYX1 +XI20<1> A D<1> VDD VSS / RSC_IHPSG13_CDLYX1 +.ENDS +.SUBCKT RSC_IHPSG13_DFNQX2 CN D Q VDD VSS +MN0 Q QIN_SL VSS VSS sg13_lv_nmos m=1 w=980.00n l=130.00n ng=1 nrd=0 ++ nrs=0 +MN10 QIN_SL CNN net21 VSS sg13_lv_nmos m=1 w=850.00n l=130.00n ng=1 nrd=0 ++ nrs=0 +MN11 net21 QI_MS VSS VSS sg13_lv_nmos m=1 w=850.00n l=130.00n ng=1 ++ nrd=0 nrs=0 +MN7 net30 QI_MS VSS VSS sg13_lv_nmos m=1 w=480.00n l=130.00n ng=1 ++ nrd=0 nrs=0 +MN6 QIN_MS CNN net30 VSS sg13_lv_nmos m=1 w=480.00n l=130.00n ng=1 nrd=0 ++ nrs=0 +MN3 QI_MS QIN_MS VSS VSS sg13_lv_nmos m=1 w=480.00n l=130.00n ng=1 ++ nrd=0 nrs=0 +MN12 CNN CN VSS VSS sg13_lv_nmos m=1 w=495.000n l=130.00n ng=1 nrd=0 ++ nrs=0 +MN9 net37 D VSS VSS sg13_lv_nmos m=1 w=870.00n l=130.00n ng=1 nrd=0 ++ nrs=0 +MN8 QIN_MS CN net37 VSS sg13_lv_nmos m=1 w=870.00n l=130.00n ng=1 nrd=0 ++ nrs=0 +MN5 QIN_SL CN net25 VSS sg13_lv_nmos m=1 w=480.00n l=130.00n ng=1 nrd=0 ++ nrs=0 +MN4 net25 QI_SL VSS VSS sg13_lv_nmos m=1 w=480.00n l=130.00n ng=1 ++ nrd=0 nrs=0 +MN2 QI_SL QIN_SL VSS VSS sg13_lv_nmos m=1 w=480.00n l=130.00n ng=1 ++ nrd=0 nrs=0 +MP0 Q QIN_SL VDD VDD sg13_lv_pmos m=1 w=1.62u l=130.00n ng=1 nrd=0 ++ nrs=0 +MP6 QI_MS QIN_MS VDD VDD sg13_lv_pmos m=1 w=480.00n l=130.00n ng=1 ++ nrd=0 nrs=0 +MP3 QIN_SL CNN net27 VDD sg13_lv_pmos m=1 w=480.00n l=130.00n ng=1 nrd=0 ++ nrs=0 +MP2 net27 QI_SL VDD VDD sg13_lv_pmos m=1 w=480.00n l=130.00n ng=1 ++ nrd=0 nrs=0 +MP10 net36 D VDD VDD sg13_lv_pmos m=1 w=975.000n l=130.00n ng=1 nrd=0 ++ nrs=0 +MP11 QIN_MS CNN net36 VDD sg13_lv_pmos m=1 w=975.000n l=130.00n ng=1 nrd=0 ++ nrs=0 +MP4 net32 QI_MS VDD VDD sg13_lv_pmos m=1 w=480.00n l=130.00n ng=1 ++ nrd=0 nrs=0 +MP5 QIN_MS CN net32 VDD sg13_lv_pmos m=1 w=480.00n l=130.00n ng=1 nrd=0 ++ nrs=0 +MP7 QI_SL QIN_SL VDD VDD sg13_lv_pmos m=1 w=480.00n l=130.00n ng=1 ++ nrd=0 nrs=0 +MP12 CNN CN VDD VDD sg13_lv_pmos m=1 w=480.00n l=130.00n ng=1 nrd=0 ++ nrs=0 +MP9 QIN_SL CN net19 VDD sg13_lv_pmos m=1 w=990.00n l=130.00n ng=1 nrd=0 ++ nrs=0 +MP8 net19 QI_MS VDD VDD sg13_lv_pmos m=1 w=990.00n l=130.00n ng=1 ++ nrd=0 nrs=0 +.ENDS +.SUBCKT RSC_IHPSG13_CNAND2X2 A B Z VDD VSS +MN0 Z B net6 VSS sg13_lv_nmos m=1 w=980.00n l=130.00n ng=1 nrd=0 nrs=0 +MN1 net6 A VSS VSS sg13_lv_nmos m=1 w=980.00n l=130.00n ng=1 nrd=0 ++ nrs=0 +MP1 Z B VDD VDD sg13_lv_pmos m=1 w=1.62u l=130.00n ng=1 nrd=0 nrs=0 +MP0 Z A VDD VDD sg13_lv_pmos m=1 w=1.62u l=130.00n ng=1 nrd=0 nrs=0 +.ENDS +.SUBCKT RSC_IHPSG13_CGATEPX4 CP E Q VDD VSS +MN1 net08 QIN VSS VSS sg13_lv_nmos m=1 w=480.00n l=130.00n ng=1 nrd=0 ++ nrs=0 +MN2 net019 net08 VSS VSS sg13_lv_nmos m=1 w=480.00n l=130.00n ng=1 ++ nrd=0 nrs=0 +MN3 QIN CP net019 VSS sg13_lv_nmos m=1 w=480.00n l=130.00n ng=1 nrd=0 nrs=0 +MN6 Q net015 VSS VSS sg13_lv_nmos m=1 w=1.41u l=130.00n ng=2 nrd=0 ++ nrs=0 +MN5 net015 net08 net018 VSS sg13_lv_nmos m=1 w=980.00n l=130.00n ng=1 ++ nrd=0 nrs=0 +MN8 QIN CPN net023 VSS sg13_lv_nmos m=1 w=870.00n l=130.00n ng=1 nrd=0 ++ nrs=0 +MN7 net023 E VSS VSS sg13_lv_nmos m=1 w=870.00n l=130.00n ng=1 nrd=0 ++ nrs=0 +MN4 net018 CP VSS VSS sg13_lv_nmos m=1 w=980.00n l=130.00n ng=1 nrd=0 ++ nrs=0 +MN0 CPN CP VSS VSS sg13_lv_nmos m=1 w=500.0n l=130.00n ng=1 nrd=0 nrs=0 +MP3 net08 QIN VDD VDD sg13_lv_pmos m=1 w=480.00n l=130.00n ng=1 nrd=0 ++ nrs=0 +MP2 QIN CPN net017 VDD sg13_lv_pmos m=1 w=480.00n l=130.00n ng=1 nrd=0 ++ nrs=0 +MP1 net017 net08 VDD VDD sg13_lv_pmos m=1 w=480.00n l=130.00n ng=1 ++ nrd=0 nrs=0 +MP0 CPN CP VDD VDD sg13_lv_pmos m=1 w=500.0n l=130.00n ng=1 nrd=0 nrs=0 +MP8 QIN CP net024 VDD sg13_lv_pmos m=1 w=975.000n l=130.00n ng=1 nrd=0 ++ nrs=0 +MP7 net024 E VDD VDD sg13_lv_pmos m=1 w=975.000n l=130.00n ng=1 nrd=0 ++ nrs=0 +MP4 net015 CP VDD VDD sg13_lv_pmos m=1 w=1.27u l=130.00n ng=1 nrd=0 ++ nrs=0 +MP6 Q net015 VDD VDD sg13_lv_pmos m=1 w=3.24u l=130.00n ng=2 nrd=0 ++ nrs=0 +MP5 net015 net08 VDD VDD sg13_lv_pmos m=1 w=1.27u l=130.00n ng=1 nrd=0 ++ nrs=0 +.ENDS +.SUBCKT RSC_IHPSG13_CBUFX8 A Z VDD VSS +MP0 net4 A VDD VDD sg13_lv_pmos m=1 w=3.24u l=130.00n ng=2 nrd=0 nrs=0 +MP1 Z net4 VDD VDD sg13_lv_pmos m=1 w=6.48u l=130.00n ng=4 nrd=0 nrs=0 +MN1 Z net4 VSS VSS sg13_lv_nmos m=1 w=2.82u l=130.00n ng=4 nrd=0 nrs=0 +MN0 net4 A VSS VSS sg13_lv_nmos m=1 w=1.41u l=130.00n ng=2 nrd=0 nrs=0 +.ENDS +.SUBCKT RSC_IHPSG13_CDLYX2 A Z VDD VSS +MN2 net4 A net9 VSS sg13_lv_nmos m=1 w=320.00n l=200.0n ng=1 nrd=0 nrs=0 +MN0 Z net4 VSS VSS sg13_lv_nmos m=1 w=705.000n l=130.00n ng=1 nrd=0 ++ nrs=0 +MN1 net9 A VSS VSS sg13_lv_nmos m=1 w=320.00n l=200.0n ng=1 nrd=0 nrs=0 +MP2 net4 A net10 VDD sg13_lv_pmos m=1 w=1.2u l=200.0n ng=1 nrd=0 nrs=0 +MP1 net10 A VDD VDD sg13_lv_pmos m=1 w=1.2u l=200.0n ng=1 nrd=0 nrs=0 +MP0 Z net4 VDD VDD sg13_lv_pmos m=1 w=1.62u l=130.00n ng=1 nrd=0 nrs=0 +.ENDS +.SUBCKT RSC_IHPSG13_MX2X2 A0 A1 S Z VDD VSS +MP6 Z net010 VDD VDD sg13_lv_pmos m=1 w=1.62u l=130.00n ng=1 nrd=0 ++ nrs=0 +MP4 SN S VDD VDD sg13_lv_pmos m=1 w=645.000n l=130.00n ng=1 nrd=0 nrs=0 +MP3 net010 SN net12 VDD sg13_lv_pmos m=1 w=985.000n l=130.00n ng=1 nrd=0 ++ nrs=0 +MP2 net12 A1 VDD VDD sg13_lv_pmos m=1 w=985.000n l=130.00n ng=1 nrd=0 ++ nrs=0 +MP1 net010 S net17 VDD sg13_lv_pmos m=1 w=985.000n l=130.00n ng=1 nrd=0 ++ nrs=0 +MP0 net17 A0 VDD VDD sg13_lv_pmos m=1 w=985.000n l=130.00n ng=1 nrd=0 ++ nrs=0 +MN6 Z net010 VSS VSS sg13_lv_nmos m=1 w=705.000n l=130.00n ng=1 nrd=0 ++ nrs=0 +MN5 SN S VSS VSS sg13_lv_nmos m=1 w=560.00n l=130.00n ng=1 nrd=0 nrs=0 +MN3 net13 A1 VSS VSS sg13_lv_nmos m=1 w=560.00n l=130.00n ng=1 nrd=0 ++ nrs=0 +MN2 net010 S net13 VSS sg13_lv_nmos m=1 w=560.00n l=130.00n ng=1 nrd=0 ++ nrs=0 +MN1 net15 A0 VSS VSS sg13_lv_nmos m=1 w=560.00n l=130.00n ng=1 nrd=0 ++ nrs=0 +MN0 net010 SN net15 VSS sg13_lv_nmos m=1 w=560.00n l=130.00n ng=1 nrd=0 ++ nrs=0 +.ENDS +.SUBCKT RSC_IHPSG13_AND2X2 A B Z VDD VSS +MN3 Z net6 VSS VSS sg13_lv_nmos m=1 w=980.00n l=130.00n ng=1 nrd=0 ++ nrs=0 +MN4 net9 B VSS VSS sg13_lv_nmos m=1 w=500.0n l=130.00n ng=1 nrd=0 nrs=0 +MN6 net6 A net9 VSS sg13_lv_nmos m=1 w=500.0n l=130.00n ng=1 nrd=0 nrs=0 +MP2 Z net6 VDD VDD sg13_lv_pmos m=1 w=1.62u l=130.00n ng=1 nrd=0 nrs=0 +MP0 net6 B VDD VDD sg13_lv_pmos m=1 w=860.00n l=130.00n ng=1 nrd=0 ++ nrs=0 +MP1 net6 A VDD VDD sg13_lv_pmos m=1 w=860.00n l=130.00n ng=1 nrd=0 ++ nrs=0 +.ENDS +.SUBCKT RSC_IHPSG13_TIEL Z VDD VSS +MN0 Z net2 VSS VSS sg13_lv_nmos m=1 w=480.00n l=130.00n ng=1 nrd=0 ++ nrs=0 +MP0 net2 net2 VDD VDD sg13_lv_pmos m=1 w=480.00n l=130.00n ng=1 nrd=0 ++ nrs=0 +.ENDS +.SUBCKT RSC_IHPSG13_XOR2X2 A B Z VDD VSS +MP8 net012 B net7 VDD sg13_lv_pmos m=1 w=825.000n l=130.00n ng=1 nrd=0 ++ nrs=0 +MP7 net011 net3 net012 VDD sg13_lv_pmos m=1 w=825.000n l=130.00n ng=1 ++ nrd=0 nrs=0 +MP6 Z net012 VDD VDD sg13_lv_pmos m=1 w=1.535u l=130.00n ng=1 nrd=0 ++ nrs=0 +MP2 net7 A VDD VDD sg13_lv_pmos m=1 w=825.000n l=130.00n ng=1 nrd=0 ++ nrs=0 +MP4 net011 net7 VDD VDD sg13_lv_pmos m=1 w=825.000n l=130.00n ng=1 ++ nrd=0 nrs=0 +MP5 net3 B VDD VDD sg13_lv_pmos m=1 w=580.00n l=130.00n ng=1 nrd=0 ++ nrs=0 +MN7 net012 B net011 VSS sg13_lv_nmos m=1 w=555.000n l=130.00n ng=1 nrd=0 ++ nrs=0 +MN6 net7 net3 net012 VSS sg13_lv_nmos m=1 w=555.000n l=130.00n ng=1 nrd=0 ++ nrs=0 +MN5 Z net012 VSS VSS sg13_lv_nmos m=1 w=775.000n l=130.00n ng=1 nrd=0 ++ nrs=0 +MN2 net7 A VSS VSS sg13_lv_nmos m=1 w=555.000n l=130.00n ng=1 nrd=0 ++ nrs=0 +MN4 net3 B VSS VSS sg13_lv_nmos m=1 w=480.00n l=130.00n ng=1 nrd=0 ++ nrs=0 +MN3 net011 net7 VSS VSS sg13_lv_nmos m=1 w=555.000n l=130.00n ng=1 ++ nrd=0 nrs=0 +.ENDS +.SUBCKT RSC_IHPSG13_OA12X1 A B C Z VDD VSS +MN2 net7 C VSS VSS sg13_lv_nmos m=1 w=980.00n l=130.00n ng=1 nrd=0 ++ nrs=0 +MN3 Z net17 VSS VSS sg13_lv_nmos m=1 w=500.0n l=130.00n ng=1 nrd=0 ++ nrs=0 +MN1 net17 B net7 VSS sg13_lv_nmos m=1 w=980.00n l=130.00n ng=1 nrd=0 nrs=0 +MN0 net17 A net7 VSS sg13_lv_nmos m=1 w=980.00n l=130.00n ng=1 nrd=0 nrs=0 +MP0 net24 A VDD VDD sg13_lv_pmos m=1 w=1.62u l=130.00n ng=1 nrd=0 nrs=0 +MP3 Z net17 VDD VDD sg13_lv_pmos m=1 w=905.000n l=130.00n ng=1 nrd=0 ++ nrs=0 +MP1 net17 B net24 VDD sg13_lv_pmos m=1 w=1.62u l=130.00n ng=1 nrd=0 nrs=0 +MP2 net17 C VDD VDD sg13_lv_pmos m=1 w=905.000n l=130.00n ng=1 nrd=0 ++ nrs=0 +.ENDS +.SUBCKT RM_IHPSG13_64x32_c2_1P_CTRL ACLK_N BIST_CK_I BIST_CS_I BIST_EN BIST_RE_I ++ BIST_WE_I B_TIEL_O CK_I CS_I DCLK ECLK PULSE_H PULSE_L PULSE_O RCLK RE_I ++ ROW_CS WCLK WE_I VDD VSS +XI17 ck_regs we col_we VDD VSS / RSC_IHPSG13_DFNQX2 +XI16 ck_regs re col_re VDD VSS / RSC_IHPSG13_DFNQX2 +XI18 ck_regs cs net7 VDD VSS / RSC_IHPSG13_DFNQX2 +XI71 ACLK_N net012 PULSE_O VDD VSS / RSC_IHPSG13_DFNQX2 +XI77 col_we net9 net016 VDD VSS / RSC_IHPSG13_CNAND2X2 +XI76 col_re net9 net018 VDD VSS / RSC_IHPSG13_CNAND2X2 +XI15 ck_dly WEorREandCS aclk VDD VSS / RSC_IHPSG13_CGATEPX4 +XI14 ck WEandCS DCLK VDD VSS / RSC_IHPSG13_CGATEPX4 +XI60 net7 ROW_CS VDD VSS / RSC_IHPSG13_CBUFX8 +XI73 PULSE_O net012 VDD VSS / RSC_IHPSG13_CINVX2 +XI8 net9 net8 VDD VSS / RSC_IHPSG13_CINVX2 +XI64 ck ck_dly VDD VSS / RSC_IHPSG13_CDLYX2 +XI86 CS_I BIST_CS_I BIST_EN cs VDD VSS / RSC_IHPSG13_MX2X2 +XI87 CK_I BIST_CK_I BIST_EN ck VDD VSS / RSC_IHPSG13_MX2X2 +XI85 WE_I BIST_WE_I BIST_EN we VDD VSS / RSC_IHPSG13_MX2X2 +XI84 RE_I BIST_RE_I BIST_EN re VDD VSS / RSC_IHPSG13_MX2X2 +XI22 we cs WEandCS VDD VSS / RSC_IHPSG13_AND2X2 +XBM_TIEL B_TIEL_O VDD VSS / RSC_IHPSG13_TIEL +XI48 ck_dly ck_regs VDD VSS / RSC_IHPSG13_CINVX4 +XI81 net016 WCLK VDD VSS / RSC_IHPSG13_CINVX4 +XI80 net018 RCLK VDD VSS / RSC_IHPSG13_CINVX4 +XI78 net8 net020 VDD VSS / RSC_IHPSG13_CINVX4 +XI6 PULSE_L PULSE_H net9 VDD VSS / RSC_IHPSG13_XOR2X2 +XI79 net020 ECLK VDD VSS / RSC_IHPSG13_CINVX8 +XI63 aclk ACLK_N VDD VSS / RSC_IHPSG13_CINVX8 +XI21 re we cs WEorREandCS VDD VSS / RSC_IHPSG13_OA12X1 +.ENDS +.SUBCKT RM_IHPSG13_64x32_c2_1P_COLDEC2 ACLK_N ADDR<1> ADDR<0> ADDR_COL<1> ADDR_COL<0> ++ ADDR_DEC<7> ADDR_DEC<6> ADDR_DEC<5> ADDR_DEC<4> ADDR_DEC<3> ADDR_DEC<2> ++ ADDR_DEC<1> ADDR_DEC<0> BIST_ADDR<1> BIST_ADDR<0> BIST_EN_I VDD VSS +XI14<5> VDD VSS / RSC_IHPSG13_FILLCAP4 +XI14<4> VDD VSS / RSC_IHPSG13_FILLCAP4 +XI14<3> VDD VSS / RSC_IHPSG13_FILLCAP4 +XI14<2> VDD VSS / RSC_IHPSG13_FILLCAP4 +XI14<1> VDD VSS / RSC_IHPSG13_FILLCAP4 +XDFF<1> BIST_EN_I BIST_ADDR<1> ACLK_N ADDR<1> padr_int<1> net6<0> VDD ++ VSS / RSC_IHPSG13_DFNQMX2IX1 +XDFF<0> BIST_EN_I BIST_ADDR<0> ACLK_N ADDR<0> padr_int<0> net6<1> VDD ++ VSS / RSC_IHPSG13_DFNQMX2IX1 +XI1<3> PADR<1> PADR<0> addr_n<3> VDD VSS / RSC_IHPSG13_NAND2X2 +XI1<2> PADR<1> NADR<0> addr_n<2> VDD VSS / RSC_IHPSG13_NAND2X2 +XI1<1> NADR<1> PADR<0> addr_n<1> VDD VSS / RSC_IHPSG13_NAND2X2 +XI1<0> NADR<1> NADR<0> addr_n<0> VDD VSS / RSC_IHPSG13_NAND2X2 +XI16<37> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI16<36> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI16<35> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI16<34> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI16<33> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI16<32> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI16<31> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI16<30> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI16<29> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI16<28> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI16<27> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI16<26> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI16<25> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI16<24> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI16<23> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI16<22> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI16<21> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI16<20> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI16<19> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI16<18> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI16<17> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI16<16> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI16<15> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI16<14> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI16<13> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI16<12> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI16<11> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI16<10> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI16<9> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI16<8> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI16<7> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI16<6> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI16<5> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI16<4> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI16<3> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI16<2> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI16<1> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI3<1> padr_int<1> NADR<1> VDD VSS / RSC_IHPSG13_INVX2 +XI3<0> padr_int<0> NADR<0> VDD VSS / RSC_IHPSG13_INVX2 +XI13<1> NADR<1> PADR<1> VDD VSS / RSC_IHPSG13_INVX2 +XI13<0> NADR<0> PADR<0> VDD VSS / RSC_IHPSG13_INVX2 +XI2<3> addr_n<3> ADDR_DEC<3> VDD VSS / RSC_IHPSG13_INVX2 +XI2<2> addr_n<2> ADDR_DEC<2> VDD VSS / RSC_IHPSG13_INVX2 +XI2<1> addr_n<1> ADDR_DEC<1> VDD VSS / RSC_IHPSG13_INVX2 +XI2<0> addr_n<0> ADDR_DEC<0> VDD VSS / RSC_IHPSG13_INVX2 +XI15<1> ADDR_COL<1> VDD VSS / RSC_IHPSG13_TIEL +XI15<0> ADDR_COL<0> VDD VSS / RSC_IHPSG13_TIEL +XI17<3> ADDR_DEC<7> VDD VSS / RSC_IHPSG13_TIEL +XI17<2> ADDR_DEC<6> VDD VSS / RSC_IHPSG13_TIEL +XI17<1> ADDR_DEC<5> VDD VSS / RSC_IHPSG13_TIEL +XI17<0> ADDR_DEC<4> VDD VSS / RSC_IHPSG13_TIEL +.ENDS +.SUBCKT RSC_IHPSG13_NOR2X2 A B Z VDD VSS +MP1 Z B net9 VDD sg13_lv_pmos m=1 w=1.62u l=130.00n ng=1 nrd=0 nrs=0 +MP0 net9 A VDD VDD sg13_lv_pmos m=1 w=1.62u l=130.00n ng=1 nrd=0 nrs=0 +MN0 Z B VSS VSS sg13_lv_nmos m=1 w=980.00n l=130.00n ng=1 nrd=0 nrs=0 +MN1 Z A VSS VSS sg13_lv_nmos m=1 w=980.00n l=130.00n ng=1 nrd=0 nrs=0 +.ENDS +.SUBCKT RSC_IHPSG13_CINVX4_WN A Z VDD VSS +MN0 Z A VSS VSS sg13_lv_nmos m=1 w=705.000n l=130.00n ng=1 nrd=0 nrs=0 +MP0 Z A VDD VDD sg13_lv_pmos m=1 w=3.24u l=130.00n ng=2 nrd=0 nrs=0 +.ENDS +.SUBCKT RM_IHPSG13_64x32_c2_1P_BLDRV BLC BLC_SEL BLT BLT_SEL PRE_N SEL_P WR_ONE WR_ZERO ++ VDD VSS +XCDEC SEL_P WR_ZERO BLC_PMOS_DRIVE VDD VSS / RSC_IHPSG13_NAND2X2 +XTDEC SEL_P WR_ONE BLT_PMOS_DRIVE VDD VSS / RSC_IHPSG13_NAND2X2 +MTWN BLT BLT_NMOS_DRIVE VSS VSS sg13_lv_nmos m=1 w=4.82u l=130.00n ++ ng=2 nrd=0 nrs=0 +MCWN BLC BLC_NMOS_DRIVE VSS VSS sg13_lv_nmos m=1 w=4.82u l=130.00n ++ ng=2 nrd=0 nrs=0 +MCWP BLC BLC_PMOS_DRIVE VDD VDD sg13_lv_pmos m=1 w=1.5u l=130.00n ng=1 ++ nrd=0 nrs=0 +MTWP BLT BLT_PMOS_DRIVE VDD VDD sg13_lv_pmos m=1 w=1.5u l=130.00n ng=1 ++ nrd=0 nrs=0 +MTSP BLT_SEL SEL_N BLT VDD sg13_lv_pmos m=1 w=1.5u l=130.00n ng=1 nrd=0 ++ nrs=0 +MTPR BLT PRE_N VDD VDD sg13_lv_pmos m=1 w=3.000u l=130.00n ng=2 nrd=0 ++ nrs=0 +MCSP BLC_SEL SEL_N BLC VDD sg13_lv_pmos m=1 w=1.5u l=130.00n ng=1 nrd=0 ++ nrs=0 +MCPR BLC PRE_N VDD VDD sg13_lv_pmos m=1 w=3.000u l=130.00n ng=2 nrd=0 ++ nrs=0 +XI86 SEL_P SEL_N VDD VSS / RSC_IHPSG13_INVX2 +XTINV BLC_PMOS_DRIVE BLT_NMOS_DRIVE VDD VSS / RSC_IHPSG13_INVX2 +XCINV BLT_PMOS_DRIVE BLC_NMOS_DRIVE VDD VSS / RSC_IHPSG13_INVX2 +.ENDS +.SUBCKT RSC_IHPSG13_TIEH Z VDD VSS +MN0 net2 net2 VSS VSS sg13_lv_nmos m=1 w=480.00n l=130.00n ng=1 nrd=0 ++ nrs=0 +MP0 Z net2 VDD VDD sg13_lv_pmos m=1 w=480.00n l=130.00n ng=1 nrd=0 ++ nrs=0 +.ENDS +.SUBCKT RSC_IHPSG13_MET3RES A B +R0 B A lvsres w=2.6e-07 l=6e-07 +.ENDS +.SUBCKT RSC_IHPSG13_DFPQD_MSAFFX2 CP DN DP QN QP VDD VSS +MN12 SN RN DIFFP VSS sg13_lv_nmos m=1 w=2.4u l=200.0n ng=2 nrd=0 nrs=0 +MN13 TAIL CP VSS VSS sg13_lv_nmos m=1 w=2.4u l=130.00n ng=2 nrd=0 nrs=0 +MN9 DIFFP DP TAIL VSS sg13_lv_nmos m=1 w=2.4u l=200.0n ng=2 nrd=0 nrs=0 +MN10 DIFFN DN TAIL VSS sg13_lv_nmos m=1 w=2.4u l=200.0n ng=2 nrd=0 nrs=0 +MN11 RN SN DIFFN VSS sg13_lv_nmos m=1 w=2.4u l=200.0n ng=2 nrd=0 nrs=0 +MN19 net33 SN VSS VSS sg13_lv_nmos m=1 w=980.00n l=130.00n ng=1 nrd=0 ++ nrs=0 +MN20 QN QP net37 VSS sg13_lv_nmos m=1 w=980.00n l=130.00n ng=1 nrd=0 nrs=0 +MN18 net37 RN VSS VSS sg13_lv_nmos m=1 w=980.00n l=130.00n ng=1 nrd=0 ++ nrs=0 +MN17 QP QN net33 VSS sg13_lv_nmos m=1 w=980.00n l=130.00n ng=1 nrd=0 nrs=0 +MP15 SN RN VDD VDD sg13_lv_pmos m=1 w=800.0n l=130.00n ng=1 nrd=0 nrs=0 +MP16 RN CP VDD VDD sg13_lv_pmos m=1 w=800.0n l=130.00n ng=1 nrd=0 nrs=0 +MP14 DIFFP CP VDD VDD sg13_lv_pmos m=1 w=800.0n l=130.00n ng=1 nrd=0 ++ nrs=0 +MP12 RN SN VDD VDD sg13_lv_pmos m=1 w=800.0n l=130.00n ng=1 nrd=0 nrs=0 +MP13 DIFFN CP VDD VDD sg13_lv_pmos m=1 w=800.0n l=130.00n ng=1 nrd=0 ++ nrs=0 +MP11 SN CP VDD VDD sg13_lv_pmos m=1 w=800.0n l=130.00n ng=1 nrd=0 nrs=0 +MP19 QN QP VDD VDD sg13_lv_pmos m=1 w=900.0n l=130.00n ng=1 nrd=0 nrs=0 +MP20 QP SN VDD VDD sg13_lv_pmos m=1 w=1.8u l=130.00n ng=2 nrd=0 nrs=0 +MP18 QN RN VDD VDD sg13_lv_pmos m=1 w=1.8u l=130.00n ng=2 nrd=0 nrs=0 +MP17 QP QN VDD VDD sg13_lv_pmos m=1 w=900.0n l=130.00n ng=1 nrd=0 nrs=0 +.ENDS +.SUBCKT RSC_IHPSG13_CBUFX2 A Z VDD VSS +MN1 Z net4 VSS VSS sg13_lv_nmos m=1 w=705.000n l=130.00n ng=1 nrd=0 ++ nrs=0 +MN0 net4 A VSS VSS sg13_lv_nmos m=1 w=540.00n l=130.00n ng=1 nrd=0 ++ nrs=0 +MP1 Z net4 VDD VDD sg13_lv_pmos m=1 w=1.62u l=130.00n ng=1 nrd=0 nrs=0 +MP0 net4 A VDD VDD sg13_lv_pmos m=1 w=1.1u l=130.00n ng=1 nrd=0 nrs=0 +.ENDS +.SUBCKT RSC_IHPSG13_INVX4 A Z VDD VSS +MN0 Z A VSS VSS sg13_lv_nmos m=1 w=1.96u l=130.00n ng=2 nrd=0 nrs=0 +MP0 Z A VDD VDD sg13_lv_pmos m=1 w=3.24u l=130.00n ng=2 nrd=0 nrs=0 +.ENDS +.SUBCKT RM_IHPSG13_64x32_c2_1P_COLCTRL2 A_ADDR_DEC<3> A_ADDR_DEC<2> A_ADDR_DEC<1> ++ A_ADDR_DEC<0> A_BIST_BM_I A_BIST_DW_I A_BIST_EN_I A_BLC<3> A_BLC<2> A_BLC<1> ++ A_BLC<0> A_BLT<3> A_BLT<2> A_BLT<1> A_BLT<0> A_BM_I A_DCLK_B_L A_DCLK_B_R ++ A_DCLK_L A_DCLK_R A_DR_O A_DW_I A_RCLK_B_L A_RCLK_B_R A_RCLK_L A_RCLK_R ++ A_TIEH_O A_WCLK_B_L A_WCLK_B_R A_WCLK_L A_WCLK_R VDD VSS +XA_DREG A_BIST_EN_I A_BIST_DW_I A_DCLK_B_L A_DW_I A_DI_R net22 VDD VSS ++ / RSC_IHPSG13_DFNQMX2IX1 +XA_BREG A_BIST_EN_I A_BIST_BM_I A_DCLK_B_L A_BM_I A_BM_R net23 VDD VSS ++ / RSC_IHPSG13_DFNQMX2IX1 +XA_CAPS<5> VDD VSS / RSC_IHPSG13_FILLCAP4 +XA_CAPS<4> VDD VSS / RSC_IHPSG13_FILLCAP4 +XA_CAPS<3> VDD VSS / RSC_IHPSG13_FILLCAP4 +XA_CAPS<2> VDD VSS / RSC_IHPSG13_FILLCAP4 +XA_CAPS<1> VDD VSS / RSC_IHPSG13_FILLCAP4 +XA_I80 A_WCLK_B_R A_RCLK_B_R net21 VDD VSS / RSC_IHPSG13_AND2X2 +XA_I75 A_DI_R A_DO_WRITE_P A_WR_ONE VDD VSS / RSC_IHPSG13_AND2X2 +XA_I76 A_DI_N A_DO_WRITE_P A_WR_ZERO VDD VSS / RSC_IHPSG13_AND2X2 +XA_I44 A_WCLK_B_R A_BM_N A_DO_WRITE_P VDD VSS / RSC_IHPSG13_NOR2X2 +XA_I81 net21 A_PRE_N VDD VSS / RSC_IHPSG13_CINVX4_WN +XA_BLTMUX<3> A_BLC<3> A_BLC_SEL A_BLT<3> A_BLT_SEL A_PRE_N A_ADDR_DEC<3> ++ A_WR_ONE A_WR_ZERO VDD VSS / RM_IHPSG13_64x32_c2_1P_BLDRV +XA_BLTMUX<2> A_BLC<2> A_BLC_SEL A_BLT<2> A_BLT_SEL A_PRE_N A_ADDR_DEC<2> ++ A_WR_ONE A_WR_ZERO VDD VSS / RM_IHPSG13_64x32_c2_1P_BLDRV +XA_BLTMUX<1> A_BLC<1> A_BLC_SEL A_BLT<1> A_BLT_SEL A_PRE_N A_ADDR_DEC<1> ++ A_WR_ONE A_WR_ZERO VDD VSS / RM_IHPSG13_64x32_c2_1P_BLDRV +XA_BLTMUX<0> A_BLC<0> A_BLC_SEL A_BLT<0> A_BLT_SEL A_PRE_N A_ADDR_DEC<0> ++ A_WR_ONE A_WR_ZERO VDD VSS / RM_IHPSG13_64x32_c2_1P_BLDRV +XA_BM_TIEH A_TIEH_O VDD VSS / RSC_IHPSG13_TIEH +XA_I89 A_DCLK_B_L A_DCLK_B_R / RSC_IHPSG13_MET3RES +XA_I88 A_DCLK_L A_DCLK_R / RSC_IHPSG13_MET3RES +XA_I87 A_WCLK_L A_WCLK_R / RSC_IHPSG13_MET3RES +XA_I91 A_RCLK_B_R A_RCLK_B_L / RSC_IHPSG13_MET3RES +XA_R2 A_RCLK_R A_RCLK_L / RSC_IHPSG13_MET3RES +XA_I90 A_WCLK_B_R A_WCLK_B_L / RSC_IHPSG13_MET3RES +XA_ISENSE A_SAE A_BLC_SEL A_BLT_SEL net19 net20 VDD VSS / ++ RSC_IHPSG13_DFPQD_MSAFFX2 +XA_I78 A_RCLK_B_R A_SAE VDD VSS / RSC_IHPSG13_CBUFX2 +XA_I83 A_BM_R A_BM_N VDD VSS / RSC_IHPSG13_INVX2 +XA_I49 A_DI_R A_DI_N VDD VSS / RSC_IHPSG13_INVX2 +XA_I51 net19 A_DR_O VDD VSS / RSC_IHPSG13_INVX4 +XA_I69 A_DCLK_L A_DCLK_B_L VDD VSS / RSC_IHPSG13_CINVX2 +XA_I50 A_WCLK_L A_WCLK_B_R VDD VSS / RSC_IHPSG13_CINVX2 +XA_EBUF A_RCLK_R A_RCLK_B_R VDD VSS / RSC_IHPSG13_CINVX2 +.ENDS +.SUBCKT RM_IHPSG13_64x32_c2_1P_COLDRV13_FILL4 VDD VSS +XI0<9> VDD VSS / RSC_IHPSG13_FILLCAP4 +XI0<8> VDD VSS / RSC_IHPSG13_FILLCAP4 +XI0<7> VDD VSS / RSC_IHPSG13_FILLCAP4 +XI0<6> VDD VSS / RSC_IHPSG13_FILLCAP4 +XI0<5> VDD VSS / RSC_IHPSG13_FILLCAP4 +XI0<4> VDD VSS / RSC_IHPSG13_FILLCAP4 +XI0<3> VDD VSS / RSC_IHPSG13_FILLCAP4 +XI0<2> VDD VSS / RSC_IHPSG13_FILLCAP4 +XI0<1> VDD VSS / RSC_IHPSG13_FILLCAP4 +.ENDS +.SUBCKT RM_IHPSG13_64x32_c2_1P_COLDRV13_FILL4C2 VDD VSS +XI0<2> VDD VSS / RSC_IHPSG13_FILLCAP4 +XI0<1> VDD VSS / RSC_IHPSG13_FILLCAP4 +.ENDS + + +.SUBCKT RM_IHPSG13_64x32_c2_1P_COLDEC4 ACLK_N ADDR<3> ADDR<2> ADDR<1> ADDR<0> ++ ADDR_COL<1> ADDR_COL<0> ADDR_DEC<7> ADDR_DEC<6> ADDR_DEC<5> ADDR_DEC<4> ++ ADDR_DEC<3> ADDR_DEC<2> ADDR_DEC<1> ADDR_DEC<0> BIST_ADDR<3> BIST_ADDR<2> ++ BIST_ADDR<1> BIST_ADDR<0> BIST_EN_I VDD VSS +XI15 ADDR_COL<1> VDD VSS / RSC_IHPSG13_TIEL +XI14 addr_int ADDR_COL<0> VDD VSS / RSC_IHPSG13_CBUFX2 +XDFF<3> BIST_EN_I BIST_ADDR<3> ACLK_N ADDR<3> addr_int net7<0> VDD VSS ++ / RSC_IHPSG13_DFNQMX2IX1 +XDFF<2> BIST_EN_I BIST_ADDR<2> ACLK_N ADDR<2> padr_int<2> net7<1> VDD ++ VSS / RSC_IHPSG13_DFNQMX2IX1 +XDFF<1> BIST_EN_I BIST_ADDR<1> ACLK_N ADDR<1> padr_int<1> net7<2> VDD ++ VSS / RSC_IHPSG13_DFNQMX2IX1 +XDFF<0> BIST_EN_I BIST_ADDR<0> ACLK_N ADDR<0> padr_int<0> net7<3> VDD ++ VSS / RSC_IHPSG13_DFNQMX2IX1 +XI1<7> PADR<0> PADR<1> PADR<2> addr_n<7> VDD VSS / RSC_IHPSG13_NAND3X2 +XI1<6> NADR<0> PADR<1> PADR<2> addr_n<6> VDD VSS / RSC_IHPSG13_NAND3X2 +XI1<5> PADR<0> NADR<1> PADR<2> addr_n<5> VDD VSS / RSC_IHPSG13_NAND3X2 +XI1<4> NADR<0> NADR<1> PADR<2> addr_n<4> VDD VSS / RSC_IHPSG13_NAND3X2 +XI1<3> PADR<0> PADR<1> NADR<2> addr_n<3> VDD VSS / RSC_IHPSG13_NAND3X2 +XI1<2> NADR<0> PADR<1> NADR<2> addr_n<2> VDD VSS / RSC_IHPSG13_NAND3X2 +XI1<1> PADR<0> NADR<1> NADR<2> addr_n<1> VDD VSS / RSC_IHPSG13_NAND3X2 +XI1<0> NADR<0> NADR<1> NADR<2> addr_n<0> VDD VSS / RSC_IHPSG13_NAND3X2 +XI13<2> NADR<2> PADR<2> VDD VSS / RSC_IHPSG13_INVX2 +XI13<1> NADR<1> PADR<1> VDD VSS / RSC_IHPSG13_INVX2 +XI13<0> NADR<0> PADR<0> VDD VSS / RSC_IHPSG13_INVX2 +XI3<2> padr_int<2> NADR<2> VDD VSS / RSC_IHPSG13_INVX2 +XI3<1> padr_int<1> NADR<1> VDD VSS / RSC_IHPSG13_INVX2 +XI3<0> padr_int<0> NADR<0> VDD VSS / RSC_IHPSG13_INVX2 +XI2<7> addr_n<7> ADDR_DEC<7> VDD VSS / RSC_IHPSG13_INVX2 +XI2<6> addr_n<6> ADDR_DEC<6> VDD VSS / RSC_IHPSG13_INVX2 +XI2<5> addr_n<5> ADDR_DEC<5> VDD VSS / RSC_IHPSG13_INVX2 +XI2<4> addr_n<4> ADDR_DEC<4> VDD VSS / RSC_IHPSG13_INVX2 +XI2<3> addr_n<3> ADDR_DEC<3> VDD VSS / RSC_IHPSG13_INVX2 +XI2<2> addr_n<2> ADDR_DEC<2> VDD VSS / RSC_IHPSG13_INVX2 +XI2<1> addr_n<1> ADDR_DEC<1> VDD VSS / RSC_IHPSG13_INVX2 +XI2<0> addr_n<0> ADDR_DEC<0> VDD VSS / RSC_IHPSG13_INVX2 +XI16<3> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI16<2> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI16<1> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI17<2> VDD VSS / RSC_IHPSG13_FILLCAP4 +XI17<1> VDD VSS / RSC_IHPSG13_FILLCAP4 +.ENDS +.SUBCKT RSC_IHPSG13_AND2X4 A B Z VDD VSS +MN3 Z net6 VSS VSS sg13_lv_nmos m=1 w=1.96u l=130.00n ng=2 nrd=0 nrs=0 +MN4 net9 B VSS VSS sg13_lv_nmos m=1 w=500.0n l=130.00n ng=1 nrd=0 nrs=0 +MN6 net6 A net9 VSS sg13_lv_nmos m=1 w=500.0n l=130.00n ng=1 nrd=0 nrs=0 +MP2 Z net6 VDD VDD sg13_lv_pmos m=1 w=3.24u l=130.00n ng=2 nrd=0 nrs=0 +MP0 net6 B VDD VDD sg13_lv_pmos m=1 w=860.00n l=130.00n ng=1 nrd=0 ++ nrs=0 +MP1 net6 A VDD VDD sg13_lv_pmos m=1 w=860.00n l=130.00n ng=1 nrd=0 ++ nrs=0 +.ENDS +.SUBCKT RM_IHPSG13_64x32_c2_1P_COLCTRL4 A_ADDR_COL A_ADDR_DEC<7> A_ADDR_DEC<6> ++ A_ADDR_DEC<5> A_ADDR_DEC<4> A_ADDR_DEC<3> A_ADDR_DEC<2> A_ADDR_DEC<1> ++ A_ADDR_DEC<0> A_BIST_BM_I A_BIST_DW_I A_BIST_EN_I A_BLC<15> A_BLC<14> ++ A_BLC<13> A_BLC<12> A_BLC<11> A_BLC<10> A_BLC<9> A_BLC<8> A_BLC<7> A_BLC<6> ++ A_BLC<5> A_BLC<4> A_BLC<3> A_BLC<2> A_BLC<1> A_BLC<0> A_BLT<15> A_BLT<14> ++ A_BLT<13> A_BLT<12> A_BLT<11> A_BLT<10> A_BLT<9> A_BLT<8> A_BLT<7> A_BLT<6> ++ A_BLT<5> A_BLT<4> A_BLT<3> A_BLT<2> A_BLT<1> A_BLT<0> A_BM_I A_DCLK_B_L ++ A_DCLK_B_R A_DCLK_L A_DCLK_R A_DR_O A_DW_I A_RCLK_B_L A_RCLK_B_R A_RCLK_L ++ A_RCLK_R A_TIEH_O A_WCLK_B_L A_WCLK_B_R A_WCLK_L A_WCLK_R VDD VSS +XA_I80 A_WCLK_B_L A_RCLK_B_L net21 VDD VSS / RSC_IHPSG13_AND2X2 +XA_I76 A_DO_WRITE_P A_DI_N A_WR_ZERO VDD VSS / RSC_IHPSG13_AND2X4 +XA_I75 A_DI_R A_DO_WRITE_P A_WR_ONE VDD VSS / RSC_IHPSG13_AND2X4 +XA_CAPS<8> VDD VSS / RSC_IHPSG13_FILLCAP4 +XA_CAPS<7> VDD VSS / RSC_IHPSG13_FILLCAP4 +XA_CAPS<6> VDD VSS / RSC_IHPSG13_FILLCAP4 +XA_CAPS<5> VDD VSS / RSC_IHPSG13_FILLCAP4 +XA_CAPS<4> VDD VSS / RSC_IHPSG13_FILLCAP4 +XA_CAPS<3> VDD VSS / RSC_IHPSG13_FILLCAP4 +XA_CAPS<2> VDD VSS / RSC_IHPSG13_FILLCAP4 +XA_CAPS<1> VDD VSS / RSC_IHPSG13_FILLCAP4 +XA_I69 A_DCLK_L A_DCLK_B_L VDD VSS / RSC_IHPSG13_CINVX4 +XA_I50 A_WCLK_L A_WCLK_B_L VDD VSS / RSC_IHPSG13_CINVX4 +XA_EBUF A_RCLK_L A_RCLK_B_L VDD VSS / RSC_IHPSG13_CINVX4 +XA_INV<1> A_N0 A_P0 VDD VSS / RSC_IHPSG13_CINVX4 +XA_INV<0> A_ADDR_COL A_N0 VDD VSS / RSC_IHPSG13_CINVX4 +XA_I81<1> net21 A_PRE_N VDD VSS / RSC_IHPSG13_CINVX4_WN +XA_I81<0> net21 A_PRE_N VDD VSS / RSC_IHPSG13_CINVX4_WN +XA_BLTMUX<15> A_BLC<15> A_BLC_SEL A_BLT<15> A_BLT_SEL A_PRE_N A_SEL_P<15> ++ A_WR_ONE A_WR_ZERO VDD VSS / RM_IHPSG13_64x32_c2_1P_BLDRV +XA_BLTMUX<14> A_BLC<14> A_BLC_SEL A_BLT<14> A_BLT_SEL A_PRE_N A_SEL_P<14> ++ A_WR_ONE A_WR_ZERO VDD VSS / RM_IHPSG13_64x32_c2_1P_BLDRV +XA_BLTMUX<13> A_BLC<13> A_BLC_SEL A_BLT<13> A_BLT_SEL A_PRE_N A_SEL_P<13> ++ A_WR_ONE A_WR_ZERO VDD VSS / RM_IHPSG13_64x32_c2_1P_BLDRV +XA_BLTMUX<12> A_BLC<12> A_BLC_SEL A_BLT<12> A_BLT_SEL A_PRE_N A_SEL_P<12> ++ A_WR_ONE A_WR_ZERO VDD VSS / RM_IHPSG13_64x32_c2_1P_BLDRV +XA_BLTMUX<11> A_BLC<11> A_BLC_SEL A_BLT<11> A_BLT_SEL A_PRE_N A_SEL_P<11> ++ A_WR_ONE A_WR_ZERO VDD VSS / RM_IHPSG13_64x32_c2_1P_BLDRV +XA_BLTMUX<10> A_BLC<10> A_BLC_SEL A_BLT<10> A_BLT_SEL A_PRE_N A_SEL_P<10> ++ A_WR_ONE A_WR_ZERO VDD VSS / RM_IHPSG13_64x32_c2_1P_BLDRV +XA_BLTMUX<9> A_BLC<9> A_BLC_SEL A_BLT<9> A_BLT_SEL A_PRE_N A_SEL_P<9> A_WR_ONE ++ A_WR_ZERO VDD VSS / RM_IHPSG13_64x32_c2_1P_BLDRV +XA_BLTMUX<8> A_BLC<8> A_BLC_SEL A_BLT<8> A_BLT_SEL A_PRE_N A_SEL_P<8> A_WR_ONE ++ A_WR_ZERO VDD VSS / RM_IHPSG13_64x32_c2_1P_BLDRV +XA_BLTMUX<7> A_BLC<7> A_BLC_SEL A_BLT<7> A_BLT_SEL A_PRE_N A_SEL_P<7> A_WR_ONE ++ A_WR_ZERO VDD VSS / RM_IHPSG13_64x32_c2_1P_BLDRV +XA_BLTMUX<6> A_BLC<6> A_BLC_SEL A_BLT<6> A_BLT_SEL A_PRE_N A_SEL_P<6> A_WR_ONE ++ A_WR_ZERO VDD VSS / RM_IHPSG13_64x32_c2_1P_BLDRV +XA_BLTMUX<5> A_BLC<5> A_BLC_SEL A_BLT<5> A_BLT_SEL A_PRE_N A_SEL_P<5> A_WR_ONE ++ A_WR_ZERO VDD VSS / RM_IHPSG13_64x32_c2_1P_BLDRV +XA_BLTMUX<4> A_BLC<4> A_BLC_SEL A_BLT<4> A_BLT_SEL A_PRE_N A_SEL_P<4> A_WR_ONE ++ A_WR_ZERO VDD VSS / RM_IHPSG13_64x32_c2_1P_BLDRV +XA_BLTMUX<3> A_BLC<3> A_BLC_SEL A_BLT<3> A_BLT_SEL A_PRE_N A_SEL_P<3> A_WR_ONE ++ A_WR_ZERO VDD VSS / RM_IHPSG13_64x32_c2_1P_BLDRV +XA_BLTMUX<2> A_BLC<2> A_BLC_SEL A_BLT<2> A_BLT_SEL A_PRE_N A_SEL_P<2> A_WR_ONE ++ A_WR_ZERO VDD VSS / RM_IHPSG13_64x32_c2_1P_BLDRV +XA_BLTMUX<1> A_BLC<1> A_BLC_SEL A_BLT<1> A_BLT_SEL A_PRE_N A_SEL_P<1> A_WR_ONE ++ A_WR_ZERO VDD VSS / RM_IHPSG13_64x32_c2_1P_BLDRV +XA_BLTMUX<0> A_BLC<0> A_BLC_SEL A_BLT<0> A_BLT_SEL A_PRE_N A_SEL_P<0> A_WR_ONE ++ A_WR_ZERO VDD VSS / RM_IHPSG13_64x32_c2_1P_BLDRV +XA_R2 A_RCLK_L A_RCLK_R / RSC_IHPSG13_MET3RES +XA_I87 A_WCLK_L A_WCLK_R / RSC_IHPSG13_MET3RES +XA_I88 A_DCLK_L A_DCLK_R / RSC_IHPSG13_MET3RES +XA_I89 A_DCLK_B_L A_DCLK_B_R / RSC_IHPSG13_MET3RES +XA_I90 A_WCLK_B_L A_WCLK_B_R / RSC_IHPSG13_MET3RES +XA_I91 A_RCLK_B_L A_RCLK_B_R / RSC_IHPSG13_MET3RES +XA_ISENSE A_SAE A_BLC_SEL A_BLT_SEL net19 net20 VDD VSS / ++ RSC_IHPSG13_DFPQD_MSAFFX2 +XA_I51 net19 A_DR_O VDD VSS / RSC_IHPSG13_INVX4 +XA_I78 A_RCLK_B_L A_SAE VDD VSS / RSC_IHPSG13_CBUFX2 +XA_DREG A_BIST_EN_I A_BIST_DW_I A_DCLK_B_L A_DW_I A_DI_R net22 VDD VSS ++ / RSC_IHPSG13_DFNQMX2IX1 +XA_BREG A_BIST_EN_I A_BIST_BM_I A_DCLK_B_L A_BM_I A_BM_R net24 VDD VSS ++ / RSC_IHPSG13_DFNQMX2IX1 +XA_DEC3INV<15> net23<0> A_SEL_P<15> VDD VSS / RSC_IHPSG13_INVX2 +XA_DEC3INV<14> net23<1> A_SEL_P<14> VDD VSS / RSC_IHPSG13_INVX2 +XA_DEC3INV<13> net23<2> A_SEL_P<13> VDD VSS / RSC_IHPSG13_INVX2 +XA_DEC3INV<12> net23<3> A_SEL_P<12> VDD VSS / RSC_IHPSG13_INVX2 +XA_DEC3INV<11> net23<4> A_SEL_P<11> VDD VSS / RSC_IHPSG13_INVX2 +XA_DEC3INV<10> net23<5> A_SEL_P<10> VDD VSS / RSC_IHPSG13_INVX2 +XA_DEC3INV<9> net23<6> A_SEL_P<9> VDD VSS / RSC_IHPSG13_INVX2 +XA_DEC3INV<8> net23<7> A_SEL_P<8> VDD VSS / RSC_IHPSG13_INVX2 +XA_DEC3INV<7> net23<8> A_SEL_P<7> VDD VSS / RSC_IHPSG13_INVX2 +XA_DEC3INV<6> net23<9> A_SEL_P<6> VDD VSS / RSC_IHPSG13_INVX2 +XA_DEC3INV<5> net23<10> A_SEL_P<5> VDD VSS / RSC_IHPSG13_INVX2 +XA_DEC3INV<4> net23<11> A_SEL_P<4> VDD VSS / RSC_IHPSG13_INVX2 +XA_DEC3INV<3> net23<12> A_SEL_P<3> VDD VSS / RSC_IHPSG13_INVX2 +XA_DEC3INV<2> net23<13> A_SEL_P<2> VDD VSS / RSC_IHPSG13_INVX2 +XA_DEC3INV<1> net23<14> A_SEL_P<1> VDD VSS / RSC_IHPSG13_INVX2 +XA_DEC3INV<0> net23<15> A_SEL_P<0> VDD VSS / RSC_IHPSG13_INVX2 +XA_I83 A_BM_R A_BM_N VDD VSS / RSC_IHPSG13_INVX2 +XA_I49 A_DI_R A_DI_N VDD VSS / RSC_IHPSG13_INVX2 +XA_I70<4> VDD VSS / RSC_IHPSG13_FILLCAP8 +XA_I70<3> VDD VSS / RSC_IHPSG13_FILLCAP8 +XA_I70<2> VDD VSS / RSC_IHPSG13_FILLCAP8 +XA_I70<1> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI73<14> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI73<13> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI73<12> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI73<11> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI73<10> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI73<9> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI73<8> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI73<7> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI73<6> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI73<5> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI73<4> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI73<3> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI73<2> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI73<1> VDD VSS / RSC_IHPSG13_FILLCAP8 +XA_I44 A_BM_N A_WCLK_B_L A_DO_WRITE_P VDD VSS / RSC_IHPSG13_NOR2X2 +XA_DEC3<15> A_P0 A_ADDR_DEC<7> net23<0> VDD VSS / RSC_IHPSG13_NAND2X2 +XA_DEC3<14> A_P0 A_ADDR_DEC<6> net23<1> VDD VSS / RSC_IHPSG13_NAND2X2 +XA_DEC3<13> A_P0 A_ADDR_DEC<5> net23<2> VDD VSS / RSC_IHPSG13_NAND2X2 +XA_DEC3<12> A_P0 A_ADDR_DEC<4> net23<3> VDD VSS / RSC_IHPSG13_NAND2X2 +XA_DEC3<11> A_P0 A_ADDR_DEC<3> net23<4> VDD VSS / RSC_IHPSG13_NAND2X2 +XA_DEC3<10> A_P0 A_ADDR_DEC<2> net23<5> VDD VSS / RSC_IHPSG13_NAND2X2 +XA_DEC3<9> A_P0 A_ADDR_DEC<1> net23<6> VDD VSS / RSC_IHPSG13_NAND2X2 +XA_DEC3<8> A_P0 A_ADDR_DEC<0> net23<7> VDD VSS / RSC_IHPSG13_NAND2X2 +XA_DEC3<7> A_N0 A_ADDR_DEC<7> net23<8> VDD VSS / RSC_IHPSG13_NAND2X2 +XA_DEC3<6> A_N0 A_ADDR_DEC<6> net23<9> VDD VSS / RSC_IHPSG13_NAND2X2 +XA_DEC3<5> A_N0 A_ADDR_DEC<5> net23<10> VDD VSS / RSC_IHPSG13_NAND2X2 +XA_DEC3<4> A_N0 A_ADDR_DEC<4> net23<11> VDD VSS / RSC_IHPSG13_NAND2X2 +XA_DEC3<3> A_N0 A_ADDR_DEC<3> net23<12> VDD VSS / RSC_IHPSG13_NAND2X2 +XA_DEC3<2> A_N0 A_ADDR_DEC<2> net23<13> VDD VSS / RSC_IHPSG13_NAND2X2 +XA_DEC3<1> A_N0 A_ADDR_DEC<1> net23<14> VDD VSS / RSC_IHPSG13_NAND2X2 +XA_DEC3<0> A_N0 A_ADDR_DEC<0> net23<15> VDD VSS / RSC_IHPSG13_NAND2X2 +XA_BM_TIEH A_TIEH_O VDD VSS / RSC_IHPSG13_TIEH +.ENDS + + +.SUBCKT RM_IHPSG13_64x32_c2_1P_COLDEC3 ACLK_N ADDR<2> ADDR<1> ADDR<0> ADDR_COL<1> ++ ADDR_COL<0> ADDR_DEC<7> ADDR_DEC<6> ADDR_DEC<5> ADDR_DEC<4> ADDR_DEC<3> ++ ADDR_DEC<2> ADDR_DEC<1> ADDR_DEC<0> BIST_ADDR<2> BIST_ADDR<1> BIST_ADDR<0> ++ BIST_EN_I VDD VSS +XI15<1> ADDR_COL<1> VDD VSS / RSC_IHPSG13_TIEL +XI15<0> ADDR_COL<0> VDD VSS / RSC_IHPSG13_TIEL +XI1<7> PADR<0> PADR<1> PADR<2> addr_n<7> VDD VSS / RSC_IHPSG13_NAND3X2 +XI1<6> NADR<0> PADR<1> PADR<2> addr_n<6> VDD VSS / RSC_IHPSG13_NAND3X2 +XI1<5> PADR<0> NADR<1> PADR<2> addr_n<5> VDD VSS / RSC_IHPSG13_NAND3X2 +XI1<4> NADR<0> NADR<1> PADR<2> addr_n<4> VDD VSS / RSC_IHPSG13_NAND3X2 +XI1<3> PADR<0> PADR<1> NADR<2> addr_n<3> VDD VSS / RSC_IHPSG13_NAND3X2 +XI1<2> NADR<0> PADR<1> NADR<2> addr_n<2> VDD VSS / RSC_IHPSG13_NAND3X2 +XI1<1> PADR<0> NADR<1> NADR<2> addr_n<1> VDD VSS / RSC_IHPSG13_NAND3X2 +XI1<0> NADR<0> NADR<1> NADR<2> addr_n<0> VDD VSS / RSC_IHPSG13_NAND3X2 +XDFF<2> BIST_EN_I BIST_ADDR<2> ACLK_N ADDR<2> padr_int<2> net6<0> VDD ++ VSS / RSC_IHPSG13_DFNQMX2IX1 +XDFF<1> BIST_EN_I BIST_ADDR<1> ACLK_N ADDR<1> padr_int<1> net6<1> VDD ++ VSS / RSC_IHPSG13_DFNQMX2IX1 +XDFF<0> BIST_EN_I BIST_ADDR<0> ACLK_N ADDR<0> padr_int<0> net6<2> VDD ++ VSS / RSC_IHPSG13_DFNQMX2IX1 +XI17<2> VDD VSS / RSC_IHPSG13_FILLCAP4 +XI17<1> VDD VSS / RSC_IHPSG13_FILLCAP4 +XI13<2> NADR<2> PADR<2> VDD VSS / RSC_IHPSG13_INVX2 +XI13<1> NADR<1> PADR<1> VDD VSS / RSC_IHPSG13_INVX2 +XI13<0> NADR<0> PADR<0> VDD VSS / RSC_IHPSG13_INVX2 +XI3<2> padr_int<2> NADR<2> VDD VSS / RSC_IHPSG13_INVX2 +XI3<1> padr_int<1> NADR<1> VDD VSS / RSC_IHPSG13_INVX2 +XI3<0> padr_int<0> NADR<0> VDD VSS / RSC_IHPSG13_INVX2 +XI2<7> addr_n<7> ADDR_DEC<7> VDD VSS / RSC_IHPSG13_INVX2 +XI2<6> addr_n<6> ADDR_DEC<6> VDD VSS / RSC_IHPSG13_INVX2 +XI2<5> addr_n<5> ADDR_DEC<5> VDD VSS / RSC_IHPSG13_INVX2 +XI2<4> addr_n<4> ADDR_DEC<4> VDD VSS / RSC_IHPSG13_INVX2 +XI2<3> addr_n<3> ADDR_DEC<3> VDD VSS / RSC_IHPSG13_INVX2 +XI2<2> addr_n<2> ADDR_DEC<2> VDD VSS / RSC_IHPSG13_INVX2 +XI2<1> addr_n<1> ADDR_DEC<1> VDD VSS / RSC_IHPSG13_INVX2 +XI2<0> addr_n<0> ADDR_DEC<0> VDD VSS / RSC_IHPSG13_INVX2 +XI16<6> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI16<5> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI16<4> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI16<3> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI16<2> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI16<1> VDD VSS / RSC_IHPSG13_FILLCAP8 +.ENDS +.SUBCKT RM_IHPSG13_64x32_c2_1P_COLCTRL3 A_ADDR_DEC<7> A_ADDR_DEC<6> A_ADDR_DEC<5> ++ A_ADDR_DEC<4> A_ADDR_DEC<3> A_ADDR_DEC<2> A_ADDR_DEC<1> A_ADDR_DEC<0> ++ A_BIST_BM_I A_BIST_DW_I A_BIST_EN_I A_BLC<7> A_BLC<6> A_BLC<5> A_BLC<4> ++ A_BLC<3> A_BLC<2> A_BLC<1> A_BLC<0> A_BLT<7> A_BLT<6> A_BLT<5> A_BLT<4> ++ A_BLT<3> A_BLT<2> A_BLT<1> A_BLT<0> A_BM_I A_DCLK_B_L A_DCLK_B_R A_DCLK_L ++ A_DCLK_R A_DR_O A_DW_I A_RCLK_B_L A_RCLK_B_R A_RCLK_L A_RCLK_R A_TIEH_O ++ A_WCLK_B_L A_WCLK_B_R A_WCLK_L A_WCLK_R VDD VSS +XA_DREG A_BIST_EN_I A_BIST_DW_I A_DCLK_B_L A_DW_I A_DI_R net22 VDD VSS ++ / RSC_IHPSG13_DFNQMX2IX1 +XA_BREG A_BIST_EN_I A_BIST_BM_I A_DCLK_B_R A_BM_I A_BM_R net23 VDD VSS ++ / RSC_IHPSG13_DFNQMX2IX1 +XA_I70<8> VDD VSS / RSC_IHPSG13_FILLCAP8 +XA_I70<7> VDD VSS / RSC_IHPSG13_FILLCAP8 +XA_I70<6> VDD VSS / RSC_IHPSG13_FILLCAP8 +XA_I70<5> VDD VSS / RSC_IHPSG13_FILLCAP8 +XA_I70<4> VDD VSS / RSC_IHPSG13_FILLCAP8 +XA_I70<3> VDD VSS / RSC_IHPSG13_FILLCAP8 +XA_I70<2> VDD VSS / RSC_IHPSG13_FILLCAP8 +XA_I70<1> VDD VSS / RSC_IHPSG13_FILLCAP8 +XA_I51 net19 A_DR_O VDD VSS / RSC_IHPSG13_INVX4 +XA_I44 A_BM_N A_WCLK_B_R A_DO_WRITE_P VDD VSS / RSC_IHPSG13_NOR2X2 +XA_BM_TIEH A_TIEH_O VDD VSS / RSC_IHPSG13_TIEH +XA_BLTMUX<7> A_BLC<7> A_BLC_SEL A_BLT<7> A_BLT_SEL A_PRE_N A_ADDR_DEC<7> ++ A_WR_ONE A_WR_ZERO VDD VSS / RM_IHPSG13_64x32_c2_1P_BLDRV +XA_BLTMUX<6> A_BLC<6> A_BLC_SEL A_BLT<6> A_BLT_SEL A_PRE_N A_ADDR_DEC<6> ++ A_WR_ONE A_WR_ZERO VDD VSS / RM_IHPSG13_64x32_c2_1P_BLDRV +XA_BLTMUX<5> A_BLC<5> A_BLC_SEL A_BLT<5> A_BLT_SEL A_PRE_N A_ADDR_DEC<5> ++ A_WR_ONE A_WR_ZERO VDD VSS / RM_IHPSG13_64x32_c2_1P_BLDRV +XA_BLTMUX<4> A_BLC<4> A_BLC_SEL A_BLT<4> A_BLT_SEL A_PRE_N A_ADDR_DEC<4> ++ A_WR_ONE A_WR_ZERO VDD VSS / RM_IHPSG13_64x32_c2_1P_BLDRV +XA_BLTMUX<3> A_BLC<3> A_BLC_SEL A_BLT<3> A_BLT_SEL A_PRE_N A_ADDR_DEC<3> ++ A_WR_ONE A_WR_ZERO VDD VSS / RM_IHPSG13_64x32_c2_1P_BLDRV +XA_BLTMUX<2> A_BLC<2> A_BLC_SEL A_BLT<2> A_BLT_SEL A_PRE_N A_ADDR_DEC<2> ++ A_WR_ONE A_WR_ZERO VDD VSS / RM_IHPSG13_64x32_c2_1P_BLDRV +XA_BLTMUX<1> A_BLC<1> A_BLC_SEL A_BLT<1> A_BLT_SEL A_PRE_N A_ADDR_DEC<1> ++ A_WR_ONE A_WR_ZERO VDD VSS / RM_IHPSG13_64x32_c2_1P_BLDRV +XA_BLTMUX<0> A_BLC<0> A_BLC_SEL A_BLT<0> A_BLT_SEL A_PRE_N A_ADDR_DEC<0> ++ A_WR_ONE A_WR_ZERO VDD VSS / RM_IHPSG13_64x32_c2_1P_BLDRV +XA_I49 A_DI_R A_DI_N VDD VSS / RSC_IHPSG13_INVX2 +XA_I83 A_BM_R A_BM_N VDD VSS / RSC_IHPSG13_INVX2 +XA_I69 A_DCLK_L A_DCLK_B_L VDD VSS / RSC_IHPSG13_CINVX2 +XA_I50 A_WCLK_L A_WCLK_B_L VDD VSS / RSC_IHPSG13_CINVX2 +XA_EBUF A_RCLK_L A_RCLK_B_L VDD VSS / RSC_IHPSG13_CINVX2 +XA_I78 A_RCLK_B_L A_SAE VDD VSS / RSC_IHPSG13_CBUFX2 +XA_I88 A_DCLK_L A_DCLK_R / RSC_IHPSG13_MET3RES +XA_I87 A_WCLK_L A_WCLK_R / RSC_IHPSG13_MET3RES +XA_R2 A_RCLK_L A_RCLK_R / RSC_IHPSG13_MET3RES +XA_I91 A_RCLK_B_L A_RCLK_B_R / RSC_IHPSG13_MET3RES +XA_I90 A_WCLK_B_L A_WCLK_B_R / RSC_IHPSG13_MET3RES +XA_I89 A_DCLK_B_L A_DCLK_B_R / RSC_IHPSG13_MET3RES +XA_I80 A_WCLK_B_R A_RCLK_B_R net21 VDD VSS / RSC_IHPSG13_AND2X2 +XA_I76 A_DI_N A_DO_WRITE_P A_WR_ZERO VDD VSS / RSC_IHPSG13_AND2X2 +XA_I75 A_DI_R A_DO_WRITE_P A_WR_ONE VDD VSS / RSC_IHPSG13_AND2X2 +XA_ISENSE A_SAE A_BLC_SEL A_BLT_SEL net19 net20 VDD VSS / ++ RSC_IHPSG13_DFPQD_MSAFFX2 +XA_I81 net21 A_PRE_N VDD VSS / RSC_IHPSG13_CINVX4_WN +XA_CAPS<5> VDD VSS / RSC_IHPSG13_FILLCAP4 +XA_CAPS<4> VDD VSS / RSC_IHPSG13_FILLCAP4 +XA_CAPS<3> VDD VSS / RSC_IHPSG13_FILLCAP4 +XA_CAPS<2> VDD VSS / RSC_IHPSG13_FILLCAP4 +XA_CAPS<1> VDD VSS / RSC_IHPSG13_FILLCAP4 +.ENDS + +.SUBCKT RM_IHPSG13_64x32_c2_2P_BITKIT_16x2_CORNER VDD_CORE VSS +XI16 VDD_CORE VSS VDD_CORE VSS / ++ RM_IHPSG13_64x32_c2_1P_BITKIT_CORNER +.ENDS +.SUBCKT RM_IHPSG13_64x32_c2_2P_BITKIT_EDGE_LR A_WL B_WL NW PW VDD VSS +MN1 VSS A_WL VSS VSS sg13_lv_nmos m=1 w=300.0n l=130.00n ng=1 nrd=0 nrs=0 +MN0 VSS B_WL VSS VSS sg13_lv_nmos m=1 w=300.0n l=130.00n ng=1 nrd=0 nrs=0 +.ENDS +.SUBCKT RM_IHPSG13_64x32_c2_2P_BITKIT_16x2_EDGE_LR A_WL<15> A_WL<14> A_WL<13> A_WL<12> ++ A_WL<11> A_WL<10> A_WL<9> A_WL<8> A_WL<7> A_WL<6> A_WL<5> A_WL<4> A_WL<3> ++ A_WL<2> A_WL<1> A_WL<0> B_WL<15> B_WL<14> B_WL<13> B_WL<12> B_WL<11> ++ B_WL<10> B_WL<9> B_WL<8> B_WL<7> B_WL<6> B_WL<5> B_WL<4> B_WL<3> B_WL<2> ++ B_WL<1> B_WL<0> VDD_CORE VSS +XI0<15> A_WL<15> B_WL<15> VDD_CORE VSS VDD_CORE VSS ++ / RM_IHPSG13_64x32_c2_2P_BITKIT_EDGE_LR +XI0<14> A_WL<14> B_WL<14> VDD_CORE VSS VDD_CORE VSS ++ / RM_IHPSG13_64x32_c2_2P_BITKIT_EDGE_LR +XI0<13> A_WL<13> B_WL<13> VDD_CORE VSS VDD_CORE VSS ++ / RM_IHPSG13_64x32_c2_2P_BITKIT_EDGE_LR +XI0<12> A_WL<12> B_WL<12> VDD_CORE VSS VDD_CORE VSS ++ / RM_IHPSG13_64x32_c2_2P_BITKIT_EDGE_LR +XI0<11> A_WL<11> B_WL<11> VDD_CORE VSS VDD_CORE VSS ++ / RM_IHPSG13_64x32_c2_2P_BITKIT_EDGE_LR +XI0<10> A_WL<10> B_WL<10> VDD_CORE VSS VDD_CORE VSS ++ / RM_IHPSG13_64x32_c2_2P_BITKIT_EDGE_LR +XI0<9> A_WL<9> B_WL<9> VDD_CORE VSS VDD_CORE VSS / ++ RM_IHPSG13_64x32_c2_2P_BITKIT_EDGE_LR +XI0<8> A_WL<8> B_WL<8> VDD_CORE VSS VDD_CORE VSS / ++ RM_IHPSG13_64x32_c2_2P_BITKIT_EDGE_LR +XI0<7> A_WL<7> B_WL<7> VDD_CORE VSS VDD_CORE VSS / ++ RM_IHPSG13_64x32_c2_2P_BITKIT_EDGE_LR +XI0<6> A_WL<6> B_WL<6> VDD_CORE VSS VDD_CORE VSS / ++ RM_IHPSG13_64x32_c2_2P_BITKIT_EDGE_LR +XI0<5> A_WL<5> B_WL<5> VDD_CORE VSS VDD_CORE VSS / ++ RM_IHPSG13_64x32_c2_2P_BITKIT_EDGE_LR +XI0<4> A_WL<4> B_WL<4> VDD_CORE VSS VDD_CORE VSS / ++ RM_IHPSG13_64x32_c2_2P_BITKIT_EDGE_LR +XI0<3> A_WL<3> B_WL<3> VDD_CORE VSS VDD_CORE VSS / ++ RM_IHPSG13_64x32_c2_2P_BITKIT_EDGE_LR +XI0<2> A_WL<2> B_WL<2> VDD_CORE VSS VDD_CORE VSS / ++ RM_IHPSG13_64x32_c2_2P_BITKIT_EDGE_LR +XI0<1> A_WL<1> B_WL<1> VDD_CORE VSS VDD_CORE VSS / ++ RM_IHPSG13_64x32_c2_2P_BITKIT_EDGE_LR +XI0<0> A_WL<0> B_WL<0> VDD_CORE VSS VDD_CORE VSS / ++ RM_IHPSG13_64x32_c2_2P_BITKIT_EDGE_LR +.ENDS +.SUBCKT RM_IHPSG13_64x32_c2_2P_BITKIT_CELL A_BLC_BOT A_BLC_TOP A_BLT_BOT A_BLT_TOP ++ A_LWL A_RWL B_BLC_BOT B_BLC_TOP B_BLT_BOT B_BLT_TOP B_LWL B_RWL NW PW VDD VSS +MN5 NC B_RWL B_BLC_BOT PW sg13_lv_nmos m=1 w=300.0n l=130.00n ng=1 nrd=0 nrs=0 +MN4 B_BLT_BOT B_LWL NT PW sg13_lv_nmos m=1 w=300.0n l=130.00n ng=1 nrd=0 nrs=0 +MN0 NC NT VSS PW sg13_lv_nmos m=1 w=600.0n l=130.00n ng=2 nrd=0 nrs=0 +MN1 NT NC VSS PW sg13_lv_nmos m=1 w=600.0n l=130.00n ng=2 nrd=0 nrs=0 +MN3 NC A_RWL A_BLC_TOP PW sg13_lv_nmos m=1 w=300.0n l=130.00n ng=1 nrd=0 nrs=0 +MN2 A_BLT_TOP A_LWL NT PW sg13_lv_nmos m=1 w=300.0n l=130.00n ng=1 nrd=0 nrs=0 +MP1 NT NC VDD NW sg13_lv_pmos m=1 w=150.00n l=130.00n ng=1 nrd=0 nrs=0 +MP0 NC NT VDD NW sg13_lv_pmos m=1 w=150.00n l=130.00n ng=1 nrd=0 nrs=0 +R5 B_RWL B_LWL lvsres w=2.6e-07 l=6e-07 +R4 B_BLC_BOT B_BLC_TOP lvsres w=2.6e-07 l=6e-07 +R3 B_BLT_BOT B_BLT_TOP lvsres w=2.6e-07 l=6e-07 +R1 A_BLC_BOT A_BLC_TOP lvsres w=2.6e-07 l=6e-07 +R0 A_BLT_BOT A_BLT_TOP lvsres w=2.6e-07 l=6e-07 +R2 A_RWL A_LWL lvsres w=2.6e-07 l=6e-07 +.ENDS +.SUBCKT RM_IHPSG13_64x32_c2_2P_BITKIT_16x2_SRAM A_BLC_BOT<1> A_BLC_BOT<0> A_BLC_TOP<1> ++ A_BLC_TOP<0> A_BLT_BOT<1> A_BLT_BOT<0> A_BLT_TOP<1> A_BLT_TOP<0> A_LWL<15> ++ A_LWL<14> A_LWL<13> A_LWL<12> A_LWL<11> A_LWL<10> A_LWL<9> A_LWL<8> A_LWL<7> ++ A_LWL<6> A_LWL<5> A_LWL<4> A_LWL<3> A_LWL<2> A_LWL<1> A_LWL<0> A_RWL<15> ++ A_RWL<14> A_RWL<13> A_RWL<12> A_RWL<11> A_RWL<10> A_RWL<9> A_RWL<8> A_RWL<7> ++ A_RWL<6> A_RWL<5> A_RWL<4> A_RWL<3> A_RWL<2> A_RWL<1> A_RWL<0> B_BLC_BOT<1> ++ B_BLC_BOT<0> B_BLC_TOP<1> B_BLC_TOP<0> B_BLT_BOT<1> B_BLT_BOT<0> ++ B_BLT_TOP<1> B_BLT_TOP<0> B_LWL<15> B_LWL<14> B_LWL<13> B_LWL<12> B_LWL<11> ++ B_LWL<10> B_LWL<9> B_LWL<8> B_LWL<7> B_LWL<6> B_LWL<5> B_LWL<4> B_LWL<3> ++ B_LWL<2> B_LWL<1> B_LWL<0> B_RWL<15> B_RWL<14> B_RWL<13> B_RWL<12> B_RWL<11> ++ B_RWL<10> B_RWL<9> B_RWL<8> B_RWL<7> B_RWL<6> B_RWL<5> B_RWL<4> B_RWL<3> ++ B_RWL<2> B_RWL<1> B_RWL<0> VDD_CORE VSS +XCELL<31> A_BLC_TOP<1> A_RBLC<15> A_BLT_TOP<1> A_RBLT<15> A_XWL<15> A_RWL<15> ++ B_BLC_TOP<1> B_RBLC<15> B_BLT_TOP<1> B_RBLT<15> B_XWL<15> B_RWL<15> ++ VDD_CORE VSS VDD_CORE VSS / ++ RM_IHPSG13_64x32_c2_2P_BITKIT_CELL +XCELL<30> A_RBLC<14> A_RBLC<15> A_RBLT<14> A_RBLT<15> A_XWL<14> A_RWL<14> ++ B_RBLC<14> B_RBLC<15> B_RBLT<14> B_RBLT<15> B_XWL<14> B_RWL<14> VDD_CORE ++ VSS VDD_CORE VSS / RM_IHPSG13_64x32_c2_2P_BITKIT_CELL +XCELL<29> A_RBLC<14> A_RBLC<13> A_RBLT<14> A_RBLT<13> A_XWL<13> A_RWL<13> ++ B_RBLC<14> B_RBLC<13> B_RBLT<14> B_RBLT<13> B_XWL<13> B_RWL<13> VDD_CORE ++ VSS VDD_CORE VSS / RM_IHPSG13_64x32_c2_2P_BITKIT_CELL +XCELL<28> A_RBLC<12> A_RBLC<13> A_RBLT<12> A_RBLT<13> A_XWL<12> A_RWL<12> ++ B_RBLC<12> B_RBLC<13> B_RBLT<12> B_RBLT<13> B_XWL<12> B_RWL<12> VDD_CORE ++ VSS VDD_CORE VSS / RM_IHPSG13_64x32_c2_2P_BITKIT_CELL +XCELL<27> A_RBLC<12> A_RBLC<11> A_RBLT<12> A_RBLT<11> A_XWL<11> A_RWL<11> ++ B_RBLC<12> B_RBLC<11> B_RBLT<12> B_RBLT<11> B_XWL<11> B_RWL<11> VDD_CORE ++ VSS VDD_CORE VSS / RM_IHPSG13_64x32_c2_2P_BITKIT_CELL +XCELL<26> A_RBLC<10> A_RBLC<11> A_RBLT<10> A_RBLT<11> A_XWL<10> A_RWL<10> ++ B_RBLC<10> B_RBLC<11> B_RBLT<10> B_RBLT<11> B_XWL<10> B_RWL<10> VDD_CORE ++ VSS VDD_CORE VSS / RM_IHPSG13_64x32_c2_2P_BITKIT_CELL +XCELL<25> A_RBLC<10> A_RBLC<9> A_RBLT<10> A_RBLT<9> A_XWL<9> A_RWL<9> ++ B_RBLC<10> B_RBLC<9> B_RBLT<10> B_RBLT<9> B_XWL<9> B_RWL<9> VDD_CORE ++ VSS VDD_CORE VSS / RM_IHPSG13_64x32_c2_2P_BITKIT_CELL +XCELL<24> A_RBLC<8> A_RBLC<9> A_RBLT<8> A_RBLT<9> A_XWL<8> A_RWL<8> B_RBLC<8> ++ B_RBLC<9> B_RBLT<8> B_RBLT<9> B_XWL<8> B_RWL<8> VDD_CORE VSS ++ VDD_CORE VSS / RM_IHPSG13_64x32_c2_2P_BITKIT_CELL +XCELL<23> A_RBLC<8> A_RBLC<7> A_RBLT<8> A_RBLT<7> A_XWL<7> A_RWL<7> B_RBLC<8> ++ B_RBLC<7> B_RBLT<8> B_RBLT<7> B_XWL<7> B_RWL<7> VDD_CORE VSS ++ VDD_CORE VSS / RM_IHPSG13_64x32_c2_2P_BITKIT_CELL +XCELL<22> A_RBLC<6> A_RBLC<7> A_RBLT<6> A_RBLT<7> A_XWL<6> A_RWL<6> B_RBLC<6> ++ B_RBLC<7> B_RBLT<6> B_RBLT<7> B_XWL<6> B_RWL<6> VDD_CORE VSS ++ VDD_CORE VSS / RM_IHPSG13_64x32_c2_2P_BITKIT_CELL +XCELL<21> A_RBLC<6> A_RBLC<5> A_RBLT<6> A_RBLT<5> A_XWL<5> A_RWL<5> B_RBLC<6> ++ B_RBLC<5> B_RBLT<6> B_RBLT<5> B_XWL<5> B_RWL<5> VDD_CORE VSS ++ VDD_CORE VSS / RM_IHPSG13_64x32_c2_2P_BITKIT_CELL +XCELL<20> A_RBLC<4> A_RBLC<5> A_RBLT<4> A_RBLT<5> A_XWL<4> A_RWL<4> B_RBLC<4> ++ B_RBLC<5> B_RBLT<4> B_RBLT<5> B_XWL<4> B_RWL<4> VDD_CORE VSS ++ VDD_CORE VSS / RM_IHPSG13_64x32_c2_2P_BITKIT_CELL +XCELL<19> A_RBLC<4> A_RBLC<3> A_RBLT<4> A_RBLT<3> A_XWL<3> A_RWL<3> B_RBLC<4> ++ B_RBLC<3> B_RBLT<4> B_RBLT<3> B_XWL<3> B_RWL<3> VDD_CORE VSS ++ VDD_CORE VSS / RM_IHPSG13_64x32_c2_2P_BITKIT_CELL +XCELL<18> A_RBLC<2> A_RBLC<3> A_RBLT<2> A_RBLT<3> A_XWL<2> A_RWL<2> B_RBLC<2> ++ B_RBLC<3> B_RBLT<2> B_RBLT<3> B_XWL<2> B_RWL<2> VDD_CORE VSS ++ VDD_CORE VSS / RM_IHPSG13_64x32_c2_2P_BITKIT_CELL +XCELL<17> A_RBLC<2> A_RBLC<1> A_RBLT<2> A_RBLT<1> A_XWL<1> A_RWL<1> B_RBLC<2> ++ B_RBLC<1> B_RBLT<2> B_RBLT<1> B_XWL<1> B_RWL<1> VDD_CORE VSS ++ VDD_CORE VSS / RM_IHPSG13_64x32_c2_2P_BITKIT_CELL +XCELL<16> A_BLC_BOT<1> A_RBLC<1> A_BLT_BOT<1> A_RBLT<1> A_XWL<0> A_RWL<0> ++ B_BLC_BOT<1> B_RBLC<1> B_BLT_BOT<1> B_RBLT<1> B_XWL<0> B_RWL<0> VDD_CORE ++ VSS VDD_CORE VSS / RM_IHPSG13_64x32_c2_2P_BITKIT_CELL +XCELL<15> A_BLC_TOP<0> A_LBLC<15> A_BLT_TOP<0> A_LBLT<15> A_LWL<15> A_XWL<15> ++ B_BLC_TOP<0> B_LBLC<15> B_BLT_TOP<0> B_LBLT<15> B_LWL<15> B_XWL<15> ++ VDD_CORE VSS VDD_CORE VSS / ++ RM_IHPSG13_64x32_c2_2P_BITKIT_CELL +XCELL<14> A_LBLC<14> A_LBLC<15> A_LBLT<14> A_LBLT<15> A_LWL<14> A_XWL<14> ++ B_LBLC<14> B_LBLC<15> B_LBLT<14> B_LBLT<15> B_LWL<14> B_XWL<14> VDD_CORE ++ VSS VDD_CORE VSS / RM_IHPSG13_64x32_c2_2P_BITKIT_CELL +XCELL<13> A_LBLC<14> A_LBLC<13> A_LBLT<14> A_LBLT<13> A_LWL<13> A_XWL<13> ++ B_LBLC<14> B_LBLC<13> B_LBLT<14> B_LBLT<13> B_LWL<13> B_XWL<13> VDD_CORE ++ VSS VDD_CORE VSS / RM_IHPSG13_64x32_c2_2P_BITKIT_CELL +XCELL<12> A_LBLC<12> A_LBLC<13> A_LBLT<12> A_LBLT<13> A_LWL<12> A_XWL<12> ++ B_LBLC<12> B_LBLC<13> B_LBLT<12> B_LBLT<13> B_LWL<12> B_XWL<12> VDD_CORE ++ VSS VDD_CORE VSS / RM_IHPSG13_64x32_c2_2P_BITKIT_CELL +XCELL<11> A_LBLC<12> A_LBLC<11> A_LBLT<12> A_LBLT<11> A_LWL<11> A_XWL<11> ++ B_LBLC<12> B_LBLC<11> B_LBLT<12> B_LBLT<11> B_LWL<11> B_XWL<11> VDD_CORE ++ VSS VDD_CORE VSS / RM_IHPSG13_64x32_c2_2P_BITKIT_CELL +XCELL<10> A_LBLC<10> A_LBLC<11> A_LBLT<10> A_LBLT<11> A_LWL<10> A_XWL<10> ++ B_LBLC<10> B_LBLC<11> B_LBLT<10> B_LBLT<11> B_LWL<10> B_XWL<10> VDD_CORE ++ VSS VDD_CORE VSS / RM_IHPSG13_64x32_c2_2P_BITKIT_CELL +XCELL<9> A_LBLC<10> A_LBLC<9> A_LBLT<10> A_LBLT<9> A_LWL<9> A_XWL<9> ++ B_LBLC<10> B_LBLC<9> B_LBLT<10> B_LBLT<9> B_LWL<9> B_XWL<9> VDD_CORE ++ VSS VDD_CORE VSS / RM_IHPSG13_64x32_c2_2P_BITKIT_CELL +XCELL<8> A_LBLC<8> A_LBLC<9> A_LBLT<8> A_LBLT<9> A_LWL<8> A_XWL<8> B_LBLC<8> ++ B_LBLC<9> B_LBLT<8> B_LBLT<9> B_LWL<8> B_XWL<8> VDD_CORE VSS ++ VDD_CORE VSS / RM_IHPSG13_64x32_c2_2P_BITKIT_CELL +XCELL<7> A_LBLC<8> A_LBLC<7> A_LBLT<8> A_LBLT<7> A_LWL<7> A_XWL<7> B_LBLC<8> ++ B_LBLC<7> B_LBLT<8> B_LBLT<7> B_LWL<7> B_XWL<7> VDD_CORE VSS ++ VDD_CORE VSS / RM_IHPSG13_64x32_c2_2P_BITKIT_CELL +XCELL<6> A_LBLC<6> A_LBLC<7> A_LBLT<6> A_LBLT<7> A_LWL<6> A_XWL<6> B_LBLC<6> ++ B_LBLC<7> B_LBLT<6> B_LBLT<7> B_LWL<6> B_XWL<6> VDD_CORE VSS ++ VDD_CORE VSS / RM_IHPSG13_64x32_c2_2P_BITKIT_CELL +XCELL<5> A_LBLC<6> A_LBLC<5> A_LBLT<6> A_LBLT<5> A_LWL<5> A_XWL<5> B_LBLC<6> ++ B_LBLC<5> B_LBLT<6> B_LBLT<5> B_LWL<5> B_XWL<5> VDD_CORE VSS ++ VDD_CORE VSS / RM_IHPSG13_64x32_c2_2P_BITKIT_CELL +XCELL<4> A_LBLC<4> A_LBLC<5> A_LBLT<4> A_LBLT<5> A_LWL<4> A_XWL<4> B_LBLC<4> ++ B_LBLC<5> B_LBLT<4> B_LBLT<5> B_LWL<4> B_XWL<4> VDD_CORE VSS ++ VDD_CORE VSS / RM_IHPSG13_64x32_c2_2P_BITKIT_CELL +XCELL<3> A_LBLC<4> A_LBLC<3> A_LBLT<4> A_LBLT<3> A_LWL<3> A_XWL<3> B_LBLC<4> ++ B_LBLC<3> B_LBLT<4> B_LBLT<3> B_LWL<3> B_XWL<3> VDD_CORE VSS ++ VDD_CORE VSS / RM_IHPSG13_64x32_c2_2P_BITKIT_CELL +XCELL<2> A_LBLC<2> A_LBLC<3> A_LBLT<2> A_LBLT<3> A_LWL<2> A_XWL<2> B_LBLC<2> ++ B_LBLC<3> B_LBLT<2> B_LBLT<3> B_LWL<2> B_XWL<2> VDD_CORE VSS ++ VDD_CORE VSS / RM_IHPSG13_64x32_c2_2P_BITKIT_CELL +XCELL<1> A_LBLC<2> A_LBLC<1> A_LBLT<2> A_LBLT<1> A_LWL<1> A_XWL<1> B_LBLC<2> ++ B_LBLC<1> B_LBLT<2> B_LBLT<1> B_LWL<1> B_XWL<1> VDD_CORE VSS ++ VDD_CORE VSS / RM_IHPSG13_64x32_c2_2P_BITKIT_CELL +XCELL<0> A_BLC_BOT<0> A_LBLC<1> A_BLT_BOT<0> A_LBLT<1> A_LWL<0> A_XWL<0> ++ B_BLC_BOT<0> B_LBLC<1> B_BLT_BOT<0> B_LBLT<1> B_LWL<0> B_XWL<0> VDD_CORE ++ VSS VDD_CORE VSS / RM_IHPSG13_64x32_c2_2P_BITKIT_CELL +.ENDS +.SUBCKT RM_IHPSG13_64x32_c2_2P_BITKIT_EDGE_TB A_BLC A_BLT B_BLC B_BLT NW PW VDD VSS +.ENDS +.SUBCKT RM_IHPSG13_64x32_c2_2P_BITKIT_16x2_EDGE_TB A_BLC<1> A_BLC<0> A_BLT<1> A_BLT<0> ++ B_BLC<1> B_BLC<0> B_BLT<1> B_BLT<0> VDD_CORE VSS +XEDGE<1> A_BLC<1> A_BLT<1> B_BLC<1> B_BLT<1> VDD_CORE VSS ++ VDD_CORE VSS / RM_IHPSG13_64x32_c2_2P_BITKIT_EDGE_TB +XEDGE<0> A_BLC<0> A_BLT<0> B_BLC<0> B_BLT<0> VDD_CORE VSS ++ VDD_CORE VSS / RM_IHPSG13_64x32_c2_2P_BITKIT_EDGE_TB +.ENDS +.SUBCKT RM_IHPSG13_64x32_c2_2P_BITKIT_TAP A_BLC A_BLT B_BLC B_BLT NW PW VDD VSS +.ENDS +.SUBCKT RM_IHPSG13_64x32_c2_2P_BITKIT_16x2_TAP A_BLC<1> A_BLC<0> A_BLT<1> A_BLT<0> ++ B_BLC<1> B_BLC<0> B_BLT<1> B_BLT<0> VDD_CORE VSS +XIEDGEBP_COL1<1> A_BLC<1> A_BLT<1> B_BLC<1> B_BLT<1> VDD_CORE VSS ++ VDD_CORE VSS / RM_IHPSG13_64x32_c2_2P_BITKIT_EDGE_TB +XIEDGEBP_COL1<0> A_BLC<1> A_BLT<1> B_BLC<1> B_BLT<1> VDD_CORE VSS ++ VDD_CORE VSS / RM_IHPSG13_64x32_c2_2P_BITKIT_EDGE_TB +XIEDGEBP_COL2<1> A_BLC<0> A_BLT<0> B_BLC<0> B_BLT<0> VDD_CORE VSS ++ VDD_CORE VSS / RM_IHPSG13_64x32_c2_2P_BITKIT_EDGE_TB +XIEDGEBP_COL2<0> A_BLC<0> A_BLT<0> B_BLC<0> B_BLT<0> VDD_CORE VSS ++ VDD_CORE VSS / RM_IHPSG13_64x32_c2_2P_BITKIT_EDGE_TB +XITAP<1> A_BLC<1> A_BLT<1> B_BLC<1> B_BLT<1> VDD_CORE VSS ++ VDD_CORE VSS / RM_IHPSG13_64x32_c2_2P_BITKIT_TAP +XITAP<0> A_BLC<0> A_BLT<0> B_BLC<0> B_BLT<0> VDD_CORE VSS ++ VDD_CORE VSS / RM_IHPSG13_64x32_c2_2P_BITKIT_TAP +.ENDS + + +.SUBCKT RM_IHPSG13_64x32_c2_1P_BITKIT_TAP_LR NW PW VDD VSS +.ENDS +.SUBCKT RM_IHPSG13_64x32_c2_2P_BITKIT_16x2_TAP_LR VDD_CORE VSS +XCORNER<1> VDD_CORE VSS VDD_CORE VSS / ++ RM_IHPSG13_64x32_c2_1P_BITKIT_CORNER +XCORNER<0> VDD_CORE VSS VDD_CORE VSS / ++ RM_IHPSG13_64x32_c2_1P_BITKIT_CORNER +XTAP_BORDER VDD_CORE VSS VDD_CORE VSS / ++ RM_IHPSG13_64x32_c2_1P_BITKIT_TAP_LR +.ENDS + +.SUBCKT RSC_IHPSG13_CBUFX12 A Z VDD VSS +MN1 Z net6 VSS VSS sg13_lv_nmos m=1 w=4.23u l=130.00n ng=6 nrd=0 nrs=0 +MN0 net6 A VSS VSS sg13_lv_nmos m=1 w=1.41u l=130.00n ng=2 nrd=0 nrs=0 +MP1 Z net6 VDD VDD sg13_lv_pmos m=1 w=9.72u l=130.00n ng=6 nrd=0 nrs=0 +MP0 net6 A VDD VDD sg13_lv_pmos m=1 w=3.24u l=130.00n ng=2 nrd=0 nrs=0 +.ENDS +.SUBCKT RM_IHPSG13_64x32_c2_2P_COLDRV13X12 ADDR_COL_I<1> ADDR_COL_I<0> ADDR_COL_O<1> ++ ADDR_COL_O<0> ADDR_DEC_I<7> ADDR_DEC_I<6> ADDR_DEC_I<5> ADDR_DEC_I<4> ++ ADDR_DEC_I<3> ADDR_DEC_I<2> ADDR_DEC_I<1> ADDR_DEC_I<0> ADDR_DEC_O<7> ++ ADDR_DEC_O<6> ADDR_DEC_O<5> ADDR_DEC_O<4> ADDR_DEC_O<3> ADDR_DEC_O<2> ++ ADDR_DEC_O<1> ADDR_DEC_O<0> DCLK_I DCLK_O RCLK_I RCLK_O WCLK_I WCLK_O ++ VDD VSS +XI1<3> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI1<2> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI1<1> VDD VSS / RSC_IHPSG13_FILLCAP8 +XWCLK_DRV WCLK_I WCLK_O VDD VSS / RSC_IHPSG13_CBUFX12 +XRCLK_DRV RCLK_I RCLK_O VDD VSS / RSC_IHPSG13_CBUFX12 +XDCLK_DRV DCLK_I DCLK_O VDD VSS / RSC_IHPSG13_CBUFX12 +XADDR_COL_DRV<1> ADDR_COL_I<1> ADDR_COL_O<1> VDD VSS / ++ RSC_IHPSG13_CBUFX12 +XADDR_COL_DRV<0> ADDR_COL_I<0> ADDR_COL_O<0> VDD VSS / ++ RSC_IHPSG13_CBUFX12 +XADDR_DEC_DRV<7> ADDR_DEC_I<7> ADDR_DEC_O<7> VDD VSS / ++ RSC_IHPSG13_CBUFX12 +XADDR_DEC_DRV<6> ADDR_DEC_I<6> ADDR_DEC_O<6> VDD VSS / ++ RSC_IHPSG13_CBUFX12 +XADDR_DEC_DRV<5> ADDR_DEC_I<5> ADDR_DEC_O<5> VDD VSS / ++ RSC_IHPSG13_CBUFX12 +XADDR_DEC_DRV<4> ADDR_DEC_I<4> ADDR_DEC_O<4> VDD VSS / ++ RSC_IHPSG13_CBUFX12 +XADDR_DEC_DRV<3> ADDR_DEC_I<3> ADDR_DEC_O<3> VDD VSS / ++ RSC_IHPSG13_CBUFX12 +XADDR_DEC_DRV<2> ADDR_DEC_I<2> ADDR_DEC_O<2> VDD VSS / ++ RSC_IHPSG13_CBUFX12 +XADDR_DEC_DRV<1> ADDR_DEC_I<1> ADDR_DEC_O<1> VDD VSS / ++ RSC_IHPSG13_CBUFX12 +XADDR_DEC_DRV<0> ADDR_DEC_I<0> ADDR_DEC_O<0> VDD VSS / ++ RSC_IHPSG13_CBUFX12 +XI0<6> VDD VSS / RSC_IHPSG13_FILLCAP4 +XI0<5> VDD VSS / RSC_IHPSG13_FILLCAP4 +XI0<4> VDD VSS / RSC_IHPSG13_FILLCAP4 +XI0<3> VDD VSS / RSC_IHPSG13_FILLCAP4 +XI0<2> VDD VSS / RSC_IHPSG13_FILLCAP4 +XI0<1> VDD VSS / RSC_IHPSG13_FILLCAP4 +.ENDS +.SUBCKT RSC_IHPSG13_WLDRVX12 A Z VDD VSS +MN1 Z net6 VSS VSS sg13_lv_nmos m=1 w=1.41u l=130.00n ng=2 nrd=0 nrs=0 +MN0 net6 A VSS VSS sg13_lv_nmos m=1 w=1.8u l=130.00n ng=2 nrd=0 nrs=0 +MP1 Z net6 VDD VDD sg13_lv_pmos m=1 w=9.72u l=130.00n ng=6 nrd=0 nrs=0 +MP0 net6 A VDD VDD sg13_lv_pmos m=1 w=900.0n l=130.00n ng=1 nrd=0 nrs=0 +.ENDS +.SUBCKT RM_IHPSG13_64x32_c2_2P_WLDRV16X12 A<15> A<14> A<13> A<12> A<11> A<10> A<9> A<8> ++ A<7> A<6> A<5> A<4> A<3> A<2> A<1> A<0> Z<15> Z<14> Z<13> Z<12> Z<11> Z<10> ++ Z<9> Z<8> Z<7> Z<6> Z<5> Z<4> Z<3> Z<2> Z<1> Z<0> VDD VSS +XBUF<15> A<15> Z<15> VDD VSS / RSC_IHPSG13_WLDRVX12 +XBUF<14> A<14> Z<14> VDD VSS / RSC_IHPSG13_WLDRVX12 +XBUF<13> A<13> Z<13> VDD VSS / RSC_IHPSG13_WLDRVX12 +XBUF<12> A<12> Z<12> VDD VSS / RSC_IHPSG13_WLDRVX12 +XBUF<11> A<11> Z<11> VDD VSS / RSC_IHPSG13_WLDRVX12 +XBUF<10> A<10> Z<10> VDD VSS / RSC_IHPSG13_WLDRVX12 +XBUF<9> A<9> Z<9> VDD VSS / RSC_IHPSG13_WLDRVX12 +XBUF<8> A<8> Z<8> VDD VSS / RSC_IHPSG13_WLDRVX12 +XBUF<7> A<7> Z<7> VDD VSS / RSC_IHPSG13_WLDRVX12 +XBUF<6> A<6> Z<6> VDD VSS / RSC_IHPSG13_WLDRVX12 +XBUF<5> A<5> Z<5> VDD VSS / RSC_IHPSG13_WLDRVX12 +XBUF<4> A<4> Z<4> VDD VSS / RSC_IHPSG13_WLDRVX12 +XBUF<3> A<3> Z<3> VDD VSS / RSC_IHPSG13_WLDRVX12 +XBUF<2> A<2> Z<2> VDD VSS / RSC_IHPSG13_WLDRVX12 +XBUF<1> A<1> Z<1> VDD VSS / RSC_IHPSG13_WLDRVX12 +XBUF<0> A<0> Z<0> VDD VSS / RSC_IHPSG13_WLDRVX12 +.ENDS +.SUBCKT RM_IHPSG13_64x32_c2_2P_DEC04 ADDR<3> ADDR<2> ADDR<1> ADDR<0> CS ECLK_H_BOT ++ ECLK_H_TOP ECLK_L_BOT ECLK_L_TOP WL<15> WL<14> WL<13> WL<12> WL<11> WL<10> ++ WL<9> WL<8> WL<7> WL<6> WL<5> WL<4> WL<3> WL<2> WL<1> WL<0> VDD VSS +XI0<3> PADR<1> PADR<0> sel01<3> VDD VSS / RSC_IHPSG13_NAND2X2 +XI0<2> PADR<1> NADR<0> sel01<2> VDD VSS / RSC_IHPSG13_NAND2X2 +XI0<1> NADR<1> PADR<0> sel01<1> VDD VSS / RSC_IHPSG13_NAND2X2 +XI0<0> NADR<1> NADR<0> sel01<0> VDD VSS / RSC_IHPSG13_NAND2X2 +XI4 ECLK_L_BOT EN VDD VSS / RSC_IHPSG13_CINVX4 +XI5 ECLK_H_BOT ECLK_L_BOT VDD VSS / RSC_IHPSG13_CINVX2 +XI3<3> PADR<3> NADR<3> VDD VSS / RSC_IHPSG13_INVX2 +XI3<2> PADR<2> NADR<2> VDD VSS / RSC_IHPSG13_INVX2 +XI3<1> PADR<1> NADR<1> VDD VSS / RSC_IHPSG13_INVX2 +XI3<0> PADR<0> NADR<0> VDD VSS / RSC_IHPSG13_INVX2 +XR0 ECLK_H_BOT ECLK_H_TOP / RSC_IHPSG13_MET2RES +XI11 ECLK_L_BOT ECLK_L_TOP / RSC_IHPSG13_MET2RES +XI1<3> PADR<2> PADR<3> CS sel23<3> VDD VSS / RSC_IHPSG13_NAND3X2 +XI1<2> NADR<2> PADR<3> CS sel23<2> VDD VSS / RSC_IHPSG13_NAND3X2 +XI1<1> PADR<2> NADR<3> CS sel23<1> VDD VSS / RSC_IHPSG13_NAND3X2 +XI1<0> NADR<2> NADR<3> CS sel23<0> VDD VSS / RSC_IHPSG13_NAND3X2 +XI2<15> sel23<3> sel01<3> EN WL<15> VDD VSS / RSC_IHPSG13_NOR3X2 +XI2<14> sel23<3> sel01<2> EN WL<14> VDD VSS / RSC_IHPSG13_NOR3X2 +XI2<13> sel23<3> sel01<1> EN WL<13> VDD VSS / RSC_IHPSG13_NOR3X2 +XI2<12> sel23<3> sel01<0> EN WL<12> VDD VSS / RSC_IHPSG13_NOR3X2 +XI2<11> sel23<2> sel01<3> EN WL<11> VDD VSS / RSC_IHPSG13_NOR3X2 +XI2<10> sel23<2> sel01<2> EN WL<10> VDD VSS / RSC_IHPSG13_NOR3X2 +XI2<9> sel23<2> sel01<1> EN WL<9> VDD VSS / RSC_IHPSG13_NOR3X2 +XI2<8> sel23<2> sel01<0> EN WL<8> VDD VSS / RSC_IHPSG13_NOR3X2 +XI2<7> sel23<1> sel01<3> EN WL<7> VDD VSS / RSC_IHPSG13_NOR3X2 +XI2<6> sel23<1> sel01<2> EN WL<6> VDD VSS / RSC_IHPSG13_NOR3X2 +XI2<5> sel23<1> sel01<1> EN WL<5> VDD VSS / RSC_IHPSG13_NOR3X2 +XI2<4> sel23<1> sel01<0> EN WL<4> VDD VSS / RSC_IHPSG13_NOR3X2 +XI2<3> sel23<0> sel01<3> EN WL<3> VDD VSS / RSC_IHPSG13_NOR3X2 +XI2<2> sel23<0> sel01<2> EN WL<2> VDD VSS / RSC_IHPSG13_NOR3X2 +XI2<1> sel23<0> sel01<1> EN WL<1> VDD VSS / RSC_IHPSG13_NOR3X2 +XI2<0> sel23<0> sel01<0> EN WL<0> VDD VSS / RSC_IHPSG13_NOR3X2 +XCAPS4 VDD VSS / RSC_IHPSG13_FILLCAP4 +XLATCH<3> CS ADDR<3> PADR<3> VDD VSS / RSC_IHPSG13_LHPQX2 +XLATCH<2> CS ADDR<2> PADR<2> VDD VSS / RSC_IHPSG13_LHPQX2 +XLATCH<1> CS ADDR<1> PADR<1> VDD VSS / RSC_IHPSG13_LHPQX2 +XLATCH<0> CS ADDR<0> PADR<0> VDD VSS / RSC_IHPSG13_LHPQX2 +.ENDS +.SUBCKT RM_IHPSG13_64x32_c2_2P_DEC02 ADDR<1> ADDR<0> CS CS_OUT VDD VSS +XDEC ADDR<1> NADDR<0> CS net1 VDD VSS / RSC_IHPSG13_NAND3X2 +XADDRINV ADDR<0> NADDR<0> VDD VSS / RSC_IHPSG13_INVX2 +XDECINV net1 CS_OUT VDD VSS / RSC_IHPSG13_INVX4 +XI2<1> VDD VSS / RSC_IHPSG13_FILLCAP4 +XI2<0> VDD VSS / RSC_IHPSG13_FILLCAP4 +.ENDS +.SUBCKT RM_IHPSG13_64x32_c2_2P_DEC01 ADDR<1> ADDR<0> CS CS_OUT VDD VSS +XDEC NADDR<1> ADDR<0> CS net1 VDD VSS / RSC_IHPSG13_NAND3X2 +XADDRINV ADDR<1> NADDR<1> VDD VSS / RSC_IHPSG13_INVX2 +XDECINV net1 CS_OUT VDD VSS / RSC_IHPSG13_INVX4 +XI2<1> VDD VSS / RSC_IHPSG13_FILLCAP4 +XI2<0> VDD VSS / RSC_IHPSG13_FILLCAP4 +.ENDS +.SUBCKT RM_IHPSG13_64x32_c2_2P_DEC00 ADDR<1> ADDR<0> CS CS_OUT VDD VSS +XDEC NADDR<1> NADDR<0> CS net1 VDD VSS / RSC_IHPSG13_NAND3X2 +XADDRINV<1> ADDR<1> NADDR<1> VDD VSS / RSC_IHPSG13_INVX2 +XADDRINV<0> ADDR<0> NADDR<0> VDD VSS / RSC_IHPSG13_INVX2 +XI1<1> VDD VSS / RSC_IHPSG13_FILLCAP4 +XI1<0> VDD VSS / RSC_IHPSG13_FILLCAP4 +XDECINV net1 CS_OUT VDD VSS / RSC_IHPSG13_INVX4 +.ENDS +.SUBCKT RM_IHPSG13_64x32_c2_2P_DEC03 ADDR<1> ADDR<0> CS CS_OUT VDD VSS +XDEC ADDR<1> ADDR<0> CS net1 VDD VSS / RSC_IHPSG13_NAND3X2 +XDECINV net1 CS_OUT VDD VSS / RSC_IHPSG13_INVX4 +XI0<1> VDD VSS / RSC_IHPSG13_FILLCAP4 +XI0<0> VDD VSS / RSC_IHPSG13_FILLCAP4 +.ENDS +.SUBCKT RM_IHPSG13_64x32_c2_2P_ROWDEC9 ADDR_N_I<8> ADDR_N_I<7> ADDR_N_I<6> ADDR_N_I<5> ++ ADDR_N_I<4> ADDR_N_I<3> ADDR_N_I<2> ADDR_N_I<1> ADDR_N_I<0> CS_I ECLK_I ++ WL_O<511> WL_O<510> WL_O<509> WL_O<508> WL_O<507> WL_O<506> WL_O<505> ++ WL_O<504> WL_O<503> WL_O<502> WL_O<501> WL_O<500> WL_O<499> WL_O<498> ++ WL_O<497> WL_O<496> WL_O<495> WL_O<494> WL_O<493> WL_O<492> WL_O<491> ++ WL_O<490> WL_O<489> WL_O<488> WL_O<487> WL_O<486> WL_O<485> WL_O<484> ++ WL_O<483> WL_O<482> WL_O<481> WL_O<480> WL_O<479> WL_O<478> WL_O<477> ++ WL_O<476> WL_O<475> WL_O<474> WL_O<473> WL_O<472> WL_O<471> WL_O<470> ++ WL_O<469> WL_O<468> WL_O<467> WL_O<466> WL_O<465> WL_O<464> WL_O<463> ++ WL_O<462> WL_O<461> WL_O<460> WL_O<459> WL_O<458> WL_O<457> WL_O<456> ++ WL_O<455> WL_O<454> WL_O<453> WL_O<452> WL_O<451> WL_O<450> WL_O<449> ++ WL_O<448> WL_O<447> WL_O<446> WL_O<445> WL_O<444> WL_O<443> WL_O<442> ++ WL_O<441> WL_O<440> WL_O<439> WL_O<438> WL_O<437> WL_O<436> WL_O<435> ++ WL_O<434> WL_O<433> WL_O<432> WL_O<431> WL_O<430> WL_O<429> WL_O<428> ++ WL_O<427> WL_O<426> WL_O<425> WL_O<424> WL_O<423> WL_O<422> WL_O<421> ++ WL_O<420> WL_O<419> WL_O<418> WL_O<417> WL_O<416> WL_O<415> WL_O<414> ++ WL_O<413> WL_O<412> WL_O<411> WL_O<410> WL_O<409> WL_O<408> WL_O<407> ++ WL_O<406> WL_O<405> WL_O<404> WL_O<403> WL_O<402> WL_O<401> WL_O<400> ++ WL_O<399> WL_O<398> WL_O<397> WL_O<396> WL_O<395> WL_O<394> WL_O<393> ++ WL_O<392> WL_O<391> WL_O<390> WL_O<389> WL_O<388> WL_O<387> WL_O<386> ++ WL_O<385> WL_O<384> WL_O<383> WL_O<382> WL_O<381> WL_O<380> WL_O<379> ++ WL_O<378> WL_O<377> WL_O<376> WL_O<375> WL_O<374> WL_O<373> WL_O<372> ++ WL_O<371> WL_O<370> WL_O<369> WL_O<368> WL_O<367> WL_O<366> WL_O<365> ++ WL_O<364> WL_O<363> WL_O<362> WL_O<361> WL_O<360> WL_O<359> WL_O<358> ++ WL_O<357> WL_O<356> WL_O<355> WL_O<354> WL_O<353> WL_O<352> WL_O<351> ++ WL_O<350> WL_O<349> WL_O<348> WL_O<347> WL_O<346> WL_O<345> WL_O<344> ++ WL_O<343> WL_O<342> WL_O<341> WL_O<340> WL_O<339> WL_O<338> WL_O<337> ++ WL_O<336> WL_O<335> WL_O<334> WL_O<333> WL_O<332> WL_O<331> WL_O<330> ++ WL_O<329> WL_O<328> WL_O<327> WL_O<326> WL_O<325> WL_O<324> WL_O<323> ++ WL_O<322> WL_O<321> WL_O<320> WL_O<319> WL_O<318> WL_O<317> WL_O<316> ++ WL_O<315> WL_O<314> WL_O<313> WL_O<312> WL_O<311> WL_O<310> WL_O<309> ++ WL_O<308> WL_O<307> WL_O<306> WL_O<305> WL_O<304> WL_O<303> WL_O<302> ++ WL_O<301> WL_O<300> WL_O<299> WL_O<298> WL_O<297> WL_O<296> WL_O<295> ++ WL_O<294> WL_O<293> WL_O<292> WL_O<291> WL_O<290> WL_O<289> WL_O<288> ++ WL_O<287> WL_O<286> WL_O<285> WL_O<284> WL_O<283> WL_O<282> WL_O<281> ++ WL_O<280> WL_O<279> WL_O<278> WL_O<277> WL_O<276> WL_O<275> WL_O<274> ++ WL_O<273> WL_O<272> WL_O<271> WL_O<270> WL_O<269> WL_O<268> WL_O<267> ++ WL_O<266> WL_O<265> WL_O<264> WL_O<263> WL_O<262> WL_O<261> WL_O<260> ++ WL_O<259> WL_O<258> WL_O<257> WL_O<256> WL_O<255> WL_O<254> WL_O<253> ++ WL_O<252> WL_O<251> WL_O<250> WL_O<249> WL_O<248> WL_O<247> WL_O<246> ++ WL_O<245> WL_O<244> WL_O<243> WL_O<242> WL_O<241> WL_O<240> WL_O<239> ++ WL_O<238> WL_O<237> WL_O<236> WL_O<235> WL_O<234> WL_O<233> WL_O<232> ++ WL_O<231> WL_O<230> WL_O<229> WL_O<228> WL_O<227> WL_O<226> WL_O<225> ++ WL_O<224> WL_O<223> WL_O<222> WL_O<221> WL_O<220> WL_O<219> WL_O<218> ++ WL_O<217> WL_O<216> WL_O<215> WL_O<214> WL_O<213> WL_O<212> WL_O<211> ++ WL_O<210> WL_O<209> WL_O<208> WL_O<207> WL_O<206> WL_O<205> WL_O<204> ++ WL_O<203> WL_O<202> WL_O<201> WL_O<200> WL_O<199> WL_O<198> WL_O<197> ++ WL_O<196> WL_O<195> WL_O<194> WL_O<193> WL_O<192> WL_O<191> WL_O<190> ++ WL_O<189> WL_O<188> WL_O<187> WL_O<186> WL_O<185> WL_O<184> WL_O<183> ++ WL_O<182> WL_O<181> WL_O<180> WL_O<179> WL_O<178> WL_O<177> WL_O<176> ++ WL_O<175> WL_O<174> WL_O<173> WL_O<172> WL_O<171> WL_O<170> WL_O<169> ++ WL_O<168> WL_O<167> WL_O<166> WL_O<165> WL_O<164> WL_O<163> WL_O<162> ++ WL_O<161> WL_O<160> WL_O<159> WL_O<158> WL_O<157> WL_O<156> WL_O<155> ++ WL_O<154> WL_O<153> WL_O<152> WL_O<151> WL_O<150> WL_O<149> WL_O<148> ++ WL_O<147> WL_O<146> WL_O<145> WL_O<144> WL_O<143> WL_O<142> WL_O<141> ++ WL_O<140> WL_O<139> WL_O<138> WL_O<137> WL_O<136> WL_O<135> WL_O<134> ++ WL_O<133> WL_O<132> WL_O<131> WL_O<130> WL_O<129> WL_O<128> WL_O<127> ++ WL_O<126> WL_O<125> WL_O<124> WL_O<123> WL_O<122> WL_O<121> WL_O<120> ++ WL_O<119> WL_O<118> WL_O<117> WL_O<116> WL_O<115> WL_O<114> WL_O<113> ++ WL_O<112> WL_O<111> WL_O<110> WL_O<109> WL_O<108> WL_O<107> WL_O<106> ++ WL_O<105> WL_O<104> WL_O<103> WL_O<102> WL_O<101> WL_O<100> WL_O<99> ++ WL_O<98> WL_O<97> WL_O<96> WL_O<95> WL_O<94> WL_O<93> WL_O<92> WL_O<91> ++ WL_O<90> WL_O<89> WL_O<88> WL_O<87> WL_O<86> WL_O<85> WL_O<84> WL_O<83> ++ WL_O<82> WL_O<81> WL_O<80> WL_O<79> WL_O<78> WL_O<77> WL_O<76> WL_O<75> ++ WL_O<74> WL_O<73> WL_O<72> WL_O<71> WL_O<70> WL_O<69> WL_O<68> WL_O<67> ++ WL_O<66> WL_O<65> WL_O<64> WL_O<63> WL_O<62> WL_O<61> WL_O<60> WL_O<59> ++ WL_O<58> WL_O<57> WL_O<56> WL_O<55> WL_O<54> WL_O<53> WL_O<52> WL_O<51> ++ WL_O<50> WL_O<49> WL_O<48> WL_O<47> WL_O<46> WL_O<45> WL_O<44> WL_O<43> ++ WL_O<42> WL_O<41> WL_O<40> WL_O<39> WL_O<38> WL_O<37> WL_O<36> WL_O<35> ++ WL_O<34> WL_O<33> WL_O<32> WL_O<31> WL_O<30> WL_O<29> WL_O<28> WL_O<27> ++ WL_O<26> WL_O<25> WL_O<24> WL_O<23> WL_O<22> WL_O<21> WL_O<20> WL_O<19> ++ WL_O<18> WL_O<17> WL_O<16> WL_O<15> WL_O<14> WL_O<13> WL_O<12> WL_O<11> ++ WL_O<10> WL_O<9> WL_O<8> WL_O<7> WL_O<6> WL_O<5> WL_O<4> WL_O<3> WL_O<2> ++ WL_O<1> WL_O<0> VDD VSS +XSEL<31> ADDR_N_I<3> ADDR_N_I<2> ADDR_N_I<1> ADDR_N_I<0> CS00<31> ECLK_H<31> ++ ECLK_H<32> ECLK_B<31> ECLK_B<32> WL_O<511> WL_O<510> WL_O<509> WL_O<508> ++ WL_O<507> WL_O<506> WL_O<505> WL_O<504> WL_O<503> WL_O<502> WL_O<501> ++ WL_O<500> WL_O<499> WL_O<498> WL_O<497> WL_O<496> VDD VSS / ++ RM_IHPSG13_64x32_c2_2P_DEC04 +XSEL<30> ADDR_N_I<3> ADDR_N_I<2> ADDR_N_I<1> ADDR_N_I<0> CS00<30> ECLK_H<30> ++ ECLK_H<31> ECLK_B<30> ECLK_B<31> WL_O<495> WL_O<494> WL_O<493> WL_O<492> ++ WL_O<491> WL_O<490> WL_O<489> WL_O<488> WL_O<487> WL_O<486> WL_O<485> ++ WL_O<484> WL_O<483> WL_O<482> WL_O<481> WL_O<480> VDD VSS / ++ RM_IHPSG13_64x32_c2_2P_DEC04 +XSEL<29> ADDR_N_I<3> ADDR_N_I<2> ADDR_N_I<1> ADDR_N_I<0> CS00<29> ECLK_H<29> ++ ECLK_H<30> ECLK_B<29> ECLK_B<30> WL_O<479> WL_O<478> WL_O<477> WL_O<476> ++ WL_O<475> WL_O<474> WL_O<473> WL_O<472> WL_O<471> WL_O<470> WL_O<469> ++ WL_O<468> WL_O<467> WL_O<466> WL_O<465> WL_O<464> VDD VSS / ++ RM_IHPSG13_64x32_c2_2P_DEC04 +XSEL<28> ADDR_N_I<3> ADDR_N_I<2> ADDR_N_I<1> ADDR_N_I<0> CS00<28> ECLK_H<28> ++ ECLK_H<29> ECLK_B<28> ECLK_B<29> WL_O<463> WL_O<462> WL_O<461> WL_O<460> ++ WL_O<459> WL_O<458> WL_O<457> WL_O<456> WL_O<455> WL_O<454> WL_O<453> ++ WL_O<452> WL_O<451> WL_O<450> WL_O<449> WL_O<448> VDD VSS / ++ RM_IHPSG13_64x32_c2_2P_DEC04 +XSEL<27> ADDR_N_I<3> ADDR_N_I<2> ADDR_N_I<1> ADDR_N_I<0> CS00<27> ECLK_H<27> ++ ECLK_H<28> ECLK_B<27> ECLK_B<28> WL_O<447> WL_O<446> WL_O<445> WL_O<444> ++ WL_O<443> WL_O<442> WL_O<441> WL_O<440> WL_O<439> WL_O<438> WL_O<437> ++ WL_O<436> WL_O<435> WL_O<434> WL_O<433> WL_O<432> VDD VSS / ++ RM_IHPSG13_64x32_c2_2P_DEC04 +XSEL<26> ADDR_N_I<3> ADDR_N_I<2> ADDR_N_I<1> ADDR_N_I<0> CS00<26> ECLK_H<26> ++ ECLK_H<27> ECLK_B<26> ECLK_B<27> WL_O<431> WL_O<430> WL_O<429> WL_O<428> ++ WL_O<427> WL_O<426> WL_O<425> WL_O<424> WL_O<423> WL_O<422> WL_O<421> ++ WL_O<420> WL_O<419> WL_O<418> WL_O<417> WL_O<416> VDD VSS / ++ RM_IHPSG13_64x32_c2_2P_DEC04 +XSEL<25> ADDR_N_I<3> ADDR_N_I<2> ADDR_N_I<1> ADDR_N_I<0> CS00<25> ECLK_H<25> ++ ECLK_H<26> ECLK_B<25> ECLK_B<26> WL_O<415> WL_O<414> WL_O<413> WL_O<412> ++ WL_O<411> WL_O<410> WL_O<409> WL_O<408> WL_O<407> WL_O<406> WL_O<405> ++ WL_O<404> WL_O<403> WL_O<402> WL_O<401> WL_O<400> VDD VSS / ++ RM_IHPSG13_64x32_c2_2P_DEC04 +XSEL<24> ADDR_N_I<3> ADDR_N_I<2> ADDR_N_I<1> ADDR_N_I<0> CS00<24> ECLK_H<24> ++ ECLK_H<25> ECLK_B<24> ECLK_B<25> WL_O<399> WL_O<398> WL_O<397> WL_O<396> ++ WL_O<395> WL_O<394> WL_O<393> WL_O<392> WL_O<391> WL_O<390> WL_O<389> ++ WL_O<388> WL_O<387> WL_O<386> WL_O<385> WL_O<384> VDD VSS / ++ RM_IHPSG13_64x32_c2_2P_DEC04 +XSEL<23> ADDR_N_I<3> ADDR_N_I<2> ADDR_N_I<1> ADDR_N_I<0> CS00<23> ECLK_H<23> ++ ECLK_H<24> ECLK_B<23> ECLK_B<24> WL_O<383> WL_O<382> WL_O<381> WL_O<380> ++ WL_O<379> WL_O<378> WL_O<377> WL_O<376> WL_O<375> WL_O<374> WL_O<373> ++ WL_O<372> WL_O<371> WL_O<370> WL_O<369> WL_O<368> VDD VSS / ++ RM_IHPSG13_64x32_c2_2P_DEC04 +XSEL<22> ADDR_N_I<3> ADDR_N_I<2> ADDR_N_I<1> ADDR_N_I<0> CS00<22> ECLK_H<22> ++ ECLK_H<23> ECLK_B<22> ECLK_B<23> WL_O<367> WL_O<366> WL_O<365> WL_O<364> ++ WL_O<363> WL_O<362> WL_O<361> WL_O<360> WL_O<359> WL_O<358> WL_O<357> ++ WL_O<356> WL_O<355> WL_O<354> WL_O<353> WL_O<352> VDD VSS / ++ RM_IHPSG13_64x32_c2_2P_DEC04 +XSEL<21> ADDR_N_I<3> ADDR_N_I<2> ADDR_N_I<1> ADDR_N_I<0> CS00<21> ECLK_H<21> ++ ECLK_H<22> ECLK_B<21> ECLK_B<22> WL_O<351> WL_O<350> WL_O<349> WL_O<348> ++ WL_O<347> WL_O<346> WL_O<345> WL_O<344> WL_O<343> WL_O<342> WL_O<341> ++ WL_O<340> WL_O<339> WL_O<338> WL_O<337> WL_O<336> VDD VSS / ++ RM_IHPSG13_64x32_c2_2P_DEC04 +XSEL<20> ADDR_N_I<3> ADDR_N_I<2> ADDR_N_I<1> ADDR_N_I<0> CS00<20> ECLK_H<20> ++ ECLK_H<21> ECLK_B<20> ECLK_B<21> WL_O<335> WL_O<334> WL_O<333> WL_O<332> ++ WL_O<331> WL_O<330> WL_O<329> WL_O<328> WL_O<327> WL_O<326> WL_O<325> ++ WL_O<324> WL_O<323> WL_O<322> WL_O<321> WL_O<320> VDD VSS / ++ RM_IHPSG13_64x32_c2_2P_DEC04 +XSEL<19> ADDR_N_I<3> ADDR_N_I<2> ADDR_N_I<1> ADDR_N_I<0> CS00<19> ECLK_H<19> ++ ECLK_H<20> ECLK_B<19> ECLK_B<20> WL_O<319> WL_O<318> WL_O<317> WL_O<316> ++ WL_O<315> WL_O<314> WL_O<313> WL_O<312> WL_O<311> WL_O<310> WL_O<309> ++ WL_O<308> WL_O<307> WL_O<306> WL_O<305> WL_O<304> VDD VSS / ++ RM_IHPSG13_64x32_c2_2P_DEC04 +XSEL<18> ADDR_N_I<3> ADDR_N_I<2> ADDR_N_I<1> ADDR_N_I<0> CS00<18> ECLK_H<18> ++ ECLK_H<19> ECLK_B<18> ECLK_B<19> WL_O<303> WL_O<302> WL_O<301> WL_O<300> ++ WL_O<299> WL_O<298> WL_O<297> WL_O<296> WL_O<295> WL_O<294> WL_O<293> ++ WL_O<292> WL_O<291> WL_O<290> WL_O<289> WL_O<288> VDD VSS / ++ RM_IHPSG13_64x32_c2_2P_DEC04 +XSEL<17> ADDR_N_I<3> ADDR_N_I<2> ADDR_N_I<1> ADDR_N_I<0> CS00<17> ECLK_H<17> ++ ECLK_H<18> ECLK_B<17> ECLK_B<18> WL_O<287> WL_O<286> WL_O<285> WL_O<284> ++ WL_O<283> WL_O<282> WL_O<281> WL_O<280> WL_O<279> WL_O<278> WL_O<277> ++ WL_O<276> WL_O<275> WL_O<274> WL_O<273> WL_O<272> VDD VSS / ++ RM_IHPSG13_64x32_c2_2P_DEC04 +XSEL<16> ADDR_N_I<3> ADDR_N_I<2> ADDR_N_I<1> ADDR_N_I<0> CS00<16> ECLK_H<16> ++ ECLK_H<17> ECLK_B<16> ECLK_B<17> WL_O<271> WL_O<270> WL_O<269> WL_O<268> ++ WL_O<267> WL_O<266> WL_O<265> WL_O<264> WL_O<263> WL_O<262> WL_O<261> ++ WL_O<260> WL_O<259> WL_O<258> WL_O<257> WL_O<256> VDD VSS / ++ RM_IHPSG13_64x32_c2_2P_DEC04 +XSEL<15> ADDR_N_I<3> ADDR_N_I<2> ADDR_N_I<1> ADDR_N_I<0> CS00<15> ECLK_H<15> ++ ECLK_H<16> ECLK_B<15> ECLK_B<16> WL_O<255> WL_O<254> WL_O<253> WL_O<252> ++ WL_O<251> WL_O<250> WL_O<249> WL_O<248> WL_O<247> WL_O<246> WL_O<245> ++ WL_O<244> WL_O<243> WL_O<242> WL_O<241> WL_O<240> VDD VSS / ++ RM_IHPSG13_64x32_c2_2P_DEC04 +XSEL<14> ADDR_N_I<3> ADDR_N_I<2> ADDR_N_I<1> ADDR_N_I<0> CS00<14> ECLK_H<14> ++ ECLK_H<15> ECLK_B<14> ECLK_B<15> WL_O<239> WL_O<238> WL_O<237> WL_O<236> ++ WL_O<235> WL_O<234> WL_O<233> WL_O<232> WL_O<231> WL_O<230> WL_O<229> ++ WL_O<228> WL_O<227> WL_O<226> WL_O<225> WL_O<224> VDD VSS / ++ RM_IHPSG13_64x32_c2_2P_DEC04 +XSEL<13> ADDR_N_I<3> ADDR_N_I<2> ADDR_N_I<1> ADDR_N_I<0> CS00<13> ECLK_H<13> ++ ECLK_H<14> ECLK_B<13> ECLK_B<14> WL_O<223> WL_O<222> WL_O<221> WL_O<220> ++ WL_O<219> WL_O<218> WL_O<217> WL_O<216> WL_O<215> WL_O<214> WL_O<213> ++ WL_O<212> WL_O<211> WL_O<210> WL_O<209> WL_O<208> VDD VSS / ++ RM_IHPSG13_64x32_c2_2P_DEC04 +XSEL<12> ADDR_N_I<3> ADDR_N_I<2> ADDR_N_I<1> ADDR_N_I<0> CS00<12> ECLK_H<12> ++ ECLK_H<13> ECLK_B<12> ECLK_B<13> WL_O<207> WL_O<206> WL_O<205> WL_O<204> ++ WL_O<203> WL_O<202> WL_O<201> WL_O<200> WL_O<199> WL_O<198> WL_O<197> ++ WL_O<196> WL_O<195> WL_O<194> WL_O<193> WL_O<192> VDD VSS / ++ RM_IHPSG13_64x32_c2_2P_DEC04 +XSEL<11> ADDR_N_I<3> ADDR_N_I<2> ADDR_N_I<1> ADDR_N_I<0> CS00<11> ECLK_H<11> ++ ECLK_H<12> ECLK_B<11> ECLK_B<12> WL_O<191> WL_O<190> WL_O<189> WL_O<188> ++ WL_O<187> WL_O<186> WL_O<185> WL_O<184> WL_O<183> WL_O<182> WL_O<181> ++ WL_O<180> WL_O<179> WL_O<178> WL_O<177> WL_O<176> VDD VSS / ++ RM_IHPSG13_64x32_c2_2P_DEC04 +XSEL<10> ADDR_N_I<3> ADDR_N_I<2> ADDR_N_I<1> ADDR_N_I<0> CS00<10> ECLK_H<10> ++ ECLK_H<11> ECLK_B<10> ECLK_B<11> WL_O<175> WL_O<174> WL_O<173> WL_O<172> ++ WL_O<171> WL_O<170> WL_O<169> WL_O<168> WL_O<167> WL_O<166> WL_O<165> ++ WL_O<164> WL_O<163> WL_O<162> WL_O<161> WL_O<160> VDD VSS / ++ RM_IHPSG13_64x32_c2_2P_DEC04 +XSEL<9> ADDR_N_I<3> ADDR_N_I<2> ADDR_N_I<1> ADDR_N_I<0> CS00<9> ECLK_H<9> ++ ECLK_H<10> ECLK_B<9> ECLK_B<10> WL_O<159> WL_O<158> WL_O<157> WL_O<156> ++ WL_O<155> WL_O<154> WL_O<153> WL_O<152> WL_O<151> WL_O<150> WL_O<149> ++ WL_O<148> WL_O<147> WL_O<146> WL_O<145> WL_O<144> VDD VSS / ++ RM_IHPSG13_64x32_c2_2P_DEC04 +XSEL<8> ADDR_N_I<3> ADDR_N_I<2> ADDR_N_I<1> ADDR_N_I<0> CS00<8> ECLK_H<8> ++ ECLK_H<9> ECLK_B<8> ECLK_B<9> WL_O<143> WL_O<142> WL_O<141> WL_O<140> ++ WL_O<139> WL_O<138> WL_O<137> WL_O<136> WL_O<135> WL_O<134> WL_O<133> ++ WL_O<132> WL_O<131> WL_O<130> WL_O<129> WL_O<128> VDD VSS / ++ RM_IHPSG13_64x32_c2_2P_DEC04 +XSEL<7> ADDR_N_I<3> ADDR_N_I<2> ADDR_N_I<1> ADDR_N_I<0> CS00<7> ECLK_H<7> ++ ECLK_H<8> ECLK_B<7> ECLK_B<8> WL_O<127> WL_O<126> WL_O<125> WL_O<124> ++ WL_O<123> WL_O<122> WL_O<121> WL_O<120> WL_O<119> WL_O<118> WL_O<117> ++ WL_O<116> WL_O<115> WL_O<114> WL_O<113> WL_O<112> VDD VSS / ++ RM_IHPSG13_64x32_c2_2P_DEC04 +XSEL<6> ADDR_N_I<3> ADDR_N_I<2> ADDR_N_I<1> ADDR_N_I<0> CS00<6> ECLK_H<6> ++ ECLK_H<7> ECLK_B<6> ECLK_B<7> WL_O<111> WL_O<110> WL_O<109> WL_O<108> ++ WL_O<107> WL_O<106> WL_O<105> WL_O<104> WL_O<103> WL_O<102> WL_O<101> ++ WL_O<100> WL_O<99> WL_O<98> WL_O<97> WL_O<96> VDD VSS / ++ RM_IHPSG13_64x32_c2_2P_DEC04 +XSEL<5> ADDR_N_I<3> ADDR_N_I<2> ADDR_N_I<1> ADDR_N_I<0> CS00<5> ECLK_H<5> ++ ECLK_H<6> ECLK_B<5> ECLK_B<6> WL_O<95> WL_O<94> WL_O<93> WL_O<92> WL_O<91> ++ WL_O<90> WL_O<89> WL_O<88> WL_O<87> WL_O<86> WL_O<85> WL_O<84> WL_O<83> ++ WL_O<82> WL_O<81> WL_O<80> VDD VSS / RM_IHPSG13_64x32_c2_2P_DEC04 +XSEL<4> ADDR_N_I<3> ADDR_N_I<2> ADDR_N_I<1> ADDR_N_I<0> CS00<4> ECLK_H<4> ++ ECLK_H<5> ECLK_B<4> ECLK_B<5> WL_O<79> WL_O<78> WL_O<77> WL_O<76> WL_O<75> ++ WL_O<74> WL_O<73> WL_O<72> WL_O<71> WL_O<70> WL_O<69> WL_O<68> WL_O<67> ++ WL_O<66> WL_O<65> WL_O<64> VDD VSS / RM_IHPSG13_64x32_c2_2P_DEC04 +XSEL<3> ADDR_N_I<3> ADDR_N_I<2> ADDR_N_I<1> ADDR_N_I<0> CS00<3> ECLK_H<3> ++ ECLK_H<4> ECLK_B<3> ECLK_B<4> WL_O<63> WL_O<62> WL_O<61> WL_O<60> WL_O<59> ++ WL_O<58> WL_O<57> WL_O<56> WL_O<55> WL_O<54> WL_O<53> WL_O<52> WL_O<51> ++ WL_O<50> WL_O<49> WL_O<48> VDD VSS / RM_IHPSG13_64x32_c2_2P_DEC04 +XSEL<2> ADDR_N_I<3> ADDR_N_I<2> ADDR_N_I<1> ADDR_N_I<0> CS00<2> ECLK_H<2> ++ ECLK_H<3> ECLK_B<2> ECLK_B<3> WL_O<47> WL_O<46> WL_O<45> WL_O<44> WL_O<43> ++ WL_O<42> WL_O<41> WL_O<40> WL_O<39> WL_O<38> WL_O<37> WL_O<36> WL_O<35> ++ WL_O<34> WL_O<33> WL_O<32> VDD VSS / RM_IHPSG13_64x32_c2_2P_DEC04 +XSEL<1> ADDR_N_I<3> ADDR_N_I<2> ADDR_N_I<1> ADDR_N_I<0> CS00<1> ECLK_H<1> ++ ECLK_H<2> ECLK_B<1> ECLK_B<2> WL_O<31> WL_O<30> WL_O<29> WL_O<28> WL_O<27> ++ WL_O<26> WL_O<25> WL_O<24> WL_O<23> WL_O<22> WL_O<21> WL_O<20> WL_O<19> ++ WL_O<18> WL_O<17> WL_O<16> VDD VSS / RM_IHPSG13_64x32_c2_2P_DEC04 +XSEL<0> ADDR_N_I<3> ADDR_N_I<2> ADDR_N_I<1> ADDR_N_I<0> CS00<0> ECLK_I ++ ECLK_H<1> ECLK_B<0> ECLK_B<1> WL_O<15> WL_O<14> WL_O<13> WL_O<12> WL_O<11> ++ WL_O<10> WL_O<9> WL_O<8> WL_O<7> WL_O<6> WL_O<5> WL_O<4> WL_O<3> WL_O<2> ++ WL_O<1> WL_O<0> VDD VSS / RM_IHPSG13_64x32_c2_2P_DEC04 +XDEC10<9> ADDR_N_I<7> ADDR_N_I<6> CS04<1> CS02<6> VDD VSS / ++ RM_IHPSG13_64x32_c2_2P_DEC02 +XDEC10<8> ADDR_N_I<7> ADDR_N_I<6> CS04<0> CS02<2> VDD VSS / ++ RM_IHPSG13_64x32_c2_2P_DEC02 +XDEC10<7> ADDR_N_I<5> ADDR_N_I<4> CS02<7> CS00<30> VDD VSS / ++ RM_IHPSG13_64x32_c2_2P_DEC02 +XDEC10<6> ADDR_N_I<5> ADDR_N_I<4> CS02<6> CS00<26> VDD VSS / ++ RM_IHPSG13_64x32_c2_2P_DEC02 +XDEC10<5> ADDR_N_I<5> ADDR_N_I<4> CS02<5> CS00<22> VDD VSS / ++ RM_IHPSG13_64x32_c2_2P_DEC02 +XDEC10<4> ADDR_N_I<5> ADDR_N_I<4> CS02<4> CS00<18> VDD VSS / ++ RM_IHPSG13_64x32_c2_2P_DEC02 +XDEC10<3> ADDR_N_I<5> ADDR_N_I<4> CS02<3> CS00<14> VDD VSS / ++ RM_IHPSG13_64x32_c2_2P_DEC02 +XDEC10<2> ADDR_N_I<5> ADDR_N_I<4> CS02<2> CS00<10> VDD VSS / ++ RM_IHPSG13_64x32_c2_2P_DEC02 +XDEC10<1> ADDR_N_I<5> ADDR_N_I<4> CS02<1> CS00<6> VDD VSS / ++ RM_IHPSG13_64x32_c2_2P_DEC02 +XDEC10<0> ADDR_N_I<5> ADDR_N_I<4> CS02<0> CS00<2> VDD VSS / ++ RM_IHPSG13_64x32_c2_2P_DEC02 +XDEC01<10> ADDR_N_I<9> ADDR_N_I<8> CS_I CS04<1> VDD VSS / ++ RM_IHPSG13_64x32_c2_2P_DEC01 +XDEC01<9> ADDR_N_I<7> ADDR_N_I<6> CS04<1> CS02<5> VDD VSS / ++ RM_IHPSG13_64x32_c2_2P_DEC01 +XDEC01<8> ADDR_N_I<7> ADDR_N_I<6> CS04<0> CS02<1> VDD VSS / ++ RM_IHPSG13_64x32_c2_2P_DEC01 +XDEC01<7> ADDR_N_I<5> ADDR_N_I<4> CS02<7> CS00<29> VDD VSS / ++ RM_IHPSG13_64x32_c2_2P_DEC01 +XDEC01<6> ADDR_N_I<5> ADDR_N_I<4> CS02<6> CS00<25> VDD VSS / ++ RM_IHPSG13_64x32_c2_2P_DEC01 +XDEC01<5> ADDR_N_I<5> ADDR_N_I<4> CS02<5> CS00<21> VDD VSS / ++ RM_IHPSG13_64x32_c2_2P_DEC01 +XDEC01<4> ADDR_N_I<5> ADDR_N_I<4> CS02<4> CS00<17> VDD VSS / ++ RM_IHPSG13_64x32_c2_2P_DEC01 +XDEC01<3> ADDR_N_I<5> ADDR_N_I<4> CS02<3> CS00<13> VDD VSS / ++ RM_IHPSG13_64x32_c2_2P_DEC01 +XDEC01<2> ADDR_N_I<5> ADDR_N_I<4> CS02<2> CS00<9> VDD VSS / ++ RM_IHPSG13_64x32_c2_2P_DEC01 +XDEC01<1> ADDR_N_I<5> ADDR_N_I<4> CS02<1> CS00<5> VDD VSS / ++ RM_IHPSG13_64x32_c2_2P_DEC01 +XDEC01<0> ADDR_N_I<5> ADDR_N_I<4> CS02<0> CS00<1> VDD VSS / ++ RM_IHPSG13_64x32_c2_2P_DEC01 +XL2<258> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<257> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<256> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<255> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<254> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<253> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<252> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<251> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<250> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<249> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<248> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<247> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<246> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<245> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<244> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<243> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<242> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<241> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<240> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<239> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<238> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<237> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<236> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<235> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<234> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<233> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<232> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<231> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<230> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<229> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<228> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<227> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<226> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<225> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<224> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<223> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<222> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<221> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<220> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<219> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<218> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<217> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<216> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<215> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<214> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<213> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<212> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<211> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<210> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<209> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<208> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<207> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<206> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<205> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<204> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<203> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<202> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<201> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<200> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<199> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<198> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<197> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<196> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<195> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<194> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<193> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<192> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<191> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<190> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<189> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<188> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<187> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<186> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<185> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<184> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<183> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<182> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<181> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<180> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<179> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<178> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<177> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<176> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<175> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<174> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<173> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<172> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<171> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<170> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<169> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<168> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<167> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<166> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<165> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<164> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<163> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<162> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<161> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<160> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<159> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<158> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<157> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<156> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<155> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<154> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<153> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<152> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<151> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<150> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<149> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<148> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<147> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<146> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<145> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<144> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<143> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<142> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<141> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<140> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<139> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<138> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<137> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<136> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<135> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<134> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<133> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<132> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<131> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<130> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<129> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<128> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<127> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<126> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<125> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<124> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<123> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<122> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<121> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<120> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<119> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<118> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<117> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<116> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<115> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<114> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<113> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<112> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<111> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<110> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<109> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<108> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<107> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<106> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<105> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<104> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<103> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<102> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<101> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<100> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<99> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<98> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<97> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<96> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<95> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<94> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<93> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<92> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<91> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<90> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<89> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<88> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<87> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<86> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<85> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<84> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<83> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<82> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<81> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<80> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<79> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<78> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<77> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<76> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<75> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<74> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<73> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<72> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<71> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<70> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<69> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<68> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<67> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<66> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<65> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<64> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<63> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<62> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<61> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<60> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<59> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<58> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<57> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<56> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<55> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<54> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<53> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<52> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<51> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<50> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<49> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<48> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<47> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<46> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<45> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<44> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<43> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<42> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<41> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<40> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<39> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<38> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<37> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<36> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<35> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<34> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<33> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<32> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<31> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<30> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<29> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<28> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<27> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<26> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<25> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<24> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<23> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<22> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<21> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<20> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<19> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<18> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<17> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<16> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<15> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<14> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<13> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<12> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<11> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<10> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<9> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<8> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<7> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<6> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<5> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<4> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<3> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<2> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<1> VDD VSS / RSC_IHPSG13_FILLCAP8 +XDEC00<10> ADDR_N_I<9> ADDR_N_I<8> CS_I CS04<0> VDD VSS / ++ RM_IHPSG13_64x32_c2_2P_DEC00 +XDEC00<9> ADDR_N_I<7> ADDR_N_I<6> CS04<1> CS02<4> VDD VSS / ++ RM_IHPSG13_64x32_c2_2P_DEC00 +XDEC00<8> ADDR_N_I<7> ADDR_N_I<6> CS04<0> CS02<0> VDD VSS / ++ RM_IHPSG13_64x32_c2_2P_DEC00 +XDEC00<7> ADDR_N_I<5> ADDR_N_I<4> CS02<7> CS00<28> VDD VSS / ++ RM_IHPSG13_64x32_c2_2P_DEC00 +XDEC00<6> ADDR_N_I<5> ADDR_N_I<4> CS02<6> CS00<24> VDD VSS / ++ RM_IHPSG13_64x32_c2_2P_DEC00 +XDEC00<5> ADDR_N_I<5> ADDR_N_I<4> CS02<5> CS00<20> VDD VSS / ++ RM_IHPSG13_64x32_c2_2P_DEC00 +XDEC00<4> ADDR_N_I<5> ADDR_N_I<4> CS02<4> CS00<16> VDD VSS / ++ RM_IHPSG13_64x32_c2_2P_DEC00 +XDEC00<3> ADDR_N_I<5> ADDR_N_I<4> CS02<3> CS00<12> VDD VSS / ++ RM_IHPSG13_64x32_c2_2P_DEC00 +XDEC00<2> ADDR_N_I<5> ADDR_N_I<4> CS02<2> CS00<8> VDD VSS / ++ RM_IHPSG13_64x32_c2_2P_DEC00 +XDEC00<1> ADDR_N_I<5> ADDR_N_I<4> CS02<1> CS00<4> VDD VSS / ++ RM_IHPSG13_64x32_c2_2P_DEC00 +XDEC00<0> ADDR_N_I<5> ADDR_N_I<4> CS02<0> CS00<0> VDD VSS / ++ RM_IHPSG13_64x32_c2_2P_DEC00 +XDEC11<9> ADDR_N_I<7> ADDR_N_I<6> CS04<1> CS02<7> VDD VSS / ++ RM_IHPSG13_64x32_c2_2P_DEC03 +XDEC11<8> ADDR_N_I<7> ADDR_N_I<6> CS04<0> CS02<3> VDD VSS / ++ RM_IHPSG13_64x32_c2_2P_DEC03 +XDEC11<7> ADDR_N_I<5> ADDR_N_I<4> CS02<7> CS00<31> VDD VSS / ++ RM_IHPSG13_64x32_c2_2P_DEC03 +XDEC11<6> ADDR_N_I<5> ADDR_N_I<4> CS02<6> CS00<27> VDD VSS / ++ RM_IHPSG13_64x32_c2_2P_DEC03 +XDEC11<5> ADDR_N_I<5> ADDR_N_I<4> CS02<5> CS00<23> VDD VSS / ++ RM_IHPSG13_64x32_c2_2P_DEC03 +XDEC11<4> ADDR_N_I<5> ADDR_N_I<4> CS02<4> CS00<19> VDD VSS / ++ RM_IHPSG13_64x32_c2_2P_DEC03 +XDEC11<3> ADDR_N_I<5> ADDR_N_I<4> CS02<3> CS00<15> VDD VSS / ++ RM_IHPSG13_64x32_c2_2P_DEC03 +XDEC11<2> ADDR_N_I<5> ADDR_N_I<4> CS02<2> CS00<11> VDD VSS / ++ RM_IHPSG13_64x32_c2_2P_DEC03 +XDEC11<1> ADDR_N_I<5> ADDR_N_I<4> CS02<1> CS00<7> VDD VSS / ++ RM_IHPSG13_64x32_c2_2P_DEC03 +XDEC11<0> ADDR_N_I<5> ADDR_N_I<4> CS02<0> CS00<3> VDD VSS / ++ RM_IHPSG13_64x32_c2_2P_DEC03 +XI0 ADDR_N_I<9> VDD VSS / RSC_IHPSG13_TIEL +.ENDS +.SUBCKT RM_IHPSG13_64x32_c2_2P_ROWREG9 ACLK_N_I ADDR_I<8> ADDR_I<7> ADDR_I<6> ADDR_I<5> ++ ADDR_I<4> ADDR_I<3> ADDR_I<2> ADDR_I<1> ADDR_I<0> ADDR_N_O<8> ADDR_N_O<7> ++ ADDR_N_O<6> ADDR_N_O<5> ADDR_N_O<4> ADDR_N_O<3> ADDR_N_O<2> ADDR_N_O<1> ++ ADDR_N_O<0> BIST_ADDR_I<8> BIST_ADDR_I<7> BIST_ADDR_I<6> BIST_ADDR_I<5> ++ BIST_ADDR_I<4> BIST_ADDR_I<3> BIST_ADDR_I<2> BIST_ADDR_I<1> BIST_ADDR_I<0> ++ BIST_EN_I VDD VSS +XDFF<8> BIST_EN_I BIST_ADDR_I<8> ACLK_N_I ADDR_I<8> q_int<8> net04<0> VDD ++ VSS / RSC_IHPSG13_DFNQMX2IX1 +XDFF<7> BIST_EN_I BIST_ADDR_I<7> ACLK_N_I ADDR_I<7> q_int<7> net04<1> VDD ++ VSS / RSC_IHPSG13_DFNQMX2IX1 +XDFF<6> BIST_EN_I BIST_ADDR_I<6> ACLK_N_I ADDR_I<6> q_int<6> net04<2> VDD ++ VSS / RSC_IHPSG13_DFNQMX2IX1 +XDFF<5> BIST_EN_I BIST_ADDR_I<5> ACLK_N_I ADDR_I<5> q_int<5> net04<3> VDD ++ VSS / RSC_IHPSG13_DFNQMX2IX1 +XDFF<4> BIST_EN_I BIST_ADDR_I<4> ACLK_N_I ADDR_I<4> q_int<4> net04<4> VDD ++ VSS / RSC_IHPSG13_DFNQMX2IX1 +XDFF<3> BIST_EN_I BIST_ADDR_I<3> ACLK_N_I ADDR_I<3> q_int<3> net04<5> VDD ++ VSS / RSC_IHPSG13_DFNQMX2IX1 +XDFF<2> BIST_EN_I BIST_ADDR_I<2> ACLK_N_I ADDR_I<2> q_int<2> net04<6> VDD ++ VSS / RSC_IHPSG13_DFNQMX2IX1 +XDFF<1> BIST_EN_I BIST_ADDR_I<1> ACLK_N_I ADDR_I<1> q_int<1> net04<7> VDD ++ VSS / RSC_IHPSG13_DFNQMX2IX1 +XDFF<0> BIST_EN_I BIST_ADDR_I<0> ACLK_N_I ADDR_I<0> q_int<0> net04<8> VDD ++ VSS / RSC_IHPSG13_DFNQMX2IX1 +XDRV<8> qn_int<8> ADDR_N_O<8> VDD VSS / RSC_IHPSG13_CINVX8 +XDRV<7> qn_int<7> ADDR_N_O<7> VDD VSS / RSC_IHPSG13_CINVX8 +XDRV<6> qn_int<6> ADDR_N_O<6> VDD VSS / RSC_IHPSG13_CINVX8 +XDRV<5> qn_int<5> ADDR_N_O<5> VDD VSS / RSC_IHPSG13_CINVX8 +XDRV<4> qn_int<4> ADDR_N_O<4> VDD VSS / RSC_IHPSG13_CINVX8 +XDRV<3> qn_int<3> ADDR_N_O<3> VDD VSS / RSC_IHPSG13_CINVX8 +XDRV<2> qn_int<2> ADDR_N_O<2> VDD VSS / RSC_IHPSG13_CINVX8 +XDRV<1> qn_int<1> ADDR_N_O<1> VDD VSS / RSC_IHPSG13_CINVX8 +XDRV<0> qn_int<0> ADDR_N_O<0> VDD VSS / RSC_IHPSG13_CINVX8 +XINV<8> q_int<8> qn_int<8> VDD VSS / RSC_IHPSG13_CINVX2 +XINV<7> q_int<7> qn_int<7> VDD VSS / RSC_IHPSG13_CINVX2 +XINV<6> q_int<6> qn_int<6> VDD VSS / RSC_IHPSG13_CINVX2 +XINV<5> q_int<5> qn_int<5> VDD VSS / RSC_IHPSG13_CINVX2 +XINV<4> q_int<4> qn_int<4> VDD VSS / RSC_IHPSG13_CINVX2 +XINV<3> q_int<3> qn_int<3> VDD VSS / RSC_IHPSG13_CINVX2 +XINV<2> q_int<2> qn_int<2> VDD VSS / RSC_IHPSG13_CINVX2 +XINV<1> q_int<1> qn_int<1> VDD VSS / RSC_IHPSG13_CINVX2 +XINV<0> q_int<0> qn_int<0> VDD VSS / RSC_IHPSG13_CINVX2 +.ENDS + +.SUBCKT RM_IHPSG13_64x32_c2_2P_DLY_MUX A SEL Z VDD VSS +XI11 net4 Z VDD VSS / RSC_IHPSG13_CINVX2 +XI8 A D<3> SEL net4 VDD VSS / RSC_IHPSG13_MX2IX1 +XI20<3> D<2> D<3> VDD VSS / RSC_IHPSG13_CDLYX1 +XI20<2> D<1> D<2> VDD VSS / RSC_IHPSG13_CDLYX1 +XI20<1> A D<1> VDD VSS / RSC_IHPSG13_CDLYX1 +.ENDS +.SUBCKT RM_IHPSG13_64x32_c2_2P_CTRL ACLK_N BIST_CK_I BIST_CS_I BIST_EN BIST_RE_I ++ BIST_WE_I B_TIEL_O CK_I CS_I DCLK ECLK PULSE_H PULSE_L PULSE_O RCLK RE_I ++ ROW_CS WCLK WE_I VDD VSS +XI17 ck_regs we col_we VDD VSS / RSC_IHPSG13_DFNQX2 +XI16 ck_regs re col_re VDD VSS / RSC_IHPSG13_DFNQX2 +XI18 ck_regs cs net7 VDD VSS / RSC_IHPSG13_DFNQX2 +XI71 ACLK_N net012 PULSE_O VDD VSS / RSC_IHPSG13_DFNQX2 +XI77 col_we net017 net016 VDD VSS / RSC_IHPSG13_CNAND2X2 +XI76 col_re net017 net018 VDD VSS / RSC_IHPSG13_CNAND2X2 +XI15 ck_dly WEorREandCS aclk VDD VSS / RSC_IHPSG13_CGATEPX4 +XI14 ck WEandCS DCLK VDD VSS / RSC_IHPSG13_CGATEPX4 +XI60 net7 ROW_CS VDD VSS / RSC_IHPSG13_CBUFX8 +XI73 PULSE_O net012 VDD VSS / RSC_IHPSG13_CINVX2 +XI8 net017 net8 VDD VSS / RSC_IHPSG13_CINVX2 +XCAPS4<7> VDD VSS / RSC_IHPSG13_FILLCAP4 +XCAPS4<6> VDD VSS / RSC_IHPSG13_FILLCAP4 +XCAPS4<5> VDD VSS / RSC_IHPSG13_FILLCAP4 +XCAPS4<4> VDD VSS / RSC_IHPSG13_FILLCAP4 +XCAPS4<3> VDD VSS / RSC_IHPSG13_FILLCAP4 +XCAPS4<2> VDD VSS / RSC_IHPSG13_FILLCAP4 +XCAPS4<1> VDD VSS / RSC_IHPSG13_FILLCAP4 +XBM_TIEL B_TIEL_O VDD VSS / RSC_IHPSG13_TIEL +XI64 ck ck_dly VDD VSS / RSC_IHPSG13_CDLYX2 +XI86 CS_I BIST_CS_I BIST_EN cs VDD VSS / RSC_IHPSG13_MX2X2 +XI87 CK_I BIST_CK_I BIST_EN ck VDD VSS / RSC_IHPSG13_MX2X2 +XI85 WE_I BIST_WE_I BIST_EN we VDD VSS / RSC_IHPSG13_MX2X2 +XI84 RE_I BIST_RE_I BIST_EN re VDD VSS / RSC_IHPSG13_MX2X2 +XI48 ck_dly ck_regs VDD VSS / RSC_IHPSG13_CINVX4 +XI81 net016 WCLK VDD VSS / RSC_IHPSG13_CINVX4 +XI80 net018 RCLK VDD VSS / RSC_IHPSG13_CINVX4 +XI78 net8 net020 VDD VSS / RSC_IHPSG13_CINVX4 +XCAPS8<7> VDD VSS / RSC_IHPSG13_FILLCAP8 +XCAPS8<6> VDD VSS / RSC_IHPSG13_FILLCAP8 +XCAPS8<5> VDD VSS / RSC_IHPSG13_FILLCAP8 +XCAPS8<4> VDD VSS / RSC_IHPSG13_FILLCAP8 +XCAPS8<3> VDD VSS / RSC_IHPSG13_FILLCAP8 +XCAPS8<2> VDD VSS / RSC_IHPSG13_FILLCAP8 +XCAPS8<1> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI6 PULSE_L PULSE_H net017 VDD VSS / RSC_IHPSG13_XOR2X2 +XI22 we cs WEandCS VDD VSS / RSC_IHPSG13_AND2X2 +XI79 net020 ECLK VDD VSS / RSC_IHPSG13_CINVX8 +XI63 aclk ACLK_N VDD VSS / RSC_IHPSG13_CINVX8 +XI21 re we cs WEorREandCS VDD VSS / RSC_IHPSG13_OA12X1 +.ENDS +.SUBCKT RM_IHPSG13_64x32_c2_2P_COLDEC5 ACLK_N ADDR<4> ADDR<3> ADDR<2> ADDR<1> ADDR<0> ++ ADDR_COL<1> ADDR_COL<0> ADDR_DEC<7> ADDR_DEC<6> ADDR_DEC<5> ADDR_DEC<4> ++ ADDR_DEC<3> ADDR_DEC<2> ADDR_DEC<1> ADDR_DEC<0> BIST_ADDR<4> BIST_ADDR<3> ++ BIST_ADDR<2> BIST_ADDR<1> BIST_ADDR<0> BIST_EN_I VDD VSS +XI17<4> VDD VSS / RSC_IHPSG13_FILLCAP4 +XI17<3> VDD VSS / RSC_IHPSG13_FILLCAP4 +XI17<2> VDD VSS / RSC_IHPSG13_FILLCAP4 +XI17<1> VDD VSS / RSC_IHPSG13_FILLCAP4 +XI1<7> PADR<0> PADR<1> PADR<2> addr_n<7> VDD VSS / RSC_IHPSG13_NAND3X2 +XI1<6> NADR<0> PADR<1> PADR<2> addr_n<6> VDD VSS / RSC_IHPSG13_NAND3X2 +XI1<5> PADR<0> NADR<1> PADR<2> addr_n<5> VDD VSS / RSC_IHPSG13_NAND3X2 +XI1<4> NADR<0> NADR<1> PADR<2> addr_n<4> VDD VSS / RSC_IHPSG13_NAND3X2 +XI1<3> PADR<0> PADR<1> NADR<2> addr_n<3> VDD VSS / RSC_IHPSG13_NAND3X2 +XI1<2> NADR<0> PADR<1> NADR<2> addr_n<2> VDD VSS / RSC_IHPSG13_NAND3X2 +XI1<1> PADR<0> NADR<1> NADR<2> addr_n<1> VDD VSS / RSC_IHPSG13_NAND3X2 +XI1<0> NADR<0> NADR<1> NADR<2> addr_n<0> VDD VSS / RSC_IHPSG13_NAND3X2 +XDFF<4> BIST_EN_I BIST_ADDR<4> ACLK_N ADDR<4> addr_int<1> net13<0> VDD ++ VSS / RSC_IHPSG13_DFNQMX2IX1 +XDFF<3> BIST_EN_I BIST_ADDR<3> ACLK_N ADDR<3> addr_int<0> net13<1> VDD ++ VSS / RSC_IHPSG13_DFNQMX2IX1 +XDFF<2> BIST_EN_I BIST_ADDR<2> ACLK_N ADDR<2> padr_int<2> net13<2> VDD ++ VSS / RSC_IHPSG13_DFNQMX2IX1 +XDFF<1> BIST_EN_I BIST_ADDR<1> ACLK_N ADDR<1> padr_int<1> net13<3> VDD ++ VSS / RSC_IHPSG13_DFNQMX2IX1 +XDFF<0> BIST_EN_I BIST_ADDR<0> ACLK_N ADDR<0> padr_int<0> net13<4> VDD ++ VSS / RSC_IHPSG13_DFNQMX2IX1 +XI3<2> padr_int<2> NADR<2> VDD VSS / RSC_IHPSG13_INVX2 +XI3<1> padr_int<1> NADR<1> VDD VSS / RSC_IHPSG13_INVX2 +XI3<0> padr_int<0> NADR<0> VDD VSS / RSC_IHPSG13_INVX2 +XI2<7> addr_n<7> ADDR_DEC<7> VDD VSS / RSC_IHPSG13_INVX2 +XI2<6> addr_n<6> ADDR_DEC<6> VDD VSS / RSC_IHPSG13_INVX2 +XI2<5> addr_n<5> ADDR_DEC<5> VDD VSS / RSC_IHPSG13_INVX2 +XI2<4> addr_n<4> ADDR_DEC<4> VDD VSS / RSC_IHPSG13_INVX2 +XI2<3> addr_n<3> ADDR_DEC<3> VDD VSS / RSC_IHPSG13_INVX2 +XI2<2> addr_n<2> ADDR_DEC<2> VDD VSS / RSC_IHPSG13_INVX2 +XI2<1> addr_n<1> ADDR_DEC<1> VDD VSS / RSC_IHPSG13_INVX2 +XI2<0> addr_n<0> ADDR_DEC<0> VDD VSS / RSC_IHPSG13_INVX2 +XI15<2> NADR<2> PADR<2> VDD VSS / RSC_IHPSG13_INVX2 +XI15<1> NADR<1> PADR<1> VDD VSS / RSC_IHPSG13_INVX2 +XI15<0> NADR<0> PADR<0> VDD VSS / RSC_IHPSG13_INVX2 +XI13<1> addr_int<1> ADDR_COL<1> VDD VSS / RSC_IHPSG13_CBUFX2 +XI13<0> addr_int<0> ADDR_COL<0> VDD VSS / RSC_IHPSG13_CBUFX2 +XI14<5> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI14<4> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI14<3> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI14<2> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI14<1> VDD VSS / RSC_IHPSG13_FILLCAP8 +.ENDS +.SUBCKT RM_IHPSG13_64x32_c2_2P_BLDRV A_BLC<3> A_BLC<2> A_BLC<1> A_BLC<0> A_BLC_SEL ++ A_BLT<3> A_BLT<2> A_BLT<1> A_BLT<0> A_BLT_SEL A_PRE_N A_SEL_P<3> A_SEL_P<2> ++ A_SEL_P<1> A_SEL_P<0> A_WR_ONE A_WR_ZERO B_BLC<3> B_BLC<2> B_BLC<1> B_BLC<0> ++ B_BLC_SEL B_BLT<3> B_BLT<2> B_BLT<1> B_BLT<0> B_BLT_SEL B_PRE_N B_SEL_P<3> ++ B_SEL_P<2> B_SEL_P<1> B_SEL_P<0> B_WR_ONE B_WR_ZERO VDD VSS +MA_CWN<3> A_BLC<3> A_BLC_NMOS_DRIVE<3> VSS VSS sg13_lv_nmos m=1 ++ w=4.82u l=130.00n ng=2 nrd=0 nrs=0 +MA_CWN<2> A_BLC<2> A_BLC_NMOS_DRIVE<2> VSS VSS sg13_lv_nmos m=1 ++ w=4.82u l=130.00n ng=2 nrd=0 nrs=0 +MA_CWN<1> A_BLC<1> A_BLC_NMOS_DRIVE<1> VSS VSS sg13_lv_nmos m=1 ++ w=4.82u l=130.00n ng=2 nrd=0 nrs=0 +MA_CWN<0> A_BLC<0> A_BLC_NMOS_DRIVE<0> VSS VSS sg13_lv_nmos m=1 ++ w=4.82u l=130.00n ng=2 nrd=0 nrs=0 +MA_TWN<3> A_BLT<3> A_BLT_NMOS_DRIVE<3> VSS VSS sg13_lv_nmos m=1 ++ w=4.82u l=130.00n ng=2 nrd=0 nrs=0 +MA_TWN<2> A_BLT<2> A_BLT_NMOS_DRIVE<2> VSS VSS sg13_lv_nmos m=1 ++ w=4.82u l=130.00n ng=2 nrd=0 nrs=0 +MA_TWN<1> A_BLT<1> A_BLT_NMOS_DRIVE<1> VSS VSS sg13_lv_nmos m=1 ++ w=4.82u l=130.00n ng=2 nrd=0 nrs=0 +MA_TWN<0> A_BLT<0> A_BLT_NMOS_DRIVE<0> VSS VSS sg13_lv_nmos m=1 ++ w=4.82u l=130.00n ng=2 nrd=0 nrs=0 +MB_TWN<3> B_BLT<3> B_BLT_NMOS_DRIVE<3> VSS VSS sg13_lv_nmos m=1 ++ w=4.82u l=130.00n ng=2 nrd=0 nrs=0 +MB_TWN<2> B_BLT<2> B_BLT_NMOS_DRIVE<2> VSS VSS sg13_lv_nmos m=1 ++ w=4.82u l=130.00n ng=2 nrd=0 nrs=0 +MB_TWN<1> B_BLT<1> B_BLT_NMOS_DRIVE<1> VSS VSS sg13_lv_nmos m=1 ++ w=4.82u l=130.00n ng=2 nrd=0 nrs=0 +MB_TWN<0> B_BLT<0> B_BLT_NMOS_DRIVE<0> VSS VSS sg13_lv_nmos m=1 ++ w=4.82u l=130.00n ng=2 nrd=0 nrs=0 +MB_CWN<3> B_BLC<3> B_BLC_NMOS_DRIVE<3> VSS VSS sg13_lv_nmos m=1 ++ w=4.82u l=130.00n ng=2 nrd=0 nrs=0 +MB_CWN<2> B_BLC<2> B_BLC_NMOS_DRIVE<2> VSS VSS sg13_lv_nmos m=1 ++ w=4.82u l=130.00n ng=2 nrd=0 nrs=0 +MB_CWN<1> B_BLC<1> B_BLC_NMOS_DRIVE<1> VSS VSS sg13_lv_nmos m=1 ++ w=4.82u l=130.00n ng=2 nrd=0 nrs=0 +MB_CWN<0> B_BLC<0> B_BLC_NMOS_DRIVE<0> VSS VSS sg13_lv_nmos m=1 ++ w=4.82u l=130.00n ng=2 nrd=0 nrs=0 +MA_CPR<3> A_BLC<3> A_PRE_N VDD VDD sg13_lv_pmos m=1 w=3.000u l=130.00n ++ ng=2 nrd=0 nrs=0 +MA_CPR<2> A_BLC<2> A_PRE_N VDD VDD sg13_lv_pmos m=1 w=3.000u l=130.00n ++ ng=2 nrd=0 nrs=0 +MA_CPR<1> A_BLC<1> A_PRE_N VDD VDD sg13_lv_pmos m=1 w=3.000u l=130.00n ++ ng=2 nrd=0 nrs=0 +MA_CPR<0> A_BLC<0> A_PRE_N VDD VDD sg13_lv_pmos m=1 w=3.000u l=130.00n ++ ng=2 nrd=0 nrs=0 +MA_TWP<3> A_BLT<3> A_BLT_PMOS_DRIVE<3> VDD VDD sg13_lv_pmos m=1 w=1.5u ++ l=130.00n ng=1 nrd=0 nrs=0 +MA_TWP<2> A_BLT<2> A_BLT_PMOS_DRIVE<2> VDD VDD sg13_lv_pmos m=1 w=1.5u ++ l=130.00n ng=1 nrd=0 nrs=0 +MA_TWP<1> A_BLT<1> A_BLT_PMOS_DRIVE<1> VDD VDD sg13_lv_pmos m=1 w=1.5u ++ l=130.00n ng=1 nrd=0 nrs=0 +MA_TWP<0> A_BLT<0> A_BLT_PMOS_DRIVE<0> VDD VDD sg13_lv_pmos m=1 w=1.5u ++ l=130.00n ng=1 nrd=0 nrs=0 +MA_CWP<3> A_BLC<3> A_BLC_PMOS_DRIVE<3> VDD VDD sg13_lv_pmos m=1 w=1.5u ++ l=130.00n ng=1 nrd=0 nrs=0 +MA_CWP<2> A_BLC<2> A_BLC_PMOS_DRIVE<2> VDD VDD sg13_lv_pmos m=1 w=1.5u ++ l=130.00n ng=1 nrd=0 nrs=0 +MA_CWP<1> A_BLC<1> A_BLC_PMOS_DRIVE<1> VDD VDD sg13_lv_pmos m=1 w=1.5u ++ l=130.00n ng=1 nrd=0 nrs=0 +MA_CWP<0> A_BLC<0> A_BLC_PMOS_DRIVE<0> VDD VDD sg13_lv_pmos m=1 w=1.5u ++ l=130.00n ng=1 nrd=0 nrs=0 +MA_TPR<3> A_BLT<3> A_PRE_N VDD VDD sg13_lv_pmos m=1 w=3.000u l=130.00n ++ ng=2 nrd=0 nrs=0 +MA_TPR<2> A_BLT<2> A_PRE_N VDD VDD sg13_lv_pmos m=1 w=3.000u l=130.00n ++ ng=2 nrd=0 nrs=0 +MA_TPR<1> A_BLT<1> A_PRE_N VDD VDD sg13_lv_pmos m=1 w=3.000u l=130.00n ++ ng=2 nrd=0 nrs=0 +MA_TPR<0> A_BLT<0> A_PRE_N VDD VDD sg13_lv_pmos m=1 w=3.000u l=130.00n ++ ng=2 nrd=0 nrs=0 +MA_TSP<3> A_BLT_SEL A_SEL_N<3> A_BLT<3> VDD sg13_lv_pmos m=1 w=1.5u ++ l=130.00n ng=1 nrd=0 nrs=0 +MA_TSP<2> A_BLT_SEL A_SEL_N<2> A_BLT<2> VDD sg13_lv_pmos m=1 w=1.5u ++ l=130.00n ng=1 nrd=0 nrs=0 +MA_TSP<1> A_BLT_SEL A_SEL_N<1> A_BLT<1> VDD sg13_lv_pmos m=1 w=1.5u ++ l=130.00n ng=1 nrd=0 nrs=0 +MA_TSP<0> A_BLT_SEL A_SEL_N<0> A_BLT<0> VDD sg13_lv_pmos m=1 w=1.5u ++ l=130.00n ng=1 nrd=0 nrs=0 +MA_CSP<3> A_BLC_SEL A_SEL_N<3> A_BLC<3> VDD sg13_lv_pmos m=1 w=1.5u ++ l=130.00n ng=1 nrd=0 nrs=0 +MA_CSP<2> A_BLC_SEL A_SEL_N<2> A_BLC<2> VDD sg13_lv_pmos m=1 w=1.5u ++ l=130.00n ng=1 nrd=0 nrs=0 +MA_CSP<1> A_BLC_SEL A_SEL_N<1> A_BLC<1> VDD sg13_lv_pmos m=1 w=1.5u ++ l=130.00n ng=1 nrd=0 nrs=0 +MA_CSP<0> A_BLC_SEL A_SEL_N<0> A_BLC<0> VDD sg13_lv_pmos m=1 w=1.5u ++ l=130.00n ng=1 nrd=0 nrs=0 +MB_CWP<3> B_BLC<3> B_BLC_PMOS_DRIVE<3> VDD VDD sg13_lv_pmos m=1 w=1.5u ++ l=130.00n ng=1 nrd=0 nrs=0 +MB_CWP<2> B_BLC<2> B_BLC_PMOS_DRIVE<2> VDD VDD sg13_lv_pmos m=1 w=1.5u ++ l=130.00n ng=1 nrd=0 nrs=0 +MB_CWP<1> B_BLC<1> B_BLC_PMOS_DRIVE<1> VDD VDD sg13_lv_pmos m=1 w=1.5u ++ l=130.00n ng=1 nrd=0 nrs=0 +MB_CWP<0> B_BLC<0> B_BLC_PMOS_DRIVE<0> VDD VDD sg13_lv_pmos m=1 w=1.5u ++ l=130.00n ng=1 nrd=0 nrs=0 +MB_TWP<3> B_BLT<3> B_BLT_PMOS_DRIVE<3> VDD VDD sg13_lv_pmos m=1 w=1.5u ++ l=130.00n ng=1 nrd=0 nrs=0 +MB_TWP<2> B_BLT<2> B_BLT_PMOS_DRIVE<2> VDD VDD sg13_lv_pmos m=1 w=1.5u ++ l=130.00n ng=1 nrd=0 nrs=0 +MB_TWP<1> B_BLT<1> B_BLT_PMOS_DRIVE<1> VDD VDD sg13_lv_pmos m=1 w=1.5u ++ l=130.00n ng=1 nrd=0 nrs=0 +MB_TWP<0> B_BLT<0> B_BLT_PMOS_DRIVE<0> VDD VDD sg13_lv_pmos m=1 w=1.5u ++ l=130.00n ng=1 nrd=0 nrs=0 +MB_TSP<3> B_BLT_SEL B_SEL_N<3> B_BLT<3> VDD sg13_lv_pmos m=1 w=1.5u ++ l=130.00n ng=1 nrd=0 nrs=0 +MB_TSP<2> B_BLT_SEL B_SEL_N<2> B_BLT<2> VDD sg13_lv_pmos m=1 w=1.5u ++ l=130.00n ng=1 nrd=0 nrs=0 +MB_TSP<1> B_BLT_SEL B_SEL_N<1> B_BLT<1> VDD sg13_lv_pmos m=1 w=1.5u ++ l=130.00n ng=1 nrd=0 nrs=0 +MB_TSP<0> B_BLT_SEL B_SEL_N<0> B_BLT<0> VDD sg13_lv_pmos m=1 w=1.5u ++ l=130.00n ng=1 nrd=0 nrs=0 +MB_TPR<3> B_BLT<3> B_PRE_N VDD VDD sg13_lv_pmos m=1 w=3.000u l=130.00n ++ ng=2 nrd=0 nrs=0 +MB_TPR<2> B_BLT<2> B_PRE_N VDD VDD sg13_lv_pmos m=1 w=3.000u l=130.00n ++ ng=2 nrd=0 nrs=0 +MB_TPR<1> B_BLT<1> B_PRE_N VDD VDD sg13_lv_pmos m=1 w=3.000u l=130.00n ++ ng=2 nrd=0 nrs=0 +MB_TPR<0> B_BLT<0> B_PRE_N VDD VDD sg13_lv_pmos m=1 w=3.000u l=130.00n ++ ng=2 nrd=0 nrs=0 +MB_CSP<3> B_BLC_SEL B_SEL_N<3> B_BLC<3> VDD sg13_lv_pmos m=1 w=1.5u ++ l=130.00n ng=1 nrd=0 nrs=0 +MB_CSP<2> B_BLC_SEL B_SEL_N<2> B_BLC<2> VDD sg13_lv_pmos m=1 w=1.5u ++ l=130.00n ng=1 nrd=0 nrs=0 +MB_CSP<1> B_BLC_SEL B_SEL_N<1> B_BLC<1> VDD sg13_lv_pmos m=1 w=1.5u ++ l=130.00n ng=1 nrd=0 nrs=0 +MB_CSP<0> B_BLC_SEL B_SEL_N<0> B_BLC<0> VDD sg13_lv_pmos m=1 w=1.5u ++ l=130.00n ng=1 nrd=0 nrs=0 +MB_CPR<3> B_BLC<3> B_PRE_N VDD VDD sg13_lv_pmos m=1 w=3.000u l=130.00n ++ ng=2 nrd=0 nrs=0 +MB_CPR<2> B_BLC<2> B_PRE_N VDD VDD sg13_lv_pmos m=1 w=3.000u l=130.00n ++ ng=2 nrd=0 nrs=0 +MB_CPR<1> B_BLC<1> B_PRE_N VDD VDD sg13_lv_pmos m=1 w=3.000u l=130.00n ++ ng=2 nrd=0 nrs=0 +MB_CPR<0> B_BLC<0> B_PRE_N VDD VDD sg13_lv_pmos m=1 w=3.000u l=130.00n ++ ng=2 nrd=0 nrs=0 +XA_SEL<3> A_SEL_P<3> A_SEL_N<3> VDD VSS / RSC_IHPSG13_INVX2 +XA_SEL<2> A_SEL_P<2> A_SEL_N<2> VDD VSS / RSC_IHPSG13_INVX2 +XA_SEL<1> A_SEL_P<1> A_SEL_N<1> VDD VSS / RSC_IHPSG13_INVX2 +XA_SEL<0> A_SEL_P<0> A_SEL_N<0> VDD VSS / RSC_IHPSG13_INVX2 +XA_CINV<3> A_BLT_PMOS_DRIVE<3> A_BLC_NMOS_DRIVE<3> VDD VSS / ++ RSC_IHPSG13_INVX2 +XA_CINV<2> A_BLT_PMOS_DRIVE<2> A_BLC_NMOS_DRIVE<2> VDD VSS / ++ RSC_IHPSG13_INVX2 +XA_CINV<1> A_BLT_PMOS_DRIVE<1> A_BLC_NMOS_DRIVE<1> VDD VSS / ++ RSC_IHPSG13_INVX2 +XA_CINV<0> A_BLT_PMOS_DRIVE<0> A_BLC_NMOS_DRIVE<0> VDD VSS / ++ RSC_IHPSG13_INVX2 +XA_TINV<3> A_BLC_PMOS_DRIVE<3> A_BLT_NMOS_DRIVE<3> VDD VSS / ++ RSC_IHPSG13_INVX2 +XA_TINV<2> A_BLC_PMOS_DRIVE<2> A_BLT_NMOS_DRIVE<2> VDD VSS / ++ RSC_IHPSG13_INVX2 +XA_TINV<1> A_BLC_PMOS_DRIVE<1> A_BLT_NMOS_DRIVE<1> VDD VSS / ++ RSC_IHPSG13_INVX2 +XA_TINV<0> A_BLC_PMOS_DRIVE<0> A_BLT_NMOS_DRIVE<0> VDD VSS / ++ RSC_IHPSG13_INVX2 +XB_SEL<3> B_SEL_P<3> B_SEL_N<3> VDD VSS / RSC_IHPSG13_INVX2 +XB_SEL<2> B_SEL_P<2> B_SEL_N<2> VDD VSS / RSC_IHPSG13_INVX2 +XB_SEL<1> B_SEL_P<1> B_SEL_N<1> VDD VSS / RSC_IHPSG13_INVX2 +XB_SEL<0> B_SEL_P<0> B_SEL_N<0> VDD VSS / RSC_IHPSG13_INVX2 +XB_TINV<3> B_BLC_PMOS_DRIVE<3> B_BLT_NMOS_DRIVE<3> VDD VSS / ++ RSC_IHPSG13_INVX2 +XB_TINV<2> B_BLC_PMOS_DRIVE<2> B_BLT_NMOS_DRIVE<2> VDD VSS / ++ RSC_IHPSG13_INVX2 +XB_TINV<1> B_BLC_PMOS_DRIVE<1> B_BLT_NMOS_DRIVE<1> VDD VSS / ++ RSC_IHPSG13_INVX2 +XB_TINV<0> B_BLC_PMOS_DRIVE<0> B_BLT_NMOS_DRIVE<0> VDD VSS / ++ RSC_IHPSG13_INVX2 +XB_CINV<3> B_BLT_PMOS_DRIVE<3> B_BLC_NMOS_DRIVE<3> VDD VSS / ++ RSC_IHPSG13_INVX2 +XB_CINV<2> B_BLT_PMOS_DRIVE<2> B_BLC_NMOS_DRIVE<2> VDD VSS / ++ RSC_IHPSG13_INVX2 +XB_CINV<1> B_BLT_PMOS_DRIVE<1> B_BLC_NMOS_DRIVE<1> VDD VSS / ++ RSC_IHPSG13_INVX2 +XB_CINV<0> B_BLT_PMOS_DRIVE<0> B_BLC_NMOS_DRIVE<0> VDD VSS / ++ RSC_IHPSG13_INVX2 +XA_TDEC<3> A_SEL_P<3> A_WR_ONE A_BLT_PMOS_DRIVE<3> VDD VSS / ++ RSC_IHPSG13_NAND2X2 +XA_TDEC<2> A_SEL_P<2> A_WR_ONE A_BLT_PMOS_DRIVE<2> VDD VSS / ++ RSC_IHPSG13_NAND2X2 +XA_TDEC<1> A_SEL_P<1> A_WR_ONE A_BLT_PMOS_DRIVE<1> VDD VSS / ++ RSC_IHPSG13_NAND2X2 +XA_TDEC<0> A_SEL_P<0> A_WR_ONE A_BLT_PMOS_DRIVE<0> VDD VSS / ++ RSC_IHPSG13_NAND2X2 +XA_CDEC<3> A_SEL_P<3> A_WR_ZERO A_BLC_PMOS_DRIVE<3> VDD VSS / ++ RSC_IHPSG13_NAND2X2 +XA_CDEC<2> A_SEL_P<2> A_WR_ZERO A_BLC_PMOS_DRIVE<2> VDD VSS / ++ RSC_IHPSG13_NAND2X2 +XA_CDEC<1> A_SEL_P<1> A_WR_ZERO A_BLC_PMOS_DRIVE<1> VDD VSS / ++ RSC_IHPSG13_NAND2X2 +XA_CDEC<0> A_SEL_P<0> A_WR_ZERO A_BLC_PMOS_DRIVE<0> VDD VSS / ++ RSC_IHPSG13_NAND2X2 +XB_CDEC<3> B_SEL_P<3> B_WR_ZERO B_BLC_PMOS_DRIVE<3> VDD VSS / ++ RSC_IHPSG13_NAND2X2 +XB_CDEC<2> B_SEL_P<2> B_WR_ZERO B_BLC_PMOS_DRIVE<2> VDD VSS / ++ RSC_IHPSG13_NAND2X2 +XB_CDEC<1> B_SEL_P<1> B_WR_ZERO B_BLC_PMOS_DRIVE<1> VDD VSS / ++ RSC_IHPSG13_NAND2X2 +XB_CDEC<0> B_SEL_P<0> B_WR_ZERO B_BLC_PMOS_DRIVE<0> VDD VSS / ++ RSC_IHPSG13_NAND2X2 +XB_TDEC<3> B_SEL_P<3> B_WR_ONE B_BLT_PMOS_DRIVE<3> VDD VSS / ++ RSC_IHPSG13_NAND2X2 +XB_TDEC<2> B_SEL_P<2> B_WR_ONE B_BLT_PMOS_DRIVE<2> VDD VSS / ++ RSC_IHPSG13_NAND2X2 +XB_TDEC<1> B_SEL_P<1> B_WR_ONE B_BLT_PMOS_DRIVE<1> VDD VSS / ++ RSC_IHPSG13_NAND2X2 +XB_TDEC<0> B_SEL_P<0> B_WR_ONE B_BLT_PMOS_DRIVE<0> VDD VSS / ++ RSC_IHPSG13_NAND2X2 +.ENDS +.SUBCKT RSC_IHPSG13_AND2X6 A B Z VDD VSS +MN3 Z net6 VSS VSS sg13_lv_nmos m=1 w=2.94u l=130.00n ng=3 nrd=0 nrs=0 +MN4 net9 B VSS VSS sg13_lv_nmos m=1 w=500.0n l=130.00n ng=1 nrd=0 nrs=0 +MN6 net6 A net9 VSS sg13_lv_nmos m=1 w=500.0n l=130.00n ng=1 nrd=0 nrs=0 +MP2 Z net6 VDD VDD sg13_lv_pmos m=1 w=4.86u l=130.00n ng=3 nrd=0 nrs=0 +MP0 net6 B VDD VDD sg13_lv_pmos m=1 w=860.00n l=130.00n ng=1 nrd=0 ++ nrs=0 +MP1 net6 A VDD VDD sg13_lv_pmos m=1 w=860.00n l=130.00n ng=1 nrd=0 ++ nrs=0 +.ENDS +.SUBCKT RM_IHPSG13_64x32_c2_2P_COLCTRL5 A_ADDR_COL<1> A_ADDR_COL<0> A_ADDR_DEC<7> ++ A_ADDR_DEC<6> A_ADDR_DEC<5> A_ADDR_DEC<4> A_ADDR_DEC<3> A_ADDR_DEC<2> ++ A_ADDR_DEC<1> A_ADDR_DEC<0> A_BIST_BM_I A_BIST_DW_I A_BIST_EN_I A_BLC<31> ++ A_BLC<30> A_BLC<29> A_BLC<28> A_BLC<27> A_BLC<26> A_BLC<25> A_BLC<24> ++ A_BLC<23> A_BLC<22> A_BLC<21> A_BLC<20> A_BLC<19> A_BLC<18> A_BLC<17> ++ A_BLC<16> A_BLC<15> A_BLC<14> A_BLC<13> A_BLC<12> A_BLC<11> A_BLC<10> ++ A_BLC<9> A_BLC<8> A_BLC<7> A_BLC<6> A_BLC<5> A_BLC<4> A_BLC<3> A_BLC<2> ++ A_BLC<1> A_BLC<0> A_BLT<31> A_BLT<30> A_BLT<29> A_BLT<28> A_BLT<27> ++ A_BLT<26> A_BLT<25> A_BLT<24> A_BLT<23> A_BLT<22> A_BLT<21> A_BLT<20> ++ A_BLT<19> A_BLT<18> A_BLT<17> A_BLT<16> A_BLT<15> A_BLT<14> A_BLT<13> ++ A_BLT<12> A_BLT<11> A_BLT<10> A_BLT<9> A_BLT<8> A_BLT<7> A_BLT<6> A_BLT<5> ++ A_BLT<4> A_BLT<3> A_BLT<2> A_BLT<1> A_BLT<0> A_BM_I A_DCLK_B_L A_DCLK_B_R ++ A_DCLK_L A_DCLK_R A_DR_O A_DW_I A_RCLK_B_L A_RCLK_B_R A_RCLK_L A_RCLK_R ++ A_TIEH_O A_WCLK_B_L A_WCLK_B_R A_WCLK_L A_WCLK_R B_ADDR_COL<1> B_ADDR_COL<0> ++ B_ADDR_DEC<7> B_ADDR_DEC<6> B_ADDR_DEC<5> B_ADDR_DEC<4> B_ADDR_DEC<3> ++ B_ADDR_DEC<2> B_ADDR_DEC<1> B_ADDR_DEC<0> B_BIST_BM_I B_BIST_DW_I ++ B_BIST_EN_I B_BLC<31> B_BLC<30> B_BLC<29> B_BLC<28> B_BLC<27> B_BLC<26> ++ B_BLC<25> B_BLC<24> B_BLC<23> B_BLC<22> B_BLC<21> B_BLC<20> B_BLC<19> ++ B_BLC<18> B_BLC<17> B_BLC<16> B_BLC<15> B_BLC<14> B_BLC<13> B_BLC<12> ++ B_BLC<11> B_BLC<10> B_BLC<9> B_BLC<8> B_BLC<7> B_BLC<6> B_BLC<5> B_BLC<4> ++ B_BLC<3> B_BLC<2> B_BLC<1> B_BLC<0> B_BLT<31> B_BLT<30> B_BLT<29> B_BLT<28> ++ B_BLT<27> B_BLT<26> B_BLT<25> B_BLT<24> B_BLT<23> B_BLT<22> B_BLT<21> ++ B_BLT<20> B_BLT<19> B_BLT<18> B_BLT<17> B_BLT<16> B_BLT<15> B_BLT<14> ++ B_BLT<13> B_BLT<12> B_BLT<11> B_BLT<10> B_BLT<9> B_BLT<8> B_BLT<7> B_BLT<6> ++ B_BLT<5> B_BLT<4> B_BLT<3> B_BLT<2> B_BLT<1> B_BLT<0> B_BM_I B_DCLK_B_L ++ B_DCLK_B_R B_DCLK_L B_DCLK_R B_DR_O B_DW_I B_RCLK_B_L B_RCLK_B_R B_RCLK_L ++ B_RCLK_R B_TIEH_O B_WCLK_B_L B_WCLK_B_R B_WCLK_L B_WCLK_R VDD VSS +XB_I80<1> B_WCLK_B_L B_RCLK_B_L B_W_nor_R<1> VDD VSS / ++ RSC_IHPSG13_AND2X2 +XB_I80<0> B_WCLK_B_L B_RCLK_B_L B_W_nor_R<0> VDD VSS / ++ RSC_IHPSG13_AND2X2 +XA_I80<1> A_WCLK_B_L A_RCLK_B_L A_W_nor_R<1> VDD VSS / ++ RSC_IHPSG13_AND2X2 +XA_I80<0> A_WCLK_B_L A_RCLK_B_L A_W_nor_R<0> VDD VSS / ++ RSC_IHPSG13_AND2X2 +XB_I44 B_BM_N B_WCLK_B_L B_DO_WRITE_P VDD VSS / RSC_IHPSG13_NOR2X2 +XA_I44 A_BM_N A_WCLK_B_L A_DO_WRITE_P VDD VSS / RSC_IHPSG13_NOR2X2 +XI_FILL4<16> VDD VSS / RSC_IHPSG13_FILLCAP4 +XI_FILL4<15> VDD VSS / RSC_IHPSG13_FILLCAP4 +XI_FILL4<14> VDD VSS / RSC_IHPSG13_FILLCAP4 +XI_FILL4<13> VDD VSS / RSC_IHPSG13_FILLCAP4 +XI_FILL4<12> VDD VSS / RSC_IHPSG13_FILLCAP4 +XI_FILL4<11> VDD VSS / RSC_IHPSG13_FILLCAP4 +XI_FILL4<10> VDD VSS / RSC_IHPSG13_FILLCAP4 +XI_FILL4<9> VDD VSS / RSC_IHPSG13_FILLCAP4 +XI_FILL4<8> VDD VSS / RSC_IHPSG13_FILLCAP4 +XI_FILL4<7> VDD VSS / RSC_IHPSG13_FILLCAP4 +XI_FILL4<6> VDD VSS / RSC_IHPSG13_FILLCAP4 +XI_FILL4<5> VDD VSS / RSC_IHPSG13_FILLCAP4 +XI_FILL4<4> VDD VSS / RSC_IHPSG13_FILLCAP4 +XI_FILL4<3> VDD VSS / RSC_IHPSG13_FILLCAP4 +XI_FILL4<2> VDD VSS / RSC_IHPSG13_FILLCAP4 +XI_FILL4<1> VDD VSS / RSC_IHPSG13_FILLCAP4 +XB_INV<6> B_N1<1> B_P1<1> VDD VSS / RSC_IHPSG13_CINVX4 +XB_INV<5> B_N0<1> B_P0<1> VDD VSS / RSC_IHPSG13_CINVX4 +XB_INV<4> B_N0<0> B_P0<0> VDD VSS / RSC_IHPSG13_CINVX4 +XB_INV<3> B_ADDR_COL<1> B_N1<1> VDD VSS / RSC_IHPSG13_CINVX4 +XB_INV<2> B_ADDR_COL<1> B_N1<0> VDD VSS / RSC_IHPSG13_CINVX4 +XB_INV<1> B_ADDR_COL<0> B_N0<1> VDD VSS / RSC_IHPSG13_CINVX4 +XB_INV<0> B_ADDR_COL<0> B_N0<0> VDD VSS / RSC_IHPSG13_CINVX4 +XA_INV<6> A_N1<1> A_P1<1> VDD VSS / RSC_IHPSG13_CINVX4 +XA_INV<5> A_N0<1> A_P0<1> VDD VSS / RSC_IHPSG13_CINVX4 +XA_INV<4> A_N0<0> A_P0<0> VDD VSS / RSC_IHPSG13_CINVX4 +XA_INV<3> A_ADDR_COL<1> A_N1<1> VDD VSS / RSC_IHPSG13_CINVX4 +XA_INV<2> A_ADDR_COL<1> A_N1<0> VDD VSS / RSC_IHPSG13_CINVX4 +XA_INV<1> A_ADDR_COL<0> A_N0<1> VDD VSS / RSC_IHPSG13_CINVX4 +XA_INV<0> A_ADDR_COL<0> A_N0<0> VDD VSS / RSC_IHPSG13_CINVX4 +XB_I81<3> B_W_nor_R<1> B_PRE_N VDD VSS / RSC_IHPSG13_CINVX4_WN +XB_I81<2> B_W_nor_R<1> B_PRE_N VDD VSS / RSC_IHPSG13_CINVX4_WN +XB_I81<1> B_W_nor_R<0> B_PRE_N VDD VSS / RSC_IHPSG13_CINVX4_WN +XB_I81<0> B_W_nor_R<0> B_PRE_N VDD VSS / RSC_IHPSG13_CINVX4_WN +XA_I81<3> A_W_nor_R<1> A_PRE_N VDD VSS / RSC_IHPSG13_CINVX4_WN +XA_I81<2> A_W_nor_R<1> A_PRE_N VDD VSS / RSC_IHPSG13_CINVX4_WN +XA_I81<1> A_W_nor_R<0> A_PRE_N VDD VSS / RSC_IHPSG13_CINVX4_WN +XA_I81<0> A_W_nor_R<0> A_PRE_N VDD VSS / RSC_IHPSG13_CINVX4_WN +XI_FILL8<78> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI_FILL8<77> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI_FILL8<76> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI_FILL8<75> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI_FILL8<74> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI_FILL8<73> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI_FILL8<72> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI_FILL8<71> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI_FILL8<70> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI_FILL8<69> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI_FILL8<68> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI_FILL8<67> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI_FILL8<66> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI_FILL8<65> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI_FILL8<64> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI_FILL8<63> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI_FILL8<62> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI_FILL8<61> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI_FILL8<60> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI_FILL8<59> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI_FILL8<58> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI_FILL8<57> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI_FILL8<56> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI_FILL8<55> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI_FILL8<54> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI_FILL8<53> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI_FILL8<52> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI_FILL8<51> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI_FILL8<50> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI_FILL8<49> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI_FILL8<48> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI_FILL8<47> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI_FILL8<46> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI_FILL8<45> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI_FILL8<44> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI_FILL8<43> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI_FILL8<42> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI_FILL8<41> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI_FILL8<40> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI_FILL8<39> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI_FILL8<38> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI_FILL8<37> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI_FILL8<36> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI_FILL8<35> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI_FILL8<34> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI_FILL8<33> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI_FILL8<32> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI_FILL8<31> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI_FILL8<30> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI_FILL8<29> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI_FILL8<28> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI_FILL8<27> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI_FILL8<26> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI_FILL8<25> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI_FILL8<24> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI_FILL8<23> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI_FILL8<22> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI_FILL8<21> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI_FILL8<20> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI_FILL8<19> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI_FILL8<18> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI_FILL8<17> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI_FILL8<16> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI_FILL8<15> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI_FILL8<14> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI_FILL8<13> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI_FILL8<12> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI_FILL8<11> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI_FILL8<10> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI_FILL8<9> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI_FILL8<8> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI_FILL8<7> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI_FILL8<6> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI_FILL8<5> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI_FILL8<4> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI_FILL8<3> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI_FILL8<2> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI_FILL8<1> VDD VSS / RSC_IHPSG13_FILLCAP8 +XAB_BLMUX<7> A_BLC<31> A_BLC<30> A_BLC<29> A_BLC<28> A_BLC_SEL A_BLT<31> ++ A_BLT<30> A_BLT<29> A_BLT<28> A_BLT_SEL A_PRE_N A_SEL_P<31> A_SEL_P<30> ++ A_SEL_P<29> A_SEL_P<28> A_WR_ONE A_WR_ZERO B_BLC<31> B_BLC<30> B_BLC<29> ++ B_BLC<28> B_BLC_SEL B_BLT<31> B_BLT<30> B_BLT<29> B_BLT<28> B_BLT_SEL ++ B_PRE_N B_SEL_P<31> B_SEL_P<30> B_SEL_P<29> B_SEL_P<28> B_WR_ONE B_WR_ZERO ++ VDD VSS / RM_IHPSG13_64x32_c2_2P_BLDRV +XAB_BLMUX<6> A_BLC<27> A_BLC<26> A_BLC<25> A_BLC<24> A_BLC_SEL A_BLT<27> ++ A_BLT<26> A_BLT<25> A_BLT<24> A_BLT_SEL A_PRE_N A_SEL_P<27> A_SEL_P<26> ++ A_SEL_P<25> A_SEL_P<24> A_WR_ONE A_WR_ZERO B_BLC<27> B_BLC<26> B_BLC<25> ++ B_BLC<24> B_BLC_SEL B_BLT<27> B_BLT<26> B_BLT<25> B_BLT<24> B_BLT_SEL ++ B_PRE_N B_SEL_P<27> B_SEL_P<26> B_SEL_P<25> B_SEL_P<24> B_WR_ONE B_WR_ZERO ++ VDD VSS / RM_IHPSG13_64x32_c2_2P_BLDRV +XAB_BLMUX<5> A_BLC<23> A_BLC<22> A_BLC<21> A_BLC<20> A_BLC_SEL A_BLT<23> ++ A_BLT<22> A_BLT<21> A_BLT<20> A_BLT_SEL A_PRE_N A_SEL_P<23> A_SEL_P<22> ++ A_SEL_P<21> A_SEL_P<20> A_WR_ONE A_WR_ZERO B_BLC<23> B_BLC<22> B_BLC<21> ++ B_BLC<20> B_BLC_SEL B_BLT<23> B_BLT<22> B_BLT<21> B_BLT<20> B_BLT_SEL ++ B_PRE_N B_SEL_P<23> B_SEL_P<22> B_SEL_P<21> B_SEL_P<20> B_WR_ONE B_WR_ZERO ++ VDD VSS / RM_IHPSG13_64x32_c2_2P_BLDRV +XAB_BLMUX<4> A_BLC<19> A_BLC<18> A_BLC<17> A_BLC<16> A_BLC_SEL A_BLT<19> ++ A_BLT<18> A_BLT<17> A_BLT<16> A_BLT_SEL A_PRE_N A_SEL_P<19> A_SEL_P<18> ++ A_SEL_P<17> A_SEL_P<16> A_WR_ONE A_WR_ZERO B_BLC<19> B_BLC<18> B_BLC<17> ++ B_BLC<16> B_BLC_SEL B_BLT<19> B_BLT<18> B_BLT<17> B_BLT<16> B_BLT_SEL ++ B_PRE_N B_SEL_P<19> B_SEL_P<18> B_SEL_P<17> B_SEL_P<16> B_WR_ONE B_WR_ZERO ++ VDD VSS / RM_IHPSG13_64x32_c2_2P_BLDRV +XAB_BLMUX<3> A_BLC<15> A_BLC<14> A_BLC<13> A_BLC<12> A_BLC_SEL A_BLT<15> ++ A_BLT<14> A_BLT<13> A_BLT<12> A_BLT_SEL A_PRE_N A_SEL_P<15> A_SEL_P<14> ++ A_SEL_P<13> A_SEL_P<12> A_WR_ONE A_WR_ZERO B_BLC<15> B_BLC<14> B_BLC<13> ++ B_BLC<12> B_BLC_SEL B_BLT<15> B_BLT<14> B_BLT<13> B_BLT<12> B_BLT_SEL ++ B_PRE_N B_SEL_P<15> B_SEL_P<14> B_SEL_P<13> B_SEL_P<12> B_WR_ONE B_WR_ZERO ++ VDD VSS / RM_IHPSG13_64x32_c2_2P_BLDRV +XAB_BLMUX<2> A_BLC<11> A_BLC<10> A_BLC<9> A_BLC<8> A_BLC_SEL A_BLT<11> ++ A_BLT<10> A_BLT<9> A_BLT<8> A_BLT_SEL A_PRE_N A_SEL_P<11> A_SEL_P<10> ++ A_SEL_P<9> A_SEL_P<8> A_WR_ONE A_WR_ZERO B_BLC<11> B_BLC<10> B_BLC<9> ++ B_BLC<8> B_BLC_SEL B_BLT<11> B_BLT<10> B_BLT<9> B_BLT<8> B_BLT_SEL B_PRE_N ++ B_SEL_P<11> B_SEL_P<10> B_SEL_P<9> B_SEL_P<8> B_WR_ONE B_WR_ZERO VDD ++ VSS / RM_IHPSG13_64x32_c2_2P_BLDRV +XAB_BLMUX<1> A_BLC<7> A_BLC<6> A_BLC<5> A_BLC<4> A_BLC_SEL A_BLT<7> A_BLT<6> ++ A_BLT<5> A_BLT<4> A_BLT_SEL A_PRE_N A_SEL_P<7> A_SEL_P<6> A_SEL_P<5> ++ A_SEL_P<4> A_WR_ONE A_WR_ZERO B_BLC<7> B_BLC<6> B_BLC<5> B_BLC<4> B_BLC_SEL ++ B_BLT<7> B_BLT<6> B_BLT<5> B_BLT<4> B_BLT_SEL B_PRE_N B_SEL_P<7> B_SEL_P<6> ++ B_SEL_P<5> B_SEL_P<4> B_WR_ONE B_WR_ZERO VDD VSS / ++ RM_IHPSG13_64x32_c2_2P_BLDRV +XAB_BLMUX<0> A_BLC<3> A_BLC<2> A_BLC<1> A_BLC<0> A_BLC_SEL A_BLT<3> A_BLT<2> ++ A_BLT<1> A_BLT<0> A_BLT_SEL A_PRE_N A_SEL_P<3> A_SEL_P<2> A_SEL_P<1> ++ A_SEL_P<0> A_WR_ONE A_WR_ZERO B_BLC<3> B_BLC<2> B_BLC<1> B_BLC<0> B_BLC_SEL ++ B_BLT<3> B_BLT<2> B_BLT<1> B_BLT<0> B_BLT_SEL B_PRE_N B_SEL_P<3> B_SEL_P<2> ++ B_SEL_P<1> B_SEL_P<0> B_WR_ONE B_WR_ZERO VDD VSS / ++ RM_IHPSG13_64x32_c2_2P_BLDRV +XB_I51 net037 B_DR_O VDD VSS / RSC_IHPSG13_INVX4 +XA_I51 net19 A_DR_O VDD VSS / RSC_IHPSG13_INVX4 +XB_I78 B_RCLK_B_L B_SAE VDD VSS / RSC_IHPSG13_CBUFX2 +XA_I78 A_RCLK_B_L A_SAE VDD VSS / RSC_IHPSG13_CBUFX2 +XB_I69 B_DCLK_L B_DCLK_B_L VDD VSS / RSC_IHPSG13_CINVX8 +XB_I50 B_WCLK_L B_WCLK_B_L VDD VSS / RSC_IHPSG13_CINVX8 +XB_EBUF B_RCLK_L B_RCLK_B_L VDD VSS / RSC_IHPSG13_CINVX8 +XA_I69 A_DCLK_L A_DCLK_B_L VDD VSS / RSC_IHPSG13_CINVX8 +XA_I50 A_WCLK_L A_WCLK_B_L VDD VSS / RSC_IHPSG13_CINVX8 +XA_EBUF A_RCLK_L A_RCLK_B_L VDD VSS / RSC_IHPSG13_CINVX8 +XB_I76 B_DI_N B_DO_WRITE_P B_WR_ZERO VDD VSS / RSC_IHPSG13_AND2X6 +XB_I75 B_DI_R B_DO_WRITE_P B_WR_ONE VDD VSS / RSC_IHPSG13_AND2X6 +XA_I76 A_DI_N A_DO_WRITE_P A_WR_ZERO VDD VSS / RSC_IHPSG13_AND2X6 +XA_I75 A_DI_R A_DO_WRITE_P A_WR_ONE VDD VSS / RSC_IHPSG13_AND2X6 +XB_I83 B_BM_R B_BM_N VDD VSS / RSC_IHPSG13_INVX2 +XB_DEC3INV<31> net041<0> B_SEL_P<31> VDD VSS / RSC_IHPSG13_INVX2 +XB_DEC3INV<30> net041<1> B_SEL_P<30> VDD VSS / RSC_IHPSG13_INVX2 +XB_DEC3INV<29> net041<2> B_SEL_P<29> VDD VSS / RSC_IHPSG13_INVX2 +XB_DEC3INV<28> net041<3> B_SEL_P<28> VDD VSS / RSC_IHPSG13_INVX2 +XB_DEC3INV<27> net041<4> B_SEL_P<27> VDD VSS / RSC_IHPSG13_INVX2 +XB_DEC3INV<26> net041<5> B_SEL_P<26> VDD VSS / RSC_IHPSG13_INVX2 +XB_DEC3INV<25> net041<6> B_SEL_P<25> VDD VSS / RSC_IHPSG13_INVX2 +XB_DEC3INV<24> net041<7> B_SEL_P<24> VDD VSS / RSC_IHPSG13_INVX2 +XB_DEC3INV<23> net041<8> B_SEL_P<23> VDD VSS / RSC_IHPSG13_INVX2 +XB_DEC3INV<22> net041<9> B_SEL_P<22> VDD VSS / RSC_IHPSG13_INVX2 +XB_DEC3INV<21> net041<10> B_SEL_P<21> VDD VSS / RSC_IHPSG13_INVX2 +XB_DEC3INV<20> net041<11> B_SEL_P<20> VDD VSS / RSC_IHPSG13_INVX2 +XB_DEC3INV<19> net041<12> B_SEL_P<19> VDD VSS / RSC_IHPSG13_INVX2 +XB_DEC3INV<18> net041<13> B_SEL_P<18> VDD VSS / RSC_IHPSG13_INVX2 +XB_DEC3INV<17> net041<14> B_SEL_P<17> VDD VSS / RSC_IHPSG13_INVX2 +XB_DEC3INV<16> net041<15> B_SEL_P<16> VDD VSS / RSC_IHPSG13_INVX2 +XB_DEC3INV<15> net041<16> B_SEL_P<15> VDD VSS / RSC_IHPSG13_INVX2 +XB_DEC3INV<14> net041<17> B_SEL_P<14> VDD VSS / RSC_IHPSG13_INVX2 +XB_DEC3INV<13> net041<18> B_SEL_P<13> VDD VSS / RSC_IHPSG13_INVX2 +XB_DEC3INV<12> net041<19> B_SEL_P<12> VDD VSS / RSC_IHPSG13_INVX2 +XB_DEC3INV<11> net041<20> B_SEL_P<11> VDD VSS / RSC_IHPSG13_INVX2 +XB_DEC3INV<10> net041<21> B_SEL_P<10> VDD VSS / RSC_IHPSG13_INVX2 +XB_DEC3INV<9> net041<22> B_SEL_P<9> VDD VSS / RSC_IHPSG13_INVX2 +XB_DEC3INV<8> net041<23> B_SEL_P<8> VDD VSS / RSC_IHPSG13_INVX2 +XB_DEC3INV<7> net041<24> B_SEL_P<7> VDD VSS / RSC_IHPSG13_INVX2 +XB_DEC3INV<6> net041<25> B_SEL_P<6> VDD VSS / RSC_IHPSG13_INVX2 +XB_DEC3INV<5> net041<26> B_SEL_P<5> VDD VSS / RSC_IHPSG13_INVX2 +XB_DEC3INV<4> net041<27> B_SEL_P<4> VDD VSS / RSC_IHPSG13_INVX2 +XB_DEC3INV<3> net041<28> B_SEL_P<3> VDD VSS / RSC_IHPSG13_INVX2 +XB_DEC3INV<2> net041<29> B_SEL_P<2> VDD VSS / RSC_IHPSG13_INVX2 +XB_DEC3INV<1> net041<30> B_SEL_P<1> VDD VSS / RSC_IHPSG13_INVX2 +XB_DEC3INV<0> net041<31> B_SEL_P<0> VDD VSS / RSC_IHPSG13_INVX2 +XB_I49 B_DI_R B_DI_N VDD VSS / RSC_IHPSG13_INVX2 +XA_I83 A_BM_R A_BM_N VDD VSS / RSC_IHPSG13_INVX2 +XA_DEC3INV<31> net23<0> A_SEL_P<31> VDD VSS / RSC_IHPSG13_INVX2 +XA_DEC3INV<30> net23<1> A_SEL_P<30> VDD VSS / RSC_IHPSG13_INVX2 +XA_DEC3INV<29> net23<2> A_SEL_P<29> VDD VSS / RSC_IHPSG13_INVX2 +XA_DEC3INV<28> net23<3> A_SEL_P<28> VDD VSS / RSC_IHPSG13_INVX2 +XA_DEC3INV<27> net23<4> A_SEL_P<27> VDD VSS / RSC_IHPSG13_INVX2 +XA_DEC3INV<26> net23<5> A_SEL_P<26> VDD VSS / RSC_IHPSG13_INVX2 +XA_DEC3INV<25> net23<6> A_SEL_P<25> VDD VSS / RSC_IHPSG13_INVX2 +XA_DEC3INV<24> net23<7> A_SEL_P<24> VDD VSS / RSC_IHPSG13_INVX2 +XA_DEC3INV<23> net23<8> A_SEL_P<23> VDD VSS / RSC_IHPSG13_INVX2 +XA_DEC3INV<22> net23<9> A_SEL_P<22> VDD VSS / RSC_IHPSG13_INVX2 +XA_DEC3INV<21> net23<10> A_SEL_P<21> VDD VSS / RSC_IHPSG13_INVX2 +XA_DEC3INV<20> net23<11> A_SEL_P<20> VDD VSS / RSC_IHPSG13_INVX2 +XA_DEC3INV<19> net23<12> A_SEL_P<19> VDD VSS / RSC_IHPSG13_INVX2 +XA_DEC3INV<18> net23<13> A_SEL_P<18> VDD VSS / RSC_IHPSG13_INVX2 +XA_DEC3INV<17> net23<14> A_SEL_P<17> VDD VSS / RSC_IHPSG13_INVX2 +XA_DEC3INV<16> net23<15> A_SEL_P<16> VDD VSS / RSC_IHPSG13_INVX2 +XA_DEC3INV<15> net23<16> A_SEL_P<15> VDD VSS / RSC_IHPSG13_INVX2 +XA_DEC3INV<14> net23<17> A_SEL_P<14> VDD VSS / RSC_IHPSG13_INVX2 +XA_DEC3INV<13> net23<18> A_SEL_P<13> VDD VSS / RSC_IHPSG13_INVX2 +XA_DEC3INV<12> net23<19> A_SEL_P<12> VDD VSS / RSC_IHPSG13_INVX2 +XA_DEC3INV<11> net23<20> A_SEL_P<11> VDD VSS / RSC_IHPSG13_INVX2 +XA_DEC3INV<10> net23<21> A_SEL_P<10> VDD VSS / RSC_IHPSG13_INVX2 +XA_DEC3INV<9> net23<22> A_SEL_P<9> VDD VSS / RSC_IHPSG13_INVX2 +XA_DEC3INV<8> net23<23> A_SEL_P<8> VDD VSS / RSC_IHPSG13_INVX2 +XA_DEC3INV<7> net23<24> A_SEL_P<7> VDD VSS / RSC_IHPSG13_INVX2 +XA_DEC3INV<6> net23<25> A_SEL_P<6> VDD VSS / RSC_IHPSG13_INVX2 +XA_DEC3INV<5> net23<26> A_SEL_P<5> VDD VSS / RSC_IHPSG13_INVX2 +XA_DEC3INV<4> net23<27> A_SEL_P<4> VDD VSS / RSC_IHPSG13_INVX2 +XA_DEC3INV<3> net23<28> A_SEL_P<3> VDD VSS / RSC_IHPSG13_INVX2 +XA_DEC3INV<2> net23<29> A_SEL_P<2> VDD VSS / RSC_IHPSG13_INVX2 +XA_DEC3INV<1> net23<30> A_SEL_P<1> VDD VSS / RSC_IHPSG13_INVX2 +XA_DEC3INV<0> net23<31> A_SEL_P<0> VDD VSS / RSC_IHPSG13_INVX2 +XA_I49 A_DI_R A_DI_N VDD VSS / RSC_IHPSG13_INVX2 +XB_ISENSE B_SAE B_BLC_SEL B_BLT_SEL net037 net038 VDD VSS / ++ RSC_IHPSG13_DFPQD_MSAFFX2 +XA_ISENSE A_SAE A_BLC_SEL A_BLT_SEL net19 net20 VDD VSS / ++ RSC_IHPSG13_DFPQD_MSAFFX2 +XB_DREG B_BIST_EN_I B_BIST_DW_I B_DCLK_B_L B_DW_I B_DI_R net042 VDD ++ VSS / RSC_IHPSG13_DFNQMX2IX1 +XB_BREG B_BIST_EN_I B_BIST_BM_I B_DCLK_B_L B_BM_I B_BM_R net043 VDD ++ VSS / RSC_IHPSG13_DFNQMX2IX1 +XA_DREG A_BIST_EN_I A_BIST_DW_I A_DCLK_B_L A_DW_I A_DI_R net22 VDD VSS ++ / RSC_IHPSG13_DFNQMX2IX1 +XA_BREG A_BIST_EN_I A_BIST_BM_I A_DCLK_B_L A_BM_I A_BM_R net21 VDD VSS ++ / RSC_IHPSG13_DFNQMX2IX1 +XB_DEC3<31> B_P1<1> B_P0<1> B_ADDR_DEC<7> net041<0> VDD VSS / ++ RSC_IHPSG13_NAND3X2 +XB_DEC3<30> B_P1<1> B_P0<1> B_ADDR_DEC<6> net041<1> VDD VSS / ++ RSC_IHPSG13_NAND3X2 +XB_DEC3<29> B_P1<1> B_P0<1> B_ADDR_DEC<5> net041<2> VDD VSS / ++ RSC_IHPSG13_NAND3X2 +XB_DEC3<28> B_P1<1> B_P0<1> B_ADDR_DEC<4> net041<3> VDD VSS / ++ RSC_IHPSG13_NAND3X2 +XB_DEC3<27> B_P1<1> B_P0<1> B_ADDR_DEC<3> net041<4> VDD VSS / ++ RSC_IHPSG13_NAND3X2 +XB_DEC3<26> B_P1<1> B_P0<1> B_ADDR_DEC<2> net041<5> VDD VSS / ++ RSC_IHPSG13_NAND3X2 +XB_DEC3<25> B_P1<1> B_P0<1> B_ADDR_DEC<1> net041<6> VDD VSS / ++ RSC_IHPSG13_NAND3X2 +XB_DEC3<24> B_P1<1> B_P0<1> B_ADDR_DEC<0> net041<7> VDD VSS / ++ RSC_IHPSG13_NAND3X2 +XB_DEC3<23> B_P1<1> B_N0<1> B_ADDR_DEC<7> net041<8> VDD VSS / ++ RSC_IHPSG13_NAND3X2 +XB_DEC3<22> B_P1<1> B_N0<1> B_ADDR_DEC<6> net041<9> VDD VSS / ++ RSC_IHPSG13_NAND3X2 +XB_DEC3<21> B_P1<1> B_N0<1> B_ADDR_DEC<5> net041<10> VDD VSS / ++ RSC_IHPSG13_NAND3X2 +XB_DEC3<20> B_P1<1> B_N0<1> B_ADDR_DEC<4> net041<11> VDD VSS / ++ RSC_IHPSG13_NAND3X2 +XB_DEC3<19> B_P1<1> B_N0<1> B_ADDR_DEC<3> net041<12> VDD VSS / ++ RSC_IHPSG13_NAND3X2 +XB_DEC3<18> B_P1<1> B_N0<1> B_ADDR_DEC<2> net041<13> VDD VSS / ++ RSC_IHPSG13_NAND3X2 +XB_DEC3<17> B_P1<1> B_N0<1> B_ADDR_DEC<1> net041<14> VDD VSS / ++ RSC_IHPSG13_NAND3X2 +XB_DEC3<16> B_P1<1> B_N0<1> B_ADDR_DEC<0> net041<15> VDD VSS / ++ RSC_IHPSG13_NAND3X2 +XB_DEC3<15> B_N1<0> B_P0<0> B_ADDR_DEC<7> net041<16> VDD VSS / ++ RSC_IHPSG13_NAND3X2 +XB_DEC3<14> B_N1<0> B_P0<0> B_ADDR_DEC<6> net041<17> VDD VSS / ++ RSC_IHPSG13_NAND3X2 +XB_DEC3<13> B_N1<0> B_P0<0> B_ADDR_DEC<5> net041<18> VDD VSS / ++ RSC_IHPSG13_NAND3X2 +XB_DEC3<12> B_N1<0> B_P0<0> B_ADDR_DEC<4> net041<19> VDD VSS / ++ RSC_IHPSG13_NAND3X2 +XB_DEC3<11> B_N1<0> B_P0<0> B_ADDR_DEC<3> net041<20> VDD VSS / ++ RSC_IHPSG13_NAND3X2 +XB_DEC3<10> B_N1<0> B_P0<0> B_ADDR_DEC<2> net041<21> VDD VSS / ++ RSC_IHPSG13_NAND3X2 +XB_DEC3<9> B_N1<0> B_P0<0> B_ADDR_DEC<1> net041<22> VDD VSS / ++ RSC_IHPSG13_NAND3X2 +XB_DEC3<8> B_N1<0> B_P0<0> B_ADDR_DEC<0> net041<23> VDD VSS / ++ RSC_IHPSG13_NAND3X2 +XB_DEC3<7> B_N1<0> B_N0<0> B_ADDR_DEC<7> net041<24> VDD VSS / ++ RSC_IHPSG13_NAND3X2 +XB_DEC3<6> B_N1<0> B_N0<0> B_ADDR_DEC<6> net041<25> VDD VSS / ++ RSC_IHPSG13_NAND3X2 +XB_DEC3<5> B_N1<0> B_N0<0> B_ADDR_DEC<5> net041<26> VDD VSS / ++ RSC_IHPSG13_NAND3X2 +XB_DEC3<4> B_N1<0> B_N0<0> B_ADDR_DEC<4> net041<27> VDD VSS / ++ RSC_IHPSG13_NAND3X2 +XB_DEC3<3> B_N1<0> B_N0<0> B_ADDR_DEC<3> net041<28> VDD VSS / ++ RSC_IHPSG13_NAND3X2 +XB_DEC3<2> B_N1<0> B_N0<0> B_ADDR_DEC<2> net041<29> VDD VSS / ++ RSC_IHPSG13_NAND3X2 +XB_DEC3<1> B_N1<0> B_N0<0> B_ADDR_DEC<1> net041<30> VDD VSS / ++ RSC_IHPSG13_NAND3X2 +XB_DEC3<0> B_N1<0> B_N0<0> B_ADDR_DEC<0> net041<31> VDD VSS / ++ RSC_IHPSG13_NAND3X2 +XA_DEC3<31> A_P1<1> A_P0<1> A_ADDR_DEC<7> net23<0> VDD VSS / ++ RSC_IHPSG13_NAND3X2 +XA_DEC3<30> A_P1<1> A_P0<1> A_ADDR_DEC<6> net23<1> VDD VSS / ++ RSC_IHPSG13_NAND3X2 +XA_DEC3<29> A_P1<1> A_P0<1> A_ADDR_DEC<5> net23<2> VDD VSS / ++ RSC_IHPSG13_NAND3X2 +XA_DEC3<28> A_P1<1> A_P0<1> A_ADDR_DEC<4> net23<3> VDD VSS / ++ RSC_IHPSG13_NAND3X2 +XA_DEC3<27> A_P1<1> A_P0<1> A_ADDR_DEC<3> net23<4> VDD VSS / ++ RSC_IHPSG13_NAND3X2 +XA_DEC3<26> A_P1<1> A_P0<1> A_ADDR_DEC<2> net23<5> VDD VSS / ++ RSC_IHPSG13_NAND3X2 +XA_DEC3<25> A_P1<1> A_P0<1> A_ADDR_DEC<1> net23<6> VDD VSS / ++ RSC_IHPSG13_NAND3X2 +XA_DEC3<24> A_P1<1> A_P0<1> A_ADDR_DEC<0> net23<7> VDD VSS / ++ RSC_IHPSG13_NAND3X2 +XA_DEC3<23> A_P1<1> A_N0<1> A_ADDR_DEC<7> net23<8> VDD VSS / ++ RSC_IHPSG13_NAND3X2 +XA_DEC3<22> A_P1<1> A_N0<1> A_ADDR_DEC<6> net23<9> VDD VSS / ++ RSC_IHPSG13_NAND3X2 +XA_DEC3<21> A_P1<1> A_N0<1> A_ADDR_DEC<5> net23<10> VDD VSS / ++ RSC_IHPSG13_NAND3X2 +XA_DEC3<20> A_P1<1> A_N0<1> A_ADDR_DEC<4> net23<11> VDD VSS / ++ RSC_IHPSG13_NAND3X2 +XA_DEC3<19> A_P1<1> A_N0<1> A_ADDR_DEC<3> net23<12> VDD VSS / ++ RSC_IHPSG13_NAND3X2 +XA_DEC3<18> A_P1<1> A_N0<1> A_ADDR_DEC<2> net23<13> VDD VSS / ++ RSC_IHPSG13_NAND3X2 +XA_DEC3<17> A_P1<1> A_N0<1> A_ADDR_DEC<1> net23<14> VDD VSS / ++ RSC_IHPSG13_NAND3X2 +XA_DEC3<16> A_P1<1> A_N0<1> A_ADDR_DEC<0> net23<15> VDD VSS / ++ RSC_IHPSG13_NAND3X2 +XA_DEC3<15> A_N1<0> A_P0<0> A_ADDR_DEC<7> net23<16> VDD VSS / ++ RSC_IHPSG13_NAND3X2 +XA_DEC3<14> A_N1<0> A_P0<0> A_ADDR_DEC<6> net23<17> VDD VSS / ++ RSC_IHPSG13_NAND3X2 +XA_DEC3<13> A_N1<0> A_P0<0> A_ADDR_DEC<5> net23<18> VDD VSS / ++ RSC_IHPSG13_NAND3X2 +XA_DEC3<12> A_N1<0> A_P0<0> A_ADDR_DEC<4> net23<19> VDD VSS / ++ RSC_IHPSG13_NAND3X2 +XA_DEC3<11> A_N1<0> A_P0<0> A_ADDR_DEC<3> net23<20> VDD VSS / ++ RSC_IHPSG13_NAND3X2 +XA_DEC3<10> A_N1<0> A_P0<0> A_ADDR_DEC<2> net23<21> VDD VSS / ++ RSC_IHPSG13_NAND3X2 +XA_DEC3<9> A_N1<0> A_P0<0> A_ADDR_DEC<1> net23<22> VDD VSS / ++ RSC_IHPSG13_NAND3X2 +XA_DEC3<8> A_N1<0> A_P0<0> A_ADDR_DEC<0> net23<23> VDD VSS / ++ RSC_IHPSG13_NAND3X2 +XA_DEC3<7> A_N1<0> A_N0<0> A_ADDR_DEC<7> net23<24> VDD VSS / ++ RSC_IHPSG13_NAND3X2 +XA_DEC3<6> A_N1<0> A_N0<0> A_ADDR_DEC<6> net23<25> VDD VSS / ++ RSC_IHPSG13_NAND3X2 +XA_DEC3<5> A_N1<0> A_N0<0> A_ADDR_DEC<5> net23<26> VDD VSS / ++ RSC_IHPSG13_NAND3X2 +XA_DEC3<4> A_N1<0> A_N0<0> A_ADDR_DEC<4> net23<27> VDD VSS / ++ RSC_IHPSG13_NAND3X2 +XA_DEC3<3> A_N1<0> A_N0<0> A_ADDR_DEC<3> net23<28> VDD VSS / ++ RSC_IHPSG13_NAND3X2 +XA_DEC3<2> A_N1<0> A_N0<0> A_ADDR_DEC<2> net23<29> VDD VSS / ++ RSC_IHPSG13_NAND3X2 +XA_DEC3<1> A_N1<0> A_N0<0> A_ADDR_DEC<1> net23<30> VDD VSS / ++ RSC_IHPSG13_NAND3X2 +XA_DEC3<0> A_N1<0> A_N0<0> A_ADDR_DEC<0> net23<31> VDD VSS / ++ RSC_IHPSG13_NAND3X2 +XB_I89 B_DCLK_B_L B_DCLK_B_R / RSC_IHPSG13_MET3RES +XB_I91 B_RCLK_B_L B_RCLK_B_R / RSC_IHPSG13_MET3RES +XB_I90 B_WCLK_B_L B_WCLK_B_R / RSC_IHPSG13_MET3RES +XB_I88 B_DCLK_L B_DCLK_R / RSC_IHPSG13_MET3RES +XB_I87 B_WCLK_L B_WCLK_R / RSC_IHPSG13_MET3RES +XB_R2 B_RCLK_L B_RCLK_R / RSC_IHPSG13_MET3RES +XA_I89 A_DCLK_B_L A_DCLK_B_R / RSC_IHPSG13_MET3RES +XA_I91 A_RCLK_B_L A_RCLK_B_R / RSC_IHPSG13_MET3RES +XA_I90 A_WCLK_B_L A_WCLK_B_R / RSC_IHPSG13_MET3RES +XA_I88 A_DCLK_L A_DCLK_R / RSC_IHPSG13_MET3RES +XA_I87 A_WCLK_L A_WCLK_R / RSC_IHPSG13_MET3RES +XA_R2 A_RCLK_L A_RCLK_R / RSC_IHPSG13_MET3RES +XB_BM_TIEH B_TIEH_O VDD VSS / RSC_IHPSG13_TIEH +XA_BM_TIEH A_TIEH_O VDD VSS / RSC_IHPSG13_TIEH +.ENDS +.SUBCKT RM_IHPSG13_64x32_c2_2P_COLDRV13_FILL4 VDD VSS +XI0<11> VDD VSS / RSC_IHPSG13_FILLCAP4 +XI0<10> VDD VSS / RSC_IHPSG13_FILLCAP4 +XI0<9> VDD VSS / RSC_IHPSG13_FILLCAP4 +XI0<8> VDD VSS / RSC_IHPSG13_FILLCAP4 +XI0<7> VDD VSS / RSC_IHPSG13_FILLCAP4 +XI0<6> VDD VSS / RSC_IHPSG13_FILLCAP4 +XI0<5> VDD VSS / RSC_IHPSG13_FILLCAP4 +XI0<4> VDD VSS / RSC_IHPSG13_FILLCAP4 +XI0<3> VDD VSS / RSC_IHPSG13_FILLCAP4 +XI0<2> VDD VSS / RSC_IHPSG13_FILLCAP4 +XI0<1> VDD VSS / RSC_IHPSG13_FILLCAP4 +.ENDS + + +.SUBCKT RSC_IHPSG13_CBUFX16 A Z VDD VSS +MN0 net4 A VSS VSS sg13_lv_nmos m=1 w=2.115u l=130.00n ng=3 nrd=0 nrs=0 +MN1 Z net4 VSS VSS sg13_lv_nmos m=1 w=5.64u l=130.00n ng=8 nrd=0 nrs=0 +MP1 Z net4 VDD VDD sg13_lv_pmos m=1 w=13.000u l=130.00n ng=8 nrd=0 ++ nrs=0 +MP0 net4 A VDD VDD sg13_lv_pmos m=1 w=4.89u l=130.00n ng=3 nrd=0 nrs=0 +.ENDS +.SUBCKT RM_IHPSG13_64x32_c2_1P_COLDRV13X16 ADDR_COL_I<1> ADDR_COL_I<0> ADDR_COL_O<1> ++ ADDR_COL_O<0> ADDR_DEC_I<7> ADDR_DEC_I<6> ADDR_DEC_I<5> ADDR_DEC_I<4> ++ ADDR_DEC_I<3> ADDR_DEC_I<2> ADDR_DEC_I<1> ADDR_DEC_I<0> ADDR_DEC_O<7> ++ ADDR_DEC_O<6> ADDR_DEC_O<5> ADDR_DEC_O<4> ADDR_DEC_O<3> ADDR_DEC_O<2> ++ ADDR_DEC_O<1> ADDR_DEC_O<0> DCLK_I DCLK_O RCLK_I RCLK_O WCLK_I WCLK_O ++ VDD VSS +XI1<1> VDD VSS / RSC_IHPSG13_FILLCAP4 +XI1<0> VDD VSS / RSC_IHPSG13_FILLCAP4 +XI0<3> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI0<2> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI0<1> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI0<0> VDD VSS / RSC_IHPSG13_FILLCAP8 +XADDR_COL_DRV<1> ADDR_COL_I<1> ADDR_COL_O<1> VDD VSS / ++ RSC_IHPSG13_CBUFX16 +XADDR_COL_DRV<0> ADDR_COL_I<0> ADDR_COL_O<0> VDD VSS / ++ RSC_IHPSG13_CBUFX16 +XADDR_DEC_DRV<7> ADDR_DEC_I<7> ADDR_DEC_O<7> VDD VSS / ++ RSC_IHPSG13_CBUFX16 +XADDR_DEC_DRV<6> ADDR_DEC_I<6> ADDR_DEC_O<6> VDD VSS / ++ RSC_IHPSG13_CBUFX16 +XADDR_DEC_DRV<5> ADDR_DEC_I<5> ADDR_DEC_O<5> VDD VSS / ++ RSC_IHPSG13_CBUFX16 +XADDR_DEC_DRV<4> ADDR_DEC_I<4> ADDR_DEC_O<4> VDD VSS / ++ RSC_IHPSG13_CBUFX16 +XADDR_DEC_DRV<3> ADDR_DEC_I<3> ADDR_DEC_O<3> VDD VSS / ++ RSC_IHPSG13_CBUFX16 +XADDR_DEC_DRV<2> ADDR_DEC_I<2> ADDR_DEC_O<2> VDD VSS / ++ RSC_IHPSG13_CBUFX16 +XADDR_DEC_DRV<1> ADDR_DEC_I<1> ADDR_DEC_O<1> VDD VSS / ++ RSC_IHPSG13_CBUFX16 +XADDR_DEC_DRV<0> ADDR_DEC_I<0> ADDR_DEC_O<0> VDD VSS / ++ RSC_IHPSG13_CBUFX16 +XDCLK_DRV DCLK_I DCLK_O VDD VSS / RSC_IHPSG13_CBUFX16 +XRCLK_DRV RCLK_I RCLK_O VDD VSS / RSC_IHPSG13_CBUFX16 +XWCLK_DRV WCLK_I WCLK_O VDD VSS / RSC_IHPSG13_CBUFX16 +.ENDS +.SUBCKT RSC_IHPSG13_WLDRVX16 A Z VDD VSS +MN1 Z net6 VSS VSS sg13_lv_nmos m=1 w=1.41u l=130.00n ng=2 nrd=0 nrs=0 +MN0 net6 A VSS VSS sg13_lv_nmos m=1 w=1.8u l=130.00n ng=2 nrd=0 nrs=0 +MP1 Z net6 VDD VDD sg13_lv_pmos m=1 w=12.96u l=130.00n ng=8 nrd=0 nrs=0 +MP0 net6 A VDD VDD sg13_lv_pmos m=1 w=900.0n l=130.00n ng=1 nrd=0 nrs=0 +.ENDS +.SUBCKT RM_IHPSG13_64x32_c2_1P_WLDRV16X16 A<15> A<14> A<13> A<12> A<11> A<10> A<9> A<8> ++ A<7> A<6> A<5> A<4> A<3> A<2> A<1> A<0> Z<15> Z<14> Z<13> Z<12> Z<11> Z<10> ++ Z<9> Z<8> Z<7> Z<6> Z<5> Z<4> Z<3> Z<2> Z<1> Z<0> VDD VSS +XBUF<15> A<15> Z<15> VDD VSS / RSC_IHPSG13_WLDRVX16 +XBUF<14> A<14> Z<14> VDD VSS / RSC_IHPSG13_WLDRVX16 +XBUF<13> A<13> Z<13> VDD VSS / RSC_IHPSG13_WLDRVX16 +XBUF<12> A<12> Z<12> VDD VSS / RSC_IHPSG13_WLDRVX16 +XBUF<11> A<11> Z<11> VDD VSS / RSC_IHPSG13_WLDRVX16 +XBUF<10> A<10> Z<10> VDD VSS / RSC_IHPSG13_WLDRVX16 +XBUF<9> A<9> Z<9> VDD VSS / RSC_IHPSG13_WLDRVX16 +XBUF<8> A<8> Z<8> VDD VSS / RSC_IHPSG13_WLDRVX16 +XBUF<7> A<7> Z<7> VDD VSS / RSC_IHPSG13_WLDRVX16 +XBUF<6> A<6> Z<6> VDD VSS / RSC_IHPSG13_WLDRVX16 +XBUF<5> A<5> Z<5> VDD VSS / RSC_IHPSG13_WLDRVX16 +XBUF<4> A<4> Z<4> VDD VSS / RSC_IHPSG13_WLDRVX16 +XBUF<3> A<3> Z<3> VDD VSS / RSC_IHPSG13_WLDRVX16 +XBUF<2> A<2> Z<2> VDD VSS / RSC_IHPSG13_WLDRVX16 +XBUF<1> A<1> Z<1> VDD VSS / RSC_IHPSG13_WLDRVX16 +XBUF<0> A<0> Z<0> VDD VSS / RSC_IHPSG13_WLDRVX16 +.ENDS + + +.SUBCKT RM_IHPSG13_64x32_c2_2P_COLDRV13X4 ADDR_COL_I<1> ADDR_COL_I<0> ADDR_COL_O<1> ++ ADDR_COL_O<0> ADDR_DEC_I<7> ADDR_DEC_I<6> ADDR_DEC_I<5> ADDR_DEC_I<4> ++ ADDR_DEC_I<3> ADDR_DEC_I<2> ADDR_DEC_I<1> ADDR_DEC_I<0> ADDR_DEC_O<7> ++ ADDR_DEC_O<6> ADDR_DEC_O<5> ADDR_DEC_O<4> ADDR_DEC_O<3> ADDR_DEC_O<2> ++ ADDR_DEC_O<1> ADDR_DEC_O<0> DCLK_I DCLK_O RCLK_I RCLK_O WCLK_I WCLK_O ++ VDD VSS +XWCLK_DRV WCLK_I WCLK_O VDD VSS / RSC_IHPSG13_CBUFX4 +XRCLK_DRV RCLK_I RCLK_O VDD VSS / RSC_IHPSG13_CBUFX4 +XDCLK_DRV DCLK_I DCLK_O VDD VSS / RSC_IHPSG13_CBUFX4 +XADDR_COL_DRV<1> ADDR_COL_I<1> ADDR_COL_O<1> VDD VSS / ++ RSC_IHPSG13_CBUFX4 +XADDR_COL_DRV<0> ADDR_COL_I<0> ADDR_COL_O<0> VDD VSS / ++ RSC_IHPSG13_CBUFX4 +XADDR_DEC_DRV<7> ADDR_DEC_I<7> ADDR_DEC_O<7> VDD VSS / ++ RSC_IHPSG13_CBUFX4 +XADDR_DEC_DRV<6> ADDR_DEC_I<6> ADDR_DEC_O<6> VDD VSS / ++ RSC_IHPSG13_CBUFX4 +XADDR_DEC_DRV<5> ADDR_DEC_I<5> ADDR_DEC_O<5> VDD VSS / ++ RSC_IHPSG13_CBUFX4 +XADDR_DEC_DRV<4> ADDR_DEC_I<4> ADDR_DEC_O<4> VDD VSS / ++ RSC_IHPSG13_CBUFX4 +XADDR_DEC_DRV<3> ADDR_DEC_I<3> ADDR_DEC_O<3> VDD VSS / ++ RSC_IHPSG13_CBUFX4 +XADDR_DEC_DRV<2> ADDR_DEC_I<2> ADDR_DEC_O<2> VDD VSS / ++ RSC_IHPSG13_CBUFX4 +XADDR_DEC_DRV<1> ADDR_DEC_I<1> ADDR_DEC_O<1> VDD VSS / ++ RSC_IHPSG13_CBUFX4 +XADDR_DEC_DRV<0> ADDR_DEC_I<0> ADDR_DEC_O<0> VDD VSS / ++ RSC_IHPSG13_CBUFX4 +XI0<6> VDD VSS / RSC_IHPSG13_FILLCAP4 +XI0<5> VDD VSS / RSC_IHPSG13_FILLCAP4 +XI0<4> VDD VSS / RSC_IHPSG13_FILLCAP4 +XI0<3> VDD VSS / RSC_IHPSG13_FILLCAP4 +XI0<2> VDD VSS / RSC_IHPSG13_FILLCAP4 +XI0<1> VDD VSS / RSC_IHPSG13_FILLCAP4 +XI1 VDD VSS / RSC_IHPSG13_FILLCAP8 +.ENDS +.SUBCKT RM_IHPSG13_64x32_c2_2P_WLDRV16X4 A<15> A<14> A<13> A<12> A<11> A<10> A<9> A<8> ++ A<7> A<6> A<5> A<4> A<3> A<2> A<1> A<0> Z<15> Z<14> Z<13> Z<12> Z<11> Z<10> ++ Z<9> Z<8> Z<7> Z<6> Z<5> Z<4> Z<3> Z<2> Z<1> Z<0> VDD VSS +XBUF<15> A<15> Z<15> VDD VSS / RSC_IHPSG13_WLDRVX4 +XBUF<14> A<14> Z<14> VDD VSS / RSC_IHPSG13_WLDRVX4 +XBUF<13> A<13> Z<13> VDD VSS / RSC_IHPSG13_WLDRVX4 +XBUF<12> A<12> Z<12> VDD VSS / RSC_IHPSG13_WLDRVX4 +XBUF<11> A<11> Z<11> VDD VSS / RSC_IHPSG13_WLDRVX4 +XBUF<10> A<10> Z<10> VDD VSS / RSC_IHPSG13_WLDRVX4 +XBUF<9> A<9> Z<9> VDD VSS / RSC_IHPSG13_WLDRVX4 +XBUF<8> A<8> Z<8> VDD VSS / RSC_IHPSG13_WLDRVX4 +XBUF<7> A<7> Z<7> VDD VSS / RSC_IHPSG13_WLDRVX4 +XBUF<6> A<6> Z<6> VDD VSS / RSC_IHPSG13_WLDRVX4 +XBUF<5> A<5> Z<5> VDD VSS / RSC_IHPSG13_WLDRVX4 +XBUF<4> A<4> Z<4> VDD VSS / RSC_IHPSG13_WLDRVX4 +XBUF<3> A<3> Z<3> VDD VSS / RSC_IHPSG13_WLDRVX4 +XBUF<2> A<2> Z<2> VDD VSS / RSC_IHPSG13_WLDRVX4 +XBUF<1> A<1> Z<1> VDD VSS / RSC_IHPSG13_WLDRVX4 +XBUF<0> A<0> Z<0> VDD VSS / RSC_IHPSG13_WLDRVX4 +.ENDS +.SUBCKT RM_IHPSG13_64x32_c2_2P_ROWDEC8 ADDR_N_I<7> ADDR_N_I<6> ADDR_N_I<5> ADDR_N_I<4> ++ ADDR_N_I<3> ADDR_N_I<2> ADDR_N_I<1> ADDR_N_I<0> CS_I ECLK_I WL_O<255> ++ WL_O<254> WL_O<253> WL_O<252> WL_O<251> WL_O<250> WL_O<249> WL_O<248> ++ WL_O<247> WL_O<246> WL_O<245> WL_O<244> WL_O<243> WL_O<242> WL_O<241> ++ WL_O<240> WL_O<239> WL_O<238> WL_O<237> WL_O<236> WL_O<235> WL_O<234> ++ WL_O<233> WL_O<232> WL_O<231> WL_O<230> WL_O<229> WL_O<228> WL_O<227> ++ WL_O<226> WL_O<225> WL_O<224> WL_O<223> WL_O<222> WL_O<221> WL_O<220> ++ WL_O<219> WL_O<218> WL_O<217> WL_O<216> WL_O<215> WL_O<214> WL_O<213> ++ WL_O<212> WL_O<211> WL_O<210> WL_O<209> WL_O<208> WL_O<207> WL_O<206> ++ WL_O<205> WL_O<204> WL_O<203> WL_O<202> WL_O<201> WL_O<200> WL_O<199> ++ WL_O<198> WL_O<197> WL_O<196> WL_O<195> WL_O<194> WL_O<193> WL_O<192> ++ WL_O<191> WL_O<190> WL_O<189> WL_O<188> WL_O<187> WL_O<186> WL_O<185> ++ WL_O<184> WL_O<183> WL_O<182> WL_O<181> WL_O<180> WL_O<179> WL_O<178> ++ WL_O<177> WL_O<176> WL_O<175> WL_O<174> WL_O<173> WL_O<172> WL_O<171> ++ WL_O<170> WL_O<169> WL_O<168> WL_O<167> WL_O<166> WL_O<165> WL_O<164> ++ WL_O<163> WL_O<162> WL_O<161> WL_O<160> WL_O<159> WL_O<158> WL_O<157> ++ WL_O<156> WL_O<155> WL_O<154> WL_O<153> WL_O<152> WL_O<151> WL_O<150> ++ WL_O<149> WL_O<148> WL_O<147> WL_O<146> WL_O<145> WL_O<144> WL_O<143> ++ WL_O<142> WL_O<141> WL_O<140> WL_O<139> WL_O<138> WL_O<137> WL_O<136> ++ WL_O<135> WL_O<134> WL_O<133> WL_O<132> WL_O<131> WL_O<130> WL_O<129> ++ WL_O<128> WL_O<127> WL_O<126> WL_O<125> WL_O<124> WL_O<123> WL_O<122> ++ WL_O<121> WL_O<120> WL_O<119> WL_O<118> WL_O<117> WL_O<116> WL_O<115> ++ WL_O<114> WL_O<113> WL_O<112> WL_O<111> WL_O<110> WL_O<109> WL_O<108> ++ WL_O<107> WL_O<106> WL_O<105> WL_O<104> WL_O<103> WL_O<102> WL_O<101> ++ WL_O<100> WL_O<99> WL_O<98> WL_O<97> WL_O<96> WL_O<95> WL_O<94> WL_O<93> ++ WL_O<92> WL_O<91> WL_O<90> WL_O<89> WL_O<88> WL_O<87> WL_O<86> WL_O<85> ++ WL_O<84> WL_O<83> WL_O<82> WL_O<81> WL_O<80> WL_O<79> WL_O<78> WL_O<77> ++ WL_O<76> WL_O<75> WL_O<74> WL_O<73> WL_O<72> WL_O<71> WL_O<70> WL_O<69> ++ WL_O<68> WL_O<67> WL_O<66> WL_O<65> WL_O<64> WL_O<63> WL_O<62> WL_O<61> ++ WL_O<60> WL_O<59> WL_O<58> WL_O<57> WL_O<56> WL_O<55> WL_O<54> WL_O<53> ++ WL_O<52> WL_O<51> WL_O<50> WL_O<49> WL_O<48> WL_O<47> WL_O<46> WL_O<45> ++ WL_O<44> WL_O<43> WL_O<42> WL_O<41> WL_O<40> WL_O<39> WL_O<38> WL_O<37> ++ WL_O<36> WL_O<35> WL_O<34> WL_O<33> WL_O<32> WL_O<31> WL_O<30> WL_O<29> ++ WL_O<28> WL_O<27> WL_O<26> WL_O<25> WL_O<24> WL_O<23> WL_O<22> WL_O<21> ++ WL_O<20> WL_O<19> WL_O<18> WL_O<17> WL_O<16> WL_O<15> WL_O<14> WL_O<13> ++ WL_O<12> WL_O<11> WL_O<10> WL_O<9> WL_O<8> WL_O<7> WL_O<6> WL_O<5> WL_O<4> ++ WL_O<3> WL_O<2> WL_O<1> WL_O<0> VDD VSS +XDEC11<4> ADDR_N_I<7> ADDR_N_I<6> CS_I CS04<3> VDD VSS / ++ RM_IHPSG13_64x32_c2_2P_DEC03 +XDEC11<3> ADDR_N_I<5> ADDR_N_I<4> CS04<3> CS00<15> VDD VSS / ++ RM_IHPSG13_64x32_c2_2P_DEC03 +XDEC11<2> ADDR_N_I<5> ADDR_N_I<4> CS04<2> CS00<11> VDD VSS / ++ RM_IHPSG13_64x32_c2_2P_DEC03 +XDEC11<1> ADDR_N_I<5> ADDR_N_I<4> CS04<1> CS00<7> VDD VSS / ++ RM_IHPSG13_64x32_c2_2P_DEC03 +XDEC11<0> ADDR_N_I<5> ADDR_N_I<4> CS04<0> CS00<3> VDD VSS / ++ RM_IHPSG13_64x32_c2_2P_DEC03 +XSEL<15> ADDR_N_I<3> ADDR_N_I<2> ADDR_N_I<1> ADDR_N_I<0> CS00<15> ECLK_H<15> ++ ECLK_H<16> ECLK_B<15> ECLK_B<16> WL_O<255> WL_O<254> WL_O<253> WL_O<252> ++ WL_O<251> WL_O<250> WL_O<249> WL_O<248> WL_O<247> WL_O<246> WL_O<245> ++ WL_O<244> WL_O<243> WL_O<242> WL_O<241> WL_O<240> VDD VSS / ++ RM_IHPSG13_64x32_c2_2P_DEC04 +XSEL<14> ADDR_N_I<3> ADDR_N_I<2> ADDR_N_I<1> ADDR_N_I<0> CS00<14> ECLK_H<14> ++ ECLK_H<15> ECLK_B<14> ECLK_B<15> WL_O<239> WL_O<238> WL_O<237> WL_O<236> ++ WL_O<235> WL_O<234> WL_O<233> WL_O<232> WL_O<231> WL_O<230> WL_O<229> ++ WL_O<228> WL_O<227> WL_O<226> WL_O<225> WL_O<224> VDD VSS / ++ RM_IHPSG13_64x32_c2_2P_DEC04 +XSEL<13> ADDR_N_I<3> ADDR_N_I<2> ADDR_N_I<1> ADDR_N_I<0> CS00<13> ECLK_H<13> ++ ECLK_H<14> ECLK_B<13> ECLK_B<14> WL_O<223> WL_O<222> WL_O<221> WL_O<220> ++ WL_O<219> WL_O<218> WL_O<217> WL_O<216> WL_O<215> WL_O<214> WL_O<213> ++ WL_O<212> WL_O<211> WL_O<210> WL_O<209> WL_O<208> VDD VSS / ++ RM_IHPSG13_64x32_c2_2P_DEC04 +XSEL<12> ADDR_N_I<3> ADDR_N_I<2> ADDR_N_I<1> ADDR_N_I<0> CS00<12> ECLK_H<12> ++ ECLK_H<13> ECLK_B<12> ECLK_B<13> WL_O<207> WL_O<206> WL_O<205> WL_O<204> ++ WL_O<203> WL_O<202> WL_O<201> WL_O<200> WL_O<199> WL_O<198> WL_O<197> ++ WL_O<196> WL_O<195> WL_O<194> WL_O<193> WL_O<192> VDD VSS / ++ RM_IHPSG13_64x32_c2_2P_DEC04 +XSEL<11> ADDR_N_I<3> ADDR_N_I<2> ADDR_N_I<1> ADDR_N_I<0> CS00<11> ECLK_H<11> ++ ECLK_H<12> ECLK_B<11> ECLK_B<12> WL_O<191> WL_O<190> WL_O<189> WL_O<188> ++ WL_O<187> WL_O<186> WL_O<185> WL_O<184> WL_O<183> WL_O<182> WL_O<181> ++ WL_O<180> WL_O<179> WL_O<178> WL_O<177> WL_O<176> VDD VSS / ++ RM_IHPSG13_64x32_c2_2P_DEC04 +XSEL<10> ADDR_N_I<3> ADDR_N_I<2> ADDR_N_I<1> ADDR_N_I<0> CS00<10> ECLK_H<10> ++ ECLK_H<11> ECLK_B<10> ECLK_B<11> WL_O<175> WL_O<174> WL_O<173> WL_O<172> ++ WL_O<171> WL_O<170> WL_O<169> WL_O<168> WL_O<167> WL_O<166> WL_O<165> ++ WL_O<164> WL_O<163> WL_O<162> WL_O<161> WL_O<160> VDD VSS / ++ RM_IHPSG13_64x32_c2_2P_DEC04 +XSEL<9> ADDR_N_I<3> ADDR_N_I<2> ADDR_N_I<1> ADDR_N_I<0> CS00<9> ECLK_H<9> ++ ECLK_H<10> ECLK_B<9> ECLK_B<10> WL_O<159> WL_O<158> WL_O<157> WL_O<156> ++ WL_O<155> WL_O<154> WL_O<153> WL_O<152> WL_O<151> WL_O<150> WL_O<149> ++ WL_O<148> WL_O<147> WL_O<146> WL_O<145> WL_O<144> VDD VSS / ++ RM_IHPSG13_64x32_c2_2P_DEC04 +XSEL<8> ADDR_N_I<3> ADDR_N_I<2> ADDR_N_I<1> ADDR_N_I<0> CS00<8> ECLK_H<8> ++ ECLK_H<9> ECLK_B<8> ECLK_B<9> WL_O<143> WL_O<142> WL_O<141> WL_O<140> ++ WL_O<139> WL_O<138> WL_O<137> WL_O<136> WL_O<135> WL_O<134> WL_O<133> ++ WL_O<132> WL_O<131> WL_O<130> WL_O<129> WL_O<128> VDD VSS / ++ RM_IHPSG13_64x32_c2_2P_DEC04 +XSEL<7> ADDR_N_I<3> ADDR_N_I<2> ADDR_N_I<1> ADDR_N_I<0> CS00<7> ECLK_H<7> ++ ECLK_H<8> ECLK_B<7> ECLK_B<8> WL_O<127> WL_O<126> WL_O<125> WL_O<124> ++ WL_O<123> WL_O<122> WL_O<121> WL_O<120> WL_O<119> WL_O<118> WL_O<117> ++ WL_O<116> WL_O<115> WL_O<114> WL_O<113> WL_O<112> VDD VSS / ++ RM_IHPSG13_64x32_c2_2P_DEC04 +XSEL<6> ADDR_N_I<3> ADDR_N_I<2> ADDR_N_I<1> ADDR_N_I<0> CS00<6> ECLK_H<6> ++ ECLK_H<7> ECLK_B<6> ECLK_B<7> WL_O<111> WL_O<110> WL_O<109> WL_O<108> ++ WL_O<107> WL_O<106> WL_O<105> WL_O<104> WL_O<103> WL_O<102> WL_O<101> ++ WL_O<100> WL_O<99> WL_O<98> WL_O<97> WL_O<96> VDD VSS / ++ RM_IHPSG13_64x32_c2_2P_DEC04 +XSEL<5> ADDR_N_I<3> ADDR_N_I<2> ADDR_N_I<1> ADDR_N_I<0> CS00<5> ECLK_H<5> ++ ECLK_H<6> ECLK_B<5> ECLK_B<6> WL_O<95> WL_O<94> WL_O<93> WL_O<92> WL_O<91> ++ WL_O<90> WL_O<89> WL_O<88> WL_O<87> WL_O<86> WL_O<85> WL_O<84> WL_O<83> ++ WL_O<82> WL_O<81> WL_O<80> VDD VSS / RM_IHPSG13_64x32_c2_2P_DEC04 +XSEL<4> ADDR_N_I<3> ADDR_N_I<2> ADDR_N_I<1> ADDR_N_I<0> CS00<4> ECLK_H<4> ++ ECLK_H<5> ECLK_B<4> ECLK_B<5> WL_O<79> WL_O<78> WL_O<77> WL_O<76> WL_O<75> ++ WL_O<74> WL_O<73> WL_O<72> WL_O<71> WL_O<70> WL_O<69> WL_O<68> WL_O<67> ++ WL_O<66> WL_O<65> WL_O<64> VDD VSS / RM_IHPSG13_64x32_c2_2P_DEC04 +XSEL<3> ADDR_N_I<3> ADDR_N_I<2> ADDR_N_I<1> ADDR_N_I<0> CS00<3> ECLK_H<3> ++ ECLK_H<4> ECLK_B<3> ECLK_B<4> WL_O<63> WL_O<62> WL_O<61> WL_O<60> WL_O<59> ++ WL_O<58> WL_O<57> WL_O<56> WL_O<55> WL_O<54> WL_O<53> WL_O<52> WL_O<51> ++ WL_O<50> WL_O<49> WL_O<48> VDD VSS / RM_IHPSG13_64x32_c2_2P_DEC04 +XSEL<2> ADDR_N_I<3> ADDR_N_I<2> ADDR_N_I<1> ADDR_N_I<0> CS00<2> ECLK_H<2> ++ ECLK_H<3> ECLK_B<2> ECLK_B<3> WL_O<47> WL_O<46> WL_O<45> WL_O<44> WL_O<43> ++ WL_O<42> WL_O<41> WL_O<40> WL_O<39> WL_O<38> WL_O<37> WL_O<36> WL_O<35> ++ WL_O<34> WL_O<33> WL_O<32> VDD VSS / RM_IHPSG13_64x32_c2_2P_DEC04 +XSEL<1> ADDR_N_I<3> ADDR_N_I<2> ADDR_N_I<1> ADDR_N_I<0> CS00<1> ECLK_H<1> ++ ECLK_H<2> ECLK_B<1> ECLK_B<2> WL_O<31> WL_O<30> WL_O<29> WL_O<28> WL_O<27> ++ WL_O<26> WL_O<25> WL_O<24> WL_O<23> WL_O<22> WL_O<21> WL_O<20> WL_O<19> ++ WL_O<18> WL_O<17> WL_O<16> VDD VSS / RM_IHPSG13_64x32_c2_2P_DEC04 +XSEL<0> ADDR_N_I<3> ADDR_N_I<2> ADDR_N_I<1> ADDR_N_I<0> CS00<0> ECLK_I ++ ECLK_H<1> ECLK_B<0> ECLK_B<1> WL_O<15> WL_O<14> WL_O<13> WL_O<12> WL_O<11> ++ WL_O<10> WL_O<9> WL_O<8> WL_O<7> WL_O<6> WL_O<5> WL_O<4> WL_O<3> WL_O<2> ++ WL_O<1> WL_O<0> VDD VSS / RM_IHPSG13_64x32_c2_2P_DEC04 +XDEC10<4> ADDR_N_I<7> ADDR_N_I<6> CS_I CS04<2> VDD VSS / ++ RM_IHPSG13_64x32_c2_2P_DEC02 +XDEC10<3> ADDR_N_I<5> ADDR_N_I<4> CS04<3> CS00<14> VDD VSS / ++ RM_IHPSG13_64x32_c2_2P_DEC02 +XDEC10<2> ADDR_N_I<5> ADDR_N_I<4> CS04<2> CS00<10> VDD VSS / ++ RM_IHPSG13_64x32_c2_2P_DEC02 +XDEC10<1> ADDR_N_I<5> ADDR_N_I<4> CS04<1> CS00<6> VDD VSS / ++ RM_IHPSG13_64x32_c2_2P_DEC02 +XDEC10<0> ADDR_N_I<5> ADDR_N_I<4> CS04<0> CS00<2> VDD VSS / ++ RM_IHPSG13_64x32_c2_2P_DEC02 +XL2<132> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<131> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<130> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<129> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<128> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<127> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<126> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<125> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<124> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<123> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<122> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<121> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<120> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<119> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<118> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<117> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<116> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<115> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<114> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<113> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<112> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<111> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<110> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<109> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<108> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<107> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<106> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<105> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<104> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<103> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<102> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<101> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<100> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<99> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<98> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<97> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<96> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<95> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<94> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<93> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<92> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<91> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<90> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<89> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<88> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<87> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<86> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<85> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<84> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<83> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<82> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<81> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<80> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<79> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<78> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<77> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<76> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<75> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<74> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<73> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<72> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<71> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<70> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<69> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<68> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<67> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<66> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<65> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<64> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<63> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<62> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<61> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<60> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<59> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<58> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<57> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<56> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<55> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<54> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<53> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<52> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<51> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<50> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<49> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<48> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<47> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<46> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<45> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<44> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<43> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<42> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<41> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<40> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<39> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<38> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<37> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<36> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<35> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<34> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<33> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<32> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<31> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<30> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<29> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<28> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<27> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<26> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<25> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<24> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<23> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<22> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<21> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<20> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<19> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<18> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<17> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<16> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<15> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<14> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<13> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<12> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<11> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<10> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<9> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<8> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<7> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<6> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<5> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<4> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<3> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<2> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<1> VDD VSS / RSC_IHPSG13_FILLCAP8 +XDEC00<4> ADDR_N_I<7> ADDR_N_I<6> CS_I CS04<0> VDD VSS / ++ RM_IHPSG13_64x32_c2_2P_DEC00 +XDEC00<3> ADDR_N_I<5> ADDR_N_I<4> CS04<3> CS00<12> VDD VSS / ++ RM_IHPSG13_64x32_c2_2P_DEC00 +XDEC00<2> ADDR_N_I<5> ADDR_N_I<4> CS04<2> CS00<8> VDD VSS / ++ RM_IHPSG13_64x32_c2_2P_DEC00 +XDEC00<1> ADDR_N_I<5> ADDR_N_I<4> CS04<1> CS00<4> VDD VSS / ++ RM_IHPSG13_64x32_c2_2P_DEC00 +XDEC00<0> ADDR_N_I<5> ADDR_N_I<4> CS04<0> CS00<0> VDD VSS / ++ RM_IHPSG13_64x32_c2_2P_DEC00 +XDEC01<4> ADDR_N_I<7> ADDR_N_I<6> CS_I CS04<1> VDD VSS / ++ RM_IHPSG13_64x32_c2_2P_DEC01 +XDEC01<3> ADDR_N_I<5> ADDR_N_I<4> CS04<3> CS00<13> VDD VSS / ++ RM_IHPSG13_64x32_c2_2P_DEC01 +XDEC01<2> ADDR_N_I<5> ADDR_N_I<4> CS04<2> CS00<9> VDD VSS / ++ RM_IHPSG13_64x32_c2_2P_DEC01 +XDEC01<1> ADDR_N_I<5> ADDR_N_I<4> CS04<1> CS00<5> VDD VSS / ++ RM_IHPSG13_64x32_c2_2P_DEC01 +XDEC01<0> ADDR_N_I<5> ADDR_N_I<4> CS04<0> CS00<1> VDD VSS / ++ RM_IHPSG13_64x32_c2_2P_DEC01 +.ENDS +.SUBCKT RM_IHPSG13_64x32_c2_2P_ROWREG8 ACLK_N_I ADDR_I<7> ADDR_I<6> ADDR_I<5> ADDR_I<4> ++ ADDR_I<3> ADDR_I<2> ADDR_I<1> ADDR_I<0> ADDR_N_O<7> ADDR_N_O<6> ADDR_N_O<5> ++ ADDR_N_O<4> ADDR_N_O<3> ADDR_N_O<2> ADDR_N_O<1> ADDR_N_O<0> BIST_ADDR_I<7> ++ BIST_ADDR_I<6> BIST_ADDR_I<5> BIST_ADDR_I<4> BIST_ADDR_I<3> BIST_ADDR_I<2> ++ BIST_ADDR_I<1> BIST_ADDR_I<0> BIST_EN_I VDD VSS +XINV<7> q_int<7> qn_int<7> VDD VSS / RSC_IHPSG13_CINVX2 +XINV<6> q_int<6> qn_int<6> VDD VSS / RSC_IHPSG13_CINVX2 +XINV<5> q_int<5> qn_int<5> VDD VSS / RSC_IHPSG13_CINVX2 +XINV<4> q_int<4> qn_int<4> VDD VSS / RSC_IHPSG13_CINVX2 +XINV<3> q_int<3> qn_int<3> VDD VSS / RSC_IHPSG13_CINVX2 +XINV<2> q_int<2> qn_int<2> VDD VSS / RSC_IHPSG13_CINVX2 +XINV<1> q_int<1> qn_int<1> VDD VSS / RSC_IHPSG13_CINVX2 +XINV<0> q_int<0> qn_int<0> VDD VSS / RSC_IHPSG13_CINVX2 +XDRV<7> qn_int<7> ADDR_N_O<7> VDD VSS / RSC_IHPSG13_CINVX8 +XDRV<6> qn_int<6> ADDR_N_O<6> VDD VSS / RSC_IHPSG13_CINVX8 +XDRV<5> qn_int<5> ADDR_N_O<5> VDD VSS / RSC_IHPSG13_CINVX8 +XDRV<4> qn_int<4> ADDR_N_O<4> VDD VSS / RSC_IHPSG13_CINVX8 +XDRV<3> qn_int<3> ADDR_N_O<3> VDD VSS / RSC_IHPSG13_CINVX8 +XDRV<2> qn_int<2> ADDR_N_O<2> VDD VSS / RSC_IHPSG13_CINVX8 +XDRV<1> qn_int<1> ADDR_N_O<1> VDD VSS / RSC_IHPSG13_CINVX8 +XDRV<0> qn_int<0> ADDR_N_O<0> VDD VSS / RSC_IHPSG13_CINVX8 +XDFF<7> BIST_EN_I BIST_ADDR_I<7> ACLK_N_I ADDR_I<7> q_int<7> net2<0> VDD ++ VSS / RSC_IHPSG13_DFNQMX2IX1 +XDFF<6> BIST_EN_I BIST_ADDR_I<6> ACLK_N_I ADDR_I<6> q_int<6> net2<1> VDD ++ VSS / RSC_IHPSG13_DFNQMX2IX1 +XDFF<5> BIST_EN_I BIST_ADDR_I<5> ACLK_N_I ADDR_I<5> q_int<5> net2<2> VDD ++ VSS / RSC_IHPSG13_DFNQMX2IX1 +XDFF<4> BIST_EN_I BIST_ADDR_I<4> ACLK_N_I ADDR_I<4> q_int<4> net2<3> VDD ++ VSS / RSC_IHPSG13_DFNQMX2IX1 +XDFF<3> BIST_EN_I BIST_ADDR_I<3> ACLK_N_I ADDR_I<3> q_int<3> net2<4> VDD ++ VSS / RSC_IHPSG13_DFNQMX2IX1 +XDFF<2> BIST_EN_I BIST_ADDR_I<2> ACLK_N_I ADDR_I<2> q_int<2> net2<5> VDD ++ VSS / RSC_IHPSG13_DFNQMX2IX1 +XDFF<1> BIST_EN_I BIST_ADDR_I<1> ACLK_N_I ADDR_I<1> q_int<1> net2<6> VDD ++ VSS / RSC_IHPSG13_DFNQMX2IX1 +XDFF<0> BIST_EN_I BIST_ADDR_I<0> ACLK_N_I ADDR_I<0> q_int<0> net2<7> VDD ++ VSS / RSC_IHPSG13_DFNQMX2IX1 +XI11<4> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI11<3> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI11<2> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI11<1> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI10 VDD VSS / RSC_IHPSG13_FILLCAP4 +.ENDS +.SUBCKT RM_IHPSG13_64x32_c2_2P_COLDEC4 ACLK_N ADDR<3> ADDR<2> ADDR<1> ADDR<0> ++ ADDR_COL<1> ADDR_COL<0> ADDR_DEC<7> ADDR_DEC<6> ADDR_DEC<5> ADDR_DEC<4> ++ ADDR_DEC<3> ADDR_DEC<2> ADDR_DEC<1> ADDR_DEC<0> BIST_ADDR<3> BIST_ADDR<2> ++ BIST_ADDR<1> BIST_ADDR<0> BIST_EN_I VDD VSS +XI1<7> PADR<0> PADR<1> PADR<2> addr_n<7> VDD VSS / RSC_IHPSG13_NAND3X2 +XI1<6> NADR<0> PADR<1> PADR<2> addr_n<6> VDD VSS / RSC_IHPSG13_NAND3X2 +XI1<5> PADR<0> NADR<1> PADR<2> addr_n<5> VDD VSS / RSC_IHPSG13_NAND3X2 +XI1<4> NADR<0> NADR<1> PADR<2> addr_n<4> VDD VSS / RSC_IHPSG13_NAND3X2 +XI1<3> PADR<0> PADR<1> NADR<2> addr_n<3> VDD VSS / RSC_IHPSG13_NAND3X2 +XI1<2> NADR<0> PADR<1> NADR<2> addr_n<2> VDD VSS / RSC_IHPSG13_NAND3X2 +XI1<1> PADR<0> NADR<1> NADR<2> addr_n<1> VDD VSS / RSC_IHPSG13_NAND3X2 +XI1<0> NADR<0> NADR<1> NADR<2> addr_n<0> VDD VSS / RSC_IHPSG13_NAND3X2 +XDFF<3> BIST_EN_I BIST_ADDR<3> ACLK_N ADDR<3> addr_int net12<0> VDD ++ VSS / RSC_IHPSG13_DFNQMX2IX1 +XDFF<2> BIST_EN_I BIST_ADDR<2> ACLK_N ADDR<2> padr_int<2> net12<1> VDD ++ VSS / RSC_IHPSG13_DFNQMX2IX1 +XDFF<1> BIST_EN_I BIST_ADDR<1> ACLK_N ADDR<1> padr_int<1> net12<2> VDD ++ VSS / RSC_IHPSG13_DFNQMX2IX1 +XDFF<0> BIST_EN_I BIST_ADDR<0> ACLK_N ADDR<0> padr_int<0> net12<3> VDD ++ VSS / RSC_IHPSG13_DFNQMX2IX1 +XI17<4> VDD VSS / RSC_IHPSG13_FILLCAP4 +XI17<3> VDD VSS / RSC_IHPSG13_FILLCAP4 +XI17<2> VDD VSS / RSC_IHPSG13_FILLCAP4 +XI17<1> VDD VSS / RSC_IHPSG13_FILLCAP4 +XI13<2> NADR<2> PADR<2> VDD VSS / RSC_IHPSG13_INVX2 +XI13<1> NADR<1> PADR<1> VDD VSS / RSC_IHPSG13_INVX2 +XI13<0> NADR<0> PADR<0> VDD VSS / RSC_IHPSG13_INVX2 +XI2<7> addr_n<7> ADDR_DEC<7> VDD VSS / RSC_IHPSG13_INVX2 +XI2<6> addr_n<6> ADDR_DEC<6> VDD VSS / RSC_IHPSG13_INVX2 +XI2<5> addr_n<5> ADDR_DEC<5> VDD VSS / RSC_IHPSG13_INVX2 +XI2<4> addr_n<4> ADDR_DEC<4> VDD VSS / RSC_IHPSG13_INVX2 +XI2<3> addr_n<3> ADDR_DEC<3> VDD VSS / RSC_IHPSG13_INVX2 +XI2<2> addr_n<2> ADDR_DEC<2> VDD VSS / RSC_IHPSG13_INVX2 +XI2<1> addr_n<1> ADDR_DEC<1> VDD VSS / RSC_IHPSG13_INVX2 +XI2<0> addr_n<0> ADDR_DEC<0> VDD VSS / RSC_IHPSG13_INVX2 +XI3<2> padr_int<2> NADR<2> VDD VSS / RSC_IHPSG13_INVX2 +XI3<1> padr_int<1> NADR<1> VDD VSS / RSC_IHPSG13_INVX2 +XI3<0> padr_int<0> NADR<0> VDD VSS / RSC_IHPSG13_INVX2 +XI14 addr_int ADDR_COL<0> VDD VSS / RSC_IHPSG13_CBUFX2 +XI16<8> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI16<7> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI16<6> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI16<5> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI16<4> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI16<3> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI16<2> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI16<1> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI15 ADDR_COL<1> VDD VSS / RSC_IHPSG13_TIEL +.ENDS +.SUBCKT RM_IHPSG13_64x32_c2_2P_COLCTRL4 A_ADDR_COL A_ADDR_DEC<7> A_ADDR_DEC<6> ++ A_ADDR_DEC<5> A_ADDR_DEC<4> A_ADDR_DEC<3> A_ADDR_DEC<2> A_ADDR_DEC<1> ++ A_ADDR_DEC<0> A_BIST_BM_I A_BIST_DW_I A_BIST_EN_I A_BLC<15> A_BLC<14> ++ A_BLC<13> A_BLC<12> A_BLC<11> A_BLC<10> A_BLC<9> A_BLC<8> A_BLC<7> A_BLC<6> ++ A_BLC<5> A_BLC<4> A_BLC<3> A_BLC<2> A_BLC<1> A_BLC<0> A_BLT<15> A_BLT<14> ++ A_BLT<13> A_BLT<12> A_BLT<11> A_BLT<10> A_BLT<9> A_BLT<8> A_BLT<7> A_BLT<6> ++ A_BLT<5> A_BLT<4> A_BLT<3> A_BLT<2> A_BLT<1> A_BLT<0> A_BM_I A_DCLK_B_L ++ A_DCLK_B_R A_DCLK_L A_DCLK_R A_DR_O A_DW_I A_RCLK_B_L A_RCLK_B_R A_RCLK_L ++ A_RCLK_R A_TIEH_O A_WCLK_B_L A_WCLK_B_R A_WCLK_L A_WCLK_R B_ADDR_COL ++ B_ADDR_DEC<7> B_ADDR_DEC<6> B_ADDR_DEC<5> B_ADDR_DEC<4> B_ADDR_DEC<3> ++ B_ADDR_DEC<2> B_ADDR_DEC<1> B_ADDR_DEC<0> B_BIST_BM_I B_BIST_DW_I ++ B_BIST_EN_I B_BLC<15> B_BLC<14> B_BLC<13> B_BLC<12> B_BLC<11> B_BLC<10> ++ B_BLC<9> B_BLC<8> B_BLC<7> B_BLC<6> B_BLC<5> B_BLC<4> B_BLC<3> B_BLC<2> ++ B_BLC<1> B_BLC<0> B_BLT<15> B_BLT<14> B_BLT<13> B_BLT<12> B_BLT<11> ++ B_BLT<10> B_BLT<9> B_BLT<8> B_BLT<7> B_BLT<6> B_BLT<5> B_BLT<4> B_BLT<3> ++ B_BLT<2> B_BLT<1> B_BLT<0> B_BM_I B_DCLK_B_L B_DCLK_B_R B_DCLK_L B_DCLK_R ++ B_DR_O B_DW_I B_RCLK_B_L B_RCLK_B_R B_RCLK_L B_RCLK_R B_TIEH_O B_WCLK_B_L ++ B_WCLK_B_R B_WCLK_L B_WCLK_R VDD VSS +XB_I80 B_RCLK_B_L B_WCLK_B_L net041 VDD VSS / RSC_IHPSG13_AND2X2 +XA_I80 A_RCLK_B_L A_WCLK_B_L net21 VDD VSS / RSC_IHPSG13_AND2X2 +XB_I76 B_DI_N B_DO_WRITE_P B_WR_ZERO VDD VSS / RSC_IHPSG13_AND2X4 +XB_I75 B_DI_R B_DO_WRITE_P B_WR_ONE VDD VSS / RSC_IHPSG13_AND2X4 +XA_I76 A_DI_N A_DO_WRITE_P A_WR_ZERO VDD VSS / RSC_IHPSG13_AND2X4 +XA_I75 A_DI_R A_DO_WRITE_P A_WR_ONE VDD VSS / RSC_IHPSG13_AND2X4 +XI_FILL4<26> VDD VSS / RSC_IHPSG13_FILLCAP4 +XI_FILL4<25> VDD VSS / RSC_IHPSG13_FILLCAP4 +XI_FILL4<24> VDD VSS / RSC_IHPSG13_FILLCAP4 +XI_FILL4<23> VDD VSS / RSC_IHPSG13_FILLCAP4 +XI_FILL4<22> VDD VSS / RSC_IHPSG13_FILLCAP4 +XI_FILL4<21> VDD VSS / RSC_IHPSG13_FILLCAP4 +XI_FILL4<20> VDD VSS / RSC_IHPSG13_FILLCAP4 +XI_FILL4<19> VDD VSS / RSC_IHPSG13_FILLCAP4 +XI_FILL4<18> VDD VSS / RSC_IHPSG13_FILLCAP4 +XI_FILL4<17> VDD VSS / RSC_IHPSG13_FILLCAP4 +XI_FILL4<16> VDD VSS / RSC_IHPSG13_FILLCAP4 +XI_FILL4<15> VDD VSS / RSC_IHPSG13_FILLCAP4 +XI_FILL4<14> VDD VSS / RSC_IHPSG13_FILLCAP4 +XI_FILL4<13> VDD VSS / RSC_IHPSG13_FILLCAP4 +XI_FILL4<12> VDD VSS / RSC_IHPSG13_FILLCAP4 +XI_FILL4<11> VDD VSS / RSC_IHPSG13_FILLCAP4 +XI_FILL4<10> VDD VSS / RSC_IHPSG13_FILLCAP4 +XI_FILL4<9> VDD VSS / RSC_IHPSG13_FILLCAP4 +XI_FILL4<8> VDD VSS / RSC_IHPSG13_FILLCAP4 +XI_FILL4<7> VDD VSS / RSC_IHPSG13_FILLCAP4 +XI_FILL4<6> VDD VSS / RSC_IHPSG13_FILLCAP4 +XI_FILL4<5> VDD VSS / RSC_IHPSG13_FILLCAP4 +XI_FILL4<4> VDD VSS / RSC_IHPSG13_FILLCAP4 +XI_FILL4<3> VDD VSS / RSC_IHPSG13_FILLCAP4 +XI_FILL4<2> VDD VSS / RSC_IHPSG13_FILLCAP4 +XI_FILL4<1> VDD VSS / RSC_IHPSG13_FILLCAP4 +XB_I69 B_DCLK_L B_DCLK_B_L VDD VSS / RSC_IHPSG13_CINVX4 +XB_I50 B_WCLK_L B_WCLK_B_L VDD VSS / RSC_IHPSG13_CINVX4 +XB_EBUF B_RCLK_L B_RCLK_B_L VDD VSS / RSC_IHPSG13_CINVX4 +XB_INV<1> B_N0 B_P0 VDD VSS / RSC_IHPSG13_CINVX4 +XB_INV<0> B_ADDR_COL B_N0 VDD VSS / RSC_IHPSG13_CINVX4 +XA_I69 A_DCLK_L A_DCLK_B_L VDD VSS / RSC_IHPSG13_CINVX4 +XA_I50 A_WCLK_L A_WCLK_B_L VDD VSS / RSC_IHPSG13_CINVX4 +XA_EBUF A_RCLK_L A_RCLK_B_L VDD VSS / RSC_IHPSG13_CINVX4 +XA_INV<1> A_N0 A_P0 VDD VSS / RSC_IHPSG13_CINVX4 +XA_INV<0> A_ADDR_COL A_N0 VDD VSS / RSC_IHPSG13_CINVX4 +XB_I81<1> net041 B_PRE_N VDD VSS / RSC_IHPSG13_CINVX4_WN +XB_I81<0> net041 B_PRE_N VDD VSS / RSC_IHPSG13_CINVX4_WN +XA_I81<1> net21 A_PRE_N VDD VSS / RSC_IHPSG13_CINVX4_WN +XA_I81<0> net21 A_PRE_N VDD VSS / RSC_IHPSG13_CINVX4_WN +XA_R2 A_RCLK_L A_RCLK_R / RSC_IHPSG13_MET3RES +XA_I87 A_WCLK_L A_WCLK_R / RSC_IHPSG13_MET3RES +XA_I88 A_DCLK_L A_DCLK_R / RSC_IHPSG13_MET3RES +XA_I89 A_DCLK_B_L A_DCLK_B_R / RSC_IHPSG13_MET3RES +XA_I90 A_WCLK_B_L A_WCLK_B_R / RSC_IHPSG13_MET3RES +XA_I91 A_RCLK_B_L A_RCLK_B_R / RSC_IHPSG13_MET3RES +XB_R2 B_RCLK_L B_RCLK_R / RSC_IHPSG13_MET3RES +XB_I87 B_WCLK_L B_WCLK_R / RSC_IHPSG13_MET3RES +XB_I88 B_DCLK_L B_DCLK_R / RSC_IHPSG13_MET3RES +XB_I89 B_DCLK_B_L B_DCLK_B_R / RSC_IHPSG13_MET3RES +XB_I90 B_WCLK_B_L B_WCLK_B_R / RSC_IHPSG13_MET3RES +XB_I91 B_RCLK_B_L B_RCLK_B_R / RSC_IHPSG13_MET3RES +XA_ISENSE A_SAE A_BLC_SEL A_BLT_SEL net19 net20 VDD VSS / ++ RSC_IHPSG13_DFPQD_MSAFFX2 +XB_ISENSE B_SAE B_BLC_SEL B_BLT_SEL net037 net038 VDD VSS / ++ RSC_IHPSG13_DFPQD_MSAFFX2 +XAB_BLMUX<3> A_BLC<15> A_BLC<14> A_BLC<13> A_BLC<12> A_BLC_SEL A_BLT<15> ++ A_BLT<14> A_BLT<13> A_BLT<12> A_BLT_SEL A_PRE_N A_SEL_P<15> A_SEL_P<14> ++ A_SEL_P<13> A_SEL_P<12> A_WR_ONE A_WR_ZERO B_BLC<15> B_BLC<14> B_BLC<13> ++ B_BLC<12> B_BLC_SEL B_BLT<15> B_BLT<14> B_BLT<13> B_BLT<12> B_BLT_SEL ++ B_PRE_N B_SEL_P<15> B_SEL_P<14> B_SEL_P<13> B_SEL_P<12> B_WR_ONE B_WR_ZERO ++ VDD VSS / RM_IHPSG13_64x32_c2_2P_BLDRV +XAB_BLMUX<2> A_BLC<11> A_BLC<10> A_BLC<9> A_BLC<8> A_BLC_SEL A_BLT<11> ++ A_BLT<10> A_BLT<9> A_BLT<8> A_BLT_SEL A_PRE_N A_SEL_P<11> A_SEL_P<10> ++ A_SEL_P<9> A_SEL_P<8> A_WR_ONE A_WR_ZERO B_BLC<11> B_BLC<10> B_BLC<9> ++ B_BLC<8> B_BLC_SEL B_BLT<11> B_BLT<10> B_BLT<9> B_BLT<8> B_BLT_SEL B_PRE_N ++ B_SEL_P<11> B_SEL_P<10> B_SEL_P<9> B_SEL_P<8> B_WR_ONE B_WR_ZERO VDD ++ VSS / RM_IHPSG13_64x32_c2_2P_BLDRV +XAB_BLMUX<1> A_BLC<7> A_BLC<6> A_BLC<5> A_BLC<4> A_BLC_SEL A_BLT<7> A_BLT<6> ++ A_BLT<5> A_BLT<4> A_BLT_SEL A_PRE_N A_SEL_P<7> A_SEL_P<6> A_SEL_P<5> ++ A_SEL_P<4> A_WR_ONE A_WR_ZERO B_BLC<7> B_BLC<6> B_BLC<5> B_BLC<4> B_BLC_SEL ++ B_BLT<7> B_BLT<6> B_BLT<5> B_BLT<4> B_BLT_SEL B_PRE_N B_SEL_P<7> B_SEL_P<6> ++ B_SEL_P<5> B_SEL_P<4> B_WR_ONE B_WR_ZERO VDD VSS / ++ RM_IHPSG13_64x32_c2_2P_BLDRV +XAB_BLMUX<0> A_BLC<3> A_BLC<2> A_BLC<1> A_BLC<0> A_BLC_SEL A_BLT<3> A_BLT<2> ++ A_BLT<1> A_BLT<0> A_BLT_SEL A_PRE_N A_SEL_P<3> A_SEL_P<2> A_SEL_P<1> ++ A_SEL_P<0> A_WR_ONE A_WR_ZERO B_BLC<3> B_BLC<2> B_BLC<1> B_BLC<0> B_BLC_SEL ++ B_BLT<3> B_BLT<2> B_BLT<1> B_BLT<0> B_BLT_SEL B_PRE_N B_SEL_P<3> B_SEL_P<2> ++ B_SEL_P<1> B_SEL_P<0> B_WR_ONE B_WR_ZERO VDD VSS / ++ RM_IHPSG13_64x32_c2_2P_BLDRV +XA_I51 net19 A_DR_O VDD VSS / RSC_IHPSG13_INVX4 +XB_I51 net037 B_DR_O VDD VSS / RSC_IHPSG13_INVX4 +XA_I78 A_RCLK_B_L A_SAE VDD VSS / RSC_IHPSG13_CBUFX2 +XB_I78 B_RCLK_B_L B_SAE VDD VSS / RSC_IHPSG13_CBUFX2 +XA_DREG A_BIST_EN_I A_BIST_DW_I A_DCLK_B_L A_DW_I A_DI_R net22 VDD VSS ++ / RSC_IHPSG13_DFNQMX2IX1 +XB_DREG B_BIST_EN_I B_BIST_DW_I B_DCLK_B_L B_DW_I B_DI_R net046 VDD ++ VSS / RSC_IHPSG13_DFNQMX2IX1 +XB_BREG B_BIST_EN_I B_BIST_BM_I B_DCLK_B_L B_BM_I B_BM_R net045 VDD ++ VSS / RSC_IHPSG13_DFNQMX2IX1 +XA_BREG A_BIST_EN_I A_BIST_BM_I A_DCLK_B_L A_BM_I A_BM_R net24 VDD VSS ++ / RSC_IHPSG13_DFNQMX2IX1 +XA_DEC3INV<15> net23<0> A_SEL_P<15> VDD VSS / RSC_IHPSG13_INVX2 +XA_DEC3INV<14> net23<1> A_SEL_P<14> VDD VSS / RSC_IHPSG13_INVX2 +XA_DEC3INV<13> net23<2> A_SEL_P<13> VDD VSS / RSC_IHPSG13_INVX2 +XA_DEC3INV<12> net23<3> A_SEL_P<12> VDD VSS / RSC_IHPSG13_INVX2 +XA_DEC3INV<11> net23<4> A_SEL_P<11> VDD VSS / RSC_IHPSG13_INVX2 +XA_DEC3INV<10> net23<5> A_SEL_P<10> VDD VSS / RSC_IHPSG13_INVX2 +XA_DEC3INV<9> net23<6> A_SEL_P<9> VDD VSS / RSC_IHPSG13_INVX2 +XA_DEC3INV<8> net23<7> A_SEL_P<8> VDD VSS / RSC_IHPSG13_INVX2 +XA_DEC3INV<7> net23<8> A_SEL_P<7> VDD VSS / RSC_IHPSG13_INVX2 +XA_DEC3INV<6> net23<9> A_SEL_P<6> VDD VSS / RSC_IHPSG13_INVX2 +XA_DEC3INV<5> net23<10> A_SEL_P<5> VDD VSS / RSC_IHPSG13_INVX2 +XA_DEC3INV<4> net23<11> A_SEL_P<4> VDD VSS / RSC_IHPSG13_INVX2 +XA_DEC3INV<3> net23<12> A_SEL_P<3> VDD VSS / RSC_IHPSG13_INVX2 +XA_DEC3INV<2> net23<13> A_SEL_P<2> VDD VSS / RSC_IHPSG13_INVX2 +XA_DEC3INV<1> net23<14> A_SEL_P<1> VDD VSS / RSC_IHPSG13_INVX2 +XA_DEC3INV<0> net23<15> A_SEL_P<0> VDD VSS / RSC_IHPSG13_INVX2 +XA_I83 A_BM_R A_BM_N VDD VSS / RSC_IHPSG13_INVX2 +XA_I49 A_DI_R A_DI_N VDD VSS / RSC_IHPSG13_INVX2 +XB_DEC3INV<15> net044<0> B_SEL_P<15> VDD VSS / RSC_IHPSG13_INVX2 +XB_DEC3INV<14> net044<1> B_SEL_P<14> VDD VSS / RSC_IHPSG13_INVX2 +XB_DEC3INV<13> net044<2> B_SEL_P<13> VDD VSS / RSC_IHPSG13_INVX2 +XB_DEC3INV<12> net044<3> B_SEL_P<12> VDD VSS / RSC_IHPSG13_INVX2 +XB_DEC3INV<11> net044<4> B_SEL_P<11> VDD VSS / RSC_IHPSG13_INVX2 +XB_DEC3INV<10> net044<5> B_SEL_P<10> VDD VSS / RSC_IHPSG13_INVX2 +XB_DEC3INV<9> net044<6> B_SEL_P<9> VDD VSS / RSC_IHPSG13_INVX2 +XB_DEC3INV<8> net044<7> B_SEL_P<8> VDD VSS / RSC_IHPSG13_INVX2 +XB_DEC3INV<7> net044<8> B_SEL_P<7> VDD VSS / RSC_IHPSG13_INVX2 +XB_DEC3INV<6> net044<9> B_SEL_P<6> VDD VSS / RSC_IHPSG13_INVX2 +XB_DEC3INV<5> net044<10> B_SEL_P<5> VDD VSS / RSC_IHPSG13_INVX2 +XB_DEC3INV<4> net044<11> B_SEL_P<4> VDD VSS / RSC_IHPSG13_INVX2 +XB_DEC3INV<3> net044<12> B_SEL_P<3> VDD VSS / RSC_IHPSG13_INVX2 +XB_DEC3INV<2> net044<13> B_SEL_P<2> VDD VSS / RSC_IHPSG13_INVX2 +XB_DEC3INV<1> net044<14> B_SEL_P<1> VDD VSS / RSC_IHPSG13_INVX2 +XB_DEC3INV<0> net044<15> B_SEL_P<0> VDD VSS / RSC_IHPSG13_INVX2 +XB_I83 B_BM_R B_BM_N VDD VSS / RSC_IHPSG13_INVX2 +XB_I49 B_DI_R B_DI_N VDD VSS / RSC_IHPSG13_INVX2 +XI_FILL8<20> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI_FILL8<19> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI_FILL8<18> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI_FILL8<17> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI_FILL8<16> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI_FILL8<15> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI_FILL8<14> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI_FILL8<13> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI_FILL8<12> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI_FILL8<11> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI_FILL8<10> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI_FILL8<9> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI_FILL8<8> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI_FILL8<7> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI_FILL8<6> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI_FILL8<5> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI_FILL8<4> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI_FILL8<3> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI_FILL8<2> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI_FILL8<1> VDD VSS / RSC_IHPSG13_FILLCAP8 +XA_I44 A_BM_N A_WCLK_B_L A_DO_WRITE_P VDD VSS / RSC_IHPSG13_NOR2X2 +XB_I44 B_BM_N B_WCLK_B_L B_DO_WRITE_P VDD VSS / RSC_IHPSG13_NOR2X2 +XA_DEC3<15> A_P0 A_ADDR_DEC<7> net23<0> VDD VSS / RSC_IHPSG13_NAND2X2 +XA_DEC3<14> A_P0 A_ADDR_DEC<6> net23<1> VDD VSS / RSC_IHPSG13_NAND2X2 +XA_DEC3<13> A_P0 A_ADDR_DEC<5> net23<2> VDD VSS / RSC_IHPSG13_NAND2X2 +XA_DEC3<12> A_P0 A_ADDR_DEC<4> net23<3> VDD VSS / RSC_IHPSG13_NAND2X2 +XA_DEC3<11> A_P0 A_ADDR_DEC<3> net23<4> VDD VSS / RSC_IHPSG13_NAND2X2 +XA_DEC3<10> A_P0 A_ADDR_DEC<2> net23<5> VDD VSS / RSC_IHPSG13_NAND2X2 +XA_DEC3<9> A_P0 A_ADDR_DEC<1> net23<6> VDD VSS / RSC_IHPSG13_NAND2X2 +XA_DEC3<8> A_P0 A_ADDR_DEC<0> net23<7> VDD VSS / RSC_IHPSG13_NAND2X2 +XA_DEC3<7> A_N0 A_ADDR_DEC<7> net23<8> VDD VSS / RSC_IHPSG13_NAND2X2 +XA_DEC3<6> A_N0 A_ADDR_DEC<6> net23<9> VDD VSS / RSC_IHPSG13_NAND2X2 +XA_DEC3<5> A_N0 A_ADDR_DEC<5> net23<10> VDD VSS / RSC_IHPSG13_NAND2X2 +XA_DEC3<4> A_N0 A_ADDR_DEC<4> net23<11> VDD VSS / RSC_IHPSG13_NAND2X2 +XA_DEC3<3> A_N0 A_ADDR_DEC<3> net23<12> VDD VSS / RSC_IHPSG13_NAND2X2 +XA_DEC3<2> A_N0 A_ADDR_DEC<2> net23<13> VDD VSS / RSC_IHPSG13_NAND2X2 +XA_DEC3<1> A_N0 A_ADDR_DEC<1> net23<14> VDD VSS / RSC_IHPSG13_NAND2X2 +XA_DEC3<0> A_N0 A_ADDR_DEC<0> net23<15> VDD VSS / RSC_IHPSG13_NAND2X2 +XB_DEC3<15> B_P0 B_ADDR_DEC<7> net044<0> VDD VSS / RSC_IHPSG13_NAND2X2 +XB_DEC3<14> B_P0 B_ADDR_DEC<6> net044<1> VDD VSS / RSC_IHPSG13_NAND2X2 +XB_DEC3<13> B_P0 B_ADDR_DEC<5> net044<2> VDD VSS / RSC_IHPSG13_NAND2X2 +XB_DEC3<12> B_P0 B_ADDR_DEC<4> net044<3> VDD VSS / RSC_IHPSG13_NAND2X2 +XB_DEC3<11> B_P0 B_ADDR_DEC<3> net044<4> VDD VSS / RSC_IHPSG13_NAND2X2 +XB_DEC3<10> B_P0 B_ADDR_DEC<2> net044<5> VDD VSS / RSC_IHPSG13_NAND2X2 +XB_DEC3<9> B_P0 B_ADDR_DEC<1> net044<6> VDD VSS / RSC_IHPSG13_NAND2X2 +XB_DEC3<8> B_P0 B_ADDR_DEC<0> net044<7> VDD VSS / RSC_IHPSG13_NAND2X2 +XB_DEC3<7> B_N0 B_ADDR_DEC<7> net044<8> VDD VSS / RSC_IHPSG13_NAND2X2 +XB_DEC3<6> B_N0 B_ADDR_DEC<6> net044<9> VDD VSS / RSC_IHPSG13_NAND2X2 +XB_DEC3<5> B_N0 B_ADDR_DEC<5> net044<10> VDD VSS / RSC_IHPSG13_NAND2X2 +XB_DEC3<4> B_N0 B_ADDR_DEC<4> net044<11> VDD VSS / RSC_IHPSG13_NAND2X2 +XB_DEC3<3> B_N0 B_ADDR_DEC<3> net044<12> VDD VSS / RSC_IHPSG13_NAND2X2 +XB_DEC3<2> B_N0 B_ADDR_DEC<2> net044<13> VDD VSS / RSC_IHPSG13_NAND2X2 +XB_DEC3<1> B_N0 B_ADDR_DEC<1> net044<14> VDD VSS / RSC_IHPSG13_NAND2X2 +XB_DEC3<0> B_N0 B_ADDR_DEC<0> net044<15> VDD VSS / RSC_IHPSG13_NAND2X2 +XB_BM_TIEH B_TIEH_O VDD VSS / RSC_IHPSG13_TIEH +XA_BM_TIEH A_TIEH_O VDD VSS / RSC_IHPSG13_TIEH +.ENDS + + +.SUBCKT RM_IHPSG13_64x32_c2_2P_ROWDEC5 ADDR_N_I<4> ADDR_N_I<3> ADDR_N_I<2> ADDR_N_I<1> ++ ADDR_N_I<0> CS_I ECLK_I WL_O<31> WL_O<30> WL_O<29> WL_O<28> WL_O<27> ++ WL_O<26> WL_O<25> WL_O<24> WL_O<23> WL_O<22> WL_O<21> WL_O<20> WL_O<19> ++ WL_O<18> WL_O<17> WL_O<16> WL_O<15> WL_O<14> WL_O<13> WL_O<12> WL_O<11> ++ WL_O<10> WL_O<9> WL_O<8> WL_O<7> WL_O<6> WL_O<5> WL_O<4> WL_O<3> WL_O<2> ++ WL_O<1> WL_O<0> VDD VSS +XDEC00 ADDR_N_I<5> ADDR_N_I<4> CS_I CS00<0> VDD VSS / ++ RM_IHPSG13_64x32_c2_2P_DEC00 +XSEL<1> ADDR_N_I<3> ADDR_N_I<2> ADDR_N_I<1> ADDR_N_I<0> CS00<1> ECLK_H<1> ++ ECLK_H<2> ECLK_B<1> ECLK_B<2> WL_O<31> WL_O<30> WL_O<29> WL_O<28> WL_O<27> ++ WL_O<26> WL_O<25> WL_O<24> WL_O<23> WL_O<22> WL_O<21> WL_O<20> WL_O<19> ++ WL_O<18> WL_O<17> WL_O<16> VDD VSS / RM_IHPSG13_64x32_c2_2P_DEC04 +XSEL<0> ADDR_N_I<3> ADDR_N_I<2> ADDR_N_I<1> ADDR_N_I<0> CS00<0> ECLK_I ++ ECLK_H<1> ECLK_B<0> ECLK_B<1> WL_O<15> WL_O<14> WL_O<13> WL_O<12> WL_O<11> ++ WL_O<10> WL_O<9> WL_O<8> WL_O<7> WL_O<6> WL_O<5> WL_O<4> WL_O<3> WL_O<2> ++ WL_O<1> WL_O<0> VDD VSS / RM_IHPSG13_64x32_c2_2P_DEC04 +XDEC01 ADDR_N_I<5> ADDR_N_I<4> CS_I CS00<1> VDD VSS / ++ RM_IHPSG13_64x32_c2_2P_DEC01 +XL2<18> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<17> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<16> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<15> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<14> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<13> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<12> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<11> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<10> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<9> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<8> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<7> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<6> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<5> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<4> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<3> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<2> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<1> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI0 ADDR_N_I<5> VDD VSS / RSC_IHPSG13_TIEL +.ENDS +.SUBCKT RM_IHPSG13_64x32_c2_2P_ROWREG5 ACLK_N_I ADDR_I<4> ADDR_I<3> ADDR_I<2> ADDR_I<1> ++ ADDR_I<0> ADDR_N_O<4> ADDR_N_O<3> ADDR_N_O<2> ADDR_N_O<1> ADDR_N_O<0> ++ BIST_ADDR_I<4> BIST_ADDR_I<3> BIST_ADDR_I<2> BIST_ADDR_I<1> BIST_ADDR_I<0> ++ BIST_EN_I VDD VSS +XINV<4> q_int<4> qn_int<4> VDD VSS / RSC_IHPSG13_CINVX2 +XINV<3> q_int<3> qn_int<3> VDD VSS / RSC_IHPSG13_CINVX2 +XINV<2> q_int<2> qn_int<2> VDD VSS / RSC_IHPSG13_CINVX2 +XINV<1> q_int<1> qn_int<1> VDD VSS / RSC_IHPSG13_CINVX2 +XINV<0> q_int<0> qn_int<0> VDD VSS / RSC_IHPSG13_CINVX2 +XDRV<4> qn_int<4> ADDR_N_O<4> VDD VSS / RSC_IHPSG13_CINVX8 +XDRV<3> qn_int<3> ADDR_N_O<3> VDD VSS / RSC_IHPSG13_CINVX8 +XDRV<2> qn_int<2> ADDR_N_O<2> VDD VSS / RSC_IHPSG13_CINVX8 +XDRV<1> qn_int<1> ADDR_N_O<1> VDD VSS / RSC_IHPSG13_CINVX8 +XDRV<0> qn_int<0> ADDR_N_O<0> VDD VSS / RSC_IHPSG13_CINVX8 +XDFF<4> BIST_EN_I BIST_ADDR_I<4> ACLK_N_I ADDR_I<4> q_int<4> net2<0> VDD ++ VSS / RSC_IHPSG13_DFNQMX2IX1 +XDFF<3> BIST_EN_I BIST_ADDR_I<3> ACLK_N_I ADDR_I<3> q_int<3> net2<1> VDD ++ VSS / RSC_IHPSG13_DFNQMX2IX1 +XDFF<2> BIST_EN_I BIST_ADDR_I<2> ACLK_N_I ADDR_I<2> q_int<2> net2<2> VDD ++ VSS / RSC_IHPSG13_DFNQMX2IX1 +XDFF<1> BIST_EN_I BIST_ADDR_I<1> ACLK_N_I ADDR_I<1> q_int<1> net2<3> VDD ++ VSS / RSC_IHPSG13_DFNQMX2IX1 +XDFF<0> BIST_EN_I BIST_ADDR_I<0> ACLK_N_I ADDR_I<0> q_int<0> net2<4> VDD ++ VSS / RSC_IHPSG13_DFNQMX2IX1 +XI11<16> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI11<15> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI11<14> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI11<13> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI11<12> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI11<11> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI11<10> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI11<9> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI11<8> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI11<7> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI11<6> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI11<5> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI11<4> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI11<3> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI11<2> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI11<1> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI12<3> VDD VSS / RSC_IHPSG13_FILLCAP4 +XI12<2> VDD VSS / RSC_IHPSG13_FILLCAP4 +XI12<1> VDD VSS / RSC_IHPSG13_FILLCAP4 +XI12<0> VDD VSS / RSC_IHPSG13_FILLCAP4 +.ENDS + + +.SUBCKT RM_IHPSG13_64x32_c2_2P_COLDEC3 ACLK_N ADDR<2> ADDR<1> ADDR<0> ADDR_COL<1> ++ ADDR_COL<0> ADDR_DEC<7> ADDR_DEC<6> ADDR_DEC<5> ADDR_DEC<4> ADDR_DEC<3> ++ ADDR_DEC<2> ADDR_DEC<1> ADDR_DEC<0> BIST_ADDR<2> BIST_ADDR<1> BIST_ADDR<0> ++ BIST_EN_I VDD VSS +XI1<7> PADR<0> PADR<1> PADR<2> addr_n<7> VDD VSS / RSC_IHPSG13_NAND3X2 +XI1<6> NADR<0> PADR<1> PADR<2> addr_n<6> VDD VSS / RSC_IHPSG13_NAND3X2 +XI1<5> PADR<0> NADR<1> PADR<2> addr_n<5> VDD VSS / RSC_IHPSG13_NAND3X2 +XI1<4> NADR<0> NADR<1> PADR<2> addr_n<4> VDD VSS / RSC_IHPSG13_NAND3X2 +XI1<3> PADR<0> PADR<1> NADR<2> addr_n<3> VDD VSS / RSC_IHPSG13_NAND3X2 +XI1<2> NADR<0> PADR<1> NADR<2> addr_n<2> VDD VSS / RSC_IHPSG13_NAND3X2 +XI1<1> PADR<0> NADR<1> NADR<2> addr_n<1> VDD VSS / RSC_IHPSG13_NAND3X2 +XI1<0> NADR<0> NADR<1> NADR<2> addr_n<0> VDD VSS / RSC_IHPSG13_NAND3X2 +XDFF<2> BIST_EN_I BIST_ADDR<2> ACLK_N ADDR<2> padr_int<2> net13<0> VDD ++ VSS / RSC_IHPSG13_DFNQMX2IX1 +XDFF<1> BIST_EN_I BIST_ADDR<1> ACLK_N ADDR<1> padr_int<1> net13<1> VDD ++ VSS / RSC_IHPSG13_DFNQMX2IX1 +XDFF<0> BIST_EN_I BIST_ADDR<0> ACLK_N ADDR<0> padr_int<0> net13<2> VDD ++ VSS / RSC_IHPSG13_DFNQMX2IX1 +XI15<1> ADDR_COL<1> VDD VSS / RSC_IHPSG13_TIEL +XI15<0> ADDR_COL<0> VDD VSS / RSC_IHPSG13_TIEL +XI13<2> NADR<2> PADR<2> VDD VSS / RSC_IHPSG13_INVX2 +XI13<1> NADR<1> PADR<1> VDD VSS / RSC_IHPSG13_INVX2 +XI13<0> NADR<0> PADR<0> VDD VSS / RSC_IHPSG13_INVX2 +XI3<2> padr_int<2> NADR<2> VDD VSS / RSC_IHPSG13_INVX2 +XI3<1> padr_int<1> NADR<1> VDD VSS / RSC_IHPSG13_INVX2 +XI3<0> padr_int<0> NADR<0> VDD VSS / RSC_IHPSG13_INVX2 +XI2<7> addr_n<7> ADDR_DEC<7> VDD VSS / RSC_IHPSG13_INVX2 +XI2<6> addr_n<6> ADDR_DEC<6> VDD VSS / RSC_IHPSG13_INVX2 +XI2<5> addr_n<5> ADDR_DEC<5> VDD VSS / RSC_IHPSG13_INVX2 +XI2<4> addr_n<4> ADDR_DEC<4> VDD VSS / RSC_IHPSG13_INVX2 +XI2<3> addr_n<3> ADDR_DEC<3> VDD VSS / RSC_IHPSG13_INVX2 +XI2<2> addr_n<2> ADDR_DEC<2> VDD VSS / RSC_IHPSG13_INVX2 +XI2<1> addr_n<1> ADDR_DEC<1> VDD VSS / RSC_IHPSG13_INVX2 +XI2<0> addr_n<0> ADDR_DEC<0> VDD VSS / RSC_IHPSG13_INVX2 +XI17<4> VDD VSS / RSC_IHPSG13_FILLCAP4 +XI17<3> VDD VSS / RSC_IHPSG13_FILLCAP4 +XI17<2> VDD VSS / RSC_IHPSG13_FILLCAP4 +XI17<1> VDD VSS / RSC_IHPSG13_FILLCAP4 +XI16<11> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI16<10> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI16<9> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI16<8> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI16<7> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI16<6> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI16<5> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI16<4> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI16<3> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI16<2> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI16<1> VDD VSS / RSC_IHPSG13_FILLCAP8 +.ENDS +.SUBCKT RSC_IHPSG13_DFPQD_MSAFFX2P CP DN DP QN QP VDD VSS +XI_AMP CP DN DP QN QP VDD VSS / RSC_IHPSG13_DFPQD_MSAFFX2 +.ENDS +.SUBCKT RM_IHPSG13_64x32_c2_2P_COLCTRL3 A_ADDR_DEC<7> A_ADDR_DEC<6> A_ADDR_DEC<5> ++ A_ADDR_DEC<4> A_ADDR_DEC<3> A_ADDR_DEC<2> A_ADDR_DEC<1> A_ADDR_DEC<0> ++ A_BIST_BM_I A_BIST_DW_I A_BIST_EN_I A_BLC<7> A_BLC<6> A_BLC<5> A_BLC<4> ++ A_BLC<3> A_BLC<2> A_BLC<1> A_BLC<0> A_BLT<7> A_BLT<6> A_BLT<5> A_BLT<4> ++ A_BLT<3> A_BLT<2> A_BLT<1> A_BLT<0> A_BM_I A_DCLK_B_L A_DCLK_B_R A_DCLK_L ++ A_DCLK_R A_DR_O A_DW_I A_RCLK_B_L A_RCLK_B_R A_RCLK_L A_RCLK_R A_TIEH_O ++ A_WCLK_B_L A_WCLK_B_R A_WCLK_L A_WCLK_R B_ADDR_DEC<7> B_ADDR_DEC<6> ++ B_ADDR_DEC<5> B_ADDR_DEC<4> B_ADDR_DEC<3> B_ADDR_DEC<2> B_ADDR_DEC<1> ++ B_ADDR_DEC<0> B_BIST_BM_I B_BIST_DW_I B_BIST_EN_I B_BLC<7> B_BLC<6> B_BLC<5> ++ B_BLC<4> B_BLC<3> B_BLC<2> B_BLC<1> B_BLC<0> B_BLT<7> B_BLT<6> B_BLT<5> ++ B_BLT<4> B_BLT<3> B_BLT<2> B_BLT<1> B_BLT<0> B_BM_I B_DCLK_B_L B_DCLK_B_R ++ B_DCLK_L B_DCLK_R B_DR_O B_DW_I B_RCLK_B_L B_RCLK_B_R B_RCLK_L B_RCLK_R ++ B_TIEH_O B_WCLK_B_L B_WCLK_B_R B_WCLK_L B_WCLK_R VDD VSS +XB_DREG B_BIST_EN_I B_BIST_DW_I B_DCLK_B_L B_DW_I B_DI_R net044 VDD ++ VSS / RSC_IHPSG13_DFNQMX2IX1 +XB_BREG B_BIST_EN_I B_BIST_BM_I B_DCLK_B_L B_BM_I B_BM_R net043 VDD ++ VSS / RSC_IHPSG13_DFNQMX2IX1 +XA_DREG A_BIST_EN_I A_BIST_DW_I A_DCLK_B_L A_DW_I A_DI_R net22 VDD VSS ++ / RSC_IHPSG13_DFNQMX2IX1 +XA_BREG A_BIST_EN_I A_BIST_BM_I A_DCLK_B_L A_BM_I A_BM_R net23 VDD VSS ++ / RSC_IHPSG13_DFNQMX2IX1 +XI_FILL8<11> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI_FILL8<10> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI_FILL8<9> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI_FILL8<8> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI_FILL8<7> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI_FILL8<6> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI_FILL8<5> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI_FILL8<4> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI_FILL8<3> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI_FILL8<2> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI_FILL8<1> VDD VSS / RSC_IHPSG13_FILLCAP8 +XB_I51 net037 B_DR_O VDD VSS / RSC_IHPSG13_INVX4 +XA_I51 net19 A_DR_O VDD VSS / RSC_IHPSG13_INVX4 +XB_I44 B_BM_N B_WCLK_B_L B_DO_WRITE_P VDD VSS / RSC_IHPSG13_NOR2X2 +XA_I44 A_BM_N A_WCLK_B_L A_DO_WRITE_P VDD VSS / RSC_IHPSG13_NOR2X2 +XB_BM_TIEH B_TIEH_O VDD VSS / RSC_IHPSG13_TIEH +XA_BM_TIEH A_TIEH_O VDD VSS / RSC_IHPSG13_TIEH +XB_ISENSE B_SAE B_BLC_SEL B_BLT_SEL net037 net038 VDD VSS / ++ RSC_IHPSG13_DFPQD_MSAFFX2P +XA_ISENSE A_SAE A_BLC_SEL A_BLT_SEL net19 net20 VDD VSS / ++ RSC_IHPSG13_DFPQD_MSAFFX2P +XB_I49 B_DI_R B_DI_N VDD VSS / RSC_IHPSG13_INVX2 +XB_I83 B_BM_R B_BM_N VDD VSS / RSC_IHPSG13_INVX2 +XA_I49 A_DI_R A_DI_N VDD VSS / RSC_IHPSG13_INVX2 +XA_I83 A_BM_R A_BM_N VDD VSS / RSC_IHPSG13_INVX2 +XB_I69 B_DCLK_L B_DCLK_B_L VDD VSS / RSC_IHPSG13_CINVX2 +XB_I50 B_WCLK_L B_WCLK_B_L VDD VSS / RSC_IHPSG13_CINVX2 +XB_EBUF B_RCLK_L B_RCLK_B_L VDD VSS / RSC_IHPSG13_CINVX2 +XA_I69 A_DCLK_L A_DCLK_B_L VDD VSS / RSC_IHPSG13_CINVX2 +XA_I50 A_WCLK_L A_WCLK_B_L VDD VSS / RSC_IHPSG13_CINVX2 +XA_EBUF A_RCLK_L A_RCLK_B_L VDD VSS / RSC_IHPSG13_CINVX2 +XAB_BLMUX<1> A_BLC<7> A_BLC<6> A_BLC<5> A_BLC<4> A_BLC_SEL A_BLT<7> A_BLT<6> ++ A_BLT<5> A_BLT<4> A_BLT_SEL A_PRE_N A_ADDR_DEC<7> A_ADDR_DEC<6> ++ A_ADDR_DEC<5> A_ADDR_DEC<4> A_WR_ONE A_WR_ZERO B_BLC<7> B_BLC<6> B_BLC<5> ++ B_BLC<4> B_BLC_SEL B_BLT<7> B_BLT<6> B_BLT<5> B_BLT<4> B_BLT_SEL B_PRE_N ++ B_ADDR_DEC<7> B_ADDR_DEC<6> B_ADDR_DEC<5> B_ADDR_DEC<4> B_WR_ONE B_WR_ZERO ++ VDD VSS / RM_IHPSG13_64x32_c2_2P_BLDRV +XAB_BLMUX<0> A_BLC<3> A_BLC<2> A_BLC<1> A_BLC<0> A_BLC_SEL A_BLT<3> A_BLT<2> ++ A_BLT<1> A_BLT<0> A_BLT_SEL A_PRE_N A_ADDR_DEC<3> A_ADDR_DEC<2> ++ A_ADDR_DEC<1> A_ADDR_DEC<0> A_WR_ONE A_WR_ZERO B_BLC<3> B_BLC<2> B_BLC<1> ++ B_BLC<0> B_BLC_SEL B_BLT<3> B_BLT<2> B_BLT<1> B_BLT<0> B_BLT_SEL B_PRE_N ++ B_ADDR_DEC<3> B_ADDR_DEC<2> B_ADDR_DEC<1> B_ADDR_DEC<0> B_WR_ONE B_WR_ZERO ++ VDD VSS / RM_IHPSG13_64x32_c2_2P_BLDRV +XB_I78 B_RCLK_B_L B_SAE VDD VSS / RSC_IHPSG13_CBUFX2 +XA_I78 A_RCLK_B_L A_SAE VDD VSS / RSC_IHPSG13_CBUFX2 +XB_I88 B_DCLK_L B_DCLK_R / RSC_IHPSG13_MET3RES +XB_I87 B_WCLK_L B_WCLK_R / RSC_IHPSG13_MET3RES +XB_R2 B_RCLK_L B_RCLK_R / RSC_IHPSG13_MET3RES +XB_I91 B_RCLK_B_L B_RCLK_B_R / RSC_IHPSG13_MET3RES +XB_I90 B_WCLK_B_L B_WCLK_B_R / RSC_IHPSG13_MET3RES +XB_I89 B_DCLK_B_L B_DCLK_B_R / RSC_IHPSG13_MET3RES +XA_I88 A_DCLK_L A_DCLK_R / RSC_IHPSG13_MET3RES +XA_I87 A_WCLK_L A_WCLK_R / RSC_IHPSG13_MET3RES +XA_R2 A_RCLK_L A_RCLK_R / RSC_IHPSG13_MET3RES +XA_I91 A_RCLK_B_L A_RCLK_B_R / RSC_IHPSG13_MET3RES +XA_I90 A_WCLK_B_L A_WCLK_B_R / RSC_IHPSG13_MET3RES +XA_I89 A_DCLK_B_L A_DCLK_B_R / RSC_IHPSG13_MET3RES +XB_I80 B_WCLK_B_L B_RCLK_B_L net041 VDD VSS / RSC_IHPSG13_AND2X2 +XB_I76 B_DO_WRITE_P B_DI_N B_WR_ZERO VDD VSS / RSC_IHPSG13_AND2X2 +XB_I75 B_DO_WRITE_P B_DI_R B_WR_ONE VDD VSS / RSC_IHPSG13_AND2X2 +XA_I80 A_WCLK_B_L A_RCLK_B_L net21 VDD VSS / RSC_IHPSG13_AND2X2 +XA_I76 A_DI_N A_DO_WRITE_P A_WR_ZERO VDD VSS / RSC_IHPSG13_AND2X2 +XA_I75 A_DI_R A_DO_WRITE_P A_WR_ONE VDD VSS / RSC_IHPSG13_AND2X2 +XB_I81 net041 B_PRE_N VDD VSS / RSC_IHPSG13_CINVX4_WN +XA_I81 net21 A_PRE_N VDD VSS / RSC_IHPSG13_CINVX4_WN +XI_FILL4<10> VDD VSS / RSC_IHPSG13_FILLCAP4 +XI_FILL4<9> VDD VSS / RSC_IHPSG13_FILLCAP4 +XI_FILL4<8> VDD VSS / RSC_IHPSG13_FILLCAP4 +XI_FILL4<7> VDD VSS / RSC_IHPSG13_FILLCAP4 +XI_FILL4<6> VDD VSS / RSC_IHPSG13_FILLCAP4 +XI_FILL4<5> VDD VSS / RSC_IHPSG13_FILLCAP4 +XI_FILL4<4> VDD VSS / RSC_IHPSG13_FILLCAP4 +XI_FILL4<3> VDD VSS / RSC_IHPSG13_FILLCAP4 +XI_FILL4<2> VDD VSS / RSC_IHPSG13_FILLCAP4 +XI_FILL4<1> VDD VSS / RSC_IHPSG13_FILLCAP4 +.ENDS + +.SUBCKT RM_IHPSG13_64x32_c2_2P_ROWDEC6 ADDR_N_I<5> ADDR_N_I<4> ADDR_N_I<3> ADDR_N_I<2> ++ ADDR_N_I<1> ADDR_N_I<0> CS_I ECLK_I WL_O<63> WL_O<62> WL_O<61> WL_O<60> ++ WL_O<59> WL_O<58> WL_O<57> WL_O<56> WL_O<55> WL_O<54> WL_O<53> WL_O<52> ++ WL_O<51> WL_O<50> WL_O<49> WL_O<48> WL_O<47> WL_O<46> WL_O<45> WL_O<44> ++ WL_O<43> WL_O<42> WL_O<41> WL_O<40> WL_O<39> WL_O<38> WL_O<37> WL_O<36> ++ WL_O<35> WL_O<34> WL_O<33> WL_O<32> WL_O<31> WL_O<30> WL_O<29> WL_O<28> ++ WL_O<27> WL_O<26> WL_O<25> WL_O<24> WL_O<23> WL_O<22> WL_O<21> WL_O<20> ++ WL_O<19> WL_O<18> WL_O<17> WL_O<16> WL_O<15> WL_O<14> WL_O<13> WL_O<12> ++ WL_O<11> WL_O<10> WL_O<9> WL_O<8> WL_O<7> WL_O<6> WL_O<5> WL_O<4> WL_O<3> ++ WL_O<2> WL_O<1> WL_O<0> VDD VSS +XDEC10 ADDR_N_I<5> ADDR_N_I<4> CS_I CS00<2> VDD VSS / ++ RM_IHPSG13_64x32_c2_2P_DEC02 +XDEC00 ADDR_N_I<5> ADDR_N_I<4> CS_I CS00<0> VDD VSS / ++ RM_IHPSG13_64x32_c2_2P_DEC00 +XSEL<3> ADDR_N_I<3> ADDR_N_I<2> ADDR_N_I<1> ADDR_N_I<0> CS00<3> ECLK_H<3> ++ ECLK_H<4> ECLK_B<3> ECLK_B<4> WL_O<63> WL_O<62> WL_O<61> WL_O<60> WL_O<59> ++ WL_O<58> WL_O<57> WL_O<56> WL_O<55> WL_O<54> WL_O<53> WL_O<52> WL_O<51> ++ WL_O<50> WL_O<49> WL_O<48> VDD VSS / RM_IHPSG13_64x32_c2_2P_DEC04 +XSEL<2> ADDR_N_I<3> ADDR_N_I<2> ADDR_N_I<1> ADDR_N_I<0> CS00<2> ECLK_H<2> ++ ECLK_H<3> ECLK_B<2> ECLK_B<3> WL_O<47> WL_O<46> WL_O<45> WL_O<44> WL_O<43> ++ WL_O<42> WL_O<41> WL_O<40> WL_O<39> WL_O<38> WL_O<37> WL_O<36> WL_O<35> ++ WL_O<34> WL_O<33> WL_O<32> VDD VSS / RM_IHPSG13_64x32_c2_2P_DEC04 +XSEL<1> ADDR_N_I<3> ADDR_N_I<2> ADDR_N_I<1> ADDR_N_I<0> CS00<1> ECLK_H<1> ++ ECLK_H<2> ECLK_B<1> ECLK_B<2> WL_O<31> WL_O<30> WL_O<29> WL_O<28> WL_O<27> ++ WL_O<26> WL_O<25> WL_O<24> WL_O<23> WL_O<22> WL_O<21> WL_O<20> WL_O<19> ++ WL_O<18> WL_O<17> WL_O<16> VDD VSS / RM_IHPSG13_64x32_c2_2P_DEC04 +XSEL<0> ADDR_N_I<3> ADDR_N_I<2> ADDR_N_I<1> ADDR_N_I<0> CS00<0> ECLK_I ++ ECLK_H<1> ECLK_B<0> ECLK_B<1> WL_O<15> WL_O<14> WL_O<13> WL_O<12> WL_O<11> ++ WL_O<10> WL_O<9> WL_O<8> WL_O<7> WL_O<6> WL_O<5> WL_O<4> WL_O<3> WL_O<2> ++ WL_O<1> WL_O<0> VDD VSS / RM_IHPSG13_64x32_c2_2P_DEC04 +XDEC11 ADDR_N_I<5> ADDR_N_I<4> CS_I CS00<3> VDD VSS / ++ RM_IHPSG13_64x32_c2_2P_DEC03 +XL2<36> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<35> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<34> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<33> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<32> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<31> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<30> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<29> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<28> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<27> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<26> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<25> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<24> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<23> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<22> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<21> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<20> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<19> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<18> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<17> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<16> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<15> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<14> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<13> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<12> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<11> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<10> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<9> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<8> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<7> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<6> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<5> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<4> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<3> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<2> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<1> VDD VSS / RSC_IHPSG13_FILLCAP8 +XDEC01 ADDR_N_I<5> ADDR_N_I<4> CS_I CS00<1> VDD VSS / ++ RM_IHPSG13_64x32_c2_2P_DEC01 +.ENDS +.SUBCKT RM_IHPSG13_64x32_c2_2P_ROWREG6 ACLK_N_I ADDR_I<5> ADDR_I<4> ADDR_I<3> ADDR_I<2> ++ ADDR_I<1> ADDR_I<0> ADDR_N_O<5> ADDR_N_O<4> ADDR_N_O<3> ADDR_N_O<2> ++ ADDR_N_O<1> ADDR_N_O<0> BIST_ADDR_I<5> BIST_ADDR_I<4> BIST_ADDR_I<3> ++ BIST_ADDR_I<2> BIST_ADDR_I<1> BIST_ADDR_I<0> BIST_EN_I VDD VSS +XINV<5> q_int<5> qn_int<5> VDD VSS / RSC_IHPSG13_CINVX2 +XINV<4> q_int<4> qn_int<4> VDD VSS / RSC_IHPSG13_CINVX2 +XINV<3> q_int<3> qn_int<3> VDD VSS / RSC_IHPSG13_CINVX2 +XINV<2> q_int<2> qn_int<2> VDD VSS / RSC_IHPSG13_CINVX2 +XINV<1> q_int<1> qn_int<1> VDD VSS / RSC_IHPSG13_CINVX2 +XINV<0> q_int<0> qn_int<0> VDD VSS / RSC_IHPSG13_CINVX2 +XDRV<5> qn_int<5> ADDR_N_O<5> VDD VSS / RSC_IHPSG13_CINVX8 +XDRV<4> qn_int<4> ADDR_N_O<4> VDD VSS / RSC_IHPSG13_CINVX8 +XDRV<3> qn_int<3> ADDR_N_O<3> VDD VSS / RSC_IHPSG13_CINVX8 +XDRV<2> qn_int<2> ADDR_N_O<2> VDD VSS / RSC_IHPSG13_CINVX8 +XDRV<1> qn_int<1> ADDR_N_O<1> VDD VSS / RSC_IHPSG13_CINVX8 +XDRV<0> qn_int<0> ADDR_N_O<0> VDD VSS / RSC_IHPSG13_CINVX8 +XDFF<5> BIST_EN_I BIST_ADDR_I<5> ACLK_N_I ADDR_I<5> q_int<5> net2<0> VDD ++ VSS / RSC_IHPSG13_DFNQMX2IX1 +XDFF<4> BIST_EN_I BIST_ADDR_I<4> ACLK_N_I ADDR_I<4> q_int<4> net2<1> VDD ++ VSS / RSC_IHPSG13_DFNQMX2IX1 +XDFF<3> BIST_EN_I BIST_ADDR_I<3> ACLK_N_I ADDR_I<3> q_int<3> net2<2> VDD ++ VSS / RSC_IHPSG13_DFNQMX2IX1 +XDFF<2> BIST_EN_I BIST_ADDR_I<2> ACLK_N_I ADDR_I<2> q_int<2> net2<3> VDD ++ VSS / RSC_IHPSG13_DFNQMX2IX1 +XDFF<1> BIST_EN_I BIST_ADDR_I<1> ACLK_N_I ADDR_I<1> q_int<1> net2<4> VDD ++ VSS / RSC_IHPSG13_DFNQMX2IX1 +XDFF<0> BIST_EN_I BIST_ADDR_I<0> ACLK_N_I ADDR_I<0> q_int<0> net2<5> VDD ++ VSS / RSC_IHPSG13_DFNQMX2IX1 +XI11<12> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI11<11> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI11<10> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI11<9> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI11<8> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI11<7> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI11<6> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI11<5> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI11<4> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI11<3> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI11<2> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI11<1> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI12<2> VDD VSS / RSC_IHPSG13_FILLCAP4 +XI12<1> VDD VSS / RSC_IHPSG13_FILLCAP4 +XI12<0> VDD VSS / RSC_IHPSG13_FILLCAP4 +.ENDS + +.SUBCKT RM_IHPSG13_64x32_c2_2P_COLDRV13X16 ADDR_COL_I<1> ADDR_COL_I<0> ADDR_COL_O<1> ++ ADDR_COL_O<0> ADDR_DEC_I<7> ADDR_DEC_I<6> ADDR_DEC_I<5> ADDR_DEC_I<4> ++ ADDR_DEC_I<3> ADDR_DEC_I<2> ADDR_DEC_I<1> ADDR_DEC_I<0> ADDR_DEC_O<7> ++ ADDR_DEC_O<6> ADDR_DEC_O<5> ADDR_DEC_O<4> ADDR_DEC_O<3> ADDR_DEC_O<2> ++ ADDR_DEC_O<1> ADDR_DEC_O<0> DCLK_I DCLK_O RCLK_I RCLK_O WCLK_I WCLK_O ++ VDD VSS +XI0<7> VDD VSS / RSC_IHPSG13_FILLCAP4 +XI0<6> VDD VSS / RSC_IHPSG13_FILLCAP4 +XI0<5> VDD VSS / RSC_IHPSG13_FILLCAP4 +XI0<4> VDD VSS / RSC_IHPSG13_FILLCAP4 +XI0<3> VDD VSS / RSC_IHPSG13_FILLCAP4 +XI0<2> VDD VSS / RSC_IHPSG13_FILLCAP4 +XI0<1> VDD VSS / RSC_IHPSG13_FILLCAP4 +XWCLK_DRV WCLK_I WCLK_O VDD VSS / RSC_IHPSG13_CBUFX16 +XRCLK_DRV RCLK_I RCLK_O VDD VSS / RSC_IHPSG13_CBUFX16 +XDCLK_DRV DCLK_I DCLK_O VDD VSS / RSC_IHPSG13_CBUFX16 +XADDR_COL_DRV<1> ADDR_COL_I<1> ADDR_COL_O<1> VDD VSS / ++ RSC_IHPSG13_CBUFX16 +XADDR_COL_DRV<0> ADDR_COL_I<0> ADDR_COL_O<0> VDD VSS / ++ RSC_IHPSG13_CBUFX16 +XADDR_DEC_DRV<7> ADDR_DEC_I<7> ADDR_DEC_O<7> VDD VSS / ++ RSC_IHPSG13_CBUFX16 +XADDR_DEC_DRV<6> ADDR_DEC_I<6> ADDR_DEC_O<6> VDD VSS / ++ RSC_IHPSG13_CBUFX16 +XADDR_DEC_DRV<5> ADDR_DEC_I<5> ADDR_DEC_O<5> VDD VSS / ++ RSC_IHPSG13_CBUFX16 +XADDR_DEC_DRV<4> ADDR_DEC_I<4> ADDR_DEC_O<4> VDD VSS / ++ RSC_IHPSG13_CBUFX16 +XADDR_DEC_DRV<3> ADDR_DEC_I<3> ADDR_DEC_O<3> VDD VSS / ++ RSC_IHPSG13_CBUFX16 +XADDR_DEC_DRV<2> ADDR_DEC_I<2> ADDR_DEC_O<2> VDD VSS / ++ RSC_IHPSG13_CBUFX16 +XADDR_DEC_DRV<1> ADDR_DEC_I<1> ADDR_DEC_O<1> VDD VSS / ++ RSC_IHPSG13_CBUFX16 +XADDR_DEC_DRV<0> ADDR_DEC_I<0> ADDR_DEC_O<0> VDD VSS / ++ RSC_IHPSG13_CBUFX16 +XI1<5> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI1<4> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI1<3> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI1<2> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI1<1> VDD VSS / RSC_IHPSG13_FILLCAP8 +.ENDS +.SUBCKT RM_IHPSG13_64x32_c2_2P_WLDRV16X16 A<15> A<14> A<13> A<12> A<11> A<10> A<9> A<8> ++ A<7> A<6> A<5> A<4> A<3> A<2> A<1> A<0> Z<15> Z<14> Z<13> Z<12> Z<11> Z<10> ++ Z<9> Z<8> Z<7> Z<6> Z<5> Z<4> Z<3> Z<2> Z<1> Z<0> VDD VSS +XBUF<15> A<15> Z<15> VDD VSS / RSC_IHPSG13_WLDRVX16 +XBUF<14> A<14> Z<14> VDD VSS / RSC_IHPSG13_WLDRVX16 +XBUF<13> A<13> Z<13> VDD VSS / RSC_IHPSG13_WLDRVX16 +XBUF<12> A<12> Z<12> VDD VSS / RSC_IHPSG13_WLDRVX16 +XBUF<11> A<11> Z<11> VDD VSS / RSC_IHPSG13_WLDRVX16 +XBUF<10> A<10> Z<10> VDD VSS / RSC_IHPSG13_WLDRVX16 +XBUF<9> A<9> Z<9> VDD VSS / RSC_IHPSG13_WLDRVX16 +XBUF<8> A<8> Z<8> VDD VSS / RSC_IHPSG13_WLDRVX16 +XBUF<7> A<7> Z<7> VDD VSS / RSC_IHPSG13_WLDRVX16 +XBUF<6> A<6> Z<6> VDD VSS / RSC_IHPSG13_WLDRVX16 +XBUF<5> A<5> Z<5> VDD VSS / RSC_IHPSG13_WLDRVX16 +XBUF<4> A<4> Z<4> VDD VSS / RSC_IHPSG13_WLDRVX16 +XBUF<3> A<3> Z<3> VDD VSS / RSC_IHPSG13_WLDRVX16 +XBUF<2> A<2> Z<2> VDD VSS / RSC_IHPSG13_WLDRVX16 +XBUF<1> A<1> Z<1> VDD VSS / RSC_IHPSG13_WLDRVX16 +XBUF<0> A<0> Z<0> VDD VSS / RSC_IHPSG13_WLDRVX16 +.ENDS + + +.SUBCKT RM_IHPSG13_64x32_c2_1P_DEC01 ADDR<1> ADDR<0> CS CS_OUT VDD VSS +XDECINV net1 CS_OUT VDD VSS / RSC_IHPSG13_INVX4 +XDEC NADDR<1> ADDR<0> CS net1 VDD VSS / RSC_IHPSG13_NAND3X2 +XI2 VDD VSS / RSC_IHPSG13_FILLCAP4 +XADDRINV ADDR<1> NADDR<1> VDD VSS / RSC_IHPSG13_INVX2 +.ENDS +.SUBCKT RM_IHPSG13_64x32_c2_1P_DEC00 ADDR<1> ADDR<0> CS CS_OUT VDD VSS +XDECINV net1 CS_OUT VDD VSS / RSC_IHPSG13_INVX4 +XDEC NADDR<1> NADDR<0> CS net1 VDD VSS / RSC_IHPSG13_NAND3X2 +XADDRINV<1> ADDR<1> NADDR<1> VDD VSS / RSC_IHPSG13_INVX2 +XADDRINV<0> ADDR<0> NADDR<0> VDD VSS / RSC_IHPSG13_INVX2 +XI1 VDD VSS / RSC_IHPSG13_FILLCAP4 +.ENDS +.SUBCKT RM_IHPSG13_64x32_c2_1P_ROWDEC5 ADDR_N_I<4> ADDR_N_I<3> ADDR_N_I<2> ADDR_N_I<1> ++ ADDR_N_I<0> CS_I ECLK_I WL_O<31> WL_O<30> WL_O<29> WL_O<28> WL_O<27> ++ WL_O<26> WL_O<25> WL_O<24> WL_O<23> WL_O<22> WL_O<21> WL_O<20> WL_O<19> ++ WL_O<18> WL_O<17> WL_O<16> WL_O<15> WL_O<14> WL_O<13> WL_O<12> WL_O<11> ++ WL_O<10> WL_O<9> WL_O<8> WL_O<7> WL_O<6> WL_O<5> WL_O<4> WL_O<3> WL_O<2> ++ WL_O<1> WL_O<0> VDD VSS +XL2<12> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<11> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<10> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<9> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<8> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<7> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<6> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<5> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<4> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<3> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<2> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<1> VDD VSS / RSC_IHPSG13_FILLCAP8 +XDEC01 ADDR_N_I<5> ADDR_N_I<4> CS_I CS00<1> VDD VSS / ++ RM_IHPSG13_64x32_c2_1P_DEC01 +XDEC00 ADDR_N_I<5> ADDR_N_I<4> CS_I CS00<0> VDD VSS / ++ RM_IHPSG13_64x32_c2_1P_DEC00 +XSEL<1> ADDR_N_I<3> ADDR_N_I<2> ADDR_N_I<1> ADDR_N_I<0> CS00<1> ECLK_H<1> ++ ECLK_H<2> ECLK_B<1> ECLK_B<2> WL_O<31> WL_O<30> WL_O<29> WL_O<28> WL_O<27> ++ WL_O<26> WL_O<25> WL_O<24> WL_O<23> WL_O<22> WL_O<21> WL_O<20> WL_O<19> ++ WL_O<18> WL_O<17> WL_O<16> VDD VSS / RM_IHPSG13_64x32_c2_1P_DEC04 +XSEL<0> ADDR_N_I<3> ADDR_N_I<2> ADDR_N_I<1> ADDR_N_I<0> CS00<0> ECLK_I ++ ECLK_H<1> ECLK_B<0> ECLK_B<1> WL_O<15> WL_O<14> WL_O<13> WL_O<12> WL_O<11> ++ WL_O<10> WL_O<9> WL_O<8> WL_O<7> WL_O<6> WL_O<5> WL_O<4> WL_O<3> WL_O<2> ++ WL_O<1> WL_O<0> VDD VSS / RM_IHPSG13_64x32_c2_1P_DEC04 +XI0 ADDR_N_I<5> VDD VSS / RSC_IHPSG13_TIEL +.ENDS +.SUBCKT RM_IHPSG13_64x32_c2_1P_ROWREG5 ACLK_N_I ADDR_I<4> ADDR_I<3> ADDR_I<2> ADDR_I<1> ++ ADDR_I<0> ADDR_N_O<4> ADDR_N_O<3> ADDR_N_O<2> ADDR_N_O<1> ADDR_N_O<0> ++ BIST_ADDR_I<4> BIST_ADDR_I<3> BIST_ADDR_I<2> BIST_ADDR_I<1> BIST_ADDR_I<0> ++ BIST_EN_I VDD VSS +XINV<4> q_int<4> qn_int<4> VDD VSS / RSC_IHPSG13_CINVX2 +XINV<3> q_int<3> qn_int<3> VDD VSS / RSC_IHPSG13_CINVX2 +XINV<2> q_int<2> qn_int<2> VDD VSS / RSC_IHPSG13_CINVX2 +XINV<1> q_int<1> qn_int<1> VDD VSS / RSC_IHPSG13_CINVX2 +XINV<0> q_int<0> qn_int<0> VDD VSS / RSC_IHPSG13_CINVX2 +XDRV<4> qn_int<4> ADDR_N_O<4> VDD VSS / RSC_IHPSG13_CINVX8 +XDRV<3> qn_int<3> ADDR_N_O<3> VDD VSS / RSC_IHPSG13_CINVX8 +XDRV<2> qn_int<2> ADDR_N_O<2> VDD VSS / RSC_IHPSG13_CINVX8 +XDRV<1> qn_int<1> ADDR_N_O<1> VDD VSS / RSC_IHPSG13_CINVX8 +XDRV<0> qn_int<0> ADDR_N_O<0> VDD VSS / RSC_IHPSG13_CINVX8 +XDFF<4> BIST_EN_I BIST_ADDR_I<4> ACLK_N_I ADDR_I<4> q_int<4> net2<0> VDD ++ VSS / RSC_IHPSG13_DFNQMX2IX1 +XDFF<3> BIST_EN_I BIST_ADDR_I<3> ACLK_N_I ADDR_I<3> q_int<3> net2<1> VDD ++ VSS / RSC_IHPSG13_DFNQMX2IX1 +XDFF<2> BIST_EN_I BIST_ADDR_I<2> ACLK_N_I ADDR_I<2> q_int<2> net2<2> VDD ++ VSS / RSC_IHPSG13_DFNQMX2IX1 +XDFF<1> BIST_EN_I BIST_ADDR_I<1> ACLK_N_I ADDR_I<1> q_int<1> net2<3> VDD ++ VSS / RSC_IHPSG13_DFNQMX2IX1 +XDFF<0> BIST_EN_I BIST_ADDR_I<0> ACLK_N_I ADDR_I<0> q_int<0> net2<4> VDD ++ VSS / RSC_IHPSG13_DFNQMX2IX1 +XI11<16> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI11<15> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI11<14> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI11<13> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI11<12> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI11<11> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI11<10> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI11<9> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI11<8> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI11<7> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI11<6> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI11<5> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI11<4> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI11<3> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI11<2> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI11<1> VDD VSS / RSC_IHPSG13_FILLCAP8 +.ENDS + + +.SUBCKT RM_IHPSG13_64x32_c2_1P_COLDEC5 ACLK_N ADDR<4> ADDR<3> ADDR<2> ADDR<1> ADDR<0> ++ ADDR_COL<1> ADDR_COL<0> ADDR_DEC<7> ADDR_DEC<6> ADDR_DEC<5> ADDR_DEC<4> ++ ADDR_DEC<3> ADDR_DEC<2> ADDR_DEC<1> ADDR_DEC<0> BIST_ADDR<4> BIST_ADDR<3> ++ BIST_ADDR<2> BIST_ADDR<1> BIST_ADDR<0> BIST_EN_I VDD VSS +XI17<2> VDD VSS / RSC_IHPSG13_FILLCAP4 +XI17<1> VDD VSS / RSC_IHPSG13_FILLCAP4 +XI13<1> addr_int<1> ADDR_COL<1> VDD VSS / RSC_IHPSG13_CBUFX2 +XI13<0> addr_int<0> ADDR_COL<0> VDD VSS / RSC_IHPSG13_CBUFX2 +XDFF<4> BIST_EN_I BIST_ADDR<4> ACLK_N ADDR<4> addr_int<1> net7<0> VDD ++ VSS / RSC_IHPSG13_DFNQMX2IX1 +XDFF<3> BIST_EN_I BIST_ADDR<3> ACLK_N ADDR<3> addr_int<0> net7<1> VDD ++ VSS / RSC_IHPSG13_DFNQMX2IX1 +XDFF<2> BIST_EN_I BIST_ADDR<2> ACLK_N ADDR<2> padr_int<2> net7<2> VDD ++ VSS / RSC_IHPSG13_DFNQMX2IX1 +XDFF<1> BIST_EN_I BIST_ADDR<1> ACLK_N ADDR<1> padr_int<1> net7<3> VDD ++ VSS / RSC_IHPSG13_DFNQMX2IX1 +XDFF<0> BIST_EN_I BIST_ADDR<0> ACLK_N ADDR<0> padr_int<0> net7<4> VDD ++ VSS / RSC_IHPSG13_DFNQMX2IX1 +XI1<7> PADR<0> PADR<1> PADR<2> addr_n<7> VDD VSS / RSC_IHPSG13_NAND3X2 +XI1<6> NADR<0> PADR<1> PADR<2> addr_n<6> VDD VSS / RSC_IHPSG13_NAND3X2 +XI1<5> PADR<0> NADR<1> PADR<2> addr_n<5> VDD VSS / RSC_IHPSG13_NAND3X2 +XI1<4> NADR<0> NADR<1> PADR<2> addr_n<4> VDD VSS / RSC_IHPSG13_NAND3X2 +XI1<3> PADR<0> PADR<1> NADR<2> addr_n<3> VDD VSS / RSC_IHPSG13_NAND3X2 +XI1<2> NADR<0> PADR<1> NADR<2> addr_n<2> VDD VSS / RSC_IHPSG13_NAND3X2 +XI1<1> PADR<0> NADR<1> NADR<2> addr_n<1> VDD VSS / RSC_IHPSG13_NAND3X2 +XI1<0> NADR<0> NADR<1> NADR<2> addr_n<0> VDD VSS / RSC_IHPSG13_NAND3X2 +XI15<2> NADR<2> PADR<2> VDD VSS / RSC_IHPSG13_INVX2 +XI15<1> NADR<1> PADR<1> VDD VSS / RSC_IHPSG13_INVX2 +XI15<0> NADR<0> PADR<0> VDD VSS / RSC_IHPSG13_INVX2 +XI3<2> padr_int<2> NADR<2> VDD VSS / RSC_IHPSG13_INVX2 +XI3<1> padr_int<1> NADR<1> VDD VSS / RSC_IHPSG13_INVX2 +XI3<0> padr_int<0> NADR<0> VDD VSS / RSC_IHPSG13_INVX2 +XI2<7> addr_n<7> ADDR_DEC<7> VDD VSS / RSC_IHPSG13_INVX2 +XI2<6> addr_n<6> ADDR_DEC<6> VDD VSS / RSC_IHPSG13_INVX2 +XI2<5> addr_n<5> ADDR_DEC<5> VDD VSS / RSC_IHPSG13_INVX2 +XI2<4> addr_n<4> ADDR_DEC<4> VDD VSS / RSC_IHPSG13_INVX2 +XI2<3> addr_n<3> ADDR_DEC<3> VDD VSS / RSC_IHPSG13_INVX2 +XI2<2> addr_n<2> ADDR_DEC<2> VDD VSS / RSC_IHPSG13_INVX2 +XI2<1> addr_n<1> ADDR_DEC<1> VDD VSS / RSC_IHPSG13_INVX2 +XI2<0> addr_n<0> ADDR_DEC<0> VDD VSS / RSC_IHPSG13_INVX2 +.ENDS +.SUBCKT RM_IHPSG13_64x32_c2_1P_COLCTRL5 A_ADDR_COL<1> A_ADDR_COL<0> A_ADDR_DEC<7> ++ A_ADDR_DEC<6> A_ADDR_DEC<5> A_ADDR_DEC<4> A_ADDR_DEC<3> A_ADDR_DEC<2> ++ A_ADDR_DEC<1> A_ADDR_DEC<0> A_BIST_BM_I A_BIST_DW_I A_BIST_EN_I A_BLC<31> ++ A_BLC<30> A_BLC<29> A_BLC<28> A_BLC<27> A_BLC<26> A_BLC<25> A_BLC<24> ++ A_BLC<23> A_BLC<22> A_BLC<21> A_BLC<20> A_BLC<19> A_BLC<18> A_BLC<17> ++ A_BLC<16> A_BLC<15> A_BLC<14> A_BLC<13> A_BLC<12> A_BLC<11> A_BLC<10> ++ A_BLC<9> A_BLC<8> A_BLC<7> A_BLC<6> A_BLC<5> A_BLC<4> A_BLC<3> A_BLC<2> ++ A_BLC<1> A_BLC<0> A_BLT<31> A_BLT<30> A_BLT<29> A_BLT<28> A_BLT<27> ++ A_BLT<26> A_BLT<25> A_BLT<24> A_BLT<23> A_BLT<22> A_BLT<21> A_BLT<20> ++ A_BLT<19> A_BLT<18> A_BLT<17> A_BLT<16> A_BLT<15> A_BLT<14> A_BLT<13> ++ A_BLT<12> A_BLT<11> A_BLT<10> A_BLT<9> A_BLT<8> A_BLT<7> A_BLT<6> A_BLT<5> ++ A_BLT<4> A_BLT<3> A_BLT<2> A_BLT<1> A_BLT<0> A_BM_I A_DCLK_B_L A_DCLK_B_R ++ A_DCLK_L A_DCLK_R A_DR_O A_DW_I A_RCLK_B_L A_RCLK_B_R A_RCLK_L A_RCLK_R ++ A_TIEH_O A_WCLK_B_L A_WCLK_B_R A_WCLK_L A_WCLK_R VDD VSS +XA_I80<1> A_WCLK_B_L A_RCLK_B_L A_W_nor_R<1> VDD VSS / ++ RSC_IHPSG13_AND2X2 +XA_I80<0> A_WCLK_B_L A_RCLK_B_L A_W_nor_R<0> VDD VSS / ++ RSC_IHPSG13_AND2X2 +XA_I44 A_BM_N A_WCLK_B_L A_DO_WRITE_P VDD VSS / RSC_IHPSG13_NOR2X2 +XI80<29> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI80<28> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI80<27> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI80<26> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI80<25> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI80<24> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI80<23> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI80<22> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI80<21> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI80<20> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI80<19> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI80<18> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI80<17> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI80<16> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI80<15> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI80<14> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI80<13> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI80<12> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI80<11> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI80<10> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI80<9> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI80<8> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI80<7> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI80<6> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI80<5> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI80<4> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI80<3> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI80<2> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI80<1> VDD VSS / RSC_IHPSG13_FILLCAP8 +XA_I74<16> VDD VSS / RSC_IHPSG13_FILLCAP8 +XA_I74<15> VDD VSS / RSC_IHPSG13_FILLCAP8 +XA_I74<14> VDD VSS / RSC_IHPSG13_FILLCAP8 +XA_I74<13> VDD VSS / RSC_IHPSG13_FILLCAP8 +XA_I74<12> VDD VSS / RSC_IHPSG13_FILLCAP8 +XA_I74<11> VDD VSS / RSC_IHPSG13_FILLCAP8 +XA_I74<10> VDD VSS / RSC_IHPSG13_FILLCAP8 +XA_I74<9> VDD VSS / RSC_IHPSG13_FILLCAP8 +XA_I74<8> VDD VSS / RSC_IHPSG13_FILLCAP8 +XA_I74<7> VDD VSS / RSC_IHPSG13_FILLCAP8 +XA_I74<6> VDD VSS / RSC_IHPSG13_FILLCAP8 +XA_I74<5> VDD VSS / RSC_IHPSG13_FILLCAP8 +XA_I74<4> VDD VSS / RSC_IHPSG13_FILLCAP8 +XA_I74<3> VDD VSS / RSC_IHPSG13_FILLCAP8 +XA_I74<2> VDD VSS / RSC_IHPSG13_FILLCAP8 +XA_I74<1> VDD VSS / RSC_IHPSG13_FILLCAP8 +XA_INV<6> A_N1<1> A_P1<1> VDD VSS / RSC_IHPSG13_CINVX4 +XA_INV<5> A_N0<1> A_P0<1> VDD VSS / RSC_IHPSG13_CINVX4 +XA_INV<4> A_N0<0> A_P0<0> VDD VSS / RSC_IHPSG13_CINVX4 +XA_INV<3> A_ADDR_COL<1> A_N1<1> VDD VSS / RSC_IHPSG13_CINVX4 +XA_INV<2> A_ADDR_COL<1> A_N1<0> VDD VSS / RSC_IHPSG13_CINVX4 +XA_INV<1> A_ADDR_COL<0> A_N0<1> VDD VSS / RSC_IHPSG13_CINVX4 +XA_INV<0> A_ADDR_COL<0> A_N0<0> VDD VSS / RSC_IHPSG13_CINVX4 +XA_I81<3> A_W_nor_R<1> A_PRE_N VDD VSS / RSC_IHPSG13_CINVX4_WN +XA_I81<2> A_W_nor_R<1> A_PRE_N VDD VSS / RSC_IHPSG13_CINVX4_WN +XA_I81<1> A_W_nor_R<0> A_PRE_N VDD VSS / RSC_IHPSG13_CINVX4_WN +XA_I81<0> A_W_nor_R<0> A_PRE_N VDD VSS / RSC_IHPSG13_CINVX4_WN +XA_BLTMUX<31> A_BLC<31> A_BLC_SEL A_BLT<31> A_BLT_SEL A_PRE_N A_SEL_P<31> ++ A_WR_ONE A_WR_ZERO VDD VSS / RM_IHPSG13_64x32_c2_1P_BLDRV +XA_BLTMUX<30> A_BLC<30> A_BLC_SEL A_BLT<30> A_BLT_SEL A_PRE_N A_SEL_P<30> ++ A_WR_ONE A_WR_ZERO VDD VSS / RM_IHPSG13_64x32_c2_1P_BLDRV +XA_BLTMUX<29> A_BLC<29> A_BLC_SEL A_BLT<29> A_BLT_SEL A_PRE_N A_SEL_P<29> ++ A_WR_ONE A_WR_ZERO VDD VSS / RM_IHPSG13_64x32_c2_1P_BLDRV +XA_BLTMUX<28> A_BLC<28> A_BLC_SEL A_BLT<28> A_BLT_SEL A_PRE_N A_SEL_P<28> ++ A_WR_ONE A_WR_ZERO VDD VSS / RM_IHPSG13_64x32_c2_1P_BLDRV +XA_BLTMUX<27> A_BLC<27> A_BLC_SEL A_BLT<27> A_BLT_SEL A_PRE_N A_SEL_P<27> ++ A_WR_ONE A_WR_ZERO VDD VSS / RM_IHPSG13_64x32_c2_1P_BLDRV +XA_BLTMUX<26> A_BLC<26> A_BLC_SEL A_BLT<26> A_BLT_SEL A_PRE_N A_SEL_P<26> ++ A_WR_ONE A_WR_ZERO VDD VSS / RM_IHPSG13_64x32_c2_1P_BLDRV +XA_BLTMUX<25> A_BLC<25> A_BLC_SEL A_BLT<25> A_BLT_SEL A_PRE_N A_SEL_P<25> ++ A_WR_ONE A_WR_ZERO VDD VSS / RM_IHPSG13_64x32_c2_1P_BLDRV +XA_BLTMUX<24> A_BLC<24> A_BLC_SEL A_BLT<24> A_BLT_SEL A_PRE_N A_SEL_P<24> ++ A_WR_ONE A_WR_ZERO VDD VSS / RM_IHPSG13_64x32_c2_1P_BLDRV +XA_BLTMUX<23> A_BLC<23> A_BLC_SEL A_BLT<23> A_BLT_SEL A_PRE_N A_SEL_P<23> ++ A_WR_ONE A_WR_ZERO VDD VSS / RM_IHPSG13_64x32_c2_1P_BLDRV +XA_BLTMUX<22> A_BLC<22> A_BLC_SEL A_BLT<22> A_BLT_SEL A_PRE_N A_SEL_P<22> ++ A_WR_ONE A_WR_ZERO VDD VSS / RM_IHPSG13_64x32_c2_1P_BLDRV +XA_BLTMUX<21> A_BLC<21> A_BLC_SEL A_BLT<21> A_BLT_SEL A_PRE_N A_SEL_P<21> ++ A_WR_ONE A_WR_ZERO VDD VSS / RM_IHPSG13_64x32_c2_1P_BLDRV +XA_BLTMUX<20> A_BLC<20> A_BLC_SEL A_BLT<20> A_BLT_SEL A_PRE_N A_SEL_P<20> ++ A_WR_ONE A_WR_ZERO VDD VSS / RM_IHPSG13_64x32_c2_1P_BLDRV +XA_BLTMUX<19> A_BLC<19> A_BLC_SEL A_BLT<19> A_BLT_SEL A_PRE_N A_SEL_P<19> ++ A_WR_ONE A_WR_ZERO VDD VSS / RM_IHPSG13_64x32_c2_1P_BLDRV +XA_BLTMUX<18> A_BLC<18> A_BLC_SEL A_BLT<18> A_BLT_SEL A_PRE_N A_SEL_P<18> ++ A_WR_ONE A_WR_ZERO VDD VSS / RM_IHPSG13_64x32_c2_1P_BLDRV +XA_BLTMUX<17> A_BLC<17> A_BLC_SEL A_BLT<17> A_BLT_SEL A_PRE_N A_SEL_P<17> ++ A_WR_ONE A_WR_ZERO VDD VSS / RM_IHPSG13_64x32_c2_1P_BLDRV +XA_BLTMUX<16> A_BLC<16> A_BLC_SEL A_BLT<16> A_BLT_SEL A_PRE_N A_SEL_P<16> ++ A_WR_ONE A_WR_ZERO VDD VSS / RM_IHPSG13_64x32_c2_1P_BLDRV +XA_BLTMUX<15> A_BLC<15> A_BLC_SEL A_BLT<15> A_BLT_SEL A_PRE_N A_SEL_P<15> ++ A_WR_ONE A_WR_ZERO VDD VSS / RM_IHPSG13_64x32_c2_1P_BLDRV +XA_BLTMUX<14> A_BLC<14> A_BLC_SEL A_BLT<14> A_BLT_SEL A_PRE_N A_SEL_P<14> ++ A_WR_ONE A_WR_ZERO VDD VSS / RM_IHPSG13_64x32_c2_1P_BLDRV +XA_BLTMUX<13> A_BLC<13> A_BLC_SEL A_BLT<13> A_BLT_SEL A_PRE_N A_SEL_P<13> ++ A_WR_ONE A_WR_ZERO VDD VSS / RM_IHPSG13_64x32_c2_1P_BLDRV +XA_BLTMUX<12> A_BLC<12> A_BLC_SEL A_BLT<12> A_BLT_SEL A_PRE_N A_SEL_P<12> ++ A_WR_ONE A_WR_ZERO VDD VSS / RM_IHPSG13_64x32_c2_1P_BLDRV +XA_BLTMUX<11> A_BLC<11> A_BLC_SEL A_BLT<11> A_BLT_SEL A_PRE_N A_SEL_P<11> ++ A_WR_ONE A_WR_ZERO VDD VSS / RM_IHPSG13_64x32_c2_1P_BLDRV +XA_BLTMUX<10> A_BLC<10> A_BLC_SEL A_BLT<10> A_BLT_SEL A_PRE_N A_SEL_P<10> ++ A_WR_ONE A_WR_ZERO VDD VSS / RM_IHPSG13_64x32_c2_1P_BLDRV +XA_BLTMUX<9> A_BLC<9> A_BLC_SEL A_BLT<9> A_BLT_SEL A_PRE_N A_SEL_P<9> A_WR_ONE ++ A_WR_ZERO VDD VSS / RM_IHPSG13_64x32_c2_1P_BLDRV +XA_BLTMUX<8> A_BLC<8> A_BLC_SEL A_BLT<8> A_BLT_SEL A_PRE_N A_SEL_P<8> A_WR_ONE ++ A_WR_ZERO VDD VSS / RM_IHPSG13_64x32_c2_1P_BLDRV +XA_BLTMUX<7> A_BLC<7> A_BLC_SEL A_BLT<7> A_BLT_SEL A_PRE_N A_SEL_P<7> A_WR_ONE ++ A_WR_ZERO VDD VSS / RM_IHPSG13_64x32_c2_1P_BLDRV +XA_BLTMUX<6> A_BLC<6> A_BLC_SEL A_BLT<6> A_BLT_SEL A_PRE_N A_SEL_P<6> A_WR_ONE ++ A_WR_ZERO VDD VSS / RM_IHPSG13_64x32_c2_1P_BLDRV +XA_BLTMUX<5> A_BLC<5> A_BLC_SEL A_BLT<5> A_BLT_SEL A_PRE_N A_SEL_P<5> A_WR_ONE ++ A_WR_ZERO VDD VSS / RM_IHPSG13_64x32_c2_1P_BLDRV +XA_BLTMUX<4> A_BLC<4> A_BLC_SEL A_BLT<4> A_BLT_SEL A_PRE_N A_SEL_P<4> A_WR_ONE ++ A_WR_ZERO VDD VSS / RM_IHPSG13_64x32_c2_1P_BLDRV +XA_BLTMUX<3> A_BLC<3> A_BLC_SEL A_BLT<3> A_BLT_SEL A_PRE_N A_SEL_P<3> A_WR_ONE ++ A_WR_ZERO VDD VSS / RM_IHPSG13_64x32_c2_1P_BLDRV +XA_BLTMUX<2> A_BLC<2> A_BLC_SEL A_BLT<2> A_BLT_SEL A_PRE_N A_SEL_P<2> A_WR_ONE ++ A_WR_ZERO VDD VSS / RM_IHPSG13_64x32_c2_1P_BLDRV +XA_BLTMUX<1> A_BLC<1> A_BLC_SEL A_BLT<1> A_BLT_SEL A_PRE_N A_SEL_P<1> A_WR_ONE ++ A_WR_ZERO VDD VSS / RM_IHPSG13_64x32_c2_1P_BLDRV +XA_BLTMUX<0> A_BLC<0> A_BLC_SEL A_BLT<0> A_BLT_SEL A_PRE_N A_SEL_P<0> A_WR_ONE ++ A_WR_ZERO VDD VSS / RM_IHPSG13_64x32_c2_1P_BLDRV +XA_CAPS<17> VDD VSS / RSC_IHPSG13_FILLCAP4 +XA_CAPS<16> VDD VSS / RSC_IHPSG13_FILLCAP4 +XA_CAPS<15> VDD VSS / RSC_IHPSG13_FILLCAP4 +XA_CAPS<14> VDD VSS / RSC_IHPSG13_FILLCAP4 +XA_CAPS<13> VDD VSS / RSC_IHPSG13_FILLCAP4 +XA_CAPS<12> VDD VSS / RSC_IHPSG13_FILLCAP4 +XA_CAPS<11> VDD VSS / RSC_IHPSG13_FILLCAP4 +XA_CAPS<10> VDD VSS / RSC_IHPSG13_FILLCAP4 +XA_CAPS<9> VDD VSS / RSC_IHPSG13_FILLCAP4 +XA_CAPS<8> VDD VSS / RSC_IHPSG13_FILLCAP4 +XA_CAPS<7> VDD VSS / RSC_IHPSG13_FILLCAP4 +XA_CAPS<6> VDD VSS / RSC_IHPSG13_FILLCAP4 +XA_CAPS<5> VDD VSS / RSC_IHPSG13_FILLCAP4 +XA_CAPS<4> VDD VSS / RSC_IHPSG13_FILLCAP4 +XA_CAPS<3> VDD VSS / RSC_IHPSG13_FILLCAP4 +XA_CAPS<2> VDD VSS / RSC_IHPSG13_FILLCAP4 +XA_CAPS<1> VDD VSS / RSC_IHPSG13_FILLCAP4 +XA_I51 net19 A_DR_O VDD VSS / RSC_IHPSG13_INVX4 +XA_I78 A_RCLK_B_L A_SAE VDD VSS / RSC_IHPSG13_CBUFX2 +XA_I69 A_DCLK_L A_DCLK_B_L VDD VSS / RSC_IHPSG13_CINVX8 +XA_I50 A_WCLK_L A_WCLK_B_L VDD VSS / RSC_IHPSG13_CINVX8 +XA_EBUF A_RCLK_L A_RCLK_B_L VDD VSS / RSC_IHPSG13_CINVX8 +XA_I76 A_DI_N A_DO_WRITE_P A_WR_ZERO VDD VSS / RSC_IHPSG13_AND2X6 +XA_I75 A_DI_R A_DO_WRITE_P A_WR_ONE VDD VSS / RSC_IHPSG13_AND2X6 +XA_I83 A_BM_R A_BM_N VDD VSS / RSC_IHPSG13_INVX2 +XA_DEC3INV<31> net23<0> A_SEL_P<31> VDD VSS / RSC_IHPSG13_INVX2 +XA_DEC3INV<30> net23<1> A_SEL_P<30> VDD VSS / RSC_IHPSG13_INVX2 +XA_DEC3INV<29> net23<2> A_SEL_P<29> VDD VSS / RSC_IHPSG13_INVX2 +XA_DEC3INV<28> net23<3> A_SEL_P<28> VDD VSS / RSC_IHPSG13_INVX2 +XA_DEC3INV<27> net23<4> A_SEL_P<27> VDD VSS / RSC_IHPSG13_INVX2 +XA_DEC3INV<26> net23<5> A_SEL_P<26> VDD VSS / RSC_IHPSG13_INVX2 +XA_DEC3INV<25> net23<6> A_SEL_P<25> VDD VSS / RSC_IHPSG13_INVX2 +XA_DEC3INV<24> net23<7> A_SEL_P<24> VDD VSS / RSC_IHPSG13_INVX2 +XA_DEC3INV<23> net23<8> A_SEL_P<23> VDD VSS / RSC_IHPSG13_INVX2 +XA_DEC3INV<22> net23<9> A_SEL_P<22> VDD VSS / RSC_IHPSG13_INVX2 +XA_DEC3INV<21> net23<10> A_SEL_P<21> VDD VSS / RSC_IHPSG13_INVX2 +XA_DEC3INV<20> net23<11> A_SEL_P<20> VDD VSS / RSC_IHPSG13_INVX2 +XA_DEC3INV<19> net23<12> A_SEL_P<19> VDD VSS / RSC_IHPSG13_INVX2 +XA_DEC3INV<18> net23<13> A_SEL_P<18> VDD VSS / RSC_IHPSG13_INVX2 +XA_DEC3INV<17> net23<14> A_SEL_P<17> VDD VSS / RSC_IHPSG13_INVX2 +XA_DEC3INV<16> net23<15> A_SEL_P<16> VDD VSS / RSC_IHPSG13_INVX2 +XA_DEC3INV<15> net23<16> A_SEL_P<15> VDD VSS / RSC_IHPSG13_INVX2 +XA_DEC3INV<14> net23<17> A_SEL_P<14> VDD VSS / RSC_IHPSG13_INVX2 +XA_DEC3INV<13> net23<18> A_SEL_P<13> VDD VSS / RSC_IHPSG13_INVX2 +XA_DEC3INV<12> net23<19> A_SEL_P<12> VDD VSS / RSC_IHPSG13_INVX2 +XA_DEC3INV<11> net23<20> A_SEL_P<11> VDD VSS / RSC_IHPSG13_INVX2 +XA_DEC3INV<10> net23<21> A_SEL_P<10> VDD VSS / RSC_IHPSG13_INVX2 +XA_DEC3INV<9> net23<22> A_SEL_P<9> VDD VSS / RSC_IHPSG13_INVX2 +XA_DEC3INV<8> net23<23> A_SEL_P<8> VDD VSS / RSC_IHPSG13_INVX2 +XA_DEC3INV<7> net23<24> A_SEL_P<7> VDD VSS / RSC_IHPSG13_INVX2 +XA_DEC3INV<6> net23<25> A_SEL_P<6> VDD VSS / RSC_IHPSG13_INVX2 +XA_DEC3INV<5> net23<26> A_SEL_P<5> VDD VSS / RSC_IHPSG13_INVX2 +XA_DEC3INV<4> net23<27> A_SEL_P<4> VDD VSS / RSC_IHPSG13_INVX2 +XA_DEC3INV<3> net23<28> A_SEL_P<3> VDD VSS / RSC_IHPSG13_INVX2 +XA_DEC3INV<2> net23<29> A_SEL_P<2> VDD VSS / RSC_IHPSG13_INVX2 +XA_DEC3INV<1> net23<30> A_SEL_P<1> VDD VSS / RSC_IHPSG13_INVX2 +XA_DEC3INV<0> net23<31> A_SEL_P<0> VDD VSS / RSC_IHPSG13_INVX2 +XA_I49 A_DI_R A_DI_N VDD VSS / RSC_IHPSG13_INVX2 +XA_ISENSE A_SAE A_BLC_SEL A_BLT_SEL net19 net20 VDD VSS / ++ RSC_IHPSG13_DFPQD_MSAFFX2 +XA_DREG A_BIST_EN_I A_BIST_DW_I A_DCLK_B_L A_DW_I A_DI_R net22 VDD VSS ++ / RSC_IHPSG13_DFNQMX2IX1 +XA_BREG A_BIST_EN_I A_BIST_BM_I A_DCLK_B_L A_BM_I A_BM_R net21 VDD VSS ++ / RSC_IHPSG13_DFNQMX2IX1 +XA_DEC3<31> A_P1<1> A_P0<1> A_ADDR_DEC<7> net23<0> VDD VSS / ++ RSC_IHPSG13_NAND3X2 +XA_DEC3<30> A_P1<1> A_P0<1> A_ADDR_DEC<6> net23<1> VDD VSS / ++ RSC_IHPSG13_NAND3X2 +XA_DEC3<29> A_P1<1> A_P0<1> A_ADDR_DEC<5> net23<2> VDD VSS / ++ RSC_IHPSG13_NAND3X2 +XA_DEC3<28> A_P1<1> A_P0<1> A_ADDR_DEC<4> net23<3> VDD VSS / ++ RSC_IHPSG13_NAND3X2 +XA_DEC3<27> A_P1<1> A_P0<1> A_ADDR_DEC<3> net23<4> VDD VSS / ++ RSC_IHPSG13_NAND3X2 +XA_DEC3<26> A_P1<1> A_P0<1> A_ADDR_DEC<2> net23<5> VDD VSS / ++ RSC_IHPSG13_NAND3X2 +XA_DEC3<25> A_P1<1> A_P0<1> A_ADDR_DEC<1> net23<6> VDD VSS / ++ RSC_IHPSG13_NAND3X2 +XA_DEC3<24> A_P1<1> A_P0<1> A_ADDR_DEC<0> net23<7> VDD VSS / ++ RSC_IHPSG13_NAND3X2 +XA_DEC3<23> A_P1<1> A_N0<1> A_ADDR_DEC<7> net23<8> VDD VSS / ++ RSC_IHPSG13_NAND3X2 +XA_DEC3<22> A_P1<1> A_N0<1> A_ADDR_DEC<6> net23<9> VDD VSS / ++ RSC_IHPSG13_NAND3X2 +XA_DEC3<21> A_P1<1> A_N0<1> A_ADDR_DEC<5> net23<10> VDD VSS / ++ RSC_IHPSG13_NAND3X2 +XA_DEC3<20> A_P1<1> A_N0<1> A_ADDR_DEC<4> net23<11> VDD VSS / ++ RSC_IHPSG13_NAND3X2 +XA_DEC3<19> A_P1<1> A_N0<1> A_ADDR_DEC<3> net23<12> VDD VSS / ++ RSC_IHPSG13_NAND3X2 +XA_DEC3<18> A_P1<1> A_N0<1> A_ADDR_DEC<2> net23<13> VDD VSS / ++ RSC_IHPSG13_NAND3X2 +XA_DEC3<17> A_P1<1> A_N0<1> A_ADDR_DEC<1> net23<14> VDD VSS / ++ RSC_IHPSG13_NAND3X2 +XA_DEC3<16> A_P1<1> A_N0<1> A_ADDR_DEC<0> net23<15> VDD VSS / ++ RSC_IHPSG13_NAND3X2 +XA_DEC3<15> A_N1<0> A_P0<0> A_ADDR_DEC<7> net23<16> VDD VSS / ++ RSC_IHPSG13_NAND3X2 +XA_DEC3<14> A_N1<0> A_P0<0> A_ADDR_DEC<6> net23<17> VDD VSS / ++ RSC_IHPSG13_NAND3X2 +XA_DEC3<13> A_N1<0> A_P0<0> A_ADDR_DEC<5> net23<18> VDD VSS / ++ RSC_IHPSG13_NAND3X2 +XA_DEC3<12> A_N1<0> A_P0<0> A_ADDR_DEC<4> net23<19> VDD VSS / ++ RSC_IHPSG13_NAND3X2 +XA_DEC3<11> A_N1<0> A_P0<0> A_ADDR_DEC<3> net23<20> VDD VSS / ++ RSC_IHPSG13_NAND3X2 +XA_DEC3<10> A_N1<0> A_P0<0> A_ADDR_DEC<2> net23<21> VDD VSS / ++ RSC_IHPSG13_NAND3X2 +XA_DEC3<9> A_N1<0> A_P0<0> A_ADDR_DEC<1> net23<22> VDD VSS / ++ RSC_IHPSG13_NAND3X2 +XA_DEC3<8> A_N1<0> A_P0<0> A_ADDR_DEC<0> net23<23> VDD VSS / ++ RSC_IHPSG13_NAND3X2 +XA_DEC3<7> A_N1<0> A_N0<0> A_ADDR_DEC<7> net23<24> VDD VSS / ++ RSC_IHPSG13_NAND3X2 +XA_DEC3<6> A_N1<0> A_N0<0> A_ADDR_DEC<6> net23<25> VDD VSS / ++ RSC_IHPSG13_NAND3X2 +XA_DEC3<5> A_N1<0> A_N0<0> A_ADDR_DEC<5> net23<26> VDD VSS / ++ RSC_IHPSG13_NAND3X2 +XA_DEC3<4> A_N1<0> A_N0<0> A_ADDR_DEC<4> net23<27> VDD VSS / ++ RSC_IHPSG13_NAND3X2 +XA_DEC3<3> A_N1<0> A_N0<0> A_ADDR_DEC<3> net23<28> VDD VSS / ++ RSC_IHPSG13_NAND3X2 +XA_DEC3<2> A_N1<0> A_N0<0> A_ADDR_DEC<2> net23<29> VDD VSS / ++ RSC_IHPSG13_NAND3X2 +XA_DEC3<1> A_N1<0> A_N0<0> A_ADDR_DEC<1> net23<30> VDD VSS / ++ RSC_IHPSG13_NAND3X2 +XA_DEC3<0> A_N1<0> A_N0<0> A_ADDR_DEC<0> net23<31> VDD VSS / ++ RSC_IHPSG13_NAND3X2 +XA_I89 A_DCLK_B_L A_DCLK_B_R / RSC_IHPSG13_MET3RES +XA_I91 A_RCLK_B_L A_RCLK_B_R / RSC_IHPSG13_MET3RES +XA_I90 A_WCLK_B_L A_WCLK_B_R / RSC_IHPSG13_MET3RES +XA_I88 A_DCLK_L A_DCLK_R / RSC_IHPSG13_MET3RES +XA_I87 A_WCLK_L A_WCLK_R / RSC_IHPSG13_MET3RES +XA_R2 A_RCLK_L A_RCLK_R / RSC_IHPSG13_MET3RES +XA_BM_TIEH A_TIEH_O VDD VSS / RSC_IHPSG13_TIEH +.ENDS + +.SUBCKT RM_IHPSG13_64x32_c2_1P_COLDRV13X12 ADDR_COL_I<1> ADDR_COL_I<0> ADDR_COL_O<1> ++ ADDR_COL_O<0> ADDR_DEC_I<7> ADDR_DEC_I<6> ADDR_DEC_I<5> ADDR_DEC_I<4> ++ ADDR_DEC_I<3> ADDR_DEC_I<2> ADDR_DEC_I<1> ADDR_DEC_I<0> ADDR_DEC_O<7> ++ ADDR_DEC_O<6> ADDR_DEC_O<5> ADDR_DEC_O<4> ADDR_DEC_O<3> ADDR_DEC_O<2> ++ ADDR_DEC_O<1> ADDR_DEC_O<0> DCLK_I DCLK_O RCLK_I RCLK_O WCLK_I WCLK_O ++ VDD VSS +XI1<1> VDD VSS / RSC_IHPSG13_FILLCAP4 +XI1<0> VDD VSS / RSC_IHPSG13_FILLCAP4 +XI0<1> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI0<0> VDD VSS / RSC_IHPSG13_FILLCAP8 +XADDR_COL_DRV<1> ADDR_COL_I<1> ADDR_COL_O<1> VDD VSS / ++ RSC_IHPSG13_CBUFX12 +XADDR_COL_DRV<0> ADDR_COL_I<0> ADDR_COL_O<0> VDD VSS / ++ RSC_IHPSG13_CBUFX12 +XADDR_DEC_DRV<7> ADDR_DEC_I<7> ADDR_DEC_O<7> VDD VSS / ++ RSC_IHPSG13_CBUFX12 +XADDR_DEC_DRV<6> ADDR_DEC_I<6> ADDR_DEC_O<6> VDD VSS / ++ RSC_IHPSG13_CBUFX12 +XADDR_DEC_DRV<5> ADDR_DEC_I<5> ADDR_DEC_O<5> VDD VSS / ++ RSC_IHPSG13_CBUFX12 +XADDR_DEC_DRV<4> ADDR_DEC_I<4> ADDR_DEC_O<4> VDD VSS / ++ RSC_IHPSG13_CBUFX12 +XADDR_DEC_DRV<3> ADDR_DEC_I<3> ADDR_DEC_O<3> VDD VSS / ++ RSC_IHPSG13_CBUFX12 +XADDR_DEC_DRV<2> ADDR_DEC_I<2> ADDR_DEC_O<2> VDD VSS / ++ RSC_IHPSG13_CBUFX12 +XADDR_DEC_DRV<1> ADDR_DEC_I<1> ADDR_DEC_O<1> VDD VSS / ++ RSC_IHPSG13_CBUFX12 +XADDR_DEC_DRV<0> ADDR_DEC_I<0> ADDR_DEC_O<0> VDD VSS / ++ RSC_IHPSG13_CBUFX12 +XDCLK_DRV DCLK_I DCLK_O VDD VSS / RSC_IHPSG13_CBUFX12 +XRCLK_DRV RCLK_I RCLK_O VDD VSS / RSC_IHPSG13_CBUFX12 +XWCLK_DRV WCLK_I WCLK_O VDD VSS / RSC_IHPSG13_CBUFX12 +.ENDS +.SUBCKT RM_IHPSG13_64x32_c2_1P_WLDRV16X12 A<15> A<14> A<13> A<12> A<11> A<10> A<9> A<8> ++ A<7> A<6> A<5> A<4> A<3> A<2> A<1> A<0> Z<15> Z<14> Z<13> Z<12> Z<11> Z<10> ++ Z<9> Z<8> Z<7> Z<6> Z<5> Z<4> Z<3> Z<2> Z<1> Z<0> VDD VSS +XBUF<15> A<15> Z<15> VDD VSS / RSC_IHPSG13_WLDRVX12 +XBUF<14> A<14> Z<14> VDD VSS / RSC_IHPSG13_WLDRVX12 +XBUF<13> A<13> Z<13> VDD VSS / RSC_IHPSG13_WLDRVX12 +XBUF<12> A<12> Z<12> VDD VSS / RSC_IHPSG13_WLDRVX12 +XBUF<11> A<11> Z<11> VDD VSS / RSC_IHPSG13_WLDRVX12 +XBUF<10> A<10> Z<10> VDD VSS / RSC_IHPSG13_WLDRVX12 +XBUF<9> A<9> Z<9> VDD VSS / RSC_IHPSG13_WLDRVX12 +XBUF<8> A<8> Z<8> VDD VSS / RSC_IHPSG13_WLDRVX12 +XBUF<7> A<7> Z<7> VDD VSS / RSC_IHPSG13_WLDRVX12 +XBUF<6> A<6> Z<6> VDD VSS / RSC_IHPSG13_WLDRVX12 +XBUF<5> A<5> Z<5> VDD VSS / RSC_IHPSG13_WLDRVX12 +XBUF<4> A<4> Z<4> VDD VSS / RSC_IHPSG13_WLDRVX12 +XBUF<3> A<3> Z<3> VDD VSS / RSC_IHPSG13_WLDRVX12 +XBUF<2> A<2> Z<2> VDD VSS / RSC_IHPSG13_WLDRVX12 +XBUF<1> A<1> Z<1> VDD VSS / RSC_IHPSG13_WLDRVX12 +XBUF<0> A<0> Z<0> VDD VSS / RSC_IHPSG13_WLDRVX12 +.ENDS + + + +.SUBCKT RM_IHPSG13_64x32_c2_2P_COLDRV13X8 ADDR_COL_I<1> ADDR_COL_I<0> ADDR_COL_O<1> ++ ADDR_COL_O<0> ADDR_DEC_I<7> ADDR_DEC_I<6> ADDR_DEC_I<5> ADDR_DEC_I<4> ++ ADDR_DEC_I<3> ADDR_DEC_I<2> ADDR_DEC_I<1> ADDR_DEC_I<0> ADDR_DEC_O<7> ++ ADDR_DEC_O<6> ADDR_DEC_O<5> ADDR_DEC_O<4> ADDR_DEC_O<3> ADDR_DEC_O<2> ++ ADDR_DEC_O<1> ADDR_DEC_O<0> DCLK_I DCLK_O RCLK_I RCLK_O WCLK_I WCLK_O ++ VDD VSS +XI0<5> VDD VSS / RSC_IHPSG13_FILLCAP4 +XI0<4> VDD VSS / RSC_IHPSG13_FILLCAP4 +XI0<3> VDD VSS / RSC_IHPSG13_FILLCAP4 +XI0<2> VDD VSS / RSC_IHPSG13_FILLCAP4 +XI0<1> VDD VSS / RSC_IHPSG13_FILLCAP4 +XWCLK_DRV WCLK_I WCLK_O VDD VSS / RSC_IHPSG13_CBUFX8 +XRCLK_DRV RCLK_I RCLK_O VDD VSS / RSC_IHPSG13_CBUFX8 +XDCLK_DRV DCLK_I DCLK_O VDD VSS / RSC_IHPSG13_CBUFX8 +XADDR_COL_DRV<1> ADDR_COL_I<1> ADDR_COL_O<1> VDD VSS / ++ RSC_IHPSG13_CBUFX8 +XADDR_COL_DRV<0> ADDR_COL_I<0> ADDR_COL_O<0> VDD VSS / ++ RSC_IHPSG13_CBUFX8 +XADDR_DEC_DRV<7> ADDR_DEC_I<7> ADDR_DEC_O<7> VDD VSS / ++ RSC_IHPSG13_CBUFX8 +XADDR_DEC_DRV<6> ADDR_DEC_I<6> ADDR_DEC_O<6> VDD VSS / ++ RSC_IHPSG13_CBUFX8 +XADDR_DEC_DRV<5> ADDR_DEC_I<5> ADDR_DEC_O<5> VDD VSS / ++ RSC_IHPSG13_CBUFX8 +XADDR_DEC_DRV<4> ADDR_DEC_I<4> ADDR_DEC_O<4> VDD VSS / ++ RSC_IHPSG13_CBUFX8 +XADDR_DEC_DRV<3> ADDR_DEC_I<3> ADDR_DEC_O<3> VDD VSS / ++ RSC_IHPSG13_CBUFX8 +XADDR_DEC_DRV<2> ADDR_DEC_I<2> ADDR_DEC_O<2> VDD VSS / ++ RSC_IHPSG13_CBUFX8 +XADDR_DEC_DRV<1> ADDR_DEC_I<1> ADDR_DEC_O<1> VDD VSS / ++ RSC_IHPSG13_CBUFX8 +XADDR_DEC_DRV<0> ADDR_DEC_I<0> ADDR_DEC_O<0> VDD VSS / ++ RSC_IHPSG13_CBUFX8 +XI1<3> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI1<2> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI1<1> VDD VSS / RSC_IHPSG13_FILLCAP8 +.ENDS +.SUBCKT RSC_IHPSG13_WLDRVX8 A Z VDD VSS +MN1 Z net6 VSS VSS sg13_lv_nmos m=1 w=1.41u l=130.00n ng=2 nrd=0 nrs=0 +MN0 net6 A VSS VSS sg13_lv_nmos m=1 w=1.8u l=130.00n ng=2 nrd=0 nrs=0 +MP1 Z net6 VDD VDD sg13_lv_pmos m=1 w=6.48u l=130.00n ng=4 nrd=0 nrs=0 +MP0 net6 A VDD VDD sg13_lv_pmos m=1 w=900.0n l=130.00n ng=1 nrd=0 nrs=0 +.ENDS +.SUBCKT RM_IHPSG13_64x32_c2_2P_WLDRV16X8 A<15> A<14> A<13> A<12> A<11> A<10> A<9> A<8> ++ A<7> A<6> A<5> A<4> A<3> A<2> A<1> A<0> Z<15> Z<14> Z<13> Z<12> Z<11> Z<10> ++ Z<9> Z<8> Z<7> Z<6> Z<5> Z<4> Z<3> Z<2> Z<1> Z<0> VDD VSS +XBUF<15> A<15> Z<15> VDD VSS / RSC_IHPSG13_WLDRVX8 +XBUF<14> A<14> Z<14> VDD VSS / RSC_IHPSG13_WLDRVX8 +XBUF<13> A<13> Z<13> VDD VSS / RSC_IHPSG13_WLDRVX8 +XBUF<12> A<12> Z<12> VDD VSS / RSC_IHPSG13_WLDRVX8 +XBUF<11> A<11> Z<11> VDD VSS / RSC_IHPSG13_WLDRVX8 +XBUF<10> A<10> Z<10> VDD VSS / RSC_IHPSG13_WLDRVX8 +XBUF<9> A<9> Z<9> VDD VSS / RSC_IHPSG13_WLDRVX8 +XBUF<8> A<8> Z<8> VDD VSS / RSC_IHPSG13_WLDRVX8 +XBUF<7> A<7> Z<7> VDD VSS / RSC_IHPSG13_WLDRVX8 +XBUF<6> A<6> Z<6> VDD VSS / RSC_IHPSG13_WLDRVX8 +XBUF<5> A<5> Z<5> VDD VSS / RSC_IHPSG13_WLDRVX8 +XBUF<4> A<4> Z<4> VDD VSS / RSC_IHPSG13_WLDRVX8 +XBUF<3> A<3> Z<3> VDD VSS / RSC_IHPSG13_WLDRVX8 +XBUF<2> A<2> Z<2> VDD VSS / RSC_IHPSG13_WLDRVX8 +XBUF<1> A<1> Z<1> VDD VSS / RSC_IHPSG13_WLDRVX8 +XBUF<0> A<0> Z<0> VDD VSS / RSC_IHPSG13_WLDRVX8 +.ENDS + + + +.SUBCKT RM_IHPSG13_64x32_c2_2P_COLDEC2 ACLK_N ADDR<1> ADDR<0> ADDR_COL<1> ADDR_COL<0> ++ ADDR_DEC<7> ADDR_DEC<6> ADDR_DEC<5> ADDR_DEC<4> ADDR_DEC<3> ADDR_DEC<2> ++ ADDR_DEC<1> ADDR_DEC<0> BIST_ADDR<1> BIST_ADDR<0> BIST_EN_I VDD VSS +XI16<17> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI16<16> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI16<15> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI16<14> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI16<13> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI16<12> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI16<11> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI16<10> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI16<9> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI16<8> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI16<7> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI16<6> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI16<5> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI16<4> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI16<3> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI16<2> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI16<1> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI18<24> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI18<23> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI18<22> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI18<21> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI18<20> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI18<19> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI18<18> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI18<17> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI18<16> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI18<15> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI18<14> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI18<13> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI18<12> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI18<11> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI18<10> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI18<9> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI18<8> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI18<7> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI18<6> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI18<5> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI18<4> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI18<3> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI18<2> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI18<1> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI1<3> PADR<0> PADR<1> addr_n<3> VDD VSS / RSC_IHPSG13_NAND2X2 +XI1<2> NADR<0> PADR<1> addr_n<2> VDD VSS / RSC_IHPSG13_NAND2X2 +XI1<1> PADR<0> NADR<1> addr_n<1> VDD VSS / RSC_IHPSG13_NAND2X2 +XI1<0> NADR<0> NADR<1> addr_n<0> VDD VSS / RSC_IHPSG13_NAND2X2 +XI17<1> ADDR_COL<1> VDD VSS / RSC_IHPSG13_TIEL +XI17<0> ADDR_COL<0> VDD VSS / RSC_IHPSG13_TIEL +XI14<3> ADDR_DEC<7> VDD VSS / RSC_IHPSG13_TIEL +XI14<2> ADDR_DEC<6> VDD VSS / RSC_IHPSG13_TIEL +XI14<1> ADDR_DEC<5> VDD VSS / RSC_IHPSG13_TIEL +XI14<0> ADDR_DEC<4> VDD VSS / RSC_IHPSG13_TIEL +XI13<1> NADR<1> PADR<1> VDD VSS / RSC_IHPSG13_INVX2 +XI13<0> NADR<0> PADR<0> VDD VSS / RSC_IHPSG13_INVX2 +XI3<1> padr_int<1> NADR<1> VDD VSS / RSC_IHPSG13_INVX2 +XI3<0> padr_int<0> NADR<0> VDD VSS / RSC_IHPSG13_INVX2 +XI2<3> addr_n<3> ADDR_DEC<3> VDD VSS / RSC_IHPSG13_INVX2 +XI2<2> addr_n<2> ADDR_DEC<2> VDD VSS / RSC_IHPSG13_INVX2 +XI2<1> addr_n<1> ADDR_DEC<1> VDD VSS / RSC_IHPSG13_INVX2 +XI2<0> addr_n<0> ADDR_DEC<0> VDD VSS / RSC_IHPSG13_INVX2 +XDFF<1> BIST_EN_I BIST_ADDR<1> ACLK_N ADDR<1> padr_int<1> net12<0> VDD ++ VSS / RSC_IHPSG13_DFNQMX2IX1 +XDFF<0> BIST_EN_I BIST_ADDR<0> ACLK_N ADDR<0> padr_int<0> net12<1> VDD ++ VSS / RSC_IHPSG13_DFNQMX2IX1 +XI15<5> VDD VSS / RSC_IHPSG13_FILLCAP4 +XI15<4> VDD VSS / RSC_IHPSG13_FILLCAP4 +XI15<3> VDD VSS / RSC_IHPSG13_FILLCAP4 +XI15<2> VDD VSS / RSC_IHPSG13_FILLCAP4 +XI15<1> VDD VSS / RSC_IHPSG13_FILLCAP4 +XI19<4> VDD VSS / RSC_IHPSG13_FILLCAP4 +XI19<3> VDD VSS / RSC_IHPSG13_FILLCAP4 +XI19<2> VDD VSS / RSC_IHPSG13_FILLCAP4 +XI19<1> VDD VSS / RSC_IHPSG13_FILLCAP4 +.ENDS +.SUBCKT RM_IHPSG13_64x32_c2_2P_COLCTRL2 A_ADDR_DEC<3> A_ADDR_DEC<2> A_ADDR_DEC<1> ++ A_ADDR_DEC<0> A_BIST_BM_I A_BIST_DW_I A_BIST_EN_I A_BLC<3> A_BLC<2> A_BLC<1> ++ A_BLC<0> A_BLT<3> A_BLT<2> A_BLT<1> A_BLT<0> A_BM_I A_DCLK_B_L A_DCLK_B_R ++ A_DCLK_L A_DCLK_R A_DR_O A_DW_I A_RCLK_B_L A_RCLK_B_R A_RCLK_L A_RCLK_R ++ A_TIEH_O A_WCLK_B_L A_WCLK_B_R A_WCLK_L A_WCLK_R B_ADDR_DEC<3> B_ADDR_DEC<2> ++ B_ADDR_DEC<1> B_ADDR_DEC<0> B_BIST_BM_I B_BIST_DW_I B_BIST_EN_I B_BLC<3> ++ B_BLC<2> B_BLC<1> B_BLC<0> B_BLT<3> B_BLT<2> B_BLT<1> B_BLT<0> B_BM_I ++ B_DCLK_B_L B_DCLK_B_R B_DCLK_L B_DCLK_R B_DR_O B_DW_I B_RCLK_B_L B_RCLK_B_R ++ B_RCLK_L B_RCLK_R B_TIEH_O B_WCLK_B_L B_WCLK_B_R B_WCLK_L B_WCLK_R VDD ++ VSS +XB_DREG B_BIST_EN_I B_BIST_DW_I B_DCLK_B_L B_DW_I B_DI_R net046 VDD ++ VSS / RSC_IHPSG13_DFNQMX2IX1 +XB_BREG B_BIST_EN_I B_BIST_BM_I B_DCLK_B_L B_BM_I B_BM_R net045 VDD ++ VSS / RSC_IHPSG13_DFNQMX2IX1 +XA_DREG A_BIST_EN_I A_BIST_DW_I A_DCLK_B_L A_DW_I A_DI_R net22 VDD VSS ++ / RSC_IHPSG13_DFNQMX2IX1 +XA_BREG A_BIST_EN_I A_BIST_BM_I A_DCLK_B_L A_BM_I A_BM_R net23 VDD VSS ++ / RSC_IHPSG13_DFNQMX2IX1 +XB_CAPS VDD VSS / RSC_IHPSG13_FILLCAP4 +XA_CAPS VDD VSS / RSC_IHPSG13_FILLCAP4 +XB_I75 B_DI_R B_DO_WRITE_P B_WR_ONE VDD VSS / RSC_IHPSG13_AND2X2 +XB_I80 B_RCLK_B_L B_WCLK_B_L net041 VDD VSS / RSC_IHPSG13_AND2X2 +XB_I76 B_DI_N B_DO_WRITE_P B_WR_ZERO VDD VSS / RSC_IHPSG13_AND2X2 +XA_I80 A_RCLK_B_L A_WCLK_B_L net21 VDD VSS / RSC_IHPSG13_AND2X2 +XA_I75 A_DI_R A_DO_WRITE_P A_WR_ONE VDD VSS / RSC_IHPSG13_AND2X2 +XA_I76 A_DI_N A_DO_WRITE_P A_WR_ZERO VDD VSS / RSC_IHPSG13_AND2X2 +XB_I44 B_WCLK_B_L B_BM_N B_DO_WRITE_P VDD VSS / RSC_IHPSG13_NOR2X2 +XA_I44 A_WCLK_B_L A_BM_N A_DO_WRITE_P VDD VSS / RSC_IHPSG13_NOR2X2 +XB_I81 net041 B_PRE_N VDD VSS / RSC_IHPSG13_CINVX4_WN +XA_I81 net21 A_PRE_N VDD VSS / RSC_IHPSG13_CINVX4_WN +XB_BM_TIEH B_TIEH_O VDD VSS / RSC_IHPSG13_TIEH +XA_BM_TIEH A_TIEH_O VDD VSS / RSC_IHPSG13_TIEH +XA_I89 A_DCLK_B_L A_DCLK_B_R / RSC_IHPSG13_MET3RES +XA_I88 A_DCLK_L A_DCLK_R / RSC_IHPSG13_MET3RES +XA_I87 A_WCLK_L A_WCLK_R / RSC_IHPSG13_MET3RES +XA_I91 A_RCLK_B_L A_RCLK_B_R / RSC_IHPSG13_MET3RES +XB_I87 B_WCLK_L B_WCLK_R / RSC_IHPSG13_MET3RES +XB_I88 B_DCLK_L B_DCLK_R / RSC_IHPSG13_MET3RES +XB_I89 B_DCLK_B_L B_DCLK_B_R / RSC_IHPSG13_MET3RES +XB_I90 B_WCLK_B_L B_WCLK_B_R / RSC_IHPSG13_MET3RES +XB_R2 B_RCLK_L B_RCLK_R / RSC_IHPSG13_MET3RES +XB_I91 B_RCLK_B_L B_RCLK_B_R / RSC_IHPSG13_MET3RES +XA_R2 A_RCLK_L A_RCLK_R / RSC_IHPSG13_MET3RES +XA_I90 A_WCLK_B_L A_WCLK_B_R / RSC_IHPSG13_MET3RES +XAB_BLMUX A_BLC<3> A_BLC<2> A_BLC<1> A_BLC<0> A_BLC_SEL A_BLT<3> A_BLT<2> ++ A_BLT<1> A_BLT<0> A_BLT_SEL A_PRE_N A_ADDR_DEC<3> A_ADDR_DEC<2> ++ A_ADDR_DEC<1> A_ADDR_DEC<0> A_WR_ONE A_WR_ZERO B_BLC<3> B_BLC<2> B_BLC<1> ++ B_BLC<0> B_BLC_SEL B_BLT<3> B_BLT<2> B_BLT<1> B_BLT<0> B_BLT_SEL B_PRE_N ++ B_ADDR_DEC<3> B_ADDR_DEC<2> B_ADDR_DEC<1> B_ADDR_DEC<0> B_WR_ONE B_WR_ZERO ++ VDD VSS / RM_IHPSG13_64x32_c2_2P_BLDRV +XB_ISENSE B_SAE B_BLC_SEL B_BLT_SEL net039 net040 VDD VSS / ++ RSC_IHPSG13_DFPQD_MSAFFX2 +XA_ISENSE A_SAE A_BLC_SEL A_BLT_SEL net19 net20 VDD VSS / ++ RSC_IHPSG13_DFPQD_MSAFFX2 +XB_I78 B_RCLK_B_L B_SAE VDD VSS / RSC_IHPSG13_CBUFX2 +XA_I78 A_RCLK_B_L A_SAE VDD VSS / RSC_IHPSG13_CBUFX2 +XB_I83 B_BM_R B_BM_N VDD VSS / RSC_IHPSG13_INVX2 +XB_I49 B_DI_R B_DI_N VDD VSS / RSC_IHPSG13_INVX2 +XA_I83 A_BM_R A_BM_N VDD VSS / RSC_IHPSG13_INVX2 +XA_I49 A_DI_R A_DI_N VDD VSS / RSC_IHPSG13_INVX2 +XB_I51 net039 B_DR_O VDD VSS / RSC_IHPSG13_INVX4 +XA_I51 net19 A_DR_O VDD VSS / RSC_IHPSG13_INVX4 +XA_I69 A_DCLK_L A_DCLK_B_L VDD VSS / RSC_IHPSG13_CINVX2 +XA_I50 A_WCLK_L A_WCLK_B_L VDD VSS / RSC_IHPSG13_CINVX2 +XA_EBUF A_RCLK_L A_RCLK_B_L VDD VSS / RSC_IHPSG13_CINVX2 +XB_EBUF B_RCLK_L B_RCLK_B_L VDD VSS / RSC_IHPSG13_CINVX2 +XB_I50 B_WCLK_L B_WCLK_B_L VDD VSS / RSC_IHPSG13_CINVX2 +XB_I69 B_DCLK_L B_DCLK_B_L VDD VSS / RSC_IHPSG13_CINVX2 +.ENDS +.SUBCKT RM_IHPSG13_64x32_c2_2P_COLDRV13_FILL4C2 VDD VSS +XI0<2> VDD VSS / RSC_IHPSG13_FILLCAP4 +XI0<1> VDD VSS / RSC_IHPSG13_FILLCAP4 +.ENDS + + +.SUBCKT RM_IHPSG13_64x32_c2_2P_ROWDEC7 ADDR_N_I<6> ADDR_N_I<5> ADDR_N_I<4> ADDR_N_I<3> ++ ADDR_N_I<2> ADDR_N_I<1> ADDR_N_I<0> CS_I ECLK_I WL_O<127> WL_O<126> ++ WL_O<125> WL_O<124> WL_O<123> WL_O<122> WL_O<121> WL_O<120> WL_O<119> ++ WL_O<118> WL_O<117> WL_O<116> WL_O<115> WL_O<114> WL_O<113> WL_O<112> ++ WL_O<111> WL_O<110> WL_O<109> WL_O<108> WL_O<107> WL_O<106> WL_O<105> ++ WL_O<104> WL_O<103> WL_O<102> WL_O<101> WL_O<100> WL_O<99> WL_O<98> WL_O<97> ++ WL_O<96> WL_O<95> WL_O<94> WL_O<93> WL_O<92> WL_O<91> WL_O<90> WL_O<89> ++ WL_O<88> WL_O<87> WL_O<86> WL_O<85> WL_O<84> WL_O<83> WL_O<82> WL_O<81> ++ WL_O<80> WL_O<79> WL_O<78> WL_O<77> WL_O<76> WL_O<75> WL_O<74> WL_O<73> ++ WL_O<72> WL_O<71> WL_O<70> WL_O<69> WL_O<68> WL_O<67> WL_O<66> WL_O<65> ++ WL_O<64> WL_O<63> WL_O<62> WL_O<61> WL_O<60> WL_O<59> WL_O<58> WL_O<57> ++ WL_O<56> WL_O<55> WL_O<54> WL_O<53> WL_O<52> WL_O<51> WL_O<50> WL_O<49> ++ WL_O<48> WL_O<47> WL_O<46> WL_O<45> WL_O<44> WL_O<43> WL_O<42> WL_O<41> ++ WL_O<40> WL_O<39> WL_O<38> WL_O<37> WL_O<36> WL_O<35> WL_O<34> WL_O<33> ++ WL_O<32> WL_O<31> WL_O<30> WL_O<29> WL_O<28> WL_O<27> WL_O<26> WL_O<25> ++ WL_O<24> WL_O<23> WL_O<22> WL_O<21> WL_O<20> WL_O<19> WL_O<18> WL_O<17> ++ WL_O<16> WL_O<15> WL_O<14> WL_O<13> WL_O<12> WL_O<11> WL_O<10> WL_O<9> ++ WL_O<8> WL_O<7> WL_O<6> WL_O<5> WL_O<4> WL_O<3> WL_O<2> WL_O<1> WL_O<0> ++ VDD VSS +XSEL<7> ADDR_N_I<3> ADDR_N_I<2> ADDR_N_I<1> ADDR_N_I<0> CS00<7> ECLK_H<7> ++ ECLK_H<8> ECLK_B<7> ECLK_B<8> WL_O<127> WL_O<126> WL_O<125> WL_O<124> ++ WL_O<123> WL_O<122> WL_O<121> WL_O<120> WL_O<119> WL_O<118> WL_O<117> ++ WL_O<116> WL_O<115> WL_O<114> WL_O<113> WL_O<112> VDD VSS / ++ RM_IHPSG13_64x32_c2_2P_DEC04 +XSEL<6> ADDR_N_I<3> ADDR_N_I<2> ADDR_N_I<1> ADDR_N_I<0> CS00<6> ECLK_H<6> ++ ECLK_H<7> ECLK_B<6> ECLK_B<7> WL_O<111> WL_O<110> WL_O<109> WL_O<108> ++ WL_O<107> WL_O<106> WL_O<105> WL_O<104> WL_O<103> WL_O<102> WL_O<101> ++ WL_O<100> WL_O<99> WL_O<98> WL_O<97> WL_O<96> VDD VSS / ++ RM_IHPSG13_64x32_c2_2P_DEC04 +XSEL<5> ADDR_N_I<3> ADDR_N_I<2> ADDR_N_I<1> ADDR_N_I<0> CS00<5> ECLK_H<5> ++ ECLK_H<6> ECLK_B<5> ECLK_B<6> WL_O<95> WL_O<94> WL_O<93> WL_O<92> WL_O<91> ++ WL_O<90> WL_O<89> WL_O<88> WL_O<87> WL_O<86> WL_O<85> WL_O<84> WL_O<83> ++ WL_O<82> WL_O<81> WL_O<80> VDD VSS / RM_IHPSG13_64x32_c2_2P_DEC04 +XSEL<4> ADDR_N_I<3> ADDR_N_I<2> ADDR_N_I<1> ADDR_N_I<0> CS00<4> ECLK_H<4> ++ ECLK_H<5> ECLK_B<4> ECLK_B<5> WL_O<79> WL_O<78> WL_O<77> WL_O<76> WL_O<75> ++ WL_O<74> WL_O<73> WL_O<72> WL_O<71> WL_O<70> WL_O<69> WL_O<68> WL_O<67> ++ WL_O<66> WL_O<65> WL_O<64> VDD VSS / RM_IHPSG13_64x32_c2_2P_DEC04 +XSEL<3> ADDR_N_I<3> ADDR_N_I<2> ADDR_N_I<1> ADDR_N_I<0> CS00<3> ECLK_H<3> ++ ECLK_H<4> ECLK_B<3> ECLK_B<4> WL_O<63> WL_O<62> WL_O<61> WL_O<60> WL_O<59> ++ WL_O<58> WL_O<57> WL_O<56> WL_O<55> WL_O<54> WL_O<53> WL_O<52> WL_O<51> ++ WL_O<50> WL_O<49> WL_O<48> VDD VSS / RM_IHPSG13_64x32_c2_2P_DEC04 +XSEL<2> ADDR_N_I<3> ADDR_N_I<2> ADDR_N_I<1> ADDR_N_I<0> CS00<2> ECLK_H<2> ++ ECLK_H<3> ECLK_B<2> ECLK_B<3> WL_O<47> WL_O<46> WL_O<45> WL_O<44> WL_O<43> ++ WL_O<42> WL_O<41> WL_O<40> WL_O<39> WL_O<38> WL_O<37> WL_O<36> WL_O<35> ++ WL_O<34> WL_O<33> WL_O<32> VDD VSS / RM_IHPSG13_64x32_c2_2P_DEC04 +XSEL<1> ADDR_N_I<3> ADDR_N_I<2> ADDR_N_I<1> ADDR_N_I<0> CS00<1> ECLK_H<1> ++ ECLK_H<2> ECLK_B<1> ECLK_B<2> WL_O<31> WL_O<30> WL_O<29> WL_O<28> WL_O<27> ++ WL_O<26> WL_O<25> WL_O<24> WL_O<23> WL_O<22> WL_O<21> WL_O<20> WL_O<19> ++ WL_O<18> WL_O<17> WL_O<16> VDD VSS / RM_IHPSG13_64x32_c2_2P_DEC04 +XSEL<0> ADDR_N_I<3> ADDR_N_I<2> ADDR_N_I<1> ADDR_N_I<0> CS00<0> ECLK_I ++ ECLK_H<1> ECLK_B<0> ECLK_B<1> WL_O<15> WL_O<14> WL_O<13> WL_O<12> WL_O<11> ++ WL_O<10> WL_O<9> WL_O<8> WL_O<7> WL_O<6> WL_O<5> WL_O<4> WL_O<3> WL_O<2> ++ WL_O<1> WL_O<0> VDD VSS / RM_IHPSG13_64x32_c2_2P_DEC04 +XDEC11<1> ADDR_N_I<5> ADDR_N_I<4> CS04<1> CS00<7> VDD VSS / ++ RM_IHPSG13_64x32_c2_2P_DEC03 +XDEC11<0> ADDR_N_I<5> ADDR_N_I<4> CS04<0> CS00<3> VDD VSS / ++ RM_IHPSG13_64x32_c2_2P_DEC03 +XDEC01<2> ADDR_N_I<7> ADDR_N_I<6> CS_I CS04<1> VDD VSS / ++ RM_IHPSG13_64x32_c2_2P_DEC01 +XDEC01<1> ADDR_N_I<5> ADDR_N_I<4> CS04<1> CS00<5> VDD VSS / ++ RM_IHPSG13_64x32_c2_2P_DEC01 +XDEC01<0> ADDR_N_I<5> ADDR_N_I<4> CS04<0> CS00<1> VDD VSS / ++ RM_IHPSG13_64x32_c2_2P_DEC01 +XL2<66> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<65> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<64> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<63> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<62> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<61> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<60> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<59> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<58> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<57> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<56> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<55> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<54> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<53> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<52> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<51> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<50> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<49> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<48> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<47> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<46> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<45> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<44> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<43> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<42> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<41> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<40> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<39> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<38> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<37> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<36> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<35> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<34> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<33> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<32> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<31> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<30> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<29> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<28> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<27> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<26> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<25> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<24> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<23> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<22> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<21> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<20> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<19> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<18> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<17> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<16> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<15> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<14> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<13> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<12> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<11> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<10> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<9> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<8> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<7> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<6> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<5> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<4> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<3> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<2> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<1> VDD VSS / RSC_IHPSG13_FILLCAP8 +XDEC10<1> ADDR_N_I<5> ADDR_N_I<4> CS04<1> CS00<6> VDD VSS / ++ RM_IHPSG13_64x32_c2_2P_DEC02 +XDEC10<0> ADDR_N_I<5> ADDR_N_I<4> CS04<0> CS00<2> VDD VSS / ++ RM_IHPSG13_64x32_c2_2P_DEC02 +XDEC00<2> ADDR_N_I<7> ADDR_N_I<6> CS_I CS04<0> VDD VSS / ++ RM_IHPSG13_64x32_c2_2P_DEC00 +XDEC00<1> ADDR_N_I<5> ADDR_N_I<4> CS04<1> CS00<4> VDD VSS / ++ RM_IHPSG13_64x32_c2_2P_DEC00 +XDEC00<0> ADDR_N_I<5> ADDR_N_I<4> CS04<0> CS00<0> VDD VSS / ++ RM_IHPSG13_64x32_c2_2P_DEC00 +XI0 ADDR_N_I<7> VDD VSS / RSC_IHPSG13_TIEL +.ENDS +.SUBCKT RM_IHPSG13_64x32_c2_2P_ROWREG7 ACLK_N_I ADDR_I<6> ADDR_I<5> ADDR_I<4> ADDR_I<3> ++ ADDR_I<2> ADDR_I<1> ADDR_I<0> ADDR_N_O<6> ADDR_N_O<5> ADDR_N_O<4> ++ ADDR_N_O<3> ADDR_N_O<2> ADDR_N_O<1> ADDR_N_O<0> BIST_ADDR_I<6> ++ BIST_ADDR_I<5> BIST_ADDR_I<4> BIST_ADDR_I<3> BIST_ADDR_I<2> BIST_ADDR_I<1> ++ BIST_ADDR_I<0> BIST_EN_I VDD VSS +XINV<6> q_int<6> qn_int<6> VDD VSS / RSC_IHPSG13_CINVX2 +XINV<5> q_int<5> qn_int<5> VDD VSS / RSC_IHPSG13_CINVX2 +XINV<4> q_int<4> qn_int<4> VDD VSS / RSC_IHPSG13_CINVX2 +XINV<3> q_int<3> qn_int<3> VDD VSS / RSC_IHPSG13_CINVX2 +XINV<2> q_int<2> qn_int<2> VDD VSS / RSC_IHPSG13_CINVX2 +XINV<1> q_int<1> qn_int<1> VDD VSS / RSC_IHPSG13_CINVX2 +XINV<0> q_int<0> qn_int<0> VDD VSS / RSC_IHPSG13_CINVX2 +XDRV<6> qn_int<6> ADDR_N_O<6> VDD VSS / RSC_IHPSG13_CINVX8 +XDRV<5> qn_int<5> ADDR_N_O<5> VDD VSS / RSC_IHPSG13_CINVX8 +XDRV<4> qn_int<4> ADDR_N_O<4> VDD VSS / RSC_IHPSG13_CINVX8 +XDRV<3> qn_int<3> ADDR_N_O<3> VDD VSS / RSC_IHPSG13_CINVX8 +XDRV<2> qn_int<2> ADDR_N_O<2> VDD VSS / RSC_IHPSG13_CINVX8 +XDRV<1> qn_int<1> ADDR_N_O<1> VDD VSS / RSC_IHPSG13_CINVX8 +XDRV<0> qn_int<0> ADDR_N_O<0> VDD VSS / RSC_IHPSG13_CINVX8 +XDFF<6> BIST_EN_I BIST_ADDR_I<6> ACLK_N_I ADDR_I<6> q_int<6> net2<0> VDD ++ VSS / RSC_IHPSG13_DFNQMX2IX1 +XDFF<5> BIST_EN_I BIST_ADDR_I<5> ACLK_N_I ADDR_I<5> q_int<5> net2<1> VDD ++ VSS / RSC_IHPSG13_DFNQMX2IX1 +XDFF<4> BIST_EN_I BIST_ADDR_I<4> ACLK_N_I ADDR_I<4> q_int<4> net2<2> VDD ++ VSS / RSC_IHPSG13_DFNQMX2IX1 +XDFF<3> BIST_EN_I BIST_ADDR_I<3> ACLK_N_I ADDR_I<3> q_int<3> net2<3> VDD ++ VSS / RSC_IHPSG13_DFNQMX2IX1 +XDFF<2> BIST_EN_I BIST_ADDR_I<2> ACLK_N_I ADDR_I<2> q_int<2> net2<4> VDD ++ VSS / RSC_IHPSG13_DFNQMX2IX1 +XDFF<1> BIST_EN_I BIST_ADDR_I<1> ACLK_N_I ADDR_I<1> q_int<1> net2<5> VDD ++ VSS / RSC_IHPSG13_DFNQMX2IX1 +XDFF<0> BIST_EN_I BIST_ADDR_I<0> ACLK_N_I ADDR_I<0> q_int<0> net2<6> VDD ++ VSS / RSC_IHPSG13_DFNQMX2IX1 +XI11<7> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI11<6> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI11<5> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI11<4> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI11<3> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI11<2> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI11<1> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI11<0> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI12<1> VDD VSS / RSC_IHPSG13_FILLCAP4 +XI12<0> VDD VSS / RSC_IHPSG13_FILLCAP4 +.ENDS + +.SUBCKT RM_IHPSG13_64x32_c2_2P_ROWDEC4 ADDR_N_I<3> ADDR_N_I<2> ADDR_N_I<1> ADDR_N_I<0> ++ CS_I ECLK_I WL_O<15> WL_O<14> WL_O<13> WL_O<12> WL_O<11> WL_O<10> WL_O<9> ++ WL_O<8> WL_O<7> WL_O<6> WL_O<5> WL_O<4> WL_O<3> WL_O<2> WL_O<1> WL_O<0> ++ VDD VSS +XL2<12> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<11> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<10> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<9> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<8> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<7> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<6> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<5> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<4> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<3> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<2> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<1> VDD VSS / RSC_IHPSG13_FILLCAP8 +XSEL ADDR_N_I<3> ADDR_N_I<2> ADDR_N_I<1> ADDR_N_I<0> CS_I ECLK_I ECLK_H<1> ++ ECLK_B<0> ECLK_B<1> WL_O<15> WL_O<14> WL_O<13> WL_O<12> WL_O<11> WL_O<10> ++ WL_O<9> WL_O<8> WL_O<7> WL_O<6> WL_O<5> WL_O<4> WL_O<3> WL_O<2> WL_O<1> ++ WL_O<0> VDD VSS / RM_IHPSG13_64x32_c2_2P_DEC04 +.ENDS +.SUBCKT RM_IHPSG13_64x32_c2_2P_ROWREG4 ACLK_N_I ADDR_I<3> ADDR_I<2> ADDR_I<1> ADDR_I<0> ++ ADDR_N_O<3> ADDR_N_O<2> ADDR_N_O<1> ADDR_N_O<0> BIST_ADDR_I<3> ++ BIST_ADDR_I<2> BIST_ADDR_I<1> BIST_ADDR_I<0> BIST_EN_I VDD VSS +XINV<3> q_int<3> qn_int<3> VDD VSS / RSC_IHPSG13_CINVX2 +XINV<2> q_int<2> qn_int<2> VDD VSS / RSC_IHPSG13_CINVX2 +XINV<1> q_int<1> qn_int<1> VDD VSS / RSC_IHPSG13_CINVX2 +XINV<0> q_int<0> qn_int<0> VDD VSS / RSC_IHPSG13_CINVX2 +XDRV<3> qn_int<3> ADDR_N_O<3> VDD VSS / RSC_IHPSG13_CINVX8 +XDRV<2> qn_int<2> ADDR_N_O<2> VDD VSS / RSC_IHPSG13_CINVX8 +XDRV<1> qn_int<1> ADDR_N_O<1> VDD VSS / RSC_IHPSG13_CINVX8 +XDRV<0> qn_int<0> ADDR_N_O<0> VDD VSS / RSC_IHPSG13_CINVX8 +XDFF<3> BIST_EN_I BIST_ADDR_I<3> ACLK_N_I ADDR_I<3> q_int<3> net7<0> VDD ++ VSS / RSC_IHPSG13_DFNQMX2IX1 +XDFF<2> BIST_EN_I BIST_ADDR_I<2> ACLK_N_I ADDR_I<2> q_int<2> net7<1> VDD ++ VSS / RSC_IHPSG13_DFNQMX2IX1 +XDFF<1> BIST_EN_I BIST_ADDR_I<1> ACLK_N_I ADDR_I<1> q_int<1> net7<2> VDD ++ VSS / RSC_IHPSG13_DFNQMX2IX1 +XDFF<0> BIST_EN_I BIST_ADDR_I<0> ACLK_N_I ADDR_I<0> q_int<0> net7<3> VDD ++ VSS / RSC_IHPSG13_DFNQMX2IX1 +XI11<20> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI11<19> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI11<18> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI11<17> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI11<16> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI11<15> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI11<14> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI11<13> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI11<12> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI11<11> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI11<10> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI11<9> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI11<8> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI11<7> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI11<6> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI11<5> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI11<4> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI11<3> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI11<2> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI11<1> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI12<4> VDD VSS / RSC_IHPSG13_FILLCAP4 +XI12<3> VDD VSS / RSC_IHPSG13_FILLCAP4 +XI12<2> VDD VSS / RSC_IHPSG13_FILLCAP4 +XI12<1> VDD VSS / RSC_IHPSG13_FILLCAP4 +XI12<0> VDD VSS / RSC_IHPSG13_FILLCAP4 +.ENDS + + +.SUBCKT RM_IHPSG13_64x32_c2_1P_BITKIT_TAP BLC BLT NW PW VDD VSS +.ENDS +.SUBCKT RM_IHPSG13_64x32_c2_1P_BITKIT_16x2_TAP A_BLC<1> A_BLC<0> A_BLT<1> A_BLT<0> ++ VDD_CORE VSS +XITAP<1> A_BLC<1> A_BLT<1> VDD_CORE VSS VDD_CORE VSS ++ / RM_IHPSG13_64x32_c2_1P_BITKIT_TAP +XITAP<0> A_BLC<0> A_BLT<0> VDD_CORE VSS VDD_CORE VSS ++ / RM_IHPSG13_64x32_c2_1P_BITKIT_TAP +XIEDGEBP_COL1<1> BLC<1> BLT<1> VDD_CORE VSS VDD_CORE ++ VSS / RM_IHPSG13_64x32_c2_1P_BITKIT_EDGE_TB +XIEDGEBP_COL1<0> BLC<1> BLT<1> VDD_CORE VSS VDD_CORE ++ VSS / RM_IHPSG13_64x32_c2_1P_BITKIT_EDGE_TB +XIEDGEBP_COL2<1> BLC<0> BLT<0> VDD_CORE VSS VDD_CORE ++ VSS / RM_IHPSG13_64x32_c2_1P_BITKIT_EDGE_TB +XIEDGEBP_COL2<0> BLC<0> BLT<0> VDD_CORE VSS VDD_CORE ++ VSS / RM_IHPSG13_64x32_c2_1P_BITKIT_EDGE_TB +.ENDS +.SUBCKT RM_IHPSG13_64x32_c2_1P_BITKIT_16x2_TAP_LR VDD_CORE VSS +XCORNER<1> VDD_CORE VSS VDD_CORE VSS / ++ RM_IHPSG13_64x32_c2_1P_BITKIT_CORNER +XCORNER<0> VDD_CORE VSS VDD_CORE VSS / ++ RM_IHPSG13_64x32_c2_1P_BITKIT_CORNER +XTAP_BORDER VDD_CORE VSS VDD_CORE VSS / ++ RM_IHPSG13_64x32_c2_1P_BITKIT_TAP_LR +.ENDS +.SUBCKT RM_IHPSG13_64x32_c2_1P_DEC03 ADDR<1> ADDR<0> CS CS_OUT VDD VSS +XDECINV net1 CS_OUT VDD VSS / RSC_IHPSG13_INVX4 +XI0 VDD VSS / RSC_IHPSG13_FILLCAP4 +XDEC ADDR<1> ADDR<0> CS net1 VDD VSS / RSC_IHPSG13_NAND3X2 +.ENDS +.SUBCKT RM_IHPSG13_64x32_c2_1P_DEC02 ADDR<1> ADDR<0> CS CS_OUT VDD VSS +XDECINV net1 CS_OUT VDD VSS / RSC_IHPSG13_INVX4 +XDEC ADDR<1> NADDR<0> CS net1 VDD VSS / RSC_IHPSG13_NAND3X2 +XI2 VDD VSS / RSC_IHPSG13_FILLCAP4 +XADDRINV ADDR<0> NADDR<0> VDD VSS / RSC_IHPSG13_INVX2 +.ENDS +.SUBCKT RM_IHPSG13_64x32_c2_1P_ROWDEC8 ADDR_N_I<7> ADDR_N_I<6> ADDR_N_I<5> ADDR_N_I<4> ++ ADDR_N_I<3> ADDR_N_I<2> ADDR_N_I<1> ADDR_N_I<0> CS_I ECLK_I WL_O<255> ++ WL_O<254> WL_O<253> WL_O<252> WL_O<251> WL_O<250> WL_O<249> WL_O<248> ++ WL_O<247> WL_O<246> WL_O<245> WL_O<244> WL_O<243> WL_O<242> WL_O<241> ++ WL_O<240> WL_O<239> WL_O<238> WL_O<237> WL_O<236> WL_O<235> WL_O<234> ++ WL_O<233> WL_O<232> WL_O<231> WL_O<230> WL_O<229> WL_O<228> WL_O<227> ++ WL_O<226> WL_O<225> WL_O<224> WL_O<223> WL_O<222> WL_O<221> WL_O<220> ++ WL_O<219> WL_O<218> WL_O<217> WL_O<216> WL_O<215> WL_O<214> WL_O<213> ++ WL_O<212> WL_O<211> WL_O<210> WL_O<209> WL_O<208> WL_O<207> WL_O<206> ++ WL_O<205> WL_O<204> WL_O<203> WL_O<202> WL_O<201> WL_O<200> WL_O<199> ++ WL_O<198> WL_O<197> WL_O<196> WL_O<195> WL_O<194> WL_O<193> WL_O<192> ++ WL_O<191> WL_O<190> WL_O<189> WL_O<188> WL_O<187> WL_O<186> WL_O<185> ++ WL_O<184> WL_O<183> WL_O<182> WL_O<181> WL_O<180> WL_O<179> WL_O<178> ++ WL_O<177> WL_O<176> WL_O<175> WL_O<174> WL_O<173> WL_O<172> WL_O<171> ++ WL_O<170> WL_O<169> WL_O<168> WL_O<167> WL_O<166> WL_O<165> WL_O<164> ++ WL_O<163> WL_O<162> WL_O<161> WL_O<160> WL_O<159> WL_O<158> WL_O<157> ++ WL_O<156> WL_O<155> WL_O<154> WL_O<153> WL_O<152> WL_O<151> WL_O<150> ++ WL_O<149> WL_O<148> WL_O<147> WL_O<146> WL_O<145> WL_O<144> WL_O<143> ++ WL_O<142> WL_O<141> WL_O<140> WL_O<139> WL_O<138> WL_O<137> WL_O<136> ++ WL_O<135> WL_O<134> WL_O<133> WL_O<132> WL_O<131> WL_O<130> WL_O<129> ++ WL_O<128> WL_O<127> WL_O<126> WL_O<125> WL_O<124> WL_O<123> WL_O<122> ++ WL_O<121> WL_O<120> WL_O<119> WL_O<118> WL_O<117> WL_O<116> WL_O<115> ++ WL_O<114> WL_O<113> WL_O<112> WL_O<111> WL_O<110> WL_O<109> WL_O<108> ++ WL_O<107> WL_O<106> WL_O<105> WL_O<104> WL_O<103> WL_O<102> WL_O<101> ++ WL_O<100> WL_O<99> WL_O<98> WL_O<97> WL_O<96> WL_O<95> WL_O<94> WL_O<93> ++ WL_O<92> WL_O<91> WL_O<90> WL_O<89> WL_O<88> WL_O<87> WL_O<86> WL_O<85> ++ WL_O<84> WL_O<83> WL_O<82> WL_O<81> WL_O<80> WL_O<79> WL_O<78> WL_O<77> ++ WL_O<76> WL_O<75> WL_O<74> WL_O<73> WL_O<72> WL_O<71> WL_O<70> WL_O<69> ++ WL_O<68> WL_O<67> WL_O<66> WL_O<65> WL_O<64> WL_O<63> WL_O<62> WL_O<61> ++ WL_O<60> WL_O<59> WL_O<58> WL_O<57> WL_O<56> WL_O<55> WL_O<54> WL_O<53> ++ WL_O<52> WL_O<51> WL_O<50> WL_O<49> WL_O<48> WL_O<47> WL_O<46> WL_O<45> ++ WL_O<44> WL_O<43> WL_O<42> WL_O<41> WL_O<40> WL_O<39> WL_O<38> WL_O<37> ++ WL_O<36> WL_O<35> WL_O<34> WL_O<33> WL_O<32> WL_O<31> WL_O<30> WL_O<29> ++ WL_O<28> WL_O<27> WL_O<26> WL_O<25> WL_O<24> WL_O<23> WL_O<22> WL_O<21> ++ WL_O<20> WL_O<19> WL_O<18> WL_O<17> WL_O<16> WL_O<15> WL_O<14> WL_O<13> ++ WL_O<12> WL_O<11> WL_O<10> WL_O<9> WL_O<8> WL_O<7> WL_O<6> WL_O<5> WL_O<4> ++ WL_O<3> WL_O<2> WL_O<1> WL_O<0> VDD VSS +XDEC11<4> ADDR_N_I<7> ADDR_N_I<6> CS_I CS04<3> VDD VSS / ++ RM_IHPSG13_64x32_c2_1P_DEC03 +XDEC11<3> ADDR_N_I<5> ADDR_N_I<4> CS04<3> CS00<15> VDD VSS / ++ RM_IHPSG13_64x32_c2_1P_DEC03 +XDEC11<2> ADDR_N_I<5> ADDR_N_I<4> CS04<2> CS00<11> VDD VSS / ++ RM_IHPSG13_64x32_c2_1P_DEC03 +XDEC11<1> ADDR_N_I<5> ADDR_N_I<4> CS04<1> CS00<7> VDD VSS / ++ RM_IHPSG13_64x32_c2_1P_DEC03 +XDEC11<0> ADDR_N_I<5> ADDR_N_I<4> CS04<0> CS00<3> VDD VSS / ++ RM_IHPSG13_64x32_c2_1P_DEC03 +XL2<88> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<87> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<86> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<85> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<84> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<83> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<82> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<81> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<80> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<79> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<78> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<77> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<76> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<75> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<74> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<73> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<72> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<71> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<70> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<69> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<68> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<67> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<66> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<65> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<64> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<63> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<62> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<61> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<60> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<59> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<58> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<57> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<56> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<55> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<54> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<53> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<52> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<51> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<50> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<49> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<48> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<47> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<46> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<45> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<44> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<43> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<42> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<41> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<40> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<39> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<38> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<37> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<36> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<35> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<34> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<33> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<32> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<31> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<30> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<29> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<28> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<27> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<26> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<25> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<24> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<23> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<22> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<21> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<20> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<19> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<18> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<17> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<16> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<15> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<14> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<13> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<12> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<11> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<10> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<9> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<8> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<7> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<6> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<5> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<4> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<3> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<2> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<1> VDD VSS / RSC_IHPSG13_FILLCAP8 +XDEC10<4> ADDR_N_I<7> ADDR_N_I<6> CS_I CS04<2> VDD VSS / ++ RM_IHPSG13_64x32_c2_1P_DEC02 +XDEC10<3> ADDR_N_I<5> ADDR_N_I<4> CS04<3> CS00<14> VDD VSS / ++ RM_IHPSG13_64x32_c2_1P_DEC02 +XDEC10<2> ADDR_N_I<5> ADDR_N_I<4> CS04<2> CS00<10> VDD VSS / ++ RM_IHPSG13_64x32_c2_1P_DEC02 +XDEC10<1> ADDR_N_I<5> ADDR_N_I<4> CS04<1> CS00<6> VDD VSS / ++ RM_IHPSG13_64x32_c2_1P_DEC02 +XDEC10<0> ADDR_N_I<5> ADDR_N_I<4> CS04<0> CS00<2> VDD VSS / ++ RM_IHPSG13_64x32_c2_1P_DEC02 +XDEC00<4> ADDR_N_I<7> ADDR_N_I<6> CS_I CS04<0> VDD VSS / ++ RM_IHPSG13_64x32_c2_1P_DEC00 +XDEC00<3> ADDR_N_I<5> ADDR_N_I<4> CS04<3> CS00<12> VDD VSS / ++ RM_IHPSG13_64x32_c2_1P_DEC00 +XDEC00<2> ADDR_N_I<5> ADDR_N_I<4> CS04<2> CS00<8> VDD VSS / ++ RM_IHPSG13_64x32_c2_1P_DEC00 +XDEC00<1> ADDR_N_I<5> ADDR_N_I<4> CS04<1> CS00<4> VDD VSS / ++ RM_IHPSG13_64x32_c2_1P_DEC00 +XDEC00<0> ADDR_N_I<5> ADDR_N_I<4> CS04<0> CS00<0> VDD VSS / ++ RM_IHPSG13_64x32_c2_1P_DEC00 +XSEL<15> ADDR_N_I<3> ADDR_N_I<2> ADDR_N_I<1> ADDR_N_I<0> CS00<15> ECLK_H<15> ++ ECLK_H<16> ECLK_B<15> ECLK_B<16> WL_O<255> WL_O<254> WL_O<253> WL_O<252> ++ WL_O<251> WL_O<250> WL_O<249> WL_O<248> WL_O<247> WL_O<246> WL_O<245> ++ WL_O<244> WL_O<243> WL_O<242> WL_O<241> WL_O<240> VDD VSS / ++ RM_IHPSG13_64x32_c2_1P_DEC04 +XSEL<14> ADDR_N_I<3> ADDR_N_I<2> ADDR_N_I<1> ADDR_N_I<0> CS00<14> ECLK_H<14> ++ ECLK_H<15> ECLK_B<14> ECLK_B<15> WL_O<239> WL_O<238> WL_O<237> WL_O<236> ++ WL_O<235> WL_O<234> WL_O<233> WL_O<232> WL_O<231> WL_O<230> WL_O<229> ++ WL_O<228> WL_O<227> WL_O<226> WL_O<225> WL_O<224> VDD VSS / ++ RM_IHPSG13_64x32_c2_1P_DEC04 +XSEL<13> ADDR_N_I<3> ADDR_N_I<2> ADDR_N_I<1> ADDR_N_I<0> CS00<13> ECLK_H<13> ++ ECLK_H<14> ECLK_B<13> ECLK_B<14> WL_O<223> WL_O<222> WL_O<221> WL_O<220> ++ WL_O<219> WL_O<218> WL_O<217> WL_O<216> WL_O<215> WL_O<214> WL_O<213> ++ WL_O<212> WL_O<211> WL_O<210> WL_O<209> WL_O<208> VDD VSS / ++ RM_IHPSG13_64x32_c2_1P_DEC04 +XSEL<12> ADDR_N_I<3> ADDR_N_I<2> ADDR_N_I<1> ADDR_N_I<0> CS00<12> ECLK_H<12> ++ ECLK_H<13> ECLK_B<12> ECLK_B<13> WL_O<207> WL_O<206> WL_O<205> WL_O<204> ++ WL_O<203> WL_O<202> WL_O<201> WL_O<200> WL_O<199> WL_O<198> WL_O<197> ++ WL_O<196> WL_O<195> WL_O<194> WL_O<193> WL_O<192> VDD VSS / ++ RM_IHPSG13_64x32_c2_1P_DEC04 +XSEL<11> ADDR_N_I<3> ADDR_N_I<2> ADDR_N_I<1> ADDR_N_I<0> CS00<11> ECLK_H<11> ++ ECLK_H<12> ECLK_B<11> ECLK_B<12> WL_O<191> WL_O<190> WL_O<189> WL_O<188> ++ WL_O<187> WL_O<186> WL_O<185> WL_O<184> WL_O<183> WL_O<182> WL_O<181> ++ WL_O<180> WL_O<179> WL_O<178> WL_O<177> WL_O<176> VDD VSS / ++ RM_IHPSG13_64x32_c2_1P_DEC04 +XSEL<10> ADDR_N_I<3> ADDR_N_I<2> ADDR_N_I<1> ADDR_N_I<0> CS00<10> ECLK_H<10> ++ ECLK_H<11> ECLK_B<10> ECLK_B<11> WL_O<175> WL_O<174> WL_O<173> WL_O<172> ++ WL_O<171> WL_O<170> WL_O<169> WL_O<168> WL_O<167> WL_O<166> WL_O<165> ++ WL_O<164> WL_O<163> WL_O<162> WL_O<161> WL_O<160> VDD VSS / ++ RM_IHPSG13_64x32_c2_1P_DEC04 +XSEL<9> ADDR_N_I<3> ADDR_N_I<2> ADDR_N_I<1> ADDR_N_I<0> CS00<9> ECLK_H<9> ++ ECLK_H<10> ECLK_B<9> ECLK_B<10> WL_O<159> WL_O<158> WL_O<157> WL_O<156> ++ WL_O<155> WL_O<154> WL_O<153> WL_O<152> WL_O<151> WL_O<150> WL_O<149> ++ WL_O<148> WL_O<147> WL_O<146> WL_O<145> WL_O<144> VDD VSS / ++ RM_IHPSG13_64x32_c2_1P_DEC04 +XSEL<8> ADDR_N_I<3> ADDR_N_I<2> ADDR_N_I<1> ADDR_N_I<0> CS00<8> ECLK_H<8> ++ ECLK_H<9> ECLK_B<8> ECLK_B<9> WL_O<143> WL_O<142> WL_O<141> WL_O<140> ++ WL_O<139> WL_O<138> WL_O<137> WL_O<136> WL_O<135> WL_O<134> WL_O<133> ++ WL_O<132> WL_O<131> WL_O<130> WL_O<129> WL_O<128> VDD VSS / ++ RM_IHPSG13_64x32_c2_1P_DEC04 +XSEL<7> ADDR_N_I<3> ADDR_N_I<2> ADDR_N_I<1> ADDR_N_I<0> CS00<7> ECLK_H<7> ++ ECLK_H<8> ECLK_B<7> ECLK_B<8> WL_O<127> WL_O<126> WL_O<125> WL_O<124> ++ WL_O<123> WL_O<122> WL_O<121> WL_O<120> WL_O<119> WL_O<118> WL_O<117> ++ WL_O<116> WL_O<115> WL_O<114> WL_O<113> WL_O<112> VDD VSS / ++ RM_IHPSG13_64x32_c2_1P_DEC04 +XSEL<6> ADDR_N_I<3> ADDR_N_I<2> ADDR_N_I<1> ADDR_N_I<0> CS00<6> ECLK_H<6> ++ ECLK_H<7> ECLK_B<6> ECLK_B<7> WL_O<111> WL_O<110> WL_O<109> WL_O<108> ++ WL_O<107> WL_O<106> WL_O<105> WL_O<104> WL_O<103> WL_O<102> WL_O<101> ++ WL_O<100> WL_O<99> WL_O<98> WL_O<97> WL_O<96> VDD VSS / ++ RM_IHPSG13_64x32_c2_1P_DEC04 +XSEL<5> ADDR_N_I<3> ADDR_N_I<2> ADDR_N_I<1> ADDR_N_I<0> CS00<5> ECLK_H<5> ++ ECLK_H<6> ECLK_B<5> ECLK_B<6> WL_O<95> WL_O<94> WL_O<93> WL_O<92> WL_O<91> ++ WL_O<90> WL_O<89> WL_O<88> WL_O<87> WL_O<86> WL_O<85> WL_O<84> WL_O<83> ++ WL_O<82> WL_O<81> WL_O<80> VDD VSS / RM_IHPSG13_64x32_c2_1P_DEC04 +XSEL<4> ADDR_N_I<3> ADDR_N_I<2> ADDR_N_I<1> ADDR_N_I<0> CS00<4> ECLK_H<4> ++ ECLK_H<5> ECLK_B<4> ECLK_B<5> WL_O<79> WL_O<78> WL_O<77> WL_O<76> WL_O<75> ++ WL_O<74> WL_O<73> WL_O<72> WL_O<71> WL_O<70> WL_O<69> WL_O<68> WL_O<67> ++ WL_O<66> WL_O<65> WL_O<64> VDD VSS / RM_IHPSG13_64x32_c2_1P_DEC04 +XSEL<3> ADDR_N_I<3> ADDR_N_I<2> ADDR_N_I<1> ADDR_N_I<0> CS00<3> ECLK_H<3> ++ ECLK_H<4> ECLK_B<3> ECLK_B<4> WL_O<63> WL_O<62> WL_O<61> WL_O<60> WL_O<59> ++ WL_O<58> WL_O<57> WL_O<56> WL_O<55> WL_O<54> WL_O<53> WL_O<52> WL_O<51> ++ WL_O<50> WL_O<49> WL_O<48> VDD VSS / RM_IHPSG13_64x32_c2_1P_DEC04 +XSEL<2> ADDR_N_I<3> ADDR_N_I<2> ADDR_N_I<1> ADDR_N_I<0> CS00<2> ECLK_H<2> ++ ECLK_H<3> ECLK_B<2> ECLK_B<3> WL_O<47> WL_O<46> WL_O<45> WL_O<44> WL_O<43> ++ WL_O<42> WL_O<41> WL_O<40> WL_O<39> WL_O<38> WL_O<37> WL_O<36> WL_O<35> ++ WL_O<34> WL_O<33> WL_O<32> VDD VSS / RM_IHPSG13_64x32_c2_1P_DEC04 +XSEL<1> ADDR_N_I<3> ADDR_N_I<2> ADDR_N_I<1> ADDR_N_I<0> CS00<1> ECLK_H<1> ++ ECLK_H<2> ECLK_B<1> ECLK_B<2> WL_O<31> WL_O<30> WL_O<29> WL_O<28> WL_O<27> ++ WL_O<26> WL_O<25> WL_O<24> WL_O<23> WL_O<22> WL_O<21> WL_O<20> WL_O<19> ++ WL_O<18> WL_O<17> WL_O<16> VDD VSS / RM_IHPSG13_64x32_c2_1P_DEC04 +XSEL<0> ADDR_N_I<3> ADDR_N_I<2> ADDR_N_I<1> ADDR_N_I<0> CS00<0> ECLK_I ++ ECLK_H<1> ECLK_B<0> ECLK_B<1> WL_O<15> WL_O<14> WL_O<13> WL_O<12> WL_O<11> ++ WL_O<10> WL_O<9> WL_O<8> WL_O<7> WL_O<6> WL_O<5> WL_O<4> WL_O<3> WL_O<2> ++ WL_O<1> WL_O<0> VDD VSS / RM_IHPSG13_64x32_c2_1P_DEC04 +XDEC01<4> ADDR_N_I<7> ADDR_N_I<6> CS_I CS04<1> VDD VSS / ++ RM_IHPSG13_64x32_c2_1P_DEC01 +XDEC01<3> ADDR_N_I<5> ADDR_N_I<4> CS04<3> CS00<13> VDD VSS / ++ RM_IHPSG13_64x32_c2_1P_DEC01 +XDEC01<2> ADDR_N_I<5> ADDR_N_I<4> CS04<2> CS00<9> VDD VSS / ++ RM_IHPSG13_64x32_c2_1P_DEC01 +XDEC01<1> ADDR_N_I<5> ADDR_N_I<4> CS04<1> CS00<5> VDD VSS / ++ RM_IHPSG13_64x32_c2_1P_DEC01 +XDEC01<0> ADDR_N_I<5> ADDR_N_I<4> CS04<0> CS00<1> VDD VSS / ++ RM_IHPSG13_64x32_c2_1P_DEC01 +.ENDS +.SUBCKT RM_IHPSG13_64x32_c2_1P_ROWREG8 ACLK_N_I ADDR_I<7> ADDR_I<6> ADDR_I<5> ADDR_I<4> ++ ADDR_I<3> ADDR_I<2> ADDR_I<1> ADDR_I<0> ADDR_N_O<7> ADDR_N_O<6> ADDR_N_O<5> ++ ADDR_N_O<4> ADDR_N_O<3> ADDR_N_O<2> ADDR_N_O<1> ADDR_N_O<0> BIST_ADDR_I<7> ++ BIST_ADDR_I<6> BIST_ADDR_I<5> BIST_ADDR_I<4> BIST_ADDR_I<3> BIST_ADDR_I<2> ++ BIST_ADDR_I<1> BIST_ADDR_I<0> BIST_EN_I VDD VSS +XINV<7> q_int<7> qn_int<7> VDD VSS / RSC_IHPSG13_CINVX2 +XINV<6> q_int<6> qn_int<6> VDD VSS / RSC_IHPSG13_CINVX2 +XINV<5> q_int<5> qn_int<5> VDD VSS / RSC_IHPSG13_CINVX2 +XINV<4> q_int<4> qn_int<4> VDD VSS / RSC_IHPSG13_CINVX2 +XINV<3> q_int<3> qn_int<3> VDD VSS / RSC_IHPSG13_CINVX2 +XINV<2> q_int<2> qn_int<2> VDD VSS / RSC_IHPSG13_CINVX2 +XINV<1> q_int<1> qn_int<1> VDD VSS / RSC_IHPSG13_CINVX2 +XINV<0> q_int<0> qn_int<0> VDD VSS / RSC_IHPSG13_CINVX2 +XDRV<7> qn_int<7> ADDR_N_O<7> VDD VSS / RSC_IHPSG13_CINVX8 +XDRV<6> qn_int<6> ADDR_N_O<6> VDD VSS / RSC_IHPSG13_CINVX8 +XDRV<5> qn_int<5> ADDR_N_O<5> VDD VSS / RSC_IHPSG13_CINVX8 +XDRV<4> qn_int<4> ADDR_N_O<4> VDD VSS / RSC_IHPSG13_CINVX8 +XDRV<3> qn_int<3> ADDR_N_O<3> VDD VSS / RSC_IHPSG13_CINVX8 +XDRV<2> qn_int<2> ADDR_N_O<2> VDD VSS / RSC_IHPSG13_CINVX8 +XDRV<1> qn_int<1> ADDR_N_O<1> VDD VSS / RSC_IHPSG13_CINVX8 +XDRV<0> qn_int<0> ADDR_N_O<0> VDD VSS / RSC_IHPSG13_CINVX8 +XDFF<7> BIST_EN_I BIST_ADDR_I<7> ACLK_N_I ADDR_I<7> q_int<7> net2<0> VDD ++ VSS / RSC_IHPSG13_DFNQMX2IX1 +XDFF<6> BIST_EN_I BIST_ADDR_I<6> ACLK_N_I ADDR_I<6> q_int<6> net2<1> VDD ++ VSS / RSC_IHPSG13_DFNQMX2IX1 +XDFF<5> BIST_EN_I BIST_ADDR_I<5> ACLK_N_I ADDR_I<5> q_int<5> net2<2> VDD ++ VSS / RSC_IHPSG13_DFNQMX2IX1 +XDFF<4> BIST_EN_I BIST_ADDR_I<4> ACLK_N_I ADDR_I<4> q_int<4> net2<3> VDD ++ VSS / RSC_IHPSG13_DFNQMX2IX1 +XDFF<3> BIST_EN_I BIST_ADDR_I<3> ACLK_N_I ADDR_I<3> q_int<3> net2<4> VDD ++ VSS / RSC_IHPSG13_DFNQMX2IX1 +XDFF<2> BIST_EN_I BIST_ADDR_I<2> ACLK_N_I ADDR_I<2> q_int<2> net2<5> VDD ++ VSS / RSC_IHPSG13_DFNQMX2IX1 +XDFF<1> BIST_EN_I BIST_ADDR_I<1> ACLK_N_I ADDR_I<1> q_int<1> net2<6> VDD ++ VSS / RSC_IHPSG13_DFNQMX2IX1 +XDFF<0> BIST_EN_I BIST_ADDR_I<0> ACLK_N_I ADDR_I<0> q_int<0> net2<7> VDD ++ VSS / RSC_IHPSG13_DFNQMX2IX1 +XI11<4> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI11<3> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI11<2> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI11<1> VDD VSS / RSC_IHPSG13_FILLCAP8 +.ENDS + +.SUBCKT RM_IHPSG13_64x32_c2_1P_ROWDEC9 ADDR_N_I<8> ADDR_N_I<7> ADDR_N_I<6> ADDR_N_I<5> ++ ADDR_N_I<4> ADDR_N_I<3> ADDR_N_I<2> ADDR_N_I<1> ADDR_N_I<0> CS_I ECLK_I ++ WL_O<511> WL_O<510> WL_O<509> WL_O<508> WL_O<507> WL_O<506> WL_O<505> ++ WL_O<504> WL_O<503> WL_O<502> WL_O<501> WL_O<500> WL_O<499> WL_O<498> ++ WL_O<497> WL_O<496> WL_O<495> WL_O<494> WL_O<493> WL_O<492> WL_O<491> ++ WL_O<490> WL_O<489> WL_O<488> WL_O<487> WL_O<486> WL_O<485> WL_O<484> ++ WL_O<483> WL_O<482> WL_O<481> WL_O<480> WL_O<479> WL_O<478> WL_O<477> ++ WL_O<476> WL_O<475> WL_O<474> WL_O<473> WL_O<472> WL_O<471> WL_O<470> ++ WL_O<469> WL_O<468> WL_O<467> WL_O<466> WL_O<465> WL_O<464> WL_O<463> ++ WL_O<462> WL_O<461> WL_O<460> WL_O<459> WL_O<458> WL_O<457> WL_O<456> ++ WL_O<455> WL_O<454> WL_O<453> WL_O<452> WL_O<451> WL_O<450> WL_O<449> ++ WL_O<448> WL_O<447> WL_O<446> WL_O<445> WL_O<444> WL_O<443> WL_O<442> ++ WL_O<441> WL_O<440> WL_O<439> WL_O<438> WL_O<437> WL_O<436> WL_O<435> ++ WL_O<434> WL_O<433> WL_O<432> WL_O<431> WL_O<430> WL_O<429> WL_O<428> ++ WL_O<427> WL_O<426> WL_O<425> WL_O<424> WL_O<423> WL_O<422> WL_O<421> ++ WL_O<420> WL_O<419> WL_O<418> WL_O<417> WL_O<416> WL_O<415> WL_O<414> ++ WL_O<413> WL_O<412> WL_O<411> WL_O<410> WL_O<409> WL_O<408> WL_O<407> ++ WL_O<406> WL_O<405> WL_O<404> WL_O<403> WL_O<402> WL_O<401> WL_O<400> ++ WL_O<399> WL_O<398> WL_O<397> WL_O<396> WL_O<395> WL_O<394> WL_O<393> ++ WL_O<392> WL_O<391> WL_O<390> WL_O<389> WL_O<388> WL_O<387> WL_O<386> ++ WL_O<385> WL_O<384> WL_O<383> WL_O<382> WL_O<381> WL_O<380> WL_O<379> ++ WL_O<378> WL_O<377> WL_O<376> WL_O<375> WL_O<374> WL_O<373> WL_O<372> ++ WL_O<371> WL_O<370> WL_O<369> WL_O<368> WL_O<367> WL_O<366> WL_O<365> ++ WL_O<364> WL_O<363> WL_O<362> WL_O<361> WL_O<360> WL_O<359> WL_O<358> ++ WL_O<357> WL_O<356> WL_O<355> WL_O<354> WL_O<353> WL_O<352> WL_O<351> ++ WL_O<350> WL_O<349> WL_O<348> WL_O<347> WL_O<346> WL_O<345> WL_O<344> ++ WL_O<343> WL_O<342> WL_O<341> WL_O<340> WL_O<339> WL_O<338> WL_O<337> ++ WL_O<336> WL_O<335> WL_O<334> WL_O<333> WL_O<332> WL_O<331> WL_O<330> ++ WL_O<329> WL_O<328> WL_O<327> WL_O<326> WL_O<325> WL_O<324> WL_O<323> ++ WL_O<322> WL_O<321> WL_O<320> WL_O<319> WL_O<318> WL_O<317> WL_O<316> ++ WL_O<315> WL_O<314> WL_O<313> WL_O<312> WL_O<311> WL_O<310> WL_O<309> ++ WL_O<308> WL_O<307> WL_O<306> WL_O<305> WL_O<304> WL_O<303> WL_O<302> ++ WL_O<301> WL_O<300> WL_O<299> WL_O<298> WL_O<297> WL_O<296> WL_O<295> ++ WL_O<294> WL_O<293> WL_O<292> WL_O<291> WL_O<290> WL_O<289> WL_O<288> ++ WL_O<287> WL_O<286> WL_O<285> WL_O<284> WL_O<283> WL_O<282> WL_O<281> ++ WL_O<280> WL_O<279> WL_O<278> WL_O<277> WL_O<276> WL_O<275> WL_O<274> ++ WL_O<273> WL_O<272> WL_O<271> WL_O<270> WL_O<269> WL_O<268> WL_O<267> ++ WL_O<266> WL_O<265> WL_O<264> WL_O<263> WL_O<262> WL_O<261> WL_O<260> ++ WL_O<259> WL_O<258> WL_O<257> WL_O<256> WL_O<255> WL_O<254> WL_O<253> ++ WL_O<252> WL_O<251> WL_O<250> WL_O<249> WL_O<248> WL_O<247> WL_O<246> ++ WL_O<245> WL_O<244> WL_O<243> WL_O<242> WL_O<241> WL_O<240> WL_O<239> ++ WL_O<238> WL_O<237> WL_O<236> WL_O<235> WL_O<234> WL_O<233> WL_O<232> ++ WL_O<231> WL_O<230> WL_O<229> WL_O<228> WL_O<227> WL_O<226> WL_O<225> ++ WL_O<224> WL_O<223> WL_O<222> WL_O<221> WL_O<220> WL_O<219> WL_O<218> ++ WL_O<217> WL_O<216> WL_O<215> WL_O<214> WL_O<213> WL_O<212> WL_O<211> ++ WL_O<210> WL_O<209> WL_O<208> WL_O<207> WL_O<206> WL_O<205> WL_O<204> ++ WL_O<203> WL_O<202> WL_O<201> WL_O<200> WL_O<199> WL_O<198> WL_O<197> ++ WL_O<196> WL_O<195> WL_O<194> WL_O<193> WL_O<192> WL_O<191> WL_O<190> ++ WL_O<189> WL_O<188> WL_O<187> WL_O<186> WL_O<185> WL_O<184> WL_O<183> ++ WL_O<182> WL_O<181> WL_O<180> WL_O<179> WL_O<178> WL_O<177> WL_O<176> ++ WL_O<175> WL_O<174> WL_O<173> WL_O<172> WL_O<171> WL_O<170> WL_O<169> ++ WL_O<168> WL_O<167> WL_O<166> WL_O<165> WL_O<164> WL_O<163> WL_O<162> ++ WL_O<161> WL_O<160> WL_O<159> WL_O<158> WL_O<157> WL_O<156> WL_O<155> ++ WL_O<154> WL_O<153> WL_O<152> WL_O<151> WL_O<150> WL_O<149> WL_O<148> ++ WL_O<147> WL_O<146> WL_O<145> WL_O<144> WL_O<143> WL_O<142> WL_O<141> ++ WL_O<140> WL_O<139> WL_O<138> WL_O<137> WL_O<136> WL_O<135> WL_O<134> ++ WL_O<133> WL_O<132> WL_O<131> WL_O<130> WL_O<129> WL_O<128> WL_O<127> ++ WL_O<126> WL_O<125> WL_O<124> WL_O<123> WL_O<122> WL_O<121> WL_O<120> ++ WL_O<119> WL_O<118> WL_O<117> WL_O<116> WL_O<115> WL_O<114> WL_O<113> ++ WL_O<112> WL_O<111> WL_O<110> WL_O<109> WL_O<108> WL_O<107> WL_O<106> ++ WL_O<105> WL_O<104> WL_O<103> WL_O<102> WL_O<101> WL_O<100> WL_O<99> ++ WL_O<98> WL_O<97> WL_O<96> WL_O<95> WL_O<94> WL_O<93> WL_O<92> WL_O<91> ++ WL_O<90> WL_O<89> WL_O<88> WL_O<87> WL_O<86> WL_O<85> WL_O<84> WL_O<83> ++ WL_O<82> WL_O<81> WL_O<80> WL_O<79> WL_O<78> WL_O<77> WL_O<76> WL_O<75> ++ WL_O<74> WL_O<73> WL_O<72> WL_O<71> WL_O<70> WL_O<69> WL_O<68> WL_O<67> ++ WL_O<66> WL_O<65> WL_O<64> WL_O<63> WL_O<62> WL_O<61> WL_O<60> WL_O<59> ++ WL_O<58> WL_O<57> WL_O<56> WL_O<55> WL_O<54> WL_O<53> WL_O<52> WL_O<51> ++ WL_O<50> WL_O<49> WL_O<48> WL_O<47> WL_O<46> WL_O<45> WL_O<44> WL_O<43> ++ WL_O<42> WL_O<41> WL_O<40> WL_O<39> WL_O<38> WL_O<37> WL_O<36> WL_O<35> ++ WL_O<34> WL_O<33> WL_O<32> WL_O<31> WL_O<30> WL_O<29> WL_O<28> WL_O<27> ++ WL_O<26> WL_O<25> WL_O<24> WL_O<23> WL_O<22> WL_O<21> WL_O<20> WL_O<19> ++ WL_O<18> WL_O<17> WL_O<16> WL_O<15> WL_O<14> WL_O<13> WL_O<12> WL_O<11> ++ WL_O<10> WL_O<9> WL_O<8> WL_O<7> WL_O<6> WL_O<5> WL_O<4> WL_O<3> WL_O<2> ++ WL_O<1> WL_O<0> VDD VSS +XL2<172> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<171> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<170> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<169> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<168> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<167> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<166> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<165> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<164> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<163> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<162> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<161> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<160> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<159> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<158> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<157> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<156> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<155> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<154> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<153> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<152> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<151> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<150> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<149> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<148> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<147> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<146> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<145> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<144> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<143> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<142> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<141> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<140> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<139> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<138> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<137> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<136> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<135> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<134> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<133> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<132> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<131> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<130> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<129> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<128> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<127> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<126> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<125> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<124> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<123> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<122> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<121> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<120> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<119> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<118> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<117> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<116> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<115> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<114> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<113> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<112> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<111> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<110> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<109> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<108> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<107> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<106> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<105> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<104> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<103> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<102> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<101> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<100> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<99> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<98> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<97> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<96> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<95> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<94> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<93> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<92> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<91> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<90> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<89> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<88> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<87> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<86> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<85> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<84> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<83> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<82> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<81> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<80> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<79> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<78> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<77> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<76> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<75> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<74> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<73> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<72> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<71> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<70> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<69> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<68> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<67> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<66> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<65> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<64> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<63> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<62> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<61> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<60> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<59> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<58> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<57> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<56> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<55> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<54> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<53> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<52> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<51> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<50> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<49> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<48> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<47> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<46> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<45> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<44> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<43> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<42> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<41> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<40> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<39> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<38> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<37> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<36> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<35> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<34> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<33> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<32> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<31> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<30> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<29> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<28> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<27> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<26> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<25> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<24> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<23> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<22> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<21> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<20> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<19> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<18> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<17> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<16> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<15> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<14> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<13> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<12> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<11> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<10> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<9> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<8> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<7> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<6> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<5> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<4> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<3> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<2> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<1> VDD VSS / RSC_IHPSG13_FILLCAP8 +XDEC11<9> ADDR_N_I<7> ADDR_N_I<6> CS04<1> CS02<7> VDD VSS / ++ RM_IHPSG13_64x32_c2_1P_DEC03 +XDEC11<8> ADDR_N_I<7> ADDR_N_I<6> CS04<0> CS02<3> VDD VSS / ++ RM_IHPSG13_64x32_c2_1P_DEC03 +XDEC11<7> ADDR_N_I<5> ADDR_N_I<4> CS02<7> CS00<31> VDD VSS / ++ RM_IHPSG13_64x32_c2_1P_DEC03 +XDEC11<6> ADDR_N_I<5> ADDR_N_I<4> CS02<6> CS00<27> VDD VSS / ++ RM_IHPSG13_64x32_c2_1P_DEC03 +XDEC11<5> ADDR_N_I<5> ADDR_N_I<4> CS02<5> CS00<23> VDD VSS / ++ RM_IHPSG13_64x32_c2_1P_DEC03 +XDEC11<4> ADDR_N_I<5> ADDR_N_I<4> CS02<4> CS00<19> VDD VSS / ++ RM_IHPSG13_64x32_c2_1P_DEC03 +XDEC11<3> ADDR_N_I<5> ADDR_N_I<4> CS02<3> CS00<15> VDD VSS / ++ RM_IHPSG13_64x32_c2_1P_DEC03 +XDEC11<2> ADDR_N_I<5> ADDR_N_I<4> CS02<2> CS00<11> VDD VSS / ++ RM_IHPSG13_64x32_c2_1P_DEC03 +XDEC11<1> ADDR_N_I<5> ADDR_N_I<4> CS02<1> CS00<7> VDD VSS / ++ RM_IHPSG13_64x32_c2_1P_DEC03 +XDEC11<0> ADDR_N_I<5> ADDR_N_I<4> CS02<0> CS00<3> VDD VSS / ++ RM_IHPSG13_64x32_c2_1P_DEC03 +XDEC00<10> ADDR_N_I<9> ADDR_N_I<8> CS_I CS04<0> VDD VSS / ++ RM_IHPSG13_64x32_c2_1P_DEC00 +XDEC00<9> ADDR_N_I<7> ADDR_N_I<6> CS04<1> CS02<4> VDD VSS / ++ RM_IHPSG13_64x32_c2_1P_DEC00 +XDEC00<8> ADDR_N_I<7> ADDR_N_I<6> CS04<0> CS02<0> VDD VSS / ++ RM_IHPSG13_64x32_c2_1P_DEC00 +XDEC00<7> ADDR_N_I<5> ADDR_N_I<4> CS02<7> CS00<28> VDD VSS / ++ RM_IHPSG13_64x32_c2_1P_DEC00 +XDEC00<6> ADDR_N_I<5> ADDR_N_I<4> CS02<6> CS00<24> VDD VSS / ++ RM_IHPSG13_64x32_c2_1P_DEC00 +XDEC00<5> ADDR_N_I<5> ADDR_N_I<4> CS02<5> CS00<20> VDD VSS / ++ RM_IHPSG13_64x32_c2_1P_DEC00 +XDEC00<4> ADDR_N_I<5> ADDR_N_I<4> CS02<4> CS00<16> VDD VSS / ++ RM_IHPSG13_64x32_c2_1P_DEC00 +XDEC00<3> ADDR_N_I<5> ADDR_N_I<4> CS02<3> CS00<12> VDD VSS / ++ RM_IHPSG13_64x32_c2_1P_DEC00 +XDEC00<2> ADDR_N_I<5> ADDR_N_I<4> CS02<2> CS00<8> VDD VSS / ++ RM_IHPSG13_64x32_c2_1P_DEC00 +XDEC00<1> ADDR_N_I<5> ADDR_N_I<4> CS02<1> CS00<4> VDD VSS / ++ RM_IHPSG13_64x32_c2_1P_DEC00 +XDEC00<0> ADDR_N_I<5> ADDR_N_I<4> CS02<0> CS00<0> VDD VSS / ++ RM_IHPSG13_64x32_c2_1P_DEC00 +XSEL<31> ADDR_N_I<3> ADDR_N_I<2> ADDR_N_I<1> ADDR_N_I<0> CS00<31> ECLK_H<31> ++ ECLK_H<32> ECLK_B<31> ECLK_B<32> WL_O<511> WL_O<510> WL_O<509> WL_O<508> ++ WL_O<507> WL_O<506> WL_O<505> WL_O<504> WL_O<503> WL_O<502> WL_O<501> ++ WL_O<500> WL_O<499> WL_O<498> WL_O<497> WL_O<496> VDD VSS / ++ RM_IHPSG13_64x32_c2_1P_DEC04 +XSEL<30> ADDR_N_I<3> ADDR_N_I<2> ADDR_N_I<1> ADDR_N_I<0> CS00<30> ECLK_H<30> ++ ECLK_H<31> ECLK_B<30> ECLK_B<31> WL_O<495> WL_O<494> WL_O<493> WL_O<492> ++ WL_O<491> WL_O<490> WL_O<489> WL_O<488> WL_O<487> WL_O<486> WL_O<485> ++ WL_O<484> WL_O<483> WL_O<482> WL_O<481> WL_O<480> VDD VSS / ++ RM_IHPSG13_64x32_c2_1P_DEC04 +XSEL<29> ADDR_N_I<3> ADDR_N_I<2> ADDR_N_I<1> ADDR_N_I<0> CS00<29> ECLK_H<29> ++ ECLK_H<30> ECLK_B<29> ECLK_B<30> WL_O<479> WL_O<478> WL_O<477> WL_O<476> ++ WL_O<475> WL_O<474> WL_O<473> WL_O<472> WL_O<471> WL_O<470> WL_O<469> ++ WL_O<468> WL_O<467> WL_O<466> WL_O<465> WL_O<464> VDD VSS / ++ RM_IHPSG13_64x32_c2_1P_DEC04 +XSEL<28> ADDR_N_I<3> ADDR_N_I<2> ADDR_N_I<1> ADDR_N_I<0> CS00<28> ECLK_H<28> ++ ECLK_H<29> ECLK_B<28> ECLK_B<29> WL_O<463> WL_O<462> WL_O<461> WL_O<460> ++ WL_O<459> WL_O<458> WL_O<457> WL_O<456> WL_O<455> WL_O<454> WL_O<453> ++ WL_O<452> WL_O<451> WL_O<450> WL_O<449> WL_O<448> VDD VSS / ++ RM_IHPSG13_64x32_c2_1P_DEC04 +XSEL<27> ADDR_N_I<3> ADDR_N_I<2> ADDR_N_I<1> ADDR_N_I<0> CS00<27> ECLK_H<27> ++ ECLK_H<28> ECLK_B<27> ECLK_B<28> WL_O<447> WL_O<446> WL_O<445> WL_O<444> ++ WL_O<443> WL_O<442> WL_O<441> WL_O<440> WL_O<439> WL_O<438> WL_O<437> ++ WL_O<436> WL_O<435> WL_O<434> WL_O<433> WL_O<432> VDD VSS / ++ RM_IHPSG13_64x32_c2_1P_DEC04 +XSEL<26> ADDR_N_I<3> ADDR_N_I<2> ADDR_N_I<1> ADDR_N_I<0> CS00<26> ECLK_H<26> ++ ECLK_H<27> ECLK_B<26> ECLK_B<27> WL_O<431> WL_O<430> WL_O<429> WL_O<428> ++ WL_O<427> WL_O<426> WL_O<425> WL_O<424> WL_O<423> WL_O<422> WL_O<421> ++ WL_O<420> WL_O<419> WL_O<418> WL_O<417> WL_O<416> VDD VSS / ++ RM_IHPSG13_64x32_c2_1P_DEC04 +XSEL<25> ADDR_N_I<3> ADDR_N_I<2> ADDR_N_I<1> ADDR_N_I<0> CS00<25> ECLK_H<25> ++ ECLK_H<26> ECLK_B<25> ECLK_B<26> WL_O<415> WL_O<414> WL_O<413> WL_O<412> ++ WL_O<411> WL_O<410> WL_O<409> WL_O<408> WL_O<407> WL_O<406> WL_O<405> ++ WL_O<404> WL_O<403> WL_O<402> WL_O<401> WL_O<400> VDD VSS / ++ RM_IHPSG13_64x32_c2_1P_DEC04 +XSEL<24> ADDR_N_I<3> ADDR_N_I<2> ADDR_N_I<1> ADDR_N_I<0> CS00<24> ECLK_H<24> ++ ECLK_H<25> ECLK_B<24> ECLK_B<25> WL_O<399> WL_O<398> WL_O<397> WL_O<396> ++ WL_O<395> WL_O<394> WL_O<393> WL_O<392> WL_O<391> WL_O<390> WL_O<389> ++ WL_O<388> WL_O<387> WL_O<386> WL_O<385> WL_O<384> VDD VSS / ++ RM_IHPSG13_64x32_c2_1P_DEC04 +XSEL<23> ADDR_N_I<3> ADDR_N_I<2> ADDR_N_I<1> ADDR_N_I<0> CS00<23> ECLK_H<23> ++ ECLK_H<24> ECLK_B<23> ECLK_B<24> WL_O<383> WL_O<382> WL_O<381> WL_O<380> ++ WL_O<379> WL_O<378> WL_O<377> WL_O<376> WL_O<375> WL_O<374> WL_O<373> ++ WL_O<372> WL_O<371> WL_O<370> WL_O<369> WL_O<368> VDD VSS / ++ RM_IHPSG13_64x32_c2_1P_DEC04 +XSEL<22> ADDR_N_I<3> ADDR_N_I<2> ADDR_N_I<1> ADDR_N_I<0> CS00<22> ECLK_H<22> ++ ECLK_H<23> ECLK_B<22> ECLK_B<23> WL_O<367> WL_O<366> WL_O<365> WL_O<364> ++ WL_O<363> WL_O<362> WL_O<361> WL_O<360> WL_O<359> WL_O<358> WL_O<357> ++ WL_O<356> WL_O<355> WL_O<354> WL_O<353> WL_O<352> VDD VSS / ++ RM_IHPSG13_64x32_c2_1P_DEC04 +XSEL<21> ADDR_N_I<3> ADDR_N_I<2> ADDR_N_I<1> ADDR_N_I<0> CS00<21> ECLK_H<21> ++ ECLK_H<22> ECLK_B<21> ECLK_B<22> WL_O<351> WL_O<350> WL_O<349> WL_O<348> ++ WL_O<347> WL_O<346> WL_O<345> WL_O<344> WL_O<343> WL_O<342> WL_O<341> ++ WL_O<340> WL_O<339> WL_O<338> WL_O<337> WL_O<336> VDD VSS / ++ RM_IHPSG13_64x32_c2_1P_DEC04 +XSEL<20> ADDR_N_I<3> ADDR_N_I<2> ADDR_N_I<1> ADDR_N_I<0> CS00<20> ECLK_H<20> ++ ECLK_H<21> ECLK_B<20> ECLK_B<21> WL_O<335> WL_O<334> WL_O<333> WL_O<332> ++ WL_O<331> WL_O<330> WL_O<329> WL_O<328> WL_O<327> WL_O<326> WL_O<325> ++ WL_O<324> WL_O<323> WL_O<322> WL_O<321> WL_O<320> VDD VSS / ++ RM_IHPSG13_64x32_c2_1P_DEC04 +XSEL<19> ADDR_N_I<3> ADDR_N_I<2> ADDR_N_I<1> ADDR_N_I<0> CS00<19> ECLK_H<19> ++ ECLK_H<20> ECLK_B<19> ECLK_B<20> WL_O<319> WL_O<318> WL_O<317> WL_O<316> ++ WL_O<315> WL_O<314> WL_O<313> WL_O<312> WL_O<311> WL_O<310> WL_O<309> ++ WL_O<308> WL_O<307> WL_O<306> WL_O<305> WL_O<304> VDD VSS / ++ RM_IHPSG13_64x32_c2_1P_DEC04 +XSEL<18> ADDR_N_I<3> ADDR_N_I<2> ADDR_N_I<1> ADDR_N_I<0> CS00<18> ECLK_H<18> ++ ECLK_H<19> ECLK_B<18> ECLK_B<19> WL_O<303> WL_O<302> WL_O<301> WL_O<300> ++ WL_O<299> WL_O<298> WL_O<297> WL_O<296> WL_O<295> WL_O<294> WL_O<293> ++ WL_O<292> WL_O<291> WL_O<290> WL_O<289> WL_O<288> VDD VSS / ++ RM_IHPSG13_64x32_c2_1P_DEC04 +XSEL<17> ADDR_N_I<3> ADDR_N_I<2> ADDR_N_I<1> ADDR_N_I<0> CS00<17> ECLK_H<17> ++ ECLK_H<18> ECLK_B<17> ECLK_B<18> WL_O<287> WL_O<286> WL_O<285> WL_O<284> ++ WL_O<283> WL_O<282> WL_O<281> WL_O<280> WL_O<279> WL_O<278> WL_O<277> ++ WL_O<276> WL_O<275> WL_O<274> WL_O<273> WL_O<272> VDD VSS / ++ RM_IHPSG13_64x32_c2_1P_DEC04 +XSEL<16> ADDR_N_I<3> ADDR_N_I<2> ADDR_N_I<1> ADDR_N_I<0> CS00<16> ECLK_H<16> ++ ECLK_H<17> ECLK_B<16> ECLK_B<17> WL_O<271> WL_O<270> WL_O<269> WL_O<268> ++ WL_O<267> WL_O<266> WL_O<265> WL_O<264> WL_O<263> WL_O<262> WL_O<261> ++ WL_O<260> WL_O<259> WL_O<258> WL_O<257> WL_O<256> VDD VSS / ++ RM_IHPSG13_64x32_c2_1P_DEC04 +XSEL<15> ADDR_N_I<3> ADDR_N_I<2> ADDR_N_I<1> ADDR_N_I<0> CS00<15> ECLK_H<15> ++ ECLK_H<16> ECLK_B<15> ECLK_B<16> WL_O<255> WL_O<254> WL_O<253> WL_O<252> ++ WL_O<251> WL_O<250> WL_O<249> WL_O<248> WL_O<247> WL_O<246> WL_O<245> ++ WL_O<244> WL_O<243> WL_O<242> WL_O<241> WL_O<240> VDD VSS / ++ RM_IHPSG13_64x32_c2_1P_DEC04 +XSEL<14> ADDR_N_I<3> ADDR_N_I<2> ADDR_N_I<1> ADDR_N_I<0> CS00<14> ECLK_H<14> ++ ECLK_H<15> ECLK_B<14> ECLK_B<15> WL_O<239> WL_O<238> WL_O<237> WL_O<236> ++ WL_O<235> WL_O<234> WL_O<233> WL_O<232> WL_O<231> WL_O<230> WL_O<229> ++ WL_O<228> WL_O<227> WL_O<226> WL_O<225> WL_O<224> VDD VSS / ++ RM_IHPSG13_64x32_c2_1P_DEC04 +XSEL<13> ADDR_N_I<3> ADDR_N_I<2> ADDR_N_I<1> ADDR_N_I<0> CS00<13> ECLK_H<13> ++ ECLK_H<14> ECLK_B<13> ECLK_B<14> WL_O<223> WL_O<222> WL_O<221> WL_O<220> ++ WL_O<219> WL_O<218> WL_O<217> WL_O<216> WL_O<215> WL_O<214> WL_O<213> ++ WL_O<212> WL_O<211> WL_O<210> WL_O<209> WL_O<208> VDD VSS / ++ RM_IHPSG13_64x32_c2_1P_DEC04 +XSEL<12> ADDR_N_I<3> ADDR_N_I<2> ADDR_N_I<1> ADDR_N_I<0> CS00<12> ECLK_H<12> ++ ECLK_H<13> ECLK_B<12> ECLK_B<13> WL_O<207> WL_O<206> WL_O<205> WL_O<204> ++ WL_O<203> WL_O<202> WL_O<201> WL_O<200> WL_O<199> WL_O<198> WL_O<197> ++ WL_O<196> WL_O<195> WL_O<194> WL_O<193> WL_O<192> VDD VSS / ++ RM_IHPSG13_64x32_c2_1P_DEC04 +XSEL<11> ADDR_N_I<3> ADDR_N_I<2> ADDR_N_I<1> ADDR_N_I<0> CS00<11> ECLK_H<11> ++ ECLK_H<12> ECLK_B<11> ECLK_B<12> WL_O<191> WL_O<190> WL_O<189> WL_O<188> ++ WL_O<187> WL_O<186> WL_O<185> WL_O<184> WL_O<183> WL_O<182> WL_O<181> ++ WL_O<180> WL_O<179> WL_O<178> WL_O<177> WL_O<176> VDD VSS / ++ RM_IHPSG13_64x32_c2_1P_DEC04 +XSEL<10> ADDR_N_I<3> ADDR_N_I<2> ADDR_N_I<1> ADDR_N_I<0> CS00<10> ECLK_H<10> ++ ECLK_H<11> ECLK_B<10> ECLK_B<11> WL_O<175> WL_O<174> WL_O<173> WL_O<172> ++ WL_O<171> WL_O<170> WL_O<169> WL_O<168> WL_O<167> WL_O<166> WL_O<165> ++ WL_O<164> WL_O<163> WL_O<162> WL_O<161> WL_O<160> VDD VSS / ++ RM_IHPSG13_64x32_c2_1P_DEC04 +XSEL<9> ADDR_N_I<3> ADDR_N_I<2> ADDR_N_I<1> ADDR_N_I<0> CS00<9> ECLK_H<9> ++ ECLK_H<10> ECLK_B<9> ECLK_B<10> WL_O<159> WL_O<158> WL_O<157> WL_O<156> ++ WL_O<155> WL_O<154> WL_O<153> WL_O<152> WL_O<151> WL_O<150> WL_O<149> ++ WL_O<148> WL_O<147> WL_O<146> WL_O<145> WL_O<144> VDD VSS / ++ RM_IHPSG13_64x32_c2_1P_DEC04 +XSEL<8> ADDR_N_I<3> ADDR_N_I<2> ADDR_N_I<1> ADDR_N_I<0> CS00<8> ECLK_H<8> ++ ECLK_H<9> ECLK_B<8> ECLK_B<9> WL_O<143> WL_O<142> WL_O<141> WL_O<140> ++ WL_O<139> WL_O<138> WL_O<137> WL_O<136> WL_O<135> WL_O<134> WL_O<133> ++ WL_O<132> WL_O<131> WL_O<130> WL_O<129> WL_O<128> VDD VSS / ++ RM_IHPSG13_64x32_c2_1P_DEC04 +XSEL<7> ADDR_N_I<3> ADDR_N_I<2> ADDR_N_I<1> ADDR_N_I<0> CS00<7> ECLK_H<7> ++ ECLK_H<8> ECLK_B<7> ECLK_B<8> WL_O<127> WL_O<126> WL_O<125> WL_O<124> ++ WL_O<123> WL_O<122> WL_O<121> WL_O<120> WL_O<119> WL_O<118> WL_O<117> ++ WL_O<116> WL_O<115> WL_O<114> WL_O<113> WL_O<112> VDD VSS / ++ RM_IHPSG13_64x32_c2_1P_DEC04 +XSEL<6> ADDR_N_I<3> ADDR_N_I<2> ADDR_N_I<1> ADDR_N_I<0> CS00<6> ECLK_H<6> ++ ECLK_H<7> ECLK_B<6> ECLK_B<7> WL_O<111> WL_O<110> WL_O<109> WL_O<108> ++ WL_O<107> WL_O<106> WL_O<105> WL_O<104> WL_O<103> WL_O<102> WL_O<101> ++ WL_O<100> WL_O<99> WL_O<98> WL_O<97> WL_O<96> VDD VSS / ++ RM_IHPSG13_64x32_c2_1P_DEC04 +XSEL<5> ADDR_N_I<3> ADDR_N_I<2> ADDR_N_I<1> ADDR_N_I<0> CS00<5> ECLK_H<5> ++ ECLK_H<6> ECLK_B<5> ECLK_B<6> WL_O<95> WL_O<94> WL_O<93> WL_O<92> WL_O<91> ++ WL_O<90> WL_O<89> WL_O<88> WL_O<87> WL_O<86> WL_O<85> WL_O<84> WL_O<83> ++ WL_O<82> WL_O<81> WL_O<80> VDD VSS / RM_IHPSG13_64x32_c2_1P_DEC04 +XSEL<4> ADDR_N_I<3> ADDR_N_I<2> ADDR_N_I<1> ADDR_N_I<0> CS00<4> ECLK_H<4> ++ ECLK_H<5> ECLK_B<4> ECLK_B<5> WL_O<79> WL_O<78> WL_O<77> WL_O<76> WL_O<75> ++ WL_O<74> WL_O<73> WL_O<72> WL_O<71> WL_O<70> WL_O<69> WL_O<68> WL_O<67> ++ WL_O<66> WL_O<65> WL_O<64> VDD VSS / RM_IHPSG13_64x32_c2_1P_DEC04 +XSEL<3> ADDR_N_I<3> ADDR_N_I<2> ADDR_N_I<1> ADDR_N_I<0> CS00<3> ECLK_H<3> ++ ECLK_H<4> ECLK_B<3> ECLK_B<4> WL_O<63> WL_O<62> WL_O<61> WL_O<60> WL_O<59> ++ WL_O<58> WL_O<57> WL_O<56> WL_O<55> WL_O<54> WL_O<53> WL_O<52> WL_O<51> ++ WL_O<50> WL_O<49> WL_O<48> VDD VSS / RM_IHPSG13_64x32_c2_1P_DEC04 +XSEL<2> ADDR_N_I<3> ADDR_N_I<2> ADDR_N_I<1> ADDR_N_I<0> CS00<2> ECLK_H<2> ++ ECLK_H<3> ECLK_B<2> ECLK_B<3> WL_O<47> WL_O<46> WL_O<45> WL_O<44> WL_O<43> ++ WL_O<42> WL_O<41> WL_O<40> WL_O<39> WL_O<38> WL_O<37> WL_O<36> WL_O<35> ++ WL_O<34> WL_O<33> WL_O<32> VDD VSS / RM_IHPSG13_64x32_c2_1P_DEC04 +XSEL<1> ADDR_N_I<3> ADDR_N_I<2> ADDR_N_I<1> ADDR_N_I<0> CS00<1> ECLK_H<1> ++ ECLK_H<2> ECLK_B<1> ECLK_B<2> WL_O<31> WL_O<30> WL_O<29> WL_O<28> WL_O<27> ++ WL_O<26> WL_O<25> WL_O<24> WL_O<23> WL_O<22> WL_O<21> WL_O<20> WL_O<19> ++ WL_O<18> WL_O<17> WL_O<16> VDD VSS / RM_IHPSG13_64x32_c2_1P_DEC04 +XSEL<0> ADDR_N_I<3> ADDR_N_I<2> ADDR_N_I<1> ADDR_N_I<0> CS00<0> ECLK_I ++ ECLK_H<1> ECLK_B<0> ECLK_B<1> WL_O<15> WL_O<14> WL_O<13> WL_O<12> WL_O<11> ++ WL_O<10> WL_O<9> WL_O<8> WL_O<7> WL_O<6> WL_O<5> WL_O<4> WL_O<3> WL_O<2> ++ WL_O<1> WL_O<0> VDD VSS / RM_IHPSG13_64x32_c2_1P_DEC04 +XDEC01<10> ADDR_N_I<9> ADDR_N_I<8> CS_I CS04<1> VDD VSS / ++ RM_IHPSG13_64x32_c2_1P_DEC01 +XDEC01<9> ADDR_N_I<7> ADDR_N_I<6> CS04<1> CS02<5> VDD VSS / ++ RM_IHPSG13_64x32_c2_1P_DEC01 +XDEC01<8> ADDR_N_I<7> ADDR_N_I<6> CS04<0> CS02<1> VDD VSS / ++ RM_IHPSG13_64x32_c2_1P_DEC01 +XDEC01<7> ADDR_N_I<5> ADDR_N_I<4> CS02<7> CS00<29> VDD VSS / ++ RM_IHPSG13_64x32_c2_1P_DEC01 +XDEC01<6> ADDR_N_I<5> ADDR_N_I<4> CS02<6> CS00<25> VDD VSS / ++ RM_IHPSG13_64x32_c2_1P_DEC01 +XDEC01<5> ADDR_N_I<5> ADDR_N_I<4> CS02<5> CS00<21> VDD VSS / ++ RM_IHPSG13_64x32_c2_1P_DEC01 +XDEC01<4> ADDR_N_I<5> ADDR_N_I<4> CS02<4> CS00<17> VDD VSS / ++ RM_IHPSG13_64x32_c2_1P_DEC01 +XDEC01<3> ADDR_N_I<5> ADDR_N_I<4> CS02<3> CS00<13> VDD VSS / ++ RM_IHPSG13_64x32_c2_1P_DEC01 +XDEC01<2> ADDR_N_I<5> ADDR_N_I<4> CS02<2> CS00<9> VDD VSS / ++ RM_IHPSG13_64x32_c2_1P_DEC01 +XDEC01<1> ADDR_N_I<5> ADDR_N_I<4> CS02<1> CS00<5> VDD VSS / ++ RM_IHPSG13_64x32_c2_1P_DEC01 +XDEC01<0> ADDR_N_I<5> ADDR_N_I<4> CS02<0> CS00<1> VDD VSS / ++ RM_IHPSG13_64x32_c2_1P_DEC01 +XDEC10<9> ADDR_N_I<7> ADDR_N_I<6> CS04<1> CS02<6> VDD VSS / ++ RM_IHPSG13_64x32_c2_1P_DEC02 +XDEC10<8> ADDR_N_I<7> ADDR_N_I<6> CS04<0> CS02<2> VDD VSS / ++ RM_IHPSG13_64x32_c2_1P_DEC02 +XDEC10<7> ADDR_N_I<5> ADDR_N_I<4> CS02<7> CS00<30> VDD VSS / ++ RM_IHPSG13_64x32_c2_1P_DEC02 +XDEC10<6> ADDR_N_I<5> ADDR_N_I<4> CS02<6> CS00<26> VDD VSS / ++ RM_IHPSG13_64x32_c2_1P_DEC02 +XDEC10<5> ADDR_N_I<5> ADDR_N_I<4> CS02<5> CS00<22> VDD VSS / ++ RM_IHPSG13_64x32_c2_1P_DEC02 +XDEC10<4> ADDR_N_I<5> ADDR_N_I<4> CS02<4> CS00<18> VDD VSS / ++ RM_IHPSG13_64x32_c2_1P_DEC02 +XDEC10<3> ADDR_N_I<5> ADDR_N_I<4> CS02<3> CS00<14> VDD VSS / ++ RM_IHPSG13_64x32_c2_1P_DEC02 +XDEC10<2> ADDR_N_I<5> ADDR_N_I<4> CS02<2> CS00<10> VDD VSS / ++ RM_IHPSG13_64x32_c2_1P_DEC02 +XDEC10<1> ADDR_N_I<5> ADDR_N_I<4> CS02<1> CS00<6> VDD VSS / ++ RM_IHPSG13_64x32_c2_1P_DEC02 +XDEC10<0> ADDR_N_I<5> ADDR_N_I<4> CS02<0> CS00<2> VDD VSS / ++ RM_IHPSG13_64x32_c2_1P_DEC02 +XI0 ADDR_N_I<9> VDD VSS / RSC_IHPSG13_TIEL +.ENDS +.SUBCKT RM_IHPSG13_64x32_c2_1P_ROWREG9 ACLK_N_I ADDR_I<8> ADDR_I<7> ADDR_I<6> ADDR_I<5> ++ ADDR_I<4> ADDR_I<3> ADDR_I<2> ADDR_I<1> ADDR_I<0> ADDR_N_O<8> ADDR_N_O<7> ++ ADDR_N_O<6> ADDR_N_O<5> ADDR_N_O<4> ADDR_N_O<3> ADDR_N_O<2> ADDR_N_O<1> ++ ADDR_N_O<0> BIST_ADDR_I<8> BIST_ADDR_I<7> BIST_ADDR_I<6> BIST_ADDR_I<5> ++ BIST_ADDR_I<4> BIST_ADDR_I<3> BIST_ADDR_I<2> BIST_ADDR_I<1> BIST_ADDR_I<0> ++ BIST_EN_I VDD VSS +XINV<8> q_int<8> qn_int<8> VDD VSS / RSC_IHPSG13_CINVX2 +XINV<7> q_int<7> qn_int<7> VDD VSS / RSC_IHPSG13_CINVX2 +XINV<6> q_int<6> qn_int<6> VDD VSS / RSC_IHPSG13_CINVX2 +XINV<5> q_int<5> qn_int<5> VDD VSS / RSC_IHPSG13_CINVX2 +XINV<4> q_int<4> qn_int<4> VDD VSS / RSC_IHPSG13_CINVX2 +XINV<3> q_int<3> qn_int<3> VDD VSS / RSC_IHPSG13_CINVX2 +XINV<2> q_int<2> qn_int<2> VDD VSS / RSC_IHPSG13_CINVX2 +XINV<1> q_int<1> qn_int<1> VDD VSS / RSC_IHPSG13_CINVX2 +XINV<0> q_int<0> qn_int<0> VDD VSS / RSC_IHPSG13_CINVX2 +XDRV<8> qn_int<8> ADDR_N_O<8> VDD VSS / RSC_IHPSG13_CINVX8 +XDRV<7> qn_int<7> ADDR_N_O<7> VDD VSS / RSC_IHPSG13_CINVX8 +XDRV<6> qn_int<6> ADDR_N_O<6> VDD VSS / RSC_IHPSG13_CINVX8 +XDRV<5> qn_int<5> ADDR_N_O<5> VDD VSS / RSC_IHPSG13_CINVX8 +XDRV<4> qn_int<4> ADDR_N_O<4> VDD VSS / RSC_IHPSG13_CINVX8 +XDRV<3> qn_int<3> ADDR_N_O<3> VDD VSS / RSC_IHPSG13_CINVX8 +XDRV<2> qn_int<2> ADDR_N_O<2> VDD VSS / RSC_IHPSG13_CINVX8 +XDRV<1> qn_int<1> ADDR_N_O<1> VDD VSS / RSC_IHPSG13_CINVX8 +XDRV<0> qn_int<0> ADDR_N_O<0> VDD VSS / RSC_IHPSG13_CINVX8 +XDFF<8> BIST_EN_I BIST_ADDR_I<8> ACLK_N_I ADDR_I<8> q_int<8> net04<0> VDD ++ VSS / RSC_IHPSG13_DFNQMX2IX1 +XDFF<7> BIST_EN_I BIST_ADDR_I<7> ACLK_N_I ADDR_I<7> q_int<7> net04<1> VDD ++ VSS / RSC_IHPSG13_DFNQMX2IX1 +XDFF<6> BIST_EN_I BIST_ADDR_I<6> ACLK_N_I ADDR_I<6> q_int<6> net04<2> VDD ++ VSS / RSC_IHPSG13_DFNQMX2IX1 +XDFF<5> BIST_EN_I BIST_ADDR_I<5> ACLK_N_I ADDR_I<5> q_int<5> net04<3> VDD ++ VSS / RSC_IHPSG13_DFNQMX2IX1 +XDFF<4> BIST_EN_I BIST_ADDR_I<4> ACLK_N_I ADDR_I<4> q_int<4> net04<4> VDD ++ VSS / RSC_IHPSG13_DFNQMX2IX1 +XDFF<3> BIST_EN_I BIST_ADDR_I<3> ACLK_N_I ADDR_I<3> q_int<3> net04<5> VDD ++ VSS / RSC_IHPSG13_DFNQMX2IX1 +XDFF<2> BIST_EN_I BIST_ADDR_I<2> ACLK_N_I ADDR_I<2> q_int<2> net04<6> VDD ++ VSS / RSC_IHPSG13_DFNQMX2IX1 +XDFF<1> BIST_EN_I BIST_ADDR_I<1> ACLK_N_I ADDR_I<1> q_int<1> net04<7> VDD ++ VSS / RSC_IHPSG13_DFNQMX2IX1 +XDFF<0> BIST_EN_I BIST_ADDR_I<0> ACLK_N_I ADDR_I<0> q_int<0> net04<8> VDD ++ VSS / RSC_IHPSG13_DFNQMX2IX1 +.ENDS + +.SUBCKT RM_IHPSG13_64x32_c2_1P_ROWDEC7 ADDR_N_I<6> ADDR_N_I<5> ADDR_N_I<4> ADDR_N_I<3> ++ ADDR_N_I<2> ADDR_N_I<1> ADDR_N_I<0> CS_I ECLK_I WL_O<127> WL_O<126> ++ WL_O<125> WL_O<124> WL_O<123> WL_O<122> WL_O<121> WL_O<120> WL_O<119> ++ WL_O<118> WL_O<117> WL_O<116> WL_O<115> WL_O<114> WL_O<113> WL_O<112> ++ WL_O<111> WL_O<110> WL_O<109> WL_O<108> WL_O<107> WL_O<106> WL_O<105> ++ WL_O<104> WL_O<103> WL_O<102> WL_O<101> WL_O<100> WL_O<99> WL_O<98> WL_O<97> ++ WL_O<96> WL_O<95> WL_O<94> WL_O<93> WL_O<92> WL_O<91> WL_O<90> WL_O<89> ++ WL_O<88> WL_O<87> WL_O<86> WL_O<85> WL_O<84> WL_O<83> WL_O<82> WL_O<81> ++ WL_O<80> WL_O<79> WL_O<78> WL_O<77> WL_O<76> WL_O<75> WL_O<74> WL_O<73> ++ WL_O<72> WL_O<71> WL_O<70> WL_O<69> WL_O<68> WL_O<67> WL_O<66> WL_O<65> ++ WL_O<64> WL_O<63> WL_O<62> WL_O<61> WL_O<60> WL_O<59> WL_O<58> WL_O<57> ++ WL_O<56> WL_O<55> WL_O<54> WL_O<53> WL_O<52> WL_O<51> WL_O<50> WL_O<49> ++ WL_O<48> WL_O<47> WL_O<46> WL_O<45> WL_O<44> WL_O<43> WL_O<42> WL_O<41> ++ WL_O<40> WL_O<39> WL_O<38> WL_O<37> WL_O<36> WL_O<35> WL_O<34> WL_O<33> ++ WL_O<32> WL_O<31> WL_O<30> WL_O<29> WL_O<28> WL_O<27> WL_O<26> WL_O<25> ++ WL_O<24> WL_O<23> WL_O<22> WL_O<21> WL_O<20> WL_O<19> WL_O<18> WL_O<17> ++ WL_O<16> WL_O<15> WL_O<14> WL_O<13> WL_O<12> WL_O<11> WL_O<10> WL_O<9> ++ WL_O<8> WL_O<7> WL_O<6> WL_O<5> WL_O<4> WL_O<3> WL_O<2> WL_O<1> WL_O<0> ++ VDD VSS +XDEC11<1> ADDR_N_I<5> ADDR_N_I<4> CS04<1> CS00<7> VDD VSS / ++ RM_IHPSG13_64x32_c2_1P_DEC03 +XDEC11<0> ADDR_N_I<5> ADDR_N_I<4> CS04<0> CS00<3> VDD VSS / ++ RM_IHPSG13_64x32_c2_1P_DEC03 +XDEC10<1> ADDR_N_I<5> ADDR_N_I<4> CS04<1> CS00<6> VDD VSS / ++ RM_IHPSG13_64x32_c2_1P_DEC02 +XDEC10<0> ADDR_N_I<5> ADDR_N_I<4> CS04<0> CS00<2> VDD VSS / ++ RM_IHPSG13_64x32_c2_1P_DEC02 +XSEL<7> ADDR_N_I<3> ADDR_N_I<2> ADDR_N_I<1> ADDR_N_I<0> CS00<7> ECLK_H<7> ++ ECLK_H<8> ECLK_B<7> ECLK_B<8> WL_O<127> WL_O<126> WL_O<125> WL_O<124> ++ WL_O<123> WL_O<122> WL_O<121> WL_O<120> WL_O<119> WL_O<118> WL_O<117> ++ WL_O<116> WL_O<115> WL_O<114> WL_O<113> WL_O<112> VDD VSS / ++ RM_IHPSG13_64x32_c2_1P_DEC04 +XSEL<6> ADDR_N_I<3> ADDR_N_I<2> ADDR_N_I<1> ADDR_N_I<0> CS00<6> ECLK_H<6> ++ ECLK_H<7> ECLK_B<6> ECLK_B<7> WL_O<111> WL_O<110> WL_O<109> WL_O<108> ++ WL_O<107> WL_O<106> WL_O<105> WL_O<104> WL_O<103> WL_O<102> WL_O<101> ++ WL_O<100> WL_O<99> WL_O<98> WL_O<97> WL_O<96> VDD VSS / ++ RM_IHPSG13_64x32_c2_1P_DEC04 +XSEL<5> ADDR_N_I<3> ADDR_N_I<2> ADDR_N_I<1> ADDR_N_I<0> CS00<5> ECLK_H<5> ++ ECLK_H<6> ECLK_B<5> ECLK_B<6> WL_O<95> WL_O<94> WL_O<93> WL_O<92> WL_O<91> ++ WL_O<90> WL_O<89> WL_O<88> WL_O<87> WL_O<86> WL_O<85> WL_O<84> WL_O<83> ++ WL_O<82> WL_O<81> WL_O<80> VDD VSS / RM_IHPSG13_64x32_c2_1P_DEC04 +XSEL<4> ADDR_N_I<3> ADDR_N_I<2> ADDR_N_I<1> ADDR_N_I<0> CS00<4> ECLK_H<4> ++ ECLK_H<5> ECLK_B<4> ECLK_B<5> WL_O<79> WL_O<78> WL_O<77> WL_O<76> WL_O<75> ++ WL_O<74> WL_O<73> WL_O<72> WL_O<71> WL_O<70> WL_O<69> WL_O<68> WL_O<67> ++ WL_O<66> WL_O<65> WL_O<64> VDD VSS / RM_IHPSG13_64x32_c2_1P_DEC04 +XSEL<3> ADDR_N_I<3> ADDR_N_I<2> ADDR_N_I<1> ADDR_N_I<0> CS00<3> ECLK_H<3> ++ ECLK_H<4> ECLK_B<3> ECLK_B<4> WL_O<63> WL_O<62> WL_O<61> WL_O<60> WL_O<59> ++ WL_O<58> WL_O<57> WL_O<56> WL_O<55> WL_O<54> WL_O<53> WL_O<52> WL_O<51> ++ WL_O<50> WL_O<49> WL_O<48> VDD VSS / RM_IHPSG13_64x32_c2_1P_DEC04 +XSEL<2> ADDR_N_I<3> ADDR_N_I<2> ADDR_N_I<1> ADDR_N_I<0> CS00<2> ECLK_H<2> ++ ECLK_H<3> ECLK_B<2> ECLK_B<3> WL_O<47> WL_O<46> WL_O<45> WL_O<44> WL_O<43> ++ WL_O<42> WL_O<41> WL_O<40> WL_O<39> WL_O<38> WL_O<37> WL_O<36> WL_O<35> ++ WL_O<34> WL_O<33> WL_O<32> VDD VSS / RM_IHPSG13_64x32_c2_1P_DEC04 +XSEL<1> ADDR_N_I<3> ADDR_N_I<2> ADDR_N_I<1> ADDR_N_I<0> CS00<1> ECLK_H<1> ++ ECLK_H<2> ECLK_B<1> ECLK_B<2> WL_O<31> WL_O<30> WL_O<29> WL_O<28> WL_O<27> ++ WL_O<26> WL_O<25> WL_O<24> WL_O<23> WL_O<22> WL_O<21> WL_O<20> WL_O<19> ++ WL_O<18> WL_O<17> WL_O<16> VDD VSS / RM_IHPSG13_64x32_c2_1P_DEC04 +XSEL<0> ADDR_N_I<3> ADDR_N_I<2> ADDR_N_I<1> ADDR_N_I<0> CS00<0> ECLK_I ++ ECLK_H<1> ECLK_B<0> ECLK_B<1> WL_O<15> WL_O<14> WL_O<13> WL_O<12> WL_O<11> ++ WL_O<10> WL_O<9> WL_O<8> WL_O<7> WL_O<6> WL_O<5> WL_O<4> WL_O<3> WL_O<2> ++ WL_O<1> WL_O<0> VDD VSS / RM_IHPSG13_64x32_c2_1P_DEC04 +XDEC00<2> ADDR_N_I<7> ADDR_N_I<6> CS_I CS04<0> VDD VSS / ++ RM_IHPSG13_64x32_c2_1P_DEC00 +XDEC00<1> ADDR_N_I<5> ADDR_N_I<4> CS04<1> CS00<4> VDD VSS / ++ RM_IHPSG13_64x32_c2_1P_DEC00 +XDEC00<0> ADDR_N_I<5> ADDR_N_I<4> CS04<0> CS00<0> VDD VSS / ++ RM_IHPSG13_64x32_c2_1P_DEC00 +XDEC01<2> ADDR_N_I<7> ADDR_N_I<6> CS_I CS04<1> VDD VSS / ++ RM_IHPSG13_64x32_c2_1P_DEC01 +XDEC01<1> ADDR_N_I<5> ADDR_N_I<4> CS04<1> CS00<5> VDD VSS / ++ RM_IHPSG13_64x32_c2_1P_DEC01 +XDEC01<0> ADDR_N_I<5> ADDR_N_I<4> CS04<0> CS00<1> VDD VSS / ++ RM_IHPSG13_64x32_c2_1P_DEC01 +XL2<44> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<43> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<42> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<41> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<40> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<39> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<38> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<37> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<36> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<35> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<34> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<33> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<32> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<31> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<30> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<29> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<28> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<27> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<26> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<25> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<24> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<23> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<22> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<21> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<20> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<19> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<18> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<17> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<16> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<15> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<14> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<13> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<12> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<11> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<10> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<9> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<8> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<7> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<6> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<5> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<4> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<3> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<2> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<1> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI0 ADDR_N_I<7> VDD VSS / RSC_IHPSG13_TIEL +.ENDS +.SUBCKT RM_IHPSG13_64x32_c2_1P_ROWREG7 ACLK_N_I ADDR_I<6> ADDR_I<5> ADDR_I<4> ADDR_I<3> ++ ADDR_I<2> ADDR_I<1> ADDR_I<0> ADDR_N_O<6> ADDR_N_O<5> ADDR_N_O<4> ++ ADDR_N_O<3> ADDR_N_O<2> ADDR_N_O<1> ADDR_N_O<0> BIST_ADDR_I<6> ++ BIST_ADDR_I<5> BIST_ADDR_I<4> BIST_ADDR_I<3> BIST_ADDR_I<2> BIST_ADDR_I<1> ++ BIST_ADDR_I<0> BIST_EN_I VDD VSS +XINV<6> q_int<6> qn_int<6> VDD VSS / RSC_IHPSG13_CINVX2 +XINV<5> q_int<5> qn_int<5> VDD VSS / RSC_IHPSG13_CINVX2 +XINV<4> q_int<4> qn_int<4> VDD VSS / RSC_IHPSG13_CINVX2 +XINV<3> q_int<3> qn_int<3> VDD VSS / RSC_IHPSG13_CINVX2 +XINV<2> q_int<2> qn_int<2> VDD VSS / RSC_IHPSG13_CINVX2 +XINV<1> q_int<1> qn_int<1> VDD VSS / RSC_IHPSG13_CINVX2 +XINV<0> q_int<0> qn_int<0> VDD VSS / RSC_IHPSG13_CINVX2 +XDRV<6> qn_int<6> ADDR_N_O<6> VDD VSS / RSC_IHPSG13_CINVX8 +XDRV<5> qn_int<5> ADDR_N_O<5> VDD VSS / RSC_IHPSG13_CINVX8 +XDRV<4> qn_int<4> ADDR_N_O<4> VDD VSS / RSC_IHPSG13_CINVX8 +XDRV<3> qn_int<3> ADDR_N_O<3> VDD VSS / RSC_IHPSG13_CINVX8 +XDRV<2> qn_int<2> ADDR_N_O<2> VDD VSS / RSC_IHPSG13_CINVX8 +XDRV<1> qn_int<1> ADDR_N_O<1> VDD VSS / RSC_IHPSG13_CINVX8 +XDRV<0> qn_int<0> ADDR_N_O<0> VDD VSS / RSC_IHPSG13_CINVX8 +XDFF<6> BIST_EN_I BIST_ADDR_I<6> ACLK_N_I ADDR_I<6> q_int<6> net2<0> VDD ++ VSS / RSC_IHPSG13_DFNQMX2IX1 +XDFF<5> BIST_EN_I BIST_ADDR_I<5> ACLK_N_I ADDR_I<5> q_int<5> net2<1> VDD ++ VSS / RSC_IHPSG13_DFNQMX2IX1 +XDFF<4> BIST_EN_I BIST_ADDR_I<4> ACLK_N_I ADDR_I<4> q_int<4> net2<2> VDD ++ VSS / RSC_IHPSG13_DFNQMX2IX1 +XDFF<3> BIST_EN_I BIST_ADDR_I<3> ACLK_N_I ADDR_I<3> q_int<3> net2<3> VDD ++ VSS / RSC_IHPSG13_DFNQMX2IX1 +XDFF<2> BIST_EN_I BIST_ADDR_I<2> ACLK_N_I ADDR_I<2> q_int<2> net2<4> VDD ++ VSS / RSC_IHPSG13_DFNQMX2IX1 +XDFF<1> BIST_EN_I BIST_ADDR_I<1> ACLK_N_I ADDR_I<1> q_int<1> net2<5> VDD ++ VSS / RSC_IHPSG13_DFNQMX2IX1 +XDFF<0> BIST_EN_I BIST_ADDR_I<0> ACLK_N_I ADDR_I<0> q_int<0> net2<6> VDD ++ VSS / RSC_IHPSG13_DFNQMX2IX1 +XI11<8> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI11<7> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI11<6> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI11<5> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI11<4> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI11<3> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI11<2> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI11<1> VDD VSS / RSC_IHPSG13_FILLCAP8 +.ENDS + +.SUBCKT RM_IHPSG13_64x32_c2_1P_COLDRV13X8 ADDR_COL_I<1> ADDR_COL_I<0> ADDR_COL_O<1> ++ ADDR_COL_O<0> ADDR_DEC_I<7> ADDR_DEC_I<6> ADDR_DEC_I<5> ADDR_DEC_I<4> ++ ADDR_DEC_I<3> ADDR_DEC_I<2> ADDR_DEC_I<1> ADDR_DEC_I<0> ADDR_DEC_O<7> ++ ADDR_DEC_O<6> ADDR_DEC_O<5> ADDR_DEC_O<4> ADDR_DEC_O<3> ADDR_DEC_O<2> ++ ADDR_DEC_O<1> ADDR_DEC_O<0> DCLK_I DCLK_O RCLK_I RCLK_O WCLK_I WCLK_O ++ VDD VSS +XI0<1> VDD VSS / RSC_IHPSG13_FILLCAP4 +XI0<0> VDD VSS / RSC_IHPSG13_FILLCAP4 +XADDR_COL_DRV<1> ADDR_COL_I<1> ADDR_COL_O<1> VDD VSS / ++ RSC_IHPSG13_CBUFX8 +XADDR_COL_DRV<0> ADDR_COL_I<0> ADDR_COL_O<0> VDD VSS / ++ RSC_IHPSG13_CBUFX8 +XADDR_DEC_DRV<7> ADDR_DEC_I<7> ADDR_DEC_O<7> VDD VSS / ++ RSC_IHPSG13_CBUFX8 +XADDR_DEC_DRV<6> ADDR_DEC_I<6> ADDR_DEC_O<6> VDD VSS / ++ RSC_IHPSG13_CBUFX8 +XADDR_DEC_DRV<5> ADDR_DEC_I<5> ADDR_DEC_O<5> VDD VSS / ++ RSC_IHPSG13_CBUFX8 +XADDR_DEC_DRV<4> ADDR_DEC_I<4> ADDR_DEC_O<4> VDD VSS / ++ RSC_IHPSG13_CBUFX8 +XADDR_DEC_DRV<3> ADDR_DEC_I<3> ADDR_DEC_O<3> VDD VSS / ++ RSC_IHPSG13_CBUFX8 +XADDR_DEC_DRV<2> ADDR_DEC_I<2> ADDR_DEC_O<2> VDD VSS / ++ RSC_IHPSG13_CBUFX8 +XADDR_DEC_DRV<1> ADDR_DEC_I<1> ADDR_DEC_O<1> VDD VSS / ++ RSC_IHPSG13_CBUFX8 +XADDR_DEC_DRV<0> ADDR_DEC_I<0> ADDR_DEC_O<0> VDD VSS / ++ RSC_IHPSG13_CBUFX8 +XDCLK_DRV DCLK_I DCLK_O VDD VSS / RSC_IHPSG13_CBUFX8 +XRCLK_DRV RCLK_I RCLK_O VDD VSS / RSC_IHPSG13_CBUFX8 +XWCLK_DRV WCLK_I WCLK_O VDD VSS / RSC_IHPSG13_CBUFX8 +.ENDS +.SUBCKT RM_IHPSG13_64x32_c2_1P_WLDRV16X8 A<15> A<14> A<13> A<12> A<11> A<10> A<9> A<8> ++ A<7> A<6> A<5> A<4> A<3> A<2> A<1> A<0> Z<15> Z<14> Z<13> Z<12> Z<11> Z<10> ++ Z<9> Z<8> Z<7> Z<6> Z<5> Z<4> Z<3> Z<2> Z<1> Z<0> VDD VSS +XBUF<15> A<15> Z<15> VDD VSS / RSC_IHPSG13_WLDRVX8 +XBUF<14> A<14> Z<14> VDD VSS / RSC_IHPSG13_WLDRVX8 +XBUF<13> A<13> Z<13> VDD VSS / RSC_IHPSG13_WLDRVX8 +XBUF<12> A<12> Z<12> VDD VSS / RSC_IHPSG13_WLDRVX8 +XBUF<11> A<11> Z<11> VDD VSS / RSC_IHPSG13_WLDRVX8 +XBUF<10> A<10> Z<10> VDD VSS / RSC_IHPSG13_WLDRVX8 +XBUF<9> A<9> Z<9> VDD VSS / RSC_IHPSG13_WLDRVX8 +XBUF<8> A<8> Z<8> VDD VSS / RSC_IHPSG13_WLDRVX8 +XBUF<7> A<7> Z<7> VDD VSS / RSC_IHPSG13_WLDRVX8 +XBUF<6> A<6> Z<6> VDD VSS / RSC_IHPSG13_WLDRVX8 +XBUF<5> A<5> Z<5> VDD VSS / RSC_IHPSG13_WLDRVX8 +XBUF<4> A<4> Z<4> VDD VSS / RSC_IHPSG13_WLDRVX8 +XBUF<3> A<3> Z<3> VDD VSS / RSC_IHPSG13_WLDRVX8 +XBUF<2> A<2> Z<2> VDD VSS / RSC_IHPSG13_WLDRVX8 +XBUF<1> A<1> Z<1> VDD VSS / RSC_IHPSG13_WLDRVX8 +XBUF<0> A<0> Z<0> VDD VSS / RSC_IHPSG13_WLDRVX8 +.ENDS + + + +.SUBCKT RM_IHPSG13_64x32_c2_1P_ROWDEC6 ADDR_N_I<5> ADDR_N_I<4> ADDR_N_I<3> ADDR_N_I<2> ++ ADDR_N_I<1> ADDR_N_I<0> CS_I ECLK_I WL_O<63> WL_O<62> WL_O<61> WL_O<60> ++ WL_O<59> WL_O<58> WL_O<57> WL_O<56> WL_O<55> WL_O<54> WL_O<53> WL_O<52> ++ WL_O<51> WL_O<50> WL_O<49> WL_O<48> WL_O<47> WL_O<46> WL_O<45> WL_O<44> ++ WL_O<43> WL_O<42> WL_O<41> WL_O<40> WL_O<39> WL_O<38> WL_O<37> WL_O<36> ++ WL_O<35> WL_O<34> WL_O<33> WL_O<32> WL_O<31> WL_O<30> WL_O<29> WL_O<28> ++ WL_O<27> WL_O<26> WL_O<25> WL_O<24> WL_O<23> WL_O<22> WL_O<21> WL_O<20> ++ WL_O<19> WL_O<18> WL_O<17> WL_O<16> WL_O<15> WL_O<14> WL_O<13> WL_O<12> ++ WL_O<11> WL_O<10> WL_O<9> WL_O<8> WL_O<7> WL_O<6> WL_O<5> WL_O<4> WL_O<3> ++ WL_O<2> WL_O<1> WL_O<0> VDD VSS +XDEC11 ADDR_N_I<5> ADDR_N_I<4> CS_I CS00<3> VDD VSS / ++ RM_IHPSG13_64x32_c2_1P_DEC03 +XDEC00 ADDR_N_I<5> ADDR_N_I<4> CS_I CS00<0> VDD VSS / ++ RM_IHPSG13_64x32_c2_1P_DEC00 +XDEC01 ADDR_N_I<5> ADDR_N_I<4> CS_I CS00<1> VDD VSS / ++ RM_IHPSG13_64x32_c2_1P_DEC01 +XDEC10 ADDR_N_I<5> ADDR_N_I<4> CS_I CS00<2> VDD VSS / ++ RM_IHPSG13_64x32_c2_1P_DEC02 +XSEL<3> ADDR_N_I<3> ADDR_N_I<2> ADDR_N_I<1> ADDR_N_I<0> CS00<3> ECLK_H<3> ++ ECLK_H<4> ECLK_B<3> ECLK_B<4> WL_O<63> WL_O<62> WL_O<61> WL_O<60> WL_O<59> ++ WL_O<58> WL_O<57> WL_O<56> WL_O<55> WL_O<54> WL_O<53> WL_O<52> WL_O<51> ++ WL_O<50> WL_O<49> WL_O<48> VDD VSS / RM_IHPSG13_64x32_c2_1P_DEC04 +XSEL<2> ADDR_N_I<3> ADDR_N_I<2> ADDR_N_I<1> ADDR_N_I<0> CS00<2> ECLK_H<2> ++ ECLK_H<3> ECLK_B<2> ECLK_B<3> WL_O<47> WL_O<46> WL_O<45> WL_O<44> WL_O<43> ++ WL_O<42> WL_O<41> WL_O<40> WL_O<39> WL_O<38> WL_O<37> WL_O<36> WL_O<35> ++ WL_O<34> WL_O<33> WL_O<32> VDD VSS / RM_IHPSG13_64x32_c2_1P_DEC04 +XSEL<1> ADDR_N_I<3> ADDR_N_I<2> ADDR_N_I<1> ADDR_N_I<0> CS00<1> ECLK_H<1> ++ ECLK_H<2> ECLK_B<1> ECLK_B<2> WL_O<31> WL_O<30> WL_O<29> WL_O<28> WL_O<27> ++ WL_O<26> WL_O<25> WL_O<24> WL_O<23> WL_O<22> WL_O<21> WL_O<20> WL_O<19> ++ WL_O<18> WL_O<17> WL_O<16> VDD VSS / RM_IHPSG13_64x32_c2_1P_DEC04 +XSEL<0> ADDR_N_I<3> ADDR_N_I<2> ADDR_N_I<1> ADDR_N_I<0> CS00<0> ECLK_I ++ ECLK_H<1> ECLK_B<0> ECLK_B<1> WL_O<15> WL_O<14> WL_O<13> WL_O<12> WL_O<11> ++ WL_O<10> WL_O<9> WL_O<8> WL_O<7> WL_O<6> WL_O<5> WL_O<4> WL_O<3> WL_O<2> ++ WL_O<1> WL_O<0> VDD VSS / RM_IHPSG13_64x32_c2_1P_DEC04 +XL2<24> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<23> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<22> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<21> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<20> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<19> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<18> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<17> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<16> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<15> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<14> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<13> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<12> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<11> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<10> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<9> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<8> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<7> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<6> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<5> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<4> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<3> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<2> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<1> VDD VSS / RSC_IHPSG13_FILLCAP8 +.ENDS +.SUBCKT RM_IHPSG13_64x32_c2_1P_ROWREG6 ACLK_N_I ADDR_I<5> ADDR_I<4> ADDR_I<3> ADDR_I<2> ++ ADDR_I<1> ADDR_I<0> ADDR_N_O<5> ADDR_N_O<4> ADDR_N_O<3> ADDR_N_O<2> ++ ADDR_N_O<1> ADDR_N_O<0> BIST_ADDR_I<5> BIST_ADDR_I<4> BIST_ADDR_I<3> ++ BIST_ADDR_I<2> BIST_ADDR_I<1> BIST_ADDR_I<0> BIST_EN_I VDD VSS +XINV<5> q_int<5> qn_int<5> VDD VSS / RSC_IHPSG13_CINVX2 +XINV<4> q_int<4> qn_int<4> VDD VSS / RSC_IHPSG13_CINVX2 +XINV<3> q_int<3> qn_int<3> VDD VSS / RSC_IHPSG13_CINVX2 +XINV<2> q_int<2> qn_int<2> VDD VSS / RSC_IHPSG13_CINVX2 +XINV<1> q_int<1> qn_int<1> VDD VSS / RSC_IHPSG13_CINVX2 +XINV<0> q_int<0> qn_int<0> VDD VSS / RSC_IHPSG13_CINVX2 +XDRV<5> qn_int<5> ADDR_N_O<5> VDD VSS / RSC_IHPSG13_CINVX8 +XDRV<4> qn_int<4> ADDR_N_O<4> VDD VSS / RSC_IHPSG13_CINVX8 +XDRV<3> qn_int<3> ADDR_N_O<3> VDD VSS / RSC_IHPSG13_CINVX8 +XDRV<2> qn_int<2> ADDR_N_O<2> VDD VSS / RSC_IHPSG13_CINVX8 +XDRV<1> qn_int<1> ADDR_N_O<1> VDD VSS / RSC_IHPSG13_CINVX8 +XDRV<0> qn_int<0> ADDR_N_O<0> VDD VSS / RSC_IHPSG13_CINVX8 +XDFF<5> BIST_EN_I BIST_ADDR_I<5> ACLK_N_I ADDR_I<5> q_int<5> net2<0> VDD ++ VSS / RSC_IHPSG13_DFNQMX2IX1 +XDFF<4> BIST_EN_I BIST_ADDR_I<4> ACLK_N_I ADDR_I<4> q_int<4> net2<1> VDD ++ VSS / RSC_IHPSG13_DFNQMX2IX1 +XDFF<3> BIST_EN_I BIST_ADDR_I<3> ACLK_N_I ADDR_I<3> q_int<3> net2<2> VDD ++ VSS / RSC_IHPSG13_DFNQMX2IX1 +XDFF<2> BIST_EN_I BIST_ADDR_I<2> ACLK_N_I ADDR_I<2> q_int<2> net2<3> VDD ++ VSS / RSC_IHPSG13_DFNQMX2IX1 +XDFF<1> BIST_EN_I BIST_ADDR_I<1> ACLK_N_I ADDR_I<1> q_int<1> net2<4> VDD ++ VSS / RSC_IHPSG13_DFNQMX2IX1 +XDFF<0> BIST_EN_I BIST_ADDR_I<0> ACLK_N_I ADDR_I<0> q_int<0> net2<5> VDD ++ VSS / RSC_IHPSG13_DFNQMX2IX1 +XI11<12> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI11<11> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI11<10> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI11<9> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI11<8> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI11<7> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI11<6> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI11<5> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI11<4> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI11<3> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI11<2> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI11<1> VDD VSS / RSC_IHPSG13_FILLCAP8 +.ENDS + + +.SUBCKT RM_IHPSG13_64x32_c2_2P_COLUMN_pcell_0 A_BLC_BOT<1> A_BLC_BOT<0> A_BLC_TOP<1> A_BLC_TOP<0> A_BLT_BOT<1> A_BLT_BOT<0> A_BLT_TOP<1> A_BLT_TOP<0> A_LWL<15> A_LWL<14> A_LWL<13> A_LWL<12> A_LWL<11> A_LWL<10> A_LWL<9> A_LWL<8> A_LWL<7> A_LWL<6> A_LWL<5> A_LWL<4> A_LWL<3> A_LWL<2> A_LWL<1> A_LWL<0> A_RWL<15> A_RWL<14> A_RWL<13> A_RWL<12> A_RWL<11> A_RWL<10> A_RWL<9> A_RWL<8> A_RWL<7> A_RWL<6> A_RWL<5> A_RWL<4> A_RWL<3> A_RWL<2> A_RWL<1> A_RWL<0> B_BLC_BOT<1> B_BLC_BOT<0> B_BLC_TOP<1> B_BLC_TOP<0> B_BLT_BOT<1> B_BLT_BOT<0> B_BLT_TOP<1> B_BLT_TOP<0> B_LWL<15> B_LWL<14> B_LWL<13> B_LWL<12> B_LWL<11> B_LWL<10> B_LWL<9> B_LWL<8> B_LWL<7> B_LWL<6> B_LWL<5> B_LWL<4> B_LWL<3> B_LWL<2> B_LWL<1> B_LWL<0> B_RWL<15> B_RWL<14> B_RWL<13> B_RWL<12> B_RWL<11> B_RWL<10> B_RWL<9> B_RWL<8> B_RWL<7> B_RWL<6> B_RWL<5> B_RWL<4> B_RWL<3> B_RWL<2> B_RWL<1> B_RWL<0> VDD_CORE VSS +XRAM A_BLC_BOT<1> A_BLC_BOT<0> A_BLC_TOP<1> A_BLC_TOP<0> A_BLT_BOT<1> A_BLT_BOT<0> A_BLT_TOP<1> A_BLT_TOP<0> A_LWL<15> A_LWL<14> A_LWL<13> A_LWL<12> A_LWL<11> A_LWL<10> A_LWL<9> A_LWL<8> A_LWL<7> A_LWL<6> A_LWL<5> A_LWL<4> A_LWL<3> A_LWL<2> A_LWL<1> A_LWL<0> A_RWL<15> A_RWL<14> A_RWL<13> A_RWL<12> A_RWL<11> A_RWL<10> A_RWL<9> A_RWL<8> A_RWL<7> A_RWL<6> A_RWL<5> A_RWL<4> A_RWL<3> A_RWL<2> A_RWL<1> A_RWL<0> B_BLC_BOT<1> B_BLC_BOT<0> B_BLC_TOP<1> B_BLC_TOP<0> B_BLT_BOT<1> B_BLT_BOT<0> B_BLT_TOP<1> B_BLT_TOP<0> B_LWL<15> B_LWL<14> B_LWL<13> B_LWL<12> B_LWL<11> B_LWL<10> B_LWL<9> B_LWL<8> B_LWL<7> B_LWL<6> B_LWL<5> B_LWL<4> B_LWL<3> B_LWL<2> B_LWL<1> B_LWL<0> B_RWL<15> B_RWL<14> B_RWL<13> B_RWL<12> B_RWL<11> B_RWL<10> B_RWL<9> B_RWL<8> B_RWL<7> B_RWL<6> B_RWL<5> B_RWL<4> B_RWL<3> B_RWL<2> B_RWL<1> B_RWL<0> VDD_CORE VSS / RM_IHPSG13_64x32_c2_2P_BITKIT_16x2_SRAM +XEDGE<1> A_BLC_TOP<1> A_BLC_TOP<0> A_BLT_TOP<1> A_BLT_TOP<0> B_BLC_TOP<1> B_BLC_TOP<0> B_BLT_TOP<1> B_BLT_TOP<0> VDD_CORE VSS / RM_IHPSG13_64x32_c2_2P_BITKIT_16x2_EDGE_TB +XEDGE<0> A_BLC_BOT<1> A_BLC_BOT<0> A_BLT_BOT<1> A_BLT_BOT<0> B_BLC_BOT<1> B_BLC_BOT<0> B_BLT_BOT<1> B_BLT_BOT<0> VDD_CORE VSS / RM_IHPSG13_64x32_c2_2P_BITKIT_16x2_EDGE_TB +.ENDS + + + + +.SUBCKT RM_IHPSG13_64x32_c2_2P_MATRIX_pcell_1 A_BLC<63> A_BLC<62> A_BLC<61> A_BLC<60> A_BLC<59> A_BLC<58> A_BLC<57> A_BLC<56> A_BLC<55> A_BLC<54> A_BLC<53> A_BLC<52> A_BLC<51> A_BLC<50> A_BLC<49> A_BLC<48> A_BLC<47> A_BLC<46> A_BLC<45> A_BLC<44> A_BLC<43> A_BLC<42> A_BLC<41> A_BLC<40> A_BLC<39> A_BLC<38> A_BLC<37> A_BLC<36> A_BLC<35> A_BLC<34> A_BLC<33> A_BLC<32> A_BLC<31> A_BLC<30> A_BLC<29> A_BLC<28> A_BLC<27> A_BLC<26> A_BLC<25> A_BLC<24> A_BLC<23> A_BLC<22> A_BLC<21> A_BLC<20> A_BLC<19> A_BLC<18> A_BLC<17> A_BLC<16> A_BLC<15> A_BLC<14> A_BLC<13> A_BLC<12> A_BLC<11> A_BLC<10> A_BLC<9> A_BLC<8> A_BLC<7> A_BLC<6> A_BLC<5> A_BLC<4> A_BLC<3> A_BLC<2> A_BLC<1> A_BLC<0> A_BLT<63> A_BLT<62> A_BLT<61> A_BLT<60> A_BLT<59> A_BLT<58> A_BLT<57> A_BLT<56> A_BLT<55> A_BLT<54> A_BLT<53> A_BLT<52> A_BLT<51> A_BLT<50> A_BLT<49> A_BLT<48> A_BLT<47> A_BLT<46> A_BLT<45> A_BLT<44> A_BLT<43> A_BLT<42> A_BLT<41> A_BLT<40> A_BLT<39> A_BLT<38> A_BLT<37> A_BLT<36> A_BLT<35> A_BLT<34> A_BLT<33> A_BLT<32> A_BLT<31> A_BLT<30> A_BLT<29> A_BLT<28> A_BLT<27> A_BLT<26> A_BLT<25> A_BLT<24> A_BLT<23> A_BLT<22> A_BLT<21> A_BLT<20> A_BLT<19> A_BLT<18> A_BLT<17> A_BLT<16> A_BLT<15> A_BLT<14> A_BLT<13> A_BLT<12> A_BLT<11> A_BLT<10> A_BLT<9> A_BLT<8> A_BLT<7> A_BLT<6> A_BLT<5> A_BLT<4> A_BLT<3> A_BLT<2> A_BLT<1> A_BLT<0> A_WL<15> A_WL<14> A_WL<13> A_WL<12> A_WL<11> A_WL<10> A_WL<9> A_WL<8> A_WL<7> A_WL<6> A_WL<5> A_WL<4> A_WL<3> A_WL<2> A_WL<1> A_WL<0> B_BLC<63> B_BLC<62> B_BLC<61> B_BLC<60> B_BLC<59> B_BLC<58> B_BLC<57> B_BLC<56> B_BLC<55> B_BLC<54> B_BLC<53> B_BLC<52> B_BLC<51> B_BLC<50> B_BLC<49> B_BLC<48> B_BLC<47> B_BLC<46> B_BLC<45> B_BLC<44> B_BLC<43> B_BLC<42> B_BLC<41> B_BLC<40> B_BLC<39> B_BLC<38> B_BLC<37> B_BLC<36> B_BLC<35> B_BLC<34> B_BLC<33> B_BLC<32> B_BLC<31> B_BLC<30> B_BLC<29> B_BLC<28> B_BLC<27> B_BLC<26> B_BLC<25> B_BLC<24> B_BLC<23> B_BLC<22> B_BLC<21> B_BLC<20> B_BLC<19> B_BLC<18> B_BLC<17> B_BLC<16> B_BLC<15> B_BLC<14> B_BLC<13> B_BLC<12> B_BLC<11> B_BLC<10> B_BLC<9> B_BLC<8> B_BLC<7> B_BLC<6> B_BLC<5> B_BLC<4> B_BLC<3> B_BLC<2> B_BLC<1> B_BLC<0> B_BLT<63> B_BLT<62> B_BLT<61> B_BLT<60> B_BLT<59> B_BLT<58> B_BLT<57> B_BLT<56> B_BLT<55> B_BLT<54> B_BLT<53> B_BLT<52> B_BLT<51> B_BLT<50> B_BLT<49> B_BLT<48> B_BLT<47> B_BLT<46> B_BLT<45> B_BLT<44> B_BLT<43> B_BLT<42> B_BLT<41> B_BLT<40> B_BLT<39> B_BLT<38> B_BLT<37> B_BLT<36> B_BLT<35> B_BLT<34> B_BLT<33> B_BLT<32> B_BLT<31> B_BLT<30> B_BLT<29> B_BLT<28> B_BLT<27> B_BLT<26> B_BLT<25> B_BLT<24> B_BLT<23> B_BLT<22> B_BLT<21> B_BLT<20> B_BLT<19> B_BLT<18> B_BLT<17> B_BLT<16> B_BLT<15> B_BLT<14> B_BLT<13> B_BLT<12> B_BLT<11> B_BLT<10> B_BLT<9> B_BLT<8> B_BLT<7> B_BLT<6> B_BLT<5> B_BLT<4> B_BLT<3> B_BLT<2> B_BLT<1> B_BLT<0> B_WL<15> B_WL<14> B_WL<13> B_WL<12> B_WL<11> B_WL<10> B_WL<9> B_WL<8> B_WL<7> B_WL<6> B_WL<5> B_WL<4> B_WL<3> B_WL<2> B_WL<1> B_WL<0> VDD_CORE VSS +XCORNER<3> VDD_CORE VSS / RM_IHPSG13_64x32_c2_2P_BITKIT_16x2_CORNER +XCORNER<2> VDD_CORE VSS / RM_IHPSG13_64x32_c2_2P_BITKIT_16x2_CORNER +XCORNER<1> VDD_CORE VSS / RM_IHPSG13_64x32_c2_2P_BITKIT_16x2_CORNER +XCORNER<0> VDD_CORE VSS / RM_IHPSG13_64x32_c2_2P_BITKIT_16x2_CORNER +XRAMEDGE_L<0> A_WL<15> A_WL<14> A_WL<13> A_WL<12> A_WL<11> A_WL<10> A_WL<9> A_WL<8> A_WL<7> A_WL<6> A_WL<5> A_WL<4> A_WL<3> A_WL<2> A_WL<1> A_WL<0> B_WL<15> B_WL<14> B_WL<13> B_WL<12> B_WL<11> B_WL<10> B_WL<9> B_WL<8> B_WL<7> B_WL<6> B_WL<5> B_WL<4> B_WL<3> B_WL<2> B_WL<1> B_WL<0> VDD_CORE VSS / RM_IHPSG13_64x32_c2_2P_BITKIT_16x2_EDGE_LR +XRAMEDGE_R<0> A_IWL<511> A_IWL<510> A_IWL<509> A_IWL<508> A_IWL<507> A_IWL<506> A_IWL<505> A_IWL<504> A_IWL<503> A_IWL<502> A_IWL<501> A_IWL<500> A_IWL<499> A_IWL<498> A_IWL<497> A_IWL<496> B_IWL<511> B_IWL<510> B_IWL<509> B_IWL<508> B_IWL<507> B_IWL<506> B_IWL<505> B_IWL<504> B_IWL<503> B_IWL<502> B_IWL<501> B_IWL<500> B_IWL<499> B_IWL<498> B_IWL<497> B_IWL<496> VDD_CORE VSS / RM_IHPSG13_64x32_c2_2P_BITKIT_16x2_EDGE_LR +XCOL<31> A_BLC<63> A_BLC<62> A_BLC_TOP<63> A_BLC_TOP<62> A_BLT<63> A_BLT<62> A_BLT_TOP<63> A_BLT_TOP<62> A_IWL<495> A_IWL<494> A_IWL<493> A_IWL<492> A_IWL<491> A_IWL<490> A_IWL<489> A_IWL<488> A_IWL<487> A_IWL<486> A_IWL<485> A_IWL<484> A_IWL<483> A_IWL<482> A_IWL<481> A_IWL<480> A_IWL<511> A_IWL<510> A_IWL<509> A_IWL<508> A_IWL<507> A_IWL<506> A_IWL<505> A_IWL<504> A_IWL<503> A_IWL<502> A_IWL<501> A_IWL<500> A_IWL<499> A_IWL<498> A_IWL<497> A_IWL<496> B_BLC<63> B_BLC<62> B_BLC_TOP<63> B_BLC_TOP<62> B_BLT<63> B_BLT<62> B_BLT_TOP<63> B_BLT_TOP<62> B_IWL<495> B_IWL<494> B_IWL<493> B_IWL<492> B_IWL<491> B_IWL<490> B_IWL<489> B_IWL<488> B_IWL<487> B_IWL<486> B_IWL<485> B_IWL<484> B_IWL<483> B_IWL<482> B_IWL<481> B_IWL<480> B_IWL<511> B_IWL<510> B_IWL<509> B_IWL<508> B_IWL<507> B_IWL<506> B_IWL<505> B_IWL<504> B_IWL<503> B_IWL<502> B_IWL<501> B_IWL<500> B_IWL<499> B_IWL<498> B_IWL<497> B_IWL<496> VDD_CORE VSS / RM_IHPSG13_64x32_c2_2P_COLUMN_pcell_0 +XCOL<30> A_BLC<61> A_BLC<60> A_BLC_TOP<61> A_BLC_TOP<60> A_BLT<61> A_BLT<60> A_BLT_TOP<61> A_BLT_TOP<60> A_IWL<479> A_IWL<478> A_IWL<477> A_IWL<476> A_IWL<475> A_IWL<474> A_IWL<473> A_IWL<472> A_IWL<471> A_IWL<470> A_IWL<469> A_IWL<468> A_IWL<467> A_IWL<466> A_IWL<465> A_IWL<464> A_IWL<495> A_IWL<494> A_IWL<493> A_IWL<492> A_IWL<491> A_IWL<490> A_IWL<489> A_IWL<488> A_IWL<487> A_IWL<486> A_IWL<485> A_IWL<484> A_IWL<483> A_IWL<482> A_IWL<481> A_IWL<480> B_BLC<61> B_BLC<60> B_BLC_TOP<61> B_BLC_TOP<60> B_BLT<61> B_BLT<60> B_BLT_TOP<61> B_BLT_TOP<60> B_IWL<479> B_IWL<478> B_IWL<477> B_IWL<476> B_IWL<475> B_IWL<474> B_IWL<473> B_IWL<472> B_IWL<471> B_IWL<470> B_IWL<469> B_IWL<468> B_IWL<467> B_IWL<466> B_IWL<465> B_IWL<464> B_IWL<495> B_IWL<494> B_IWL<493> B_IWL<492> B_IWL<491> B_IWL<490> B_IWL<489> B_IWL<488> B_IWL<487> B_IWL<486> B_IWL<485> B_IWL<484> B_IWL<483> B_IWL<482> B_IWL<481> B_IWL<480> VDD_CORE VSS / RM_IHPSG13_64x32_c2_2P_COLUMN_pcell_0 +XCOL<29> A_BLC<59> A_BLC<58> A_BLC_TOP<59> A_BLC_TOP<58> A_BLT<59> A_BLT<58> A_BLT_TOP<59> A_BLT_TOP<58> A_IWL<463> A_IWL<462> A_IWL<461> A_IWL<460> A_IWL<459> A_IWL<458> A_IWL<457> A_IWL<456> A_IWL<455> A_IWL<454> A_IWL<453> A_IWL<452> A_IWL<451> A_IWL<450> A_IWL<449> A_IWL<448> A_IWL<479> A_IWL<478> A_IWL<477> A_IWL<476> A_IWL<475> A_IWL<474> A_IWL<473> A_IWL<472> A_IWL<471> A_IWL<470> A_IWL<469> A_IWL<468> A_IWL<467> A_IWL<466> A_IWL<465> A_IWL<464> B_BLC<59> B_BLC<58> B_BLC_TOP<59> B_BLC_TOP<58> B_BLT<59> B_BLT<58> B_BLT_TOP<59> B_BLT_TOP<58> B_IWL<463> B_IWL<462> B_IWL<461> B_IWL<460> B_IWL<459> B_IWL<458> B_IWL<457> B_IWL<456> B_IWL<455> B_IWL<454> B_IWL<453> B_IWL<452> B_IWL<451> B_IWL<450> B_IWL<449> B_IWL<448> B_IWL<479> B_IWL<478> B_IWL<477> B_IWL<476> B_IWL<475> B_IWL<474> B_IWL<473> B_IWL<472> B_IWL<471> B_IWL<470> B_IWL<469> B_IWL<468> B_IWL<467> B_IWL<466> B_IWL<465> B_IWL<464> VDD_CORE VSS / RM_IHPSG13_64x32_c2_2P_COLUMN_pcell_0 +XCOL<28> A_BLC<57> A_BLC<56> A_BLC_TOP<57> A_BLC_TOP<56> A_BLT<57> A_BLT<56> A_BLT_TOP<57> A_BLT_TOP<56> A_IWL<447> A_IWL<446> A_IWL<445> A_IWL<444> A_IWL<443> A_IWL<442> A_IWL<441> A_IWL<440> A_IWL<439> A_IWL<438> A_IWL<437> A_IWL<436> A_IWL<435> A_IWL<434> A_IWL<433> A_IWL<432> A_IWL<463> A_IWL<462> A_IWL<461> A_IWL<460> A_IWL<459> A_IWL<458> A_IWL<457> A_IWL<456> A_IWL<455> A_IWL<454> A_IWL<453> A_IWL<452> A_IWL<451> A_IWL<450> A_IWL<449> A_IWL<448> B_BLC<57> B_BLC<56> B_BLC_TOP<57> B_BLC_TOP<56> B_BLT<57> B_BLT<56> B_BLT_TOP<57> B_BLT_TOP<56> B_IWL<447> B_IWL<446> B_IWL<445> B_IWL<444> B_IWL<443> B_IWL<442> B_IWL<441> B_IWL<440> B_IWL<439> B_IWL<438> B_IWL<437> B_IWL<436> B_IWL<435> B_IWL<434> B_IWL<433> B_IWL<432> B_IWL<463> B_IWL<462> B_IWL<461> B_IWL<460> B_IWL<459> B_IWL<458> B_IWL<457> B_IWL<456> B_IWL<455> B_IWL<454> B_IWL<453> B_IWL<452> B_IWL<451> B_IWL<450> B_IWL<449> B_IWL<448> VDD_CORE VSS / RM_IHPSG13_64x32_c2_2P_COLUMN_pcell_0 +XCOL<27> A_BLC<55> A_BLC<54> A_BLC_TOP<55> A_BLC_TOP<54> A_BLT<55> A_BLT<54> A_BLT_TOP<55> A_BLT_TOP<54> A_IWL<431> A_IWL<430> A_IWL<429> A_IWL<428> A_IWL<427> A_IWL<426> A_IWL<425> A_IWL<424> A_IWL<423> A_IWL<422> A_IWL<421> A_IWL<420> A_IWL<419> A_IWL<418> A_IWL<417> A_IWL<416> A_IWL<447> A_IWL<446> A_IWL<445> A_IWL<444> A_IWL<443> A_IWL<442> A_IWL<441> A_IWL<440> A_IWL<439> A_IWL<438> A_IWL<437> A_IWL<436> A_IWL<435> A_IWL<434> A_IWL<433> A_IWL<432> B_BLC<55> B_BLC<54> B_BLC_TOP<55> B_BLC_TOP<54> B_BLT<55> B_BLT<54> B_BLT_TOP<55> B_BLT_TOP<54> B_IWL<431> B_IWL<430> B_IWL<429> B_IWL<428> B_IWL<427> B_IWL<426> B_IWL<425> B_IWL<424> B_IWL<423> B_IWL<422> B_IWL<421> B_IWL<420> B_IWL<419> B_IWL<418> B_IWL<417> B_IWL<416> B_IWL<447> B_IWL<446> B_IWL<445> B_IWL<444> B_IWL<443> B_IWL<442> B_IWL<441> B_IWL<440> B_IWL<439> B_IWL<438> B_IWL<437> B_IWL<436> B_IWL<435> B_IWL<434> B_IWL<433> B_IWL<432> VDD_CORE VSS / RM_IHPSG13_64x32_c2_2P_COLUMN_pcell_0 +XCOL<26> A_BLC<53> A_BLC<52> A_BLC_TOP<53> A_BLC_TOP<52> A_BLT<53> A_BLT<52> A_BLT_TOP<53> A_BLT_TOP<52> A_IWL<415> A_IWL<414> A_IWL<413> A_IWL<412> A_IWL<411> A_IWL<410> A_IWL<409> A_IWL<408> A_IWL<407> A_IWL<406> A_IWL<405> A_IWL<404> A_IWL<403> A_IWL<402> A_IWL<401> A_IWL<400> A_IWL<431> A_IWL<430> A_IWL<429> A_IWL<428> A_IWL<427> A_IWL<426> A_IWL<425> A_IWL<424> A_IWL<423> A_IWL<422> A_IWL<421> A_IWL<420> A_IWL<419> A_IWL<418> A_IWL<417> A_IWL<416> B_BLC<53> B_BLC<52> B_BLC_TOP<53> B_BLC_TOP<52> B_BLT<53> B_BLT<52> B_BLT_TOP<53> B_BLT_TOP<52> B_IWL<415> B_IWL<414> B_IWL<413> B_IWL<412> B_IWL<411> B_IWL<410> B_IWL<409> B_IWL<408> B_IWL<407> B_IWL<406> B_IWL<405> B_IWL<404> B_IWL<403> B_IWL<402> B_IWL<401> B_IWL<400> B_IWL<431> B_IWL<430> B_IWL<429> B_IWL<428> B_IWL<427> B_IWL<426> B_IWL<425> B_IWL<424> B_IWL<423> B_IWL<422> B_IWL<421> B_IWL<420> B_IWL<419> B_IWL<418> B_IWL<417> B_IWL<416> VDD_CORE VSS / RM_IHPSG13_64x32_c2_2P_COLUMN_pcell_0 +XCOL<25> A_BLC<51> A_BLC<50> A_BLC_TOP<51> A_BLC_TOP<50> A_BLT<51> A_BLT<50> A_BLT_TOP<51> A_BLT_TOP<50> A_IWL<399> A_IWL<398> A_IWL<397> A_IWL<396> A_IWL<395> A_IWL<394> A_IWL<393> A_IWL<392> A_IWL<391> A_IWL<390> A_IWL<389> A_IWL<388> A_IWL<387> A_IWL<386> A_IWL<385> A_IWL<384> A_IWL<415> A_IWL<414> A_IWL<413> A_IWL<412> A_IWL<411> A_IWL<410> A_IWL<409> A_IWL<408> A_IWL<407> A_IWL<406> A_IWL<405> A_IWL<404> A_IWL<403> A_IWL<402> A_IWL<401> A_IWL<400> B_BLC<51> B_BLC<50> B_BLC_TOP<51> B_BLC_TOP<50> B_BLT<51> B_BLT<50> B_BLT_TOP<51> B_BLT_TOP<50> B_IWL<399> B_IWL<398> B_IWL<397> B_IWL<396> B_IWL<395> B_IWL<394> B_IWL<393> B_IWL<392> B_IWL<391> B_IWL<390> B_IWL<389> B_IWL<388> B_IWL<387> B_IWL<386> B_IWL<385> B_IWL<384> B_IWL<415> B_IWL<414> B_IWL<413> B_IWL<412> B_IWL<411> B_IWL<410> B_IWL<409> B_IWL<408> B_IWL<407> B_IWL<406> B_IWL<405> B_IWL<404> B_IWL<403> B_IWL<402> B_IWL<401> B_IWL<400> VDD_CORE VSS / RM_IHPSG13_64x32_c2_2P_COLUMN_pcell_0 +XCOL<24> A_BLC<49> A_BLC<48> A_BLC_TOP<49> A_BLC_TOP<48> A_BLT<49> A_BLT<48> A_BLT_TOP<49> A_BLT_TOP<48> A_IWL<383> A_IWL<382> A_IWL<381> A_IWL<380> A_IWL<379> A_IWL<378> A_IWL<377> A_IWL<376> A_IWL<375> A_IWL<374> A_IWL<373> A_IWL<372> A_IWL<371> A_IWL<370> A_IWL<369> A_IWL<368> A_IWL<399> A_IWL<398> A_IWL<397> A_IWL<396> A_IWL<395> A_IWL<394> A_IWL<393> A_IWL<392> A_IWL<391> A_IWL<390> A_IWL<389> A_IWL<388> A_IWL<387> A_IWL<386> A_IWL<385> A_IWL<384> B_BLC<49> B_BLC<48> B_BLC_TOP<49> B_BLC_TOP<48> B_BLT<49> B_BLT<48> B_BLT_TOP<49> B_BLT_TOP<48> B_IWL<383> B_IWL<382> B_IWL<381> B_IWL<380> B_IWL<379> B_IWL<378> B_IWL<377> B_IWL<376> B_IWL<375> B_IWL<374> B_IWL<373> B_IWL<372> B_IWL<371> B_IWL<370> B_IWL<369> B_IWL<368> B_IWL<399> B_IWL<398> B_IWL<397> B_IWL<396> B_IWL<395> B_IWL<394> B_IWL<393> B_IWL<392> B_IWL<391> B_IWL<390> B_IWL<389> B_IWL<388> B_IWL<387> B_IWL<386> B_IWL<385> B_IWL<384> VDD_CORE VSS / RM_IHPSG13_64x32_c2_2P_COLUMN_pcell_0 +XCOL<23> A_BLC<47> A_BLC<46> A_BLC_TOP<47> A_BLC_TOP<46> A_BLT<47> A_BLT<46> A_BLT_TOP<47> A_BLT_TOP<46> A_IWL<367> A_IWL<366> A_IWL<365> A_IWL<364> A_IWL<363> A_IWL<362> A_IWL<361> A_IWL<360> A_IWL<359> A_IWL<358> A_IWL<357> A_IWL<356> A_IWL<355> A_IWL<354> A_IWL<353> A_IWL<352> A_IWL<383> A_IWL<382> A_IWL<381> A_IWL<380> A_IWL<379> A_IWL<378> A_IWL<377> A_IWL<376> A_IWL<375> A_IWL<374> A_IWL<373> A_IWL<372> A_IWL<371> A_IWL<370> A_IWL<369> A_IWL<368> B_BLC<47> B_BLC<46> B_BLC_TOP<47> B_BLC_TOP<46> B_BLT<47> B_BLT<46> B_BLT_TOP<47> B_BLT_TOP<46> B_IWL<367> B_IWL<366> B_IWL<365> B_IWL<364> B_IWL<363> B_IWL<362> B_IWL<361> B_IWL<360> B_IWL<359> B_IWL<358> B_IWL<357> B_IWL<356> B_IWL<355> B_IWL<354> B_IWL<353> B_IWL<352> B_IWL<383> B_IWL<382> B_IWL<381> B_IWL<380> B_IWL<379> B_IWL<378> B_IWL<377> B_IWL<376> B_IWL<375> B_IWL<374> B_IWL<373> B_IWL<372> B_IWL<371> B_IWL<370> B_IWL<369> B_IWL<368> VDD_CORE VSS / RM_IHPSG13_64x32_c2_2P_COLUMN_pcell_0 +XCOL<22> A_BLC<45> A_BLC<44> A_BLC_TOP<45> A_BLC_TOP<44> A_BLT<45> A_BLT<44> A_BLT_TOP<45> A_BLT_TOP<44> A_IWL<351> A_IWL<350> A_IWL<349> A_IWL<348> A_IWL<347> A_IWL<346> A_IWL<345> A_IWL<344> A_IWL<343> A_IWL<342> A_IWL<341> A_IWL<340> A_IWL<339> A_IWL<338> A_IWL<337> A_IWL<336> A_IWL<367> A_IWL<366> A_IWL<365> A_IWL<364> A_IWL<363> A_IWL<362> A_IWL<361> A_IWL<360> A_IWL<359> A_IWL<358> A_IWL<357> A_IWL<356> A_IWL<355> A_IWL<354> A_IWL<353> A_IWL<352> B_BLC<45> B_BLC<44> B_BLC_TOP<45> B_BLC_TOP<44> B_BLT<45> B_BLT<44> B_BLT_TOP<45> B_BLT_TOP<44> B_IWL<351> B_IWL<350> B_IWL<349> B_IWL<348> B_IWL<347> B_IWL<346> B_IWL<345> B_IWL<344> B_IWL<343> B_IWL<342> B_IWL<341> B_IWL<340> B_IWL<339> B_IWL<338> B_IWL<337> B_IWL<336> B_IWL<367> B_IWL<366> B_IWL<365> B_IWL<364> B_IWL<363> B_IWL<362> B_IWL<361> B_IWL<360> B_IWL<359> B_IWL<358> B_IWL<357> B_IWL<356> B_IWL<355> B_IWL<354> B_IWL<353> B_IWL<352> VDD_CORE VSS / RM_IHPSG13_64x32_c2_2P_COLUMN_pcell_0 +XCOL<21> A_BLC<43> A_BLC<42> A_BLC_TOP<43> A_BLC_TOP<42> A_BLT<43> A_BLT<42> A_BLT_TOP<43> A_BLT_TOP<42> A_IWL<335> A_IWL<334> A_IWL<333> A_IWL<332> A_IWL<331> A_IWL<330> A_IWL<329> A_IWL<328> A_IWL<327> A_IWL<326> A_IWL<325> A_IWL<324> A_IWL<323> A_IWL<322> A_IWL<321> A_IWL<320> A_IWL<351> A_IWL<350> A_IWL<349> A_IWL<348> A_IWL<347> A_IWL<346> A_IWL<345> A_IWL<344> A_IWL<343> A_IWL<342> A_IWL<341> A_IWL<340> A_IWL<339> A_IWL<338> A_IWL<337> A_IWL<336> B_BLC<43> B_BLC<42> B_BLC_TOP<43> B_BLC_TOP<42> B_BLT<43> B_BLT<42> B_BLT_TOP<43> B_BLT_TOP<42> B_IWL<335> B_IWL<334> B_IWL<333> B_IWL<332> B_IWL<331> B_IWL<330> B_IWL<329> B_IWL<328> B_IWL<327> B_IWL<326> B_IWL<325> B_IWL<324> B_IWL<323> B_IWL<322> B_IWL<321> B_IWL<320> B_IWL<351> B_IWL<350> B_IWL<349> B_IWL<348> B_IWL<347> B_IWL<346> B_IWL<345> B_IWL<344> B_IWL<343> B_IWL<342> B_IWL<341> B_IWL<340> B_IWL<339> B_IWL<338> B_IWL<337> B_IWL<336> VDD_CORE VSS / RM_IHPSG13_64x32_c2_2P_COLUMN_pcell_0 +XCOL<20> A_BLC<41> A_BLC<40> A_BLC_TOP<41> A_BLC_TOP<40> A_BLT<41> A_BLT<40> A_BLT_TOP<41> A_BLT_TOP<40> A_IWL<319> A_IWL<318> A_IWL<317> A_IWL<316> A_IWL<315> A_IWL<314> A_IWL<313> A_IWL<312> A_IWL<311> A_IWL<310> A_IWL<309> A_IWL<308> A_IWL<307> A_IWL<306> A_IWL<305> A_IWL<304> A_IWL<335> A_IWL<334> A_IWL<333> A_IWL<332> A_IWL<331> A_IWL<330> A_IWL<329> A_IWL<328> A_IWL<327> A_IWL<326> A_IWL<325> A_IWL<324> A_IWL<323> A_IWL<322> A_IWL<321> A_IWL<320> B_BLC<41> B_BLC<40> B_BLC_TOP<41> B_BLC_TOP<40> B_BLT<41> B_BLT<40> B_BLT_TOP<41> B_BLT_TOP<40> B_IWL<319> B_IWL<318> B_IWL<317> B_IWL<316> B_IWL<315> B_IWL<314> B_IWL<313> B_IWL<312> B_IWL<311> B_IWL<310> B_IWL<309> B_IWL<308> B_IWL<307> B_IWL<306> B_IWL<305> B_IWL<304> B_IWL<335> B_IWL<334> B_IWL<333> B_IWL<332> B_IWL<331> B_IWL<330> B_IWL<329> B_IWL<328> B_IWL<327> B_IWL<326> B_IWL<325> B_IWL<324> B_IWL<323> B_IWL<322> B_IWL<321> B_IWL<320> VDD_CORE VSS / RM_IHPSG13_64x32_c2_2P_COLUMN_pcell_0 +XCOL<19> A_BLC<39> A_BLC<38> A_BLC_TOP<39> A_BLC_TOP<38> A_BLT<39> A_BLT<38> A_BLT_TOP<39> A_BLT_TOP<38> A_IWL<303> A_IWL<302> A_IWL<301> A_IWL<300> A_IWL<299> A_IWL<298> A_IWL<297> A_IWL<296> A_IWL<295> A_IWL<294> A_IWL<293> A_IWL<292> A_IWL<291> A_IWL<290> A_IWL<289> A_IWL<288> A_IWL<319> A_IWL<318> A_IWL<317> A_IWL<316> A_IWL<315> A_IWL<314> A_IWL<313> A_IWL<312> A_IWL<311> A_IWL<310> A_IWL<309> A_IWL<308> A_IWL<307> A_IWL<306> A_IWL<305> A_IWL<304> B_BLC<39> B_BLC<38> B_BLC_TOP<39> B_BLC_TOP<38> B_BLT<39> B_BLT<38> B_BLT_TOP<39> B_BLT_TOP<38> B_IWL<303> B_IWL<302> B_IWL<301> B_IWL<300> B_IWL<299> B_IWL<298> B_IWL<297> B_IWL<296> B_IWL<295> B_IWL<294> B_IWL<293> B_IWL<292> B_IWL<291> B_IWL<290> B_IWL<289> B_IWL<288> B_IWL<319> B_IWL<318> B_IWL<317> B_IWL<316> B_IWL<315> B_IWL<314> B_IWL<313> B_IWL<312> B_IWL<311> B_IWL<310> B_IWL<309> B_IWL<308> B_IWL<307> B_IWL<306> B_IWL<305> B_IWL<304> VDD_CORE VSS / RM_IHPSG13_64x32_c2_2P_COLUMN_pcell_0 +XCOL<18> A_BLC<37> A_BLC<36> A_BLC_TOP<37> A_BLC_TOP<36> A_BLT<37> A_BLT<36> A_BLT_TOP<37> A_BLT_TOP<36> A_IWL<287> A_IWL<286> A_IWL<285> A_IWL<284> A_IWL<283> A_IWL<282> A_IWL<281> A_IWL<280> A_IWL<279> A_IWL<278> A_IWL<277> A_IWL<276> A_IWL<275> A_IWL<274> A_IWL<273> A_IWL<272> A_IWL<303> A_IWL<302> A_IWL<301> A_IWL<300> A_IWL<299> A_IWL<298> A_IWL<297> A_IWL<296> A_IWL<295> A_IWL<294> A_IWL<293> A_IWL<292> A_IWL<291> A_IWL<290> A_IWL<289> A_IWL<288> B_BLC<37> B_BLC<36> B_BLC_TOP<37> B_BLC_TOP<36> B_BLT<37> B_BLT<36> B_BLT_TOP<37> B_BLT_TOP<36> B_IWL<287> B_IWL<286> B_IWL<285> B_IWL<284> B_IWL<283> B_IWL<282> B_IWL<281> B_IWL<280> B_IWL<279> B_IWL<278> B_IWL<277> B_IWL<276> B_IWL<275> B_IWL<274> B_IWL<273> B_IWL<272> B_IWL<303> B_IWL<302> B_IWL<301> B_IWL<300> B_IWL<299> B_IWL<298> B_IWL<297> B_IWL<296> B_IWL<295> B_IWL<294> B_IWL<293> B_IWL<292> B_IWL<291> B_IWL<290> B_IWL<289> B_IWL<288> VDD_CORE VSS / RM_IHPSG13_64x32_c2_2P_COLUMN_pcell_0 +XCOL<17> A_BLC<35> A_BLC<34> A_BLC_TOP<35> A_BLC_TOP<34> A_BLT<35> A_BLT<34> A_BLT_TOP<35> A_BLT_TOP<34> A_IWL<271> A_IWL<270> A_IWL<269> A_IWL<268> A_IWL<267> A_IWL<266> A_IWL<265> A_IWL<264> A_IWL<263> A_IWL<262> A_IWL<261> A_IWL<260> A_IWL<259> A_IWL<258> A_IWL<257> A_IWL<256> A_IWL<287> A_IWL<286> A_IWL<285> A_IWL<284> A_IWL<283> A_IWL<282> A_IWL<281> A_IWL<280> A_IWL<279> A_IWL<278> A_IWL<277> A_IWL<276> A_IWL<275> A_IWL<274> A_IWL<273> A_IWL<272> B_BLC<35> B_BLC<34> B_BLC_TOP<35> B_BLC_TOP<34> B_BLT<35> B_BLT<34> B_BLT_TOP<35> B_BLT_TOP<34> B_IWL<271> B_IWL<270> B_IWL<269> B_IWL<268> B_IWL<267> B_IWL<266> B_IWL<265> B_IWL<264> B_IWL<263> B_IWL<262> B_IWL<261> B_IWL<260> B_IWL<259> B_IWL<258> B_IWL<257> B_IWL<256> B_IWL<287> B_IWL<286> B_IWL<285> B_IWL<284> B_IWL<283> B_IWL<282> B_IWL<281> B_IWL<280> B_IWL<279> B_IWL<278> B_IWL<277> B_IWL<276> B_IWL<275> B_IWL<274> B_IWL<273> B_IWL<272> VDD_CORE VSS / RM_IHPSG13_64x32_c2_2P_COLUMN_pcell_0 +XCOL<16> A_BLC<33> A_BLC<32> A_BLC_TOP<33> A_BLC_TOP<32> A_BLT<33> A_BLT<32> A_BLT_TOP<33> A_BLT_TOP<32> A_IWL<255> A_IWL<254> A_IWL<253> A_IWL<252> A_IWL<251> A_IWL<250> A_IWL<249> A_IWL<248> A_IWL<247> A_IWL<246> A_IWL<245> A_IWL<244> A_IWL<243> A_IWL<242> A_IWL<241> A_IWL<240> A_IWL<271> A_IWL<270> A_IWL<269> A_IWL<268> A_IWL<267> A_IWL<266> A_IWL<265> A_IWL<264> A_IWL<263> A_IWL<262> A_IWL<261> A_IWL<260> A_IWL<259> A_IWL<258> A_IWL<257> A_IWL<256> B_BLC<33> B_BLC<32> B_BLC_TOP<33> B_BLC_TOP<32> B_BLT<33> B_BLT<32> B_BLT_TOP<33> B_BLT_TOP<32> B_IWL<255> B_IWL<254> B_IWL<253> B_IWL<252> B_IWL<251> B_IWL<250> B_IWL<249> B_IWL<248> B_IWL<247> B_IWL<246> B_IWL<245> B_IWL<244> B_IWL<243> B_IWL<242> B_IWL<241> B_IWL<240> B_IWL<271> B_IWL<270> B_IWL<269> B_IWL<268> B_IWL<267> B_IWL<266> B_IWL<265> B_IWL<264> B_IWL<263> B_IWL<262> B_IWL<261> B_IWL<260> B_IWL<259> B_IWL<258> B_IWL<257> B_IWL<256> VDD_CORE VSS / RM_IHPSG13_64x32_c2_2P_COLUMN_pcell_0 +XCOL<15> A_BLC<31> A_BLC<30> A_BLC_TOP<31> A_BLC_TOP<30> A_BLT<31> A_BLT<30> A_BLT_TOP<31> A_BLT_TOP<30> A_IWL<239> A_IWL<238> A_IWL<237> A_IWL<236> A_IWL<235> A_IWL<234> A_IWL<233> A_IWL<232> A_IWL<231> A_IWL<230> A_IWL<229> A_IWL<228> A_IWL<227> A_IWL<226> A_IWL<225> A_IWL<224> A_IWL<255> A_IWL<254> A_IWL<253> A_IWL<252> A_IWL<251> A_IWL<250> A_IWL<249> A_IWL<248> A_IWL<247> A_IWL<246> A_IWL<245> A_IWL<244> A_IWL<243> A_IWL<242> A_IWL<241> A_IWL<240> B_BLC<31> B_BLC<30> B_BLC_TOP<31> B_BLC_TOP<30> B_BLT<31> B_BLT<30> B_BLT_TOP<31> B_BLT_TOP<30> B_IWL<239> B_IWL<238> B_IWL<237> B_IWL<236> B_IWL<235> B_IWL<234> B_IWL<233> B_IWL<232> B_IWL<231> B_IWL<230> B_IWL<229> B_IWL<228> B_IWL<227> B_IWL<226> B_IWL<225> B_IWL<224> B_IWL<255> B_IWL<254> B_IWL<253> B_IWL<252> B_IWL<251> B_IWL<250> B_IWL<249> B_IWL<248> B_IWL<247> B_IWL<246> B_IWL<245> B_IWL<244> B_IWL<243> B_IWL<242> B_IWL<241> B_IWL<240> VDD_CORE VSS / RM_IHPSG13_64x32_c2_2P_COLUMN_pcell_0 +XCOL<14> A_BLC<29> A_BLC<28> A_BLC_TOP<29> A_BLC_TOP<28> A_BLT<29> A_BLT<28> A_BLT_TOP<29> A_BLT_TOP<28> A_IWL<223> A_IWL<222> A_IWL<221> A_IWL<220> A_IWL<219> A_IWL<218> A_IWL<217> A_IWL<216> A_IWL<215> A_IWL<214> A_IWL<213> A_IWL<212> A_IWL<211> A_IWL<210> A_IWL<209> A_IWL<208> A_IWL<239> A_IWL<238> A_IWL<237> A_IWL<236> A_IWL<235> A_IWL<234> A_IWL<233> A_IWL<232> A_IWL<231> A_IWL<230> A_IWL<229> A_IWL<228> A_IWL<227> A_IWL<226> A_IWL<225> A_IWL<224> B_BLC<29> B_BLC<28> B_BLC_TOP<29> B_BLC_TOP<28> B_BLT<29> B_BLT<28> B_BLT_TOP<29> B_BLT_TOP<28> B_IWL<223> B_IWL<222> B_IWL<221> B_IWL<220> B_IWL<219> B_IWL<218> B_IWL<217> B_IWL<216> B_IWL<215> B_IWL<214> B_IWL<213> B_IWL<212> B_IWL<211> B_IWL<210> B_IWL<209> B_IWL<208> B_IWL<239> B_IWL<238> B_IWL<237> B_IWL<236> B_IWL<235> B_IWL<234> B_IWL<233> B_IWL<232> B_IWL<231> B_IWL<230> B_IWL<229> B_IWL<228> B_IWL<227> B_IWL<226> B_IWL<225> B_IWL<224> VDD_CORE VSS / RM_IHPSG13_64x32_c2_2P_COLUMN_pcell_0 +XCOL<13> A_BLC<27> A_BLC<26> A_BLC_TOP<27> A_BLC_TOP<26> A_BLT<27> A_BLT<26> A_BLT_TOP<27> A_BLT_TOP<26> A_IWL<207> A_IWL<206> A_IWL<205> A_IWL<204> A_IWL<203> A_IWL<202> A_IWL<201> A_IWL<200> A_IWL<199> A_IWL<198> A_IWL<197> A_IWL<196> A_IWL<195> A_IWL<194> A_IWL<193> A_IWL<192> A_IWL<223> A_IWL<222> A_IWL<221> A_IWL<220> A_IWL<219> A_IWL<218> A_IWL<217> A_IWL<216> A_IWL<215> A_IWL<214> A_IWL<213> A_IWL<212> A_IWL<211> A_IWL<210> A_IWL<209> A_IWL<208> B_BLC<27> B_BLC<26> B_BLC_TOP<27> B_BLC_TOP<26> B_BLT<27> B_BLT<26> B_BLT_TOP<27> B_BLT_TOP<26> B_IWL<207> B_IWL<206> B_IWL<205> B_IWL<204> B_IWL<203> B_IWL<202> B_IWL<201> B_IWL<200> B_IWL<199> B_IWL<198> B_IWL<197> B_IWL<196> B_IWL<195> B_IWL<194> B_IWL<193> B_IWL<192> B_IWL<223> B_IWL<222> B_IWL<221> B_IWL<220> B_IWL<219> B_IWL<218> B_IWL<217> B_IWL<216> B_IWL<215> B_IWL<214> B_IWL<213> B_IWL<212> B_IWL<211> B_IWL<210> B_IWL<209> B_IWL<208> VDD_CORE VSS / RM_IHPSG13_64x32_c2_2P_COLUMN_pcell_0 +XCOL<12> A_BLC<25> A_BLC<24> A_BLC_TOP<25> A_BLC_TOP<24> A_BLT<25> A_BLT<24> A_BLT_TOP<25> A_BLT_TOP<24> A_IWL<191> A_IWL<190> A_IWL<189> A_IWL<188> A_IWL<187> A_IWL<186> A_IWL<185> A_IWL<184> A_IWL<183> A_IWL<182> A_IWL<181> A_IWL<180> A_IWL<179> A_IWL<178> A_IWL<177> A_IWL<176> A_IWL<207> A_IWL<206> A_IWL<205> A_IWL<204> A_IWL<203> A_IWL<202> A_IWL<201> A_IWL<200> A_IWL<199> A_IWL<198> A_IWL<197> A_IWL<196> A_IWL<195> A_IWL<194> A_IWL<193> A_IWL<192> B_BLC<25> B_BLC<24> B_BLC_TOP<25> B_BLC_TOP<24> B_BLT<25> B_BLT<24> B_BLT_TOP<25> B_BLT_TOP<24> B_IWL<191> B_IWL<190> B_IWL<189> B_IWL<188> B_IWL<187> B_IWL<186> B_IWL<185> B_IWL<184> B_IWL<183> B_IWL<182> B_IWL<181> B_IWL<180> B_IWL<179> B_IWL<178> B_IWL<177> B_IWL<176> B_IWL<207> B_IWL<206> B_IWL<205> B_IWL<204> B_IWL<203> B_IWL<202> B_IWL<201> B_IWL<200> B_IWL<199> B_IWL<198> B_IWL<197> B_IWL<196> B_IWL<195> B_IWL<194> B_IWL<193> B_IWL<192> VDD_CORE VSS / RM_IHPSG13_64x32_c2_2P_COLUMN_pcell_0 +XCOL<11> A_BLC<23> A_BLC<22> A_BLC_TOP<23> A_BLC_TOP<22> A_BLT<23> A_BLT<22> A_BLT_TOP<23> A_BLT_TOP<22> A_IWL<175> A_IWL<174> A_IWL<173> A_IWL<172> A_IWL<171> A_IWL<170> A_IWL<169> A_IWL<168> A_IWL<167> A_IWL<166> A_IWL<165> A_IWL<164> A_IWL<163> A_IWL<162> A_IWL<161> A_IWL<160> A_IWL<191> A_IWL<190> A_IWL<189> A_IWL<188> A_IWL<187> A_IWL<186> A_IWL<185> A_IWL<184> A_IWL<183> A_IWL<182> A_IWL<181> A_IWL<180> A_IWL<179> A_IWL<178> A_IWL<177> A_IWL<176> B_BLC<23> B_BLC<22> B_BLC_TOP<23> B_BLC_TOP<22> B_BLT<23> B_BLT<22> B_BLT_TOP<23> B_BLT_TOP<22> B_IWL<175> B_IWL<174> B_IWL<173> B_IWL<172> B_IWL<171> B_IWL<170> B_IWL<169> B_IWL<168> B_IWL<167> B_IWL<166> B_IWL<165> B_IWL<164> B_IWL<163> B_IWL<162> B_IWL<161> B_IWL<160> B_IWL<191> B_IWL<190> B_IWL<189> B_IWL<188> B_IWL<187> B_IWL<186> B_IWL<185> B_IWL<184> B_IWL<183> B_IWL<182> B_IWL<181> B_IWL<180> B_IWL<179> B_IWL<178> B_IWL<177> B_IWL<176> VDD_CORE VSS / RM_IHPSG13_64x32_c2_2P_COLUMN_pcell_0 +XCOL<10> A_BLC<21> A_BLC<20> A_BLC_TOP<21> A_BLC_TOP<20> A_BLT<21> A_BLT<20> A_BLT_TOP<21> A_BLT_TOP<20> A_IWL<159> A_IWL<158> A_IWL<157> A_IWL<156> A_IWL<155> A_IWL<154> A_IWL<153> A_IWL<152> A_IWL<151> A_IWL<150> A_IWL<149> A_IWL<148> A_IWL<147> A_IWL<146> A_IWL<145> A_IWL<144> A_IWL<175> A_IWL<174> A_IWL<173> A_IWL<172> A_IWL<171> A_IWL<170> A_IWL<169> A_IWL<168> A_IWL<167> A_IWL<166> A_IWL<165> A_IWL<164> A_IWL<163> A_IWL<162> A_IWL<161> A_IWL<160> B_BLC<21> B_BLC<20> B_BLC_TOP<21> B_BLC_TOP<20> B_BLT<21> B_BLT<20> B_BLT_TOP<21> B_BLT_TOP<20> B_IWL<159> B_IWL<158> B_IWL<157> B_IWL<156> B_IWL<155> B_IWL<154> B_IWL<153> B_IWL<152> B_IWL<151> B_IWL<150> B_IWL<149> B_IWL<148> B_IWL<147> B_IWL<146> B_IWL<145> B_IWL<144> B_IWL<175> B_IWL<174> B_IWL<173> B_IWL<172> B_IWL<171> B_IWL<170> B_IWL<169> B_IWL<168> B_IWL<167> B_IWL<166> B_IWL<165> B_IWL<164> B_IWL<163> B_IWL<162> B_IWL<161> B_IWL<160> VDD_CORE VSS / RM_IHPSG13_64x32_c2_2P_COLUMN_pcell_0 +XCOL<9> A_BLC<19> A_BLC<18> A_BLC_TOP<19> A_BLC_TOP<18> A_BLT<19> A_BLT<18> A_BLT_TOP<19> A_BLT_TOP<18> A_IWL<143> A_IWL<142> A_IWL<141> A_IWL<140> A_IWL<139> A_IWL<138> A_IWL<137> A_IWL<136> A_IWL<135> A_IWL<134> A_IWL<133> A_IWL<132> A_IWL<131> A_IWL<130> A_IWL<129> A_IWL<128> A_IWL<159> A_IWL<158> A_IWL<157> A_IWL<156> A_IWL<155> A_IWL<154> A_IWL<153> A_IWL<152> A_IWL<151> A_IWL<150> A_IWL<149> A_IWL<148> A_IWL<147> A_IWL<146> A_IWL<145> A_IWL<144> B_BLC<19> B_BLC<18> B_BLC_TOP<19> B_BLC_TOP<18> B_BLT<19> B_BLT<18> B_BLT_TOP<19> B_BLT_TOP<18> B_IWL<143> B_IWL<142> B_IWL<141> B_IWL<140> B_IWL<139> B_IWL<138> B_IWL<137> B_IWL<136> B_IWL<135> B_IWL<134> B_IWL<133> B_IWL<132> B_IWL<131> B_IWL<130> B_IWL<129> B_IWL<128> B_IWL<159> B_IWL<158> B_IWL<157> B_IWL<156> B_IWL<155> B_IWL<154> B_IWL<153> B_IWL<152> B_IWL<151> B_IWL<150> B_IWL<149> B_IWL<148> B_IWL<147> B_IWL<146> B_IWL<145> B_IWL<144> VDD_CORE VSS / RM_IHPSG13_64x32_c2_2P_COLUMN_pcell_0 +XCOL<8> A_BLC<17> A_BLC<16> A_BLC_TOP<17> A_BLC_TOP<16> A_BLT<17> A_BLT<16> A_BLT_TOP<17> A_BLT_TOP<16> A_IWL<127> A_IWL<126> A_IWL<125> A_IWL<124> A_IWL<123> A_IWL<122> A_IWL<121> A_IWL<120> A_IWL<119> A_IWL<118> A_IWL<117> A_IWL<116> A_IWL<115> A_IWL<114> A_IWL<113> A_IWL<112> A_IWL<143> A_IWL<142> A_IWL<141> A_IWL<140> A_IWL<139> A_IWL<138> A_IWL<137> A_IWL<136> A_IWL<135> A_IWL<134> A_IWL<133> A_IWL<132> A_IWL<131> A_IWL<130> A_IWL<129> A_IWL<128> B_BLC<17> B_BLC<16> B_BLC_TOP<17> B_BLC_TOP<16> B_BLT<17> B_BLT<16> B_BLT_TOP<17> B_BLT_TOP<16> B_IWL<127> B_IWL<126> B_IWL<125> B_IWL<124> B_IWL<123> B_IWL<122> B_IWL<121> B_IWL<120> B_IWL<119> B_IWL<118> B_IWL<117> B_IWL<116> B_IWL<115> B_IWL<114> B_IWL<113> B_IWL<112> B_IWL<143> B_IWL<142> B_IWL<141> B_IWL<140> B_IWL<139> B_IWL<138> B_IWL<137> B_IWL<136> B_IWL<135> B_IWL<134> B_IWL<133> B_IWL<132> B_IWL<131> B_IWL<130> B_IWL<129> B_IWL<128> VDD_CORE VSS / RM_IHPSG13_64x32_c2_2P_COLUMN_pcell_0 +XCOL<7> A_BLC<15> A_BLC<14> A_BLC_TOP<15> A_BLC_TOP<14> A_BLT<15> A_BLT<14> A_BLT_TOP<15> A_BLT_TOP<14> A_IWL<111> A_IWL<110> A_IWL<109> A_IWL<108> A_IWL<107> A_IWL<106> A_IWL<105> A_IWL<104> A_IWL<103> A_IWL<102> A_IWL<101> A_IWL<100> A_IWL<99> A_IWL<98> A_IWL<97> A_IWL<96> A_IWL<127> A_IWL<126> A_IWL<125> A_IWL<124> A_IWL<123> A_IWL<122> A_IWL<121> A_IWL<120> A_IWL<119> A_IWL<118> A_IWL<117> A_IWL<116> A_IWL<115> A_IWL<114> A_IWL<113> A_IWL<112> B_BLC<15> B_BLC<14> B_BLC_TOP<15> B_BLC_TOP<14> B_BLT<15> B_BLT<14> B_BLT_TOP<15> B_BLT_TOP<14> B_IWL<111> B_IWL<110> B_IWL<109> B_IWL<108> B_IWL<107> B_IWL<106> B_IWL<105> B_IWL<104> B_IWL<103> B_IWL<102> B_IWL<101> B_IWL<100> B_IWL<99> B_IWL<98> B_IWL<97> B_IWL<96> B_IWL<127> B_IWL<126> B_IWL<125> B_IWL<124> B_IWL<123> B_IWL<122> B_IWL<121> B_IWL<120> B_IWL<119> B_IWL<118> B_IWL<117> B_IWL<116> B_IWL<115> B_IWL<114> B_IWL<113> B_IWL<112> VDD_CORE VSS / RM_IHPSG13_64x32_c2_2P_COLUMN_pcell_0 +XCOL<6> A_BLC<13> A_BLC<12> A_BLC_TOP<13> A_BLC_TOP<12> A_BLT<13> A_BLT<12> A_BLT_TOP<13> A_BLT_TOP<12> A_IWL<95> A_IWL<94> A_IWL<93> A_IWL<92> A_IWL<91> A_IWL<90> A_IWL<89> A_IWL<88> A_IWL<87> A_IWL<86> A_IWL<85> A_IWL<84> A_IWL<83> A_IWL<82> A_IWL<81> A_IWL<80> A_IWL<111> A_IWL<110> A_IWL<109> A_IWL<108> A_IWL<107> A_IWL<106> A_IWL<105> A_IWL<104> A_IWL<103> A_IWL<102> A_IWL<101> A_IWL<100> A_IWL<99> A_IWL<98> A_IWL<97> A_IWL<96> B_BLC<13> B_BLC<12> B_BLC_TOP<13> B_BLC_TOP<12> B_BLT<13> B_BLT<12> B_BLT_TOP<13> B_BLT_TOP<12> B_IWL<95> B_IWL<94> B_IWL<93> B_IWL<92> B_IWL<91> B_IWL<90> B_IWL<89> B_IWL<88> B_IWL<87> B_IWL<86> B_IWL<85> B_IWL<84> B_IWL<83> B_IWL<82> B_IWL<81> B_IWL<80> B_IWL<111> B_IWL<110> B_IWL<109> B_IWL<108> B_IWL<107> B_IWL<106> B_IWL<105> B_IWL<104> B_IWL<103> B_IWL<102> B_IWL<101> B_IWL<100> B_IWL<99> B_IWL<98> B_IWL<97> B_IWL<96> VDD_CORE VSS / RM_IHPSG13_64x32_c2_2P_COLUMN_pcell_0 +XCOL<5> A_BLC<11> A_BLC<10> A_BLC_TOP<11> A_BLC_TOP<10> A_BLT<11> A_BLT<10> A_BLT_TOP<11> A_BLT_TOP<10> A_IWL<79> A_IWL<78> A_IWL<77> A_IWL<76> A_IWL<75> A_IWL<74> A_IWL<73> A_IWL<72> A_IWL<71> A_IWL<70> A_IWL<69> A_IWL<68> A_IWL<67> A_IWL<66> A_IWL<65> A_IWL<64> A_IWL<95> A_IWL<94> A_IWL<93> A_IWL<92> A_IWL<91> A_IWL<90> A_IWL<89> A_IWL<88> A_IWL<87> A_IWL<86> A_IWL<85> A_IWL<84> A_IWL<83> A_IWL<82> A_IWL<81> A_IWL<80> B_BLC<11> B_BLC<10> B_BLC_TOP<11> B_BLC_TOP<10> B_BLT<11> B_BLT<10> B_BLT_TOP<11> B_BLT_TOP<10> B_IWL<79> B_IWL<78> B_IWL<77> B_IWL<76> B_IWL<75> B_IWL<74> B_IWL<73> B_IWL<72> B_IWL<71> B_IWL<70> B_IWL<69> B_IWL<68> B_IWL<67> B_IWL<66> B_IWL<65> B_IWL<64> B_IWL<95> B_IWL<94> B_IWL<93> B_IWL<92> B_IWL<91> B_IWL<90> B_IWL<89> B_IWL<88> B_IWL<87> B_IWL<86> B_IWL<85> B_IWL<84> B_IWL<83> B_IWL<82> B_IWL<81> B_IWL<80> VDD_CORE VSS / RM_IHPSG13_64x32_c2_2P_COLUMN_pcell_0 +XCOL<4> A_BLC<9> A_BLC<8> A_BLC_TOP<9> A_BLC_TOP<8> A_BLT<9> A_BLT<8> A_BLT_TOP<9> A_BLT_TOP<8> A_IWL<63> A_IWL<62> A_IWL<61> A_IWL<60> A_IWL<59> A_IWL<58> A_IWL<57> A_IWL<56> A_IWL<55> A_IWL<54> A_IWL<53> A_IWL<52> A_IWL<51> A_IWL<50> A_IWL<49> A_IWL<48> A_IWL<79> A_IWL<78> A_IWL<77> A_IWL<76> A_IWL<75> A_IWL<74> A_IWL<73> A_IWL<72> A_IWL<71> A_IWL<70> A_IWL<69> A_IWL<68> A_IWL<67> A_IWL<66> A_IWL<65> A_IWL<64> B_BLC<9> B_BLC<8> B_BLC_TOP<9> B_BLC_TOP<8> B_BLT<9> B_BLT<8> B_BLT_TOP<9> B_BLT_TOP<8> B_IWL<63> B_IWL<62> B_IWL<61> B_IWL<60> B_IWL<59> B_IWL<58> B_IWL<57> B_IWL<56> B_IWL<55> B_IWL<54> B_IWL<53> B_IWL<52> B_IWL<51> B_IWL<50> B_IWL<49> B_IWL<48> B_IWL<79> B_IWL<78> B_IWL<77> B_IWL<76> B_IWL<75> B_IWL<74> B_IWL<73> B_IWL<72> B_IWL<71> B_IWL<70> B_IWL<69> B_IWL<68> B_IWL<67> B_IWL<66> B_IWL<65> B_IWL<64> VDD_CORE VSS / RM_IHPSG13_64x32_c2_2P_COLUMN_pcell_0 +XCOL<3> A_BLC<7> A_BLC<6> A_BLC_TOP<7> A_BLC_TOP<6> A_BLT<7> A_BLT<6> A_BLT_TOP<7> A_BLT_TOP<6> A_IWL<47> A_IWL<46> A_IWL<45> A_IWL<44> A_IWL<43> A_IWL<42> A_IWL<41> A_IWL<40> A_IWL<39> A_IWL<38> A_IWL<37> A_IWL<36> A_IWL<35> A_IWL<34> A_IWL<33> A_IWL<32> A_IWL<63> A_IWL<62> A_IWL<61> A_IWL<60> A_IWL<59> A_IWL<58> A_IWL<57> A_IWL<56> A_IWL<55> A_IWL<54> A_IWL<53> A_IWL<52> A_IWL<51> A_IWL<50> A_IWL<49> A_IWL<48> B_BLC<7> B_BLC<6> B_BLC_TOP<7> B_BLC_TOP<6> B_BLT<7> B_BLT<6> B_BLT_TOP<7> B_BLT_TOP<6> B_IWL<47> B_IWL<46> B_IWL<45> B_IWL<44> B_IWL<43> B_IWL<42> B_IWL<41> B_IWL<40> B_IWL<39> B_IWL<38> B_IWL<37> B_IWL<36> B_IWL<35> B_IWL<34> B_IWL<33> B_IWL<32> B_IWL<63> B_IWL<62> B_IWL<61> B_IWL<60> B_IWL<59> B_IWL<58> B_IWL<57> B_IWL<56> B_IWL<55> B_IWL<54> B_IWL<53> B_IWL<52> B_IWL<51> B_IWL<50> B_IWL<49> B_IWL<48> VDD_CORE VSS / RM_IHPSG13_64x32_c2_2P_COLUMN_pcell_0 +XCOL<2> A_BLC<5> A_BLC<4> A_BLC_TOP<5> A_BLC_TOP<4> A_BLT<5> A_BLT<4> A_BLT_TOP<5> A_BLT_TOP<4> A_IWL<31> A_IWL<30> A_IWL<29> A_IWL<28> A_IWL<27> A_IWL<26> A_IWL<25> A_IWL<24> A_IWL<23> A_IWL<22> A_IWL<21> A_IWL<20> A_IWL<19> A_IWL<18> A_IWL<17> A_IWL<16> A_IWL<47> A_IWL<46> A_IWL<45> A_IWL<44> A_IWL<43> A_IWL<42> A_IWL<41> A_IWL<40> A_IWL<39> A_IWL<38> A_IWL<37> A_IWL<36> A_IWL<35> A_IWL<34> A_IWL<33> A_IWL<32> B_BLC<5> B_BLC<4> B_BLC_TOP<5> B_BLC_TOP<4> B_BLT<5> B_BLT<4> B_BLT_TOP<5> B_BLT_TOP<4> B_IWL<31> B_IWL<30> B_IWL<29> B_IWL<28> B_IWL<27> B_IWL<26> B_IWL<25> B_IWL<24> B_IWL<23> B_IWL<22> B_IWL<21> B_IWL<20> B_IWL<19> B_IWL<18> B_IWL<17> B_IWL<16> B_IWL<47> B_IWL<46> B_IWL<45> B_IWL<44> B_IWL<43> B_IWL<42> B_IWL<41> B_IWL<40> B_IWL<39> B_IWL<38> B_IWL<37> B_IWL<36> B_IWL<35> B_IWL<34> B_IWL<33> B_IWL<32> VDD_CORE VSS / RM_IHPSG13_64x32_c2_2P_COLUMN_pcell_0 +XCOL<1> A_BLC<3> A_BLC<2> A_BLC_TOP<3> A_BLC_TOP<2> A_BLT<3> A_BLT<2> A_BLT_TOP<3> A_BLT_TOP<2> A_IWL<15> A_IWL<14> A_IWL<13> A_IWL<12> A_IWL<11> A_IWL<10> A_IWL<9> A_IWL<8> A_IWL<7> A_IWL<6> A_IWL<5> A_IWL<4> A_IWL<3> A_IWL<2> A_IWL<1> A_IWL<0> A_IWL<31> A_IWL<30> A_IWL<29> A_IWL<28> A_IWL<27> A_IWL<26> A_IWL<25> A_IWL<24> A_IWL<23> A_IWL<22> A_IWL<21> A_IWL<20> A_IWL<19> A_IWL<18> A_IWL<17> A_IWL<16> B_BLC<3> B_BLC<2> B_BLC_TOP<3> B_BLC_TOP<2> B_BLT<3> B_BLT<2> B_BLT_TOP<3> B_BLT_TOP<2> B_IWL<15> B_IWL<14> B_IWL<13> B_IWL<12> B_IWL<11> B_IWL<10> B_IWL<9> B_IWL<8> B_IWL<7> B_IWL<6> B_IWL<5> B_IWL<4> B_IWL<3> B_IWL<2> B_IWL<1> B_IWL<0> B_IWL<31> B_IWL<30> B_IWL<29> B_IWL<28> B_IWL<27> B_IWL<26> B_IWL<25> B_IWL<24> B_IWL<23> B_IWL<22> B_IWL<21> B_IWL<20> B_IWL<19> B_IWL<18> B_IWL<17> B_IWL<16> VDD_CORE VSS / RM_IHPSG13_64x32_c2_2P_COLUMN_pcell_0 +XCOL<0> A_BLC<1> A_BLC<0> A_BLC_TOP<1> A_BLC_TOP<0> A_BLT<1> A_BLT<0> A_BLT_TOP<1> A_BLT_TOP<0> A_WL<15> A_WL<14> A_WL<13> A_WL<12> A_WL<11> A_WL<10> A_WL<9> A_WL<8> A_WL<7> A_WL<6> A_WL<5> A_WL<4> A_WL<3> A_WL<2> A_WL<1> A_WL<0> A_IWL<15> A_IWL<14> A_IWL<13> A_IWL<12> A_IWL<11> A_IWL<10> A_IWL<9> A_IWL<8> A_IWL<7> A_IWL<6> A_IWL<5> A_IWL<4> A_IWL<3> A_IWL<2> A_IWL<1> A_IWL<0> B_BLC<1> B_BLC<0> B_BLC_TOP<1> B_BLC_TOP<0> B_BLT<1> B_BLT<0> B_BLT_TOP<1> B_BLT_TOP<0> B_WL<15> B_WL<14> B_WL<13> B_WL<12> B_WL<11> B_WL<10> B_WL<9> B_WL<8> B_WL<7> B_WL<6> B_WL<5> B_WL<4> B_WL<3> B_WL<2> B_WL<1> B_WL<0> B_IWL<15> B_IWL<14> B_IWL<13> B_IWL<12> B_IWL<11> B_IWL<10> B_IWL<9> B_IWL<8> B_IWL<7> B_IWL<6> B_IWL<5> B_IWL<4> B_IWL<3> B_IWL<2> B_IWL<1> B_IWL<0> VDD_CORE VSS / RM_IHPSG13_64x32_c2_2P_COLUMN_pcell_0 +.ENDS + + + + +.SUBCKT RM_IHPSG13_64x32_c2_2P_DLY_pcell_2 A Z VDD VSS + XIDL D<9> Z VDD VSS / RSC_IHPSG13_CDLYX1 + XIDM<9> D<8> D<9> VDD VSS / RSC_IHPSG13_CDLYX1_DUMMY + XIDM<8> D<7> D<8> VDD VSS / RSC_IHPSG13_CDLYX1_DUMMY + XIDM<7> D<6> D<7> VDD VSS / RSC_IHPSG13_CDLYX1_DUMMY + XIDM<6> D<5> D<6> VDD VSS / RSC_IHPSG13_CDLYX1_DUMMY + XIDM<5> D<4> D<5> VDD VSS / RSC_IHPSG13_CDLYX1_DUMMY + XIDM<4> D<3> D<4> VDD VSS / RSC_IHPSG13_CDLYX1_DUMMY + XIDM<3> D<2> D<3> VDD VSS / RSC_IHPSG13_CDLYX1_DUMMY + XIDM<2> D<1> D<2> VDD VSS / RSC_IHPSG13_CDLYX1_DUMMY + XIDM<1> A D<1> VDD VSS / RSC_IHPSG13_CDLYX1_DUMMY +.ENDS + + +.SUBCKT RM_IHPSG13_64x32_c2_2P_DLY_pcell_3 A Z VDD VSS + XIDM<10> D<9> Z VDD VSS / RSC_IHPSG13_CDLYX1_DUMMY + XIDM<9> D<8> D<9> VDD VSS / RSC_IHPSG13_CDLYX1_DUMMY + XIDM<8> D<7> D<8> VDD VSS / RSC_IHPSG13_CDLYX1_DUMMY + XIDM<7> D<6> D<7> VDD VSS / RSC_IHPSG13_CDLYX1_DUMMY + XIDM<6> D<5> D<6> VDD VSS / RSC_IHPSG13_CDLYX1_DUMMY + XIDM<5> D<4> D<5> VDD VSS / RSC_IHPSG13_CDLYX1_DUMMY + XIDM<4> D<3> D<4> VDD VSS / RSC_IHPSG13_CDLYX1_DUMMY + XIDM<3> D<2> D<3> VDD VSS / RSC_IHPSG13_CDLYX1_DUMMY + XIDM<2> D<1> D<2> VDD VSS / RSC_IHPSG13_CDLYX1_DUMMY + XIDM<1> A D<1> VDD VSS / RSC_IHPSG13_CDLYX1_DUMMY +.ENDS + + + +.SUBCKT RM_IHPSG13_2P_64x32_c2 A_ADDR<5> A_ADDR<4> A_ADDR<3> A_ADDR<2> A_ADDR<1> A_ADDR<0> A_CLK A_DIN<31> A_DIN<30> A_DIN<29> A_DIN<28> A_DIN<27> A_DIN<26> A_DIN<25> A_DIN<24> A_DIN<23> A_DIN<22> A_DIN<21> A_DIN<20> A_DIN<19> A_DIN<18> A_DIN<17> A_DIN<16> A_DIN<15> A_DIN<14> A_DIN<13> A_DIN<12> A_DIN<11> A_DIN<10> A_DIN<9> A_DIN<8> A_DIN<7> A_DIN<6> A_DIN<5> A_DIN<4> A_DIN<3> A_DIN<2> A_DIN<1> A_DIN<0> A_DLY A_DOUT<31> A_DOUT<30> A_DOUT<29> A_DOUT<28> A_DOUT<27> A_DOUT<26> A_DOUT<25> A_DOUT<24> A_DOUT<23> A_DOUT<22> A_DOUT<21> A_DOUT<20> A_DOUT<19> A_DOUT<18> A_DOUT<17> A_DOUT<16> A_DOUT<15> A_DOUT<14> A_DOUT<13> A_DOUT<12> A_DOUT<11> A_DOUT<10> A_DOUT<9> A_DOUT<8> A_DOUT<7> A_DOUT<6> A_DOUT<5> A_DOUT<4> A_DOUT<3> A_DOUT<2> A_DOUT<1> A_DOUT<0> A_MEN A_REN A_WEN B_ADDR<5> B_ADDR<4> B_ADDR<3> B_ADDR<2> B_ADDR<1> B_ADDR<0> B_CLK B_DIN<31> B_DIN<30> B_DIN<29> B_DIN<28> B_DIN<27> B_DIN<26> B_DIN<25> B_DIN<24> B_DIN<23> B_DIN<22> B_DIN<21> B_DIN<20> B_DIN<19> B_DIN<18> B_DIN<17> B_DIN<16> B_DIN<15> B_DIN<14> B_DIN<13> B_DIN<12> B_DIN<11> B_DIN<10> B_DIN<9> B_DIN<8> B_DIN<7> B_DIN<6> B_DIN<5> B_DIN<4> B_DIN<3> B_DIN<2> B_DIN<1> B_DIN<0> B_DLY B_DOUT<31> B_DOUT<30> B_DOUT<29> B_DOUT<28> B_DOUT<27> B_DOUT<26> B_DOUT<25> B_DOUT<24> B_DOUT<23> B_DOUT<22> B_DOUT<21> B_DOUT<20> B_DOUT<19> B_DOUT<18> B_DOUT<17> B_DOUT<16> B_DOUT<15> B_DOUT<14> B_DOUT<13> B_DOUT<12> B_DOUT<11> B_DOUT<10> B_DOUT<9> B_DOUT<8> B_DOUT<7> B_DOUT<6> B_DOUT<5> B_DOUT<4> B_DOUT<3> B_DOUT<2> B_DOUT<1> B_DOUT<0> B_MEN B_REN B_WEN VDD! VDDARRAY! VSS! + + +XRAM<1> a_blc_r<63> a_blc_r<62> a_blc_r<61> a_blc_r<60> a_blc_r<59> a_blc_r<58> a_blc_r<57> a_blc_r<56> a_blc_r<55> a_blc_r<54> a_blc_r<53> a_blc_r<52> a_blc_r<51> a_blc_r<50> a_blc_r<49> a_blc_r<48> a_blc_r<47> a_blc_r<46> a_blc_r<45> a_blc_r<44> a_blc_r<43> a_blc_r<42> a_blc_r<41> a_blc_r<40> a_blc_r<39> a_blc_r<38> a_blc_r<37> a_blc_r<36> a_blc_r<35> a_blc_r<34> a_blc_r<33> a_blc_r<32> a_blc_r<31> a_blc_r<30> a_blc_r<29> a_blc_r<28> a_blc_r<27> a_blc_r<26> a_blc_r<25> a_blc_r<24> a_blc_r<23> a_blc_r<22> a_blc_r<21> a_blc_r<20> a_blc_r<19> a_blc_r<18> a_blc_r<17> a_blc_r<16> a_blc_r<15> a_blc_r<14> a_blc_r<13> a_blc_r<12> a_blc_r<11> a_blc_r<10> a_blc_r<9> a_blc_r<8> a_blc_r<7> a_blc_r<6> a_blc_r<5> a_blc_r<4> a_blc_r<3> a_blc_r<2> a_blc_r<1> a_blc_r<0> a_blt_r<63> a_blt_r<62> a_blt_r<61> a_blt_r<60> a_blt_r<59> a_blt_r<58> a_blt_r<57> a_blt_r<56> a_blt_r<55> a_blt_r<54> a_blt_r<53> a_blt_r<52> a_blt_r<51> a_blt_r<50> a_blt_r<49> a_blt_r<48> a_blt_r<47> a_blt_r<46> a_blt_r<45> a_blt_r<44> a_blt_r<43> a_blt_r<42> a_blt_r<41> a_blt_r<40> a_blt_r<39> a_blt_r<38> a_blt_r<37> a_blt_r<36> a_blt_r<35> a_blt_r<34> a_blt_r<33> a_blt_r<32> a_blt_r<31> a_blt_r<30> a_blt_r<29> a_blt_r<28> a_blt_r<27> a_blt_r<26> a_blt_r<25> a_blt_r<24> a_blt_r<23> a_blt_r<22> a_blt_r<21> a_blt_r<20> a_blt_r<19> a_blt_r<18> a_blt_r<17> a_blt_r<16> a_blt_r<15> a_blt_r<14> a_blt_r<13> a_blt_r<12> a_blt_r<11> a_blt_r<10> a_blt_r<9> a_blt_r<8> a_blt_r<7> a_blt_r<6> a_blt_r<5> a_blt_r<4> a_blt_r<3> a_blt_r<2> a_blt_r<1> a_blt_r<0> a_wl_r<15> a_wl_r<14> a_wl_r<13> a_wl_r<12> a_wl_r<11> a_wl_r<10> a_wl_r<9> a_wl_r<8> a_wl_r<7> a_wl_r<6> a_wl_r<5> a_wl_r<4> a_wl_r<3> a_wl_r<2> a_wl_r<1> a_wl_r<0> b_blc_r<63> b_blc_r<62> b_blc_r<61> b_blc_r<60> b_blc_r<59> b_blc_r<58> b_blc_r<57> b_blc_r<56> b_blc_r<55> b_blc_r<54> b_blc_r<53> b_blc_r<52> b_blc_r<51> b_blc_r<50> b_blc_r<49> b_blc_r<48> b_blc_r<47> b_blc_r<46> b_blc_r<45> b_blc_r<44> b_blc_r<43> b_blc_r<42> b_blc_r<41> b_blc_r<40> b_blc_r<39> b_blc_r<38> b_blc_r<37> b_blc_r<36> b_blc_r<35> b_blc_r<34> b_blc_r<33> b_blc_r<32> b_blc_r<31> b_blc_r<30> b_blc_r<29> b_blc_r<28> b_blc_r<27> b_blc_r<26> b_blc_r<25> b_blc_r<24> b_blc_r<23> b_blc_r<22> b_blc_r<21> b_blc_r<20> b_blc_r<19> b_blc_r<18> b_blc_r<17> b_blc_r<16> b_blc_r<15> b_blc_r<14> b_blc_r<13> b_blc_r<12> b_blc_r<11> b_blc_r<10> b_blc_r<9> b_blc_r<8> b_blc_r<7> b_blc_r<6> b_blc_r<5> b_blc_r<4> b_blc_r<3> b_blc_r<2> b_blc_r<1> b_blc_r<0> b_blt_r<63> b_blt_r<62> b_blt_r<61> b_blt_r<60> b_blt_r<59> b_blt_r<58> b_blt_r<57> b_blt_r<56> b_blt_r<55> b_blt_r<54> b_blt_r<53> b_blt_r<52> b_blt_r<51> b_blt_r<50> b_blt_r<49> b_blt_r<48> b_blt_r<47> b_blt_r<46> b_blt_r<45> b_blt_r<44> b_blt_r<43> b_blt_r<42> b_blt_r<41> b_blt_r<40> b_blt_r<39> b_blt_r<38> b_blt_r<37> b_blt_r<36> b_blt_r<35> b_blt_r<34> b_blt_r<33> b_blt_r<32> b_blt_r<31> b_blt_r<30> b_blt_r<29> b_blt_r<28> b_blt_r<27> b_blt_r<26> b_blt_r<25> b_blt_r<24> b_blt_r<23> b_blt_r<22> b_blt_r<21> b_blt_r<20> b_blt_r<19> b_blt_r<18> b_blt_r<17> b_blt_r<16> b_blt_r<15> b_blt_r<14> b_blt_r<13> b_blt_r<12> b_blt_r<11> b_blt_r<10> b_blt_r<9> b_blt_r<8> b_blt_r<7> b_blt_r<6> b_blt_r<5> b_blt_r<4> b_blt_r<3> b_blt_r<2> b_blt_r<1> b_blt_r<0> b_wl_r<15> b_wl_r<14> b_wl_r<13> b_wl_r<12> b_wl_r<11> b_wl_r<10> b_wl_r<9> b_wl_r<8> b_wl_r<7> b_wl_r<6> b_wl_r<5> b_wl_r<4> b_wl_r<3> b_wl_r<2> b_wl_r<1> b_wl_r<0> VDDARRAY! VSS! / RM_IHPSG13_64x32_c2_2P_MATRIX_pcell_1 +XRAM<0> a_blc_l<63> a_blc_l<62> a_blc_l<61> a_blc_l<60> a_blc_l<59> a_blc_l<58> a_blc_l<57> a_blc_l<56> a_blc_l<55> a_blc_l<54> a_blc_l<53> a_blc_l<52> a_blc_l<51> a_blc_l<50> a_blc_l<49> a_blc_l<48> a_blc_l<47> a_blc_l<46> a_blc_l<45> a_blc_l<44> a_blc_l<43> a_blc_l<42> a_blc_l<41> a_blc_l<40> a_blc_l<39> a_blc_l<38> a_blc_l<37> a_blc_l<36> a_blc_l<35> a_blc_l<34> a_blc_l<33> a_blc_l<32> a_blc_l<31> a_blc_l<30> a_blc_l<29> a_blc_l<28> a_blc_l<27> a_blc_l<26> a_blc_l<25> a_blc_l<24> a_blc_l<23> a_blc_l<22> a_blc_l<21> a_blc_l<20> a_blc_l<19> a_blc_l<18> a_blc_l<17> a_blc_l<16> a_blc_l<15> a_blc_l<14> a_blc_l<13> a_blc_l<12> a_blc_l<11> a_blc_l<10> a_blc_l<9> a_blc_l<8> a_blc_l<7> a_blc_l<6> a_blc_l<5> a_blc_l<4> a_blc_l<3> a_blc_l<2> a_blc_l<1> a_blc_l<0> a_blt_l<63> a_blt_l<62> a_blt_l<61> a_blt_l<60> a_blt_l<59> a_blt_l<58> a_blt_l<57> a_blt_l<56> a_blt_l<55> a_blt_l<54> a_blt_l<53> a_blt_l<52> a_blt_l<51> a_blt_l<50> a_blt_l<49> a_blt_l<48> a_blt_l<47> a_blt_l<46> a_blt_l<45> a_blt_l<44> a_blt_l<43> a_blt_l<42> a_blt_l<41> a_blt_l<40> a_blt_l<39> a_blt_l<38> a_blt_l<37> a_blt_l<36> a_blt_l<35> a_blt_l<34> a_blt_l<33> a_blt_l<32> a_blt_l<31> a_blt_l<30> a_blt_l<29> a_blt_l<28> a_blt_l<27> a_blt_l<26> a_blt_l<25> a_blt_l<24> a_blt_l<23> a_blt_l<22> a_blt_l<21> a_blt_l<20> a_blt_l<19> a_blt_l<18> a_blt_l<17> a_blt_l<16> a_blt_l<15> a_blt_l<14> a_blt_l<13> a_blt_l<12> a_blt_l<11> a_blt_l<10> a_blt_l<9> a_blt_l<8> a_blt_l<7> a_blt_l<6> a_blt_l<5> a_blt_l<4> a_blt_l<3> a_blt_l<2> a_blt_l<1> a_blt_l<0> a_wl_l<15> a_wl_l<14> a_wl_l<13> a_wl_l<12> a_wl_l<11> a_wl_l<10> a_wl_l<9> a_wl_l<8> a_wl_l<7> a_wl_l<6> a_wl_l<5> a_wl_l<4> a_wl_l<3> a_wl_l<2> a_wl_l<1> a_wl_l<0> b_blc_l<63> b_blc_l<62> b_blc_l<61> b_blc_l<60> b_blc_l<59> b_blc_l<58> b_blc_l<57> b_blc_l<56> b_blc_l<55> b_blc_l<54> b_blc_l<53> b_blc_l<52> b_blc_l<51> b_blc_l<50> b_blc_l<49> b_blc_l<48> b_blc_l<47> b_blc_l<46> b_blc_l<45> b_blc_l<44> b_blc_l<43> b_blc_l<42> b_blc_l<41> b_blc_l<40> b_blc_l<39> b_blc_l<38> b_blc_l<37> b_blc_l<36> b_blc_l<35> b_blc_l<34> b_blc_l<33> b_blc_l<32> b_blc_l<31> b_blc_l<30> b_blc_l<29> b_blc_l<28> b_blc_l<27> b_blc_l<26> b_blc_l<25> b_blc_l<24> b_blc_l<23> b_blc_l<22> b_blc_l<21> b_blc_l<20> b_blc_l<19> b_blc_l<18> b_blc_l<17> b_blc_l<16> b_blc_l<15> b_blc_l<14> b_blc_l<13> b_blc_l<12> b_blc_l<11> b_blc_l<10> b_blc_l<9> b_blc_l<8> b_blc_l<7> b_blc_l<6> b_blc_l<5> b_blc_l<4> b_blc_l<3> b_blc_l<2> b_blc_l<1> b_blc_l<0> b_blt_l<63> b_blt_l<62> b_blt_l<61> b_blt_l<60> b_blt_l<59> b_blt_l<58> b_blt_l<57> b_blt_l<56> b_blt_l<55> b_blt_l<54> b_blt_l<53> b_blt_l<52> b_blt_l<51> b_blt_l<50> b_blt_l<49> b_blt_l<48> b_blt_l<47> b_blt_l<46> b_blt_l<45> b_blt_l<44> b_blt_l<43> b_blt_l<42> b_blt_l<41> b_blt_l<40> b_blt_l<39> b_blt_l<38> b_blt_l<37> b_blt_l<36> b_blt_l<35> b_blt_l<34> b_blt_l<33> b_blt_l<32> b_blt_l<31> b_blt_l<30> b_blt_l<29> b_blt_l<28> b_blt_l<27> b_blt_l<26> b_blt_l<25> b_blt_l<24> b_blt_l<23> b_blt_l<22> b_blt_l<21> b_blt_l<20> b_blt_l<19> b_blt_l<18> b_blt_l<17> b_blt_l<16> b_blt_l<15> b_blt_l<14> b_blt_l<13> b_blt_l<12> b_blt_l<11> b_blt_l<10> b_blt_l<9> b_blt_l<8> b_blt_l<7> b_blt_l<6> b_blt_l<5> b_blt_l<4> b_blt_l<3> b_blt_l<2> b_blt_l<1> b_blt_l<0> b_wl_l<15> b_wl_l<14> b_wl_l<13> b_wl_l<12> b_wl_l<11> b_wl_l<10> b_wl_l<9> b_wl_l<8> b_wl_l<7> b_wl_l<6> b_wl_l<5> b_wl_l<4> b_wl_l<3> b_wl_l<2> b_wl_l<1> b_wl_l<0> VDDARRAY! VSS! / RM_IHPSG13_64x32_c2_2P_MATRIX_pcell_1 + + +XB_COLDRV<1> b_addr_col<1> b_addr_col<0> b_addr_col_r<1> b_addr_col_r<0> b_addr_dec<7> b_addr_dec<6> b_addr_dec<5> b_addr_dec<4> b_addr_dec<3> b_addr_dec<2> b_addr_dec<1> b_addr_dec<0> b_addr_dec_r<7> b_addr_dec_r<6> b_addr_dec_r<5> b_addr_dec_r<4> b_addr_dec_r<3> b_addr_dec_r<2> b_addr_dec_r<1> b_addr_dec_r<0> b_dclk b_dclk_p_r<0> b_rclk b_rclk_p_r<0> b_wclk b_wclk_p_r<0> VDD! VSS! / RM_IHPSG13_64x32_c2_2P_COLDRV13X8 +XB_COLDRV<0> b_addr_col<1> b_addr_col<0> b_addr_col_l<1> b_addr_col_l<0> b_addr_dec<7> b_addr_dec<6> b_addr_dec<5> b_addr_dec<4> b_addr_dec<3> b_addr_dec<2> b_addr_dec<1> b_addr_dec<0> b_addr_dec_l<7> b_addr_dec_l<6> b_addr_dec_l<5> b_addr_dec_l<4> b_addr_dec_l<3> b_addr_dec_l<2> b_addr_dec_l<1> b_addr_dec_l<0> b_dclk b_dclk_p_l<0> b_rclk b_rclk_p_l<0> b_wclk b_wclk_p_l<0> VDD! VSS! / RM_IHPSG13_64x32_c2_2P_COLDRV13X8 +XA_COLDRV<1> a_addr_col<1> a_addr_col<0> a_addr_col_r<1> a_addr_col_r<0> a_addr_dec<7> a_addr_dec<6> a_addr_dec<5> a_addr_dec<4> a_addr_dec<3> a_addr_dec<2> a_addr_dec<1> a_addr_dec<0> a_addr_dec_r<7> a_addr_dec_r<6> a_addr_dec_r<5> a_addr_dec_r<4> a_addr_dec_r<3> a_addr_dec_r<2> a_addr_dec_r<1> a_addr_dec_r<0> a_dclk a_dclk_p_r<0> a_rclk a_rclk_p_r<0> a_wclk a_wclk_p_r<0> VDD! VSS! / RM_IHPSG13_64x32_c2_2P_COLDRV13X8 +XA_COLDRV<0> a_addr_col<1> a_addr_col<0> a_addr_col_l<1> a_addr_col_l<0> a_addr_dec<7> a_addr_dec<6> a_addr_dec<5> a_addr_dec<4> a_addr_dec<3> a_addr_dec<2> a_addr_dec<1> a_addr_dec<0> a_addr_dec_l<7> a_addr_dec_l<6> a_addr_dec_l<5> a_addr_dec_l<4> a_addr_dec_l<3> a_addr_dec_l<2> a_addr_dec_l<1> a_addr_dec_l<0> a_dclk a_dclk_p_l<0> a_rclk a_rclk_p_l<0> a_wclk a_wclk_p_l<0> VDD! VSS! / RM_IHPSG13_64x32_c2_2P_COLDRV13X8 + + +XB_WLDRV<1> b_wi<15> b_wi<14> b_wi<13> b_wi<12> b_wi<11> b_wi<10> b_wi<9> b_wi<8> b_wi<7> b_wi<6> b_wi<5> b_wi<4> b_wi<3> b_wi<2> b_wi<1> b_wi<0> b_wl_r<15> b_wl_r<14> b_wl_r<13> b_wl_r<12> b_wl_r<11> b_wl_r<10> b_wl_r<9> b_wl_r<8> b_wl_r<7> b_wl_r<6> b_wl_r<5> b_wl_r<4> b_wl_r<3> b_wl_r<2> b_wl_r<1> b_wl_r<0> VDD! VSS! / RM_IHPSG13_64x32_c2_2P_WLDRV16X8 +XB_WLDRV<0> b_wi<15> b_wi<14> b_wi<13> b_wi<12> b_wi<11> b_wi<10> b_wi<9> b_wi<8> b_wi<7> b_wi<6> b_wi<5> b_wi<4> b_wi<3> b_wi<2> b_wi<1> b_wi<0> b_wl_l<15> b_wl_l<14> b_wl_l<13> b_wl_l<12> b_wl_l<11> b_wl_l<10> b_wl_l<9> b_wl_l<8> b_wl_l<7> b_wl_l<6> b_wl_l<5> b_wl_l<4> b_wl_l<3> b_wl_l<2> b_wl_l<1> b_wl_l<0> VDD! VSS! / RM_IHPSG13_64x32_c2_2P_WLDRV16X8 +XA_WLDRV<1> a_wi<15> a_wi<14> a_wi<13> a_wi<12> a_wi<11> a_wi<10> a_wi<9> a_wi<8> a_wi<7> a_wi<6> a_wi<5> a_wi<4> a_wi<3> a_wi<2> a_wi<1> a_wi<0> a_wl_r<15> a_wl_r<14> a_wl_r<13> a_wl_r<12> a_wl_r<11> a_wl_r<10> a_wl_r<9> a_wl_r<8> a_wl_r<7> a_wl_r<6> a_wl_r<5> a_wl_r<4> a_wl_r<3> a_wl_r<2> a_wl_r<1> a_wl_r<0> VDD! VSS! / RM_IHPSG13_64x32_c2_2P_WLDRV16X8 +XA_WLDRV<0> a_wi<15> a_wi<14> a_wi<13> a_wi<12> a_wi<11> a_wi<10> a_wi<9> a_wi<8> a_wi<7> a_wi<6> a_wi<5> a_wi<4> a_wi<3> a_wi<2> a_wi<1> a_wi<0> a_wl_l<15> a_wl_l<14> a_wl_l<13> a_wl_l<12> a_wl_l<11> a_wl_l<10> a_wl_l<9> a_wl_l<8> a_wl_l<7> a_wl_l<6> a_wl_l<5> a_wl_l<4> a_wl_l<3> a_wl_l<2> a_wl_l<1> a_wl_l<0> VDD! VSS! / RM_IHPSG13_64x32_c2_2P_WLDRV16X8 + + +XB_CTRL b_aclk_n b_tiel b_tiel b_tiel b_tiel b_tiel b_tiel B_CLK B_MEN b_dclk b_eclk b_pulse_h b_pulse_l b_pulse b_rclk B_REN b_cs b_wclk B_WEN VDD! VSS! / RM_IHPSG13_64x32_c2_2P_CTRL +XA_CTRL a_aclk_n a_tiel a_tiel a_tiel a_tiel a_tiel a_tiel A_CLK A_MEN a_dclk a_eclk a_pulse_h a_pulse_l a_pulse a_rclk A_REN a_cs a_wclk A_WEN VDD! VSS! / RM_IHPSG13_64x32_c2_2P_CTRL + + +XB_ROWDEC b_addr_row<3> b_addr_row<2> b_addr_row<1> b_addr_row<0> b_cs b_eclk b_wi<15> b_wi<14> b_wi<13> b_wi<12> b_wi<11> b_wi<10> b_wi<9> b_wi<8> b_wi<7> b_wi<6> b_wi<5> b_wi<4> b_wi<3> b_wi<2> b_wi<1> b_wi<0> VDD! VSS! / RM_IHPSG13_64x32_c2_2P_ROWDEC4 +XA_ROWDEC a_addr_row<3> a_addr_row<2> a_addr_row<1> a_addr_row<0> a_cs a_eclk a_wi<15> a_wi<14> a_wi<13> a_wi<12> a_wi<11> a_wi<10> a_wi<9> a_wi<8> a_wi<7> a_wi<6> a_wi<5> a_wi<4> a_wi<3> a_wi<2> a_wi<1> a_wi<0> VDD! VSS! / RM_IHPSG13_64x32_c2_2P_ROWDEC4 +XB_ROWREG b_aclk_n B_ADDR<5> B_ADDR<4> B_ADDR<3> B_ADDR<2> b_addr_row<3> b_addr_row<2> b_addr_row<1> b_addr_row<0> b_tiel b_tiel b_tiel b_tiel b_tiel VDD! VSS! / RM_IHPSG13_64x32_c2_2P_ROWREG4 +XA_ROWREG a_aclk_n A_ADDR<5> A_ADDR<4> A_ADDR<3> A_ADDR<2> a_addr_row<3> a_addr_row<2> a_addr_row<1> a_addr_row<0> a_tiel a_tiel a_tiel a_tiel a_tiel VDD! VSS! / RM_IHPSG13_64x32_c2_2P_ROWREG4 +XB_COLDEC b_aclk_n B_ADDR<1> B_ADDR<0> b_addr_col<1> b_addr_col<0> b_addr_dec<7> b_addr_dec<6> b_addr_dec<5> b_addr_dec<4> b_addr_dec<3> b_addr_dec<2> b_addr_dec<1> b_addr_dec<0> b_tiel b_tiel b_tiel VDD! VSS! / RM_IHPSG13_64x32_c2_2P_COLDEC2 +XA_COLDEC a_aclk_n A_ADDR<1> A_ADDR<0> a_addr_col<1> a_addr_col<0> a_addr_dec<7> a_addr_dec<6> a_addr_dec<5> a_addr_dec<4> a_addr_dec<3> a_addr_dec<2> a_addr_dec<1> a_addr_dec<0> a_tiel a_tiel a_tiel VDD! VSS! / RM_IHPSG13_64x32_c2_2P_COLDEC2 + + +XB_DLYH b_pulse b_pulse_h VDD! VSS! / RM_IHPSG13_64x32_c2_2P_DLY_pcell_2 +XB_DLYL b_pulse_x b_pulse_l VDD! VSS! / RM_IHPSG13_64x32_c2_2P_DLY_pcell_3 +XA_DLYH a_pulse a_pulse_h VDD! VSS! / RM_IHPSG13_64x32_c2_2P_DLY_pcell_2 +XA_DLYL a_pulse_x a_pulse_l VDD! VSS! / RM_IHPSG13_64x32_c2_2P_DLY_pcell_3 +XB_DLYMUX b_pulse_h B_DLY b_pulse_x VDD! VSS! / RM_IHPSG13_64x32_c2_2P_DLY_MUX +XA_DLYMUX a_pulse_h A_DLY a_pulse_x VDD! VSS! / RM_IHPSG13_64x32_c2_2P_DLY_MUX + +XCOLCTRL<31> a_addr_dec_r<3> a_addr_dec_r<2> a_addr_dec_r<1> a_addr_dec_r<0> a_tiel a_tiel a_tiel a_blc_r<63> a_blc_r<62> a_blc_r<61> a_blc_r<60> a_blt_r<63> a_blt_r<62> a_blt_r<61> a_blt_r<60> a_tieh<31> a_dclk_n_r<15> a_dclk_n_r<16> a_dclk_p_r<15> a_dclk_p_r<16> A_DOUT<31> A_DIN<31> a_rclk_n_r<15> a_rclk_n_r<16> a_rclk_p_r<15> a_rclk_p_r<16> a_tieh<31> a_wclk_n_r<15> a_wclk_n_r<16> a_wclk_p_r<15> a_wclk_p_r<16> b_addr_dec_r<3> b_addr_dec_r<2> b_addr_dec_r<1> b_addr_dec_r<0> b_tiel b_tiel b_tiel b_blc_r<63> b_blc_r<62> b_blc_r<61> b_blc_r<60> b_blt_r<63> b_blt_r<62> b_blt_r<61> b_blt_r<60> b_tieh<31> b_dclk_n_r<15> b_dclk_n_r<16> b_dclk_p_r<15> b_dclk_p_r<16> B_DOUT<31> B_DIN<31> b_rclk_n_r<15> b_rclk_n_r<16> b_rclk_p_r<15> b_rclk_p_r<16> b_tieh<31> b_wclk_n_r<15> b_wclk_n_r<16> b_wclk_p_r<15> b_wclk_p_r<16> VDD! VSS! / RM_IHPSG13_64x32_c2_2P_COLCTRL2 +XCOLCTRL<30> a_addr_dec_r<3> a_addr_dec_r<2> a_addr_dec_r<1> a_addr_dec_r<0> a_tiel a_tiel a_tiel a_blc_r<59> a_blc_r<58> a_blc_r<57> a_blc_r<56> a_blt_r<59> a_blt_r<58> a_blt_r<57> a_blt_r<56> a_tieh<30> a_dclk_n_r<14> a_dclk_n_r<15> a_dclk_p_r<14> a_dclk_p_r<15> A_DOUT<30> A_DIN<30> a_rclk_n_r<14> a_rclk_n_r<15> a_rclk_p_r<14> a_rclk_p_r<15> a_tieh<30> a_wclk_n_r<14> a_wclk_n_r<15> a_wclk_p_r<14> a_wclk_p_r<15> b_addr_dec_r<3> b_addr_dec_r<2> b_addr_dec_r<1> b_addr_dec_r<0> b_tiel b_tiel b_tiel b_blc_r<59> b_blc_r<58> b_blc_r<57> b_blc_r<56> b_blt_r<59> b_blt_r<58> b_blt_r<57> b_blt_r<56> b_tieh<30> b_dclk_n_r<14> b_dclk_n_r<15> b_dclk_p_r<14> b_dclk_p_r<15> B_DOUT<30> B_DIN<30> b_rclk_n_r<14> b_rclk_n_r<15> b_rclk_p_r<14> b_rclk_p_r<15> b_tieh<30> b_wclk_n_r<14> b_wclk_n_r<15> b_wclk_p_r<14> b_wclk_p_r<15> VDD! VSS! / RM_IHPSG13_64x32_c2_2P_COLCTRL2 +XCOLCTRL<29> a_addr_dec_r<3> a_addr_dec_r<2> a_addr_dec_r<1> a_addr_dec_r<0> a_tiel a_tiel a_tiel a_blc_r<55> a_blc_r<54> a_blc_r<53> a_blc_r<52> a_blt_r<55> a_blt_r<54> a_blt_r<53> a_blt_r<52> a_tieh<29> a_dclk_n_r<13> a_dclk_n_r<14> a_dclk_p_r<13> a_dclk_p_r<14> A_DOUT<29> A_DIN<29> a_rclk_n_r<13> a_rclk_n_r<14> a_rclk_p_r<13> a_rclk_p_r<14> a_tieh<29> a_wclk_n_r<13> a_wclk_n_r<14> a_wclk_p_r<13> a_wclk_p_r<14> b_addr_dec_r<3> b_addr_dec_r<2> b_addr_dec_r<1> b_addr_dec_r<0> b_tiel b_tiel b_tiel b_blc_r<55> b_blc_r<54> b_blc_r<53> b_blc_r<52> b_blt_r<55> b_blt_r<54> b_blt_r<53> b_blt_r<52> b_tieh<29> b_dclk_n_r<13> b_dclk_n_r<14> b_dclk_p_r<13> b_dclk_p_r<14> B_DOUT<29> B_DIN<29> b_rclk_n_r<13> b_rclk_n_r<14> b_rclk_p_r<13> b_rclk_p_r<14> b_tieh<29> b_wclk_n_r<13> b_wclk_n_r<14> b_wclk_p_r<13> b_wclk_p_r<14> VDD! VSS! / RM_IHPSG13_64x32_c2_2P_COLCTRL2 +XCOLCTRL<28> a_addr_dec_r<3> a_addr_dec_r<2> a_addr_dec_r<1> a_addr_dec_r<0> a_tiel a_tiel a_tiel a_blc_r<51> a_blc_r<50> a_blc_r<49> a_blc_r<48> a_blt_r<51> a_blt_r<50> a_blt_r<49> a_blt_r<48> a_tieh<28> a_dclk_n_r<12> a_dclk_n_r<13> a_dclk_p_r<12> a_dclk_p_r<13> A_DOUT<28> A_DIN<28> a_rclk_n_r<12> a_rclk_n_r<13> a_rclk_p_r<12> a_rclk_p_r<13> a_tieh<28> a_wclk_n_r<12> a_wclk_n_r<13> a_wclk_p_r<12> a_wclk_p_r<13> b_addr_dec_r<3> b_addr_dec_r<2> b_addr_dec_r<1> b_addr_dec_r<0> b_tiel b_tiel b_tiel b_blc_r<51> b_blc_r<50> b_blc_r<49> b_blc_r<48> b_blt_r<51> b_blt_r<50> b_blt_r<49> b_blt_r<48> b_tieh<28> b_dclk_n_r<12> b_dclk_n_r<13> b_dclk_p_r<12> b_dclk_p_r<13> B_DOUT<28> B_DIN<28> b_rclk_n_r<12> b_rclk_n_r<13> b_rclk_p_r<12> b_rclk_p_r<13> b_tieh<28> b_wclk_n_r<12> b_wclk_n_r<13> b_wclk_p_r<12> b_wclk_p_r<13> VDD! VSS! / RM_IHPSG13_64x32_c2_2P_COLCTRL2 +XCOLCTRL<27> a_addr_dec_r<3> a_addr_dec_r<2> a_addr_dec_r<1> a_addr_dec_r<0> a_tiel a_tiel a_tiel a_blc_r<47> a_blc_r<46> a_blc_r<45> a_blc_r<44> a_blt_r<47> a_blt_r<46> a_blt_r<45> a_blt_r<44> a_tieh<27> a_dclk_n_r<11> a_dclk_n_r<12> a_dclk_p_r<11> a_dclk_p_r<12> A_DOUT<27> A_DIN<27> a_rclk_n_r<11> a_rclk_n_r<12> a_rclk_p_r<11> a_rclk_p_r<12> a_tieh<27> a_wclk_n_r<11> a_wclk_n_r<12> a_wclk_p_r<11> a_wclk_p_r<12> b_addr_dec_r<3> b_addr_dec_r<2> b_addr_dec_r<1> b_addr_dec_r<0> b_tiel b_tiel b_tiel b_blc_r<47> b_blc_r<46> b_blc_r<45> b_blc_r<44> b_blt_r<47> b_blt_r<46> b_blt_r<45> b_blt_r<44> b_tieh<27> b_dclk_n_r<11> b_dclk_n_r<12> b_dclk_p_r<11> b_dclk_p_r<12> B_DOUT<27> B_DIN<27> b_rclk_n_r<11> b_rclk_n_r<12> b_rclk_p_r<11> b_rclk_p_r<12> b_tieh<27> b_wclk_n_r<11> b_wclk_n_r<12> b_wclk_p_r<11> b_wclk_p_r<12> VDD! VSS! / RM_IHPSG13_64x32_c2_2P_COLCTRL2 +XCOLCTRL<26> a_addr_dec_r<3> a_addr_dec_r<2> a_addr_dec_r<1> a_addr_dec_r<0> a_tiel a_tiel a_tiel a_blc_r<43> a_blc_r<42> a_blc_r<41> a_blc_r<40> a_blt_r<43> a_blt_r<42> a_blt_r<41> a_blt_r<40> a_tieh<26> a_dclk_n_r<10> a_dclk_n_r<11> a_dclk_p_r<10> a_dclk_p_r<11> A_DOUT<26> A_DIN<26> a_rclk_n_r<10> a_rclk_n_r<11> a_rclk_p_r<10> a_rclk_p_r<11> a_tieh<26> a_wclk_n_r<10> a_wclk_n_r<11> a_wclk_p_r<10> a_wclk_p_r<11> b_addr_dec_r<3> b_addr_dec_r<2> b_addr_dec_r<1> b_addr_dec_r<0> b_tiel b_tiel b_tiel b_blc_r<43> b_blc_r<42> b_blc_r<41> b_blc_r<40> b_blt_r<43> b_blt_r<42> b_blt_r<41> b_blt_r<40> b_tieh<26> b_dclk_n_r<10> b_dclk_n_r<11> b_dclk_p_r<10> b_dclk_p_r<11> B_DOUT<26> B_DIN<26> b_rclk_n_r<10> b_rclk_n_r<11> b_rclk_p_r<10> b_rclk_p_r<11> b_tieh<26> b_wclk_n_r<10> b_wclk_n_r<11> b_wclk_p_r<10> b_wclk_p_r<11> VDD! VSS! / RM_IHPSG13_64x32_c2_2P_COLCTRL2 +XCOLCTRL<25> a_addr_dec_r<3> a_addr_dec_r<2> a_addr_dec_r<1> a_addr_dec_r<0> a_tiel a_tiel a_tiel a_blc_r<39> a_blc_r<38> a_blc_r<37> a_blc_r<36> a_blt_r<39> a_blt_r<38> a_blt_r<37> a_blt_r<36> a_tieh<25> a_dclk_n_r<9> a_dclk_n_r<10> a_dclk_p_r<9> a_dclk_p_r<10> A_DOUT<25> A_DIN<25> a_rclk_n_r<9> a_rclk_n_r<10> a_rclk_p_r<9> a_rclk_p_r<10> a_tieh<25> a_wclk_n_r<9> a_wclk_n_r<10> a_wclk_p_r<9> a_wclk_p_r<10> b_addr_dec_r<3> b_addr_dec_r<2> b_addr_dec_r<1> b_addr_dec_r<0> b_tiel b_tiel b_tiel b_blc_r<39> b_blc_r<38> b_blc_r<37> b_blc_r<36> b_blt_r<39> b_blt_r<38> b_blt_r<37> b_blt_r<36> b_tieh<25> b_dclk_n_r<9> b_dclk_n_r<10> b_dclk_p_r<9> b_dclk_p_r<10> B_DOUT<25> B_DIN<25> b_rclk_n_r<9> b_rclk_n_r<10> b_rclk_p_r<9> b_rclk_p_r<10> b_tieh<25> b_wclk_n_r<9> b_wclk_n_r<10> b_wclk_p_r<9> b_wclk_p_r<10> VDD! VSS! / RM_IHPSG13_64x32_c2_2P_COLCTRL2 +XCOLCTRL<24> a_addr_dec_r<3> a_addr_dec_r<2> a_addr_dec_r<1> a_addr_dec_r<0> a_tiel a_tiel a_tiel a_blc_r<35> a_blc_r<34> a_blc_r<33> a_blc_r<32> a_blt_r<35> a_blt_r<34> a_blt_r<33> a_blt_r<32> a_tieh<24> a_dclk_n_r<8> a_dclk_n_r<9> a_dclk_p_r<8> a_dclk_p_r<9> A_DOUT<24> A_DIN<24> a_rclk_n_r<8> a_rclk_n_r<9> a_rclk_p_r<8> a_rclk_p_r<9> a_tieh<24> a_wclk_n_r<8> a_wclk_n_r<9> a_wclk_p_r<8> a_wclk_p_r<9> b_addr_dec_r<3> b_addr_dec_r<2> b_addr_dec_r<1> b_addr_dec_r<0> b_tiel b_tiel b_tiel b_blc_r<35> b_blc_r<34> b_blc_r<33> b_blc_r<32> b_blt_r<35> b_blt_r<34> b_blt_r<33> b_blt_r<32> b_tieh<24> b_dclk_n_r<8> b_dclk_n_r<9> b_dclk_p_r<8> b_dclk_p_r<9> B_DOUT<24> B_DIN<24> b_rclk_n_r<8> b_rclk_n_r<9> b_rclk_p_r<8> b_rclk_p_r<9> b_tieh<24> b_wclk_n_r<8> b_wclk_n_r<9> b_wclk_p_r<8> b_wclk_p_r<9> VDD! VSS! / RM_IHPSG13_64x32_c2_2P_COLCTRL2 +XCOLCTRL<23> a_addr_dec_r<3> a_addr_dec_r<2> a_addr_dec_r<1> a_addr_dec_r<0> a_tiel a_tiel a_tiel a_blc_r<31> a_blc_r<30> a_blc_r<29> a_blc_r<28> a_blt_r<31> a_blt_r<30> a_blt_r<29> a_blt_r<28> a_tieh<23> a_dclk_n_r<7> a_dclk_n_r<8> a_dclk_p_r<7> a_dclk_p_r<8> A_DOUT<23> A_DIN<23> a_rclk_n_r<7> a_rclk_n_r<8> a_rclk_p_r<7> a_rclk_p_r<8> a_tieh<23> a_wclk_n_r<7> a_wclk_n_r<8> a_wclk_p_r<7> a_wclk_p_r<8> b_addr_dec_r<3> b_addr_dec_r<2> b_addr_dec_r<1> b_addr_dec_r<0> b_tiel b_tiel b_tiel b_blc_r<31> b_blc_r<30> b_blc_r<29> b_blc_r<28> b_blt_r<31> b_blt_r<30> b_blt_r<29> b_blt_r<28> b_tieh<23> b_dclk_n_r<7> b_dclk_n_r<8> b_dclk_p_r<7> b_dclk_p_r<8> B_DOUT<23> B_DIN<23> b_rclk_n_r<7> b_rclk_n_r<8> b_rclk_p_r<7> b_rclk_p_r<8> b_tieh<23> b_wclk_n_r<7> b_wclk_n_r<8> b_wclk_p_r<7> b_wclk_p_r<8> VDD! VSS! / RM_IHPSG13_64x32_c2_2P_COLCTRL2 +XCOLCTRL<22> a_addr_dec_r<3> a_addr_dec_r<2> a_addr_dec_r<1> a_addr_dec_r<0> a_tiel a_tiel a_tiel a_blc_r<27> a_blc_r<26> a_blc_r<25> a_blc_r<24> a_blt_r<27> a_blt_r<26> a_blt_r<25> a_blt_r<24> a_tieh<22> a_dclk_n_r<6> a_dclk_n_r<7> a_dclk_p_r<6> a_dclk_p_r<7> A_DOUT<22> A_DIN<22> a_rclk_n_r<6> a_rclk_n_r<7> a_rclk_p_r<6> a_rclk_p_r<7> a_tieh<22> a_wclk_n_r<6> a_wclk_n_r<7> a_wclk_p_r<6> a_wclk_p_r<7> b_addr_dec_r<3> b_addr_dec_r<2> b_addr_dec_r<1> b_addr_dec_r<0> b_tiel b_tiel b_tiel b_blc_r<27> b_blc_r<26> b_blc_r<25> b_blc_r<24> b_blt_r<27> b_blt_r<26> b_blt_r<25> b_blt_r<24> b_tieh<22> b_dclk_n_r<6> b_dclk_n_r<7> b_dclk_p_r<6> b_dclk_p_r<7> B_DOUT<22> B_DIN<22> b_rclk_n_r<6> b_rclk_n_r<7> b_rclk_p_r<6> b_rclk_p_r<7> b_tieh<22> b_wclk_n_r<6> b_wclk_n_r<7> b_wclk_p_r<6> b_wclk_p_r<7> VDD! VSS! / RM_IHPSG13_64x32_c2_2P_COLCTRL2 +XCOLCTRL<21> a_addr_dec_r<3> a_addr_dec_r<2> a_addr_dec_r<1> a_addr_dec_r<0> a_tiel a_tiel a_tiel a_blc_r<23> a_blc_r<22> a_blc_r<21> a_blc_r<20> a_blt_r<23> a_blt_r<22> a_blt_r<21> a_blt_r<20> a_tieh<21> a_dclk_n_r<5> a_dclk_n_r<6> a_dclk_p_r<5> a_dclk_p_r<6> A_DOUT<21> A_DIN<21> a_rclk_n_r<5> a_rclk_n_r<6> a_rclk_p_r<5> a_rclk_p_r<6> a_tieh<21> a_wclk_n_r<5> a_wclk_n_r<6> a_wclk_p_r<5> a_wclk_p_r<6> b_addr_dec_r<3> b_addr_dec_r<2> b_addr_dec_r<1> b_addr_dec_r<0> b_tiel b_tiel b_tiel b_blc_r<23> b_blc_r<22> b_blc_r<21> b_blc_r<20> b_blt_r<23> b_blt_r<22> b_blt_r<21> b_blt_r<20> b_tieh<21> b_dclk_n_r<5> b_dclk_n_r<6> b_dclk_p_r<5> b_dclk_p_r<6> B_DOUT<21> B_DIN<21> b_rclk_n_r<5> b_rclk_n_r<6> b_rclk_p_r<5> b_rclk_p_r<6> b_tieh<21> b_wclk_n_r<5> b_wclk_n_r<6> b_wclk_p_r<5> b_wclk_p_r<6> VDD! VSS! / RM_IHPSG13_64x32_c2_2P_COLCTRL2 +XCOLCTRL<20> a_addr_dec_r<3> a_addr_dec_r<2> a_addr_dec_r<1> a_addr_dec_r<0> a_tiel a_tiel a_tiel a_blc_r<19> a_blc_r<18> a_blc_r<17> a_blc_r<16> a_blt_r<19> a_blt_r<18> a_blt_r<17> a_blt_r<16> a_tieh<20> a_dclk_n_r<4> a_dclk_n_r<5> a_dclk_p_r<4> a_dclk_p_r<5> A_DOUT<20> A_DIN<20> a_rclk_n_r<4> a_rclk_n_r<5> a_rclk_p_r<4> a_rclk_p_r<5> a_tieh<20> a_wclk_n_r<4> a_wclk_n_r<5> a_wclk_p_r<4> a_wclk_p_r<5> b_addr_dec_r<3> b_addr_dec_r<2> b_addr_dec_r<1> b_addr_dec_r<0> b_tiel b_tiel b_tiel b_blc_r<19> b_blc_r<18> b_blc_r<17> b_blc_r<16> b_blt_r<19> b_blt_r<18> b_blt_r<17> b_blt_r<16> b_tieh<20> b_dclk_n_r<4> b_dclk_n_r<5> b_dclk_p_r<4> b_dclk_p_r<5> B_DOUT<20> B_DIN<20> b_rclk_n_r<4> b_rclk_n_r<5> b_rclk_p_r<4> b_rclk_p_r<5> b_tieh<20> b_wclk_n_r<4> b_wclk_n_r<5> b_wclk_p_r<4> b_wclk_p_r<5> VDD! VSS! / RM_IHPSG13_64x32_c2_2P_COLCTRL2 +XCOLCTRL<19> a_addr_dec_r<3> a_addr_dec_r<2> a_addr_dec_r<1> a_addr_dec_r<0> a_tiel a_tiel a_tiel a_blc_r<15> a_blc_r<14> a_blc_r<13> a_blc_r<12> a_blt_r<15> a_blt_r<14> a_blt_r<13> a_blt_r<12> a_tieh<19> a_dclk_n_r<3> a_dclk_n_r<4> a_dclk_p_r<3> a_dclk_p_r<4> A_DOUT<19> A_DIN<19> a_rclk_n_r<3> a_rclk_n_r<4> a_rclk_p_r<3> a_rclk_p_r<4> a_tieh<19> a_wclk_n_r<3> a_wclk_n_r<4> a_wclk_p_r<3> a_wclk_p_r<4> b_addr_dec_r<3> b_addr_dec_r<2> b_addr_dec_r<1> b_addr_dec_r<0> b_tiel b_tiel b_tiel b_blc_r<15> b_blc_r<14> b_blc_r<13> b_blc_r<12> b_blt_r<15> b_blt_r<14> b_blt_r<13> b_blt_r<12> b_tieh<19> b_dclk_n_r<3> b_dclk_n_r<4> b_dclk_p_r<3> b_dclk_p_r<4> B_DOUT<19> B_DIN<19> b_rclk_n_r<3> b_rclk_n_r<4> b_rclk_p_r<3> b_rclk_p_r<4> b_tieh<19> b_wclk_n_r<3> b_wclk_n_r<4> b_wclk_p_r<3> b_wclk_p_r<4> VDD! VSS! / RM_IHPSG13_64x32_c2_2P_COLCTRL2 +XCOLCTRL<18> a_addr_dec_r<3> a_addr_dec_r<2> a_addr_dec_r<1> a_addr_dec_r<0> a_tiel a_tiel a_tiel a_blc_r<11> a_blc_r<10> a_blc_r<9> a_blc_r<8> a_blt_r<11> a_blt_r<10> a_blt_r<9> a_blt_r<8> a_tieh<18> a_dclk_n_r<2> a_dclk_n_r<3> a_dclk_p_r<2> a_dclk_p_r<3> A_DOUT<18> A_DIN<18> a_rclk_n_r<2> a_rclk_n_r<3> a_rclk_p_r<2> a_rclk_p_r<3> a_tieh<18> a_wclk_n_r<2> a_wclk_n_r<3> a_wclk_p_r<2> a_wclk_p_r<3> b_addr_dec_r<3> b_addr_dec_r<2> b_addr_dec_r<1> b_addr_dec_r<0> b_tiel b_tiel b_tiel b_blc_r<11> b_blc_r<10> b_blc_r<9> b_blc_r<8> b_blt_r<11> b_blt_r<10> b_blt_r<9> b_blt_r<8> b_tieh<18> b_dclk_n_r<2> b_dclk_n_r<3> b_dclk_p_r<2> b_dclk_p_r<3> B_DOUT<18> B_DIN<18> b_rclk_n_r<2> b_rclk_n_r<3> b_rclk_p_r<2> b_rclk_p_r<3> b_tieh<18> b_wclk_n_r<2> b_wclk_n_r<3> b_wclk_p_r<2> b_wclk_p_r<3> VDD! VSS! / RM_IHPSG13_64x32_c2_2P_COLCTRL2 +XCOLCTRL<17> a_addr_dec_r<3> a_addr_dec_r<2> a_addr_dec_r<1> a_addr_dec_r<0> a_tiel a_tiel a_tiel a_blc_r<7> a_blc_r<6> a_blc_r<5> a_blc_r<4> a_blt_r<7> a_blt_r<6> a_blt_r<5> a_blt_r<4> a_tieh<17> a_dclk_n_r<1> a_dclk_n_r<2> a_dclk_p_r<1> a_dclk_p_r<2> A_DOUT<17> A_DIN<17> a_rclk_n_r<1> a_rclk_n_r<2> a_rclk_p_r<1> a_rclk_p_r<2> a_tieh<17> a_wclk_n_r<1> a_wclk_n_r<2> a_wclk_p_r<1> a_wclk_p_r<2> b_addr_dec_r<3> b_addr_dec_r<2> b_addr_dec_r<1> b_addr_dec_r<0> b_tiel b_tiel b_tiel b_blc_r<7> b_blc_r<6> b_blc_r<5> b_blc_r<4> b_blt_r<7> b_blt_r<6> b_blt_r<5> b_blt_r<4> b_tieh<17> b_dclk_n_r<1> b_dclk_n_r<2> b_dclk_p_r<1> b_dclk_p_r<2> B_DOUT<17> B_DIN<17> b_rclk_n_r<1> b_rclk_n_r<2> b_rclk_p_r<1> b_rclk_p_r<2> b_tieh<17> b_wclk_n_r<1> b_wclk_n_r<2> b_wclk_p_r<1> b_wclk_p_r<2> VDD! VSS! / RM_IHPSG13_64x32_c2_2P_COLCTRL2 +XCOLCTRL<16> a_addr_dec_r<3> a_addr_dec_r<2> a_addr_dec_r<1> a_addr_dec_r<0> a_tiel a_tiel a_tiel a_blc_r<3> a_blc_r<2> a_blc_r<1> a_blc_r<0> a_blt_r<3> a_blt_r<2> a_blt_r<1> a_blt_r<0> a_tieh<16> a_dclk_n_r<0> a_dclk_n_r<1> a_dclk_p_r<0> a_dclk_p_r<1> A_DOUT<16> A_DIN<16> a_rclk_n_r<0> a_rclk_n_r<1> a_rclk_p_r<0> a_rclk_p_r<1> a_tieh<16> a_wclk_n_r<0> a_wclk_n_r<1> a_wclk_p_r<0> a_wclk_p_r<1> b_addr_dec_r<3> b_addr_dec_r<2> b_addr_dec_r<1> b_addr_dec_r<0> b_tiel b_tiel b_tiel b_blc_r<3> b_blc_r<2> b_blc_r<1> b_blc_r<0> b_blt_r<3> b_blt_r<2> b_blt_r<1> b_blt_r<0> b_tieh<16> b_dclk_n_r<0> b_dclk_n_r<1> b_dclk_p_r<0> b_dclk_p_r<1> B_DOUT<16> B_DIN<16> b_rclk_n_r<0> b_rclk_n_r<1> b_rclk_p_r<0> b_rclk_p_r<1> b_tieh<16> b_wclk_n_r<0> b_wclk_n_r<1> b_wclk_p_r<0> b_wclk_p_r<1> VDD! VSS! / RM_IHPSG13_64x32_c2_2P_COLCTRL2 +XCOLCTRL<15> a_addr_dec_l<3> a_addr_dec_l<2> a_addr_dec_l<1> a_addr_dec_l<0> a_tiel a_tiel a_tiel a_blc_l<63> a_blc_l<62> a_blc_l<61> a_blc_l<60> a_blt_l<63> a_blt_l<62> a_blt_l<61> a_blt_l<60> a_tieh<0> a_dclk_n_l<15> a_dclk_n_l<16> a_dclk_p_l<15> a_dclk_p_l<16> A_DOUT<0> A_DIN<0> a_rclk_n_l<15> a_rclk_n_l<16> a_rclk_p_l<15> a_rclk_p_l<16> a_tieh<0> a_wclk_n_l<15> a_wclk_n_l<16> a_wclk_p_l<15> a_wclk_p_l<16> b_addr_dec_l<3> b_addr_dec_l<2> b_addr_dec_l<1> b_addr_dec_l<0> b_tiel b_tiel b_tiel b_blc_l<63> b_blc_l<62> b_blc_l<61> b_blc_l<60> b_blt_l<63> b_blt_l<62> b_blt_l<61> b_blt_l<60> b_tieh<0> b_dclk_n_l<15> b_dclk_n_l<16> b_dclk_p_l<15> b_dclk_p_l<16> B_DOUT<0> B_DIN<0> b_rclk_n_l<15> b_rclk_n_l<16> b_rclk_p_l<15> b_rclk_p_l<16> b_tieh<0> b_wclk_n_l<15> b_wclk_n_l<16> b_wclk_p_l<15> b_wclk_p_l<16> VDD! VSS! / RM_IHPSG13_64x32_c2_2P_COLCTRL2 +XCOLCTRL<14> a_addr_dec_l<3> a_addr_dec_l<2> a_addr_dec_l<1> a_addr_dec_l<0> a_tiel a_tiel a_tiel a_blc_l<59> a_blc_l<58> a_blc_l<57> a_blc_l<56> a_blt_l<59> a_blt_l<58> a_blt_l<57> a_blt_l<56> a_tieh<1> a_dclk_n_l<14> a_dclk_n_l<15> a_dclk_p_l<14> a_dclk_p_l<15> A_DOUT<1> A_DIN<1> a_rclk_n_l<14> a_rclk_n_l<15> a_rclk_p_l<14> a_rclk_p_l<15> a_tieh<1> a_wclk_n_l<14> a_wclk_n_l<15> a_wclk_p_l<14> a_wclk_p_l<15> b_addr_dec_l<3> b_addr_dec_l<2> b_addr_dec_l<1> b_addr_dec_l<0> b_tiel b_tiel b_tiel b_blc_l<59> b_blc_l<58> b_blc_l<57> b_blc_l<56> b_blt_l<59> b_blt_l<58> b_blt_l<57> b_blt_l<56> b_tieh<1> b_dclk_n_l<14> b_dclk_n_l<15> b_dclk_p_l<14> b_dclk_p_l<15> B_DOUT<1> B_DIN<1> b_rclk_n_l<14> b_rclk_n_l<15> b_rclk_p_l<14> b_rclk_p_l<15> b_tieh<1> b_wclk_n_l<14> b_wclk_n_l<15> b_wclk_p_l<14> b_wclk_p_l<15> VDD! VSS! / RM_IHPSG13_64x32_c2_2P_COLCTRL2 +XCOLCTRL<13> a_addr_dec_l<3> a_addr_dec_l<2> a_addr_dec_l<1> a_addr_dec_l<0> a_tiel a_tiel a_tiel a_blc_l<55> a_blc_l<54> a_blc_l<53> a_blc_l<52> a_blt_l<55> a_blt_l<54> a_blt_l<53> a_blt_l<52> a_tieh<2> a_dclk_n_l<13> a_dclk_n_l<14> a_dclk_p_l<13> a_dclk_p_l<14> A_DOUT<2> A_DIN<2> a_rclk_n_l<13> a_rclk_n_l<14> a_rclk_p_l<13> a_rclk_p_l<14> a_tieh<2> a_wclk_n_l<13> a_wclk_n_l<14> a_wclk_p_l<13> a_wclk_p_l<14> b_addr_dec_l<3> b_addr_dec_l<2> b_addr_dec_l<1> b_addr_dec_l<0> b_tiel b_tiel b_tiel b_blc_l<55> b_blc_l<54> b_blc_l<53> b_blc_l<52> b_blt_l<55> b_blt_l<54> b_blt_l<53> b_blt_l<52> b_tieh<2> b_dclk_n_l<13> b_dclk_n_l<14> b_dclk_p_l<13> b_dclk_p_l<14> B_DOUT<2> B_DIN<2> b_rclk_n_l<13> b_rclk_n_l<14> b_rclk_p_l<13> b_rclk_p_l<14> b_tieh<2> b_wclk_n_l<13> b_wclk_n_l<14> b_wclk_p_l<13> b_wclk_p_l<14> VDD! VSS! / RM_IHPSG13_64x32_c2_2P_COLCTRL2 +XCOLCTRL<12> a_addr_dec_l<3> a_addr_dec_l<2> a_addr_dec_l<1> a_addr_dec_l<0> a_tiel a_tiel a_tiel a_blc_l<51> a_blc_l<50> a_blc_l<49> a_blc_l<48> a_blt_l<51> a_blt_l<50> a_blt_l<49> a_blt_l<48> a_tieh<3> a_dclk_n_l<12> a_dclk_n_l<13> a_dclk_p_l<12> a_dclk_p_l<13> A_DOUT<3> A_DIN<3> a_rclk_n_l<12> a_rclk_n_l<13> a_rclk_p_l<12> a_rclk_p_l<13> a_tieh<3> a_wclk_n_l<12> a_wclk_n_l<13> a_wclk_p_l<12> a_wclk_p_l<13> b_addr_dec_l<3> b_addr_dec_l<2> b_addr_dec_l<1> b_addr_dec_l<0> b_tiel b_tiel b_tiel b_blc_l<51> b_blc_l<50> b_blc_l<49> b_blc_l<48> b_blt_l<51> b_blt_l<50> b_blt_l<49> b_blt_l<48> b_tieh<3> b_dclk_n_l<12> b_dclk_n_l<13> b_dclk_p_l<12> b_dclk_p_l<13> B_DOUT<3> B_DIN<3> b_rclk_n_l<12> b_rclk_n_l<13> b_rclk_p_l<12> b_rclk_p_l<13> b_tieh<3> b_wclk_n_l<12> b_wclk_n_l<13> b_wclk_p_l<12> b_wclk_p_l<13> VDD! VSS! / RM_IHPSG13_64x32_c2_2P_COLCTRL2 +XCOLCTRL<11> a_addr_dec_l<3> a_addr_dec_l<2> a_addr_dec_l<1> a_addr_dec_l<0> a_tiel a_tiel a_tiel a_blc_l<47> a_blc_l<46> a_blc_l<45> a_blc_l<44> a_blt_l<47> a_blt_l<46> a_blt_l<45> a_blt_l<44> a_tieh<4> a_dclk_n_l<11> a_dclk_n_l<12> a_dclk_p_l<11> a_dclk_p_l<12> A_DOUT<4> A_DIN<4> a_rclk_n_l<11> a_rclk_n_l<12> a_rclk_p_l<11> a_rclk_p_l<12> a_tieh<4> a_wclk_n_l<11> a_wclk_n_l<12> a_wclk_p_l<11> a_wclk_p_l<12> b_addr_dec_l<3> b_addr_dec_l<2> b_addr_dec_l<1> b_addr_dec_l<0> b_tiel b_tiel b_tiel b_blc_l<47> b_blc_l<46> b_blc_l<45> b_blc_l<44> b_blt_l<47> b_blt_l<46> b_blt_l<45> b_blt_l<44> b_tieh<4> b_dclk_n_l<11> b_dclk_n_l<12> b_dclk_p_l<11> b_dclk_p_l<12> B_DOUT<4> B_DIN<4> b_rclk_n_l<11> b_rclk_n_l<12> b_rclk_p_l<11> b_rclk_p_l<12> b_tieh<4> b_wclk_n_l<11> b_wclk_n_l<12> b_wclk_p_l<11> b_wclk_p_l<12> VDD! VSS! / RM_IHPSG13_64x32_c2_2P_COLCTRL2 +XCOLCTRL<10> a_addr_dec_l<3> a_addr_dec_l<2> a_addr_dec_l<1> a_addr_dec_l<0> a_tiel a_tiel a_tiel a_blc_l<43> a_blc_l<42> a_blc_l<41> a_blc_l<40> a_blt_l<43> a_blt_l<42> a_blt_l<41> a_blt_l<40> a_tieh<5> a_dclk_n_l<10> a_dclk_n_l<11> a_dclk_p_l<10> a_dclk_p_l<11> A_DOUT<5> A_DIN<5> a_rclk_n_l<10> a_rclk_n_l<11> a_rclk_p_l<10> a_rclk_p_l<11> a_tieh<5> a_wclk_n_l<10> a_wclk_n_l<11> a_wclk_p_l<10> a_wclk_p_l<11> b_addr_dec_l<3> b_addr_dec_l<2> b_addr_dec_l<1> b_addr_dec_l<0> b_tiel b_tiel b_tiel b_blc_l<43> b_blc_l<42> b_blc_l<41> b_blc_l<40> b_blt_l<43> b_blt_l<42> b_blt_l<41> b_blt_l<40> b_tieh<5> b_dclk_n_l<10> b_dclk_n_l<11> b_dclk_p_l<10> b_dclk_p_l<11> B_DOUT<5> B_DIN<5> b_rclk_n_l<10> b_rclk_n_l<11> b_rclk_p_l<10> b_rclk_p_l<11> b_tieh<5> b_wclk_n_l<10> b_wclk_n_l<11> b_wclk_p_l<10> b_wclk_p_l<11> VDD! VSS! / RM_IHPSG13_64x32_c2_2P_COLCTRL2 +XCOLCTRL<9> a_addr_dec_l<3> a_addr_dec_l<2> a_addr_dec_l<1> a_addr_dec_l<0> a_tiel a_tiel a_tiel a_blc_l<39> a_blc_l<38> a_blc_l<37> a_blc_l<36> a_blt_l<39> a_blt_l<38> a_blt_l<37> a_blt_l<36> a_tieh<6> a_dclk_n_l<9> a_dclk_n_l<10> a_dclk_p_l<9> a_dclk_p_l<10> A_DOUT<6> A_DIN<6> a_rclk_n_l<9> a_rclk_n_l<10> a_rclk_p_l<9> a_rclk_p_l<10> a_tieh<6> a_wclk_n_l<9> a_wclk_n_l<10> a_wclk_p_l<9> a_wclk_p_l<10> b_addr_dec_l<3> b_addr_dec_l<2> b_addr_dec_l<1> b_addr_dec_l<0> b_tiel b_tiel b_tiel b_blc_l<39> b_blc_l<38> b_blc_l<37> b_blc_l<36> b_blt_l<39> b_blt_l<38> b_blt_l<37> b_blt_l<36> b_tieh<6> b_dclk_n_l<9> b_dclk_n_l<10> b_dclk_p_l<9> b_dclk_p_l<10> B_DOUT<6> B_DIN<6> b_rclk_n_l<9> b_rclk_n_l<10> b_rclk_p_l<9> b_rclk_p_l<10> b_tieh<6> b_wclk_n_l<9> b_wclk_n_l<10> b_wclk_p_l<9> b_wclk_p_l<10> VDD! VSS! / RM_IHPSG13_64x32_c2_2P_COLCTRL2 +XCOLCTRL<8> a_addr_dec_l<3> a_addr_dec_l<2> a_addr_dec_l<1> a_addr_dec_l<0> a_tiel a_tiel a_tiel a_blc_l<35> a_blc_l<34> a_blc_l<33> a_blc_l<32> a_blt_l<35> a_blt_l<34> a_blt_l<33> a_blt_l<32> a_tieh<7> a_dclk_n_l<8> a_dclk_n_l<9> a_dclk_p_l<8> a_dclk_p_l<9> A_DOUT<7> A_DIN<7> a_rclk_n_l<8> a_rclk_n_l<9> a_rclk_p_l<8> a_rclk_p_l<9> a_tieh<7> a_wclk_n_l<8> a_wclk_n_l<9> a_wclk_p_l<8> a_wclk_p_l<9> b_addr_dec_l<3> b_addr_dec_l<2> b_addr_dec_l<1> b_addr_dec_l<0> b_tiel b_tiel b_tiel b_blc_l<35> b_blc_l<34> b_blc_l<33> b_blc_l<32> b_blt_l<35> b_blt_l<34> b_blt_l<33> b_blt_l<32> b_tieh<7> b_dclk_n_l<8> b_dclk_n_l<9> b_dclk_p_l<8> b_dclk_p_l<9> B_DOUT<7> B_DIN<7> b_rclk_n_l<8> b_rclk_n_l<9> b_rclk_p_l<8> b_rclk_p_l<9> b_tieh<7> b_wclk_n_l<8> b_wclk_n_l<9> b_wclk_p_l<8> b_wclk_p_l<9> VDD! VSS! / RM_IHPSG13_64x32_c2_2P_COLCTRL2 +XCOLCTRL<7> a_addr_dec_l<3> a_addr_dec_l<2> a_addr_dec_l<1> a_addr_dec_l<0> a_tiel a_tiel a_tiel a_blc_l<31> a_blc_l<30> a_blc_l<29> a_blc_l<28> a_blt_l<31> a_blt_l<30> a_blt_l<29> a_blt_l<28> a_tieh<8> a_dclk_n_l<7> a_dclk_n_l<8> a_dclk_p_l<7> a_dclk_p_l<8> A_DOUT<8> A_DIN<8> a_rclk_n_l<7> a_rclk_n_l<8> a_rclk_p_l<7> a_rclk_p_l<8> a_tieh<8> a_wclk_n_l<7> a_wclk_n_l<8> a_wclk_p_l<7> a_wclk_p_l<8> b_addr_dec_l<3> b_addr_dec_l<2> b_addr_dec_l<1> b_addr_dec_l<0> b_tiel b_tiel b_tiel b_blc_l<31> b_blc_l<30> b_blc_l<29> b_blc_l<28> b_blt_l<31> b_blt_l<30> b_blt_l<29> b_blt_l<28> b_tieh<8> b_dclk_n_l<7> b_dclk_n_l<8> b_dclk_p_l<7> b_dclk_p_l<8> B_DOUT<8> B_DIN<8> b_rclk_n_l<7> b_rclk_n_l<8> b_rclk_p_l<7> b_rclk_p_l<8> b_tieh<8> b_wclk_n_l<7> b_wclk_n_l<8> b_wclk_p_l<7> b_wclk_p_l<8> VDD! VSS! / RM_IHPSG13_64x32_c2_2P_COLCTRL2 +XCOLCTRL<6> a_addr_dec_l<3> a_addr_dec_l<2> a_addr_dec_l<1> a_addr_dec_l<0> a_tiel a_tiel a_tiel a_blc_l<27> a_blc_l<26> a_blc_l<25> a_blc_l<24> a_blt_l<27> a_blt_l<26> a_blt_l<25> a_blt_l<24> a_tieh<9> a_dclk_n_l<6> a_dclk_n_l<7> a_dclk_p_l<6> a_dclk_p_l<7> A_DOUT<9> A_DIN<9> a_rclk_n_l<6> a_rclk_n_l<7> a_rclk_p_l<6> a_rclk_p_l<7> a_tieh<9> a_wclk_n_l<6> a_wclk_n_l<7> a_wclk_p_l<6> a_wclk_p_l<7> b_addr_dec_l<3> b_addr_dec_l<2> b_addr_dec_l<1> b_addr_dec_l<0> b_tiel b_tiel b_tiel b_blc_l<27> b_blc_l<26> b_blc_l<25> b_blc_l<24> b_blt_l<27> b_blt_l<26> b_blt_l<25> b_blt_l<24> b_tieh<9> b_dclk_n_l<6> b_dclk_n_l<7> b_dclk_p_l<6> b_dclk_p_l<7> B_DOUT<9> B_DIN<9> b_rclk_n_l<6> b_rclk_n_l<7> b_rclk_p_l<6> b_rclk_p_l<7> b_tieh<9> b_wclk_n_l<6> b_wclk_n_l<7> b_wclk_p_l<6> b_wclk_p_l<7> VDD! VSS! / RM_IHPSG13_64x32_c2_2P_COLCTRL2 +XCOLCTRL<5> a_addr_dec_l<3> a_addr_dec_l<2> a_addr_dec_l<1> a_addr_dec_l<0> a_tiel a_tiel a_tiel a_blc_l<23> a_blc_l<22> a_blc_l<21> a_blc_l<20> a_blt_l<23> a_blt_l<22> a_blt_l<21> a_blt_l<20> a_tieh<10> a_dclk_n_l<5> a_dclk_n_l<6> a_dclk_p_l<5> a_dclk_p_l<6> A_DOUT<10> A_DIN<10> a_rclk_n_l<5> a_rclk_n_l<6> a_rclk_p_l<5> a_rclk_p_l<6> a_tieh<10> a_wclk_n_l<5> a_wclk_n_l<6> a_wclk_p_l<5> a_wclk_p_l<6> b_addr_dec_l<3> b_addr_dec_l<2> b_addr_dec_l<1> b_addr_dec_l<0> b_tiel b_tiel b_tiel b_blc_l<23> b_blc_l<22> b_blc_l<21> b_blc_l<20> b_blt_l<23> b_blt_l<22> b_blt_l<21> b_blt_l<20> b_tieh<10> b_dclk_n_l<5> b_dclk_n_l<6> b_dclk_p_l<5> b_dclk_p_l<6> B_DOUT<10> B_DIN<10> b_rclk_n_l<5> b_rclk_n_l<6> b_rclk_p_l<5> b_rclk_p_l<6> b_tieh<10> b_wclk_n_l<5> b_wclk_n_l<6> b_wclk_p_l<5> b_wclk_p_l<6> VDD! VSS! / RM_IHPSG13_64x32_c2_2P_COLCTRL2 +XCOLCTRL<4> a_addr_dec_l<3> a_addr_dec_l<2> a_addr_dec_l<1> a_addr_dec_l<0> a_tiel a_tiel a_tiel a_blc_l<19> a_blc_l<18> a_blc_l<17> a_blc_l<16> a_blt_l<19> a_blt_l<18> a_blt_l<17> a_blt_l<16> a_tieh<11> a_dclk_n_l<4> a_dclk_n_l<5> a_dclk_p_l<4> a_dclk_p_l<5> A_DOUT<11> A_DIN<11> a_rclk_n_l<4> a_rclk_n_l<5> a_rclk_p_l<4> a_rclk_p_l<5> a_tieh<11> a_wclk_n_l<4> a_wclk_n_l<5> a_wclk_p_l<4> a_wclk_p_l<5> b_addr_dec_l<3> b_addr_dec_l<2> b_addr_dec_l<1> b_addr_dec_l<0> b_tiel b_tiel b_tiel b_blc_l<19> b_blc_l<18> b_blc_l<17> b_blc_l<16> b_blt_l<19> b_blt_l<18> b_blt_l<17> b_blt_l<16> b_tieh<11> b_dclk_n_l<4> b_dclk_n_l<5> b_dclk_p_l<4> b_dclk_p_l<5> B_DOUT<11> B_DIN<11> b_rclk_n_l<4> b_rclk_n_l<5> b_rclk_p_l<4> b_rclk_p_l<5> b_tieh<11> b_wclk_n_l<4> b_wclk_n_l<5> b_wclk_p_l<4> b_wclk_p_l<5> VDD! VSS! / RM_IHPSG13_64x32_c2_2P_COLCTRL2 +XCOLCTRL<3> a_addr_dec_l<3> a_addr_dec_l<2> a_addr_dec_l<1> a_addr_dec_l<0> a_tiel a_tiel a_tiel a_blc_l<15> a_blc_l<14> a_blc_l<13> a_blc_l<12> a_blt_l<15> a_blt_l<14> a_blt_l<13> a_blt_l<12> a_tieh<12> a_dclk_n_l<3> a_dclk_n_l<4> a_dclk_p_l<3> a_dclk_p_l<4> A_DOUT<12> A_DIN<12> a_rclk_n_l<3> a_rclk_n_l<4> a_rclk_p_l<3> a_rclk_p_l<4> a_tieh<12> a_wclk_n_l<3> a_wclk_n_l<4> a_wclk_p_l<3> a_wclk_p_l<4> b_addr_dec_l<3> b_addr_dec_l<2> b_addr_dec_l<1> b_addr_dec_l<0> b_tiel b_tiel b_tiel b_blc_l<15> b_blc_l<14> b_blc_l<13> b_blc_l<12> b_blt_l<15> b_blt_l<14> b_blt_l<13> b_blt_l<12> b_tieh<12> b_dclk_n_l<3> b_dclk_n_l<4> b_dclk_p_l<3> b_dclk_p_l<4> B_DOUT<12> B_DIN<12> b_rclk_n_l<3> b_rclk_n_l<4> b_rclk_p_l<3> b_rclk_p_l<4> b_tieh<12> b_wclk_n_l<3> b_wclk_n_l<4> b_wclk_p_l<3> b_wclk_p_l<4> VDD! VSS! / RM_IHPSG13_64x32_c2_2P_COLCTRL2 +XCOLCTRL<2> a_addr_dec_l<3> a_addr_dec_l<2> a_addr_dec_l<1> a_addr_dec_l<0> a_tiel a_tiel a_tiel a_blc_l<11> a_blc_l<10> a_blc_l<9> a_blc_l<8> a_blt_l<11> a_blt_l<10> a_blt_l<9> a_blt_l<8> a_tieh<13> a_dclk_n_l<2> a_dclk_n_l<3> a_dclk_p_l<2> a_dclk_p_l<3> A_DOUT<13> A_DIN<13> a_rclk_n_l<2> a_rclk_n_l<3> a_rclk_p_l<2> a_rclk_p_l<3> a_tieh<13> a_wclk_n_l<2> a_wclk_n_l<3> a_wclk_p_l<2> a_wclk_p_l<3> b_addr_dec_l<3> b_addr_dec_l<2> b_addr_dec_l<1> b_addr_dec_l<0> b_tiel b_tiel b_tiel b_blc_l<11> b_blc_l<10> b_blc_l<9> b_blc_l<8> b_blt_l<11> b_blt_l<10> b_blt_l<9> b_blt_l<8> b_tieh<13> b_dclk_n_l<2> b_dclk_n_l<3> b_dclk_p_l<2> b_dclk_p_l<3> B_DOUT<13> B_DIN<13> b_rclk_n_l<2> b_rclk_n_l<3> b_rclk_p_l<2> b_rclk_p_l<3> b_tieh<13> b_wclk_n_l<2> b_wclk_n_l<3> b_wclk_p_l<2> b_wclk_p_l<3> VDD! VSS! / RM_IHPSG13_64x32_c2_2P_COLCTRL2 +XCOLCTRL<1> a_addr_dec_l<3> a_addr_dec_l<2> a_addr_dec_l<1> a_addr_dec_l<0> a_tiel a_tiel a_tiel a_blc_l<7> a_blc_l<6> a_blc_l<5> a_blc_l<4> a_blt_l<7> a_blt_l<6> a_blt_l<5> a_blt_l<4> a_tieh<14> a_dclk_n_l<1> a_dclk_n_l<2> a_dclk_p_l<1> a_dclk_p_l<2> A_DOUT<14> A_DIN<14> a_rclk_n_l<1> a_rclk_n_l<2> a_rclk_p_l<1> a_rclk_p_l<2> a_tieh<14> a_wclk_n_l<1> a_wclk_n_l<2> a_wclk_p_l<1> a_wclk_p_l<2> b_addr_dec_l<3> b_addr_dec_l<2> b_addr_dec_l<1> b_addr_dec_l<0> b_tiel b_tiel b_tiel b_blc_l<7> b_blc_l<6> b_blc_l<5> b_blc_l<4> b_blt_l<7> b_blt_l<6> b_blt_l<5> b_blt_l<4> b_tieh<14> b_dclk_n_l<1> b_dclk_n_l<2> b_dclk_p_l<1> b_dclk_p_l<2> B_DOUT<14> B_DIN<14> b_rclk_n_l<1> b_rclk_n_l<2> b_rclk_p_l<1> b_rclk_p_l<2> b_tieh<14> b_wclk_n_l<1> b_wclk_n_l<2> b_wclk_p_l<1> b_wclk_p_l<2> VDD! VSS! / RM_IHPSG13_64x32_c2_2P_COLCTRL2 +XCOLCTRL<0> a_addr_dec_l<3> a_addr_dec_l<2> a_addr_dec_l<1> a_addr_dec_l<0> a_tiel a_tiel a_tiel a_blc_l<3> a_blc_l<2> a_blc_l<1> a_blc_l<0> a_blt_l<3> a_blt_l<2> a_blt_l<1> a_blt_l<0> a_tieh<15> a_dclk_n_l<0> a_dclk_n_l<1> a_dclk_p_l<0> a_dclk_p_l<1> A_DOUT<15> A_DIN<15> a_rclk_n_l<0> a_rclk_n_l<1> a_rclk_p_l<0> a_rclk_p_l<1> a_tieh<15> a_wclk_n_l<0> a_wclk_n_l<1> a_wclk_p_l<0> a_wclk_p_l<1> b_addr_dec_l<3> b_addr_dec_l<2> b_addr_dec_l<1> b_addr_dec_l<0> b_tiel b_tiel b_tiel b_blc_l<3> b_blc_l<2> b_blc_l<1> b_blc_l<0> b_blt_l<3> b_blt_l<2> b_blt_l<1> b_blt_l<0> b_tieh<15> b_dclk_n_l<0> b_dclk_n_l<1> b_dclk_p_l<0> b_dclk_p_l<1> B_DOUT<15> B_DIN<15> b_rclk_n_l<0> b_rclk_n_l<1> b_rclk_p_l<0> b_rclk_p_l<1> b_tieh<15> b_wclk_n_l<0> b_wclk_n_l<1> b_wclk_p_l<0> b_wclk_p_l<1> VDD! VSS! / RM_IHPSG13_64x32_c2_2P_COLCTRL2 + + +XDRVFILL4<1> VDD! VSS! / RM_IHPSG13_64x32_c2_2P_COLDRV13_FILL4 +XDRVFILL4<2> VDD! VSS! / RM_IHPSG13_64x32_c2_2P_COLDRV13_FILL4 +XDRVFILL4<3> VDD! VSS! / RM_IHPSG13_64x32_c2_2P_COLDRV13_FILL4 +XDRVFILL4<4> VDD! VSS! / RM_IHPSG13_64x32_c2_2P_COLDRV13_FILL4 +XDRVFILL4<5> VDD! VSS! / RM_IHPSG13_64x32_c2_2P_COLDRV13_FILL4 +XDRVFILL4<6> VDD! VSS! / RM_IHPSG13_64x32_c2_2P_COLDRV13_FILL4 +XDRVFILL4<7> VDD! VSS! / RM_IHPSG13_64x32_c2_2P_COLDRV13_FILL4 +XDRVFILL4<8> VDD! VSS! / RM_IHPSG13_64x32_c2_2P_COLDRV13_FILL4 +XDRVFILL4<9> VDD! VSS! / RM_IHPSG13_64x32_c2_2P_COLDRV13_FILL4 +XDRVFILL4<10> VDD! VSS! / RM_IHPSG13_64x32_c2_2P_COLDRV13_FILL4 +XCOLFILL4<1> VDD! VSS! / RM_IHPSG13_64x32_c2_2P_COLDRV13_FILL4C2 +XCOLFILL4<2> VDD! VSS! / RM_IHPSG13_64x32_c2_2P_COLDRV13_FILL4C2 +XCOLFILL4<3> VDD! VSS! / RM_IHPSG13_64x32_c2_2P_COLDRV13_FILL4C2 +XCOLFILL4<4> VDD! VSS! / RM_IHPSG13_64x32_c2_2P_COLDRV13_FILL4C2 +XCOLFILL4<5> VDD! VSS! / RM_IHPSG13_64x32_c2_2P_COLDRV13_FILL4C2 +XCOLFILL4<6> VDD! VSS! / RM_IHPSG13_64x32_c2_2P_COLDRV13_FILL4C2 +XCOLFILL4<7> VDD! VSS! / RM_IHPSG13_64x32_c2_2P_COLDRV13_FILL4C2 +XCOLFILL4<8> VDD! VSS! / RM_IHPSG13_64x32_c2_2P_COLDRV13_FILL4C2 +XCOLFILL4<9> VDD! VSS! / RM_IHPSG13_64x32_c2_2P_COLDRV13_FILL4C2 +XCOLFILL4<10> VDD! VSS! / RM_IHPSG13_64x32_c2_2P_COLDRV13_FILL4C2 +XCOLFILL4<11> VDD! VSS! / RM_IHPSG13_64x32_c2_2P_COLDRV13_FILL4C2 +XCOLFILL4<12> VDD! VSS! / RM_IHPSG13_64x32_c2_2P_COLDRV13_FILL4C2 +XCOLFILL4<13> VDD! VSS! / RM_IHPSG13_64x32_c2_2P_COLDRV13_FILL4C2 +XCOLFILL4<14> VDD! VSS! / RM_IHPSG13_64x32_c2_2P_COLDRV13_FILL4C2 +XCOLFILL4<15> VDD! VSS! / RM_IHPSG13_64x32_c2_2P_COLDRV13_FILL4C2 +XCOLFILL4<16> VDD! VSS! / RM_IHPSG13_64x32_c2_2P_COLDRV13_FILL4C2 +XCOLFILL4<17> VDD! VSS! / RM_IHPSG13_64x32_c2_2P_COLDRV13_FILL4C2 +XCOLFILL4<18> VDD! VSS! / RM_IHPSG13_64x32_c2_2P_COLDRV13_FILL4C2 +XCOLFILL4<19> VDD! VSS! / RM_IHPSG13_64x32_c2_2P_COLDRV13_FILL4C2 +XCOLFILL4<20> VDD! VSS! / RM_IHPSG13_64x32_c2_2P_COLDRV13_FILL4C2 +XCOLFILL4<21> VDD! VSS! / RM_IHPSG13_64x32_c2_2P_COLDRV13_FILL4C2 +XCOLFILL4<22> VDD! VSS! / RM_IHPSG13_64x32_c2_2P_COLDRV13_FILL4C2 +XCOLFILL4<23> VDD! VSS! / RM_IHPSG13_64x32_c2_2P_COLDRV13_FILL4C2 +XCOLFILL4<24> VDD! VSS! / RM_IHPSG13_64x32_c2_2P_COLDRV13_FILL4C2 +.ENDS diff --git a/flow/platforms/ihp-sg13g2/cdl/sg13g2_io.cdl b/flow/platforms/ihp-sg13g2/cdl/sg13g2_io.cdl index b7a31729f4..7265449958 100644 --- a/flow/platforms/ihp-sg13g2/cdl/sg13g2_io.cdl +++ b/flow/platforms/ihp-sg13g2/cdl/sg13g2_io.cdl @@ -902,11 +902,11 @@ XR2 iovss sub! / ptap1 r=214.8m A=4.3n Perim=262.3u w=65.575u l=65.575u ************************************************************************ * Library Name: sg13g2_io -* Cell Name: sg12g2_Gallery +* Cell Name: sg13g2_Gallery * View Name: schematic ************************************************************************ -.SUBCKT sg12g2_Gallery +.SUBCKT sg13g2_Gallery *.PININFO XI3 iovdd iovss vdd vss / sg13g2_IOPadIOVss XI4 iovdd iovss vdd vss / sg13g2_IOPadVdd @@ -944,4 +944,3 @@ XI23 iovdd iovss vdd vss / sg13g2_Filler2000 XI24 iovdd iovss vdd vss / sg13g2_Filler10000 XI25 iovdd iovss net31 net30 vdd vss / sg13g2_IOPadAnalog .ENDS - diff --git a/flow/platforms/ihp-sg13g2/cdl/sg13g2_stdcell.cdl b/flow/platforms/ihp-sg13g2/cdl/sg13g2_stdcell.cdl index 782eb87693..a8d76c5609 100644 --- a/flow/platforms/ihp-sg13g2/cdl/sg13g2_stdcell.cdl +++ b/flow/platforms/ihp-sg13g2/cdl/sg13g2_stdcell.cdl @@ -28,9 +28,9 @@ MN0 net1 A1 net2 VSS sg13_lv_nmos m=1 w=640.00n l=130.00n ng=1 MN1 net2 A2 VSS VSS sg13_lv_nmos m=1 w=640.00n l=130.00n ng=1 MN2 net1 B1 VSS VSS sg13_lv_nmos m=1 w=640.00n l=130.00n ng=1 MN3 X net1 VSS VSS sg13_lv_nmos m=1 w=740.00n l=130.00n ng=1 -MP0 net1 B1 net3 VDD sg13_lv_pmos m=1 w=1.000u l=130.00n ng=1 -MP1 net3 A1 VDD VDD sg13_lv_pmos m=1 w=1.000u l=130.00n ng=1 -MP2 net3 A2 VDD VDD sg13_lv_pmos m=1 w=1.000u l=130.00n ng=1 +MP2 net1 B1 net3 VDD sg13_lv_pmos m=1 w=1.000u l=130.00n ng=1 +MP0 net3 A1 VDD VDD sg13_lv_pmos m=1 w=1.000u l=130.00n ng=1 +MP1 net3 A2 VDD VDD sg13_lv_pmos m=1 w=1.000u l=130.00n ng=1 MP3 X net1 VDD VDD sg13_lv_pmos m=1 w=1.12u l=130.00n ng=1 .ENDS @@ -46,9 +46,9 @@ MN0 net1 A1 net2 VSS sg13_lv_nmos m=1 w=740.00n l=130.00n ng=1 MN1 net2 A2 VSS VSS sg13_lv_nmos m=1 w=740.00n l=130.00n ng=1 MN2 net1 B1 VSS VSS sg13_lv_nmos m=1 w=740.00n l=130.00n ng=1 MN3 X net1 VSS VSS sg13_lv_nmos m=1 w=1.48u l=130.00n ng=2 -MP0 net1 B1 net3 VDD sg13_lv_pmos m=1 w=1.000u l=130.00n ng=1 -MP1 net3 A1 VDD VDD sg13_lv_pmos m=1 w=1.000u l=130.00n ng=1 -MP2 net3 A2 VDD VDD sg13_lv_pmos m=1 w=1.000u l=130.00n ng=1 +MP2 net1 B1 net3 VDD sg13_lv_pmos m=1 w=1.000u l=130.00n ng=1 +MP0 net3 A1 VDD VDD sg13_lv_pmos m=1 w=1.000u l=130.00n ng=1 +MP1 net3 A2 VDD VDD sg13_lv_pmos m=1 w=1.000u l=130.00n ng=1 MP3 X net1 VDD VDD sg13_lv_pmos m=1 w=2.24u l=130.00n ng=2 .ENDS @@ -60,12 +60,12 @@ MP3 X net1 VDD VDD sg13_lv_pmos m=1 w=2.24u l=130.00n ng=2 .SUBCKT sg13g2_a21oi_1 Y A1 A2 B1 VDD VSS *.PININFO A1:I A2:I B1:I Y:O VDD:B VSS:B -MMNB0 Y B1 VSS VSS sg13_lv_nmos m=1 w=740.00n l=130.00n ng=1 -MMNA1 sndA1 A2 VSS VSS sg13_lv_nmos m=1 w=740.00n l=130.00n ng=1 -MMNA0 Y A1 sndA1 VSS sg13_lv_nmos m=1 w=740.00n l=130.00n ng=1 -MMPB0 Y B1 pndA VDD sg13_lv_pmos m=1 w=1.12u l=130.00n ng=1 -MMPA1 pndA A2 VDD VDD sg13_lv_pmos m=1 w=1.12u l=130.00n ng=1 -MMPA0 pndA A1 VDD VDD sg13_lv_pmos m=1 w=1.12u l=130.00n ng=1 +MN0 Y B1 VSS VSS sg13_lv_nmos m=1 w=740.00n l=130.00n ng=1 +MN2 net1 A2 VSS VSS sg13_lv_nmos m=1 w=740.00n l=130.00n ng=1 +MN1 Y A1 net1 VSS sg13_lv_nmos m=1 w=740.00n l=130.00n ng=1 +MP2 Y B1 net2 VDD sg13_lv_pmos m=1 w=1.12u l=130.00n ng=1 +MP1 net2 A2 VDD VDD sg13_lv_pmos m=1 w=1.12u l=130.00n ng=1 +MP0 net2 A1 VDD VDD sg13_lv_pmos m=1 w=1.12u l=130.00n ng=1 .ENDS ************************************************************************ @@ -76,12 +76,12 @@ MMPA0 pndA A1 VDD VDD sg13_lv_pmos m=1 w=1.12u l=130.00n ng=1 .SUBCKT sg13g2_a21oi_2 Y A1 A2 B1 VDD VSS *.PININFO A1:I A2:I B1:I Y:O VDD:B VSS:B -MMNB0 Y B1 VSS VSS sg13_lv_nmos m=1 w=1.48u l=130.00n ng=2 -MMNA1 sndA1 A2 VSS VSS sg13_lv_nmos m=1 w=1.48u l=130.00n ng=2 -MMNA0 Y A1 sndA1 VSS sg13_lv_nmos m=1 w=1.48u l=130.00n ng=2 -MMPB0 Y B1 pndA VDD sg13_lv_pmos m=1 w=2.24u l=130.00n ng=2 -MMPA1 pndA A2 VDD VDD sg13_lv_pmos m=1 w=2.24u l=130.00n ng=2 -MMPA0 pndA A1 VDD VDD sg13_lv_pmos m=1 w=2.24u l=130.00n ng=2 +MN0 Y B1 VSS VSS sg13_lv_nmos m=1 w=1.48u l=130.00n ng=2 +MN2 net2 A2 VSS VSS sg13_lv_nmos m=1 w=1.48u l=130.00n ng=2 +MN1 Y A1 net2 VSS sg13_lv_nmos m=1 w=1.48u l=130.00n ng=2 +MP2 Y B1 net1 VDD sg13_lv_pmos m=1 w=2.24u l=130.00n ng=2 +MP1 net1 A2 VDD VDD sg13_lv_pmos m=1 w=2.24u l=130.00n ng=2 +MP0 net1 A1 VDD VDD sg13_lv_pmos m=1 w=2.24u l=130.00n ng=2 .ENDS ************************************************************************ @@ -92,16 +92,16 @@ MMPA0 pndA A1 VDD VDD sg13_lv_pmos m=1 w=2.24u l=130.00n ng=2 .SUBCKT sg13g2_a221oi_1 Y A1 A2 B1 B2 C1 VDD VSS *.PININFO A1:I A2:I B1:I B2:I C1:I Y:O VDD:B VSS:B -MMPC0 Y C1 pndB VDD sg13_lv_pmos m=1 w=1.12u l=130.00n ng=1 -MMPB1 pndB B2 pndA VDD sg13_lv_pmos m=1 w=1.12u l=130.00n ng=1 -MMPB0 pndB B1 pndA VDD sg13_lv_pmos m=1 w=1.12u l=130.00n ng=1 -MMPA1 pndA A2 VDD VDD sg13_lv_pmos m=1 w=1.12u l=130.00n ng=1 -MMPA0 pndA A1 VDD VDD sg13_lv_pmos m=1 w=1.12u l=130.00n ng=1 -MMNC0 Y C1 VSS VSS sg13_lv_nmos m=1 w=740.00n l=130.00n ng=1 -MMNB1 sndB1 B2 VSS VSS sg13_lv_nmos m=1 w=740.00n l=130.00n ng=1 -MMNB0 Y B1 sndB1 VSS sg13_lv_nmos m=1 w=740.00n l=130.00n ng=1 -MMNA1 sndA1 A2 VSS VSS sg13_lv_nmos m=1 w=740.00n l=130.00n ng=1 -MMNA0 Y A1 sndA1 VSS sg13_lv_nmos m=1 w=740.00n l=130.00n ng=1 +MP2 Y C1 net3 VDD sg13_lv_pmos m=1 w=1.12u l=130.00n ng=1 +MP4 net3 B2 net1 VDD sg13_lv_pmos m=1 w=1.12u l=130.00n ng=1 +MP1 net3 B1 net1 VDD sg13_lv_pmos m=1 w=1.12u l=130.00n ng=1 +MP3 net1 A2 VDD VDD sg13_lv_pmos m=1 w=1.12u l=130.00n ng=1 +MP0 net1 A1 VDD VDD sg13_lv_pmos m=1 w=1.12u l=130.00n ng=1 +MN4 Y C1 VSS VSS sg13_lv_nmos m=1 w=740.00n l=130.00n ng=1 +MN3 net4 B2 VSS VSS sg13_lv_nmos m=1 w=740.00n l=130.00n ng=1 +MN2 Y B1 net4 VSS sg13_lv_nmos m=1 w=740.00n l=130.00n ng=1 +MN1 net2 A2 VSS VSS sg13_lv_nmos m=1 w=740.00n l=130.00n ng=1 +MN0 Y A1 net2 VSS sg13_lv_nmos m=1 w=740.00n l=130.00n ng=1 .ENDS ************************************************************************ @@ -112,12 +112,12 @@ MMNA0 Y A1 sndA1 VSS sg13_lv_nmos m=1 w=740.00n l=130.00n ng=1 .SUBCKT sg13g2_and2_1 X A B VDD VSS *.PININFO A:I B:I X:O VDD:B VSS:B -MX0 net4 A net2 VSS sg13_lv_nmos m=1 w=640.00n l=130.00n ng=1 -MX2 X net4 VSS VSS sg13_lv_nmos m=1 w=740.00n l=130.00n ng=1 -MX3 net2 B VSS VSS sg13_lv_nmos m=1 w=640.00n l=130.00n ng=1 -MX1 net4 B VDD VDD sg13_lv_pmos m=1 w=840.00n l=130.00n ng=1 -MX4 X net4 VDD VDD sg13_lv_pmos m=1 w=1.12u l=130.00n ng=1 -MX5 net4 A VDD VDD sg13_lv_pmos m=1 w=840.00n l=130.00n ng=1 +MN0 net4 A net2 VSS sg13_lv_nmos m=1 w=640.00n l=130.00n ng=1 +MN2 X net4 VSS VSS sg13_lv_nmos m=1 w=740.00n l=130.00n ng=1 +MN1 net2 B VSS VSS sg13_lv_nmos m=1 w=640.00n l=130.00n ng=1 +MP0 net4 B VDD VDD sg13_lv_pmos m=1 w=840.00n l=130.00n ng=1 +MP2 X net4 VDD VDD sg13_lv_pmos m=1 w=1.12u l=130.00n ng=1 +MP1 net4 A VDD VDD sg13_lv_pmos m=1 w=840.00n l=130.00n ng=1 .ENDS ************************************************************************ @@ -128,12 +128,12 @@ MX5 net4 A VDD VDD sg13_lv_pmos m=1 w=840.00n l=130.00n ng=1 .SUBCKT sg13g2_and2_2 X A B VDD VSS *.PININFO A:I B:I X:O VDD:B VSS:B -MX0 net4 A net2 VSS sg13_lv_nmos m=1 w=640.00n l=130.00n ng=1 -MX2 X net4 VSS VSS sg13_lv_nmos m=1 w=1.48u l=130.00n ng=2 -MX3 net2 B VSS VSS sg13_lv_nmos m=1 w=640.00n l=130.00n ng=1 -MX1 net4 B VDD VDD sg13_lv_pmos m=1 w=840.00n l=130.00n ng=1 -MX4 X net4 VDD VDD sg13_lv_pmos m=1 w=2.24u l=130.00n ng=2 -MX5 net4 A VDD VDD sg13_lv_pmos m=1 w=840.00n l=130.00n ng=1 +MN0 net1 A net2 VSS sg13_lv_nmos m=1 w=640.00n l=130.00n ng=1 +MN2 X net1 VSS VSS sg13_lv_nmos m=1 w=1.48u l=130.00n ng=2 +MN1 net2 B VSS VSS sg13_lv_nmos m=1 w=640.00n l=130.00n ng=1 +MP0 net1 B VDD VDD sg13_lv_pmos m=1 w=840.00n l=130.00n ng=1 +MP2 X net1 VDD VDD sg13_lv_pmos m=1 w=2.24u l=130.00n ng=2 +MP1 net1 A VDD VDD sg13_lv_pmos m=1 w=840.00n l=130.00n ng=1 .ENDS ************************************************************************ @@ -144,14 +144,14 @@ MX5 net4 A VDD VDD sg13_lv_pmos m=1 w=840.00n l=130.00n ng=1 .SUBCKT sg13g2_and3_1 X A B C VDD VSS *.PININFO A:I B:I C:I X:O VDD:B VSS:B -MX0 net3 C VSS VSS sg13_lv_nmos m=1 w=640.00n l=130.00n ng=1 -MX2 X net2 VSS VSS sg13_lv_nmos m=1 w=740.00n l=130.00n ng=1 -MX5 net2 A net1 VSS sg13_lv_nmos m=1 w=640.00n l=130.00n ng=1 -MX6 net1 B net3 VSS sg13_lv_nmos m=1 w=640.00n l=130.00n ng=1 -MX3 X net2 VDD VDD sg13_lv_pmos m=1 w=1.12u l=130.00n ng=1 -MX1 net2 B VDD VDD sg13_lv_pmos m=1 w=840.00n l=130.00n ng=1 -MX4 net2 A VDD VDD sg13_lv_pmos m=1 w=840.00n l=130.00n ng=1 -MX7 net2 C VDD VDD sg13_lv_pmos m=1 w=840.00n l=130.00n ng=1 +MN2 net3 C VSS VSS sg13_lv_nmos m=1 w=640.00n l=130.00n ng=1 +MN3 X net2 VSS VSS sg13_lv_nmos m=1 w=740.00n l=130.00n ng=1 +MN0 net2 A net1 VSS sg13_lv_nmos m=1 w=640.00n l=130.00n ng=1 +MN1 net1 B net3 VSS sg13_lv_nmos m=1 w=640.00n l=130.00n ng=1 +MP3 X net2 VDD VDD sg13_lv_pmos m=1 w=1.12u l=130.00n ng=1 +MP1 net2 B VDD VDD sg13_lv_pmos m=1 w=840.00n l=130.00n ng=1 +MP2 net2 A VDD VDD sg13_lv_pmos m=1 w=840.00n l=130.00n ng=1 +MP0 net2 C VDD VDD sg13_lv_pmos m=1 w=840.00n l=130.00n ng=1 .ENDS ************************************************************************ @@ -162,14 +162,14 @@ MX7 net2 C VDD VDD sg13_lv_pmos m=1 w=840.00n l=130.00n ng=1 .SUBCKT sg13g2_and3_2 X A B C VDD VSS *.PININFO A:I B:I C:I X:O VDD:B VSS:B -MX0 net3 C VSS VSS sg13_lv_nmos m=1 w=640.00n l=130.00n ng=1 -MX2 X net2 VSS VSS sg13_lv_nmos m=1 w=1.48u l=130.00n ng=2 -MX5 net2 A net1 VSS sg13_lv_nmos m=1 w=640.00n l=130.00n ng=1 -MX6 net1 B net3 VSS sg13_lv_nmos m=1 w=640.00n l=130.00n ng=1 -MX3 X net2 VDD VDD sg13_lv_pmos m=1 w=2.24u l=130.00n ng=2 -MX1 net2 B VDD VDD sg13_lv_pmos m=1 w=840.00n l=130.00n ng=1 -MX4 net2 A VDD VDD sg13_lv_pmos m=1 w=840.00n l=130.00n ng=1 -MX7 net2 C VDD VDD sg13_lv_pmos m=1 w=840.00n l=130.00n ng=1 +MN2 net3 C VSS VSS sg13_lv_nmos m=1 w=640.00n l=130.00n ng=1 +MN3 X net2 VSS VSS sg13_lv_nmos m=1 w=1.48u l=130.00n ng=2 +MN0 net2 A net1 VSS sg13_lv_nmos m=1 w=640.00n l=130.00n ng=1 +MN1 net1 B net3 VSS sg13_lv_nmos m=1 w=640.00n l=130.00n ng=1 +MP3 X net2 VDD VDD sg13_lv_pmos m=1 w=2.24u l=130.00n ng=2 +MP1 net2 B VDD VDD sg13_lv_pmos m=1 w=840.00n l=130.00n ng=1 +MP2 net2 A VDD VDD sg13_lv_pmos m=1 w=840.00n l=130.00n ng=1 +MP0 net2 C VDD VDD sg13_lv_pmos m=1 w=840.00n l=130.00n ng=1 .ENDS ************************************************************************ @@ -180,16 +180,16 @@ MX7 net2 C VDD VDD sg13_lv_pmos m=1 w=840.00n l=130.00n ng=1 .SUBCKT sg13g2_and4_1 X A B C D VDD VSS *.PININFO A:I B:I C:I D:I X:O VDD:B VSS:B -MN4 net17 D VSS VSS sg13_lv_nmos m=1 w=640.00n l=130.00n ng=1 -MN3 net16 C net17 VSS sg13_lv_nmos m=1 w=640.00n l=130.00n ng=1 -MN2 net15 B net16 VSS sg13_lv_nmos m=1 w=640.00n l=130.00n ng=1 -MN1 net1 A net15 VSS sg13_lv_nmos m=1 w=640.00n l=130.00n ng=1 -MN0 X net1 VSS VSS sg13_lv_nmos m=1 w=740.00n l=130.00n ng=1 -MP0 net1 A VDD VDD sg13_lv_pmos m=1 w=840.00n l=130.00n ng=1 +MN3 net17 D VSS VSS sg13_lv_nmos m=1 w=640.00n l=130.00n ng=1 +MN2 net16 C net17 VSS sg13_lv_nmos m=1 w=640.00n l=130.00n ng=1 +MN1 net15 B net16 VSS sg13_lv_nmos m=1 w=640.00n l=130.00n ng=1 +MN0 net1 A net15 VSS sg13_lv_nmos m=1 w=640.00n l=130.00n ng=1 +MN4 X net1 VSS VSS sg13_lv_nmos m=1 w=740.00n l=130.00n ng=1 +MP3 net1 A VDD VDD sg13_lv_pmos m=1 w=840.00n l=130.00n ng=1 MP4 X net1 VDD VDD sg13_lv_pmos m=1 w=1.12u l=130.00n ng=1 -MP3 net1 D VDD VDD sg13_lv_pmos m=1 w=840.00n l=130.00n ng=1 -MP2 net1 C VDD VDD sg13_lv_pmos m=1 w=840.00n l=130.00n ng=1 -MP1 net1 B VDD VDD sg13_lv_pmos m=1 w=840.00n l=130.00n ng=1 +MP0 net1 D VDD VDD sg13_lv_pmos m=1 w=840.00n l=130.00n ng=1 +MP1 net1 C VDD VDD sg13_lv_pmos m=1 w=840.00n l=130.00n ng=1 +MP2 net1 B VDD VDD sg13_lv_pmos m=1 w=840.00n l=130.00n ng=1 .ENDS ************************************************************************ @@ -200,16 +200,16 @@ MP1 net1 B VDD VDD sg13_lv_pmos m=1 w=840.00n l=130.00n ng=1 .SUBCKT sg13g2_and4_2 X A B C D VDD VSS *.PININFO A:I B:I C:I D:I X:O VDD:B VSS:B -MN4 net17 D VSS VSS sg13_lv_nmos m=1 w=640.00n l=130.00n ng=1 -MN3 net16 C net17 VSS sg13_lv_nmos m=1 w=640.00n l=130.00n ng=1 -MN2 net15 B net16 VSS sg13_lv_nmos m=1 w=640.00n l=130.00n ng=1 -MN1 net1 A net15 VSS sg13_lv_nmos m=1 w=640.00n l=130.00n ng=1 -MN0 X net1 VSS VSS sg13_lv_nmos m=1 w=1.48u l=130.00n ng=2 -MP0 net1 A VDD VDD sg13_lv_pmos m=1 w=840.00n l=130.00n ng=1 +MN3 net17 D VSS VSS sg13_lv_nmos m=1 w=640.00n l=130.00n ng=1 +MN2 net16 C net17 VSS sg13_lv_nmos m=1 w=640.00n l=130.00n ng=1 +MN1 net15 B net16 VSS sg13_lv_nmos m=1 w=640.00n l=130.00n ng=1 +MN0 net1 A net15 VSS sg13_lv_nmos m=1 w=640.00n l=130.00n ng=1 +MN4 X net1 VSS VSS sg13_lv_nmos m=1 w=1.48u l=130.00n ng=2 +MP3 net1 A VDD VDD sg13_lv_pmos m=1 w=840.00n l=130.00n ng=1 MP4 X net1 VDD VDD sg13_lv_pmos m=1 w=2.24u l=130.00n ng=2 -MP3 net1 D VDD VDD sg13_lv_pmos m=1 w=840.00n l=130.00n ng=1 -MP2 net1 C VDD VDD sg13_lv_pmos m=1 w=840.00n l=130.00n ng=1 -MP1 net1 B VDD VDD sg13_lv_pmos m=1 w=840.00n l=130.00n ng=1 +MP0 net1 D VDD VDD sg13_lv_pmos m=1 w=840.00n l=130.00n ng=1 +MP1 net1 C VDD VDD sg13_lv_pmos m=1 w=840.00n l=130.00n ng=1 +MP2 net1 B VDD VDD sg13_lv_pmos m=1 w=840.00n l=130.00n ng=1 .ENDS ************************************************************************ @@ -220,7 +220,7 @@ MP1 net1 B VDD VDD sg13_lv_pmos m=1 w=840.00n l=130.00n ng=1 .SUBCKT sg13g2_antennanp A VDD VSS *.PININFO A:I VDD:B VSS:B -Ddn_1 VSS A dantenna m=1 w=780n l=780n a=608.4f p=3.12u +DD1 VSS A dantenna m=1 w=780n l=780n a=608.4f p=3.12u DD0 A VDD dpantenna m=1 w=1.05u l=1.34u a=1.407p p=4.78u .ENDS @@ -232,8 +232,8 @@ DD0 A VDD dpantenna m=1 w=1.05u l=1.34u a=1.407p p=4.78u .SUBCKT sg13g2_buf_1 X A VDD VSS *.PININFO A:I X:O VDD:B VSS:B -MN1 net1 A VSS VSS sg13_lv_nmos m=1 w=550.00n l=130.00n ng=1 -MN0 X net1 VSS VSS sg13_lv_nmos m=1 w=740.00n l=130.00n ng=1 +MN0 net1 A VSS VSS sg13_lv_nmos m=1 w=550.00n l=130.00n ng=1 +MN1 X net1 VSS VSS sg13_lv_nmos m=1 w=740.00n l=130.00n ng=1 MP1 X net1 VDD VDD sg13_lv_pmos m=1 w=1.12u l=130.00n ng=1 MP0 net1 A VDD VDD sg13_lv_pmos m=1 w=840.00n l=130.00n ng=1 .ENDS @@ -246,8 +246,8 @@ MP0 net1 A VDD VDD sg13_lv_pmos m=1 w=840.00n l=130.00n ng=1 .SUBCKT sg13g2_buf_16 X A VDD VSS *.PININFO A:I X:O VDD:B VSS:B -MN1 net1 A VSS VSS sg13_lv_nmos m=1 w=4.44u l=130.00n ng=6 -MN0 X net1 VSS VSS sg13_lv_nmos m=1 w=11.84u l=130.00n ng=16 +MN0 net1 A VSS VSS sg13_lv_nmos m=1 w=4.44u l=130.00n ng=6 +MN1 X net1 VSS VSS sg13_lv_nmos m=1 w=11.84u l=130.00n ng=16 MP1 X net1 VDD VDD sg13_lv_pmos m=1 w=17.92u l=130.00n ng=16 MP0 net1 A VDD VDD sg13_lv_pmos m=1 w=6.72u l=130.00n ng=6 .ENDS @@ -260,8 +260,8 @@ MP0 net1 A VDD VDD sg13_lv_pmos m=1 w=6.72u l=130.00n ng=6 .SUBCKT sg13g2_buf_2 X A VDD VSS *.PININFO A:I X:O VDD:B VSS:B -MN1 net1 A VSS VSS sg13_lv_nmos m=1 w=640.00n l=130.00n ng=1 -MN0 X net1 VSS VSS sg13_lv_nmos m=1 w=1.48u l=130.00n ng=2 +MN0 net1 A VSS VSS sg13_lv_nmos m=1 w=640.00n l=130.00n ng=1 +MN1 X net1 VSS VSS sg13_lv_nmos m=1 w=1.48u l=130.00n ng=2 MP1 X net1 VDD VDD sg13_lv_pmos m=1 w=2.24u l=130.00n ng=2 MP0 net1 A VDD VDD sg13_lv_pmos m=1 w=1.000u l=130.00n ng=1 .ENDS @@ -274,8 +274,8 @@ MP0 net1 A VDD VDD sg13_lv_pmos m=1 w=1.000u l=130.00n ng=1 .SUBCKT sg13g2_buf_4 X A VDD VSS *.PININFO A:I X:O VDD:B VSS:B -MN1 net1 A VSS VSS sg13_lv_nmos m=1 w=740.00n l=130.00n ng=1 -MN0 X net1 VSS VSS sg13_lv_nmos m=1 w=2.96u l=130.00n ng=4 +MN0 net1 A VSS VSS sg13_lv_nmos m=1 w=740.00n l=130.00n ng=1 +MN1 X net1 VSS VSS sg13_lv_nmos m=1 w=2.96u l=130.00n ng=4 MP1 X net1 VDD VDD sg13_lv_pmos m=1 w=4.48u l=130.00n ng=4 MP0 net1 A VDD VDD sg13_lv_pmos m=1 w=1.68u l=130.00n ng=2 .ENDS @@ -288,8 +288,8 @@ MP0 net1 A VDD VDD sg13_lv_pmos m=1 w=1.68u l=130.00n ng=2 .SUBCKT sg13g2_buf_8 X A VDD VSS *.PININFO A:I X:O VDD:B VSS:B -MN1 net1 A VSS VSS sg13_lv_nmos m=1 w=2.22u l=130.00n ng=3 -MN0 X net1 VSS VSS sg13_lv_nmos m=1 w=5.92u l=130.00n ng=8 +MN0 net1 A VSS VSS sg13_lv_nmos m=1 w=2.22u l=130.00n ng=3 +MN1 X net1 VSS VSS sg13_lv_nmos m=1 w=5.92u l=130.00n ng=8 MP1 X net1 VDD VDD sg13_lv_pmos m=1 w=8.96u l=130.00n ng=8 MP0 net1 A VDD VDD sg13_lv_pmos m=1 w=3.36u l=130.00n ng=3 .ENDS @@ -302,8 +302,8 @@ MP0 net1 A VDD VDD sg13_lv_pmos m=1 w=3.36u l=130.00n ng=3 .SUBCKT sg13g2_decap_4 VDD VSS *.PININFO VDD:B VSS:B -MX1 VSS VDD VSS VSS sg13_lv_nmos m=1 w=420.00n l=1.000u ng=1 -MX0 VDD VSS VDD VDD sg13_lv_pmos m=1 w=1.000u l=1.000u ng=1 +MN0 VSS VDD VSS VSS sg13_lv_nmos m=1 w=420.00n l=1.000u ng=1 +MP0 VDD VSS VDD VDD sg13_lv_pmos m=1 w=1.000u l=1.000u ng=1 .ENDS ************************************************************************ @@ -314,8 +314,8 @@ MX0 VDD VSS VDD VDD sg13_lv_pmos m=1 w=1.000u l=1.000u ng=1 .SUBCKT sg13g2_decap_8 VDD VSS *.PININFO VDD:B VSS:B -MX1 VSS VDD VSS VSS sg13_lv_nmos m=1 w=840.00n l=1.000u ng=2 -MX0 VDD VSS VDD VDD sg13_lv_pmos m=1 w=2.000u l=1.000u ng=2 +MN0 VSS VDD VSS VSS sg13_lv_nmos m=1 w=840.00n l=1.000u ng=2 +MP0 VDD VSS VDD VDD sg13_lv_pmos m=1 w=2.000u l=1.000u ng=2 .ENDS ************************************************************************ @@ -326,40 +326,40 @@ MX0 VDD VSS VDD VDD sg13_lv_pmos m=1 w=2.000u l=1.000u ng=2 .SUBCKT sg13g2_dfrbp_1 Q Q_N CLK D RESET_B VDD VSS *.PININFO CLK:I D:I RESET_B:I Q:O Q_N:O VDD:B VSS:B -MN13 net12 net2 VSS VSS sg13_lv_nmos m=1 w=420.00n l=130.00n ng=1 -MN14 net5 clkneg net12 VSS sg13_lv_nmos m=1 w=420.00n l=130.00n ng=1 -MN15 net2 net5 net11 VSS sg13_lv_nmos m=1 w=420.00n l=130.00n ng=1 -MN16 net11 RESET_B VSS VSS sg13_lv_nmos m=1 w=420.00n l=130.00n ng=1 -MN6 Q_N net5 VSS VSS sg13_lv_nmos m=1 w=740.00n l=130.00n ng=1 +MN11 net12 net2 VSS VSS sg13_lv_nmos m=1 w=420.00n l=130.00n ng=1 +MN10 net5 clkneg net12 VSS sg13_lv_nmos m=1 w=420.00n l=130.00n ng=1 +MN12 net2 net5 net11 VSS sg13_lv_nmos m=1 w=420.00n l=130.00n ng=1 +MN13 net11 RESET_B VSS VSS sg13_lv_nmos m=1 w=420.00n l=130.00n ng=1 +MN14 Q_N net5 VSS VSS sg13_lv_nmos m=1 w=740.00n l=130.00n ng=1 MN0 Db D net10 VSS sg13_lv_nmos m=1 w=420.00n l=130.00n ng=1 MN1 net10 RESET_B VSS VSS sg13_lv_nmos m=1 w=420.00n l=130.00n ng=1 -MN7 Db clkneg net6 VSS sg13_lv_nmos m=1 w=420.00n l=130.00n ng=1 -MN8 net6 clkpos net9 VSS sg13_lv_nmos m=1 w=420.00n l=130.00n ng=1 -MN9 net9 net4 net8 VSS sg13_lv_nmos m=1 w=420.00n l=130.00n ng=1 -MN10 net8 RESET_B VSS VSS sg13_lv_nmos m=1 w=420.00n l=130.00n ng=1 -MN11 net4 net6 VSS VSS sg13_lv_nmos m=1 w=740.00n l=130.00n ng=1 +MN4 Db clkneg net6 VSS sg13_lv_nmos m=1 w=420.00n l=130.00n ng=1 +MN5 net6 clkpos net9 VSS sg13_lv_nmos m=1 w=420.00n l=130.00n ng=1 +MN6 net9 net4 net8 VSS sg13_lv_nmos m=1 w=420.00n l=130.00n ng=1 +MN7 net8 RESET_B VSS VSS sg13_lv_nmos m=1 w=420.00n l=130.00n ng=1 +MN8 net4 net6 VSS VSS sg13_lv_nmos m=1 w=740.00n l=130.00n ng=1 MN2 clkneg CLK VSS VSS sg13_lv_nmos m=1 w=740.00n l=130.00n ng=1 -MN12 net4 clkpos net5 VSS sg13_lv_nmos m=1 w=740.00n l=130.00n ng=1 +MN9 net4 clkpos net5 VSS sg13_lv_nmos m=1 w=740.00n l=130.00n ng=1 MN3 clkpos clkneg VSS VSS sg13_lv_nmos m=1 w=740.00n l=130.00n ng=1 -MN4 Q net1 VSS VSS sg13_lv_nmos m=1 w=740.00n l=130.00n ng=1 -MN5 net1 net5 VSS VSS sg13_lv_nmos m=1 w=740.00n l=130.00n ng=1 -MP14 net5 clkpos net3 VDD sg13_lv_pmos m=1 w=420.00n l=130.00n ng=1 -MP15 net2 net5 VDD VDD sg13_lv_pmos m=1 w=420.00n l=130.00n ng=1 -MP16 net2 RESET_B VDD VDD sg13_lv_pmos m=1 w=420.00n l=130.00n ng=1 -MP6 Q_N net5 VDD VDD sg13_lv_pmos m=1 w=1.12u l=130.00n ng=1 -MP7 Db clkpos net6 VDD sg13_lv_pmos m=1 w=420.00n l=130.00n ng=1 +MN16 Q net1 VSS VSS sg13_lv_nmos m=1 w=740.00n l=130.00n ng=1 +MN15 net1 net5 VSS VSS sg13_lv_nmos m=1 w=740.00n l=130.00n ng=1 +MP11 net5 clkpos net3 VDD sg13_lv_pmos m=1 w=420.00n l=130.00n ng=1 +MP12 net2 net5 VDD VDD sg13_lv_pmos m=1 w=420.00n l=130.00n ng=1 +MP13 net2 RESET_B VDD VDD sg13_lv_pmos m=1 w=420.00n l=130.00n ng=1 +MP14 Q_N net5 VDD VDD sg13_lv_pmos m=1 w=1.12u l=130.00n ng=1 +MP4 Db clkpos net6 VDD sg13_lv_pmos m=1 w=420.00n l=130.00n ng=1 MP0 Db RESET_B VDD VDD sg13_lv_pmos m=1 w=420.00n l=130.00n ng=1 MP1 Db D VDD VDD sg13_lv_pmos m=1 w=420.00n l=130.00n ng=1 -MP8 net7 net4 VDD VDD sg13_lv_pmos m=1 w=420.00n l=130.00n ng=1 -MP9 net6 clkneg net7 VDD sg13_lv_pmos m=1 w=420.00n l=130.00n ng=1 -MP10 net6 RESET_B VDD VDD sg13_lv_pmos m=1 w=420.00n l=130.00n ng=1 +MP5 net7 net4 VDD VDD sg13_lv_pmos m=1 w=420.00n l=130.00n ng=1 +MP6 net6 clkneg net7 VDD sg13_lv_pmos m=1 w=420.00n l=130.00n ng=1 +MP7 net6 RESET_B VDD VDD sg13_lv_pmos m=1 w=420.00n l=130.00n ng=1 MP2 clkneg CLK VDD VDD sg13_lv_pmos m=1 w=1.12u l=130.00n ng=1 MP3 clkpos clkneg VDD VDD sg13_lv_pmos m=1 w=1.12u l=130.00n ng=1 -MP11 net4 net6 VDD VDD sg13_lv_pmos m=1 w=1.000u l=130.00n ng=1 -MP12 net4 clkneg net5 VDD sg13_lv_pmos m=1 w=1.000u l=130.00n ng=1 -MP4 Q net1 VDD VDD sg13_lv_pmos m=1 w=1.12u l=130.00n ng=1 -MP13 net3 net2 VDD VDD sg13_lv_pmos m=1 w=420.00n l=130.00n ng=1 -MP5 net1 net5 VDD VDD sg13_lv_pmos m=1 w=1.12u l=130.00n ng=1 +MP8 net4 net6 VDD VDD sg13_lv_pmos m=1 w=1.000u l=130.00n ng=1 +MP9 net4 clkneg net5 VDD sg13_lv_pmos m=1 w=1.000u l=130.00n ng=1 +MP16 Q net1 VDD VDD sg13_lv_pmos m=1 w=1.12u l=130.00n ng=1 +MP10 net3 net2 VDD VDD sg13_lv_pmos m=1 w=420.00n l=130.00n ng=1 +MP15 net1 net5 VDD VDD sg13_lv_pmos m=1 w=1.12u l=130.00n ng=1 .ENDS ************************************************************************ @@ -370,40 +370,40 @@ MP5 net1 net5 VDD VDD sg13_lv_pmos m=1 w=1.12u l=130.00n ng=1 .SUBCKT sg13g2_dfrbp_2 Q Q_N CLK D RESET_B VDD VSS *.PININFO CLK:I D:I RESET_B:I Q:O Q_N:O VDD:B VSS:B -MN13 net12 net2 VSS VSS sg13_lv_nmos m=1 w=420.00n l=130.00n ng=1 -MN14 net5 clkneg net12 VSS sg13_lv_nmos m=1 w=420.00n l=130.00n ng=1 -MN15 net2 net5 net11 VSS sg13_lv_nmos m=1 w=420.00n l=130.00n ng=1 -MN16 net11 RESET_B VSS VSS sg13_lv_nmos m=1 w=420.00n l=130.00n ng=1 -MN6 Q_N net5 VSS VSS sg13_lv_nmos m=1 w=1.48u l=130.00n ng=2 +MN11 net12 net2 VSS VSS sg13_lv_nmos m=1 w=420.00n l=130.00n ng=1 +MN10 net5 clkneg net12 VSS sg13_lv_nmos m=1 w=420.00n l=130.00n ng=1 +MN12 net2 net5 net11 VSS sg13_lv_nmos m=1 w=420.00n l=130.00n ng=1 +MN13 net11 RESET_B VSS VSS sg13_lv_nmos m=1 w=420.00n l=130.00n ng=1 +MN14 Q_N net5 VSS VSS sg13_lv_nmos m=1 w=1.48u l=130.00n ng=2 MN0 Db D net10 VSS sg13_lv_nmos m=1 w=420.00n l=130.00n ng=1 MN1 net10 RESET_B VSS VSS sg13_lv_nmos m=1 w=420.00n l=130.00n ng=1 -MN7 Db clkneg net6 VSS sg13_lv_nmos m=1 w=420.00n l=130.00n ng=1 -MN8 net6 clkpos net9 VSS sg13_lv_nmos m=1 w=420.00n l=130.00n ng=1 -MN9 net9 net4 net8 VSS sg13_lv_nmos m=1 w=420.00n l=130.00n ng=1 -MN10 net8 RESET_B VSS VSS sg13_lv_nmos m=1 w=420.00n l=130.00n ng=1 -MN11 net4 net6 VSS VSS sg13_lv_nmos m=1 w=740.00n l=130.00n ng=1 +MN4 Db clkneg net6 VSS sg13_lv_nmos m=1 w=420.00n l=130.00n ng=1 +MN5 net6 clkpos net9 VSS sg13_lv_nmos m=1 w=420.00n l=130.00n ng=1 +MN6 net9 net4 net8 VSS sg13_lv_nmos m=1 w=420.00n l=130.00n ng=1 +MN7 net8 RESET_B VSS VSS sg13_lv_nmos m=1 w=420.00n l=130.00n ng=1 +MN8 net4 net6 VSS VSS sg13_lv_nmos m=1 w=740.00n l=130.00n ng=1 MN2 clkneg CLK VSS VSS sg13_lv_nmos m=1 w=740.00n l=130.00n ng=1 -MN12 net4 clkpos net5 VSS sg13_lv_nmos m=1 w=740.00n l=130.00n ng=1 +MN9 net4 clkpos net5 VSS sg13_lv_nmos m=1 w=740.00n l=130.00n ng=1 MN3 clkpos clkneg VSS VSS sg13_lv_nmos m=1 w=740.00n l=130.00n ng=1 -MN4 Q net1 VSS VSS sg13_lv_nmos m=1 w=1.48u l=130.00n ng=2 -MN5 net1 net5 VSS VSS sg13_lv_nmos m=1 w=640.00n l=130.00n ng=1 -MP14 net5 clkpos net3 VDD sg13_lv_pmos m=1 w=420.00n l=130.00n ng=1 -MP15 net2 net5 VDD VDD sg13_lv_pmos m=1 w=420.00n l=130.00n ng=1 -MP16 net2 RESET_B VDD VDD sg13_lv_pmos m=1 w=420.00n l=130.00n ng=1 -MP6 Q_N net5 VDD VDD sg13_lv_pmos m=1 w=2.24u l=130.00n ng=2 -MP7 Db clkpos net6 VDD sg13_lv_pmos m=1 w=420.00n l=130.00n ng=1 +MN16 Q net1 VSS VSS sg13_lv_nmos m=1 w=1.48u l=130.00n ng=2 +MN15 net1 net5 VSS VSS sg13_lv_nmos m=1 w=640.00n l=130.00n ng=1 +MP11 net5 clkpos net3 VDD sg13_lv_pmos m=1 w=420.00n l=130.00n ng=1 +MP12 net2 net5 VDD VDD sg13_lv_pmos m=1 w=420.00n l=130.00n ng=1 +MP13 net2 RESET_B VDD VDD sg13_lv_pmos m=1 w=420.00n l=130.00n ng=1 +MP14 Q_N net5 VDD VDD sg13_lv_pmos m=1 w=2.24u l=130.00n ng=2 +MP4 Db clkpos net6 VDD sg13_lv_pmos m=1 w=420.00n l=130.00n ng=1 MP0 Db RESET_B VDD VDD sg13_lv_pmos m=1 w=420.00n l=130.00n ng=1 MP1 Db D VDD VDD sg13_lv_pmos m=1 w=420.00n l=130.00n ng=1 -MP8 net7 net4 VDD VDD sg13_lv_pmos m=1 w=420.00n l=130.00n ng=1 -MP9 net6 clkneg net7 VDD sg13_lv_pmos m=1 w=420.00n l=130.00n ng=1 -MP10 net6 RESET_B VDD VDD sg13_lv_pmos m=1 w=420.00n l=130.00n ng=1 +MP5 net7 net4 VDD VDD sg13_lv_pmos m=1 w=420.00n l=130.00n ng=1 +MP6 net6 clkneg net7 VDD sg13_lv_pmos m=1 w=420.00n l=130.00n ng=1 +MP7 net6 RESET_B VDD VDD sg13_lv_pmos m=1 w=420.00n l=130.00n ng=1 MP2 clkneg CLK VDD VDD sg13_lv_pmos m=1 w=1.12u l=130.00n ng=1 MP3 clkpos clkneg VDD VDD sg13_lv_pmos m=1 w=1.12u l=130.00n ng=1 -MP11 net4 net6 VDD VDD sg13_lv_pmos m=1 w=1.000u l=130.00n ng=1 -MP12 net4 clkneg net5 VDD sg13_lv_pmos m=1 w=1.000u l=130.00n ng=1 -MP4 Q net1 VDD VDD sg13_lv_pmos m=1 w=2.24u l=130.00n ng=2 -MP13 net3 net2 VDD VDD sg13_lv_pmos m=1 w=420.00n l=130.00n ng=1 -MP5 net1 net5 VDD VDD sg13_lv_pmos m=1 w=1.000u l=130.00n ng=1 +MP8 net4 net6 VDD VDD sg13_lv_pmos m=1 w=1.000u l=130.00n ng=1 +MP9 net4 clkneg net5 VDD sg13_lv_pmos m=1 w=1.000u l=130.00n ng=1 +MP16 Q net1 VDD VDD sg13_lv_pmos m=1 w=2.24u l=130.00n ng=2 +MP10 net3 net2 VDD VDD sg13_lv_pmos m=1 w=420.00n l=130.00n ng=1 +MP15 net1 net5 VDD VDD sg13_lv_pmos m=1 w=1.000u l=130.00n ng=1 .ENDS ************************************************************************ @@ -414,24 +414,24 @@ MP5 net1 net5 VDD VDD sg13_lv_pmos m=1 w=1.000u l=130.00n ng=1 .SUBCKT sg13g2_dlhq_1 Q D GATE VDD VSS *.PININFO D:I GATE:I Q:O VDD:B VSS:B -MX17 Q qint_b VDD VDD sg13_lv_pmos m=1 w=1.12u l=130.00n ng=1 -MX16 qint GATE_BB net8 VDD sg13_lv_pmos m=1 w=420.00n l=130.00n ng=1 -MX14 qint_b qint VDD VDD sg13_lv_pmos m=1 w=1.12u l=130.00n ng=1 -MX12 Db D VDD VDD sg13_lv_pmos m=1 w=840.00n l=130.00n ng=1 -MX9 GATE_B GATE VDD VDD sg13_lv_pmos m=1 w=840.00n l=130.00n ng=1 -MX7 GATE_BB GATE_B VDD VDD sg13_lv_pmos m=1 w=840.00n l=130.00n ng=1 -MX4 net8 qint_b VDD VDD sg13_lv_pmos m=1 w=420.00n l=130.00n ng=1 -MX3 net4 GATE_B qint VDD sg13_lv_pmos m=1 w=1.000u l=130.00n ng=1 -MX1 net4 Db VDD VDD sg13_lv_pmos m=1 w=1.000u l=130.00n ng=1 -MX15 GATE_B GATE VSS VSS sg13_lv_nmos m=1 w=740.00n l=130.00n ng=1 -MX13 GATE_BB GATE_B VSS VSS sg13_lv_nmos m=1 w=740.00n l=130.00n ng=1 -MX11 qint GATE_B net9 VSS sg13_lv_nmos m=1 w=420.00n l=130.00n ng=1 -MX10 Q qint_b VSS VSS sg13_lv_nmos m=1 w=740.00n l=130.00n ng=1 -MX8 net7 Db VSS VSS sg13_lv_nmos m=1 w=740.00n l=130.00n ng=1 -MX6 net9 qint_b VSS VSS sg13_lv_nmos m=1 w=420.00n l=130.00n ng=1 -MX5 qint_b qint VSS VSS sg13_lv_nmos m=1 w=740.00n l=130.00n ng=1 -MX2 qint GATE_BB net7 VSS sg13_lv_nmos m=1 w=740.00n l=130.00n ng=1 -MX0 Db D VSS VSS sg13_lv_nmos m=1 w=550.00n l=130.00n ng=1 +MP8 Q qint_b VDD VDD sg13_lv_pmos m=1 w=1.12u l=130.00n ng=1 +MP6 qint GATE_BB net8 VDD sg13_lv_pmos m=1 w=420.00n l=130.00n ng=1 +MP7 qint_b qint VDD VDD sg13_lv_pmos m=1 w=1.12u l=130.00n ng=1 +MP2 Db D VDD VDD sg13_lv_pmos m=1 w=840.00n l=130.00n ng=1 +MP0 GATE_B GATE VDD VDD sg13_lv_pmos m=1 w=840.00n l=130.00n ng=1 +MP1 GATE_BB GATE_B VDD VDD sg13_lv_pmos m=1 w=840.00n l=130.00n ng=1 +MP5 net8 qint_b VDD VDD sg13_lv_pmos m=1 w=420.00n l=130.00n ng=1 +MP4 net4 GATE_B qint VDD sg13_lv_pmos m=1 w=1.000u l=130.00n ng=1 +MP3 net4 Db VDD VDD sg13_lv_pmos m=1 w=1.000u l=130.00n ng=1 +MN0 GATE_B GATE VSS VSS sg13_lv_nmos m=1 w=740.00n l=130.00n ng=1 +MN1 GATE_BB GATE_B VSS VSS sg13_lv_nmos m=1 w=740.00n l=130.00n ng=1 +MN5 qint GATE_B net9 VSS sg13_lv_nmos m=1 w=420.00n l=130.00n ng=1 +MN8 Q qint_b VSS VSS sg13_lv_nmos m=1 w=740.00n l=130.00n ng=1 +MN4 net7 Db VSS VSS sg13_lv_nmos m=1 w=740.00n l=130.00n ng=1 +MN6 net9 qint_b VSS VSS sg13_lv_nmos m=1 w=420.00n l=130.00n ng=1 +MN7 qint_b qint VSS VSS sg13_lv_nmos m=1 w=740.00n l=130.00n ng=1 +MN3 qint GATE_BB net7 VSS sg13_lv_nmos m=1 w=740.00n l=130.00n ng=1 +MN2 Db D VSS VSS sg13_lv_nmos m=1 w=550.00n l=130.00n ng=1 .ENDS ************************************************************************ @@ -442,30 +442,30 @@ MX0 Db D VSS VSS sg13_lv_nmos m=1 w=550.00n l=130.00n ng=1 .SUBCKT sg13g2_dlhr_1 Q Q_N D GATE RESET_B VDD VSS *.PININFO D:I GATE:I RESET_B:I Q:O Q_N:O VDD:B VSS:B -MX0 qint_b RESET_B VDD VDD sg13_lv_pmos m=1 w=1.12u l=130.00n ng=1 -MX9 Q qint_b VDD VDD sg13_lv_pmos m=1 w=1.12u l=130.00n ng=1 -MX15 qint GATE_BB net11 VDD sg13_lv_pmos m=1 w=420.00n l=130.00n ng=1 -MX6 net11 qint_b VDD VDD sg13_lv_pmos m=1 w=420.00n l=130.00n ng=1 -MX10 qint GATE_B net2 VDD sg13_lv_pmos m=1 w=1.000u l=130.00n ng=1 -MX18 net2 Db VDD VDD sg13_lv_pmos m=1 w=1.000u l=130.00n ng=1 -MX13 Db D VDD VDD sg13_lv_pmos m=1 w=840.00n l=130.00n ng=1 -MX5 GATE_B GATE VDD VDD sg13_lv_pmos m=1 w=840.00n l=130.00n ng=1 -MX3 Q_N qintn_b VDD VDD sg13_lv_pmos m=1 w=1.12u l=130.00n ng=1 -MX1 qint_b qint VDD VDD sg13_lv_pmos m=1 w=1.12u l=130.00n ng=1 -MX20 GATE_BB GATE_B VDD VDD sg13_lv_pmos m=1 w=840.00n l=130.00n ng=1 -MX2 qintn_b qint_b VDD VDD sg13_lv_pmos m=1 w=840.00n l=130.00n ng=1 -MX12 qint_b qint net9 VSS sg13_lv_nmos m=1 w=740.00n l=130.00n ng=1 -MX21 net9 RESET_B VSS VSS sg13_lv_nmos m=1 w=740.00n l=130.00n ng=1 -MX11 qint GATE_B net7 VSS sg13_lv_nmos m=1 w=420.00n l=130.00n ng=1 -MX14 net7 qint_b VSS VSS sg13_lv_nmos m=1 w=420.00n l=130.00n ng=1 -MX7 Q qint_b VSS VSS sg13_lv_nmos m=1 w=740.00n l=130.00n ng=1 -MX16 qint GATE_BB net1 VSS sg13_lv_nmos m=1 w=640.00n l=130.00n ng=1 -MX23 net1 Db VSS VSS sg13_lv_nmos m=1 w=640.00n l=130.00n ng=1 -MX4 Db D VSS VSS sg13_lv_nmos m=1 w=550.00n l=130.00n ng=1 -MX19 GATE_B GATE VSS VSS sg13_lv_nmos m=1 w=740.00n l=130.00n ng=1 -MX8 Q_N qintn_b VSS VSS sg13_lv_nmos m=1 w=740.00n l=130.00n ng=1 -MX17 GATE_BB GATE_B VSS VSS sg13_lv_nmos m=1 w=740.00n l=130.00n ng=1 -MX22 qintn_b qint_b VSS VSS sg13_lv_nmos m=1 w=550.00n l=130.00n ng=1 +MP8 qint_b RESET_B VDD VDD sg13_lv_pmos m=1 w=1.12u l=130.00n ng=1 +MP9 Q qint_b VDD VDD sg13_lv_pmos m=1 w=1.12u l=130.00n ng=1 +MP6 qint GATE_BB net11 VDD sg13_lv_pmos m=1 w=420.00n l=130.00n ng=1 +MP5 net11 qint_b VDD VDD sg13_lv_pmos m=1 w=420.00n l=130.00n ng=1 +MP4 qint GATE_B net2 VDD sg13_lv_pmos m=1 w=1.000u l=130.00n ng=1 +MP3 net2 Db VDD VDD sg13_lv_pmos m=1 w=1.000u l=130.00n ng=1 +MP2 Db D VDD VDD sg13_lv_pmos m=1 w=840.00n l=130.00n ng=1 +MP0 GATE_B GATE VDD VDD sg13_lv_pmos m=1 w=840.00n l=130.00n ng=1 +MP11 Q_N qintn_b VDD VDD sg13_lv_pmos m=1 w=1.12u l=130.00n ng=1 +MP7 qint_b qint VDD VDD sg13_lv_pmos m=1 w=1.12u l=130.00n ng=1 +MP1 GATE_BB GATE_B VDD VDD sg13_lv_pmos m=1 w=840.00n l=130.00n ng=1 +MP10 qintn_b qint_b VDD VDD sg13_lv_pmos m=1 w=840.00n l=130.00n ng=1 +MN7 qint_b qint net9 VSS sg13_lv_nmos m=1 w=740.00n l=130.00n ng=1 +MN8 net9 RESET_B VSS VSS sg13_lv_nmos m=1 w=740.00n l=130.00n ng=1 +MN5 qint GATE_B net7 VSS sg13_lv_nmos m=1 w=420.00n l=130.00n ng=1 +MN6 net7 qint_b VSS VSS sg13_lv_nmos m=1 w=420.00n l=130.00n ng=1 +MN9 Q qint_b VSS VSS sg13_lv_nmos m=1 w=740.00n l=130.00n ng=1 +MN3 qint GATE_BB net1 VSS sg13_lv_nmos m=1 w=640.00n l=130.00n ng=1 +MN4 net1 Db VSS VSS sg13_lv_nmos m=1 w=640.00n l=130.00n ng=1 +MN2 Db D VSS VSS sg13_lv_nmos m=1 w=550.00n l=130.00n ng=1 +MN0 GATE_B GATE VSS VSS sg13_lv_nmos m=1 w=740.00n l=130.00n ng=1 +MN11 Q_N qintn_b VSS VSS sg13_lv_nmos m=1 w=740.00n l=130.00n ng=1 +MN1 GATE_BB GATE_B VSS VSS sg13_lv_nmos m=1 w=740.00n l=130.00n ng=1 +MN10 qintn_b qint_b VSS VSS sg13_lv_nmos m=1 w=550.00n l=130.00n ng=1 .ENDS ************************************************************************ @@ -476,26 +476,26 @@ MX22 qintn_b qint_b VSS VSS sg13_lv_nmos m=1 w=550.00n l=130.00n ng=1 .SUBCKT sg13g2_dlhrq_1 Q D GATE RESET_B VDD VSS *.PININFO D:I GATE:I RESET_B:I Q:O VDD:B VSS:B -MX21 net116 RESET_B VSS VSS sg13_lv_nmos m=1 w=740.00n l=130.00n ng=1 -MX7 Q qint_b VSS VSS sg13_lv_nmos m=1 w=740.00n l=130.00n ng=1 -MX17 GATE_BB GATE_B VSS VSS sg13_lv_nmos m=1 w=740.00n l=130.00n ng=1 -MX11 qint GATE_B net89 VSS sg13_lv_nmos m=1 w=420.00n l=130.00n ng=1 -MX12 qint_b qint net116 VSS sg13_lv_nmos m=1 w=740.00n l=130.00n ng=1 -MX4 Db D VSS VSS sg13_lv_nmos m=1 w=550.00n l=130.00n ng=1 -MX23 net61 Db VSS VSS sg13_lv_nmos m=1 w=640.00n l=130.00n ng=1 -MX16 qint GATE_BB net61 VSS sg13_lv_nmos m=1 w=640.00n l=130.00n ng=1 -MX14 net89 qint_b VSS VSS sg13_lv_nmos m=1 w=420.00n l=130.00n ng=1 -MX19 GATE_B GATE VSS VSS sg13_lv_nmos m=1 w=740.00n l=130.00n ng=1 -MX18 net60 Db VDD VDD sg13_lv_pmos m=1 w=1.000u l=130.00n ng=1 -MX0 qint_b RESET_B VDD VDD sg13_lv_pmos m=1 w=1.000u l=130.00n ng=1 -MX15 qint GATE_BB net92 VDD sg13_lv_pmos m=1 w=420.00n l=130.00n ng=1 -MX9 Q qint_b VDD VDD sg13_lv_pmos m=1 w=1.12u l=130.00n ng=1 -MX6 net92 qint_b VDD VDD sg13_lv_pmos m=1 w=420.00n l=130.00n ng=1 -MX5 GATE_B GATE VDD VDD sg13_lv_pmos m=1 w=840.00n l=130.00n ng=1 -MX13 Db D VDD VDD sg13_lv_pmos m=1 w=840.00n l=130.00n ng=1 -MX10 qint GATE_B net60 VDD sg13_lv_pmos m=1 w=1.000u l=130.00n ng=1 -MX20 GATE_BB GATE_B VDD VDD sg13_lv_pmos m=1 w=840.00n l=130.00n ng=1 -MX1 qint_b qint VDD VDD sg13_lv_pmos m=1 w=1.000u l=130.00n ng=1 +MN8 net116 RESET_B VSS VSS sg13_lv_nmos m=1 w=740.00n l=130.00n ng=1 +MN9 Q qint_b VSS VSS sg13_lv_nmos m=1 w=740.00n l=130.00n ng=1 +MN1 GATE_BB GATE_B VSS VSS sg13_lv_nmos m=1 w=740.00n l=130.00n ng=1 +MN5 qint GATE_B net89 VSS sg13_lv_nmos m=1 w=420.00n l=130.00n ng=1 +MN7 qint_b qint net116 VSS sg13_lv_nmos m=1 w=740.00n l=130.00n ng=1 +MN2 Db D VSS VSS sg13_lv_nmos m=1 w=550.00n l=130.00n ng=1 +MN4 net61 Db VSS VSS sg13_lv_nmos m=1 w=640.00n l=130.00n ng=1 +MN3 qint GATE_BB net61 VSS sg13_lv_nmos m=1 w=640.00n l=130.00n ng=1 +MN6 net89 qint_b VSS VSS sg13_lv_nmos m=1 w=420.00n l=130.00n ng=1 +MN0 GATE_B GATE VSS VSS sg13_lv_nmos m=1 w=740.00n l=130.00n ng=1 +MP3 net60 Db VDD VDD sg13_lv_pmos m=1 w=1.000u l=130.00n ng=1 +MP8 qint_b RESET_B VDD VDD sg13_lv_pmos m=1 w=1.000u l=130.00n ng=1 +MP6 qint GATE_BB net92 VDD sg13_lv_pmos m=1 w=420.00n l=130.00n ng=1 +MP9 Q qint_b VDD VDD sg13_lv_pmos m=1 w=1.12u l=130.00n ng=1 +MP5 net92 qint_b VDD VDD sg13_lv_pmos m=1 w=420.00n l=130.00n ng=1 +MP0 GATE_B GATE VDD VDD sg13_lv_pmos m=1 w=840.00n l=130.00n ng=1 +MP2 Db D VDD VDD sg13_lv_pmos m=1 w=840.00n l=130.00n ng=1 +MP4 qint GATE_B net60 VDD sg13_lv_pmos m=1 w=1.000u l=130.00n ng=1 +MP1 GATE_BB GATE_B VDD VDD sg13_lv_pmos m=1 w=840.00n l=130.00n ng=1 +MP7 qint_b qint VDD VDD sg13_lv_pmos m=1 w=1.000u l=130.00n ng=1 .ENDS ************************************************************************ @@ -506,30 +506,30 @@ MX1 qint_b qint VDD VDD sg13_lv_pmos m=1 w=1.000u l=130.00n ng=1 .SUBCKT sg13g2_dllr_1 Q Q_N D GATE_N RESET_B VDD VSS *.PININFO D:I GATE_N:I RESET_B:I Q:O Q_N:O VDD:B VSS:B -MX4 Db D VSS VSS sg13_lv_nmos m=1 w=550.00n l=130.00n ng=1 -MX19 gnb GATE_N VSS VSS sg13_lv_nmos m=1 w=740.00n l=130.00n ng=1 -MX17 gnbb gnb VSS VSS sg13_lv_nmos m=1 w=740.00n l=130.00n ng=1 -MX14 net89 qint_b VSS VSS sg13_lv_nmos m=1 w=420.00n l=130.00n ng=1 -MX12 qint_b qint net116 VSS sg13_lv_nmos m=1 w=740.00n l=130.00n ng=1 -MX21 net116 RESET_B VSS VSS sg13_lv_nmos m=1 w=740.00n l=130.00n ng=1 -MX11 qint gnbb net89 VSS sg13_lv_nmos m=1 w=420.00n l=130.00n ng=1 -MX8 Q_N qintn_b VSS VSS sg13_lv_nmos m=1 w=740.00n l=130.00n ng=1 -MX16 qint gnb net61 VSS sg13_lv_nmos m=1 w=640.00n l=130.00n ng=1 -MX22 qintn_b qint_b VSS VSS sg13_lv_nmos m=1 w=550.00n l=130.00n ng=1 -MX23 net61 Db VSS VSS sg13_lv_nmos m=1 w=640.00n l=130.00n ng=1 -MX7 Q qint_b VSS VSS sg13_lv_nmos m=1 w=740.00n l=130.00n ng=1 -MX20 gnbb gnb VDD VDD sg13_lv_pmos m=1 w=840.00n l=130.00n ng=1 -MX10 qint gnbb net60 VDD sg13_lv_pmos m=1 w=1.000u l=130.00n ng=1 -MX2 qintn_b qint_b VDD VDD sg13_lv_pmos m=1 w=840.00n l=130.00n ng=1 -MX3 Q_N qintn_b VDD VDD sg13_lv_pmos m=1 w=1.12u l=130.00n ng=1 -MX18 net60 Db VDD VDD sg13_lv_pmos m=1 w=1.000u l=130.00n ng=1 -MX6 net92 qint_b VDD VDD sg13_lv_pmos m=1 w=420.00n l=130.00n ng=1 -MX0 qint_b RESET_B VDD VDD sg13_lv_pmos m=1 w=1.12u l=130.00n ng=1 -MX13 Db D VDD VDD sg13_lv_pmos m=1 w=840.00n l=130.00n ng=1 -MX5 gnb GATE_N VDD VDD sg13_lv_pmos m=1 w=840.00n l=130.00n ng=1 -MX9 Q qint_b VDD VDD sg13_lv_pmos m=1 w=1.12u l=130.00n ng=1 -MX15 qint gnb net92 VDD sg13_lv_pmos m=1 w=420.00n l=130.00n ng=1 -MX1 qint_b qint VDD VDD sg13_lv_pmos m=1 w=1.12u l=130.00n ng=1 +MN2 Db D VSS VSS sg13_lv_nmos m=1 w=550.00n l=130.00n ng=1 +MN0 gnb GATE_N VSS VSS sg13_lv_nmos m=1 w=740.00n l=130.00n ng=1 +MN1 gnbb gnb VSS VSS sg13_lv_nmos m=1 w=740.00n l=130.00n ng=1 +MN6 net89 qint_b VSS VSS sg13_lv_nmos m=1 w=420.00n l=130.00n ng=1 +MN7 qint_b qint net116 VSS sg13_lv_nmos m=1 w=740.00n l=130.00n ng=1 +MN8 net116 RESET_B VSS VSS sg13_lv_nmos m=1 w=740.00n l=130.00n ng=1 +MN5 qint gnbb net89 VSS sg13_lv_nmos m=1 w=420.00n l=130.00n ng=1 +MN11 Q_N qintn_b VSS VSS sg13_lv_nmos m=1 w=740.00n l=130.00n ng=1 +MN3 qint gnb net61 VSS sg13_lv_nmos m=1 w=640.00n l=130.00n ng=1 +MN10 qintn_b qint_b VSS VSS sg13_lv_nmos m=1 w=550.00n l=130.00n ng=1 +MN4 net61 Db VSS VSS sg13_lv_nmos m=1 w=640.00n l=130.00n ng=1 +MN9 Q qint_b VSS VSS sg13_lv_nmos m=1 w=740.00n l=130.00n ng=1 +MP1 gnbb gnb VDD VDD sg13_lv_pmos m=1 w=840.00n l=130.00n ng=1 +MP4 qint gnbb net60 VDD sg13_lv_pmos m=1 w=1.000u l=130.00n ng=1 +MP10 qintn_b qint_b VDD VDD sg13_lv_pmos m=1 w=840.00n l=130.00n ng=1 +MP11 Q_N qintn_b VDD VDD sg13_lv_pmos m=1 w=1.12u l=130.00n ng=1 +MP3 net60 Db VDD VDD sg13_lv_pmos m=1 w=1.000u l=130.00n ng=1 +MP5 net92 qint_b VDD VDD sg13_lv_pmos m=1 w=420.00n l=130.00n ng=1 +MP8 qint_b RESET_B VDD VDD sg13_lv_pmos m=1 w=1.12u l=130.00n ng=1 +MP2 Db D VDD VDD sg13_lv_pmos m=1 w=840.00n l=130.00n ng=1 +MP0 gnb GATE_N VDD VDD sg13_lv_pmos m=1 w=840.00n l=130.00n ng=1 +MP9 Q qint_b VDD VDD sg13_lv_pmos m=1 w=1.12u l=130.00n ng=1 +MP6 qint gnb net92 VDD sg13_lv_pmos m=1 w=420.00n l=130.00n ng=1 +MP7 qint_b qint VDD VDD sg13_lv_pmos m=1 w=1.12u l=130.00n ng=1 .ENDS ************************************************************************ @@ -540,26 +540,26 @@ MX1 qint_b qint VDD VDD sg13_lv_pmos m=1 w=1.12u l=130.00n ng=1 .SUBCKT sg13g2_dllrq_1 Q D GATE_N RESET_B VDD VSS *.PININFO D:I GATE_N:I RESET_B:I Q:O VDD:B VSS:B -MX11 qint gnbb net89 VSS sg13_lv_nmos m=1 w=420.00n l=130.00n ng=1 -MX16 qint gnb net61 VSS sg13_lv_nmos m=1 w=640.00n l=130.00n ng=1 -MX21 net116 RESET_B VSS VSS sg13_lv_nmos m=1 w=740.00n l=130.00n ng=1 -MX7 Q qint_b VSS VSS sg13_lv_nmos m=1 w=740.00n l=130.00n ng=1 -MX23 net61 Db VSS VSS sg13_lv_nmos m=1 w=640.00n l=130.00n ng=1 -MX14 net89 qint_b VSS VSS sg13_lv_nmos m=1 w=420.00n l=130.00n ng=1 -MX12 qint_b qint net116 VSS sg13_lv_nmos m=1 w=740.00n l=130.00n ng=1 -MX4 Db D VSS VSS sg13_lv_nmos m=1 w=550.00n l=130.00n ng=1 -MX19 gnb GATE_N VSS VSS sg13_lv_nmos m=1 w=740.00n l=130.00n ng=1 -MX17 gnbb gnb VSS VSS sg13_lv_nmos m=1 w=740.00n l=130.00n ng=1 -MX18 net59 Db VDD VDD sg13_lv_pmos m=1 w=1.000u l=130.00n ng=1 -MX0 qint_b RESET_B VDD VDD sg13_lv_pmos m=1 w=1.000u l=130.00n ng=1 -MX5 gnb GATE_N VDD VDD sg13_lv_pmos m=1 w=840.00n l=130.00n ng=1 -MX6 net92 qint_b VDD VDD sg13_lv_pmos m=1 w=420.00n l=130.00n ng=1 -MX1 qint_b qint VDD VDD sg13_lv_pmos m=1 w=1.000u l=130.00n ng=1 -MX9 Q qint_b VDD VDD sg13_lv_pmos m=1 w=1.12u l=130.00n ng=1 -MX10 qint gnbb net59 VDD sg13_lv_pmos m=1 w=1.000u l=130.00n ng=1 -MX13 Db D VDD VDD sg13_lv_pmos m=1 w=840.00n l=130.00n ng=1 -MX20 gnbb gnb VDD VDD sg13_lv_pmos m=1 w=840.00n l=130.00n ng=1 -MX15 qint gnb net92 VDD sg13_lv_pmos m=1 w=420.00n l=130.00n ng=1 +MN5 qint gnbb net89 VSS sg13_lv_nmos m=1 w=420.00n l=130.00n ng=1 +MN3 qint gnb net61 VSS sg13_lv_nmos m=1 w=640.00n l=130.00n ng=1 +MN8 net116 RESET_B VSS VSS sg13_lv_nmos m=1 w=740.00n l=130.00n ng=1 +MN9 Q qint_b VSS VSS sg13_lv_nmos m=1 w=740.00n l=130.00n ng=1 +MN4 net61 Db VSS VSS sg13_lv_nmos m=1 w=640.00n l=130.00n ng=1 +MN6 net89 qint_b VSS VSS sg13_lv_nmos m=1 w=420.00n l=130.00n ng=1 +MN7 qint_b qint net116 VSS sg13_lv_nmos m=1 w=740.00n l=130.00n ng=1 +MN2 Db D VSS VSS sg13_lv_nmos m=1 w=550.00n l=130.00n ng=1 +MN0 gnb GATE_N VSS VSS sg13_lv_nmos m=1 w=740.00n l=130.00n ng=1 +MN1 gnbb gnb VSS VSS sg13_lv_nmos m=1 w=740.00n l=130.00n ng=1 +MP3 net59 Db VDD VDD sg13_lv_pmos m=1 w=1.000u l=130.00n ng=1 +MP8 qint_b RESET_B VDD VDD sg13_lv_pmos m=1 w=1.000u l=130.00n ng=1 +MP0 gnb GATE_N VDD VDD sg13_lv_pmos m=1 w=840.00n l=130.00n ng=1 +MP5 net92 qint_b VDD VDD sg13_lv_pmos m=1 w=420.00n l=130.00n ng=1 +MP7 qint_b qint VDD VDD sg13_lv_pmos m=1 w=1.000u l=130.00n ng=1 +MP9 Q qint_b VDD VDD sg13_lv_pmos m=1 w=1.12u l=130.00n ng=1 +MP4 qint gnbb net59 VDD sg13_lv_pmos m=1 w=1.000u l=130.00n ng=1 +MP2 Db D VDD VDD sg13_lv_pmos m=1 w=840.00n l=130.00n ng=1 +MP1 gnbb gnb VDD VDD sg13_lv_pmos m=1 w=840.00n l=130.00n ng=1 +MP6 qint gnb net92 VDD sg13_lv_pmos m=1 w=420.00n l=130.00n ng=1 .ENDS ************************************************************************ @@ -628,8 +628,8 @@ MN3 net4 net3 VSS VSS sg13_lv_nmos m=1 w=1.48u l=130.00n ng=2 MN2 Z net1 net4 VSS sg13_lv_nmos m=1 w=1.48u l=130.00n ng=2 MN1 net3 TE_B VSS VSS sg13_lv_nmos m=1 w=640.00n l=130.00n ng=1 MN0 net1 A VSS VSS sg13_lv_nmos m=1 w=640.00n l=130.00n ng=1 -MP3 net2 TE_B VDD VDD sg13_lv_pmos m=1 w=2.24u l=130.00n ng=2 -MP2 Z net1 net2 VDD sg13_lv_pmos m=1 w=2.24u l=130.00n ng=2 +MP2 net2 TE_B VDD VDD sg13_lv_pmos m=1 w=2.24u l=130.00n ng=2 +MP3 Z net1 net2 VDD sg13_lv_pmos m=1 w=2.24u l=130.00n ng=2 MP1 net3 TE_B VDD VDD sg13_lv_pmos m=1 w=1.000u l=130.00n ng=1 MP0 net1 A VDD VDD sg13_lv_pmos m=1 w=1.000u l=130.00n ng=1 .ENDS @@ -648,8 +648,8 @@ MN2 Z net23 net22 VSS sg13_lv_nmos m=1 w=2.96u l=130.00n ng=4 MN3 net22 net21 VSS VSS sg13_lv_nmos m=1 w=2.96u l=130.00n ng=4 MP0 net23 A VDD VDD sg13_lv_pmos m=1 w=1.12u l=130.00n ng=1 MP1 net21 TE_B VDD VDD sg13_lv_pmos m=1 w=1.12u l=130.00n ng=1 -MP2 Z net23 net24 VDD sg13_lv_pmos m=1 w=4.48u l=130.00n ng=4 -MP3 net24 TE_B VDD VDD sg13_lv_pmos m=1 w=4.48u l=130.00n ng=4 +MP3 Z net23 net24 VDD sg13_lv_pmos m=1 w=4.48u l=130.00n ng=4 +MP2 net24 TE_B VDD VDD sg13_lv_pmos m=1 w=4.48u l=130.00n ng=4 .ENDS ************************************************************************ @@ -664,8 +664,8 @@ MN3 net23 net22 VSS VSS sg13_lv_nmos m=1 w=5.92u l=130.00n ng=8 MN2 Z net21 net23 VSS sg13_lv_nmos m=1 w=5.92u l=130.00n ng=8 MN1 net22 TE_B VSS VSS sg13_lv_nmos m=1 w=740.00n l=130.00n ng=1 MN0 net21 A VSS VSS sg13_lv_nmos m=1 w=1.48u l=130.00n ng=2 -MP3 net24 TE_B VDD VDD sg13_lv_pmos m=1 w=8.96u l=130.00n ng=8 -MP2 Z net21 net24 VDD sg13_lv_pmos m=1 w=8.96u l=130.00n ng=8 +MP2 net24 TE_B VDD VDD sg13_lv_pmos m=1 w=8.96u l=130.00n ng=8 +MP3 Z net21 net24 VDD sg13_lv_pmos m=1 w=8.96u l=130.00n ng=8 MP1 net22 TE_B VDD VDD sg13_lv_pmos m=1 w=1.12u l=130.00n ng=1 MP0 net21 A VDD VDD sg13_lv_pmos m=1 w=2.24u l=130.00n ng=2 .ENDS @@ -678,12 +678,12 @@ MP0 net21 A VDD VDD sg13_lv_pmos m=1 w=2.24u l=130.00n ng=2 .SUBCKT sg13g2_einvn_2 Z A TE_B VDD VSS *.PININFO A:I TE_B:I Z:O VDD:B VSS:B -MN2 TE TE_B VSS VSS sg13_lv_nmos m=1 w=420.00n l=130.00n ng=1 -MN1 net1 TE VSS VSS sg13_lv_nmos m=1 w=1.48u l=130.00n ng=2 -MN0 Z A net1 VSS sg13_lv_nmos m=1 w=1.48u l=130.00n ng=2 -MP2 TE TE_B VDD VDD sg13_lv_pmos m=1 w=640.00n l=130.00n ng=1 +MN0 TE TE_B VSS VSS sg13_lv_nmos m=1 w=420.00n l=130.00n ng=1 +MN2 net1 TE VSS VSS sg13_lv_nmos m=1 w=1.48u l=130.00n ng=2 +MN1 Z A net1 VSS sg13_lv_nmos m=1 w=1.48u l=130.00n ng=2 +MP0 TE TE_B VDD VDD sg13_lv_pmos m=1 w=640.00n l=130.00n ng=1 MP1 net2 TE_B VDD VDD sg13_lv_pmos m=1 w=2.24u l=130.00n ng=2 -MP0 Z A net2 VDD sg13_lv_pmos m=1 w=2.24u l=130.00n ng=2 +MP2 Z A net2 VDD sg13_lv_pmos m=1 w=2.24u l=130.00n ng=2 .ENDS ************************************************************************ @@ -694,12 +694,12 @@ MP0 Z A net2 VDD sg13_lv_pmos m=1 w=2.24u l=130.00n ng=2 .SUBCKT sg13g2_einvn_4 Z A TE_B VDD VSS *.PININFO A:I TE_B:I Z:O VDD:B VSS:B -MN1 net16 TE VSS VSS sg13_lv_nmos m=1 w=2.96u l=130.00n ng=4 -MN2 TE TE_B VSS VSS sg13_lv_nmos m=1 w=740.00n l=130.00n ng=1 -MN0 Z A net16 VSS sg13_lv_nmos m=1 w=2.96u l=130.00n ng=4 -MP2 TE TE_B VDD VDD sg13_lv_pmos m=1 w=1.12u l=130.00n ng=1 +MN2 net16 TE VSS VSS sg13_lv_nmos m=1 w=2.96u l=130.00n ng=4 +MN0 TE TE_B VSS VSS sg13_lv_nmos m=1 w=740.00n l=130.00n ng=1 +MN1 Z A net16 VSS sg13_lv_nmos m=1 w=2.96u l=130.00n ng=4 +MP0 TE TE_B VDD VDD sg13_lv_pmos m=1 w=1.12u l=130.00n ng=1 MP1 net17 TE_B VDD VDD sg13_lv_pmos m=1 w=4.48u l=130.00n ng=4 -MP0 Z A net17 VDD sg13_lv_pmos m=1 w=4.48u l=130.00n ng=4 +MP2 Z A net17 VDD sg13_lv_pmos m=1 w=4.48u l=130.00n ng=4 .ENDS ************************************************************************ @@ -710,12 +710,12 @@ MP0 Z A net17 VDD sg13_lv_pmos m=1 w=4.48u l=130.00n ng=4 .SUBCKT sg13g2_einvn_8 Z A TE_B VDD VSS *.PININFO A:I TE_B:I Z:O VDD:B VSS:B -MN0 Z A net29 VSS sg13_lv_nmos m=1 w=5.92u l=130.00n ng=8 -MN2 TE TE_B VSS VSS sg13_lv_nmos m=1 w=740.00n l=130.00n ng=1 -MN1 net29 TE VSS VSS sg13_lv_nmos m=1 w=5.92u l=130.00n ng=8 +MN1 Z A net29 VSS sg13_lv_nmos m=1 w=5.92u l=130.00n ng=8 +MN0 TE TE_B VSS VSS sg13_lv_nmos m=1 w=740.00n l=130.00n ng=1 +MN2 net29 TE VSS VSS sg13_lv_nmos m=1 w=5.92u l=130.00n ng=8 MP1 net28 TE_B VDD VDD sg13_lv_pmos m=1 w=8.96u l=130.00n ng=8 -MP0 Z A net28 VDD sg13_lv_pmos m=1 w=8.96u l=130.00n ng=8 -MP2 TE TE_B VDD VDD sg13_lv_pmos m=1 w=1.12u l=130.00n ng=1 +MP2 Z A net28 VDD sg13_lv_pmos m=1 w=8.96u l=130.00n ng=8 +MP0 TE TE_B VDD VDD sg13_lv_pmos m=1 w=1.12u l=130.00n ng=1 .ENDS ************************************************************************ @@ -726,8 +726,8 @@ MP2 TE TE_B VDD VDD sg13_lv_pmos m=1 w=1.12u l=130.00n ng=1 .SUBCKT sg13g2_inv_1 Y A VDD VSS *.PININFO A:I Y:O VDD:B VSS:B -MX1 Y A VSS VSS sg13_lv_nmos m=1 w=740.00n l=130.00n ng=1 -MX0 Y A VDD VDD sg13_lv_pmos m=1 w=1.12u l=130.00n ng=1 +MN0 Y A VSS VSS sg13_lv_nmos m=1 w=740.00n l=130.00n ng=1 +MP0 Y A VDD VDD sg13_lv_pmos m=1 w=1.12u l=130.00n ng=1 .ENDS ************************************************************************ @@ -738,8 +738,8 @@ MX0 Y A VDD VDD sg13_lv_pmos m=1 w=1.12u l=130.00n ng=1 .SUBCKT sg13g2_inv_16 Y A VDD VSS *.PININFO A:I Y:O VDD:B VSS:B -MX1 Y A VSS VSS sg13_lv_nmos m=1 w=11.84u l=130.00n ng=16 -MX0 Y A VDD VDD sg13_lv_pmos m=1 w=17.92u l=130.00n ng=16 +MN0 Y A VSS VSS sg13_lv_nmos m=1 w=11.84u l=130.00n ng=16 +MP0 Y A VDD VDD sg13_lv_pmos m=1 w=17.92u l=130.00n ng=16 .ENDS ************************************************************************ @@ -750,8 +750,8 @@ MX0 Y A VDD VDD sg13_lv_pmos m=1 w=17.92u l=130.00n ng=16 .SUBCKT sg13g2_inv_2 Y A VDD VSS *.PININFO A:I Y:O VDD:B VSS:B -MX1 Y A VSS VSS sg13_lv_nmos m=1 w=1.48u l=130.00n ng=2 -MX0 Y A VDD VDD sg13_lv_pmos m=1 w=2.24u l=130.00n ng=2 +MN0 Y A VSS VSS sg13_lv_nmos m=1 w=1.48u l=130.00n ng=2 +MP0 Y A VDD VDD sg13_lv_pmos m=1 w=2.24u l=130.00n ng=2 .ENDS ************************************************************************ @@ -774,8 +774,8 @@ MN0 Y A VSS VSS sg13_lv_nmos m=1 w=2.96u l=130.00n ng=4 .SUBCKT sg13g2_inv_8 Y A VDD VSS *.PININFO A:I Y:O VDD:B VSS:B -MX1 Y A VSS VSS sg13_lv_nmos m=1 w=5.92u l=130.00n ng=8 -MX0 Y A VDD VDD sg13_lv_pmos m=1 w=8.96u l=130.00n ng=8 +MN0 Y A VSS VSS sg13_lv_nmos m=1 w=5.92u l=130.00n ng=8 +MP0 Y A VDD VDD sg13_lv_pmos m=1 w=8.96u l=130.00n ng=8 .ENDS ************************************************************************ @@ -786,26 +786,26 @@ MX0 Y A VDD VDD sg13_lv_pmos m=1 w=8.96u l=130.00n ng=8 .SUBCKT sg13g2_lgcp_1 GCLK CLK GATE VDD VSS *.PININFO CLK:I GATE:I GCLK:O VDD:B VSS:B -MX15 CLKBB CLKB VDD VDD sg13_lv_pmos m=1 w=840.00n l=130.00n ng=1 -MX14 net1 CLKBB net4 VDD sg13_lv_pmos m=1 w=1.000u l=130.00n ng=1 -MX12 int_GATE net1 VDD VDD sg13_lv_pmos m=1 w=1.12u l=130.00n ng=1 -MX11 net4 GATE VDD VDD sg13_lv_pmos m=1 w=1.000u l=130.00n ng=1 -MX9 net3 int_GATE VDD VDD sg13_lv_pmos m=1 w=840.00n l=130.00n ng=1 -MX7 GCLK net3 VDD VDD sg13_lv_pmos m=1 w=1.12u l=130.00n ng=1 -MX5 net1 CLKB net6 VDD sg13_lv_pmos m=1 w=420.00n l=130.00n ng=1 -MX4 CLKB CLK VDD VDD sg13_lv_pmos m=1 w=840.00n l=130.00n ng=1 -MX3 net3 CLK VDD VDD sg13_lv_pmos m=1 w=840.00n l=130.00n ng=1 -MX2 net6 int_GATE VDD VDD sg13_lv_pmos m=1 w=420.00n l=130.00n ng=1 -MX19 GCLK net3 VSS VSS sg13_lv_nmos m=1 w=740.00n l=130.00n ng=1 -MX18 net3 int_GATE net5 VSS sg13_lv_nmos m=1 w=640.00n l=130.00n ng=1 -MX17 int_GATE net1 VSS VSS sg13_lv_nmos m=1 w=740.00n l=130.00n ng=1 -MX16 CLKBB CLKB VSS VSS sg13_lv_nmos m=1 w=740.00n l=130.00n ng=1 -MX13 net7 int_GATE VSS VSS sg13_lv_nmos m=1 w=420.00n l=130.00n ng=1 -MX10 net2 GATE VSS VSS sg13_lv_nmos m=1 w=640.00n l=130.00n ng=1 -MX8 net1 CLKBB net7 VSS sg13_lv_nmos m=1 w=420.00n l=130.00n ng=1 -MX6 CLKB CLK VSS VSS sg13_lv_nmos m=1 w=740.00n l=130.00n ng=1 -MX1 net5 CLK VSS VSS sg13_lv_nmos m=1 w=640.00n l=130.00n ng=1 -MX0 net1 CLKB net2 VSS sg13_lv_nmos m=1 w=640.00n l=130.00n ng=1 +MP1 CLKBB CLKB VDD VDD sg13_lv_pmos m=1 w=840.00n l=130.00n ng=1 +MP3 net1 CLKBB net4 VDD sg13_lv_pmos m=1 w=1.000u l=130.00n ng=1 +MP4 int_GATE net1 VDD VDD sg13_lv_pmos m=1 w=1.12u l=130.00n ng=1 +MP2 net4 GATE VDD VDD sg13_lv_pmos m=1 w=1.000u l=130.00n ng=1 +MP8 net3 int_GATE VDD VDD sg13_lv_pmos m=1 w=840.00n l=130.00n ng=1 +MP9 GCLK net3 VDD VDD sg13_lv_pmos m=1 w=1.12u l=130.00n ng=1 +MP6 net1 CLKB net6 VDD sg13_lv_pmos m=1 w=420.00n l=130.00n ng=1 +MP0 CLKB CLK VDD VDD sg13_lv_pmos m=1 w=840.00n l=130.00n ng=1 +MP7 net3 CLK VDD VDD sg13_lv_pmos m=1 w=840.00n l=130.00n ng=1 +MP5 net6 int_GATE VDD VDD sg13_lv_pmos m=1 w=420.00n l=130.00n ng=1 +MN9 GCLK net3 VSS VSS sg13_lv_nmos m=1 w=740.00n l=130.00n ng=1 +MN7 net3 int_GATE net5 VSS sg13_lv_nmos m=1 w=640.00n l=130.00n ng=1 +MN4 int_GATE net1 VSS VSS sg13_lv_nmos m=1 w=740.00n l=130.00n ng=1 +MN1 CLKBB CLKB VSS VSS sg13_lv_nmos m=1 w=740.00n l=130.00n ng=1 +MN6 net7 int_GATE VSS VSS sg13_lv_nmos m=1 w=420.00n l=130.00n ng=1 +MN3 net2 GATE VSS VSS sg13_lv_nmos m=1 w=640.00n l=130.00n ng=1 +MN5 net1 CLKBB net7 VSS sg13_lv_nmos m=1 w=420.00n l=130.00n ng=1 +MN0 CLKB CLK VSS VSS sg13_lv_nmos m=1 w=740.00n l=130.00n ng=1 +MN8 net5 CLK VSS VSS sg13_lv_nmos m=1 w=640.00n l=130.00n ng=1 +MN2 net1 CLKB net2 VSS sg13_lv_nmos m=1 w=640.00n l=130.00n ng=1 .ENDS ************************************************************************ @@ -816,18 +816,18 @@ MX0 net1 CLKB net2 VSS sg13_lv_nmos m=1 w=640.00n l=130.00n ng=1 .SUBCKT sg13g2_mux2_1 X A0 A1 S VDD VSS *.PININFO A0:I A1:I S:I X:O VDD:B VSS:B -MP0 net4 S VDD VDD sg13_lv_pmos m=1 w=1.000u l=130.00n ng=1 -MP4 X net6 VDD VDD sg13_lv_pmos m=1 w=1.12u l=130.00n ng=1 -MP3 net6 A1 net5 VDD sg13_lv_pmos m=1 w=1.000u l=130.00n ng=1 -MP5 Sb S VDD VDD sg13_lv_pmos m=1 w=840.00n l=130.00n ng=1 -MP2 net5 Sb VDD VDD sg13_lv_pmos m=1 w=1.000u l=130.00n ng=1 -MP1 net6 A0 net4 VDD sg13_lv_pmos m=1 w=1.000u l=130.00n ng=1 +MP1 net4 S VDD VDD sg13_lv_pmos m=1 w=1.000u l=130.00n ng=1 +MP5 X net6 VDD VDD sg13_lv_pmos m=1 w=1.12u l=130.00n ng=1 +MP4 net6 A1 net5 VDD sg13_lv_pmos m=1 w=1.000u l=130.00n ng=1 +MP0 Sb S VDD VDD sg13_lv_pmos m=1 w=840.00n l=130.00n ng=1 +MP3 net5 Sb VDD VDD sg13_lv_pmos m=1 w=1.000u l=130.00n ng=1 +MP2 net6 A0 net4 VDD sg13_lv_pmos m=1 w=1.000u l=130.00n ng=1 MN4 net3 S VSS VSS sg13_lv_nmos m=1 w=740.00n l=130.00n ng=1 -MN1 net1 Sb VSS VSS sg13_lv_nmos m=1 w=740.00n l=130.00n ng=1 -MN6 X net6 VSS VSS sg13_lv_nmos m=1 w=740.00n l=130.00n ng=1 -MN5 Sb S VSS VSS sg13_lv_nmos m=1 w=550.00n l=130.00n ng=1 -MN2 net6 A1 net3 VSS sg13_lv_nmos m=1 w=740.00n l=130.00n ng=1 -MN0 net6 A0 net1 VSS sg13_lv_nmos m=1 w=740.00n l=130.00n ng=1 +MN2 net1 Sb VSS VSS sg13_lv_nmos m=1 w=740.00n l=130.00n ng=1 +MN5 X net6 VSS VSS sg13_lv_nmos m=1 w=740.00n l=130.00n ng=1 +MN0 Sb S VSS VSS sg13_lv_nmos m=1 w=550.00n l=130.00n ng=1 +MN3 net6 A1 net3 VSS sg13_lv_nmos m=1 w=740.00n l=130.00n ng=1 +MN1 net6 A0 net1 VSS sg13_lv_nmos m=1 w=740.00n l=130.00n ng=1 .ENDS ************************************************************************ @@ -838,18 +838,18 @@ MN0 net6 A0 net1 VSS sg13_lv_nmos m=1 w=740.00n l=130.00n ng=1 .SUBCKT sg13g2_mux2_2 X A0 A1 S VDD VSS *.PININFO A0:I A1:I S:I X:O VDD:B VSS:B -MP0 net4 S VDD VDD sg13_lv_pmos m=1 w=1.000u l=130.00n ng=1 -MP4 X net6 VDD VDD sg13_lv_pmos m=1 w=2.24u l=130.00n ng=2 -MP3 net6 A1 net5 VDD sg13_lv_pmos m=1 w=1.000u l=130.00n ng=1 -MP5 Sb S VDD VDD sg13_lv_pmos m=1 w=840.00n l=130.00n ng=1 -MP2 net5 Sb VDD VDD sg13_lv_pmos m=1 w=1.000u l=130.00n ng=1 -MP1 net6 A0 net4 VDD sg13_lv_pmos m=1 w=1.000u l=130.00n ng=1 +MP1 net4 S VDD VDD sg13_lv_pmos m=1 w=1.000u l=130.00n ng=1 +MP5 X net6 VDD VDD sg13_lv_pmos m=1 w=2.24u l=130.00n ng=2 +MP4 net6 A1 net5 VDD sg13_lv_pmos m=1 w=1.000u l=130.00n ng=1 +MP0 Sb S VDD VDD sg13_lv_pmos m=1 w=840.00n l=130.00n ng=1 +MP3 net5 Sb VDD VDD sg13_lv_pmos m=1 w=1.000u l=130.00n ng=1 +MP2 net6 A0 net4 VDD sg13_lv_pmos m=1 w=1.000u l=130.00n ng=1 MN4 net3 S VSS VSS sg13_lv_nmos m=1 w=740.00n l=130.00n ng=1 -MN1 net1 Sb VSS VSS sg13_lv_nmos m=1 w=740.00n l=130.00n ng=1 -MN6 X net6 VSS VSS sg13_lv_nmos m=1 w=1.48u l=130.00n ng=2 -MN5 Sb S VSS VSS sg13_lv_nmos m=1 w=550.00n l=130.00n ng=1 -MN2 net6 A1 net3 VSS sg13_lv_nmos m=1 w=740.00n l=130.00n ng=1 -MN0 net6 A0 net1 VSS sg13_lv_nmos m=1 w=740.00n l=130.00n ng=1 +MN2 net1 Sb VSS VSS sg13_lv_nmos m=1 w=740.00n l=130.00n ng=1 +MN5 X net6 VSS VSS sg13_lv_nmos m=1 w=1.48u l=130.00n ng=2 +MN0 Sb S VSS VSS sg13_lv_nmos m=1 w=550.00n l=130.00n ng=1 +MN3 net6 A1 net3 VSS sg13_lv_nmos m=1 w=740.00n l=130.00n ng=1 +MN1 net6 A0 net1 VSS sg13_lv_nmos m=1 w=740.00n l=130.00n ng=1 .ENDS ************************************************************************ @@ -861,31 +861,31 @@ MN0 net6 A0 net1 VSS sg13_lv_nmos m=1 w=740.00n l=130.00n ng=1 .SUBCKT sg13g2_mux4_1 X A0 A1 A2 A3 S0 S1 VDD VSS *.PININFO A0:I A1:I A2:I A3:I S0:I S1:I X:O VDD:B VSS:B MN12 X Xb VSS VSS sg13_lv_nmos m=1 w=740.00n l=130.00n ng=1 -MN18 low S0b net7 VSS sg13_lv_nmos m=1 w=640.00n l=130.00n ng=1 -MN17 net7 A0 VSS VSS sg13_lv_nmos m=1 w=640.00n l=130.00n ng=1 -MN19 low S1b Xb VSS sg13_lv_nmos m=1 w=640.00n l=130.00n ng=1 -MN10 high S1 Xb VSS sg13_lv_nmos m=1 w=640.00n l=130.00n ng=1 -MN9 net4 A3 VSS VSS sg13_lv_nmos m=1 w=640.00n l=130.00n ng=1 -MN8 high S0 net4 VSS sg13_lv_nmos m=1 w=640.00n l=130.00n ng=1 -MN14 net6 A2 VSS VSS sg13_lv_nmos m=1 w=640.00n l=130.00n ng=1 -MN13 high S0b net6 VSS sg13_lv_nmos m=1 w=640.00n l=130.00n ng=1 -MN16 net2 A1 VSS VSS sg13_lv_nmos m=1 w=640.00n l=130.00n ng=1 -MN15 low S0 net2 VSS sg13_lv_nmos m=1 w=640.00n l=130.00n ng=1 +MN2 low S0b net7 VSS sg13_lv_nmos m=1 w=640.00n l=130.00n ng=1 +MN3 net7 A0 VSS VSS sg13_lv_nmos m=1 w=640.00n l=130.00n ng=1 +MN6 low S1b Xb VSS sg13_lv_nmos m=1 w=640.00n l=130.00n ng=1 +MN11 high S1 Xb VSS sg13_lv_nmos m=1 w=640.00n l=130.00n ng=1 +MN10 net4 A3 VSS VSS sg13_lv_nmos m=1 w=640.00n l=130.00n ng=1 +MN9 high S0 net4 VSS sg13_lv_nmos m=1 w=640.00n l=130.00n ng=1 +MN8 net6 A2 VSS VSS sg13_lv_nmos m=1 w=640.00n l=130.00n ng=1 +MN7 high S0b net6 VSS sg13_lv_nmos m=1 w=640.00n l=130.00n ng=1 +MN5 net2 A1 VSS VSS sg13_lv_nmos m=1 w=640.00n l=130.00n ng=1 +MN4 low S0 net2 VSS sg13_lv_nmos m=1 w=640.00n l=130.00n ng=1 MN1 S1b S1 VSS VSS sg13_lv_nmos m=1 w=640.00n l=130.00n ng=1 MN0 S0b S0 VSS VSS sg13_lv_nmos m=1 w=640.00n l=130.00n ng=1 -MP19 low S1 Xb VDD sg13_lv_pmos m=1 w=1.000u l=130.00n ng=1 +MP6 low S1 Xb VDD sg13_lv_pmos m=1 w=1.000u l=130.00n ng=1 MP11 high S1b Xb VDD sg13_lv_pmos m=1 w=1.000u l=130.00n ng=1 -MP10 X Xb VDD VDD sg13_lv_pmos m=1 w=1.12u l=130.00n ng=1 -MP9 high S0b net3 VDD sg13_lv_pmos m=1 w=1.000u l=130.00n ng=1 -MP8 net3 A3 VDD VDD sg13_lv_pmos m=1 w=1.000u l=130.00n ng=1 -MP14 high S0 net5 VDD sg13_lv_pmos m=1 w=1.000u l=130.00n ng=1 -MP13 net5 A2 VDD VDD sg13_lv_pmos m=1 w=1.000u l=130.00n ng=1 -MP18 net8 A0 VDD VDD sg13_lv_pmos m=1 w=1.000u l=130.00n ng=1 -MP17 low S0 net8 VDD sg13_lv_pmos m=1 w=1.000u l=130.00n ng=1 +MP12 X Xb VDD VDD sg13_lv_pmos m=1 w=1.12u l=130.00n ng=1 +MP10 high S0b net3 VDD sg13_lv_pmos m=1 w=1.000u l=130.00n ng=1 +MP9 net3 A3 VDD VDD sg13_lv_pmos m=1 w=1.000u l=130.00n ng=1 +MP8 high S0 net5 VDD sg13_lv_pmos m=1 w=1.000u l=130.00n ng=1 +MP7 net5 A2 VDD VDD sg13_lv_pmos m=1 w=1.000u l=130.00n ng=1 +MP2 net8 A0 VDD VDD sg13_lv_pmos m=1 w=1.000u l=130.00n ng=1 +MP3 low S0 net8 VDD sg13_lv_pmos m=1 w=1.000u l=130.00n ng=1 MP1 S1b S1 VDD VDD sg13_lv_pmos m=1 w=1.000u l=130.00n ng=1 MP0 S0b S0 VDD VDD sg13_lv_pmos m=1 w=1.000u l=130.00n ng=1 -MP16 low S0b net1 VDD sg13_lv_pmos m=1 w=1.000u l=130.00n ng=1 -MP15 net1 A1 VDD VDD sg13_lv_pmos m=1 w=1.000u l=130.00n ng=1 +MP5 low S0b net1 VDD sg13_lv_pmos m=1 w=1.000u l=130.00n ng=1 +MP4 net1 A1 VDD VDD sg13_lv_pmos m=1 w=1.000u l=130.00n ng=1 .ENDS ************************************************************************ @@ -924,12 +924,12 @@ MN0 Y A net1 VSS sg13_lv_nmos m=1 w=1.44u l=130.00n ng=2 .SUBCKT sg13g2_nand2b_1 Y A_N B VDD VSS *.PININFO A_N:I B:I Y:O VDD:B VSS:B -MX0 Y net2 VDD VDD sg13_lv_pmos m=1 w=1.12u l=130.00n ng=1 -MX1 net2 A_N VDD VDD sg13_lv_pmos m=1 w=840.00n l=130.00n ng=1 -MX3 Y B VDD VDD sg13_lv_pmos m=1 w=1.12u l=130.00n ng=1 -MX2 Y net2 net1 VSS sg13_lv_nmos m=1 w=740.00n l=130.00n ng=1 -MX4 net2 A_N VSS VSS sg13_lv_nmos m=1 w=550.00n l=130.00n ng=1 -MX5 net1 B VSS VSS sg13_lv_nmos m=1 w=740.00n l=130.00n ng=1 +MP2 Y net2 VDD VDD sg13_lv_pmos m=1 w=1.12u l=130.00n ng=1 +MP1 net2 A_N VDD VDD sg13_lv_pmos m=1 w=840.00n l=130.00n ng=1 +MP0 Y B VDD VDD sg13_lv_pmos m=1 w=1.12u l=130.00n ng=1 +MN1 Y net2 net1 VSS sg13_lv_nmos m=1 w=740.00n l=130.00n ng=1 +MN0 net2 A_N VSS VSS sg13_lv_nmos m=1 w=550.00n l=130.00n ng=1 +MN2 net1 B VSS VSS sg13_lv_nmos m=1 w=740.00n l=130.00n ng=1 .ENDS ************************************************************************ @@ -940,12 +940,12 @@ MX5 net1 B VSS VSS sg13_lv_nmos m=1 w=740.00n l=130.00n ng=1 .SUBCKT sg13g2_nand2b_2 Y A_N B VDD VSS *.PININFO A_N:I B:I Y:O VDD:B VSS:B -MX0 Y A VDD VDD sg13_lv_pmos m=1 w=2.24u l=130.00n ng=2 -MX1 A A_N VDD VDD sg13_lv_pmos m=1 w=840.00n l=130.00n ng=1 -MX3 Y B VDD VDD sg13_lv_pmos m=1 w=2.24u l=130.00n ng=2 -MX2 Y B net1 VSS sg13_lv_nmos m=1 w=1.44u l=130.00n ng=2 -MX4 A A_N VSS VSS sg13_lv_nmos m=1 w=550.00n l=130.00n ng=1 -MX5 net1 A VSS VSS sg13_lv_nmos m=1 w=1.44u l=130.00n ng=2 +MP2 Y A VDD VDD sg13_lv_pmos m=1 w=2.24u l=130.00n ng=2 +MP0 A A_N VDD VDD sg13_lv_pmos m=1 w=840.00n l=130.00n ng=1 +MP1 Y B VDD VDD sg13_lv_pmos m=1 w=2.24u l=130.00n ng=2 +MN1 Y B net1 VSS sg13_lv_nmos m=1 w=1.44u l=130.00n ng=2 +MN0 A A_N VSS VSS sg13_lv_nmos m=1 w=550.00n l=130.00n ng=1 +MN2 net1 A VSS VSS sg13_lv_nmos m=1 w=1.44u l=130.00n ng=2 .ENDS ************************************************************************ @@ -956,12 +956,12 @@ MX5 net1 A VSS VSS sg13_lv_nmos m=1 w=1.44u l=130.00n ng=2 .SUBCKT sg13g2_nand3_1 Y A B C VDD VSS *.PININFO A:I B:I C:I Y:O VDD:B VSS:B -MX1 Y A VDD VDD sg13_lv_pmos m=1 w=1.12u l=130.00n ng=1 -MX2 Y B VDD VDD sg13_lv_pmos m=1 w=1.12u l=130.00n ng=1 -MX6 Y C VDD VDD sg13_lv_pmos m=1 w=1.12u l=130.00n ng=1 -MX3 net2 B net3 VSS sg13_lv_nmos m=1 w=740.00n l=130.00n ng=1 -MX4 net3 C VSS VSS sg13_lv_nmos m=1 w=740.00n l=130.00n ng=1 -MX7 Y A net2 VSS sg13_lv_nmos m=1 w=740.00n l=130.00n ng=1 +MP0 Y A VDD VDD sg13_lv_pmos m=1 w=1.12u l=130.00n ng=1 +MP1 Y B VDD VDD sg13_lv_pmos m=1 w=1.12u l=130.00n ng=1 +MP2 Y C VDD VDD sg13_lv_pmos m=1 w=1.12u l=130.00n ng=1 +MN1 net2 B net3 VSS sg13_lv_nmos m=1 w=740.00n l=130.00n ng=1 +MN2 net3 C VSS VSS sg13_lv_nmos m=1 w=740.00n l=130.00n ng=1 +MN0 Y A net2 VSS sg13_lv_nmos m=1 w=740.00n l=130.00n ng=1 .ENDS ************************************************************************ @@ -972,14 +972,14 @@ MX7 Y A net2 VSS sg13_lv_nmos m=1 w=740.00n l=130.00n ng=1 .SUBCKT sg13g2_nand3b_1 Y A_N B C VDD VSS *.PININFO A_N:I B:I C:I Y:O VDD:B VSS:B -MX0 net1 A_N VDD VDD sg13_lv_pmos m=1 w=840.00n l=130.00n ng=1 -MX1 Y net1 VDD VDD sg13_lv_pmos m=1 w=1.12u l=130.00n ng=1 -MX2 Y B VDD VDD sg13_lv_pmos m=1 w=1.12u l=130.00n ng=1 -MX6 Y C VDD VDD sg13_lv_pmos m=1 w=1.12u l=130.00n ng=1 -MX3 net2 B net3 VSS sg13_lv_nmos m=1 w=740.00n l=130.00n ng=1 -MX4 net3 C VSS VSS sg13_lv_nmos m=1 w=740.00n l=130.00n ng=1 -MX5 net1 A_N VSS VSS sg13_lv_nmos m=1 w=550.00n l=130.00n ng=1 -MX7 Y net1 net2 VSS sg13_lv_nmos m=1 w=740.00n l=130.00n ng=1 +MP0 net1 A_N VDD VDD sg13_lv_pmos m=1 w=840.00n l=130.00n ng=1 +MP1 Y net1 VDD VDD sg13_lv_pmos m=1 w=1.12u l=130.00n ng=1 +MP2 Y B VDD VDD sg13_lv_pmos m=1 w=1.12u l=130.00n ng=1 +MP3 Y C VDD VDD sg13_lv_pmos m=1 w=1.12u l=130.00n ng=1 +MN2 net2 B net3 VSS sg13_lv_nmos m=1 w=740.00n l=130.00n ng=1 +MN3 net3 C VSS VSS sg13_lv_nmos m=1 w=740.00n l=130.00n ng=1 +MN0 net1 A_N VSS VSS sg13_lv_nmos m=1 w=550.00n l=130.00n ng=1 +MN1 Y net1 net2 VSS sg13_lv_nmos m=1 w=740.00n l=130.00n ng=1 .ENDS ************************************************************************ @@ -990,14 +990,14 @@ MX7 Y net1 net2 VSS sg13_lv_nmos m=1 w=740.00n l=130.00n ng=1 .SUBCKT sg13g2_nand4_1 Y A B C D VDD VSS *.PININFO A:I B:I C:I D:I Y:O VDD:B VSS:B -MP0 Y D VDD VDD sg13_lv_pmos m=1 w=1.12u l=130.00n ng=1 -MX1 Y A VDD VDD sg13_lv_pmos m=1 w=1.12u l=130.00n ng=1 -MX2 Y B VDD VDD sg13_lv_pmos m=1 w=1.12u l=130.00n ng=1 -MX6 Y C VDD VDD sg13_lv_pmos m=1 w=1.12u l=130.00n ng=1 -MX3 net2 B net3 VSS sg13_lv_nmos m=1 w=740.00n l=130.00n ng=1 -MX4 net3 C net5 VSS sg13_lv_nmos m=1 w=740.00n l=130.00n ng=1 -MX7 Y A net2 VSS sg13_lv_nmos m=1 w=740.00n l=130.00n ng=1 -MN0 net5 D VSS VSS sg13_lv_nmos m=1 w=740.00n l=130.00n ng=1 +MP3 Y D VDD VDD sg13_lv_pmos m=1 w=1.12u l=130.00n ng=1 +MP0 Y A VDD VDD sg13_lv_pmos m=1 w=1.12u l=130.00n ng=1 +MP1 Y B VDD VDD sg13_lv_pmos m=1 w=1.12u l=130.00n ng=1 +MP2 Y C VDD VDD sg13_lv_pmos m=1 w=1.12u l=130.00n ng=1 +MN1 net2 B net3 VSS sg13_lv_nmos m=1 w=740.00n l=130.00n ng=1 +MN2 net3 C net5 VSS sg13_lv_nmos m=1 w=740.00n l=130.00n ng=1 +MN0 Y A net2 VSS sg13_lv_nmos m=1 w=740.00n l=130.00n ng=1 +MN3 net5 D VSS VSS sg13_lv_nmos m=1 w=740.00n l=130.00n ng=1 .ENDS ************************************************************************ @@ -1008,10 +1008,10 @@ MN0 net5 D VSS VSS sg13_lv_nmos m=1 w=740.00n l=130.00n ng=1 .SUBCKT sg13g2_nor2_1 Y A B VDD VSS *.PININFO A:I B:I Y:O VDD:B VSS:B -MX0 Y A VSS VSS sg13_lv_nmos m=1 w=740.00n l=130.00n ng=1 -MX3 Y B VSS VSS sg13_lv_nmos m=1 w=740.00n l=130.00n ng=1 -MX1 net1 A VDD VDD sg13_lv_pmos m=1 w=1.12u l=130.00n ng=1 -MX2 Y B net1 VDD sg13_lv_pmos m=1 w=1.12u l=130.00n ng=1 +MN0 Y A VSS VSS sg13_lv_nmos m=1 w=740.00n l=130.00n ng=1 +MN1 Y B VSS VSS sg13_lv_nmos m=1 w=740.00n l=130.00n ng=1 +MP0 net1 A VDD VDD sg13_lv_pmos m=1 w=1.12u l=130.00n ng=1 +MP1 Y B net1 VDD sg13_lv_pmos m=1 w=1.12u l=130.00n ng=1 .ENDS ************************************************************************ @@ -1022,10 +1022,10 @@ MX2 Y B net1 VDD sg13_lv_pmos m=1 w=1.12u l=130.00n ng=1 .SUBCKT sg13g2_nor2_2 Y A B VDD VSS *.PININFO A:I B:I Y:O VDD:B VSS:B -MX0 Y A VSS VSS sg13_lv_nmos m=1 w=1.48u l=130.00n ng=2 -MX3 Y B VSS VSS sg13_lv_nmos m=1 w=1.48u l=130.00n ng=2 -MX1 net1 A VDD VDD sg13_lv_pmos m=1 w=2.24u l=130.00n ng=2 -MX2 Y B net1 VDD sg13_lv_pmos m=1 w=2.24u l=130.00n ng=2 +MN0 Y A VSS VSS sg13_lv_nmos m=1 w=1.48u l=130.00n ng=2 +MN1 Y B VSS VSS sg13_lv_nmos m=1 w=1.48u l=130.00n ng=2 +MP0 net1 A VDD VDD sg13_lv_pmos m=1 w=2.24u l=130.00n ng=2 +MP1 Y B net1 VDD sg13_lv_pmos m=1 w=2.24u l=130.00n ng=2 .ENDS ************************************************************************ @@ -1037,11 +1037,11 @@ MX2 Y B net1 VDD sg13_lv_pmos m=1 w=2.24u l=130.00n ng=2 .SUBCKT sg13g2_nor2b_1 Y A B_N VDD VSS *.PININFO A:I B_N:I Y:O VDD:B VSS:B MN0 B B_N VSS VSS sg13_lv_nmos m=1 w=550.00n l=130.00n ng=1 -MX0 Y A VSS VSS sg13_lv_nmos m=1 w=740.00n l=130.00n ng=1 -MX3 Y B VSS VSS sg13_lv_nmos m=1 w=740.00n l=130.00n ng=1 +MN1 Y A VSS VSS sg13_lv_nmos m=1 w=740.00n l=130.00n ng=1 +MN2 Y B VSS VSS sg13_lv_nmos m=1 w=740.00n l=130.00n ng=1 MP0 B B_N VDD VDD sg13_lv_pmos m=1 w=840.00n l=130.00n ng=1 -MX1 net1 B VDD VDD sg13_lv_pmos m=1 w=1.12e-06 l=130.00n ng=1 -MX2 Y A net1 VDD sg13_lv_pmos m=1 w=1.12e-06 l=130.00n ng=1 +MP1 net1 B VDD VDD sg13_lv_pmos m=1 w=1.12u l=130.00n ng=1 +MP2 Y A net1 VDD sg13_lv_pmos m=1 w=1.12u l=130.00n ng=1 .ENDS ************************************************************************ @@ -1053,11 +1053,11 @@ MX2 Y A net1 VDD sg13_lv_pmos m=1 w=1.12e-06 l=130.00n ng=1 .SUBCKT sg13g2_nor2b_2 Y A B_N VDD VSS *.PININFO A:I B_N:I Y:O VDD:B VSS:B MN0 B B_N VSS VSS sg13_lv_nmos m=1 w=640.00n l=130.00n ng=1 -MX0 Y A VSS VSS sg13_lv_nmos m=1 w=1.44u l=130.00n ng=2 -MX3 Y B VSS VSS sg13_lv_nmos m=1 w=1.44u l=130.00n ng=2 +MN1 Y A VSS VSS sg13_lv_nmos m=1 w=1.44u l=130.00n ng=2 +MN2 Y B VSS VSS sg13_lv_nmos m=1 w=1.44u l=130.00n ng=2 MP0 B B_N VDD VDD sg13_lv_pmos m=1 w=1.000u l=130.00n ng=1 -MX1 net1 B VDD VDD sg13_lv_pmos m=1 w=2.24u l=130.00n ng=2 -MX2 Y A net1 VDD sg13_lv_pmos m=1 w=2.24u l=130.00n ng=2 +MP1 net1 B VDD VDD sg13_lv_pmos m=1 w=2.24u l=130.00n ng=2 +MP2 Y A net1 VDD sg13_lv_pmos m=1 w=2.24u l=130.00n ng=2 .ENDS ************************************************************************ @@ -1068,12 +1068,12 @@ MX2 Y A net1 VDD sg13_lv_pmos m=1 w=2.24u l=130.00n ng=2 .SUBCKT sg13g2_nor3_1 Y A B C VDD VSS *.PININFO A:I B:I C:I Y:O VDD:B VSS:B -MX3 Y C net2 VDD sg13_lv_pmos m=1 w=1.12u l=130.00n ng=1 -MX0 net2 B net3 VDD sg13_lv_pmos m=1 w=1.12u l=130.00n ng=1 -MX2 net3 A VDD VDD sg13_lv_pmos m=1 w=1.12u l=130.00n ng=1 -MX4 Y A VSS VSS sg13_lv_nmos m=1 w=770.00n l=130.00n ng=1 -MX1 Y B VSS VSS sg13_lv_nmos m=1 w=770.00n l=130.00n ng=1 -MX5 Y C VSS VSS sg13_lv_nmos m=1 w=770.00n l=130.00n ng=1 +MP2 Y C net2 VDD sg13_lv_pmos m=1 w=1.12u l=130.00n ng=1 +MP1 net2 B net3 VDD sg13_lv_pmos m=1 w=1.12u l=130.00n ng=1 +MP0 net3 A VDD VDD sg13_lv_pmos m=1 w=1.12u l=130.00n ng=1 +MN0 Y A VSS VSS sg13_lv_nmos m=1 w=770.00n l=130.00n ng=1 +MN1 Y B VSS VSS sg13_lv_nmos m=1 w=770.00n l=130.00n ng=1 +MN2 Y C VSS VSS sg13_lv_nmos m=1 w=770.00n l=130.00n ng=1 .ENDS ************************************************************************ @@ -1084,12 +1084,12 @@ MX5 Y C VSS VSS sg13_lv_nmos m=1 w=770.00n l=130.00n ng=1 .SUBCKT sg13g2_nor3_2 Y A B C VDD VSS *.PININFO A:I B:I C:I Y:O VDD:B VSS:B -MX3 Y C net2 VDD sg13_lv_pmos m=1 w=2.24u l=130.00n ng=2 -MX0 net2 B net3 VDD sg13_lv_pmos m=1 w=2.24u l=130.00n ng=2 -MX2 net3 A VDD VDD sg13_lv_pmos m=1 w=2.24u l=130.00n ng=2 -MX4 Y A VSS VSS sg13_lv_nmos m=1 w=1.48u l=130.00n ng=2 -MX1 Y B VSS VSS sg13_lv_nmos m=1 w=1.48u l=130.00n ng=2 -MX5 Y C VSS VSS sg13_lv_nmos m=1 w=1.48u l=130.00n ng=2 +MP2 Y C net2 VDD sg13_lv_pmos m=1 w=2.24u l=130.00n ng=2 +MP1 net2 B net3 VDD sg13_lv_pmos m=1 w=2.24u l=130.00n ng=2 +MP0 net3 A VDD VDD sg13_lv_pmos m=1 w=2.24u l=130.00n ng=2 +MN0 Y A VSS VSS sg13_lv_nmos m=1 w=1.48u l=130.00n ng=2 +MN1 Y B VSS VSS sg13_lv_nmos m=1 w=1.48u l=130.00n ng=2 +MN2 Y C VSS VSS sg13_lv_nmos m=1 w=1.48u l=130.00n ng=2 .ENDS ************************************************************************ @@ -1100,14 +1100,14 @@ MX5 Y C VSS VSS sg13_lv_nmos m=1 w=1.48u l=130.00n ng=2 .SUBCKT sg13g2_nor4_1 Y A B C D VDD VSS *.PININFO A:I B:I C:I D:I Y:O VDD:B VSS:B -MX0 net3 A VDD VDD sg13_lv_pmos m=1 w=1.12u l=130.00n ng=1 -MX5 net2 B net3 VDD sg13_lv_pmos m=1 w=1.12u l=130.00n ng=1 -MX6 net1 C net2 VDD sg13_lv_pmos m=1 w=1.12u l=130.00n ng=1 -MX7 Y D net1 VDD sg13_lv_pmos m=1 w=1.12u l=130.00n ng=1 -MX1 Y A VSS VSS sg13_lv_nmos m=1 w=740.00n l=130.00n ng=1 -MX2 Y D VSS VSS sg13_lv_nmos m=1 w=740.00n l=130.00n ng=1 -MX3 Y B VSS VSS sg13_lv_nmos m=1 w=740.00n l=130.00n ng=1 -MX4 Y C VSS VSS sg13_lv_nmos m=1 w=740.00n l=130.00n ng=1 +MP0 net3 A VDD VDD sg13_lv_pmos m=1 w=1.12u l=130.00n ng=1 +MP1 net2 B net3 VDD sg13_lv_pmos m=1 w=1.12u l=130.00n ng=1 +MP2 net1 C net2 VDD sg13_lv_pmos m=1 w=1.12u l=130.00n ng=1 +MP3 Y D net1 VDD sg13_lv_pmos m=1 w=1.12u l=130.00n ng=1 +MN0 Y A VSS VSS sg13_lv_nmos m=1 w=740.00n l=130.00n ng=1 +MN3 Y D VSS VSS sg13_lv_nmos m=1 w=740.00n l=130.00n ng=1 +MN1 Y B VSS VSS sg13_lv_nmos m=1 w=740.00n l=130.00n ng=1 +MN2 Y C VSS VSS sg13_lv_nmos m=1 w=740.00n l=130.00n ng=1 .ENDS ************************************************************************ @@ -1118,14 +1118,14 @@ MX4 Y C VSS VSS sg13_lv_nmos m=1 w=740.00n l=130.00n ng=1 .SUBCKT sg13g2_nor4_2 Y A B C D VDD VSS *.PININFO A:I B:I C:I D:I Y:O VDD:B VSS:B -MX0 net3 A VDD VDD sg13_lv_pmos m=1 w=2.24u l=130.00n ng=2 -MX5 net2 B net3 VDD sg13_lv_pmos m=1 w=2.24u l=130.00n ng=2 -MX6 net1 C net2 VDD sg13_lv_pmos m=1 w=2.24u l=130.00n ng=2 -MX7 Y D net1 VDD sg13_lv_pmos m=1 w=2.24u l=130.00n ng=2 -MX1 Y A VSS VSS sg13_lv_nmos m=1 w=1.48u l=130.00n ng=2 -MX2 Y D VSS VSS sg13_lv_nmos m=1 w=1.48u l=130.00n ng=2 -MX3 Y B VSS VSS sg13_lv_nmos m=1 w=1.48u l=130.00n ng=2 -MX4 Y C VSS VSS sg13_lv_nmos m=1 w=1.48u l=130.00n ng=2 +MP0 net3 A VDD VDD sg13_lv_pmos m=1 w=2.24u l=130.00n ng=2 +MP1 net2 B net3 VDD sg13_lv_pmos m=1 w=2.24u l=130.00n ng=2 +MP2 net1 C net2 VDD sg13_lv_pmos m=1 w=2.24u l=130.00n ng=2 +MP3 Y D net1 VDD sg13_lv_pmos m=1 w=2.24u l=130.00n ng=2 +MN0 Y A VSS VSS sg13_lv_nmos m=1 w=1.48u l=130.00n ng=2 +MN3 Y D VSS VSS sg13_lv_nmos m=1 w=1.48u l=130.00n ng=2 +MN1 Y B VSS VSS sg13_lv_nmos m=1 w=1.48u l=130.00n ng=2 +MN2 Y C VSS VSS sg13_lv_nmos m=1 w=1.48u l=130.00n ng=2 .ENDS ************************************************************************ @@ -1136,12 +1136,12 @@ MX4 Y C VSS VSS sg13_lv_nmos m=1 w=1.48u l=130.00n ng=2 .SUBCKT sg13g2_o21ai_1 Y A1 A2 B1 VDD VSS *.PININFO A1:I A2:I B1:I Y:O VDD:B VSS:B -MP2 net14 A1 VDD VDD sg13_lv_pmos m=1 w=1.12u l=150.00n ng=1 +MP0 net14 A1 VDD VDD sg13_lv_pmos m=1 w=1.12u l=150.00n ng=1 MP1 Y A2 net14 VDD sg13_lv_pmos m=1 w=1.12u l=150.00n ng=1 -MP0 Y B1 VDD VDD sg13_lv_pmos m=1 w=1.12u l=150.00n ng=1 -MN2 net1 A2 VSS VSS sg13_lv_nmos m=1 w=740.00n l=150.00n ng=1 -MN3 net1 A1 VSS VSS sg13_lv_nmos m=1 w=740.00n l=150.00n ng=1 -MN0 Y B1 net1 VSS sg13_lv_nmos m=1 w=740.00n l=150.00n ng=1 +MP2 Y B1 VDD VDD sg13_lv_pmos m=1 w=1.12u l=150.00n ng=1 +MN0 net1 A2 VSS VSS sg13_lv_nmos m=1 w=740.00n l=150.00n ng=1 +MN2 net1 A1 VSS VSS sg13_lv_nmos m=1 w=740.00n l=150.00n ng=1 +MN1 Y B1 net1 VSS sg13_lv_nmos m=1 w=740.00n l=150.00n ng=1 .ENDS ************************************************************************ @@ -1152,11 +1152,11 @@ MN0 Y B1 net1 VSS sg13_lv_nmos m=1 w=740.00n l=150.00n ng=1 .SUBCKT sg13g2_or2_1 X A B VDD VSS *.PININFO A:I B:I X:O VDD:B VSS:B -MP0 net2 B net3 VDD sg13_lv_pmos m=1 w=840.00n l=130.00n ng=1 -MP1 net3 A VDD VDD sg13_lv_pmos m=1 w=840.00n l=130.00n ng=1 +MP1 net2 B net3 VDD sg13_lv_pmos m=1 w=840.00n l=130.00n ng=1 +MP0 net3 A VDD VDD sg13_lv_pmos m=1 w=840.00n l=130.00n ng=1 MP2 X net2 VDD VDD sg13_lv_pmos m=1 w=1.12u l=130.00n ng=1 -MN0 net2 A VSS VSS sg13_lv_nmos m=1 w=550.00n l=130.00n ng=1 -MN1 net2 B VSS VSS sg13_lv_nmos m=1 w=550.00n l=130.00n ng=1 +MN1 net2 A VSS VSS sg13_lv_nmos m=1 w=550.00n l=130.00n ng=1 +MN0 net2 B VSS VSS sg13_lv_nmos m=1 w=550.00n l=130.00n ng=1 MN2 X net2 VSS VSS sg13_lv_nmos m=1 w=740.00n l=130.00n ng=1 .ENDS @@ -1168,11 +1168,11 @@ MN2 X net2 VSS VSS sg13_lv_nmos m=1 w=740.00n l=130.00n ng=1 .SUBCKT sg13g2_or2_2 X A B VDD VSS *.PININFO A:I B:I X:O VDD:B VSS:B -MP0 net2 B net3 VDD sg13_lv_pmos m=1 w=840.00n l=130.00n ng=1 -MP1 net3 A VDD VDD sg13_lv_pmos m=1 w=840.00n l=130.00n ng=1 +MP1 net2 B net3 VDD sg13_lv_pmos m=1 w=840.00n l=130.00n ng=1 +MP0 net3 A VDD VDD sg13_lv_pmos m=1 w=840.00n l=130.00n ng=1 MP2 X net2 VDD VDD sg13_lv_pmos m=1 w=2.24u l=130.00n ng=2 -MN0 net2 A VSS VSS sg13_lv_nmos m=1 w=550.00n l=130.00n ng=1 -MN1 net2 B VSS VSS sg13_lv_nmos m=1 w=550.00n l=130.00n ng=1 +MN1 net2 A VSS VSS sg13_lv_nmos m=1 w=550.00n l=130.00n ng=1 +MN0 net2 B VSS VSS sg13_lv_nmos m=1 w=550.00n l=130.00n ng=1 MN2 X net2 VSS VSS sg13_lv_nmos m=1 w=1.48u l=130.00n ng=2 .ENDS @@ -1184,14 +1184,14 @@ MN2 X net2 VSS VSS sg13_lv_nmos m=1 w=1.48u l=130.00n ng=2 .SUBCKT sg13g2_or3_1 X A B C VDD VSS *.PININFO A:I B:I C:I X:O VDD:B VSS:B -MX0 net1 C VSS VSS sg13_lv_nmos m=1 w=550.00n l=130.00n ng=1 -MX1 X net1 VSS VSS sg13_lv_nmos m=1 w=740.00n l=130.00n ng=1 -MX6 net1 B VSS VSS sg13_lv_nmos m=1 w=550.00n l=130.00n ng=1 -MX7 net1 A VSS VSS sg13_lv_nmos m=1 w=550.00n l=130.00n ng=1 -MX2 X net1 VDD VDD sg13_lv_pmos m=1 w=1.12e-06 l=130.00n ng=1 -MX3 net9 B net12 VDD sg13_lv_pmos m=1 w=1.000u l=130.00n ng=1 -MX4 net12 A VDD VDD sg13_lv_pmos m=1 w=1.000u l=130.00n ng=1 -MX5 net1 C net9 VDD sg13_lv_pmos m=1 w=1.000u l=130.00n ng=1 +MN2 net1 C VSS VSS sg13_lv_nmos m=1 w=550.00n l=130.00n ng=1 +MN3 X net1 VSS VSS sg13_lv_nmos m=1 w=740.00n l=130.00n ng=1 +MN1 net1 B VSS VSS sg13_lv_nmos m=1 w=550.00n l=130.00n ng=1 +MN0 net1 A VSS VSS sg13_lv_nmos m=1 w=550.00n l=130.00n ng=1 +MP3 X net1 VDD VDD sg13_lv_pmos m=1 w=1.12u l=130.00n ng=1 +MP1 net9 B net12 VDD sg13_lv_pmos m=1 w=1.000u l=130.00n ng=1 +MP0 net12 A VDD VDD sg13_lv_pmos m=1 w=1.000u l=130.00n ng=1 +MP2 net1 C net9 VDD sg13_lv_pmos m=1 w=1.000u l=130.00n ng=1 .ENDS ************************************************************************ @@ -1202,14 +1202,14 @@ MX5 net1 C net9 VDD sg13_lv_pmos m=1 w=1.000u l=130.00n ng=1 .SUBCKT sg13g2_or3_2 X A B C VDD VSS *.PININFO A:I B:I C:I X:O VDD:B VSS:B -MX0 net1 C VSS VSS sg13_lv_nmos m=1 w=550.00n l=130.00n ng=1 -MX1 X net1 VSS VSS sg13_lv_nmos m=1 w=1.48u l=130.00n ng=2 -MX6 net1 B VSS VSS sg13_lv_nmos m=1 w=550.00n l=130.00n ng=1 -MX7 net1 A VSS VSS sg13_lv_nmos m=1 w=550.00n l=130.00n ng=1 -MX2 X net1 VDD VDD sg13_lv_pmos m=1 w=2.24u l=130.00n ng=2 -MX3 net9 B net12 VDD sg13_lv_pmos m=1 w=1.000u l=130.00n ng=1 -MX4 net12 A VDD VDD sg13_lv_pmos m=1 w=1.000u l=130.00n ng=1 -MX5 net1 C net9 VDD sg13_lv_pmos m=1 w=1.000u l=130.00n ng=1 +MN2 net1 C VSS VSS sg13_lv_nmos m=1 w=550.00n l=130.00n ng=1 +MN3 X net1 VSS VSS sg13_lv_nmos m=1 w=1.48u l=130.00n ng=2 +MN1 net1 B VSS VSS sg13_lv_nmos m=1 w=550.00n l=130.00n ng=1 +MN0 net1 A VSS VSS sg13_lv_nmos m=1 w=550.00n l=130.00n ng=1 +MP3 X net1 VDD VDD sg13_lv_pmos m=1 w=2.24u l=130.00n ng=2 +MP1 net9 B net12 VDD sg13_lv_pmos m=1 w=1.000u l=130.00n ng=1 +MP0 net12 A VDD VDD sg13_lv_pmos m=1 w=1.000u l=130.00n ng=1 +MP2 net1 C net9 VDD sg13_lv_pmos m=1 w=1.000u l=130.00n ng=1 .ENDS ************************************************************************ @@ -1225,11 +1225,11 @@ MN3 net1 D VSS VSS sg13_lv_nmos m=1 w=550.00n l=130.00n ng=1 MN2 net1 C VSS VSS sg13_lv_nmos m=1 w=550.00n l=130.00n ng=1 MN1 net1 B VSS VSS sg13_lv_nmos m=1 w=550.00n l=130.00n ng=1 MN0 net1 A VSS VSS sg13_lv_nmos m=1 w=550.00n l=130.00n ng=1 -MP4 net4 A VDD VDD sg13_lv_pmos m=1 w=1.000u l=130.00n ng=1 -MP3 net3 B net4 VDD sg13_lv_pmos m=1 w=1.000u l=130.00n ng=1 +MP0 net4 A VDD VDD sg13_lv_pmos m=1 w=1.000u l=130.00n ng=1 +MP1 net3 B net4 VDD sg13_lv_pmos m=1 w=1.000u l=130.00n ng=1 MP2 net2 C net3 VDD sg13_lv_pmos m=1 w=1.000u l=130.00n ng=1 -MP1 net1 D net2 VDD sg13_lv_pmos m=1 w=1.000u l=130.00n ng=1 -MP0 X net1 VDD VDD sg13_lv_pmos m=1 w=1.12u l=130.00n ng=1 +MP3 net1 D net2 VDD sg13_lv_pmos m=1 w=1.000u l=130.00n ng=1 +MP4 X net1 VDD VDD sg13_lv_pmos m=1 w=1.12u l=130.00n ng=1 .ENDS ************************************************************************ @@ -1245,11 +1245,11 @@ MN3 net1 D VSS VSS sg13_lv_nmos m=1 w=550.00n l=130.00n ng=1 MN2 net1 C VSS VSS sg13_lv_nmos m=1 w=550.00n l=130.00n ng=1 MN1 net1 B VSS VSS sg13_lv_nmos m=1 w=550.00n l=130.00n ng=1 MN0 net1 A VSS VSS sg13_lv_nmos m=1 w=550.00n l=130.00n ng=1 -MP4 net4 A VDD VDD sg13_lv_pmos m=1 w=1.000u l=130.00n ng=1 -MP3 net3 B net4 VDD sg13_lv_pmos m=1 w=1.000u l=130.00n ng=1 +MP0 net4 A VDD VDD sg13_lv_pmos m=1 w=1.000u l=130.00n ng=1 +MP1 net3 B net4 VDD sg13_lv_pmos m=1 w=1.000u l=130.00n ng=1 MP2 net2 C net3 VDD sg13_lv_pmos m=1 w=1.000u l=130.00n ng=1 -MP1 net1 D net2 VDD sg13_lv_pmos m=1 w=1.000u l=130.00n ng=1 -MP0 X net1 VDD VDD sg13_lv_pmos m=1 w=2.24u l=130.00n ng=2 +MP3 net1 D net2 VDD sg13_lv_pmos m=1 w=1.000u l=130.00n ng=1 +MP4 X net1 VDD VDD sg13_lv_pmos m=1 w=2.24u l=130.00n ng=2 .ENDS ************************************************************************ @@ -1260,54 +1260,54 @@ MP0 X net1 VDD VDD sg13_lv_pmos m=1 w=2.24u l=130.00n ng=2 .SUBCKT sg13g2_sdfbbp_1 Q Q_N CLK D RESET_B SCD SCE SET_B VDD VSS *.PININFO CLK:I D:I RESET_B:I SCD:I SCE:I SET_B:I Q:O Q_N:O VDD:B VSS:B -MX46 resetbb RESET_B VDD VDD sg13_lv_pmos m=1 w=640.00n l=130.00n ng=1 -MX45 pre_q DbbLatch2 net8 VDD sg13_lv_pmos m=1 w=1.000u l=130.00n ng=1 -MX44 pre_q SET_B VDD VDD sg13_lv_pmos m=1 w=1.000u l=130.00n ng=1 -MX41 CLKbb CLKb VDD VDD sg13_lv_pmos m=1 w=1.12u l=130.00n ng=1 -MX39 SCEb SCE VDD VDD sg13_lv_pmos m=1 w=640.00n l=130.00n ng=1 -MX38 Db D net3 VDD sg13_lv_pmos m=1 w=640.00n l=130.00n ng=1 -MX33 DbbTG CLKb net10 VDD sg13_lv_pmos m=1 w=420.00n l=130.00n ng=1 -MX28 net10 DbLatchM VDD VDD sg13_lv_pmos m=1 w=420.00n l=130.00n ng=1 -MX27 net3 SCE VDD VDD sg13_lv_pmos m=1 w=640.00n l=130.00n ng=1 -MX26 Q_N pre_q VDD VDD sg13_lv_pmos m=1 w=1.12u l=130.00n ng=1 -MX24 net1 DbLatchM VDD VDD sg13_lv_pmos m=1 w=840.00n l=130.00n ng=1 -MX19 net8 resetbb VDD VDD sg13_lv_pmos m=1 w=1.000u l=130.00n ng=1 -MX17 DbLatchM SET_B VDD VDD sg13_lv_pmos m=1 w=840.00n l=130.00n ng=1 -MX16 net2 SCD VDD VDD sg13_lv_pmos m=1 w=640.00n l=130.00n ng=1 -MX15 CLKb CLK VDD VDD sg13_lv_pmos m=1 w=1.12u l=130.00n ng=1 -MX14 DbLatchM DbbTG net7 VDD sg13_lv_pmos m=1 w=840.00n l=130.00n ng=1 -MX11 Db CLKbb DbbTG VDD sg13_lv_pmos m=1 w=640.00n l=130.00n ng=1 -MX9 Db SCEb net2 VDD sg13_lv_pmos m=1 w=640.00n l=130.00n ng=1 -MX8 pre_qb pre_q VDD VDD sg13_lv_pmos m=1 w=840.00n l=130.00n ng=1 -MX7 net7 resetbb VDD VDD sg13_lv_pmos m=1 w=840.00n l=130.00n ng=1 -MX6 net6 pre_q VDD VDD sg13_lv_pmos m=1 w=420.00n l=130.00n ng=1 -MX5 DbbLatch2 CLKbb net6 VDD sg13_lv_pmos m=1 w=420.00n l=130.00n ng=1 -MX4 DbbLatch2 CLKb net1 VDD sg13_lv_pmos m=1 w=840.00n l=130.00n ng=1 -MX3 Q pre_qb VDD VDD sg13_lv_pmos m=1 w=1.12u l=130.00n ng=1 -MN1 Db SCE net5 VSS sg13_lv_nmos m=1 w=420.00n l=130.00n ng=1 -MN0 net5 SCD VSS VSS sg13_lv_nmos m=1 w=420.00n l=130.00n ng=1 -MX47 pre_q DbbLatch2 net11 VSS sg13_lv_nmos m=1 w=740.00n l=130.00n ng=1 -MX43 Db CLKb DbbTG VSS sg13_lv_nmos m=1 w=420.00n l=130.00n ng=1 -MX42 net4 SCEb VSS VSS sg13_lv_nmos m=1 w=420.00n l=130.00n ng=1 -MX40 CLKbb CLKb VSS VSS sg13_lv_nmos m=1 w=740.00n l=130.00n ng=1 -MX37 resetbb RESET_B VSS VSS sg13_lv_nmos m=1 w=420.00n l=130.00n ng=1 -MX36 net14 pre_q VSS VSS sg13_lv_nmos m=1 w=420.00n l=130.00n ng=1 -MX35 DbLatchM DbbTG net12 VSS sg13_lv_nmos m=1 w=550.00n l=130.00n ng=1 -MX34 SCEb SCE VSS VSS sg13_lv_nmos m=1 w=420.00n l=130.00n ng=1 -MX32 net12 SET_B VSS VSS sg13_lv_nmos m=1 w=550.00n l=130.00n ng=1 -MX31 net15 DbLatchM VSS VSS sg13_lv_nmos m=1 w=420.00n l=130.00n ng=1 -MX29 net11 SET_B VSS VSS sg13_lv_nmos m=1 w=740.00n l=130.00n ng=1 -MX25 DbbTG CLKbb net15 VSS sg13_lv_nmos m=1 w=420.00n l=130.00n ng=1 -MX23 Db D net4 VSS sg13_lv_nmos m=1 w=420.00n l=130.00n ng=1 -MX22 pre_qb pre_q VSS VSS sg13_lv_nmos m=1 w=550.00n l=130.00n ng=1 -MX21 DbbLatch2 CLKb net14 VSS sg13_lv_nmos m=1 w=420.00n l=130.00n ng=1 -MX20 Q pre_qb VSS VSS sg13_lv_nmos m=1 w=740.00n l=130.00n ng=1 -MX18 net13 DbLatchM VSS VSS sg13_lv_nmos m=1 w=550.00n l=130.00n ng=1 -MX13 CLKb CLK VSS VSS sg13_lv_nmos m=1 w=740.00n l=130.00n ng=1 -MX10 DbbLatch2 CLKbb net13 VSS sg13_lv_nmos m=1 w=550.00n l=130.00n ng=1 -MX2 DbLatchM resetbb net12 VSS sg13_lv_nmos m=1 w=550.00n l=130.00n ng=1 -MX1 Q_N pre_q VSS VSS sg13_lv_nmos m=1 w=740.00n l=130.00n ng=1 -MX0 pre_q resetbb net11 VSS sg13_lv_nmos m=1 w=740.00n l=130.00n ng=1 +MP1 resetbb RESET_B VDD VDD sg13_lv_pmos m=1 w=640.00n l=130.00n ng=1 +MP19 pre_q DbbLatch2 net8 VDD sg13_lv_pmos m=1 w=1.000u l=130.00n ng=1 +MP20 pre_q SET_B VDD VDD sg13_lv_pmos m=1 w=1.000u l=130.00n ng=1 +MP3 CLKbb CLKb VDD VDD sg13_lv_pmos m=1 w=1.12u l=130.00n ng=1 +MP0 SCEb SCE VDD VDD sg13_lv_pmos m=1 w=640.00n l=130.00n ng=1 +MP7 Db D net3 VDD sg13_lv_pmos m=1 w=640.00n l=130.00n ng=1 +MP13 DbbTG CLKb net10 VDD sg13_lv_pmos m=1 w=420.00n l=130.00n ng=1 +MP12 net10 DbLatchM VDD VDD sg13_lv_pmos m=1 w=420.00n l=130.00n ng=1 +MP6 net3 SCE VDD VDD sg13_lv_pmos m=1 w=640.00n l=130.00n ng=1 +MP21 Q_N pre_q VDD VDD sg13_lv_pmos m=1 w=1.12u l=130.00n ng=1 +MP14 net1 DbLatchM VDD VDD sg13_lv_pmos m=1 w=840.00n l=130.00n ng=1 +MP18 net8 resetbb VDD VDD sg13_lv_pmos m=1 w=1.000u l=130.00n ng=1 +MP11 DbLatchM SET_B VDD VDD sg13_lv_pmos m=1 w=840.00n l=130.00n ng=1 +MP4 net2 SCD VDD VDD sg13_lv_pmos m=1 w=640.00n l=130.00n ng=1 +MP2 CLKb CLK VDD VDD sg13_lv_pmos m=1 w=1.12u l=130.00n ng=1 +MP10 DbLatchM DbbTG net7 VDD sg13_lv_pmos m=1 w=840.00n l=130.00n ng=1 +MP8 Db CLKbb DbbTG VDD sg13_lv_pmos m=1 w=640.00n l=130.00n ng=1 +MP5 Db SCEb net2 VDD sg13_lv_pmos m=1 w=640.00n l=130.00n ng=1 +MP22 pre_qb pre_q VDD VDD sg13_lv_pmos m=1 w=840.00n l=130.00n ng=1 +MP9 net7 resetbb VDD VDD sg13_lv_pmos m=1 w=840.00n l=130.00n ng=1 +MP16 net6 pre_q VDD VDD sg13_lv_pmos m=1 w=420.00n l=130.00n ng=1 +MP17 DbbLatch2 CLKbb net6 VDD sg13_lv_pmos m=1 w=420.00n l=130.00n ng=1 +MP15 DbbLatch2 CLKb net1 VDD sg13_lv_pmos m=1 w=840.00n l=130.00n ng=1 +MP23 Q pre_qb VDD VDD sg13_lv_pmos m=1 w=1.12u l=130.00n ng=1 +MN4 Db SCE net5 VSS sg13_lv_nmos m=1 w=420.00n l=130.00n ng=1 +MN5 net5 SCD VSS VSS sg13_lv_nmos m=1 w=420.00n l=130.00n ng=1 +MN18 pre_q DbbLatch2 net11 VSS sg13_lv_nmos m=1 w=740.00n l=130.00n ng=1 +MN8 Db CLKb DbbTG VSS sg13_lv_nmos m=1 w=420.00n l=130.00n ng=1 +MN7 net4 SCEb VSS VSS sg13_lv_nmos m=1 w=420.00n l=130.00n ng=1 +MN3 CLKbb CLKb VSS VSS sg13_lv_nmos m=1 w=740.00n l=130.00n ng=1 +MN1 resetbb RESET_B VSS VSS sg13_lv_nmos m=1 w=420.00n l=130.00n ng=1 +MN17 net14 pre_q VSS VSS sg13_lv_nmos m=1 w=420.00n l=130.00n ng=1 +MN9 DbLatchM DbbTG net12 VSS sg13_lv_nmos m=1 w=550.00n l=130.00n ng=1 +MN0 SCEb SCE VSS VSS sg13_lv_nmos m=1 w=420.00n l=130.00n ng=1 +MN10 net12 SET_B VSS VSS sg13_lv_nmos m=1 w=550.00n l=130.00n ng=1 +MN13 net15 DbLatchM VSS VSS sg13_lv_nmos m=1 w=420.00n l=130.00n ng=1 +MN19 net11 SET_B VSS VSS sg13_lv_nmos m=1 w=740.00n l=130.00n ng=1 +MN12 DbbTG CLKbb net15 VSS sg13_lv_nmos m=1 w=420.00n l=130.00n ng=1 +MN6 Db D net4 VSS sg13_lv_nmos m=1 w=420.00n l=130.00n ng=1 +MN22 pre_qb pre_q VSS VSS sg13_lv_nmos m=1 w=550.00n l=130.00n ng=1 +MN16 DbbLatch2 CLKb net14 VSS sg13_lv_nmos m=1 w=420.00n l=130.00n ng=1 +MN23 Q pre_qb VSS VSS sg13_lv_nmos m=1 w=740.00n l=130.00n ng=1 +MN15 net13 DbLatchM VSS VSS sg13_lv_nmos m=1 w=550.00n l=130.00n ng=1 +MN2 CLKb CLK VSS VSS sg13_lv_nmos m=1 w=740.00n l=130.00n ng=1 +MN14 DbbLatch2 CLKbb net13 VSS sg13_lv_nmos m=1 w=550.00n l=130.00n ng=1 +MN11 DbLatchM resetbb net12 VSS sg13_lv_nmos m=1 w=550.00n l=130.00n ng=1 +MN21 Q_N pre_q VSS VSS sg13_lv_nmos m=1 w=740.00n l=130.00n ng=1 +MN20 pre_q resetbb net11 VSS sg13_lv_nmos m=1 w=740.00n l=130.00n ng=1 .ENDS ************************************************************************ @@ -1318,10 +1318,10 @@ MX0 pre_q resetbb net11 VSS sg13_lv_nmos m=1 w=740.00n l=130.00n ng=1 .SUBCKT sg13g2_sighold SH VDD VSS *.PININFO SH:B VDD:B VSS:B -MN0 net1 SH VSS VSS sg13_lv_nmos m=1 w=300.0n l=130.00n ng=1 -MN1 SH net1 VSS VSS sg13_lv_nmos m=1 w=300.0n l=700.0n ng=1 -MP0 net1 SH VDD VDD sg13_lv_pmos m=1 w=450.00n l=130.00n ng=1 -MP1 SH net1 VDD VDD sg13_lv_pmos m=1 w=300.0n l=700.0n ng=1 +MN1 net1 SH VSS VSS sg13_lv_nmos m=1 w=300.0n l=130.00n ng=1 +MN0 SH net1 VSS VSS sg13_lv_nmos m=1 w=300.0n l=700.0n ng=1 +MP1 net1 SH VDD VDD sg13_lv_pmos m=1 w=450.00n l=130.00n ng=1 +MP0 SH net1 VDD VDD sg13_lv_pmos m=1 w=300.0n l=700.0n ng=1 .ENDS ************************************************************************ @@ -1332,28 +1332,28 @@ MP1 SH net1 VDD VDD sg13_lv_pmos m=1 w=300.0n l=700.0n ng=1 .SUBCKT sg13g2_slgcp_1 GCLK CLK GATE SCE VDD VSS *.PININFO CLK:I GATE:I SCE:I GCLK:O VDD:B VSS:B -MX19 GCLK net5 VDD VDD sg13_lv_pmos m=1 w=1.12u l=130.00n ng=1 -MX18 net1 CLKbb net6 VDD sg13_lv_pmos m=1 w=840.00n l=130.00n ng=1 -MX16 CLKbb CLKb VDD VDD sg13_lv_pmos m=1 w=840.00n l=130.00n ng=1 -MX14 net5 int_GATE VDD VDD sg13_lv_pmos m=1 w=840.00n l=130.00n ng=1 -MX13 net3 SCE VDD VDD sg13_lv_pmos m=1 w=840.00n l=130.00n ng=1 -MX11 net6 CLKb net4 VDD sg13_lv_pmos m=1 w=420.00n l=130.00n ng=1 -MX9 int_GATE net6 VDD VDD sg13_lv_pmos m=1 w=1.12u l=130.00n ng=1 -MX7 CLKb CLK VDD VDD sg13_lv_pmos m=1 w=840.00n l=130.00n ng=1 -MX5 net5 CLK VDD VDD sg13_lv_pmos m=1 w=840.00n l=130.00n ng=1 -MX3 net4 int_GATE VDD VDD sg13_lv_pmos m=1 w=420.00n l=130.00n ng=1 -MX2 net1 GATE net3 VDD sg13_lv_pmos m=1 w=840.00n l=130.00n ng=1 -MX21 int_GATE net6 VSS VSS sg13_lv_nmos m=1 w=740.00n l=130.00n ng=1 -MX20 net2 CLK VSS VSS sg13_lv_nmos m=1 w=640.00n l=130.00n ng=1 -MX17 net1 SCE VSS VSS sg13_lv_nmos m=1 w=550.00n l=130.00n ng=1 -MX15 net6 CLKb net1 VSS sg13_lv_nmos m=1 w=550.00n l=130.00n ng=1 -MX12 net7 int_GATE VSS VSS sg13_lv_nmos m=1 w=420.00n l=130.00n ng=1 -MX10 net5 int_GATE net2 VSS sg13_lv_nmos m=1 w=640.00n l=130.00n ng=1 -MX8 GCLK net5 VSS VSS sg13_lv_nmos m=1 w=740.00n l=130.00n ng=1 -MX6 CLKbb CLKb VSS VSS sg13_lv_nmos m=1 w=740.00n l=130.00n ng=1 -MX4 net1 GATE VSS VSS sg13_lv_nmos m=1 w=550.00n l=130.00n ng=1 -MX1 CLKb CLK VSS VSS sg13_lv_nmos m=1 w=740.00n l=130.00n ng=1 -MX0 net6 CLKbb net7 VSS sg13_lv_nmos m=1 w=420.00n l=130.00n ng=1 +MP10 GCLK net5 VDD VDD sg13_lv_pmos m=1 w=1.12u l=130.00n ng=1 +MP4 net1 CLKbb net6 VDD sg13_lv_pmos m=1 w=840.00n l=130.00n ng=1 +MP1 CLKbb CLKb VDD VDD sg13_lv_pmos m=1 w=840.00n l=130.00n ng=1 +MP8 net5 int_GATE VDD VDD sg13_lv_pmos m=1 w=840.00n l=130.00n ng=1 +MP2 net3 SCE VDD VDD sg13_lv_pmos m=1 w=840.00n l=130.00n ng=1 +MP7 net6 CLKb net4 VDD sg13_lv_pmos m=1 w=420.00n l=130.00n ng=1 +MP5 int_GATE net6 VDD VDD sg13_lv_pmos m=1 w=1.12u l=130.00n ng=1 +MP0 CLKb CLK VDD VDD sg13_lv_pmos m=1 w=840.00n l=130.00n ng=1 +MP9 net5 CLK VDD VDD sg13_lv_pmos m=1 w=840.00n l=130.00n ng=1 +MP6 net4 int_GATE VDD VDD sg13_lv_pmos m=1 w=420.00n l=130.00n ng=1 +MP3 net1 GATE net3 VDD sg13_lv_pmos m=1 w=840.00n l=130.00n ng=1 +MN5 int_GATE net6 VSS VSS sg13_lv_nmos m=1 w=740.00n l=130.00n ng=1 +MN9 net2 CLK VSS VSS sg13_lv_nmos m=1 w=640.00n l=130.00n ng=1 +MN2 net1 SCE VSS VSS sg13_lv_nmos m=1 w=550.00n l=130.00n ng=1 +MN4 net6 CLKb net1 VSS sg13_lv_nmos m=1 w=550.00n l=130.00n ng=1 +MN7 net7 int_GATE VSS VSS sg13_lv_nmos m=1 w=420.00n l=130.00n ng=1 +MN8 net5 int_GATE net2 VSS sg13_lv_nmos m=1 w=640.00n l=130.00n ng=1 +MN10 GCLK net5 VSS VSS sg13_lv_nmos m=1 w=740.00n l=130.00n ng=1 +MN1 CLKbb CLKb VSS VSS sg13_lv_nmos m=1 w=740.00n l=130.00n ng=1 +MN3 net1 GATE VSS VSS sg13_lv_nmos m=1 w=550.00n l=130.00n ng=1 +MN0 CLKb CLK VSS VSS sg13_lv_nmos m=1 w=740.00n l=130.00n ng=1 +MN6 net6 CLKbb net7 VSS sg13_lv_nmos m=1 w=420.00n l=130.00n ng=1 .ENDS ************************************************************************ @@ -1364,10 +1364,10 @@ MX0 net6 CLKbb net7 VSS sg13_lv_nmos m=1 w=420.00n l=130.00n ng=1 .SUBCKT sg13g2_tiehi L_HI VDD VSS *.PININFO L_HI:O VDD:B VSS:B -MMN2 net3 net2 VSS VSS sg13_lv_nmos m=1 w=795.00n l=130.00n ng=1 -MMN1 net1 net1 VSS VSS sg13_lv_nmos m=1 w=300n l=130.00n ng=1 -MMP2 L_HI net3 VDD VDD sg13_lv_pmos m=1 w=1.155u l=130.00n ng=1 -MMP1 net2 net1 VDD VDD sg13_lv_pmos m=1 w=660.0n l=130.00n ng=1 +MN1 net3 net2 VSS VSS sg13_lv_nmos m=1 w=795.00n l=130.00n ng=1 +MN0 net1 net1 VSS VSS sg13_lv_nmos m=1 w=300n l=130.00n ng=1 +MP1 L_HI net3 VDD VDD sg13_lv_pmos m=1 w=1.155u l=130.00n ng=1 +MP0 net2 net1 VDD VDD sg13_lv_pmos m=1 w=660.0n l=130.00n ng=1 .ENDS ************************************************************************ @@ -1378,10 +1378,10 @@ MMP1 net2 net1 VDD VDD sg13_lv_pmos m=1 w=660.0n l=130.00n ng=1 .SUBCKT sg13g2_tielo L_LO VDD VSS *.PININFO L_LO:O VDD:B VSS:B -MMN1 net3 net2 VSS VSS sg13_lv_nmos m=1 w=385.00n l=130.00n ng=1 -MMN2 L_LO net1 VSS VSS sg13_lv_nmos m=1 w=880.0n l=130.00n ng=1 -MMP1 net2 net2 VDD VDD sg13_lv_pmos m=1 w=300n l=130.00n ng=1 -MMP2 net1 net3 VDD VDD sg13_lv_pmos m=1 w=1.045u l=130.00n ng=1 +MN0 net3 net2 VSS VSS sg13_lv_nmos m=1 w=385.00n l=130.00n ng=1 +MN1 L_LO net1 VSS VSS sg13_lv_nmos m=1 w=880.0n l=130.00n ng=1 +MP0 net2 net2 VDD VDD sg13_lv_pmos m=1 w=300n l=130.00n ng=1 +MP1 net1 net3 VDD VDD sg13_lv_pmos m=1 w=1.045u l=130.00n ng=1 .ENDS ************************************************************************ @@ -1392,15 +1392,15 @@ MMP2 net1 net3 VDD VDD sg13_lv_pmos m=1 w=1.045u l=130.00n ng=1 .SUBCKT sg13g2_xnor2_1 Y A B VDD VSS *.PININFO A:I B:I Y:O VDD:B VSS:B -MP9 Y net1 VDD VDD sg13_lv_pmos m=1 w=1.12u l=130.00n ng=1 -MP8 Y B net4 VDD sg13_lv_pmos m=1 w=1.12u l=130.00n ng=1 -MP7 net4 A VDD VDD sg13_lv_pmos m=1 w=1.12u l=130.00n ng=1 +MP4 Y net1 VDD VDD sg13_lv_pmos m=1 w=1.12u l=130.00n ng=1 +MP3 Y B net4 VDD sg13_lv_pmos m=1 w=1.12u l=130.00n ng=1 +MP2 net4 A VDD VDD sg13_lv_pmos m=1 w=1.12u l=130.00n ng=1 MP1 net1 B VDD VDD sg13_lv_pmos m=1 w=840.00n l=130.00n ng=1 MP0 net1 A VDD VDD sg13_lv_pmos m=1 w=840.00n l=130.00n ng=1 -MN4 Y net1 net3 VSS sg13_lv_nmos m=1 w=740.00n l=130.00n ng=1 -MN6 net2 A VSS VSS sg13_lv_nmos m=1 w=640.00n l=130.00n ng=1 -MN5 net1 B net2 VSS sg13_lv_nmos m=1 w=640.00n l=130.00n ng=1 -MN3 net3 B VSS VSS sg13_lv_nmos m=1 w=740.00n l=130.00n ng=1 +MN3 Y net1 net3 VSS sg13_lv_nmos m=1 w=740.00n l=130.00n ng=1 +MN1 net2 A VSS VSS sg13_lv_nmos m=1 w=640.00n l=130.00n ng=1 +MN0 net1 B net2 VSS sg13_lv_nmos m=1 w=640.00n l=130.00n ng=1 +MN4 net3 B VSS VSS sg13_lv_nmos m=1 w=740.00n l=130.00n ng=1 MN2 net3 A VSS VSS sg13_lv_nmos m=1 w=740.00n l=130.00n ng=1 .ENDS @@ -1412,16 +1412,16 @@ MN2 net3 A VSS VSS sg13_lv_nmos m=1 w=740.00n l=130.00n ng=1 .SUBCKT sg13g2_xor2_1 X A B VDD VSS *.PININFO A:I B:I X:O VDD:B VSS:B -MX0 net1 A VSS VSS sg13_lv_nmos m=1 w=550.00n l=130.00n ng=1 -MX4 X B net3 VSS sg13_lv_nmos m=1 w=740.00n l=130.00n ng=1 -MX6 X net1 VSS VSS sg13_lv_nmos m=1 w=740.00n l=130.00n ng=1 -MX8 net3 A VSS VSS sg13_lv_nmos m=1 w=740.00n l=130.00n ng=1 -MX9 net1 B VSS VSS sg13_lv_nmos m=1 w=550.00n l=130.00n ng=1 -MX1 net6 A VDD VDD sg13_lv_pmos m=1 w=1.000u l=130.00n ng=1 -MX2 net1 B net6 VDD sg13_lv_pmos m=1 w=1.000u l=130.00n ng=1 -MX3 net5 A VDD VDD sg13_lv_pmos m=1 w=1.12u l=130.00n ng=1 -MX5 net5 B VDD VDD sg13_lv_pmos m=1 w=1.12u l=130.00n ng=1 -MX7 X net1 net5 VDD sg13_lv_pmos m=1 w=1.12u l=130.00n ng=1 +MN0 net1 A VSS VSS sg13_lv_nmos m=1 w=550.00n l=130.00n ng=1 +MN3 X B net3 VSS sg13_lv_nmos m=1 w=740.00n l=130.00n ng=1 +MN2 X net1 VSS VSS sg13_lv_nmos m=1 w=740.00n l=130.00n ng=1 +MN4 net3 A VSS VSS sg13_lv_nmos m=1 w=740.00n l=130.00n ng=1 +MN1 net1 B VSS VSS sg13_lv_nmos m=1 w=550.00n l=130.00n ng=1 +MP0 net6 A VDD VDD sg13_lv_pmos m=1 w=1.000u l=130.00n ng=1 +MP1 net1 B net6 VDD sg13_lv_pmos m=1 w=1.000u l=130.00n ng=1 +MP2 net5 A VDD VDD sg13_lv_pmos m=1 w=1.12u l=130.00n ng=1 +MP4 net5 B VDD VDD sg13_lv_pmos m=1 w=1.12u l=130.00n ng=1 +MP3 X net1 net5 VDD sg13_lv_pmos m=1 w=1.12u l=130.00n ng=1 .ENDS ************************************************************************ @@ -1432,118 +1432,118 @@ MX7 X net1 net5 VDD sg13_lv_pmos m=1 w=1.12u l=130.00n ng=1 .SUBCKT sg13g2_a22oi_1 Y A1 A2 B1 B2 VDD VSS *.PININFO A1:I A2:I B1:I B2:I Y:O VDD:B VSS:B -MN3 net1 B1 VSS VSS sg13_lv_nmos m=1 w=740.00n l=130.00n ng=1 -MMNB0 Y B2 net1 VSS sg13_lv_nmos m=1 w=740.00n l=130.00n ng=1 -MMNA1 sndA1 A2 VSS VSS sg13_lv_nmos m=1 w=740.00n l=130.00n ng=1 -MMNA0 Y A1 sndA1 VSS sg13_lv_nmos m=1 w=740.00n l=130.00n ng=1 -MP3 Y B1 pndA VDD sg13_lv_pmos m=1 w=1.12u l=130.00n ng=1 -MMPB0 Y B2 pndA VDD sg13_lv_pmos m=1 w=1.12u l=130.00n ng=1 -MMPA1 pndA A2 VDD VDD sg13_lv_pmos m=1 w=1.12u l=130.00n ng=1 -MMPA0 pndA A1 VDD VDD sg13_lv_pmos m=1 w=1.12u l=130.00n ng=1 +MN1 net1 B1 VSS VSS sg13_lv_nmos m=1 w=740.00n l=130.00n ng=1 +MN0 Y B2 net1 VSS sg13_lv_nmos m=1 w=740.00n l=130.00n ng=1 +MN3 net2 A2 VSS VSS sg13_lv_nmos m=1 w=740.00n l=130.00n ng=1 +MN2 Y A1 net2 VSS sg13_lv_nmos m=1 w=740.00n l=130.00n ng=1 +MP1 Y B1 net3 VDD sg13_lv_pmos m=1 w=1.12u l=130.00n ng=1 +MP3 Y B2 net3 VDD sg13_lv_pmos m=1 w=1.12u l=130.00n ng=1 +MP2 net3 A2 VDD VDD sg13_lv_pmos m=1 w=1.12u l=130.00n ng=1 +MP0 net3 A1 VDD VDD sg13_lv_pmos m=1 w=1.12u l=130.00n ng=1 .ENDS ************************************************************************ * Library Name: sg13g2_stdcell -* Cell Name: sg13g2_sdfrbpq_2 +* Cell Name: sg13g2_sdfrbpq_1 * View Name: schematic ************************************************************************ -.SUBCKT sg13g2_sdfrbpq_2 Q CLK D RESET_B SCD SCE VDD VSS +.SUBCKT sg13g2_sdfrbpq_1 Q CLK D RESET_B SCD SCE VDD VSS *.PININFO CLK:I D:I RESET_B:I SCD:I SCE:I Q:O VDD:B VSS:B -MN22 Db SCD net63 VSS sg13_lv_nmos m=1 w=740.00n l=130.00n ng=1 -MN21 Db D net65 VSS sg13_lv_nmos m=1 w=740.00n l=130.00n ng=1 -MN19 SCEb SCE VSS VSS sg13_lv_nmos m=1 w=550.00n l=130.00n ng=1 -MN18 net63 SCE VSS VSS sg13_lv_nmos m=1 w=740.00n l=130.00n ng=1 -MN17 net65 SCEb VSS VSS sg13_lv_nmos m=1 w=740.00n l=130.00n ng=1 -MN23 Dbb Db VSS VSS sg13_lv_nmos m=1 w=740.00n l=130.00n ng=1 -MN13 net12 net2 VSS VSS sg13_lv_nmos m=1 w=420.00n l=130.00n ng=1 -MN14 net5 clkneg net12 VSS sg13_lv_nmos m=1 w=420.00n l=130.00n ng=1 -MN15 net2 net5 net11 VSS sg13_lv_nmos m=1 w=420.00n l=130.00n ng=1 -MN16 net11 RESET_B VSS VSS sg13_lv_nmos m=1 w=420.00n l=130.00n ng=1 -MN6 Q net2 VSS VSS sg13_lv_nmos m=1 w=1.48u l=130.00n ng=2 -MN0 Dbbb Dbb net10 VSS sg13_lv_nmos m=1 w=420.00n l=130.00n ng=1 -MN1 net10 RESET_B VSS VSS sg13_lv_nmos m=1 w=420.00n l=130.00n ng=1 -MN7 Dbbb clkneg net6 VSS sg13_lv_nmos m=1 w=420.00n l=130.00n ng=1 -MN8 net6 clkpos net9 VSS sg13_lv_nmos m=1 w=420.00n l=130.00n ng=1 -MN9 net9 net4 net8 VSS sg13_lv_nmos m=1 w=420.00n l=130.00n ng=1 -MN10 net8 RESET_B VSS VSS sg13_lv_nmos m=1 w=420.00n l=130.00n ng=1 -MN11 net4 net6 VSS VSS sg13_lv_nmos m=1 w=740.00n l=130.00n ng=1 -MN2 clkneg CLK VSS VSS sg13_lv_nmos m=1 w=740.00n l=130.00n ng=1 -MN12 net4 clkpos net5 VSS sg13_lv_nmos m=1 w=740.00n l=130.00n ng=1 -MN3 clkpos clkneg VSS VSS sg13_lv_nmos m=1 w=740.00n l=130.00n ng=1 -MP22 net64 SCE VDD VDD sg13_lv_pmos m=1 w=1.000u l=130.00n ng=1 -MP21 net62 SCEb VDD VDD sg13_lv_pmos m=1 w=1.000u l=130.00n ng=1 -MP20 SCEb SCE VDD VDD sg13_lv_pmos m=1 w=840.00n l=130.00n ng=1 -MP18 Db SCD net62 VDD sg13_lv_pmos m=1 w=1.000u l=130.00n ng=1 -MP17 Db D net64 VDD sg13_lv_pmos m=1 w=1.000u l=130.00n ng=1 -MP23 Dbb Db VDD VDD sg13_lv_pmos m=1 w=1.12u l=130.00n ng=1 -MP14 net5 clkpos net3 VDD sg13_lv_pmos m=1 w=420.00n l=130.00n ng=1 -MP15 net2 net5 VDD VDD sg13_lv_pmos m=1 w=420.00n l=130.00n ng=1 -MP16 net2 RESET_B VDD VDD sg13_lv_pmos m=1 w=420.00n l=130.00n ng=1 -MP6 Q net2 VDD VDD sg13_lv_pmos m=1 w=2.24u l=130.00n ng=2 -MP7 Dbbb clkpos net6 VDD sg13_lv_pmos m=1 w=420.00n l=130.00n ng=1 -MP0 Dbbb RESET_B VDD VDD sg13_lv_pmos m=1 w=420.00n l=130.00n ng=1 -MP1 Dbbb Dbb VDD VDD sg13_lv_pmos m=1 w=420.00n l=130.00n ng=1 -MP8 net7 net4 VDD VDD sg13_lv_pmos m=1 w=420.00n l=130.00n ng=1 -MP9 net6 clkneg net7 VDD sg13_lv_pmos m=1 w=420.00n l=130.00n ng=1 -MP10 net6 RESET_B VDD VDD sg13_lv_pmos m=1 w=420.00n l=130.00n ng=1 -MP2 clkneg CLK VDD VDD sg13_lv_pmos m=1 w=1.12u l=130.00n ng=1 -MP3 clkpos clkneg VDD VDD sg13_lv_pmos m=1 w=1.12u l=130.00n ng=1 -MP11 net4 net6 VDD VDD sg13_lv_pmos m=1 w=1.000u l=130.00n ng=1 -MP12 net4 clkneg net5 VDD sg13_lv_pmos m=1 w=1.000u l=130.00n ng=1 -MP13 net3 net2 VDD VDD sg13_lv_pmos m=1 w=420.00n l=130.00n ng=1 +MN3 Db SCD net63 VSS sg13_lv_nmos m=1 w=740.00n l=130.00n ng=1 +MN1 Db D net65 VSS sg13_lv_nmos m=1 w=740.00n l=130.00n ng=1 +MN0 SCEb SCE VSS VSS sg13_lv_nmos m=1 w=550.00n l=130.00n ng=1 +MN4 net63 SCE VSS VSS sg13_lv_nmos m=1 w=740.00n l=130.00n ng=1 +MN2 net65 SCEb VSS VSS sg13_lv_nmos m=1 w=740.00n l=130.00n ng=1 +MN17 net12 net2 VSS VSS sg13_lv_nmos m=1 w=420.00n l=130.00n ng=1 +MN16 net5 clkneg net12 VSS sg13_lv_nmos m=1 w=420.00n l=130.00n ng=1 +MN18 net2 net5 net11 VSS sg13_lv_nmos m=1 w=420.00n l=130.00n ng=1 +MN19 net11 RESET_B VSS VSS sg13_lv_nmos m=1 w=420.00n l=130.00n ng=1 +MN20 Q net2 VSS VSS sg13_lv_nmos m=1 w=740.00n l=130.00n ng=1 +MN6 Dbbb Dbb net10 VSS sg13_lv_nmos m=1 w=420.00n l=130.00n ng=1 +MN7 net10 RESET_B VSS VSS sg13_lv_nmos m=1 w=420.00n l=130.00n ng=1 +MN10 Dbbb clkneg net6 VSS sg13_lv_nmos m=1 w=420.00n l=130.00n ng=1 +MN11 net6 clkpos net9 VSS sg13_lv_nmos m=1 w=420.00n l=130.00n ng=1 +MN12 net9 net4 net8 VSS sg13_lv_nmos m=1 w=420.00n l=130.00n ng=1 +MN13 net8 RESET_B VSS VSS sg13_lv_nmos m=1 w=420.00n l=130.00n ng=1 +MN14 net4 net6 VSS VSS sg13_lv_nmos m=1 w=740.00n l=130.00n ng=1 +MN8 clkneg CLK VSS VSS sg13_lv_nmos m=1 w=740.00n l=130.00n ng=1 +MN15 net4 clkpos net5 VSS sg13_lv_nmos m=1 w=740.00n l=130.00n ng=1 +MN9 clkpos clkneg VSS VSS sg13_lv_nmos m=1 w=740.00n l=130.00n ng=1 +MN5 Dbb Db VSS VSS sg13_lv_nmos m=1 w=740.00n l=130.00n ng=1 +MP1 net64 SCE VDD VDD sg13_lv_pmos m=1 w=1.000u l=130.00n ng=1 +MP3 net62 SCEb VDD VDD sg13_lv_pmos m=1 w=1.000u l=130.00n ng=1 +MP0 SCEb SCE VDD VDD sg13_lv_pmos m=1 w=840.00n l=130.00n ng=1 +MP4 Db SCD net62 VDD sg13_lv_pmos m=1 w=1.000u l=130.00n ng=1 +MP2 Db D net64 VDD sg13_lv_pmos m=1 w=1.000u l=130.00n ng=1 +MP17 net5 clkpos net3 VDD sg13_lv_pmos m=1 w=420.00n l=130.00n ng=1 +MP18 net2 net5 VDD VDD sg13_lv_pmos m=1 w=420.00n l=130.00n ng=1 +MP19 net2 RESET_B VDD VDD sg13_lv_pmos m=1 w=420.00n l=130.00n ng=1 +MP20 Q net2 VDD VDD sg13_lv_pmos m=1 w=1.12u l=130.00n ng=1 +MP10 Dbbb clkpos net6 VDD sg13_lv_pmos m=1 w=420.00n l=130.00n ng=1 +MP6 Dbbb RESET_B VDD VDD sg13_lv_pmos m=1 w=420.00n l=130.00n ng=1 +MP7 Dbbb Dbb VDD VDD sg13_lv_pmos m=1 w=420.00n l=130.00n ng=1 +MP11 net7 net4 VDD VDD sg13_lv_pmos m=1 w=420.00n l=130.00n ng=1 +MP12 net6 clkneg net7 VDD sg13_lv_pmos m=1 w=420.00n l=130.00n ng=1 +MP13 net6 RESET_B VDD VDD sg13_lv_pmos m=1 w=420.00n l=130.00n ng=1 +MP8 clkneg CLK VDD VDD sg13_lv_pmos m=1 w=1.12u l=130.00n ng=1 +MP9 clkpos clkneg VDD VDD sg13_lv_pmos m=1 w=1.12u l=130.00n ng=1 +MP14 net4 net6 VDD VDD sg13_lv_pmos m=1 w=1.000u l=130.00n ng=1 +MP15 net4 clkneg net5 VDD sg13_lv_pmos m=1 w=1.000u l=130.00n ng=1 +MP5 Dbb Db VDD VDD sg13_lv_pmos m=1 w=1.12u l=130.00n ng=1 +MP16 net3 net2 VDD VDD sg13_lv_pmos m=1 w=420.00n l=130.00n ng=1 .ENDS ************************************************************************ * Library Name: sg13g2_stdcell -* Cell Name: sg13g2_sdfrbpq_1 +* Cell Name: sg13g2_sdfrbpq_2 * View Name: schematic ************************************************************************ -.SUBCKT sg13g2_sdfrbpq_1 Q CLK D RESET_B SCD SCE VDD VSS +.SUBCKT sg13g2_sdfrbpq_2 Q CLK D RESET_B SCD SCE VDD VSS *.PININFO CLK:I D:I RESET_B:I SCD:I SCE:I Q:O VDD:B VSS:B -MN22 Db SCD net63 VSS sg13_lv_nmos m=1 w=740.00n l=130.00n ng=1 -MN21 Db D net65 VSS sg13_lv_nmos m=1 w=740.00n l=130.00n ng=1 -MN19 SCEb SCE VSS VSS sg13_lv_nmos m=1 w=550.00n l=130.00n ng=1 -MN18 net63 SCE VSS VSS sg13_lv_nmos m=1 w=740.00n l=130.00n ng=1 -MN17 net65 SCEb VSS VSS sg13_lv_nmos m=1 w=740.00n l=130.00n ng=1 -MN13 net12 net2 VSS VSS sg13_lv_nmos m=1 w=420.00n l=130.00n ng=1 -MN14 net5 clkneg net12 VSS sg13_lv_nmos m=1 w=420.00n l=130.00n ng=1 -MN15 net2 net5 net11 VSS sg13_lv_nmos m=1 w=420.00n l=130.00n ng=1 -MN16 net11 RESET_B VSS VSS sg13_lv_nmos m=1 w=420.00n l=130.00n ng=1 -MN6 Q net2 VSS VSS sg13_lv_nmos m=1 w=740.00n l=130.00n ng=1 -MN0 Dbbb Dbb net10 VSS sg13_lv_nmos m=1 w=420.00n l=130.00n ng=1 -MN1 net10 RESET_B VSS VSS sg13_lv_nmos m=1 w=420.00n l=130.00n ng=1 -MN7 Dbbb clkneg net6 VSS sg13_lv_nmos m=1 w=420.00n l=130.00n ng=1 -MN8 net6 clkpos net9 VSS sg13_lv_nmos m=1 w=420.00n l=130.00n ng=1 -MN9 net9 net4 net8 VSS sg13_lv_nmos m=1 w=420.00n l=130.00n ng=1 -MN10 net8 RESET_B VSS VSS sg13_lv_nmos m=1 w=420.00n l=130.00n ng=1 -MN11 net4 net6 VSS VSS sg13_lv_nmos m=1 w=740.00n l=130.00n ng=1 -MN2 clkneg CLK VSS VSS sg13_lv_nmos m=1 w=740.00n l=130.00n ng=1 -MN12 net4 clkpos net5 VSS sg13_lv_nmos m=1 w=740.00n l=130.00n ng=1 -MN3 clkpos clkneg VSS VSS sg13_lv_nmos m=1 w=740.00n l=130.00n ng=1 -MN23 Dbb Db VSS VSS sg13_lv_nmos m=1 w=740.00n l=130.00n ng=1 -MP22 net64 SCE VDD VDD sg13_lv_pmos m=1 w=1.000u l=130.00n ng=1 -MP21 net62 SCEb VDD VDD sg13_lv_pmos m=1 w=1.000u l=130.00n ng=1 -MP20 SCEb SCE VDD VDD sg13_lv_pmos m=1 w=840.00n l=130.00n ng=1 -MP18 Db SCD net62 VDD sg13_lv_pmos m=1 w=1.000u l=130.00n ng=1 -MP17 Db D net64 VDD sg13_lv_pmos m=1 w=1.000u l=130.00n ng=1 -MP14 net5 clkpos net3 VDD sg13_lv_pmos m=1 w=420.00n l=130.00n ng=1 -MP15 net2 net5 VDD VDD sg13_lv_pmos m=1 w=420.00n l=130.00n ng=1 -MP16 net2 RESET_B VDD VDD sg13_lv_pmos m=1 w=420.00n l=130.00n ng=1 -MP6 Q net2 VDD VDD sg13_lv_pmos m=1 w=1.12u l=130.00n ng=1 -MP7 Dbbb clkpos net6 VDD sg13_lv_pmos m=1 w=420.00n l=130.00n ng=1 -MP0 Dbbb RESET_B VDD VDD sg13_lv_pmos m=1 w=420.00n l=130.00n ng=1 -MP1 Dbbb Dbb VDD VDD sg13_lv_pmos m=1 w=420.00n l=130.00n ng=1 -MP8 net7 net4 VDD VDD sg13_lv_pmos m=1 w=420.00n l=130.00n ng=1 -MP9 net6 clkneg net7 VDD sg13_lv_pmos m=1 w=420.00n l=130.00n ng=1 -MP10 net6 RESET_B VDD VDD sg13_lv_pmos m=1 w=420.00n l=130.00n ng=1 -MP2 clkneg CLK VDD VDD sg13_lv_pmos m=1 w=1.12u l=130.00n ng=1 -MP3 clkpos clkneg VDD VDD sg13_lv_pmos m=1 w=1.12u l=130.00n ng=1 -MP11 net4 net6 VDD VDD sg13_lv_pmos m=1 w=1.000u l=130.00n ng=1 -MP12 net4 clkneg net5 VDD sg13_lv_pmos m=1 w=1.000u l=130.00n ng=1 -MP23 Dbb Db VDD VDD sg13_lv_pmos m=1 w=1.12u l=130.00n ng=1 -MP13 net3 net2 VDD VDD sg13_lv_pmos m=1 w=420.00n l=130.00n ng=1 +MN3 Db SCD net63 VSS sg13_lv_nmos m=1 w=740.00n l=130.00n ng=1 +MN1 Db D net65 VSS sg13_lv_nmos m=1 w=740.00n l=130.00n ng=1 +MN0 SCEb SCE VSS VSS sg13_lv_nmos m=1 w=550.00n l=130.00n ng=1 +MN4 net63 SCE VSS VSS sg13_lv_nmos m=1 w=740.00n l=130.00n ng=1 +MN2 net65 SCEb VSS VSS sg13_lv_nmos m=1 w=740.00n l=130.00n ng=1 +MN5 Dbb Db VSS VSS sg13_lv_nmos m=1 w=740.00n l=130.00n ng=1 +MN17 net12 net2 VSS VSS sg13_lv_nmos m=1 w=420.00n l=130.00n ng=1 +MN16 net5 clkneg net12 VSS sg13_lv_nmos m=1 w=420.00n l=130.00n ng=1 +MN18 net2 net5 net11 VSS sg13_lv_nmos m=1 w=420.00n l=130.00n ng=1 +MN19 net11 RESET_B VSS VSS sg13_lv_nmos m=1 w=420.00n l=130.00n ng=1 +MN20 Q net2 VSS VSS sg13_lv_nmos m=1 w=1.48u l=130.00n ng=2 +MN6 Dbbb Dbb net10 VSS sg13_lv_nmos m=1 w=420.00n l=130.00n ng=1 +MN7 net10 RESET_B VSS VSS sg13_lv_nmos m=1 w=420.00n l=130.00n ng=1 +MN10 Dbbb clkneg net6 VSS sg13_lv_nmos m=1 w=420.00n l=130.00n ng=1 +MN11 net6 clkpos net9 VSS sg13_lv_nmos m=1 w=420.00n l=130.00n ng=1 +MN12 net9 net4 net8 VSS sg13_lv_nmos m=1 w=420.00n l=130.00n ng=1 +MN13 net8 RESET_B VSS VSS sg13_lv_nmos m=1 w=420.00n l=130.00n ng=1 +MN14 net4 net6 VSS VSS sg13_lv_nmos m=1 w=740.00n l=130.00n ng=1 +MN8 clkneg CLK VSS VSS sg13_lv_nmos m=1 w=740.00n l=130.00n ng=1 +MN15 net4 clkpos net5 VSS sg13_lv_nmos m=1 w=740.00n l=130.00n ng=1 +MN9 clkpos clkneg VSS VSS sg13_lv_nmos m=1 w=740.00n l=130.00n ng=1 +MP1 net64 SCE VDD VDD sg13_lv_pmos m=1 w=1.000u l=130.00n ng=1 +MP3 net62 SCEb VDD VDD sg13_lv_pmos m=1 w=1.000u l=130.00n ng=1 +MP0 SCEb SCE VDD VDD sg13_lv_pmos m=1 w=840.00n l=130.00n ng=1 +MP4 Db SCD net62 VDD sg13_lv_pmos m=1 w=1.000u l=130.00n ng=1 +MP2 Db D net64 VDD sg13_lv_pmos m=1 w=1.000u l=130.00n ng=1 +MP5 Dbb Db VDD VDD sg13_lv_pmos m=1 w=1.12u l=130.00n ng=1 +MP17 net5 clkpos net3 VDD sg13_lv_pmos m=1 w=420.00n l=130.00n ng=1 +MP18 net2 net5 VDD VDD sg13_lv_pmos m=1 w=420.00n l=130.00n ng=1 +MP19 net2 RESET_B VDD VDD sg13_lv_pmos m=1 w=420.00n l=130.00n ng=1 +MP20 Q net2 VDD VDD sg13_lv_pmos m=1 w=2.24u l=130.00n ng=2 +MP10 Dbbb clkpos net6 VDD sg13_lv_pmos m=1 w=420.00n l=130.00n ng=1 +MP6 Dbbb RESET_B VDD VDD sg13_lv_pmos m=1 w=420.00n l=130.00n ng=1 +MP7 Dbbb Dbb VDD VDD sg13_lv_pmos m=1 w=420.00n l=130.00n ng=1 +MP11 net7 net4 VDD VDD sg13_lv_pmos m=1 w=420.00n l=130.00n ng=1 +MP12 net6 clkneg net7 VDD sg13_lv_pmos m=1 w=420.00n l=130.00n ng=1 +MP13 net6 RESET_B VDD VDD sg13_lv_pmos m=1 w=420.00n l=130.00n ng=1 +MP8 clkneg CLK VDD VDD sg13_lv_pmos m=1 w=1.12u l=130.00n ng=1 +MP9 clkpos clkneg VDD VDD sg13_lv_pmos m=1 w=1.12u l=130.00n ng=1 +MP14 net4 net6 VDD VDD sg13_lv_pmos m=1 w=1.000u l=130.00n ng=1 +MP15 net4 clkneg net5 VDD sg13_lv_pmos m=1 w=1.000u l=130.00n ng=1 +MP16 net3 net2 VDD VDD sg13_lv_pmos m=1 w=420.00n l=130.00n ng=1 .ENDS ************************************************************************ @@ -1554,52 +1554,52 @@ MP13 net3 net2 VDD VDD sg13_lv_pmos m=1 w=420.00n l=130.00n ng=1 .SUBCKT sg13g2_sdfrbp_2 Q Q_N CLK D RESET_B SCD SCE VDD VSS *.PININFO CLK:I D:I RESET_B:I SCD:I SCE:I Q:O Q_N:O VDD:B VSS:B -MN22 Db SCD net63 VSS sg13_lv_nmos m=1 w=740.00n l=130.00n ng=1 -MN21 Db D net65 VSS sg13_lv_nmos m=1 w=740.00n l=130.00n ng=1 -MN19 SCEb SCE VSS VSS sg13_lv_nmos m=1 w=550.00n l=130.00n ng=1 -MN18 net63 SCE VSS VSS sg13_lv_nmos m=1 w=740.00n l=130.00n ng=1 -MN17 net65 SCEb VSS VSS sg13_lv_nmos m=1 w=740.00n l=130.00n ng=1 -MN23 Dbb Db VSS VSS sg13_lv_nmos m=1 w=740.00n l=130.00n ng=1 -MN13 net12 net2 VSS VSS sg13_lv_nmos m=1 w=420.00n l=130.00n ng=1 -MN14 net5 clkneg net12 VSS sg13_lv_nmos m=1 w=420.00n l=130.00n ng=1 -MN15 net2 net5 net11 VSS sg13_lv_nmos m=1 w=420.00n l=130.00n ng=1 -MN16 net11 RESET_B VSS VSS sg13_lv_nmos m=1 w=420.00n l=130.00n ng=1 -MN6 Q_N net5 VSS VSS sg13_lv_nmos m=1 w=1.48u l=130.00n ng=2 -MN0 Dbbb Dbb net10 VSS sg13_lv_nmos m=1 w=420.00n l=130.00n ng=1 -MN1 net10 RESET_B VSS VSS sg13_lv_nmos m=1 w=420.00n l=130.00n ng=1 -MN7 Dbbb clkneg net6 VSS sg13_lv_nmos m=1 w=420.00n l=130.00n ng=1 -MN8 net6 clkpos net9 VSS sg13_lv_nmos m=1 w=420.00n l=130.00n ng=1 -MN9 net9 net4 net8 VSS sg13_lv_nmos m=1 w=420.00n l=130.00n ng=1 -MN10 net8 RESET_B VSS VSS sg13_lv_nmos m=1 w=420.00n l=130.00n ng=1 -MN11 net4 net6 VSS VSS sg13_lv_nmos m=1 w=740.00n l=130.00n ng=1 -MN2 clkneg CLK VSS VSS sg13_lv_nmos m=1 w=740.00n l=130.00n ng=1 -MN12 net4 clkpos net5 VSS sg13_lv_nmos m=1 w=740.00n l=130.00n ng=1 -MN3 clkpos clkneg VSS VSS sg13_lv_nmos m=1 w=740.00n l=130.00n ng=1 -MN4 Q net1 VSS VSS sg13_lv_nmos m=1 w=1.48u l=130.00n ng=2 -MN5 net1 net5 VSS VSS sg13_lv_nmos m=1 w=640.00n l=130.00n ng=1 -MP22 net64 SCE VDD VDD sg13_lv_pmos m=1 w=1.000u l=130.00n ng=1 -MP21 net62 SCEb VDD VDD sg13_lv_pmos m=1 w=1.000u l=130.00n ng=1 -MP20 SCEb SCE VDD VDD sg13_lv_pmos m=1 w=840.00n l=130.00n ng=1 -MP18 Db SCD net62 VDD sg13_lv_pmos m=1 w=1.000u l=130.00n ng=1 -MP17 Db D net64 VDD sg13_lv_pmos m=1 w=1.000u l=130.00n ng=1 -MP23 Dbb Db VDD VDD sg13_lv_pmos m=1 w=1.12u l=130.00n ng=1 -MP14 net5 clkpos net3 VDD sg13_lv_pmos m=1 w=420.00n l=130.00n ng=1 -MP15 net2 net5 VDD VDD sg13_lv_pmos m=1 w=420.00n l=130.00n ng=1 -MP16 net2 RESET_B VDD VDD sg13_lv_pmos m=1 w=420.00n l=130.00n ng=1 -MP6 Q_N net5 VDD VDD sg13_lv_pmos m=1 w=2.24u l=130.00n ng=2 -MP7 Dbbb clkpos net6 VDD sg13_lv_pmos m=1 w=420.00n l=130.00n ng=1 -MP0 Dbbb RESET_B VDD VDD sg13_lv_pmos m=1 w=420.00n l=130.00n ng=1 -MP1 Dbbb Dbb VDD VDD sg13_lv_pmos m=1 w=420.00n l=130.00n ng=1 -MP8 net7 net4 VDD VDD sg13_lv_pmos m=1 w=420.00n l=130.00n ng=1 -MP9 net6 clkneg net7 VDD sg13_lv_pmos m=1 w=420.00n l=130.00n ng=1 -MP10 net6 RESET_B VDD VDD sg13_lv_pmos m=1 w=420.00n l=130.00n ng=1 -MP2 clkneg CLK VDD VDD sg13_lv_pmos m=1 w=1.12u l=130.00n ng=1 -MP3 clkpos clkneg VDD VDD sg13_lv_pmos m=1 w=1.12u l=130.00n ng=1 -MP11 net4 net6 VDD VDD sg13_lv_pmos m=1 w=1.000u l=130.00n ng=1 -MP12 net4 clkneg net5 VDD sg13_lv_pmos m=1 w=1.000u l=130.00n ng=1 -MP4 Q net1 VDD VDD sg13_lv_pmos m=1 w=2.24u l=130.00n ng=2 -MP13 net3 net2 VDD VDD sg13_lv_pmos m=1 w=420.00n l=130.00n ng=1 -MP5 net1 net5 VDD VDD sg13_lv_pmos m=1 w=1.000u l=130.00n ng=1 +MN3 Db SCD net63 VSS sg13_lv_nmos m=1 w=740.00n l=130.00n ng=1 +MN1 Db D net65 VSS sg13_lv_nmos m=1 w=740.00n l=130.00n ng=1 +MN0 SCEb SCE VSS VSS sg13_lv_nmos m=1 w=550.00n l=130.00n ng=1 +MN4 net63 SCE VSS VSS sg13_lv_nmos m=1 w=740.00n l=130.00n ng=1 +MN2 net65 SCEb VSS VSS sg13_lv_nmos m=1 w=740.00n l=130.00n ng=1 +MN5 Dbb Db VSS VSS sg13_lv_nmos m=1 w=740.00n l=130.00n ng=1 +MN17 net12 net2 VSS VSS sg13_lv_nmos m=1 w=420.00n l=130.00n ng=1 +MN16 net5 clkneg net12 VSS sg13_lv_nmos m=1 w=420.00n l=130.00n ng=1 +MN18 net2 net5 net11 VSS sg13_lv_nmos m=1 w=420.00n l=130.00n ng=1 +MN19 net11 RESET_B VSS VSS sg13_lv_nmos m=1 w=420.00n l=130.00n ng=1 +MN20 Q_N net5 VSS VSS sg13_lv_nmos m=1 w=1.48u l=130.00n ng=2 +MN6 Dbbb Dbb net10 VSS sg13_lv_nmos m=1 w=420.00n l=130.00n ng=1 +MN7 net10 RESET_B VSS VSS sg13_lv_nmos m=1 w=420.00n l=130.00n ng=1 +MN10 Dbbb clkneg net6 VSS sg13_lv_nmos m=1 w=420.00n l=130.00n ng=1 +MN11 net6 clkpos net9 VSS sg13_lv_nmos m=1 w=420.00n l=130.00n ng=1 +MN12 net9 net4 net8 VSS sg13_lv_nmos m=1 w=420.00n l=130.00n ng=1 +MN13 net8 RESET_B VSS VSS sg13_lv_nmos m=1 w=420.00n l=130.00n ng=1 +MN14 net4 net6 VSS VSS sg13_lv_nmos m=1 w=740.00n l=130.00n ng=1 +MN8 clkneg CLK VSS VSS sg13_lv_nmos m=1 w=740.00n l=130.00n ng=1 +MN15 net4 clkpos net5 VSS sg13_lv_nmos m=1 w=740.00n l=130.00n ng=1 +MN9 clkpos clkneg VSS VSS sg13_lv_nmos m=1 w=740.00n l=130.00n ng=1 +MN22 Q net1 VSS VSS sg13_lv_nmos m=1 w=1.48u l=130.00n ng=2 +MN21 net1 net5 VSS VSS sg13_lv_nmos m=1 w=640.00n l=130.00n ng=1 +MP1 net64 SCE VDD VDD sg13_lv_pmos m=1 w=1.000u l=130.00n ng=1 +MP3 net62 SCEb VDD VDD sg13_lv_pmos m=1 w=1.000u l=130.00n ng=1 +MP0 SCEb SCE VDD VDD sg13_lv_pmos m=1 w=840.00n l=130.00n ng=1 +MP4 Db SCD net62 VDD sg13_lv_pmos m=1 w=1.000u l=130.00n ng=1 +MP2 Db D net64 VDD sg13_lv_pmos m=1 w=1.000u l=130.00n ng=1 +MP5 Dbb Db VDD VDD sg13_lv_pmos m=1 w=1.12u l=130.00n ng=1 +MP17 net5 clkpos net3 VDD sg13_lv_pmos m=1 w=420.00n l=130.00n ng=1 +MP18 net2 net5 VDD VDD sg13_lv_pmos m=1 w=420.00n l=130.00n ng=1 +MP19 net2 RESET_B VDD VDD sg13_lv_pmos m=1 w=420.00n l=130.00n ng=1 +MP20 Q_N net5 VDD VDD sg13_lv_pmos m=1 w=2.24u l=130.00n ng=2 +MP10 Dbbb clkpos net6 VDD sg13_lv_pmos m=1 w=420.00n l=130.00n ng=1 +MP6 Dbbb RESET_B VDD VDD sg13_lv_pmos m=1 w=420.00n l=130.00n ng=1 +MP7 Dbbb Dbb VDD VDD sg13_lv_pmos m=1 w=420.00n l=130.00n ng=1 +MP11 net7 net4 VDD VDD sg13_lv_pmos m=1 w=420.00n l=130.00n ng=1 +MP12 net6 clkneg net7 VDD sg13_lv_pmos m=1 w=420.00n l=130.00n ng=1 +MP13 net6 RESET_B VDD VDD sg13_lv_pmos m=1 w=420.00n l=130.00n ng=1 +MP8 clkneg CLK VDD VDD sg13_lv_pmos m=1 w=1.12u l=130.00n ng=1 +MP9 clkpos clkneg VDD VDD sg13_lv_pmos m=1 w=1.12u l=130.00n ng=1 +MP14 net4 net6 VDD VDD sg13_lv_pmos m=1 w=1.000u l=130.00n ng=1 +MP15 net4 clkneg net5 VDD sg13_lv_pmos m=1 w=1.000u l=130.00n ng=1 +MP22 Q net1 VDD VDD sg13_lv_pmos m=1 w=2.24u l=130.00n ng=2 +MP16 net3 net2 VDD VDD sg13_lv_pmos m=1 w=420.00n l=130.00n ng=1 +MP21 net1 net5 VDD VDD sg13_lv_pmos m=1 w=1.000u l=130.00n ng=1 .ENDS ************************************************************************ @@ -1610,52 +1610,52 @@ MP5 net1 net5 VDD VDD sg13_lv_pmos m=1 w=1.000u l=130.00n ng=1 .SUBCKT sg13g2_sdfrbp_1 Q Q_N CLK D RESET_B SCD SCE VDD VSS *.PININFO CLK:I D:I RESET_B:I SCD:I SCE:I Q:O Q_N:O VDD:B VSS:B -MN22 Db SCD net63 VSS sg13_lv_nmos m=1 w=740.00n l=130.00n ng=1 -MN21 Db D net65 VSS sg13_lv_nmos m=1 w=740.00n l=130.00n ng=1 -MN19 SCEb SCE VSS VSS sg13_lv_nmos m=1 w=550.00n l=130.00n ng=1 -MN18 net63 SCE VSS VSS sg13_lv_nmos m=1 w=740.00n l=130.00n ng=1 -MN17 net65 SCEb VSS VSS sg13_lv_nmos m=1 w=740.00n l=130.00n ng=1 -MN23 net13 Db VSS VSS sg13_lv_nmos m=1 w=740.00n l=130.00n ng=1 -MN13 net12 net2 VSS VSS sg13_lv_nmos m=1 w=420.00n l=130.00n ng=1 -MN14 net5 clkneg net12 VSS sg13_lv_nmos m=1 w=420.00n l=130.00n ng=1 -MN15 net2 net5 net11 VSS sg13_lv_nmos m=1 w=420.00n l=130.00n ng=1 -MN16 net11 RESET_B VSS VSS sg13_lv_nmos m=1 w=420.00n l=130.00n ng=1 -MN6 Q_N net5 VSS VSS sg13_lv_nmos m=1 w=740.00n l=130.00n ng=1 -MN0 Dbb net13 net10 VSS sg13_lv_nmos m=1 w=420.00n l=130.00n ng=1 -MN1 net10 RESET_B VSS VSS sg13_lv_nmos m=1 w=420.00n l=130.00n ng=1 -MN7 Dbb clkneg net6 VSS sg13_lv_nmos m=1 w=420.00n l=130.00n ng=1 -MN8 net6 clkpos net9 VSS sg13_lv_nmos m=1 w=420.00n l=130.00n ng=1 -MN9 net9 net4 net8 VSS sg13_lv_nmos m=1 w=420.00n l=130.00n ng=1 -MN10 net8 RESET_B VSS VSS sg13_lv_nmos m=1 w=420.00n l=130.00n ng=1 -MN11 net4 net6 VSS VSS sg13_lv_nmos m=1 w=740.00n l=130.00n ng=1 -MN2 clkneg CLK VSS VSS sg13_lv_nmos m=1 w=740.00n l=130.00n ng=1 -MN12 net4 clkpos net5 VSS sg13_lv_nmos m=1 w=740.00n l=130.00n ng=1 -MN3 clkpos clkneg VSS VSS sg13_lv_nmos m=1 w=740.00n l=130.00n ng=1 -MN4 Q net1 VSS VSS sg13_lv_nmos m=1 w=740.00n l=130.00n ng=1 -MN5 net1 net5 VSS VSS sg13_lv_nmos m=1 w=640.00n l=130.00n ng=1 -MP22 net64 SCE VDD VDD sg13_lv_pmos m=1 w=1.000u l=130.00n ng=1 -MP21 net62 SCEb VDD VDD sg13_lv_pmos m=1 w=1.000u l=130.00n ng=1 -MP20 SCEb SCE VDD VDD sg13_lv_pmos m=1 w=840.00n l=130.00n ng=1 -MP18 Db SCD net62 VDD sg13_lv_pmos m=1 w=1.000u l=130.00n ng=1 -MP17 Db D net64 VDD sg13_lv_pmos m=1 w=1.000u l=130.00n ng=1 -MP23 net13 Db VDD VDD sg13_lv_pmos m=1 w=1.12u l=130.00n ng=1 -MP14 net5 clkpos net3 VDD sg13_lv_pmos m=1 w=420.00n l=130.00n ng=1 -MP15 net2 net5 VDD VDD sg13_lv_pmos m=1 w=420.00n l=130.00n ng=1 -MP16 net2 RESET_B VDD VDD sg13_lv_pmos m=1 w=420.00n l=130.00n ng=1 -MP6 Q_N net5 VDD VDD sg13_lv_pmos m=1 w=1.12u l=130.00n ng=1 -MP7 Dbb clkpos net6 VDD sg13_lv_pmos m=1 w=420.00n l=130.00n ng=1 -MP0 Dbb RESET_B VDD VDD sg13_lv_pmos m=1 w=420.00n l=130.00n ng=1 -MP1 Dbb net13 VDD VDD sg13_lv_pmos m=1 w=420.00n l=130.00n ng=1 -MP8 net7 net4 VDD VDD sg13_lv_pmos m=1 w=420.00n l=130.00n ng=1 -MP9 net6 clkneg net7 VDD sg13_lv_pmos m=1 w=420.00n l=130.00n ng=1 -MP10 net6 RESET_B VDD VDD sg13_lv_pmos m=1 w=420.00n l=130.00n ng=1 -MP2 clkneg CLK VDD VDD sg13_lv_pmos m=1 w=1.12u l=130.00n ng=1 -MP3 clkpos clkneg VDD VDD sg13_lv_pmos m=1 w=1.12u l=130.00n ng=1 -MP11 net4 net6 VDD VDD sg13_lv_pmos m=1 w=1.000u l=130.00n ng=1 -MP12 net4 clkneg net5 VDD sg13_lv_pmos m=1 w=1.000u l=130.00n ng=1 -MP4 Q net1 VDD VDD sg13_lv_pmos m=1 w=1.12u l=130.00n ng=1 -MP13 net3 net2 VDD VDD sg13_lv_pmos m=1 w=420.00n l=130.00n ng=1 -MP5 net1 net5 VDD VDD sg13_lv_pmos m=1 w=1.000u l=130.00n ng=1 +MN3 Db SCD net63 VSS sg13_lv_nmos m=1 w=740.00n l=130.00n ng=1 +MN1 Db D net65 VSS sg13_lv_nmos m=1 w=740.00n l=130.00n ng=1 +MN0 SCEb SCE VSS VSS sg13_lv_nmos m=1 w=550.00n l=130.00n ng=1 +MN4 net63 SCE VSS VSS sg13_lv_nmos m=1 w=740.00n l=130.00n ng=1 +MN2 net65 SCEb VSS VSS sg13_lv_nmos m=1 w=740.00n l=130.00n ng=1 +MN5 net13 Db VSS VSS sg13_lv_nmos m=1 w=740.00n l=130.00n ng=1 +MN17 net12 net2 VSS VSS sg13_lv_nmos m=1 w=420.00n l=130.00n ng=1 +MN16 net5 clkneg net12 VSS sg13_lv_nmos m=1 w=420.00n l=130.00n ng=1 +MN18 net2 net5 net11 VSS sg13_lv_nmos m=1 w=420.00n l=130.00n ng=1 +MN19 net11 RESET_B VSS VSS sg13_lv_nmos m=1 w=420.00n l=130.00n ng=1 +MN20 Q_N net5 VSS VSS sg13_lv_nmos m=1 w=740.00n l=130.00n ng=1 +MN6 Dbb net13 net10 VSS sg13_lv_nmos m=1 w=420.00n l=130.00n ng=1 +MN7 net10 RESET_B VSS VSS sg13_lv_nmos m=1 w=420.00n l=130.00n ng=1 +MN10 Dbb clkneg net6 VSS sg13_lv_nmos m=1 w=420.00n l=130.00n ng=1 +MN11 net6 clkpos net9 VSS sg13_lv_nmos m=1 w=420.00n l=130.00n ng=1 +MN12 net9 net4 net8 VSS sg13_lv_nmos m=1 w=420.00n l=130.00n ng=1 +MN13 net8 RESET_B VSS VSS sg13_lv_nmos m=1 w=420.00n l=130.00n ng=1 +MN14 net4 net6 VSS VSS sg13_lv_nmos m=1 w=740.00n l=130.00n ng=1 +MN8 clkneg CLK VSS VSS sg13_lv_nmos m=1 w=740.00n l=130.00n ng=1 +MN15 net4 clkpos net5 VSS sg13_lv_nmos m=1 w=740.00n l=130.00n ng=1 +MN9 clkpos clkneg VSS VSS sg13_lv_nmos m=1 w=740.00n l=130.00n ng=1 +MN22 Q net1 VSS VSS sg13_lv_nmos m=1 w=740.00n l=130.00n ng=1 +MN21 net1 net5 VSS VSS sg13_lv_nmos m=1 w=640.00n l=130.00n ng=1 +MP1 net64 SCE VDD VDD sg13_lv_pmos m=1 w=1.000u l=130.00n ng=1 +MP3 net62 SCEb VDD VDD sg13_lv_pmos m=1 w=1.000u l=130.00n ng=1 +MP0 SCEb SCE VDD VDD sg13_lv_pmos m=1 w=840.00n l=130.00n ng=1 +MP4 Db SCD net62 VDD sg13_lv_pmos m=1 w=1.000u l=130.00n ng=1 +MP2 Db D net64 VDD sg13_lv_pmos m=1 w=1.000u l=130.00n ng=1 +MP5 net13 Db VDD VDD sg13_lv_pmos m=1 w=1.12u l=130.00n ng=1 +MP17 net5 clkpos net3 VDD sg13_lv_pmos m=1 w=420.00n l=130.00n ng=1 +MP18 net2 net5 VDD VDD sg13_lv_pmos m=1 w=420.00n l=130.00n ng=1 +MP19 net2 RESET_B VDD VDD sg13_lv_pmos m=1 w=420.00n l=130.00n ng=1 +MP20 Q_N net5 VDD VDD sg13_lv_pmos m=1 w=1.12u l=130.00n ng=1 +MP10 Dbb clkpos net6 VDD sg13_lv_pmos m=1 w=420.00n l=130.00n ng=1 +MP6 Dbb RESET_B VDD VDD sg13_lv_pmos m=1 w=420.00n l=130.00n ng=1 +MP7 Dbb net13 VDD VDD sg13_lv_pmos m=1 w=420.00n l=130.00n ng=1 +MP11 net7 net4 VDD VDD sg13_lv_pmos m=1 w=420.00n l=130.00n ng=1 +MP12 net6 clkneg net7 VDD sg13_lv_pmos m=1 w=420.00n l=130.00n ng=1 +MP13 net6 RESET_B VDD VDD sg13_lv_pmos m=1 w=420.00n l=130.00n ng=1 +MP8 clkneg CLK VDD VDD sg13_lv_pmos m=1 w=1.12u l=130.00n ng=1 +MP9 clkpos clkneg VDD VDD sg13_lv_pmos m=1 w=1.12u l=130.00n ng=1 +MP14 net4 net6 VDD VDD sg13_lv_pmos m=1 w=1.000u l=130.00n ng=1 +MP15 net4 clkneg net5 VDD sg13_lv_pmos m=1 w=1.000u l=130.00n ng=1 +MP22 Q net1 VDD VDD sg13_lv_pmos m=1 w=1.12u l=130.00n ng=1 +MP16 net3 net2 VDD VDD sg13_lv_pmos m=1 w=420.00n l=130.00n ng=1 +MP21 net1 net5 VDD VDD sg13_lv_pmos m=1 w=1.000u l=130.00n ng=1 .ENDS ************************************************************************ @@ -1666,38 +1666,38 @@ MP5 net1 net5 VDD VDD sg13_lv_pmos m=1 w=1.000u l=130.00n ng=1 .SUBCKT sg13g2_dfrbpq_2 Q CLK D RESET_B VDD VSS *.PININFO CLK:I D:I RESET_B:I Q:O VDD:B VSS:B -MN13 net12 net2 VSS VSS sg13_lv_nmos m=1 w=420.00n l=130.00n ng=1 -MN14 net5 clkneg net12 VSS sg13_lv_nmos m=1 w=420.00n l=130.00n ng=1 -MN15 net2 net5 net11 VSS sg13_lv_nmos m=1 w=420.00n l=130.00n ng=1 -MN16 net11 RESET_B VSS VSS sg13_lv_nmos m=1 w=420.00n l=130.00n ng=1 +MN11 net12 net2 VSS VSS sg13_lv_nmos m=1 w=420.00n l=130.00n ng=1 +MN10 net5 clkneg net12 VSS sg13_lv_nmos m=1 w=420.00n l=130.00n ng=1 +MN12 net2 net5 net11 VSS sg13_lv_nmos m=1 w=420.00n l=130.00n ng=1 +MN13 net11 RESET_B VSS VSS sg13_lv_nmos m=1 w=420.00n l=130.00n ng=1 MN0 Db D net10 VSS sg13_lv_nmos m=1 w=420.00n l=130.00n ng=1 MN1 net10 RESET_B VSS VSS sg13_lv_nmos m=1 w=420.00n l=130.00n ng=1 -MN7 Db clkneg net6 VSS sg13_lv_nmos m=1 w=420.00n l=130.00n ng=1 -MN8 net6 clkpos net9 VSS sg13_lv_nmos m=1 w=420.00n l=130.00n ng=1 -MN9 net9 net4 net8 VSS sg13_lv_nmos m=1 w=420.00n l=130.00n ng=1 -MN10 net8 RESET_B VSS VSS sg13_lv_nmos m=1 w=420.00n l=130.00n ng=1 -MN11 net4 net6 VSS VSS sg13_lv_nmos m=1 w=740.00n l=130.00n ng=1 +MN4 Db clkneg net6 VSS sg13_lv_nmos m=1 w=420.00n l=130.00n ng=1 +MN5 net6 clkpos net9 VSS sg13_lv_nmos m=1 w=420.00n l=130.00n ng=1 +MN6 net9 net4 net8 VSS sg13_lv_nmos m=1 w=420.00n l=130.00n ng=1 +MN7 net8 RESET_B VSS VSS sg13_lv_nmos m=1 w=420.00n l=130.00n ng=1 +MN8 net4 net6 VSS VSS sg13_lv_nmos m=1 w=740.00n l=130.00n ng=1 MN2 clkneg CLK VSS VSS sg13_lv_nmos m=1 w=740.00n l=130.00n ng=1 -MN12 net4 clkpos net5 VSS sg13_lv_nmos m=1 w=740.00n l=130.00n ng=1 +MN9 net4 clkpos net5 VSS sg13_lv_nmos m=1 w=740.00n l=130.00n ng=1 MN3 clkpos clkneg VSS VSS sg13_lv_nmos m=1 w=740.00n l=130.00n ng=1 -MN4 Q net1 VSS VSS sg13_lv_nmos m=1 w=1.48u l=130.00n ng=2 -MN5 net1 net5 VSS VSS sg13_lv_nmos m=1 w=640.00n l=130.00n ng=1 -MP14 net5 clkpos net3 VDD sg13_lv_pmos m=1 w=420.00n l=130.00n ng=1 -MP15 net2 net5 VDD VDD sg13_lv_pmos m=1 w=420.00n l=130.00n ng=1 -MP16 net2 RESET_B VDD VDD sg13_lv_pmos m=1 w=420.00n l=130.00n ng=1 -MP7 Db clkpos net6 VDD sg13_lv_pmos m=1 w=420.00n l=130.00n ng=1 +MN15 Q net1 VSS VSS sg13_lv_nmos m=1 w=1.48u l=130.00n ng=2 +MN14 net1 net5 VSS VSS sg13_lv_nmos m=1 w=640.00n l=130.00n ng=1 +MP11 net5 clkpos net3 VDD sg13_lv_pmos m=1 w=420.00n l=130.00n ng=1 +MP12 net2 net5 VDD VDD sg13_lv_pmos m=1 w=420.00n l=130.00n ng=1 +MP13 net2 RESET_B VDD VDD sg13_lv_pmos m=1 w=420.00n l=130.00n ng=1 +MP4 Db clkpos net6 VDD sg13_lv_pmos m=1 w=420.00n l=130.00n ng=1 MP0 Db RESET_B VDD VDD sg13_lv_pmos m=1 w=420.00n l=130.00n ng=1 MP1 Db D VDD VDD sg13_lv_pmos m=1 w=420.00n l=130.00n ng=1 -MP8 net7 net4 VDD VDD sg13_lv_pmos m=1 w=420.00n l=130.00n ng=1 -MP9 net6 clkneg net7 VDD sg13_lv_pmos m=1 w=420.00n l=130.00n ng=1 -MP10 net6 RESET_B VDD VDD sg13_lv_pmos m=1 w=420.00n l=130.00n ng=1 +MP5 net7 net4 VDD VDD sg13_lv_pmos m=1 w=420.00n l=130.00n ng=1 +MP6 net6 clkneg net7 VDD sg13_lv_pmos m=1 w=420.00n l=130.00n ng=1 +MP7 net6 RESET_B VDD VDD sg13_lv_pmos m=1 w=420.00n l=130.00n ng=1 MP2 clkneg CLK VDD VDD sg13_lv_pmos m=1 w=1.12u l=130.00n ng=1 MP3 clkpos clkneg VDD VDD sg13_lv_pmos m=1 w=1.12u l=130.00n ng=1 -MP11 net4 net6 VDD VDD sg13_lv_pmos m=1 w=1.000u l=130.00n ng=1 -MP12 net4 clkneg net5 VDD sg13_lv_pmos m=1 w=1.000u l=130.00n ng=1 -MP4 Q net1 VDD VDD sg13_lv_pmos m=1 w=2.24u l=130.00n ng=2 -MP13 net3 net2 VDD VDD sg13_lv_pmos m=1 w=420.00n l=130.00n ng=1 -MP5 net1 net5 VDD VDD sg13_lv_pmos m=1 w=1.000u l=130.00n ng=1 +MP8 net4 net6 VDD VDD sg13_lv_pmos m=1 w=1.000u l=130.00n ng=1 +MP9 net4 clkneg net5 VDD sg13_lv_pmos m=1 w=1.000u l=130.00n ng=1 +MP15 Q net1 VDD VDD sg13_lv_pmos m=1 w=2.24u l=130.00n ng=2 +MP10 net3 net2 VDD VDD sg13_lv_pmos m=1 w=420.00n l=130.00n ng=1 +MP14 net1 net5 VDD VDD sg13_lv_pmos m=1 w=1.000u l=130.00n ng=1 .ENDS ************************************************************************ @@ -1708,38 +1708,38 @@ MP5 net1 net5 VDD VDD sg13_lv_pmos m=1 w=1.000u l=130.00n ng=1 .SUBCKT sg13g2_dfrbpq_1 Q CLK D RESET_B VDD VSS *.PININFO CLK:I D:I RESET_B:I Q:O VDD:B VSS:B -MN13 net12 net2 VSS VSS sg13_lv_nmos m=1 w=420.00n l=130.00n ng=1 -MN14 net5 clkneg net12 VSS sg13_lv_nmos m=1 w=420.00n l=130.00n ng=1 -MN15 net2 net5 net11 VSS sg13_lv_nmos m=1 w=420.00n l=130.00n ng=1 -MN16 net11 RESET_B VSS VSS sg13_lv_nmos m=1 w=420.00n l=130.00n ng=1 +MN11 net12 net2 VSS VSS sg13_lv_nmos m=1 w=420.00n l=130.00n ng=1 +MN10 net5 clkneg net12 VSS sg13_lv_nmos m=1 w=420.00n l=130.00n ng=1 +MN12 net2 net5 net11 VSS sg13_lv_nmos m=1 w=420.00n l=130.00n ng=1 +MN13 net11 RESET_B VSS VSS sg13_lv_nmos m=1 w=420.00n l=130.00n ng=1 MN0 Db D net10 VSS sg13_lv_nmos m=1 w=420.00n l=130.00n ng=1 MN1 net10 RESET_B VSS VSS sg13_lv_nmos m=1 w=420.00n l=130.00n ng=1 -MN7 Db clkneg net6 VSS sg13_lv_nmos m=1 w=420.00n l=130.00n ng=1 -MN8 net6 clkpos net9 VSS sg13_lv_nmos m=1 w=420.00n l=130.00n ng=1 -MN9 net9 net4 net8 VSS sg13_lv_nmos m=1 w=420.00n l=130.00n ng=1 -MN10 net8 RESET_B VSS VSS sg13_lv_nmos m=1 w=420.00n l=130.00n ng=1 -MN11 net4 net6 VSS VSS sg13_lv_nmos m=1 w=740.00n l=130.00n ng=1 +MN4 Db clkneg net6 VSS sg13_lv_nmos m=1 w=420.00n l=130.00n ng=1 +MN5 net6 clkpos net9 VSS sg13_lv_nmos m=1 w=420.00n l=130.00n ng=1 +MN6 net9 net4 net8 VSS sg13_lv_nmos m=1 w=420.00n l=130.00n ng=1 +MN7 net8 RESET_B VSS VSS sg13_lv_nmos m=1 w=420.00n l=130.00n ng=1 +MN8 net4 net6 VSS VSS sg13_lv_nmos m=1 w=740.00n l=130.00n ng=1 MN2 clkneg CLK VSS VSS sg13_lv_nmos m=1 w=740.00n l=130.00n ng=1 -MN12 net4 clkpos net5 VSS sg13_lv_nmos m=1 w=740.00n l=130.00n ng=1 +MN9 net4 clkpos net5 VSS sg13_lv_nmos m=1 w=740.00n l=130.00n ng=1 MN3 clkpos clkneg VSS VSS sg13_lv_nmos m=1 w=740.00n l=130.00n ng=1 -MN4 Q net1 VSS VSS sg13_lv_nmos m=1 w=740.00n l=130.00n ng=1 -MN5 net1 net5 VSS VSS sg13_lv_nmos m=1 w=740.00n l=130.00n ng=1 -MP14 net5 clkpos net3 VDD sg13_lv_pmos m=1 w=420.00n l=130.00n ng=1 -MP15 net2 net5 VDD VDD sg13_lv_pmos m=1 w=420.00n l=130.00n ng=1 -MP16 net2 RESET_B VDD VDD sg13_lv_pmos m=1 w=420.00n l=130.00n ng=1 -MP7 Db clkpos net6 VDD sg13_lv_pmos m=1 w=420.00n l=130.00n ng=1 +MN15 Q net1 VSS VSS sg13_lv_nmos m=1 w=740.00n l=130.00n ng=1 +MN14 net1 net5 VSS VSS sg13_lv_nmos m=1 w=740.00n l=130.00n ng=1 +MP11 net5 clkpos net3 VDD sg13_lv_pmos m=1 w=420.00n l=130.00n ng=1 +MP12 net2 net5 VDD VDD sg13_lv_pmos m=1 w=420.00n l=130.00n ng=1 +MP13 net2 RESET_B VDD VDD sg13_lv_pmos m=1 w=420.00n l=130.00n ng=1 +MP4 Db clkpos net6 VDD sg13_lv_pmos m=1 w=420.00n l=130.00n ng=1 MP0 Db RESET_B VDD VDD sg13_lv_pmos m=1 w=420.00n l=130.00n ng=1 MP1 Db D VDD VDD sg13_lv_pmos m=1 w=420.00n l=130.00n ng=1 -MP8 net7 net4 VDD VDD sg13_lv_pmos m=1 w=420.00n l=130.00n ng=1 -MP9 net6 clkneg net7 VDD sg13_lv_pmos m=1 w=420.00n l=130.00n ng=1 -MP10 net6 RESET_B VDD VDD sg13_lv_pmos m=1 w=420.00n l=130.00n ng=1 +MP5 net7 net4 VDD VDD sg13_lv_pmos m=1 w=420.00n l=130.00n ng=1 +MP6 net6 clkneg net7 VDD sg13_lv_pmos m=1 w=420.00n l=130.00n ng=1 +MP7 net6 RESET_B VDD VDD sg13_lv_pmos m=1 w=420.00n l=130.00n ng=1 MP2 clkneg CLK VDD VDD sg13_lv_pmos m=1 w=1.12u l=130.00n ng=1 MP3 clkpos clkneg VDD VDD sg13_lv_pmos m=1 w=1.12u l=130.00n ng=1 -MP11 net4 net6 VDD VDD sg13_lv_pmos m=1 w=1.000u l=130.00n ng=1 -MP12 net4 clkneg net5 VDD sg13_lv_pmos m=1 w=1.000u l=130.00n ng=1 -MP4 Q net1 VDD VDD sg13_lv_pmos m=1 w=1.12u l=130.00n ng=1 -MP13 net3 net2 VDD VDD sg13_lv_pmos m=1 w=420.00n l=130.00n ng=1 -MP5 net1 net5 VDD VDD sg13_lv_pmos m=1 w=1.12u l=130.00n ng=1 +MP8 net4 net6 VDD VDD sg13_lv_pmos m=1 w=1.000u l=130.00n ng=1 +MP9 net4 clkneg net5 VDD sg13_lv_pmos m=1 w=1.000u l=130.00n ng=1 +MP15 Q net1 VDD VDD sg13_lv_pmos m=1 w=1.12u l=130.00n ng=1 +MP10 net3 net2 VDD VDD sg13_lv_pmos m=1 w=420.00n l=130.00n ng=1 +MP14 net1 net5 VDD VDD sg13_lv_pmos m=1 w=1.12u l=130.00n ng=1 .ENDS ************************************************************************ diff --git a/flow/platforms/ihp-sg13g2/gds/RM_IHPSG13_1P_1024x16_c2_bm_bist.gds b/flow/platforms/ihp-sg13g2/gds/RM_IHPSG13_1P_1024x16_c2_bm_bist.gds index 3a7ed84817..093671d506 100644 Binary files a/flow/platforms/ihp-sg13g2/gds/RM_IHPSG13_1P_1024x16_c2_bm_bist.gds and b/flow/platforms/ihp-sg13g2/gds/RM_IHPSG13_1P_1024x16_c2_bm_bist.gds differ diff --git a/flow/platforms/ihp-sg13g2/gds/RM_IHPSG13_1P_1024x32_c2_bm_bist.gds b/flow/platforms/ihp-sg13g2/gds/RM_IHPSG13_1P_1024x32_c2_bm_bist.gds new file mode 100644 index 0000000000..e316ecd5a3 Binary files /dev/null and b/flow/platforms/ihp-sg13g2/gds/RM_IHPSG13_1P_1024x32_c2_bm_bist.gds differ diff --git a/flow/platforms/ihp-sg13g2/gds/RM_IHPSG13_1P_1024x64_c2_bm_bist.gds b/flow/platforms/ihp-sg13g2/gds/RM_IHPSG13_1P_1024x64_c2_bm_bist.gds index 04dbc2e164..201fbfc664 100644 Binary files a/flow/platforms/ihp-sg13g2/gds/RM_IHPSG13_1P_1024x64_c2_bm_bist.gds and b/flow/platforms/ihp-sg13g2/gds/RM_IHPSG13_1P_1024x64_c2_bm_bist.gds differ diff --git a/flow/platforms/ihp-sg13g2/gds/RM_IHPSG13_1P_1024x8_c2_bm_bist.gds b/flow/platforms/ihp-sg13g2/gds/RM_IHPSG13_1P_1024x8_c2_bm_bist.gds index 09642aa858..a726656e6d 100644 Binary files a/flow/platforms/ihp-sg13g2/gds/RM_IHPSG13_1P_1024x8_c2_bm_bist.gds and b/flow/platforms/ihp-sg13g2/gds/RM_IHPSG13_1P_1024x8_c2_bm_bist.gds differ diff --git a/flow/platforms/ihp-sg13g2/gds/RM_IHPSG13_1P_2048x64_c2_bm_bist.gds b/flow/platforms/ihp-sg13g2/gds/RM_IHPSG13_1P_2048x64_c2_bm_bist.gds index 7b0c7dadf8..3b70b484ca 100644 Binary files a/flow/platforms/ihp-sg13g2/gds/RM_IHPSG13_1P_2048x64_c2_bm_bist.gds and b/flow/platforms/ihp-sg13g2/gds/RM_IHPSG13_1P_2048x64_c2_bm_bist.gds differ diff --git a/flow/platforms/ihp-sg13g2/gds/RM_IHPSG13_1P_256x16_c2_bm_bist.gds b/flow/platforms/ihp-sg13g2/gds/RM_IHPSG13_1P_256x16_c2_bm_bist.gds new file mode 100644 index 0000000000..77d647ddd9 Binary files /dev/null and b/flow/platforms/ihp-sg13g2/gds/RM_IHPSG13_1P_256x16_c2_bm_bist.gds differ diff --git a/flow/platforms/ihp-sg13g2/gds/RM_IHPSG13_1P_256x32_c2_bm_bist.gds b/flow/platforms/ihp-sg13g2/gds/RM_IHPSG13_1P_256x32_c2_bm_bist.gds new file mode 100644 index 0000000000..2dc8474880 Binary files /dev/null and b/flow/platforms/ihp-sg13g2/gds/RM_IHPSG13_1P_256x32_c2_bm_bist.gds differ diff --git a/flow/platforms/ihp-sg13g2/gds/RM_IHPSG13_1P_256x48_c2_bm_bist.gds b/flow/platforms/ihp-sg13g2/gds/RM_IHPSG13_1P_256x48_c2_bm_bist.gds index 3d2e786aac..dd36459b4e 100644 Binary files a/flow/platforms/ihp-sg13g2/gds/RM_IHPSG13_1P_256x48_c2_bm_bist.gds and b/flow/platforms/ihp-sg13g2/gds/RM_IHPSG13_1P_256x48_c2_bm_bist.gds differ diff --git a/flow/platforms/ihp-sg13g2/gds/RM_IHPSG13_1P_256x64_c2_bm_bist.gds b/flow/platforms/ihp-sg13g2/gds/RM_IHPSG13_1P_256x64_c2_bm_bist.gds index 25d743fa42..e684b005c9 100644 Binary files a/flow/platforms/ihp-sg13g2/gds/RM_IHPSG13_1P_256x64_c2_bm_bist.gds and b/flow/platforms/ihp-sg13g2/gds/RM_IHPSG13_1P_256x64_c2_bm_bist.gds differ diff --git a/flow/platforms/ihp-sg13g2/gds/RM_IHPSG13_1P_256x8_c3_bm_bist.gds b/flow/platforms/ihp-sg13g2/gds/RM_IHPSG13_1P_256x8_c3_bm_bist.gds new file mode 100644 index 0000000000..2cc6dbc4ad Binary files /dev/null and b/flow/platforms/ihp-sg13g2/gds/RM_IHPSG13_1P_256x8_c3_bm_bist.gds differ diff --git a/flow/platforms/ihp-sg13g2/gds/RM_IHPSG13_1P_4096x16_c3_bm_bist.gds b/flow/platforms/ihp-sg13g2/gds/RM_IHPSG13_1P_4096x16_c3_bm_bist.gds index 5274f684cc..ca1f1ec1e9 100644 Binary files a/flow/platforms/ihp-sg13g2/gds/RM_IHPSG13_1P_4096x16_c3_bm_bist.gds and b/flow/platforms/ihp-sg13g2/gds/RM_IHPSG13_1P_4096x16_c3_bm_bist.gds differ diff --git a/flow/platforms/ihp-sg13g2/gds/RM_IHPSG13_1P_4096x8_c3_bm_bist.gds b/flow/platforms/ihp-sg13g2/gds/RM_IHPSG13_1P_4096x8_c3_bm_bist.gds index 049382f624..10ec7ec43a 100644 Binary files a/flow/platforms/ihp-sg13g2/gds/RM_IHPSG13_1P_4096x8_c3_bm_bist.gds and b/flow/platforms/ihp-sg13g2/gds/RM_IHPSG13_1P_4096x8_c3_bm_bist.gds differ diff --git a/flow/platforms/ihp-sg13g2/gds/RM_IHPSG13_1P_512x16_c2_bm_bist.gds b/flow/platforms/ihp-sg13g2/gds/RM_IHPSG13_1P_512x16_c2_bm_bist.gds new file mode 100644 index 0000000000..f43f6a972a Binary files /dev/null and b/flow/platforms/ihp-sg13g2/gds/RM_IHPSG13_1P_512x16_c2_bm_bist.gds differ diff --git a/flow/platforms/ihp-sg13g2/gds/RM_IHPSG13_1P_512x32_c2_bm_bist.gds b/flow/platforms/ihp-sg13g2/gds/RM_IHPSG13_1P_512x32_c2_bm_bist.gds new file mode 100644 index 0000000000..465394fecb Binary files /dev/null and b/flow/platforms/ihp-sg13g2/gds/RM_IHPSG13_1P_512x32_c2_bm_bist.gds differ diff --git a/flow/platforms/ihp-sg13g2/gds/RM_IHPSG13_1P_512x64_c2_bm_bist.gds b/flow/platforms/ihp-sg13g2/gds/RM_IHPSG13_1P_512x64_c2_bm_bist.gds index aa41dec684..eb089ec553 100644 Binary files a/flow/platforms/ihp-sg13g2/gds/RM_IHPSG13_1P_512x64_c2_bm_bist.gds and b/flow/platforms/ihp-sg13g2/gds/RM_IHPSG13_1P_512x64_c2_bm_bist.gds differ diff --git a/flow/platforms/ihp-sg13g2/gds/RM_IHPSG13_1P_512x8_c3_bm_bist.gds b/flow/platforms/ihp-sg13g2/gds/RM_IHPSG13_1P_512x8_c3_bm_bist.gds new file mode 100644 index 0000000000..bc35bc6efa Binary files /dev/null and b/flow/platforms/ihp-sg13g2/gds/RM_IHPSG13_1P_512x8_c3_bm_bist.gds differ diff --git a/flow/platforms/ihp-sg13g2/gds/RM_IHPSG13_1P_64x64_c2_bm_bist.gds b/flow/platforms/ihp-sg13g2/gds/RM_IHPSG13_1P_64x64_c2_bm_bist.gds index 9023a7da7b..87c1e73543 100644 Binary files a/flow/platforms/ihp-sg13g2/gds/RM_IHPSG13_1P_64x64_c2_bm_bist.gds and b/flow/platforms/ihp-sg13g2/gds/RM_IHPSG13_1P_64x64_c2_bm_bist.gds differ diff --git a/flow/platforms/ihp-sg13g2/gds/RM_IHPSG13_1P_8192x32_c4.gds b/flow/platforms/ihp-sg13g2/gds/RM_IHPSG13_1P_8192x32_c4.gds new file mode 100644 index 0000000000..7c3a822dfd Binary files /dev/null and b/flow/platforms/ihp-sg13g2/gds/RM_IHPSG13_1P_8192x32_c4.gds differ diff --git a/flow/platforms/ihp-sg13g2/gds/RM_IHPSG13_2P_1024x16_c2_bm_bist.gds b/flow/platforms/ihp-sg13g2/gds/RM_IHPSG13_2P_1024x16_c2_bm_bist.gds new file mode 100644 index 0000000000..22ede7571e Binary files /dev/null and b/flow/platforms/ihp-sg13g2/gds/RM_IHPSG13_2P_1024x16_c2_bm_bist.gds differ diff --git a/flow/platforms/ihp-sg13g2/gds/RM_IHPSG13_2P_1024x32_c2_bm_bist.gds b/flow/platforms/ihp-sg13g2/gds/RM_IHPSG13_2P_1024x32_c2_bm_bist.gds new file mode 100644 index 0000000000..03f216c3b3 Binary files /dev/null and b/flow/platforms/ihp-sg13g2/gds/RM_IHPSG13_2P_1024x32_c2_bm_bist.gds differ diff --git a/flow/platforms/ihp-sg13g2/gds/RM_IHPSG13_2P_256x16_c2_bm_bist.gds b/flow/platforms/ihp-sg13g2/gds/RM_IHPSG13_2P_256x16_c2_bm_bist.gds new file mode 100644 index 0000000000..6c7273d8b9 Binary files /dev/null and b/flow/platforms/ihp-sg13g2/gds/RM_IHPSG13_2P_256x16_c2_bm_bist.gds differ diff --git a/flow/platforms/ihp-sg13g2/gds/RM_IHPSG13_2P_256x32_c2_bm_bist.gds b/flow/platforms/ihp-sg13g2/gds/RM_IHPSG13_2P_256x32_c2_bm_bist.gds new file mode 100644 index 0000000000..c65ddcae9d Binary files /dev/null and b/flow/platforms/ihp-sg13g2/gds/RM_IHPSG13_2P_256x32_c2_bm_bist.gds differ diff --git a/flow/platforms/ihp-sg13g2/gds/RM_IHPSG13_2P_256x8_c2_bm_bist.gds b/flow/platforms/ihp-sg13g2/gds/RM_IHPSG13_2P_256x8_c2_bm_bist.gds new file mode 100644 index 0000000000..0f385a11be Binary files /dev/null and b/flow/platforms/ihp-sg13g2/gds/RM_IHPSG13_2P_256x8_c2_bm_bist.gds differ diff --git a/flow/platforms/ihp-sg13g2/gds/RM_IHPSG13_2P_512x16_c2_bm_bist.gds b/flow/platforms/ihp-sg13g2/gds/RM_IHPSG13_2P_512x16_c2_bm_bist.gds new file mode 100644 index 0000000000..197ecbc61b Binary files /dev/null and b/flow/platforms/ihp-sg13g2/gds/RM_IHPSG13_2P_512x16_c2_bm_bist.gds differ diff --git a/flow/platforms/ihp-sg13g2/gds/RM_IHPSG13_2P_512x32_c2_bm_bist.gds b/flow/platforms/ihp-sg13g2/gds/RM_IHPSG13_2P_512x32_c2_bm_bist.gds new file mode 100644 index 0000000000..a9c02811f8 Binary files /dev/null and b/flow/platforms/ihp-sg13g2/gds/RM_IHPSG13_2P_512x32_c2_bm_bist.gds differ diff --git a/flow/platforms/ihp-sg13g2/gds/RM_IHPSG13_2P_512x8_c2_bm_bist.gds b/flow/platforms/ihp-sg13g2/gds/RM_IHPSG13_2P_512x8_c2_bm_bist.gds new file mode 100644 index 0000000000..4faf0bc3b1 Binary files /dev/null and b/flow/platforms/ihp-sg13g2/gds/RM_IHPSG13_2P_512x8_c2_bm_bist.gds differ diff --git a/flow/platforms/ihp-sg13g2/gds/RM_IHPSG13_2P_64x32_c2.gds b/flow/platforms/ihp-sg13g2/gds/RM_IHPSG13_2P_64x32_c2.gds new file mode 100644 index 0000000000..292a855d2b Binary files /dev/null and b/flow/platforms/ihp-sg13g2/gds/RM_IHPSG13_2P_64x32_c2.gds differ diff --git a/flow/platforms/ihp-sg13g2/gds/sg13g2_io.gds b/flow/platforms/ihp-sg13g2/gds/sg13g2_io.gds index 6b9cf6fd11..e2ec374e7e 100644 Binary files a/flow/platforms/ihp-sg13g2/gds/sg13g2_io.gds and b/flow/platforms/ihp-sg13g2/gds/sg13g2_io.gds differ diff --git a/flow/platforms/ihp-sg13g2/lef/RM_IHPSG13_1P_1024x32_c2_bm_bist.lef b/flow/platforms/ihp-sg13g2/lef/RM_IHPSG13_1P_1024x32_c2_bm_bist.lef new file mode 100644 index 0000000000..0b75577755 --- /dev/null +++ b/flow/platforms/ihp-sg13g2/lef/RM_IHPSG13_1P_1024x32_c2_bm_bist.lef @@ -0,0 +1,4308 @@ +# ------------------------------------------------------ +# +# Copyright 2025 IHP PDK Authors +# +# Licensed under the Apache License, Version 2.0 (the "License"); +# you may not use this file except in compliance with the License. +# You may obtain a copy of the License at +# +# https://www.apache.org/licenses/LICENSE-2.0 +# +# Unless required by applicable law or agreed to in writing, software +# distributed under the License is distributed on an "AS IS" BASIS, +# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +# See the License for the specific language governing permissions and +# limitations under the License. +# +# Generated on Thu Aug 21 20:48:28 2025 +# +# ------------------------------------------------------ +VERSION 5.7 ; +BUSBITCHARS "[]" ; +DIVIDERCHAR "/" ; + +MACRO RM_IHPSG13_1P_1024x32_c2_bm_bist + CLASS BLOCK ; + ORIGIN 0 0 ; + FOREIGN RM_IHPSG13_1P_1024x32_c2_bm_bist 0 0 ; + SIZE 416.64 BY 336.46 ; + SYMMETRY X Y R90 ; + PIN A_DIN[16] + DIRECTION INPUT ; + USE SIGNAL ; + ANTENNAPARTIALMETALAREA 1.794 LAYER Metal2 ; + ANTENNAMODEL OXIDE1 ; + ANTENNAGATEAREA 0.20085 LAYER Metal2 ; + ANTENNAMAXAREACAR 9.838188 LAYER Metal2 ; + PORT + LAYER Metal2 ; + RECT 244.49 0 244.75 0.26 ; + END + END A_DIN[16] + PIN A_DIN[15] + DIRECTION INPUT ; + USE SIGNAL ; + ANTENNAPARTIALMETALAREA 1.794 LAYER Metal2 ; + ANTENNAMODEL OXIDE1 ; + ANTENNAGATEAREA 0.20085 LAYER Metal2 ; + ANTENNAMAXAREACAR 9.838188 LAYER Metal2 ; + PORT + LAYER Metal2 ; + RECT 171.89 0 172.15 0.26 ; + END + END A_DIN[15] + PIN A_BIST_DIN[16] + DIRECTION INPUT ; + USE SIGNAL ; + ANTENNAPARTIALMETALAREA 1.6263 LAYER Metal2 ; + ANTENNAMODEL OXIDE1 ; + ANTENNAGATEAREA 0.20085 LAYER Metal2 ; + ANTENNAMAXAREACAR 9.365945 LAYER Metal2 ; + PORT + LAYER Metal2 ; + RECT 243.635 0 243.895 0.26 ; + END + END A_BIST_DIN[16] + PIN A_BIST_DIN[15] + DIRECTION INPUT ; + USE SIGNAL ; + ANTENNAPARTIALMETALAREA 1.6263 LAYER Metal2 ; + ANTENNAMODEL OXIDE1 ; + ANTENNAGATEAREA 0.20085 LAYER Metal2 ; + ANTENNAMAXAREACAR 9.365945 LAYER Metal2 ; + PORT + LAYER Metal2 ; + RECT 172.745 0 173.005 0.26 ; + END + END A_BIST_DIN[15] + PIN A_BM[16] + DIRECTION INPUT ; + USE SIGNAL ; + ANTENNAPARTIALMETALAREA 0.7215 LAYER Metal2 ; + ANTENNAMODEL OXIDE1 ; + ANTENNAGATEAREA 0.20085 LAYER Metal2 ; + ANTENNAMAXAREACAR 4.498382 LAYER Metal2 ; + PORT + LAYER Metal2 ; + RECT 236.65 0 236.91 0.26 ; + END + END A_BM[16] + PIN A_BM[15] + DIRECTION INPUT ; + USE SIGNAL ; + ANTENNAPARTIALMETALAREA 0.7215 LAYER Metal2 ; + ANTENNAMODEL OXIDE1 ; + ANTENNAGATEAREA 0.20085 LAYER Metal2 ; + ANTENNAMAXAREACAR 4.498382 LAYER Metal2 ; + PORT + LAYER Metal2 ; + RECT 179.73 0 179.99 0.26 ; + END + END A_BM[15] + PIN A_BIST_BM[16] + DIRECTION INPUT ; + USE SIGNAL ; + ANTENNAPARTIALMETALAREA 0.7605 LAYER Metal2 ; + ANTENNAMODEL OXIDE1 ; + ANTENNAGATEAREA 0.20085 LAYER Metal2 ; + ANTENNAMAXAREACAR 5.055265 LAYER Metal2 ; + PORT + LAYER Metal2 ; + RECT 238.025 0 238.285 0.26 ; + END + END A_BIST_BM[16] + PIN A_BIST_BM[15] + DIRECTION INPUT ; + USE SIGNAL ; + ANTENNAPARTIALMETALAREA 0.7605 LAYER Metal2 ; + ANTENNAMODEL OXIDE1 ; + ANTENNAGATEAREA 0.20085 LAYER Metal2 ; + ANTENNAMAXAREACAR 5.055265 LAYER Metal2 ; + PORT + LAYER Metal2 ; + RECT 178.355 0 178.615 0.26 ; + END + END A_BIST_BM[15] + PIN A_DOUT[16] + DIRECTION OUTPUT ; + USE SIGNAL ; + ANTENNAPARTIALMETALAREA 3.7095 LAYER Metal2 ; + ANTENNADIFFAREA 0.988 LAYER Metal2 ; + PORT + LAYER Metal2 ; + RECT 237.16 0 237.42 0.26 ; + END + END A_DOUT[16] + PIN A_DOUT[15] + DIRECTION OUTPUT ; + USE SIGNAL ; + ANTENNAPARTIALMETALAREA 3.7095 LAYER Metal2 ; + ANTENNADIFFAREA 0.988 LAYER Metal2 ; + PORT + LAYER Metal2 ; + RECT 179.22 0 179.48 0.26 ; + END + END A_DOUT[15] + PIN VSS! + DIRECTION INOUT ; + USE GROUND ; + NETEXPR "vss VSS!" ; + PORT + LAYER Metal4 ; + RECT 403.95 0 406.76 336.46 ; + END + PORT + LAYER Metal4 ; + RECT 392.71 0 395.52 336.46 ; + END + PORT + LAYER Metal4 ; + RECT 381.47 0 384.28 336.46 ; + END + PORT + LAYER Metal4 ; + RECT 370.23 0 373.04 336.46 ; + END + PORT + LAYER Metal4 ; + RECT 358.99 0 361.8 336.46 ; + END + PORT + LAYER Metal4 ; + RECT 347.75 0 350.56 336.46 ; + END + PORT + LAYER Metal4 ; + RECT 336.51 0 339.32 336.46 ; + END + PORT + LAYER Metal4 ; + RECT 325.27 0 328.08 336.46 ; + END + PORT + LAYER Metal4 ; + RECT 314.03 0 316.84 336.46 ; + END + PORT + LAYER Metal4 ; + RECT 302.79 0 305.6 336.46 ; + END + PORT + LAYER Metal4 ; + RECT 291.55 0 294.36 336.46 ; + END + PORT + LAYER Metal4 ; + RECT 280.31 0 283.12 336.46 ; + END + PORT + LAYER Metal4 ; + RECT 269.07 0 271.88 336.46 ; + END + PORT + LAYER Metal4 ; + RECT 257.83 0 260.64 336.46 ; + END + PORT + LAYER Metal4 ; + RECT 246.59 0 249.4 336.46 ; + END + PORT + LAYER Metal4 ; + RECT 235.35 0 238.16 336.46 ; + END + PORT + LAYER Metal4 ; + RECT 224.94 0 227.75 336.46 ; + END + PORT + LAYER Metal4 ; + RECT 214.64 0 217.45 336.46 ; + END + PORT + LAYER Metal4 ; + RECT 199.19 0 202 336.46 ; + END + PORT + LAYER Metal4 ; + RECT 188.89 0 191.7 336.46 ; + END + PORT + LAYER Metal4 ; + RECT 178.48 0 181.29 336.46 ; + END + PORT + LAYER Metal4 ; + RECT 167.24 0 170.05 336.46 ; + END + PORT + LAYER Metal4 ; + RECT 156 0 158.81 336.46 ; + END + PORT + LAYER Metal4 ; + RECT 144.76 0 147.57 336.46 ; + END + PORT + LAYER Metal4 ; + RECT 133.52 0 136.33 336.46 ; + END + PORT + LAYER Metal4 ; + RECT 122.28 0 125.09 336.46 ; + END + PORT + LAYER Metal4 ; + RECT 111.04 0 113.85 336.46 ; + END + PORT + LAYER Metal4 ; + RECT 99.8 0 102.61 336.46 ; + END + PORT + LAYER Metal4 ; + RECT 88.56 0 91.37 336.46 ; + END + PORT + LAYER Metal4 ; + RECT 77.32 0 80.13 336.46 ; + END + PORT + LAYER Metal4 ; + RECT 66.08 0 68.89 336.46 ; + END + PORT + LAYER Metal4 ; + RECT 54.84 0 57.65 336.46 ; + END + PORT + LAYER Metal4 ; + RECT 43.6 0 46.41 336.46 ; + END + PORT + LAYER Metal4 ; + RECT 32.36 0 35.17 336.46 ; + END + PORT + LAYER Metal4 ; + RECT 21.12 0 23.93 336.46 ; + END + PORT + LAYER Metal4 ; + RECT 9.88 0 12.69 336.46 ; + END + END VSS! + PIN VDD! + DIRECTION INOUT ; + USE POWER ; + NETEXPR "vdd VDD!" ; + PORT + LAYER Metal4 ; + RECT 409.57 0 412.38 38.825 ; + END + PORT + LAYER Metal4 ; + RECT 398.33 0 401.14 38.825 ; + END + PORT + LAYER Metal4 ; + RECT 387.09 0 389.9 38.825 ; + END + PORT + LAYER Metal4 ; + RECT 375.85 0 378.66 38.825 ; + END + PORT + LAYER Metal4 ; + RECT 364.61 0 367.42 38.825 ; + END + PORT + LAYER Metal4 ; + RECT 353.37 0 356.18 38.825 ; + END + PORT + LAYER Metal4 ; + RECT 342.13 0 344.94 38.825 ; + END + PORT + LAYER Metal4 ; + RECT 330.89 0 333.7 38.825 ; + END + PORT + LAYER Metal4 ; + RECT 319.65 0 322.46 38.825 ; + END + PORT + LAYER Metal4 ; + RECT 308.41 0 311.22 38.825 ; + END + PORT + LAYER Metal4 ; + RECT 297.17 0 299.98 38.825 ; + END + PORT + LAYER Metal4 ; + RECT 285.93 0 288.74 38.825 ; + END + PORT + LAYER Metal4 ; + RECT 274.69 0 277.5 38.825 ; + END + PORT + LAYER Metal4 ; + RECT 263.45 0 266.26 38.825 ; + END + PORT + LAYER Metal4 ; + RECT 252.21 0 255.02 38.825 ; + END + PORT + LAYER Metal4 ; + RECT 240.97 0 243.78 38.825 ; + END + PORT + LAYER Metal4 ; + RECT 219.79 0 222.6 336.46 ; + END + PORT + LAYER Metal4 ; + RECT 209.49 0 212.3 336.46 ; + END + PORT + LAYER Metal4 ; + RECT 204.34 0 207.15 336.46 ; + END + PORT + LAYER Metal4 ; + RECT 194.04 0 196.85 336.46 ; + END + PORT + LAYER Metal4 ; + RECT 172.86 0 175.67 38.825 ; + END + PORT + LAYER Metal4 ; + RECT 161.62 0 164.43 38.825 ; + END + PORT + LAYER Metal4 ; + RECT 150.38 0 153.19 38.825 ; + END + PORT + LAYER Metal4 ; + RECT 139.14 0 141.95 38.825 ; + END + PORT + LAYER Metal4 ; + RECT 127.9 0 130.71 38.825 ; + END + PORT + LAYER Metal4 ; + RECT 116.66 0 119.47 38.825 ; + END + PORT + LAYER Metal4 ; + RECT 105.42 0 108.23 38.825 ; + END + PORT + LAYER Metal4 ; + RECT 94.18 0 96.99 38.825 ; + END + PORT + LAYER Metal4 ; + RECT 82.94 0 85.75 38.825 ; + END + PORT + LAYER Metal4 ; + RECT 71.7 0 74.51 38.825 ; + END + PORT + LAYER Metal4 ; + RECT 60.46 0 63.27 38.825 ; + END + PORT + LAYER Metal4 ; + RECT 49.22 0 52.03 38.825 ; + END + PORT + LAYER Metal4 ; + RECT 37.98 0 40.79 38.825 ; + END + PORT + LAYER Metal4 ; + RECT 26.74 0 29.55 38.825 ; + END + PORT + LAYER Metal4 ; + RECT 15.5 0 18.31 38.825 ; + END + PORT + LAYER Metal4 ; + RECT 4.26 0 7.07 38.825 ; + END + END VDD! + PIN VDDARRAY! + DIRECTION INOUT ; + USE POWER ; + NETEXPR "vddarray VDDARRAY!" ; + PORT + LAYER Metal4 ; + RECT 409.57 45.465 412.38 336.46 ; + END + PORT + LAYER Metal4 ; + RECT 398.33 45.465 401.14 336.46 ; + END + PORT + LAYER Metal4 ; + RECT 387.09 45.465 389.9 336.46 ; + END + PORT + LAYER Metal4 ; + RECT 375.85 45.465 378.66 336.46 ; + END + PORT + LAYER Metal4 ; + RECT 364.61 45.465 367.42 336.46 ; + END + PORT + LAYER Metal4 ; + RECT 353.37 45.465 356.18 336.46 ; + END + PORT + LAYER Metal4 ; + RECT 342.13 45.465 344.94 336.46 ; + END + PORT + LAYER Metal4 ; + RECT 330.89 45.465 333.7 336.46 ; + END + PORT + LAYER Metal4 ; + RECT 319.65 45.465 322.46 336.46 ; + END + PORT + LAYER Metal4 ; + RECT 308.41 45.465 311.22 336.46 ; + END + PORT + LAYER Metal4 ; + RECT 297.17 45.465 299.98 336.46 ; + END + PORT + LAYER Metal4 ; + RECT 285.93 45.465 288.74 336.46 ; + END + PORT + LAYER Metal4 ; + RECT 274.69 45.465 277.5 336.46 ; + END + PORT + LAYER Metal4 ; + RECT 263.45 45.465 266.26 336.46 ; + END + PORT + LAYER Metal4 ; + RECT 252.21 45.465 255.02 336.46 ; + END + PORT + LAYER Metal4 ; + RECT 240.97 45.465 243.78 336.46 ; + END + PORT + LAYER Metal4 ; + RECT 172.86 45.465 175.67 336.46 ; + END + PORT + LAYER Metal4 ; + RECT 161.62 45.465 164.43 336.46 ; + END + PORT + LAYER Metal4 ; + RECT 150.38 45.465 153.19 336.46 ; + END + PORT + LAYER Metal4 ; + RECT 139.14 45.465 141.95 336.46 ; + END + PORT + LAYER Metal4 ; + RECT 127.9 45.465 130.71 336.46 ; + END + PORT + LAYER Metal4 ; + RECT 116.66 45.465 119.47 336.46 ; + END + PORT + LAYER Metal4 ; + RECT 105.42 45.465 108.23 336.46 ; + END + PORT + LAYER Metal4 ; + RECT 94.18 45.465 96.99 336.46 ; + END + PORT + LAYER Metal4 ; + RECT 82.94 45.465 85.75 336.46 ; + END + PORT + LAYER Metal4 ; + RECT 71.7 45.465 74.51 336.46 ; + END + PORT + LAYER Metal4 ; + RECT 60.46 45.465 63.27 336.46 ; + END + PORT + LAYER Metal4 ; + RECT 49.22 45.465 52.03 336.46 ; + END + PORT + LAYER Metal4 ; + RECT 37.98 45.465 40.79 336.46 ; + END + PORT + LAYER Metal4 ; + RECT 26.74 45.465 29.55 336.46 ; + END + PORT + LAYER Metal4 ; + RECT 15.5 45.465 18.31 336.46 ; + END + PORT + LAYER Metal4 ; + RECT 4.26 45.465 7.07 336.46 ; + END + END VDDARRAY! + PIN A_DIN[17] + DIRECTION INPUT ; + USE SIGNAL ; + ANTENNAPARTIALMETALAREA 1.794 LAYER Metal2 ; + ANTENNAMODEL OXIDE1 ; + ANTENNAGATEAREA 0.20085 LAYER Metal2 ; + ANTENNAMAXAREACAR 9.838188 LAYER Metal2 ; + PORT + LAYER Metal2 ; + RECT 255.73 0 255.99 0.26 ; + END + END A_DIN[17] + PIN A_DIN[14] + DIRECTION INPUT ; + USE SIGNAL ; + ANTENNAPARTIALMETALAREA 1.794 LAYER Metal2 ; + ANTENNAMODEL OXIDE1 ; + ANTENNAGATEAREA 0.20085 LAYER Metal2 ; + ANTENNAMAXAREACAR 9.838188 LAYER Metal2 ; + PORT + LAYER Metal2 ; + RECT 160.65 0 160.91 0.26 ; + END + END A_DIN[14] + PIN A_BIST_DIN[17] + DIRECTION INPUT ; + USE SIGNAL ; + ANTENNAPARTIALMETALAREA 1.6263 LAYER Metal2 ; + ANTENNAMODEL OXIDE1 ; + ANTENNAGATEAREA 0.20085 LAYER Metal2 ; + ANTENNAMAXAREACAR 9.365945 LAYER Metal2 ; + PORT + LAYER Metal2 ; + RECT 254.875 0 255.135 0.26 ; + END + END A_BIST_DIN[17] + PIN A_BIST_DIN[14] + DIRECTION INPUT ; + USE SIGNAL ; + ANTENNAPARTIALMETALAREA 1.6263 LAYER Metal2 ; + ANTENNAMODEL OXIDE1 ; + ANTENNAGATEAREA 0.20085 LAYER Metal2 ; + ANTENNAMAXAREACAR 9.365945 LAYER Metal2 ; + PORT + LAYER Metal2 ; + RECT 161.505 0 161.765 0.26 ; + END + END A_BIST_DIN[14] + PIN A_BM[17] + DIRECTION INPUT ; + USE SIGNAL ; + ANTENNAPARTIALMETALAREA 0.7215 LAYER Metal2 ; + ANTENNAMODEL OXIDE1 ; + ANTENNAGATEAREA 0.20085 LAYER Metal2 ; + ANTENNAMAXAREACAR 4.498382 LAYER Metal2 ; + PORT + LAYER Metal2 ; + RECT 247.89 0 248.15 0.26 ; + END + END A_BM[17] + PIN A_BM[14] + DIRECTION INPUT ; + USE SIGNAL ; + ANTENNAPARTIALMETALAREA 0.7215 LAYER Metal2 ; + ANTENNAMODEL OXIDE1 ; + ANTENNAGATEAREA 0.20085 LAYER Metal2 ; + ANTENNAMAXAREACAR 4.498382 LAYER Metal2 ; + PORT + LAYER Metal2 ; + RECT 168.49 0 168.75 0.26 ; + END + END A_BM[14] + PIN A_BIST_BM[17] + DIRECTION INPUT ; + USE SIGNAL ; + ANTENNAPARTIALMETALAREA 0.7605 LAYER Metal2 ; + ANTENNAMODEL OXIDE1 ; + ANTENNAGATEAREA 0.20085 LAYER Metal2 ; + ANTENNAMAXAREACAR 5.055265 LAYER Metal2 ; + PORT + LAYER Metal2 ; + RECT 249.265 0 249.525 0.26 ; + END + END A_BIST_BM[17] + PIN A_BIST_BM[14] + DIRECTION INPUT ; + USE SIGNAL ; + ANTENNAPARTIALMETALAREA 0.7605 LAYER Metal2 ; + ANTENNAMODEL OXIDE1 ; + ANTENNAGATEAREA 0.20085 LAYER Metal2 ; + ANTENNAMAXAREACAR 5.055265 LAYER Metal2 ; + PORT + LAYER Metal2 ; + RECT 167.115 0 167.375 0.26 ; + END + END A_BIST_BM[14] + PIN A_DOUT[17] + DIRECTION OUTPUT ; + USE SIGNAL ; + ANTENNAPARTIALMETALAREA 3.7095 LAYER Metal2 ; + ANTENNADIFFAREA 0.988 LAYER Metal2 ; + PORT + LAYER Metal2 ; + RECT 248.4 0 248.66 0.26 ; + END + END A_DOUT[17] + PIN A_DOUT[14] + DIRECTION OUTPUT ; + USE SIGNAL ; + ANTENNAPARTIALMETALAREA 3.7095 LAYER Metal2 ; + ANTENNADIFFAREA 0.988 LAYER Metal2 ; + PORT + LAYER Metal2 ; + RECT 167.98 0 168.24 0.26 ; + END + END A_DOUT[14] + PIN A_DIN[18] + DIRECTION INPUT ; + USE SIGNAL ; + ANTENNAPARTIALMETALAREA 1.794 LAYER Metal2 ; + ANTENNAMODEL OXIDE1 ; + ANTENNAGATEAREA 0.20085 LAYER Metal2 ; + ANTENNAMAXAREACAR 9.838188 LAYER Metal2 ; + PORT + LAYER Metal2 ; + RECT 266.97 0 267.23 0.26 ; + END + END A_DIN[18] + PIN A_DIN[13] + DIRECTION INPUT ; + USE SIGNAL ; + ANTENNAPARTIALMETALAREA 1.794 LAYER Metal2 ; + ANTENNAMODEL OXIDE1 ; + ANTENNAGATEAREA 0.20085 LAYER Metal2 ; + ANTENNAMAXAREACAR 9.838188 LAYER Metal2 ; + PORT + LAYER Metal2 ; + RECT 149.41 0 149.67 0.26 ; + END + END A_DIN[13] + PIN A_BIST_DIN[18] + DIRECTION INPUT ; + USE SIGNAL ; + ANTENNAPARTIALMETALAREA 1.6263 LAYER Metal2 ; + ANTENNAMODEL OXIDE1 ; + ANTENNAGATEAREA 0.20085 LAYER Metal2 ; + ANTENNAMAXAREACAR 9.365945 LAYER Metal2 ; + PORT + LAYER Metal2 ; + RECT 266.115 0 266.375 0.26 ; + END + END A_BIST_DIN[18] + PIN A_BIST_DIN[13] + DIRECTION INPUT ; + USE SIGNAL ; + ANTENNAPARTIALMETALAREA 1.6263 LAYER Metal2 ; + ANTENNAMODEL OXIDE1 ; + ANTENNAGATEAREA 0.20085 LAYER Metal2 ; + ANTENNAMAXAREACAR 9.365945 LAYER Metal2 ; + PORT + LAYER Metal2 ; + RECT 150.265 0 150.525 0.26 ; + END + END A_BIST_DIN[13] + PIN A_BM[18] + DIRECTION INPUT ; + USE SIGNAL ; + ANTENNAPARTIALMETALAREA 0.7215 LAYER Metal2 ; + ANTENNAMODEL OXIDE1 ; + ANTENNAGATEAREA 0.20085 LAYER Metal2 ; + ANTENNAMAXAREACAR 4.498382 LAYER Metal2 ; + PORT + LAYER Metal2 ; + RECT 259.13 0 259.39 0.26 ; + END + END A_BM[18] + PIN A_BM[13] + DIRECTION INPUT ; + USE SIGNAL ; + ANTENNAPARTIALMETALAREA 0.7215 LAYER Metal2 ; + ANTENNAMODEL OXIDE1 ; + ANTENNAGATEAREA 0.20085 LAYER Metal2 ; + ANTENNAMAXAREACAR 4.498382 LAYER Metal2 ; + PORT + LAYER Metal2 ; + RECT 157.25 0 157.51 0.26 ; + END + END A_BM[13] + PIN A_BIST_BM[18] + DIRECTION INPUT ; + USE SIGNAL ; + ANTENNAPARTIALMETALAREA 0.7605 LAYER Metal2 ; + ANTENNAMODEL OXIDE1 ; + ANTENNAGATEAREA 0.20085 LAYER Metal2 ; + ANTENNAMAXAREACAR 5.055265 LAYER Metal2 ; + PORT + LAYER Metal2 ; + RECT 260.505 0 260.765 0.26 ; + END + END A_BIST_BM[18] + PIN A_BIST_BM[13] + DIRECTION INPUT ; + USE SIGNAL ; + ANTENNAPARTIALMETALAREA 0.7605 LAYER Metal2 ; + ANTENNAMODEL OXIDE1 ; + ANTENNAGATEAREA 0.20085 LAYER Metal2 ; + ANTENNAMAXAREACAR 5.055265 LAYER Metal2 ; + PORT + LAYER Metal2 ; + RECT 155.875 0 156.135 0.26 ; + END + END A_BIST_BM[13] + PIN A_DOUT[18] + DIRECTION OUTPUT ; + USE SIGNAL ; + ANTENNAPARTIALMETALAREA 3.7095 LAYER Metal2 ; + ANTENNADIFFAREA 0.988 LAYER Metal2 ; + PORT + LAYER Metal2 ; + RECT 259.64 0 259.9 0.26 ; + END + END A_DOUT[18] + PIN A_DOUT[13] + DIRECTION OUTPUT ; + USE SIGNAL ; + ANTENNAPARTIALMETALAREA 3.7095 LAYER Metal2 ; + ANTENNADIFFAREA 0.988 LAYER Metal2 ; + PORT + LAYER Metal2 ; + RECT 156.74 0 157 0.26 ; + END + END A_DOUT[13] + PIN A_DIN[19] + DIRECTION INPUT ; + USE SIGNAL ; + ANTENNAPARTIALMETALAREA 1.794 LAYER Metal2 ; + ANTENNAMODEL OXIDE1 ; + ANTENNAGATEAREA 0.20085 LAYER Metal2 ; + ANTENNAMAXAREACAR 9.838188 LAYER Metal2 ; + PORT + LAYER Metal2 ; + RECT 278.21 0 278.47 0.26 ; + END + END A_DIN[19] + PIN A_DIN[12] + DIRECTION INPUT ; + USE SIGNAL ; + ANTENNAPARTIALMETALAREA 1.794 LAYER Metal2 ; + ANTENNAMODEL OXIDE1 ; + ANTENNAGATEAREA 0.20085 LAYER Metal2 ; + ANTENNAMAXAREACAR 9.838188 LAYER Metal2 ; + PORT + LAYER Metal2 ; + RECT 138.17 0 138.43 0.26 ; + END + END A_DIN[12] + PIN A_BIST_DIN[19] + DIRECTION INPUT ; + USE SIGNAL ; + ANTENNAPARTIALMETALAREA 1.6263 LAYER Metal2 ; + ANTENNAMODEL OXIDE1 ; + ANTENNAGATEAREA 0.20085 LAYER Metal2 ; + ANTENNAMAXAREACAR 9.365945 LAYER Metal2 ; + PORT + LAYER Metal2 ; + RECT 277.355 0 277.615 0.26 ; + END + END A_BIST_DIN[19] + PIN A_BIST_DIN[12] + DIRECTION INPUT ; + USE SIGNAL ; + ANTENNAPARTIALMETALAREA 1.6263 LAYER Metal2 ; + ANTENNAMODEL OXIDE1 ; + ANTENNAGATEAREA 0.20085 LAYER Metal2 ; + ANTENNAMAXAREACAR 9.365945 LAYER Metal2 ; + PORT + LAYER Metal2 ; + RECT 139.025 0 139.285 0.26 ; + END + END A_BIST_DIN[12] + PIN A_BM[19] + DIRECTION INPUT ; + USE SIGNAL ; + ANTENNAPARTIALMETALAREA 0.7215 LAYER Metal2 ; + ANTENNAMODEL OXIDE1 ; + ANTENNAGATEAREA 0.20085 LAYER Metal2 ; + ANTENNAMAXAREACAR 4.498382 LAYER Metal2 ; + PORT + LAYER Metal2 ; + RECT 270.37 0 270.63 0.26 ; + END + END A_BM[19] + PIN A_BM[12] + DIRECTION INPUT ; + USE SIGNAL ; + ANTENNAPARTIALMETALAREA 0.7215 LAYER Metal2 ; + ANTENNAMODEL OXIDE1 ; + ANTENNAGATEAREA 0.20085 LAYER Metal2 ; + ANTENNAMAXAREACAR 4.498382 LAYER Metal2 ; + PORT + LAYER Metal2 ; + RECT 146.01 0 146.27 0.26 ; + END + END A_BM[12] + PIN A_BIST_BM[19] + DIRECTION INPUT ; + USE SIGNAL ; + ANTENNAPARTIALMETALAREA 0.7605 LAYER Metal2 ; + ANTENNAMODEL OXIDE1 ; + ANTENNAGATEAREA 0.20085 LAYER Metal2 ; + ANTENNAMAXAREACAR 5.055265 LAYER Metal2 ; + PORT + LAYER Metal2 ; + RECT 271.745 0 272.005 0.26 ; + END + END A_BIST_BM[19] + PIN A_BIST_BM[12] + DIRECTION INPUT ; + USE SIGNAL ; + ANTENNAPARTIALMETALAREA 0.7605 LAYER Metal2 ; + ANTENNAMODEL OXIDE1 ; + ANTENNAGATEAREA 0.20085 LAYER Metal2 ; + ANTENNAMAXAREACAR 5.055265 LAYER Metal2 ; + PORT + LAYER Metal2 ; + RECT 144.635 0 144.895 0.26 ; + END + END A_BIST_BM[12] + PIN A_DOUT[19] + DIRECTION OUTPUT ; + USE SIGNAL ; + ANTENNAPARTIALMETALAREA 3.7095 LAYER Metal2 ; + ANTENNADIFFAREA 0.988 LAYER Metal2 ; + PORT + LAYER Metal2 ; + RECT 270.88 0 271.14 0.26 ; + END + END A_DOUT[19] + PIN A_DOUT[12] + DIRECTION OUTPUT ; + USE SIGNAL ; + ANTENNAPARTIALMETALAREA 3.7095 LAYER Metal2 ; + ANTENNADIFFAREA 0.988 LAYER Metal2 ; + PORT + LAYER Metal2 ; + RECT 145.5 0 145.76 0.26 ; + END + END A_DOUT[12] + PIN A_DIN[20] + DIRECTION INPUT ; + USE SIGNAL ; + ANTENNAPARTIALMETALAREA 1.794 LAYER Metal2 ; + ANTENNAMODEL OXIDE1 ; + ANTENNAGATEAREA 0.20085 LAYER Metal2 ; + ANTENNAMAXAREACAR 9.838188 LAYER Metal2 ; + PORT + LAYER Metal2 ; + RECT 289.45 0 289.71 0.26 ; + END + END A_DIN[20] + PIN A_DIN[11] + DIRECTION INPUT ; + USE SIGNAL ; + ANTENNAPARTIALMETALAREA 1.794 LAYER Metal2 ; + ANTENNAMODEL OXIDE1 ; + ANTENNAGATEAREA 0.20085 LAYER Metal2 ; + ANTENNAMAXAREACAR 9.838188 LAYER Metal2 ; + PORT + LAYER Metal2 ; + RECT 126.93 0 127.19 0.26 ; + END + END A_DIN[11] + PIN A_BIST_DIN[20] + DIRECTION INPUT ; + USE SIGNAL ; + ANTENNAPARTIALMETALAREA 1.6263 LAYER Metal2 ; + ANTENNAMODEL OXIDE1 ; + ANTENNAGATEAREA 0.20085 LAYER Metal2 ; + ANTENNAMAXAREACAR 9.365945 LAYER Metal2 ; + PORT + LAYER Metal2 ; + RECT 288.595 0 288.855 0.26 ; + END + END A_BIST_DIN[20] + PIN A_BIST_DIN[11] + DIRECTION INPUT ; + USE SIGNAL ; + ANTENNAPARTIALMETALAREA 1.6263 LAYER Metal2 ; + ANTENNAMODEL OXIDE1 ; + ANTENNAGATEAREA 0.20085 LAYER Metal2 ; + ANTENNAMAXAREACAR 9.365945 LAYER Metal2 ; + PORT + LAYER Metal2 ; + RECT 127.785 0 128.045 0.26 ; + END + END A_BIST_DIN[11] + PIN A_BM[20] + DIRECTION INPUT ; + USE SIGNAL ; + ANTENNAPARTIALMETALAREA 0.7215 LAYER Metal2 ; + ANTENNAMODEL OXIDE1 ; + ANTENNAGATEAREA 0.20085 LAYER Metal2 ; + ANTENNAMAXAREACAR 4.498382 LAYER Metal2 ; + PORT + LAYER Metal2 ; + RECT 281.61 0 281.87 0.26 ; + END + END A_BM[20] + PIN A_BM[11] + DIRECTION INPUT ; + USE SIGNAL ; + ANTENNAPARTIALMETALAREA 0.7215 LAYER Metal2 ; + ANTENNAMODEL OXIDE1 ; + ANTENNAGATEAREA 0.20085 LAYER Metal2 ; + ANTENNAMAXAREACAR 4.498382 LAYER Metal2 ; + PORT + LAYER Metal2 ; + RECT 134.77 0 135.03 0.26 ; + END + END A_BM[11] + PIN A_BIST_BM[20] + DIRECTION INPUT ; + USE SIGNAL ; + ANTENNAPARTIALMETALAREA 0.7605 LAYER Metal2 ; + ANTENNAMODEL OXIDE1 ; + ANTENNAGATEAREA 0.20085 LAYER Metal2 ; + ANTENNAMAXAREACAR 5.055265 LAYER Metal2 ; + PORT + LAYER Metal2 ; + RECT 282.985 0 283.245 0.26 ; + END + END A_BIST_BM[20] + PIN A_BIST_BM[11] + DIRECTION INPUT ; + USE SIGNAL ; + ANTENNAPARTIALMETALAREA 0.7605 LAYER Metal2 ; + ANTENNAMODEL OXIDE1 ; + ANTENNAGATEAREA 0.20085 LAYER Metal2 ; + ANTENNAMAXAREACAR 5.055265 LAYER Metal2 ; + PORT + LAYER Metal2 ; + RECT 133.395 0 133.655 0.26 ; + END + END A_BIST_BM[11] + PIN A_DOUT[20] + DIRECTION OUTPUT ; + USE SIGNAL ; + ANTENNAPARTIALMETALAREA 3.7095 LAYER Metal2 ; + ANTENNADIFFAREA 0.988 LAYER Metal2 ; + PORT + LAYER Metal2 ; + RECT 282.12 0 282.38 0.26 ; + END + END A_DOUT[20] + PIN A_DOUT[11] + DIRECTION OUTPUT ; + USE SIGNAL ; + ANTENNAPARTIALMETALAREA 3.7095 LAYER Metal2 ; + ANTENNADIFFAREA 0.988 LAYER Metal2 ; + PORT + LAYER Metal2 ; + RECT 134.26 0 134.52 0.26 ; + END + END A_DOUT[11] + PIN A_DIN[21] + DIRECTION INPUT ; + USE SIGNAL ; + ANTENNAPARTIALMETALAREA 1.794 LAYER Metal2 ; + ANTENNAMODEL OXIDE1 ; + ANTENNAGATEAREA 0.20085 LAYER Metal2 ; + ANTENNAMAXAREACAR 9.838188 LAYER Metal2 ; + PORT + LAYER Metal2 ; + RECT 300.69 0 300.95 0.26 ; + END + END A_DIN[21] + PIN A_DIN[10] + DIRECTION INPUT ; + USE SIGNAL ; + ANTENNAPARTIALMETALAREA 1.794 LAYER Metal2 ; + ANTENNAMODEL OXIDE1 ; + ANTENNAGATEAREA 0.20085 LAYER Metal2 ; + ANTENNAMAXAREACAR 9.838188 LAYER Metal2 ; + PORT + LAYER Metal2 ; + RECT 115.69 0 115.95 0.26 ; + END + END A_DIN[10] + PIN A_BIST_DIN[21] + DIRECTION INPUT ; + USE SIGNAL ; + ANTENNAPARTIALMETALAREA 1.6263 LAYER Metal2 ; + ANTENNAMODEL OXIDE1 ; + ANTENNAGATEAREA 0.20085 LAYER Metal2 ; + ANTENNAMAXAREACAR 9.365945 LAYER Metal2 ; + PORT + LAYER Metal2 ; + RECT 299.835 0 300.095 0.26 ; + END + END A_BIST_DIN[21] + PIN A_BIST_DIN[10] + DIRECTION INPUT ; + USE SIGNAL ; + ANTENNAPARTIALMETALAREA 1.6263 LAYER Metal2 ; + ANTENNAMODEL OXIDE1 ; + ANTENNAGATEAREA 0.20085 LAYER Metal2 ; + ANTENNAMAXAREACAR 9.365945 LAYER Metal2 ; + PORT + LAYER Metal2 ; + RECT 116.545 0 116.805 0.26 ; + END + END A_BIST_DIN[10] + PIN A_BM[21] + DIRECTION INPUT ; + USE SIGNAL ; + ANTENNAPARTIALMETALAREA 0.7215 LAYER Metal2 ; + ANTENNAMODEL OXIDE1 ; + ANTENNAGATEAREA 0.20085 LAYER Metal2 ; + ANTENNAMAXAREACAR 4.498382 LAYER Metal2 ; + PORT + LAYER Metal2 ; + RECT 292.85 0 293.11 0.26 ; + END + END A_BM[21] + PIN A_BM[10] + DIRECTION INPUT ; + USE SIGNAL ; + ANTENNAPARTIALMETALAREA 0.7215 LAYER Metal2 ; + ANTENNAMODEL OXIDE1 ; + ANTENNAGATEAREA 0.20085 LAYER Metal2 ; + ANTENNAMAXAREACAR 4.498382 LAYER Metal2 ; + PORT + LAYER Metal2 ; + RECT 123.53 0 123.79 0.26 ; + END + END A_BM[10] + PIN A_BIST_BM[21] + DIRECTION INPUT ; + USE SIGNAL ; + ANTENNAPARTIALMETALAREA 0.7605 LAYER Metal2 ; + ANTENNAMODEL OXIDE1 ; + ANTENNAGATEAREA 0.20085 LAYER Metal2 ; + ANTENNAMAXAREACAR 5.055265 LAYER Metal2 ; + PORT + LAYER Metal2 ; + RECT 294.225 0 294.485 0.26 ; + END + END A_BIST_BM[21] + PIN A_BIST_BM[10] + DIRECTION INPUT ; + USE SIGNAL ; + ANTENNAPARTIALMETALAREA 0.7605 LAYER Metal2 ; + ANTENNAMODEL OXIDE1 ; + ANTENNAGATEAREA 0.20085 LAYER Metal2 ; + ANTENNAMAXAREACAR 5.055265 LAYER Metal2 ; + PORT + LAYER Metal2 ; + RECT 122.155 0 122.415 0.26 ; + END + END A_BIST_BM[10] + PIN A_DOUT[21] + DIRECTION OUTPUT ; + USE SIGNAL ; + ANTENNAPARTIALMETALAREA 3.7095 LAYER Metal2 ; + ANTENNADIFFAREA 0.988 LAYER Metal2 ; + PORT + LAYER Metal2 ; + RECT 293.36 0 293.62 0.26 ; + END + END A_DOUT[21] + PIN A_DOUT[10] + DIRECTION OUTPUT ; + USE SIGNAL ; + ANTENNAPARTIALMETALAREA 3.7095 LAYER Metal2 ; + ANTENNADIFFAREA 0.988 LAYER Metal2 ; + PORT + LAYER Metal2 ; + RECT 123.02 0 123.28 0.26 ; + END + END A_DOUT[10] + PIN A_DIN[22] + DIRECTION INPUT ; + USE SIGNAL ; + ANTENNAPARTIALMETALAREA 1.794 LAYER Metal2 ; + ANTENNAMODEL OXIDE1 ; + ANTENNAGATEAREA 0.20085 LAYER Metal2 ; + ANTENNAMAXAREACAR 9.838188 LAYER Metal2 ; + PORT + LAYER Metal2 ; + RECT 311.93 0 312.19 0.26 ; + END + END A_DIN[22] + PIN A_DIN[9] + DIRECTION INPUT ; + USE SIGNAL ; + ANTENNAPARTIALMETALAREA 1.794 LAYER Metal2 ; + ANTENNAMODEL OXIDE1 ; + ANTENNAGATEAREA 0.20085 LAYER Metal2 ; + ANTENNAMAXAREACAR 9.838188 LAYER Metal2 ; + PORT + LAYER Metal2 ; + RECT 104.45 0 104.71 0.26 ; + END + END A_DIN[9] + PIN A_BIST_DIN[22] + DIRECTION INPUT ; + USE SIGNAL ; + ANTENNAPARTIALMETALAREA 1.6263 LAYER Metal2 ; + ANTENNAMODEL OXIDE1 ; + ANTENNAGATEAREA 0.20085 LAYER Metal2 ; + ANTENNAMAXAREACAR 9.365945 LAYER Metal2 ; + PORT + LAYER Metal2 ; + RECT 311.075 0 311.335 0.26 ; + END + END A_BIST_DIN[22] + PIN A_BIST_DIN[9] + DIRECTION INPUT ; + USE SIGNAL ; + ANTENNAPARTIALMETALAREA 1.6263 LAYER Metal2 ; + ANTENNAMODEL OXIDE1 ; + ANTENNAGATEAREA 0.20085 LAYER Metal2 ; + ANTENNAMAXAREACAR 9.365945 LAYER Metal2 ; + PORT + LAYER Metal2 ; + RECT 105.305 0 105.565 0.26 ; + END + END A_BIST_DIN[9] + PIN A_BM[22] + DIRECTION INPUT ; + USE SIGNAL ; + ANTENNAPARTIALMETALAREA 0.7215 LAYER Metal2 ; + ANTENNAMODEL OXIDE1 ; + ANTENNAGATEAREA 0.20085 LAYER Metal2 ; + ANTENNAMAXAREACAR 4.498382 LAYER Metal2 ; + PORT + LAYER Metal2 ; + RECT 304.09 0 304.35 0.26 ; + END + END A_BM[22] + PIN A_BM[9] + DIRECTION INPUT ; + USE SIGNAL ; + ANTENNAPARTIALMETALAREA 0.7215 LAYER Metal2 ; + ANTENNAMODEL OXIDE1 ; + ANTENNAGATEAREA 0.20085 LAYER Metal2 ; + ANTENNAMAXAREACAR 4.498382 LAYER Metal2 ; + PORT + LAYER Metal2 ; + RECT 112.29 0 112.55 0.26 ; + END + END A_BM[9] + PIN A_BIST_BM[22] + DIRECTION INPUT ; + USE SIGNAL ; + ANTENNAPARTIALMETALAREA 0.7605 LAYER Metal2 ; + ANTENNAMODEL OXIDE1 ; + ANTENNAGATEAREA 0.20085 LAYER Metal2 ; + ANTENNAMAXAREACAR 5.055265 LAYER Metal2 ; + PORT + LAYER Metal2 ; + RECT 305.465 0 305.725 0.26 ; + END + END A_BIST_BM[22] + PIN A_BIST_BM[9] + DIRECTION INPUT ; + USE SIGNAL ; + ANTENNAPARTIALMETALAREA 0.7605 LAYER Metal2 ; + ANTENNAMODEL OXIDE1 ; + ANTENNAGATEAREA 0.20085 LAYER Metal2 ; + ANTENNAMAXAREACAR 5.055265 LAYER Metal2 ; + PORT + LAYER Metal2 ; + RECT 110.915 0 111.175 0.26 ; + END + END A_BIST_BM[9] + PIN A_DOUT[22] + DIRECTION OUTPUT ; + USE SIGNAL ; + ANTENNAPARTIALMETALAREA 3.7095 LAYER Metal2 ; + ANTENNADIFFAREA 0.988 LAYER Metal2 ; + PORT + LAYER Metal2 ; + RECT 304.6 0 304.86 0.26 ; + END + END A_DOUT[22] + PIN A_DOUT[9] + DIRECTION OUTPUT ; + USE SIGNAL ; + ANTENNAPARTIALMETALAREA 3.7095 LAYER Metal2 ; + ANTENNADIFFAREA 0.988 LAYER Metal2 ; + PORT + LAYER Metal2 ; + RECT 111.78 0 112.04 0.26 ; + END + END A_DOUT[9] + PIN A_DIN[23] + DIRECTION INPUT ; + USE SIGNAL ; + ANTENNAPARTIALMETALAREA 1.794 LAYER Metal2 ; + ANTENNAMODEL OXIDE1 ; + ANTENNAGATEAREA 0.20085 LAYER Metal2 ; + ANTENNAMAXAREACAR 9.838188 LAYER Metal2 ; + PORT + LAYER Metal2 ; + RECT 323.17 0 323.43 0.26 ; + END + END A_DIN[23] + PIN A_DIN[8] + DIRECTION INPUT ; + USE SIGNAL ; + ANTENNAPARTIALMETALAREA 1.794 LAYER Metal2 ; + ANTENNAMODEL OXIDE1 ; + ANTENNAGATEAREA 0.20085 LAYER Metal2 ; + ANTENNAMAXAREACAR 9.838188 LAYER Metal2 ; + PORT + LAYER Metal2 ; + RECT 93.21 0 93.47 0.26 ; + END + END A_DIN[8] + PIN A_BIST_DIN[23] + DIRECTION INPUT ; + USE SIGNAL ; + ANTENNAPARTIALMETALAREA 1.6263 LAYER Metal2 ; + ANTENNAMODEL OXIDE1 ; + ANTENNAGATEAREA 0.20085 LAYER Metal2 ; + ANTENNAMAXAREACAR 9.365945 LAYER Metal2 ; + PORT + LAYER Metal2 ; + RECT 322.315 0 322.575 0.26 ; + END + END A_BIST_DIN[23] + PIN A_BIST_DIN[8] + DIRECTION INPUT ; + USE SIGNAL ; + ANTENNAPARTIALMETALAREA 1.6263 LAYER Metal2 ; + ANTENNAMODEL OXIDE1 ; + ANTENNAGATEAREA 0.20085 LAYER Metal2 ; + ANTENNAMAXAREACAR 9.365945 LAYER Metal2 ; + PORT + LAYER Metal2 ; + RECT 94.065 0 94.325 0.26 ; + END + END A_BIST_DIN[8] + PIN A_BM[23] + DIRECTION INPUT ; + USE SIGNAL ; + ANTENNAPARTIALMETALAREA 0.7215 LAYER Metal2 ; + ANTENNAMODEL OXIDE1 ; + ANTENNAGATEAREA 0.20085 LAYER Metal2 ; + ANTENNAMAXAREACAR 4.498382 LAYER Metal2 ; + PORT + LAYER Metal2 ; + RECT 315.33 0 315.59 0.26 ; + END + END A_BM[23] + PIN A_BM[8] + DIRECTION INPUT ; + USE SIGNAL ; + ANTENNAPARTIALMETALAREA 0.7215 LAYER Metal2 ; + ANTENNAMODEL OXIDE1 ; + ANTENNAGATEAREA 0.20085 LAYER Metal2 ; + ANTENNAMAXAREACAR 4.498382 LAYER Metal2 ; + PORT + LAYER Metal2 ; + RECT 101.05 0 101.31 0.26 ; + END + END A_BM[8] + PIN A_BIST_BM[23] + DIRECTION INPUT ; + USE SIGNAL ; + ANTENNAPARTIALMETALAREA 0.7605 LAYER Metal2 ; + ANTENNAMODEL OXIDE1 ; + ANTENNAGATEAREA 0.20085 LAYER Metal2 ; + ANTENNAMAXAREACAR 5.055265 LAYER Metal2 ; + PORT + LAYER Metal2 ; + RECT 316.705 0 316.965 0.26 ; + END + END A_BIST_BM[23] + PIN A_BIST_BM[8] + DIRECTION INPUT ; + USE SIGNAL ; + ANTENNAPARTIALMETALAREA 0.7605 LAYER Metal2 ; + ANTENNAMODEL OXIDE1 ; + ANTENNAGATEAREA 0.20085 LAYER Metal2 ; + ANTENNAMAXAREACAR 5.055265 LAYER Metal2 ; + PORT + LAYER Metal2 ; + RECT 99.675 0 99.935 0.26 ; + END + END A_BIST_BM[8] + PIN A_DOUT[23] + DIRECTION OUTPUT ; + USE SIGNAL ; + ANTENNAPARTIALMETALAREA 3.7095 LAYER Metal2 ; + ANTENNADIFFAREA 0.988 LAYER Metal2 ; + PORT + LAYER Metal2 ; + RECT 315.84 0 316.1 0.26 ; + END + END A_DOUT[23] + PIN A_DOUT[8] + DIRECTION OUTPUT ; + USE SIGNAL ; + ANTENNAPARTIALMETALAREA 3.7095 LAYER Metal2 ; + ANTENNADIFFAREA 0.988 LAYER Metal2 ; + PORT + LAYER Metal2 ; + RECT 100.54 0 100.8 0.26 ; + END + END A_DOUT[8] + PIN A_DIN[24] + DIRECTION INPUT ; + USE SIGNAL ; + ANTENNAPARTIALMETALAREA 1.794 LAYER Metal2 ; + ANTENNAMODEL OXIDE1 ; + ANTENNAGATEAREA 0.20085 LAYER Metal2 ; + ANTENNAMAXAREACAR 9.838188 LAYER Metal2 ; + PORT + LAYER Metal2 ; + RECT 334.41 0 334.67 0.26 ; + END + END A_DIN[24] + PIN A_DIN[7] + DIRECTION INPUT ; + USE SIGNAL ; + ANTENNAPARTIALMETALAREA 1.794 LAYER Metal2 ; + ANTENNAMODEL OXIDE1 ; + ANTENNAGATEAREA 0.20085 LAYER Metal2 ; + ANTENNAMAXAREACAR 9.838188 LAYER Metal2 ; + PORT + LAYER Metal2 ; + RECT 81.97 0 82.23 0.26 ; + END + END A_DIN[7] + PIN A_BIST_DIN[24] + DIRECTION INPUT ; + USE SIGNAL ; + ANTENNAPARTIALMETALAREA 1.6263 LAYER Metal2 ; + ANTENNAMODEL OXIDE1 ; + ANTENNAGATEAREA 0.20085 LAYER Metal2 ; + ANTENNAMAXAREACAR 9.365945 LAYER Metal2 ; + PORT + LAYER Metal2 ; + RECT 333.555 0 333.815 0.26 ; + END + END A_BIST_DIN[24] + PIN A_BIST_DIN[7] + DIRECTION INPUT ; + USE SIGNAL ; + ANTENNAPARTIALMETALAREA 1.6263 LAYER Metal2 ; + ANTENNAMODEL OXIDE1 ; + ANTENNAGATEAREA 0.20085 LAYER Metal2 ; + ANTENNAMAXAREACAR 9.365945 LAYER Metal2 ; + PORT + LAYER Metal2 ; + RECT 82.825 0 83.085 0.26 ; + END + END A_BIST_DIN[7] + PIN A_BM[24] + DIRECTION INPUT ; + USE SIGNAL ; + ANTENNAPARTIALMETALAREA 0.7215 LAYER Metal2 ; + ANTENNAMODEL OXIDE1 ; + ANTENNAGATEAREA 0.20085 LAYER Metal2 ; + ANTENNAMAXAREACAR 4.498382 LAYER Metal2 ; + PORT + LAYER Metal2 ; + RECT 326.57 0 326.83 0.26 ; + END + END A_BM[24] + PIN A_BM[7] + DIRECTION INPUT ; + USE SIGNAL ; + ANTENNAPARTIALMETALAREA 0.7215 LAYER Metal2 ; + ANTENNAMODEL OXIDE1 ; + ANTENNAGATEAREA 0.20085 LAYER Metal2 ; + ANTENNAMAXAREACAR 4.498382 LAYER Metal2 ; + PORT + LAYER Metal2 ; + RECT 89.81 0 90.07 0.26 ; + END + END A_BM[7] + PIN A_BIST_BM[24] + DIRECTION INPUT ; + USE SIGNAL ; + ANTENNAPARTIALMETALAREA 0.7605 LAYER Metal2 ; + ANTENNAMODEL OXIDE1 ; + ANTENNAGATEAREA 0.20085 LAYER Metal2 ; + ANTENNAMAXAREACAR 5.055265 LAYER Metal2 ; + PORT + LAYER Metal2 ; + RECT 327.945 0 328.205 0.26 ; + END + END A_BIST_BM[24] + PIN A_BIST_BM[7] + DIRECTION INPUT ; + USE SIGNAL ; + ANTENNAPARTIALMETALAREA 0.7605 LAYER Metal2 ; + ANTENNAMODEL OXIDE1 ; + ANTENNAGATEAREA 0.20085 LAYER Metal2 ; + ANTENNAMAXAREACAR 5.055265 LAYER Metal2 ; + PORT + LAYER Metal2 ; + RECT 88.435 0 88.695 0.26 ; + END + END A_BIST_BM[7] + PIN A_DOUT[24] + DIRECTION OUTPUT ; + USE SIGNAL ; + ANTENNAPARTIALMETALAREA 3.7095 LAYER Metal2 ; + ANTENNADIFFAREA 0.988 LAYER Metal2 ; + PORT + LAYER Metal2 ; + RECT 327.08 0 327.34 0.26 ; + END + END A_DOUT[24] + PIN A_DOUT[7] + DIRECTION OUTPUT ; + USE SIGNAL ; + ANTENNAPARTIALMETALAREA 3.7095 LAYER Metal2 ; + ANTENNADIFFAREA 0.988 LAYER Metal2 ; + PORT + LAYER Metal2 ; + RECT 89.3 0 89.56 0.26 ; + END + END A_DOUT[7] + PIN A_DIN[25] + DIRECTION INPUT ; + USE SIGNAL ; + ANTENNAPARTIALMETALAREA 1.794 LAYER Metal2 ; + ANTENNAMODEL OXIDE1 ; + ANTENNAGATEAREA 0.20085 LAYER Metal2 ; + ANTENNAMAXAREACAR 9.838188 LAYER Metal2 ; + PORT + LAYER Metal2 ; + RECT 345.65 0 345.91 0.26 ; + END + END A_DIN[25] + PIN A_DIN[6] + DIRECTION INPUT ; + USE SIGNAL ; + ANTENNAPARTIALMETALAREA 1.794 LAYER Metal2 ; + ANTENNAMODEL OXIDE1 ; + ANTENNAGATEAREA 0.20085 LAYER Metal2 ; + ANTENNAMAXAREACAR 9.838188 LAYER Metal2 ; + PORT + LAYER Metal2 ; + RECT 70.73 0 70.99 0.26 ; + END + END A_DIN[6] + PIN A_BIST_DIN[25] + DIRECTION INPUT ; + USE SIGNAL ; + ANTENNAPARTIALMETALAREA 1.6263 LAYER Metal2 ; + ANTENNAMODEL OXIDE1 ; + ANTENNAGATEAREA 0.20085 LAYER Metal2 ; + ANTENNAMAXAREACAR 9.365945 LAYER Metal2 ; + PORT + LAYER Metal2 ; + RECT 344.795 0 345.055 0.26 ; + END + END A_BIST_DIN[25] + PIN A_BIST_DIN[6] + DIRECTION INPUT ; + USE SIGNAL ; + ANTENNAPARTIALMETALAREA 1.6263 LAYER Metal2 ; + ANTENNAMODEL OXIDE1 ; + ANTENNAGATEAREA 0.20085 LAYER Metal2 ; + ANTENNAMAXAREACAR 9.365945 LAYER Metal2 ; + PORT + LAYER Metal2 ; + RECT 71.585 0 71.845 0.26 ; + END + END A_BIST_DIN[6] + PIN A_BM[25] + DIRECTION INPUT ; + USE SIGNAL ; + ANTENNAPARTIALMETALAREA 0.7215 LAYER Metal2 ; + ANTENNAMODEL OXIDE1 ; + ANTENNAGATEAREA 0.20085 LAYER Metal2 ; + ANTENNAMAXAREACAR 4.498382 LAYER Metal2 ; + PORT + LAYER Metal2 ; + RECT 337.81 0 338.07 0.26 ; + END + END A_BM[25] + PIN A_BM[6] + DIRECTION INPUT ; + USE SIGNAL ; + ANTENNAPARTIALMETALAREA 0.7215 LAYER Metal2 ; + ANTENNAMODEL OXIDE1 ; + ANTENNAGATEAREA 0.20085 LAYER Metal2 ; + ANTENNAMAXAREACAR 4.498382 LAYER Metal2 ; + PORT + LAYER Metal2 ; + RECT 78.57 0 78.83 0.26 ; + END + END A_BM[6] + PIN A_BIST_BM[25] + DIRECTION INPUT ; + USE SIGNAL ; + ANTENNAPARTIALMETALAREA 0.7605 LAYER Metal2 ; + ANTENNAMODEL OXIDE1 ; + ANTENNAGATEAREA 0.20085 LAYER Metal2 ; + ANTENNAMAXAREACAR 5.055265 LAYER Metal2 ; + PORT + LAYER Metal2 ; + RECT 339.185 0 339.445 0.26 ; + END + END A_BIST_BM[25] + PIN A_BIST_BM[6] + DIRECTION INPUT ; + USE SIGNAL ; + ANTENNAPARTIALMETALAREA 0.7605 LAYER Metal2 ; + ANTENNAMODEL OXIDE1 ; + ANTENNAGATEAREA 0.20085 LAYER Metal2 ; + ANTENNAMAXAREACAR 5.055265 LAYER Metal2 ; + PORT + LAYER Metal2 ; + RECT 77.195 0 77.455 0.26 ; + END + END A_BIST_BM[6] + PIN A_DOUT[25] + DIRECTION OUTPUT ; + USE SIGNAL ; + ANTENNAPARTIALMETALAREA 3.7095 LAYER Metal2 ; + ANTENNADIFFAREA 0.988 LAYER Metal2 ; + PORT + LAYER Metal2 ; + RECT 338.32 0 338.58 0.26 ; + END + END A_DOUT[25] + PIN A_DOUT[6] + DIRECTION OUTPUT ; + USE SIGNAL ; + ANTENNAPARTIALMETALAREA 3.7095 LAYER Metal2 ; + ANTENNADIFFAREA 0.988 LAYER Metal2 ; + PORT + LAYER Metal2 ; + RECT 78.06 0 78.32 0.26 ; + END + END A_DOUT[6] + PIN A_DIN[26] + DIRECTION INPUT ; + USE SIGNAL ; + ANTENNAPARTIALMETALAREA 1.794 LAYER Metal2 ; + ANTENNAMODEL OXIDE1 ; + ANTENNAGATEAREA 0.20085 LAYER Metal2 ; + ANTENNAMAXAREACAR 9.838188 LAYER Metal2 ; + PORT + LAYER Metal2 ; + RECT 356.89 0 357.15 0.26 ; + END + END A_DIN[26] + PIN A_DIN[5] + DIRECTION INPUT ; + USE SIGNAL ; + ANTENNAPARTIALMETALAREA 1.794 LAYER Metal2 ; + ANTENNAMODEL OXIDE1 ; + ANTENNAGATEAREA 0.20085 LAYER Metal2 ; + ANTENNAMAXAREACAR 9.838188 LAYER Metal2 ; + PORT + LAYER Metal2 ; + RECT 59.49 0 59.75 0.26 ; + END + END A_DIN[5] + PIN A_BIST_DIN[26] + DIRECTION INPUT ; + USE SIGNAL ; + ANTENNAPARTIALMETALAREA 1.6263 LAYER Metal2 ; + ANTENNAMODEL OXIDE1 ; + ANTENNAGATEAREA 0.20085 LAYER Metal2 ; + ANTENNAMAXAREACAR 9.365945 LAYER Metal2 ; + PORT + LAYER Metal2 ; + RECT 356.035 0 356.295 0.26 ; + END + END A_BIST_DIN[26] + PIN A_BIST_DIN[5] + DIRECTION INPUT ; + USE SIGNAL ; + ANTENNAPARTIALMETALAREA 1.6263 LAYER Metal2 ; + ANTENNAMODEL OXIDE1 ; + ANTENNAGATEAREA 0.20085 LAYER Metal2 ; + ANTENNAMAXAREACAR 9.365945 LAYER Metal2 ; + PORT + LAYER Metal2 ; + RECT 60.345 0 60.605 0.26 ; + END + END A_BIST_DIN[5] + PIN A_BM[26] + DIRECTION INPUT ; + USE SIGNAL ; + ANTENNAPARTIALMETALAREA 0.7215 LAYER Metal2 ; + ANTENNAMODEL OXIDE1 ; + ANTENNAGATEAREA 0.20085 LAYER Metal2 ; + ANTENNAMAXAREACAR 4.498382 LAYER Metal2 ; + PORT + LAYER Metal2 ; + RECT 349.05 0 349.31 0.26 ; + END + END A_BM[26] + PIN A_BM[5] + DIRECTION INPUT ; + USE SIGNAL ; + ANTENNAPARTIALMETALAREA 0.7215 LAYER Metal2 ; + ANTENNAMODEL OXIDE1 ; + ANTENNAGATEAREA 0.20085 LAYER Metal2 ; + ANTENNAMAXAREACAR 4.498382 LAYER Metal2 ; + PORT + LAYER Metal2 ; + RECT 67.33 0 67.59 0.26 ; + END + END A_BM[5] + PIN A_BIST_BM[26] + DIRECTION INPUT ; + USE SIGNAL ; + ANTENNAPARTIALMETALAREA 0.7605 LAYER Metal2 ; + ANTENNAMODEL OXIDE1 ; + ANTENNAGATEAREA 0.20085 LAYER Metal2 ; + ANTENNAMAXAREACAR 5.055265 LAYER Metal2 ; + PORT + LAYER Metal2 ; + RECT 350.425 0 350.685 0.26 ; + END + END A_BIST_BM[26] + PIN A_BIST_BM[5] + DIRECTION INPUT ; + USE SIGNAL ; + ANTENNAPARTIALMETALAREA 0.7605 LAYER Metal2 ; + ANTENNAMODEL OXIDE1 ; + ANTENNAGATEAREA 0.20085 LAYER Metal2 ; + ANTENNAMAXAREACAR 5.055265 LAYER Metal2 ; + PORT + LAYER Metal2 ; + RECT 65.955 0 66.215 0.26 ; + END + END A_BIST_BM[5] + PIN A_DOUT[26] + DIRECTION OUTPUT ; + USE SIGNAL ; + ANTENNAPARTIALMETALAREA 3.7095 LAYER Metal2 ; + ANTENNADIFFAREA 0.988 LAYER Metal2 ; + PORT + LAYER Metal2 ; + RECT 349.56 0 349.82 0.26 ; + END + END A_DOUT[26] + PIN A_DOUT[5] + DIRECTION OUTPUT ; + USE SIGNAL ; + ANTENNAPARTIALMETALAREA 3.7095 LAYER Metal2 ; + ANTENNADIFFAREA 0.988 LAYER Metal2 ; + PORT + LAYER Metal2 ; + RECT 66.82 0 67.08 0.26 ; + END + END A_DOUT[5] + PIN A_DIN[27] + DIRECTION INPUT ; + USE SIGNAL ; + ANTENNAPARTIALMETALAREA 1.794 LAYER Metal2 ; + ANTENNAMODEL OXIDE1 ; + ANTENNAGATEAREA 0.20085 LAYER Metal2 ; + ANTENNAMAXAREACAR 9.838188 LAYER Metal2 ; + PORT + LAYER Metal2 ; + RECT 368.13 0 368.39 0.26 ; + END + END A_DIN[27] + PIN A_DIN[4] + DIRECTION INPUT ; + USE SIGNAL ; + ANTENNAPARTIALMETALAREA 1.794 LAYER Metal2 ; + ANTENNAMODEL OXIDE1 ; + ANTENNAGATEAREA 0.20085 LAYER Metal2 ; + ANTENNAMAXAREACAR 9.838188 LAYER Metal2 ; + PORT + LAYER Metal2 ; + RECT 48.25 0 48.51 0.26 ; + END + END A_DIN[4] + PIN A_BIST_DIN[27] + DIRECTION INPUT ; + USE SIGNAL ; + ANTENNAPARTIALMETALAREA 1.6263 LAYER Metal2 ; + ANTENNAMODEL OXIDE1 ; + ANTENNAGATEAREA 0.20085 LAYER Metal2 ; + ANTENNAMAXAREACAR 9.365945 LAYER Metal2 ; + PORT + LAYER Metal2 ; + RECT 367.275 0 367.535 0.26 ; + END + END A_BIST_DIN[27] + PIN A_BIST_DIN[4] + DIRECTION INPUT ; + USE SIGNAL ; + ANTENNAPARTIALMETALAREA 1.6263 LAYER Metal2 ; + ANTENNAMODEL OXIDE1 ; + ANTENNAGATEAREA 0.20085 LAYER Metal2 ; + ANTENNAMAXAREACAR 9.365945 LAYER Metal2 ; + PORT + LAYER Metal2 ; + RECT 49.105 0 49.365 0.26 ; + END + END A_BIST_DIN[4] + PIN A_BM[27] + DIRECTION INPUT ; + USE SIGNAL ; + ANTENNAPARTIALMETALAREA 0.7215 LAYER Metal2 ; + ANTENNAMODEL OXIDE1 ; + ANTENNAGATEAREA 0.20085 LAYER Metal2 ; + ANTENNAMAXAREACAR 4.498382 LAYER Metal2 ; + PORT + LAYER Metal2 ; + RECT 360.29 0 360.55 0.26 ; + END + END A_BM[27] + PIN A_BM[4] + DIRECTION INPUT ; + USE SIGNAL ; + ANTENNAPARTIALMETALAREA 0.7215 LAYER Metal2 ; + ANTENNAMODEL OXIDE1 ; + ANTENNAGATEAREA 0.20085 LAYER Metal2 ; + ANTENNAMAXAREACAR 4.498382 LAYER Metal2 ; + PORT + LAYER Metal2 ; + RECT 56.09 0 56.35 0.26 ; + END + END A_BM[4] + PIN A_BIST_BM[27] + DIRECTION INPUT ; + USE SIGNAL ; + ANTENNAPARTIALMETALAREA 0.7605 LAYER Metal2 ; + ANTENNAMODEL OXIDE1 ; + ANTENNAGATEAREA 0.20085 LAYER Metal2 ; + ANTENNAMAXAREACAR 5.055265 LAYER Metal2 ; + PORT + LAYER Metal2 ; + RECT 361.665 0 361.925 0.26 ; + END + END A_BIST_BM[27] + PIN A_BIST_BM[4] + DIRECTION INPUT ; + USE SIGNAL ; + ANTENNAPARTIALMETALAREA 0.7605 LAYER Metal2 ; + ANTENNAMODEL OXIDE1 ; + ANTENNAGATEAREA 0.20085 LAYER Metal2 ; + ANTENNAMAXAREACAR 5.055265 LAYER Metal2 ; + PORT + LAYER Metal2 ; + RECT 54.715 0 54.975 0.26 ; + END + END A_BIST_BM[4] + PIN A_DOUT[27] + DIRECTION OUTPUT ; + USE SIGNAL ; + ANTENNAPARTIALMETALAREA 3.7095 LAYER Metal2 ; + ANTENNADIFFAREA 0.988 LAYER Metal2 ; + PORT + LAYER Metal2 ; + RECT 360.8 0 361.06 0.26 ; + END + END A_DOUT[27] + PIN A_DOUT[4] + DIRECTION OUTPUT ; + USE SIGNAL ; + ANTENNAPARTIALMETALAREA 3.7095 LAYER Metal2 ; + ANTENNADIFFAREA 0.988 LAYER Metal2 ; + PORT + LAYER Metal2 ; + RECT 55.58 0 55.84 0.26 ; + END + END A_DOUT[4] + PIN A_DIN[28] + DIRECTION INPUT ; + USE SIGNAL ; + ANTENNAPARTIALMETALAREA 1.794 LAYER Metal2 ; + ANTENNAMODEL OXIDE1 ; + ANTENNAGATEAREA 0.20085 LAYER Metal2 ; + ANTENNAMAXAREACAR 9.838188 LAYER Metal2 ; + PORT + LAYER Metal2 ; + RECT 379.37 0 379.63 0.26 ; + END + END A_DIN[28] + PIN A_DIN[3] + DIRECTION INPUT ; + USE SIGNAL ; + ANTENNAPARTIALMETALAREA 1.794 LAYER Metal2 ; + ANTENNAMODEL OXIDE1 ; + ANTENNAGATEAREA 0.20085 LAYER Metal2 ; + ANTENNAMAXAREACAR 9.838188 LAYER Metal2 ; + PORT + LAYER Metal2 ; + RECT 37.01 0 37.27 0.26 ; + END + END A_DIN[3] + PIN A_BIST_DIN[28] + DIRECTION INPUT ; + USE SIGNAL ; + ANTENNAPARTIALMETALAREA 1.6263 LAYER Metal2 ; + ANTENNAMODEL OXIDE1 ; + ANTENNAGATEAREA 0.20085 LAYER Metal2 ; + ANTENNAMAXAREACAR 9.365945 LAYER Metal2 ; + PORT + LAYER Metal2 ; + RECT 378.515 0 378.775 0.26 ; + END + END A_BIST_DIN[28] + PIN A_BIST_DIN[3] + DIRECTION INPUT ; + USE SIGNAL ; + ANTENNAPARTIALMETALAREA 1.6263 LAYER Metal2 ; + ANTENNAMODEL OXIDE1 ; + ANTENNAGATEAREA 0.20085 LAYER Metal2 ; + ANTENNAMAXAREACAR 9.365945 LAYER Metal2 ; + PORT + LAYER Metal2 ; + RECT 37.865 0 38.125 0.26 ; + END + END A_BIST_DIN[3] + PIN A_BM[28] + DIRECTION INPUT ; + USE SIGNAL ; + ANTENNAPARTIALMETALAREA 0.7215 LAYER Metal2 ; + ANTENNAMODEL OXIDE1 ; + ANTENNAGATEAREA 0.20085 LAYER Metal2 ; + ANTENNAMAXAREACAR 4.498382 LAYER Metal2 ; + PORT + LAYER Metal2 ; + RECT 371.53 0 371.79 0.26 ; + END + END A_BM[28] + PIN A_BM[3] + DIRECTION INPUT ; + USE SIGNAL ; + ANTENNAPARTIALMETALAREA 0.7215 LAYER Metal2 ; + ANTENNAMODEL OXIDE1 ; + ANTENNAGATEAREA 0.20085 LAYER Metal2 ; + ANTENNAMAXAREACAR 4.498382 LAYER Metal2 ; + PORT + LAYER Metal2 ; + RECT 44.85 0 45.11 0.26 ; + END + END A_BM[3] + PIN A_BIST_BM[28] + DIRECTION INPUT ; + USE SIGNAL ; + ANTENNAPARTIALMETALAREA 0.7605 LAYER Metal2 ; + ANTENNAMODEL OXIDE1 ; + ANTENNAGATEAREA 0.20085 LAYER Metal2 ; + ANTENNAMAXAREACAR 5.055265 LAYER Metal2 ; + PORT + LAYER Metal2 ; + RECT 372.905 0 373.165 0.26 ; + END + END A_BIST_BM[28] + PIN A_BIST_BM[3] + DIRECTION INPUT ; + USE SIGNAL ; + ANTENNAPARTIALMETALAREA 0.7605 LAYER Metal2 ; + ANTENNAMODEL OXIDE1 ; + ANTENNAGATEAREA 0.20085 LAYER Metal2 ; + ANTENNAMAXAREACAR 5.055265 LAYER Metal2 ; + PORT + LAYER Metal2 ; + RECT 43.475 0 43.735 0.26 ; + END + END A_BIST_BM[3] + PIN A_DOUT[28] + DIRECTION OUTPUT ; + USE SIGNAL ; + ANTENNAPARTIALMETALAREA 3.7095 LAYER Metal2 ; + ANTENNADIFFAREA 0.988 LAYER Metal2 ; + PORT + LAYER Metal2 ; + RECT 372.04 0 372.3 0.26 ; + END + END A_DOUT[28] + PIN A_DOUT[3] + DIRECTION OUTPUT ; + USE SIGNAL ; + ANTENNAPARTIALMETALAREA 3.7095 LAYER Metal2 ; + ANTENNADIFFAREA 0.988 LAYER Metal2 ; + PORT + LAYER Metal2 ; + RECT 44.34 0 44.6 0.26 ; + END + END A_DOUT[3] + PIN A_DIN[29] + DIRECTION INPUT ; + USE SIGNAL ; + ANTENNAPARTIALMETALAREA 1.794 LAYER Metal2 ; + ANTENNAMODEL OXIDE1 ; + ANTENNAGATEAREA 0.20085 LAYER Metal2 ; + ANTENNAMAXAREACAR 9.838188 LAYER Metal2 ; + PORT + LAYER Metal2 ; + RECT 390.61 0 390.87 0.26 ; + END + END A_DIN[29] + PIN A_DIN[2] + DIRECTION INPUT ; + USE SIGNAL ; + ANTENNAPARTIALMETALAREA 1.794 LAYER Metal2 ; + ANTENNAMODEL OXIDE1 ; + ANTENNAGATEAREA 0.20085 LAYER Metal2 ; + ANTENNAMAXAREACAR 9.838188 LAYER Metal2 ; + PORT + LAYER Metal2 ; + RECT 25.77 0 26.03 0.26 ; + END + END A_DIN[2] + PIN A_BIST_DIN[29] + DIRECTION INPUT ; + USE SIGNAL ; + ANTENNAPARTIALMETALAREA 1.6263 LAYER Metal2 ; + ANTENNAMODEL OXIDE1 ; + ANTENNAGATEAREA 0.20085 LAYER Metal2 ; + ANTENNAMAXAREACAR 9.365945 LAYER Metal2 ; + PORT + LAYER Metal2 ; + RECT 389.755 0 390.015 0.26 ; + END + END A_BIST_DIN[29] + PIN A_BIST_DIN[2] + DIRECTION INPUT ; + USE SIGNAL ; + ANTENNAPARTIALMETALAREA 1.6263 LAYER Metal2 ; + ANTENNAMODEL OXIDE1 ; + ANTENNAGATEAREA 0.20085 LAYER Metal2 ; + ANTENNAMAXAREACAR 9.365945 LAYER Metal2 ; + PORT + LAYER Metal2 ; + RECT 26.625 0 26.885 0.26 ; + END + END A_BIST_DIN[2] + PIN A_BM[29] + DIRECTION INPUT ; + USE SIGNAL ; + ANTENNAPARTIALMETALAREA 0.7215 LAYER Metal2 ; + ANTENNAMODEL OXIDE1 ; + ANTENNAGATEAREA 0.20085 LAYER Metal2 ; + ANTENNAMAXAREACAR 4.498382 LAYER Metal2 ; + PORT + LAYER Metal2 ; + RECT 382.77 0 383.03 0.26 ; + END + END A_BM[29] + PIN A_BM[2] + DIRECTION INPUT ; + USE SIGNAL ; + ANTENNAPARTIALMETALAREA 0.7215 LAYER Metal2 ; + ANTENNAMODEL OXIDE1 ; + ANTENNAGATEAREA 0.20085 LAYER Metal2 ; + ANTENNAMAXAREACAR 4.498382 LAYER Metal2 ; + PORT + LAYER Metal2 ; + RECT 33.61 0 33.87 0.26 ; + END + END A_BM[2] + PIN A_BIST_BM[29] + DIRECTION INPUT ; + USE SIGNAL ; + ANTENNAPARTIALMETALAREA 0.7605 LAYER Metal2 ; + ANTENNAMODEL OXIDE1 ; + ANTENNAGATEAREA 0.20085 LAYER Metal2 ; + ANTENNAMAXAREACAR 5.055265 LAYER Metal2 ; + PORT + LAYER Metal2 ; + RECT 384.145 0 384.405 0.26 ; + END + END A_BIST_BM[29] + PIN A_BIST_BM[2] + DIRECTION INPUT ; + USE SIGNAL ; + ANTENNAPARTIALMETALAREA 0.7605 LAYER Metal2 ; + ANTENNAMODEL OXIDE1 ; + ANTENNAGATEAREA 0.20085 LAYER Metal2 ; + ANTENNAMAXAREACAR 5.055265 LAYER Metal2 ; + PORT + LAYER Metal2 ; + RECT 32.235 0 32.495 0.26 ; + END + END A_BIST_BM[2] + PIN A_DOUT[29] + DIRECTION OUTPUT ; + USE SIGNAL ; + ANTENNAPARTIALMETALAREA 3.7095 LAYER Metal2 ; + ANTENNADIFFAREA 0.988 LAYER Metal2 ; + PORT + LAYER Metal2 ; + RECT 383.28 0 383.54 0.26 ; + END + END A_DOUT[29] + PIN A_DOUT[2] + DIRECTION OUTPUT ; + USE SIGNAL ; + ANTENNAPARTIALMETALAREA 3.7095 LAYER Metal2 ; + ANTENNADIFFAREA 0.988 LAYER Metal2 ; + PORT + LAYER Metal2 ; + RECT 33.1 0 33.36 0.26 ; + END + END A_DOUT[2] + PIN A_DIN[30] + DIRECTION INPUT ; + USE SIGNAL ; + ANTENNAPARTIALMETALAREA 1.794 LAYER Metal2 ; + ANTENNAMODEL OXIDE1 ; + ANTENNAGATEAREA 0.20085 LAYER Metal2 ; + ANTENNAMAXAREACAR 9.838188 LAYER Metal2 ; + PORT + LAYER Metal2 ; + RECT 401.85 0 402.11 0.26 ; + END + END A_DIN[30] + PIN A_DIN[1] + DIRECTION INPUT ; + USE SIGNAL ; + ANTENNAPARTIALMETALAREA 1.794 LAYER Metal2 ; + ANTENNAMODEL OXIDE1 ; + ANTENNAGATEAREA 0.20085 LAYER Metal2 ; + ANTENNAMAXAREACAR 9.838188 LAYER Metal2 ; + PORT + LAYER Metal2 ; + RECT 14.53 0 14.79 0.26 ; + END + END A_DIN[1] + PIN A_BIST_DIN[30] + DIRECTION INPUT ; + USE SIGNAL ; + ANTENNAPARTIALMETALAREA 1.6263 LAYER Metal2 ; + ANTENNAMODEL OXIDE1 ; + ANTENNAGATEAREA 0.20085 LAYER Metal2 ; + ANTENNAMAXAREACAR 9.365945 LAYER Metal2 ; + PORT + LAYER Metal2 ; + RECT 400.995 0 401.255 0.26 ; + END + END A_BIST_DIN[30] + PIN A_BIST_DIN[1] + DIRECTION INPUT ; + USE SIGNAL ; + ANTENNAPARTIALMETALAREA 1.6263 LAYER Metal2 ; + ANTENNAMODEL OXIDE1 ; + ANTENNAGATEAREA 0.20085 LAYER Metal2 ; + ANTENNAMAXAREACAR 9.365945 LAYER Metal2 ; + PORT + LAYER Metal2 ; + RECT 15.385 0 15.645 0.26 ; + END + END A_BIST_DIN[1] + PIN A_BM[30] + DIRECTION INPUT ; + USE SIGNAL ; + ANTENNAPARTIALMETALAREA 0.7215 LAYER Metal2 ; + ANTENNAMODEL OXIDE1 ; + ANTENNAGATEAREA 0.20085 LAYER Metal2 ; + ANTENNAMAXAREACAR 4.498382 LAYER Metal2 ; + PORT + LAYER Metal2 ; + RECT 394.01 0 394.27 0.26 ; + END + END A_BM[30] + PIN A_BM[1] + DIRECTION INPUT ; + USE SIGNAL ; + ANTENNAPARTIALMETALAREA 0.7215 LAYER Metal2 ; + ANTENNAMODEL OXIDE1 ; + ANTENNAGATEAREA 0.20085 LAYER Metal2 ; + ANTENNAMAXAREACAR 4.498382 LAYER Metal2 ; + PORT + LAYER Metal2 ; + RECT 22.37 0 22.63 0.26 ; + END + END A_BM[1] + PIN A_BIST_BM[30] + DIRECTION INPUT ; + USE SIGNAL ; + ANTENNAPARTIALMETALAREA 0.7605 LAYER Metal2 ; + ANTENNAMODEL OXIDE1 ; + ANTENNAGATEAREA 0.20085 LAYER Metal2 ; + ANTENNAMAXAREACAR 5.055265 LAYER Metal2 ; + PORT + LAYER Metal2 ; + RECT 395.385 0 395.645 0.26 ; + END + END A_BIST_BM[30] + PIN A_BIST_BM[1] + DIRECTION INPUT ; + USE SIGNAL ; + ANTENNAPARTIALMETALAREA 0.7605 LAYER Metal2 ; + ANTENNAMODEL OXIDE1 ; + ANTENNAGATEAREA 0.20085 LAYER Metal2 ; + ANTENNAMAXAREACAR 5.055265 LAYER Metal2 ; + PORT + LAYER Metal2 ; + RECT 20.995 0 21.255 0.26 ; + END + END A_BIST_BM[1] + PIN A_DOUT[30] + DIRECTION OUTPUT ; + USE SIGNAL ; + ANTENNAPARTIALMETALAREA 3.7095 LAYER Metal2 ; + ANTENNADIFFAREA 0.988 LAYER Metal2 ; + PORT + LAYER Metal2 ; + RECT 394.52 0 394.78 0.26 ; + END + END A_DOUT[30] + PIN A_DOUT[1] + DIRECTION OUTPUT ; + USE SIGNAL ; + ANTENNAPARTIALMETALAREA 3.7095 LAYER Metal2 ; + ANTENNADIFFAREA 0.988 LAYER Metal2 ; + PORT + LAYER Metal2 ; + RECT 21.86 0 22.12 0.26 ; + END + END A_DOUT[1] + PIN A_DIN[31] + DIRECTION INPUT ; + USE SIGNAL ; + ANTENNAPARTIALMETALAREA 1.794 LAYER Metal2 ; + ANTENNAMODEL OXIDE1 ; + ANTENNAGATEAREA 0.20085 LAYER Metal2 ; + ANTENNAMAXAREACAR 9.838188 LAYER Metal2 ; + PORT + LAYER Metal2 ; + RECT 413.09 0 413.35 0.26 ; + END + END A_DIN[31] + PIN A_DIN[0] + DIRECTION INPUT ; + USE SIGNAL ; + ANTENNAPARTIALMETALAREA 1.794 LAYER Metal2 ; + ANTENNAMODEL OXIDE1 ; + ANTENNAGATEAREA 0.20085 LAYER Metal2 ; + ANTENNAMAXAREACAR 9.838188 LAYER Metal2 ; + PORT + LAYER Metal2 ; + RECT 3.29 0 3.55 0.26 ; + END + END A_DIN[0] + PIN A_BIST_DIN[31] + DIRECTION INPUT ; + USE SIGNAL ; + ANTENNAPARTIALMETALAREA 1.6263 LAYER Metal2 ; + ANTENNAMODEL OXIDE1 ; + ANTENNAGATEAREA 0.20085 LAYER Metal2 ; + ANTENNAMAXAREACAR 9.365945 LAYER Metal2 ; + PORT + LAYER Metal2 ; + RECT 412.235 0 412.495 0.26 ; + END + END A_BIST_DIN[31] + PIN A_BIST_DIN[0] + DIRECTION INPUT ; + USE SIGNAL ; + ANTENNAPARTIALMETALAREA 1.6263 LAYER Metal2 ; + ANTENNAMODEL OXIDE1 ; + ANTENNAGATEAREA 0.20085 LAYER Metal2 ; + ANTENNAMAXAREACAR 9.365945 LAYER Metal2 ; + PORT + LAYER Metal2 ; + RECT 4.145 0 4.405 0.26 ; + END + END A_BIST_DIN[0] + PIN A_BM[31] + DIRECTION INPUT ; + USE SIGNAL ; + ANTENNAPARTIALMETALAREA 0.7215 LAYER Metal2 ; + ANTENNAMODEL OXIDE1 ; + ANTENNAGATEAREA 0.20085 LAYER Metal2 ; + ANTENNAMAXAREACAR 4.498382 LAYER Metal2 ; + PORT + LAYER Metal2 ; + RECT 405.25 0 405.51 0.26 ; + END + END A_BM[31] + PIN A_BM[0] + DIRECTION INPUT ; + USE SIGNAL ; + ANTENNAPARTIALMETALAREA 0.7215 LAYER Metal2 ; + ANTENNAMODEL OXIDE1 ; + ANTENNAGATEAREA 0.20085 LAYER Metal2 ; + ANTENNAMAXAREACAR 4.498382 LAYER Metal2 ; + PORT + LAYER Metal2 ; + RECT 11.13 0 11.39 0.26 ; + END + END A_BM[0] + PIN A_BIST_BM[31] + DIRECTION INPUT ; + USE SIGNAL ; + ANTENNAPARTIALMETALAREA 0.7605 LAYER Metal2 ; + ANTENNAMODEL OXIDE1 ; + ANTENNAGATEAREA 0.20085 LAYER Metal2 ; + ANTENNAMAXAREACAR 5.055265 LAYER Metal2 ; + PORT + LAYER Metal2 ; + RECT 406.625 0 406.885 0.26 ; + END + END A_BIST_BM[31] + PIN A_BIST_BM[0] + DIRECTION INPUT ; + USE SIGNAL ; + ANTENNAPARTIALMETALAREA 0.7605 LAYER Metal2 ; + ANTENNAMODEL OXIDE1 ; + ANTENNAGATEAREA 0.20085 LAYER Metal2 ; + ANTENNAMAXAREACAR 5.055265 LAYER Metal2 ; + PORT + LAYER Metal2 ; + RECT 9.755 0 10.015 0.26 ; + END + END A_BIST_BM[0] + PIN A_DOUT[31] + DIRECTION OUTPUT ; + USE SIGNAL ; + ANTENNAPARTIALMETALAREA 3.7095 LAYER Metal2 ; + ANTENNADIFFAREA 0.988 LAYER Metal2 ; + PORT + LAYER Metal2 ; + RECT 405.76 0 406.02 0.26 ; + END + END A_DOUT[31] + PIN A_DOUT[0] + DIRECTION OUTPUT ; + USE SIGNAL ; + ANTENNAPARTIALMETALAREA 3.7095 LAYER Metal2 ; + ANTENNADIFFAREA 0.988 LAYER Metal2 ; + PORT + LAYER Metal2 ; + RECT 10.62 0 10.88 0.26 ; + END + END A_DOUT[0] + PIN A_ADDR[0] + DIRECTION INPUT ; + USE SIGNAL ; + ANTENNAPARTIALMETALAREA 8.9011 LAYER Metal2 ; + ANTENNAMODEL OXIDE1 ; + ANTENNAGATEAREA 0.20085 LAYER Metal2 ; + ANTENNAMAXAREACAR 45.223301 LAYER Metal2 ; + PORT + LAYER Metal2 ; + RECT 204.52 0 204.78 0.26 ; + END + END A_ADDR[0] + PIN A_BIST_ADDR[0] + DIRECTION INPUT ; + USE SIGNAL ; + ANTENNAPARTIALMETALAREA 9.6967 LAYER Metal2 ; + ANTENNAMODEL OXIDE1 ; + ANTENNAGATEAREA 0.20085 LAYER Metal2 ; + ANTENNAMAXAREACAR 49.184466 LAYER Metal2 ; + PORT + LAYER Metal2 ; + RECT 209.11 0 209.37 0.26 ; + END + END A_BIST_ADDR[0] + PIN A_ADDR[1] + DIRECTION INPUT ; + USE SIGNAL ; + ANTENNAPARTIALMETALAREA 7.774 LAYER Metal2 ; + ANTENNAMODEL OXIDE1 ; + ANTENNAGATEAREA 0.20085 LAYER Metal2 ; + ANTENNAMAXAREACAR 39.656958 LAYER Metal2 ; + PORT + LAYER Metal2 ; + RECT 204.01 0 204.27 0.26 ; + END + END A_ADDR[1] + PIN A_BIST_ADDR[1] + DIRECTION INPUT ; + USE SIGNAL ; + ANTENNAPARTIALMETALAREA 8.5696 LAYER Metal2 ; + ANTENNAMODEL OXIDE1 ; + ANTENNAGATEAREA 0.20085 LAYER Metal2 ; + ANTENNAMAXAREACAR 43.618123 LAYER Metal2 ; + PORT + LAYER Metal2 ; + RECT 208.6 0 208.86 0.26 ; + END + END A_BIST_ADDR[1] + PIN A_ADDR[2] + DIRECTION INPUT ; + USE SIGNAL ; + ANTENNAPARTIALMETALAREA 10.6327 LAYER Metal2 ; + ANTENNAPARTIALMETALAREA 1.5246 LAYER Metal3 ; + ANTENNAPARTIALCUTAREA 0.0722 LAYER Via2 ; + ANTENNAMODEL OXIDE1 ; + ANTENNAGATEAREA 0.20085 LAYER Metal3 ; + ANTENNAMAXAREACAR 9.415982 LAYER Metal3 ; + PORT + LAYER Metal2 ; + RECT 212.17 0 212.43 0.26 ; + END + END A_ADDR[2] + PIN A_BIST_ADDR[2] + DIRECTION INPUT ; + USE SIGNAL ; + ANTENNAPARTIALMETALAREA 10.6327 LAYER Metal2 ; + ANTENNAPARTIALMETALAREA 1.0962 LAYER Metal3 ; + ANTENNAPARTIALCUTAREA 0.0722 LAYER Via2 ; + ANTENNAMODEL OXIDE1 ; + ANTENNAGATEAREA 0.20085 LAYER Metal3 ; + ANTENNAMAXAREACAR 7.813791 LAYER Metal3 ; + PORT + LAYER Metal2 ; + RECT 212.68 0 212.94 0.26 ; + END + END A_BIST_ADDR[2] + PIN A_ADDR[3] + DIRECTION INPUT ; + USE SIGNAL ; + ANTENNAPARTIALMETALAREA 10.6327 LAYER Metal2 ; + ANTENNAPARTIALMETALAREA 3.8367 LAYER Metal3 ; + ANTENNAPARTIALCUTAREA 0.0722 LAYER Via2 ; + ANTENNAMODEL OXIDE1 ; + ANTENNAGATEAREA 0.20085 LAYER Metal3 ; + ANTENNAMAXAREACAR 20.927558 LAYER Metal3 ; + PORT + LAYER Metal2 ; + RECT 211.15 0 211.41 0.26 ; + END + END A_ADDR[3] + PIN A_BIST_ADDR[3] + DIRECTION INPUT ; + USE SIGNAL ; + ANTENNAPARTIALMETALAREA 10.6327 LAYER Metal2 ; + ANTENNAPARTIALMETALAREA 3.5175 LAYER Metal3 ; + ANTENNAPARTIALCUTAREA 0.0722 LAYER Via2 ; + ANTENNAMODEL OXIDE1 ; + ANTENNAGATEAREA 0.20085 LAYER Metal3 ; + ANTENNAMAXAREACAR 19.869057 LAYER Metal3 ; + PORT + LAYER Metal2 ; + RECT 211.66 0 211.92 0.26 ; + END + END A_BIST_ADDR[3] + PIN A_ADDR[4] + DIRECTION INPUT ; + USE SIGNAL ; + ANTENNAPARTIALMETALAREA 12.1979 LAYER Metal2 ; + ANTENNAMODEL OXIDE1 ; + ANTENNAGATEAREA 0.20085 LAYER Metal2 ; + ANTENNAMAXAREACAR 61.63754 LAYER Metal2 ; + PORT + LAYER Metal2 ; + RECT 214.72 0 214.98 0.26 ; + END + END A_ADDR[4] + PIN A_BIST_ADDR[4] + DIRECTION INPUT ; + USE SIGNAL ; + ANTENNAPARTIALMETALAREA 11.9327 LAYER Metal2 ; + ANTENNAMODEL OXIDE1 ; + ANTENNAGATEAREA 0.20085 LAYER Metal2 ; + ANTENNAMAXAREACAR 60.317152 LAYER Metal2 ; + PORT + LAYER Metal2 ; + RECT 214.21 0 214.47 0.26 ; + END + END A_BIST_ADDR[4] + PIN A_ADDR[5] + DIRECTION INPUT ; + USE SIGNAL ; + ANTENNAPARTIALMETALAREA 13.9269 LAYER Metal2 ; + ANTENNAMODEL OXIDE1 ; + ANTENNAGATEAREA 0.20085 LAYER Metal2 ; + ANTENNAMAXAREACAR 70.245955 LAYER Metal2 ; + PORT + LAYER Metal2 ; + RECT 213.7 0 213.96 0.26 ; + END + END A_ADDR[5] + PIN A_BIST_ADDR[5] + DIRECTION INPUT ; + USE SIGNAL ; + ANTENNAPARTIALMETALAREA 13.6617 LAYER Metal2 ; + ANTENNAMODEL OXIDE1 ; + ANTENNAGATEAREA 0.20085 LAYER Metal2 ; + ANTENNAMAXAREACAR 68.925566 LAYER Metal2 ; + PORT + LAYER Metal2 ; + RECT 213.19 0 213.45 0.26 ; + END + END A_BIST_ADDR[5] + PIN A_ADDR[6] + DIRECTION INPUT ; + USE SIGNAL ; + ANTENNAPARTIALMETALAREA 10.9525 LAYER Metal2 ; + ANTENNAMODEL OXIDE1 ; + ANTENNAGATEAREA 0.20085 LAYER Metal2 ; + ANTENNAMAXAREACAR 55.436893 LAYER Metal2 ; + PORT + LAYER Metal2 ; + RECT 192.28 0 192.54 0.26 ; + END + END A_ADDR[6] + PIN A_BIST_ADDR[6] + DIRECTION INPUT ; + USE SIGNAL ; + ANTENNAPARTIALMETALAREA 10.6771 LAYER Metal2 ; + ANTENNAMODEL OXIDE1 ; + ANTENNAGATEAREA 0.20085 LAYER Metal2 ; + ANTENNAMAXAREACAR 54.065721 LAYER Metal2 ; + PORT + LAYER Metal2 ; + RECT 192.79 0 193.05 0.26 ; + END + END A_BIST_ADDR[6] + PIN A_ADDR[7] + DIRECTION INPUT ; + USE SIGNAL ; + ANTENNAPARTIALMETALAREA 12.4163 LAYER Metal2 ; + ANTENNAMODEL OXIDE1 ; + ANTENNAGATEAREA 0.20085 LAYER Metal2 ; + ANTENNAMAXAREACAR 62.724919 LAYER Metal2 ; + PORT + LAYER Metal2 ; + RECT 193.3 0 193.56 0.26 ; + END + END A_ADDR[7] + PIN A_BIST_ADDR[7] + DIRECTION INPUT ; + USE SIGNAL ; + ANTENNAPARTIALMETALAREA 12.1511 LAYER Metal2 ; + ANTENNAMODEL OXIDE1 ; + ANTENNAGATEAREA 0.20085 LAYER Metal2 ; + ANTENNAMAXAREACAR 61.404531 LAYER Metal2 ; + PORT + LAYER Metal2 ; + RECT 193.81 0 194.07 0.26 ; + END + END A_BIST_ADDR[7] + PIN A_ADDR[8] + DIRECTION INPUT ; + USE SIGNAL ; + ANTENNAPARTIALMETALAREA 10.3675 LAYER Metal2 ; + ANTENNAPARTIALMETALAREA 1.5897 LAYER Metal3 ; + ANTENNAPARTIALCUTAREA 0.0722 LAYER Via2 ; + ANTENNAMODEL OXIDE1 ; + ANTENNAGATEAREA 0.20085 LAYER Metal3 ; + ANTENNAMAXAREACAR 9.740105 LAYER Metal3 ; + PORT + LAYER Metal2 ; + RECT 222.37 0 222.63 0.26 ; + END + END A_ADDR[8] + PIN A_BIST_ADDR[8] + DIRECTION INPUT ; + USE SIGNAL ; + ANTENNAPARTIALMETALAREA 10.3675 LAYER Metal2 ; + ANTENNAPARTIALMETALAREA 1.3755 LAYER Metal3 ; + ANTENNAPARTIALCUTAREA 0.0722 LAYER Via2 ; + ANTENNAMODEL OXIDE1 ; + ANTENNAGATEAREA 0.20085 LAYER Metal3 ; + ANTENNAMAXAREACAR 9.204381 LAYER Metal3 ; + PORT + LAYER Metal2 ; + RECT 222.88 0 223.14 0.26 ; + END + END A_BIST_ADDR[8] + PIN A_ADDR[9] + DIRECTION INPUT ; + USE SIGNAL ; + ANTENNAPARTIALMETALAREA 12.2633 LAYER Metal2 ; + ANTENNAMODEL OXIDE1 ; + ANTENNAGATEAREA 0.20085 LAYER Metal2 ; + ANTENNAMAXAREACAR 61.963157 LAYER Metal2 ; + PORT + LAYER Metal2 ; + RECT 217.27 0 217.53 0.26 ; + END + END A_ADDR[9] + PIN A_BIST_ADDR[9] + DIRECTION INPUT ; + USE SIGNAL ; + ANTENNAPARTIALMETALAREA 12.0083 LAYER Metal2 ; + ANTENNAMODEL OXIDE1 ; + ANTENNAGATEAREA 0.20085 LAYER Metal2 ; + ANTENNAMAXAREACAR 60.693552 LAYER Metal2 ; + PORT + LAYER Metal2 ; + RECT 217.78 0 218.04 0.26 ; + END + END A_BIST_ADDR[9] + PIN A_CLK + DIRECTION INPUT ; + USE SIGNAL ; + ANTENNAPARTIALMETALAREA 4.0547 LAYER Metal2 ; + ANTENNAMODEL OXIDE1 ; + ANTENNAGATEAREA 0.20085 LAYER Metal2 ; + ANTENNAMAXAREACAR 21.093851 LAYER Metal2 ; + PORT + LAYER Metal2 ; + RECT 202.48 0 202.74 0.26 ; + END + END A_CLK + PIN A_REN + DIRECTION INPUT ; + USE SIGNAL ; + ANTENNAPARTIALMETALAREA 3.99505 LAYER Metal2 ; + ANTENNAMODEL OXIDE1 ; + ANTENNAGATEAREA 0.20085 LAYER Metal2 ; + ANTENNAMAXAREACAR 20.796863 LAYER Metal2 ; + PORT + LAYER Metal2 ; + RECT 206.05 0 206.31 0.26 ; + END + END A_REN + PIN A_WEN + DIRECTION INPUT ; + USE SIGNAL ; + ANTENNAPARTIALMETALAREA 2.8847 LAYER Metal2 ; + ANTENNAMODEL OXIDE1 ; + ANTENNAGATEAREA 0.20085 LAYER Metal2 ; + ANTENNAMAXAREACAR 15.268608 LAYER Metal2 ; + PORT + LAYER Metal2 ; + RECT 205.54 0 205.8 0.26 ; + END + END A_WEN + PIN A_MEN + DIRECTION INPUT ; + USE SIGNAL ; + ANTENNAPARTIALMETALAREA 3.0247 LAYER Metal2 ; + ANTENNAMODEL OXIDE1 ; + ANTENNAGATEAREA 0.20085 LAYER Metal2 ; + ANTENNAMAXAREACAR 15.965646 LAYER Metal2 ; + PORT + LAYER Metal2 ; + RECT 202.99 0 203.25 0.26 ; + END + END A_MEN + PIN A_DLY + DIRECTION INPUT ; + USE SIGNAL ; + ANTENNAPARTIALMETALAREA 6.058 LAYER Metal2 ; + ANTENNAMODEL OXIDE1 ; + ANTENNAGATEAREA 0.3367 LAYER Metal2 ; + ANTENNAMAXAREACAR 18.532819 LAYER Metal2 ; + PORT + LAYER Metal2 ; + RECT 224.41 0 224.67 0.26 ; + END + END A_DLY + PIN A_BIST_EN + DIRECTION INPUT ; + USE SIGNAL ; + ANTENNAPARTIALMETALAREA 3.9871 LAYER Metal2 ; + ANTENNAPARTIALMETALAREA 203.31695 LAYER Metal3 ; + ANTENNAPARTIALCUTAREA 0.0722 LAYER Via2 ; + ANTENNAMODEL OXIDE1 ; + ANTENNAGATEAREA 1.43 LAYER Metal2 ; + ANTENNAGATEAREA 27.885 LAYER Metal3 ; + ANTENNAMAXAREACAR 3.213636 LAYER Metal2 ; + ANTENNAMAXAREACAR 17.563993 LAYER Metal3 ; + ANTENNAMAXCUTCAR 0.151469 LAYER Via2 ; + PORT + LAYER Metal2 ; + RECT 205.03 0 205.29 0.26 ; + END + END A_BIST_EN + PIN A_BIST_CLK + DIRECTION INPUT ; + USE SIGNAL ; + ANTENNAPARTIALMETALAREA 4.1639 LAYER Metal2 ; + ANTENNAMODEL OXIDE1 ; + ANTENNAGATEAREA 0.20085 LAYER Metal2 ; + ANTENNAMAXAREACAR 21.953448 LAYER Metal2 ; + PORT + LAYER Metal2 ; + RECT 200.95 0 201.21 0.26 ; + END + END A_BIST_CLK + PIN A_BIST_REN + DIRECTION INPUT ; + USE SIGNAL ; + ANTENNAPARTIALMETALAREA 4.1119 LAYER Metal2 ; + ANTENNAMODEL OXIDE1 ; + ANTENNAGATEAREA 0.20085 LAYER Metal2 ; + ANTENNAMAXAREACAR 21.694548 LAYER Metal2 ; + PORT + LAYER Metal2 ; + RECT 207.58 0 207.84 0.26 ; + END + END A_BIST_REN + PIN A_BIST_WEN + DIRECTION INPUT ; + USE SIGNAL ; + ANTENNAPARTIALMETALAREA 2.9051 LAYER Metal2 ; + ANTENNAMODEL OXIDE1 ; + ANTENNAGATEAREA 0.20085 LAYER Metal2 ; + ANTENNAMAXAREACAR 15.686084 LAYER Metal2 ; + PORT + LAYER Metal2 ; + RECT 207.07 0 207.33 0.26 ; + END + END A_BIST_WEN + PIN A_BIST_MEN + DIRECTION INPUT ; + USE SIGNAL ; + ANTENNAPARTIALMETALAREA 2.8977 LAYER Metal2 ; + ANTENNAMODEL OXIDE1 ; + ANTENNAGATEAREA 0.20085 LAYER Metal2 ; + ANTENNAMAXAREACAR 15.649241 LAYER Metal2 ; + PORT + LAYER Metal2 ; + RECT 201.46 0 201.72 0.26 ; + END + END A_BIST_MEN + OBS + LAYER Metal1 ; + RECT 0 0 416.64 336.46 ; + LAYER Metal2 ; + RECT 0.105 45.465 0.305 336.435 ; + RECT 1.1 335.705 1.3 336.435 ; + RECT 3.29 0.52 3.55 5.16 ; + RECT 2.77 4.9 3.55 5.16 ; + RECT 2.77 4.9 3.03 6.64 ; + RECT 1.92 335.705 2.12 336.435 ; + RECT 2.415 335.705 2.615 336.435 ; + RECT 2.915 335.705 3.115 336.435 ; + RECT 3.415 335.705 3.615 336.435 ; + RECT 3.91 335.705 4.11 336.435 ; + RECT 4.655 0.17 5.425 0.94 ; + RECT 4.655 0.17 4.915 12.9 ; + RECT 5.165 0.17 5.425 12.9 ; + RECT 4.145 0.52 4.405 5.815 ; + RECT 4.73 335.705 4.93 336.435 ; + RECT 5.675 0.17 6.445 0.43 ; + RECT 5.675 0.17 5.935 11.5 ; + RECT 6.185 0.17 6.445 11.5 ; + RECT 5.225 335.705 5.425 336.435 ; + RECT 5.725 335.705 5.925 336.435 ; + RECT 6.225 335.705 6.425 336.435 ; + RECT 7.715 0.17 8.485 0.43 ; + RECT 7.715 0.17 7.975 10.48 ; + RECT 8.225 0.17 8.485 10.99 ; + RECT 6.72 335.705 6.92 336.435 ; + RECT 7.54 335.705 7.74 336.435 ; + RECT 8.735 0.17 9.505 0.94 ; + RECT 8.735 0.17 8.995 8.7 ; + RECT 9.245 0.17 9.505 12.9 ; + RECT 8.035 335.705 8.235 336.435 ; + RECT 8.535 335.705 8.735 336.435 ; + RECT 9.035 335.705 9.235 336.435 ; + RECT 9.53 335.705 9.73 336.435 ; + RECT 9.755 0.52 10.015 2.485 ; + RECT 10.35 335.705 10.55 336.435 ; + RECT 10.62 0.52 10.88 14.11 ; + RECT 10.845 335.705 11.045 336.435 ; + RECT 11.13 0.52 11.39 2.335 ; + RECT 11.345 335.705 11.545 336.435 ; + RECT 11.845 335.705 12.045 336.435 ; + RECT 12.34 335.705 12.54 336.435 ; + RECT 14.53 0.52 14.79 5.16 ; + RECT 14.01 4.9 14.79 5.16 ; + RECT 14.01 4.9 14.27 6.64 ; + RECT 13.16 335.705 13.36 336.435 ; + RECT 13.655 335.705 13.855 336.435 ; + RECT 14.155 335.705 14.355 336.435 ; + RECT 14.655 335.705 14.855 336.435 ; + RECT 15.15 335.705 15.35 336.435 ; + RECT 15.895 0.17 16.665 0.94 ; + RECT 15.895 0.17 16.155 12.9 ; + RECT 16.405 0.17 16.665 12.9 ; + RECT 15.385 0.52 15.645 5.815 ; + RECT 15.97 335.705 16.17 336.435 ; + RECT 16.915 0.17 17.685 0.43 ; + RECT 16.915 0.17 17.175 11.5 ; + RECT 17.425 0.17 17.685 11.5 ; + RECT 16.465 335.705 16.665 336.435 ; + RECT 16.965 335.705 17.165 336.435 ; + RECT 17.465 335.705 17.665 336.435 ; + RECT 18.955 0.17 19.725 0.43 ; + RECT 18.955 0.17 19.215 10.48 ; + RECT 19.465 0.17 19.725 10.99 ; + RECT 17.96 335.705 18.16 336.435 ; + RECT 18.78 335.705 18.98 336.435 ; + RECT 19.975 0.17 20.745 0.94 ; + RECT 19.975 0.17 20.235 8.7 ; + RECT 20.485 0.17 20.745 12.9 ; + RECT 19.275 335.705 19.475 336.435 ; + RECT 19.775 335.705 19.975 336.435 ; + RECT 20.275 335.705 20.475 336.435 ; + RECT 20.77 335.705 20.97 336.435 ; + RECT 20.995 0.52 21.255 2.485 ; + RECT 21.59 335.705 21.79 336.435 ; + RECT 21.86 0.52 22.12 14.11 ; + RECT 22.085 335.705 22.285 336.435 ; + RECT 22.37 0.52 22.63 2.335 ; + RECT 22.585 335.705 22.785 336.435 ; + RECT 23.085 335.705 23.285 336.435 ; + RECT 23.58 335.705 23.78 336.435 ; + RECT 25.77 0.52 26.03 5.16 ; + RECT 25.25 4.9 26.03 5.16 ; + RECT 25.25 4.9 25.51 6.64 ; + RECT 24.4 335.705 24.6 336.435 ; + RECT 24.895 335.705 25.095 336.435 ; + RECT 25.395 335.705 25.595 336.435 ; + RECT 25.895 335.705 26.095 336.435 ; + RECT 26.39 335.705 26.59 336.435 ; + RECT 27.135 0.17 27.905 0.94 ; + RECT 27.135 0.17 27.395 12.9 ; + RECT 27.645 0.17 27.905 12.9 ; + RECT 26.625 0.52 26.885 5.815 ; + RECT 27.21 335.705 27.41 336.435 ; + RECT 28.155 0.17 28.925 0.43 ; + RECT 28.155 0.17 28.415 11.5 ; + RECT 28.665 0.17 28.925 11.5 ; + RECT 27.705 335.705 27.905 336.435 ; + RECT 28.205 335.705 28.405 336.435 ; + RECT 28.705 335.705 28.905 336.435 ; + RECT 30.195 0.17 30.965 0.43 ; + RECT 30.195 0.17 30.455 10.48 ; + RECT 30.705 0.17 30.965 10.99 ; + RECT 29.2 335.705 29.4 336.435 ; + RECT 30.02 335.705 30.22 336.435 ; + RECT 31.215 0.17 31.985 0.94 ; + RECT 31.215 0.17 31.475 8.7 ; + RECT 31.725 0.17 31.985 12.9 ; + RECT 30.515 335.705 30.715 336.435 ; + RECT 31.015 335.705 31.215 336.435 ; + RECT 31.515 335.705 31.715 336.435 ; + RECT 32.01 335.705 32.21 336.435 ; + RECT 32.235 0.52 32.495 2.485 ; + RECT 32.83 335.705 33.03 336.435 ; + RECT 33.1 0.52 33.36 14.11 ; + RECT 33.325 335.705 33.525 336.435 ; + RECT 33.61 0.52 33.87 2.335 ; + RECT 33.825 335.705 34.025 336.435 ; + RECT 34.325 335.705 34.525 336.435 ; + RECT 34.82 335.705 35.02 336.435 ; + RECT 37.01 0.52 37.27 5.16 ; + RECT 36.49 4.9 37.27 5.16 ; + RECT 36.49 4.9 36.75 6.64 ; + RECT 35.64 335.705 35.84 336.435 ; + RECT 36.135 335.705 36.335 336.435 ; + RECT 36.635 335.705 36.835 336.435 ; + RECT 37.135 335.705 37.335 336.435 ; + RECT 37.63 335.705 37.83 336.435 ; + RECT 38.375 0.17 39.145 0.94 ; + RECT 38.375 0.17 38.635 12.9 ; + RECT 38.885 0.17 39.145 12.9 ; + RECT 37.865 0.52 38.125 5.815 ; + RECT 38.45 335.705 38.65 336.435 ; + RECT 39.395 0.17 40.165 0.43 ; + RECT 39.395 0.17 39.655 11.5 ; + RECT 39.905 0.17 40.165 11.5 ; + RECT 38.945 335.705 39.145 336.435 ; + RECT 39.445 335.705 39.645 336.435 ; + RECT 39.945 335.705 40.145 336.435 ; + RECT 41.435 0.17 42.205 0.43 ; + RECT 41.435 0.17 41.695 10.48 ; + RECT 41.945 0.17 42.205 10.99 ; + RECT 40.44 335.705 40.64 336.435 ; + RECT 41.26 335.705 41.46 336.435 ; + RECT 42.455 0.17 43.225 0.94 ; + RECT 42.455 0.17 42.715 8.7 ; + RECT 42.965 0.17 43.225 12.9 ; + RECT 41.755 335.705 41.955 336.435 ; + RECT 42.255 335.705 42.455 336.435 ; + RECT 42.755 335.705 42.955 336.435 ; + RECT 43.25 335.705 43.45 336.435 ; + RECT 43.475 0.52 43.735 2.485 ; + RECT 44.07 335.705 44.27 336.435 ; + RECT 44.34 0.52 44.6 14.11 ; + RECT 44.565 335.705 44.765 336.435 ; + RECT 44.85 0.52 45.11 2.335 ; + RECT 45.065 335.705 45.265 336.435 ; + RECT 45.565 335.705 45.765 336.435 ; + RECT 46.06 335.705 46.26 336.435 ; + RECT 48.25 0.52 48.51 5.16 ; + RECT 47.73 4.9 48.51 5.16 ; + RECT 47.73 4.9 47.99 6.64 ; + RECT 46.88 335.705 47.08 336.435 ; + RECT 47.375 335.705 47.575 336.435 ; + RECT 47.875 335.705 48.075 336.435 ; + RECT 48.375 335.705 48.575 336.435 ; + RECT 48.87 335.705 49.07 336.435 ; + RECT 49.615 0.17 50.385 0.94 ; + RECT 49.615 0.17 49.875 12.9 ; + RECT 50.125 0.17 50.385 12.9 ; + RECT 49.105 0.52 49.365 5.815 ; + RECT 49.69 335.705 49.89 336.435 ; + RECT 50.635 0.17 51.405 0.43 ; + RECT 50.635 0.17 50.895 11.5 ; + RECT 51.145 0.17 51.405 11.5 ; + RECT 50.185 335.705 50.385 336.435 ; + RECT 50.685 335.705 50.885 336.435 ; + RECT 51.185 335.705 51.385 336.435 ; + RECT 52.675 0.17 53.445 0.43 ; + RECT 52.675 0.17 52.935 10.48 ; + RECT 53.185 0.17 53.445 10.99 ; + RECT 51.68 335.705 51.88 336.435 ; + RECT 52.5 335.705 52.7 336.435 ; + RECT 53.695 0.17 54.465 0.94 ; + RECT 53.695 0.17 53.955 8.7 ; + RECT 54.205 0.17 54.465 12.9 ; + RECT 52.995 335.705 53.195 336.435 ; + RECT 53.495 335.705 53.695 336.435 ; + RECT 53.995 335.705 54.195 336.435 ; + RECT 54.49 335.705 54.69 336.435 ; + RECT 54.715 0.52 54.975 2.485 ; + RECT 55.31 335.705 55.51 336.435 ; + RECT 55.58 0.52 55.84 14.11 ; + RECT 55.805 335.705 56.005 336.435 ; + RECT 56.09 0.52 56.35 2.335 ; + RECT 56.305 335.705 56.505 336.435 ; + RECT 56.805 335.705 57.005 336.435 ; + RECT 57.3 335.705 57.5 336.435 ; + RECT 59.49 0.52 59.75 5.16 ; + RECT 58.97 4.9 59.75 5.16 ; + RECT 58.97 4.9 59.23 6.64 ; + RECT 58.12 335.705 58.32 336.435 ; + RECT 58.615 335.705 58.815 336.435 ; + RECT 59.115 335.705 59.315 336.435 ; + RECT 59.615 335.705 59.815 336.435 ; + RECT 60.11 335.705 60.31 336.435 ; + RECT 60.855 0.17 61.625 0.94 ; + RECT 60.855 0.17 61.115 12.9 ; + RECT 61.365 0.17 61.625 12.9 ; + RECT 60.345 0.52 60.605 5.815 ; + RECT 60.93 335.705 61.13 336.435 ; + RECT 61.875 0.17 62.645 0.43 ; + RECT 61.875 0.17 62.135 11.5 ; + RECT 62.385 0.17 62.645 11.5 ; + RECT 61.425 335.705 61.625 336.435 ; + RECT 61.925 335.705 62.125 336.435 ; + RECT 62.425 335.705 62.625 336.435 ; + RECT 63.915 0.17 64.685 0.43 ; + RECT 63.915 0.17 64.175 10.48 ; + RECT 64.425 0.17 64.685 10.99 ; + RECT 62.92 335.705 63.12 336.435 ; + RECT 63.74 335.705 63.94 336.435 ; + RECT 64.935 0.17 65.705 0.94 ; + RECT 64.935 0.17 65.195 8.7 ; + RECT 65.445 0.17 65.705 12.9 ; + RECT 64.235 335.705 64.435 336.435 ; + RECT 64.735 335.705 64.935 336.435 ; + RECT 65.235 335.705 65.435 336.435 ; + RECT 65.73 335.705 65.93 336.435 ; + RECT 65.955 0.52 66.215 2.485 ; + RECT 66.55 335.705 66.75 336.435 ; + RECT 66.82 0.52 67.08 14.11 ; + RECT 67.045 335.705 67.245 336.435 ; + RECT 67.33 0.52 67.59 2.335 ; + RECT 67.545 335.705 67.745 336.435 ; + RECT 68.045 335.705 68.245 336.435 ; + RECT 68.54 335.705 68.74 336.435 ; + RECT 70.73 0.52 70.99 5.16 ; + RECT 70.21 4.9 70.99 5.16 ; + RECT 70.21 4.9 70.47 6.64 ; + RECT 69.36 335.705 69.56 336.435 ; + RECT 69.855 335.705 70.055 336.435 ; + RECT 70.355 335.705 70.555 336.435 ; + RECT 70.855 335.705 71.055 336.435 ; + RECT 71.35 335.705 71.55 336.435 ; + RECT 72.095 0.17 72.865 0.94 ; + RECT 72.095 0.17 72.355 12.9 ; + RECT 72.605 0.17 72.865 12.9 ; + RECT 71.585 0.52 71.845 5.815 ; + RECT 72.17 335.705 72.37 336.435 ; + RECT 73.115 0.17 73.885 0.43 ; + RECT 73.115 0.17 73.375 11.5 ; + RECT 73.625 0.17 73.885 11.5 ; + RECT 72.665 335.705 72.865 336.435 ; + RECT 73.165 335.705 73.365 336.435 ; + RECT 73.665 335.705 73.865 336.435 ; + RECT 75.155 0.17 75.925 0.43 ; + RECT 75.155 0.17 75.415 10.48 ; + RECT 75.665 0.17 75.925 10.99 ; + RECT 74.16 335.705 74.36 336.435 ; + RECT 74.98 335.705 75.18 336.435 ; + RECT 76.175 0.17 76.945 0.94 ; + RECT 76.175 0.17 76.435 8.7 ; + RECT 76.685 0.17 76.945 12.9 ; + RECT 75.475 335.705 75.675 336.435 ; + RECT 75.975 335.705 76.175 336.435 ; + RECT 76.475 335.705 76.675 336.435 ; + RECT 76.97 335.705 77.17 336.435 ; + RECT 77.195 0.52 77.455 2.485 ; + RECT 77.79 335.705 77.99 336.435 ; + RECT 78.06 0.52 78.32 14.11 ; + RECT 78.285 335.705 78.485 336.435 ; + RECT 78.57 0.52 78.83 2.335 ; + RECT 78.785 335.705 78.985 336.435 ; + RECT 79.285 335.705 79.485 336.435 ; + RECT 79.78 335.705 79.98 336.435 ; + RECT 81.97 0.52 82.23 5.16 ; + RECT 81.45 4.9 82.23 5.16 ; + RECT 81.45 4.9 81.71 6.64 ; + RECT 80.6 335.705 80.8 336.435 ; + RECT 81.095 335.705 81.295 336.435 ; + RECT 81.595 335.705 81.795 336.435 ; + RECT 82.095 335.705 82.295 336.435 ; + RECT 82.59 335.705 82.79 336.435 ; + RECT 83.335 0.17 84.105 0.94 ; + RECT 83.335 0.17 83.595 12.9 ; + RECT 83.845 0.17 84.105 12.9 ; + RECT 82.825 0.52 83.085 5.815 ; + RECT 83.41 335.705 83.61 336.435 ; + RECT 84.355 0.17 85.125 0.43 ; + RECT 84.355 0.17 84.615 11.5 ; + RECT 84.865 0.17 85.125 11.5 ; + RECT 83.905 335.705 84.105 336.435 ; + RECT 84.405 335.705 84.605 336.435 ; + RECT 84.905 335.705 85.105 336.435 ; + RECT 86.395 0.17 87.165 0.43 ; + RECT 86.395 0.17 86.655 10.48 ; + RECT 86.905 0.17 87.165 10.99 ; + RECT 85.4 335.705 85.6 336.435 ; + RECT 86.22 335.705 86.42 336.435 ; + RECT 87.415 0.17 88.185 0.94 ; + RECT 87.415 0.17 87.675 8.7 ; + RECT 87.925 0.17 88.185 12.9 ; + RECT 86.715 335.705 86.915 336.435 ; + RECT 87.215 335.705 87.415 336.435 ; + RECT 87.715 335.705 87.915 336.435 ; + RECT 88.21 335.705 88.41 336.435 ; + RECT 88.435 0.52 88.695 2.485 ; + RECT 89.03 335.705 89.23 336.435 ; + RECT 89.3 0.52 89.56 14.11 ; + RECT 89.525 335.705 89.725 336.435 ; + RECT 89.81 0.52 90.07 2.335 ; + RECT 90.025 335.705 90.225 336.435 ; + RECT 90.525 335.705 90.725 336.435 ; + RECT 91.02 335.705 91.22 336.435 ; + RECT 93.21 0.52 93.47 5.16 ; + RECT 92.69 4.9 93.47 5.16 ; + RECT 92.69 4.9 92.95 6.64 ; + RECT 91.84 335.705 92.04 336.435 ; + RECT 92.335 335.705 92.535 336.435 ; + RECT 92.835 335.705 93.035 336.435 ; + RECT 93.335 335.705 93.535 336.435 ; + RECT 93.83 335.705 94.03 336.435 ; + RECT 94.575 0.17 95.345 0.94 ; + RECT 94.575 0.17 94.835 12.9 ; + RECT 95.085 0.17 95.345 12.9 ; + RECT 94.065 0.52 94.325 5.815 ; + RECT 94.65 335.705 94.85 336.435 ; + RECT 95.595 0.17 96.365 0.43 ; + RECT 95.595 0.17 95.855 11.5 ; + RECT 96.105 0.17 96.365 11.5 ; + RECT 95.145 335.705 95.345 336.435 ; + RECT 95.645 335.705 95.845 336.435 ; + RECT 96.145 335.705 96.345 336.435 ; + RECT 97.635 0.17 98.405 0.43 ; + RECT 97.635 0.17 97.895 10.48 ; + RECT 98.145 0.17 98.405 10.99 ; + RECT 96.64 335.705 96.84 336.435 ; + RECT 97.46 335.705 97.66 336.435 ; + RECT 98.655 0.17 99.425 0.94 ; + RECT 98.655 0.17 98.915 8.7 ; + RECT 99.165 0.17 99.425 12.9 ; + RECT 97.955 335.705 98.155 336.435 ; + RECT 98.455 335.705 98.655 336.435 ; + RECT 98.955 335.705 99.155 336.435 ; + RECT 99.45 335.705 99.65 336.435 ; + RECT 99.675 0.52 99.935 2.485 ; + RECT 100.27 335.705 100.47 336.435 ; + RECT 100.54 0.52 100.8 14.11 ; + RECT 100.765 335.705 100.965 336.435 ; + RECT 101.05 0.52 101.31 2.335 ; + RECT 101.265 335.705 101.465 336.435 ; + RECT 101.765 335.705 101.965 336.435 ; + RECT 102.26 335.705 102.46 336.435 ; + RECT 104.45 0.52 104.71 5.16 ; + RECT 103.93 4.9 104.71 5.16 ; + RECT 103.93 4.9 104.19 6.64 ; + RECT 103.08 335.705 103.28 336.435 ; + RECT 103.575 335.705 103.775 336.435 ; + RECT 104.075 335.705 104.275 336.435 ; + RECT 104.575 335.705 104.775 336.435 ; + RECT 105.07 335.705 105.27 336.435 ; + RECT 105.815 0.17 106.585 0.94 ; + RECT 105.815 0.17 106.075 12.9 ; + RECT 106.325 0.17 106.585 12.9 ; + RECT 105.305 0.52 105.565 5.815 ; + RECT 105.89 335.705 106.09 336.435 ; + RECT 106.835 0.17 107.605 0.43 ; + RECT 106.835 0.17 107.095 11.5 ; + RECT 107.345 0.17 107.605 11.5 ; + RECT 106.385 335.705 106.585 336.435 ; + RECT 106.885 335.705 107.085 336.435 ; + RECT 107.385 335.705 107.585 336.435 ; + RECT 108.875 0.17 109.645 0.43 ; + RECT 108.875 0.17 109.135 10.48 ; + RECT 109.385 0.17 109.645 10.99 ; + RECT 107.88 335.705 108.08 336.435 ; + RECT 108.7 335.705 108.9 336.435 ; + RECT 109.895 0.17 110.665 0.94 ; + RECT 109.895 0.17 110.155 8.7 ; + RECT 110.405 0.17 110.665 12.9 ; + RECT 109.195 335.705 109.395 336.435 ; + RECT 109.695 335.705 109.895 336.435 ; + RECT 110.195 335.705 110.395 336.435 ; + RECT 110.69 335.705 110.89 336.435 ; + RECT 110.915 0.52 111.175 2.485 ; + RECT 111.51 335.705 111.71 336.435 ; + RECT 111.78 0.52 112.04 14.11 ; + RECT 112.005 335.705 112.205 336.435 ; + RECT 112.29 0.52 112.55 2.335 ; + RECT 112.505 335.705 112.705 336.435 ; + RECT 113.005 335.705 113.205 336.435 ; + RECT 113.5 335.705 113.7 336.435 ; + RECT 115.69 0.52 115.95 5.16 ; + RECT 115.17 4.9 115.95 5.16 ; + RECT 115.17 4.9 115.43 6.64 ; + RECT 114.32 335.705 114.52 336.435 ; + RECT 114.815 335.705 115.015 336.435 ; + RECT 115.315 335.705 115.515 336.435 ; + RECT 115.815 335.705 116.015 336.435 ; + RECT 116.31 335.705 116.51 336.435 ; + RECT 117.055 0.17 117.825 0.94 ; + RECT 117.055 0.17 117.315 12.9 ; + RECT 117.565 0.17 117.825 12.9 ; + RECT 116.545 0.52 116.805 5.815 ; + RECT 117.13 335.705 117.33 336.435 ; + RECT 118.075 0.17 118.845 0.43 ; + RECT 118.075 0.17 118.335 11.5 ; + RECT 118.585 0.17 118.845 11.5 ; + RECT 117.625 335.705 117.825 336.435 ; + RECT 118.125 335.705 118.325 336.435 ; + RECT 118.625 335.705 118.825 336.435 ; + RECT 120.115 0.17 120.885 0.43 ; + RECT 120.115 0.17 120.375 10.48 ; + RECT 120.625 0.17 120.885 10.99 ; + RECT 119.12 335.705 119.32 336.435 ; + RECT 119.94 335.705 120.14 336.435 ; + RECT 121.135 0.17 121.905 0.94 ; + RECT 121.135 0.17 121.395 8.7 ; + RECT 121.645 0.17 121.905 12.9 ; + RECT 120.435 335.705 120.635 336.435 ; + RECT 120.935 335.705 121.135 336.435 ; + RECT 121.435 335.705 121.635 336.435 ; + RECT 121.93 335.705 122.13 336.435 ; + RECT 122.155 0.52 122.415 2.485 ; + RECT 122.75 335.705 122.95 336.435 ; + RECT 123.02 0.52 123.28 14.11 ; + RECT 123.245 335.705 123.445 336.435 ; + RECT 123.53 0.52 123.79 2.335 ; + RECT 123.745 335.705 123.945 336.435 ; + RECT 124.245 335.705 124.445 336.435 ; + RECT 124.74 335.705 124.94 336.435 ; + RECT 126.93 0.52 127.19 5.16 ; + RECT 126.41 4.9 127.19 5.16 ; + RECT 126.41 4.9 126.67 6.64 ; + RECT 125.56 335.705 125.76 336.435 ; + RECT 126.055 335.705 126.255 336.435 ; + RECT 126.555 335.705 126.755 336.435 ; + RECT 127.055 335.705 127.255 336.435 ; + RECT 127.55 335.705 127.75 336.435 ; + RECT 128.295 0.17 129.065 0.94 ; + RECT 128.295 0.17 128.555 12.9 ; + RECT 128.805 0.17 129.065 12.9 ; + RECT 127.785 0.52 128.045 5.815 ; + RECT 128.37 335.705 128.57 336.435 ; + RECT 129.315 0.17 130.085 0.43 ; + RECT 129.315 0.17 129.575 11.5 ; + RECT 129.825 0.17 130.085 11.5 ; + RECT 128.865 335.705 129.065 336.435 ; + RECT 129.365 335.705 129.565 336.435 ; + RECT 129.865 335.705 130.065 336.435 ; + RECT 131.355 0.17 132.125 0.43 ; + RECT 131.355 0.17 131.615 10.48 ; + RECT 131.865 0.17 132.125 10.99 ; + RECT 130.36 335.705 130.56 336.435 ; + RECT 131.18 335.705 131.38 336.435 ; + RECT 132.375 0.17 133.145 0.94 ; + RECT 132.375 0.17 132.635 8.7 ; + RECT 132.885 0.17 133.145 12.9 ; + RECT 131.675 335.705 131.875 336.435 ; + RECT 132.175 335.705 132.375 336.435 ; + RECT 132.675 335.705 132.875 336.435 ; + RECT 133.17 335.705 133.37 336.435 ; + RECT 133.395 0.52 133.655 2.485 ; + RECT 133.99 335.705 134.19 336.435 ; + RECT 134.26 0.52 134.52 14.11 ; + RECT 134.485 335.705 134.685 336.435 ; + RECT 134.77 0.52 135.03 2.335 ; + RECT 134.985 335.705 135.185 336.435 ; + RECT 135.485 335.705 135.685 336.435 ; + RECT 135.98 335.705 136.18 336.435 ; + RECT 138.17 0.52 138.43 5.16 ; + RECT 137.65 4.9 138.43 5.16 ; + RECT 137.65 4.9 137.91 6.64 ; + RECT 136.8 335.705 137 336.435 ; + RECT 137.295 335.705 137.495 336.435 ; + RECT 137.795 335.705 137.995 336.435 ; + RECT 138.295 335.705 138.495 336.435 ; + RECT 138.79 335.705 138.99 336.435 ; + RECT 139.535 0.17 140.305 0.94 ; + RECT 139.535 0.17 139.795 12.9 ; + RECT 140.045 0.17 140.305 12.9 ; + RECT 139.025 0.52 139.285 5.815 ; + RECT 139.61 335.705 139.81 336.435 ; + RECT 140.555 0.17 141.325 0.43 ; + RECT 140.555 0.17 140.815 11.5 ; + RECT 141.065 0.17 141.325 11.5 ; + RECT 140.105 335.705 140.305 336.435 ; + RECT 140.605 335.705 140.805 336.435 ; + RECT 141.105 335.705 141.305 336.435 ; + RECT 142.595 0.17 143.365 0.43 ; + RECT 142.595 0.17 142.855 10.48 ; + RECT 143.105 0.17 143.365 10.99 ; + RECT 141.6 335.705 141.8 336.435 ; + RECT 142.42 335.705 142.62 336.435 ; + RECT 143.615 0.17 144.385 0.94 ; + RECT 143.615 0.17 143.875 8.7 ; + RECT 144.125 0.17 144.385 12.9 ; + RECT 142.915 335.705 143.115 336.435 ; + RECT 143.415 335.705 143.615 336.435 ; + RECT 143.915 335.705 144.115 336.435 ; + RECT 144.41 335.705 144.61 336.435 ; + RECT 144.635 0.52 144.895 2.485 ; + RECT 145.23 335.705 145.43 336.435 ; + RECT 145.5 0.52 145.76 14.11 ; + RECT 145.725 335.705 145.925 336.435 ; + RECT 146.01 0.52 146.27 2.335 ; + RECT 146.225 335.705 146.425 336.435 ; + RECT 146.725 335.705 146.925 336.435 ; + RECT 147.22 335.705 147.42 336.435 ; + RECT 149.41 0.52 149.67 5.16 ; + RECT 148.89 4.9 149.67 5.16 ; + RECT 148.89 4.9 149.15 6.64 ; + RECT 148.04 335.705 148.24 336.435 ; + RECT 148.535 335.705 148.735 336.435 ; + RECT 149.035 335.705 149.235 336.435 ; + RECT 149.535 335.705 149.735 336.435 ; + RECT 150.03 335.705 150.23 336.435 ; + RECT 150.775 0.17 151.545 0.94 ; + RECT 150.775 0.17 151.035 12.9 ; + RECT 151.285 0.17 151.545 12.9 ; + RECT 150.265 0.52 150.525 5.815 ; + RECT 150.85 335.705 151.05 336.435 ; + RECT 151.795 0.17 152.565 0.43 ; + RECT 151.795 0.17 152.055 11.5 ; + RECT 152.305 0.17 152.565 11.5 ; + RECT 151.345 335.705 151.545 336.435 ; + RECT 151.845 335.705 152.045 336.435 ; + RECT 152.345 335.705 152.545 336.435 ; + RECT 153.835 0.17 154.605 0.43 ; + RECT 153.835 0.17 154.095 10.48 ; + RECT 154.345 0.17 154.605 10.99 ; + RECT 152.84 335.705 153.04 336.435 ; + RECT 153.66 335.705 153.86 336.435 ; + RECT 154.855 0.17 155.625 0.94 ; + RECT 154.855 0.17 155.115 8.7 ; + RECT 155.365 0.17 155.625 12.9 ; + RECT 154.155 335.705 154.355 336.435 ; + RECT 154.655 335.705 154.855 336.435 ; + RECT 155.155 335.705 155.355 336.435 ; + RECT 155.65 335.705 155.85 336.435 ; + RECT 155.875 0.52 156.135 2.485 ; + RECT 156.47 335.705 156.67 336.435 ; + RECT 156.74 0.52 157 14.11 ; + RECT 156.965 335.705 157.165 336.435 ; + RECT 157.25 0.52 157.51 2.335 ; + RECT 157.465 335.705 157.665 336.435 ; + RECT 157.965 335.705 158.165 336.435 ; + RECT 158.46 335.705 158.66 336.435 ; + RECT 160.65 0.52 160.91 5.16 ; + RECT 160.13 4.9 160.91 5.16 ; + RECT 160.13 4.9 160.39 6.64 ; + RECT 159.28 335.705 159.48 336.435 ; + RECT 159.775 335.705 159.975 336.435 ; + RECT 160.275 335.705 160.475 336.435 ; + RECT 160.775 335.705 160.975 336.435 ; + RECT 161.27 335.705 161.47 336.435 ; + RECT 162.015 0.17 162.785 0.94 ; + RECT 162.015 0.17 162.275 12.9 ; + RECT 162.525 0.17 162.785 12.9 ; + RECT 161.505 0.52 161.765 5.815 ; + RECT 162.09 335.705 162.29 336.435 ; + RECT 163.035 0.17 163.805 0.43 ; + RECT 163.035 0.17 163.295 11.5 ; + RECT 163.545 0.17 163.805 11.5 ; + RECT 162.585 335.705 162.785 336.435 ; + RECT 163.085 335.705 163.285 336.435 ; + RECT 163.585 335.705 163.785 336.435 ; + RECT 165.075 0.17 165.845 0.43 ; + RECT 165.075 0.17 165.335 10.48 ; + RECT 165.585 0.17 165.845 10.99 ; + RECT 164.08 335.705 164.28 336.435 ; + RECT 164.9 335.705 165.1 336.435 ; + RECT 166.095 0.17 166.865 0.94 ; + RECT 166.095 0.17 166.355 8.7 ; + RECT 166.605 0.17 166.865 12.9 ; + RECT 165.395 335.705 165.595 336.435 ; + RECT 165.895 335.705 166.095 336.435 ; + RECT 166.395 335.705 166.595 336.435 ; + RECT 166.89 335.705 167.09 336.435 ; + RECT 167.115 0.52 167.375 2.485 ; + RECT 167.71 335.705 167.91 336.435 ; + RECT 167.98 0.52 168.24 14.11 ; + RECT 168.205 335.705 168.405 336.435 ; + RECT 168.49 0.52 168.75 2.335 ; + RECT 168.705 335.705 168.905 336.435 ; + RECT 169.205 335.705 169.405 336.435 ; + RECT 169.7 335.705 169.9 336.435 ; + RECT 171.89 0.52 172.15 5.16 ; + RECT 171.37 4.9 172.15 5.16 ; + RECT 171.37 4.9 171.63 6.64 ; + RECT 170.52 335.705 170.72 336.435 ; + RECT 171.015 335.705 171.215 336.435 ; + RECT 171.515 335.705 171.715 336.435 ; + RECT 172.015 335.705 172.215 336.435 ; + RECT 172.51 335.705 172.71 336.435 ; + RECT 173.255 0.17 174.025 0.94 ; + RECT 173.255 0.17 173.515 12.9 ; + RECT 173.765 0.17 174.025 12.9 ; + RECT 172.745 0.52 173.005 5.815 ; + RECT 173.33 335.705 173.53 336.435 ; + RECT 174.275 0.17 175.045 0.43 ; + RECT 174.275 0.17 174.535 11.5 ; + RECT 174.785 0.17 175.045 11.5 ; + RECT 173.825 335.705 174.025 336.435 ; + RECT 174.325 335.705 174.525 336.435 ; + RECT 174.825 335.705 175.025 336.435 ; + RECT 176.315 0.17 177.085 0.43 ; + RECT 176.315 0.17 176.575 10.48 ; + RECT 176.825 0.17 177.085 10.99 ; + RECT 175.32 335.705 175.52 336.435 ; + RECT 176.14 335.705 176.34 336.435 ; + RECT 177.335 0.17 178.105 0.94 ; + RECT 177.335 0.17 177.595 8.7 ; + RECT 177.845 0.17 178.105 12.9 ; + RECT 176.635 335.705 176.835 336.435 ; + RECT 177.135 335.705 177.335 336.435 ; + RECT 177.635 335.705 177.835 336.435 ; + RECT 178.13 335.705 178.33 336.435 ; + RECT 178.355 0.52 178.615 2.485 ; + RECT 178.95 335.705 179.15 336.435 ; + RECT 179.22 0.52 179.48 14.11 ; + RECT 179.445 335.705 179.645 336.435 ; + RECT 179.73 0.52 179.99 2.335 ; + RECT 179.945 335.705 180.145 336.435 ; + RECT 180.445 335.705 180.645 336.435 ; + RECT 182.435 0.17 183.205 0.43 ; + RECT 182.435 0.17 182.695 8.7 ; + RECT 182.945 0.17 183.205 8.7 ; + RECT 183.455 0.17 184.225 0.94 ; + RECT 183.455 0.17 183.715 8.7 ; + RECT 183.965 0.17 184.225 8.7 ; + RECT 184.475 0.17 185.245 0.43 ; + RECT 184.475 0.17 184.735 8.7 ; + RECT 184.985 0.17 185.245 8.7 ; + RECT 185.495 0.17 186.265 0.94 ; + RECT 185.495 0.17 185.755 8.7 ; + RECT 186.005 0.17 186.265 8.7 ; + RECT 186.515 0.17 187.285 0.43 ; + RECT 186.515 0.17 186.775 8.7 ; + RECT 187.025 0.17 187.285 8.7 ; + RECT 187.535 0.17 188.305 0.94 ; + RECT 187.535 0.17 187.795 8.7 ; + RECT 188.045 0.17 188.305 8.7 ; + RECT 180.94 335.705 181.14 336.435 ; + RECT 181.76 335.705 181.96 336.435 ; + RECT 182.755 335.705 182.955 336.435 ; + RECT 190.24 0.17 191.01 0.94 ; + RECT 190.24 0.17 190.5 8.7 ; + RECT 190.75 0.17 191.01 8.7 ; + RECT 188.71 0.3 188.97 8.7 ; + RECT 189.22 0 189.48 8.7 ; + RECT 189.73 0 189.99 8.7 ; + RECT 191.26 0 191.52 8.7 ; + RECT 191.77 0 192.03 8.7 ; + RECT 192.28 0.52 192.54 8.7 ; + RECT 192.79 0.52 193.05 8.7 ; + RECT 193.3 0.52 193.56 8.7 ; + RECT 195.34 0.17 196.11 0.94 ; + RECT 195.34 0.17 195.6 8.7 ; + RECT 195.85 0.17 196.11 8.7 ; + RECT 196.36 0.17 197.13 0.43 ; + RECT 196.36 0.17 196.62 8.7 ; + RECT 196.87 0.17 197.13 8.7 ; + RECT 193.81 0.52 194.07 8.7 ; + RECT 194.32 0 194.58 8.7 ; + RECT 194.83 0 195.09 8.7 ; + RECT 197.38 0.3 197.64 8.7 ; + RECT 197.89 0.3 198.15 8.7 ; + RECT 199.93 0.17 200.7 0.94 ; + RECT 199.93 0.17 200.19 8.7 ; + RECT 200.44 0.17 200.7 8.7 ; + RECT 198.4 0.3 198.66 8.7 ; + RECT 198.91 0.3 199.17 8.7 ; + RECT 199.42 0.3 199.68 8.7 ; + RECT 200.95 0.52 201.21 8.7 ; + RECT 201.46 0.52 201.72 8.7 ; + RECT 201.97 0.3 202.23 8.7 ; + RECT 202.48 0.52 202.74 8.7 ; + RECT 202.99 0.52 203.25 8.7 ; + RECT 203.5 0.3 203.76 8.7 ; + RECT 204.01 0.52 204.27 8.7 ; + RECT 204.52 0.52 204.78 8.7 ; + RECT 205.03 0.52 205.29 8.7 ; + RECT 205.54 0.52 205.8 8.7 ; + RECT 206.05 0.52 206.31 8.7 ; + RECT 206.56 0.3 206.82 8.7 ; + RECT 207.07 0.52 207.33 8.7 ; + RECT 207.58 0.52 207.84 8.7 ; + RECT 208.09 0.3 208.35 8.7 ; + RECT 210.13 0.17 210.9 0.94 ; + RECT 210.13 0.17 210.39 8.7 ; + RECT 210.64 0.17 210.9 8.7 ; + RECT 208.6 0.52 208.86 8.7 ; + RECT 209.11 0.52 209.37 8.7 ; + RECT 209.62 0.3 209.88 8.7 ; + RECT 211.15 0.52 211.41 8.7 ; + RECT 211.66 0.52 211.92 8.7 ; + RECT 212.17 0.52 212.43 8.7 ; + RECT 212.68 0.52 212.94 8.7 ; + RECT 213.19 0.52 213.45 8.7 ; + RECT 213.7 0.52 213.96 8.7 ; + RECT 214.21 0.52 214.47 8.7 ; + RECT 216.25 0.17 217.02 0.94 ; + RECT 216.25 0.17 216.51 8.7 ; + RECT 216.76 0.17 217.02 8.7 ; + RECT 214.72 0.52 214.98 8.7 ; + RECT 215.23 0 215.49 8.7 ; + RECT 215.74 0 216 8.7 ; + RECT 217.27 0.52 217.53 8.7 ; + RECT 219.31 0.17 220.08 0.43 ; + RECT 219.31 0.17 219.57 8.7 ; + RECT 219.82 0.17 220.08 8.7 ; + RECT 217.78 0.52 218.04 8.7 ; + RECT 218.29 0.3 218.55 8.7 ; + RECT 218.8 0.3 219.06 8.7 ; + RECT 220.33 0.3 220.59 8.7 ; + RECT 220.84 0.3 221.1 8.7 ; + RECT 221.35 0.3 221.61 8.7 ; + RECT 221.86 0.3 222.12 8.7 ; + RECT 222.37 0.52 222.63 8.7 ; + RECT 222.88 0.52 223.14 8.7 ; + RECT 224.92 0.17 225.69 0.43 ; + RECT 224.92 0.17 225.18 8.7 ; + RECT 225.43 0.17 225.69 8.7 ; + RECT 225.94 0.17 226.71 0.94 ; + RECT 225.94 0.17 226.2 25.5 ; + RECT 226.45 0.17 226.71 33.9 ; + RECT 226.96 0.17 227.73 0.43 ; + RECT 226.96 0.17 227.22 8.7 ; + RECT 227.47 0.17 227.73 8.7 ; + RECT 228.335 0.17 229.105 0.94 ; + RECT 228.335 0.17 228.595 8.7 ; + RECT 228.845 0.17 229.105 8.7 ; + RECT 229.355 0.17 230.125 0.43 ; + RECT 229.355 0.17 229.615 8.7 ; + RECT 229.865 0.17 230.125 8.7 ; + RECT 230.375 0.17 231.145 0.94 ; + RECT 230.375 0.17 230.635 8.7 ; + RECT 230.885 0.17 231.145 8.7 ; + RECT 231.395 0.17 232.165 0.43 ; + RECT 231.395 0.17 231.655 8.7 ; + RECT 231.905 0.17 232.165 8.7 ; + RECT 232.415 0.17 233.185 0.94 ; + RECT 232.415 0.17 232.675 8.7 ; + RECT 232.925 0.17 233.185 8.7 ; + RECT 223.39 0.3 223.65 8.7 ; + RECT 233.435 0.17 234.205 0.43 ; + RECT 233.435 0.17 233.695 8.7 ; + RECT 233.945 0.17 234.205 8.7 ; + RECT 223.9 0.3 224.16 8.7 ; + RECT 224.41 0.52 224.67 8.7 ; + RECT 233.685 335.705 233.885 336.435 ; + RECT 234.68 335.705 234.88 336.435 ; + RECT 235.5 335.705 235.7 336.435 ; + RECT 235.995 335.705 236.195 336.435 ; + RECT 236.495 335.705 236.695 336.435 ; + RECT 236.65 0.52 236.91 2.335 ; + RECT 236.995 335.705 237.195 336.435 ; + RECT 237.16 0.52 237.42 14.11 ; + RECT 237.49 335.705 237.69 336.435 ; + RECT 238.535 0.17 239.305 0.94 ; + RECT 239.045 0.17 239.305 8.7 ; + RECT 238.535 0.17 238.795 12.9 ; + RECT 238.025 0.52 238.285 2.485 ; + RECT 238.31 335.705 238.51 336.435 ; + RECT 239.555 0.17 240.325 0.43 ; + RECT 240.065 0.17 240.325 10.48 ; + RECT 239.555 0.17 239.815 10.99 ; + RECT 238.805 335.705 239.005 336.435 ; + RECT 239.305 335.705 239.505 336.435 ; + RECT 239.805 335.705 240.005 336.435 ; + RECT 240.3 335.705 240.5 336.435 ; + RECT 241.595 0.17 242.365 0.43 ; + RECT 241.595 0.17 241.855 11.5 ; + RECT 242.105 0.17 242.365 11.5 ; + RECT 241.12 335.705 241.32 336.435 ; + RECT 241.615 335.705 241.815 336.435 ; + RECT 242.615 0.17 243.385 0.94 ; + RECT 242.615 0.17 242.875 12.9 ; + RECT 243.125 0.17 243.385 12.9 ; + RECT 242.115 335.705 242.315 336.435 ; + RECT 242.615 335.705 242.815 336.435 ; + RECT 243.11 335.705 243.31 336.435 ; + RECT 243.635 0.52 243.895 5.815 ; + RECT 244.49 0.52 244.75 5.16 ; + RECT 244.49 4.9 245.27 5.16 ; + RECT 245.01 4.9 245.27 6.64 ; + RECT 243.93 335.705 244.13 336.435 ; + RECT 244.425 335.705 244.625 336.435 ; + RECT 244.925 335.705 245.125 336.435 ; + RECT 245.425 335.705 245.625 336.435 ; + RECT 245.92 335.705 246.12 336.435 ; + RECT 246.74 335.705 246.94 336.435 ; + RECT 247.235 335.705 247.435 336.435 ; + RECT 247.735 335.705 247.935 336.435 ; + RECT 247.89 0.52 248.15 2.335 ; + RECT 248.235 335.705 248.435 336.435 ; + RECT 248.4 0.52 248.66 14.11 ; + RECT 248.73 335.705 248.93 336.435 ; + RECT 249.775 0.17 250.545 0.94 ; + RECT 250.285 0.17 250.545 8.7 ; + RECT 249.775 0.17 250.035 12.9 ; + RECT 249.265 0.52 249.525 2.485 ; + RECT 249.55 335.705 249.75 336.435 ; + RECT 250.795 0.17 251.565 0.43 ; + RECT 251.305 0.17 251.565 10.48 ; + RECT 250.795 0.17 251.055 10.99 ; + RECT 250.045 335.705 250.245 336.435 ; + RECT 250.545 335.705 250.745 336.435 ; + RECT 251.045 335.705 251.245 336.435 ; + RECT 251.54 335.705 251.74 336.435 ; + RECT 252.835 0.17 253.605 0.43 ; + RECT 252.835 0.17 253.095 11.5 ; + RECT 253.345 0.17 253.605 11.5 ; + RECT 252.36 335.705 252.56 336.435 ; + RECT 252.855 335.705 253.055 336.435 ; + RECT 253.855 0.17 254.625 0.94 ; + RECT 253.855 0.17 254.115 12.9 ; + RECT 254.365 0.17 254.625 12.9 ; + RECT 253.355 335.705 253.555 336.435 ; + RECT 253.855 335.705 254.055 336.435 ; + RECT 254.35 335.705 254.55 336.435 ; + RECT 254.875 0.52 255.135 5.815 ; + RECT 255.73 0.52 255.99 5.16 ; + RECT 255.73 4.9 256.51 5.16 ; + RECT 256.25 4.9 256.51 6.64 ; + RECT 255.17 335.705 255.37 336.435 ; + RECT 255.665 335.705 255.865 336.435 ; + RECT 256.165 335.705 256.365 336.435 ; + RECT 256.665 335.705 256.865 336.435 ; + RECT 257.16 335.705 257.36 336.435 ; + RECT 257.98 335.705 258.18 336.435 ; + RECT 258.475 335.705 258.675 336.435 ; + RECT 258.975 335.705 259.175 336.435 ; + RECT 259.13 0.52 259.39 2.335 ; + RECT 259.475 335.705 259.675 336.435 ; + RECT 259.64 0.52 259.9 14.11 ; + RECT 259.97 335.705 260.17 336.435 ; + RECT 261.015 0.17 261.785 0.94 ; + RECT 261.525 0.17 261.785 8.7 ; + RECT 261.015 0.17 261.275 12.9 ; + RECT 260.505 0.52 260.765 2.485 ; + RECT 260.79 335.705 260.99 336.435 ; + RECT 262.035 0.17 262.805 0.43 ; + RECT 262.545 0.17 262.805 10.48 ; + RECT 262.035 0.17 262.295 10.99 ; + RECT 261.285 335.705 261.485 336.435 ; + RECT 261.785 335.705 261.985 336.435 ; + RECT 262.285 335.705 262.485 336.435 ; + RECT 262.78 335.705 262.98 336.435 ; + RECT 264.075 0.17 264.845 0.43 ; + RECT 264.075 0.17 264.335 11.5 ; + RECT 264.585 0.17 264.845 11.5 ; + RECT 263.6 335.705 263.8 336.435 ; + RECT 264.095 335.705 264.295 336.435 ; + RECT 265.095 0.17 265.865 0.94 ; + RECT 265.095 0.17 265.355 12.9 ; + RECT 265.605 0.17 265.865 12.9 ; + RECT 264.595 335.705 264.795 336.435 ; + RECT 265.095 335.705 265.295 336.435 ; + RECT 265.59 335.705 265.79 336.435 ; + RECT 266.115 0.52 266.375 5.815 ; + RECT 266.97 0.52 267.23 5.16 ; + RECT 266.97 4.9 267.75 5.16 ; + RECT 267.49 4.9 267.75 6.64 ; + RECT 266.41 335.705 266.61 336.435 ; + RECT 266.905 335.705 267.105 336.435 ; + RECT 267.405 335.705 267.605 336.435 ; + RECT 267.905 335.705 268.105 336.435 ; + RECT 268.4 335.705 268.6 336.435 ; + RECT 269.22 335.705 269.42 336.435 ; + RECT 269.715 335.705 269.915 336.435 ; + RECT 270.215 335.705 270.415 336.435 ; + RECT 270.37 0.52 270.63 2.335 ; + RECT 270.715 335.705 270.915 336.435 ; + RECT 270.88 0.52 271.14 14.11 ; + RECT 271.21 335.705 271.41 336.435 ; + RECT 272.255 0.17 273.025 0.94 ; + RECT 272.765 0.17 273.025 8.7 ; + RECT 272.255 0.17 272.515 12.9 ; + RECT 271.745 0.52 272.005 2.485 ; + RECT 272.03 335.705 272.23 336.435 ; + RECT 273.275 0.17 274.045 0.43 ; + RECT 273.785 0.17 274.045 10.48 ; + RECT 273.275 0.17 273.535 10.99 ; + RECT 272.525 335.705 272.725 336.435 ; + RECT 273.025 335.705 273.225 336.435 ; + RECT 273.525 335.705 273.725 336.435 ; + RECT 274.02 335.705 274.22 336.435 ; + RECT 275.315 0.17 276.085 0.43 ; + RECT 275.315 0.17 275.575 11.5 ; + RECT 275.825 0.17 276.085 11.5 ; + RECT 274.84 335.705 275.04 336.435 ; + RECT 275.335 335.705 275.535 336.435 ; + RECT 276.335 0.17 277.105 0.94 ; + RECT 276.335 0.17 276.595 12.9 ; + RECT 276.845 0.17 277.105 12.9 ; + RECT 275.835 335.705 276.035 336.435 ; + RECT 276.335 335.705 276.535 336.435 ; + RECT 276.83 335.705 277.03 336.435 ; + RECT 277.355 0.52 277.615 5.815 ; + RECT 278.21 0.52 278.47 5.16 ; + RECT 278.21 4.9 278.99 5.16 ; + RECT 278.73 4.9 278.99 6.64 ; + RECT 277.65 335.705 277.85 336.435 ; + RECT 278.145 335.705 278.345 336.435 ; + RECT 278.645 335.705 278.845 336.435 ; + RECT 279.145 335.705 279.345 336.435 ; + RECT 279.64 335.705 279.84 336.435 ; + RECT 280.46 335.705 280.66 336.435 ; + RECT 280.955 335.705 281.155 336.435 ; + RECT 281.455 335.705 281.655 336.435 ; + RECT 281.61 0.52 281.87 2.335 ; + RECT 281.955 335.705 282.155 336.435 ; + RECT 282.12 0.52 282.38 14.11 ; + RECT 282.45 335.705 282.65 336.435 ; + RECT 283.495 0.17 284.265 0.94 ; + RECT 284.005 0.17 284.265 8.7 ; + RECT 283.495 0.17 283.755 12.9 ; + RECT 282.985 0.52 283.245 2.485 ; + RECT 283.27 335.705 283.47 336.435 ; + RECT 284.515 0.17 285.285 0.43 ; + RECT 285.025 0.17 285.285 10.48 ; + RECT 284.515 0.17 284.775 10.99 ; + RECT 283.765 335.705 283.965 336.435 ; + RECT 284.265 335.705 284.465 336.435 ; + RECT 284.765 335.705 284.965 336.435 ; + RECT 285.26 335.705 285.46 336.435 ; + RECT 286.555 0.17 287.325 0.43 ; + RECT 286.555 0.17 286.815 11.5 ; + RECT 287.065 0.17 287.325 11.5 ; + RECT 286.08 335.705 286.28 336.435 ; + RECT 286.575 335.705 286.775 336.435 ; + RECT 287.575 0.17 288.345 0.94 ; + RECT 287.575 0.17 287.835 12.9 ; + RECT 288.085 0.17 288.345 12.9 ; + RECT 287.075 335.705 287.275 336.435 ; + RECT 287.575 335.705 287.775 336.435 ; + RECT 288.07 335.705 288.27 336.435 ; + RECT 288.595 0.52 288.855 5.815 ; + RECT 289.45 0.52 289.71 5.16 ; + RECT 289.45 4.9 290.23 5.16 ; + RECT 289.97 4.9 290.23 6.64 ; + RECT 288.89 335.705 289.09 336.435 ; + RECT 289.385 335.705 289.585 336.435 ; + RECT 289.885 335.705 290.085 336.435 ; + RECT 290.385 335.705 290.585 336.435 ; + RECT 290.88 335.705 291.08 336.435 ; + RECT 291.7 335.705 291.9 336.435 ; + RECT 292.195 335.705 292.395 336.435 ; + RECT 292.695 335.705 292.895 336.435 ; + RECT 292.85 0.52 293.11 2.335 ; + RECT 293.195 335.705 293.395 336.435 ; + RECT 293.36 0.52 293.62 14.11 ; + RECT 293.69 335.705 293.89 336.435 ; + RECT 294.735 0.17 295.505 0.94 ; + RECT 295.245 0.17 295.505 8.7 ; + RECT 294.735 0.17 294.995 12.9 ; + RECT 294.225 0.52 294.485 2.485 ; + RECT 294.51 335.705 294.71 336.435 ; + RECT 295.755 0.17 296.525 0.43 ; + RECT 296.265 0.17 296.525 10.48 ; + RECT 295.755 0.17 296.015 10.99 ; + RECT 295.005 335.705 295.205 336.435 ; + RECT 295.505 335.705 295.705 336.435 ; + RECT 296.005 335.705 296.205 336.435 ; + RECT 296.5 335.705 296.7 336.435 ; + RECT 297.795 0.17 298.565 0.43 ; + RECT 297.795 0.17 298.055 11.5 ; + RECT 298.305 0.17 298.565 11.5 ; + RECT 297.32 335.705 297.52 336.435 ; + RECT 297.815 335.705 298.015 336.435 ; + RECT 298.815 0.17 299.585 0.94 ; + RECT 298.815 0.17 299.075 12.9 ; + RECT 299.325 0.17 299.585 12.9 ; + RECT 298.315 335.705 298.515 336.435 ; + RECT 298.815 335.705 299.015 336.435 ; + RECT 299.31 335.705 299.51 336.435 ; + RECT 299.835 0.52 300.095 5.815 ; + RECT 300.69 0.52 300.95 5.16 ; + RECT 300.69 4.9 301.47 5.16 ; + RECT 301.21 4.9 301.47 6.64 ; + RECT 300.13 335.705 300.33 336.435 ; + RECT 300.625 335.705 300.825 336.435 ; + RECT 301.125 335.705 301.325 336.435 ; + RECT 301.625 335.705 301.825 336.435 ; + RECT 302.12 335.705 302.32 336.435 ; + RECT 302.94 335.705 303.14 336.435 ; + RECT 303.435 335.705 303.635 336.435 ; + RECT 303.935 335.705 304.135 336.435 ; + RECT 304.09 0.52 304.35 2.335 ; + RECT 304.435 335.705 304.635 336.435 ; + RECT 304.6 0.52 304.86 14.11 ; + RECT 304.93 335.705 305.13 336.435 ; + RECT 305.975 0.17 306.745 0.94 ; + RECT 306.485 0.17 306.745 8.7 ; + RECT 305.975 0.17 306.235 12.9 ; + RECT 305.465 0.52 305.725 2.485 ; + RECT 305.75 335.705 305.95 336.435 ; + RECT 306.995 0.17 307.765 0.43 ; + RECT 307.505 0.17 307.765 10.48 ; + RECT 306.995 0.17 307.255 10.99 ; + RECT 306.245 335.705 306.445 336.435 ; + RECT 306.745 335.705 306.945 336.435 ; + RECT 307.245 335.705 307.445 336.435 ; + RECT 307.74 335.705 307.94 336.435 ; + RECT 309.035 0.17 309.805 0.43 ; + RECT 309.035 0.17 309.295 11.5 ; + RECT 309.545 0.17 309.805 11.5 ; + RECT 308.56 335.705 308.76 336.435 ; + RECT 309.055 335.705 309.255 336.435 ; + RECT 310.055 0.17 310.825 0.94 ; + RECT 310.055 0.17 310.315 12.9 ; + RECT 310.565 0.17 310.825 12.9 ; + RECT 309.555 335.705 309.755 336.435 ; + RECT 310.055 335.705 310.255 336.435 ; + RECT 310.55 335.705 310.75 336.435 ; + RECT 311.075 0.52 311.335 5.815 ; + RECT 311.93 0.52 312.19 5.16 ; + RECT 311.93 4.9 312.71 5.16 ; + RECT 312.45 4.9 312.71 6.64 ; + RECT 311.37 335.705 311.57 336.435 ; + RECT 311.865 335.705 312.065 336.435 ; + RECT 312.365 335.705 312.565 336.435 ; + RECT 312.865 335.705 313.065 336.435 ; + RECT 313.36 335.705 313.56 336.435 ; + RECT 314.18 335.705 314.38 336.435 ; + RECT 314.675 335.705 314.875 336.435 ; + RECT 315.175 335.705 315.375 336.435 ; + RECT 315.33 0.52 315.59 2.335 ; + RECT 315.675 335.705 315.875 336.435 ; + RECT 315.84 0.52 316.1 14.11 ; + RECT 316.17 335.705 316.37 336.435 ; + RECT 317.215 0.17 317.985 0.94 ; + RECT 317.725 0.17 317.985 8.7 ; + RECT 317.215 0.17 317.475 12.9 ; + RECT 316.705 0.52 316.965 2.485 ; + RECT 316.99 335.705 317.19 336.435 ; + RECT 318.235 0.17 319.005 0.43 ; + RECT 318.745 0.17 319.005 10.48 ; + RECT 318.235 0.17 318.495 10.99 ; + RECT 317.485 335.705 317.685 336.435 ; + RECT 317.985 335.705 318.185 336.435 ; + RECT 318.485 335.705 318.685 336.435 ; + RECT 318.98 335.705 319.18 336.435 ; + RECT 320.275 0.17 321.045 0.43 ; + RECT 320.275 0.17 320.535 11.5 ; + RECT 320.785 0.17 321.045 11.5 ; + RECT 319.8 335.705 320 336.435 ; + RECT 320.295 335.705 320.495 336.435 ; + RECT 321.295 0.17 322.065 0.94 ; + RECT 321.295 0.17 321.555 12.9 ; + RECT 321.805 0.17 322.065 12.9 ; + RECT 320.795 335.705 320.995 336.435 ; + RECT 321.295 335.705 321.495 336.435 ; + RECT 321.79 335.705 321.99 336.435 ; + RECT 322.315 0.52 322.575 5.815 ; + RECT 323.17 0.52 323.43 5.16 ; + RECT 323.17 4.9 323.95 5.16 ; + RECT 323.69 4.9 323.95 6.64 ; + RECT 322.61 335.705 322.81 336.435 ; + RECT 323.105 335.705 323.305 336.435 ; + RECT 323.605 335.705 323.805 336.435 ; + RECT 324.105 335.705 324.305 336.435 ; + RECT 324.6 335.705 324.8 336.435 ; + RECT 325.42 335.705 325.62 336.435 ; + RECT 325.915 335.705 326.115 336.435 ; + RECT 326.415 335.705 326.615 336.435 ; + RECT 326.57 0.52 326.83 2.335 ; + RECT 326.915 335.705 327.115 336.435 ; + RECT 327.08 0.52 327.34 14.11 ; + RECT 327.41 335.705 327.61 336.435 ; + RECT 328.455 0.17 329.225 0.94 ; + RECT 328.965 0.17 329.225 8.7 ; + RECT 328.455 0.17 328.715 12.9 ; + RECT 327.945 0.52 328.205 2.485 ; + RECT 328.23 335.705 328.43 336.435 ; + RECT 329.475 0.17 330.245 0.43 ; + RECT 329.985 0.17 330.245 10.48 ; + RECT 329.475 0.17 329.735 10.99 ; + RECT 328.725 335.705 328.925 336.435 ; + RECT 329.225 335.705 329.425 336.435 ; + RECT 329.725 335.705 329.925 336.435 ; + RECT 330.22 335.705 330.42 336.435 ; + RECT 331.515 0.17 332.285 0.43 ; + RECT 331.515 0.17 331.775 11.5 ; + RECT 332.025 0.17 332.285 11.5 ; + RECT 331.04 335.705 331.24 336.435 ; + RECT 331.535 335.705 331.735 336.435 ; + RECT 332.535 0.17 333.305 0.94 ; + RECT 332.535 0.17 332.795 12.9 ; + RECT 333.045 0.17 333.305 12.9 ; + RECT 332.035 335.705 332.235 336.435 ; + RECT 332.535 335.705 332.735 336.435 ; + RECT 333.03 335.705 333.23 336.435 ; + RECT 333.555 0.52 333.815 5.815 ; + RECT 334.41 0.52 334.67 5.16 ; + RECT 334.41 4.9 335.19 5.16 ; + RECT 334.93 4.9 335.19 6.64 ; + RECT 333.85 335.705 334.05 336.435 ; + RECT 334.345 335.705 334.545 336.435 ; + RECT 334.845 335.705 335.045 336.435 ; + RECT 335.345 335.705 335.545 336.435 ; + RECT 335.84 335.705 336.04 336.435 ; + RECT 336.66 335.705 336.86 336.435 ; + RECT 337.155 335.705 337.355 336.435 ; + RECT 337.655 335.705 337.855 336.435 ; + RECT 337.81 0.52 338.07 2.335 ; + RECT 338.155 335.705 338.355 336.435 ; + RECT 338.32 0.52 338.58 14.11 ; + RECT 338.65 335.705 338.85 336.435 ; + RECT 339.695 0.17 340.465 0.94 ; + RECT 340.205 0.17 340.465 8.7 ; + RECT 339.695 0.17 339.955 12.9 ; + RECT 339.185 0.52 339.445 2.485 ; + RECT 339.47 335.705 339.67 336.435 ; + RECT 340.715 0.17 341.485 0.43 ; + RECT 341.225 0.17 341.485 10.48 ; + RECT 340.715 0.17 340.975 10.99 ; + RECT 339.965 335.705 340.165 336.435 ; + RECT 340.465 335.705 340.665 336.435 ; + RECT 340.965 335.705 341.165 336.435 ; + RECT 341.46 335.705 341.66 336.435 ; + RECT 342.755 0.17 343.525 0.43 ; + RECT 342.755 0.17 343.015 11.5 ; + RECT 343.265 0.17 343.525 11.5 ; + RECT 342.28 335.705 342.48 336.435 ; + RECT 342.775 335.705 342.975 336.435 ; + RECT 343.775 0.17 344.545 0.94 ; + RECT 343.775 0.17 344.035 12.9 ; + RECT 344.285 0.17 344.545 12.9 ; + RECT 343.275 335.705 343.475 336.435 ; + RECT 343.775 335.705 343.975 336.435 ; + RECT 344.27 335.705 344.47 336.435 ; + RECT 344.795 0.52 345.055 5.815 ; + RECT 345.65 0.52 345.91 5.16 ; + RECT 345.65 4.9 346.43 5.16 ; + RECT 346.17 4.9 346.43 6.64 ; + RECT 345.09 335.705 345.29 336.435 ; + RECT 345.585 335.705 345.785 336.435 ; + RECT 346.085 335.705 346.285 336.435 ; + RECT 346.585 335.705 346.785 336.435 ; + RECT 347.08 335.705 347.28 336.435 ; + RECT 347.9 335.705 348.1 336.435 ; + RECT 348.395 335.705 348.595 336.435 ; + RECT 348.895 335.705 349.095 336.435 ; + RECT 349.05 0.52 349.31 2.335 ; + RECT 349.395 335.705 349.595 336.435 ; + RECT 349.56 0.52 349.82 14.11 ; + RECT 349.89 335.705 350.09 336.435 ; + RECT 350.935 0.17 351.705 0.94 ; + RECT 351.445 0.17 351.705 8.7 ; + RECT 350.935 0.17 351.195 12.9 ; + RECT 350.425 0.52 350.685 2.485 ; + RECT 350.71 335.705 350.91 336.435 ; + RECT 351.955 0.17 352.725 0.43 ; + RECT 352.465 0.17 352.725 10.48 ; + RECT 351.955 0.17 352.215 10.99 ; + RECT 351.205 335.705 351.405 336.435 ; + RECT 351.705 335.705 351.905 336.435 ; + RECT 352.205 335.705 352.405 336.435 ; + RECT 352.7 335.705 352.9 336.435 ; + RECT 353.995 0.17 354.765 0.43 ; + RECT 353.995 0.17 354.255 11.5 ; + RECT 354.505 0.17 354.765 11.5 ; + RECT 353.52 335.705 353.72 336.435 ; + RECT 354.015 335.705 354.215 336.435 ; + RECT 355.015 0.17 355.785 0.94 ; + RECT 355.015 0.17 355.275 12.9 ; + RECT 355.525 0.17 355.785 12.9 ; + RECT 354.515 335.705 354.715 336.435 ; + RECT 355.015 335.705 355.215 336.435 ; + RECT 355.51 335.705 355.71 336.435 ; + RECT 356.035 0.52 356.295 5.815 ; + RECT 356.89 0.52 357.15 5.16 ; + RECT 356.89 4.9 357.67 5.16 ; + RECT 357.41 4.9 357.67 6.64 ; + RECT 356.33 335.705 356.53 336.435 ; + RECT 356.825 335.705 357.025 336.435 ; + RECT 357.325 335.705 357.525 336.435 ; + RECT 357.825 335.705 358.025 336.435 ; + RECT 358.32 335.705 358.52 336.435 ; + RECT 359.14 335.705 359.34 336.435 ; + RECT 359.635 335.705 359.835 336.435 ; + RECT 360.135 335.705 360.335 336.435 ; + RECT 360.29 0.52 360.55 2.335 ; + RECT 360.635 335.705 360.835 336.435 ; + RECT 360.8 0.52 361.06 14.11 ; + RECT 361.13 335.705 361.33 336.435 ; + RECT 362.175 0.17 362.945 0.94 ; + RECT 362.685 0.17 362.945 8.7 ; + RECT 362.175 0.17 362.435 12.9 ; + RECT 361.665 0.52 361.925 2.485 ; + RECT 361.95 335.705 362.15 336.435 ; + RECT 363.195 0.17 363.965 0.43 ; + RECT 363.705 0.17 363.965 10.48 ; + RECT 363.195 0.17 363.455 10.99 ; + RECT 362.445 335.705 362.645 336.435 ; + RECT 362.945 335.705 363.145 336.435 ; + RECT 363.445 335.705 363.645 336.435 ; + RECT 363.94 335.705 364.14 336.435 ; + RECT 365.235 0.17 366.005 0.43 ; + RECT 365.235 0.17 365.495 11.5 ; + RECT 365.745 0.17 366.005 11.5 ; + RECT 364.76 335.705 364.96 336.435 ; + RECT 365.255 335.705 365.455 336.435 ; + RECT 366.255 0.17 367.025 0.94 ; + RECT 366.255 0.17 366.515 12.9 ; + RECT 366.765 0.17 367.025 12.9 ; + RECT 365.755 335.705 365.955 336.435 ; + RECT 366.255 335.705 366.455 336.435 ; + RECT 366.75 335.705 366.95 336.435 ; + RECT 367.275 0.52 367.535 5.815 ; + RECT 368.13 0.52 368.39 5.16 ; + RECT 368.13 4.9 368.91 5.16 ; + RECT 368.65 4.9 368.91 6.64 ; + RECT 367.57 335.705 367.77 336.435 ; + RECT 368.065 335.705 368.265 336.435 ; + RECT 368.565 335.705 368.765 336.435 ; + RECT 369.065 335.705 369.265 336.435 ; + RECT 369.56 335.705 369.76 336.435 ; + RECT 370.38 335.705 370.58 336.435 ; + RECT 370.875 335.705 371.075 336.435 ; + RECT 371.375 335.705 371.575 336.435 ; + RECT 371.53 0.52 371.79 2.335 ; + RECT 371.875 335.705 372.075 336.435 ; + RECT 372.04 0.52 372.3 14.11 ; + RECT 372.37 335.705 372.57 336.435 ; + RECT 373.415 0.17 374.185 0.94 ; + RECT 373.925 0.17 374.185 8.7 ; + RECT 373.415 0.17 373.675 12.9 ; + RECT 372.905 0.52 373.165 2.485 ; + RECT 373.19 335.705 373.39 336.435 ; + RECT 374.435 0.17 375.205 0.43 ; + RECT 374.945 0.17 375.205 10.48 ; + RECT 374.435 0.17 374.695 10.99 ; + RECT 373.685 335.705 373.885 336.435 ; + RECT 374.185 335.705 374.385 336.435 ; + RECT 374.685 335.705 374.885 336.435 ; + RECT 375.18 335.705 375.38 336.435 ; + RECT 376.475 0.17 377.245 0.43 ; + RECT 376.475 0.17 376.735 11.5 ; + RECT 376.985 0.17 377.245 11.5 ; + RECT 376 335.705 376.2 336.435 ; + RECT 376.495 335.705 376.695 336.435 ; + RECT 377.495 0.17 378.265 0.94 ; + RECT 377.495 0.17 377.755 12.9 ; + RECT 378.005 0.17 378.265 12.9 ; + RECT 376.995 335.705 377.195 336.435 ; + RECT 377.495 335.705 377.695 336.435 ; + RECT 377.99 335.705 378.19 336.435 ; + RECT 378.515 0.52 378.775 5.815 ; + RECT 379.37 0.52 379.63 5.16 ; + RECT 379.37 4.9 380.15 5.16 ; + RECT 379.89 4.9 380.15 6.64 ; + RECT 378.81 335.705 379.01 336.435 ; + RECT 379.305 335.705 379.505 336.435 ; + RECT 379.805 335.705 380.005 336.435 ; + RECT 380.305 335.705 380.505 336.435 ; + RECT 380.8 335.705 381 336.435 ; + RECT 381.62 335.705 381.82 336.435 ; + RECT 382.115 335.705 382.315 336.435 ; + RECT 382.615 335.705 382.815 336.435 ; + RECT 382.77 0.52 383.03 2.335 ; + RECT 383.115 335.705 383.315 336.435 ; + RECT 383.28 0.52 383.54 14.11 ; + RECT 383.61 335.705 383.81 336.435 ; + RECT 384.655 0.17 385.425 0.94 ; + RECT 385.165 0.17 385.425 8.7 ; + RECT 384.655 0.17 384.915 12.9 ; + RECT 384.145 0.52 384.405 2.485 ; + RECT 384.43 335.705 384.63 336.435 ; + RECT 385.675 0.17 386.445 0.43 ; + RECT 386.185 0.17 386.445 10.48 ; + RECT 385.675 0.17 385.935 10.99 ; + RECT 384.925 335.705 385.125 336.435 ; + RECT 385.425 335.705 385.625 336.435 ; + RECT 385.925 335.705 386.125 336.435 ; + RECT 386.42 335.705 386.62 336.435 ; + RECT 387.715 0.17 388.485 0.43 ; + RECT 387.715 0.17 387.975 11.5 ; + RECT 388.225 0.17 388.485 11.5 ; + RECT 387.24 335.705 387.44 336.435 ; + RECT 387.735 335.705 387.935 336.435 ; + RECT 388.735 0.17 389.505 0.94 ; + RECT 388.735 0.17 388.995 12.9 ; + RECT 389.245 0.17 389.505 12.9 ; + RECT 388.235 335.705 388.435 336.435 ; + RECT 388.735 335.705 388.935 336.435 ; + RECT 389.23 335.705 389.43 336.435 ; + RECT 389.755 0.52 390.015 5.815 ; + RECT 390.61 0.52 390.87 5.16 ; + RECT 390.61 4.9 391.39 5.16 ; + RECT 391.13 4.9 391.39 6.64 ; + RECT 390.05 335.705 390.25 336.435 ; + RECT 390.545 335.705 390.745 336.435 ; + RECT 391.045 335.705 391.245 336.435 ; + RECT 391.545 335.705 391.745 336.435 ; + RECT 392.04 335.705 392.24 336.435 ; + RECT 392.86 335.705 393.06 336.435 ; + RECT 393.355 335.705 393.555 336.435 ; + RECT 393.855 335.705 394.055 336.435 ; + RECT 394.01 0.52 394.27 2.335 ; + RECT 394.355 335.705 394.555 336.435 ; + RECT 394.52 0.52 394.78 14.11 ; + RECT 394.85 335.705 395.05 336.435 ; + RECT 395.895 0.17 396.665 0.94 ; + RECT 396.405 0.17 396.665 8.7 ; + RECT 395.895 0.17 396.155 12.9 ; + RECT 395.385 0.52 395.645 2.485 ; + RECT 395.67 335.705 395.87 336.435 ; + RECT 396.915 0.17 397.685 0.43 ; + RECT 397.425 0.17 397.685 10.48 ; + RECT 396.915 0.17 397.175 10.99 ; + RECT 396.165 335.705 396.365 336.435 ; + RECT 396.665 335.705 396.865 336.435 ; + RECT 397.165 335.705 397.365 336.435 ; + RECT 397.66 335.705 397.86 336.435 ; + RECT 398.955 0.17 399.725 0.43 ; + RECT 398.955 0.17 399.215 11.5 ; + RECT 399.465 0.17 399.725 11.5 ; + RECT 398.48 335.705 398.68 336.435 ; + RECT 398.975 335.705 399.175 336.435 ; + RECT 399.975 0.17 400.745 0.94 ; + RECT 399.975 0.17 400.235 12.9 ; + RECT 400.485 0.17 400.745 12.9 ; + RECT 399.475 335.705 399.675 336.435 ; + RECT 399.975 335.705 400.175 336.435 ; + RECT 400.47 335.705 400.67 336.435 ; + RECT 400.995 0.52 401.255 5.815 ; + RECT 401.85 0.52 402.11 5.16 ; + RECT 401.85 4.9 402.63 5.16 ; + RECT 402.37 4.9 402.63 6.64 ; + RECT 401.29 335.705 401.49 336.435 ; + RECT 401.785 335.705 401.985 336.435 ; + RECT 402.285 335.705 402.485 336.435 ; + RECT 402.785 335.705 402.985 336.435 ; + RECT 403.28 335.705 403.48 336.435 ; + RECT 404.1 335.705 404.3 336.435 ; + RECT 404.595 335.705 404.795 336.435 ; + RECT 405.095 335.705 405.295 336.435 ; + RECT 405.25 0.52 405.51 2.335 ; + RECT 405.595 335.705 405.795 336.435 ; + RECT 405.76 0.52 406.02 14.11 ; + RECT 406.09 335.705 406.29 336.435 ; + RECT 407.135 0.17 407.905 0.94 ; + RECT 407.645 0.17 407.905 8.7 ; + RECT 407.135 0.17 407.395 12.9 ; + RECT 406.625 0.52 406.885 2.485 ; + RECT 406.91 335.705 407.11 336.435 ; + RECT 408.155 0.17 408.925 0.43 ; + RECT 408.665 0.17 408.925 10.48 ; + RECT 408.155 0.17 408.415 10.99 ; + RECT 407.405 335.705 407.605 336.435 ; + RECT 407.905 335.705 408.105 336.435 ; + RECT 408.405 335.705 408.605 336.435 ; + RECT 408.9 335.705 409.1 336.435 ; + RECT 410.195 0.17 410.965 0.43 ; + RECT 410.195 0.17 410.455 11.5 ; + RECT 410.705 0.17 410.965 11.5 ; + RECT 409.72 335.705 409.92 336.435 ; + RECT 410.215 335.705 410.415 336.435 ; + RECT 411.215 0.17 411.985 0.94 ; + RECT 411.215 0.17 411.475 12.9 ; + RECT 411.725 0.17 411.985 12.9 ; + RECT 410.715 335.705 410.915 336.435 ; + RECT 411.215 335.705 411.415 336.435 ; + RECT 411.71 335.705 411.91 336.435 ; + RECT 412.235 0.52 412.495 5.815 ; + RECT 413.09 0.52 413.35 5.16 ; + RECT 413.09 4.9 413.87 5.16 ; + RECT 413.61 4.9 413.87 6.64 ; + RECT 412.53 335.705 412.73 336.435 ; + RECT 413.025 335.705 413.225 336.435 ; + RECT 413.525 335.705 413.725 336.435 ; + RECT 414.025 335.705 414.225 336.435 ; + RECT 414.52 335.705 414.72 336.435 ; + RECT 415.34 335.705 415.54 336.435 ; + RECT 416.335 45.465 416.535 336.435 ; + LAYER Metal2 SPACING 0.21 ; + RECT 272.265 0 277.095 336.46 ; + RECT 283.505 0 288.335 336.46 ; + RECT 294.745 0 299.575 336.46 ; + RECT 305.985 0 310.815 336.46 ; + RECT 317.225 0 322.055 336.46 ; + RECT 328.465 0 333.295 336.46 ; + RECT 339.705 0 344.535 336.46 ; + RECT 350.945 0 355.775 336.46 ; + RECT 362.185 0 367.015 336.46 ; + RECT 373.425 0 378.255 336.46 ; + RECT 384.665 0 389.495 336.46 ; + RECT 395.905 0 400.735 336.46 ; + RECT 407.145 0 411.975 336.46 ; + RECT 201.98 0 202.22 336.46 ; + RECT 203.51 0 203.75 336.46 ; + RECT 206.57 0 206.81 336.46 ; + RECT 208.1 0 208.34 336.46 ; + RECT 218.3 0 222.11 336.46 ; + RECT 223.4 0 224.15 336.46 ; + RECT 0 0 3.03 336.46 ; + RECT 4.655 0.17 9.505 336.46 ; + RECT 11.65 0 14.27 336.46 ; + RECT 15.895 0.17 20.745 336.46 ; + RECT 22.89 0 25.51 336.46 ; + RECT 27.135 0.17 31.985 336.46 ; + RECT 34.13 0 36.75 336.46 ; + RECT 38.375 0.17 43.225 336.46 ; + RECT 45.37 0 47.99 336.46 ; + RECT 49.615 0.17 54.465 336.46 ; + RECT 56.61 0 59.23 336.46 ; + RECT 60.855 0.17 65.705 336.46 ; + RECT 67.85 0 70.47 336.46 ; + RECT 72.095 0.17 76.945 336.46 ; + RECT 79.09 0 81.71 336.46 ; + RECT 83.335 0.17 88.185 336.46 ; + RECT 90.33 0 92.95 336.46 ; + RECT 94.575 0.17 99.425 336.46 ; + RECT 101.57 0 104.19 336.46 ; + RECT 105.815 0.17 110.665 336.46 ; + RECT 112.81 0 115.43 336.46 ; + RECT 117.055 0.17 121.905 336.46 ; + RECT 124.05 0 126.67 336.46 ; + RECT 128.295 0.17 133.145 336.46 ; + RECT 135.29 0 137.91 336.46 ; + RECT 139.535 0.17 144.385 336.46 ; + RECT 146.53 0 149.15 336.46 ; + RECT 150.775 0.17 155.625 336.46 ; + RECT 157.77 0 160.39 336.46 ; + RECT 162.015 0.17 166.865 336.46 ; + RECT 169.01 0 171.63 336.46 ; + RECT 173.255 0.17 178.105 336.46 ; + RECT 180.25 0 192.03 336.46 ; + RECT 194.32 0.17 200.7 336.46 ; + RECT 201.97 0.3 202.23 336.46 ; + RECT 203.5 0.3 203.76 336.46 ; + RECT 206.56 0.3 206.82 336.46 ; + RECT 208.09 0.3 208.35 336.46 ; + RECT 209.63 0.17 210.9 336.46 ; + RECT 209.62 0.3 210.9 336.46 ; + RECT 215.23 0.17 217.02 336.46 ; + RECT 218.29 0.3 222.12 336.46 ; + RECT 223.39 0.3 224.16 336.46 ; + RECT 224.93 0 236.39 336.46 ; + RECT 224.92 0.17 236.39 336.46 ; + RECT 238.535 0.17 243.385 336.46 ; + RECT 245.01 0 247.63 336.46 ; + RECT 249.775 0.17 254.625 336.46 ; + RECT 256.25 0 258.87 336.46 ; + RECT 261.015 0.17 265.865 336.46 ; + RECT 267.49 0 270.11 336.46 ; + RECT 272.255 0.17 277.105 336.46 ; + RECT 278.73 0 281.35 336.46 ; + RECT 283.495 0.17 288.345 336.46 ; + RECT 289.97 0 292.59 336.46 ; + RECT 294.735 0.17 299.585 336.46 ; + RECT 301.21 0 303.83 336.46 ; + RECT 305.975 0.17 310.825 336.46 ; + RECT 312.45 0 315.07 336.46 ; + RECT 317.215 0.17 322.065 336.46 ; + RECT 323.69 0 326.31 336.46 ; + RECT 328.455 0.17 333.305 336.46 ; + RECT 334.93 0 337.55 336.46 ; + RECT 339.695 0.17 344.545 336.46 ; + RECT 346.17 0 348.79 336.46 ; + RECT 350.935 0.17 355.785 336.46 ; + RECT 357.41 0 360.03 336.46 ; + RECT 362.175 0.17 367.025 336.46 ; + RECT 368.65 0 371.27 336.46 ; + RECT 373.415 0.17 378.265 336.46 ; + RECT 379.89 0 382.51 336.46 ; + RECT 384.655 0.17 389.505 336.46 ; + RECT 391.13 0 393.75 336.46 ; + RECT 395.895 0.17 400.745 336.46 ; + RECT 402.37 0 404.99 336.46 ; + RECT 407.135 0.17 411.985 336.46 ; + RECT 413.61 0 416.64 336.46 ; + RECT 0 0.52 416.64 336.46 ; + RECT 4.665 0 9.495 336.46 ; + RECT 15.905 0 20.735 336.46 ; + RECT 27.145 0 31.975 336.46 ; + RECT 38.385 0 43.215 336.46 ; + RECT 49.625 0 54.455 336.46 ; + RECT 60.865 0 65.695 336.46 ; + RECT 72.105 0 76.935 336.46 ; + RECT 83.345 0 88.175 336.46 ; + RECT 94.585 0 99.415 336.46 ; + RECT 105.825 0 110.655 336.46 ; + RECT 117.065 0 121.895 336.46 ; + RECT 128.305 0 133.135 336.46 ; + RECT 139.545 0 144.375 336.46 ; + RECT 150.785 0 155.615 336.46 ; + RECT 162.025 0 166.855 336.46 ; + RECT 173.265 0 178.095 336.46 ; + RECT 194.32 0 200.69 336.46 ; + RECT 209.63 0 210.89 336.46 ; + RECT 215.23 0 217.01 336.46 ; + RECT 238.545 0 243.375 336.46 ; + RECT 249.785 0 254.615 336.46 ; + RECT 261.025 0 265.855 336.46 ; + LAYER Metal3 ; + RECT 0 0 416.64 336.46 ; + LAYER Metal4 SPACING 0.21 ; + RECT 0 39.085 9.62 45.205 ; + RECT 0 0 4 336.46 ; + RECT 7.33 0 9.62 336.46 ; + RECT 12.95 39.085 20.86 45.205 ; + RECT 12.95 0 15.24 336.46 ; + RECT 18.57 0 20.86 336.46 ; + RECT 24.19 39.085 32.1 45.205 ; + RECT 24.19 0 26.48 336.46 ; + RECT 29.81 0 32.1 336.46 ; + RECT 35.43 39.085 43.34 45.205 ; + RECT 35.43 0 37.72 336.46 ; + RECT 41.05 0 43.34 336.46 ; + RECT 46.67 39.085 54.58 45.205 ; + RECT 46.67 0 48.96 336.46 ; + RECT 52.29 0 54.58 336.46 ; + RECT 57.91 39.085 65.82 45.205 ; + RECT 57.91 0 60.2 336.46 ; + RECT 63.53 0 65.82 336.46 ; + RECT 69.15 39.085 77.06 45.205 ; + RECT 69.15 0 71.44 336.46 ; + RECT 74.77 0 77.06 336.46 ; + RECT 80.39 39.085 88.3 45.205 ; + RECT 80.39 0 82.68 336.46 ; + RECT 86.01 0 88.3 336.46 ; + RECT 91.63 39.085 99.54 45.205 ; + RECT 91.63 0 93.92 336.46 ; + RECT 97.25 0 99.54 336.46 ; + RECT 102.87 39.085 110.78 45.205 ; + RECT 102.87 0 105.16 336.46 ; + RECT 108.49 0 110.78 336.46 ; + RECT 114.11 39.085 122.02 45.205 ; + RECT 114.11 0 116.4 336.46 ; + RECT 119.73 0 122.02 336.46 ; + RECT 125.35 39.085 133.26 45.205 ; + RECT 125.35 0 127.64 336.46 ; + RECT 130.97 0 133.26 336.46 ; + RECT 136.59 39.085 144.5 45.205 ; + RECT 136.59 0 138.88 336.46 ; + RECT 142.21 0 144.5 336.46 ; + RECT 147.83 39.085 155.74 45.205 ; + RECT 147.83 0 150.12 336.46 ; + RECT 153.45 0 155.74 336.46 ; + RECT 159.07 39.085 166.98 45.205 ; + RECT 159.07 0 161.36 336.46 ; + RECT 164.69 0 166.98 336.46 ; + RECT 170.31 39.085 178.22 45.205 ; + RECT 170.31 0 172.6 336.46 ; + RECT 175.93 0 178.22 336.46 ; + RECT 181.55 0 188.63 336.46 ; + RECT 191.96 0 193.78 336.46 ; + RECT 197.11 0 198.93 336.46 ; + RECT 202.26 0 204.08 336.46 ; + RECT 207.41 0 209.23 336.46 ; + RECT 212.56 0 214.38 336.46 ; + RECT 238.42 39.085 246.33 45.205 ; + RECT 238.42 0 240.71 336.46 ; + RECT 244.04 0 246.33 336.46 ; + RECT 249.66 39.085 257.57 45.205 ; + RECT 249.66 0 251.95 336.46 ; + RECT 255.28 0 257.57 336.46 ; + RECT 260.9 39.085 268.81 45.205 ; + RECT 260.9 0 263.19 336.46 ; + RECT 266.52 0 268.81 336.46 ; + RECT 272.14 39.085 280.05 45.205 ; + RECT 272.14 0 274.43 336.46 ; + RECT 277.76 0 280.05 336.46 ; + RECT 283.38 39.085 291.29 45.205 ; + RECT 283.38 0 285.67 336.46 ; + RECT 289 0 291.29 336.46 ; + RECT 294.62 39.085 302.53 45.205 ; + RECT 294.62 0 296.91 336.46 ; + RECT 300.24 0 302.53 336.46 ; + RECT 305.86 39.085 313.77 45.205 ; + RECT 305.86 0 308.15 336.46 ; + RECT 311.48 0 313.77 336.46 ; + RECT 317.1 39.085 325.01 45.205 ; + RECT 317.1 0 319.39 336.46 ; + RECT 322.72 0 325.01 336.46 ; + RECT 328.34 39.085 336.25 45.205 ; + RECT 328.34 0 330.63 336.46 ; + RECT 333.96 0 336.25 336.46 ; + RECT 339.58 39.085 347.49 45.205 ; + RECT 339.58 0 341.87 336.46 ; + RECT 345.2 0 347.49 336.46 ; + RECT 350.82 39.085 358.73 45.205 ; + RECT 350.82 0 353.11 336.46 ; + RECT 356.44 0 358.73 336.46 ; + RECT 362.06 39.085 369.97 45.205 ; + RECT 362.06 0 364.35 336.46 ; + RECT 367.68 0 369.97 336.46 ; + RECT 373.3 39.085 381.21 45.205 ; + RECT 373.3 0 375.59 336.46 ; + RECT 378.92 0 381.21 336.46 ; + RECT 384.54 39.085 392.45 45.205 ; + RECT 384.54 0 386.83 336.46 ; + RECT 390.16 0 392.45 336.46 ; + RECT 395.78 39.085 403.69 45.205 ; + RECT 395.78 0 398.07 336.46 ; + RECT 401.4 0 403.69 336.46 ; + RECT 407.02 39.085 416.64 45.205 ; + RECT 407.02 0 409.31 336.46 ; + RECT 412.64 0 416.64 336.46 ; + RECT 217.71 0 219.53 336.46 ; + RECT 222.86 0 224.68 336.46 ; + RECT 228.01 0 235.09 336.46 ; + END +END RM_IHPSG13_1P_1024x32_c2_bm_bist + +END LIBRARY diff --git a/flow/platforms/ihp-sg13g2/lef/RM_IHPSG13_1P_256x16_c2_bm_bist.lef b/flow/platforms/ihp-sg13g2/lef/RM_IHPSG13_1P_256x16_c2_bm_bist.lef new file mode 100644 index 0000000000..1a7c846648 --- /dev/null +++ b/flow/platforms/ihp-sg13g2/lef/RM_IHPSG13_1P_256x16_c2_bm_bist.lef @@ -0,0 +1,2412 @@ +# ------------------------------------------------------ +# +# Copyright 2025 IHP PDK Authors +# +# Licensed under the Apache License, Version 2.0 (the "License"); +# you may not use this file except in compliance with the License. +# You may obtain a copy of the License at +# +# https://www.apache.org/licenses/LICENSE-2.0 +# +# Unless required by applicable law or agreed to in writing, software +# distributed under the License is distributed on an "AS IS" BASIS, +# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +# See the License for the specific language governing permissions and +# limitations under the License. +# +# Generated on Wed Aug 27 12:14:52 2025 +# +# ------------------------------------------------------ +VERSION 5.7 ; +BUSBITCHARS "[]" ; +DIVIDERCHAR "/" ; + +MACRO RM_IHPSG13_1P_256x16_c2_bm_bist + CLASS BLOCK ; + ORIGIN 0 0 ; + FOREIGN RM_IHPSG13_1P_256x16_c2_bm_bist 0 0 ; + SIZE 236.8 BY 118.78 ; + SYMMETRY X Y R90 ; + PIN A_DIN[8] + DIRECTION INPUT ; + USE SIGNAL ; + ANTENNAPARTIALMETALAREA 1.794 LAYER Metal2 ; + ANTENNAMODEL OXIDE1 ; + ANTENNAGATEAREA 0.20085 LAYER Metal2 ; + ANTENNAMAXAREACAR 9.838188 LAYER Metal2 ; + PORT + LAYER Metal2 ; + RECT 154.57 0 154.83 0.26 ; + END + END A_DIN[8] + PIN A_DIN[7] + DIRECTION INPUT ; + USE SIGNAL ; + ANTENNAPARTIALMETALAREA 1.794 LAYER Metal2 ; + ANTENNAMODEL OXIDE1 ; + ANTENNAGATEAREA 0.20085 LAYER Metal2 ; + ANTENNAMAXAREACAR 9.838188 LAYER Metal2 ; + PORT + LAYER Metal2 ; + RECT 81.97 0 82.23 0.26 ; + END + END A_DIN[7] + PIN A_BIST_DIN[8] + DIRECTION INPUT ; + USE SIGNAL ; + ANTENNAPARTIALMETALAREA 1.6263 LAYER Metal2 ; + ANTENNAMODEL OXIDE1 ; + ANTENNAGATEAREA 0.20085 LAYER Metal2 ; + ANTENNAMAXAREACAR 9.365945 LAYER Metal2 ; + PORT + LAYER Metal2 ; + RECT 153.715 0 153.975 0.26 ; + END + END A_BIST_DIN[8] + PIN A_BIST_DIN[7] + DIRECTION INPUT ; + USE SIGNAL ; + ANTENNAPARTIALMETALAREA 1.6263 LAYER Metal2 ; + ANTENNAMODEL OXIDE1 ; + ANTENNAGATEAREA 0.20085 LAYER Metal2 ; + ANTENNAMAXAREACAR 9.365945 LAYER Metal2 ; + PORT + LAYER Metal2 ; + RECT 82.825 0 83.085 0.26 ; + END + END A_BIST_DIN[7] + PIN A_BM[8] + DIRECTION INPUT ; + USE SIGNAL ; + ANTENNAPARTIALMETALAREA 0.7215 LAYER Metal2 ; + ANTENNAMODEL OXIDE1 ; + ANTENNAGATEAREA 0.20085 LAYER Metal2 ; + ANTENNAMAXAREACAR 4.498382 LAYER Metal2 ; + PORT + LAYER Metal2 ; + RECT 146.73 0 146.99 0.26 ; + END + END A_BM[8] + PIN A_BM[7] + DIRECTION INPUT ; + USE SIGNAL ; + ANTENNAPARTIALMETALAREA 0.7215 LAYER Metal2 ; + ANTENNAMODEL OXIDE1 ; + ANTENNAGATEAREA 0.20085 LAYER Metal2 ; + ANTENNAMAXAREACAR 4.498382 LAYER Metal2 ; + PORT + LAYER Metal2 ; + RECT 89.81 0 90.07 0.26 ; + END + END A_BM[7] + PIN A_BIST_BM[8] + DIRECTION INPUT ; + USE SIGNAL ; + ANTENNAPARTIALMETALAREA 0.7605 LAYER Metal2 ; + ANTENNAMODEL OXIDE1 ; + ANTENNAGATEAREA 0.20085 LAYER Metal2 ; + ANTENNAMAXAREACAR 5.055265 LAYER Metal2 ; + PORT + LAYER Metal2 ; + RECT 148.105 0 148.365 0.26 ; + END + END A_BIST_BM[8] + PIN A_BIST_BM[7] + DIRECTION INPUT ; + USE SIGNAL ; + ANTENNAPARTIALMETALAREA 0.7605 LAYER Metal2 ; + ANTENNAMODEL OXIDE1 ; + ANTENNAGATEAREA 0.20085 LAYER Metal2 ; + ANTENNAMAXAREACAR 5.055265 LAYER Metal2 ; + PORT + LAYER Metal2 ; + RECT 88.435 0 88.695 0.26 ; + END + END A_BIST_BM[7] + PIN A_DOUT[8] + DIRECTION OUTPUT ; + USE SIGNAL ; + ANTENNAPARTIALMETALAREA 3.7095 LAYER Metal2 ; + ANTENNADIFFAREA 0.988 LAYER Metal2 ; + PORT + LAYER Metal2 ; + RECT 147.24 0 147.5 0.26 ; + END + END A_DOUT[8] + PIN A_DOUT[7] + DIRECTION OUTPUT ; + USE SIGNAL ; + ANTENNAPARTIALMETALAREA 3.7095 LAYER Metal2 ; + ANTENNADIFFAREA 0.988 LAYER Metal2 ; + PORT + LAYER Metal2 ; + RECT 89.3 0 89.56 0.26 ; + END + END A_DOUT[7] + PIN VSS! + DIRECTION INOUT ; + USE GROUND ; + NETEXPR "vss VSS!" ; + PORT + LAYER Metal4 ; + RECT 224.11 0 226.92 118.78 ; + END + PORT + LAYER Metal4 ; + RECT 212.87 0 215.68 118.78 ; + END + PORT + LAYER Metal4 ; + RECT 201.63 0 204.44 118.78 ; + END + PORT + LAYER Metal4 ; + RECT 190.39 0 193.2 118.78 ; + END + PORT + LAYER Metal4 ; + RECT 179.15 0 181.96 118.78 ; + END + PORT + LAYER Metal4 ; + RECT 167.91 0 170.72 118.78 ; + END + PORT + LAYER Metal4 ; + RECT 156.67 0 159.48 118.78 ; + END + PORT + LAYER Metal4 ; + RECT 145.43 0 148.24 118.78 ; + END + PORT + LAYER Metal4 ; + RECT 135.02 0 137.83 118.78 ; + END + PORT + LAYER Metal4 ; + RECT 124.72 0 127.53 118.78 ; + END + PORT + LAYER Metal4 ; + RECT 109.27 0 112.08 118.78 ; + END + PORT + LAYER Metal4 ; + RECT 98.97 0 101.78 118.78 ; + END + PORT + LAYER Metal4 ; + RECT 88.56 0 91.37 118.78 ; + END + PORT + LAYER Metal4 ; + RECT 77.32 0 80.13 118.78 ; + END + PORT + LAYER Metal4 ; + RECT 66.08 0 68.89 118.78 ; + END + PORT + LAYER Metal4 ; + RECT 54.84 0 57.65 118.78 ; + END + PORT + LAYER Metal4 ; + RECT 43.6 0 46.41 118.78 ; + END + PORT + LAYER Metal4 ; + RECT 32.36 0 35.17 118.78 ; + END + PORT + LAYER Metal4 ; + RECT 21.12 0 23.93 118.78 ; + END + PORT + LAYER Metal4 ; + RECT 9.88 0 12.69 118.78 ; + END + END VSS! + PIN VDD! + DIRECTION INOUT ; + USE POWER ; + NETEXPR "vdd VDD!" ; + PORT + LAYER Metal4 ; + RECT 229.73 0 232.54 38.825 ; + END + PORT + LAYER Metal4 ; + RECT 218.49 0 221.3 38.825 ; + END + PORT + LAYER Metal4 ; + RECT 207.25 0 210.06 38.825 ; + END + PORT + LAYER Metal4 ; + RECT 196.01 0 198.82 38.825 ; + END + PORT + LAYER Metal4 ; + RECT 184.77 0 187.58 38.825 ; + END + PORT + LAYER Metal4 ; + RECT 173.53 0 176.34 38.825 ; + END + PORT + LAYER Metal4 ; + RECT 162.29 0 165.1 38.825 ; + END + PORT + LAYER Metal4 ; + RECT 151.05 0 153.86 38.825 ; + END + PORT + LAYER Metal4 ; + RECT 129.87 0 132.68 118.78 ; + END + PORT + LAYER Metal4 ; + RECT 119.57 0 122.38 118.78 ; + END + PORT + LAYER Metal4 ; + RECT 114.42 0 117.23 118.78 ; + END + PORT + LAYER Metal4 ; + RECT 104.12 0 106.93 118.78 ; + END + PORT + LAYER Metal4 ; + RECT 82.94 0 85.75 38.825 ; + END + PORT + LAYER Metal4 ; + RECT 71.7 0 74.51 38.825 ; + END + PORT + LAYER Metal4 ; + RECT 60.46 0 63.27 38.825 ; + END + PORT + LAYER Metal4 ; + RECT 49.22 0 52.03 38.825 ; + END + PORT + LAYER Metal4 ; + RECT 37.98 0 40.79 38.825 ; + END + PORT + LAYER Metal4 ; + RECT 26.74 0 29.55 38.825 ; + END + PORT + LAYER Metal4 ; + RECT 15.5 0 18.31 38.825 ; + END + PORT + LAYER Metal4 ; + RECT 4.26 0 7.07 38.825 ; + END + END VDD! + PIN VDDARRAY! + DIRECTION INOUT ; + USE POWER ; + NETEXPR "vddarray VDDARRAY!" ; + PORT + LAYER Metal4 ; + RECT 229.73 45.465 232.54 118.78 ; + END + PORT + LAYER Metal4 ; + RECT 218.49 45.465 221.3 118.78 ; + END + PORT + LAYER Metal4 ; + RECT 207.25 45.465 210.06 118.78 ; + END + PORT + LAYER Metal4 ; + RECT 196.01 45.465 198.82 118.78 ; + END + PORT + LAYER Metal4 ; + RECT 184.77 45.465 187.58 118.78 ; + END + PORT + LAYER Metal4 ; + RECT 173.53 45.465 176.34 118.78 ; + END + PORT + LAYER Metal4 ; + RECT 162.29 45.465 165.1 118.78 ; + END + PORT + LAYER Metal4 ; + RECT 151.05 45.465 153.86 118.78 ; + END + PORT + LAYER Metal4 ; + RECT 82.94 45.465 85.75 118.78 ; + END + PORT + LAYER Metal4 ; + RECT 71.7 45.465 74.51 118.78 ; + END + PORT + LAYER Metal4 ; + RECT 60.46 45.465 63.27 118.78 ; + END + PORT + LAYER Metal4 ; + RECT 49.22 45.465 52.03 118.78 ; + END + PORT + LAYER Metal4 ; + RECT 37.98 45.465 40.79 118.78 ; + END + PORT + LAYER Metal4 ; + RECT 26.74 45.465 29.55 118.78 ; + END + PORT + LAYER Metal4 ; + RECT 15.5 45.465 18.31 118.78 ; + END + PORT + LAYER Metal4 ; + RECT 4.26 45.465 7.07 118.78 ; + END + END VDDARRAY! + PIN A_DIN[9] + DIRECTION INPUT ; + USE SIGNAL ; + ANTENNAPARTIALMETALAREA 1.794 LAYER Metal2 ; + ANTENNAMODEL OXIDE1 ; + ANTENNAGATEAREA 0.20085 LAYER Metal2 ; + ANTENNAMAXAREACAR 9.838188 LAYER Metal2 ; + PORT + LAYER Metal2 ; + RECT 165.81 0 166.07 0.26 ; + END + END A_DIN[9] + PIN A_DIN[6] + DIRECTION INPUT ; + USE SIGNAL ; + ANTENNAPARTIALMETALAREA 1.794 LAYER Metal2 ; + ANTENNAMODEL OXIDE1 ; + ANTENNAGATEAREA 0.20085 LAYER Metal2 ; + ANTENNAMAXAREACAR 9.838188 LAYER Metal2 ; + PORT + LAYER Metal2 ; + RECT 70.73 0 70.99 0.26 ; + END + END A_DIN[6] + PIN A_BIST_DIN[9] + DIRECTION INPUT ; + USE SIGNAL ; + ANTENNAPARTIALMETALAREA 1.6263 LAYER Metal2 ; + ANTENNAMODEL OXIDE1 ; + ANTENNAGATEAREA 0.20085 LAYER Metal2 ; + ANTENNAMAXAREACAR 9.365945 LAYER Metal2 ; + PORT + LAYER Metal2 ; + RECT 164.955 0 165.215 0.26 ; + END + END A_BIST_DIN[9] + PIN A_BIST_DIN[6] + DIRECTION INPUT ; + USE SIGNAL ; + ANTENNAPARTIALMETALAREA 1.6263 LAYER Metal2 ; + ANTENNAMODEL OXIDE1 ; + ANTENNAGATEAREA 0.20085 LAYER Metal2 ; + ANTENNAMAXAREACAR 9.365945 LAYER Metal2 ; + PORT + LAYER Metal2 ; + RECT 71.585 0 71.845 0.26 ; + END + END A_BIST_DIN[6] + PIN A_BM[9] + DIRECTION INPUT ; + USE SIGNAL ; + ANTENNAPARTIALMETALAREA 0.7215 LAYER Metal2 ; + ANTENNAMODEL OXIDE1 ; + ANTENNAGATEAREA 0.20085 LAYER Metal2 ; + ANTENNAMAXAREACAR 4.498382 LAYER Metal2 ; + PORT + LAYER Metal2 ; + RECT 157.97 0 158.23 0.26 ; + END + END A_BM[9] + PIN A_BM[6] + DIRECTION INPUT ; + USE SIGNAL ; + ANTENNAPARTIALMETALAREA 0.7215 LAYER Metal2 ; + ANTENNAMODEL OXIDE1 ; + ANTENNAGATEAREA 0.20085 LAYER Metal2 ; + ANTENNAMAXAREACAR 4.498382 LAYER Metal2 ; + PORT + LAYER Metal2 ; + RECT 78.57 0 78.83 0.26 ; + END + END A_BM[6] + PIN A_BIST_BM[9] + DIRECTION INPUT ; + USE SIGNAL ; + ANTENNAPARTIALMETALAREA 0.7605 LAYER Metal2 ; + ANTENNAMODEL OXIDE1 ; + ANTENNAGATEAREA 0.20085 LAYER Metal2 ; + ANTENNAMAXAREACAR 5.055265 LAYER Metal2 ; + PORT + LAYER Metal2 ; + RECT 159.345 0 159.605 0.26 ; + END + END A_BIST_BM[9] + PIN A_BIST_BM[6] + DIRECTION INPUT ; + USE SIGNAL ; + ANTENNAPARTIALMETALAREA 0.7605 LAYER Metal2 ; + ANTENNAMODEL OXIDE1 ; + ANTENNAGATEAREA 0.20085 LAYER Metal2 ; + ANTENNAMAXAREACAR 5.055265 LAYER Metal2 ; + PORT + LAYER Metal2 ; + RECT 77.195 0 77.455 0.26 ; + END + END A_BIST_BM[6] + PIN A_DOUT[9] + DIRECTION OUTPUT ; + USE SIGNAL ; + ANTENNAPARTIALMETALAREA 3.7095 LAYER Metal2 ; + ANTENNADIFFAREA 0.988 LAYER Metal2 ; + PORT + LAYER Metal2 ; + RECT 158.48 0 158.74 0.26 ; + END + END A_DOUT[9] + PIN A_DOUT[6] + DIRECTION OUTPUT ; + USE SIGNAL ; + ANTENNAPARTIALMETALAREA 3.7095 LAYER Metal2 ; + ANTENNADIFFAREA 0.988 LAYER Metal2 ; + PORT + LAYER Metal2 ; + RECT 78.06 0 78.32 0.26 ; + END + END A_DOUT[6] + PIN A_DIN[10] + DIRECTION INPUT ; + USE SIGNAL ; + ANTENNAPARTIALMETALAREA 1.794 LAYER Metal2 ; + ANTENNAMODEL OXIDE1 ; + ANTENNAGATEAREA 0.20085 LAYER Metal2 ; + ANTENNAMAXAREACAR 9.838188 LAYER Metal2 ; + PORT + LAYER Metal2 ; + RECT 177.05 0 177.31 0.26 ; + END + END A_DIN[10] + PIN A_DIN[5] + DIRECTION INPUT ; + USE SIGNAL ; + ANTENNAPARTIALMETALAREA 1.794 LAYER Metal2 ; + ANTENNAMODEL OXIDE1 ; + ANTENNAGATEAREA 0.20085 LAYER Metal2 ; + ANTENNAMAXAREACAR 9.838188 LAYER Metal2 ; + PORT + LAYER Metal2 ; + RECT 59.49 0 59.75 0.26 ; + END + END A_DIN[5] + PIN A_BIST_DIN[10] + DIRECTION INPUT ; + USE SIGNAL ; + ANTENNAPARTIALMETALAREA 1.6263 LAYER Metal2 ; + ANTENNAMODEL OXIDE1 ; + ANTENNAGATEAREA 0.20085 LAYER Metal2 ; + ANTENNAMAXAREACAR 9.365945 LAYER Metal2 ; + PORT + LAYER Metal2 ; + RECT 176.195 0 176.455 0.26 ; + END + END A_BIST_DIN[10] + PIN A_BIST_DIN[5] + DIRECTION INPUT ; + USE SIGNAL ; + ANTENNAPARTIALMETALAREA 1.6263 LAYER Metal2 ; + ANTENNAMODEL OXIDE1 ; + ANTENNAGATEAREA 0.20085 LAYER Metal2 ; + ANTENNAMAXAREACAR 9.365945 LAYER Metal2 ; + PORT + LAYER Metal2 ; + RECT 60.345 0 60.605 0.26 ; + END + END A_BIST_DIN[5] + PIN A_BM[10] + DIRECTION INPUT ; + USE SIGNAL ; + ANTENNAPARTIALMETALAREA 0.7215 LAYER Metal2 ; + ANTENNAMODEL OXIDE1 ; + ANTENNAGATEAREA 0.20085 LAYER Metal2 ; + ANTENNAMAXAREACAR 4.498382 LAYER Metal2 ; + PORT + LAYER Metal2 ; + RECT 169.21 0 169.47 0.26 ; + END + END A_BM[10] + PIN A_BM[5] + DIRECTION INPUT ; + USE SIGNAL ; + ANTENNAPARTIALMETALAREA 0.7215 LAYER Metal2 ; + ANTENNAMODEL OXIDE1 ; + ANTENNAGATEAREA 0.20085 LAYER Metal2 ; + ANTENNAMAXAREACAR 4.498382 LAYER Metal2 ; + PORT + LAYER Metal2 ; + RECT 67.33 0 67.59 0.26 ; + END + END A_BM[5] + PIN A_BIST_BM[10] + DIRECTION INPUT ; + USE SIGNAL ; + ANTENNAPARTIALMETALAREA 0.7605 LAYER Metal2 ; + ANTENNAMODEL OXIDE1 ; + ANTENNAGATEAREA 0.20085 LAYER Metal2 ; + ANTENNAMAXAREACAR 5.055265 LAYER Metal2 ; + PORT + LAYER Metal2 ; + RECT 170.585 0 170.845 0.26 ; + END + END A_BIST_BM[10] + PIN A_BIST_BM[5] + DIRECTION INPUT ; + USE SIGNAL ; + ANTENNAPARTIALMETALAREA 0.7605 LAYER Metal2 ; + ANTENNAMODEL OXIDE1 ; + ANTENNAGATEAREA 0.20085 LAYER Metal2 ; + ANTENNAMAXAREACAR 5.055265 LAYER Metal2 ; + PORT + LAYER Metal2 ; + RECT 65.955 0 66.215 0.26 ; + END + END A_BIST_BM[5] + PIN A_DOUT[10] + DIRECTION OUTPUT ; + USE SIGNAL ; + ANTENNAPARTIALMETALAREA 3.7095 LAYER Metal2 ; + ANTENNADIFFAREA 0.988 LAYER Metal2 ; + PORT + LAYER Metal2 ; + RECT 169.72 0 169.98 0.26 ; + END + END A_DOUT[10] + PIN A_DOUT[5] + DIRECTION OUTPUT ; + USE SIGNAL ; + ANTENNAPARTIALMETALAREA 3.7095 LAYER Metal2 ; + ANTENNADIFFAREA 0.988 LAYER Metal2 ; + PORT + LAYER Metal2 ; + RECT 66.82 0 67.08 0.26 ; + END + END A_DOUT[5] + PIN A_DIN[11] + DIRECTION INPUT ; + USE SIGNAL ; + ANTENNAPARTIALMETALAREA 1.794 LAYER Metal2 ; + ANTENNAMODEL OXIDE1 ; + ANTENNAGATEAREA 0.20085 LAYER Metal2 ; + ANTENNAMAXAREACAR 9.838188 LAYER Metal2 ; + PORT + LAYER Metal2 ; + RECT 188.29 0 188.55 0.26 ; + END + END A_DIN[11] + PIN A_DIN[4] + DIRECTION INPUT ; + USE SIGNAL ; + ANTENNAPARTIALMETALAREA 1.794 LAYER Metal2 ; + ANTENNAMODEL OXIDE1 ; + ANTENNAGATEAREA 0.20085 LAYER Metal2 ; + ANTENNAMAXAREACAR 9.838188 LAYER Metal2 ; + PORT + LAYER Metal2 ; + RECT 48.25 0 48.51 0.26 ; + END + END A_DIN[4] + PIN A_BIST_DIN[11] + DIRECTION INPUT ; + USE SIGNAL ; + ANTENNAPARTIALMETALAREA 1.6263 LAYER Metal2 ; + ANTENNAMODEL OXIDE1 ; + ANTENNAGATEAREA 0.20085 LAYER Metal2 ; + ANTENNAMAXAREACAR 9.365945 LAYER Metal2 ; + PORT + LAYER Metal2 ; + RECT 187.435 0 187.695 0.26 ; + END + END A_BIST_DIN[11] + PIN A_BIST_DIN[4] + DIRECTION INPUT ; + USE SIGNAL ; + ANTENNAPARTIALMETALAREA 1.6263 LAYER Metal2 ; + ANTENNAMODEL OXIDE1 ; + ANTENNAGATEAREA 0.20085 LAYER Metal2 ; + ANTENNAMAXAREACAR 9.365945 LAYER Metal2 ; + PORT + LAYER Metal2 ; + RECT 49.105 0 49.365 0.26 ; + END + END A_BIST_DIN[4] + PIN A_BM[11] + DIRECTION INPUT ; + USE SIGNAL ; + ANTENNAPARTIALMETALAREA 0.7215 LAYER Metal2 ; + ANTENNAMODEL OXIDE1 ; + ANTENNAGATEAREA 0.20085 LAYER Metal2 ; + ANTENNAMAXAREACAR 4.498382 LAYER Metal2 ; + PORT + LAYER Metal2 ; + RECT 180.45 0 180.71 0.26 ; + END + END A_BM[11] + PIN A_BM[4] + DIRECTION INPUT ; + USE SIGNAL ; + ANTENNAPARTIALMETALAREA 0.7215 LAYER Metal2 ; + ANTENNAMODEL OXIDE1 ; + ANTENNAGATEAREA 0.20085 LAYER Metal2 ; + ANTENNAMAXAREACAR 4.498382 LAYER Metal2 ; + PORT + LAYER Metal2 ; + RECT 56.09 0 56.35 0.26 ; + END + END A_BM[4] + PIN A_BIST_BM[11] + DIRECTION INPUT ; + USE SIGNAL ; + ANTENNAPARTIALMETALAREA 0.7605 LAYER Metal2 ; + ANTENNAMODEL OXIDE1 ; + ANTENNAGATEAREA 0.20085 LAYER Metal2 ; + ANTENNAMAXAREACAR 5.055265 LAYER Metal2 ; + PORT + LAYER Metal2 ; + RECT 181.825 0 182.085 0.26 ; + END + END A_BIST_BM[11] + PIN A_BIST_BM[4] + DIRECTION INPUT ; + USE SIGNAL ; + ANTENNAPARTIALMETALAREA 0.7605 LAYER Metal2 ; + ANTENNAMODEL OXIDE1 ; + ANTENNAGATEAREA 0.20085 LAYER Metal2 ; + ANTENNAMAXAREACAR 5.055265 LAYER Metal2 ; + PORT + LAYER Metal2 ; + RECT 54.715 0 54.975 0.26 ; + END + END A_BIST_BM[4] + PIN A_DOUT[11] + DIRECTION OUTPUT ; + USE SIGNAL ; + ANTENNAPARTIALMETALAREA 3.7095 LAYER Metal2 ; + ANTENNADIFFAREA 0.988 LAYER Metal2 ; + PORT + LAYER Metal2 ; + RECT 180.96 0 181.22 0.26 ; + END + END A_DOUT[11] + PIN A_DOUT[4] + DIRECTION OUTPUT ; + USE SIGNAL ; + ANTENNAPARTIALMETALAREA 3.7095 LAYER Metal2 ; + ANTENNADIFFAREA 0.988 LAYER Metal2 ; + PORT + LAYER Metal2 ; + RECT 55.58 0 55.84 0.26 ; + END + END A_DOUT[4] + PIN A_DIN[12] + DIRECTION INPUT ; + USE SIGNAL ; + ANTENNAPARTIALMETALAREA 1.794 LAYER Metal2 ; + ANTENNAMODEL OXIDE1 ; + ANTENNAGATEAREA 0.20085 LAYER Metal2 ; + ANTENNAMAXAREACAR 9.838188 LAYER Metal2 ; + PORT + LAYER Metal2 ; + RECT 199.53 0 199.79 0.26 ; + END + END A_DIN[12] + PIN A_DIN[3] + DIRECTION INPUT ; + USE SIGNAL ; + ANTENNAPARTIALMETALAREA 1.794 LAYER Metal2 ; + ANTENNAMODEL OXIDE1 ; + ANTENNAGATEAREA 0.20085 LAYER Metal2 ; + ANTENNAMAXAREACAR 9.838188 LAYER Metal2 ; + PORT + LAYER Metal2 ; + RECT 37.01 0 37.27 0.26 ; + END + END A_DIN[3] + PIN A_BIST_DIN[12] + DIRECTION INPUT ; + USE SIGNAL ; + ANTENNAPARTIALMETALAREA 1.6263 LAYER Metal2 ; + ANTENNAMODEL OXIDE1 ; + ANTENNAGATEAREA 0.20085 LAYER Metal2 ; + ANTENNAMAXAREACAR 9.365945 LAYER Metal2 ; + PORT + LAYER Metal2 ; + RECT 198.675 0 198.935 0.26 ; + END + END A_BIST_DIN[12] + PIN A_BIST_DIN[3] + DIRECTION INPUT ; + USE SIGNAL ; + ANTENNAPARTIALMETALAREA 1.6263 LAYER Metal2 ; + ANTENNAMODEL OXIDE1 ; + ANTENNAGATEAREA 0.20085 LAYER Metal2 ; + ANTENNAMAXAREACAR 9.365945 LAYER Metal2 ; + PORT + LAYER Metal2 ; + RECT 37.865 0 38.125 0.26 ; + END + END A_BIST_DIN[3] + PIN A_BM[12] + DIRECTION INPUT ; + USE SIGNAL ; + ANTENNAPARTIALMETALAREA 0.7215 LAYER Metal2 ; + ANTENNAMODEL OXIDE1 ; + ANTENNAGATEAREA 0.20085 LAYER Metal2 ; + ANTENNAMAXAREACAR 4.498382 LAYER Metal2 ; + PORT + LAYER Metal2 ; + RECT 191.69 0 191.95 0.26 ; + END + END A_BM[12] + PIN A_BM[3] + DIRECTION INPUT ; + USE SIGNAL ; + ANTENNAPARTIALMETALAREA 0.7215 LAYER Metal2 ; + ANTENNAMODEL OXIDE1 ; + ANTENNAGATEAREA 0.20085 LAYER Metal2 ; + ANTENNAMAXAREACAR 4.498382 LAYER Metal2 ; + PORT + LAYER Metal2 ; + RECT 44.85 0 45.11 0.26 ; + END + END A_BM[3] + PIN A_BIST_BM[12] + DIRECTION INPUT ; + USE SIGNAL ; + ANTENNAPARTIALMETALAREA 0.7605 LAYER Metal2 ; + ANTENNAMODEL OXIDE1 ; + ANTENNAGATEAREA 0.20085 LAYER Metal2 ; + ANTENNAMAXAREACAR 5.055265 LAYER Metal2 ; + PORT + LAYER Metal2 ; + RECT 193.065 0 193.325 0.26 ; + END + END A_BIST_BM[12] + PIN A_BIST_BM[3] + DIRECTION INPUT ; + USE SIGNAL ; + ANTENNAPARTIALMETALAREA 0.7605 LAYER Metal2 ; + ANTENNAMODEL OXIDE1 ; + ANTENNAGATEAREA 0.20085 LAYER Metal2 ; + ANTENNAMAXAREACAR 5.055265 LAYER Metal2 ; + PORT + LAYER Metal2 ; + RECT 43.475 0 43.735 0.26 ; + END + END A_BIST_BM[3] + PIN A_DOUT[12] + DIRECTION OUTPUT ; + USE SIGNAL ; + ANTENNAPARTIALMETALAREA 3.7095 LAYER Metal2 ; + ANTENNADIFFAREA 0.988 LAYER Metal2 ; + PORT + LAYER Metal2 ; + RECT 192.2 0 192.46 0.26 ; + END + END A_DOUT[12] + PIN A_DOUT[3] + DIRECTION OUTPUT ; + USE SIGNAL ; + ANTENNAPARTIALMETALAREA 3.7095 LAYER Metal2 ; + ANTENNADIFFAREA 0.988 LAYER Metal2 ; + PORT + LAYER Metal2 ; + RECT 44.34 0 44.6 0.26 ; + END + END A_DOUT[3] + PIN A_DIN[13] + DIRECTION INPUT ; + USE SIGNAL ; + ANTENNAPARTIALMETALAREA 1.794 LAYER Metal2 ; + ANTENNAMODEL OXIDE1 ; + ANTENNAGATEAREA 0.20085 LAYER Metal2 ; + ANTENNAMAXAREACAR 9.838188 LAYER Metal2 ; + PORT + LAYER Metal2 ; + RECT 210.77 0 211.03 0.26 ; + END + END A_DIN[13] + PIN A_DIN[2] + DIRECTION INPUT ; + USE SIGNAL ; + ANTENNAPARTIALMETALAREA 1.794 LAYER Metal2 ; + ANTENNAMODEL OXIDE1 ; + ANTENNAGATEAREA 0.20085 LAYER Metal2 ; + ANTENNAMAXAREACAR 9.838188 LAYER Metal2 ; + PORT + LAYER Metal2 ; + RECT 25.77 0 26.03 0.26 ; + END + END A_DIN[2] + PIN A_BIST_DIN[13] + DIRECTION INPUT ; + USE SIGNAL ; + ANTENNAPARTIALMETALAREA 1.6263 LAYER Metal2 ; + ANTENNAMODEL OXIDE1 ; + ANTENNAGATEAREA 0.20085 LAYER Metal2 ; + ANTENNAMAXAREACAR 9.365945 LAYER Metal2 ; + PORT + LAYER Metal2 ; + RECT 209.915 0 210.175 0.26 ; + END + END A_BIST_DIN[13] + PIN A_BIST_DIN[2] + DIRECTION INPUT ; + USE SIGNAL ; + ANTENNAPARTIALMETALAREA 1.6263 LAYER Metal2 ; + ANTENNAMODEL OXIDE1 ; + ANTENNAGATEAREA 0.20085 LAYER Metal2 ; + ANTENNAMAXAREACAR 9.365945 LAYER Metal2 ; + PORT + LAYER Metal2 ; + RECT 26.625 0 26.885 0.26 ; + END + END A_BIST_DIN[2] + PIN A_BM[13] + DIRECTION INPUT ; + USE SIGNAL ; + ANTENNAPARTIALMETALAREA 0.7215 LAYER Metal2 ; + ANTENNAMODEL OXIDE1 ; + ANTENNAGATEAREA 0.20085 LAYER Metal2 ; + ANTENNAMAXAREACAR 4.498382 LAYER Metal2 ; + PORT + LAYER Metal2 ; + RECT 202.93 0 203.19 0.26 ; + END + END A_BM[13] + PIN A_BM[2] + DIRECTION INPUT ; + USE SIGNAL ; + ANTENNAPARTIALMETALAREA 0.7215 LAYER Metal2 ; + ANTENNAMODEL OXIDE1 ; + ANTENNAGATEAREA 0.20085 LAYER Metal2 ; + ANTENNAMAXAREACAR 4.498382 LAYER Metal2 ; + PORT + LAYER Metal2 ; + RECT 33.61 0 33.87 0.26 ; + END + END A_BM[2] + PIN A_BIST_BM[13] + DIRECTION INPUT ; + USE SIGNAL ; + ANTENNAPARTIALMETALAREA 0.7605 LAYER Metal2 ; + ANTENNAMODEL OXIDE1 ; + ANTENNAGATEAREA 0.20085 LAYER Metal2 ; + ANTENNAMAXAREACAR 5.055265 LAYER Metal2 ; + PORT + LAYER Metal2 ; + RECT 204.305 0 204.565 0.26 ; + END + END A_BIST_BM[13] + PIN A_BIST_BM[2] + DIRECTION INPUT ; + USE SIGNAL ; + ANTENNAPARTIALMETALAREA 0.7605 LAYER Metal2 ; + ANTENNAMODEL OXIDE1 ; + ANTENNAGATEAREA 0.20085 LAYER Metal2 ; + ANTENNAMAXAREACAR 5.055265 LAYER Metal2 ; + PORT + LAYER Metal2 ; + RECT 32.235 0 32.495 0.26 ; + END + END A_BIST_BM[2] + PIN A_DOUT[13] + DIRECTION OUTPUT ; + USE SIGNAL ; + ANTENNAPARTIALMETALAREA 3.7095 LAYER Metal2 ; + ANTENNADIFFAREA 0.988 LAYER Metal2 ; + PORT + LAYER Metal2 ; + RECT 203.44 0 203.7 0.26 ; + END + END A_DOUT[13] + PIN A_DOUT[2] + DIRECTION OUTPUT ; + USE SIGNAL ; + ANTENNAPARTIALMETALAREA 3.7095 LAYER Metal2 ; + ANTENNADIFFAREA 0.988 LAYER Metal2 ; + PORT + LAYER Metal2 ; + RECT 33.1 0 33.36 0.26 ; + END + END A_DOUT[2] + PIN A_DIN[14] + DIRECTION INPUT ; + USE SIGNAL ; + ANTENNAPARTIALMETALAREA 1.794 LAYER Metal2 ; + ANTENNAMODEL OXIDE1 ; + ANTENNAGATEAREA 0.20085 LAYER Metal2 ; + ANTENNAMAXAREACAR 9.838188 LAYER Metal2 ; + PORT + LAYER Metal2 ; + RECT 222.01 0 222.27 0.26 ; + END + END A_DIN[14] + PIN A_DIN[1] + DIRECTION INPUT ; + USE SIGNAL ; + ANTENNAPARTIALMETALAREA 1.794 LAYER Metal2 ; + ANTENNAMODEL OXIDE1 ; + ANTENNAGATEAREA 0.20085 LAYER Metal2 ; + ANTENNAMAXAREACAR 9.838188 LAYER Metal2 ; + PORT + LAYER Metal2 ; + RECT 14.53 0 14.79 0.26 ; + END + END A_DIN[1] + PIN A_BIST_DIN[14] + DIRECTION INPUT ; + USE SIGNAL ; + ANTENNAPARTIALMETALAREA 1.6263 LAYER Metal2 ; + ANTENNAMODEL OXIDE1 ; + ANTENNAGATEAREA 0.20085 LAYER Metal2 ; + ANTENNAMAXAREACAR 9.365945 LAYER Metal2 ; + PORT + LAYER Metal2 ; + RECT 221.155 0 221.415 0.26 ; + END + END A_BIST_DIN[14] + PIN A_BIST_DIN[1] + DIRECTION INPUT ; + USE SIGNAL ; + ANTENNAPARTIALMETALAREA 1.6263 LAYER Metal2 ; + ANTENNAMODEL OXIDE1 ; + ANTENNAGATEAREA 0.20085 LAYER Metal2 ; + ANTENNAMAXAREACAR 9.365945 LAYER Metal2 ; + PORT + LAYER Metal2 ; + RECT 15.385 0 15.645 0.26 ; + END + END A_BIST_DIN[1] + PIN A_BM[14] + DIRECTION INPUT ; + USE SIGNAL ; + ANTENNAPARTIALMETALAREA 0.7215 LAYER Metal2 ; + ANTENNAMODEL OXIDE1 ; + ANTENNAGATEAREA 0.20085 LAYER Metal2 ; + ANTENNAMAXAREACAR 4.498382 LAYER Metal2 ; + PORT + LAYER Metal2 ; + RECT 214.17 0 214.43 0.26 ; + END + END A_BM[14] + PIN A_BM[1] + DIRECTION INPUT ; + USE SIGNAL ; + ANTENNAPARTIALMETALAREA 0.7215 LAYER Metal2 ; + ANTENNAMODEL OXIDE1 ; + ANTENNAGATEAREA 0.20085 LAYER Metal2 ; + ANTENNAMAXAREACAR 4.498382 LAYER Metal2 ; + PORT + LAYER Metal2 ; + RECT 22.37 0 22.63 0.26 ; + END + END A_BM[1] + PIN A_BIST_BM[14] + DIRECTION INPUT ; + USE SIGNAL ; + ANTENNAPARTIALMETALAREA 0.7605 LAYER Metal2 ; + ANTENNAMODEL OXIDE1 ; + ANTENNAGATEAREA 0.20085 LAYER Metal2 ; + ANTENNAMAXAREACAR 5.055265 LAYER Metal2 ; + PORT + LAYER Metal2 ; + RECT 215.545 0 215.805 0.26 ; + END + END A_BIST_BM[14] + PIN A_BIST_BM[1] + DIRECTION INPUT ; + USE SIGNAL ; + ANTENNAPARTIALMETALAREA 0.7605 LAYER Metal2 ; + ANTENNAMODEL OXIDE1 ; + ANTENNAGATEAREA 0.20085 LAYER Metal2 ; + ANTENNAMAXAREACAR 5.055265 LAYER Metal2 ; + PORT + LAYER Metal2 ; + RECT 20.995 0 21.255 0.26 ; + END + END A_BIST_BM[1] + PIN A_DOUT[14] + DIRECTION OUTPUT ; + USE SIGNAL ; + ANTENNAPARTIALMETALAREA 3.7095 LAYER Metal2 ; + ANTENNADIFFAREA 0.988 LAYER Metal2 ; + PORT + LAYER Metal2 ; + RECT 214.68 0 214.94 0.26 ; + END + END A_DOUT[14] + PIN A_DOUT[1] + DIRECTION OUTPUT ; + USE SIGNAL ; + ANTENNAPARTIALMETALAREA 3.7095 LAYER Metal2 ; + ANTENNADIFFAREA 0.988 LAYER Metal2 ; + PORT + LAYER Metal2 ; + RECT 21.86 0 22.12 0.26 ; + END + END A_DOUT[1] + PIN A_DIN[15] + DIRECTION INPUT ; + USE SIGNAL ; + ANTENNAPARTIALMETALAREA 1.794 LAYER Metal2 ; + ANTENNAMODEL OXIDE1 ; + ANTENNAGATEAREA 0.20085 LAYER Metal2 ; + ANTENNAMAXAREACAR 9.838188 LAYER Metal2 ; + PORT + LAYER Metal2 ; + RECT 233.25 0 233.51 0.26 ; + END + END A_DIN[15] + PIN A_DIN[0] + DIRECTION INPUT ; + USE SIGNAL ; + ANTENNAPARTIALMETALAREA 1.794 LAYER Metal2 ; + ANTENNAMODEL OXIDE1 ; + ANTENNAGATEAREA 0.20085 LAYER Metal2 ; + ANTENNAMAXAREACAR 9.838188 LAYER Metal2 ; + PORT + LAYER Metal2 ; + RECT 3.29 0 3.55 0.26 ; + END + END A_DIN[0] + PIN A_BIST_DIN[15] + DIRECTION INPUT ; + USE SIGNAL ; + ANTENNAPARTIALMETALAREA 1.6263 LAYER Metal2 ; + ANTENNAMODEL OXIDE1 ; + ANTENNAGATEAREA 0.20085 LAYER Metal2 ; + ANTENNAMAXAREACAR 9.365945 LAYER Metal2 ; + PORT + LAYER Metal2 ; + RECT 232.395 0 232.655 0.26 ; + END + END A_BIST_DIN[15] + PIN A_BIST_DIN[0] + DIRECTION INPUT ; + USE SIGNAL ; + ANTENNAPARTIALMETALAREA 1.6263 LAYER Metal2 ; + ANTENNAMODEL OXIDE1 ; + ANTENNAGATEAREA 0.20085 LAYER Metal2 ; + ANTENNAMAXAREACAR 9.365945 LAYER Metal2 ; + PORT + LAYER Metal2 ; + RECT 4.145 0 4.405 0.26 ; + END + END A_BIST_DIN[0] + PIN A_BM[15] + DIRECTION INPUT ; + USE SIGNAL ; + ANTENNAPARTIALMETALAREA 0.7215 LAYER Metal2 ; + ANTENNAMODEL OXIDE1 ; + ANTENNAGATEAREA 0.20085 LAYER Metal2 ; + ANTENNAMAXAREACAR 4.498382 LAYER Metal2 ; + PORT + LAYER Metal2 ; + RECT 225.41 0 225.67 0.26 ; + END + END A_BM[15] + PIN A_BM[0] + DIRECTION INPUT ; + USE SIGNAL ; + ANTENNAPARTIALMETALAREA 0.7215 LAYER Metal2 ; + ANTENNAMODEL OXIDE1 ; + ANTENNAGATEAREA 0.20085 LAYER Metal2 ; + ANTENNAMAXAREACAR 4.498382 LAYER Metal2 ; + PORT + LAYER Metal2 ; + RECT 11.13 0 11.39 0.26 ; + END + END A_BM[0] + PIN A_BIST_BM[15] + DIRECTION INPUT ; + USE SIGNAL ; + ANTENNAPARTIALMETALAREA 0.7605 LAYER Metal2 ; + ANTENNAMODEL OXIDE1 ; + ANTENNAGATEAREA 0.20085 LAYER Metal2 ; + ANTENNAMAXAREACAR 5.055265 LAYER Metal2 ; + PORT + LAYER Metal2 ; + RECT 226.785 0 227.045 0.26 ; + END + END A_BIST_BM[15] + PIN A_BIST_BM[0] + DIRECTION INPUT ; + USE SIGNAL ; + ANTENNAPARTIALMETALAREA 0.7605 LAYER Metal2 ; + ANTENNAMODEL OXIDE1 ; + ANTENNAGATEAREA 0.20085 LAYER Metal2 ; + ANTENNAMAXAREACAR 5.055265 LAYER Metal2 ; + PORT + LAYER Metal2 ; + RECT 9.755 0 10.015 0.26 ; + END + END A_BIST_BM[0] + PIN A_DOUT[15] + DIRECTION OUTPUT ; + USE SIGNAL ; + ANTENNAPARTIALMETALAREA 3.7095 LAYER Metal2 ; + ANTENNADIFFAREA 0.988 LAYER Metal2 ; + PORT + LAYER Metal2 ; + RECT 225.92 0 226.18 0.26 ; + END + END A_DOUT[15] + PIN A_DOUT[0] + DIRECTION OUTPUT ; + USE SIGNAL ; + ANTENNAPARTIALMETALAREA 3.7095 LAYER Metal2 ; + ANTENNADIFFAREA 0.988 LAYER Metal2 ; + PORT + LAYER Metal2 ; + RECT 10.62 0 10.88 0.26 ; + END + END A_DOUT[0] + PIN A_ADDR[0] + DIRECTION INPUT ; + USE SIGNAL ; + ANTENNAPARTIALMETALAREA 8.9011 LAYER Metal2 ; + ANTENNAMODEL OXIDE1 ; + ANTENNAGATEAREA 0.20085 LAYER Metal2 ; + ANTENNAMAXAREACAR 45.223301 LAYER Metal2 ; + PORT + LAYER Metal2 ; + RECT 114.6 0 114.86 0.26 ; + END + END A_ADDR[0] + PIN A_BIST_ADDR[0] + DIRECTION INPUT ; + USE SIGNAL ; + ANTENNAPARTIALMETALAREA 9.6967 LAYER Metal2 ; + ANTENNAMODEL OXIDE1 ; + ANTENNAGATEAREA 0.20085 LAYER Metal2 ; + ANTENNAMAXAREACAR 49.184466 LAYER Metal2 ; + PORT + LAYER Metal2 ; + RECT 119.19 0 119.45 0.26 ; + END + END A_BIST_ADDR[0] + PIN A_ADDR[1] + DIRECTION INPUT ; + USE SIGNAL ; + ANTENNAPARTIALMETALAREA 7.774 LAYER Metal2 ; + ANTENNAMODEL OXIDE1 ; + ANTENNAGATEAREA 0.20085 LAYER Metal2 ; + ANTENNAMAXAREACAR 39.656958 LAYER Metal2 ; + PORT + LAYER Metal2 ; + RECT 114.09 0 114.35 0.26 ; + END + END A_ADDR[1] + PIN A_BIST_ADDR[1] + DIRECTION INPUT ; + USE SIGNAL ; + ANTENNAPARTIALMETALAREA 8.5696 LAYER Metal2 ; + ANTENNAMODEL OXIDE1 ; + ANTENNAGATEAREA 0.20085 LAYER Metal2 ; + ANTENNAMAXAREACAR 43.618123 LAYER Metal2 ; + PORT + LAYER Metal2 ; + RECT 118.68 0 118.94 0.26 ; + END + END A_BIST_ADDR[1] + PIN A_ADDR[2] + DIRECTION INPUT ; + USE SIGNAL ; + ANTENNAPARTIALMETALAREA 10.6327 LAYER Metal2 ; + ANTENNAPARTIALMETALAREA 1.5246 LAYER Metal3 ; + ANTENNAPARTIALCUTAREA 0.0722 LAYER Via2 ; + ANTENNAMODEL OXIDE1 ; + ANTENNAGATEAREA 0.20085 LAYER Metal3 ; + ANTENNAMAXAREACAR 9.415982 LAYER Metal3 ; + PORT + LAYER Metal2 ; + RECT 122.25 0 122.51 0.26 ; + END + END A_ADDR[2] + PIN A_BIST_ADDR[2] + DIRECTION INPUT ; + USE SIGNAL ; + ANTENNAPARTIALMETALAREA 10.6327 LAYER Metal2 ; + ANTENNAPARTIALMETALAREA 1.0962 LAYER Metal3 ; + ANTENNAPARTIALCUTAREA 0.0722 LAYER Via2 ; + ANTENNAMODEL OXIDE1 ; + ANTENNAGATEAREA 0.20085 LAYER Metal3 ; + ANTENNAMAXAREACAR 7.813791 LAYER Metal3 ; + PORT + LAYER Metal2 ; + RECT 122.76 0 123.02 0.26 ; + END + END A_BIST_ADDR[2] + PIN A_ADDR[3] + DIRECTION INPUT ; + USE SIGNAL ; + ANTENNAPARTIALMETALAREA 10.6327 LAYER Metal2 ; + ANTENNAPARTIALMETALAREA 3.8367 LAYER Metal3 ; + ANTENNAPARTIALCUTAREA 0.0722 LAYER Via2 ; + ANTENNAMODEL OXIDE1 ; + ANTENNAGATEAREA 0.20085 LAYER Metal3 ; + ANTENNAMAXAREACAR 20.927558 LAYER Metal3 ; + PORT + LAYER Metal2 ; + RECT 121.23 0 121.49 0.26 ; + END + END A_ADDR[3] + PIN A_BIST_ADDR[3] + DIRECTION INPUT ; + USE SIGNAL ; + ANTENNAPARTIALMETALAREA 10.6327 LAYER Metal2 ; + ANTENNAPARTIALMETALAREA 3.5175 LAYER Metal3 ; + ANTENNAPARTIALCUTAREA 0.0722 LAYER Via2 ; + ANTENNAMODEL OXIDE1 ; + ANTENNAGATEAREA 0.20085 LAYER Metal3 ; + ANTENNAMAXAREACAR 19.869057 LAYER Metal3 ; + PORT + LAYER Metal2 ; + RECT 121.74 0 122 0.26 ; + END + END A_BIST_ADDR[3] + PIN A_ADDR[4] + DIRECTION INPUT ; + USE SIGNAL ; + ANTENNAPARTIALMETALAREA 12.1979 LAYER Metal2 ; + ANTENNAMODEL OXIDE1 ; + ANTENNAGATEAREA 0.20085 LAYER Metal2 ; + ANTENNAMAXAREACAR 61.63754 LAYER Metal2 ; + PORT + LAYER Metal2 ; + RECT 124.8 0 125.06 0.26 ; + END + END A_ADDR[4] + PIN A_BIST_ADDR[4] + DIRECTION INPUT ; + USE SIGNAL ; + ANTENNAPARTIALMETALAREA 11.9327 LAYER Metal2 ; + ANTENNAMODEL OXIDE1 ; + ANTENNAGATEAREA 0.20085 LAYER Metal2 ; + ANTENNAMAXAREACAR 60.317152 LAYER Metal2 ; + PORT + LAYER Metal2 ; + RECT 124.29 0 124.55 0.26 ; + END + END A_BIST_ADDR[4] + PIN A_ADDR[5] + DIRECTION INPUT ; + USE SIGNAL ; + ANTENNAPARTIALMETALAREA 13.9269 LAYER Metal2 ; + ANTENNAMODEL OXIDE1 ; + ANTENNAGATEAREA 0.20085 LAYER Metal2 ; + ANTENNAMAXAREACAR 70.245955 LAYER Metal2 ; + PORT + LAYER Metal2 ; + RECT 123.78 0 124.04 0.26 ; + END + END A_ADDR[5] + PIN A_BIST_ADDR[5] + DIRECTION INPUT ; + USE SIGNAL ; + ANTENNAPARTIALMETALAREA 13.6617 LAYER Metal2 ; + ANTENNAMODEL OXIDE1 ; + ANTENNAGATEAREA 0.20085 LAYER Metal2 ; + ANTENNAMAXAREACAR 68.925566 LAYER Metal2 ; + PORT + LAYER Metal2 ; + RECT 123.27 0 123.53 0.26 ; + END + END A_BIST_ADDR[5] + PIN A_ADDR[6] + DIRECTION INPUT ; + USE SIGNAL ; + ANTENNAPARTIALMETALAREA 10.9525 LAYER Metal2 ; + ANTENNAMODEL OXIDE1 ; + ANTENNAGATEAREA 0.20085 LAYER Metal2 ; + ANTENNAMAXAREACAR 55.436893 LAYER Metal2 ; + PORT + LAYER Metal2 ; + RECT 102.36 0 102.62 0.26 ; + END + END A_ADDR[6] + PIN A_BIST_ADDR[6] + DIRECTION INPUT ; + USE SIGNAL ; + ANTENNAPARTIALMETALAREA 10.6771 LAYER Metal2 ; + ANTENNAMODEL OXIDE1 ; + ANTENNAGATEAREA 0.20085 LAYER Metal2 ; + ANTENNAMAXAREACAR 54.065721 LAYER Metal2 ; + PORT + LAYER Metal2 ; + RECT 102.87 0 103.13 0.26 ; + END + END A_BIST_ADDR[6] + PIN A_ADDR[7] + DIRECTION INPUT ; + USE SIGNAL ; + ANTENNAPARTIALMETALAREA 12.4163 LAYER Metal2 ; + ANTENNAMODEL OXIDE1 ; + ANTENNAGATEAREA 0.20085 LAYER Metal2 ; + ANTENNAMAXAREACAR 62.724919 LAYER Metal2 ; + PORT + LAYER Metal2 ; + RECT 103.38 0 103.64 0.26 ; + END + END A_ADDR[7] + PIN A_BIST_ADDR[7] + DIRECTION INPUT ; + USE SIGNAL ; + ANTENNAPARTIALMETALAREA 12.1511 LAYER Metal2 ; + ANTENNAMODEL OXIDE1 ; + ANTENNAGATEAREA 0.20085 LAYER Metal2 ; + ANTENNAMAXAREACAR 61.404531 LAYER Metal2 ; + PORT + LAYER Metal2 ; + RECT 103.89 0 104.15 0.26 ; + END + END A_BIST_ADDR[7] + PIN A_CLK + DIRECTION INPUT ; + USE SIGNAL ; + ANTENNAPARTIALMETALAREA 4.0547 LAYER Metal2 ; + ANTENNAMODEL OXIDE1 ; + ANTENNAGATEAREA 0.20085 LAYER Metal2 ; + ANTENNAMAXAREACAR 21.093851 LAYER Metal2 ; + PORT + LAYER Metal2 ; + RECT 112.56 0 112.82 0.26 ; + END + END A_CLK + PIN A_REN + DIRECTION INPUT ; + USE SIGNAL ; + ANTENNAPARTIALMETALAREA 3.99505 LAYER Metal2 ; + ANTENNAMODEL OXIDE1 ; + ANTENNAGATEAREA 0.20085 LAYER Metal2 ; + ANTENNAMAXAREACAR 20.796863 LAYER Metal2 ; + PORT + LAYER Metal2 ; + RECT 116.13 0 116.39 0.26 ; + END + END A_REN + PIN A_WEN + DIRECTION INPUT ; + USE SIGNAL ; + ANTENNAPARTIALMETALAREA 2.8847 LAYER Metal2 ; + ANTENNAMODEL OXIDE1 ; + ANTENNAGATEAREA 0.20085 LAYER Metal2 ; + ANTENNAMAXAREACAR 15.268608 LAYER Metal2 ; + PORT + LAYER Metal2 ; + RECT 115.62 0 115.88 0.26 ; + END + END A_WEN + PIN A_MEN + DIRECTION INPUT ; + USE SIGNAL ; + ANTENNAPARTIALMETALAREA 3.0247 LAYER Metal2 ; + ANTENNAMODEL OXIDE1 ; + ANTENNAGATEAREA 0.20085 LAYER Metal2 ; + ANTENNAMAXAREACAR 15.965646 LAYER Metal2 ; + PORT + LAYER Metal2 ; + RECT 113.07 0 113.33 0.26 ; + END + END A_MEN + PIN A_DLY + DIRECTION INPUT ; + USE SIGNAL ; + ANTENNAPARTIALMETALAREA 6.058 LAYER Metal2 ; + ANTENNAMODEL OXIDE1 ; + ANTENNAGATEAREA 0.3367 LAYER Metal2 ; + ANTENNAMAXAREACAR 18.532819 LAYER Metal2 ; + PORT + LAYER Metal2 ; + RECT 134.49 0 134.75 0.26 ; + END + END A_DLY + PIN A_BIST_EN + DIRECTION INPUT ; + USE SIGNAL ; + ANTENNAPARTIALMETALAREA 3.9871 LAYER Metal2 ; + ANTENNAPARTIALMETALAREA 114.62575 LAYER Metal3 ; + ANTENNAPARTIALCUTAREA 0.0722 LAYER Via2 ; + ANTENNAMODEL OXIDE1 ; + ANTENNAGATEAREA 1.43 LAYER Metal2 ; + ANTENNAGATEAREA 15.73 LAYER Metal3 ; + ANTENNAMAXAREACAR 3.213636 LAYER Metal2 ; + ANTENNAMAXAREACAR 17.559806 LAYER Metal3 ; + ANTENNAMAXCUTCAR 0.151469 LAYER Via2 ; + PORT + LAYER Metal2 ; + RECT 115.11 0 115.37 0.26 ; + END + END A_BIST_EN + PIN A_BIST_CLK + DIRECTION INPUT ; + USE SIGNAL ; + ANTENNAPARTIALMETALAREA 4.1639 LAYER Metal2 ; + ANTENNAMODEL OXIDE1 ; + ANTENNAGATEAREA 0.20085 LAYER Metal2 ; + ANTENNAMAXAREACAR 21.953448 LAYER Metal2 ; + PORT + LAYER Metal2 ; + RECT 111.03 0 111.29 0.26 ; + END + END A_BIST_CLK + PIN A_BIST_REN + DIRECTION INPUT ; + USE SIGNAL ; + ANTENNAPARTIALMETALAREA 4.1119 LAYER Metal2 ; + ANTENNAMODEL OXIDE1 ; + ANTENNAGATEAREA 0.20085 LAYER Metal2 ; + ANTENNAMAXAREACAR 21.694548 LAYER Metal2 ; + PORT + LAYER Metal2 ; + RECT 117.66 0 117.92 0.26 ; + END + END A_BIST_REN + PIN A_BIST_WEN + DIRECTION INPUT ; + USE SIGNAL ; + ANTENNAPARTIALMETALAREA 2.9051 LAYER Metal2 ; + ANTENNAMODEL OXIDE1 ; + ANTENNAGATEAREA 0.20085 LAYER Metal2 ; + ANTENNAMAXAREACAR 15.686084 LAYER Metal2 ; + PORT + LAYER Metal2 ; + RECT 117.15 0 117.41 0.26 ; + END + END A_BIST_WEN + PIN A_BIST_MEN + DIRECTION INPUT ; + USE SIGNAL ; + ANTENNAPARTIALMETALAREA 2.8977 LAYER Metal2 ; + ANTENNAMODEL OXIDE1 ; + ANTENNAGATEAREA 0.20085 LAYER Metal2 ; + ANTENNAMAXAREACAR 15.649241 LAYER Metal2 ; + PORT + LAYER Metal2 ; + RECT 111.54 0 111.8 0.26 ; + END + END A_BIST_MEN + OBS + LAYER Metal1 ; + RECT 0 0 236.8 118.78 ; + LAYER Metal2 ; + RECT 0.105 45.465 0.305 118.755 ; + RECT 1.1 118.025 1.3 118.755 ; + RECT 3.29 0.52 3.55 5.16 ; + RECT 2.77 4.9 3.55 5.16 ; + RECT 2.77 4.9 3.03 6.64 ; + RECT 1.92 118.025 2.12 118.755 ; + RECT 2.415 118.025 2.615 118.755 ; + RECT 2.915 118.025 3.115 118.755 ; + RECT 3.415 118.025 3.615 118.755 ; + RECT 3.91 118.025 4.11 118.755 ; + RECT 4.655 0.17 5.425 0.94 ; + RECT 4.655 0.17 4.915 12.9 ; + RECT 5.165 0.17 5.425 12.9 ; + RECT 4.145 0.52 4.405 5.815 ; + RECT 4.73 118.025 4.93 118.755 ; + RECT 5.675 0.17 6.445 0.43 ; + RECT 5.675 0.17 5.935 11.5 ; + RECT 6.185 0.17 6.445 11.5 ; + RECT 5.225 118.025 5.425 118.755 ; + RECT 5.725 118.025 5.925 118.755 ; + RECT 6.225 118.025 6.425 118.755 ; + RECT 7.715 0.17 8.485 0.43 ; + RECT 7.715 0.17 7.975 10.48 ; + RECT 8.225 0.17 8.485 10.99 ; + RECT 6.72 118.025 6.92 118.755 ; + RECT 7.54 118.025 7.74 118.755 ; + RECT 8.735 0.17 9.505 0.94 ; + RECT 8.735 0.17 8.995 8.7 ; + RECT 9.245 0.17 9.505 12.9 ; + RECT 8.035 118.025 8.235 118.755 ; + RECT 8.535 118.025 8.735 118.755 ; + RECT 9.035 118.025 9.235 118.755 ; + RECT 9.53 118.025 9.73 118.755 ; + RECT 9.755 0.52 10.015 2.485 ; + RECT 10.35 118.025 10.55 118.755 ; + RECT 10.62 0.52 10.88 14.11 ; + RECT 10.845 118.025 11.045 118.755 ; + RECT 11.13 0.52 11.39 2.335 ; + RECT 11.345 118.025 11.545 118.755 ; + RECT 11.845 118.025 12.045 118.755 ; + RECT 12.34 118.025 12.54 118.755 ; + RECT 14.53 0.52 14.79 5.16 ; + RECT 14.01 4.9 14.79 5.16 ; + RECT 14.01 4.9 14.27 6.64 ; + RECT 13.16 118.025 13.36 118.755 ; + RECT 13.655 118.025 13.855 118.755 ; + RECT 14.155 118.025 14.355 118.755 ; + RECT 14.655 118.025 14.855 118.755 ; + RECT 15.15 118.025 15.35 118.755 ; + RECT 15.895 0.17 16.665 0.94 ; + RECT 15.895 0.17 16.155 12.9 ; + RECT 16.405 0.17 16.665 12.9 ; + RECT 15.385 0.52 15.645 5.815 ; + RECT 15.97 118.025 16.17 118.755 ; + RECT 16.915 0.17 17.685 0.43 ; + RECT 16.915 0.17 17.175 11.5 ; + RECT 17.425 0.17 17.685 11.5 ; + RECT 16.465 118.025 16.665 118.755 ; + RECT 16.965 118.025 17.165 118.755 ; + RECT 17.465 118.025 17.665 118.755 ; + RECT 18.955 0.17 19.725 0.43 ; + RECT 18.955 0.17 19.215 10.48 ; + RECT 19.465 0.17 19.725 10.99 ; + RECT 17.96 118.025 18.16 118.755 ; + RECT 18.78 118.025 18.98 118.755 ; + RECT 19.975 0.17 20.745 0.94 ; + RECT 19.975 0.17 20.235 8.7 ; + RECT 20.485 0.17 20.745 12.9 ; + RECT 19.275 118.025 19.475 118.755 ; + RECT 19.775 118.025 19.975 118.755 ; + RECT 20.275 118.025 20.475 118.755 ; + RECT 20.77 118.025 20.97 118.755 ; + RECT 20.995 0.52 21.255 2.485 ; + RECT 21.59 118.025 21.79 118.755 ; + RECT 21.86 0.52 22.12 14.11 ; + RECT 22.085 118.025 22.285 118.755 ; + RECT 22.37 0.52 22.63 2.335 ; + RECT 22.585 118.025 22.785 118.755 ; + RECT 23.085 118.025 23.285 118.755 ; + RECT 23.58 118.025 23.78 118.755 ; + RECT 25.77 0.52 26.03 5.16 ; + RECT 25.25 4.9 26.03 5.16 ; + RECT 25.25 4.9 25.51 6.64 ; + RECT 24.4 118.025 24.6 118.755 ; + RECT 24.895 118.025 25.095 118.755 ; + RECT 25.395 118.025 25.595 118.755 ; + RECT 25.895 118.025 26.095 118.755 ; + RECT 26.39 118.025 26.59 118.755 ; + RECT 27.135 0.17 27.905 0.94 ; + RECT 27.135 0.17 27.395 12.9 ; + RECT 27.645 0.17 27.905 12.9 ; + RECT 26.625 0.52 26.885 5.815 ; + RECT 27.21 118.025 27.41 118.755 ; + RECT 28.155 0.17 28.925 0.43 ; + RECT 28.155 0.17 28.415 11.5 ; + RECT 28.665 0.17 28.925 11.5 ; + RECT 27.705 118.025 27.905 118.755 ; + RECT 28.205 118.025 28.405 118.755 ; + RECT 28.705 118.025 28.905 118.755 ; + RECT 30.195 0.17 30.965 0.43 ; + RECT 30.195 0.17 30.455 10.48 ; + RECT 30.705 0.17 30.965 10.99 ; + RECT 29.2 118.025 29.4 118.755 ; + RECT 30.02 118.025 30.22 118.755 ; + RECT 31.215 0.17 31.985 0.94 ; + RECT 31.215 0.17 31.475 8.7 ; + RECT 31.725 0.17 31.985 12.9 ; + RECT 30.515 118.025 30.715 118.755 ; + RECT 31.015 118.025 31.215 118.755 ; + RECT 31.515 118.025 31.715 118.755 ; + RECT 32.01 118.025 32.21 118.755 ; + RECT 32.235 0.52 32.495 2.485 ; + RECT 32.83 118.025 33.03 118.755 ; + RECT 33.1 0.52 33.36 14.11 ; + RECT 33.325 118.025 33.525 118.755 ; + RECT 33.61 0.52 33.87 2.335 ; + RECT 33.825 118.025 34.025 118.755 ; + RECT 34.325 118.025 34.525 118.755 ; + RECT 34.82 118.025 35.02 118.755 ; + RECT 37.01 0.52 37.27 5.16 ; + RECT 36.49 4.9 37.27 5.16 ; + RECT 36.49 4.9 36.75 6.64 ; + RECT 35.64 118.025 35.84 118.755 ; + RECT 36.135 118.025 36.335 118.755 ; + RECT 36.635 118.025 36.835 118.755 ; + RECT 37.135 118.025 37.335 118.755 ; + RECT 37.63 118.025 37.83 118.755 ; + RECT 38.375 0.17 39.145 0.94 ; + RECT 38.375 0.17 38.635 12.9 ; + RECT 38.885 0.17 39.145 12.9 ; + RECT 37.865 0.52 38.125 5.815 ; + RECT 38.45 118.025 38.65 118.755 ; + RECT 39.395 0.17 40.165 0.43 ; + RECT 39.395 0.17 39.655 11.5 ; + RECT 39.905 0.17 40.165 11.5 ; + RECT 38.945 118.025 39.145 118.755 ; + RECT 39.445 118.025 39.645 118.755 ; + RECT 39.945 118.025 40.145 118.755 ; + RECT 41.435 0.17 42.205 0.43 ; + RECT 41.435 0.17 41.695 10.48 ; + RECT 41.945 0.17 42.205 10.99 ; + RECT 40.44 118.025 40.64 118.755 ; + RECT 41.26 118.025 41.46 118.755 ; + RECT 42.455 0.17 43.225 0.94 ; + RECT 42.455 0.17 42.715 8.7 ; + RECT 42.965 0.17 43.225 12.9 ; + RECT 41.755 118.025 41.955 118.755 ; + RECT 42.255 118.025 42.455 118.755 ; + RECT 42.755 118.025 42.955 118.755 ; + RECT 43.25 118.025 43.45 118.755 ; + RECT 43.475 0.52 43.735 2.485 ; + RECT 44.07 118.025 44.27 118.755 ; + RECT 44.34 0.52 44.6 14.11 ; + RECT 44.565 118.025 44.765 118.755 ; + RECT 44.85 0.52 45.11 2.335 ; + RECT 45.065 118.025 45.265 118.755 ; + RECT 45.565 118.025 45.765 118.755 ; + RECT 46.06 118.025 46.26 118.755 ; + RECT 48.25 0.52 48.51 5.16 ; + RECT 47.73 4.9 48.51 5.16 ; + RECT 47.73 4.9 47.99 6.64 ; + RECT 46.88 118.025 47.08 118.755 ; + RECT 47.375 118.025 47.575 118.755 ; + RECT 47.875 118.025 48.075 118.755 ; + RECT 48.375 118.025 48.575 118.755 ; + RECT 48.87 118.025 49.07 118.755 ; + RECT 49.615 0.17 50.385 0.94 ; + RECT 49.615 0.17 49.875 12.9 ; + RECT 50.125 0.17 50.385 12.9 ; + RECT 49.105 0.52 49.365 5.815 ; + RECT 49.69 118.025 49.89 118.755 ; + RECT 50.635 0.17 51.405 0.43 ; + RECT 50.635 0.17 50.895 11.5 ; + RECT 51.145 0.17 51.405 11.5 ; + RECT 50.185 118.025 50.385 118.755 ; + RECT 50.685 118.025 50.885 118.755 ; + RECT 51.185 118.025 51.385 118.755 ; + RECT 52.675 0.17 53.445 0.43 ; + RECT 52.675 0.17 52.935 10.48 ; + RECT 53.185 0.17 53.445 10.99 ; + RECT 51.68 118.025 51.88 118.755 ; + RECT 52.5 118.025 52.7 118.755 ; + RECT 53.695 0.17 54.465 0.94 ; + RECT 53.695 0.17 53.955 8.7 ; + RECT 54.205 0.17 54.465 12.9 ; + RECT 52.995 118.025 53.195 118.755 ; + RECT 53.495 118.025 53.695 118.755 ; + RECT 53.995 118.025 54.195 118.755 ; + RECT 54.49 118.025 54.69 118.755 ; + RECT 54.715 0.52 54.975 2.485 ; + RECT 55.31 118.025 55.51 118.755 ; + RECT 55.58 0.52 55.84 14.11 ; + RECT 55.805 118.025 56.005 118.755 ; + RECT 56.09 0.52 56.35 2.335 ; + RECT 56.305 118.025 56.505 118.755 ; + RECT 56.805 118.025 57.005 118.755 ; + RECT 57.3 118.025 57.5 118.755 ; + RECT 59.49 0.52 59.75 5.16 ; + RECT 58.97 4.9 59.75 5.16 ; + RECT 58.97 4.9 59.23 6.64 ; + RECT 58.12 118.025 58.32 118.755 ; + RECT 58.615 118.025 58.815 118.755 ; + RECT 59.115 118.025 59.315 118.755 ; + RECT 59.615 118.025 59.815 118.755 ; + RECT 60.11 118.025 60.31 118.755 ; + RECT 60.855 0.17 61.625 0.94 ; + RECT 60.855 0.17 61.115 12.9 ; + RECT 61.365 0.17 61.625 12.9 ; + RECT 60.345 0.52 60.605 5.815 ; + RECT 60.93 118.025 61.13 118.755 ; + RECT 61.875 0.17 62.645 0.43 ; + RECT 61.875 0.17 62.135 11.5 ; + RECT 62.385 0.17 62.645 11.5 ; + RECT 61.425 118.025 61.625 118.755 ; + RECT 61.925 118.025 62.125 118.755 ; + RECT 62.425 118.025 62.625 118.755 ; + RECT 63.915 0.17 64.685 0.43 ; + RECT 63.915 0.17 64.175 10.48 ; + RECT 64.425 0.17 64.685 10.99 ; + RECT 62.92 118.025 63.12 118.755 ; + RECT 63.74 118.025 63.94 118.755 ; + RECT 64.935 0.17 65.705 0.94 ; + RECT 64.935 0.17 65.195 8.7 ; + RECT 65.445 0.17 65.705 12.9 ; + RECT 64.235 118.025 64.435 118.755 ; + RECT 64.735 118.025 64.935 118.755 ; + RECT 65.235 118.025 65.435 118.755 ; + RECT 65.73 118.025 65.93 118.755 ; + RECT 65.955 0.52 66.215 2.485 ; + RECT 66.55 118.025 66.75 118.755 ; + RECT 66.82 0.52 67.08 14.11 ; + RECT 67.045 118.025 67.245 118.755 ; + RECT 67.33 0.52 67.59 2.335 ; + RECT 67.545 118.025 67.745 118.755 ; + RECT 68.045 118.025 68.245 118.755 ; + RECT 68.54 118.025 68.74 118.755 ; + RECT 70.73 0.52 70.99 5.16 ; + RECT 70.21 4.9 70.99 5.16 ; + RECT 70.21 4.9 70.47 6.64 ; + RECT 69.36 118.025 69.56 118.755 ; + RECT 69.855 118.025 70.055 118.755 ; + RECT 70.355 118.025 70.555 118.755 ; + RECT 70.855 118.025 71.055 118.755 ; + RECT 71.35 118.025 71.55 118.755 ; + RECT 72.095 0.17 72.865 0.94 ; + RECT 72.095 0.17 72.355 12.9 ; + RECT 72.605 0.17 72.865 12.9 ; + RECT 71.585 0.52 71.845 5.815 ; + RECT 72.17 118.025 72.37 118.755 ; + RECT 73.115 0.17 73.885 0.43 ; + RECT 73.115 0.17 73.375 11.5 ; + RECT 73.625 0.17 73.885 11.5 ; + RECT 72.665 118.025 72.865 118.755 ; + RECT 73.165 118.025 73.365 118.755 ; + RECT 73.665 118.025 73.865 118.755 ; + RECT 75.155 0.17 75.925 0.43 ; + RECT 75.155 0.17 75.415 10.48 ; + RECT 75.665 0.17 75.925 10.99 ; + RECT 74.16 118.025 74.36 118.755 ; + RECT 74.98 118.025 75.18 118.755 ; + RECT 76.175 0.17 76.945 0.94 ; + RECT 76.175 0.17 76.435 8.7 ; + RECT 76.685 0.17 76.945 12.9 ; + RECT 75.475 118.025 75.675 118.755 ; + RECT 75.975 118.025 76.175 118.755 ; + RECT 76.475 118.025 76.675 118.755 ; + RECT 76.97 118.025 77.17 118.755 ; + RECT 77.195 0.52 77.455 2.485 ; + RECT 77.79 118.025 77.99 118.755 ; + RECT 78.06 0.52 78.32 14.11 ; + RECT 78.285 118.025 78.485 118.755 ; + RECT 78.57 0.52 78.83 2.335 ; + RECT 78.785 118.025 78.985 118.755 ; + RECT 79.285 118.025 79.485 118.755 ; + RECT 79.78 118.025 79.98 118.755 ; + RECT 81.97 0.52 82.23 5.16 ; + RECT 81.45 4.9 82.23 5.16 ; + RECT 81.45 4.9 81.71 6.64 ; + RECT 80.6 118.025 80.8 118.755 ; + RECT 81.095 118.025 81.295 118.755 ; + RECT 81.595 118.025 81.795 118.755 ; + RECT 82.095 118.025 82.295 118.755 ; + RECT 82.59 118.025 82.79 118.755 ; + RECT 83.335 0.17 84.105 0.94 ; + RECT 83.335 0.17 83.595 12.9 ; + RECT 83.845 0.17 84.105 12.9 ; + RECT 82.825 0.52 83.085 5.815 ; + RECT 83.41 118.025 83.61 118.755 ; + RECT 84.355 0.17 85.125 0.43 ; + RECT 84.355 0.17 84.615 11.5 ; + RECT 84.865 0.17 85.125 11.5 ; + RECT 83.905 118.025 84.105 118.755 ; + RECT 84.405 118.025 84.605 118.755 ; + RECT 84.905 118.025 85.105 118.755 ; + RECT 86.395 0.17 87.165 0.43 ; + RECT 86.395 0.17 86.655 10.48 ; + RECT 86.905 0.17 87.165 10.99 ; + RECT 85.4 118.025 85.6 118.755 ; + RECT 86.22 118.025 86.42 118.755 ; + RECT 87.415 0.17 88.185 0.94 ; + RECT 87.415 0.17 87.675 8.7 ; + RECT 87.925 0.17 88.185 12.9 ; + RECT 86.715 118.025 86.915 118.755 ; + RECT 87.215 118.025 87.415 118.755 ; + RECT 87.715 118.025 87.915 118.755 ; + RECT 88.21 118.025 88.41 118.755 ; + RECT 88.435 0.52 88.695 2.485 ; + RECT 89.03 118.025 89.23 118.755 ; + RECT 89.3 0.52 89.56 14.11 ; + RECT 89.525 118.025 89.725 118.755 ; + RECT 89.81 0.52 90.07 2.335 ; + RECT 90.025 118.025 90.225 118.755 ; + RECT 90.525 118.025 90.725 118.755 ; + RECT 92.515 0.17 93.285 0.43 ; + RECT 92.515 0.17 92.775 8.7 ; + RECT 93.025 0.17 93.285 8.7 ; + RECT 93.535 0.17 94.305 0.94 ; + RECT 93.535 0.17 93.795 8.7 ; + RECT 94.045 0.17 94.305 8.7 ; + RECT 94.555 0.17 95.325 0.43 ; + RECT 94.555 0.17 94.815 8.7 ; + RECT 95.065 0.17 95.325 8.7 ; + RECT 95.575 0.17 96.345 0.94 ; + RECT 95.575 0.17 95.835 8.7 ; + RECT 96.085 0.17 96.345 8.7 ; + RECT 96.595 0.17 97.365 0.43 ; + RECT 96.595 0.17 96.855 8.7 ; + RECT 97.105 0.17 97.365 8.7 ; + RECT 97.615 0.17 98.385 0.94 ; + RECT 97.615 0.17 97.875 8.7 ; + RECT 98.125 0.17 98.385 8.7 ; + RECT 91.02 118.025 91.22 118.755 ; + RECT 91.84 118.025 92.04 118.755 ; + RECT 92.835 118.025 93.035 118.755 ; + RECT 100.32 0.17 101.09 0.94 ; + RECT 100.32 0.17 100.58 8.7 ; + RECT 100.83 0.17 101.09 8.7 ; + RECT 98.79 0.3 99.05 8.7 ; + RECT 99.3 0 99.56 8.7 ; + RECT 99.81 0 100.07 8.7 ; + RECT 101.34 0 101.6 8.7 ; + RECT 101.85 0 102.11 8.7 ; + RECT 102.36 0.52 102.62 8.7 ; + RECT 102.87 0.52 103.13 8.7 ; + RECT 103.38 0.52 103.64 8.7 ; + RECT 105.42 0.17 106.19 0.94 ; + RECT 105.42 0.17 105.68 8.7 ; + RECT 105.93 0.17 106.19 8.7 ; + RECT 106.44 0.17 107.21 0.43 ; + RECT 106.44 0.17 106.7 8.7 ; + RECT 106.95 0.17 107.21 8.7 ; + RECT 103.89 0.52 104.15 8.7 ; + RECT 104.4 0 104.66 8.7 ; + RECT 104.91 0 105.17 8.7 ; + RECT 107.46 0.3 107.72 8.7 ; + RECT 107.97 0.3 108.23 8.7 ; + RECT 110.01 0.17 110.78 0.94 ; + RECT 110.01 0.17 110.27 8.7 ; + RECT 110.52 0.17 110.78 8.7 ; + RECT 108.48 0.3 108.74 8.7 ; + RECT 108.99 0.3 109.25 8.7 ; + RECT 109.5 0.3 109.76 8.7 ; + RECT 111.03 0.52 111.29 8.7 ; + RECT 111.54 0.52 111.8 8.7 ; + RECT 112.05 0.3 112.31 8.7 ; + RECT 112.56 0.52 112.82 8.7 ; + RECT 113.07 0.52 113.33 8.7 ; + RECT 113.58 0.3 113.84 8.7 ; + RECT 114.09 0.52 114.35 8.7 ; + RECT 114.6 0.52 114.86 8.7 ; + RECT 115.11 0.52 115.37 8.7 ; + RECT 115.62 0.52 115.88 8.7 ; + RECT 116.13 0.52 116.39 8.7 ; + RECT 116.64 0.3 116.9 8.7 ; + RECT 117.15 0.52 117.41 8.7 ; + RECT 117.66 0.52 117.92 8.7 ; + RECT 118.17 0.3 118.43 8.7 ; + RECT 120.21 0.17 120.98 0.94 ; + RECT 120.21 0.17 120.47 8.7 ; + RECT 120.72 0.17 120.98 8.7 ; + RECT 118.68 0.52 118.94 8.7 ; + RECT 119.19 0.52 119.45 8.7 ; + RECT 119.7 0.3 119.96 8.7 ; + RECT 121.23 0.52 121.49 8.7 ; + RECT 121.74 0.52 122 8.7 ; + RECT 122.25 0.52 122.51 8.7 ; + RECT 122.76 0.52 123.02 8.7 ; + RECT 123.27 0.52 123.53 8.7 ; + RECT 123.78 0.52 124.04 8.7 ; + RECT 124.29 0.52 124.55 8.7 ; + RECT 126.33 0.17 127.1 0.94 ; + RECT 126.33 0.17 126.59 8.7 ; + RECT 126.84 0.17 127.1 8.7 ; + RECT 124.8 0.52 125.06 8.7 ; + RECT 125.31 0 125.57 8.7 ; + RECT 125.82 0 126.08 8.7 ; + RECT 127.35 0 127.61 8.7 ; + RECT 129.39 0.17 130.16 0.43 ; + RECT 129.39 0.17 129.65 8.7 ; + RECT 129.9 0.17 130.16 8.7 ; + RECT 127.86 0 128.12 8.7 ; + RECT 128.37 0.3 128.63 8.7 ; + RECT 128.88 0.3 129.14 8.7 ; + RECT 130.41 0.3 130.67 8.7 ; + RECT 130.92 0.3 131.18 8.7 ; + RECT 131.43 0.3 131.69 8.7 ; + RECT 131.94 0.3 132.2 8.7 ; + RECT 132.45 0 132.71 8.7 ; + RECT 132.96 0 133.22 8.7 ; + RECT 135 0.17 135.77 0.43 ; + RECT 135 0.17 135.26 8.7 ; + RECT 135.51 0.17 135.77 8.7 ; + RECT 136.02 0.17 136.79 0.94 ; + RECT 136.02 0.17 136.28 25.5 ; + RECT 136.53 0.17 136.79 33.9 ; + RECT 137.04 0.17 137.81 0.43 ; + RECT 137.04 0.17 137.3 8.7 ; + RECT 137.55 0.17 137.81 8.7 ; + RECT 138.415 0.17 139.185 0.94 ; + RECT 138.415 0.17 138.675 8.7 ; + RECT 138.925 0.17 139.185 8.7 ; + RECT 139.435 0.17 140.205 0.43 ; + RECT 139.435 0.17 139.695 8.7 ; + RECT 139.945 0.17 140.205 8.7 ; + RECT 140.455 0.17 141.225 0.94 ; + RECT 140.455 0.17 140.715 8.7 ; + RECT 140.965 0.17 141.225 8.7 ; + RECT 141.475 0.17 142.245 0.43 ; + RECT 141.475 0.17 141.735 8.7 ; + RECT 141.985 0.17 142.245 8.7 ; + RECT 142.495 0.17 143.265 0.94 ; + RECT 142.495 0.17 142.755 8.7 ; + RECT 143.005 0.17 143.265 8.7 ; + RECT 133.47 0.3 133.73 8.7 ; + RECT 143.515 0.17 144.285 0.43 ; + RECT 143.515 0.17 143.775 8.7 ; + RECT 144.025 0.17 144.285 8.7 ; + RECT 133.98 0.3 134.24 8.7 ; + RECT 134.49 0.52 134.75 8.7 ; + RECT 143.765 118.025 143.965 118.755 ; + RECT 144.76 118.025 144.96 118.755 ; + RECT 145.58 118.025 145.78 118.755 ; + RECT 146.075 118.025 146.275 118.755 ; + RECT 146.575 118.025 146.775 118.755 ; + RECT 146.73 0.52 146.99 2.335 ; + RECT 147.075 118.025 147.275 118.755 ; + RECT 147.24 0.52 147.5 14.11 ; + RECT 147.57 118.025 147.77 118.755 ; + RECT 148.615 0.17 149.385 0.94 ; + RECT 149.125 0.17 149.385 8.7 ; + RECT 148.615 0.17 148.875 12.9 ; + RECT 148.105 0.52 148.365 2.485 ; + RECT 148.39 118.025 148.59 118.755 ; + RECT 149.635 0.17 150.405 0.43 ; + RECT 150.145 0.17 150.405 10.48 ; + RECT 149.635 0.17 149.895 10.99 ; + RECT 148.885 118.025 149.085 118.755 ; + RECT 149.385 118.025 149.585 118.755 ; + RECT 149.885 118.025 150.085 118.755 ; + RECT 150.38 118.025 150.58 118.755 ; + RECT 151.675 0.17 152.445 0.43 ; + RECT 151.675 0.17 151.935 11.5 ; + RECT 152.185 0.17 152.445 11.5 ; + RECT 151.2 118.025 151.4 118.755 ; + RECT 151.695 118.025 151.895 118.755 ; + RECT 152.695 0.17 153.465 0.94 ; + RECT 152.695 0.17 152.955 12.9 ; + RECT 153.205 0.17 153.465 12.9 ; + RECT 152.195 118.025 152.395 118.755 ; + RECT 152.695 118.025 152.895 118.755 ; + RECT 153.19 118.025 153.39 118.755 ; + RECT 153.715 0.52 153.975 5.815 ; + RECT 154.57 0.52 154.83 5.16 ; + RECT 154.57 4.9 155.35 5.16 ; + RECT 155.09 4.9 155.35 6.64 ; + RECT 154.01 118.025 154.21 118.755 ; + RECT 154.505 118.025 154.705 118.755 ; + RECT 155.005 118.025 155.205 118.755 ; + RECT 155.505 118.025 155.705 118.755 ; + RECT 156 118.025 156.2 118.755 ; + RECT 156.82 118.025 157.02 118.755 ; + RECT 157.315 118.025 157.515 118.755 ; + RECT 157.815 118.025 158.015 118.755 ; + RECT 157.97 0.52 158.23 2.335 ; + RECT 158.315 118.025 158.515 118.755 ; + RECT 158.48 0.52 158.74 14.11 ; + RECT 158.81 118.025 159.01 118.755 ; + RECT 159.855 0.17 160.625 0.94 ; + RECT 160.365 0.17 160.625 8.7 ; + RECT 159.855 0.17 160.115 12.9 ; + RECT 159.345 0.52 159.605 2.485 ; + RECT 159.63 118.025 159.83 118.755 ; + RECT 160.875 0.17 161.645 0.43 ; + RECT 161.385 0.17 161.645 10.48 ; + RECT 160.875 0.17 161.135 10.99 ; + RECT 160.125 118.025 160.325 118.755 ; + RECT 160.625 118.025 160.825 118.755 ; + RECT 161.125 118.025 161.325 118.755 ; + RECT 161.62 118.025 161.82 118.755 ; + RECT 162.915 0.17 163.685 0.43 ; + RECT 162.915 0.17 163.175 11.5 ; + RECT 163.425 0.17 163.685 11.5 ; + RECT 162.44 118.025 162.64 118.755 ; + RECT 162.935 118.025 163.135 118.755 ; + RECT 163.935 0.17 164.705 0.94 ; + RECT 163.935 0.17 164.195 12.9 ; + RECT 164.445 0.17 164.705 12.9 ; + RECT 163.435 118.025 163.635 118.755 ; + RECT 163.935 118.025 164.135 118.755 ; + RECT 164.43 118.025 164.63 118.755 ; + RECT 164.955 0.52 165.215 5.815 ; + RECT 165.81 0.52 166.07 5.16 ; + RECT 165.81 4.9 166.59 5.16 ; + RECT 166.33 4.9 166.59 6.64 ; + RECT 165.25 118.025 165.45 118.755 ; + RECT 165.745 118.025 165.945 118.755 ; + RECT 166.245 118.025 166.445 118.755 ; + RECT 166.745 118.025 166.945 118.755 ; + RECT 167.24 118.025 167.44 118.755 ; + RECT 168.06 118.025 168.26 118.755 ; + RECT 168.555 118.025 168.755 118.755 ; + RECT 169.055 118.025 169.255 118.755 ; + RECT 169.21 0.52 169.47 2.335 ; + RECT 169.555 118.025 169.755 118.755 ; + RECT 169.72 0.52 169.98 14.11 ; + RECT 170.05 118.025 170.25 118.755 ; + RECT 171.095 0.17 171.865 0.94 ; + RECT 171.605 0.17 171.865 8.7 ; + RECT 171.095 0.17 171.355 12.9 ; + RECT 170.585 0.52 170.845 2.485 ; + RECT 170.87 118.025 171.07 118.755 ; + RECT 172.115 0.17 172.885 0.43 ; + RECT 172.625 0.17 172.885 10.48 ; + RECT 172.115 0.17 172.375 10.99 ; + RECT 171.365 118.025 171.565 118.755 ; + RECT 171.865 118.025 172.065 118.755 ; + RECT 172.365 118.025 172.565 118.755 ; + RECT 172.86 118.025 173.06 118.755 ; + RECT 174.155 0.17 174.925 0.43 ; + RECT 174.155 0.17 174.415 11.5 ; + RECT 174.665 0.17 174.925 11.5 ; + RECT 173.68 118.025 173.88 118.755 ; + RECT 174.175 118.025 174.375 118.755 ; + RECT 175.175 0.17 175.945 0.94 ; + RECT 175.175 0.17 175.435 12.9 ; + RECT 175.685 0.17 175.945 12.9 ; + RECT 174.675 118.025 174.875 118.755 ; + RECT 175.175 118.025 175.375 118.755 ; + RECT 175.67 118.025 175.87 118.755 ; + RECT 176.195 0.52 176.455 5.815 ; + RECT 177.05 0.52 177.31 5.16 ; + RECT 177.05 4.9 177.83 5.16 ; + RECT 177.57 4.9 177.83 6.64 ; + RECT 176.49 118.025 176.69 118.755 ; + RECT 176.985 118.025 177.185 118.755 ; + RECT 177.485 118.025 177.685 118.755 ; + RECT 177.985 118.025 178.185 118.755 ; + RECT 178.48 118.025 178.68 118.755 ; + RECT 179.3 118.025 179.5 118.755 ; + RECT 179.795 118.025 179.995 118.755 ; + RECT 180.295 118.025 180.495 118.755 ; + RECT 180.45 0.52 180.71 2.335 ; + RECT 180.795 118.025 180.995 118.755 ; + RECT 180.96 0.52 181.22 14.11 ; + RECT 181.29 118.025 181.49 118.755 ; + RECT 182.335 0.17 183.105 0.94 ; + RECT 182.845 0.17 183.105 8.7 ; + RECT 182.335 0.17 182.595 12.9 ; + RECT 181.825 0.52 182.085 2.485 ; + RECT 182.11 118.025 182.31 118.755 ; + RECT 183.355 0.17 184.125 0.43 ; + RECT 183.865 0.17 184.125 10.48 ; + RECT 183.355 0.17 183.615 10.99 ; + RECT 182.605 118.025 182.805 118.755 ; + RECT 183.105 118.025 183.305 118.755 ; + RECT 183.605 118.025 183.805 118.755 ; + RECT 184.1 118.025 184.3 118.755 ; + RECT 185.395 0.17 186.165 0.43 ; + RECT 185.395 0.17 185.655 11.5 ; + RECT 185.905 0.17 186.165 11.5 ; + RECT 184.92 118.025 185.12 118.755 ; + RECT 185.415 118.025 185.615 118.755 ; + RECT 186.415 0.17 187.185 0.94 ; + RECT 186.415 0.17 186.675 12.9 ; + RECT 186.925 0.17 187.185 12.9 ; + RECT 185.915 118.025 186.115 118.755 ; + RECT 186.415 118.025 186.615 118.755 ; + RECT 186.91 118.025 187.11 118.755 ; + RECT 187.435 0.52 187.695 5.815 ; + RECT 188.29 0.52 188.55 5.16 ; + RECT 188.29 4.9 189.07 5.16 ; + RECT 188.81 4.9 189.07 6.64 ; + RECT 187.73 118.025 187.93 118.755 ; + RECT 188.225 118.025 188.425 118.755 ; + RECT 188.725 118.025 188.925 118.755 ; + RECT 189.225 118.025 189.425 118.755 ; + RECT 189.72 118.025 189.92 118.755 ; + RECT 190.54 118.025 190.74 118.755 ; + RECT 191.035 118.025 191.235 118.755 ; + RECT 191.535 118.025 191.735 118.755 ; + RECT 191.69 0.52 191.95 2.335 ; + RECT 192.035 118.025 192.235 118.755 ; + RECT 192.2 0.52 192.46 14.11 ; + RECT 192.53 118.025 192.73 118.755 ; + RECT 193.575 0.17 194.345 0.94 ; + RECT 194.085 0.17 194.345 8.7 ; + RECT 193.575 0.17 193.835 12.9 ; + RECT 193.065 0.52 193.325 2.485 ; + RECT 193.35 118.025 193.55 118.755 ; + RECT 194.595 0.17 195.365 0.43 ; + RECT 195.105 0.17 195.365 10.48 ; + RECT 194.595 0.17 194.855 10.99 ; + RECT 193.845 118.025 194.045 118.755 ; + RECT 194.345 118.025 194.545 118.755 ; + RECT 194.845 118.025 195.045 118.755 ; + RECT 195.34 118.025 195.54 118.755 ; + RECT 196.635 0.17 197.405 0.43 ; + RECT 196.635 0.17 196.895 11.5 ; + RECT 197.145 0.17 197.405 11.5 ; + RECT 196.16 118.025 196.36 118.755 ; + RECT 196.655 118.025 196.855 118.755 ; + RECT 197.655 0.17 198.425 0.94 ; + RECT 197.655 0.17 197.915 12.9 ; + RECT 198.165 0.17 198.425 12.9 ; + RECT 197.155 118.025 197.355 118.755 ; + RECT 197.655 118.025 197.855 118.755 ; + RECT 198.15 118.025 198.35 118.755 ; + RECT 198.675 0.52 198.935 5.815 ; + RECT 199.53 0.52 199.79 5.16 ; + RECT 199.53 4.9 200.31 5.16 ; + RECT 200.05 4.9 200.31 6.64 ; + RECT 198.97 118.025 199.17 118.755 ; + RECT 199.465 118.025 199.665 118.755 ; + RECT 199.965 118.025 200.165 118.755 ; + RECT 200.465 118.025 200.665 118.755 ; + RECT 200.96 118.025 201.16 118.755 ; + RECT 201.78 118.025 201.98 118.755 ; + RECT 202.275 118.025 202.475 118.755 ; + RECT 202.775 118.025 202.975 118.755 ; + RECT 202.93 0.52 203.19 2.335 ; + RECT 203.275 118.025 203.475 118.755 ; + RECT 203.44 0.52 203.7 14.11 ; + RECT 203.77 118.025 203.97 118.755 ; + RECT 204.815 0.17 205.585 0.94 ; + RECT 205.325 0.17 205.585 8.7 ; + RECT 204.815 0.17 205.075 12.9 ; + RECT 204.305 0.52 204.565 2.485 ; + RECT 204.59 118.025 204.79 118.755 ; + RECT 205.835 0.17 206.605 0.43 ; + RECT 206.345 0.17 206.605 10.48 ; + RECT 205.835 0.17 206.095 10.99 ; + RECT 205.085 118.025 205.285 118.755 ; + RECT 205.585 118.025 205.785 118.755 ; + RECT 206.085 118.025 206.285 118.755 ; + RECT 206.58 118.025 206.78 118.755 ; + RECT 207.875 0.17 208.645 0.43 ; + RECT 207.875 0.17 208.135 11.5 ; + RECT 208.385 0.17 208.645 11.5 ; + RECT 207.4 118.025 207.6 118.755 ; + RECT 207.895 118.025 208.095 118.755 ; + RECT 208.895 0.17 209.665 0.94 ; + RECT 208.895 0.17 209.155 12.9 ; + RECT 209.405 0.17 209.665 12.9 ; + RECT 208.395 118.025 208.595 118.755 ; + RECT 208.895 118.025 209.095 118.755 ; + RECT 209.39 118.025 209.59 118.755 ; + RECT 209.915 0.52 210.175 5.815 ; + RECT 210.77 0.52 211.03 5.16 ; + RECT 210.77 4.9 211.55 5.16 ; + RECT 211.29 4.9 211.55 6.64 ; + RECT 210.21 118.025 210.41 118.755 ; + RECT 210.705 118.025 210.905 118.755 ; + RECT 211.205 118.025 211.405 118.755 ; + RECT 211.705 118.025 211.905 118.755 ; + RECT 212.2 118.025 212.4 118.755 ; + RECT 213.02 118.025 213.22 118.755 ; + RECT 213.515 118.025 213.715 118.755 ; + RECT 214.015 118.025 214.215 118.755 ; + RECT 214.17 0.52 214.43 2.335 ; + RECT 214.515 118.025 214.715 118.755 ; + RECT 214.68 0.52 214.94 14.11 ; + RECT 215.01 118.025 215.21 118.755 ; + RECT 216.055 0.17 216.825 0.94 ; + RECT 216.565 0.17 216.825 8.7 ; + RECT 216.055 0.17 216.315 12.9 ; + RECT 215.545 0.52 215.805 2.485 ; + RECT 215.83 118.025 216.03 118.755 ; + RECT 217.075 0.17 217.845 0.43 ; + RECT 217.585 0.17 217.845 10.48 ; + RECT 217.075 0.17 217.335 10.99 ; + RECT 216.325 118.025 216.525 118.755 ; + RECT 216.825 118.025 217.025 118.755 ; + RECT 217.325 118.025 217.525 118.755 ; + RECT 217.82 118.025 218.02 118.755 ; + RECT 219.115 0.17 219.885 0.43 ; + RECT 219.115 0.17 219.375 11.5 ; + RECT 219.625 0.17 219.885 11.5 ; + RECT 218.64 118.025 218.84 118.755 ; + RECT 219.135 118.025 219.335 118.755 ; + RECT 220.135 0.17 220.905 0.94 ; + RECT 220.135 0.17 220.395 12.9 ; + RECT 220.645 0.17 220.905 12.9 ; + RECT 219.635 118.025 219.835 118.755 ; + RECT 220.135 118.025 220.335 118.755 ; + RECT 220.63 118.025 220.83 118.755 ; + RECT 221.155 0.52 221.415 5.815 ; + RECT 222.01 0.52 222.27 5.16 ; + RECT 222.01 4.9 222.79 5.16 ; + RECT 222.53 4.9 222.79 6.64 ; + RECT 221.45 118.025 221.65 118.755 ; + RECT 221.945 118.025 222.145 118.755 ; + RECT 222.445 118.025 222.645 118.755 ; + RECT 222.945 118.025 223.145 118.755 ; + RECT 223.44 118.025 223.64 118.755 ; + RECT 224.26 118.025 224.46 118.755 ; + RECT 224.755 118.025 224.955 118.755 ; + RECT 225.255 118.025 225.455 118.755 ; + RECT 225.41 0.52 225.67 2.335 ; + RECT 225.755 118.025 225.955 118.755 ; + RECT 225.92 0.52 226.18 14.11 ; + RECT 226.25 118.025 226.45 118.755 ; + RECT 227.295 0.17 228.065 0.94 ; + RECT 227.805 0.17 228.065 8.7 ; + RECT 227.295 0.17 227.555 12.9 ; + RECT 226.785 0.52 227.045 2.485 ; + RECT 227.07 118.025 227.27 118.755 ; + RECT 228.315 0.17 229.085 0.43 ; + RECT 228.825 0.17 229.085 10.48 ; + RECT 228.315 0.17 228.575 10.99 ; + RECT 227.565 118.025 227.765 118.755 ; + RECT 228.065 118.025 228.265 118.755 ; + RECT 228.565 118.025 228.765 118.755 ; + RECT 229.06 118.025 229.26 118.755 ; + RECT 230.355 0.17 231.125 0.43 ; + RECT 230.355 0.17 230.615 11.5 ; + RECT 230.865 0.17 231.125 11.5 ; + RECT 229.88 118.025 230.08 118.755 ; + RECT 230.375 118.025 230.575 118.755 ; + RECT 231.375 0.17 232.145 0.94 ; + RECT 231.375 0.17 231.635 12.9 ; + RECT 231.885 0.17 232.145 12.9 ; + RECT 230.875 118.025 231.075 118.755 ; + RECT 231.375 118.025 231.575 118.755 ; + RECT 231.87 118.025 232.07 118.755 ; + RECT 232.395 0.52 232.655 5.815 ; + RECT 233.25 0.52 233.51 5.16 ; + RECT 233.25 4.9 234.03 5.16 ; + RECT 233.77 4.9 234.03 6.64 ; + RECT 232.69 118.025 232.89 118.755 ; + RECT 233.185 118.025 233.385 118.755 ; + RECT 233.685 118.025 233.885 118.755 ; + RECT 234.185 118.025 234.385 118.755 ; + RECT 234.68 118.025 234.88 118.755 ; + RECT 235.5 118.025 235.7 118.755 ; + RECT 236.495 45.465 236.695 118.755 ; + LAYER Metal2 SPACING 0.21 ; + RECT 216.065 0 220.895 118.78 ; + RECT 227.305 0 232.135 118.78 ; + RECT 112.06 0 112.3 118.78 ; + RECT 113.59 0 113.83 118.78 ; + RECT 116.65 0 116.89 118.78 ; + RECT 118.18 0 118.42 118.78 ; + RECT 125.31 0 134.23 118.78 ; + RECT 0 0 3.03 118.78 ; + RECT 4.655 0.17 9.505 118.78 ; + RECT 11.65 0 14.27 118.78 ; + RECT 15.895 0.17 20.745 118.78 ; + RECT 22.89 0 25.51 118.78 ; + RECT 27.135 0.17 31.985 118.78 ; + RECT 34.13 0 36.75 118.78 ; + RECT 38.375 0.17 43.225 118.78 ; + RECT 45.37 0 47.99 118.78 ; + RECT 49.615 0.17 54.465 118.78 ; + RECT 56.61 0 59.23 118.78 ; + RECT 60.855 0.17 65.705 118.78 ; + RECT 67.85 0 70.47 118.78 ; + RECT 72.095 0.17 76.945 118.78 ; + RECT 79.09 0 81.71 118.78 ; + RECT 83.335 0.17 88.185 118.78 ; + RECT 90.33 0 102.11 118.78 ; + RECT 104.4 0.17 110.78 118.78 ; + RECT 112.05 0.3 112.31 118.78 ; + RECT 113.58 0.3 113.84 118.78 ; + RECT 116.64 0.3 116.9 118.78 ; + RECT 118.17 0.3 118.43 118.78 ; + RECT 119.71 0.17 120.98 118.78 ; + RECT 119.7 0.3 120.98 118.78 ; + RECT 125.31 0.3 134.24 118.78 ; + RECT 135.01 0 146.47 118.78 ; + RECT 135 0.17 146.47 118.78 ; + RECT 148.615 0.17 153.465 118.78 ; + RECT 155.09 0 157.71 118.78 ; + RECT 159.855 0.17 164.705 118.78 ; + RECT 166.33 0 168.95 118.78 ; + RECT 171.095 0.17 175.945 118.78 ; + RECT 177.57 0 180.19 118.78 ; + RECT 182.335 0.17 187.185 118.78 ; + RECT 188.81 0 191.43 118.78 ; + RECT 193.575 0.17 198.425 118.78 ; + RECT 200.05 0 202.67 118.78 ; + RECT 204.815 0.17 209.665 118.78 ; + RECT 211.29 0 213.91 118.78 ; + RECT 216.055 0.17 220.905 118.78 ; + RECT 222.53 0 225.15 118.78 ; + RECT 227.295 0.17 232.145 118.78 ; + RECT 233.77 0 236.8 118.78 ; + RECT 0 0.52 236.8 118.78 ; + RECT 4.665 0 9.495 118.78 ; + RECT 15.905 0 20.735 118.78 ; + RECT 27.145 0 31.975 118.78 ; + RECT 38.385 0 43.215 118.78 ; + RECT 49.625 0 54.455 118.78 ; + RECT 60.865 0 65.695 118.78 ; + RECT 72.105 0 76.935 118.78 ; + RECT 83.345 0 88.175 118.78 ; + RECT 104.4 0 110.77 118.78 ; + RECT 119.71 0 120.97 118.78 ; + RECT 148.625 0 153.455 118.78 ; + RECT 159.865 0 164.695 118.78 ; + RECT 171.105 0 175.935 118.78 ; + RECT 182.345 0 187.175 118.78 ; + RECT 193.585 0 198.415 118.78 ; + RECT 204.825 0 209.655 118.78 ; + LAYER Metal3 ; + RECT 0 0 236.8 118.78 ; + LAYER Metal4 SPACING 0.21 ; + RECT 0 39.085 9.62 45.205 ; + RECT 0 0 4 118.78 ; + RECT 7.33 0 9.62 118.78 ; + RECT 12.95 39.085 20.86 45.205 ; + RECT 12.95 0 15.24 118.78 ; + RECT 18.57 0 20.86 118.78 ; + RECT 24.19 39.085 32.1 45.205 ; + RECT 24.19 0 26.48 118.78 ; + RECT 29.81 0 32.1 118.78 ; + RECT 35.43 39.085 43.34 45.205 ; + RECT 35.43 0 37.72 118.78 ; + RECT 41.05 0 43.34 118.78 ; + RECT 46.67 39.085 54.58 45.205 ; + RECT 46.67 0 48.96 118.78 ; + RECT 52.29 0 54.58 118.78 ; + RECT 57.91 39.085 65.82 45.205 ; + RECT 57.91 0 60.2 118.78 ; + RECT 63.53 0 65.82 118.78 ; + RECT 69.15 39.085 77.06 45.205 ; + RECT 69.15 0 71.44 118.78 ; + RECT 74.77 0 77.06 118.78 ; + RECT 80.39 39.085 88.3 45.205 ; + RECT 80.39 0 82.68 118.78 ; + RECT 86.01 0 88.3 118.78 ; + RECT 91.63 0 98.71 118.78 ; + RECT 102.04 0 103.86 118.78 ; + RECT 107.19 0 109.01 118.78 ; + RECT 112.34 0 114.16 118.78 ; + RECT 117.49 0 119.31 118.78 ; + RECT 122.64 0 124.46 118.78 ; + RECT 148.5 39.085 156.41 45.205 ; + RECT 148.5 0 150.79 118.78 ; + RECT 154.12 0 156.41 118.78 ; + RECT 159.74 39.085 167.65 45.205 ; + RECT 159.74 0 162.03 118.78 ; + RECT 165.36 0 167.65 118.78 ; + RECT 170.98 39.085 178.89 45.205 ; + RECT 170.98 0 173.27 118.78 ; + RECT 176.6 0 178.89 118.78 ; + RECT 182.22 39.085 190.13 45.205 ; + RECT 182.22 0 184.51 118.78 ; + RECT 187.84 0 190.13 118.78 ; + RECT 193.46 39.085 201.37 45.205 ; + RECT 193.46 0 195.75 118.78 ; + RECT 199.08 0 201.37 118.78 ; + RECT 204.7 39.085 212.61 45.205 ; + RECT 204.7 0 206.99 118.78 ; + RECT 210.32 0 212.61 118.78 ; + RECT 215.94 39.085 223.85 45.205 ; + RECT 215.94 0 218.23 118.78 ; + RECT 221.56 0 223.85 118.78 ; + RECT 227.18 39.085 236.8 45.205 ; + RECT 227.18 0 229.47 118.78 ; + RECT 232.8 0 236.8 118.78 ; + RECT 127.79 0 129.61 118.78 ; + RECT 132.94 0 134.76 118.78 ; + RECT 138.09 0 145.17 118.78 ; + END +END RM_IHPSG13_1P_256x16_c2_bm_bist + +END LIBRARY diff --git a/flow/platforms/ihp-sg13g2/lef/RM_IHPSG13_1P_256x32_c2_bm_bist.lef b/flow/platforms/ihp-sg13g2/lef/RM_IHPSG13_1P_256x32_c2_bm_bist.lef new file mode 100644 index 0000000000..b0eea90d5c --- /dev/null +++ b/flow/platforms/ihp-sg13g2/lef/RM_IHPSG13_1P_256x32_c2_bm_bist.lef @@ -0,0 +1,4252 @@ +# ------------------------------------------------------ +# +# Copyright 2025 IHP PDK Authors +# +# Licensed under the Apache License, Version 2.0 (the "License"); +# you may not use this file except in compliance with the License. +# You may obtain a copy of the License at +# +# https://www.apache.org/licenses/LICENSE-2.0 +# +# Unless required by applicable law or agreed to in writing, software +# distributed under the License is distributed on an "AS IS" BASIS, +# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +# See the License for the specific language governing permissions and +# limitations under the License. +# +# Generated on Thu Aug 21 20:49:12 2025 +# +# ------------------------------------------------------ +VERSION 5.7 ; +BUSBITCHARS "[]" ; +DIVIDERCHAR "/" ; + +MACRO RM_IHPSG13_1P_256x32_c2_bm_bist + CLASS BLOCK ; + ORIGIN 0 0 ; + FOREIGN RM_IHPSG13_1P_256x32_c2_bm_bist 0 0 ; + SIZE 416.64 BY 118.78 ; + SYMMETRY X Y R90 ; + PIN A_DIN[16] + DIRECTION INPUT ; + USE SIGNAL ; + ANTENNAPARTIALMETALAREA 1.794 LAYER Metal2 ; + ANTENNAMODEL OXIDE1 ; + ANTENNAGATEAREA 0.20085 LAYER Metal2 ; + ANTENNAMAXAREACAR 9.838188 LAYER Metal2 ; + PORT + LAYER Metal2 ; + RECT 244.49 0 244.75 0.26 ; + END + END A_DIN[16] + PIN A_DIN[15] + DIRECTION INPUT ; + USE SIGNAL ; + ANTENNAPARTIALMETALAREA 1.794 LAYER Metal2 ; + ANTENNAMODEL OXIDE1 ; + ANTENNAGATEAREA 0.20085 LAYER Metal2 ; + ANTENNAMAXAREACAR 9.838188 LAYER Metal2 ; + PORT + LAYER Metal2 ; + RECT 171.89 0 172.15 0.26 ; + END + END A_DIN[15] + PIN A_BIST_DIN[16] + DIRECTION INPUT ; + USE SIGNAL ; + ANTENNAPARTIALMETALAREA 1.6263 LAYER Metal2 ; + ANTENNAMODEL OXIDE1 ; + ANTENNAGATEAREA 0.20085 LAYER Metal2 ; + ANTENNAMAXAREACAR 9.365945 LAYER Metal2 ; + PORT + LAYER Metal2 ; + RECT 243.635 0 243.895 0.26 ; + END + END A_BIST_DIN[16] + PIN A_BIST_DIN[15] + DIRECTION INPUT ; + USE SIGNAL ; + ANTENNAPARTIALMETALAREA 1.6263 LAYER Metal2 ; + ANTENNAMODEL OXIDE1 ; + ANTENNAGATEAREA 0.20085 LAYER Metal2 ; + ANTENNAMAXAREACAR 9.365945 LAYER Metal2 ; + PORT + LAYER Metal2 ; + RECT 172.745 0 173.005 0.26 ; + END + END A_BIST_DIN[15] + PIN A_BM[16] + DIRECTION INPUT ; + USE SIGNAL ; + ANTENNAPARTIALMETALAREA 0.7215 LAYER Metal2 ; + ANTENNAMODEL OXIDE1 ; + ANTENNAGATEAREA 0.20085 LAYER Metal2 ; + ANTENNAMAXAREACAR 4.498382 LAYER Metal2 ; + PORT + LAYER Metal2 ; + RECT 236.65 0 236.91 0.26 ; + END + END A_BM[16] + PIN A_BM[15] + DIRECTION INPUT ; + USE SIGNAL ; + ANTENNAPARTIALMETALAREA 0.7215 LAYER Metal2 ; + ANTENNAMODEL OXIDE1 ; + ANTENNAGATEAREA 0.20085 LAYER Metal2 ; + ANTENNAMAXAREACAR 4.498382 LAYER Metal2 ; + PORT + LAYER Metal2 ; + RECT 179.73 0 179.99 0.26 ; + END + END A_BM[15] + PIN A_BIST_BM[16] + DIRECTION INPUT ; + USE SIGNAL ; + ANTENNAPARTIALMETALAREA 0.7605 LAYER Metal2 ; + ANTENNAMODEL OXIDE1 ; + ANTENNAGATEAREA 0.20085 LAYER Metal2 ; + ANTENNAMAXAREACAR 5.055265 LAYER Metal2 ; + PORT + LAYER Metal2 ; + RECT 238.025 0 238.285 0.26 ; + END + END A_BIST_BM[16] + PIN A_BIST_BM[15] + DIRECTION INPUT ; + USE SIGNAL ; + ANTENNAPARTIALMETALAREA 0.7605 LAYER Metal2 ; + ANTENNAMODEL OXIDE1 ; + ANTENNAGATEAREA 0.20085 LAYER Metal2 ; + ANTENNAMAXAREACAR 5.055265 LAYER Metal2 ; + PORT + LAYER Metal2 ; + RECT 178.355 0 178.615 0.26 ; + END + END A_BIST_BM[15] + PIN A_DOUT[16] + DIRECTION OUTPUT ; + USE SIGNAL ; + ANTENNAPARTIALMETALAREA 3.7095 LAYER Metal2 ; + ANTENNADIFFAREA 0.988 LAYER Metal2 ; + PORT + LAYER Metal2 ; + RECT 237.16 0 237.42 0.26 ; + END + END A_DOUT[16] + PIN A_DOUT[15] + DIRECTION OUTPUT ; + USE SIGNAL ; + ANTENNAPARTIALMETALAREA 3.7095 LAYER Metal2 ; + ANTENNADIFFAREA 0.988 LAYER Metal2 ; + PORT + LAYER Metal2 ; + RECT 179.22 0 179.48 0.26 ; + END + END A_DOUT[15] + PIN VSS! + DIRECTION INOUT ; + USE GROUND ; + NETEXPR "vss VSS!" ; + PORT + LAYER Metal4 ; + RECT 403.95 0 406.76 118.78 ; + END + PORT + LAYER Metal4 ; + RECT 392.71 0 395.52 118.78 ; + END + PORT + LAYER Metal4 ; + RECT 381.47 0 384.28 118.78 ; + END + PORT + LAYER Metal4 ; + RECT 370.23 0 373.04 118.78 ; + END + PORT + LAYER Metal4 ; + RECT 358.99 0 361.8 118.78 ; + END + PORT + LAYER Metal4 ; + RECT 347.75 0 350.56 118.78 ; + END + PORT + LAYER Metal4 ; + RECT 336.51 0 339.32 118.78 ; + END + PORT + LAYER Metal4 ; + RECT 325.27 0 328.08 118.78 ; + END + PORT + LAYER Metal4 ; + RECT 314.03 0 316.84 118.78 ; + END + PORT + LAYER Metal4 ; + RECT 302.79 0 305.6 118.78 ; + END + PORT + LAYER Metal4 ; + RECT 291.55 0 294.36 118.78 ; + END + PORT + LAYER Metal4 ; + RECT 280.31 0 283.12 118.78 ; + END + PORT + LAYER Metal4 ; + RECT 269.07 0 271.88 118.78 ; + END + PORT + LAYER Metal4 ; + RECT 257.83 0 260.64 118.78 ; + END + PORT + LAYER Metal4 ; + RECT 246.59 0 249.4 118.78 ; + END + PORT + LAYER Metal4 ; + RECT 235.35 0 238.16 118.78 ; + END + PORT + LAYER Metal4 ; + RECT 224.94 0 227.75 118.78 ; + END + PORT + LAYER Metal4 ; + RECT 214.64 0 217.45 118.78 ; + END + PORT + LAYER Metal4 ; + RECT 199.19 0 202 118.78 ; + END + PORT + LAYER Metal4 ; + RECT 188.89 0 191.7 118.78 ; + END + PORT + LAYER Metal4 ; + RECT 178.48 0 181.29 118.78 ; + END + PORT + LAYER Metal4 ; + RECT 167.24 0 170.05 118.78 ; + END + PORT + LAYER Metal4 ; + RECT 156 0 158.81 118.78 ; + END + PORT + LAYER Metal4 ; + RECT 144.76 0 147.57 118.78 ; + END + PORT + LAYER Metal4 ; + RECT 133.52 0 136.33 118.78 ; + END + PORT + LAYER Metal4 ; + RECT 122.28 0 125.09 118.78 ; + END + PORT + LAYER Metal4 ; + RECT 111.04 0 113.85 118.78 ; + END + PORT + LAYER Metal4 ; + RECT 99.8 0 102.61 118.78 ; + END + PORT + LAYER Metal4 ; + RECT 88.56 0 91.37 118.78 ; + END + PORT + LAYER Metal4 ; + RECT 77.32 0 80.13 118.78 ; + END + PORT + LAYER Metal4 ; + RECT 66.08 0 68.89 118.78 ; + END + PORT + LAYER Metal4 ; + RECT 54.84 0 57.65 118.78 ; + END + PORT + LAYER Metal4 ; + RECT 43.6 0 46.41 118.78 ; + END + PORT + LAYER Metal4 ; + RECT 32.36 0 35.17 118.78 ; + END + PORT + LAYER Metal4 ; + RECT 21.12 0 23.93 118.78 ; + END + PORT + LAYER Metal4 ; + RECT 9.88 0 12.69 118.78 ; + END + END VSS! + PIN VDD! + DIRECTION INOUT ; + USE POWER ; + NETEXPR "vdd VDD!" ; + PORT + LAYER Metal4 ; + RECT 409.57 0 412.38 38.825 ; + END + PORT + LAYER Metal4 ; + RECT 398.33 0 401.14 38.825 ; + END + PORT + LAYER Metal4 ; + RECT 387.09 0 389.9 38.825 ; + END + PORT + LAYER Metal4 ; + RECT 375.85 0 378.66 38.825 ; + END + PORT + LAYER Metal4 ; + RECT 364.61 0 367.42 38.825 ; + END + PORT + LAYER Metal4 ; + RECT 353.37 0 356.18 38.825 ; + END + PORT + LAYER Metal4 ; + RECT 342.13 0 344.94 38.825 ; + END + PORT + LAYER Metal4 ; + RECT 330.89 0 333.7 38.825 ; + END + PORT + LAYER Metal4 ; + RECT 319.65 0 322.46 38.825 ; + END + PORT + LAYER Metal4 ; + RECT 308.41 0 311.22 38.825 ; + END + PORT + LAYER Metal4 ; + RECT 297.17 0 299.98 38.825 ; + END + PORT + LAYER Metal4 ; + RECT 285.93 0 288.74 38.825 ; + END + PORT + LAYER Metal4 ; + RECT 274.69 0 277.5 38.825 ; + END + PORT + LAYER Metal4 ; + RECT 263.45 0 266.26 38.825 ; + END + PORT + LAYER Metal4 ; + RECT 252.21 0 255.02 38.825 ; + END + PORT + LAYER Metal4 ; + RECT 240.97 0 243.78 38.825 ; + END + PORT + LAYER Metal4 ; + RECT 219.79 0 222.6 118.78 ; + END + PORT + LAYER Metal4 ; + RECT 209.49 0 212.3 118.78 ; + END + PORT + LAYER Metal4 ; + RECT 204.34 0 207.15 118.78 ; + END + PORT + LAYER Metal4 ; + RECT 194.04 0 196.85 118.78 ; + END + PORT + LAYER Metal4 ; + RECT 172.86 0 175.67 38.825 ; + END + PORT + LAYER Metal4 ; + RECT 161.62 0 164.43 38.825 ; + END + PORT + LAYER Metal4 ; + RECT 150.38 0 153.19 38.825 ; + END + PORT + LAYER Metal4 ; + RECT 139.14 0 141.95 38.825 ; + END + PORT + LAYER Metal4 ; + RECT 127.9 0 130.71 38.825 ; + END + PORT + LAYER Metal4 ; + RECT 116.66 0 119.47 38.825 ; + END + PORT + LAYER Metal4 ; + RECT 105.42 0 108.23 38.825 ; + END + PORT + LAYER Metal4 ; + RECT 94.18 0 96.99 38.825 ; + END + PORT + LAYER Metal4 ; + RECT 82.94 0 85.75 38.825 ; + END + PORT + LAYER Metal4 ; + RECT 71.7 0 74.51 38.825 ; + END + PORT + LAYER Metal4 ; + RECT 60.46 0 63.27 38.825 ; + END + PORT + LAYER Metal4 ; + RECT 49.22 0 52.03 38.825 ; + END + PORT + LAYER Metal4 ; + RECT 37.98 0 40.79 38.825 ; + END + PORT + LAYER Metal4 ; + RECT 26.74 0 29.55 38.825 ; + END + PORT + LAYER Metal4 ; + RECT 15.5 0 18.31 38.825 ; + END + PORT + LAYER Metal4 ; + RECT 4.26 0 7.07 38.825 ; + END + END VDD! + PIN VDDARRAY! + DIRECTION INOUT ; + USE POWER ; + NETEXPR "vddarray VDDARRAY!" ; + PORT + LAYER Metal4 ; + RECT 409.57 45.465 412.38 118.78 ; + END + PORT + LAYER Metal4 ; + RECT 398.33 45.465 401.14 118.78 ; + END + PORT + LAYER Metal4 ; + RECT 387.09 45.465 389.9 118.78 ; + END + PORT + LAYER Metal4 ; + RECT 375.85 45.465 378.66 118.78 ; + END + PORT + LAYER Metal4 ; + RECT 364.61 45.465 367.42 118.78 ; + END + PORT + LAYER Metal4 ; + RECT 353.37 45.465 356.18 118.78 ; + END + PORT + LAYER Metal4 ; + RECT 342.13 45.465 344.94 118.78 ; + END + PORT + LAYER Metal4 ; + RECT 330.89 45.465 333.7 118.78 ; + END + PORT + LAYER Metal4 ; + RECT 319.65 45.465 322.46 118.78 ; + END + PORT + LAYER Metal4 ; + RECT 308.41 45.465 311.22 118.78 ; + END + PORT + LAYER Metal4 ; + RECT 297.17 45.465 299.98 118.78 ; + END + PORT + LAYER Metal4 ; + RECT 285.93 45.465 288.74 118.78 ; + END + PORT + LAYER Metal4 ; + RECT 274.69 45.465 277.5 118.78 ; + END + PORT + LAYER Metal4 ; + RECT 263.45 45.465 266.26 118.78 ; + END + PORT + LAYER Metal4 ; + RECT 252.21 45.465 255.02 118.78 ; + END + PORT + LAYER Metal4 ; + RECT 240.97 45.465 243.78 118.78 ; + END + PORT + LAYER Metal4 ; + RECT 172.86 45.465 175.67 118.78 ; + END + PORT + LAYER Metal4 ; + RECT 161.62 45.465 164.43 118.78 ; + END + PORT + LAYER Metal4 ; + RECT 150.38 45.465 153.19 118.78 ; + END + PORT + LAYER Metal4 ; + RECT 139.14 45.465 141.95 118.78 ; + END + PORT + LAYER Metal4 ; + RECT 127.9 45.465 130.71 118.78 ; + END + PORT + LAYER Metal4 ; + RECT 116.66 45.465 119.47 118.78 ; + END + PORT + LAYER Metal4 ; + RECT 105.42 45.465 108.23 118.78 ; + END + PORT + LAYER Metal4 ; + RECT 94.18 45.465 96.99 118.78 ; + END + PORT + LAYER Metal4 ; + RECT 82.94 45.465 85.75 118.78 ; + END + PORT + LAYER Metal4 ; + RECT 71.7 45.465 74.51 118.78 ; + END + PORT + LAYER Metal4 ; + RECT 60.46 45.465 63.27 118.78 ; + END + PORT + LAYER Metal4 ; + RECT 49.22 45.465 52.03 118.78 ; + END + PORT + LAYER Metal4 ; + RECT 37.98 45.465 40.79 118.78 ; + END + PORT + LAYER Metal4 ; + RECT 26.74 45.465 29.55 118.78 ; + END + PORT + LAYER Metal4 ; + RECT 15.5 45.465 18.31 118.78 ; + END + PORT + LAYER Metal4 ; + RECT 4.26 45.465 7.07 118.78 ; + END + END VDDARRAY! + PIN A_DIN[17] + DIRECTION INPUT ; + USE SIGNAL ; + ANTENNAPARTIALMETALAREA 1.794 LAYER Metal2 ; + ANTENNAMODEL OXIDE1 ; + ANTENNAGATEAREA 0.20085 LAYER Metal2 ; + ANTENNAMAXAREACAR 9.838188 LAYER Metal2 ; + PORT + LAYER Metal2 ; + RECT 255.73 0 255.99 0.26 ; + END + END A_DIN[17] + PIN A_DIN[14] + DIRECTION INPUT ; + USE SIGNAL ; + ANTENNAPARTIALMETALAREA 1.794 LAYER Metal2 ; + ANTENNAMODEL OXIDE1 ; + ANTENNAGATEAREA 0.20085 LAYER Metal2 ; + ANTENNAMAXAREACAR 9.838188 LAYER Metal2 ; + PORT + LAYER Metal2 ; + RECT 160.65 0 160.91 0.26 ; + END + END A_DIN[14] + PIN A_BIST_DIN[17] + DIRECTION INPUT ; + USE SIGNAL ; + ANTENNAPARTIALMETALAREA 1.6263 LAYER Metal2 ; + ANTENNAMODEL OXIDE1 ; + ANTENNAGATEAREA 0.20085 LAYER Metal2 ; + ANTENNAMAXAREACAR 9.365945 LAYER Metal2 ; + PORT + LAYER Metal2 ; + RECT 254.875 0 255.135 0.26 ; + END + END A_BIST_DIN[17] + PIN A_BIST_DIN[14] + DIRECTION INPUT ; + USE SIGNAL ; + ANTENNAPARTIALMETALAREA 1.6263 LAYER Metal2 ; + ANTENNAMODEL OXIDE1 ; + ANTENNAGATEAREA 0.20085 LAYER Metal2 ; + ANTENNAMAXAREACAR 9.365945 LAYER Metal2 ; + PORT + LAYER Metal2 ; + RECT 161.505 0 161.765 0.26 ; + END + END A_BIST_DIN[14] + PIN A_BM[17] + DIRECTION INPUT ; + USE SIGNAL ; + ANTENNAPARTIALMETALAREA 0.7215 LAYER Metal2 ; + ANTENNAMODEL OXIDE1 ; + ANTENNAGATEAREA 0.20085 LAYER Metal2 ; + ANTENNAMAXAREACAR 4.498382 LAYER Metal2 ; + PORT + LAYER Metal2 ; + RECT 247.89 0 248.15 0.26 ; + END + END A_BM[17] + PIN A_BM[14] + DIRECTION INPUT ; + USE SIGNAL ; + ANTENNAPARTIALMETALAREA 0.7215 LAYER Metal2 ; + ANTENNAMODEL OXIDE1 ; + ANTENNAGATEAREA 0.20085 LAYER Metal2 ; + ANTENNAMAXAREACAR 4.498382 LAYER Metal2 ; + PORT + LAYER Metal2 ; + RECT 168.49 0 168.75 0.26 ; + END + END A_BM[14] + PIN A_BIST_BM[17] + DIRECTION INPUT ; + USE SIGNAL ; + ANTENNAPARTIALMETALAREA 0.7605 LAYER Metal2 ; + ANTENNAMODEL OXIDE1 ; + ANTENNAGATEAREA 0.20085 LAYER Metal2 ; + ANTENNAMAXAREACAR 5.055265 LAYER Metal2 ; + PORT + LAYER Metal2 ; + RECT 249.265 0 249.525 0.26 ; + END + END A_BIST_BM[17] + PIN A_BIST_BM[14] + DIRECTION INPUT ; + USE SIGNAL ; + ANTENNAPARTIALMETALAREA 0.7605 LAYER Metal2 ; + ANTENNAMODEL OXIDE1 ; + ANTENNAGATEAREA 0.20085 LAYER Metal2 ; + ANTENNAMAXAREACAR 5.055265 LAYER Metal2 ; + PORT + LAYER Metal2 ; + RECT 167.115 0 167.375 0.26 ; + END + END A_BIST_BM[14] + PIN A_DOUT[17] + DIRECTION OUTPUT ; + USE SIGNAL ; + ANTENNAPARTIALMETALAREA 3.7095 LAYER Metal2 ; + ANTENNADIFFAREA 0.988 LAYER Metal2 ; + PORT + LAYER Metal2 ; + RECT 248.4 0 248.66 0.26 ; + END + END A_DOUT[17] + PIN A_DOUT[14] + DIRECTION OUTPUT ; + USE SIGNAL ; + ANTENNAPARTIALMETALAREA 3.7095 LAYER Metal2 ; + ANTENNADIFFAREA 0.988 LAYER Metal2 ; + PORT + LAYER Metal2 ; + RECT 167.98 0 168.24 0.26 ; + END + END A_DOUT[14] + PIN A_DIN[18] + DIRECTION INPUT ; + USE SIGNAL ; + ANTENNAPARTIALMETALAREA 1.794 LAYER Metal2 ; + ANTENNAMODEL OXIDE1 ; + ANTENNAGATEAREA 0.20085 LAYER Metal2 ; + ANTENNAMAXAREACAR 9.838188 LAYER Metal2 ; + PORT + LAYER Metal2 ; + RECT 266.97 0 267.23 0.26 ; + END + END A_DIN[18] + PIN A_DIN[13] + DIRECTION INPUT ; + USE SIGNAL ; + ANTENNAPARTIALMETALAREA 1.794 LAYER Metal2 ; + ANTENNAMODEL OXIDE1 ; + ANTENNAGATEAREA 0.20085 LAYER Metal2 ; + ANTENNAMAXAREACAR 9.838188 LAYER Metal2 ; + PORT + LAYER Metal2 ; + RECT 149.41 0 149.67 0.26 ; + END + END A_DIN[13] + PIN A_BIST_DIN[18] + DIRECTION INPUT ; + USE SIGNAL ; + ANTENNAPARTIALMETALAREA 1.6263 LAYER Metal2 ; + ANTENNAMODEL OXIDE1 ; + ANTENNAGATEAREA 0.20085 LAYER Metal2 ; + ANTENNAMAXAREACAR 9.365945 LAYER Metal2 ; + PORT + LAYER Metal2 ; + RECT 266.115 0 266.375 0.26 ; + END + END A_BIST_DIN[18] + PIN A_BIST_DIN[13] + DIRECTION INPUT ; + USE SIGNAL ; + ANTENNAPARTIALMETALAREA 1.6263 LAYER Metal2 ; + ANTENNAMODEL OXIDE1 ; + ANTENNAGATEAREA 0.20085 LAYER Metal2 ; + ANTENNAMAXAREACAR 9.365945 LAYER Metal2 ; + PORT + LAYER Metal2 ; + RECT 150.265 0 150.525 0.26 ; + END + END A_BIST_DIN[13] + PIN A_BM[18] + DIRECTION INPUT ; + USE SIGNAL ; + ANTENNAPARTIALMETALAREA 0.7215 LAYER Metal2 ; + ANTENNAMODEL OXIDE1 ; + ANTENNAGATEAREA 0.20085 LAYER Metal2 ; + ANTENNAMAXAREACAR 4.498382 LAYER Metal2 ; + PORT + LAYER Metal2 ; + RECT 259.13 0 259.39 0.26 ; + END + END A_BM[18] + PIN A_BM[13] + DIRECTION INPUT ; + USE SIGNAL ; + ANTENNAPARTIALMETALAREA 0.7215 LAYER Metal2 ; + ANTENNAMODEL OXIDE1 ; + ANTENNAGATEAREA 0.20085 LAYER Metal2 ; + ANTENNAMAXAREACAR 4.498382 LAYER Metal2 ; + PORT + LAYER Metal2 ; + RECT 157.25 0 157.51 0.26 ; + END + END A_BM[13] + PIN A_BIST_BM[18] + DIRECTION INPUT ; + USE SIGNAL ; + ANTENNAPARTIALMETALAREA 0.7605 LAYER Metal2 ; + ANTENNAMODEL OXIDE1 ; + ANTENNAGATEAREA 0.20085 LAYER Metal2 ; + ANTENNAMAXAREACAR 5.055265 LAYER Metal2 ; + PORT + LAYER Metal2 ; + RECT 260.505 0 260.765 0.26 ; + END + END A_BIST_BM[18] + PIN A_BIST_BM[13] + DIRECTION INPUT ; + USE SIGNAL ; + ANTENNAPARTIALMETALAREA 0.7605 LAYER Metal2 ; + ANTENNAMODEL OXIDE1 ; + ANTENNAGATEAREA 0.20085 LAYER Metal2 ; + ANTENNAMAXAREACAR 5.055265 LAYER Metal2 ; + PORT + LAYER Metal2 ; + RECT 155.875 0 156.135 0.26 ; + END + END A_BIST_BM[13] + PIN A_DOUT[18] + DIRECTION OUTPUT ; + USE SIGNAL ; + ANTENNAPARTIALMETALAREA 3.7095 LAYER Metal2 ; + ANTENNADIFFAREA 0.988 LAYER Metal2 ; + PORT + LAYER Metal2 ; + RECT 259.64 0 259.9 0.26 ; + END + END A_DOUT[18] + PIN A_DOUT[13] + DIRECTION OUTPUT ; + USE SIGNAL ; + ANTENNAPARTIALMETALAREA 3.7095 LAYER Metal2 ; + ANTENNADIFFAREA 0.988 LAYER Metal2 ; + PORT + LAYER Metal2 ; + RECT 156.74 0 157 0.26 ; + END + END A_DOUT[13] + PIN A_DIN[19] + DIRECTION INPUT ; + USE SIGNAL ; + ANTENNAPARTIALMETALAREA 1.794 LAYER Metal2 ; + ANTENNAMODEL OXIDE1 ; + ANTENNAGATEAREA 0.20085 LAYER Metal2 ; + ANTENNAMAXAREACAR 9.838188 LAYER Metal2 ; + PORT + LAYER Metal2 ; + RECT 278.21 0 278.47 0.26 ; + END + END A_DIN[19] + PIN A_DIN[12] + DIRECTION INPUT ; + USE SIGNAL ; + ANTENNAPARTIALMETALAREA 1.794 LAYER Metal2 ; + ANTENNAMODEL OXIDE1 ; + ANTENNAGATEAREA 0.20085 LAYER Metal2 ; + ANTENNAMAXAREACAR 9.838188 LAYER Metal2 ; + PORT + LAYER Metal2 ; + RECT 138.17 0 138.43 0.26 ; + END + END A_DIN[12] + PIN A_BIST_DIN[19] + DIRECTION INPUT ; + USE SIGNAL ; + ANTENNAPARTIALMETALAREA 1.6263 LAYER Metal2 ; + ANTENNAMODEL OXIDE1 ; + ANTENNAGATEAREA 0.20085 LAYER Metal2 ; + ANTENNAMAXAREACAR 9.365945 LAYER Metal2 ; + PORT + LAYER Metal2 ; + RECT 277.355 0 277.615 0.26 ; + END + END A_BIST_DIN[19] + PIN A_BIST_DIN[12] + DIRECTION INPUT ; + USE SIGNAL ; + ANTENNAPARTIALMETALAREA 1.6263 LAYER Metal2 ; + ANTENNAMODEL OXIDE1 ; + ANTENNAGATEAREA 0.20085 LAYER Metal2 ; + ANTENNAMAXAREACAR 9.365945 LAYER Metal2 ; + PORT + LAYER Metal2 ; + RECT 139.025 0 139.285 0.26 ; + END + END A_BIST_DIN[12] + PIN A_BM[19] + DIRECTION INPUT ; + USE SIGNAL ; + ANTENNAPARTIALMETALAREA 0.7215 LAYER Metal2 ; + ANTENNAMODEL OXIDE1 ; + ANTENNAGATEAREA 0.20085 LAYER Metal2 ; + ANTENNAMAXAREACAR 4.498382 LAYER Metal2 ; + PORT + LAYER Metal2 ; + RECT 270.37 0 270.63 0.26 ; + END + END A_BM[19] + PIN A_BM[12] + DIRECTION INPUT ; + USE SIGNAL ; + ANTENNAPARTIALMETALAREA 0.7215 LAYER Metal2 ; + ANTENNAMODEL OXIDE1 ; + ANTENNAGATEAREA 0.20085 LAYER Metal2 ; + ANTENNAMAXAREACAR 4.498382 LAYER Metal2 ; + PORT + LAYER Metal2 ; + RECT 146.01 0 146.27 0.26 ; + END + END A_BM[12] + PIN A_BIST_BM[19] + DIRECTION INPUT ; + USE SIGNAL ; + ANTENNAPARTIALMETALAREA 0.7605 LAYER Metal2 ; + ANTENNAMODEL OXIDE1 ; + ANTENNAGATEAREA 0.20085 LAYER Metal2 ; + ANTENNAMAXAREACAR 5.055265 LAYER Metal2 ; + PORT + LAYER Metal2 ; + RECT 271.745 0 272.005 0.26 ; + END + END A_BIST_BM[19] + PIN A_BIST_BM[12] + DIRECTION INPUT ; + USE SIGNAL ; + ANTENNAPARTIALMETALAREA 0.7605 LAYER Metal2 ; + ANTENNAMODEL OXIDE1 ; + ANTENNAGATEAREA 0.20085 LAYER Metal2 ; + ANTENNAMAXAREACAR 5.055265 LAYER Metal2 ; + PORT + LAYER Metal2 ; + RECT 144.635 0 144.895 0.26 ; + END + END A_BIST_BM[12] + PIN A_DOUT[19] + DIRECTION OUTPUT ; + USE SIGNAL ; + ANTENNAPARTIALMETALAREA 3.7095 LAYER Metal2 ; + ANTENNADIFFAREA 0.988 LAYER Metal2 ; + PORT + LAYER Metal2 ; + RECT 270.88 0 271.14 0.26 ; + END + END A_DOUT[19] + PIN A_DOUT[12] + DIRECTION OUTPUT ; + USE SIGNAL ; + ANTENNAPARTIALMETALAREA 3.7095 LAYER Metal2 ; + ANTENNADIFFAREA 0.988 LAYER Metal2 ; + PORT + LAYER Metal2 ; + RECT 145.5 0 145.76 0.26 ; + END + END A_DOUT[12] + PIN A_DIN[20] + DIRECTION INPUT ; + USE SIGNAL ; + ANTENNAPARTIALMETALAREA 1.794 LAYER Metal2 ; + ANTENNAMODEL OXIDE1 ; + ANTENNAGATEAREA 0.20085 LAYER Metal2 ; + ANTENNAMAXAREACAR 9.838188 LAYER Metal2 ; + PORT + LAYER Metal2 ; + RECT 289.45 0 289.71 0.26 ; + END + END A_DIN[20] + PIN A_DIN[11] + DIRECTION INPUT ; + USE SIGNAL ; + ANTENNAPARTIALMETALAREA 1.794 LAYER Metal2 ; + ANTENNAMODEL OXIDE1 ; + ANTENNAGATEAREA 0.20085 LAYER Metal2 ; + ANTENNAMAXAREACAR 9.838188 LAYER Metal2 ; + PORT + LAYER Metal2 ; + RECT 126.93 0 127.19 0.26 ; + END + END A_DIN[11] + PIN A_BIST_DIN[20] + DIRECTION INPUT ; + USE SIGNAL ; + ANTENNAPARTIALMETALAREA 1.6263 LAYER Metal2 ; + ANTENNAMODEL OXIDE1 ; + ANTENNAGATEAREA 0.20085 LAYER Metal2 ; + ANTENNAMAXAREACAR 9.365945 LAYER Metal2 ; + PORT + LAYER Metal2 ; + RECT 288.595 0 288.855 0.26 ; + END + END A_BIST_DIN[20] + PIN A_BIST_DIN[11] + DIRECTION INPUT ; + USE SIGNAL ; + ANTENNAPARTIALMETALAREA 1.6263 LAYER Metal2 ; + ANTENNAMODEL OXIDE1 ; + ANTENNAGATEAREA 0.20085 LAYER Metal2 ; + ANTENNAMAXAREACAR 9.365945 LAYER Metal2 ; + PORT + LAYER Metal2 ; + RECT 127.785 0 128.045 0.26 ; + END + END A_BIST_DIN[11] + PIN A_BM[20] + DIRECTION INPUT ; + USE SIGNAL ; + ANTENNAPARTIALMETALAREA 0.7215 LAYER Metal2 ; + ANTENNAMODEL OXIDE1 ; + ANTENNAGATEAREA 0.20085 LAYER Metal2 ; + ANTENNAMAXAREACAR 4.498382 LAYER Metal2 ; + PORT + LAYER Metal2 ; + RECT 281.61 0 281.87 0.26 ; + END + END A_BM[20] + PIN A_BM[11] + DIRECTION INPUT ; + USE SIGNAL ; + ANTENNAPARTIALMETALAREA 0.7215 LAYER Metal2 ; + ANTENNAMODEL OXIDE1 ; + ANTENNAGATEAREA 0.20085 LAYER Metal2 ; + ANTENNAMAXAREACAR 4.498382 LAYER Metal2 ; + PORT + LAYER Metal2 ; + RECT 134.77 0 135.03 0.26 ; + END + END A_BM[11] + PIN A_BIST_BM[20] + DIRECTION INPUT ; + USE SIGNAL ; + ANTENNAPARTIALMETALAREA 0.7605 LAYER Metal2 ; + ANTENNAMODEL OXIDE1 ; + ANTENNAGATEAREA 0.20085 LAYER Metal2 ; + ANTENNAMAXAREACAR 5.055265 LAYER Metal2 ; + PORT + LAYER Metal2 ; + RECT 282.985 0 283.245 0.26 ; + END + END A_BIST_BM[20] + PIN A_BIST_BM[11] + DIRECTION INPUT ; + USE SIGNAL ; + ANTENNAPARTIALMETALAREA 0.7605 LAYER Metal2 ; + ANTENNAMODEL OXIDE1 ; + ANTENNAGATEAREA 0.20085 LAYER Metal2 ; + ANTENNAMAXAREACAR 5.055265 LAYER Metal2 ; + PORT + LAYER Metal2 ; + RECT 133.395 0 133.655 0.26 ; + END + END A_BIST_BM[11] + PIN A_DOUT[20] + DIRECTION OUTPUT ; + USE SIGNAL ; + ANTENNAPARTIALMETALAREA 3.7095 LAYER Metal2 ; + ANTENNADIFFAREA 0.988 LAYER Metal2 ; + PORT + LAYER Metal2 ; + RECT 282.12 0 282.38 0.26 ; + END + END A_DOUT[20] + PIN A_DOUT[11] + DIRECTION OUTPUT ; + USE SIGNAL ; + ANTENNAPARTIALMETALAREA 3.7095 LAYER Metal2 ; + ANTENNADIFFAREA 0.988 LAYER Metal2 ; + PORT + LAYER Metal2 ; + RECT 134.26 0 134.52 0.26 ; + END + END A_DOUT[11] + PIN A_DIN[21] + DIRECTION INPUT ; + USE SIGNAL ; + ANTENNAPARTIALMETALAREA 1.794 LAYER Metal2 ; + ANTENNAMODEL OXIDE1 ; + ANTENNAGATEAREA 0.20085 LAYER Metal2 ; + ANTENNAMAXAREACAR 9.838188 LAYER Metal2 ; + PORT + LAYER Metal2 ; + RECT 300.69 0 300.95 0.26 ; + END + END A_DIN[21] + PIN A_DIN[10] + DIRECTION INPUT ; + USE SIGNAL ; + ANTENNAPARTIALMETALAREA 1.794 LAYER Metal2 ; + ANTENNAMODEL OXIDE1 ; + ANTENNAGATEAREA 0.20085 LAYER Metal2 ; + ANTENNAMAXAREACAR 9.838188 LAYER Metal2 ; + PORT + LAYER Metal2 ; + RECT 115.69 0 115.95 0.26 ; + END + END A_DIN[10] + PIN A_BIST_DIN[21] + DIRECTION INPUT ; + USE SIGNAL ; + ANTENNAPARTIALMETALAREA 1.6263 LAYER Metal2 ; + ANTENNAMODEL OXIDE1 ; + ANTENNAGATEAREA 0.20085 LAYER Metal2 ; + ANTENNAMAXAREACAR 9.365945 LAYER Metal2 ; + PORT + LAYER Metal2 ; + RECT 299.835 0 300.095 0.26 ; + END + END A_BIST_DIN[21] + PIN A_BIST_DIN[10] + DIRECTION INPUT ; + USE SIGNAL ; + ANTENNAPARTIALMETALAREA 1.6263 LAYER Metal2 ; + ANTENNAMODEL OXIDE1 ; + ANTENNAGATEAREA 0.20085 LAYER Metal2 ; + ANTENNAMAXAREACAR 9.365945 LAYER Metal2 ; + PORT + LAYER Metal2 ; + RECT 116.545 0 116.805 0.26 ; + END + END A_BIST_DIN[10] + PIN A_BM[21] + DIRECTION INPUT ; + USE SIGNAL ; + ANTENNAPARTIALMETALAREA 0.7215 LAYER Metal2 ; + ANTENNAMODEL OXIDE1 ; + ANTENNAGATEAREA 0.20085 LAYER Metal2 ; + ANTENNAMAXAREACAR 4.498382 LAYER Metal2 ; + PORT + LAYER Metal2 ; + RECT 292.85 0 293.11 0.26 ; + END + END A_BM[21] + PIN A_BM[10] + DIRECTION INPUT ; + USE SIGNAL ; + ANTENNAPARTIALMETALAREA 0.7215 LAYER Metal2 ; + ANTENNAMODEL OXIDE1 ; + ANTENNAGATEAREA 0.20085 LAYER Metal2 ; + ANTENNAMAXAREACAR 4.498382 LAYER Metal2 ; + PORT + LAYER Metal2 ; + RECT 123.53 0 123.79 0.26 ; + END + END A_BM[10] + PIN A_BIST_BM[21] + DIRECTION INPUT ; + USE SIGNAL ; + ANTENNAPARTIALMETALAREA 0.7605 LAYER Metal2 ; + ANTENNAMODEL OXIDE1 ; + ANTENNAGATEAREA 0.20085 LAYER Metal2 ; + ANTENNAMAXAREACAR 5.055265 LAYER Metal2 ; + PORT + LAYER Metal2 ; + RECT 294.225 0 294.485 0.26 ; + END + END A_BIST_BM[21] + PIN A_BIST_BM[10] + DIRECTION INPUT ; + USE SIGNAL ; + ANTENNAPARTIALMETALAREA 0.7605 LAYER Metal2 ; + ANTENNAMODEL OXIDE1 ; + ANTENNAGATEAREA 0.20085 LAYER Metal2 ; + ANTENNAMAXAREACAR 5.055265 LAYER Metal2 ; + PORT + LAYER Metal2 ; + RECT 122.155 0 122.415 0.26 ; + END + END A_BIST_BM[10] + PIN A_DOUT[21] + DIRECTION OUTPUT ; + USE SIGNAL ; + ANTENNAPARTIALMETALAREA 3.7095 LAYER Metal2 ; + ANTENNADIFFAREA 0.988 LAYER Metal2 ; + PORT + LAYER Metal2 ; + RECT 293.36 0 293.62 0.26 ; + END + END A_DOUT[21] + PIN A_DOUT[10] + DIRECTION OUTPUT ; + USE SIGNAL ; + ANTENNAPARTIALMETALAREA 3.7095 LAYER Metal2 ; + ANTENNADIFFAREA 0.988 LAYER Metal2 ; + PORT + LAYER Metal2 ; + RECT 123.02 0 123.28 0.26 ; + END + END A_DOUT[10] + PIN A_DIN[22] + DIRECTION INPUT ; + USE SIGNAL ; + ANTENNAPARTIALMETALAREA 1.794 LAYER Metal2 ; + ANTENNAMODEL OXIDE1 ; + ANTENNAGATEAREA 0.20085 LAYER Metal2 ; + ANTENNAMAXAREACAR 9.838188 LAYER Metal2 ; + PORT + LAYER Metal2 ; + RECT 311.93 0 312.19 0.26 ; + END + END A_DIN[22] + PIN A_DIN[9] + DIRECTION INPUT ; + USE SIGNAL ; + ANTENNAPARTIALMETALAREA 1.794 LAYER Metal2 ; + ANTENNAMODEL OXIDE1 ; + ANTENNAGATEAREA 0.20085 LAYER Metal2 ; + ANTENNAMAXAREACAR 9.838188 LAYER Metal2 ; + PORT + LAYER Metal2 ; + RECT 104.45 0 104.71 0.26 ; + END + END A_DIN[9] + PIN A_BIST_DIN[22] + DIRECTION INPUT ; + USE SIGNAL ; + ANTENNAPARTIALMETALAREA 1.6263 LAYER Metal2 ; + ANTENNAMODEL OXIDE1 ; + ANTENNAGATEAREA 0.20085 LAYER Metal2 ; + ANTENNAMAXAREACAR 9.365945 LAYER Metal2 ; + PORT + LAYER Metal2 ; + RECT 311.075 0 311.335 0.26 ; + END + END A_BIST_DIN[22] + PIN A_BIST_DIN[9] + DIRECTION INPUT ; + USE SIGNAL ; + ANTENNAPARTIALMETALAREA 1.6263 LAYER Metal2 ; + ANTENNAMODEL OXIDE1 ; + ANTENNAGATEAREA 0.20085 LAYER Metal2 ; + ANTENNAMAXAREACAR 9.365945 LAYER Metal2 ; + PORT + LAYER Metal2 ; + RECT 105.305 0 105.565 0.26 ; + END + END A_BIST_DIN[9] + PIN A_BM[22] + DIRECTION INPUT ; + USE SIGNAL ; + ANTENNAPARTIALMETALAREA 0.7215 LAYER Metal2 ; + ANTENNAMODEL OXIDE1 ; + ANTENNAGATEAREA 0.20085 LAYER Metal2 ; + ANTENNAMAXAREACAR 4.498382 LAYER Metal2 ; + PORT + LAYER Metal2 ; + RECT 304.09 0 304.35 0.26 ; + END + END A_BM[22] + PIN A_BM[9] + DIRECTION INPUT ; + USE SIGNAL ; + ANTENNAPARTIALMETALAREA 0.7215 LAYER Metal2 ; + ANTENNAMODEL OXIDE1 ; + ANTENNAGATEAREA 0.20085 LAYER Metal2 ; + ANTENNAMAXAREACAR 4.498382 LAYER Metal2 ; + PORT + LAYER Metal2 ; + RECT 112.29 0 112.55 0.26 ; + END + END A_BM[9] + PIN A_BIST_BM[22] + DIRECTION INPUT ; + USE SIGNAL ; + ANTENNAPARTIALMETALAREA 0.7605 LAYER Metal2 ; + ANTENNAMODEL OXIDE1 ; + ANTENNAGATEAREA 0.20085 LAYER Metal2 ; + ANTENNAMAXAREACAR 5.055265 LAYER Metal2 ; + PORT + LAYER Metal2 ; + RECT 305.465 0 305.725 0.26 ; + END + END A_BIST_BM[22] + PIN A_BIST_BM[9] + DIRECTION INPUT ; + USE SIGNAL ; + ANTENNAPARTIALMETALAREA 0.7605 LAYER Metal2 ; + ANTENNAMODEL OXIDE1 ; + ANTENNAGATEAREA 0.20085 LAYER Metal2 ; + ANTENNAMAXAREACAR 5.055265 LAYER Metal2 ; + PORT + LAYER Metal2 ; + RECT 110.915 0 111.175 0.26 ; + END + END A_BIST_BM[9] + PIN A_DOUT[22] + DIRECTION OUTPUT ; + USE SIGNAL ; + ANTENNAPARTIALMETALAREA 3.7095 LAYER Metal2 ; + ANTENNADIFFAREA 0.988 LAYER Metal2 ; + PORT + LAYER Metal2 ; + RECT 304.6 0 304.86 0.26 ; + END + END A_DOUT[22] + PIN A_DOUT[9] + DIRECTION OUTPUT ; + USE SIGNAL ; + ANTENNAPARTIALMETALAREA 3.7095 LAYER Metal2 ; + ANTENNADIFFAREA 0.988 LAYER Metal2 ; + PORT + LAYER Metal2 ; + RECT 111.78 0 112.04 0.26 ; + END + END A_DOUT[9] + PIN A_DIN[23] + DIRECTION INPUT ; + USE SIGNAL ; + ANTENNAPARTIALMETALAREA 1.794 LAYER Metal2 ; + ANTENNAMODEL OXIDE1 ; + ANTENNAGATEAREA 0.20085 LAYER Metal2 ; + ANTENNAMAXAREACAR 9.838188 LAYER Metal2 ; + PORT + LAYER Metal2 ; + RECT 323.17 0 323.43 0.26 ; + END + END A_DIN[23] + PIN A_DIN[8] + DIRECTION INPUT ; + USE SIGNAL ; + ANTENNAPARTIALMETALAREA 1.794 LAYER Metal2 ; + ANTENNAMODEL OXIDE1 ; + ANTENNAGATEAREA 0.20085 LAYER Metal2 ; + ANTENNAMAXAREACAR 9.838188 LAYER Metal2 ; + PORT + LAYER Metal2 ; + RECT 93.21 0 93.47 0.26 ; + END + END A_DIN[8] + PIN A_BIST_DIN[23] + DIRECTION INPUT ; + USE SIGNAL ; + ANTENNAPARTIALMETALAREA 1.6263 LAYER Metal2 ; + ANTENNAMODEL OXIDE1 ; + ANTENNAGATEAREA 0.20085 LAYER Metal2 ; + ANTENNAMAXAREACAR 9.365945 LAYER Metal2 ; + PORT + LAYER Metal2 ; + RECT 322.315 0 322.575 0.26 ; + END + END A_BIST_DIN[23] + PIN A_BIST_DIN[8] + DIRECTION INPUT ; + USE SIGNAL ; + ANTENNAPARTIALMETALAREA 1.6263 LAYER Metal2 ; + ANTENNAMODEL OXIDE1 ; + ANTENNAGATEAREA 0.20085 LAYER Metal2 ; + ANTENNAMAXAREACAR 9.365945 LAYER Metal2 ; + PORT + LAYER Metal2 ; + RECT 94.065 0 94.325 0.26 ; + END + END A_BIST_DIN[8] + PIN A_BM[23] + DIRECTION INPUT ; + USE SIGNAL ; + ANTENNAPARTIALMETALAREA 0.7215 LAYER Metal2 ; + ANTENNAMODEL OXIDE1 ; + ANTENNAGATEAREA 0.20085 LAYER Metal2 ; + ANTENNAMAXAREACAR 4.498382 LAYER Metal2 ; + PORT + LAYER Metal2 ; + RECT 315.33 0 315.59 0.26 ; + END + END A_BM[23] + PIN A_BM[8] + DIRECTION INPUT ; + USE SIGNAL ; + ANTENNAPARTIALMETALAREA 0.7215 LAYER Metal2 ; + ANTENNAMODEL OXIDE1 ; + ANTENNAGATEAREA 0.20085 LAYER Metal2 ; + ANTENNAMAXAREACAR 4.498382 LAYER Metal2 ; + PORT + LAYER Metal2 ; + RECT 101.05 0 101.31 0.26 ; + END + END A_BM[8] + PIN A_BIST_BM[23] + DIRECTION INPUT ; + USE SIGNAL ; + ANTENNAPARTIALMETALAREA 0.7605 LAYER Metal2 ; + ANTENNAMODEL OXIDE1 ; + ANTENNAGATEAREA 0.20085 LAYER Metal2 ; + ANTENNAMAXAREACAR 5.055265 LAYER Metal2 ; + PORT + LAYER Metal2 ; + RECT 316.705 0 316.965 0.26 ; + END + END A_BIST_BM[23] + PIN A_BIST_BM[8] + DIRECTION INPUT ; + USE SIGNAL ; + ANTENNAPARTIALMETALAREA 0.7605 LAYER Metal2 ; + ANTENNAMODEL OXIDE1 ; + ANTENNAGATEAREA 0.20085 LAYER Metal2 ; + ANTENNAMAXAREACAR 5.055265 LAYER Metal2 ; + PORT + LAYER Metal2 ; + RECT 99.675 0 99.935 0.26 ; + END + END A_BIST_BM[8] + PIN A_DOUT[23] + DIRECTION OUTPUT ; + USE SIGNAL ; + ANTENNAPARTIALMETALAREA 3.7095 LAYER Metal2 ; + ANTENNADIFFAREA 0.988 LAYER Metal2 ; + PORT + LAYER Metal2 ; + RECT 315.84 0 316.1 0.26 ; + END + END A_DOUT[23] + PIN A_DOUT[8] + DIRECTION OUTPUT ; + USE SIGNAL ; + ANTENNAPARTIALMETALAREA 3.7095 LAYER Metal2 ; + ANTENNADIFFAREA 0.988 LAYER Metal2 ; + PORT + LAYER Metal2 ; + RECT 100.54 0 100.8 0.26 ; + END + END A_DOUT[8] + PIN A_DIN[24] + DIRECTION INPUT ; + USE SIGNAL ; + ANTENNAPARTIALMETALAREA 1.794 LAYER Metal2 ; + ANTENNAMODEL OXIDE1 ; + ANTENNAGATEAREA 0.20085 LAYER Metal2 ; + ANTENNAMAXAREACAR 9.838188 LAYER Metal2 ; + PORT + LAYER Metal2 ; + RECT 334.41 0 334.67 0.26 ; + END + END A_DIN[24] + PIN A_DIN[7] + DIRECTION INPUT ; + USE SIGNAL ; + ANTENNAPARTIALMETALAREA 1.794 LAYER Metal2 ; + ANTENNAMODEL OXIDE1 ; + ANTENNAGATEAREA 0.20085 LAYER Metal2 ; + ANTENNAMAXAREACAR 9.838188 LAYER Metal2 ; + PORT + LAYER Metal2 ; + RECT 81.97 0 82.23 0.26 ; + END + END A_DIN[7] + PIN A_BIST_DIN[24] + DIRECTION INPUT ; + USE SIGNAL ; + ANTENNAPARTIALMETALAREA 1.6263 LAYER Metal2 ; + ANTENNAMODEL OXIDE1 ; + ANTENNAGATEAREA 0.20085 LAYER Metal2 ; + ANTENNAMAXAREACAR 9.365945 LAYER Metal2 ; + PORT + LAYER Metal2 ; + RECT 333.555 0 333.815 0.26 ; + END + END A_BIST_DIN[24] + PIN A_BIST_DIN[7] + DIRECTION INPUT ; + USE SIGNAL ; + ANTENNAPARTIALMETALAREA 1.6263 LAYER Metal2 ; + ANTENNAMODEL OXIDE1 ; + ANTENNAGATEAREA 0.20085 LAYER Metal2 ; + ANTENNAMAXAREACAR 9.365945 LAYER Metal2 ; + PORT + LAYER Metal2 ; + RECT 82.825 0 83.085 0.26 ; + END + END A_BIST_DIN[7] + PIN A_BM[24] + DIRECTION INPUT ; + USE SIGNAL ; + ANTENNAPARTIALMETALAREA 0.7215 LAYER Metal2 ; + ANTENNAMODEL OXIDE1 ; + ANTENNAGATEAREA 0.20085 LAYER Metal2 ; + ANTENNAMAXAREACAR 4.498382 LAYER Metal2 ; + PORT + LAYER Metal2 ; + RECT 326.57 0 326.83 0.26 ; + END + END A_BM[24] + PIN A_BM[7] + DIRECTION INPUT ; + USE SIGNAL ; + ANTENNAPARTIALMETALAREA 0.7215 LAYER Metal2 ; + ANTENNAMODEL OXIDE1 ; + ANTENNAGATEAREA 0.20085 LAYER Metal2 ; + ANTENNAMAXAREACAR 4.498382 LAYER Metal2 ; + PORT + LAYER Metal2 ; + RECT 89.81 0 90.07 0.26 ; + END + END A_BM[7] + PIN A_BIST_BM[24] + DIRECTION INPUT ; + USE SIGNAL ; + ANTENNAPARTIALMETALAREA 0.7605 LAYER Metal2 ; + ANTENNAMODEL OXIDE1 ; + ANTENNAGATEAREA 0.20085 LAYER Metal2 ; + ANTENNAMAXAREACAR 5.055265 LAYER Metal2 ; + PORT + LAYER Metal2 ; + RECT 327.945 0 328.205 0.26 ; + END + END A_BIST_BM[24] + PIN A_BIST_BM[7] + DIRECTION INPUT ; + USE SIGNAL ; + ANTENNAPARTIALMETALAREA 0.7605 LAYER Metal2 ; + ANTENNAMODEL OXIDE1 ; + ANTENNAGATEAREA 0.20085 LAYER Metal2 ; + ANTENNAMAXAREACAR 5.055265 LAYER Metal2 ; + PORT + LAYER Metal2 ; + RECT 88.435 0 88.695 0.26 ; + END + END A_BIST_BM[7] + PIN A_DOUT[24] + DIRECTION OUTPUT ; + USE SIGNAL ; + ANTENNAPARTIALMETALAREA 3.7095 LAYER Metal2 ; + ANTENNADIFFAREA 0.988 LAYER Metal2 ; + PORT + LAYER Metal2 ; + RECT 327.08 0 327.34 0.26 ; + END + END A_DOUT[24] + PIN A_DOUT[7] + DIRECTION OUTPUT ; + USE SIGNAL ; + ANTENNAPARTIALMETALAREA 3.7095 LAYER Metal2 ; + ANTENNADIFFAREA 0.988 LAYER Metal2 ; + PORT + LAYER Metal2 ; + RECT 89.3 0 89.56 0.26 ; + END + END A_DOUT[7] + PIN A_DIN[25] + DIRECTION INPUT ; + USE SIGNAL ; + ANTENNAPARTIALMETALAREA 1.794 LAYER Metal2 ; + ANTENNAMODEL OXIDE1 ; + ANTENNAGATEAREA 0.20085 LAYER Metal2 ; + ANTENNAMAXAREACAR 9.838188 LAYER Metal2 ; + PORT + LAYER Metal2 ; + RECT 345.65 0 345.91 0.26 ; + END + END A_DIN[25] + PIN A_DIN[6] + DIRECTION INPUT ; + USE SIGNAL ; + ANTENNAPARTIALMETALAREA 1.794 LAYER Metal2 ; + ANTENNAMODEL OXIDE1 ; + ANTENNAGATEAREA 0.20085 LAYER Metal2 ; + ANTENNAMAXAREACAR 9.838188 LAYER Metal2 ; + PORT + LAYER Metal2 ; + RECT 70.73 0 70.99 0.26 ; + END + END A_DIN[6] + PIN A_BIST_DIN[25] + DIRECTION INPUT ; + USE SIGNAL ; + ANTENNAPARTIALMETALAREA 1.6263 LAYER Metal2 ; + ANTENNAMODEL OXIDE1 ; + ANTENNAGATEAREA 0.20085 LAYER Metal2 ; + ANTENNAMAXAREACAR 9.365945 LAYER Metal2 ; + PORT + LAYER Metal2 ; + RECT 344.795 0 345.055 0.26 ; + END + END A_BIST_DIN[25] + PIN A_BIST_DIN[6] + DIRECTION INPUT ; + USE SIGNAL ; + ANTENNAPARTIALMETALAREA 1.6263 LAYER Metal2 ; + ANTENNAMODEL OXIDE1 ; + ANTENNAGATEAREA 0.20085 LAYER Metal2 ; + ANTENNAMAXAREACAR 9.365945 LAYER Metal2 ; + PORT + LAYER Metal2 ; + RECT 71.585 0 71.845 0.26 ; + END + END A_BIST_DIN[6] + PIN A_BM[25] + DIRECTION INPUT ; + USE SIGNAL ; + ANTENNAPARTIALMETALAREA 0.7215 LAYER Metal2 ; + ANTENNAMODEL OXIDE1 ; + ANTENNAGATEAREA 0.20085 LAYER Metal2 ; + ANTENNAMAXAREACAR 4.498382 LAYER Metal2 ; + PORT + LAYER Metal2 ; + RECT 337.81 0 338.07 0.26 ; + END + END A_BM[25] + PIN A_BM[6] + DIRECTION INPUT ; + USE SIGNAL ; + ANTENNAPARTIALMETALAREA 0.7215 LAYER Metal2 ; + ANTENNAMODEL OXIDE1 ; + ANTENNAGATEAREA 0.20085 LAYER Metal2 ; + ANTENNAMAXAREACAR 4.498382 LAYER Metal2 ; + PORT + LAYER Metal2 ; + RECT 78.57 0 78.83 0.26 ; + END + END A_BM[6] + PIN A_BIST_BM[25] + DIRECTION INPUT ; + USE SIGNAL ; + ANTENNAPARTIALMETALAREA 0.7605 LAYER Metal2 ; + ANTENNAMODEL OXIDE1 ; + ANTENNAGATEAREA 0.20085 LAYER Metal2 ; + ANTENNAMAXAREACAR 5.055265 LAYER Metal2 ; + PORT + LAYER Metal2 ; + RECT 339.185 0 339.445 0.26 ; + END + END A_BIST_BM[25] + PIN A_BIST_BM[6] + DIRECTION INPUT ; + USE SIGNAL ; + ANTENNAPARTIALMETALAREA 0.7605 LAYER Metal2 ; + ANTENNAMODEL OXIDE1 ; + ANTENNAGATEAREA 0.20085 LAYER Metal2 ; + ANTENNAMAXAREACAR 5.055265 LAYER Metal2 ; + PORT + LAYER Metal2 ; + RECT 77.195 0 77.455 0.26 ; + END + END A_BIST_BM[6] + PIN A_DOUT[25] + DIRECTION OUTPUT ; + USE SIGNAL ; + ANTENNAPARTIALMETALAREA 3.7095 LAYER Metal2 ; + ANTENNADIFFAREA 0.988 LAYER Metal2 ; + PORT + LAYER Metal2 ; + RECT 338.32 0 338.58 0.26 ; + END + END A_DOUT[25] + PIN A_DOUT[6] + DIRECTION OUTPUT ; + USE SIGNAL ; + ANTENNAPARTIALMETALAREA 3.7095 LAYER Metal2 ; + ANTENNADIFFAREA 0.988 LAYER Metal2 ; + PORT + LAYER Metal2 ; + RECT 78.06 0 78.32 0.26 ; + END + END A_DOUT[6] + PIN A_DIN[26] + DIRECTION INPUT ; + USE SIGNAL ; + ANTENNAPARTIALMETALAREA 1.794 LAYER Metal2 ; + ANTENNAMODEL OXIDE1 ; + ANTENNAGATEAREA 0.20085 LAYER Metal2 ; + ANTENNAMAXAREACAR 9.838188 LAYER Metal2 ; + PORT + LAYER Metal2 ; + RECT 356.89 0 357.15 0.26 ; + END + END A_DIN[26] + PIN A_DIN[5] + DIRECTION INPUT ; + USE SIGNAL ; + ANTENNAPARTIALMETALAREA 1.794 LAYER Metal2 ; + ANTENNAMODEL OXIDE1 ; + ANTENNAGATEAREA 0.20085 LAYER Metal2 ; + ANTENNAMAXAREACAR 9.838188 LAYER Metal2 ; + PORT + LAYER Metal2 ; + RECT 59.49 0 59.75 0.26 ; + END + END A_DIN[5] + PIN A_BIST_DIN[26] + DIRECTION INPUT ; + USE SIGNAL ; + ANTENNAPARTIALMETALAREA 1.6263 LAYER Metal2 ; + ANTENNAMODEL OXIDE1 ; + ANTENNAGATEAREA 0.20085 LAYER Metal2 ; + ANTENNAMAXAREACAR 9.365945 LAYER Metal2 ; + PORT + LAYER Metal2 ; + RECT 356.035 0 356.295 0.26 ; + END + END A_BIST_DIN[26] + PIN A_BIST_DIN[5] + DIRECTION INPUT ; + USE SIGNAL ; + ANTENNAPARTIALMETALAREA 1.6263 LAYER Metal2 ; + ANTENNAMODEL OXIDE1 ; + ANTENNAGATEAREA 0.20085 LAYER Metal2 ; + ANTENNAMAXAREACAR 9.365945 LAYER Metal2 ; + PORT + LAYER Metal2 ; + RECT 60.345 0 60.605 0.26 ; + END + END A_BIST_DIN[5] + PIN A_BM[26] + DIRECTION INPUT ; + USE SIGNAL ; + ANTENNAPARTIALMETALAREA 0.7215 LAYER Metal2 ; + ANTENNAMODEL OXIDE1 ; + ANTENNAGATEAREA 0.20085 LAYER Metal2 ; + ANTENNAMAXAREACAR 4.498382 LAYER Metal2 ; + PORT + LAYER Metal2 ; + RECT 349.05 0 349.31 0.26 ; + END + END A_BM[26] + PIN A_BM[5] + DIRECTION INPUT ; + USE SIGNAL ; + ANTENNAPARTIALMETALAREA 0.7215 LAYER Metal2 ; + ANTENNAMODEL OXIDE1 ; + ANTENNAGATEAREA 0.20085 LAYER Metal2 ; + ANTENNAMAXAREACAR 4.498382 LAYER Metal2 ; + PORT + LAYER Metal2 ; + RECT 67.33 0 67.59 0.26 ; + END + END A_BM[5] + PIN A_BIST_BM[26] + DIRECTION INPUT ; + USE SIGNAL ; + ANTENNAPARTIALMETALAREA 0.7605 LAYER Metal2 ; + ANTENNAMODEL OXIDE1 ; + ANTENNAGATEAREA 0.20085 LAYER Metal2 ; + ANTENNAMAXAREACAR 5.055265 LAYER Metal2 ; + PORT + LAYER Metal2 ; + RECT 350.425 0 350.685 0.26 ; + END + END A_BIST_BM[26] + PIN A_BIST_BM[5] + DIRECTION INPUT ; + USE SIGNAL ; + ANTENNAPARTIALMETALAREA 0.7605 LAYER Metal2 ; + ANTENNAMODEL OXIDE1 ; + ANTENNAGATEAREA 0.20085 LAYER Metal2 ; + ANTENNAMAXAREACAR 5.055265 LAYER Metal2 ; + PORT + LAYER Metal2 ; + RECT 65.955 0 66.215 0.26 ; + END + END A_BIST_BM[5] + PIN A_DOUT[26] + DIRECTION OUTPUT ; + USE SIGNAL ; + ANTENNAPARTIALMETALAREA 3.7095 LAYER Metal2 ; + ANTENNADIFFAREA 0.988 LAYER Metal2 ; + PORT + LAYER Metal2 ; + RECT 349.56 0 349.82 0.26 ; + END + END A_DOUT[26] + PIN A_DOUT[5] + DIRECTION OUTPUT ; + USE SIGNAL ; + ANTENNAPARTIALMETALAREA 3.7095 LAYER Metal2 ; + ANTENNADIFFAREA 0.988 LAYER Metal2 ; + PORT + LAYER Metal2 ; + RECT 66.82 0 67.08 0.26 ; + END + END A_DOUT[5] + PIN A_DIN[27] + DIRECTION INPUT ; + USE SIGNAL ; + ANTENNAPARTIALMETALAREA 1.794 LAYER Metal2 ; + ANTENNAMODEL OXIDE1 ; + ANTENNAGATEAREA 0.20085 LAYER Metal2 ; + ANTENNAMAXAREACAR 9.838188 LAYER Metal2 ; + PORT + LAYER Metal2 ; + RECT 368.13 0 368.39 0.26 ; + END + END A_DIN[27] + PIN A_DIN[4] + DIRECTION INPUT ; + USE SIGNAL ; + ANTENNAPARTIALMETALAREA 1.794 LAYER Metal2 ; + ANTENNAMODEL OXIDE1 ; + ANTENNAGATEAREA 0.20085 LAYER Metal2 ; + ANTENNAMAXAREACAR 9.838188 LAYER Metal2 ; + PORT + LAYER Metal2 ; + RECT 48.25 0 48.51 0.26 ; + END + END A_DIN[4] + PIN A_BIST_DIN[27] + DIRECTION INPUT ; + USE SIGNAL ; + ANTENNAPARTIALMETALAREA 1.6263 LAYER Metal2 ; + ANTENNAMODEL OXIDE1 ; + ANTENNAGATEAREA 0.20085 LAYER Metal2 ; + ANTENNAMAXAREACAR 9.365945 LAYER Metal2 ; + PORT + LAYER Metal2 ; + RECT 367.275 0 367.535 0.26 ; + END + END A_BIST_DIN[27] + PIN A_BIST_DIN[4] + DIRECTION INPUT ; + USE SIGNAL ; + ANTENNAPARTIALMETALAREA 1.6263 LAYER Metal2 ; + ANTENNAMODEL OXIDE1 ; + ANTENNAGATEAREA 0.20085 LAYER Metal2 ; + ANTENNAMAXAREACAR 9.365945 LAYER Metal2 ; + PORT + LAYER Metal2 ; + RECT 49.105 0 49.365 0.26 ; + END + END A_BIST_DIN[4] + PIN A_BM[27] + DIRECTION INPUT ; + USE SIGNAL ; + ANTENNAPARTIALMETALAREA 0.7215 LAYER Metal2 ; + ANTENNAMODEL OXIDE1 ; + ANTENNAGATEAREA 0.20085 LAYER Metal2 ; + ANTENNAMAXAREACAR 4.498382 LAYER Metal2 ; + PORT + LAYER Metal2 ; + RECT 360.29 0 360.55 0.26 ; + END + END A_BM[27] + PIN A_BM[4] + DIRECTION INPUT ; + USE SIGNAL ; + ANTENNAPARTIALMETALAREA 0.7215 LAYER Metal2 ; + ANTENNAMODEL OXIDE1 ; + ANTENNAGATEAREA 0.20085 LAYER Metal2 ; + ANTENNAMAXAREACAR 4.498382 LAYER Metal2 ; + PORT + LAYER Metal2 ; + RECT 56.09 0 56.35 0.26 ; + END + END A_BM[4] + PIN A_BIST_BM[27] + DIRECTION INPUT ; + USE SIGNAL ; + ANTENNAPARTIALMETALAREA 0.7605 LAYER Metal2 ; + ANTENNAMODEL OXIDE1 ; + ANTENNAGATEAREA 0.20085 LAYER Metal2 ; + ANTENNAMAXAREACAR 5.055265 LAYER Metal2 ; + PORT + LAYER Metal2 ; + RECT 361.665 0 361.925 0.26 ; + END + END A_BIST_BM[27] + PIN A_BIST_BM[4] + DIRECTION INPUT ; + USE SIGNAL ; + ANTENNAPARTIALMETALAREA 0.7605 LAYER Metal2 ; + ANTENNAMODEL OXIDE1 ; + ANTENNAGATEAREA 0.20085 LAYER Metal2 ; + ANTENNAMAXAREACAR 5.055265 LAYER Metal2 ; + PORT + LAYER Metal2 ; + RECT 54.715 0 54.975 0.26 ; + END + END A_BIST_BM[4] + PIN A_DOUT[27] + DIRECTION OUTPUT ; + USE SIGNAL ; + ANTENNAPARTIALMETALAREA 3.7095 LAYER Metal2 ; + ANTENNADIFFAREA 0.988 LAYER Metal2 ; + PORT + LAYER Metal2 ; + RECT 360.8 0 361.06 0.26 ; + END + END A_DOUT[27] + PIN A_DOUT[4] + DIRECTION OUTPUT ; + USE SIGNAL ; + ANTENNAPARTIALMETALAREA 3.7095 LAYER Metal2 ; + ANTENNADIFFAREA 0.988 LAYER Metal2 ; + PORT + LAYER Metal2 ; + RECT 55.58 0 55.84 0.26 ; + END + END A_DOUT[4] + PIN A_DIN[28] + DIRECTION INPUT ; + USE SIGNAL ; + ANTENNAPARTIALMETALAREA 1.794 LAYER Metal2 ; + ANTENNAMODEL OXIDE1 ; + ANTENNAGATEAREA 0.20085 LAYER Metal2 ; + ANTENNAMAXAREACAR 9.838188 LAYER Metal2 ; + PORT + LAYER Metal2 ; + RECT 379.37 0 379.63 0.26 ; + END + END A_DIN[28] + PIN A_DIN[3] + DIRECTION INPUT ; + USE SIGNAL ; + ANTENNAPARTIALMETALAREA 1.794 LAYER Metal2 ; + ANTENNAMODEL OXIDE1 ; + ANTENNAGATEAREA 0.20085 LAYER Metal2 ; + ANTENNAMAXAREACAR 9.838188 LAYER Metal2 ; + PORT + LAYER Metal2 ; + RECT 37.01 0 37.27 0.26 ; + END + END A_DIN[3] + PIN A_BIST_DIN[28] + DIRECTION INPUT ; + USE SIGNAL ; + ANTENNAPARTIALMETALAREA 1.6263 LAYER Metal2 ; + ANTENNAMODEL OXIDE1 ; + ANTENNAGATEAREA 0.20085 LAYER Metal2 ; + ANTENNAMAXAREACAR 9.365945 LAYER Metal2 ; + PORT + LAYER Metal2 ; + RECT 378.515 0 378.775 0.26 ; + END + END A_BIST_DIN[28] + PIN A_BIST_DIN[3] + DIRECTION INPUT ; + USE SIGNAL ; + ANTENNAPARTIALMETALAREA 1.6263 LAYER Metal2 ; + ANTENNAMODEL OXIDE1 ; + ANTENNAGATEAREA 0.20085 LAYER Metal2 ; + ANTENNAMAXAREACAR 9.365945 LAYER Metal2 ; + PORT + LAYER Metal2 ; + RECT 37.865 0 38.125 0.26 ; + END + END A_BIST_DIN[3] + PIN A_BM[28] + DIRECTION INPUT ; + USE SIGNAL ; + ANTENNAPARTIALMETALAREA 0.7215 LAYER Metal2 ; + ANTENNAMODEL OXIDE1 ; + ANTENNAGATEAREA 0.20085 LAYER Metal2 ; + ANTENNAMAXAREACAR 4.498382 LAYER Metal2 ; + PORT + LAYER Metal2 ; + RECT 371.53 0 371.79 0.26 ; + END + END A_BM[28] + PIN A_BM[3] + DIRECTION INPUT ; + USE SIGNAL ; + ANTENNAPARTIALMETALAREA 0.7215 LAYER Metal2 ; + ANTENNAMODEL OXIDE1 ; + ANTENNAGATEAREA 0.20085 LAYER Metal2 ; + ANTENNAMAXAREACAR 4.498382 LAYER Metal2 ; + PORT + LAYER Metal2 ; + RECT 44.85 0 45.11 0.26 ; + END + END A_BM[3] + PIN A_BIST_BM[28] + DIRECTION INPUT ; + USE SIGNAL ; + ANTENNAPARTIALMETALAREA 0.7605 LAYER Metal2 ; + ANTENNAMODEL OXIDE1 ; + ANTENNAGATEAREA 0.20085 LAYER Metal2 ; + ANTENNAMAXAREACAR 5.055265 LAYER Metal2 ; + PORT + LAYER Metal2 ; + RECT 372.905 0 373.165 0.26 ; + END + END A_BIST_BM[28] + PIN A_BIST_BM[3] + DIRECTION INPUT ; + USE SIGNAL ; + ANTENNAPARTIALMETALAREA 0.7605 LAYER Metal2 ; + ANTENNAMODEL OXIDE1 ; + ANTENNAGATEAREA 0.20085 LAYER Metal2 ; + ANTENNAMAXAREACAR 5.055265 LAYER Metal2 ; + PORT + LAYER Metal2 ; + RECT 43.475 0 43.735 0.26 ; + END + END A_BIST_BM[3] + PIN A_DOUT[28] + DIRECTION OUTPUT ; + USE SIGNAL ; + ANTENNAPARTIALMETALAREA 3.7095 LAYER Metal2 ; + ANTENNADIFFAREA 0.988 LAYER Metal2 ; + PORT + LAYER Metal2 ; + RECT 372.04 0 372.3 0.26 ; + END + END A_DOUT[28] + PIN A_DOUT[3] + DIRECTION OUTPUT ; + USE SIGNAL ; + ANTENNAPARTIALMETALAREA 3.7095 LAYER Metal2 ; + ANTENNADIFFAREA 0.988 LAYER Metal2 ; + PORT + LAYER Metal2 ; + RECT 44.34 0 44.6 0.26 ; + END + END A_DOUT[3] + PIN A_DIN[29] + DIRECTION INPUT ; + USE SIGNAL ; + ANTENNAPARTIALMETALAREA 1.794 LAYER Metal2 ; + ANTENNAMODEL OXIDE1 ; + ANTENNAGATEAREA 0.20085 LAYER Metal2 ; + ANTENNAMAXAREACAR 9.838188 LAYER Metal2 ; + PORT + LAYER Metal2 ; + RECT 390.61 0 390.87 0.26 ; + END + END A_DIN[29] + PIN A_DIN[2] + DIRECTION INPUT ; + USE SIGNAL ; + ANTENNAPARTIALMETALAREA 1.794 LAYER Metal2 ; + ANTENNAMODEL OXIDE1 ; + ANTENNAGATEAREA 0.20085 LAYER Metal2 ; + ANTENNAMAXAREACAR 9.838188 LAYER Metal2 ; + PORT + LAYER Metal2 ; + RECT 25.77 0 26.03 0.26 ; + END + END A_DIN[2] + PIN A_BIST_DIN[29] + DIRECTION INPUT ; + USE SIGNAL ; + ANTENNAPARTIALMETALAREA 1.6263 LAYER Metal2 ; + ANTENNAMODEL OXIDE1 ; + ANTENNAGATEAREA 0.20085 LAYER Metal2 ; + ANTENNAMAXAREACAR 9.365945 LAYER Metal2 ; + PORT + LAYER Metal2 ; + RECT 389.755 0 390.015 0.26 ; + END + END A_BIST_DIN[29] + PIN A_BIST_DIN[2] + DIRECTION INPUT ; + USE SIGNAL ; + ANTENNAPARTIALMETALAREA 1.6263 LAYER Metal2 ; + ANTENNAMODEL OXIDE1 ; + ANTENNAGATEAREA 0.20085 LAYER Metal2 ; + ANTENNAMAXAREACAR 9.365945 LAYER Metal2 ; + PORT + LAYER Metal2 ; + RECT 26.625 0 26.885 0.26 ; + END + END A_BIST_DIN[2] + PIN A_BM[29] + DIRECTION INPUT ; + USE SIGNAL ; + ANTENNAPARTIALMETALAREA 0.7215 LAYER Metal2 ; + ANTENNAMODEL OXIDE1 ; + ANTENNAGATEAREA 0.20085 LAYER Metal2 ; + ANTENNAMAXAREACAR 4.498382 LAYER Metal2 ; + PORT + LAYER Metal2 ; + RECT 382.77 0 383.03 0.26 ; + END + END A_BM[29] + PIN A_BM[2] + DIRECTION INPUT ; + USE SIGNAL ; + ANTENNAPARTIALMETALAREA 0.7215 LAYER Metal2 ; + ANTENNAMODEL OXIDE1 ; + ANTENNAGATEAREA 0.20085 LAYER Metal2 ; + ANTENNAMAXAREACAR 4.498382 LAYER Metal2 ; + PORT + LAYER Metal2 ; + RECT 33.61 0 33.87 0.26 ; + END + END A_BM[2] + PIN A_BIST_BM[29] + DIRECTION INPUT ; + USE SIGNAL ; + ANTENNAPARTIALMETALAREA 0.7605 LAYER Metal2 ; + ANTENNAMODEL OXIDE1 ; + ANTENNAGATEAREA 0.20085 LAYER Metal2 ; + ANTENNAMAXAREACAR 5.055265 LAYER Metal2 ; + PORT + LAYER Metal2 ; + RECT 384.145 0 384.405 0.26 ; + END + END A_BIST_BM[29] + PIN A_BIST_BM[2] + DIRECTION INPUT ; + USE SIGNAL ; + ANTENNAPARTIALMETALAREA 0.7605 LAYER Metal2 ; + ANTENNAMODEL OXIDE1 ; + ANTENNAGATEAREA 0.20085 LAYER Metal2 ; + ANTENNAMAXAREACAR 5.055265 LAYER Metal2 ; + PORT + LAYER Metal2 ; + RECT 32.235 0 32.495 0.26 ; + END + END A_BIST_BM[2] + PIN A_DOUT[29] + DIRECTION OUTPUT ; + USE SIGNAL ; + ANTENNAPARTIALMETALAREA 3.7095 LAYER Metal2 ; + ANTENNADIFFAREA 0.988 LAYER Metal2 ; + PORT + LAYER Metal2 ; + RECT 383.28 0 383.54 0.26 ; + END + END A_DOUT[29] + PIN A_DOUT[2] + DIRECTION OUTPUT ; + USE SIGNAL ; + ANTENNAPARTIALMETALAREA 3.7095 LAYER Metal2 ; + ANTENNADIFFAREA 0.988 LAYER Metal2 ; + PORT + LAYER Metal2 ; + RECT 33.1 0 33.36 0.26 ; + END + END A_DOUT[2] + PIN A_DIN[30] + DIRECTION INPUT ; + USE SIGNAL ; + ANTENNAPARTIALMETALAREA 1.794 LAYER Metal2 ; + ANTENNAMODEL OXIDE1 ; + ANTENNAGATEAREA 0.20085 LAYER Metal2 ; + ANTENNAMAXAREACAR 9.838188 LAYER Metal2 ; + PORT + LAYER Metal2 ; + RECT 401.85 0 402.11 0.26 ; + END + END A_DIN[30] + PIN A_DIN[1] + DIRECTION INPUT ; + USE SIGNAL ; + ANTENNAPARTIALMETALAREA 1.794 LAYER Metal2 ; + ANTENNAMODEL OXIDE1 ; + ANTENNAGATEAREA 0.20085 LAYER Metal2 ; + ANTENNAMAXAREACAR 9.838188 LAYER Metal2 ; + PORT + LAYER Metal2 ; + RECT 14.53 0 14.79 0.26 ; + END + END A_DIN[1] + PIN A_BIST_DIN[30] + DIRECTION INPUT ; + USE SIGNAL ; + ANTENNAPARTIALMETALAREA 1.6263 LAYER Metal2 ; + ANTENNAMODEL OXIDE1 ; + ANTENNAGATEAREA 0.20085 LAYER Metal2 ; + ANTENNAMAXAREACAR 9.365945 LAYER Metal2 ; + PORT + LAYER Metal2 ; + RECT 400.995 0 401.255 0.26 ; + END + END A_BIST_DIN[30] + PIN A_BIST_DIN[1] + DIRECTION INPUT ; + USE SIGNAL ; + ANTENNAPARTIALMETALAREA 1.6263 LAYER Metal2 ; + ANTENNAMODEL OXIDE1 ; + ANTENNAGATEAREA 0.20085 LAYER Metal2 ; + ANTENNAMAXAREACAR 9.365945 LAYER Metal2 ; + PORT + LAYER Metal2 ; + RECT 15.385 0 15.645 0.26 ; + END + END A_BIST_DIN[1] + PIN A_BM[30] + DIRECTION INPUT ; + USE SIGNAL ; + ANTENNAPARTIALMETALAREA 0.7215 LAYER Metal2 ; + ANTENNAMODEL OXIDE1 ; + ANTENNAGATEAREA 0.20085 LAYER Metal2 ; + ANTENNAMAXAREACAR 4.498382 LAYER Metal2 ; + PORT + LAYER Metal2 ; + RECT 394.01 0 394.27 0.26 ; + END + END A_BM[30] + PIN A_BM[1] + DIRECTION INPUT ; + USE SIGNAL ; + ANTENNAPARTIALMETALAREA 0.7215 LAYER Metal2 ; + ANTENNAMODEL OXIDE1 ; + ANTENNAGATEAREA 0.20085 LAYER Metal2 ; + ANTENNAMAXAREACAR 4.498382 LAYER Metal2 ; + PORT + LAYER Metal2 ; + RECT 22.37 0 22.63 0.26 ; + END + END A_BM[1] + PIN A_BIST_BM[30] + DIRECTION INPUT ; + USE SIGNAL ; + ANTENNAPARTIALMETALAREA 0.7605 LAYER Metal2 ; + ANTENNAMODEL OXIDE1 ; + ANTENNAGATEAREA 0.20085 LAYER Metal2 ; + ANTENNAMAXAREACAR 5.055265 LAYER Metal2 ; + PORT + LAYER Metal2 ; + RECT 395.385 0 395.645 0.26 ; + END + END A_BIST_BM[30] + PIN A_BIST_BM[1] + DIRECTION INPUT ; + USE SIGNAL ; + ANTENNAPARTIALMETALAREA 0.7605 LAYER Metal2 ; + ANTENNAMODEL OXIDE1 ; + ANTENNAGATEAREA 0.20085 LAYER Metal2 ; + ANTENNAMAXAREACAR 5.055265 LAYER Metal2 ; + PORT + LAYER Metal2 ; + RECT 20.995 0 21.255 0.26 ; + END + END A_BIST_BM[1] + PIN A_DOUT[30] + DIRECTION OUTPUT ; + USE SIGNAL ; + ANTENNAPARTIALMETALAREA 3.7095 LAYER Metal2 ; + ANTENNADIFFAREA 0.988 LAYER Metal2 ; + PORT + LAYER Metal2 ; + RECT 394.52 0 394.78 0.26 ; + END + END A_DOUT[30] + PIN A_DOUT[1] + DIRECTION OUTPUT ; + USE SIGNAL ; + ANTENNAPARTIALMETALAREA 3.7095 LAYER Metal2 ; + ANTENNADIFFAREA 0.988 LAYER Metal2 ; + PORT + LAYER Metal2 ; + RECT 21.86 0 22.12 0.26 ; + END + END A_DOUT[1] + PIN A_DIN[31] + DIRECTION INPUT ; + USE SIGNAL ; + ANTENNAPARTIALMETALAREA 1.794 LAYER Metal2 ; + ANTENNAMODEL OXIDE1 ; + ANTENNAGATEAREA 0.20085 LAYER Metal2 ; + ANTENNAMAXAREACAR 9.838188 LAYER Metal2 ; + PORT + LAYER Metal2 ; + RECT 413.09 0 413.35 0.26 ; + END + END A_DIN[31] + PIN A_DIN[0] + DIRECTION INPUT ; + USE SIGNAL ; + ANTENNAPARTIALMETALAREA 1.794 LAYER Metal2 ; + ANTENNAMODEL OXIDE1 ; + ANTENNAGATEAREA 0.20085 LAYER Metal2 ; + ANTENNAMAXAREACAR 9.838188 LAYER Metal2 ; + PORT + LAYER Metal2 ; + RECT 3.29 0 3.55 0.26 ; + END + END A_DIN[0] + PIN A_BIST_DIN[31] + DIRECTION INPUT ; + USE SIGNAL ; + ANTENNAPARTIALMETALAREA 1.6263 LAYER Metal2 ; + ANTENNAMODEL OXIDE1 ; + ANTENNAGATEAREA 0.20085 LAYER Metal2 ; + ANTENNAMAXAREACAR 9.365945 LAYER Metal2 ; + PORT + LAYER Metal2 ; + RECT 412.235 0 412.495 0.26 ; + END + END A_BIST_DIN[31] + PIN A_BIST_DIN[0] + DIRECTION INPUT ; + USE SIGNAL ; + ANTENNAPARTIALMETALAREA 1.6263 LAYER Metal2 ; + ANTENNAMODEL OXIDE1 ; + ANTENNAGATEAREA 0.20085 LAYER Metal2 ; + ANTENNAMAXAREACAR 9.365945 LAYER Metal2 ; + PORT + LAYER Metal2 ; + RECT 4.145 0 4.405 0.26 ; + END + END A_BIST_DIN[0] + PIN A_BM[31] + DIRECTION INPUT ; + USE SIGNAL ; + ANTENNAPARTIALMETALAREA 0.7215 LAYER Metal2 ; + ANTENNAMODEL OXIDE1 ; + ANTENNAGATEAREA 0.20085 LAYER Metal2 ; + ANTENNAMAXAREACAR 4.498382 LAYER Metal2 ; + PORT + LAYER Metal2 ; + RECT 405.25 0 405.51 0.26 ; + END + END A_BM[31] + PIN A_BM[0] + DIRECTION INPUT ; + USE SIGNAL ; + ANTENNAPARTIALMETALAREA 0.7215 LAYER Metal2 ; + ANTENNAMODEL OXIDE1 ; + ANTENNAGATEAREA 0.20085 LAYER Metal2 ; + ANTENNAMAXAREACAR 4.498382 LAYER Metal2 ; + PORT + LAYER Metal2 ; + RECT 11.13 0 11.39 0.26 ; + END + END A_BM[0] + PIN A_BIST_BM[31] + DIRECTION INPUT ; + USE SIGNAL ; + ANTENNAPARTIALMETALAREA 0.7605 LAYER Metal2 ; + ANTENNAMODEL OXIDE1 ; + ANTENNAGATEAREA 0.20085 LAYER Metal2 ; + ANTENNAMAXAREACAR 5.055265 LAYER Metal2 ; + PORT + LAYER Metal2 ; + RECT 406.625 0 406.885 0.26 ; + END + END A_BIST_BM[31] + PIN A_BIST_BM[0] + DIRECTION INPUT ; + USE SIGNAL ; + ANTENNAPARTIALMETALAREA 0.7605 LAYER Metal2 ; + ANTENNAMODEL OXIDE1 ; + ANTENNAGATEAREA 0.20085 LAYER Metal2 ; + ANTENNAMAXAREACAR 5.055265 LAYER Metal2 ; + PORT + LAYER Metal2 ; + RECT 9.755 0 10.015 0.26 ; + END + END A_BIST_BM[0] + PIN A_DOUT[31] + DIRECTION OUTPUT ; + USE SIGNAL ; + ANTENNAPARTIALMETALAREA 3.7095 LAYER Metal2 ; + ANTENNADIFFAREA 0.988 LAYER Metal2 ; + PORT + LAYER Metal2 ; + RECT 405.76 0 406.02 0.26 ; + END + END A_DOUT[31] + PIN A_DOUT[0] + DIRECTION OUTPUT ; + USE SIGNAL ; + ANTENNAPARTIALMETALAREA 3.7095 LAYER Metal2 ; + ANTENNADIFFAREA 0.988 LAYER Metal2 ; + PORT + LAYER Metal2 ; + RECT 10.62 0 10.88 0.26 ; + END + END A_DOUT[0] + PIN A_ADDR[0] + DIRECTION INPUT ; + USE SIGNAL ; + ANTENNAPARTIALMETALAREA 8.9011 LAYER Metal2 ; + ANTENNAMODEL OXIDE1 ; + ANTENNAGATEAREA 0.20085 LAYER Metal2 ; + ANTENNAMAXAREACAR 45.223301 LAYER Metal2 ; + PORT + LAYER Metal2 ; + RECT 204.52 0 204.78 0.26 ; + END + END A_ADDR[0] + PIN A_BIST_ADDR[0] + DIRECTION INPUT ; + USE SIGNAL ; + ANTENNAPARTIALMETALAREA 9.6967 LAYER Metal2 ; + ANTENNAMODEL OXIDE1 ; + ANTENNAGATEAREA 0.20085 LAYER Metal2 ; + ANTENNAMAXAREACAR 49.184466 LAYER Metal2 ; + PORT + LAYER Metal2 ; + RECT 209.11 0 209.37 0.26 ; + END + END A_BIST_ADDR[0] + PIN A_ADDR[1] + DIRECTION INPUT ; + USE SIGNAL ; + ANTENNAPARTIALMETALAREA 7.774 LAYER Metal2 ; + ANTENNAMODEL OXIDE1 ; + ANTENNAGATEAREA 0.20085 LAYER Metal2 ; + ANTENNAMAXAREACAR 39.656958 LAYER Metal2 ; + PORT + LAYER Metal2 ; + RECT 204.01 0 204.27 0.26 ; + END + END A_ADDR[1] + PIN A_BIST_ADDR[1] + DIRECTION INPUT ; + USE SIGNAL ; + ANTENNAPARTIALMETALAREA 8.5696 LAYER Metal2 ; + ANTENNAMODEL OXIDE1 ; + ANTENNAGATEAREA 0.20085 LAYER Metal2 ; + ANTENNAMAXAREACAR 43.618123 LAYER Metal2 ; + PORT + LAYER Metal2 ; + RECT 208.6 0 208.86 0.26 ; + END + END A_BIST_ADDR[1] + PIN A_ADDR[2] + DIRECTION INPUT ; + USE SIGNAL ; + ANTENNAPARTIALMETALAREA 10.6327 LAYER Metal2 ; + ANTENNAPARTIALMETALAREA 1.5246 LAYER Metal3 ; + ANTENNAPARTIALCUTAREA 0.0722 LAYER Via2 ; + ANTENNAMODEL OXIDE1 ; + ANTENNAGATEAREA 0.20085 LAYER Metal3 ; + ANTENNAMAXAREACAR 9.415982 LAYER Metal3 ; + PORT + LAYER Metal2 ; + RECT 212.17 0 212.43 0.26 ; + END + END A_ADDR[2] + PIN A_BIST_ADDR[2] + DIRECTION INPUT ; + USE SIGNAL ; + ANTENNAPARTIALMETALAREA 10.6327 LAYER Metal2 ; + ANTENNAPARTIALMETALAREA 1.0962 LAYER Metal3 ; + ANTENNAPARTIALCUTAREA 0.0722 LAYER Via2 ; + ANTENNAMODEL OXIDE1 ; + ANTENNAGATEAREA 0.20085 LAYER Metal3 ; + ANTENNAMAXAREACAR 7.813791 LAYER Metal3 ; + PORT + LAYER Metal2 ; + RECT 212.68 0 212.94 0.26 ; + END + END A_BIST_ADDR[2] + PIN A_ADDR[3] + DIRECTION INPUT ; + USE SIGNAL ; + ANTENNAPARTIALMETALAREA 10.6327 LAYER Metal2 ; + ANTENNAPARTIALMETALAREA 3.8367 LAYER Metal3 ; + ANTENNAPARTIALCUTAREA 0.0722 LAYER Via2 ; + ANTENNAMODEL OXIDE1 ; + ANTENNAGATEAREA 0.20085 LAYER Metal3 ; + ANTENNAMAXAREACAR 20.927558 LAYER Metal3 ; + PORT + LAYER Metal2 ; + RECT 211.15 0 211.41 0.26 ; + END + END A_ADDR[3] + PIN A_BIST_ADDR[3] + DIRECTION INPUT ; + USE SIGNAL ; + ANTENNAPARTIALMETALAREA 10.6327 LAYER Metal2 ; + ANTENNAPARTIALMETALAREA 3.5175 LAYER Metal3 ; + ANTENNAPARTIALCUTAREA 0.0722 LAYER Via2 ; + ANTENNAMODEL OXIDE1 ; + ANTENNAGATEAREA 0.20085 LAYER Metal3 ; + ANTENNAMAXAREACAR 19.869057 LAYER Metal3 ; + PORT + LAYER Metal2 ; + RECT 211.66 0 211.92 0.26 ; + END + END A_BIST_ADDR[3] + PIN A_ADDR[4] + DIRECTION INPUT ; + USE SIGNAL ; + ANTENNAPARTIALMETALAREA 12.1979 LAYER Metal2 ; + ANTENNAMODEL OXIDE1 ; + ANTENNAGATEAREA 0.20085 LAYER Metal2 ; + ANTENNAMAXAREACAR 61.63754 LAYER Metal2 ; + PORT + LAYER Metal2 ; + RECT 214.72 0 214.98 0.26 ; + END + END A_ADDR[4] + PIN A_BIST_ADDR[4] + DIRECTION INPUT ; + USE SIGNAL ; + ANTENNAPARTIALMETALAREA 11.9327 LAYER Metal2 ; + ANTENNAMODEL OXIDE1 ; + ANTENNAGATEAREA 0.20085 LAYER Metal2 ; + ANTENNAMAXAREACAR 60.317152 LAYER Metal2 ; + PORT + LAYER Metal2 ; + RECT 214.21 0 214.47 0.26 ; + END + END A_BIST_ADDR[4] + PIN A_ADDR[5] + DIRECTION INPUT ; + USE SIGNAL ; + ANTENNAPARTIALMETALAREA 13.9269 LAYER Metal2 ; + ANTENNAMODEL OXIDE1 ; + ANTENNAGATEAREA 0.20085 LAYER Metal2 ; + ANTENNAMAXAREACAR 70.245955 LAYER Metal2 ; + PORT + LAYER Metal2 ; + RECT 213.7 0 213.96 0.26 ; + END + END A_ADDR[5] + PIN A_BIST_ADDR[5] + DIRECTION INPUT ; + USE SIGNAL ; + ANTENNAPARTIALMETALAREA 13.6617 LAYER Metal2 ; + ANTENNAMODEL OXIDE1 ; + ANTENNAGATEAREA 0.20085 LAYER Metal2 ; + ANTENNAMAXAREACAR 68.925566 LAYER Metal2 ; + PORT + LAYER Metal2 ; + RECT 213.19 0 213.45 0.26 ; + END + END A_BIST_ADDR[5] + PIN A_ADDR[6] + DIRECTION INPUT ; + USE SIGNAL ; + ANTENNAPARTIALMETALAREA 10.9525 LAYER Metal2 ; + ANTENNAMODEL OXIDE1 ; + ANTENNAGATEAREA 0.20085 LAYER Metal2 ; + ANTENNAMAXAREACAR 55.436893 LAYER Metal2 ; + PORT + LAYER Metal2 ; + RECT 192.28 0 192.54 0.26 ; + END + END A_ADDR[6] + PIN A_BIST_ADDR[6] + DIRECTION INPUT ; + USE SIGNAL ; + ANTENNAPARTIALMETALAREA 10.6771 LAYER Metal2 ; + ANTENNAMODEL OXIDE1 ; + ANTENNAGATEAREA 0.20085 LAYER Metal2 ; + ANTENNAMAXAREACAR 54.065721 LAYER Metal2 ; + PORT + LAYER Metal2 ; + RECT 192.79 0 193.05 0.26 ; + END + END A_BIST_ADDR[6] + PIN A_ADDR[7] + DIRECTION INPUT ; + USE SIGNAL ; + ANTENNAPARTIALMETALAREA 12.4163 LAYER Metal2 ; + ANTENNAMODEL OXIDE1 ; + ANTENNAGATEAREA 0.20085 LAYER Metal2 ; + ANTENNAMAXAREACAR 62.724919 LAYER Metal2 ; + PORT + LAYER Metal2 ; + RECT 193.3 0 193.56 0.26 ; + END + END A_ADDR[7] + PIN A_BIST_ADDR[7] + DIRECTION INPUT ; + USE SIGNAL ; + ANTENNAPARTIALMETALAREA 12.1511 LAYER Metal2 ; + ANTENNAMODEL OXIDE1 ; + ANTENNAGATEAREA 0.20085 LAYER Metal2 ; + ANTENNAMAXAREACAR 61.404531 LAYER Metal2 ; + PORT + LAYER Metal2 ; + RECT 193.81 0 194.07 0.26 ; + END + END A_BIST_ADDR[7] + PIN A_CLK + DIRECTION INPUT ; + USE SIGNAL ; + ANTENNAPARTIALMETALAREA 4.0547 LAYER Metal2 ; + ANTENNAMODEL OXIDE1 ; + ANTENNAGATEAREA 0.20085 LAYER Metal2 ; + ANTENNAMAXAREACAR 21.093851 LAYER Metal2 ; + PORT + LAYER Metal2 ; + RECT 202.48 0 202.74 0.26 ; + END + END A_CLK + PIN A_REN + DIRECTION INPUT ; + USE SIGNAL ; + ANTENNAPARTIALMETALAREA 3.99505 LAYER Metal2 ; + ANTENNAMODEL OXIDE1 ; + ANTENNAGATEAREA 0.20085 LAYER Metal2 ; + ANTENNAMAXAREACAR 20.796863 LAYER Metal2 ; + PORT + LAYER Metal2 ; + RECT 206.05 0 206.31 0.26 ; + END + END A_REN + PIN A_WEN + DIRECTION INPUT ; + USE SIGNAL ; + ANTENNAPARTIALMETALAREA 2.8847 LAYER Metal2 ; + ANTENNAMODEL OXIDE1 ; + ANTENNAGATEAREA 0.20085 LAYER Metal2 ; + ANTENNAMAXAREACAR 15.268608 LAYER Metal2 ; + PORT + LAYER Metal2 ; + RECT 205.54 0 205.8 0.26 ; + END + END A_WEN + PIN A_MEN + DIRECTION INPUT ; + USE SIGNAL ; + ANTENNAPARTIALMETALAREA 3.0247 LAYER Metal2 ; + ANTENNAMODEL OXIDE1 ; + ANTENNAGATEAREA 0.20085 LAYER Metal2 ; + ANTENNAMAXAREACAR 15.965646 LAYER Metal2 ; + PORT + LAYER Metal2 ; + RECT 202.99 0 203.25 0.26 ; + END + END A_MEN + PIN A_DLY + DIRECTION INPUT ; + USE SIGNAL ; + ANTENNAPARTIALMETALAREA 6.058 LAYER Metal2 ; + ANTENNAMODEL OXIDE1 ; + ANTENNAGATEAREA 0.3367 LAYER Metal2 ; + ANTENNAMAXAREACAR 18.532819 LAYER Metal2 ; + PORT + LAYER Metal2 ; + RECT 224.41 0 224.67 0.26 ; + END + END A_DLY + PIN A_BIST_EN + DIRECTION INPUT ; + USE SIGNAL ; + ANTENNAPARTIALMETALAREA 3.9871 LAYER Metal2 ; + ANTENNAPARTIALMETALAREA 203.31695 LAYER Metal3 ; + ANTENNAPARTIALCUTAREA 0.0722 LAYER Via2 ; + ANTENNAMODEL OXIDE1 ; + ANTENNAGATEAREA 1.43 LAYER Metal2 ; + ANTENNAGATEAREA 27.17 LAYER Metal3 ; + ANTENNAMAXAREACAR 3.213636 LAYER Metal2 ; + ANTENNAMAXAREACAR 17.755869 LAYER Metal3 ; + ANTENNAMAXCUTCAR 0.151469 LAYER Via2 ; + PORT + LAYER Metal2 ; + RECT 205.03 0 205.29 0.26 ; + END + END A_BIST_EN + PIN A_BIST_CLK + DIRECTION INPUT ; + USE SIGNAL ; + ANTENNAPARTIALMETALAREA 4.1639 LAYER Metal2 ; + ANTENNAMODEL OXIDE1 ; + ANTENNAGATEAREA 0.20085 LAYER Metal2 ; + ANTENNAMAXAREACAR 21.953448 LAYER Metal2 ; + PORT + LAYER Metal2 ; + RECT 200.95 0 201.21 0.26 ; + END + END A_BIST_CLK + PIN A_BIST_REN + DIRECTION INPUT ; + USE SIGNAL ; + ANTENNAPARTIALMETALAREA 4.1119 LAYER Metal2 ; + ANTENNAMODEL OXIDE1 ; + ANTENNAGATEAREA 0.20085 LAYER Metal2 ; + ANTENNAMAXAREACAR 21.694548 LAYER Metal2 ; + PORT + LAYER Metal2 ; + RECT 207.58 0 207.84 0.26 ; + END + END A_BIST_REN + PIN A_BIST_WEN + DIRECTION INPUT ; + USE SIGNAL ; + ANTENNAPARTIALMETALAREA 2.9051 LAYER Metal2 ; + ANTENNAMODEL OXIDE1 ; + ANTENNAGATEAREA 0.20085 LAYER Metal2 ; + ANTENNAMAXAREACAR 15.686084 LAYER Metal2 ; + PORT + LAYER Metal2 ; + RECT 207.07 0 207.33 0.26 ; + END + END A_BIST_WEN + PIN A_BIST_MEN + DIRECTION INPUT ; + USE SIGNAL ; + ANTENNAPARTIALMETALAREA 2.8977 LAYER Metal2 ; + ANTENNAMODEL OXIDE1 ; + ANTENNAGATEAREA 0.20085 LAYER Metal2 ; + ANTENNAMAXAREACAR 15.649241 LAYER Metal2 ; + PORT + LAYER Metal2 ; + RECT 201.46 0 201.72 0.26 ; + END + END A_BIST_MEN + OBS + LAYER Metal1 ; + RECT 0 0 416.64 118.78 ; + LAYER Metal2 ; + RECT 0.105 45.465 0.305 118.755 ; + RECT 1.1 118.025 1.3 118.755 ; + RECT 3.29 0.52 3.55 5.16 ; + RECT 2.77 4.9 3.55 5.16 ; + RECT 2.77 4.9 3.03 6.64 ; + RECT 1.92 118.025 2.12 118.755 ; + RECT 2.415 118.025 2.615 118.755 ; + RECT 2.915 118.025 3.115 118.755 ; + RECT 3.415 118.025 3.615 118.755 ; + RECT 3.91 118.025 4.11 118.755 ; + RECT 4.655 0.17 5.425 0.94 ; + RECT 4.655 0.17 4.915 12.9 ; + RECT 5.165 0.17 5.425 12.9 ; + RECT 4.145 0.52 4.405 5.815 ; + RECT 4.73 118.025 4.93 118.755 ; + RECT 5.675 0.17 6.445 0.43 ; + RECT 5.675 0.17 5.935 11.5 ; + RECT 6.185 0.17 6.445 11.5 ; + RECT 5.225 118.025 5.425 118.755 ; + RECT 5.725 118.025 5.925 118.755 ; + RECT 6.225 118.025 6.425 118.755 ; + RECT 7.715 0.17 8.485 0.43 ; + RECT 7.715 0.17 7.975 10.48 ; + RECT 8.225 0.17 8.485 10.99 ; + RECT 6.72 118.025 6.92 118.755 ; + RECT 7.54 118.025 7.74 118.755 ; + RECT 8.735 0.17 9.505 0.94 ; + RECT 8.735 0.17 8.995 8.7 ; + RECT 9.245 0.17 9.505 12.9 ; + RECT 8.035 118.025 8.235 118.755 ; + RECT 8.535 118.025 8.735 118.755 ; + RECT 9.035 118.025 9.235 118.755 ; + RECT 9.53 118.025 9.73 118.755 ; + RECT 9.755 0.52 10.015 2.485 ; + RECT 10.35 118.025 10.55 118.755 ; + RECT 10.62 0.52 10.88 14.11 ; + RECT 10.845 118.025 11.045 118.755 ; + RECT 11.13 0.52 11.39 2.335 ; + RECT 11.345 118.025 11.545 118.755 ; + RECT 11.845 118.025 12.045 118.755 ; + RECT 12.34 118.025 12.54 118.755 ; + RECT 14.53 0.52 14.79 5.16 ; + RECT 14.01 4.9 14.79 5.16 ; + RECT 14.01 4.9 14.27 6.64 ; + RECT 13.16 118.025 13.36 118.755 ; + RECT 13.655 118.025 13.855 118.755 ; + RECT 14.155 118.025 14.355 118.755 ; + RECT 14.655 118.025 14.855 118.755 ; + RECT 15.15 118.025 15.35 118.755 ; + RECT 15.895 0.17 16.665 0.94 ; + RECT 15.895 0.17 16.155 12.9 ; + RECT 16.405 0.17 16.665 12.9 ; + RECT 15.385 0.52 15.645 5.815 ; + RECT 15.97 118.025 16.17 118.755 ; + RECT 16.915 0.17 17.685 0.43 ; + RECT 16.915 0.17 17.175 11.5 ; + RECT 17.425 0.17 17.685 11.5 ; + RECT 16.465 118.025 16.665 118.755 ; + RECT 16.965 118.025 17.165 118.755 ; + RECT 17.465 118.025 17.665 118.755 ; + RECT 18.955 0.17 19.725 0.43 ; + RECT 18.955 0.17 19.215 10.48 ; + RECT 19.465 0.17 19.725 10.99 ; + RECT 17.96 118.025 18.16 118.755 ; + RECT 18.78 118.025 18.98 118.755 ; + RECT 19.975 0.17 20.745 0.94 ; + RECT 19.975 0.17 20.235 8.7 ; + RECT 20.485 0.17 20.745 12.9 ; + RECT 19.275 118.025 19.475 118.755 ; + RECT 19.775 118.025 19.975 118.755 ; + RECT 20.275 118.025 20.475 118.755 ; + RECT 20.77 118.025 20.97 118.755 ; + RECT 20.995 0.52 21.255 2.485 ; + RECT 21.59 118.025 21.79 118.755 ; + RECT 21.86 0.52 22.12 14.11 ; + RECT 22.085 118.025 22.285 118.755 ; + RECT 22.37 0.52 22.63 2.335 ; + RECT 22.585 118.025 22.785 118.755 ; + RECT 23.085 118.025 23.285 118.755 ; + RECT 23.58 118.025 23.78 118.755 ; + RECT 25.77 0.52 26.03 5.16 ; + RECT 25.25 4.9 26.03 5.16 ; + RECT 25.25 4.9 25.51 6.64 ; + RECT 24.4 118.025 24.6 118.755 ; + RECT 24.895 118.025 25.095 118.755 ; + RECT 25.395 118.025 25.595 118.755 ; + RECT 25.895 118.025 26.095 118.755 ; + RECT 26.39 118.025 26.59 118.755 ; + RECT 27.135 0.17 27.905 0.94 ; + RECT 27.135 0.17 27.395 12.9 ; + RECT 27.645 0.17 27.905 12.9 ; + RECT 26.625 0.52 26.885 5.815 ; + RECT 27.21 118.025 27.41 118.755 ; + RECT 28.155 0.17 28.925 0.43 ; + RECT 28.155 0.17 28.415 11.5 ; + RECT 28.665 0.17 28.925 11.5 ; + RECT 27.705 118.025 27.905 118.755 ; + RECT 28.205 118.025 28.405 118.755 ; + RECT 28.705 118.025 28.905 118.755 ; + RECT 30.195 0.17 30.965 0.43 ; + RECT 30.195 0.17 30.455 10.48 ; + RECT 30.705 0.17 30.965 10.99 ; + RECT 29.2 118.025 29.4 118.755 ; + RECT 30.02 118.025 30.22 118.755 ; + RECT 31.215 0.17 31.985 0.94 ; + RECT 31.215 0.17 31.475 8.7 ; + RECT 31.725 0.17 31.985 12.9 ; + RECT 30.515 118.025 30.715 118.755 ; + RECT 31.015 118.025 31.215 118.755 ; + RECT 31.515 118.025 31.715 118.755 ; + RECT 32.01 118.025 32.21 118.755 ; + RECT 32.235 0.52 32.495 2.485 ; + RECT 32.83 118.025 33.03 118.755 ; + RECT 33.1 0.52 33.36 14.11 ; + RECT 33.325 118.025 33.525 118.755 ; + RECT 33.61 0.52 33.87 2.335 ; + RECT 33.825 118.025 34.025 118.755 ; + RECT 34.325 118.025 34.525 118.755 ; + RECT 34.82 118.025 35.02 118.755 ; + RECT 37.01 0.52 37.27 5.16 ; + RECT 36.49 4.9 37.27 5.16 ; + RECT 36.49 4.9 36.75 6.64 ; + RECT 35.64 118.025 35.84 118.755 ; + RECT 36.135 118.025 36.335 118.755 ; + RECT 36.635 118.025 36.835 118.755 ; + RECT 37.135 118.025 37.335 118.755 ; + RECT 37.63 118.025 37.83 118.755 ; + RECT 38.375 0.17 39.145 0.94 ; + RECT 38.375 0.17 38.635 12.9 ; + RECT 38.885 0.17 39.145 12.9 ; + RECT 37.865 0.52 38.125 5.815 ; + RECT 38.45 118.025 38.65 118.755 ; + RECT 39.395 0.17 40.165 0.43 ; + RECT 39.395 0.17 39.655 11.5 ; + RECT 39.905 0.17 40.165 11.5 ; + RECT 38.945 118.025 39.145 118.755 ; + RECT 39.445 118.025 39.645 118.755 ; + RECT 39.945 118.025 40.145 118.755 ; + RECT 41.435 0.17 42.205 0.43 ; + RECT 41.435 0.17 41.695 10.48 ; + RECT 41.945 0.17 42.205 10.99 ; + RECT 40.44 118.025 40.64 118.755 ; + RECT 41.26 118.025 41.46 118.755 ; + RECT 42.455 0.17 43.225 0.94 ; + RECT 42.455 0.17 42.715 8.7 ; + RECT 42.965 0.17 43.225 12.9 ; + RECT 41.755 118.025 41.955 118.755 ; + RECT 42.255 118.025 42.455 118.755 ; + RECT 42.755 118.025 42.955 118.755 ; + RECT 43.25 118.025 43.45 118.755 ; + RECT 43.475 0.52 43.735 2.485 ; + RECT 44.07 118.025 44.27 118.755 ; + RECT 44.34 0.52 44.6 14.11 ; + RECT 44.565 118.025 44.765 118.755 ; + RECT 44.85 0.52 45.11 2.335 ; + RECT 45.065 118.025 45.265 118.755 ; + RECT 45.565 118.025 45.765 118.755 ; + RECT 46.06 118.025 46.26 118.755 ; + RECT 48.25 0.52 48.51 5.16 ; + RECT 47.73 4.9 48.51 5.16 ; + RECT 47.73 4.9 47.99 6.64 ; + RECT 46.88 118.025 47.08 118.755 ; + RECT 47.375 118.025 47.575 118.755 ; + RECT 47.875 118.025 48.075 118.755 ; + RECT 48.375 118.025 48.575 118.755 ; + RECT 48.87 118.025 49.07 118.755 ; + RECT 49.615 0.17 50.385 0.94 ; + RECT 49.615 0.17 49.875 12.9 ; + RECT 50.125 0.17 50.385 12.9 ; + RECT 49.105 0.52 49.365 5.815 ; + RECT 49.69 118.025 49.89 118.755 ; + RECT 50.635 0.17 51.405 0.43 ; + RECT 50.635 0.17 50.895 11.5 ; + RECT 51.145 0.17 51.405 11.5 ; + RECT 50.185 118.025 50.385 118.755 ; + RECT 50.685 118.025 50.885 118.755 ; + RECT 51.185 118.025 51.385 118.755 ; + RECT 52.675 0.17 53.445 0.43 ; + RECT 52.675 0.17 52.935 10.48 ; + RECT 53.185 0.17 53.445 10.99 ; + RECT 51.68 118.025 51.88 118.755 ; + RECT 52.5 118.025 52.7 118.755 ; + RECT 53.695 0.17 54.465 0.94 ; + RECT 53.695 0.17 53.955 8.7 ; + RECT 54.205 0.17 54.465 12.9 ; + RECT 52.995 118.025 53.195 118.755 ; + RECT 53.495 118.025 53.695 118.755 ; + RECT 53.995 118.025 54.195 118.755 ; + RECT 54.49 118.025 54.69 118.755 ; + RECT 54.715 0.52 54.975 2.485 ; + RECT 55.31 118.025 55.51 118.755 ; + RECT 55.58 0.52 55.84 14.11 ; + RECT 55.805 118.025 56.005 118.755 ; + RECT 56.09 0.52 56.35 2.335 ; + RECT 56.305 118.025 56.505 118.755 ; + RECT 56.805 118.025 57.005 118.755 ; + RECT 57.3 118.025 57.5 118.755 ; + RECT 59.49 0.52 59.75 5.16 ; + RECT 58.97 4.9 59.75 5.16 ; + RECT 58.97 4.9 59.23 6.64 ; + RECT 58.12 118.025 58.32 118.755 ; + RECT 58.615 118.025 58.815 118.755 ; + RECT 59.115 118.025 59.315 118.755 ; + RECT 59.615 118.025 59.815 118.755 ; + RECT 60.11 118.025 60.31 118.755 ; + RECT 60.855 0.17 61.625 0.94 ; + RECT 60.855 0.17 61.115 12.9 ; + RECT 61.365 0.17 61.625 12.9 ; + RECT 60.345 0.52 60.605 5.815 ; + RECT 60.93 118.025 61.13 118.755 ; + RECT 61.875 0.17 62.645 0.43 ; + RECT 61.875 0.17 62.135 11.5 ; + RECT 62.385 0.17 62.645 11.5 ; + RECT 61.425 118.025 61.625 118.755 ; + RECT 61.925 118.025 62.125 118.755 ; + RECT 62.425 118.025 62.625 118.755 ; + RECT 63.915 0.17 64.685 0.43 ; + RECT 63.915 0.17 64.175 10.48 ; + RECT 64.425 0.17 64.685 10.99 ; + RECT 62.92 118.025 63.12 118.755 ; + RECT 63.74 118.025 63.94 118.755 ; + RECT 64.935 0.17 65.705 0.94 ; + RECT 64.935 0.17 65.195 8.7 ; + RECT 65.445 0.17 65.705 12.9 ; + RECT 64.235 118.025 64.435 118.755 ; + RECT 64.735 118.025 64.935 118.755 ; + RECT 65.235 118.025 65.435 118.755 ; + RECT 65.73 118.025 65.93 118.755 ; + RECT 65.955 0.52 66.215 2.485 ; + RECT 66.55 118.025 66.75 118.755 ; + RECT 66.82 0.52 67.08 14.11 ; + RECT 67.045 118.025 67.245 118.755 ; + RECT 67.33 0.52 67.59 2.335 ; + RECT 67.545 118.025 67.745 118.755 ; + RECT 68.045 118.025 68.245 118.755 ; + RECT 68.54 118.025 68.74 118.755 ; + RECT 70.73 0.52 70.99 5.16 ; + RECT 70.21 4.9 70.99 5.16 ; + RECT 70.21 4.9 70.47 6.64 ; + RECT 69.36 118.025 69.56 118.755 ; + RECT 69.855 118.025 70.055 118.755 ; + RECT 70.355 118.025 70.555 118.755 ; + RECT 70.855 118.025 71.055 118.755 ; + RECT 71.35 118.025 71.55 118.755 ; + RECT 72.095 0.17 72.865 0.94 ; + RECT 72.095 0.17 72.355 12.9 ; + RECT 72.605 0.17 72.865 12.9 ; + RECT 71.585 0.52 71.845 5.815 ; + RECT 72.17 118.025 72.37 118.755 ; + RECT 73.115 0.17 73.885 0.43 ; + RECT 73.115 0.17 73.375 11.5 ; + RECT 73.625 0.17 73.885 11.5 ; + RECT 72.665 118.025 72.865 118.755 ; + RECT 73.165 118.025 73.365 118.755 ; + RECT 73.665 118.025 73.865 118.755 ; + RECT 75.155 0.17 75.925 0.43 ; + RECT 75.155 0.17 75.415 10.48 ; + RECT 75.665 0.17 75.925 10.99 ; + RECT 74.16 118.025 74.36 118.755 ; + RECT 74.98 118.025 75.18 118.755 ; + RECT 76.175 0.17 76.945 0.94 ; + RECT 76.175 0.17 76.435 8.7 ; + RECT 76.685 0.17 76.945 12.9 ; + RECT 75.475 118.025 75.675 118.755 ; + RECT 75.975 118.025 76.175 118.755 ; + RECT 76.475 118.025 76.675 118.755 ; + RECT 76.97 118.025 77.17 118.755 ; + RECT 77.195 0.52 77.455 2.485 ; + RECT 77.79 118.025 77.99 118.755 ; + RECT 78.06 0.52 78.32 14.11 ; + RECT 78.285 118.025 78.485 118.755 ; + RECT 78.57 0.52 78.83 2.335 ; + RECT 78.785 118.025 78.985 118.755 ; + RECT 79.285 118.025 79.485 118.755 ; + RECT 79.78 118.025 79.98 118.755 ; + RECT 81.97 0.52 82.23 5.16 ; + RECT 81.45 4.9 82.23 5.16 ; + RECT 81.45 4.9 81.71 6.64 ; + RECT 80.6 118.025 80.8 118.755 ; + RECT 81.095 118.025 81.295 118.755 ; + RECT 81.595 118.025 81.795 118.755 ; + RECT 82.095 118.025 82.295 118.755 ; + RECT 82.59 118.025 82.79 118.755 ; + RECT 83.335 0.17 84.105 0.94 ; + RECT 83.335 0.17 83.595 12.9 ; + RECT 83.845 0.17 84.105 12.9 ; + RECT 82.825 0.52 83.085 5.815 ; + RECT 83.41 118.025 83.61 118.755 ; + RECT 84.355 0.17 85.125 0.43 ; + RECT 84.355 0.17 84.615 11.5 ; + RECT 84.865 0.17 85.125 11.5 ; + RECT 83.905 118.025 84.105 118.755 ; + RECT 84.405 118.025 84.605 118.755 ; + RECT 84.905 118.025 85.105 118.755 ; + RECT 86.395 0.17 87.165 0.43 ; + RECT 86.395 0.17 86.655 10.48 ; + RECT 86.905 0.17 87.165 10.99 ; + RECT 85.4 118.025 85.6 118.755 ; + RECT 86.22 118.025 86.42 118.755 ; + RECT 87.415 0.17 88.185 0.94 ; + RECT 87.415 0.17 87.675 8.7 ; + RECT 87.925 0.17 88.185 12.9 ; + RECT 86.715 118.025 86.915 118.755 ; + RECT 87.215 118.025 87.415 118.755 ; + RECT 87.715 118.025 87.915 118.755 ; + RECT 88.21 118.025 88.41 118.755 ; + RECT 88.435 0.52 88.695 2.485 ; + RECT 89.03 118.025 89.23 118.755 ; + RECT 89.3 0.52 89.56 14.11 ; + RECT 89.525 118.025 89.725 118.755 ; + RECT 89.81 0.52 90.07 2.335 ; + RECT 90.025 118.025 90.225 118.755 ; + RECT 90.525 118.025 90.725 118.755 ; + RECT 91.02 118.025 91.22 118.755 ; + RECT 93.21 0.52 93.47 5.16 ; + RECT 92.69 4.9 93.47 5.16 ; + RECT 92.69 4.9 92.95 6.64 ; + RECT 91.84 118.025 92.04 118.755 ; + RECT 92.335 118.025 92.535 118.755 ; + RECT 92.835 118.025 93.035 118.755 ; + RECT 93.335 118.025 93.535 118.755 ; + RECT 93.83 118.025 94.03 118.755 ; + RECT 94.575 0.17 95.345 0.94 ; + RECT 94.575 0.17 94.835 12.9 ; + RECT 95.085 0.17 95.345 12.9 ; + RECT 94.065 0.52 94.325 5.815 ; + RECT 94.65 118.025 94.85 118.755 ; + RECT 95.595 0.17 96.365 0.43 ; + RECT 95.595 0.17 95.855 11.5 ; + RECT 96.105 0.17 96.365 11.5 ; + RECT 95.145 118.025 95.345 118.755 ; + RECT 95.645 118.025 95.845 118.755 ; + RECT 96.145 118.025 96.345 118.755 ; + RECT 97.635 0.17 98.405 0.43 ; + RECT 97.635 0.17 97.895 10.48 ; + RECT 98.145 0.17 98.405 10.99 ; + RECT 96.64 118.025 96.84 118.755 ; + RECT 97.46 118.025 97.66 118.755 ; + RECT 98.655 0.17 99.425 0.94 ; + RECT 98.655 0.17 98.915 8.7 ; + RECT 99.165 0.17 99.425 12.9 ; + RECT 97.955 118.025 98.155 118.755 ; + RECT 98.455 118.025 98.655 118.755 ; + RECT 98.955 118.025 99.155 118.755 ; + RECT 99.45 118.025 99.65 118.755 ; + RECT 99.675 0.52 99.935 2.485 ; + RECT 100.27 118.025 100.47 118.755 ; + RECT 100.54 0.52 100.8 14.11 ; + RECT 100.765 118.025 100.965 118.755 ; + RECT 101.05 0.52 101.31 2.335 ; + RECT 101.265 118.025 101.465 118.755 ; + RECT 101.765 118.025 101.965 118.755 ; + RECT 102.26 118.025 102.46 118.755 ; + RECT 104.45 0.52 104.71 5.16 ; + RECT 103.93 4.9 104.71 5.16 ; + RECT 103.93 4.9 104.19 6.64 ; + RECT 103.08 118.025 103.28 118.755 ; + RECT 103.575 118.025 103.775 118.755 ; + RECT 104.075 118.025 104.275 118.755 ; + RECT 104.575 118.025 104.775 118.755 ; + RECT 105.07 118.025 105.27 118.755 ; + RECT 105.815 0.17 106.585 0.94 ; + RECT 105.815 0.17 106.075 12.9 ; + RECT 106.325 0.17 106.585 12.9 ; + RECT 105.305 0.52 105.565 5.815 ; + RECT 105.89 118.025 106.09 118.755 ; + RECT 106.835 0.17 107.605 0.43 ; + RECT 106.835 0.17 107.095 11.5 ; + RECT 107.345 0.17 107.605 11.5 ; + RECT 106.385 118.025 106.585 118.755 ; + RECT 106.885 118.025 107.085 118.755 ; + RECT 107.385 118.025 107.585 118.755 ; + RECT 108.875 0.17 109.645 0.43 ; + RECT 108.875 0.17 109.135 10.48 ; + RECT 109.385 0.17 109.645 10.99 ; + RECT 107.88 118.025 108.08 118.755 ; + RECT 108.7 118.025 108.9 118.755 ; + RECT 109.895 0.17 110.665 0.94 ; + RECT 109.895 0.17 110.155 8.7 ; + RECT 110.405 0.17 110.665 12.9 ; + RECT 109.195 118.025 109.395 118.755 ; + RECT 109.695 118.025 109.895 118.755 ; + RECT 110.195 118.025 110.395 118.755 ; + RECT 110.69 118.025 110.89 118.755 ; + RECT 110.915 0.52 111.175 2.485 ; + RECT 111.51 118.025 111.71 118.755 ; + RECT 111.78 0.52 112.04 14.11 ; + RECT 112.005 118.025 112.205 118.755 ; + RECT 112.29 0.52 112.55 2.335 ; + RECT 112.505 118.025 112.705 118.755 ; + RECT 113.005 118.025 113.205 118.755 ; + RECT 113.5 118.025 113.7 118.755 ; + RECT 115.69 0.52 115.95 5.16 ; + RECT 115.17 4.9 115.95 5.16 ; + RECT 115.17 4.9 115.43 6.64 ; + RECT 114.32 118.025 114.52 118.755 ; + RECT 114.815 118.025 115.015 118.755 ; + RECT 115.315 118.025 115.515 118.755 ; + RECT 115.815 118.025 116.015 118.755 ; + RECT 116.31 118.025 116.51 118.755 ; + RECT 117.055 0.17 117.825 0.94 ; + RECT 117.055 0.17 117.315 12.9 ; + RECT 117.565 0.17 117.825 12.9 ; + RECT 116.545 0.52 116.805 5.815 ; + RECT 117.13 118.025 117.33 118.755 ; + RECT 118.075 0.17 118.845 0.43 ; + RECT 118.075 0.17 118.335 11.5 ; + RECT 118.585 0.17 118.845 11.5 ; + RECT 117.625 118.025 117.825 118.755 ; + RECT 118.125 118.025 118.325 118.755 ; + RECT 118.625 118.025 118.825 118.755 ; + RECT 120.115 0.17 120.885 0.43 ; + RECT 120.115 0.17 120.375 10.48 ; + RECT 120.625 0.17 120.885 10.99 ; + RECT 119.12 118.025 119.32 118.755 ; + RECT 119.94 118.025 120.14 118.755 ; + RECT 121.135 0.17 121.905 0.94 ; + RECT 121.135 0.17 121.395 8.7 ; + RECT 121.645 0.17 121.905 12.9 ; + RECT 120.435 118.025 120.635 118.755 ; + RECT 120.935 118.025 121.135 118.755 ; + RECT 121.435 118.025 121.635 118.755 ; + RECT 121.93 118.025 122.13 118.755 ; + RECT 122.155 0.52 122.415 2.485 ; + RECT 122.75 118.025 122.95 118.755 ; + RECT 123.02 0.52 123.28 14.11 ; + RECT 123.245 118.025 123.445 118.755 ; + RECT 123.53 0.52 123.79 2.335 ; + RECT 123.745 118.025 123.945 118.755 ; + RECT 124.245 118.025 124.445 118.755 ; + RECT 124.74 118.025 124.94 118.755 ; + RECT 126.93 0.52 127.19 5.16 ; + RECT 126.41 4.9 127.19 5.16 ; + RECT 126.41 4.9 126.67 6.64 ; + RECT 125.56 118.025 125.76 118.755 ; + RECT 126.055 118.025 126.255 118.755 ; + RECT 126.555 118.025 126.755 118.755 ; + RECT 127.055 118.025 127.255 118.755 ; + RECT 127.55 118.025 127.75 118.755 ; + RECT 128.295 0.17 129.065 0.94 ; + RECT 128.295 0.17 128.555 12.9 ; + RECT 128.805 0.17 129.065 12.9 ; + RECT 127.785 0.52 128.045 5.815 ; + RECT 128.37 118.025 128.57 118.755 ; + RECT 129.315 0.17 130.085 0.43 ; + RECT 129.315 0.17 129.575 11.5 ; + RECT 129.825 0.17 130.085 11.5 ; + RECT 128.865 118.025 129.065 118.755 ; + RECT 129.365 118.025 129.565 118.755 ; + RECT 129.865 118.025 130.065 118.755 ; + RECT 131.355 0.17 132.125 0.43 ; + RECT 131.355 0.17 131.615 10.48 ; + RECT 131.865 0.17 132.125 10.99 ; + RECT 130.36 118.025 130.56 118.755 ; + RECT 131.18 118.025 131.38 118.755 ; + RECT 132.375 0.17 133.145 0.94 ; + RECT 132.375 0.17 132.635 8.7 ; + RECT 132.885 0.17 133.145 12.9 ; + RECT 131.675 118.025 131.875 118.755 ; + RECT 132.175 118.025 132.375 118.755 ; + RECT 132.675 118.025 132.875 118.755 ; + RECT 133.17 118.025 133.37 118.755 ; + RECT 133.395 0.52 133.655 2.485 ; + RECT 133.99 118.025 134.19 118.755 ; + RECT 134.26 0.52 134.52 14.11 ; + RECT 134.485 118.025 134.685 118.755 ; + RECT 134.77 0.52 135.03 2.335 ; + RECT 134.985 118.025 135.185 118.755 ; + RECT 135.485 118.025 135.685 118.755 ; + RECT 135.98 118.025 136.18 118.755 ; + RECT 138.17 0.52 138.43 5.16 ; + RECT 137.65 4.9 138.43 5.16 ; + RECT 137.65 4.9 137.91 6.64 ; + RECT 136.8 118.025 137 118.755 ; + RECT 137.295 118.025 137.495 118.755 ; + RECT 137.795 118.025 137.995 118.755 ; + RECT 138.295 118.025 138.495 118.755 ; + RECT 138.79 118.025 138.99 118.755 ; + RECT 139.535 0.17 140.305 0.94 ; + RECT 139.535 0.17 139.795 12.9 ; + RECT 140.045 0.17 140.305 12.9 ; + RECT 139.025 0.52 139.285 5.815 ; + RECT 139.61 118.025 139.81 118.755 ; + RECT 140.555 0.17 141.325 0.43 ; + RECT 140.555 0.17 140.815 11.5 ; + RECT 141.065 0.17 141.325 11.5 ; + RECT 140.105 118.025 140.305 118.755 ; + RECT 140.605 118.025 140.805 118.755 ; + RECT 141.105 118.025 141.305 118.755 ; + RECT 142.595 0.17 143.365 0.43 ; + RECT 142.595 0.17 142.855 10.48 ; + RECT 143.105 0.17 143.365 10.99 ; + RECT 141.6 118.025 141.8 118.755 ; + RECT 142.42 118.025 142.62 118.755 ; + RECT 143.615 0.17 144.385 0.94 ; + RECT 143.615 0.17 143.875 8.7 ; + RECT 144.125 0.17 144.385 12.9 ; + RECT 142.915 118.025 143.115 118.755 ; + RECT 143.415 118.025 143.615 118.755 ; + RECT 143.915 118.025 144.115 118.755 ; + RECT 144.41 118.025 144.61 118.755 ; + RECT 144.635 0.52 144.895 2.485 ; + RECT 145.23 118.025 145.43 118.755 ; + RECT 145.5 0.52 145.76 14.11 ; + RECT 145.725 118.025 145.925 118.755 ; + RECT 146.01 0.52 146.27 2.335 ; + RECT 146.225 118.025 146.425 118.755 ; + RECT 146.725 118.025 146.925 118.755 ; + RECT 147.22 118.025 147.42 118.755 ; + RECT 149.41 0.52 149.67 5.16 ; + RECT 148.89 4.9 149.67 5.16 ; + RECT 148.89 4.9 149.15 6.64 ; + RECT 148.04 118.025 148.24 118.755 ; + RECT 148.535 118.025 148.735 118.755 ; + RECT 149.035 118.025 149.235 118.755 ; + RECT 149.535 118.025 149.735 118.755 ; + RECT 150.03 118.025 150.23 118.755 ; + RECT 150.775 0.17 151.545 0.94 ; + RECT 150.775 0.17 151.035 12.9 ; + RECT 151.285 0.17 151.545 12.9 ; + RECT 150.265 0.52 150.525 5.815 ; + RECT 150.85 118.025 151.05 118.755 ; + RECT 151.795 0.17 152.565 0.43 ; + RECT 151.795 0.17 152.055 11.5 ; + RECT 152.305 0.17 152.565 11.5 ; + RECT 151.345 118.025 151.545 118.755 ; + RECT 151.845 118.025 152.045 118.755 ; + RECT 152.345 118.025 152.545 118.755 ; + RECT 153.835 0.17 154.605 0.43 ; + RECT 153.835 0.17 154.095 10.48 ; + RECT 154.345 0.17 154.605 10.99 ; + RECT 152.84 118.025 153.04 118.755 ; + RECT 153.66 118.025 153.86 118.755 ; + RECT 154.855 0.17 155.625 0.94 ; + RECT 154.855 0.17 155.115 8.7 ; + RECT 155.365 0.17 155.625 12.9 ; + RECT 154.155 118.025 154.355 118.755 ; + RECT 154.655 118.025 154.855 118.755 ; + RECT 155.155 118.025 155.355 118.755 ; + RECT 155.65 118.025 155.85 118.755 ; + RECT 155.875 0.52 156.135 2.485 ; + RECT 156.47 118.025 156.67 118.755 ; + RECT 156.74 0.52 157 14.11 ; + RECT 156.965 118.025 157.165 118.755 ; + RECT 157.25 0.52 157.51 2.335 ; + RECT 157.465 118.025 157.665 118.755 ; + RECT 157.965 118.025 158.165 118.755 ; + RECT 158.46 118.025 158.66 118.755 ; + RECT 160.65 0.52 160.91 5.16 ; + RECT 160.13 4.9 160.91 5.16 ; + RECT 160.13 4.9 160.39 6.64 ; + RECT 159.28 118.025 159.48 118.755 ; + RECT 159.775 118.025 159.975 118.755 ; + RECT 160.275 118.025 160.475 118.755 ; + RECT 160.775 118.025 160.975 118.755 ; + RECT 161.27 118.025 161.47 118.755 ; + RECT 162.015 0.17 162.785 0.94 ; + RECT 162.015 0.17 162.275 12.9 ; + RECT 162.525 0.17 162.785 12.9 ; + RECT 161.505 0.52 161.765 5.815 ; + RECT 162.09 118.025 162.29 118.755 ; + RECT 163.035 0.17 163.805 0.43 ; + RECT 163.035 0.17 163.295 11.5 ; + RECT 163.545 0.17 163.805 11.5 ; + RECT 162.585 118.025 162.785 118.755 ; + RECT 163.085 118.025 163.285 118.755 ; + RECT 163.585 118.025 163.785 118.755 ; + RECT 165.075 0.17 165.845 0.43 ; + RECT 165.075 0.17 165.335 10.48 ; + RECT 165.585 0.17 165.845 10.99 ; + RECT 164.08 118.025 164.28 118.755 ; + RECT 164.9 118.025 165.1 118.755 ; + RECT 166.095 0.17 166.865 0.94 ; + RECT 166.095 0.17 166.355 8.7 ; + RECT 166.605 0.17 166.865 12.9 ; + RECT 165.395 118.025 165.595 118.755 ; + RECT 165.895 118.025 166.095 118.755 ; + RECT 166.395 118.025 166.595 118.755 ; + RECT 166.89 118.025 167.09 118.755 ; + RECT 167.115 0.52 167.375 2.485 ; + RECT 167.71 118.025 167.91 118.755 ; + RECT 167.98 0.52 168.24 14.11 ; + RECT 168.205 118.025 168.405 118.755 ; + RECT 168.49 0.52 168.75 2.335 ; + RECT 168.705 118.025 168.905 118.755 ; + RECT 169.205 118.025 169.405 118.755 ; + RECT 169.7 118.025 169.9 118.755 ; + RECT 171.89 0.52 172.15 5.16 ; + RECT 171.37 4.9 172.15 5.16 ; + RECT 171.37 4.9 171.63 6.64 ; + RECT 170.52 118.025 170.72 118.755 ; + RECT 171.015 118.025 171.215 118.755 ; + RECT 171.515 118.025 171.715 118.755 ; + RECT 172.015 118.025 172.215 118.755 ; + RECT 172.51 118.025 172.71 118.755 ; + RECT 173.255 0.17 174.025 0.94 ; + RECT 173.255 0.17 173.515 12.9 ; + RECT 173.765 0.17 174.025 12.9 ; + RECT 172.745 0.52 173.005 5.815 ; + RECT 173.33 118.025 173.53 118.755 ; + RECT 174.275 0.17 175.045 0.43 ; + RECT 174.275 0.17 174.535 11.5 ; + RECT 174.785 0.17 175.045 11.5 ; + RECT 173.825 118.025 174.025 118.755 ; + RECT 174.325 118.025 174.525 118.755 ; + RECT 174.825 118.025 175.025 118.755 ; + RECT 176.315 0.17 177.085 0.43 ; + RECT 176.315 0.17 176.575 10.48 ; + RECT 176.825 0.17 177.085 10.99 ; + RECT 175.32 118.025 175.52 118.755 ; + RECT 176.14 118.025 176.34 118.755 ; + RECT 177.335 0.17 178.105 0.94 ; + RECT 177.335 0.17 177.595 8.7 ; + RECT 177.845 0.17 178.105 12.9 ; + RECT 176.635 118.025 176.835 118.755 ; + RECT 177.135 118.025 177.335 118.755 ; + RECT 177.635 118.025 177.835 118.755 ; + RECT 178.13 118.025 178.33 118.755 ; + RECT 178.355 0.52 178.615 2.485 ; + RECT 178.95 118.025 179.15 118.755 ; + RECT 179.22 0.52 179.48 14.11 ; + RECT 179.445 118.025 179.645 118.755 ; + RECT 179.73 0.52 179.99 2.335 ; + RECT 179.945 118.025 180.145 118.755 ; + RECT 180.445 118.025 180.645 118.755 ; + RECT 182.435 0.17 183.205 0.43 ; + RECT 182.435 0.17 182.695 8.7 ; + RECT 182.945 0.17 183.205 8.7 ; + RECT 183.455 0.17 184.225 0.94 ; + RECT 183.455 0.17 183.715 8.7 ; + RECT 183.965 0.17 184.225 8.7 ; + RECT 184.475 0.17 185.245 0.43 ; + RECT 184.475 0.17 184.735 8.7 ; + RECT 184.985 0.17 185.245 8.7 ; + RECT 185.495 0.17 186.265 0.94 ; + RECT 185.495 0.17 185.755 8.7 ; + RECT 186.005 0.17 186.265 8.7 ; + RECT 186.515 0.17 187.285 0.43 ; + RECT 186.515 0.17 186.775 8.7 ; + RECT 187.025 0.17 187.285 8.7 ; + RECT 187.535 0.17 188.305 0.94 ; + RECT 187.535 0.17 187.795 8.7 ; + RECT 188.045 0.17 188.305 8.7 ; + RECT 180.94 118.025 181.14 118.755 ; + RECT 181.76 118.025 181.96 118.755 ; + RECT 182.755 118.025 182.955 118.755 ; + RECT 190.24 0.17 191.01 0.94 ; + RECT 190.24 0.17 190.5 8.7 ; + RECT 190.75 0.17 191.01 8.7 ; + RECT 188.71 0.3 188.97 8.7 ; + RECT 189.22 0 189.48 8.7 ; + RECT 189.73 0 189.99 8.7 ; + RECT 191.26 0 191.52 8.7 ; + RECT 191.77 0 192.03 8.7 ; + RECT 192.28 0.52 192.54 8.7 ; + RECT 192.79 0.52 193.05 8.7 ; + RECT 193.3 0.52 193.56 8.7 ; + RECT 195.34 0.17 196.11 0.94 ; + RECT 195.34 0.17 195.6 8.7 ; + RECT 195.85 0.17 196.11 8.7 ; + RECT 196.36 0.17 197.13 0.43 ; + RECT 196.36 0.17 196.62 8.7 ; + RECT 196.87 0.17 197.13 8.7 ; + RECT 193.81 0.52 194.07 8.7 ; + RECT 194.32 0 194.58 8.7 ; + RECT 194.83 0 195.09 8.7 ; + RECT 197.38 0.3 197.64 8.7 ; + RECT 197.89 0.3 198.15 8.7 ; + RECT 199.93 0.17 200.7 0.94 ; + RECT 199.93 0.17 200.19 8.7 ; + RECT 200.44 0.17 200.7 8.7 ; + RECT 198.4 0.3 198.66 8.7 ; + RECT 198.91 0.3 199.17 8.7 ; + RECT 199.42 0.3 199.68 8.7 ; + RECT 200.95 0.52 201.21 8.7 ; + RECT 201.46 0.52 201.72 8.7 ; + RECT 201.97 0.3 202.23 8.7 ; + RECT 202.48 0.52 202.74 8.7 ; + RECT 202.99 0.52 203.25 8.7 ; + RECT 203.5 0.3 203.76 8.7 ; + RECT 204.01 0.52 204.27 8.7 ; + RECT 204.52 0.52 204.78 8.7 ; + RECT 205.03 0.52 205.29 8.7 ; + RECT 205.54 0.52 205.8 8.7 ; + RECT 206.05 0.52 206.31 8.7 ; + RECT 206.56 0.3 206.82 8.7 ; + RECT 207.07 0.52 207.33 8.7 ; + RECT 207.58 0.52 207.84 8.7 ; + RECT 208.09 0.3 208.35 8.7 ; + RECT 210.13 0.17 210.9 0.94 ; + RECT 210.13 0.17 210.39 8.7 ; + RECT 210.64 0.17 210.9 8.7 ; + RECT 208.6 0.52 208.86 8.7 ; + RECT 209.11 0.52 209.37 8.7 ; + RECT 209.62 0.3 209.88 8.7 ; + RECT 211.15 0.52 211.41 8.7 ; + RECT 211.66 0.52 211.92 8.7 ; + RECT 212.17 0.52 212.43 8.7 ; + RECT 212.68 0.52 212.94 8.7 ; + RECT 213.19 0.52 213.45 8.7 ; + RECT 213.7 0.52 213.96 8.7 ; + RECT 214.21 0.52 214.47 8.7 ; + RECT 216.25 0.17 217.02 0.94 ; + RECT 216.25 0.17 216.51 8.7 ; + RECT 216.76 0.17 217.02 8.7 ; + RECT 214.72 0.52 214.98 8.7 ; + RECT 215.23 0 215.49 8.7 ; + RECT 215.74 0 216 8.7 ; + RECT 217.27 0 217.53 8.7 ; + RECT 219.31 0.17 220.08 0.43 ; + RECT 219.31 0.17 219.57 8.7 ; + RECT 219.82 0.17 220.08 8.7 ; + RECT 217.78 0 218.04 8.7 ; + RECT 218.29 0.3 218.55 8.7 ; + RECT 218.8 0.3 219.06 8.7 ; + RECT 220.33 0.3 220.59 8.7 ; + RECT 220.84 0.3 221.1 8.7 ; + RECT 221.35 0.3 221.61 8.7 ; + RECT 221.86 0.3 222.12 8.7 ; + RECT 222.37 0 222.63 8.7 ; + RECT 222.88 0 223.14 8.7 ; + RECT 224.92 0.17 225.69 0.43 ; + RECT 224.92 0.17 225.18 8.7 ; + RECT 225.43 0.17 225.69 8.7 ; + RECT 225.94 0.17 226.71 0.94 ; + RECT 225.94 0.17 226.2 25.5 ; + RECT 226.45 0.17 226.71 33.9 ; + RECT 226.96 0.17 227.73 0.43 ; + RECT 226.96 0.17 227.22 8.7 ; + RECT 227.47 0.17 227.73 8.7 ; + RECT 228.335 0.17 229.105 0.94 ; + RECT 228.335 0.17 228.595 8.7 ; + RECT 228.845 0.17 229.105 8.7 ; + RECT 229.355 0.17 230.125 0.43 ; + RECT 229.355 0.17 229.615 8.7 ; + RECT 229.865 0.17 230.125 8.7 ; + RECT 230.375 0.17 231.145 0.94 ; + RECT 230.375 0.17 230.635 8.7 ; + RECT 230.885 0.17 231.145 8.7 ; + RECT 231.395 0.17 232.165 0.43 ; + RECT 231.395 0.17 231.655 8.7 ; + RECT 231.905 0.17 232.165 8.7 ; + RECT 232.415 0.17 233.185 0.94 ; + RECT 232.415 0.17 232.675 8.7 ; + RECT 232.925 0.17 233.185 8.7 ; + RECT 223.39 0.3 223.65 8.7 ; + RECT 233.435 0.17 234.205 0.43 ; + RECT 233.435 0.17 233.695 8.7 ; + RECT 233.945 0.17 234.205 8.7 ; + RECT 223.9 0.3 224.16 8.7 ; + RECT 224.41 0.52 224.67 8.7 ; + RECT 233.685 118.025 233.885 118.755 ; + RECT 234.68 118.025 234.88 118.755 ; + RECT 235.5 118.025 235.7 118.755 ; + RECT 235.995 118.025 236.195 118.755 ; + RECT 236.495 118.025 236.695 118.755 ; + RECT 236.65 0.52 236.91 2.335 ; + RECT 236.995 118.025 237.195 118.755 ; + RECT 237.16 0.52 237.42 14.11 ; + RECT 237.49 118.025 237.69 118.755 ; + RECT 238.535 0.17 239.305 0.94 ; + RECT 239.045 0.17 239.305 8.7 ; + RECT 238.535 0.17 238.795 12.9 ; + RECT 238.025 0.52 238.285 2.485 ; + RECT 238.31 118.025 238.51 118.755 ; + RECT 239.555 0.17 240.325 0.43 ; + RECT 240.065 0.17 240.325 10.48 ; + RECT 239.555 0.17 239.815 10.99 ; + RECT 238.805 118.025 239.005 118.755 ; + RECT 239.305 118.025 239.505 118.755 ; + RECT 239.805 118.025 240.005 118.755 ; + RECT 240.3 118.025 240.5 118.755 ; + RECT 241.595 0.17 242.365 0.43 ; + RECT 241.595 0.17 241.855 11.5 ; + RECT 242.105 0.17 242.365 11.5 ; + RECT 241.12 118.025 241.32 118.755 ; + RECT 241.615 118.025 241.815 118.755 ; + RECT 242.615 0.17 243.385 0.94 ; + RECT 242.615 0.17 242.875 12.9 ; + RECT 243.125 0.17 243.385 12.9 ; + RECT 242.115 118.025 242.315 118.755 ; + RECT 242.615 118.025 242.815 118.755 ; + RECT 243.11 118.025 243.31 118.755 ; + RECT 243.635 0.52 243.895 5.815 ; + RECT 244.49 0.52 244.75 5.16 ; + RECT 244.49 4.9 245.27 5.16 ; + RECT 245.01 4.9 245.27 6.64 ; + RECT 243.93 118.025 244.13 118.755 ; + RECT 244.425 118.025 244.625 118.755 ; + RECT 244.925 118.025 245.125 118.755 ; + RECT 245.425 118.025 245.625 118.755 ; + RECT 245.92 118.025 246.12 118.755 ; + RECT 246.74 118.025 246.94 118.755 ; + RECT 247.235 118.025 247.435 118.755 ; + RECT 247.735 118.025 247.935 118.755 ; + RECT 247.89 0.52 248.15 2.335 ; + RECT 248.235 118.025 248.435 118.755 ; + RECT 248.4 0.52 248.66 14.11 ; + RECT 248.73 118.025 248.93 118.755 ; + RECT 249.775 0.17 250.545 0.94 ; + RECT 250.285 0.17 250.545 8.7 ; + RECT 249.775 0.17 250.035 12.9 ; + RECT 249.265 0.52 249.525 2.485 ; + RECT 249.55 118.025 249.75 118.755 ; + RECT 250.795 0.17 251.565 0.43 ; + RECT 251.305 0.17 251.565 10.48 ; + RECT 250.795 0.17 251.055 10.99 ; + RECT 250.045 118.025 250.245 118.755 ; + RECT 250.545 118.025 250.745 118.755 ; + RECT 251.045 118.025 251.245 118.755 ; + RECT 251.54 118.025 251.74 118.755 ; + RECT 252.835 0.17 253.605 0.43 ; + RECT 252.835 0.17 253.095 11.5 ; + RECT 253.345 0.17 253.605 11.5 ; + RECT 252.36 118.025 252.56 118.755 ; + RECT 252.855 118.025 253.055 118.755 ; + RECT 253.855 0.17 254.625 0.94 ; + RECT 253.855 0.17 254.115 12.9 ; + RECT 254.365 0.17 254.625 12.9 ; + RECT 253.355 118.025 253.555 118.755 ; + RECT 253.855 118.025 254.055 118.755 ; + RECT 254.35 118.025 254.55 118.755 ; + RECT 254.875 0.52 255.135 5.815 ; + RECT 255.73 0.52 255.99 5.16 ; + RECT 255.73 4.9 256.51 5.16 ; + RECT 256.25 4.9 256.51 6.64 ; + RECT 255.17 118.025 255.37 118.755 ; + RECT 255.665 118.025 255.865 118.755 ; + RECT 256.165 118.025 256.365 118.755 ; + RECT 256.665 118.025 256.865 118.755 ; + RECT 257.16 118.025 257.36 118.755 ; + RECT 257.98 118.025 258.18 118.755 ; + RECT 258.475 118.025 258.675 118.755 ; + RECT 258.975 118.025 259.175 118.755 ; + RECT 259.13 0.52 259.39 2.335 ; + RECT 259.475 118.025 259.675 118.755 ; + RECT 259.64 0.52 259.9 14.11 ; + RECT 259.97 118.025 260.17 118.755 ; + RECT 261.015 0.17 261.785 0.94 ; + RECT 261.525 0.17 261.785 8.7 ; + RECT 261.015 0.17 261.275 12.9 ; + RECT 260.505 0.52 260.765 2.485 ; + RECT 260.79 118.025 260.99 118.755 ; + RECT 262.035 0.17 262.805 0.43 ; + RECT 262.545 0.17 262.805 10.48 ; + RECT 262.035 0.17 262.295 10.99 ; + RECT 261.285 118.025 261.485 118.755 ; + RECT 261.785 118.025 261.985 118.755 ; + RECT 262.285 118.025 262.485 118.755 ; + RECT 262.78 118.025 262.98 118.755 ; + RECT 264.075 0.17 264.845 0.43 ; + RECT 264.075 0.17 264.335 11.5 ; + RECT 264.585 0.17 264.845 11.5 ; + RECT 263.6 118.025 263.8 118.755 ; + RECT 264.095 118.025 264.295 118.755 ; + RECT 265.095 0.17 265.865 0.94 ; + RECT 265.095 0.17 265.355 12.9 ; + RECT 265.605 0.17 265.865 12.9 ; + RECT 264.595 118.025 264.795 118.755 ; + RECT 265.095 118.025 265.295 118.755 ; + RECT 265.59 118.025 265.79 118.755 ; + RECT 266.115 0.52 266.375 5.815 ; + RECT 266.97 0.52 267.23 5.16 ; + RECT 266.97 4.9 267.75 5.16 ; + RECT 267.49 4.9 267.75 6.64 ; + RECT 266.41 118.025 266.61 118.755 ; + RECT 266.905 118.025 267.105 118.755 ; + RECT 267.405 118.025 267.605 118.755 ; + RECT 267.905 118.025 268.105 118.755 ; + RECT 268.4 118.025 268.6 118.755 ; + RECT 269.22 118.025 269.42 118.755 ; + RECT 269.715 118.025 269.915 118.755 ; + RECT 270.215 118.025 270.415 118.755 ; + RECT 270.37 0.52 270.63 2.335 ; + RECT 270.715 118.025 270.915 118.755 ; + RECT 270.88 0.52 271.14 14.11 ; + RECT 271.21 118.025 271.41 118.755 ; + RECT 272.255 0.17 273.025 0.94 ; + RECT 272.765 0.17 273.025 8.7 ; + RECT 272.255 0.17 272.515 12.9 ; + RECT 271.745 0.52 272.005 2.485 ; + RECT 272.03 118.025 272.23 118.755 ; + RECT 273.275 0.17 274.045 0.43 ; + RECT 273.785 0.17 274.045 10.48 ; + RECT 273.275 0.17 273.535 10.99 ; + RECT 272.525 118.025 272.725 118.755 ; + RECT 273.025 118.025 273.225 118.755 ; + RECT 273.525 118.025 273.725 118.755 ; + RECT 274.02 118.025 274.22 118.755 ; + RECT 275.315 0.17 276.085 0.43 ; + RECT 275.315 0.17 275.575 11.5 ; + RECT 275.825 0.17 276.085 11.5 ; + RECT 274.84 118.025 275.04 118.755 ; + RECT 275.335 118.025 275.535 118.755 ; + RECT 276.335 0.17 277.105 0.94 ; + RECT 276.335 0.17 276.595 12.9 ; + RECT 276.845 0.17 277.105 12.9 ; + RECT 275.835 118.025 276.035 118.755 ; + RECT 276.335 118.025 276.535 118.755 ; + RECT 276.83 118.025 277.03 118.755 ; + RECT 277.355 0.52 277.615 5.815 ; + RECT 278.21 0.52 278.47 5.16 ; + RECT 278.21 4.9 278.99 5.16 ; + RECT 278.73 4.9 278.99 6.64 ; + RECT 277.65 118.025 277.85 118.755 ; + RECT 278.145 118.025 278.345 118.755 ; + RECT 278.645 118.025 278.845 118.755 ; + RECT 279.145 118.025 279.345 118.755 ; + RECT 279.64 118.025 279.84 118.755 ; + RECT 280.46 118.025 280.66 118.755 ; + RECT 280.955 118.025 281.155 118.755 ; + RECT 281.455 118.025 281.655 118.755 ; + RECT 281.61 0.52 281.87 2.335 ; + RECT 281.955 118.025 282.155 118.755 ; + RECT 282.12 0.52 282.38 14.11 ; + RECT 282.45 118.025 282.65 118.755 ; + RECT 283.495 0.17 284.265 0.94 ; + RECT 284.005 0.17 284.265 8.7 ; + RECT 283.495 0.17 283.755 12.9 ; + RECT 282.985 0.52 283.245 2.485 ; + RECT 283.27 118.025 283.47 118.755 ; + RECT 284.515 0.17 285.285 0.43 ; + RECT 285.025 0.17 285.285 10.48 ; + RECT 284.515 0.17 284.775 10.99 ; + RECT 283.765 118.025 283.965 118.755 ; + RECT 284.265 118.025 284.465 118.755 ; + RECT 284.765 118.025 284.965 118.755 ; + RECT 285.26 118.025 285.46 118.755 ; + RECT 286.555 0.17 287.325 0.43 ; + RECT 286.555 0.17 286.815 11.5 ; + RECT 287.065 0.17 287.325 11.5 ; + RECT 286.08 118.025 286.28 118.755 ; + RECT 286.575 118.025 286.775 118.755 ; + RECT 287.575 0.17 288.345 0.94 ; + RECT 287.575 0.17 287.835 12.9 ; + RECT 288.085 0.17 288.345 12.9 ; + RECT 287.075 118.025 287.275 118.755 ; + RECT 287.575 118.025 287.775 118.755 ; + RECT 288.07 118.025 288.27 118.755 ; + RECT 288.595 0.52 288.855 5.815 ; + RECT 289.45 0.52 289.71 5.16 ; + RECT 289.45 4.9 290.23 5.16 ; + RECT 289.97 4.9 290.23 6.64 ; + RECT 288.89 118.025 289.09 118.755 ; + RECT 289.385 118.025 289.585 118.755 ; + RECT 289.885 118.025 290.085 118.755 ; + RECT 290.385 118.025 290.585 118.755 ; + RECT 290.88 118.025 291.08 118.755 ; + RECT 291.7 118.025 291.9 118.755 ; + RECT 292.195 118.025 292.395 118.755 ; + RECT 292.695 118.025 292.895 118.755 ; + RECT 292.85 0.52 293.11 2.335 ; + RECT 293.195 118.025 293.395 118.755 ; + RECT 293.36 0.52 293.62 14.11 ; + RECT 293.69 118.025 293.89 118.755 ; + RECT 294.735 0.17 295.505 0.94 ; + RECT 295.245 0.17 295.505 8.7 ; + RECT 294.735 0.17 294.995 12.9 ; + RECT 294.225 0.52 294.485 2.485 ; + RECT 294.51 118.025 294.71 118.755 ; + RECT 295.755 0.17 296.525 0.43 ; + RECT 296.265 0.17 296.525 10.48 ; + RECT 295.755 0.17 296.015 10.99 ; + RECT 295.005 118.025 295.205 118.755 ; + RECT 295.505 118.025 295.705 118.755 ; + RECT 296.005 118.025 296.205 118.755 ; + RECT 296.5 118.025 296.7 118.755 ; + RECT 297.795 0.17 298.565 0.43 ; + RECT 297.795 0.17 298.055 11.5 ; + RECT 298.305 0.17 298.565 11.5 ; + RECT 297.32 118.025 297.52 118.755 ; + RECT 297.815 118.025 298.015 118.755 ; + RECT 298.815 0.17 299.585 0.94 ; + RECT 298.815 0.17 299.075 12.9 ; + RECT 299.325 0.17 299.585 12.9 ; + RECT 298.315 118.025 298.515 118.755 ; + RECT 298.815 118.025 299.015 118.755 ; + RECT 299.31 118.025 299.51 118.755 ; + RECT 299.835 0.52 300.095 5.815 ; + RECT 300.69 0.52 300.95 5.16 ; + RECT 300.69 4.9 301.47 5.16 ; + RECT 301.21 4.9 301.47 6.64 ; + RECT 300.13 118.025 300.33 118.755 ; + RECT 300.625 118.025 300.825 118.755 ; + RECT 301.125 118.025 301.325 118.755 ; + RECT 301.625 118.025 301.825 118.755 ; + RECT 302.12 118.025 302.32 118.755 ; + RECT 302.94 118.025 303.14 118.755 ; + RECT 303.435 118.025 303.635 118.755 ; + RECT 303.935 118.025 304.135 118.755 ; + RECT 304.09 0.52 304.35 2.335 ; + RECT 304.435 118.025 304.635 118.755 ; + RECT 304.6 0.52 304.86 14.11 ; + RECT 304.93 118.025 305.13 118.755 ; + RECT 305.975 0.17 306.745 0.94 ; + RECT 306.485 0.17 306.745 8.7 ; + RECT 305.975 0.17 306.235 12.9 ; + RECT 305.465 0.52 305.725 2.485 ; + RECT 305.75 118.025 305.95 118.755 ; + RECT 306.995 0.17 307.765 0.43 ; + RECT 307.505 0.17 307.765 10.48 ; + RECT 306.995 0.17 307.255 10.99 ; + RECT 306.245 118.025 306.445 118.755 ; + RECT 306.745 118.025 306.945 118.755 ; + RECT 307.245 118.025 307.445 118.755 ; + RECT 307.74 118.025 307.94 118.755 ; + RECT 309.035 0.17 309.805 0.43 ; + RECT 309.035 0.17 309.295 11.5 ; + RECT 309.545 0.17 309.805 11.5 ; + RECT 308.56 118.025 308.76 118.755 ; + RECT 309.055 118.025 309.255 118.755 ; + RECT 310.055 0.17 310.825 0.94 ; + RECT 310.055 0.17 310.315 12.9 ; + RECT 310.565 0.17 310.825 12.9 ; + RECT 309.555 118.025 309.755 118.755 ; + RECT 310.055 118.025 310.255 118.755 ; + RECT 310.55 118.025 310.75 118.755 ; + RECT 311.075 0.52 311.335 5.815 ; + RECT 311.93 0.52 312.19 5.16 ; + RECT 311.93 4.9 312.71 5.16 ; + RECT 312.45 4.9 312.71 6.64 ; + RECT 311.37 118.025 311.57 118.755 ; + RECT 311.865 118.025 312.065 118.755 ; + RECT 312.365 118.025 312.565 118.755 ; + RECT 312.865 118.025 313.065 118.755 ; + RECT 313.36 118.025 313.56 118.755 ; + RECT 314.18 118.025 314.38 118.755 ; + RECT 314.675 118.025 314.875 118.755 ; + RECT 315.175 118.025 315.375 118.755 ; + RECT 315.33 0.52 315.59 2.335 ; + RECT 315.675 118.025 315.875 118.755 ; + RECT 315.84 0.52 316.1 14.11 ; + RECT 316.17 118.025 316.37 118.755 ; + RECT 317.215 0.17 317.985 0.94 ; + RECT 317.725 0.17 317.985 8.7 ; + RECT 317.215 0.17 317.475 12.9 ; + RECT 316.705 0.52 316.965 2.485 ; + RECT 316.99 118.025 317.19 118.755 ; + RECT 318.235 0.17 319.005 0.43 ; + RECT 318.745 0.17 319.005 10.48 ; + RECT 318.235 0.17 318.495 10.99 ; + RECT 317.485 118.025 317.685 118.755 ; + RECT 317.985 118.025 318.185 118.755 ; + RECT 318.485 118.025 318.685 118.755 ; + RECT 318.98 118.025 319.18 118.755 ; + RECT 320.275 0.17 321.045 0.43 ; + RECT 320.275 0.17 320.535 11.5 ; + RECT 320.785 0.17 321.045 11.5 ; + RECT 319.8 118.025 320 118.755 ; + RECT 320.295 118.025 320.495 118.755 ; + RECT 321.295 0.17 322.065 0.94 ; + RECT 321.295 0.17 321.555 12.9 ; + RECT 321.805 0.17 322.065 12.9 ; + RECT 320.795 118.025 320.995 118.755 ; + RECT 321.295 118.025 321.495 118.755 ; + RECT 321.79 118.025 321.99 118.755 ; + RECT 322.315 0.52 322.575 5.815 ; + RECT 323.17 0.52 323.43 5.16 ; + RECT 323.17 4.9 323.95 5.16 ; + RECT 323.69 4.9 323.95 6.64 ; + RECT 322.61 118.025 322.81 118.755 ; + RECT 323.105 118.025 323.305 118.755 ; + RECT 323.605 118.025 323.805 118.755 ; + RECT 324.105 118.025 324.305 118.755 ; + RECT 324.6 118.025 324.8 118.755 ; + RECT 325.42 118.025 325.62 118.755 ; + RECT 325.915 118.025 326.115 118.755 ; + RECT 326.415 118.025 326.615 118.755 ; + RECT 326.57 0.52 326.83 2.335 ; + RECT 326.915 118.025 327.115 118.755 ; + RECT 327.08 0.52 327.34 14.11 ; + RECT 327.41 118.025 327.61 118.755 ; + RECT 328.455 0.17 329.225 0.94 ; + RECT 328.965 0.17 329.225 8.7 ; + RECT 328.455 0.17 328.715 12.9 ; + RECT 327.945 0.52 328.205 2.485 ; + RECT 328.23 118.025 328.43 118.755 ; + RECT 329.475 0.17 330.245 0.43 ; + RECT 329.985 0.17 330.245 10.48 ; + RECT 329.475 0.17 329.735 10.99 ; + RECT 328.725 118.025 328.925 118.755 ; + RECT 329.225 118.025 329.425 118.755 ; + RECT 329.725 118.025 329.925 118.755 ; + RECT 330.22 118.025 330.42 118.755 ; + RECT 331.515 0.17 332.285 0.43 ; + RECT 331.515 0.17 331.775 11.5 ; + RECT 332.025 0.17 332.285 11.5 ; + RECT 331.04 118.025 331.24 118.755 ; + RECT 331.535 118.025 331.735 118.755 ; + RECT 332.535 0.17 333.305 0.94 ; + RECT 332.535 0.17 332.795 12.9 ; + RECT 333.045 0.17 333.305 12.9 ; + RECT 332.035 118.025 332.235 118.755 ; + RECT 332.535 118.025 332.735 118.755 ; + RECT 333.03 118.025 333.23 118.755 ; + RECT 333.555 0.52 333.815 5.815 ; + RECT 334.41 0.52 334.67 5.16 ; + RECT 334.41 4.9 335.19 5.16 ; + RECT 334.93 4.9 335.19 6.64 ; + RECT 333.85 118.025 334.05 118.755 ; + RECT 334.345 118.025 334.545 118.755 ; + RECT 334.845 118.025 335.045 118.755 ; + RECT 335.345 118.025 335.545 118.755 ; + RECT 335.84 118.025 336.04 118.755 ; + RECT 336.66 118.025 336.86 118.755 ; + RECT 337.155 118.025 337.355 118.755 ; + RECT 337.655 118.025 337.855 118.755 ; + RECT 337.81 0.52 338.07 2.335 ; + RECT 338.155 118.025 338.355 118.755 ; + RECT 338.32 0.52 338.58 14.11 ; + RECT 338.65 118.025 338.85 118.755 ; + RECT 339.695 0.17 340.465 0.94 ; + RECT 340.205 0.17 340.465 8.7 ; + RECT 339.695 0.17 339.955 12.9 ; + RECT 339.185 0.52 339.445 2.485 ; + RECT 339.47 118.025 339.67 118.755 ; + RECT 340.715 0.17 341.485 0.43 ; + RECT 341.225 0.17 341.485 10.48 ; + RECT 340.715 0.17 340.975 10.99 ; + RECT 339.965 118.025 340.165 118.755 ; + RECT 340.465 118.025 340.665 118.755 ; + RECT 340.965 118.025 341.165 118.755 ; + RECT 341.46 118.025 341.66 118.755 ; + RECT 342.755 0.17 343.525 0.43 ; + RECT 342.755 0.17 343.015 11.5 ; + RECT 343.265 0.17 343.525 11.5 ; + RECT 342.28 118.025 342.48 118.755 ; + RECT 342.775 118.025 342.975 118.755 ; + RECT 343.775 0.17 344.545 0.94 ; + RECT 343.775 0.17 344.035 12.9 ; + RECT 344.285 0.17 344.545 12.9 ; + RECT 343.275 118.025 343.475 118.755 ; + RECT 343.775 118.025 343.975 118.755 ; + RECT 344.27 118.025 344.47 118.755 ; + RECT 344.795 0.52 345.055 5.815 ; + RECT 345.65 0.52 345.91 5.16 ; + RECT 345.65 4.9 346.43 5.16 ; + RECT 346.17 4.9 346.43 6.64 ; + RECT 345.09 118.025 345.29 118.755 ; + RECT 345.585 118.025 345.785 118.755 ; + RECT 346.085 118.025 346.285 118.755 ; + RECT 346.585 118.025 346.785 118.755 ; + RECT 347.08 118.025 347.28 118.755 ; + RECT 347.9 118.025 348.1 118.755 ; + RECT 348.395 118.025 348.595 118.755 ; + RECT 348.895 118.025 349.095 118.755 ; + RECT 349.05 0.52 349.31 2.335 ; + RECT 349.395 118.025 349.595 118.755 ; + RECT 349.56 0.52 349.82 14.11 ; + RECT 349.89 118.025 350.09 118.755 ; + RECT 350.935 0.17 351.705 0.94 ; + RECT 351.445 0.17 351.705 8.7 ; + RECT 350.935 0.17 351.195 12.9 ; + RECT 350.425 0.52 350.685 2.485 ; + RECT 350.71 118.025 350.91 118.755 ; + RECT 351.955 0.17 352.725 0.43 ; + RECT 352.465 0.17 352.725 10.48 ; + RECT 351.955 0.17 352.215 10.99 ; + RECT 351.205 118.025 351.405 118.755 ; + RECT 351.705 118.025 351.905 118.755 ; + RECT 352.205 118.025 352.405 118.755 ; + RECT 352.7 118.025 352.9 118.755 ; + RECT 353.995 0.17 354.765 0.43 ; + RECT 353.995 0.17 354.255 11.5 ; + RECT 354.505 0.17 354.765 11.5 ; + RECT 353.52 118.025 353.72 118.755 ; + RECT 354.015 118.025 354.215 118.755 ; + RECT 355.015 0.17 355.785 0.94 ; + RECT 355.015 0.17 355.275 12.9 ; + RECT 355.525 0.17 355.785 12.9 ; + RECT 354.515 118.025 354.715 118.755 ; + RECT 355.015 118.025 355.215 118.755 ; + RECT 355.51 118.025 355.71 118.755 ; + RECT 356.035 0.52 356.295 5.815 ; + RECT 356.89 0.52 357.15 5.16 ; + RECT 356.89 4.9 357.67 5.16 ; + RECT 357.41 4.9 357.67 6.64 ; + RECT 356.33 118.025 356.53 118.755 ; + RECT 356.825 118.025 357.025 118.755 ; + RECT 357.325 118.025 357.525 118.755 ; + RECT 357.825 118.025 358.025 118.755 ; + RECT 358.32 118.025 358.52 118.755 ; + RECT 359.14 118.025 359.34 118.755 ; + RECT 359.635 118.025 359.835 118.755 ; + RECT 360.135 118.025 360.335 118.755 ; + RECT 360.29 0.52 360.55 2.335 ; + RECT 360.635 118.025 360.835 118.755 ; + RECT 360.8 0.52 361.06 14.11 ; + RECT 361.13 118.025 361.33 118.755 ; + RECT 362.175 0.17 362.945 0.94 ; + RECT 362.685 0.17 362.945 8.7 ; + RECT 362.175 0.17 362.435 12.9 ; + RECT 361.665 0.52 361.925 2.485 ; + RECT 361.95 118.025 362.15 118.755 ; + RECT 363.195 0.17 363.965 0.43 ; + RECT 363.705 0.17 363.965 10.48 ; + RECT 363.195 0.17 363.455 10.99 ; + RECT 362.445 118.025 362.645 118.755 ; + RECT 362.945 118.025 363.145 118.755 ; + RECT 363.445 118.025 363.645 118.755 ; + RECT 363.94 118.025 364.14 118.755 ; + RECT 365.235 0.17 366.005 0.43 ; + RECT 365.235 0.17 365.495 11.5 ; + RECT 365.745 0.17 366.005 11.5 ; + RECT 364.76 118.025 364.96 118.755 ; + RECT 365.255 118.025 365.455 118.755 ; + RECT 366.255 0.17 367.025 0.94 ; + RECT 366.255 0.17 366.515 12.9 ; + RECT 366.765 0.17 367.025 12.9 ; + RECT 365.755 118.025 365.955 118.755 ; + RECT 366.255 118.025 366.455 118.755 ; + RECT 366.75 118.025 366.95 118.755 ; + RECT 367.275 0.52 367.535 5.815 ; + RECT 368.13 0.52 368.39 5.16 ; + RECT 368.13 4.9 368.91 5.16 ; + RECT 368.65 4.9 368.91 6.64 ; + RECT 367.57 118.025 367.77 118.755 ; + RECT 368.065 118.025 368.265 118.755 ; + RECT 368.565 118.025 368.765 118.755 ; + RECT 369.065 118.025 369.265 118.755 ; + RECT 369.56 118.025 369.76 118.755 ; + RECT 370.38 118.025 370.58 118.755 ; + RECT 370.875 118.025 371.075 118.755 ; + RECT 371.375 118.025 371.575 118.755 ; + RECT 371.53 0.52 371.79 2.335 ; + RECT 371.875 118.025 372.075 118.755 ; + RECT 372.04 0.52 372.3 14.11 ; + RECT 372.37 118.025 372.57 118.755 ; + RECT 373.415 0.17 374.185 0.94 ; + RECT 373.925 0.17 374.185 8.7 ; + RECT 373.415 0.17 373.675 12.9 ; + RECT 372.905 0.52 373.165 2.485 ; + RECT 373.19 118.025 373.39 118.755 ; + RECT 374.435 0.17 375.205 0.43 ; + RECT 374.945 0.17 375.205 10.48 ; + RECT 374.435 0.17 374.695 10.99 ; + RECT 373.685 118.025 373.885 118.755 ; + RECT 374.185 118.025 374.385 118.755 ; + RECT 374.685 118.025 374.885 118.755 ; + RECT 375.18 118.025 375.38 118.755 ; + RECT 376.475 0.17 377.245 0.43 ; + RECT 376.475 0.17 376.735 11.5 ; + RECT 376.985 0.17 377.245 11.5 ; + RECT 376 118.025 376.2 118.755 ; + RECT 376.495 118.025 376.695 118.755 ; + RECT 377.495 0.17 378.265 0.94 ; + RECT 377.495 0.17 377.755 12.9 ; + RECT 378.005 0.17 378.265 12.9 ; + RECT 376.995 118.025 377.195 118.755 ; + RECT 377.495 118.025 377.695 118.755 ; + RECT 377.99 118.025 378.19 118.755 ; + RECT 378.515 0.52 378.775 5.815 ; + RECT 379.37 0.52 379.63 5.16 ; + RECT 379.37 4.9 380.15 5.16 ; + RECT 379.89 4.9 380.15 6.64 ; + RECT 378.81 118.025 379.01 118.755 ; + RECT 379.305 118.025 379.505 118.755 ; + RECT 379.805 118.025 380.005 118.755 ; + RECT 380.305 118.025 380.505 118.755 ; + RECT 380.8 118.025 381 118.755 ; + RECT 381.62 118.025 381.82 118.755 ; + RECT 382.115 118.025 382.315 118.755 ; + RECT 382.615 118.025 382.815 118.755 ; + RECT 382.77 0.52 383.03 2.335 ; + RECT 383.115 118.025 383.315 118.755 ; + RECT 383.28 0.52 383.54 14.11 ; + RECT 383.61 118.025 383.81 118.755 ; + RECT 384.655 0.17 385.425 0.94 ; + RECT 385.165 0.17 385.425 8.7 ; + RECT 384.655 0.17 384.915 12.9 ; + RECT 384.145 0.52 384.405 2.485 ; + RECT 384.43 118.025 384.63 118.755 ; + RECT 385.675 0.17 386.445 0.43 ; + RECT 386.185 0.17 386.445 10.48 ; + RECT 385.675 0.17 385.935 10.99 ; + RECT 384.925 118.025 385.125 118.755 ; + RECT 385.425 118.025 385.625 118.755 ; + RECT 385.925 118.025 386.125 118.755 ; + RECT 386.42 118.025 386.62 118.755 ; + RECT 387.715 0.17 388.485 0.43 ; + RECT 387.715 0.17 387.975 11.5 ; + RECT 388.225 0.17 388.485 11.5 ; + RECT 387.24 118.025 387.44 118.755 ; + RECT 387.735 118.025 387.935 118.755 ; + RECT 388.735 0.17 389.505 0.94 ; + RECT 388.735 0.17 388.995 12.9 ; + RECT 389.245 0.17 389.505 12.9 ; + RECT 388.235 118.025 388.435 118.755 ; + RECT 388.735 118.025 388.935 118.755 ; + RECT 389.23 118.025 389.43 118.755 ; + RECT 389.755 0.52 390.015 5.815 ; + RECT 390.61 0.52 390.87 5.16 ; + RECT 390.61 4.9 391.39 5.16 ; + RECT 391.13 4.9 391.39 6.64 ; + RECT 390.05 118.025 390.25 118.755 ; + RECT 390.545 118.025 390.745 118.755 ; + RECT 391.045 118.025 391.245 118.755 ; + RECT 391.545 118.025 391.745 118.755 ; + RECT 392.04 118.025 392.24 118.755 ; + RECT 392.86 118.025 393.06 118.755 ; + RECT 393.355 118.025 393.555 118.755 ; + RECT 393.855 118.025 394.055 118.755 ; + RECT 394.01 0.52 394.27 2.335 ; + RECT 394.355 118.025 394.555 118.755 ; + RECT 394.52 0.52 394.78 14.11 ; + RECT 394.85 118.025 395.05 118.755 ; + RECT 395.895 0.17 396.665 0.94 ; + RECT 396.405 0.17 396.665 8.7 ; + RECT 395.895 0.17 396.155 12.9 ; + RECT 395.385 0.52 395.645 2.485 ; + RECT 395.67 118.025 395.87 118.755 ; + RECT 396.915 0.17 397.685 0.43 ; + RECT 397.425 0.17 397.685 10.48 ; + RECT 396.915 0.17 397.175 10.99 ; + RECT 396.165 118.025 396.365 118.755 ; + RECT 396.665 118.025 396.865 118.755 ; + RECT 397.165 118.025 397.365 118.755 ; + RECT 397.66 118.025 397.86 118.755 ; + RECT 398.955 0.17 399.725 0.43 ; + RECT 398.955 0.17 399.215 11.5 ; + RECT 399.465 0.17 399.725 11.5 ; + RECT 398.48 118.025 398.68 118.755 ; + RECT 398.975 118.025 399.175 118.755 ; + RECT 399.975 0.17 400.745 0.94 ; + RECT 399.975 0.17 400.235 12.9 ; + RECT 400.485 0.17 400.745 12.9 ; + RECT 399.475 118.025 399.675 118.755 ; + RECT 399.975 118.025 400.175 118.755 ; + RECT 400.47 118.025 400.67 118.755 ; + RECT 400.995 0.52 401.255 5.815 ; + RECT 401.85 0.52 402.11 5.16 ; + RECT 401.85 4.9 402.63 5.16 ; + RECT 402.37 4.9 402.63 6.64 ; + RECT 401.29 118.025 401.49 118.755 ; + RECT 401.785 118.025 401.985 118.755 ; + RECT 402.285 118.025 402.485 118.755 ; + RECT 402.785 118.025 402.985 118.755 ; + RECT 403.28 118.025 403.48 118.755 ; + RECT 404.1 118.025 404.3 118.755 ; + RECT 404.595 118.025 404.795 118.755 ; + RECT 405.095 118.025 405.295 118.755 ; + RECT 405.25 0.52 405.51 2.335 ; + RECT 405.595 118.025 405.795 118.755 ; + RECT 405.76 0.52 406.02 14.11 ; + RECT 406.09 118.025 406.29 118.755 ; + RECT 407.135 0.17 407.905 0.94 ; + RECT 407.645 0.17 407.905 8.7 ; + RECT 407.135 0.17 407.395 12.9 ; + RECT 406.625 0.52 406.885 2.485 ; + RECT 406.91 118.025 407.11 118.755 ; + RECT 408.155 0.17 408.925 0.43 ; + RECT 408.665 0.17 408.925 10.48 ; + RECT 408.155 0.17 408.415 10.99 ; + RECT 407.405 118.025 407.605 118.755 ; + RECT 407.905 118.025 408.105 118.755 ; + RECT 408.405 118.025 408.605 118.755 ; + RECT 408.9 118.025 409.1 118.755 ; + RECT 410.195 0.17 410.965 0.43 ; + RECT 410.195 0.17 410.455 11.5 ; + RECT 410.705 0.17 410.965 11.5 ; + RECT 409.72 118.025 409.92 118.755 ; + RECT 410.215 118.025 410.415 118.755 ; + RECT 411.215 0.17 411.985 0.94 ; + RECT 411.215 0.17 411.475 12.9 ; + RECT 411.725 0.17 411.985 12.9 ; + RECT 410.715 118.025 410.915 118.755 ; + RECT 411.215 118.025 411.415 118.755 ; + RECT 411.71 118.025 411.91 118.755 ; + RECT 412.235 0.52 412.495 5.815 ; + RECT 413.09 0.52 413.35 5.16 ; + RECT 413.09 4.9 413.87 5.16 ; + RECT 413.61 4.9 413.87 6.64 ; + RECT 412.53 118.025 412.73 118.755 ; + RECT 413.025 118.025 413.225 118.755 ; + RECT 413.525 118.025 413.725 118.755 ; + RECT 414.025 118.025 414.225 118.755 ; + RECT 414.52 118.025 414.72 118.755 ; + RECT 415.34 118.025 415.54 118.755 ; + RECT 416.335 45.465 416.535 118.755 ; + LAYER Metal2 SPACING 0.21 ; + RECT 194.32 0 200.69 118.78 ; + RECT 209.63 0 210.89 118.78 ; + RECT 238.545 0 243.375 118.78 ; + RECT 249.785 0 254.615 118.78 ; + RECT 261.025 0 265.855 118.78 ; + RECT 272.265 0 277.095 118.78 ; + RECT 283.505 0 288.335 118.78 ; + RECT 294.745 0 299.575 118.78 ; + RECT 305.985 0 310.815 118.78 ; + RECT 317.225 0 322.055 118.78 ; + RECT 328.465 0 333.295 118.78 ; + RECT 339.705 0 344.535 118.78 ; + RECT 350.945 0 355.775 118.78 ; + RECT 362.185 0 367.015 118.78 ; + RECT 373.425 0 378.255 118.78 ; + RECT 384.665 0 389.495 118.78 ; + RECT 395.905 0 400.735 118.78 ; + RECT 407.145 0 411.975 118.78 ; + RECT 201.98 0 202.22 118.78 ; + RECT 203.51 0 203.75 118.78 ; + RECT 206.57 0 206.81 118.78 ; + RECT 208.1 0 208.34 118.78 ; + RECT 215.23 0 224.15 118.78 ; + RECT 0 0 3.03 118.78 ; + RECT 4.655 0.17 9.505 118.78 ; + RECT 11.65 0 14.27 118.78 ; + RECT 15.895 0.17 20.745 118.78 ; + RECT 22.89 0 25.51 118.78 ; + RECT 27.135 0.17 31.985 118.78 ; + RECT 34.13 0 36.75 118.78 ; + RECT 38.375 0.17 43.225 118.78 ; + RECT 45.37 0 47.99 118.78 ; + RECT 49.615 0.17 54.465 118.78 ; + RECT 56.61 0 59.23 118.78 ; + RECT 60.855 0.17 65.705 118.78 ; + RECT 67.85 0 70.47 118.78 ; + RECT 72.095 0.17 76.945 118.78 ; + RECT 79.09 0 81.71 118.78 ; + RECT 83.335 0.17 88.185 118.78 ; + RECT 90.33 0 92.95 118.78 ; + RECT 94.575 0.17 99.425 118.78 ; + RECT 101.57 0 104.19 118.78 ; + RECT 105.815 0.17 110.665 118.78 ; + RECT 112.81 0 115.43 118.78 ; + RECT 117.055 0.17 121.905 118.78 ; + RECT 124.05 0 126.67 118.78 ; + RECT 128.295 0.17 133.145 118.78 ; + RECT 135.29 0 137.91 118.78 ; + RECT 139.535 0.17 144.385 118.78 ; + RECT 146.53 0 149.15 118.78 ; + RECT 150.775 0.17 155.625 118.78 ; + RECT 157.77 0 160.39 118.78 ; + RECT 162.015 0.17 166.865 118.78 ; + RECT 169.01 0 171.63 118.78 ; + RECT 173.255 0.17 178.105 118.78 ; + RECT 180.25 0 192.03 118.78 ; + RECT 194.32 0.17 200.7 118.78 ; + RECT 201.97 0.3 202.23 118.78 ; + RECT 203.5 0.3 203.76 118.78 ; + RECT 206.56 0.3 206.82 118.78 ; + RECT 208.09 0.3 208.35 118.78 ; + RECT 209.63 0.17 210.9 118.78 ; + RECT 209.62 0.3 210.9 118.78 ; + RECT 215.23 0.3 224.16 118.78 ; + RECT 224.93 0 236.39 118.78 ; + RECT 224.92 0.17 236.39 118.78 ; + RECT 238.535 0.17 243.385 118.78 ; + RECT 245.01 0 247.63 118.78 ; + RECT 249.775 0.17 254.625 118.78 ; + RECT 256.25 0 258.87 118.78 ; + RECT 261.015 0.17 265.865 118.78 ; + RECT 267.49 0 270.11 118.78 ; + RECT 272.255 0.17 277.105 118.78 ; + RECT 278.73 0 281.35 118.78 ; + RECT 283.495 0.17 288.345 118.78 ; + RECT 289.97 0 292.59 118.78 ; + RECT 294.735 0.17 299.585 118.78 ; + RECT 301.21 0 303.83 118.78 ; + RECT 305.975 0.17 310.825 118.78 ; + RECT 312.45 0 315.07 118.78 ; + RECT 317.215 0.17 322.065 118.78 ; + RECT 323.69 0 326.31 118.78 ; + RECT 328.455 0.17 333.305 118.78 ; + RECT 334.93 0 337.55 118.78 ; + RECT 339.695 0.17 344.545 118.78 ; + RECT 346.17 0 348.79 118.78 ; + RECT 350.935 0.17 355.785 118.78 ; + RECT 357.41 0 360.03 118.78 ; + RECT 362.175 0.17 367.025 118.78 ; + RECT 368.65 0 371.27 118.78 ; + RECT 373.415 0.17 378.265 118.78 ; + RECT 379.89 0 382.51 118.78 ; + RECT 384.655 0.17 389.505 118.78 ; + RECT 391.13 0 393.75 118.78 ; + RECT 395.895 0.17 400.745 118.78 ; + RECT 402.37 0 404.99 118.78 ; + RECT 407.135 0.17 411.985 118.78 ; + RECT 413.61 0 416.64 118.78 ; + RECT 0 0.52 416.64 118.78 ; + RECT 4.665 0 9.495 118.78 ; + RECT 15.905 0 20.735 118.78 ; + RECT 27.145 0 31.975 118.78 ; + RECT 38.385 0 43.215 118.78 ; + RECT 49.625 0 54.455 118.78 ; + RECT 60.865 0 65.695 118.78 ; + RECT 72.105 0 76.935 118.78 ; + RECT 83.345 0 88.175 118.78 ; + RECT 94.585 0 99.415 118.78 ; + RECT 105.825 0 110.655 118.78 ; + RECT 117.065 0 121.895 118.78 ; + RECT 128.305 0 133.135 118.78 ; + RECT 139.545 0 144.375 118.78 ; + RECT 150.785 0 155.615 118.78 ; + RECT 162.025 0 166.855 118.78 ; + RECT 173.265 0 178.095 118.78 ; + LAYER Metal3 ; + RECT 0 0 416.64 118.78 ; + LAYER Metal4 SPACING 0.21 ; + RECT 0 39.085 9.62 45.205 ; + RECT 0 0 4 118.78 ; + RECT 7.33 0 9.62 118.78 ; + RECT 12.95 39.085 20.86 45.205 ; + RECT 12.95 0 15.24 118.78 ; + RECT 18.57 0 20.86 118.78 ; + RECT 24.19 39.085 32.1 45.205 ; + RECT 24.19 0 26.48 118.78 ; + RECT 29.81 0 32.1 118.78 ; + RECT 35.43 39.085 43.34 45.205 ; + RECT 35.43 0 37.72 118.78 ; + RECT 41.05 0 43.34 118.78 ; + RECT 46.67 39.085 54.58 45.205 ; + RECT 46.67 0 48.96 118.78 ; + RECT 52.29 0 54.58 118.78 ; + RECT 57.91 39.085 65.82 45.205 ; + RECT 57.91 0 60.2 118.78 ; + RECT 63.53 0 65.82 118.78 ; + RECT 69.15 39.085 77.06 45.205 ; + RECT 69.15 0 71.44 118.78 ; + RECT 74.77 0 77.06 118.78 ; + RECT 80.39 39.085 88.3 45.205 ; + RECT 80.39 0 82.68 118.78 ; + RECT 86.01 0 88.3 118.78 ; + RECT 91.63 39.085 99.54 45.205 ; + RECT 91.63 0 93.92 118.78 ; + RECT 97.25 0 99.54 118.78 ; + RECT 102.87 39.085 110.78 45.205 ; + RECT 102.87 0 105.16 118.78 ; + RECT 108.49 0 110.78 118.78 ; + RECT 114.11 39.085 122.02 45.205 ; + RECT 114.11 0 116.4 118.78 ; + RECT 119.73 0 122.02 118.78 ; + RECT 125.35 39.085 133.26 45.205 ; + RECT 125.35 0 127.64 118.78 ; + RECT 130.97 0 133.26 118.78 ; + RECT 136.59 39.085 144.5 45.205 ; + RECT 136.59 0 138.88 118.78 ; + RECT 142.21 0 144.5 118.78 ; + RECT 147.83 39.085 155.74 45.205 ; + RECT 147.83 0 150.12 118.78 ; + RECT 153.45 0 155.74 118.78 ; + RECT 159.07 39.085 166.98 45.205 ; + RECT 159.07 0 161.36 118.78 ; + RECT 164.69 0 166.98 118.78 ; + RECT 170.31 39.085 178.22 45.205 ; + RECT 170.31 0 172.6 118.78 ; + RECT 175.93 0 178.22 118.78 ; + RECT 181.55 0 188.63 118.78 ; + RECT 191.96 0 193.78 118.78 ; + RECT 197.11 0 198.93 118.78 ; + RECT 202.26 0 204.08 118.78 ; + RECT 207.41 0 209.23 118.78 ; + RECT 212.56 0 214.38 118.78 ; + RECT 238.42 39.085 246.33 45.205 ; + RECT 238.42 0 240.71 118.78 ; + RECT 244.04 0 246.33 118.78 ; + RECT 249.66 39.085 257.57 45.205 ; + RECT 249.66 0 251.95 118.78 ; + RECT 255.28 0 257.57 118.78 ; + RECT 260.9 39.085 268.81 45.205 ; + RECT 260.9 0 263.19 118.78 ; + RECT 266.52 0 268.81 118.78 ; + RECT 272.14 39.085 280.05 45.205 ; + RECT 272.14 0 274.43 118.78 ; + RECT 277.76 0 280.05 118.78 ; + RECT 283.38 39.085 291.29 45.205 ; + RECT 283.38 0 285.67 118.78 ; + RECT 289 0 291.29 118.78 ; + RECT 294.62 39.085 302.53 45.205 ; + RECT 294.62 0 296.91 118.78 ; + RECT 300.24 0 302.53 118.78 ; + RECT 305.86 39.085 313.77 45.205 ; + RECT 305.86 0 308.15 118.78 ; + RECT 311.48 0 313.77 118.78 ; + RECT 317.1 39.085 325.01 45.205 ; + RECT 317.1 0 319.39 118.78 ; + RECT 322.72 0 325.01 118.78 ; + RECT 328.34 39.085 336.25 45.205 ; + RECT 328.34 0 330.63 118.78 ; + RECT 333.96 0 336.25 118.78 ; + RECT 339.58 39.085 347.49 45.205 ; + RECT 339.58 0 341.87 118.78 ; + RECT 345.2 0 347.49 118.78 ; + RECT 350.82 39.085 358.73 45.205 ; + RECT 350.82 0 353.11 118.78 ; + RECT 356.44 0 358.73 118.78 ; + RECT 362.06 39.085 369.97 45.205 ; + RECT 362.06 0 364.35 118.78 ; + RECT 367.68 0 369.97 118.78 ; + RECT 373.3 39.085 381.21 45.205 ; + RECT 373.3 0 375.59 118.78 ; + RECT 378.92 0 381.21 118.78 ; + RECT 384.54 39.085 392.45 45.205 ; + RECT 384.54 0 386.83 118.78 ; + RECT 390.16 0 392.45 118.78 ; + RECT 395.78 39.085 403.69 45.205 ; + RECT 395.78 0 398.07 118.78 ; + RECT 401.4 0 403.69 118.78 ; + RECT 407.02 39.085 416.64 45.205 ; + RECT 407.02 0 409.31 118.78 ; + RECT 412.64 0 416.64 118.78 ; + RECT 217.71 0 219.53 118.78 ; + RECT 222.86 0 224.68 118.78 ; + RECT 228.01 0 235.09 118.78 ; + END +END RM_IHPSG13_1P_256x32_c2_bm_bist + +END LIBRARY diff --git a/flow/platforms/ihp-sg13g2/lef/RM_IHPSG13_1P_256x8_c3_bm_bist.lef b/flow/platforms/ihp-sg13g2/lef/RM_IHPSG13_1P_256x8_c3_bm_bist.lef new file mode 100644 index 0000000000..d8a5729669 --- /dev/null +++ b/flow/platforms/ihp-sg13g2/lef/RM_IHPSG13_1P_256x8_c3_bm_bist.lef @@ -0,0 +1,1670 @@ +# ------------------------------------------------------ +# +# Copyright 2025 IHP PDK Authors +# +# Licensed under the Apache License, Version 2.0 (the "License"); +# you may not use this file except in compliance with the License. +# You may obtain a copy of the License at +# +# https://www.apache.org/licenses/LICENSE-2.0 +# +# Unless required by applicable law or agreed to in writing, software +# distributed under the License is distributed on an "AS IS" BASIS, +# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +# See the License for the specific language governing permissions and +# limitations under the License. +# +# Generated on Wed Aug 27 16:22:45 2025 +# +# ------------------------------------------------------ +VERSION 5.7 ; +BUSBITCHARS "[]" ; +DIVIDERCHAR "/" ; + +MACRO RM_IHPSG13_1P_256x8_c3_bm_bist + CLASS BLOCK ; + ORIGIN 0 0 ; + FOREIGN RM_IHPSG13_1P_256x8_c3_bm_bist 0 0 ; + SIZE 236.8 BY 74.1 ; + SYMMETRY X Y R90 ; + PIN A_DIN[4] + DIRECTION INPUT ; + USE SIGNAL ; + ANTENNAPARTIALMETALAREA 0.7007 LAYER Metal2 ; + ANTENNAMODEL OXIDE1 ; + ANTENNAGATEAREA 0.20085 LAYER Metal2 ; + ANTENNAMAXAREACAR 4.394822 LAYER Metal2 ; + PORT + LAYER Metal2 ; + RECT 155.09 0 155.35 0.26 ; + END + END A_DIN[4] + PIN A_DIN[3] + DIRECTION INPUT ; + USE SIGNAL ; + ANTENNAPARTIALMETALAREA 0.7007 LAYER Metal2 ; + ANTENNAMODEL OXIDE1 ; + ANTENNAGATEAREA 0.20085 LAYER Metal2 ; + ANTENNAMAXAREACAR 4.394822 LAYER Metal2 ; + PORT + LAYER Metal2 ; + RECT 81.45 0 81.71 0.26 ; + END + END A_DIN[3] + PIN A_BIST_DIN[4] + DIRECTION INPUT ; + USE SIGNAL ; + ANTENNAPARTIALMETALAREA 0.7007 LAYER Metal2 ; + ANTENNAMODEL OXIDE1 ; + ANTENNAGATEAREA 0.20085 LAYER Metal2 ; + ANTENNAMAXAREACAR 4.394822 LAYER Metal2 ; + PORT + LAYER Metal2 ; + RECT 153.56 0 153.82 0.26 ; + END + END A_BIST_DIN[4] + PIN A_BIST_DIN[3] + DIRECTION INPUT ; + USE SIGNAL ; + ANTENNAPARTIALMETALAREA 0.7007 LAYER Metal2 ; + ANTENNAMODEL OXIDE1 ; + ANTENNAGATEAREA 0.20085 LAYER Metal2 ; + ANTENNAMAXAREACAR 4.394822 LAYER Metal2 ; + PORT + LAYER Metal2 ; + RECT 82.98 0 83.24 0.26 ; + END + END A_BIST_DIN[3] + PIN A_BM[4] + DIRECTION INPUT ; + USE SIGNAL ; + ANTENNAPARTIALMETALAREA 0.7007 LAYER Metal2 ; + ANTENNAMODEL OXIDE1 ; + ANTENNAGATEAREA 0.20085 LAYER Metal2 ; + ANTENNAMAXAREACAR 4.394822 LAYER Metal2 ; + PORT + LAYER Metal2 ; + RECT 158.97 0 159.23 0.26 ; + END + END A_BM[4] + PIN A_BM[3] + DIRECTION INPUT ; + USE SIGNAL ; + ANTENNAPARTIALMETALAREA 0.7007 LAYER Metal2 ; + ANTENNAMODEL OXIDE1 ; + ANTENNAGATEAREA 0.20085 LAYER Metal2 ; + ANTENNAMAXAREACAR 4.394822 LAYER Metal2 ; + PORT + LAYER Metal2 ; + RECT 77.57 0 77.83 0.26 ; + END + END A_BM[3] + PIN A_BIST_BM[4] + DIRECTION INPUT ; + USE SIGNAL ; + ANTENNAPARTIALMETALAREA 0.7007 LAYER Metal2 ; + ANTENNAMODEL OXIDE1 ; + ANTENNAGATEAREA 0.20085 LAYER Metal2 ; + ANTENNAMAXAREACAR 4.394822 LAYER Metal2 ; + PORT + LAYER Metal2 ; + RECT 160.5 0 160.76 0.26 ; + END + END A_BIST_BM[4] + PIN A_BIST_BM[3] + DIRECTION INPUT ; + USE SIGNAL ; + ANTENNAPARTIALMETALAREA 0.7007 LAYER Metal2 ; + ANTENNAMODEL OXIDE1 ; + ANTENNAGATEAREA 0.20085 LAYER Metal2 ; + ANTENNAMAXAREACAR 4.394822 LAYER Metal2 ; + PORT + LAYER Metal2 ; + RECT 76.04 0 76.3 0.26 ; + END + END A_BIST_BM[3] + PIN A_DOUT[4] + DIRECTION OUTPUT ; + USE SIGNAL ; + ANTENNAPARTIALMETALAREA 2.0345 LAYER Metal2 ; + ANTENNADIFFAREA 0.988 LAYER Metal2 ; + PORT + LAYER Metal2 ; + RECT 159.835 0 160.095 0.26 ; + END + END A_DOUT[4] + PIN A_DOUT[3] + DIRECTION OUTPUT ; + USE SIGNAL ; + ANTENNAPARTIALMETALAREA 2.0345 LAYER Metal2 ; + ANTENNADIFFAREA 0.988 LAYER Metal2 ; + PORT + LAYER Metal2 ; + RECT 76.705 0 76.965 0.26 ; + END + END A_DOUT[3] + PIN VSS! + DIRECTION INOUT ; + USE GROUND ; + NETEXPR "vss VSS!" ; + PORT + LAYER Metal4 ; + RECT 224.11 0 226.92 74.1 ; + END + PORT + LAYER Metal4 ; + RECT 212.87 0 215.68 74.1 ; + END + PORT + LAYER Metal4 ; + RECT 201.63 0 204.44 74.1 ; + END + PORT + LAYER Metal4 ; + RECT 190.39 0 193.2 74.1 ; + END + PORT + LAYER Metal4 ; + RECT 179.15 0 181.96 74.1 ; + END + PORT + LAYER Metal4 ; + RECT 167.91 0 170.72 74.1 ; + END + PORT + LAYER Metal4 ; + RECT 156.67 0 159.48 74.1 ; + END + PORT + LAYER Metal4 ; + RECT 145.43 0 148.24 74.1 ; + END + PORT + LAYER Metal4 ; + RECT 135.02 0 137.83 74.1 ; + END + PORT + LAYER Metal4 ; + RECT 124.72 0 127.53 74.1 ; + END + PORT + LAYER Metal4 ; + RECT 109.27 0 112.08 74.1 ; + END + PORT + LAYER Metal4 ; + RECT 98.97 0 101.78 74.1 ; + END + PORT + LAYER Metal4 ; + RECT 88.56 0 91.37 74.1 ; + END + PORT + LAYER Metal4 ; + RECT 77.32 0 80.13 74.1 ; + END + PORT + LAYER Metal4 ; + RECT 66.08 0 68.89 74.1 ; + END + PORT + LAYER Metal4 ; + RECT 54.84 0 57.65 74.1 ; + END + PORT + LAYER Metal4 ; + RECT 43.6 0 46.41 74.1 ; + END + PORT + LAYER Metal4 ; + RECT 32.36 0 35.17 74.1 ; + END + PORT + LAYER Metal4 ; + RECT 21.12 0 23.93 74.1 ; + END + PORT + LAYER Metal4 ; + RECT 9.88 0 12.69 74.1 ; + END + END VSS! + PIN VDD! + DIRECTION INOUT ; + USE POWER ; + NETEXPR "vdd VDD!" ; + PORT + LAYER Metal4 ; + RECT 229.73 0 232.54 30.425 ; + END + PORT + LAYER Metal4 ; + RECT 218.49 0 221.3 30.425 ; + END + PORT + LAYER Metal4 ; + RECT 207.25 0 210.06 30.425 ; + END + PORT + LAYER Metal4 ; + RECT 196.01 0 198.82 30.425 ; + END + PORT + LAYER Metal4 ; + RECT 184.77 0 187.58 30.425 ; + END + PORT + LAYER Metal4 ; + RECT 173.53 0 176.34 30.425 ; + END + PORT + LAYER Metal4 ; + RECT 162.29 0 165.1 30.425 ; + END + PORT + LAYER Metal4 ; + RECT 151.05 0 153.86 30.425 ; + END + PORT + LAYER Metal4 ; + RECT 129.87 0 132.68 74.1 ; + END + PORT + LAYER Metal4 ; + RECT 119.57 0 122.38 74.1 ; + END + PORT + LAYER Metal4 ; + RECT 114.42 0 117.23 74.1 ; + END + PORT + LAYER Metal4 ; + RECT 104.12 0 106.93 74.1 ; + END + PORT + LAYER Metal4 ; + RECT 82.94 0 85.75 30.425 ; + END + PORT + LAYER Metal4 ; + RECT 71.7 0 74.51 30.425 ; + END + PORT + LAYER Metal4 ; + RECT 60.46 0 63.27 30.425 ; + END + PORT + LAYER Metal4 ; + RECT 49.22 0 52.03 30.425 ; + END + PORT + LAYER Metal4 ; + RECT 37.98 0 40.79 30.425 ; + END + PORT + LAYER Metal4 ; + RECT 26.74 0 29.55 30.425 ; + END + PORT + LAYER Metal4 ; + RECT 15.5 0 18.31 30.425 ; + END + PORT + LAYER Metal4 ; + RECT 4.26 0 7.07 30.425 ; + END + END VDD! + PIN VDDARRAY! + DIRECTION INOUT ; + USE POWER ; + NETEXPR "vddarray VDDARRAY!" ; + PORT + LAYER Metal4 ; + RECT 229.73 37.065 232.54 74.1 ; + END + PORT + LAYER Metal4 ; + RECT 218.49 37.065 221.3 74.1 ; + END + PORT + LAYER Metal4 ; + RECT 207.25 37.065 210.06 74.1 ; + END + PORT + LAYER Metal4 ; + RECT 196.01 37.065 198.82 74.1 ; + END + PORT + LAYER Metal4 ; + RECT 184.77 37.065 187.58 74.1 ; + END + PORT + LAYER Metal4 ; + RECT 173.53 37.065 176.34 74.1 ; + END + PORT + LAYER Metal4 ; + RECT 162.29 37.065 165.1 74.1 ; + END + PORT + LAYER Metal4 ; + RECT 151.05 37.065 153.86 74.1 ; + END + PORT + LAYER Metal4 ; + RECT 82.94 37.065 85.75 74.1 ; + END + PORT + LAYER Metal4 ; + RECT 71.7 37.065 74.51 74.1 ; + END + PORT + LAYER Metal4 ; + RECT 60.46 37.065 63.27 74.1 ; + END + PORT + LAYER Metal4 ; + RECT 49.22 37.065 52.03 74.1 ; + END + PORT + LAYER Metal4 ; + RECT 37.98 37.065 40.79 74.1 ; + END + PORT + LAYER Metal4 ; + RECT 26.74 37.065 29.55 74.1 ; + END + PORT + LAYER Metal4 ; + RECT 15.5 37.065 18.31 74.1 ; + END + PORT + LAYER Metal4 ; + RECT 4.26 37.065 7.07 74.1 ; + END + END VDDARRAY! + PIN A_DIN[5] + DIRECTION INPUT ; + USE SIGNAL ; + ANTENNAPARTIALMETALAREA 0.7007 LAYER Metal2 ; + ANTENNAMODEL OXIDE1 ; + ANTENNAGATEAREA 0.20085 LAYER Metal2 ; + ANTENNAMAXAREACAR 4.394822 LAYER Metal2 ; + PORT + LAYER Metal2 ; + RECT 177.57 0 177.83 0.26 ; + END + END A_DIN[5] + PIN A_DIN[2] + DIRECTION INPUT ; + USE SIGNAL ; + ANTENNAPARTIALMETALAREA 0.7007 LAYER Metal2 ; + ANTENNAMODEL OXIDE1 ; + ANTENNAGATEAREA 0.20085 LAYER Metal2 ; + ANTENNAMAXAREACAR 4.394822 LAYER Metal2 ; + PORT + LAYER Metal2 ; + RECT 58.97 0 59.23 0.26 ; + END + END A_DIN[2] + PIN A_BIST_DIN[5] + DIRECTION INPUT ; + USE SIGNAL ; + ANTENNAPARTIALMETALAREA 0.7007 LAYER Metal2 ; + ANTENNAMODEL OXIDE1 ; + ANTENNAGATEAREA 0.20085 LAYER Metal2 ; + ANTENNAMAXAREACAR 4.394822 LAYER Metal2 ; + PORT + LAYER Metal2 ; + RECT 176.04 0 176.3 0.26 ; + END + END A_BIST_DIN[5] + PIN A_BIST_DIN[2] + DIRECTION INPUT ; + USE SIGNAL ; + ANTENNAPARTIALMETALAREA 0.7007 LAYER Metal2 ; + ANTENNAMODEL OXIDE1 ; + ANTENNAGATEAREA 0.20085 LAYER Metal2 ; + ANTENNAMAXAREACAR 4.394822 LAYER Metal2 ; + PORT + LAYER Metal2 ; + RECT 60.5 0 60.76 0.26 ; + END + END A_BIST_DIN[2] + PIN A_BM[5] + DIRECTION INPUT ; + USE SIGNAL ; + ANTENNAPARTIALMETALAREA 0.7007 LAYER Metal2 ; + ANTENNAMODEL OXIDE1 ; + ANTENNAGATEAREA 0.20085 LAYER Metal2 ; + ANTENNAMAXAREACAR 4.394822 LAYER Metal2 ; + PORT + LAYER Metal2 ; + RECT 181.45 0 181.71 0.26 ; + END + END A_BM[5] + PIN A_BM[2] + DIRECTION INPUT ; + USE SIGNAL ; + ANTENNAPARTIALMETALAREA 0.7007 LAYER Metal2 ; + ANTENNAMODEL OXIDE1 ; + ANTENNAGATEAREA 0.20085 LAYER Metal2 ; + ANTENNAMAXAREACAR 4.394822 LAYER Metal2 ; + PORT + LAYER Metal2 ; + RECT 55.09 0 55.35 0.26 ; + END + END A_BM[2] + PIN A_BIST_BM[5] + DIRECTION INPUT ; + USE SIGNAL ; + ANTENNAPARTIALMETALAREA 0.7007 LAYER Metal2 ; + ANTENNAMODEL OXIDE1 ; + ANTENNAGATEAREA 0.20085 LAYER Metal2 ; + ANTENNAMAXAREACAR 4.394822 LAYER Metal2 ; + PORT + LAYER Metal2 ; + RECT 182.98 0 183.24 0.26 ; + END + END A_BIST_BM[5] + PIN A_BIST_BM[2] + DIRECTION INPUT ; + USE SIGNAL ; + ANTENNAPARTIALMETALAREA 0.7007 LAYER Metal2 ; + ANTENNAMODEL OXIDE1 ; + ANTENNAGATEAREA 0.20085 LAYER Metal2 ; + ANTENNAMAXAREACAR 4.394822 LAYER Metal2 ; + PORT + LAYER Metal2 ; + RECT 53.56 0 53.82 0.26 ; + END + END A_BIST_BM[2] + PIN A_DOUT[5] + DIRECTION OUTPUT ; + USE SIGNAL ; + ANTENNAPARTIALMETALAREA 2.0345 LAYER Metal2 ; + ANTENNADIFFAREA 0.988 LAYER Metal2 ; + PORT + LAYER Metal2 ; + RECT 182.315 0 182.575 0.26 ; + END + END A_DOUT[5] + PIN A_DOUT[2] + DIRECTION OUTPUT ; + USE SIGNAL ; + ANTENNAPARTIALMETALAREA 2.0345 LAYER Metal2 ; + ANTENNADIFFAREA 0.988 LAYER Metal2 ; + PORT + LAYER Metal2 ; + RECT 54.225 0 54.485 0.26 ; + END + END A_DOUT[2] + PIN A_DIN[6] + DIRECTION INPUT ; + USE SIGNAL ; + ANTENNAPARTIALMETALAREA 0.7007 LAYER Metal2 ; + ANTENNAMODEL OXIDE1 ; + ANTENNAGATEAREA 0.20085 LAYER Metal2 ; + ANTENNAMAXAREACAR 4.394822 LAYER Metal2 ; + PORT + LAYER Metal2 ; + RECT 200.05 0 200.31 0.26 ; + END + END A_DIN[6] + PIN A_DIN[1] + DIRECTION INPUT ; + USE SIGNAL ; + ANTENNAPARTIALMETALAREA 0.7007 LAYER Metal2 ; + ANTENNAMODEL OXIDE1 ; + ANTENNAGATEAREA 0.20085 LAYER Metal2 ; + ANTENNAMAXAREACAR 4.394822 LAYER Metal2 ; + PORT + LAYER Metal2 ; + RECT 36.49 0 36.75 0.26 ; + END + END A_DIN[1] + PIN A_BIST_DIN[6] + DIRECTION INPUT ; + USE SIGNAL ; + ANTENNAPARTIALMETALAREA 0.7007 LAYER Metal2 ; + ANTENNAMODEL OXIDE1 ; + ANTENNAGATEAREA 0.20085 LAYER Metal2 ; + ANTENNAMAXAREACAR 4.394822 LAYER Metal2 ; + PORT + LAYER Metal2 ; + RECT 198.52 0 198.78 0.26 ; + END + END A_BIST_DIN[6] + PIN A_BIST_DIN[1] + DIRECTION INPUT ; + USE SIGNAL ; + ANTENNAPARTIALMETALAREA 0.7007 LAYER Metal2 ; + ANTENNAMODEL OXIDE1 ; + ANTENNAGATEAREA 0.20085 LAYER Metal2 ; + ANTENNAMAXAREACAR 4.394822 LAYER Metal2 ; + PORT + LAYER Metal2 ; + RECT 38.02 0 38.28 0.26 ; + END + END A_BIST_DIN[1] + PIN A_BM[6] + DIRECTION INPUT ; + USE SIGNAL ; + ANTENNAPARTIALMETALAREA 0.7007 LAYER Metal2 ; + ANTENNAMODEL OXIDE1 ; + ANTENNAGATEAREA 0.20085 LAYER Metal2 ; + ANTENNAMAXAREACAR 4.394822 LAYER Metal2 ; + PORT + LAYER Metal2 ; + RECT 203.93 0 204.19 0.26 ; + END + END A_BM[6] + PIN A_BM[1] + DIRECTION INPUT ; + USE SIGNAL ; + ANTENNAPARTIALMETALAREA 0.7007 LAYER Metal2 ; + ANTENNAMODEL OXIDE1 ; + ANTENNAGATEAREA 0.20085 LAYER Metal2 ; + ANTENNAMAXAREACAR 4.394822 LAYER Metal2 ; + PORT + LAYER Metal2 ; + RECT 32.61 0 32.87 0.26 ; + END + END A_BM[1] + PIN A_BIST_BM[6] + DIRECTION INPUT ; + USE SIGNAL ; + ANTENNAPARTIALMETALAREA 0.7007 LAYER Metal2 ; + ANTENNAMODEL OXIDE1 ; + ANTENNAGATEAREA 0.20085 LAYER Metal2 ; + ANTENNAMAXAREACAR 4.394822 LAYER Metal2 ; + PORT + LAYER Metal2 ; + RECT 205.46 0 205.72 0.26 ; + END + END A_BIST_BM[6] + PIN A_BIST_BM[1] + DIRECTION INPUT ; + USE SIGNAL ; + ANTENNAPARTIALMETALAREA 0.7007 LAYER Metal2 ; + ANTENNAMODEL OXIDE1 ; + ANTENNAGATEAREA 0.20085 LAYER Metal2 ; + ANTENNAMAXAREACAR 4.394822 LAYER Metal2 ; + PORT + LAYER Metal2 ; + RECT 31.08 0 31.34 0.26 ; + END + END A_BIST_BM[1] + PIN A_DOUT[6] + DIRECTION OUTPUT ; + USE SIGNAL ; + ANTENNAPARTIALMETALAREA 2.0345 LAYER Metal2 ; + ANTENNADIFFAREA 0.988 LAYER Metal2 ; + PORT + LAYER Metal2 ; + RECT 204.795 0 205.055 0.26 ; + END + END A_DOUT[6] + PIN A_DOUT[1] + DIRECTION OUTPUT ; + USE SIGNAL ; + ANTENNAPARTIALMETALAREA 2.0345 LAYER Metal2 ; + ANTENNADIFFAREA 0.988 LAYER Metal2 ; + PORT + LAYER Metal2 ; + RECT 31.745 0 32.005 0.26 ; + END + END A_DOUT[1] + PIN A_DIN[7] + DIRECTION INPUT ; + USE SIGNAL ; + ANTENNAPARTIALMETALAREA 0.7007 LAYER Metal2 ; + ANTENNAMODEL OXIDE1 ; + ANTENNAGATEAREA 0.20085 LAYER Metal2 ; + ANTENNAMAXAREACAR 4.394822 LAYER Metal2 ; + PORT + LAYER Metal2 ; + RECT 222.53 0 222.79 0.26 ; + END + END A_DIN[7] + PIN A_DIN[0] + DIRECTION INPUT ; + USE SIGNAL ; + ANTENNAPARTIALMETALAREA 0.7007 LAYER Metal2 ; + ANTENNAMODEL OXIDE1 ; + ANTENNAGATEAREA 0.20085 LAYER Metal2 ; + ANTENNAMAXAREACAR 4.394822 LAYER Metal2 ; + PORT + LAYER Metal2 ; + RECT 14.01 0 14.27 0.26 ; + END + END A_DIN[0] + PIN A_BIST_DIN[7] + DIRECTION INPUT ; + USE SIGNAL ; + ANTENNAPARTIALMETALAREA 0.7007 LAYER Metal2 ; + ANTENNAMODEL OXIDE1 ; + ANTENNAGATEAREA 0.20085 LAYER Metal2 ; + ANTENNAMAXAREACAR 4.394822 LAYER Metal2 ; + PORT + LAYER Metal2 ; + RECT 221 0 221.26 0.26 ; + END + END A_BIST_DIN[7] + PIN A_BIST_DIN[0] + DIRECTION INPUT ; + USE SIGNAL ; + ANTENNAPARTIALMETALAREA 0.7007 LAYER Metal2 ; + ANTENNAMODEL OXIDE1 ; + ANTENNAGATEAREA 0.20085 LAYER Metal2 ; + ANTENNAMAXAREACAR 4.394822 LAYER Metal2 ; + PORT + LAYER Metal2 ; + RECT 15.54 0 15.8 0.26 ; + END + END A_BIST_DIN[0] + PIN A_BM[7] + DIRECTION INPUT ; + USE SIGNAL ; + ANTENNAPARTIALMETALAREA 0.7007 LAYER Metal2 ; + ANTENNAMODEL OXIDE1 ; + ANTENNAGATEAREA 0.20085 LAYER Metal2 ; + ANTENNAMAXAREACAR 4.394822 LAYER Metal2 ; + PORT + LAYER Metal2 ; + RECT 226.41 0 226.67 0.26 ; + END + END A_BM[7] + PIN A_BM[0] + DIRECTION INPUT ; + USE SIGNAL ; + ANTENNAPARTIALMETALAREA 0.7007 LAYER Metal2 ; + ANTENNAMODEL OXIDE1 ; + ANTENNAGATEAREA 0.20085 LAYER Metal2 ; + ANTENNAMAXAREACAR 4.394822 LAYER Metal2 ; + PORT + LAYER Metal2 ; + RECT 10.13 0 10.39 0.26 ; + END + END A_BM[0] + PIN A_BIST_BM[7] + DIRECTION INPUT ; + USE SIGNAL ; + ANTENNAPARTIALMETALAREA 0.7007 LAYER Metal2 ; + ANTENNAMODEL OXIDE1 ; + ANTENNAGATEAREA 0.20085 LAYER Metal2 ; + ANTENNAMAXAREACAR 4.394822 LAYER Metal2 ; + PORT + LAYER Metal2 ; + RECT 227.94 0 228.2 0.26 ; + END + END A_BIST_BM[7] + PIN A_BIST_BM[0] + DIRECTION INPUT ; + USE SIGNAL ; + ANTENNAPARTIALMETALAREA 0.7007 LAYER Metal2 ; + ANTENNAMODEL OXIDE1 ; + ANTENNAGATEAREA 0.20085 LAYER Metal2 ; + ANTENNAMAXAREACAR 4.394822 LAYER Metal2 ; + PORT + LAYER Metal2 ; + RECT 8.6 0 8.86 0.26 ; + END + END A_BIST_BM[0] + PIN A_DOUT[7] + DIRECTION OUTPUT ; + USE SIGNAL ; + ANTENNAPARTIALMETALAREA 2.0345 LAYER Metal2 ; + ANTENNADIFFAREA 0.988 LAYER Metal2 ; + PORT + LAYER Metal2 ; + RECT 227.275 0 227.535 0.26 ; + END + END A_DOUT[7] + PIN A_DOUT[0] + DIRECTION OUTPUT ; + USE SIGNAL ; + ANTENNAPARTIALMETALAREA 2.0345 LAYER Metal2 ; + ANTENNADIFFAREA 0.988 LAYER Metal2 ; + PORT + LAYER Metal2 ; + RECT 9.265 0 9.525 0.26 ; + END + END A_DOUT[0] + PIN A_ADDR[0] + DIRECTION INPUT ; + USE SIGNAL ; + ANTENNAPARTIALMETALAREA 6.7171 LAYER Metal2 ; + ANTENNAMODEL OXIDE1 ; + ANTENNAGATEAREA 0.20085 LAYER Metal2 ; + ANTENNAMAXAREACAR 34.349515 LAYER Metal2 ; + PORT + LAYER Metal2 ; + RECT 114.6 0 114.86 0.26 ; + END + END A_ADDR[0] + PIN A_BIST_ADDR[0] + DIRECTION INPUT ; + USE SIGNAL ; + ANTENNAPARTIALMETALAREA 7.5127 LAYER Metal2 ; + ANTENNAMODEL OXIDE1 ; + ANTENNAGATEAREA 0.20085 LAYER Metal2 ; + ANTENNAMAXAREACAR 38.31068 LAYER Metal2 ; + PORT + LAYER Metal2 ; + RECT 119.19 0 119.45 0.26 ; + END + END A_BIST_ADDR[0] + PIN A_ADDR[1] + DIRECTION INPUT ; + USE SIGNAL ; + ANTENNAPARTIALMETALAREA 5.59 LAYER Metal2 ; + ANTENNAMODEL OXIDE1 ; + ANTENNAGATEAREA 0.20085 LAYER Metal2 ; + ANTENNAMAXAREACAR 28.783172 LAYER Metal2 ; + PORT + LAYER Metal2 ; + RECT 114.09 0 114.35 0.26 ; + END + END A_ADDR[1] + PIN A_BIST_ADDR[1] + DIRECTION INPUT ; + USE SIGNAL ; + ANTENNAPARTIALMETALAREA 6.3856 LAYER Metal2 ; + ANTENNAMODEL OXIDE1 ; + ANTENNAGATEAREA 0.20085 LAYER Metal2 ; + ANTENNAMAXAREACAR 32.744337 LAYER Metal2 ; + PORT + LAYER Metal2 ; + RECT 118.68 0 118.94 0.26 ; + END + END A_BIST_ADDR[1] + PIN A_ADDR[2] + DIRECTION INPUT ; + USE SIGNAL ; + ANTENNAPARTIALMETALAREA 6.4519 LAYER Metal2 ; + ANTENNAMODEL OXIDE1 ; + ANTENNAGATEAREA 0.20085 LAYER Metal2 ; + ANTENNAMAXAREACAR 33.029126 LAYER Metal2 ; + PORT + LAYER Metal2 ; + RECT 99.81 0 100.07 0.26 ; + END + END A_ADDR[2] + PIN A_BIST_ADDR[2] + DIRECTION INPUT ; + USE SIGNAL ; + ANTENNAPARTIALMETALAREA 6.1867 LAYER Metal2 ; + ANTENNAMODEL OXIDE1 ; + ANTENNAGATEAREA 0.20085 LAYER Metal2 ; + ANTENNAMAXAREACAR 31.708738 LAYER Metal2 ; + PORT + LAYER Metal2 ; + RECT 101.34 0 101.6 0.26 ; + END + END A_BIST_ADDR[2] + PIN A_ADDR[3] + DIRECTION INPUT ; + USE SIGNAL ; + ANTENNAPARTIALMETALAREA 8.4487 LAYER Metal2 ; + ANTENNAPARTIALMETALAREA 1.5246 LAYER Metal3 ; + ANTENNAPARTIALCUTAREA 0.0722 LAYER Via2 ; + ANTENNAMODEL OXIDE1 ; + ANTENNAGATEAREA 0.20085 LAYER Metal3 ; + ANTENNAMAXAREACAR 9.415982 LAYER Metal3 ; + PORT + LAYER Metal2 ; + RECT 122.25 0 122.51 0.26 ; + END + END A_ADDR[3] + PIN A_BIST_ADDR[3] + DIRECTION INPUT ; + USE SIGNAL ; + ANTENNAPARTIALMETALAREA 8.4487 LAYER Metal2 ; + ANTENNAPARTIALMETALAREA 1.0962 LAYER Metal3 ; + ANTENNAPARTIALCUTAREA 0.0722 LAYER Via2 ; + ANTENNAMODEL OXIDE1 ; + ANTENNAGATEAREA 0.20085 LAYER Metal3 ; + ANTENNAMAXAREACAR 7.813791 LAYER Metal3 ; + PORT + LAYER Metal2 ; + RECT 122.76 0 123.02 0.26 ; + END + END A_BIST_ADDR[3] + PIN A_ADDR[4] + DIRECTION INPUT ; + USE SIGNAL ; + ANTENNAPARTIALMETALAREA 8.4487 LAYER Metal2 ; + ANTENNAPARTIALMETALAREA 3.8367 LAYER Metal3 ; + ANTENNAPARTIALCUTAREA 0.0722 LAYER Via2 ; + ANTENNAMODEL OXIDE1 ; + ANTENNAGATEAREA 0.20085 LAYER Metal3 ; + ANTENNAMAXAREACAR 20.927558 LAYER Metal3 ; + PORT + LAYER Metal2 ; + RECT 121.23 0 121.49 0.26 ; + END + END A_ADDR[4] + PIN A_BIST_ADDR[4] + DIRECTION INPUT ; + USE SIGNAL ; + ANTENNAPARTIALMETALAREA 8.4487 LAYER Metal2 ; + ANTENNAPARTIALMETALAREA 3.5175 LAYER Metal3 ; + ANTENNAPARTIALCUTAREA 0.0722 LAYER Via2 ; + ANTENNAMODEL OXIDE1 ; + ANTENNAGATEAREA 0.20085 LAYER Metal3 ; + ANTENNAMAXAREACAR 19.869057 LAYER Metal3 ; + PORT + LAYER Metal2 ; + RECT 121.74 0 122 0.26 ; + END + END A_BIST_ADDR[4] + PIN A_ADDR[5] + DIRECTION INPUT ; + USE SIGNAL ; + ANTENNAPARTIALMETALAREA 10.0139 LAYER Metal2 ; + ANTENNAMODEL OXIDE1 ; + ANTENNAGATEAREA 0.20085 LAYER Metal2 ; + ANTENNAMAXAREACAR 50.763754 LAYER Metal2 ; + PORT + LAYER Metal2 ; + RECT 124.8 0 125.06 0.26 ; + END + END A_ADDR[5] + PIN A_BIST_ADDR[5] + DIRECTION INPUT ; + USE SIGNAL ; + ANTENNAPARTIALMETALAREA 9.7487 LAYER Metal2 ; + ANTENNAMODEL OXIDE1 ; + ANTENNAGATEAREA 0.20085 LAYER Metal2 ; + ANTENNAMAXAREACAR 49.443366 LAYER Metal2 ; + PORT + LAYER Metal2 ; + RECT 124.29 0 124.55 0.26 ; + END + END A_BIST_ADDR[5] + PIN A_ADDR[6] + DIRECTION INPUT ; + USE SIGNAL ; + ANTENNAPARTIALMETALAREA 11.7429 LAYER Metal2 ; + ANTENNAMODEL OXIDE1 ; + ANTENNAGATEAREA 0.20085 LAYER Metal2 ; + ANTENNAMAXAREACAR 59.372168 LAYER Metal2 ; + PORT + LAYER Metal2 ; + RECT 123.78 0 124.04 0.26 ; + END + END A_ADDR[6] + PIN A_BIST_ADDR[6] + DIRECTION INPUT ; + USE SIGNAL ; + ANTENNAPARTIALMETALAREA 11.4777 LAYER Metal2 ; + ANTENNAMODEL OXIDE1 ; + ANTENNAGATEAREA 0.20085 LAYER Metal2 ; + ANTENNAMAXAREACAR 58.05178 LAYER Metal2 ; + PORT + LAYER Metal2 ; + RECT 123.27 0 123.53 0.26 ; + END + END A_BIST_ADDR[6] + PIN A_ADDR[7] + DIRECTION INPUT ; + USE SIGNAL ; + ANTENNAPARTIALMETALAREA 8.7685 LAYER Metal2 ; + ANTENNAMODEL OXIDE1 ; + ANTENNAGATEAREA 0.20085 LAYER Metal2 ; + ANTENNAMAXAREACAR 44.563107 LAYER Metal2 ; + PORT + LAYER Metal2 ; + RECT 102.36 0 102.62 0.26 ; + END + END A_ADDR[7] + PIN A_BIST_ADDR[7] + DIRECTION INPUT ; + USE SIGNAL ; + ANTENNAPARTIALMETALAREA 8.4931 LAYER Metal2 ; + ANTENNAMODEL OXIDE1 ; + ANTENNAGATEAREA 0.20085 LAYER Metal2 ; + ANTENNAMAXAREACAR 43.191934 LAYER Metal2 ; + PORT + LAYER Metal2 ; + RECT 102.87 0 103.13 0.26 ; + END + END A_BIST_ADDR[7] + PIN A_CLK + DIRECTION INPUT ; + USE SIGNAL ; + ANTENNAPARTIALMETALAREA 1.8707 LAYER Metal2 ; + ANTENNAMODEL OXIDE1 ; + ANTENNAGATEAREA 0.20085 LAYER Metal2 ; + ANTENNAMAXAREACAR 10.220065 LAYER Metal2 ; + PORT + LAYER Metal2 ; + RECT 112.56 0 112.82 0.26 ; + END + END A_CLK + PIN A_REN + DIRECTION INPUT ; + USE SIGNAL ; + ANTENNAPARTIALMETALAREA 1.81105 LAYER Metal2 ; + ANTENNAMODEL OXIDE1 ; + ANTENNAGATEAREA 0.20085 LAYER Metal2 ; + ANTENNAMAXAREACAR 9.923077 LAYER Metal2 ; + PORT + LAYER Metal2 ; + RECT 116.13 0 116.39 0.26 ; + END + END A_REN + PIN A_WEN + DIRECTION INPUT ; + USE SIGNAL ; + ANTENNAPARTIALMETALAREA 0.7007 LAYER Metal2 ; + ANTENNAMODEL OXIDE1 ; + ANTENNAGATEAREA 0.20085 LAYER Metal2 ; + ANTENNAMAXAREACAR 4.394822 LAYER Metal2 ; + PORT + LAYER Metal2 ; + RECT 115.62 0 115.88 0.26 ; + END + END A_WEN + PIN A_MEN + DIRECTION INPUT ; + USE SIGNAL ; + ANTENNAPARTIALMETALAREA 0.8407 LAYER Metal2 ; + ANTENNAMODEL OXIDE1 ; + ANTENNAGATEAREA 0.20085 LAYER Metal2 ; + ANTENNAMAXAREACAR 5.09186 LAYER Metal2 ; + PORT + LAYER Metal2 ; + RECT 113.07 0 113.33 0.26 ; + END + END A_MEN + PIN A_DLY + DIRECTION INPUT ; + USE SIGNAL ; + ANTENNAPARTIALMETALAREA 3.874 LAYER Metal2 ; + ANTENNAMODEL OXIDE1 ; + ANTENNAGATEAREA 0.3367 LAYER Metal2 ; + ANTENNAMAXAREACAR 12.046332 LAYER Metal2 ; + PORT + LAYER Metal2 ; + RECT 134.49 0 134.75 0.26 ; + END + END A_DLY + PIN A_BIST_EN + DIRECTION INPUT ; + USE SIGNAL ; + ANTENNAPARTIALMETALAREA 1.8031 LAYER Metal2 ; + ANTENNAPARTIALMETALAREA 72.69295 LAYER Metal3 ; + ANTENNAPARTIALCUTAREA 0.0722 LAYER Via2 ; + ANTENNAMODEL OXIDE1 ; + ANTENNAGATEAREA 1.43 LAYER Metal2 ; + ANTENNAGATEAREA 10.01 LAYER Metal3 ; + ANTENNAMAXAREACAR 1.686364 LAYER Metal2 ; + ANTENNAMAXAREACAR 16.344457 LAYER Metal3 ; + ANTENNAMAXCUTCAR 0.151469 LAYER Via2 ; + PORT + LAYER Metal2 ; + RECT 115.11 0 115.37 0.26 ; + END + END A_BIST_EN + PIN A_BIST_CLK + DIRECTION INPUT ; + USE SIGNAL ; + ANTENNAPARTIALMETALAREA 1.9799 LAYER Metal2 ; + ANTENNAMODEL OXIDE1 ; + ANTENNAGATEAREA 0.20085 LAYER Metal2 ; + ANTENNAMAXAREACAR 11.079661 LAYER Metal2 ; + PORT + LAYER Metal2 ; + RECT 111.03 0 111.29 0.26 ; + END + END A_BIST_CLK + PIN A_BIST_REN + DIRECTION INPUT ; + USE SIGNAL ; + ANTENNAPARTIALMETALAREA 1.9279 LAYER Metal2 ; + ANTENNAMODEL OXIDE1 ; + ANTENNAGATEAREA 0.20085 LAYER Metal2 ; + ANTENNAMAXAREACAR 10.820762 LAYER Metal2 ; + PORT + LAYER Metal2 ; + RECT 117.66 0 117.92 0.26 ; + END + END A_BIST_REN + PIN A_BIST_WEN + DIRECTION INPUT ; + USE SIGNAL ; + ANTENNAPARTIALMETALAREA 0.7211 LAYER Metal2 ; + ANTENNAMODEL OXIDE1 ; + ANTENNAGATEAREA 0.20085 LAYER Metal2 ; + ANTENNAMAXAREACAR 4.812298 LAYER Metal2 ; + PORT + LAYER Metal2 ; + RECT 117.15 0 117.41 0.26 ; + END + END A_BIST_WEN + PIN A_BIST_MEN + DIRECTION INPUT ; + USE SIGNAL ; + ANTENNAPARTIALMETALAREA 0.7137 LAYER Metal2 ; + ANTENNAMODEL OXIDE1 ; + ANTENNAGATEAREA 0.20085 LAYER Metal2 ; + ANTENNAMAXAREACAR 4.775454 LAYER Metal2 ; + PORT + LAYER Metal2 ; + RECT 111.54 0 111.8 0.26 ; + END + END A_BIST_MEN + OBS + LAYER Metal1 ; + RECT 0 0 236.8 74.1 ; + LAYER Metal2 ; + RECT 0.105 37.065 0.305 74.075 ; + RECT 1.1 73.345 1.3 74.075 ; + RECT 1.92 73.345 2.12 74.075 ; + RECT 2.415 73.345 2.615 74.075 ; + RECT 2.915 73.345 3.115 74.075 ; + RECT 3.415 73.345 3.615 74.075 ; + RECT 3.91 73.345 4.11 74.075 ; + RECT 4.73 73.345 4.93 74.075 ; + RECT 5.225 73.345 5.425 74.075 ; + RECT 5.725 73.345 5.925 74.075 ; + RECT 7.225 0.17 7.995 0.43 ; + RECT 7.225 0.17 7.485 11.38 ; + RECT 7.735 0.17 7.995 17.1 ; + RECT 6.225 73.345 6.425 74.075 ; + RECT 6.72 73.345 6.92 74.075 ; + RECT 7.54 73.345 7.74 74.075 ; + RECT 8.035 73.345 8.235 74.075 ; + RECT 8.535 73.345 8.735 74.075 ; + RECT 8.6 0.52 8.86 2.255 ; + RECT 9.035 73.345 9.235 74.075 ; + RECT 9.265 0.52 9.525 8.085 ; + RECT 9.53 73.345 9.73 74.075 ; + RECT 10.13 0.52 10.39 1.5 ; + RECT 10.35 73.345 10.55 74.075 ; + RECT 10.845 73.345 11.045 74.075 ; + RECT 11.345 73.345 11.545 74.075 ; + RECT 11.845 73.345 12.045 74.075 ; + RECT 12.34 73.345 12.54 74.075 ; + RECT 13.16 73.345 13.36 74.075 ; + RECT 13.655 73.345 13.855 74.075 ; + RECT 14.01 0.52 14.27 2.255 ; + RECT 14.155 73.345 14.355 74.075 ; + RECT 14.655 73.345 14.855 74.075 ; + RECT 15.15 73.345 15.35 74.075 ; + RECT 16.255 0.8 17.025 1.57 ; + RECT 16.255 0.3 16.515 13.03 ; + RECT 16.765 0.3 17.025 13.03 ; + RECT 15.54 0.52 15.8 2.255 ; + RECT 15.97 73.345 16.17 74.075 ; + RECT 16.465 73.345 16.665 74.075 ; + RECT 16.965 73.345 17.165 74.075 ; + RECT 17.465 73.345 17.665 74.075 ; + RECT 17.96 73.345 18.16 74.075 ; + RECT 18.78 73.345 18.98 74.075 ; + RECT 19.975 0.17 20.745 0.43 ; + RECT 19.975 0.17 20.235 13.055 ; + RECT 20.485 0.17 20.745 13.055 ; + RECT 19.275 73.345 19.475 74.075 ; + RECT 19.775 73.345 19.975 74.075 ; + RECT 20.275 73.345 20.475 74.075 ; + RECT 20.77 73.345 20.97 74.075 ; + RECT 21.59 73.345 21.79 74.075 ; + RECT 22.085 73.345 22.285 74.075 ; + RECT 22.585 73.345 22.785 74.075 ; + RECT 23.085 73.345 23.285 74.075 ; + RECT 23.58 73.345 23.78 74.075 ; + RECT 24.4 73.345 24.6 74.075 ; + RECT 24.895 73.345 25.095 74.075 ; + RECT 25.395 73.345 25.595 74.075 ; + RECT 25.895 73.345 26.095 74.075 ; + RECT 26.39 73.345 26.59 74.075 ; + RECT 27.21 73.345 27.41 74.075 ; + RECT 27.705 73.345 27.905 74.075 ; + RECT 28.205 73.345 28.405 74.075 ; + RECT 29.705 0.17 30.475 0.43 ; + RECT 29.705 0.17 29.965 11.38 ; + RECT 30.215 0.17 30.475 17.1 ; + RECT 28.705 73.345 28.905 74.075 ; + RECT 29.2 73.345 29.4 74.075 ; + RECT 30.02 73.345 30.22 74.075 ; + RECT 30.515 73.345 30.715 74.075 ; + RECT 31.015 73.345 31.215 74.075 ; + RECT 31.08 0.52 31.34 2.255 ; + RECT 31.515 73.345 31.715 74.075 ; + RECT 31.745 0.52 32.005 8.085 ; + RECT 32.01 73.345 32.21 74.075 ; + RECT 32.61 0.52 32.87 1.5 ; + RECT 32.83 73.345 33.03 74.075 ; + RECT 33.325 73.345 33.525 74.075 ; + RECT 33.825 73.345 34.025 74.075 ; + RECT 34.325 73.345 34.525 74.075 ; + RECT 34.82 73.345 35.02 74.075 ; + RECT 35.64 73.345 35.84 74.075 ; + RECT 36.135 73.345 36.335 74.075 ; + RECT 36.49 0.52 36.75 2.255 ; + RECT 36.635 73.345 36.835 74.075 ; + RECT 37.135 73.345 37.335 74.075 ; + RECT 37.63 73.345 37.83 74.075 ; + RECT 38.735 0.8 39.505 1.57 ; + RECT 38.735 0.3 38.995 13.03 ; + RECT 39.245 0.3 39.505 13.03 ; + RECT 38.02 0.52 38.28 2.255 ; + RECT 38.45 73.345 38.65 74.075 ; + RECT 38.945 73.345 39.145 74.075 ; + RECT 39.445 73.345 39.645 74.075 ; + RECT 39.945 73.345 40.145 74.075 ; + RECT 40.44 73.345 40.64 74.075 ; + RECT 41.26 73.345 41.46 74.075 ; + RECT 42.455 0.17 43.225 0.43 ; + RECT 42.455 0.17 42.715 13.055 ; + RECT 42.965 0.17 43.225 13.055 ; + RECT 41.755 73.345 41.955 74.075 ; + RECT 42.255 73.345 42.455 74.075 ; + RECT 42.755 73.345 42.955 74.075 ; + RECT 43.25 73.345 43.45 74.075 ; + RECT 44.07 73.345 44.27 74.075 ; + RECT 44.565 73.345 44.765 74.075 ; + RECT 45.065 73.345 45.265 74.075 ; + RECT 45.565 73.345 45.765 74.075 ; + RECT 46.06 73.345 46.26 74.075 ; + RECT 46.88 73.345 47.08 74.075 ; + RECT 47.375 73.345 47.575 74.075 ; + RECT 47.875 73.345 48.075 74.075 ; + RECT 48.375 73.345 48.575 74.075 ; + RECT 48.87 73.345 49.07 74.075 ; + RECT 49.69 73.345 49.89 74.075 ; + RECT 50.185 73.345 50.385 74.075 ; + RECT 50.685 73.345 50.885 74.075 ; + RECT 52.185 0.17 52.955 0.43 ; + RECT 52.185 0.17 52.445 11.38 ; + RECT 52.695 0.17 52.955 17.1 ; + RECT 51.185 73.345 51.385 74.075 ; + RECT 51.68 73.345 51.88 74.075 ; + RECT 52.5 73.345 52.7 74.075 ; + RECT 52.995 73.345 53.195 74.075 ; + RECT 53.495 73.345 53.695 74.075 ; + RECT 53.56 0.52 53.82 2.255 ; + RECT 53.995 73.345 54.195 74.075 ; + RECT 54.225 0.52 54.485 8.085 ; + RECT 54.49 73.345 54.69 74.075 ; + RECT 55.09 0.52 55.35 1.5 ; + RECT 55.31 73.345 55.51 74.075 ; + RECT 55.805 73.345 56.005 74.075 ; + RECT 56.305 73.345 56.505 74.075 ; + RECT 56.805 73.345 57.005 74.075 ; + RECT 57.3 73.345 57.5 74.075 ; + RECT 58.12 73.345 58.32 74.075 ; + RECT 58.615 73.345 58.815 74.075 ; + RECT 58.97 0.52 59.23 2.255 ; + RECT 59.115 73.345 59.315 74.075 ; + RECT 59.615 73.345 59.815 74.075 ; + RECT 60.11 73.345 60.31 74.075 ; + RECT 61.215 0.8 61.985 1.57 ; + RECT 61.215 0.3 61.475 13.03 ; + RECT 61.725 0.3 61.985 13.03 ; + RECT 60.5 0.52 60.76 2.255 ; + RECT 60.93 73.345 61.13 74.075 ; + RECT 61.425 73.345 61.625 74.075 ; + RECT 61.925 73.345 62.125 74.075 ; + RECT 62.425 73.345 62.625 74.075 ; + RECT 62.92 73.345 63.12 74.075 ; + RECT 63.74 73.345 63.94 74.075 ; + RECT 64.935 0.17 65.705 0.43 ; + RECT 64.935 0.17 65.195 13.055 ; + RECT 65.445 0.17 65.705 13.055 ; + RECT 64.235 73.345 64.435 74.075 ; + RECT 64.735 73.345 64.935 74.075 ; + RECT 65.235 73.345 65.435 74.075 ; + RECT 65.73 73.345 65.93 74.075 ; + RECT 66.55 73.345 66.75 74.075 ; + RECT 67.045 73.345 67.245 74.075 ; + RECT 67.545 73.345 67.745 74.075 ; + RECT 68.045 73.345 68.245 74.075 ; + RECT 68.54 73.345 68.74 74.075 ; + RECT 69.36 73.345 69.56 74.075 ; + RECT 69.855 73.345 70.055 74.075 ; + RECT 70.355 73.345 70.555 74.075 ; + RECT 70.855 73.345 71.055 74.075 ; + RECT 71.35 73.345 71.55 74.075 ; + RECT 72.17 73.345 72.37 74.075 ; + RECT 72.665 73.345 72.865 74.075 ; + RECT 73.165 73.345 73.365 74.075 ; + RECT 74.665 0.17 75.435 0.43 ; + RECT 74.665 0.17 74.925 11.38 ; + RECT 75.175 0.17 75.435 17.1 ; + RECT 73.665 73.345 73.865 74.075 ; + RECT 74.16 73.345 74.36 74.075 ; + RECT 74.98 73.345 75.18 74.075 ; + RECT 75.475 73.345 75.675 74.075 ; + RECT 75.975 73.345 76.175 74.075 ; + RECT 76.04 0.52 76.3 2.255 ; + RECT 76.475 73.345 76.675 74.075 ; + RECT 76.705 0.52 76.965 8.085 ; + RECT 76.97 73.345 77.17 74.075 ; + RECT 77.57 0.52 77.83 1.5 ; + RECT 77.79 73.345 77.99 74.075 ; + RECT 78.285 73.345 78.485 74.075 ; + RECT 78.785 73.345 78.985 74.075 ; + RECT 79.285 73.345 79.485 74.075 ; + RECT 79.78 73.345 79.98 74.075 ; + RECT 80.6 73.345 80.8 74.075 ; + RECT 81.095 73.345 81.295 74.075 ; + RECT 81.45 0.52 81.71 2.255 ; + RECT 81.595 73.345 81.795 74.075 ; + RECT 82.095 73.345 82.295 74.075 ; + RECT 82.59 73.345 82.79 74.075 ; + RECT 83.695 0.8 84.465 1.57 ; + RECT 83.695 0.3 83.955 13.03 ; + RECT 84.205 0.3 84.465 13.03 ; + RECT 82.98 0.52 83.24 2.255 ; + RECT 83.41 73.345 83.61 74.075 ; + RECT 83.905 73.345 84.105 74.075 ; + RECT 84.405 73.345 84.605 74.075 ; + RECT 84.905 73.345 85.105 74.075 ; + RECT 85.4 73.345 85.6 74.075 ; + RECT 86.22 73.345 86.42 74.075 ; + RECT 87.415 0.17 88.185 0.43 ; + RECT 87.415 0.17 87.675 13.055 ; + RECT 87.925 0.17 88.185 13.055 ; + RECT 86.715 73.345 86.915 74.075 ; + RECT 87.215 73.345 87.415 74.075 ; + RECT 87.715 73.345 87.915 74.075 ; + RECT 88.21 73.345 88.41 74.075 ; + RECT 89.03 73.345 89.23 74.075 ; + RECT 89.525 73.345 89.725 74.075 ; + RECT 90.025 73.345 90.225 74.075 ; + RECT 90.525 73.345 90.725 74.075 ; + RECT 96.595 0.17 97.365 0.43 ; + RECT 96.595 0.17 96.855 36.945 ; + RECT 97.105 0.17 97.365 36.945 ; + RECT 91.02 73.345 91.22 74.075 ; + RECT 91.84 73.345 92.04 74.075 ; + RECT 99.3 0 99.56 4.94 ; + RECT 99.3 4.68 100.07 4.94 ; + RECT 99.81 4.68 100.07 12.9 ; + RECT 99.81 0.52 100.07 1.78 ; + RECT 99.81 1.52 100.58 1.78 ; + RECT 100.32 1.52 100.58 12.9 ; + RECT 92.835 73.345 93.035 74.075 ; + RECT 100.32 0.59 101.09 1.27 ; + RECT 100.83 0.59 101.09 7.965 ; + RECT 97.615 0.3 97.875 37.365 ; + RECT 98.125 0.3 98.385 37.365 ; + RECT 101.34 0.52 101.6 12.9 ; + RECT 101.85 0 102.11 12.9 ; + RECT 102.36 0.52 102.62 12.9 ; + RECT 102.87 0.52 103.13 12.9 ; + RECT 103.38 0 103.64 12.9 ; + RECT 106.44 0.17 107.21 0.43 ; + RECT 106.44 0.17 106.7 2.085 ; + RECT 106.95 0.17 107.21 9 ; + RECT 103.89 0 104.15 12.9 ; + RECT 104.4 0 104.66 8.565 ; + RECT 104.91 0 105.17 8.055 ; + RECT 111.03 0.52 111.29 6.59 ; + RECT 112.56 0.52 112.82 6.305 ; + RECT 112.56 6.045 113.53 6.305 ; + RECT 111.54 0.52 111.8 2.23 ; + RECT 113.07 0.52 113.33 2.955 ; + RECT 114.09 0.52 114.35 12.9 ; + RECT 114.6 0.52 114.86 12.9 ; + RECT 116.13 0.52 116.39 6.29 ; + RECT 115.62 6.045 116.39 6.29 ; + RECT 115.11 0.52 115.37 6.745 ; + RECT 117.66 0.52 117.92 6.59 ; + RECT 117.015 6.33 117.92 6.59 ; + RECT 115.62 0.52 115.88 2.955 ; + RECT 117.15 0.52 117.41 2.67 ; + RECT 118.68 0.52 118.94 12.9 ; + RECT 119.19 0.52 119.45 12.9 ; + RECT 120.72 0.575 120.98 7.965 ; + RECT 121.23 0.52 121.49 12.9 ; + RECT 121.74 0.52 122 12.9 ; + RECT 122.25 0.52 122.51 12.9 ; + RECT 122.76 0.52 123.02 12.9 ; + RECT 123.27 0.52 123.53 12.9 ; + RECT 123.78 0.52 124.04 12.9 ; + RECT 124.29 0.52 124.55 12.9 ; + RECT 124.8 0.52 125.06 12.9 ; + RECT 125.31 0 125.57 12.9 ; + RECT 125.82 0 126.08 12.9 ; + RECT 127.35 0 127.61 12.9 ; + RECT 127.86 0 128.12 12.9 ; + RECT 135 0.17 135.77 0.43 ; + RECT 135 0.17 135.26 13.845 ; + RECT 135.51 0.17 135.77 13.845 ; + RECT 137.04 0.17 137.81 0.43 ; + RECT 137.04 0.17 137.3 2.11 ; + RECT 137.55 0.17 137.81 2.11 ; + RECT 132.45 0 132.71 3.61 ; + RECT 132.96 0 133.22 4.12 ; + RECT 139.435 0.17 140.205 0.43 ; + RECT 139.435 0.17 139.695 36.945 ; + RECT 139.945 0.17 140.205 36.945 ; + RECT 134.49 0.52 134.75 15.16 ; + RECT 138.415 0.3 138.675 37.365 ; + RECT 138.925 0.3 139.185 37.365 ; + RECT 143.765 73.345 143.965 74.075 ; + RECT 144.76 73.345 144.96 74.075 ; + RECT 145.58 73.345 145.78 74.075 ; + RECT 146.075 73.345 146.275 74.075 ; + RECT 146.575 73.345 146.775 74.075 ; + RECT 147.075 73.345 147.275 74.075 ; + RECT 148.615 0.17 149.385 0.43 ; + RECT 148.615 0.17 148.875 13.055 ; + RECT 149.125 0.17 149.385 13.055 ; + RECT 147.57 73.345 147.77 74.075 ; + RECT 148.39 73.345 148.59 74.075 ; + RECT 148.885 73.345 149.085 74.075 ; + RECT 149.385 73.345 149.585 74.075 ; + RECT 149.885 73.345 150.085 74.075 ; + RECT 150.38 73.345 150.58 74.075 ; + RECT 151.2 73.345 151.4 74.075 ; + RECT 152.335 0.8 153.105 1.57 ; + RECT 152.335 0.3 152.595 13.03 ; + RECT 152.845 0.3 153.105 13.03 ; + RECT 151.695 73.345 151.895 74.075 ; + RECT 152.195 73.345 152.395 74.075 ; + RECT 152.695 73.345 152.895 74.075 ; + RECT 153.19 73.345 153.39 74.075 ; + RECT 153.56 0.52 153.82 2.255 ; + RECT 154.01 73.345 154.21 74.075 ; + RECT 154.505 73.345 154.705 74.075 ; + RECT 155.005 73.345 155.205 74.075 ; + RECT 155.09 0.52 155.35 2.255 ; + RECT 155.505 73.345 155.705 74.075 ; + RECT 156 73.345 156.2 74.075 ; + RECT 156.82 73.345 157.02 74.075 ; + RECT 157.315 73.345 157.515 74.075 ; + RECT 157.815 73.345 158.015 74.075 ; + RECT 158.315 73.345 158.515 74.075 ; + RECT 158.81 73.345 159.01 74.075 ; + RECT 158.97 0.52 159.23 1.5 ; + RECT 159.63 73.345 159.83 74.075 ; + RECT 159.835 0.52 160.095 8.085 ; + RECT 160.125 73.345 160.325 74.075 ; + RECT 160.5 0.52 160.76 2.255 ; + RECT 161.365 0.17 162.135 0.43 ; + RECT 161.875 0.17 162.135 11.38 ; + RECT 161.365 0.17 161.625 17.1 ; + RECT 160.625 73.345 160.825 74.075 ; + RECT 161.125 73.345 161.325 74.075 ; + RECT 161.62 73.345 161.82 74.075 ; + RECT 162.44 73.345 162.64 74.075 ; + RECT 162.935 73.345 163.135 74.075 ; + RECT 163.435 73.345 163.635 74.075 ; + RECT 163.935 73.345 164.135 74.075 ; + RECT 164.43 73.345 164.63 74.075 ; + RECT 165.25 73.345 165.45 74.075 ; + RECT 165.745 73.345 165.945 74.075 ; + RECT 166.245 73.345 166.445 74.075 ; + RECT 166.745 73.345 166.945 74.075 ; + RECT 167.24 73.345 167.44 74.075 ; + RECT 168.06 73.345 168.26 74.075 ; + RECT 168.555 73.345 168.755 74.075 ; + RECT 169.055 73.345 169.255 74.075 ; + RECT 169.555 73.345 169.755 74.075 ; + RECT 171.095 0.17 171.865 0.43 ; + RECT 171.095 0.17 171.355 13.055 ; + RECT 171.605 0.17 171.865 13.055 ; + RECT 170.05 73.345 170.25 74.075 ; + RECT 170.87 73.345 171.07 74.075 ; + RECT 171.365 73.345 171.565 74.075 ; + RECT 171.865 73.345 172.065 74.075 ; + RECT 172.365 73.345 172.565 74.075 ; + RECT 172.86 73.345 173.06 74.075 ; + RECT 173.68 73.345 173.88 74.075 ; + RECT 174.815 0.8 175.585 1.57 ; + RECT 174.815 0.3 175.075 13.03 ; + RECT 175.325 0.3 175.585 13.03 ; + RECT 174.175 73.345 174.375 74.075 ; + RECT 174.675 73.345 174.875 74.075 ; + RECT 175.175 73.345 175.375 74.075 ; + RECT 175.67 73.345 175.87 74.075 ; + RECT 176.04 0.52 176.3 2.255 ; + RECT 176.49 73.345 176.69 74.075 ; + RECT 176.985 73.345 177.185 74.075 ; + RECT 177.485 73.345 177.685 74.075 ; + RECT 177.57 0.52 177.83 2.255 ; + RECT 177.985 73.345 178.185 74.075 ; + RECT 178.48 73.345 178.68 74.075 ; + RECT 179.3 73.345 179.5 74.075 ; + RECT 179.795 73.345 179.995 74.075 ; + RECT 180.295 73.345 180.495 74.075 ; + RECT 180.795 73.345 180.995 74.075 ; + RECT 181.29 73.345 181.49 74.075 ; + RECT 181.45 0.52 181.71 1.5 ; + RECT 182.11 73.345 182.31 74.075 ; + RECT 182.315 0.52 182.575 8.085 ; + RECT 182.605 73.345 182.805 74.075 ; + RECT 182.98 0.52 183.24 2.255 ; + RECT 183.845 0.17 184.615 0.43 ; + RECT 184.355 0.17 184.615 11.38 ; + RECT 183.845 0.17 184.105 17.1 ; + RECT 183.105 73.345 183.305 74.075 ; + RECT 183.605 73.345 183.805 74.075 ; + RECT 184.1 73.345 184.3 74.075 ; + RECT 184.92 73.345 185.12 74.075 ; + RECT 185.415 73.345 185.615 74.075 ; + RECT 185.915 73.345 186.115 74.075 ; + RECT 186.415 73.345 186.615 74.075 ; + RECT 186.91 73.345 187.11 74.075 ; + RECT 187.73 73.345 187.93 74.075 ; + RECT 188.225 73.345 188.425 74.075 ; + RECT 188.725 73.345 188.925 74.075 ; + RECT 189.225 73.345 189.425 74.075 ; + RECT 189.72 73.345 189.92 74.075 ; + RECT 190.54 73.345 190.74 74.075 ; + RECT 191.035 73.345 191.235 74.075 ; + RECT 191.535 73.345 191.735 74.075 ; + RECT 192.035 73.345 192.235 74.075 ; + RECT 193.575 0.17 194.345 0.43 ; + RECT 193.575 0.17 193.835 13.055 ; + RECT 194.085 0.17 194.345 13.055 ; + RECT 192.53 73.345 192.73 74.075 ; + RECT 193.35 73.345 193.55 74.075 ; + RECT 193.845 73.345 194.045 74.075 ; + RECT 194.345 73.345 194.545 74.075 ; + RECT 194.845 73.345 195.045 74.075 ; + RECT 195.34 73.345 195.54 74.075 ; + RECT 196.16 73.345 196.36 74.075 ; + RECT 197.295 0.8 198.065 1.57 ; + RECT 197.295 0.3 197.555 13.03 ; + RECT 197.805 0.3 198.065 13.03 ; + RECT 196.655 73.345 196.855 74.075 ; + RECT 197.155 73.345 197.355 74.075 ; + RECT 197.655 73.345 197.855 74.075 ; + RECT 198.15 73.345 198.35 74.075 ; + RECT 198.52 0.52 198.78 2.255 ; + RECT 198.97 73.345 199.17 74.075 ; + RECT 199.465 73.345 199.665 74.075 ; + RECT 199.965 73.345 200.165 74.075 ; + RECT 200.05 0.52 200.31 2.255 ; + RECT 200.465 73.345 200.665 74.075 ; + RECT 200.96 73.345 201.16 74.075 ; + RECT 201.78 73.345 201.98 74.075 ; + RECT 202.275 73.345 202.475 74.075 ; + RECT 202.775 73.345 202.975 74.075 ; + RECT 203.275 73.345 203.475 74.075 ; + RECT 203.77 73.345 203.97 74.075 ; + RECT 203.93 0.52 204.19 1.5 ; + RECT 204.59 73.345 204.79 74.075 ; + RECT 204.795 0.52 205.055 8.085 ; + RECT 205.085 73.345 205.285 74.075 ; + RECT 205.46 0.52 205.72 2.255 ; + RECT 206.325 0.17 207.095 0.43 ; + RECT 206.835 0.17 207.095 11.38 ; + RECT 206.325 0.17 206.585 17.1 ; + RECT 205.585 73.345 205.785 74.075 ; + RECT 206.085 73.345 206.285 74.075 ; + RECT 206.58 73.345 206.78 74.075 ; + RECT 207.4 73.345 207.6 74.075 ; + RECT 207.895 73.345 208.095 74.075 ; + RECT 208.395 73.345 208.595 74.075 ; + RECT 208.895 73.345 209.095 74.075 ; + RECT 209.39 73.345 209.59 74.075 ; + RECT 210.21 73.345 210.41 74.075 ; + RECT 210.705 73.345 210.905 74.075 ; + RECT 211.205 73.345 211.405 74.075 ; + RECT 211.705 73.345 211.905 74.075 ; + RECT 212.2 73.345 212.4 74.075 ; + RECT 213.02 73.345 213.22 74.075 ; + RECT 213.515 73.345 213.715 74.075 ; + RECT 214.015 73.345 214.215 74.075 ; + RECT 214.515 73.345 214.715 74.075 ; + RECT 216.055 0.17 216.825 0.43 ; + RECT 216.055 0.17 216.315 13.055 ; + RECT 216.565 0.17 216.825 13.055 ; + RECT 215.01 73.345 215.21 74.075 ; + RECT 215.83 73.345 216.03 74.075 ; + RECT 216.325 73.345 216.525 74.075 ; + RECT 216.825 73.345 217.025 74.075 ; + RECT 217.325 73.345 217.525 74.075 ; + RECT 217.82 73.345 218.02 74.075 ; + RECT 218.64 73.345 218.84 74.075 ; + RECT 219.775 0.8 220.545 1.57 ; + RECT 219.775 0.3 220.035 13.03 ; + RECT 220.285 0.3 220.545 13.03 ; + RECT 219.135 73.345 219.335 74.075 ; + RECT 219.635 73.345 219.835 74.075 ; + RECT 220.135 73.345 220.335 74.075 ; + RECT 220.63 73.345 220.83 74.075 ; + RECT 221 0.52 221.26 2.255 ; + RECT 221.45 73.345 221.65 74.075 ; + RECT 221.945 73.345 222.145 74.075 ; + RECT 222.445 73.345 222.645 74.075 ; + RECT 222.53 0.52 222.79 2.255 ; + RECT 222.945 73.345 223.145 74.075 ; + RECT 223.44 73.345 223.64 74.075 ; + RECT 224.26 73.345 224.46 74.075 ; + RECT 224.755 73.345 224.955 74.075 ; + RECT 225.255 73.345 225.455 74.075 ; + RECT 225.755 73.345 225.955 74.075 ; + RECT 226.25 73.345 226.45 74.075 ; + RECT 226.41 0.52 226.67 1.5 ; + RECT 227.07 73.345 227.27 74.075 ; + RECT 227.275 0.52 227.535 8.085 ; + RECT 227.565 73.345 227.765 74.075 ; + RECT 227.94 0.52 228.2 2.255 ; + RECT 228.805 0.17 229.575 0.43 ; + RECT 229.315 0.17 229.575 11.38 ; + RECT 228.805 0.17 229.065 17.1 ; + RECT 228.065 73.345 228.265 74.075 ; + RECT 228.565 73.345 228.765 74.075 ; + RECT 229.06 73.345 229.26 74.075 ; + RECT 229.88 73.345 230.08 74.075 ; + RECT 230.375 73.345 230.575 74.075 ; + RECT 230.875 73.345 231.075 74.075 ; + RECT 231.375 73.345 231.575 74.075 ; + RECT 231.87 73.345 232.07 74.075 ; + RECT 232.69 73.345 232.89 74.075 ; + RECT 233.185 73.345 233.385 74.075 ; + RECT 233.685 73.345 233.885 74.075 ; + RECT 234.185 73.345 234.385 74.075 ; + RECT 234.68 73.345 234.88 74.075 ; + RECT 235.5 73.345 235.7 74.075 ; + RECT 236.495 37.065 236.695 74.075 ; + LAYER Metal2 SPACING 0.21 ; + RECT 0 0.52 236.8 74.1 ; + RECT 228.46 0 236.8 74.1 ; + RECT 223.05 0 226.15 74.1 ; + RECT 221.52 0 222.27 74.1 ; + RECT 205.98 0 220.74 74.1 ; + RECT 200.57 0 203.67 74.1 ; + RECT 199.04 0 199.79 74.1 ; + RECT 183.5 0 198.26 74.1 ; + RECT 178.09 0 181.19 74.1 ; + RECT 176.56 0 177.31 74.1 ; + RECT 161.02 0 175.78 74.1 ; + RECT 155.61 0 158.71 74.1 ; + RECT 154.08 0 154.83 74.1 ; + RECT 135 0.17 153.3 74.1 ; + RECT 135.01 0 153.3 74.1 ; + RECT 125.31 0 134.23 74.1 ; + RECT 119.71 0 120.97 74.1 ; + RECT 118.18 0 118.42 74.1 ; + RECT 116.65 0 116.89 74.1 ; + RECT 113.59 0 113.83 74.1 ; + RECT 112.06 0 112.3 74.1 ; + RECT 103.38 0 110.77 74.1 ; + RECT 101.85 0 102.11 74.1 ; + RECT 100.33 0 101.08 74.1 ; + RECT 83.5 0 99.56 74.1 ; + RECT 81.97 0 82.72 74.1 ; + RECT 78.09 0 81.19 74.1 ; + RECT 61.02 0 75.78 74.1 ; + RECT 59.49 0 60.24 74.1 ; + RECT 55.61 0 58.71 74.1 ; + RECT 38.54 0 53.3 74.1 ; + RECT 37.01 0 37.76 74.1 ; + RECT 33.13 0 36.23 74.1 ; + RECT 16.06 0 30.82 74.1 ; + RECT 14.53 0 15.28 74.1 ; + RECT 10.65 0 13.75 74.1 ; + RECT 0 0 8.34 74.1 ; + LAYER Metal3 ; + RECT 0 0 236.8 74.1 ; + LAYER Metal4 SPACING 0.21 ; + RECT 138.09 0 145.17 74.1 ; + RECT 132.94 0 134.76 74.1 ; + RECT 127.79 0 129.61 74.1 ; + RECT 232.8 0 236.8 74.1 ; + RECT 227.18 0 229.47 74.1 ; + RECT 227.18 30.685 236.8 36.805 ; + RECT 221.56 0 223.85 74.1 ; + RECT 215.94 0 218.23 74.1 ; + RECT 215.94 30.685 223.85 36.805 ; + RECT 210.32 0 212.61 74.1 ; + RECT 204.7 0 206.99 74.1 ; + RECT 204.7 30.685 212.61 36.805 ; + RECT 199.08 0 201.37 74.1 ; + RECT 193.46 0 195.75 74.1 ; + RECT 193.46 30.685 201.37 36.805 ; + RECT 187.84 0 190.13 74.1 ; + RECT 52.29 0 54.58 74.1 ; + RECT 46.67 0 48.96 74.1 ; + RECT 46.67 30.685 54.58 36.805 ; + RECT 41.05 0 43.34 74.1 ; + RECT 35.43 0 37.72 74.1 ; + RECT 35.43 30.685 43.34 36.805 ; + RECT 29.81 0 32.1 74.1 ; + RECT 24.19 0 26.48 74.1 ; + RECT 24.19 30.685 32.1 36.805 ; + RECT 18.57 0 20.86 74.1 ; + RECT 12.95 0 15.24 74.1 ; + RECT 12.95 30.685 20.86 36.805 ; + RECT 7.33 0 9.62 74.1 ; + RECT 0 0 4 74.1 ; + RECT 0 30.685 9.62 36.805 ; + RECT 182.22 0 184.51 74.1 ; + RECT 182.22 30.685 190.13 36.805 ; + RECT 176.6 0 178.89 74.1 ; + RECT 170.98 0 173.27 74.1 ; + RECT 170.98 30.685 178.89 36.805 ; + RECT 165.36 0 167.65 74.1 ; + RECT 159.74 0 162.03 74.1 ; + RECT 159.74 30.685 167.65 36.805 ; + RECT 154.12 0 156.41 74.1 ; + RECT 148.5 0 150.79 74.1 ; + RECT 148.5 30.685 156.41 36.805 ; + RECT 122.64 0 124.46 74.1 ; + RECT 117.49 0 119.31 74.1 ; + RECT 112.34 0 114.16 74.1 ; + RECT 107.19 0 109.01 74.1 ; + RECT 102.04 0 103.86 74.1 ; + RECT 91.63 0 98.71 74.1 ; + RECT 86.01 0 88.3 74.1 ; + RECT 80.39 0 82.68 74.1 ; + RECT 80.39 30.685 88.3 36.805 ; + RECT 74.77 0 77.06 74.1 ; + RECT 69.15 0 71.44 74.1 ; + RECT 69.15 30.685 77.06 36.805 ; + RECT 63.53 0 65.82 74.1 ; + RECT 57.91 0 60.2 74.1 ; + RECT 57.91 30.685 65.82 36.805 ; + END +END RM_IHPSG13_1P_256x8_c3_bm_bist + +END LIBRARY diff --git a/flow/platforms/ihp-sg13g2/lef/RM_IHPSG13_1P_512x16_c2_bm_bist.lef b/flow/platforms/ihp-sg13g2/lef/RM_IHPSG13_1P_512x16_c2_bm_bist.lef new file mode 100644 index 0000000000..f18d627bbd --- /dev/null +++ b/flow/platforms/ihp-sg13g2/lef/RM_IHPSG13_1P_512x16_c2_bm_bist.lef @@ -0,0 +1,2442 @@ +# ------------------------------------------------------ +# +# Copyright 2025 IHP PDK Authors +# +# Licensed under the Apache License, Version 2.0 (the "License"); +# you may not use this file except in compliance with the License. +# You may obtain a copy of the License at +# +# https://www.apache.org/licenses/LICENSE-2.0 +# +# Unless required by applicable law or agreed to in writing, software +# distributed under the License is distributed on an "AS IS" BASIS, +# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +# See the License for the specific language governing permissions and +# limitations under the License. +# +# Generated on Wed Aug 27 12:16:39 2025 +# +# ------------------------------------------------------ +VERSION 5.7 ; +BUSBITCHARS "[]" ; +DIVIDERCHAR "/" ; + +MACRO RM_IHPSG13_1P_512x16_c2_bm_bist + CLASS BLOCK ; + ORIGIN 0 0 ; + FOREIGN RM_IHPSG13_1P_512x16_c2_bm_bist 0 0 ; + SIZE 236.8 BY 191.34 ; + SYMMETRY X Y R90 ; + PIN A_DIN[8] + DIRECTION INPUT ; + USE SIGNAL ; + ANTENNAPARTIALMETALAREA 1.794 LAYER Metal2 ; + ANTENNAMODEL OXIDE1 ; + ANTENNAGATEAREA 0.20085 LAYER Metal2 ; + ANTENNAMAXAREACAR 9.838188 LAYER Metal2 ; + PORT + LAYER Metal2 ; + RECT 154.57 0 154.83 0.26 ; + END + END A_DIN[8] + PIN A_DIN[7] + DIRECTION INPUT ; + USE SIGNAL ; + ANTENNAPARTIALMETALAREA 1.794 LAYER Metal2 ; + ANTENNAMODEL OXIDE1 ; + ANTENNAGATEAREA 0.20085 LAYER Metal2 ; + ANTENNAMAXAREACAR 9.838188 LAYER Metal2 ; + PORT + LAYER Metal2 ; + RECT 81.97 0 82.23 0.26 ; + END + END A_DIN[7] + PIN A_BIST_DIN[8] + DIRECTION INPUT ; + USE SIGNAL ; + ANTENNAPARTIALMETALAREA 1.6263 LAYER Metal2 ; + ANTENNAMODEL OXIDE1 ; + ANTENNAGATEAREA 0.20085 LAYER Metal2 ; + ANTENNAMAXAREACAR 9.365945 LAYER Metal2 ; + PORT + LAYER Metal2 ; + RECT 153.715 0 153.975 0.26 ; + END + END A_BIST_DIN[8] + PIN A_BIST_DIN[7] + DIRECTION INPUT ; + USE SIGNAL ; + ANTENNAPARTIALMETALAREA 1.6263 LAYER Metal2 ; + ANTENNAMODEL OXIDE1 ; + ANTENNAGATEAREA 0.20085 LAYER Metal2 ; + ANTENNAMAXAREACAR 9.365945 LAYER Metal2 ; + PORT + LAYER Metal2 ; + RECT 82.825 0 83.085 0.26 ; + END + END A_BIST_DIN[7] + PIN A_BM[8] + DIRECTION INPUT ; + USE SIGNAL ; + ANTENNAPARTIALMETALAREA 0.7215 LAYER Metal2 ; + ANTENNAMODEL OXIDE1 ; + ANTENNAGATEAREA 0.20085 LAYER Metal2 ; + ANTENNAMAXAREACAR 4.498382 LAYER Metal2 ; + PORT + LAYER Metal2 ; + RECT 146.73 0 146.99 0.26 ; + END + END A_BM[8] + PIN A_BM[7] + DIRECTION INPUT ; + USE SIGNAL ; + ANTENNAPARTIALMETALAREA 0.7215 LAYER Metal2 ; + ANTENNAMODEL OXIDE1 ; + ANTENNAGATEAREA 0.20085 LAYER Metal2 ; + ANTENNAMAXAREACAR 4.498382 LAYER Metal2 ; + PORT + LAYER Metal2 ; + RECT 89.81 0 90.07 0.26 ; + END + END A_BM[7] + PIN A_BIST_BM[8] + DIRECTION INPUT ; + USE SIGNAL ; + ANTENNAPARTIALMETALAREA 0.7605 LAYER Metal2 ; + ANTENNAMODEL OXIDE1 ; + ANTENNAGATEAREA 0.20085 LAYER Metal2 ; + ANTENNAMAXAREACAR 5.055265 LAYER Metal2 ; + PORT + LAYER Metal2 ; + RECT 148.105 0 148.365 0.26 ; + END + END A_BIST_BM[8] + PIN A_BIST_BM[7] + DIRECTION INPUT ; + USE SIGNAL ; + ANTENNAPARTIALMETALAREA 0.7605 LAYER Metal2 ; + ANTENNAMODEL OXIDE1 ; + ANTENNAGATEAREA 0.20085 LAYER Metal2 ; + ANTENNAMAXAREACAR 5.055265 LAYER Metal2 ; + PORT + LAYER Metal2 ; + RECT 88.435 0 88.695 0.26 ; + END + END A_BIST_BM[7] + PIN A_DOUT[8] + DIRECTION OUTPUT ; + USE SIGNAL ; + ANTENNAPARTIALMETALAREA 3.7095 LAYER Metal2 ; + ANTENNADIFFAREA 0.988 LAYER Metal2 ; + PORT + LAYER Metal2 ; + RECT 147.24 0 147.5 0.26 ; + END + END A_DOUT[8] + PIN A_DOUT[7] + DIRECTION OUTPUT ; + USE SIGNAL ; + ANTENNAPARTIALMETALAREA 3.7095 LAYER Metal2 ; + ANTENNADIFFAREA 0.988 LAYER Metal2 ; + PORT + LAYER Metal2 ; + RECT 89.3 0 89.56 0.26 ; + END + END A_DOUT[7] + PIN VSS! + DIRECTION INOUT ; + USE GROUND ; + NETEXPR "vss VSS!" ; + PORT + LAYER Metal4 ; + RECT 224.11 0 226.92 191.34 ; + END + PORT + LAYER Metal4 ; + RECT 212.87 0 215.68 191.34 ; + END + PORT + LAYER Metal4 ; + RECT 201.63 0 204.44 191.34 ; + END + PORT + LAYER Metal4 ; + RECT 190.39 0 193.2 191.34 ; + END + PORT + LAYER Metal4 ; + RECT 179.15 0 181.96 191.34 ; + END + PORT + LAYER Metal4 ; + RECT 167.91 0 170.72 191.34 ; + END + PORT + LAYER Metal4 ; + RECT 156.67 0 159.48 191.34 ; + END + PORT + LAYER Metal4 ; + RECT 145.43 0 148.24 191.34 ; + END + PORT + LAYER Metal4 ; + RECT 135.02 0 137.83 191.34 ; + END + PORT + LAYER Metal4 ; + RECT 124.72 0 127.53 191.34 ; + END + PORT + LAYER Metal4 ; + RECT 109.27 0 112.08 191.34 ; + END + PORT + LAYER Metal4 ; + RECT 98.97 0 101.78 191.34 ; + END + PORT + LAYER Metal4 ; + RECT 88.56 0 91.37 191.34 ; + END + PORT + LAYER Metal4 ; + RECT 77.32 0 80.13 191.34 ; + END + PORT + LAYER Metal4 ; + RECT 66.08 0 68.89 191.34 ; + END + PORT + LAYER Metal4 ; + RECT 54.84 0 57.65 191.34 ; + END + PORT + LAYER Metal4 ; + RECT 43.6 0 46.41 191.34 ; + END + PORT + LAYER Metal4 ; + RECT 32.36 0 35.17 191.34 ; + END + PORT + LAYER Metal4 ; + RECT 21.12 0 23.93 191.34 ; + END + PORT + LAYER Metal4 ; + RECT 9.88 0 12.69 191.34 ; + END + END VSS! + PIN VDD! + DIRECTION INOUT ; + USE POWER ; + NETEXPR "vdd VDD!" ; + PORT + LAYER Metal4 ; + RECT 229.73 0 232.54 38.825 ; + END + PORT + LAYER Metal4 ; + RECT 218.49 0 221.3 38.825 ; + END + PORT + LAYER Metal4 ; + RECT 207.25 0 210.06 38.825 ; + END + PORT + LAYER Metal4 ; + RECT 196.01 0 198.82 38.825 ; + END + PORT + LAYER Metal4 ; + RECT 184.77 0 187.58 38.825 ; + END + PORT + LAYER Metal4 ; + RECT 173.53 0 176.34 38.825 ; + END + PORT + LAYER Metal4 ; + RECT 162.29 0 165.1 38.825 ; + END + PORT + LAYER Metal4 ; + RECT 151.05 0 153.86 38.825 ; + END + PORT + LAYER Metal4 ; + RECT 129.87 0 132.68 191.34 ; + END + PORT + LAYER Metal4 ; + RECT 119.57 0 122.38 191.34 ; + END + PORT + LAYER Metal4 ; + RECT 114.42 0 117.23 191.34 ; + END + PORT + LAYER Metal4 ; + RECT 104.12 0 106.93 191.34 ; + END + PORT + LAYER Metal4 ; + RECT 82.94 0 85.75 38.825 ; + END + PORT + LAYER Metal4 ; + RECT 71.7 0 74.51 38.825 ; + END + PORT + LAYER Metal4 ; + RECT 60.46 0 63.27 38.825 ; + END + PORT + LAYER Metal4 ; + RECT 49.22 0 52.03 38.825 ; + END + PORT + LAYER Metal4 ; + RECT 37.98 0 40.79 38.825 ; + END + PORT + LAYER Metal4 ; + RECT 26.74 0 29.55 38.825 ; + END + PORT + LAYER Metal4 ; + RECT 15.5 0 18.31 38.825 ; + END + PORT + LAYER Metal4 ; + RECT 4.26 0 7.07 38.825 ; + END + END VDD! + PIN VDDARRAY! + DIRECTION INOUT ; + USE POWER ; + NETEXPR "vddarray VDDARRAY!" ; + PORT + LAYER Metal4 ; + RECT 229.73 45.465 232.54 191.34 ; + END + PORT + LAYER Metal4 ; + RECT 218.49 45.465 221.3 191.34 ; + END + PORT + LAYER Metal4 ; + RECT 207.25 45.465 210.06 191.34 ; + END + PORT + LAYER Metal4 ; + RECT 196.01 45.465 198.82 191.34 ; + END + PORT + LAYER Metal4 ; + RECT 184.77 45.465 187.58 191.34 ; + END + PORT + LAYER Metal4 ; + RECT 173.53 45.465 176.34 191.34 ; + END + PORT + LAYER Metal4 ; + RECT 162.29 45.465 165.1 191.34 ; + END + PORT + LAYER Metal4 ; + RECT 151.05 45.465 153.86 191.34 ; + END + PORT + LAYER Metal4 ; + RECT 82.94 45.465 85.75 191.34 ; + END + PORT + LAYER Metal4 ; + RECT 71.7 45.465 74.51 191.34 ; + END + PORT + LAYER Metal4 ; + RECT 60.46 45.465 63.27 191.34 ; + END + PORT + LAYER Metal4 ; + RECT 49.22 45.465 52.03 191.34 ; + END + PORT + LAYER Metal4 ; + RECT 37.98 45.465 40.79 191.34 ; + END + PORT + LAYER Metal4 ; + RECT 26.74 45.465 29.55 191.34 ; + END + PORT + LAYER Metal4 ; + RECT 15.5 45.465 18.31 191.34 ; + END + PORT + LAYER Metal4 ; + RECT 4.26 45.465 7.07 191.34 ; + END + END VDDARRAY! + PIN A_DIN[9] + DIRECTION INPUT ; + USE SIGNAL ; + ANTENNAPARTIALMETALAREA 1.794 LAYER Metal2 ; + ANTENNAMODEL OXIDE1 ; + ANTENNAGATEAREA 0.20085 LAYER Metal2 ; + ANTENNAMAXAREACAR 9.838188 LAYER Metal2 ; + PORT + LAYER Metal2 ; + RECT 165.81 0 166.07 0.26 ; + END + END A_DIN[9] + PIN A_DIN[6] + DIRECTION INPUT ; + USE SIGNAL ; + ANTENNAPARTIALMETALAREA 1.794 LAYER Metal2 ; + ANTENNAMODEL OXIDE1 ; + ANTENNAGATEAREA 0.20085 LAYER Metal2 ; + ANTENNAMAXAREACAR 9.838188 LAYER Metal2 ; + PORT + LAYER Metal2 ; + RECT 70.73 0 70.99 0.26 ; + END + END A_DIN[6] + PIN A_BIST_DIN[9] + DIRECTION INPUT ; + USE SIGNAL ; + ANTENNAPARTIALMETALAREA 1.6263 LAYER Metal2 ; + ANTENNAMODEL OXIDE1 ; + ANTENNAGATEAREA 0.20085 LAYER Metal2 ; + ANTENNAMAXAREACAR 9.365945 LAYER Metal2 ; + PORT + LAYER Metal2 ; + RECT 164.955 0 165.215 0.26 ; + END + END A_BIST_DIN[9] + PIN A_BIST_DIN[6] + DIRECTION INPUT ; + USE SIGNAL ; + ANTENNAPARTIALMETALAREA 1.6263 LAYER Metal2 ; + ANTENNAMODEL OXIDE1 ; + ANTENNAGATEAREA 0.20085 LAYER Metal2 ; + ANTENNAMAXAREACAR 9.365945 LAYER Metal2 ; + PORT + LAYER Metal2 ; + RECT 71.585 0 71.845 0.26 ; + END + END A_BIST_DIN[6] + PIN A_BM[9] + DIRECTION INPUT ; + USE SIGNAL ; + ANTENNAPARTIALMETALAREA 0.7215 LAYER Metal2 ; + ANTENNAMODEL OXIDE1 ; + ANTENNAGATEAREA 0.20085 LAYER Metal2 ; + ANTENNAMAXAREACAR 4.498382 LAYER Metal2 ; + PORT + LAYER Metal2 ; + RECT 157.97 0 158.23 0.26 ; + END + END A_BM[9] + PIN A_BM[6] + DIRECTION INPUT ; + USE SIGNAL ; + ANTENNAPARTIALMETALAREA 0.7215 LAYER Metal2 ; + ANTENNAMODEL OXIDE1 ; + ANTENNAGATEAREA 0.20085 LAYER Metal2 ; + ANTENNAMAXAREACAR 4.498382 LAYER Metal2 ; + PORT + LAYER Metal2 ; + RECT 78.57 0 78.83 0.26 ; + END + END A_BM[6] + PIN A_BIST_BM[9] + DIRECTION INPUT ; + USE SIGNAL ; + ANTENNAPARTIALMETALAREA 0.7605 LAYER Metal2 ; + ANTENNAMODEL OXIDE1 ; + ANTENNAGATEAREA 0.20085 LAYER Metal2 ; + ANTENNAMAXAREACAR 5.055265 LAYER Metal2 ; + PORT + LAYER Metal2 ; + RECT 159.345 0 159.605 0.26 ; + END + END A_BIST_BM[9] + PIN A_BIST_BM[6] + DIRECTION INPUT ; + USE SIGNAL ; + ANTENNAPARTIALMETALAREA 0.7605 LAYER Metal2 ; + ANTENNAMODEL OXIDE1 ; + ANTENNAGATEAREA 0.20085 LAYER Metal2 ; + ANTENNAMAXAREACAR 5.055265 LAYER Metal2 ; + PORT + LAYER Metal2 ; + RECT 77.195 0 77.455 0.26 ; + END + END A_BIST_BM[6] + PIN A_DOUT[9] + DIRECTION OUTPUT ; + USE SIGNAL ; + ANTENNAPARTIALMETALAREA 3.7095 LAYER Metal2 ; + ANTENNADIFFAREA 0.988 LAYER Metal2 ; + PORT + LAYER Metal2 ; + RECT 158.48 0 158.74 0.26 ; + END + END A_DOUT[9] + PIN A_DOUT[6] + DIRECTION OUTPUT ; + USE SIGNAL ; + ANTENNAPARTIALMETALAREA 3.7095 LAYER Metal2 ; + ANTENNADIFFAREA 0.988 LAYER Metal2 ; + PORT + LAYER Metal2 ; + RECT 78.06 0 78.32 0.26 ; + END + END A_DOUT[6] + PIN A_DIN[10] + DIRECTION INPUT ; + USE SIGNAL ; + ANTENNAPARTIALMETALAREA 1.794 LAYER Metal2 ; + ANTENNAMODEL OXIDE1 ; + ANTENNAGATEAREA 0.20085 LAYER Metal2 ; + ANTENNAMAXAREACAR 9.838188 LAYER Metal2 ; + PORT + LAYER Metal2 ; + RECT 177.05 0 177.31 0.26 ; + END + END A_DIN[10] + PIN A_DIN[5] + DIRECTION INPUT ; + USE SIGNAL ; + ANTENNAPARTIALMETALAREA 1.794 LAYER Metal2 ; + ANTENNAMODEL OXIDE1 ; + ANTENNAGATEAREA 0.20085 LAYER Metal2 ; + ANTENNAMAXAREACAR 9.838188 LAYER Metal2 ; + PORT + LAYER Metal2 ; + RECT 59.49 0 59.75 0.26 ; + END + END A_DIN[5] + PIN A_BIST_DIN[10] + DIRECTION INPUT ; + USE SIGNAL ; + ANTENNAPARTIALMETALAREA 1.6263 LAYER Metal2 ; + ANTENNAMODEL OXIDE1 ; + ANTENNAGATEAREA 0.20085 LAYER Metal2 ; + ANTENNAMAXAREACAR 9.365945 LAYER Metal2 ; + PORT + LAYER Metal2 ; + RECT 176.195 0 176.455 0.26 ; + END + END A_BIST_DIN[10] + PIN A_BIST_DIN[5] + DIRECTION INPUT ; + USE SIGNAL ; + ANTENNAPARTIALMETALAREA 1.6263 LAYER Metal2 ; + ANTENNAMODEL OXIDE1 ; + ANTENNAGATEAREA 0.20085 LAYER Metal2 ; + ANTENNAMAXAREACAR 9.365945 LAYER Metal2 ; + PORT + LAYER Metal2 ; + RECT 60.345 0 60.605 0.26 ; + END + END A_BIST_DIN[5] + PIN A_BM[10] + DIRECTION INPUT ; + USE SIGNAL ; + ANTENNAPARTIALMETALAREA 0.7215 LAYER Metal2 ; + ANTENNAMODEL OXIDE1 ; + ANTENNAGATEAREA 0.20085 LAYER Metal2 ; + ANTENNAMAXAREACAR 4.498382 LAYER Metal2 ; + PORT + LAYER Metal2 ; + RECT 169.21 0 169.47 0.26 ; + END + END A_BM[10] + PIN A_BM[5] + DIRECTION INPUT ; + USE SIGNAL ; + ANTENNAPARTIALMETALAREA 0.7215 LAYER Metal2 ; + ANTENNAMODEL OXIDE1 ; + ANTENNAGATEAREA 0.20085 LAYER Metal2 ; + ANTENNAMAXAREACAR 4.498382 LAYER Metal2 ; + PORT + LAYER Metal2 ; + RECT 67.33 0 67.59 0.26 ; + END + END A_BM[5] + PIN A_BIST_BM[10] + DIRECTION INPUT ; + USE SIGNAL ; + ANTENNAPARTIALMETALAREA 0.7605 LAYER Metal2 ; + ANTENNAMODEL OXIDE1 ; + ANTENNAGATEAREA 0.20085 LAYER Metal2 ; + ANTENNAMAXAREACAR 5.055265 LAYER Metal2 ; + PORT + LAYER Metal2 ; + RECT 170.585 0 170.845 0.26 ; + END + END A_BIST_BM[10] + PIN A_BIST_BM[5] + DIRECTION INPUT ; + USE SIGNAL ; + ANTENNAPARTIALMETALAREA 0.7605 LAYER Metal2 ; + ANTENNAMODEL OXIDE1 ; + ANTENNAGATEAREA 0.20085 LAYER Metal2 ; + ANTENNAMAXAREACAR 5.055265 LAYER Metal2 ; + PORT + LAYER Metal2 ; + RECT 65.955 0 66.215 0.26 ; + END + END A_BIST_BM[5] + PIN A_DOUT[10] + DIRECTION OUTPUT ; + USE SIGNAL ; + ANTENNAPARTIALMETALAREA 3.7095 LAYER Metal2 ; + ANTENNADIFFAREA 0.988 LAYER Metal2 ; + PORT + LAYER Metal2 ; + RECT 169.72 0 169.98 0.26 ; + END + END A_DOUT[10] + PIN A_DOUT[5] + DIRECTION OUTPUT ; + USE SIGNAL ; + ANTENNAPARTIALMETALAREA 3.7095 LAYER Metal2 ; + ANTENNADIFFAREA 0.988 LAYER Metal2 ; + PORT + LAYER Metal2 ; + RECT 66.82 0 67.08 0.26 ; + END + END A_DOUT[5] + PIN A_DIN[11] + DIRECTION INPUT ; + USE SIGNAL ; + ANTENNAPARTIALMETALAREA 1.794 LAYER Metal2 ; + ANTENNAMODEL OXIDE1 ; + ANTENNAGATEAREA 0.20085 LAYER Metal2 ; + ANTENNAMAXAREACAR 9.838188 LAYER Metal2 ; + PORT + LAYER Metal2 ; + RECT 188.29 0 188.55 0.26 ; + END + END A_DIN[11] + PIN A_DIN[4] + DIRECTION INPUT ; + USE SIGNAL ; + ANTENNAPARTIALMETALAREA 1.794 LAYER Metal2 ; + ANTENNAMODEL OXIDE1 ; + ANTENNAGATEAREA 0.20085 LAYER Metal2 ; + ANTENNAMAXAREACAR 9.838188 LAYER Metal2 ; + PORT + LAYER Metal2 ; + RECT 48.25 0 48.51 0.26 ; + END + END A_DIN[4] + PIN A_BIST_DIN[11] + DIRECTION INPUT ; + USE SIGNAL ; + ANTENNAPARTIALMETALAREA 1.6263 LAYER Metal2 ; + ANTENNAMODEL OXIDE1 ; + ANTENNAGATEAREA 0.20085 LAYER Metal2 ; + ANTENNAMAXAREACAR 9.365945 LAYER Metal2 ; + PORT + LAYER Metal2 ; + RECT 187.435 0 187.695 0.26 ; + END + END A_BIST_DIN[11] + PIN A_BIST_DIN[4] + DIRECTION INPUT ; + USE SIGNAL ; + ANTENNAPARTIALMETALAREA 1.6263 LAYER Metal2 ; + ANTENNAMODEL OXIDE1 ; + ANTENNAGATEAREA 0.20085 LAYER Metal2 ; + ANTENNAMAXAREACAR 9.365945 LAYER Metal2 ; + PORT + LAYER Metal2 ; + RECT 49.105 0 49.365 0.26 ; + END + END A_BIST_DIN[4] + PIN A_BM[11] + DIRECTION INPUT ; + USE SIGNAL ; + ANTENNAPARTIALMETALAREA 0.7215 LAYER Metal2 ; + ANTENNAMODEL OXIDE1 ; + ANTENNAGATEAREA 0.20085 LAYER Metal2 ; + ANTENNAMAXAREACAR 4.498382 LAYER Metal2 ; + PORT + LAYER Metal2 ; + RECT 180.45 0 180.71 0.26 ; + END + END A_BM[11] + PIN A_BM[4] + DIRECTION INPUT ; + USE SIGNAL ; + ANTENNAPARTIALMETALAREA 0.7215 LAYER Metal2 ; + ANTENNAMODEL OXIDE1 ; + ANTENNAGATEAREA 0.20085 LAYER Metal2 ; + ANTENNAMAXAREACAR 4.498382 LAYER Metal2 ; + PORT + LAYER Metal2 ; + RECT 56.09 0 56.35 0.26 ; + END + END A_BM[4] + PIN A_BIST_BM[11] + DIRECTION INPUT ; + USE SIGNAL ; + ANTENNAPARTIALMETALAREA 0.7605 LAYER Metal2 ; + ANTENNAMODEL OXIDE1 ; + ANTENNAGATEAREA 0.20085 LAYER Metal2 ; + ANTENNAMAXAREACAR 5.055265 LAYER Metal2 ; + PORT + LAYER Metal2 ; + RECT 181.825 0 182.085 0.26 ; + END + END A_BIST_BM[11] + PIN A_BIST_BM[4] + DIRECTION INPUT ; + USE SIGNAL ; + ANTENNAPARTIALMETALAREA 0.7605 LAYER Metal2 ; + ANTENNAMODEL OXIDE1 ; + ANTENNAGATEAREA 0.20085 LAYER Metal2 ; + ANTENNAMAXAREACAR 5.055265 LAYER Metal2 ; + PORT + LAYER Metal2 ; + RECT 54.715 0 54.975 0.26 ; + END + END A_BIST_BM[4] + PIN A_DOUT[11] + DIRECTION OUTPUT ; + USE SIGNAL ; + ANTENNAPARTIALMETALAREA 3.7095 LAYER Metal2 ; + ANTENNADIFFAREA 0.988 LAYER Metal2 ; + PORT + LAYER Metal2 ; + RECT 180.96 0 181.22 0.26 ; + END + END A_DOUT[11] + PIN A_DOUT[4] + DIRECTION OUTPUT ; + USE SIGNAL ; + ANTENNAPARTIALMETALAREA 3.7095 LAYER Metal2 ; + ANTENNADIFFAREA 0.988 LAYER Metal2 ; + PORT + LAYER Metal2 ; + RECT 55.58 0 55.84 0.26 ; + END + END A_DOUT[4] + PIN A_DIN[12] + DIRECTION INPUT ; + USE SIGNAL ; + ANTENNAPARTIALMETALAREA 1.794 LAYER Metal2 ; + ANTENNAMODEL OXIDE1 ; + ANTENNAGATEAREA 0.20085 LAYER Metal2 ; + ANTENNAMAXAREACAR 9.838188 LAYER Metal2 ; + PORT + LAYER Metal2 ; + RECT 199.53 0 199.79 0.26 ; + END + END A_DIN[12] + PIN A_DIN[3] + DIRECTION INPUT ; + USE SIGNAL ; + ANTENNAPARTIALMETALAREA 1.794 LAYER Metal2 ; + ANTENNAMODEL OXIDE1 ; + ANTENNAGATEAREA 0.20085 LAYER Metal2 ; + ANTENNAMAXAREACAR 9.838188 LAYER Metal2 ; + PORT + LAYER Metal2 ; + RECT 37.01 0 37.27 0.26 ; + END + END A_DIN[3] + PIN A_BIST_DIN[12] + DIRECTION INPUT ; + USE SIGNAL ; + ANTENNAPARTIALMETALAREA 1.6263 LAYER Metal2 ; + ANTENNAMODEL OXIDE1 ; + ANTENNAGATEAREA 0.20085 LAYER Metal2 ; + ANTENNAMAXAREACAR 9.365945 LAYER Metal2 ; + PORT + LAYER Metal2 ; + RECT 198.675 0 198.935 0.26 ; + END + END A_BIST_DIN[12] + PIN A_BIST_DIN[3] + DIRECTION INPUT ; + USE SIGNAL ; + ANTENNAPARTIALMETALAREA 1.6263 LAYER Metal2 ; + ANTENNAMODEL OXIDE1 ; + ANTENNAGATEAREA 0.20085 LAYER Metal2 ; + ANTENNAMAXAREACAR 9.365945 LAYER Metal2 ; + PORT + LAYER Metal2 ; + RECT 37.865 0 38.125 0.26 ; + END + END A_BIST_DIN[3] + PIN A_BM[12] + DIRECTION INPUT ; + USE SIGNAL ; + ANTENNAPARTIALMETALAREA 0.7215 LAYER Metal2 ; + ANTENNAMODEL OXIDE1 ; + ANTENNAGATEAREA 0.20085 LAYER Metal2 ; + ANTENNAMAXAREACAR 4.498382 LAYER Metal2 ; + PORT + LAYER Metal2 ; + RECT 191.69 0 191.95 0.26 ; + END + END A_BM[12] + PIN A_BM[3] + DIRECTION INPUT ; + USE SIGNAL ; + ANTENNAPARTIALMETALAREA 0.7215 LAYER Metal2 ; + ANTENNAMODEL OXIDE1 ; + ANTENNAGATEAREA 0.20085 LAYER Metal2 ; + ANTENNAMAXAREACAR 4.498382 LAYER Metal2 ; + PORT + LAYER Metal2 ; + RECT 44.85 0 45.11 0.26 ; + END + END A_BM[3] + PIN A_BIST_BM[12] + DIRECTION INPUT ; + USE SIGNAL ; + ANTENNAPARTIALMETALAREA 0.7605 LAYER Metal2 ; + ANTENNAMODEL OXIDE1 ; + ANTENNAGATEAREA 0.20085 LAYER Metal2 ; + ANTENNAMAXAREACAR 5.055265 LAYER Metal2 ; + PORT + LAYER Metal2 ; + RECT 193.065 0 193.325 0.26 ; + END + END A_BIST_BM[12] + PIN A_BIST_BM[3] + DIRECTION INPUT ; + USE SIGNAL ; + ANTENNAPARTIALMETALAREA 0.7605 LAYER Metal2 ; + ANTENNAMODEL OXIDE1 ; + ANTENNAGATEAREA 0.20085 LAYER Metal2 ; + ANTENNAMAXAREACAR 5.055265 LAYER Metal2 ; + PORT + LAYER Metal2 ; + RECT 43.475 0 43.735 0.26 ; + END + END A_BIST_BM[3] + PIN A_DOUT[12] + DIRECTION OUTPUT ; + USE SIGNAL ; + ANTENNAPARTIALMETALAREA 3.7095 LAYER Metal2 ; + ANTENNADIFFAREA 0.988 LAYER Metal2 ; + PORT + LAYER Metal2 ; + RECT 192.2 0 192.46 0.26 ; + END + END A_DOUT[12] + PIN A_DOUT[3] + DIRECTION OUTPUT ; + USE SIGNAL ; + ANTENNAPARTIALMETALAREA 3.7095 LAYER Metal2 ; + ANTENNADIFFAREA 0.988 LAYER Metal2 ; + PORT + LAYER Metal2 ; + RECT 44.34 0 44.6 0.26 ; + END + END A_DOUT[3] + PIN A_DIN[13] + DIRECTION INPUT ; + USE SIGNAL ; + ANTENNAPARTIALMETALAREA 1.794 LAYER Metal2 ; + ANTENNAMODEL OXIDE1 ; + ANTENNAGATEAREA 0.20085 LAYER Metal2 ; + ANTENNAMAXAREACAR 9.838188 LAYER Metal2 ; + PORT + LAYER Metal2 ; + RECT 210.77 0 211.03 0.26 ; + END + END A_DIN[13] + PIN A_DIN[2] + DIRECTION INPUT ; + USE SIGNAL ; + ANTENNAPARTIALMETALAREA 1.794 LAYER Metal2 ; + ANTENNAMODEL OXIDE1 ; + ANTENNAGATEAREA 0.20085 LAYER Metal2 ; + ANTENNAMAXAREACAR 9.838188 LAYER Metal2 ; + PORT + LAYER Metal2 ; + RECT 25.77 0 26.03 0.26 ; + END + END A_DIN[2] + PIN A_BIST_DIN[13] + DIRECTION INPUT ; + USE SIGNAL ; + ANTENNAPARTIALMETALAREA 1.6263 LAYER Metal2 ; + ANTENNAMODEL OXIDE1 ; + ANTENNAGATEAREA 0.20085 LAYER Metal2 ; + ANTENNAMAXAREACAR 9.365945 LAYER Metal2 ; + PORT + LAYER Metal2 ; + RECT 209.915 0 210.175 0.26 ; + END + END A_BIST_DIN[13] + PIN A_BIST_DIN[2] + DIRECTION INPUT ; + USE SIGNAL ; + ANTENNAPARTIALMETALAREA 1.6263 LAYER Metal2 ; + ANTENNAMODEL OXIDE1 ; + ANTENNAGATEAREA 0.20085 LAYER Metal2 ; + ANTENNAMAXAREACAR 9.365945 LAYER Metal2 ; + PORT + LAYER Metal2 ; + RECT 26.625 0 26.885 0.26 ; + END + END A_BIST_DIN[2] + PIN A_BM[13] + DIRECTION INPUT ; + USE SIGNAL ; + ANTENNAPARTIALMETALAREA 0.7215 LAYER Metal2 ; + ANTENNAMODEL OXIDE1 ; + ANTENNAGATEAREA 0.20085 LAYER Metal2 ; + ANTENNAMAXAREACAR 4.498382 LAYER Metal2 ; + PORT + LAYER Metal2 ; + RECT 202.93 0 203.19 0.26 ; + END + END A_BM[13] + PIN A_BM[2] + DIRECTION INPUT ; + USE SIGNAL ; + ANTENNAPARTIALMETALAREA 0.7215 LAYER Metal2 ; + ANTENNAMODEL OXIDE1 ; + ANTENNAGATEAREA 0.20085 LAYER Metal2 ; + ANTENNAMAXAREACAR 4.498382 LAYER Metal2 ; + PORT + LAYER Metal2 ; + RECT 33.61 0 33.87 0.26 ; + END + END A_BM[2] + PIN A_BIST_BM[13] + DIRECTION INPUT ; + USE SIGNAL ; + ANTENNAPARTIALMETALAREA 0.7605 LAYER Metal2 ; + ANTENNAMODEL OXIDE1 ; + ANTENNAGATEAREA 0.20085 LAYER Metal2 ; + ANTENNAMAXAREACAR 5.055265 LAYER Metal2 ; + PORT + LAYER Metal2 ; + RECT 204.305 0 204.565 0.26 ; + END + END A_BIST_BM[13] + PIN A_BIST_BM[2] + DIRECTION INPUT ; + USE SIGNAL ; + ANTENNAPARTIALMETALAREA 0.7605 LAYER Metal2 ; + ANTENNAMODEL OXIDE1 ; + ANTENNAGATEAREA 0.20085 LAYER Metal2 ; + ANTENNAMAXAREACAR 5.055265 LAYER Metal2 ; + PORT + LAYER Metal2 ; + RECT 32.235 0 32.495 0.26 ; + END + END A_BIST_BM[2] + PIN A_DOUT[13] + DIRECTION OUTPUT ; + USE SIGNAL ; + ANTENNAPARTIALMETALAREA 3.7095 LAYER Metal2 ; + ANTENNADIFFAREA 0.988 LAYER Metal2 ; + PORT + LAYER Metal2 ; + RECT 203.44 0 203.7 0.26 ; + END + END A_DOUT[13] + PIN A_DOUT[2] + DIRECTION OUTPUT ; + USE SIGNAL ; + ANTENNAPARTIALMETALAREA 3.7095 LAYER Metal2 ; + ANTENNADIFFAREA 0.988 LAYER Metal2 ; + PORT + LAYER Metal2 ; + RECT 33.1 0 33.36 0.26 ; + END + END A_DOUT[2] + PIN A_DIN[14] + DIRECTION INPUT ; + USE SIGNAL ; + ANTENNAPARTIALMETALAREA 1.794 LAYER Metal2 ; + ANTENNAMODEL OXIDE1 ; + ANTENNAGATEAREA 0.20085 LAYER Metal2 ; + ANTENNAMAXAREACAR 9.838188 LAYER Metal2 ; + PORT + LAYER Metal2 ; + RECT 222.01 0 222.27 0.26 ; + END + END A_DIN[14] + PIN A_DIN[1] + DIRECTION INPUT ; + USE SIGNAL ; + ANTENNAPARTIALMETALAREA 1.794 LAYER Metal2 ; + ANTENNAMODEL OXIDE1 ; + ANTENNAGATEAREA 0.20085 LAYER Metal2 ; + ANTENNAMAXAREACAR 9.838188 LAYER Metal2 ; + PORT + LAYER Metal2 ; + RECT 14.53 0 14.79 0.26 ; + END + END A_DIN[1] + PIN A_BIST_DIN[14] + DIRECTION INPUT ; + USE SIGNAL ; + ANTENNAPARTIALMETALAREA 1.6263 LAYER Metal2 ; + ANTENNAMODEL OXIDE1 ; + ANTENNAGATEAREA 0.20085 LAYER Metal2 ; + ANTENNAMAXAREACAR 9.365945 LAYER Metal2 ; + PORT + LAYER Metal2 ; + RECT 221.155 0 221.415 0.26 ; + END + END A_BIST_DIN[14] + PIN A_BIST_DIN[1] + DIRECTION INPUT ; + USE SIGNAL ; + ANTENNAPARTIALMETALAREA 1.6263 LAYER Metal2 ; + ANTENNAMODEL OXIDE1 ; + ANTENNAGATEAREA 0.20085 LAYER Metal2 ; + ANTENNAMAXAREACAR 9.365945 LAYER Metal2 ; + PORT + LAYER Metal2 ; + RECT 15.385 0 15.645 0.26 ; + END + END A_BIST_DIN[1] + PIN A_BM[14] + DIRECTION INPUT ; + USE SIGNAL ; + ANTENNAPARTIALMETALAREA 0.7215 LAYER Metal2 ; + ANTENNAMODEL OXIDE1 ; + ANTENNAGATEAREA 0.20085 LAYER Metal2 ; + ANTENNAMAXAREACAR 4.498382 LAYER Metal2 ; + PORT + LAYER Metal2 ; + RECT 214.17 0 214.43 0.26 ; + END + END A_BM[14] + PIN A_BM[1] + DIRECTION INPUT ; + USE SIGNAL ; + ANTENNAPARTIALMETALAREA 0.7215 LAYER Metal2 ; + ANTENNAMODEL OXIDE1 ; + ANTENNAGATEAREA 0.20085 LAYER Metal2 ; + ANTENNAMAXAREACAR 4.498382 LAYER Metal2 ; + PORT + LAYER Metal2 ; + RECT 22.37 0 22.63 0.26 ; + END + END A_BM[1] + PIN A_BIST_BM[14] + DIRECTION INPUT ; + USE SIGNAL ; + ANTENNAPARTIALMETALAREA 0.7605 LAYER Metal2 ; + ANTENNAMODEL OXIDE1 ; + ANTENNAGATEAREA 0.20085 LAYER Metal2 ; + ANTENNAMAXAREACAR 5.055265 LAYER Metal2 ; + PORT + LAYER Metal2 ; + RECT 215.545 0 215.805 0.26 ; + END + END A_BIST_BM[14] + PIN A_BIST_BM[1] + DIRECTION INPUT ; + USE SIGNAL ; + ANTENNAPARTIALMETALAREA 0.7605 LAYER Metal2 ; + ANTENNAMODEL OXIDE1 ; + ANTENNAGATEAREA 0.20085 LAYER Metal2 ; + ANTENNAMAXAREACAR 5.055265 LAYER Metal2 ; + PORT + LAYER Metal2 ; + RECT 20.995 0 21.255 0.26 ; + END + END A_BIST_BM[1] + PIN A_DOUT[14] + DIRECTION OUTPUT ; + USE SIGNAL ; + ANTENNAPARTIALMETALAREA 3.7095 LAYER Metal2 ; + ANTENNADIFFAREA 0.988 LAYER Metal2 ; + PORT + LAYER Metal2 ; + RECT 214.68 0 214.94 0.26 ; + END + END A_DOUT[14] + PIN A_DOUT[1] + DIRECTION OUTPUT ; + USE SIGNAL ; + ANTENNAPARTIALMETALAREA 3.7095 LAYER Metal2 ; + ANTENNADIFFAREA 0.988 LAYER Metal2 ; + PORT + LAYER Metal2 ; + RECT 21.86 0 22.12 0.26 ; + END + END A_DOUT[1] + PIN A_DIN[15] + DIRECTION INPUT ; + USE SIGNAL ; + ANTENNAPARTIALMETALAREA 1.794 LAYER Metal2 ; + ANTENNAMODEL OXIDE1 ; + ANTENNAGATEAREA 0.20085 LAYER Metal2 ; + ANTENNAMAXAREACAR 9.838188 LAYER Metal2 ; + PORT + LAYER Metal2 ; + RECT 233.25 0 233.51 0.26 ; + END + END A_DIN[15] + PIN A_DIN[0] + DIRECTION INPUT ; + USE SIGNAL ; + ANTENNAPARTIALMETALAREA 1.794 LAYER Metal2 ; + ANTENNAMODEL OXIDE1 ; + ANTENNAGATEAREA 0.20085 LAYER Metal2 ; + ANTENNAMAXAREACAR 9.838188 LAYER Metal2 ; + PORT + LAYER Metal2 ; + RECT 3.29 0 3.55 0.26 ; + END + END A_DIN[0] + PIN A_BIST_DIN[15] + DIRECTION INPUT ; + USE SIGNAL ; + ANTENNAPARTIALMETALAREA 1.6263 LAYER Metal2 ; + ANTENNAMODEL OXIDE1 ; + ANTENNAGATEAREA 0.20085 LAYER Metal2 ; + ANTENNAMAXAREACAR 9.365945 LAYER Metal2 ; + PORT + LAYER Metal2 ; + RECT 232.395 0 232.655 0.26 ; + END + END A_BIST_DIN[15] + PIN A_BIST_DIN[0] + DIRECTION INPUT ; + USE SIGNAL ; + ANTENNAPARTIALMETALAREA 1.6263 LAYER Metal2 ; + ANTENNAMODEL OXIDE1 ; + ANTENNAGATEAREA 0.20085 LAYER Metal2 ; + ANTENNAMAXAREACAR 9.365945 LAYER Metal2 ; + PORT + LAYER Metal2 ; + RECT 4.145 0 4.405 0.26 ; + END + END A_BIST_DIN[0] + PIN A_BM[15] + DIRECTION INPUT ; + USE SIGNAL ; + ANTENNAPARTIALMETALAREA 0.7215 LAYER Metal2 ; + ANTENNAMODEL OXIDE1 ; + ANTENNAGATEAREA 0.20085 LAYER Metal2 ; + ANTENNAMAXAREACAR 4.498382 LAYER Metal2 ; + PORT + LAYER Metal2 ; + RECT 225.41 0 225.67 0.26 ; + END + END A_BM[15] + PIN A_BM[0] + DIRECTION INPUT ; + USE SIGNAL ; + ANTENNAPARTIALMETALAREA 0.7215 LAYER Metal2 ; + ANTENNAMODEL OXIDE1 ; + ANTENNAGATEAREA 0.20085 LAYER Metal2 ; + ANTENNAMAXAREACAR 4.498382 LAYER Metal2 ; + PORT + LAYER Metal2 ; + RECT 11.13 0 11.39 0.26 ; + END + END A_BM[0] + PIN A_BIST_BM[15] + DIRECTION INPUT ; + USE SIGNAL ; + ANTENNAPARTIALMETALAREA 0.7605 LAYER Metal2 ; + ANTENNAMODEL OXIDE1 ; + ANTENNAGATEAREA 0.20085 LAYER Metal2 ; + ANTENNAMAXAREACAR 5.055265 LAYER Metal2 ; + PORT + LAYER Metal2 ; + RECT 226.785 0 227.045 0.26 ; + END + END A_BIST_BM[15] + PIN A_BIST_BM[0] + DIRECTION INPUT ; + USE SIGNAL ; + ANTENNAPARTIALMETALAREA 0.7605 LAYER Metal2 ; + ANTENNAMODEL OXIDE1 ; + ANTENNAGATEAREA 0.20085 LAYER Metal2 ; + ANTENNAMAXAREACAR 5.055265 LAYER Metal2 ; + PORT + LAYER Metal2 ; + RECT 9.755 0 10.015 0.26 ; + END + END A_BIST_BM[0] + PIN A_DOUT[15] + DIRECTION OUTPUT ; + USE SIGNAL ; + ANTENNAPARTIALMETALAREA 3.7095 LAYER Metal2 ; + ANTENNADIFFAREA 0.988 LAYER Metal2 ; + PORT + LAYER Metal2 ; + RECT 225.92 0 226.18 0.26 ; + END + END A_DOUT[15] + PIN A_DOUT[0] + DIRECTION OUTPUT ; + USE SIGNAL ; + ANTENNAPARTIALMETALAREA 3.7095 LAYER Metal2 ; + ANTENNADIFFAREA 0.988 LAYER Metal2 ; + PORT + LAYER Metal2 ; + RECT 10.62 0 10.88 0.26 ; + END + END A_DOUT[0] + PIN A_ADDR[0] + DIRECTION INPUT ; + USE SIGNAL ; + ANTENNAPARTIALMETALAREA 8.9011 LAYER Metal2 ; + ANTENNAMODEL OXIDE1 ; + ANTENNAGATEAREA 0.20085 LAYER Metal2 ; + ANTENNAMAXAREACAR 45.223301 LAYER Metal2 ; + PORT + LAYER Metal2 ; + RECT 114.6 0 114.86 0.26 ; + END + END A_ADDR[0] + PIN A_BIST_ADDR[0] + DIRECTION INPUT ; + USE SIGNAL ; + ANTENNAPARTIALMETALAREA 9.6967 LAYER Metal2 ; + ANTENNAMODEL OXIDE1 ; + ANTENNAGATEAREA 0.20085 LAYER Metal2 ; + ANTENNAMAXAREACAR 49.184466 LAYER Metal2 ; + PORT + LAYER Metal2 ; + RECT 119.19 0 119.45 0.26 ; + END + END A_BIST_ADDR[0] + PIN A_ADDR[1] + DIRECTION INPUT ; + USE SIGNAL ; + ANTENNAPARTIALMETALAREA 7.774 LAYER Metal2 ; + ANTENNAMODEL OXIDE1 ; + ANTENNAGATEAREA 0.20085 LAYER Metal2 ; + ANTENNAMAXAREACAR 39.656958 LAYER Metal2 ; + PORT + LAYER Metal2 ; + RECT 114.09 0 114.35 0.26 ; + END + END A_ADDR[1] + PIN A_BIST_ADDR[1] + DIRECTION INPUT ; + USE SIGNAL ; + ANTENNAPARTIALMETALAREA 8.5696 LAYER Metal2 ; + ANTENNAMODEL OXIDE1 ; + ANTENNAGATEAREA 0.20085 LAYER Metal2 ; + ANTENNAMAXAREACAR 43.618123 LAYER Metal2 ; + PORT + LAYER Metal2 ; + RECT 118.68 0 118.94 0.26 ; + END + END A_BIST_ADDR[1] + PIN A_ADDR[2] + DIRECTION INPUT ; + USE SIGNAL ; + ANTENNAPARTIALMETALAREA 10.6327 LAYER Metal2 ; + ANTENNAPARTIALMETALAREA 1.5246 LAYER Metal3 ; + ANTENNAPARTIALCUTAREA 0.0722 LAYER Via2 ; + ANTENNAMODEL OXIDE1 ; + ANTENNAGATEAREA 0.20085 LAYER Metal3 ; + ANTENNAMAXAREACAR 9.415982 LAYER Metal3 ; + PORT + LAYER Metal2 ; + RECT 122.25 0 122.51 0.26 ; + END + END A_ADDR[2] + PIN A_BIST_ADDR[2] + DIRECTION INPUT ; + USE SIGNAL ; + ANTENNAPARTIALMETALAREA 10.6327 LAYER Metal2 ; + ANTENNAPARTIALMETALAREA 1.0962 LAYER Metal3 ; + ANTENNAPARTIALCUTAREA 0.0722 LAYER Via2 ; + ANTENNAMODEL OXIDE1 ; + ANTENNAGATEAREA 0.20085 LAYER Metal3 ; + ANTENNAMAXAREACAR 7.813791 LAYER Metal3 ; + PORT + LAYER Metal2 ; + RECT 122.76 0 123.02 0.26 ; + END + END A_BIST_ADDR[2] + PIN A_ADDR[3] + DIRECTION INPUT ; + USE SIGNAL ; + ANTENNAPARTIALMETALAREA 10.6327 LAYER Metal2 ; + ANTENNAPARTIALMETALAREA 3.8367 LAYER Metal3 ; + ANTENNAPARTIALCUTAREA 0.0722 LAYER Via2 ; + ANTENNAMODEL OXIDE1 ; + ANTENNAGATEAREA 0.20085 LAYER Metal3 ; + ANTENNAMAXAREACAR 20.927558 LAYER Metal3 ; + PORT + LAYER Metal2 ; + RECT 121.23 0 121.49 0.26 ; + END + END A_ADDR[3] + PIN A_BIST_ADDR[3] + DIRECTION INPUT ; + USE SIGNAL ; + ANTENNAPARTIALMETALAREA 10.6327 LAYER Metal2 ; + ANTENNAPARTIALMETALAREA 3.5175 LAYER Metal3 ; + ANTENNAPARTIALCUTAREA 0.0722 LAYER Via2 ; + ANTENNAMODEL OXIDE1 ; + ANTENNAGATEAREA 0.20085 LAYER Metal3 ; + ANTENNAMAXAREACAR 19.869057 LAYER Metal3 ; + PORT + LAYER Metal2 ; + RECT 121.74 0 122 0.26 ; + END + END A_BIST_ADDR[3] + PIN A_ADDR[4] + DIRECTION INPUT ; + USE SIGNAL ; + ANTENNAPARTIALMETALAREA 12.1979 LAYER Metal2 ; + ANTENNAMODEL OXIDE1 ; + ANTENNAGATEAREA 0.20085 LAYER Metal2 ; + ANTENNAMAXAREACAR 61.63754 LAYER Metal2 ; + PORT + LAYER Metal2 ; + RECT 124.8 0 125.06 0.26 ; + END + END A_ADDR[4] + PIN A_BIST_ADDR[4] + DIRECTION INPUT ; + USE SIGNAL ; + ANTENNAPARTIALMETALAREA 11.9327 LAYER Metal2 ; + ANTENNAMODEL OXIDE1 ; + ANTENNAGATEAREA 0.20085 LAYER Metal2 ; + ANTENNAMAXAREACAR 60.317152 LAYER Metal2 ; + PORT + LAYER Metal2 ; + RECT 124.29 0 124.55 0.26 ; + END + END A_BIST_ADDR[4] + PIN A_ADDR[5] + DIRECTION INPUT ; + USE SIGNAL ; + ANTENNAPARTIALMETALAREA 13.9269 LAYER Metal2 ; + ANTENNAMODEL OXIDE1 ; + ANTENNAGATEAREA 0.20085 LAYER Metal2 ; + ANTENNAMAXAREACAR 70.245955 LAYER Metal2 ; + PORT + LAYER Metal2 ; + RECT 123.78 0 124.04 0.26 ; + END + END A_ADDR[5] + PIN A_BIST_ADDR[5] + DIRECTION INPUT ; + USE SIGNAL ; + ANTENNAPARTIALMETALAREA 13.6617 LAYER Metal2 ; + ANTENNAMODEL OXIDE1 ; + ANTENNAGATEAREA 0.20085 LAYER Metal2 ; + ANTENNAMAXAREACAR 68.925566 LAYER Metal2 ; + PORT + LAYER Metal2 ; + RECT 123.27 0 123.53 0.26 ; + END + END A_BIST_ADDR[5] + PIN A_ADDR[6] + DIRECTION INPUT ; + USE SIGNAL ; + ANTENNAPARTIALMETALAREA 10.9525 LAYER Metal2 ; + ANTENNAMODEL OXIDE1 ; + ANTENNAGATEAREA 0.20085 LAYER Metal2 ; + ANTENNAMAXAREACAR 55.436893 LAYER Metal2 ; + PORT + LAYER Metal2 ; + RECT 102.36 0 102.62 0.26 ; + END + END A_ADDR[6] + PIN A_BIST_ADDR[6] + DIRECTION INPUT ; + USE SIGNAL ; + ANTENNAPARTIALMETALAREA 10.6771 LAYER Metal2 ; + ANTENNAMODEL OXIDE1 ; + ANTENNAGATEAREA 0.20085 LAYER Metal2 ; + ANTENNAMAXAREACAR 54.065721 LAYER Metal2 ; + PORT + LAYER Metal2 ; + RECT 102.87 0 103.13 0.26 ; + END + END A_BIST_ADDR[6] + PIN A_ADDR[7] + DIRECTION INPUT ; + USE SIGNAL ; + ANTENNAPARTIALMETALAREA 12.4163 LAYER Metal2 ; + ANTENNAMODEL OXIDE1 ; + ANTENNAGATEAREA 0.20085 LAYER Metal2 ; + ANTENNAMAXAREACAR 62.724919 LAYER Metal2 ; + PORT + LAYER Metal2 ; + RECT 103.38 0 103.64 0.26 ; + END + END A_ADDR[7] + PIN A_BIST_ADDR[7] + DIRECTION INPUT ; + USE SIGNAL ; + ANTENNAPARTIALMETALAREA 12.1511 LAYER Metal2 ; + ANTENNAMODEL OXIDE1 ; + ANTENNAGATEAREA 0.20085 LAYER Metal2 ; + ANTENNAMAXAREACAR 61.404531 LAYER Metal2 ; + PORT + LAYER Metal2 ; + RECT 103.89 0 104.15 0.26 ; + END + END A_BIST_ADDR[7] + PIN A_ADDR[8] + DIRECTION INPUT ; + USE SIGNAL ; + ANTENNAPARTIALMETALAREA 10.3675 LAYER Metal2 ; + ANTENNAPARTIALMETALAREA 1.5897 LAYER Metal3 ; + ANTENNAPARTIALCUTAREA 0.0722 LAYER Via2 ; + ANTENNAMODEL OXIDE1 ; + ANTENNAGATEAREA 0.20085 LAYER Metal3 ; + ANTENNAMAXAREACAR 9.740105 LAYER Metal3 ; + PORT + LAYER Metal2 ; + RECT 132.45 0 132.71 0.26 ; + END + END A_ADDR[8] + PIN A_BIST_ADDR[8] + DIRECTION INPUT ; + USE SIGNAL ; + ANTENNAPARTIALMETALAREA 10.3675 LAYER Metal2 ; + ANTENNAPARTIALMETALAREA 1.3755 LAYER Metal3 ; + ANTENNAPARTIALCUTAREA 0.0722 LAYER Via2 ; + ANTENNAMODEL OXIDE1 ; + ANTENNAGATEAREA 0.20085 LAYER Metal3 ; + ANTENNAMAXAREACAR 9.204381 LAYER Metal3 ; + PORT + LAYER Metal2 ; + RECT 132.96 0 133.22 0.26 ; + END + END A_BIST_ADDR[8] + PIN A_CLK + DIRECTION INPUT ; + USE SIGNAL ; + ANTENNAPARTIALMETALAREA 4.0547 LAYER Metal2 ; + ANTENNAMODEL OXIDE1 ; + ANTENNAGATEAREA 0.20085 LAYER Metal2 ; + ANTENNAMAXAREACAR 21.093851 LAYER Metal2 ; + PORT + LAYER Metal2 ; + RECT 112.56 0 112.82 0.26 ; + END + END A_CLK + PIN A_REN + DIRECTION INPUT ; + USE SIGNAL ; + ANTENNAPARTIALMETALAREA 3.99505 LAYER Metal2 ; + ANTENNAMODEL OXIDE1 ; + ANTENNAGATEAREA 0.20085 LAYER Metal2 ; + ANTENNAMAXAREACAR 20.796863 LAYER Metal2 ; + PORT + LAYER Metal2 ; + RECT 116.13 0 116.39 0.26 ; + END + END A_REN + PIN A_WEN + DIRECTION INPUT ; + USE SIGNAL ; + ANTENNAPARTIALMETALAREA 2.8847 LAYER Metal2 ; + ANTENNAMODEL OXIDE1 ; + ANTENNAGATEAREA 0.20085 LAYER Metal2 ; + ANTENNAMAXAREACAR 15.268608 LAYER Metal2 ; + PORT + LAYER Metal2 ; + RECT 115.62 0 115.88 0.26 ; + END + END A_WEN + PIN A_MEN + DIRECTION INPUT ; + USE SIGNAL ; + ANTENNAPARTIALMETALAREA 3.0247 LAYER Metal2 ; + ANTENNAMODEL OXIDE1 ; + ANTENNAGATEAREA 0.20085 LAYER Metal2 ; + ANTENNAMAXAREACAR 15.965646 LAYER Metal2 ; + PORT + LAYER Metal2 ; + RECT 113.07 0 113.33 0.26 ; + END + END A_MEN + PIN A_DLY + DIRECTION INPUT ; + USE SIGNAL ; + ANTENNAPARTIALMETALAREA 6.058 LAYER Metal2 ; + ANTENNAMODEL OXIDE1 ; + ANTENNAGATEAREA 0.3367 LAYER Metal2 ; + ANTENNAMAXAREACAR 18.532819 LAYER Metal2 ; + PORT + LAYER Metal2 ; + RECT 134.49 0 134.75 0.26 ; + END + END A_DLY + PIN A_BIST_EN + DIRECTION INPUT ; + USE SIGNAL ; + ANTENNAPARTIALMETALAREA 3.9871 LAYER Metal2 ; + ANTENNAPARTIALMETALAREA 114.62575 LAYER Metal3 ; + ANTENNAPARTIALCUTAREA 0.0722 LAYER Via2 ; + ANTENNAMODEL OXIDE1 ; + ANTENNAGATEAREA 1.43 LAYER Metal2 ; + ANTENNAGATEAREA 16.0875 LAYER Metal3 ; + ANTENNAMAXAREACAR 3.213636 LAYER Metal2 ; + ANTENNAMAXAREACAR 17.397871 LAYER Metal3 ; + ANTENNAMAXCUTCAR 0.151469 LAYER Via2 ; + PORT + LAYER Metal2 ; + RECT 115.11 0 115.37 0.26 ; + END + END A_BIST_EN + PIN A_BIST_CLK + DIRECTION INPUT ; + USE SIGNAL ; + ANTENNAPARTIALMETALAREA 4.1639 LAYER Metal2 ; + ANTENNAMODEL OXIDE1 ; + ANTENNAGATEAREA 0.20085 LAYER Metal2 ; + ANTENNAMAXAREACAR 21.953448 LAYER Metal2 ; + PORT + LAYER Metal2 ; + RECT 111.03 0 111.29 0.26 ; + END + END A_BIST_CLK + PIN A_BIST_REN + DIRECTION INPUT ; + USE SIGNAL ; + ANTENNAPARTIALMETALAREA 4.1119 LAYER Metal2 ; + ANTENNAMODEL OXIDE1 ; + ANTENNAGATEAREA 0.20085 LAYER Metal2 ; + ANTENNAMAXAREACAR 21.694548 LAYER Metal2 ; + PORT + LAYER Metal2 ; + RECT 117.66 0 117.92 0.26 ; + END + END A_BIST_REN + PIN A_BIST_WEN + DIRECTION INPUT ; + USE SIGNAL ; + ANTENNAPARTIALMETALAREA 2.9051 LAYER Metal2 ; + ANTENNAMODEL OXIDE1 ; + ANTENNAGATEAREA 0.20085 LAYER Metal2 ; + ANTENNAMAXAREACAR 15.686084 LAYER Metal2 ; + PORT + LAYER Metal2 ; + RECT 117.15 0 117.41 0.26 ; + END + END A_BIST_WEN + PIN A_BIST_MEN + DIRECTION INPUT ; + USE SIGNAL ; + ANTENNAPARTIALMETALAREA 2.8977 LAYER Metal2 ; + ANTENNAMODEL OXIDE1 ; + ANTENNAGATEAREA 0.20085 LAYER Metal2 ; + ANTENNAMAXAREACAR 15.649241 LAYER Metal2 ; + PORT + LAYER Metal2 ; + RECT 111.54 0 111.8 0.26 ; + END + END A_BIST_MEN + OBS + LAYER Metal1 ; + RECT 0 0 236.8 191.34 ; + LAYER Metal2 ; + RECT 0.105 45.465 0.305 191.315 ; + RECT 1.1 190.585 1.3 191.315 ; + RECT 3.29 0.52 3.55 5.16 ; + RECT 2.77 4.9 3.55 5.16 ; + RECT 2.77 4.9 3.03 6.64 ; + RECT 1.92 190.585 2.12 191.315 ; + RECT 2.415 190.585 2.615 191.315 ; + RECT 2.915 190.585 3.115 191.315 ; + RECT 3.415 190.585 3.615 191.315 ; + RECT 3.91 190.585 4.11 191.315 ; + RECT 4.655 0.17 5.425 0.94 ; + RECT 4.655 0.17 4.915 12.9 ; + RECT 5.165 0.17 5.425 12.9 ; + RECT 4.145 0.52 4.405 5.815 ; + RECT 4.73 190.585 4.93 191.315 ; + RECT 5.675 0.17 6.445 0.43 ; + RECT 5.675 0.17 5.935 11.5 ; + RECT 6.185 0.17 6.445 11.5 ; + RECT 5.225 190.585 5.425 191.315 ; + RECT 5.725 190.585 5.925 191.315 ; + RECT 6.225 190.585 6.425 191.315 ; + RECT 7.715 0.17 8.485 0.43 ; + RECT 7.715 0.17 7.975 10.48 ; + RECT 8.225 0.17 8.485 10.99 ; + RECT 6.72 190.585 6.92 191.315 ; + RECT 7.54 190.585 7.74 191.315 ; + RECT 8.735 0.17 9.505 0.94 ; + RECT 8.735 0.17 8.995 8.7 ; + RECT 9.245 0.17 9.505 12.9 ; + RECT 8.035 190.585 8.235 191.315 ; + RECT 8.535 190.585 8.735 191.315 ; + RECT 9.035 190.585 9.235 191.315 ; + RECT 9.53 190.585 9.73 191.315 ; + RECT 9.755 0.52 10.015 2.485 ; + RECT 10.35 190.585 10.55 191.315 ; + RECT 10.62 0.52 10.88 14.11 ; + RECT 10.845 190.585 11.045 191.315 ; + RECT 11.13 0.52 11.39 2.335 ; + RECT 11.345 190.585 11.545 191.315 ; + RECT 11.845 190.585 12.045 191.315 ; + RECT 12.34 190.585 12.54 191.315 ; + RECT 14.53 0.52 14.79 5.16 ; + RECT 14.01 4.9 14.79 5.16 ; + RECT 14.01 4.9 14.27 6.64 ; + RECT 13.16 190.585 13.36 191.315 ; + RECT 13.655 190.585 13.855 191.315 ; + RECT 14.155 190.585 14.355 191.315 ; + RECT 14.655 190.585 14.855 191.315 ; + RECT 15.15 190.585 15.35 191.315 ; + RECT 15.895 0.17 16.665 0.94 ; + RECT 15.895 0.17 16.155 12.9 ; + RECT 16.405 0.17 16.665 12.9 ; + RECT 15.385 0.52 15.645 5.815 ; + RECT 15.97 190.585 16.17 191.315 ; + RECT 16.915 0.17 17.685 0.43 ; + RECT 16.915 0.17 17.175 11.5 ; + RECT 17.425 0.17 17.685 11.5 ; + RECT 16.465 190.585 16.665 191.315 ; + RECT 16.965 190.585 17.165 191.315 ; + RECT 17.465 190.585 17.665 191.315 ; + RECT 18.955 0.17 19.725 0.43 ; + RECT 18.955 0.17 19.215 10.48 ; + RECT 19.465 0.17 19.725 10.99 ; + RECT 17.96 190.585 18.16 191.315 ; + RECT 18.78 190.585 18.98 191.315 ; + RECT 19.975 0.17 20.745 0.94 ; + RECT 19.975 0.17 20.235 8.7 ; + RECT 20.485 0.17 20.745 12.9 ; + RECT 19.275 190.585 19.475 191.315 ; + RECT 19.775 190.585 19.975 191.315 ; + RECT 20.275 190.585 20.475 191.315 ; + RECT 20.77 190.585 20.97 191.315 ; + RECT 20.995 0.52 21.255 2.485 ; + RECT 21.59 190.585 21.79 191.315 ; + RECT 21.86 0.52 22.12 14.11 ; + RECT 22.085 190.585 22.285 191.315 ; + RECT 22.37 0.52 22.63 2.335 ; + RECT 22.585 190.585 22.785 191.315 ; + RECT 23.085 190.585 23.285 191.315 ; + RECT 23.58 190.585 23.78 191.315 ; + RECT 25.77 0.52 26.03 5.16 ; + RECT 25.25 4.9 26.03 5.16 ; + RECT 25.25 4.9 25.51 6.64 ; + RECT 24.4 190.585 24.6 191.315 ; + RECT 24.895 190.585 25.095 191.315 ; + RECT 25.395 190.585 25.595 191.315 ; + RECT 25.895 190.585 26.095 191.315 ; + RECT 26.39 190.585 26.59 191.315 ; + RECT 27.135 0.17 27.905 0.94 ; + RECT 27.135 0.17 27.395 12.9 ; + RECT 27.645 0.17 27.905 12.9 ; + RECT 26.625 0.52 26.885 5.815 ; + RECT 27.21 190.585 27.41 191.315 ; + RECT 28.155 0.17 28.925 0.43 ; + RECT 28.155 0.17 28.415 11.5 ; + RECT 28.665 0.17 28.925 11.5 ; + RECT 27.705 190.585 27.905 191.315 ; + RECT 28.205 190.585 28.405 191.315 ; + RECT 28.705 190.585 28.905 191.315 ; + RECT 30.195 0.17 30.965 0.43 ; + RECT 30.195 0.17 30.455 10.48 ; + RECT 30.705 0.17 30.965 10.99 ; + RECT 29.2 190.585 29.4 191.315 ; + RECT 30.02 190.585 30.22 191.315 ; + RECT 31.215 0.17 31.985 0.94 ; + RECT 31.215 0.17 31.475 8.7 ; + RECT 31.725 0.17 31.985 12.9 ; + RECT 30.515 190.585 30.715 191.315 ; + RECT 31.015 190.585 31.215 191.315 ; + RECT 31.515 190.585 31.715 191.315 ; + RECT 32.01 190.585 32.21 191.315 ; + RECT 32.235 0.52 32.495 2.485 ; + RECT 32.83 190.585 33.03 191.315 ; + RECT 33.1 0.52 33.36 14.11 ; + RECT 33.325 190.585 33.525 191.315 ; + RECT 33.61 0.52 33.87 2.335 ; + RECT 33.825 190.585 34.025 191.315 ; + RECT 34.325 190.585 34.525 191.315 ; + RECT 34.82 190.585 35.02 191.315 ; + RECT 37.01 0.52 37.27 5.16 ; + RECT 36.49 4.9 37.27 5.16 ; + RECT 36.49 4.9 36.75 6.64 ; + RECT 35.64 190.585 35.84 191.315 ; + RECT 36.135 190.585 36.335 191.315 ; + RECT 36.635 190.585 36.835 191.315 ; + RECT 37.135 190.585 37.335 191.315 ; + RECT 37.63 190.585 37.83 191.315 ; + RECT 38.375 0.17 39.145 0.94 ; + RECT 38.375 0.17 38.635 12.9 ; + RECT 38.885 0.17 39.145 12.9 ; + RECT 37.865 0.52 38.125 5.815 ; + RECT 38.45 190.585 38.65 191.315 ; + RECT 39.395 0.17 40.165 0.43 ; + RECT 39.395 0.17 39.655 11.5 ; + RECT 39.905 0.17 40.165 11.5 ; + RECT 38.945 190.585 39.145 191.315 ; + RECT 39.445 190.585 39.645 191.315 ; + RECT 39.945 190.585 40.145 191.315 ; + RECT 41.435 0.17 42.205 0.43 ; + RECT 41.435 0.17 41.695 10.48 ; + RECT 41.945 0.17 42.205 10.99 ; + RECT 40.44 190.585 40.64 191.315 ; + RECT 41.26 190.585 41.46 191.315 ; + RECT 42.455 0.17 43.225 0.94 ; + RECT 42.455 0.17 42.715 8.7 ; + RECT 42.965 0.17 43.225 12.9 ; + RECT 41.755 190.585 41.955 191.315 ; + RECT 42.255 190.585 42.455 191.315 ; + RECT 42.755 190.585 42.955 191.315 ; + RECT 43.25 190.585 43.45 191.315 ; + RECT 43.475 0.52 43.735 2.485 ; + RECT 44.07 190.585 44.27 191.315 ; + RECT 44.34 0.52 44.6 14.11 ; + RECT 44.565 190.585 44.765 191.315 ; + RECT 44.85 0.52 45.11 2.335 ; + RECT 45.065 190.585 45.265 191.315 ; + RECT 45.565 190.585 45.765 191.315 ; + RECT 46.06 190.585 46.26 191.315 ; + RECT 48.25 0.52 48.51 5.16 ; + RECT 47.73 4.9 48.51 5.16 ; + RECT 47.73 4.9 47.99 6.64 ; + RECT 46.88 190.585 47.08 191.315 ; + RECT 47.375 190.585 47.575 191.315 ; + RECT 47.875 190.585 48.075 191.315 ; + RECT 48.375 190.585 48.575 191.315 ; + RECT 48.87 190.585 49.07 191.315 ; + RECT 49.615 0.17 50.385 0.94 ; + RECT 49.615 0.17 49.875 12.9 ; + RECT 50.125 0.17 50.385 12.9 ; + RECT 49.105 0.52 49.365 5.815 ; + RECT 49.69 190.585 49.89 191.315 ; + RECT 50.635 0.17 51.405 0.43 ; + RECT 50.635 0.17 50.895 11.5 ; + RECT 51.145 0.17 51.405 11.5 ; + RECT 50.185 190.585 50.385 191.315 ; + RECT 50.685 190.585 50.885 191.315 ; + RECT 51.185 190.585 51.385 191.315 ; + RECT 52.675 0.17 53.445 0.43 ; + RECT 52.675 0.17 52.935 10.48 ; + RECT 53.185 0.17 53.445 10.99 ; + RECT 51.68 190.585 51.88 191.315 ; + RECT 52.5 190.585 52.7 191.315 ; + RECT 53.695 0.17 54.465 0.94 ; + RECT 53.695 0.17 53.955 8.7 ; + RECT 54.205 0.17 54.465 12.9 ; + RECT 52.995 190.585 53.195 191.315 ; + RECT 53.495 190.585 53.695 191.315 ; + RECT 53.995 190.585 54.195 191.315 ; + RECT 54.49 190.585 54.69 191.315 ; + RECT 54.715 0.52 54.975 2.485 ; + RECT 55.31 190.585 55.51 191.315 ; + RECT 55.58 0.52 55.84 14.11 ; + RECT 55.805 190.585 56.005 191.315 ; + RECT 56.09 0.52 56.35 2.335 ; + RECT 56.305 190.585 56.505 191.315 ; + RECT 56.805 190.585 57.005 191.315 ; + RECT 57.3 190.585 57.5 191.315 ; + RECT 59.49 0.52 59.75 5.16 ; + RECT 58.97 4.9 59.75 5.16 ; + RECT 58.97 4.9 59.23 6.64 ; + RECT 58.12 190.585 58.32 191.315 ; + RECT 58.615 190.585 58.815 191.315 ; + RECT 59.115 190.585 59.315 191.315 ; + RECT 59.615 190.585 59.815 191.315 ; + RECT 60.11 190.585 60.31 191.315 ; + RECT 60.855 0.17 61.625 0.94 ; + RECT 60.855 0.17 61.115 12.9 ; + RECT 61.365 0.17 61.625 12.9 ; + RECT 60.345 0.52 60.605 5.815 ; + RECT 60.93 190.585 61.13 191.315 ; + RECT 61.875 0.17 62.645 0.43 ; + RECT 61.875 0.17 62.135 11.5 ; + RECT 62.385 0.17 62.645 11.5 ; + RECT 61.425 190.585 61.625 191.315 ; + RECT 61.925 190.585 62.125 191.315 ; + RECT 62.425 190.585 62.625 191.315 ; + RECT 63.915 0.17 64.685 0.43 ; + RECT 63.915 0.17 64.175 10.48 ; + RECT 64.425 0.17 64.685 10.99 ; + RECT 62.92 190.585 63.12 191.315 ; + RECT 63.74 190.585 63.94 191.315 ; + RECT 64.935 0.17 65.705 0.94 ; + RECT 64.935 0.17 65.195 8.7 ; + RECT 65.445 0.17 65.705 12.9 ; + RECT 64.235 190.585 64.435 191.315 ; + RECT 64.735 190.585 64.935 191.315 ; + RECT 65.235 190.585 65.435 191.315 ; + RECT 65.73 190.585 65.93 191.315 ; + RECT 65.955 0.52 66.215 2.485 ; + RECT 66.55 190.585 66.75 191.315 ; + RECT 66.82 0.52 67.08 14.11 ; + RECT 67.045 190.585 67.245 191.315 ; + RECT 67.33 0.52 67.59 2.335 ; + RECT 67.545 190.585 67.745 191.315 ; + RECT 68.045 190.585 68.245 191.315 ; + RECT 68.54 190.585 68.74 191.315 ; + RECT 70.73 0.52 70.99 5.16 ; + RECT 70.21 4.9 70.99 5.16 ; + RECT 70.21 4.9 70.47 6.64 ; + RECT 69.36 190.585 69.56 191.315 ; + RECT 69.855 190.585 70.055 191.315 ; + RECT 70.355 190.585 70.555 191.315 ; + RECT 70.855 190.585 71.055 191.315 ; + RECT 71.35 190.585 71.55 191.315 ; + RECT 72.095 0.17 72.865 0.94 ; + RECT 72.095 0.17 72.355 12.9 ; + RECT 72.605 0.17 72.865 12.9 ; + RECT 71.585 0.52 71.845 5.815 ; + RECT 72.17 190.585 72.37 191.315 ; + RECT 73.115 0.17 73.885 0.43 ; + RECT 73.115 0.17 73.375 11.5 ; + RECT 73.625 0.17 73.885 11.5 ; + RECT 72.665 190.585 72.865 191.315 ; + RECT 73.165 190.585 73.365 191.315 ; + RECT 73.665 190.585 73.865 191.315 ; + RECT 75.155 0.17 75.925 0.43 ; + RECT 75.155 0.17 75.415 10.48 ; + RECT 75.665 0.17 75.925 10.99 ; + RECT 74.16 190.585 74.36 191.315 ; + RECT 74.98 190.585 75.18 191.315 ; + RECT 76.175 0.17 76.945 0.94 ; + RECT 76.175 0.17 76.435 8.7 ; + RECT 76.685 0.17 76.945 12.9 ; + RECT 75.475 190.585 75.675 191.315 ; + RECT 75.975 190.585 76.175 191.315 ; + RECT 76.475 190.585 76.675 191.315 ; + RECT 76.97 190.585 77.17 191.315 ; + RECT 77.195 0.52 77.455 2.485 ; + RECT 77.79 190.585 77.99 191.315 ; + RECT 78.06 0.52 78.32 14.11 ; + RECT 78.285 190.585 78.485 191.315 ; + RECT 78.57 0.52 78.83 2.335 ; + RECT 78.785 190.585 78.985 191.315 ; + RECT 79.285 190.585 79.485 191.315 ; + RECT 79.78 190.585 79.98 191.315 ; + RECT 81.97 0.52 82.23 5.16 ; + RECT 81.45 4.9 82.23 5.16 ; + RECT 81.45 4.9 81.71 6.64 ; + RECT 80.6 190.585 80.8 191.315 ; + RECT 81.095 190.585 81.295 191.315 ; + RECT 81.595 190.585 81.795 191.315 ; + RECT 82.095 190.585 82.295 191.315 ; + RECT 82.59 190.585 82.79 191.315 ; + RECT 83.335 0.17 84.105 0.94 ; + RECT 83.335 0.17 83.595 12.9 ; + RECT 83.845 0.17 84.105 12.9 ; + RECT 82.825 0.52 83.085 5.815 ; + RECT 83.41 190.585 83.61 191.315 ; + RECT 84.355 0.17 85.125 0.43 ; + RECT 84.355 0.17 84.615 11.5 ; + RECT 84.865 0.17 85.125 11.5 ; + RECT 83.905 190.585 84.105 191.315 ; + RECT 84.405 190.585 84.605 191.315 ; + RECT 84.905 190.585 85.105 191.315 ; + RECT 86.395 0.17 87.165 0.43 ; + RECT 86.395 0.17 86.655 10.48 ; + RECT 86.905 0.17 87.165 10.99 ; + RECT 85.4 190.585 85.6 191.315 ; + RECT 86.22 190.585 86.42 191.315 ; + RECT 87.415 0.17 88.185 0.94 ; + RECT 87.415 0.17 87.675 8.7 ; + RECT 87.925 0.17 88.185 12.9 ; + RECT 86.715 190.585 86.915 191.315 ; + RECT 87.215 190.585 87.415 191.315 ; + RECT 87.715 190.585 87.915 191.315 ; + RECT 88.21 190.585 88.41 191.315 ; + RECT 88.435 0.52 88.695 2.485 ; + RECT 89.03 190.585 89.23 191.315 ; + RECT 89.3 0.52 89.56 14.11 ; + RECT 89.525 190.585 89.725 191.315 ; + RECT 89.81 0.52 90.07 2.335 ; + RECT 90.025 190.585 90.225 191.315 ; + RECT 90.525 190.585 90.725 191.315 ; + RECT 92.515 0.17 93.285 0.43 ; + RECT 92.515 0.17 92.775 8.7 ; + RECT 93.025 0.17 93.285 8.7 ; + RECT 93.535 0.17 94.305 0.94 ; + RECT 93.535 0.17 93.795 8.7 ; + RECT 94.045 0.17 94.305 8.7 ; + RECT 94.555 0.17 95.325 0.43 ; + RECT 94.555 0.17 94.815 8.7 ; + RECT 95.065 0.17 95.325 8.7 ; + RECT 95.575 0.17 96.345 0.94 ; + RECT 95.575 0.17 95.835 8.7 ; + RECT 96.085 0.17 96.345 8.7 ; + RECT 96.595 0.17 97.365 0.43 ; + RECT 96.595 0.17 96.855 8.7 ; + RECT 97.105 0.17 97.365 8.7 ; + RECT 97.615 0.17 98.385 0.94 ; + RECT 97.615 0.17 97.875 8.7 ; + RECT 98.125 0.17 98.385 8.7 ; + RECT 91.02 190.585 91.22 191.315 ; + RECT 91.84 190.585 92.04 191.315 ; + RECT 92.835 190.585 93.035 191.315 ; + RECT 100.32 0.17 101.09 0.94 ; + RECT 100.32 0.17 100.58 8.7 ; + RECT 100.83 0.17 101.09 8.7 ; + RECT 98.79 0.3 99.05 8.7 ; + RECT 99.3 0 99.56 8.7 ; + RECT 99.81 0 100.07 8.7 ; + RECT 101.34 0 101.6 8.7 ; + RECT 101.85 0 102.11 8.7 ; + RECT 102.36 0.52 102.62 8.7 ; + RECT 102.87 0.52 103.13 8.7 ; + RECT 103.38 0.52 103.64 8.7 ; + RECT 105.42 0.17 106.19 0.94 ; + RECT 105.42 0.17 105.68 8.7 ; + RECT 105.93 0.17 106.19 8.7 ; + RECT 106.44 0.17 107.21 0.43 ; + RECT 106.44 0.17 106.7 8.7 ; + RECT 106.95 0.17 107.21 8.7 ; + RECT 103.89 0.52 104.15 8.7 ; + RECT 104.4 0 104.66 8.7 ; + RECT 104.91 0 105.17 8.7 ; + RECT 107.46 0.3 107.72 8.7 ; + RECT 107.97 0.3 108.23 8.7 ; + RECT 110.01 0.17 110.78 0.94 ; + RECT 110.01 0.17 110.27 8.7 ; + RECT 110.52 0.17 110.78 8.7 ; + RECT 108.48 0.3 108.74 8.7 ; + RECT 108.99 0.3 109.25 8.7 ; + RECT 109.5 0.3 109.76 8.7 ; + RECT 111.03 0.52 111.29 8.7 ; + RECT 111.54 0.52 111.8 8.7 ; + RECT 112.05 0.3 112.31 8.7 ; + RECT 112.56 0.52 112.82 8.7 ; + RECT 113.07 0.52 113.33 8.7 ; + RECT 113.58 0.3 113.84 8.7 ; + RECT 114.09 0.52 114.35 8.7 ; + RECT 114.6 0.52 114.86 8.7 ; + RECT 115.11 0.52 115.37 8.7 ; + RECT 115.62 0.52 115.88 8.7 ; + RECT 116.13 0.52 116.39 8.7 ; + RECT 116.64 0.3 116.9 8.7 ; + RECT 117.15 0.52 117.41 8.7 ; + RECT 117.66 0.52 117.92 8.7 ; + RECT 118.17 0.3 118.43 8.7 ; + RECT 120.21 0.17 120.98 0.94 ; + RECT 120.21 0.17 120.47 8.7 ; + RECT 120.72 0.17 120.98 8.7 ; + RECT 118.68 0.52 118.94 8.7 ; + RECT 119.19 0.52 119.45 8.7 ; + RECT 119.7 0.3 119.96 8.7 ; + RECT 121.23 0.52 121.49 8.7 ; + RECT 121.74 0.52 122 8.7 ; + RECT 122.25 0.52 122.51 8.7 ; + RECT 122.76 0.52 123.02 8.7 ; + RECT 123.27 0.52 123.53 8.7 ; + RECT 123.78 0.52 124.04 8.7 ; + RECT 124.29 0.52 124.55 8.7 ; + RECT 126.33 0.17 127.1 0.94 ; + RECT 126.33 0.17 126.59 8.7 ; + RECT 126.84 0.17 127.1 8.7 ; + RECT 124.8 0.52 125.06 8.7 ; + RECT 125.31 0 125.57 8.7 ; + RECT 125.82 0 126.08 8.7 ; + RECT 127.35 0 127.61 8.7 ; + RECT 129.39 0.17 130.16 0.43 ; + RECT 129.39 0.17 129.65 8.7 ; + RECT 129.9 0.17 130.16 8.7 ; + RECT 127.86 0 128.12 8.7 ; + RECT 128.37 0.3 128.63 8.7 ; + RECT 128.88 0.3 129.14 8.7 ; + RECT 130.41 0.3 130.67 8.7 ; + RECT 130.92 0.3 131.18 8.7 ; + RECT 131.43 0.3 131.69 8.7 ; + RECT 131.94 0.3 132.2 8.7 ; + RECT 132.45 0.52 132.71 8.7 ; + RECT 132.96 0.52 133.22 8.7 ; + RECT 135 0.17 135.77 0.43 ; + RECT 135 0.17 135.26 8.7 ; + RECT 135.51 0.17 135.77 8.7 ; + RECT 136.02 0.17 136.79 0.94 ; + RECT 136.02 0.17 136.28 25.5 ; + RECT 136.53 0.17 136.79 33.9 ; + RECT 137.04 0.17 137.81 0.43 ; + RECT 137.04 0.17 137.3 8.7 ; + RECT 137.55 0.17 137.81 8.7 ; + RECT 138.415 0.17 139.185 0.94 ; + RECT 138.415 0.17 138.675 8.7 ; + RECT 138.925 0.17 139.185 8.7 ; + RECT 139.435 0.17 140.205 0.43 ; + RECT 139.435 0.17 139.695 8.7 ; + RECT 139.945 0.17 140.205 8.7 ; + RECT 140.455 0.17 141.225 0.94 ; + RECT 140.455 0.17 140.715 8.7 ; + RECT 140.965 0.17 141.225 8.7 ; + RECT 141.475 0.17 142.245 0.43 ; + RECT 141.475 0.17 141.735 8.7 ; + RECT 141.985 0.17 142.245 8.7 ; + RECT 142.495 0.17 143.265 0.94 ; + RECT 142.495 0.17 142.755 8.7 ; + RECT 143.005 0.17 143.265 8.7 ; + RECT 133.47 0.3 133.73 8.7 ; + RECT 143.515 0.17 144.285 0.43 ; + RECT 143.515 0.17 143.775 8.7 ; + RECT 144.025 0.17 144.285 8.7 ; + RECT 133.98 0.3 134.24 8.7 ; + RECT 134.49 0.52 134.75 8.7 ; + RECT 143.765 190.585 143.965 191.315 ; + RECT 144.76 190.585 144.96 191.315 ; + RECT 145.58 190.585 145.78 191.315 ; + RECT 146.075 190.585 146.275 191.315 ; + RECT 146.575 190.585 146.775 191.315 ; + RECT 146.73 0.52 146.99 2.335 ; + RECT 147.075 190.585 147.275 191.315 ; + RECT 147.24 0.52 147.5 14.11 ; + RECT 147.57 190.585 147.77 191.315 ; + RECT 148.615 0.17 149.385 0.94 ; + RECT 149.125 0.17 149.385 8.7 ; + RECT 148.615 0.17 148.875 12.9 ; + RECT 148.105 0.52 148.365 2.485 ; + RECT 148.39 190.585 148.59 191.315 ; + RECT 149.635 0.17 150.405 0.43 ; + RECT 150.145 0.17 150.405 10.48 ; + RECT 149.635 0.17 149.895 10.99 ; + RECT 148.885 190.585 149.085 191.315 ; + RECT 149.385 190.585 149.585 191.315 ; + RECT 149.885 190.585 150.085 191.315 ; + RECT 150.38 190.585 150.58 191.315 ; + RECT 151.675 0.17 152.445 0.43 ; + RECT 151.675 0.17 151.935 11.5 ; + RECT 152.185 0.17 152.445 11.5 ; + RECT 151.2 190.585 151.4 191.315 ; + RECT 151.695 190.585 151.895 191.315 ; + RECT 152.695 0.17 153.465 0.94 ; + RECT 152.695 0.17 152.955 12.9 ; + RECT 153.205 0.17 153.465 12.9 ; + RECT 152.195 190.585 152.395 191.315 ; + RECT 152.695 190.585 152.895 191.315 ; + RECT 153.19 190.585 153.39 191.315 ; + RECT 153.715 0.52 153.975 5.815 ; + RECT 154.57 0.52 154.83 5.16 ; + RECT 154.57 4.9 155.35 5.16 ; + RECT 155.09 4.9 155.35 6.64 ; + RECT 154.01 190.585 154.21 191.315 ; + RECT 154.505 190.585 154.705 191.315 ; + RECT 155.005 190.585 155.205 191.315 ; + RECT 155.505 190.585 155.705 191.315 ; + RECT 156 190.585 156.2 191.315 ; + RECT 156.82 190.585 157.02 191.315 ; + RECT 157.315 190.585 157.515 191.315 ; + RECT 157.815 190.585 158.015 191.315 ; + RECT 157.97 0.52 158.23 2.335 ; + RECT 158.315 190.585 158.515 191.315 ; + RECT 158.48 0.52 158.74 14.11 ; + RECT 158.81 190.585 159.01 191.315 ; + RECT 159.855 0.17 160.625 0.94 ; + RECT 160.365 0.17 160.625 8.7 ; + RECT 159.855 0.17 160.115 12.9 ; + RECT 159.345 0.52 159.605 2.485 ; + RECT 159.63 190.585 159.83 191.315 ; + RECT 160.875 0.17 161.645 0.43 ; + RECT 161.385 0.17 161.645 10.48 ; + RECT 160.875 0.17 161.135 10.99 ; + RECT 160.125 190.585 160.325 191.315 ; + RECT 160.625 190.585 160.825 191.315 ; + RECT 161.125 190.585 161.325 191.315 ; + RECT 161.62 190.585 161.82 191.315 ; + RECT 162.915 0.17 163.685 0.43 ; + RECT 162.915 0.17 163.175 11.5 ; + RECT 163.425 0.17 163.685 11.5 ; + RECT 162.44 190.585 162.64 191.315 ; + RECT 162.935 190.585 163.135 191.315 ; + RECT 163.935 0.17 164.705 0.94 ; + RECT 163.935 0.17 164.195 12.9 ; + RECT 164.445 0.17 164.705 12.9 ; + RECT 163.435 190.585 163.635 191.315 ; + RECT 163.935 190.585 164.135 191.315 ; + RECT 164.43 190.585 164.63 191.315 ; + RECT 164.955 0.52 165.215 5.815 ; + RECT 165.81 0.52 166.07 5.16 ; + RECT 165.81 4.9 166.59 5.16 ; + RECT 166.33 4.9 166.59 6.64 ; + RECT 165.25 190.585 165.45 191.315 ; + RECT 165.745 190.585 165.945 191.315 ; + RECT 166.245 190.585 166.445 191.315 ; + RECT 166.745 190.585 166.945 191.315 ; + RECT 167.24 190.585 167.44 191.315 ; + RECT 168.06 190.585 168.26 191.315 ; + RECT 168.555 190.585 168.755 191.315 ; + RECT 169.055 190.585 169.255 191.315 ; + RECT 169.21 0.52 169.47 2.335 ; + RECT 169.555 190.585 169.755 191.315 ; + RECT 169.72 0.52 169.98 14.11 ; + RECT 170.05 190.585 170.25 191.315 ; + RECT 171.095 0.17 171.865 0.94 ; + RECT 171.605 0.17 171.865 8.7 ; + RECT 171.095 0.17 171.355 12.9 ; + RECT 170.585 0.52 170.845 2.485 ; + RECT 170.87 190.585 171.07 191.315 ; + RECT 172.115 0.17 172.885 0.43 ; + RECT 172.625 0.17 172.885 10.48 ; + RECT 172.115 0.17 172.375 10.99 ; + RECT 171.365 190.585 171.565 191.315 ; + RECT 171.865 190.585 172.065 191.315 ; + RECT 172.365 190.585 172.565 191.315 ; + RECT 172.86 190.585 173.06 191.315 ; + RECT 174.155 0.17 174.925 0.43 ; + RECT 174.155 0.17 174.415 11.5 ; + RECT 174.665 0.17 174.925 11.5 ; + RECT 173.68 190.585 173.88 191.315 ; + RECT 174.175 190.585 174.375 191.315 ; + RECT 175.175 0.17 175.945 0.94 ; + RECT 175.175 0.17 175.435 12.9 ; + RECT 175.685 0.17 175.945 12.9 ; + RECT 174.675 190.585 174.875 191.315 ; + RECT 175.175 190.585 175.375 191.315 ; + RECT 175.67 190.585 175.87 191.315 ; + RECT 176.195 0.52 176.455 5.815 ; + RECT 177.05 0.52 177.31 5.16 ; + RECT 177.05 4.9 177.83 5.16 ; + RECT 177.57 4.9 177.83 6.64 ; + RECT 176.49 190.585 176.69 191.315 ; + RECT 176.985 190.585 177.185 191.315 ; + RECT 177.485 190.585 177.685 191.315 ; + RECT 177.985 190.585 178.185 191.315 ; + RECT 178.48 190.585 178.68 191.315 ; + RECT 179.3 190.585 179.5 191.315 ; + RECT 179.795 190.585 179.995 191.315 ; + RECT 180.295 190.585 180.495 191.315 ; + RECT 180.45 0.52 180.71 2.335 ; + RECT 180.795 190.585 180.995 191.315 ; + RECT 180.96 0.52 181.22 14.11 ; + RECT 181.29 190.585 181.49 191.315 ; + RECT 182.335 0.17 183.105 0.94 ; + RECT 182.845 0.17 183.105 8.7 ; + RECT 182.335 0.17 182.595 12.9 ; + RECT 181.825 0.52 182.085 2.485 ; + RECT 182.11 190.585 182.31 191.315 ; + RECT 183.355 0.17 184.125 0.43 ; + RECT 183.865 0.17 184.125 10.48 ; + RECT 183.355 0.17 183.615 10.99 ; + RECT 182.605 190.585 182.805 191.315 ; + RECT 183.105 190.585 183.305 191.315 ; + RECT 183.605 190.585 183.805 191.315 ; + RECT 184.1 190.585 184.3 191.315 ; + RECT 185.395 0.17 186.165 0.43 ; + RECT 185.395 0.17 185.655 11.5 ; + RECT 185.905 0.17 186.165 11.5 ; + RECT 184.92 190.585 185.12 191.315 ; + RECT 185.415 190.585 185.615 191.315 ; + RECT 186.415 0.17 187.185 0.94 ; + RECT 186.415 0.17 186.675 12.9 ; + RECT 186.925 0.17 187.185 12.9 ; + RECT 185.915 190.585 186.115 191.315 ; + RECT 186.415 190.585 186.615 191.315 ; + RECT 186.91 190.585 187.11 191.315 ; + RECT 187.435 0.52 187.695 5.815 ; + RECT 188.29 0.52 188.55 5.16 ; + RECT 188.29 4.9 189.07 5.16 ; + RECT 188.81 4.9 189.07 6.64 ; + RECT 187.73 190.585 187.93 191.315 ; + RECT 188.225 190.585 188.425 191.315 ; + RECT 188.725 190.585 188.925 191.315 ; + RECT 189.225 190.585 189.425 191.315 ; + RECT 189.72 190.585 189.92 191.315 ; + RECT 190.54 190.585 190.74 191.315 ; + RECT 191.035 190.585 191.235 191.315 ; + RECT 191.535 190.585 191.735 191.315 ; + RECT 191.69 0.52 191.95 2.335 ; + RECT 192.035 190.585 192.235 191.315 ; + RECT 192.2 0.52 192.46 14.11 ; + RECT 192.53 190.585 192.73 191.315 ; + RECT 193.575 0.17 194.345 0.94 ; + RECT 194.085 0.17 194.345 8.7 ; + RECT 193.575 0.17 193.835 12.9 ; + RECT 193.065 0.52 193.325 2.485 ; + RECT 193.35 190.585 193.55 191.315 ; + RECT 194.595 0.17 195.365 0.43 ; + RECT 195.105 0.17 195.365 10.48 ; + RECT 194.595 0.17 194.855 10.99 ; + RECT 193.845 190.585 194.045 191.315 ; + RECT 194.345 190.585 194.545 191.315 ; + RECT 194.845 190.585 195.045 191.315 ; + RECT 195.34 190.585 195.54 191.315 ; + RECT 196.635 0.17 197.405 0.43 ; + RECT 196.635 0.17 196.895 11.5 ; + RECT 197.145 0.17 197.405 11.5 ; + RECT 196.16 190.585 196.36 191.315 ; + RECT 196.655 190.585 196.855 191.315 ; + RECT 197.655 0.17 198.425 0.94 ; + RECT 197.655 0.17 197.915 12.9 ; + RECT 198.165 0.17 198.425 12.9 ; + RECT 197.155 190.585 197.355 191.315 ; + RECT 197.655 190.585 197.855 191.315 ; + RECT 198.15 190.585 198.35 191.315 ; + RECT 198.675 0.52 198.935 5.815 ; + RECT 199.53 0.52 199.79 5.16 ; + RECT 199.53 4.9 200.31 5.16 ; + RECT 200.05 4.9 200.31 6.64 ; + RECT 198.97 190.585 199.17 191.315 ; + RECT 199.465 190.585 199.665 191.315 ; + RECT 199.965 190.585 200.165 191.315 ; + RECT 200.465 190.585 200.665 191.315 ; + RECT 200.96 190.585 201.16 191.315 ; + RECT 201.78 190.585 201.98 191.315 ; + RECT 202.275 190.585 202.475 191.315 ; + RECT 202.775 190.585 202.975 191.315 ; + RECT 202.93 0.52 203.19 2.335 ; + RECT 203.275 190.585 203.475 191.315 ; + RECT 203.44 0.52 203.7 14.11 ; + RECT 203.77 190.585 203.97 191.315 ; + RECT 204.815 0.17 205.585 0.94 ; + RECT 205.325 0.17 205.585 8.7 ; + RECT 204.815 0.17 205.075 12.9 ; + RECT 204.305 0.52 204.565 2.485 ; + RECT 204.59 190.585 204.79 191.315 ; + RECT 205.835 0.17 206.605 0.43 ; + RECT 206.345 0.17 206.605 10.48 ; + RECT 205.835 0.17 206.095 10.99 ; + RECT 205.085 190.585 205.285 191.315 ; + RECT 205.585 190.585 205.785 191.315 ; + RECT 206.085 190.585 206.285 191.315 ; + RECT 206.58 190.585 206.78 191.315 ; + RECT 207.875 0.17 208.645 0.43 ; + RECT 207.875 0.17 208.135 11.5 ; + RECT 208.385 0.17 208.645 11.5 ; + RECT 207.4 190.585 207.6 191.315 ; + RECT 207.895 190.585 208.095 191.315 ; + RECT 208.895 0.17 209.665 0.94 ; + RECT 208.895 0.17 209.155 12.9 ; + RECT 209.405 0.17 209.665 12.9 ; + RECT 208.395 190.585 208.595 191.315 ; + RECT 208.895 190.585 209.095 191.315 ; + RECT 209.39 190.585 209.59 191.315 ; + RECT 209.915 0.52 210.175 5.815 ; + RECT 210.77 0.52 211.03 5.16 ; + RECT 210.77 4.9 211.55 5.16 ; + RECT 211.29 4.9 211.55 6.64 ; + RECT 210.21 190.585 210.41 191.315 ; + RECT 210.705 190.585 210.905 191.315 ; + RECT 211.205 190.585 211.405 191.315 ; + RECT 211.705 190.585 211.905 191.315 ; + RECT 212.2 190.585 212.4 191.315 ; + RECT 213.02 190.585 213.22 191.315 ; + RECT 213.515 190.585 213.715 191.315 ; + RECT 214.015 190.585 214.215 191.315 ; + RECT 214.17 0.52 214.43 2.335 ; + RECT 214.515 190.585 214.715 191.315 ; + RECT 214.68 0.52 214.94 14.11 ; + RECT 215.01 190.585 215.21 191.315 ; + RECT 216.055 0.17 216.825 0.94 ; + RECT 216.565 0.17 216.825 8.7 ; + RECT 216.055 0.17 216.315 12.9 ; + RECT 215.545 0.52 215.805 2.485 ; + RECT 215.83 190.585 216.03 191.315 ; + RECT 217.075 0.17 217.845 0.43 ; + RECT 217.585 0.17 217.845 10.48 ; + RECT 217.075 0.17 217.335 10.99 ; + RECT 216.325 190.585 216.525 191.315 ; + RECT 216.825 190.585 217.025 191.315 ; + RECT 217.325 190.585 217.525 191.315 ; + RECT 217.82 190.585 218.02 191.315 ; + RECT 219.115 0.17 219.885 0.43 ; + RECT 219.115 0.17 219.375 11.5 ; + RECT 219.625 0.17 219.885 11.5 ; + RECT 218.64 190.585 218.84 191.315 ; + RECT 219.135 190.585 219.335 191.315 ; + RECT 220.135 0.17 220.905 0.94 ; + RECT 220.135 0.17 220.395 12.9 ; + RECT 220.645 0.17 220.905 12.9 ; + RECT 219.635 190.585 219.835 191.315 ; + RECT 220.135 190.585 220.335 191.315 ; + RECT 220.63 190.585 220.83 191.315 ; + RECT 221.155 0.52 221.415 5.815 ; + RECT 222.01 0.52 222.27 5.16 ; + RECT 222.01 4.9 222.79 5.16 ; + RECT 222.53 4.9 222.79 6.64 ; + RECT 221.45 190.585 221.65 191.315 ; + RECT 221.945 190.585 222.145 191.315 ; + RECT 222.445 190.585 222.645 191.315 ; + RECT 222.945 190.585 223.145 191.315 ; + RECT 223.44 190.585 223.64 191.315 ; + RECT 224.26 190.585 224.46 191.315 ; + RECT 224.755 190.585 224.955 191.315 ; + RECT 225.255 190.585 225.455 191.315 ; + RECT 225.41 0.52 225.67 2.335 ; + RECT 225.755 190.585 225.955 191.315 ; + RECT 225.92 0.52 226.18 14.11 ; + RECT 226.25 190.585 226.45 191.315 ; + RECT 227.295 0.17 228.065 0.94 ; + RECT 227.805 0.17 228.065 8.7 ; + RECT 227.295 0.17 227.555 12.9 ; + RECT 226.785 0.52 227.045 2.485 ; + RECT 227.07 190.585 227.27 191.315 ; + RECT 228.315 0.17 229.085 0.43 ; + RECT 228.825 0.17 229.085 10.48 ; + RECT 228.315 0.17 228.575 10.99 ; + RECT 227.565 190.585 227.765 191.315 ; + RECT 228.065 190.585 228.265 191.315 ; + RECT 228.565 190.585 228.765 191.315 ; + RECT 229.06 190.585 229.26 191.315 ; + RECT 230.355 0.17 231.125 0.43 ; + RECT 230.355 0.17 230.615 11.5 ; + RECT 230.865 0.17 231.125 11.5 ; + RECT 229.88 190.585 230.08 191.315 ; + RECT 230.375 190.585 230.575 191.315 ; + RECT 231.375 0.17 232.145 0.94 ; + RECT 231.375 0.17 231.635 12.9 ; + RECT 231.885 0.17 232.145 12.9 ; + RECT 230.875 190.585 231.075 191.315 ; + RECT 231.375 190.585 231.575 191.315 ; + RECT 231.87 190.585 232.07 191.315 ; + RECT 232.395 0.52 232.655 5.815 ; + RECT 233.25 0.52 233.51 5.16 ; + RECT 233.25 4.9 234.03 5.16 ; + RECT 233.77 4.9 234.03 6.64 ; + RECT 232.69 190.585 232.89 191.315 ; + RECT 233.185 190.585 233.385 191.315 ; + RECT 233.685 190.585 233.885 191.315 ; + RECT 234.185 190.585 234.385 191.315 ; + RECT 234.68 190.585 234.88 191.315 ; + RECT 235.5 190.585 235.7 191.315 ; + RECT 236.495 45.465 236.695 191.315 ; + LAYER Metal2 SPACING 0.21 ; + RECT 113.59 0 113.83 191.34 ; + RECT 116.65 0 116.89 191.34 ; + RECT 118.18 0 118.42 191.34 ; + RECT 125.31 0 132.19 191.34 ; + RECT 133.48 0 134.23 191.34 ; + RECT 0 0 3.03 191.34 ; + RECT 4.655 0.17 9.505 191.34 ; + RECT 11.65 0 14.27 191.34 ; + RECT 15.895 0.17 20.745 191.34 ; + RECT 22.89 0 25.51 191.34 ; + RECT 27.135 0.17 31.985 191.34 ; + RECT 34.13 0 36.75 191.34 ; + RECT 38.375 0.17 43.225 191.34 ; + RECT 45.37 0 47.99 191.34 ; + RECT 49.615 0.17 54.465 191.34 ; + RECT 56.61 0 59.23 191.34 ; + RECT 60.855 0.17 65.705 191.34 ; + RECT 67.85 0 70.47 191.34 ; + RECT 72.095 0.17 76.945 191.34 ; + RECT 79.09 0 81.71 191.34 ; + RECT 83.335 0.17 88.185 191.34 ; + RECT 90.33 0 102.11 191.34 ; + RECT 104.4 0.17 110.78 191.34 ; + RECT 112.05 0.3 112.31 191.34 ; + RECT 113.58 0.3 113.84 191.34 ; + RECT 116.64 0.3 116.9 191.34 ; + RECT 118.17 0.3 118.43 191.34 ; + RECT 119.71 0.17 120.98 191.34 ; + RECT 119.7 0.3 120.98 191.34 ; + RECT 125.31 0.3 132.2 191.34 ; + RECT 133.47 0.3 134.24 191.34 ; + RECT 135.01 0 146.47 191.34 ; + RECT 135 0.17 146.47 191.34 ; + RECT 148.615 0.17 153.465 191.34 ; + RECT 155.09 0 157.71 191.34 ; + RECT 159.855 0.17 164.705 191.34 ; + RECT 166.33 0 168.95 191.34 ; + RECT 171.095 0.17 175.945 191.34 ; + RECT 177.57 0 180.19 191.34 ; + RECT 182.335 0.17 187.185 191.34 ; + RECT 188.81 0 191.43 191.34 ; + RECT 193.575 0.17 198.425 191.34 ; + RECT 200.05 0 202.67 191.34 ; + RECT 204.815 0.17 209.665 191.34 ; + RECT 211.29 0 213.91 191.34 ; + RECT 216.055 0.17 220.905 191.34 ; + RECT 222.53 0 225.15 191.34 ; + RECT 227.295 0.17 232.145 191.34 ; + RECT 233.77 0 236.8 191.34 ; + RECT 0 0.52 236.8 191.34 ; + RECT 4.665 0 9.495 191.34 ; + RECT 15.905 0 20.735 191.34 ; + RECT 27.145 0 31.975 191.34 ; + RECT 38.385 0 43.215 191.34 ; + RECT 49.625 0 54.455 191.34 ; + RECT 60.865 0 65.695 191.34 ; + RECT 72.105 0 76.935 191.34 ; + RECT 83.345 0 88.175 191.34 ; + RECT 104.4 0 110.77 191.34 ; + RECT 119.71 0 120.97 191.34 ; + RECT 148.625 0 153.455 191.34 ; + RECT 159.865 0 164.695 191.34 ; + RECT 171.105 0 175.935 191.34 ; + RECT 182.345 0 187.175 191.34 ; + RECT 193.585 0 198.415 191.34 ; + RECT 204.825 0 209.655 191.34 ; + RECT 216.065 0 220.895 191.34 ; + RECT 227.305 0 232.135 191.34 ; + RECT 112.06 0 112.3 191.34 ; + LAYER Metal3 ; + RECT 0 0 236.8 191.34 ; + LAYER Metal4 SPACING 0.21 ; + RECT 0 39.085 9.62 45.205 ; + RECT 0 0 4 191.34 ; + RECT 7.33 0 9.62 191.34 ; + RECT 12.95 39.085 20.86 45.205 ; + RECT 12.95 0 15.24 191.34 ; + RECT 18.57 0 20.86 191.34 ; + RECT 24.19 39.085 32.1 45.205 ; + RECT 24.19 0 26.48 191.34 ; + RECT 29.81 0 32.1 191.34 ; + RECT 35.43 39.085 43.34 45.205 ; + RECT 35.43 0 37.72 191.34 ; + RECT 41.05 0 43.34 191.34 ; + RECT 46.67 39.085 54.58 45.205 ; + RECT 46.67 0 48.96 191.34 ; + RECT 52.29 0 54.58 191.34 ; + RECT 57.91 39.085 65.82 45.205 ; + RECT 57.91 0 60.2 191.34 ; + RECT 63.53 0 65.82 191.34 ; + RECT 69.15 39.085 77.06 45.205 ; + RECT 69.15 0 71.44 191.34 ; + RECT 74.77 0 77.06 191.34 ; + RECT 80.39 39.085 88.3 45.205 ; + RECT 80.39 0 82.68 191.34 ; + RECT 86.01 0 88.3 191.34 ; + RECT 91.63 0 98.71 191.34 ; + RECT 102.04 0 103.86 191.34 ; + RECT 107.19 0 109.01 191.34 ; + RECT 112.34 0 114.16 191.34 ; + RECT 117.49 0 119.31 191.34 ; + RECT 122.64 0 124.46 191.34 ; + RECT 148.5 39.085 156.41 45.205 ; + RECT 148.5 0 150.79 191.34 ; + RECT 154.12 0 156.41 191.34 ; + RECT 159.74 39.085 167.65 45.205 ; + RECT 159.74 0 162.03 191.34 ; + RECT 165.36 0 167.65 191.34 ; + RECT 170.98 39.085 178.89 45.205 ; + RECT 170.98 0 173.27 191.34 ; + RECT 176.6 0 178.89 191.34 ; + RECT 182.22 39.085 190.13 45.205 ; + RECT 182.22 0 184.51 191.34 ; + RECT 187.84 0 190.13 191.34 ; + RECT 193.46 39.085 201.37 45.205 ; + RECT 193.46 0 195.75 191.34 ; + RECT 199.08 0 201.37 191.34 ; + RECT 204.7 39.085 212.61 45.205 ; + RECT 204.7 0 206.99 191.34 ; + RECT 210.32 0 212.61 191.34 ; + RECT 215.94 39.085 223.85 45.205 ; + RECT 215.94 0 218.23 191.34 ; + RECT 221.56 0 223.85 191.34 ; + RECT 227.18 39.085 236.8 45.205 ; + RECT 227.18 0 229.47 191.34 ; + RECT 232.8 0 236.8 191.34 ; + RECT 127.79 0 129.61 191.34 ; + RECT 132.94 0 134.76 191.34 ; + RECT 138.09 0 145.17 191.34 ; + END +END RM_IHPSG13_1P_512x16_c2_bm_bist + +END LIBRARY diff --git a/flow/platforms/ihp-sg13g2/lef/RM_IHPSG13_1P_512x32_c2_bm_bist.lef b/flow/platforms/ihp-sg13g2/lef/RM_IHPSG13_1P_512x32_c2_bm_bist.lef new file mode 100644 index 0000000000..afaba43396 --- /dev/null +++ b/flow/platforms/ihp-sg13g2/lef/RM_IHPSG13_1P_512x32_c2_bm_bist.lef @@ -0,0 +1,4282 @@ +# ------------------------------------------------------ +# +# Copyright 2023 IHP PDK Authors +# +# Licensed under the Apache License, Version 2.0 (the "License"); +# you may not use this file except in compliance with the License. +# You may obtain a copy of the License at +# +# https://www.apache.org/licenses/LICENSE-2.0 +# +# Unless required by applicable law or agreed to in writing, software +# distributed under the License is distributed on an "AS IS" BASIS, +# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +# See the License for the specific language governing permissions and +# limitations under the License. +# +# Generated on Wed Apr 2 16:02:47 2025 +# +# ------------------------------------------------------ +VERSION 5.7 ; +BUSBITCHARS "[]" ; +DIVIDERCHAR "/" ; + +MACRO RM_IHPSG13_1P_512x32_c2_bm_bist + CLASS BLOCK ; + ORIGIN 0 0 ; + FOREIGN RM_IHPSG13_1P_512x32_c2_bm_bist 0 0 ; + SIZE 416.64 BY 191.34 ; + SYMMETRY X Y R90 ; + PIN A_DIN[16] + DIRECTION INPUT ; + USE SIGNAL ; + ANTENNAPARTIALMETALAREA 1.794 LAYER Metal2 ; + ANTENNAMODEL OXIDE1 ; + ANTENNAGATEAREA 0.20085 LAYER Metal2 ; + ANTENNAMAXAREACAR 9.838188 LAYER Metal2 ; + PORT + LAYER Metal2 ; + RECT 244.49 0 244.75 0.26 ; + END + END A_DIN[16] + PIN A_DIN[15] + DIRECTION INPUT ; + USE SIGNAL ; + ANTENNAPARTIALMETALAREA 1.794 LAYER Metal2 ; + ANTENNAMODEL OXIDE1 ; + ANTENNAGATEAREA 0.20085 LAYER Metal2 ; + ANTENNAMAXAREACAR 9.838188 LAYER Metal2 ; + PORT + LAYER Metal2 ; + RECT 171.89 0 172.15 0.26 ; + END + END A_DIN[15] + PIN A_BIST_DIN[16] + DIRECTION INPUT ; + USE SIGNAL ; + ANTENNAPARTIALMETALAREA 1.6263 LAYER Metal2 ; + ANTENNAMODEL OXIDE1 ; + ANTENNAGATEAREA 0.20085 LAYER Metal2 ; + ANTENNAMAXAREACAR 9.365945 LAYER Metal2 ; + PORT + LAYER Metal2 ; + RECT 243.635 0 243.895 0.26 ; + END + END A_BIST_DIN[16] + PIN A_BIST_DIN[15] + DIRECTION INPUT ; + USE SIGNAL ; + ANTENNAPARTIALMETALAREA 1.6263 LAYER Metal2 ; + ANTENNAMODEL OXIDE1 ; + ANTENNAGATEAREA 0.20085 LAYER Metal2 ; + ANTENNAMAXAREACAR 9.365945 LAYER Metal2 ; + PORT + LAYER Metal2 ; + RECT 172.745 0 173.005 0.26 ; + END + END A_BIST_DIN[15] + PIN A_BM[16] + DIRECTION INPUT ; + USE SIGNAL ; + ANTENNAPARTIALMETALAREA 0.7215 LAYER Metal2 ; + ANTENNAMODEL OXIDE1 ; + ANTENNAGATEAREA 0.20085 LAYER Metal2 ; + ANTENNAMAXAREACAR 4.498382 LAYER Metal2 ; + PORT + LAYER Metal2 ; + RECT 236.65 0 236.91 0.26 ; + END + END A_BM[16] + PIN A_BM[15] + DIRECTION INPUT ; + USE SIGNAL ; + ANTENNAPARTIALMETALAREA 0.7215 LAYER Metal2 ; + ANTENNAMODEL OXIDE1 ; + ANTENNAGATEAREA 0.20085 LAYER Metal2 ; + ANTENNAMAXAREACAR 4.498382 LAYER Metal2 ; + PORT + LAYER Metal2 ; + RECT 179.73 0 179.99 0.26 ; + END + END A_BM[15] + PIN A_BIST_BM[16] + DIRECTION INPUT ; + USE SIGNAL ; + ANTENNAPARTIALMETALAREA 0.7605 LAYER Metal2 ; + ANTENNAMODEL OXIDE1 ; + ANTENNAGATEAREA 0.20085 LAYER Metal2 ; + ANTENNAMAXAREACAR 5.055265 LAYER Metal2 ; + PORT + LAYER Metal2 ; + RECT 238.025 0 238.285 0.26 ; + END + END A_BIST_BM[16] + PIN A_BIST_BM[15] + DIRECTION INPUT ; + USE SIGNAL ; + ANTENNAPARTIALMETALAREA 0.7605 LAYER Metal2 ; + ANTENNAMODEL OXIDE1 ; + ANTENNAGATEAREA 0.20085 LAYER Metal2 ; + ANTENNAMAXAREACAR 5.055265 LAYER Metal2 ; + PORT + LAYER Metal2 ; + RECT 178.355 0 178.615 0.26 ; + END + END A_BIST_BM[15] + PIN A_DOUT[16] + DIRECTION OUTPUT ; + USE SIGNAL ; + ANTENNAPARTIALMETALAREA 3.7095 LAYER Metal2 ; + ANTENNADIFFAREA 0.988 LAYER Metal2 ; + PORT + LAYER Metal2 ; + RECT 237.16 0 237.42 0.26 ; + END + END A_DOUT[16] + PIN A_DOUT[15] + DIRECTION OUTPUT ; + USE SIGNAL ; + ANTENNAPARTIALMETALAREA 3.7095 LAYER Metal2 ; + ANTENNADIFFAREA 0.988 LAYER Metal2 ; + PORT + LAYER Metal2 ; + RECT 179.22 0 179.48 0.26 ; + END + END A_DOUT[15] + PIN VSS! + DIRECTION INOUT ; + USE GROUND ; + NETEXPR "vss VSS!" ; + PORT + LAYER Metal4 ; + RECT 403.95 0 406.76 191.34 ; + END + PORT + LAYER Metal4 ; + RECT 392.71 0 395.52 191.34 ; + END + PORT + LAYER Metal4 ; + RECT 381.47 0 384.28 191.34 ; + END + PORT + LAYER Metal4 ; + RECT 370.23 0 373.04 191.34 ; + END + PORT + LAYER Metal4 ; + RECT 358.99 0 361.8 191.34 ; + END + PORT + LAYER Metal4 ; + RECT 347.75 0 350.56 191.34 ; + END + PORT + LAYER Metal4 ; + RECT 336.51 0 339.32 191.34 ; + END + PORT + LAYER Metal4 ; + RECT 325.27 0 328.08 191.34 ; + END + PORT + LAYER Metal4 ; + RECT 314.03 0 316.84 191.34 ; + END + PORT + LAYER Metal4 ; + RECT 302.79 0 305.6 191.34 ; + END + PORT + LAYER Metal4 ; + RECT 291.55 0 294.36 191.34 ; + END + PORT + LAYER Metal4 ; + RECT 280.31 0 283.12 191.34 ; + END + PORT + LAYER Metal4 ; + RECT 269.07 0 271.88 191.34 ; + END + PORT + LAYER Metal4 ; + RECT 257.83 0 260.64 191.34 ; + END + PORT + LAYER Metal4 ; + RECT 246.59 0 249.4 191.34 ; + END + PORT + LAYER Metal4 ; + RECT 235.35 0 238.16 191.34 ; + END + PORT + LAYER Metal4 ; + RECT 224.94 0 227.75 191.34 ; + END + PORT + LAYER Metal4 ; + RECT 214.64 0 217.45 191.34 ; + END + PORT + LAYER Metal4 ; + RECT 199.19 0 202 191.34 ; + END + PORT + LAYER Metal4 ; + RECT 188.89 0 191.7 191.34 ; + END + PORT + LAYER Metal4 ; + RECT 178.48 0 181.29 191.34 ; + END + PORT + LAYER Metal4 ; + RECT 167.24 0 170.05 191.34 ; + END + PORT + LAYER Metal4 ; + RECT 156 0 158.81 191.34 ; + END + PORT + LAYER Metal4 ; + RECT 144.76 0 147.57 191.34 ; + END + PORT + LAYER Metal4 ; + RECT 133.52 0 136.33 191.34 ; + END + PORT + LAYER Metal4 ; + RECT 122.28 0 125.09 191.34 ; + END + PORT + LAYER Metal4 ; + RECT 111.04 0 113.85 191.34 ; + END + PORT + LAYER Metal4 ; + RECT 99.8 0 102.61 191.34 ; + END + PORT + LAYER Metal4 ; + RECT 88.56 0 91.37 191.34 ; + END + PORT + LAYER Metal4 ; + RECT 77.32 0 80.13 191.34 ; + END + PORT + LAYER Metal4 ; + RECT 66.08 0 68.89 191.34 ; + END + PORT + LAYER Metal4 ; + RECT 54.84 0 57.65 191.34 ; + END + PORT + LAYER Metal4 ; + RECT 43.6 0 46.41 191.34 ; + END + PORT + LAYER Metal4 ; + RECT 32.36 0 35.17 191.34 ; + END + PORT + LAYER Metal4 ; + RECT 21.12 0 23.93 191.34 ; + END + PORT + LAYER Metal4 ; + RECT 9.88 0 12.69 191.34 ; + END + END VSS! + PIN VDD! + DIRECTION INOUT ; + USE POWER ; + NETEXPR "vdd VDD!" ; + PORT + LAYER Metal4 ; + RECT 409.57 0 412.38 38.825 ; + END + PORT + LAYER Metal4 ; + RECT 398.33 0 401.14 38.825 ; + END + PORT + LAYER Metal4 ; + RECT 387.09 0 389.9 38.825 ; + END + PORT + LAYER Metal4 ; + RECT 375.85 0 378.66 38.825 ; + END + PORT + LAYER Metal4 ; + RECT 364.61 0 367.42 38.825 ; + END + PORT + LAYER Metal4 ; + RECT 353.37 0 356.18 38.825 ; + END + PORT + LAYER Metal4 ; + RECT 342.13 0 344.94 38.825 ; + END + PORT + LAYER Metal4 ; + RECT 330.89 0 333.7 38.825 ; + END + PORT + LAYER Metal4 ; + RECT 319.65 0 322.46 38.825 ; + END + PORT + LAYER Metal4 ; + RECT 308.41 0 311.22 38.825 ; + END + PORT + LAYER Metal4 ; + RECT 297.17 0 299.98 38.825 ; + END + PORT + LAYER Metal4 ; + RECT 285.93 0 288.74 38.825 ; + END + PORT + LAYER Metal4 ; + RECT 274.69 0 277.5 38.825 ; + END + PORT + LAYER Metal4 ; + RECT 263.45 0 266.26 38.825 ; + END + PORT + LAYER Metal4 ; + RECT 252.21 0 255.02 38.825 ; + END + PORT + LAYER Metal4 ; + RECT 240.97 0 243.78 38.825 ; + END + PORT + LAYER Metal4 ; + RECT 219.79 0 222.6 191.34 ; + END + PORT + LAYER Metal4 ; + RECT 209.49 0 212.3 191.34 ; + END + PORT + LAYER Metal4 ; + RECT 204.34 0 207.15 191.34 ; + END + PORT + LAYER Metal4 ; + RECT 194.04 0 196.85 191.34 ; + END + PORT + LAYER Metal4 ; + RECT 172.86 0 175.67 38.825 ; + END + PORT + LAYER Metal4 ; + RECT 161.62 0 164.43 38.825 ; + END + PORT + LAYER Metal4 ; + RECT 150.38 0 153.19 38.825 ; + END + PORT + LAYER Metal4 ; + RECT 139.14 0 141.95 38.825 ; + END + PORT + LAYER Metal4 ; + RECT 127.9 0 130.71 38.825 ; + END + PORT + LAYER Metal4 ; + RECT 116.66 0 119.47 38.825 ; + END + PORT + LAYER Metal4 ; + RECT 105.42 0 108.23 38.825 ; + END + PORT + LAYER Metal4 ; + RECT 94.18 0 96.99 38.825 ; + END + PORT + LAYER Metal4 ; + RECT 82.94 0 85.75 38.825 ; + END + PORT + LAYER Metal4 ; + RECT 71.7 0 74.51 38.825 ; + END + PORT + LAYER Metal4 ; + RECT 60.46 0 63.27 38.825 ; + END + PORT + LAYER Metal4 ; + RECT 49.22 0 52.03 38.825 ; + END + PORT + LAYER Metal4 ; + RECT 37.98 0 40.79 38.825 ; + END + PORT + LAYER Metal4 ; + RECT 26.74 0 29.55 38.825 ; + END + PORT + LAYER Metal4 ; + RECT 15.5 0 18.31 38.825 ; + END + PORT + LAYER Metal4 ; + RECT 4.26 0 7.07 38.825 ; + END + END VDD! + PIN VDDARRAY! + DIRECTION INOUT ; + USE POWER ; + NETEXPR "vddarray VDDARRAY!" ; + PORT + LAYER Metal4 ; + RECT 409.57 45.465 412.38 191.34 ; + END + PORT + LAYER Metal4 ; + RECT 398.33 45.465 401.14 191.34 ; + END + PORT + LAYER Metal4 ; + RECT 387.09 45.465 389.9 191.34 ; + END + PORT + LAYER Metal4 ; + RECT 375.85 45.465 378.66 191.34 ; + END + PORT + LAYER Metal4 ; + RECT 364.61 45.465 367.42 191.34 ; + END + PORT + LAYER Metal4 ; + RECT 353.37 45.465 356.18 191.34 ; + END + PORT + LAYER Metal4 ; + RECT 342.13 45.465 344.94 191.34 ; + END + PORT + LAYER Metal4 ; + RECT 330.89 45.465 333.7 191.34 ; + END + PORT + LAYER Metal4 ; + RECT 319.65 45.465 322.46 191.34 ; + END + PORT + LAYER Metal4 ; + RECT 308.41 45.465 311.22 191.34 ; + END + PORT + LAYER Metal4 ; + RECT 297.17 45.465 299.98 191.34 ; + END + PORT + LAYER Metal4 ; + RECT 285.93 45.465 288.74 191.34 ; + END + PORT + LAYER Metal4 ; + RECT 274.69 45.465 277.5 191.34 ; + END + PORT + LAYER Metal4 ; + RECT 263.45 45.465 266.26 191.34 ; + END + PORT + LAYER Metal4 ; + RECT 252.21 45.465 255.02 191.34 ; + END + PORT + LAYER Metal4 ; + RECT 240.97 45.465 243.78 191.34 ; + END + PORT + LAYER Metal4 ; + RECT 172.86 45.465 175.67 191.34 ; + END + PORT + LAYER Metal4 ; + RECT 161.62 45.465 164.43 191.34 ; + END + PORT + LAYER Metal4 ; + RECT 150.38 45.465 153.19 191.34 ; + END + PORT + LAYER Metal4 ; + RECT 139.14 45.465 141.95 191.34 ; + END + PORT + LAYER Metal4 ; + RECT 127.9 45.465 130.71 191.34 ; + END + PORT + LAYER Metal4 ; + RECT 116.66 45.465 119.47 191.34 ; + END + PORT + LAYER Metal4 ; + RECT 105.42 45.465 108.23 191.34 ; + END + PORT + LAYER Metal4 ; + RECT 94.18 45.465 96.99 191.34 ; + END + PORT + LAYER Metal4 ; + RECT 82.94 45.465 85.75 191.34 ; + END + PORT + LAYER Metal4 ; + RECT 71.7 45.465 74.51 191.34 ; + END + PORT + LAYER Metal4 ; + RECT 60.46 45.465 63.27 191.34 ; + END + PORT + LAYER Metal4 ; + RECT 49.22 45.465 52.03 191.34 ; + END + PORT + LAYER Metal4 ; + RECT 37.98 45.465 40.79 191.34 ; + END + PORT + LAYER Metal4 ; + RECT 26.74 45.465 29.55 191.34 ; + END + PORT + LAYER Metal4 ; + RECT 15.5 45.465 18.31 191.34 ; + END + PORT + LAYER Metal4 ; + RECT 4.26 45.465 7.07 191.34 ; + END + END VDDARRAY! + PIN A_DIN[17] + DIRECTION INPUT ; + USE SIGNAL ; + ANTENNAPARTIALMETALAREA 1.794 LAYER Metal2 ; + ANTENNAMODEL OXIDE1 ; + ANTENNAGATEAREA 0.20085 LAYER Metal2 ; + ANTENNAMAXAREACAR 9.838188 LAYER Metal2 ; + PORT + LAYER Metal2 ; + RECT 255.73 0 255.99 0.26 ; + END + END A_DIN[17] + PIN A_DIN[14] + DIRECTION INPUT ; + USE SIGNAL ; + ANTENNAPARTIALMETALAREA 1.794 LAYER Metal2 ; + ANTENNAMODEL OXIDE1 ; + ANTENNAGATEAREA 0.20085 LAYER Metal2 ; + ANTENNAMAXAREACAR 9.838188 LAYER Metal2 ; + PORT + LAYER Metal2 ; + RECT 160.65 0 160.91 0.26 ; + END + END A_DIN[14] + PIN A_BIST_DIN[17] + DIRECTION INPUT ; + USE SIGNAL ; + ANTENNAPARTIALMETALAREA 1.6263 LAYER Metal2 ; + ANTENNAMODEL OXIDE1 ; + ANTENNAGATEAREA 0.20085 LAYER Metal2 ; + ANTENNAMAXAREACAR 9.365945 LAYER Metal2 ; + PORT + LAYER Metal2 ; + RECT 254.875 0 255.135 0.26 ; + END + END A_BIST_DIN[17] + PIN A_BIST_DIN[14] + DIRECTION INPUT ; + USE SIGNAL ; + ANTENNAPARTIALMETALAREA 1.6263 LAYER Metal2 ; + ANTENNAMODEL OXIDE1 ; + ANTENNAGATEAREA 0.20085 LAYER Metal2 ; + ANTENNAMAXAREACAR 9.365945 LAYER Metal2 ; + PORT + LAYER Metal2 ; + RECT 161.505 0 161.765 0.26 ; + END + END A_BIST_DIN[14] + PIN A_BM[17] + DIRECTION INPUT ; + USE SIGNAL ; + ANTENNAPARTIALMETALAREA 0.7215 LAYER Metal2 ; + ANTENNAMODEL OXIDE1 ; + ANTENNAGATEAREA 0.20085 LAYER Metal2 ; + ANTENNAMAXAREACAR 4.498382 LAYER Metal2 ; + PORT + LAYER Metal2 ; + RECT 247.89 0 248.15 0.26 ; + END + END A_BM[17] + PIN A_BM[14] + DIRECTION INPUT ; + USE SIGNAL ; + ANTENNAPARTIALMETALAREA 0.7215 LAYER Metal2 ; + ANTENNAMODEL OXIDE1 ; + ANTENNAGATEAREA 0.20085 LAYER Metal2 ; + ANTENNAMAXAREACAR 4.498382 LAYER Metal2 ; + PORT + LAYER Metal2 ; + RECT 168.49 0 168.75 0.26 ; + END + END A_BM[14] + PIN A_BIST_BM[17] + DIRECTION INPUT ; + USE SIGNAL ; + ANTENNAPARTIALMETALAREA 0.7605 LAYER Metal2 ; + ANTENNAMODEL OXIDE1 ; + ANTENNAGATEAREA 0.20085 LAYER Metal2 ; + ANTENNAMAXAREACAR 5.055265 LAYER Metal2 ; + PORT + LAYER Metal2 ; + RECT 249.265 0 249.525 0.26 ; + END + END A_BIST_BM[17] + PIN A_BIST_BM[14] + DIRECTION INPUT ; + USE SIGNAL ; + ANTENNAPARTIALMETALAREA 0.7605 LAYER Metal2 ; + ANTENNAMODEL OXIDE1 ; + ANTENNAGATEAREA 0.20085 LAYER Metal2 ; + ANTENNAMAXAREACAR 5.055265 LAYER Metal2 ; + PORT + LAYER Metal2 ; + RECT 167.115 0 167.375 0.26 ; + END + END A_BIST_BM[14] + PIN A_DOUT[17] + DIRECTION OUTPUT ; + USE SIGNAL ; + ANTENNAPARTIALMETALAREA 3.7095 LAYER Metal2 ; + ANTENNADIFFAREA 0.988 LAYER Metal2 ; + PORT + LAYER Metal2 ; + RECT 248.4 0 248.66 0.26 ; + END + END A_DOUT[17] + PIN A_DOUT[14] + DIRECTION OUTPUT ; + USE SIGNAL ; + ANTENNAPARTIALMETALAREA 3.7095 LAYER Metal2 ; + ANTENNADIFFAREA 0.988 LAYER Metal2 ; + PORT + LAYER Metal2 ; + RECT 167.98 0 168.24 0.26 ; + END + END A_DOUT[14] + PIN A_DIN[18] + DIRECTION INPUT ; + USE SIGNAL ; + ANTENNAPARTIALMETALAREA 1.794 LAYER Metal2 ; + ANTENNAMODEL OXIDE1 ; + ANTENNAGATEAREA 0.20085 LAYER Metal2 ; + ANTENNAMAXAREACAR 9.838188 LAYER Metal2 ; + PORT + LAYER Metal2 ; + RECT 266.97 0 267.23 0.26 ; + END + END A_DIN[18] + PIN A_DIN[13] + DIRECTION INPUT ; + USE SIGNAL ; + ANTENNAPARTIALMETALAREA 1.794 LAYER Metal2 ; + ANTENNAMODEL OXIDE1 ; + ANTENNAGATEAREA 0.20085 LAYER Metal2 ; + ANTENNAMAXAREACAR 9.838188 LAYER Metal2 ; + PORT + LAYER Metal2 ; + RECT 149.41 0 149.67 0.26 ; + END + END A_DIN[13] + PIN A_BIST_DIN[18] + DIRECTION INPUT ; + USE SIGNAL ; + ANTENNAPARTIALMETALAREA 1.6263 LAYER Metal2 ; + ANTENNAMODEL OXIDE1 ; + ANTENNAGATEAREA 0.20085 LAYER Metal2 ; + ANTENNAMAXAREACAR 9.365945 LAYER Metal2 ; + PORT + LAYER Metal2 ; + RECT 266.115 0 266.375 0.26 ; + END + END A_BIST_DIN[18] + PIN A_BIST_DIN[13] + DIRECTION INPUT ; + USE SIGNAL ; + ANTENNAPARTIALMETALAREA 1.6263 LAYER Metal2 ; + ANTENNAMODEL OXIDE1 ; + ANTENNAGATEAREA 0.20085 LAYER Metal2 ; + ANTENNAMAXAREACAR 9.365945 LAYER Metal2 ; + PORT + LAYER Metal2 ; + RECT 150.265 0 150.525 0.26 ; + END + END A_BIST_DIN[13] + PIN A_BM[18] + DIRECTION INPUT ; + USE SIGNAL ; + ANTENNAPARTIALMETALAREA 0.7215 LAYER Metal2 ; + ANTENNAMODEL OXIDE1 ; + ANTENNAGATEAREA 0.20085 LAYER Metal2 ; + ANTENNAMAXAREACAR 4.498382 LAYER Metal2 ; + PORT + LAYER Metal2 ; + RECT 259.13 0 259.39 0.26 ; + END + END A_BM[18] + PIN A_BM[13] + DIRECTION INPUT ; + USE SIGNAL ; + ANTENNAPARTIALMETALAREA 0.7215 LAYER Metal2 ; + ANTENNAMODEL OXIDE1 ; + ANTENNAGATEAREA 0.20085 LAYER Metal2 ; + ANTENNAMAXAREACAR 4.498382 LAYER Metal2 ; + PORT + LAYER Metal2 ; + RECT 157.25 0 157.51 0.26 ; + END + END A_BM[13] + PIN A_BIST_BM[18] + DIRECTION INPUT ; + USE SIGNAL ; + ANTENNAPARTIALMETALAREA 0.7605 LAYER Metal2 ; + ANTENNAMODEL OXIDE1 ; + ANTENNAGATEAREA 0.20085 LAYER Metal2 ; + ANTENNAMAXAREACAR 5.055265 LAYER Metal2 ; + PORT + LAYER Metal2 ; + RECT 260.505 0 260.765 0.26 ; + END + END A_BIST_BM[18] + PIN A_BIST_BM[13] + DIRECTION INPUT ; + USE SIGNAL ; + ANTENNAPARTIALMETALAREA 0.7605 LAYER Metal2 ; + ANTENNAMODEL OXIDE1 ; + ANTENNAGATEAREA 0.20085 LAYER Metal2 ; + ANTENNAMAXAREACAR 5.055265 LAYER Metal2 ; + PORT + LAYER Metal2 ; + RECT 155.875 0 156.135 0.26 ; + END + END A_BIST_BM[13] + PIN A_DOUT[18] + DIRECTION OUTPUT ; + USE SIGNAL ; + ANTENNAPARTIALMETALAREA 3.7095 LAYER Metal2 ; + ANTENNADIFFAREA 0.988 LAYER Metal2 ; + PORT + LAYER Metal2 ; + RECT 259.64 0 259.9 0.26 ; + END + END A_DOUT[18] + PIN A_DOUT[13] + DIRECTION OUTPUT ; + USE SIGNAL ; + ANTENNAPARTIALMETALAREA 3.7095 LAYER Metal2 ; + ANTENNADIFFAREA 0.988 LAYER Metal2 ; + PORT + LAYER Metal2 ; + RECT 156.74 0 157 0.26 ; + END + END A_DOUT[13] + PIN A_DIN[19] + DIRECTION INPUT ; + USE SIGNAL ; + ANTENNAPARTIALMETALAREA 1.794 LAYER Metal2 ; + ANTENNAMODEL OXIDE1 ; + ANTENNAGATEAREA 0.20085 LAYER Metal2 ; + ANTENNAMAXAREACAR 9.838188 LAYER Metal2 ; + PORT + LAYER Metal2 ; + RECT 278.21 0 278.47 0.26 ; + END + END A_DIN[19] + PIN A_DIN[12] + DIRECTION INPUT ; + USE SIGNAL ; + ANTENNAPARTIALMETALAREA 1.794 LAYER Metal2 ; + ANTENNAMODEL OXIDE1 ; + ANTENNAGATEAREA 0.20085 LAYER Metal2 ; + ANTENNAMAXAREACAR 9.838188 LAYER Metal2 ; + PORT + LAYER Metal2 ; + RECT 138.17 0 138.43 0.26 ; + END + END A_DIN[12] + PIN A_BIST_DIN[19] + DIRECTION INPUT ; + USE SIGNAL ; + ANTENNAPARTIALMETALAREA 1.6263 LAYER Metal2 ; + ANTENNAMODEL OXIDE1 ; + ANTENNAGATEAREA 0.20085 LAYER Metal2 ; + ANTENNAMAXAREACAR 9.365945 LAYER Metal2 ; + PORT + LAYER Metal2 ; + RECT 277.355 0 277.615 0.26 ; + END + END A_BIST_DIN[19] + PIN A_BIST_DIN[12] + DIRECTION INPUT ; + USE SIGNAL ; + ANTENNAPARTIALMETALAREA 1.6263 LAYER Metal2 ; + ANTENNAMODEL OXIDE1 ; + ANTENNAGATEAREA 0.20085 LAYER Metal2 ; + ANTENNAMAXAREACAR 9.365945 LAYER Metal2 ; + PORT + LAYER Metal2 ; + RECT 139.025 0 139.285 0.26 ; + END + END A_BIST_DIN[12] + PIN A_BM[19] + DIRECTION INPUT ; + USE SIGNAL ; + ANTENNAPARTIALMETALAREA 0.7215 LAYER Metal2 ; + ANTENNAMODEL OXIDE1 ; + ANTENNAGATEAREA 0.20085 LAYER Metal2 ; + ANTENNAMAXAREACAR 4.498382 LAYER Metal2 ; + PORT + LAYER Metal2 ; + RECT 270.37 0 270.63 0.26 ; + END + END A_BM[19] + PIN A_BM[12] + DIRECTION INPUT ; + USE SIGNAL ; + ANTENNAPARTIALMETALAREA 0.7215 LAYER Metal2 ; + ANTENNAMODEL OXIDE1 ; + ANTENNAGATEAREA 0.20085 LAYER Metal2 ; + ANTENNAMAXAREACAR 4.498382 LAYER Metal2 ; + PORT + LAYER Metal2 ; + RECT 146.01 0 146.27 0.26 ; + END + END A_BM[12] + PIN A_BIST_BM[19] + DIRECTION INPUT ; + USE SIGNAL ; + ANTENNAPARTIALMETALAREA 0.7605 LAYER Metal2 ; + ANTENNAMODEL OXIDE1 ; + ANTENNAGATEAREA 0.20085 LAYER Metal2 ; + ANTENNAMAXAREACAR 5.055265 LAYER Metal2 ; + PORT + LAYER Metal2 ; + RECT 271.745 0 272.005 0.26 ; + END + END A_BIST_BM[19] + PIN A_BIST_BM[12] + DIRECTION INPUT ; + USE SIGNAL ; + ANTENNAPARTIALMETALAREA 0.7605 LAYER Metal2 ; + ANTENNAMODEL OXIDE1 ; + ANTENNAGATEAREA 0.20085 LAYER Metal2 ; + ANTENNAMAXAREACAR 5.055265 LAYER Metal2 ; + PORT + LAYER Metal2 ; + RECT 144.635 0 144.895 0.26 ; + END + END A_BIST_BM[12] + PIN A_DOUT[19] + DIRECTION OUTPUT ; + USE SIGNAL ; + ANTENNAPARTIALMETALAREA 3.7095 LAYER Metal2 ; + ANTENNADIFFAREA 0.988 LAYER Metal2 ; + PORT + LAYER Metal2 ; + RECT 270.88 0 271.14 0.26 ; + END + END A_DOUT[19] + PIN A_DOUT[12] + DIRECTION OUTPUT ; + USE SIGNAL ; + ANTENNAPARTIALMETALAREA 3.7095 LAYER Metal2 ; + ANTENNADIFFAREA 0.988 LAYER Metal2 ; + PORT + LAYER Metal2 ; + RECT 145.5 0 145.76 0.26 ; + END + END A_DOUT[12] + PIN A_DIN[20] + DIRECTION INPUT ; + USE SIGNAL ; + ANTENNAPARTIALMETALAREA 1.794 LAYER Metal2 ; + ANTENNAMODEL OXIDE1 ; + ANTENNAGATEAREA 0.20085 LAYER Metal2 ; + ANTENNAMAXAREACAR 9.838188 LAYER Metal2 ; + PORT + LAYER Metal2 ; + RECT 289.45 0 289.71 0.26 ; + END + END A_DIN[20] + PIN A_DIN[11] + DIRECTION INPUT ; + USE SIGNAL ; + ANTENNAPARTIALMETALAREA 1.794 LAYER Metal2 ; + ANTENNAMODEL OXIDE1 ; + ANTENNAGATEAREA 0.20085 LAYER Metal2 ; + ANTENNAMAXAREACAR 9.838188 LAYER Metal2 ; + PORT + LAYER Metal2 ; + RECT 126.93 0 127.19 0.26 ; + END + END A_DIN[11] + PIN A_BIST_DIN[20] + DIRECTION INPUT ; + USE SIGNAL ; + ANTENNAPARTIALMETALAREA 1.6263 LAYER Metal2 ; + ANTENNAMODEL OXIDE1 ; + ANTENNAGATEAREA 0.20085 LAYER Metal2 ; + ANTENNAMAXAREACAR 9.365945 LAYER Metal2 ; + PORT + LAYER Metal2 ; + RECT 288.595 0 288.855 0.26 ; + END + END A_BIST_DIN[20] + PIN A_BIST_DIN[11] + DIRECTION INPUT ; + USE SIGNAL ; + ANTENNAPARTIALMETALAREA 1.6263 LAYER Metal2 ; + ANTENNAMODEL OXIDE1 ; + ANTENNAGATEAREA 0.20085 LAYER Metal2 ; + ANTENNAMAXAREACAR 9.365945 LAYER Metal2 ; + PORT + LAYER Metal2 ; + RECT 127.785 0 128.045 0.26 ; + END + END A_BIST_DIN[11] + PIN A_BM[20] + DIRECTION INPUT ; + USE SIGNAL ; + ANTENNAPARTIALMETALAREA 0.7215 LAYER Metal2 ; + ANTENNAMODEL OXIDE1 ; + ANTENNAGATEAREA 0.20085 LAYER Metal2 ; + ANTENNAMAXAREACAR 4.498382 LAYER Metal2 ; + PORT + LAYER Metal2 ; + RECT 281.61 0 281.87 0.26 ; + END + END A_BM[20] + PIN A_BM[11] + DIRECTION INPUT ; + USE SIGNAL ; + ANTENNAPARTIALMETALAREA 0.7215 LAYER Metal2 ; + ANTENNAMODEL OXIDE1 ; + ANTENNAGATEAREA 0.20085 LAYER Metal2 ; + ANTENNAMAXAREACAR 4.498382 LAYER Metal2 ; + PORT + LAYER Metal2 ; + RECT 134.77 0 135.03 0.26 ; + END + END A_BM[11] + PIN A_BIST_BM[20] + DIRECTION INPUT ; + USE SIGNAL ; + ANTENNAPARTIALMETALAREA 0.7605 LAYER Metal2 ; + ANTENNAMODEL OXIDE1 ; + ANTENNAGATEAREA 0.20085 LAYER Metal2 ; + ANTENNAMAXAREACAR 5.055265 LAYER Metal2 ; + PORT + LAYER Metal2 ; + RECT 282.985 0 283.245 0.26 ; + END + END A_BIST_BM[20] + PIN A_BIST_BM[11] + DIRECTION INPUT ; + USE SIGNAL ; + ANTENNAPARTIALMETALAREA 0.7605 LAYER Metal2 ; + ANTENNAMODEL OXIDE1 ; + ANTENNAGATEAREA 0.20085 LAYER Metal2 ; + ANTENNAMAXAREACAR 5.055265 LAYER Metal2 ; + PORT + LAYER Metal2 ; + RECT 133.395 0 133.655 0.26 ; + END + END A_BIST_BM[11] + PIN A_DOUT[20] + DIRECTION OUTPUT ; + USE SIGNAL ; + ANTENNAPARTIALMETALAREA 3.7095 LAYER Metal2 ; + ANTENNADIFFAREA 0.988 LAYER Metal2 ; + PORT + LAYER Metal2 ; + RECT 282.12 0 282.38 0.26 ; + END + END A_DOUT[20] + PIN A_DOUT[11] + DIRECTION OUTPUT ; + USE SIGNAL ; + ANTENNAPARTIALMETALAREA 3.7095 LAYER Metal2 ; + ANTENNADIFFAREA 0.988 LAYER Metal2 ; + PORT + LAYER Metal2 ; + RECT 134.26 0 134.52 0.26 ; + END + END A_DOUT[11] + PIN A_DIN[21] + DIRECTION INPUT ; + USE SIGNAL ; + ANTENNAPARTIALMETALAREA 1.794 LAYER Metal2 ; + ANTENNAMODEL OXIDE1 ; + ANTENNAGATEAREA 0.20085 LAYER Metal2 ; + ANTENNAMAXAREACAR 9.838188 LAYER Metal2 ; + PORT + LAYER Metal2 ; + RECT 300.69 0 300.95 0.26 ; + END + END A_DIN[21] + PIN A_DIN[10] + DIRECTION INPUT ; + USE SIGNAL ; + ANTENNAPARTIALMETALAREA 1.794 LAYER Metal2 ; + ANTENNAMODEL OXIDE1 ; + ANTENNAGATEAREA 0.20085 LAYER Metal2 ; + ANTENNAMAXAREACAR 9.838188 LAYER Metal2 ; + PORT + LAYER Metal2 ; + RECT 115.69 0 115.95 0.26 ; + END + END A_DIN[10] + PIN A_BIST_DIN[21] + DIRECTION INPUT ; + USE SIGNAL ; + ANTENNAPARTIALMETALAREA 1.6263 LAYER Metal2 ; + ANTENNAMODEL OXIDE1 ; + ANTENNAGATEAREA 0.20085 LAYER Metal2 ; + ANTENNAMAXAREACAR 9.365945 LAYER Metal2 ; + PORT + LAYER Metal2 ; + RECT 299.835 0 300.095 0.26 ; + END + END A_BIST_DIN[21] + PIN A_BIST_DIN[10] + DIRECTION INPUT ; + USE SIGNAL ; + ANTENNAPARTIALMETALAREA 1.6263 LAYER Metal2 ; + ANTENNAMODEL OXIDE1 ; + ANTENNAGATEAREA 0.20085 LAYER Metal2 ; + ANTENNAMAXAREACAR 9.365945 LAYER Metal2 ; + PORT + LAYER Metal2 ; + RECT 116.545 0 116.805 0.26 ; + END + END A_BIST_DIN[10] + PIN A_BM[21] + DIRECTION INPUT ; + USE SIGNAL ; + ANTENNAPARTIALMETALAREA 0.7215 LAYER Metal2 ; + ANTENNAMODEL OXIDE1 ; + ANTENNAGATEAREA 0.20085 LAYER Metal2 ; + ANTENNAMAXAREACAR 4.498382 LAYER Metal2 ; + PORT + LAYER Metal2 ; + RECT 292.85 0 293.11 0.26 ; + END + END A_BM[21] + PIN A_BM[10] + DIRECTION INPUT ; + USE SIGNAL ; + ANTENNAPARTIALMETALAREA 0.7215 LAYER Metal2 ; + ANTENNAMODEL OXIDE1 ; + ANTENNAGATEAREA 0.20085 LAYER Metal2 ; + ANTENNAMAXAREACAR 4.498382 LAYER Metal2 ; + PORT + LAYER Metal2 ; + RECT 123.53 0 123.79 0.26 ; + END + END A_BM[10] + PIN A_BIST_BM[21] + DIRECTION INPUT ; + USE SIGNAL ; + ANTENNAPARTIALMETALAREA 0.7605 LAYER Metal2 ; + ANTENNAMODEL OXIDE1 ; + ANTENNAGATEAREA 0.20085 LAYER Metal2 ; + ANTENNAMAXAREACAR 5.055265 LAYER Metal2 ; + PORT + LAYER Metal2 ; + RECT 294.225 0 294.485 0.26 ; + END + END A_BIST_BM[21] + PIN A_BIST_BM[10] + DIRECTION INPUT ; + USE SIGNAL ; + ANTENNAPARTIALMETALAREA 0.7605 LAYER Metal2 ; + ANTENNAMODEL OXIDE1 ; + ANTENNAGATEAREA 0.20085 LAYER Metal2 ; + ANTENNAMAXAREACAR 5.055265 LAYER Metal2 ; + PORT + LAYER Metal2 ; + RECT 122.155 0 122.415 0.26 ; + END + END A_BIST_BM[10] + PIN A_DOUT[21] + DIRECTION OUTPUT ; + USE SIGNAL ; + ANTENNAPARTIALMETALAREA 3.7095 LAYER Metal2 ; + ANTENNADIFFAREA 0.988 LAYER Metal2 ; + PORT + LAYER Metal2 ; + RECT 293.36 0 293.62 0.26 ; + END + END A_DOUT[21] + PIN A_DOUT[10] + DIRECTION OUTPUT ; + USE SIGNAL ; + ANTENNAPARTIALMETALAREA 3.7095 LAYER Metal2 ; + ANTENNADIFFAREA 0.988 LAYER Metal2 ; + PORT + LAYER Metal2 ; + RECT 123.02 0 123.28 0.26 ; + END + END A_DOUT[10] + PIN A_DIN[22] + DIRECTION INPUT ; + USE SIGNAL ; + ANTENNAPARTIALMETALAREA 1.794 LAYER Metal2 ; + ANTENNAMODEL OXIDE1 ; + ANTENNAGATEAREA 0.20085 LAYER Metal2 ; + ANTENNAMAXAREACAR 9.838188 LAYER Metal2 ; + PORT + LAYER Metal2 ; + RECT 311.93 0 312.19 0.26 ; + END + END A_DIN[22] + PIN A_DIN[9] + DIRECTION INPUT ; + USE SIGNAL ; + ANTENNAPARTIALMETALAREA 1.794 LAYER Metal2 ; + ANTENNAMODEL OXIDE1 ; + ANTENNAGATEAREA 0.20085 LAYER Metal2 ; + ANTENNAMAXAREACAR 9.838188 LAYER Metal2 ; + PORT + LAYER Metal2 ; + RECT 104.45 0 104.71 0.26 ; + END + END A_DIN[9] + PIN A_BIST_DIN[22] + DIRECTION INPUT ; + USE SIGNAL ; + ANTENNAPARTIALMETALAREA 1.6263 LAYER Metal2 ; + ANTENNAMODEL OXIDE1 ; + ANTENNAGATEAREA 0.20085 LAYER Metal2 ; + ANTENNAMAXAREACAR 9.365945 LAYER Metal2 ; + PORT + LAYER Metal2 ; + RECT 311.075 0 311.335 0.26 ; + END + END A_BIST_DIN[22] + PIN A_BIST_DIN[9] + DIRECTION INPUT ; + USE SIGNAL ; + ANTENNAPARTIALMETALAREA 1.6263 LAYER Metal2 ; + ANTENNAMODEL OXIDE1 ; + ANTENNAGATEAREA 0.20085 LAYER Metal2 ; + ANTENNAMAXAREACAR 9.365945 LAYER Metal2 ; + PORT + LAYER Metal2 ; + RECT 105.305 0 105.565 0.26 ; + END + END A_BIST_DIN[9] + PIN A_BM[22] + DIRECTION INPUT ; + USE SIGNAL ; + ANTENNAPARTIALMETALAREA 0.7215 LAYER Metal2 ; + ANTENNAMODEL OXIDE1 ; + ANTENNAGATEAREA 0.20085 LAYER Metal2 ; + ANTENNAMAXAREACAR 4.498382 LAYER Metal2 ; + PORT + LAYER Metal2 ; + RECT 304.09 0 304.35 0.26 ; + END + END A_BM[22] + PIN A_BM[9] + DIRECTION INPUT ; + USE SIGNAL ; + ANTENNAPARTIALMETALAREA 0.7215 LAYER Metal2 ; + ANTENNAMODEL OXIDE1 ; + ANTENNAGATEAREA 0.20085 LAYER Metal2 ; + ANTENNAMAXAREACAR 4.498382 LAYER Metal2 ; + PORT + LAYER Metal2 ; + RECT 112.29 0 112.55 0.26 ; + END + END A_BM[9] + PIN A_BIST_BM[22] + DIRECTION INPUT ; + USE SIGNAL ; + ANTENNAPARTIALMETALAREA 0.7605 LAYER Metal2 ; + ANTENNAMODEL OXIDE1 ; + ANTENNAGATEAREA 0.20085 LAYER Metal2 ; + ANTENNAMAXAREACAR 5.055265 LAYER Metal2 ; + PORT + LAYER Metal2 ; + RECT 305.465 0 305.725 0.26 ; + END + END A_BIST_BM[22] + PIN A_BIST_BM[9] + DIRECTION INPUT ; + USE SIGNAL ; + ANTENNAPARTIALMETALAREA 0.7605 LAYER Metal2 ; + ANTENNAMODEL OXIDE1 ; + ANTENNAGATEAREA 0.20085 LAYER Metal2 ; + ANTENNAMAXAREACAR 5.055265 LAYER Metal2 ; + PORT + LAYER Metal2 ; + RECT 110.915 0 111.175 0.26 ; + END + END A_BIST_BM[9] + PIN A_DOUT[22] + DIRECTION OUTPUT ; + USE SIGNAL ; + ANTENNAPARTIALMETALAREA 3.7095 LAYER Metal2 ; + ANTENNADIFFAREA 0.988 LAYER Metal2 ; + PORT + LAYER Metal2 ; + RECT 304.6 0 304.86 0.26 ; + END + END A_DOUT[22] + PIN A_DOUT[9] + DIRECTION OUTPUT ; + USE SIGNAL ; + ANTENNAPARTIALMETALAREA 3.7095 LAYER Metal2 ; + ANTENNADIFFAREA 0.988 LAYER Metal2 ; + PORT + LAYER Metal2 ; + RECT 111.78 0 112.04 0.26 ; + END + END A_DOUT[9] + PIN A_DIN[23] + DIRECTION INPUT ; + USE SIGNAL ; + ANTENNAPARTIALMETALAREA 1.794 LAYER Metal2 ; + ANTENNAMODEL OXIDE1 ; + ANTENNAGATEAREA 0.20085 LAYER Metal2 ; + ANTENNAMAXAREACAR 9.838188 LAYER Metal2 ; + PORT + LAYER Metal2 ; + RECT 323.17 0 323.43 0.26 ; + END + END A_DIN[23] + PIN A_DIN[8] + DIRECTION INPUT ; + USE SIGNAL ; + ANTENNAPARTIALMETALAREA 1.794 LAYER Metal2 ; + ANTENNAMODEL OXIDE1 ; + ANTENNAGATEAREA 0.20085 LAYER Metal2 ; + ANTENNAMAXAREACAR 9.838188 LAYER Metal2 ; + PORT + LAYER Metal2 ; + RECT 93.21 0 93.47 0.26 ; + END + END A_DIN[8] + PIN A_BIST_DIN[23] + DIRECTION INPUT ; + USE SIGNAL ; + ANTENNAPARTIALMETALAREA 1.6263 LAYER Metal2 ; + ANTENNAMODEL OXIDE1 ; + ANTENNAGATEAREA 0.20085 LAYER Metal2 ; + ANTENNAMAXAREACAR 9.365945 LAYER Metal2 ; + PORT + LAYER Metal2 ; + RECT 322.315 0 322.575 0.26 ; + END + END A_BIST_DIN[23] + PIN A_BIST_DIN[8] + DIRECTION INPUT ; + USE SIGNAL ; + ANTENNAPARTIALMETALAREA 1.6263 LAYER Metal2 ; + ANTENNAMODEL OXIDE1 ; + ANTENNAGATEAREA 0.20085 LAYER Metal2 ; + ANTENNAMAXAREACAR 9.365945 LAYER Metal2 ; + PORT + LAYER Metal2 ; + RECT 94.065 0 94.325 0.26 ; + END + END A_BIST_DIN[8] + PIN A_BM[23] + DIRECTION INPUT ; + USE SIGNAL ; + ANTENNAPARTIALMETALAREA 0.7215 LAYER Metal2 ; + ANTENNAMODEL OXIDE1 ; + ANTENNAGATEAREA 0.20085 LAYER Metal2 ; + ANTENNAMAXAREACAR 4.498382 LAYER Metal2 ; + PORT + LAYER Metal2 ; + RECT 315.33 0 315.59 0.26 ; + END + END A_BM[23] + PIN A_BM[8] + DIRECTION INPUT ; + USE SIGNAL ; + ANTENNAPARTIALMETALAREA 0.7215 LAYER Metal2 ; + ANTENNAMODEL OXIDE1 ; + ANTENNAGATEAREA 0.20085 LAYER Metal2 ; + ANTENNAMAXAREACAR 4.498382 LAYER Metal2 ; + PORT + LAYER Metal2 ; + RECT 101.05 0 101.31 0.26 ; + END + END A_BM[8] + PIN A_BIST_BM[23] + DIRECTION INPUT ; + USE SIGNAL ; + ANTENNAPARTIALMETALAREA 0.7605 LAYER Metal2 ; + ANTENNAMODEL OXIDE1 ; + ANTENNAGATEAREA 0.20085 LAYER Metal2 ; + ANTENNAMAXAREACAR 5.055265 LAYER Metal2 ; + PORT + LAYER Metal2 ; + RECT 316.705 0 316.965 0.26 ; + END + END A_BIST_BM[23] + PIN A_BIST_BM[8] + DIRECTION INPUT ; + USE SIGNAL ; + ANTENNAPARTIALMETALAREA 0.7605 LAYER Metal2 ; + ANTENNAMODEL OXIDE1 ; + ANTENNAGATEAREA 0.20085 LAYER Metal2 ; + ANTENNAMAXAREACAR 5.055265 LAYER Metal2 ; + PORT + LAYER Metal2 ; + RECT 99.675 0 99.935 0.26 ; + END + END A_BIST_BM[8] + PIN A_DOUT[23] + DIRECTION OUTPUT ; + USE SIGNAL ; + ANTENNAPARTIALMETALAREA 3.7095 LAYER Metal2 ; + ANTENNADIFFAREA 0.988 LAYER Metal2 ; + PORT + LAYER Metal2 ; + RECT 315.84 0 316.1 0.26 ; + END + END A_DOUT[23] + PIN A_DOUT[8] + DIRECTION OUTPUT ; + USE SIGNAL ; + ANTENNAPARTIALMETALAREA 3.7095 LAYER Metal2 ; + ANTENNADIFFAREA 0.988 LAYER Metal2 ; + PORT + LAYER Metal2 ; + RECT 100.54 0 100.8 0.26 ; + END + END A_DOUT[8] + PIN A_DIN[24] + DIRECTION INPUT ; + USE SIGNAL ; + ANTENNAPARTIALMETALAREA 1.794 LAYER Metal2 ; + ANTENNAMODEL OXIDE1 ; + ANTENNAGATEAREA 0.20085 LAYER Metal2 ; + ANTENNAMAXAREACAR 9.838188 LAYER Metal2 ; + PORT + LAYER Metal2 ; + RECT 334.41 0 334.67 0.26 ; + END + END A_DIN[24] + PIN A_DIN[7] + DIRECTION INPUT ; + USE SIGNAL ; + ANTENNAPARTIALMETALAREA 1.794 LAYER Metal2 ; + ANTENNAMODEL OXIDE1 ; + ANTENNAGATEAREA 0.20085 LAYER Metal2 ; + ANTENNAMAXAREACAR 9.838188 LAYER Metal2 ; + PORT + LAYER Metal2 ; + RECT 81.97 0 82.23 0.26 ; + END + END A_DIN[7] + PIN A_BIST_DIN[24] + DIRECTION INPUT ; + USE SIGNAL ; + ANTENNAPARTIALMETALAREA 1.6263 LAYER Metal2 ; + ANTENNAMODEL OXIDE1 ; + ANTENNAGATEAREA 0.20085 LAYER Metal2 ; + ANTENNAMAXAREACAR 9.365945 LAYER Metal2 ; + PORT + LAYER Metal2 ; + RECT 333.555 0 333.815 0.26 ; + END + END A_BIST_DIN[24] + PIN A_BIST_DIN[7] + DIRECTION INPUT ; + USE SIGNAL ; + ANTENNAPARTIALMETALAREA 1.6263 LAYER Metal2 ; + ANTENNAMODEL OXIDE1 ; + ANTENNAGATEAREA 0.20085 LAYER Metal2 ; + ANTENNAMAXAREACAR 9.365945 LAYER Metal2 ; + PORT + LAYER Metal2 ; + RECT 82.825 0 83.085 0.26 ; + END + END A_BIST_DIN[7] + PIN A_BM[24] + DIRECTION INPUT ; + USE SIGNAL ; + ANTENNAPARTIALMETALAREA 0.7215 LAYER Metal2 ; + ANTENNAMODEL OXIDE1 ; + ANTENNAGATEAREA 0.20085 LAYER Metal2 ; + ANTENNAMAXAREACAR 4.498382 LAYER Metal2 ; + PORT + LAYER Metal2 ; + RECT 326.57 0 326.83 0.26 ; + END + END A_BM[24] + PIN A_BM[7] + DIRECTION INPUT ; + USE SIGNAL ; + ANTENNAPARTIALMETALAREA 0.7215 LAYER Metal2 ; + ANTENNAMODEL OXIDE1 ; + ANTENNAGATEAREA 0.20085 LAYER Metal2 ; + ANTENNAMAXAREACAR 4.498382 LAYER Metal2 ; + PORT + LAYER Metal2 ; + RECT 89.81 0 90.07 0.26 ; + END + END A_BM[7] + PIN A_BIST_BM[24] + DIRECTION INPUT ; + USE SIGNAL ; + ANTENNAPARTIALMETALAREA 0.7605 LAYER Metal2 ; + ANTENNAMODEL OXIDE1 ; + ANTENNAGATEAREA 0.20085 LAYER Metal2 ; + ANTENNAMAXAREACAR 5.055265 LAYER Metal2 ; + PORT + LAYER Metal2 ; + RECT 327.945 0 328.205 0.26 ; + END + END A_BIST_BM[24] + PIN A_BIST_BM[7] + DIRECTION INPUT ; + USE SIGNAL ; + ANTENNAPARTIALMETALAREA 0.7605 LAYER Metal2 ; + ANTENNAMODEL OXIDE1 ; + ANTENNAGATEAREA 0.20085 LAYER Metal2 ; + ANTENNAMAXAREACAR 5.055265 LAYER Metal2 ; + PORT + LAYER Metal2 ; + RECT 88.435 0 88.695 0.26 ; + END + END A_BIST_BM[7] + PIN A_DOUT[24] + DIRECTION OUTPUT ; + USE SIGNAL ; + ANTENNAPARTIALMETALAREA 3.7095 LAYER Metal2 ; + ANTENNADIFFAREA 0.988 LAYER Metal2 ; + PORT + LAYER Metal2 ; + RECT 327.08 0 327.34 0.26 ; + END + END A_DOUT[24] + PIN A_DOUT[7] + DIRECTION OUTPUT ; + USE SIGNAL ; + ANTENNAPARTIALMETALAREA 3.7095 LAYER Metal2 ; + ANTENNADIFFAREA 0.988 LAYER Metal2 ; + PORT + LAYER Metal2 ; + RECT 89.3 0 89.56 0.26 ; + END + END A_DOUT[7] + PIN A_DIN[25] + DIRECTION INPUT ; + USE SIGNAL ; + ANTENNAPARTIALMETALAREA 1.794 LAYER Metal2 ; + ANTENNAMODEL OXIDE1 ; + ANTENNAGATEAREA 0.20085 LAYER Metal2 ; + ANTENNAMAXAREACAR 9.838188 LAYER Metal2 ; + PORT + LAYER Metal2 ; + RECT 345.65 0 345.91 0.26 ; + END + END A_DIN[25] + PIN A_DIN[6] + DIRECTION INPUT ; + USE SIGNAL ; + ANTENNAPARTIALMETALAREA 1.794 LAYER Metal2 ; + ANTENNAMODEL OXIDE1 ; + ANTENNAGATEAREA 0.20085 LAYER Metal2 ; + ANTENNAMAXAREACAR 9.838188 LAYER Metal2 ; + PORT + LAYER Metal2 ; + RECT 70.73 0 70.99 0.26 ; + END + END A_DIN[6] + PIN A_BIST_DIN[25] + DIRECTION INPUT ; + USE SIGNAL ; + ANTENNAPARTIALMETALAREA 1.6263 LAYER Metal2 ; + ANTENNAMODEL OXIDE1 ; + ANTENNAGATEAREA 0.20085 LAYER Metal2 ; + ANTENNAMAXAREACAR 9.365945 LAYER Metal2 ; + PORT + LAYER Metal2 ; + RECT 344.795 0 345.055 0.26 ; + END + END A_BIST_DIN[25] + PIN A_BIST_DIN[6] + DIRECTION INPUT ; + USE SIGNAL ; + ANTENNAPARTIALMETALAREA 1.6263 LAYER Metal2 ; + ANTENNAMODEL OXIDE1 ; + ANTENNAGATEAREA 0.20085 LAYER Metal2 ; + ANTENNAMAXAREACAR 9.365945 LAYER Metal2 ; + PORT + LAYER Metal2 ; + RECT 71.585 0 71.845 0.26 ; + END + END A_BIST_DIN[6] + PIN A_BM[25] + DIRECTION INPUT ; + USE SIGNAL ; + ANTENNAPARTIALMETALAREA 0.7215 LAYER Metal2 ; + ANTENNAMODEL OXIDE1 ; + ANTENNAGATEAREA 0.20085 LAYER Metal2 ; + ANTENNAMAXAREACAR 4.498382 LAYER Metal2 ; + PORT + LAYER Metal2 ; + RECT 337.81 0 338.07 0.26 ; + END + END A_BM[25] + PIN A_BM[6] + DIRECTION INPUT ; + USE SIGNAL ; + ANTENNAPARTIALMETALAREA 0.7215 LAYER Metal2 ; + ANTENNAMODEL OXIDE1 ; + ANTENNAGATEAREA 0.20085 LAYER Metal2 ; + ANTENNAMAXAREACAR 4.498382 LAYER Metal2 ; + PORT + LAYER Metal2 ; + RECT 78.57 0 78.83 0.26 ; + END + END A_BM[6] + PIN A_BIST_BM[25] + DIRECTION INPUT ; + USE SIGNAL ; + ANTENNAPARTIALMETALAREA 0.7605 LAYER Metal2 ; + ANTENNAMODEL OXIDE1 ; + ANTENNAGATEAREA 0.20085 LAYER Metal2 ; + ANTENNAMAXAREACAR 5.055265 LAYER Metal2 ; + PORT + LAYER Metal2 ; + RECT 339.185 0 339.445 0.26 ; + END + END A_BIST_BM[25] + PIN A_BIST_BM[6] + DIRECTION INPUT ; + USE SIGNAL ; + ANTENNAPARTIALMETALAREA 0.7605 LAYER Metal2 ; + ANTENNAMODEL OXIDE1 ; + ANTENNAGATEAREA 0.20085 LAYER Metal2 ; + ANTENNAMAXAREACAR 5.055265 LAYER Metal2 ; + PORT + LAYER Metal2 ; + RECT 77.195 0 77.455 0.26 ; + END + END A_BIST_BM[6] + PIN A_DOUT[25] + DIRECTION OUTPUT ; + USE SIGNAL ; + ANTENNAPARTIALMETALAREA 3.7095 LAYER Metal2 ; + ANTENNADIFFAREA 0.988 LAYER Metal2 ; + PORT + LAYER Metal2 ; + RECT 338.32 0 338.58 0.26 ; + END + END A_DOUT[25] + PIN A_DOUT[6] + DIRECTION OUTPUT ; + USE SIGNAL ; + ANTENNAPARTIALMETALAREA 3.7095 LAYER Metal2 ; + ANTENNADIFFAREA 0.988 LAYER Metal2 ; + PORT + LAYER Metal2 ; + RECT 78.06 0 78.32 0.26 ; + END + END A_DOUT[6] + PIN A_DIN[26] + DIRECTION INPUT ; + USE SIGNAL ; + ANTENNAPARTIALMETALAREA 1.794 LAYER Metal2 ; + ANTENNAMODEL OXIDE1 ; + ANTENNAGATEAREA 0.20085 LAYER Metal2 ; + ANTENNAMAXAREACAR 9.838188 LAYER Metal2 ; + PORT + LAYER Metal2 ; + RECT 356.89 0 357.15 0.26 ; + END + END A_DIN[26] + PIN A_DIN[5] + DIRECTION INPUT ; + USE SIGNAL ; + ANTENNAPARTIALMETALAREA 1.794 LAYER Metal2 ; + ANTENNAMODEL OXIDE1 ; + ANTENNAGATEAREA 0.20085 LAYER Metal2 ; + ANTENNAMAXAREACAR 9.838188 LAYER Metal2 ; + PORT + LAYER Metal2 ; + RECT 59.49 0 59.75 0.26 ; + END + END A_DIN[5] + PIN A_BIST_DIN[26] + DIRECTION INPUT ; + USE SIGNAL ; + ANTENNAPARTIALMETALAREA 1.6263 LAYER Metal2 ; + ANTENNAMODEL OXIDE1 ; + ANTENNAGATEAREA 0.20085 LAYER Metal2 ; + ANTENNAMAXAREACAR 9.365945 LAYER Metal2 ; + PORT + LAYER Metal2 ; + RECT 356.035 0 356.295 0.26 ; + END + END A_BIST_DIN[26] + PIN A_BIST_DIN[5] + DIRECTION INPUT ; + USE SIGNAL ; + ANTENNAPARTIALMETALAREA 1.6263 LAYER Metal2 ; + ANTENNAMODEL OXIDE1 ; + ANTENNAGATEAREA 0.20085 LAYER Metal2 ; + ANTENNAMAXAREACAR 9.365945 LAYER Metal2 ; + PORT + LAYER Metal2 ; + RECT 60.345 0 60.605 0.26 ; + END + END A_BIST_DIN[5] + PIN A_BM[26] + DIRECTION INPUT ; + USE SIGNAL ; + ANTENNAPARTIALMETALAREA 0.7215 LAYER Metal2 ; + ANTENNAMODEL OXIDE1 ; + ANTENNAGATEAREA 0.20085 LAYER Metal2 ; + ANTENNAMAXAREACAR 4.498382 LAYER Metal2 ; + PORT + LAYER Metal2 ; + RECT 349.05 0 349.31 0.26 ; + END + END A_BM[26] + PIN A_BM[5] + DIRECTION INPUT ; + USE SIGNAL ; + ANTENNAPARTIALMETALAREA 0.7215 LAYER Metal2 ; + ANTENNAMODEL OXIDE1 ; + ANTENNAGATEAREA 0.20085 LAYER Metal2 ; + ANTENNAMAXAREACAR 4.498382 LAYER Metal2 ; + PORT + LAYER Metal2 ; + RECT 67.33 0 67.59 0.26 ; + END + END A_BM[5] + PIN A_BIST_BM[26] + DIRECTION INPUT ; + USE SIGNAL ; + ANTENNAPARTIALMETALAREA 0.7605 LAYER Metal2 ; + ANTENNAMODEL OXIDE1 ; + ANTENNAGATEAREA 0.20085 LAYER Metal2 ; + ANTENNAMAXAREACAR 5.055265 LAYER Metal2 ; + PORT + LAYER Metal2 ; + RECT 350.425 0 350.685 0.26 ; + END + END A_BIST_BM[26] + PIN A_BIST_BM[5] + DIRECTION INPUT ; + USE SIGNAL ; + ANTENNAPARTIALMETALAREA 0.7605 LAYER Metal2 ; + ANTENNAMODEL OXIDE1 ; + ANTENNAGATEAREA 0.20085 LAYER Metal2 ; + ANTENNAMAXAREACAR 5.055265 LAYER Metal2 ; + PORT + LAYER Metal2 ; + RECT 65.955 0 66.215 0.26 ; + END + END A_BIST_BM[5] + PIN A_DOUT[26] + DIRECTION OUTPUT ; + USE SIGNAL ; + ANTENNAPARTIALMETALAREA 3.7095 LAYER Metal2 ; + ANTENNADIFFAREA 0.988 LAYER Metal2 ; + PORT + LAYER Metal2 ; + RECT 349.56 0 349.82 0.26 ; + END + END A_DOUT[26] + PIN A_DOUT[5] + DIRECTION OUTPUT ; + USE SIGNAL ; + ANTENNAPARTIALMETALAREA 3.7095 LAYER Metal2 ; + ANTENNADIFFAREA 0.988 LAYER Metal2 ; + PORT + LAYER Metal2 ; + RECT 66.82 0 67.08 0.26 ; + END + END A_DOUT[5] + PIN A_DIN[27] + DIRECTION INPUT ; + USE SIGNAL ; + ANTENNAPARTIALMETALAREA 1.794 LAYER Metal2 ; + ANTENNAMODEL OXIDE1 ; + ANTENNAGATEAREA 0.20085 LAYER Metal2 ; + ANTENNAMAXAREACAR 9.838188 LAYER Metal2 ; + PORT + LAYER Metal2 ; + RECT 368.13 0 368.39 0.26 ; + END + END A_DIN[27] + PIN A_DIN[4] + DIRECTION INPUT ; + USE SIGNAL ; + ANTENNAPARTIALMETALAREA 1.794 LAYER Metal2 ; + ANTENNAMODEL OXIDE1 ; + ANTENNAGATEAREA 0.20085 LAYER Metal2 ; + ANTENNAMAXAREACAR 9.838188 LAYER Metal2 ; + PORT + LAYER Metal2 ; + RECT 48.25 0 48.51 0.26 ; + END + END A_DIN[4] + PIN A_BIST_DIN[27] + DIRECTION INPUT ; + USE SIGNAL ; + ANTENNAPARTIALMETALAREA 1.6263 LAYER Metal2 ; + ANTENNAMODEL OXIDE1 ; + ANTENNAGATEAREA 0.20085 LAYER Metal2 ; + ANTENNAMAXAREACAR 9.365945 LAYER Metal2 ; + PORT + LAYER Metal2 ; + RECT 367.275 0 367.535 0.26 ; + END + END A_BIST_DIN[27] + PIN A_BIST_DIN[4] + DIRECTION INPUT ; + USE SIGNAL ; + ANTENNAPARTIALMETALAREA 1.6263 LAYER Metal2 ; + ANTENNAMODEL OXIDE1 ; + ANTENNAGATEAREA 0.20085 LAYER Metal2 ; + ANTENNAMAXAREACAR 9.365945 LAYER Metal2 ; + PORT + LAYER Metal2 ; + RECT 49.105 0 49.365 0.26 ; + END + END A_BIST_DIN[4] + PIN A_BM[27] + DIRECTION INPUT ; + USE SIGNAL ; + ANTENNAPARTIALMETALAREA 0.7215 LAYER Metal2 ; + ANTENNAMODEL OXIDE1 ; + ANTENNAGATEAREA 0.20085 LAYER Metal2 ; + ANTENNAMAXAREACAR 4.498382 LAYER Metal2 ; + PORT + LAYER Metal2 ; + RECT 360.29 0 360.55 0.26 ; + END + END A_BM[27] + PIN A_BM[4] + DIRECTION INPUT ; + USE SIGNAL ; + ANTENNAPARTIALMETALAREA 0.7215 LAYER Metal2 ; + ANTENNAMODEL OXIDE1 ; + ANTENNAGATEAREA 0.20085 LAYER Metal2 ; + ANTENNAMAXAREACAR 4.498382 LAYER Metal2 ; + PORT + LAYER Metal2 ; + RECT 56.09 0 56.35 0.26 ; + END + END A_BM[4] + PIN A_BIST_BM[27] + DIRECTION INPUT ; + USE SIGNAL ; + ANTENNAPARTIALMETALAREA 0.7605 LAYER Metal2 ; + ANTENNAMODEL OXIDE1 ; + ANTENNAGATEAREA 0.20085 LAYER Metal2 ; + ANTENNAMAXAREACAR 5.055265 LAYER Metal2 ; + PORT + LAYER Metal2 ; + RECT 361.665 0 361.925 0.26 ; + END + END A_BIST_BM[27] + PIN A_BIST_BM[4] + DIRECTION INPUT ; + USE SIGNAL ; + ANTENNAPARTIALMETALAREA 0.7605 LAYER Metal2 ; + ANTENNAMODEL OXIDE1 ; + ANTENNAGATEAREA 0.20085 LAYER Metal2 ; + ANTENNAMAXAREACAR 5.055265 LAYER Metal2 ; + PORT + LAYER Metal2 ; + RECT 54.715 0 54.975 0.26 ; + END + END A_BIST_BM[4] + PIN A_DOUT[27] + DIRECTION OUTPUT ; + USE SIGNAL ; + ANTENNAPARTIALMETALAREA 3.7095 LAYER Metal2 ; + ANTENNADIFFAREA 0.988 LAYER Metal2 ; + PORT + LAYER Metal2 ; + RECT 360.8 0 361.06 0.26 ; + END + END A_DOUT[27] + PIN A_DOUT[4] + DIRECTION OUTPUT ; + USE SIGNAL ; + ANTENNAPARTIALMETALAREA 3.7095 LAYER Metal2 ; + ANTENNADIFFAREA 0.988 LAYER Metal2 ; + PORT + LAYER Metal2 ; + RECT 55.58 0 55.84 0.26 ; + END + END A_DOUT[4] + PIN A_DIN[28] + DIRECTION INPUT ; + USE SIGNAL ; + ANTENNAPARTIALMETALAREA 1.794 LAYER Metal2 ; + ANTENNAMODEL OXIDE1 ; + ANTENNAGATEAREA 0.20085 LAYER Metal2 ; + ANTENNAMAXAREACAR 9.838188 LAYER Metal2 ; + PORT + LAYER Metal2 ; + RECT 379.37 0 379.63 0.26 ; + END + END A_DIN[28] + PIN A_DIN[3] + DIRECTION INPUT ; + USE SIGNAL ; + ANTENNAPARTIALMETALAREA 1.794 LAYER Metal2 ; + ANTENNAMODEL OXIDE1 ; + ANTENNAGATEAREA 0.20085 LAYER Metal2 ; + ANTENNAMAXAREACAR 9.838188 LAYER Metal2 ; + PORT + LAYER Metal2 ; + RECT 37.01 0 37.27 0.26 ; + END + END A_DIN[3] + PIN A_BIST_DIN[28] + DIRECTION INPUT ; + USE SIGNAL ; + ANTENNAPARTIALMETALAREA 1.6263 LAYER Metal2 ; + ANTENNAMODEL OXIDE1 ; + ANTENNAGATEAREA 0.20085 LAYER Metal2 ; + ANTENNAMAXAREACAR 9.365945 LAYER Metal2 ; + PORT + LAYER Metal2 ; + RECT 378.515 0 378.775 0.26 ; + END + END A_BIST_DIN[28] + PIN A_BIST_DIN[3] + DIRECTION INPUT ; + USE SIGNAL ; + ANTENNAPARTIALMETALAREA 1.6263 LAYER Metal2 ; + ANTENNAMODEL OXIDE1 ; + ANTENNAGATEAREA 0.20085 LAYER Metal2 ; + ANTENNAMAXAREACAR 9.365945 LAYER Metal2 ; + PORT + LAYER Metal2 ; + RECT 37.865 0 38.125 0.26 ; + END + END A_BIST_DIN[3] + PIN A_BM[28] + DIRECTION INPUT ; + USE SIGNAL ; + ANTENNAPARTIALMETALAREA 0.7215 LAYER Metal2 ; + ANTENNAMODEL OXIDE1 ; + ANTENNAGATEAREA 0.20085 LAYER Metal2 ; + ANTENNAMAXAREACAR 4.498382 LAYER Metal2 ; + PORT + LAYER Metal2 ; + RECT 371.53 0 371.79 0.26 ; + END + END A_BM[28] + PIN A_BM[3] + DIRECTION INPUT ; + USE SIGNAL ; + ANTENNAPARTIALMETALAREA 0.7215 LAYER Metal2 ; + ANTENNAMODEL OXIDE1 ; + ANTENNAGATEAREA 0.20085 LAYER Metal2 ; + ANTENNAMAXAREACAR 4.498382 LAYER Metal2 ; + PORT + LAYER Metal2 ; + RECT 44.85 0 45.11 0.26 ; + END + END A_BM[3] + PIN A_BIST_BM[28] + DIRECTION INPUT ; + USE SIGNAL ; + ANTENNAPARTIALMETALAREA 0.7605 LAYER Metal2 ; + ANTENNAMODEL OXIDE1 ; + ANTENNAGATEAREA 0.20085 LAYER Metal2 ; + ANTENNAMAXAREACAR 5.055265 LAYER Metal2 ; + PORT + LAYER Metal2 ; + RECT 372.905 0 373.165 0.26 ; + END + END A_BIST_BM[28] + PIN A_BIST_BM[3] + DIRECTION INPUT ; + USE SIGNAL ; + ANTENNAPARTIALMETALAREA 0.7605 LAYER Metal2 ; + ANTENNAMODEL OXIDE1 ; + ANTENNAGATEAREA 0.20085 LAYER Metal2 ; + ANTENNAMAXAREACAR 5.055265 LAYER Metal2 ; + PORT + LAYER Metal2 ; + RECT 43.475 0 43.735 0.26 ; + END + END A_BIST_BM[3] + PIN A_DOUT[28] + DIRECTION OUTPUT ; + USE SIGNAL ; + ANTENNAPARTIALMETALAREA 3.7095 LAYER Metal2 ; + ANTENNADIFFAREA 0.988 LAYER Metal2 ; + PORT + LAYER Metal2 ; + RECT 372.04 0 372.3 0.26 ; + END + END A_DOUT[28] + PIN A_DOUT[3] + DIRECTION OUTPUT ; + USE SIGNAL ; + ANTENNAPARTIALMETALAREA 3.7095 LAYER Metal2 ; + ANTENNADIFFAREA 0.988 LAYER Metal2 ; + PORT + LAYER Metal2 ; + RECT 44.34 0 44.6 0.26 ; + END + END A_DOUT[3] + PIN A_DIN[29] + DIRECTION INPUT ; + USE SIGNAL ; + ANTENNAPARTIALMETALAREA 1.794 LAYER Metal2 ; + ANTENNAMODEL OXIDE1 ; + ANTENNAGATEAREA 0.20085 LAYER Metal2 ; + ANTENNAMAXAREACAR 9.838188 LAYER Metal2 ; + PORT + LAYER Metal2 ; + RECT 390.61 0 390.87 0.26 ; + END + END A_DIN[29] + PIN A_DIN[2] + DIRECTION INPUT ; + USE SIGNAL ; + ANTENNAPARTIALMETALAREA 1.794 LAYER Metal2 ; + ANTENNAMODEL OXIDE1 ; + ANTENNAGATEAREA 0.20085 LAYER Metal2 ; + ANTENNAMAXAREACAR 9.838188 LAYER Metal2 ; + PORT + LAYER Metal2 ; + RECT 25.77 0 26.03 0.26 ; + END + END A_DIN[2] + PIN A_BIST_DIN[29] + DIRECTION INPUT ; + USE SIGNAL ; + ANTENNAPARTIALMETALAREA 1.6263 LAYER Metal2 ; + ANTENNAMODEL OXIDE1 ; + ANTENNAGATEAREA 0.20085 LAYER Metal2 ; + ANTENNAMAXAREACAR 9.365945 LAYER Metal2 ; + PORT + LAYER Metal2 ; + RECT 389.755 0 390.015 0.26 ; + END + END A_BIST_DIN[29] + PIN A_BIST_DIN[2] + DIRECTION INPUT ; + USE SIGNAL ; + ANTENNAPARTIALMETALAREA 1.6263 LAYER Metal2 ; + ANTENNAMODEL OXIDE1 ; + ANTENNAGATEAREA 0.20085 LAYER Metal2 ; + ANTENNAMAXAREACAR 9.365945 LAYER Metal2 ; + PORT + LAYER Metal2 ; + RECT 26.625 0 26.885 0.26 ; + END + END A_BIST_DIN[2] + PIN A_BM[29] + DIRECTION INPUT ; + USE SIGNAL ; + ANTENNAPARTIALMETALAREA 0.7215 LAYER Metal2 ; + ANTENNAMODEL OXIDE1 ; + ANTENNAGATEAREA 0.20085 LAYER Metal2 ; + ANTENNAMAXAREACAR 4.498382 LAYER Metal2 ; + PORT + LAYER Metal2 ; + RECT 382.77 0 383.03 0.26 ; + END + END A_BM[29] + PIN A_BM[2] + DIRECTION INPUT ; + USE SIGNAL ; + ANTENNAPARTIALMETALAREA 0.7215 LAYER Metal2 ; + ANTENNAMODEL OXIDE1 ; + ANTENNAGATEAREA 0.20085 LAYER Metal2 ; + ANTENNAMAXAREACAR 4.498382 LAYER Metal2 ; + PORT + LAYER Metal2 ; + RECT 33.61 0 33.87 0.26 ; + END + END A_BM[2] + PIN A_BIST_BM[29] + DIRECTION INPUT ; + USE SIGNAL ; + ANTENNAPARTIALMETALAREA 0.7605 LAYER Metal2 ; + ANTENNAMODEL OXIDE1 ; + ANTENNAGATEAREA 0.20085 LAYER Metal2 ; + ANTENNAMAXAREACAR 5.055265 LAYER Metal2 ; + PORT + LAYER Metal2 ; + RECT 384.145 0 384.405 0.26 ; + END + END A_BIST_BM[29] + PIN A_BIST_BM[2] + DIRECTION INPUT ; + USE SIGNAL ; + ANTENNAPARTIALMETALAREA 0.7605 LAYER Metal2 ; + ANTENNAMODEL OXIDE1 ; + ANTENNAGATEAREA 0.20085 LAYER Metal2 ; + ANTENNAMAXAREACAR 5.055265 LAYER Metal2 ; + PORT + LAYER Metal2 ; + RECT 32.235 0 32.495 0.26 ; + END + END A_BIST_BM[2] + PIN A_DOUT[29] + DIRECTION OUTPUT ; + USE SIGNAL ; + ANTENNAPARTIALMETALAREA 3.7095 LAYER Metal2 ; + ANTENNADIFFAREA 0.988 LAYER Metal2 ; + PORT + LAYER Metal2 ; + RECT 383.28 0 383.54 0.26 ; + END + END A_DOUT[29] + PIN A_DOUT[2] + DIRECTION OUTPUT ; + USE SIGNAL ; + ANTENNAPARTIALMETALAREA 3.7095 LAYER Metal2 ; + ANTENNADIFFAREA 0.988 LAYER Metal2 ; + PORT + LAYER Metal2 ; + RECT 33.1 0 33.36 0.26 ; + END + END A_DOUT[2] + PIN A_DIN[30] + DIRECTION INPUT ; + USE SIGNAL ; + ANTENNAPARTIALMETALAREA 1.794 LAYER Metal2 ; + ANTENNAMODEL OXIDE1 ; + ANTENNAGATEAREA 0.20085 LAYER Metal2 ; + ANTENNAMAXAREACAR 9.838188 LAYER Metal2 ; + PORT + LAYER Metal2 ; + RECT 401.85 0 402.11 0.26 ; + END + END A_DIN[30] + PIN A_DIN[1] + DIRECTION INPUT ; + USE SIGNAL ; + ANTENNAPARTIALMETALAREA 1.794 LAYER Metal2 ; + ANTENNAMODEL OXIDE1 ; + ANTENNAGATEAREA 0.20085 LAYER Metal2 ; + ANTENNAMAXAREACAR 9.838188 LAYER Metal2 ; + PORT + LAYER Metal2 ; + RECT 14.53 0 14.79 0.26 ; + END + END A_DIN[1] + PIN A_BIST_DIN[30] + DIRECTION INPUT ; + USE SIGNAL ; + ANTENNAPARTIALMETALAREA 1.6263 LAYER Metal2 ; + ANTENNAMODEL OXIDE1 ; + ANTENNAGATEAREA 0.20085 LAYER Metal2 ; + ANTENNAMAXAREACAR 9.365945 LAYER Metal2 ; + PORT + LAYER Metal2 ; + RECT 400.995 0 401.255 0.26 ; + END + END A_BIST_DIN[30] + PIN A_BIST_DIN[1] + DIRECTION INPUT ; + USE SIGNAL ; + ANTENNAPARTIALMETALAREA 1.6263 LAYER Metal2 ; + ANTENNAMODEL OXIDE1 ; + ANTENNAGATEAREA 0.20085 LAYER Metal2 ; + ANTENNAMAXAREACAR 9.365945 LAYER Metal2 ; + PORT + LAYER Metal2 ; + RECT 15.385 0 15.645 0.26 ; + END + END A_BIST_DIN[1] + PIN A_BM[30] + DIRECTION INPUT ; + USE SIGNAL ; + ANTENNAPARTIALMETALAREA 0.7215 LAYER Metal2 ; + ANTENNAMODEL OXIDE1 ; + ANTENNAGATEAREA 0.20085 LAYER Metal2 ; + ANTENNAMAXAREACAR 4.498382 LAYER Metal2 ; + PORT + LAYER Metal2 ; + RECT 394.01 0 394.27 0.26 ; + END + END A_BM[30] + PIN A_BM[1] + DIRECTION INPUT ; + USE SIGNAL ; + ANTENNAPARTIALMETALAREA 0.7215 LAYER Metal2 ; + ANTENNAMODEL OXIDE1 ; + ANTENNAGATEAREA 0.20085 LAYER Metal2 ; + ANTENNAMAXAREACAR 4.498382 LAYER Metal2 ; + PORT + LAYER Metal2 ; + RECT 22.37 0 22.63 0.26 ; + END + END A_BM[1] + PIN A_BIST_BM[30] + DIRECTION INPUT ; + USE SIGNAL ; + ANTENNAPARTIALMETALAREA 0.7605 LAYER Metal2 ; + ANTENNAMODEL OXIDE1 ; + ANTENNAGATEAREA 0.20085 LAYER Metal2 ; + ANTENNAMAXAREACAR 5.055265 LAYER Metal2 ; + PORT + LAYER Metal2 ; + RECT 395.385 0 395.645 0.26 ; + END + END A_BIST_BM[30] + PIN A_BIST_BM[1] + DIRECTION INPUT ; + USE SIGNAL ; + ANTENNAPARTIALMETALAREA 0.7605 LAYER Metal2 ; + ANTENNAMODEL OXIDE1 ; + ANTENNAGATEAREA 0.20085 LAYER Metal2 ; + ANTENNAMAXAREACAR 5.055265 LAYER Metal2 ; + PORT + LAYER Metal2 ; + RECT 20.995 0 21.255 0.26 ; + END + END A_BIST_BM[1] + PIN A_DOUT[30] + DIRECTION OUTPUT ; + USE SIGNAL ; + ANTENNAPARTIALMETALAREA 3.7095 LAYER Metal2 ; + ANTENNADIFFAREA 0.988 LAYER Metal2 ; + PORT + LAYER Metal2 ; + RECT 394.52 0 394.78 0.26 ; + END + END A_DOUT[30] + PIN A_DOUT[1] + DIRECTION OUTPUT ; + USE SIGNAL ; + ANTENNAPARTIALMETALAREA 3.7095 LAYER Metal2 ; + ANTENNADIFFAREA 0.988 LAYER Metal2 ; + PORT + LAYER Metal2 ; + RECT 21.86 0 22.12 0.26 ; + END + END A_DOUT[1] + PIN A_DIN[31] + DIRECTION INPUT ; + USE SIGNAL ; + ANTENNAPARTIALMETALAREA 1.794 LAYER Metal2 ; + ANTENNAMODEL OXIDE1 ; + ANTENNAGATEAREA 0.20085 LAYER Metal2 ; + ANTENNAMAXAREACAR 9.838188 LAYER Metal2 ; + PORT + LAYER Metal2 ; + RECT 413.09 0 413.35 0.26 ; + END + END A_DIN[31] + PIN A_DIN[0] + DIRECTION INPUT ; + USE SIGNAL ; + ANTENNAPARTIALMETALAREA 1.794 LAYER Metal2 ; + ANTENNAMODEL OXIDE1 ; + ANTENNAGATEAREA 0.20085 LAYER Metal2 ; + ANTENNAMAXAREACAR 9.838188 LAYER Metal2 ; + PORT + LAYER Metal2 ; + RECT 3.29 0 3.55 0.26 ; + END + END A_DIN[0] + PIN A_BIST_DIN[31] + DIRECTION INPUT ; + USE SIGNAL ; + ANTENNAPARTIALMETALAREA 1.6263 LAYER Metal2 ; + ANTENNAMODEL OXIDE1 ; + ANTENNAGATEAREA 0.20085 LAYER Metal2 ; + ANTENNAMAXAREACAR 9.365945 LAYER Metal2 ; + PORT + LAYER Metal2 ; + RECT 412.235 0 412.495 0.26 ; + END + END A_BIST_DIN[31] + PIN A_BIST_DIN[0] + DIRECTION INPUT ; + USE SIGNAL ; + ANTENNAPARTIALMETALAREA 1.6263 LAYER Metal2 ; + ANTENNAMODEL OXIDE1 ; + ANTENNAGATEAREA 0.20085 LAYER Metal2 ; + ANTENNAMAXAREACAR 9.365945 LAYER Metal2 ; + PORT + LAYER Metal2 ; + RECT 4.145 0 4.405 0.26 ; + END + END A_BIST_DIN[0] + PIN A_BM[31] + DIRECTION INPUT ; + USE SIGNAL ; + ANTENNAPARTIALMETALAREA 0.7215 LAYER Metal2 ; + ANTENNAMODEL OXIDE1 ; + ANTENNAGATEAREA 0.20085 LAYER Metal2 ; + ANTENNAMAXAREACAR 4.498382 LAYER Metal2 ; + PORT + LAYER Metal2 ; + RECT 405.25 0 405.51 0.26 ; + END + END A_BM[31] + PIN A_BM[0] + DIRECTION INPUT ; + USE SIGNAL ; + ANTENNAPARTIALMETALAREA 0.7215 LAYER Metal2 ; + ANTENNAMODEL OXIDE1 ; + ANTENNAGATEAREA 0.20085 LAYER Metal2 ; + ANTENNAMAXAREACAR 4.498382 LAYER Metal2 ; + PORT + LAYER Metal2 ; + RECT 11.13 0 11.39 0.26 ; + END + END A_BM[0] + PIN A_BIST_BM[31] + DIRECTION INPUT ; + USE SIGNAL ; + ANTENNAPARTIALMETALAREA 0.7605 LAYER Metal2 ; + ANTENNAMODEL OXIDE1 ; + ANTENNAGATEAREA 0.20085 LAYER Metal2 ; + ANTENNAMAXAREACAR 5.055265 LAYER Metal2 ; + PORT + LAYER Metal2 ; + RECT 406.625 0 406.885 0.26 ; + END + END A_BIST_BM[31] + PIN A_BIST_BM[0] + DIRECTION INPUT ; + USE SIGNAL ; + ANTENNAPARTIALMETALAREA 0.7605 LAYER Metal2 ; + ANTENNAMODEL OXIDE1 ; + ANTENNAGATEAREA 0.20085 LAYER Metal2 ; + ANTENNAMAXAREACAR 5.055265 LAYER Metal2 ; + PORT + LAYER Metal2 ; + RECT 9.755 0 10.015 0.26 ; + END + END A_BIST_BM[0] + PIN A_DOUT[31] + DIRECTION OUTPUT ; + USE SIGNAL ; + ANTENNAPARTIALMETALAREA 3.7095 LAYER Metal2 ; + ANTENNADIFFAREA 0.988 LAYER Metal2 ; + PORT + LAYER Metal2 ; + RECT 405.76 0 406.02 0.26 ; + END + END A_DOUT[31] + PIN A_DOUT[0] + DIRECTION OUTPUT ; + USE SIGNAL ; + ANTENNAPARTIALMETALAREA 3.7095 LAYER Metal2 ; + ANTENNADIFFAREA 0.988 LAYER Metal2 ; + PORT + LAYER Metal2 ; + RECT 10.62 0 10.88 0.26 ; + END + END A_DOUT[0] + PIN A_ADDR[0] + DIRECTION INPUT ; + USE SIGNAL ; + ANTENNAPARTIALMETALAREA 8.9011 LAYER Metal2 ; + ANTENNAMODEL OXIDE1 ; + ANTENNAGATEAREA 0.20085 LAYER Metal2 ; + ANTENNAMAXAREACAR 45.223301 LAYER Metal2 ; + PORT + LAYER Metal2 ; + RECT 204.52 0 204.78 0.26 ; + END + END A_ADDR[0] + PIN A_BIST_ADDR[0] + DIRECTION INPUT ; + USE SIGNAL ; + ANTENNAPARTIALMETALAREA 9.6967 LAYER Metal2 ; + ANTENNAMODEL OXIDE1 ; + ANTENNAGATEAREA 0.20085 LAYER Metal2 ; + ANTENNAMAXAREACAR 49.184466 LAYER Metal2 ; + PORT + LAYER Metal2 ; + RECT 209.11 0 209.37 0.26 ; + END + END A_BIST_ADDR[0] + PIN A_ADDR[1] + DIRECTION INPUT ; + USE SIGNAL ; + ANTENNAPARTIALMETALAREA 7.774 LAYER Metal2 ; + ANTENNAMODEL OXIDE1 ; + ANTENNAGATEAREA 0.20085 LAYER Metal2 ; + ANTENNAMAXAREACAR 39.656958 LAYER Metal2 ; + PORT + LAYER Metal2 ; + RECT 204.01 0 204.27 0.26 ; + END + END A_ADDR[1] + PIN A_BIST_ADDR[1] + DIRECTION INPUT ; + USE SIGNAL ; + ANTENNAPARTIALMETALAREA 8.5696 LAYER Metal2 ; + ANTENNAMODEL OXIDE1 ; + ANTENNAGATEAREA 0.20085 LAYER Metal2 ; + ANTENNAMAXAREACAR 43.618123 LAYER Metal2 ; + PORT + LAYER Metal2 ; + RECT 208.6 0 208.86 0.26 ; + END + END A_BIST_ADDR[1] + PIN A_ADDR[2] + DIRECTION INPUT ; + USE SIGNAL ; + ANTENNAPARTIALMETALAREA 10.6327 LAYER Metal2 ; + ANTENNAPARTIALMETALAREA 1.5246 LAYER Metal3 ; + ANTENNAPARTIALCUTAREA 0.0722 LAYER Via2 ; + ANTENNAMODEL OXIDE1 ; + ANTENNAGATEAREA 0.20085 LAYER Metal3 ; + ANTENNAMAXAREACAR 9.415982 LAYER Metal3 ; + PORT + LAYER Metal2 ; + RECT 212.17 0 212.43 0.26 ; + END + END A_ADDR[2] + PIN A_BIST_ADDR[2] + DIRECTION INPUT ; + USE SIGNAL ; + ANTENNAPARTIALMETALAREA 10.6327 LAYER Metal2 ; + ANTENNAPARTIALMETALAREA 1.0962 LAYER Metal3 ; + ANTENNAPARTIALCUTAREA 0.0722 LAYER Via2 ; + ANTENNAMODEL OXIDE1 ; + ANTENNAGATEAREA 0.20085 LAYER Metal3 ; + ANTENNAMAXAREACAR 7.813791 LAYER Metal3 ; + PORT + LAYER Metal2 ; + RECT 212.68 0 212.94 0.26 ; + END + END A_BIST_ADDR[2] + PIN A_ADDR[3] + DIRECTION INPUT ; + USE SIGNAL ; + ANTENNAPARTIALMETALAREA 10.6327 LAYER Metal2 ; + ANTENNAPARTIALMETALAREA 3.8367 LAYER Metal3 ; + ANTENNAPARTIALCUTAREA 0.0722 LAYER Via2 ; + ANTENNAMODEL OXIDE1 ; + ANTENNAGATEAREA 0.20085 LAYER Metal3 ; + ANTENNAMAXAREACAR 20.927558 LAYER Metal3 ; + PORT + LAYER Metal2 ; + RECT 211.15 0 211.41 0.26 ; + END + END A_ADDR[3] + PIN A_BIST_ADDR[3] + DIRECTION INPUT ; + USE SIGNAL ; + ANTENNAPARTIALMETALAREA 10.6327 LAYER Metal2 ; + ANTENNAPARTIALMETALAREA 3.5175 LAYER Metal3 ; + ANTENNAPARTIALCUTAREA 0.0722 LAYER Via2 ; + ANTENNAMODEL OXIDE1 ; + ANTENNAGATEAREA 0.20085 LAYER Metal3 ; + ANTENNAMAXAREACAR 19.869057 LAYER Metal3 ; + PORT + LAYER Metal2 ; + RECT 211.66 0 211.92 0.26 ; + END + END A_BIST_ADDR[3] + PIN A_ADDR[4] + DIRECTION INPUT ; + USE SIGNAL ; + ANTENNAPARTIALMETALAREA 12.1979 LAYER Metal2 ; + ANTENNAMODEL OXIDE1 ; + ANTENNAGATEAREA 0.20085 LAYER Metal2 ; + ANTENNAMAXAREACAR 61.63754 LAYER Metal2 ; + PORT + LAYER Metal2 ; + RECT 214.72 0 214.98 0.26 ; + END + END A_ADDR[4] + PIN A_BIST_ADDR[4] + DIRECTION INPUT ; + USE SIGNAL ; + ANTENNAPARTIALMETALAREA 11.9327 LAYER Metal2 ; + ANTENNAMODEL OXIDE1 ; + ANTENNAGATEAREA 0.20085 LAYER Metal2 ; + ANTENNAMAXAREACAR 60.317152 LAYER Metal2 ; + PORT + LAYER Metal2 ; + RECT 214.21 0 214.47 0.26 ; + END + END A_BIST_ADDR[4] + PIN A_ADDR[5] + DIRECTION INPUT ; + USE SIGNAL ; + ANTENNAPARTIALMETALAREA 13.9269 LAYER Metal2 ; + ANTENNAMODEL OXIDE1 ; + ANTENNAGATEAREA 0.20085 LAYER Metal2 ; + ANTENNAMAXAREACAR 70.245955 LAYER Metal2 ; + PORT + LAYER Metal2 ; + RECT 213.7 0 213.96 0.26 ; + END + END A_ADDR[5] + PIN A_BIST_ADDR[5] + DIRECTION INPUT ; + USE SIGNAL ; + ANTENNAPARTIALMETALAREA 13.6617 LAYER Metal2 ; + ANTENNAMODEL OXIDE1 ; + ANTENNAGATEAREA 0.20085 LAYER Metal2 ; + ANTENNAMAXAREACAR 68.925566 LAYER Metal2 ; + PORT + LAYER Metal2 ; + RECT 213.19 0 213.45 0.26 ; + END + END A_BIST_ADDR[5] + PIN A_ADDR[6] + DIRECTION INPUT ; + USE SIGNAL ; + ANTENNAPARTIALMETALAREA 10.9525 LAYER Metal2 ; + ANTENNAMODEL OXIDE1 ; + ANTENNAGATEAREA 0.20085 LAYER Metal2 ; + ANTENNAMAXAREACAR 55.436893 LAYER Metal2 ; + PORT + LAYER Metal2 ; + RECT 192.28 0 192.54 0.26 ; + END + END A_ADDR[6] + PIN A_BIST_ADDR[6] + DIRECTION INPUT ; + USE SIGNAL ; + ANTENNAPARTIALMETALAREA 10.6771 LAYER Metal2 ; + ANTENNAMODEL OXIDE1 ; + ANTENNAGATEAREA 0.20085 LAYER Metal2 ; + ANTENNAMAXAREACAR 54.065721 LAYER Metal2 ; + PORT + LAYER Metal2 ; + RECT 192.79 0 193.05 0.26 ; + END + END A_BIST_ADDR[6] + PIN A_ADDR[7] + DIRECTION INPUT ; + USE SIGNAL ; + ANTENNAPARTIALMETALAREA 12.4163 LAYER Metal2 ; + ANTENNAMODEL OXIDE1 ; + ANTENNAGATEAREA 0.20085 LAYER Metal2 ; + ANTENNAMAXAREACAR 62.724919 LAYER Metal2 ; + PORT + LAYER Metal2 ; + RECT 193.3 0 193.56 0.26 ; + END + END A_ADDR[7] + PIN A_BIST_ADDR[7] + DIRECTION INPUT ; + USE SIGNAL ; + ANTENNAPARTIALMETALAREA 12.1511 LAYER Metal2 ; + ANTENNAMODEL OXIDE1 ; + ANTENNAGATEAREA 0.20085 LAYER Metal2 ; + ANTENNAMAXAREACAR 61.404531 LAYER Metal2 ; + PORT + LAYER Metal2 ; + RECT 193.81 0 194.07 0.26 ; + END + END A_BIST_ADDR[7] + PIN A_ADDR[8] + DIRECTION INPUT ; + USE SIGNAL ; + ANTENNAPARTIALMETALAREA 10.3675 LAYER Metal2 ; + ANTENNAPARTIALMETALAREA 1.5897 LAYER Metal3 ; + ANTENNAPARTIALCUTAREA 0.0722 LAYER Via2 ; + ANTENNAMODEL OXIDE1 ; + ANTENNAGATEAREA 0.20085 LAYER Metal3 ; + ANTENNAMAXAREACAR 9.740105 LAYER Metal3 ; + PORT + LAYER Metal2 ; + RECT 222.37 0 222.63 0.26 ; + END + END A_ADDR[8] + PIN A_BIST_ADDR[8] + DIRECTION INPUT ; + USE SIGNAL ; + ANTENNAPARTIALMETALAREA 10.3675 LAYER Metal2 ; + ANTENNAPARTIALMETALAREA 1.3755 LAYER Metal3 ; + ANTENNAPARTIALCUTAREA 0.0722 LAYER Via2 ; + ANTENNAMODEL OXIDE1 ; + ANTENNAGATEAREA 0.20085 LAYER Metal3 ; + ANTENNAMAXAREACAR 9.204381 LAYER Metal3 ; + PORT + LAYER Metal2 ; + RECT 222.88 0 223.14 0.26 ; + END + END A_BIST_ADDR[8] + PIN A_CLK + DIRECTION INPUT ; + USE SIGNAL ; + ANTENNAPARTIALMETALAREA 4.0547 LAYER Metal2 ; + ANTENNAMODEL OXIDE1 ; + ANTENNAGATEAREA 0.20085 LAYER Metal2 ; + ANTENNAMAXAREACAR 21.093851 LAYER Metal2 ; + PORT + LAYER Metal2 ; + RECT 202.48 0 202.74 0.26 ; + END + END A_CLK + PIN A_REN + DIRECTION INPUT ; + USE SIGNAL ; + ANTENNAPARTIALMETALAREA 3.99505 LAYER Metal2 ; + ANTENNAMODEL OXIDE1 ; + ANTENNAGATEAREA 0.20085 LAYER Metal2 ; + ANTENNAMAXAREACAR 20.796863 LAYER Metal2 ; + PORT + LAYER Metal2 ; + RECT 206.05 0 206.31 0.26 ; + END + END A_REN + PIN A_WEN + DIRECTION INPUT ; + USE SIGNAL ; + ANTENNAPARTIALMETALAREA 2.8847 LAYER Metal2 ; + ANTENNAMODEL OXIDE1 ; + ANTENNAGATEAREA 0.20085 LAYER Metal2 ; + ANTENNAMAXAREACAR 15.268608 LAYER Metal2 ; + PORT + LAYER Metal2 ; + RECT 205.54 0 205.8 0.26 ; + END + END A_WEN + PIN A_MEN + DIRECTION INPUT ; + USE SIGNAL ; + ANTENNAPARTIALMETALAREA 3.0247 LAYER Metal2 ; + ANTENNAMODEL OXIDE1 ; + ANTENNAGATEAREA 0.20085 LAYER Metal2 ; + ANTENNAMAXAREACAR 15.965646 LAYER Metal2 ; + PORT + LAYER Metal2 ; + RECT 202.99 0 203.25 0.26 ; + END + END A_MEN + PIN A_DLY + DIRECTION INPUT ; + USE SIGNAL ; + ANTENNAPARTIALMETALAREA 6.058 LAYER Metal2 ; + ANTENNAMODEL OXIDE1 ; + ANTENNAGATEAREA 0.3367 LAYER Metal2 ; + ANTENNAMAXAREACAR 18.532819 LAYER Metal2 ; + PORT + LAYER Metal2 ; + RECT 224.41 0 224.67 0.26 ; + END + END A_DLY + PIN A_BIST_EN + DIRECTION INPUT ; + USE SIGNAL ; + ANTENNAPARTIALMETALAREA 3.9871 LAYER Metal2 ; + ANTENNAPARTIALMETALAREA 203.31695 LAYER Metal3 ; + ANTENNAPARTIALCUTAREA 0.0722 LAYER Via2 ; + ANTENNAMODEL OXIDE1 ; + ANTENNAGATEAREA 1.43 LAYER Metal2 ; + ANTENNAGATEAREA 27.5275 LAYER Metal3 ; + ANTENNAMAXAREACAR 3.213636 LAYER Metal2 ; + ANTENNAMAXAREACAR 17.658685 LAYER Metal3 ; + ANTENNAMAXCUTCAR 0.151469 LAYER Via2 ; + PORT + LAYER Metal2 ; + RECT 205.03 0 205.29 0.26 ; + END + END A_BIST_EN + PIN A_BIST_CLK + DIRECTION INPUT ; + USE SIGNAL ; + ANTENNAPARTIALMETALAREA 4.1639 LAYER Metal2 ; + ANTENNAMODEL OXIDE1 ; + ANTENNAGATEAREA 0.20085 LAYER Metal2 ; + ANTENNAMAXAREACAR 21.953448 LAYER Metal2 ; + PORT + LAYER Metal2 ; + RECT 200.95 0 201.21 0.26 ; + END + END A_BIST_CLK + PIN A_BIST_REN + DIRECTION INPUT ; + USE SIGNAL ; + ANTENNAPARTIALMETALAREA 4.1119 LAYER Metal2 ; + ANTENNAMODEL OXIDE1 ; + ANTENNAGATEAREA 0.20085 LAYER Metal2 ; + ANTENNAMAXAREACAR 21.694548 LAYER Metal2 ; + PORT + LAYER Metal2 ; + RECT 207.58 0 207.84 0.26 ; + END + END A_BIST_REN + PIN A_BIST_WEN + DIRECTION INPUT ; + USE SIGNAL ; + ANTENNAPARTIALMETALAREA 2.9051 LAYER Metal2 ; + ANTENNAMODEL OXIDE1 ; + ANTENNAGATEAREA 0.20085 LAYER Metal2 ; + ANTENNAMAXAREACAR 15.686084 LAYER Metal2 ; + PORT + LAYER Metal2 ; + RECT 207.07 0 207.33 0.26 ; + END + END A_BIST_WEN + PIN A_BIST_MEN + DIRECTION INPUT ; + USE SIGNAL ; + ANTENNAPARTIALMETALAREA 2.8977 LAYER Metal2 ; + ANTENNAMODEL OXIDE1 ; + ANTENNAGATEAREA 0.20085 LAYER Metal2 ; + ANTENNAMAXAREACAR 15.649241 LAYER Metal2 ; + PORT + LAYER Metal2 ; + RECT 201.46 0 201.72 0.26 ; + END + END A_BIST_MEN + OBS + LAYER Metal1 ; + RECT 0 0 416.64 191.34 ; + LAYER Metal2 ; + RECT 0.105 45.465 0.305 191.315 ; + RECT 1.1 190.585 1.3 191.315 ; + RECT 3.29 0.52 3.55 5.16 ; + RECT 2.77 4.9 3.55 5.16 ; + RECT 2.77 4.9 3.03 6.64 ; + RECT 1.92 190.585 2.12 191.315 ; + RECT 2.415 190.585 2.615 191.315 ; + RECT 2.915 190.585 3.115 191.315 ; + RECT 3.415 190.585 3.615 191.315 ; + RECT 3.91 190.585 4.11 191.315 ; + RECT 4.655 0.17 5.425 0.94 ; + RECT 4.655 0.17 4.915 12.9 ; + RECT 5.165 0.17 5.425 12.9 ; + RECT 4.145 0.52 4.405 5.815 ; + RECT 4.73 190.585 4.93 191.315 ; + RECT 5.675 0.17 6.445 0.43 ; + RECT 5.675 0.17 5.935 11.5 ; + RECT 6.185 0.17 6.445 11.5 ; + RECT 5.225 190.585 5.425 191.315 ; + RECT 5.725 190.585 5.925 191.315 ; + RECT 6.225 190.585 6.425 191.315 ; + RECT 7.715 0.17 8.485 0.43 ; + RECT 7.715 0.17 7.975 10.48 ; + RECT 8.225 0.17 8.485 10.99 ; + RECT 6.72 190.585 6.92 191.315 ; + RECT 7.54 190.585 7.74 191.315 ; + RECT 8.735 0.17 9.505 0.94 ; + RECT 8.735 0.17 8.995 8.7 ; + RECT 9.245 0.17 9.505 12.9 ; + RECT 8.035 190.585 8.235 191.315 ; + RECT 8.535 190.585 8.735 191.315 ; + RECT 9.035 190.585 9.235 191.315 ; + RECT 9.53 190.585 9.73 191.315 ; + RECT 9.755 0.52 10.015 2.485 ; + RECT 10.35 190.585 10.55 191.315 ; + RECT 10.62 0.52 10.88 14.11 ; + RECT 10.845 190.585 11.045 191.315 ; + RECT 11.13 0.52 11.39 2.335 ; + RECT 11.345 190.585 11.545 191.315 ; + RECT 11.845 190.585 12.045 191.315 ; + RECT 12.34 190.585 12.54 191.315 ; + RECT 14.53 0.52 14.79 5.16 ; + RECT 14.01 4.9 14.79 5.16 ; + RECT 14.01 4.9 14.27 6.64 ; + RECT 13.16 190.585 13.36 191.315 ; + RECT 13.655 190.585 13.855 191.315 ; + RECT 14.155 190.585 14.355 191.315 ; + RECT 14.655 190.585 14.855 191.315 ; + RECT 15.15 190.585 15.35 191.315 ; + RECT 15.895 0.17 16.665 0.94 ; + RECT 15.895 0.17 16.155 12.9 ; + RECT 16.405 0.17 16.665 12.9 ; + RECT 15.385 0.52 15.645 5.815 ; + RECT 15.97 190.585 16.17 191.315 ; + RECT 16.915 0.17 17.685 0.43 ; + RECT 16.915 0.17 17.175 11.5 ; + RECT 17.425 0.17 17.685 11.5 ; + RECT 16.465 190.585 16.665 191.315 ; + RECT 16.965 190.585 17.165 191.315 ; + RECT 17.465 190.585 17.665 191.315 ; + RECT 18.955 0.17 19.725 0.43 ; + RECT 18.955 0.17 19.215 10.48 ; + RECT 19.465 0.17 19.725 10.99 ; + RECT 17.96 190.585 18.16 191.315 ; + RECT 18.78 190.585 18.98 191.315 ; + RECT 19.975 0.17 20.745 0.94 ; + RECT 19.975 0.17 20.235 8.7 ; + RECT 20.485 0.17 20.745 12.9 ; + RECT 19.275 190.585 19.475 191.315 ; + RECT 19.775 190.585 19.975 191.315 ; + RECT 20.275 190.585 20.475 191.315 ; + RECT 20.77 190.585 20.97 191.315 ; + RECT 20.995 0.52 21.255 2.485 ; + RECT 21.59 190.585 21.79 191.315 ; + RECT 21.86 0.52 22.12 14.11 ; + RECT 22.085 190.585 22.285 191.315 ; + RECT 22.37 0.52 22.63 2.335 ; + RECT 22.585 190.585 22.785 191.315 ; + RECT 23.085 190.585 23.285 191.315 ; + RECT 23.58 190.585 23.78 191.315 ; + RECT 25.77 0.52 26.03 5.16 ; + RECT 25.25 4.9 26.03 5.16 ; + RECT 25.25 4.9 25.51 6.64 ; + RECT 24.4 190.585 24.6 191.315 ; + RECT 24.895 190.585 25.095 191.315 ; + RECT 25.395 190.585 25.595 191.315 ; + RECT 25.895 190.585 26.095 191.315 ; + RECT 26.39 190.585 26.59 191.315 ; + RECT 27.135 0.17 27.905 0.94 ; + RECT 27.135 0.17 27.395 12.9 ; + RECT 27.645 0.17 27.905 12.9 ; + RECT 26.625 0.52 26.885 5.815 ; + RECT 27.21 190.585 27.41 191.315 ; + RECT 28.155 0.17 28.925 0.43 ; + RECT 28.155 0.17 28.415 11.5 ; + RECT 28.665 0.17 28.925 11.5 ; + RECT 27.705 190.585 27.905 191.315 ; + RECT 28.205 190.585 28.405 191.315 ; + RECT 28.705 190.585 28.905 191.315 ; + RECT 30.195 0.17 30.965 0.43 ; + RECT 30.195 0.17 30.455 10.48 ; + RECT 30.705 0.17 30.965 10.99 ; + RECT 29.2 190.585 29.4 191.315 ; + RECT 30.02 190.585 30.22 191.315 ; + RECT 31.215 0.17 31.985 0.94 ; + RECT 31.215 0.17 31.475 8.7 ; + RECT 31.725 0.17 31.985 12.9 ; + RECT 30.515 190.585 30.715 191.315 ; + RECT 31.015 190.585 31.215 191.315 ; + RECT 31.515 190.585 31.715 191.315 ; + RECT 32.01 190.585 32.21 191.315 ; + RECT 32.235 0.52 32.495 2.485 ; + RECT 32.83 190.585 33.03 191.315 ; + RECT 33.1 0.52 33.36 14.11 ; + RECT 33.325 190.585 33.525 191.315 ; + RECT 33.61 0.52 33.87 2.335 ; + RECT 33.825 190.585 34.025 191.315 ; + RECT 34.325 190.585 34.525 191.315 ; + RECT 34.82 190.585 35.02 191.315 ; + RECT 37.01 0.52 37.27 5.16 ; + RECT 36.49 4.9 37.27 5.16 ; + RECT 36.49 4.9 36.75 6.64 ; + RECT 35.64 190.585 35.84 191.315 ; + RECT 36.135 190.585 36.335 191.315 ; + RECT 36.635 190.585 36.835 191.315 ; + RECT 37.135 190.585 37.335 191.315 ; + RECT 37.63 190.585 37.83 191.315 ; + RECT 38.375 0.17 39.145 0.94 ; + RECT 38.375 0.17 38.635 12.9 ; + RECT 38.885 0.17 39.145 12.9 ; + RECT 37.865 0.52 38.125 5.815 ; + RECT 38.45 190.585 38.65 191.315 ; + RECT 39.395 0.17 40.165 0.43 ; + RECT 39.395 0.17 39.655 11.5 ; + RECT 39.905 0.17 40.165 11.5 ; + RECT 38.945 190.585 39.145 191.315 ; + RECT 39.445 190.585 39.645 191.315 ; + RECT 39.945 190.585 40.145 191.315 ; + RECT 41.435 0.17 42.205 0.43 ; + RECT 41.435 0.17 41.695 10.48 ; + RECT 41.945 0.17 42.205 10.99 ; + RECT 40.44 190.585 40.64 191.315 ; + RECT 41.26 190.585 41.46 191.315 ; + RECT 42.455 0.17 43.225 0.94 ; + RECT 42.455 0.17 42.715 8.7 ; + RECT 42.965 0.17 43.225 12.9 ; + RECT 41.755 190.585 41.955 191.315 ; + RECT 42.255 190.585 42.455 191.315 ; + RECT 42.755 190.585 42.955 191.315 ; + RECT 43.25 190.585 43.45 191.315 ; + RECT 43.475 0.52 43.735 2.485 ; + RECT 44.07 190.585 44.27 191.315 ; + RECT 44.34 0.52 44.6 14.11 ; + RECT 44.565 190.585 44.765 191.315 ; + RECT 44.85 0.52 45.11 2.335 ; + RECT 45.065 190.585 45.265 191.315 ; + RECT 45.565 190.585 45.765 191.315 ; + RECT 46.06 190.585 46.26 191.315 ; + RECT 48.25 0.52 48.51 5.16 ; + RECT 47.73 4.9 48.51 5.16 ; + RECT 47.73 4.9 47.99 6.64 ; + RECT 46.88 190.585 47.08 191.315 ; + RECT 47.375 190.585 47.575 191.315 ; + RECT 47.875 190.585 48.075 191.315 ; + RECT 48.375 190.585 48.575 191.315 ; + RECT 48.87 190.585 49.07 191.315 ; + RECT 49.615 0.17 50.385 0.94 ; + RECT 49.615 0.17 49.875 12.9 ; + RECT 50.125 0.17 50.385 12.9 ; + RECT 49.105 0.52 49.365 5.815 ; + RECT 49.69 190.585 49.89 191.315 ; + RECT 50.635 0.17 51.405 0.43 ; + RECT 50.635 0.17 50.895 11.5 ; + RECT 51.145 0.17 51.405 11.5 ; + RECT 50.185 190.585 50.385 191.315 ; + RECT 50.685 190.585 50.885 191.315 ; + RECT 51.185 190.585 51.385 191.315 ; + RECT 52.675 0.17 53.445 0.43 ; + RECT 52.675 0.17 52.935 10.48 ; + RECT 53.185 0.17 53.445 10.99 ; + RECT 51.68 190.585 51.88 191.315 ; + RECT 52.5 190.585 52.7 191.315 ; + RECT 53.695 0.17 54.465 0.94 ; + RECT 53.695 0.17 53.955 8.7 ; + RECT 54.205 0.17 54.465 12.9 ; + RECT 52.995 190.585 53.195 191.315 ; + RECT 53.495 190.585 53.695 191.315 ; + RECT 53.995 190.585 54.195 191.315 ; + RECT 54.49 190.585 54.69 191.315 ; + RECT 54.715 0.52 54.975 2.485 ; + RECT 55.31 190.585 55.51 191.315 ; + RECT 55.58 0.52 55.84 14.11 ; + RECT 55.805 190.585 56.005 191.315 ; + RECT 56.09 0.52 56.35 2.335 ; + RECT 56.305 190.585 56.505 191.315 ; + RECT 56.805 190.585 57.005 191.315 ; + RECT 57.3 190.585 57.5 191.315 ; + RECT 59.49 0.52 59.75 5.16 ; + RECT 58.97 4.9 59.75 5.16 ; + RECT 58.97 4.9 59.23 6.64 ; + RECT 58.12 190.585 58.32 191.315 ; + RECT 58.615 190.585 58.815 191.315 ; + RECT 59.115 190.585 59.315 191.315 ; + RECT 59.615 190.585 59.815 191.315 ; + RECT 60.11 190.585 60.31 191.315 ; + RECT 60.855 0.17 61.625 0.94 ; + RECT 60.855 0.17 61.115 12.9 ; + RECT 61.365 0.17 61.625 12.9 ; + RECT 60.345 0.52 60.605 5.815 ; + RECT 60.93 190.585 61.13 191.315 ; + RECT 61.875 0.17 62.645 0.43 ; + RECT 61.875 0.17 62.135 11.5 ; + RECT 62.385 0.17 62.645 11.5 ; + RECT 61.425 190.585 61.625 191.315 ; + RECT 61.925 190.585 62.125 191.315 ; + RECT 62.425 190.585 62.625 191.315 ; + RECT 63.915 0.17 64.685 0.43 ; + RECT 63.915 0.17 64.175 10.48 ; + RECT 64.425 0.17 64.685 10.99 ; + RECT 62.92 190.585 63.12 191.315 ; + RECT 63.74 190.585 63.94 191.315 ; + RECT 64.935 0.17 65.705 0.94 ; + RECT 64.935 0.17 65.195 8.7 ; + RECT 65.445 0.17 65.705 12.9 ; + RECT 64.235 190.585 64.435 191.315 ; + RECT 64.735 190.585 64.935 191.315 ; + RECT 65.235 190.585 65.435 191.315 ; + RECT 65.73 190.585 65.93 191.315 ; + RECT 65.955 0.52 66.215 2.485 ; + RECT 66.55 190.585 66.75 191.315 ; + RECT 66.82 0.52 67.08 14.11 ; + RECT 67.045 190.585 67.245 191.315 ; + RECT 67.33 0.52 67.59 2.335 ; + RECT 67.545 190.585 67.745 191.315 ; + RECT 68.045 190.585 68.245 191.315 ; + RECT 68.54 190.585 68.74 191.315 ; + RECT 70.73 0.52 70.99 5.16 ; + RECT 70.21 4.9 70.99 5.16 ; + RECT 70.21 4.9 70.47 6.64 ; + RECT 69.36 190.585 69.56 191.315 ; + RECT 69.855 190.585 70.055 191.315 ; + RECT 70.355 190.585 70.555 191.315 ; + RECT 70.855 190.585 71.055 191.315 ; + RECT 71.35 190.585 71.55 191.315 ; + RECT 72.095 0.17 72.865 0.94 ; + RECT 72.095 0.17 72.355 12.9 ; + RECT 72.605 0.17 72.865 12.9 ; + RECT 71.585 0.52 71.845 5.815 ; + RECT 72.17 190.585 72.37 191.315 ; + RECT 73.115 0.17 73.885 0.43 ; + RECT 73.115 0.17 73.375 11.5 ; + RECT 73.625 0.17 73.885 11.5 ; + RECT 72.665 190.585 72.865 191.315 ; + RECT 73.165 190.585 73.365 191.315 ; + RECT 73.665 190.585 73.865 191.315 ; + RECT 75.155 0.17 75.925 0.43 ; + RECT 75.155 0.17 75.415 10.48 ; + RECT 75.665 0.17 75.925 10.99 ; + RECT 74.16 190.585 74.36 191.315 ; + RECT 74.98 190.585 75.18 191.315 ; + RECT 76.175 0.17 76.945 0.94 ; + RECT 76.175 0.17 76.435 8.7 ; + RECT 76.685 0.17 76.945 12.9 ; + RECT 75.475 190.585 75.675 191.315 ; + RECT 75.975 190.585 76.175 191.315 ; + RECT 76.475 190.585 76.675 191.315 ; + RECT 76.97 190.585 77.17 191.315 ; + RECT 77.195 0.52 77.455 2.485 ; + RECT 77.79 190.585 77.99 191.315 ; + RECT 78.06 0.52 78.32 14.11 ; + RECT 78.285 190.585 78.485 191.315 ; + RECT 78.57 0.52 78.83 2.335 ; + RECT 78.785 190.585 78.985 191.315 ; + RECT 79.285 190.585 79.485 191.315 ; + RECT 79.78 190.585 79.98 191.315 ; + RECT 81.97 0.52 82.23 5.16 ; + RECT 81.45 4.9 82.23 5.16 ; + RECT 81.45 4.9 81.71 6.64 ; + RECT 80.6 190.585 80.8 191.315 ; + RECT 81.095 190.585 81.295 191.315 ; + RECT 81.595 190.585 81.795 191.315 ; + RECT 82.095 190.585 82.295 191.315 ; + RECT 82.59 190.585 82.79 191.315 ; + RECT 83.335 0.17 84.105 0.94 ; + RECT 83.335 0.17 83.595 12.9 ; + RECT 83.845 0.17 84.105 12.9 ; + RECT 82.825 0.52 83.085 5.815 ; + RECT 83.41 190.585 83.61 191.315 ; + RECT 84.355 0.17 85.125 0.43 ; + RECT 84.355 0.17 84.615 11.5 ; + RECT 84.865 0.17 85.125 11.5 ; + RECT 83.905 190.585 84.105 191.315 ; + RECT 84.405 190.585 84.605 191.315 ; + RECT 84.905 190.585 85.105 191.315 ; + RECT 86.395 0.17 87.165 0.43 ; + RECT 86.395 0.17 86.655 10.48 ; + RECT 86.905 0.17 87.165 10.99 ; + RECT 85.4 190.585 85.6 191.315 ; + RECT 86.22 190.585 86.42 191.315 ; + RECT 87.415 0.17 88.185 0.94 ; + RECT 87.415 0.17 87.675 8.7 ; + RECT 87.925 0.17 88.185 12.9 ; + RECT 86.715 190.585 86.915 191.315 ; + RECT 87.215 190.585 87.415 191.315 ; + RECT 87.715 190.585 87.915 191.315 ; + RECT 88.21 190.585 88.41 191.315 ; + RECT 88.435 0.52 88.695 2.485 ; + RECT 89.03 190.585 89.23 191.315 ; + RECT 89.3 0.52 89.56 14.11 ; + RECT 89.525 190.585 89.725 191.315 ; + RECT 89.81 0.52 90.07 2.335 ; + RECT 90.025 190.585 90.225 191.315 ; + RECT 90.525 190.585 90.725 191.315 ; + RECT 91.02 190.585 91.22 191.315 ; + RECT 93.21 0.52 93.47 5.16 ; + RECT 92.69 4.9 93.47 5.16 ; + RECT 92.69 4.9 92.95 6.64 ; + RECT 91.84 190.585 92.04 191.315 ; + RECT 92.335 190.585 92.535 191.315 ; + RECT 92.835 190.585 93.035 191.315 ; + RECT 93.335 190.585 93.535 191.315 ; + RECT 93.83 190.585 94.03 191.315 ; + RECT 94.575 0.17 95.345 0.94 ; + RECT 94.575 0.17 94.835 12.9 ; + RECT 95.085 0.17 95.345 12.9 ; + RECT 94.065 0.52 94.325 5.815 ; + RECT 94.65 190.585 94.85 191.315 ; + RECT 95.595 0.17 96.365 0.43 ; + RECT 95.595 0.17 95.855 11.5 ; + RECT 96.105 0.17 96.365 11.5 ; + RECT 95.145 190.585 95.345 191.315 ; + RECT 95.645 190.585 95.845 191.315 ; + RECT 96.145 190.585 96.345 191.315 ; + RECT 97.635 0.17 98.405 0.43 ; + RECT 97.635 0.17 97.895 10.48 ; + RECT 98.145 0.17 98.405 10.99 ; + RECT 96.64 190.585 96.84 191.315 ; + RECT 97.46 190.585 97.66 191.315 ; + RECT 98.655 0.17 99.425 0.94 ; + RECT 98.655 0.17 98.915 8.7 ; + RECT 99.165 0.17 99.425 12.9 ; + RECT 97.955 190.585 98.155 191.315 ; + RECT 98.455 190.585 98.655 191.315 ; + RECT 98.955 190.585 99.155 191.315 ; + RECT 99.45 190.585 99.65 191.315 ; + RECT 99.675 0.52 99.935 2.485 ; + RECT 100.27 190.585 100.47 191.315 ; + RECT 100.54 0.52 100.8 14.11 ; + RECT 100.765 190.585 100.965 191.315 ; + RECT 101.05 0.52 101.31 2.335 ; + RECT 101.265 190.585 101.465 191.315 ; + RECT 101.765 190.585 101.965 191.315 ; + RECT 102.26 190.585 102.46 191.315 ; + RECT 104.45 0.52 104.71 5.16 ; + RECT 103.93 4.9 104.71 5.16 ; + RECT 103.93 4.9 104.19 6.64 ; + RECT 103.08 190.585 103.28 191.315 ; + RECT 103.575 190.585 103.775 191.315 ; + RECT 104.075 190.585 104.275 191.315 ; + RECT 104.575 190.585 104.775 191.315 ; + RECT 105.07 190.585 105.27 191.315 ; + RECT 105.815 0.17 106.585 0.94 ; + RECT 105.815 0.17 106.075 12.9 ; + RECT 106.325 0.17 106.585 12.9 ; + RECT 105.305 0.52 105.565 5.815 ; + RECT 105.89 190.585 106.09 191.315 ; + RECT 106.835 0.17 107.605 0.43 ; + RECT 106.835 0.17 107.095 11.5 ; + RECT 107.345 0.17 107.605 11.5 ; + RECT 106.385 190.585 106.585 191.315 ; + RECT 106.885 190.585 107.085 191.315 ; + RECT 107.385 190.585 107.585 191.315 ; + RECT 108.875 0.17 109.645 0.43 ; + RECT 108.875 0.17 109.135 10.48 ; + RECT 109.385 0.17 109.645 10.99 ; + RECT 107.88 190.585 108.08 191.315 ; + RECT 108.7 190.585 108.9 191.315 ; + RECT 109.895 0.17 110.665 0.94 ; + RECT 109.895 0.17 110.155 8.7 ; + RECT 110.405 0.17 110.665 12.9 ; + RECT 109.195 190.585 109.395 191.315 ; + RECT 109.695 190.585 109.895 191.315 ; + RECT 110.195 190.585 110.395 191.315 ; + RECT 110.69 190.585 110.89 191.315 ; + RECT 110.915 0.52 111.175 2.485 ; + RECT 111.51 190.585 111.71 191.315 ; + RECT 111.78 0.52 112.04 14.11 ; + RECT 112.005 190.585 112.205 191.315 ; + RECT 112.29 0.52 112.55 2.335 ; + RECT 112.505 190.585 112.705 191.315 ; + RECT 113.005 190.585 113.205 191.315 ; + RECT 113.5 190.585 113.7 191.315 ; + RECT 115.69 0.52 115.95 5.16 ; + RECT 115.17 4.9 115.95 5.16 ; + RECT 115.17 4.9 115.43 6.64 ; + RECT 114.32 190.585 114.52 191.315 ; + RECT 114.815 190.585 115.015 191.315 ; + RECT 115.315 190.585 115.515 191.315 ; + RECT 115.815 190.585 116.015 191.315 ; + RECT 116.31 190.585 116.51 191.315 ; + RECT 117.055 0.17 117.825 0.94 ; + RECT 117.055 0.17 117.315 12.9 ; + RECT 117.565 0.17 117.825 12.9 ; + RECT 116.545 0.52 116.805 5.815 ; + RECT 117.13 190.585 117.33 191.315 ; + RECT 118.075 0.17 118.845 0.43 ; + RECT 118.075 0.17 118.335 11.5 ; + RECT 118.585 0.17 118.845 11.5 ; + RECT 117.625 190.585 117.825 191.315 ; + RECT 118.125 190.585 118.325 191.315 ; + RECT 118.625 190.585 118.825 191.315 ; + RECT 120.115 0.17 120.885 0.43 ; + RECT 120.115 0.17 120.375 10.48 ; + RECT 120.625 0.17 120.885 10.99 ; + RECT 119.12 190.585 119.32 191.315 ; + RECT 119.94 190.585 120.14 191.315 ; + RECT 121.135 0.17 121.905 0.94 ; + RECT 121.135 0.17 121.395 8.7 ; + RECT 121.645 0.17 121.905 12.9 ; + RECT 120.435 190.585 120.635 191.315 ; + RECT 120.935 190.585 121.135 191.315 ; + RECT 121.435 190.585 121.635 191.315 ; + RECT 121.93 190.585 122.13 191.315 ; + RECT 122.155 0.52 122.415 2.485 ; + RECT 122.75 190.585 122.95 191.315 ; + RECT 123.02 0.52 123.28 14.11 ; + RECT 123.245 190.585 123.445 191.315 ; + RECT 123.53 0.52 123.79 2.335 ; + RECT 123.745 190.585 123.945 191.315 ; + RECT 124.245 190.585 124.445 191.315 ; + RECT 124.74 190.585 124.94 191.315 ; + RECT 126.93 0.52 127.19 5.16 ; + RECT 126.41 4.9 127.19 5.16 ; + RECT 126.41 4.9 126.67 6.64 ; + RECT 125.56 190.585 125.76 191.315 ; + RECT 126.055 190.585 126.255 191.315 ; + RECT 126.555 190.585 126.755 191.315 ; + RECT 127.055 190.585 127.255 191.315 ; + RECT 127.55 190.585 127.75 191.315 ; + RECT 128.295 0.17 129.065 0.94 ; + RECT 128.295 0.17 128.555 12.9 ; + RECT 128.805 0.17 129.065 12.9 ; + RECT 127.785 0.52 128.045 5.815 ; + RECT 128.37 190.585 128.57 191.315 ; + RECT 129.315 0.17 130.085 0.43 ; + RECT 129.315 0.17 129.575 11.5 ; + RECT 129.825 0.17 130.085 11.5 ; + RECT 128.865 190.585 129.065 191.315 ; + RECT 129.365 190.585 129.565 191.315 ; + RECT 129.865 190.585 130.065 191.315 ; + RECT 131.355 0.17 132.125 0.43 ; + RECT 131.355 0.17 131.615 10.48 ; + RECT 131.865 0.17 132.125 10.99 ; + RECT 130.36 190.585 130.56 191.315 ; + RECT 131.18 190.585 131.38 191.315 ; + RECT 132.375 0.17 133.145 0.94 ; + RECT 132.375 0.17 132.635 8.7 ; + RECT 132.885 0.17 133.145 12.9 ; + RECT 131.675 190.585 131.875 191.315 ; + RECT 132.175 190.585 132.375 191.315 ; + RECT 132.675 190.585 132.875 191.315 ; + RECT 133.17 190.585 133.37 191.315 ; + RECT 133.395 0.52 133.655 2.485 ; + RECT 133.99 190.585 134.19 191.315 ; + RECT 134.26 0.52 134.52 14.11 ; + RECT 134.485 190.585 134.685 191.315 ; + RECT 134.77 0.52 135.03 2.335 ; + RECT 134.985 190.585 135.185 191.315 ; + RECT 135.485 190.585 135.685 191.315 ; + RECT 135.98 190.585 136.18 191.315 ; + RECT 138.17 0.52 138.43 5.16 ; + RECT 137.65 4.9 138.43 5.16 ; + RECT 137.65 4.9 137.91 6.64 ; + RECT 136.8 190.585 137 191.315 ; + RECT 137.295 190.585 137.495 191.315 ; + RECT 137.795 190.585 137.995 191.315 ; + RECT 138.295 190.585 138.495 191.315 ; + RECT 138.79 190.585 138.99 191.315 ; + RECT 139.535 0.17 140.305 0.94 ; + RECT 139.535 0.17 139.795 12.9 ; + RECT 140.045 0.17 140.305 12.9 ; + RECT 139.025 0.52 139.285 5.815 ; + RECT 139.61 190.585 139.81 191.315 ; + RECT 140.555 0.17 141.325 0.43 ; + RECT 140.555 0.17 140.815 11.5 ; + RECT 141.065 0.17 141.325 11.5 ; + RECT 140.105 190.585 140.305 191.315 ; + RECT 140.605 190.585 140.805 191.315 ; + RECT 141.105 190.585 141.305 191.315 ; + RECT 142.595 0.17 143.365 0.43 ; + RECT 142.595 0.17 142.855 10.48 ; + RECT 143.105 0.17 143.365 10.99 ; + RECT 141.6 190.585 141.8 191.315 ; + RECT 142.42 190.585 142.62 191.315 ; + RECT 143.615 0.17 144.385 0.94 ; + RECT 143.615 0.17 143.875 8.7 ; + RECT 144.125 0.17 144.385 12.9 ; + RECT 142.915 190.585 143.115 191.315 ; + RECT 143.415 190.585 143.615 191.315 ; + RECT 143.915 190.585 144.115 191.315 ; + RECT 144.41 190.585 144.61 191.315 ; + RECT 144.635 0.52 144.895 2.485 ; + RECT 145.23 190.585 145.43 191.315 ; + RECT 145.5 0.52 145.76 14.11 ; + RECT 145.725 190.585 145.925 191.315 ; + RECT 146.01 0.52 146.27 2.335 ; + RECT 146.225 190.585 146.425 191.315 ; + RECT 146.725 190.585 146.925 191.315 ; + RECT 147.22 190.585 147.42 191.315 ; + RECT 149.41 0.52 149.67 5.16 ; + RECT 148.89 4.9 149.67 5.16 ; + RECT 148.89 4.9 149.15 6.64 ; + RECT 148.04 190.585 148.24 191.315 ; + RECT 148.535 190.585 148.735 191.315 ; + RECT 149.035 190.585 149.235 191.315 ; + RECT 149.535 190.585 149.735 191.315 ; + RECT 150.03 190.585 150.23 191.315 ; + RECT 150.775 0.17 151.545 0.94 ; + RECT 150.775 0.17 151.035 12.9 ; + RECT 151.285 0.17 151.545 12.9 ; + RECT 150.265 0.52 150.525 5.815 ; + RECT 150.85 190.585 151.05 191.315 ; + RECT 151.795 0.17 152.565 0.43 ; + RECT 151.795 0.17 152.055 11.5 ; + RECT 152.305 0.17 152.565 11.5 ; + RECT 151.345 190.585 151.545 191.315 ; + RECT 151.845 190.585 152.045 191.315 ; + RECT 152.345 190.585 152.545 191.315 ; + RECT 153.835 0.17 154.605 0.43 ; + RECT 153.835 0.17 154.095 10.48 ; + RECT 154.345 0.17 154.605 10.99 ; + RECT 152.84 190.585 153.04 191.315 ; + RECT 153.66 190.585 153.86 191.315 ; + RECT 154.855 0.17 155.625 0.94 ; + RECT 154.855 0.17 155.115 8.7 ; + RECT 155.365 0.17 155.625 12.9 ; + RECT 154.155 190.585 154.355 191.315 ; + RECT 154.655 190.585 154.855 191.315 ; + RECT 155.155 190.585 155.355 191.315 ; + RECT 155.65 190.585 155.85 191.315 ; + RECT 155.875 0.52 156.135 2.485 ; + RECT 156.47 190.585 156.67 191.315 ; + RECT 156.74 0.52 157 14.11 ; + RECT 156.965 190.585 157.165 191.315 ; + RECT 157.25 0.52 157.51 2.335 ; + RECT 157.465 190.585 157.665 191.315 ; + RECT 157.965 190.585 158.165 191.315 ; + RECT 158.46 190.585 158.66 191.315 ; + RECT 160.65 0.52 160.91 5.16 ; + RECT 160.13 4.9 160.91 5.16 ; + RECT 160.13 4.9 160.39 6.64 ; + RECT 159.28 190.585 159.48 191.315 ; + RECT 159.775 190.585 159.975 191.315 ; + RECT 160.275 190.585 160.475 191.315 ; + RECT 160.775 190.585 160.975 191.315 ; + RECT 161.27 190.585 161.47 191.315 ; + RECT 162.015 0.17 162.785 0.94 ; + RECT 162.015 0.17 162.275 12.9 ; + RECT 162.525 0.17 162.785 12.9 ; + RECT 161.505 0.52 161.765 5.815 ; + RECT 162.09 190.585 162.29 191.315 ; + RECT 163.035 0.17 163.805 0.43 ; + RECT 163.035 0.17 163.295 11.5 ; + RECT 163.545 0.17 163.805 11.5 ; + RECT 162.585 190.585 162.785 191.315 ; + RECT 163.085 190.585 163.285 191.315 ; + RECT 163.585 190.585 163.785 191.315 ; + RECT 165.075 0.17 165.845 0.43 ; + RECT 165.075 0.17 165.335 10.48 ; + RECT 165.585 0.17 165.845 10.99 ; + RECT 164.08 190.585 164.28 191.315 ; + RECT 164.9 190.585 165.1 191.315 ; + RECT 166.095 0.17 166.865 0.94 ; + RECT 166.095 0.17 166.355 8.7 ; + RECT 166.605 0.17 166.865 12.9 ; + RECT 165.395 190.585 165.595 191.315 ; + RECT 165.895 190.585 166.095 191.315 ; + RECT 166.395 190.585 166.595 191.315 ; + RECT 166.89 190.585 167.09 191.315 ; + RECT 167.115 0.52 167.375 2.485 ; + RECT 167.71 190.585 167.91 191.315 ; + RECT 167.98 0.52 168.24 14.11 ; + RECT 168.205 190.585 168.405 191.315 ; + RECT 168.49 0.52 168.75 2.335 ; + RECT 168.705 190.585 168.905 191.315 ; + RECT 169.205 190.585 169.405 191.315 ; + RECT 169.7 190.585 169.9 191.315 ; + RECT 171.89 0.52 172.15 5.16 ; + RECT 171.37 4.9 172.15 5.16 ; + RECT 171.37 4.9 171.63 6.64 ; + RECT 170.52 190.585 170.72 191.315 ; + RECT 171.015 190.585 171.215 191.315 ; + RECT 171.515 190.585 171.715 191.315 ; + RECT 172.015 190.585 172.215 191.315 ; + RECT 172.51 190.585 172.71 191.315 ; + RECT 173.255 0.17 174.025 0.94 ; + RECT 173.255 0.17 173.515 12.9 ; + RECT 173.765 0.17 174.025 12.9 ; + RECT 172.745 0.52 173.005 5.815 ; + RECT 173.33 190.585 173.53 191.315 ; + RECT 174.275 0.17 175.045 0.43 ; + RECT 174.275 0.17 174.535 11.5 ; + RECT 174.785 0.17 175.045 11.5 ; + RECT 173.825 190.585 174.025 191.315 ; + RECT 174.325 190.585 174.525 191.315 ; + RECT 174.825 190.585 175.025 191.315 ; + RECT 176.315 0.17 177.085 0.43 ; + RECT 176.315 0.17 176.575 10.48 ; + RECT 176.825 0.17 177.085 10.99 ; + RECT 175.32 190.585 175.52 191.315 ; + RECT 176.14 190.585 176.34 191.315 ; + RECT 177.335 0.17 178.105 0.94 ; + RECT 177.335 0.17 177.595 8.7 ; + RECT 177.845 0.17 178.105 12.9 ; + RECT 176.635 190.585 176.835 191.315 ; + RECT 177.135 190.585 177.335 191.315 ; + RECT 177.635 190.585 177.835 191.315 ; + RECT 178.13 190.585 178.33 191.315 ; + RECT 178.355 0.52 178.615 2.485 ; + RECT 178.95 190.585 179.15 191.315 ; + RECT 179.22 0.52 179.48 14.11 ; + RECT 179.445 190.585 179.645 191.315 ; + RECT 179.73 0.52 179.99 2.335 ; + RECT 179.945 190.585 180.145 191.315 ; + RECT 180.445 190.585 180.645 191.315 ; + RECT 182.435 0.17 183.205 0.43 ; + RECT 182.435 0.17 182.695 8.7 ; + RECT 182.945 0.17 183.205 8.7 ; + RECT 183.455 0.17 184.225 0.94 ; + RECT 183.455 0.17 183.715 8.7 ; + RECT 183.965 0.17 184.225 8.7 ; + RECT 184.475 0.17 185.245 0.43 ; + RECT 184.475 0.17 184.735 8.7 ; + RECT 184.985 0.17 185.245 8.7 ; + RECT 185.495 0.17 186.265 0.94 ; + RECT 185.495 0.17 185.755 8.7 ; + RECT 186.005 0.17 186.265 8.7 ; + RECT 186.515 0.17 187.285 0.43 ; + RECT 186.515 0.17 186.775 8.7 ; + RECT 187.025 0.17 187.285 8.7 ; + RECT 187.535 0.17 188.305 0.94 ; + RECT 187.535 0.17 187.795 8.7 ; + RECT 188.045 0.17 188.305 8.7 ; + RECT 180.94 190.585 181.14 191.315 ; + RECT 181.76 190.585 181.96 191.315 ; + RECT 182.755 190.585 182.955 191.315 ; + RECT 190.24 0.17 191.01 0.94 ; + RECT 190.24 0.17 190.5 8.7 ; + RECT 190.75 0.17 191.01 8.7 ; + RECT 188.71 0.3 188.97 8.7 ; + RECT 189.22 0 189.48 8.7 ; + RECT 189.73 0 189.99 8.7 ; + RECT 191.26 0 191.52 8.7 ; + RECT 191.77 0 192.03 8.7 ; + RECT 192.28 0.52 192.54 8.7 ; + RECT 192.79 0.52 193.05 8.7 ; + RECT 193.3 0.52 193.56 8.7 ; + RECT 195.34 0.17 196.11 0.94 ; + RECT 195.34 0.17 195.6 8.7 ; + RECT 195.85 0.17 196.11 8.7 ; + RECT 196.36 0.17 197.13 0.43 ; + RECT 196.36 0.17 196.62 8.7 ; + RECT 196.87 0.17 197.13 8.7 ; + RECT 193.81 0.52 194.07 8.7 ; + RECT 194.32 0 194.58 8.7 ; + RECT 194.83 0 195.09 8.7 ; + RECT 197.38 0.3 197.64 8.7 ; + RECT 197.89 0.3 198.15 8.7 ; + RECT 199.93 0.17 200.7 0.94 ; + RECT 199.93 0.17 200.19 8.7 ; + RECT 200.44 0.17 200.7 8.7 ; + RECT 198.4 0.3 198.66 8.7 ; + RECT 198.91 0.3 199.17 8.7 ; + RECT 199.42 0.3 199.68 8.7 ; + RECT 200.95 0.52 201.21 8.7 ; + RECT 201.46 0.52 201.72 8.7 ; + RECT 201.97 0.3 202.23 8.7 ; + RECT 202.48 0.52 202.74 8.7 ; + RECT 202.99 0.52 203.25 8.7 ; + RECT 203.5 0.3 203.76 8.7 ; + RECT 204.01 0.52 204.27 8.7 ; + RECT 204.52 0.52 204.78 8.7 ; + RECT 205.03 0.52 205.29 8.7 ; + RECT 205.54 0.52 205.8 8.7 ; + RECT 206.05 0.52 206.31 8.7 ; + RECT 206.56 0.3 206.82 8.7 ; + RECT 207.07 0.52 207.33 8.7 ; + RECT 207.58 0.52 207.84 8.7 ; + RECT 208.09 0.3 208.35 8.7 ; + RECT 210.13 0.17 210.9 0.94 ; + RECT 210.13 0.17 210.39 8.7 ; + RECT 210.64 0.17 210.9 8.7 ; + RECT 208.6 0.52 208.86 8.7 ; + RECT 209.11 0.52 209.37 8.7 ; + RECT 209.62 0.3 209.88 8.7 ; + RECT 211.15 0.52 211.41 8.7 ; + RECT 211.66 0.52 211.92 8.7 ; + RECT 212.17 0.52 212.43 8.7 ; + RECT 212.68 0.52 212.94 8.7 ; + RECT 213.19 0.52 213.45 8.7 ; + RECT 213.7 0.52 213.96 8.7 ; + RECT 214.21 0.52 214.47 8.7 ; + RECT 216.25 0.17 217.02 0.94 ; + RECT 216.25 0.17 216.51 8.7 ; + RECT 216.76 0.17 217.02 8.7 ; + RECT 214.72 0.52 214.98 8.7 ; + RECT 215.23 0 215.49 8.7 ; + RECT 215.74 0 216 8.7 ; + RECT 217.27 0 217.53 8.7 ; + RECT 219.31 0.17 220.08 0.43 ; + RECT 219.31 0.17 219.57 8.7 ; + RECT 219.82 0.17 220.08 8.7 ; + RECT 217.78 0 218.04 8.7 ; + RECT 218.29 0.3 218.55 8.7 ; + RECT 218.8 0.3 219.06 8.7 ; + RECT 220.33 0.3 220.59 8.7 ; + RECT 220.84 0.3 221.1 8.7 ; + RECT 221.35 0.3 221.61 8.7 ; + RECT 221.86 0.3 222.12 8.7 ; + RECT 222.37 0.52 222.63 8.7 ; + RECT 222.88 0.52 223.14 8.7 ; + RECT 224.92 0.17 225.69 0.43 ; + RECT 224.92 0.17 225.18 8.7 ; + RECT 225.43 0.17 225.69 8.7 ; + RECT 225.94 0.17 226.71 0.94 ; + RECT 225.94 0.17 226.2 25.5 ; + RECT 226.45 0.17 226.71 33.9 ; + RECT 226.96 0.17 227.73 0.43 ; + RECT 226.96 0.17 227.22 8.7 ; + RECT 227.47 0.17 227.73 8.7 ; + RECT 228.335 0.17 229.105 0.94 ; + RECT 228.335 0.17 228.595 8.7 ; + RECT 228.845 0.17 229.105 8.7 ; + RECT 229.355 0.17 230.125 0.43 ; + RECT 229.355 0.17 229.615 8.7 ; + RECT 229.865 0.17 230.125 8.7 ; + RECT 230.375 0.17 231.145 0.94 ; + RECT 230.375 0.17 230.635 8.7 ; + RECT 230.885 0.17 231.145 8.7 ; + RECT 231.395 0.17 232.165 0.43 ; + RECT 231.395 0.17 231.655 8.7 ; + RECT 231.905 0.17 232.165 8.7 ; + RECT 232.415 0.17 233.185 0.94 ; + RECT 232.415 0.17 232.675 8.7 ; + RECT 232.925 0.17 233.185 8.7 ; + RECT 223.39 0.3 223.65 8.7 ; + RECT 233.435 0.17 234.205 0.43 ; + RECT 233.435 0.17 233.695 8.7 ; + RECT 233.945 0.17 234.205 8.7 ; + RECT 223.9 0.3 224.16 8.7 ; + RECT 224.41 0.52 224.67 8.7 ; + RECT 233.685 190.585 233.885 191.315 ; + RECT 234.68 190.585 234.88 191.315 ; + RECT 235.5 190.585 235.7 191.315 ; + RECT 235.995 190.585 236.195 191.315 ; + RECT 236.495 190.585 236.695 191.315 ; + RECT 236.65 0.52 236.91 2.335 ; + RECT 236.995 190.585 237.195 191.315 ; + RECT 237.16 0.52 237.42 14.11 ; + RECT 237.49 190.585 237.69 191.315 ; + RECT 238.535 0.17 239.305 0.94 ; + RECT 239.045 0.17 239.305 8.7 ; + RECT 238.535 0.17 238.795 12.9 ; + RECT 238.025 0.52 238.285 2.485 ; + RECT 238.31 190.585 238.51 191.315 ; + RECT 239.555 0.17 240.325 0.43 ; + RECT 240.065 0.17 240.325 10.48 ; + RECT 239.555 0.17 239.815 10.99 ; + RECT 238.805 190.585 239.005 191.315 ; + RECT 239.305 190.585 239.505 191.315 ; + RECT 239.805 190.585 240.005 191.315 ; + RECT 240.3 190.585 240.5 191.315 ; + RECT 241.595 0.17 242.365 0.43 ; + RECT 241.595 0.17 241.855 11.5 ; + RECT 242.105 0.17 242.365 11.5 ; + RECT 241.12 190.585 241.32 191.315 ; + RECT 241.615 190.585 241.815 191.315 ; + RECT 242.615 0.17 243.385 0.94 ; + RECT 242.615 0.17 242.875 12.9 ; + RECT 243.125 0.17 243.385 12.9 ; + RECT 242.115 190.585 242.315 191.315 ; + RECT 242.615 190.585 242.815 191.315 ; + RECT 243.11 190.585 243.31 191.315 ; + RECT 243.635 0.52 243.895 5.815 ; + RECT 244.49 0.52 244.75 5.16 ; + RECT 244.49 4.9 245.27 5.16 ; + RECT 245.01 4.9 245.27 6.64 ; + RECT 243.93 190.585 244.13 191.315 ; + RECT 244.425 190.585 244.625 191.315 ; + RECT 244.925 190.585 245.125 191.315 ; + RECT 245.425 190.585 245.625 191.315 ; + RECT 245.92 190.585 246.12 191.315 ; + RECT 246.74 190.585 246.94 191.315 ; + RECT 247.235 190.585 247.435 191.315 ; + RECT 247.735 190.585 247.935 191.315 ; + RECT 247.89 0.52 248.15 2.335 ; + RECT 248.235 190.585 248.435 191.315 ; + RECT 248.4 0.52 248.66 14.11 ; + RECT 248.73 190.585 248.93 191.315 ; + RECT 249.775 0.17 250.545 0.94 ; + RECT 250.285 0.17 250.545 8.7 ; + RECT 249.775 0.17 250.035 12.9 ; + RECT 249.265 0.52 249.525 2.485 ; + RECT 249.55 190.585 249.75 191.315 ; + RECT 250.795 0.17 251.565 0.43 ; + RECT 251.305 0.17 251.565 10.48 ; + RECT 250.795 0.17 251.055 10.99 ; + RECT 250.045 190.585 250.245 191.315 ; + RECT 250.545 190.585 250.745 191.315 ; + RECT 251.045 190.585 251.245 191.315 ; + RECT 251.54 190.585 251.74 191.315 ; + RECT 252.835 0.17 253.605 0.43 ; + RECT 252.835 0.17 253.095 11.5 ; + RECT 253.345 0.17 253.605 11.5 ; + RECT 252.36 190.585 252.56 191.315 ; + RECT 252.855 190.585 253.055 191.315 ; + RECT 253.855 0.17 254.625 0.94 ; + RECT 253.855 0.17 254.115 12.9 ; + RECT 254.365 0.17 254.625 12.9 ; + RECT 253.355 190.585 253.555 191.315 ; + RECT 253.855 190.585 254.055 191.315 ; + RECT 254.35 190.585 254.55 191.315 ; + RECT 254.875 0.52 255.135 5.815 ; + RECT 255.73 0.52 255.99 5.16 ; + RECT 255.73 4.9 256.51 5.16 ; + RECT 256.25 4.9 256.51 6.64 ; + RECT 255.17 190.585 255.37 191.315 ; + RECT 255.665 190.585 255.865 191.315 ; + RECT 256.165 190.585 256.365 191.315 ; + RECT 256.665 190.585 256.865 191.315 ; + RECT 257.16 190.585 257.36 191.315 ; + RECT 257.98 190.585 258.18 191.315 ; + RECT 258.475 190.585 258.675 191.315 ; + RECT 258.975 190.585 259.175 191.315 ; + RECT 259.13 0.52 259.39 2.335 ; + RECT 259.475 190.585 259.675 191.315 ; + RECT 259.64 0.52 259.9 14.11 ; + RECT 259.97 190.585 260.17 191.315 ; + RECT 261.015 0.17 261.785 0.94 ; + RECT 261.525 0.17 261.785 8.7 ; + RECT 261.015 0.17 261.275 12.9 ; + RECT 260.505 0.52 260.765 2.485 ; + RECT 260.79 190.585 260.99 191.315 ; + RECT 262.035 0.17 262.805 0.43 ; + RECT 262.545 0.17 262.805 10.48 ; + RECT 262.035 0.17 262.295 10.99 ; + RECT 261.285 190.585 261.485 191.315 ; + RECT 261.785 190.585 261.985 191.315 ; + RECT 262.285 190.585 262.485 191.315 ; + RECT 262.78 190.585 262.98 191.315 ; + RECT 264.075 0.17 264.845 0.43 ; + RECT 264.075 0.17 264.335 11.5 ; + RECT 264.585 0.17 264.845 11.5 ; + RECT 263.6 190.585 263.8 191.315 ; + RECT 264.095 190.585 264.295 191.315 ; + RECT 265.095 0.17 265.865 0.94 ; + RECT 265.095 0.17 265.355 12.9 ; + RECT 265.605 0.17 265.865 12.9 ; + RECT 264.595 190.585 264.795 191.315 ; + RECT 265.095 190.585 265.295 191.315 ; + RECT 265.59 190.585 265.79 191.315 ; + RECT 266.115 0.52 266.375 5.815 ; + RECT 266.97 0.52 267.23 5.16 ; + RECT 266.97 4.9 267.75 5.16 ; + RECT 267.49 4.9 267.75 6.64 ; + RECT 266.41 190.585 266.61 191.315 ; + RECT 266.905 190.585 267.105 191.315 ; + RECT 267.405 190.585 267.605 191.315 ; + RECT 267.905 190.585 268.105 191.315 ; + RECT 268.4 190.585 268.6 191.315 ; + RECT 269.22 190.585 269.42 191.315 ; + RECT 269.715 190.585 269.915 191.315 ; + RECT 270.215 190.585 270.415 191.315 ; + RECT 270.37 0.52 270.63 2.335 ; + RECT 270.715 190.585 270.915 191.315 ; + RECT 270.88 0.52 271.14 14.11 ; + RECT 271.21 190.585 271.41 191.315 ; + RECT 272.255 0.17 273.025 0.94 ; + RECT 272.765 0.17 273.025 8.7 ; + RECT 272.255 0.17 272.515 12.9 ; + RECT 271.745 0.52 272.005 2.485 ; + RECT 272.03 190.585 272.23 191.315 ; + RECT 273.275 0.17 274.045 0.43 ; + RECT 273.785 0.17 274.045 10.48 ; + RECT 273.275 0.17 273.535 10.99 ; + RECT 272.525 190.585 272.725 191.315 ; + RECT 273.025 190.585 273.225 191.315 ; + RECT 273.525 190.585 273.725 191.315 ; + RECT 274.02 190.585 274.22 191.315 ; + RECT 275.315 0.17 276.085 0.43 ; + RECT 275.315 0.17 275.575 11.5 ; + RECT 275.825 0.17 276.085 11.5 ; + RECT 274.84 190.585 275.04 191.315 ; + RECT 275.335 190.585 275.535 191.315 ; + RECT 276.335 0.17 277.105 0.94 ; + RECT 276.335 0.17 276.595 12.9 ; + RECT 276.845 0.17 277.105 12.9 ; + RECT 275.835 190.585 276.035 191.315 ; + RECT 276.335 190.585 276.535 191.315 ; + RECT 276.83 190.585 277.03 191.315 ; + RECT 277.355 0.52 277.615 5.815 ; + RECT 278.21 0.52 278.47 5.16 ; + RECT 278.21 4.9 278.99 5.16 ; + RECT 278.73 4.9 278.99 6.64 ; + RECT 277.65 190.585 277.85 191.315 ; + RECT 278.145 190.585 278.345 191.315 ; + RECT 278.645 190.585 278.845 191.315 ; + RECT 279.145 190.585 279.345 191.315 ; + RECT 279.64 190.585 279.84 191.315 ; + RECT 280.46 190.585 280.66 191.315 ; + RECT 280.955 190.585 281.155 191.315 ; + RECT 281.455 190.585 281.655 191.315 ; + RECT 281.61 0.52 281.87 2.335 ; + RECT 281.955 190.585 282.155 191.315 ; + RECT 282.12 0.52 282.38 14.11 ; + RECT 282.45 190.585 282.65 191.315 ; + RECT 283.495 0.17 284.265 0.94 ; + RECT 284.005 0.17 284.265 8.7 ; + RECT 283.495 0.17 283.755 12.9 ; + RECT 282.985 0.52 283.245 2.485 ; + RECT 283.27 190.585 283.47 191.315 ; + RECT 284.515 0.17 285.285 0.43 ; + RECT 285.025 0.17 285.285 10.48 ; + RECT 284.515 0.17 284.775 10.99 ; + RECT 283.765 190.585 283.965 191.315 ; + RECT 284.265 190.585 284.465 191.315 ; + RECT 284.765 190.585 284.965 191.315 ; + RECT 285.26 190.585 285.46 191.315 ; + RECT 286.555 0.17 287.325 0.43 ; + RECT 286.555 0.17 286.815 11.5 ; + RECT 287.065 0.17 287.325 11.5 ; + RECT 286.08 190.585 286.28 191.315 ; + RECT 286.575 190.585 286.775 191.315 ; + RECT 287.575 0.17 288.345 0.94 ; + RECT 287.575 0.17 287.835 12.9 ; + RECT 288.085 0.17 288.345 12.9 ; + RECT 287.075 190.585 287.275 191.315 ; + RECT 287.575 190.585 287.775 191.315 ; + RECT 288.07 190.585 288.27 191.315 ; + RECT 288.595 0.52 288.855 5.815 ; + RECT 289.45 0.52 289.71 5.16 ; + RECT 289.45 4.9 290.23 5.16 ; + RECT 289.97 4.9 290.23 6.64 ; + RECT 288.89 190.585 289.09 191.315 ; + RECT 289.385 190.585 289.585 191.315 ; + RECT 289.885 190.585 290.085 191.315 ; + RECT 290.385 190.585 290.585 191.315 ; + RECT 290.88 190.585 291.08 191.315 ; + RECT 291.7 190.585 291.9 191.315 ; + RECT 292.195 190.585 292.395 191.315 ; + RECT 292.695 190.585 292.895 191.315 ; + RECT 292.85 0.52 293.11 2.335 ; + RECT 293.195 190.585 293.395 191.315 ; + RECT 293.36 0.52 293.62 14.11 ; + RECT 293.69 190.585 293.89 191.315 ; + RECT 294.735 0.17 295.505 0.94 ; + RECT 295.245 0.17 295.505 8.7 ; + RECT 294.735 0.17 294.995 12.9 ; + RECT 294.225 0.52 294.485 2.485 ; + RECT 294.51 190.585 294.71 191.315 ; + RECT 295.755 0.17 296.525 0.43 ; + RECT 296.265 0.17 296.525 10.48 ; + RECT 295.755 0.17 296.015 10.99 ; + RECT 295.005 190.585 295.205 191.315 ; + RECT 295.505 190.585 295.705 191.315 ; + RECT 296.005 190.585 296.205 191.315 ; + RECT 296.5 190.585 296.7 191.315 ; + RECT 297.795 0.17 298.565 0.43 ; + RECT 297.795 0.17 298.055 11.5 ; + RECT 298.305 0.17 298.565 11.5 ; + RECT 297.32 190.585 297.52 191.315 ; + RECT 297.815 190.585 298.015 191.315 ; + RECT 298.815 0.17 299.585 0.94 ; + RECT 298.815 0.17 299.075 12.9 ; + RECT 299.325 0.17 299.585 12.9 ; + RECT 298.315 190.585 298.515 191.315 ; + RECT 298.815 190.585 299.015 191.315 ; + RECT 299.31 190.585 299.51 191.315 ; + RECT 299.835 0.52 300.095 5.815 ; + RECT 300.69 0.52 300.95 5.16 ; + RECT 300.69 4.9 301.47 5.16 ; + RECT 301.21 4.9 301.47 6.64 ; + RECT 300.13 190.585 300.33 191.315 ; + RECT 300.625 190.585 300.825 191.315 ; + RECT 301.125 190.585 301.325 191.315 ; + RECT 301.625 190.585 301.825 191.315 ; + RECT 302.12 190.585 302.32 191.315 ; + RECT 302.94 190.585 303.14 191.315 ; + RECT 303.435 190.585 303.635 191.315 ; + RECT 303.935 190.585 304.135 191.315 ; + RECT 304.09 0.52 304.35 2.335 ; + RECT 304.435 190.585 304.635 191.315 ; + RECT 304.6 0.52 304.86 14.11 ; + RECT 304.93 190.585 305.13 191.315 ; + RECT 305.975 0.17 306.745 0.94 ; + RECT 306.485 0.17 306.745 8.7 ; + RECT 305.975 0.17 306.235 12.9 ; + RECT 305.465 0.52 305.725 2.485 ; + RECT 305.75 190.585 305.95 191.315 ; + RECT 306.995 0.17 307.765 0.43 ; + RECT 307.505 0.17 307.765 10.48 ; + RECT 306.995 0.17 307.255 10.99 ; + RECT 306.245 190.585 306.445 191.315 ; + RECT 306.745 190.585 306.945 191.315 ; + RECT 307.245 190.585 307.445 191.315 ; + RECT 307.74 190.585 307.94 191.315 ; + RECT 309.035 0.17 309.805 0.43 ; + RECT 309.035 0.17 309.295 11.5 ; + RECT 309.545 0.17 309.805 11.5 ; + RECT 308.56 190.585 308.76 191.315 ; + RECT 309.055 190.585 309.255 191.315 ; + RECT 310.055 0.17 310.825 0.94 ; + RECT 310.055 0.17 310.315 12.9 ; + RECT 310.565 0.17 310.825 12.9 ; + RECT 309.555 190.585 309.755 191.315 ; + RECT 310.055 190.585 310.255 191.315 ; + RECT 310.55 190.585 310.75 191.315 ; + RECT 311.075 0.52 311.335 5.815 ; + RECT 311.93 0.52 312.19 5.16 ; + RECT 311.93 4.9 312.71 5.16 ; + RECT 312.45 4.9 312.71 6.64 ; + RECT 311.37 190.585 311.57 191.315 ; + RECT 311.865 190.585 312.065 191.315 ; + RECT 312.365 190.585 312.565 191.315 ; + RECT 312.865 190.585 313.065 191.315 ; + RECT 313.36 190.585 313.56 191.315 ; + RECT 314.18 190.585 314.38 191.315 ; + RECT 314.675 190.585 314.875 191.315 ; + RECT 315.175 190.585 315.375 191.315 ; + RECT 315.33 0.52 315.59 2.335 ; + RECT 315.675 190.585 315.875 191.315 ; + RECT 315.84 0.52 316.1 14.11 ; + RECT 316.17 190.585 316.37 191.315 ; + RECT 317.215 0.17 317.985 0.94 ; + RECT 317.725 0.17 317.985 8.7 ; + RECT 317.215 0.17 317.475 12.9 ; + RECT 316.705 0.52 316.965 2.485 ; + RECT 316.99 190.585 317.19 191.315 ; + RECT 318.235 0.17 319.005 0.43 ; + RECT 318.745 0.17 319.005 10.48 ; + RECT 318.235 0.17 318.495 10.99 ; + RECT 317.485 190.585 317.685 191.315 ; + RECT 317.985 190.585 318.185 191.315 ; + RECT 318.485 190.585 318.685 191.315 ; + RECT 318.98 190.585 319.18 191.315 ; + RECT 320.275 0.17 321.045 0.43 ; + RECT 320.275 0.17 320.535 11.5 ; + RECT 320.785 0.17 321.045 11.5 ; + RECT 319.8 190.585 320 191.315 ; + RECT 320.295 190.585 320.495 191.315 ; + RECT 321.295 0.17 322.065 0.94 ; + RECT 321.295 0.17 321.555 12.9 ; + RECT 321.805 0.17 322.065 12.9 ; + RECT 320.795 190.585 320.995 191.315 ; + RECT 321.295 190.585 321.495 191.315 ; + RECT 321.79 190.585 321.99 191.315 ; + RECT 322.315 0.52 322.575 5.815 ; + RECT 323.17 0.52 323.43 5.16 ; + RECT 323.17 4.9 323.95 5.16 ; + RECT 323.69 4.9 323.95 6.64 ; + RECT 322.61 190.585 322.81 191.315 ; + RECT 323.105 190.585 323.305 191.315 ; + RECT 323.605 190.585 323.805 191.315 ; + RECT 324.105 190.585 324.305 191.315 ; + RECT 324.6 190.585 324.8 191.315 ; + RECT 325.42 190.585 325.62 191.315 ; + RECT 325.915 190.585 326.115 191.315 ; + RECT 326.415 190.585 326.615 191.315 ; + RECT 326.57 0.52 326.83 2.335 ; + RECT 326.915 190.585 327.115 191.315 ; + RECT 327.08 0.52 327.34 14.11 ; + RECT 327.41 190.585 327.61 191.315 ; + RECT 328.455 0.17 329.225 0.94 ; + RECT 328.965 0.17 329.225 8.7 ; + RECT 328.455 0.17 328.715 12.9 ; + RECT 327.945 0.52 328.205 2.485 ; + RECT 328.23 190.585 328.43 191.315 ; + RECT 329.475 0.17 330.245 0.43 ; + RECT 329.985 0.17 330.245 10.48 ; + RECT 329.475 0.17 329.735 10.99 ; + RECT 328.725 190.585 328.925 191.315 ; + RECT 329.225 190.585 329.425 191.315 ; + RECT 329.725 190.585 329.925 191.315 ; + RECT 330.22 190.585 330.42 191.315 ; + RECT 331.515 0.17 332.285 0.43 ; + RECT 331.515 0.17 331.775 11.5 ; + RECT 332.025 0.17 332.285 11.5 ; + RECT 331.04 190.585 331.24 191.315 ; + RECT 331.535 190.585 331.735 191.315 ; + RECT 332.535 0.17 333.305 0.94 ; + RECT 332.535 0.17 332.795 12.9 ; + RECT 333.045 0.17 333.305 12.9 ; + RECT 332.035 190.585 332.235 191.315 ; + RECT 332.535 190.585 332.735 191.315 ; + RECT 333.03 190.585 333.23 191.315 ; + RECT 333.555 0.52 333.815 5.815 ; + RECT 334.41 0.52 334.67 5.16 ; + RECT 334.41 4.9 335.19 5.16 ; + RECT 334.93 4.9 335.19 6.64 ; + RECT 333.85 190.585 334.05 191.315 ; + RECT 334.345 190.585 334.545 191.315 ; + RECT 334.845 190.585 335.045 191.315 ; + RECT 335.345 190.585 335.545 191.315 ; + RECT 335.84 190.585 336.04 191.315 ; + RECT 336.66 190.585 336.86 191.315 ; + RECT 337.155 190.585 337.355 191.315 ; + RECT 337.655 190.585 337.855 191.315 ; + RECT 337.81 0.52 338.07 2.335 ; + RECT 338.155 190.585 338.355 191.315 ; + RECT 338.32 0.52 338.58 14.11 ; + RECT 338.65 190.585 338.85 191.315 ; + RECT 339.695 0.17 340.465 0.94 ; + RECT 340.205 0.17 340.465 8.7 ; + RECT 339.695 0.17 339.955 12.9 ; + RECT 339.185 0.52 339.445 2.485 ; + RECT 339.47 190.585 339.67 191.315 ; + RECT 340.715 0.17 341.485 0.43 ; + RECT 341.225 0.17 341.485 10.48 ; + RECT 340.715 0.17 340.975 10.99 ; + RECT 339.965 190.585 340.165 191.315 ; + RECT 340.465 190.585 340.665 191.315 ; + RECT 340.965 190.585 341.165 191.315 ; + RECT 341.46 190.585 341.66 191.315 ; + RECT 342.755 0.17 343.525 0.43 ; + RECT 342.755 0.17 343.015 11.5 ; + RECT 343.265 0.17 343.525 11.5 ; + RECT 342.28 190.585 342.48 191.315 ; + RECT 342.775 190.585 342.975 191.315 ; + RECT 343.775 0.17 344.545 0.94 ; + RECT 343.775 0.17 344.035 12.9 ; + RECT 344.285 0.17 344.545 12.9 ; + RECT 343.275 190.585 343.475 191.315 ; + RECT 343.775 190.585 343.975 191.315 ; + RECT 344.27 190.585 344.47 191.315 ; + RECT 344.795 0.52 345.055 5.815 ; + RECT 345.65 0.52 345.91 5.16 ; + RECT 345.65 4.9 346.43 5.16 ; + RECT 346.17 4.9 346.43 6.64 ; + RECT 345.09 190.585 345.29 191.315 ; + RECT 345.585 190.585 345.785 191.315 ; + RECT 346.085 190.585 346.285 191.315 ; + RECT 346.585 190.585 346.785 191.315 ; + RECT 347.08 190.585 347.28 191.315 ; + RECT 347.9 190.585 348.1 191.315 ; + RECT 348.395 190.585 348.595 191.315 ; + RECT 348.895 190.585 349.095 191.315 ; + RECT 349.05 0.52 349.31 2.335 ; + RECT 349.395 190.585 349.595 191.315 ; + RECT 349.56 0.52 349.82 14.11 ; + RECT 349.89 190.585 350.09 191.315 ; + RECT 350.935 0.17 351.705 0.94 ; + RECT 351.445 0.17 351.705 8.7 ; + RECT 350.935 0.17 351.195 12.9 ; + RECT 350.425 0.52 350.685 2.485 ; + RECT 350.71 190.585 350.91 191.315 ; + RECT 351.955 0.17 352.725 0.43 ; + RECT 352.465 0.17 352.725 10.48 ; + RECT 351.955 0.17 352.215 10.99 ; + RECT 351.205 190.585 351.405 191.315 ; + RECT 351.705 190.585 351.905 191.315 ; + RECT 352.205 190.585 352.405 191.315 ; + RECT 352.7 190.585 352.9 191.315 ; + RECT 353.995 0.17 354.765 0.43 ; + RECT 353.995 0.17 354.255 11.5 ; + RECT 354.505 0.17 354.765 11.5 ; + RECT 353.52 190.585 353.72 191.315 ; + RECT 354.015 190.585 354.215 191.315 ; + RECT 355.015 0.17 355.785 0.94 ; + RECT 355.015 0.17 355.275 12.9 ; + RECT 355.525 0.17 355.785 12.9 ; + RECT 354.515 190.585 354.715 191.315 ; + RECT 355.015 190.585 355.215 191.315 ; + RECT 355.51 190.585 355.71 191.315 ; + RECT 356.035 0.52 356.295 5.815 ; + RECT 356.89 0.52 357.15 5.16 ; + RECT 356.89 4.9 357.67 5.16 ; + RECT 357.41 4.9 357.67 6.64 ; + RECT 356.33 190.585 356.53 191.315 ; + RECT 356.825 190.585 357.025 191.315 ; + RECT 357.325 190.585 357.525 191.315 ; + RECT 357.825 190.585 358.025 191.315 ; + RECT 358.32 190.585 358.52 191.315 ; + RECT 359.14 190.585 359.34 191.315 ; + RECT 359.635 190.585 359.835 191.315 ; + RECT 360.135 190.585 360.335 191.315 ; + RECT 360.29 0.52 360.55 2.335 ; + RECT 360.635 190.585 360.835 191.315 ; + RECT 360.8 0.52 361.06 14.11 ; + RECT 361.13 190.585 361.33 191.315 ; + RECT 362.175 0.17 362.945 0.94 ; + RECT 362.685 0.17 362.945 8.7 ; + RECT 362.175 0.17 362.435 12.9 ; + RECT 361.665 0.52 361.925 2.485 ; + RECT 361.95 190.585 362.15 191.315 ; + RECT 363.195 0.17 363.965 0.43 ; + RECT 363.705 0.17 363.965 10.48 ; + RECT 363.195 0.17 363.455 10.99 ; + RECT 362.445 190.585 362.645 191.315 ; + RECT 362.945 190.585 363.145 191.315 ; + RECT 363.445 190.585 363.645 191.315 ; + RECT 363.94 190.585 364.14 191.315 ; + RECT 365.235 0.17 366.005 0.43 ; + RECT 365.235 0.17 365.495 11.5 ; + RECT 365.745 0.17 366.005 11.5 ; + RECT 364.76 190.585 364.96 191.315 ; + RECT 365.255 190.585 365.455 191.315 ; + RECT 366.255 0.17 367.025 0.94 ; + RECT 366.255 0.17 366.515 12.9 ; + RECT 366.765 0.17 367.025 12.9 ; + RECT 365.755 190.585 365.955 191.315 ; + RECT 366.255 190.585 366.455 191.315 ; + RECT 366.75 190.585 366.95 191.315 ; + RECT 367.275 0.52 367.535 5.815 ; + RECT 368.13 0.52 368.39 5.16 ; + RECT 368.13 4.9 368.91 5.16 ; + RECT 368.65 4.9 368.91 6.64 ; + RECT 367.57 190.585 367.77 191.315 ; + RECT 368.065 190.585 368.265 191.315 ; + RECT 368.565 190.585 368.765 191.315 ; + RECT 369.065 190.585 369.265 191.315 ; + RECT 369.56 190.585 369.76 191.315 ; + RECT 370.38 190.585 370.58 191.315 ; + RECT 370.875 190.585 371.075 191.315 ; + RECT 371.375 190.585 371.575 191.315 ; + RECT 371.53 0.52 371.79 2.335 ; + RECT 371.875 190.585 372.075 191.315 ; + RECT 372.04 0.52 372.3 14.11 ; + RECT 372.37 190.585 372.57 191.315 ; + RECT 373.415 0.17 374.185 0.94 ; + RECT 373.925 0.17 374.185 8.7 ; + RECT 373.415 0.17 373.675 12.9 ; + RECT 372.905 0.52 373.165 2.485 ; + RECT 373.19 190.585 373.39 191.315 ; + RECT 374.435 0.17 375.205 0.43 ; + RECT 374.945 0.17 375.205 10.48 ; + RECT 374.435 0.17 374.695 10.99 ; + RECT 373.685 190.585 373.885 191.315 ; + RECT 374.185 190.585 374.385 191.315 ; + RECT 374.685 190.585 374.885 191.315 ; + RECT 375.18 190.585 375.38 191.315 ; + RECT 376.475 0.17 377.245 0.43 ; + RECT 376.475 0.17 376.735 11.5 ; + RECT 376.985 0.17 377.245 11.5 ; + RECT 376 190.585 376.2 191.315 ; + RECT 376.495 190.585 376.695 191.315 ; + RECT 377.495 0.17 378.265 0.94 ; + RECT 377.495 0.17 377.755 12.9 ; + RECT 378.005 0.17 378.265 12.9 ; + RECT 376.995 190.585 377.195 191.315 ; + RECT 377.495 190.585 377.695 191.315 ; + RECT 377.99 190.585 378.19 191.315 ; + RECT 378.515 0.52 378.775 5.815 ; + RECT 379.37 0.52 379.63 5.16 ; + RECT 379.37 4.9 380.15 5.16 ; + RECT 379.89 4.9 380.15 6.64 ; + RECT 378.81 190.585 379.01 191.315 ; + RECT 379.305 190.585 379.505 191.315 ; + RECT 379.805 190.585 380.005 191.315 ; + RECT 380.305 190.585 380.505 191.315 ; + RECT 380.8 190.585 381 191.315 ; + RECT 381.62 190.585 381.82 191.315 ; + RECT 382.115 190.585 382.315 191.315 ; + RECT 382.615 190.585 382.815 191.315 ; + RECT 382.77 0.52 383.03 2.335 ; + RECT 383.115 190.585 383.315 191.315 ; + RECT 383.28 0.52 383.54 14.11 ; + RECT 383.61 190.585 383.81 191.315 ; + RECT 384.655 0.17 385.425 0.94 ; + RECT 385.165 0.17 385.425 8.7 ; + RECT 384.655 0.17 384.915 12.9 ; + RECT 384.145 0.52 384.405 2.485 ; + RECT 384.43 190.585 384.63 191.315 ; + RECT 385.675 0.17 386.445 0.43 ; + RECT 386.185 0.17 386.445 10.48 ; + RECT 385.675 0.17 385.935 10.99 ; + RECT 384.925 190.585 385.125 191.315 ; + RECT 385.425 190.585 385.625 191.315 ; + RECT 385.925 190.585 386.125 191.315 ; + RECT 386.42 190.585 386.62 191.315 ; + RECT 387.715 0.17 388.485 0.43 ; + RECT 387.715 0.17 387.975 11.5 ; + RECT 388.225 0.17 388.485 11.5 ; + RECT 387.24 190.585 387.44 191.315 ; + RECT 387.735 190.585 387.935 191.315 ; + RECT 388.735 0.17 389.505 0.94 ; + RECT 388.735 0.17 388.995 12.9 ; + RECT 389.245 0.17 389.505 12.9 ; + RECT 388.235 190.585 388.435 191.315 ; + RECT 388.735 190.585 388.935 191.315 ; + RECT 389.23 190.585 389.43 191.315 ; + RECT 389.755 0.52 390.015 5.815 ; + RECT 390.61 0.52 390.87 5.16 ; + RECT 390.61 4.9 391.39 5.16 ; + RECT 391.13 4.9 391.39 6.64 ; + RECT 390.05 190.585 390.25 191.315 ; + RECT 390.545 190.585 390.745 191.315 ; + RECT 391.045 190.585 391.245 191.315 ; + RECT 391.545 190.585 391.745 191.315 ; + RECT 392.04 190.585 392.24 191.315 ; + RECT 392.86 190.585 393.06 191.315 ; + RECT 393.355 190.585 393.555 191.315 ; + RECT 393.855 190.585 394.055 191.315 ; + RECT 394.01 0.52 394.27 2.335 ; + RECT 394.355 190.585 394.555 191.315 ; + RECT 394.52 0.52 394.78 14.11 ; + RECT 394.85 190.585 395.05 191.315 ; + RECT 395.895 0.17 396.665 0.94 ; + RECT 396.405 0.17 396.665 8.7 ; + RECT 395.895 0.17 396.155 12.9 ; + RECT 395.385 0.52 395.645 2.485 ; + RECT 395.67 190.585 395.87 191.315 ; + RECT 396.915 0.17 397.685 0.43 ; + RECT 397.425 0.17 397.685 10.48 ; + RECT 396.915 0.17 397.175 10.99 ; + RECT 396.165 190.585 396.365 191.315 ; + RECT 396.665 190.585 396.865 191.315 ; + RECT 397.165 190.585 397.365 191.315 ; + RECT 397.66 190.585 397.86 191.315 ; + RECT 398.955 0.17 399.725 0.43 ; + RECT 398.955 0.17 399.215 11.5 ; + RECT 399.465 0.17 399.725 11.5 ; + RECT 398.48 190.585 398.68 191.315 ; + RECT 398.975 190.585 399.175 191.315 ; + RECT 399.975 0.17 400.745 0.94 ; + RECT 399.975 0.17 400.235 12.9 ; + RECT 400.485 0.17 400.745 12.9 ; + RECT 399.475 190.585 399.675 191.315 ; + RECT 399.975 190.585 400.175 191.315 ; + RECT 400.47 190.585 400.67 191.315 ; + RECT 400.995 0.52 401.255 5.815 ; + RECT 401.85 0.52 402.11 5.16 ; + RECT 401.85 4.9 402.63 5.16 ; + RECT 402.37 4.9 402.63 6.64 ; + RECT 401.29 190.585 401.49 191.315 ; + RECT 401.785 190.585 401.985 191.315 ; + RECT 402.285 190.585 402.485 191.315 ; + RECT 402.785 190.585 402.985 191.315 ; + RECT 403.28 190.585 403.48 191.315 ; + RECT 404.1 190.585 404.3 191.315 ; + RECT 404.595 190.585 404.795 191.315 ; + RECT 405.095 190.585 405.295 191.315 ; + RECT 405.25 0.52 405.51 2.335 ; + RECT 405.595 190.585 405.795 191.315 ; + RECT 405.76 0.52 406.02 14.11 ; + RECT 406.09 190.585 406.29 191.315 ; + RECT 407.135 0.17 407.905 0.94 ; + RECT 407.645 0.17 407.905 8.7 ; + RECT 407.135 0.17 407.395 12.9 ; + RECT 406.625 0.52 406.885 2.485 ; + RECT 406.91 190.585 407.11 191.315 ; + RECT 408.155 0.17 408.925 0.43 ; + RECT 408.665 0.17 408.925 10.48 ; + RECT 408.155 0.17 408.415 10.99 ; + RECT 407.405 190.585 407.605 191.315 ; + RECT 407.905 190.585 408.105 191.315 ; + RECT 408.405 190.585 408.605 191.315 ; + RECT 408.9 190.585 409.1 191.315 ; + RECT 410.195 0.17 410.965 0.43 ; + RECT 410.195 0.17 410.455 11.5 ; + RECT 410.705 0.17 410.965 11.5 ; + RECT 409.72 190.585 409.92 191.315 ; + RECT 410.215 190.585 410.415 191.315 ; + RECT 411.215 0.17 411.985 0.94 ; + RECT 411.215 0.17 411.475 12.9 ; + RECT 411.725 0.17 411.985 12.9 ; + RECT 410.715 190.585 410.915 191.315 ; + RECT 411.215 190.585 411.415 191.315 ; + RECT 411.71 190.585 411.91 191.315 ; + RECT 412.235 0.52 412.495 5.815 ; + RECT 413.09 0.52 413.35 5.16 ; + RECT 413.09 4.9 413.87 5.16 ; + RECT 413.61 4.9 413.87 6.64 ; + RECT 412.53 190.585 412.73 191.315 ; + RECT 413.025 190.585 413.225 191.315 ; + RECT 413.525 190.585 413.725 191.315 ; + RECT 414.025 190.585 414.225 191.315 ; + RECT 414.52 190.585 414.72 191.315 ; + RECT 415.34 190.585 415.54 191.315 ; + RECT 416.335 45.465 416.535 191.315 ; + LAYER Metal2 SPACING 0.21 ; + RECT 249.785 0 254.615 191.34 ; + RECT 261.025 0 265.855 191.34 ; + RECT 272.265 0 277.095 191.34 ; + RECT 283.505 0 288.335 191.34 ; + RECT 294.745 0 299.575 191.34 ; + RECT 305.985 0 310.815 191.34 ; + RECT 317.225 0 322.055 191.34 ; + RECT 328.465 0 333.295 191.34 ; + RECT 339.705 0 344.535 191.34 ; + RECT 350.945 0 355.775 191.34 ; + RECT 362.185 0 367.015 191.34 ; + RECT 373.425 0 378.255 191.34 ; + RECT 384.665 0 389.495 191.34 ; + RECT 395.905 0 400.735 191.34 ; + RECT 407.145 0 411.975 191.34 ; + RECT 201.98 0 202.22 191.34 ; + RECT 203.51 0 203.75 191.34 ; + RECT 206.57 0 206.81 191.34 ; + RECT 208.1 0 208.34 191.34 ; + RECT 215.23 0 222.11 191.34 ; + RECT 223.4 0 224.15 191.34 ; + RECT 0 0 3.03 191.34 ; + RECT 4.655 0.17 9.505 191.34 ; + RECT 11.65 0 14.27 191.34 ; + RECT 15.895 0.17 20.745 191.34 ; + RECT 22.89 0 25.51 191.34 ; + RECT 27.135 0.17 31.985 191.34 ; + RECT 34.13 0 36.75 191.34 ; + RECT 38.375 0.17 43.225 191.34 ; + RECT 45.37 0 47.99 191.34 ; + RECT 49.615 0.17 54.465 191.34 ; + RECT 56.61 0 59.23 191.34 ; + RECT 60.855 0.17 65.705 191.34 ; + RECT 67.85 0 70.47 191.34 ; + RECT 72.095 0.17 76.945 191.34 ; + RECT 79.09 0 81.71 191.34 ; + RECT 83.335 0.17 88.185 191.34 ; + RECT 90.33 0 92.95 191.34 ; + RECT 94.575 0.17 99.425 191.34 ; + RECT 101.57 0 104.19 191.34 ; + RECT 105.815 0.17 110.665 191.34 ; + RECT 112.81 0 115.43 191.34 ; + RECT 117.055 0.17 121.905 191.34 ; + RECT 124.05 0 126.67 191.34 ; + RECT 128.295 0.17 133.145 191.34 ; + RECT 135.29 0 137.91 191.34 ; + RECT 139.535 0.17 144.385 191.34 ; + RECT 146.53 0 149.15 191.34 ; + RECT 150.775 0.17 155.625 191.34 ; + RECT 157.77 0 160.39 191.34 ; + RECT 162.015 0.17 166.865 191.34 ; + RECT 169.01 0 171.63 191.34 ; + RECT 173.255 0.17 178.105 191.34 ; + RECT 180.25 0 192.03 191.34 ; + RECT 194.32 0.17 200.7 191.34 ; + RECT 201.97 0.3 202.23 191.34 ; + RECT 203.5 0.3 203.76 191.34 ; + RECT 206.56 0.3 206.82 191.34 ; + RECT 208.09 0.3 208.35 191.34 ; + RECT 209.63 0.17 210.9 191.34 ; + RECT 209.62 0.3 210.9 191.34 ; + RECT 215.23 0.3 222.12 191.34 ; + RECT 223.39 0.3 224.16 191.34 ; + RECT 224.93 0 236.39 191.34 ; + RECT 224.92 0.17 236.39 191.34 ; + RECT 238.535 0.17 243.385 191.34 ; + RECT 245.01 0 247.63 191.34 ; + RECT 249.775 0.17 254.625 191.34 ; + RECT 256.25 0 258.87 191.34 ; + RECT 261.015 0.17 265.865 191.34 ; + RECT 267.49 0 270.11 191.34 ; + RECT 272.255 0.17 277.105 191.34 ; + RECT 278.73 0 281.35 191.34 ; + RECT 283.495 0.17 288.345 191.34 ; + RECT 289.97 0 292.59 191.34 ; + RECT 294.735 0.17 299.585 191.34 ; + RECT 301.21 0 303.83 191.34 ; + RECT 305.975 0.17 310.825 191.34 ; + RECT 312.45 0 315.07 191.34 ; + RECT 317.215 0.17 322.065 191.34 ; + RECT 323.69 0 326.31 191.34 ; + RECT 328.455 0.17 333.305 191.34 ; + RECT 334.93 0 337.55 191.34 ; + RECT 339.695 0.17 344.545 191.34 ; + RECT 346.17 0 348.79 191.34 ; + RECT 350.935 0.17 355.785 191.34 ; + RECT 357.41 0 360.03 191.34 ; + RECT 362.175 0.17 367.025 191.34 ; + RECT 368.65 0 371.27 191.34 ; + RECT 373.415 0.17 378.265 191.34 ; + RECT 379.89 0 382.51 191.34 ; + RECT 384.655 0.17 389.505 191.34 ; + RECT 391.13 0 393.75 191.34 ; + RECT 395.895 0.17 400.745 191.34 ; + RECT 402.37 0 404.99 191.34 ; + RECT 407.135 0.17 411.985 191.34 ; + RECT 413.61 0 416.64 191.34 ; + RECT 0 0.52 416.64 191.34 ; + RECT 4.665 0 9.495 191.34 ; + RECT 15.905 0 20.735 191.34 ; + RECT 27.145 0 31.975 191.34 ; + RECT 38.385 0 43.215 191.34 ; + RECT 49.625 0 54.455 191.34 ; + RECT 60.865 0 65.695 191.34 ; + RECT 72.105 0 76.935 191.34 ; + RECT 83.345 0 88.175 191.34 ; + RECT 94.585 0 99.415 191.34 ; + RECT 105.825 0 110.655 191.34 ; + RECT 117.065 0 121.895 191.34 ; + RECT 128.305 0 133.135 191.34 ; + RECT 139.545 0 144.375 191.34 ; + RECT 150.785 0 155.615 191.34 ; + RECT 162.025 0 166.855 191.34 ; + RECT 173.265 0 178.095 191.34 ; + RECT 194.32 0 200.69 191.34 ; + RECT 209.63 0 210.89 191.34 ; + RECT 238.545 0 243.375 191.34 ; + LAYER Metal3 ; + RECT 0 0 416.64 191.34 ; + LAYER Metal4 SPACING 0.21 ; + RECT 0 39.085 9.62 45.205 ; + RECT 0 0 4 191.34 ; + RECT 7.33 0 9.62 191.34 ; + RECT 12.95 39.085 20.86 45.205 ; + RECT 12.95 0 15.24 191.34 ; + RECT 18.57 0 20.86 191.34 ; + RECT 24.19 39.085 32.1 45.205 ; + RECT 24.19 0 26.48 191.34 ; + RECT 29.81 0 32.1 191.34 ; + RECT 35.43 39.085 43.34 45.205 ; + RECT 35.43 0 37.72 191.34 ; + RECT 41.05 0 43.34 191.34 ; + RECT 46.67 39.085 54.58 45.205 ; + RECT 46.67 0 48.96 191.34 ; + RECT 52.29 0 54.58 191.34 ; + RECT 57.91 39.085 65.82 45.205 ; + RECT 57.91 0 60.2 191.34 ; + RECT 63.53 0 65.82 191.34 ; + RECT 69.15 39.085 77.06 45.205 ; + RECT 69.15 0 71.44 191.34 ; + RECT 74.77 0 77.06 191.34 ; + RECT 80.39 39.085 88.3 45.205 ; + RECT 80.39 0 82.68 191.34 ; + RECT 86.01 0 88.3 191.34 ; + RECT 91.63 39.085 99.54 45.205 ; + RECT 91.63 0 93.92 191.34 ; + RECT 97.25 0 99.54 191.34 ; + RECT 102.87 39.085 110.78 45.205 ; + RECT 102.87 0 105.16 191.34 ; + RECT 108.49 0 110.78 191.34 ; + RECT 114.11 39.085 122.02 45.205 ; + RECT 114.11 0 116.4 191.34 ; + RECT 119.73 0 122.02 191.34 ; + RECT 125.35 39.085 133.26 45.205 ; + RECT 125.35 0 127.64 191.34 ; + RECT 130.97 0 133.26 191.34 ; + RECT 136.59 39.085 144.5 45.205 ; + RECT 136.59 0 138.88 191.34 ; + RECT 142.21 0 144.5 191.34 ; + RECT 147.83 39.085 155.74 45.205 ; + RECT 147.83 0 150.12 191.34 ; + RECT 153.45 0 155.74 191.34 ; + RECT 159.07 39.085 166.98 45.205 ; + RECT 159.07 0 161.36 191.34 ; + RECT 164.69 0 166.98 191.34 ; + RECT 170.31 39.085 178.22 45.205 ; + RECT 170.31 0 172.6 191.34 ; + RECT 175.93 0 178.22 191.34 ; + RECT 181.55 0 188.63 191.34 ; + RECT 191.96 0 193.78 191.34 ; + RECT 197.11 0 198.93 191.34 ; + RECT 202.26 0 204.08 191.34 ; + RECT 207.41 0 209.23 191.34 ; + RECT 212.56 0 214.38 191.34 ; + RECT 238.42 39.085 246.33 45.205 ; + RECT 238.42 0 240.71 191.34 ; + RECT 244.04 0 246.33 191.34 ; + RECT 249.66 39.085 257.57 45.205 ; + RECT 249.66 0 251.95 191.34 ; + RECT 255.28 0 257.57 191.34 ; + RECT 260.9 39.085 268.81 45.205 ; + RECT 260.9 0 263.19 191.34 ; + RECT 266.52 0 268.81 191.34 ; + RECT 272.14 39.085 280.05 45.205 ; + RECT 272.14 0 274.43 191.34 ; + RECT 277.76 0 280.05 191.34 ; + RECT 283.38 39.085 291.29 45.205 ; + RECT 283.38 0 285.67 191.34 ; + RECT 289 0 291.29 191.34 ; + RECT 294.62 39.085 302.53 45.205 ; + RECT 294.62 0 296.91 191.34 ; + RECT 300.24 0 302.53 191.34 ; + RECT 305.86 39.085 313.77 45.205 ; + RECT 305.86 0 308.15 191.34 ; + RECT 311.48 0 313.77 191.34 ; + RECT 317.1 39.085 325.01 45.205 ; + RECT 317.1 0 319.39 191.34 ; + RECT 322.72 0 325.01 191.34 ; + RECT 328.34 39.085 336.25 45.205 ; + RECT 328.34 0 330.63 191.34 ; + RECT 333.96 0 336.25 191.34 ; + RECT 339.58 39.085 347.49 45.205 ; + RECT 339.58 0 341.87 191.34 ; + RECT 345.2 0 347.49 191.34 ; + RECT 350.82 39.085 358.73 45.205 ; + RECT 350.82 0 353.11 191.34 ; + RECT 356.44 0 358.73 191.34 ; + RECT 362.06 39.085 369.97 45.205 ; + RECT 362.06 0 364.35 191.34 ; + RECT 367.68 0 369.97 191.34 ; + RECT 373.3 39.085 381.21 45.205 ; + RECT 373.3 0 375.59 191.34 ; + RECT 378.92 0 381.21 191.34 ; + RECT 384.54 39.085 392.45 45.205 ; + RECT 384.54 0 386.83 191.34 ; + RECT 390.16 0 392.45 191.34 ; + RECT 395.78 39.085 403.69 45.205 ; + RECT 395.78 0 398.07 191.34 ; + RECT 401.4 0 403.69 191.34 ; + RECT 407.02 39.085 416.64 45.205 ; + RECT 407.02 0 409.31 191.34 ; + RECT 412.64 0 416.64 191.34 ; + RECT 217.71 0 219.53 191.34 ; + RECT 222.86 0 224.68 191.34 ; + RECT 228.01 0 235.09 191.34 ; + END +END RM_IHPSG13_1P_512x32_c2_bm_bist + +END LIBRARY diff --git a/flow/platforms/ihp-sg13g2/lef/RM_IHPSG13_1P_512x8_c3_bm_bist.lef b/flow/platforms/ihp-sg13g2/lef/RM_IHPSG13_1P_512x8_c3_bm_bist.lef new file mode 100644 index 0000000000..83ecc6db0d --- /dev/null +++ b/flow/platforms/ihp-sg13g2/lef/RM_IHPSG13_1P_512x8_c3_bm_bist.lef @@ -0,0 +1,1694 @@ +# ------------------------------------------------------ +# +# Copyright 2025 IHP PDK Authors +# +# Licensed under the Apache License, Version 2.0 (the "License"); +# you may not use this file except in compliance with the License. +# You may obtain a copy of the License at +# +# https://www.apache.org/licenses/LICENSE-2.0 +# +# Unless required by applicable law or agreed to in writing, software +# distributed under the License is distributed on an "AS IS" BASIS, +# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +# See the License for the specific language governing permissions and +# limitations under the License. +# +# Generated on Wed Aug 27 16:20:24 2025 +# +# ------------------------------------------------------ +VERSION 5.7 ; +BUSBITCHARS "[]" ; +DIVIDERCHAR "/" ; + +MACRO RM_IHPSG13_1P_512x8_c3_bm_bist + CLASS BLOCK ; + ORIGIN 0 0 ; + FOREIGN RM_IHPSG13_1P_512x8_c3_bm_bist 0 0 ; + SIZE 236.8 BY 110.38 ; + SYMMETRY X Y R90 ; + PIN A_DIN[4] + DIRECTION INPUT ; + USE SIGNAL ; + ANTENNAPARTIALMETALAREA 0.7007 LAYER Metal2 ; + ANTENNAMODEL OXIDE1 ; + ANTENNAGATEAREA 0.20085 LAYER Metal2 ; + ANTENNAMAXAREACAR 4.394822 LAYER Metal2 ; + PORT + LAYER Metal2 ; + RECT 155.09 0 155.35 0.26 ; + END + END A_DIN[4] + PIN A_DIN[3] + DIRECTION INPUT ; + USE SIGNAL ; + ANTENNAPARTIALMETALAREA 0.7007 LAYER Metal2 ; + ANTENNAMODEL OXIDE1 ; + ANTENNAGATEAREA 0.20085 LAYER Metal2 ; + ANTENNAMAXAREACAR 4.394822 LAYER Metal2 ; + PORT + LAYER Metal2 ; + RECT 81.45 0 81.71 0.26 ; + END + END A_DIN[3] + PIN A_BIST_DIN[4] + DIRECTION INPUT ; + USE SIGNAL ; + ANTENNAPARTIALMETALAREA 0.7007 LAYER Metal2 ; + ANTENNAMODEL OXIDE1 ; + ANTENNAGATEAREA 0.20085 LAYER Metal2 ; + ANTENNAMAXAREACAR 4.394822 LAYER Metal2 ; + PORT + LAYER Metal2 ; + RECT 153.56 0 153.82 0.26 ; + END + END A_BIST_DIN[4] + PIN A_BIST_DIN[3] + DIRECTION INPUT ; + USE SIGNAL ; + ANTENNAPARTIALMETALAREA 0.7007 LAYER Metal2 ; + ANTENNAMODEL OXIDE1 ; + ANTENNAGATEAREA 0.20085 LAYER Metal2 ; + ANTENNAMAXAREACAR 4.394822 LAYER Metal2 ; + PORT + LAYER Metal2 ; + RECT 82.98 0 83.24 0.26 ; + END + END A_BIST_DIN[3] + PIN A_BM[4] + DIRECTION INPUT ; + USE SIGNAL ; + ANTENNAPARTIALMETALAREA 0.7007 LAYER Metal2 ; + ANTENNAMODEL OXIDE1 ; + ANTENNAGATEAREA 0.20085 LAYER Metal2 ; + ANTENNAMAXAREACAR 4.394822 LAYER Metal2 ; + PORT + LAYER Metal2 ; + RECT 158.97 0 159.23 0.26 ; + END + END A_BM[4] + PIN A_BM[3] + DIRECTION INPUT ; + USE SIGNAL ; + ANTENNAPARTIALMETALAREA 0.7007 LAYER Metal2 ; + ANTENNAMODEL OXIDE1 ; + ANTENNAGATEAREA 0.20085 LAYER Metal2 ; + ANTENNAMAXAREACAR 4.394822 LAYER Metal2 ; + PORT + LAYER Metal2 ; + RECT 77.57 0 77.83 0.26 ; + END + END A_BM[3] + PIN A_BIST_BM[4] + DIRECTION INPUT ; + USE SIGNAL ; + ANTENNAPARTIALMETALAREA 0.7007 LAYER Metal2 ; + ANTENNAMODEL OXIDE1 ; + ANTENNAGATEAREA 0.20085 LAYER Metal2 ; + ANTENNAMAXAREACAR 4.394822 LAYER Metal2 ; + PORT + LAYER Metal2 ; + RECT 160.5 0 160.76 0.26 ; + END + END A_BIST_BM[4] + PIN A_BIST_BM[3] + DIRECTION INPUT ; + USE SIGNAL ; + ANTENNAPARTIALMETALAREA 0.7007 LAYER Metal2 ; + ANTENNAMODEL OXIDE1 ; + ANTENNAGATEAREA 0.20085 LAYER Metal2 ; + ANTENNAMAXAREACAR 4.394822 LAYER Metal2 ; + PORT + LAYER Metal2 ; + RECT 76.04 0 76.3 0.26 ; + END + END A_BIST_BM[3] + PIN A_DOUT[4] + DIRECTION OUTPUT ; + USE SIGNAL ; + ANTENNAPARTIALMETALAREA 2.0345 LAYER Metal2 ; + ANTENNADIFFAREA 0.988 LAYER Metal2 ; + PORT + LAYER Metal2 ; + RECT 159.835 0 160.095 0.26 ; + END + END A_DOUT[4] + PIN A_DOUT[3] + DIRECTION OUTPUT ; + USE SIGNAL ; + ANTENNAPARTIALMETALAREA 2.0345 LAYER Metal2 ; + ANTENNADIFFAREA 0.988 LAYER Metal2 ; + PORT + LAYER Metal2 ; + RECT 76.705 0 76.965 0.26 ; + END + END A_DOUT[3] + PIN VSS! + DIRECTION INOUT ; + USE GROUND ; + NETEXPR "vss VSS!" ; + PORT + LAYER Metal4 ; + RECT 224.11 0 226.92 110.38 ; + END + PORT + LAYER Metal4 ; + RECT 212.87 0 215.68 110.38 ; + END + PORT + LAYER Metal4 ; + RECT 201.63 0 204.44 110.38 ; + END + PORT + LAYER Metal4 ; + RECT 190.39 0 193.2 110.38 ; + END + PORT + LAYER Metal4 ; + RECT 179.15 0 181.96 110.38 ; + END + PORT + LAYER Metal4 ; + RECT 167.91 0 170.72 110.38 ; + END + PORT + LAYER Metal4 ; + RECT 156.67 0 159.48 110.38 ; + END + PORT + LAYER Metal4 ; + RECT 145.43 0 148.24 110.38 ; + END + PORT + LAYER Metal4 ; + RECT 135.02 0 137.83 110.38 ; + END + PORT + LAYER Metal4 ; + RECT 124.72 0 127.53 110.38 ; + END + PORT + LAYER Metal4 ; + RECT 109.27 0 112.08 110.38 ; + END + PORT + LAYER Metal4 ; + RECT 98.97 0 101.78 110.38 ; + END + PORT + LAYER Metal4 ; + RECT 88.56 0 91.37 110.38 ; + END + PORT + LAYER Metal4 ; + RECT 77.32 0 80.13 110.38 ; + END + PORT + LAYER Metal4 ; + RECT 66.08 0 68.89 110.38 ; + END + PORT + LAYER Metal4 ; + RECT 54.84 0 57.65 110.38 ; + END + PORT + LAYER Metal4 ; + RECT 43.6 0 46.41 110.38 ; + END + PORT + LAYER Metal4 ; + RECT 32.36 0 35.17 110.38 ; + END + PORT + LAYER Metal4 ; + RECT 21.12 0 23.93 110.38 ; + END + PORT + LAYER Metal4 ; + RECT 9.88 0 12.69 110.38 ; + END + END VSS! + PIN VDD! + DIRECTION INOUT ; + USE POWER ; + NETEXPR "vdd VDD!" ; + PORT + LAYER Metal4 ; + RECT 229.73 0 232.54 30.425 ; + END + PORT + LAYER Metal4 ; + RECT 218.49 0 221.3 30.425 ; + END + PORT + LAYER Metal4 ; + RECT 207.25 0 210.06 30.425 ; + END + PORT + LAYER Metal4 ; + RECT 196.01 0 198.82 30.425 ; + END + PORT + LAYER Metal4 ; + RECT 184.77 0 187.58 30.425 ; + END + PORT + LAYER Metal4 ; + RECT 173.53 0 176.34 30.425 ; + END + PORT + LAYER Metal4 ; + RECT 162.29 0 165.1 30.425 ; + END + PORT + LAYER Metal4 ; + RECT 151.05 0 153.86 30.425 ; + END + PORT + LAYER Metal4 ; + RECT 129.87 0 132.68 110.38 ; + END + PORT + LAYER Metal4 ; + RECT 119.57 0 122.38 110.38 ; + END + PORT + LAYER Metal4 ; + RECT 114.42 0 117.23 110.38 ; + END + PORT + LAYER Metal4 ; + RECT 104.12 0 106.93 110.38 ; + END + PORT + LAYER Metal4 ; + RECT 82.94 0 85.75 30.425 ; + END + PORT + LAYER Metal4 ; + RECT 71.7 0 74.51 30.425 ; + END + PORT + LAYER Metal4 ; + RECT 60.46 0 63.27 30.425 ; + END + PORT + LAYER Metal4 ; + RECT 49.22 0 52.03 30.425 ; + END + PORT + LAYER Metal4 ; + RECT 37.98 0 40.79 30.425 ; + END + PORT + LAYER Metal4 ; + RECT 26.74 0 29.55 30.425 ; + END + PORT + LAYER Metal4 ; + RECT 15.5 0 18.31 30.425 ; + END + PORT + LAYER Metal4 ; + RECT 4.26 0 7.07 30.425 ; + END + END VDD! + PIN VDDARRAY! + DIRECTION INOUT ; + USE POWER ; + NETEXPR "vddarray VDDARRAY!" ; + PORT + LAYER Metal4 ; + RECT 229.73 37.065 232.54 110.38 ; + END + PORT + LAYER Metal4 ; + RECT 218.49 37.065 221.3 110.38 ; + END + PORT + LAYER Metal4 ; + RECT 207.25 37.065 210.06 110.38 ; + END + PORT + LAYER Metal4 ; + RECT 196.01 37.065 198.82 110.38 ; + END + PORT + LAYER Metal4 ; + RECT 184.77 37.065 187.58 110.38 ; + END + PORT + LAYER Metal4 ; + RECT 173.53 37.065 176.34 110.38 ; + END + PORT + LAYER Metal4 ; + RECT 162.29 37.065 165.1 110.38 ; + END + PORT + LAYER Metal4 ; + RECT 151.05 37.065 153.86 110.38 ; + END + PORT + LAYER Metal4 ; + RECT 82.94 37.065 85.75 110.38 ; + END + PORT + LAYER Metal4 ; + RECT 71.7 37.065 74.51 110.38 ; + END + PORT + LAYER Metal4 ; + RECT 60.46 37.065 63.27 110.38 ; + END + PORT + LAYER Metal4 ; + RECT 49.22 37.065 52.03 110.38 ; + END + PORT + LAYER Metal4 ; + RECT 37.98 37.065 40.79 110.38 ; + END + PORT + LAYER Metal4 ; + RECT 26.74 37.065 29.55 110.38 ; + END + PORT + LAYER Metal4 ; + RECT 15.5 37.065 18.31 110.38 ; + END + PORT + LAYER Metal4 ; + RECT 4.26 37.065 7.07 110.38 ; + END + END VDDARRAY! + PIN A_DIN[5] + DIRECTION INPUT ; + USE SIGNAL ; + ANTENNAPARTIALMETALAREA 0.7007 LAYER Metal2 ; + ANTENNAMODEL OXIDE1 ; + ANTENNAGATEAREA 0.20085 LAYER Metal2 ; + ANTENNAMAXAREACAR 4.394822 LAYER Metal2 ; + PORT + LAYER Metal2 ; + RECT 177.57 0 177.83 0.26 ; + END + END A_DIN[5] + PIN A_DIN[2] + DIRECTION INPUT ; + USE SIGNAL ; + ANTENNAPARTIALMETALAREA 0.7007 LAYER Metal2 ; + ANTENNAMODEL OXIDE1 ; + ANTENNAGATEAREA 0.20085 LAYER Metal2 ; + ANTENNAMAXAREACAR 4.394822 LAYER Metal2 ; + PORT + LAYER Metal2 ; + RECT 58.97 0 59.23 0.26 ; + END + END A_DIN[2] + PIN A_BIST_DIN[5] + DIRECTION INPUT ; + USE SIGNAL ; + ANTENNAPARTIALMETALAREA 0.7007 LAYER Metal2 ; + ANTENNAMODEL OXIDE1 ; + ANTENNAGATEAREA 0.20085 LAYER Metal2 ; + ANTENNAMAXAREACAR 4.394822 LAYER Metal2 ; + PORT + LAYER Metal2 ; + RECT 176.04 0 176.3 0.26 ; + END + END A_BIST_DIN[5] + PIN A_BIST_DIN[2] + DIRECTION INPUT ; + USE SIGNAL ; + ANTENNAPARTIALMETALAREA 0.7007 LAYER Metal2 ; + ANTENNAMODEL OXIDE1 ; + ANTENNAGATEAREA 0.20085 LAYER Metal2 ; + ANTENNAMAXAREACAR 4.394822 LAYER Metal2 ; + PORT + LAYER Metal2 ; + RECT 60.5 0 60.76 0.26 ; + END + END A_BIST_DIN[2] + PIN A_BM[5] + DIRECTION INPUT ; + USE SIGNAL ; + ANTENNAPARTIALMETALAREA 0.7007 LAYER Metal2 ; + ANTENNAMODEL OXIDE1 ; + ANTENNAGATEAREA 0.20085 LAYER Metal2 ; + ANTENNAMAXAREACAR 4.394822 LAYER Metal2 ; + PORT + LAYER Metal2 ; + RECT 181.45 0 181.71 0.26 ; + END + END A_BM[5] + PIN A_BM[2] + DIRECTION INPUT ; + USE SIGNAL ; + ANTENNAPARTIALMETALAREA 0.7007 LAYER Metal2 ; + ANTENNAMODEL OXIDE1 ; + ANTENNAGATEAREA 0.20085 LAYER Metal2 ; + ANTENNAMAXAREACAR 4.394822 LAYER Metal2 ; + PORT + LAYER Metal2 ; + RECT 55.09 0 55.35 0.26 ; + END + END A_BM[2] + PIN A_BIST_BM[5] + DIRECTION INPUT ; + USE SIGNAL ; + ANTENNAPARTIALMETALAREA 0.7007 LAYER Metal2 ; + ANTENNAMODEL OXIDE1 ; + ANTENNAGATEAREA 0.20085 LAYER Metal2 ; + ANTENNAMAXAREACAR 4.394822 LAYER Metal2 ; + PORT + LAYER Metal2 ; + RECT 182.98 0 183.24 0.26 ; + END + END A_BIST_BM[5] + PIN A_BIST_BM[2] + DIRECTION INPUT ; + USE SIGNAL ; + ANTENNAPARTIALMETALAREA 0.7007 LAYER Metal2 ; + ANTENNAMODEL OXIDE1 ; + ANTENNAGATEAREA 0.20085 LAYER Metal2 ; + ANTENNAMAXAREACAR 4.394822 LAYER Metal2 ; + PORT + LAYER Metal2 ; + RECT 53.56 0 53.82 0.26 ; + END + END A_BIST_BM[2] + PIN A_DOUT[5] + DIRECTION OUTPUT ; + USE SIGNAL ; + ANTENNAPARTIALMETALAREA 2.0345 LAYER Metal2 ; + ANTENNADIFFAREA 0.988 LAYER Metal2 ; + PORT + LAYER Metal2 ; + RECT 182.315 0 182.575 0.26 ; + END + END A_DOUT[5] + PIN A_DOUT[2] + DIRECTION OUTPUT ; + USE SIGNAL ; + ANTENNAPARTIALMETALAREA 2.0345 LAYER Metal2 ; + ANTENNADIFFAREA 0.988 LAYER Metal2 ; + PORT + LAYER Metal2 ; + RECT 54.225 0 54.485 0.26 ; + END + END A_DOUT[2] + PIN A_DIN[6] + DIRECTION INPUT ; + USE SIGNAL ; + ANTENNAPARTIALMETALAREA 0.7007 LAYER Metal2 ; + ANTENNAMODEL OXIDE1 ; + ANTENNAGATEAREA 0.20085 LAYER Metal2 ; + ANTENNAMAXAREACAR 4.394822 LAYER Metal2 ; + PORT + LAYER Metal2 ; + RECT 200.05 0 200.31 0.26 ; + END + END A_DIN[6] + PIN A_DIN[1] + DIRECTION INPUT ; + USE SIGNAL ; + ANTENNAPARTIALMETALAREA 0.7007 LAYER Metal2 ; + ANTENNAMODEL OXIDE1 ; + ANTENNAGATEAREA 0.20085 LAYER Metal2 ; + ANTENNAMAXAREACAR 4.394822 LAYER Metal2 ; + PORT + LAYER Metal2 ; + RECT 36.49 0 36.75 0.26 ; + END + END A_DIN[1] + PIN A_BIST_DIN[6] + DIRECTION INPUT ; + USE SIGNAL ; + ANTENNAPARTIALMETALAREA 0.7007 LAYER Metal2 ; + ANTENNAMODEL OXIDE1 ; + ANTENNAGATEAREA 0.20085 LAYER Metal2 ; + ANTENNAMAXAREACAR 4.394822 LAYER Metal2 ; + PORT + LAYER Metal2 ; + RECT 198.52 0 198.78 0.26 ; + END + END A_BIST_DIN[6] + PIN A_BIST_DIN[1] + DIRECTION INPUT ; + USE SIGNAL ; + ANTENNAPARTIALMETALAREA 0.7007 LAYER Metal2 ; + ANTENNAMODEL OXIDE1 ; + ANTENNAGATEAREA 0.20085 LAYER Metal2 ; + ANTENNAMAXAREACAR 4.394822 LAYER Metal2 ; + PORT + LAYER Metal2 ; + RECT 38.02 0 38.28 0.26 ; + END + END A_BIST_DIN[1] + PIN A_BM[6] + DIRECTION INPUT ; + USE SIGNAL ; + ANTENNAPARTIALMETALAREA 0.7007 LAYER Metal2 ; + ANTENNAMODEL OXIDE1 ; + ANTENNAGATEAREA 0.20085 LAYER Metal2 ; + ANTENNAMAXAREACAR 4.394822 LAYER Metal2 ; + PORT + LAYER Metal2 ; + RECT 203.93 0 204.19 0.26 ; + END + END A_BM[6] + PIN A_BM[1] + DIRECTION INPUT ; + USE SIGNAL ; + ANTENNAPARTIALMETALAREA 0.7007 LAYER Metal2 ; + ANTENNAMODEL OXIDE1 ; + ANTENNAGATEAREA 0.20085 LAYER Metal2 ; + ANTENNAMAXAREACAR 4.394822 LAYER Metal2 ; + PORT + LAYER Metal2 ; + RECT 32.61 0 32.87 0.26 ; + END + END A_BM[1] + PIN A_BIST_BM[6] + DIRECTION INPUT ; + USE SIGNAL ; + ANTENNAPARTIALMETALAREA 0.7007 LAYER Metal2 ; + ANTENNAMODEL OXIDE1 ; + ANTENNAGATEAREA 0.20085 LAYER Metal2 ; + ANTENNAMAXAREACAR 4.394822 LAYER Metal2 ; + PORT + LAYER Metal2 ; + RECT 205.46 0 205.72 0.26 ; + END + END A_BIST_BM[6] + PIN A_BIST_BM[1] + DIRECTION INPUT ; + USE SIGNAL ; + ANTENNAPARTIALMETALAREA 0.7007 LAYER Metal2 ; + ANTENNAMODEL OXIDE1 ; + ANTENNAGATEAREA 0.20085 LAYER Metal2 ; + ANTENNAMAXAREACAR 4.394822 LAYER Metal2 ; + PORT + LAYER Metal2 ; + RECT 31.08 0 31.34 0.26 ; + END + END A_BIST_BM[1] + PIN A_DOUT[6] + DIRECTION OUTPUT ; + USE SIGNAL ; + ANTENNAPARTIALMETALAREA 2.0345 LAYER Metal2 ; + ANTENNADIFFAREA 0.988 LAYER Metal2 ; + PORT + LAYER Metal2 ; + RECT 204.795 0 205.055 0.26 ; + END + END A_DOUT[6] + PIN A_DOUT[1] + DIRECTION OUTPUT ; + USE SIGNAL ; + ANTENNAPARTIALMETALAREA 2.0345 LAYER Metal2 ; + ANTENNADIFFAREA 0.988 LAYER Metal2 ; + PORT + LAYER Metal2 ; + RECT 31.745 0 32.005 0.26 ; + END + END A_DOUT[1] + PIN A_DIN[7] + DIRECTION INPUT ; + USE SIGNAL ; + ANTENNAPARTIALMETALAREA 0.7007 LAYER Metal2 ; + ANTENNAMODEL OXIDE1 ; + ANTENNAGATEAREA 0.20085 LAYER Metal2 ; + ANTENNAMAXAREACAR 4.394822 LAYER Metal2 ; + PORT + LAYER Metal2 ; + RECT 222.53 0 222.79 0.26 ; + END + END A_DIN[7] + PIN A_DIN[0] + DIRECTION INPUT ; + USE SIGNAL ; + ANTENNAPARTIALMETALAREA 0.7007 LAYER Metal2 ; + ANTENNAMODEL OXIDE1 ; + ANTENNAGATEAREA 0.20085 LAYER Metal2 ; + ANTENNAMAXAREACAR 4.394822 LAYER Metal2 ; + PORT + LAYER Metal2 ; + RECT 14.01 0 14.27 0.26 ; + END + END A_DIN[0] + PIN A_BIST_DIN[7] + DIRECTION INPUT ; + USE SIGNAL ; + ANTENNAPARTIALMETALAREA 0.7007 LAYER Metal2 ; + ANTENNAMODEL OXIDE1 ; + ANTENNAGATEAREA 0.20085 LAYER Metal2 ; + ANTENNAMAXAREACAR 4.394822 LAYER Metal2 ; + PORT + LAYER Metal2 ; + RECT 221 0 221.26 0.26 ; + END + END A_BIST_DIN[7] + PIN A_BIST_DIN[0] + DIRECTION INPUT ; + USE SIGNAL ; + ANTENNAPARTIALMETALAREA 0.7007 LAYER Metal2 ; + ANTENNAMODEL OXIDE1 ; + ANTENNAGATEAREA 0.20085 LAYER Metal2 ; + ANTENNAMAXAREACAR 4.394822 LAYER Metal2 ; + PORT + LAYER Metal2 ; + RECT 15.54 0 15.8 0.26 ; + END + END A_BIST_DIN[0] + PIN A_BM[7] + DIRECTION INPUT ; + USE SIGNAL ; + ANTENNAPARTIALMETALAREA 0.7007 LAYER Metal2 ; + ANTENNAMODEL OXIDE1 ; + ANTENNAGATEAREA 0.20085 LAYER Metal2 ; + ANTENNAMAXAREACAR 4.394822 LAYER Metal2 ; + PORT + LAYER Metal2 ; + RECT 226.41 0 226.67 0.26 ; + END + END A_BM[7] + PIN A_BM[0] + DIRECTION INPUT ; + USE SIGNAL ; + ANTENNAPARTIALMETALAREA 0.7007 LAYER Metal2 ; + ANTENNAMODEL OXIDE1 ; + ANTENNAGATEAREA 0.20085 LAYER Metal2 ; + ANTENNAMAXAREACAR 4.394822 LAYER Metal2 ; + PORT + LAYER Metal2 ; + RECT 10.13 0 10.39 0.26 ; + END + END A_BM[0] + PIN A_BIST_BM[7] + DIRECTION INPUT ; + USE SIGNAL ; + ANTENNAPARTIALMETALAREA 0.7007 LAYER Metal2 ; + ANTENNAMODEL OXIDE1 ; + ANTENNAGATEAREA 0.20085 LAYER Metal2 ; + ANTENNAMAXAREACAR 4.394822 LAYER Metal2 ; + PORT + LAYER Metal2 ; + RECT 227.94 0 228.2 0.26 ; + END + END A_BIST_BM[7] + PIN A_BIST_BM[0] + DIRECTION INPUT ; + USE SIGNAL ; + ANTENNAPARTIALMETALAREA 0.7007 LAYER Metal2 ; + ANTENNAMODEL OXIDE1 ; + ANTENNAGATEAREA 0.20085 LAYER Metal2 ; + ANTENNAMAXAREACAR 4.394822 LAYER Metal2 ; + PORT + LAYER Metal2 ; + RECT 8.6 0 8.86 0.26 ; + END + END A_BIST_BM[0] + PIN A_DOUT[7] + DIRECTION OUTPUT ; + USE SIGNAL ; + ANTENNAPARTIALMETALAREA 2.0345 LAYER Metal2 ; + ANTENNADIFFAREA 0.988 LAYER Metal2 ; + PORT + LAYER Metal2 ; + RECT 227.275 0 227.535 0.26 ; + END + END A_DOUT[7] + PIN A_DOUT[0] + DIRECTION OUTPUT ; + USE SIGNAL ; + ANTENNAPARTIALMETALAREA 2.0345 LAYER Metal2 ; + ANTENNADIFFAREA 0.988 LAYER Metal2 ; + PORT + LAYER Metal2 ; + RECT 9.265 0 9.525 0.26 ; + END + END A_DOUT[0] + PIN A_ADDR[0] + DIRECTION INPUT ; + USE SIGNAL ; + ANTENNAPARTIALMETALAREA 6.7171 LAYER Metal2 ; + ANTENNAMODEL OXIDE1 ; + ANTENNAGATEAREA 0.20085 LAYER Metal2 ; + ANTENNAMAXAREACAR 34.349515 LAYER Metal2 ; + PORT + LAYER Metal2 ; + RECT 114.6 0 114.86 0.26 ; + END + END A_ADDR[0] + PIN A_BIST_ADDR[0] + DIRECTION INPUT ; + USE SIGNAL ; + ANTENNAPARTIALMETALAREA 7.5127 LAYER Metal2 ; + ANTENNAMODEL OXIDE1 ; + ANTENNAGATEAREA 0.20085 LAYER Metal2 ; + ANTENNAMAXAREACAR 38.31068 LAYER Metal2 ; + PORT + LAYER Metal2 ; + RECT 119.19 0 119.45 0.26 ; + END + END A_BIST_ADDR[0] + PIN A_ADDR[1] + DIRECTION INPUT ; + USE SIGNAL ; + ANTENNAPARTIALMETALAREA 5.59 LAYER Metal2 ; + ANTENNAMODEL OXIDE1 ; + ANTENNAGATEAREA 0.20085 LAYER Metal2 ; + ANTENNAMAXAREACAR 28.783172 LAYER Metal2 ; + PORT + LAYER Metal2 ; + RECT 114.09 0 114.35 0.26 ; + END + END A_ADDR[1] + PIN A_BIST_ADDR[1] + DIRECTION INPUT ; + USE SIGNAL ; + ANTENNAPARTIALMETALAREA 6.3856 LAYER Metal2 ; + ANTENNAMODEL OXIDE1 ; + ANTENNAGATEAREA 0.20085 LAYER Metal2 ; + ANTENNAMAXAREACAR 32.744337 LAYER Metal2 ; + PORT + LAYER Metal2 ; + RECT 118.68 0 118.94 0.26 ; + END + END A_BIST_ADDR[1] + PIN A_ADDR[2] + DIRECTION INPUT ; + USE SIGNAL ; + ANTENNAPARTIALMETALAREA 6.4519 LAYER Metal2 ; + ANTENNAMODEL OXIDE1 ; + ANTENNAGATEAREA 0.20085 LAYER Metal2 ; + ANTENNAMAXAREACAR 33.029126 LAYER Metal2 ; + PORT + LAYER Metal2 ; + RECT 99.81 0 100.07 0.26 ; + END + END A_ADDR[2] + PIN A_BIST_ADDR[2] + DIRECTION INPUT ; + USE SIGNAL ; + ANTENNAPARTIALMETALAREA 6.1867 LAYER Metal2 ; + ANTENNAMODEL OXIDE1 ; + ANTENNAGATEAREA 0.20085 LAYER Metal2 ; + ANTENNAMAXAREACAR 31.708738 LAYER Metal2 ; + PORT + LAYER Metal2 ; + RECT 101.34 0 101.6 0.26 ; + END + END A_BIST_ADDR[2] + PIN A_ADDR[3] + DIRECTION INPUT ; + USE SIGNAL ; + ANTENNAPARTIALMETALAREA 8.4487 LAYER Metal2 ; + ANTENNAPARTIALMETALAREA 1.5246 LAYER Metal3 ; + ANTENNAPARTIALCUTAREA 0.0722 LAYER Via2 ; + ANTENNAMODEL OXIDE1 ; + ANTENNAGATEAREA 0.20085 LAYER Metal3 ; + ANTENNAMAXAREACAR 9.415982 LAYER Metal3 ; + PORT + LAYER Metal2 ; + RECT 122.25 0 122.51 0.26 ; + END + END A_ADDR[3] + PIN A_BIST_ADDR[3] + DIRECTION INPUT ; + USE SIGNAL ; + ANTENNAPARTIALMETALAREA 8.4487 LAYER Metal2 ; + ANTENNAPARTIALMETALAREA 1.0962 LAYER Metal3 ; + ANTENNAPARTIALCUTAREA 0.0722 LAYER Via2 ; + ANTENNAMODEL OXIDE1 ; + ANTENNAGATEAREA 0.20085 LAYER Metal3 ; + ANTENNAMAXAREACAR 7.813791 LAYER Metal3 ; + PORT + LAYER Metal2 ; + RECT 122.76 0 123.02 0.26 ; + END + END A_BIST_ADDR[3] + PIN A_ADDR[4] + DIRECTION INPUT ; + USE SIGNAL ; + ANTENNAPARTIALMETALAREA 8.4487 LAYER Metal2 ; + ANTENNAPARTIALMETALAREA 3.8367 LAYER Metal3 ; + ANTENNAPARTIALCUTAREA 0.0722 LAYER Via2 ; + ANTENNAMODEL OXIDE1 ; + ANTENNAGATEAREA 0.20085 LAYER Metal3 ; + ANTENNAMAXAREACAR 20.927558 LAYER Metal3 ; + PORT + LAYER Metal2 ; + RECT 121.23 0 121.49 0.26 ; + END + END A_ADDR[4] + PIN A_BIST_ADDR[4] + DIRECTION INPUT ; + USE SIGNAL ; + ANTENNAPARTIALMETALAREA 8.4487 LAYER Metal2 ; + ANTENNAPARTIALMETALAREA 3.5175 LAYER Metal3 ; + ANTENNAPARTIALCUTAREA 0.0722 LAYER Via2 ; + ANTENNAMODEL OXIDE1 ; + ANTENNAGATEAREA 0.20085 LAYER Metal3 ; + ANTENNAMAXAREACAR 19.869057 LAYER Metal3 ; + PORT + LAYER Metal2 ; + RECT 121.74 0 122 0.26 ; + END + END A_BIST_ADDR[4] + PIN A_ADDR[5] + DIRECTION INPUT ; + USE SIGNAL ; + ANTENNAPARTIALMETALAREA 10.0139 LAYER Metal2 ; + ANTENNAMODEL OXIDE1 ; + ANTENNAGATEAREA 0.20085 LAYER Metal2 ; + ANTENNAMAXAREACAR 50.763754 LAYER Metal2 ; + PORT + LAYER Metal2 ; + RECT 124.8 0 125.06 0.26 ; + END + END A_ADDR[5] + PIN A_BIST_ADDR[5] + DIRECTION INPUT ; + USE SIGNAL ; + ANTENNAPARTIALMETALAREA 9.7487 LAYER Metal2 ; + ANTENNAMODEL OXIDE1 ; + ANTENNAGATEAREA 0.20085 LAYER Metal2 ; + ANTENNAMAXAREACAR 49.443366 LAYER Metal2 ; + PORT + LAYER Metal2 ; + RECT 124.29 0 124.55 0.26 ; + END + END A_BIST_ADDR[5] + PIN A_ADDR[6] + DIRECTION INPUT ; + USE SIGNAL ; + ANTENNAPARTIALMETALAREA 11.7429 LAYER Metal2 ; + ANTENNAMODEL OXIDE1 ; + ANTENNAGATEAREA 0.20085 LAYER Metal2 ; + ANTENNAMAXAREACAR 59.372168 LAYER Metal2 ; + PORT + LAYER Metal2 ; + RECT 123.78 0 124.04 0.26 ; + END + END A_ADDR[6] + PIN A_BIST_ADDR[6] + DIRECTION INPUT ; + USE SIGNAL ; + ANTENNAPARTIALMETALAREA 11.4777 LAYER Metal2 ; + ANTENNAMODEL OXIDE1 ; + ANTENNAGATEAREA 0.20085 LAYER Metal2 ; + ANTENNAMAXAREACAR 58.05178 LAYER Metal2 ; + PORT + LAYER Metal2 ; + RECT 123.27 0 123.53 0.26 ; + END + END A_BIST_ADDR[6] + PIN A_ADDR[7] + DIRECTION INPUT ; + USE SIGNAL ; + ANTENNAPARTIALMETALAREA 8.7685 LAYER Metal2 ; + ANTENNAMODEL OXIDE1 ; + ANTENNAGATEAREA 0.20085 LAYER Metal2 ; + ANTENNAMAXAREACAR 44.563107 LAYER Metal2 ; + PORT + LAYER Metal2 ; + RECT 102.36 0 102.62 0.26 ; + END + END A_ADDR[7] + PIN A_BIST_ADDR[7] + DIRECTION INPUT ; + USE SIGNAL ; + ANTENNAPARTIALMETALAREA 8.4931 LAYER Metal2 ; + ANTENNAMODEL OXIDE1 ; + ANTENNAGATEAREA 0.20085 LAYER Metal2 ; + ANTENNAMAXAREACAR 43.191934 LAYER Metal2 ; + PORT + LAYER Metal2 ; + RECT 102.87 0 103.13 0.26 ; + END + END A_BIST_ADDR[7] + PIN A_ADDR[8] + DIRECTION INPUT ; + USE SIGNAL ; + ANTENNAPARTIALMETALAREA 10.2323 LAYER Metal2 ; + ANTENNAMODEL OXIDE1 ; + ANTENNAGATEAREA 0.20085 LAYER Metal2 ; + ANTENNAMAXAREACAR 51.851133 LAYER Metal2 ; + PORT + LAYER Metal2 ; + RECT 103.38 0 103.64 0.26 ; + END + END A_ADDR[8] + PIN A_BIST_ADDR[8] + DIRECTION INPUT ; + USE SIGNAL ; + ANTENNAPARTIALMETALAREA 9.9671 LAYER Metal2 ; + ANTENNAMODEL OXIDE1 ; + ANTENNAGATEAREA 0.20085 LAYER Metal2 ; + ANTENNAMAXAREACAR 50.530744 LAYER Metal2 ; + PORT + LAYER Metal2 ; + RECT 103.89 0 104.15 0.26 ; + END + END A_BIST_ADDR[8] + PIN A_CLK + DIRECTION INPUT ; + USE SIGNAL ; + ANTENNAPARTIALMETALAREA 1.8707 LAYER Metal2 ; + ANTENNAMODEL OXIDE1 ; + ANTENNAGATEAREA 0.20085 LAYER Metal2 ; + ANTENNAMAXAREACAR 10.220065 LAYER Metal2 ; + PORT + LAYER Metal2 ; + RECT 112.56 0 112.82 0.26 ; + END + END A_CLK + PIN A_REN + DIRECTION INPUT ; + USE SIGNAL ; + ANTENNAPARTIALMETALAREA 1.81105 LAYER Metal2 ; + ANTENNAMODEL OXIDE1 ; + ANTENNAGATEAREA 0.20085 LAYER Metal2 ; + ANTENNAMAXAREACAR 9.923077 LAYER Metal2 ; + PORT + LAYER Metal2 ; + RECT 116.13 0 116.39 0.26 ; + END + END A_REN + PIN A_WEN + DIRECTION INPUT ; + USE SIGNAL ; + ANTENNAPARTIALMETALAREA 0.7007 LAYER Metal2 ; + ANTENNAMODEL OXIDE1 ; + ANTENNAGATEAREA 0.20085 LAYER Metal2 ; + ANTENNAMAXAREACAR 4.394822 LAYER Metal2 ; + PORT + LAYER Metal2 ; + RECT 115.62 0 115.88 0.26 ; + END + END A_WEN + PIN A_MEN + DIRECTION INPUT ; + USE SIGNAL ; + ANTENNAPARTIALMETALAREA 0.8407 LAYER Metal2 ; + ANTENNAMODEL OXIDE1 ; + ANTENNAGATEAREA 0.20085 LAYER Metal2 ; + ANTENNAMAXAREACAR 5.09186 LAYER Metal2 ; + PORT + LAYER Metal2 ; + RECT 113.07 0 113.33 0.26 ; + END + END A_MEN + PIN A_DLY + DIRECTION INPUT ; + USE SIGNAL ; + ANTENNAPARTIALMETALAREA 3.874 LAYER Metal2 ; + ANTENNAMODEL OXIDE1 ; + ANTENNAGATEAREA 0.3367 LAYER Metal2 ; + ANTENNAMAXAREACAR 12.046332 LAYER Metal2 ; + PORT + LAYER Metal2 ; + RECT 134.49 0 134.75 0.26 ; + END + END A_DLY + PIN A_BIST_EN + DIRECTION INPUT ; + USE SIGNAL ; + ANTENNAPARTIALMETALAREA 1.8031 LAYER Metal2 ; + ANTENNAPARTIALMETALAREA 72.69295 LAYER Metal3 ; + ANTENNAPARTIALCUTAREA 0.0722 LAYER Via2 ; + ANTENNAMODEL OXIDE1 ; + ANTENNAGATEAREA 1.43 LAYER Metal2 ; + ANTENNAGATEAREA 10.3675 LAYER Metal3 ; + ANTENNAMAXAREACAR 1.686364 LAYER Metal2 ; + ANTENNAMAXAREACAR 13.950709 LAYER Metal3 ; + ANTENNAMAXCUTCAR 0.151469 LAYER Via2 ; + PORT + LAYER Metal2 ; + RECT 115.11 0 115.37 0.26 ; + END + END A_BIST_EN + PIN A_BIST_CLK + DIRECTION INPUT ; + USE SIGNAL ; + ANTENNAPARTIALMETALAREA 1.9799 LAYER Metal2 ; + ANTENNAMODEL OXIDE1 ; + ANTENNAGATEAREA 0.20085 LAYER Metal2 ; + ANTENNAMAXAREACAR 11.079661 LAYER Metal2 ; + PORT + LAYER Metal2 ; + RECT 111.03 0 111.29 0.26 ; + END + END A_BIST_CLK + PIN A_BIST_REN + DIRECTION INPUT ; + USE SIGNAL ; + ANTENNAPARTIALMETALAREA 1.9279 LAYER Metal2 ; + ANTENNAMODEL OXIDE1 ; + ANTENNAGATEAREA 0.20085 LAYER Metal2 ; + ANTENNAMAXAREACAR 10.820762 LAYER Metal2 ; + PORT + LAYER Metal2 ; + RECT 117.66 0 117.92 0.26 ; + END + END A_BIST_REN + PIN A_BIST_WEN + DIRECTION INPUT ; + USE SIGNAL ; + ANTENNAPARTIALMETALAREA 0.7211 LAYER Metal2 ; + ANTENNAMODEL OXIDE1 ; + ANTENNAGATEAREA 0.20085 LAYER Metal2 ; + ANTENNAMAXAREACAR 4.812298 LAYER Metal2 ; + PORT + LAYER Metal2 ; + RECT 117.15 0 117.41 0.26 ; + END + END A_BIST_WEN + PIN A_BIST_MEN + DIRECTION INPUT ; + USE SIGNAL ; + ANTENNAPARTIALMETALAREA 0.7137 LAYER Metal2 ; + ANTENNAMODEL OXIDE1 ; + ANTENNAGATEAREA 0.20085 LAYER Metal2 ; + ANTENNAMAXAREACAR 4.775454 LAYER Metal2 ; + PORT + LAYER Metal2 ; + RECT 111.54 0 111.8 0.26 ; + END + END A_BIST_MEN + OBS + LAYER Metal1 ; + RECT 0 0 236.8 110.38 ; + LAYER Metal2 ; + RECT 0.105 37.065 0.305 110.355 ; + RECT 1.1 109.625 1.3 110.355 ; + RECT 1.92 109.625 2.12 110.355 ; + RECT 2.415 109.625 2.615 110.355 ; + RECT 2.915 109.625 3.115 110.355 ; + RECT 3.415 109.625 3.615 110.355 ; + RECT 3.91 109.625 4.11 110.355 ; + RECT 4.73 109.625 4.93 110.355 ; + RECT 5.225 109.625 5.425 110.355 ; + RECT 5.725 109.625 5.925 110.355 ; + RECT 7.225 0.17 7.995 0.43 ; + RECT 7.225 0.17 7.485 11.38 ; + RECT 7.735 0.17 7.995 17.1 ; + RECT 6.225 109.625 6.425 110.355 ; + RECT 6.72 109.625 6.92 110.355 ; + RECT 7.54 109.625 7.74 110.355 ; + RECT 8.035 109.625 8.235 110.355 ; + RECT 8.535 109.625 8.735 110.355 ; + RECT 8.6 0.52 8.86 2.255 ; + RECT 9.035 109.625 9.235 110.355 ; + RECT 9.265 0.52 9.525 8.085 ; + RECT 9.53 109.625 9.73 110.355 ; + RECT 10.13 0.52 10.39 1.5 ; + RECT 10.35 109.625 10.55 110.355 ; + RECT 10.845 109.625 11.045 110.355 ; + RECT 11.345 109.625 11.545 110.355 ; + RECT 11.845 109.625 12.045 110.355 ; + RECT 12.34 109.625 12.54 110.355 ; + RECT 13.16 109.625 13.36 110.355 ; + RECT 13.655 109.625 13.855 110.355 ; + RECT 14.01 0.52 14.27 2.255 ; + RECT 14.155 109.625 14.355 110.355 ; + RECT 14.655 109.625 14.855 110.355 ; + RECT 15.15 109.625 15.35 110.355 ; + RECT 16.255 0.8 17.025 1.57 ; + RECT 16.255 0.3 16.515 13.03 ; + RECT 16.765 0.3 17.025 13.03 ; + RECT 15.54 0.52 15.8 2.255 ; + RECT 15.97 109.625 16.17 110.355 ; + RECT 16.465 109.625 16.665 110.355 ; + RECT 16.965 109.625 17.165 110.355 ; + RECT 17.465 109.625 17.665 110.355 ; + RECT 17.96 109.625 18.16 110.355 ; + RECT 18.78 109.625 18.98 110.355 ; + RECT 19.975 0.17 20.745 0.43 ; + RECT 19.975 0.17 20.235 13.055 ; + RECT 20.485 0.17 20.745 13.055 ; + RECT 19.275 109.625 19.475 110.355 ; + RECT 19.775 109.625 19.975 110.355 ; + RECT 20.275 109.625 20.475 110.355 ; + RECT 20.77 109.625 20.97 110.355 ; + RECT 21.59 109.625 21.79 110.355 ; + RECT 22.085 109.625 22.285 110.355 ; + RECT 22.585 109.625 22.785 110.355 ; + RECT 23.085 109.625 23.285 110.355 ; + RECT 23.58 109.625 23.78 110.355 ; + RECT 24.4 109.625 24.6 110.355 ; + RECT 24.895 109.625 25.095 110.355 ; + RECT 25.395 109.625 25.595 110.355 ; + RECT 25.895 109.625 26.095 110.355 ; + RECT 26.39 109.625 26.59 110.355 ; + RECT 27.21 109.625 27.41 110.355 ; + RECT 27.705 109.625 27.905 110.355 ; + RECT 28.205 109.625 28.405 110.355 ; + RECT 29.705 0.17 30.475 0.43 ; + RECT 29.705 0.17 29.965 11.38 ; + RECT 30.215 0.17 30.475 17.1 ; + RECT 28.705 109.625 28.905 110.355 ; + RECT 29.2 109.625 29.4 110.355 ; + RECT 30.02 109.625 30.22 110.355 ; + RECT 30.515 109.625 30.715 110.355 ; + RECT 31.015 109.625 31.215 110.355 ; + RECT 31.08 0.52 31.34 2.255 ; + RECT 31.515 109.625 31.715 110.355 ; + RECT 31.745 0.52 32.005 8.085 ; + RECT 32.01 109.625 32.21 110.355 ; + RECT 32.61 0.52 32.87 1.5 ; + RECT 32.83 109.625 33.03 110.355 ; + RECT 33.325 109.625 33.525 110.355 ; + RECT 33.825 109.625 34.025 110.355 ; + RECT 34.325 109.625 34.525 110.355 ; + RECT 34.82 109.625 35.02 110.355 ; + RECT 35.64 109.625 35.84 110.355 ; + RECT 36.135 109.625 36.335 110.355 ; + RECT 36.49 0.52 36.75 2.255 ; + RECT 36.635 109.625 36.835 110.355 ; + RECT 37.135 109.625 37.335 110.355 ; + RECT 37.63 109.625 37.83 110.355 ; + RECT 38.735 0.8 39.505 1.57 ; + RECT 38.735 0.3 38.995 13.03 ; + RECT 39.245 0.3 39.505 13.03 ; + RECT 38.02 0.52 38.28 2.255 ; + RECT 38.45 109.625 38.65 110.355 ; + RECT 38.945 109.625 39.145 110.355 ; + RECT 39.445 109.625 39.645 110.355 ; + RECT 39.945 109.625 40.145 110.355 ; + RECT 40.44 109.625 40.64 110.355 ; + RECT 41.26 109.625 41.46 110.355 ; + RECT 42.455 0.17 43.225 0.43 ; + RECT 42.455 0.17 42.715 13.055 ; + RECT 42.965 0.17 43.225 13.055 ; + RECT 41.755 109.625 41.955 110.355 ; + RECT 42.255 109.625 42.455 110.355 ; + RECT 42.755 109.625 42.955 110.355 ; + RECT 43.25 109.625 43.45 110.355 ; + RECT 44.07 109.625 44.27 110.355 ; + RECT 44.565 109.625 44.765 110.355 ; + RECT 45.065 109.625 45.265 110.355 ; + RECT 45.565 109.625 45.765 110.355 ; + RECT 46.06 109.625 46.26 110.355 ; + RECT 46.88 109.625 47.08 110.355 ; + RECT 47.375 109.625 47.575 110.355 ; + RECT 47.875 109.625 48.075 110.355 ; + RECT 48.375 109.625 48.575 110.355 ; + RECT 48.87 109.625 49.07 110.355 ; + RECT 49.69 109.625 49.89 110.355 ; + RECT 50.185 109.625 50.385 110.355 ; + RECT 50.685 109.625 50.885 110.355 ; + RECT 52.185 0.17 52.955 0.43 ; + RECT 52.185 0.17 52.445 11.38 ; + RECT 52.695 0.17 52.955 17.1 ; + RECT 51.185 109.625 51.385 110.355 ; + RECT 51.68 109.625 51.88 110.355 ; + RECT 52.5 109.625 52.7 110.355 ; + RECT 52.995 109.625 53.195 110.355 ; + RECT 53.495 109.625 53.695 110.355 ; + RECT 53.56 0.52 53.82 2.255 ; + RECT 53.995 109.625 54.195 110.355 ; + RECT 54.225 0.52 54.485 8.085 ; + RECT 54.49 109.625 54.69 110.355 ; + RECT 55.09 0.52 55.35 1.5 ; + RECT 55.31 109.625 55.51 110.355 ; + RECT 55.805 109.625 56.005 110.355 ; + RECT 56.305 109.625 56.505 110.355 ; + RECT 56.805 109.625 57.005 110.355 ; + RECT 57.3 109.625 57.5 110.355 ; + RECT 58.12 109.625 58.32 110.355 ; + RECT 58.615 109.625 58.815 110.355 ; + RECT 58.97 0.52 59.23 2.255 ; + RECT 59.115 109.625 59.315 110.355 ; + RECT 59.615 109.625 59.815 110.355 ; + RECT 60.11 109.625 60.31 110.355 ; + RECT 61.215 0.8 61.985 1.57 ; + RECT 61.215 0.3 61.475 13.03 ; + RECT 61.725 0.3 61.985 13.03 ; + RECT 60.5 0.52 60.76 2.255 ; + RECT 60.93 109.625 61.13 110.355 ; + RECT 61.425 109.625 61.625 110.355 ; + RECT 61.925 109.625 62.125 110.355 ; + RECT 62.425 109.625 62.625 110.355 ; + RECT 62.92 109.625 63.12 110.355 ; + RECT 63.74 109.625 63.94 110.355 ; + RECT 64.935 0.17 65.705 0.43 ; + RECT 64.935 0.17 65.195 13.055 ; + RECT 65.445 0.17 65.705 13.055 ; + RECT 64.235 109.625 64.435 110.355 ; + RECT 64.735 109.625 64.935 110.355 ; + RECT 65.235 109.625 65.435 110.355 ; + RECT 65.73 109.625 65.93 110.355 ; + RECT 66.55 109.625 66.75 110.355 ; + RECT 67.045 109.625 67.245 110.355 ; + RECT 67.545 109.625 67.745 110.355 ; + RECT 68.045 109.625 68.245 110.355 ; + RECT 68.54 109.625 68.74 110.355 ; + RECT 69.36 109.625 69.56 110.355 ; + RECT 69.855 109.625 70.055 110.355 ; + RECT 70.355 109.625 70.555 110.355 ; + RECT 70.855 109.625 71.055 110.355 ; + RECT 71.35 109.625 71.55 110.355 ; + RECT 72.17 109.625 72.37 110.355 ; + RECT 72.665 109.625 72.865 110.355 ; + RECT 73.165 109.625 73.365 110.355 ; + RECT 74.665 0.17 75.435 0.43 ; + RECT 74.665 0.17 74.925 11.38 ; + RECT 75.175 0.17 75.435 17.1 ; + RECT 73.665 109.625 73.865 110.355 ; + RECT 74.16 109.625 74.36 110.355 ; + RECT 74.98 109.625 75.18 110.355 ; + RECT 75.475 109.625 75.675 110.355 ; + RECT 75.975 109.625 76.175 110.355 ; + RECT 76.04 0.52 76.3 2.255 ; + RECT 76.475 109.625 76.675 110.355 ; + RECT 76.705 0.52 76.965 8.085 ; + RECT 76.97 109.625 77.17 110.355 ; + RECT 77.57 0.52 77.83 1.5 ; + RECT 77.79 109.625 77.99 110.355 ; + RECT 78.285 109.625 78.485 110.355 ; + RECT 78.785 109.625 78.985 110.355 ; + RECT 79.285 109.625 79.485 110.355 ; + RECT 79.78 109.625 79.98 110.355 ; + RECT 80.6 109.625 80.8 110.355 ; + RECT 81.095 109.625 81.295 110.355 ; + RECT 81.45 0.52 81.71 2.255 ; + RECT 81.595 109.625 81.795 110.355 ; + RECT 82.095 109.625 82.295 110.355 ; + RECT 82.59 109.625 82.79 110.355 ; + RECT 83.695 0.8 84.465 1.57 ; + RECT 83.695 0.3 83.955 13.03 ; + RECT 84.205 0.3 84.465 13.03 ; + RECT 82.98 0.52 83.24 2.255 ; + RECT 83.41 109.625 83.61 110.355 ; + RECT 83.905 109.625 84.105 110.355 ; + RECT 84.405 109.625 84.605 110.355 ; + RECT 84.905 109.625 85.105 110.355 ; + RECT 85.4 109.625 85.6 110.355 ; + RECT 86.22 109.625 86.42 110.355 ; + RECT 87.415 0.17 88.185 0.43 ; + RECT 87.415 0.17 87.675 13.055 ; + RECT 87.925 0.17 88.185 13.055 ; + RECT 86.715 109.625 86.915 110.355 ; + RECT 87.215 109.625 87.415 110.355 ; + RECT 87.715 109.625 87.915 110.355 ; + RECT 88.21 109.625 88.41 110.355 ; + RECT 89.03 109.625 89.23 110.355 ; + RECT 89.525 109.625 89.725 110.355 ; + RECT 90.025 109.625 90.225 110.355 ; + RECT 90.525 109.625 90.725 110.355 ; + RECT 96.595 0.17 97.365 0.43 ; + RECT 96.595 0.17 96.855 36.945 ; + RECT 97.105 0.17 97.365 36.945 ; + RECT 91.02 109.625 91.22 110.355 ; + RECT 91.84 109.625 92.04 110.355 ; + RECT 99.3 0 99.56 4.94 ; + RECT 99.3 4.68 100.07 4.94 ; + RECT 99.81 4.68 100.07 12.9 ; + RECT 99.81 0.52 100.07 1.78 ; + RECT 99.81 1.52 100.58 1.78 ; + RECT 100.32 1.52 100.58 12.9 ; + RECT 92.835 109.625 93.035 110.355 ; + RECT 100.32 0.59 101.09 1.27 ; + RECT 100.83 0.59 101.09 7.965 ; + RECT 97.615 0.3 97.875 37.365 ; + RECT 98.125 0.3 98.385 37.365 ; + RECT 101.34 0.52 101.6 12.9 ; + RECT 101.85 0 102.11 12.9 ; + RECT 102.36 0.52 102.62 12.9 ; + RECT 102.87 0.52 103.13 12.9 ; + RECT 103.38 0.52 103.64 12.9 ; + RECT 106.44 0.17 107.21 0.43 ; + RECT 106.44 0.17 106.7 2.085 ; + RECT 106.95 0.17 107.21 9 ; + RECT 103.89 0.52 104.15 12.9 ; + RECT 104.4 0 104.66 8.565 ; + RECT 104.91 0 105.17 8.055 ; + RECT 111.03 0.52 111.29 6.59 ; + RECT 112.56 0.52 112.82 6.305 ; + RECT 112.56 6.045 113.53 6.305 ; + RECT 111.54 0.52 111.8 2.23 ; + RECT 113.07 0.52 113.33 2.955 ; + RECT 114.09 0.52 114.35 12.9 ; + RECT 114.6 0.52 114.86 12.9 ; + RECT 116.13 0.52 116.39 6.29 ; + RECT 115.62 6.045 116.39 6.29 ; + RECT 115.11 0.52 115.37 6.745 ; + RECT 117.66 0.52 117.92 6.59 ; + RECT 117.015 6.33 117.92 6.59 ; + RECT 115.62 0.52 115.88 2.955 ; + RECT 117.15 0.52 117.41 2.67 ; + RECT 118.68 0.52 118.94 12.9 ; + RECT 119.19 0.52 119.45 12.9 ; + RECT 120.72 0.575 120.98 7.965 ; + RECT 121.23 0.52 121.49 12.9 ; + RECT 121.74 0.52 122 12.9 ; + RECT 122.25 0.52 122.51 12.9 ; + RECT 122.76 0.52 123.02 12.9 ; + RECT 123.27 0.52 123.53 12.9 ; + RECT 123.78 0.52 124.04 12.9 ; + RECT 124.29 0.52 124.55 12.9 ; + RECT 124.8 0.52 125.06 12.9 ; + RECT 125.31 0 125.57 12.9 ; + RECT 125.82 0 126.08 12.9 ; + RECT 127.35 0 127.61 12.9 ; + RECT 127.86 0 128.12 12.9 ; + RECT 135 0.17 135.77 0.43 ; + RECT 135 0.17 135.26 13.845 ; + RECT 135.51 0.17 135.77 13.845 ; + RECT 137.04 0.17 137.81 0.43 ; + RECT 137.04 0.17 137.3 2.11 ; + RECT 137.55 0.17 137.81 2.11 ; + RECT 132.45 0 132.71 3.61 ; + RECT 132.96 0 133.22 4.12 ; + RECT 139.435 0.17 140.205 0.43 ; + RECT 139.435 0.17 139.695 36.945 ; + RECT 139.945 0.17 140.205 36.945 ; + RECT 134.49 0.52 134.75 15.16 ; + RECT 138.415 0.3 138.675 37.365 ; + RECT 138.925 0.3 139.185 37.365 ; + RECT 143.765 109.625 143.965 110.355 ; + RECT 144.76 109.625 144.96 110.355 ; + RECT 145.58 109.625 145.78 110.355 ; + RECT 146.075 109.625 146.275 110.355 ; + RECT 146.575 109.625 146.775 110.355 ; + RECT 147.075 109.625 147.275 110.355 ; + RECT 148.615 0.17 149.385 0.43 ; + RECT 148.615 0.17 148.875 13.055 ; + RECT 149.125 0.17 149.385 13.055 ; + RECT 147.57 109.625 147.77 110.355 ; + RECT 148.39 109.625 148.59 110.355 ; + RECT 148.885 109.625 149.085 110.355 ; + RECT 149.385 109.625 149.585 110.355 ; + RECT 149.885 109.625 150.085 110.355 ; + RECT 150.38 109.625 150.58 110.355 ; + RECT 151.2 109.625 151.4 110.355 ; + RECT 152.335 0.8 153.105 1.57 ; + RECT 152.335 0.3 152.595 13.03 ; + RECT 152.845 0.3 153.105 13.03 ; + RECT 151.695 109.625 151.895 110.355 ; + RECT 152.195 109.625 152.395 110.355 ; + RECT 152.695 109.625 152.895 110.355 ; + RECT 153.19 109.625 153.39 110.355 ; + RECT 153.56 0.52 153.82 2.255 ; + RECT 154.01 109.625 154.21 110.355 ; + RECT 154.505 109.625 154.705 110.355 ; + RECT 155.005 109.625 155.205 110.355 ; + RECT 155.09 0.52 155.35 2.255 ; + RECT 155.505 109.625 155.705 110.355 ; + RECT 156 109.625 156.2 110.355 ; + RECT 156.82 109.625 157.02 110.355 ; + RECT 157.315 109.625 157.515 110.355 ; + RECT 157.815 109.625 158.015 110.355 ; + RECT 158.315 109.625 158.515 110.355 ; + RECT 158.81 109.625 159.01 110.355 ; + RECT 158.97 0.52 159.23 1.5 ; + RECT 159.63 109.625 159.83 110.355 ; + RECT 159.835 0.52 160.095 8.085 ; + RECT 160.125 109.625 160.325 110.355 ; + RECT 160.5 0.52 160.76 2.255 ; + RECT 161.365 0.17 162.135 0.43 ; + RECT 161.875 0.17 162.135 11.38 ; + RECT 161.365 0.17 161.625 17.1 ; + RECT 160.625 109.625 160.825 110.355 ; + RECT 161.125 109.625 161.325 110.355 ; + RECT 161.62 109.625 161.82 110.355 ; + RECT 162.44 109.625 162.64 110.355 ; + RECT 162.935 109.625 163.135 110.355 ; + RECT 163.435 109.625 163.635 110.355 ; + RECT 163.935 109.625 164.135 110.355 ; + RECT 164.43 109.625 164.63 110.355 ; + RECT 165.25 109.625 165.45 110.355 ; + RECT 165.745 109.625 165.945 110.355 ; + RECT 166.245 109.625 166.445 110.355 ; + RECT 166.745 109.625 166.945 110.355 ; + RECT 167.24 109.625 167.44 110.355 ; + RECT 168.06 109.625 168.26 110.355 ; + RECT 168.555 109.625 168.755 110.355 ; + RECT 169.055 109.625 169.255 110.355 ; + RECT 169.555 109.625 169.755 110.355 ; + RECT 171.095 0.17 171.865 0.43 ; + RECT 171.095 0.17 171.355 13.055 ; + RECT 171.605 0.17 171.865 13.055 ; + RECT 170.05 109.625 170.25 110.355 ; + RECT 170.87 109.625 171.07 110.355 ; + RECT 171.365 109.625 171.565 110.355 ; + RECT 171.865 109.625 172.065 110.355 ; + RECT 172.365 109.625 172.565 110.355 ; + RECT 172.86 109.625 173.06 110.355 ; + RECT 173.68 109.625 173.88 110.355 ; + RECT 174.815 0.8 175.585 1.57 ; + RECT 174.815 0.3 175.075 13.03 ; + RECT 175.325 0.3 175.585 13.03 ; + RECT 174.175 109.625 174.375 110.355 ; + RECT 174.675 109.625 174.875 110.355 ; + RECT 175.175 109.625 175.375 110.355 ; + RECT 175.67 109.625 175.87 110.355 ; + RECT 176.04 0.52 176.3 2.255 ; + RECT 176.49 109.625 176.69 110.355 ; + RECT 176.985 109.625 177.185 110.355 ; + RECT 177.485 109.625 177.685 110.355 ; + RECT 177.57 0.52 177.83 2.255 ; + RECT 177.985 109.625 178.185 110.355 ; + RECT 178.48 109.625 178.68 110.355 ; + RECT 179.3 109.625 179.5 110.355 ; + RECT 179.795 109.625 179.995 110.355 ; + RECT 180.295 109.625 180.495 110.355 ; + RECT 180.795 109.625 180.995 110.355 ; + RECT 181.29 109.625 181.49 110.355 ; + RECT 181.45 0.52 181.71 1.5 ; + RECT 182.11 109.625 182.31 110.355 ; + RECT 182.315 0.52 182.575 8.085 ; + RECT 182.605 109.625 182.805 110.355 ; + RECT 182.98 0.52 183.24 2.255 ; + RECT 183.845 0.17 184.615 0.43 ; + RECT 184.355 0.17 184.615 11.38 ; + RECT 183.845 0.17 184.105 17.1 ; + RECT 183.105 109.625 183.305 110.355 ; + RECT 183.605 109.625 183.805 110.355 ; + RECT 184.1 109.625 184.3 110.355 ; + RECT 184.92 109.625 185.12 110.355 ; + RECT 185.415 109.625 185.615 110.355 ; + RECT 185.915 109.625 186.115 110.355 ; + RECT 186.415 109.625 186.615 110.355 ; + RECT 186.91 109.625 187.11 110.355 ; + RECT 187.73 109.625 187.93 110.355 ; + RECT 188.225 109.625 188.425 110.355 ; + RECT 188.725 109.625 188.925 110.355 ; + RECT 189.225 109.625 189.425 110.355 ; + RECT 189.72 109.625 189.92 110.355 ; + RECT 190.54 109.625 190.74 110.355 ; + RECT 191.035 109.625 191.235 110.355 ; + RECT 191.535 109.625 191.735 110.355 ; + RECT 192.035 109.625 192.235 110.355 ; + RECT 193.575 0.17 194.345 0.43 ; + RECT 193.575 0.17 193.835 13.055 ; + RECT 194.085 0.17 194.345 13.055 ; + RECT 192.53 109.625 192.73 110.355 ; + RECT 193.35 109.625 193.55 110.355 ; + RECT 193.845 109.625 194.045 110.355 ; + RECT 194.345 109.625 194.545 110.355 ; + RECT 194.845 109.625 195.045 110.355 ; + RECT 195.34 109.625 195.54 110.355 ; + RECT 196.16 109.625 196.36 110.355 ; + RECT 197.295 0.8 198.065 1.57 ; + RECT 197.295 0.3 197.555 13.03 ; + RECT 197.805 0.3 198.065 13.03 ; + RECT 196.655 109.625 196.855 110.355 ; + RECT 197.155 109.625 197.355 110.355 ; + RECT 197.655 109.625 197.855 110.355 ; + RECT 198.15 109.625 198.35 110.355 ; + RECT 198.52 0.52 198.78 2.255 ; + RECT 198.97 109.625 199.17 110.355 ; + RECT 199.465 109.625 199.665 110.355 ; + RECT 199.965 109.625 200.165 110.355 ; + RECT 200.05 0.52 200.31 2.255 ; + RECT 200.465 109.625 200.665 110.355 ; + RECT 200.96 109.625 201.16 110.355 ; + RECT 201.78 109.625 201.98 110.355 ; + RECT 202.275 109.625 202.475 110.355 ; + RECT 202.775 109.625 202.975 110.355 ; + RECT 203.275 109.625 203.475 110.355 ; + RECT 203.77 109.625 203.97 110.355 ; + RECT 203.93 0.52 204.19 1.5 ; + RECT 204.59 109.625 204.79 110.355 ; + RECT 204.795 0.52 205.055 8.085 ; + RECT 205.085 109.625 205.285 110.355 ; + RECT 205.46 0.52 205.72 2.255 ; + RECT 206.325 0.17 207.095 0.43 ; + RECT 206.835 0.17 207.095 11.38 ; + RECT 206.325 0.17 206.585 17.1 ; + RECT 205.585 109.625 205.785 110.355 ; + RECT 206.085 109.625 206.285 110.355 ; + RECT 206.58 109.625 206.78 110.355 ; + RECT 207.4 109.625 207.6 110.355 ; + RECT 207.895 109.625 208.095 110.355 ; + RECT 208.395 109.625 208.595 110.355 ; + RECT 208.895 109.625 209.095 110.355 ; + RECT 209.39 109.625 209.59 110.355 ; + RECT 210.21 109.625 210.41 110.355 ; + RECT 210.705 109.625 210.905 110.355 ; + RECT 211.205 109.625 211.405 110.355 ; + RECT 211.705 109.625 211.905 110.355 ; + RECT 212.2 109.625 212.4 110.355 ; + RECT 213.02 109.625 213.22 110.355 ; + RECT 213.515 109.625 213.715 110.355 ; + RECT 214.015 109.625 214.215 110.355 ; + RECT 214.515 109.625 214.715 110.355 ; + RECT 216.055 0.17 216.825 0.43 ; + RECT 216.055 0.17 216.315 13.055 ; + RECT 216.565 0.17 216.825 13.055 ; + RECT 215.01 109.625 215.21 110.355 ; + RECT 215.83 109.625 216.03 110.355 ; + RECT 216.325 109.625 216.525 110.355 ; + RECT 216.825 109.625 217.025 110.355 ; + RECT 217.325 109.625 217.525 110.355 ; + RECT 217.82 109.625 218.02 110.355 ; + RECT 218.64 109.625 218.84 110.355 ; + RECT 219.775 0.8 220.545 1.57 ; + RECT 219.775 0.3 220.035 13.03 ; + RECT 220.285 0.3 220.545 13.03 ; + RECT 219.135 109.625 219.335 110.355 ; + RECT 219.635 109.625 219.835 110.355 ; + RECT 220.135 109.625 220.335 110.355 ; + RECT 220.63 109.625 220.83 110.355 ; + RECT 221 0.52 221.26 2.255 ; + RECT 221.45 109.625 221.65 110.355 ; + RECT 221.945 109.625 222.145 110.355 ; + RECT 222.445 109.625 222.645 110.355 ; + RECT 222.53 0.52 222.79 2.255 ; + RECT 222.945 109.625 223.145 110.355 ; + RECT 223.44 109.625 223.64 110.355 ; + RECT 224.26 109.625 224.46 110.355 ; + RECT 224.755 109.625 224.955 110.355 ; + RECT 225.255 109.625 225.455 110.355 ; + RECT 225.755 109.625 225.955 110.355 ; + RECT 226.25 109.625 226.45 110.355 ; + RECT 226.41 0.52 226.67 1.5 ; + RECT 227.07 109.625 227.27 110.355 ; + RECT 227.275 0.52 227.535 8.085 ; + RECT 227.565 109.625 227.765 110.355 ; + RECT 227.94 0.52 228.2 2.255 ; + RECT 228.805 0.17 229.575 0.43 ; + RECT 229.315 0.17 229.575 11.38 ; + RECT 228.805 0.17 229.065 17.1 ; + RECT 228.065 109.625 228.265 110.355 ; + RECT 228.565 109.625 228.765 110.355 ; + RECT 229.06 109.625 229.26 110.355 ; + RECT 229.88 109.625 230.08 110.355 ; + RECT 230.375 109.625 230.575 110.355 ; + RECT 230.875 109.625 231.075 110.355 ; + RECT 231.375 109.625 231.575 110.355 ; + RECT 231.87 109.625 232.07 110.355 ; + RECT 232.69 109.625 232.89 110.355 ; + RECT 233.185 109.625 233.385 110.355 ; + RECT 233.685 109.625 233.885 110.355 ; + RECT 234.185 109.625 234.385 110.355 ; + RECT 234.68 109.625 234.88 110.355 ; + RECT 235.5 109.625 235.7 110.355 ; + RECT 236.495 37.065 236.695 110.355 ; + LAYER Metal2 SPACING 0.21 ; + RECT 0 0.52 236.8 110.38 ; + RECT 228.46 0 236.8 110.38 ; + RECT 223.05 0 226.15 110.38 ; + RECT 221.52 0 222.27 110.38 ; + RECT 205.98 0 220.74 110.38 ; + RECT 200.57 0 203.67 110.38 ; + RECT 199.04 0 199.79 110.38 ; + RECT 183.5 0 198.26 110.38 ; + RECT 178.09 0 181.19 110.38 ; + RECT 176.56 0 177.31 110.38 ; + RECT 161.02 0 175.78 110.38 ; + RECT 155.61 0 158.71 110.38 ; + RECT 154.08 0 154.83 110.38 ; + RECT 135 0.17 153.3 110.38 ; + RECT 135.01 0 153.3 110.38 ; + RECT 125.31 0 134.23 110.38 ; + RECT 119.71 0 120.97 110.38 ; + RECT 118.18 0 118.42 110.38 ; + RECT 116.65 0 116.89 110.38 ; + RECT 113.59 0 113.83 110.38 ; + RECT 112.06 0 112.3 110.38 ; + RECT 104.4 0 110.77 110.38 ; + RECT 101.85 0 102.11 110.38 ; + RECT 100.33 0 101.08 110.38 ; + RECT 83.5 0 99.56 110.38 ; + RECT 81.97 0 82.72 110.38 ; + RECT 78.09 0 81.19 110.38 ; + RECT 61.02 0 75.78 110.38 ; + RECT 59.49 0 60.24 110.38 ; + RECT 55.61 0 58.71 110.38 ; + RECT 38.54 0 53.3 110.38 ; + RECT 37.01 0 37.76 110.38 ; + RECT 33.13 0 36.23 110.38 ; + RECT 16.06 0 30.82 110.38 ; + RECT 14.53 0 15.28 110.38 ; + RECT 10.65 0 13.75 110.38 ; + RECT 0 0 8.34 110.38 ; + LAYER Metal3 ; + RECT 0 0 236.8 110.38 ; + LAYER Metal4 SPACING 0.21 ; + RECT 138.09 0 145.17 110.38 ; + RECT 132.94 0 134.76 110.38 ; + RECT 127.79 0 129.61 110.38 ; + RECT 232.8 0 236.8 110.38 ; + RECT 227.18 0 229.47 110.38 ; + RECT 227.18 30.685 236.8 36.805 ; + RECT 221.56 0 223.85 110.38 ; + RECT 215.94 0 218.23 110.38 ; + RECT 215.94 30.685 223.85 36.805 ; + RECT 210.32 0 212.61 110.38 ; + RECT 204.7 0 206.99 110.38 ; + RECT 204.7 30.685 212.61 36.805 ; + RECT 199.08 0 201.37 110.38 ; + RECT 193.46 0 195.75 110.38 ; + RECT 193.46 30.685 201.37 36.805 ; + RECT 187.84 0 190.13 110.38 ; + RECT 46.67 30.685 54.58 36.805 ; + RECT 41.05 0 43.34 110.38 ; + RECT 35.43 0 37.72 110.38 ; + RECT 35.43 30.685 43.34 36.805 ; + RECT 29.81 0 32.1 110.38 ; + RECT 24.19 0 26.48 110.38 ; + RECT 24.19 30.685 32.1 36.805 ; + RECT 18.57 0 20.86 110.38 ; + RECT 12.95 0 15.24 110.38 ; + RECT 12.95 30.685 20.86 36.805 ; + RECT 7.33 0 9.62 110.38 ; + RECT 0 0 4 110.38 ; + RECT 0 30.685 9.62 36.805 ; + RECT 182.22 0 184.51 110.38 ; + RECT 182.22 30.685 190.13 36.805 ; + RECT 176.6 0 178.89 110.38 ; + RECT 170.98 0 173.27 110.38 ; + RECT 170.98 30.685 178.89 36.805 ; + RECT 165.36 0 167.65 110.38 ; + RECT 159.74 0 162.03 110.38 ; + RECT 159.74 30.685 167.65 36.805 ; + RECT 154.12 0 156.41 110.38 ; + RECT 148.5 0 150.79 110.38 ; + RECT 148.5 30.685 156.41 36.805 ; + RECT 122.64 0 124.46 110.38 ; + RECT 117.49 0 119.31 110.38 ; + RECT 112.34 0 114.16 110.38 ; + RECT 107.19 0 109.01 110.38 ; + RECT 102.04 0 103.86 110.38 ; + RECT 91.63 0 98.71 110.38 ; + RECT 86.01 0 88.3 110.38 ; + RECT 80.39 0 82.68 110.38 ; + RECT 80.39 30.685 88.3 36.805 ; + RECT 74.77 0 77.06 110.38 ; + RECT 69.15 0 71.44 110.38 ; + RECT 69.15 30.685 77.06 36.805 ; + RECT 63.53 0 65.82 110.38 ; + RECT 57.91 0 60.2 110.38 ; + RECT 57.91 30.685 65.82 36.805 ; + RECT 52.29 0 54.58 110.38 ; + RECT 46.67 0 48.96 110.38 ; + END +END RM_IHPSG13_1P_512x8_c3_bm_bist + +END LIBRARY diff --git a/flow/platforms/ihp-sg13g2/lef/RM_IHPSG13_1P_8192x32_c4.lef b/flow/platforms/ihp-sg13g2/lef/RM_IHPSG13_1P_8192x32_c4.lef new file mode 100644 index 0000000000..a08f1bc1ba --- /dev/null +++ b/flow/platforms/ihp-sg13g2/lef/RM_IHPSG13_1P_8192x32_c4.lef @@ -0,0 +1,6422 @@ +# ------------------------------------------------------ +# +# Copyright 2023 IHP PDK Authors +# +# Licensed under the Apache License, Version 2.0 (the "License"); +# you may not use this file except in compliance with the License. +# You may obtain a copy of the License at +# +# https://www.apache.org/licenses/LICENSE-2.0 +# +# Unless required by applicable law or agreed to in writing, software +# distributed under the License is distributed on an "AS IS" BASIS, +# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +# See the License for the specific language governing permissions and +# limitations under the License. +# +# Generated on Mon Apr 7 14:15:46 2025 +# +# ------------------------------------------------------ +VERSION 5.7 ; +BUSBITCHARS "[]" ; +DIVIDERCHAR "/" ; + +MACRO RM_IHPSG13_1P_8192x32_c4 + CLASS BLOCK ; + ORIGIN 0 0 ; + FOREIGN RM_IHPSG13_1P_8192x32_c4 0 0 ; + SIZE 1520.16 BY 618.3 ; + SYMMETRY X Y R90 ; + PIN A_DIN[16] + DIRECTION INPUT ; + USE SIGNAL ; + ANTENNAPARTIALMETALAREA 2.8847 LAYER Metal2 ; + ANTENNAMODEL OXIDE1 ; + ANTENNAGATEAREA 0.20085 LAYER Metal2 ; + ANTENNAMAXAREACAR 15.268608 LAYER Metal2 ; + PORT + LAYER Metal2 ; + RECT 803.71 0 803.97 0.26 ; + END + END A_DIN[16] + PIN A_DIN[15] + DIRECTION INPUT ; + USE SIGNAL ; + ANTENNAPARTIALMETALAREA 2.8847 LAYER Metal2 ; + ANTENNAMODEL OXIDE1 ; + ANTENNAGATEAREA 0.20085 LAYER Metal2 ; + ANTENNAMAXAREACAR 15.268608 LAYER Metal2 ; + PORT + LAYER Metal2 ; + RECT 716.19 0 716.45 0.26 ; + END + END A_DIN[15] + PIN A_DOUT[16] + DIRECTION OUTPUT ; + USE SIGNAL ; + ANTENNAPARTIALMETALAREA 1.5834 LAYER Metal2 ; + ANTENNADIFFAREA 0.988 LAYER Metal2 ; + PORT + LAYER Metal2 ; + RECT 825.485 0 825.745 0.26 ; + END + END A_DOUT[16] + PIN A_DOUT[15] + DIRECTION OUTPUT ; + USE SIGNAL ; + ANTENNAPARTIALMETALAREA 1.5834 LAYER Metal2 ; + ANTENNADIFFAREA 0.988 LAYER Metal2 ; + PORT + LAYER Metal2 ; + RECT 694.415 0 694.675 0.26 ; + END + END A_DOUT[15] + PIN VSS! + DIRECTION INOUT ; + USE GROUND ; + NETEXPR "vss VSS!" ; + PORT + LAYER Metal4 ; + RECT 1496.23 0 1499.04 618.3 ; + END + PORT + LAYER Metal4 ; + RECT 1484.99 0 1487.8 618.3 ; + END + PORT + LAYER Metal4 ; + RECT 1473.75 0 1476.56 618.3 ; + END + PORT + LAYER Metal4 ; + RECT 1451.27 0 1454.08 618.3 ; + END + PORT + LAYER Metal4 ; + RECT 1440.03 0 1442.84 618.3 ; + END + PORT + LAYER Metal4 ; + RECT 1428.79 0 1431.6 618.3 ; + END + PORT + LAYER Metal4 ; + RECT 1406.31 0 1409.12 618.3 ; + END + PORT + LAYER Metal4 ; + RECT 1395.07 0 1397.88 618.3 ; + END + PORT + LAYER Metal4 ; + RECT 1383.83 0 1386.64 618.3 ; + END + PORT + LAYER Metal4 ; + RECT 1361.35 0 1364.16 618.3 ; + END + PORT + LAYER Metal4 ; + RECT 1350.11 0 1352.92 618.3 ; + END + PORT + LAYER Metal4 ; + RECT 1338.87 0 1341.68 618.3 ; + END + PORT + LAYER Metal4 ; + RECT 1316.39 0 1319.2 618.3 ; + END + PORT + LAYER Metal4 ; + RECT 1305.15 0 1307.96 618.3 ; + END + PORT + LAYER Metal4 ; + RECT 1293.91 0 1296.72 618.3 ; + END + PORT + LAYER Metal4 ; + RECT 1271.43 0 1274.24 618.3 ; + END + PORT + LAYER Metal4 ; + RECT 1260.19 0 1263 618.3 ; + END + PORT + LAYER Metal4 ; + RECT 1248.95 0 1251.76 618.3 ; + END + PORT + LAYER Metal4 ; + RECT 1226.47 0 1229.28 618.3 ; + END + PORT + LAYER Metal4 ; + RECT 1215.23 0 1218.04 618.3 ; + END + PORT + LAYER Metal4 ; + RECT 1203.99 0 1206.8 618.3 ; + END + PORT + LAYER Metal4 ; + RECT 1181.51 0 1184.32 618.3 ; + END + PORT + LAYER Metal4 ; + RECT 1170.27 0 1173.08 618.3 ; + END + PORT + LAYER Metal4 ; + RECT 1159.03 0 1161.84 618.3 ; + END + PORT + LAYER Metal4 ; + RECT 1136.55 0 1139.36 618.3 ; + END + PORT + LAYER Metal4 ; + RECT 1125.31 0 1128.12 618.3 ; + END + PORT + LAYER Metal4 ; + RECT 1114.07 0 1116.88 618.3 ; + END + PORT + LAYER Metal4 ; + RECT 1091.59 0 1094.4 618.3 ; + END + PORT + LAYER Metal4 ; + RECT 1080.35 0 1083.16 618.3 ; + END + PORT + LAYER Metal4 ; + RECT 1069.11 0 1071.92 618.3 ; + END + PORT + LAYER Metal4 ; + RECT 1046.63 0 1049.44 618.3 ; + END + PORT + LAYER Metal4 ; + RECT 1035.39 0 1038.2 618.3 ; + END + PORT + LAYER Metal4 ; + RECT 1024.15 0 1026.96 618.3 ; + END + PORT + LAYER Metal4 ; + RECT 1001.67 0 1004.48 618.3 ; + END + PORT + LAYER Metal4 ; + RECT 990.43 0 993.24 618.3 ; + END + PORT + LAYER Metal4 ; + RECT 979.19 0 982 618.3 ; + END + PORT + LAYER Metal4 ; + RECT 956.71 0 959.52 618.3 ; + END + PORT + LAYER Metal4 ; + RECT 945.47 0 948.28 618.3 ; + END + PORT + LAYER Metal4 ; + RECT 934.23 0 937.04 618.3 ; + END + PORT + LAYER Metal4 ; + RECT 911.75 0 914.56 618.3 ; + END + PORT + LAYER Metal4 ; + RECT 900.51 0 903.32 618.3 ; + END + PORT + LAYER Metal4 ; + RECT 889.27 0 892.08 618.3 ; + END + PORT + LAYER Metal4 ; + RECT 866.79 0 869.6 618.3 ; + END + PORT + LAYER Metal4 ; + RECT 855.55 0 858.36 618.3 ; + END + PORT + LAYER Metal4 ; + RECT 844.31 0 847.12 618.3 ; + END + PORT + LAYER Metal4 ; + RECT 821.83 0 824.64 618.3 ; + END + PORT + LAYER Metal4 ; + RECT 810.59 0 813.4 618.3 ; + END + PORT + LAYER Metal4 ; + RECT 799.35 0 802.16 618.3 ; + END + PORT + LAYER Metal4 ; + RECT 776.7 0 779.51 618.3 ; + END + PORT + LAYER Metal4 ; + RECT 766.4 0 769.21 618.3 ; + END + PORT + LAYER Metal4 ; + RECT 750.95 0 753.76 618.3 ; + END + PORT + LAYER Metal4 ; + RECT 740.65 0 743.46 618.3 ; + END + PORT + LAYER Metal4 ; + RECT 718 0 720.81 618.3 ; + END + PORT + LAYER Metal4 ; + RECT 706.76 0 709.57 618.3 ; + END + PORT + LAYER Metal4 ; + RECT 695.52 0 698.33 618.3 ; + END + PORT + LAYER Metal4 ; + RECT 673.04 0 675.85 618.3 ; + END + PORT + LAYER Metal4 ; + RECT 661.8 0 664.61 618.3 ; + END + PORT + LAYER Metal4 ; + RECT 650.56 0 653.37 618.3 ; + END + PORT + LAYER Metal4 ; + RECT 628.08 0 630.89 618.3 ; + END + PORT + LAYER Metal4 ; + RECT 616.84 0 619.65 618.3 ; + END + PORT + LAYER Metal4 ; + RECT 605.6 0 608.41 618.3 ; + END + PORT + LAYER Metal4 ; + RECT 583.12 0 585.93 618.3 ; + END + PORT + LAYER Metal4 ; + RECT 571.88 0 574.69 618.3 ; + END + PORT + LAYER Metal4 ; + RECT 560.64 0 563.45 618.3 ; + END + PORT + LAYER Metal4 ; + RECT 538.16 0 540.97 618.3 ; + END + PORT + LAYER Metal4 ; + RECT 526.92 0 529.73 618.3 ; + END + PORT + LAYER Metal4 ; + RECT 515.68 0 518.49 618.3 ; + END + PORT + LAYER Metal4 ; + RECT 493.2 0 496.01 618.3 ; + END + PORT + LAYER Metal4 ; + RECT 481.96 0 484.77 618.3 ; + END + PORT + LAYER Metal4 ; + RECT 470.72 0 473.53 618.3 ; + END + PORT + LAYER Metal4 ; + RECT 448.24 0 451.05 618.3 ; + END + PORT + LAYER Metal4 ; + RECT 437 0 439.81 618.3 ; + END + PORT + LAYER Metal4 ; + RECT 425.76 0 428.57 618.3 ; + END + PORT + LAYER Metal4 ; + RECT 403.28 0 406.09 618.3 ; + END + PORT + LAYER Metal4 ; + RECT 392.04 0 394.85 618.3 ; + END + PORT + LAYER Metal4 ; + RECT 380.8 0 383.61 618.3 ; + END + PORT + LAYER Metal4 ; + RECT 358.32 0 361.13 618.3 ; + END + PORT + LAYER Metal4 ; + RECT 347.08 0 349.89 618.3 ; + END + PORT + LAYER Metal4 ; + RECT 335.84 0 338.65 618.3 ; + END + PORT + LAYER Metal4 ; + RECT 313.36 0 316.17 618.3 ; + END + PORT + LAYER Metal4 ; + RECT 302.12 0 304.93 618.3 ; + END + PORT + LAYER Metal4 ; + RECT 290.88 0 293.69 618.3 ; + END + PORT + LAYER Metal4 ; + RECT 268.4 0 271.21 618.3 ; + END + PORT + LAYER Metal4 ; + RECT 257.16 0 259.97 618.3 ; + END + PORT + LAYER Metal4 ; + RECT 245.92 0 248.73 618.3 ; + END + PORT + LAYER Metal4 ; + RECT 223.44 0 226.25 618.3 ; + END + PORT + LAYER Metal4 ; + RECT 212.2 0 215.01 618.3 ; + END + PORT + LAYER Metal4 ; + RECT 200.96 0 203.77 618.3 ; + END + PORT + LAYER Metal4 ; + RECT 178.48 0 181.29 618.3 ; + END + PORT + LAYER Metal4 ; + RECT 167.24 0 170.05 618.3 ; + END + PORT + LAYER Metal4 ; + RECT 156 0 158.81 618.3 ; + END + PORT + LAYER Metal4 ; + RECT 133.52 0 136.33 618.3 ; + END + PORT + LAYER Metal4 ; + RECT 122.28 0 125.09 618.3 ; + END + PORT + LAYER Metal4 ; + RECT 111.04 0 113.85 618.3 ; + END + PORT + LAYER Metal4 ; + RECT 88.56 0 91.37 618.3 ; + END + PORT + LAYER Metal4 ; + RECT 77.32 0 80.13 618.3 ; + END + PORT + LAYER Metal4 ; + RECT 66.08 0 68.89 618.3 ; + END + PORT + LAYER Metal4 ; + RECT 43.6 0 46.41 618.3 ; + END + PORT + LAYER Metal4 ; + RECT 32.36 0 35.17 618.3 ; + END + PORT + LAYER Metal4 ; + RECT 21.12 0 23.93 618.3 ; + END + END VSS! + PIN VDD! + DIRECTION INOUT ; + USE POWER ; + NETEXPR "vdd VDD!" ; + PORT + LAYER Metal4 ; + RECT 1501.85 0 1504.66 30.425 ; + END + PORT + LAYER Metal4 ; + RECT 1490.61 0 1493.42 30.425 ; + END + PORT + LAYER Metal4 ; + RECT 1479.37 0 1482.18 30.425 ; + END + PORT + LAYER Metal4 ; + RECT 1456.89 0 1459.7 30.425 ; + END + PORT + LAYER Metal4 ; + RECT 1445.65 0 1448.46 30.425 ; + END + PORT + LAYER Metal4 ; + RECT 1434.41 0 1437.22 30.425 ; + END + PORT + LAYER Metal4 ; + RECT 1411.93 0 1414.74 30.425 ; + END + PORT + LAYER Metal4 ; + RECT 1400.69 0 1403.5 30.425 ; + END + PORT + LAYER Metal4 ; + RECT 1389.45 0 1392.26 30.425 ; + END + PORT + LAYER Metal4 ; + RECT 1366.97 0 1369.78 30.425 ; + END + PORT + LAYER Metal4 ; + RECT 1355.73 0 1358.54 30.425 ; + END + PORT + LAYER Metal4 ; + RECT 1344.49 0 1347.3 30.425 ; + END + PORT + LAYER Metal4 ; + RECT 1322.01 0 1324.82 30.425 ; + END + PORT + LAYER Metal4 ; + RECT 1310.77 0 1313.58 30.425 ; + END + PORT + LAYER Metal4 ; + RECT 1299.53 0 1302.34 30.425 ; + END + PORT + LAYER Metal4 ; + RECT 1277.05 0 1279.86 30.425 ; + END + PORT + LAYER Metal4 ; + RECT 1265.81 0 1268.62 30.425 ; + END + PORT + LAYER Metal4 ; + RECT 1254.57 0 1257.38 30.425 ; + END + PORT + LAYER Metal4 ; + RECT 1232.09 0 1234.9 30.425 ; + END + PORT + LAYER Metal4 ; + RECT 1220.85 0 1223.66 30.425 ; + END + PORT + LAYER Metal4 ; + RECT 1209.61 0 1212.42 30.425 ; + END + PORT + LAYER Metal4 ; + RECT 1187.13 0 1189.94 30.425 ; + END + PORT + LAYER Metal4 ; + RECT 1175.89 0 1178.7 30.425 ; + END + PORT + LAYER Metal4 ; + RECT 1164.65 0 1167.46 30.425 ; + END + PORT + LAYER Metal4 ; + RECT 1142.17 0 1144.98 30.425 ; + END + PORT + LAYER Metal4 ; + RECT 1130.93 0 1133.74 30.425 ; + END + PORT + LAYER Metal4 ; + RECT 1119.69 0 1122.5 30.425 ; + END + PORT + LAYER Metal4 ; + RECT 1097.21 0 1100.02 30.425 ; + END + PORT + LAYER Metal4 ; + RECT 1085.97 0 1088.78 30.425 ; + END + PORT + LAYER Metal4 ; + RECT 1074.73 0 1077.54 30.425 ; + END + PORT + LAYER Metal4 ; + RECT 1052.25 0 1055.06 30.425 ; + END + PORT + LAYER Metal4 ; + RECT 1041.01 0 1043.82 30.425 ; + END + PORT + LAYER Metal4 ; + RECT 1029.77 0 1032.58 30.425 ; + END + PORT + LAYER Metal4 ; + RECT 1007.29 0 1010.1 30.425 ; + END + PORT + LAYER Metal4 ; + RECT 996.05 0 998.86 30.425 ; + END + PORT + LAYER Metal4 ; + RECT 984.81 0 987.62 30.425 ; + END + PORT + LAYER Metal4 ; + RECT 962.33 0 965.14 30.425 ; + END + PORT + LAYER Metal4 ; + RECT 951.09 0 953.9 30.425 ; + END + PORT + LAYER Metal4 ; + RECT 939.85 0 942.66 30.425 ; + END + PORT + LAYER Metal4 ; + RECT 917.37 0 920.18 30.425 ; + END + PORT + LAYER Metal4 ; + RECT 906.13 0 908.94 30.425 ; + END + PORT + LAYER Metal4 ; + RECT 894.89 0 897.7 30.425 ; + END + PORT + LAYER Metal4 ; + RECT 872.41 0 875.22 30.425 ; + END + PORT + LAYER Metal4 ; + RECT 861.17 0 863.98 30.425 ; + END + PORT + LAYER Metal4 ; + RECT 849.93 0 852.74 30.425 ; + END + PORT + LAYER Metal4 ; + RECT 827.45 0 830.26 30.425 ; + END + PORT + LAYER Metal4 ; + RECT 816.21 0 819.02 30.425 ; + END + PORT + LAYER Metal4 ; + RECT 804.97 0 807.78 30.425 ; + END + PORT + LAYER Metal4 ; + RECT 771.55 0 774.36 618.3 ; + END + PORT + LAYER Metal4 ; + RECT 761.25 0 764.06 618.3 ; + END + PORT + LAYER Metal4 ; + RECT 756.1 0 758.91 618.3 ; + END + PORT + LAYER Metal4 ; + RECT 745.8 0 748.61 618.3 ; + END + PORT + LAYER Metal4 ; + RECT 712.38 0 715.19 30.425 ; + END + PORT + LAYER Metal4 ; + RECT 701.14 0 703.95 30.425 ; + END + PORT + LAYER Metal4 ; + RECT 689.9 0 692.71 30.425 ; + END + PORT + LAYER Metal4 ; + RECT 667.42 0 670.23 30.425 ; + END + PORT + LAYER Metal4 ; + RECT 656.18 0 658.99 30.425 ; + END + PORT + LAYER Metal4 ; + RECT 644.94 0 647.75 30.425 ; + END + PORT + LAYER Metal4 ; + RECT 622.46 0 625.27 30.425 ; + END + PORT + LAYER Metal4 ; + RECT 611.22 0 614.03 30.425 ; + END + PORT + LAYER Metal4 ; + RECT 599.98 0 602.79 30.425 ; + END + PORT + LAYER Metal4 ; + RECT 577.5 0 580.31 30.425 ; + END + PORT + LAYER Metal4 ; + RECT 566.26 0 569.07 30.425 ; + END + PORT + LAYER Metal4 ; + RECT 555.02 0 557.83 30.425 ; + END + PORT + LAYER Metal4 ; + RECT 532.54 0 535.35 30.425 ; + END + PORT + LAYER Metal4 ; + RECT 521.3 0 524.11 30.425 ; + END + PORT + LAYER Metal4 ; + RECT 510.06 0 512.87 30.425 ; + END + PORT + LAYER Metal4 ; + RECT 487.58 0 490.39 30.425 ; + END + PORT + LAYER Metal4 ; + RECT 476.34 0 479.15 30.425 ; + END + PORT + LAYER Metal4 ; + RECT 465.1 0 467.91 30.425 ; + END + PORT + LAYER Metal4 ; + RECT 442.62 0 445.43 30.425 ; + END + PORT + LAYER Metal4 ; + RECT 431.38 0 434.19 30.425 ; + END + PORT + LAYER Metal4 ; + RECT 420.14 0 422.95 30.425 ; + END + PORT + LAYER Metal4 ; + RECT 397.66 0 400.47 30.425 ; + END + PORT + LAYER Metal4 ; + RECT 386.42 0 389.23 30.425 ; + END + PORT + LAYER Metal4 ; + RECT 375.18 0 377.99 30.425 ; + END + PORT + LAYER Metal4 ; + RECT 352.7 0 355.51 30.425 ; + END + PORT + LAYER Metal4 ; + RECT 341.46 0 344.27 30.425 ; + END + PORT + LAYER Metal4 ; + RECT 330.22 0 333.03 30.425 ; + END + PORT + LAYER Metal4 ; + RECT 307.74 0 310.55 30.425 ; + END + PORT + LAYER Metal4 ; + RECT 296.5 0 299.31 30.425 ; + END + PORT + LAYER Metal4 ; + RECT 285.26 0 288.07 30.425 ; + END + PORT + LAYER Metal4 ; + RECT 262.78 0 265.59 30.425 ; + END + PORT + LAYER Metal4 ; + RECT 251.54 0 254.35 30.425 ; + END + PORT + LAYER Metal4 ; + RECT 240.3 0 243.11 30.425 ; + END + PORT + LAYER Metal4 ; + RECT 217.82 0 220.63 30.425 ; + END + PORT + LAYER Metal4 ; + RECT 206.58 0 209.39 30.425 ; + END + PORT + LAYER Metal4 ; + RECT 195.34 0 198.15 30.425 ; + END + PORT + LAYER Metal4 ; + RECT 172.86 0 175.67 30.425 ; + END + PORT + LAYER Metal4 ; + RECT 161.62 0 164.43 30.425 ; + END + PORT + LAYER Metal4 ; + RECT 150.38 0 153.19 30.425 ; + END + PORT + LAYER Metal4 ; + RECT 127.9 0 130.71 30.425 ; + END + PORT + LAYER Metal4 ; + RECT 116.66 0 119.47 30.425 ; + END + PORT + LAYER Metal4 ; + RECT 105.42 0 108.23 30.425 ; + END + PORT + LAYER Metal4 ; + RECT 82.94 0 85.75 30.425 ; + END + PORT + LAYER Metal4 ; + RECT 71.7 0 74.51 30.425 ; + END + PORT + LAYER Metal4 ; + RECT 60.46 0 63.27 30.425 ; + END + PORT + LAYER Metal4 ; + RECT 37.98 0 40.79 30.425 ; + END + PORT + LAYER Metal4 ; + RECT 26.74 0 29.55 30.425 ; + END + PORT + LAYER Metal4 ; + RECT 15.5 0 18.31 30.425 ; + END + END VDD! + PIN VDDARRAY! + DIRECTION INOUT ; + USE POWER ; + NETEXPR "vddarray VDDARRAY!" ; + PORT + LAYER Metal4 ; + RECT 1501.85 37.065 1504.66 618.3 ; + END + PORT + LAYER Metal4 ; + RECT 1490.61 37.065 1493.42 618.3 ; + END + PORT + LAYER Metal4 ; + RECT 1479.37 37.065 1482.18 618.3 ; + END + PORT + LAYER Metal4 ; + RECT 1456.89 37.065 1459.7 618.3 ; + END + PORT + LAYER Metal4 ; + RECT 1445.65 37.065 1448.46 618.3 ; + END + PORT + LAYER Metal4 ; + RECT 1434.41 37.065 1437.22 618.3 ; + END + PORT + LAYER Metal4 ; + RECT 1411.93 37.065 1414.74 618.3 ; + END + PORT + LAYER Metal4 ; + RECT 1400.69 37.065 1403.5 618.3 ; + END + PORT + LAYER Metal4 ; + RECT 1389.45 37.065 1392.26 618.3 ; + END + PORT + LAYER Metal4 ; + RECT 1366.97 37.065 1369.78 618.3 ; + END + PORT + LAYER Metal4 ; + RECT 1355.73 37.065 1358.54 618.3 ; + END + PORT + LAYER Metal4 ; + RECT 1344.49 37.065 1347.3 618.3 ; + END + PORT + LAYER Metal4 ; + RECT 1322.01 37.065 1324.82 618.3 ; + END + PORT + LAYER Metal4 ; + RECT 1310.77 37.065 1313.58 618.3 ; + END + PORT + LAYER Metal4 ; + RECT 1299.53 37.065 1302.34 618.3 ; + END + PORT + LAYER Metal4 ; + RECT 1277.05 37.065 1279.86 618.3 ; + END + PORT + LAYER Metal4 ; + RECT 1265.81 37.065 1268.62 618.3 ; + END + PORT + LAYER Metal4 ; + RECT 1254.57 37.065 1257.38 618.3 ; + END + PORT + LAYER Metal4 ; + RECT 1232.09 37.065 1234.9 618.3 ; + END + PORT + LAYER Metal4 ; + RECT 1220.85 37.065 1223.66 618.3 ; + END + PORT + LAYER Metal4 ; + RECT 1209.61 37.065 1212.42 618.3 ; + END + PORT + LAYER Metal4 ; + RECT 1187.13 37.065 1189.94 618.3 ; + END + PORT + LAYER Metal4 ; + RECT 1175.89 37.065 1178.7 618.3 ; + END + PORT + LAYER Metal4 ; + RECT 1164.65 37.065 1167.46 618.3 ; + END + PORT + LAYER Metal4 ; + RECT 1142.17 37.065 1144.98 618.3 ; + END + PORT + LAYER Metal4 ; + RECT 1130.93 37.065 1133.74 618.3 ; + END + PORT + LAYER Metal4 ; + RECT 1119.69 37.065 1122.5 618.3 ; + END + PORT + LAYER Metal4 ; + RECT 1097.21 37.065 1100.02 618.3 ; + END + PORT + LAYER Metal4 ; + RECT 1085.97 37.065 1088.78 618.3 ; + END + PORT + LAYER Metal4 ; + RECT 1074.73 37.065 1077.54 618.3 ; + END + PORT + LAYER Metal4 ; + RECT 1052.25 37.065 1055.06 618.3 ; + END + PORT + LAYER Metal4 ; + RECT 1041.01 37.065 1043.82 618.3 ; + END + PORT + LAYER Metal4 ; + RECT 1029.77 37.065 1032.58 618.3 ; + END + PORT + LAYER Metal4 ; + RECT 1007.29 37.065 1010.1 618.3 ; + END + PORT + LAYER Metal4 ; + RECT 996.05 37.065 998.86 618.3 ; + END + PORT + LAYER Metal4 ; + RECT 984.81 37.065 987.62 618.3 ; + END + PORT + LAYER Metal4 ; + RECT 962.33 37.065 965.14 618.3 ; + END + PORT + LAYER Metal4 ; + RECT 951.09 37.065 953.9 618.3 ; + END + PORT + LAYER Metal4 ; + RECT 939.85 37.065 942.66 618.3 ; + END + PORT + LAYER Metal4 ; + RECT 917.37 37.065 920.18 618.3 ; + END + PORT + LAYER Metal4 ; + RECT 906.13 37.065 908.94 618.3 ; + END + PORT + LAYER Metal4 ; + RECT 894.89 37.065 897.7 618.3 ; + END + PORT + LAYER Metal4 ; + RECT 872.41 37.065 875.22 618.3 ; + END + PORT + LAYER Metal4 ; + RECT 861.17 37.065 863.98 618.3 ; + END + PORT + LAYER Metal4 ; + RECT 849.93 37.065 852.74 618.3 ; + END + PORT + LAYER Metal4 ; + RECT 827.45 37.065 830.26 618.3 ; + END + PORT + LAYER Metal4 ; + RECT 816.21 37.065 819.02 618.3 ; + END + PORT + LAYER Metal4 ; + RECT 804.97 37.065 807.78 618.3 ; + END + PORT + LAYER Metal4 ; + RECT 712.38 37.065 715.19 618.3 ; + END + PORT + LAYER Metal4 ; + RECT 701.14 37.065 703.95 618.3 ; + END + PORT + LAYER Metal4 ; + RECT 689.9 37.065 692.71 618.3 ; + END + PORT + LAYER Metal4 ; + RECT 667.42 37.065 670.23 618.3 ; + END + PORT + LAYER Metal4 ; + RECT 656.18 37.065 658.99 618.3 ; + END + PORT + LAYER Metal4 ; + RECT 644.94 37.065 647.75 618.3 ; + END + PORT + LAYER Metal4 ; + RECT 622.46 37.065 625.27 618.3 ; + END + PORT + LAYER Metal4 ; + RECT 611.22 37.065 614.03 618.3 ; + END + PORT + LAYER Metal4 ; + RECT 599.98 37.065 602.79 618.3 ; + END + PORT + LAYER Metal4 ; + RECT 577.5 37.065 580.31 618.3 ; + END + PORT + LAYER Metal4 ; + RECT 566.26 37.065 569.07 618.3 ; + END + PORT + LAYER Metal4 ; + RECT 555.02 37.065 557.83 618.3 ; + END + PORT + LAYER Metal4 ; + RECT 532.54 37.065 535.35 618.3 ; + END + PORT + LAYER Metal4 ; + RECT 521.3 37.065 524.11 618.3 ; + END + PORT + LAYER Metal4 ; + RECT 510.06 37.065 512.87 618.3 ; + END + PORT + LAYER Metal4 ; + RECT 487.58 37.065 490.39 618.3 ; + END + PORT + LAYER Metal4 ; + RECT 476.34 37.065 479.15 618.3 ; + END + PORT + LAYER Metal4 ; + RECT 465.1 37.065 467.91 618.3 ; + END + PORT + LAYER Metal4 ; + RECT 442.62 37.065 445.43 618.3 ; + END + PORT + LAYER Metal4 ; + RECT 431.38 37.065 434.19 618.3 ; + END + PORT + LAYER Metal4 ; + RECT 420.14 37.065 422.95 618.3 ; + END + PORT + LAYER Metal4 ; + RECT 397.66 37.065 400.47 618.3 ; + END + PORT + LAYER Metal4 ; + RECT 386.42 37.065 389.23 618.3 ; + END + PORT + LAYER Metal4 ; + RECT 375.18 37.065 377.99 618.3 ; + END + PORT + LAYER Metal4 ; + RECT 352.7 37.065 355.51 618.3 ; + END + PORT + LAYER Metal4 ; + RECT 341.46 37.065 344.27 618.3 ; + END + PORT + LAYER Metal4 ; + RECT 330.22 37.065 333.03 618.3 ; + END + PORT + LAYER Metal4 ; + RECT 307.74 37.065 310.55 618.3 ; + END + PORT + LAYER Metal4 ; + RECT 296.5 37.065 299.31 618.3 ; + END + PORT + LAYER Metal4 ; + RECT 285.26 37.065 288.07 618.3 ; + END + PORT + LAYER Metal4 ; + RECT 262.78 37.065 265.59 618.3 ; + END + PORT + LAYER Metal4 ; + RECT 251.54 37.065 254.35 618.3 ; + END + PORT + LAYER Metal4 ; + RECT 240.3 37.065 243.11 618.3 ; + END + PORT + LAYER Metal4 ; + RECT 217.82 37.065 220.63 618.3 ; + END + PORT + LAYER Metal4 ; + RECT 206.58 37.065 209.39 618.3 ; + END + PORT + LAYER Metal4 ; + RECT 195.34 37.065 198.15 618.3 ; + END + PORT + LAYER Metal4 ; + RECT 172.86 37.065 175.67 618.3 ; + END + PORT + LAYER Metal4 ; + RECT 161.62 37.065 164.43 618.3 ; + END + PORT + LAYER Metal4 ; + RECT 150.38 37.065 153.19 618.3 ; + END + PORT + LAYER Metal4 ; + RECT 127.9 37.065 130.71 618.3 ; + END + PORT + LAYER Metal4 ; + RECT 116.66 37.065 119.47 618.3 ; + END + PORT + LAYER Metal4 ; + RECT 105.42 37.065 108.23 618.3 ; + END + PORT + LAYER Metal4 ; + RECT 82.94 37.065 85.75 618.3 ; + END + PORT + LAYER Metal4 ; + RECT 71.7 37.065 74.51 618.3 ; + END + PORT + LAYER Metal4 ; + RECT 60.46 37.065 63.27 618.3 ; + END + PORT + LAYER Metal4 ; + RECT 37.98 37.065 40.79 618.3 ; + END + PORT + LAYER Metal4 ; + RECT 26.74 37.065 29.55 618.3 ; + END + PORT + LAYER Metal4 ; + RECT 15.5 37.065 18.31 618.3 ; + END + END VDDARRAY! + PIN A_DIN[17] + DIRECTION INPUT ; + USE SIGNAL ; + ANTENNAPARTIALMETALAREA 2.8847 LAYER Metal2 ; + ANTENNAMODEL OXIDE1 ; + ANTENNAGATEAREA 0.20085 LAYER Metal2 ; + ANTENNAMAXAREACAR 15.268608 LAYER Metal2 ; + PORT + LAYER Metal2 ; + RECT 848.67 0 848.93 0.26 ; + END + END A_DIN[17] + PIN A_DIN[14] + DIRECTION INPUT ; + USE SIGNAL ; + ANTENNAPARTIALMETALAREA 2.8847 LAYER Metal2 ; + ANTENNAMODEL OXIDE1 ; + ANTENNAGATEAREA 0.20085 LAYER Metal2 ; + ANTENNAMAXAREACAR 15.268608 LAYER Metal2 ; + PORT + LAYER Metal2 ; + RECT 671.23 0 671.49 0.26 ; + END + END A_DIN[14] + PIN A_DOUT[17] + DIRECTION OUTPUT ; + USE SIGNAL ; + ANTENNAPARTIALMETALAREA 1.5834 LAYER Metal2 ; + ANTENNADIFFAREA 0.988 LAYER Metal2 ; + PORT + LAYER Metal2 ; + RECT 870.445 0 870.705 0.26 ; + END + END A_DOUT[17] + PIN A_DOUT[14] + DIRECTION OUTPUT ; + USE SIGNAL ; + ANTENNAPARTIALMETALAREA 1.5834 LAYER Metal2 ; + ANTENNADIFFAREA 0.988 LAYER Metal2 ; + PORT + LAYER Metal2 ; + RECT 649.455 0 649.715 0.26 ; + END + END A_DOUT[14] + PIN A_DIN[18] + DIRECTION INPUT ; + USE SIGNAL ; + ANTENNAPARTIALMETALAREA 2.8847 LAYER Metal2 ; + ANTENNAMODEL OXIDE1 ; + ANTENNAGATEAREA 0.20085 LAYER Metal2 ; + ANTENNAMAXAREACAR 15.268608 LAYER Metal2 ; + PORT + LAYER Metal2 ; + RECT 893.63 0 893.89 0.26 ; + END + END A_DIN[18] + PIN A_DIN[13] + DIRECTION INPUT ; + USE SIGNAL ; + ANTENNAPARTIALMETALAREA 2.8847 LAYER Metal2 ; + ANTENNAMODEL OXIDE1 ; + ANTENNAGATEAREA 0.20085 LAYER Metal2 ; + ANTENNAMAXAREACAR 15.268608 LAYER Metal2 ; + PORT + LAYER Metal2 ; + RECT 626.27 0 626.53 0.26 ; + END + END A_DIN[13] + PIN A_DOUT[18] + DIRECTION OUTPUT ; + USE SIGNAL ; + ANTENNAPARTIALMETALAREA 1.5834 LAYER Metal2 ; + ANTENNADIFFAREA 0.988 LAYER Metal2 ; + PORT + LAYER Metal2 ; + RECT 915.405 0 915.665 0.26 ; + END + END A_DOUT[18] + PIN A_DOUT[13] + DIRECTION OUTPUT ; + USE SIGNAL ; + ANTENNAPARTIALMETALAREA 1.5834 LAYER Metal2 ; + ANTENNADIFFAREA 0.988 LAYER Metal2 ; + PORT + LAYER Metal2 ; + RECT 604.495 0 604.755 0.26 ; + END + END A_DOUT[13] + PIN A_DIN[19] + DIRECTION INPUT ; + USE SIGNAL ; + ANTENNAPARTIALMETALAREA 2.8847 LAYER Metal2 ; + ANTENNAMODEL OXIDE1 ; + ANTENNAGATEAREA 0.20085 LAYER Metal2 ; + ANTENNAMAXAREACAR 15.268608 LAYER Metal2 ; + PORT + LAYER Metal2 ; + RECT 938.59 0 938.85 0.26 ; + END + END A_DIN[19] + PIN A_DIN[12] + DIRECTION INPUT ; + USE SIGNAL ; + ANTENNAPARTIALMETALAREA 2.8847 LAYER Metal2 ; + ANTENNAMODEL OXIDE1 ; + ANTENNAGATEAREA 0.20085 LAYER Metal2 ; + ANTENNAMAXAREACAR 15.268608 LAYER Metal2 ; + PORT + LAYER Metal2 ; + RECT 581.31 0 581.57 0.26 ; + END + END A_DIN[12] + PIN A_DOUT[19] + DIRECTION OUTPUT ; + USE SIGNAL ; + ANTENNAPARTIALMETALAREA 1.5834 LAYER Metal2 ; + ANTENNADIFFAREA 0.988 LAYER Metal2 ; + PORT + LAYER Metal2 ; + RECT 960.365 0 960.625 0.26 ; + END + END A_DOUT[19] + PIN A_DOUT[12] + DIRECTION OUTPUT ; + USE SIGNAL ; + ANTENNAPARTIALMETALAREA 1.5834 LAYER Metal2 ; + ANTENNADIFFAREA 0.988 LAYER Metal2 ; + PORT + LAYER Metal2 ; + RECT 559.535 0 559.795 0.26 ; + END + END A_DOUT[12] + PIN A_DIN[20] + DIRECTION INPUT ; + USE SIGNAL ; + ANTENNAPARTIALMETALAREA 2.8847 LAYER Metal2 ; + ANTENNAMODEL OXIDE1 ; + ANTENNAGATEAREA 0.20085 LAYER Metal2 ; + ANTENNAMAXAREACAR 15.268608 LAYER Metal2 ; + PORT + LAYER Metal2 ; + RECT 983.55 0 983.81 0.26 ; + END + END A_DIN[20] + PIN A_DIN[11] + DIRECTION INPUT ; + USE SIGNAL ; + ANTENNAPARTIALMETALAREA 2.8847 LAYER Metal2 ; + ANTENNAMODEL OXIDE1 ; + ANTENNAGATEAREA 0.20085 LAYER Metal2 ; + ANTENNAMAXAREACAR 15.268608 LAYER Metal2 ; + PORT + LAYER Metal2 ; + RECT 536.35 0 536.61 0.26 ; + END + END A_DIN[11] + PIN A_DOUT[20] + DIRECTION OUTPUT ; + USE SIGNAL ; + ANTENNAPARTIALMETALAREA 1.5834 LAYER Metal2 ; + ANTENNADIFFAREA 0.988 LAYER Metal2 ; + PORT + LAYER Metal2 ; + RECT 1005.325 0 1005.585 0.26 ; + END + END A_DOUT[20] + PIN A_DOUT[11] + DIRECTION OUTPUT ; + USE SIGNAL ; + ANTENNAPARTIALMETALAREA 1.5834 LAYER Metal2 ; + ANTENNADIFFAREA 0.988 LAYER Metal2 ; + PORT + LAYER Metal2 ; + RECT 514.575 0 514.835 0.26 ; + END + END A_DOUT[11] + PIN A_DIN[21] + DIRECTION INPUT ; + USE SIGNAL ; + ANTENNAPARTIALMETALAREA 2.8847 LAYER Metal2 ; + ANTENNAMODEL OXIDE1 ; + ANTENNAGATEAREA 0.20085 LAYER Metal2 ; + ANTENNAMAXAREACAR 15.268608 LAYER Metal2 ; + PORT + LAYER Metal2 ; + RECT 1028.51 0 1028.77 0.26 ; + END + END A_DIN[21] + PIN A_DIN[10] + DIRECTION INPUT ; + USE SIGNAL ; + ANTENNAPARTIALMETALAREA 2.8847 LAYER Metal2 ; + ANTENNAMODEL OXIDE1 ; + ANTENNAGATEAREA 0.20085 LAYER Metal2 ; + ANTENNAMAXAREACAR 15.268608 LAYER Metal2 ; + PORT + LAYER Metal2 ; + RECT 491.39 0 491.65 0.26 ; + END + END A_DIN[10] + PIN A_DOUT[21] + DIRECTION OUTPUT ; + USE SIGNAL ; + ANTENNAPARTIALMETALAREA 1.5834 LAYER Metal2 ; + ANTENNADIFFAREA 0.988 LAYER Metal2 ; + PORT + LAYER Metal2 ; + RECT 1050.285 0 1050.545 0.26 ; + END + END A_DOUT[21] + PIN A_DOUT[10] + DIRECTION OUTPUT ; + USE SIGNAL ; + ANTENNAPARTIALMETALAREA 1.5834 LAYER Metal2 ; + ANTENNADIFFAREA 0.988 LAYER Metal2 ; + PORT + LAYER Metal2 ; + RECT 469.615 0 469.875 0.26 ; + END + END A_DOUT[10] + PIN A_DIN[22] + DIRECTION INPUT ; + USE SIGNAL ; + ANTENNAPARTIALMETALAREA 2.8847 LAYER Metal2 ; + ANTENNAMODEL OXIDE1 ; + ANTENNAGATEAREA 0.20085 LAYER Metal2 ; + ANTENNAMAXAREACAR 15.268608 LAYER Metal2 ; + PORT + LAYER Metal2 ; + RECT 1073.47 0 1073.73 0.26 ; + END + END A_DIN[22] + PIN A_DIN[9] + DIRECTION INPUT ; + USE SIGNAL ; + ANTENNAPARTIALMETALAREA 2.8847 LAYER Metal2 ; + ANTENNAMODEL OXIDE1 ; + ANTENNAGATEAREA 0.20085 LAYER Metal2 ; + ANTENNAMAXAREACAR 15.268608 LAYER Metal2 ; + PORT + LAYER Metal2 ; + RECT 446.43 0 446.69 0.26 ; + END + END A_DIN[9] + PIN A_DOUT[22] + DIRECTION OUTPUT ; + USE SIGNAL ; + ANTENNAPARTIALMETALAREA 1.5834 LAYER Metal2 ; + ANTENNADIFFAREA 0.988 LAYER Metal2 ; + PORT + LAYER Metal2 ; + RECT 1095.245 0 1095.505 0.26 ; + END + END A_DOUT[22] + PIN A_DOUT[9] + DIRECTION OUTPUT ; + USE SIGNAL ; + ANTENNAPARTIALMETALAREA 1.5834 LAYER Metal2 ; + ANTENNADIFFAREA 0.988 LAYER Metal2 ; + PORT + LAYER Metal2 ; + RECT 424.655 0 424.915 0.26 ; + END + END A_DOUT[9] + PIN A_DIN[23] + DIRECTION INPUT ; + USE SIGNAL ; + ANTENNAPARTIALMETALAREA 2.8847 LAYER Metal2 ; + ANTENNAMODEL OXIDE1 ; + ANTENNAGATEAREA 0.20085 LAYER Metal2 ; + ANTENNAMAXAREACAR 15.268608 LAYER Metal2 ; + PORT + LAYER Metal2 ; + RECT 1118.43 0 1118.69 0.26 ; + END + END A_DIN[23] + PIN A_DIN[8] + DIRECTION INPUT ; + USE SIGNAL ; + ANTENNAPARTIALMETALAREA 2.8847 LAYER Metal2 ; + ANTENNAMODEL OXIDE1 ; + ANTENNAGATEAREA 0.20085 LAYER Metal2 ; + ANTENNAMAXAREACAR 15.268608 LAYER Metal2 ; + PORT + LAYER Metal2 ; + RECT 401.47 0 401.73 0.26 ; + END + END A_DIN[8] + PIN A_DOUT[23] + DIRECTION OUTPUT ; + USE SIGNAL ; + ANTENNAPARTIALMETALAREA 1.5834 LAYER Metal2 ; + ANTENNADIFFAREA 0.988 LAYER Metal2 ; + PORT + LAYER Metal2 ; + RECT 1140.205 0 1140.465 0.26 ; + END + END A_DOUT[23] + PIN A_DOUT[8] + DIRECTION OUTPUT ; + USE SIGNAL ; + ANTENNAPARTIALMETALAREA 1.5834 LAYER Metal2 ; + ANTENNADIFFAREA 0.988 LAYER Metal2 ; + PORT + LAYER Metal2 ; + RECT 379.695 0 379.955 0.26 ; + END + END A_DOUT[8] + PIN A_DIN[24] + DIRECTION INPUT ; + USE SIGNAL ; + ANTENNAPARTIALMETALAREA 2.8847 LAYER Metal2 ; + ANTENNAMODEL OXIDE1 ; + ANTENNAGATEAREA 0.20085 LAYER Metal2 ; + ANTENNAMAXAREACAR 15.268608 LAYER Metal2 ; + PORT + LAYER Metal2 ; + RECT 1163.39 0 1163.65 0.26 ; + END + END A_DIN[24] + PIN A_DIN[7] + DIRECTION INPUT ; + USE SIGNAL ; + ANTENNAPARTIALMETALAREA 2.8847 LAYER Metal2 ; + ANTENNAMODEL OXIDE1 ; + ANTENNAGATEAREA 0.20085 LAYER Metal2 ; + ANTENNAMAXAREACAR 15.268608 LAYER Metal2 ; + PORT + LAYER Metal2 ; + RECT 356.51 0 356.77 0.26 ; + END + END A_DIN[7] + PIN A_DOUT[24] + DIRECTION OUTPUT ; + USE SIGNAL ; + ANTENNAPARTIALMETALAREA 1.5834 LAYER Metal2 ; + ANTENNADIFFAREA 0.988 LAYER Metal2 ; + PORT + LAYER Metal2 ; + RECT 1185.165 0 1185.425 0.26 ; + END + END A_DOUT[24] + PIN A_DOUT[7] + DIRECTION OUTPUT ; + USE SIGNAL ; + ANTENNAPARTIALMETALAREA 1.5834 LAYER Metal2 ; + ANTENNADIFFAREA 0.988 LAYER Metal2 ; + PORT + LAYER Metal2 ; + RECT 334.735 0 334.995 0.26 ; + END + END A_DOUT[7] + PIN A_DIN[25] + DIRECTION INPUT ; + USE SIGNAL ; + ANTENNAPARTIALMETALAREA 2.8847 LAYER Metal2 ; + ANTENNAMODEL OXIDE1 ; + ANTENNAGATEAREA 0.20085 LAYER Metal2 ; + ANTENNAMAXAREACAR 15.268608 LAYER Metal2 ; + PORT + LAYER Metal2 ; + RECT 1208.35 0 1208.61 0.26 ; + END + END A_DIN[25] + PIN A_DIN[6] + DIRECTION INPUT ; + USE SIGNAL ; + ANTENNAPARTIALMETALAREA 2.8847 LAYER Metal2 ; + ANTENNAMODEL OXIDE1 ; + ANTENNAGATEAREA 0.20085 LAYER Metal2 ; + ANTENNAMAXAREACAR 15.268608 LAYER Metal2 ; + PORT + LAYER Metal2 ; + RECT 311.55 0 311.81 0.26 ; + END + END A_DIN[6] + PIN A_DOUT[25] + DIRECTION OUTPUT ; + USE SIGNAL ; + ANTENNAPARTIALMETALAREA 1.5834 LAYER Metal2 ; + ANTENNADIFFAREA 0.988 LAYER Metal2 ; + PORT + LAYER Metal2 ; + RECT 1230.125 0 1230.385 0.26 ; + END + END A_DOUT[25] + PIN A_DOUT[6] + DIRECTION OUTPUT ; + USE SIGNAL ; + ANTENNAPARTIALMETALAREA 1.5834 LAYER Metal2 ; + ANTENNADIFFAREA 0.988 LAYER Metal2 ; + PORT + LAYER Metal2 ; + RECT 289.775 0 290.035 0.26 ; + END + END A_DOUT[6] + PIN A_DIN[26] + DIRECTION INPUT ; + USE SIGNAL ; + ANTENNAPARTIALMETALAREA 2.8847 LAYER Metal2 ; + ANTENNAMODEL OXIDE1 ; + ANTENNAGATEAREA 0.20085 LAYER Metal2 ; + ANTENNAMAXAREACAR 15.268608 LAYER Metal2 ; + PORT + LAYER Metal2 ; + RECT 1253.31 0 1253.57 0.26 ; + END + END A_DIN[26] + PIN A_DIN[5] + DIRECTION INPUT ; + USE SIGNAL ; + ANTENNAPARTIALMETALAREA 2.8847 LAYER Metal2 ; + ANTENNAMODEL OXIDE1 ; + ANTENNAGATEAREA 0.20085 LAYER Metal2 ; + ANTENNAMAXAREACAR 15.268608 LAYER Metal2 ; + PORT + LAYER Metal2 ; + RECT 266.59 0 266.85 0.26 ; + END + END A_DIN[5] + PIN A_DOUT[26] + DIRECTION OUTPUT ; + USE SIGNAL ; + ANTENNAPARTIALMETALAREA 1.5834 LAYER Metal2 ; + ANTENNADIFFAREA 0.988 LAYER Metal2 ; + PORT + LAYER Metal2 ; + RECT 1275.085 0 1275.345 0.26 ; + END + END A_DOUT[26] + PIN A_DOUT[5] + DIRECTION OUTPUT ; + USE SIGNAL ; + ANTENNAPARTIALMETALAREA 1.5834 LAYER Metal2 ; + ANTENNADIFFAREA 0.988 LAYER Metal2 ; + PORT + LAYER Metal2 ; + RECT 244.815 0 245.075 0.26 ; + END + END A_DOUT[5] + PIN A_DIN[27] + DIRECTION INPUT ; + USE SIGNAL ; + ANTENNAPARTIALMETALAREA 2.8847 LAYER Metal2 ; + ANTENNAMODEL OXIDE1 ; + ANTENNAGATEAREA 0.20085 LAYER Metal2 ; + ANTENNAMAXAREACAR 15.268608 LAYER Metal2 ; + PORT + LAYER Metal2 ; + RECT 1298.27 0 1298.53 0.26 ; + END + END A_DIN[27] + PIN A_DIN[4] + DIRECTION INPUT ; + USE SIGNAL ; + ANTENNAPARTIALMETALAREA 2.8847 LAYER Metal2 ; + ANTENNAMODEL OXIDE1 ; + ANTENNAGATEAREA 0.20085 LAYER Metal2 ; + ANTENNAMAXAREACAR 15.268608 LAYER Metal2 ; + PORT + LAYER Metal2 ; + RECT 221.63 0 221.89 0.26 ; + END + END A_DIN[4] + PIN A_DOUT[27] + DIRECTION OUTPUT ; + USE SIGNAL ; + ANTENNAPARTIALMETALAREA 1.5834 LAYER Metal2 ; + ANTENNADIFFAREA 0.988 LAYER Metal2 ; + PORT + LAYER Metal2 ; + RECT 1320.045 0 1320.305 0.26 ; + END + END A_DOUT[27] + PIN A_DOUT[4] + DIRECTION OUTPUT ; + USE SIGNAL ; + ANTENNAPARTIALMETALAREA 1.5834 LAYER Metal2 ; + ANTENNADIFFAREA 0.988 LAYER Metal2 ; + PORT + LAYER Metal2 ; + RECT 199.855 0 200.115 0.26 ; + END + END A_DOUT[4] + PIN A_DIN[28] + DIRECTION INPUT ; + USE SIGNAL ; + ANTENNAPARTIALMETALAREA 2.8847 LAYER Metal2 ; + ANTENNAMODEL OXIDE1 ; + ANTENNAGATEAREA 0.20085 LAYER Metal2 ; + ANTENNAMAXAREACAR 15.268608 LAYER Metal2 ; + PORT + LAYER Metal2 ; + RECT 1343.23 0 1343.49 0.26 ; + END + END A_DIN[28] + PIN A_DIN[3] + DIRECTION INPUT ; + USE SIGNAL ; + ANTENNAPARTIALMETALAREA 2.8847 LAYER Metal2 ; + ANTENNAMODEL OXIDE1 ; + ANTENNAGATEAREA 0.20085 LAYER Metal2 ; + ANTENNAMAXAREACAR 15.268608 LAYER Metal2 ; + PORT + LAYER Metal2 ; + RECT 176.67 0 176.93 0.26 ; + END + END A_DIN[3] + PIN A_DOUT[28] + DIRECTION OUTPUT ; + USE SIGNAL ; + ANTENNAPARTIALMETALAREA 1.5834 LAYER Metal2 ; + ANTENNADIFFAREA 0.988 LAYER Metal2 ; + PORT + LAYER Metal2 ; + RECT 1365.005 0 1365.265 0.26 ; + END + END A_DOUT[28] + PIN A_DOUT[3] + DIRECTION OUTPUT ; + USE SIGNAL ; + ANTENNAPARTIALMETALAREA 1.5834 LAYER Metal2 ; + ANTENNADIFFAREA 0.988 LAYER Metal2 ; + PORT + LAYER Metal2 ; + RECT 154.895 0 155.155 0.26 ; + END + END A_DOUT[3] + PIN A_DIN[29] + DIRECTION INPUT ; + USE SIGNAL ; + ANTENNAPARTIALMETALAREA 2.8847 LAYER Metal2 ; + ANTENNAMODEL OXIDE1 ; + ANTENNAGATEAREA 0.20085 LAYER Metal2 ; + ANTENNAMAXAREACAR 15.268608 LAYER Metal2 ; + PORT + LAYER Metal2 ; + RECT 1388.19 0 1388.45 0.26 ; + END + END A_DIN[29] + PIN A_DIN[2] + DIRECTION INPUT ; + USE SIGNAL ; + ANTENNAPARTIALMETALAREA 2.8847 LAYER Metal2 ; + ANTENNAMODEL OXIDE1 ; + ANTENNAGATEAREA 0.20085 LAYER Metal2 ; + ANTENNAMAXAREACAR 15.268608 LAYER Metal2 ; + PORT + LAYER Metal2 ; + RECT 131.71 0 131.97 0.26 ; + END + END A_DIN[2] + PIN A_DOUT[29] + DIRECTION OUTPUT ; + USE SIGNAL ; + ANTENNAPARTIALMETALAREA 1.5834 LAYER Metal2 ; + ANTENNADIFFAREA 0.988 LAYER Metal2 ; + PORT + LAYER Metal2 ; + RECT 1409.965 0 1410.225 0.26 ; + END + END A_DOUT[29] + PIN A_DOUT[2] + DIRECTION OUTPUT ; + USE SIGNAL ; + ANTENNAPARTIALMETALAREA 1.5834 LAYER Metal2 ; + ANTENNADIFFAREA 0.988 LAYER Metal2 ; + PORT + LAYER Metal2 ; + RECT 109.935 0 110.195 0.26 ; + END + END A_DOUT[2] + PIN A_DIN[30] + DIRECTION INPUT ; + USE SIGNAL ; + ANTENNAPARTIALMETALAREA 2.8847 LAYER Metal2 ; + ANTENNAMODEL OXIDE1 ; + ANTENNAGATEAREA 0.20085 LAYER Metal2 ; + ANTENNAMAXAREACAR 15.268608 LAYER Metal2 ; + PORT + LAYER Metal2 ; + RECT 1433.15 0 1433.41 0.26 ; + END + END A_DIN[30] + PIN A_DIN[1] + DIRECTION INPUT ; + USE SIGNAL ; + ANTENNAPARTIALMETALAREA 2.8847 LAYER Metal2 ; + ANTENNAMODEL OXIDE1 ; + ANTENNAGATEAREA 0.20085 LAYER Metal2 ; + ANTENNAMAXAREACAR 15.268608 LAYER Metal2 ; + PORT + LAYER Metal2 ; + RECT 86.75 0 87.01 0.26 ; + END + END A_DIN[1] + PIN A_DOUT[30] + DIRECTION OUTPUT ; + USE SIGNAL ; + ANTENNAPARTIALMETALAREA 1.5834 LAYER Metal2 ; + ANTENNADIFFAREA 0.988 LAYER Metal2 ; + PORT + LAYER Metal2 ; + RECT 1454.925 0 1455.185 0.26 ; + END + END A_DOUT[30] + PIN A_DOUT[1] + DIRECTION OUTPUT ; + USE SIGNAL ; + ANTENNAPARTIALMETALAREA 1.5834 LAYER Metal2 ; + ANTENNADIFFAREA 0.988 LAYER Metal2 ; + PORT + LAYER Metal2 ; + RECT 64.975 0 65.235 0.26 ; + END + END A_DOUT[1] + PIN A_DIN[31] + DIRECTION INPUT ; + USE SIGNAL ; + ANTENNAPARTIALMETALAREA 2.8847 LAYER Metal2 ; + ANTENNAMODEL OXIDE1 ; + ANTENNAGATEAREA 0.20085 LAYER Metal2 ; + ANTENNAMAXAREACAR 15.268608 LAYER Metal2 ; + PORT + LAYER Metal2 ; + RECT 1478.11 0 1478.37 0.26 ; + END + END A_DIN[31] + PIN A_DIN[0] + DIRECTION INPUT ; + USE SIGNAL ; + ANTENNAPARTIALMETALAREA 2.8847 LAYER Metal2 ; + ANTENNAMODEL OXIDE1 ; + ANTENNAGATEAREA 0.20085 LAYER Metal2 ; + ANTENNAMAXAREACAR 15.268608 LAYER Metal2 ; + PORT + LAYER Metal2 ; + RECT 41.79 0 42.05 0.26 ; + END + END A_DIN[0] + PIN A_DOUT[31] + DIRECTION OUTPUT ; + USE SIGNAL ; + ANTENNAPARTIALMETALAREA 1.5834 LAYER Metal2 ; + ANTENNADIFFAREA 0.988 LAYER Metal2 ; + PORT + LAYER Metal2 ; + RECT 1499.885 0 1500.145 0.26 ; + END + END A_DOUT[31] + PIN A_DOUT[0] + DIRECTION OUTPUT ; + USE SIGNAL ; + ANTENNAPARTIALMETALAREA 1.5834 LAYER Metal2 ; + ANTENNADIFFAREA 0.988 LAYER Metal2 ; + PORT + LAYER Metal2 ; + RECT 20.015 0 20.275 0.26 ; + END + END A_DOUT[0] + PIN A_ADDR[0] + DIRECTION INPUT ; + USE SIGNAL ; + ANTENNAPARTIALMETALAREA 6.7171 LAYER Metal2 ; + ANTENNAMODEL OXIDE1 ; + ANTENNAGATEAREA 0.20085 LAYER Metal2 ; + ANTENNAMAXAREACAR 34.349515 LAYER Metal2 ; + PORT + LAYER Metal2 ; + RECT 756.28 0 756.54 0.26 ; + END + END A_ADDR[0] + PIN A_ADDR[1] + DIRECTION INPUT ; + USE SIGNAL ; + ANTENNAPARTIALMETALAREA 5.59 LAYER Metal2 ; + ANTENNAMODEL OXIDE1 ; + ANTENNAGATEAREA 0.20085 LAYER Metal2 ; + ANTENNAMAXAREACAR 28.783172 LAYER Metal2 ; + PORT + LAYER Metal2 ; + RECT 755.77 0 756.03 0.26 ; + END + END A_ADDR[1] + PIN A_ADDR[2] + DIRECTION INPUT ; + USE SIGNAL ; + ANTENNAPARTIALMETALAREA 6.4519 LAYER Metal2 ; + ANTENNAMODEL OXIDE1 ; + ANTENNAGATEAREA 0.20085 LAYER Metal2 ; + ANTENNAMAXAREACAR 33.029126 LAYER Metal2 ; + PORT + LAYER Metal2 ; + RECT 741.49 0 741.75 0.26 ; + END + END A_ADDR[2] + PIN A_ADDR[3] + DIRECTION INPUT ; + USE SIGNAL ; + ANTENNAPARTIALMETALAREA 5.0947 LAYER Metal2 ; + ANTENNAPARTIALMETALAREA 1.2684 LAYER Metal3 ; + ANTENNAPARTIALCUTAREA 0.0722 LAYER Via2 ; + ANTENNAMODEL OXIDE1 ; + ANTENNAGATEAREA 0.20085 LAYER Metal3 ; + ANTENNAMAXAREACAR 8.671148 LAYER Metal3 ; + PORT + LAYER Metal2 ; + RECT 746.08 0 746.34 0.26 ; + END + END A_ADDR[3] + PIN A_ADDR[4] + DIRECTION INPUT ; + USE SIGNAL ; + ANTENNAPARTIALMETALAREA 8.4487 LAYER Metal2 ; + ANTENNAPARTIALMETALAREA 1.5246 LAYER Metal3 ; + ANTENNAPARTIALCUTAREA 0.0722 LAYER Via2 ; + ANTENNAMODEL OXIDE1 ; + ANTENNAGATEAREA 0.20085 LAYER Metal3 ; + ANTENNAMAXAREACAR 9.415982 LAYER Metal3 ; + PORT + LAYER Metal2 ; + RECT 763.93 0 764.19 0.26 ; + END + END A_ADDR[4] + PIN A_ADDR[5] + DIRECTION INPUT ; + USE SIGNAL ; + ANTENNAPARTIALMETALAREA 8.4487 LAYER Metal2 ; + ANTENNAPARTIALMETALAREA 3.8367 LAYER Metal3 ; + ANTENNAPARTIALCUTAREA 0.0722 LAYER Via2 ; + ANTENNAMODEL OXIDE1 ; + ANTENNAGATEAREA 0.20085 LAYER Metal3 ; + ANTENNAMAXAREACAR 20.927558 LAYER Metal3 ; + PORT + LAYER Metal2 ; + RECT 762.91 0 763.17 0.26 ; + END + END A_ADDR[5] + PIN A_ADDR[6] + DIRECTION INPUT ; + USE SIGNAL ; + ANTENNAPARTIALMETALAREA 10.0139 LAYER Metal2 ; + ANTENNAMODEL OXIDE1 ; + ANTENNAGATEAREA 0.20085 LAYER Metal2 ; + ANTENNAMAXAREACAR 50.763754 LAYER Metal2 ; + PORT + LAYER Metal2 ; + RECT 766.48 0 766.74 0.26 ; + END + END A_ADDR[6] + PIN A_ADDR[7] + DIRECTION INPUT ; + USE SIGNAL ; + ANTENNAPARTIALMETALAREA 11.7429 LAYER Metal2 ; + ANTENNAMODEL OXIDE1 ; + ANTENNAGATEAREA 0.20085 LAYER Metal2 ; + ANTENNAMAXAREACAR 59.372168 LAYER Metal2 ; + PORT + LAYER Metal2 ; + RECT 765.46 0 765.72 0.26 ; + END + END A_ADDR[7] + PIN A_ADDR[8] + DIRECTION INPUT ; + USE SIGNAL ; + ANTENNAPARTIALMETALAREA 8.7685 LAYER Metal2 ; + ANTENNAMODEL OXIDE1 ; + ANTENNAGATEAREA 0.20085 LAYER Metal2 ; + ANTENNAMAXAREACAR 44.563107 LAYER Metal2 ; + PORT + LAYER Metal2 ; + RECT 744.04 0 744.3 0.26 ; + END + END A_ADDR[8] + PIN A_ADDR[9] + DIRECTION INPUT ; + USE SIGNAL ; + ANTENNAPARTIALMETALAREA 10.2323 LAYER Metal2 ; + ANTENNAMODEL OXIDE1 ; + ANTENNAGATEAREA 0.20085 LAYER Metal2 ; + ANTENNAMAXAREACAR 51.851133 LAYER Metal2 ; + PORT + LAYER Metal2 ; + RECT 745.06 0 745.32 0.26 ; + END + END A_ADDR[9] + PIN A_ADDR[10] + DIRECTION INPUT ; + USE SIGNAL ; + ANTENNAPARTIALMETALAREA 7.9183 LAYER Metal2 ; + ANTENNAPARTIALMETALAREA 1.5897 LAYER Metal3 ; + ANTENNAPARTIALCUTAREA 0.0722 LAYER Via2 ; + ANTENNAMODEL OXIDE1 ; + ANTENNAGATEAREA 0.20085 LAYER Metal3 ; + ANTENNAMAXAREACAR 9.740105 LAYER Metal3 ; + PORT + LAYER Metal2 ; + RECT 774.13 0 774.39 0.26 ; + END + END A_ADDR[10] + PIN A_ADDR[11] + DIRECTION INPUT ; + USE SIGNAL ; + ANTENNAPARTIALMETALAREA 10.6097 LAYER Metal2 ; + ANTENNAMODEL OXIDE1 ; + ANTENNAGATEAREA 0.20085 LAYER Metal2 ; + ANTENNAMAXAREACAR 53.730147 LAYER Metal2 ; + PORT + LAYER Metal2 ; + RECT 769.03 0 769.29 0.26 ; + END + END A_ADDR[11] + PIN A_ADDR[12] + DIRECTION INPUT ; + USE SIGNAL ; + ANTENNAPARTIALMETALAREA 8.6359 LAYER Metal2 ; + ANTENNAMODEL OXIDE1 ; + ANTENNAGATEAREA 0.20085 LAYER Metal2 ; + ANTENNAMAXAREACAR 43.902913 LAYER Metal2 ; + PORT + LAYER Metal2 ; + RECT 766.99 0 767.25 0.26 ; + END + END A_ADDR[12] + PIN A_CLK + DIRECTION INPUT ; + USE SIGNAL ; + ANTENNAPARTIALMETALAREA 1.8707 LAYER Metal2 ; + ANTENNAMODEL OXIDE1 ; + ANTENNAGATEAREA 0.20085 LAYER Metal2 ; + ANTENNAMAXAREACAR 10.220065 LAYER Metal2 ; + PORT + LAYER Metal2 ; + RECT 754.24 0 754.5 0.26 ; + END + END A_CLK + PIN A_REN + DIRECTION INPUT ; + USE SIGNAL ; + ANTENNAPARTIALMETALAREA 1.81105 LAYER Metal2 ; + ANTENNAMODEL OXIDE1 ; + ANTENNAGATEAREA 0.20085 LAYER Metal2 ; + ANTENNAMAXAREACAR 9.923077 LAYER Metal2 ; + PORT + LAYER Metal2 ; + RECT 757.81 0 758.07 0.26 ; + END + END A_REN + PIN A_WEN + DIRECTION INPUT ; + USE SIGNAL ; + ANTENNAPARTIALMETALAREA 0.7007 LAYER Metal2 ; + ANTENNAMODEL OXIDE1 ; + ANTENNAGATEAREA 0.20085 LAYER Metal2 ; + ANTENNAMAXAREACAR 4.394822 LAYER Metal2 ; + PORT + LAYER Metal2 ; + RECT 757.3 0 757.56 0.26 ; + END + END A_WEN + PIN A_MEN + DIRECTION INPUT ; + USE SIGNAL ; + ANTENNAPARTIALMETALAREA 0.8407 LAYER Metal2 ; + ANTENNAMODEL OXIDE1 ; + ANTENNAGATEAREA 0.20085 LAYER Metal2 ; + ANTENNAMAXAREACAR 5.09186 LAYER Metal2 ; + PORT + LAYER Metal2 ; + RECT 754.75 0 755.01 0.26 ; + END + END A_MEN + PIN A_DLY + DIRECTION INPUT ; + USE SIGNAL ; + ANTENNAPARTIALMETALAREA 3.874 LAYER Metal2 ; + ANTENNAMODEL OXIDE1 ; + ANTENNAGATEAREA 0.3367 LAYER Metal2 ; + ANTENNAMAXAREACAR 12.046332 LAYER Metal2 ; + PORT + LAYER Metal2 ; + RECT 776.17 0 776.43 0.26 ; + END + END A_DLY + OBS + LAYER Metal1 ; + RECT 0 0 1520.16 618.3 ; + LAYER Metal2 ; + RECT 0.105 37.065 0.305 618.275 ; + RECT 1.1 617.545 1.3 618.275 ; + RECT 1.92 617.545 2.12 618.275 ; + RECT 2.415 617.545 2.615 618.275 ; + RECT 2.915 617.545 3.115 618.275 ; + RECT 3.415 617.545 3.615 618.275 ; + RECT 3.91 617.545 4.11 618.275 ; + RECT 5.225 0.17 5.995 0.43 ; + RECT 5.735 0.17 5.995 11.38 ; + RECT 5.225 0.17 5.485 16.7 ; + RECT 4.73 617.545 4.93 618.275 ; + RECT 5.225 617.545 5.425 618.275 ; + RECT 5.725 617.545 5.925 618.275 ; + RECT 6.225 617.545 6.425 618.275 ; + RECT 6.72 617.545 6.92 618.275 ; + RECT 7.54 617.545 7.74 618.275 ; + RECT 8.795 0.17 9.565 0.43 ; + RECT 9.305 0.17 9.565 8.7 ; + RECT 8.795 0.17 9.055 16.7 ; + RECT 8.035 617.545 8.235 618.275 ; + RECT 8.535 617.545 8.735 618.275 ; + RECT 9.035 617.545 9.235 618.275 ; + RECT 9.53 617.545 9.73 618.275 ; + RECT 9.815 0.3 10.075 4.63 ; + RECT 10.35 617.545 10.55 618.275 ; + RECT 10.835 0.17 11.605 0.43 ; + RECT 11.345 0.17 11.605 8.7 ; + RECT 10.835 0.17 11.095 16.7 ; + RECT 10.325 0.3 10.585 4.63 ; + RECT 10.845 617.545 11.045 618.275 ; + RECT 11.345 617.545 11.545 618.275 ; + RECT 11.845 617.545 12.045 618.275 ; + RECT 12.34 617.545 12.54 618.275 ; + RECT 13.16 617.545 13.36 618.275 ; + RECT 13.655 617.545 13.855 618.275 ; + RECT 14.155 617.545 14.355 618.275 ; + RECT 14.655 617.545 14.855 618.275 ; + RECT 15.15 617.545 15.35 618.275 ; + RECT 15.97 617.545 16.17 618.275 ; + RECT 16.465 617.545 16.665 618.275 ; + RECT 16.965 617.545 17.165 618.275 ; + RECT 17.465 617.545 17.665 618.275 ; + RECT 17.565 0.3 17.825 4.63 ; + RECT 18.585 0.165 19.355 0.425 ; + RECT 18.585 0.165 18.845 8.825 ; + RECT 19.095 0.165 19.355 8.825 ; + RECT 17.96 617.545 18.16 618.275 ; + RECT 18.075 0.3 18.335 4.63 ; + RECT 18.78 617.545 18.98 618.275 ; + RECT 19.275 617.545 19.475 618.275 ; + RECT 19.775 617.545 19.975 618.275 ; + RECT 20.015 0.52 20.275 4.5 ; + RECT 20.275 617.545 20.475 618.275 ; + RECT 20.77 617.545 20.97 618.275 ; + RECT 21.59 617.545 21.79 618.275 ; + RECT 22.085 617.545 22.285 618.275 ; + RECT 22.585 617.545 22.785 618.275 ; + RECT 23.085 617.545 23.285 618.275 ; + RECT 23.58 617.545 23.78 618.275 ; + RECT 24.4 617.545 24.6 618.275 ; + RECT 24.895 617.545 25.095 618.275 ; + RECT 25.395 617.545 25.595 618.275 ; + RECT 25.895 617.545 26.095 618.275 ; + RECT 26.39 617.545 26.59 618.275 ; + RECT 27.21 617.545 27.41 618.275 ; + RECT 27.705 617.545 27.905 618.275 ; + RECT 28.205 617.545 28.405 618.275 ; + RECT 28.705 617.545 28.905 618.275 ; + RECT 29.2 617.545 29.4 618.275 ; + RECT 30.02 617.545 30.22 618.275 ; + RECT 30.515 617.545 30.715 618.275 ; + RECT 31.015 617.545 31.215 618.275 ; + RECT 31.515 617.545 31.715 618.275 ; + RECT 32.01 617.545 32.21 618.275 ; + RECT 32.83 617.545 33.03 618.275 ; + RECT 33.785 0.16 34.555 0.42 ; + RECT 34.295 0.16 34.555 4.63 ; + RECT 33.785 0.16 34.045 8.82 ; + RECT 33.325 617.545 33.525 618.275 ; + RECT 33.825 617.545 34.025 618.275 ; + RECT 34.325 617.545 34.525 618.275 ; + RECT 34.82 617.545 35.02 618.275 ; + RECT 34.805 0.3 35.065 4.63 ; + RECT 35.315 0.3 35.575 4.63 ; + RECT 35.64 617.545 35.84 618.275 ; + RECT 36.135 617.545 36.335 618.275 ; + RECT 36.635 617.545 36.835 618.275 ; + RECT 38.32 0.16 39.09 0.42 ; + RECT 38.32 0.16 38.58 8.82 ; + RECT 38.83 0.16 39.09 8.82 ; + RECT 37.135 617.545 37.335 618.275 ; + RECT 37.63 617.545 37.83 618.275 ; + RECT 38.45 617.545 38.65 618.275 ; + RECT 38.945 617.545 39.145 618.275 ; + RECT 39.34 0.3 39.6 4.63 ; + RECT 39.445 617.545 39.645 618.275 ; + RECT 39.85 0.3 40.11 4.63 ; + RECT 39.945 617.545 40.145 618.275 ; + RECT 40.44 617.545 40.64 618.275 ; + RECT 41.26 617.545 41.46 618.275 ; + RECT 41.755 617.545 41.955 618.275 ; + RECT 41.79 0.52 42.05 4.5 ; + RECT 42.255 617.545 42.455 618.275 ; + RECT 42.755 617.545 42.955 618.275 ; + RECT 43.25 617.545 43.45 618.275 ; + RECT 44.495 0.165 45.265 0.425 ; + RECT 44.495 0.165 44.755 8.825 ; + RECT 45.005 0.165 45.265 8.825 ; + RECT 44.07 617.545 44.27 618.275 ; + RECT 44.565 617.545 44.765 618.275 ; + RECT 45.065 617.545 45.265 618.275 ; + RECT 45.565 617.545 45.765 618.275 ; + RECT 45.515 0.3 45.775 4.63 ; + RECT 46.06 617.545 46.26 618.275 ; + RECT 46.025 0.3 46.285 8.23 ; + RECT 46.88 617.545 47.08 618.275 ; + RECT 47.375 617.545 47.575 618.275 ; + RECT 47.875 617.545 48.075 618.275 ; + RECT 48.375 617.545 48.575 618.275 ; + RECT 48.87 617.545 49.07 618.275 ; + RECT 50.185 0.17 50.955 0.43 ; + RECT 50.695 0.17 50.955 11.38 ; + RECT 50.185 0.17 50.445 16.7 ; + RECT 49.69 617.545 49.89 618.275 ; + RECT 50.185 617.545 50.385 618.275 ; + RECT 50.685 617.545 50.885 618.275 ; + RECT 51.185 617.545 51.385 618.275 ; + RECT 51.68 617.545 51.88 618.275 ; + RECT 52.5 617.545 52.7 618.275 ; + RECT 53.755 0.17 54.525 0.43 ; + RECT 54.265 0.17 54.525 8.7 ; + RECT 53.755 0.17 54.015 16.7 ; + RECT 52.995 617.545 53.195 618.275 ; + RECT 53.495 617.545 53.695 618.275 ; + RECT 53.995 617.545 54.195 618.275 ; + RECT 54.49 617.545 54.69 618.275 ; + RECT 54.775 0.3 55.035 4.63 ; + RECT 55.31 617.545 55.51 618.275 ; + RECT 55.795 0.17 56.565 0.43 ; + RECT 56.305 0.17 56.565 8.7 ; + RECT 55.795 0.17 56.055 16.7 ; + RECT 55.285 0.3 55.545 4.63 ; + RECT 55.805 617.545 56.005 618.275 ; + RECT 56.305 617.545 56.505 618.275 ; + RECT 56.805 617.545 57.005 618.275 ; + RECT 57.3 617.545 57.5 618.275 ; + RECT 58.12 617.545 58.32 618.275 ; + RECT 58.615 617.545 58.815 618.275 ; + RECT 59.115 617.545 59.315 618.275 ; + RECT 59.615 617.545 59.815 618.275 ; + RECT 60.11 617.545 60.31 618.275 ; + RECT 60.93 617.545 61.13 618.275 ; + RECT 61.425 617.545 61.625 618.275 ; + RECT 61.925 617.545 62.125 618.275 ; + RECT 62.425 617.545 62.625 618.275 ; + RECT 62.525 0.3 62.785 4.63 ; + RECT 63.545 0.165 64.315 0.425 ; + RECT 63.545 0.165 63.805 8.825 ; + RECT 64.055 0.165 64.315 8.825 ; + RECT 62.92 617.545 63.12 618.275 ; + RECT 63.035 0.3 63.295 4.63 ; + RECT 63.74 617.545 63.94 618.275 ; + RECT 64.235 617.545 64.435 618.275 ; + RECT 64.735 617.545 64.935 618.275 ; + RECT 64.975 0.52 65.235 4.5 ; + RECT 65.235 617.545 65.435 618.275 ; + RECT 65.73 617.545 65.93 618.275 ; + RECT 66.55 617.545 66.75 618.275 ; + RECT 67.045 617.545 67.245 618.275 ; + RECT 67.545 617.545 67.745 618.275 ; + RECT 68.045 617.545 68.245 618.275 ; + RECT 68.54 617.545 68.74 618.275 ; + RECT 69.36 617.545 69.56 618.275 ; + RECT 69.855 617.545 70.055 618.275 ; + RECT 70.355 617.545 70.555 618.275 ; + RECT 70.855 617.545 71.055 618.275 ; + RECT 71.35 617.545 71.55 618.275 ; + RECT 72.17 617.545 72.37 618.275 ; + RECT 72.665 617.545 72.865 618.275 ; + RECT 73.165 617.545 73.365 618.275 ; + RECT 73.665 617.545 73.865 618.275 ; + RECT 74.16 617.545 74.36 618.275 ; + RECT 74.98 617.545 75.18 618.275 ; + RECT 75.475 617.545 75.675 618.275 ; + RECT 75.975 617.545 76.175 618.275 ; + RECT 76.475 617.545 76.675 618.275 ; + RECT 76.97 617.545 77.17 618.275 ; + RECT 77.79 617.545 77.99 618.275 ; + RECT 78.745 0.16 79.515 0.42 ; + RECT 79.255 0.16 79.515 4.63 ; + RECT 78.745 0.16 79.005 8.82 ; + RECT 78.285 617.545 78.485 618.275 ; + RECT 78.785 617.545 78.985 618.275 ; + RECT 79.285 617.545 79.485 618.275 ; + RECT 79.78 617.545 79.98 618.275 ; + RECT 79.765 0.3 80.025 4.63 ; + RECT 80.275 0.3 80.535 4.63 ; + RECT 80.6 617.545 80.8 618.275 ; + RECT 81.095 617.545 81.295 618.275 ; + RECT 81.595 617.545 81.795 618.275 ; + RECT 83.28 0.16 84.05 0.42 ; + RECT 83.28 0.16 83.54 8.82 ; + RECT 83.79 0.16 84.05 8.82 ; + RECT 82.095 617.545 82.295 618.275 ; + RECT 82.59 617.545 82.79 618.275 ; + RECT 83.41 617.545 83.61 618.275 ; + RECT 83.905 617.545 84.105 618.275 ; + RECT 84.3 0.3 84.56 4.63 ; + RECT 84.405 617.545 84.605 618.275 ; + RECT 84.81 0.3 85.07 4.63 ; + RECT 84.905 617.545 85.105 618.275 ; + RECT 85.4 617.545 85.6 618.275 ; + RECT 86.22 617.545 86.42 618.275 ; + RECT 86.715 617.545 86.915 618.275 ; + RECT 86.75 0.52 87.01 4.5 ; + RECT 87.215 617.545 87.415 618.275 ; + RECT 87.715 617.545 87.915 618.275 ; + RECT 88.21 617.545 88.41 618.275 ; + RECT 89.455 0.165 90.225 0.425 ; + RECT 89.455 0.165 89.715 8.825 ; + RECT 89.965 0.165 90.225 8.825 ; + RECT 89.03 617.545 89.23 618.275 ; + RECT 89.525 617.545 89.725 618.275 ; + RECT 90.025 617.545 90.225 618.275 ; + RECT 90.525 617.545 90.725 618.275 ; + RECT 90.475 0.3 90.735 4.63 ; + RECT 91.02 617.545 91.22 618.275 ; + RECT 90.985 0.3 91.245 8.23 ; + RECT 91.84 617.545 92.04 618.275 ; + RECT 92.335 617.545 92.535 618.275 ; + RECT 92.835 617.545 93.035 618.275 ; + RECT 93.335 617.545 93.535 618.275 ; + RECT 93.83 617.545 94.03 618.275 ; + RECT 95.145 0.17 95.915 0.43 ; + RECT 95.655 0.17 95.915 11.38 ; + RECT 95.145 0.17 95.405 16.7 ; + RECT 94.65 617.545 94.85 618.275 ; + RECT 95.145 617.545 95.345 618.275 ; + RECT 95.645 617.545 95.845 618.275 ; + RECT 96.145 617.545 96.345 618.275 ; + RECT 96.64 617.545 96.84 618.275 ; + RECT 97.46 617.545 97.66 618.275 ; + RECT 98.715 0.17 99.485 0.43 ; + RECT 99.225 0.17 99.485 8.7 ; + RECT 98.715 0.17 98.975 16.7 ; + RECT 97.955 617.545 98.155 618.275 ; + RECT 98.455 617.545 98.655 618.275 ; + RECT 98.955 617.545 99.155 618.275 ; + RECT 99.45 617.545 99.65 618.275 ; + RECT 99.735 0.3 99.995 4.63 ; + RECT 100.27 617.545 100.47 618.275 ; + RECT 100.755 0.17 101.525 0.43 ; + RECT 101.265 0.17 101.525 8.7 ; + RECT 100.755 0.17 101.015 16.7 ; + RECT 100.245 0.3 100.505 4.63 ; + RECT 100.765 617.545 100.965 618.275 ; + RECT 101.265 617.545 101.465 618.275 ; + RECT 101.765 617.545 101.965 618.275 ; + RECT 102.26 617.545 102.46 618.275 ; + RECT 103.08 617.545 103.28 618.275 ; + RECT 103.575 617.545 103.775 618.275 ; + RECT 104.075 617.545 104.275 618.275 ; + RECT 104.575 617.545 104.775 618.275 ; + RECT 105.07 617.545 105.27 618.275 ; + RECT 105.89 617.545 106.09 618.275 ; + RECT 106.385 617.545 106.585 618.275 ; + RECT 106.885 617.545 107.085 618.275 ; + RECT 107.385 617.545 107.585 618.275 ; + RECT 107.485 0.3 107.745 4.63 ; + RECT 108.505 0.165 109.275 0.425 ; + RECT 108.505 0.165 108.765 8.825 ; + RECT 109.015 0.165 109.275 8.825 ; + RECT 107.88 617.545 108.08 618.275 ; + RECT 107.995 0.3 108.255 4.63 ; + RECT 108.7 617.545 108.9 618.275 ; + RECT 109.195 617.545 109.395 618.275 ; + RECT 109.695 617.545 109.895 618.275 ; + RECT 109.935 0.52 110.195 4.5 ; + RECT 110.195 617.545 110.395 618.275 ; + RECT 110.69 617.545 110.89 618.275 ; + RECT 111.51 617.545 111.71 618.275 ; + RECT 112.005 617.545 112.205 618.275 ; + RECT 112.505 617.545 112.705 618.275 ; + RECT 113.005 617.545 113.205 618.275 ; + RECT 113.5 617.545 113.7 618.275 ; + RECT 114.32 617.545 114.52 618.275 ; + RECT 114.815 617.545 115.015 618.275 ; + RECT 115.315 617.545 115.515 618.275 ; + RECT 115.815 617.545 116.015 618.275 ; + RECT 116.31 617.545 116.51 618.275 ; + RECT 117.13 617.545 117.33 618.275 ; + RECT 117.625 617.545 117.825 618.275 ; + RECT 118.125 617.545 118.325 618.275 ; + RECT 118.625 617.545 118.825 618.275 ; + RECT 119.12 617.545 119.32 618.275 ; + RECT 119.94 617.545 120.14 618.275 ; + RECT 120.435 617.545 120.635 618.275 ; + RECT 120.935 617.545 121.135 618.275 ; + RECT 121.435 617.545 121.635 618.275 ; + RECT 121.93 617.545 122.13 618.275 ; + RECT 122.75 617.545 122.95 618.275 ; + RECT 123.705 0.16 124.475 0.42 ; + RECT 124.215 0.16 124.475 4.63 ; + RECT 123.705 0.16 123.965 8.82 ; + RECT 123.245 617.545 123.445 618.275 ; + RECT 123.745 617.545 123.945 618.275 ; + RECT 124.245 617.545 124.445 618.275 ; + RECT 124.74 617.545 124.94 618.275 ; + RECT 124.725 0.3 124.985 4.63 ; + RECT 125.235 0.3 125.495 4.63 ; + RECT 125.56 617.545 125.76 618.275 ; + RECT 126.055 617.545 126.255 618.275 ; + RECT 126.555 617.545 126.755 618.275 ; + RECT 128.24 0.16 129.01 0.42 ; + RECT 128.24 0.16 128.5 8.82 ; + RECT 128.75 0.16 129.01 8.82 ; + RECT 127.055 617.545 127.255 618.275 ; + RECT 127.55 617.545 127.75 618.275 ; + RECT 128.37 617.545 128.57 618.275 ; + RECT 128.865 617.545 129.065 618.275 ; + RECT 129.26 0.3 129.52 4.63 ; + RECT 129.365 617.545 129.565 618.275 ; + RECT 129.77 0.3 130.03 4.63 ; + RECT 129.865 617.545 130.065 618.275 ; + RECT 130.36 617.545 130.56 618.275 ; + RECT 131.18 617.545 131.38 618.275 ; + RECT 131.675 617.545 131.875 618.275 ; + RECT 131.71 0.52 131.97 4.5 ; + RECT 132.175 617.545 132.375 618.275 ; + RECT 132.675 617.545 132.875 618.275 ; + RECT 133.17 617.545 133.37 618.275 ; + RECT 134.415 0.165 135.185 0.425 ; + RECT 134.415 0.165 134.675 8.825 ; + RECT 134.925 0.165 135.185 8.825 ; + RECT 133.99 617.545 134.19 618.275 ; + RECT 134.485 617.545 134.685 618.275 ; + RECT 134.985 617.545 135.185 618.275 ; + RECT 135.485 617.545 135.685 618.275 ; + RECT 135.435 0.3 135.695 4.63 ; + RECT 135.98 617.545 136.18 618.275 ; + RECT 135.945 0.3 136.205 8.23 ; + RECT 136.8 617.545 137 618.275 ; + RECT 137.295 617.545 137.495 618.275 ; + RECT 137.795 617.545 137.995 618.275 ; + RECT 138.295 617.545 138.495 618.275 ; + RECT 138.79 617.545 138.99 618.275 ; + RECT 140.105 0.17 140.875 0.43 ; + RECT 140.615 0.17 140.875 11.38 ; + RECT 140.105 0.17 140.365 16.7 ; + RECT 139.61 617.545 139.81 618.275 ; + RECT 140.105 617.545 140.305 618.275 ; + RECT 140.605 617.545 140.805 618.275 ; + RECT 141.105 617.545 141.305 618.275 ; + RECT 141.6 617.545 141.8 618.275 ; + RECT 142.42 617.545 142.62 618.275 ; + RECT 143.675 0.17 144.445 0.43 ; + RECT 144.185 0.17 144.445 8.7 ; + RECT 143.675 0.17 143.935 16.7 ; + RECT 142.915 617.545 143.115 618.275 ; + RECT 143.415 617.545 143.615 618.275 ; + RECT 143.915 617.545 144.115 618.275 ; + RECT 144.41 617.545 144.61 618.275 ; + RECT 144.695 0.3 144.955 4.63 ; + RECT 145.23 617.545 145.43 618.275 ; + RECT 145.715 0.17 146.485 0.43 ; + RECT 146.225 0.17 146.485 8.7 ; + RECT 145.715 0.17 145.975 16.7 ; + RECT 145.205 0.3 145.465 4.63 ; + RECT 145.725 617.545 145.925 618.275 ; + RECT 146.225 617.545 146.425 618.275 ; + RECT 146.725 617.545 146.925 618.275 ; + RECT 147.22 617.545 147.42 618.275 ; + RECT 148.04 617.545 148.24 618.275 ; + RECT 148.535 617.545 148.735 618.275 ; + RECT 149.035 617.545 149.235 618.275 ; + RECT 149.535 617.545 149.735 618.275 ; + RECT 150.03 617.545 150.23 618.275 ; + RECT 150.85 617.545 151.05 618.275 ; + RECT 151.345 617.545 151.545 618.275 ; + RECT 151.845 617.545 152.045 618.275 ; + RECT 152.345 617.545 152.545 618.275 ; + RECT 152.445 0.3 152.705 4.63 ; + RECT 153.465 0.165 154.235 0.425 ; + RECT 153.465 0.165 153.725 8.825 ; + RECT 153.975 0.165 154.235 8.825 ; + RECT 152.84 617.545 153.04 618.275 ; + RECT 152.955 0.3 153.215 4.63 ; + RECT 153.66 617.545 153.86 618.275 ; + RECT 154.155 617.545 154.355 618.275 ; + RECT 154.655 617.545 154.855 618.275 ; + RECT 154.895 0.52 155.155 4.5 ; + RECT 155.155 617.545 155.355 618.275 ; + RECT 155.65 617.545 155.85 618.275 ; + RECT 156.47 617.545 156.67 618.275 ; + RECT 156.965 617.545 157.165 618.275 ; + RECT 157.465 617.545 157.665 618.275 ; + RECT 157.965 617.545 158.165 618.275 ; + RECT 158.46 617.545 158.66 618.275 ; + RECT 159.28 617.545 159.48 618.275 ; + RECT 159.775 617.545 159.975 618.275 ; + RECT 160.275 617.545 160.475 618.275 ; + RECT 160.775 617.545 160.975 618.275 ; + RECT 161.27 617.545 161.47 618.275 ; + RECT 162.09 617.545 162.29 618.275 ; + RECT 162.585 617.545 162.785 618.275 ; + RECT 163.085 617.545 163.285 618.275 ; + RECT 163.585 617.545 163.785 618.275 ; + RECT 164.08 617.545 164.28 618.275 ; + RECT 164.9 617.545 165.1 618.275 ; + RECT 165.395 617.545 165.595 618.275 ; + RECT 165.895 617.545 166.095 618.275 ; + RECT 166.395 617.545 166.595 618.275 ; + RECT 166.89 617.545 167.09 618.275 ; + RECT 167.71 617.545 167.91 618.275 ; + RECT 168.665 0.16 169.435 0.42 ; + RECT 169.175 0.16 169.435 4.63 ; + RECT 168.665 0.16 168.925 8.82 ; + RECT 168.205 617.545 168.405 618.275 ; + RECT 168.705 617.545 168.905 618.275 ; + RECT 169.205 617.545 169.405 618.275 ; + RECT 169.7 617.545 169.9 618.275 ; + RECT 169.685 0.3 169.945 4.63 ; + RECT 170.195 0.3 170.455 4.63 ; + RECT 170.52 617.545 170.72 618.275 ; + RECT 171.015 617.545 171.215 618.275 ; + RECT 171.515 617.545 171.715 618.275 ; + RECT 173.2 0.16 173.97 0.42 ; + RECT 173.2 0.16 173.46 8.82 ; + RECT 173.71 0.16 173.97 8.82 ; + RECT 172.015 617.545 172.215 618.275 ; + RECT 172.51 617.545 172.71 618.275 ; + RECT 173.33 617.545 173.53 618.275 ; + RECT 173.825 617.545 174.025 618.275 ; + RECT 174.22 0.3 174.48 4.63 ; + RECT 174.325 617.545 174.525 618.275 ; + RECT 174.73 0.3 174.99 4.63 ; + RECT 174.825 617.545 175.025 618.275 ; + RECT 175.32 617.545 175.52 618.275 ; + RECT 176.14 617.545 176.34 618.275 ; + RECT 176.635 617.545 176.835 618.275 ; + RECT 176.67 0.52 176.93 4.5 ; + RECT 177.135 617.545 177.335 618.275 ; + RECT 177.635 617.545 177.835 618.275 ; + RECT 178.13 617.545 178.33 618.275 ; + RECT 179.375 0.165 180.145 0.425 ; + RECT 179.375 0.165 179.635 8.825 ; + RECT 179.885 0.165 180.145 8.825 ; + RECT 178.95 617.545 179.15 618.275 ; + RECT 179.445 617.545 179.645 618.275 ; + RECT 179.945 617.545 180.145 618.275 ; + RECT 180.445 617.545 180.645 618.275 ; + RECT 180.395 0.3 180.655 4.63 ; + RECT 180.94 617.545 181.14 618.275 ; + RECT 180.905 0.3 181.165 8.23 ; + RECT 181.76 617.545 181.96 618.275 ; + RECT 182.255 617.545 182.455 618.275 ; + RECT 182.755 617.545 182.955 618.275 ; + RECT 183.255 617.545 183.455 618.275 ; + RECT 183.75 617.545 183.95 618.275 ; + RECT 185.065 0.17 185.835 0.43 ; + RECT 185.575 0.17 185.835 11.38 ; + RECT 185.065 0.17 185.325 16.7 ; + RECT 184.57 617.545 184.77 618.275 ; + RECT 185.065 617.545 185.265 618.275 ; + RECT 185.565 617.545 185.765 618.275 ; + RECT 186.065 617.545 186.265 618.275 ; + RECT 186.56 617.545 186.76 618.275 ; + RECT 187.38 617.545 187.58 618.275 ; + RECT 188.635 0.17 189.405 0.43 ; + RECT 189.145 0.17 189.405 8.7 ; + RECT 188.635 0.17 188.895 16.7 ; + RECT 187.875 617.545 188.075 618.275 ; + RECT 188.375 617.545 188.575 618.275 ; + RECT 188.875 617.545 189.075 618.275 ; + RECT 189.37 617.545 189.57 618.275 ; + RECT 189.655 0.3 189.915 4.63 ; + RECT 190.19 617.545 190.39 618.275 ; + RECT 190.675 0.17 191.445 0.43 ; + RECT 191.185 0.17 191.445 8.7 ; + RECT 190.675 0.17 190.935 16.7 ; + RECT 190.165 0.3 190.425 4.63 ; + RECT 190.685 617.545 190.885 618.275 ; + RECT 191.185 617.545 191.385 618.275 ; + RECT 191.685 617.545 191.885 618.275 ; + RECT 192.18 617.545 192.38 618.275 ; + RECT 193 617.545 193.2 618.275 ; + RECT 193.495 617.545 193.695 618.275 ; + RECT 193.995 617.545 194.195 618.275 ; + RECT 194.495 617.545 194.695 618.275 ; + RECT 194.99 617.545 195.19 618.275 ; + RECT 195.81 617.545 196.01 618.275 ; + RECT 196.305 617.545 196.505 618.275 ; + RECT 196.805 617.545 197.005 618.275 ; + RECT 197.305 617.545 197.505 618.275 ; + RECT 197.405 0.3 197.665 4.63 ; + RECT 198.425 0.165 199.195 0.425 ; + RECT 198.425 0.165 198.685 8.825 ; + RECT 198.935 0.165 199.195 8.825 ; + RECT 197.8 617.545 198 618.275 ; + RECT 197.915 0.3 198.175 4.63 ; + RECT 198.62 617.545 198.82 618.275 ; + RECT 199.115 617.545 199.315 618.275 ; + RECT 199.615 617.545 199.815 618.275 ; + RECT 199.855 0.52 200.115 4.5 ; + RECT 200.115 617.545 200.315 618.275 ; + RECT 200.61 617.545 200.81 618.275 ; + RECT 201.43 617.545 201.63 618.275 ; + RECT 201.925 617.545 202.125 618.275 ; + RECT 202.425 617.545 202.625 618.275 ; + RECT 202.925 617.545 203.125 618.275 ; + RECT 203.42 617.545 203.62 618.275 ; + RECT 204.24 617.545 204.44 618.275 ; + RECT 204.735 617.545 204.935 618.275 ; + RECT 205.235 617.545 205.435 618.275 ; + RECT 205.735 617.545 205.935 618.275 ; + RECT 206.23 617.545 206.43 618.275 ; + RECT 207.05 617.545 207.25 618.275 ; + RECT 207.545 617.545 207.745 618.275 ; + RECT 208.045 617.545 208.245 618.275 ; + RECT 208.545 617.545 208.745 618.275 ; + RECT 209.04 617.545 209.24 618.275 ; + RECT 209.86 617.545 210.06 618.275 ; + RECT 210.355 617.545 210.555 618.275 ; + RECT 210.855 617.545 211.055 618.275 ; + RECT 211.355 617.545 211.555 618.275 ; + RECT 211.85 617.545 212.05 618.275 ; + RECT 212.67 617.545 212.87 618.275 ; + RECT 213.625 0.16 214.395 0.42 ; + RECT 214.135 0.16 214.395 4.63 ; + RECT 213.625 0.16 213.885 8.82 ; + RECT 213.165 617.545 213.365 618.275 ; + RECT 213.665 617.545 213.865 618.275 ; + RECT 214.165 617.545 214.365 618.275 ; + RECT 214.66 617.545 214.86 618.275 ; + RECT 214.645 0.3 214.905 4.63 ; + RECT 215.155 0.3 215.415 4.63 ; + RECT 215.48 617.545 215.68 618.275 ; + RECT 215.975 617.545 216.175 618.275 ; + RECT 216.475 617.545 216.675 618.275 ; + RECT 218.16 0.16 218.93 0.42 ; + RECT 218.16 0.16 218.42 8.82 ; + RECT 218.67 0.16 218.93 8.82 ; + RECT 216.975 617.545 217.175 618.275 ; + RECT 217.47 617.545 217.67 618.275 ; + RECT 218.29 617.545 218.49 618.275 ; + RECT 218.785 617.545 218.985 618.275 ; + RECT 219.18 0.3 219.44 4.63 ; + RECT 219.285 617.545 219.485 618.275 ; + RECT 219.69 0.3 219.95 4.63 ; + RECT 219.785 617.545 219.985 618.275 ; + RECT 220.28 617.545 220.48 618.275 ; + RECT 221.1 617.545 221.3 618.275 ; + RECT 221.595 617.545 221.795 618.275 ; + RECT 221.63 0.52 221.89 4.5 ; + RECT 222.095 617.545 222.295 618.275 ; + RECT 222.595 617.545 222.795 618.275 ; + RECT 223.09 617.545 223.29 618.275 ; + RECT 224.335 0.165 225.105 0.425 ; + RECT 224.335 0.165 224.595 8.825 ; + RECT 224.845 0.165 225.105 8.825 ; + RECT 223.91 617.545 224.11 618.275 ; + RECT 224.405 617.545 224.605 618.275 ; + RECT 224.905 617.545 225.105 618.275 ; + RECT 225.405 617.545 225.605 618.275 ; + RECT 225.355 0.3 225.615 4.63 ; + RECT 225.9 617.545 226.1 618.275 ; + RECT 225.865 0.3 226.125 8.23 ; + RECT 226.72 617.545 226.92 618.275 ; + RECT 227.215 617.545 227.415 618.275 ; + RECT 227.715 617.545 227.915 618.275 ; + RECT 228.215 617.545 228.415 618.275 ; + RECT 228.71 617.545 228.91 618.275 ; + RECT 230.025 0.17 230.795 0.43 ; + RECT 230.535 0.17 230.795 11.38 ; + RECT 230.025 0.17 230.285 16.7 ; + RECT 229.53 617.545 229.73 618.275 ; + RECT 230.025 617.545 230.225 618.275 ; + RECT 230.525 617.545 230.725 618.275 ; + RECT 231.025 617.545 231.225 618.275 ; + RECT 231.52 617.545 231.72 618.275 ; + RECT 232.34 617.545 232.54 618.275 ; + RECT 233.595 0.17 234.365 0.43 ; + RECT 234.105 0.17 234.365 8.7 ; + RECT 233.595 0.17 233.855 16.7 ; + RECT 232.835 617.545 233.035 618.275 ; + RECT 233.335 617.545 233.535 618.275 ; + RECT 233.835 617.545 234.035 618.275 ; + RECT 234.33 617.545 234.53 618.275 ; + RECT 234.615 0.3 234.875 4.63 ; + RECT 235.15 617.545 235.35 618.275 ; + RECT 235.635 0.17 236.405 0.43 ; + RECT 236.145 0.17 236.405 8.7 ; + RECT 235.635 0.17 235.895 16.7 ; + RECT 235.125 0.3 235.385 4.63 ; + RECT 235.645 617.545 235.845 618.275 ; + RECT 236.145 617.545 236.345 618.275 ; + RECT 236.645 617.545 236.845 618.275 ; + RECT 237.14 617.545 237.34 618.275 ; + RECT 237.96 617.545 238.16 618.275 ; + RECT 238.455 617.545 238.655 618.275 ; + RECT 238.955 617.545 239.155 618.275 ; + RECT 239.455 617.545 239.655 618.275 ; + RECT 239.95 617.545 240.15 618.275 ; + RECT 240.77 617.545 240.97 618.275 ; + RECT 241.265 617.545 241.465 618.275 ; + RECT 241.765 617.545 241.965 618.275 ; + RECT 242.265 617.545 242.465 618.275 ; + RECT 242.365 0.3 242.625 4.63 ; + RECT 243.385 0.165 244.155 0.425 ; + RECT 243.385 0.165 243.645 8.825 ; + RECT 243.895 0.165 244.155 8.825 ; + RECT 242.76 617.545 242.96 618.275 ; + RECT 242.875 0.3 243.135 4.63 ; + RECT 243.58 617.545 243.78 618.275 ; + RECT 244.075 617.545 244.275 618.275 ; + RECT 244.575 617.545 244.775 618.275 ; + RECT 244.815 0.52 245.075 4.5 ; + RECT 245.075 617.545 245.275 618.275 ; + RECT 245.57 617.545 245.77 618.275 ; + RECT 246.39 617.545 246.59 618.275 ; + RECT 246.885 617.545 247.085 618.275 ; + RECT 247.385 617.545 247.585 618.275 ; + RECT 247.885 617.545 248.085 618.275 ; + RECT 248.38 617.545 248.58 618.275 ; + RECT 249.2 617.545 249.4 618.275 ; + RECT 249.695 617.545 249.895 618.275 ; + RECT 250.195 617.545 250.395 618.275 ; + RECT 250.695 617.545 250.895 618.275 ; + RECT 251.19 617.545 251.39 618.275 ; + RECT 252.01 617.545 252.21 618.275 ; + RECT 252.505 617.545 252.705 618.275 ; + RECT 253.005 617.545 253.205 618.275 ; + RECT 253.505 617.545 253.705 618.275 ; + RECT 254 617.545 254.2 618.275 ; + RECT 254.82 617.545 255.02 618.275 ; + RECT 255.315 617.545 255.515 618.275 ; + RECT 255.815 617.545 256.015 618.275 ; + RECT 256.315 617.545 256.515 618.275 ; + RECT 256.81 617.545 257.01 618.275 ; + RECT 257.63 617.545 257.83 618.275 ; + RECT 258.585 0.16 259.355 0.42 ; + RECT 259.095 0.16 259.355 4.63 ; + RECT 258.585 0.16 258.845 8.82 ; + RECT 258.125 617.545 258.325 618.275 ; + RECT 258.625 617.545 258.825 618.275 ; + RECT 259.125 617.545 259.325 618.275 ; + RECT 259.62 617.545 259.82 618.275 ; + RECT 259.605 0.3 259.865 4.63 ; + RECT 260.115 0.3 260.375 4.63 ; + RECT 260.44 617.545 260.64 618.275 ; + RECT 260.935 617.545 261.135 618.275 ; + RECT 261.435 617.545 261.635 618.275 ; + RECT 263.12 0.16 263.89 0.42 ; + RECT 263.12 0.16 263.38 8.82 ; + RECT 263.63 0.16 263.89 8.82 ; + RECT 261.935 617.545 262.135 618.275 ; + RECT 262.43 617.545 262.63 618.275 ; + RECT 263.25 617.545 263.45 618.275 ; + RECT 263.745 617.545 263.945 618.275 ; + RECT 264.14 0.3 264.4 4.63 ; + RECT 264.245 617.545 264.445 618.275 ; + RECT 264.65 0.3 264.91 4.63 ; + RECT 264.745 617.545 264.945 618.275 ; + RECT 265.24 617.545 265.44 618.275 ; + RECT 266.06 617.545 266.26 618.275 ; + RECT 266.555 617.545 266.755 618.275 ; + RECT 266.59 0.52 266.85 4.5 ; + RECT 267.055 617.545 267.255 618.275 ; + RECT 267.555 617.545 267.755 618.275 ; + RECT 268.05 617.545 268.25 618.275 ; + RECT 269.295 0.165 270.065 0.425 ; + RECT 269.295 0.165 269.555 8.825 ; + RECT 269.805 0.165 270.065 8.825 ; + RECT 268.87 617.545 269.07 618.275 ; + RECT 269.365 617.545 269.565 618.275 ; + RECT 269.865 617.545 270.065 618.275 ; + RECT 270.365 617.545 270.565 618.275 ; + RECT 270.315 0.3 270.575 4.63 ; + RECT 270.86 617.545 271.06 618.275 ; + RECT 270.825 0.3 271.085 8.23 ; + RECT 271.68 617.545 271.88 618.275 ; + RECT 272.175 617.545 272.375 618.275 ; + RECT 272.675 617.545 272.875 618.275 ; + RECT 273.175 617.545 273.375 618.275 ; + RECT 273.67 617.545 273.87 618.275 ; + RECT 274.985 0.17 275.755 0.43 ; + RECT 275.495 0.17 275.755 11.38 ; + RECT 274.985 0.17 275.245 16.7 ; + RECT 274.49 617.545 274.69 618.275 ; + RECT 274.985 617.545 275.185 618.275 ; + RECT 275.485 617.545 275.685 618.275 ; + RECT 275.985 617.545 276.185 618.275 ; + RECT 276.48 617.545 276.68 618.275 ; + RECT 277.3 617.545 277.5 618.275 ; + RECT 278.555 0.17 279.325 0.43 ; + RECT 279.065 0.17 279.325 8.7 ; + RECT 278.555 0.17 278.815 16.7 ; + RECT 277.795 617.545 277.995 618.275 ; + RECT 278.295 617.545 278.495 618.275 ; + RECT 278.795 617.545 278.995 618.275 ; + RECT 279.29 617.545 279.49 618.275 ; + RECT 279.575 0.3 279.835 4.63 ; + RECT 280.11 617.545 280.31 618.275 ; + RECT 280.595 0.17 281.365 0.43 ; + RECT 281.105 0.17 281.365 8.7 ; + RECT 280.595 0.17 280.855 16.7 ; + RECT 280.085 0.3 280.345 4.63 ; + RECT 280.605 617.545 280.805 618.275 ; + RECT 281.105 617.545 281.305 618.275 ; + RECT 281.605 617.545 281.805 618.275 ; + RECT 282.1 617.545 282.3 618.275 ; + RECT 282.92 617.545 283.12 618.275 ; + RECT 283.415 617.545 283.615 618.275 ; + RECT 283.915 617.545 284.115 618.275 ; + RECT 284.415 617.545 284.615 618.275 ; + RECT 284.91 617.545 285.11 618.275 ; + RECT 285.73 617.545 285.93 618.275 ; + RECT 286.225 617.545 286.425 618.275 ; + RECT 286.725 617.545 286.925 618.275 ; + RECT 287.225 617.545 287.425 618.275 ; + RECT 287.325 0.3 287.585 4.63 ; + RECT 288.345 0.165 289.115 0.425 ; + RECT 288.345 0.165 288.605 8.825 ; + RECT 288.855 0.165 289.115 8.825 ; + RECT 287.72 617.545 287.92 618.275 ; + RECT 287.835 0.3 288.095 4.63 ; + RECT 288.54 617.545 288.74 618.275 ; + RECT 289.035 617.545 289.235 618.275 ; + RECT 289.535 617.545 289.735 618.275 ; + RECT 289.775 0.52 290.035 4.5 ; + RECT 290.035 617.545 290.235 618.275 ; + RECT 290.53 617.545 290.73 618.275 ; + RECT 291.35 617.545 291.55 618.275 ; + RECT 291.845 617.545 292.045 618.275 ; + RECT 292.345 617.545 292.545 618.275 ; + RECT 292.845 617.545 293.045 618.275 ; + RECT 293.34 617.545 293.54 618.275 ; + RECT 294.16 617.545 294.36 618.275 ; + RECT 294.655 617.545 294.855 618.275 ; + RECT 295.155 617.545 295.355 618.275 ; + RECT 295.655 617.545 295.855 618.275 ; + RECT 296.15 617.545 296.35 618.275 ; + RECT 296.97 617.545 297.17 618.275 ; + RECT 297.465 617.545 297.665 618.275 ; + RECT 297.965 617.545 298.165 618.275 ; + RECT 298.465 617.545 298.665 618.275 ; + RECT 298.96 617.545 299.16 618.275 ; + RECT 299.78 617.545 299.98 618.275 ; + RECT 300.275 617.545 300.475 618.275 ; + RECT 300.775 617.545 300.975 618.275 ; + RECT 301.275 617.545 301.475 618.275 ; + RECT 301.77 617.545 301.97 618.275 ; + RECT 302.59 617.545 302.79 618.275 ; + RECT 303.545 0.16 304.315 0.42 ; + RECT 304.055 0.16 304.315 4.63 ; + RECT 303.545 0.16 303.805 8.82 ; + RECT 303.085 617.545 303.285 618.275 ; + RECT 303.585 617.545 303.785 618.275 ; + RECT 304.085 617.545 304.285 618.275 ; + RECT 304.58 617.545 304.78 618.275 ; + RECT 304.565 0.3 304.825 4.63 ; + RECT 305.075 0.3 305.335 4.63 ; + RECT 305.4 617.545 305.6 618.275 ; + RECT 305.895 617.545 306.095 618.275 ; + RECT 306.395 617.545 306.595 618.275 ; + RECT 308.08 0.16 308.85 0.42 ; + RECT 308.08 0.16 308.34 8.82 ; + RECT 308.59 0.16 308.85 8.82 ; + RECT 306.895 617.545 307.095 618.275 ; + RECT 307.39 617.545 307.59 618.275 ; + RECT 308.21 617.545 308.41 618.275 ; + RECT 308.705 617.545 308.905 618.275 ; + RECT 309.1 0.3 309.36 4.63 ; + RECT 309.205 617.545 309.405 618.275 ; + RECT 309.61 0.3 309.87 4.63 ; + RECT 309.705 617.545 309.905 618.275 ; + RECT 310.2 617.545 310.4 618.275 ; + RECT 311.02 617.545 311.22 618.275 ; + RECT 311.515 617.545 311.715 618.275 ; + RECT 311.55 0.52 311.81 4.5 ; + RECT 312.015 617.545 312.215 618.275 ; + RECT 312.515 617.545 312.715 618.275 ; + RECT 313.01 617.545 313.21 618.275 ; + RECT 314.255 0.165 315.025 0.425 ; + RECT 314.255 0.165 314.515 8.825 ; + RECT 314.765 0.165 315.025 8.825 ; + RECT 313.83 617.545 314.03 618.275 ; + RECT 314.325 617.545 314.525 618.275 ; + RECT 314.825 617.545 315.025 618.275 ; + RECT 315.325 617.545 315.525 618.275 ; + RECT 315.275 0.3 315.535 4.63 ; + RECT 315.82 617.545 316.02 618.275 ; + RECT 315.785 0.3 316.045 8.23 ; + RECT 316.64 617.545 316.84 618.275 ; + RECT 317.135 617.545 317.335 618.275 ; + RECT 317.635 617.545 317.835 618.275 ; + RECT 318.135 617.545 318.335 618.275 ; + RECT 318.63 617.545 318.83 618.275 ; + RECT 319.945 0.17 320.715 0.43 ; + RECT 320.455 0.17 320.715 11.38 ; + RECT 319.945 0.17 320.205 16.7 ; + RECT 319.45 617.545 319.65 618.275 ; + RECT 319.945 617.545 320.145 618.275 ; + RECT 320.445 617.545 320.645 618.275 ; + RECT 320.945 617.545 321.145 618.275 ; + RECT 321.44 617.545 321.64 618.275 ; + RECT 322.26 617.545 322.46 618.275 ; + RECT 323.515 0.17 324.285 0.43 ; + RECT 324.025 0.17 324.285 8.7 ; + RECT 323.515 0.17 323.775 16.7 ; + RECT 322.755 617.545 322.955 618.275 ; + RECT 323.255 617.545 323.455 618.275 ; + RECT 323.755 617.545 323.955 618.275 ; + RECT 324.25 617.545 324.45 618.275 ; + RECT 324.535 0.3 324.795 4.63 ; + RECT 325.07 617.545 325.27 618.275 ; + RECT 325.555 0.17 326.325 0.43 ; + RECT 326.065 0.17 326.325 8.7 ; + RECT 325.555 0.17 325.815 16.7 ; + RECT 325.045 0.3 325.305 4.63 ; + RECT 325.565 617.545 325.765 618.275 ; + RECT 326.065 617.545 326.265 618.275 ; + RECT 326.565 617.545 326.765 618.275 ; + RECT 327.06 617.545 327.26 618.275 ; + RECT 327.88 617.545 328.08 618.275 ; + RECT 328.375 617.545 328.575 618.275 ; + RECT 328.875 617.545 329.075 618.275 ; + RECT 329.375 617.545 329.575 618.275 ; + RECT 329.87 617.545 330.07 618.275 ; + RECT 330.69 617.545 330.89 618.275 ; + RECT 331.185 617.545 331.385 618.275 ; + RECT 331.685 617.545 331.885 618.275 ; + RECT 332.185 617.545 332.385 618.275 ; + RECT 332.285 0.3 332.545 4.63 ; + RECT 333.305 0.165 334.075 0.425 ; + RECT 333.305 0.165 333.565 8.825 ; + RECT 333.815 0.165 334.075 8.825 ; + RECT 332.68 617.545 332.88 618.275 ; + RECT 332.795 0.3 333.055 4.63 ; + RECT 333.5 617.545 333.7 618.275 ; + RECT 333.995 617.545 334.195 618.275 ; + RECT 334.495 617.545 334.695 618.275 ; + RECT 334.735 0.52 334.995 4.5 ; + RECT 334.995 617.545 335.195 618.275 ; + RECT 335.49 617.545 335.69 618.275 ; + RECT 336.31 617.545 336.51 618.275 ; + RECT 336.805 617.545 337.005 618.275 ; + RECT 337.305 617.545 337.505 618.275 ; + RECT 337.805 617.545 338.005 618.275 ; + RECT 338.3 617.545 338.5 618.275 ; + RECT 339.12 617.545 339.32 618.275 ; + RECT 339.615 617.545 339.815 618.275 ; + RECT 340.115 617.545 340.315 618.275 ; + RECT 340.615 617.545 340.815 618.275 ; + RECT 341.11 617.545 341.31 618.275 ; + RECT 341.93 617.545 342.13 618.275 ; + RECT 342.425 617.545 342.625 618.275 ; + RECT 342.925 617.545 343.125 618.275 ; + RECT 343.425 617.545 343.625 618.275 ; + RECT 343.92 617.545 344.12 618.275 ; + RECT 344.74 617.545 344.94 618.275 ; + RECT 345.235 617.545 345.435 618.275 ; + RECT 345.735 617.545 345.935 618.275 ; + RECT 346.235 617.545 346.435 618.275 ; + RECT 346.73 617.545 346.93 618.275 ; + RECT 347.55 617.545 347.75 618.275 ; + RECT 348.505 0.16 349.275 0.42 ; + RECT 349.015 0.16 349.275 4.63 ; + RECT 348.505 0.16 348.765 8.82 ; + RECT 348.045 617.545 348.245 618.275 ; + RECT 348.545 617.545 348.745 618.275 ; + RECT 349.045 617.545 349.245 618.275 ; + RECT 349.54 617.545 349.74 618.275 ; + RECT 349.525 0.3 349.785 4.63 ; + RECT 350.035 0.3 350.295 4.63 ; + RECT 350.36 617.545 350.56 618.275 ; + RECT 350.855 617.545 351.055 618.275 ; + RECT 351.355 617.545 351.555 618.275 ; + RECT 353.04 0.16 353.81 0.42 ; + RECT 353.04 0.16 353.3 8.82 ; + RECT 353.55 0.16 353.81 8.82 ; + RECT 351.855 617.545 352.055 618.275 ; + RECT 352.35 617.545 352.55 618.275 ; + RECT 353.17 617.545 353.37 618.275 ; + RECT 353.665 617.545 353.865 618.275 ; + RECT 354.06 0.3 354.32 4.63 ; + RECT 354.165 617.545 354.365 618.275 ; + RECT 354.57 0.3 354.83 4.63 ; + RECT 354.665 617.545 354.865 618.275 ; + RECT 355.16 617.545 355.36 618.275 ; + RECT 355.98 617.545 356.18 618.275 ; + RECT 356.475 617.545 356.675 618.275 ; + RECT 356.51 0.52 356.77 4.5 ; + RECT 356.975 617.545 357.175 618.275 ; + RECT 357.475 617.545 357.675 618.275 ; + RECT 357.97 617.545 358.17 618.275 ; + RECT 359.215 0.165 359.985 0.425 ; + RECT 359.215 0.165 359.475 8.825 ; + RECT 359.725 0.165 359.985 8.825 ; + RECT 358.79 617.545 358.99 618.275 ; + RECT 359.285 617.545 359.485 618.275 ; + RECT 359.785 617.545 359.985 618.275 ; + RECT 360.285 617.545 360.485 618.275 ; + RECT 360.235 0.3 360.495 4.63 ; + RECT 360.78 617.545 360.98 618.275 ; + RECT 360.745 0.3 361.005 8.23 ; + RECT 361.6 617.545 361.8 618.275 ; + RECT 362.095 617.545 362.295 618.275 ; + RECT 362.595 617.545 362.795 618.275 ; + RECT 363.095 617.545 363.295 618.275 ; + RECT 363.59 617.545 363.79 618.275 ; + RECT 364.905 0.17 365.675 0.43 ; + RECT 365.415 0.17 365.675 11.38 ; + RECT 364.905 0.17 365.165 16.7 ; + RECT 364.41 617.545 364.61 618.275 ; + RECT 364.905 617.545 365.105 618.275 ; + RECT 365.405 617.545 365.605 618.275 ; + RECT 365.905 617.545 366.105 618.275 ; + RECT 366.4 617.545 366.6 618.275 ; + RECT 367.22 617.545 367.42 618.275 ; + RECT 368.475 0.17 369.245 0.43 ; + RECT 368.985 0.17 369.245 8.7 ; + RECT 368.475 0.17 368.735 16.7 ; + RECT 367.715 617.545 367.915 618.275 ; + RECT 368.215 617.545 368.415 618.275 ; + RECT 368.715 617.545 368.915 618.275 ; + RECT 369.21 617.545 369.41 618.275 ; + RECT 369.495 0.3 369.755 4.63 ; + RECT 370.03 617.545 370.23 618.275 ; + RECT 370.515 0.17 371.285 0.43 ; + RECT 371.025 0.17 371.285 8.7 ; + RECT 370.515 0.17 370.775 16.7 ; + RECT 370.005 0.3 370.265 4.63 ; + RECT 370.525 617.545 370.725 618.275 ; + RECT 371.025 617.545 371.225 618.275 ; + RECT 371.525 617.545 371.725 618.275 ; + RECT 372.02 617.545 372.22 618.275 ; + RECT 372.84 617.545 373.04 618.275 ; + RECT 373.335 617.545 373.535 618.275 ; + RECT 373.835 617.545 374.035 618.275 ; + RECT 374.335 617.545 374.535 618.275 ; + RECT 374.83 617.545 375.03 618.275 ; + RECT 375.65 617.545 375.85 618.275 ; + RECT 376.145 617.545 376.345 618.275 ; + RECT 376.645 617.545 376.845 618.275 ; + RECT 377.145 617.545 377.345 618.275 ; + RECT 377.245 0.3 377.505 4.63 ; + RECT 378.265 0.165 379.035 0.425 ; + RECT 378.265 0.165 378.525 8.825 ; + RECT 378.775 0.165 379.035 8.825 ; + RECT 377.64 617.545 377.84 618.275 ; + RECT 377.755 0.3 378.015 4.63 ; + RECT 378.46 617.545 378.66 618.275 ; + RECT 378.955 617.545 379.155 618.275 ; + RECT 379.455 617.545 379.655 618.275 ; + RECT 379.695 0.52 379.955 4.5 ; + RECT 379.955 617.545 380.155 618.275 ; + RECT 380.45 617.545 380.65 618.275 ; + RECT 381.27 617.545 381.47 618.275 ; + RECT 381.765 617.545 381.965 618.275 ; + RECT 382.265 617.545 382.465 618.275 ; + RECT 382.765 617.545 382.965 618.275 ; + RECT 383.26 617.545 383.46 618.275 ; + RECT 384.08 617.545 384.28 618.275 ; + RECT 384.575 617.545 384.775 618.275 ; + RECT 385.075 617.545 385.275 618.275 ; + RECT 385.575 617.545 385.775 618.275 ; + RECT 386.07 617.545 386.27 618.275 ; + RECT 386.89 617.545 387.09 618.275 ; + RECT 387.385 617.545 387.585 618.275 ; + RECT 387.885 617.545 388.085 618.275 ; + RECT 388.385 617.545 388.585 618.275 ; + RECT 388.88 617.545 389.08 618.275 ; + RECT 389.7 617.545 389.9 618.275 ; + RECT 390.195 617.545 390.395 618.275 ; + RECT 390.695 617.545 390.895 618.275 ; + RECT 391.195 617.545 391.395 618.275 ; + RECT 391.69 617.545 391.89 618.275 ; + RECT 392.51 617.545 392.71 618.275 ; + RECT 393.465 0.16 394.235 0.42 ; + RECT 393.975 0.16 394.235 4.63 ; + RECT 393.465 0.16 393.725 8.82 ; + RECT 393.005 617.545 393.205 618.275 ; + RECT 393.505 617.545 393.705 618.275 ; + RECT 394.005 617.545 394.205 618.275 ; + RECT 394.5 617.545 394.7 618.275 ; + RECT 394.485 0.3 394.745 4.63 ; + RECT 394.995 0.3 395.255 4.63 ; + RECT 395.32 617.545 395.52 618.275 ; + RECT 395.815 617.545 396.015 618.275 ; + RECT 396.315 617.545 396.515 618.275 ; + RECT 398 0.16 398.77 0.42 ; + RECT 398 0.16 398.26 8.82 ; + RECT 398.51 0.16 398.77 8.82 ; + RECT 396.815 617.545 397.015 618.275 ; + RECT 397.31 617.545 397.51 618.275 ; + RECT 398.13 617.545 398.33 618.275 ; + RECT 398.625 617.545 398.825 618.275 ; + RECT 399.02 0.3 399.28 4.63 ; + RECT 399.125 617.545 399.325 618.275 ; + RECT 399.53 0.3 399.79 4.63 ; + RECT 399.625 617.545 399.825 618.275 ; + RECT 400.12 617.545 400.32 618.275 ; + RECT 400.94 617.545 401.14 618.275 ; + RECT 401.435 617.545 401.635 618.275 ; + RECT 401.47 0.52 401.73 4.5 ; + RECT 401.935 617.545 402.135 618.275 ; + RECT 402.435 617.545 402.635 618.275 ; + RECT 402.93 617.545 403.13 618.275 ; + RECT 404.175 0.165 404.945 0.425 ; + RECT 404.175 0.165 404.435 8.825 ; + RECT 404.685 0.165 404.945 8.825 ; + RECT 403.75 617.545 403.95 618.275 ; + RECT 404.245 617.545 404.445 618.275 ; + RECT 404.745 617.545 404.945 618.275 ; + RECT 405.245 617.545 405.445 618.275 ; + RECT 405.195 0.3 405.455 4.63 ; + RECT 405.74 617.545 405.94 618.275 ; + RECT 405.705 0.3 405.965 8.23 ; + RECT 406.56 617.545 406.76 618.275 ; + RECT 407.055 617.545 407.255 618.275 ; + RECT 407.555 617.545 407.755 618.275 ; + RECT 408.055 617.545 408.255 618.275 ; + RECT 408.55 617.545 408.75 618.275 ; + RECT 409.865 0.17 410.635 0.43 ; + RECT 410.375 0.17 410.635 11.38 ; + RECT 409.865 0.17 410.125 16.7 ; + RECT 409.37 617.545 409.57 618.275 ; + RECT 409.865 617.545 410.065 618.275 ; + RECT 410.365 617.545 410.565 618.275 ; + RECT 410.865 617.545 411.065 618.275 ; + RECT 411.36 617.545 411.56 618.275 ; + RECT 412.18 617.545 412.38 618.275 ; + RECT 413.435 0.17 414.205 0.43 ; + RECT 413.945 0.17 414.205 8.7 ; + RECT 413.435 0.17 413.695 16.7 ; + RECT 412.675 617.545 412.875 618.275 ; + RECT 413.175 617.545 413.375 618.275 ; + RECT 413.675 617.545 413.875 618.275 ; + RECT 414.17 617.545 414.37 618.275 ; + RECT 414.455 0.3 414.715 4.63 ; + RECT 414.99 617.545 415.19 618.275 ; + RECT 415.475 0.17 416.245 0.43 ; + RECT 415.985 0.17 416.245 8.7 ; + RECT 415.475 0.17 415.735 16.7 ; + RECT 414.965 0.3 415.225 4.63 ; + RECT 415.485 617.545 415.685 618.275 ; + RECT 415.985 617.545 416.185 618.275 ; + RECT 416.485 617.545 416.685 618.275 ; + RECT 416.98 617.545 417.18 618.275 ; + RECT 417.8 617.545 418 618.275 ; + RECT 418.295 617.545 418.495 618.275 ; + RECT 418.795 617.545 418.995 618.275 ; + RECT 419.295 617.545 419.495 618.275 ; + RECT 419.79 617.545 419.99 618.275 ; + RECT 420.61 617.545 420.81 618.275 ; + RECT 421.105 617.545 421.305 618.275 ; + RECT 421.605 617.545 421.805 618.275 ; + RECT 422.105 617.545 422.305 618.275 ; + RECT 422.205 0.3 422.465 4.63 ; + RECT 423.225 0.165 423.995 0.425 ; + RECT 423.225 0.165 423.485 8.825 ; + RECT 423.735 0.165 423.995 8.825 ; + RECT 422.6 617.545 422.8 618.275 ; + RECT 422.715 0.3 422.975 4.63 ; + RECT 423.42 617.545 423.62 618.275 ; + RECT 423.915 617.545 424.115 618.275 ; + RECT 424.415 617.545 424.615 618.275 ; + RECT 424.655 0.52 424.915 4.5 ; + RECT 424.915 617.545 425.115 618.275 ; + RECT 425.41 617.545 425.61 618.275 ; + RECT 426.23 617.545 426.43 618.275 ; + RECT 426.725 617.545 426.925 618.275 ; + RECT 427.225 617.545 427.425 618.275 ; + RECT 427.725 617.545 427.925 618.275 ; + RECT 428.22 617.545 428.42 618.275 ; + RECT 429.04 617.545 429.24 618.275 ; + RECT 429.535 617.545 429.735 618.275 ; + RECT 430.035 617.545 430.235 618.275 ; + RECT 430.535 617.545 430.735 618.275 ; + RECT 431.03 617.545 431.23 618.275 ; + RECT 431.85 617.545 432.05 618.275 ; + RECT 432.345 617.545 432.545 618.275 ; + RECT 432.845 617.545 433.045 618.275 ; + RECT 433.345 617.545 433.545 618.275 ; + RECT 433.84 617.545 434.04 618.275 ; + RECT 434.66 617.545 434.86 618.275 ; + RECT 435.155 617.545 435.355 618.275 ; + RECT 435.655 617.545 435.855 618.275 ; + RECT 436.155 617.545 436.355 618.275 ; + RECT 436.65 617.545 436.85 618.275 ; + RECT 437.47 617.545 437.67 618.275 ; + RECT 438.425 0.16 439.195 0.42 ; + RECT 438.935 0.16 439.195 4.63 ; + RECT 438.425 0.16 438.685 8.82 ; + RECT 437.965 617.545 438.165 618.275 ; + RECT 438.465 617.545 438.665 618.275 ; + RECT 438.965 617.545 439.165 618.275 ; + RECT 439.46 617.545 439.66 618.275 ; + RECT 439.445 0.3 439.705 4.63 ; + RECT 439.955 0.3 440.215 4.63 ; + RECT 440.28 617.545 440.48 618.275 ; + RECT 440.775 617.545 440.975 618.275 ; + RECT 441.275 617.545 441.475 618.275 ; + RECT 442.96 0.16 443.73 0.42 ; + RECT 442.96 0.16 443.22 8.82 ; + RECT 443.47 0.16 443.73 8.82 ; + RECT 441.775 617.545 441.975 618.275 ; + RECT 442.27 617.545 442.47 618.275 ; + RECT 443.09 617.545 443.29 618.275 ; + RECT 443.585 617.545 443.785 618.275 ; + RECT 443.98 0.3 444.24 4.63 ; + RECT 444.085 617.545 444.285 618.275 ; + RECT 444.49 0.3 444.75 4.63 ; + RECT 444.585 617.545 444.785 618.275 ; + RECT 445.08 617.545 445.28 618.275 ; + RECT 445.9 617.545 446.1 618.275 ; + RECT 446.395 617.545 446.595 618.275 ; + RECT 446.43 0.52 446.69 4.5 ; + RECT 446.895 617.545 447.095 618.275 ; + RECT 447.395 617.545 447.595 618.275 ; + RECT 447.89 617.545 448.09 618.275 ; + RECT 449.135 0.165 449.905 0.425 ; + RECT 449.135 0.165 449.395 8.825 ; + RECT 449.645 0.165 449.905 8.825 ; + RECT 448.71 617.545 448.91 618.275 ; + RECT 449.205 617.545 449.405 618.275 ; + RECT 449.705 617.545 449.905 618.275 ; + RECT 450.205 617.545 450.405 618.275 ; + RECT 450.155 0.3 450.415 4.63 ; + RECT 450.7 617.545 450.9 618.275 ; + RECT 450.665 0.3 450.925 8.23 ; + RECT 451.52 617.545 451.72 618.275 ; + RECT 452.015 617.545 452.215 618.275 ; + RECT 452.515 617.545 452.715 618.275 ; + RECT 453.015 617.545 453.215 618.275 ; + RECT 453.51 617.545 453.71 618.275 ; + RECT 454.825 0.17 455.595 0.43 ; + RECT 455.335 0.17 455.595 11.38 ; + RECT 454.825 0.17 455.085 16.7 ; + RECT 454.33 617.545 454.53 618.275 ; + RECT 454.825 617.545 455.025 618.275 ; + RECT 455.325 617.545 455.525 618.275 ; + RECT 455.825 617.545 456.025 618.275 ; + RECT 456.32 617.545 456.52 618.275 ; + RECT 457.14 617.545 457.34 618.275 ; + RECT 458.395 0.17 459.165 0.43 ; + RECT 458.905 0.17 459.165 8.7 ; + RECT 458.395 0.17 458.655 16.7 ; + RECT 457.635 617.545 457.835 618.275 ; + RECT 458.135 617.545 458.335 618.275 ; + RECT 458.635 617.545 458.835 618.275 ; + RECT 459.13 617.545 459.33 618.275 ; + RECT 459.415 0.3 459.675 4.63 ; + RECT 459.95 617.545 460.15 618.275 ; + RECT 460.435 0.17 461.205 0.43 ; + RECT 460.945 0.17 461.205 8.7 ; + RECT 460.435 0.17 460.695 16.7 ; + RECT 459.925 0.3 460.185 4.63 ; + RECT 460.445 617.545 460.645 618.275 ; + RECT 460.945 617.545 461.145 618.275 ; + RECT 461.445 617.545 461.645 618.275 ; + RECT 461.94 617.545 462.14 618.275 ; + RECT 462.76 617.545 462.96 618.275 ; + RECT 463.255 617.545 463.455 618.275 ; + RECT 463.755 617.545 463.955 618.275 ; + RECT 464.255 617.545 464.455 618.275 ; + RECT 464.75 617.545 464.95 618.275 ; + RECT 465.57 617.545 465.77 618.275 ; + RECT 466.065 617.545 466.265 618.275 ; + RECT 466.565 617.545 466.765 618.275 ; + RECT 467.065 617.545 467.265 618.275 ; + RECT 467.165 0.3 467.425 4.63 ; + RECT 468.185 0.165 468.955 0.425 ; + RECT 468.185 0.165 468.445 8.825 ; + RECT 468.695 0.165 468.955 8.825 ; + RECT 467.56 617.545 467.76 618.275 ; + RECT 467.675 0.3 467.935 4.63 ; + RECT 468.38 617.545 468.58 618.275 ; + RECT 468.875 617.545 469.075 618.275 ; + RECT 469.375 617.545 469.575 618.275 ; + RECT 469.615 0.52 469.875 4.5 ; + RECT 469.875 617.545 470.075 618.275 ; + RECT 470.37 617.545 470.57 618.275 ; + RECT 471.19 617.545 471.39 618.275 ; + RECT 471.685 617.545 471.885 618.275 ; + RECT 472.185 617.545 472.385 618.275 ; + RECT 472.685 617.545 472.885 618.275 ; + RECT 473.18 617.545 473.38 618.275 ; + RECT 474 617.545 474.2 618.275 ; + RECT 474.495 617.545 474.695 618.275 ; + RECT 474.995 617.545 475.195 618.275 ; + RECT 475.495 617.545 475.695 618.275 ; + RECT 475.99 617.545 476.19 618.275 ; + RECT 476.81 617.545 477.01 618.275 ; + RECT 477.305 617.545 477.505 618.275 ; + RECT 477.805 617.545 478.005 618.275 ; + RECT 478.305 617.545 478.505 618.275 ; + RECT 478.8 617.545 479 618.275 ; + RECT 479.62 617.545 479.82 618.275 ; + RECT 480.115 617.545 480.315 618.275 ; + RECT 480.615 617.545 480.815 618.275 ; + RECT 481.115 617.545 481.315 618.275 ; + RECT 481.61 617.545 481.81 618.275 ; + RECT 482.43 617.545 482.63 618.275 ; + RECT 483.385 0.16 484.155 0.42 ; + RECT 483.895 0.16 484.155 4.63 ; + RECT 483.385 0.16 483.645 8.82 ; + RECT 482.925 617.545 483.125 618.275 ; + RECT 483.425 617.545 483.625 618.275 ; + RECT 483.925 617.545 484.125 618.275 ; + RECT 484.42 617.545 484.62 618.275 ; + RECT 484.405 0.3 484.665 4.63 ; + RECT 484.915 0.3 485.175 4.63 ; + RECT 485.24 617.545 485.44 618.275 ; + RECT 485.735 617.545 485.935 618.275 ; + RECT 486.235 617.545 486.435 618.275 ; + RECT 487.92 0.16 488.69 0.42 ; + RECT 487.92 0.16 488.18 8.82 ; + RECT 488.43 0.16 488.69 8.82 ; + RECT 486.735 617.545 486.935 618.275 ; + RECT 487.23 617.545 487.43 618.275 ; + RECT 488.05 617.545 488.25 618.275 ; + RECT 488.545 617.545 488.745 618.275 ; + RECT 488.94 0.3 489.2 4.63 ; + RECT 489.045 617.545 489.245 618.275 ; + RECT 489.45 0.3 489.71 4.63 ; + RECT 489.545 617.545 489.745 618.275 ; + RECT 490.04 617.545 490.24 618.275 ; + RECT 490.86 617.545 491.06 618.275 ; + RECT 491.355 617.545 491.555 618.275 ; + RECT 491.39 0.52 491.65 4.5 ; + RECT 491.855 617.545 492.055 618.275 ; + RECT 492.355 617.545 492.555 618.275 ; + RECT 492.85 617.545 493.05 618.275 ; + RECT 494.095 0.165 494.865 0.425 ; + RECT 494.095 0.165 494.355 8.825 ; + RECT 494.605 0.165 494.865 8.825 ; + RECT 493.67 617.545 493.87 618.275 ; + RECT 494.165 617.545 494.365 618.275 ; + RECT 494.665 617.545 494.865 618.275 ; + RECT 495.165 617.545 495.365 618.275 ; + RECT 495.115 0.3 495.375 4.63 ; + RECT 495.66 617.545 495.86 618.275 ; + RECT 495.625 0.3 495.885 8.23 ; + RECT 496.48 617.545 496.68 618.275 ; + RECT 496.975 617.545 497.175 618.275 ; + RECT 497.475 617.545 497.675 618.275 ; + RECT 497.975 617.545 498.175 618.275 ; + RECT 498.47 617.545 498.67 618.275 ; + RECT 499.785 0.17 500.555 0.43 ; + RECT 500.295 0.17 500.555 11.38 ; + RECT 499.785 0.17 500.045 16.7 ; + RECT 499.29 617.545 499.49 618.275 ; + RECT 499.785 617.545 499.985 618.275 ; + RECT 500.285 617.545 500.485 618.275 ; + RECT 500.785 617.545 500.985 618.275 ; + RECT 501.28 617.545 501.48 618.275 ; + RECT 502.1 617.545 502.3 618.275 ; + RECT 503.355 0.17 504.125 0.43 ; + RECT 503.865 0.17 504.125 8.7 ; + RECT 503.355 0.17 503.615 16.7 ; + RECT 502.595 617.545 502.795 618.275 ; + RECT 503.095 617.545 503.295 618.275 ; + RECT 503.595 617.545 503.795 618.275 ; + RECT 504.09 617.545 504.29 618.275 ; + RECT 504.375 0.3 504.635 4.63 ; + RECT 504.91 617.545 505.11 618.275 ; + RECT 505.395 0.17 506.165 0.43 ; + RECT 505.905 0.17 506.165 8.7 ; + RECT 505.395 0.17 505.655 16.7 ; + RECT 504.885 0.3 505.145 4.63 ; + RECT 505.405 617.545 505.605 618.275 ; + RECT 505.905 617.545 506.105 618.275 ; + RECT 506.405 617.545 506.605 618.275 ; + RECT 506.9 617.545 507.1 618.275 ; + RECT 507.72 617.545 507.92 618.275 ; + RECT 508.215 617.545 508.415 618.275 ; + RECT 508.715 617.545 508.915 618.275 ; + RECT 509.215 617.545 509.415 618.275 ; + RECT 509.71 617.545 509.91 618.275 ; + RECT 510.53 617.545 510.73 618.275 ; + RECT 511.025 617.545 511.225 618.275 ; + RECT 511.525 617.545 511.725 618.275 ; + RECT 512.025 617.545 512.225 618.275 ; + RECT 512.125 0.3 512.385 4.63 ; + RECT 513.145 0.165 513.915 0.425 ; + RECT 513.145 0.165 513.405 8.825 ; + RECT 513.655 0.165 513.915 8.825 ; + RECT 512.52 617.545 512.72 618.275 ; + RECT 512.635 0.3 512.895 4.63 ; + RECT 513.34 617.545 513.54 618.275 ; + RECT 513.835 617.545 514.035 618.275 ; + RECT 514.335 617.545 514.535 618.275 ; + RECT 514.575 0.52 514.835 4.5 ; + RECT 514.835 617.545 515.035 618.275 ; + RECT 515.33 617.545 515.53 618.275 ; + RECT 516.15 617.545 516.35 618.275 ; + RECT 516.645 617.545 516.845 618.275 ; + RECT 517.145 617.545 517.345 618.275 ; + RECT 517.645 617.545 517.845 618.275 ; + RECT 518.14 617.545 518.34 618.275 ; + RECT 518.96 617.545 519.16 618.275 ; + RECT 519.455 617.545 519.655 618.275 ; + RECT 519.955 617.545 520.155 618.275 ; + RECT 520.455 617.545 520.655 618.275 ; + RECT 520.95 617.545 521.15 618.275 ; + RECT 521.77 617.545 521.97 618.275 ; + RECT 522.265 617.545 522.465 618.275 ; + RECT 522.765 617.545 522.965 618.275 ; + RECT 523.265 617.545 523.465 618.275 ; + RECT 523.76 617.545 523.96 618.275 ; + RECT 524.58 617.545 524.78 618.275 ; + RECT 525.075 617.545 525.275 618.275 ; + RECT 525.575 617.545 525.775 618.275 ; + RECT 526.075 617.545 526.275 618.275 ; + RECT 526.57 617.545 526.77 618.275 ; + RECT 527.39 617.545 527.59 618.275 ; + RECT 528.345 0.16 529.115 0.42 ; + RECT 528.855 0.16 529.115 4.63 ; + RECT 528.345 0.16 528.605 8.82 ; + RECT 527.885 617.545 528.085 618.275 ; + RECT 528.385 617.545 528.585 618.275 ; + RECT 528.885 617.545 529.085 618.275 ; + RECT 529.38 617.545 529.58 618.275 ; + RECT 529.365 0.3 529.625 4.63 ; + RECT 529.875 0.3 530.135 4.63 ; + RECT 530.2 617.545 530.4 618.275 ; + RECT 530.695 617.545 530.895 618.275 ; + RECT 531.195 617.545 531.395 618.275 ; + RECT 532.88 0.16 533.65 0.42 ; + RECT 532.88 0.16 533.14 8.82 ; + RECT 533.39 0.16 533.65 8.82 ; + RECT 531.695 617.545 531.895 618.275 ; + RECT 532.19 617.545 532.39 618.275 ; + RECT 533.01 617.545 533.21 618.275 ; + RECT 533.505 617.545 533.705 618.275 ; + RECT 533.9 0.3 534.16 4.63 ; + RECT 534.005 617.545 534.205 618.275 ; + RECT 534.41 0.3 534.67 4.63 ; + RECT 534.505 617.545 534.705 618.275 ; + RECT 535 617.545 535.2 618.275 ; + RECT 535.82 617.545 536.02 618.275 ; + RECT 536.315 617.545 536.515 618.275 ; + RECT 536.35 0.52 536.61 4.5 ; + RECT 536.815 617.545 537.015 618.275 ; + RECT 537.315 617.545 537.515 618.275 ; + RECT 537.81 617.545 538.01 618.275 ; + RECT 539.055 0.165 539.825 0.425 ; + RECT 539.055 0.165 539.315 8.825 ; + RECT 539.565 0.165 539.825 8.825 ; + RECT 538.63 617.545 538.83 618.275 ; + RECT 539.125 617.545 539.325 618.275 ; + RECT 539.625 617.545 539.825 618.275 ; + RECT 540.125 617.545 540.325 618.275 ; + RECT 540.075 0.3 540.335 4.63 ; + RECT 540.62 617.545 540.82 618.275 ; + RECT 540.585 0.3 540.845 8.23 ; + RECT 541.44 617.545 541.64 618.275 ; + RECT 541.935 617.545 542.135 618.275 ; + RECT 542.435 617.545 542.635 618.275 ; + RECT 542.935 617.545 543.135 618.275 ; + RECT 543.43 617.545 543.63 618.275 ; + RECT 544.745 0.17 545.515 0.43 ; + RECT 545.255 0.17 545.515 11.38 ; + RECT 544.745 0.17 545.005 16.7 ; + RECT 544.25 617.545 544.45 618.275 ; + RECT 544.745 617.545 544.945 618.275 ; + RECT 545.245 617.545 545.445 618.275 ; + RECT 545.745 617.545 545.945 618.275 ; + RECT 546.24 617.545 546.44 618.275 ; + RECT 547.06 617.545 547.26 618.275 ; + RECT 548.315 0.17 549.085 0.43 ; + RECT 548.825 0.17 549.085 8.7 ; + RECT 548.315 0.17 548.575 16.7 ; + RECT 547.555 617.545 547.755 618.275 ; + RECT 548.055 617.545 548.255 618.275 ; + RECT 548.555 617.545 548.755 618.275 ; + RECT 549.05 617.545 549.25 618.275 ; + RECT 549.335 0.3 549.595 4.63 ; + RECT 549.87 617.545 550.07 618.275 ; + RECT 550.355 0.17 551.125 0.43 ; + RECT 550.865 0.17 551.125 8.7 ; + RECT 550.355 0.17 550.615 16.7 ; + RECT 549.845 0.3 550.105 4.63 ; + RECT 550.365 617.545 550.565 618.275 ; + RECT 550.865 617.545 551.065 618.275 ; + RECT 551.365 617.545 551.565 618.275 ; + RECT 551.86 617.545 552.06 618.275 ; + RECT 552.68 617.545 552.88 618.275 ; + RECT 553.175 617.545 553.375 618.275 ; + RECT 553.675 617.545 553.875 618.275 ; + RECT 554.175 617.545 554.375 618.275 ; + RECT 554.67 617.545 554.87 618.275 ; + RECT 555.49 617.545 555.69 618.275 ; + RECT 555.985 617.545 556.185 618.275 ; + RECT 556.485 617.545 556.685 618.275 ; + RECT 556.985 617.545 557.185 618.275 ; + RECT 557.085 0.3 557.345 4.63 ; + RECT 558.105 0.165 558.875 0.425 ; + RECT 558.105 0.165 558.365 8.825 ; + RECT 558.615 0.165 558.875 8.825 ; + RECT 557.48 617.545 557.68 618.275 ; + RECT 557.595 0.3 557.855 4.63 ; + RECT 558.3 617.545 558.5 618.275 ; + RECT 558.795 617.545 558.995 618.275 ; + RECT 559.295 617.545 559.495 618.275 ; + RECT 559.535 0.52 559.795 4.5 ; + RECT 559.795 617.545 559.995 618.275 ; + RECT 560.29 617.545 560.49 618.275 ; + RECT 561.11 617.545 561.31 618.275 ; + RECT 561.605 617.545 561.805 618.275 ; + RECT 562.105 617.545 562.305 618.275 ; + RECT 562.605 617.545 562.805 618.275 ; + RECT 563.1 617.545 563.3 618.275 ; + RECT 563.92 617.545 564.12 618.275 ; + RECT 564.415 617.545 564.615 618.275 ; + RECT 564.915 617.545 565.115 618.275 ; + RECT 565.415 617.545 565.615 618.275 ; + RECT 565.91 617.545 566.11 618.275 ; + RECT 566.73 617.545 566.93 618.275 ; + RECT 567.225 617.545 567.425 618.275 ; + RECT 567.725 617.545 567.925 618.275 ; + RECT 568.225 617.545 568.425 618.275 ; + RECT 568.72 617.545 568.92 618.275 ; + RECT 569.54 617.545 569.74 618.275 ; + RECT 570.035 617.545 570.235 618.275 ; + RECT 570.535 617.545 570.735 618.275 ; + RECT 571.035 617.545 571.235 618.275 ; + RECT 571.53 617.545 571.73 618.275 ; + RECT 572.35 617.545 572.55 618.275 ; + RECT 573.305 0.16 574.075 0.42 ; + RECT 573.815 0.16 574.075 4.63 ; + RECT 573.305 0.16 573.565 8.82 ; + RECT 572.845 617.545 573.045 618.275 ; + RECT 573.345 617.545 573.545 618.275 ; + RECT 573.845 617.545 574.045 618.275 ; + RECT 574.34 617.545 574.54 618.275 ; + RECT 574.325 0.3 574.585 4.63 ; + RECT 574.835 0.3 575.095 4.63 ; + RECT 575.16 617.545 575.36 618.275 ; + RECT 575.655 617.545 575.855 618.275 ; + RECT 576.155 617.545 576.355 618.275 ; + RECT 577.84 0.16 578.61 0.42 ; + RECT 577.84 0.16 578.1 8.82 ; + RECT 578.35 0.16 578.61 8.82 ; + RECT 576.655 617.545 576.855 618.275 ; + RECT 577.15 617.545 577.35 618.275 ; + RECT 577.97 617.545 578.17 618.275 ; + RECT 578.465 617.545 578.665 618.275 ; + RECT 578.86 0.3 579.12 4.63 ; + RECT 578.965 617.545 579.165 618.275 ; + RECT 579.37 0.3 579.63 4.63 ; + RECT 579.465 617.545 579.665 618.275 ; + RECT 579.96 617.545 580.16 618.275 ; + RECT 580.78 617.545 580.98 618.275 ; + RECT 581.275 617.545 581.475 618.275 ; + RECT 581.31 0.52 581.57 4.5 ; + RECT 581.775 617.545 581.975 618.275 ; + RECT 582.275 617.545 582.475 618.275 ; + RECT 582.77 617.545 582.97 618.275 ; + RECT 584.015 0.165 584.785 0.425 ; + RECT 584.015 0.165 584.275 8.825 ; + RECT 584.525 0.165 584.785 8.825 ; + RECT 583.59 617.545 583.79 618.275 ; + RECT 584.085 617.545 584.285 618.275 ; + RECT 584.585 617.545 584.785 618.275 ; + RECT 585.085 617.545 585.285 618.275 ; + RECT 585.035 0.3 585.295 4.63 ; + RECT 585.58 617.545 585.78 618.275 ; + RECT 585.545 0.3 585.805 8.23 ; + RECT 586.4 617.545 586.6 618.275 ; + RECT 586.895 617.545 587.095 618.275 ; + RECT 587.395 617.545 587.595 618.275 ; + RECT 587.895 617.545 588.095 618.275 ; + RECT 588.39 617.545 588.59 618.275 ; + RECT 589.705 0.17 590.475 0.43 ; + RECT 590.215 0.17 590.475 11.38 ; + RECT 589.705 0.17 589.965 16.7 ; + RECT 589.21 617.545 589.41 618.275 ; + RECT 589.705 617.545 589.905 618.275 ; + RECT 590.205 617.545 590.405 618.275 ; + RECT 590.705 617.545 590.905 618.275 ; + RECT 591.2 617.545 591.4 618.275 ; + RECT 592.02 617.545 592.22 618.275 ; + RECT 593.275 0.17 594.045 0.43 ; + RECT 593.785 0.17 594.045 8.7 ; + RECT 593.275 0.17 593.535 16.7 ; + RECT 592.515 617.545 592.715 618.275 ; + RECT 593.015 617.545 593.215 618.275 ; + RECT 593.515 617.545 593.715 618.275 ; + RECT 594.01 617.545 594.21 618.275 ; + RECT 594.295 0.3 594.555 4.63 ; + RECT 594.83 617.545 595.03 618.275 ; + RECT 595.315 0.17 596.085 0.43 ; + RECT 595.825 0.17 596.085 8.7 ; + RECT 595.315 0.17 595.575 16.7 ; + RECT 594.805 0.3 595.065 4.63 ; + RECT 595.325 617.545 595.525 618.275 ; + RECT 595.825 617.545 596.025 618.275 ; + RECT 596.325 617.545 596.525 618.275 ; + RECT 596.82 617.545 597.02 618.275 ; + RECT 597.64 617.545 597.84 618.275 ; + RECT 598.135 617.545 598.335 618.275 ; + RECT 598.635 617.545 598.835 618.275 ; + RECT 599.135 617.545 599.335 618.275 ; + RECT 599.63 617.545 599.83 618.275 ; + RECT 600.45 617.545 600.65 618.275 ; + RECT 600.945 617.545 601.145 618.275 ; + RECT 601.445 617.545 601.645 618.275 ; + RECT 601.945 617.545 602.145 618.275 ; + RECT 602.045 0.3 602.305 4.63 ; + RECT 603.065 0.165 603.835 0.425 ; + RECT 603.065 0.165 603.325 8.825 ; + RECT 603.575 0.165 603.835 8.825 ; + RECT 602.44 617.545 602.64 618.275 ; + RECT 602.555 0.3 602.815 4.63 ; + RECT 603.26 617.545 603.46 618.275 ; + RECT 603.755 617.545 603.955 618.275 ; + RECT 604.255 617.545 604.455 618.275 ; + RECT 604.495 0.52 604.755 4.5 ; + RECT 604.755 617.545 604.955 618.275 ; + RECT 605.25 617.545 605.45 618.275 ; + RECT 606.07 617.545 606.27 618.275 ; + RECT 606.565 617.545 606.765 618.275 ; + RECT 607.065 617.545 607.265 618.275 ; + RECT 607.565 617.545 607.765 618.275 ; + RECT 608.06 617.545 608.26 618.275 ; + RECT 608.88 617.545 609.08 618.275 ; + RECT 609.375 617.545 609.575 618.275 ; + RECT 609.875 617.545 610.075 618.275 ; + RECT 610.375 617.545 610.575 618.275 ; + RECT 610.87 617.545 611.07 618.275 ; + RECT 611.69 617.545 611.89 618.275 ; + RECT 612.185 617.545 612.385 618.275 ; + RECT 612.685 617.545 612.885 618.275 ; + RECT 613.185 617.545 613.385 618.275 ; + RECT 613.68 617.545 613.88 618.275 ; + RECT 614.5 617.545 614.7 618.275 ; + RECT 614.995 617.545 615.195 618.275 ; + RECT 615.495 617.545 615.695 618.275 ; + RECT 615.995 617.545 616.195 618.275 ; + RECT 616.49 617.545 616.69 618.275 ; + RECT 617.31 617.545 617.51 618.275 ; + RECT 618.265 0.16 619.035 0.42 ; + RECT 618.775 0.16 619.035 4.63 ; + RECT 618.265 0.16 618.525 8.82 ; + RECT 617.805 617.545 618.005 618.275 ; + RECT 618.305 617.545 618.505 618.275 ; + RECT 618.805 617.545 619.005 618.275 ; + RECT 619.3 617.545 619.5 618.275 ; + RECT 619.285 0.3 619.545 4.63 ; + RECT 619.795 0.3 620.055 4.63 ; + RECT 620.12 617.545 620.32 618.275 ; + RECT 620.615 617.545 620.815 618.275 ; + RECT 621.115 617.545 621.315 618.275 ; + RECT 622.8 0.16 623.57 0.42 ; + RECT 622.8 0.16 623.06 8.82 ; + RECT 623.31 0.16 623.57 8.82 ; + RECT 621.615 617.545 621.815 618.275 ; + RECT 622.11 617.545 622.31 618.275 ; + RECT 622.93 617.545 623.13 618.275 ; + RECT 623.425 617.545 623.625 618.275 ; + RECT 623.82 0.3 624.08 4.63 ; + RECT 623.925 617.545 624.125 618.275 ; + RECT 624.33 0.3 624.59 4.63 ; + RECT 624.425 617.545 624.625 618.275 ; + RECT 624.92 617.545 625.12 618.275 ; + RECT 625.74 617.545 625.94 618.275 ; + RECT 626.235 617.545 626.435 618.275 ; + RECT 626.27 0.52 626.53 4.5 ; + RECT 626.735 617.545 626.935 618.275 ; + RECT 627.235 617.545 627.435 618.275 ; + RECT 627.73 617.545 627.93 618.275 ; + RECT 628.975 0.165 629.745 0.425 ; + RECT 628.975 0.165 629.235 8.825 ; + RECT 629.485 0.165 629.745 8.825 ; + RECT 628.55 617.545 628.75 618.275 ; + RECT 629.045 617.545 629.245 618.275 ; + RECT 629.545 617.545 629.745 618.275 ; + RECT 630.045 617.545 630.245 618.275 ; + RECT 629.995 0.3 630.255 4.63 ; + RECT 630.54 617.545 630.74 618.275 ; + RECT 630.505 0.3 630.765 8.23 ; + RECT 631.36 617.545 631.56 618.275 ; + RECT 631.855 617.545 632.055 618.275 ; + RECT 632.355 617.545 632.555 618.275 ; + RECT 632.855 617.545 633.055 618.275 ; + RECT 633.35 617.545 633.55 618.275 ; + RECT 634.665 0.17 635.435 0.43 ; + RECT 635.175 0.17 635.435 11.38 ; + RECT 634.665 0.17 634.925 16.7 ; + RECT 634.17 617.545 634.37 618.275 ; + RECT 634.665 617.545 634.865 618.275 ; + RECT 635.165 617.545 635.365 618.275 ; + RECT 635.665 617.545 635.865 618.275 ; + RECT 636.16 617.545 636.36 618.275 ; + RECT 636.98 617.545 637.18 618.275 ; + RECT 638.235 0.17 639.005 0.43 ; + RECT 638.745 0.17 639.005 8.7 ; + RECT 638.235 0.17 638.495 16.7 ; + RECT 637.475 617.545 637.675 618.275 ; + RECT 637.975 617.545 638.175 618.275 ; + RECT 638.475 617.545 638.675 618.275 ; + RECT 638.97 617.545 639.17 618.275 ; + RECT 639.255 0.3 639.515 4.63 ; + RECT 639.79 617.545 639.99 618.275 ; + RECT 640.275 0.17 641.045 0.43 ; + RECT 640.785 0.17 641.045 8.7 ; + RECT 640.275 0.17 640.535 16.7 ; + RECT 639.765 0.3 640.025 4.63 ; + RECT 640.285 617.545 640.485 618.275 ; + RECT 640.785 617.545 640.985 618.275 ; + RECT 641.285 617.545 641.485 618.275 ; + RECT 641.78 617.545 641.98 618.275 ; + RECT 642.6 617.545 642.8 618.275 ; + RECT 643.095 617.545 643.295 618.275 ; + RECT 643.595 617.545 643.795 618.275 ; + RECT 644.095 617.545 644.295 618.275 ; + RECT 644.59 617.545 644.79 618.275 ; + RECT 645.41 617.545 645.61 618.275 ; + RECT 645.905 617.545 646.105 618.275 ; + RECT 646.405 617.545 646.605 618.275 ; + RECT 646.905 617.545 647.105 618.275 ; + RECT 647.005 0.3 647.265 4.63 ; + RECT 648.025 0.165 648.795 0.425 ; + RECT 648.025 0.165 648.285 8.825 ; + RECT 648.535 0.165 648.795 8.825 ; + RECT 647.4 617.545 647.6 618.275 ; + RECT 647.515 0.3 647.775 4.63 ; + RECT 648.22 617.545 648.42 618.275 ; + RECT 648.715 617.545 648.915 618.275 ; + RECT 649.215 617.545 649.415 618.275 ; + RECT 649.455 0.52 649.715 4.5 ; + RECT 649.715 617.545 649.915 618.275 ; + RECT 650.21 617.545 650.41 618.275 ; + RECT 651.03 617.545 651.23 618.275 ; + RECT 651.525 617.545 651.725 618.275 ; + RECT 652.025 617.545 652.225 618.275 ; + RECT 652.525 617.545 652.725 618.275 ; + RECT 653.02 617.545 653.22 618.275 ; + RECT 653.84 617.545 654.04 618.275 ; + RECT 654.335 617.545 654.535 618.275 ; + RECT 654.835 617.545 655.035 618.275 ; + RECT 655.335 617.545 655.535 618.275 ; + RECT 655.83 617.545 656.03 618.275 ; + RECT 656.65 617.545 656.85 618.275 ; + RECT 657.145 617.545 657.345 618.275 ; + RECT 657.645 617.545 657.845 618.275 ; + RECT 658.145 617.545 658.345 618.275 ; + RECT 658.64 617.545 658.84 618.275 ; + RECT 659.46 617.545 659.66 618.275 ; + RECT 659.955 617.545 660.155 618.275 ; + RECT 660.455 617.545 660.655 618.275 ; + RECT 660.955 617.545 661.155 618.275 ; + RECT 661.45 617.545 661.65 618.275 ; + RECT 662.27 617.545 662.47 618.275 ; + RECT 663.225 0.16 663.995 0.42 ; + RECT 663.735 0.16 663.995 4.63 ; + RECT 663.225 0.16 663.485 8.82 ; + RECT 662.765 617.545 662.965 618.275 ; + RECT 663.265 617.545 663.465 618.275 ; + RECT 663.765 617.545 663.965 618.275 ; + RECT 664.26 617.545 664.46 618.275 ; + RECT 664.245 0.3 664.505 4.63 ; + RECT 664.755 0.3 665.015 4.63 ; + RECT 665.08 617.545 665.28 618.275 ; + RECT 665.575 617.545 665.775 618.275 ; + RECT 666.075 617.545 666.275 618.275 ; + RECT 667.76 0.16 668.53 0.42 ; + RECT 667.76 0.16 668.02 8.82 ; + RECT 668.27 0.16 668.53 8.82 ; + RECT 666.575 617.545 666.775 618.275 ; + RECT 667.07 617.545 667.27 618.275 ; + RECT 667.89 617.545 668.09 618.275 ; + RECT 668.385 617.545 668.585 618.275 ; + RECT 668.78 0.3 669.04 4.63 ; + RECT 668.885 617.545 669.085 618.275 ; + RECT 669.29 0.3 669.55 4.63 ; + RECT 669.385 617.545 669.585 618.275 ; + RECT 669.88 617.545 670.08 618.275 ; + RECT 670.7 617.545 670.9 618.275 ; + RECT 671.195 617.545 671.395 618.275 ; + RECT 671.23 0.52 671.49 4.5 ; + RECT 671.695 617.545 671.895 618.275 ; + RECT 672.195 617.545 672.395 618.275 ; + RECT 672.69 617.545 672.89 618.275 ; + RECT 673.935 0.165 674.705 0.425 ; + RECT 673.935 0.165 674.195 8.825 ; + RECT 674.445 0.165 674.705 8.825 ; + RECT 673.51 617.545 673.71 618.275 ; + RECT 674.005 617.545 674.205 618.275 ; + RECT 674.505 617.545 674.705 618.275 ; + RECT 675.005 617.545 675.205 618.275 ; + RECT 674.955 0.3 675.215 4.63 ; + RECT 675.5 617.545 675.7 618.275 ; + RECT 675.465 0.3 675.725 8.23 ; + RECT 676.32 617.545 676.52 618.275 ; + RECT 676.815 617.545 677.015 618.275 ; + RECT 677.315 617.545 677.515 618.275 ; + RECT 677.815 617.545 678.015 618.275 ; + RECT 678.31 617.545 678.51 618.275 ; + RECT 679.625 0.17 680.395 0.43 ; + RECT 680.135 0.17 680.395 11.38 ; + RECT 679.625 0.17 679.885 16.7 ; + RECT 679.13 617.545 679.33 618.275 ; + RECT 679.625 617.545 679.825 618.275 ; + RECT 680.125 617.545 680.325 618.275 ; + RECT 680.625 617.545 680.825 618.275 ; + RECT 681.12 617.545 681.32 618.275 ; + RECT 681.94 617.545 682.14 618.275 ; + RECT 683.195 0.17 683.965 0.43 ; + RECT 683.705 0.17 683.965 8.7 ; + RECT 683.195 0.17 683.455 16.7 ; + RECT 682.435 617.545 682.635 618.275 ; + RECT 682.935 617.545 683.135 618.275 ; + RECT 683.435 617.545 683.635 618.275 ; + RECT 683.93 617.545 684.13 618.275 ; + RECT 684.215 0.3 684.475 4.63 ; + RECT 684.75 617.545 684.95 618.275 ; + RECT 685.235 0.17 686.005 0.43 ; + RECT 685.745 0.17 686.005 8.7 ; + RECT 685.235 0.17 685.495 16.7 ; + RECT 684.725 0.3 684.985 4.63 ; + RECT 685.245 617.545 685.445 618.275 ; + RECT 685.745 617.545 685.945 618.275 ; + RECT 686.245 617.545 686.445 618.275 ; + RECT 686.74 617.545 686.94 618.275 ; + RECT 687.56 617.545 687.76 618.275 ; + RECT 688.055 617.545 688.255 618.275 ; + RECT 688.555 617.545 688.755 618.275 ; + RECT 689.055 617.545 689.255 618.275 ; + RECT 689.55 617.545 689.75 618.275 ; + RECT 690.37 617.545 690.57 618.275 ; + RECT 690.865 617.545 691.065 618.275 ; + RECT 691.365 617.545 691.565 618.275 ; + RECT 691.865 617.545 692.065 618.275 ; + RECT 691.965 0.3 692.225 4.63 ; + RECT 692.985 0.165 693.755 0.425 ; + RECT 692.985 0.165 693.245 8.825 ; + RECT 693.495 0.165 693.755 8.825 ; + RECT 692.36 617.545 692.56 618.275 ; + RECT 692.475 0.3 692.735 4.63 ; + RECT 693.18 617.545 693.38 618.275 ; + RECT 693.675 617.545 693.875 618.275 ; + RECT 694.175 617.545 694.375 618.275 ; + RECT 694.415 0.52 694.675 4.5 ; + RECT 694.675 617.545 694.875 618.275 ; + RECT 695.17 617.545 695.37 618.275 ; + RECT 695.99 617.545 696.19 618.275 ; + RECT 696.485 617.545 696.685 618.275 ; + RECT 696.985 617.545 697.185 618.275 ; + RECT 697.485 617.545 697.685 618.275 ; + RECT 697.98 617.545 698.18 618.275 ; + RECT 698.8 617.545 699 618.275 ; + RECT 699.295 617.545 699.495 618.275 ; + RECT 699.795 617.545 699.995 618.275 ; + RECT 700.295 617.545 700.495 618.275 ; + RECT 700.79 617.545 700.99 618.275 ; + RECT 701.61 617.545 701.81 618.275 ; + RECT 702.105 617.545 702.305 618.275 ; + RECT 702.605 617.545 702.805 618.275 ; + RECT 703.105 617.545 703.305 618.275 ; + RECT 703.6 617.545 703.8 618.275 ; + RECT 704.42 617.545 704.62 618.275 ; + RECT 704.915 617.545 705.115 618.275 ; + RECT 705.415 617.545 705.615 618.275 ; + RECT 705.915 617.545 706.115 618.275 ; + RECT 706.41 617.545 706.61 618.275 ; + RECT 707.23 617.545 707.43 618.275 ; + RECT 708.185 0.16 708.955 0.42 ; + RECT 708.695 0.16 708.955 4.63 ; + RECT 708.185 0.16 708.445 8.82 ; + RECT 707.725 617.545 707.925 618.275 ; + RECT 708.225 617.545 708.425 618.275 ; + RECT 708.725 617.545 708.925 618.275 ; + RECT 709.22 617.545 709.42 618.275 ; + RECT 709.205 0.3 709.465 4.63 ; + RECT 709.715 0.3 709.975 4.63 ; + RECT 710.04 617.545 710.24 618.275 ; + RECT 710.535 617.545 710.735 618.275 ; + RECT 711.035 617.545 711.235 618.275 ; + RECT 712.72 0.16 713.49 0.42 ; + RECT 712.72 0.16 712.98 8.82 ; + RECT 713.23 0.16 713.49 8.82 ; + RECT 711.535 617.545 711.735 618.275 ; + RECT 712.03 617.545 712.23 618.275 ; + RECT 712.85 617.545 713.05 618.275 ; + RECT 713.345 617.545 713.545 618.275 ; + RECT 713.74 0.3 714 4.63 ; + RECT 713.845 617.545 714.045 618.275 ; + RECT 714.25 0.3 714.51 4.63 ; + RECT 714.345 617.545 714.545 618.275 ; + RECT 714.84 617.545 715.04 618.275 ; + RECT 715.66 617.545 715.86 618.275 ; + RECT 716.155 617.545 716.355 618.275 ; + RECT 716.19 0.52 716.45 4.5 ; + RECT 716.655 617.545 716.855 618.275 ; + RECT 717.155 617.545 717.355 618.275 ; + RECT 717.65 617.545 717.85 618.275 ; + RECT 718.895 0.165 719.665 0.425 ; + RECT 718.895 0.165 719.155 8.825 ; + RECT 719.405 0.165 719.665 8.825 ; + RECT 718.47 617.545 718.67 618.275 ; + RECT 718.965 617.545 719.165 618.275 ; + RECT 719.465 617.545 719.665 618.275 ; + RECT 719.965 617.545 720.165 618.275 ; + RECT 719.915 0.3 720.175 4.63 ; + RECT 720.46 617.545 720.66 618.275 ; + RECT 720.425 0.3 720.685 8.23 ; + RECT 721.28 617.545 721.48 618.275 ; + RECT 723.995 0.17 724.765 0.43 ; + RECT 723.995 0.17 724.255 34.45 ; + RECT 724.505 0.17 724.765 34.45 ; + RECT 722.275 617.545 722.475 618.275 ; + RECT 722.975 0.3 723.235 35.29 ; + RECT 723.485 0.3 723.745 35.29 ; + RECT 725.015 0.3 725.275 35.29 ; + RECT 725.525 0.3 725.785 35.29 ; + RECT 730.115 0.17 730.885 0.43 ; + RECT 730.115 0.17 730.375 34.03 ; + RECT 730.625 0.17 730.885 34.03 ; + RECT 726.035 0.3 726.295 34.03 ; + RECT 729.095 0.3 729.355 35.29 ; + RECT 729.605 0.3 729.865 35.29 ; + RECT 731.135 0.3 731.395 35.29 ; + RECT 734.195 0.17 734.965 0.43 ; + RECT 734.195 0.17 734.455 36.945 ; + RECT 734.705 0.17 734.965 36.945 ; + RECT 731.645 0.3 731.905 35.29 ; + RECT 732.155 0.3 732.415 34.03 ; + RECT 736.235 0.17 737.005 0.43 ; + RECT 736.235 0.17 736.495 36.945 ; + RECT 736.745 0.17 737.005 36.945 ; + RECT 732.665 0.3 732.925 2.225 ; + RECT 735.215 0.3 735.475 37.365 ; + RECT 738.275 0.17 739.045 0.43 ; + RECT 738.275 0.17 738.535 36.945 ; + RECT 738.785 0.17 739.045 36.945 ; + RECT 735.725 0.3 735.985 37.365 ; + RECT 737.255 0.3 737.515 37.365 ; + RECT 740.98 0 741.24 4.94 ; + RECT 740.98 4.68 741.75 4.94 ; + RECT 741.49 4.68 741.75 12.9 ; + RECT 741.49 0.52 741.75 1.78 ; + RECT 741.49 1.52 742.26 1.78 ; + RECT 742 1.52 742.26 12.9 ; + RECT 737.765 0.3 738.025 37.365 ; + RECT 739.295 0.3 739.555 37.365 ; + RECT 739.805 0.3 740.065 37.365 ; + RECT 742 0.59 742.77 1.27 ; + RECT 743.02 0 743.28 12.9 ; + RECT 743.53 0 743.79 12.9 ; + RECT 744.04 0.52 744.3 12.9 ; + RECT 744.55 0 744.81 12.9 ; + RECT 745.06 0.52 745.32 12.9 ; + RECT 748.12 0.17 748.89 0.43 ; + RECT 748.12 0.17 748.38 2.085 ; + RECT 748.63 0.17 748.89 9 ; + RECT 745.57 0 745.83 12.9 ; + RECT 746.08 0.52 746.34 8.565 ; + RECT 746.59 0 746.85 8.055 ; + RECT 752.71 0 752.97 6.59 ; + RECT 754.24 0.52 754.5 6.305 ; + RECT 754.24 6.045 755.21 6.305 ; + RECT 753.22 0 753.48 2.23 ; + RECT 754.75 0.52 755.01 2.955 ; + RECT 755.77 0.52 756.03 12.9 ; + RECT 756.28 0.52 756.54 12.9 ; + RECT 757.81 0.52 758.07 6.29 ; + RECT 757.3 6.045 758.07 6.29 ; + RECT 756.79 0 757.05 6.745 ; + RECT 759.34 0 759.6 6.59 ; + RECT 758.695 6.33 759.6 6.59 ; + RECT 757.3 0.52 757.56 2.955 ; + RECT 758.83 0 759.09 2.67 ; + RECT 760.36 0 760.62 12.9 ; + RECT 760.87 0 761.13 12.9 ; + RECT 762.4 0.575 762.66 7.965 ; + RECT 762.91 0.52 763.17 12.9 ; + RECT 763.42 0 763.68 12.9 ; + RECT 763.93 0.52 764.19 12.9 ; + RECT 764.44 0 764.7 12.9 ; + RECT 764.95 0 765.21 12.9 ; + RECT 765.46 0.52 765.72 12.9 ; + RECT 765.97 0 766.23 12.9 ; + RECT 766.48 0.52 766.74 12.9 ; + RECT 766.99 0.52 767.25 12.9 ; + RECT 767.5 0 767.76 12.9 ; + RECT 768.01 0.59 768.78 1.27 ; + RECT 769.03 0.52 769.29 12.9 ; + RECT 769.54 0 769.8 12.9 ; + RECT 776.68 0.17 777.45 0.43 ; + RECT 776.68 0.17 776.94 13.845 ; + RECT 777.19 0.17 777.45 13.845 ; + RECT 778.72 0.17 779.49 0.43 ; + RECT 778.72 0.17 778.98 2.11 ; + RECT 779.23 0.17 779.49 2.11 ; + RECT 774.13 0.52 774.39 3.61 ; + RECT 774.64 0 774.9 4.12 ; + RECT 781.115 0.17 781.885 0.43 ; + RECT 781.115 0.17 781.375 36.945 ; + RECT 781.625 0.17 781.885 36.945 ; + RECT 776.17 0.52 776.43 15.16 ; + RECT 780.095 0.3 780.355 37.365 ; + RECT 783.155 0.17 783.925 0.43 ; + RECT 783.155 0.17 783.415 36.945 ; + RECT 783.665 0.17 783.925 36.945 ; + RECT 780.605 0.3 780.865 37.365 ; + RECT 782.135 0.3 782.395 37.365 ; + RECT 785.195 0.17 785.965 0.43 ; + RECT 785.195 0.17 785.455 36.945 ; + RECT 785.705 0.17 785.965 36.945 ; + RECT 782.645 0.3 782.905 37.365 ; + RECT 784.175 0.3 784.435 37.365 ; + RECT 784.685 0.3 784.945 37.365 ; + RECT 787.235 0.3 787.495 2.225 ; + RECT 789.275 0.17 790.045 0.43 ; + RECT 789.275 0.17 789.535 34.03 ; + RECT 789.785 0.17 790.045 34.03 ; + RECT 787.745 0.3 788.005 34.03 ; + RECT 788.255 0.3 788.515 35.29 ; + RECT 788.765 0.3 789.025 35.29 ; + RECT 790.295 0.3 790.555 35.29 ; + RECT 790.805 0.3 791.065 35.29 ; + RECT 795.395 0.17 796.165 0.43 ; + RECT 795.395 0.17 795.655 34.45 ; + RECT 795.905 0.17 796.165 34.45 ; + RECT 793.865 0.3 794.125 34.03 ; + RECT 794.375 0.3 794.635 35.29 ; + RECT 794.885 0.3 795.145 35.29 ; + RECT 796.415 0.3 796.675 35.29 ; + RECT 796.925 0.3 797.185 35.29 ; + RECT 797.685 617.545 797.885 618.275 ; + RECT 798.68 617.545 798.88 618.275 ; + RECT 799.5 617.545 799.7 618.275 ; + RECT 799.475 0.3 799.735 8.23 ; + RECT 799.995 617.545 800.195 618.275 ; + RECT 800.495 0.165 801.265 0.425 ; + RECT 800.495 0.165 800.755 8.825 ; + RECT 801.005 0.165 801.265 8.825 ; + RECT 799.985 0.3 800.245 4.63 ; + RECT 800.495 617.545 800.695 618.275 ; + RECT 800.995 617.545 801.195 618.275 ; + RECT 801.49 617.545 801.69 618.275 ; + RECT 802.31 617.545 802.51 618.275 ; + RECT 802.805 617.545 803.005 618.275 ; + RECT 803.305 617.545 803.505 618.275 ; + RECT 803.71 0.52 803.97 4.5 ; + RECT 803.805 617.545 804.005 618.275 ; + RECT 804.3 617.545 804.5 618.275 ; + RECT 805.12 617.545 805.32 618.275 ; + RECT 805.615 617.545 805.815 618.275 ; + RECT 805.65 0.3 805.91 4.63 ; + RECT 806.115 617.545 806.315 618.275 ; + RECT 806.67 0.16 807.44 0.42 ; + RECT 806.67 0.16 806.93 8.82 ; + RECT 807.18 0.16 807.44 8.82 ; + RECT 806.16 0.3 806.42 4.63 ; + RECT 806.615 617.545 806.815 618.275 ; + RECT 807.11 617.545 807.31 618.275 ; + RECT 807.93 617.545 808.13 618.275 ; + RECT 808.425 617.545 808.625 618.275 ; + RECT 808.925 617.545 809.125 618.275 ; + RECT 809.425 617.545 809.625 618.275 ; + RECT 809.92 617.545 810.12 618.275 ; + RECT 810.185 0.3 810.445 4.63 ; + RECT 810.74 617.545 810.94 618.275 ; + RECT 811.205 0.16 811.975 0.42 ; + RECT 811.205 0.16 811.465 4.63 ; + RECT 811.715 0.16 811.975 8.82 ; + RECT 810.695 0.3 810.955 4.63 ; + RECT 811.235 617.545 811.435 618.275 ; + RECT 811.735 617.545 811.935 618.275 ; + RECT 812.235 617.545 812.435 618.275 ; + RECT 812.73 617.545 812.93 618.275 ; + RECT 813.55 617.545 813.75 618.275 ; + RECT 814.045 617.545 814.245 618.275 ; + RECT 814.545 617.545 814.745 618.275 ; + RECT 815.045 617.545 815.245 618.275 ; + RECT 815.54 617.545 815.74 618.275 ; + RECT 816.36 617.545 816.56 618.275 ; + RECT 816.855 617.545 817.055 618.275 ; + RECT 817.355 617.545 817.555 618.275 ; + RECT 817.855 617.545 818.055 618.275 ; + RECT 818.35 617.545 818.55 618.275 ; + RECT 819.17 617.545 819.37 618.275 ; + RECT 819.665 617.545 819.865 618.275 ; + RECT 820.165 617.545 820.365 618.275 ; + RECT 820.665 617.545 820.865 618.275 ; + RECT 821.16 617.545 821.36 618.275 ; + RECT 821.98 617.545 822.18 618.275 ; + RECT 822.475 617.545 822.675 618.275 ; + RECT 822.975 617.545 823.175 618.275 ; + RECT 823.475 617.545 823.675 618.275 ; + RECT 823.97 617.545 824.17 618.275 ; + RECT 824.79 617.545 824.99 618.275 ; + RECT 825.285 617.545 825.485 618.275 ; + RECT 825.485 0.52 825.745 4.5 ; + RECT 826.405 0.165 827.175 0.425 ; + RECT 826.405 0.165 826.665 8.825 ; + RECT 826.915 0.165 827.175 8.825 ; + RECT 825.785 617.545 825.985 618.275 ; + RECT 826.285 617.545 826.485 618.275 ; + RECT 826.78 617.545 826.98 618.275 ; + RECT 827.425 0.3 827.685 4.63 ; + RECT 827.6 617.545 827.8 618.275 ; + RECT 827.935 0.3 828.195 4.63 ; + RECT 828.095 617.545 828.295 618.275 ; + RECT 828.595 617.545 828.795 618.275 ; + RECT 829.095 617.545 829.295 618.275 ; + RECT 829.59 617.545 829.79 618.275 ; + RECT 830.41 617.545 830.61 618.275 ; + RECT 830.905 617.545 831.105 618.275 ; + RECT 831.405 617.545 831.605 618.275 ; + RECT 831.905 617.545 832.105 618.275 ; + RECT 832.4 617.545 832.6 618.275 ; + RECT 833.22 617.545 833.42 618.275 ; + RECT 834.155 0.17 834.925 0.43 ; + RECT 834.155 0.17 834.415 8.7 ; + RECT 834.665 0.17 834.925 16.7 ; + RECT 833.715 617.545 833.915 618.275 ; + RECT 834.215 617.545 834.415 618.275 ; + RECT 834.715 617.545 834.915 618.275 ; + RECT 835.21 617.545 835.41 618.275 ; + RECT 835.175 0.3 835.435 4.63 ; + RECT 836.195 0.17 836.965 0.43 ; + RECT 836.195 0.17 836.455 8.7 ; + RECT 836.705 0.17 836.965 16.7 ; + RECT 835.685 0.3 835.945 4.63 ; + RECT 836.03 617.545 836.23 618.275 ; + RECT 836.525 617.545 836.725 618.275 ; + RECT 837.025 617.545 837.225 618.275 ; + RECT 837.525 617.545 837.725 618.275 ; + RECT 838.02 617.545 838.22 618.275 ; + RECT 838.84 617.545 839.04 618.275 ; + RECT 839.765 0.17 840.535 0.43 ; + RECT 839.765 0.17 840.025 11.38 ; + RECT 840.275 0.17 840.535 16.7 ; + RECT 839.335 617.545 839.535 618.275 ; + RECT 839.835 617.545 840.035 618.275 ; + RECT 840.335 617.545 840.535 618.275 ; + RECT 840.83 617.545 841.03 618.275 ; + RECT 841.65 617.545 841.85 618.275 ; + RECT 842.145 617.545 842.345 618.275 ; + RECT 842.645 617.545 842.845 618.275 ; + RECT 843.145 617.545 843.345 618.275 ; + RECT 843.64 617.545 843.84 618.275 ; + RECT 844.46 617.545 844.66 618.275 ; + RECT 844.435 0.3 844.695 8.23 ; + RECT 844.955 617.545 845.155 618.275 ; + RECT 845.455 0.165 846.225 0.425 ; + RECT 845.455 0.165 845.715 8.825 ; + RECT 845.965 0.165 846.225 8.825 ; + RECT 844.945 0.3 845.205 4.63 ; + RECT 845.455 617.545 845.655 618.275 ; + RECT 845.955 617.545 846.155 618.275 ; + RECT 846.45 617.545 846.65 618.275 ; + RECT 847.27 617.545 847.47 618.275 ; + RECT 847.765 617.545 847.965 618.275 ; + RECT 848.265 617.545 848.465 618.275 ; + RECT 848.67 0.52 848.93 4.5 ; + RECT 848.765 617.545 848.965 618.275 ; + RECT 849.26 617.545 849.46 618.275 ; + RECT 850.08 617.545 850.28 618.275 ; + RECT 850.575 617.545 850.775 618.275 ; + RECT 850.61 0.3 850.87 4.63 ; + RECT 851.075 617.545 851.275 618.275 ; + RECT 851.63 0.16 852.4 0.42 ; + RECT 851.63 0.16 851.89 8.82 ; + RECT 852.14 0.16 852.4 8.82 ; + RECT 851.12 0.3 851.38 4.63 ; + RECT 851.575 617.545 851.775 618.275 ; + RECT 852.07 617.545 852.27 618.275 ; + RECT 852.89 617.545 853.09 618.275 ; + RECT 853.385 617.545 853.585 618.275 ; + RECT 853.885 617.545 854.085 618.275 ; + RECT 854.385 617.545 854.585 618.275 ; + RECT 854.88 617.545 855.08 618.275 ; + RECT 855.145 0.3 855.405 4.63 ; + RECT 855.7 617.545 855.9 618.275 ; + RECT 856.165 0.16 856.935 0.42 ; + RECT 856.165 0.16 856.425 4.63 ; + RECT 856.675 0.16 856.935 8.82 ; + RECT 855.655 0.3 855.915 4.63 ; + RECT 856.195 617.545 856.395 618.275 ; + RECT 856.695 617.545 856.895 618.275 ; + RECT 857.195 617.545 857.395 618.275 ; + RECT 857.69 617.545 857.89 618.275 ; + RECT 858.51 617.545 858.71 618.275 ; + RECT 859.005 617.545 859.205 618.275 ; + RECT 859.505 617.545 859.705 618.275 ; + RECT 860.005 617.545 860.205 618.275 ; + RECT 860.5 617.545 860.7 618.275 ; + RECT 861.32 617.545 861.52 618.275 ; + RECT 861.815 617.545 862.015 618.275 ; + RECT 862.315 617.545 862.515 618.275 ; + RECT 862.815 617.545 863.015 618.275 ; + RECT 863.31 617.545 863.51 618.275 ; + RECT 864.13 617.545 864.33 618.275 ; + RECT 864.625 617.545 864.825 618.275 ; + RECT 865.125 617.545 865.325 618.275 ; + RECT 865.625 617.545 865.825 618.275 ; + RECT 866.12 617.545 866.32 618.275 ; + RECT 866.94 617.545 867.14 618.275 ; + RECT 867.435 617.545 867.635 618.275 ; + RECT 867.935 617.545 868.135 618.275 ; + RECT 868.435 617.545 868.635 618.275 ; + RECT 868.93 617.545 869.13 618.275 ; + RECT 869.75 617.545 869.95 618.275 ; + RECT 870.245 617.545 870.445 618.275 ; + RECT 870.445 0.52 870.705 4.5 ; + RECT 871.365 0.165 872.135 0.425 ; + RECT 871.365 0.165 871.625 8.825 ; + RECT 871.875 0.165 872.135 8.825 ; + RECT 870.745 617.545 870.945 618.275 ; + RECT 871.245 617.545 871.445 618.275 ; + RECT 871.74 617.545 871.94 618.275 ; + RECT 872.385 0.3 872.645 4.63 ; + RECT 872.56 617.545 872.76 618.275 ; + RECT 872.895 0.3 873.155 4.63 ; + RECT 873.055 617.545 873.255 618.275 ; + RECT 873.555 617.545 873.755 618.275 ; + RECT 874.055 617.545 874.255 618.275 ; + RECT 874.55 617.545 874.75 618.275 ; + RECT 875.37 617.545 875.57 618.275 ; + RECT 875.865 617.545 876.065 618.275 ; + RECT 876.365 617.545 876.565 618.275 ; + RECT 876.865 617.545 877.065 618.275 ; + RECT 877.36 617.545 877.56 618.275 ; + RECT 878.18 617.545 878.38 618.275 ; + RECT 879.115 0.17 879.885 0.43 ; + RECT 879.115 0.17 879.375 8.7 ; + RECT 879.625 0.17 879.885 16.7 ; + RECT 878.675 617.545 878.875 618.275 ; + RECT 879.175 617.545 879.375 618.275 ; + RECT 879.675 617.545 879.875 618.275 ; + RECT 880.17 617.545 880.37 618.275 ; + RECT 880.135 0.3 880.395 4.63 ; + RECT 881.155 0.17 881.925 0.43 ; + RECT 881.155 0.17 881.415 8.7 ; + RECT 881.665 0.17 881.925 16.7 ; + RECT 880.645 0.3 880.905 4.63 ; + RECT 880.99 617.545 881.19 618.275 ; + RECT 881.485 617.545 881.685 618.275 ; + RECT 881.985 617.545 882.185 618.275 ; + RECT 882.485 617.545 882.685 618.275 ; + RECT 882.98 617.545 883.18 618.275 ; + RECT 883.8 617.545 884 618.275 ; + RECT 884.725 0.17 885.495 0.43 ; + RECT 884.725 0.17 884.985 11.38 ; + RECT 885.235 0.17 885.495 16.7 ; + RECT 884.295 617.545 884.495 618.275 ; + RECT 884.795 617.545 884.995 618.275 ; + RECT 885.295 617.545 885.495 618.275 ; + RECT 885.79 617.545 885.99 618.275 ; + RECT 886.61 617.545 886.81 618.275 ; + RECT 887.105 617.545 887.305 618.275 ; + RECT 887.605 617.545 887.805 618.275 ; + RECT 888.105 617.545 888.305 618.275 ; + RECT 888.6 617.545 888.8 618.275 ; + RECT 889.42 617.545 889.62 618.275 ; + RECT 889.395 0.3 889.655 8.23 ; + RECT 889.915 617.545 890.115 618.275 ; + RECT 890.415 0.165 891.185 0.425 ; + RECT 890.415 0.165 890.675 8.825 ; + RECT 890.925 0.165 891.185 8.825 ; + RECT 889.905 0.3 890.165 4.63 ; + RECT 890.415 617.545 890.615 618.275 ; + RECT 890.915 617.545 891.115 618.275 ; + RECT 891.41 617.545 891.61 618.275 ; + RECT 892.23 617.545 892.43 618.275 ; + RECT 892.725 617.545 892.925 618.275 ; + RECT 893.225 617.545 893.425 618.275 ; + RECT 893.63 0.52 893.89 4.5 ; + RECT 893.725 617.545 893.925 618.275 ; + RECT 894.22 617.545 894.42 618.275 ; + RECT 895.04 617.545 895.24 618.275 ; + RECT 895.535 617.545 895.735 618.275 ; + RECT 895.57 0.3 895.83 4.63 ; + RECT 896.035 617.545 896.235 618.275 ; + RECT 896.59 0.16 897.36 0.42 ; + RECT 896.59 0.16 896.85 8.82 ; + RECT 897.1 0.16 897.36 8.82 ; + RECT 896.08 0.3 896.34 4.63 ; + RECT 896.535 617.545 896.735 618.275 ; + RECT 897.03 617.545 897.23 618.275 ; + RECT 897.85 617.545 898.05 618.275 ; + RECT 898.345 617.545 898.545 618.275 ; + RECT 898.845 617.545 899.045 618.275 ; + RECT 899.345 617.545 899.545 618.275 ; + RECT 899.84 617.545 900.04 618.275 ; + RECT 900.105 0.3 900.365 4.63 ; + RECT 900.66 617.545 900.86 618.275 ; + RECT 901.125 0.16 901.895 0.42 ; + RECT 901.125 0.16 901.385 4.63 ; + RECT 901.635 0.16 901.895 8.82 ; + RECT 900.615 0.3 900.875 4.63 ; + RECT 901.155 617.545 901.355 618.275 ; + RECT 901.655 617.545 901.855 618.275 ; + RECT 902.155 617.545 902.355 618.275 ; + RECT 902.65 617.545 902.85 618.275 ; + RECT 903.47 617.545 903.67 618.275 ; + RECT 903.965 617.545 904.165 618.275 ; + RECT 904.465 617.545 904.665 618.275 ; + RECT 904.965 617.545 905.165 618.275 ; + RECT 905.46 617.545 905.66 618.275 ; + RECT 906.28 617.545 906.48 618.275 ; + RECT 906.775 617.545 906.975 618.275 ; + RECT 907.275 617.545 907.475 618.275 ; + RECT 907.775 617.545 907.975 618.275 ; + RECT 908.27 617.545 908.47 618.275 ; + RECT 909.09 617.545 909.29 618.275 ; + RECT 909.585 617.545 909.785 618.275 ; + RECT 910.085 617.545 910.285 618.275 ; + RECT 910.585 617.545 910.785 618.275 ; + RECT 911.08 617.545 911.28 618.275 ; + RECT 911.9 617.545 912.1 618.275 ; + RECT 912.395 617.545 912.595 618.275 ; + RECT 912.895 617.545 913.095 618.275 ; + RECT 913.395 617.545 913.595 618.275 ; + RECT 913.89 617.545 914.09 618.275 ; + RECT 914.71 617.545 914.91 618.275 ; + RECT 915.205 617.545 915.405 618.275 ; + RECT 915.405 0.52 915.665 4.5 ; + RECT 916.325 0.165 917.095 0.425 ; + RECT 916.325 0.165 916.585 8.825 ; + RECT 916.835 0.165 917.095 8.825 ; + RECT 915.705 617.545 915.905 618.275 ; + RECT 916.205 617.545 916.405 618.275 ; + RECT 916.7 617.545 916.9 618.275 ; + RECT 917.345 0.3 917.605 4.63 ; + RECT 917.52 617.545 917.72 618.275 ; + RECT 917.855 0.3 918.115 4.63 ; + RECT 918.015 617.545 918.215 618.275 ; + RECT 918.515 617.545 918.715 618.275 ; + RECT 919.015 617.545 919.215 618.275 ; + RECT 919.51 617.545 919.71 618.275 ; + RECT 920.33 617.545 920.53 618.275 ; + RECT 920.825 617.545 921.025 618.275 ; + RECT 921.325 617.545 921.525 618.275 ; + RECT 921.825 617.545 922.025 618.275 ; + RECT 922.32 617.545 922.52 618.275 ; + RECT 923.14 617.545 923.34 618.275 ; + RECT 924.075 0.17 924.845 0.43 ; + RECT 924.075 0.17 924.335 8.7 ; + RECT 924.585 0.17 924.845 16.7 ; + RECT 923.635 617.545 923.835 618.275 ; + RECT 924.135 617.545 924.335 618.275 ; + RECT 924.635 617.545 924.835 618.275 ; + RECT 925.13 617.545 925.33 618.275 ; + RECT 925.095 0.3 925.355 4.63 ; + RECT 926.115 0.17 926.885 0.43 ; + RECT 926.115 0.17 926.375 8.7 ; + RECT 926.625 0.17 926.885 16.7 ; + RECT 925.605 0.3 925.865 4.63 ; + RECT 925.95 617.545 926.15 618.275 ; + RECT 926.445 617.545 926.645 618.275 ; + RECT 926.945 617.545 927.145 618.275 ; + RECT 927.445 617.545 927.645 618.275 ; + RECT 927.94 617.545 928.14 618.275 ; + RECT 928.76 617.545 928.96 618.275 ; + RECT 929.685 0.17 930.455 0.43 ; + RECT 929.685 0.17 929.945 11.38 ; + RECT 930.195 0.17 930.455 16.7 ; + RECT 929.255 617.545 929.455 618.275 ; + RECT 929.755 617.545 929.955 618.275 ; + RECT 930.255 617.545 930.455 618.275 ; + RECT 930.75 617.545 930.95 618.275 ; + RECT 931.57 617.545 931.77 618.275 ; + RECT 932.065 617.545 932.265 618.275 ; + RECT 932.565 617.545 932.765 618.275 ; + RECT 933.065 617.545 933.265 618.275 ; + RECT 933.56 617.545 933.76 618.275 ; + RECT 934.38 617.545 934.58 618.275 ; + RECT 934.355 0.3 934.615 8.23 ; + RECT 934.875 617.545 935.075 618.275 ; + RECT 935.375 0.165 936.145 0.425 ; + RECT 935.375 0.165 935.635 8.825 ; + RECT 935.885 0.165 936.145 8.825 ; + RECT 934.865 0.3 935.125 4.63 ; + RECT 935.375 617.545 935.575 618.275 ; + RECT 935.875 617.545 936.075 618.275 ; + RECT 936.37 617.545 936.57 618.275 ; + RECT 937.19 617.545 937.39 618.275 ; + RECT 937.685 617.545 937.885 618.275 ; + RECT 938.185 617.545 938.385 618.275 ; + RECT 938.59 0.52 938.85 4.5 ; + RECT 938.685 617.545 938.885 618.275 ; + RECT 939.18 617.545 939.38 618.275 ; + RECT 940 617.545 940.2 618.275 ; + RECT 940.495 617.545 940.695 618.275 ; + RECT 940.53 0.3 940.79 4.63 ; + RECT 940.995 617.545 941.195 618.275 ; + RECT 941.55 0.16 942.32 0.42 ; + RECT 941.55 0.16 941.81 8.82 ; + RECT 942.06 0.16 942.32 8.82 ; + RECT 941.04 0.3 941.3 4.63 ; + RECT 941.495 617.545 941.695 618.275 ; + RECT 941.99 617.545 942.19 618.275 ; + RECT 942.81 617.545 943.01 618.275 ; + RECT 943.305 617.545 943.505 618.275 ; + RECT 943.805 617.545 944.005 618.275 ; + RECT 944.305 617.545 944.505 618.275 ; + RECT 944.8 617.545 945 618.275 ; + RECT 945.065 0.3 945.325 4.63 ; + RECT 945.62 617.545 945.82 618.275 ; + RECT 946.085 0.16 946.855 0.42 ; + RECT 946.085 0.16 946.345 4.63 ; + RECT 946.595 0.16 946.855 8.82 ; + RECT 945.575 0.3 945.835 4.63 ; + RECT 946.115 617.545 946.315 618.275 ; + RECT 946.615 617.545 946.815 618.275 ; + RECT 947.115 617.545 947.315 618.275 ; + RECT 947.61 617.545 947.81 618.275 ; + RECT 948.43 617.545 948.63 618.275 ; + RECT 948.925 617.545 949.125 618.275 ; + RECT 949.425 617.545 949.625 618.275 ; + RECT 949.925 617.545 950.125 618.275 ; + RECT 950.42 617.545 950.62 618.275 ; + RECT 951.24 617.545 951.44 618.275 ; + RECT 951.735 617.545 951.935 618.275 ; + RECT 952.235 617.545 952.435 618.275 ; + RECT 952.735 617.545 952.935 618.275 ; + RECT 953.23 617.545 953.43 618.275 ; + RECT 954.05 617.545 954.25 618.275 ; + RECT 954.545 617.545 954.745 618.275 ; + RECT 955.045 617.545 955.245 618.275 ; + RECT 955.545 617.545 955.745 618.275 ; + RECT 956.04 617.545 956.24 618.275 ; + RECT 956.86 617.545 957.06 618.275 ; + RECT 957.355 617.545 957.555 618.275 ; + RECT 957.855 617.545 958.055 618.275 ; + RECT 958.355 617.545 958.555 618.275 ; + RECT 958.85 617.545 959.05 618.275 ; + RECT 959.67 617.545 959.87 618.275 ; + RECT 960.165 617.545 960.365 618.275 ; + RECT 960.365 0.52 960.625 4.5 ; + RECT 961.285 0.165 962.055 0.425 ; + RECT 961.285 0.165 961.545 8.825 ; + RECT 961.795 0.165 962.055 8.825 ; + RECT 960.665 617.545 960.865 618.275 ; + RECT 961.165 617.545 961.365 618.275 ; + RECT 961.66 617.545 961.86 618.275 ; + RECT 962.305 0.3 962.565 4.63 ; + RECT 962.48 617.545 962.68 618.275 ; + RECT 962.815 0.3 963.075 4.63 ; + RECT 962.975 617.545 963.175 618.275 ; + RECT 963.475 617.545 963.675 618.275 ; + RECT 963.975 617.545 964.175 618.275 ; + RECT 964.47 617.545 964.67 618.275 ; + RECT 965.29 617.545 965.49 618.275 ; + RECT 965.785 617.545 965.985 618.275 ; + RECT 966.285 617.545 966.485 618.275 ; + RECT 966.785 617.545 966.985 618.275 ; + RECT 967.28 617.545 967.48 618.275 ; + RECT 968.1 617.545 968.3 618.275 ; + RECT 969.035 0.17 969.805 0.43 ; + RECT 969.035 0.17 969.295 8.7 ; + RECT 969.545 0.17 969.805 16.7 ; + RECT 968.595 617.545 968.795 618.275 ; + RECT 969.095 617.545 969.295 618.275 ; + RECT 969.595 617.545 969.795 618.275 ; + RECT 970.09 617.545 970.29 618.275 ; + RECT 970.055 0.3 970.315 4.63 ; + RECT 971.075 0.17 971.845 0.43 ; + RECT 971.075 0.17 971.335 8.7 ; + RECT 971.585 0.17 971.845 16.7 ; + RECT 970.565 0.3 970.825 4.63 ; + RECT 970.91 617.545 971.11 618.275 ; + RECT 971.405 617.545 971.605 618.275 ; + RECT 971.905 617.545 972.105 618.275 ; + RECT 972.405 617.545 972.605 618.275 ; + RECT 972.9 617.545 973.1 618.275 ; + RECT 973.72 617.545 973.92 618.275 ; + RECT 974.645 0.17 975.415 0.43 ; + RECT 974.645 0.17 974.905 11.38 ; + RECT 975.155 0.17 975.415 16.7 ; + RECT 974.215 617.545 974.415 618.275 ; + RECT 974.715 617.545 974.915 618.275 ; + RECT 975.215 617.545 975.415 618.275 ; + RECT 975.71 617.545 975.91 618.275 ; + RECT 976.53 617.545 976.73 618.275 ; + RECT 977.025 617.545 977.225 618.275 ; + RECT 977.525 617.545 977.725 618.275 ; + RECT 978.025 617.545 978.225 618.275 ; + RECT 978.52 617.545 978.72 618.275 ; + RECT 979.34 617.545 979.54 618.275 ; + RECT 979.315 0.3 979.575 8.23 ; + RECT 979.835 617.545 980.035 618.275 ; + RECT 980.335 0.165 981.105 0.425 ; + RECT 980.335 0.165 980.595 8.825 ; + RECT 980.845 0.165 981.105 8.825 ; + RECT 979.825 0.3 980.085 4.63 ; + RECT 980.335 617.545 980.535 618.275 ; + RECT 980.835 617.545 981.035 618.275 ; + RECT 981.33 617.545 981.53 618.275 ; + RECT 982.15 617.545 982.35 618.275 ; + RECT 982.645 617.545 982.845 618.275 ; + RECT 983.145 617.545 983.345 618.275 ; + RECT 983.55 0.52 983.81 4.5 ; + RECT 983.645 617.545 983.845 618.275 ; + RECT 984.14 617.545 984.34 618.275 ; + RECT 984.96 617.545 985.16 618.275 ; + RECT 985.455 617.545 985.655 618.275 ; + RECT 985.49 0.3 985.75 4.63 ; + RECT 985.955 617.545 986.155 618.275 ; + RECT 986.51 0.16 987.28 0.42 ; + RECT 986.51 0.16 986.77 8.82 ; + RECT 987.02 0.16 987.28 8.82 ; + RECT 986 0.3 986.26 4.63 ; + RECT 986.455 617.545 986.655 618.275 ; + RECT 986.95 617.545 987.15 618.275 ; + RECT 987.77 617.545 987.97 618.275 ; + RECT 988.265 617.545 988.465 618.275 ; + RECT 988.765 617.545 988.965 618.275 ; + RECT 989.265 617.545 989.465 618.275 ; + RECT 989.76 617.545 989.96 618.275 ; + RECT 990.025 0.3 990.285 4.63 ; + RECT 990.58 617.545 990.78 618.275 ; + RECT 991.045 0.16 991.815 0.42 ; + RECT 991.045 0.16 991.305 4.63 ; + RECT 991.555 0.16 991.815 8.82 ; + RECT 990.535 0.3 990.795 4.63 ; + RECT 991.075 617.545 991.275 618.275 ; + RECT 991.575 617.545 991.775 618.275 ; + RECT 992.075 617.545 992.275 618.275 ; + RECT 992.57 617.545 992.77 618.275 ; + RECT 993.39 617.545 993.59 618.275 ; + RECT 993.885 617.545 994.085 618.275 ; + RECT 994.385 617.545 994.585 618.275 ; + RECT 994.885 617.545 995.085 618.275 ; + RECT 995.38 617.545 995.58 618.275 ; + RECT 996.2 617.545 996.4 618.275 ; + RECT 996.695 617.545 996.895 618.275 ; + RECT 997.195 617.545 997.395 618.275 ; + RECT 997.695 617.545 997.895 618.275 ; + RECT 998.19 617.545 998.39 618.275 ; + RECT 999.01 617.545 999.21 618.275 ; + RECT 999.505 617.545 999.705 618.275 ; + RECT 1000.005 617.545 1000.205 618.275 ; + RECT 1000.505 617.545 1000.705 618.275 ; + RECT 1001 617.545 1001.2 618.275 ; + RECT 1001.82 617.545 1002.02 618.275 ; + RECT 1002.315 617.545 1002.515 618.275 ; + RECT 1002.815 617.545 1003.015 618.275 ; + RECT 1003.315 617.545 1003.515 618.275 ; + RECT 1003.81 617.545 1004.01 618.275 ; + RECT 1004.63 617.545 1004.83 618.275 ; + RECT 1005.125 617.545 1005.325 618.275 ; + RECT 1005.325 0.52 1005.585 4.5 ; + RECT 1006.245 0.165 1007.015 0.425 ; + RECT 1006.245 0.165 1006.505 8.825 ; + RECT 1006.755 0.165 1007.015 8.825 ; + RECT 1005.625 617.545 1005.825 618.275 ; + RECT 1006.125 617.545 1006.325 618.275 ; + RECT 1006.62 617.545 1006.82 618.275 ; + RECT 1007.265 0.3 1007.525 4.63 ; + RECT 1007.44 617.545 1007.64 618.275 ; + RECT 1007.775 0.3 1008.035 4.63 ; + RECT 1007.935 617.545 1008.135 618.275 ; + RECT 1008.435 617.545 1008.635 618.275 ; + RECT 1008.935 617.545 1009.135 618.275 ; + RECT 1009.43 617.545 1009.63 618.275 ; + RECT 1010.25 617.545 1010.45 618.275 ; + RECT 1010.745 617.545 1010.945 618.275 ; + RECT 1011.245 617.545 1011.445 618.275 ; + RECT 1011.745 617.545 1011.945 618.275 ; + RECT 1012.24 617.545 1012.44 618.275 ; + RECT 1013.06 617.545 1013.26 618.275 ; + RECT 1013.995 0.17 1014.765 0.43 ; + RECT 1013.995 0.17 1014.255 8.7 ; + RECT 1014.505 0.17 1014.765 16.7 ; + RECT 1013.555 617.545 1013.755 618.275 ; + RECT 1014.055 617.545 1014.255 618.275 ; + RECT 1014.555 617.545 1014.755 618.275 ; + RECT 1015.05 617.545 1015.25 618.275 ; + RECT 1015.015 0.3 1015.275 4.63 ; + RECT 1016.035 0.17 1016.805 0.43 ; + RECT 1016.035 0.17 1016.295 8.7 ; + RECT 1016.545 0.17 1016.805 16.7 ; + RECT 1015.525 0.3 1015.785 4.63 ; + RECT 1015.87 617.545 1016.07 618.275 ; + RECT 1016.365 617.545 1016.565 618.275 ; + RECT 1016.865 617.545 1017.065 618.275 ; + RECT 1017.365 617.545 1017.565 618.275 ; + RECT 1017.86 617.545 1018.06 618.275 ; + RECT 1018.68 617.545 1018.88 618.275 ; + RECT 1019.605 0.17 1020.375 0.43 ; + RECT 1019.605 0.17 1019.865 11.38 ; + RECT 1020.115 0.17 1020.375 16.7 ; + RECT 1019.175 617.545 1019.375 618.275 ; + RECT 1019.675 617.545 1019.875 618.275 ; + RECT 1020.175 617.545 1020.375 618.275 ; + RECT 1020.67 617.545 1020.87 618.275 ; + RECT 1021.49 617.545 1021.69 618.275 ; + RECT 1021.985 617.545 1022.185 618.275 ; + RECT 1022.485 617.545 1022.685 618.275 ; + RECT 1022.985 617.545 1023.185 618.275 ; + RECT 1023.48 617.545 1023.68 618.275 ; + RECT 1024.3 617.545 1024.5 618.275 ; + RECT 1024.275 0.3 1024.535 8.23 ; + RECT 1024.795 617.545 1024.995 618.275 ; + RECT 1025.295 0.165 1026.065 0.425 ; + RECT 1025.295 0.165 1025.555 8.825 ; + RECT 1025.805 0.165 1026.065 8.825 ; + RECT 1024.785 0.3 1025.045 4.63 ; + RECT 1025.295 617.545 1025.495 618.275 ; + RECT 1025.795 617.545 1025.995 618.275 ; + RECT 1026.29 617.545 1026.49 618.275 ; + RECT 1027.11 617.545 1027.31 618.275 ; + RECT 1027.605 617.545 1027.805 618.275 ; + RECT 1028.105 617.545 1028.305 618.275 ; + RECT 1028.51 0.52 1028.77 4.5 ; + RECT 1028.605 617.545 1028.805 618.275 ; + RECT 1029.1 617.545 1029.3 618.275 ; + RECT 1029.92 617.545 1030.12 618.275 ; + RECT 1030.415 617.545 1030.615 618.275 ; + RECT 1030.45 0.3 1030.71 4.63 ; + RECT 1030.915 617.545 1031.115 618.275 ; + RECT 1031.47 0.16 1032.24 0.42 ; + RECT 1031.47 0.16 1031.73 8.82 ; + RECT 1031.98 0.16 1032.24 8.82 ; + RECT 1030.96 0.3 1031.22 4.63 ; + RECT 1031.415 617.545 1031.615 618.275 ; + RECT 1031.91 617.545 1032.11 618.275 ; + RECT 1032.73 617.545 1032.93 618.275 ; + RECT 1033.225 617.545 1033.425 618.275 ; + RECT 1033.725 617.545 1033.925 618.275 ; + RECT 1034.225 617.545 1034.425 618.275 ; + RECT 1034.72 617.545 1034.92 618.275 ; + RECT 1034.985 0.3 1035.245 4.63 ; + RECT 1035.54 617.545 1035.74 618.275 ; + RECT 1036.005 0.16 1036.775 0.42 ; + RECT 1036.005 0.16 1036.265 4.63 ; + RECT 1036.515 0.16 1036.775 8.82 ; + RECT 1035.495 0.3 1035.755 4.63 ; + RECT 1036.035 617.545 1036.235 618.275 ; + RECT 1036.535 617.545 1036.735 618.275 ; + RECT 1037.035 617.545 1037.235 618.275 ; + RECT 1037.53 617.545 1037.73 618.275 ; + RECT 1038.35 617.545 1038.55 618.275 ; + RECT 1038.845 617.545 1039.045 618.275 ; + RECT 1039.345 617.545 1039.545 618.275 ; + RECT 1039.845 617.545 1040.045 618.275 ; + RECT 1040.34 617.545 1040.54 618.275 ; + RECT 1041.16 617.545 1041.36 618.275 ; + RECT 1041.655 617.545 1041.855 618.275 ; + RECT 1042.155 617.545 1042.355 618.275 ; + RECT 1042.655 617.545 1042.855 618.275 ; + RECT 1043.15 617.545 1043.35 618.275 ; + RECT 1043.97 617.545 1044.17 618.275 ; + RECT 1044.465 617.545 1044.665 618.275 ; + RECT 1044.965 617.545 1045.165 618.275 ; + RECT 1045.465 617.545 1045.665 618.275 ; + RECT 1045.96 617.545 1046.16 618.275 ; + RECT 1046.78 617.545 1046.98 618.275 ; + RECT 1047.275 617.545 1047.475 618.275 ; + RECT 1047.775 617.545 1047.975 618.275 ; + RECT 1048.275 617.545 1048.475 618.275 ; + RECT 1048.77 617.545 1048.97 618.275 ; + RECT 1049.59 617.545 1049.79 618.275 ; + RECT 1050.085 617.545 1050.285 618.275 ; + RECT 1050.285 0.52 1050.545 4.5 ; + RECT 1051.205 0.165 1051.975 0.425 ; + RECT 1051.205 0.165 1051.465 8.825 ; + RECT 1051.715 0.165 1051.975 8.825 ; + RECT 1050.585 617.545 1050.785 618.275 ; + RECT 1051.085 617.545 1051.285 618.275 ; + RECT 1051.58 617.545 1051.78 618.275 ; + RECT 1052.225 0.3 1052.485 4.63 ; + RECT 1052.4 617.545 1052.6 618.275 ; + RECT 1052.735 0.3 1052.995 4.63 ; + RECT 1052.895 617.545 1053.095 618.275 ; + RECT 1053.395 617.545 1053.595 618.275 ; + RECT 1053.895 617.545 1054.095 618.275 ; + RECT 1054.39 617.545 1054.59 618.275 ; + RECT 1055.21 617.545 1055.41 618.275 ; + RECT 1055.705 617.545 1055.905 618.275 ; + RECT 1056.205 617.545 1056.405 618.275 ; + RECT 1056.705 617.545 1056.905 618.275 ; + RECT 1057.2 617.545 1057.4 618.275 ; + RECT 1058.02 617.545 1058.22 618.275 ; + RECT 1058.955 0.17 1059.725 0.43 ; + RECT 1058.955 0.17 1059.215 8.7 ; + RECT 1059.465 0.17 1059.725 16.7 ; + RECT 1058.515 617.545 1058.715 618.275 ; + RECT 1059.015 617.545 1059.215 618.275 ; + RECT 1059.515 617.545 1059.715 618.275 ; + RECT 1060.01 617.545 1060.21 618.275 ; + RECT 1059.975 0.3 1060.235 4.63 ; + RECT 1060.995 0.17 1061.765 0.43 ; + RECT 1060.995 0.17 1061.255 8.7 ; + RECT 1061.505 0.17 1061.765 16.7 ; + RECT 1060.485 0.3 1060.745 4.63 ; + RECT 1060.83 617.545 1061.03 618.275 ; + RECT 1061.325 617.545 1061.525 618.275 ; + RECT 1061.825 617.545 1062.025 618.275 ; + RECT 1062.325 617.545 1062.525 618.275 ; + RECT 1062.82 617.545 1063.02 618.275 ; + RECT 1063.64 617.545 1063.84 618.275 ; + RECT 1064.565 0.17 1065.335 0.43 ; + RECT 1064.565 0.17 1064.825 11.38 ; + RECT 1065.075 0.17 1065.335 16.7 ; + RECT 1064.135 617.545 1064.335 618.275 ; + RECT 1064.635 617.545 1064.835 618.275 ; + RECT 1065.135 617.545 1065.335 618.275 ; + RECT 1065.63 617.545 1065.83 618.275 ; + RECT 1066.45 617.545 1066.65 618.275 ; + RECT 1066.945 617.545 1067.145 618.275 ; + RECT 1067.445 617.545 1067.645 618.275 ; + RECT 1067.945 617.545 1068.145 618.275 ; + RECT 1068.44 617.545 1068.64 618.275 ; + RECT 1069.26 617.545 1069.46 618.275 ; + RECT 1069.235 0.3 1069.495 8.23 ; + RECT 1069.755 617.545 1069.955 618.275 ; + RECT 1070.255 0.165 1071.025 0.425 ; + RECT 1070.255 0.165 1070.515 8.825 ; + RECT 1070.765 0.165 1071.025 8.825 ; + RECT 1069.745 0.3 1070.005 4.63 ; + RECT 1070.255 617.545 1070.455 618.275 ; + RECT 1070.755 617.545 1070.955 618.275 ; + RECT 1071.25 617.545 1071.45 618.275 ; + RECT 1072.07 617.545 1072.27 618.275 ; + RECT 1072.565 617.545 1072.765 618.275 ; + RECT 1073.065 617.545 1073.265 618.275 ; + RECT 1073.47 0.52 1073.73 4.5 ; + RECT 1073.565 617.545 1073.765 618.275 ; + RECT 1074.06 617.545 1074.26 618.275 ; + RECT 1074.88 617.545 1075.08 618.275 ; + RECT 1075.375 617.545 1075.575 618.275 ; + RECT 1075.41 0.3 1075.67 4.63 ; + RECT 1075.875 617.545 1076.075 618.275 ; + RECT 1076.43 0.16 1077.2 0.42 ; + RECT 1076.43 0.16 1076.69 8.82 ; + RECT 1076.94 0.16 1077.2 8.82 ; + RECT 1075.92 0.3 1076.18 4.63 ; + RECT 1076.375 617.545 1076.575 618.275 ; + RECT 1076.87 617.545 1077.07 618.275 ; + RECT 1077.69 617.545 1077.89 618.275 ; + RECT 1078.185 617.545 1078.385 618.275 ; + RECT 1078.685 617.545 1078.885 618.275 ; + RECT 1079.185 617.545 1079.385 618.275 ; + RECT 1079.68 617.545 1079.88 618.275 ; + RECT 1079.945 0.3 1080.205 4.63 ; + RECT 1080.5 617.545 1080.7 618.275 ; + RECT 1080.965 0.16 1081.735 0.42 ; + RECT 1080.965 0.16 1081.225 4.63 ; + RECT 1081.475 0.16 1081.735 8.82 ; + RECT 1080.455 0.3 1080.715 4.63 ; + RECT 1080.995 617.545 1081.195 618.275 ; + RECT 1081.495 617.545 1081.695 618.275 ; + RECT 1081.995 617.545 1082.195 618.275 ; + RECT 1082.49 617.545 1082.69 618.275 ; + RECT 1083.31 617.545 1083.51 618.275 ; + RECT 1083.805 617.545 1084.005 618.275 ; + RECT 1084.305 617.545 1084.505 618.275 ; + RECT 1084.805 617.545 1085.005 618.275 ; + RECT 1085.3 617.545 1085.5 618.275 ; + RECT 1086.12 617.545 1086.32 618.275 ; + RECT 1086.615 617.545 1086.815 618.275 ; + RECT 1087.115 617.545 1087.315 618.275 ; + RECT 1087.615 617.545 1087.815 618.275 ; + RECT 1088.11 617.545 1088.31 618.275 ; + RECT 1088.93 617.545 1089.13 618.275 ; + RECT 1089.425 617.545 1089.625 618.275 ; + RECT 1089.925 617.545 1090.125 618.275 ; + RECT 1090.425 617.545 1090.625 618.275 ; + RECT 1090.92 617.545 1091.12 618.275 ; + RECT 1091.74 617.545 1091.94 618.275 ; + RECT 1092.235 617.545 1092.435 618.275 ; + RECT 1092.735 617.545 1092.935 618.275 ; + RECT 1093.235 617.545 1093.435 618.275 ; + RECT 1093.73 617.545 1093.93 618.275 ; + RECT 1094.55 617.545 1094.75 618.275 ; + RECT 1095.045 617.545 1095.245 618.275 ; + RECT 1095.245 0.52 1095.505 4.5 ; + RECT 1096.165 0.165 1096.935 0.425 ; + RECT 1096.165 0.165 1096.425 8.825 ; + RECT 1096.675 0.165 1096.935 8.825 ; + RECT 1095.545 617.545 1095.745 618.275 ; + RECT 1096.045 617.545 1096.245 618.275 ; + RECT 1096.54 617.545 1096.74 618.275 ; + RECT 1097.185 0.3 1097.445 4.63 ; + RECT 1097.36 617.545 1097.56 618.275 ; + RECT 1097.695 0.3 1097.955 4.63 ; + RECT 1097.855 617.545 1098.055 618.275 ; + RECT 1098.355 617.545 1098.555 618.275 ; + RECT 1098.855 617.545 1099.055 618.275 ; + RECT 1099.35 617.545 1099.55 618.275 ; + RECT 1100.17 617.545 1100.37 618.275 ; + RECT 1100.665 617.545 1100.865 618.275 ; + RECT 1101.165 617.545 1101.365 618.275 ; + RECT 1101.665 617.545 1101.865 618.275 ; + RECT 1102.16 617.545 1102.36 618.275 ; + RECT 1102.98 617.545 1103.18 618.275 ; + RECT 1103.915 0.17 1104.685 0.43 ; + RECT 1103.915 0.17 1104.175 8.7 ; + RECT 1104.425 0.17 1104.685 16.7 ; + RECT 1103.475 617.545 1103.675 618.275 ; + RECT 1103.975 617.545 1104.175 618.275 ; + RECT 1104.475 617.545 1104.675 618.275 ; + RECT 1104.97 617.545 1105.17 618.275 ; + RECT 1104.935 0.3 1105.195 4.63 ; + RECT 1105.955 0.17 1106.725 0.43 ; + RECT 1105.955 0.17 1106.215 8.7 ; + RECT 1106.465 0.17 1106.725 16.7 ; + RECT 1105.445 0.3 1105.705 4.63 ; + RECT 1105.79 617.545 1105.99 618.275 ; + RECT 1106.285 617.545 1106.485 618.275 ; + RECT 1106.785 617.545 1106.985 618.275 ; + RECT 1107.285 617.545 1107.485 618.275 ; + RECT 1107.78 617.545 1107.98 618.275 ; + RECT 1108.6 617.545 1108.8 618.275 ; + RECT 1109.525 0.17 1110.295 0.43 ; + RECT 1109.525 0.17 1109.785 11.38 ; + RECT 1110.035 0.17 1110.295 16.7 ; + RECT 1109.095 617.545 1109.295 618.275 ; + RECT 1109.595 617.545 1109.795 618.275 ; + RECT 1110.095 617.545 1110.295 618.275 ; + RECT 1110.59 617.545 1110.79 618.275 ; + RECT 1111.41 617.545 1111.61 618.275 ; + RECT 1111.905 617.545 1112.105 618.275 ; + RECT 1112.405 617.545 1112.605 618.275 ; + RECT 1112.905 617.545 1113.105 618.275 ; + RECT 1113.4 617.545 1113.6 618.275 ; + RECT 1114.22 617.545 1114.42 618.275 ; + RECT 1114.195 0.3 1114.455 8.23 ; + RECT 1114.715 617.545 1114.915 618.275 ; + RECT 1115.215 0.165 1115.985 0.425 ; + RECT 1115.215 0.165 1115.475 8.825 ; + RECT 1115.725 0.165 1115.985 8.825 ; + RECT 1114.705 0.3 1114.965 4.63 ; + RECT 1115.215 617.545 1115.415 618.275 ; + RECT 1115.715 617.545 1115.915 618.275 ; + RECT 1116.21 617.545 1116.41 618.275 ; + RECT 1117.03 617.545 1117.23 618.275 ; + RECT 1117.525 617.545 1117.725 618.275 ; + RECT 1118.025 617.545 1118.225 618.275 ; + RECT 1118.43 0.52 1118.69 4.5 ; + RECT 1118.525 617.545 1118.725 618.275 ; + RECT 1119.02 617.545 1119.22 618.275 ; + RECT 1119.84 617.545 1120.04 618.275 ; + RECT 1120.335 617.545 1120.535 618.275 ; + RECT 1120.37 0.3 1120.63 4.63 ; + RECT 1120.835 617.545 1121.035 618.275 ; + RECT 1121.39 0.16 1122.16 0.42 ; + RECT 1121.39 0.16 1121.65 8.82 ; + RECT 1121.9 0.16 1122.16 8.82 ; + RECT 1120.88 0.3 1121.14 4.63 ; + RECT 1121.335 617.545 1121.535 618.275 ; + RECT 1121.83 617.545 1122.03 618.275 ; + RECT 1122.65 617.545 1122.85 618.275 ; + RECT 1123.145 617.545 1123.345 618.275 ; + RECT 1123.645 617.545 1123.845 618.275 ; + RECT 1124.145 617.545 1124.345 618.275 ; + RECT 1124.64 617.545 1124.84 618.275 ; + RECT 1124.905 0.3 1125.165 4.63 ; + RECT 1125.46 617.545 1125.66 618.275 ; + RECT 1125.925 0.16 1126.695 0.42 ; + RECT 1125.925 0.16 1126.185 4.63 ; + RECT 1126.435 0.16 1126.695 8.82 ; + RECT 1125.415 0.3 1125.675 4.63 ; + RECT 1125.955 617.545 1126.155 618.275 ; + RECT 1126.455 617.545 1126.655 618.275 ; + RECT 1126.955 617.545 1127.155 618.275 ; + RECT 1127.45 617.545 1127.65 618.275 ; + RECT 1128.27 617.545 1128.47 618.275 ; + RECT 1128.765 617.545 1128.965 618.275 ; + RECT 1129.265 617.545 1129.465 618.275 ; + RECT 1129.765 617.545 1129.965 618.275 ; + RECT 1130.26 617.545 1130.46 618.275 ; + RECT 1131.08 617.545 1131.28 618.275 ; + RECT 1131.575 617.545 1131.775 618.275 ; + RECT 1132.075 617.545 1132.275 618.275 ; + RECT 1132.575 617.545 1132.775 618.275 ; + RECT 1133.07 617.545 1133.27 618.275 ; + RECT 1133.89 617.545 1134.09 618.275 ; + RECT 1134.385 617.545 1134.585 618.275 ; + RECT 1134.885 617.545 1135.085 618.275 ; + RECT 1135.385 617.545 1135.585 618.275 ; + RECT 1135.88 617.545 1136.08 618.275 ; + RECT 1136.7 617.545 1136.9 618.275 ; + RECT 1137.195 617.545 1137.395 618.275 ; + RECT 1137.695 617.545 1137.895 618.275 ; + RECT 1138.195 617.545 1138.395 618.275 ; + RECT 1138.69 617.545 1138.89 618.275 ; + RECT 1139.51 617.545 1139.71 618.275 ; + RECT 1140.005 617.545 1140.205 618.275 ; + RECT 1140.205 0.52 1140.465 4.5 ; + RECT 1141.125 0.165 1141.895 0.425 ; + RECT 1141.125 0.165 1141.385 8.825 ; + RECT 1141.635 0.165 1141.895 8.825 ; + RECT 1140.505 617.545 1140.705 618.275 ; + RECT 1141.005 617.545 1141.205 618.275 ; + RECT 1141.5 617.545 1141.7 618.275 ; + RECT 1142.145 0.3 1142.405 4.63 ; + RECT 1142.32 617.545 1142.52 618.275 ; + RECT 1142.655 0.3 1142.915 4.63 ; + RECT 1142.815 617.545 1143.015 618.275 ; + RECT 1143.315 617.545 1143.515 618.275 ; + RECT 1143.815 617.545 1144.015 618.275 ; + RECT 1144.31 617.545 1144.51 618.275 ; + RECT 1145.13 617.545 1145.33 618.275 ; + RECT 1145.625 617.545 1145.825 618.275 ; + RECT 1146.125 617.545 1146.325 618.275 ; + RECT 1146.625 617.545 1146.825 618.275 ; + RECT 1147.12 617.545 1147.32 618.275 ; + RECT 1147.94 617.545 1148.14 618.275 ; + RECT 1148.875 0.17 1149.645 0.43 ; + RECT 1148.875 0.17 1149.135 8.7 ; + RECT 1149.385 0.17 1149.645 16.7 ; + RECT 1148.435 617.545 1148.635 618.275 ; + RECT 1148.935 617.545 1149.135 618.275 ; + RECT 1149.435 617.545 1149.635 618.275 ; + RECT 1149.93 617.545 1150.13 618.275 ; + RECT 1149.895 0.3 1150.155 4.63 ; + RECT 1150.915 0.17 1151.685 0.43 ; + RECT 1150.915 0.17 1151.175 8.7 ; + RECT 1151.425 0.17 1151.685 16.7 ; + RECT 1150.405 0.3 1150.665 4.63 ; + RECT 1150.75 617.545 1150.95 618.275 ; + RECT 1151.245 617.545 1151.445 618.275 ; + RECT 1151.745 617.545 1151.945 618.275 ; + RECT 1152.245 617.545 1152.445 618.275 ; + RECT 1152.74 617.545 1152.94 618.275 ; + RECT 1153.56 617.545 1153.76 618.275 ; + RECT 1154.485 0.17 1155.255 0.43 ; + RECT 1154.485 0.17 1154.745 11.38 ; + RECT 1154.995 0.17 1155.255 16.7 ; + RECT 1154.055 617.545 1154.255 618.275 ; + RECT 1154.555 617.545 1154.755 618.275 ; + RECT 1155.055 617.545 1155.255 618.275 ; + RECT 1155.55 617.545 1155.75 618.275 ; + RECT 1156.37 617.545 1156.57 618.275 ; + RECT 1156.865 617.545 1157.065 618.275 ; + RECT 1157.365 617.545 1157.565 618.275 ; + RECT 1157.865 617.545 1158.065 618.275 ; + RECT 1158.36 617.545 1158.56 618.275 ; + RECT 1159.18 617.545 1159.38 618.275 ; + RECT 1159.155 0.3 1159.415 8.23 ; + RECT 1159.675 617.545 1159.875 618.275 ; + RECT 1160.175 0.165 1160.945 0.425 ; + RECT 1160.175 0.165 1160.435 8.825 ; + RECT 1160.685 0.165 1160.945 8.825 ; + RECT 1159.665 0.3 1159.925 4.63 ; + RECT 1160.175 617.545 1160.375 618.275 ; + RECT 1160.675 617.545 1160.875 618.275 ; + RECT 1161.17 617.545 1161.37 618.275 ; + RECT 1161.99 617.545 1162.19 618.275 ; + RECT 1162.485 617.545 1162.685 618.275 ; + RECT 1162.985 617.545 1163.185 618.275 ; + RECT 1163.39 0.52 1163.65 4.5 ; + RECT 1163.485 617.545 1163.685 618.275 ; + RECT 1163.98 617.545 1164.18 618.275 ; + RECT 1164.8 617.545 1165 618.275 ; + RECT 1165.295 617.545 1165.495 618.275 ; + RECT 1165.33 0.3 1165.59 4.63 ; + RECT 1165.795 617.545 1165.995 618.275 ; + RECT 1166.35 0.16 1167.12 0.42 ; + RECT 1166.35 0.16 1166.61 8.82 ; + RECT 1166.86 0.16 1167.12 8.82 ; + RECT 1165.84 0.3 1166.1 4.63 ; + RECT 1166.295 617.545 1166.495 618.275 ; + RECT 1166.79 617.545 1166.99 618.275 ; + RECT 1167.61 617.545 1167.81 618.275 ; + RECT 1168.105 617.545 1168.305 618.275 ; + RECT 1168.605 617.545 1168.805 618.275 ; + RECT 1169.105 617.545 1169.305 618.275 ; + RECT 1169.6 617.545 1169.8 618.275 ; + RECT 1169.865 0.3 1170.125 4.63 ; + RECT 1170.42 617.545 1170.62 618.275 ; + RECT 1170.885 0.16 1171.655 0.42 ; + RECT 1170.885 0.16 1171.145 4.63 ; + RECT 1171.395 0.16 1171.655 8.82 ; + RECT 1170.375 0.3 1170.635 4.63 ; + RECT 1170.915 617.545 1171.115 618.275 ; + RECT 1171.415 617.545 1171.615 618.275 ; + RECT 1171.915 617.545 1172.115 618.275 ; + RECT 1172.41 617.545 1172.61 618.275 ; + RECT 1173.23 617.545 1173.43 618.275 ; + RECT 1173.725 617.545 1173.925 618.275 ; + RECT 1174.225 617.545 1174.425 618.275 ; + RECT 1174.725 617.545 1174.925 618.275 ; + RECT 1175.22 617.545 1175.42 618.275 ; + RECT 1176.04 617.545 1176.24 618.275 ; + RECT 1176.535 617.545 1176.735 618.275 ; + RECT 1177.035 617.545 1177.235 618.275 ; + RECT 1177.535 617.545 1177.735 618.275 ; + RECT 1178.03 617.545 1178.23 618.275 ; + RECT 1178.85 617.545 1179.05 618.275 ; + RECT 1179.345 617.545 1179.545 618.275 ; + RECT 1179.845 617.545 1180.045 618.275 ; + RECT 1180.345 617.545 1180.545 618.275 ; + RECT 1180.84 617.545 1181.04 618.275 ; + RECT 1181.66 617.545 1181.86 618.275 ; + RECT 1182.155 617.545 1182.355 618.275 ; + RECT 1182.655 617.545 1182.855 618.275 ; + RECT 1183.155 617.545 1183.355 618.275 ; + RECT 1183.65 617.545 1183.85 618.275 ; + RECT 1184.47 617.545 1184.67 618.275 ; + RECT 1184.965 617.545 1185.165 618.275 ; + RECT 1185.165 0.52 1185.425 4.5 ; + RECT 1186.085 0.165 1186.855 0.425 ; + RECT 1186.085 0.165 1186.345 8.825 ; + RECT 1186.595 0.165 1186.855 8.825 ; + RECT 1185.465 617.545 1185.665 618.275 ; + RECT 1185.965 617.545 1186.165 618.275 ; + RECT 1186.46 617.545 1186.66 618.275 ; + RECT 1187.105 0.3 1187.365 4.63 ; + RECT 1187.28 617.545 1187.48 618.275 ; + RECT 1187.615 0.3 1187.875 4.63 ; + RECT 1187.775 617.545 1187.975 618.275 ; + RECT 1188.275 617.545 1188.475 618.275 ; + RECT 1188.775 617.545 1188.975 618.275 ; + RECT 1189.27 617.545 1189.47 618.275 ; + RECT 1190.09 617.545 1190.29 618.275 ; + RECT 1190.585 617.545 1190.785 618.275 ; + RECT 1191.085 617.545 1191.285 618.275 ; + RECT 1191.585 617.545 1191.785 618.275 ; + RECT 1192.08 617.545 1192.28 618.275 ; + RECT 1192.9 617.545 1193.1 618.275 ; + RECT 1193.835 0.17 1194.605 0.43 ; + RECT 1193.835 0.17 1194.095 8.7 ; + RECT 1194.345 0.17 1194.605 16.7 ; + RECT 1193.395 617.545 1193.595 618.275 ; + RECT 1193.895 617.545 1194.095 618.275 ; + RECT 1194.395 617.545 1194.595 618.275 ; + RECT 1194.89 617.545 1195.09 618.275 ; + RECT 1194.855 0.3 1195.115 4.63 ; + RECT 1195.875 0.17 1196.645 0.43 ; + RECT 1195.875 0.17 1196.135 8.7 ; + RECT 1196.385 0.17 1196.645 16.7 ; + RECT 1195.365 0.3 1195.625 4.63 ; + RECT 1195.71 617.545 1195.91 618.275 ; + RECT 1196.205 617.545 1196.405 618.275 ; + RECT 1196.705 617.545 1196.905 618.275 ; + RECT 1197.205 617.545 1197.405 618.275 ; + RECT 1197.7 617.545 1197.9 618.275 ; + RECT 1198.52 617.545 1198.72 618.275 ; + RECT 1199.445 0.17 1200.215 0.43 ; + RECT 1199.445 0.17 1199.705 11.38 ; + RECT 1199.955 0.17 1200.215 16.7 ; + RECT 1199.015 617.545 1199.215 618.275 ; + RECT 1199.515 617.545 1199.715 618.275 ; + RECT 1200.015 617.545 1200.215 618.275 ; + RECT 1200.51 617.545 1200.71 618.275 ; + RECT 1201.33 617.545 1201.53 618.275 ; + RECT 1201.825 617.545 1202.025 618.275 ; + RECT 1202.325 617.545 1202.525 618.275 ; + RECT 1202.825 617.545 1203.025 618.275 ; + RECT 1203.32 617.545 1203.52 618.275 ; + RECT 1204.14 617.545 1204.34 618.275 ; + RECT 1204.115 0.3 1204.375 8.23 ; + RECT 1204.635 617.545 1204.835 618.275 ; + RECT 1205.135 0.165 1205.905 0.425 ; + RECT 1205.135 0.165 1205.395 8.825 ; + RECT 1205.645 0.165 1205.905 8.825 ; + RECT 1204.625 0.3 1204.885 4.63 ; + RECT 1205.135 617.545 1205.335 618.275 ; + RECT 1205.635 617.545 1205.835 618.275 ; + RECT 1206.13 617.545 1206.33 618.275 ; + RECT 1206.95 617.545 1207.15 618.275 ; + RECT 1207.445 617.545 1207.645 618.275 ; + RECT 1207.945 617.545 1208.145 618.275 ; + RECT 1208.35 0.52 1208.61 4.5 ; + RECT 1208.445 617.545 1208.645 618.275 ; + RECT 1208.94 617.545 1209.14 618.275 ; + RECT 1209.76 617.545 1209.96 618.275 ; + RECT 1210.255 617.545 1210.455 618.275 ; + RECT 1210.29 0.3 1210.55 4.63 ; + RECT 1210.755 617.545 1210.955 618.275 ; + RECT 1211.31 0.16 1212.08 0.42 ; + RECT 1211.31 0.16 1211.57 8.82 ; + RECT 1211.82 0.16 1212.08 8.82 ; + RECT 1210.8 0.3 1211.06 4.63 ; + RECT 1211.255 617.545 1211.455 618.275 ; + RECT 1211.75 617.545 1211.95 618.275 ; + RECT 1212.57 617.545 1212.77 618.275 ; + RECT 1213.065 617.545 1213.265 618.275 ; + RECT 1213.565 617.545 1213.765 618.275 ; + RECT 1214.065 617.545 1214.265 618.275 ; + RECT 1214.56 617.545 1214.76 618.275 ; + RECT 1214.825 0.3 1215.085 4.63 ; + RECT 1215.38 617.545 1215.58 618.275 ; + RECT 1215.845 0.16 1216.615 0.42 ; + RECT 1215.845 0.16 1216.105 4.63 ; + RECT 1216.355 0.16 1216.615 8.82 ; + RECT 1215.335 0.3 1215.595 4.63 ; + RECT 1215.875 617.545 1216.075 618.275 ; + RECT 1216.375 617.545 1216.575 618.275 ; + RECT 1216.875 617.545 1217.075 618.275 ; + RECT 1217.37 617.545 1217.57 618.275 ; + RECT 1218.19 617.545 1218.39 618.275 ; + RECT 1218.685 617.545 1218.885 618.275 ; + RECT 1219.185 617.545 1219.385 618.275 ; + RECT 1219.685 617.545 1219.885 618.275 ; + RECT 1220.18 617.545 1220.38 618.275 ; + RECT 1221 617.545 1221.2 618.275 ; + RECT 1221.495 617.545 1221.695 618.275 ; + RECT 1221.995 617.545 1222.195 618.275 ; + RECT 1222.495 617.545 1222.695 618.275 ; + RECT 1222.99 617.545 1223.19 618.275 ; + RECT 1223.81 617.545 1224.01 618.275 ; + RECT 1224.305 617.545 1224.505 618.275 ; + RECT 1224.805 617.545 1225.005 618.275 ; + RECT 1225.305 617.545 1225.505 618.275 ; + RECT 1225.8 617.545 1226 618.275 ; + RECT 1226.62 617.545 1226.82 618.275 ; + RECT 1227.115 617.545 1227.315 618.275 ; + RECT 1227.615 617.545 1227.815 618.275 ; + RECT 1228.115 617.545 1228.315 618.275 ; + RECT 1228.61 617.545 1228.81 618.275 ; + RECT 1229.43 617.545 1229.63 618.275 ; + RECT 1229.925 617.545 1230.125 618.275 ; + RECT 1230.125 0.52 1230.385 4.5 ; + RECT 1231.045 0.165 1231.815 0.425 ; + RECT 1231.045 0.165 1231.305 8.825 ; + RECT 1231.555 0.165 1231.815 8.825 ; + RECT 1230.425 617.545 1230.625 618.275 ; + RECT 1230.925 617.545 1231.125 618.275 ; + RECT 1231.42 617.545 1231.62 618.275 ; + RECT 1232.065 0.3 1232.325 4.63 ; + RECT 1232.24 617.545 1232.44 618.275 ; + RECT 1232.575 0.3 1232.835 4.63 ; + RECT 1232.735 617.545 1232.935 618.275 ; + RECT 1233.235 617.545 1233.435 618.275 ; + RECT 1233.735 617.545 1233.935 618.275 ; + RECT 1234.23 617.545 1234.43 618.275 ; + RECT 1235.05 617.545 1235.25 618.275 ; + RECT 1235.545 617.545 1235.745 618.275 ; + RECT 1236.045 617.545 1236.245 618.275 ; + RECT 1236.545 617.545 1236.745 618.275 ; + RECT 1237.04 617.545 1237.24 618.275 ; + RECT 1237.86 617.545 1238.06 618.275 ; + RECT 1238.795 0.17 1239.565 0.43 ; + RECT 1238.795 0.17 1239.055 8.7 ; + RECT 1239.305 0.17 1239.565 16.7 ; + RECT 1238.355 617.545 1238.555 618.275 ; + RECT 1238.855 617.545 1239.055 618.275 ; + RECT 1239.355 617.545 1239.555 618.275 ; + RECT 1239.85 617.545 1240.05 618.275 ; + RECT 1239.815 0.3 1240.075 4.63 ; + RECT 1240.835 0.17 1241.605 0.43 ; + RECT 1240.835 0.17 1241.095 8.7 ; + RECT 1241.345 0.17 1241.605 16.7 ; + RECT 1240.325 0.3 1240.585 4.63 ; + RECT 1240.67 617.545 1240.87 618.275 ; + RECT 1241.165 617.545 1241.365 618.275 ; + RECT 1241.665 617.545 1241.865 618.275 ; + RECT 1242.165 617.545 1242.365 618.275 ; + RECT 1242.66 617.545 1242.86 618.275 ; + RECT 1243.48 617.545 1243.68 618.275 ; + RECT 1244.405 0.17 1245.175 0.43 ; + RECT 1244.405 0.17 1244.665 11.38 ; + RECT 1244.915 0.17 1245.175 16.7 ; + RECT 1243.975 617.545 1244.175 618.275 ; + RECT 1244.475 617.545 1244.675 618.275 ; + RECT 1244.975 617.545 1245.175 618.275 ; + RECT 1245.47 617.545 1245.67 618.275 ; + RECT 1246.29 617.545 1246.49 618.275 ; + RECT 1246.785 617.545 1246.985 618.275 ; + RECT 1247.285 617.545 1247.485 618.275 ; + RECT 1247.785 617.545 1247.985 618.275 ; + RECT 1248.28 617.545 1248.48 618.275 ; + RECT 1249.1 617.545 1249.3 618.275 ; + RECT 1249.075 0.3 1249.335 8.23 ; + RECT 1249.595 617.545 1249.795 618.275 ; + RECT 1250.095 0.165 1250.865 0.425 ; + RECT 1250.095 0.165 1250.355 8.825 ; + RECT 1250.605 0.165 1250.865 8.825 ; + RECT 1249.585 0.3 1249.845 4.63 ; + RECT 1250.095 617.545 1250.295 618.275 ; + RECT 1250.595 617.545 1250.795 618.275 ; + RECT 1251.09 617.545 1251.29 618.275 ; + RECT 1251.91 617.545 1252.11 618.275 ; + RECT 1252.405 617.545 1252.605 618.275 ; + RECT 1252.905 617.545 1253.105 618.275 ; + RECT 1253.31 0.52 1253.57 4.5 ; + RECT 1253.405 617.545 1253.605 618.275 ; + RECT 1253.9 617.545 1254.1 618.275 ; + RECT 1254.72 617.545 1254.92 618.275 ; + RECT 1255.215 617.545 1255.415 618.275 ; + RECT 1255.25 0.3 1255.51 4.63 ; + RECT 1255.715 617.545 1255.915 618.275 ; + RECT 1256.27 0.16 1257.04 0.42 ; + RECT 1256.27 0.16 1256.53 8.82 ; + RECT 1256.78 0.16 1257.04 8.82 ; + RECT 1255.76 0.3 1256.02 4.63 ; + RECT 1256.215 617.545 1256.415 618.275 ; + RECT 1256.71 617.545 1256.91 618.275 ; + RECT 1257.53 617.545 1257.73 618.275 ; + RECT 1258.025 617.545 1258.225 618.275 ; + RECT 1258.525 617.545 1258.725 618.275 ; + RECT 1259.025 617.545 1259.225 618.275 ; + RECT 1259.52 617.545 1259.72 618.275 ; + RECT 1259.785 0.3 1260.045 4.63 ; + RECT 1260.34 617.545 1260.54 618.275 ; + RECT 1260.805 0.16 1261.575 0.42 ; + RECT 1260.805 0.16 1261.065 4.63 ; + RECT 1261.315 0.16 1261.575 8.82 ; + RECT 1260.295 0.3 1260.555 4.63 ; + RECT 1260.835 617.545 1261.035 618.275 ; + RECT 1261.335 617.545 1261.535 618.275 ; + RECT 1261.835 617.545 1262.035 618.275 ; + RECT 1262.33 617.545 1262.53 618.275 ; + RECT 1263.15 617.545 1263.35 618.275 ; + RECT 1263.645 617.545 1263.845 618.275 ; + RECT 1264.145 617.545 1264.345 618.275 ; + RECT 1264.645 617.545 1264.845 618.275 ; + RECT 1265.14 617.545 1265.34 618.275 ; + RECT 1265.96 617.545 1266.16 618.275 ; + RECT 1266.455 617.545 1266.655 618.275 ; + RECT 1266.955 617.545 1267.155 618.275 ; + RECT 1267.455 617.545 1267.655 618.275 ; + RECT 1267.95 617.545 1268.15 618.275 ; + RECT 1268.77 617.545 1268.97 618.275 ; + RECT 1269.265 617.545 1269.465 618.275 ; + RECT 1269.765 617.545 1269.965 618.275 ; + RECT 1270.265 617.545 1270.465 618.275 ; + RECT 1270.76 617.545 1270.96 618.275 ; + RECT 1271.58 617.545 1271.78 618.275 ; + RECT 1272.075 617.545 1272.275 618.275 ; + RECT 1272.575 617.545 1272.775 618.275 ; + RECT 1273.075 617.545 1273.275 618.275 ; + RECT 1273.57 617.545 1273.77 618.275 ; + RECT 1274.39 617.545 1274.59 618.275 ; + RECT 1274.885 617.545 1275.085 618.275 ; + RECT 1275.085 0.52 1275.345 4.5 ; + RECT 1276.005 0.165 1276.775 0.425 ; + RECT 1276.005 0.165 1276.265 8.825 ; + RECT 1276.515 0.165 1276.775 8.825 ; + RECT 1275.385 617.545 1275.585 618.275 ; + RECT 1275.885 617.545 1276.085 618.275 ; + RECT 1276.38 617.545 1276.58 618.275 ; + RECT 1277.025 0.3 1277.285 4.63 ; + RECT 1277.2 617.545 1277.4 618.275 ; + RECT 1277.535 0.3 1277.795 4.63 ; + RECT 1277.695 617.545 1277.895 618.275 ; + RECT 1278.195 617.545 1278.395 618.275 ; + RECT 1278.695 617.545 1278.895 618.275 ; + RECT 1279.19 617.545 1279.39 618.275 ; + RECT 1280.01 617.545 1280.21 618.275 ; + RECT 1280.505 617.545 1280.705 618.275 ; + RECT 1281.005 617.545 1281.205 618.275 ; + RECT 1281.505 617.545 1281.705 618.275 ; + RECT 1282 617.545 1282.2 618.275 ; + RECT 1282.82 617.545 1283.02 618.275 ; + RECT 1283.755 0.17 1284.525 0.43 ; + RECT 1283.755 0.17 1284.015 8.7 ; + RECT 1284.265 0.17 1284.525 16.7 ; + RECT 1283.315 617.545 1283.515 618.275 ; + RECT 1283.815 617.545 1284.015 618.275 ; + RECT 1284.315 617.545 1284.515 618.275 ; + RECT 1284.81 617.545 1285.01 618.275 ; + RECT 1284.775 0.3 1285.035 4.63 ; + RECT 1285.795 0.17 1286.565 0.43 ; + RECT 1285.795 0.17 1286.055 8.7 ; + RECT 1286.305 0.17 1286.565 16.7 ; + RECT 1285.285 0.3 1285.545 4.63 ; + RECT 1285.63 617.545 1285.83 618.275 ; + RECT 1286.125 617.545 1286.325 618.275 ; + RECT 1286.625 617.545 1286.825 618.275 ; + RECT 1287.125 617.545 1287.325 618.275 ; + RECT 1287.62 617.545 1287.82 618.275 ; + RECT 1288.44 617.545 1288.64 618.275 ; + RECT 1289.365 0.17 1290.135 0.43 ; + RECT 1289.365 0.17 1289.625 11.38 ; + RECT 1289.875 0.17 1290.135 16.7 ; + RECT 1288.935 617.545 1289.135 618.275 ; + RECT 1289.435 617.545 1289.635 618.275 ; + RECT 1289.935 617.545 1290.135 618.275 ; + RECT 1290.43 617.545 1290.63 618.275 ; + RECT 1291.25 617.545 1291.45 618.275 ; + RECT 1291.745 617.545 1291.945 618.275 ; + RECT 1292.245 617.545 1292.445 618.275 ; + RECT 1292.745 617.545 1292.945 618.275 ; + RECT 1293.24 617.545 1293.44 618.275 ; + RECT 1294.06 617.545 1294.26 618.275 ; + RECT 1294.035 0.3 1294.295 8.23 ; + RECT 1294.555 617.545 1294.755 618.275 ; + RECT 1295.055 0.165 1295.825 0.425 ; + RECT 1295.055 0.165 1295.315 8.825 ; + RECT 1295.565 0.165 1295.825 8.825 ; + RECT 1294.545 0.3 1294.805 4.63 ; + RECT 1295.055 617.545 1295.255 618.275 ; + RECT 1295.555 617.545 1295.755 618.275 ; + RECT 1296.05 617.545 1296.25 618.275 ; + RECT 1296.87 617.545 1297.07 618.275 ; + RECT 1297.365 617.545 1297.565 618.275 ; + RECT 1297.865 617.545 1298.065 618.275 ; + RECT 1298.27 0.52 1298.53 4.5 ; + RECT 1298.365 617.545 1298.565 618.275 ; + RECT 1298.86 617.545 1299.06 618.275 ; + RECT 1299.68 617.545 1299.88 618.275 ; + RECT 1300.175 617.545 1300.375 618.275 ; + RECT 1300.21 0.3 1300.47 4.63 ; + RECT 1300.675 617.545 1300.875 618.275 ; + RECT 1301.23 0.16 1302 0.42 ; + RECT 1301.23 0.16 1301.49 8.82 ; + RECT 1301.74 0.16 1302 8.82 ; + RECT 1300.72 0.3 1300.98 4.63 ; + RECT 1301.175 617.545 1301.375 618.275 ; + RECT 1301.67 617.545 1301.87 618.275 ; + RECT 1302.49 617.545 1302.69 618.275 ; + RECT 1302.985 617.545 1303.185 618.275 ; + RECT 1303.485 617.545 1303.685 618.275 ; + RECT 1303.985 617.545 1304.185 618.275 ; + RECT 1304.48 617.545 1304.68 618.275 ; + RECT 1304.745 0.3 1305.005 4.63 ; + RECT 1305.3 617.545 1305.5 618.275 ; + RECT 1305.765 0.16 1306.535 0.42 ; + RECT 1305.765 0.16 1306.025 4.63 ; + RECT 1306.275 0.16 1306.535 8.82 ; + RECT 1305.255 0.3 1305.515 4.63 ; + RECT 1305.795 617.545 1305.995 618.275 ; + RECT 1306.295 617.545 1306.495 618.275 ; + RECT 1306.795 617.545 1306.995 618.275 ; + RECT 1307.29 617.545 1307.49 618.275 ; + RECT 1308.11 617.545 1308.31 618.275 ; + RECT 1308.605 617.545 1308.805 618.275 ; + RECT 1309.105 617.545 1309.305 618.275 ; + RECT 1309.605 617.545 1309.805 618.275 ; + RECT 1310.1 617.545 1310.3 618.275 ; + RECT 1310.92 617.545 1311.12 618.275 ; + RECT 1311.415 617.545 1311.615 618.275 ; + RECT 1311.915 617.545 1312.115 618.275 ; + RECT 1312.415 617.545 1312.615 618.275 ; + RECT 1312.91 617.545 1313.11 618.275 ; + RECT 1313.73 617.545 1313.93 618.275 ; + RECT 1314.225 617.545 1314.425 618.275 ; + RECT 1314.725 617.545 1314.925 618.275 ; + RECT 1315.225 617.545 1315.425 618.275 ; + RECT 1315.72 617.545 1315.92 618.275 ; + RECT 1316.54 617.545 1316.74 618.275 ; + RECT 1317.035 617.545 1317.235 618.275 ; + RECT 1317.535 617.545 1317.735 618.275 ; + RECT 1318.035 617.545 1318.235 618.275 ; + RECT 1318.53 617.545 1318.73 618.275 ; + RECT 1319.35 617.545 1319.55 618.275 ; + RECT 1319.845 617.545 1320.045 618.275 ; + RECT 1320.045 0.52 1320.305 4.5 ; + RECT 1320.965 0.165 1321.735 0.425 ; + RECT 1320.965 0.165 1321.225 8.825 ; + RECT 1321.475 0.165 1321.735 8.825 ; + RECT 1320.345 617.545 1320.545 618.275 ; + RECT 1320.845 617.545 1321.045 618.275 ; + RECT 1321.34 617.545 1321.54 618.275 ; + RECT 1321.985 0.3 1322.245 4.63 ; + RECT 1322.16 617.545 1322.36 618.275 ; + RECT 1322.495 0.3 1322.755 4.63 ; + RECT 1322.655 617.545 1322.855 618.275 ; + RECT 1323.155 617.545 1323.355 618.275 ; + RECT 1323.655 617.545 1323.855 618.275 ; + RECT 1324.15 617.545 1324.35 618.275 ; + RECT 1324.97 617.545 1325.17 618.275 ; + RECT 1325.465 617.545 1325.665 618.275 ; + RECT 1325.965 617.545 1326.165 618.275 ; + RECT 1326.465 617.545 1326.665 618.275 ; + RECT 1326.96 617.545 1327.16 618.275 ; + RECT 1327.78 617.545 1327.98 618.275 ; + RECT 1328.715 0.17 1329.485 0.43 ; + RECT 1328.715 0.17 1328.975 8.7 ; + RECT 1329.225 0.17 1329.485 16.7 ; + RECT 1328.275 617.545 1328.475 618.275 ; + RECT 1328.775 617.545 1328.975 618.275 ; + RECT 1329.275 617.545 1329.475 618.275 ; + RECT 1329.77 617.545 1329.97 618.275 ; + RECT 1329.735 0.3 1329.995 4.63 ; + RECT 1330.755 0.17 1331.525 0.43 ; + RECT 1330.755 0.17 1331.015 8.7 ; + RECT 1331.265 0.17 1331.525 16.7 ; + RECT 1330.245 0.3 1330.505 4.63 ; + RECT 1330.59 617.545 1330.79 618.275 ; + RECT 1331.085 617.545 1331.285 618.275 ; + RECT 1331.585 617.545 1331.785 618.275 ; + RECT 1332.085 617.545 1332.285 618.275 ; + RECT 1332.58 617.545 1332.78 618.275 ; + RECT 1333.4 617.545 1333.6 618.275 ; + RECT 1334.325 0.17 1335.095 0.43 ; + RECT 1334.325 0.17 1334.585 11.38 ; + RECT 1334.835 0.17 1335.095 16.7 ; + RECT 1333.895 617.545 1334.095 618.275 ; + RECT 1334.395 617.545 1334.595 618.275 ; + RECT 1334.895 617.545 1335.095 618.275 ; + RECT 1335.39 617.545 1335.59 618.275 ; + RECT 1336.21 617.545 1336.41 618.275 ; + RECT 1336.705 617.545 1336.905 618.275 ; + RECT 1337.205 617.545 1337.405 618.275 ; + RECT 1337.705 617.545 1337.905 618.275 ; + RECT 1338.2 617.545 1338.4 618.275 ; + RECT 1339.02 617.545 1339.22 618.275 ; + RECT 1338.995 0.3 1339.255 8.23 ; + RECT 1339.515 617.545 1339.715 618.275 ; + RECT 1340.015 0.165 1340.785 0.425 ; + RECT 1340.015 0.165 1340.275 8.825 ; + RECT 1340.525 0.165 1340.785 8.825 ; + RECT 1339.505 0.3 1339.765 4.63 ; + RECT 1340.015 617.545 1340.215 618.275 ; + RECT 1340.515 617.545 1340.715 618.275 ; + RECT 1341.01 617.545 1341.21 618.275 ; + RECT 1341.83 617.545 1342.03 618.275 ; + RECT 1342.325 617.545 1342.525 618.275 ; + RECT 1342.825 617.545 1343.025 618.275 ; + RECT 1343.23 0.52 1343.49 4.5 ; + RECT 1343.325 617.545 1343.525 618.275 ; + RECT 1343.82 617.545 1344.02 618.275 ; + RECT 1344.64 617.545 1344.84 618.275 ; + RECT 1345.135 617.545 1345.335 618.275 ; + RECT 1345.17 0.3 1345.43 4.63 ; + RECT 1345.635 617.545 1345.835 618.275 ; + RECT 1346.19 0.16 1346.96 0.42 ; + RECT 1346.19 0.16 1346.45 8.82 ; + RECT 1346.7 0.16 1346.96 8.82 ; + RECT 1345.68 0.3 1345.94 4.63 ; + RECT 1346.135 617.545 1346.335 618.275 ; + RECT 1346.63 617.545 1346.83 618.275 ; + RECT 1347.45 617.545 1347.65 618.275 ; + RECT 1347.945 617.545 1348.145 618.275 ; + RECT 1348.445 617.545 1348.645 618.275 ; + RECT 1348.945 617.545 1349.145 618.275 ; + RECT 1349.44 617.545 1349.64 618.275 ; + RECT 1349.705 0.3 1349.965 4.63 ; + RECT 1350.26 617.545 1350.46 618.275 ; + RECT 1350.725 0.16 1351.495 0.42 ; + RECT 1350.725 0.16 1350.985 4.63 ; + RECT 1351.235 0.16 1351.495 8.82 ; + RECT 1350.215 0.3 1350.475 4.63 ; + RECT 1350.755 617.545 1350.955 618.275 ; + RECT 1351.255 617.545 1351.455 618.275 ; + RECT 1351.755 617.545 1351.955 618.275 ; + RECT 1352.25 617.545 1352.45 618.275 ; + RECT 1353.07 617.545 1353.27 618.275 ; + RECT 1353.565 617.545 1353.765 618.275 ; + RECT 1354.065 617.545 1354.265 618.275 ; + RECT 1354.565 617.545 1354.765 618.275 ; + RECT 1355.06 617.545 1355.26 618.275 ; + RECT 1355.88 617.545 1356.08 618.275 ; + RECT 1356.375 617.545 1356.575 618.275 ; + RECT 1356.875 617.545 1357.075 618.275 ; + RECT 1357.375 617.545 1357.575 618.275 ; + RECT 1357.87 617.545 1358.07 618.275 ; + RECT 1358.69 617.545 1358.89 618.275 ; + RECT 1359.185 617.545 1359.385 618.275 ; + RECT 1359.685 617.545 1359.885 618.275 ; + RECT 1360.185 617.545 1360.385 618.275 ; + RECT 1360.68 617.545 1360.88 618.275 ; + RECT 1361.5 617.545 1361.7 618.275 ; + RECT 1361.995 617.545 1362.195 618.275 ; + RECT 1362.495 617.545 1362.695 618.275 ; + RECT 1362.995 617.545 1363.195 618.275 ; + RECT 1363.49 617.545 1363.69 618.275 ; + RECT 1364.31 617.545 1364.51 618.275 ; + RECT 1364.805 617.545 1365.005 618.275 ; + RECT 1365.005 0.52 1365.265 4.5 ; + RECT 1365.925 0.165 1366.695 0.425 ; + RECT 1365.925 0.165 1366.185 8.825 ; + RECT 1366.435 0.165 1366.695 8.825 ; + RECT 1365.305 617.545 1365.505 618.275 ; + RECT 1365.805 617.545 1366.005 618.275 ; + RECT 1366.3 617.545 1366.5 618.275 ; + RECT 1366.945 0.3 1367.205 4.63 ; + RECT 1367.12 617.545 1367.32 618.275 ; + RECT 1367.455 0.3 1367.715 4.63 ; + RECT 1367.615 617.545 1367.815 618.275 ; + RECT 1368.115 617.545 1368.315 618.275 ; + RECT 1368.615 617.545 1368.815 618.275 ; + RECT 1369.11 617.545 1369.31 618.275 ; + RECT 1369.93 617.545 1370.13 618.275 ; + RECT 1370.425 617.545 1370.625 618.275 ; + RECT 1370.925 617.545 1371.125 618.275 ; + RECT 1371.425 617.545 1371.625 618.275 ; + RECT 1371.92 617.545 1372.12 618.275 ; + RECT 1372.74 617.545 1372.94 618.275 ; + RECT 1373.675 0.17 1374.445 0.43 ; + RECT 1373.675 0.17 1373.935 8.7 ; + RECT 1374.185 0.17 1374.445 16.7 ; + RECT 1373.235 617.545 1373.435 618.275 ; + RECT 1373.735 617.545 1373.935 618.275 ; + RECT 1374.235 617.545 1374.435 618.275 ; + RECT 1374.73 617.545 1374.93 618.275 ; + RECT 1374.695 0.3 1374.955 4.63 ; + RECT 1375.715 0.17 1376.485 0.43 ; + RECT 1375.715 0.17 1375.975 8.7 ; + RECT 1376.225 0.17 1376.485 16.7 ; + RECT 1375.205 0.3 1375.465 4.63 ; + RECT 1375.55 617.545 1375.75 618.275 ; + RECT 1376.045 617.545 1376.245 618.275 ; + RECT 1376.545 617.545 1376.745 618.275 ; + RECT 1377.045 617.545 1377.245 618.275 ; + RECT 1377.54 617.545 1377.74 618.275 ; + RECT 1378.36 617.545 1378.56 618.275 ; + RECT 1379.285 0.17 1380.055 0.43 ; + RECT 1379.285 0.17 1379.545 11.38 ; + RECT 1379.795 0.17 1380.055 16.7 ; + RECT 1378.855 617.545 1379.055 618.275 ; + RECT 1379.355 617.545 1379.555 618.275 ; + RECT 1379.855 617.545 1380.055 618.275 ; + RECT 1380.35 617.545 1380.55 618.275 ; + RECT 1381.17 617.545 1381.37 618.275 ; + RECT 1381.665 617.545 1381.865 618.275 ; + RECT 1382.165 617.545 1382.365 618.275 ; + RECT 1382.665 617.545 1382.865 618.275 ; + RECT 1383.16 617.545 1383.36 618.275 ; + RECT 1383.98 617.545 1384.18 618.275 ; + RECT 1383.955 0.3 1384.215 8.23 ; + RECT 1384.475 617.545 1384.675 618.275 ; + RECT 1384.975 0.165 1385.745 0.425 ; + RECT 1384.975 0.165 1385.235 8.825 ; + RECT 1385.485 0.165 1385.745 8.825 ; + RECT 1384.465 0.3 1384.725 4.63 ; + RECT 1384.975 617.545 1385.175 618.275 ; + RECT 1385.475 617.545 1385.675 618.275 ; + RECT 1385.97 617.545 1386.17 618.275 ; + RECT 1386.79 617.545 1386.99 618.275 ; + RECT 1387.285 617.545 1387.485 618.275 ; + RECT 1387.785 617.545 1387.985 618.275 ; + RECT 1388.19 0.52 1388.45 4.5 ; + RECT 1388.285 617.545 1388.485 618.275 ; + RECT 1388.78 617.545 1388.98 618.275 ; + RECT 1389.6 617.545 1389.8 618.275 ; + RECT 1390.095 617.545 1390.295 618.275 ; + RECT 1390.13 0.3 1390.39 4.63 ; + RECT 1390.595 617.545 1390.795 618.275 ; + RECT 1391.15 0.16 1391.92 0.42 ; + RECT 1391.15 0.16 1391.41 8.82 ; + RECT 1391.66 0.16 1391.92 8.82 ; + RECT 1390.64 0.3 1390.9 4.63 ; + RECT 1391.095 617.545 1391.295 618.275 ; + RECT 1391.59 617.545 1391.79 618.275 ; + RECT 1392.41 617.545 1392.61 618.275 ; + RECT 1392.905 617.545 1393.105 618.275 ; + RECT 1393.405 617.545 1393.605 618.275 ; + RECT 1393.905 617.545 1394.105 618.275 ; + RECT 1394.4 617.545 1394.6 618.275 ; + RECT 1394.665 0.3 1394.925 4.63 ; + RECT 1395.22 617.545 1395.42 618.275 ; + RECT 1395.685 0.16 1396.455 0.42 ; + RECT 1395.685 0.16 1395.945 4.63 ; + RECT 1396.195 0.16 1396.455 8.82 ; + RECT 1395.175 0.3 1395.435 4.63 ; + RECT 1395.715 617.545 1395.915 618.275 ; + RECT 1396.215 617.545 1396.415 618.275 ; + RECT 1396.715 617.545 1396.915 618.275 ; + RECT 1397.21 617.545 1397.41 618.275 ; + RECT 1398.03 617.545 1398.23 618.275 ; + RECT 1398.525 617.545 1398.725 618.275 ; + RECT 1399.025 617.545 1399.225 618.275 ; + RECT 1399.525 617.545 1399.725 618.275 ; + RECT 1400.02 617.545 1400.22 618.275 ; + RECT 1400.84 617.545 1401.04 618.275 ; + RECT 1401.335 617.545 1401.535 618.275 ; + RECT 1401.835 617.545 1402.035 618.275 ; + RECT 1402.335 617.545 1402.535 618.275 ; + RECT 1402.83 617.545 1403.03 618.275 ; + RECT 1403.65 617.545 1403.85 618.275 ; + RECT 1404.145 617.545 1404.345 618.275 ; + RECT 1404.645 617.545 1404.845 618.275 ; + RECT 1405.145 617.545 1405.345 618.275 ; + RECT 1405.64 617.545 1405.84 618.275 ; + RECT 1406.46 617.545 1406.66 618.275 ; + RECT 1406.955 617.545 1407.155 618.275 ; + RECT 1407.455 617.545 1407.655 618.275 ; + RECT 1407.955 617.545 1408.155 618.275 ; + RECT 1408.45 617.545 1408.65 618.275 ; + RECT 1409.27 617.545 1409.47 618.275 ; + RECT 1409.765 617.545 1409.965 618.275 ; + RECT 1409.965 0.52 1410.225 4.5 ; + RECT 1410.885 0.165 1411.655 0.425 ; + RECT 1410.885 0.165 1411.145 8.825 ; + RECT 1411.395 0.165 1411.655 8.825 ; + RECT 1410.265 617.545 1410.465 618.275 ; + RECT 1410.765 617.545 1410.965 618.275 ; + RECT 1411.26 617.545 1411.46 618.275 ; + RECT 1411.905 0.3 1412.165 4.63 ; + RECT 1412.08 617.545 1412.28 618.275 ; + RECT 1412.415 0.3 1412.675 4.63 ; + RECT 1412.575 617.545 1412.775 618.275 ; + RECT 1413.075 617.545 1413.275 618.275 ; + RECT 1413.575 617.545 1413.775 618.275 ; + RECT 1414.07 617.545 1414.27 618.275 ; + RECT 1414.89 617.545 1415.09 618.275 ; + RECT 1415.385 617.545 1415.585 618.275 ; + RECT 1415.885 617.545 1416.085 618.275 ; + RECT 1416.385 617.545 1416.585 618.275 ; + RECT 1416.88 617.545 1417.08 618.275 ; + RECT 1417.7 617.545 1417.9 618.275 ; + RECT 1418.635 0.17 1419.405 0.43 ; + RECT 1418.635 0.17 1418.895 8.7 ; + RECT 1419.145 0.17 1419.405 16.7 ; + RECT 1418.195 617.545 1418.395 618.275 ; + RECT 1418.695 617.545 1418.895 618.275 ; + RECT 1419.195 617.545 1419.395 618.275 ; + RECT 1419.69 617.545 1419.89 618.275 ; + RECT 1419.655 0.3 1419.915 4.63 ; + RECT 1420.675 0.17 1421.445 0.43 ; + RECT 1420.675 0.17 1420.935 8.7 ; + RECT 1421.185 0.17 1421.445 16.7 ; + RECT 1420.165 0.3 1420.425 4.63 ; + RECT 1420.51 617.545 1420.71 618.275 ; + RECT 1421.005 617.545 1421.205 618.275 ; + RECT 1421.505 617.545 1421.705 618.275 ; + RECT 1422.005 617.545 1422.205 618.275 ; + RECT 1422.5 617.545 1422.7 618.275 ; + RECT 1423.32 617.545 1423.52 618.275 ; + RECT 1424.245 0.17 1425.015 0.43 ; + RECT 1424.245 0.17 1424.505 11.38 ; + RECT 1424.755 0.17 1425.015 16.7 ; + RECT 1423.815 617.545 1424.015 618.275 ; + RECT 1424.315 617.545 1424.515 618.275 ; + RECT 1424.815 617.545 1425.015 618.275 ; + RECT 1425.31 617.545 1425.51 618.275 ; + RECT 1426.13 617.545 1426.33 618.275 ; + RECT 1426.625 617.545 1426.825 618.275 ; + RECT 1427.125 617.545 1427.325 618.275 ; + RECT 1427.625 617.545 1427.825 618.275 ; + RECT 1428.12 617.545 1428.32 618.275 ; + RECT 1428.94 617.545 1429.14 618.275 ; + RECT 1428.915 0.3 1429.175 8.23 ; + RECT 1429.435 617.545 1429.635 618.275 ; + RECT 1429.935 0.165 1430.705 0.425 ; + RECT 1429.935 0.165 1430.195 8.825 ; + RECT 1430.445 0.165 1430.705 8.825 ; + RECT 1429.425 0.3 1429.685 4.63 ; + RECT 1429.935 617.545 1430.135 618.275 ; + RECT 1430.435 617.545 1430.635 618.275 ; + RECT 1430.93 617.545 1431.13 618.275 ; + RECT 1431.75 617.545 1431.95 618.275 ; + RECT 1432.245 617.545 1432.445 618.275 ; + RECT 1432.745 617.545 1432.945 618.275 ; + RECT 1433.15 0.52 1433.41 4.5 ; + RECT 1433.245 617.545 1433.445 618.275 ; + RECT 1433.74 617.545 1433.94 618.275 ; + RECT 1434.56 617.545 1434.76 618.275 ; + RECT 1435.055 617.545 1435.255 618.275 ; + RECT 1435.09 0.3 1435.35 4.63 ; + RECT 1435.555 617.545 1435.755 618.275 ; + RECT 1436.11 0.16 1436.88 0.42 ; + RECT 1436.11 0.16 1436.37 8.82 ; + RECT 1436.62 0.16 1436.88 8.82 ; + RECT 1435.6 0.3 1435.86 4.63 ; + RECT 1436.055 617.545 1436.255 618.275 ; + RECT 1436.55 617.545 1436.75 618.275 ; + RECT 1437.37 617.545 1437.57 618.275 ; + RECT 1437.865 617.545 1438.065 618.275 ; + RECT 1438.365 617.545 1438.565 618.275 ; + RECT 1438.865 617.545 1439.065 618.275 ; + RECT 1439.36 617.545 1439.56 618.275 ; + RECT 1439.625 0.3 1439.885 4.63 ; + RECT 1440.18 617.545 1440.38 618.275 ; + RECT 1440.645 0.16 1441.415 0.42 ; + RECT 1440.645 0.16 1440.905 4.63 ; + RECT 1441.155 0.16 1441.415 8.82 ; + RECT 1440.135 0.3 1440.395 4.63 ; + RECT 1440.675 617.545 1440.875 618.275 ; + RECT 1441.175 617.545 1441.375 618.275 ; + RECT 1441.675 617.545 1441.875 618.275 ; + RECT 1442.17 617.545 1442.37 618.275 ; + RECT 1442.99 617.545 1443.19 618.275 ; + RECT 1443.485 617.545 1443.685 618.275 ; + RECT 1443.985 617.545 1444.185 618.275 ; + RECT 1444.485 617.545 1444.685 618.275 ; + RECT 1444.98 617.545 1445.18 618.275 ; + RECT 1445.8 617.545 1446 618.275 ; + RECT 1446.295 617.545 1446.495 618.275 ; + RECT 1446.795 617.545 1446.995 618.275 ; + RECT 1447.295 617.545 1447.495 618.275 ; + RECT 1447.79 617.545 1447.99 618.275 ; + RECT 1448.61 617.545 1448.81 618.275 ; + RECT 1449.105 617.545 1449.305 618.275 ; + RECT 1449.605 617.545 1449.805 618.275 ; + RECT 1450.105 617.545 1450.305 618.275 ; + RECT 1450.6 617.545 1450.8 618.275 ; + RECT 1451.42 617.545 1451.62 618.275 ; + RECT 1451.915 617.545 1452.115 618.275 ; + RECT 1452.415 617.545 1452.615 618.275 ; + RECT 1452.915 617.545 1453.115 618.275 ; + RECT 1453.41 617.545 1453.61 618.275 ; + RECT 1454.23 617.545 1454.43 618.275 ; + RECT 1454.725 617.545 1454.925 618.275 ; + RECT 1454.925 0.52 1455.185 4.5 ; + RECT 1455.845 0.165 1456.615 0.425 ; + RECT 1455.845 0.165 1456.105 8.825 ; + RECT 1456.355 0.165 1456.615 8.825 ; + RECT 1455.225 617.545 1455.425 618.275 ; + RECT 1455.725 617.545 1455.925 618.275 ; + RECT 1456.22 617.545 1456.42 618.275 ; + RECT 1456.865 0.3 1457.125 4.63 ; + RECT 1457.04 617.545 1457.24 618.275 ; + RECT 1457.375 0.3 1457.635 4.63 ; + RECT 1457.535 617.545 1457.735 618.275 ; + RECT 1458.035 617.545 1458.235 618.275 ; + RECT 1458.535 617.545 1458.735 618.275 ; + RECT 1459.03 617.545 1459.23 618.275 ; + RECT 1459.85 617.545 1460.05 618.275 ; + RECT 1460.345 617.545 1460.545 618.275 ; + RECT 1460.845 617.545 1461.045 618.275 ; + RECT 1461.345 617.545 1461.545 618.275 ; + RECT 1461.84 617.545 1462.04 618.275 ; + RECT 1462.66 617.545 1462.86 618.275 ; + RECT 1463.595 0.17 1464.365 0.43 ; + RECT 1463.595 0.17 1463.855 8.7 ; + RECT 1464.105 0.17 1464.365 16.7 ; + RECT 1463.155 617.545 1463.355 618.275 ; + RECT 1463.655 617.545 1463.855 618.275 ; + RECT 1464.155 617.545 1464.355 618.275 ; + RECT 1464.65 617.545 1464.85 618.275 ; + RECT 1464.615 0.3 1464.875 4.63 ; + RECT 1465.635 0.17 1466.405 0.43 ; + RECT 1465.635 0.17 1465.895 8.7 ; + RECT 1466.145 0.17 1466.405 16.7 ; + RECT 1465.125 0.3 1465.385 4.63 ; + RECT 1465.47 617.545 1465.67 618.275 ; + RECT 1465.965 617.545 1466.165 618.275 ; + RECT 1466.465 617.545 1466.665 618.275 ; + RECT 1466.965 617.545 1467.165 618.275 ; + RECT 1467.46 617.545 1467.66 618.275 ; + RECT 1468.28 617.545 1468.48 618.275 ; + RECT 1469.205 0.17 1469.975 0.43 ; + RECT 1469.205 0.17 1469.465 11.38 ; + RECT 1469.715 0.17 1469.975 16.7 ; + RECT 1468.775 617.545 1468.975 618.275 ; + RECT 1469.275 617.545 1469.475 618.275 ; + RECT 1469.775 617.545 1469.975 618.275 ; + RECT 1470.27 617.545 1470.47 618.275 ; + RECT 1471.09 617.545 1471.29 618.275 ; + RECT 1471.585 617.545 1471.785 618.275 ; + RECT 1472.085 617.545 1472.285 618.275 ; + RECT 1472.585 617.545 1472.785 618.275 ; + RECT 1473.08 617.545 1473.28 618.275 ; + RECT 1473.9 617.545 1474.1 618.275 ; + RECT 1473.875 0.3 1474.135 8.23 ; + RECT 1474.395 617.545 1474.595 618.275 ; + RECT 1474.895 0.165 1475.665 0.425 ; + RECT 1474.895 0.165 1475.155 8.825 ; + RECT 1475.405 0.165 1475.665 8.825 ; + RECT 1474.385 0.3 1474.645 4.63 ; + RECT 1474.895 617.545 1475.095 618.275 ; + RECT 1475.395 617.545 1475.595 618.275 ; + RECT 1475.89 617.545 1476.09 618.275 ; + RECT 1476.71 617.545 1476.91 618.275 ; + RECT 1477.205 617.545 1477.405 618.275 ; + RECT 1477.705 617.545 1477.905 618.275 ; + RECT 1478.11 0.52 1478.37 4.5 ; + RECT 1478.205 617.545 1478.405 618.275 ; + RECT 1478.7 617.545 1478.9 618.275 ; + RECT 1479.52 617.545 1479.72 618.275 ; + RECT 1480.015 617.545 1480.215 618.275 ; + RECT 1480.05 0.3 1480.31 4.63 ; + RECT 1480.515 617.545 1480.715 618.275 ; + RECT 1481.07 0.16 1481.84 0.42 ; + RECT 1481.07 0.16 1481.33 8.82 ; + RECT 1481.58 0.16 1481.84 8.82 ; + RECT 1480.56 0.3 1480.82 4.63 ; + RECT 1481.015 617.545 1481.215 618.275 ; + RECT 1481.51 617.545 1481.71 618.275 ; + RECT 1482.33 617.545 1482.53 618.275 ; + RECT 1482.825 617.545 1483.025 618.275 ; + RECT 1483.325 617.545 1483.525 618.275 ; + RECT 1483.825 617.545 1484.025 618.275 ; + RECT 1484.32 617.545 1484.52 618.275 ; + RECT 1484.585 0.3 1484.845 4.63 ; + RECT 1485.14 617.545 1485.34 618.275 ; + RECT 1485.605 0.16 1486.375 0.42 ; + RECT 1485.605 0.16 1485.865 4.63 ; + RECT 1486.115 0.16 1486.375 8.82 ; + RECT 1485.095 0.3 1485.355 4.63 ; + RECT 1485.635 617.545 1485.835 618.275 ; + RECT 1486.135 617.545 1486.335 618.275 ; + RECT 1486.635 617.545 1486.835 618.275 ; + RECT 1487.13 617.545 1487.33 618.275 ; + RECT 1487.95 617.545 1488.15 618.275 ; + RECT 1488.445 617.545 1488.645 618.275 ; + RECT 1488.945 617.545 1489.145 618.275 ; + RECT 1489.445 617.545 1489.645 618.275 ; + RECT 1489.94 617.545 1490.14 618.275 ; + RECT 1490.76 617.545 1490.96 618.275 ; + RECT 1491.255 617.545 1491.455 618.275 ; + RECT 1491.755 617.545 1491.955 618.275 ; + RECT 1492.255 617.545 1492.455 618.275 ; + RECT 1492.75 617.545 1492.95 618.275 ; + RECT 1493.57 617.545 1493.77 618.275 ; + RECT 1494.065 617.545 1494.265 618.275 ; + RECT 1494.565 617.545 1494.765 618.275 ; + RECT 1495.065 617.545 1495.265 618.275 ; + RECT 1495.56 617.545 1495.76 618.275 ; + RECT 1496.38 617.545 1496.58 618.275 ; + RECT 1496.875 617.545 1497.075 618.275 ; + RECT 1497.375 617.545 1497.575 618.275 ; + RECT 1497.875 617.545 1498.075 618.275 ; + RECT 1498.37 617.545 1498.57 618.275 ; + RECT 1499.19 617.545 1499.39 618.275 ; + RECT 1499.685 617.545 1499.885 618.275 ; + RECT 1499.885 0.52 1500.145 4.5 ; + RECT 1500.805 0.165 1501.575 0.425 ; + RECT 1500.805 0.165 1501.065 8.825 ; + RECT 1501.315 0.165 1501.575 8.825 ; + RECT 1500.185 617.545 1500.385 618.275 ; + RECT 1500.685 617.545 1500.885 618.275 ; + RECT 1501.18 617.545 1501.38 618.275 ; + RECT 1501.825 0.3 1502.085 4.63 ; + RECT 1502 617.545 1502.2 618.275 ; + RECT 1502.335 0.3 1502.595 4.63 ; + RECT 1502.495 617.545 1502.695 618.275 ; + RECT 1502.995 617.545 1503.195 618.275 ; + RECT 1503.495 617.545 1503.695 618.275 ; + RECT 1503.99 617.545 1504.19 618.275 ; + RECT 1504.81 617.545 1505.01 618.275 ; + RECT 1505.305 617.545 1505.505 618.275 ; + RECT 1505.805 617.545 1506.005 618.275 ; + RECT 1506.305 617.545 1506.505 618.275 ; + RECT 1506.8 617.545 1507 618.275 ; + RECT 1507.62 617.545 1507.82 618.275 ; + RECT 1508.555 0.17 1509.325 0.43 ; + RECT 1508.555 0.17 1508.815 8.7 ; + RECT 1509.065 0.17 1509.325 16.7 ; + RECT 1508.115 617.545 1508.315 618.275 ; + RECT 1508.615 617.545 1508.815 618.275 ; + RECT 1509.115 617.545 1509.315 618.275 ; + RECT 1509.61 617.545 1509.81 618.275 ; + RECT 1509.575 0.3 1509.835 4.63 ; + RECT 1510.595 0.17 1511.365 0.43 ; + RECT 1510.595 0.17 1510.855 8.7 ; + RECT 1511.105 0.17 1511.365 16.7 ; + RECT 1510.085 0.3 1510.345 4.63 ; + RECT 1510.43 617.545 1510.63 618.275 ; + RECT 1510.925 617.545 1511.125 618.275 ; + RECT 1511.425 617.545 1511.625 618.275 ; + RECT 1511.925 617.545 1512.125 618.275 ; + RECT 1512.42 617.545 1512.62 618.275 ; + RECT 1513.24 617.545 1513.44 618.275 ; + RECT 1514.165 0.17 1514.935 0.43 ; + RECT 1514.165 0.17 1514.425 11.38 ; + RECT 1514.675 0.17 1514.935 16.7 ; + RECT 1513.735 617.545 1513.935 618.275 ; + RECT 1514.235 617.545 1514.435 618.275 ; + RECT 1514.735 617.545 1514.935 618.275 ; + RECT 1515.23 617.545 1515.43 618.275 ; + RECT 1516.05 617.545 1516.25 618.275 ; + RECT 1516.545 617.545 1516.745 618.275 ; + RECT 1517.045 617.545 1517.245 618.275 ; + RECT 1517.545 617.545 1517.745 618.275 ; + RECT 1518.04 617.545 1518.24 618.275 ; + RECT 1518.86 617.545 1519.06 618.275 ; + RECT 1519.855 37.065 1520.055 618.275 ; + LAYER Metal2 SPACING 0.21 ; + RECT 0 0.52 1520.16 618.3 ; + RECT 0 0 19.755 618.3 ; + RECT 20.535 0 41.53 618.3 ; + RECT 42.31 0 64.715 618.3 ; + RECT 65.495 0 86.49 618.3 ; + RECT 87.27 0 109.675 618.3 ; + RECT 110.455 0 131.45 618.3 ; + RECT 132.23 0 154.635 618.3 ; + RECT 155.415 0 176.41 618.3 ; + RECT 177.19 0 199.595 618.3 ; + RECT 200.375 0 221.37 618.3 ; + RECT 222.15 0 244.555 618.3 ; + RECT 245.335 0 266.33 618.3 ; + RECT 267.11 0 289.515 618.3 ; + RECT 290.295 0 311.29 618.3 ; + RECT 312.07 0 334.475 618.3 ; + RECT 335.255 0 356.25 618.3 ; + RECT 357.03 0 379.435 618.3 ; + RECT 380.215 0 401.21 618.3 ; + RECT 401.99 0 424.395 618.3 ; + RECT 425.175 0 446.17 618.3 ; + RECT 446.95 0 469.355 618.3 ; + RECT 470.135 0 491.13 618.3 ; + RECT 491.91 0 514.315 618.3 ; + RECT 515.095 0 536.09 618.3 ; + RECT 536.87 0 559.275 618.3 ; + RECT 560.055 0 581.05 618.3 ; + RECT 581.83 0 604.235 618.3 ; + RECT 605.015 0 626.01 618.3 ; + RECT 626.79 0 649.195 618.3 ; + RECT 649.975 0 670.97 618.3 ; + RECT 671.75 0 694.155 618.3 ; + RECT 694.935 0 715.93 618.3 ; + RECT 716.71 0 741.24 618.3 ; + RECT 742.01 0 743.79 618.3 ; + RECT 744.55 0 744.81 618.3 ; + RECT 745.57 0 745.83 618.3 ; + RECT 746.59 0 753.98 618.3 ; + RECT 755.27 0 755.51 618.3 ; + RECT 756.79 0 757.05 618.3 ; + RECT 758.33 0 762.65 618.3 ; + RECT 763.42 0 763.68 618.3 ; + RECT 764.44 0 765.21 618.3 ; + RECT 765.97 0 766.23 618.3 ; + RECT 767.5 0 768.77 618.3 ; + RECT 769.54 0 773.87 618.3 ; + RECT 774.64 0 775.91 618.3 ; + RECT 776.69 0 803.45 618.3 ; + RECT 776.68 0.17 803.45 618.3 ; + RECT 804.23 0 825.225 618.3 ; + RECT 826.005 0 848.41 618.3 ; + RECT 849.19 0 870.185 618.3 ; + RECT 870.965 0 893.37 618.3 ; + RECT 894.15 0 915.145 618.3 ; + RECT 915.925 0 938.33 618.3 ; + RECT 939.11 0 960.105 618.3 ; + RECT 960.885 0 983.29 618.3 ; + RECT 984.07 0 1005.065 618.3 ; + RECT 1005.845 0 1028.25 618.3 ; + RECT 1029.03 0 1050.025 618.3 ; + RECT 1050.805 0 1073.21 618.3 ; + RECT 1073.99 0 1094.985 618.3 ; + RECT 1095.765 0 1118.17 618.3 ; + RECT 1118.95 0 1139.945 618.3 ; + RECT 1140.725 0 1163.13 618.3 ; + RECT 1163.91 0 1184.905 618.3 ; + RECT 1185.685 0 1208.09 618.3 ; + RECT 1208.87 0 1229.865 618.3 ; + RECT 1230.645 0 1253.05 618.3 ; + RECT 1253.83 0 1274.825 618.3 ; + RECT 1275.605 0 1298.01 618.3 ; + RECT 1298.79 0 1319.785 618.3 ; + RECT 1320.565 0 1342.97 618.3 ; + RECT 1343.75 0 1364.745 618.3 ; + RECT 1365.525 0 1387.93 618.3 ; + RECT 1388.71 0 1409.705 618.3 ; + RECT 1410.485 0 1432.89 618.3 ; + RECT 1433.67 0 1454.665 618.3 ; + RECT 1455.445 0 1477.85 618.3 ; + RECT 1478.63 0 1499.625 618.3 ; + RECT 1500.405 0 1520.16 618.3 ; + LAYER Metal3 ; + RECT 0 0 1520.16 618.3 ; + LAYER Metal4 ; + RECT 4.26 599.405 7.07 618.3 ; + RECT 4.26 0 7.07 30.425 ; + RECT 9.88 599.405 12.69 618.3 ; + RECT 9.88 0 12.69 37.065 ; + RECT 49.22 599.405 52.03 618.3 ; + RECT 49.22 0 52.03 30.425 ; + RECT 54.84 599.405 57.65 618.3 ; + RECT 54.84 0 57.65 37.065 ; + RECT 94.18 599.405 96.99 618.3 ; + RECT 94.18 0 96.99 30.425 ; + RECT 99.8 599.405 102.61 618.3 ; + RECT 99.8 0 102.61 37.065 ; + RECT 139.14 599.405 141.95 618.3 ; + RECT 139.14 0 141.95 30.425 ; + RECT 144.76 599.405 147.57 618.3 ; + RECT 144.76 0 147.57 37.065 ; + RECT 184.1 599.405 186.91 618.3 ; + RECT 184.1 0 186.91 30.425 ; + RECT 189.72 599.405 192.53 618.3 ; + RECT 189.72 0 192.53 37.065 ; + RECT 229.06 599.405 231.87 618.3 ; + RECT 229.06 0 231.87 30.425 ; + RECT 234.68 599.405 237.49 618.3 ; + RECT 234.68 0 237.49 37.065 ; + RECT 274.02 599.405 276.83 618.3 ; + RECT 274.02 0 276.83 30.425 ; + RECT 279.64 599.405 282.45 618.3 ; + RECT 279.64 0 282.45 37.065 ; + RECT 318.98 599.405 321.79 618.3 ; + RECT 318.98 0 321.79 30.425 ; + RECT 324.6 599.405 327.41 618.3 ; + RECT 324.6 0 327.41 37.065 ; + RECT 363.94 599.405 366.75 618.3 ; + RECT 363.94 0 366.75 30.425 ; + RECT 369.56 599.405 372.37 618.3 ; + RECT 369.56 0 372.37 37.065 ; + RECT 408.9 599.405 411.71 618.3 ; + RECT 408.9 0 411.71 30.425 ; + RECT 414.52 599.405 417.33 618.3 ; + RECT 414.52 0 417.33 37.065 ; + RECT 453.86 599.405 456.67 618.3 ; + RECT 453.86 0 456.67 30.425 ; + RECT 459.48 599.405 462.29 618.3 ; + RECT 459.48 0 462.29 37.065 ; + RECT 498.82 599.405 501.63 618.3 ; + RECT 498.82 0 501.63 30.425 ; + RECT 504.44 599.405 507.25 618.3 ; + RECT 504.44 0 507.25 37.065 ; + RECT 543.78 599.405 546.59 618.3 ; + RECT 543.78 0 546.59 30.425 ; + RECT 549.4 599.405 552.21 618.3 ; + RECT 549.4 0 552.21 37.065 ; + RECT 588.74 599.405 591.55 618.3 ; + RECT 588.74 0 591.55 30.425 ; + RECT 594.36 599.405 597.17 618.3 ; + RECT 594.36 0 597.17 37.065 ; + RECT 633.7 599.405 636.51 618.3 ; + RECT 633.7 0 636.51 30.425 ; + RECT 639.32 599.405 642.13 618.3 ; + RECT 639.32 0 642.13 37.065 ; + RECT 678.66 599.405 681.47 618.3 ; + RECT 678.66 0 681.47 30.425 ; + RECT 684.28 599.405 687.09 618.3 ; + RECT 684.28 0 687.09 37.065 ; + RECT 833.07 599.405 835.88 618.3 ; + RECT 833.07 0 835.88 37.065 ; + RECT 838.69 599.405 841.5 618.3 ; + RECT 838.69 0 841.5 30.425 ; + RECT 878.03 599.405 880.84 618.3 ; + RECT 878.03 0 880.84 37.065 ; + RECT 883.65 599.405 886.46 618.3 ; + RECT 883.65 0 886.46 30.425 ; + RECT 922.99 599.405 925.8 618.3 ; + RECT 922.99 0 925.8 37.065 ; + RECT 928.61 599.405 931.42 618.3 ; + RECT 928.61 0 931.42 30.425 ; + RECT 967.95 599.405 970.76 618.3 ; + RECT 967.95 0 970.76 37.065 ; + RECT 973.57 599.405 976.38 618.3 ; + RECT 973.57 0 976.38 30.425 ; + RECT 1012.91 599.405 1015.72 618.3 ; + RECT 1012.91 0 1015.72 37.065 ; + RECT 1018.53 599.405 1021.34 618.3 ; + RECT 1018.53 0 1021.34 30.425 ; + RECT 1057.87 599.405 1060.68 618.3 ; + LAYER Metal4 SPACING 0.21 ; + RECT 91.63 0 105.16 618.3 ; + RECT 108.49 0 110.78 618.3 ; + RECT 114.11 30.685 122.02 36.805 ; + RECT 114.11 0 116.4 618.3 ; + RECT 119.73 0 122.02 618.3 ; + RECT 125.35 30.685 133.26 36.805 ; + RECT 125.35 0 127.64 618.3 ; + RECT 130.97 0 133.26 618.3 ; + RECT 136.59 30.685 155.74 36.805 ; + RECT 136.59 0 150.12 618.3 ; + RECT 153.45 0 155.74 618.3 ; + RECT 159.07 30.685 166.98 36.805 ; + RECT 159.07 0 161.36 618.3 ; + RECT 164.69 0 166.98 618.3 ; + RECT 170.31 30.685 178.22 36.805 ; + RECT 170.31 0 172.6 618.3 ; + RECT 175.93 0 178.22 618.3 ; + RECT 181.55 30.685 200.7 36.805 ; + RECT 181.55 0 195.08 618.3 ; + RECT 198.41 0 200.7 618.3 ; + RECT 204.03 30.685 211.94 36.805 ; + RECT 204.03 0 206.32 618.3 ; + RECT 209.65 0 211.94 618.3 ; + RECT 215.27 30.685 223.18 36.805 ; + RECT 215.27 0 217.56 618.3 ; + RECT 220.89 0 223.18 618.3 ; + RECT 226.51 30.685 245.66 36.805 ; + RECT 226.51 0 240.04 618.3 ; + RECT 243.37 0 245.66 618.3 ; + RECT 248.99 30.685 256.9 36.805 ; + RECT 248.99 0 251.28 618.3 ; + RECT 254.61 0 256.9 618.3 ; + RECT 260.23 30.685 268.14 36.805 ; + RECT 260.23 0 262.52 618.3 ; + RECT 265.85 0 268.14 618.3 ; + RECT 271.47 30.685 290.62 36.805 ; + RECT 271.47 0 285 618.3 ; + RECT 288.33 0 290.62 618.3 ; + RECT 293.95 30.685 301.86 36.805 ; + RECT 293.95 0 296.24 618.3 ; + RECT 299.57 0 301.86 618.3 ; + RECT 305.19 30.685 313.1 36.805 ; + RECT 305.19 0 307.48 618.3 ; + RECT 310.81 0 313.1 618.3 ; + RECT 316.43 30.685 335.58 36.805 ; + RECT 316.43 0 329.96 618.3 ; + RECT 333.29 0 335.58 618.3 ; + RECT 338.91 30.685 346.82 36.805 ; + RECT 338.91 0 341.2 618.3 ; + RECT 344.53 0 346.82 618.3 ; + RECT 350.15 30.685 358.06 36.805 ; + RECT 350.15 0 352.44 618.3 ; + RECT 355.77 0 358.06 618.3 ; + RECT 361.39 30.685 380.54 36.805 ; + RECT 361.39 0 374.92 618.3 ; + RECT 378.25 0 380.54 618.3 ; + RECT 383.87 30.685 391.78 36.805 ; + RECT 383.87 0 386.16 618.3 ; + RECT 389.49 0 391.78 618.3 ; + RECT 395.11 30.685 403.02 36.805 ; + RECT 395.11 0 397.4 618.3 ; + RECT 400.73 0 403.02 618.3 ; + RECT 406.35 30.685 425.5 36.805 ; + RECT 406.35 0 419.88 618.3 ; + RECT 423.21 0 425.5 618.3 ; + RECT 428.83 30.685 436.74 36.805 ; + RECT 428.83 0 431.12 618.3 ; + RECT 434.45 0 436.74 618.3 ; + RECT 440.07 30.685 447.98 36.805 ; + RECT 440.07 0 442.36 618.3 ; + RECT 445.69 0 447.98 618.3 ; + RECT 451.31 30.685 470.46 36.805 ; + RECT 451.31 0 464.84 618.3 ; + RECT 468.17 0 470.46 618.3 ; + RECT 473.79 30.685 481.7 36.805 ; + RECT 473.79 0 476.08 618.3 ; + RECT 479.41 0 481.7 618.3 ; + RECT 485.03 30.685 492.94 36.805 ; + RECT 485.03 0 487.32 618.3 ; + RECT 490.65 0 492.94 618.3 ; + RECT 496.27 30.685 515.42 36.805 ; + RECT 496.27 0 509.8 618.3 ; + LAYER Metal4 ; + RECT 1057.87 0 1060.68 37.065 ; + RECT 1063.49 599.405 1066.3 618.3 ; + RECT 1063.49 0 1066.3 30.425 ; + RECT 1102.83 599.405 1105.64 618.3 ; + RECT 1102.83 0 1105.64 37.065 ; + RECT 1108.45 599.405 1111.26 618.3 ; + RECT 1108.45 0 1111.26 30.425 ; + RECT 1147.79 599.405 1150.6 618.3 ; + RECT 1147.79 0 1150.6 37.065 ; + RECT 1153.41 599.405 1156.22 618.3 ; + RECT 1153.41 0 1156.22 30.425 ; + RECT 1192.75 599.405 1195.56 618.3 ; + RECT 1192.75 0 1195.56 37.065 ; + RECT 1198.37 599.405 1201.18 618.3 ; + RECT 1198.37 0 1201.18 30.425 ; + RECT 1237.71 599.405 1240.52 618.3 ; + RECT 1237.71 0 1240.52 37.065 ; + RECT 1243.33 599.405 1246.14 618.3 ; + RECT 1243.33 0 1246.14 30.425 ; + RECT 1282.67 599.405 1285.48 618.3 ; + RECT 1282.67 0 1285.48 37.065 ; + RECT 1288.29 599.405 1291.1 618.3 ; + RECT 1288.29 0 1291.1 30.425 ; + RECT 1327.63 599.405 1330.44 618.3 ; + RECT 1327.63 0 1330.44 37.065 ; + RECT 1333.25 599.405 1336.06 618.3 ; + RECT 1333.25 0 1336.06 30.425 ; + RECT 1372.59 599.405 1375.4 618.3 ; + RECT 1372.59 0 1375.4 37.065 ; + RECT 1378.21 599.405 1381.02 618.3 ; + RECT 1378.21 0 1381.02 30.425 ; + RECT 1417.55 599.405 1420.36 618.3 ; + RECT 1417.55 0 1420.36 37.065 ; + RECT 1423.17 599.405 1425.98 618.3 ; + RECT 1423.17 0 1425.98 30.425 ; + RECT 1462.51 599.405 1465.32 618.3 ; + RECT 1462.51 0 1465.32 37.065 ; + RECT 1468.13 599.405 1470.94 618.3 ; + RECT 1468.13 0 1470.94 30.425 ; + RECT 1507.47 599.405 1510.28 618.3 ; + RECT 1507.47 0 1510.28 37.065 ; + RECT 1513.09 599.405 1515.9 618.3 ; + RECT 1513.09 0 1515.9 30.425 ; + LAYER Metal4 SPACING 0.21 ; + RECT 0 30.685 20.86 36.805 ; + RECT 0 0 15.24 618.3 ; + RECT 18.57 0 20.86 618.3 ; + RECT 24.19 30.685 32.1 36.805 ; + RECT 24.19 0 26.48 618.3 ; + RECT 29.81 0 32.1 618.3 ; + RECT 35.43 30.685 43.34 36.805 ; + RECT 35.43 0 37.72 618.3 ; + RECT 41.05 0 43.34 618.3 ; + RECT 46.67 30.685 65.82 36.805 ; + RECT 46.67 0 60.2 618.3 ; + RECT 63.53 0 65.82 618.3 ; + RECT 69.15 30.685 77.06 36.805 ; + RECT 69.15 0 71.44 618.3 ; + RECT 74.77 0 77.06 618.3 ; + RECT 80.39 30.685 88.3 36.805 ; + RECT 80.39 0 82.68 618.3 ; + RECT 86.01 0 88.3 618.3 ; + RECT 91.63 30.685 110.78 36.805 ; + RECT 513.13 0 515.42 618.3 ; + RECT 518.75 30.685 526.66 36.805 ; + RECT 518.75 0 521.04 618.3 ; + RECT 524.37 0 526.66 618.3 ; + RECT 529.99 30.685 537.9 36.805 ; + RECT 529.99 0 532.28 618.3 ; + RECT 535.61 0 537.9 618.3 ; + RECT 541.23 30.685 560.38 36.805 ; + RECT 541.23 0 554.76 618.3 ; + RECT 558.09 0 560.38 618.3 ; + RECT 563.71 30.685 571.62 36.805 ; + RECT 563.71 0 566 618.3 ; + RECT 569.33 0 571.62 618.3 ; + RECT 574.95 30.685 582.86 36.805 ; + RECT 574.95 0 577.24 618.3 ; + RECT 580.57 0 582.86 618.3 ; + RECT 586.19 30.685 605.34 36.805 ; + RECT 586.19 0 599.72 618.3 ; + RECT 603.05 0 605.34 618.3 ; + RECT 608.67 30.685 616.58 36.805 ; + RECT 608.67 0 610.96 618.3 ; + RECT 614.29 0 616.58 618.3 ; + RECT 619.91 30.685 627.82 36.805 ; + RECT 619.91 0 622.2 618.3 ; + RECT 625.53 0 627.82 618.3 ; + RECT 631.15 30.685 650.3 36.805 ; + RECT 631.15 0 644.68 618.3 ; + RECT 648.01 0 650.3 618.3 ; + RECT 653.63 30.685 661.54 36.805 ; + RECT 653.63 0 655.92 618.3 ; + RECT 659.25 0 661.54 618.3 ; + RECT 664.87 30.685 672.78 36.805 ; + RECT 664.87 0 667.16 618.3 ; + RECT 670.49 0 672.78 618.3 ; + RECT 676.11 30.685 695.26 36.805 ; + RECT 676.11 0 689.64 618.3 ; + RECT 692.97 0 695.26 618.3 ; + RECT 698.59 30.685 706.5 36.805 ; + RECT 698.59 0 700.88 618.3 ; + RECT 704.21 0 706.5 618.3 ; + RECT 709.83 30.685 717.74 36.805 ; + RECT 709.83 0 712.12 618.3 ; + RECT 715.45 0 717.74 618.3 ; + RECT 721.07 0 740.39 618.3 ; + RECT 743.72 0 745.54 618.3 ; + RECT 748.87 0 750.69 618.3 ; + RECT 754.02 0 755.84 618.3 ; + RECT 759.17 0 760.99 618.3 ; + RECT 764.32 0 766.14 618.3 ; + RECT 802.42 30.685 810.33 36.805 ; + RECT 802.42 0 804.71 618.3 ; + RECT 808.04 0 810.33 618.3 ; + RECT 813.66 30.685 821.57 36.805 ; + RECT 813.66 0 815.95 618.3 ; + RECT 819.28 0 821.57 618.3 ; + RECT 824.9 30.685 844.05 36.805 ; + RECT 824.9 0 827.19 618.3 ; + RECT 830.52 0 844.05 618.3 ; + RECT 847.38 30.685 855.29 36.805 ; + RECT 847.38 0 849.67 618.3 ; + RECT 853 0 855.29 618.3 ; + RECT 858.62 30.685 866.53 36.805 ; + RECT 858.62 0 860.91 618.3 ; + RECT 864.24 0 866.53 618.3 ; + RECT 869.86 30.685 889.01 36.805 ; + RECT 869.86 0 872.15 618.3 ; + RECT 875.48 0 889.01 618.3 ; + RECT 892.34 30.685 900.25 36.805 ; + RECT 892.34 0 894.63 618.3 ; + RECT 897.96 0 900.25 618.3 ; + RECT 903.58 30.685 911.49 36.805 ; + RECT 903.58 0 905.87 618.3 ; + RECT 909.2 0 911.49 618.3 ; + RECT 914.82 30.685 933.97 36.805 ; + RECT 914.82 0 917.11 618.3 ; + RECT 920.44 0 933.97 618.3 ; + RECT 937.3 30.685 945.21 36.805 ; + RECT 937.3 0 939.59 618.3 ; + RECT 942.92 0 945.21 618.3 ; + RECT 948.54 30.685 956.45 36.805 ; + RECT 948.54 0 950.83 618.3 ; + RECT 954.16 0 956.45 618.3 ; + RECT 959.78 30.685 978.93 36.805 ; + RECT 959.78 0 962.07 618.3 ; + RECT 965.4 0 978.93 618.3 ; + RECT 982.26 30.685 990.17 36.805 ; + RECT 982.26 0 984.55 618.3 ; + RECT 987.88 0 990.17 618.3 ; + RECT 993.5 30.685 1001.41 36.805 ; + RECT 993.5 0 995.79 618.3 ; + RECT 999.12 0 1001.41 618.3 ; + RECT 1004.74 30.685 1023.89 36.805 ; + RECT 1004.74 0 1007.03 618.3 ; + RECT 1010.36 0 1023.89 618.3 ; + RECT 1027.22 30.685 1035.13 36.805 ; + RECT 1027.22 0 1029.51 618.3 ; + RECT 1032.84 0 1035.13 618.3 ; + RECT 1038.46 30.685 1046.37 36.805 ; + RECT 1038.46 0 1040.75 618.3 ; + RECT 1044.08 0 1046.37 618.3 ; + RECT 1049.7 30.685 1068.85 36.805 ; + RECT 1049.7 0 1051.99 618.3 ; + RECT 1055.32 0 1068.85 618.3 ; + RECT 1072.18 30.685 1080.09 36.805 ; + RECT 1072.18 0 1074.47 618.3 ; + RECT 1077.8 0 1080.09 618.3 ; + RECT 1083.42 30.685 1091.33 36.805 ; + RECT 1083.42 0 1085.71 618.3 ; + RECT 1089.04 0 1091.33 618.3 ; + RECT 1094.66 30.685 1113.81 36.805 ; + RECT 1094.66 0 1096.95 618.3 ; + RECT 1100.28 0 1113.81 618.3 ; + RECT 1117.14 30.685 1125.05 36.805 ; + RECT 1117.14 0 1119.43 618.3 ; + RECT 1122.76 0 1125.05 618.3 ; + RECT 1128.38 30.685 1136.29 36.805 ; + RECT 1128.38 0 1130.67 618.3 ; + RECT 1134 0 1136.29 618.3 ; + RECT 1139.62 30.685 1158.77 36.805 ; + RECT 1139.62 0 1141.91 618.3 ; + RECT 1145.24 0 1158.77 618.3 ; + RECT 1162.1 30.685 1170.01 36.805 ; + RECT 1162.1 0 1164.39 618.3 ; + RECT 1167.72 0 1170.01 618.3 ; + RECT 1173.34 30.685 1181.25 36.805 ; + RECT 1173.34 0 1175.63 618.3 ; + RECT 1178.96 0 1181.25 618.3 ; + RECT 1184.58 30.685 1203.73 36.805 ; + RECT 1184.58 0 1186.87 618.3 ; + RECT 1190.2 0 1203.73 618.3 ; + RECT 1207.06 30.685 1214.97 36.805 ; + RECT 1207.06 0 1209.35 618.3 ; + RECT 1212.68 0 1214.97 618.3 ; + RECT 1218.3 30.685 1226.21 36.805 ; + RECT 1218.3 0 1220.59 618.3 ; + RECT 1223.92 0 1226.21 618.3 ; + RECT 1229.54 30.685 1248.69 36.805 ; + RECT 1229.54 0 1231.83 618.3 ; + RECT 1235.16 0 1248.69 618.3 ; + RECT 1252.02 30.685 1259.93 36.805 ; + RECT 1252.02 0 1254.31 618.3 ; + RECT 1263.26 0 1265.55 618.3 ; + RECT 1268.88 0 1271.17 618.3 ; + RECT 1274.5 30.685 1293.65 36.805 ; + RECT 1274.5 0 1276.79 618.3 ; + RECT 1280.12 0 1293.65 618.3 ; + RECT 1296.98 30.685 1304.89 36.805 ; + RECT 1296.98 0 1299.27 618.3 ; + RECT 1302.6 0 1304.89 618.3 ; + RECT 1308.22 30.685 1316.13 36.805 ; + RECT 1308.22 0 1310.51 618.3 ; + RECT 1313.84 0 1316.13 618.3 ; + RECT 1319.46 30.685 1338.61 36.805 ; + RECT 1319.46 0 1321.75 618.3 ; + RECT 1325.08 0 1338.61 618.3 ; + RECT 1341.94 30.685 1349.85 36.805 ; + RECT 1341.94 0 1344.23 618.3 ; + RECT 1347.56 0 1349.85 618.3 ; + RECT 1353.18 30.685 1361.09 36.805 ; + RECT 1353.18 0 1355.47 618.3 ; + RECT 1358.8 0 1361.09 618.3 ; + RECT 1364.42 30.685 1383.57 36.805 ; + RECT 1364.42 0 1366.71 618.3 ; + RECT 1370.04 0 1383.57 618.3 ; + RECT 1386.9 30.685 1394.81 36.805 ; + RECT 1386.9 0 1389.19 618.3 ; + RECT 1392.52 0 1394.81 618.3 ; + RECT 1398.14 30.685 1406.05 36.805 ; + RECT 1398.14 0 1400.43 618.3 ; + RECT 1403.76 0 1406.05 618.3 ; + RECT 1409.38 30.685 1428.53 36.805 ; + RECT 1409.38 0 1411.67 618.3 ; + RECT 1415 0 1428.53 618.3 ; + RECT 1431.86 30.685 1439.77 36.805 ; + RECT 1431.86 0 1434.15 618.3 ; + RECT 1437.48 0 1439.77 618.3 ; + RECT 1443.1 30.685 1451.01 36.805 ; + RECT 1443.1 0 1445.39 618.3 ; + RECT 1448.72 0 1451.01 618.3 ; + RECT 1454.34 30.685 1473.49 36.805 ; + RECT 1454.34 0 1456.63 618.3 ; + RECT 1459.96 0 1473.49 618.3 ; + RECT 1476.82 30.685 1484.73 36.805 ; + RECT 1476.82 0 1479.11 618.3 ; + RECT 1482.44 0 1484.73 618.3 ; + RECT 1488.06 30.685 1495.97 36.805 ; + RECT 1488.06 0 1490.35 618.3 ; + RECT 1493.68 0 1495.97 618.3 ; + RECT 1499.3 30.685 1520.16 36.805 ; + RECT 1499.3 0 1501.59 618.3 ; + RECT 1504.92 0 1520.16 618.3 ; + RECT 769.47 0 771.29 618.3 ; + RECT 774.62 0 776.44 618.3 ; + RECT 779.77 0 799.09 618.3 ; + RECT 1257.64 0 1259.93 618.3 ; + RECT 1263.26 30.685 1271.17 36.805 ; + END +END RM_IHPSG13_1P_8192x32_c4 + +END LIBRARY diff --git a/flow/platforms/ihp-sg13g2/lef/RM_IHPSG13_2P_1024x16_c2_bm_bist.lef b/flow/platforms/ihp-sg13g2/lef/RM_IHPSG13_2P_1024x16_c2_bm_bist.lef new file mode 100644 index 0000000000..4162076069 --- /dev/null +++ b/flow/platforms/ihp-sg13g2/lef/RM_IHPSG13_2P_1024x16_c2_bm_bist.lef @@ -0,0 +1,4307 @@ +# ------------------------------------------------------ +# +# Copyright 2025 IHP PDK Authors +# +# Licensed under the Apache License, Version 2.0 (the "License"); +# you may not use this file except in compliance with the License. +# You may obtain a copy of the License at +# +# https://www.apache.org/licenses/LICENSE-2.0 +# +# Unless required by applicable law or agreed to in writing, software +# distributed under the License is distributed on an "AS IS" BASIS, +# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +# See the License for the specific language governing permissions and +# limitations under the License. +# +# Generated on Tue Sep 9 10:49:24 2025 +# +# ------------------------------------------------------ +VERSION 5.7 ; +BUSBITCHARS "[]" ; +DIVIDERCHAR "/" ; + +MACRO RM_IHPSG13_2P_1024x16_c2_bm_bist + CLASS BLOCK ; + ORIGIN 0 0 ; + FOREIGN RM_IHPSG13_2P_1024x16_c2_bm_bist 0 0 ; + SIZE 402.61 BY 385.37 ; + SYMMETRY X Y R90 ; + PIN A_DIN[8] + DIRECTION INPUT ; + USE SIGNAL ; + ANTENNAPARTIALMETALAREA 3.9091 LAYER Metal2 ; + ANTENNAMODEL OXIDE1 ; + ANTENNAGATEAREA 0.20085 LAYER Metal2 ; + ANTENNAMAXAREACAR 20.368932 LAYER Metal2 ; + PORT + LAYER Metal2 ; + RECT 266.71 0 266.97 0.26 ; + END + END A_DIN[8] + PIN A_DIN[7] + DIRECTION INPUT ; + USE SIGNAL ; + ANTENNAPARTIALMETALAREA 3.9091 LAYER Metal2 ; + ANTENNAMODEL OXIDE1 ; + ANTENNAGATEAREA 0.20085 LAYER Metal2 ; + ANTENNAMAXAREACAR 20.368932 LAYER Metal2 ; + PORT + LAYER Metal2 ; + RECT 135.64 0 135.9 0.26 ; + END + END A_DIN[7] + PIN A_BIST_DIN[8] + DIRECTION INPUT ; + USE SIGNAL ; + ANTENNAPARTIALMETALAREA 4.136375 LAYER Metal2 ; + ANTENNAMODEL OXIDE1 ; + ANTENNAGATEAREA 0.20085 LAYER Metal2 ; + ANTENNAMAXAREACAR 21.874907 LAYER Metal2 ; + PORT + LAYER Metal2 ; + RECT 267.22 0 267.48 0.26 ; + END + END A_BIST_DIN[8] + PIN A_BIST_DIN[7] + DIRECTION INPUT ; + USE SIGNAL ; + ANTENNAPARTIALMETALAREA 4.136375 LAYER Metal2 ; + ANTENNAMODEL OXIDE1 ; + ANTENNAGATEAREA 0.20085 LAYER Metal2 ; + ANTENNAMAXAREACAR 21.874907 LAYER Metal2 ; + PORT + LAYER Metal2 ; + RECT 135.13 0 135.39 0.26 ; + END + END A_BIST_DIN[7] + PIN A_BM[8] + DIRECTION INPUT ; + USE SIGNAL ; + ANTENNAPARTIALMETALAREA 1.7264 LAYER Metal2 ; + ANTENNAMODEL OXIDE1 ; + ANTENNAGATEAREA 0.20085 LAYER Metal2 ; + ANTENNAMAXAREACAR 9.501618 LAYER Metal2 ; + PORT + LAYER Metal2 ; + RECT 275.38 0 275.64 0.26 ; + END + END A_BM[8] + PIN A_BM[7] + DIRECTION INPUT ; + USE SIGNAL ; + ANTENNAPARTIALMETALAREA 1.7264 LAYER Metal2 ; + ANTENNAMODEL OXIDE1 ; + ANTENNAGATEAREA 0.20085 LAYER Metal2 ; + ANTENNAMAXAREACAR 9.501618 LAYER Metal2 ; + PORT + LAYER Metal2 ; + RECT 126.97 0 127.23 0.26 ; + END + END A_BM[7] + PIN A_BIST_BM[8] + DIRECTION INPUT ; + USE SIGNAL ; + ANTENNAPARTIALMETALAREA 1.7602 LAYER Metal2 ; + ANTENNAMODEL OXIDE1 ; + ANTENNAGATEAREA 0.20085 LAYER Metal2 ; + ANTENNAMAXAREACAR 9.678367 LAYER Metal2 ; + PORT + LAYER Metal2 ; + RECT 274.005 0 274.265 0.26 ; + END + END A_BIST_BM[8] + PIN A_BIST_BM[7] + DIRECTION INPUT ; + USE SIGNAL ; + ANTENNAPARTIALMETALAREA 1.7602 LAYER Metal2 ; + ANTENNAMODEL OXIDE1 ; + ANTENNAGATEAREA 0.20085 LAYER Metal2 ; + ANTENNAMAXAREACAR 9.678367 LAYER Metal2 ; + PORT + LAYER Metal2 ; + RECT 128.345 0 128.605 0.26 ; + END + END A_BIST_BM[7] + PIN A_DOUT[8] + DIRECTION OUTPUT ; + USE SIGNAL ; + ANTENNAPARTIALMETALAREA 4.8256 LAYER Metal2 ; + ANTENNADIFFAREA 0.988 LAYER Metal2 ; + PORT + LAYER Metal2 ; + RECT 259.57 0 259.83 0.26 ; + END + END A_DOUT[8] + PIN A_DOUT[7] + DIRECTION OUTPUT ; + USE SIGNAL ; + ANTENNAPARTIALMETALAREA 4.8256 LAYER Metal2 ; + ANTENNADIFFAREA 0.988 LAYER Metal2 ; + PORT + LAYER Metal2 ; + RECT 142.78 0 143.04 0.26 ; + END + END A_DOUT[7] + PIN B_DIN[8] + DIRECTION INPUT ; + USE SIGNAL ; + ANTENNAPARTIALMETALAREA 2.925 LAYER Metal2 ; + ANTENNAMODEL OXIDE1 ; + ANTENNAGATEAREA 0.20085 LAYER Metal2 ; + ANTENNAMAXAREACAR 15.469256 LAYER Metal2 ; + PORT + LAYER Metal2 ; + RECT 269.26 0 269.52 0.26 ; + END + END B_DIN[8] + PIN B_DIN[7] + DIRECTION INPUT ; + USE SIGNAL ; + ANTENNAPARTIALMETALAREA 2.925 LAYER Metal2 ; + ANTENNAMODEL OXIDE1 ; + ANTENNAGATEAREA 0.20085 LAYER Metal2 ; + ANTENNAMAXAREACAR 15.469256 LAYER Metal2 ; + PORT + LAYER Metal2 ; + RECT 133.09 0 133.35 0.26 ; + END + END B_DIN[7] + PIN B_BIST_DIN[8] + DIRECTION INPUT ; + USE SIGNAL ; + ANTENNAPARTIALMETALAREA 2.9445 LAYER Metal2 ; + ANTENNAMODEL OXIDE1 ; + ANTENNAGATEAREA 0.20085 LAYER Metal2 ; + ANTENNAMAXAREACAR 15.929052 LAYER Metal2 ; + PORT + LAYER Metal2 ; + RECT 267.73 0 267.99 0.26 ; + END + END B_BIST_DIN[8] + PIN B_BIST_DIN[7] + DIRECTION INPUT ; + USE SIGNAL ; + ANTENNAPARTIALMETALAREA 2.9445 LAYER Metal2 ; + ANTENNAMODEL OXIDE1 ; + ANTENNAGATEAREA 0.20085 LAYER Metal2 ; + ANTENNAMAXAREACAR 15.929052 LAYER Metal2 ; + PORT + LAYER Metal2 ; + RECT 134.62 0 134.88 0.26 ; + END + END B_BIST_DIN[7] + PIN B_BM[8] + DIRECTION INPUT ; + USE SIGNAL ; + ANTENNAPARTIALMETALAREA 0.7007 LAYER Metal2 ; + ANTENNAMODEL OXIDE1 ; + ANTENNAGATEAREA 0.20085 LAYER Metal2 ; + ANTENNAMAXAREACAR 4.394822 LAYER Metal2 ; + PORT + LAYER Metal2 ; + RECT 260.745 0 261.005 0.26 ; + END + END B_BM[8] + PIN B_BM[7] + DIRECTION INPUT ; + USE SIGNAL ; + ANTENNAPARTIALMETALAREA 0.7007 LAYER Metal2 ; + ANTENNAMODEL OXIDE1 ; + ANTENNAGATEAREA 0.20085 LAYER Metal2 ; + ANTENNAMAXAREACAR 4.394822 LAYER Metal2 ; + PORT + LAYER Metal2 ; + RECT 141.605 0 141.865 0.26 ; + END + END B_BM[7] + PIN B_BIST_BM[8] + DIRECTION INPUT ; + USE SIGNAL ; + ANTENNAPARTIALMETALAREA 0.7007 LAYER Metal2 ; + ANTENNAMODEL OXIDE1 ; + ANTENNAGATEAREA 0.20085 LAYER Metal2 ; + ANTENNAMAXAREACAR 4.394822 LAYER Metal2 ; + PORT + LAYER Metal2 ; + RECT 262.275 0 262.535 0.26 ; + END + END B_BIST_BM[8] + PIN B_BIST_BM[7] + DIRECTION INPUT ; + USE SIGNAL ; + ANTENNAPARTIALMETALAREA 0.7007 LAYER Metal2 ; + ANTENNAMODEL OXIDE1 ; + ANTENNAGATEAREA 0.20085 LAYER Metal2 ; + ANTENNAMAXAREACAR 4.394822 LAYER Metal2 ; + PORT + LAYER Metal2 ; + RECT 140.075 0 140.335 0.26 ; + END + END B_BIST_BM[7] + PIN B_DOUT[8] + DIRECTION OUTPUT ; + USE SIGNAL ; + ANTENNAPARTIALMETALAREA 4.836 LAYER Metal2 ; + ANTENNADIFFAREA 0.988 LAYER Metal2 ; + PORT + LAYER Metal2 ; + RECT 276.4 0 276.66 0.26 ; + END + END B_DOUT[8] + PIN B_DOUT[7] + DIRECTION OUTPUT ; + USE SIGNAL ; + ANTENNAPARTIALMETALAREA 4.836 LAYER Metal2 ; + ANTENNADIFFAREA 0.988 LAYER Metal2 ; + PORT + LAYER Metal2 ; + RECT 125.95 0 126.21 0.26 ; + END + END B_DOUT[7] + PIN VSS! + DIRECTION INOUT ; + USE GROUND ; + NETEXPR "vss VSS!" ; + PORT + LAYER Metal4 ; + RECT 383.205 0 387.625 385.37 ; + END + PORT + LAYER Metal4 ; + RECT 365.525 0 369.945 385.37 ; + END + PORT + LAYER Metal4 ; + RECT 347.845 0 352.265 385.37 ; + END + PORT + LAYER Metal4 ; + RECT 330.165 0 334.585 385.37 ; + END + PORT + LAYER Metal4 ; + RECT 312.485 0 316.905 385.37 ; + END + PORT + LAYER Metal4 ; + RECT 294.805 0 299.225 385.37 ; + END + PORT + LAYER Metal4 ; + RECT 277.125 0 281.545 385.37 ; + END + PORT + LAYER Metal4 ; + RECT 259.445 0 263.865 385.37 ; + END + PORT + LAYER Metal4 ; + RECT 238.525 0 241.335 385.37 ; + END + PORT + LAYER Metal4 ; + RECT 228.225 0 231.035 385.37 ; + END + PORT + LAYER Metal4 ; + RECT 212.775 0 215.585 385.37 ; + END + PORT + LAYER Metal4 ; + RECT 202.475 0 205.285 385.37 ; + END + PORT + LAYER Metal4 ; + RECT 197.325 0 200.135 385.37 ; + END + PORT + LAYER Metal4 ; + RECT 187.025 0 189.835 385.37 ; + END + PORT + LAYER Metal4 ; + RECT 171.575 0 174.385 385.37 ; + END + PORT + LAYER Metal4 ; + RECT 161.275 0 164.085 385.37 ; + END + PORT + LAYER Metal4 ; + RECT 138.745 0 143.165 385.37 ; + END + PORT + LAYER Metal4 ; + RECT 121.065 0 125.485 385.37 ; + END + PORT + LAYER Metal4 ; + RECT 103.385 0 107.805 385.37 ; + END + PORT + LAYER Metal4 ; + RECT 85.705 0 90.125 385.37 ; + END + PORT + LAYER Metal4 ; + RECT 68.025 0 72.445 385.37 ; + END + PORT + LAYER Metal4 ; + RECT 50.345 0 54.765 385.37 ; + END + PORT + LAYER Metal4 ; + RECT 32.665 0 37.085 385.37 ; + END + PORT + LAYER Metal4 ; + RECT 14.985 0 19.405 385.37 ; + END + END VSS! + PIN VDD! + DIRECTION INOUT ; + USE POWER ; + NETEXPR "vdd VDD!" ; + PORT + LAYER Metal4 ; + RECT 392.045 0 396.465 47.045 ; + END + PORT + LAYER Metal4 ; + RECT 374.365 0 378.785 47.045 ; + END + PORT + LAYER Metal4 ; + RECT 356.685 0 361.105 47.045 ; + END + PORT + LAYER Metal4 ; + RECT 339.005 0 343.425 47.045 ; + END + PORT + LAYER Metal4 ; + RECT 321.325 0 325.745 47.045 ; + END + PORT + LAYER Metal4 ; + RECT 303.645 0 308.065 47.045 ; + END + PORT + LAYER Metal4 ; + RECT 285.965 0 290.385 47.045 ; + END + PORT + LAYER Metal4 ; + RECT 268.285 0 272.705 47.045 ; + END + PORT + LAYER Metal4 ; + RECT 233.375 0 236.185 385.37 ; + END + PORT + LAYER Metal4 ; + RECT 223.075 0 225.885 385.37 ; + END + PORT + LAYER Metal4 ; + RECT 217.925 0 220.735 385.37 ; + END + PORT + LAYER Metal4 ; + RECT 207.625 0 210.435 385.37 ; + END + PORT + LAYER Metal4 ; + RECT 192.175 0 194.985 385.37 ; + END + PORT + LAYER Metal4 ; + RECT 181.875 0 184.685 385.37 ; + END + PORT + LAYER Metal4 ; + RECT 176.725 0 179.535 385.37 ; + END + PORT + LAYER Metal4 ; + RECT 166.425 0 169.235 385.37 ; + END + PORT + LAYER Metal4 ; + RECT 129.905 0 134.325 47.045 ; + END + PORT + LAYER Metal4 ; + RECT 112.225 0 116.645 47.045 ; + END + PORT + LAYER Metal4 ; + RECT 94.545 0 98.965 47.045 ; + END + PORT + LAYER Metal4 ; + RECT 76.865 0 81.285 47.045 ; + END + PORT + LAYER Metal4 ; + RECT 59.185 0 63.605 47.045 ; + END + PORT + LAYER Metal4 ; + RECT 41.505 0 45.925 47.045 ; + END + PORT + LAYER Metal4 ; + RECT 23.825 0 28.245 47.045 ; + END + PORT + LAYER Metal4 ; + RECT 6.145 0 10.565 47.045 ; + END + END VDD! + PIN VDDARRAY! + DIRECTION INOUT ; + USE POWER ; + NETEXPR "vddarray VDDARRAY!" ; + PORT + LAYER Metal4 ; + RECT 392.045 53.41 396.465 385.37 ; + END + PORT + LAYER Metal4 ; + RECT 374.365 53.41 378.785 385.37 ; + END + PORT + LAYER Metal4 ; + RECT 356.685 53.41 361.105 385.37 ; + END + PORT + LAYER Metal4 ; + RECT 339.005 53.41 343.425 385.37 ; + END + PORT + LAYER Metal4 ; + RECT 321.325 53.41 325.745 385.37 ; + END + PORT + LAYER Metal4 ; + RECT 303.645 53.41 308.065 385.37 ; + END + PORT + LAYER Metal4 ; + RECT 285.965 53.41 290.385 385.37 ; + END + PORT + LAYER Metal4 ; + RECT 268.285 53.41 272.705 385.37 ; + END + PORT + LAYER Metal4 ; + RECT 129.905 53.41 134.325 385.37 ; + END + PORT + LAYER Metal4 ; + RECT 112.225 53.41 116.645 385.37 ; + END + PORT + LAYER Metal4 ; + RECT 94.545 53.41 98.965 385.37 ; + END + PORT + LAYER Metal4 ; + RECT 76.865 53.41 81.285 385.37 ; + END + PORT + LAYER Metal4 ; + RECT 59.185 53.41 63.605 385.37 ; + END + PORT + LAYER Metal4 ; + RECT 41.505 53.41 45.925 385.37 ; + END + PORT + LAYER Metal4 ; + RECT 23.825 53.41 28.245 385.37 ; + END + PORT + LAYER Metal4 ; + RECT 6.145 53.41 10.565 385.37 ; + END + END VDDARRAY! + PIN A_DIN[9] + DIRECTION INPUT ; + USE SIGNAL ; + ANTENNAPARTIALMETALAREA 3.9091 LAYER Metal2 ; + ANTENNAMODEL OXIDE1 ; + ANTENNAGATEAREA 0.20085 LAYER Metal2 ; + ANTENNAMAXAREACAR 20.368932 LAYER Metal2 ; + PORT + LAYER Metal2 ; + RECT 284.39 0 284.65 0.26 ; + END + END A_DIN[9] + PIN A_DIN[6] + DIRECTION INPUT ; + USE SIGNAL ; + ANTENNAPARTIALMETALAREA 3.9091 LAYER Metal2 ; + ANTENNAMODEL OXIDE1 ; + ANTENNAGATEAREA 0.20085 LAYER Metal2 ; + ANTENNAMAXAREACAR 20.368932 LAYER Metal2 ; + PORT + LAYER Metal2 ; + RECT 117.96 0 118.22 0.26 ; + END + END A_DIN[6] + PIN A_BIST_DIN[9] + DIRECTION INPUT ; + USE SIGNAL ; + ANTENNAPARTIALMETALAREA 4.136375 LAYER Metal2 ; + ANTENNAMODEL OXIDE1 ; + ANTENNAGATEAREA 0.20085 LAYER Metal2 ; + ANTENNAMAXAREACAR 21.874907 LAYER Metal2 ; + PORT + LAYER Metal2 ; + RECT 284.9 0 285.16 0.26 ; + END + END A_BIST_DIN[9] + PIN A_BIST_DIN[6] + DIRECTION INPUT ; + USE SIGNAL ; + ANTENNAPARTIALMETALAREA 4.136375 LAYER Metal2 ; + ANTENNAMODEL OXIDE1 ; + ANTENNAGATEAREA 0.20085 LAYER Metal2 ; + ANTENNAMAXAREACAR 21.874907 LAYER Metal2 ; + PORT + LAYER Metal2 ; + RECT 117.45 0 117.71 0.26 ; + END + END A_BIST_DIN[6] + PIN A_BM[9] + DIRECTION INPUT ; + USE SIGNAL ; + ANTENNAPARTIALMETALAREA 1.7264 LAYER Metal2 ; + ANTENNAMODEL OXIDE1 ; + ANTENNAGATEAREA 0.20085 LAYER Metal2 ; + ANTENNAMAXAREACAR 9.501618 LAYER Metal2 ; + PORT + LAYER Metal2 ; + RECT 293.06 0 293.32 0.26 ; + END + END A_BM[9] + PIN A_BM[6] + DIRECTION INPUT ; + USE SIGNAL ; + ANTENNAPARTIALMETALAREA 1.7264 LAYER Metal2 ; + ANTENNAMODEL OXIDE1 ; + ANTENNAGATEAREA 0.20085 LAYER Metal2 ; + ANTENNAMAXAREACAR 9.501618 LAYER Metal2 ; + PORT + LAYER Metal2 ; + RECT 109.29 0 109.55 0.26 ; + END + END A_BM[6] + PIN A_BIST_BM[9] + DIRECTION INPUT ; + USE SIGNAL ; + ANTENNAPARTIALMETALAREA 1.7602 LAYER Metal2 ; + ANTENNAMODEL OXIDE1 ; + ANTENNAGATEAREA 0.20085 LAYER Metal2 ; + ANTENNAMAXAREACAR 9.678367 LAYER Metal2 ; + PORT + LAYER Metal2 ; + RECT 291.685 0 291.945 0.26 ; + END + END A_BIST_BM[9] + PIN A_BIST_BM[6] + DIRECTION INPUT ; + USE SIGNAL ; + ANTENNAPARTIALMETALAREA 1.7602 LAYER Metal2 ; + ANTENNAMODEL OXIDE1 ; + ANTENNAGATEAREA 0.20085 LAYER Metal2 ; + ANTENNAMAXAREACAR 9.678367 LAYER Metal2 ; + PORT + LAYER Metal2 ; + RECT 110.665 0 110.925 0.26 ; + END + END A_BIST_BM[6] + PIN A_DOUT[9] + DIRECTION OUTPUT ; + USE SIGNAL ; + ANTENNAPARTIALMETALAREA 4.8256 LAYER Metal2 ; + ANTENNADIFFAREA 0.988 LAYER Metal2 ; + PORT + LAYER Metal2 ; + RECT 277.25 0 277.51 0.26 ; + END + END A_DOUT[9] + PIN A_DOUT[6] + DIRECTION OUTPUT ; + USE SIGNAL ; + ANTENNAPARTIALMETALAREA 4.8256 LAYER Metal2 ; + ANTENNADIFFAREA 0.988 LAYER Metal2 ; + PORT + LAYER Metal2 ; + RECT 125.1 0 125.36 0.26 ; + END + END A_DOUT[6] + PIN B_DIN[9] + DIRECTION INPUT ; + USE SIGNAL ; + ANTENNAPARTIALMETALAREA 2.925 LAYER Metal2 ; + ANTENNAMODEL OXIDE1 ; + ANTENNAGATEAREA 0.20085 LAYER Metal2 ; + ANTENNAMAXAREACAR 15.469256 LAYER Metal2 ; + PORT + LAYER Metal2 ; + RECT 286.94 0 287.2 0.26 ; + END + END B_DIN[9] + PIN B_DIN[6] + DIRECTION INPUT ; + USE SIGNAL ; + ANTENNAPARTIALMETALAREA 2.925 LAYER Metal2 ; + ANTENNAMODEL OXIDE1 ; + ANTENNAGATEAREA 0.20085 LAYER Metal2 ; + ANTENNAMAXAREACAR 15.469256 LAYER Metal2 ; + PORT + LAYER Metal2 ; + RECT 115.41 0 115.67 0.26 ; + END + END B_DIN[6] + PIN B_BIST_DIN[9] + DIRECTION INPUT ; + USE SIGNAL ; + ANTENNAPARTIALMETALAREA 2.9445 LAYER Metal2 ; + ANTENNAMODEL OXIDE1 ; + ANTENNAGATEAREA 0.20085 LAYER Metal2 ; + ANTENNAMAXAREACAR 15.929052 LAYER Metal2 ; + PORT + LAYER Metal2 ; + RECT 285.41 0 285.67 0.26 ; + END + END B_BIST_DIN[9] + PIN B_BIST_DIN[6] + DIRECTION INPUT ; + USE SIGNAL ; + ANTENNAPARTIALMETALAREA 2.9445 LAYER Metal2 ; + ANTENNAMODEL OXIDE1 ; + ANTENNAGATEAREA 0.20085 LAYER Metal2 ; + ANTENNAMAXAREACAR 15.929052 LAYER Metal2 ; + PORT + LAYER Metal2 ; + RECT 116.94 0 117.2 0.26 ; + END + END B_BIST_DIN[6] + PIN B_BM[9] + DIRECTION INPUT ; + USE SIGNAL ; + ANTENNAPARTIALMETALAREA 0.7007 LAYER Metal2 ; + ANTENNAMODEL OXIDE1 ; + ANTENNAGATEAREA 0.20085 LAYER Metal2 ; + ANTENNAMAXAREACAR 4.394822 LAYER Metal2 ; + PORT + LAYER Metal2 ; + RECT 278.425 0 278.685 0.26 ; + END + END B_BM[9] + PIN B_BM[6] + DIRECTION INPUT ; + USE SIGNAL ; + ANTENNAPARTIALMETALAREA 0.7007 LAYER Metal2 ; + ANTENNAMODEL OXIDE1 ; + ANTENNAGATEAREA 0.20085 LAYER Metal2 ; + ANTENNAMAXAREACAR 4.394822 LAYER Metal2 ; + PORT + LAYER Metal2 ; + RECT 123.925 0 124.185 0.26 ; + END + END B_BM[6] + PIN B_BIST_BM[9] + DIRECTION INPUT ; + USE SIGNAL ; + ANTENNAPARTIALMETALAREA 0.7007 LAYER Metal2 ; + ANTENNAMODEL OXIDE1 ; + ANTENNAGATEAREA 0.20085 LAYER Metal2 ; + ANTENNAMAXAREACAR 4.394822 LAYER Metal2 ; + PORT + LAYER Metal2 ; + RECT 279.955 0 280.215 0.26 ; + END + END B_BIST_BM[9] + PIN B_BIST_BM[6] + DIRECTION INPUT ; + USE SIGNAL ; + ANTENNAPARTIALMETALAREA 0.7007 LAYER Metal2 ; + ANTENNAMODEL OXIDE1 ; + ANTENNAGATEAREA 0.20085 LAYER Metal2 ; + ANTENNAMAXAREACAR 4.394822 LAYER Metal2 ; + PORT + LAYER Metal2 ; + RECT 122.395 0 122.655 0.26 ; + END + END B_BIST_BM[6] + PIN B_DOUT[9] + DIRECTION OUTPUT ; + USE SIGNAL ; + ANTENNAPARTIALMETALAREA 4.836 LAYER Metal2 ; + ANTENNADIFFAREA 0.988 LAYER Metal2 ; + PORT + LAYER Metal2 ; + RECT 294.08 0 294.34 0.26 ; + END + END B_DOUT[9] + PIN B_DOUT[6] + DIRECTION OUTPUT ; + USE SIGNAL ; + ANTENNAPARTIALMETALAREA 4.836 LAYER Metal2 ; + ANTENNADIFFAREA 0.988 LAYER Metal2 ; + PORT + LAYER Metal2 ; + RECT 108.27 0 108.53 0.26 ; + END + END B_DOUT[6] + PIN A_DIN[10] + DIRECTION INPUT ; + USE SIGNAL ; + ANTENNAPARTIALMETALAREA 3.9091 LAYER Metal2 ; + ANTENNAMODEL OXIDE1 ; + ANTENNAGATEAREA 0.20085 LAYER Metal2 ; + ANTENNAMAXAREACAR 20.368932 LAYER Metal2 ; + PORT + LAYER Metal2 ; + RECT 302.07 0 302.33 0.26 ; + END + END A_DIN[10] + PIN A_DIN[5] + DIRECTION INPUT ; + USE SIGNAL ; + ANTENNAPARTIALMETALAREA 3.9091 LAYER Metal2 ; + ANTENNAMODEL OXIDE1 ; + ANTENNAGATEAREA 0.20085 LAYER Metal2 ; + ANTENNAMAXAREACAR 20.368932 LAYER Metal2 ; + PORT + LAYER Metal2 ; + RECT 100.28 0 100.54 0.26 ; + END + END A_DIN[5] + PIN A_BIST_DIN[10] + DIRECTION INPUT ; + USE SIGNAL ; + ANTENNAPARTIALMETALAREA 4.136375 LAYER Metal2 ; + ANTENNAMODEL OXIDE1 ; + ANTENNAGATEAREA 0.20085 LAYER Metal2 ; + ANTENNAMAXAREACAR 21.874907 LAYER Metal2 ; + PORT + LAYER Metal2 ; + RECT 302.58 0 302.84 0.26 ; + END + END A_BIST_DIN[10] + PIN A_BIST_DIN[5] + DIRECTION INPUT ; + USE SIGNAL ; + ANTENNAPARTIALMETALAREA 4.136375 LAYER Metal2 ; + ANTENNAMODEL OXIDE1 ; + ANTENNAGATEAREA 0.20085 LAYER Metal2 ; + ANTENNAMAXAREACAR 21.874907 LAYER Metal2 ; + PORT + LAYER Metal2 ; + RECT 99.77 0 100.03 0.26 ; + END + END A_BIST_DIN[5] + PIN A_BM[10] + DIRECTION INPUT ; + USE SIGNAL ; + ANTENNAPARTIALMETALAREA 1.7264 LAYER Metal2 ; + ANTENNAMODEL OXIDE1 ; + ANTENNAGATEAREA 0.20085 LAYER Metal2 ; + ANTENNAMAXAREACAR 9.501618 LAYER Metal2 ; + PORT + LAYER Metal2 ; + RECT 310.74 0 311 0.26 ; + END + END A_BM[10] + PIN A_BM[5] + DIRECTION INPUT ; + USE SIGNAL ; + ANTENNAPARTIALMETALAREA 1.7264 LAYER Metal2 ; + ANTENNAMODEL OXIDE1 ; + ANTENNAGATEAREA 0.20085 LAYER Metal2 ; + ANTENNAMAXAREACAR 9.501618 LAYER Metal2 ; + PORT + LAYER Metal2 ; + RECT 91.61 0 91.87 0.26 ; + END + END A_BM[5] + PIN A_BIST_BM[10] + DIRECTION INPUT ; + USE SIGNAL ; + ANTENNAPARTIALMETALAREA 1.7602 LAYER Metal2 ; + ANTENNAMODEL OXIDE1 ; + ANTENNAGATEAREA 0.20085 LAYER Metal2 ; + ANTENNAMAXAREACAR 9.678367 LAYER Metal2 ; + PORT + LAYER Metal2 ; + RECT 309.365 0 309.625 0.26 ; + END + END A_BIST_BM[10] + PIN A_BIST_BM[5] + DIRECTION INPUT ; + USE SIGNAL ; + ANTENNAPARTIALMETALAREA 1.7602 LAYER Metal2 ; + ANTENNAMODEL OXIDE1 ; + ANTENNAGATEAREA 0.20085 LAYER Metal2 ; + ANTENNAMAXAREACAR 9.678367 LAYER Metal2 ; + PORT + LAYER Metal2 ; + RECT 92.985 0 93.245 0.26 ; + END + END A_BIST_BM[5] + PIN A_DOUT[10] + DIRECTION OUTPUT ; + USE SIGNAL ; + ANTENNAPARTIALMETALAREA 4.8256 LAYER Metal2 ; + ANTENNADIFFAREA 0.988 LAYER Metal2 ; + PORT + LAYER Metal2 ; + RECT 294.93 0 295.19 0.26 ; + END + END A_DOUT[10] + PIN A_DOUT[5] + DIRECTION OUTPUT ; + USE SIGNAL ; + ANTENNAPARTIALMETALAREA 4.8256 LAYER Metal2 ; + ANTENNADIFFAREA 0.988 LAYER Metal2 ; + PORT + LAYER Metal2 ; + RECT 107.42 0 107.68 0.26 ; + END + END A_DOUT[5] + PIN B_DIN[10] + DIRECTION INPUT ; + USE SIGNAL ; + ANTENNAPARTIALMETALAREA 2.925 LAYER Metal2 ; + ANTENNAMODEL OXIDE1 ; + ANTENNAGATEAREA 0.20085 LAYER Metal2 ; + ANTENNAMAXAREACAR 15.469256 LAYER Metal2 ; + PORT + LAYER Metal2 ; + RECT 304.62 0 304.88 0.26 ; + END + END B_DIN[10] + PIN B_DIN[5] + DIRECTION INPUT ; + USE SIGNAL ; + ANTENNAPARTIALMETALAREA 2.925 LAYER Metal2 ; + ANTENNAMODEL OXIDE1 ; + ANTENNAGATEAREA 0.20085 LAYER Metal2 ; + ANTENNAMAXAREACAR 15.469256 LAYER Metal2 ; + PORT + LAYER Metal2 ; + RECT 97.73 0 97.99 0.26 ; + END + END B_DIN[5] + PIN B_BIST_DIN[10] + DIRECTION INPUT ; + USE SIGNAL ; + ANTENNAPARTIALMETALAREA 2.9445 LAYER Metal2 ; + ANTENNAMODEL OXIDE1 ; + ANTENNAGATEAREA 0.20085 LAYER Metal2 ; + ANTENNAMAXAREACAR 15.929052 LAYER Metal2 ; + PORT + LAYER Metal2 ; + RECT 303.09 0 303.35 0.26 ; + END + END B_BIST_DIN[10] + PIN B_BIST_DIN[5] + DIRECTION INPUT ; + USE SIGNAL ; + ANTENNAPARTIALMETALAREA 2.9445 LAYER Metal2 ; + ANTENNAMODEL OXIDE1 ; + ANTENNAGATEAREA 0.20085 LAYER Metal2 ; + ANTENNAMAXAREACAR 15.929052 LAYER Metal2 ; + PORT + LAYER Metal2 ; + RECT 99.26 0 99.52 0.26 ; + END + END B_BIST_DIN[5] + PIN B_BM[10] + DIRECTION INPUT ; + USE SIGNAL ; + ANTENNAPARTIALMETALAREA 0.7007 LAYER Metal2 ; + ANTENNAMODEL OXIDE1 ; + ANTENNAGATEAREA 0.20085 LAYER Metal2 ; + ANTENNAMAXAREACAR 4.394822 LAYER Metal2 ; + PORT + LAYER Metal2 ; + RECT 296.105 0 296.365 0.26 ; + END + END B_BM[10] + PIN B_BM[5] + DIRECTION INPUT ; + USE SIGNAL ; + ANTENNAPARTIALMETALAREA 0.7007 LAYER Metal2 ; + ANTENNAMODEL OXIDE1 ; + ANTENNAGATEAREA 0.20085 LAYER Metal2 ; + ANTENNAMAXAREACAR 4.394822 LAYER Metal2 ; + PORT + LAYER Metal2 ; + RECT 106.245 0 106.505 0.26 ; + END + END B_BM[5] + PIN B_BIST_BM[10] + DIRECTION INPUT ; + USE SIGNAL ; + ANTENNAPARTIALMETALAREA 0.7007 LAYER Metal2 ; + ANTENNAMODEL OXIDE1 ; + ANTENNAGATEAREA 0.20085 LAYER Metal2 ; + ANTENNAMAXAREACAR 4.394822 LAYER Metal2 ; + PORT + LAYER Metal2 ; + RECT 297.635 0 297.895 0.26 ; + END + END B_BIST_BM[10] + PIN B_BIST_BM[5] + DIRECTION INPUT ; + USE SIGNAL ; + ANTENNAPARTIALMETALAREA 0.7007 LAYER Metal2 ; + ANTENNAMODEL OXIDE1 ; + ANTENNAGATEAREA 0.20085 LAYER Metal2 ; + ANTENNAMAXAREACAR 4.394822 LAYER Metal2 ; + PORT + LAYER Metal2 ; + RECT 104.715 0 104.975 0.26 ; + END + END B_BIST_BM[5] + PIN B_DOUT[10] + DIRECTION OUTPUT ; + USE SIGNAL ; + ANTENNAPARTIALMETALAREA 4.836 LAYER Metal2 ; + ANTENNADIFFAREA 0.988 LAYER Metal2 ; + PORT + LAYER Metal2 ; + RECT 311.76 0 312.02 0.26 ; + END + END B_DOUT[10] + PIN B_DOUT[5] + DIRECTION OUTPUT ; + USE SIGNAL ; + ANTENNAPARTIALMETALAREA 4.836 LAYER Metal2 ; + ANTENNADIFFAREA 0.988 LAYER Metal2 ; + PORT + LAYER Metal2 ; + RECT 90.59 0 90.85 0.26 ; + END + END B_DOUT[5] + PIN A_DIN[11] + DIRECTION INPUT ; + USE SIGNAL ; + ANTENNAPARTIALMETALAREA 3.9091 LAYER Metal2 ; + ANTENNAMODEL OXIDE1 ; + ANTENNAGATEAREA 0.20085 LAYER Metal2 ; + ANTENNAMAXAREACAR 20.368932 LAYER Metal2 ; + PORT + LAYER Metal2 ; + RECT 319.75 0 320.01 0.26 ; + END + END A_DIN[11] + PIN A_DIN[4] + DIRECTION INPUT ; + USE SIGNAL ; + ANTENNAPARTIALMETALAREA 3.9091 LAYER Metal2 ; + ANTENNAMODEL OXIDE1 ; + ANTENNAGATEAREA 0.20085 LAYER Metal2 ; + ANTENNAMAXAREACAR 20.368932 LAYER Metal2 ; + PORT + LAYER Metal2 ; + RECT 82.6 0 82.86 0.26 ; + END + END A_DIN[4] + PIN A_BIST_DIN[11] + DIRECTION INPUT ; + USE SIGNAL ; + ANTENNAPARTIALMETALAREA 4.136375 LAYER Metal2 ; + ANTENNAMODEL OXIDE1 ; + ANTENNAGATEAREA 0.20085 LAYER Metal2 ; + ANTENNAMAXAREACAR 21.874907 LAYER Metal2 ; + PORT + LAYER Metal2 ; + RECT 320.26 0 320.52 0.26 ; + END + END A_BIST_DIN[11] + PIN A_BIST_DIN[4] + DIRECTION INPUT ; + USE SIGNAL ; + ANTENNAPARTIALMETALAREA 4.136375 LAYER Metal2 ; + ANTENNAMODEL OXIDE1 ; + ANTENNAGATEAREA 0.20085 LAYER Metal2 ; + ANTENNAMAXAREACAR 21.874907 LAYER Metal2 ; + PORT + LAYER Metal2 ; + RECT 82.09 0 82.35 0.26 ; + END + END A_BIST_DIN[4] + PIN A_BM[11] + DIRECTION INPUT ; + USE SIGNAL ; + ANTENNAPARTIALMETALAREA 1.7264 LAYER Metal2 ; + ANTENNAMODEL OXIDE1 ; + ANTENNAGATEAREA 0.20085 LAYER Metal2 ; + ANTENNAMAXAREACAR 9.501618 LAYER Metal2 ; + PORT + LAYER Metal2 ; + RECT 328.42 0 328.68 0.26 ; + END + END A_BM[11] + PIN A_BM[4] + DIRECTION INPUT ; + USE SIGNAL ; + ANTENNAPARTIALMETALAREA 1.7264 LAYER Metal2 ; + ANTENNAMODEL OXIDE1 ; + ANTENNAGATEAREA 0.20085 LAYER Metal2 ; + ANTENNAMAXAREACAR 9.501618 LAYER Metal2 ; + PORT + LAYER Metal2 ; + RECT 73.93 0 74.19 0.26 ; + END + END A_BM[4] + PIN A_BIST_BM[11] + DIRECTION INPUT ; + USE SIGNAL ; + ANTENNAPARTIALMETALAREA 1.7602 LAYER Metal2 ; + ANTENNAMODEL OXIDE1 ; + ANTENNAGATEAREA 0.20085 LAYER Metal2 ; + ANTENNAMAXAREACAR 9.678367 LAYER Metal2 ; + PORT + LAYER Metal2 ; + RECT 327.045 0 327.305 0.26 ; + END + END A_BIST_BM[11] + PIN A_BIST_BM[4] + DIRECTION INPUT ; + USE SIGNAL ; + ANTENNAPARTIALMETALAREA 1.7602 LAYER Metal2 ; + ANTENNAMODEL OXIDE1 ; + ANTENNAGATEAREA 0.20085 LAYER Metal2 ; + ANTENNAMAXAREACAR 9.678367 LAYER Metal2 ; + PORT + LAYER Metal2 ; + RECT 75.305 0 75.565 0.26 ; + END + END A_BIST_BM[4] + PIN A_DOUT[11] + DIRECTION OUTPUT ; + USE SIGNAL ; + ANTENNAPARTIALMETALAREA 4.8256 LAYER Metal2 ; + ANTENNADIFFAREA 0.988 LAYER Metal2 ; + PORT + LAYER Metal2 ; + RECT 312.61 0 312.87 0.26 ; + END + END A_DOUT[11] + PIN A_DOUT[4] + DIRECTION OUTPUT ; + USE SIGNAL ; + ANTENNAPARTIALMETALAREA 4.8256 LAYER Metal2 ; + ANTENNADIFFAREA 0.988 LAYER Metal2 ; + PORT + LAYER Metal2 ; + RECT 89.74 0 90 0.26 ; + END + END A_DOUT[4] + PIN B_DIN[11] + DIRECTION INPUT ; + USE SIGNAL ; + ANTENNAPARTIALMETALAREA 2.925 LAYER Metal2 ; + ANTENNAMODEL OXIDE1 ; + ANTENNAGATEAREA 0.20085 LAYER Metal2 ; + ANTENNAMAXAREACAR 15.469256 LAYER Metal2 ; + PORT + LAYER Metal2 ; + RECT 322.3 0 322.56 0.26 ; + END + END B_DIN[11] + PIN B_DIN[4] + DIRECTION INPUT ; + USE SIGNAL ; + ANTENNAPARTIALMETALAREA 2.925 LAYER Metal2 ; + ANTENNAMODEL OXIDE1 ; + ANTENNAGATEAREA 0.20085 LAYER Metal2 ; + ANTENNAMAXAREACAR 15.469256 LAYER Metal2 ; + PORT + LAYER Metal2 ; + RECT 80.05 0 80.31 0.26 ; + END + END B_DIN[4] + PIN B_BIST_DIN[11] + DIRECTION INPUT ; + USE SIGNAL ; + ANTENNAPARTIALMETALAREA 2.9445 LAYER Metal2 ; + ANTENNAMODEL OXIDE1 ; + ANTENNAGATEAREA 0.20085 LAYER Metal2 ; + ANTENNAMAXAREACAR 15.929052 LAYER Metal2 ; + PORT + LAYER Metal2 ; + RECT 320.77 0 321.03 0.26 ; + END + END B_BIST_DIN[11] + PIN B_BIST_DIN[4] + DIRECTION INPUT ; + USE SIGNAL ; + ANTENNAPARTIALMETALAREA 2.9445 LAYER Metal2 ; + ANTENNAMODEL OXIDE1 ; + ANTENNAGATEAREA 0.20085 LAYER Metal2 ; + ANTENNAMAXAREACAR 15.929052 LAYER Metal2 ; + PORT + LAYER Metal2 ; + RECT 81.58 0 81.84 0.26 ; + END + END B_BIST_DIN[4] + PIN B_BM[11] + DIRECTION INPUT ; + USE SIGNAL ; + ANTENNAPARTIALMETALAREA 0.7007 LAYER Metal2 ; + ANTENNAMODEL OXIDE1 ; + ANTENNAGATEAREA 0.20085 LAYER Metal2 ; + ANTENNAMAXAREACAR 4.394822 LAYER Metal2 ; + PORT + LAYER Metal2 ; + RECT 313.785 0 314.045 0.26 ; + END + END B_BM[11] + PIN B_BM[4] + DIRECTION INPUT ; + USE SIGNAL ; + ANTENNAPARTIALMETALAREA 0.7007 LAYER Metal2 ; + ANTENNAMODEL OXIDE1 ; + ANTENNAGATEAREA 0.20085 LAYER Metal2 ; + ANTENNAMAXAREACAR 4.394822 LAYER Metal2 ; + PORT + LAYER Metal2 ; + RECT 88.565 0 88.825 0.26 ; + END + END B_BM[4] + PIN B_BIST_BM[11] + DIRECTION INPUT ; + USE SIGNAL ; + ANTENNAPARTIALMETALAREA 0.7007 LAYER Metal2 ; + ANTENNAMODEL OXIDE1 ; + ANTENNAGATEAREA 0.20085 LAYER Metal2 ; + ANTENNAMAXAREACAR 4.394822 LAYER Metal2 ; + PORT + LAYER Metal2 ; + RECT 315.315 0 315.575 0.26 ; + END + END B_BIST_BM[11] + PIN B_BIST_BM[4] + DIRECTION INPUT ; + USE SIGNAL ; + ANTENNAPARTIALMETALAREA 0.7007 LAYER Metal2 ; + ANTENNAMODEL OXIDE1 ; + ANTENNAGATEAREA 0.20085 LAYER Metal2 ; + ANTENNAMAXAREACAR 4.394822 LAYER Metal2 ; + PORT + LAYER Metal2 ; + RECT 87.035 0 87.295 0.26 ; + END + END B_BIST_BM[4] + PIN B_DOUT[11] + DIRECTION OUTPUT ; + USE SIGNAL ; + ANTENNAPARTIALMETALAREA 4.836 LAYER Metal2 ; + ANTENNADIFFAREA 0.988 LAYER Metal2 ; + PORT + LAYER Metal2 ; + RECT 329.44 0 329.7 0.26 ; + END + END B_DOUT[11] + PIN B_DOUT[4] + DIRECTION OUTPUT ; + USE SIGNAL ; + ANTENNAPARTIALMETALAREA 4.836 LAYER Metal2 ; + ANTENNADIFFAREA 0.988 LAYER Metal2 ; + PORT + LAYER Metal2 ; + RECT 72.91 0 73.17 0.26 ; + END + END B_DOUT[4] + PIN A_DIN[12] + DIRECTION INPUT ; + USE SIGNAL ; + ANTENNAPARTIALMETALAREA 3.9091 LAYER Metal2 ; + ANTENNAMODEL OXIDE1 ; + ANTENNAGATEAREA 0.20085 LAYER Metal2 ; + ANTENNAMAXAREACAR 20.368932 LAYER Metal2 ; + PORT + LAYER Metal2 ; + RECT 337.43 0 337.69 0.26 ; + END + END A_DIN[12] + PIN A_DIN[3] + DIRECTION INPUT ; + USE SIGNAL ; + ANTENNAPARTIALMETALAREA 3.9091 LAYER Metal2 ; + ANTENNAMODEL OXIDE1 ; + ANTENNAGATEAREA 0.20085 LAYER Metal2 ; + ANTENNAMAXAREACAR 20.368932 LAYER Metal2 ; + PORT + LAYER Metal2 ; + RECT 64.92 0 65.18 0.26 ; + END + END A_DIN[3] + PIN A_BIST_DIN[12] + DIRECTION INPUT ; + USE SIGNAL ; + ANTENNAPARTIALMETALAREA 4.136375 LAYER Metal2 ; + ANTENNAMODEL OXIDE1 ; + ANTENNAGATEAREA 0.20085 LAYER Metal2 ; + ANTENNAMAXAREACAR 21.874907 LAYER Metal2 ; + PORT + LAYER Metal2 ; + RECT 337.94 0 338.2 0.26 ; + END + END A_BIST_DIN[12] + PIN A_BIST_DIN[3] + DIRECTION INPUT ; + USE SIGNAL ; + ANTENNAPARTIALMETALAREA 4.136375 LAYER Metal2 ; + ANTENNAMODEL OXIDE1 ; + ANTENNAGATEAREA 0.20085 LAYER Metal2 ; + ANTENNAMAXAREACAR 21.874907 LAYER Metal2 ; + PORT + LAYER Metal2 ; + RECT 64.41 0 64.67 0.26 ; + END + END A_BIST_DIN[3] + PIN A_BM[12] + DIRECTION INPUT ; + USE SIGNAL ; + ANTENNAPARTIALMETALAREA 1.7264 LAYER Metal2 ; + ANTENNAMODEL OXIDE1 ; + ANTENNAGATEAREA 0.20085 LAYER Metal2 ; + ANTENNAMAXAREACAR 9.501618 LAYER Metal2 ; + PORT + LAYER Metal2 ; + RECT 346.1 0 346.36 0.26 ; + END + END A_BM[12] + PIN A_BM[3] + DIRECTION INPUT ; + USE SIGNAL ; + ANTENNAPARTIALMETALAREA 1.7264 LAYER Metal2 ; + ANTENNAMODEL OXIDE1 ; + ANTENNAGATEAREA 0.20085 LAYER Metal2 ; + ANTENNAMAXAREACAR 9.501618 LAYER Metal2 ; + PORT + LAYER Metal2 ; + RECT 56.25 0 56.51 0.26 ; + END + END A_BM[3] + PIN A_BIST_BM[12] + DIRECTION INPUT ; + USE SIGNAL ; + ANTENNAPARTIALMETALAREA 1.7602 LAYER Metal2 ; + ANTENNAMODEL OXIDE1 ; + ANTENNAGATEAREA 0.20085 LAYER Metal2 ; + ANTENNAMAXAREACAR 9.678367 LAYER Metal2 ; + PORT + LAYER Metal2 ; + RECT 344.725 0 344.985 0.26 ; + END + END A_BIST_BM[12] + PIN A_BIST_BM[3] + DIRECTION INPUT ; + USE SIGNAL ; + ANTENNAPARTIALMETALAREA 1.7602 LAYER Metal2 ; + ANTENNAMODEL OXIDE1 ; + ANTENNAGATEAREA 0.20085 LAYER Metal2 ; + ANTENNAMAXAREACAR 9.678367 LAYER Metal2 ; + PORT + LAYER Metal2 ; + RECT 57.625 0 57.885 0.26 ; + END + END A_BIST_BM[3] + PIN A_DOUT[12] + DIRECTION OUTPUT ; + USE SIGNAL ; + ANTENNAPARTIALMETALAREA 4.8256 LAYER Metal2 ; + ANTENNADIFFAREA 0.988 LAYER Metal2 ; + PORT + LAYER Metal2 ; + RECT 330.29 0 330.55 0.26 ; + END + END A_DOUT[12] + PIN A_DOUT[3] + DIRECTION OUTPUT ; + USE SIGNAL ; + ANTENNAPARTIALMETALAREA 4.8256 LAYER Metal2 ; + ANTENNADIFFAREA 0.988 LAYER Metal2 ; + PORT + LAYER Metal2 ; + RECT 72.06 0 72.32 0.26 ; + END + END A_DOUT[3] + PIN B_DIN[12] + DIRECTION INPUT ; + USE SIGNAL ; + ANTENNAPARTIALMETALAREA 2.925 LAYER Metal2 ; + ANTENNAMODEL OXIDE1 ; + ANTENNAGATEAREA 0.20085 LAYER Metal2 ; + ANTENNAMAXAREACAR 15.469256 LAYER Metal2 ; + PORT + LAYER Metal2 ; + RECT 339.98 0 340.24 0.26 ; + END + END B_DIN[12] + PIN B_DIN[3] + DIRECTION INPUT ; + USE SIGNAL ; + ANTENNAPARTIALMETALAREA 2.925 LAYER Metal2 ; + ANTENNAMODEL OXIDE1 ; + ANTENNAGATEAREA 0.20085 LAYER Metal2 ; + ANTENNAMAXAREACAR 15.469256 LAYER Metal2 ; + PORT + LAYER Metal2 ; + RECT 62.37 0 62.63 0.26 ; + END + END B_DIN[3] + PIN B_BIST_DIN[12] + DIRECTION INPUT ; + USE SIGNAL ; + ANTENNAPARTIALMETALAREA 2.9445 LAYER Metal2 ; + ANTENNAMODEL OXIDE1 ; + ANTENNAGATEAREA 0.20085 LAYER Metal2 ; + ANTENNAMAXAREACAR 15.929052 LAYER Metal2 ; + PORT + LAYER Metal2 ; + RECT 338.45 0 338.71 0.26 ; + END + END B_BIST_DIN[12] + PIN B_BIST_DIN[3] + DIRECTION INPUT ; + USE SIGNAL ; + ANTENNAPARTIALMETALAREA 2.9445 LAYER Metal2 ; + ANTENNAMODEL OXIDE1 ; + ANTENNAGATEAREA 0.20085 LAYER Metal2 ; + ANTENNAMAXAREACAR 15.929052 LAYER Metal2 ; + PORT + LAYER Metal2 ; + RECT 63.9 0 64.16 0.26 ; + END + END B_BIST_DIN[3] + PIN B_BM[12] + DIRECTION INPUT ; + USE SIGNAL ; + ANTENNAPARTIALMETALAREA 0.7007 LAYER Metal2 ; + ANTENNAMODEL OXIDE1 ; + ANTENNAGATEAREA 0.20085 LAYER Metal2 ; + ANTENNAMAXAREACAR 4.394822 LAYER Metal2 ; + PORT + LAYER Metal2 ; + RECT 331.465 0 331.725 0.26 ; + END + END B_BM[12] + PIN B_BM[3] + DIRECTION INPUT ; + USE SIGNAL ; + ANTENNAPARTIALMETALAREA 0.7007 LAYER Metal2 ; + ANTENNAMODEL OXIDE1 ; + ANTENNAGATEAREA 0.20085 LAYER Metal2 ; + ANTENNAMAXAREACAR 4.394822 LAYER Metal2 ; + PORT + LAYER Metal2 ; + RECT 70.885 0 71.145 0.26 ; + END + END B_BM[3] + PIN B_BIST_BM[12] + DIRECTION INPUT ; + USE SIGNAL ; + ANTENNAPARTIALMETALAREA 0.7007 LAYER Metal2 ; + ANTENNAMODEL OXIDE1 ; + ANTENNAGATEAREA 0.20085 LAYER Metal2 ; + ANTENNAMAXAREACAR 4.394822 LAYER Metal2 ; + PORT + LAYER Metal2 ; + RECT 332.995 0 333.255 0.26 ; + END + END B_BIST_BM[12] + PIN B_BIST_BM[3] + DIRECTION INPUT ; + USE SIGNAL ; + ANTENNAPARTIALMETALAREA 0.7007 LAYER Metal2 ; + ANTENNAMODEL OXIDE1 ; + ANTENNAGATEAREA 0.20085 LAYER Metal2 ; + ANTENNAMAXAREACAR 4.394822 LAYER Metal2 ; + PORT + LAYER Metal2 ; + RECT 69.355 0 69.615 0.26 ; + END + END B_BIST_BM[3] + PIN B_DOUT[12] + DIRECTION OUTPUT ; + USE SIGNAL ; + ANTENNAPARTIALMETALAREA 4.836 LAYER Metal2 ; + ANTENNADIFFAREA 0.988 LAYER Metal2 ; + PORT + LAYER Metal2 ; + RECT 347.12 0 347.38 0.26 ; + END + END B_DOUT[12] + PIN B_DOUT[3] + DIRECTION OUTPUT ; + USE SIGNAL ; + ANTENNAPARTIALMETALAREA 4.836 LAYER Metal2 ; + ANTENNADIFFAREA 0.988 LAYER Metal2 ; + PORT + LAYER Metal2 ; + RECT 55.23 0 55.49 0.26 ; + END + END B_DOUT[3] + PIN A_DIN[13] + DIRECTION INPUT ; + USE SIGNAL ; + ANTENNAPARTIALMETALAREA 3.9091 LAYER Metal2 ; + ANTENNAMODEL OXIDE1 ; + ANTENNAGATEAREA 0.20085 LAYER Metal2 ; + ANTENNAMAXAREACAR 20.368932 LAYER Metal2 ; + PORT + LAYER Metal2 ; + RECT 355.11 0 355.37 0.26 ; + END + END A_DIN[13] + PIN A_DIN[2] + DIRECTION INPUT ; + USE SIGNAL ; + ANTENNAPARTIALMETALAREA 3.9091 LAYER Metal2 ; + ANTENNAMODEL OXIDE1 ; + ANTENNAGATEAREA 0.20085 LAYER Metal2 ; + ANTENNAMAXAREACAR 20.368932 LAYER Metal2 ; + PORT + LAYER Metal2 ; + RECT 47.24 0 47.5 0.26 ; + END + END A_DIN[2] + PIN A_BIST_DIN[13] + DIRECTION INPUT ; + USE SIGNAL ; + ANTENNAPARTIALMETALAREA 4.136375 LAYER Metal2 ; + ANTENNAMODEL OXIDE1 ; + ANTENNAGATEAREA 0.20085 LAYER Metal2 ; + ANTENNAMAXAREACAR 21.874907 LAYER Metal2 ; + PORT + LAYER Metal2 ; + RECT 355.62 0 355.88 0.26 ; + END + END A_BIST_DIN[13] + PIN A_BIST_DIN[2] + DIRECTION INPUT ; + USE SIGNAL ; + ANTENNAPARTIALMETALAREA 4.136375 LAYER Metal2 ; + ANTENNAMODEL OXIDE1 ; + ANTENNAGATEAREA 0.20085 LAYER Metal2 ; + ANTENNAMAXAREACAR 21.874907 LAYER Metal2 ; + PORT + LAYER Metal2 ; + RECT 46.73 0 46.99 0.26 ; + END + END A_BIST_DIN[2] + PIN A_BM[13] + DIRECTION INPUT ; + USE SIGNAL ; + ANTENNAPARTIALMETALAREA 1.7264 LAYER Metal2 ; + ANTENNAMODEL OXIDE1 ; + ANTENNAGATEAREA 0.20085 LAYER Metal2 ; + ANTENNAMAXAREACAR 9.501618 LAYER Metal2 ; + PORT + LAYER Metal2 ; + RECT 363.78 0 364.04 0.26 ; + END + END A_BM[13] + PIN A_BM[2] + DIRECTION INPUT ; + USE SIGNAL ; + ANTENNAPARTIALMETALAREA 1.7264 LAYER Metal2 ; + ANTENNAMODEL OXIDE1 ; + ANTENNAGATEAREA 0.20085 LAYER Metal2 ; + ANTENNAMAXAREACAR 9.501618 LAYER Metal2 ; + PORT + LAYER Metal2 ; + RECT 38.57 0 38.83 0.26 ; + END + END A_BM[2] + PIN A_BIST_BM[13] + DIRECTION INPUT ; + USE SIGNAL ; + ANTENNAPARTIALMETALAREA 1.7602 LAYER Metal2 ; + ANTENNAMODEL OXIDE1 ; + ANTENNAGATEAREA 0.20085 LAYER Metal2 ; + ANTENNAMAXAREACAR 9.678367 LAYER Metal2 ; + PORT + LAYER Metal2 ; + RECT 362.405 0 362.665 0.26 ; + END + END A_BIST_BM[13] + PIN A_BIST_BM[2] + DIRECTION INPUT ; + USE SIGNAL ; + ANTENNAPARTIALMETALAREA 1.7602 LAYER Metal2 ; + ANTENNAMODEL OXIDE1 ; + ANTENNAGATEAREA 0.20085 LAYER Metal2 ; + ANTENNAMAXAREACAR 9.678367 LAYER Metal2 ; + PORT + LAYER Metal2 ; + RECT 39.945 0 40.205 0.26 ; + END + END A_BIST_BM[2] + PIN A_DOUT[13] + DIRECTION OUTPUT ; + USE SIGNAL ; + ANTENNAPARTIALMETALAREA 4.8256 LAYER Metal2 ; + ANTENNADIFFAREA 0.988 LAYER Metal2 ; + PORT + LAYER Metal2 ; + RECT 347.97 0 348.23 0.26 ; + END + END A_DOUT[13] + PIN A_DOUT[2] + DIRECTION OUTPUT ; + USE SIGNAL ; + ANTENNAPARTIALMETALAREA 4.8256 LAYER Metal2 ; + ANTENNADIFFAREA 0.988 LAYER Metal2 ; + PORT + LAYER Metal2 ; + RECT 54.38 0 54.64 0.26 ; + END + END A_DOUT[2] + PIN B_DIN[13] + DIRECTION INPUT ; + USE SIGNAL ; + ANTENNAPARTIALMETALAREA 2.925 LAYER Metal2 ; + ANTENNAMODEL OXIDE1 ; + ANTENNAGATEAREA 0.20085 LAYER Metal2 ; + ANTENNAMAXAREACAR 15.469256 LAYER Metal2 ; + PORT + LAYER Metal2 ; + RECT 357.66 0 357.92 0.26 ; + END + END B_DIN[13] + PIN B_DIN[2] + DIRECTION INPUT ; + USE SIGNAL ; + ANTENNAPARTIALMETALAREA 2.925 LAYER Metal2 ; + ANTENNAMODEL OXIDE1 ; + ANTENNAGATEAREA 0.20085 LAYER Metal2 ; + ANTENNAMAXAREACAR 15.469256 LAYER Metal2 ; + PORT + LAYER Metal2 ; + RECT 44.69 0 44.95 0.26 ; + END + END B_DIN[2] + PIN B_BIST_DIN[13] + DIRECTION INPUT ; + USE SIGNAL ; + ANTENNAPARTIALMETALAREA 2.9445 LAYER Metal2 ; + ANTENNAMODEL OXIDE1 ; + ANTENNAGATEAREA 0.20085 LAYER Metal2 ; + ANTENNAMAXAREACAR 15.929052 LAYER Metal2 ; + PORT + LAYER Metal2 ; + RECT 356.13 0 356.39 0.26 ; + END + END B_BIST_DIN[13] + PIN B_BIST_DIN[2] + DIRECTION INPUT ; + USE SIGNAL ; + ANTENNAPARTIALMETALAREA 2.9445 LAYER Metal2 ; + ANTENNAMODEL OXIDE1 ; + ANTENNAGATEAREA 0.20085 LAYER Metal2 ; + ANTENNAMAXAREACAR 15.929052 LAYER Metal2 ; + PORT + LAYER Metal2 ; + RECT 46.22 0 46.48 0.26 ; + END + END B_BIST_DIN[2] + PIN B_BM[13] + DIRECTION INPUT ; + USE SIGNAL ; + ANTENNAPARTIALMETALAREA 0.7007 LAYER Metal2 ; + ANTENNAMODEL OXIDE1 ; + ANTENNAGATEAREA 0.20085 LAYER Metal2 ; + ANTENNAMAXAREACAR 4.394822 LAYER Metal2 ; + PORT + LAYER Metal2 ; + RECT 349.145 0 349.405 0.26 ; + END + END B_BM[13] + PIN B_BM[2] + DIRECTION INPUT ; + USE SIGNAL ; + ANTENNAPARTIALMETALAREA 0.7007 LAYER Metal2 ; + ANTENNAMODEL OXIDE1 ; + ANTENNAGATEAREA 0.20085 LAYER Metal2 ; + ANTENNAMAXAREACAR 4.394822 LAYER Metal2 ; + PORT + LAYER Metal2 ; + RECT 53.205 0 53.465 0.26 ; + END + END B_BM[2] + PIN B_BIST_BM[13] + DIRECTION INPUT ; + USE SIGNAL ; + ANTENNAPARTIALMETALAREA 0.7007 LAYER Metal2 ; + ANTENNAMODEL OXIDE1 ; + ANTENNAGATEAREA 0.20085 LAYER Metal2 ; + ANTENNAMAXAREACAR 4.394822 LAYER Metal2 ; + PORT + LAYER Metal2 ; + RECT 350.675 0 350.935 0.26 ; + END + END B_BIST_BM[13] + PIN B_BIST_BM[2] + DIRECTION INPUT ; + USE SIGNAL ; + ANTENNAPARTIALMETALAREA 0.7007 LAYER Metal2 ; + ANTENNAMODEL OXIDE1 ; + ANTENNAGATEAREA 0.20085 LAYER Metal2 ; + ANTENNAMAXAREACAR 4.394822 LAYER Metal2 ; + PORT + LAYER Metal2 ; + RECT 51.675 0 51.935 0.26 ; + END + END B_BIST_BM[2] + PIN B_DOUT[13] + DIRECTION OUTPUT ; + USE SIGNAL ; + ANTENNAPARTIALMETALAREA 4.836 LAYER Metal2 ; + ANTENNADIFFAREA 0.988 LAYER Metal2 ; + PORT + LAYER Metal2 ; + RECT 364.8 0 365.06 0.26 ; + END + END B_DOUT[13] + PIN B_DOUT[2] + DIRECTION OUTPUT ; + USE SIGNAL ; + ANTENNAPARTIALMETALAREA 4.836 LAYER Metal2 ; + ANTENNADIFFAREA 0.988 LAYER Metal2 ; + PORT + LAYER Metal2 ; + RECT 37.55 0 37.81 0.26 ; + END + END B_DOUT[2] + PIN A_DIN[14] + DIRECTION INPUT ; + USE SIGNAL ; + ANTENNAPARTIALMETALAREA 3.9091 LAYER Metal2 ; + ANTENNAMODEL OXIDE1 ; + ANTENNAGATEAREA 0.20085 LAYER Metal2 ; + ANTENNAMAXAREACAR 20.368932 LAYER Metal2 ; + PORT + LAYER Metal2 ; + RECT 372.79 0 373.05 0.26 ; + END + END A_DIN[14] + PIN A_DIN[1] + DIRECTION INPUT ; + USE SIGNAL ; + ANTENNAPARTIALMETALAREA 3.9091 LAYER Metal2 ; + ANTENNAMODEL OXIDE1 ; + ANTENNAGATEAREA 0.20085 LAYER Metal2 ; + ANTENNAMAXAREACAR 20.368932 LAYER Metal2 ; + PORT + LAYER Metal2 ; + RECT 29.56 0 29.82 0.26 ; + END + END A_DIN[1] + PIN A_BIST_DIN[14] + DIRECTION INPUT ; + USE SIGNAL ; + ANTENNAPARTIALMETALAREA 4.136375 LAYER Metal2 ; + ANTENNAMODEL OXIDE1 ; + ANTENNAGATEAREA 0.20085 LAYER Metal2 ; + ANTENNAMAXAREACAR 21.874907 LAYER Metal2 ; + PORT + LAYER Metal2 ; + RECT 373.3 0 373.56 0.26 ; + END + END A_BIST_DIN[14] + PIN A_BIST_DIN[1] + DIRECTION INPUT ; + USE SIGNAL ; + ANTENNAPARTIALMETALAREA 4.136375 LAYER Metal2 ; + ANTENNAMODEL OXIDE1 ; + ANTENNAGATEAREA 0.20085 LAYER Metal2 ; + ANTENNAMAXAREACAR 21.874907 LAYER Metal2 ; + PORT + LAYER Metal2 ; + RECT 29.05 0 29.31 0.26 ; + END + END A_BIST_DIN[1] + PIN A_BM[14] + DIRECTION INPUT ; + USE SIGNAL ; + ANTENNAPARTIALMETALAREA 1.7264 LAYER Metal2 ; + ANTENNAMODEL OXIDE1 ; + ANTENNAGATEAREA 0.20085 LAYER Metal2 ; + ANTENNAMAXAREACAR 9.501618 LAYER Metal2 ; + PORT + LAYER Metal2 ; + RECT 381.46 0 381.72 0.26 ; + END + END A_BM[14] + PIN A_BM[1] + DIRECTION INPUT ; + USE SIGNAL ; + ANTENNAPARTIALMETALAREA 1.7264 LAYER Metal2 ; + ANTENNAMODEL OXIDE1 ; + ANTENNAGATEAREA 0.20085 LAYER Metal2 ; + ANTENNAMAXAREACAR 9.501618 LAYER Metal2 ; + PORT + LAYER Metal2 ; + RECT 20.89 0 21.15 0.26 ; + END + END A_BM[1] + PIN A_BIST_BM[14] + DIRECTION INPUT ; + USE SIGNAL ; + ANTENNAPARTIALMETALAREA 1.7602 LAYER Metal2 ; + ANTENNAMODEL OXIDE1 ; + ANTENNAGATEAREA 0.20085 LAYER Metal2 ; + ANTENNAMAXAREACAR 9.678367 LAYER Metal2 ; + PORT + LAYER Metal2 ; + RECT 380.085 0 380.345 0.26 ; + END + END A_BIST_BM[14] + PIN A_BIST_BM[1] + DIRECTION INPUT ; + USE SIGNAL ; + ANTENNAPARTIALMETALAREA 1.7602 LAYER Metal2 ; + ANTENNAMODEL OXIDE1 ; + ANTENNAGATEAREA 0.20085 LAYER Metal2 ; + ANTENNAMAXAREACAR 9.678367 LAYER Metal2 ; + PORT + LAYER Metal2 ; + RECT 22.265 0 22.525 0.26 ; + END + END A_BIST_BM[1] + PIN A_DOUT[14] + DIRECTION OUTPUT ; + USE SIGNAL ; + ANTENNAPARTIALMETALAREA 4.8256 LAYER Metal2 ; + ANTENNADIFFAREA 0.988 LAYER Metal2 ; + PORT + LAYER Metal2 ; + RECT 365.65 0 365.91 0.26 ; + END + END A_DOUT[14] + PIN A_DOUT[1] + DIRECTION OUTPUT ; + USE SIGNAL ; + ANTENNAPARTIALMETALAREA 4.8256 LAYER Metal2 ; + ANTENNADIFFAREA 0.988 LAYER Metal2 ; + PORT + LAYER Metal2 ; + RECT 36.7 0 36.96 0.26 ; + END + END A_DOUT[1] + PIN B_DIN[14] + DIRECTION INPUT ; + USE SIGNAL ; + ANTENNAPARTIALMETALAREA 2.925 LAYER Metal2 ; + ANTENNAMODEL OXIDE1 ; + ANTENNAGATEAREA 0.20085 LAYER Metal2 ; + ANTENNAMAXAREACAR 15.469256 LAYER Metal2 ; + PORT + LAYER Metal2 ; + RECT 375.34 0 375.6 0.26 ; + END + END B_DIN[14] + PIN B_DIN[1] + DIRECTION INPUT ; + USE SIGNAL ; + ANTENNAPARTIALMETALAREA 2.925 LAYER Metal2 ; + ANTENNAMODEL OXIDE1 ; + ANTENNAGATEAREA 0.20085 LAYER Metal2 ; + ANTENNAMAXAREACAR 15.469256 LAYER Metal2 ; + PORT + LAYER Metal2 ; + RECT 27.01 0 27.27 0.26 ; + END + END B_DIN[1] + PIN B_BIST_DIN[14] + DIRECTION INPUT ; + USE SIGNAL ; + ANTENNAPARTIALMETALAREA 2.9445 LAYER Metal2 ; + ANTENNAMODEL OXIDE1 ; + ANTENNAGATEAREA 0.20085 LAYER Metal2 ; + ANTENNAMAXAREACAR 15.929052 LAYER Metal2 ; + PORT + LAYER Metal2 ; + RECT 373.81 0 374.07 0.26 ; + END + END B_BIST_DIN[14] + PIN B_BIST_DIN[1] + DIRECTION INPUT ; + USE SIGNAL ; + ANTENNAPARTIALMETALAREA 2.9445 LAYER Metal2 ; + ANTENNAMODEL OXIDE1 ; + ANTENNAGATEAREA 0.20085 LAYER Metal2 ; + ANTENNAMAXAREACAR 15.929052 LAYER Metal2 ; + PORT + LAYER Metal2 ; + RECT 28.54 0 28.8 0.26 ; + END + END B_BIST_DIN[1] + PIN B_BM[14] + DIRECTION INPUT ; + USE SIGNAL ; + ANTENNAPARTIALMETALAREA 0.7007 LAYER Metal2 ; + ANTENNAMODEL OXIDE1 ; + ANTENNAGATEAREA 0.20085 LAYER Metal2 ; + ANTENNAMAXAREACAR 4.394822 LAYER Metal2 ; + PORT + LAYER Metal2 ; + RECT 366.825 0 367.085 0.26 ; + END + END B_BM[14] + PIN B_BM[1] + DIRECTION INPUT ; + USE SIGNAL ; + ANTENNAPARTIALMETALAREA 0.7007 LAYER Metal2 ; + ANTENNAMODEL OXIDE1 ; + ANTENNAGATEAREA 0.20085 LAYER Metal2 ; + ANTENNAMAXAREACAR 4.394822 LAYER Metal2 ; + PORT + LAYER Metal2 ; + RECT 35.525 0 35.785 0.26 ; + END + END B_BM[1] + PIN B_BIST_BM[14] + DIRECTION INPUT ; + USE SIGNAL ; + ANTENNAPARTIALMETALAREA 0.7007 LAYER Metal2 ; + ANTENNAMODEL OXIDE1 ; + ANTENNAGATEAREA 0.20085 LAYER Metal2 ; + ANTENNAMAXAREACAR 4.394822 LAYER Metal2 ; + PORT + LAYER Metal2 ; + RECT 368.355 0 368.615 0.26 ; + END + END B_BIST_BM[14] + PIN B_BIST_BM[1] + DIRECTION INPUT ; + USE SIGNAL ; + ANTENNAPARTIALMETALAREA 0.7007 LAYER Metal2 ; + ANTENNAMODEL OXIDE1 ; + ANTENNAGATEAREA 0.20085 LAYER Metal2 ; + ANTENNAMAXAREACAR 4.394822 LAYER Metal2 ; + PORT + LAYER Metal2 ; + RECT 33.995 0 34.255 0.26 ; + END + END B_BIST_BM[1] + PIN B_DOUT[14] + DIRECTION OUTPUT ; + USE SIGNAL ; + ANTENNAPARTIALMETALAREA 4.836 LAYER Metal2 ; + ANTENNADIFFAREA 0.988 LAYER Metal2 ; + PORT + LAYER Metal2 ; + RECT 382.48 0 382.74 0.26 ; + END + END B_DOUT[14] + PIN B_DOUT[1] + DIRECTION OUTPUT ; + USE SIGNAL ; + ANTENNAPARTIALMETALAREA 4.836 LAYER Metal2 ; + ANTENNADIFFAREA 0.988 LAYER Metal2 ; + PORT + LAYER Metal2 ; + RECT 19.87 0 20.13 0.26 ; + END + END B_DOUT[1] + PIN A_DIN[15] + DIRECTION INPUT ; + USE SIGNAL ; + ANTENNAPARTIALMETALAREA 3.9091 LAYER Metal2 ; + ANTENNAMODEL OXIDE1 ; + ANTENNAGATEAREA 0.20085 LAYER Metal2 ; + ANTENNAMAXAREACAR 20.368932 LAYER Metal2 ; + PORT + LAYER Metal2 ; + RECT 390.47 0 390.73 0.26 ; + END + END A_DIN[15] + PIN A_DIN[0] + DIRECTION INPUT ; + USE SIGNAL ; + ANTENNAPARTIALMETALAREA 3.9091 LAYER Metal2 ; + ANTENNAMODEL OXIDE1 ; + ANTENNAGATEAREA 0.20085 LAYER Metal2 ; + ANTENNAMAXAREACAR 20.368932 LAYER Metal2 ; + PORT + LAYER Metal2 ; + RECT 11.88 0 12.14 0.26 ; + END + END A_DIN[0] + PIN A_BIST_DIN[15] + DIRECTION INPUT ; + USE SIGNAL ; + ANTENNAPARTIALMETALAREA 4.136375 LAYER Metal2 ; + ANTENNAMODEL OXIDE1 ; + ANTENNAGATEAREA 0.20085 LAYER Metal2 ; + ANTENNAMAXAREACAR 21.874907 LAYER Metal2 ; + PORT + LAYER Metal2 ; + RECT 390.98 0 391.24 0.26 ; + END + END A_BIST_DIN[15] + PIN A_BIST_DIN[0] + DIRECTION INPUT ; + USE SIGNAL ; + ANTENNAPARTIALMETALAREA 4.136375 LAYER Metal2 ; + ANTENNAMODEL OXIDE1 ; + ANTENNAGATEAREA 0.20085 LAYER Metal2 ; + ANTENNAMAXAREACAR 21.874907 LAYER Metal2 ; + PORT + LAYER Metal2 ; + RECT 11.37 0 11.63 0.26 ; + END + END A_BIST_DIN[0] + PIN A_BM[15] + DIRECTION INPUT ; + USE SIGNAL ; + ANTENNAPARTIALMETALAREA 1.7264 LAYER Metal2 ; + ANTENNAMODEL OXIDE1 ; + ANTENNAGATEAREA 0.20085 LAYER Metal2 ; + ANTENNAMAXAREACAR 9.501618 LAYER Metal2 ; + PORT + LAYER Metal2 ; + RECT 399.14 0 399.4 0.26 ; + END + END A_BM[15] + PIN A_BM[0] + DIRECTION INPUT ; + USE SIGNAL ; + ANTENNAPARTIALMETALAREA 1.7264 LAYER Metal2 ; + ANTENNAMODEL OXIDE1 ; + ANTENNAGATEAREA 0.20085 LAYER Metal2 ; + ANTENNAMAXAREACAR 9.501618 LAYER Metal2 ; + PORT + LAYER Metal2 ; + RECT 3.21 0 3.47 0.26 ; + END + END A_BM[0] + PIN A_BIST_BM[15] + DIRECTION INPUT ; + USE SIGNAL ; + ANTENNAPARTIALMETALAREA 1.7602 LAYER Metal2 ; + ANTENNAMODEL OXIDE1 ; + ANTENNAGATEAREA 0.20085 LAYER Metal2 ; + ANTENNAMAXAREACAR 9.678367 LAYER Metal2 ; + PORT + LAYER Metal2 ; + RECT 397.765 0 398.025 0.26 ; + END + END A_BIST_BM[15] + PIN A_BIST_BM[0] + DIRECTION INPUT ; + USE SIGNAL ; + ANTENNAPARTIALMETALAREA 1.7602 LAYER Metal2 ; + ANTENNAMODEL OXIDE1 ; + ANTENNAGATEAREA 0.20085 LAYER Metal2 ; + ANTENNAMAXAREACAR 9.678367 LAYER Metal2 ; + PORT + LAYER Metal2 ; + RECT 4.585 0 4.845 0.26 ; + END + END A_BIST_BM[0] + PIN A_DOUT[15] + DIRECTION OUTPUT ; + USE SIGNAL ; + ANTENNAPARTIALMETALAREA 4.8256 LAYER Metal2 ; + ANTENNADIFFAREA 0.988 LAYER Metal2 ; + PORT + LAYER Metal2 ; + RECT 383.33 0 383.59 0.26 ; + END + END A_DOUT[15] + PIN A_DOUT[0] + DIRECTION OUTPUT ; + USE SIGNAL ; + ANTENNAPARTIALMETALAREA 4.8256 LAYER Metal2 ; + ANTENNADIFFAREA 0.988 LAYER Metal2 ; + PORT + LAYER Metal2 ; + RECT 19.02 0 19.28 0.26 ; + END + END A_DOUT[0] + PIN B_DIN[15] + DIRECTION INPUT ; + USE SIGNAL ; + ANTENNAPARTIALMETALAREA 2.925 LAYER Metal2 ; + ANTENNAMODEL OXIDE1 ; + ANTENNAGATEAREA 0.20085 LAYER Metal2 ; + ANTENNAMAXAREACAR 15.469256 LAYER Metal2 ; + PORT + LAYER Metal2 ; + RECT 393.02 0 393.28 0.26 ; + END + END B_DIN[15] + PIN B_DIN[0] + DIRECTION INPUT ; + USE SIGNAL ; + ANTENNAPARTIALMETALAREA 2.925 LAYER Metal2 ; + ANTENNAMODEL OXIDE1 ; + ANTENNAGATEAREA 0.20085 LAYER Metal2 ; + ANTENNAMAXAREACAR 15.469256 LAYER Metal2 ; + PORT + LAYER Metal2 ; + RECT 9.33 0 9.59 0.26 ; + END + END B_DIN[0] + PIN B_BIST_DIN[15] + DIRECTION INPUT ; + USE SIGNAL ; + ANTENNAPARTIALMETALAREA 2.9445 LAYER Metal2 ; + ANTENNAMODEL OXIDE1 ; + ANTENNAGATEAREA 0.20085 LAYER Metal2 ; + ANTENNAMAXAREACAR 15.929052 LAYER Metal2 ; + PORT + LAYER Metal2 ; + RECT 391.49 0 391.75 0.26 ; + END + END B_BIST_DIN[15] + PIN B_BIST_DIN[0] + DIRECTION INPUT ; + USE SIGNAL ; + ANTENNAPARTIALMETALAREA 2.9445 LAYER Metal2 ; + ANTENNAMODEL OXIDE1 ; + ANTENNAGATEAREA 0.20085 LAYER Metal2 ; + ANTENNAMAXAREACAR 15.929052 LAYER Metal2 ; + PORT + LAYER Metal2 ; + RECT 10.86 0 11.12 0.26 ; + END + END B_BIST_DIN[0] + PIN B_BM[15] + DIRECTION INPUT ; + USE SIGNAL ; + ANTENNAPARTIALMETALAREA 0.7007 LAYER Metal2 ; + ANTENNAMODEL OXIDE1 ; + ANTENNAGATEAREA 0.20085 LAYER Metal2 ; + ANTENNAMAXAREACAR 4.394822 LAYER Metal2 ; + PORT + LAYER Metal2 ; + RECT 384.505 0 384.765 0.26 ; + END + END B_BM[15] + PIN B_BM[0] + DIRECTION INPUT ; + USE SIGNAL ; + ANTENNAPARTIALMETALAREA 0.7007 LAYER Metal2 ; + ANTENNAMODEL OXIDE1 ; + ANTENNAGATEAREA 0.20085 LAYER Metal2 ; + ANTENNAMAXAREACAR 4.394822 LAYER Metal2 ; + PORT + LAYER Metal2 ; + RECT 17.845 0 18.105 0.26 ; + END + END B_BM[0] + PIN B_BIST_BM[15] + DIRECTION INPUT ; + USE SIGNAL ; + ANTENNAPARTIALMETALAREA 0.7007 LAYER Metal2 ; + ANTENNAMODEL OXIDE1 ; + ANTENNAGATEAREA 0.20085 LAYER Metal2 ; + ANTENNAMAXAREACAR 4.394822 LAYER Metal2 ; + PORT + LAYER Metal2 ; + RECT 386.035 0 386.295 0.26 ; + END + END B_BIST_BM[15] + PIN B_BIST_BM[0] + DIRECTION INPUT ; + USE SIGNAL ; + ANTENNAPARTIALMETALAREA 0.7007 LAYER Metal2 ; + ANTENNAMODEL OXIDE1 ; + ANTENNAGATEAREA 0.20085 LAYER Metal2 ; + ANTENNAMAXAREACAR 4.394822 LAYER Metal2 ; + PORT + LAYER Metal2 ; + RECT 16.315 0 16.575 0.26 ; + END + END B_BIST_BM[0] + PIN B_DOUT[15] + DIRECTION OUTPUT ; + USE SIGNAL ; + ANTENNAPARTIALMETALAREA 4.836 LAYER Metal2 ; + ANTENNADIFFAREA 0.988 LAYER Metal2 ; + PORT + LAYER Metal2 ; + RECT 400.16 0 400.42 0.26 ; + END + END B_DOUT[15] + PIN B_DOUT[0] + DIRECTION OUTPUT ; + USE SIGNAL ; + ANTENNAPARTIALMETALAREA 4.836 LAYER Metal2 ; + ANTENNADIFFAREA 0.988 LAYER Metal2 ; + PORT + LAYER Metal2 ; + RECT 2.19 0 2.45 0.26 ; + END + END B_DOUT[0] + PIN A_ADDR[0] + DIRECTION INPUT ; + USE SIGNAL ; + ANTENNAPARTIALMETALAREA 8.7685 LAYER Metal2 ; + ANTENNAMODEL OXIDE1 ; + ANTENNAGATEAREA 0.20085 LAYER Metal2 ; + ANTENNAMAXAREACAR 44.563107 LAYER Metal2 ; + PORT + LAYER Metal2 ; + RECT 217.395 0 217.655 0.26 ; + END + END A_ADDR[0] + PIN A_BIST_ADDR[0] + DIRECTION INPUT ; + USE SIGNAL ; + ANTENNAPARTIALMETALAREA 9.8293 LAYER Metal2 ; + ANTENNAMODEL OXIDE1 ; + ANTENNAGATEAREA 0.20085 LAYER Metal2 ; + ANTENNAMAXAREACAR 49.84466 LAYER Metal2 ; + PORT + LAYER Metal2 ; + RECT 223.005 0 223.265 0.26 ; + END + END A_BIST_ADDR[0] + PIN B_ADDR[0] + DIRECTION INPUT ; + USE SIGNAL ; + ANTENNAPARTIALMETALAREA 8.7685 LAYER Metal2 ; + ANTENNAMODEL OXIDE1 ; + ANTENNAGATEAREA 0.20085 LAYER Metal2 ; + ANTENNAMAXAREACAR 44.563107 LAYER Metal2 ; + PORT + LAYER Metal2 ; + RECT 184.955 0 185.215 0.26 ; + END + END B_ADDR[0] + PIN B_BIST_ADDR[0] + DIRECTION INPUT ; + USE SIGNAL ; + ANTENNAPARTIALMETALAREA 9.8293 LAYER Metal2 ; + ANTENNAMODEL OXIDE1 ; + ANTENNAGATEAREA 0.20085 LAYER Metal2 ; + ANTENNAMAXAREACAR 49.84466 LAYER Metal2 ; + PORT + LAYER Metal2 ; + RECT 179.345 0 179.605 0.26 ; + END + END B_BIST_ADDR[0] + PIN A_ADDR[1] + DIRECTION INPUT ; + USE SIGNAL ; + ANTENNAPARTIALMETALAREA 11.0851 LAYER Metal2 ; + ANTENNAMODEL OXIDE1 ; + ANTENNAGATEAREA 0.20085 LAYER Metal2 ; + ANTENNAMAXAREACAR 56.097087 LAYER Metal2 ; + PORT + LAYER Metal2 ; + RECT 217.905 0 218.165 0.26 ; + END + END A_ADDR[1] + PIN A_BIST_ADDR[1] + DIRECTION INPUT ; + USE SIGNAL ; + ANTENNAPARTIALMETALAREA 12.1459 LAYER Metal2 ; + ANTENNAMODEL OXIDE1 ; + ANTENNAGATEAREA 0.20085 LAYER Metal2 ; + ANTENNAMAXAREACAR 61.378641 LAYER Metal2 ; + PORT + LAYER Metal2 ; + RECT 223.515 0 223.775 0.26 ; + END + END A_BIST_ADDR[1] + PIN B_ADDR[1] + DIRECTION INPUT ; + USE SIGNAL ; + ANTENNAPARTIALMETALAREA 11.0851 LAYER Metal2 ; + ANTENNAMODEL OXIDE1 ; + ANTENNAGATEAREA 0.20085 LAYER Metal2 ; + ANTENNAMAXAREACAR 56.097087 LAYER Metal2 ; + PORT + LAYER Metal2 ; + RECT 184.445 0 184.705 0.26 ; + END + END B_ADDR[1] + PIN B_BIST_ADDR[1] + DIRECTION INPUT ; + USE SIGNAL ; + ANTENNAPARTIALMETALAREA 12.1459 LAYER Metal2 ; + ANTENNAMODEL OXIDE1 ; + ANTENNAGATEAREA 0.20085 LAYER Metal2 ; + ANTENNAMAXAREACAR 61.378641 LAYER Metal2 ; + PORT + LAYER Metal2 ; + RECT 178.835 0 179.095 0.26 ; + END + END B_BIST_ADDR[1] + PIN A_ADDR[2] + DIRECTION INPUT ; + USE SIGNAL ; + ANTENNAPARTIALMETALAREA 13.0819 LAYER Metal2 ; + ANTENNAPARTIALMETALAREA 1.5246 LAYER Metal3 ; + ANTENNAPARTIALCUTAREA 0.0722 LAYER Via2 ; + ANTENNAMODEL OXIDE1 ; + ANTENNAGATEAREA 0.20085 LAYER Metal3 ; + ANTENNAMAXAREACAR 9.415982 LAYER Metal3 ; + PORT + LAYER Metal2 ; + RECT 226.575 0 226.835 0.26 ; + END + END A_ADDR[2] + PIN A_BIST_ADDR[2] + DIRECTION INPUT ; + USE SIGNAL ; + ANTENNAPARTIALMETALAREA 13.0819 LAYER Metal2 ; + ANTENNAPARTIALMETALAREA 1.0962 LAYER Metal3 ; + ANTENNAPARTIALCUTAREA 0.0722 LAYER Via2 ; + ANTENNAMODEL OXIDE1 ; + ANTENNAGATEAREA 0.20085 LAYER Metal3 ; + ANTENNAMAXAREACAR 7.813791 LAYER Metal3 ; + PORT + LAYER Metal2 ; + RECT 227.085 0 227.345 0.26 ; + END + END A_BIST_ADDR[2] + PIN B_ADDR[2] + DIRECTION INPUT ; + USE SIGNAL ; + ANTENNAPARTIALMETALAREA 13.0819 LAYER Metal2 ; + ANTENNAPARTIALMETALAREA 1.5246 LAYER Metal3 ; + ANTENNAPARTIALCUTAREA 0.0722 LAYER Via2 ; + ANTENNAMODEL OXIDE1 ; + ANTENNAGATEAREA 0.20085 LAYER Metal3 ; + ANTENNAMAXAREACAR 9.415982 LAYER Metal3 ; + PORT + LAYER Metal2 ; + RECT 175.775 0 176.035 0.26 ; + END + END B_ADDR[2] + PIN B_BIST_ADDR[2] + DIRECTION INPUT ; + USE SIGNAL ; + ANTENNAPARTIALMETALAREA 13.0819 LAYER Metal2 ; + ANTENNAPARTIALMETALAREA 1.0962 LAYER Metal3 ; + ANTENNAPARTIALCUTAREA 0.0722 LAYER Via2 ; + ANTENNAMODEL OXIDE1 ; + ANTENNAGATEAREA 0.20085 LAYER Metal3 ; + ANTENNAMAXAREACAR 7.813791 LAYER Metal3 ; + PORT + LAYER Metal2 ; + RECT 175.265 0 175.525 0.26 ; + END + END B_BIST_ADDR[2] + PIN A_ADDR[3] + DIRECTION INPUT ; + USE SIGNAL ; + ANTENNAPARTIALMETALAREA 13.0819 LAYER Metal2 ; + ANTENNAPARTIALMETALAREA 3.9459 LAYER Metal3 ; + ANTENNAPARTIALCUTAREA 0.0722 LAYER Via2 ; + ANTENNAMODEL OXIDE1 ; + ANTENNAGATEAREA 0.20085 LAYER Metal3 ; + ANTENNAMAXAREACAR 21.471247 LAYER Metal3 ; + PORT + LAYER Metal2 ; + RECT 225.555 0 225.815 0.26 ; + END + END A_ADDR[3] + PIN A_BIST_ADDR[3] + DIRECTION INPUT ; + USE SIGNAL ; + ANTENNAPARTIALMETALAREA 13.0819 LAYER Metal2 ; + ANTENNAPARTIALMETALAREA 3.7317 LAYER Metal3 ; + ANTENNAPARTIALCUTAREA 0.0722 LAYER Via2 ; + ANTENNAMODEL OXIDE1 ; + ANTENNAGATEAREA 0.20085 LAYER Metal3 ; + ANTENNAMAXAREACAR 20.935524 LAYER Metal3 ; + PORT + LAYER Metal2 ; + RECT 226.065 0 226.325 0.26 ; + END + END A_BIST_ADDR[3] + PIN B_ADDR[3] + DIRECTION INPUT ; + USE SIGNAL ; + ANTENNAPARTIALMETALAREA 13.0819 LAYER Metal2 ; + ANTENNAPARTIALMETALAREA 3.9459 LAYER Metal3 ; + ANTENNAPARTIALCUTAREA 0.0722 LAYER Via2 ; + ANTENNAMODEL OXIDE1 ; + ANTENNAGATEAREA 0.20085 LAYER Metal3 ; + ANTENNAMAXAREACAR 21.471247 LAYER Metal3 ; + PORT + LAYER Metal2 ; + RECT 176.795 0 177.055 0.26 ; + END + END B_ADDR[3] + PIN B_BIST_ADDR[3] + DIRECTION INPUT ; + USE SIGNAL ; + ANTENNAPARTIALMETALAREA 13.0819 LAYER Metal2 ; + ANTENNAPARTIALMETALAREA 3.7317 LAYER Metal3 ; + ANTENNAPARTIALCUTAREA 0.0722 LAYER Via2 ; + ANTENNAMODEL OXIDE1 ; + ANTENNAGATEAREA 0.20085 LAYER Metal3 ; + ANTENNAMAXAREACAR 20.935524 LAYER Metal3 ; + PORT + LAYER Metal2 ; + RECT 176.285 0 176.545 0.26 ; + END + END B_BIST_ADDR[3] + PIN A_ADDR[4] + DIRECTION INPUT ; + USE SIGNAL ; + ANTENNAPARTIALMETALAREA 14.7329 LAYER Metal2 ; + ANTENNAMODEL OXIDE1 ; + ANTENNAGATEAREA 0.20085 LAYER Metal2 ; + ANTENNAMAXAREACAR 74.2589 LAYER Metal2 ; + PORT + LAYER Metal2 ; + RECT 206.175 0 206.435 0.26 ; + END + END A_ADDR[4] + PIN A_BIST_ADDR[4] + DIRECTION INPUT ; + USE SIGNAL ; + ANTENNAPARTIALMETALAREA 14.4677 LAYER Metal2 ; + ANTENNAMODEL OXIDE1 ; + ANTENNAGATEAREA 0.20085 LAYER Metal2 ; + ANTENNAMAXAREACAR 72.938511 LAYER Metal2 ; + PORT + LAYER Metal2 ; + RECT 206.685 0 206.945 0.26 ; + END + END A_BIST_ADDR[4] + PIN B_ADDR[4] + DIRECTION INPUT ; + USE SIGNAL ; + ANTENNAPARTIALMETALAREA 14.7329 LAYER Metal2 ; + ANTENNAMODEL OXIDE1 ; + ANTENNAGATEAREA 0.20085 LAYER Metal2 ; + ANTENNAMAXAREACAR 74.2589 LAYER Metal2 ; + PORT + LAYER Metal2 ; + RECT 196.175 0 196.435 0.26 ; + END + END B_ADDR[4] + PIN B_BIST_ADDR[4] + DIRECTION INPUT ; + USE SIGNAL ; + ANTENNAPARTIALMETALAREA 14.4677 LAYER Metal2 ; + ANTENNAMODEL OXIDE1 ; + ANTENNAGATEAREA 0.20085 LAYER Metal2 ; + ANTENNAMAXAREACAR 72.938511 LAYER Metal2 ; + PORT + LAYER Metal2 ; + RECT 195.665 0 195.925 0.26 ; + END + END B_BIST_ADDR[4] + PIN A_ADDR[5] + DIRECTION INPUT ; + USE SIGNAL ; + ANTENNAPARTIALMETALAREA 13.2691 LAYER Metal2 ; + ANTENNAMODEL OXIDE1 ; + ANTENNAGATEAREA 0.20085 LAYER Metal2 ; + ANTENNAMAXAREACAR 66.970874 LAYER Metal2 ; + PORT + LAYER Metal2 ; + RECT 205.155 0 205.415 0.26 ; + END + END A_ADDR[5] + PIN A_BIST_ADDR[5] + DIRECTION INPUT ; + USE SIGNAL ; + ANTENNAPARTIALMETALAREA 12.9937 LAYER Metal2 ; + ANTENNAMODEL OXIDE1 ; + ANTENNAGATEAREA 0.20085 LAYER Metal2 ; + ANTENNAMAXAREACAR 65.599701 LAYER Metal2 ; + PORT + LAYER Metal2 ; + RECT 205.665 0 205.925 0.26 ; + END + END A_BIST_ADDR[5] + PIN B_ADDR[5] + DIRECTION INPUT ; + USE SIGNAL ; + ANTENNAPARTIALMETALAREA 13.2691 LAYER Metal2 ; + ANTENNAMODEL OXIDE1 ; + ANTENNAGATEAREA 0.20085 LAYER Metal2 ; + ANTENNAMAXAREACAR 66.970874 LAYER Metal2 ; + PORT + LAYER Metal2 ; + RECT 197.195 0 197.455 0.26 ; + END + END B_ADDR[5] + PIN B_BIST_ADDR[5] + DIRECTION INPUT ; + USE SIGNAL ; + ANTENNAPARTIALMETALAREA 12.9937 LAYER Metal2 ; + ANTENNAMODEL OXIDE1 ; + ANTENNAGATEAREA 0.20085 LAYER Metal2 ; + ANTENNAMAXAREACAR 65.599701 LAYER Metal2 ; + PORT + LAYER Metal2 ; + RECT 196.685 0 196.945 0.26 ; + END + END B_BIST_ADDR[5] + PIN A_ADDR[6] + DIRECTION INPUT ; + USE SIGNAL ; + ANTENNAPARTIALMETALAREA 14.3819 LAYER Metal2 ; + ANTENNAMODEL OXIDE1 ; + ANTENNAGATEAREA 0.20085 LAYER Metal2 ; + ANTENNAMAXAREACAR 72.511327 LAYER Metal2 ; + PORT + LAYER Metal2 ; + RECT 229.125 0 229.385 0.26 ; + END + END A_ADDR[6] + PIN A_BIST_ADDR[6] + DIRECTION INPUT ; + USE SIGNAL ; + ANTENNAPARTIALMETALAREA 14.1167 LAYER Metal2 ; + ANTENNAMODEL OXIDE1 ; + ANTENNAGATEAREA 0.20085 LAYER Metal2 ; + ANTENNAMAXAREACAR 71.190939 LAYER Metal2 ; + PORT + LAYER Metal2 ; + RECT 228.615 0 228.875 0.26 ; + END + END A_BIST_ADDR[6] + PIN B_ADDR[6] + DIRECTION INPUT ; + USE SIGNAL ; + ANTENNAPARTIALMETALAREA 14.3819 LAYER Metal2 ; + ANTENNAMODEL OXIDE1 ; + ANTENNAGATEAREA 0.20085 LAYER Metal2 ; + ANTENNAMAXAREACAR 72.511327 LAYER Metal2 ; + PORT + LAYER Metal2 ; + RECT 173.225 0 173.485 0.26 ; + END + END B_ADDR[6] + PIN B_BIST_ADDR[6] + DIRECTION INPUT ; + USE SIGNAL ; + ANTENNAPARTIALMETALAREA 14.1167 LAYER Metal2 ; + ANTENNAMODEL OXIDE1 ; + ANTENNAGATEAREA 0.20085 LAYER Metal2 ; + ANTENNAMAXAREACAR 71.190939 LAYER Metal2 ; + PORT + LAYER Metal2 ; + RECT 173.735 0 173.995 0.26 ; + END + END B_BIST_ADDR[6] + PIN A_ADDR[7] + DIRECTION INPUT ; + USE SIGNAL ; + ANTENNAPARTIALMETALAREA 16.3761 LAYER Metal2 ; + ANTENNAMODEL OXIDE1 ; + ANTENNAGATEAREA 0.20085 LAYER Metal2 ; + ANTENNAMAXAREACAR 82.440129 LAYER Metal2 ; + PORT + LAYER Metal2 ; + RECT 228.105 0 228.365 0.26 ; + END + END A_ADDR[7] + PIN A_BIST_ADDR[7] + DIRECTION INPUT ; + USE SIGNAL ; + ANTENNAPARTIALMETALAREA 16.1109 LAYER Metal2 ; + ANTENNAMODEL OXIDE1 ; + ANTENNAGATEAREA 0.20085 LAYER Metal2 ; + ANTENNAMAXAREACAR 81.119741 LAYER Metal2 ; + PORT + LAYER Metal2 ; + RECT 227.595 0 227.855 0.26 ; + END + END A_BIST_ADDR[7] + PIN B_ADDR[7] + DIRECTION INPUT ; + USE SIGNAL ; + ANTENNAPARTIALMETALAREA 16.3761 LAYER Metal2 ; + ANTENNAMODEL OXIDE1 ; + ANTENNAGATEAREA 0.20085 LAYER Metal2 ; + ANTENNAMAXAREACAR 82.440129 LAYER Metal2 ; + PORT + LAYER Metal2 ; + RECT 174.245 0 174.505 0.26 ; + END + END B_ADDR[7] + PIN B_BIST_ADDR[7] + DIRECTION INPUT ; + USE SIGNAL ; + ANTENNAPARTIALMETALAREA 16.1109 LAYER Metal2 ; + ANTENNAMODEL OXIDE1 ; + ANTENNAGATEAREA 0.20085 LAYER Metal2 ; + ANTENNAMAXAREACAR 81.119741 LAYER Metal2 ; + PORT + LAYER Metal2 ; + RECT 174.755 0 175.015 0.26 ; + END + END B_BIST_ADDR[7] + PIN A_ADDR[8] + DIRECTION INPUT ; + USE SIGNAL ; + ANTENNAPARTIALMETALAREA 14.4422 LAYER Metal2 ; + ANTENNAMODEL OXIDE1 ; + ANTENNAGATEAREA 0.20085 LAYER Metal2 ; + ANTENNAMAXAREACAR 72.811551 LAYER Metal2 ; + PORT + LAYER Metal2 ; + RECT 231.675 0 231.935 0.26 ; + END + END A_ADDR[8] + PIN A_BIST_ADDR[8] + DIRECTION INPUT ; + USE SIGNAL ; + ANTENNAPARTIALMETALAREA 14.1872 LAYER Metal2 ; + ANTENNAMODEL OXIDE1 ; + ANTENNAGATEAREA 0.20085 LAYER Metal2 ; + ANTENNAMAXAREACAR 71.541947 LAYER Metal2 ; + PORT + LAYER Metal2 ; + RECT 232.185 0 232.445 0.26 ; + END + END A_BIST_ADDR[8] + PIN B_ADDR[8] + DIRECTION INPUT ; + USE SIGNAL ; + ANTENNAPARTIALMETALAREA 14.4422 LAYER Metal2 ; + ANTENNAMODEL OXIDE1 ; + ANTENNAGATEAREA 0.20085 LAYER Metal2 ; + ANTENNAMAXAREACAR 72.811551 LAYER Metal2 ; + PORT + LAYER Metal2 ; + RECT 170.675 0 170.935 0.26 ; + END + END B_ADDR[8] + PIN B_BIST_ADDR[8] + DIRECTION INPUT ; + USE SIGNAL ; + ANTENNAPARTIALMETALAREA 14.1872 LAYER Metal2 ; + ANTENNAMODEL OXIDE1 ; + ANTENNAGATEAREA 0.20085 LAYER Metal2 ; + ANTENNAMAXAREACAR 71.541947 LAYER Metal2 ; + PORT + LAYER Metal2 ; + RECT 170.165 0 170.425 0.26 ; + END + END B_BIST_ADDR[8] + PIN A_ADDR[9] + DIRECTION INPUT ; + USE SIGNAL ; + ANTENNAPARTIALMETALAREA 13.7995 LAYER Metal2 ; + ANTENNAMODEL OXIDE1 ; + ANTENNAGATEAREA 0.20085 LAYER Metal2 ; + ANTENNAMAXAREACAR 69.61165 LAYER Metal2 ; + PORT + LAYER Metal2 ; + RECT 229.635 0 229.895 0.26 ; + END + END A_ADDR[9] + PIN A_BIST_ADDR[9] + DIRECTION INPUT ; + USE SIGNAL ; + ANTENNAPARTIALMETALAREA 13.7995 LAYER Metal2 ; + ANTENNAMODEL OXIDE1 ; + ANTENNAGATEAREA 0.20085 LAYER Metal2 ; + ANTENNAMAXAREACAR 69.61165 LAYER Metal2 ; + PORT + LAYER Metal2 ; + RECT 230.145 0 230.405 0.26 ; + END + END A_BIST_ADDR[9] + PIN B_ADDR[9] + DIRECTION INPUT ; + USE SIGNAL ; + ANTENNAPARTIALMETALAREA 13.7995 LAYER Metal2 ; + ANTENNAMODEL OXIDE1 ; + ANTENNAGATEAREA 0.20085 LAYER Metal2 ; + ANTENNAMAXAREACAR 69.61165 LAYER Metal2 ; + PORT + LAYER Metal2 ; + RECT 172.715 0 172.975 0.26 ; + END + END B_ADDR[9] + PIN B_BIST_ADDR[9] + DIRECTION INPUT ; + USE SIGNAL ; + ANTENNAPARTIALMETALAREA 13.7995 LAYER Metal2 ; + ANTENNAMODEL OXIDE1 ; + ANTENNAGATEAREA 0.20085 LAYER Metal2 ; + ANTENNAMAXAREACAR 69.61165 LAYER Metal2 ; + PORT + LAYER Metal2 ; + RECT 172.205 0 172.465 0.26 ; + END + END B_BIST_ADDR[9] + PIN A_CLK + DIRECTION INPUT ; + USE SIGNAL ; + ANTENNAPARTIALMETALAREA 4.0547 LAYER Metal2 ; + ANTENNAMODEL OXIDE1 ; + ANTENNAGATEAREA 0.20085 LAYER Metal2 ; + ANTENNAMAXAREACAR 21.093851 LAYER Metal2 ; + PORT + LAYER Metal2 ; + RECT 215.865 0 216.125 0.26 ; + END + END A_CLK + PIN A_REN + DIRECTION INPUT ; + USE SIGNAL ; + ANTENNAPARTIALMETALAREA 3.98465 LAYER Metal2 ; + ANTENNAMODEL OXIDE1 ; + ANTENNAGATEAREA 0.20085 LAYER Metal2 ; + ANTENNAMAXAREACAR 20.745083 LAYER Metal2 ; + PORT + LAYER Metal2 ; + RECT 219.435 0 219.695 0.26 ; + END + END A_REN + PIN A_WEN + DIRECTION INPUT ; + USE SIGNAL ; + ANTENNAPARTIALMETALAREA 2.8847 LAYER Metal2 ; + ANTENNAMODEL OXIDE1 ; + ANTENNAGATEAREA 0.20085 LAYER Metal2 ; + ANTENNAMAXAREACAR 15.268608 LAYER Metal2 ; + PORT + LAYER Metal2 ; + RECT 218.925 0 219.185 0.26 ; + END + END A_WEN + PIN A_MEN + DIRECTION INPUT ; + USE SIGNAL ; + ANTENNAPARTIALMETALAREA 3.0247 LAYER Metal2 ; + ANTENNAMODEL OXIDE1 ; + ANTENNAGATEAREA 0.20085 LAYER Metal2 ; + ANTENNAMAXAREACAR 15.965646 LAYER Metal2 ; + PORT + LAYER Metal2 ; + RECT 216.375 0 216.635 0.26 ; + END + END A_MEN + PIN A_DLY + DIRECTION INPUT ; + USE SIGNAL ; + ANTENNAPARTIALMETALAREA 7.7792 LAYER Metal2 ; + ANTENNAMODEL OXIDE1 ; + ANTENNAGATEAREA 0.3367 LAYER Metal2 ; + ANTENNAMAXAREACAR 23.644788 LAYER Metal2 ; + PORT + LAYER Metal2 ; + RECT 236.775 0 237.035 0.26 ; + END + END A_DLY + PIN B_CLK + DIRECTION INPUT ; + USE SIGNAL ; + ANTENNAPARTIALMETALAREA 4.0547 LAYER Metal2 ; + ANTENNAMODEL OXIDE1 ; + ANTENNAGATEAREA 0.20085 LAYER Metal2 ; + ANTENNAMAXAREACAR 21.093851 LAYER Metal2 ; + PORT + LAYER Metal2 ; + RECT 186.485 0 186.745 0.26 ; + END + END B_CLK + PIN B_REN + DIRECTION INPUT ; + USE SIGNAL ; + ANTENNAPARTIALMETALAREA 3.98465 LAYER Metal2 ; + ANTENNAMODEL OXIDE1 ; + ANTENNAGATEAREA 0.20085 LAYER Metal2 ; + ANTENNAMAXAREACAR 20.745083 LAYER Metal2 ; + PORT + LAYER Metal2 ; + RECT 182.915 0 183.175 0.26 ; + END + END B_REN + PIN B_WEN + DIRECTION INPUT ; + USE SIGNAL ; + ANTENNAPARTIALMETALAREA 2.8847 LAYER Metal2 ; + ANTENNAMODEL OXIDE1 ; + ANTENNAGATEAREA 0.20085 LAYER Metal2 ; + ANTENNAMAXAREACAR 15.268608 LAYER Metal2 ; + PORT + LAYER Metal2 ; + RECT 183.425 0 183.685 0.26 ; + END + END B_WEN + PIN B_MEN + DIRECTION INPUT ; + USE SIGNAL ; + ANTENNAPARTIALMETALAREA 3.0247 LAYER Metal2 ; + ANTENNAMODEL OXIDE1 ; + ANTENNAGATEAREA 0.20085 LAYER Metal2 ; + ANTENNAMAXAREACAR 15.965646 LAYER Metal2 ; + PORT + LAYER Metal2 ; + RECT 185.975 0 186.235 0.26 ; + END + END B_MEN + PIN B_DLY + DIRECTION INPUT ; + USE SIGNAL ; + ANTENNAPARTIALMETALAREA 7.7792 LAYER Metal2 ; + ANTENNAMODEL OXIDE1 ; + ANTENNAGATEAREA 0.3367 LAYER Metal2 ; + ANTENNAMAXAREACAR 23.644788 LAYER Metal2 ; + PORT + LAYER Metal2 ; + RECT 165.575 0 165.835 0.26 ; + END + END B_DLY + PIN A_BIST_EN + DIRECTION INPUT ; + USE SIGNAL ; + ANTENNAPARTIALMETALAREA 4.0634 LAYER Metal2 ; + ANTENNAPARTIALMETALAREA 146.7701 LAYER Metal3 ; + ANTENNAPARTIALCUTAREA 0.0722 LAYER Via2 ; + ANTENNAMODEL OXIDE1 ; + ANTENNAGATEAREA 1.43 LAYER Metal2 ; + ANTENNAGATEAREA 16.445 LAYER Metal3 ; + ANTENNAMAXAREACAR 3.266993 LAYER Metal2 ; + ANTENNAMAXAREACAR 20.096283 LAYER Metal3 ; + ANTENNAMAXCUTCAR 0.151469 LAYER Via2 ; + PORT + LAYER Metal2 ; + RECT 218.415 0 218.675 0.26 ; + END + END A_BIST_EN + PIN A_BIST_CLK + DIRECTION INPUT ; + USE SIGNAL ; + ANTENNAPARTIALMETALAREA 4.1639 LAYER Metal2 ; + ANTENNAMODEL OXIDE1 ; + ANTENNAGATEAREA 0.20085 LAYER Metal2 ; + ANTENNAMAXAREACAR 21.953448 LAYER Metal2 ; + PORT + LAYER Metal2 ; + RECT 214.335 0 214.595 0.26 ; + END + END A_BIST_CLK + PIN A_BIST_REN + DIRECTION INPUT ; + USE SIGNAL ; + ANTENNAPARTIALMETALAREA 4.1119 LAYER Metal2 ; + ANTENNAMODEL OXIDE1 ; + ANTENNAGATEAREA 0.20085 LAYER Metal2 ; + ANTENNAMAXAREACAR 21.694548 LAYER Metal2 ; + PORT + LAYER Metal2 ; + RECT 220.965 0 221.225 0.26 ; + END + END A_BIST_REN + PIN A_BIST_WEN + DIRECTION INPUT ; + USE SIGNAL ; + ANTENNAPARTIALMETALAREA 2.9051 LAYER Metal2 ; + ANTENNAMODEL OXIDE1 ; + ANTENNAGATEAREA 0.20085 LAYER Metal2 ; + ANTENNAMAXAREACAR 15.686084 LAYER Metal2 ; + PORT + LAYER Metal2 ; + RECT 220.455 0 220.715 0.26 ; + END + END A_BIST_WEN + PIN A_BIST_MEN + DIRECTION INPUT ; + USE SIGNAL ; + ANTENNAPARTIALMETALAREA 2.8977 LAYER Metal2 ; + ANTENNAMODEL OXIDE1 ; + ANTENNAGATEAREA 0.20085 LAYER Metal2 ; + ANTENNAMAXAREACAR 15.649241 LAYER Metal2 ; + PORT + LAYER Metal2 ; + RECT 214.845 0 215.105 0.26 ; + END + END A_BIST_MEN + PIN B_BIST_EN + DIRECTION INPUT ; + USE SIGNAL ; + ANTENNAPARTIALMETALAREA 3.9646 LAYER Metal2 ; + ANTENNAPARTIALMETALAREA 147.2093 LAYER Metal3 ; + ANTENNAPARTIALCUTAREA 0.0722 LAYER Via2 ; + ANTENNAMODEL OXIDE1 ; + ANTENNAGATEAREA 1.43 LAYER Metal2 ; + ANTENNAGATEAREA 16.445 LAYER Metal3 ; + ANTENNAMAXAREACAR 3.197902 LAYER Metal2 ; + ANTENNAMAXAREACAR 20.12299 LAYER Metal3 ; + ANTENNAMAXCUTCAR 0.151469 LAYER Via2 ; + PORT + LAYER Metal2 ; + RECT 183.935 0 184.195 0.26 ; + END + END B_BIST_EN + PIN B_BIST_CLK + DIRECTION INPUT ; + USE SIGNAL ; + ANTENNAPARTIALMETALAREA 4.1639 LAYER Metal2 ; + ANTENNAMODEL OXIDE1 ; + ANTENNAGATEAREA 0.20085 LAYER Metal2 ; + ANTENNAMAXAREACAR 21.953448 LAYER Metal2 ; + PORT + LAYER Metal2 ; + RECT 188.015 0 188.275 0.26 ; + END + END B_BIST_CLK + PIN B_BIST_REN + DIRECTION INPUT ; + USE SIGNAL ; + ANTENNAPARTIALMETALAREA 4.1119 LAYER Metal2 ; + ANTENNAMODEL OXIDE1 ; + ANTENNAGATEAREA 0.20085 LAYER Metal2 ; + ANTENNAMAXAREACAR 21.694548 LAYER Metal2 ; + PORT + LAYER Metal2 ; + RECT 181.385 0 181.645 0.26 ; + END + END B_BIST_REN + PIN B_BIST_WEN + DIRECTION INPUT ; + USE SIGNAL ; + ANTENNAPARTIALMETALAREA 2.9051 LAYER Metal2 ; + ANTENNAMODEL OXIDE1 ; + ANTENNAGATEAREA 0.20085 LAYER Metal2 ; + ANTENNAMAXAREACAR 15.686084 LAYER Metal2 ; + PORT + LAYER Metal2 ; + RECT 181.895 0 182.155 0.26 ; + END + END B_BIST_WEN + PIN B_BIST_MEN + DIRECTION INPUT ; + USE SIGNAL ; + ANTENNAPARTIALMETALAREA 2.8977 LAYER Metal2 ; + ANTENNAMODEL OXIDE1 ; + ANTENNAGATEAREA 0.20085 LAYER Metal2 ; + ANTENNAMAXAREACAR 15.649241 LAYER Metal2 ; + PORT + LAYER Metal2 ; + RECT 187.505 0 187.765 0.26 ; + END + END B_BIST_MEN + OBS + LAYER Metal1 ; + RECT 0 0 402.61 385.37 ; + LAYER Metal2 ; + RECT 0.31 53.41 0.51 385.34 ; + RECT 1.135 384.61 1.335 385.34 ; + RECT 1.545 384.61 1.905 385.34 ; + RECT 2.115 384.61 2.315 385.34 ; + RECT 2.19 0.52 2.45 7.78 ; + RECT 2.7 0.3 2.96 5.235 ; + RECT 2.77 384.61 2.97 385.34 ; + RECT 3.21 0.52 3.47 5.57 ; + RECT 3.18 384.61 3.54 385.34 ; + RECT 3.835 384.61 4.035 385.34 ; + RECT 4.33 384.61 4.69 385.34 ; + RECT 4.585 0.52 4.845 6.28 ; + RECT 4.9 384.61 5.1 385.34 ; + RECT 5.555 384.61 5.755 385.34 ; + RECT 5.965 384.61 6.325 385.34 ; + RECT 6.535 384.61 6.735 385.34 ; + RECT 6.27 0.18 7.04 0.88 ; + RECT 7.19 384.61 7.39 385.34 ; + RECT 7.29 0.3 7.55 8.7 ; + RECT 7.6 384.61 7.96 385.34 ; + RECT 8.255 384.61 8.455 385.34 ; + RECT 8.75 384.61 9.11 385.34 ; + RECT 9.84 0.155 10.61 0.445 ; + RECT 9.84 0.155 10.1 8.665 ; + RECT 10.35 0.155 10.61 8.665 ; + RECT 9.32 384.61 9.52 385.34 ; + RECT 9.33 0.52 9.59 9.955 ; + RECT 9.975 384.61 10.175 385.34 ; + RECT 10.385 384.61 10.745 385.34 ; + RECT 10.86 0.52 11.12 11.315 ; + RECT 10.955 384.61 11.155 385.34 ; + RECT 11.37 0.52 11.63 13.45 ; + RECT 11.61 384.61 11.81 385.34 ; + RECT 11.88 0.52 12.14 14.115 ; + RECT 12.02 384.61 12.38 385.34 ; + RECT 12.675 384.61 12.875 385.34 ; + RECT 14.075 0.155 14.845 0.445 ; + RECT 14.075 0.155 14.335 13.21 ; + RECT 14.585 0.155 14.845 13.21 ; + RECT 13.17 384.61 13.53 385.34 ; + RECT 13.74 384.61 13.94 385.34 ; + RECT 15.095 0.18 15.865 0.88 ; + RECT 15.095 0.18 15.355 12.9 ; + RECT 15.605 0.18 15.865 12.9 ; + RECT 14.395 384.61 14.595 385.34 ; + RECT 14.805 384.61 15.165 385.34 ; + RECT 15.375 384.61 15.575 385.34 ; + RECT 16.03 384.61 16.23 385.34 ; + RECT 16.315 0.52 16.575 2.82 ; + RECT 16.44 384.61 16.8 385.34 ; + RECT 17.095 384.61 17.295 385.34 ; + RECT 17.59 384.61 17.95 385.34 ; + RECT 17.845 0.52 18.105 2.82 ; + RECT 18.16 384.61 18.36 385.34 ; + RECT 18.815 384.61 19.015 385.34 ; + RECT 19.02 0.52 19.28 4.315 ; + RECT 19.225 384.61 19.585 385.34 ; + RECT 19.795 384.61 19.995 385.34 ; + RECT 19.87 0.52 20.13 7.78 ; + RECT 20.38 0.3 20.64 5.235 ; + RECT 20.45 384.61 20.65 385.34 ; + RECT 20.89 0.52 21.15 5.57 ; + RECT 20.86 384.61 21.22 385.34 ; + RECT 21.515 384.61 21.715 385.34 ; + RECT 22.01 384.61 22.37 385.34 ; + RECT 22.265 0.52 22.525 6.28 ; + RECT 22.58 384.61 22.78 385.34 ; + RECT 23.235 384.61 23.435 385.34 ; + RECT 23.645 384.61 24.005 385.34 ; + RECT 24.215 384.61 24.415 385.34 ; + RECT 23.95 0.18 24.72 0.88 ; + RECT 24.87 384.61 25.07 385.34 ; + RECT 24.97 0.3 25.23 8.7 ; + RECT 25.28 384.61 25.64 385.34 ; + RECT 25.935 384.61 26.135 385.34 ; + RECT 26.43 384.61 26.79 385.34 ; + RECT 27.52 0.155 28.29 0.445 ; + RECT 27.52 0.155 27.78 8.665 ; + RECT 28.03 0.155 28.29 8.665 ; + RECT 27 384.61 27.2 385.34 ; + RECT 27.01 0.52 27.27 9.955 ; + RECT 27.655 384.61 27.855 385.34 ; + RECT 28.065 384.61 28.425 385.34 ; + RECT 28.54 0.52 28.8 11.315 ; + RECT 28.635 384.61 28.835 385.34 ; + RECT 29.05 0.52 29.31 13.45 ; + RECT 29.29 384.61 29.49 385.34 ; + RECT 29.56 0.52 29.82 14.115 ; + RECT 29.7 384.61 30.06 385.34 ; + RECT 30.355 384.61 30.555 385.34 ; + RECT 31.755 0.155 32.525 0.445 ; + RECT 31.755 0.155 32.015 13.21 ; + RECT 32.265 0.155 32.525 13.21 ; + RECT 30.85 384.61 31.21 385.34 ; + RECT 31.42 384.61 31.62 385.34 ; + RECT 32.775 0.18 33.545 0.88 ; + RECT 32.775 0.18 33.035 12.9 ; + RECT 33.285 0.18 33.545 12.9 ; + RECT 32.075 384.61 32.275 385.34 ; + RECT 32.485 384.61 32.845 385.34 ; + RECT 33.055 384.61 33.255 385.34 ; + RECT 33.71 384.61 33.91 385.34 ; + RECT 33.995 0.52 34.255 2.82 ; + RECT 34.12 384.61 34.48 385.34 ; + RECT 34.775 384.61 34.975 385.34 ; + RECT 35.27 384.61 35.63 385.34 ; + RECT 35.525 0.52 35.785 2.82 ; + RECT 35.84 384.61 36.04 385.34 ; + RECT 36.495 384.61 36.695 385.34 ; + RECT 36.7 0.52 36.96 4.315 ; + RECT 36.905 384.61 37.265 385.34 ; + RECT 37.475 384.61 37.675 385.34 ; + RECT 37.55 0.52 37.81 7.78 ; + RECT 38.06 0.3 38.32 5.235 ; + RECT 38.13 384.61 38.33 385.34 ; + RECT 38.57 0.52 38.83 5.57 ; + RECT 38.54 384.61 38.9 385.34 ; + RECT 39.195 384.61 39.395 385.34 ; + RECT 39.69 384.61 40.05 385.34 ; + RECT 39.945 0.52 40.205 6.28 ; + RECT 40.26 384.61 40.46 385.34 ; + RECT 40.915 384.61 41.115 385.34 ; + RECT 41.325 384.61 41.685 385.34 ; + RECT 41.895 384.61 42.095 385.34 ; + RECT 41.63 0.18 42.4 0.88 ; + RECT 42.55 384.61 42.75 385.34 ; + RECT 42.65 0.3 42.91 8.7 ; + RECT 42.96 384.61 43.32 385.34 ; + RECT 43.615 384.61 43.815 385.34 ; + RECT 44.11 384.61 44.47 385.34 ; + RECT 45.2 0.155 45.97 0.445 ; + RECT 45.2 0.155 45.46 8.665 ; + RECT 45.71 0.155 45.97 8.665 ; + RECT 44.68 384.61 44.88 385.34 ; + RECT 44.69 0.52 44.95 9.955 ; + RECT 45.335 384.61 45.535 385.34 ; + RECT 45.745 384.61 46.105 385.34 ; + RECT 46.22 0.52 46.48 11.315 ; + RECT 46.315 384.61 46.515 385.34 ; + RECT 46.73 0.52 46.99 13.45 ; + RECT 46.97 384.61 47.17 385.34 ; + RECT 47.24 0.52 47.5 14.115 ; + RECT 47.38 384.61 47.74 385.34 ; + RECT 48.035 384.61 48.235 385.34 ; + RECT 49.435 0.155 50.205 0.445 ; + RECT 49.435 0.155 49.695 13.21 ; + RECT 49.945 0.155 50.205 13.21 ; + RECT 48.53 384.61 48.89 385.34 ; + RECT 49.1 384.61 49.3 385.34 ; + RECT 50.455 0.18 51.225 0.88 ; + RECT 50.455 0.18 50.715 12.9 ; + RECT 50.965 0.18 51.225 12.9 ; + RECT 49.755 384.61 49.955 385.34 ; + RECT 50.165 384.61 50.525 385.34 ; + RECT 50.735 384.61 50.935 385.34 ; + RECT 51.39 384.61 51.59 385.34 ; + RECT 51.675 0.52 51.935 2.82 ; + RECT 51.8 384.61 52.16 385.34 ; + RECT 52.455 384.61 52.655 385.34 ; + RECT 52.95 384.61 53.31 385.34 ; + RECT 53.205 0.52 53.465 2.82 ; + RECT 53.52 384.61 53.72 385.34 ; + RECT 54.175 384.61 54.375 385.34 ; + RECT 54.38 0.52 54.64 4.315 ; + RECT 54.585 384.61 54.945 385.34 ; + RECT 55.155 384.61 55.355 385.34 ; + RECT 55.23 0.52 55.49 7.78 ; + RECT 55.74 0.3 56 5.235 ; + RECT 55.81 384.61 56.01 385.34 ; + RECT 56.25 0.52 56.51 5.57 ; + RECT 56.22 384.61 56.58 385.34 ; + RECT 56.875 384.61 57.075 385.34 ; + RECT 57.37 384.61 57.73 385.34 ; + RECT 57.625 0.52 57.885 6.28 ; + RECT 57.94 384.61 58.14 385.34 ; + RECT 58.595 384.61 58.795 385.34 ; + RECT 59.005 384.61 59.365 385.34 ; + RECT 59.575 384.61 59.775 385.34 ; + RECT 59.31 0.18 60.08 0.88 ; + RECT 60.23 384.61 60.43 385.34 ; + RECT 60.33 0.3 60.59 8.7 ; + RECT 60.64 384.61 61 385.34 ; + RECT 61.295 384.61 61.495 385.34 ; + RECT 61.79 384.61 62.15 385.34 ; + RECT 62.88 0.155 63.65 0.445 ; + RECT 62.88 0.155 63.14 8.665 ; + RECT 63.39 0.155 63.65 8.665 ; + RECT 62.36 384.61 62.56 385.34 ; + RECT 62.37 0.52 62.63 9.955 ; + RECT 63.015 384.61 63.215 385.34 ; + RECT 63.425 384.61 63.785 385.34 ; + RECT 63.9 0.52 64.16 11.315 ; + RECT 63.995 384.61 64.195 385.34 ; + RECT 64.41 0.52 64.67 13.45 ; + RECT 64.65 384.61 64.85 385.34 ; + RECT 64.92 0.52 65.18 14.115 ; + RECT 65.06 384.61 65.42 385.34 ; + RECT 65.715 384.61 65.915 385.34 ; + RECT 67.115 0.155 67.885 0.445 ; + RECT 67.115 0.155 67.375 13.21 ; + RECT 67.625 0.155 67.885 13.21 ; + RECT 66.21 384.61 66.57 385.34 ; + RECT 66.78 384.61 66.98 385.34 ; + RECT 68.135 0.18 68.905 0.88 ; + RECT 68.135 0.18 68.395 12.9 ; + RECT 68.645 0.18 68.905 12.9 ; + RECT 67.435 384.61 67.635 385.34 ; + RECT 67.845 384.61 68.205 385.34 ; + RECT 68.415 384.61 68.615 385.34 ; + RECT 69.07 384.61 69.27 385.34 ; + RECT 69.355 0.52 69.615 2.82 ; + RECT 69.48 384.61 69.84 385.34 ; + RECT 70.135 384.61 70.335 385.34 ; + RECT 70.63 384.61 70.99 385.34 ; + RECT 70.885 0.52 71.145 2.82 ; + RECT 71.2 384.61 71.4 385.34 ; + RECT 71.855 384.61 72.055 385.34 ; + RECT 72.06 0.52 72.32 4.315 ; + RECT 72.265 384.61 72.625 385.34 ; + RECT 72.835 384.61 73.035 385.34 ; + RECT 72.91 0.52 73.17 7.78 ; + RECT 73.42 0.3 73.68 5.235 ; + RECT 73.49 384.61 73.69 385.34 ; + RECT 73.93 0.52 74.19 5.57 ; + RECT 73.9 384.61 74.26 385.34 ; + RECT 74.555 384.61 74.755 385.34 ; + RECT 75.05 384.61 75.41 385.34 ; + RECT 75.305 0.52 75.565 6.28 ; + RECT 75.62 384.61 75.82 385.34 ; + RECT 76.275 384.61 76.475 385.34 ; + RECT 76.685 384.61 77.045 385.34 ; + RECT 77.255 384.61 77.455 385.34 ; + RECT 76.99 0.18 77.76 0.88 ; + RECT 77.91 384.61 78.11 385.34 ; + RECT 78.01 0.3 78.27 8.7 ; + RECT 78.32 384.61 78.68 385.34 ; + RECT 78.975 384.61 79.175 385.34 ; + RECT 79.47 384.61 79.83 385.34 ; + RECT 80.56 0.155 81.33 0.445 ; + RECT 80.56 0.155 80.82 8.665 ; + RECT 81.07 0.155 81.33 8.665 ; + RECT 80.04 384.61 80.24 385.34 ; + RECT 80.05 0.52 80.31 9.955 ; + RECT 80.695 384.61 80.895 385.34 ; + RECT 81.105 384.61 81.465 385.34 ; + RECT 81.58 0.52 81.84 11.315 ; + RECT 81.675 384.61 81.875 385.34 ; + RECT 82.09 0.52 82.35 13.45 ; + RECT 82.33 384.61 82.53 385.34 ; + RECT 82.6 0.52 82.86 14.115 ; + RECT 82.74 384.61 83.1 385.34 ; + RECT 83.395 384.61 83.595 385.34 ; + RECT 84.795 0.155 85.565 0.445 ; + RECT 84.795 0.155 85.055 13.21 ; + RECT 85.305 0.155 85.565 13.21 ; + RECT 83.89 384.61 84.25 385.34 ; + RECT 84.46 384.61 84.66 385.34 ; + RECT 85.815 0.18 86.585 0.88 ; + RECT 85.815 0.18 86.075 12.9 ; + RECT 86.325 0.18 86.585 12.9 ; + RECT 85.115 384.61 85.315 385.34 ; + RECT 85.525 384.61 85.885 385.34 ; + RECT 86.095 384.61 86.295 385.34 ; + RECT 86.75 384.61 86.95 385.34 ; + RECT 87.035 0.52 87.295 2.82 ; + RECT 87.16 384.61 87.52 385.34 ; + RECT 87.815 384.61 88.015 385.34 ; + RECT 88.31 384.61 88.67 385.34 ; + RECT 88.565 0.52 88.825 2.82 ; + RECT 88.88 384.61 89.08 385.34 ; + RECT 89.535 384.61 89.735 385.34 ; + RECT 89.74 0.52 90 4.315 ; + RECT 89.945 384.61 90.305 385.34 ; + RECT 90.515 384.61 90.715 385.34 ; + RECT 90.59 0.52 90.85 7.78 ; + RECT 91.1 0.3 91.36 5.235 ; + RECT 91.17 384.61 91.37 385.34 ; + RECT 91.61 0.52 91.87 5.57 ; + RECT 91.58 384.61 91.94 385.34 ; + RECT 92.235 384.61 92.435 385.34 ; + RECT 92.73 384.61 93.09 385.34 ; + RECT 92.985 0.52 93.245 6.28 ; + RECT 93.3 384.61 93.5 385.34 ; + RECT 93.955 384.61 94.155 385.34 ; + RECT 94.365 384.61 94.725 385.34 ; + RECT 94.935 384.61 95.135 385.34 ; + RECT 94.67 0.18 95.44 0.88 ; + RECT 95.59 384.61 95.79 385.34 ; + RECT 95.69 0.3 95.95 8.7 ; + RECT 96 384.61 96.36 385.34 ; + RECT 96.655 384.61 96.855 385.34 ; + RECT 97.15 384.61 97.51 385.34 ; + RECT 98.24 0.155 99.01 0.445 ; + RECT 98.24 0.155 98.5 8.665 ; + RECT 98.75 0.155 99.01 8.665 ; + RECT 97.72 384.61 97.92 385.34 ; + RECT 97.73 0.52 97.99 9.955 ; + RECT 98.375 384.61 98.575 385.34 ; + RECT 98.785 384.61 99.145 385.34 ; + RECT 99.26 0.52 99.52 11.315 ; + RECT 99.355 384.61 99.555 385.34 ; + RECT 99.77 0.52 100.03 13.45 ; + RECT 100.01 384.61 100.21 385.34 ; + RECT 100.28 0.52 100.54 14.115 ; + RECT 100.42 384.61 100.78 385.34 ; + RECT 101.075 384.61 101.275 385.34 ; + RECT 102.475 0.155 103.245 0.445 ; + RECT 102.475 0.155 102.735 13.21 ; + RECT 102.985 0.155 103.245 13.21 ; + RECT 101.57 384.61 101.93 385.34 ; + RECT 102.14 384.61 102.34 385.34 ; + RECT 103.495 0.18 104.265 0.88 ; + RECT 103.495 0.18 103.755 12.9 ; + RECT 104.005 0.18 104.265 12.9 ; + RECT 102.795 384.61 102.995 385.34 ; + RECT 103.205 384.61 103.565 385.34 ; + RECT 103.775 384.61 103.975 385.34 ; + RECT 104.43 384.61 104.63 385.34 ; + RECT 104.715 0.52 104.975 2.82 ; + RECT 104.84 384.61 105.2 385.34 ; + RECT 105.495 384.61 105.695 385.34 ; + RECT 105.99 384.61 106.35 385.34 ; + RECT 106.245 0.52 106.505 2.82 ; + RECT 106.56 384.61 106.76 385.34 ; + RECT 107.215 384.61 107.415 385.34 ; + RECT 107.42 0.52 107.68 4.315 ; + RECT 107.625 384.61 107.985 385.34 ; + RECT 108.195 384.61 108.395 385.34 ; + RECT 108.27 0.52 108.53 7.78 ; + RECT 108.78 0.3 109.04 5.235 ; + RECT 108.85 384.61 109.05 385.34 ; + RECT 109.29 0.52 109.55 5.57 ; + RECT 109.26 384.61 109.62 385.34 ; + RECT 109.915 384.61 110.115 385.34 ; + RECT 110.41 384.61 110.77 385.34 ; + RECT 110.665 0.52 110.925 6.28 ; + RECT 110.98 384.61 111.18 385.34 ; + RECT 111.635 384.61 111.835 385.34 ; + RECT 112.045 384.61 112.405 385.34 ; + RECT 112.615 384.61 112.815 385.34 ; + RECT 112.35 0.18 113.12 0.88 ; + RECT 113.27 384.61 113.47 385.34 ; + RECT 113.37 0.3 113.63 8.7 ; + RECT 113.68 384.61 114.04 385.34 ; + RECT 114.335 384.61 114.535 385.34 ; + RECT 114.83 384.61 115.19 385.34 ; + RECT 115.92 0.155 116.69 0.445 ; + RECT 115.92 0.155 116.18 8.665 ; + RECT 116.43 0.155 116.69 8.665 ; + RECT 115.4 384.61 115.6 385.34 ; + RECT 115.41 0.52 115.67 9.955 ; + RECT 116.055 384.61 116.255 385.34 ; + RECT 116.465 384.61 116.825 385.34 ; + RECT 116.94 0.52 117.2 11.315 ; + RECT 117.035 384.61 117.235 385.34 ; + RECT 117.45 0.52 117.71 13.45 ; + RECT 117.69 384.61 117.89 385.34 ; + RECT 117.96 0.52 118.22 14.115 ; + RECT 118.1 384.61 118.46 385.34 ; + RECT 118.755 384.61 118.955 385.34 ; + RECT 120.155 0.155 120.925 0.445 ; + RECT 120.155 0.155 120.415 13.21 ; + RECT 120.665 0.155 120.925 13.21 ; + RECT 119.25 384.61 119.61 385.34 ; + RECT 119.82 384.61 120.02 385.34 ; + RECT 121.175 0.18 121.945 0.88 ; + RECT 121.175 0.18 121.435 12.9 ; + RECT 121.685 0.18 121.945 12.9 ; + RECT 120.475 384.61 120.675 385.34 ; + RECT 120.885 384.61 121.245 385.34 ; + RECT 121.455 384.61 121.655 385.34 ; + RECT 122.11 384.61 122.31 385.34 ; + RECT 122.395 0.52 122.655 2.82 ; + RECT 122.52 384.61 122.88 385.34 ; + RECT 123.175 384.61 123.375 385.34 ; + RECT 123.67 384.61 124.03 385.34 ; + RECT 123.925 0.52 124.185 2.82 ; + RECT 124.24 384.61 124.44 385.34 ; + RECT 124.895 384.61 125.095 385.34 ; + RECT 125.1 0.52 125.36 4.315 ; + RECT 125.305 384.61 125.665 385.34 ; + RECT 125.875 384.61 126.075 385.34 ; + RECT 125.95 0.52 126.21 7.78 ; + RECT 126.46 0.3 126.72 5.235 ; + RECT 126.53 384.61 126.73 385.34 ; + RECT 126.97 0.52 127.23 5.57 ; + RECT 126.94 384.61 127.3 385.34 ; + RECT 127.595 384.61 127.795 385.34 ; + RECT 128.09 384.61 128.45 385.34 ; + RECT 128.345 0.52 128.605 6.28 ; + RECT 128.66 384.61 128.86 385.34 ; + RECT 129.315 384.61 129.515 385.34 ; + RECT 129.725 384.61 130.085 385.34 ; + RECT 130.295 384.61 130.495 385.34 ; + RECT 130.03 0.18 130.8 0.88 ; + RECT 130.95 384.61 131.15 385.34 ; + RECT 131.05 0.3 131.31 8.7 ; + RECT 131.36 384.61 131.72 385.34 ; + RECT 132.015 384.61 132.215 385.34 ; + RECT 132.51 384.61 132.87 385.34 ; + RECT 133.6 0.155 134.37 0.445 ; + RECT 133.6 0.155 133.86 8.665 ; + RECT 134.11 0.155 134.37 8.665 ; + RECT 133.08 384.61 133.28 385.34 ; + RECT 133.09 0.52 133.35 9.955 ; + RECT 133.735 384.61 133.935 385.34 ; + RECT 134.145 384.61 134.505 385.34 ; + RECT 134.62 0.52 134.88 11.315 ; + RECT 134.715 384.61 134.915 385.34 ; + RECT 135.13 0.52 135.39 13.45 ; + RECT 135.37 384.61 135.57 385.34 ; + RECT 135.64 0.52 135.9 14.115 ; + RECT 135.78 384.61 136.14 385.34 ; + RECT 136.435 384.61 136.635 385.34 ; + RECT 137.835 0.155 138.605 0.445 ; + RECT 137.835 0.155 138.095 13.21 ; + RECT 138.345 0.155 138.605 13.21 ; + RECT 136.93 384.61 137.29 385.34 ; + RECT 137.5 384.61 137.7 385.34 ; + RECT 138.855 0.18 139.625 0.88 ; + RECT 138.855 0.18 139.115 12.9 ; + RECT 139.365 0.18 139.625 12.9 ; + RECT 138.155 384.61 138.355 385.34 ; + RECT 138.565 384.61 138.925 385.34 ; + RECT 139.135 384.61 139.335 385.34 ; + RECT 139.79 384.61 139.99 385.34 ; + RECT 140.075 0.52 140.335 2.82 ; + RECT 140.2 384.61 140.56 385.34 ; + RECT 140.855 384.61 141.055 385.34 ; + RECT 141.35 384.61 141.71 385.34 ; + RECT 141.605 0.52 141.865 2.82 ; + RECT 141.92 384.61 142.12 385.34 ; + RECT 142.575 384.61 142.775 385.34 ; + RECT 143.8 0.17 144.57 0.43 ; + RECT 143.8 0.17 144.06 8.7 ; + RECT 144.31 0.17 144.57 8.7 ; + RECT 142.78 0.52 143.04 4.315 ; + RECT 144.82 0.18 145.59 0.88 ; + RECT 144.82 0.18 145.08 8.7 ; + RECT 145.33 0.18 145.59 8.7 ; + RECT 145.84 0.17 146.61 0.43 ; + RECT 145.84 0.17 146.1 8.7 ; + RECT 146.35 0.17 146.61 8.7 ; + RECT 146.86 0.18 147.63 0.88 ; + RECT 146.86 0.18 147.12 8.7 ; + RECT 147.37 0.18 147.63 8.7 ; + RECT 147.88 0.17 148.65 0.43 ; + RECT 147.88 0.17 148.14 8.7 ; + RECT 148.39 0.17 148.65 8.7 ; + RECT 148.9 0.18 149.67 0.88 ; + RECT 148.9 0.18 149.16 8.7 ; + RECT 149.41 0.18 149.67 8.7 ; + RECT 149.92 0.17 150.69 0.43 ; + RECT 149.92 0.17 150.18 8.7 ; + RECT 150.43 0.17 150.69 8.7 ; + RECT 150.94 0.18 151.71 0.88 ; + RECT 150.94 0.18 151.2 8.7 ; + RECT 151.45 0.18 151.71 8.7 ; + RECT 151.96 0.17 152.73 0.43 ; + RECT 151.96 0.17 152.22 8.7 ; + RECT 152.47 0.17 152.73 8.7 ; + RECT 152.98 0.18 153.75 0.88 ; + RECT 152.98 0.18 153.24 8.7 ; + RECT 153.49 0.18 153.75 8.7 ; + RECT 154 0.17 154.77 0.43 ; + RECT 154 0.17 154.26 8.7 ; + RECT 154.51 0.17 154.77 8.7 ; + RECT 155.02 0.18 155.79 0.88 ; + RECT 155.02 0.18 155.28 8.7 ; + RECT 155.53 0.18 155.79 8.7 ; + RECT 156.04 0.17 156.81 0.43 ; + RECT 156.04 0.17 156.3 8.7 ; + RECT 156.55 0.17 156.81 8.7 ; + RECT 157.06 0.18 157.83 0.88 ; + RECT 157.06 0.18 157.32 8.7 ; + RECT 157.57 0.18 157.83 8.7 ; + RECT 158.08 0.17 158.85 0.43 ; + RECT 158.08 0.17 158.34 8.7 ; + RECT 158.59 0.17 158.85 8.7 ; + RECT 159.1 0.18 159.87 0.88 ; + RECT 159.1 0.18 159.36 8.7 ; + RECT 159.61 0.18 159.87 8.7 ; + RECT 142.985 384.61 143.345 385.34 ; + RECT 143.555 384.61 143.755 385.34 ; + RECT 161.495 0.18 162.265 0.88 ; + RECT 161.495 0.18 161.755 8.7 ; + RECT 162.005 0.18 162.265 8.7 ; + RECT 162.515 0.17 163.285 0.43 ; + RECT 162.515 0.17 162.775 8.7 ; + RECT 163.025 0.17 163.285 8.7 ; + RECT 144.38 384.53 144.58 385.34 ; + RECT 160.475 0.3 160.735 8.7 ; + RECT 164.555 0.18 165.325 0.88 ; + RECT 164.555 0.18 164.815 8.7 ; + RECT 165.065 0.18 165.325 8.7 ; + RECT 160.985 0.3 161.245 8.7 ; + RECT 163.535 0 163.795 8.7 ; + RECT 164.045 0 164.305 8.7 ; + RECT 165.575 0.52 165.835 8.7 ; + RECT 166.085 0.3 166.345 8.7 ; + RECT 166.595 0.3 166.855 8.7 ; + RECT 167.105 0.3 167.365 8.7 ; + RECT 167.615 0.3 167.875 8.7 ; + RECT 168.125 0.3 168.385 8.7 ; + RECT 168.635 0.3 168.895 8.7 ; + RECT 169.145 0.3 169.405 8.7 ; + RECT 171.185 0.18 171.955 0.88 ; + RECT 171.185 0.18 171.445 8.7 ; + RECT 171.695 0.18 171.955 8.7 ; + RECT 169.655 0.3 169.915 8.7 ; + RECT 170.165 0.52 170.425 8.7 ; + RECT 170.675 0.52 170.935 8.7 ; + RECT 172.205 0.52 172.465 8.7 ; + RECT 172.715 0.52 172.975 8.7 ; + RECT 173.225 0.52 173.485 8.7 ; + RECT 173.735 0.52 173.995 8.7 ; + RECT 174.245 0.52 174.505 8.7 ; + RECT 174.755 0.52 175.015 8.7 ; + RECT 175.265 0.52 175.525 8.7 ; + RECT 175.775 0.52 176.035 8.7 ; + RECT 176.285 0.52 176.545 8.7 ; + RECT 176.795 0.52 177.055 8.7 ; + RECT 177.305 0.3 177.565 8.7 ; + RECT 177.815 0.3 178.075 8.7 ; + RECT 178.325 0.3 178.585 8.7 ; + RECT 178.835 0.52 179.095 8.7 ; + RECT 179.345 0.52 179.605 8.7 ; + RECT 179.855 0.3 180.115 8.7 ; + RECT 180.365 0.3 180.625 8.7 ; + RECT 180.875 0.3 181.135 8.7 ; + RECT 181.385 0.52 181.645 8.7 ; + RECT 181.895 0.52 182.155 8.7 ; + RECT 182.405 0.3 182.665 8.7 ; + RECT 182.915 0.52 183.175 8.7 ; + RECT 183.425 0.52 183.685 8.7 ; + RECT 183.935 0.52 184.195 8.7 ; + RECT 184.445 0.52 184.705 8.7 ; + RECT 184.955 0.52 185.215 8.7 ; + RECT 185.465 0.3 185.725 8.7 ; + RECT 185.975 0.52 186.235 8.7 ; + RECT 186.485 0.52 186.745 8.7 ; + RECT 186.995 0.3 187.255 8.7 ; + RECT 187.505 0.52 187.765 8.7 ; + RECT 189.545 0.17 190.315 0.43 ; + RECT 189.545 0.17 189.805 8.7 ; + RECT 190.055 0.17 190.315 8.7 ; + RECT 188.015 0.52 188.275 8.7 ; + RECT 188.525 0.3 188.785 8.7 ; + RECT 189.035 0.3 189.295 8.7 ; + RECT 192.095 0.17 192.865 0.43 ; + RECT 192.095 0.17 192.355 8.7 ; + RECT 192.605 0.17 192.865 8.7 ; + RECT 190.565 0.3 190.825 8.7 ; + RECT 193.625 0.18 194.395 0.88 ; + RECT 193.625 0.18 193.885 8.7 ; + RECT 194.135 0.18 194.395 8.7 ; + RECT 191.075 0.3 191.335 8.7 ; + RECT 191.585 0.3 191.845 8.7 ; + RECT 193.115 0.3 193.375 8.7 ; + RECT 194.645 0 194.905 8.7 ; + RECT 195.155 0 195.415 8.7 ; + RECT 195.665 0.52 195.925 8.7 ; + RECT 196.175 0.52 196.435 8.7 ; + RECT 196.685 0.52 196.945 8.7 ; + RECT 197.195 0.52 197.455 8.7 ; + RECT 197.705 0 197.965 8.7 ; + RECT 198.215 0 198.475 8.7 ; + RECT 198.725 0.3 198.985 8.7 ; + RECT 199.235 0.3 199.495 8.7 ; + RECT 199.745 0 200.005 8.7 ; + RECT 200.255 0 200.515 8.7 ; + RECT 200.765 0.3 201.025 8.7 ; + RECT 201.585 0.3 201.845 8.7 ; + RECT 202.095 0 202.355 8.7 ; + RECT 202.605 0 202.865 8.7 ; + RECT 203.115 0.3 203.375 8.7 ; + RECT 203.625 0.3 203.885 8.7 ; + RECT 204.135 0 204.395 8.7 ; + RECT 204.645 0 204.905 8.7 ; + RECT 205.155 0.52 205.415 8.7 ; + RECT 205.665 0.52 205.925 8.7 ; + RECT 206.175 0.52 206.435 8.7 ; + RECT 208.215 0.18 208.985 0.88 ; + RECT 208.215 0.18 208.475 8.7 ; + RECT 208.725 0.18 208.985 8.7 ; + RECT 206.685 0.52 206.945 8.7 ; + RECT 209.745 0.17 210.515 0.43 ; + RECT 209.745 0.17 210.005 8.7 ; + RECT 210.255 0.17 210.515 8.7 ; + RECT 207.195 0 207.455 8.7 ; + RECT 207.705 0 207.965 8.7 ; + RECT 209.235 0.3 209.495 8.7 ; + RECT 212.295 0.17 213.065 0.43 ; + RECT 212.295 0.17 212.555 8.7 ; + RECT 212.805 0.17 213.065 8.7 ; + RECT 210.765 0.3 211.025 8.7 ; + RECT 211.275 0.3 211.535 8.7 ; + RECT 211.785 0.3 212.045 8.7 ; + RECT 213.315 0.3 213.575 8.7 ; + RECT 213.825 0.3 214.085 8.7 ; + RECT 214.335 0.52 214.595 8.7 ; + RECT 214.845 0.52 215.105 8.7 ; + RECT 215.355 0.3 215.615 8.7 ; + RECT 215.865 0.52 216.125 8.7 ; + RECT 216.375 0.52 216.635 8.7 ; + RECT 216.885 0.3 217.145 8.7 ; + RECT 217.395 0.52 217.655 8.7 ; + RECT 217.905 0.52 218.165 8.7 ; + RECT 218.415 0.52 218.675 8.7 ; + RECT 218.925 0.52 219.185 8.7 ; + RECT 219.435 0.52 219.695 8.7 ; + RECT 219.945 0.3 220.205 8.7 ; + RECT 220.455 0.52 220.715 8.7 ; + RECT 220.965 0.52 221.225 8.7 ; + RECT 221.475 0.3 221.735 8.7 ; + RECT 221.985 0.3 222.245 8.7 ; + RECT 222.495 0.3 222.755 8.7 ; + RECT 223.005 0.52 223.265 8.7 ; + RECT 223.515 0.52 223.775 8.7 ; + RECT 224.025 0.3 224.285 8.7 ; + RECT 224.535 0.3 224.795 8.7 ; + RECT 225.045 0.3 225.305 8.7 ; + RECT 225.555 0.52 225.815 8.7 ; + RECT 226.065 0.52 226.325 8.7 ; + RECT 226.575 0.52 226.835 8.7 ; + RECT 227.085 0.52 227.345 8.7 ; + RECT 227.595 0.52 227.855 8.7 ; + RECT 228.105 0.52 228.365 8.7 ; + RECT 228.615 0.52 228.875 8.7 ; + RECT 230.655 0.18 231.425 0.88 ; + RECT 230.655 0.18 230.915 8.7 ; + RECT 231.165 0.18 231.425 8.7 ; + RECT 229.125 0.52 229.385 8.7 ; + RECT 229.635 0.52 229.895 8.7 ; + RECT 230.145 0.52 230.405 8.7 ; + RECT 231.675 0.52 231.935 8.7 ; + RECT 232.185 0.52 232.445 8.7 ; + RECT 232.695 0.3 232.955 8.7 ; + RECT 233.205 0.3 233.465 8.7 ; + RECT 233.715 0.3 233.975 8.7 ; + RECT 234.225 0.3 234.485 8.7 ; + RECT 234.735 0.3 234.995 8.7 ; + RECT 235.245 0.3 235.505 8.7 ; + RECT 237.285 0.18 238.055 0.88 ; + RECT 237.285 0.18 237.545 8.7 ; + RECT 237.795 0.18 238.055 8.7 ; + RECT 235.755 0.3 236.015 8.7 ; + RECT 236.265 0.3 236.525 8.7 ; + RECT 239.325 0.17 240.095 0.43 ; + RECT 239.325 0.17 239.585 8.7 ; + RECT 239.835 0.17 240.095 8.7 ; + RECT 240.345 0.18 241.115 0.88 ; + RECT 240.345 0.18 240.605 8.7 ; + RECT 240.855 0.18 241.115 8.7 ; + RECT 236.775 0.52 237.035 8.7 ; + RECT 238.305 0 238.565 8.7 ; + RECT 242.74 0.18 243.51 0.88 ; + RECT 242.74 0.18 243 8.7 ; + RECT 243.25 0.18 243.51 8.7 ; + RECT 243.76 0.17 244.53 0.43 ; + RECT 243.76 0.17 244.02 8.7 ; + RECT 244.27 0.17 244.53 8.7 ; + RECT 244.78 0.18 245.55 0.88 ; + RECT 244.78 0.18 245.04 8.7 ; + RECT 245.29 0.18 245.55 8.7 ; + RECT 245.8 0.17 246.57 0.43 ; + RECT 245.8 0.17 246.06 8.7 ; + RECT 246.31 0.17 246.57 8.7 ; + RECT 246.82 0.18 247.59 0.88 ; + RECT 246.82 0.18 247.08 8.7 ; + RECT 247.33 0.18 247.59 8.7 ; + RECT 247.84 0.17 248.61 0.43 ; + RECT 247.84 0.17 248.1 8.7 ; + RECT 248.35 0.17 248.61 8.7 ; + RECT 248.86 0.18 249.63 0.88 ; + RECT 248.86 0.18 249.12 8.7 ; + RECT 249.37 0.18 249.63 8.7 ; + RECT 249.88 0.17 250.65 0.43 ; + RECT 249.88 0.17 250.14 8.7 ; + RECT 250.39 0.17 250.65 8.7 ; + RECT 250.9 0.18 251.67 0.88 ; + RECT 250.9 0.18 251.16 8.7 ; + RECT 251.41 0.18 251.67 8.7 ; + RECT 251.92 0.17 252.69 0.43 ; + RECT 251.92 0.17 252.18 8.7 ; + RECT 252.43 0.17 252.69 8.7 ; + RECT 252.94 0.18 253.71 0.88 ; + RECT 252.94 0.18 253.2 8.7 ; + RECT 253.45 0.18 253.71 8.7 ; + RECT 253.96 0.17 254.73 0.43 ; + RECT 253.96 0.17 254.22 8.7 ; + RECT 254.47 0.17 254.73 8.7 ; + RECT 254.98 0.18 255.75 0.88 ; + RECT 254.98 0.18 255.24 8.7 ; + RECT 255.49 0.18 255.75 8.7 ; + RECT 256 0.17 256.77 0.43 ; + RECT 256 0.17 256.26 8.7 ; + RECT 256.51 0.17 256.77 8.7 ; + RECT 257.02 0.18 257.79 0.88 ; + RECT 257.02 0.18 257.28 8.7 ; + RECT 257.53 0.18 257.79 8.7 ; + RECT 238.815 0 239.075 8.7 ; + RECT 258.04 0.17 258.81 0.43 ; + RECT 258.04 0.17 258.3 8.7 ; + RECT 258.55 0.17 258.81 8.7 ; + RECT 241.365 0.3 241.625 8.7 ; + RECT 241.875 0.3 242.135 8.7 ; + RECT 258.03 384.53 258.23 385.34 ; + RECT 258.855 384.61 259.055 385.34 ; + RECT 259.265 384.61 259.625 385.34 ; + RECT 259.57 0.52 259.83 4.315 ; + RECT 259.835 384.61 260.035 385.34 ; + RECT 260.49 384.61 260.69 385.34 ; + RECT 260.745 0.52 261.005 2.82 ; + RECT 260.9 384.61 261.26 385.34 ; + RECT 261.555 384.61 261.755 385.34 ; + RECT 262.05 384.61 262.41 385.34 ; + RECT 262.985 0.18 263.755 0.88 ; + RECT 262.985 0.18 263.245 12.9 ; + RECT 263.495 0.18 263.755 12.9 ; + RECT 262.275 0.52 262.535 2.82 ; + RECT 262.62 384.61 262.82 385.34 ; + RECT 264.005 0.155 264.775 0.445 ; + RECT 264.005 0.155 264.265 13.21 ; + RECT 264.515 0.155 264.775 13.21 ; + RECT 263.275 384.61 263.475 385.34 ; + RECT 263.685 384.61 264.045 385.34 ; + RECT 264.255 384.61 264.455 385.34 ; + RECT 264.91 384.61 265.11 385.34 ; + RECT 265.32 384.61 265.68 385.34 ; + RECT 265.975 384.61 266.175 385.34 ; + RECT 266.47 384.61 266.83 385.34 ; + RECT 266.71 0.52 266.97 14.115 ; + RECT 267.04 384.61 267.24 385.34 ; + RECT 267.22 0.52 267.48 13.45 ; + RECT 267.695 384.61 267.895 385.34 ; + RECT 268.24 0.155 269.01 0.445 ; + RECT 268.24 0.155 268.5 8.665 ; + RECT 268.75 0.155 269.01 8.665 ; + RECT 267.73 0.52 267.99 11.315 ; + RECT 268.105 384.61 268.465 385.34 ; + RECT 268.675 384.61 268.875 385.34 ; + RECT 269.26 0.52 269.52 9.955 ; + RECT 269.33 384.61 269.53 385.34 ; + RECT 269.74 384.61 270.1 385.34 ; + RECT 270.395 384.61 270.595 385.34 ; + RECT 270.89 384.61 271.25 385.34 ; + RECT 271.3 0.3 271.56 8.7 ; + RECT 271.46 384.61 271.66 385.34 ; + RECT 272.115 384.61 272.315 385.34 ; + RECT 271.81 0.18 272.58 0.88 ; + RECT 272.525 384.61 272.885 385.34 ; + RECT 273.095 384.61 273.295 385.34 ; + RECT 273.75 384.61 273.95 385.34 ; + RECT 274.005 0.52 274.265 6.28 ; + RECT 274.16 384.61 274.52 385.34 ; + RECT 274.815 384.61 275.015 385.34 ; + RECT 275.38 0.52 275.64 5.57 ; + RECT 275.31 384.61 275.67 385.34 ; + RECT 275.88 384.61 276.08 385.34 ; + RECT 275.89 0.3 276.15 5.235 ; + RECT 276.4 0.52 276.66 7.78 ; + RECT 276.535 384.61 276.735 385.34 ; + RECT 276.945 384.61 277.305 385.34 ; + RECT 277.25 0.52 277.51 4.315 ; + RECT 277.515 384.61 277.715 385.34 ; + RECT 278.17 384.61 278.37 385.34 ; + RECT 278.425 0.52 278.685 2.82 ; + RECT 278.58 384.61 278.94 385.34 ; + RECT 279.235 384.61 279.435 385.34 ; + RECT 279.73 384.61 280.09 385.34 ; + RECT 280.665 0.18 281.435 0.88 ; + RECT 280.665 0.18 280.925 12.9 ; + RECT 281.175 0.18 281.435 12.9 ; + RECT 279.955 0.52 280.215 2.82 ; + RECT 280.3 384.61 280.5 385.34 ; + RECT 281.685 0.155 282.455 0.445 ; + RECT 281.685 0.155 281.945 13.21 ; + RECT 282.195 0.155 282.455 13.21 ; + RECT 280.955 384.61 281.155 385.34 ; + RECT 281.365 384.61 281.725 385.34 ; + RECT 281.935 384.61 282.135 385.34 ; + RECT 282.59 384.61 282.79 385.34 ; + RECT 283 384.61 283.36 385.34 ; + RECT 283.655 384.61 283.855 385.34 ; + RECT 284.15 384.61 284.51 385.34 ; + RECT 284.39 0.52 284.65 14.115 ; + RECT 284.72 384.61 284.92 385.34 ; + RECT 284.9 0.52 285.16 13.45 ; + RECT 285.375 384.61 285.575 385.34 ; + RECT 285.92 0.155 286.69 0.445 ; + RECT 285.92 0.155 286.18 8.665 ; + RECT 286.43 0.155 286.69 8.665 ; + RECT 285.41 0.52 285.67 11.315 ; + RECT 285.785 384.61 286.145 385.34 ; + RECT 286.355 384.61 286.555 385.34 ; + RECT 286.94 0.52 287.2 9.955 ; + RECT 287.01 384.61 287.21 385.34 ; + RECT 287.42 384.61 287.78 385.34 ; + RECT 288.075 384.61 288.275 385.34 ; + RECT 288.57 384.61 288.93 385.34 ; + RECT 288.98 0.3 289.24 8.7 ; + RECT 289.14 384.61 289.34 385.34 ; + RECT 289.795 384.61 289.995 385.34 ; + RECT 289.49 0.18 290.26 0.88 ; + RECT 290.205 384.61 290.565 385.34 ; + RECT 290.775 384.61 290.975 385.34 ; + RECT 291.43 384.61 291.63 385.34 ; + RECT 291.685 0.52 291.945 6.28 ; + RECT 291.84 384.61 292.2 385.34 ; + RECT 292.495 384.61 292.695 385.34 ; + RECT 293.06 0.52 293.32 5.57 ; + RECT 292.99 384.61 293.35 385.34 ; + RECT 293.56 384.61 293.76 385.34 ; + RECT 293.57 0.3 293.83 5.235 ; + RECT 294.08 0.52 294.34 7.78 ; + RECT 294.215 384.61 294.415 385.34 ; + RECT 294.625 384.61 294.985 385.34 ; + RECT 294.93 0.52 295.19 4.315 ; + RECT 295.195 384.61 295.395 385.34 ; + RECT 295.85 384.61 296.05 385.34 ; + RECT 296.105 0.52 296.365 2.82 ; + RECT 296.26 384.61 296.62 385.34 ; + RECT 296.915 384.61 297.115 385.34 ; + RECT 297.41 384.61 297.77 385.34 ; + RECT 298.345 0.18 299.115 0.88 ; + RECT 298.345 0.18 298.605 12.9 ; + RECT 298.855 0.18 299.115 12.9 ; + RECT 297.635 0.52 297.895 2.82 ; + RECT 297.98 384.61 298.18 385.34 ; + RECT 299.365 0.155 300.135 0.445 ; + RECT 299.365 0.155 299.625 13.21 ; + RECT 299.875 0.155 300.135 13.21 ; + RECT 298.635 384.61 298.835 385.34 ; + RECT 299.045 384.61 299.405 385.34 ; + RECT 299.615 384.61 299.815 385.34 ; + RECT 300.27 384.61 300.47 385.34 ; + RECT 300.68 384.61 301.04 385.34 ; + RECT 301.335 384.61 301.535 385.34 ; + RECT 301.83 384.61 302.19 385.34 ; + RECT 302.07 0.52 302.33 14.115 ; + RECT 302.4 384.61 302.6 385.34 ; + RECT 302.58 0.52 302.84 13.45 ; + RECT 303.055 384.61 303.255 385.34 ; + RECT 303.6 0.155 304.37 0.445 ; + RECT 303.6 0.155 303.86 8.665 ; + RECT 304.11 0.155 304.37 8.665 ; + RECT 303.09 0.52 303.35 11.315 ; + RECT 303.465 384.61 303.825 385.34 ; + RECT 304.035 384.61 304.235 385.34 ; + RECT 304.62 0.52 304.88 9.955 ; + RECT 304.69 384.61 304.89 385.34 ; + RECT 305.1 384.61 305.46 385.34 ; + RECT 305.755 384.61 305.955 385.34 ; + RECT 306.25 384.61 306.61 385.34 ; + RECT 306.66 0.3 306.92 8.7 ; + RECT 306.82 384.61 307.02 385.34 ; + RECT 307.475 384.61 307.675 385.34 ; + RECT 307.17 0.18 307.94 0.88 ; + RECT 307.885 384.61 308.245 385.34 ; + RECT 308.455 384.61 308.655 385.34 ; + RECT 309.11 384.61 309.31 385.34 ; + RECT 309.365 0.52 309.625 6.28 ; + RECT 309.52 384.61 309.88 385.34 ; + RECT 310.175 384.61 310.375 385.34 ; + RECT 310.74 0.52 311 5.57 ; + RECT 310.67 384.61 311.03 385.34 ; + RECT 311.24 384.61 311.44 385.34 ; + RECT 311.25 0.3 311.51 5.235 ; + RECT 311.76 0.52 312.02 7.78 ; + RECT 311.895 384.61 312.095 385.34 ; + RECT 312.305 384.61 312.665 385.34 ; + RECT 312.61 0.52 312.87 4.315 ; + RECT 312.875 384.61 313.075 385.34 ; + RECT 313.53 384.61 313.73 385.34 ; + RECT 313.785 0.52 314.045 2.82 ; + RECT 313.94 384.61 314.3 385.34 ; + RECT 314.595 384.61 314.795 385.34 ; + RECT 315.09 384.61 315.45 385.34 ; + RECT 316.025 0.18 316.795 0.88 ; + RECT 316.025 0.18 316.285 12.9 ; + RECT 316.535 0.18 316.795 12.9 ; + RECT 315.315 0.52 315.575 2.82 ; + RECT 315.66 384.61 315.86 385.34 ; + RECT 317.045 0.155 317.815 0.445 ; + RECT 317.045 0.155 317.305 13.21 ; + RECT 317.555 0.155 317.815 13.21 ; + RECT 316.315 384.61 316.515 385.34 ; + RECT 316.725 384.61 317.085 385.34 ; + RECT 317.295 384.61 317.495 385.34 ; + RECT 317.95 384.61 318.15 385.34 ; + RECT 318.36 384.61 318.72 385.34 ; + RECT 319.015 384.61 319.215 385.34 ; + RECT 319.51 384.61 319.87 385.34 ; + RECT 319.75 0.52 320.01 14.115 ; + RECT 320.08 384.61 320.28 385.34 ; + RECT 320.26 0.52 320.52 13.45 ; + RECT 320.735 384.61 320.935 385.34 ; + RECT 321.28 0.155 322.05 0.445 ; + RECT 321.28 0.155 321.54 8.665 ; + RECT 321.79 0.155 322.05 8.665 ; + RECT 320.77 0.52 321.03 11.315 ; + RECT 321.145 384.61 321.505 385.34 ; + RECT 321.715 384.61 321.915 385.34 ; + RECT 322.3 0.52 322.56 9.955 ; + RECT 322.37 384.61 322.57 385.34 ; + RECT 322.78 384.61 323.14 385.34 ; + RECT 323.435 384.61 323.635 385.34 ; + RECT 323.93 384.61 324.29 385.34 ; + RECT 324.34 0.3 324.6 8.7 ; + RECT 324.5 384.61 324.7 385.34 ; + RECT 325.155 384.61 325.355 385.34 ; + RECT 324.85 0.18 325.62 0.88 ; + RECT 325.565 384.61 325.925 385.34 ; + RECT 326.135 384.61 326.335 385.34 ; + RECT 326.79 384.61 326.99 385.34 ; + RECT 327.045 0.52 327.305 6.28 ; + RECT 327.2 384.61 327.56 385.34 ; + RECT 327.855 384.61 328.055 385.34 ; + RECT 328.42 0.52 328.68 5.57 ; + RECT 328.35 384.61 328.71 385.34 ; + RECT 328.92 384.61 329.12 385.34 ; + RECT 328.93 0.3 329.19 5.235 ; + RECT 329.44 0.52 329.7 7.78 ; + RECT 329.575 384.61 329.775 385.34 ; + RECT 329.985 384.61 330.345 385.34 ; + RECT 330.29 0.52 330.55 4.315 ; + RECT 330.555 384.61 330.755 385.34 ; + RECT 331.21 384.61 331.41 385.34 ; + RECT 331.465 0.52 331.725 2.82 ; + RECT 331.62 384.61 331.98 385.34 ; + RECT 332.275 384.61 332.475 385.34 ; + RECT 332.77 384.61 333.13 385.34 ; + RECT 333.705 0.18 334.475 0.88 ; + RECT 333.705 0.18 333.965 12.9 ; + RECT 334.215 0.18 334.475 12.9 ; + RECT 332.995 0.52 333.255 2.82 ; + RECT 333.34 384.61 333.54 385.34 ; + RECT 334.725 0.155 335.495 0.445 ; + RECT 334.725 0.155 334.985 13.21 ; + RECT 335.235 0.155 335.495 13.21 ; + RECT 333.995 384.61 334.195 385.34 ; + RECT 334.405 384.61 334.765 385.34 ; + RECT 334.975 384.61 335.175 385.34 ; + RECT 335.63 384.61 335.83 385.34 ; + RECT 336.04 384.61 336.4 385.34 ; + RECT 336.695 384.61 336.895 385.34 ; + RECT 337.19 384.61 337.55 385.34 ; + RECT 337.43 0.52 337.69 14.115 ; + RECT 337.76 384.61 337.96 385.34 ; + RECT 337.94 0.52 338.2 13.45 ; + RECT 338.415 384.61 338.615 385.34 ; + RECT 338.96 0.155 339.73 0.445 ; + RECT 338.96 0.155 339.22 8.665 ; + RECT 339.47 0.155 339.73 8.665 ; + RECT 338.45 0.52 338.71 11.315 ; + RECT 338.825 384.61 339.185 385.34 ; + RECT 339.395 384.61 339.595 385.34 ; + RECT 339.98 0.52 340.24 9.955 ; + RECT 340.05 384.61 340.25 385.34 ; + RECT 340.46 384.61 340.82 385.34 ; + RECT 341.115 384.61 341.315 385.34 ; + RECT 341.61 384.61 341.97 385.34 ; + RECT 342.02 0.3 342.28 8.7 ; + RECT 342.18 384.61 342.38 385.34 ; + RECT 342.835 384.61 343.035 385.34 ; + RECT 342.53 0.18 343.3 0.88 ; + RECT 343.245 384.61 343.605 385.34 ; + RECT 343.815 384.61 344.015 385.34 ; + RECT 344.47 384.61 344.67 385.34 ; + RECT 344.725 0.52 344.985 6.28 ; + RECT 344.88 384.61 345.24 385.34 ; + RECT 345.535 384.61 345.735 385.34 ; + RECT 346.1 0.52 346.36 5.57 ; + RECT 346.03 384.61 346.39 385.34 ; + RECT 346.6 384.61 346.8 385.34 ; + RECT 346.61 0.3 346.87 5.235 ; + RECT 347.12 0.52 347.38 7.78 ; + RECT 347.255 384.61 347.455 385.34 ; + RECT 347.665 384.61 348.025 385.34 ; + RECT 347.97 0.52 348.23 4.315 ; + RECT 348.235 384.61 348.435 385.34 ; + RECT 348.89 384.61 349.09 385.34 ; + RECT 349.145 0.52 349.405 2.82 ; + RECT 349.3 384.61 349.66 385.34 ; + RECT 349.955 384.61 350.155 385.34 ; + RECT 350.45 384.61 350.81 385.34 ; + RECT 351.385 0.18 352.155 0.88 ; + RECT 351.385 0.18 351.645 12.9 ; + RECT 351.895 0.18 352.155 12.9 ; + RECT 350.675 0.52 350.935 2.82 ; + RECT 351.02 384.61 351.22 385.34 ; + RECT 352.405 0.155 353.175 0.445 ; + RECT 352.405 0.155 352.665 13.21 ; + RECT 352.915 0.155 353.175 13.21 ; + RECT 351.675 384.61 351.875 385.34 ; + RECT 352.085 384.61 352.445 385.34 ; + RECT 352.655 384.61 352.855 385.34 ; + RECT 353.31 384.61 353.51 385.34 ; + RECT 353.72 384.61 354.08 385.34 ; + RECT 354.375 384.61 354.575 385.34 ; + RECT 354.87 384.61 355.23 385.34 ; + RECT 355.11 0.52 355.37 14.115 ; + RECT 355.44 384.61 355.64 385.34 ; + RECT 355.62 0.52 355.88 13.45 ; + RECT 356.095 384.61 356.295 385.34 ; + RECT 356.64 0.155 357.41 0.445 ; + RECT 356.64 0.155 356.9 8.665 ; + RECT 357.15 0.155 357.41 8.665 ; + RECT 356.13 0.52 356.39 11.315 ; + RECT 356.505 384.61 356.865 385.34 ; + RECT 357.075 384.61 357.275 385.34 ; + RECT 357.66 0.52 357.92 9.955 ; + RECT 357.73 384.61 357.93 385.34 ; + RECT 358.14 384.61 358.5 385.34 ; + RECT 358.795 384.61 358.995 385.34 ; + RECT 359.29 384.61 359.65 385.34 ; + RECT 359.7 0.3 359.96 8.7 ; + RECT 359.86 384.61 360.06 385.34 ; + RECT 360.515 384.61 360.715 385.34 ; + RECT 360.21 0.18 360.98 0.88 ; + RECT 360.925 384.61 361.285 385.34 ; + RECT 361.495 384.61 361.695 385.34 ; + RECT 362.15 384.61 362.35 385.34 ; + RECT 362.405 0.52 362.665 6.28 ; + RECT 362.56 384.61 362.92 385.34 ; + RECT 363.215 384.61 363.415 385.34 ; + RECT 363.78 0.52 364.04 5.57 ; + RECT 363.71 384.61 364.07 385.34 ; + RECT 364.28 384.61 364.48 385.34 ; + RECT 364.29 0.3 364.55 5.235 ; + RECT 364.8 0.52 365.06 7.78 ; + RECT 364.935 384.61 365.135 385.34 ; + RECT 365.345 384.61 365.705 385.34 ; + RECT 365.65 0.52 365.91 4.315 ; + RECT 365.915 384.61 366.115 385.34 ; + RECT 366.57 384.61 366.77 385.34 ; + RECT 366.825 0.52 367.085 2.82 ; + RECT 366.98 384.61 367.34 385.34 ; + RECT 367.635 384.61 367.835 385.34 ; + RECT 368.13 384.61 368.49 385.34 ; + RECT 369.065 0.18 369.835 0.88 ; + RECT 369.065 0.18 369.325 12.9 ; + RECT 369.575 0.18 369.835 12.9 ; + RECT 368.355 0.52 368.615 2.82 ; + RECT 368.7 384.61 368.9 385.34 ; + RECT 370.085 0.155 370.855 0.445 ; + RECT 370.085 0.155 370.345 13.21 ; + RECT 370.595 0.155 370.855 13.21 ; + RECT 369.355 384.61 369.555 385.34 ; + RECT 369.765 384.61 370.125 385.34 ; + RECT 370.335 384.61 370.535 385.34 ; + RECT 370.99 384.61 371.19 385.34 ; + RECT 371.4 384.61 371.76 385.34 ; + RECT 372.055 384.61 372.255 385.34 ; + RECT 372.55 384.61 372.91 385.34 ; + RECT 372.79 0.52 373.05 14.115 ; + RECT 373.12 384.61 373.32 385.34 ; + RECT 373.3 0.52 373.56 13.45 ; + RECT 373.775 384.61 373.975 385.34 ; + RECT 374.32 0.155 375.09 0.445 ; + RECT 374.32 0.155 374.58 8.665 ; + RECT 374.83 0.155 375.09 8.665 ; + RECT 373.81 0.52 374.07 11.315 ; + RECT 374.185 384.61 374.545 385.34 ; + RECT 374.755 384.61 374.955 385.34 ; + RECT 375.34 0.52 375.6 9.955 ; + RECT 375.41 384.61 375.61 385.34 ; + RECT 375.82 384.61 376.18 385.34 ; + RECT 376.475 384.61 376.675 385.34 ; + RECT 376.97 384.61 377.33 385.34 ; + RECT 377.38 0.3 377.64 8.7 ; + RECT 377.54 384.61 377.74 385.34 ; + RECT 378.195 384.61 378.395 385.34 ; + RECT 377.89 0.18 378.66 0.88 ; + RECT 378.605 384.61 378.965 385.34 ; + RECT 379.175 384.61 379.375 385.34 ; + RECT 379.83 384.61 380.03 385.34 ; + RECT 380.085 0.52 380.345 6.28 ; + RECT 380.24 384.61 380.6 385.34 ; + RECT 380.895 384.61 381.095 385.34 ; + RECT 381.46 0.52 381.72 5.57 ; + RECT 381.39 384.61 381.75 385.34 ; + RECT 381.96 384.61 382.16 385.34 ; + RECT 381.97 0.3 382.23 5.235 ; + RECT 382.48 0.52 382.74 7.78 ; + RECT 382.615 384.61 382.815 385.34 ; + RECT 383.025 384.61 383.385 385.34 ; + RECT 383.33 0.52 383.59 4.315 ; + RECT 383.595 384.61 383.795 385.34 ; + RECT 384.25 384.61 384.45 385.34 ; + RECT 384.505 0.52 384.765 2.82 ; + RECT 384.66 384.61 385.02 385.34 ; + RECT 385.315 384.61 385.515 385.34 ; + RECT 385.81 384.61 386.17 385.34 ; + RECT 386.745 0.18 387.515 0.88 ; + RECT 386.745 0.18 387.005 12.9 ; + RECT 387.255 0.18 387.515 12.9 ; + RECT 386.035 0.52 386.295 2.82 ; + RECT 386.38 384.61 386.58 385.34 ; + RECT 387.765 0.155 388.535 0.445 ; + RECT 387.765 0.155 388.025 13.21 ; + RECT 388.275 0.155 388.535 13.21 ; + RECT 387.035 384.61 387.235 385.34 ; + RECT 387.445 384.61 387.805 385.34 ; + RECT 388.015 384.61 388.215 385.34 ; + RECT 388.67 384.61 388.87 385.34 ; + RECT 389.08 384.61 389.44 385.34 ; + RECT 389.735 384.61 389.935 385.34 ; + RECT 390.23 384.61 390.59 385.34 ; + RECT 390.47 0.52 390.73 14.115 ; + RECT 390.8 384.61 391 385.34 ; + RECT 390.98 0.52 391.24 13.45 ; + RECT 391.455 384.61 391.655 385.34 ; + RECT 392 0.155 392.77 0.445 ; + RECT 392 0.155 392.26 8.665 ; + RECT 392.51 0.155 392.77 8.665 ; + RECT 391.49 0.52 391.75 11.315 ; + RECT 391.865 384.61 392.225 385.34 ; + RECT 392.435 384.61 392.635 385.34 ; + RECT 393.02 0.52 393.28 9.955 ; + RECT 393.09 384.61 393.29 385.34 ; + RECT 393.5 384.61 393.86 385.34 ; + RECT 394.155 384.61 394.355 385.34 ; + RECT 394.65 384.61 395.01 385.34 ; + RECT 395.06 0.3 395.32 8.7 ; + RECT 395.22 384.61 395.42 385.34 ; + RECT 395.875 384.61 396.075 385.34 ; + RECT 395.57 0.18 396.34 0.88 ; + RECT 396.285 384.61 396.645 385.34 ; + RECT 396.855 384.61 397.055 385.34 ; + RECT 397.51 384.61 397.71 385.34 ; + RECT 397.765 0.52 398.025 6.28 ; + RECT 397.92 384.61 398.28 385.34 ; + RECT 398.575 384.61 398.775 385.34 ; + RECT 399.14 0.52 399.4 5.57 ; + RECT 399.07 384.61 399.43 385.34 ; + RECT 399.64 384.61 399.84 385.34 ; + RECT 399.65 0.3 399.91 5.235 ; + RECT 400.16 0.52 400.42 7.78 ; + RECT 400.295 384.61 400.495 385.34 ; + RECT 400.705 384.61 401.065 385.34 ; + RECT 401.275 384.61 401.475 385.34 ; + RECT 402.1 53.41 402.3 385.34 ; + LAYER Metal2 SPACING 0.21 ; + RECT 398.285 0 398.88 385.37 ; + RECT 399.65 0.3 399.91 385.37 ; + RECT 400.68 0 402.61 385.37 ; + RECT 0 0.52 402.61 385.37 ; + RECT 393.54 0 397.505 385.37 ; + RECT 392 0.155 392.77 385.37 ; + RECT 386.555 0 390.21 385.37 ; + RECT 385.025 0 385.775 385.37 ; + RECT 383.85 0 384.245 385.37 ; + RECT 381.97 0.3 382.23 385.37 ; + RECT 380.605 0 381.2 385.37 ; + RECT 375.86 0 379.825 385.37 ; + RECT 374.32 0.155 375.09 385.37 ; + RECT 368.875 0 372.53 385.37 ; + RECT 367.345 0 368.095 385.37 ; + RECT 366.17 0 366.565 385.37 ; + RECT 364.29 0.3 364.55 385.37 ; + RECT 362.925 0 363.52 385.37 ; + RECT 358.18 0 362.145 385.37 ; + RECT 356.64 0.155 357.41 385.37 ; + RECT 351.195 0 354.85 385.37 ; + RECT 349.665 0 350.415 385.37 ; + RECT 348.49 0 348.885 385.37 ; + RECT 346.61 0.3 346.87 385.37 ; + RECT 345.245 0 345.84 385.37 ; + RECT 340.5 0 344.465 385.37 ; + RECT 338.96 0.155 339.73 385.37 ; + RECT 333.515 0 337.17 385.37 ; + RECT 331.985 0 332.735 385.37 ; + RECT 330.81 0 331.205 385.37 ; + RECT 328.93 0.3 329.19 385.37 ; + RECT 327.565 0 328.16 385.37 ; + RECT 322.82 0 326.785 385.37 ; + RECT 321.28 0.155 322.05 385.37 ; + RECT 315.835 0 319.49 385.37 ; + RECT 314.305 0 315.055 385.37 ; + RECT 313.13 0 313.525 385.37 ; + RECT 311.25 0.3 311.51 385.37 ; + RECT 309.885 0 310.48 385.37 ; + RECT 305.14 0 309.105 385.37 ; + RECT 303.6 0.155 304.37 385.37 ; + RECT 298.155 0 301.81 385.37 ; + RECT 296.625 0 297.375 385.37 ; + RECT 295.45 0 295.845 385.37 ; + RECT 293.57 0.3 293.83 385.37 ; + RECT 292.205 0 292.8 385.37 ; + RECT 287.46 0 291.425 385.37 ; + RECT 285.92 0.155 286.69 385.37 ; + RECT 280.475 0 284.13 385.37 ; + RECT 278.945 0 279.695 385.37 ; + RECT 277.77 0 278.165 385.37 ; + RECT 275.89 0.3 276.15 385.37 ; + RECT 274.525 0 275.12 385.37 ; + RECT 269.78 0 273.745 385.37 ; + RECT 268.24 0.155 269.01 385.37 ; + RECT 262.795 0 266.45 385.37 ; + RECT 261.265 0 262.015 385.37 ; + RECT 260.09 0 260.485 385.37 ; + RECT 237.285 0.18 259.31 385.37 ; + RECT 237.295 0 259.31 385.37 ; + RECT 232.695 0.3 236.525 385.37 ; + RECT 230.655 0.18 231.425 385.37 ; + RECT 224.025 0.3 225.305 385.37 ; + RECT 221.475 0.3 222.755 385.37 ; + RECT 219.945 0.3 220.205 385.37 ; + RECT 216.885 0.3 217.145 385.37 ; + RECT 215.355 0.3 215.615 385.37 ; + RECT 207.195 0.3 214.085 385.37 ; + RECT 197.705 0 204.905 385.37 ; + RECT 188.525 0.3 195.415 385.37 ; + RECT 188.535 0 195.415 385.37 ; + RECT 186.995 0.3 187.255 385.37 ; + RECT 185.465 0.3 185.725 385.37 ; + RECT 182.405 0.3 182.665 385.37 ; + RECT 179.855 0.3 181.135 385.37 ; + RECT 177.305 0.3 178.585 385.37 ; + RECT 171.185 0.18 171.955 385.37 ; + RECT 166.085 0.3 169.915 385.37 ; + RECT 143.3 0.18 165.325 385.37 ; + RECT 142.125 0 142.52 385.37 ; + RECT 140.595 0 141.345 385.37 ; + RECT 136.16 0 139.815 385.37 ; + RECT 133.6 0.155 134.37 385.37 ; + RECT 128.865 0 132.83 385.37 ; + RECT 127.49 0 128.085 385.37 ; + RECT 126.46 0.3 126.72 385.37 ; + RECT 124.445 0 124.84 385.37 ; + RECT 122.915 0 123.665 385.37 ; + RECT 118.48 0 122.135 385.37 ; + RECT 115.92 0.155 116.69 385.37 ; + RECT 111.185 0 115.15 385.37 ; + RECT 109.81 0 110.405 385.37 ; + RECT 108.78 0.3 109.04 385.37 ; + RECT 106.765 0 107.16 385.37 ; + RECT 105.235 0 105.985 385.37 ; + RECT 100.8 0 104.455 385.37 ; + RECT 98.24 0.155 99.01 385.37 ; + RECT 93.505 0 97.47 385.37 ; + RECT 92.13 0 92.725 385.37 ; + RECT 91.1 0.3 91.36 385.37 ; + RECT 89.085 0 89.48 385.37 ; + RECT 87.555 0 88.305 385.37 ; + RECT 83.12 0 86.775 385.37 ; + RECT 80.56 0.155 81.33 385.37 ; + RECT 75.825 0 79.79 385.37 ; + RECT 74.45 0 75.045 385.37 ; + RECT 73.42 0.3 73.68 385.37 ; + RECT 71.405 0 71.8 385.37 ; + RECT 69.875 0 70.625 385.37 ; + RECT 65.44 0 69.095 385.37 ; + RECT 62.88 0.155 63.65 385.37 ; + RECT 58.145 0 62.11 385.37 ; + RECT 56.77 0 57.365 385.37 ; + RECT 55.74 0.3 56 385.37 ; + RECT 53.725 0 54.12 385.37 ; + RECT 52.195 0 52.945 385.37 ; + RECT 47.76 0 51.415 385.37 ; + RECT 45.2 0.155 45.97 385.37 ; + RECT 40.465 0 44.43 385.37 ; + RECT 39.09 0 39.685 385.37 ; + RECT 38.06 0.3 38.32 385.37 ; + RECT 36.045 0 36.44 385.37 ; + RECT 34.515 0 35.265 385.37 ; + RECT 30.08 0 33.735 385.37 ; + RECT 27.52 0.155 28.29 385.37 ; + RECT 22.785 0 26.75 385.37 ; + RECT 21.41 0 22.005 385.37 ; + RECT 20.38 0.3 20.64 385.37 ; + RECT 18.365 0 18.76 385.37 ; + RECT 16.835 0 17.585 385.37 ; + RECT 12.4 0 16.055 385.37 ; + RECT 9.84 0.155 10.61 385.37 ; + RECT 5.105 0 9.07 385.37 ; + RECT 3.73 0 4.325 385.37 ; + RECT 2.7 0.3 2.96 385.37 ; + RECT 0 0 1.93 385.37 ; + RECT 399.66 0 399.9 385.37 ; + RECT 381.98 0 382.22 385.37 ; + RECT 364.3 0 364.54 385.37 ; + RECT 346.62 0 346.86 385.37 ; + RECT 328.94 0 329.18 385.37 ; + RECT 311.26 0 311.5 385.37 ; + RECT 293.58 0 293.82 385.37 ; + RECT 275.9 0 276.14 385.37 ; + RECT 232.705 0 236.515 385.37 ; + RECT 224.035 0 225.295 385.37 ; + RECT 221.485 0 222.745 385.37 ; + RECT 219.955 0 220.195 385.37 ; + RECT 216.895 0 217.135 385.37 ; + RECT 215.365 0 215.605 385.37 ; + RECT 207.195 0 214.075 385.37 ; + RECT 187.005 0 187.245 385.37 ; + RECT 185.475 0 185.715 385.37 ; + RECT 182.415 0 182.655 385.37 ; + RECT 179.865 0 181.125 385.37 ; + RECT 177.315 0 178.575 385.37 ; + RECT 166.095 0 169.905 385.37 ; + RECT 126.47 0 126.71 385.37 ; + RECT 108.79 0 109.03 385.37 ; + RECT 91.11 0 91.35 385.37 ; + RECT 73.43 0 73.67 385.37 ; + RECT 55.75 0 55.99 385.37 ; + RECT 38.07 0 38.31 385.37 ; + RECT 20.39 0 20.63 385.37 ; + RECT 2.71 0 2.95 385.37 ; + RECT 230.665 0 231.415 385.37 ; + RECT 171.195 0 171.945 385.37 ; + RECT 143.3 0 165.315 385.37 ; + RECT 392.01 0 392.76 385.37 ; + RECT 374.33 0 375.08 385.37 ; + RECT 356.65 0 357.4 385.37 ; + RECT 338.97 0 339.72 385.37 ; + RECT 321.29 0 322.04 385.37 ; + RECT 303.61 0 304.36 385.37 ; + RECT 285.93 0 286.68 385.37 ; + RECT 268.25 0 269 385.37 ; + RECT 133.61 0 134.36 385.37 ; + RECT 115.93 0 116.68 385.37 ; + RECT 98.25 0 99 385.37 ; + RECT 80.57 0 81.32 385.37 ; + RECT 62.89 0 63.64 385.37 ; + RECT 45.21 0 45.96 385.37 ; + RECT 27.53 0 28.28 385.37 ; + RECT 9.85 0 10.6 385.37 ; + LAYER Metal3 ; + RECT 0 0 402.61 385.37 ; + LAYER Metal4 SPACING 0.21 ; + RECT 241.595 0 259.185 385.37 ; + RECT 236.445 0 238.265 385.37 ; + RECT 231.295 0 233.115 385.37 ; + RECT 396.725 0 402.61 385.37 ; + RECT 387.885 0 391.785 385.37 ; + RECT 387.885 47.305 402.61 53.15 ; + RECT 379.045 0 382.945 385.37 ; + RECT 370.205 0 374.105 385.37 ; + RECT 370.205 47.305 382.945 53.15 ; + RECT 361.365 0 365.265 385.37 ; + RECT 352.525 0 356.425 385.37 ; + RECT 352.525 47.305 365.265 53.15 ; + RECT 343.685 0 347.585 385.37 ; + RECT 334.845 0 338.745 385.37 ; + RECT 334.845 47.305 347.585 53.15 ; + RECT 326.005 0 329.905 385.37 ; + RECT 317.165 0 321.065 385.37 ; + RECT 317.165 47.305 329.905 53.15 ; + RECT 308.325 0 312.225 385.37 ; + RECT 299.485 0 303.385 385.37 ; + RECT 299.485 47.305 312.225 53.15 ; + RECT 290.645 0 294.545 385.37 ; + RECT 281.805 0 285.705 385.37 ; + RECT 281.805 47.305 294.545 53.15 ; + RECT 272.965 0 276.865 385.37 ; + RECT 264.125 0 268.025 385.37 ; + RECT 264.125 47.305 276.865 53.15 ; + RECT 226.145 0 227.965 385.37 ; + RECT 220.995 0 222.815 385.37 ; + RECT 215.845 0 217.665 385.37 ; + RECT 210.695 0 212.515 385.37 ; + RECT 205.545 0 207.365 385.37 ; + RECT 200.395 0 202.215 385.37 ; + RECT 195.245 0 197.065 385.37 ; + RECT 190.095 0 191.915 385.37 ; + RECT 184.945 0 186.765 385.37 ; + RECT 179.795 0 181.615 385.37 ; + RECT 174.645 0 176.465 385.37 ; + RECT 169.495 0 171.315 385.37 ; + RECT 164.345 0 166.165 385.37 ; + RECT 143.425 0 161.015 385.37 ; + RECT 134.585 0 138.485 385.37 ; + RECT 125.745 0 129.645 385.37 ; + RECT 125.745 47.305 138.485 53.15 ; + RECT 116.905 0 120.805 385.37 ; + RECT 108.065 0 111.965 385.37 ; + RECT 108.065 47.305 120.805 53.15 ; + RECT 99.225 0 103.125 385.37 ; + RECT 90.385 0 94.285 385.37 ; + RECT 90.385 47.305 103.125 53.15 ; + RECT 81.545 0 85.445 385.37 ; + RECT 72.705 0 76.605 385.37 ; + RECT 72.705 47.305 85.445 53.15 ; + RECT 63.865 0 67.765 385.37 ; + RECT 55.025 0 58.925 385.37 ; + RECT 55.025 47.305 67.765 53.15 ; + RECT 46.185 0 50.085 385.37 ; + RECT 37.345 0 41.245 385.37 ; + RECT 37.345 47.305 50.085 53.15 ; + RECT 28.505 0 32.405 385.37 ; + RECT 19.665 0 23.565 385.37 ; + RECT 19.665 47.305 32.405 53.15 ; + RECT 10.825 0 14.725 385.37 ; + RECT 0 0 5.885 385.37 ; + RECT 0 47.305 14.725 53.15 ; + END +END RM_IHPSG13_2P_1024x16_c2_bm_bist + +END LIBRARY diff --git a/flow/platforms/ihp-sg13g2/lef/RM_IHPSG13_2P_1024x32_c2_bm_bist.lef b/flow/platforms/ihp-sg13g2/lef/RM_IHPSG13_2P_1024x32_c2_bm_bist.lef new file mode 100644 index 0000000000..62442b894b --- /dev/null +++ b/flow/platforms/ihp-sg13g2/lef/RM_IHPSG13_2P_1024x32_c2_bm_bist.lef @@ -0,0 +1,7411 @@ +# ------------------------------------------------------ +# +# Copyright 2025 IHP PDK Authors +# +# Licensed under the Apache License, Version 2.0 (the "License"); +# you may not use this file except in compliance with the License. +# You may obtain a copy of the License at +# +# https://www.apache.org/licenses/LICENSE-2.0 +# +# Unless required by applicable law or agreed to in writing, software +# distributed under the License is distributed on an "AS IS" BASIS, +# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +# See the License for the specific language governing permissions and +# limitations under the License. +# +# Generated on Wed Aug 27 13:09:02 2025 +# +# ------------------------------------------------------ +VERSION 5.7 ; +BUSBITCHARS "[]" ; +DIVIDERCHAR "/" ; + +MACRO RM_IHPSG13_2P_1024x32_c2_bm_bist + CLASS BLOCK ; + ORIGIN 0 0 ; + FOREIGN RM_IHPSG13_2P_1024x32_c2_bm_bist 0 0 ; + SIZE 685.49 BY 385.37 ; + SYMMETRY X Y R90 ; + PIN A_DIN[16] + DIRECTION INPUT ; + USE SIGNAL ; + ANTENNAPARTIALMETALAREA 3.9091 LAYER Metal2 ; + ANTENNAMODEL OXIDE1 ; + ANTENNAGATEAREA 0.20085 LAYER Metal2 ; + ANTENNAMAXAREACAR 20.368932 LAYER Metal2 ; + PORT + LAYER Metal2 ; + RECT 408.15 0 408.41 0.26 ; + END + END A_DIN[16] + PIN A_DIN[15] + DIRECTION INPUT ; + USE SIGNAL ; + ANTENNAPARTIALMETALAREA 3.9091 LAYER Metal2 ; + ANTENNAMODEL OXIDE1 ; + ANTENNAGATEAREA 0.20085 LAYER Metal2 ; + ANTENNAMAXAREACAR 20.368932 LAYER Metal2 ; + PORT + LAYER Metal2 ; + RECT 277.08 0 277.34 0.26 ; + END + END A_DIN[15] + PIN A_BIST_DIN[16] + DIRECTION INPUT ; + USE SIGNAL ; + ANTENNAPARTIALMETALAREA 4.136375 LAYER Metal2 ; + ANTENNAMODEL OXIDE1 ; + ANTENNAGATEAREA 0.20085 LAYER Metal2 ; + ANTENNAMAXAREACAR 21.874907 LAYER Metal2 ; + PORT + LAYER Metal2 ; + RECT 408.66 0 408.92 0.26 ; + END + END A_BIST_DIN[16] + PIN A_BIST_DIN[15] + DIRECTION INPUT ; + USE SIGNAL ; + ANTENNAPARTIALMETALAREA 4.136375 LAYER Metal2 ; + ANTENNAMODEL OXIDE1 ; + ANTENNAGATEAREA 0.20085 LAYER Metal2 ; + ANTENNAMAXAREACAR 21.874907 LAYER Metal2 ; + PORT + LAYER Metal2 ; + RECT 276.57 0 276.83 0.26 ; + END + END A_BIST_DIN[15] + PIN A_BM[16] + DIRECTION INPUT ; + USE SIGNAL ; + ANTENNAPARTIALMETALAREA 1.7264 LAYER Metal2 ; + ANTENNAMODEL OXIDE1 ; + ANTENNAGATEAREA 0.20085 LAYER Metal2 ; + ANTENNAMAXAREACAR 9.501618 LAYER Metal2 ; + PORT + LAYER Metal2 ; + RECT 416.82 0 417.08 0.26 ; + END + END A_BM[16] + PIN A_BM[15] + DIRECTION INPUT ; + USE SIGNAL ; + ANTENNAPARTIALMETALAREA 1.7264 LAYER Metal2 ; + ANTENNAMODEL OXIDE1 ; + ANTENNAGATEAREA 0.20085 LAYER Metal2 ; + ANTENNAMAXAREACAR 9.501618 LAYER Metal2 ; + PORT + LAYER Metal2 ; + RECT 268.41 0 268.67 0.26 ; + END + END A_BM[15] + PIN A_BIST_BM[16] + DIRECTION INPUT ; + USE SIGNAL ; + ANTENNAPARTIALMETALAREA 1.7602 LAYER Metal2 ; + ANTENNAMODEL OXIDE1 ; + ANTENNAGATEAREA 0.20085 LAYER Metal2 ; + ANTENNAMAXAREACAR 9.678367 LAYER Metal2 ; + PORT + LAYER Metal2 ; + RECT 415.445 0 415.705 0.26 ; + END + END A_BIST_BM[16] + PIN A_BIST_BM[15] + DIRECTION INPUT ; + USE SIGNAL ; + ANTENNAPARTIALMETALAREA 1.7602 LAYER Metal2 ; + ANTENNAMODEL OXIDE1 ; + ANTENNAGATEAREA 0.20085 LAYER Metal2 ; + ANTENNAMAXAREACAR 9.678367 LAYER Metal2 ; + PORT + LAYER Metal2 ; + RECT 269.785 0 270.045 0.26 ; + END + END A_BIST_BM[15] + PIN A_DOUT[16] + DIRECTION OUTPUT ; + USE SIGNAL ; + ANTENNAPARTIALMETALAREA 4.8256 LAYER Metal2 ; + ANTENNADIFFAREA 0.988 LAYER Metal2 ; + PORT + LAYER Metal2 ; + RECT 401.01 0 401.27 0.26 ; + END + END A_DOUT[16] + PIN A_DOUT[15] + DIRECTION OUTPUT ; + USE SIGNAL ; + ANTENNAPARTIALMETALAREA 4.8256 LAYER Metal2 ; + ANTENNADIFFAREA 0.988 LAYER Metal2 ; + PORT + LAYER Metal2 ; + RECT 284.22 0 284.48 0.26 ; + END + END A_DOUT[15] + PIN B_DIN[16] + DIRECTION INPUT ; + USE SIGNAL ; + ANTENNAPARTIALMETALAREA 2.925 LAYER Metal2 ; + ANTENNAMODEL OXIDE1 ; + ANTENNAGATEAREA 0.20085 LAYER Metal2 ; + ANTENNAMAXAREACAR 15.469256 LAYER Metal2 ; + PORT + LAYER Metal2 ; + RECT 410.7 0 410.96 0.26 ; + END + END B_DIN[16] + PIN B_DIN[15] + DIRECTION INPUT ; + USE SIGNAL ; + ANTENNAPARTIALMETALAREA 2.925 LAYER Metal2 ; + ANTENNAMODEL OXIDE1 ; + ANTENNAGATEAREA 0.20085 LAYER Metal2 ; + ANTENNAMAXAREACAR 15.469256 LAYER Metal2 ; + PORT + LAYER Metal2 ; + RECT 274.53 0 274.79 0.26 ; + END + END B_DIN[15] + PIN B_BIST_DIN[16] + DIRECTION INPUT ; + USE SIGNAL ; + ANTENNAPARTIALMETALAREA 2.9445 LAYER Metal2 ; + ANTENNAMODEL OXIDE1 ; + ANTENNAGATEAREA 0.20085 LAYER Metal2 ; + ANTENNAMAXAREACAR 15.929052 LAYER Metal2 ; + PORT + LAYER Metal2 ; + RECT 409.17 0 409.43 0.26 ; + END + END B_BIST_DIN[16] + PIN B_BIST_DIN[15] + DIRECTION INPUT ; + USE SIGNAL ; + ANTENNAPARTIALMETALAREA 2.9445 LAYER Metal2 ; + ANTENNAMODEL OXIDE1 ; + ANTENNAGATEAREA 0.20085 LAYER Metal2 ; + ANTENNAMAXAREACAR 15.929052 LAYER Metal2 ; + PORT + LAYER Metal2 ; + RECT 276.06 0 276.32 0.26 ; + END + END B_BIST_DIN[15] + PIN B_BM[16] + DIRECTION INPUT ; + USE SIGNAL ; + ANTENNAPARTIALMETALAREA 0.7007 LAYER Metal2 ; + ANTENNAMODEL OXIDE1 ; + ANTENNAGATEAREA 0.20085 LAYER Metal2 ; + ANTENNAMAXAREACAR 4.394822 LAYER Metal2 ; + PORT + LAYER Metal2 ; + RECT 402.185 0 402.445 0.26 ; + END + END B_BM[16] + PIN B_BM[15] + DIRECTION INPUT ; + USE SIGNAL ; + ANTENNAPARTIALMETALAREA 0.7007 LAYER Metal2 ; + ANTENNAMODEL OXIDE1 ; + ANTENNAGATEAREA 0.20085 LAYER Metal2 ; + ANTENNAMAXAREACAR 4.394822 LAYER Metal2 ; + PORT + LAYER Metal2 ; + RECT 283.045 0 283.305 0.26 ; + END + END B_BM[15] + PIN B_BIST_BM[16] + DIRECTION INPUT ; + USE SIGNAL ; + ANTENNAPARTIALMETALAREA 0.7007 LAYER Metal2 ; + ANTENNAMODEL OXIDE1 ; + ANTENNAGATEAREA 0.20085 LAYER Metal2 ; + ANTENNAMAXAREACAR 4.394822 LAYER Metal2 ; + PORT + LAYER Metal2 ; + RECT 403.715 0 403.975 0.26 ; + END + END B_BIST_BM[16] + PIN B_BIST_BM[15] + DIRECTION INPUT ; + USE SIGNAL ; + ANTENNAPARTIALMETALAREA 0.7007 LAYER Metal2 ; + ANTENNAMODEL OXIDE1 ; + ANTENNAGATEAREA 0.20085 LAYER Metal2 ; + ANTENNAMAXAREACAR 4.394822 LAYER Metal2 ; + PORT + LAYER Metal2 ; + RECT 281.515 0 281.775 0.26 ; + END + END B_BIST_BM[15] + PIN B_DOUT[16] + DIRECTION OUTPUT ; + USE SIGNAL ; + ANTENNAPARTIALMETALAREA 4.836 LAYER Metal2 ; + ANTENNADIFFAREA 0.988 LAYER Metal2 ; + PORT + LAYER Metal2 ; + RECT 417.84 0 418.1 0.26 ; + END + END B_DOUT[16] + PIN B_DOUT[15] + DIRECTION OUTPUT ; + USE SIGNAL ; + ANTENNAPARTIALMETALAREA 4.836 LAYER Metal2 ; + ANTENNADIFFAREA 0.988 LAYER Metal2 ; + PORT + LAYER Metal2 ; + RECT 267.39 0 267.65 0.26 ; + END + END B_DOUT[15] + PIN VSS! + DIRECTION INOUT ; + USE GROUND ; + NETEXPR "vss VSS!" ; + PORT + LAYER Metal4 ; + RECT 666.085 0 670.505 385.37 ; + END + PORT + LAYER Metal4 ; + RECT 648.405 0 652.825 385.37 ; + END + PORT + LAYER Metal4 ; + RECT 630.725 0 635.145 385.37 ; + END + PORT + LAYER Metal4 ; + RECT 613.045 0 617.465 385.37 ; + END + PORT + LAYER Metal4 ; + RECT 595.365 0 599.785 385.37 ; + END + PORT + LAYER Metal4 ; + RECT 577.685 0 582.105 385.37 ; + END + PORT + LAYER Metal4 ; + RECT 560.005 0 564.425 385.37 ; + END + PORT + LAYER Metal4 ; + RECT 542.325 0 546.745 385.37 ; + END + PORT + LAYER Metal4 ; + RECT 524.645 0 529.065 385.37 ; + END + PORT + LAYER Metal4 ; + RECT 506.965 0 511.385 385.37 ; + END + PORT + LAYER Metal4 ; + RECT 489.285 0 493.705 385.37 ; + END + PORT + LAYER Metal4 ; + RECT 471.605 0 476.025 385.37 ; + END + PORT + LAYER Metal4 ; + RECT 453.925 0 458.345 385.37 ; + END + PORT + LAYER Metal4 ; + RECT 436.245 0 440.665 385.37 ; + END + PORT + LAYER Metal4 ; + RECT 418.565 0 422.985 385.37 ; + END + PORT + LAYER Metal4 ; + RECT 400.885 0 405.305 385.37 ; + END + PORT + LAYER Metal4 ; + RECT 379.965 0 382.775 385.37 ; + END + PORT + LAYER Metal4 ; + RECT 369.665 0 372.475 385.37 ; + END + PORT + LAYER Metal4 ; + RECT 354.215 0 357.025 385.37 ; + END + PORT + LAYER Metal4 ; + RECT 343.915 0 346.725 385.37 ; + END + PORT + LAYER Metal4 ; + RECT 338.765 0 341.575 385.37 ; + END + PORT + LAYER Metal4 ; + RECT 328.465 0 331.275 385.37 ; + END + PORT + LAYER Metal4 ; + RECT 313.015 0 315.825 385.37 ; + END + PORT + LAYER Metal4 ; + RECT 302.715 0 305.525 385.37 ; + END + PORT + LAYER Metal4 ; + RECT 280.185 0 284.605 385.37 ; + END + PORT + LAYER Metal4 ; + RECT 262.505 0 266.925 385.37 ; + END + PORT + LAYER Metal4 ; + RECT 244.825 0 249.245 385.37 ; + END + PORT + LAYER Metal4 ; + RECT 227.145 0 231.565 385.37 ; + END + PORT + LAYER Metal4 ; + RECT 209.465 0 213.885 385.37 ; + END + PORT + LAYER Metal4 ; + RECT 191.785 0 196.205 385.37 ; + END + PORT + LAYER Metal4 ; + RECT 174.105 0 178.525 385.37 ; + END + PORT + LAYER Metal4 ; + RECT 156.425 0 160.845 385.37 ; + END + PORT + LAYER Metal4 ; + RECT 138.745 0 143.165 385.37 ; + END + PORT + LAYER Metal4 ; + RECT 121.065 0 125.485 385.37 ; + END + PORT + LAYER Metal4 ; + RECT 103.385 0 107.805 385.37 ; + END + PORT + LAYER Metal4 ; + RECT 85.705 0 90.125 385.37 ; + END + PORT + LAYER Metal4 ; + RECT 68.025 0 72.445 385.37 ; + END + PORT + LAYER Metal4 ; + RECT 50.345 0 54.765 385.37 ; + END + PORT + LAYER Metal4 ; + RECT 32.665 0 37.085 385.37 ; + END + PORT + LAYER Metal4 ; + RECT 14.985 0 19.405 385.37 ; + END + END VSS! + PIN VDD! + DIRECTION INOUT ; + USE POWER ; + NETEXPR "vdd VDD!" ; + PORT + LAYER Metal4 ; + RECT 674.925 0 679.345 47.045 ; + END + PORT + LAYER Metal4 ; + RECT 657.245 0 661.665 47.045 ; + END + PORT + LAYER Metal4 ; + RECT 639.565 0 643.985 47.045 ; + END + PORT + LAYER Metal4 ; + RECT 621.885 0 626.305 47.045 ; + END + PORT + LAYER Metal4 ; + RECT 604.205 0 608.625 47.045 ; + END + PORT + LAYER Metal4 ; + RECT 586.525 0 590.945 47.045 ; + END + PORT + LAYER Metal4 ; + RECT 568.845 0 573.265 47.045 ; + END + PORT + LAYER Metal4 ; + RECT 551.165 0 555.585 47.045 ; + END + PORT + LAYER Metal4 ; + RECT 533.485 0 537.905 47.045 ; + END + PORT + LAYER Metal4 ; + RECT 515.805 0 520.225 47.045 ; + END + PORT + LAYER Metal4 ; + RECT 498.125 0 502.545 47.045 ; + END + PORT + LAYER Metal4 ; + RECT 480.445 0 484.865 47.045 ; + END + PORT + LAYER Metal4 ; + RECT 462.765 0 467.185 47.045 ; + END + PORT + LAYER Metal4 ; + RECT 445.085 0 449.505 47.045 ; + END + PORT + LAYER Metal4 ; + RECT 427.405 0 431.825 47.045 ; + END + PORT + LAYER Metal4 ; + RECT 409.725 0 414.145 47.045 ; + END + PORT + LAYER Metal4 ; + RECT 374.815 0 377.625 385.37 ; + END + PORT + LAYER Metal4 ; + RECT 364.515 0 367.325 385.37 ; + END + PORT + LAYER Metal4 ; + RECT 359.365 0 362.175 385.37 ; + END + PORT + LAYER Metal4 ; + RECT 349.065 0 351.875 385.37 ; + END + PORT + LAYER Metal4 ; + RECT 333.615 0 336.425 385.37 ; + END + PORT + LAYER Metal4 ; + RECT 323.315 0 326.125 385.37 ; + END + PORT + LAYER Metal4 ; + RECT 318.165 0 320.975 385.37 ; + END + PORT + LAYER Metal4 ; + RECT 307.865 0 310.675 385.37 ; + END + PORT + LAYER Metal4 ; + RECT 271.345 0 275.765 47.045 ; + END + PORT + LAYER Metal4 ; + RECT 253.665 0 258.085 47.045 ; + END + PORT + LAYER Metal4 ; + RECT 235.985 0 240.405 47.045 ; + END + PORT + LAYER Metal4 ; + RECT 218.305 0 222.725 47.045 ; + END + PORT + LAYER Metal4 ; + RECT 200.625 0 205.045 47.045 ; + END + PORT + LAYER Metal4 ; + RECT 182.945 0 187.365 47.045 ; + END + PORT + LAYER Metal4 ; + RECT 165.265 0 169.685 47.045 ; + END + PORT + LAYER Metal4 ; + RECT 147.585 0 152.005 47.045 ; + END + PORT + LAYER Metal4 ; + RECT 129.905 0 134.325 47.045 ; + END + PORT + LAYER Metal4 ; + RECT 112.225 0 116.645 47.045 ; + END + PORT + LAYER Metal4 ; + RECT 94.545 0 98.965 47.045 ; + END + PORT + LAYER Metal4 ; + RECT 76.865 0 81.285 47.045 ; + END + PORT + LAYER Metal4 ; + RECT 59.185 0 63.605 47.045 ; + END + PORT + LAYER Metal4 ; + RECT 41.505 0 45.925 47.045 ; + END + PORT + LAYER Metal4 ; + RECT 23.825 0 28.245 47.045 ; + END + PORT + LAYER Metal4 ; + RECT 6.145 0 10.565 47.045 ; + END + END VDD! + PIN VDDARRAY! + DIRECTION INOUT ; + USE POWER ; + NETEXPR "vddarray VDDARRAY!" ; + PORT + LAYER Metal4 ; + RECT 674.925 53.41 679.345 385.37 ; + END + PORT + LAYER Metal4 ; + RECT 657.245 53.41 661.665 385.37 ; + END + PORT + LAYER Metal4 ; + RECT 639.565 53.41 643.985 385.37 ; + END + PORT + LAYER Metal4 ; + RECT 621.885 53.41 626.305 385.37 ; + END + PORT + LAYER Metal4 ; + RECT 604.205 53.41 608.625 385.37 ; + END + PORT + LAYER Metal4 ; + RECT 586.525 53.41 590.945 385.37 ; + END + PORT + LAYER Metal4 ; + RECT 568.845 53.41 573.265 385.37 ; + END + PORT + LAYER Metal4 ; + RECT 551.165 53.41 555.585 385.37 ; + END + PORT + LAYER Metal4 ; + RECT 533.485 53.41 537.905 385.37 ; + END + PORT + LAYER Metal4 ; + RECT 515.805 53.41 520.225 385.37 ; + END + PORT + LAYER Metal4 ; + RECT 498.125 53.41 502.545 385.37 ; + END + PORT + LAYER Metal4 ; + RECT 480.445 53.41 484.865 385.37 ; + END + PORT + LAYER Metal4 ; + RECT 462.765 53.41 467.185 385.37 ; + END + PORT + LAYER Metal4 ; + RECT 445.085 53.41 449.505 385.37 ; + END + PORT + LAYER Metal4 ; + RECT 427.405 53.41 431.825 385.37 ; + END + PORT + LAYER Metal4 ; + RECT 409.725 53.41 414.145 385.37 ; + END + PORT + LAYER Metal4 ; + RECT 271.345 53.41 275.765 385.37 ; + END + PORT + LAYER Metal4 ; + RECT 253.665 53.41 258.085 385.37 ; + END + PORT + LAYER Metal4 ; + RECT 235.985 53.41 240.405 385.37 ; + END + PORT + LAYER Metal4 ; + RECT 218.305 53.41 222.725 385.37 ; + END + PORT + LAYER Metal4 ; + RECT 200.625 53.41 205.045 385.37 ; + END + PORT + LAYER Metal4 ; + RECT 182.945 53.41 187.365 385.37 ; + END + PORT + LAYER Metal4 ; + RECT 165.265 53.41 169.685 385.37 ; + END + PORT + LAYER Metal4 ; + RECT 147.585 53.41 152.005 385.37 ; + END + PORT + LAYER Metal4 ; + RECT 129.905 53.41 134.325 385.37 ; + END + PORT + LAYER Metal4 ; + RECT 112.225 53.41 116.645 385.37 ; + END + PORT + LAYER Metal4 ; + RECT 94.545 53.41 98.965 385.37 ; + END + PORT + LAYER Metal4 ; + RECT 76.865 53.41 81.285 385.37 ; + END + PORT + LAYER Metal4 ; + RECT 59.185 53.41 63.605 385.37 ; + END + PORT + LAYER Metal4 ; + RECT 41.505 53.41 45.925 385.37 ; + END + PORT + LAYER Metal4 ; + RECT 23.825 53.41 28.245 385.37 ; + END + PORT + LAYER Metal4 ; + RECT 6.145 53.41 10.565 385.37 ; + END + END VDDARRAY! + PIN A_DIN[17] + DIRECTION INPUT ; + USE SIGNAL ; + ANTENNAPARTIALMETALAREA 3.9091 LAYER Metal2 ; + ANTENNAMODEL OXIDE1 ; + ANTENNAGATEAREA 0.20085 LAYER Metal2 ; + ANTENNAMAXAREACAR 20.368932 LAYER Metal2 ; + PORT + LAYER Metal2 ; + RECT 425.83 0 426.09 0.26 ; + END + END A_DIN[17] + PIN A_DIN[14] + DIRECTION INPUT ; + USE SIGNAL ; + ANTENNAPARTIALMETALAREA 3.9091 LAYER Metal2 ; + ANTENNAMODEL OXIDE1 ; + ANTENNAGATEAREA 0.20085 LAYER Metal2 ; + ANTENNAMAXAREACAR 20.368932 LAYER Metal2 ; + PORT + LAYER Metal2 ; + RECT 259.4 0 259.66 0.26 ; + END + END A_DIN[14] + PIN A_BIST_DIN[17] + DIRECTION INPUT ; + USE SIGNAL ; + ANTENNAPARTIALMETALAREA 4.136375 LAYER Metal2 ; + ANTENNAMODEL OXIDE1 ; + ANTENNAGATEAREA 0.20085 LAYER Metal2 ; + ANTENNAMAXAREACAR 21.874907 LAYER Metal2 ; + PORT + LAYER Metal2 ; + RECT 426.34 0 426.6 0.26 ; + END + END A_BIST_DIN[17] + PIN A_BIST_DIN[14] + DIRECTION INPUT ; + USE SIGNAL ; + ANTENNAPARTIALMETALAREA 4.136375 LAYER Metal2 ; + ANTENNAMODEL OXIDE1 ; + ANTENNAGATEAREA 0.20085 LAYER Metal2 ; + ANTENNAMAXAREACAR 21.874907 LAYER Metal2 ; + PORT + LAYER Metal2 ; + RECT 258.89 0 259.15 0.26 ; + END + END A_BIST_DIN[14] + PIN A_BM[17] + DIRECTION INPUT ; + USE SIGNAL ; + ANTENNAPARTIALMETALAREA 1.7264 LAYER Metal2 ; + ANTENNAMODEL OXIDE1 ; + ANTENNAGATEAREA 0.20085 LAYER Metal2 ; + ANTENNAMAXAREACAR 9.501618 LAYER Metal2 ; + PORT + LAYER Metal2 ; + RECT 434.5 0 434.76 0.26 ; + END + END A_BM[17] + PIN A_BM[14] + DIRECTION INPUT ; + USE SIGNAL ; + ANTENNAPARTIALMETALAREA 1.7264 LAYER Metal2 ; + ANTENNAMODEL OXIDE1 ; + ANTENNAGATEAREA 0.20085 LAYER Metal2 ; + ANTENNAMAXAREACAR 9.501618 LAYER Metal2 ; + PORT + LAYER Metal2 ; + RECT 250.73 0 250.99 0.26 ; + END + END A_BM[14] + PIN A_BIST_BM[17] + DIRECTION INPUT ; + USE SIGNAL ; + ANTENNAPARTIALMETALAREA 1.7602 LAYER Metal2 ; + ANTENNAMODEL OXIDE1 ; + ANTENNAGATEAREA 0.20085 LAYER Metal2 ; + ANTENNAMAXAREACAR 9.678367 LAYER Metal2 ; + PORT + LAYER Metal2 ; + RECT 433.125 0 433.385 0.26 ; + END + END A_BIST_BM[17] + PIN A_BIST_BM[14] + DIRECTION INPUT ; + USE SIGNAL ; + ANTENNAPARTIALMETALAREA 1.7602 LAYER Metal2 ; + ANTENNAMODEL OXIDE1 ; + ANTENNAGATEAREA 0.20085 LAYER Metal2 ; + ANTENNAMAXAREACAR 9.678367 LAYER Metal2 ; + PORT + LAYER Metal2 ; + RECT 252.105 0 252.365 0.26 ; + END + END A_BIST_BM[14] + PIN A_DOUT[17] + DIRECTION OUTPUT ; + USE SIGNAL ; + ANTENNAPARTIALMETALAREA 4.8256 LAYER Metal2 ; + ANTENNADIFFAREA 0.988 LAYER Metal2 ; + PORT + LAYER Metal2 ; + RECT 418.69 0 418.95 0.26 ; + END + END A_DOUT[17] + PIN A_DOUT[14] + DIRECTION OUTPUT ; + USE SIGNAL ; + ANTENNAPARTIALMETALAREA 4.8256 LAYER Metal2 ; + ANTENNADIFFAREA 0.988 LAYER Metal2 ; + PORT + LAYER Metal2 ; + RECT 266.54 0 266.8 0.26 ; + END + END A_DOUT[14] + PIN B_DIN[17] + DIRECTION INPUT ; + USE SIGNAL ; + ANTENNAPARTIALMETALAREA 2.925 LAYER Metal2 ; + ANTENNAMODEL OXIDE1 ; + ANTENNAGATEAREA 0.20085 LAYER Metal2 ; + ANTENNAMAXAREACAR 15.469256 LAYER Metal2 ; + PORT + LAYER Metal2 ; + RECT 428.38 0 428.64 0.26 ; + END + END B_DIN[17] + PIN B_DIN[14] + DIRECTION INPUT ; + USE SIGNAL ; + ANTENNAPARTIALMETALAREA 2.925 LAYER Metal2 ; + ANTENNAMODEL OXIDE1 ; + ANTENNAGATEAREA 0.20085 LAYER Metal2 ; + ANTENNAMAXAREACAR 15.469256 LAYER Metal2 ; + PORT + LAYER Metal2 ; + RECT 256.85 0 257.11 0.26 ; + END + END B_DIN[14] + PIN B_BIST_DIN[17] + DIRECTION INPUT ; + USE SIGNAL ; + ANTENNAPARTIALMETALAREA 2.9445 LAYER Metal2 ; + ANTENNAMODEL OXIDE1 ; + ANTENNAGATEAREA 0.20085 LAYER Metal2 ; + ANTENNAMAXAREACAR 15.929052 LAYER Metal2 ; + PORT + LAYER Metal2 ; + RECT 426.85 0 427.11 0.26 ; + END + END B_BIST_DIN[17] + PIN B_BIST_DIN[14] + DIRECTION INPUT ; + USE SIGNAL ; + ANTENNAPARTIALMETALAREA 2.9445 LAYER Metal2 ; + ANTENNAMODEL OXIDE1 ; + ANTENNAGATEAREA 0.20085 LAYER Metal2 ; + ANTENNAMAXAREACAR 15.929052 LAYER Metal2 ; + PORT + LAYER Metal2 ; + RECT 258.38 0 258.64 0.26 ; + END + END B_BIST_DIN[14] + PIN B_BM[17] + DIRECTION INPUT ; + USE SIGNAL ; + ANTENNAPARTIALMETALAREA 0.7007 LAYER Metal2 ; + ANTENNAMODEL OXIDE1 ; + ANTENNAGATEAREA 0.20085 LAYER Metal2 ; + ANTENNAMAXAREACAR 4.394822 LAYER Metal2 ; + PORT + LAYER Metal2 ; + RECT 419.865 0 420.125 0.26 ; + END + END B_BM[17] + PIN B_BM[14] + DIRECTION INPUT ; + USE SIGNAL ; + ANTENNAPARTIALMETALAREA 0.7007 LAYER Metal2 ; + ANTENNAMODEL OXIDE1 ; + ANTENNAGATEAREA 0.20085 LAYER Metal2 ; + ANTENNAMAXAREACAR 4.394822 LAYER Metal2 ; + PORT + LAYER Metal2 ; + RECT 265.365 0 265.625 0.26 ; + END + END B_BM[14] + PIN B_BIST_BM[17] + DIRECTION INPUT ; + USE SIGNAL ; + ANTENNAPARTIALMETALAREA 0.7007 LAYER Metal2 ; + ANTENNAMODEL OXIDE1 ; + ANTENNAGATEAREA 0.20085 LAYER Metal2 ; + ANTENNAMAXAREACAR 4.394822 LAYER Metal2 ; + PORT + LAYER Metal2 ; + RECT 421.395 0 421.655 0.26 ; + END + END B_BIST_BM[17] + PIN B_BIST_BM[14] + DIRECTION INPUT ; + USE SIGNAL ; + ANTENNAPARTIALMETALAREA 0.7007 LAYER Metal2 ; + ANTENNAMODEL OXIDE1 ; + ANTENNAGATEAREA 0.20085 LAYER Metal2 ; + ANTENNAMAXAREACAR 4.394822 LAYER Metal2 ; + PORT + LAYER Metal2 ; + RECT 263.835 0 264.095 0.26 ; + END + END B_BIST_BM[14] + PIN B_DOUT[17] + DIRECTION OUTPUT ; + USE SIGNAL ; + ANTENNAPARTIALMETALAREA 4.836 LAYER Metal2 ; + ANTENNADIFFAREA 0.988 LAYER Metal2 ; + PORT + LAYER Metal2 ; + RECT 435.52 0 435.78 0.26 ; + END + END B_DOUT[17] + PIN B_DOUT[14] + DIRECTION OUTPUT ; + USE SIGNAL ; + ANTENNAPARTIALMETALAREA 4.836 LAYER Metal2 ; + ANTENNADIFFAREA 0.988 LAYER Metal2 ; + PORT + LAYER Metal2 ; + RECT 249.71 0 249.97 0.26 ; + END + END B_DOUT[14] + PIN A_DIN[18] + DIRECTION INPUT ; + USE SIGNAL ; + ANTENNAPARTIALMETALAREA 3.9091 LAYER Metal2 ; + ANTENNAMODEL OXIDE1 ; + ANTENNAGATEAREA 0.20085 LAYER Metal2 ; + ANTENNAMAXAREACAR 20.368932 LAYER Metal2 ; + PORT + LAYER Metal2 ; + RECT 443.51 0 443.77 0.26 ; + END + END A_DIN[18] + PIN A_DIN[13] + DIRECTION INPUT ; + USE SIGNAL ; + ANTENNAPARTIALMETALAREA 3.9091 LAYER Metal2 ; + ANTENNAMODEL OXIDE1 ; + ANTENNAGATEAREA 0.20085 LAYER Metal2 ; + ANTENNAMAXAREACAR 20.368932 LAYER Metal2 ; + PORT + LAYER Metal2 ; + RECT 241.72 0 241.98 0.26 ; + END + END A_DIN[13] + PIN A_BIST_DIN[18] + DIRECTION INPUT ; + USE SIGNAL ; + ANTENNAPARTIALMETALAREA 4.136375 LAYER Metal2 ; + ANTENNAMODEL OXIDE1 ; + ANTENNAGATEAREA 0.20085 LAYER Metal2 ; + ANTENNAMAXAREACAR 21.874907 LAYER Metal2 ; + PORT + LAYER Metal2 ; + RECT 444.02 0 444.28 0.26 ; + END + END A_BIST_DIN[18] + PIN A_BIST_DIN[13] + DIRECTION INPUT ; + USE SIGNAL ; + ANTENNAPARTIALMETALAREA 4.136375 LAYER Metal2 ; + ANTENNAMODEL OXIDE1 ; + ANTENNAGATEAREA 0.20085 LAYER Metal2 ; + ANTENNAMAXAREACAR 21.874907 LAYER Metal2 ; + PORT + LAYER Metal2 ; + RECT 241.21 0 241.47 0.26 ; + END + END A_BIST_DIN[13] + PIN A_BM[18] + DIRECTION INPUT ; + USE SIGNAL ; + ANTENNAPARTIALMETALAREA 1.7264 LAYER Metal2 ; + ANTENNAMODEL OXIDE1 ; + ANTENNAGATEAREA 0.20085 LAYER Metal2 ; + ANTENNAMAXAREACAR 9.501618 LAYER Metal2 ; + PORT + LAYER Metal2 ; + RECT 452.18 0 452.44 0.26 ; + END + END A_BM[18] + PIN A_BM[13] + DIRECTION INPUT ; + USE SIGNAL ; + ANTENNAPARTIALMETALAREA 1.7264 LAYER Metal2 ; + ANTENNAMODEL OXIDE1 ; + ANTENNAGATEAREA 0.20085 LAYER Metal2 ; + ANTENNAMAXAREACAR 9.501618 LAYER Metal2 ; + PORT + LAYER Metal2 ; + RECT 233.05 0 233.31 0.26 ; + END + END A_BM[13] + PIN A_BIST_BM[18] + DIRECTION INPUT ; + USE SIGNAL ; + ANTENNAPARTIALMETALAREA 1.7602 LAYER Metal2 ; + ANTENNAMODEL OXIDE1 ; + ANTENNAGATEAREA 0.20085 LAYER Metal2 ; + ANTENNAMAXAREACAR 9.678367 LAYER Metal2 ; + PORT + LAYER Metal2 ; + RECT 450.805 0 451.065 0.26 ; + END + END A_BIST_BM[18] + PIN A_BIST_BM[13] + DIRECTION INPUT ; + USE SIGNAL ; + ANTENNAPARTIALMETALAREA 1.7602 LAYER Metal2 ; + ANTENNAMODEL OXIDE1 ; + ANTENNAGATEAREA 0.20085 LAYER Metal2 ; + ANTENNAMAXAREACAR 9.678367 LAYER Metal2 ; + PORT + LAYER Metal2 ; + RECT 234.425 0 234.685 0.26 ; + END + END A_BIST_BM[13] + PIN A_DOUT[18] + DIRECTION OUTPUT ; + USE SIGNAL ; + ANTENNAPARTIALMETALAREA 4.8256 LAYER Metal2 ; + ANTENNADIFFAREA 0.988 LAYER Metal2 ; + PORT + LAYER Metal2 ; + RECT 436.37 0 436.63 0.26 ; + END + END A_DOUT[18] + PIN A_DOUT[13] + DIRECTION OUTPUT ; + USE SIGNAL ; + ANTENNAPARTIALMETALAREA 4.8256 LAYER Metal2 ; + ANTENNADIFFAREA 0.988 LAYER Metal2 ; + PORT + LAYER Metal2 ; + RECT 248.86 0 249.12 0.26 ; + END + END A_DOUT[13] + PIN B_DIN[18] + DIRECTION INPUT ; + USE SIGNAL ; + ANTENNAPARTIALMETALAREA 2.925 LAYER Metal2 ; + ANTENNAMODEL OXIDE1 ; + ANTENNAGATEAREA 0.20085 LAYER Metal2 ; + ANTENNAMAXAREACAR 15.469256 LAYER Metal2 ; + PORT + LAYER Metal2 ; + RECT 446.06 0 446.32 0.26 ; + END + END B_DIN[18] + PIN B_DIN[13] + DIRECTION INPUT ; + USE SIGNAL ; + ANTENNAPARTIALMETALAREA 2.925 LAYER Metal2 ; + ANTENNAMODEL OXIDE1 ; + ANTENNAGATEAREA 0.20085 LAYER Metal2 ; + ANTENNAMAXAREACAR 15.469256 LAYER Metal2 ; + PORT + LAYER Metal2 ; + RECT 239.17 0 239.43 0.26 ; + END + END B_DIN[13] + PIN B_BIST_DIN[18] + DIRECTION INPUT ; + USE SIGNAL ; + ANTENNAPARTIALMETALAREA 2.9445 LAYER Metal2 ; + ANTENNAMODEL OXIDE1 ; + ANTENNAGATEAREA 0.20085 LAYER Metal2 ; + ANTENNAMAXAREACAR 15.929052 LAYER Metal2 ; + PORT + LAYER Metal2 ; + RECT 444.53 0 444.79 0.26 ; + END + END B_BIST_DIN[18] + PIN B_BIST_DIN[13] + DIRECTION INPUT ; + USE SIGNAL ; + ANTENNAPARTIALMETALAREA 2.9445 LAYER Metal2 ; + ANTENNAMODEL OXIDE1 ; + ANTENNAGATEAREA 0.20085 LAYER Metal2 ; + ANTENNAMAXAREACAR 15.929052 LAYER Metal2 ; + PORT + LAYER Metal2 ; + RECT 240.7 0 240.96 0.26 ; + END + END B_BIST_DIN[13] + PIN B_BM[18] + DIRECTION INPUT ; + USE SIGNAL ; + ANTENNAPARTIALMETALAREA 0.7007 LAYER Metal2 ; + ANTENNAMODEL OXIDE1 ; + ANTENNAGATEAREA 0.20085 LAYER Metal2 ; + ANTENNAMAXAREACAR 4.394822 LAYER Metal2 ; + PORT + LAYER Metal2 ; + RECT 437.545 0 437.805 0.26 ; + END + END B_BM[18] + PIN B_BM[13] + DIRECTION INPUT ; + USE SIGNAL ; + ANTENNAPARTIALMETALAREA 0.7007 LAYER Metal2 ; + ANTENNAMODEL OXIDE1 ; + ANTENNAGATEAREA 0.20085 LAYER Metal2 ; + ANTENNAMAXAREACAR 4.394822 LAYER Metal2 ; + PORT + LAYER Metal2 ; + RECT 247.685 0 247.945 0.26 ; + END + END B_BM[13] + PIN B_BIST_BM[18] + DIRECTION INPUT ; + USE SIGNAL ; + ANTENNAPARTIALMETALAREA 0.7007 LAYER Metal2 ; + ANTENNAMODEL OXIDE1 ; + ANTENNAGATEAREA 0.20085 LAYER Metal2 ; + ANTENNAMAXAREACAR 4.394822 LAYER Metal2 ; + PORT + LAYER Metal2 ; + RECT 439.075 0 439.335 0.26 ; + END + END B_BIST_BM[18] + PIN B_BIST_BM[13] + DIRECTION INPUT ; + USE SIGNAL ; + ANTENNAPARTIALMETALAREA 0.7007 LAYER Metal2 ; + ANTENNAMODEL OXIDE1 ; + ANTENNAGATEAREA 0.20085 LAYER Metal2 ; + ANTENNAMAXAREACAR 4.394822 LAYER Metal2 ; + PORT + LAYER Metal2 ; + RECT 246.155 0 246.415 0.26 ; + END + END B_BIST_BM[13] + PIN B_DOUT[18] + DIRECTION OUTPUT ; + USE SIGNAL ; + ANTENNAPARTIALMETALAREA 4.836 LAYER Metal2 ; + ANTENNADIFFAREA 0.988 LAYER Metal2 ; + PORT + LAYER Metal2 ; + RECT 453.2 0 453.46 0.26 ; + END + END B_DOUT[18] + PIN B_DOUT[13] + DIRECTION OUTPUT ; + USE SIGNAL ; + ANTENNAPARTIALMETALAREA 4.836 LAYER Metal2 ; + ANTENNADIFFAREA 0.988 LAYER Metal2 ; + PORT + LAYER Metal2 ; + RECT 232.03 0 232.29 0.26 ; + END + END B_DOUT[13] + PIN A_DIN[19] + DIRECTION INPUT ; + USE SIGNAL ; + ANTENNAPARTIALMETALAREA 3.9091 LAYER Metal2 ; + ANTENNAMODEL OXIDE1 ; + ANTENNAGATEAREA 0.20085 LAYER Metal2 ; + ANTENNAMAXAREACAR 20.368932 LAYER Metal2 ; + PORT + LAYER Metal2 ; + RECT 461.19 0 461.45 0.26 ; + END + END A_DIN[19] + PIN A_DIN[12] + DIRECTION INPUT ; + USE SIGNAL ; + ANTENNAPARTIALMETALAREA 3.9091 LAYER Metal2 ; + ANTENNAMODEL OXIDE1 ; + ANTENNAGATEAREA 0.20085 LAYER Metal2 ; + ANTENNAMAXAREACAR 20.368932 LAYER Metal2 ; + PORT + LAYER Metal2 ; + RECT 224.04 0 224.3 0.26 ; + END + END A_DIN[12] + PIN A_BIST_DIN[19] + DIRECTION INPUT ; + USE SIGNAL ; + ANTENNAPARTIALMETALAREA 4.136375 LAYER Metal2 ; + ANTENNAMODEL OXIDE1 ; + ANTENNAGATEAREA 0.20085 LAYER Metal2 ; + ANTENNAMAXAREACAR 21.874907 LAYER Metal2 ; + PORT + LAYER Metal2 ; + RECT 461.7 0 461.96 0.26 ; + END + END A_BIST_DIN[19] + PIN A_BIST_DIN[12] + DIRECTION INPUT ; + USE SIGNAL ; + ANTENNAPARTIALMETALAREA 4.136375 LAYER Metal2 ; + ANTENNAMODEL OXIDE1 ; + ANTENNAGATEAREA 0.20085 LAYER Metal2 ; + ANTENNAMAXAREACAR 21.874907 LAYER Metal2 ; + PORT + LAYER Metal2 ; + RECT 223.53 0 223.79 0.26 ; + END + END A_BIST_DIN[12] + PIN A_BM[19] + DIRECTION INPUT ; + USE SIGNAL ; + ANTENNAPARTIALMETALAREA 1.7264 LAYER Metal2 ; + ANTENNAMODEL OXIDE1 ; + ANTENNAGATEAREA 0.20085 LAYER Metal2 ; + ANTENNAMAXAREACAR 9.501618 LAYER Metal2 ; + PORT + LAYER Metal2 ; + RECT 469.86 0 470.12 0.26 ; + END + END A_BM[19] + PIN A_BM[12] + DIRECTION INPUT ; + USE SIGNAL ; + ANTENNAPARTIALMETALAREA 1.7264 LAYER Metal2 ; + ANTENNAMODEL OXIDE1 ; + ANTENNAGATEAREA 0.20085 LAYER Metal2 ; + ANTENNAMAXAREACAR 9.501618 LAYER Metal2 ; + PORT + LAYER Metal2 ; + RECT 215.37 0 215.63 0.26 ; + END + END A_BM[12] + PIN A_BIST_BM[19] + DIRECTION INPUT ; + USE SIGNAL ; + ANTENNAPARTIALMETALAREA 1.7602 LAYER Metal2 ; + ANTENNAMODEL OXIDE1 ; + ANTENNAGATEAREA 0.20085 LAYER Metal2 ; + ANTENNAMAXAREACAR 9.678367 LAYER Metal2 ; + PORT + LAYER Metal2 ; + RECT 468.485 0 468.745 0.26 ; + END + END A_BIST_BM[19] + PIN A_BIST_BM[12] + DIRECTION INPUT ; + USE SIGNAL ; + ANTENNAPARTIALMETALAREA 1.7602 LAYER Metal2 ; + ANTENNAMODEL OXIDE1 ; + ANTENNAGATEAREA 0.20085 LAYER Metal2 ; + ANTENNAMAXAREACAR 9.678367 LAYER Metal2 ; + PORT + LAYER Metal2 ; + RECT 216.745 0 217.005 0.26 ; + END + END A_BIST_BM[12] + PIN A_DOUT[19] + DIRECTION OUTPUT ; + USE SIGNAL ; + ANTENNAPARTIALMETALAREA 4.8256 LAYER Metal2 ; + ANTENNADIFFAREA 0.988 LAYER Metal2 ; + PORT + LAYER Metal2 ; + RECT 454.05 0 454.31 0.26 ; + END + END A_DOUT[19] + PIN A_DOUT[12] + DIRECTION OUTPUT ; + USE SIGNAL ; + ANTENNAPARTIALMETALAREA 4.8256 LAYER Metal2 ; + ANTENNADIFFAREA 0.988 LAYER Metal2 ; + PORT + LAYER Metal2 ; + RECT 231.18 0 231.44 0.26 ; + END + END A_DOUT[12] + PIN B_DIN[19] + DIRECTION INPUT ; + USE SIGNAL ; + ANTENNAPARTIALMETALAREA 2.925 LAYER Metal2 ; + ANTENNAMODEL OXIDE1 ; + ANTENNAGATEAREA 0.20085 LAYER Metal2 ; + ANTENNAMAXAREACAR 15.469256 LAYER Metal2 ; + PORT + LAYER Metal2 ; + RECT 463.74 0 464 0.26 ; + END + END B_DIN[19] + PIN B_DIN[12] + DIRECTION INPUT ; + USE SIGNAL ; + ANTENNAPARTIALMETALAREA 2.925 LAYER Metal2 ; + ANTENNAMODEL OXIDE1 ; + ANTENNAGATEAREA 0.20085 LAYER Metal2 ; + ANTENNAMAXAREACAR 15.469256 LAYER Metal2 ; + PORT + LAYER Metal2 ; + RECT 221.49 0 221.75 0.26 ; + END + END B_DIN[12] + PIN B_BIST_DIN[19] + DIRECTION INPUT ; + USE SIGNAL ; + ANTENNAPARTIALMETALAREA 2.9445 LAYER Metal2 ; + ANTENNAMODEL OXIDE1 ; + ANTENNAGATEAREA 0.20085 LAYER Metal2 ; + ANTENNAMAXAREACAR 15.929052 LAYER Metal2 ; + PORT + LAYER Metal2 ; + RECT 462.21 0 462.47 0.26 ; + END + END B_BIST_DIN[19] + PIN B_BIST_DIN[12] + DIRECTION INPUT ; + USE SIGNAL ; + ANTENNAPARTIALMETALAREA 2.9445 LAYER Metal2 ; + ANTENNAMODEL OXIDE1 ; + ANTENNAGATEAREA 0.20085 LAYER Metal2 ; + ANTENNAMAXAREACAR 15.929052 LAYER Metal2 ; + PORT + LAYER Metal2 ; + RECT 223.02 0 223.28 0.26 ; + END + END B_BIST_DIN[12] + PIN B_BM[19] + DIRECTION INPUT ; + USE SIGNAL ; + ANTENNAPARTIALMETALAREA 0.7007 LAYER Metal2 ; + ANTENNAMODEL OXIDE1 ; + ANTENNAGATEAREA 0.20085 LAYER Metal2 ; + ANTENNAMAXAREACAR 4.394822 LAYER Metal2 ; + PORT + LAYER Metal2 ; + RECT 455.225 0 455.485 0.26 ; + END + END B_BM[19] + PIN B_BM[12] + DIRECTION INPUT ; + USE SIGNAL ; + ANTENNAPARTIALMETALAREA 0.7007 LAYER Metal2 ; + ANTENNAMODEL OXIDE1 ; + ANTENNAGATEAREA 0.20085 LAYER Metal2 ; + ANTENNAMAXAREACAR 4.394822 LAYER Metal2 ; + PORT + LAYER Metal2 ; + RECT 230.005 0 230.265 0.26 ; + END + END B_BM[12] + PIN B_BIST_BM[19] + DIRECTION INPUT ; + USE SIGNAL ; + ANTENNAPARTIALMETALAREA 0.7007 LAYER Metal2 ; + ANTENNAMODEL OXIDE1 ; + ANTENNAGATEAREA 0.20085 LAYER Metal2 ; + ANTENNAMAXAREACAR 4.394822 LAYER Metal2 ; + PORT + LAYER Metal2 ; + RECT 456.755 0 457.015 0.26 ; + END + END B_BIST_BM[19] + PIN B_BIST_BM[12] + DIRECTION INPUT ; + USE SIGNAL ; + ANTENNAPARTIALMETALAREA 0.7007 LAYER Metal2 ; + ANTENNAMODEL OXIDE1 ; + ANTENNAGATEAREA 0.20085 LAYER Metal2 ; + ANTENNAMAXAREACAR 4.394822 LAYER Metal2 ; + PORT + LAYER Metal2 ; + RECT 228.475 0 228.735 0.26 ; + END + END B_BIST_BM[12] + PIN B_DOUT[19] + DIRECTION OUTPUT ; + USE SIGNAL ; + ANTENNAPARTIALMETALAREA 4.836 LAYER Metal2 ; + ANTENNADIFFAREA 0.988 LAYER Metal2 ; + PORT + LAYER Metal2 ; + RECT 470.88 0 471.14 0.26 ; + END + END B_DOUT[19] + PIN B_DOUT[12] + DIRECTION OUTPUT ; + USE SIGNAL ; + ANTENNAPARTIALMETALAREA 4.836 LAYER Metal2 ; + ANTENNADIFFAREA 0.988 LAYER Metal2 ; + PORT + LAYER Metal2 ; + RECT 214.35 0 214.61 0.26 ; + END + END B_DOUT[12] + PIN A_DIN[20] + DIRECTION INPUT ; + USE SIGNAL ; + ANTENNAPARTIALMETALAREA 3.9091 LAYER Metal2 ; + ANTENNAMODEL OXIDE1 ; + ANTENNAGATEAREA 0.20085 LAYER Metal2 ; + ANTENNAMAXAREACAR 20.368932 LAYER Metal2 ; + PORT + LAYER Metal2 ; + RECT 478.87 0 479.13 0.26 ; + END + END A_DIN[20] + PIN A_DIN[11] + DIRECTION INPUT ; + USE SIGNAL ; + ANTENNAPARTIALMETALAREA 3.9091 LAYER Metal2 ; + ANTENNAMODEL OXIDE1 ; + ANTENNAGATEAREA 0.20085 LAYER Metal2 ; + ANTENNAMAXAREACAR 20.368932 LAYER Metal2 ; + PORT + LAYER Metal2 ; + RECT 206.36 0 206.62 0.26 ; + END + END A_DIN[11] + PIN A_BIST_DIN[20] + DIRECTION INPUT ; + USE SIGNAL ; + ANTENNAPARTIALMETALAREA 4.136375 LAYER Metal2 ; + ANTENNAMODEL OXIDE1 ; + ANTENNAGATEAREA 0.20085 LAYER Metal2 ; + ANTENNAMAXAREACAR 21.874907 LAYER Metal2 ; + PORT + LAYER Metal2 ; + RECT 479.38 0 479.64 0.26 ; + END + END A_BIST_DIN[20] + PIN A_BIST_DIN[11] + DIRECTION INPUT ; + USE SIGNAL ; + ANTENNAPARTIALMETALAREA 4.136375 LAYER Metal2 ; + ANTENNAMODEL OXIDE1 ; + ANTENNAGATEAREA 0.20085 LAYER Metal2 ; + ANTENNAMAXAREACAR 21.874907 LAYER Metal2 ; + PORT + LAYER Metal2 ; + RECT 205.85 0 206.11 0.26 ; + END + END A_BIST_DIN[11] + PIN A_BM[20] + DIRECTION INPUT ; + USE SIGNAL ; + ANTENNAPARTIALMETALAREA 1.7264 LAYER Metal2 ; + ANTENNAMODEL OXIDE1 ; + ANTENNAGATEAREA 0.20085 LAYER Metal2 ; + ANTENNAMAXAREACAR 9.501618 LAYER Metal2 ; + PORT + LAYER Metal2 ; + RECT 487.54 0 487.8 0.26 ; + END + END A_BM[20] + PIN A_BM[11] + DIRECTION INPUT ; + USE SIGNAL ; + ANTENNAPARTIALMETALAREA 1.7264 LAYER Metal2 ; + ANTENNAMODEL OXIDE1 ; + ANTENNAGATEAREA 0.20085 LAYER Metal2 ; + ANTENNAMAXAREACAR 9.501618 LAYER Metal2 ; + PORT + LAYER Metal2 ; + RECT 197.69 0 197.95 0.26 ; + END + END A_BM[11] + PIN A_BIST_BM[20] + DIRECTION INPUT ; + USE SIGNAL ; + ANTENNAPARTIALMETALAREA 1.7602 LAYER Metal2 ; + ANTENNAMODEL OXIDE1 ; + ANTENNAGATEAREA 0.20085 LAYER Metal2 ; + ANTENNAMAXAREACAR 9.678367 LAYER Metal2 ; + PORT + LAYER Metal2 ; + RECT 486.165 0 486.425 0.26 ; + END + END A_BIST_BM[20] + PIN A_BIST_BM[11] + DIRECTION INPUT ; + USE SIGNAL ; + ANTENNAPARTIALMETALAREA 1.7602 LAYER Metal2 ; + ANTENNAMODEL OXIDE1 ; + ANTENNAGATEAREA 0.20085 LAYER Metal2 ; + ANTENNAMAXAREACAR 9.678367 LAYER Metal2 ; + PORT + LAYER Metal2 ; + RECT 199.065 0 199.325 0.26 ; + END + END A_BIST_BM[11] + PIN A_DOUT[20] + DIRECTION OUTPUT ; + USE SIGNAL ; + ANTENNAPARTIALMETALAREA 4.8256 LAYER Metal2 ; + ANTENNADIFFAREA 0.988 LAYER Metal2 ; + PORT + LAYER Metal2 ; + RECT 471.73 0 471.99 0.26 ; + END + END A_DOUT[20] + PIN A_DOUT[11] + DIRECTION OUTPUT ; + USE SIGNAL ; + ANTENNAPARTIALMETALAREA 4.8256 LAYER Metal2 ; + ANTENNADIFFAREA 0.988 LAYER Metal2 ; + PORT + LAYER Metal2 ; + RECT 213.5 0 213.76 0.26 ; + END + END A_DOUT[11] + PIN B_DIN[20] + DIRECTION INPUT ; + USE SIGNAL ; + ANTENNAPARTIALMETALAREA 2.925 LAYER Metal2 ; + ANTENNAMODEL OXIDE1 ; + ANTENNAGATEAREA 0.20085 LAYER Metal2 ; + ANTENNAMAXAREACAR 15.469256 LAYER Metal2 ; + PORT + LAYER Metal2 ; + RECT 481.42 0 481.68 0.26 ; + END + END B_DIN[20] + PIN B_DIN[11] + DIRECTION INPUT ; + USE SIGNAL ; + ANTENNAPARTIALMETALAREA 2.925 LAYER Metal2 ; + ANTENNAMODEL OXIDE1 ; + ANTENNAGATEAREA 0.20085 LAYER Metal2 ; + ANTENNAMAXAREACAR 15.469256 LAYER Metal2 ; + PORT + LAYER Metal2 ; + RECT 203.81 0 204.07 0.26 ; + END + END B_DIN[11] + PIN B_BIST_DIN[20] + DIRECTION INPUT ; + USE SIGNAL ; + ANTENNAPARTIALMETALAREA 2.9445 LAYER Metal2 ; + ANTENNAMODEL OXIDE1 ; + ANTENNAGATEAREA 0.20085 LAYER Metal2 ; + ANTENNAMAXAREACAR 15.929052 LAYER Metal2 ; + PORT + LAYER Metal2 ; + RECT 479.89 0 480.15 0.26 ; + END + END B_BIST_DIN[20] + PIN B_BIST_DIN[11] + DIRECTION INPUT ; + USE SIGNAL ; + ANTENNAPARTIALMETALAREA 2.9445 LAYER Metal2 ; + ANTENNAMODEL OXIDE1 ; + ANTENNAGATEAREA 0.20085 LAYER Metal2 ; + ANTENNAMAXAREACAR 15.929052 LAYER Metal2 ; + PORT + LAYER Metal2 ; + RECT 205.34 0 205.6 0.26 ; + END + END B_BIST_DIN[11] + PIN B_BM[20] + DIRECTION INPUT ; + USE SIGNAL ; + ANTENNAPARTIALMETALAREA 0.7007 LAYER Metal2 ; + ANTENNAMODEL OXIDE1 ; + ANTENNAGATEAREA 0.20085 LAYER Metal2 ; + ANTENNAMAXAREACAR 4.394822 LAYER Metal2 ; + PORT + LAYER Metal2 ; + RECT 472.905 0 473.165 0.26 ; + END + END B_BM[20] + PIN B_BM[11] + DIRECTION INPUT ; + USE SIGNAL ; + ANTENNAPARTIALMETALAREA 0.7007 LAYER Metal2 ; + ANTENNAMODEL OXIDE1 ; + ANTENNAGATEAREA 0.20085 LAYER Metal2 ; + ANTENNAMAXAREACAR 4.394822 LAYER Metal2 ; + PORT + LAYER Metal2 ; + RECT 212.325 0 212.585 0.26 ; + END + END B_BM[11] + PIN B_BIST_BM[20] + DIRECTION INPUT ; + USE SIGNAL ; + ANTENNAPARTIALMETALAREA 0.7007 LAYER Metal2 ; + ANTENNAMODEL OXIDE1 ; + ANTENNAGATEAREA 0.20085 LAYER Metal2 ; + ANTENNAMAXAREACAR 4.394822 LAYER Metal2 ; + PORT + LAYER Metal2 ; + RECT 474.435 0 474.695 0.26 ; + END + END B_BIST_BM[20] + PIN B_BIST_BM[11] + DIRECTION INPUT ; + USE SIGNAL ; + ANTENNAPARTIALMETALAREA 0.7007 LAYER Metal2 ; + ANTENNAMODEL OXIDE1 ; + ANTENNAGATEAREA 0.20085 LAYER Metal2 ; + ANTENNAMAXAREACAR 4.394822 LAYER Metal2 ; + PORT + LAYER Metal2 ; + RECT 210.795 0 211.055 0.26 ; + END + END B_BIST_BM[11] + PIN B_DOUT[20] + DIRECTION OUTPUT ; + USE SIGNAL ; + ANTENNAPARTIALMETALAREA 4.836 LAYER Metal2 ; + ANTENNADIFFAREA 0.988 LAYER Metal2 ; + PORT + LAYER Metal2 ; + RECT 488.56 0 488.82 0.26 ; + END + END B_DOUT[20] + PIN B_DOUT[11] + DIRECTION OUTPUT ; + USE SIGNAL ; + ANTENNAPARTIALMETALAREA 4.836 LAYER Metal2 ; + ANTENNADIFFAREA 0.988 LAYER Metal2 ; + PORT + LAYER Metal2 ; + RECT 196.67 0 196.93 0.26 ; + END + END B_DOUT[11] + PIN A_DIN[21] + DIRECTION INPUT ; + USE SIGNAL ; + ANTENNAPARTIALMETALAREA 3.9091 LAYER Metal2 ; + ANTENNAMODEL OXIDE1 ; + ANTENNAGATEAREA 0.20085 LAYER Metal2 ; + ANTENNAMAXAREACAR 20.368932 LAYER Metal2 ; + PORT + LAYER Metal2 ; + RECT 496.55 0 496.81 0.26 ; + END + END A_DIN[21] + PIN A_DIN[10] + DIRECTION INPUT ; + USE SIGNAL ; + ANTENNAPARTIALMETALAREA 3.9091 LAYER Metal2 ; + ANTENNAMODEL OXIDE1 ; + ANTENNAGATEAREA 0.20085 LAYER Metal2 ; + ANTENNAMAXAREACAR 20.368932 LAYER Metal2 ; + PORT + LAYER Metal2 ; + RECT 188.68 0 188.94 0.26 ; + END + END A_DIN[10] + PIN A_BIST_DIN[21] + DIRECTION INPUT ; + USE SIGNAL ; + ANTENNAPARTIALMETALAREA 4.136375 LAYER Metal2 ; + ANTENNAMODEL OXIDE1 ; + ANTENNAGATEAREA 0.20085 LAYER Metal2 ; + ANTENNAMAXAREACAR 21.874907 LAYER Metal2 ; + PORT + LAYER Metal2 ; + RECT 497.06 0 497.32 0.26 ; + END + END A_BIST_DIN[21] + PIN A_BIST_DIN[10] + DIRECTION INPUT ; + USE SIGNAL ; + ANTENNAPARTIALMETALAREA 4.136375 LAYER Metal2 ; + ANTENNAMODEL OXIDE1 ; + ANTENNAGATEAREA 0.20085 LAYER Metal2 ; + ANTENNAMAXAREACAR 21.874907 LAYER Metal2 ; + PORT + LAYER Metal2 ; + RECT 188.17 0 188.43 0.26 ; + END + END A_BIST_DIN[10] + PIN A_BM[21] + DIRECTION INPUT ; + USE SIGNAL ; + ANTENNAPARTIALMETALAREA 1.7264 LAYER Metal2 ; + ANTENNAMODEL OXIDE1 ; + ANTENNAGATEAREA 0.20085 LAYER Metal2 ; + ANTENNAMAXAREACAR 9.501618 LAYER Metal2 ; + PORT + LAYER Metal2 ; + RECT 505.22 0 505.48 0.26 ; + END + END A_BM[21] + PIN A_BM[10] + DIRECTION INPUT ; + USE SIGNAL ; + ANTENNAPARTIALMETALAREA 1.7264 LAYER Metal2 ; + ANTENNAMODEL OXIDE1 ; + ANTENNAGATEAREA 0.20085 LAYER Metal2 ; + ANTENNAMAXAREACAR 9.501618 LAYER Metal2 ; + PORT + LAYER Metal2 ; + RECT 180.01 0 180.27 0.26 ; + END + END A_BM[10] + PIN A_BIST_BM[21] + DIRECTION INPUT ; + USE SIGNAL ; + ANTENNAPARTIALMETALAREA 1.7602 LAYER Metal2 ; + ANTENNAMODEL OXIDE1 ; + ANTENNAGATEAREA 0.20085 LAYER Metal2 ; + ANTENNAMAXAREACAR 9.678367 LAYER Metal2 ; + PORT + LAYER Metal2 ; + RECT 503.845 0 504.105 0.26 ; + END + END A_BIST_BM[21] + PIN A_BIST_BM[10] + DIRECTION INPUT ; + USE SIGNAL ; + ANTENNAPARTIALMETALAREA 1.7602 LAYER Metal2 ; + ANTENNAMODEL OXIDE1 ; + ANTENNAGATEAREA 0.20085 LAYER Metal2 ; + ANTENNAMAXAREACAR 9.678367 LAYER Metal2 ; + PORT + LAYER Metal2 ; + RECT 181.385 0 181.645 0.26 ; + END + END A_BIST_BM[10] + PIN A_DOUT[21] + DIRECTION OUTPUT ; + USE SIGNAL ; + ANTENNAPARTIALMETALAREA 4.8256 LAYER Metal2 ; + ANTENNADIFFAREA 0.988 LAYER Metal2 ; + PORT + LAYER Metal2 ; + RECT 489.41 0 489.67 0.26 ; + END + END A_DOUT[21] + PIN A_DOUT[10] + DIRECTION OUTPUT ; + USE SIGNAL ; + ANTENNAPARTIALMETALAREA 4.8256 LAYER Metal2 ; + ANTENNADIFFAREA 0.988 LAYER Metal2 ; + PORT + LAYER Metal2 ; + RECT 195.82 0 196.08 0.26 ; + END + END A_DOUT[10] + PIN B_DIN[21] + DIRECTION INPUT ; + USE SIGNAL ; + ANTENNAPARTIALMETALAREA 2.925 LAYER Metal2 ; + ANTENNAMODEL OXIDE1 ; + ANTENNAGATEAREA 0.20085 LAYER Metal2 ; + ANTENNAMAXAREACAR 15.469256 LAYER Metal2 ; + PORT + LAYER Metal2 ; + RECT 499.1 0 499.36 0.26 ; + END + END B_DIN[21] + PIN B_DIN[10] + DIRECTION INPUT ; + USE SIGNAL ; + ANTENNAPARTIALMETALAREA 2.925 LAYER Metal2 ; + ANTENNAMODEL OXIDE1 ; + ANTENNAGATEAREA 0.20085 LAYER Metal2 ; + ANTENNAMAXAREACAR 15.469256 LAYER Metal2 ; + PORT + LAYER Metal2 ; + RECT 186.13 0 186.39 0.26 ; + END + END B_DIN[10] + PIN B_BIST_DIN[21] + DIRECTION INPUT ; + USE SIGNAL ; + ANTENNAPARTIALMETALAREA 2.9445 LAYER Metal2 ; + ANTENNAMODEL OXIDE1 ; + ANTENNAGATEAREA 0.20085 LAYER Metal2 ; + ANTENNAMAXAREACAR 15.929052 LAYER Metal2 ; + PORT + LAYER Metal2 ; + RECT 497.57 0 497.83 0.26 ; + END + END B_BIST_DIN[21] + PIN B_BIST_DIN[10] + DIRECTION INPUT ; + USE SIGNAL ; + ANTENNAPARTIALMETALAREA 2.9445 LAYER Metal2 ; + ANTENNAMODEL OXIDE1 ; + ANTENNAGATEAREA 0.20085 LAYER Metal2 ; + ANTENNAMAXAREACAR 15.929052 LAYER Metal2 ; + PORT + LAYER Metal2 ; + RECT 187.66 0 187.92 0.26 ; + END + END B_BIST_DIN[10] + PIN B_BM[21] + DIRECTION INPUT ; + USE SIGNAL ; + ANTENNAPARTIALMETALAREA 0.7007 LAYER Metal2 ; + ANTENNAMODEL OXIDE1 ; + ANTENNAGATEAREA 0.20085 LAYER Metal2 ; + ANTENNAMAXAREACAR 4.394822 LAYER Metal2 ; + PORT + LAYER Metal2 ; + RECT 490.585 0 490.845 0.26 ; + END + END B_BM[21] + PIN B_BM[10] + DIRECTION INPUT ; + USE SIGNAL ; + ANTENNAPARTIALMETALAREA 0.7007 LAYER Metal2 ; + ANTENNAMODEL OXIDE1 ; + ANTENNAGATEAREA 0.20085 LAYER Metal2 ; + ANTENNAMAXAREACAR 4.394822 LAYER Metal2 ; + PORT + LAYER Metal2 ; + RECT 194.645 0 194.905 0.26 ; + END + END B_BM[10] + PIN B_BIST_BM[21] + DIRECTION INPUT ; + USE SIGNAL ; + ANTENNAPARTIALMETALAREA 0.7007 LAYER Metal2 ; + ANTENNAMODEL OXIDE1 ; + ANTENNAGATEAREA 0.20085 LAYER Metal2 ; + ANTENNAMAXAREACAR 4.394822 LAYER Metal2 ; + PORT + LAYER Metal2 ; + RECT 492.115 0 492.375 0.26 ; + END + END B_BIST_BM[21] + PIN B_BIST_BM[10] + DIRECTION INPUT ; + USE SIGNAL ; + ANTENNAPARTIALMETALAREA 0.7007 LAYER Metal2 ; + ANTENNAMODEL OXIDE1 ; + ANTENNAGATEAREA 0.20085 LAYER Metal2 ; + ANTENNAMAXAREACAR 4.394822 LAYER Metal2 ; + PORT + LAYER Metal2 ; + RECT 193.115 0 193.375 0.26 ; + END + END B_BIST_BM[10] + PIN B_DOUT[21] + DIRECTION OUTPUT ; + USE SIGNAL ; + ANTENNAPARTIALMETALAREA 4.836 LAYER Metal2 ; + ANTENNADIFFAREA 0.988 LAYER Metal2 ; + PORT + LAYER Metal2 ; + RECT 506.24 0 506.5 0.26 ; + END + END B_DOUT[21] + PIN B_DOUT[10] + DIRECTION OUTPUT ; + USE SIGNAL ; + ANTENNAPARTIALMETALAREA 4.836 LAYER Metal2 ; + ANTENNADIFFAREA 0.988 LAYER Metal2 ; + PORT + LAYER Metal2 ; + RECT 178.99 0 179.25 0.26 ; + END + END B_DOUT[10] + PIN A_DIN[22] + DIRECTION INPUT ; + USE SIGNAL ; + ANTENNAPARTIALMETALAREA 3.9091 LAYER Metal2 ; + ANTENNAMODEL OXIDE1 ; + ANTENNAGATEAREA 0.20085 LAYER Metal2 ; + ANTENNAMAXAREACAR 20.368932 LAYER Metal2 ; + PORT + LAYER Metal2 ; + RECT 514.23 0 514.49 0.26 ; + END + END A_DIN[22] + PIN A_DIN[9] + DIRECTION INPUT ; + USE SIGNAL ; + ANTENNAPARTIALMETALAREA 3.9091 LAYER Metal2 ; + ANTENNAMODEL OXIDE1 ; + ANTENNAGATEAREA 0.20085 LAYER Metal2 ; + ANTENNAMAXAREACAR 20.368932 LAYER Metal2 ; + PORT + LAYER Metal2 ; + RECT 171 0 171.26 0.26 ; + END + END A_DIN[9] + PIN A_BIST_DIN[22] + DIRECTION INPUT ; + USE SIGNAL ; + ANTENNAPARTIALMETALAREA 4.136375 LAYER Metal2 ; + ANTENNAMODEL OXIDE1 ; + ANTENNAGATEAREA 0.20085 LAYER Metal2 ; + ANTENNAMAXAREACAR 21.874907 LAYER Metal2 ; + PORT + LAYER Metal2 ; + RECT 514.74 0 515 0.26 ; + END + END A_BIST_DIN[22] + PIN A_BIST_DIN[9] + DIRECTION INPUT ; + USE SIGNAL ; + ANTENNAPARTIALMETALAREA 4.136375 LAYER Metal2 ; + ANTENNAMODEL OXIDE1 ; + ANTENNAGATEAREA 0.20085 LAYER Metal2 ; + ANTENNAMAXAREACAR 21.874907 LAYER Metal2 ; + PORT + LAYER Metal2 ; + RECT 170.49 0 170.75 0.26 ; + END + END A_BIST_DIN[9] + PIN A_BM[22] + DIRECTION INPUT ; + USE SIGNAL ; + ANTENNAPARTIALMETALAREA 1.7264 LAYER Metal2 ; + ANTENNAMODEL OXIDE1 ; + ANTENNAGATEAREA 0.20085 LAYER Metal2 ; + ANTENNAMAXAREACAR 9.501618 LAYER Metal2 ; + PORT + LAYER Metal2 ; + RECT 522.9 0 523.16 0.26 ; + END + END A_BM[22] + PIN A_BM[9] + DIRECTION INPUT ; + USE SIGNAL ; + ANTENNAPARTIALMETALAREA 1.7264 LAYER Metal2 ; + ANTENNAMODEL OXIDE1 ; + ANTENNAGATEAREA 0.20085 LAYER Metal2 ; + ANTENNAMAXAREACAR 9.501618 LAYER Metal2 ; + PORT + LAYER Metal2 ; + RECT 162.33 0 162.59 0.26 ; + END + END A_BM[9] + PIN A_BIST_BM[22] + DIRECTION INPUT ; + USE SIGNAL ; + ANTENNAPARTIALMETALAREA 1.7602 LAYER Metal2 ; + ANTENNAMODEL OXIDE1 ; + ANTENNAGATEAREA 0.20085 LAYER Metal2 ; + ANTENNAMAXAREACAR 9.678367 LAYER Metal2 ; + PORT + LAYER Metal2 ; + RECT 521.525 0 521.785 0.26 ; + END + END A_BIST_BM[22] + PIN A_BIST_BM[9] + DIRECTION INPUT ; + USE SIGNAL ; + ANTENNAPARTIALMETALAREA 1.7602 LAYER Metal2 ; + ANTENNAMODEL OXIDE1 ; + ANTENNAGATEAREA 0.20085 LAYER Metal2 ; + ANTENNAMAXAREACAR 9.678367 LAYER Metal2 ; + PORT + LAYER Metal2 ; + RECT 163.705 0 163.965 0.26 ; + END + END A_BIST_BM[9] + PIN A_DOUT[22] + DIRECTION OUTPUT ; + USE SIGNAL ; + ANTENNAPARTIALMETALAREA 4.8256 LAYER Metal2 ; + ANTENNADIFFAREA 0.988 LAYER Metal2 ; + PORT + LAYER Metal2 ; + RECT 507.09 0 507.35 0.26 ; + END + END A_DOUT[22] + PIN A_DOUT[9] + DIRECTION OUTPUT ; + USE SIGNAL ; + ANTENNAPARTIALMETALAREA 4.8256 LAYER Metal2 ; + ANTENNADIFFAREA 0.988 LAYER Metal2 ; + PORT + LAYER Metal2 ; + RECT 178.14 0 178.4 0.26 ; + END + END A_DOUT[9] + PIN B_DIN[22] + DIRECTION INPUT ; + USE SIGNAL ; + ANTENNAPARTIALMETALAREA 2.925 LAYER Metal2 ; + ANTENNAMODEL OXIDE1 ; + ANTENNAGATEAREA 0.20085 LAYER Metal2 ; + ANTENNAMAXAREACAR 15.469256 LAYER Metal2 ; + PORT + LAYER Metal2 ; + RECT 516.78 0 517.04 0.26 ; + END + END B_DIN[22] + PIN B_DIN[9] + DIRECTION INPUT ; + USE SIGNAL ; + ANTENNAPARTIALMETALAREA 2.925 LAYER Metal2 ; + ANTENNAMODEL OXIDE1 ; + ANTENNAGATEAREA 0.20085 LAYER Metal2 ; + ANTENNAMAXAREACAR 15.469256 LAYER Metal2 ; + PORT + LAYER Metal2 ; + RECT 168.45 0 168.71 0.26 ; + END + END B_DIN[9] + PIN B_BIST_DIN[22] + DIRECTION INPUT ; + USE SIGNAL ; + ANTENNAPARTIALMETALAREA 2.9445 LAYER Metal2 ; + ANTENNAMODEL OXIDE1 ; + ANTENNAGATEAREA 0.20085 LAYER Metal2 ; + ANTENNAMAXAREACAR 15.929052 LAYER Metal2 ; + PORT + LAYER Metal2 ; + RECT 515.25 0 515.51 0.26 ; + END + END B_BIST_DIN[22] + PIN B_BIST_DIN[9] + DIRECTION INPUT ; + USE SIGNAL ; + ANTENNAPARTIALMETALAREA 2.9445 LAYER Metal2 ; + ANTENNAMODEL OXIDE1 ; + ANTENNAGATEAREA 0.20085 LAYER Metal2 ; + ANTENNAMAXAREACAR 15.929052 LAYER Metal2 ; + PORT + LAYER Metal2 ; + RECT 169.98 0 170.24 0.26 ; + END + END B_BIST_DIN[9] + PIN B_BM[22] + DIRECTION INPUT ; + USE SIGNAL ; + ANTENNAPARTIALMETALAREA 0.7007 LAYER Metal2 ; + ANTENNAMODEL OXIDE1 ; + ANTENNAGATEAREA 0.20085 LAYER Metal2 ; + ANTENNAMAXAREACAR 4.394822 LAYER Metal2 ; + PORT + LAYER Metal2 ; + RECT 508.265 0 508.525 0.26 ; + END + END B_BM[22] + PIN B_BM[9] + DIRECTION INPUT ; + USE SIGNAL ; + ANTENNAPARTIALMETALAREA 0.7007 LAYER Metal2 ; + ANTENNAMODEL OXIDE1 ; + ANTENNAGATEAREA 0.20085 LAYER Metal2 ; + ANTENNAMAXAREACAR 4.394822 LAYER Metal2 ; + PORT + LAYER Metal2 ; + RECT 176.965 0 177.225 0.26 ; + END + END B_BM[9] + PIN B_BIST_BM[22] + DIRECTION INPUT ; + USE SIGNAL ; + ANTENNAPARTIALMETALAREA 0.7007 LAYER Metal2 ; + ANTENNAMODEL OXIDE1 ; + ANTENNAGATEAREA 0.20085 LAYER Metal2 ; + ANTENNAMAXAREACAR 4.394822 LAYER Metal2 ; + PORT + LAYER Metal2 ; + RECT 509.795 0 510.055 0.26 ; + END + END B_BIST_BM[22] + PIN B_BIST_BM[9] + DIRECTION INPUT ; + USE SIGNAL ; + ANTENNAPARTIALMETALAREA 0.7007 LAYER Metal2 ; + ANTENNAMODEL OXIDE1 ; + ANTENNAGATEAREA 0.20085 LAYER Metal2 ; + ANTENNAMAXAREACAR 4.394822 LAYER Metal2 ; + PORT + LAYER Metal2 ; + RECT 175.435 0 175.695 0.26 ; + END + END B_BIST_BM[9] + PIN B_DOUT[22] + DIRECTION OUTPUT ; + USE SIGNAL ; + ANTENNAPARTIALMETALAREA 4.836 LAYER Metal2 ; + ANTENNADIFFAREA 0.988 LAYER Metal2 ; + PORT + LAYER Metal2 ; + RECT 523.92 0 524.18 0.26 ; + END + END B_DOUT[22] + PIN B_DOUT[9] + DIRECTION OUTPUT ; + USE SIGNAL ; + ANTENNAPARTIALMETALAREA 4.836 LAYER Metal2 ; + ANTENNADIFFAREA 0.988 LAYER Metal2 ; + PORT + LAYER Metal2 ; + RECT 161.31 0 161.57 0.26 ; + END + END B_DOUT[9] + PIN A_DIN[23] + DIRECTION INPUT ; + USE SIGNAL ; + ANTENNAPARTIALMETALAREA 3.9091 LAYER Metal2 ; + ANTENNAMODEL OXIDE1 ; + ANTENNAGATEAREA 0.20085 LAYER Metal2 ; + ANTENNAMAXAREACAR 20.368932 LAYER Metal2 ; + PORT + LAYER Metal2 ; + RECT 531.91 0 532.17 0.26 ; + END + END A_DIN[23] + PIN A_DIN[8] + DIRECTION INPUT ; + USE SIGNAL ; + ANTENNAPARTIALMETALAREA 3.9091 LAYER Metal2 ; + ANTENNAMODEL OXIDE1 ; + ANTENNAGATEAREA 0.20085 LAYER Metal2 ; + ANTENNAMAXAREACAR 20.368932 LAYER Metal2 ; + PORT + LAYER Metal2 ; + RECT 153.32 0 153.58 0.26 ; + END + END A_DIN[8] + PIN A_BIST_DIN[23] + DIRECTION INPUT ; + USE SIGNAL ; + ANTENNAPARTIALMETALAREA 4.136375 LAYER Metal2 ; + ANTENNAMODEL OXIDE1 ; + ANTENNAGATEAREA 0.20085 LAYER Metal2 ; + ANTENNAMAXAREACAR 21.874907 LAYER Metal2 ; + PORT + LAYER Metal2 ; + RECT 532.42 0 532.68 0.26 ; + END + END A_BIST_DIN[23] + PIN A_BIST_DIN[8] + DIRECTION INPUT ; + USE SIGNAL ; + ANTENNAPARTIALMETALAREA 4.136375 LAYER Metal2 ; + ANTENNAMODEL OXIDE1 ; + ANTENNAGATEAREA 0.20085 LAYER Metal2 ; + ANTENNAMAXAREACAR 21.874907 LAYER Metal2 ; + PORT + LAYER Metal2 ; + RECT 152.81 0 153.07 0.26 ; + END + END A_BIST_DIN[8] + PIN A_BM[23] + DIRECTION INPUT ; + USE SIGNAL ; + ANTENNAPARTIALMETALAREA 1.7264 LAYER Metal2 ; + ANTENNAMODEL OXIDE1 ; + ANTENNAGATEAREA 0.20085 LAYER Metal2 ; + ANTENNAMAXAREACAR 9.501618 LAYER Metal2 ; + PORT + LAYER Metal2 ; + RECT 540.58 0 540.84 0.26 ; + END + END A_BM[23] + PIN A_BM[8] + DIRECTION INPUT ; + USE SIGNAL ; + ANTENNAPARTIALMETALAREA 1.7264 LAYER Metal2 ; + ANTENNAMODEL OXIDE1 ; + ANTENNAGATEAREA 0.20085 LAYER Metal2 ; + ANTENNAMAXAREACAR 9.501618 LAYER Metal2 ; + PORT + LAYER Metal2 ; + RECT 144.65 0 144.91 0.26 ; + END + END A_BM[8] + PIN A_BIST_BM[23] + DIRECTION INPUT ; + USE SIGNAL ; + ANTENNAPARTIALMETALAREA 1.7602 LAYER Metal2 ; + ANTENNAMODEL OXIDE1 ; + ANTENNAGATEAREA 0.20085 LAYER Metal2 ; + ANTENNAMAXAREACAR 9.678367 LAYER Metal2 ; + PORT + LAYER Metal2 ; + RECT 539.205 0 539.465 0.26 ; + END + END A_BIST_BM[23] + PIN A_BIST_BM[8] + DIRECTION INPUT ; + USE SIGNAL ; + ANTENNAPARTIALMETALAREA 1.7602 LAYER Metal2 ; + ANTENNAMODEL OXIDE1 ; + ANTENNAGATEAREA 0.20085 LAYER Metal2 ; + ANTENNAMAXAREACAR 9.678367 LAYER Metal2 ; + PORT + LAYER Metal2 ; + RECT 146.025 0 146.285 0.26 ; + END + END A_BIST_BM[8] + PIN A_DOUT[23] + DIRECTION OUTPUT ; + USE SIGNAL ; + ANTENNAPARTIALMETALAREA 4.8256 LAYER Metal2 ; + ANTENNADIFFAREA 0.988 LAYER Metal2 ; + PORT + LAYER Metal2 ; + RECT 524.77 0 525.03 0.26 ; + END + END A_DOUT[23] + PIN A_DOUT[8] + DIRECTION OUTPUT ; + USE SIGNAL ; + ANTENNAPARTIALMETALAREA 4.8256 LAYER Metal2 ; + ANTENNADIFFAREA 0.988 LAYER Metal2 ; + PORT + LAYER Metal2 ; + RECT 160.46 0 160.72 0.26 ; + END + END A_DOUT[8] + PIN B_DIN[23] + DIRECTION INPUT ; + USE SIGNAL ; + ANTENNAPARTIALMETALAREA 2.925 LAYER Metal2 ; + ANTENNAMODEL OXIDE1 ; + ANTENNAGATEAREA 0.20085 LAYER Metal2 ; + ANTENNAMAXAREACAR 15.469256 LAYER Metal2 ; + PORT + LAYER Metal2 ; + RECT 534.46 0 534.72 0.26 ; + END + END B_DIN[23] + PIN B_DIN[8] + DIRECTION INPUT ; + USE SIGNAL ; + ANTENNAPARTIALMETALAREA 2.925 LAYER Metal2 ; + ANTENNAMODEL OXIDE1 ; + ANTENNAGATEAREA 0.20085 LAYER Metal2 ; + ANTENNAMAXAREACAR 15.469256 LAYER Metal2 ; + PORT + LAYER Metal2 ; + RECT 150.77 0 151.03 0.26 ; + END + END B_DIN[8] + PIN B_BIST_DIN[23] + DIRECTION INPUT ; + USE SIGNAL ; + ANTENNAPARTIALMETALAREA 2.9445 LAYER Metal2 ; + ANTENNAMODEL OXIDE1 ; + ANTENNAGATEAREA 0.20085 LAYER Metal2 ; + ANTENNAMAXAREACAR 15.929052 LAYER Metal2 ; + PORT + LAYER Metal2 ; + RECT 532.93 0 533.19 0.26 ; + END + END B_BIST_DIN[23] + PIN B_BIST_DIN[8] + DIRECTION INPUT ; + USE SIGNAL ; + ANTENNAPARTIALMETALAREA 2.9445 LAYER Metal2 ; + ANTENNAMODEL OXIDE1 ; + ANTENNAGATEAREA 0.20085 LAYER Metal2 ; + ANTENNAMAXAREACAR 15.929052 LAYER Metal2 ; + PORT + LAYER Metal2 ; + RECT 152.3 0 152.56 0.26 ; + END + END B_BIST_DIN[8] + PIN B_BM[23] + DIRECTION INPUT ; + USE SIGNAL ; + ANTENNAPARTIALMETALAREA 0.7007 LAYER Metal2 ; + ANTENNAMODEL OXIDE1 ; + ANTENNAGATEAREA 0.20085 LAYER Metal2 ; + ANTENNAMAXAREACAR 4.394822 LAYER Metal2 ; + PORT + LAYER Metal2 ; + RECT 525.945 0 526.205 0.26 ; + END + END B_BM[23] + PIN B_BM[8] + DIRECTION INPUT ; + USE SIGNAL ; + ANTENNAPARTIALMETALAREA 0.7007 LAYER Metal2 ; + ANTENNAMODEL OXIDE1 ; + ANTENNAGATEAREA 0.20085 LAYER Metal2 ; + ANTENNAMAXAREACAR 4.394822 LAYER Metal2 ; + PORT + LAYER Metal2 ; + RECT 159.285 0 159.545 0.26 ; + END + END B_BM[8] + PIN B_BIST_BM[23] + DIRECTION INPUT ; + USE SIGNAL ; + ANTENNAPARTIALMETALAREA 0.7007 LAYER Metal2 ; + ANTENNAMODEL OXIDE1 ; + ANTENNAGATEAREA 0.20085 LAYER Metal2 ; + ANTENNAMAXAREACAR 4.394822 LAYER Metal2 ; + PORT + LAYER Metal2 ; + RECT 527.475 0 527.735 0.26 ; + END + END B_BIST_BM[23] + PIN B_BIST_BM[8] + DIRECTION INPUT ; + USE SIGNAL ; + ANTENNAPARTIALMETALAREA 0.7007 LAYER Metal2 ; + ANTENNAMODEL OXIDE1 ; + ANTENNAGATEAREA 0.20085 LAYER Metal2 ; + ANTENNAMAXAREACAR 4.394822 LAYER Metal2 ; + PORT + LAYER Metal2 ; + RECT 157.755 0 158.015 0.26 ; + END + END B_BIST_BM[8] + PIN B_DOUT[23] + DIRECTION OUTPUT ; + USE SIGNAL ; + ANTENNAPARTIALMETALAREA 4.836 LAYER Metal2 ; + ANTENNADIFFAREA 0.988 LAYER Metal2 ; + PORT + LAYER Metal2 ; + RECT 541.6 0 541.86 0.26 ; + END + END B_DOUT[23] + PIN B_DOUT[8] + DIRECTION OUTPUT ; + USE SIGNAL ; + ANTENNAPARTIALMETALAREA 4.836 LAYER Metal2 ; + ANTENNADIFFAREA 0.988 LAYER Metal2 ; + PORT + LAYER Metal2 ; + RECT 143.63 0 143.89 0.26 ; + END + END B_DOUT[8] + PIN A_DIN[24] + DIRECTION INPUT ; + USE SIGNAL ; + ANTENNAPARTIALMETALAREA 3.9091 LAYER Metal2 ; + ANTENNAMODEL OXIDE1 ; + ANTENNAGATEAREA 0.20085 LAYER Metal2 ; + ANTENNAMAXAREACAR 20.368932 LAYER Metal2 ; + PORT + LAYER Metal2 ; + RECT 549.59 0 549.85 0.26 ; + END + END A_DIN[24] + PIN A_DIN[7] + DIRECTION INPUT ; + USE SIGNAL ; + ANTENNAPARTIALMETALAREA 3.9091 LAYER Metal2 ; + ANTENNAMODEL OXIDE1 ; + ANTENNAGATEAREA 0.20085 LAYER Metal2 ; + ANTENNAMAXAREACAR 20.368932 LAYER Metal2 ; + PORT + LAYER Metal2 ; + RECT 135.64 0 135.9 0.26 ; + END + END A_DIN[7] + PIN A_BIST_DIN[24] + DIRECTION INPUT ; + USE SIGNAL ; + ANTENNAPARTIALMETALAREA 4.136375 LAYER Metal2 ; + ANTENNAMODEL OXIDE1 ; + ANTENNAGATEAREA 0.20085 LAYER Metal2 ; + ANTENNAMAXAREACAR 21.874907 LAYER Metal2 ; + PORT + LAYER Metal2 ; + RECT 550.1 0 550.36 0.26 ; + END + END A_BIST_DIN[24] + PIN A_BIST_DIN[7] + DIRECTION INPUT ; + USE SIGNAL ; + ANTENNAPARTIALMETALAREA 4.136375 LAYER Metal2 ; + ANTENNAMODEL OXIDE1 ; + ANTENNAGATEAREA 0.20085 LAYER Metal2 ; + ANTENNAMAXAREACAR 21.874907 LAYER Metal2 ; + PORT + LAYER Metal2 ; + RECT 135.13 0 135.39 0.26 ; + END + END A_BIST_DIN[7] + PIN A_BM[24] + DIRECTION INPUT ; + USE SIGNAL ; + ANTENNAPARTIALMETALAREA 1.7264 LAYER Metal2 ; + ANTENNAMODEL OXIDE1 ; + ANTENNAGATEAREA 0.20085 LAYER Metal2 ; + ANTENNAMAXAREACAR 9.501618 LAYER Metal2 ; + PORT + LAYER Metal2 ; + RECT 558.26 0 558.52 0.26 ; + END + END A_BM[24] + PIN A_BM[7] + DIRECTION INPUT ; + USE SIGNAL ; + ANTENNAPARTIALMETALAREA 1.7264 LAYER Metal2 ; + ANTENNAMODEL OXIDE1 ; + ANTENNAGATEAREA 0.20085 LAYER Metal2 ; + ANTENNAMAXAREACAR 9.501618 LAYER Metal2 ; + PORT + LAYER Metal2 ; + RECT 126.97 0 127.23 0.26 ; + END + END A_BM[7] + PIN A_BIST_BM[24] + DIRECTION INPUT ; + USE SIGNAL ; + ANTENNAPARTIALMETALAREA 1.7602 LAYER Metal2 ; + ANTENNAMODEL OXIDE1 ; + ANTENNAGATEAREA 0.20085 LAYER Metal2 ; + ANTENNAMAXAREACAR 9.678367 LAYER Metal2 ; + PORT + LAYER Metal2 ; + RECT 556.885 0 557.145 0.26 ; + END + END A_BIST_BM[24] + PIN A_BIST_BM[7] + DIRECTION INPUT ; + USE SIGNAL ; + ANTENNAPARTIALMETALAREA 1.7602 LAYER Metal2 ; + ANTENNAMODEL OXIDE1 ; + ANTENNAGATEAREA 0.20085 LAYER Metal2 ; + ANTENNAMAXAREACAR 9.678367 LAYER Metal2 ; + PORT + LAYER Metal2 ; + RECT 128.345 0 128.605 0.26 ; + END + END A_BIST_BM[7] + PIN A_DOUT[24] + DIRECTION OUTPUT ; + USE SIGNAL ; + ANTENNAPARTIALMETALAREA 4.8256 LAYER Metal2 ; + ANTENNADIFFAREA 0.988 LAYER Metal2 ; + PORT + LAYER Metal2 ; + RECT 542.45 0 542.71 0.26 ; + END + END A_DOUT[24] + PIN A_DOUT[7] + DIRECTION OUTPUT ; + USE SIGNAL ; + ANTENNAPARTIALMETALAREA 4.8256 LAYER Metal2 ; + ANTENNADIFFAREA 0.988 LAYER Metal2 ; + PORT + LAYER Metal2 ; + RECT 142.78 0 143.04 0.26 ; + END + END A_DOUT[7] + PIN B_DIN[24] + DIRECTION INPUT ; + USE SIGNAL ; + ANTENNAPARTIALMETALAREA 2.925 LAYER Metal2 ; + ANTENNAMODEL OXIDE1 ; + ANTENNAGATEAREA 0.20085 LAYER Metal2 ; + ANTENNAMAXAREACAR 15.469256 LAYER Metal2 ; + PORT + LAYER Metal2 ; + RECT 552.14 0 552.4 0.26 ; + END + END B_DIN[24] + PIN B_DIN[7] + DIRECTION INPUT ; + USE SIGNAL ; + ANTENNAPARTIALMETALAREA 2.925 LAYER Metal2 ; + ANTENNAMODEL OXIDE1 ; + ANTENNAGATEAREA 0.20085 LAYER Metal2 ; + ANTENNAMAXAREACAR 15.469256 LAYER Metal2 ; + PORT + LAYER Metal2 ; + RECT 133.09 0 133.35 0.26 ; + END + END B_DIN[7] + PIN B_BIST_DIN[24] + DIRECTION INPUT ; + USE SIGNAL ; + ANTENNAPARTIALMETALAREA 2.9445 LAYER Metal2 ; + ANTENNAMODEL OXIDE1 ; + ANTENNAGATEAREA 0.20085 LAYER Metal2 ; + ANTENNAMAXAREACAR 15.929052 LAYER Metal2 ; + PORT + LAYER Metal2 ; + RECT 550.61 0 550.87 0.26 ; + END + END B_BIST_DIN[24] + PIN B_BIST_DIN[7] + DIRECTION INPUT ; + USE SIGNAL ; + ANTENNAPARTIALMETALAREA 2.9445 LAYER Metal2 ; + ANTENNAMODEL OXIDE1 ; + ANTENNAGATEAREA 0.20085 LAYER Metal2 ; + ANTENNAMAXAREACAR 15.929052 LAYER Metal2 ; + PORT + LAYER Metal2 ; + RECT 134.62 0 134.88 0.26 ; + END + END B_BIST_DIN[7] + PIN B_BM[24] + DIRECTION INPUT ; + USE SIGNAL ; + ANTENNAPARTIALMETALAREA 0.7007 LAYER Metal2 ; + ANTENNAMODEL OXIDE1 ; + ANTENNAGATEAREA 0.20085 LAYER Metal2 ; + ANTENNAMAXAREACAR 4.394822 LAYER Metal2 ; + PORT + LAYER Metal2 ; + RECT 543.625 0 543.885 0.26 ; + END + END B_BM[24] + PIN B_BM[7] + DIRECTION INPUT ; + USE SIGNAL ; + ANTENNAPARTIALMETALAREA 0.7007 LAYER Metal2 ; + ANTENNAMODEL OXIDE1 ; + ANTENNAGATEAREA 0.20085 LAYER Metal2 ; + ANTENNAMAXAREACAR 4.394822 LAYER Metal2 ; + PORT + LAYER Metal2 ; + RECT 141.605 0 141.865 0.26 ; + END + END B_BM[7] + PIN B_BIST_BM[24] + DIRECTION INPUT ; + USE SIGNAL ; + ANTENNAPARTIALMETALAREA 0.7007 LAYER Metal2 ; + ANTENNAMODEL OXIDE1 ; + ANTENNAGATEAREA 0.20085 LAYER Metal2 ; + ANTENNAMAXAREACAR 4.394822 LAYER Metal2 ; + PORT + LAYER Metal2 ; + RECT 545.155 0 545.415 0.26 ; + END + END B_BIST_BM[24] + PIN B_BIST_BM[7] + DIRECTION INPUT ; + USE SIGNAL ; + ANTENNAPARTIALMETALAREA 0.7007 LAYER Metal2 ; + ANTENNAMODEL OXIDE1 ; + ANTENNAGATEAREA 0.20085 LAYER Metal2 ; + ANTENNAMAXAREACAR 4.394822 LAYER Metal2 ; + PORT + LAYER Metal2 ; + RECT 140.075 0 140.335 0.26 ; + END + END B_BIST_BM[7] + PIN B_DOUT[24] + DIRECTION OUTPUT ; + USE SIGNAL ; + ANTENNAPARTIALMETALAREA 4.836 LAYER Metal2 ; + ANTENNADIFFAREA 0.988 LAYER Metal2 ; + PORT + LAYER Metal2 ; + RECT 559.28 0 559.54 0.26 ; + END + END B_DOUT[24] + PIN B_DOUT[7] + DIRECTION OUTPUT ; + USE SIGNAL ; + ANTENNAPARTIALMETALAREA 4.836 LAYER Metal2 ; + ANTENNADIFFAREA 0.988 LAYER Metal2 ; + PORT + LAYER Metal2 ; + RECT 125.95 0 126.21 0.26 ; + END + END B_DOUT[7] + PIN A_DIN[25] + DIRECTION INPUT ; + USE SIGNAL ; + ANTENNAPARTIALMETALAREA 3.9091 LAYER Metal2 ; + ANTENNAMODEL OXIDE1 ; + ANTENNAGATEAREA 0.20085 LAYER Metal2 ; + ANTENNAMAXAREACAR 20.368932 LAYER Metal2 ; + PORT + LAYER Metal2 ; + RECT 567.27 0 567.53 0.26 ; + END + END A_DIN[25] + PIN A_DIN[6] + DIRECTION INPUT ; + USE SIGNAL ; + ANTENNAPARTIALMETALAREA 3.9091 LAYER Metal2 ; + ANTENNAMODEL OXIDE1 ; + ANTENNAGATEAREA 0.20085 LAYER Metal2 ; + ANTENNAMAXAREACAR 20.368932 LAYER Metal2 ; + PORT + LAYER Metal2 ; + RECT 117.96 0 118.22 0.26 ; + END + END A_DIN[6] + PIN A_BIST_DIN[25] + DIRECTION INPUT ; + USE SIGNAL ; + ANTENNAPARTIALMETALAREA 4.136375 LAYER Metal2 ; + ANTENNAMODEL OXIDE1 ; + ANTENNAGATEAREA 0.20085 LAYER Metal2 ; + ANTENNAMAXAREACAR 21.874907 LAYER Metal2 ; + PORT + LAYER Metal2 ; + RECT 567.78 0 568.04 0.26 ; + END + END A_BIST_DIN[25] + PIN A_BIST_DIN[6] + DIRECTION INPUT ; + USE SIGNAL ; + ANTENNAPARTIALMETALAREA 4.136375 LAYER Metal2 ; + ANTENNAMODEL OXIDE1 ; + ANTENNAGATEAREA 0.20085 LAYER Metal2 ; + ANTENNAMAXAREACAR 21.874907 LAYER Metal2 ; + PORT + LAYER Metal2 ; + RECT 117.45 0 117.71 0.26 ; + END + END A_BIST_DIN[6] + PIN A_BM[25] + DIRECTION INPUT ; + USE SIGNAL ; + ANTENNAPARTIALMETALAREA 1.7264 LAYER Metal2 ; + ANTENNAMODEL OXIDE1 ; + ANTENNAGATEAREA 0.20085 LAYER Metal2 ; + ANTENNAMAXAREACAR 9.501618 LAYER Metal2 ; + PORT + LAYER Metal2 ; + RECT 575.94 0 576.2 0.26 ; + END + END A_BM[25] + PIN A_BM[6] + DIRECTION INPUT ; + USE SIGNAL ; + ANTENNAPARTIALMETALAREA 1.7264 LAYER Metal2 ; + ANTENNAMODEL OXIDE1 ; + ANTENNAGATEAREA 0.20085 LAYER Metal2 ; + ANTENNAMAXAREACAR 9.501618 LAYER Metal2 ; + PORT + LAYER Metal2 ; + RECT 109.29 0 109.55 0.26 ; + END + END A_BM[6] + PIN A_BIST_BM[25] + DIRECTION INPUT ; + USE SIGNAL ; + ANTENNAPARTIALMETALAREA 1.7602 LAYER Metal2 ; + ANTENNAMODEL OXIDE1 ; + ANTENNAGATEAREA 0.20085 LAYER Metal2 ; + ANTENNAMAXAREACAR 9.678367 LAYER Metal2 ; + PORT + LAYER Metal2 ; + RECT 574.565 0 574.825 0.26 ; + END + END A_BIST_BM[25] + PIN A_BIST_BM[6] + DIRECTION INPUT ; + USE SIGNAL ; + ANTENNAPARTIALMETALAREA 1.7602 LAYER Metal2 ; + ANTENNAMODEL OXIDE1 ; + ANTENNAGATEAREA 0.20085 LAYER Metal2 ; + ANTENNAMAXAREACAR 9.678367 LAYER Metal2 ; + PORT + LAYER Metal2 ; + RECT 110.665 0 110.925 0.26 ; + END + END A_BIST_BM[6] + PIN A_DOUT[25] + DIRECTION OUTPUT ; + USE SIGNAL ; + ANTENNAPARTIALMETALAREA 4.8256 LAYER Metal2 ; + ANTENNADIFFAREA 0.988 LAYER Metal2 ; + PORT + LAYER Metal2 ; + RECT 560.13 0 560.39 0.26 ; + END + END A_DOUT[25] + PIN A_DOUT[6] + DIRECTION OUTPUT ; + USE SIGNAL ; + ANTENNAPARTIALMETALAREA 4.8256 LAYER Metal2 ; + ANTENNADIFFAREA 0.988 LAYER Metal2 ; + PORT + LAYER Metal2 ; + RECT 125.1 0 125.36 0.26 ; + END + END A_DOUT[6] + PIN B_DIN[25] + DIRECTION INPUT ; + USE SIGNAL ; + ANTENNAPARTIALMETALAREA 2.925 LAYER Metal2 ; + ANTENNAMODEL OXIDE1 ; + ANTENNAGATEAREA 0.20085 LAYER Metal2 ; + ANTENNAMAXAREACAR 15.469256 LAYER Metal2 ; + PORT + LAYER Metal2 ; + RECT 569.82 0 570.08 0.26 ; + END + END B_DIN[25] + PIN B_DIN[6] + DIRECTION INPUT ; + USE SIGNAL ; + ANTENNAPARTIALMETALAREA 2.925 LAYER Metal2 ; + ANTENNAMODEL OXIDE1 ; + ANTENNAGATEAREA 0.20085 LAYER Metal2 ; + ANTENNAMAXAREACAR 15.469256 LAYER Metal2 ; + PORT + LAYER Metal2 ; + RECT 115.41 0 115.67 0.26 ; + END + END B_DIN[6] + PIN B_BIST_DIN[25] + DIRECTION INPUT ; + USE SIGNAL ; + ANTENNAPARTIALMETALAREA 2.9445 LAYER Metal2 ; + ANTENNAMODEL OXIDE1 ; + ANTENNAGATEAREA 0.20085 LAYER Metal2 ; + ANTENNAMAXAREACAR 15.929052 LAYER Metal2 ; + PORT + LAYER Metal2 ; + RECT 568.29 0 568.55 0.26 ; + END + END B_BIST_DIN[25] + PIN B_BIST_DIN[6] + DIRECTION INPUT ; + USE SIGNAL ; + ANTENNAPARTIALMETALAREA 2.9445 LAYER Metal2 ; + ANTENNAMODEL OXIDE1 ; + ANTENNAGATEAREA 0.20085 LAYER Metal2 ; + ANTENNAMAXAREACAR 15.929052 LAYER Metal2 ; + PORT + LAYER Metal2 ; + RECT 116.94 0 117.2 0.26 ; + END + END B_BIST_DIN[6] + PIN B_BM[25] + DIRECTION INPUT ; + USE SIGNAL ; + ANTENNAPARTIALMETALAREA 0.7007 LAYER Metal2 ; + ANTENNAMODEL OXIDE1 ; + ANTENNAGATEAREA 0.20085 LAYER Metal2 ; + ANTENNAMAXAREACAR 4.394822 LAYER Metal2 ; + PORT + LAYER Metal2 ; + RECT 561.305 0 561.565 0.26 ; + END + END B_BM[25] + PIN B_BM[6] + DIRECTION INPUT ; + USE SIGNAL ; + ANTENNAPARTIALMETALAREA 0.7007 LAYER Metal2 ; + ANTENNAMODEL OXIDE1 ; + ANTENNAGATEAREA 0.20085 LAYER Metal2 ; + ANTENNAMAXAREACAR 4.394822 LAYER Metal2 ; + PORT + LAYER Metal2 ; + RECT 123.925 0 124.185 0.26 ; + END + END B_BM[6] + PIN B_BIST_BM[25] + DIRECTION INPUT ; + USE SIGNAL ; + ANTENNAPARTIALMETALAREA 0.7007 LAYER Metal2 ; + ANTENNAMODEL OXIDE1 ; + ANTENNAGATEAREA 0.20085 LAYER Metal2 ; + ANTENNAMAXAREACAR 4.394822 LAYER Metal2 ; + PORT + LAYER Metal2 ; + RECT 562.835 0 563.095 0.26 ; + END + END B_BIST_BM[25] + PIN B_BIST_BM[6] + DIRECTION INPUT ; + USE SIGNAL ; + ANTENNAPARTIALMETALAREA 0.7007 LAYER Metal2 ; + ANTENNAMODEL OXIDE1 ; + ANTENNAGATEAREA 0.20085 LAYER Metal2 ; + ANTENNAMAXAREACAR 4.394822 LAYER Metal2 ; + PORT + LAYER Metal2 ; + RECT 122.395 0 122.655 0.26 ; + END + END B_BIST_BM[6] + PIN B_DOUT[25] + DIRECTION OUTPUT ; + USE SIGNAL ; + ANTENNAPARTIALMETALAREA 4.836 LAYER Metal2 ; + ANTENNADIFFAREA 0.988 LAYER Metal2 ; + PORT + LAYER Metal2 ; + RECT 576.96 0 577.22 0.26 ; + END + END B_DOUT[25] + PIN B_DOUT[6] + DIRECTION OUTPUT ; + USE SIGNAL ; + ANTENNAPARTIALMETALAREA 4.836 LAYER Metal2 ; + ANTENNADIFFAREA 0.988 LAYER Metal2 ; + PORT + LAYER Metal2 ; + RECT 108.27 0 108.53 0.26 ; + END + END B_DOUT[6] + PIN A_DIN[26] + DIRECTION INPUT ; + USE SIGNAL ; + ANTENNAPARTIALMETALAREA 3.9091 LAYER Metal2 ; + ANTENNAMODEL OXIDE1 ; + ANTENNAGATEAREA 0.20085 LAYER Metal2 ; + ANTENNAMAXAREACAR 20.368932 LAYER Metal2 ; + PORT + LAYER Metal2 ; + RECT 584.95 0 585.21 0.26 ; + END + END A_DIN[26] + PIN A_DIN[5] + DIRECTION INPUT ; + USE SIGNAL ; + ANTENNAPARTIALMETALAREA 3.9091 LAYER Metal2 ; + ANTENNAMODEL OXIDE1 ; + ANTENNAGATEAREA 0.20085 LAYER Metal2 ; + ANTENNAMAXAREACAR 20.368932 LAYER Metal2 ; + PORT + LAYER Metal2 ; + RECT 100.28 0 100.54 0.26 ; + END + END A_DIN[5] + PIN A_BIST_DIN[26] + DIRECTION INPUT ; + USE SIGNAL ; + ANTENNAPARTIALMETALAREA 4.136375 LAYER Metal2 ; + ANTENNAMODEL OXIDE1 ; + ANTENNAGATEAREA 0.20085 LAYER Metal2 ; + ANTENNAMAXAREACAR 21.874907 LAYER Metal2 ; + PORT + LAYER Metal2 ; + RECT 585.46 0 585.72 0.26 ; + END + END A_BIST_DIN[26] + PIN A_BIST_DIN[5] + DIRECTION INPUT ; + USE SIGNAL ; + ANTENNAPARTIALMETALAREA 4.136375 LAYER Metal2 ; + ANTENNAMODEL OXIDE1 ; + ANTENNAGATEAREA 0.20085 LAYER Metal2 ; + ANTENNAMAXAREACAR 21.874907 LAYER Metal2 ; + PORT + LAYER Metal2 ; + RECT 99.77 0 100.03 0.26 ; + END + END A_BIST_DIN[5] + PIN A_BM[26] + DIRECTION INPUT ; + USE SIGNAL ; + ANTENNAPARTIALMETALAREA 1.7264 LAYER Metal2 ; + ANTENNAMODEL OXIDE1 ; + ANTENNAGATEAREA 0.20085 LAYER Metal2 ; + ANTENNAMAXAREACAR 9.501618 LAYER Metal2 ; + PORT + LAYER Metal2 ; + RECT 593.62 0 593.88 0.26 ; + END + END A_BM[26] + PIN A_BM[5] + DIRECTION INPUT ; + USE SIGNAL ; + ANTENNAPARTIALMETALAREA 1.7264 LAYER Metal2 ; + ANTENNAMODEL OXIDE1 ; + ANTENNAGATEAREA 0.20085 LAYER Metal2 ; + ANTENNAMAXAREACAR 9.501618 LAYER Metal2 ; + PORT + LAYER Metal2 ; + RECT 91.61 0 91.87 0.26 ; + END + END A_BM[5] + PIN A_BIST_BM[26] + DIRECTION INPUT ; + USE SIGNAL ; + ANTENNAPARTIALMETALAREA 1.7602 LAYER Metal2 ; + ANTENNAMODEL OXIDE1 ; + ANTENNAGATEAREA 0.20085 LAYER Metal2 ; + ANTENNAMAXAREACAR 9.678367 LAYER Metal2 ; + PORT + LAYER Metal2 ; + RECT 592.245 0 592.505 0.26 ; + END + END A_BIST_BM[26] + PIN A_BIST_BM[5] + DIRECTION INPUT ; + USE SIGNAL ; + ANTENNAPARTIALMETALAREA 1.7602 LAYER Metal2 ; + ANTENNAMODEL OXIDE1 ; + ANTENNAGATEAREA 0.20085 LAYER Metal2 ; + ANTENNAMAXAREACAR 9.678367 LAYER Metal2 ; + PORT + LAYER Metal2 ; + RECT 92.985 0 93.245 0.26 ; + END + END A_BIST_BM[5] + PIN A_DOUT[26] + DIRECTION OUTPUT ; + USE SIGNAL ; + ANTENNAPARTIALMETALAREA 4.8256 LAYER Metal2 ; + ANTENNADIFFAREA 0.988 LAYER Metal2 ; + PORT + LAYER Metal2 ; + RECT 577.81 0 578.07 0.26 ; + END + END A_DOUT[26] + PIN A_DOUT[5] + DIRECTION OUTPUT ; + USE SIGNAL ; + ANTENNAPARTIALMETALAREA 4.8256 LAYER Metal2 ; + ANTENNADIFFAREA 0.988 LAYER Metal2 ; + PORT + LAYER Metal2 ; + RECT 107.42 0 107.68 0.26 ; + END + END A_DOUT[5] + PIN B_DIN[26] + DIRECTION INPUT ; + USE SIGNAL ; + ANTENNAPARTIALMETALAREA 2.925 LAYER Metal2 ; + ANTENNAMODEL OXIDE1 ; + ANTENNAGATEAREA 0.20085 LAYER Metal2 ; + ANTENNAMAXAREACAR 15.469256 LAYER Metal2 ; + PORT + LAYER Metal2 ; + RECT 587.5 0 587.76 0.26 ; + END + END B_DIN[26] + PIN B_DIN[5] + DIRECTION INPUT ; + USE SIGNAL ; + ANTENNAPARTIALMETALAREA 2.925 LAYER Metal2 ; + ANTENNAMODEL OXIDE1 ; + ANTENNAGATEAREA 0.20085 LAYER Metal2 ; + ANTENNAMAXAREACAR 15.469256 LAYER Metal2 ; + PORT + LAYER Metal2 ; + RECT 97.73 0 97.99 0.26 ; + END + END B_DIN[5] + PIN B_BIST_DIN[26] + DIRECTION INPUT ; + USE SIGNAL ; + ANTENNAPARTIALMETALAREA 2.9445 LAYER Metal2 ; + ANTENNAMODEL OXIDE1 ; + ANTENNAGATEAREA 0.20085 LAYER Metal2 ; + ANTENNAMAXAREACAR 15.929052 LAYER Metal2 ; + PORT + LAYER Metal2 ; + RECT 585.97 0 586.23 0.26 ; + END + END B_BIST_DIN[26] + PIN B_BIST_DIN[5] + DIRECTION INPUT ; + USE SIGNAL ; + ANTENNAPARTIALMETALAREA 2.9445 LAYER Metal2 ; + ANTENNAMODEL OXIDE1 ; + ANTENNAGATEAREA 0.20085 LAYER Metal2 ; + ANTENNAMAXAREACAR 15.929052 LAYER Metal2 ; + PORT + LAYER Metal2 ; + RECT 99.26 0 99.52 0.26 ; + END + END B_BIST_DIN[5] + PIN B_BM[26] + DIRECTION INPUT ; + USE SIGNAL ; + ANTENNAPARTIALMETALAREA 0.7007 LAYER Metal2 ; + ANTENNAMODEL OXIDE1 ; + ANTENNAGATEAREA 0.20085 LAYER Metal2 ; + ANTENNAMAXAREACAR 4.394822 LAYER Metal2 ; + PORT + LAYER Metal2 ; + RECT 578.985 0 579.245 0.26 ; + END + END B_BM[26] + PIN B_BM[5] + DIRECTION INPUT ; + USE SIGNAL ; + ANTENNAPARTIALMETALAREA 0.7007 LAYER Metal2 ; + ANTENNAMODEL OXIDE1 ; + ANTENNAGATEAREA 0.20085 LAYER Metal2 ; + ANTENNAMAXAREACAR 4.394822 LAYER Metal2 ; + PORT + LAYER Metal2 ; + RECT 106.245 0 106.505 0.26 ; + END + END B_BM[5] + PIN B_BIST_BM[26] + DIRECTION INPUT ; + USE SIGNAL ; + ANTENNAPARTIALMETALAREA 0.7007 LAYER Metal2 ; + ANTENNAMODEL OXIDE1 ; + ANTENNAGATEAREA 0.20085 LAYER Metal2 ; + ANTENNAMAXAREACAR 4.394822 LAYER Metal2 ; + PORT + LAYER Metal2 ; + RECT 580.515 0 580.775 0.26 ; + END + END B_BIST_BM[26] + PIN B_BIST_BM[5] + DIRECTION INPUT ; + USE SIGNAL ; + ANTENNAPARTIALMETALAREA 0.7007 LAYER Metal2 ; + ANTENNAMODEL OXIDE1 ; + ANTENNAGATEAREA 0.20085 LAYER Metal2 ; + ANTENNAMAXAREACAR 4.394822 LAYER Metal2 ; + PORT + LAYER Metal2 ; + RECT 104.715 0 104.975 0.26 ; + END + END B_BIST_BM[5] + PIN B_DOUT[26] + DIRECTION OUTPUT ; + USE SIGNAL ; + ANTENNAPARTIALMETALAREA 4.836 LAYER Metal2 ; + ANTENNADIFFAREA 0.988 LAYER Metal2 ; + PORT + LAYER Metal2 ; + RECT 594.64 0 594.9 0.26 ; + END + END B_DOUT[26] + PIN B_DOUT[5] + DIRECTION OUTPUT ; + USE SIGNAL ; + ANTENNAPARTIALMETALAREA 4.836 LAYER Metal2 ; + ANTENNADIFFAREA 0.988 LAYER Metal2 ; + PORT + LAYER Metal2 ; + RECT 90.59 0 90.85 0.26 ; + END + END B_DOUT[5] + PIN A_DIN[27] + DIRECTION INPUT ; + USE SIGNAL ; + ANTENNAPARTIALMETALAREA 3.9091 LAYER Metal2 ; + ANTENNAMODEL OXIDE1 ; + ANTENNAGATEAREA 0.20085 LAYER Metal2 ; + ANTENNAMAXAREACAR 20.368932 LAYER Metal2 ; + PORT + LAYER Metal2 ; + RECT 602.63 0 602.89 0.26 ; + END + END A_DIN[27] + PIN A_DIN[4] + DIRECTION INPUT ; + USE SIGNAL ; + ANTENNAPARTIALMETALAREA 3.9091 LAYER Metal2 ; + ANTENNAMODEL OXIDE1 ; + ANTENNAGATEAREA 0.20085 LAYER Metal2 ; + ANTENNAMAXAREACAR 20.368932 LAYER Metal2 ; + PORT + LAYER Metal2 ; + RECT 82.6 0 82.86 0.26 ; + END + END A_DIN[4] + PIN A_BIST_DIN[27] + DIRECTION INPUT ; + USE SIGNAL ; + ANTENNAPARTIALMETALAREA 4.136375 LAYER Metal2 ; + ANTENNAMODEL OXIDE1 ; + ANTENNAGATEAREA 0.20085 LAYER Metal2 ; + ANTENNAMAXAREACAR 21.874907 LAYER Metal2 ; + PORT + LAYER Metal2 ; + RECT 603.14 0 603.4 0.26 ; + END + END A_BIST_DIN[27] + PIN A_BIST_DIN[4] + DIRECTION INPUT ; + USE SIGNAL ; + ANTENNAPARTIALMETALAREA 4.136375 LAYER Metal2 ; + ANTENNAMODEL OXIDE1 ; + ANTENNAGATEAREA 0.20085 LAYER Metal2 ; + ANTENNAMAXAREACAR 21.874907 LAYER Metal2 ; + PORT + LAYER Metal2 ; + RECT 82.09 0 82.35 0.26 ; + END + END A_BIST_DIN[4] + PIN A_BM[27] + DIRECTION INPUT ; + USE SIGNAL ; + ANTENNAPARTIALMETALAREA 1.7264 LAYER Metal2 ; + ANTENNAMODEL OXIDE1 ; + ANTENNAGATEAREA 0.20085 LAYER Metal2 ; + ANTENNAMAXAREACAR 9.501618 LAYER Metal2 ; + PORT + LAYER Metal2 ; + RECT 611.3 0 611.56 0.26 ; + END + END A_BM[27] + PIN A_BM[4] + DIRECTION INPUT ; + USE SIGNAL ; + ANTENNAPARTIALMETALAREA 1.7264 LAYER Metal2 ; + ANTENNAMODEL OXIDE1 ; + ANTENNAGATEAREA 0.20085 LAYER Metal2 ; + ANTENNAMAXAREACAR 9.501618 LAYER Metal2 ; + PORT + LAYER Metal2 ; + RECT 73.93 0 74.19 0.26 ; + END + END A_BM[4] + PIN A_BIST_BM[27] + DIRECTION INPUT ; + USE SIGNAL ; + ANTENNAPARTIALMETALAREA 1.7602 LAYER Metal2 ; + ANTENNAMODEL OXIDE1 ; + ANTENNAGATEAREA 0.20085 LAYER Metal2 ; + ANTENNAMAXAREACAR 9.678367 LAYER Metal2 ; + PORT + LAYER Metal2 ; + RECT 609.925 0 610.185 0.26 ; + END + END A_BIST_BM[27] + PIN A_BIST_BM[4] + DIRECTION INPUT ; + USE SIGNAL ; + ANTENNAPARTIALMETALAREA 1.7602 LAYER Metal2 ; + ANTENNAMODEL OXIDE1 ; + ANTENNAGATEAREA 0.20085 LAYER Metal2 ; + ANTENNAMAXAREACAR 9.678367 LAYER Metal2 ; + PORT + LAYER Metal2 ; + RECT 75.305 0 75.565 0.26 ; + END + END A_BIST_BM[4] + PIN A_DOUT[27] + DIRECTION OUTPUT ; + USE SIGNAL ; + ANTENNAPARTIALMETALAREA 4.8256 LAYER Metal2 ; + ANTENNADIFFAREA 0.988 LAYER Metal2 ; + PORT + LAYER Metal2 ; + RECT 595.49 0 595.75 0.26 ; + END + END A_DOUT[27] + PIN A_DOUT[4] + DIRECTION OUTPUT ; + USE SIGNAL ; + ANTENNAPARTIALMETALAREA 4.8256 LAYER Metal2 ; + ANTENNADIFFAREA 0.988 LAYER Metal2 ; + PORT + LAYER Metal2 ; + RECT 89.74 0 90 0.26 ; + END + END A_DOUT[4] + PIN B_DIN[27] + DIRECTION INPUT ; + USE SIGNAL ; + ANTENNAPARTIALMETALAREA 2.925 LAYER Metal2 ; + ANTENNAMODEL OXIDE1 ; + ANTENNAGATEAREA 0.20085 LAYER Metal2 ; + ANTENNAMAXAREACAR 15.469256 LAYER Metal2 ; + PORT + LAYER Metal2 ; + RECT 605.18 0 605.44 0.26 ; + END + END B_DIN[27] + PIN B_DIN[4] + DIRECTION INPUT ; + USE SIGNAL ; + ANTENNAPARTIALMETALAREA 2.925 LAYER Metal2 ; + ANTENNAMODEL OXIDE1 ; + ANTENNAGATEAREA 0.20085 LAYER Metal2 ; + ANTENNAMAXAREACAR 15.469256 LAYER Metal2 ; + PORT + LAYER Metal2 ; + RECT 80.05 0 80.31 0.26 ; + END + END B_DIN[4] + PIN B_BIST_DIN[27] + DIRECTION INPUT ; + USE SIGNAL ; + ANTENNAPARTIALMETALAREA 2.9445 LAYER Metal2 ; + ANTENNAMODEL OXIDE1 ; + ANTENNAGATEAREA 0.20085 LAYER Metal2 ; + ANTENNAMAXAREACAR 15.929052 LAYER Metal2 ; + PORT + LAYER Metal2 ; + RECT 603.65 0 603.91 0.26 ; + END + END B_BIST_DIN[27] + PIN B_BIST_DIN[4] + DIRECTION INPUT ; + USE SIGNAL ; + ANTENNAPARTIALMETALAREA 2.9445 LAYER Metal2 ; + ANTENNAMODEL OXIDE1 ; + ANTENNAGATEAREA 0.20085 LAYER Metal2 ; + ANTENNAMAXAREACAR 15.929052 LAYER Metal2 ; + PORT + LAYER Metal2 ; + RECT 81.58 0 81.84 0.26 ; + END + END B_BIST_DIN[4] + PIN B_BM[27] + DIRECTION INPUT ; + USE SIGNAL ; + ANTENNAPARTIALMETALAREA 0.7007 LAYER Metal2 ; + ANTENNAMODEL OXIDE1 ; + ANTENNAGATEAREA 0.20085 LAYER Metal2 ; + ANTENNAMAXAREACAR 4.394822 LAYER Metal2 ; + PORT + LAYER Metal2 ; + RECT 596.665 0 596.925 0.26 ; + END + END B_BM[27] + PIN B_BM[4] + DIRECTION INPUT ; + USE SIGNAL ; + ANTENNAPARTIALMETALAREA 0.7007 LAYER Metal2 ; + ANTENNAMODEL OXIDE1 ; + ANTENNAGATEAREA 0.20085 LAYER Metal2 ; + ANTENNAMAXAREACAR 4.394822 LAYER Metal2 ; + PORT + LAYER Metal2 ; + RECT 88.565 0 88.825 0.26 ; + END + END B_BM[4] + PIN B_BIST_BM[27] + DIRECTION INPUT ; + USE SIGNAL ; + ANTENNAPARTIALMETALAREA 0.7007 LAYER Metal2 ; + ANTENNAMODEL OXIDE1 ; + ANTENNAGATEAREA 0.20085 LAYER Metal2 ; + ANTENNAMAXAREACAR 4.394822 LAYER Metal2 ; + PORT + LAYER Metal2 ; + RECT 598.195 0 598.455 0.26 ; + END + END B_BIST_BM[27] + PIN B_BIST_BM[4] + DIRECTION INPUT ; + USE SIGNAL ; + ANTENNAPARTIALMETALAREA 0.7007 LAYER Metal2 ; + ANTENNAMODEL OXIDE1 ; + ANTENNAGATEAREA 0.20085 LAYER Metal2 ; + ANTENNAMAXAREACAR 4.394822 LAYER Metal2 ; + PORT + LAYER Metal2 ; + RECT 87.035 0 87.295 0.26 ; + END + END B_BIST_BM[4] + PIN B_DOUT[27] + DIRECTION OUTPUT ; + USE SIGNAL ; + ANTENNAPARTIALMETALAREA 4.836 LAYER Metal2 ; + ANTENNADIFFAREA 0.988 LAYER Metal2 ; + PORT + LAYER Metal2 ; + RECT 612.32 0 612.58 0.26 ; + END + END B_DOUT[27] + PIN B_DOUT[4] + DIRECTION OUTPUT ; + USE SIGNAL ; + ANTENNAPARTIALMETALAREA 4.836 LAYER Metal2 ; + ANTENNADIFFAREA 0.988 LAYER Metal2 ; + PORT + LAYER Metal2 ; + RECT 72.91 0 73.17 0.26 ; + END + END B_DOUT[4] + PIN A_DIN[28] + DIRECTION INPUT ; + USE SIGNAL ; + ANTENNAPARTIALMETALAREA 3.9091 LAYER Metal2 ; + ANTENNAMODEL OXIDE1 ; + ANTENNAGATEAREA 0.20085 LAYER Metal2 ; + ANTENNAMAXAREACAR 20.368932 LAYER Metal2 ; + PORT + LAYER Metal2 ; + RECT 620.31 0 620.57 0.26 ; + END + END A_DIN[28] + PIN A_DIN[3] + DIRECTION INPUT ; + USE SIGNAL ; + ANTENNAPARTIALMETALAREA 3.9091 LAYER Metal2 ; + ANTENNAMODEL OXIDE1 ; + ANTENNAGATEAREA 0.20085 LAYER Metal2 ; + ANTENNAMAXAREACAR 20.368932 LAYER Metal2 ; + PORT + LAYER Metal2 ; + RECT 64.92 0 65.18 0.26 ; + END + END A_DIN[3] + PIN A_BIST_DIN[28] + DIRECTION INPUT ; + USE SIGNAL ; + ANTENNAPARTIALMETALAREA 4.136375 LAYER Metal2 ; + ANTENNAMODEL OXIDE1 ; + ANTENNAGATEAREA 0.20085 LAYER Metal2 ; + ANTENNAMAXAREACAR 21.874907 LAYER Metal2 ; + PORT + LAYER Metal2 ; + RECT 620.82 0 621.08 0.26 ; + END + END A_BIST_DIN[28] + PIN A_BIST_DIN[3] + DIRECTION INPUT ; + USE SIGNAL ; + ANTENNAPARTIALMETALAREA 4.136375 LAYER Metal2 ; + ANTENNAMODEL OXIDE1 ; + ANTENNAGATEAREA 0.20085 LAYER Metal2 ; + ANTENNAMAXAREACAR 21.874907 LAYER Metal2 ; + PORT + LAYER Metal2 ; + RECT 64.41 0 64.67 0.26 ; + END + END A_BIST_DIN[3] + PIN A_BM[28] + DIRECTION INPUT ; + USE SIGNAL ; + ANTENNAPARTIALMETALAREA 1.7264 LAYER Metal2 ; + ANTENNAMODEL OXIDE1 ; + ANTENNAGATEAREA 0.20085 LAYER Metal2 ; + ANTENNAMAXAREACAR 9.501618 LAYER Metal2 ; + PORT + LAYER Metal2 ; + RECT 628.98 0 629.24 0.26 ; + END + END A_BM[28] + PIN A_BM[3] + DIRECTION INPUT ; + USE SIGNAL ; + ANTENNAPARTIALMETALAREA 1.7264 LAYER Metal2 ; + ANTENNAMODEL OXIDE1 ; + ANTENNAGATEAREA 0.20085 LAYER Metal2 ; + ANTENNAMAXAREACAR 9.501618 LAYER Metal2 ; + PORT + LAYER Metal2 ; + RECT 56.25 0 56.51 0.26 ; + END + END A_BM[3] + PIN A_BIST_BM[28] + DIRECTION INPUT ; + USE SIGNAL ; + ANTENNAPARTIALMETALAREA 1.7602 LAYER Metal2 ; + ANTENNAMODEL OXIDE1 ; + ANTENNAGATEAREA 0.20085 LAYER Metal2 ; + ANTENNAMAXAREACAR 9.678367 LAYER Metal2 ; + PORT + LAYER Metal2 ; + RECT 627.605 0 627.865 0.26 ; + END + END A_BIST_BM[28] + PIN A_BIST_BM[3] + DIRECTION INPUT ; + USE SIGNAL ; + ANTENNAPARTIALMETALAREA 1.7602 LAYER Metal2 ; + ANTENNAMODEL OXIDE1 ; + ANTENNAGATEAREA 0.20085 LAYER Metal2 ; + ANTENNAMAXAREACAR 9.678367 LAYER Metal2 ; + PORT + LAYER Metal2 ; + RECT 57.625 0 57.885 0.26 ; + END + END A_BIST_BM[3] + PIN A_DOUT[28] + DIRECTION OUTPUT ; + USE SIGNAL ; + ANTENNAPARTIALMETALAREA 4.8256 LAYER Metal2 ; + ANTENNADIFFAREA 0.988 LAYER Metal2 ; + PORT + LAYER Metal2 ; + RECT 613.17 0 613.43 0.26 ; + END + END A_DOUT[28] + PIN A_DOUT[3] + DIRECTION OUTPUT ; + USE SIGNAL ; + ANTENNAPARTIALMETALAREA 4.8256 LAYER Metal2 ; + ANTENNADIFFAREA 0.988 LAYER Metal2 ; + PORT + LAYER Metal2 ; + RECT 72.06 0 72.32 0.26 ; + END + END A_DOUT[3] + PIN B_DIN[28] + DIRECTION INPUT ; + USE SIGNAL ; + ANTENNAPARTIALMETALAREA 2.925 LAYER Metal2 ; + ANTENNAMODEL OXIDE1 ; + ANTENNAGATEAREA 0.20085 LAYER Metal2 ; + ANTENNAMAXAREACAR 15.469256 LAYER Metal2 ; + PORT + LAYER Metal2 ; + RECT 622.86 0 623.12 0.26 ; + END + END B_DIN[28] + PIN B_DIN[3] + DIRECTION INPUT ; + USE SIGNAL ; + ANTENNAPARTIALMETALAREA 2.925 LAYER Metal2 ; + ANTENNAMODEL OXIDE1 ; + ANTENNAGATEAREA 0.20085 LAYER Metal2 ; + ANTENNAMAXAREACAR 15.469256 LAYER Metal2 ; + PORT + LAYER Metal2 ; + RECT 62.37 0 62.63 0.26 ; + END + END B_DIN[3] + PIN B_BIST_DIN[28] + DIRECTION INPUT ; + USE SIGNAL ; + ANTENNAPARTIALMETALAREA 2.9445 LAYER Metal2 ; + ANTENNAMODEL OXIDE1 ; + ANTENNAGATEAREA 0.20085 LAYER Metal2 ; + ANTENNAMAXAREACAR 15.929052 LAYER Metal2 ; + PORT + LAYER Metal2 ; + RECT 621.33 0 621.59 0.26 ; + END + END B_BIST_DIN[28] + PIN B_BIST_DIN[3] + DIRECTION INPUT ; + USE SIGNAL ; + ANTENNAPARTIALMETALAREA 2.9445 LAYER Metal2 ; + ANTENNAMODEL OXIDE1 ; + ANTENNAGATEAREA 0.20085 LAYER Metal2 ; + ANTENNAMAXAREACAR 15.929052 LAYER Metal2 ; + PORT + LAYER Metal2 ; + RECT 63.9 0 64.16 0.26 ; + END + END B_BIST_DIN[3] + PIN B_BM[28] + DIRECTION INPUT ; + USE SIGNAL ; + ANTENNAPARTIALMETALAREA 0.7007 LAYER Metal2 ; + ANTENNAMODEL OXIDE1 ; + ANTENNAGATEAREA 0.20085 LAYER Metal2 ; + ANTENNAMAXAREACAR 4.394822 LAYER Metal2 ; + PORT + LAYER Metal2 ; + RECT 614.345 0 614.605 0.26 ; + END + END B_BM[28] + PIN B_BM[3] + DIRECTION INPUT ; + USE SIGNAL ; + ANTENNAPARTIALMETALAREA 0.7007 LAYER Metal2 ; + ANTENNAMODEL OXIDE1 ; + ANTENNAGATEAREA 0.20085 LAYER Metal2 ; + ANTENNAMAXAREACAR 4.394822 LAYER Metal2 ; + PORT + LAYER Metal2 ; + RECT 70.885 0 71.145 0.26 ; + END + END B_BM[3] + PIN B_BIST_BM[28] + DIRECTION INPUT ; + USE SIGNAL ; + ANTENNAPARTIALMETALAREA 0.7007 LAYER Metal2 ; + ANTENNAMODEL OXIDE1 ; + ANTENNAGATEAREA 0.20085 LAYER Metal2 ; + ANTENNAMAXAREACAR 4.394822 LAYER Metal2 ; + PORT + LAYER Metal2 ; + RECT 615.875 0 616.135 0.26 ; + END + END B_BIST_BM[28] + PIN B_BIST_BM[3] + DIRECTION INPUT ; + USE SIGNAL ; + ANTENNAPARTIALMETALAREA 0.7007 LAYER Metal2 ; + ANTENNAMODEL OXIDE1 ; + ANTENNAGATEAREA 0.20085 LAYER Metal2 ; + ANTENNAMAXAREACAR 4.394822 LAYER Metal2 ; + PORT + LAYER Metal2 ; + RECT 69.355 0 69.615 0.26 ; + END + END B_BIST_BM[3] + PIN B_DOUT[28] + DIRECTION OUTPUT ; + USE SIGNAL ; + ANTENNAPARTIALMETALAREA 4.836 LAYER Metal2 ; + ANTENNADIFFAREA 0.988 LAYER Metal2 ; + PORT + LAYER Metal2 ; + RECT 630 0 630.26 0.26 ; + END + END B_DOUT[28] + PIN B_DOUT[3] + DIRECTION OUTPUT ; + USE SIGNAL ; + ANTENNAPARTIALMETALAREA 4.836 LAYER Metal2 ; + ANTENNADIFFAREA 0.988 LAYER Metal2 ; + PORT + LAYER Metal2 ; + RECT 55.23 0 55.49 0.26 ; + END + END B_DOUT[3] + PIN A_DIN[29] + DIRECTION INPUT ; + USE SIGNAL ; + ANTENNAPARTIALMETALAREA 3.9091 LAYER Metal2 ; + ANTENNAMODEL OXIDE1 ; + ANTENNAGATEAREA 0.20085 LAYER Metal2 ; + ANTENNAMAXAREACAR 20.368932 LAYER Metal2 ; + PORT + LAYER Metal2 ; + RECT 637.99 0 638.25 0.26 ; + END + END A_DIN[29] + PIN A_DIN[2] + DIRECTION INPUT ; + USE SIGNAL ; + ANTENNAPARTIALMETALAREA 3.9091 LAYER Metal2 ; + ANTENNAMODEL OXIDE1 ; + ANTENNAGATEAREA 0.20085 LAYER Metal2 ; + ANTENNAMAXAREACAR 20.368932 LAYER Metal2 ; + PORT + LAYER Metal2 ; + RECT 47.24 0 47.5 0.26 ; + END + END A_DIN[2] + PIN A_BIST_DIN[29] + DIRECTION INPUT ; + USE SIGNAL ; + ANTENNAPARTIALMETALAREA 4.136375 LAYER Metal2 ; + ANTENNAMODEL OXIDE1 ; + ANTENNAGATEAREA 0.20085 LAYER Metal2 ; + ANTENNAMAXAREACAR 21.874907 LAYER Metal2 ; + PORT + LAYER Metal2 ; + RECT 638.5 0 638.76 0.26 ; + END + END A_BIST_DIN[29] + PIN A_BIST_DIN[2] + DIRECTION INPUT ; + USE SIGNAL ; + ANTENNAPARTIALMETALAREA 4.136375 LAYER Metal2 ; + ANTENNAMODEL OXIDE1 ; + ANTENNAGATEAREA 0.20085 LAYER Metal2 ; + ANTENNAMAXAREACAR 21.874907 LAYER Metal2 ; + PORT + LAYER Metal2 ; + RECT 46.73 0 46.99 0.26 ; + END + END A_BIST_DIN[2] + PIN A_BM[29] + DIRECTION INPUT ; + USE SIGNAL ; + ANTENNAPARTIALMETALAREA 1.7264 LAYER Metal2 ; + ANTENNAMODEL OXIDE1 ; + ANTENNAGATEAREA 0.20085 LAYER Metal2 ; + ANTENNAMAXAREACAR 9.501618 LAYER Metal2 ; + PORT + LAYER Metal2 ; + RECT 646.66 0 646.92 0.26 ; + END + END A_BM[29] + PIN A_BM[2] + DIRECTION INPUT ; + USE SIGNAL ; + ANTENNAPARTIALMETALAREA 1.7264 LAYER Metal2 ; + ANTENNAMODEL OXIDE1 ; + ANTENNAGATEAREA 0.20085 LAYER Metal2 ; + ANTENNAMAXAREACAR 9.501618 LAYER Metal2 ; + PORT + LAYER Metal2 ; + RECT 38.57 0 38.83 0.26 ; + END + END A_BM[2] + PIN A_BIST_BM[29] + DIRECTION INPUT ; + USE SIGNAL ; + ANTENNAPARTIALMETALAREA 1.7602 LAYER Metal2 ; + ANTENNAMODEL OXIDE1 ; + ANTENNAGATEAREA 0.20085 LAYER Metal2 ; + ANTENNAMAXAREACAR 9.678367 LAYER Metal2 ; + PORT + LAYER Metal2 ; + RECT 645.285 0 645.545 0.26 ; + END + END A_BIST_BM[29] + PIN A_BIST_BM[2] + DIRECTION INPUT ; + USE SIGNAL ; + ANTENNAPARTIALMETALAREA 1.7602 LAYER Metal2 ; + ANTENNAMODEL OXIDE1 ; + ANTENNAGATEAREA 0.20085 LAYER Metal2 ; + ANTENNAMAXAREACAR 9.678367 LAYER Metal2 ; + PORT + LAYER Metal2 ; + RECT 39.945 0 40.205 0.26 ; + END + END A_BIST_BM[2] + PIN A_DOUT[29] + DIRECTION OUTPUT ; + USE SIGNAL ; + ANTENNAPARTIALMETALAREA 4.8256 LAYER Metal2 ; + ANTENNADIFFAREA 0.988 LAYER Metal2 ; + PORT + LAYER Metal2 ; + RECT 630.85 0 631.11 0.26 ; + END + END A_DOUT[29] + PIN A_DOUT[2] + DIRECTION OUTPUT ; + USE SIGNAL ; + ANTENNAPARTIALMETALAREA 4.8256 LAYER Metal2 ; + ANTENNADIFFAREA 0.988 LAYER Metal2 ; + PORT + LAYER Metal2 ; + RECT 54.38 0 54.64 0.26 ; + END + END A_DOUT[2] + PIN B_DIN[29] + DIRECTION INPUT ; + USE SIGNAL ; + ANTENNAPARTIALMETALAREA 2.925 LAYER Metal2 ; + ANTENNAMODEL OXIDE1 ; + ANTENNAGATEAREA 0.20085 LAYER Metal2 ; + ANTENNAMAXAREACAR 15.469256 LAYER Metal2 ; + PORT + LAYER Metal2 ; + RECT 640.54 0 640.8 0.26 ; + END + END B_DIN[29] + PIN B_DIN[2] + DIRECTION INPUT ; + USE SIGNAL ; + ANTENNAPARTIALMETALAREA 2.925 LAYER Metal2 ; + ANTENNAMODEL OXIDE1 ; + ANTENNAGATEAREA 0.20085 LAYER Metal2 ; + ANTENNAMAXAREACAR 15.469256 LAYER Metal2 ; + PORT + LAYER Metal2 ; + RECT 44.69 0 44.95 0.26 ; + END + END B_DIN[2] + PIN B_BIST_DIN[29] + DIRECTION INPUT ; + USE SIGNAL ; + ANTENNAPARTIALMETALAREA 2.9445 LAYER Metal2 ; + ANTENNAMODEL OXIDE1 ; + ANTENNAGATEAREA 0.20085 LAYER Metal2 ; + ANTENNAMAXAREACAR 15.929052 LAYER Metal2 ; + PORT + LAYER Metal2 ; + RECT 639.01 0 639.27 0.26 ; + END + END B_BIST_DIN[29] + PIN B_BIST_DIN[2] + DIRECTION INPUT ; + USE SIGNAL ; + ANTENNAPARTIALMETALAREA 2.9445 LAYER Metal2 ; + ANTENNAMODEL OXIDE1 ; + ANTENNAGATEAREA 0.20085 LAYER Metal2 ; + ANTENNAMAXAREACAR 15.929052 LAYER Metal2 ; + PORT + LAYER Metal2 ; + RECT 46.22 0 46.48 0.26 ; + END + END B_BIST_DIN[2] + PIN B_BM[29] + DIRECTION INPUT ; + USE SIGNAL ; + ANTENNAPARTIALMETALAREA 0.7007 LAYER Metal2 ; + ANTENNAMODEL OXIDE1 ; + ANTENNAGATEAREA 0.20085 LAYER Metal2 ; + ANTENNAMAXAREACAR 4.394822 LAYER Metal2 ; + PORT + LAYER Metal2 ; + RECT 632.025 0 632.285 0.26 ; + END + END B_BM[29] + PIN B_BM[2] + DIRECTION INPUT ; + USE SIGNAL ; + ANTENNAPARTIALMETALAREA 0.7007 LAYER Metal2 ; + ANTENNAMODEL OXIDE1 ; + ANTENNAGATEAREA 0.20085 LAYER Metal2 ; + ANTENNAMAXAREACAR 4.394822 LAYER Metal2 ; + PORT + LAYER Metal2 ; + RECT 53.205 0 53.465 0.26 ; + END + END B_BM[2] + PIN B_BIST_BM[29] + DIRECTION INPUT ; + USE SIGNAL ; + ANTENNAPARTIALMETALAREA 0.7007 LAYER Metal2 ; + ANTENNAMODEL OXIDE1 ; + ANTENNAGATEAREA 0.20085 LAYER Metal2 ; + ANTENNAMAXAREACAR 4.394822 LAYER Metal2 ; + PORT + LAYER Metal2 ; + RECT 633.555 0 633.815 0.26 ; + END + END B_BIST_BM[29] + PIN B_BIST_BM[2] + DIRECTION INPUT ; + USE SIGNAL ; + ANTENNAPARTIALMETALAREA 0.7007 LAYER Metal2 ; + ANTENNAMODEL OXIDE1 ; + ANTENNAGATEAREA 0.20085 LAYER Metal2 ; + ANTENNAMAXAREACAR 4.394822 LAYER Metal2 ; + PORT + LAYER Metal2 ; + RECT 51.675 0 51.935 0.26 ; + END + END B_BIST_BM[2] + PIN B_DOUT[29] + DIRECTION OUTPUT ; + USE SIGNAL ; + ANTENNAPARTIALMETALAREA 4.836 LAYER Metal2 ; + ANTENNADIFFAREA 0.988 LAYER Metal2 ; + PORT + LAYER Metal2 ; + RECT 647.68 0 647.94 0.26 ; + END + END B_DOUT[29] + PIN B_DOUT[2] + DIRECTION OUTPUT ; + USE SIGNAL ; + ANTENNAPARTIALMETALAREA 4.836 LAYER Metal2 ; + ANTENNADIFFAREA 0.988 LAYER Metal2 ; + PORT + LAYER Metal2 ; + RECT 37.55 0 37.81 0.26 ; + END + END B_DOUT[2] + PIN A_DIN[30] + DIRECTION INPUT ; + USE SIGNAL ; + ANTENNAPARTIALMETALAREA 3.9091 LAYER Metal2 ; + ANTENNAMODEL OXIDE1 ; + ANTENNAGATEAREA 0.20085 LAYER Metal2 ; + ANTENNAMAXAREACAR 20.368932 LAYER Metal2 ; + PORT + LAYER Metal2 ; + RECT 655.67 0 655.93 0.26 ; + END + END A_DIN[30] + PIN A_DIN[1] + DIRECTION INPUT ; + USE SIGNAL ; + ANTENNAPARTIALMETALAREA 3.9091 LAYER Metal2 ; + ANTENNAMODEL OXIDE1 ; + ANTENNAGATEAREA 0.20085 LAYER Metal2 ; + ANTENNAMAXAREACAR 20.368932 LAYER Metal2 ; + PORT + LAYER Metal2 ; + RECT 29.56 0 29.82 0.26 ; + END + END A_DIN[1] + PIN A_BIST_DIN[30] + DIRECTION INPUT ; + USE SIGNAL ; + ANTENNAPARTIALMETALAREA 4.136375 LAYER Metal2 ; + ANTENNAMODEL OXIDE1 ; + ANTENNAGATEAREA 0.20085 LAYER Metal2 ; + ANTENNAMAXAREACAR 21.874907 LAYER Metal2 ; + PORT + LAYER Metal2 ; + RECT 656.18 0 656.44 0.26 ; + END + END A_BIST_DIN[30] + PIN A_BIST_DIN[1] + DIRECTION INPUT ; + USE SIGNAL ; + ANTENNAPARTIALMETALAREA 4.136375 LAYER Metal2 ; + ANTENNAMODEL OXIDE1 ; + ANTENNAGATEAREA 0.20085 LAYER Metal2 ; + ANTENNAMAXAREACAR 21.874907 LAYER Metal2 ; + PORT + LAYER Metal2 ; + RECT 29.05 0 29.31 0.26 ; + END + END A_BIST_DIN[1] + PIN A_BM[30] + DIRECTION INPUT ; + USE SIGNAL ; + ANTENNAPARTIALMETALAREA 1.7264 LAYER Metal2 ; + ANTENNAMODEL OXIDE1 ; + ANTENNAGATEAREA 0.20085 LAYER Metal2 ; + ANTENNAMAXAREACAR 9.501618 LAYER Metal2 ; + PORT + LAYER Metal2 ; + RECT 664.34 0 664.6 0.26 ; + END + END A_BM[30] + PIN A_BM[1] + DIRECTION INPUT ; + USE SIGNAL ; + ANTENNAPARTIALMETALAREA 1.7264 LAYER Metal2 ; + ANTENNAMODEL OXIDE1 ; + ANTENNAGATEAREA 0.20085 LAYER Metal2 ; + ANTENNAMAXAREACAR 9.501618 LAYER Metal2 ; + PORT + LAYER Metal2 ; + RECT 20.89 0 21.15 0.26 ; + END + END A_BM[1] + PIN A_BIST_BM[30] + DIRECTION INPUT ; + USE SIGNAL ; + ANTENNAPARTIALMETALAREA 1.7602 LAYER Metal2 ; + ANTENNAMODEL OXIDE1 ; + ANTENNAGATEAREA 0.20085 LAYER Metal2 ; + ANTENNAMAXAREACAR 9.678367 LAYER Metal2 ; + PORT + LAYER Metal2 ; + RECT 662.965 0 663.225 0.26 ; + END + END A_BIST_BM[30] + PIN A_BIST_BM[1] + DIRECTION INPUT ; + USE SIGNAL ; + ANTENNAPARTIALMETALAREA 1.7602 LAYER Metal2 ; + ANTENNAMODEL OXIDE1 ; + ANTENNAGATEAREA 0.20085 LAYER Metal2 ; + ANTENNAMAXAREACAR 9.678367 LAYER Metal2 ; + PORT + LAYER Metal2 ; + RECT 22.265 0 22.525 0.26 ; + END + END A_BIST_BM[1] + PIN A_DOUT[30] + DIRECTION OUTPUT ; + USE SIGNAL ; + ANTENNAPARTIALMETALAREA 4.8256 LAYER Metal2 ; + ANTENNADIFFAREA 0.988 LAYER Metal2 ; + PORT + LAYER Metal2 ; + RECT 648.53 0 648.79 0.26 ; + END + END A_DOUT[30] + PIN A_DOUT[1] + DIRECTION OUTPUT ; + USE SIGNAL ; + ANTENNAPARTIALMETALAREA 4.8256 LAYER Metal2 ; + ANTENNADIFFAREA 0.988 LAYER Metal2 ; + PORT + LAYER Metal2 ; + RECT 36.7 0 36.96 0.26 ; + END + END A_DOUT[1] + PIN B_DIN[30] + DIRECTION INPUT ; + USE SIGNAL ; + ANTENNAPARTIALMETALAREA 2.925 LAYER Metal2 ; + ANTENNAMODEL OXIDE1 ; + ANTENNAGATEAREA 0.20085 LAYER Metal2 ; + ANTENNAMAXAREACAR 15.469256 LAYER Metal2 ; + PORT + LAYER Metal2 ; + RECT 658.22 0 658.48 0.26 ; + END + END B_DIN[30] + PIN B_DIN[1] + DIRECTION INPUT ; + USE SIGNAL ; + ANTENNAPARTIALMETALAREA 2.925 LAYER Metal2 ; + ANTENNAMODEL OXIDE1 ; + ANTENNAGATEAREA 0.20085 LAYER Metal2 ; + ANTENNAMAXAREACAR 15.469256 LAYER Metal2 ; + PORT + LAYER Metal2 ; + RECT 27.01 0 27.27 0.26 ; + END + END B_DIN[1] + PIN B_BIST_DIN[30] + DIRECTION INPUT ; + USE SIGNAL ; + ANTENNAPARTIALMETALAREA 2.9445 LAYER Metal2 ; + ANTENNAMODEL OXIDE1 ; + ANTENNAGATEAREA 0.20085 LAYER Metal2 ; + ANTENNAMAXAREACAR 15.929052 LAYER Metal2 ; + PORT + LAYER Metal2 ; + RECT 656.69 0 656.95 0.26 ; + END + END B_BIST_DIN[30] + PIN B_BIST_DIN[1] + DIRECTION INPUT ; + USE SIGNAL ; + ANTENNAPARTIALMETALAREA 2.9445 LAYER Metal2 ; + ANTENNAMODEL OXIDE1 ; + ANTENNAGATEAREA 0.20085 LAYER Metal2 ; + ANTENNAMAXAREACAR 15.929052 LAYER Metal2 ; + PORT + LAYER Metal2 ; + RECT 28.54 0 28.8 0.26 ; + END + END B_BIST_DIN[1] + PIN B_BM[30] + DIRECTION INPUT ; + USE SIGNAL ; + ANTENNAPARTIALMETALAREA 0.7007 LAYER Metal2 ; + ANTENNAMODEL OXIDE1 ; + ANTENNAGATEAREA 0.20085 LAYER Metal2 ; + ANTENNAMAXAREACAR 4.394822 LAYER Metal2 ; + PORT + LAYER Metal2 ; + RECT 649.705 0 649.965 0.26 ; + END + END B_BM[30] + PIN B_BM[1] + DIRECTION INPUT ; + USE SIGNAL ; + ANTENNAPARTIALMETALAREA 0.7007 LAYER Metal2 ; + ANTENNAMODEL OXIDE1 ; + ANTENNAGATEAREA 0.20085 LAYER Metal2 ; + ANTENNAMAXAREACAR 4.394822 LAYER Metal2 ; + PORT + LAYER Metal2 ; + RECT 35.525 0 35.785 0.26 ; + END + END B_BM[1] + PIN B_BIST_BM[30] + DIRECTION INPUT ; + USE SIGNAL ; + ANTENNAPARTIALMETALAREA 0.7007 LAYER Metal2 ; + ANTENNAMODEL OXIDE1 ; + ANTENNAGATEAREA 0.20085 LAYER Metal2 ; + ANTENNAMAXAREACAR 4.394822 LAYER Metal2 ; + PORT + LAYER Metal2 ; + RECT 651.235 0 651.495 0.26 ; + END + END B_BIST_BM[30] + PIN B_BIST_BM[1] + DIRECTION INPUT ; + USE SIGNAL ; + ANTENNAPARTIALMETALAREA 0.7007 LAYER Metal2 ; + ANTENNAMODEL OXIDE1 ; + ANTENNAGATEAREA 0.20085 LAYER Metal2 ; + ANTENNAMAXAREACAR 4.394822 LAYER Metal2 ; + PORT + LAYER Metal2 ; + RECT 33.995 0 34.255 0.26 ; + END + END B_BIST_BM[1] + PIN B_DOUT[30] + DIRECTION OUTPUT ; + USE SIGNAL ; + ANTENNAPARTIALMETALAREA 4.836 LAYER Metal2 ; + ANTENNADIFFAREA 0.988 LAYER Metal2 ; + PORT + LAYER Metal2 ; + RECT 665.36 0 665.62 0.26 ; + END + END B_DOUT[30] + PIN B_DOUT[1] + DIRECTION OUTPUT ; + USE SIGNAL ; + ANTENNAPARTIALMETALAREA 4.836 LAYER Metal2 ; + ANTENNADIFFAREA 0.988 LAYER Metal2 ; + PORT + LAYER Metal2 ; + RECT 19.87 0 20.13 0.26 ; + END + END B_DOUT[1] + PIN A_DIN[31] + DIRECTION INPUT ; + USE SIGNAL ; + ANTENNAPARTIALMETALAREA 3.9091 LAYER Metal2 ; + ANTENNAMODEL OXIDE1 ; + ANTENNAGATEAREA 0.20085 LAYER Metal2 ; + ANTENNAMAXAREACAR 20.368932 LAYER Metal2 ; + PORT + LAYER Metal2 ; + RECT 673.35 0 673.61 0.26 ; + END + END A_DIN[31] + PIN A_DIN[0] + DIRECTION INPUT ; + USE SIGNAL ; + ANTENNAPARTIALMETALAREA 3.9091 LAYER Metal2 ; + ANTENNAMODEL OXIDE1 ; + ANTENNAGATEAREA 0.20085 LAYER Metal2 ; + ANTENNAMAXAREACAR 20.368932 LAYER Metal2 ; + PORT + LAYER Metal2 ; + RECT 11.88 0 12.14 0.26 ; + END + END A_DIN[0] + PIN A_BIST_DIN[31] + DIRECTION INPUT ; + USE SIGNAL ; + ANTENNAPARTIALMETALAREA 4.136375 LAYER Metal2 ; + ANTENNAMODEL OXIDE1 ; + ANTENNAGATEAREA 0.20085 LAYER Metal2 ; + ANTENNAMAXAREACAR 21.874907 LAYER Metal2 ; + PORT + LAYER Metal2 ; + RECT 673.86 0 674.12 0.26 ; + END + END A_BIST_DIN[31] + PIN A_BIST_DIN[0] + DIRECTION INPUT ; + USE SIGNAL ; + ANTENNAPARTIALMETALAREA 4.136375 LAYER Metal2 ; + ANTENNAMODEL OXIDE1 ; + ANTENNAGATEAREA 0.20085 LAYER Metal2 ; + ANTENNAMAXAREACAR 21.874907 LAYER Metal2 ; + PORT + LAYER Metal2 ; + RECT 11.37 0 11.63 0.26 ; + END + END A_BIST_DIN[0] + PIN A_BM[31] + DIRECTION INPUT ; + USE SIGNAL ; + ANTENNAPARTIALMETALAREA 1.7264 LAYER Metal2 ; + ANTENNAMODEL OXIDE1 ; + ANTENNAGATEAREA 0.20085 LAYER Metal2 ; + ANTENNAMAXAREACAR 9.501618 LAYER Metal2 ; + PORT + LAYER Metal2 ; + RECT 682.02 0 682.28 0.26 ; + END + END A_BM[31] + PIN A_BM[0] + DIRECTION INPUT ; + USE SIGNAL ; + ANTENNAPARTIALMETALAREA 1.7264 LAYER Metal2 ; + ANTENNAMODEL OXIDE1 ; + ANTENNAGATEAREA 0.20085 LAYER Metal2 ; + ANTENNAMAXAREACAR 9.501618 LAYER Metal2 ; + PORT + LAYER Metal2 ; + RECT 3.21 0 3.47 0.26 ; + END + END A_BM[0] + PIN A_BIST_BM[31] + DIRECTION INPUT ; + USE SIGNAL ; + ANTENNAPARTIALMETALAREA 1.7602 LAYER Metal2 ; + ANTENNAMODEL OXIDE1 ; + ANTENNAGATEAREA 0.20085 LAYER Metal2 ; + ANTENNAMAXAREACAR 9.678367 LAYER Metal2 ; + PORT + LAYER Metal2 ; + RECT 680.645 0 680.905 0.26 ; + END + END A_BIST_BM[31] + PIN A_BIST_BM[0] + DIRECTION INPUT ; + USE SIGNAL ; + ANTENNAPARTIALMETALAREA 1.7602 LAYER Metal2 ; + ANTENNAMODEL OXIDE1 ; + ANTENNAGATEAREA 0.20085 LAYER Metal2 ; + ANTENNAMAXAREACAR 9.678367 LAYER Metal2 ; + PORT + LAYER Metal2 ; + RECT 4.585 0 4.845 0.26 ; + END + END A_BIST_BM[0] + PIN A_DOUT[31] + DIRECTION OUTPUT ; + USE SIGNAL ; + ANTENNAPARTIALMETALAREA 4.8256 LAYER Metal2 ; + ANTENNADIFFAREA 0.988 LAYER Metal2 ; + PORT + LAYER Metal2 ; + RECT 666.21 0 666.47 0.26 ; + END + END A_DOUT[31] + PIN A_DOUT[0] + DIRECTION OUTPUT ; + USE SIGNAL ; + ANTENNAPARTIALMETALAREA 4.8256 LAYER Metal2 ; + ANTENNADIFFAREA 0.988 LAYER Metal2 ; + PORT + LAYER Metal2 ; + RECT 19.02 0 19.28 0.26 ; + END + END A_DOUT[0] + PIN B_DIN[31] + DIRECTION INPUT ; + USE SIGNAL ; + ANTENNAPARTIALMETALAREA 2.925 LAYER Metal2 ; + ANTENNAMODEL OXIDE1 ; + ANTENNAGATEAREA 0.20085 LAYER Metal2 ; + ANTENNAMAXAREACAR 15.469256 LAYER Metal2 ; + PORT + LAYER Metal2 ; + RECT 675.9 0 676.16 0.26 ; + END + END B_DIN[31] + PIN B_DIN[0] + DIRECTION INPUT ; + USE SIGNAL ; + ANTENNAPARTIALMETALAREA 2.925 LAYER Metal2 ; + ANTENNAMODEL OXIDE1 ; + ANTENNAGATEAREA 0.20085 LAYER Metal2 ; + ANTENNAMAXAREACAR 15.469256 LAYER Metal2 ; + PORT + LAYER Metal2 ; + RECT 9.33 0 9.59 0.26 ; + END + END B_DIN[0] + PIN B_BIST_DIN[31] + DIRECTION INPUT ; + USE SIGNAL ; + ANTENNAPARTIALMETALAREA 2.9445 LAYER Metal2 ; + ANTENNAMODEL OXIDE1 ; + ANTENNAGATEAREA 0.20085 LAYER Metal2 ; + ANTENNAMAXAREACAR 15.929052 LAYER Metal2 ; + PORT + LAYER Metal2 ; + RECT 674.37 0 674.63 0.26 ; + END + END B_BIST_DIN[31] + PIN B_BIST_DIN[0] + DIRECTION INPUT ; + USE SIGNAL ; + ANTENNAPARTIALMETALAREA 2.9445 LAYER Metal2 ; + ANTENNAMODEL OXIDE1 ; + ANTENNAGATEAREA 0.20085 LAYER Metal2 ; + ANTENNAMAXAREACAR 15.929052 LAYER Metal2 ; + PORT + LAYER Metal2 ; + RECT 10.86 0 11.12 0.26 ; + END + END B_BIST_DIN[0] + PIN B_BM[31] + DIRECTION INPUT ; + USE SIGNAL ; + ANTENNAPARTIALMETALAREA 0.7007 LAYER Metal2 ; + ANTENNAMODEL OXIDE1 ; + ANTENNAGATEAREA 0.20085 LAYER Metal2 ; + ANTENNAMAXAREACAR 4.394822 LAYER Metal2 ; + PORT + LAYER Metal2 ; + RECT 667.385 0 667.645 0.26 ; + END + END B_BM[31] + PIN B_BM[0] + DIRECTION INPUT ; + USE SIGNAL ; + ANTENNAPARTIALMETALAREA 0.7007 LAYER Metal2 ; + ANTENNAMODEL OXIDE1 ; + ANTENNAGATEAREA 0.20085 LAYER Metal2 ; + ANTENNAMAXAREACAR 4.394822 LAYER Metal2 ; + PORT + LAYER Metal2 ; + RECT 17.845 0 18.105 0.26 ; + END + END B_BM[0] + PIN B_BIST_BM[31] + DIRECTION INPUT ; + USE SIGNAL ; + ANTENNAPARTIALMETALAREA 0.7007 LAYER Metal2 ; + ANTENNAMODEL OXIDE1 ; + ANTENNAGATEAREA 0.20085 LAYER Metal2 ; + ANTENNAMAXAREACAR 4.394822 LAYER Metal2 ; + PORT + LAYER Metal2 ; + RECT 668.915 0 669.175 0.26 ; + END + END B_BIST_BM[31] + PIN B_BIST_BM[0] + DIRECTION INPUT ; + USE SIGNAL ; + ANTENNAPARTIALMETALAREA 0.7007 LAYER Metal2 ; + ANTENNAMODEL OXIDE1 ; + ANTENNAGATEAREA 0.20085 LAYER Metal2 ; + ANTENNAMAXAREACAR 4.394822 LAYER Metal2 ; + PORT + LAYER Metal2 ; + RECT 16.315 0 16.575 0.26 ; + END + END B_BIST_BM[0] + PIN B_DOUT[31] + DIRECTION OUTPUT ; + USE SIGNAL ; + ANTENNAPARTIALMETALAREA 4.836 LAYER Metal2 ; + ANTENNADIFFAREA 0.988 LAYER Metal2 ; + PORT + LAYER Metal2 ; + RECT 683.04 0 683.3 0.26 ; + END + END B_DOUT[31] + PIN B_DOUT[0] + DIRECTION OUTPUT ; + USE SIGNAL ; + ANTENNAPARTIALMETALAREA 4.836 LAYER Metal2 ; + ANTENNADIFFAREA 0.988 LAYER Metal2 ; + PORT + LAYER Metal2 ; + RECT 2.19 0 2.45 0.26 ; + END + END B_DOUT[0] + PIN A_ADDR[0] + DIRECTION INPUT ; + USE SIGNAL ; + ANTENNAPARTIALMETALAREA 8.7685 LAYER Metal2 ; + ANTENNAMODEL OXIDE1 ; + ANTENNAGATEAREA 0.20085 LAYER Metal2 ; + ANTENNAMAXAREACAR 44.563107 LAYER Metal2 ; + PORT + LAYER Metal2 ; + RECT 358.835 0 359.095 0.26 ; + END + END A_ADDR[0] + PIN A_BIST_ADDR[0] + DIRECTION INPUT ; + USE SIGNAL ; + ANTENNAPARTIALMETALAREA 9.8293 LAYER Metal2 ; + ANTENNAMODEL OXIDE1 ; + ANTENNAGATEAREA 0.20085 LAYER Metal2 ; + ANTENNAMAXAREACAR 49.84466 LAYER Metal2 ; + PORT + LAYER Metal2 ; + RECT 364.445 0 364.705 0.26 ; + END + END A_BIST_ADDR[0] + PIN B_ADDR[0] + DIRECTION INPUT ; + USE SIGNAL ; + ANTENNAPARTIALMETALAREA 8.7685 LAYER Metal2 ; + ANTENNAMODEL OXIDE1 ; + ANTENNAGATEAREA 0.20085 LAYER Metal2 ; + ANTENNAMAXAREACAR 44.563107 LAYER Metal2 ; + PORT + LAYER Metal2 ; + RECT 326.395 0 326.655 0.26 ; + END + END B_ADDR[0] + PIN B_BIST_ADDR[0] + DIRECTION INPUT ; + USE SIGNAL ; + ANTENNAPARTIALMETALAREA 9.8293 LAYER Metal2 ; + ANTENNAMODEL OXIDE1 ; + ANTENNAGATEAREA 0.20085 LAYER Metal2 ; + ANTENNAMAXAREACAR 49.84466 LAYER Metal2 ; + PORT + LAYER Metal2 ; + RECT 320.785 0 321.045 0.26 ; + END + END B_BIST_ADDR[0] + PIN A_ADDR[1] + DIRECTION INPUT ; + USE SIGNAL ; + ANTENNAPARTIALMETALAREA 11.0851 LAYER Metal2 ; + ANTENNAMODEL OXIDE1 ; + ANTENNAGATEAREA 0.20085 LAYER Metal2 ; + ANTENNAMAXAREACAR 56.097087 LAYER Metal2 ; + PORT + LAYER Metal2 ; + RECT 359.345 0 359.605 0.26 ; + END + END A_ADDR[1] + PIN A_BIST_ADDR[1] + DIRECTION INPUT ; + USE SIGNAL ; + ANTENNAPARTIALMETALAREA 12.1459 LAYER Metal2 ; + ANTENNAMODEL OXIDE1 ; + ANTENNAGATEAREA 0.20085 LAYER Metal2 ; + ANTENNAMAXAREACAR 61.378641 LAYER Metal2 ; + PORT + LAYER Metal2 ; + RECT 364.955 0 365.215 0.26 ; + END + END A_BIST_ADDR[1] + PIN B_ADDR[1] + DIRECTION INPUT ; + USE SIGNAL ; + ANTENNAPARTIALMETALAREA 11.0851 LAYER Metal2 ; + ANTENNAMODEL OXIDE1 ; + ANTENNAGATEAREA 0.20085 LAYER Metal2 ; + ANTENNAMAXAREACAR 56.097087 LAYER Metal2 ; + PORT + LAYER Metal2 ; + RECT 325.885 0 326.145 0.26 ; + END + END B_ADDR[1] + PIN B_BIST_ADDR[1] + DIRECTION INPUT ; + USE SIGNAL ; + ANTENNAPARTIALMETALAREA 12.1459 LAYER Metal2 ; + ANTENNAMODEL OXIDE1 ; + ANTENNAGATEAREA 0.20085 LAYER Metal2 ; + ANTENNAMAXAREACAR 61.378641 LAYER Metal2 ; + PORT + LAYER Metal2 ; + RECT 320.275 0 320.535 0.26 ; + END + END B_BIST_ADDR[1] + PIN A_ADDR[2] + DIRECTION INPUT ; + USE SIGNAL ; + ANTENNAPARTIALMETALAREA 13.0819 LAYER Metal2 ; + ANTENNAPARTIALMETALAREA 1.5246 LAYER Metal3 ; + ANTENNAPARTIALCUTAREA 0.0722 LAYER Via2 ; + ANTENNAMODEL OXIDE1 ; + ANTENNAGATEAREA 0.20085 LAYER Metal3 ; + ANTENNAMAXAREACAR 9.415982 LAYER Metal3 ; + PORT + LAYER Metal2 ; + RECT 368.015 0 368.275 0.26 ; + END + END A_ADDR[2] + PIN A_BIST_ADDR[2] + DIRECTION INPUT ; + USE SIGNAL ; + ANTENNAPARTIALMETALAREA 13.0819 LAYER Metal2 ; + ANTENNAPARTIALMETALAREA 1.0962 LAYER Metal3 ; + ANTENNAPARTIALCUTAREA 0.0722 LAYER Via2 ; + ANTENNAMODEL OXIDE1 ; + ANTENNAGATEAREA 0.20085 LAYER Metal3 ; + ANTENNAMAXAREACAR 7.813791 LAYER Metal3 ; + PORT + LAYER Metal2 ; + RECT 368.525 0 368.785 0.26 ; + END + END A_BIST_ADDR[2] + PIN B_ADDR[2] + DIRECTION INPUT ; + USE SIGNAL ; + ANTENNAPARTIALMETALAREA 13.0819 LAYER Metal2 ; + ANTENNAPARTIALMETALAREA 1.5246 LAYER Metal3 ; + ANTENNAPARTIALCUTAREA 0.0722 LAYER Via2 ; + ANTENNAMODEL OXIDE1 ; + ANTENNAGATEAREA 0.20085 LAYER Metal3 ; + ANTENNAMAXAREACAR 9.415982 LAYER Metal3 ; + PORT + LAYER Metal2 ; + RECT 317.215 0 317.475 0.26 ; + END + END B_ADDR[2] + PIN B_BIST_ADDR[2] + DIRECTION INPUT ; + USE SIGNAL ; + ANTENNAPARTIALMETALAREA 13.0819 LAYER Metal2 ; + ANTENNAPARTIALMETALAREA 1.0962 LAYER Metal3 ; + ANTENNAPARTIALCUTAREA 0.0722 LAYER Via2 ; + ANTENNAMODEL OXIDE1 ; + ANTENNAGATEAREA 0.20085 LAYER Metal3 ; + ANTENNAMAXAREACAR 7.813791 LAYER Metal3 ; + PORT + LAYER Metal2 ; + RECT 316.705 0 316.965 0.26 ; + END + END B_BIST_ADDR[2] + PIN A_ADDR[3] + DIRECTION INPUT ; + USE SIGNAL ; + ANTENNAPARTIALMETALAREA 13.0819 LAYER Metal2 ; + ANTENNAPARTIALMETALAREA 3.9459 LAYER Metal3 ; + ANTENNAPARTIALCUTAREA 0.0722 LAYER Via2 ; + ANTENNAMODEL OXIDE1 ; + ANTENNAGATEAREA 0.20085 LAYER Metal3 ; + ANTENNAMAXAREACAR 21.471247 LAYER Metal3 ; + PORT + LAYER Metal2 ; + RECT 366.995 0 367.255 0.26 ; + END + END A_ADDR[3] + PIN A_BIST_ADDR[3] + DIRECTION INPUT ; + USE SIGNAL ; + ANTENNAPARTIALMETALAREA 13.0819 LAYER Metal2 ; + ANTENNAPARTIALMETALAREA 3.7317 LAYER Metal3 ; + ANTENNAPARTIALCUTAREA 0.0722 LAYER Via2 ; + ANTENNAMODEL OXIDE1 ; + ANTENNAGATEAREA 0.20085 LAYER Metal3 ; + ANTENNAMAXAREACAR 20.935524 LAYER Metal3 ; + PORT + LAYER Metal2 ; + RECT 367.505 0 367.765 0.26 ; + END + END A_BIST_ADDR[3] + PIN B_ADDR[3] + DIRECTION INPUT ; + USE SIGNAL ; + ANTENNAPARTIALMETALAREA 13.0819 LAYER Metal2 ; + ANTENNAPARTIALMETALAREA 3.9459 LAYER Metal3 ; + ANTENNAPARTIALCUTAREA 0.0722 LAYER Via2 ; + ANTENNAMODEL OXIDE1 ; + ANTENNAGATEAREA 0.20085 LAYER Metal3 ; + ANTENNAMAXAREACAR 21.471247 LAYER Metal3 ; + PORT + LAYER Metal2 ; + RECT 318.235 0 318.495 0.26 ; + END + END B_ADDR[3] + PIN B_BIST_ADDR[3] + DIRECTION INPUT ; + USE SIGNAL ; + ANTENNAPARTIALMETALAREA 13.0819 LAYER Metal2 ; + ANTENNAPARTIALMETALAREA 3.7317 LAYER Metal3 ; + ANTENNAPARTIALCUTAREA 0.0722 LAYER Via2 ; + ANTENNAMODEL OXIDE1 ; + ANTENNAGATEAREA 0.20085 LAYER Metal3 ; + ANTENNAMAXAREACAR 20.935524 LAYER Metal3 ; + PORT + LAYER Metal2 ; + RECT 317.725 0 317.985 0.26 ; + END + END B_BIST_ADDR[3] + PIN A_ADDR[4] + DIRECTION INPUT ; + USE SIGNAL ; + ANTENNAPARTIALMETALAREA 14.7329 LAYER Metal2 ; + ANTENNAMODEL OXIDE1 ; + ANTENNAGATEAREA 0.20085 LAYER Metal2 ; + ANTENNAMAXAREACAR 74.2589 LAYER Metal2 ; + PORT + LAYER Metal2 ; + RECT 347.615 0 347.875 0.26 ; + END + END A_ADDR[4] + PIN A_BIST_ADDR[4] + DIRECTION INPUT ; + USE SIGNAL ; + ANTENNAPARTIALMETALAREA 14.4677 LAYER Metal2 ; + ANTENNAMODEL OXIDE1 ; + ANTENNAGATEAREA 0.20085 LAYER Metal2 ; + ANTENNAMAXAREACAR 72.938511 LAYER Metal2 ; + PORT + LAYER Metal2 ; + RECT 348.125 0 348.385 0.26 ; + END + END A_BIST_ADDR[4] + PIN B_ADDR[4] + DIRECTION INPUT ; + USE SIGNAL ; + ANTENNAPARTIALMETALAREA 14.7329 LAYER Metal2 ; + ANTENNAMODEL OXIDE1 ; + ANTENNAGATEAREA 0.20085 LAYER Metal2 ; + ANTENNAMAXAREACAR 74.2589 LAYER Metal2 ; + PORT + LAYER Metal2 ; + RECT 337.615 0 337.875 0.26 ; + END + END B_ADDR[4] + PIN B_BIST_ADDR[4] + DIRECTION INPUT ; + USE SIGNAL ; + ANTENNAPARTIALMETALAREA 14.4677 LAYER Metal2 ; + ANTENNAMODEL OXIDE1 ; + ANTENNAGATEAREA 0.20085 LAYER Metal2 ; + ANTENNAMAXAREACAR 72.938511 LAYER Metal2 ; + PORT + LAYER Metal2 ; + RECT 337.105 0 337.365 0.26 ; + END + END B_BIST_ADDR[4] + PIN A_ADDR[5] + DIRECTION INPUT ; + USE SIGNAL ; + ANTENNAPARTIALMETALAREA 13.2691 LAYER Metal2 ; + ANTENNAMODEL OXIDE1 ; + ANTENNAGATEAREA 0.20085 LAYER Metal2 ; + ANTENNAMAXAREACAR 66.970874 LAYER Metal2 ; + PORT + LAYER Metal2 ; + RECT 346.595 0 346.855 0.26 ; + END + END A_ADDR[5] + PIN A_BIST_ADDR[5] + DIRECTION INPUT ; + USE SIGNAL ; + ANTENNAPARTIALMETALAREA 12.9937 LAYER Metal2 ; + ANTENNAMODEL OXIDE1 ; + ANTENNAGATEAREA 0.20085 LAYER Metal2 ; + ANTENNAMAXAREACAR 65.599701 LAYER Metal2 ; + PORT + LAYER Metal2 ; + RECT 347.105 0 347.365 0.26 ; + END + END A_BIST_ADDR[5] + PIN B_ADDR[5] + DIRECTION INPUT ; + USE SIGNAL ; + ANTENNAPARTIALMETALAREA 13.2691 LAYER Metal2 ; + ANTENNAMODEL OXIDE1 ; + ANTENNAGATEAREA 0.20085 LAYER Metal2 ; + ANTENNAMAXAREACAR 66.970874 LAYER Metal2 ; + PORT + LAYER Metal2 ; + RECT 338.635 0 338.895 0.26 ; + END + END B_ADDR[5] + PIN B_BIST_ADDR[5] + DIRECTION INPUT ; + USE SIGNAL ; + ANTENNAPARTIALMETALAREA 12.9937 LAYER Metal2 ; + ANTENNAMODEL OXIDE1 ; + ANTENNAGATEAREA 0.20085 LAYER Metal2 ; + ANTENNAMAXAREACAR 65.599701 LAYER Metal2 ; + PORT + LAYER Metal2 ; + RECT 338.125 0 338.385 0.26 ; + END + END B_BIST_ADDR[5] + PIN A_ADDR[6] + DIRECTION INPUT ; + USE SIGNAL ; + ANTENNAPARTIALMETALAREA 14.3819 LAYER Metal2 ; + ANTENNAMODEL OXIDE1 ; + ANTENNAGATEAREA 0.20085 LAYER Metal2 ; + ANTENNAMAXAREACAR 72.511327 LAYER Metal2 ; + PORT + LAYER Metal2 ; + RECT 370.565 0 370.825 0.26 ; + END + END A_ADDR[6] + PIN A_BIST_ADDR[6] + DIRECTION INPUT ; + USE SIGNAL ; + ANTENNAPARTIALMETALAREA 14.1167 LAYER Metal2 ; + ANTENNAMODEL OXIDE1 ; + ANTENNAGATEAREA 0.20085 LAYER Metal2 ; + ANTENNAMAXAREACAR 71.190939 LAYER Metal2 ; + PORT + LAYER Metal2 ; + RECT 370.055 0 370.315 0.26 ; + END + END A_BIST_ADDR[6] + PIN B_ADDR[6] + DIRECTION INPUT ; + USE SIGNAL ; + ANTENNAPARTIALMETALAREA 14.3819 LAYER Metal2 ; + ANTENNAMODEL OXIDE1 ; + ANTENNAGATEAREA 0.20085 LAYER Metal2 ; + ANTENNAMAXAREACAR 72.511327 LAYER Metal2 ; + PORT + LAYER Metal2 ; + RECT 314.665 0 314.925 0.26 ; + END + END B_ADDR[6] + PIN B_BIST_ADDR[6] + DIRECTION INPUT ; + USE SIGNAL ; + ANTENNAPARTIALMETALAREA 14.1167 LAYER Metal2 ; + ANTENNAMODEL OXIDE1 ; + ANTENNAGATEAREA 0.20085 LAYER Metal2 ; + ANTENNAMAXAREACAR 71.190939 LAYER Metal2 ; + PORT + LAYER Metal2 ; + RECT 315.175 0 315.435 0.26 ; + END + END B_BIST_ADDR[6] + PIN A_ADDR[7] + DIRECTION INPUT ; + USE SIGNAL ; + ANTENNAPARTIALMETALAREA 16.3761 LAYER Metal2 ; + ANTENNAMODEL OXIDE1 ; + ANTENNAGATEAREA 0.20085 LAYER Metal2 ; + ANTENNAMAXAREACAR 82.440129 LAYER Metal2 ; + PORT + LAYER Metal2 ; + RECT 369.545 0 369.805 0.26 ; + END + END A_ADDR[7] + PIN A_BIST_ADDR[7] + DIRECTION INPUT ; + USE SIGNAL ; + ANTENNAPARTIALMETALAREA 16.1109 LAYER Metal2 ; + ANTENNAMODEL OXIDE1 ; + ANTENNAGATEAREA 0.20085 LAYER Metal2 ; + ANTENNAMAXAREACAR 81.119741 LAYER Metal2 ; + PORT + LAYER Metal2 ; + RECT 369.035 0 369.295 0.26 ; + END + END A_BIST_ADDR[7] + PIN B_ADDR[7] + DIRECTION INPUT ; + USE SIGNAL ; + ANTENNAPARTIALMETALAREA 16.3761 LAYER Metal2 ; + ANTENNAMODEL OXIDE1 ; + ANTENNAGATEAREA 0.20085 LAYER Metal2 ; + ANTENNAMAXAREACAR 82.440129 LAYER Metal2 ; + PORT + LAYER Metal2 ; + RECT 315.685 0 315.945 0.26 ; + END + END B_ADDR[7] + PIN B_BIST_ADDR[7] + DIRECTION INPUT ; + USE SIGNAL ; + ANTENNAPARTIALMETALAREA 16.1109 LAYER Metal2 ; + ANTENNAMODEL OXIDE1 ; + ANTENNAGATEAREA 0.20085 LAYER Metal2 ; + ANTENNAMAXAREACAR 81.119741 LAYER Metal2 ; + PORT + LAYER Metal2 ; + RECT 316.195 0 316.455 0.26 ; + END + END B_BIST_ADDR[7] + PIN A_ADDR[8] + DIRECTION INPUT ; + USE SIGNAL ; + ANTENNAPARTIALMETALAREA 14.4422 LAYER Metal2 ; + ANTENNAMODEL OXIDE1 ; + ANTENNAGATEAREA 0.20085 LAYER Metal2 ; + ANTENNAMAXAREACAR 72.811551 LAYER Metal2 ; + PORT + LAYER Metal2 ; + RECT 373.115 0 373.375 0.26 ; + END + END A_ADDR[8] + PIN A_BIST_ADDR[8] + DIRECTION INPUT ; + USE SIGNAL ; + ANTENNAPARTIALMETALAREA 14.1872 LAYER Metal2 ; + ANTENNAMODEL OXIDE1 ; + ANTENNAGATEAREA 0.20085 LAYER Metal2 ; + ANTENNAMAXAREACAR 71.541947 LAYER Metal2 ; + PORT + LAYER Metal2 ; + RECT 373.625 0 373.885 0.26 ; + END + END A_BIST_ADDR[8] + PIN B_ADDR[8] + DIRECTION INPUT ; + USE SIGNAL ; + ANTENNAPARTIALMETALAREA 14.4422 LAYER Metal2 ; + ANTENNAMODEL OXIDE1 ; + ANTENNAGATEAREA 0.20085 LAYER Metal2 ; + ANTENNAMAXAREACAR 72.811551 LAYER Metal2 ; + PORT + LAYER Metal2 ; + RECT 312.115 0 312.375 0.26 ; + END + END B_ADDR[8] + PIN B_BIST_ADDR[8] + DIRECTION INPUT ; + USE SIGNAL ; + ANTENNAPARTIALMETALAREA 14.1872 LAYER Metal2 ; + ANTENNAMODEL OXIDE1 ; + ANTENNAGATEAREA 0.20085 LAYER Metal2 ; + ANTENNAMAXAREACAR 71.541947 LAYER Metal2 ; + PORT + LAYER Metal2 ; + RECT 311.605 0 311.865 0.26 ; + END + END B_BIST_ADDR[8] + PIN A_ADDR[9] + DIRECTION INPUT ; + USE SIGNAL ; + ANTENNAPARTIALMETALAREA 13.7995 LAYER Metal2 ; + ANTENNAMODEL OXIDE1 ; + ANTENNAGATEAREA 0.20085 LAYER Metal2 ; + ANTENNAMAXAREACAR 69.61165 LAYER Metal2 ; + PORT + LAYER Metal2 ; + RECT 371.075 0 371.335 0.26 ; + END + END A_ADDR[9] + PIN A_BIST_ADDR[9] + DIRECTION INPUT ; + USE SIGNAL ; + ANTENNAPARTIALMETALAREA 13.7995 LAYER Metal2 ; + ANTENNAMODEL OXIDE1 ; + ANTENNAGATEAREA 0.20085 LAYER Metal2 ; + ANTENNAMAXAREACAR 69.61165 LAYER Metal2 ; + PORT + LAYER Metal2 ; + RECT 371.585 0 371.845 0.26 ; + END + END A_BIST_ADDR[9] + PIN B_ADDR[9] + DIRECTION INPUT ; + USE SIGNAL ; + ANTENNAPARTIALMETALAREA 13.7995 LAYER Metal2 ; + ANTENNAMODEL OXIDE1 ; + ANTENNAGATEAREA 0.20085 LAYER Metal2 ; + ANTENNAMAXAREACAR 69.61165 LAYER Metal2 ; + PORT + LAYER Metal2 ; + RECT 314.155 0 314.415 0.26 ; + END + END B_ADDR[9] + PIN B_BIST_ADDR[9] + DIRECTION INPUT ; + USE SIGNAL ; + ANTENNAPARTIALMETALAREA 13.7995 LAYER Metal2 ; + ANTENNAMODEL OXIDE1 ; + ANTENNAGATEAREA 0.20085 LAYER Metal2 ; + ANTENNAMAXAREACAR 69.61165 LAYER Metal2 ; + PORT + LAYER Metal2 ; + RECT 313.645 0 313.905 0.26 ; + END + END B_BIST_ADDR[9] + PIN A_CLK + DIRECTION INPUT ; + USE SIGNAL ; + ANTENNAPARTIALMETALAREA 4.0547 LAYER Metal2 ; + ANTENNAMODEL OXIDE1 ; + ANTENNAGATEAREA 0.20085 LAYER Metal2 ; + ANTENNAMAXAREACAR 21.093851 LAYER Metal2 ; + PORT + LAYER Metal2 ; + RECT 357.305 0 357.565 0.26 ; + END + END A_CLK + PIN A_REN + DIRECTION INPUT ; + USE SIGNAL ; + ANTENNAPARTIALMETALAREA 3.98465 LAYER Metal2 ; + ANTENNAMODEL OXIDE1 ; + ANTENNAGATEAREA 0.20085 LAYER Metal2 ; + ANTENNAMAXAREACAR 20.745083 LAYER Metal2 ; + PORT + LAYER Metal2 ; + RECT 360.875 0 361.135 0.26 ; + END + END A_REN + PIN A_WEN + DIRECTION INPUT ; + USE SIGNAL ; + ANTENNAPARTIALMETALAREA 2.8847 LAYER Metal2 ; + ANTENNAMODEL OXIDE1 ; + ANTENNAGATEAREA 0.20085 LAYER Metal2 ; + ANTENNAMAXAREACAR 15.268608 LAYER Metal2 ; + PORT + LAYER Metal2 ; + RECT 360.365 0 360.625 0.26 ; + END + END A_WEN + PIN A_MEN + DIRECTION INPUT ; + USE SIGNAL ; + ANTENNAPARTIALMETALAREA 3.0247 LAYER Metal2 ; + ANTENNAMODEL OXIDE1 ; + ANTENNAGATEAREA 0.20085 LAYER Metal2 ; + ANTENNAMAXAREACAR 15.965646 LAYER Metal2 ; + PORT + LAYER Metal2 ; + RECT 357.815 0 358.075 0.26 ; + END + END A_MEN + PIN A_DLY + DIRECTION INPUT ; + USE SIGNAL ; + ANTENNAPARTIALMETALAREA 7.7792 LAYER Metal2 ; + ANTENNAMODEL OXIDE1 ; + ANTENNAGATEAREA 0.3367 LAYER Metal2 ; + ANTENNAMAXAREACAR 23.644788 LAYER Metal2 ; + PORT + LAYER Metal2 ; + RECT 378.215 0 378.475 0.26 ; + END + END A_DLY + PIN B_CLK + DIRECTION INPUT ; + USE SIGNAL ; + ANTENNAPARTIALMETALAREA 4.0547 LAYER Metal2 ; + ANTENNAMODEL OXIDE1 ; + ANTENNAGATEAREA 0.20085 LAYER Metal2 ; + ANTENNAMAXAREACAR 21.093851 LAYER Metal2 ; + PORT + LAYER Metal2 ; + RECT 327.925 0 328.185 0.26 ; + END + END B_CLK + PIN B_REN + DIRECTION INPUT ; + USE SIGNAL ; + ANTENNAPARTIALMETALAREA 3.98465 LAYER Metal2 ; + ANTENNAMODEL OXIDE1 ; + ANTENNAGATEAREA 0.20085 LAYER Metal2 ; + ANTENNAMAXAREACAR 20.745083 LAYER Metal2 ; + PORT + LAYER Metal2 ; + RECT 324.355 0 324.615 0.26 ; + END + END B_REN + PIN B_WEN + DIRECTION INPUT ; + USE SIGNAL ; + ANTENNAPARTIALMETALAREA 2.8847 LAYER Metal2 ; + ANTENNAMODEL OXIDE1 ; + ANTENNAGATEAREA 0.20085 LAYER Metal2 ; + ANTENNAMAXAREACAR 15.268608 LAYER Metal2 ; + PORT + LAYER Metal2 ; + RECT 324.865 0 325.125 0.26 ; + END + END B_WEN + PIN B_MEN + DIRECTION INPUT ; + USE SIGNAL ; + ANTENNAPARTIALMETALAREA 3.0247 LAYER Metal2 ; + ANTENNAMODEL OXIDE1 ; + ANTENNAGATEAREA 0.20085 LAYER Metal2 ; + ANTENNAMAXAREACAR 15.965646 LAYER Metal2 ; + PORT + LAYER Metal2 ; + RECT 327.415 0 327.675 0.26 ; + END + END B_MEN + PIN B_DLY + DIRECTION INPUT ; + USE SIGNAL ; + ANTENNAPARTIALMETALAREA 7.7792 LAYER Metal2 ; + ANTENNAMODEL OXIDE1 ; + ANTENNAGATEAREA 0.3367 LAYER Metal2 ; + ANTENNAMAXAREACAR 23.644788 LAYER Metal2 ; + PORT + LAYER Metal2 ; + RECT 307.015 0 307.275 0.26 ; + END + END B_DLY + PIN A_BIST_EN + DIRECTION INPUT ; + USE SIGNAL ; + ANTENNAPARTIALMETALAREA 4.0634 LAYER Metal2 ; + ANTENNAPARTIALMETALAREA 254.5589 LAYER Metal3 ; + ANTENNAPARTIALCUTAREA 0.0722 LAYER Via2 ; + ANTENNAMODEL OXIDE1 ; + ANTENNAGATEAREA 1.43 LAYER Metal2 ; + ANTENNAGATEAREA 27.885 LAYER Metal3 ; + ANTENNAMAXAREACAR 3.266993 LAYER Metal2 ; + ANTENNAMAXAREACAR 20.300258 LAYER Metal3 ; + ANTENNAMAXCUTCAR 0.151469 LAYER Via2 ; + PORT + LAYER Metal2 ; + RECT 359.855 0 360.115 0.26 ; + END + END A_BIST_EN + PIN A_BIST_CLK + DIRECTION INPUT ; + USE SIGNAL ; + ANTENNAPARTIALMETALAREA 4.1639 LAYER Metal2 ; + ANTENNAMODEL OXIDE1 ; + ANTENNAGATEAREA 0.20085 LAYER Metal2 ; + ANTENNAMAXAREACAR 21.953448 LAYER Metal2 ; + PORT + LAYER Metal2 ; + RECT 355.775 0 356.035 0.26 ; + END + END A_BIST_CLK + PIN A_BIST_REN + DIRECTION INPUT ; + USE SIGNAL ; + ANTENNAPARTIALMETALAREA 4.1119 LAYER Metal2 ; + ANTENNAMODEL OXIDE1 ; + ANTENNAGATEAREA 0.20085 LAYER Metal2 ; + ANTENNAMAXAREACAR 21.694548 LAYER Metal2 ; + PORT + LAYER Metal2 ; + RECT 362.405 0 362.665 0.26 ; + END + END A_BIST_REN + PIN A_BIST_WEN + DIRECTION INPUT ; + USE SIGNAL ; + ANTENNAPARTIALMETALAREA 2.9051 LAYER Metal2 ; + ANTENNAMODEL OXIDE1 ; + ANTENNAGATEAREA 0.20085 LAYER Metal2 ; + ANTENNAMAXAREACAR 15.686084 LAYER Metal2 ; + PORT + LAYER Metal2 ; + RECT 361.895 0 362.155 0.26 ; + END + END A_BIST_WEN + PIN A_BIST_MEN + DIRECTION INPUT ; + USE SIGNAL ; + ANTENNAPARTIALMETALAREA 2.8977 LAYER Metal2 ; + ANTENNAMODEL OXIDE1 ; + ANTENNAGATEAREA 0.20085 LAYER Metal2 ; + ANTENNAMAXAREACAR 15.649241 LAYER Metal2 ; + PORT + LAYER Metal2 ; + RECT 356.285 0 356.545 0.26 ; + END + END A_BIST_MEN + PIN B_BIST_EN + DIRECTION INPUT ; + USE SIGNAL ; + ANTENNAPARTIALMETALAREA 3.9646 LAYER Metal2 ; + ANTENNAPARTIALMETALAREA 254.9981 LAYER Metal3 ; + ANTENNAPARTIALCUTAREA 0.0722 LAYER Via2 ; + ANTENNAMODEL OXIDE1 ; + ANTENNAGATEAREA 1.43 LAYER Metal2 ; + ANTENNAGATEAREA 27.885 LAYER Metal3 ; + ANTENNAMAXAREACAR 3.197902 LAYER Metal2 ; + ANTENNAMAXAREACAR 20.316009 LAYER Metal3 ; + ANTENNAMAXCUTCAR 0.151469 LAYER Via2 ; + PORT + LAYER Metal2 ; + RECT 325.375 0 325.635 0.26 ; + END + END B_BIST_EN + PIN B_BIST_CLK + DIRECTION INPUT ; + USE SIGNAL ; + ANTENNAPARTIALMETALAREA 4.1639 LAYER Metal2 ; + ANTENNAMODEL OXIDE1 ; + ANTENNAGATEAREA 0.20085 LAYER Metal2 ; + ANTENNAMAXAREACAR 21.953448 LAYER Metal2 ; + PORT + LAYER Metal2 ; + RECT 329.455 0 329.715 0.26 ; + END + END B_BIST_CLK + PIN B_BIST_REN + DIRECTION INPUT ; + USE SIGNAL ; + ANTENNAPARTIALMETALAREA 4.1119 LAYER Metal2 ; + ANTENNAMODEL OXIDE1 ; + ANTENNAGATEAREA 0.20085 LAYER Metal2 ; + ANTENNAMAXAREACAR 21.694548 LAYER Metal2 ; + PORT + LAYER Metal2 ; + RECT 322.825 0 323.085 0.26 ; + END + END B_BIST_REN + PIN B_BIST_WEN + DIRECTION INPUT ; + USE SIGNAL ; + ANTENNAPARTIALMETALAREA 2.9051 LAYER Metal2 ; + ANTENNAMODEL OXIDE1 ; + ANTENNAGATEAREA 0.20085 LAYER Metal2 ; + ANTENNAMAXAREACAR 15.686084 LAYER Metal2 ; + PORT + LAYER Metal2 ; + RECT 323.335 0 323.595 0.26 ; + END + END B_BIST_WEN + PIN B_BIST_MEN + DIRECTION INPUT ; + USE SIGNAL ; + ANTENNAPARTIALMETALAREA 2.8977 LAYER Metal2 ; + ANTENNAMODEL OXIDE1 ; + ANTENNAGATEAREA 0.20085 LAYER Metal2 ; + ANTENNAMAXAREACAR 15.649241 LAYER Metal2 ; + PORT + LAYER Metal2 ; + RECT 328.945 0 329.205 0.26 ; + END + END B_BIST_MEN + OBS + LAYER Metal1 ; + RECT 0 0 685.49 385.37 ; + LAYER Metal2 ; + RECT 0.31 53.41 0.51 385.34 ; + RECT 1.135 384.61 1.335 385.34 ; + RECT 1.545 384.61 1.905 385.34 ; + RECT 2.115 384.61 2.315 385.34 ; + RECT 2.19 0.52 2.45 7.78 ; + RECT 2.7 0.3 2.96 5.235 ; + RECT 2.77 384.61 2.97 385.34 ; + RECT 3.21 0.52 3.47 5.57 ; + RECT 3.18 384.61 3.54 385.34 ; + RECT 3.835 384.61 4.035 385.34 ; + RECT 4.33 384.61 4.69 385.34 ; + RECT 4.585 0.52 4.845 6.28 ; + RECT 4.9 384.61 5.1 385.34 ; + RECT 5.555 384.61 5.755 385.34 ; + RECT 5.965 384.61 6.325 385.34 ; + RECT 6.535 384.61 6.735 385.34 ; + RECT 6.27 0.18 7.04 0.88 ; + RECT 7.19 384.61 7.39 385.34 ; + RECT 7.29 0.3 7.55 8.7 ; + RECT 7.6 384.61 7.96 385.34 ; + RECT 8.255 384.61 8.455 385.34 ; + RECT 8.75 384.61 9.11 385.34 ; + RECT 9.84 0.155 10.61 0.445 ; + RECT 9.84 0.155 10.1 8.665 ; + RECT 10.35 0.155 10.61 8.665 ; + RECT 9.32 384.61 9.52 385.34 ; + RECT 9.33 0.52 9.59 9.955 ; + RECT 9.975 384.61 10.175 385.34 ; + RECT 10.385 384.61 10.745 385.34 ; + RECT 10.86 0.52 11.12 11.315 ; + RECT 10.955 384.61 11.155 385.34 ; + RECT 11.37 0.52 11.63 13.45 ; + RECT 11.61 384.61 11.81 385.34 ; + RECT 11.88 0.52 12.14 14.115 ; + RECT 12.02 384.61 12.38 385.34 ; + RECT 12.675 384.61 12.875 385.34 ; + RECT 14.075 0.155 14.845 0.445 ; + RECT 14.075 0.155 14.335 13.21 ; + RECT 14.585 0.155 14.845 13.21 ; + RECT 13.17 384.61 13.53 385.34 ; + RECT 13.74 384.61 13.94 385.34 ; + RECT 15.095 0.18 15.865 0.88 ; + RECT 15.095 0.18 15.355 12.9 ; + RECT 15.605 0.18 15.865 12.9 ; + RECT 14.395 384.61 14.595 385.34 ; + RECT 14.805 384.61 15.165 385.34 ; + RECT 15.375 384.61 15.575 385.34 ; + RECT 16.03 384.61 16.23 385.34 ; + RECT 16.315 0.52 16.575 2.82 ; + RECT 16.44 384.61 16.8 385.34 ; + RECT 17.095 384.61 17.295 385.34 ; + RECT 17.59 384.61 17.95 385.34 ; + RECT 17.845 0.52 18.105 2.82 ; + RECT 18.16 384.61 18.36 385.34 ; + RECT 18.815 384.61 19.015 385.34 ; + RECT 19.02 0.52 19.28 4.315 ; + RECT 19.225 384.61 19.585 385.34 ; + RECT 19.795 384.61 19.995 385.34 ; + RECT 19.87 0.52 20.13 7.78 ; + RECT 20.38 0.3 20.64 5.235 ; + RECT 20.45 384.61 20.65 385.34 ; + RECT 20.89 0.52 21.15 5.57 ; + RECT 20.86 384.61 21.22 385.34 ; + RECT 21.515 384.61 21.715 385.34 ; + RECT 22.01 384.61 22.37 385.34 ; + RECT 22.265 0.52 22.525 6.28 ; + RECT 22.58 384.61 22.78 385.34 ; + RECT 23.235 384.61 23.435 385.34 ; + RECT 23.645 384.61 24.005 385.34 ; + RECT 24.215 384.61 24.415 385.34 ; + RECT 23.95 0.18 24.72 0.88 ; + RECT 24.87 384.61 25.07 385.34 ; + RECT 24.97 0.3 25.23 8.7 ; + RECT 25.28 384.61 25.64 385.34 ; + RECT 25.935 384.61 26.135 385.34 ; + RECT 26.43 384.61 26.79 385.34 ; + RECT 27.52 0.155 28.29 0.445 ; + RECT 27.52 0.155 27.78 8.665 ; + RECT 28.03 0.155 28.29 8.665 ; + RECT 27 384.61 27.2 385.34 ; + RECT 27.01 0.52 27.27 9.955 ; + RECT 27.655 384.61 27.855 385.34 ; + RECT 28.065 384.61 28.425 385.34 ; + RECT 28.54 0.52 28.8 11.315 ; + RECT 28.635 384.61 28.835 385.34 ; + RECT 29.05 0.52 29.31 13.45 ; + RECT 29.29 384.61 29.49 385.34 ; + RECT 29.56 0.52 29.82 14.115 ; + RECT 29.7 384.61 30.06 385.34 ; + RECT 30.355 384.61 30.555 385.34 ; + RECT 31.755 0.155 32.525 0.445 ; + RECT 31.755 0.155 32.015 13.21 ; + RECT 32.265 0.155 32.525 13.21 ; + RECT 30.85 384.61 31.21 385.34 ; + RECT 31.42 384.61 31.62 385.34 ; + RECT 32.775 0.18 33.545 0.88 ; + RECT 32.775 0.18 33.035 12.9 ; + RECT 33.285 0.18 33.545 12.9 ; + RECT 32.075 384.61 32.275 385.34 ; + RECT 32.485 384.61 32.845 385.34 ; + RECT 33.055 384.61 33.255 385.34 ; + RECT 33.71 384.61 33.91 385.34 ; + RECT 33.995 0.52 34.255 2.82 ; + RECT 34.12 384.61 34.48 385.34 ; + RECT 34.775 384.61 34.975 385.34 ; + RECT 35.27 384.61 35.63 385.34 ; + RECT 35.525 0.52 35.785 2.82 ; + RECT 35.84 384.61 36.04 385.34 ; + RECT 36.495 384.61 36.695 385.34 ; + RECT 36.7 0.52 36.96 4.315 ; + RECT 36.905 384.61 37.265 385.34 ; + RECT 37.475 384.61 37.675 385.34 ; + RECT 37.55 0.52 37.81 7.78 ; + RECT 38.06 0.3 38.32 5.235 ; + RECT 38.13 384.61 38.33 385.34 ; + RECT 38.57 0.52 38.83 5.57 ; + RECT 38.54 384.61 38.9 385.34 ; + RECT 39.195 384.61 39.395 385.34 ; + RECT 39.69 384.61 40.05 385.34 ; + RECT 39.945 0.52 40.205 6.28 ; + RECT 40.26 384.61 40.46 385.34 ; + RECT 40.915 384.61 41.115 385.34 ; + RECT 41.325 384.61 41.685 385.34 ; + RECT 41.895 384.61 42.095 385.34 ; + RECT 41.63 0.18 42.4 0.88 ; + RECT 42.55 384.61 42.75 385.34 ; + RECT 42.65 0.3 42.91 8.7 ; + RECT 42.96 384.61 43.32 385.34 ; + RECT 43.615 384.61 43.815 385.34 ; + RECT 44.11 384.61 44.47 385.34 ; + RECT 45.2 0.155 45.97 0.445 ; + RECT 45.2 0.155 45.46 8.665 ; + RECT 45.71 0.155 45.97 8.665 ; + RECT 44.68 384.61 44.88 385.34 ; + RECT 44.69 0.52 44.95 9.955 ; + RECT 45.335 384.61 45.535 385.34 ; + RECT 45.745 384.61 46.105 385.34 ; + RECT 46.22 0.52 46.48 11.315 ; + RECT 46.315 384.61 46.515 385.34 ; + RECT 46.73 0.52 46.99 13.45 ; + RECT 46.97 384.61 47.17 385.34 ; + RECT 47.24 0.52 47.5 14.115 ; + RECT 47.38 384.61 47.74 385.34 ; + RECT 48.035 384.61 48.235 385.34 ; + RECT 49.435 0.155 50.205 0.445 ; + RECT 49.435 0.155 49.695 13.21 ; + RECT 49.945 0.155 50.205 13.21 ; + RECT 48.53 384.61 48.89 385.34 ; + RECT 49.1 384.61 49.3 385.34 ; + RECT 50.455 0.18 51.225 0.88 ; + RECT 50.455 0.18 50.715 12.9 ; + RECT 50.965 0.18 51.225 12.9 ; + RECT 49.755 384.61 49.955 385.34 ; + RECT 50.165 384.61 50.525 385.34 ; + RECT 50.735 384.61 50.935 385.34 ; + RECT 51.39 384.61 51.59 385.34 ; + RECT 51.675 0.52 51.935 2.82 ; + RECT 51.8 384.61 52.16 385.34 ; + RECT 52.455 384.61 52.655 385.34 ; + RECT 52.95 384.61 53.31 385.34 ; + RECT 53.205 0.52 53.465 2.82 ; + RECT 53.52 384.61 53.72 385.34 ; + RECT 54.175 384.61 54.375 385.34 ; + RECT 54.38 0.52 54.64 4.315 ; + RECT 54.585 384.61 54.945 385.34 ; + RECT 55.155 384.61 55.355 385.34 ; + RECT 55.23 0.52 55.49 7.78 ; + RECT 55.74 0.3 56 5.235 ; + RECT 55.81 384.61 56.01 385.34 ; + RECT 56.25 0.52 56.51 5.57 ; + RECT 56.22 384.61 56.58 385.34 ; + RECT 56.875 384.61 57.075 385.34 ; + RECT 57.37 384.61 57.73 385.34 ; + RECT 57.625 0.52 57.885 6.28 ; + RECT 57.94 384.61 58.14 385.34 ; + RECT 58.595 384.61 58.795 385.34 ; + RECT 59.005 384.61 59.365 385.34 ; + RECT 59.575 384.61 59.775 385.34 ; + RECT 59.31 0.18 60.08 0.88 ; + RECT 60.23 384.61 60.43 385.34 ; + RECT 60.33 0.3 60.59 8.7 ; + RECT 60.64 384.61 61 385.34 ; + RECT 61.295 384.61 61.495 385.34 ; + RECT 61.79 384.61 62.15 385.34 ; + RECT 62.88 0.155 63.65 0.445 ; + RECT 62.88 0.155 63.14 8.665 ; + RECT 63.39 0.155 63.65 8.665 ; + RECT 62.36 384.61 62.56 385.34 ; + RECT 62.37 0.52 62.63 9.955 ; + RECT 63.015 384.61 63.215 385.34 ; + RECT 63.425 384.61 63.785 385.34 ; + RECT 63.9 0.52 64.16 11.315 ; + RECT 63.995 384.61 64.195 385.34 ; + RECT 64.41 0.52 64.67 13.45 ; + RECT 64.65 384.61 64.85 385.34 ; + RECT 64.92 0.52 65.18 14.115 ; + RECT 65.06 384.61 65.42 385.34 ; + RECT 65.715 384.61 65.915 385.34 ; + RECT 67.115 0.155 67.885 0.445 ; + RECT 67.115 0.155 67.375 13.21 ; + RECT 67.625 0.155 67.885 13.21 ; + RECT 66.21 384.61 66.57 385.34 ; + RECT 66.78 384.61 66.98 385.34 ; + RECT 68.135 0.18 68.905 0.88 ; + RECT 68.135 0.18 68.395 12.9 ; + RECT 68.645 0.18 68.905 12.9 ; + RECT 67.435 384.61 67.635 385.34 ; + RECT 67.845 384.61 68.205 385.34 ; + RECT 68.415 384.61 68.615 385.34 ; + RECT 69.07 384.61 69.27 385.34 ; + RECT 69.355 0.52 69.615 2.82 ; + RECT 69.48 384.61 69.84 385.34 ; + RECT 70.135 384.61 70.335 385.34 ; + RECT 70.63 384.61 70.99 385.34 ; + RECT 70.885 0.52 71.145 2.82 ; + RECT 71.2 384.61 71.4 385.34 ; + RECT 71.855 384.61 72.055 385.34 ; + RECT 72.06 0.52 72.32 4.315 ; + RECT 72.265 384.61 72.625 385.34 ; + RECT 72.835 384.61 73.035 385.34 ; + RECT 72.91 0.52 73.17 7.78 ; + RECT 73.42 0.3 73.68 5.235 ; + RECT 73.49 384.61 73.69 385.34 ; + RECT 73.93 0.52 74.19 5.57 ; + RECT 73.9 384.61 74.26 385.34 ; + RECT 74.555 384.61 74.755 385.34 ; + RECT 75.05 384.61 75.41 385.34 ; + RECT 75.305 0.52 75.565 6.28 ; + RECT 75.62 384.61 75.82 385.34 ; + RECT 76.275 384.61 76.475 385.34 ; + RECT 76.685 384.61 77.045 385.34 ; + RECT 77.255 384.61 77.455 385.34 ; + RECT 76.99 0.18 77.76 0.88 ; + RECT 77.91 384.61 78.11 385.34 ; + RECT 78.01 0.3 78.27 8.7 ; + RECT 78.32 384.61 78.68 385.34 ; + RECT 78.975 384.61 79.175 385.34 ; + RECT 79.47 384.61 79.83 385.34 ; + RECT 80.56 0.155 81.33 0.445 ; + RECT 80.56 0.155 80.82 8.665 ; + RECT 81.07 0.155 81.33 8.665 ; + RECT 80.04 384.61 80.24 385.34 ; + RECT 80.05 0.52 80.31 9.955 ; + RECT 80.695 384.61 80.895 385.34 ; + RECT 81.105 384.61 81.465 385.34 ; + RECT 81.58 0.52 81.84 11.315 ; + RECT 81.675 384.61 81.875 385.34 ; + RECT 82.09 0.52 82.35 13.45 ; + RECT 82.33 384.61 82.53 385.34 ; + RECT 82.6 0.52 82.86 14.115 ; + RECT 82.74 384.61 83.1 385.34 ; + RECT 83.395 384.61 83.595 385.34 ; + RECT 84.795 0.155 85.565 0.445 ; + RECT 84.795 0.155 85.055 13.21 ; + RECT 85.305 0.155 85.565 13.21 ; + RECT 83.89 384.61 84.25 385.34 ; + RECT 84.46 384.61 84.66 385.34 ; + RECT 85.815 0.18 86.585 0.88 ; + RECT 85.815 0.18 86.075 12.9 ; + RECT 86.325 0.18 86.585 12.9 ; + RECT 85.115 384.61 85.315 385.34 ; + RECT 85.525 384.61 85.885 385.34 ; + RECT 86.095 384.61 86.295 385.34 ; + RECT 86.75 384.61 86.95 385.34 ; + RECT 87.035 0.52 87.295 2.82 ; + RECT 87.16 384.61 87.52 385.34 ; + RECT 87.815 384.61 88.015 385.34 ; + RECT 88.31 384.61 88.67 385.34 ; + RECT 88.565 0.52 88.825 2.82 ; + RECT 88.88 384.61 89.08 385.34 ; + RECT 89.535 384.61 89.735 385.34 ; + RECT 89.74 0.52 90 4.315 ; + RECT 89.945 384.61 90.305 385.34 ; + RECT 90.515 384.61 90.715 385.34 ; + RECT 90.59 0.52 90.85 7.78 ; + RECT 91.1 0.3 91.36 5.235 ; + RECT 91.17 384.61 91.37 385.34 ; + RECT 91.61 0.52 91.87 5.57 ; + RECT 91.58 384.61 91.94 385.34 ; + RECT 92.235 384.61 92.435 385.34 ; + RECT 92.73 384.61 93.09 385.34 ; + RECT 92.985 0.52 93.245 6.28 ; + RECT 93.3 384.61 93.5 385.34 ; + RECT 93.955 384.61 94.155 385.34 ; + RECT 94.365 384.61 94.725 385.34 ; + RECT 94.935 384.61 95.135 385.34 ; + RECT 94.67 0.18 95.44 0.88 ; + RECT 95.59 384.61 95.79 385.34 ; + RECT 95.69 0.3 95.95 8.7 ; + RECT 96 384.61 96.36 385.34 ; + RECT 96.655 384.61 96.855 385.34 ; + RECT 97.15 384.61 97.51 385.34 ; + RECT 98.24 0.155 99.01 0.445 ; + RECT 98.24 0.155 98.5 8.665 ; + RECT 98.75 0.155 99.01 8.665 ; + RECT 97.72 384.61 97.92 385.34 ; + RECT 97.73 0.52 97.99 9.955 ; + RECT 98.375 384.61 98.575 385.34 ; + RECT 98.785 384.61 99.145 385.34 ; + RECT 99.26 0.52 99.52 11.315 ; + RECT 99.355 384.61 99.555 385.34 ; + RECT 99.77 0.52 100.03 13.45 ; + RECT 100.01 384.61 100.21 385.34 ; + RECT 100.28 0.52 100.54 14.115 ; + RECT 100.42 384.61 100.78 385.34 ; + RECT 101.075 384.61 101.275 385.34 ; + RECT 102.475 0.155 103.245 0.445 ; + RECT 102.475 0.155 102.735 13.21 ; + RECT 102.985 0.155 103.245 13.21 ; + RECT 101.57 384.61 101.93 385.34 ; + RECT 102.14 384.61 102.34 385.34 ; + RECT 103.495 0.18 104.265 0.88 ; + RECT 103.495 0.18 103.755 12.9 ; + RECT 104.005 0.18 104.265 12.9 ; + RECT 102.795 384.61 102.995 385.34 ; + RECT 103.205 384.61 103.565 385.34 ; + RECT 103.775 384.61 103.975 385.34 ; + RECT 104.43 384.61 104.63 385.34 ; + RECT 104.715 0.52 104.975 2.82 ; + RECT 104.84 384.61 105.2 385.34 ; + RECT 105.495 384.61 105.695 385.34 ; + RECT 105.99 384.61 106.35 385.34 ; + RECT 106.245 0.52 106.505 2.82 ; + RECT 106.56 384.61 106.76 385.34 ; + RECT 107.215 384.61 107.415 385.34 ; + RECT 107.42 0.52 107.68 4.315 ; + RECT 107.625 384.61 107.985 385.34 ; + RECT 108.195 384.61 108.395 385.34 ; + RECT 108.27 0.52 108.53 7.78 ; + RECT 108.78 0.3 109.04 5.235 ; + RECT 108.85 384.61 109.05 385.34 ; + RECT 109.29 0.52 109.55 5.57 ; + RECT 109.26 384.61 109.62 385.34 ; + RECT 109.915 384.61 110.115 385.34 ; + RECT 110.41 384.61 110.77 385.34 ; + RECT 110.665 0.52 110.925 6.28 ; + RECT 110.98 384.61 111.18 385.34 ; + RECT 111.635 384.61 111.835 385.34 ; + RECT 112.045 384.61 112.405 385.34 ; + RECT 112.615 384.61 112.815 385.34 ; + RECT 112.35 0.18 113.12 0.88 ; + RECT 113.27 384.61 113.47 385.34 ; + RECT 113.37 0.3 113.63 8.7 ; + RECT 113.68 384.61 114.04 385.34 ; + RECT 114.335 384.61 114.535 385.34 ; + RECT 114.83 384.61 115.19 385.34 ; + RECT 115.92 0.155 116.69 0.445 ; + RECT 115.92 0.155 116.18 8.665 ; + RECT 116.43 0.155 116.69 8.665 ; + RECT 115.4 384.61 115.6 385.34 ; + RECT 115.41 0.52 115.67 9.955 ; + RECT 116.055 384.61 116.255 385.34 ; + RECT 116.465 384.61 116.825 385.34 ; + RECT 116.94 0.52 117.2 11.315 ; + RECT 117.035 384.61 117.235 385.34 ; + RECT 117.45 0.52 117.71 13.45 ; + RECT 117.69 384.61 117.89 385.34 ; + RECT 117.96 0.52 118.22 14.115 ; + RECT 118.1 384.61 118.46 385.34 ; + RECT 118.755 384.61 118.955 385.34 ; + RECT 120.155 0.155 120.925 0.445 ; + RECT 120.155 0.155 120.415 13.21 ; + RECT 120.665 0.155 120.925 13.21 ; + RECT 119.25 384.61 119.61 385.34 ; + RECT 119.82 384.61 120.02 385.34 ; + RECT 121.175 0.18 121.945 0.88 ; + RECT 121.175 0.18 121.435 12.9 ; + RECT 121.685 0.18 121.945 12.9 ; + RECT 120.475 384.61 120.675 385.34 ; + RECT 120.885 384.61 121.245 385.34 ; + RECT 121.455 384.61 121.655 385.34 ; + RECT 122.11 384.61 122.31 385.34 ; + RECT 122.395 0.52 122.655 2.82 ; + RECT 122.52 384.61 122.88 385.34 ; + RECT 123.175 384.61 123.375 385.34 ; + RECT 123.67 384.61 124.03 385.34 ; + RECT 123.925 0.52 124.185 2.82 ; + RECT 124.24 384.61 124.44 385.34 ; + RECT 124.895 384.61 125.095 385.34 ; + RECT 125.1 0.52 125.36 4.315 ; + RECT 125.305 384.61 125.665 385.34 ; + RECT 125.875 384.61 126.075 385.34 ; + RECT 125.95 0.52 126.21 7.78 ; + RECT 126.46 0.3 126.72 5.235 ; + RECT 126.53 384.61 126.73 385.34 ; + RECT 126.97 0.52 127.23 5.57 ; + RECT 126.94 384.61 127.3 385.34 ; + RECT 127.595 384.61 127.795 385.34 ; + RECT 128.09 384.61 128.45 385.34 ; + RECT 128.345 0.52 128.605 6.28 ; + RECT 128.66 384.61 128.86 385.34 ; + RECT 129.315 384.61 129.515 385.34 ; + RECT 129.725 384.61 130.085 385.34 ; + RECT 130.295 384.61 130.495 385.34 ; + RECT 130.03 0.18 130.8 0.88 ; + RECT 130.95 384.61 131.15 385.34 ; + RECT 131.05 0.3 131.31 8.7 ; + RECT 131.36 384.61 131.72 385.34 ; + RECT 132.015 384.61 132.215 385.34 ; + RECT 132.51 384.61 132.87 385.34 ; + RECT 133.6 0.155 134.37 0.445 ; + RECT 133.6 0.155 133.86 8.665 ; + RECT 134.11 0.155 134.37 8.665 ; + RECT 133.08 384.61 133.28 385.34 ; + RECT 133.09 0.52 133.35 9.955 ; + RECT 133.735 384.61 133.935 385.34 ; + RECT 134.145 384.61 134.505 385.34 ; + RECT 134.62 0.52 134.88 11.315 ; + RECT 134.715 384.61 134.915 385.34 ; + RECT 135.13 0.52 135.39 13.45 ; + RECT 135.37 384.61 135.57 385.34 ; + RECT 135.64 0.52 135.9 14.115 ; + RECT 135.78 384.61 136.14 385.34 ; + RECT 136.435 384.61 136.635 385.34 ; + RECT 137.835 0.155 138.605 0.445 ; + RECT 137.835 0.155 138.095 13.21 ; + RECT 138.345 0.155 138.605 13.21 ; + RECT 136.93 384.61 137.29 385.34 ; + RECT 137.5 384.61 137.7 385.34 ; + RECT 138.855 0.18 139.625 0.88 ; + RECT 138.855 0.18 139.115 12.9 ; + RECT 139.365 0.18 139.625 12.9 ; + RECT 138.155 384.61 138.355 385.34 ; + RECT 138.565 384.61 138.925 385.34 ; + RECT 139.135 384.61 139.335 385.34 ; + RECT 139.79 384.61 139.99 385.34 ; + RECT 140.075 0.52 140.335 2.82 ; + RECT 140.2 384.61 140.56 385.34 ; + RECT 140.855 384.61 141.055 385.34 ; + RECT 141.35 384.61 141.71 385.34 ; + RECT 141.605 0.52 141.865 2.82 ; + RECT 141.92 384.61 142.12 385.34 ; + RECT 142.575 384.61 142.775 385.34 ; + RECT 142.78 0.52 143.04 4.315 ; + RECT 142.985 384.61 143.345 385.34 ; + RECT 143.555 384.61 143.755 385.34 ; + RECT 143.63 0.52 143.89 7.78 ; + RECT 144.14 0.3 144.4 5.235 ; + RECT 144.21 384.61 144.41 385.34 ; + RECT 144.65 0.52 144.91 5.57 ; + RECT 144.62 384.61 144.98 385.34 ; + RECT 145.275 384.61 145.475 385.34 ; + RECT 145.77 384.61 146.13 385.34 ; + RECT 146.025 0.52 146.285 6.28 ; + RECT 146.34 384.61 146.54 385.34 ; + RECT 146.995 384.61 147.195 385.34 ; + RECT 147.405 384.61 147.765 385.34 ; + RECT 147.975 384.61 148.175 385.34 ; + RECT 147.71 0.18 148.48 0.88 ; + RECT 148.63 384.61 148.83 385.34 ; + RECT 148.73 0.3 148.99 8.7 ; + RECT 149.04 384.61 149.4 385.34 ; + RECT 149.695 384.61 149.895 385.34 ; + RECT 150.19 384.61 150.55 385.34 ; + RECT 151.28 0.155 152.05 0.445 ; + RECT 151.28 0.155 151.54 8.665 ; + RECT 151.79 0.155 152.05 8.665 ; + RECT 150.76 384.61 150.96 385.34 ; + RECT 150.77 0.52 151.03 9.955 ; + RECT 151.415 384.61 151.615 385.34 ; + RECT 151.825 384.61 152.185 385.34 ; + RECT 152.3 0.52 152.56 11.315 ; + RECT 152.395 384.61 152.595 385.34 ; + RECT 152.81 0.52 153.07 13.45 ; + RECT 153.05 384.61 153.25 385.34 ; + RECT 153.32 0.52 153.58 14.115 ; + RECT 153.46 384.61 153.82 385.34 ; + RECT 154.115 384.61 154.315 385.34 ; + RECT 155.515 0.155 156.285 0.445 ; + RECT 155.515 0.155 155.775 13.21 ; + RECT 156.025 0.155 156.285 13.21 ; + RECT 154.61 384.61 154.97 385.34 ; + RECT 155.18 384.61 155.38 385.34 ; + RECT 156.535 0.18 157.305 0.88 ; + RECT 156.535 0.18 156.795 12.9 ; + RECT 157.045 0.18 157.305 12.9 ; + RECT 155.835 384.61 156.035 385.34 ; + RECT 156.245 384.61 156.605 385.34 ; + RECT 156.815 384.61 157.015 385.34 ; + RECT 157.47 384.61 157.67 385.34 ; + RECT 157.755 0.52 158.015 2.82 ; + RECT 157.88 384.61 158.24 385.34 ; + RECT 158.535 384.61 158.735 385.34 ; + RECT 159.03 384.61 159.39 385.34 ; + RECT 159.285 0.52 159.545 2.82 ; + RECT 159.6 384.61 159.8 385.34 ; + RECT 160.255 384.61 160.455 385.34 ; + RECT 160.46 0.52 160.72 4.315 ; + RECT 160.665 384.61 161.025 385.34 ; + RECT 161.235 384.61 161.435 385.34 ; + RECT 161.31 0.52 161.57 7.78 ; + RECT 161.82 0.3 162.08 5.235 ; + RECT 161.89 384.61 162.09 385.34 ; + RECT 162.33 0.52 162.59 5.57 ; + RECT 162.3 384.61 162.66 385.34 ; + RECT 162.955 384.61 163.155 385.34 ; + RECT 163.45 384.61 163.81 385.34 ; + RECT 163.705 0.52 163.965 6.28 ; + RECT 164.02 384.61 164.22 385.34 ; + RECT 164.675 384.61 164.875 385.34 ; + RECT 165.085 384.61 165.445 385.34 ; + RECT 165.655 384.61 165.855 385.34 ; + RECT 165.39 0.18 166.16 0.88 ; + RECT 166.31 384.61 166.51 385.34 ; + RECT 166.41 0.3 166.67 8.7 ; + RECT 166.72 384.61 167.08 385.34 ; + RECT 167.375 384.61 167.575 385.34 ; + RECT 167.87 384.61 168.23 385.34 ; + RECT 168.96 0.155 169.73 0.445 ; + RECT 168.96 0.155 169.22 8.665 ; + RECT 169.47 0.155 169.73 8.665 ; + RECT 168.44 384.61 168.64 385.34 ; + RECT 168.45 0.52 168.71 9.955 ; + RECT 169.095 384.61 169.295 385.34 ; + RECT 169.505 384.61 169.865 385.34 ; + RECT 169.98 0.52 170.24 11.315 ; + RECT 170.075 384.61 170.275 385.34 ; + RECT 170.49 0.52 170.75 13.45 ; + RECT 170.73 384.61 170.93 385.34 ; + RECT 171 0.52 171.26 14.115 ; + RECT 171.14 384.61 171.5 385.34 ; + RECT 171.795 384.61 171.995 385.34 ; + RECT 173.195 0.155 173.965 0.445 ; + RECT 173.195 0.155 173.455 13.21 ; + RECT 173.705 0.155 173.965 13.21 ; + RECT 172.29 384.61 172.65 385.34 ; + RECT 172.86 384.61 173.06 385.34 ; + RECT 174.215 0.18 174.985 0.88 ; + RECT 174.215 0.18 174.475 12.9 ; + RECT 174.725 0.18 174.985 12.9 ; + RECT 173.515 384.61 173.715 385.34 ; + RECT 173.925 384.61 174.285 385.34 ; + RECT 174.495 384.61 174.695 385.34 ; + RECT 175.15 384.61 175.35 385.34 ; + RECT 175.435 0.52 175.695 2.82 ; + RECT 175.56 384.61 175.92 385.34 ; + RECT 176.215 384.61 176.415 385.34 ; + RECT 176.71 384.61 177.07 385.34 ; + RECT 176.965 0.52 177.225 2.82 ; + RECT 177.28 384.61 177.48 385.34 ; + RECT 177.935 384.61 178.135 385.34 ; + RECT 178.14 0.52 178.4 4.315 ; + RECT 178.345 384.61 178.705 385.34 ; + RECT 178.915 384.61 179.115 385.34 ; + RECT 178.99 0.52 179.25 7.78 ; + RECT 179.5 0.3 179.76 5.235 ; + RECT 179.57 384.61 179.77 385.34 ; + RECT 180.01 0.52 180.27 5.57 ; + RECT 179.98 384.61 180.34 385.34 ; + RECT 180.635 384.61 180.835 385.34 ; + RECT 181.13 384.61 181.49 385.34 ; + RECT 181.385 0.52 181.645 6.28 ; + RECT 181.7 384.61 181.9 385.34 ; + RECT 182.355 384.61 182.555 385.34 ; + RECT 182.765 384.61 183.125 385.34 ; + RECT 183.335 384.61 183.535 385.34 ; + RECT 183.07 0.18 183.84 0.88 ; + RECT 183.99 384.61 184.19 385.34 ; + RECT 184.09 0.3 184.35 8.7 ; + RECT 184.4 384.61 184.76 385.34 ; + RECT 185.055 384.61 185.255 385.34 ; + RECT 185.55 384.61 185.91 385.34 ; + RECT 186.64 0.155 187.41 0.445 ; + RECT 186.64 0.155 186.9 8.665 ; + RECT 187.15 0.155 187.41 8.665 ; + RECT 186.12 384.61 186.32 385.34 ; + RECT 186.13 0.52 186.39 9.955 ; + RECT 186.775 384.61 186.975 385.34 ; + RECT 187.185 384.61 187.545 385.34 ; + RECT 187.66 0.52 187.92 11.315 ; + RECT 187.755 384.61 187.955 385.34 ; + RECT 188.17 0.52 188.43 13.45 ; + RECT 188.41 384.61 188.61 385.34 ; + RECT 188.68 0.52 188.94 14.115 ; + RECT 188.82 384.61 189.18 385.34 ; + RECT 189.475 384.61 189.675 385.34 ; + RECT 190.875 0.155 191.645 0.445 ; + RECT 190.875 0.155 191.135 13.21 ; + RECT 191.385 0.155 191.645 13.21 ; + RECT 189.97 384.61 190.33 385.34 ; + RECT 190.54 384.61 190.74 385.34 ; + RECT 191.895 0.18 192.665 0.88 ; + RECT 191.895 0.18 192.155 12.9 ; + RECT 192.405 0.18 192.665 12.9 ; + RECT 191.195 384.61 191.395 385.34 ; + RECT 191.605 384.61 191.965 385.34 ; + RECT 192.175 384.61 192.375 385.34 ; + RECT 192.83 384.61 193.03 385.34 ; + RECT 193.115 0.52 193.375 2.82 ; + RECT 193.24 384.61 193.6 385.34 ; + RECT 193.895 384.61 194.095 385.34 ; + RECT 194.39 384.61 194.75 385.34 ; + RECT 194.645 0.52 194.905 2.82 ; + RECT 194.96 384.61 195.16 385.34 ; + RECT 195.615 384.61 195.815 385.34 ; + RECT 195.82 0.52 196.08 4.315 ; + RECT 196.025 384.61 196.385 385.34 ; + RECT 196.595 384.61 196.795 385.34 ; + RECT 196.67 0.52 196.93 7.78 ; + RECT 197.18 0.3 197.44 5.235 ; + RECT 197.25 384.61 197.45 385.34 ; + RECT 197.69 0.52 197.95 5.57 ; + RECT 197.66 384.61 198.02 385.34 ; + RECT 198.315 384.61 198.515 385.34 ; + RECT 198.81 384.61 199.17 385.34 ; + RECT 199.065 0.52 199.325 6.28 ; + RECT 199.38 384.61 199.58 385.34 ; + RECT 200.035 384.61 200.235 385.34 ; + RECT 200.445 384.61 200.805 385.34 ; + RECT 201.015 384.61 201.215 385.34 ; + RECT 200.75 0.18 201.52 0.88 ; + RECT 201.67 384.61 201.87 385.34 ; + RECT 201.77 0.3 202.03 8.7 ; + RECT 202.08 384.61 202.44 385.34 ; + RECT 202.735 384.61 202.935 385.34 ; + RECT 203.23 384.61 203.59 385.34 ; + RECT 204.32 0.155 205.09 0.445 ; + RECT 204.32 0.155 204.58 8.665 ; + RECT 204.83 0.155 205.09 8.665 ; + RECT 203.8 384.61 204 385.34 ; + RECT 203.81 0.52 204.07 9.955 ; + RECT 204.455 384.61 204.655 385.34 ; + RECT 204.865 384.61 205.225 385.34 ; + RECT 205.34 0.52 205.6 11.315 ; + RECT 205.435 384.61 205.635 385.34 ; + RECT 205.85 0.52 206.11 13.45 ; + RECT 206.09 384.61 206.29 385.34 ; + RECT 206.36 0.52 206.62 14.115 ; + RECT 206.5 384.61 206.86 385.34 ; + RECT 207.155 384.61 207.355 385.34 ; + RECT 208.555 0.155 209.325 0.445 ; + RECT 208.555 0.155 208.815 13.21 ; + RECT 209.065 0.155 209.325 13.21 ; + RECT 207.65 384.61 208.01 385.34 ; + RECT 208.22 384.61 208.42 385.34 ; + RECT 209.575 0.18 210.345 0.88 ; + RECT 209.575 0.18 209.835 12.9 ; + RECT 210.085 0.18 210.345 12.9 ; + RECT 208.875 384.61 209.075 385.34 ; + RECT 209.285 384.61 209.645 385.34 ; + RECT 209.855 384.61 210.055 385.34 ; + RECT 210.51 384.61 210.71 385.34 ; + RECT 210.795 0.52 211.055 2.82 ; + RECT 210.92 384.61 211.28 385.34 ; + RECT 211.575 384.61 211.775 385.34 ; + RECT 212.07 384.61 212.43 385.34 ; + RECT 212.325 0.52 212.585 2.82 ; + RECT 212.64 384.61 212.84 385.34 ; + RECT 213.295 384.61 213.495 385.34 ; + RECT 213.5 0.52 213.76 4.315 ; + RECT 213.705 384.61 214.065 385.34 ; + RECT 214.275 384.61 214.475 385.34 ; + RECT 214.35 0.52 214.61 7.78 ; + RECT 214.86 0.3 215.12 5.235 ; + RECT 214.93 384.61 215.13 385.34 ; + RECT 215.37 0.52 215.63 5.57 ; + RECT 215.34 384.61 215.7 385.34 ; + RECT 215.995 384.61 216.195 385.34 ; + RECT 216.49 384.61 216.85 385.34 ; + RECT 216.745 0.52 217.005 6.28 ; + RECT 217.06 384.61 217.26 385.34 ; + RECT 217.715 384.61 217.915 385.34 ; + RECT 218.125 384.61 218.485 385.34 ; + RECT 218.695 384.61 218.895 385.34 ; + RECT 218.43 0.18 219.2 0.88 ; + RECT 219.35 384.61 219.55 385.34 ; + RECT 219.45 0.3 219.71 8.7 ; + RECT 219.76 384.61 220.12 385.34 ; + RECT 220.415 384.61 220.615 385.34 ; + RECT 220.91 384.61 221.27 385.34 ; + RECT 222 0.155 222.77 0.445 ; + RECT 222 0.155 222.26 8.665 ; + RECT 222.51 0.155 222.77 8.665 ; + RECT 221.48 384.61 221.68 385.34 ; + RECT 221.49 0.52 221.75 9.955 ; + RECT 222.135 384.61 222.335 385.34 ; + RECT 222.545 384.61 222.905 385.34 ; + RECT 223.02 0.52 223.28 11.315 ; + RECT 223.115 384.61 223.315 385.34 ; + RECT 223.53 0.52 223.79 13.45 ; + RECT 223.77 384.61 223.97 385.34 ; + RECT 224.04 0.52 224.3 14.115 ; + RECT 224.18 384.61 224.54 385.34 ; + RECT 224.835 384.61 225.035 385.34 ; + RECT 226.235 0.155 227.005 0.445 ; + RECT 226.235 0.155 226.495 13.21 ; + RECT 226.745 0.155 227.005 13.21 ; + RECT 225.33 384.61 225.69 385.34 ; + RECT 225.9 384.61 226.1 385.34 ; + RECT 227.255 0.18 228.025 0.88 ; + RECT 227.255 0.18 227.515 12.9 ; + RECT 227.765 0.18 228.025 12.9 ; + RECT 226.555 384.61 226.755 385.34 ; + RECT 226.965 384.61 227.325 385.34 ; + RECT 227.535 384.61 227.735 385.34 ; + RECT 228.19 384.61 228.39 385.34 ; + RECT 228.475 0.52 228.735 2.82 ; + RECT 228.6 384.61 228.96 385.34 ; + RECT 229.255 384.61 229.455 385.34 ; + RECT 229.75 384.61 230.11 385.34 ; + RECT 230.005 0.52 230.265 2.82 ; + RECT 230.32 384.61 230.52 385.34 ; + RECT 230.975 384.61 231.175 385.34 ; + RECT 231.18 0.52 231.44 4.315 ; + RECT 231.385 384.61 231.745 385.34 ; + RECT 231.955 384.61 232.155 385.34 ; + RECT 232.03 0.52 232.29 7.78 ; + RECT 232.54 0.3 232.8 5.235 ; + RECT 232.61 384.61 232.81 385.34 ; + RECT 233.05 0.52 233.31 5.57 ; + RECT 233.02 384.61 233.38 385.34 ; + RECT 233.675 384.61 233.875 385.34 ; + RECT 234.17 384.61 234.53 385.34 ; + RECT 234.425 0.52 234.685 6.28 ; + RECT 234.74 384.61 234.94 385.34 ; + RECT 235.395 384.61 235.595 385.34 ; + RECT 235.805 384.61 236.165 385.34 ; + RECT 236.375 384.61 236.575 385.34 ; + RECT 236.11 0.18 236.88 0.88 ; + RECT 237.03 384.61 237.23 385.34 ; + RECT 237.13 0.3 237.39 8.7 ; + RECT 237.44 384.61 237.8 385.34 ; + RECT 238.095 384.61 238.295 385.34 ; + RECT 238.59 384.61 238.95 385.34 ; + RECT 239.68 0.155 240.45 0.445 ; + RECT 239.68 0.155 239.94 8.665 ; + RECT 240.19 0.155 240.45 8.665 ; + RECT 239.16 384.61 239.36 385.34 ; + RECT 239.17 0.52 239.43 9.955 ; + RECT 239.815 384.61 240.015 385.34 ; + RECT 240.225 384.61 240.585 385.34 ; + RECT 240.7 0.52 240.96 11.315 ; + RECT 240.795 384.61 240.995 385.34 ; + RECT 241.21 0.52 241.47 13.45 ; + RECT 241.45 384.61 241.65 385.34 ; + RECT 241.72 0.52 241.98 14.115 ; + RECT 241.86 384.61 242.22 385.34 ; + RECT 242.515 384.61 242.715 385.34 ; + RECT 243.915 0.155 244.685 0.445 ; + RECT 243.915 0.155 244.175 13.21 ; + RECT 244.425 0.155 244.685 13.21 ; + RECT 243.01 384.61 243.37 385.34 ; + RECT 243.58 384.61 243.78 385.34 ; + RECT 244.935 0.18 245.705 0.88 ; + RECT 244.935 0.18 245.195 12.9 ; + RECT 245.445 0.18 245.705 12.9 ; + RECT 244.235 384.61 244.435 385.34 ; + RECT 244.645 384.61 245.005 385.34 ; + RECT 245.215 384.61 245.415 385.34 ; + RECT 245.87 384.61 246.07 385.34 ; + RECT 246.155 0.52 246.415 2.82 ; + RECT 246.28 384.61 246.64 385.34 ; + RECT 246.935 384.61 247.135 385.34 ; + RECT 247.43 384.61 247.79 385.34 ; + RECT 247.685 0.52 247.945 2.82 ; + RECT 248 384.61 248.2 385.34 ; + RECT 248.655 384.61 248.855 385.34 ; + RECT 248.86 0.52 249.12 4.315 ; + RECT 249.065 384.61 249.425 385.34 ; + RECT 249.635 384.61 249.835 385.34 ; + RECT 249.71 0.52 249.97 7.78 ; + RECT 250.22 0.3 250.48 5.235 ; + RECT 250.29 384.61 250.49 385.34 ; + RECT 250.73 0.52 250.99 5.57 ; + RECT 250.7 384.61 251.06 385.34 ; + RECT 251.355 384.61 251.555 385.34 ; + RECT 251.85 384.61 252.21 385.34 ; + RECT 252.105 0.52 252.365 6.28 ; + RECT 252.42 384.61 252.62 385.34 ; + RECT 253.075 384.61 253.275 385.34 ; + RECT 253.485 384.61 253.845 385.34 ; + RECT 254.055 384.61 254.255 385.34 ; + RECT 253.79 0.18 254.56 0.88 ; + RECT 254.71 384.61 254.91 385.34 ; + RECT 254.81 0.3 255.07 8.7 ; + RECT 255.12 384.61 255.48 385.34 ; + RECT 255.775 384.61 255.975 385.34 ; + RECT 256.27 384.61 256.63 385.34 ; + RECT 257.36 0.155 258.13 0.445 ; + RECT 257.36 0.155 257.62 8.665 ; + RECT 257.87 0.155 258.13 8.665 ; + RECT 256.84 384.61 257.04 385.34 ; + RECT 256.85 0.52 257.11 9.955 ; + RECT 257.495 384.61 257.695 385.34 ; + RECT 257.905 384.61 258.265 385.34 ; + RECT 258.38 0.52 258.64 11.315 ; + RECT 258.475 384.61 258.675 385.34 ; + RECT 258.89 0.52 259.15 13.45 ; + RECT 259.13 384.61 259.33 385.34 ; + RECT 259.4 0.52 259.66 14.115 ; + RECT 259.54 384.61 259.9 385.34 ; + RECT 260.195 384.61 260.395 385.34 ; + RECT 261.595 0.155 262.365 0.445 ; + RECT 261.595 0.155 261.855 13.21 ; + RECT 262.105 0.155 262.365 13.21 ; + RECT 260.69 384.61 261.05 385.34 ; + RECT 261.26 384.61 261.46 385.34 ; + RECT 262.615 0.18 263.385 0.88 ; + RECT 262.615 0.18 262.875 12.9 ; + RECT 263.125 0.18 263.385 12.9 ; + RECT 261.915 384.61 262.115 385.34 ; + RECT 262.325 384.61 262.685 385.34 ; + RECT 262.895 384.61 263.095 385.34 ; + RECT 263.55 384.61 263.75 385.34 ; + RECT 263.835 0.52 264.095 2.82 ; + RECT 263.96 384.61 264.32 385.34 ; + RECT 264.615 384.61 264.815 385.34 ; + RECT 265.11 384.61 265.47 385.34 ; + RECT 265.365 0.52 265.625 2.82 ; + RECT 265.68 384.61 265.88 385.34 ; + RECT 266.335 384.61 266.535 385.34 ; + RECT 266.54 0.52 266.8 4.315 ; + RECT 266.745 384.61 267.105 385.34 ; + RECT 267.315 384.61 267.515 385.34 ; + RECT 267.39 0.52 267.65 7.78 ; + RECT 267.9 0.3 268.16 5.235 ; + RECT 267.97 384.61 268.17 385.34 ; + RECT 268.41 0.52 268.67 5.57 ; + RECT 268.38 384.61 268.74 385.34 ; + RECT 269.035 384.61 269.235 385.34 ; + RECT 269.53 384.61 269.89 385.34 ; + RECT 269.785 0.52 270.045 6.28 ; + RECT 270.1 384.61 270.3 385.34 ; + RECT 270.755 384.61 270.955 385.34 ; + RECT 271.165 384.61 271.525 385.34 ; + RECT 271.735 384.61 271.935 385.34 ; + RECT 271.47 0.18 272.24 0.88 ; + RECT 272.39 384.61 272.59 385.34 ; + RECT 272.49 0.3 272.75 8.7 ; + RECT 272.8 384.61 273.16 385.34 ; + RECT 273.455 384.61 273.655 385.34 ; + RECT 273.95 384.61 274.31 385.34 ; + RECT 275.04 0.155 275.81 0.445 ; + RECT 275.04 0.155 275.3 8.665 ; + RECT 275.55 0.155 275.81 8.665 ; + RECT 274.52 384.61 274.72 385.34 ; + RECT 274.53 0.52 274.79 9.955 ; + RECT 275.175 384.61 275.375 385.34 ; + RECT 275.585 384.61 275.945 385.34 ; + RECT 276.06 0.52 276.32 11.315 ; + RECT 276.155 384.61 276.355 385.34 ; + RECT 276.57 0.52 276.83 13.45 ; + RECT 276.81 384.61 277.01 385.34 ; + RECT 277.08 0.52 277.34 14.115 ; + RECT 277.22 384.61 277.58 385.34 ; + RECT 277.875 384.61 278.075 385.34 ; + RECT 279.275 0.155 280.045 0.445 ; + RECT 279.275 0.155 279.535 13.21 ; + RECT 279.785 0.155 280.045 13.21 ; + RECT 278.37 384.61 278.73 385.34 ; + RECT 278.94 384.61 279.14 385.34 ; + RECT 280.295 0.18 281.065 0.88 ; + RECT 280.295 0.18 280.555 12.9 ; + RECT 280.805 0.18 281.065 12.9 ; + RECT 279.595 384.61 279.795 385.34 ; + RECT 280.005 384.61 280.365 385.34 ; + RECT 280.575 384.61 280.775 385.34 ; + RECT 281.23 384.61 281.43 385.34 ; + RECT 281.515 0.52 281.775 2.82 ; + RECT 281.64 384.61 282 385.34 ; + RECT 282.295 384.61 282.495 385.34 ; + RECT 282.79 384.61 283.15 385.34 ; + RECT 283.045 0.52 283.305 2.82 ; + RECT 283.36 384.61 283.56 385.34 ; + RECT 284.015 384.61 284.215 385.34 ; + RECT 285.24 0.17 286.01 0.43 ; + RECT 285.24 0.17 285.5 8.7 ; + RECT 285.75 0.17 286.01 8.7 ; + RECT 284.22 0.52 284.48 4.315 ; + RECT 286.26 0.18 287.03 0.88 ; + RECT 286.26 0.18 286.52 8.7 ; + RECT 286.77 0.18 287.03 8.7 ; + RECT 287.28 0.17 288.05 0.43 ; + RECT 287.28 0.17 287.54 8.7 ; + RECT 287.79 0.17 288.05 8.7 ; + RECT 288.3 0.18 289.07 0.88 ; + RECT 288.3 0.18 288.56 8.7 ; + RECT 288.81 0.18 289.07 8.7 ; + RECT 289.32 0.17 290.09 0.43 ; + RECT 289.32 0.17 289.58 8.7 ; + RECT 289.83 0.17 290.09 8.7 ; + RECT 290.34 0.18 291.11 0.88 ; + RECT 290.34 0.18 290.6 8.7 ; + RECT 290.85 0.18 291.11 8.7 ; + RECT 291.36 0.17 292.13 0.43 ; + RECT 291.36 0.17 291.62 8.7 ; + RECT 291.87 0.17 292.13 8.7 ; + RECT 292.38 0.18 293.15 0.88 ; + RECT 292.38 0.18 292.64 8.7 ; + RECT 292.89 0.18 293.15 8.7 ; + RECT 293.4 0.17 294.17 0.43 ; + RECT 293.4 0.17 293.66 8.7 ; + RECT 293.91 0.17 294.17 8.7 ; + RECT 294.42 0.18 295.19 0.88 ; + RECT 294.42 0.18 294.68 8.7 ; + RECT 294.93 0.18 295.19 8.7 ; + RECT 295.44 0.17 296.21 0.43 ; + RECT 295.44 0.17 295.7 8.7 ; + RECT 295.95 0.17 296.21 8.7 ; + RECT 296.46 0.18 297.23 0.88 ; + RECT 296.46 0.18 296.72 8.7 ; + RECT 296.97 0.18 297.23 8.7 ; + RECT 297.48 0.17 298.25 0.43 ; + RECT 297.48 0.17 297.74 8.7 ; + RECT 297.99 0.17 298.25 8.7 ; + RECT 298.5 0.18 299.27 0.88 ; + RECT 298.5 0.18 298.76 8.7 ; + RECT 299.01 0.18 299.27 8.7 ; + RECT 299.52 0.17 300.29 0.43 ; + RECT 299.52 0.17 299.78 8.7 ; + RECT 300.03 0.17 300.29 8.7 ; + RECT 300.54 0.18 301.31 0.88 ; + RECT 300.54 0.18 300.8 8.7 ; + RECT 301.05 0.18 301.31 8.7 ; + RECT 284.425 384.61 284.785 385.34 ; + RECT 284.995 384.61 285.195 385.34 ; + RECT 302.935 0.18 303.705 0.88 ; + RECT 302.935 0.18 303.195 8.7 ; + RECT 303.445 0.18 303.705 8.7 ; + RECT 303.955 0.17 304.725 0.43 ; + RECT 303.955 0.17 304.215 8.7 ; + RECT 304.465 0.17 304.725 8.7 ; + RECT 285.82 384.53 286.02 385.34 ; + RECT 301.915 0.3 302.175 8.7 ; + RECT 305.995 0.18 306.765 0.88 ; + RECT 305.995 0.18 306.255 8.7 ; + RECT 306.505 0.18 306.765 8.7 ; + RECT 302.425 0.3 302.685 8.7 ; + RECT 304.975 0 305.235 8.7 ; + RECT 305.485 0 305.745 8.7 ; + RECT 307.015 0.52 307.275 8.7 ; + RECT 307.525 0.3 307.785 8.7 ; + RECT 308.035 0.3 308.295 8.7 ; + RECT 308.545 0.3 308.805 8.7 ; + RECT 309.055 0.3 309.315 8.7 ; + RECT 309.565 0.3 309.825 8.7 ; + RECT 310.075 0.3 310.335 8.7 ; + RECT 310.585 0.3 310.845 8.7 ; + RECT 312.625 0.18 313.395 0.88 ; + RECT 312.625 0.18 312.885 8.7 ; + RECT 313.135 0.18 313.395 8.7 ; + RECT 311.095 0.3 311.355 8.7 ; + RECT 311.605 0.52 311.865 8.7 ; + RECT 312.115 0.52 312.375 8.7 ; + RECT 313.645 0.52 313.905 8.7 ; + RECT 314.155 0.52 314.415 8.7 ; + RECT 314.665 0.52 314.925 8.7 ; + RECT 315.175 0.52 315.435 8.7 ; + RECT 315.685 0.52 315.945 8.7 ; + RECT 316.195 0.52 316.455 8.7 ; + RECT 316.705 0.52 316.965 8.7 ; + RECT 317.215 0.52 317.475 8.7 ; + RECT 317.725 0.52 317.985 8.7 ; + RECT 318.235 0.52 318.495 8.7 ; + RECT 318.745 0.3 319.005 8.7 ; + RECT 319.255 0.3 319.515 8.7 ; + RECT 319.765 0.3 320.025 8.7 ; + RECT 320.275 0.52 320.535 8.7 ; + RECT 320.785 0.52 321.045 8.7 ; + RECT 321.295 0.3 321.555 8.7 ; + RECT 321.805 0.3 322.065 8.7 ; + RECT 322.315 0.3 322.575 8.7 ; + RECT 322.825 0.52 323.085 8.7 ; + RECT 323.335 0.52 323.595 8.7 ; + RECT 323.845 0.3 324.105 8.7 ; + RECT 324.355 0.52 324.615 8.7 ; + RECT 324.865 0.52 325.125 8.7 ; + RECT 325.375 0.52 325.635 8.7 ; + RECT 325.885 0.52 326.145 8.7 ; + RECT 326.395 0.52 326.655 8.7 ; + RECT 326.905 0.3 327.165 8.7 ; + RECT 327.415 0.52 327.675 8.7 ; + RECT 327.925 0.52 328.185 8.7 ; + RECT 328.435 0.3 328.695 8.7 ; + RECT 328.945 0.52 329.205 8.7 ; + RECT 330.985 0.17 331.755 0.43 ; + RECT 330.985 0.17 331.245 8.7 ; + RECT 331.495 0.17 331.755 8.7 ; + RECT 329.455 0.52 329.715 8.7 ; + RECT 329.965 0.3 330.225 8.7 ; + RECT 330.475 0.3 330.735 8.7 ; + RECT 333.535 0.17 334.305 0.43 ; + RECT 333.535 0.17 333.795 8.7 ; + RECT 334.045 0.17 334.305 8.7 ; + RECT 332.005 0.3 332.265 8.7 ; + RECT 335.065 0.18 335.835 0.88 ; + RECT 335.065 0.18 335.325 8.7 ; + RECT 335.575 0.18 335.835 8.7 ; + RECT 332.515 0.3 332.775 8.7 ; + RECT 333.025 0.3 333.285 8.7 ; + RECT 334.555 0.3 334.815 8.7 ; + RECT 336.085 0 336.345 8.7 ; + RECT 336.595 0 336.855 8.7 ; + RECT 337.105 0.52 337.365 8.7 ; + RECT 337.615 0.52 337.875 8.7 ; + RECT 338.125 0.52 338.385 8.7 ; + RECT 338.635 0.52 338.895 8.7 ; + RECT 339.145 0 339.405 8.7 ; + RECT 339.655 0 339.915 8.7 ; + RECT 340.165 0.3 340.425 8.7 ; + RECT 340.675 0.3 340.935 8.7 ; + RECT 341.185 0 341.445 8.7 ; + RECT 341.695 0 341.955 8.7 ; + RECT 342.205 0.3 342.465 8.7 ; + RECT 343.025 0.3 343.285 8.7 ; + RECT 343.535 0 343.795 8.7 ; + RECT 344.045 0 344.305 8.7 ; + RECT 344.555 0.3 344.815 8.7 ; + RECT 345.065 0.3 345.325 8.7 ; + RECT 345.575 0 345.835 8.7 ; + RECT 346.085 0 346.345 8.7 ; + RECT 346.595 0.52 346.855 8.7 ; + RECT 347.105 0.52 347.365 8.7 ; + RECT 347.615 0.52 347.875 8.7 ; + RECT 349.655 0.18 350.425 0.88 ; + RECT 349.655 0.18 349.915 8.7 ; + RECT 350.165 0.18 350.425 8.7 ; + RECT 348.125 0.52 348.385 8.7 ; + RECT 351.185 0.17 351.955 0.43 ; + RECT 351.185 0.17 351.445 8.7 ; + RECT 351.695 0.17 351.955 8.7 ; + RECT 348.635 0 348.895 8.7 ; + RECT 349.145 0 349.405 8.7 ; + RECT 350.675 0.3 350.935 8.7 ; + RECT 353.735 0.17 354.505 0.43 ; + RECT 353.735 0.17 353.995 8.7 ; + RECT 354.245 0.17 354.505 8.7 ; + RECT 352.205 0.3 352.465 8.7 ; + RECT 352.715 0.3 352.975 8.7 ; + RECT 353.225 0.3 353.485 8.7 ; + RECT 354.755 0.3 355.015 8.7 ; + RECT 355.265 0.3 355.525 8.7 ; + RECT 355.775 0.52 356.035 8.7 ; + RECT 356.285 0.52 356.545 8.7 ; + RECT 356.795 0.3 357.055 8.7 ; + RECT 357.305 0.52 357.565 8.7 ; + RECT 357.815 0.52 358.075 8.7 ; + RECT 358.325 0.3 358.585 8.7 ; + RECT 358.835 0.52 359.095 8.7 ; + RECT 359.345 0.52 359.605 8.7 ; + RECT 359.855 0.52 360.115 8.7 ; + RECT 360.365 0.52 360.625 8.7 ; + RECT 360.875 0.52 361.135 8.7 ; + RECT 361.385 0.3 361.645 8.7 ; + RECT 361.895 0.52 362.155 8.7 ; + RECT 362.405 0.52 362.665 8.7 ; + RECT 362.915 0.3 363.175 8.7 ; + RECT 363.425 0.3 363.685 8.7 ; + RECT 363.935 0.3 364.195 8.7 ; + RECT 364.445 0.52 364.705 8.7 ; + RECT 364.955 0.52 365.215 8.7 ; + RECT 365.465 0.3 365.725 8.7 ; + RECT 365.975 0.3 366.235 8.7 ; + RECT 366.485 0.3 366.745 8.7 ; + RECT 366.995 0.52 367.255 8.7 ; + RECT 367.505 0.52 367.765 8.7 ; + RECT 368.015 0.52 368.275 8.7 ; + RECT 368.525 0.52 368.785 8.7 ; + RECT 369.035 0.52 369.295 8.7 ; + RECT 369.545 0.52 369.805 8.7 ; + RECT 370.055 0.52 370.315 8.7 ; + RECT 372.095 0.18 372.865 0.88 ; + RECT 372.095 0.18 372.355 8.7 ; + RECT 372.605 0.18 372.865 8.7 ; + RECT 370.565 0.52 370.825 8.7 ; + RECT 371.075 0.52 371.335 8.7 ; + RECT 371.585 0.52 371.845 8.7 ; + RECT 373.115 0.52 373.375 8.7 ; + RECT 373.625 0.52 373.885 8.7 ; + RECT 374.135 0.3 374.395 8.7 ; + RECT 374.645 0.3 374.905 8.7 ; + RECT 375.155 0.3 375.415 8.7 ; + RECT 375.665 0.3 375.925 8.7 ; + RECT 376.175 0.3 376.435 8.7 ; + RECT 376.685 0.3 376.945 8.7 ; + RECT 378.725 0.18 379.495 0.88 ; + RECT 378.725 0.18 378.985 8.7 ; + RECT 379.235 0.18 379.495 8.7 ; + RECT 377.195 0.3 377.455 8.7 ; + RECT 377.705 0.3 377.965 8.7 ; + RECT 380.765 0.17 381.535 0.43 ; + RECT 380.765 0.17 381.025 8.7 ; + RECT 381.275 0.17 381.535 8.7 ; + RECT 381.785 0.18 382.555 0.88 ; + RECT 381.785 0.18 382.045 8.7 ; + RECT 382.295 0.18 382.555 8.7 ; + RECT 378.215 0.52 378.475 8.7 ; + RECT 379.745 0 380.005 8.7 ; + RECT 384.18 0.18 384.95 0.88 ; + RECT 384.18 0.18 384.44 8.7 ; + RECT 384.69 0.18 384.95 8.7 ; + RECT 385.2 0.17 385.97 0.43 ; + RECT 385.2 0.17 385.46 8.7 ; + RECT 385.71 0.17 385.97 8.7 ; + RECT 386.22 0.18 386.99 0.88 ; + RECT 386.22 0.18 386.48 8.7 ; + RECT 386.73 0.18 386.99 8.7 ; + RECT 387.24 0.17 388.01 0.43 ; + RECT 387.24 0.17 387.5 8.7 ; + RECT 387.75 0.17 388.01 8.7 ; + RECT 388.26 0.18 389.03 0.88 ; + RECT 388.26 0.18 388.52 8.7 ; + RECT 388.77 0.18 389.03 8.7 ; + RECT 389.28 0.17 390.05 0.43 ; + RECT 389.28 0.17 389.54 8.7 ; + RECT 389.79 0.17 390.05 8.7 ; + RECT 390.3 0.18 391.07 0.88 ; + RECT 390.3 0.18 390.56 8.7 ; + RECT 390.81 0.18 391.07 8.7 ; + RECT 391.32 0.17 392.09 0.43 ; + RECT 391.32 0.17 391.58 8.7 ; + RECT 391.83 0.17 392.09 8.7 ; + RECT 392.34 0.18 393.11 0.88 ; + RECT 392.34 0.18 392.6 8.7 ; + RECT 392.85 0.18 393.11 8.7 ; + RECT 393.36 0.17 394.13 0.43 ; + RECT 393.36 0.17 393.62 8.7 ; + RECT 393.87 0.17 394.13 8.7 ; + RECT 394.38 0.18 395.15 0.88 ; + RECT 394.38 0.18 394.64 8.7 ; + RECT 394.89 0.18 395.15 8.7 ; + RECT 395.4 0.17 396.17 0.43 ; + RECT 395.4 0.17 395.66 8.7 ; + RECT 395.91 0.17 396.17 8.7 ; + RECT 396.42 0.18 397.19 0.88 ; + RECT 396.42 0.18 396.68 8.7 ; + RECT 396.93 0.18 397.19 8.7 ; + RECT 397.44 0.17 398.21 0.43 ; + RECT 397.44 0.17 397.7 8.7 ; + RECT 397.95 0.17 398.21 8.7 ; + RECT 398.46 0.18 399.23 0.88 ; + RECT 398.46 0.18 398.72 8.7 ; + RECT 398.97 0.18 399.23 8.7 ; + RECT 380.255 0 380.515 8.7 ; + RECT 399.48 0.17 400.25 0.43 ; + RECT 399.48 0.17 399.74 8.7 ; + RECT 399.99 0.17 400.25 8.7 ; + RECT 382.805 0.3 383.065 8.7 ; + RECT 383.315 0.3 383.575 8.7 ; + RECT 399.47 384.53 399.67 385.34 ; + RECT 400.295 384.61 400.495 385.34 ; + RECT 400.705 384.61 401.065 385.34 ; + RECT 401.01 0.52 401.27 4.315 ; + RECT 401.275 384.61 401.475 385.34 ; + RECT 401.93 384.61 402.13 385.34 ; + RECT 402.185 0.52 402.445 2.82 ; + RECT 402.34 384.61 402.7 385.34 ; + RECT 402.995 384.61 403.195 385.34 ; + RECT 403.49 384.61 403.85 385.34 ; + RECT 404.425 0.18 405.195 0.88 ; + RECT 404.425 0.18 404.685 12.9 ; + RECT 404.935 0.18 405.195 12.9 ; + RECT 403.715 0.52 403.975 2.82 ; + RECT 404.06 384.61 404.26 385.34 ; + RECT 405.445 0.155 406.215 0.445 ; + RECT 405.445 0.155 405.705 13.21 ; + RECT 405.955 0.155 406.215 13.21 ; + RECT 404.715 384.61 404.915 385.34 ; + RECT 405.125 384.61 405.485 385.34 ; + RECT 405.695 384.61 405.895 385.34 ; + RECT 406.35 384.61 406.55 385.34 ; + RECT 406.76 384.61 407.12 385.34 ; + RECT 407.415 384.61 407.615 385.34 ; + RECT 407.91 384.61 408.27 385.34 ; + RECT 408.15 0.52 408.41 14.115 ; + RECT 408.48 384.61 408.68 385.34 ; + RECT 408.66 0.52 408.92 13.45 ; + RECT 409.135 384.61 409.335 385.34 ; + RECT 409.68 0.155 410.45 0.445 ; + RECT 409.68 0.155 409.94 8.665 ; + RECT 410.19 0.155 410.45 8.665 ; + RECT 409.17 0.52 409.43 11.315 ; + RECT 409.545 384.61 409.905 385.34 ; + RECT 410.115 384.61 410.315 385.34 ; + RECT 410.7 0.52 410.96 9.955 ; + RECT 410.77 384.61 410.97 385.34 ; + RECT 411.18 384.61 411.54 385.34 ; + RECT 411.835 384.61 412.035 385.34 ; + RECT 412.33 384.61 412.69 385.34 ; + RECT 412.74 0.3 413 8.7 ; + RECT 412.9 384.61 413.1 385.34 ; + RECT 413.555 384.61 413.755 385.34 ; + RECT 413.25 0.18 414.02 0.88 ; + RECT 413.965 384.61 414.325 385.34 ; + RECT 414.535 384.61 414.735 385.34 ; + RECT 415.19 384.61 415.39 385.34 ; + RECT 415.445 0.52 415.705 6.28 ; + RECT 415.6 384.61 415.96 385.34 ; + RECT 416.255 384.61 416.455 385.34 ; + RECT 416.82 0.52 417.08 5.57 ; + RECT 416.75 384.61 417.11 385.34 ; + RECT 417.32 384.61 417.52 385.34 ; + RECT 417.33 0.3 417.59 5.235 ; + RECT 417.84 0.52 418.1 7.78 ; + RECT 417.975 384.61 418.175 385.34 ; + RECT 418.385 384.61 418.745 385.34 ; + RECT 418.69 0.52 418.95 4.315 ; + RECT 418.955 384.61 419.155 385.34 ; + RECT 419.61 384.61 419.81 385.34 ; + RECT 419.865 0.52 420.125 2.82 ; + RECT 420.02 384.61 420.38 385.34 ; + RECT 420.675 384.61 420.875 385.34 ; + RECT 421.17 384.61 421.53 385.34 ; + RECT 422.105 0.18 422.875 0.88 ; + RECT 422.105 0.18 422.365 12.9 ; + RECT 422.615 0.18 422.875 12.9 ; + RECT 421.395 0.52 421.655 2.82 ; + RECT 421.74 384.61 421.94 385.34 ; + RECT 423.125 0.155 423.895 0.445 ; + RECT 423.125 0.155 423.385 13.21 ; + RECT 423.635 0.155 423.895 13.21 ; + RECT 422.395 384.61 422.595 385.34 ; + RECT 422.805 384.61 423.165 385.34 ; + RECT 423.375 384.61 423.575 385.34 ; + RECT 424.03 384.61 424.23 385.34 ; + RECT 424.44 384.61 424.8 385.34 ; + RECT 425.095 384.61 425.295 385.34 ; + RECT 425.59 384.61 425.95 385.34 ; + RECT 425.83 0.52 426.09 14.115 ; + RECT 426.16 384.61 426.36 385.34 ; + RECT 426.34 0.52 426.6 13.45 ; + RECT 426.815 384.61 427.015 385.34 ; + RECT 427.36 0.155 428.13 0.445 ; + RECT 427.36 0.155 427.62 8.665 ; + RECT 427.87 0.155 428.13 8.665 ; + RECT 426.85 0.52 427.11 11.315 ; + RECT 427.225 384.61 427.585 385.34 ; + RECT 427.795 384.61 427.995 385.34 ; + RECT 428.38 0.52 428.64 9.955 ; + RECT 428.45 384.61 428.65 385.34 ; + RECT 428.86 384.61 429.22 385.34 ; + RECT 429.515 384.61 429.715 385.34 ; + RECT 430.01 384.61 430.37 385.34 ; + RECT 430.42 0.3 430.68 8.7 ; + RECT 430.58 384.61 430.78 385.34 ; + RECT 431.235 384.61 431.435 385.34 ; + RECT 430.93 0.18 431.7 0.88 ; + RECT 431.645 384.61 432.005 385.34 ; + RECT 432.215 384.61 432.415 385.34 ; + RECT 432.87 384.61 433.07 385.34 ; + RECT 433.125 0.52 433.385 6.28 ; + RECT 433.28 384.61 433.64 385.34 ; + RECT 433.935 384.61 434.135 385.34 ; + RECT 434.5 0.52 434.76 5.57 ; + RECT 434.43 384.61 434.79 385.34 ; + RECT 435 384.61 435.2 385.34 ; + RECT 435.01 0.3 435.27 5.235 ; + RECT 435.52 0.52 435.78 7.78 ; + RECT 435.655 384.61 435.855 385.34 ; + RECT 436.065 384.61 436.425 385.34 ; + RECT 436.37 0.52 436.63 4.315 ; + RECT 436.635 384.61 436.835 385.34 ; + RECT 437.29 384.61 437.49 385.34 ; + RECT 437.545 0.52 437.805 2.82 ; + RECT 437.7 384.61 438.06 385.34 ; + RECT 438.355 384.61 438.555 385.34 ; + RECT 438.85 384.61 439.21 385.34 ; + RECT 439.785 0.18 440.555 0.88 ; + RECT 439.785 0.18 440.045 12.9 ; + RECT 440.295 0.18 440.555 12.9 ; + RECT 439.075 0.52 439.335 2.82 ; + RECT 439.42 384.61 439.62 385.34 ; + RECT 440.805 0.155 441.575 0.445 ; + RECT 440.805 0.155 441.065 13.21 ; + RECT 441.315 0.155 441.575 13.21 ; + RECT 440.075 384.61 440.275 385.34 ; + RECT 440.485 384.61 440.845 385.34 ; + RECT 441.055 384.61 441.255 385.34 ; + RECT 441.71 384.61 441.91 385.34 ; + RECT 442.12 384.61 442.48 385.34 ; + RECT 442.775 384.61 442.975 385.34 ; + RECT 443.27 384.61 443.63 385.34 ; + RECT 443.51 0.52 443.77 14.115 ; + RECT 443.84 384.61 444.04 385.34 ; + RECT 444.02 0.52 444.28 13.45 ; + RECT 444.495 384.61 444.695 385.34 ; + RECT 445.04 0.155 445.81 0.445 ; + RECT 445.04 0.155 445.3 8.665 ; + RECT 445.55 0.155 445.81 8.665 ; + RECT 444.53 0.52 444.79 11.315 ; + RECT 444.905 384.61 445.265 385.34 ; + RECT 445.475 384.61 445.675 385.34 ; + RECT 446.06 0.52 446.32 9.955 ; + RECT 446.13 384.61 446.33 385.34 ; + RECT 446.54 384.61 446.9 385.34 ; + RECT 447.195 384.61 447.395 385.34 ; + RECT 447.69 384.61 448.05 385.34 ; + RECT 448.1 0.3 448.36 8.7 ; + RECT 448.26 384.61 448.46 385.34 ; + RECT 448.915 384.61 449.115 385.34 ; + RECT 448.61 0.18 449.38 0.88 ; + RECT 449.325 384.61 449.685 385.34 ; + RECT 449.895 384.61 450.095 385.34 ; + RECT 450.55 384.61 450.75 385.34 ; + RECT 450.805 0.52 451.065 6.28 ; + RECT 450.96 384.61 451.32 385.34 ; + RECT 451.615 384.61 451.815 385.34 ; + RECT 452.18 0.52 452.44 5.57 ; + RECT 452.11 384.61 452.47 385.34 ; + RECT 452.68 384.61 452.88 385.34 ; + RECT 452.69 0.3 452.95 5.235 ; + RECT 453.2 0.52 453.46 7.78 ; + RECT 453.335 384.61 453.535 385.34 ; + RECT 453.745 384.61 454.105 385.34 ; + RECT 454.05 0.52 454.31 4.315 ; + RECT 454.315 384.61 454.515 385.34 ; + RECT 454.97 384.61 455.17 385.34 ; + RECT 455.225 0.52 455.485 2.82 ; + RECT 455.38 384.61 455.74 385.34 ; + RECT 456.035 384.61 456.235 385.34 ; + RECT 456.53 384.61 456.89 385.34 ; + RECT 457.465 0.18 458.235 0.88 ; + RECT 457.465 0.18 457.725 12.9 ; + RECT 457.975 0.18 458.235 12.9 ; + RECT 456.755 0.52 457.015 2.82 ; + RECT 457.1 384.61 457.3 385.34 ; + RECT 458.485 0.155 459.255 0.445 ; + RECT 458.485 0.155 458.745 13.21 ; + RECT 458.995 0.155 459.255 13.21 ; + RECT 457.755 384.61 457.955 385.34 ; + RECT 458.165 384.61 458.525 385.34 ; + RECT 458.735 384.61 458.935 385.34 ; + RECT 459.39 384.61 459.59 385.34 ; + RECT 459.8 384.61 460.16 385.34 ; + RECT 460.455 384.61 460.655 385.34 ; + RECT 460.95 384.61 461.31 385.34 ; + RECT 461.19 0.52 461.45 14.115 ; + RECT 461.52 384.61 461.72 385.34 ; + RECT 461.7 0.52 461.96 13.45 ; + RECT 462.175 384.61 462.375 385.34 ; + RECT 462.72 0.155 463.49 0.445 ; + RECT 462.72 0.155 462.98 8.665 ; + RECT 463.23 0.155 463.49 8.665 ; + RECT 462.21 0.52 462.47 11.315 ; + RECT 462.585 384.61 462.945 385.34 ; + RECT 463.155 384.61 463.355 385.34 ; + RECT 463.74 0.52 464 9.955 ; + RECT 463.81 384.61 464.01 385.34 ; + RECT 464.22 384.61 464.58 385.34 ; + RECT 464.875 384.61 465.075 385.34 ; + RECT 465.37 384.61 465.73 385.34 ; + RECT 465.78 0.3 466.04 8.7 ; + RECT 465.94 384.61 466.14 385.34 ; + RECT 466.595 384.61 466.795 385.34 ; + RECT 466.29 0.18 467.06 0.88 ; + RECT 467.005 384.61 467.365 385.34 ; + RECT 467.575 384.61 467.775 385.34 ; + RECT 468.23 384.61 468.43 385.34 ; + RECT 468.485 0.52 468.745 6.28 ; + RECT 468.64 384.61 469 385.34 ; + RECT 469.295 384.61 469.495 385.34 ; + RECT 469.86 0.52 470.12 5.57 ; + RECT 469.79 384.61 470.15 385.34 ; + RECT 470.36 384.61 470.56 385.34 ; + RECT 470.37 0.3 470.63 5.235 ; + RECT 470.88 0.52 471.14 7.78 ; + RECT 471.015 384.61 471.215 385.34 ; + RECT 471.425 384.61 471.785 385.34 ; + RECT 471.73 0.52 471.99 4.315 ; + RECT 471.995 384.61 472.195 385.34 ; + RECT 472.65 384.61 472.85 385.34 ; + RECT 472.905 0.52 473.165 2.82 ; + RECT 473.06 384.61 473.42 385.34 ; + RECT 473.715 384.61 473.915 385.34 ; + RECT 474.21 384.61 474.57 385.34 ; + RECT 475.145 0.18 475.915 0.88 ; + RECT 475.145 0.18 475.405 12.9 ; + RECT 475.655 0.18 475.915 12.9 ; + RECT 474.435 0.52 474.695 2.82 ; + RECT 474.78 384.61 474.98 385.34 ; + RECT 476.165 0.155 476.935 0.445 ; + RECT 476.165 0.155 476.425 13.21 ; + RECT 476.675 0.155 476.935 13.21 ; + RECT 475.435 384.61 475.635 385.34 ; + RECT 475.845 384.61 476.205 385.34 ; + RECT 476.415 384.61 476.615 385.34 ; + RECT 477.07 384.61 477.27 385.34 ; + RECT 477.48 384.61 477.84 385.34 ; + RECT 478.135 384.61 478.335 385.34 ; + RECT 478.63 384.61 478.99 385.34 ; + RECT 478.87 0.52 479.13 14.115 ; + RECT 479.2 384.61 479.4 385.34 ; + RECT 479.38 0.52 479.64 13.45 ; + RECT 479.855 384.61 480.055 385.34 ; + RECT 480.4 0.155 481.17 0.445 ; + RECT 480.4 0.155 480.66 8.665 ; + RECT 480.91 0.155 481.17 8.665 ; + RECT 479.89 0.52 480.15 11.315 ; + RECT 480.265 384.61 480.625 385.34 ; + RECT 480.835 384.61 481.035 385.34 ; + RECT 481.42 0.52 481.68 9.955 ; + RECT 481.49 384.61 481.69 385.34 ; + RECT 481.9 384.61 482.26 385.34 ; + RECT 482.555 384.61 482.755 385.34 ; + RECT 483.05 384.61 483.41 385.34 ; + RECT 483.46 0.3 483.72 8.7 ; + RECT 483.62 384.61 483.82 385.34 ; + RECT 484.275 384.61 484.475 385.34 ; + RECT 483.97 0.18 484.74 0.88 ; + RECT 484.685 384.61 485.045 385.34 ; + RECT 485.255 384.61 485.455 385.34 ; + RECT 485.91 384.61 486.11 385.34 ; + RECT 486.165 0.52 486.425 6.28 ; + RECT 486.32 384.61 486.68 385.34 ; + RECT 486.975 384.61 487.175 385.34 ; + RECT 487.54 0.52 487.8 5.57 ; + RECT 487.47 384.61 487.83 385.34 ; + RECT 488.04 384.61 488.24 385.34 ; + RECT 488.05 0.3 488.31 5.235 ; + RECT 488.56 0.52 488.82 7.78 ; + RECT 488.695 384.61 488.895 385.34 ; + RECT 489.105 384.61 489.465 385.34 ; + RECT 489.41 0.52 489.67 4.315 ; + RECT 489.675 384.61 489.875 385.34 ; + RECT 490.33 384.61 490.53 385.34 ; + RECT 490.585 0.52 490.845 2.82 ; + RECT 490.74 384.61 491.1 385.34 ; + RECT 491.395 384.61 491.595 385.34 ; + RECT 491.89 384.61 492.25 385.34 ; + RECT 492.825 0.18 493.595 0.88 ; + RECT 492.825 0.18 493.085 12.9 ; + RECT 493.335 0.18 493.595 12.9 ; + RECT 492.115 0.52 492.375 2.82 ; + RECT 492.46 384.61 492.66 385.34 ; + RECT 493.845 0.155 494.615 0.445 ; + RECT 493.845 0.155 494.105 13.21 ; + RECT 494.355 0.155 494.615 13.21 ; + RECT 493.115 384.61 493.315 385.34 ; + RECT 493.525 384.61 493.885 385.34 ; + RECT 494.095 384.61 494.295 385.34 ; + RECT 494.75 384.61 494.95 385.34 ; + RECT 495.16 384.61 495.52 385.34 ; + RECT 495.815 384.61 496.015 385.34 ; + RECT 496.31 384.61 496.67 385.34 ; + RECT 496.55 0.52 496.81 14.115 ; + RECT 496.88 384.61 497.08 385.34 ; + RECT 497.06 0.52 497.32 13.45 ; + RECT 497.535 384.61 497.735 385.34 ; + RECT 498.08 0.155 498.85 0.445 ; + RECT 498.08 0.155 498.34 8.665 ; + RECT 498.59 0.155 498.85 8.665 ; + RECT 497.57 0.52 497.83 11.315 ; + RECT 497.945 384.61 498.305 385.34 ; + RECT 498.515 384.61 498.715 385.34 ; + RECT 499.1 0.52 499.36 9.955 ; + RECT 499.17 384.61 499.37 385.34 ; + RECT 499.58 384.61 499.94 385.34 ; + RECT 500.235 384.61 500.435 385.34 ; + RECT 500.73 384.61 501.09 385.34 ; + RECT 501.14 0.3 501.4 8.7 ; + RECT 501.3 384.61 501.5 385.34 ; + RECT 501.955 384.61 502.155 385.34 ; + RECT 501.65 0.18 502.42 0.88 ; + RECT 502.365 384.61 502.725 385.34 ; + RECT 502.935 384.61 503.135 385.34 ; + RECT 503.59 384.61 503.79 385.34 ; + RECT 503.845 0.52 504.105 6.28 ; + RECT 504 384.61 504.36 385.34 ; + RECT 504.655 384.61 504.855 385.34 ; + RECT 505.22 0.52 505.48 5.57 ; + RECT 505.15 384.61 505.51 385.34 ; + RECT 505.72 384.61 505.92 385.34 ; + RECT 505.73 0.3 505.99 5.235 ; + RECT 506.24 0.52 506.5 7.78 ; + RECT 506.375 384.61 506.575 385.34 ; + RECT 506.785 384.61 507.145 385.34 ; + RECT 507.09 0.52 507.35 4.315 ; + RECT 507.355 384.61 507.555 385.34 ; + RECT 508.01 384.61 508.21 385.34 ; + RECT 508.265 0.52 508.525 2.82 ; + RECT 508.42 384.61 508.78 385.34 ; + RECT 509.075 384.61 509.275 385.34 ; + RECT 509.57 384.61 509.93 385.34 ; + RECT 510.505 0.18 511.275 0.88 ; + RECT 510.505 0.18 510.765 12.9 ; + RECT 511.015 0.18 511.275 12.9 ; + RECT 509.795 0.52 510.055 2.82 ; + RECT 510.14 384.61 510.34 385.34 ; + RECT 511.525 0.155 512.295 0.445 ; + RECT 511.525 0.155 511.785 13.21 ; + RECT 512.035 0.155 512.295 13.21 ; + RECT 510.795 384.61 510.995 385.34 ; + RECT 511.205 384.61 511.565 385.34 ; + RECT 511.775 384.61 511.975 385.34 ; + RECT 512.43 384.61 512.63 385.34 ; + RECT 512.84 384.61 513.2 385.34 ; + RECT 513.495 384.61 513.695 385.34 ; + RECT 513.99 384.61 514.35 385.34 ; + RECT 514.23 0.52 514.49 14.115 ; + RECT 514.56 384.61 514.76 385.34 ; + RECT 514.74 0.52 515 13.45 ; + RECT 515.215 384.61 515.415 385.34 ; + RECT 515.76 0.155 516.53 0.445 ; + RECT 515.76 0.155 516.02 8.665 ; + RECT 516.27 0.155 516.53 8.665 ; + RECT 515.25 0.52 515.51 11.315 ; + RECT 515.625 384.61 515.985 385.34 ; + RECT 516.195 384.61 516.395 385.34 ; + RECT 516.78 0.52 517.04 9.955 ; + RECT 516.85 384.61 517.05 385.34 ; + RECT 517.26 384.61 517.62 385.34 ; + RECT 517.915 384.61 518.115 385.34 ; + RECT 518.41 384.61 518.77 385.34 ; + RECT 518.82 0.3 519.08 8.7 ; + RECT 518.98 384.61 519.18 385.34 ; + RECT 519.635 384.61 519.835 385.34 ; + RECT 519.33 0.18 520.1 0.88 ; + RECT 520.045 384.61 520.405 385.34 ; + RECT 520.615 384.61 520.815 385.34 ; + RECT 521.27 384.61 521.47 385.34 ; + RECT 521.525 0.52 521.785 6.28 ; + RECT 521.68 384.61 522.04 385.34 ; + RECT 522.335 384.61 522.535 385.34 ; + RECT 522.9 0.52 523.16 5.57 ; + RECT 522.83 384.61 523.19 385.34 ; + RECT 523.4 384.61 523.6 385.34 ; + RECT 523.41 0.3 523.67 5.235 ; + RECT 523.92 0.52 524.18 7.78 ; + RECT 524.055 384.61 524.255 385.34 ; + RECT 524.465 384.61 524.825 385.34 ; + RECT 524.77 0.52 525.03 4.315 ; + RECT 525.035 384.61 525.235 385.34 ; + RECT 525.69 384.61 525.89 385.34 ; + RECT 525.945 0.52 526.205 2.82 ; + RECT 526.1 384.61 526.46 385.34 ; + RECT 526.755 384.61 526.955 385.34 ; + RECT 527.25 384.61 527.61 385.34 ; + RECT 528.185 0.18 528.955 0.88 ; + RECT 528.185 0.18 528.445 12.9 ; + RECT 528.695 0.18 528.955 12.9 ; + RECT 527.475 0.52 527.735 2.82 ; + RECT 527.82 384.61 528.02 385.34 ; + RECT 529.205 0.155 529.975 0.445 ; + RECT 529.205 0.155 529.465 13.21 ; + RECT 529.715 0.155 529.975 13.21 ; + RECT 528.475 384.61 528.675 385.34 ; + RECT 528.885 384.61 529.245 385.34 ; + RECT 529.455 384.61 529.655 385.34 ; + RECT 530.11 384.61 530.31 385.34 ; + RECT 530.52 384.61 530.88 385.34 ; + RECT 531.175 384.61 531.375 385.34 ; + RECT 531.67 384.61 532.03 385.34 ; + RECT 531.91 0.52 532.17 14.115 ; + RECT 532.24 384.61 532.44 385.34 ; + RECT 532.42 0.52 532.68 13.45 ; + RECT 532.895 384.61 533.095 385.34 ; + RECT 533.44 0.155 534.21 0.445 ; + RECT 533.44 0.155 533.7 8.665 ; + RECT 533.95 0.155 534.21 8.665 ; + RECT 532.93 0.52 533.19 11.315 ; + RECT 533.305 384.61 533.665 385.34 ; + RECT 533.875 384.61 534.075 385.34 ; + RECT 534.46 0.52 534.72 9.955 ; + RECT 534.53 384.61 534.73 385.34 ; + RECT 534.94 384.61 535.3 385.34 ; + RECT 535.595 384.61 535.795 385.34 ; + RECT 536.09 384.61 536.45 385.34 ; + RECT 536.5 0.3 536.76 8.7 ; + RECT 536.66 384.61 536.86 385.34 ; + RECT 537.315 384.61 537.515 385.34 ; + RECT 537.01 0.18 537.78 0.88 ; + RECT 537.725 384.61 538.085 385.34 ; + RECT 538.295 384.61 538.495 385.34 ; + RECT 538.95 384.61 539.15 385.34 ; + RECT 539.205 0.52 539.465 6.28 ; + RECT 539.36 384.61 539.72 385.34 ; + RECT 540.015 384.61 540.215 385.34 ; + RECT 540.58 0.52 540.84 5.57 ; + RECT 540.51 384.61 540.87 385.34 ; + RECT 541.08 384.61 541.28 385.34 ; + RECT 541.09 0.3 541.35 5.235 ; + RECT 541.6 0.52 541.86 7.78 ; + RECT 541.735 384.61 541.935 385.34 ; + RECT 542.145 384.61 542.505 385.34 ; + RECT 542.45 0.52 542.71 4.315 ; + RECT 542.715 384.61 542.915 385.34 ; + RECT 543.37 384.61 543.57 385.34 ; + RECT 543.625 0.52 543.885 2.82 ; + RECT 543.78 384.61 544.14 385.34 ; + RECT 544.435 384.61 544.635 385.34 ; + RECT 544.93 384.61 545.29 385.34 ; + RECT 545.865 0.18 546.635 0.88 ; + RECT 545.865 0.18 546.125 12.9 ; + RECT 546.375 0.18 546.635 12.9 ; + RECT 545.155 0.52 545.415 2.82 ; + RECT 545.5 384.61 545.7 385.34 ; + RECT 546.885 0.155 547.655 0.445 ; + RECT 546.885 0.155 547.145 13.21 ; + RECT 547.395 0.155 547.655 13.21 ; + RECT 546.155 384.61 546.355 385.34 ; + RECT 546.565 384.61 546.925 385.34 ; + RECT 547.135 384.61 547.335 385.34 ; + RECT 547.79 384.61 547.99 385.34 ; + RECT 548.2 384.61 548.56 385.34 ; + RECT 548.855 384.61 549.055 385.34 ; + RECT 549.35 384.61 549.71 385.34 ; + RECT 549.59 0.52 549.85 14.115 ; + RECT 549.92 384.61 550.12 385.34 ; + RECT 550.1 0.52 550.36 13.45 ; + RECT 550.575 384.61 550.775 385.34 ; + RECT 551.12 0.155 551.89 0.445 ; + RECT 551.12 0.155 551.38 8.665 ; + RECT 551.63 0.155 551.89 8.665 ; + RECT 550.61 0.52 550.87 11.315 ; + RECT 550.985 384.61 551.345 385.34 ; + RECT 551.555 384.61 551.755 385.34 ; + RECT 552.14 0.52 552.4 9.955 ; + RECT 552.21 384.61 552.41 385.34 ; + RECT 552.62 384.61 552.98 385.34 ; + RECT 553.275 384.61 553.475 385.34 ; + RECT 553.77 384.61 554.13 385.34 ; + RECT 554.18 0.3 554.44 8.7 ; + RECT 554.34 384.61 554.54 385.34 ; + RECT 554.995 384.61 555.195 385.34 ; + RECT 554.69 0.18 555.46 0.88 ; + RECT 555.405 384.61 555.765 385.34 ; + RECT 555.975 384.61 556.175 385.34 ; + RECT 556.63 384.61 556.83 385.34 ; + RECT 556.885 0.52 557.145 6.28 ; + RECT 557.04 384.61 557.4 385.34 ; + RECT 557.695 384.61 557.895 385.34 ; + RECT 558.26 0.52 558.52 5.57 ; + RECT 558.19 384.61 558.55 385.34 ; + RECT 558.76 384.61 558.96 385.34 ; + RECT 558.77 0.3 559.03 5.235 ; + RECT 559.28 0.52 559.54 7.78 ; + RECT 559.415 384.61 559.615 385.34 ; + RECT 559.825 384.61 560.185 385.34 ; + RECT 560.13 0.52 560.39 4.315 ; + RECT 560.395 384.61 560.595 385.34 ; + RECT 561.05 384.61 561.25 385.34 ; + RECT 561.305 0.52 561.565 2.82 ; + RECT 561.46 384.61 561.82 385.34 ; + RECT 562.115 384.61 562.315 385.34 ; + RECT 562.61 384.61 562.97 385.34 ; + RECT 563.545 0.18 564.315 0.88 ; + RECT 563.545 0.18 563.805 12.9 ; + RECT 564.055 0.18 564.315 12.9 ; + RECT 562.835 0.52 563.095 2.82 ; + RECT 563.18 384.61 563.38 385.34 ; + RECT 564.565 0.155 565.335 0.445 ; + RECT 564.565 0.155 564.825 13.21 ; + RECT 565.075 0.155 565.335 13.21 ; + RECT 563.835 384.61 564.035 385.34 ; + RECT 564.245 384.61 564.605 385.34 ; + RECT 564.815 384.61 565.015 385.34 ; + RECT 565.47 384.61 565.67 385.34 ; + RECT 565.88 384.61 566.24 385.34 ; + RECT 566.535 384.61 566.735 385.34 ; + RECT 567.03 384.61 567.39 385.34 ; + RECT 567.27 0.52 567.53 14.115 ; + RECT 567.6 384.61 567.8 385.34 ; + RECT 567.78 0.52 568.04 13.45 ; + RECT 568.255 384.61 568.455 385.34 ; + RECT 568.8 0.155 569.57 0.445 ; + RECT 568.8 0.155 569.06 8.665 ; + RECT 569.31 0.155 569.57 8.665 ; + RECT 568.29 0.52 568.55 11.315 ; + RECT 568.665 384.61 569.025 385.34 ; + RECT 569.235 384.61 569.435 385.34 ; + RECT 569.82 0.52 570.08 9.955 ; + RECT 569.89 384.61 570.09 385.34 ; + RECT 570.3 384.61 570.66 385.34 ; + RECT 570.955 384.61 571.155 385.34 ; + RECT 571.45 384.61 571.81 385.34 ; + RECT 571.86 0.3 572.12 8.7 ; + RECT 572.02 384.61 572.22 385.34 ; + RECT 572.675 384.61 572.875 385.34 ; + RECT 572.37 0.18 573.14 0.88 ; + RECT 573.085 384.61 573.445 385.34 ; + RECT 573.655 384.61 573.855 385.34 ; + RECT 574.31 384.61 574.51 385.34 ; + RECT 574.565 0.52 574.825 6.28 ; + RECT 574.72 384.61 575.08 385.34 ; + RECT 575.375 384.61 575.575 385.34 ; + RECT 575.94 0.52 576.2 5.57 ; + RECT 575.87 384.61 576.23 385.34 ; + RECT 576.44 384.61 576.64 385.34 ; + RECT 576.45 0.3 576.71 5.235 ; + RECT 576.96 0.52 577.22 7.78 ; + RECT 577.095 384.61 577.295 385.34 ; + RECT 577.505 384.61 577.865 385.34 ; + RECT 577.81 0.52 578.07 4.315 ; + RECT 578.075 384.61 578.275 385.34 ; + RECT 578.73 384.61 578.93 385.34 ; + RECT 578.985 0.52 579.245 2.82 ; + RECT 579.14 384.61 579.5 385.34 ; + RECT 579.795 384.61 579.995 385.34 ; + RECT 580.29 384.61 580.65 385.34 ; + RECT 581.225 0.18 581.995 0.88 ; + RECT 581.225 0.18 581.485 12.9 ; + RECT 581.735 0.18 581.995 12.9 ; + RECT 580.515 0.52 580.775 2.82 ; + RECT 580.86 384.61 581.06 385.34 ; + RECT 582.245 0.155 583.015 0.445 ; + RECT 582.245 0.155 582.505 13.21 ; + RECT 582.755 0.155 583.015 13.21 ; + RECT 581.515 384.61 581.715 385.34 ; + RECT 581.925 384.61 582.285 385.34 ; + RECT 582.495 384.61 582.695 385.34 ; + RECT 583.15 384.61 583.35 385.34 ; + RECT 583.56 384.61 583.92 385.34 ; + RECT 584.215 384.61 584.415 385.34 ; + RECT 584.71 384.61 585.07 385.34 ; + RECT 584.95 0.52 585.21 14.115 ; + RECT 585.28 384.61 585.48 385.34 ; + RECT 585.46 0.52 585.72 13.45 ; + RECT 585.935 384.61 586.135 385.34 ; + RECT 586.48 0.155 587.25 0.445 ; + RECT 586.48 0.155 586.74 8.665 ; + RECT 586.99 0.155 587.25 8.665 ; + RECT 585.97 0.52 586.23 11.315 ; + RECT 586.345 384.61 586.705 385.34 ; + RECT 586.915 384.61 587.115 385.34 ; + RECT 587.5 0.52 587.76 9.955 ; + RECT 587.57 384.61 587.77 385.34 ; + RECT 587.98 384.61 588.34 385.34 ; + RECT 588.635 384.61 588.835 385.34 ; + RECT 589.13 384.61 589.49 385.34 ; + RECT 589.54 0.3 589.8 8.7 ; + RECT 589.7 384.61 589.9 385.34 ; + RECT 590.355 384.61 590.555 385.34 ; + RECT 590.05 0.18 590.82 0.88 ; + RECT 590.765 384.61 591.125 385.34 ; + RECT 591.335 384.61 591.535 385.34 ; + RECT 591.99 384.61 592.19 385.34 ; + RECT 592.245 0.52 592.505 6.28 ; + RECT 592.4 384.61 592.76 385.34 ; + RECT 593.055 384.61 593.255 385.34 ; + RECT 593.62 0.52 593.88 5.57 ; + RECT 593.55 384.61 593.91 385.34 ; + RECT 594.12 384.61 594.32 385.34 ; + RECT 594.13 0.3 594.39 5.235 ; + RECT 594.64 0.52 594.9 7.78 ; + RECT 594.775 384.61 594.975 385.34 ; + RECT 595.185 384.61 595.545 385.34 ; + RECT 595.49 0.52 595.75 4.315 ; + RECT 595.755 384.61 595.955 385.34 ; + RECT 596.41 384.61 596.61 385.34 ; + RECT 596.665 0.52 596.925 2.82 ; + RECT 596.82 384.61 597.18 385.34 ; + RECT 597.475 384.61 597.675 385.34 ; + RECT 597.97 384.61 598.33 385.34 ; + RECT 598.905 0.18 599.675 0.88 ; + RECT 598.905 0.18 599.165 12.9 ; + RECT 599.415 0.18 599.675 12.9 ; + RECT 598.195 0.52 598.455 2.82 ; + RECT 598.54 384.61 598.74 385.34 ; + RECT 599.925 0.155 600.695 0.445 ; + RECT 599.925 0.155 600.185 13.21 ; + RECT 600.435 0.155 600.695 13.21 ; + RECT 599.195 384.61 599.395 385.34 ; + RECT 599.605 384.61 599.965 385.34 ; + RECT 600.175 384.61 600.375 385.34 ; + RECT 600.83 384.61 601.03 385.34 ; + RECT 601.24 384.61 601.6 385.34 ; + RECT 601.895 384.61 602.095 385.34 ; + RECT 602.39 384.61 602.75 385.34 ; + RECT 602.63 0.52 602.89 14.115 ; + RECT 602.96 384.61 603.16 385.34 ; + RECT 603.14 0.52 603.4 13.45 ; + RECT 603.615 384.61 603.815 385.34 ; + RECT 604.16 0.155 604.93 0.445 ; + RECT 604.16 0.155 604.42 8.665 ; + RECT 604.67 0.155 604.93 8.665 ; + RECT 603.65 0.52 603.91 11.315 ; + RECT 604.025 384.61 604.385 385.34 ; + RECT 604.595 384.61 604.795 385.34 ; + RECT 605.18 0.52 605.44 9.955 ; + RECT 605.25 384.61 605.45 385.34 ; + RECT 605.66 384.61 606.02 385.34 ; + RECT 606.315 384.61 606.515 385.34 ; + RECT 606.81 384.61 607.17 385.34 ; + RECT 607.22 0.3 607.48 8.7 ; + RECT 607.38 384.61 607.58 385.34 ; + RECT 608.035 384.61 608.235 385.34 ; + RECT 607.73 0.18 608.5 0.88 ; + RECT 608.445 384.61 608.805 385.34 ; + RECT 609.015 384.61 609.215 385.34 ; + RECT 609.67 384.61 609.87 385.34 ; + RECT 609.925 0.52 610.185 6.28 ; + RECT 610.08 384.61 610.44 385.34 ; + RECT 610.735 384.61 610.935 385.34 ; + RECT 611.3 0.52 611.56 5.57 ; + RECT 611.23 384.61 611.59 385.34 ; + RECT 611.8 384.61 612 385.34 ; + RECT 611.81 0.3 612.07 5.235 ; + RECT 612.32 0.52 612.58 7.78 ; + RECT 612.455 384.61 612.655 385.34 ; + RECT 612.865 384.61 613.225 385.34 ; + RECT 613.17 0.52 613.43 4.315 ; + RECT 613.435 384.61 613.635 385.34 ; + RECT 614.09 384.61 614.29 385.34 ; + RECT 614.345 0.52 614.605 2.82 ; + RECT 614.5 384.61 614.86 385.34 ; + RECT 615.155 384.61 615.355 385.34 ; + RECT 615.65 384.61 616.01 385.34 ; + RECT 616.585 0.18 617.355 0.88 ; + RECT 616.585 0.18 616.845 12.9 ; + RECT 617.095 0.18 617.355 12.9 ; + RECT 615.875 0.52 616.135 2.82 ; + RECT 616.22 384.61 616.42 385.34 ; + RECT 617.605 0.155 618.375 0.445 ; + RECT 617.605 0.155 617.865 13.21 ; + RECT 618.115 0.155 618.375 13.21 ; + RECT 616.875 384.61 617.075 385.34 ; + RECT 617.285 384.61 617.645 385.34 ; + RECT 617.855 384.61 618.055 385.34 ; + RECT 618.51 384.61 618.71 385.34 ; + RECT 618.92 384.61 619.28 385.34 ; + RECT 619.575 384.61 619.775 385.34 ; + RECT 620.07 384.61 620.43 385.34 ; + RECT 620.31 0.52 620.57 14.115 ; + RECT 620.64 384.61 620.84 385.34 ; + RECT 620.82 0.52 621.08 13.45 ; + RECT 621.295 384.61 621.495 385.34 ; + RECT 621.84 0.155 622.61 0.445 ; + RECT 621.84 0.155 622.1 8.665 ; + RECT 622.35 0.155 622.61 8.665 ; + RECT 621.33 0.52 621.59 11.315 ; + RECT 621.705 384.61 622.065 385.34 ; + RECT 622.275 384.61 622.475 385.34 ; + RECT 622.86 0.52 623.12 9.955 ; + RECT 622.93 384.61 623.13 385.34 ; + RECT 623.34 384.61 623.7 385.34 ; + RECT 623.995 384.61 624.195 385.34 ; + RECT 624.49 384.61 624.85 385.34 ; + RECT 624.9 0.3 625.16 8.7 ; + RECT 625.06 384.61 625.26 385.34 ; + RECT 625.715 384.61 625.915 385.34 ; + RECT 625.41 0.18 626.18 0.88 ; + RECT 626.125 384.61 626.485 385.34 ; + RECT 626.695 384.61 626.895 385.34 ; + RECT 627.35 384.61 627.55 385.34 ; + RECT 627.605 0.52 627.865 6.28 ; + RECT 627.76 384.61 628.12 385.34 ; + RECT 628.415 384.61 628.615 385.34 ; + RECT 628.98 0.52 629.24 5.57 ; + RECT 628.91 384.61 629.27 385.34 ; + RECT 629.48 384.61 629.68 385.34 ; + RECT 629.49 0.3 629.75 5.235 ; + RECT 630 0.52 630.26 7.78 ; + RECT 630.135 384.61 630.335 385.34 ; + RECT 630.545 384.61 630.905 385.34 ; + RECT 630.85 0.52 631.11 4.315 ; + RECT 631.115 384.61 631.315 385.34 ; + RECT 631.77 384.61 631.97 385.34 ; + RECT 632.025 0.52 632.285 2.82 ; + RECT 632.18 384.61 632.54 385.34 ; + RECT 632.835 384.61 633.035 385.34 ; + RECT 633.33 384.61 633.69 385.34 ; + RECT 634.265 0.18 635.035 0.88 ; + RECT 634.265 0.18 634.525 12.9 ; + RECT 634.775 0.18 635.035 12.9 ; + RECT 633.555 0.52 633.815 2.82 ; + RECT 633.9 384.61 634.1 385.34 ; + RECT 635.285 0.155 636.055 0.445 ; + RECT 635.285 0.155 635.545 13.21 ; + RECT 635.795 0.155 636.055 13.21 ; + RECT 634.555 384.61 634.755 385.34 ; + RECT 634.965 384.61 635.325 385.34 ; + RECT 635.535 384.61 635.735 385.34 ; + RECT 636.19 384.61 636.39 385.34 ; + RECT 636.6 384.61 636.96 385.34 ; + RECT 637.255 384.61 637.455 385.34 ; + RECT 637.75 384.61 638.11 385.34 ; + RECT 637.99 0.52 638.25 14.115 ; + RECT 638.32 384.61 638.52 385.34 ; + RECT 638.5 0.52 638.76 13.45 ; + RECT 638.975 384.61 639.175 385.34 ; + RECT 639.52 0.155 640.29 0.445 ; + RECT 639.52 0.155 639.78 8.665 ; + RECT 640.03 0.155 640.29 8.665 ; + RECT 639.01 0.52 639.27 11.315 ; + RECT 639.385 384.61 639.745 385.34 ; + RECT 639.955 384.61 640.155 385.34 ; + RECT 640.54 0.52 640.8 9.955 ; + RECT 640.61 384.61 640.81 385.34 ; + RECT 641.02 384.61 641.38 385.34 ; + RECT 641.675 384.61 641.875 385.34 ; + RECT 642.17 384.61 642.53 385.34 ; + RECT 642.58 0.3 642.84 8.7 ; + RECT 642.74 384.61 642.94 385.34 ; + RECT 643.395 384.61 643.595 385.34 ; + RECT 643.09 0.18 643.86 0.88 ; + RECT 643.805 384.61 644.165 385.34 ; + RECT 644.375 384.61 644.575 385.34 ; + RECT 645.03 384.61 645.23 385.34 ; + RECT 645.285 0.52 645.545 6.28 ; + RECT 645.44 384.61 645.8 385.34 ; + RECT 646.095 384.61 646.295 385.34 ; + RECT 646.66 0.52 646.92 5.57 ; + RECT 646.59 384.61 646.95 385.34 ; + RECT 647.16 384.61 647.36 385.34 ; + RECT 647.17 0.3 647.43 5.235 ; + RECT 647.68 0.52 647.94 7.78 ; + RECT 647.815 384.61 648.015 385.34 ; + RECT 648.225 384.61 648.585 385.34 ; + RECT 648.53 0.52 648.79 4.315 ; + RECT 648.795 384.61 648.995 385.34 ; + RECT 649.45 384.61 649.65 385.34 ; + RECT 649.705 0.52 649.965 2.82 ; + RECT 649.86 384.61 650.22 385.34 ; + RECT 650.515 384.61 650.715 385.34 ; + RECT 651.01 384.61 651.37 385.34 ; + RECT 651.945 0.18 652.715 0.88 ; + RECT 651.945 0.18 652.205 12.9 ; + RECT 652.455 0.18 652.715 12.9 ; + RECT 651.235 0.52 651.495 2.82 ; + RECT 651.58 384.61 651.78 385.34 ; + RECT 652.965 0.155 653.735 0.445 ; + RECT 652.965 0.155 653.225 13.21 ; + RECT 653.475 0.155 653.735 13.21 ; + RECT 652.235 384.61 652.435 385.34 ; + RECT 652.645 384.61 653.005 385.34 ; + RECT 653.215 384.61 653.415 385.34 ; + RECT 653.87 384.61 654.07 385.34 ; + RECT 654.28 384.61 654.64 385.34 ; + RECT 654.935 384.61 655.135 385.34 ; + RECT 655.43 384.61 655.79 385.34 ; + RECT 655.67 0.52 655.93 14.115 ; + RECT 656 384.61 656.2 385.34 ; + RECT 656.18 0.52 656.44 13.45 ; + RECT 656.655 384.61 656.855 385.34 ; + RECT 657.2 0.155 657.97 0.445 ; + RECT 657.2 0.155 657.46 8.665 ; + RECT 657.71 0.155 657.97 8.665 ; + RECT 656.69 0.52 656.95 11.315 ; + RECT 657.065 384.61 657.425 385.34 ; + RECT 657.635 384.61 657.835 385.34 ; + RECT 658.22 0.52 658.48 9.955 ; + RECT 658.29 384.61 658.49 385.34 ; + RECT 658.7 384.61 659.06 385.34 ; + RECT 659.355 384.61 659.555 385.34 ; + RECT 659.85 384.61 660.21 385.34 ; + RECT 660.26 0.3 660.52 8.7 ; + RECT 660.42 384.61 660.62 385.34 ; + RECT 661.075 384.61 661.275 385.34 ; + RECT 660.77 0.18 661.54 0.88 ; + RECT 661.485 384.61 661.845 385.34 ; + RECT 662.055 384.61 662.255 385.34 ; + RECT 662.71 384.61 662.91 385.34 ; + RECT 662.965 0.52 663.225 6.28 ; + RECT 663.12 384.61 663.48 385.34 ; + RECT 663.775 384.61 663.975 385.34 ; + RECT 664.34 0.52 664.6 5.57 ; + RECT 664.27 384.61 664.63 385.34 ; + RECT 664.84 384.61 665.04 385.34 ; + RECT 664.85 0.3 665.11 5.235 ; + RECT 665.36 0.52 665.62 7.78 ; + RECT 665.495 384.61 665.695 385.34 ; + RECT 665.905 384.61 666.265 385.34 ; + RECT 666.21 0.52 666.47 4.315 ; + RECT 666.475 384.61 666.675 385.34 ; + RECT 667.13 384.61 667.33 385.34 ; + RECT 667.385 0.52 667.645 2.82 ; + RECT 667.54 384.61 667.9 385.34 ; + RECT 668.195 384.61 668.395 385.34 ; + RECT 668.69 384.61 669.05 385.34 ; + RECT 669.625 0.18 670.395 0.88 ; + RECT 669.625 0.18 669.885 12.9 ; + RECT 670.135 0.18 670.395 12.9 ; + RECT 668.915 0.52 669.175 2.82 ; + RECT 669.26 384.61 669.46 385.34 ; + RECT 670.645 0.155 671.415 0.445 ; + RECT 670.645 0.155 670.905 13.21 ; + RECT 671.155 0.155 671.415 13.21 ; + RECT 669.915 384.61 670.115 385.34 ; + RECT 670.325 384.61 670.685 385.34 ; + RECT 670.895 384.61 671.095 385.34 ; + RECT 671.55 384.61 671.75 385.34 ; + RECT 671.96 384.61 672.32 385.34 ; + RECT 672.615 384.61 672.815 385.34 ; + RECT 673.11 384.61 673.47 385.34 ; + RECT 673.35 0.52 673.61 14.115 ; + RECT 673.68 384.61 673.88 385.34 ; + RECT 673.86 0.52 674.12 13.45 ; + RECT 674.335 384.61 674.535 385.34 ; + RECT 674.88 0.155 675.65 0.445 ; + RECT 674.88 0.155 675.14 8.665 ; + RECT 675.39 0.155 675.65 8.665 ; + RECT 674.37 0.52 674.63 11.315 ; + RECT 674.745 384.61 675.105 385.34 ; + RECT 675.315 384.61 675.515 385.34 ; + RECT 675.9 0.52 676.16 9.955 ; + RECT 675.97 384.61 676.17 385.34 ; + RECT 676.38 384.61 676.74 385.34 ; + RECT 677.035 384.61 677.235 385.34 ; + RECT 677.53 384.61 677.89 385.34 ; + RECT 677.94 0.3 678.2 8.7 ; + RECT 678.1 384.61 678.3 385.34 ; + RECT 678.755 384.61 678.955 385.34 ; + RECT 678.45 0.18 679.22 0.88 ; + RECT 679.165 384.61 679.525 385.34 ; + RECT 679.735 384.61 679.935 385.34 ; + RECT 680.39 384.61 680.59 385.34 ; + RECT 680.645 0.52 680.905 6.28 ; + RECT 680.8 384.61 681.16 385.34 ; + RECT 681.455 384.61 681.655 385.34 ; + RECT 682.02 0.52 682.28 5.57 ; + RECT 681.95 384.61 682.31 385.34 ; + RECT 682.52 384.61 682.72 385.34 ; + RECT 682.53 0.3 682.79 5.235 ; + RECT 683.04 0.52 683.3 7.78 ; + RECT 683.175 384.61 683.375 385.34 ; + RECT 683.585 384.61 683.945 385.34 ; + RECT 684.155 384.61 684.355 385.34 ; + RECT 684.98 53.41 685.18 385.34 ; + LAYER Metal2 SPACING 0.21 ; + RECT 681.165 0 681.76 385.37 ; + RECT 682.53 0.3 682.79 385.37 ; + RECT 683.56 0 685.49 385.37 ; + RECT 0 0.52 685.49 385.37 ; + RECT 676.42 0 680.385 385.37 ; + RECT 674.88 0.155 675.65 385.37 ; + RECT 669.435 0 673.09 385.37 ; + RECT 667.905 0 668.655 385.37 ; + RECT 666.73 0 667.125 385.37 ; + RECT 664.85 0.3 665.11 385.37 ; + RECT 663.485 0 664.08 385.37 ; + RECT 658.74 0 662.705 385.37 ; + RECT 657.2 0.155 657.97 385.37 ; + RECT 651.755 0 655.41 385.37 ; + RECT 650.225 0 650.975 385.37 ; + RECT 649.05 0 649.445 385.37 ; + RECT 647.17 0.3 647.43 385.37 ; + RECT 645.805 0 646.4 385.37 ; + RECT 641.06 0 645.025 385.37 ; + RECT 639.52 0.155 640.29 385.37 ; + RECT 634.075 0 637.73 385.37 ; + RECT 632.545 0 633.295 385.37 ; + RECT 631.37 0 631.765 385.37 ; + RECT 629.49 0.3 629.75 385.37 ; + RECT 628.125 0 628.72 385.37 ; + RECT 623.38 0 627.345 385.37 ; + RECT 621.84 0.155 622.61 385.37 ; + RECT 616.395 0 620.05 385.37 ; + RECT 614.865 0 615.615 385.37 ; + RECT 613.69 0 614.085 385.37 ; + RECT 611.81 0.3 612.07 385.37 ; + RECT 610.445 0 611.04 385.37 ; + RECT 605.7 0 609.665 385.37 ; + RECT 604.16 0.155 604.93 385.37 ; + RECT 598.715 0 602.37 385.37 ; + RECT 597.185 0 597.935 385.37 ; + RECT 596.01 0 596.405 385.37 ; + RECT 594.13 0.3 594.39 385.37 ; + RECT 592.765 0 593.36 385.37 ; + RECT 588.02 0 591.985 385.37 ; + RECT 586.48 0.155 587.25 385.37 ; + RECT 581.035 0 584.69 385.37 ; + RECT 579.505 0 580.255 385.37 ; + RECT 578.33 0 578.725 385.37 ; + RECT 576.45 0.3 576.71 385.37 ; + RECT 575.085 0 575.68 385.37 ; + RECT 570.34 0 574.305 385.37 ; + RECT 568.8 0.155 569.57 385.37 ; + RECT 563.355 0 567.01 385.37 ; + RECT 561.825 0 562.575 385.37 ; + RECT 560.65 0 561.045 385.37 ; + RECT 558.77 0.3 559.03 385.37 ; + RECT 557.405 0 558 385.37 ; + RECT 552.66 0 556.625 385.37 ; + RECT 551.12 0.155 551.89 385.37 ; + RECT 545.675 0 549.33 385.37 ; + RECT 544.145 0 544.895 385.37 ; + RECT 542.97 0 543.365 385.37 ; + RECT 541.09 0.3 541.35 385.37 ; + RECT 539.725 0 540.32 385.37 ; + RECT 534.98 0 538.945 385.37 ; + RECT 533.44 0.155 534.21 385.37 ; + RECT 527.995 0 531.65 385.37 ; + RECT 526.465 0 527.215 385.37 ; + RECT 525.29 0 525.685 385.37 ; + RECT 523.41 0.3 523.67 385.37 ; + RECT 522.045 0 522.64 385.37 ; + RECT 517.3 0 521.265 385.37 ; + RECT 515.76 0.155 516.53 385.37 ; + RECT 510.315 0 513.97 385.37 ; + RECT 508.785 0 509.535 385.37 ; + RECT 507.61 0 508.005 385.37 ; + RECT 505.73 0.3 505.99 385.37 ; + RECT 504.365 0 504.96 385.37 ; + RECT 499.62 0 503.585 385.37 ; + RECT 498.08 0.155 498.85 385.37 ; + RECT 492.635 0 496.29 385.37 ; + RECT 491.105 0 491.855 385.37 ; + RECT 489.93 0 490.325 385.37 ; + RECT 488.05 0.3 488.31 385.37 ; + RECT 486.685 0 487.28 385.37 ; + RECT 481.94 0 485.905 385.37 ; + RECT 480.4 0.155 481.17 385.37 ; + RECT 474.955 0 478.61 385.37 ; + RECT 473.425 0 474.175 385.37 ; + RECT 472.25 0 472.645 385.37 ; + RECT 470.37 0.3 470.63 385.37 ; + RECT 469.005 0 469.6 385.37 ; + RECT 464.26 0 468.225 385.37 ; + RECT 462.72 0.155 463.49 385.37 ; + RECT 457.275 0 460.93 385.37 ; + RECT 455.745 0 456.495 385.37 ; + RECT 454.57 0 454.965 385.37 ; + RECT 452.69 0.3 452.95 385.37 ; + RECT 451.325 0 451.92 385.37 ; + RECT 446.58 0 450.545 385.37 ; + RECT 445.04 0.155 445.81 385.37 ; + RECT 439.595 0 443.25 385.37 ; + RECT 438.065 0 438.815 385.37 ; + RECT 436.89 0 437.285 385.37 ; + RECT 435.01 0.3 435.27 385.37 ; + RECT 433.645 0 434.24 385.37 ; + RECT 428.9 0 432.865 385.37 ; + RECT 427.36 0.155 428.13 385.37 ; + RECT 421.915 0 425.57 385.37 ; + RECT 420.385 0 421.135 385.37 ; + RECT 419.21 0 419.605 385.37 ; + RECT 417.33 0.3 417.59 385.37 ; + RECT 415.965 0 416.56 385.37 ; + RECT 411.22 0 415.185 385.37 ; + RECT 409.68 0.155 410.45 385.37 ; + RECT 404.235 0 407.89 385.37 ; + RECT 402.705 0 403.455 385.37 ; + RECT 401.53 0 401.925 385.37 ; + RECT 378.725 0.18 400.75 385.37 ; + RECT 378.735 0 400.75 385.37 ; + RECT 374.135 0.3 377.965 385.37 ; + RECT 372.095 0.18 372.865 385.37 ; + RECT 365.465 0.3 366.745 385.37 ; + RECT 362.915 0.3 364.195 385.37 ; + RECT 361.385 0.3 361.645 385.37 ; + RECT 358.325 0.3 358.585 385.37 ; + RECT 356.795 0.3 357.055 385.37 ; + RECT 348.635 0.3 355.525 385.37 ; + RECT 339.145 0 346.345 385.37 ; + RECT 329.965 0.3 336.855 385.37 ; + RECT 329.975 0 336.855 385.37 ; + RECT 328.435 0.3 328.695 385.37 ; + RECT 326.905 0.3 327.165 385.37 ; + RECT 323.845 0.3 324.105 385.37 ; + RECT 321.295 0.3 322.575 385.37 ; + RECT 318.745 0.3 320.025 385.37 ; + RECT 312.625 0.18 313.395 385.37 ; + RECT 307.525 0.3 311.355 385.37 ; + RECT 284.74 0.18 306.765 385.37 ; + RECT 283.565 0 283.96 385.37 ; + RECT 282.035 0 282.785 385.37 ; + RECT 277.6 0 281.255 385.37 ; + RECT 275.04 0.155 275.81 385.37 ; + RECT 270.305 0 274.27 385.37 ; + RECT 268.93 0 269.525 385.37 ; + RECT 267.9 0.3 268.16 385.37 ; + RECT 265.885 0 266.28 385.37 ; + RECT 264.355 0 265.105 385.37 ; + RECT 259.92 0 263.575 385.37 ; + RECT 257.36 0.155 258.13 385.37 ; + RECT 252.625 0 256.59 385.37 ; + RECT 251.25 0 251.845 385.37 ; + RECT 250.22 0.3 250.48 385.37 ; + RECT 248.205 0 248.6 385.37 ; + RECT 246.675 0 247.425 385.37 ; + RECT 242.24 0 245.895 385.37 ; + RECT 239.68 0.155 240.45 385.37 ; + RECT 234.945 0 238.91 385.37 ; + RECT 233.57 0 234.165 385.37 ; + RECT 232.54 0.3 232.8 385.37 ; + RECT 230.525 0 230.92 385.37 ; + RECT 228.995 0 229.745 385.37 ; + RECT 224.56 0 228.215 385.37 ; + RECT 222 0.155 222.77 385.37 ; + RECT 217.265 0 221.23 385.37 ; + RECT 215.89 0 216.485 385.37 ; + RECT 214.86 0.3 215.12 385.37 ; + RECT 212.845 0 213.24 385.37 ; + RECT 211.315 0 212.065 385.37 ; + RECT 206.88 0 210.535 385.37 ; + RECT 204.32 0.155 205.09 385.37 ; + RECT 199.585 0 203.55 385.37 ; + RECT 198.21 0 198.805 385.37 ; + RECT 197.18 0.3 197.44 385.37 ; + RECT 195.165 0 195.56 385.37 ; + RECT 193.635 0 194.385 385.37 ; + RECT 189.2 0 192.855 385.37 ; + RECT 186.64 0.155 187.41 385.37 ; + RECT 181.905 0 185.87 385.37 ; + RECT 180.53 0 181.125 385.37 ; + RECT 179.5 0.3 179.76 385.37 ; + RECT 177.485 0 177.88 385.37 ; + RECT 175.955 0 176.705 385.37 ; + RECT 171.52 0 175.175 385.37 ; + RECT 168.96 0.155 169.73 385.37 ; + RECT 164.225 0 168.19 385.37 ; + RECT 162.85 0 163.445 385.37 ; + RECT 161.82 0.3 162.08 385.37 ; + RECT 159.805 0 160.2 385.37 ; + RECT 158.275 0 159.025 385.37 ; + RECT 153.84 0 157.495 385.37 ; + RECT 151.28 0.155 152.05 385.37 ; + RECT 146.545 0 150.51 385.37 ; + RECT 145.17 0 145.765 385.37 ; + RECT 144.14 0.3 144.4 385.37 ; + RECT 142.125 0 142.52 385.37 ; + RECT 140.595 0 141.345 385.37 ; + RECT 136.16 0 139.815 385.37 ; + RECT 133.6 0.155 134.37 385.37 ; + RECT 128.865 0 132.83 385.37 ; + RECT 127.49 0 128.085 385.37 ; + RECT 126.46 0.3 126.72 385.37 ; + RECT 124.445 0 124.84 385.37 ; + RECT 122.915 0 123.665 385.37 ; + RECT 118.48 0 122.135 385.37 ; + RECT 115.92 0.155 116.69 385.37 ; + RECT 111.185 0 115.15 385.37 ; + RECT 109.81 0 110.405 385.37 ; + RECT 108.78 0.3 109.04 385.37 ; + RECT 106.765 0 107.16 385.37 ; + RECT 105.235 0 105.985 385.37 ; + RECT 100.8 0 104.455 385.37 ; + RECT 98.24 0.155 99.01 385.37 ; + RECT 93.505 0 97.47 385.37 ; + RECT 92.13 0 92.725 385.37 ; + RECT 91.1 0.3 91.36 385.37 ; + RECT 89.085 0 89.48 385.37 ; + RECT 87.555 0 88.305 385.37 ; + RECT 83.12 0 86.775 385.37 ; + RECT 80.56 0.155 81.33 385.37 ; + RECT 75.825 0 79.79 385.37 ; + RECT 74.45 0 75.045 385.37 ; + RECT 73.42 0.3 73.68 385.37 ; + RECT 71.405 0 71.8 385.37 ; + RECT 69.875 0 70.625 385.37 ; + RECT 65.44 0 69.095 385.37 ; + RECT 62.88 0.155 63.65 385.37 ; + RECT 58.145 0 62.11 385.37 ; + RECT 56.77 0 57.365 385.37 ; + RECT 55.74 0.3 56 385.37 ; + RECT 53.725 0 54.12 385.37 ; + RECT 52.195 0 52.945 385.37 ; + RECT 47.76 0 51.415 385.37 ; + RECT 45.2 0.155 45.97 385.37 ; + RECT 40.465 0 44.43 385.37 ; + RECT 39.09 0 39.685 385.37 ; + RECT 38.06 0.3 38.32 385.37 ; + RECT 36.045 0 36.44 385.37 ; + RECT 34.515 0 35.265 385.37 ; + RECT 30.08 0 33.735 385.37 ; + RECT 27.52 0.155 28.29 385.37 ; + RECT 22.785 0 26.75 385.37 ; + RECT 21.41 0 22.005 385.37 ; + RECT 20.38 0.3 20.64 385.37 ; + RECT 18.365 0 18.76 385.37 ; + RECT 16.835 0 17.585 385.37 ; + RECT 12.4 0 16.055 385.37 ; + RECT 9.84 0.155 10.61 385.37 ; + RECT 5.105 0 9.07 385.37 ; + RECT 3.73 0 4.325 385.37 ; + RECT 2.7 0.3 2.96 385.37 ; + RECT 0 0 1.93 385.37 ; + RECT 682.54 0 682.78 385.37 ; + RECT 664.86 0 665.1 385.37 ; + RECT 647.18 0 647.42 385.37 ; + RECT 629.5 0 629.74 385.37 ; + RECT 611.82 0 612.06 385.37 ; + RECT 594.14 0 594.38 385.37 ; + RECT 576.46 0 576.7 385.37 ; + RECT 558.78 0 559.02 385.37 ; + RECT 541.1 0 541.34 385.37 ; + RECT 523.42 0 523.66 385.37 ; + RECT 505.74 0 505.98 385.37 ; + RECT 488.06 0 488.3 385.37 ; + RECT 470.38 0 470.62 385.37 ; + RECT 452.7 0 452.94 385.37 ; + RECT 435.02 0 435.26 385.37 ; + RECT 417.34 0 417.58 385.37 ; + RECT 374.145 0 377.955 385.37 ; + RECT 365.475 0 366.735 385.37 ; + RECT 362.925 0 364.185 385.37 ; + RECT 361.395 0 361.635 385.37 ; + RECT 358.335 0 358.575 385.37 ; + RECT 356.805 0 357.045 385.37 ; + RECT 348.635 0 355.515 385.37 ; + RECT 328.445 0 328.685 385.37 ; + RECT 326.915 0 327.155 385.37 ; + RECT 323.855 0 324.095 385.37 ; + RECT 321.305 0 322.565 385.37 ; + RECT 318.755 0 320.015 385.37 ; + RECT 307.535 0 311.345 385.37 ; + RECT 267.91 0 268.15 385.37 ; + RECT 250.23 0 250.47 385.37 ; + RECT 232.55 0 232.79 385.37 ; + RECT 214.87 0 215.11 385.37 ; + RECT 197.19 0 197.43 385.37 ; + RECT 179.51 0 179.75 385.37 ; + RECT 161.83 0 162.07 385.37 ; + RECT 144.15 0 144.39 385.37 ; + RECT 126.47 0 126.71 385.37 ; + RECT 108.79 0 109.03 385.37 ; + RECT 91.11 0 91.35 385.37 ; + RECT 73.43 0 73.67 385.37 ; + RECT 55.75 0 55.99 385.37 ; + RECT 38.07 0 38.31 385.37 ; + RECT 20.39 0 20.63 385.37 ; + RECT 2.71 0 2.95 385.37 ; + RECT 372.105 0 372.855 385.37 ; + RECT 312.635 0 313.385 385.37 ; + RECT 284.74 0 306.755 385.37 ; + RECT 674.89 0 675.64 385.37 ; + RECT 657.21 0 657.96 385.37 ; + RECT 639.53 0 640.28 385.37 ; + RECT 621.85 0 622.6 385.37 ; + RECT 604.17 0 604.92 385.37 ; + RECT 586.49 0 587.24 385.37 ; + RECT 568.81 0 569.56 385.37 ; + RECT 551.13 0 551.88 385.37 ; + RECT 533.45 0 534.2 385.37 ; + RECT 515.77 0 516.52 385.37 ; + RECT 498.09 0 498.84 385.37 ; + RECT 480.41 0 481.16 385.37 ; + RECT 462.73 0 463.48 385.37 ; + RECT 445.05 0 445.8 385.37 ; + RECT 427.37 0 428.12 385.37 ; + RECT 409.69 0 410.44 385.37 ; + RECT 275.05 0 275.8 385.37 ; + RECT 257.37 0 258.12 385.37 ; + RECT 239.69 0 240.44 385.37 ; + RECT 222.01 0 222.76 385.37 ; + RECT 204.33 0 205.08 385.37 ; + RECT 186.65 0 187.4 385.37 ; + RECT 168.97 0 169.72 385.37 ; + RECT 151.29 0 152.04 385.37 ; + RECT 133.61 0 134.36 385.37 ; + RECT 115.93 0 116.68 385.37 ; + RECT 98.25 0 99 385.37 ; + RECT 80.57 0 81.32 385.37 ; + RECT 62.89 0 63.64 385.37 ; + RECT 45.21 0 45.96 385.37 ; + RECT 27.53 0 28.28 385.37 ; + RECT 9.85 0 10.6 385.37 ; + LAYER Metal3 ; + RECT 0 0 685.49 385.37 ; + LAYER Metal4 SPACING 0.21 ; + RECT 383.035 0 400.625 385.37 ; + RECT 377.885 0 379.705 385.37 ; + RECT 372.735 0 374.555 385.37 ; + RECT 679.605 0 685.49 385.37 ; + RECT 670.765 0 674.665 385.37 ; + RECT 670.765 47.305 685.49 53.15 ; + RECT 661.925 0 665.825 385.37 ; + RECT 653.085 0 656.985 385.37 ; + RECT 653.085 47.305 665.825 53.15 ; + RECT 644.245 0 648.145 385.37 ; + RECT 635.405 0 639.305 385.37 ; + RECT 635.405 47.305 648.145 53.15 ; + RECT 626.565 0 630.465 385.37 ; + RECT 617.725 0 621.625 385.37 ; + RECT 617.725 47.305 630.465 53.15 ; + RECT 608.885 0 612.785 385.37 ; + RECT 600.045 0 603.945 385.37 ; + RECT 600.045 47.305 612.785 53.15 ; + RECT 591.205 0 595.105 385.37 ; + RECT 582.365 0 586.265 385.37 ; + RECT 582.365 47.305 595.105 53.15 ; + RECT 573.525 0 577.425 385.37 ; + RECT 564.685 0 568.585 385.37 ; + RECT 564.685 47.305 577.425 53.15 ; + RECT 555.845 0 559.745 385.37 ; + RECT 547.005 0 550.905 385.37 ; + RECT 547.005 47.305 559.745 53.15 ; + RECT 538.165 0 542.065 385.37 ; + RECT 529.325 0 533.225 385.37 ; + RECT 529.325 47.305 542.065 53.15 ; + RECT 520.485 0 524.385 385.37 ; + RECT 511.645 0 515.545 385.37 ; + RECT 511.645 47.305 524.385 53.15 ; + RECT 502.805 0 506.705 385.37 ; + RECT 493.965 0 497.865 385.37 ; + RECT 493.965 47.305 506.705 53.15 ; + RECT 485.125 0 489.025 385.37 ; + RECT 476.285 0 480.185 385.37 ; + RECT 476.285 47.305 489.025 53.15 ; + RECT 467.445 0 471.345 385.37 ; + RECT 458.605 0 462.505 385.37 ; + RECT 458.605 47.305 471.345 53.15 ; + RECT 449.765 0 453.665 385.37 ; + RECT 440.925 0 444.825 385.37 ; + RECT 440.925 47.305 453.665 53.15 ; + RECT 432.085 0 435.985 385.37 ; + RECT 423.245 0 427.145 385.37 ; + RECT 423.245 47.305 435.985 53.15 ; + RECT 414.405 0 418.305 385.37 ; + RECT 405.565 0 409.465 385.37 ; + RECT 405.565 47.305 418.305 53.15 ; + RECT 367.585 0 369.405 385.37 ; + RECT 362.435 0 364.255 385.37 ; + RECT 357.285 0 359.105 385.37 ; + RECT 352.135 0 353.955 385.37 ; + RECT 346.985 0 348.805 385.37 ; + RECT 341.835 0 343.655 385.37 ; + RECT 336.685 0 338.505 385.37 ; + RECT 331.535 0 333.355 385.37 ; + RECT 326.385 0 328.205 385.37 ; + RECT 321.235 0 323.055 385.37 ; + RECT 316.085 0 317.905 385.37 ; + RECT 310.935 0 312.755 385.37 ; + RECT 305.785 0 307.605 385.37 ; + RECT 284.865 0 302.455 385.37 ; + RECT 276.025 0 279.925 385.37 ; + RECT 267.185 0 271.085 385.37 ; + RECT 267.185 47.305 279.925 53.15 ; + RECT 258.345 0 262.245 385.37 ; + RECT 249.505 0 253.405 385.37 ; + RECT 249.505 47.305 262.245 53.15 ; + RECT 240.665 0 244.565 385.37 ; + RECT 231.825 0 235.725 385.37 ; + RECT 231.825 47.305 244.565 53.15 ; + RECT 222.985 0 226.885 385.37 ; + RECT 214.145 0 218.045 385.37 ; + RECT 214.145 47.305 226.885 53.15 ; + RECT 205.305 0 209.205 385.37 ; + RECT 196.465 0 200.365 385.37 ; + RECT 196.465 47.305 209.205 53.15 ; + RECT 187.625 0 191.525 385.37 ; + RECT 178.785 0 182.685 385.37 ; + RECT 178.785 47.305 191.525 53.15 ; + RECT 169.945 0 173.845 385.37 ; + RECT 161.105 0 165.005 385.37 ; + RECT 161.105 47.305 173.845 53.15 ; + RECT 152.265 0 156.165 385.37 ; + RECT 143.425 0 147.325 385.37 ; + RECT 143.425 47.305 156.165 53.15 ; + RECT 134.585 0 138.485 385.37 ; + RECT 125.745 0 129.645 385.37 ; + RECT 125.745 47.305 138.485 53.15 ; + RECT 116.905 0 120.805 385.37 ; + RECT 108.065 0 111.965 385.37 ; + RECT 108.065 47.305 120.805 53.15 ; + RECT 99.225 0 103.125 385.37 ; + RECT 90.385 0 94.285 385.37 ; + RECT 90.385 47.305 103.125 53.15 ; + RECT 81.545 0 85.445 385.37 ; + RECT 72.705 0 76.605 385.37 ; + RECT 72.705 47.305 85.445 53.15 ; + RECT 63.865 0 67.765 385.37 ; + RECT 55.025 0 58.925 385.37 ; + RECT 55.025 47.305 67.765 53.15 ; + RECT 46.185 0 50.085 385.37 ; + RECT 37.345 0 41.245 385.37 ; + RECT 37.345 47.305 50.085 53.15 ; + RECT 28.505 0 32.405 385.37 ; + RECT 19.665 0 23.565 385.37 ; + RECT 19.665 47.305 32.405 53.15 ; + RECT 10.825 0 14.725 385.37 ; + RECT 0 0 5.885 385.37 ; + RECT 0 47.305 14.725 53.15 ; + END +END RM_IHPSG13_2P_1024x32_c2_bm_bist + +END LIBRARY diff --git a/flow/platforms/ihp-sg13g2/lef/RM_IHPSG13_2P_256x16_c2_bm_bist.lef b/flow/platforms/ihp-sg13g2/lef/RM_IHPSG13_2P_256x16_c2_bm_bist.lef new file mode 100644 index 0000000000..72f4fd920a --- /dev/null +++ b/flow/platforms/ihp-sg13g2/lef/RM_IHPSG13_2P_256x16_c2_bm_bist.lef @@ -0,0 +1,4255 @@ +# ------------------------------------------------------ +# +# Copyright 2025 IHP PDK Authors +# +# Licensed under the Apache License, Version 2.0 (the "License"); +# you may not use this file except in compliance with the License. +# You may obtain a copy of the License at +# +# https://www.apache.org/licenses/LICENSE-2.0 +# +# Unless required by applicable law or agreed to in writing, software +# distributed under the License is distributed on an "AS IS" BASIS, +# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +# See the License for the specific language governing permissions and +# limitations under the License. +# +# Generated on Wed Aug 27 13:19:48 2025 +# +# ------------------------------------------------------ +VERSION 5.7 ; +BUSBITCHARS "[]" ; +DIVIDERCHAR "/" ; + +MACRO RM_IHPSG13_2P_256x16_c2_bm_bist + CLASS BLOCK ; + ORIGIN 0 0 ; + FOREIGN RM_IHPSG13_2P_256x16_c2_bm_bist 0 0 ; + SIZE 419.95 BY 136.97 ; + SYMMETRY X Y R90 ; + PIN A_DIN[8] + DIRECTION INPUT ; + USE SIGNAL ; + ANTENNAPARTIALMETALAREA 3.9091 LAYER Metal2 ; + ANTENNAMODEL OXIDE1 ; + ANTENNAGATEAREA 0.20085 LAYER Metal2 ; + ANTENNAMAXAREACAR 20.368932 LAYER Metal2 ; + PORT + LAYER Metal2 ; + RECT 284.05 0 284.31 0.26 ; + END + END A_DIN[8] + PIN A_DIN[7] + DIRECTION INPUT ; + USE SIGNAL ; + ANTENNAPARTIALMETALAREA 3.9091 LAYER Metal2 ; + ANTENNAMODEL OXIDE1 ; + ANTENNAGATEAREA 0.20085 LAYER Metal2 ; + ANTENNAMAXAREACAR 20.368932 LAYER Metal2 ; + PORT + LAYER Metal2 ; + RECT 135.64 0 135.9 0.26 ; + END + END A_DIN[7] + PIN A_BIST_DIN[8] + DIRECTION INPUT ; + USE SIGNAL ; + ANTENNAPARTIALMETALAREA 4.136375 LAYER Metal2 ; + ANTENNAMODEL OXIDE1 ; + ANTENNAGATEAREA 0.20085 LAYER Metal2 ; + ANTENNAMAXAREACAR 21.874907 LAYER Metal2 ; + PORT + LAYER Metal2 ; + RECT 284.56 0 284.82 0.26 ; + END + END A_BIST_DIN[8] + PIN A_BIST_DIN[7] + DIRECTION INPUT ; + USE SIGNAL ; + ANTENNAPARTIALMETALAREA 4.136375 LAYER Metal2 ; + ANTENNAMODEL OXIDE1 ; + ANTENNAGATEAREA 0.20085 LAYER Metal2 ; + ANTENNAMAXAREACAR 21.874907 LAYER Metal2 ; + PORT + LAYER Metal2 ; + RECT 135.13 0 135.39 0.26 ; + END + END A_BIST_DIN[7] + PIN A_BM[8] + DIRECTION INPUT ; + USE SIGNAL ; + ANTENNAPARTIALMETALAREA 1.7264 LAYER Metal2 ; + ANTENNAMODEL OXIDE1 ; + ANTENNAGATEAREA 0.20085 LAYER Metal2 ; + ANTENNAMAXAREACAR 9.501618 LAYER Metal2 ; + PORT + LAYER Metal2 ; + RECT 292.72 0 292.98 0.26 ; + END + END A_BM[8] + PIN A_BM[7] + DIRECTION INPUT ; + USE SIGNAL ; + ANTENNAPARTIALMETALAREA 1.7264 LAYER Metal2 ; + ANTENNAMODEL OXIDE1 ; + ANTENNAGATEAREA 0.20085 LAYER Metal2 ; + ANTENNAMAXAREACAR 9.501618 LAYER Metal2 ; + PORT + LAYER Metal2 ; + RECT 126.97 0 127.23 0.26 ; + END + END A_BM[7] + PIN A_BIST_BM[8] + DIRECTION INPUT ; + USE SIGNAL ; + ANTENNAPARTIALMETALAREA 1.7602 LAYER Metal2 ; + ANTENNAMODEL OXIDE1 ; + ANTENNAGATEAREA 0.20085 LAYER Metal2 ; + ANTENNAMAXAREACAR 9.678367 LAYER Metal2 ; + PORT + LAYER Metal2 ; + RECT 291.345 0 291.605 0.26 ; + END + END A_BIST_BM[8] + PIN A_BIST_BM[7] + DIRECTION INPUT ; + USE SIGNAL ; + ANTENNAPARTIALMETALAREA 1.7602 LAYER Metal2 ; + ANTENNAMODEL OXIDE1 ; + ANTENNAGATEAREA 0.20085 LAYER Metal2 ; + ANTENNAMAXAREACAR 9.678367 LAYER Metal2 ; + PORT + LAYER Metal2 ; + RECT 128.345 0 128.605 0.26 ; + END + END A_BIST_BM[7] + PIN A_DOUT[8] + DIRECTION OUTPUT ; + USE SIGNAL ; + ANTENNAPARTIALMETALAREA 4.8256 LAYER Metal2 ; + ANTENNADIFFAREA 0.988 LAYER Metal2 ; + PORT + LAYER Metal2 ; + RECT 276.91 0 277.17 0.26 ; + END + END A_DOUT[8] + PIN A_DOUT[7] + DIRECTION OUTPUT ; + USE SIGNAL ; + ANTENNAPARTIALMETALAREA 4.8256 LAYER Metal2 ; + ANTENNADIFFAREA 0.988 LAYER Metal2 ; + PORT + LAYER Metal2 ; + RECT 142.78 0 143.04 0.26 ; + END + END A_DOUT[7] + PIN B_DIN[8] + DIRECTION INPUT ; + USE SIGNAL ; + ANTENNAPARTIALMETALAREA 2.925 LAYER Metal2 ; + ANTENNAMODEL OXIDE1 ; + ANTENNAGATEAREA 0.20085 LAYER Metal2 ; + ANTENNAMAXAREACAR 15.469256 LAYER Metal2 ; + PORT + LAYER Metal2 ; + RECT 286.6 0 286.86 0.26 ; + END + END B_DIN[8] + PIN B_DIN[7] + DIRECTION INPUT ; + USE SIGNAL ; + ANTENNAPARTIALMETALAREA 2.925 LAYER Metal2 ; + ANTENNAMODEL OXIDE1 ; + ANTENNAGATEAREA 0.20085 LAYER Metal2 ; + ANTENNAMAXAREACAR 15.469256 LAYER Metal2 ; + PORT + LAYER Metal2 ; + RECT 133.09 0 133.35 0.26 ; + END + END B_DIN[7] + PIN B_BIST_DIN[8] + DIRECTION INPUT ; + USE SIGNAL ; + ANTENNAPARTIALMETALAREA 2.9445 LAYER Metal2 ; + ANTENNAMODEL OXIDE1 ; + ANTENNAGATEAREA 0.20085 LAYER Metal2 ; + ANTENNAMAXAREACAR 15.929052 LAYER Metal2 ; + PORT + LAYER Metal2 ; + RECT 285.07 0 285.33 0.26 ; + END + END B_BIST_DIN[8] + PIN B_BIST_DIN[7] + DIRECTION INPUT ; + USE SIGNAL ; + ANTENNAPARTIALMETALAREA 2.9445 LAYER Metal2 ; + ANTENNAMODEL OXIDE1 ; + ANTENNAGATEAREA 0.20085 LAYER Metal2 ; + ANTENNAMAXAREACAR 15.929052 LAYER Metal2 ; + PORT + LAYER Metal2 ; + RECT 134.62 0 134.88 0.26 ; + END + END B_BIST_DIN[7] + PIN B_BM[8] + DIRECTION INPUT ; + USE SIGNAL ; + ANTENNAPARTIALMETALAREA 0.7007 LAYER Metal2 ; + ANTENNAMODEL OXIDE1 ; + ANTENNAGATEAREA 0.20085 LAYER Metal2 ; + ANTENNAMAXAREACAR 4.394822 LAYER Metal2 ; + PORT + LAYER Metal2 ; + RECT 278.085 0 278.345 0.26 ; + END + END B_BM[8] + PIN B_BM[7] + DIRECTION INPUT ; + USE SIGNAL ; + ANTENNAPARTIALMETALAREA 0.7007 LAYER Metal2 ; + ANTENNAMODEL OXIDE1 ; + ANTENNAGATEAREA 0.20085 LAYER Metal2 ; + ANTENNAMAXAREACAR 4.394822 LAYER Metal2 ; + PORT + LAYER Metal2 ; + RECT 141.605 0 141.865 0.26 ; + END + END B_BM[7] + PIN B_BIST_BM[8] + DIRECTION INPUT ; + USE SIGNAL ; + ANTENNAPARTIALMETALAREA 0.7007 LAYER Metal2 ; + ANTENNAMODEL OXIDE1 ; + ANTENNAGATEAREA 0.20085 LAYER Metal2 ; + ANTENNAMAXAREACAR 4.394822 LAYER Metal2 ; + PORT + LAYER Metal2 ; + RECT 279.615 0 279.875 0.26 ; + END + END B_BIST_BM[8] + PIN B_BIST_BM[7] + DIRECTION INPUT ; + USE SIGNAL ; + ANTENNAPARTIALMETALAREA 0.7007 LAYER Metal2 ; + ANTENNAMODEL OXIDE1 ; + ANTENNAGATEAREA 0.20085 LAYER Metal2 ; + ANTENNAMAXAREACAR 4.394822 LAYER Metal2 ; + PORT + LAYER Metal2 ; + RECT 140.075 0 140.335 0.26 ; + END + END B_BIST_BM[7] + PIN B_DOUT[8] + DIRECTION OUTPUT ; + USE SIGNAL ; + ANTENNAPARTIALMETALAREA 4.836 LAYER Metal2 ; + ANTENNADIFFAREA 0.988 LAYER Metal2 ; + PORT + LAYER Metal2 ; + RECT 293.74 0 294 0.26 ; + END + END B_DOUT[8] + PIN B_DOUT[7] + DIRECTION OUTPUT ; + USE SIGNAL ; + ANTENNAPARTIALMETALAREA 4.836 LAYER Metal2 ; + ANTENNADIFFAREA 0.988 LAYER Metal2 ; + PORT + LAYER Metal2 ; + RECT 125.95 0 126.21 0.26 ; + END + END B_DOUT[7] + PIN VSS! + DIRECTION INOUT ; + USE GROUND ; + NETEXPR "vss VSS!" ; + PORT + LAYER Metal4 ; + RECT 400.545 0 404.965 136.97 ; + END + PORT + LAYER Metal4 ; + RECT 382.865 0 387.285 136.97 ; + END + PORT + LAYER Metal4 ; + RECT 365.185 0 369.605 136.97 ; + END + PORT + LAYER Metal4 ; + RECT 347.505 0 351.925 136.97 ; + END + PORT + LAYER Metal4 ; + RECT 329.825 0 334.245 136.97 ; + END + PORT + LAYER Metal4 ; + RECT 312.145 0 316.565 136.97 ; + END + PORT + LAYER Metal4 ; + RECT 294.465 0 298.885 136.97 ; + END + PORT + LAYER Metal4 ; + RECT 276.785 0 281.205 136.97 ; + END + PORT + LAYER Metal4 ; + RECT 247.195 0 250.005 136.97 ; + END + PORT + LAYER Metal4 ; + RECT 236.895 0 239.705 136.97 ; + END + PORT + LAYER Metal4 ; + RECT 221.445 0 224.255 136.97 ; + END + PORT + LAYER Metal4 ; + RECT 211.145 0 213.955 136.97 ; + END + PORT + LAYER Metal4 ; + RECT 205.995 0 208.805 136.97 ; + END + PORT + LAYER Metal4 ; + RECT 195.695 0 198.505 136.97 ; + END + PORT + LAYER Metal4 ; + RECT 180.245 0 183.055 136.97 ; + END + PORT + LAYER Metal4 ; + RECT 169.945 0 172.755 136.97 ; + END + PORT + LAYER Metal4 ; + RECT 138.745 0 143.165 136.97 ; + END + PORT + LAYER Metal4 ; + RECT 121.065 0 125.485 136.97 ; + END + PORT + LAYER Metal4 ; + RECT 103.385 0 107.805 136.97 ; + END + PORT + LAYER Metal4 ; + RECT 85.705 0 90.125 136.97 ; + END + PORT + LAYER Metal4 ; + RECT 68.025 0 72.445 136.97 ; + END + PORT + LAYER Metal4 ; + RECT 50.345 0 54.765 136.97 ; + END + PORT + LAYER Metal4 ; + RECT 32.665 0 37.085 136.97 ; + END + PORT + LAYER Metal4 ; + RECT 14.985 0 19.405 136.97 ; + END + END VSS! + PIN VDD! + DIRECTION INOUT ; + USE POWER ; + NETEXPR "vdd VDD!" ; + PORT + LAYER Metal4 ; + RECT 409.385 0 413.805 47.045 ; + END + PORT + LAYER Metal4 ; + RECT 391.705 0 396.125 47.045 ; + END + PORT + LAYER Metal4 ; + RECT 374.025 0 378.445 47.045 ; + END + PORT + LAYER Metal4 ; + RECT 356.345 0 360.765 47.045 ; + END + PORT + LAYER Metal4 ; + RECT 338.665 0 343.085 47.045 ; + END + PORT + LAYER Metal4 ; + RECT 320.985 0 325.405 47.045 ; + END + PORT + LAYER Metal4 ; + RECT 303.305 0 307.725 47.045 ; + END + PORT + LAYER Metal4 ; + RECT 285.625 0 290.045 47.045 ; + END + PORT + LAYER Metal4 ; + RECT 242.045 0 244.855 136.97 ; + END + PORT + LAYER Metal4 ; + RECT 231.745 0 234.555 136.97 ; + END + PORT + LAYER Metal4 ; + RECT 226.595 0 229.405 136.97 ; + END + PORT + LAYER Metal4 ; + RECT 216.295 0 219.105 136.97 ; + END + PORT + LAYER Metal4 ; + RECT 200.845 0 203.655 136.97 ; + END + PORT + LAYER Metal4 ; + RECT 190.545 0 193.355 136.97 ; + END + PORT + LAYER Metal4 ; + RECT 185.395 0 188.205 136.97 ; + END + PORT + LAYER Metal4 ; + RECT 175.095 0 177.905 136.97 ; + END + PORT + LAYER Metal4 ; + RECT 129.905 0 134.325 47.045 ; + END + PORT + LAYER Metal4 ; + RECT 112.225 0 116.645 47.045 ; + END + PORT + LAYER Metal4 ; + RECT 94.545 0 98.965 47.045 ; + END + PORT + LAYER Metal4 ; + RECT 76.865 0 81.285 47.045 ; + END + PORT + LAYER Metal4 ; + RECT 59.185 0 63.605 47.045 ; + END + PORT + LAYER Metal4 ; + RECT 41.505 0 45.925 47.045 ; + END + PORT + LAYER Metal4 ; + RECT 23.825 0 28.245 47.045 ; + END + PORT + LAYER Metal4 ; + RECT 6.145 0 10.565 47.045 ; + END + END VDD! + PIN VDDARRAY! + DIRECTION INOUT ; + USE POWER ; + NETEXPR "vddarray VDDARRAY!" ; + PORT + LAYER Metal4 ; + RECT 409.385 53.41 413.805 136.97 ; + END + PORT + LAYER Metal4 ; + RECT 391.705 53.41 396.125 136.97 ; + END + PORT + LAYER Metal4 ; + RECT 374.025 53.41 378.445 136.97 ; + END + PORT + LAYER Metal4 ; + RECT 356.345 53.41 360.765 136.97 ; + END + PORT + LAYER Metal4 ; + RECT 338.665 53.41 343.085 136.97 ; + END + PORT + LAYER Metal4 ; + RECT 320.985 53.41 325.405 136.97 ; + END + PORT + LAYER Metal4 ; + RECT 303.305 53.41 307.725 136.97 ; + END + PORT + LAYER Metal4 ; + RECT 285.625 53.41 290.045 136.97 ; + END + PORT + LAYER Metal4 ; + RECT 129.905 53.41 134.325 136.97 ; + END + PORT + LAYER Metal4 ; + RECT 112.225 53.41 116.645 136.97 ; + END + PORT + LAYER Metal4 ; + RECT 94.545 53.41 98.965 136.97 ; + END + PORT + LAYER Metal4 ; + RECT 76.865 53.41 81.285 136.97 ; + END + PORT + LAYER Metal4 ; + RECT 59.185 53.41 63.605 136.97 ; + END + PORT + LAYER Metal4 ; + RECT 41.505 53.41 45.925 136.97 ; + END + PORT + LAYER Metal4 ; + RECT 23.825 53.41 28.245 136.97 ; + END + PORT + LAYER Metal4 ; + RECT 6.145 53.41 10.565 136.97 ; + END + END VDDARRAY! + PIN A_DIN[9] + DIRECTION INPUT ; + USE SIGNAL ; + ANTENNAPARTIALMETALAREA 3.9091 LAYER Metal2 ; + ANTENNAMODEL OXIDE1 ; + ANTENNAGATEAREA 0.20085 LAYER Metal2 ; + ANTENNAMAXAREACAR 20.368932 LAYER Metal2 ; + PORT + LAYER Metal2 ; + RECT 301.73 0 301.99 0.26 ; + END + END A_DIN[9] + PIN A_DIN[6] + DIRECTION INPUT ; + USE SIGNAL ; + ANTENNAPARTIALMETALAREA 3.9091 LAYER Metal2 ; + ANTENNAMODEL OXIDE1 ; + ANTENNAGATEAREA 0.20085 LAYER Metal2 ; + ANTENNAMAXAREACAR 20.368932 LAYER Metal2 ; + PORT + LAYER Metal2 ; + RECT 117.96 0 118.22 0.26 ; + END + END A_DIN[6] + PIN A_BIST_DIN[9] + DIRECTION INPUT ; + USE SIGNAL ; + ANTENNAPARTIALMETALAREA 4.136375 LAYER Metal2 ; + ANTENNAMODEL OXIDE1 ; + ANTENNAGATEAREA 0.20085 LAYER Metal2 ; + ANTENNAMAXAREACAR 21.874907 LAYER Metal2 ; + PORT + LAYER Metal2 ; + RECT 302.24 0 302.5 0.26 ; + END + END A_BIST_DIN[9] + PIN A_BIST_DIN[6] + DIRECTION INPUT ; + USE SIGNAL ; + ANTENNAPARTIALMETALAREA 4.136375 LAYER Metal2 ; + ANTENNAMODEL OXIDE1 ; + ANTENNAGATEAREA 0.20085 LAYER Metal2 ; + ANTENNAMAXAREACAR 21.874907 LAYER Metal2 ; + PORT + LAYER Metal2 ; + RECT 117.45 0 117.71 0.26 ; + END + END A_BIST_DIN[6] + PIN A_BM[9] + DIRECTION INPUT ; + USE SIGNAL ; + ANTENNAPARTIALMETALAREA 1.7264 LAYER Metal2 ; + ANTENNAMODEL OXIDE1 ; + ANTENNAGATEAREA 0.20085 LAYER Metal2 ; + ANTENNAMAXAREACAR 9.501618 LAYER Metal2 ; + PORT + LAYER Metal2 ; + RECT 310.4 0 310.66 0.26 ; + END + END A_BM[9] + PIN A_BM[6] + DIRECTION INPUT ; + USE SIGNAL ; + ANTENNAPARTIALMETALAREA 1.7264 LAYER Metal2 ; + ANTENNAMODEL OXIDE1 ; + ANTENNAGATEAREA 0.20085 LAYER Metal2 ; + ANTENNAMAXAREACAR 9.501618 LAYER Metal2 ; + PORT + LAYER Metal2 ; + RECT 109.29 0 109.55 0.26 ; + END + END A_BM[6] + PIN A_BIST_BM[9] + DIRECTION INPUT ; + USE SIGNAL ; + ANTENNAPARTIALMETALAREA 1.7602 LAYER Metal2 ; + ANTENNAMODEL OXIDE1 ; + ANTENNAGATEAREA 0.20085 LAYER Metal2 ; + ANTENNAMAXAREACAR 9.678367 LAYER Metal2 ; + PORT + LAYER Metal2 ; + RECT 309.025 0 309.285 0.26 ; + END + END A_BIST_BM[9] + PIN A_BIST_BM[6] + DIRECTION INPUT ; + USE SIGNAL ; + ANTENNAPARTIALMETALAREA 1.7602 LAYER Metal2 ; + ANTENNAMODEL OXIDE1 ; + ANTENNAGATEAREA 0.20085 LAYER Metal2 ; + ANTENNAMAXAREACAR 9.678367 LAYER Metal2 ; + PORT + LAYER Metal2 ; + RECT 110.665 0 110.925 0.26 ; + END + END A_BIST_BM[6] + PIN A_DOUT[9] + DIRECTION OUTPUT ; + USE SIGNAL ; + ANTENNAPARTIALMETALAREA 4.8256 LAYER Metal2 ; + ANTENNADIFFAREA 0.988 LAYER Metal2 ; + PORT + LAYER Metal2 ; + RECT 294.59 0 294.85 0.26 ; + END + END A_DOUT[9] + PIN A_DOUT[6] + DIRECTION OUTPUT ; + USE SIGNAL ; + ANTENNAPARTIALMETALAREA 4.8256 LAYER Metal2 ; + ANTENNADIFFAREA 0.988 LAYER Metal2 ; + PORT + LAYER Metal2 ; + RECT 125.1 0 125.36 0.26 ; + END + END A_DOUT[6] + PIN B_DIN[9] + DIRECTION INPUT ; + USE SIGNAL ; + ANTENNAPARTIALMETALAREA 2.925 LAYER Metal2 ; + ANTENNAMODEL OXIDE1 ; + ANTENNAGATEAREA 0.20085 LAYER Metal2 ; + ANTENNAMAXAREACAR 15.469256 LAYER Metal2 ; + PORT + LAYER Metal2 ; + RECT 304.28 0 304.54 0.26 ; + END + END B_DIN[9] + PIN B_DIN[6] + DIRECTION INPUT ; + USE SIGNAL ; + ANTENNAPARTIALMETALAREA 2.925 LAYER Metal2 ; + ANTENNAMODEL OXIDE1 ; + ANTENNAGATEAREA 0.20085 LAYER Metal2 ; + ANTENNAMAXAREACAR 15.469256 LAYER Metal2 ; + PORT + LAYER Metal2 ; + RECT 115.41 0 115.67 0.26 ; + END + END B_DIN[6] + PIN B_BIST_DIN[9] + DIRECTION INPUT ; + USE SIGNAL ; + ANTENNAPARTIALMETALAREA 2.9445 LAYER Metal2 ; + ANTENNAMODEL OXIDE1 ; + ANTENNAGATEAREA 0.20085 LAYER Metal2 ; + ANTENNAMAXAREACAR 15.929052 LAYER Metal2 ; + PORT + LAYER Metal2 ; + RECT 302.75 0 303.01 0.26 ; + END + END B_BIST_DIN[9] + PIN B_BIST_DIN[6] + DIRECTION INPUT ; + USE SIGNAL ; + ANTENNAPARTIALMETALAREA 2.9445 LAYER Metal2 ; + ANTENNAMODEL OXIDE1 ; + ANTENNAGATEAREA 0.20085 LAYER Metal2 ; + ANTENNAMAXAREACAR 15.929052 LAYER Metal2 ; + PORT + LAYER Metal2 ; + RECT 116.94 0 117.2 0.26 ; + END + END B_BIST_DIN[6] + PIN B_BM[9] + DIRECTION INPUT ; + USE SIGNAL ; + ANTENNAPARTIALMETALAREA 0.7007 LAYER Metal2 ; + ANTENNAMODEL OXIDE1 ; + ANTENNAGATEAREA 0.20085 LAYER Metal2 ; + ANTENNAMAXAREACAR 4.394822 LAYER Metal2 ; + PORT + LAYER Metal2 ; + RECT 295.765 0 296.025 0.26 ; + END + END B_BM[9] + PIN B_BM[6] + DIRECTION INPUT ; + USE SIGNAL ; + ANTENNAPARTIALMETALAREA 0.7007 LAYER Metal2 ; + ANTENNAMODEL OXIDE1 ; + ANTENNAGATEAREA 0.20085 LAYER Metal2 ; + ANTENNAMAXAREACAR 4.394822 LAYER Metal2 ; + PORT + LAYER Metal2 ; + RECT 123.925 0 124.185 0.26 ; + END + END B_BM[6] + PIN B_BIST_BM[9] + DIRECTION INPUT ; + USE SIGNAL ; + ANTENNAPARTIALMETALAREA 0.7007 LAYER Metal2 ; + ANTENNAMODEL OXIDE1 ; + ANTENNAGATEAREA 0.20085 LAYER Metal2 ; + ANTENNAMAXAREACAR 4.394822 LAYER Metal2 ; + PORT + LAYER Metal2 ; + RECT 297.295 0 297.555 0.26 ; + END + END B_BIST_BM[9] + PIN B_BIST_BM[6] + DIRECTION INPUT ; + USE SIGNAL ; + ANTENNAPARTIALMETALAREA 0.7007 LAYER Metal2 ; + ANTENNAMODEL OXIDE1 ; + ANTENNAGATEAREA 0.20085 LAYER Metal2 ; + ANTENNAMAXAREACAR 4.394822 LAYER Metal2 ; + PORT + LAYER Metal2 ; + RECT 122.395 0 122.655 0.26 ; + END + END B_BIST_BM[6] + PIN B_DOUT[9] + DIRECTION OUTPUT ; + USE SIGNAL ; + ANTENNAPARTIALMETALAREA 4.836 LAYER Metal2 ; + ANTENNADIFFAREA 0.988 LAYER Metal2 ; + PORT + LAYER Metal2 ; + RECT 311.42 0 311.68 0.26 ; + END + END B_DOUT[9] + PIN B_DOUT[6] + DIRECTION OUTPUT ; + USE SIGNAL ; + ANTENNAPARTIALMETALAREA 4.836 LAYER Metal2 ; + ANTENNADIFFAREA 0.988 LAYER Metal2 ; + PORT + LAYER Metal2 ; + RECT 108.27 0 108.53 0.26 ; + END + END B_DOUT[6] + PIN A_DIN[10] + DIRECTION INPUT ; + USE SIGNAL ; + ANTENNAPARTIALMETALAREA 3.9091 LAYER Metal2 ; + ANTENNAMODEL OXIDE1 ; + ANTENNAGATEAREA 0.20085 LAYER Metal2 ; + ANTENNAMAXAREACAR 20.368932 LAYER Metal2 ; + PORT + LAYER Metal2 ; + RECT 319.41 0 319.67 0.26 ; + END + END A_DIN[10] + PIN A_DIN[5] + DIRECTION INPUT ; + USE SIGNAL ; + ANTENNAPARTIALMETALAREA 3.9091 LAYER Metal2 ; + ANTENNAMODEL OXIDE1 ; + ANTENNAGATEAREA 0.20085 LAYER Metal2 ; + ANTENNAMAXAREACAR 20.368932 LAYER Metal2 ; + PORT + LAYER Metal2 ; + RECT 100.28 0 100.54 0.26 ; + END + END A_DIN[5] + PIN A_BIST_DIN[10] + DIRECTION INPUT ; + USE SIGNAL ; + ANTENNAPARTIALMETALAREA 4.136375 LAYER Metal2 ; + ANTENNAMODEL OXIDE1 ; + ANTENNAGATEAREA 0.20085 LAYER Metal2 ; + ANTENNAMAXAREACAR 21.874907 LAYER Metal2 ; + PORT + LAYER Metal2 ; + RECT 319.92 0 320.18 0.26 ; + END + END A_BIST_DIN[10] + PIN A_BIST_DIN[5] + DIRECTION INPUT ; + USE SIGNAL ; + ANTENNAPARTIALMETALAREA 4.136375 LAYER Metal2 ; + ANTENNAMODEL OXIDE1 ; + ANTENNAGATEAREA 0.20085 LAYER Metal2 ; + ANTENNAMAXAREACAR 21.874907 LAYER Metal2 ; + PORT + LAYER Metal2 ; + RECT 99.77 0 100.03 0.26 ; + END + END A_BIST_DIN[5] + PIN A_BM[10] + DIRECTION INPUT ; + USE SIGNAL ; + ANTENNAPARTIALMETALAREA 1.7264 LAYER Metal2 ; + ANTENNAMODEL OXIDE1 ; + ANTENNAGATEAREA 0.20085 LAYER Metal2 ; + ANTENNAMAXAREACAR 9.501618 LAYER Metal2 ; + PORT + LAYER Metal2 ; + RECT 328.08 0 328.34 0.26 ; + END + END A_BM[10] + PIN A_BM[5] + DIRECTION INPUT ; + USE SIGNAL ; + ANTENNAPARTIALMETALAREA 1.7264 LAYER Metal2 ; + ANTENNAMODEL OXIDE1 ; + ANTENNAGATEAREA 0.20085 LAYER Metal2 ; + ANTENNAMAXAREACAR 9.501618 LAYER Metal2 ; + PORT + LAYER Metal2 ; + RECT 91.61 0 91.87 0.26 ; + END + END A_BM[5] + PIN A_BIST_BM[10] + DIRECTION INPUT ; + USE SIGNAL ; + ANTENNAPARTIALMETALAREA 1.7602 LAYER Metal2 ; + ANTENNAMODEL OXIDE1 ; + ANTENNAGATEAREA 0.20085 LAYER Metal2 ; + ANTENNAMAXAREACAR 9.678367 LAYER Metal2 ; + PORT + LAYER Metal2 ; + RECT 326.705 0 326.965 0.26 ; + END + END A_BIST_BM[10] + PIN A_BIST_BM[5] + DIRECTION INPUT ; + USE SIGNAL ; + ANTENNAPARTIALMETALAREA 1.7602 LAYER Metal2 ; + ANTENNAMODEL OXIDE1 ; + ANTENNAGATEAREA 0.20085 LAYER Metal2 ; + ANTENNAMAXAREACAR 9.678367 LAYER Metal2 ; + PORT + LAYER Metal2 ; + RECT 92.985 0 93.245 0.26 ; + END + END A_BIST_BM[5] + PIN A_DOUT[10] + DIRECTION OUTPUT ; + USE SIGNAL ; + ANTENNAPARTIALMETALAREA 4.8256 LAYER Metal2 ; + ANTENNADIFFAREA 0.988 LAYER Metal2 ; + PORT + LAYER Metal2 ; + RECT 312.27 0 312.53 0.26 ; + END + END A_DOUT[10] + PIN A_DOUT[5] + DIRECTION OUTPUT ; + USE SIGNAL ; + ANTENNAPARTIALMETALAREA 4.8256 LAYER Metal2 ; + ANTENNADIFFAREA 0.988 LAYER Metal2 ; + PORT + LAYER Metal2 ; + RECT 107.42 0 107.68 0.26 ; + END + END A_DOUT[5] + PIN B_DIN[10] + DIRECTION INPUT ; + USE SIGNAL ; + ANTENNAPARTIALMETALAREA 2.925 LAYER Metal2 ; + ANTENNAMODEL OXIDE1 ; + ANTENNAGATEAREA 0.20085 LAYER Metal2 ; + ANTENNAMAXAREACAR 15.469256 LAYER Metal2 ; + PORT + LAYER Metal2 ; + RECT 321.96 0 322.22 0.26 ; + END + END B_DIN[10] + PIN B_DIN[5] + DIRECTION INPUT ; + USE SIGNAL ; + ANTENNAPARTIALMETALAREA 2.925 LAYER Metal2 ; + ANTENNAMODEL OXIDE1 ; + ANTENNAGATEAREA 0.20085 LAYER Metal2 ; + ANTENNAMAXAREACAR 15.469256 LAYER Metal2 ; + PORT + LAYER Metal2 ; + RECT 97.73 0 97.99 0.26 ; + END + END B_DIN[5] + PIN B_BIST_DIN[10] + DIRECTION INPUT ; + USE SIGNAL ; + ANTENNAPARTIALMETALAREA 2.9445 LAYER Metal2 ; + ANTENNAMODEL OXIDE1 ; + ANTENNAGATEAREA 0.20085 LAYER Metal2 ; + ANTENNAMAXAREACAR 15.929052 LAYER Metal2 ; + PORT + LAYER Metal2 ; + RECT 320.43 0 320.69 0.26 ; + END + END B_BIST_DIN[10] + PIN B_BIST_DIN[5] + DIRECTION INPUT ; + USE SIGNAL ; + ANTENNAPARTIALMETALAREA 2.9445 LAYER Metal2 ; + ANTENNAMODEL OXIDE1 ; + ANTENNAGATEAREA 0.20085 LAYER Metal2 ; + ANTENNAMAXAREACAR 15.929052 LAYER Metal2 ; + PORT + LAYER Metal2 ; + RECT 99.26 0 99.52 0.26 ; + END + END B_BIST_DIN[5] + PIN B_BM[10] + DIRECTION INPUT ; + USE SIGNAL ; + ANTENNAPARTIALMETALAREA 0.7007 LAYER Metal2 ; + ANTENNAMODEL OXIDE1 ; + ANTENNAGATEAREA 0.20085 LAYER Metal2 ; + ANTENNAMAXAREACAR 4.394822 LAYER Metal2 ; + PORT + LAYER Metal2 ; + RECT 313.445 0 313.705 0.26 ; + END + END B_BM[10] + PIN B_BM[5] + DIRECTION INPUT ; + USE SIGNAL ; + ANTENNAPARTIALMETALAREA 0.7007 LAYER Metal2 ; + ANTENNAMODEL OXIDE1 ; + ANTENNAGATEAREA 0.20085 LAYER Metal2 ; + ANTENNAMAXAREACAR 4.394822 LAYER Metal2 ; + PORT + LAYER Metal2 ; + RECT 106.245 0 106.505 0.26 ; + END + END B_BM[5] + PIN B_BIST_BM[10] + DIRECTION INPUT ; + USE SIGNAL ; + ANTENNAPARTIALMETALAREA 0.7007 LAYER Metal2 ; + ANTENNAMODEL OXIDE1 ; + ANTENNAGATEAREA 0.20085 LAYER Metal2 ; + ANTENNAMAXAREACAR 4.394822 LAYER Metal2 ; + PORT + LAYER Metal2 ; + RECT 314.975 0 315.235 0.26 ; + END + END B_BIST_BM[10] + PIN B_BIST_BM[5] + DIRECTION INPUT ; + USE SIGNAL ; + ANTENNAPARTIALMETALAREA 0.7007 LAYER Metal2 ; + ANTENNAMODEL OXIDE1 ; + ANTENNAGATEAREA 0.20085 LAYER Metal2 ; + ANTENNAMAXAREACAR 4.394822 LAYER Metal2 ; + PORT + LAYER Metal2 ; + RECT 104.715 0 104.975 0.26 ; + END + END B_BIST_BM[5] + PIN B_DOUT[10] + DIRECTION OUTPUT ; + USE SIGNAL ; + ANTENNAPARTIALMETALAREA 4.836 LAYER Metal2 ; + ANTENNADIFFAREA 0.988 LAYER Metal2 ; + PORT + LAYER Metal2 ; + RECT 329.1 0 329.36 0.26 ; + END + END B_DOUT[10] + PIN B_DOUT[5] + DIRECTION OUTPUT ; + USE SIGNAL ; + ANTENNAPARTIALMETALAREA 4.836 LAYER Metal2 ; + ANTENNADIFFAREA 0.988 LAYER Metal2 ; + PORT + LAYER Metal2 ; + RECT 90.59 0 90.85 0.26 ; + END + END B_DOUT[5] + PIN A_DIN[11] + DIRECTION INPUT ; + USE SIGNAL ; + ANTENNAPARTIALMETALAREA 3.9091 LAYER Metal2 ; + ANTENNAMODEL OXIDE1 ; + ANTENNAGATEAREA 0.20085 LAYER Metal2 ; + ANTENNAMAXAREACAR 20.368932 LAYER Metal2 ; + PORT + LAYER Metal2 ; + RECT 337.09 0 337.35 0.26 ; + END + END A_DIN[11] + PIN A_DIN[4] + DIRECTION INPUT ; + USE SIGNAL ; + ANTENNAPARTIALMETALAREA 3.9091 LAYER Metal2 ; + ANTENNAMODEL OXIDE1 ; + ANTENNAGATEAREA 0.20085 LAYER Metal2 ; + ANTENNAMAXAREACAR 20.368932 LAYER Metal2 ; + PORT + LAYER Metal2 ; + RECT 82.6 0 82.86 0.26 ; + END + END A_DIN[4] + PIN A_BIST_DIN[11] + DIRECTION INPUT ; + USE SIGNAL ; + ANTENNAPARTIALMETALAREA 4.136375 LAYER Metal2 ; + ANTENNAMODEL OXIDE1 ; + ANTENNAGATEAREA 0.20085 LAYER Metal2 ; + ANTENNAMAXAREACAR 21.874907 LAYER Metal2 ; + PORT + LAYER Metal2 ; + RECT 337.6 0 337.86 0.26 ; + END + END A_BIST_DIN[11] + PIN A_BIST_DIN[4] + DIRECTION INPUT ; + USE SIGNAL ; + ANTENNAPARTIALMETALAREA 4.136375 LAYER Metal2 ; + ANTENNAMODEL OXIDE1 ; + ANTENNAGATEAREA 0.20085 LAYER Metal2 ; + ANTENNAMAXAREACAR 21.874907 LAYER Metal2 ; + PORT + LAYER Metal2 ; + RECT 82.09 0 82.35 0.26 ; + END + END A_BIST_DIN[4] + PIN A_BM[11] + DIRECTION INPUT ; + USE SIGNAL ; + ANTENNAPARTIALMETALAREA 1.7264 LAYER Metal2 ; + ANTENNAMODEL OXIDE1 ; + ANTENNAGATEAREA 0.20085 LAYER Metal2 ; + ANTENNAMAXAREACAR 9.501618 LAYER Metal2 ; + PORT + LAYER Metal2 ; + RECT 345.76 0 346.02 0.26 ; + END + END A_BM[11] + PIN A_BM[4] + DIRECTION INPUT ; + USE SIGNAL ; + ANTENNAPARTIALMETALAREA 1.7264 LAYER Metal2 ; + ANTENNAMODEL OXIDE1 ; + ANTENNAGATEAREA 0.20085 LAYER Metal2 ; + ANTENNAMAXAREACAR 9.501618 LAYER Metal2 ; + PORT + LAYER Metal2 ; + RECT 73.93 0 74.19 0.26 ; + END + END A_BM[4] + PIN A_BIST_BM[11] + DIRECTION INPUT ; + USE SIGNAL ; + ANTENNAPARTIALMETALAREA 1.7602 LAYER Metal2 ; + ANTENNAMODEL OXIDE1 ; + ANTENNAGATEAREA 0.20085 LAYER Metal2 ; + ANTENNAMAXAREACAR 9.678367 LAYER Metal2 ; + PORT + LAYER Metal2 ; + RECT 344.385 0 344.645 0.26 ; + END + END A_BIST_BM[11] + PIN A_BIST_BM[4] + DIRECTION INPUT ; + USE SIGNAL ; + ANTENNAPARTIALMETALAREA 1.7602 LAYER Metal2 ; + ANTENNAMODEL OXIDE1 ; + ANTENNAGATEAREA 0.20085 LAYER Metal2 ; + ANTENNAMAXAREACAR 9.678367 LAYER Metal2 ; + PORT + LAYER Metal2 ; + RECT 75.305 0 75.565 0.26 ; + END + END A_BIST_BM[4] + PIN A_DOUT[11] + DIRECTION OUTPUT ; + USE SIGNAL ; + ANTENNAPARTIALMETALAREA 4.8256 LAYER Metal2 ; + ANTENNADIFFAREA 0.988 LAYER Metal2 ; + PORT + LAYER Metal2 ; + RECT 329.95 0 330.21 0.26 ; + END + END A_DOUT[11] + PIN A_DOUT[4] + DIRECTION OUTPUT ; + USE SIGNAL ; + ANTENNAPARTIALMETALAREA 4.8256 LAYER Metal2 ; + ANTENNADIFFAREA 0.988 LAYER Metal2 ; + PORT + LAYER Metal2 ; + RECT 89.74 0 90 0.26 ; + END + END A_DOUT[4] + PIN B_DIN[11] + DIRECTION INPUT ; + USE SIGNAL ; + ANTENNAPARTIALMETALAREA 2.925 LAYER Metal2 ; + ANTENNAMODEL OXIDE1 ; + ANTENNAGATEAREA 0.20085 LAYER Metal2 ; + ANTENNAMAXAREACAR 15.469256 LAYER Metal2 ; + PORT + LAYER Metal2 ; + RECT 339.64 0 339.9 0.26 ; + END + END B_DIN[11] + PIN B_DIN[4] + DIRECTION INPUT ; + USE SIGNAL ; + ANTENNAPARTIALMETALAREA 2.925 LAYER Metal2 ; + ANTENNAMODEL OXIDE1 ; + ANTENNAGATEAREA 0.20085 LAYER Metal2 ; + ANTENNAMAXAREACAR 15.469256 LAYER Metal2 ; + PORT + LAYER Metal2 ; + RECT 80.05 0 80.31 0.26 ; + END + END B_DIN[4] + PIN B_BIST_DIN[11] + DIRECTION INPUT ; + USE SIGNAL ; + ANTENNAPARTIALMETALAREA 2.9445 LAYER Metal2 ; + ANTENNAMODEL OXIDE1 ; + ANTENNAGATEAREA 0.20085 LAYER Metal2 ; + ANTENNAMAXAREACAR 15.929052 LAYER Metal2 ; + PORT + LAYER Metal2 ; + RECT 338.11 0 338.37 0.26 ; + END + END B_BIST_DIN[11] + PIN B_BIST_DIN[4] + DIRECTION INPUT ; + USE SIGNAL ; + ANTENNAPARTIALMETALAREA 2.9445 LAYER Metal2 ; + ANTENNAMODEL OXIDE1 ; + ANTENNAGATEAREA 0.20085 LAYER Metal2 ; + ANTENNAMAXAREACAR 15.929052 LAYER Metal2 ; + PORT + LAYER Metal2 ; + RECT 81.58 0 81.84 0.26 ; + END + END B_BIST_DIN[4] + PIN B_BM[11] + DIRECTION INPUT ; + USE SIGNAL ; + ANTENNAPARTIALMETALAREA 0.7007 LAYER Metal2 ; + ANTENNAMODEL OXIDE1 ; + ANTENNAGATEAREA 0.20085 LAYER Metal2 ; + ANTENNAMAXAREACAR 4.394822 LAYER Metal2 ; + PORT + LAYER Metal2 ; + RECT 331.125 0 331.385 0.26 ; + END + END B_BM[11] + PIN B_BM[4] + DIRECTION INPUT ; + USE SIGNAL ; + ANTENNAPARTIALMETALAREA 0.7007 LAYER Metal2 ; + ANTENNAMODEL OXIDE1 ; + ANTENNAGATEAREA 0.20085 LAYER Metal2 ; + ANTENNAMAXAREACAR 4.394822 LAYER Metal2 ; + PORT + LAYER Metal2 ; + RECT 88.565 0 88.825 0.26 ; + END + END B_BM[4] + PIN B_BIST_BM[11] + DIRECTION INPUT ; + USE SIGNAL ; + ANTENNAPARTIALMETALAREA 0.7007 LAYER Metal2 ; + ANTENNAMODEL OXIDE1 ; + ANTENNAGATEAREA 0.20085 LAYER Metal2 ; + ANTENNAMAXAREACAR 4.394822 LAYER Metal2 ; + PORT + LAYER Metal2 ; + RECT 332.655 0 332.915 0.26 ; + END + END B_BIST_BM[11] + PIN B_BIST_BM[4] + DIRECTION INPUT ; + USE SIGNAL ; + ANTENNAPARTIALMETALAREA 0.7007 LAYER Metal2 ; + ANTENNAMODEL OXIDE1 ; + ANTENNAGATEAREA 0.20085 LAYER Metal2 ; + ANTENNAMAXAREACAR 4.394822 LAYER Metal2 ; + PORT + LAYER Metal2 ; + RECT 87.035 0 87.295 0.26 ; + END + END B_BIST_BM[4] + PIN B_DOUT[11] + DIRECTION OUTPUT ; + USE SIGNAL ; + ANTENNAPARTIALMETALAREA 4.836 LAYER Metal2 ; + ANTENNADIFFAREA 0.988 LAYER Metal2 ; + PORT + LAYER Metal2 ; + RECT 346.78 0 347.04 0.26 ; + END + END B_DOUT[11] + PIN B_DOUT[4] + DIRECTION OUTPUT ; + USE SIGNAL ; + ANTENNAPARTIALMETALAREA 4.836 LAYER Metal2 ; + ANTENNADIFFAREA 0.988 LAYER Metal2 ; + PORT + LAYER Metal2 ; + RECT 72.91 0 73.17 0.26 ; + END + END B_DOUT[4] + PIN A_DIN[12] + DIRECTION INPUT ; + USE SIGNAL ; + ANTENNAPARTIALMETALAREA 3.9091 LAYER Metal2 ; + ANTENNAMODEL OXIDE1 ; + ANTENNAGATEAREA 0.20085 LAYER Metal2 ; + ANTENNAMAXAREACAR 20.368932 LAYER Metal2 ; + PORT + LAYER Metal2 ; + RECT 354.77 0 355.03 0.26 ; + END + END A_DIN[12] + PIN A_DIN[3] + DIRECTION INPUT ; + USE SIGNAL ; + ANTENNAPARTIALMETALAREA 3.9091 LAYER Metal2 ; + ANTENNAMODEL OXIDE1 ; + ANTENNAGATEAREA 0.20085 LAYER Metal2 ; + ANTENNAMAXAREACAR 20.368932 LAYER Metal2 ; + PORT + LAYER Metal2 ; + RECT 64.92 0 65.18 0.26 ; + END + END A_DIN[3] + PIN A_BIST_DIN[12] + DIRECTION INPUT ; + USE SIGNAL ; + ANTENNAPARTIALMETALAREA 4.136375 LAYER Metal2 ; + ANTENNAMODEL OXIDE1 ; + ANTENNAGATEAREA 0.20085 LAYER Metal2 ; + ANTENNAMAXAREACAR 21.874907 LAYER Metal2 ; + PORT + LAYER Metal2 ; + RECT 355.28 0 355.54 0.26 ; + END + END A_BIST_DIN[12] + PIN A_BIST_DIN[3] + DIRECTION INPUT ; + USE SIGNAL ; + ANTENNAPARTIALMETALAREA 4.136375 LAYER Metal2 ; + ANTENNAMODEL OXIDE1 ; + ANTENNAGATEAREA 0.20085 LAYER Metal2 ; + ANTENNAMAXAREACAR 21.874907 LAYER Metal2 ; + PORT + LAYER Metal2 ; + RECT 64.41 0 64.67 0.26 ; + END + END A_BIST_DIN[3] + PIN A_BM[12] + DIRECTION INPUT ; + USE SIGNAL ; + ANTENNAPARTIALMETALAREA 1.7264 LAYER Metal2 ; + ANTENNAMODEL OXIDE1 ; + ANTENNAGATEAREA 0.20085 LAYER Metal2 ; + ANTENNAMAXAREACAR 9.501618 LAYER Metal2 ; + PORT + LAYER Metal2 ; + RECT 363.44 0 363.7 0.26 ; + END + END A_BM[12] + PIN A_BM[3] + DIRECTION INPUT ; + USE SIGNAL ; + ANTENNAPARTIALMETALAREA 1.7264 LAYER Metal2 ; + ANTENNAMODEL OXIDE1 ; + ANTENNAGATEAREA 0.20085 LAYER Metal2 ; + ANTENNAMAXAREACAR 9.501618 LAYER Metal2 ; + PORT + LAYER Metal2 ; + RECT 56.25 0 56.51 0.26 ; + END + END A_BM[3] + PIN A_BIST_BM[12] + DIRECTION INPUT ; + USE SIGNAL ; + ANTENNAPARTIALMETALAREA 1.7602 LAYER Metal2 ; + ANTENNAMODEL OXIDE1 ; + ANTENNAGATEAREA 0.20085 LAYER Metal2 ; + ANTENNAMAXAREACAR 9.678367 LAYER Metal2 ; + PORT + LAYER Metal2 ; + RECT 362.065 0 362.325 0.26 ; + END + END A_BIST_BM[12] + PIN A_BIST_BM[3] + DIRECTION INPUT ; + USE SIGNAL ; + ANTENNAPARTIALMETALAREA 1.7602 LAYER Metal2 ; + ANTENNAMODEL OXIDE1 ; + ANTENNAGATEAREA 0.20085 LAYER Metal2 ; + ANTENNAMAXAREACAR 9.678367 LAYER Metal2 ; + PORT + LAYER Metal2 ; + RECT 57.625 0 57.885 0.26 ; + END + END A_BIST_BM[3] + PIN A_DOUT[12] + DIRECTION OUTPUT ; + USE SIGNAL ; + ANTENNAPARTIALMETALAREA 4.8256 LAYER Metal2 ; + ANTENNADIFFAREA 0.988 LAYER Metal2 ; + PORT + LAYER Metal2 ; + RECT 347.63 0 347.89 0.26 ; + END + END A_DOUT[12] + PIN A_DOUT[3] + DIRECTION OUTPUT ; + USE SIGNAL ; + ANTENNAPARTIALMETALAREA 4.8256 LAYER Metal2 ; + ANTENNADIFFAREA 0.988 LAYER Metal2 ; + PORT + LAYER Metal2 ; + RECT 72.06 0 72.32 0.26 ; + END + END A_DOUT[3] + PIN B_DIN[12] + DIRECTION INPUT ; + USE SIGNAL ; + ANTENNAPARTIALMETALAREA 2.925 LAYER Metal2 ; + ANTENNAMODEL OXIDE1 ; + ANTENNAGATEAREA 0.20085 LAYER Metal2 ; + ANTENNAMAXAREACAR 15.469256 LAYER Metal2 ; + PORT + LAYER Metal2 ; + RECT 357.32 0 357.58 0.26 ; + END + END B_DIN[12] + PIN B_DIN[3] + DIRECTION INPUT ; + USE SIGNAL ; + ANTENNAPARTIALMETALAREA 2.925 LAYER Metal2 ; + ANTENNAMODEL OXIDE1 ; + ANTENNAGATEAREA 0.20085 LAYER Metal2 ; + ANTENNAMAXAREACAR 15.469256 LAYER Metal2 ; + PORT + LAYER Metal2 ; + RECT 62.37 0 62.63 0.26 ; + END + END B_DIN[3] + PIN B_BIST_DIN[12] + DIRECTION INPUT ; + USE SIGNAL ; + ANTENNAPARTIALMETALAREA 2.9445 LAYER Metal2 ; + ANTENNAMODEL OXIDE1 ; + ANTENNAGATEAREA 0.20085 LAYER Metal2 ; + ANTENNAMAXAREACAR 15.929052 LAYER Metal2 ; + PORT + LAYER Metal2 ; + RECT 355.79 0 356.05 0.26 ; + END + END B_BIST_DIN[12] + PIN B_BIST_DIN[3] + DIRECTION INPUT ; + USE SIGNAL ; + ANTENNAPARTIALMETALAREA 2.9445 LAYER Metal2 ; + ANTENNAMODEL OXIDE1 ; + ANTENNAGATEAREA 0.20085 LAYER Metal2 ; + ANTENNAMAXAREACAR 15.929052 LAYER Metal2 ; + PORT + LAYER Metal2 ; + RECT 63.9 0 64.16 0.26 ; + END + END B_BIST_DIN[3] + PIN B_BM[12] + DIRECTION INPUT ; + USE SIGNAL ; + ANTENNAPARTIALMETALAREA 0.7007 LAYER Metal2 ; + ANTENNAMODEL OXIDE1 ; + ANTENNAGATEAREA 0.20085 LAYER Metal2 ; + ANTENNAMAXAREACAR 4.394822 LAYER Metal2 ; + PORT + LAYER Metal2 ; + RECT 348.805 0 349.065 0.26 ; + END + END B_BM[12] + PIN B_BM[3] + DIRECTION INPUT ; + USE SIGNAL ; + ANTENNAPARTIALMETALAREA 0.7007 LAYER Metal2 ; + ANTENNAMODEL OXIDE1 ; + ANTENNAGATEAREA 0.20085 LAYER Metal2 ; + ANTENNAMAXAREACAR 4.394822 LAYER Metal2 ; + PORT + LAYER Metal2 ; + RECT 70.885 0 71.145 0.26 ; + END + END B_BM[3] + PIN B_BIST_BM[12] + DIRECTION INPUT ; + USE SIGNAL ; + ANTENNAPARTIALMETALAREA 0.7007 LAYER Metal2 ; + ANTENNAMODEL OXIDE1 ; + ANTENNAGATEAREA 0.20085 LAYER Metal2 ; + ANTENNAMAXAREACAR 4.394822 LAYER Metal2 ; + PORT + LAYER Metal2 ; + RECT 350.335 0 350.595 0.26 ; + END + END B_BIST_BM[12] + PIN B_BIST_BM[3] + DIRECTION INPUT ; + USE SIGNAL ; + ANTENNAPARTIALMETALAREA 0.7007 LAYER Metal2 ; + ANTENNAMODEL OXIDE1 ; + ANTENNAGATEAREA 0.20085 LAYER Metal2 ; + ANTENNAMAXAREACAR 4.394822 LAYER Metal2 ; + PORT + LAYER Metal2 ; + RECT 69.355 0 69.615 0.26 ; + END + END B_BIST_BM[3] + PIN B_DOUT[12] + DIRECTION OUTPUT ; + USE SIGNAL ; + ANTENNAPARTIALMETALAREA 4.836 LAYER Metal2 ; + ANTENNADIFFAREA 0.988 LAYER Metal2 ; + PORT + LAYER Metal2 ; + RECT 364.46 0 364.72 0.26 ; + END + END B_DOUT[12] + PIN B_DOUT[3] + DIRECTION OUTPUT ; + USE SIGNAL ; + ANTENNAPARTIALMETALAREA 4.836 LAYER Metal2 ; + ANTENNADIFFAREA 0.988 LAYER Metal2 ; + PORT + LAYER Metal2 ; + RECT 55.23 0 55.49 0.26 ; + END + END B_DOUT[3] + PIN A_DIN[13] + DIRECTION INPUT ; + USE SIGNAL ; + ANTENNAPARTIALMETALAREA 3.9091 LAYER Metal2 ; + ANTENNAMODEL OXIDE1 ; + ANTENNAGATEAREA 0.20085 LAYER Metal2 ; + ANTENNAMAXAREACAR 20.368932 LAYER Metal2 ; + PORT + LAYER Metal2 ; + RECT 372.45 0 372.71 0.26 ; + END + END A_DIN[13] + PIN A_DIN[2] + DIRECTION INPUT ; + USE SIGNAL ; + ANTENNAPARTIALMETALAREA 3.9091 LAYER Metal2 ; + ANTENNAMODEL OXIDE1 ; + ANTENNAGATEAREA 0.20085 LAYER Metal2 ; + ANTENNAMAXAREACAR 20.368932 LAYER Metal2 ; + PORT + LAYER Metal2 ; + RECT 47.24 0 47.5 0.26 ; + END + END A_DIN[2] + PIN A_BIST_DIN[13] + DIRECTION INPUT ; + USE SIGNAL ; + ANTENNAPARTIALMETALAREA 4.136375 LAYER Metal2 ; + ANTENNAMODEL OXIDE1 ; + ANTENNAGATEAREA 0.20085 LAYER Metal2 ; + ANTENNAMAXAREACAR 21.874907 LAYER Metal2 ; + PORT + LAYER Metal2 ; + RECT 372.96 0 373.22 0.26 ; + END + END A_BIST_DIN[13] + PIN A_BIST_DIN[2] + DIRECTION INPUT ; + USE SIGNAL ; + ANTENNAPARTIALMETALAREA 4.136375 LAYER Metal2 ; + ANTENNAMODEL OXIDE1 ; + ANTENNAGATEAREA 0.20085 LAYER Metal2 ; + ANTENNAMAXAREACAR 21.874907 LAYER Metal2 ; + PORT + LAYER Metal2 ; + RECT 46.73 0 46.99 0.26 ; + END + END A_BIST_DIN[2] + PIN A_BM[13] + DIRECTION INPUT ; + USE SIGNAL ; + ANTENNAPARTIALMETALAREA 1.7264 LAYER Metal2 ; + ANTENNAMODEL OXIDE1 ; + ANTENNAGATEAREA 0.20085 LAYER Metal2 ; + ANTENNAMAXAREACAR 9.501618 LAYER Metal2 ; + PORT + LAYER Metal2 ; + RECT 381.12 0 381.38 0.26 ; + END + END A_BM[13] + PIN A_BM[2] + DIRECTION INPUT ; + USE SIGNAL ; + ANTENNAPARTIALMETALAREA 1.7264 LAYER Metal2 ; + ANTENNAMODEL OXIDE1 ; + ANTENNAGATEAREA 0.20085 LAYER Metal2 ; + ANTENNAMAXAREACAR 9.501618 LAYER Metal2 ; + PORT + LAYER Metal2 ; + RECT 38.57 0 38.83 0.26 ; + END + END A_BM[2] + PIN A_BIST_BM[13] + DIRECTION INPUT ; + USE SIGNAL ; + ANTENNAPARTIALMETALAREA 1.7602 LAYER Metal2 ; + ANTENNAMODEL OXIDE1 ; + ANTENNAGATEAREA 0.20085 LAYER Metal2 ; + ANTENNAMAXAREACAR 9.678367 LAYER Metal2 ; + PORT + LAYER Metal2 ; + RECT 379.745 0 380.005 0.26 ; + END + END A_BIST_BM[13] + PIN A_BIST_BM[2] + DIRECTION INPUT ; + USE SIGNAL ; + ANTENNAPARTIALMETALAREA 1.7602 LAYER Metal2 ; + ANTENNAMODEL OXIDE1 ; + ANTENNAGATEAREA 0.20085 LAYER Metal2 ; + ANTENNAMAXAREACAR 9.678367 LAYER Metal2 ; + PORT + LAYER Metal2 ; + RECT 39.945 0 40.205 0.26 ; + END + END A_BIST_BM[2] + PIN A_DOUT[13] + DIRECTION OUTPUT ; + USE SIGNAL ; + ANTENNAPARTIALMETALAREA 4.8256 LAYER Metal2 ; + ANTENNADIFFAREA 0.988 LAYER Metal2 ; + PORT + LAYER Metal2 ; + RECT 365.31 0 365.57 0.26 ; + END + END A_DOUT[13] + PIN A_DOUT[2] + DIRECTION OUTPUT ; + USE SIGNAL ; + ANTENNAPARTIALMETALAREA 4.8256 LAYER Metal2 ; + ANTENNADIFFAREA 0.988 LAYER Metal2 ; + PORT + LAYER Metal2 ; + RECT 54.38 0 54.64 0.26 ; + END + END A_DOUT[2] + PIN B_DIN[13] + DIRECTION INPUT ; + USE SIGNAL ; + ANTENNAPARTIALMETALAREA 2.925 LAYER Metal2 ; + ANTENNAMODEL OXIDE1 ; + ANTENNAGATEAREA 0.20085 LAYER Metal2 ; + ANTENNAMAXAREACAR 15.469256 LAYER Metal2 ; + PORT + LAYER Metal2 ; + RECT 375 0 375.26 0.26 ; + END + END B_DIN[13] + PIN B_DIN[2] + DIRECTION INPUT ; + USE SIGNAL ; + ANTENNAPARTIALMETALAREA 2.925 LAYER Metal2 ; + ANTENNAMODEL OXIDE1 ; + ANTENNAGATEAREA 0.20085 LAYER Metal2 ; + ANTENNAMAXAREACAR 15.469256 LAYER Metal2 ; + PORT + LAYER Metal2 ; + RECT 44.69 0 44.95 0.26 ; + END + END B_DIN[2] + PIN B_BIST_DIN[13] + DIRECTION INPUT ; + USE SIGNAL ; + ANTENNAPARTIALMETALAREA 2.9445 LAYER Metal2 ; + ANTENNAMODEL OXIDE1 ; + ANTENNAGATEAREA 0.20085 LAYER Metal2 ; + ANTENNAMAXAREACAR 15.929052 LAYER Metal2 ; + PORT + LAYER Metal2 ; + RECT 373.47 0 373.73 0.26 ; + END + END B_BIST_DIN[13] + PIN B_BIST_DIN[2] + DIRECTION INPUT ; + USE SIGNAL ; + ANTENNAPARTIALMETALAREA 2.9445 LAYER Metal2 ; + ANTENNAMODEL OXIDE1 ; + ANTENNAGATEAREA 0.20085 LAYER Metal2 ; + ANTENNAMAXAREACAR 15.929052 LAYER Metal2 ; + PORT + LAYER Metal2 ; + RECT 46.22 0 46.48 0.26 ; + END + END B_BIST_DIN[2] + PIN B_BM[13] + DIRECTION INPUT ; + USE SIGNAL ; + ANTENNAPARTIALMETALAREA 0.7007 LAYER Metal2 ; + ANTENNAMODEL OXIDE1 ; + ANTENNAGATEAREA 0.20085 LAYER Metal2 ; + ANTENNAMAXAREACAR 4.394822 LAYER Metal2 ; + PORT + LAYER Metal2 ; + RECT 366.485 0 366.745 0.26 ; + END + END B_BM[13] + PIN B_BM[2] + DIRECTION INPUT ; + USE SIGNAL ; + ANTENNAPARTIALMETALAREA 0.7007 LAYER Metal2 ; + ANTENNAMODEL OXIDE1 ; + ANTENNAGATEAREA 0.20085 LAYER Metal2 ; + ANTENNAMAXAREACAR 4.394822 LAYER Metal2 ; + PORT + LAYER Metal2 ; + RECT 53.205 0 53.465 0.26 ; + END + END B_BM[2] + PIN B_BIST_BM[13] + DIRECTION INPUT ; + USE SIGNAL ; + ANTENNAPARTIALMETALAREA 0.7007 LAYER Metal2 ; + ANTENNAMODEL OXIDE1 ; + ANTENNAGATEAREA 0.20085 LAYER Metal2 ; + ANTENNAMAXAREACAR 4.394822 LAYER Metal2 ; + PORT + LAYER Metal2 ; + RECT 368.015 0 368.275 0.26 ; + END + END B_BIST_BM[13] + PIN B_BIST_BM[2] + DIRECTION INPUT ; + USE SIGNAL ; + ANTENNAPARTIALMETALAREA 0.7007 LAYER Metal2 ; + ANTENNAMODEL OXIDE1 ; + ANTENNAGATEAREA 0.20085 LAYER Metal2 ; + ANTENNAMAXAREACAR 4.394822 LAYER Metal2 ; + PORT + LAYER Metal2 ; + RECT 51.675 0 51.935 0.26 ; + END + END B_BIST_BM[2] + PIN B_DOUT[13] + DIRECTION OUTPUT ; + USE SIGNAL ; + ANTENNAPARTIALMETALAREA 4.836 LAYER Metal2 ; + ANTENNADIFFAREA 0.988 LAYER Metal2 ; + PORT + LAYER Metal2 ; + RECT 382.14 0 382.4 0.26 ; + END + END B_DOUT[13] + PIN B_DOUT[2] + DIRECTION OUTPUT ; + USE SIGNAL ; + ANTENNAPARTIALMETALAREA 4.836 LAYER Metal2 ; + ANTENNADIFFAREA 0.988 LAYER Metal2 ; + PORT + LAYER Metal2 ; + RECT 37.55 0 37.81 0.26 ; + END + END B_DOUT[2] + PIN A_DIN[14] + DIRECTION INPUT ; + USE SIGNAL ; + ANTENNAPARTIALMETALAREA 3.9091 LAYER Metal2 ; + ANTENNAMODEL OXIDE1 ; + ANTENNAGATEAREA 0.20085 LAYER Metal2 ; + ANTENNAMAXAREACAR 20.368932 LAYER Metal2 ; + PORT + LAYER Metal2 ; + RECT 390.13 0 390.39 0.26 ; + END + END A_DIN[14] + PIN A_DIN[1] + DIRECTION INPUT ; + USE SIGNAL ; + ANTENNAPARTIALMETALAREA 3.9091 LAYER Metal2 ; + ANTENNAMODEL OXIDE1 ; + ANTENNAGATEAREA 0.20085 LAYER Metal2 ; + ANTENNAMAXAREACAR 20.368932 LAYER Metal2 ; + PORT + LAYER Metal2 ; + RECT 29.56 0 29.82 0.26 ; + END + END A_DIN[1] + PIN A_BIST_DIN[14] + DIRECTION INPUT ; + USE SIGNAL ; + ANTENNAPARTIALMETALAREA 4.136375 LAYER Metal2 ; + ANTENNAMODEL OXIDE1 ; + ANTENNAGATEAREA 0.20085 LAYER Metal2 ; + ANTENNAMAXAREACAR 21.874907 LAYER Metal2 ; + PORT + LAYER Metal2 ; + RECT 390.64 0 390.9 0.26 ; + END + END A_BIST_DIN[14] + PIN A_BIST_DIN[1] + DIRECTION INPUT ; + USE SIGNAL ; + ANTENNAPARTIALMETALAREA 4.136375 LAYER Metal2 ; + ANTENNAMODEL OXIDE1 ; + ANTENNAGATEAREA 0.20085 LAYER Metal2 ; + ANTENNAMAXAREACAR 21.874907 LAYER Metal2 ; + PORT + LAYER Metal2 ; + RECT 29.05 0 29.31 0.26 ; + END + END A_BIST_DIN[1] + PIN A_BM[14] + DIRECTION INPUT ; + USE SIGNAL ; + ANTENNAPARTIALMETALAREA 1.7264 LAYER Metal2 ; + ANTENNAMODEL OXIDE1 ; + ANTENNAGATEAREA 0.20085 LAYER Metal2 ; + ANTENNAMAXAREACAR 9.501618 LAYER Metal2 ; + PORT + LAYER Metal2 ; + RECT 398.8 0 399.06 0.26 ; + END + END A_BM[14] + PIN A_BM[1] + DIRECTION INPUT ; + USE SIGNAL ; + ANTENNAPARTIALMETALAREA 1.7264 LAYER Metal2 ; + ANTENNAMODEL OXIDE1 ; + ANTENNAGATEAREA 0.20085 LAYER Metal2 ; + ANTENNAMAXAREACAR 9.501618 LAYER Metal2 ; + PORT + LAYER Metal2 ; + RECT 20.89 0 21.15 0.26 ; + END + END A_BM[1] + PIN A_BIST_BM[14] + DIRECTION INPUT ; + USE SIGNAL ; + ANTENNAPARTIALMETALAREA 1.7602 LAYER Metal2 ; + ANTENNAMODEL OXIDE1 ; + ANTENNAGATEAREA 0.20085 LAYER Metal2 ; + ANTENNAMAXAREACAR 9.678367 LAYER Metal2 ; + PORT + LAYER Metal2 ; + RECT 397.425 0 397.685 0.26 ; + END + END A_BIST_BM[14] + PIN A_BIST_BM[1] + DIRECTION INPUT ; + USE SIGNAL ; + ANTENNAPARTIALMETALAREA 1.7602 LAYER Metal2 ; + ANTENNAMODEL OXIDE1 ; + ANTENNAGATEAREA 0.20085 LAYER Metal2 ; + ANTENNAMAXAREACAR 9.678367 LAYER Metal2 ; + PORT + LAYER Metal2 ; + RECT 22.265 0 22.525 0.26 ; + END + END A_BIST_BM[1] + PIN A_DOUT[14] + DIRECTION OUTPUT ; + USE SIGNAL ; + ANTENNAPARTIALMETALAREA 4.8256 LAYER Metal2 ; + ANTENNADIFFAREA 0.988 LAYER Metal2 ; + PORT + LAYER Metal2 ; + RECT 382.99 0 383.25 0.26 ; + END + END A_DOUT[14] + PIN A_DOUT[1] + DIRECTION OUTPUT ; + USE SIGNAL ; + ANTENNAPARTIALMETALAREA 4.8256 LAYER Metal2 ; + ANTENNADIFFAREA 0.988 LAYER Metal2 ; + PORT + LAYER Metal2 ; + RECT 36.7 0 36.96 0.26 ; + END + END A_DOUT[1] + PIN B_DIN[14] + DIRECTION INPUT ; + USE SIGNAL ; + ANTENNAPARTIALMETALAREA 2.925 LAYER Metal2 ; + ANTENNAMODEL OXIDE1 ; + ANTENNAGATEAREA 0.20085 LAYER Metal2 ; + ANTENNAMAXAREACAR 15.469256 LAYER Metal2 ; + PORT + LAYER Metal2 ; + RECT 392.68 0 392.94 0.26 ; + END + END B_DIN[14] + PIN B_DIN[1] + DIRECTION INPUT ; + USE SIGNAL ; + ANTENNAPARTIALMETALAREA 2.925 LAYER Metal2 ; + ANTENNAMODEL OXIDE1 ; + ANTENNAGATEAREA 0.20085 LAYER Metal2 ; + ANTENNAMAXAREACAR 15.469256 LAYER Metal2 ; + PORT + LAYER Metal2 ; + RECT 27.01 0 27.27 0.26 ; + END + END B_DIN[1] + PIN B_BIST_DIN[14] + DIRECTION INPUT ; + USE SIGNAL ; + ANTENNAPARTIALMETALAREA 2.9445 LAYER Metal2 ; + ANTENNAMODEL OXIDE1 ; + ANTENNAGATEAREA 0.20085 LAYER Metal2 ; + ANTENNAMAXAREACAR 15.929052 LAYER Metal2 ; + PORT + LAYER Metal2 ; + RECT 391.15 0 391.41 0.26 ; + END + END B_BIST_DIN[14] + PIN B_BIST_DIN[1] + DIRECTION INPUT ; + USE SIGNAL ; + ANTENNAPARTIALMETALAREA 2.9445 LAYER Metal2 ; + ANTENNAMODEL OXIDE1 ; + ANTENNAGATEAREA 0.20085 LAYER Metal2 ; + ANTENNAMAXAREACAR 15.929052 LAYER Metal2 ; + PORT + LAYER Metal2 ; + RECT 28.54 0 28.8 0.26 ; + END + END B_BIST_DIN[1] + PIN B_BM[14] + DIRECTION INPUT ; + USE SIGNAL ; + ANTENNAPARTIALMETALAREA 0.7007 LAYER Metal2 ; + ANTENNAMODEL OXIDE1 ; + ANTENNAGATEAREA 0.20085 LAYER Metal2 ; + ANTENNAMAXAREACAR 4.394822 LAYER Metal2 ; + PORT + LAYER Metal2 ; + RECT 384.165 0 384.425 0.26 ; + END + END B_BM[14] + PIN B_BM[1] + DIRECTION INPUT ; + USE SIGNAL ; + ANTENNAPARTIALMETALAREA 0.7007 LAYER Metal2 ; + ANTENNAMODEL OXIDE1 ; + ANTENNAGATEAREA 0.20085 LAYER Metal2 ; + ANTENNAMAXAREACAR 4.394822 LAYER Metal2 ; + PORT + LAYER Metal2 ; + RECT 35.525 0 35.785 0.26 ; + END + END B_BM[1] + PIN B_BIST_BM[14] + DIRECTION INPUT ; + USE SIGNAL ; + ANTENNAPARTIALMETALAREA 0.7007 LAYER Metal2 ; + ANTENNAMODEL OXIDE1 ; + ANTENNAGATEAREA 0.20085 LAYER Metal2 ; + ANTENNAMAXAREACAR 4.394822 LAYER Metal2 ; + PORT + LAYER Metal2 ; + RECT 385.695 0 385.955 0.26 ; + END + END B_BIST_BM[14] + PIN B_BIST_BM[1] + DIRECTION INPUT ; + USE SIGNAL ; + ANTENNAPARTIALMETALAREA 0.7007 LAYER Metal2 ; + ANTENNAMODEL OXIDE1 ; + ANTENNAGATEAREA 0.20085 LAYER Metal2 ; + ANTENNAMAXAREACAR 4.394822 LAYER Metal2 ; + PORT + LAYER Metal2 ; + RECT 33.995 0 34.255 0.26 ; + END + END B_BIST_BM[1] + PIN B_DOUT[14] + DIRECTION OUTPUT ; + USE SIGNAL ; + ANTENNAPARTIALMETALAREA 4.836 LAYER Metal2 ; + ANTENNADIFFAREA 0.988 LAYER Metal2 ; + PORT + LAYER Metal2 ; + RECT 399.82 0 400.08 0.26 ; + END + END B_DOUT[14] + PIN B_DOUT[1] + DIRECTION OUTPUT ; + USE SIGNAL ; + ANTENNAPARTIALMETALAREA 4.836 LAYER Metal2 ; + ANTENNADIFFAREA 0.988 LAYER Metal2 ; + PORT + LAYER Metal2 ; + RECT 19.87 0 20.13 0.26 ; + END + END B_DOUT[1] + PIN A_DIN[15] + DIRECTION INPUT ; + USE SIGNAL ; + ANTENNAPARTIALMETALAREA 3.9091 LAYER Metal2 ; + ANTENNAMODEL OXIDE1 ; + ANTENNAGATEAREA 0.20085 LAYER Metal2 ; + ANTENNAMAXAREACAR 20.368932 LAYER Metal2 ; + PORT + LAYER Metal2 ; + RECT 407.81 0 408.07 0.26 ; + END + END A_DIN[15] + PIN A_DIN[0] + DIRECTION INPUT ; + USE SIGNAL ; + ANTENNAPARTIALMETALAREA 3.9091 LAYER Metal2 ; + ANTENNAMODEL OXIDE1 ; + ANTENNAGATEAREA 0.20085 LAYER Metal2 ; + ANTENNAMAXAREACAR 20.368932 LAYER Metal2 ; + PORT + LAYER Metal2 ; + RECT 11.88 0 12.14 0.26 ; + END + END A_DIN[0] + PIN A_BIST_DIN[15] + DIRECTION INPUT ; + USE SIGNAL ; + ANTENNAPARTIALMETALAREA 4.136375 LAYER Metal2 ; + ANTENNAMODEL OXIDE1 ; + ANTENNAGATEAREA 0.20085 LAYER Metal2 ; + ANTENNAMAXAREACAR 21.874907 LAYER Metal2 ; + PORT + LAYER Metal2 ; + RECT 408.32 0 408.58 0.26 ; + END + END A_BIST_DIN[15] + PIN A_BIST_DIN[0] + DIRECTION INPUT ; + USE SIGNAL ; + ANTENNAPARTIALMETALAREA 4.136375 LAYER Metal2 ; + ANTENNAMODEL OXIDE1 ; + ANTENNAGATEAREA 0.20085 LAYER Metal2 ; + ANTENNAMAXAREACAR 21.874907 LAYER Metal2 ; + PORT + LAYER Metal2 ; + RECT 11.37 0 11.63 0.26 ; + END + END A_BIST_DIN[0] + PIN A_BM[15] + DIRECTION INPUT ; + USE SIGNAL ; + ANTENNAPARTIALMETALAREA 1.7264 LAYER Metal2 ; + ANTENNAMODEL OXIDE1 ; + ANTENNAGATEAREA 0.20085 LAYER Metal2 ; + ANTENNAMAXAREACAR 9.501618 LAYER Metal2 ; + PORT + LAYER Metal2 ; + RECT 416.48 0 416.74 0.26 ; + END + END A_BM[15] + PIN A_BM[0] + DIRECTION INPUT ; + USE SIGNAL ; + ANTENNAPARTIALMETALAREA 1.7264 LAYER Metal2 ; + ANTENNAMODEL OXIDE1 ; + ANTENNAGATEAREA 0.20085 LAYER Metal2 ; + ANTENNAMAXAREACAR 9.501618 LAYER Metal2 ; + PORT + LAYER Metal2 ; + RECT 3.21 0 3.47 0.26 ; + END + END A_BM[0] + PIN A_BIST_BM[15] + DIRECTION INPUT ; + USE SIGNAL ; + ANTENNAPARTIALMETALAREA 1.7602 LAYER Metal2 ; + ANTENNAMODEL OXIDE1 ; + ANTENNAGATEAREA 0.20085 LAYER Metal2 ; + ANTENNAMAXAREACAR 9.678367 LAYER Metal2 ; + PORT + LAYER Metal2 ; + RECT 415.105 0 415.365 0.26 ; + END + END A_BIST_BM[15] + PIN A_BIST_BM[0] + DIRECTION INPUT ; + USE SIGNAL ; + ANTENNAPARTIALMETALAREA 1.7602 LAYER Metal2 ; + ANTENNAMODEL OXIDE1 ; + ANTENNAGATEAREA 0.20085 LAYER Metal2 ; + ANTENNAMAXAREACAR 9.678367 LAYER Metal2 ; + PORT + LAYER Metal2 ; + RECT 4.585 0 4.845 0.26 ; + END + END A_BIST_BM[0] + PIN A_DOUT[15] + DIRECTION OUTPUT ; + USE SIGNAL ; + ANTENNAPARTIALMETALAREA 4.8256 LAYER Metal2 ; + ANTENNADIFFAREA 0.988 LAYER Metal2 ; + PORT + LAYER Metal2 ; + RECT 400.67 0 400.93 0.26 ; + END + END A_DOUT[15] + PIN A_DOUT[0] + DIRECTION OUTPUT ; + USE SIGNAL ; + ANTENNAPARTIALMETALAREA 4.8256 LAYER Metal2 ; + ANTENNADIFFAREA 0.988 LAYER Metal2 ; + PORT + LAYER Metal2 ; + RECT 19.02 0 19.28 0.26 ; + END + END A_DOUT[0] + PIN B_DIN[15] + DIRECTION INPUT ; + USE SIGNAL ; + ANTENNAPARTIALMETALAREA 2.925 LAYER Metal2 ; + ANTENNAMODEL OXIDE1 ; + ANTENNAGATEAREA 0.20085 LAYER Metal2 ; + ANTENNAMAXAREACAR 15.469256 LAYER Metal2 ; + PORT + LAYER Metal2 ; + RECT 410.36 0 410.62 0.26 ; + END + END B_DIN[15] + PIN B_DIN[0] + DIRECTION INPUT ; + USE SIGNAL ; + ANTENNAPARTIALMETALAREA 2.925 LAYER Metal2 ; + ANTENNAMODEL OXIDE1 ; + ANTENNAGATEAREA 0.20085 LAYER Metal2 ; + ANTENNAMAXAREACAR 15.469256 LAYER Metal2 ; + PORT + LAYER Metal2 ; + RECT 9.33 0 9.59 0.26 ; + END + END B_DIN[0] + PIN B_BIST_DIN[15] + DIRECTION INPUT ; + USE SIGNAL ; + ANTENNAPARTIALMETALAREA 2.9445 LAYER Metal2 ; + ANTENNAMODEL OXIDE1 ; + ANTENNAGATEAREA 0.20085 LAYER Metal2 ; + ANTENNAMAXAREACAR 15.929052 LAYER Metal2 ; + PORT + LAYER Metal2 ; + RECT 408.83 0 409.09 0.26 ; + END + END B_BIST_DIN[15] + PIN B_BIST_DIN[0] + DIRECTION INPUT ; + USE SIGNAL ; + ANTENNAPARTIALMETALAREA 2.9445 LAYER Metal2 ; + ANTENNAMODEL OXIDE1 ; + ANTENNAGATEAREA 0.20085 LAYER Metal2 ; + ANTENNAMAXAREACAR 15.929052 LAYER Metal2 ; + PORT + LAYER Metal2 ; + RECT 10.86 0 11.12 0.26 ; + END + END B_BIST_DIN[0] + PIN B_BM[15] + DIRECTION INPUT ; + USE SIGNAL ; + ANTENNAPARTIALMETALAREA 0.7007 LAYER Metal2 ; + ANTENNAMODEL OXIDE1 ; + ANTENNAGATEAREA 0.20085 LAYER Metal2 ; + ANTENNAMAXAREACAR 4.394822 LAYER Metal2 ; + PORT + LAYER Metal2 ; + RECT 401.845 0 402.105 0.26 ; + END + END B_BM[15] + PIN B_BM[0] + DIRECTION INPUT ; + USE SIGNAL ; + ANTENNAPARTIALMETALAREA 0.7007 LAYER Metal2 ; + ANTENNAMODEL OXIDE1 ; + ANTENNAGATEAREA 0.20085 LAYER Metal2 ; + ANTENNAMAXAREACAR 4.394822 LAYER Metal2 ; + PORT + LAYER Metal2 ; + RECT 17.845 0 18.105 0.26 ; + END + END B_BM[0] + PIN B_BIST_BM[15] + DIRECTION INPUT ; + USE SIGNAL ; + ANTENNAPARTIALMETALAREA 0.7007 LAYER Metal2 ; + ANTENNAMODEL OXIDE1 ; + ANTENNAGATEAREA 0.20085 LAYER Metal2 ; + ANTENNAMAXAREACAR 4.394822 LAYER Metal2 ; + PORT + LAYER Metal2 ; + RECT 403.375 0 403.635 0.26 ; + END + END B_BIST_BM[15] + PIN B_BIST_BM[0] + DIRECTION INPUT ; + USE SIGNAL ; + ANTENNAPARTIALMETALAREA 0.7007 LAYER Metal2 ; + ANTENNAMODEL OXIDE1 ; + ANTENNAGATEAREA 0.20085 LAYER Metal2 ; + ANTENNAMAXAREACAR 4.394822 LAYER Metal2 ; + PORT + LAYER Metal2 ; + RECT 16.315 0 16.575 0.26 ; + END + END B_BIST_BM[0] + PIN B_DOUT[15] + DIRECTION OUTPUT ; + USE SIGNAL ; + ANTENNAPARTIALMETALAREA 4.836 LAYER Metal2 ; + ANTENNADIFFAREA 0.988 LAYER Metal2 ; + PORT + LAYER Metal2 ; + RECT 417.5 0 417.76 0.26 ; + END + END B_DOUT[15] + PIN B_DOUT[0] + DIRECTION OUTPUT ; + USE SIGNAL ; + ANTENNAPARTIALMETALAREA 4.836 LAYER Metal2 ; + ANTENNADIFFAREA 0.988 LAYER Metal2 ; + PORT + LAYER Metal2 ; + RECT 2.19 0 2.45 0.26 ; + END + END B_DOUT[0] + PIN A_ADDR[0] + DIRECTION INPUT ; + USE SIGNAL ; + ANTENNAPARTIALMETALAREA 8.7685 LAYER Metal2 ; + ANTENNAMODEL OXIDE1 ; + ANTENNAGATEAREA 0.20085 LAYER Metal2 ; + ANTENNAMAXAREACAR 44.563107 LAYER Metal2 ; + PORT + LAYER Metal2 ; + RECT 226.065 0 226.325 0.26 ; + END + END A_ADDR[0] + PIN A_BIST_ADDR[0] + DIRECTION INPUT ; + USE SIGNAL ; + ANTENNAPARTIALMETALAREA 9.8293 LAYER Metal2 ; + ANTENNAMODEL OXIDE1 ; + ANTENNAGATEAREA 0.20085 LAYER Metal2 ; + ANTENNAMAXAREACAR 49.84466 LAYER Metal2 ; + PORT + LAYER Metal2 ; + RECT 231.675 0 231.935 0.26 ; + END + END A_BIST_ADDR[0] + PIN B_ADDR[0] + DIRECTION INPUT ; + USE SIGNAL ; + ANTENNAPARTIALMETALAREA 8.7685 LAYER Metal2 ; + ANTENNAMODEL OXIDE1 ; + ANTENNAGATEAREA 0.20085 LAYER Metal2 ; + ANTENNAMAXAREACAR 44.563107 LAYER Metal2 ; + PORT + LAYER Metal2 ; + RECT 193.625 0 193.885 0.26 ; + END + END B_ADDR[0] + PIN B_BIST_ADDR[0] + DIRECTION INPUT ; + USE SIGNAL ; + ANTENNAPARTIALMETALAREA 9.8293 LAYER Metal2 ; + ANTENNAMODEL OXIDE1 ; + ANTENNAGATEAREA 0.20085 LAYER Metal2 ; + ANTENNAMAXAREACAR 49.84466 LAYER Metal2 ; + PORT + LAYER Metal2 ; + RECT 188.015 0 188.275 0.26 ; + END + END B_BIST_ADDR[0] + PIN A_ADDR[1] + DIRECTION INPUT ; + USE SIGNAL ; + ANTENNAPARTIALMETALAREA 11.0851 LAYER Metal2 ; + ANTENNAMODEL OXIDE1 ; + ANTENNAGATEAREA 0.20085 LAYER Metal2 ; + ANTENNAMAXAREACAR 56.097087 LAYER Metal2 ; + PORT + LAYER Metal2 ; + RECT 226.575 0 226.835 0.26 ; + END + END A_ADDR[1] + PIN A_BIST_ADDR[1] + DIRECTION INPUT ; + USE SIGNAL ; + ANTENNAPARTIALMETALAREA 12.1459 LAYER Metal2 ; + ANTENNAMODEL OXIDE1 ; + ANTENNAGATEAREA 0.20085 LAYER Metal2 ; + ANTENNAMAXAREACAR 61.378641 LAYER Metal2 ; + PORT + LAYER Metal2 ; + RECT 232.185 0 232.445 0.26 ; + END + END A_BIST_ADDR[1] + PIN B_ADDR[1] + DIRECTION INPUT ; + USE SIGNAL ; + ANTENNAPARTIALMETALAREA 11.0851 LAYER Metal2 ; + ANTENNAMODEL OXIDE1 ; + ANTENNAGATEAREA 0.20085 LAYER Metal2 ; + ANTENNAMAXAREACAR 56.097087 LAYER Metal2 ; + PORT + LAYER Metal2 ; + RECT 193.115 0 193.375 0.26 ; + END + END B_ADDR[1] + PIN B_BIST_ADDR[1] + DIRECTION INPUT ; + USE SIGNAL ; + ANTENNAPARTIALMETALAREA 12.1459 LAYER Metal2 ; + ANTENNAMODEL OXIDE1 ; + ANTENNAGATEAREA 0.20085 LAYER Metal2 ; + ANTENNAMAXAREACAR 61.378641 LAYER Metal2 ; + PORT + LAYER Metal2 ; + RECT 187.505 0 187.765 0.26 ; + END + END B_BIST_ADDR[1] + PIN A_ADDR[2] + DIRECTION INPUT ; + USE SIGNAL ; + ANTENNAPARTIALMETALAREA 13.0819 LAYER Metal2 ; + ANTENNAPARTIALMETALAREA 1.5246 LAYER Metal3 ; + ANTENNAPARTIALCUTAREA 0.0722 LAYER Via2 ; + ANTENNAMODEL OXIDE1 ; + ANTENNAGATEAREA 0.20085 LAYER Metal3 ; + ANTENNAMAXAREACAR 9.415982 LAYER Metal3 ; + PORT + LAYER Metal2 ; + RECT 235.245 0 235.505 0.26 ; + END + END A_ADDR[2] + PIN A_BIST_ADDR[2] + DIRECTION INPUT ; + USE SIGNAL ; + ANTENNAPARTIALMETALAREA 13.0819 LAYER Metal2 ; + ANTENNAPARTIALMETALAREA 1.0962 LAYER Metal3 ; + ANTENNAPARTIALCUTAREA 0.0722 LAYER Via2 ; + ANTENNAMODEL OXIDE1 ; + ANTENNAGATEAREA 0.20085 LAYER Metal3 ; + ANTENNAMAXAREACAR 7.813791 LAYER Metal3 ; + PORT + LAYER Metal2 ; + RECT 235.755 0 236.015 0.26 ; + END + END A_BIST_ADDR[2] + PIN B_ADDR[2] + DIRECTION INPUT ; + USE SIGNAL ; + ANTENNAPARTIALMETALAREA 13.0819 LAYER Metal2 ; + ANTENNAPARTIALMETALAREA 1.5246 LAYER Metal3 ; + ANTENNAPARTIALCUTAREA 0.0722 LAYER Via2 ; + ANTENNAMODEL OXIDE1 ; + ANTENNAGATEAREA 0.20085 LAYER Metal3 ; + ANTENNAMAXAREACAR 9.415982 LAYER Metal3 ; + PORT + LAYER Metal2 ; + RECT 184.445 0 184.705 0.26 ; + END + END B_ADDR[2] + PIN B_BIST_ADDR[2] + DIRECTION INPUT ; + USE SIGNAL ; + ANTENNAPARTIALMETALAREA 13.0819 LAYER Metal2 ; + ANTENNAPARTIALMETALAREA 1.0962 LAYER Metal3 ; + ANTENNAPARTIALCUTAREA 0.0722 LAYER Via2 ; + ANTENNAMODEL OXIDE1 ; + ANTENNAGATEAREA 0.20085 LAYER Metal3 ; + ANTENNAMAXAREACAR 7.813791 LAYER Metal3 ; + PORT + LAYER Metal2 ; + RECT 183.935 0 184.195 0.26 ; + END + END B_BIST_ADDR[2] + PIN A_ADDR[3] + DIRECTION INPUT ; + USE SIGNAL ; + ANTENNAPARTIALMETALAREA 13.0819 LAYER Metal2 ; + ANTENNAPARTIALMETALAREA 3.9459 LAYER Metal3 ; + ANTENNAPARTIALCUTAREA 0.0722 LAYER Via2 ; + ANTENNAMODEL OXIDE1 ; + ANTENNAGATEAREA 0.20085 LAYER Metal3 ; + ANTENNAMAXAREACAR 21.471247 LAYER Metal3 ; + PORT + LAYER Metal2 ; + RECT 234.225 0 234.485 0.26 ; + END + END A_ADDR[3] + PIN A_BIST_ADDR[3] + DIRECTION INPUT ; + USE SIGNAL ; + ANTENNAPARTIALMETALAREA 13.0819 LAYER Metal2 ; + ANTENNAPARTIALMETALAREA 3.7317 LAYER Metal3 ; + ANTENNAPARTIALCUTAREA 0.0722 LAYER Via2 ; + ANTENNAMODEL OXIDE1 ; + ANTENNAGATEAREA 0.20085 LAYER Metal3 ; + ANTENNAMAXAREACAR 20.935524 LAYER Metal3 ; + PORT + LAYER Metal2 ; + RECT 234.735 0 234.995 0.26 ; + END + END A_BIST_ADDR[3] + PIN B_ADDR[3] + DIRECTION INPUT ; + USE SIGNAL ; + ANTENNAPARTIALMETALAREA 13.0819 LAYER Metal2 ; + ANTENNAPARTIALMETALAREA 3.9459 LAYER Metal3 ; + ANTENNAPARTIALCUTAREA 0.0722 LAYER Via2 ; + ANTENNAMODEL OXIDE1 ; + ANTENNAGATEAREA 0.20085 LAYER Metal3 ; + ANTENNAMAXAREACAR 21.471247 LAYER Metal3 ; + PORT + LAYER Metal2 ; + RECT 185.465 0 185.725 0.26 ; + END + END B_ADDR[3] + PIN B_BIST_ADDR[3] + DIRECTION INPUT ; + USE SIGNAL ; + ANTENNAPARTIALMETALAREA 13.0819 LAYER Metal2 ; + ANTENNAPARTIALMETALAREA 3.7317 LAYER Metal3 ; + ANTENNAPARTIALCUTAREA 0.0722 LAYER Via2 ; + ANTENNAMODEL OXIDE1 ; + ANTENNAGATEAREA 0.20085 LAYER Metal3 ; + ANTENNAMAXAREACAR 20.935524 LAYER Metal3 ; + PORT + LAYER Metal2 ; + RECT 184.955 0 185.215 0.26 ; + END + END B_BIST_ADDR[3] + PIN A_ADDR[4] + DIRECTION INPUT ; + USE SIGNAL ; + ANTENNAPARTIALMETALAREA 14.7329 LAYER Metal2 ; + ANTENNAMODEL OXIDE1 ; + ANTENNAGATEAREA 0.20085 LAYER Metal2 ; + ANTENNAMAXAREACAR 74.2589 LAYER Metal2 ; + PORT + LAYER Metal2 ; + RECT 214.845 0 215.105 0.26 ; + END + END A_ADDR[4] + PIN A_BIST_ADDR[4] + DIRECTION INPUT ; + USE SIGNAL ; + ANTENNAPARTIALMETALAREA 14.4677 LAYER Metal2 ; + ANTENNAMODEL OXIDE1 ; + ANTENNAGATEAREA 0.20085 LAYER Metal2 ; + ANTENNAMAXAREACAR 72.938511 LAYER Metal2 ; + PORT + LAYER Metal2 ; + RECT 215.355 0 215.615 0.26 ; + END + END A_BIST_ADDR[4] + PIN B_ADDR[4] + DIRECTION INPUT ; + USE SIGNAL ; + ANTENNAPARTIALMETALAREA 14.7329 LAYER Metal2 ; + ANTENNAMODEL OXIDE1 ; + ANTENNAGATEAREA 0.20085 LAYER Metal2 ; + ANTENNAMAXAREACAR 74.2589 LAYER Metal2 ; + PORT + LAYER Metal2 ; + RECT 204.845 0 205.105 0.26 ; + END + END B_ADDR[4] + PIN B_BIST_ADDR[4] + DIRECTION INPUT ; + USE SIGNAL ; + ANTENNAPARTIALMETALAREA 14.4677 LAYER Metal2 ; + ANTENNAMODEL OXIDE1 ; + ANTENNAGATEAREA 0.20085 LAYER Metal2 ; + ANTENNAMAXAREACAR 72.938511 LAYER Metal2 ; + PORT + LAYER Metal2 ; + RECT 204.335 0 204.595 0.26 ; + END + END B_BIST_ADDR[4] + PIN A_ADDR[5] + DIRECTION INPUT ; + USE SIGNAL ; + ANTENNAPARTIALMETALAREA 13.2691 LAYER Metal2 ; + ANTENNAMODEL OXIDE1 ; + ANTENNAGATEAREA 0.20085 LAYER Metal2 ; + ANTENNAMAXAREACAR 66.970874 LAYER Metal2 ; + PORT + LAYER Metal2 ; + RECT 213.825 0 214.085 0.26 ; + END + END A_ADDR[5] + PIN A_BIST_ADDR[5] + DIRECTION INPUT ; + USE SIGNAL ; + ANTENNAPARTIALMETALAREA 12.9937 LAYER Metal2 ; + ANTENNAMODEL OXIDE1 ; + ANTENNAGATEAREA 0.20085 LAYER Metal2 ; + ANTENNAMAXAREACAR 65.599701 LAYER Metal2 ; + PORT + LAYER Metal2 ; + RECT 214.335 0 214.595 0.26 ; + END + END A_BIST_ADDR[5] + PIN B_ADDR[5] + DIRECTION INPUT ; + USE SIGNAL ; + ANTENNAPARTIALMETALAREA 13.2691 LAYER Metal2 ; + ANTENNAMODEL OXIDE1 ; + ANTENNAGATEAREA 0.20085 LAYER Metal2 ; + ANTENNAMAXAREACAR 66.970874 LAYER Metal2 ; + PORT + LAYER Metal2 ; + RECT 205.865 0 206.125 0.26 ; + END + END B_ADDR[5] + PIN B_BIST_ADDR[5] + DIRECTION INPUT ; + USE SIGNAL ; + ANTENNAPARTIALMETALAREA 12.9937 LAYER Metal2 ; + ANTENNAMODEL OXIDE1 ; + ANTENNAGATEAREA 0.20085 LAYER Metal2 ; + ANTENNAMAXAREACAR 65.599701 LAYER Metal2 ; + PORT + LAYER Metal2 ; + RECT 205.355 0 205.615 0.26 ; + END + END B_BIST_ADDR[5] + PIN A_ADDR[6] + DIRECTION INPUT ; + USE SIGNAL ; + ANTENNAPARTIALMETALAREA 14.3819 LAYER Metal2 ; + ANTENNAMODEL OXIDE1 ; + ANTENNAGATEAREA 0.20085 LAYER Metal2 ; + ANTENNAMAXAREACAR 72.511327 LAYER Metal2 ; + PORT + LAYER Metal2 ; + RECT 237.795 0 238.055 0.26 ; + END + END A_ADDR[6] + PIN A_BIST_ADDR[6] + DIRECTION INPUT ; + USE SIGNAL ; + ANTENNAPARTIALMETALAREA 14.1167 LAYER Metal2 ; + ANTENNAMODEL OXIDE1 ; + ANTENNAGATEAREA 0.20085 LAYER Metal2 ; + ANTENNAMAXAREACAR 71.190939 LAYER Metal2 ; + PORT + LAYER Metal2 ; + RECT 237.285 0 237.545 0.26 ; + END + END A_BIST_ADDR[6] + PIN B_ADDR[6] + DIRECTION INPUT ; + USE SIGNAL ; + ANTENNAPARTIALMETALAREA 14.3819 LAYER Metal2 ; + ANTENNAMODEL OXIDE1 ; + ANTENNAGATEAREA 0.20085 LAYER Metal2 ; + ANTENNAMAXAREACAR 72.511327 LAYER Metal2 ; + PORT + LAYER Metal2 ; + RECT 181.895 0 182.155 0.26 ; + END + END B_ADDR[6] + PIN B_BIST_ADDR[6] + DIRECTION INPUT ; + USE SIGNAL ; + ANTENNAPARTIALMETALAREA 14.1167 LAYER Metal2 ; + ANTENNAMODEL OXIDE1 ; + ANTENNAGATEAREA 0.20085 LAYER Metal2 ; + ANTENNAMAXAREACAR 71.190939 LAYER Metal2 ; + PORT + LAYER Metal2 ; + RECT 182.405 0 182.665 0.26 ; + END + END B_BIST_ADDR[6] + PIN A_ADDR[7] + DIRECTION INPUT ; + USE SIGNAL ; + ANTENNAPARTIALMETALAREA 16.3761 LAYER Metal2 ; + ANTENNAMODEL OXIDE1 ; + ANTENNAGATEAREA 0.20085 LAYER Metal2 ; + ANTENNAMAXAREACAR 82.440129 LAYER Metal2 ; + PORT + LAYER Metal2 ; + RECT 236.775 0 237.035 0.26 ; + END + END A_ADDR[7] + PIN A_BIST_ADDR[7] + DIRECTION INPUT ; + USE SIGNAL ; + ANTENNAPARTIALMETALAREA 16.1109 LAYER Metal2 ; + ANTENNAMODEL OXIDE1 ; + ANTENNAGATEAREA 0.20085 LAYER Metal2 ; + ANTENNAMAXAREACAR 81.119741 LAYER Metal2 ; + PORT + LAYER Metal2 ; + RECT 236.265 0 236.525 0.26 ; + END + END A_BIST_ADDR[7] + PIN B_ADDR[7] + DIRECTION INPUT ; + USE SIGNAL ; + ANTENNAPARTIALMETALAREA 16.3761 LAYER Metal2 ; + ANTENNAMODEL OXIDE1 ; + ANTENNAGATEAREA 0.20085 LAYER Metal2 ; + ANTENNAMAXAREACAR 82.440129 LAYER Metal2 ; + PORT + LAYER Metal2 ; + RECT 182.915 0 183.175 0.26 ; + END + END B_ADDR[7] + PIN B_BIST_ADDR[7] + DIRECTION INPUT ; + USE SIGNAL ; + ANTENNAPARTIALMETALAREA 16.1109 LAYER Metal2 ; + ANTENNAMODEL OXIDE1 ; + ANTENNAGATEAREA 0.20085 LAYER Metal2 ; + ANTENNAMAXAREACAR 81.119741 LAYER Metal2 ; + PORT + LAYER Metal2 ; + RECT 183.425 0 183.685 0.26 ; + END + END B_BIST_ADDR[7] + PIN A_CLK + DIRECTION INPUT ; + USE SIGNAL ; + ANTENNAPARTIALMETALAREA 4.0547 LAYER Metal2 ; + ANTENNAMODEL OXIDE1 ; + ANTENNAGATEAREA 0.20085 LAYER Metal2 ; + ANTENNAMAXAREACAR 21.093851 LAYER Metal2 ; + PORT + LAYER Metal2 ; + RECT 224.535 0 224.795 0.26 ; + END + END A_CLK + PIN A_REN + DIRECTION INPUT ; + USE SIGNAL ; + ANTENNAPARTIALMETALAREA 3.98465 LAYER Metal2 ; + ANTENNAMODEL OXIDE1 ; + ANTENNAGATEAREA 0.20085 LAYER Metal2 ; + ANTENNAMAXAREACAR 20.745083 LAYER Metal2 ; + PORT + LAYER Metal2 ; + RECT 228.105 0 228.365 0.26 ; + END + END A_REN + PIN A_WEN + DIRECTION INPUT ; + USE SIGNAL ; + ANTENNAPARTIALMETALAREA 2.8847 LAYER Metal2 ; + ANTENNAMODEL OXIDE1 ; + ANTENNAGATEAREA 0.20085 LAYER Metal2 ; + ANTENNAMAXAREACAR 15.268608 LAYER Metal2 ; + PORT + LAYER Metal2 ; + RECT 227.595 0 227.855 0.26 ; + END + END A_WEN + PIN A_MEN + DIRECTION INPUT ; + USE SIGNAL ; + ANTENNAPARTIALMETALAREA 3.0247 LAYER Metal2 ; + ANTENNAMODEL OXIDE1 ; + ANTENNAGATEAREA 0.20085 LAYER Metal2 ; + ANTENNAMAXAREACAR 15.965646 LAYER Metal2 ; + PORT + LAYER Metal2 ; + RECT 225.045 0 225.305 0.26 ; + END + END A_MEN + PIN A_DLY + DIRECTION INPUT ; + USE SIGNAL ; + ANTENNAPARTIALMETALAREA 7.7792 LAYER Metal2 ; + ANTENNAMODEL OXIDE1 ; + ANTENNAGATEAREA 0.3367 LAYER Metal2 ; + ANTENNAMAXAREACAR 23.644788 LAYER Metal2 ; + PORT + LAYER Metal2 ; + RECT 245.445 0 245.705 0.26 ; + END + END A_DLY + PIN B_CLK + DIRECTION INPUT ; + USE SIGNAL ; + ANTENNAPARTIALMETALAREA 4.0547 LAYER Metal2 ; + ANTENNAMODEL OXIDE1 ; + ANTENNAGATEAREA 0.20085 LAYER Metal2 ; + ANTENNAMAXAREACAR 21.093851 LAYER Metal2 ; + PORT + LAYER Metal2 ; + RECT 195.155 0 195.415 0.26 ; + END + END B_CLK + PIN B_REN + DIRECTION INPUT ; + USE SIGNAL ; + ANTENNAPARTIALMETALAREA 3.98465 LAYER Metal2 ; + ANTENNAMODEL OXIDE1 ; + ANTENNAGATEAREA 0.20085 LAYER Metal2 ; + ANTENNAMAXAREACAR 20.745083 LAYER Metal2 ; + PORT + LAYER Metal2 ; + RECT 191.585 0 191.845 0.26 ; + END + END B_REN + PIN B_WEN + DIRECTION INPUT ; + USE SIGNAL ; + ANTENNAPARTIALMETALAREA 2.8847 LAYER Metal2 ; + ANTENNAMODEL OXIDE1 ; + ANTENNAGATEAREA 0.20085 LAYER Metal2 ; + ANTENNAMAXAREACAR 15.268608 LAYER Metal2 ; + PORT + LAYER Metal2 ; + RECT 192.095 0 192.355 0.26 ; + END + END B_WEN + PIN B_MEN + DIRECTION INPUT ; + USE SIGNAL ; + ANTENNAPARTIALMETALAREA 3.0247 LAYER Metal2 ; + ANTENNAMODEL OXIDE1 ; + ANTENNAGATEAREA 0.20085 LAYER Metal2 ; + ANTENNAMAXAREACAR 15.965646 LAYER Metal2 ; + PORT + LAYER Metal2 ; + RECT 194.645 0 194.905 0.26 ; + END + END B_MEN + PIN B_DLY + DIRECTION INPUT ; + USE SIGNAL ; + ANTENNAPARTIALMETALAREA 7.7792 LAYER Metal2 ; + ANTENNAMODEL OXIDE1 ; + ANTENNAGATEAREA 0.3367 LAYER Metal2 ; + ANTENNAMAXAREACAR 23.644788 LAYER Metal2 ; + PORT + LAYER Metal2 ; + RECT 174.245 0 174.505 0.26 ; + END + END B_DLY + PIN A_BIST_EN + DIRECTION INPUT ; + USE SIGNAL ; + ANTENNAPARTIALMETALAREA 4.0634 LAYER Metal2 ; + ANTENNAPARTIALMETALAREA 150.4115 LAYER Metal3 ; + ANTENNAPARTIALCUTAREA 0.0722 LAYER Via2 ; + ANTENNAMODEL OXIDE1 ; + ANTENNAGATEAREA 1.43 LAYER Metal2 ; + ANTENNAGATEAREA 15.73 LAYER Metal3 ; + ANTENNAMAXAREACAR 3.266993 LAYER Metal2 ; + ANTENNAMAXAREACAR 20.733454 LAYER Metal3 ; + ANTENNAMAXCUTCAR 0.151469 LAYER Via2 ; + PORT + LAYER Metal2 ; + RECT 227.085 0 227.345 0.26 ; + END + END A_BIST_EN + PIN A_BIST_CLK + DIRECTION INPUT ; + USE SIGNAL ; + ANTENNAPARTIALMETALAREA 4.1639 LAYER Metal2 ; + ANTENNAMODEL OXIDE1 ; + ANTENNAGATEAREA 0.20085 LAYER Metal2 ; + ANTENNAMAXAREACAR 21.953448 LAYER Metal2 ; + PORT + LAYER Metal2 ; + RECT 223.005 0 223.265 0.26 ; + END + END A_BIST_CLK + PIN A_BIST_REN + DIRECTION INPUT ; + USE SIGNAL ; + ANTENNAPARTIALMETALAREA 4.1119 LAYER Metal2 ; + ANTENNAMODEL OXIDE1 ; + ANTENNAGATEAREA 0.20085 LAYER Metal2 ; + ANTENNAMAXAREACAR 21.694548 LAYER Metal2 ; + PORT + LAYER Metal2 ; + RECT 229.635 0 229.895 0.26 ; + END + END A_BIST_REN + PIN A_BIST_WEN + DIRECTION INPUT ; + USE SIGNAL ; + ANTENNAPARTIALMETALAREA 2.9051 LAYER Metal2 ; + ANTENNAMODEL OXIDE1 ; + ANTENNAGATEAREA 0.20085 LAYER Metal2 ; + ANTENNAMAXAREACAR 15.686084 LAYER Metal2 ; + PORT + LAYER Metal2 ; + RECT 229.125 0 229.385 0.26 ; + END + END A_BIST_WEN + PIN A_BIST_MEN + DIRECTION INPUT ; + USE SIGNAL ; + ANTENNAPARTIALMETALAREA 2.8977 LAYER Metal2 ; + ANTENNAMODEL OXIDE1 ; + ANTENNAGATEAREA 0.20085 LAYER Metal2 ; + ANTENNAMAXAREACAR 15.649241 LAYER Metal2 ; + PORT + LAYER Metal2 ; + RECT 223.515 0 223.775 0.26 ; + END + END A_BIST_MEN + PIN B_BIST_EN + DIRECTION INPUT ; + USE SIGNAL ; + ANTENNAPARTIALMETALAREA 3.9646 LAYER Metal2 ; + ANTENNAPARTIALMETALAREA 150.9886 LAYER Metal3 ; + ANTENNAPARTIALCUTAREA 0.0722 LAYER Via2 ; + ANTENNAMODEL OXIDE1 ; + ANTENNAGATEAREA 1.43 LAYER Metal2 ; + ANTENNAGATEAREA 15.73 LAYER Metal3 ; + ANTENNAMAXAREACAR 3.197902 LAYER Metal2 ; + ANTENNAMAXAREACAR 20.770142 LAYER Metal3 ; + ANTENNAMAXCUTCAR 0.151469 LAYER Via2 ; + PORT + LAYER Metal2 ; + RECT 192.605 0 192.865 0.26 ; + END + END B_BIST_EN + PIN B_BIST_CLK + DIRECTION INPUT ; + USE SIGNAL ; + ANTENNAPARTIALMETALAREA 4.1639 LAYER Metal2 ; + ANTENNAMODEL OXIDE1 ; + ANTENNAGATEAREA 0.20085 LAYER Metal2 ; + ANTENNAMAXAREACAR 21.953448 LAYER Metal2 ; + PORT + LAYER Metal2 ; + RECT 196.685 0 196.945 0.26 ; + END + END B_BIST_CLK + PIN B_BIST_REN + DIRECTION INPUT ; + USE SIGNAL ; + ANTENNAPARTIALMETALAREA 4.1119 LAYER Metal2 ; + ANTENNAMODEL OXIDE1 ; + ANTENNAGATEAREA 0.20085 LAYER Metal2 ; + ANTENNAMAXAREACAR 21.694548 LAYER Metal2 ; + PORT + LAYER Metal2 ; + RECT 190.055 0 190.315 0.26 ; + END + END B_BIST_REN + PIN B_BIST_WEN + DIRECTION INPUT ; + USE SIGNAL ; + ANTENNAPARTIALMETALAREA 2.9051 LAYER Metal2 ; + ANTENNAMODEL OXIDE1 ; + ANTENNAGATEAREA 0.20085 LAYER Metal2 ; + ANTENNAMAXAREACAR 15.686084 LAYER Metal2 ; + PORT + LAYER Metal2 ; + RECT 190.565 0 190.825 0.26 ; + END + END B_BIST_WEN + PIN B_BIST_MEN + DIRECTION INPUT ; + USE SIGNAL ; + ANTENNAPARTIALMETALAREA 2.8977 LAYER Metal2 ; + ANTENNAMODEL OXIDE1 ; + ANTENNAGATEAREA 0.20085 LAYER Metal2 ; + ANTENNAMAXAREACAR 15.649241 LAYER Metal2 ; + PORT + LAYER Metal2 ; + RECT 196.175 0 196.435 0.26 ; + END + END B_BIST_MEN + OBS + LAYER Metal1 ; + RECT 0 0 419.95 136.97 ; + LAYER Metal2 ; + RECT 0.31 53.41 0.51 136.94 ; + RECT 1.135 136.21 1.335 136.94 ; + RECT 1.545 136.21 1.905 136.94 ; + RECT 2.115 136.21 2.315 136.94 ; + RECT 2.19 0.52 2.45 7.78 ; + RECT 2.7 0.3 2.96 5.235 ; + RECT 2.77 136.21 2.97 136.94 ; + RECT 3.21 0.52 3.47 5.57 ; + RECT 3.18 136.21 3.54 136.94 ; + RECT 3.835 136.21 4.035 136.94 ; + RECT 4.33 136.21 4.69 136.94 ; + RECT 4.585 0.52 4.845 6.28 ; + RECT 4.9 136.21 5.1 136.94 ; + RECT 5.555 136.21 5.755 136.94 ; + RECT 5.965 136.21 6.325 136.94 ; + RECT 6.535 136.21 6.735 136.94 ; + RECT 6.27 0.18 7.04 0.88 ; + RECT 7.19 136.21 7.39 136.94 ; + RECT 7.29 0.3 7.55 8.7 ; + RECT 7.6 136.21 7.96 136.94 ; + RECT 8.255 136.21 8.455 136.94 ; + RECT 8.75 136.21 9.11 136.94 ; + RECT 9.84 0.155 10.61 0.445 ; + RECT 9.84 0.155 10.1 8.665 ; + RECT 10.35 0.155 10.61 8.665 ; + RECT 9.32 136.21 9.52 136.94 ; + RECT 9.33 0.52 9.59 9.955 ; + RECT 9.975 136.21 10.175 136.94 ; + RECT 10.385 136.21 10.745 136.94 ; + RECT 10.86 0.52 11.12 11.315 ; + RECT 10.955 136.21 11.155 136.94 ; + RECT 11.37 0.52 11.63 13.45 ; + RECT 11.61 136.21 11.81 136.94 ; + RECT 11.88 0.52 12.14 14.115 ; + RECT 12.02 136.21 12.38 136.94 ; + RECT 12.675 136.21 12.875 136.94 ; + RECT 14.075 0.155 14.845 0.445 ; + RECT 14.075 0.155 14.335 13.21 ; + RECT 14.585 0.155 14.845 13.21 ; + RECT 13.17 136.21 13.53 136.94 ; + RECT 13.74 136.21 13.94 136.94 ; + RECT 15.095 0.18 15.865 0.88 ; + RECT 15.095 0.18 15.355 12.9 ; + RECT 15.605 0.18 15.865 12.9 ; + RECT 14.395 136.21 14.595 136.94 ; + RECT 14.805 136.21 15.165 136.94 ; + RECT 15.375 136.21 15.575 136.94 ; + RECT 16.03 136.21 16.23 136.94 ; + RECT 16.315 0.52 16.575 2.82 ; + RECT 16.44 136.21 16.8 136.94 ; + RECT 17.095 136.21 17.295 136.94 ; + RECT 17.59 136.21 17.95 136.94 ; + RECT 17.845 0.52 18.105 2.82 ; + RECT 18.16 136.21 18.36 136.94 ; + RECT 18.815 136.21 19.015 136.94 ; + RECT 19.02 0.52 19.28 4.315 ; + RECT 19.225 136.21 19.585 136.94 ; + RECT 19.795 136.21 19.995 136.94 ; + RECT 19.87 0.52 20.13 7.78 ; + RECT 20.38 0.3 20.64 5.235 ; + RECT 20.45 136.21 20.65 136.94 ; + RECT 20.89 0.52 21.15 5.57 ; + RECT 20.86 136.21 21.22 136.94 ; + RECT 21.515 136.21 21.715 136.94 ; + RECT 22.01 136.21 22.37 136.94 ; + RECT 22.265 0.52 22.525 6.28 ; + RECT 22.58 136.21 22.78 136.94 ; + RECT 23.235 136.21 23.435 136.94 ; + RECT 23.645 136.21 24.005 136.94 ; + RECT 24.215 136.21 24.415 136.94 ; + RECT 23.95 0.18 24.72 0.88 ; + RECT 24.87 136.21 25.07 136.94 ; + RECT 24.97 0.3 25.23 8.7 ; + RECT 25.28 136.21 25.64 136.94 ; + RECT 25.935 136.21 26.135 136.94 ; + RECT 26.43 136.21 26.79 136.94 ; + RECT 27.52 0.155 28.29 0.445 ; + RECT 27.52 0.155 27.78 8.665 ; + RECT 28.03 0.155 28.29 8.665 ; + RECT 27 136.21 27.2 136.94 ; + RECT 27.01 0.52 27.27 9.955 ; + RECT 27.655 136.21 27.855 136.94 ; + RECT 28.065 136.21 28.425 136.94 ; + RECT 28.54 0.52 28.8 11.315 ; + RECT 28.635 136.21 28.835 136.94 ; + RECT 29.05 0.52 29.31 13.45 ; + RECT 29.29 136.21 29.49 136.94 ; + RECT 29.56 0.52 29.82 14.115 ; + RECT 29.7 136.21 30.06 136.94 ; + RECT 30.355 136.21 30.555 136.94 ; + RECT 31.755 0.155 32.525 0.445 ; + RECT 31.755 0.155 32.015 13.21 ; + RECT 32.265 0.155 32.525 13.21 ; + RECT 30.85 136.21 31.21 136.94 ; + RECT 31.42 136.21 31.62 136.94 ; + RECT 32.775 0.18 33.545 0.88 ; + RECT 32.775 0.18 33.035 12.9 ; + RECT 33.285 0.18 33.545 12.9 ; + RECT 32.075 136.21 32.275 136.94 ; + RECT 32.485 136.21 32.845 136.94 ; + RECT 33.055 136.21 33.255 136.94 ; + RECT 33.71 136.21 33.91 136.94 ; + RECT 33.995 0.52 34.255 2.82 ; + RECT 34.12 136.21 34.48 136.94 ; + RECT 34.775 136.21 34.975 136.94 ; + RECT 35.27 136.21 35.63 136.94 ; + RECT 35.525 0.52 35.785 2.82 ; + RECT 35.84 136.21 36.04 136.94 ; + RECT 36.495 136.21 36.695 136.94 ; + RECT 36.7 0.52 36.96 4.315 ; + RECT 36.905 136.21 37.265 136.94 ; + RECT 37.475 136.21 37.675 136.94 ; + RECT 37.55 0.52 37.81 7.78 ; + RECT 38.06 0.3 38.32 5.235 ; + RECT 38.13 136.21 38.33 136.94 ; + RECT 38.57 0.52 38.83 5.57 ; + RECT 38.54 136.21 38.9 136.94 ; + RECT 39.195 136.21 39.395 136.94 ; + RECT 39.69 136.21 40.05 136.94 ; + RECT 39.945 0.52 40.205 6.28 ; + RECT 40.26 136.21 40.46 136.94 ; + RECT 40.915 136.21 41.115 136.94 ; + RECT 41.325 136.21 41.685 136.94 ; + RECT 41.895 136.21 42.095 136.94 ; + RECT 41.63 0.18 42.4 0.88 ; + RECT 42.55 136.21 42.75 136.94 ; + RECT 42.65 0.3 42.91 8.7 ; + RECT 42.96 136.21 43.32 136.94 ; + RECT 43.615 136.21 43.815 136.94 ; + RECT 44.11 136.21 44.47 136.94 ; + RECT 45.2 0.155 45.97 0.445 ; + RECT 45.2 0.155 45.46 8.665 ; + RECT 45.71 0.155 45.97 8.665 ; + RECT 44.68 136.21 44.88 136.94 ; + RECT 44.69 0.52 44.95 9.955 ; + RECT 45.335 136.21 45.535 136.94 ; + RECT 45.745 136.21 46.105 136.94 ; + RECT 46.22 0.52 46.48 11.315 ; + RECT 46.315 136.21 46.515 136.94 ; + RECT 46.73 0.52 46.99 13.45 ; + RECT 46.97 136.21 47.17 136.94 ; + RECT 47.24 0.52 47.5 14.115 ; + RECT 47.38 136.21 47.74 136.94 ; + RECT 48.035 136.21 48.235 136.94 ; + RECT 49.435 0.155 50.205 0.445 ; + RECT 49.435 0.155 49.695 13.21 ; + RECT 49.945 0.155 50.205 13.21 ; + RECT 48.53 136.21 48.89 136.94 ; + RECT 49.1 136.21 49.3 136.94 ; + RECT 50.455 0.18 51.225 0.88 ; + RECT 50.455 0.18 50.715 12.9 ; + RECT 50.965 0.18 51.225 12.9 ; + RECT 49.755 136.21 49.955 136.94 ; + RECT 50.165 136.21 50.525 136.94 ; + RECT 50.735 136.21 50.935 136.94 ; + RECT 51.39 136.21 51.59 136.94 ; + RECT 51.675 0.52 51.935 2.82 ; + RECT 51.8 136.21 52.16 136.94 ; + RECT 52.455 136.21 52.655 136.94 ; + RECT 52.95 136.21 53.31 136.94 ; + RECT 53.205 0.52 53.465 2.82 ; + RECT 53.52 136.21 53.72 136.94 ; + RECT 54.175 136.21 54.375 136.94 ; + RECT 54.38 0.52 54.64 4.315 ; + RECT 54.585 136.21 54.945 136.94 ; + RECT 55.155 136.21 55.355 136.94 ; + RECT 55.23 0.52 55.49 7.78 ; + RECT 55.74 0.3 56 5.235 ; + RECT 55.81 136.21 56.01 136.94 ; + RECT 56.25 0.52 56.51 5.57 ; + RECT 56.22 136.21 56.58 136.94 ; + RECT 56.875 136.21 57.075 136.94 ; + RECT 57.37 136.21 57.73 136.94 ; + RECT 57.625 0.52 57.885 6.28 ; + RECT 57.94 136.21 58.14 136.94 ; + RECT 58.595 136.21 58.795 136.94 ; + RECT 59.005 136.21 59.365 136.94 ; + RECT 59.575 136.21 59.775 136.94 ; + RECT 59.31 0.18 60.08 0.88 ; + RECT 60.23 136.21 60.43 136.94 ; + RECT 60.33 0.3 60.59 8.7 ; + RECT 60.64 136.21 61 136.94 ; + RECT 61.295 136.21 61.495 136.94 ; + RECT 61.79 136.21 62.15 136.94 ; + RECT 62.88 0.155 63.65 0.445 ; + RECT 62.88 0.155 63.14 8.665 ; + RECT 63.39 0.155 63.65 8.665 ; + RECT 62.36 136.21 62.56 136.94 ; + RECT 62.37 0.52 62.63 9.955 ; + RECT 63.015 136.21 63.215 136.94 ; + RECT 63.425 136.21 63.785 136.94 ; + RECT 63.9 0.52 64.16 11.315 ; + RECT 63.995 136.21 64.195 136.94 ; + RECT 64.41 0.52 64.67 13.45 ; + RECT 64.65 136.21 64.85 136.94 ; + RECT 64.92 0.52 65.18 14.115 ; + RECT 65.06 136.21 65.42 136.94 ; + RECT 65.715 136.21 65.915 136.94 ; + RECT 67.115 0.155 67.885 0.445 ; + RECT 67.115 0.155 67.375 13.21 ; + RECT 67.625 0.155 67.885 13.21 ; + RECT 66.21 136.21 66.57 136.94 ; + RECT 66.78 136.21 66.98 136.94 ; + RECT 68.135 0.18 68.905 0.88 ; + RECT 68.135 0.18 68.395 12.9 ; + RECT 68.645 0.18 68.905 12.9 ; + RECT 67.435 136.21 67.635 136.94 ; + RECT 67.845 136.21 68.205 136.94 ; + RECT 68.415 136.21 68.615 136.94 ; + RECT 69.07 136.21 69.27 136.94 ; + RECT 69.355 0.52 69.615 2.82 ; + RECT 69.48 136.21 69.84 136.94 ; + RECT 70.135 136.21 70.335 136.94 ; + RECT 70.63 136.21 70.99 136.94 ; + RECT 70.885 0.52 71.145 2.82 ; + RECT 71.2 136.21 71.4 136.94 ; + RECT 71.855 136.21 72.055 136.94 ; + RECT 72.06 0.52 72.32 4.315 ; + RECT 72.265 136.21 72.625 136.94 ; + RECT 72.835 136.21 73.035 136.94 ; + RECT 72.91 0.52 73.17 7.78 ; + RECT 73.42 0.3 73.68 5.235 ; + RECT 73.49 136.21 73.69 136.94 ; + RECT 73.93 0.52 74.19 5.57 ; + RECT 73.9 136.21 74.26 136.94 ; + RECT 74.555 136.21 74.755 136.94 ; + RECT 75.05 136.21 75.41 136.94 ; + RECT 75.305 0.52 75.565 6.28 ; + RECT 75.62 136.21 75.82 136.94 ; + RECT 76.275 136.21 76.475 136.94 ; + RECT 76.685 136.21 77.045 136.94 ; + RECT 77.255 136.21 77.455 136.94 ; + RECT 76.99 0.18 77.76 0.88 ; + RECT 77.91 136.21 78.11 136.94 ; + RECT 78.01 0.3 78.27 8.7 ; + RECT 78.32 136.21 78.68 136.94 ; + RECT 78.975 136.21 79.175 136.94 ; + RECT 79.47 136.21 79.83 136.94 ; + RECT 80.56 0.155 81.33 0.445 ; + RECT 80.56 0.155 80.82 8.665 ; + RECT 81.07 0.155 81.33 8.665 ; + RECT 80.04 136.21 80.24 136.94 ; + RECT 80.05 0.52 80.31 9.955 ; + RECT 80.695 136.21 80.895 136.94 ; + RECT 81.105 136.21 81.465 136.94 ; + RECT 81.58 0.52 81.84 11.315 ; + RECT 81.675 136.21 81.875 136.94 ; + RECT 82.09 0.52 82.35 13.45 ; + RECT 82.33 136.21 82.53 136.94 ; + RECT 82.6 0.52 82.86 14.115 ; + RECT 82.74 136.21 83.1 136.94 ; + RECT 83.395 136.21 83.595 136.94 ; + RECT 84.795 0.155 85.565 0.445 ; + RECT 84.795 0.155 85.055 13.21 ; + RECT 85.305 0.155 85.565 13.21 ; + RECT 83.89 136.21 84.25 136.94 ; + RECT 84.46 136.21 84.66 136.94 ; + RECT 85.815 0.18 86.585 0.88 ; + RECT 85.815 0.18 86.075 12.9 ; + RECT 86.325 0.18 86.585 12.9 ; + RECT 85.115 136.21 85.315 136.94 ; + RECT 85.525 136.21 85.885 136.94 ; + RECT 86.095 136.21 86.295 136.94 ; + RECT 86.75 136.21 86.95 136.94 ; + RECT 87.035 0.52 87.295 2.82 ; + RECT 87.16 136.21 87.52 136.94 ; + RECT 87.815 136.21 88.015 136.94 ; + RECT 88.31 136.21 88.67 136.94 ; + RECT 88.565 0.52 88.825 2.82 ; + RECT 88.88 136.21 89.08 136.94 ; + RECT 89.535 136.21 89.735 136.94 ; + RECT 89.74 0.52 90 4.315 ; + RECT 89.945 136.21 90.305 136.94 ; + RECT 90.515 136.21 90.715 136.94 ; + RECT 90.59 0.52 90.85 7.78 ; + RECT 91.1 0.3 91.36 5.235 ; + RECT 91.17 136.21 91.37 136.94 ; + RECT 91.61 0.52 91.87 5.57 ; + RECT 91.58 136.21 91.94 136.94 ; + RECT 92.235 136.21 92.435 136.94 ; + RECT 92.73 136.21 93.09 136.94 ; + RECT 92.985 0.52 93.245 6.28 ; + RECT 93.3 136.21 93.5 136.94 ; + RECT 93.955 136.21 94.155 136.94 ; + RECT 94.365 136.21 94.725 136.94 ; + RECT 94.935 136.21 95.135 136.94 ; + RECT 94.67 0.18 95.44 0.88 ; + RECT 95.59 136.21 95.79 136.94 ; + RECT 95.69 0.3 95.95 8.7 ; + RECT 96 136.21 96.36 136.94 ; + RECT 96.655 136.21 96.855 136.94 ; + RECT 97.15 136.21 97.51 136.94 ; + RECT 98.24 0.155 99.01 0.445 ; + RECT 98.24 0.155 98.5 8.665 ; + RECT 98.75 0.155 99.01 8.665 ; + RECT 97.72 136.21 97.92 136.94 ; + RECT 97.73 0.52 97.99 9.955 ; + RECT 98.375 136.21 98.575 136.94 ; + RECT 98.785 136.21 99.145 136.94 ; + RECT 99.26 0.52 99.52 11.315 ; + RECT 99.355 136.21 99.555 136.94 ; + RECT 99.77 0.52 100.03 13.45 ; + RECT 100.01 136.21 100.21 136.94 ; + RECT 100.28 0.52 100.54 14.115 ; + RECT 100.42 136.21 100.78 136.94 ; + RECT 101.075 136.21 101.275 136.94 ; + RECT 102.475 0.155 103.245 0.445 ; + RECT 102.475 0.155 102.735 13.21 ; + RECT 102.985 0.155 103.245 13.21 ; + RECT 101.57 136.21 101.93 136.94 ; + RECT 102.14 136.21 102.34 136.94 ; + RECT 103.495 0.18 104.265 0.88 ; + RECT 103.495 0.18 103.755 12.9 ; + RECT 104.005 0.18 104.265 12.9 ; + RECT 102.795 136.21 102.995 136.94 ; + RECT 103.205 136.21 103.565 136.94 ; + RECT 103.775 136.21 103.975 136.94 ; + RECT 104.43 136.21 104.63 136.94 ; + RECT 104.715 0.52 104.975 2.82 ; + RECT 104.84 136.21 105.2 136.94 ; + RECT 105.495 136.21 105.695 136.94 ; + RECT 105.99 136.21 106.35 136.94 ; + RECT 106.245 0.52 106.505 2.82 ; + RECT 106.56 136.21 106.76 136.94 ; + RECT 107.215 136.21 107.415 136.94 ; + RECT 107.42 0.52 107.68 4.315 ; + RECT 107.625 136.21 107.985 136.94 ; + RECT 108.195 136.21 108.395 136.94 ; + RECT 108.27 0.52 108.53 7.78 ; + RECT 108.78 0.3 109.04 5.235 ; + RECT 108.85 136.21 109.05 136.94 ; + RECT 109.29 0.52 109.55 5.57 ; + RECT 109.26 136.21 109.62 136.94 ; + RECT 109.915 136.21 110.115 136.94 ; + RECT 110.41 136.21 110.77 136.94 ; + RECT 110.665 0.52 110.925 6.28 ; + RECT 110.98 136.21 111.18 136.94 ; + RECT 111.635 136.21 111.835 136.94 ; + RECT 112.045 136.21 112.405 136.94 ; + RECT 112.615 136.21 112.815 136.94 ; + RECT 112.35 0.18 113.12 0.88 ; + RECT 113.27 136.21 113.47 136.94 ; + RECT 113.37 0.3 113.63 8.7 ; + RECT 113.68 136.21 114.04 136.94 ; + RECT 114.335 136.21 114.535 136.94 ; + RECT 114.83 136.21 115.19 136.94 ; + RECT 115.92 0.155 116.69 0.445 ; + RECT 115.92 0.155 116.18 8.665 ; + RECT 116.43 0.155 116.69 8.665 ; + RECT 115.4 136.21 115.6 136.94 ; + RECT 115.41 0.52 115.67 9.955 ; + RECT 116.055 136.21 116.255 136.94 ; + RECT 116.465 136.21 116.825 136.94 ; + RECT 116.94 0.52 117.2 11.315 ; + RECT 117.035 136.21 117.235 136.94 ; + RECT 117.45 0.52 117.71 13.45 ; + RECT 117.69 136.21 117.89 136.94 ; + RECT 117.96 0.52 118.22 14.115 ; + RECT 118.1 136.21 118.46 136.94 ; + RECT 118.755 136.21 118.955 136.94 ; + RECT 120.155 0.155 120.925 0.445 ; + RECT 120.155 0.155 120.415 13.21 ; + RECT 120.665 0.155 120.925 13.21 ; + RECT 119.25 136.21 119.61 136.94 ; + RECT 119.82 136.21 120.02 136.94 ; + RECT 121.175 0.18 121.945 0.88 ; + RECT 121.175 0.18 121.435 12.9 ; + RECT 121.685 0.18 121.945 12.9 ; + RECT 120.475 136.21 120.675 136.94 ; + RECT 120.885 136.21 121.245 136.94 ; + RECT 121.455 136.21 121.655 136.94 ; + RECT 122.11 136.21 122.31 136.94 ; + RECT 122.395 0.52 122.655 2.82 ; + RECT 122.52 136.21 122.88 136.94 ; + RECT 123.175 136.21 123.375 136.94 ; + RECT 123.67 136.21 124.03 136.94 ; + RECT 123.925 0.52 124.185 2.82 ; + RECT 124.24 136.21 124.44 136.94 ; + RECT 124.895 136.21 125.095 136.94 ; + RECT 125.1 0.52 125.36 4.315 ; + RECT 125.305 136.21 125.665 136.94 ; + RECT 125.875 136.21 126.075 136.94 ; + RECT 125.95 0.52 126.21 7.78 ; + RECT 126.46 0.3 126.72 5.235 ; + RECT 126.53 136.21 126.73 136.94 ; + RECT 126.97 0.52 127.23 5.57 ; + RECT 126.94 136.21 127.3 136.94 ; + RECT 127.595 136.21 127.795 136.94 ; + RECT 128.09 136.21 128.45 136.94 ; + RECT 128.345 0.52 128.605 6.28 ; + RECT 128.66 136.21 128.86 136.94 ; + RECT 129.315 136.21 129.515 136.94 ; + RECT 129.725 136.21 130.085 136.94 ; + RECT 130.295 136.21 130.495 136.94 ; + RECT 130.03 0.18 130.8 0.88 ; + RECT 130.95 136.21 131.15 136.94 ; + RECT 131.05 0.3 131.31 8.7 ; + RECT 131.36 136.21 131.72 136.94 ; + RECT 132.015 136.21 132.215 136.94 ; + RECT 132.51 136.21 132.87 136.94 ; + RECT 133.6 0.155 134.37 0.445 ; + RECT 133.6 0.155 133.86 8.665 ; + RECT 134.11 0.155 134.37 8.665 ; + RECT 133.08 136.21 133.28 136.94 ; + RECT 133.09 0.52 133.35 9.955 ; + RECT 133.735 136.21 133.935 136.94 ; + RECT 134.145 136.21 134.505 136.94 ; + RECT 134.62 0.52 134.88 11.315 ; + RECT 134.715 136.21 134.915 136.94 ; + RECT 135.13 0.52 135.39 13.45 ; + RECT 135.37 136.21 135.57 136.94 ; + RECT 135.64 0.52 135.9 14.115 ; + RECT 135.78 136.21 136.14 136.94 ; + RECT 136.435 136.21 136.635 136.94 ; + RECT 137.835 0.155 138.605 0.445 ; + RECT 137.835 0.155 138.095 13.21 ; + RECT 138.345 0.155 138.605 13.21 ; + RECT 136.93 136.21 137.29 136.94 ; + RECT 137.5 136.21 137.7 136.94 ; + RECT 138.855 0.18 139.625 0.88 ; + RECT 138.855 0.18 139.115 12.9 ; + RECT 139.365 0.18 139.625 12.9 ; + RECT 138.155 136.21 138.355 136.94 ; + RECT 138.565 136.21 138.925 136.94 ; + RECT 139.135 136.21 139.335 136.94 ; + RECT 139.79 136.21 139.99 136.94 ; + RECT 140.075 0.52 140.335 2.82 ; + RECT 140.2 136.21 140.56 136.94 ; + RECT 140.855 136.21 141.055 136.94 ; + RECT 141.35 136.21 141.71 136.94 ; + RECT 141.605 0.52 141.865 2.82 ; + RECT 141.92 136.21 142.12 136.94 ; + RECT 142.575 136.21 142.775 136.94 ; + RECT 142.78 0.52 143.04 4.315 ; + RECT 144.31 0.17 145.08 0.43 ; + RECT 144.31 0.17 144.57 8.7 ; + RECT 144.82 0.17 145.08 8.7 ; + RECT 145.33 0.18 146.1 0.88 ; + RECT 145.33 0.18 145.59 8.7 ; + RECT 145.84 0.18 146.1 8.7 ; + RECT 146.35 0.17 147.12 0.43 ; + RECT 146.35 0.17 146.61 8.7 ; + RECT 146.86 0.17 147.12 8.7 ; + RECT 147.37 0.18 148.14 0.88 ; + RECT 147.37 0.18 147.63 8.7 ; + RECT 147.88 0.18 148.14 8.7 ; + RECT 148.39 0.17 149.16 0.43 ; + RECT 148.39 0.17 148.65 8.7 ; + RECT 148.9 0.17 149.16 8.7 ; + RECT 149.41 0.18 150.18 0.88 ; + RECT 149.41 0.18 149.67 8.7 ; + RECT 149.92 0.18 150.18 8.7 ; + RECT 150.43 0.17 151.2 0.43 ; + RECT 150.43 0.17 150.69 8.7 ; + RECT 150.94 0.17 151.2 8.7 ; + RECT 151.45 0.18 152.22 0.88 ; + RECT 151.45 0.18 151.71 8.7 ; + RECT 151.96 0.18 152.22 8.7 ; + RECT 152.47 0.17 153.24 0.43 ; + RECT 152.47 0.17 152.73 8.7 ; + RECT 152.98 0.17 153.24 8.7 ; + RECT 153.49 0.18 154.26 0.88 ; + RECT 153.49 0.18 153.75 8.7 ; + RECT 154 0.18 154.26 8.7 ; + RECT 154.51 0.17 155.28 0.43 ; + RECT 154.51 0.17 154.77 8.7 ; + RECT 155.02 0.17 155.28 8.7 ; + RECT 155.53 0.18 156.3 0.88 ; + RECT 155.53 0.18 155.79 8.7 ; + RECT 156.04 0.18 156.3 8.7 ; + RECT 156.55 0.17 157.32 0.43 ; + RECT 156.55 0.17 156.81 8.7 ; + RECT 157.06 0.17 157.32 8.7 ; + RECT 157.57 0.18 158.34 0.88 ; + RECT 157.57 0.18 157.83 8.7 ; + RECT 158.08 0.18 158.34 8.7 ; + RECT 158.59 0.17 159.36 0.43 ; + RECT 158.59 0.17 158.85 8.7 ; + RECT 159.1 0.17 159.36 8.7 ; + RECT 159.61 0.18 160.38 0.88 ; + RECT 159.61 0.18 159.87 8.7 ; + RECT 160.12 0.18 160.38 8.7 ; + RECT 160.63 0.17 161.4 0.43 ; + RECT 160.63 0.17 160.89 8.7 ; + RECT 161.14 0.17 161.4 8.7 ; + RECT 161.65 0.18 162.42 0.88 ; + RECT 161.65 0.18 161.91 8.7 ; + RECT 162.16 0.18 162.42 8.7 ; + RECT 162.67 0.17 163.44 0.43 ; + RECT 162.67 0.17 162.93 8.7 ; + RECT 163.18 0.17 163.44 8.7 ; + RECT 163.69 0.18 164.46 0.88 ; + RECT 163.69 0.18 163.95 8.7 ; + RECT 164.2 0.18 164.46 8.7 ; + RECT 164.71 0.17 165.48 0.43 ; + RECT 164.71 0.17 164.97 8.7 ; + RECT 165.22 0.17 165.48 8.7 ; + RECT 165.73 0.18 166.5 0.88 ; + RECT 165.73 0.18 165.99 8.7 ; + RECT 166.24 0.18 166.5 8.7 ; + RECT 166.75 0.17 167.52 0.43 ; + RECT 166.75 0.17 167.01 8.7 ; + RECT 167.26 0.17 167.52 8.7 ; + RECT 167.77 0.18 168.54 0.88 ; + RECT 167.77 0.18 168.03 8.7 ; + RECT 168.28 0.18 168.54 8.7 ; + RECT 142.985 136.21 143.345 136.94 ; + RECT 143.555 136.21 143.755 136.94 ; + RECT 170.165 0.18 170.935 0.88 ; + RECT 170.165 0.18 170.425 8.7 ; + RECT 170.675 0.18 170.935 8.7 ; + RECT 171.185 0.17 171.955 0.43 ; + RECT 171.185 0.17 171.445 8.7 ; + RECT 171.695 0.17 171.955 8.7 ; + RECT 144.38 136.13 144.58 136.94 ; + RECT 169.145 0.3 169.405 8.7 ; + RECT 173.225 0.18 173.995 0.88 ; + RECT 173.225 0.18 173.485 8.7 ; + RECT 173.735 0.18 173.995 8.7 ; + RECT 169.655 0.3 169.915 8.7 ; + RECT 172.205 0 172.465 8.7 ; + RECT 172.715 0 172.975 8.7 ; + RECT 174.245 0.52 174.505 8.7 ; + RECT 174.755 0.3 175.015 8.7 ; + RECT 175.265 0.3 175.525 8.7 ; + RECT 175.775 0.3 176.035 8.7 ; + RECT 176.285 0.3 176.545 8.7 ; + RECT 176.795 0.3 177.055 8.7 ; + RECT 177.305 0.3 177.565 8.7 ; + RECT 177.815 0.3 178.075 8.7 ; + RECT 179.855 0.18 180.625 0.88 ; + RECT 179.855 0.18 180.115 8.7 ; + RECT 180.365 0.18 180.625 8.7 ; + RECT 178.325 0.3 178.585 8.7 ; + RECT 178.835 0 179.095 8.7 ; + RECT 179.345 0 179.605 8.7 ; + RECT 180.875 0 181.135 8.7 ; + RECT 181.385 0 181.645 8.7 ; + RECT 181.895 0.52 182.155 8.7 ; + RECT 182.405 0.52 182.665 8.7 ; + RECT 182.915 0.52 183.175 8.7 ; + RECT 183.425 0.52 183.685 8.7 ; + RECT 183.935 0.52 184.195 8.7 ; + RECT 184.445 0.52 184.705 8.7 ; + RECT 184.955 0.52 185.215 8.7 ; + RECT 185.465 0.52 185.725 8.7 ; + RECT 185.975 0.3 186.235 8.7 ; + RECT 186.485 0.3 186.745 8.7 ; + RECT 186.995 0.3 187.255 8.7 ; + RECT 187.505 0.52 187.765 8.7 ; + RECT 188.015 0.52 188.275 8.7 ; + RECT 188.525 0.3 188.785 8.7 ; + RECT 189.035 0.3 189.295 8.7 ; + RECT 189.545 0.3 189.805 8.7 ; + RECT 190.055 0.52 190.315 8.7 ; + RECT 190.565 0.52 190.825 8.7 ; + RECT 191.075 0.3 191.335 8.7 ; + RECT 191.585 0.52 191.845 8.7 ; + RECT 192.095 0.52 192.355 8.7 ; + RECT 192.605 0.52 192.865 8.7 ; + RECT 193.115 0.52 193.375 8.7 ; + RECT 193.625 0.52 193.885 8.7 ; + RECT 194.135 0.3 194.395 8.7 ; + RECT 194.645 0.52 194.905 8.7 ; + RECT 195.155 0.52 195.415 8.7 ; + RECT 195.665 0.3 195.925 8.7 ; + RECT 196.175 0.52 196.435 8.7 ; + RECT 198.215 0.17 198.985 0.43 ; + RECT 198.215 0.17 198.475 8.7 ; + RECT 198.725 0.17 198.985 8.7 ; + RECT 196.685 0.52 196.945 8.7 ; + RECT 197.195 0.3 197.455 8.7 ; + RECT 197.705 0.3 197.965 8.7 ; + RECT 200.765 0.17 201.535 0.43 ; + RECT 200.765 0.17 201.025 8.7 ; + RECT 201.275 0.17 201.535 8.7 ; + RECT 199.235 0.3 199.495 8.7 ; + RECT 202.295 0.18 203.065 0.88 ; + RECT 202.295 0.18 202.555 8.7 ; + RECT 202.805 0.18 203.065 8.7 ; + RECT 199.745 0.3 200.005 8.7 ; + RECT 200.255 0.3 200.515 8.7 ; + RECT 201.785 0.3 202.045 8.7 ; + RECT 203.315 0 203.575 8.7 ; + RECT 203.825 0 204.085 8.7 ; + RECT 204.335 0.52 204.595 8.7 ; + RECT 204.845 0.52 205.105 8.7 ; + RECT 205.355 0.52 205.615 8.7 ; + RECT 205.865 0.52 206.125 8.7 ; + RECT 206.375 0 206.635 8.7 ; + RECT 206.885 0 207.145 8.7 ; + RECT 207.395 0.3 207.655 8.7 ; + RECT 207.905 0.3 208.165 8.7 ; + RECT 208.415 0 208.675 8.7 ; + RECT 208.925 0 209.185 8.7 ; + RECT 209.435 0.3 209.695 8.7 ; + RECT 210.255 0.3 210.515 8.7 ; + RECT 210.765 0 211.025 8.7 ; + RECT 211.275 0 211.535 8.7 ; + RECT 211.785 0.3 212.045 8.7 ; + RECT 212.295 0.3 212.555 8.7 ; + RECT 212.805 0 213.065 8.7 ; + RECT 213.315 0 213.575 8.7 ; + RECT 213.825 0.52 214.085 8.7 ; + RECT 214.335 0.52 214.595 8.7 ; + RECT 214.845 0.52 215.105 8.7 ; + RECT 216.885 0.18 217.655 0.88 ; + RECT 216.885 0.18 217.145 8.7 ; + RECT 217.395 0.18 217.655 8.7 ; + RECT 215.355 0.52 215.615 8.7 ; + RECT 218.415 0.17 219.185 0.43 ; + RECT 218.415 0.17 218.675 8.7 ; + RECT 218.925 0.17 219.185 8.7 ; + RECT 215.865 0 216.125 8.7 ; + RECT 216.375 0 216.635 8.7 ; + RECT 217.905 0.3 218.165 8.7 ; + RECT 220.965 0.17 221.735 0.43 ; + RECT 220.965 0.17 221.225 8.7 ; + RECT 221.475 0.17 221.735 8.7 ; + RECT 219.435 0.3 219.695 8.7 ; + RECT 219.945 0.3 220.205 8.7 ; + RECT 220.455 0.3 220.715 8.7 ; + RECT 221.985 0.3 222.245 8.7 ; + RECT 222.495 0.3 222.755 8.7 ; + RECT 223.005 0.52 223.265 8.7 ; + RECT 223.515 0.52 223.775 8.7 ; + RECT 224.025 0.3 224.285 8.7 ; + RECT 224.535 0.52 224.795 8.7 ; + RECT 225.045 0.52 225.305 8.7 ; + RECT 225.555 0.3 225.815 8.7 ; + RECT 226.065 0.52 226.325 8.7 ; + RECT 226.575 0.52 226.835 8.7 ; + RECT 227.085 0.52 227.345 8.7 ; + RECT 227.595 0.52 227.855 8.7 ; + RECT 228.105 0.52 228.365 8.7 ; + RECT 228.615 0.3 228.875 8.7 ; + RECT 229.125 0.52 229.385 8.7 ; + RECT 229.635 0.52 229.895 8.7 ; + RECT 230.145 0.3 230.405 8.7 ; + RECT 230.655 0.3 230.915 8.7 ; + RECT 231.165 0.3 231.425 8.7 ; + RECT 231.675 0.52 231.935 8.7 ; + RECT 232.185 0.52 232.445 8.7 ; + RECT 232.695 0.3 232.955 8.7 ; + RECT 233.205 0.3 233.465 8.7 ; + RECT 233.715 0.3 233.975 8.7 ; + RECT 234.225 0.52 234.485 8.7 ; + RECT 234.735 0.52 234.995 8.7 ; + RECT 235.245 0.52 235.505 8.7 ; + RECT 235.755 0.52 236.015 8.7 ; + RECT 236.265 0.52 236.525 8.7 ; + RECT 236.775 0.52 237.035 8.7 ; + RECT 237.285 0.52 237.545 8.7 ; + RECT 239.325 0.18 240.095 0.88 ; + RECT 239.325 0.18 239.585 8.7 ; + RECT 239.835 0.18 240.095 8.7 ; + RECT 237.795 0.52 238.055 8.7 ; + RECT 238.305 0 238.565 8.7 ; + RECT 238.815 0 239.075 8.7 ; + RECT 240.345 0 240.605 8.7 ; + RECT 240.855 0 241.115 8.7 ; + RECT 241.365 0.3 241.625 8.7 ; + RECT 241.875 0.3 242.135 8.7 ; + RECT 242.385 0.3 242.645 8.7 ; + RECT 242.895 0.3 243.155 8.7 ; + RECT 243.405 0.3 243.665 8.7 ; + RECT 243.915 0.3 244.175 8.7 ; + RECT 245.955 0.18 246.725 0.88 ; + RECT 245.955 0.18 246.215 8.7 ; + RECT 246.465 0.18 246.725 8.7 ; + RECT 244.425 0.3 244.685 8.7 ; + RECT 244.935 0.3 245.195 8.7 ; + RECT 247.995 0.17 248.765 0.43 ; + RECT 247.995 0.17 248.255 8.7 ; + RECT 248.505 0.17 248.765 8.7 ; + RECT 249.015 0.18 249.785 0.88 ; + RECT 249.015 0.18 249.275 8.7 ; + RECT 249.525 0.18 249.785 8.7 ; + RECT 245.445 0.52 245.705 8.7 ; + RECT 246.975 0 247.235 8.7 ; + RECT 251.41 0.18 252.18 0.88 ; + RECT 251.41 0.18 251.67 8.7 ; + RECT 251.92 0.18 252.18 8.7 ; + RECT 252.43 0.17 253.2 0.43 ; + RECT 252.43 0.17 252.69 8.7 ; + RECT 252.94 0.17 253.2 8.7 ; + RECT 253.45 0.18 254.22 0.88 ; + RECT 253.45 0.18 253.71 8.7 ; + RECT 253.96 0.18 254.22 8.7 ; + RECT 254.47 0.17 255.24 0.43 ; + RECT 254.47 0.17 254.73 8.7 ; + RECT 254.98 0.17 255.24 8.7 ; + RECT 255.49 0.18 256.26 0.88 ; + RECT 255.49 0.18 255.75 8.7 ; + RECT 256 0.18 256.26 8.7 ; + RECT 256.51 0.17 257.28 0.43 ; + RECT 256.51 0.17 256.77 8.7 ; + RECT 257.02 0.17 257.28 8.7 ; + RECT 257.53 0.18 258.3 0.88 ; + RECT 257.53 0.18 257.79 8.7 ; + RECT 258.04 0.18 258.3 8.7 ; + RECT 258.55 0.17 259.32 0.43 ; + RECT 258.55 0.17 258.81 8.7 ; + RECT 259.06 0.17 259.32 8.7 ; + RECT 259.57 0.18 260.34 0.88 ; + RECT 259.57 0.18 259.83 8.7 ; + RECT 260.08 0.18 260.34 8.7 ; + RECT 260.59 0.17 261.36 0.43 ; + RECT 260.59 0.17 260.85 8.7 ; + RECT 261.1 0.17 261.36 8.7 ; + RECT 261.61 0.18 262.38 0.88 ; + RECT 261.61 0.18 261.87 8.7 ; + RECT 262.12 0.18 262.38 8.7 ; + RECT 262.63 0.17 263.4 0.43 ; + RECT 262.63 0.17 262.89 8.7 ; + RECT 263.14 0.17 263.4 8.7 ; + RECT 263.65 0.18 264.42 0.88 ; + RECT 263.65 0.18 263.91 8.7 ; + RECT 264.16 0.18 264.42 8.7 ; + RECT 264.67 0.17 265.44 0.43 ; + RECT 264.67 0.17 264.93 8.7 ; + RECT 265.18 0.17 265.44 8.7 ; + RECT 265.69 0.18 266.46 0.88 ; + RECT 265.69 0.18 265.95 8.7 ; + RECT 266.2 0.18 266.46 8.7 ; + RECT 266.71 0.17 267.48 0.43 ; + RECT 266.71 0.17 266.97 8.7 ; + RECT 267.22 0.17 267.48 8.7 ; + RECT 267.73 0.18 268.5 0.88 ; + RECT 267.73 0.18 267.99 8.7 ; + RECT 268.24 0.18 268.5 8.7 ; + RECT 268.75 0.17 269.52 0.43 ; + RECT 268.75 0.17 269.01 8.7 ; + RECT 269.26 0.17 269.52 8.7 ; + RECT 269.77 0.18 270.54 0.88 ; + RECT 269.77 0.18 270.03 8.7 ; + RECT 270.28 0.18 270.54 8.7 ; + RECT 270.79 0.17 271.56 0.43 ; + RECT 270.79 0.17 271.05 8.7 ; + RECT 271.3 0.17 271.56 8.7 ; + RECT 271.81 0.18 272.58 0.88 ; + RECT 271.81 0.18 272.07 8.7 ; + RECT 272.32 0.18 272.58 8.7 ; + RECT 272.83 0.17 273.6 0.43 ; + RECT 272.83 0.17 273.09 8.7 ; + RECT 273.34 0.17 273.6 8.7 ; + RECT 273.85 0.18 274.62 0.88 ; + RECT 273.85 0.18 274.11 8.7 ; + RECT 274.36 0.18 274.62 8.7 ; + RECT 247.485 0 247.745 8.7 ; + RECT 274.87 0.17 275.64 0.43 ; + RECT 274.87 0.17 275.13 8.7 ; + RECT 275.38 0.17 275.64 8.7 ; + RECT 250.035 0.3 250.295 8.7 ; + RECT 250.545 0.3 250.805 8.7 ; + RECT 275.37 136.13 275.57 136.94 ; + RECT 276.195 136.21 276.395 136.94 ; + RECT 276.605 136.21 276.965 136.94 ; + RECT 276.91 0.52 277.17 4.315 ; + RECT 277.175 136.21 277.375 136.94 ; + RECT 277.83 136.21 278.03 136.94 ; + RECT 278.085 0.52 278.345 2.82 ; + RECT 278.24 136.21 278.6 136.94 ; + RECT 278.895 136.21 279.095 136.94 ; + RECT 279.39 136.21 279.75 136.94 ; + RECT 280.325 0.18 281.095 0.88 ; + RECT 280.325 0.18 280.585 12.9 ; + RECT 280.835 0.18 281.095 12.9 ; + RECT 279.615 0.52 279.875 2.82 ; + RECT 279.96 136.21 280.16 136.94 ; + RECT 281.345 0.155 282.115 0.445 ; + RECT 281.345 0.155 281.605 13.21 ; + RECT 281.855 0.155 282.115 13.21 ; + RECT 280.615 136.21 280.815 136.94 ; + RECT 281.025 136.21 281.385 136.94 ; + RECT 281.595 136.21 281.795 136.94 ; + RECT 282.25 136.21 282.45 136.94 ; + RECT 282.66 136.21 283.02 136.94 ; + RECT 283.315 136.21 283.515 136.94 ; + RECT 283.81 136.21 284.17 136.94 ; + RECT 284.05 0.52 284.31 14.115 ; + RECT 284.38 136.21 284.58 136.94 ; + RECT 284.56 0.52 284.82 13.45 ; + RECT 285.035 136.21 285.235 136.94 ; + RECT 285.58 0.155 286.35 0.445 ; + RECT 285.58 0.155 285.84 8.665 ; + RECT 286.09 0.155 286.35 8.665 ; + RECT 285.07 0.52 285.33 11.315 ; + RECT 285.445 136.21 285.805 136.94 ; + RECT 286.015 136.21 286.215 136.94 ; + RECT 286.6 0.52 286.86 9.955 ; + RECT 286.67 136.21 286.87 136.94 ; + RECT 287.08 136.21 287.44 136.94 ; + RECT 287.735 136.21 287.935 136.94 ; + RECT 288.23 136.21 288.59 136.94 ; + RECT 288.64 0.3 288.9 8.7 ; + RECT 288.8 136.21 289 136.94 ; + RECT 289.455 136.21 289.655 136.94 ; + RECT 289.15 0.18 289.92 0.88 ; + RECT 289.865 136.21 290.225 136.94 ; + RECT 290.435 136.21 290.635 136.94 ; + RECT 291.09 136.21 291.29 136.94 ; + RECT 291.345 0.52 291.605 6.28 ; + RECT 291.5 136.21 291.86 136.94 ; + RECT 292.155 136.21 292.355 136.94 ; + RECT 292.72 0.52 292.98 5.57 ; + RECT 292.65 136.21 293.01 136.94 ; + RECT 293.22 136.21 293.42 136.94 ; + RECT 293.23 0.3 293.49 5.235 ; + RECT 293.74 0.52 294 7.78 ; + RECT 293.875 136.21 294.075 136.94 ; + RECT 294.285 136.21 294.645 136.94 ; + RECT 294.59 0.52 294.85 4.315 ; + RECT 294.855 136.21 295.055 136.94 ; + RECT 295.51 136.21 295.71 136.94 ; + RECT 295.765 0.52 296.025 2.82 ; + RECT 295.92 136.21 296.28 136.94 ; + RECT 296.575 136.21 296.775 136.94 ; + RECT 297.07 136.21 297.43 136.94 ; + RECT 298.005 0.18 298.775 0.88 ; + RECT 298.005 0.18 298.265 12.9 ; + RECT 298.515 0.18 298.775 12.9 ; + RECT 297.295 0.52 297.555 2.82 ; + RECT 297.64 136.21 297.84 136.94 ; + RECT 299.025 0.155 299.795 0.445 ; + RECT 299.025 0.155 299.285 13.21 ; + RECT 299.535 0.155 299.795 13.21 ; + RECT 298.295 136.21 298.495 136.94 ; + RECT 298.705 136.21 299.065 136.94 ; + RECT 299.275 136.21 299.475 136.94 ; + RECT 299.93 136.21 300.13 136.94 ; + RECT 300.34 136.21 300.7 136.94 ; + RECT 300.995 136.21 301.195 136.94 ; + RECT 301.49 136.21 301.85 136.94 ; + RECT 301.73 0.52 301.99 14.115 ; + RECT 302.06 136.21 302.26 136.94 ; + RECT 302.24 0.52 302.5 13.45 ; + RECT 302.715 136.21 302.915 136.94 ; + RECT 303.26 0.155 304.03 0.445 ; + RECT 303.26 0.155 303.52 8.665 ; + RECT 303.77 0.155 304.03 8.665 ; + RECT 302.75 0.52 303.01 11.315 ; + RECT 303.125 136.21 303.485 136.94 ; + RECT 303.695 136.21 303.895 136.94 ; + RECT 304.28 0.52 304.54 9.955 ; + RECT 304.35 136.21 304.55 136.94 ; + RECT 304.76 136.21 305.12 136.94 ; + RECT 305.415 136.21 305.615 136.94 ; + RECT 305.91 136.21 306.27 136.94 ; + RECT 306.32 0.3 306.58 8.7 ; + RECT 306.48 136.21 306.68 136.94 ; + RECT 307.135 136.21 307.335 136.94 ; + RECT 306.83 0.18 307.6 0.88 ; + RECT 307.545 136.21 307.905 136.94 ; + RECT 308.115 136.21 308.315 136.94 ; + RECT 308.77 136.21 308.97 136.94 ; + RECT 309.025 0.52 309.285 6.28 ; + RECT 309.18 136.21 309.54 136.94 ; + RECT 309.835 136.21 310.035 136.94 ; + RECT 310.4 0.52 310.66 5.57 ; + RECT 310.33 136.21 310.69 136.94 ; + RECT 310.9 136.21 311.1 136.94 ; + RECT 310.91 0.3 311.17 5.235 ; + RECT 311.42 0.52 311.68 7.78 ; + RECT 311.555 136.21 311.755 136.94 ; + RECT 311.965 136.21 312.325 136.94 ; + RECT 312.27 0.52 312.53 4.315 ; + RECT 312.535 136.21 312.735 136.94 ; + RECT 313.19 136.21 313.39 136.94 ; + RECT 313.445 0.52 313.705 2.82 ; + RECT 313.6 136.21 313.96 136.94 ; + RECT 314.255 136.21 314.455 136.94 ; + RECT 314.75 136.21 315.11 136.94 ; + RECT 315.685 0.18 316.455 0.88 ; + RECT 315.685 0.18 315.945 12.9 ; + RECT 316.195 0.18 316.455 12.9 ; + RECT 314.975 0.52 315.235 2.82 ; + RECT 315.32 136.21 315.52 136.94 ; + RECT 316.705 0.155 317.475 0.445 ; + RECT 316.705 0.155 316.965 13.21 ; + RECT 317.215 0.155 317.475 13.21 ; + RECT 315.975 136.21 316.175 136.94 ; + RECT 316.385 136.21 316.745 136.94 ; + RECT 316.955 136.21 317.155 136.94 ; + RECT 317.61 136.21 317.81 136.94 ; + RECT 318.02 136.21 318.38 136.94 ; + RECT 318.675 136.21 318.875 136.94 ; + RECT 319.17 136.21 319.53 136.94 ; + RECT 319.41 0.52 319.67 14.115 ; + RECT 319.74 136.21 319.94 136.94 ; + RECT 319.92 0.52 320.18 13.45 ; + RECT 320.395 136.21 320.595 136.94 ; + RECT 320.94 0.155 321.71 0.445 ; + RECT 320.94 0.155 321.2 8.665 ; + RECT 321.45 0.155 321.71 8.665 ; + RECT 320.43 0.52 320.69 11.315 ; + RECT 320.805 136.21 321.165 136.94 ; + RECT 321.375 136.21 321.575 136.94 ; + RECT 321.96 0.52 322.22 9.955 ; + RECT 322.03 136.21 322.23 136.94 ; + RECT 322.44 136.21 322.8 136.94 ; + RECT 323.095 136.21 323.295 136.94 ; + RECT 323.59 136.21 323.95 136.94 ; + RECT 324 0.3 324.26 8.7 ; + RECT 324.16 136.21 324.36 136.94 ; + RECT 324.815 136.21 325.015 136.94 ; + RECT 324.51 0.18 325.28 0.88 ; + RECT 325.225 136.21 325.585 136.94 ; + RECT 325.795 136.21 325.995 136.94 ; + RECT 326.45 136.21 326.65 136.94 ; + RECT 326.705 0.52 326.965 6.28 ; + RECT 326.86 136.21 327.22 136.94 ; + RECT 327.515 136.21 327.715 136.94 ; + RECT 328.08 0.52 328.34 5.57 ; + RECT 328.01 136.21 328.37 136.94 ; + RECT 328.58 136.21 328.78 136.94 ; + RECT 328.59 0.3 328.85 5.235 ; + RECT 329.1 0.52 329.36 7.78 ; + RECT 329.235 136.21 329.435 136.94 ; + RECT 329.645 136.21 330.005 136.94 ; + RECT 329.95 0.52 330.21 4.315 ; + RECT 330.215 136.21 330.415 136.94 ; + RECT 330.87 136.21 331.07 136.94 ; + RECT 331.125 0.52 331.385 2.82 ; + RECT 331.28 136.21 331.64 136.94 ; + RECT 331.935 136.21 332.135 136.94 ; + RECT 332.43 136.21 332.79 136.94 ; + RECT 333.365 0.18 334.135 0.88 ; + RECT 333.365 0.18 333.625 12.9 ; + RECT 333.875 0.18 334.135 12.9 ; + RECT 332.655 0.52 332.915 2.82 ; + RECT 333 136.21 333.2 136.94 ; + RECT 334.385 0.155 335.155 0.445 ; + RECT 334.385 0.155 334.645 13.21 ; + RECT 334.895 0.155 335.155 13.21 ; + RECT 333.655 136.21 333.855 136.94 ; + RECT 334.065 136.21 334.425 136.94 ; + RECT 334.635 136.21 334.835 136.94 ; + RECT 335.29 136.21 335.49 136.94 ; + RECT 335.7 136.21 336.06 136.94 ; + RECT 336.355 136.21 336.555 136.94 ; + RECT 336.85 136.21 337.21 136.94 ; + RECT 337.09 0.52 337.35 14.115 ; + RECT 337.42 136.21 337.62 136.94 ; + RECT 337.6 0.52 337.86 13.45 ; + RECT 338.075 136.21 338.275 136.94 ; + RECT 338.62 0.155 339.39 0.445 ; + RECT 338.62 0.155 338.88 8.665 ; + RECT 339.13 0.155 339.39 8.665 ; + RECT 338.11 0.52 338.37 11.315 ; + RECT 338.485 136.21 338.845 136.94 ; + RECT 339.055 136.21 339.255 136.94 ; + RECT 339.64 0.52 339.9 9.955 ; + RECT 339.71 136.21 339.91 136.94 ; + RECT 340.12 136.21 340.48 136.94 ; + RECT 340.775 136.21 340.975 136.94 ; + RECT 341.27 136.21 341.63 136.94 ; + RECT 341.68 0.3 341.94 8.7 ; + RECT 341.84 136.21 342.04 136.94 ; + RECT 342.495 136.21 342.695 136.94 ; + RECT 342.19 0.18 342.96 0.88 ; + RECT 342.905 136.21 343.265 136.94 ; + RECT 343.475 136.21 343.675 136.94 ; + RECT 344.13 136.21 344.33 136.94 ; + RECT 344.385 0.52 344.645 6.28 ; + RECT 344.54 136.21 344.9 136.94 ; + RECT 345.195 136.21 345.395 136.94 ; + RECT 345.76 0.52 346.02 5.57 ; + RECT 345.69 136.21 346.05 136.94 ; + RECT 346.26 136.21 346.46 136.94 ; + RECT 346.27 0.3 346.53 5.235 ; + RECT 346.78 0.52 347.04 7.78 ; + RECT 346.915 136.21 347.115 136.94 ; + RECT 347.325 136.21 347.685 136.94 ; + RECT 347.63 0.52 347.89 4.315 ; + RECT 347.895 136.21 348.095 136.94 ; + RECT 348.55 136.21 348.75 136.94 ; + RECT 348.805 0.52 349.065 2.82 ; + RECT 348.96 136.21 349.32 136.94 ; + RECT 349.615 136.21 349.815 136.94 ; + RECT 350.11 136.21 350.47 136.94 ; + RECT 351.045 0.18 351.815 0.88 ; + RECT 351.045 0.18 351.305 12.9 ; + RECT 351.555 0.18 351.815 12.9 ; + RECT 350.335 0.52 350.595 2.82 ; + RECT 350.68 136.21 350.88 136.94 ; + RECT 352.065 0.155 352.835 0.445 ; + RECT 352.065 0.155 352.325 13.21 ; + RECT 352.575 0.155 352.835 13.21 ; + RECT 351.335 136.21 351.535 136.94 ; + RECT 351.745 136.21 352.105 136.94 ; + RECT 352.315 136.21 352.515 136.94 ; + RECT 352.97 136.21 353.17 136.94 ; + RECT 353.38 136.21 353.74 136.94 ; + RECT 354.035 136.21 354.235 136.94 ; + RECT 354.53 136.21 354.89 136.94 ; + RECT 354.77 0.52 355.03 14.115 ; + RECT 355.1 136.21 355.3 136.94 ; + RECT 355.28 0.52 355.54 13.45 ; + RECT 355.755 136.21 355.955 136.94 ; + RECT 356.3 0.155 357.07 0.445 ; + RECT 356.3 0.155 356.56 8.665 ; + RECT 356.81 0.155 357.07 8.665 ; + RECT 355.79 0.52 356.05 11.315 ; + RECT 356.165 136.21 356.525 136.94 ; + RECT 356.735 136.21 356.935 136.94 ; + RECT 357.32 0.52 357.58 9.955 ; + RECT 357.39 136.21 357.59 136.94 ; + RECT 357.8 136.21 358.16 136.94 ; + RECT 358.455 136.21 358.655 136.94 ; + RECT 358.95 136.21 359.31 136.94 ; + RECT 359.36 0.3 359.62 8.7 ; + RECT 359.52 136.21 359.72 136.94 ; + RECT 360.175 136.21 360.375 136.94 ; + RECT 359.87 0.18 360.64 0.88 ; + RECT 360.585 136.21 360.945 136.94 ; + RECT 361.155 136.21 361.355 136.94 ; + RECT 361.81 136.21 362.01 136.94 ; + RECT 362.065 0.52 362.325 6.28 ; + RECT 362.22 136.21 362.58 136.94 ; + RECT 362.875 136.21 363.075 136.94 ; + RECT 363.44 0.52 363.7 5.57 ; + RECT 363.37 136.21 363.73 136.94 ; + RECT 363.94 136.21 364.14 136.94 ; + RECT 363.95 0.3 364.21 5.235 ; + RECT 364.46 0.52 364.72 7.78 ; + RECT 364.595 136.21 364.795 136.94 ; + RECT 365.005 136.21 365.365 136.94 ; + RECT 365.31 0.52 365.57 4.315 ; + RECT 365.575 136.21 365.775 136.94 ; + RECT 366.23 136.21 366.43 136.94 ; + RECT 366.485 0.52 366.745 2.82 ; + RECT 366.64 136.21 367 136.94 ; + RECT 367.295 136.21 367.495 136.94 ; + RECT 367.79 136.21 368.15 136.94 ; + RECT 368.725 0.18 369.495 0.88 ; + RECT 368.725 0.18 368.985 12.9 ; + RECT 369.235 0.18 369.495 12.9 ; + RECT 368.015 0.52 368.275 2.82 ; + RECT 368.36 136.21 368.56 136.94 ; + RECT 369.745 0.155 370.515 0.445 ; + RECT 369.745 0.155 370.005 13.21 ; + RECT 370.255 0.155 370.515 13.21 ; + RECT 369.015 136.21 369.215 136.94 ; + RECT 369.425 136.21 369.785 136.94 ; + RECT 369.995 136.21 370.195 136.94 ; + RECT 370.65 136.21 370.85 136.94 ; + RECT 371.06 136.21 371.42 136.94 ; + RECT 371.715 136.21 371.915 136.94 ; + RECT 372.21 136.21 372.57 136.94 ; + RECT 372.45 0.52 372.71 14.115 ; + RECT 372.78 136.21 372.98 136.94 ; + RECT 372.96 0.52 373.22 13.45 ; + RECT 373.435 136.21 373.635 136.94 ; + RECT 373.98 0.155 374.75 0.445 ; + RECT 373.98 0.155 374.24 8.665 ; + RECT 374.49 0.155 374.75 8.665 ; + RECT 373.47 0.52 373.73 11.315 ; + RECT 373.845 136.21 374.205 136.94 ; + RECT 374.415 136.21 374.615 136.94 ; + RECT 375 0.52 375.26 9.955 ; + RECT 375.07 136.21 375.27 136.94 ; + RECT 375.48 136.21 375.84 136.94 ; + RECT 376.135 136.21 376.335 136.94 ; + RECT 376.63 136.21 376.99 136.94 ; + RECT 377.04 0.3 377.3 8.7 ; + RECT 377.2 136.21 377.4 136.94 ; + RECT 377.855 136.21 378.055 136.94 ; + RECT 377.55 0.18 378.32 0.88 ; + RECT 378.265 136.21 378.625 136.94 ; + RECT 378.835 136.21 379.035 136.94 ; + RECT 379.49 136.21 379.69 136.94 ; + RECT 379.745 0.52 380.005 6.28 ; + RECT 379.9 136.21 380.26 136.94 ; + RECT 380.555 136.21 380.755 136.94 ; + RECT 381.12 0.52 381.38 5.57 ; + RECT 381.05 136.21 381.41 136.94 ; + RECT 381.62 136.21 381.82 136.94 ; + RECT 381.63 0.3 381.89 5.235 ; + RECT 382.14 0.52 382.4 7.78 ; + RECT 382.275 136.21 382.475 136.94 ; + RECT 382.685 136.21 383.045 136.94 ; + RECT 382.99 0.52 383.25 4.315 ; + RECT 383.255 136.21 383.455 136.94 ; + RECT 383.91 136.21 384.11 136.94 ; + RECT 384.165 0.52 384.425 2.82 ; + RECT 384.32 136.21 384.68 136.94 ; + RECT 384.975 136.21 385.175 136.94 ; + RECT 385.47 136.21 385.83 136.94 ; + RECT 386.405 0.18 387.175 0.88 ; + RECT 386.405 0.18 386.665 12.9 ; + RECT 386.915 0.18 387.175 12.9 ; + RECT 385.695 0.52 385.955 2.82 ; + RECT 386.04 136.21 386.24 136.94 ; + RECT 387.425 0.155 388.195 0.445 ; + RECT 387.425 0.155 387.685 13.21 ; + RECT 387.935 0.155 388.195 13.21 ; + RECT 386.695 136.21 386.895 136.94 ; + RECT 387.105 136.21 387.465 136.94 ; + RECT 387.675 136.21 387.875 136.94 ; + RECT 388.33 136.21 388.53 136.94 ; + RECT 388.74 136.21 389.1 136.94 ; + RECT 389.395 136.21 389.595 136.94 ; + RECT 389.89 136.21 390.25 136.94 ; + RECT 390.13 0.52 390.39 14.115 ; + RECT 390.46 136.21 390.66 136.94 ; + RECT 390.64 0.52 390.9 13.45 ; + RECT 391.115 136.21 391.315 136.94 ; + RECT 391.66 0.155 392.43 0.445 ; + RECT 391.66 0.155 391.92 8.665 ; + RECT 392.17 0.155 392.43 8.665 ; + RECT 391.15 0.52 391.41 11.315 ; + RECT 391.525 136.21 391.885 136.94 ; + RECT 392.095 136.21 392.295 136.94 ; + RECT 392.68 0.52 392.94 9.955 ; + RECT 392.75 136.21 392.95 136.94 ; + RECT 393.16 136.21 393.52 136.94 ; + RECT 393.815 136.21 394.015 136.94 ; + RECT 394.31 136.21 394.67 136.94 ; + RECT 394.72 0.3 394.98 8.7 ; + RECT 394.88 136.21 395.08 136.94 ; + RECT 395.535 136.21 395.735 136.94 ; + RECT 395.23 0.18 396 0.88 ; + RECT 395.945 136.21 396.305 136.94 ; + RECT 396.515 136.21 396.715 136.94 ; + RECT 397.17 136.21 397.37 136.94 ; + RECT 397.425 0.52 397.685 6.28 ; + RECT 397.58 136.21 397.94 136.94 ; + RECT 398.235 136.21 398.435 136.94 ; + RECT 398.8 0.52 399.06 5.57 ; + RECT 398.73 136.21 399.09 136.94 ; + RECT 399.3 136.21 399.5 136.94 ; + RECT 399.31 0.3 399.57 5.235 ; + RECT 399.82 0.52 400.08 7.78 ; + RECT 399.955 136.21 400.155 136.94 ; + RECT 400.365 136.21 400.725 136.94 ; + RECT 400.67 0.52 400.93 4.315 ; + RECT 400.935 136.21 401.135 136.94 ; + RECT 401.59 136.21 401.79 136.94 ; + RECT 401.845 0.52 402.105 2.82 ; + RECT 402 136.21 402.36 136.94 ; + RECT 402.655 136.21 402.855 136.94 ; + RECT 403.15 136.21 403.51 136.94 ; + RECT 404.085 0.18 404.855 0.88 ; + RECT 404.085 0.18 404.345 12.9 ; + RECT 404.595 0.18 404.855 12.9 ; + RECT 403.375 0.52 403.635 2.82 ; + RECT 403.72 136.21 403.92 136.94 ; + RECT 405.105 0.155 405.875 0.445 ; + RECT 405.105 0.155 405.365 13.21 ; + RECT 405.615 0.155 405.875 13.21 ; + RECT 404.375 136.21 404.575 136.94 ; + RECT 404.785 136.21 405.145 136.94 ; + RECT 405.355 136.21 405.555 136.94 ; + RECT 406.01 136.21 406.21 136.94 ; + RECT 406.42 136.21 406.78 136.94 ; + RECT 407.075 136.21 407.275 136.94 ; + RECT 407.57 136.21 407.93 136.94 ; + RECT 407.81 0.52 408.07 14.115 ; + RECT 408.14 136.21 408.34 136.94 ; + RECT 408.32 0.52 408.58 13.45 ; + RECT 408.795 136.21 408.995 136.94 ; + RECT 409.34 0.155 410.11 0.445 ; + RECT 409.34 0.155 409.6 8.665 ; + RECT 409.85 0.155 410.11 8.665 ; + RECT 408.83 0.52 409.09 11.315 ; + RECT 409.205 136.21 409.565 136.94 ; + RECT 409.775 136.21 409.975 136.94 ; + RECT 410.36 0.52 410.62 9.955 ; + RECT 410.43 136.21 410.63 136.94 ; + RECT 410.84 136.21 411.2 136.94 ; + RECT 411.495 136.21 411.695 136.94 ; + RECT 411.99 136.21 412.35 136.94 ; + RECT 412.4 0.3 412.66 8.7 ; + RECT 412.56 136.21 412.76 136.94 ; + RECT 413.215 136.21 413.415 136.94 ; + RECT 412.91 0.18 413.68 0.88 ; + RECT 413.625 136.21 413.985 136.94 ; + RECT 414.195 136.21 414.395 136.94 ; + RECT 414.85 136.21 415.05 136.94 ; + RECT 415.105 0.52 415.365 6.28 ; + RECT 415.26 136.21 415.62 136.94 ; + RECT 415.915 136.21 416.115 136.94 ; + RECT 416.48 0.52 416.74 5.57 ; + RECT 416.41 136.21 416.77 136.94 ; + RECT 416.98 136.21 417.18 136.94 ; + RECT 416.99 0.3 417.25 5.235 ; + RECT 417.5 0.52 417.76 7.78 ; + RECT 417.635 136.21 417.835 136.94 ; + RECT 418.045 136.21 418.405 136.94 ; + RECT 418.615 136.21 418.815 136.94 ; + RECT 419.44 53.41 419.64 136.94 ; + LAYER Metal2 SPACING 0.21 ; + RECT 415.625 0 416.22 136.97 ; + RECT 416.99 0.3 417.25 136.97 ; + RECT 418.02 0 419.95 136.97 ; + RECT 0 0.52 419.95 136.97 ; + RECT 410.88 0 414.845 136.97 ; + RECT 409.34 0.155 410.11 136.97 ; + RECT 403.895 0 407.55 136.97 ; + RECT 402.365 0 403.115 136.97 ; + RECT 401.19 0 401.585 136.97 ; + RECT 399.31 0.3 399.57 136.97 ; + RECT 397.945 0 398.54 136.97 ; + RECT 393.2 0 397.165 136.97 ; + RECT 391.66 0.155 392.43 136.97 ; + RECT 386.215 0 389.87 136.97 ; + RECT 384.685 0 385.435 136.97 ; + RECT 383.51 0 383.905 136.97 ; + RECT 381.63 0.3 381.89 136.97 ; + RECT 380.265 0 380.86 136.97 ; + RECT 375.52 0 379.485 136.97 ; + RECT 373.98 0.155 374.75 136.97 ; + RECT 368.535 0 372.19 136.97 ; + RECT 367.005 0 367.755 136.97 ; + RECT 365.83 0 366.225 136.97 ; + RECT 363.95 0.3 364.21 136.97 ; + RECT 362.585 0 363.18 136.97 ; + RECT 357.84 0 361.805 136.97 ; + RECT 356.3 0.155 357.07 136.97 ; + RECT 350.855 0 354.51 136.97 ; + RECT 349.325 0 350.075 136.97 ; + RECT 348.15 0 348.545 136.97 ; + RECT 346.27 0.3 346.53 136.97 ; + RECT 344.905 0 345.5 136.97 ; + RECT 340.16 0 344.125 136.97 ; + RECT 338.62 0.155 339.39 136.97 ; + RECT 333.175 0 336.83 136.97 ; + RECT 331.645 0 332.395 136.97 ; + RECT 330.47 0 330.865 136.97 ; + RECT 328.59 0.3 328.85 136.97 ; + RECT 327.225 0 327.82 136.97 ; + RECT 322.48 0 326.445 136.97 ; + RECT 320.94 0.155 321.71 136.97 ; + RECT 315.495 0 319.15 136.97 ; + RECT 313.965 0 314.715 136.97 ; + RECT 312.79 0 313.185 136.97 ; + RECT 310.91 0.3 311.17 136.97 ; + RECT 309.545 0 310.14 136.97 ; + RECT 304.8 0 308.765 136.97 ; + RECT 303.26 0.155 304.03 136.97 ; + RECT 297.815 0 301.47 136.97 ; + RECT 296.285 0 297.035 136.97 ; + RECT 295.11 0 295.505 136.97 ; + RECT 293.23 0.3 293.49 136.97 ; + RECT 291.865 0 292.46 136.97 ; + RECT 287.12 0 291.085 136.97 ; + RECT 285.58 0.155 286.35 136.97 ; + RECT 280.135 0 283.79 136.97 ; + RECT 278.605 0 279.355 136.97 ; + RECT 277.43 0 277.825 136.97 ; + RECT 245.955 0.18 276.65 136.97 ; + RECT 245.965 0 276.65 136.97 ; + RECT 238.305 0.3 245.195 136.97 ; + RECT 232.695 0.3 233.975 136.97 ; + RECT 230.145 0.3 231.425 136.97 ; + RECT 228.615 0.3 228.875 136.97 ; + RECT 225.555 0.3 225.815 136.97 ; + RECT 224.025 0.3 224.285 136.97 ; + RECT 215.865 0.3 222.755 136.97 ; + RECT 206.375 0 213.575 136.97 ; + RECT 197.195 0.3 204.085 136.97 ; + RECT 197.205 0 204.085 136.97 ; + RECT 195.665 0.3 195.925 136.97 ; + RECT 194.135 0.3 194.395 136.97 ; + RECT 191.075 0.3 191.335 136.97 ; + RECT 188.525 0.3 189.805 136.97 ; + RECT 185.975 0.3 187.255 136.97 ; + RECT 174.755 0.3 181.645 136.97 ; + RECT 174.765 0 181.645 136.97 ; + RECT 143.3 0.18 173.995 136.97 ; + RECT 142.125 0 142.52 136.97 ; + RECT 140.595 0 141.345 136.97 ; + RECT 136.16 0 139.815 136.97 ; + RECT 133.6 0.155 134.37 136.97 ; + RECT 128.865 0 132.83 136.97 ; + RECT 127.49 0 128.085 136.97 ; + RECT 126.46 0.3 126.72 136.97 ; + RECT 124.445 0 124.84 136.97 ; + RECT 122.915 0 123.665 136.97 ; + RECT 118.48 0 122.135 136.97 ; + RECT 115.92 0.155 116.69 136.97 ; + RECT 111.185 0 115.15 136.97 ; + RECT 109.81 0 110.405 136.97 ; + RECT 108.78 0.3 109.04 136.97 ; + RECT 106.765 0 107.16 136.97 ; + RECT 105.235 0 105.985 136.97 ; + RECT 100.8 0 104.455 136.97 ; + RECT 98.24 0.155 99.01 136.97 ; + RECT 93.505 0 97.47 136.97 ; + RECT 92.13 0 92.725 136.97 ; + RECT 91.1 0.3 91.36 136.97 ; + RECT 89.085 0 89.48 136.97 ; + RECT 87.555 0 88.305 136.97 ; + RECT 83.12 0 86.775 136.97 ; + RECT 80.56 0.155 81.33 136.97 ; + RECT 75.825 0 79.79 136.97 ; + RECT 74.45 0 75.045 136.97 ; + RECT 73.42 0.3 73.68 136.97 ; + RECT 71.405 0 71.8 136.97 ; + RECT 69.875 0 70.625 136.97 ; + RECT 65.44 0 69.095 136.97 ; + RECT 62.88 0.155 63.65 136.97 ; + RECT 58.145 0 62.11 136.97 ; + RECT 56.77 0 57.365 136.97 ; + RECT 55.74 0.3 56 136.97 ; + RECT 53.725 0 54.12 136.97 ; + RECT 52.195 0 52.945 136.97 ; + RECT 47.76 0 51.415 136.97 ; + RECT 45.2 0.155 45.97 136.97 ; + RECT 40.465 0 44.43 136.97 ; + RECT 39.09 0 39.685 136.97 ; + RECT 38.06 0.3 38.32 136.97 ; + RECT 36.045 0 36.44 136.97 ; + RECT 34.515 0 35.265 136.97 ; + RECT 30.08 0 33.735 136.97 ; + RECT 27.52 0.155 28.29 136.97 ; + RECT 22.785 0 26.75 136.97 ; + RECT 21.41 0 22.005 136.97 ; + RECT 20.38 0.3 20.64 136.97 ; + RECT 18.365 0 18.76 136.97 ; + RECT 16.835 0 17.585 136.97 ; + RECT 12.4 0 16.055 136.97 ; + RECT 9.84 0.155 10.61 136.97 ; + RECT 5.105 0 9.07 136.97 ; + RECT 3.73 0 4.325 136.97 ; + RECT 2.7 0.3 2.96 136.97 ; + RECT 0 0 1.93 136.97 ; + RECT 417 0 417.24 136.97 ; + RECT 399.32 0 399.56 136.97 ; + RECT 381.64 0 381.88 136.97 ; + RECT 363.96 0 364.2 136.97 ; + RECT 346.28 0 346.52 136.97 ; + RECT 328.6 0 328.84 136.97 ; + RECT 310.92 0 311.16 136.97 ; + RECT 293.24 0 293.48 136.97 ; + RECT 238.305 0 245.185 136.97 ; + RECT 232.705 0 233.965 136.97 ; + RECT 230.155 0 231.415 136.97 ; + RECT 228.625 0 228.865 136.97 ; + RECT 225.565 0 225.805 136.97 ; + RECT 224.035 0 224.275 136.97 ; + RECT 215.865 0 222.745 136.97 ; + RECT 195.675 0 195.915 136.97 ; + RECT 194.145 0 194.385 136.97 ; + RECT 191.085 0 191.325 136.97 ; + RECT 188.535 0 189.795 136.97 ; + RECT 185.985 0 187.245 136.97 ; + RECT 126.47 0 126.71 136.97 ; + RECT 108.79 0 109.03 136.97 ; + RECT 91.11 0 91.35 136.97 ; + RECT 73.43 0 73.67 136.97 ; + RECT 55.75 0 55.99 136.97 ; + RECT 38.07 0 38.31 136.97 ; + RECT 20.39 0 20.63 136.97 ; + RECT 2.71 0 2.95 136.97 ; + RECT 143.3 0 173.985 136.97 ; + RECT 409.35 0 410.1 136.97 ; + RECT 391.67 0 392.42 136.97 ; + RECT 373.99 0 374.74 136.97 ; + RECT 356.31 0 357.06 136.97 ; + RECT 338.63 0 339.38 136.97 ; + RECT 320.95 0 321.7 136.97 ; + RECT 303.27 0 304.02 136.97 ; + RECT 285.59 0 286.34 136.97 ; + RECT 133.61 0 134.36 136.97 ; + RECT 115.93 0 116.68 136.97 ; + RECT 98.25 0 99 136.97 ; + RECT 80.57 0 81.32 136.97 ; + RECT 62.89 0 63.64 136.97 ; + RECT 45.21 0 45.96 136.97 ; + RECT 27.53 0 28.28 136.97 ; + RECT 9.85 0 10.6 136.97 ; + LAYER Metal3 ; + RECT 0 0 419.95 136.97 ; + LAYER Metal4 SPACING 0.21 ; + RECT 250.265 0 276.525 136.97 ; + RECT 245.115 0 246.935 136.97 ; + RECT 239.965 0 241.785 136.97 ; + RECT 414.065 0 419.95 136.97 ; + RECT 405.225 0 409.125 136.97 ; + RECT 405.225 47.305 419.95 53.15 ; + RECT 396.385 0 400.285 136.97 ; + RECT 387.545 0 391.445 136.97 ; + RECT 387.545 47.305 400.285 53.15 ; + RECT 378.705 0 382.605 136.97 ; + RECT 369.865 0 373.765 136.97 ; + RECT 369.865 47.305 382.605 53.15 ; + RECT 361.025 0 364.925 136.97 ; + RECT 352.185 0 356.085 136.97 ; + RECT 352.185 47.305 364.925 53.15 ; + RECT 343.345 0 347.245 136.97 ; + RECT 334.505 0 338.405 136.97 ; + RECT 334.505 47.305 347.245 53.15 ; + RECT 325.665 0 329.565 136.97 ; + RECT 316.825 0 320.725 136.97 ; + RECT 316.825 47.305 329.565 53.15 ; + RECT 307.985 0 311.885 136.97 ; + RECT 299.145 0 303.045 136.97 ; + RECT 299.145 47.305 311.885 53.15 ; + RECT 290.305 0 294.205 136.97 ; + RECT 281.465 0 285.365 136.97 ; + RECT 281.465 47.305 294.205 53.15 ; + RECT 234.815 0 236.635 136.97 ; + RECT 229.665 0 231.485 136.97 ; + RECT 224.515 0 226.335 136.97 ; + RECT 219.365 0 221.185 136.97 ; + RECT 214.215 0 216.035 136.97 ; + RECT 209.065 0 210.885 136.97 ; + RECT 203.915 0 205.735 136.97 ; + RECT 198.765 0 200.585 136.97 ; + RECT 193.615 0 195.435 136.97 ; + RECT 188.465 0 190.285 136.97 ; + RECT 183.315 0 185.135 136.97 ; + RECT 178.165 0 179.985 136.97 ; + RECT 173.015 0 174.835 136.97 ; + RECT 143.425 0 169.685 136.97 ; + RECT 134.585 0 138.485 136.97 ; + RECT 125.745 0 129.645 136.97 ; + RECT 125.745 47.305 138.485 53.15 ; + RECT 116.905 0 120.805 136.97 ; + RECT 108.065 0 111.965 136.97 ; + RECT 108.065 47.305 120.805 53.15 ; + RECT 99.225 0 103.125 136.97 ; + RECT 90.385 0 94.285 136.97 ; + RECT 90.385 47.305 103.125 53.15 ; + RECT 81.545 0 85.445 136.97 ; + RECT 72.705 0 76.605 136.97 ; + RECT 72.705 47.305 85.445 53.15 ; + RECT 63.865 0 67.765 136.97 ; + RECT 55.025 0 58.925 136.97 ; + RECT 55.025 47.305 67.765 53.15 ; + RECT 46.185 0 50.085 136.97 ; + RECT 37.345 0 41.245 136.97 ; + RECT 37.345 47.305 50.085 53.15 ; + RECT 28.505 0 32.405 136.97 ; + RECT 19.665 0 23.565 136.97 ; + RECT 19.665 47.305 32.405 53.15 ; + RECT 10.825 0 14.725 136.97 ; + RECT 0 0 5.885 136.97 ; + RECT 0 47.305 14.725 53.15 ; + END +END RM_IHPSG13_2P_256x16_c2_bm_bist + +END LIBRARY diff --git a/flow/platforms/ihp-sg13g2/lef/RM_IHPSG13_2P_256x32_c2_bm_bist.lef b/flow/platforms/ihp-sg13g2/lef/RM_IHPSG13_2P_256x32_c2_bm_bist.lef new file mode 100644 index 0000000000..e851d2e598 --- /dev/null +++ b/flow/platforms/ihp-sg13g2/lef/RM_IHPSG13_2P_256x32_c2_bm_bist.lef @@ -0,0 +1,7359 @@ +# ------------------------------------------------------ +# +# Copyright 2025 IHP PDK Authors +# +# Licensed under the Apache License, Version 2.0 (the "License"); +# you may not use this file except in compliance with the License. +# You may obtain a copy of the License at +# +# https://www.apache.org/licenses/LICENSE-2.0 +# +# Unless required by applicable law or agreed to in writing, software +# distributed under the License is distributed on an "AS IS" BASIS, +# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +# See the License for the specific language governing permissions and +# limitations under the License. +# +# Generated on Wed Aug 27 13:14:43 2025 +# +# ------------------------------------------------------ +VERSION 5.7 ; +BUSBITCHARS "[]" ; +DIVIDERCHAR "/" ; + +MACRO RM_IHPSG13_2P_256x32_c2_bm_bist + CLASS BLOCK ; + ORIGIN 0 0 ; + FOREIGN RM_IHPSG13_2P_256x32_c2_bm_bist 0 0 ; + SIZE 702.83 BY 136.97 ; + SYMMETRY X Y R90 ; + PIN A_DIN[16] + DIRECTION INPUT ; + USE SIGNAL ; + ANTENNAPARTIALMETALAREA 3.9091 LAYER Metal2 ; + ANTENNAMODEL OXIDE1 ; + ANTENNAGATEAREA 0.20085 LAYER Metal2 ; + ANTENNAMAXAREACAR 20.368932 LAYER Metal2 ; + PORT + LAYER Metal2 ; + RECT 425.49 0 425.75 0.26 ; + END + END A_DIN[16] + PIN A_DIN[15] + DIRECTION INPUT ; + USE SIGNAL ; + ANTENNAPARTIALMETALAREA 3.9091 LAYER Metal2 ; + ANTENNAMODEL OXIDE1 ; + ANTENNAGATEAREA 0.20085 LAYER Metal2 ; + ANTENNAMAXAREACAR 20.368932 LAYER Metal2 ; + PORT + LAYER Metal2 ; + RECT 277.08 0 277.34 0.26 ; + END + END A_DIN[15] + PIN A_BIST_DIN[16] + DIRECTION INPUT ; + USE SIGNAL ; + ANTENNAPARTIALMETALAREA 4.136375 LAYER Metal2 ; + ANTENNAMODEL OXIDE1 ; + ANTENNAGATEAREA 0.20085 LAYER Metal2 ; + ANTENNAMAXAREACAR 21.874907 LAYER Metal2 ; + PORT + LAYER Metal2 ; + RECT 426 0 426.26 0.26 ; + END + END A_BIST_DIN[16] + PIN A_BIST_DIN[15] + DIRECTION INPUT ; + USE SIGNAL ; + ANTENNAPARTIALMETALAREA 4.136375 LAYER Metal2 ; + ANTENNAMODEL OXIDE1 ; + ANTENNAGATEAREA 0.20085 LAYER Metal2 ; + ANTENNAMAXAREACAR 21.874907 LAYER Metal2 ; + PORT + LAYER Metal2 ; + RECT 276.57 0 276.83 0.26 ; + END + END A_BIST_DIN[15] + PIN A_BM[16] + DIRECTION INPUT ; + USE SIGNAL ; + ANTENNAPARTIALMETALAREA 1.7264 LAYER Metal2 ; + ANTENNAMODEL OXIDE1 ; + ANTENNAGATEAREA 0.20085 LAYER Metal2 ; + ANTENNAMAXAREACAR 9.501618 LAYER Metal2 ; + PORT + LAYER Metal2 ; + RECT 434.16 0 434.42 0.26 ; + END + END A_BM[16] + PIN A_BM[15] + DIRECTION INPUT ; + USE SIGNAL ; + ANTENNAPARTIALMETALAREA 1.7264 LAYER Metal2 ; + ANTENNAMODEL OXIDE1 ; + ANTENNAGATEAREA 0.20085 LAYER Metal2 ; + ANTENNAMAXAREACAR 9.501618 LAYER Metal2 ; + PORT + LAYER Metal2 ; + RECT 268.41 0 268.67 0.26 ; + END + END A_BM[15] + PIN A_BIST_BM[16] + DIRECTION INPUT ; + USE SIGNAL ; + ANTENNAPARTIALMETALAREA 1.7602 LAYER Metal2 ; + ANTENNAMODEL OXIDE1 ; + ANTENNAGATEAREA 0.20085 LAYER Metal2 ; + ANTENNAMAXAREACAR 9.678367 LAYER Metal2 ; + PORT + LAYER Metal2 ; + RECT 432.785 0 433.045 0.26 ; + END + END A_BIST_BM[16] + PIN A_BIST_BM[15] + DIRECTION INPUT ; + USE SIGNAL ; + ANTENNAPARTIALMETALAREA 1.7602 LAYER Metal2 ; + ANTENNAMODEL OXIDE1 ; + ANTENNAGATEAREA 0.20085 LAYER Metal2 ; + ANTENNAMAXAREACAR 9.678367 LAYER Metal2 ; + PORT + LAYER Metal2 ; + RECT 269.785 0 270.045 0.26 ; + END + END A_BIST_BM[15] + PIN A_DOUT[16] + DIRECTION OUTPUT ; + USE SIGNAL ; + ANTENNAPARTIALMETALAREA 4.8256 LAYER Metal2 ; + ANTENNADIFFAREA 0.988 LAYER Metal2 ; + PORT + LAYER Metal2 ; + RECT 418.35 0 418.61 0.26 ; + END + END A_DOUT[16] + PIN A_DOUT[15] + DIRECTION OUTPUT ; + USE SIGNAL ; + ANTENNAPARTIALMETALAREA 4.8256 LAYER Metal2 ; + ANTENNADIFFAREA 0.988 LAYER Metal2 ; + PORT + LAYER Metal2 ; + RECT 284.22 0 284.48 0.26 ; + END + END A_DOUT[15] + PIN B_DIN[16] + DIRECTION INPUT ; + USE SIGNAL ; + ANTENNAPARTIALMETALAREA 2.925 LAYER Metal2 ; + ANTENNAMODEL OXIDE1 ; + ANTENNAGATEAREA 0.20085 LAYER Metal2 ; + ANTENNAMAXAREACAR 15.469256 LAYER Metal2 ; + PORT + LAYER Metal2 ; + RECT 428.04 0 428.3 0.26 ; + END + END B_DIN[16] + PIN B_DIN[15] + DIRECTION INPUT ; + USE SIGNAL ; + ANTENNAPARTIALMETALAREA 2.925 LAYER Metal2 ; + ANTENNAMODEL OXIDE1 ; + ANTENNAGATEAREA 0.20085 LAYER Metal2 ; + ANTENNAMAXAREACAR 15.469256 LAYER Metal2 ; + PORT + LAYER Metal2 ; + RECT 274.53 0 274.79 0.26 ; + END + END B_DIN[15] + PIN B_BIST_DIN[16] + DIRECTION INPUT ; + USE SIGNAL ; + ANTENNAPARTIALMETALAREA 2.9445 LAYER Metal2 ; + ANTENNAMODEL OXIDE1 ; + ANTENNAGATEAREA 0.20085 LAYER Metal2 ; + ANTENNAMAXAREACAR 15.929052 LAYER Metal2 ; + PORT + LAYER Metal2 ; + RECT 426.51 0 426.77 0.26 ; + END + END B_BIST_DIN[16] + PIN B_BIST_DIN[15] + DIRECTION INPUT ; + USE SIGNAL ; + ANTENNAPARTIALMETALAREA 2.9445 LAYER Metal2 ; + ANTENNAMODEL OXIDE1 ; + ANTENNAGATEAREA 0.20085 LAYER Metal2 ; + ANTENNAMAXAREACAR 15.929052 LAYER Metal2 ; + PORT + LAYER Metal2 ; + RECT 276.06 0 276.32 0.26 ; + END + END B_BIST_DIN[15] + PIN B_BM[16] + DIRECTION INPUT ; + USE SIGNAL ; + ANTENNAPARTIALMETALAREA 0.7007 LAYER Metal2 ; + ANTENNAMODEL OXIDE1 ; + ANTENNAGATEAREA 0.20085 LAYER Metal2 ; + ANTENNAMAXAREACAR 4.394822 LAYER Metal2 ; + PORT + LAYER Metal2 ; + RECT 419.525 0 419.785 0.26 ; + END + END B_BM[16] + PIN B_BM[15] + DIRECTION INPUT ; + USE SIGNAL ; + ANTENNAPARTIALMETALAREA 0.7007 LAYER Metal2 ; + ANTENNAMODEL OXIDE1 ; + ANTENNAGATEAREA 0.20085 LAYER Metal2 ; + ANTENNAMAXAREACAR 4.394822 LAYER Metal2 ; + PORT + LAYER Metal2 ; + RECT 283.045 0 283.305 0.26 ; + END + END B_BM[15] + PIN B_BIST_BM[16] + DIRECTION INPUT ; + USE SIGNAL ; + ANTENNAPARTIALMETALAREA 0.7007 LAYER Metal2 ; + ANTENNAMODEL OXIDE1 ; + ANTENNAGATEAREA 0.20085 LAYER Metal2 ; + ANTENNAMAXAREACAR 4.394822 LAYER Metal2 ; + PORT + LAYER Metal2 ; + RECT 421.055 0 421.315 0.26 ; + END + END B_BIST_BM[16] + PIN B_BIST_BM[15] + DIRECTION INPUT ; + USE SIGNAL ; + ANTENNAPARTIALMETALAREA 0.7007 LAYER Metal2 ; + ANTENNAMODEL OXIDE1 ; + ANTENNAGATEAREA 0.20085 LAYER Metal2 ; + ANTENNAMAXAREACAR 4.394822 LAYER Metal2 ; + PORT + LAYER Metal2 ; + RECT 281.515 0 281.775 0.26 ; + END + END B_BIST_BM[15] + PIN B_DOUT[16] + DIRECTION OUTPUT ; + USE SIGNAL ; + ANTENNAPARTIALMETALAREA 4.836 LAYER Metal2 ; + ANTENNADIFFAREA 0.988 LAYER Metal2 ; + PORT + LAYER Metal2 ; + RECT 435.18 0 435.44 0.26 ; + END + END B_DOUT[16] + PIN B_DOUT[15] + DIRECTION OUTPUT ; + USE SIGNAL ; + ANTENNAPARTIALMETALAREA 4.836 LAYER Metal2 ; + ANTENNADIFFAREA 0.988 LAYER Metal2 ; + PORT + LAYER Metal2 ; + RECT 267.39 0 267.65 0.26 ; + END + END B_DOUT[15] + PIN VSS! + DIRECTION INOUT ; + USE GROUND ; + NETEXPR "vss VSS!" ; + PORT + LAYER Metal4 ; + RECT 683.425 0 687.845 136.97 ; + END + PORT + LAYER Metal4 ; + RECT 665.745 0 670.165 136.97 ; + END + PORT + LAYER Metal4 ; + RECT 648.065 0 652.485 136.97 ; + END + PORT + LAYER Metal4 ; + RECT 630.385 0 634.805 136.97 ; + END + PORT + LAYER Metal4 ; + RECT 612.705 0 617.125 136.97 ; + END + PORT + LAYER Metal4 ; + RECT 595.025 0 599.445 136.97 ; + END + PORT + LAYER Metal4 ; + RECT 577.345 0 581.765 136.97 ; + END + PORT + LAYER Metal4 ; + RECT 559.665 0 564.085 136.97 ; + END + PORT + LAYER Metal4 ; + RECT 541.985 0 546.405 136.97 ; + END + PORT + LAYER Metal4 ; + RECT 524.305 0 528.725 136.97 ; + END + PORT + LAYER Metal4 ; + RECT 506.625 0 511.045 136.97 ; + END + PORT + LAYER Metal4 ; + RECT 488.945 0 493.365 136.97 ; + END + PORT + LAYER Metal4 ; + RECT 471.265 0 475.685 136.97 ; + END + PORT + LAYER Metal4 ; + RECT 453.585 0 458.005 136.97 ; + END + PORT + LAYER Metal4 ; + RECT 435.905 0 440.325 136.97 ; + END + PORT + LAYER Metal4 ; + RECT 418.225 0 422.645 136.97 ; + END + PORT + LAYER Metal4 ; + RECT 388.635 0 391.445 136.97 ; + END + PORT + LAYER Metal4 ; + RECT 378.335 0 381.145 136.97 ; + END + PORT + LAYER Metal4 ; + RECT 362.885 0 365.695 136.97 ; + END + PORT + LAYER Metal4 ; + RECT 352.585 0 355.395 136.97 ; + END + PORT + LAYER Metal4 ; + RECT 347.435 0 350.245 136.97 ; + END + PORT + LAYER Metal4 ; + RECT 337.135 0 339.945 136.97 ; + END + PORT + LAYER Metal4 ; + RECT 321.685 0 324.495 136.97 ; + END + PORT + LAYER Metal4 ; + RECT 311.385 0 314.195 136.97 ; + END + PORT + LAYER Metal4 ; + RECT 280.185 0 284.605 136.97 ; + END + PORT + LAYER Metal4 ; + RECT 262.505 0 266.925 136.97 ; + END + PORT + LAYER Metal4 ; + RECT 244.825 0 249.245 136.97 ; + END + PORT + LAYER Metal4 ; + RECT 227.145 0 231.565 136.97 ; + END + PORT + LAYER Metal4 ; + RECT 209.465 0 213.885 136.97 ; + END + PORT + LAYER Metal4 ; + RECT 191.785 0 196.205 136.97 ; + END + PORT + LAYER Metal4 ; + RECT 174.105 0 178.525 136.97 ; + END + PORT + LAYER Metal4 ; + RECT 156.425 0 160.845 136.97 ; + END + PORT + LAYER Metal4 ; + RECT 138.745 0 143.165 136.97 ; + END + PORT + LAYER Metal4 ; + RECT 121.065 0 125.485 136.97 ; + END + PORT + LAYER Metal4 ; + RECT 103.385 0 107.805 136.97 ; + END + PORT + LAYER Metal4 ; + RECT 85.705 0 90.125 136.97 ; + END + PORT + LAYER Metal4 ; + RECT 68.025 0 72.445 136.97 ; + END + PORT + LAYER Metal4 ; + RECT 50.345 0 54.765 136.97 ; + END + PORT + LAYER Metal4 ; + RECT 32.665 0 37.085 136.97 ; + END + PORT + LAYER Metal4 ; + RECT 14.985 0 19.405 136.97 ; + END + END VSS! + PIN VDD! + DIRECTION INOUT ; + USE POWER ; + NETEXPR "vdd VDD!" ; + PORT + LAYER Metal4 ; + RECT 692.265 0 696.685 47.045 ; + END + PORT + LAYER Metal4 ; + RECT 674.585 0 679.005 47.045 ; + END + PORT + LAYER Metal4 ; + RECT 656.905 0 661.325 47.045 ; + END + PORT + LAYER Metal4 ; + RECT 639.225 0 643.645 47.045 ; + END + PORT + LAYER Metal4 ; + RECT 621.545 0 625.965 47.045 ; + END + PORT + LAYER Metal4 ; + RECT 603.865 0 608.285 47.045 ; + END + PORT + LAYER Metal4 ; + RECT 586.185 0 590.605 47.045 ; + END + PORT + LAYER Metal4 ; + RECT 568.505 0 572.925 47.045 ; + END + PORT + LAYER Metal4 ; + RECT 550.825 0 555.245 47.045 ; + END + PORT + LAYER Metal4 ; + RECT 533.145 0 537.565 47.045 ; + END + PORT + LAYER Metal4 ; + RECT 515.465 0 519.885 47.045 ; + END + PORT + LAYER Metal4 ; + RECT 497.785 0 502.205 47.045 ; + END + PORT + LAYER Metal4 ; + RECT 480.105 0 484.525 47.045 ; + END + PORT + LAYER Metal4 ; + RECT 462.425 0 466.845 47.045 ; + END + PORT + LAYER Metal4 ; + RECT 444.745 0 449.165 47.045 ; + END + PORT + LAYER Metal4 ; + RECT 427.065 0 431.485 47.045 ; + END + PORT + LAYER Metal4 ; + RECT 383.485 0 386.295 136.97 ; + END + PORT + LAYER Metal4 ; + RECT 373.185 0 375.995 136.97 ; + END + PORT + LAYER Metal4 ; + RECT 368.035 0 370.845 136.97 ; + END + PORT + LAYER Metal4 ; + RECT 357.735 0 360.545 136.97 ; + END + PORT + LAYER Metal4 ; + RECT 342.285 0 345.095 136.97 ; + END + PORT + LAYER Metal4 ; + RECT 331.985 0 334.795 136.97 ; + END + PORT + LAYER Metal4 ; + RECT 326.835 0 329.645 136.97 ; + END + PORT + LAYER Metal4 ; + RECT 316.535 0 319.345 136.97 ; + END + PORT + LAYER Metal4 ; + RECT 271.345 0 275.765 47.045 ; + END + PORT + LAYER Metal4 ; + RECT 253.665 0 258.085 47.045 ; + END + PORT + LAYER Metal4 ; + RECT 235.985 0 240.405 47.045 ; + END + PORT + LAYER Metal4 ; + RECT 218.305 0 222.725 47.045 ; + END + PORT + LAYER Metal4 ; + RECT 200.625 0 205.045 47.045 ; + END + PORT + LAYER Metal4 ; + RECT 182.945 0 187.365 47.045 ; + END + PORT + LAYER Metal4 ; + RECT 165.265 0 169.685 47.045 ; + END + PORT + LAYER Metal4 ; + RECT 147.585 0 152.005 47.045 ; + END + PORT + LAYER Metal4 ; + RECT 129.905 0 134.325 47.045 ; + END + PORT + LAYER Metal4 ; + RECT 112.225 0 116.645 47.045 ; + END + PORT + LAYER Metal4 ; + RECT 94.545 0 98.965 47.045 ; + END + PORT + LAYER Metal4 ; + RECT 76.865 0 81.285 47.045 ; + END + PORT + LAYER Metal4 ; + RECT 59.185 0 63.605 47.045 ; + END + PORT + LAYER Metal4 ; + RECT 41.505 0 45.925 47.045 ; + END + PORT + LAYER Metal4 ; + RECT 23.825 0 28.245 47.045 ; + END + PORT + LAYER Metal4 ; + RECT 6.145 0 10.565 47.045 ; + END + END VDD! + PIN VDDARRAY! + DIRECTION INOUT ; + USE POWER ; + NETEXPR "vddarray VDDARRAY!" ; + PORT + LAYER Metal4 ; + RECT 692.265 53.41 696.685 136.97 ; + END + PORT + LAYER Metal4 ; + RECT 674.585 53.41 679.005 136.97 ; + END + PORT + LAYER Metal4 ; + RECT 656.905 53.41 661.325 136.97 ; + END + PORT + LAYER Metal4 ; + RECT 639.225 53.41 643.645 136.97 ; + END + PORT + LAYER Metal4 ; + RECT 621.545 53.41 625.965 136.97 ; + END + PORT + LAYER Metal4 ; + RECT 603.865 53.41 608.285 136.97 ; + END + PORT + LAYER Metal4 ; + RECT 586.185 53.41 590.605 136.97 ; + END + PORT + LAYER Metal4 ; + RECT 568.505 53.41 572.925 136.97 ; + END + PORT + LAYER Metal4 ; + RECT 550.825 53.41 555.245 136.97 ; + END + PORT + LAYER Metal4 ; + RECT 533.145 53.41 537.565 136.97 ; + END + PORT + LAYER Metal4 ; + RECT 515.465 53.41 519.885 136.97 ; + END + PORT + LAYER Metal4 ; + RECT 497.785 53.41 502.205 136.97 ; + END + PORT + LAYER Metal4 ; + RECT 480.105 53.41 484.525 136.97 ; + END + PORT + LAYER Metal4 ; + RECT 462.425 53.41 466.845 136.97 ; + END + PORT + LAYER Metal4 ; + RECT 444.745 53.41 449.165 136.97 ; + END + PORT + LAYER Metal4 ; + RECT 427.065 53.41 431.485 136.97 ; + END + PORT + LAYER Metal4 ; + RECT 271.345 53.41 275.765 136.97 ; + END + PORT + LAYER Metal4 ; + RECT 253.665 53.41 258.085 136.97 ; + END + PORT + LAYER Metal4 ; + RECT 235.985 53.41 240.405 136.97 ; + END + PORT + LAYER Metal4 ; + RECT 218.305 53.41 222.725 136.97 ; + END + PORT + LAYER Metal4 ; + RECT 200.625 53.41 205.045 136.97 ; + END + PORT + LAYER Metal4 ; + RECT 182.945 53.41 187.365 136.97 ; + END + PORT + LAYER Metal4 ; + RECT 165.265 53.41 169.685 136.97 ; + END + PORT + LAYER Metal4 ; + RECT 147.585 53.41 152.005 136.97 ; + END + PORT + LAYER Metal4 ; + RECT 129.905 53.41 134.325 136.97 ; + END + PORT + LAYER Metal4 ; + RECT 112.225 53.41 116.645 136.97 ; + END + PORT + LAYER Metal4 ; + RECT 94.545 53.41 98.965 136.97 ; + END + PORT + LAYER Metal4 ; + RECT 76.865 53.41 81.285 136.97 ; + END + PORT + LAYER Metal4 ; + RECT 59.185 53.41 63.605 136.97 ; + END + PORT + LAYER Metal4 ; + RECT 41.505 53.41 45.925 136.97 ; + END + PORT + LAYER Metal4 ; + RECT 23.825 53.41 28.245 136.97 ; + END + PORT + LAYER Metal4 ; + RECT 6.145 53.41 10.565 136.97 ; + END + END VDDARRAY! + PIN A_DIN[17] + DIRECTION INPUT ; + USE SIGNAL ; + ANTENNAPARTIALMETALAREA 3.9091 LAYER Metal2 ; + ANTENNAMODEL OXIDE1 ; + ANTENNAGATEAREA 0.20085 LAYER Metal2 ; + ANTENNAMAXAREACAR 20.368932 LAYER Metal2 ; + PORT + LAYER Metal2 ; + RECT 443.17 0 443.43 0.26 ; + END + END A_DIN[17] + PIN A_DIN[14] + DIRECTION INPUT ; + USE SIGNAL ; + ANTENNAPARTIALMETALAREA 3.9091 LAYER Metal2 ; + ANTENNAMODEL OXIDE1 ; + ANTENNAGATEAREA 0.20085 LAYER Metal2 ; + ANTENNAMAXAREACAR 20.368932 LAYER Metal2 ; + PORT + LAYER Metal2 ; + RECT 259.4 0 259.66 0.26 ; + END + END A_DIN[14] + PIN A_BIST_DIN[17] + DIRECTION INPUT ; + USE SIGNAL ; + ANTENNAPARTIALMETALAREA 4.136375 LAYER Metal2 ; + ANTENNAMODEL OXIDE1 ; + ANTENNAGATEAREA 0.20085 LAYER Metal2 ; + ANTENNAMAXAREACAR 21.874907 LAYER Metal2 ; + PORT + LAYER Metal2 ; + RECT 443.68 0 443.94 0.26 ; + END + END A_BIST_DIN[17] + PIN A_BIST_DIN[14] + DIRECTION INPUT ; + USE SIGNAL ; + ANTENNAPARTIALMETALAREA 4.136375 LAYER Metal2 ; + ANTENNAMODEL OXIDE1 ; + ANTENNAGATEAREA 0.20085 LAYER Metal2 ; + ANTENNAMAXAREACAR 21.874907 LAYER Metal2 ; + PORT + LAYER Metal2 ; + RECT 258.89 0 259.15 0.26 ; + END + END A_BIST_DIN[14] + PIN A_BM[17] + DIRECTION INPUT ; + USE SIGNAL ; + ANTENNAPARTIALMETALAREA 1.7264 LAYER Metal2 ; + ANTENNAMODEL OXIDE1 ; + ANTENNAGATEAREA 0.20085 LAYER Metal2 ; + ANTENNAMAXAREACAR 9.501618 LAYER Metal2 ; + PORT + LAYER Metal2 ; + RECT 451.84 0 452.1 0.26 ; + END + END A_BM[17] + PIN A_BM[14] + DIRECTION INPUT ; + USE SIGNAL ; + ANTENNAPARTIALMETALAREA 1.7264 LAYER Metal2 ; + ANTENNAMODEL OXIDE1 ; + ANTENNAGATEAREA 0.20085 LAYER Metal2 ; + ANTENNAMAXAREACAR 9.501618 LAYER Metal2 ; + PORT + LAYER Metal2 ; + RECT 250.73 0 250.99 0.26 ; + END + END A_BM[14] + PIN A_BIST_BM[17] + DIRECTION INPUT ; + USE SIGNAL ; + ANTENNAPARTIALMETALAREA 1.7602 LAYER Metal2 ; + ANTENNAMODEL OXIDE1 ; + ANTENNAGATEAREA 0.20085 LAYER Metal2 ; + ANTENNAMAXAREACAR 9.678367 LAYER Metal2 ; + PORT + LAYER Metal2 ; + RECT 450.465 0 450.725 0.26 ; + END + END A_BIST_BM[17] + PIN A_BIST_BM[14] + DIRECTION INPUT ; + USE SIGNAL ; + ANTENNAPARTIALMETALAREA 1.7602 LAYER Metal2 ; + ANTENNAMODEL OXIDE1 ; + ANTENNAGATEAREA 0.20085 LAYER Metal2 ; + ANTENNAMAXAREACAR 9.678367 LAYER Metal2 ; + PORT + LAYER Metal2 ; + RECT 252.105 0 252.365 0.26 ; + END + END A_BIST_BM[14] + PIN A_DOUT[17] + DIRECTION OUTPUT ; + USE SIGNAL ; + ANTENNAPARTIALMETALAREA 4.8256 LAYER Metal2 ; + ANTENNADIFFAREA 0.988 LAYER Metal2 ; + PORT + LAYER Metal2 ; + RECT 436.03 0 436.29 0.26 ; + END + END A_DOUT[17] + PIN A_DOUT[14] + DIRECTION OUTPUT ; + USE SIGNAL ; + ANTENNAPARTIALMETALAREA 4.8256 LAYER Metal2 ; + ANTENNADIFFAREA 0.988 LAYER Metal2 ; + PORT + LAYER Metal2 ; + RECT 266.54 0 266.8 0.26 ; + END + END A_DOUT[14] + PIN B_DIN[17] + DIRECTION INPUT ; + USE SIGNAL ; + ANTENNAPARTIALMETALAREA 2.925 LAYER Metal2 ; + ANTENNAMODEL OXIDE1 ; + ANTENNAGATEAREA 0.20085 LAYER Metal2 ; + ANTENNAMAXAREACAR 15.469256 LAYER Metal2 ; + PORT + LAYER Metal2 ; + RECT 445.72 0 445.98 0.26 ; + END + END B_DIN[17] + PIN B_DIN[14] + DIRECTION INPUT ; + USE SIGNAL ; + ANTENNAPARTIALMETALAREA 2.925 LAYER Metal2 ; + ANTENNAMODEL OXIDE1 ; + ANTENNAGATEAREA 0.20085 LAYER Metal2 ; + ANTENNAMAXAREACAR 15.469256 LAYER Metal2 ; + PORT + LAYER Metal2 ; + RECT 256.85 0 257.11 0.26 ; + END + END B_DIN[14] + PIN B_BIST_DIN[17] + DIRECTION INPUT ; + USE SIGNAL ; + ANTENNAPARTIALMETALAREA 2.9445 LAYER Metal2 ; + ANTENNAMODEL OXIDE1 ; + ANTENNAGATEAREA 0.20085 LAYER Metal2 ; + ANTENNAMAXAREACAR 15.929052 LAYER Metal2 ; + PORT + LAYER Metal2 ; + RECT 444.19 0 444.45 0.26 ; + END + END B_BIST_DIN[17] + PIN B_BIST_DIN[14] + DIRECTION INPUT ; + USE SIGNAL ; + ANTENNAPARTIALMETALAREA 2.9445 LAYER Metal2 ; + ANTENNAMODEL OXIDE1 ; + ANTENNAGATEAREA 0.20085 LAYER Metal2 ; + ANTENNAMAXAREACAR 15.929052 LAYER Metal2 ; + PORT + LAYER Metal2 ; + RECT 258.38 0 258.64 0.26 ; + END + END B_BIST_DIN[14] + PIN B_BM[17] + DIRECTION INPUT ; + USE SIGNAL ; + ANTENNAPARTIALMETALAREA 0.7007 LAYER Metal2 ; + ANTENNAMODEL OXIDE1 ; + ANTENNAGATEAREA 0.20085 LAYER Metal2 ; + ANTENNAMAXAREACAR 4.394822 LAYER Metal2 ; + PORT + LAYER Metal2 ; + RECT 437.205 0 437.465 0.26 ; + END + END B_BM[17] + PIN B_BM[14] + DIRECTION INPUT ; + USE SIGNAL ; + ANTENNAPARTIALMETALAREA 0.7007 LAYER Metal2 ; + ANTENNAMODEL OXIDE1 ; + ANTENNAGATEAREA 0.20085 LAYER Metal2 ; + ANTENNAMAXAREACAR 4.394822 LAYER Metal2 ; + PORT + LAYER Metal2 ; + RECT 265.365 0 265.625 0.26 ; + END + END B_BM[14] + PIN B_BIST_BM[17] + DIRECTION INPUT ; + USE SIGNAL ; + ANTENNAPARTIALMETALAREA 0.7007 LAYER Metal2 ; + ANTENNAMODEL OXIDE1 ; + ANTENNAGATEAREA 0.20085 LAYER Metal2 ; + ANTENNAMAXAREACAR 4.394822 LAYER Metal2 ; + PORT + LAYER Metal2 ; + RECT 438.735 0 438.995 0.26 ; + END + END B_BIST_BM[17] + PIN B_BIST_BM[14] + DIRECTION INPUT ; + USE SIGNAL ; + ANTENNAPARTIALMETALAREA 0.7007 LAYER Metal2 ; + ANTENNAMODEL OXIDE1 ; + ANTENNAGATEAREA 0.20085 LAYER Metal2 ; + ANTENNAMAXAREACAR 4.394822 LAYER Metal2 ; + PORT + LAYER Metal2 ; + RECT 263.835 0 264.095 0.26 ; + END + END B_BIST_BM[14] + PIN B_DOUT[17] + DIRECTION OUTPUT ; + USE SIGNAL ; + ANTENNAPARTIALMETALAREA 4.836 LAYER Metal2 ; + ANTENNADIFFAREA 0.988 LAYER Metal2 ; + PORT + LAYER Metal2 ; + RECT 452.86 0 453.12 0.26 ; + END + END B_DOUT[17] + PIN B_DOUT[14] + DIRECTION OUTPUT ; + USE SIGNAL ; + ANTENNAPARTIALMETALAREA 4.836 LAYER Metal2 ; + ANTENNADIFFAREA 0.988 LAYER Metal2 ; + PORT + LAYER Metal2 ; + RECT 249.71 0 249.97 0.26 ; + END + END B_DOUT[14] + PIN A_DIN[18] + DIRECTION INPUT ; + USE SIGNAL ; + ANTENNAPARTIALMETALAREA 3.9091 LAYER Metal2 ; + ANTENNAMODEL OXIDE1 ; + ANTENNAGATEAREA 0.20085 LAYER Metal2 ; + ANTENNAMAXAREACAR 20.368932 LAYER Metal2 ; + PORT + LAYER Metal2 ; + RECT 460.85 0 461.11 0.26 ; + END + END A_DIN[18] + PIN A_DIN[13] + DIRECTION INPUT ; + USE SIGNAL ; + ANTENNAPARTIALMETALAREA 3.9091 LAYER Metal2 ; + ANTENNAMODEL OXIDE1 ; + ANTENNAGATEAREA 0.20085 LAYER Metal2 ; + ANTENNAMAXAREACAR 20.368932 LAYER Metal2 ; + PORT + LAYER Metal2 ; + RECT 241.72 0 241.98 0.26 ; + END + END A_DIN[13] + PIN A_BIST_DIN[18] + DIRECTION INPUT ; + USE SIGNAL ; + ANTENNAPARTIALMETALAREA 4.136375 LAYER Metal2 ; + ANTENNAMODEL OXIDE1 ; + ANTENNAGATEAREA 0.20085 LAYER Metal2 ; + ANTENNAMAXAREACAR 21.874907 LAYER Metal2 ; + PORT + LAYER Metal2 ; + RECT 461.36 0 461.62 0.26 ; + END + END A_BIST_DIN[18] + PIN A_BIST_DIN[13] + DIRECTION INPUT ; + USE SIGNAL ; + ANTENNAPARTIALMETALAREA 4.136375 LAYER Metal2 ; + ANTENNAMODEL OXIDE1 ; + ANTENNAGATEAREA 0.20085 LAYER Metal2 ; + ANTENNAMAXAREACAR 21.874907 LAYER Metal2 ; + PORT + LAYER Metal2 ; + RECT 241.21 0 241.47 0.26 ; + END + END A_BIST_DIN[13] + PIN A_BM[18] + DIRECTION INPUT ; + USE SIGNAL ; + ANTENNAPARTIALMETALAREA 1.7264 LAYER Metal2 ; + ANTENNAMODEL OXIDE1 ; + ANTENNAGATEAREA 0.20085 LAYER Metal2 ; + ANTENNAMAXAREACAR 9.501618 LAYER Metal2 ; + PORT + LAYER Metal2 ; + RECT 469.52 0 469.78 0.26 ; + END + END A_BM[18] + PIN A_BM[13] + DIRECTION INPUT ; + USE SIGNAL ; + ANTENNAPARTIALMETALAREA 1.7264 LAYER Metal2 ; + ANTENNAMODEL OXIDE1 ; + ANTENNAGATEAREA 0.20085 LAYER Metal2 ; + ANTENNAMAXAREACAR 9.501618 LAYER Metal2 ; + PORT + LAYER Metal2 ; + RECT 233.05 0 233.31 0.26 ; + END + END A_BM[13] + PIN A_BIST_BM[18] + DIRECTION INPUT ; + USE SIGNAL ; + ANTENNAPARTIALMETALAREA 1.7602 LAYER Metal2 ; + ANTENNAMODEL OXIDE1 ; + ANTENNAGATEAREA 0.20085 LAYER Metal2 ; + ANTENNAMAXAREACAR 9.678367 LAYER Metal2 ; + PORT + LAYER Metal2 ; + RECT 468.145 0 468.405 0.26 ; + END + END A_BIST_BM[18] + PIN A_BIST_BM[13] + DIRECTION INPUT ; + USE SIGNAL ; + ANTENNAPARTIALMETALAREA 1.7602 LAYER Metal2 ; + ANTENNAMODEL OXIDE1 ; + ANTENNAGATEAREA 0.20085 LAYER Metal2 ; + ANTENNAMAXAREACAR 9.678367 LAYER Metal2 ; + PORT + LAYER Metal2 ; + RECT 234.425 0 234.685 0.26 ; + END + END A_BIST_BM[13] + PIN A_DOUT[18] + DIRECTION OUTPUT ; + USE SIGNAL ; + ANTENNAPARTIALMETALAREA 4.8256 LAYER Metal2 ; + ANTENNADIFFAREA 0.988 LAYER Metal2 ; + PORT + LAYER Metal2 ; + RECT 453.71 0 453.97 0.26 ; + END + END A_DOUT[18] + PIN A_DOUT[13] + DIRECTION OUTPUT ; + USE SIGNAL ; + ANTENNAPARTIALMETALAREA 4.8256 LAYER Metal2 ; + ANTENNADIFFAREA 0.988 LAYER Metal2 ; + PORT + LAYER Metal2 ; + RECT 248.86 0 249.12 0.26 ; + END + END A_DOUT[13] + PIN B_DIN[18] + DIRECTION INPUT ; + USE SIGNAL ; + ANTENNAPARTIALMETALAREA 2.925 LAYER Metal2 ; + ANTENNAMODEL OXIDE1 ; + ANTENNAGATEAREA 0.20085 LAYER Metal2 ; + ANTENNAMAXAREACAR 15.469256 LAYER Metal2 ; + PORT + LAYER Metal2 ; + RECT 463.4 0 463.66 0.26 ; + END + END B_DIN[18] + PIN B_DIN[13] + DIRECTION INPUT ; + USE SIGNAL ; + ANTENNAPARTIALMETALAREA 2.925 LAYER Metal2 ; + ANTENNAMODEL OXIDE1 ; + ANTENNAGATEAREA 0.20085 LAYER Metal2 ; + ANTENNAMAXAREACAR 15.469256 LAYER Metal2 ; + PORT + LAYER Metal2 ; + RECT 239.17 0 239.43 0.26 ; + END + END B_DIN[13] + PIN B_BIST_DIN[18] + DIRECTION INPUT ; + USE SIGNAL ; + ANTENNAPARTIALMETALAREA 2.9445 LAYER Metal2 ; + ANTENNAMODEL OXIDE1 ; + ANTENNAGATEAREA 0.20085 LAYER Metal2 ; + ANTENNAMAXAREACAR 15.929052 LAYER Metal2 ; + PORT + LAYER Metal2 ; + RECT 461.87 0 462.13 0.26 ; + END + END B_BIST_DIN[18] + PIN B_BIST_DIN[13] + DIRECTION INPUT ; + USE SIGNAL ; + ANTENNAPARTIALMETALAREA 2.9445 LAYER Metal2 ; + ANTENNAMODEL OXIDE1 ; + ANTENNAGATEAREA 0.20085 LAYER Metal2 ; + ANTENNAMAXAREACAR 15.929052 LAYER Metal2 ; + PORT + LAYER Metal2 ; + RECT 240.7 0 240.96 0.26 ; + END + END B_BIST_DIN[13] + PIN B_BM[18] + DIRECTION INPUT ; + USE SIGNAL ; + ANTENNAPARTIALMETALAREA 0.7007 LAYER Metal2 ; + ANTENNAMODEL OXIDE1 ; + ANTENNAGATEAREA 0.20085 LAYER Metal2 ; + ANTENNAMAXAREACAR 4.394822 LAYER Metal2 ; + PORT + LAYER Metal2 ; + RECT 454.885 0 455.145 0.26 ; + END + END B_BM[18] + PIN B_BM[13] + DIRECTION INPUT ; + USE SIGNAL ; + ANTENNAPARTIALMETALAREA 0.7007 LAYER Metal2 ; + ANTENNAMODEL OXIDE1 ; + ANTENNAGATEAREA 0.20085 LAYER Metal2 ; + ANTENNAMAXAREACAR 4.394822 LAYER Metal2 ; + PORT + LAYER Metal2 ; + RECT 247.685 0 247.945 0.26 ; + END + END B_BM[13] + PIN B_BIST_BM[18] + DIRECTION INPUT ; + USE SIGNAL ; + ANTENNAPARTIALMETALAREA 0.7007 LAYER Metal2 ; + ANTENNAMODEL OXIDE1 ; + ANTENNAGATEAREA 0.20085 LAYER Metal2 ; + ANTENNAMAXAREACAR 4.394822 LAYER Metal2 ; + PORT + LAYER Metal2 ; + RECT 456.415 0 456.675 0.26 ; + END + END B_BIST_BM[18] + PIN B_BIST_BM[13] + DIRECTION INPUT ; + USE SIGNAL ; + ANTENNAPARTIALMETALAREA 0.7007 LAYER Metal2 ; + ANTENNAMODEL OXIDE1 ; + ANTENNAGATEAREA 0.20085 LAYER Metal2 ; + ANTENNAMAXAREACAR 4.394822 LAYER Metal2 ; + PORT + LAYER Metal2 ; + RECT 246.155 0 246.415 0.26 ; + END + END B_BIST_BM[13] + PIN B_DOUT[18] + DIRECTION OUTPUT ; + USE SIGNAL ; + ANTENNAPARTIALMETALAREA 4.836 LAYER Metal2 ; + ANTENNADIFFAREA 0.988 LAYER Metal2 ; + PORT + LAYER Metal2 ; + RECT 470.54 0 470.8 0.26 ; + END + END B_DOUT[18] + PIN B_DOUT[13] + DIRECTION OUTPUT ; + USE SIGNAL ; + ANTENNAPARTIALMETALAREA 4.836 LAYER Metal2 ; + ANTENNADIFFAREA 0.988 LAYER Metal2 ; + PORT + LAYER Metal2 ; + RECT 232.03 0 232.29 0.26 ; + END + END B_DOUT[13] + PIN A_DIN[19] + DIRECTION INPUT ; + USE SIGNAL ; + ANTENNAPARTIALMETALAREA 3.9091 LAYER Metal2 ; + ANTENNAMODEL OXIDE1 ; + ANTENNAGATEAREA 0.20085 LAYER Metal2 ; + ANTENNAMAXAREACAR 20.368932 LAYER Metal2 ; + PORT + LAYER Metal2 ; + RECT 478.53 0 478.79 0.26 ; + END + END A_DIN[19] + PIN A_DIN[12] + DIRECTION INPUT ; + USE SIGNAL ; + ANTENNAPARTIALMETALAREA 3.9091 LAYER Metal2 ; + ANTENNAMODEL OXIDE1 ; + ANTENNAGATEAREA 0.20085 LAYER Metal2 ; + ANTENNAMAXAREACAR 20.368932 LAYER Metal2 ; + PORT + LAYER Metal2 ; + RECT 224.04 0 224.3 0.26 ; + END + END A_DIN[12] + PIN A_BIST_DIN[19] + DIRECTION INPUT ; + USE SIGNAL ; + ANTENNAPARTIALMETALAREA 4.136375 LAYER Metal2 ; + ANTENNAMODEL OXIDE1 ; + ANTENNAGATEAREA 0.20085 LAYER Metal2 ; + ANTENNAMAXAREACAR 21.874907 LAYER Metal2 ; + PORT + LAYER Metal2 ; + RECT 479.04 0 479.3 0.26 ; + END + END A_BIST_DIN[19] + PIN A_BIST_DIN[12] + DIRECTION INPUT ; + USE SIGNAL ; + ANTENNAPARTIALMETALAREA 4.136375 LAYER Metal2 ; + ANTENNAMODEL OXIDE1 ; + ANTENNAGATEAREA 0.20085 LAYER Metal2 ; + ANTENNAMAXAREACAR 21.874907 LAYER Metal2 ; + PORT + LAYER Metal2 ; + RECT 223.53 0 223.79 0.26 ; + END + END A_BIST_DIN[12] + PIN A_BM[19] + DIRECTION INPUT ; + USE SIGNAL ; + ANTENNAPARTIALMETALAREA 1.7264 LAYER Metal2 ; + ANTENNAMODEL OXIDE1 ; + ANTENNAGATEAREA 0.20085 LAYER Metal2 ; + ANTENNAMAXAREACAR 9.501618 LAYER Metal2 ; + PORT + LAYER Metal2 ; + RECT 487.2 0 487.46 0.26 ; + END + END A_BM[19] + PIN A_BM[12] + DIRECTION INPUT ; + USE SIGNAL ; + ANTENNAPARTIALMETALAREA 1.7264 LAYER Metal2 ; + ANTENNAMODEL OXIDE1 ; + ANTENNAGATEAREA 0.20085 LAYER Metal2 ; + ANTENNAMAXAREACAR 9.501618 LAYER Metal2 ; + PORT + LAYER Metal2 ; + RECT 215.37 0 215.63 0.26 ; + END + END A_BM[12] + PIN A_BIST_BM[19] + DIRECTION INPUT ; + USE SIGNAL ; + ANTENNAPARTIALMETALAREA 1.7602 LAYER Metal2 ; + ANTENNAMODEL OXIDE1 ; + ANTENNAGATEAREA 0.20085 LAYER Metal2 ; + ANTENNAMAXAREACAR 9.678367 LAYER Metal2 ; + PORT + LAYER Metal2 ; + RECT 485.825 0 486.085 0.26 ; + END + END A_BIST_BM[19] + PIN A_BIST_BM[12] + DIRECTION INPUT ; + USE SIGNAL ; + ANTENNAPARTIALMETALAREA 1.7602 LAYER Metal2 ; + ANTENNAMODEL OXIDE1 ; + ANTENNAGATEAREA 0.20085 LAYER Metal2 ; + ANTENNAMAXAREACAR 9.678367 LAYER Metal2 ; + PORT + LAYER Metal2 ; + RECT 216.745 0 217.005 0.26 ; + END + END A_BIST_BM[12] + PIN A_DOUT[19] + DIRECTION OUTPUT ; + USE SIGNAL ; + ANTENNAPARTIALMETALAREA 4.8256 LAYER Metal2 ; + ANTENNADIFFAREA 0.988 LAYER Metal2 ; + PORT + LAYER Metal2 ; + RECT 471.39 0 471.65 0.26 ; + END + END A_DOUT[19] + PIN A_DOUT[12] + DIRECTION OUTPUT ; + USE SIGNAL ; + ANTENNAPARTIALMETALAREA 4.8256 LAYER Metal2 ; + ANTENNADIFFAREA 0.988 LAYER Metal2 ; + PORT + LAYER Metal2 ; + RECT 231.18 0 231.44 0.26 ; + END + END A_DOUT[12] + PIN B_DIN[19] + DIRECTION INPUT ; + USE SIGNAL ; + ANTENNAPARTIALMETALAREA 2.925 LAYER Metal2 ; + ANTENNAMODEL OXIDE1 ; + ANTENNAGATEAREA 0.20085 LAYER Metal2 ; + ANTENNAMAXAREACAR 15.469256 LAYER Metal2 ; + PORT + LAYER Metal2 ; + RECT 481.08 0 481.34 0.26 ; + END + END B_DIN[19] + PIN B_DIN[12] + DIRECTION INPUT ; + USE SIGNAL ; + ANTENNAPARTIALMETALAREA 2.925 LAYER Metal2 ; + ANTENNAMODEL OXIDE1 ; + ANTENNAGATEAREA 0.20085 LAYER Metal2 ; + ANTENNAMAXAREACAR 15.469256 LAYER Metal2 ; + PORT + LAYER Metal2 ; + RECT 221.49 0 221.75 0.26 ; + END + END B_DIN[12] + PIN B_BIST_DIN[19] + DIRECTION INPUT ; + USE SIGNAL ; + ANTENNAPARTIALMETALAREA 2.9445 LAYER Metal2 ; + ANTENNAMODEL OXIDE1 ; + ANTENNAGATEAREA 0.20085 LAYER Metal2 ; + ANTENNAMAXAREACAR 15.929052 LAYER Metal2 ; + PORT + LAYER Metal2 ; + RECT 479.55 0 479.81 0.26 ; + END + END B_BIST_DIN[19] + PIN B_BIST_DIN[12] + DIRECTION INPUT ; + USE SIGNAL ; + ANTENNAPARTIALMETALAREA 2.9445 LAYER Metal2 ; + ANTENNAMODEL OXIDE1 ; + ANTENNAGATEAREA 0.20085 LAYER Metal2 ; + ANTENNAMAXAREACAR 15.929052 LAYER Metal2 ; + PORT + LAYER Metal2 ; + RECT 223.02 0 223.28 0.26 ; + END + END B_BIST_DIN[12] + PIN B_BM[19] + DIRECTION INPUT ; + USE SIGNAL ; + ANTENNAPARTIALMETALAREA 0.7007 LAYER Metal2 ; + ANTENNAMODEL OXIDE1 ; + ANTENNAGATEAREA 0.20085 LAYER Metal2 ; + ANTENNAMAXAREACAR 4.394822 LAYER Metal2 ; + PORT + LAYER Metal2 ; + RECT 472.565 0 472.825 0.26 ; + END + END B_BM[19] + PIN B_BM[12] + DIRECTION INPUT ; + USE SIGNAL ; + ANTENNAPARTIALMETALAREA 0.7007 LAYER Metal2 ; + ANTENNAMODEL OXIDE1 ; + ANTENNAGATEAREA 0.20085 LAYER Metal2 ; + ANTENNAMAXAREACAR 4.394822 LAYER Metal2 ; + PORT + LAYER Metal2 ; + RECT 230.005 0 230.265 0.26 ; + END + END B_BM[12] + PIN B_BIST_BM[19] + DIRECTION INPUT ; + USE SIGNAL ; + ANTENNAPARTIALMETALAREA 0.7007 LAYER Metal2 ; + ANTENNAMODEL OXIDE1 ; + ANTENNAGATEAREA 0.20085 LAYER Metal2 ; + ANTENNAMAXAREACAR 4.394822 LAYER Metal2 ; + PORT + LAYER Metal2 ; + RECT 474.095 0 474.355 0.26 ; + END + END B_BIST_BM[19] + PIN B_BIST_BM[12] + DIRECTION INPUT ; + USE SIGNAL ; + ANTENNAPARTIALMETALAREA 0.7007 LAYER Metal2 ; + ANTENNAMODEL OXIDE1 ; + ANTENNAGATEAREA 0.20085 LAYER Metal2 ; + ANTENNAMAXAREACAR 4.394822 LAYER Metal2 ; + PORT + LAYER Metal2 ; + RECT 228.475 0 228.735 0.26 ; + END + END B_BIST_BM[12] + PIN B_DOUT[19] + DIRECTION OUTPUT ; + USE SIGNAL ; + ANTENNAPARTIALMETALAREA 4.836 LAYER Metal2 ; + ANTENNADIFFAREA 0.988 LAYER Metal2 ; + PORT + LAYER Metal2 ; + RECT 488.22 0 488.48 0.26 ; + END + END B_DOUT[19] + PIN B_DOUT[12] + DIRECTION OUTPUT ; + USE SIGNAL ; + ANTENNAPARTIALMETALAREA 4.836 LAYER Metal2 ; + ANTENNADIFFAREA 0.988 LAYER Metal2 ; + PORT + LAYER Metal2 ; + RECT 214.35 0 214.61 0.26 ; + END + END B_DOUT[12] + PIN A_DIN[20] + DIRECTION INPUT ; + USE SIGNAL ; + ANTENNAPARTIALMETALAREA 3.9091 LAYER Metal2 ; + ANTENNAMODEL OXIDE1 ; + ANTENNAGATEAREA 0.20085 LAYER Metal2 ; + ANTENNAMAXAREACAR 20.368932 LAYER Metal2 ; + PORT + LAYER Metal2 ; + RECT 496.21 0 496.47 0.26 ; + END + END A_DIN[20] + PIN A_DIN[11] + DIRECTION INPUT ; + USE SIGNAL ; + ANTENNAPARTIALMETALAREA 3.9091 LAYER Metal2 ; + ANTENNAMODEL OXIDE1 ; + ANTENNAGATEAREA 0.20085 LAYER Metal2 ; + ANTENNAMAXAREACAR 20.368932 LAYER Metal2 ; + PORT + LAYER Metal2 ; + RECT 206.36 0 206.62 0.26 ; + END + END A_DIN[11] + PIN A_BIST_DIN[20] + DIRECTION INPUT ; + USE SIGNAL ; + ANTENNAPARTIALMETALAREA 4.136375 LAYER Metal2 ; + ANTENNAMODEL OXIDE1 ; + ANTENNAGATEAREA 0.20085 LAYER Metal2 ; + ANTENNAMAXAREACAR 21.874907 LAYER Metal2 ; + PORT + LAYER Metal2 ; + RECT 496.72 0 496.98 0.26 ; + END + END A_BIST_DIN[20] + PIN A_BIST_DIN[11] + DIRECTION INPUT ; + USE SIGNAL ; + ANTENNAPARTIALMETALAREA 4.136375 LAYER Metal2 ; + ANTENNAMODEL OXIDE1 ; + ANTENNAGATEAREA 0.20085 LAYER Metal2 ; + ANTENNAMAXAREACAR 21.874907 LAYER Metal2 ; + PORT + LAYER Metal2 ; + RECT 205.85 0 206.11 0.26 ; + END + END A_BIST_DIN[11] + PIN A_BM[20] + DIRECTION INPUT ; + USE SIGNAL ; + ANTENNAPARTIALMETALAREA 1.7264 LAYER Metal2 ; + ANTENNAMODEL OXIDE1 ; + ANTENNAGATEAREA 0.20085 LAYER Metal2 ; + ANTENNAMAXAREACAR 9.501618 LAYER Metal2 ; + PORT + LAYER Metal2 ; + RECT 504.88 0 505.14 0.26 ; + END + END A_BM[20] + PIN A_BM[11] + DIRECTION INPUT ; + USE SIGNAL ; + ANTENNAPARTIALMETALAREA 1.7264 LAYER Metal2 ; + ANTENNAMODEL OXIDE1 ; + ANTENNAGATEAREA 0.20085 LAYER Metal2 ; + ANTENNAMAXAREACAR 9.501618 LAYER Metal2 ; + PORT + LAYER Metal2 ; + RECT 197.69 0 197.95 0.26 ; + END + END A_BM[11] + PIN A_BIST_BM[20] + DIRECTION INPUT ; + USE SIGNAL ; + ANTENNAPARTIALMETALAREA 1.7602 LAYER Metal2 ; + ANTENNAMODEL OXIDE1 ; + ANTENNAGATEAREA 0.20085 LAYER Metal2 ; + ANTENNAMAXAREACAR 9.678367 LAYER Metal2 ; + PORT + LAYER Metal2 ; + RECT 503.505 0 503.765 0.26 ; + END + END A_BIST_BM[20] + PIN A_BIST_BM[11] + DIRECTION INPUT ; + USE SIGNAL ; + ANTENNAPARTIALMETALAREA 1.7602 LAYER Metal2 ; + ANTENNAMODEL OXIDE1 ; + ANTENNAGATEAREA 0.20085 LAYER Metal2 ; + ANTENNAMAXAREACAR 9.678367 LAYER Metal2 ; + PORT + LAYER Metal2 ; + RECT 199.065 0 199.325 0.26 ; + END + END A_BIST_BM[11] + PIN A_DOUT[20] + DIRECTION OUTPUT ; + USE SIGNAL ; + ANTENNAPARTIALMETALAREA 4.8256 LAYER Metal2 ; + ANTENNADIFFAREA 0.988 LAYER Metal2 ; + PORT + LAYER Metal2 ; + RECT 489.07 0 489.33 0.26 ; + END + END A_DOUT[20] + PIN A_DOUT[11] + DIRECTION OUTPUT ; + USE SIGNAL ; + ANTENNAPARTIALMETALAREA 4.8256 LAYER Metal2 ; + ANTENNADIFFAREA 0.988 LAYER Metal2 ; + PORT + LAYER Metal2 ; + RECT 213.5 0 213.76 0.26 ; + END + END A_DOUT[11] + PIN B_DIN[20] + DIRECTION INPUT ; + USE SIGNAL ; + ANTENNAPARTIALMETALAREA 2.925 LAYER Metal2 ; + ANTENNAMODEL OXIDE1 ; + ANTENNAGATEAREA 0.20085 LAYER Metal2 ; + ANTENNAMAXAREACAR 15.469256 LAYER Metal2 ; + PORT + LAYER Metal2 ; + RECT 498.76 0 499.02 0.26 ; + END + END B_DIN[20] + PIN B_DIN[11] + DIRECTION INPUT ; + USE SIGNAL ; + ANTENNAPARTIALMETALAREA 2.925 LAYER Metal2 ; + ANTENNAMODEL OXIDE1 ; + ANTENNAGATEAREA 0.20085 LAYER Metal2 ; + ANTENNAMAXAREACAR 15.469256 LAYER Metal2 ; + PORT + LAYER Metal2 ; + RECT 203.81 0 204.07 0.26 ; + END + END B_DIN[11] + PIN B_BIST_DIN[20] + DIRECTION INPUT ; + USE SIGNAL ; + ANTENNAPARTIALMETALAREA 2.9445 LAYER Metal2 ; + ANTENNAMODEL OXIDE1 ; + ANTENNAGATEAREA 0.20085 LAYER Metal2 ; + ANTENNAMAXAREACAR 15.929052 LAYER Metal2 ; + PORT + LAYER Metal2 ; + RECT 497.23 0 497.49 0.26 ; + END + END B_BIST_DIN[20] + PIN B_BIST_DIN[11] + DIRECTION INPUT ; + USE SIGNAL ; + ANTENNAPARTIALMETALAREA 2.9445 LAYER Metal2 ; + ANTENNAMODEL OXIDE1 ; + ANTENNAGATEAREA 0.20085 LAYER Metal2 ; + ANTENNAMAXAREACAR 15.929052 LAYER Metal2 ; + PORT + LAYER Metal2 ; + RECT 205.34 0 205.6 0.26 ; + END + END B_BIST_DIN[11] + PIN B_BM[20] + DIRECTION INPUT ; + USE SIGNAL ; + ANTENNAPARTIALMETALAREA 0.7007 LAYER Metal2 ; + ANTENNAMODEL OXIDE1 ; + ANTENNAGATEAREA 0.20085 LAYER Metal2 ; + ANTENNAMAXAREACAR 4.394822 LAYER Metal2 ; + PORT + LAYER Metal2 ; + RECT 490.245 0 490.505 0.26 ; + END + END B_BM[20] + PIN B_BM[11] + DIRECTION INPUT ; + USE SIGNAL ; + ANTENNAPARTIALMETALAREA 0.7007 LAYER Metal2 ; + ANTENNAMODEL OXIDE1 ; + ANTENNAGATEAREA 0.20085 LAYER Metal2 ; + ANTENNAMAXAREACAR 4.394822 LAYER Metal2 ; + PORT + LAYER Metal2 ; + RECT 212.325 0 212.585 0.26 ; + END + END B_BM[11] + PIN B_BIST_BM[20] + DIRECTION INPUT ; + USE SIGNAL ; + ANTENNAPARTIALMETALAREA 0.7007 LAYER Metal2 ; + ANTENNAMODEL OXIDE1 ; + ANTENNAGATEAREA 0.20085 LAYER Metal2 ; + ANTENNAMAXAREACAR 4.394822 LAYER Metal2 ; + PORT + LAYER Metal2 ; + RECT 491.775 0 492.035 0.26 ; + END + END B_BIST_BM[20] + PIN B_BIST_BM[11] + DIRECTION INPUT ; + USE SIGNAL ; + ANTENNAPARTIALMETALAREA 0.7007 LAYER Metal2 ; + ANTENNAMODEL OXIDE1 ; + ANTENNAGATEAREA 0.20085 LAYER Metal2 ; + ANTENNAMAXAREACAR 4.394822 LAYER Metal2 ; + PORT + LAYER Metal2 ; + RECT 210.795 0 211.055 0.26 ; + END + END B_BIST_BM[11] + PIN B_DOUT[20] + DIRECTION OUTPUT ; + USE SIGNAL ; + ANTENNAPARTIALMETALAREA 4.836 LAYER Metal2 ; + ANTENNADIFFAREA 0.988 LAYER Metal2 ; + PORT + LAYER Metal2 ; + RECT 505.9 0 506.16 0.26 ; + END + END B_DOUT[20] + PIN B_DOUT[11] + DIRECTION OUTPUT ; + USE SIGNAL ; + ANTENNAPARTIALMETALAREA 4.836 LAYER Metal2 ; + ANTENNADIFFAREA 0.988 LAYER Metal2 ; + PORT + LAYER Metal2 ; + RECT 196.67 0 196.93 0.26 ; + END + END B_DOUT[11] + PIN A_DIN[21] + DIRECTION INPUT ; + USE SIGNAL ; + ANTENNAPARTIALMETALAREA 3.9091 LAYER Metal2 ; + ANTENNAMODEL OXIDE1 ; + ANTENNAGATEAREA 0.20085 LAYER Metal2 ; + ANTENNAMAXAREACAR 20.368932 LAYER Metal2 ; + PORT + LAYER Metal2 ; + RECT 513.89 0 514.15 0.26 ; + END + END A_DIN[21] + PIN A_DIN[10] + DIRECTION INPUT ; + USE SIGNAL ; + ANTENNAPARTIALMETALAREA 3.9091 LAYER Metal2 ; + ANTENNAMODEL OXIDE1 ; + ANTENNAGATEAREA 0.20085 LAYER Metal2 ; + ANTENNAMAXAREACAR 20.368932 LAYER Metal2 ; + PORT + LAYER Metal2 ; + RECT 188.68 0 188.94 0.26 ; + END + END A_DIN[10] + PIN A_BIST_DIN[21] + DIRECTION INPUT ; + USE SIGNAL ; + ANTENNAPARTIALMETALAREA 4.136375 LAYER Metal2 ; + ANTENNAMODEL OXIDE1 ; + ANTENNAGATEAREA 0.20085 LAYER Metal2 ; + ANTENNAMAXAREACAR 21.874907 LAYER Metal2 ; + PORT + LAYER Metal2 ; + RECT 514.4 0 514.66 0.26 ; + END + END A_BIST_DIN[21] + PIN A_BIST_DIN[10] + DIRECTION INPUT ; + USE SIGNAL ; + ANTENNAPARTIALMETALAREA 4.136375 LAYER Metal2 ; + ANTENNAMODEL OXIDE1 ; + ANTENNAGATEAREA 0.20085 LAYER Metal2 ; + ANTENNAMAXAREACAR 21.874907 LAYER Metal2 ; + PORT + LAYER Metal2 ; + RECT 188.17 0 188.43 0.26 ; + END + END A_BIST_DIN[10] + PIN A_BM[21] + DIRECTION INPUT ; + USE SIGNAL ; + ANTENNAPARTIALMETALAREA 1.7264 LAYER Metal2 ; + ANTENNAMODEL OXIDE1 ; + ANTENNAGATEAREA 0.20085 LAYER Metal2 ; + ANTENNAMAXAREACAR 9.501618 LAYER Metal2 ; + PORT + LAYER Metal2 ; + RECT 522.56 0 522.82 0.26 ; + END + END A_BM[21] + PIN A_BM[10] + DIRECTION INPUT ; + USE SIGNAL ; + ANTENNAPARTIALMETALAREA 1.7264 LAYER Metal2 ; + ANTENNAMODEL OXIDE1 ; + ANTENNAGATEAREA 0.20085 LAYER Metal2 ; + ANTENNAMAXAREACAR 9.501618 LAYER Metal2 ; + PORT + LAYER Metal2 ; + RECT 180.01 0 180.27 0.26 ; + END + END A_BM[10] + PIN A_BIST_BM[21] + DIRECTION INPUT ; + USE SIGNAL ; + ANTENNAPARTIALMETALAREA 1.7602 LAYER Metal2 ; + ANTENNAMODEL OXIDE1 ; + ANTENNAGATEAREA 0.20085 LAYER Metal2 ; + ANTENNAMAXAREACAR 9.678367 LAYER Metal2 ; + PORT + LAYER Metal2 ; + RECT 521.185 0 521.445 0.26 ; + END + END A_BIST_BM[21] + PIN A_BIST_BM[10] + DIRECTION INPUT ; + USE SIGNAL ; + ANTENNAPARTIALMETALAREA 1.7602 LAYER Metal2 ; + ANTENNAMODEL OXIDE1 ; + ANTENNAGATEAREA 0.20085 LAYER Metal2 ; + ANTENNAMAXAREACAR 9.678367 LAYER Metal2 ; + PORT + LAYER Metal2 ; + RECT 181.385 0 181.645 0.26 ; + END + END A_BIST_BM[10] + PIN A_DOUT[21] + DIRECTION OUTPUT ; + USE SIGNAL ; + ANTENNAPARTIALMETALAREA 4.8256 LAYER Metal2 ; + ANTENNADIFFAREA 0.988 LAYER Metal2 ; + PORT + LAYER Metal2 ; + RECT 506.75 0 507.01 0.26 ; + END + END A_DOUT[21] + PIN A_DOUT[10] + DIRECTION OUTPUT ; + USE SIGNAL ; + ANTENNAPARTIALMETALAREA 4.8256 LAYER Metal2 ; + ANTENNADIFFAREA 0.988 LAYER Metal2 ; + PORT + LAYER Metal2 ; + RECT 195.82 0 196.08 0.26 ; + END + END A_DOUT[10] + PIN B_DIN[21] + DIRECTION INPUT ; + USE SIGNAL ; + ANTENNAPARTIALMETALAREA 2.925 LAYER Metal2 ; + ANTENNAMODEL OXIDE1 ; + ANTENNAGATEAREA 0.20085 LAYER Metal2 ; + ANTENNAMAXAREACAR 15.469256 LAYER Metal2 ; + PORT + LAYER Metal2 ; + RECT 516.44 0 516.7 0.26 ; + END + END B_DIN[21] + PIN B_DIN[10] + DIRECTION INPUT ; + USE SIGNAL ; + ANTENNAPARTIALMETALAREA 2.925 LAYER Metal2 ; + ANTENNAMODEL OXIDE1 ; + ANTENNAGATEAREA 0.20085 LAYER Metal2 ; + ANTENNAMAXAREACAR 15.469256 LAYER Metal2 ; + PORT + LAYER Metal2 ; + RECT 186.13 0 186.39 0.26 ; + END + END B_DIN[10] + PIN B_BIST_DIN[21] + DIRECTION INPUT ; + USE SIGNAL ; + ANTENNAPARTIALMETALAREA 2.9445 LAYER Metal2 ; + ANTENNAMODEL OXIDE1 ; + ANTENNAGATEAREA 0.20085 LAYER Metal2 ; + ANTENNAMAXAREACAR 15.929052 LAYER Metal2 ; + PORT + LAYER Metal2 ; + RECT 514.91 0 515.17 0.26 ; + END + END B_BIST_DIN[21] + PIN B_BIST_DIN[10] + DIRECTION INPUT ; + USE SIGNAL ; + ANTENNAPARTIALMETALAREA 2.9445 LAYER Metal2 ; + ANTENNAMODEL OXIDE1 ; + ANTENNAGATEAREA 0.20085 LAYER Metal2 ; + ANTENNAMAXAREACAR 15.929052 LAYER Metal2 ; + PORT + LAYER Metal2 ; + RECT 187.66 0 187.92 0.26 ; + END + END B_BIST_DIN[10] + PIN B_BM[21] + DIRECTION INPUT ; + USE SIGNAL ; + ANTENNAPARTIALMETALAREA 0.7007 LAYER Metal2 ; + ANTENNAMODEL OXIDE1 ; + ANTENNAGATEAREA 0.20085 LAYER Metal2 ; + ANTENNAMAXAREACAR 4.394822 LAYER Metal2 ; + PORT + LAYER Metal2 ; + RECT 507.925 0 508.185 0.26 ; + END + END B_BM[21] + PIN B_BM[10] + DIRECTION INPUT ; + USE SIGNAL ; + ANTENNAPARTIALMETALAREA 0.7007 LAYER Metal2 ; + ANTENNAMODEL OXIDE1 ; + ANTENNAGATEAREA 0.20085 LAYER Metal2 ; + ANTENNAMAXAREACAR 4.394822 LAYER Metal2 ; + PORT + LAYER Metal2 ; + RECT 194.645 0 194.905 0.26 ; + END + END B_BM[10] + PIN B_BIST_BM[21] + DIRECTION INPUT ; + USE SIGNAL ; + ANTENNAPARTIALMETALAREA 0.7007 LAYER Metal2 ; + ANTENNAMODEL OXIDE1 ; + ANTENNAGATEAREA 0.20085 LAYER Metal2 ; + ANTENNAMAXAREACAR 4.394822 LAYER Metal2 ; + PORT + LAYER Metal2 ; + RECT 509.455 0 509.715 0.26 ; + END + END B_BIST_BM[21] + PIN B_BIST_BM[10] + DIRECTION INPUT ; + USE SIGNAL ; + ANTENNAPARTIALMETALAREA 0.7007 LAYER Metal2 ; + ANTENNAMODEL OXIDE1 ; + ANTENNAGATEAREA 0.20085 LAYER Metal2 ; + ANTENNAMAXAREACAR 4.394822 LAYER Metal2 ; + PORT + LAYER Metal2 ; + RECT 193.115 0 193.375 0.26 ; + END + END B_BIST_BM[10] + PIN B_DOUT[21] + DIRECTION OUTPUT ; + USE SIGNAL ; + ANTENNAPARTIALMETALAREA 4.836 LAYER Metal2 ; + ANTENNADIFFAREA 0.988 LAYER Metal2 ; + PORT + LAYER Metal2 ; + RECT 523.58 0 523.84 0.26 ; + END + END B_DOUT[21] + PIN B_DOUT[10] + DIRECTION OUTPUT ; + USE SIGNAL ; + ANTENNAPARTIALMETALAREA 4.836 LAYER Metal2 ; + ANTENNADIFFAREA 0.988 LAYER Metal2 ; + PORT + LAYER Metal2 ; + RECT 178.99 0 179.25 0.26 ; + END + END B_DOUT[10] + PIN A_DIN[22] + DIRECTION INPUT ; + USE SIGNAL ; + ANTENNAPARTIALMETALAREA 3.9091 LAYER Metal2 ; + ANTENNAMODEL OXIDE1 ; + ANTENNAGATEAREA 0.20085 LAYER Metal2 ; + ANTENNAMAXAREACAR 20.368932 LAYER Metal2 ; + PORT + LAYER Metal2 ; + RECT 531.57 0 531.83 0.26 ; + END + END A_DIN[22] + PIN A_DIN[9] + DIRECTION INPUT ; + USE SIGNAL ; + ANTENNAPARTIALMETALAREA 3.9091 LAYER Metal2 ; + ANTENNAMODEL OXIDE1 ; + ANTENNAGATEAREA 0.20085 LAYER Metal2 ; + ANTENNAMAXAREACAR 20.368932 LAYER Metal2 ; + PORT + LAYER Metal2 ; + RECT 171 0 171.26 0.26 ; + END + END A_DIN[9] + PIN A_BIST_DIN[22] + DIRECTION INPUT ; + USE SIGNAL ; + ANTENNAPARTIALMETALAREA 4.136375 LAYER Metal2 ; + ANTENNAMODEL OXIDE1 ; + ANTENNAGATEAREA 0.20085 LAYER Metal2 ; + ANTENNAMAXAREACAR 21.874907 LAYER Metal2 ; + PORT + LAYER Metal2 ; + RECT 532.08 0 532.34 0.26 ; + END + END A_BIST_DIN[22] + PIN A_BIST_DIN[9] + DIRECTION INPUT ; + USE SIGNAL ; + ANTENNAPARTIALMETALAREA 4.136375 LAYER Metal2 ; + ANTENNAMODEL OXIDE1 ; + ANTENNAGATEAREA 0.20085 LAYER Metal2 ; + ANTENNAMAXAREACAR 21.874907 LAYER Metal2 ; + PORT + LAYER Metal2 ; + RECT 170.49 0 170.75 0.26 ; + END + END A_BIST_DIN[9] + PIN A_BM[22] + DIRECTION INPUT ; + USE SIGNAL ; + ANTENNAPARTIALMETALAREA 1.7264 LAYER Metal2 ; + ANTENNAMODEL OXIDE1 ; + ANTENNAGATEAREA 0.20085 LAYER Metal2 ; + ANTENNAMAXAREACAR 9.501618 LAYER Metal2 ; + PORT + LAYER Metal2 ; + RECT 540.24 0 540.5 0.26 ; + END + END A_BM[22] + PIN A_BM[9] + DIRECTION INPUT ; + USE SIGNAL ; + ANTENNAPARTIALMETALAREA 1.7264 LAYER Metal2 ; + ANTENNAMODEL OXIDE1 ; + ANTENNAGATEAREA 0.20085 LAYER Metal2 ; + ANTENNAMAXAREACAR 9.501618 LAYER Metal2 ; + PORT + LAYER Metal2 ; + RECT 162.33 0 162.59 0.26 ; + END + END A_BM[9] + PIN A_BIST_BM[22] + DIRECTION INPUT ; + USE SIGNAL ; + ANTENNAPARTIALMETALAREA 1.7602 LAYER Metal2 ; + ANTENNAMODEL OXIDE1 ; + ANTENNAGATEAREA 0.20085 LAYER Metal2 ; + ANTENNAMAXAREACAR 9.678367 LAYER Metal2 ; + PORT + LAYER Metal2 ; + RECT 538.865 0 539.125 0.26 ; + END + END A_BIST_BM[22] + PIN A_BIST_BM[9] + DIRECTION INPUT ; + USE SIGNAL ; + ANTENNAPARTIALMETALAREA 1.7602 LAYER Metal2 ; + ANTENNAMODEL OXIDE1 ; + ANTENNAGATEAREA 0.20085 LAYER Metal2 ; + ANTENNAMAXAREACAR 9.678367 LAYER Metal2 ; + PORT + LAYER Metal2 ; + RECT 163.705 0 163.965 0.26 ; + END + END A_BIST_BM[9] + PIN A_DOUT[22] + DIRECTION OUTPUT ; + USE SIGNAL ; + ANTENNAPARTIALMETALAREA 4.8256 LAYER Metal2 ; + ANTENNADIFFAREA 0.988 LAYER Metal2 ; + PORT + LAYER Metal2 ; + RECT 524.43 0 524.69 0.26 ; + END + END A_DOUT[22] + PIN A_DOUT[9] + DIRECTION OUTPUT ; + USE SIGNAL ; + ANTENNAPARTIALMETALAREA 4.8256 LAYER Metal2 ; + ANTENNADIFFAREA 0.988 LAYER Metal2 ; + PORT + LAYER Metal2 ; + RECT 178.14 0 178.4 0.26 ; + END + END A_DOUT[9] + PIN B_DIN[22] + DIRECTION INPUT ; + USE SIGNAL ; + ANTENNAPARTIALMETALAREA 2.925 LAYER Metal2 ; + ANTENNAMODEL OXIDE1 ; + ANTENNAGATEAREA 0.20085 LAYER Metal2 ; + ANTENNAMAXAREACAR 15.469256 LAYER Metal2 ; + PORT + LAYER Metal2 ; + RECT 534.12 0 534.38 0.26 ; + END + END B_DIN[22] + PIN B_DIN[9] + DIRECTION INPUT ; + USE SIGNAL ; + ANTENNAPARTIALMETALAREA 2.925 LAYER Metal2 ; + ANTENNAMODEL OXIDE1 ; + ANTENNAGATEAREA 0.20085 LAYER Metal2 ; + ANTENNAMAXAREACAR 15.469256 LAYER Metal2 ; + PORT + LAYER Metal2 ; + RECT 168.45 0 168.71 0.26 ; + END + END B_DIN[9] + PIN B_BIST_DIN[22] + DIRECTION INPUT ; + USE SIGNAL ; + ANTENNAPARTIALMETALAREA 2.9445 LAYER Metal2 ; + ANTENNAMODEL OXIDE1 ; + ANTENNAGATEAREA 0.20085 LAYER Metal2 ; + ANTENNAMAXAREACAR 15.929052 LAYER Metal2 ; + PORT + LAYER Metal2 ; + RECT 532.59 0 532.85 0.26 ; + END + END B_BIST_DIN[22] + PIN B_BIST_DIN[9] + DIRECTION INPUT ; + USE SIGNAL ; + ANTENNAPARTIALMETALAREA 2.9445 LAYER Metal2 ; + ANTENNAMODEL OXIDE1 ; + ANTENNAGATEAREA 0.20085 LAYER Metal2 ; + ANTENNAMAXAREACAR 15.929052 LAYER Metal2 ; + PORT + LAYER Metal2 ; + RECT 169.98 0 170.24 0.26 ; + END + END B_BIST_DIN[9] + PIN B_BM[22] + DIRECTION INPUT ; + USE SIGNAL ; + ANTENNAPARTIALMETALAREA 0.7007 LAYER Metal2 ; + ANTENNAMODEL OXIDE1 ; + ANTENNAGATEAREA 0.20085 LAYER Metal2 ; + ANTENNAMAXAREACAR 4.394822 LAYER Metal2 ; + PORT + LAYER Metal2 ; + RECT 525.605 0 525.865 0.26 ; + END + END B_BM[22] + PIN B_BM[9] + DIRECTION INPUT ; + USE SIGNAL ; + ANTENNAPARTIALMETALAREA 0.7007 LAYER Metal2 ; + ANTENNAMODEL OXIDE1 ; + ANTENNAGATEAREA 0.20085 LAYER Metal2 ; + ANTENNAMAXAREACAR 4.394822 LAYER Metal2 ; + PORT + LAYER Metal2 ; + RECT 176.965 0 177.225 0.26 ; + END + END B_BM[9] + PIN B_BIST_BM[22] + DIRECTION INPUT ; + USE SIGNAL ; + ANTENNAPARTIALMETALAREA 0.7007 LAYER Metal2 ; + ANTENNAMODEL OXIDE1 ; + ANTENNAGATEAREA 0.20085 LAYER Metal2 ; + ANTENNAMAXAREACAR 4.394822 LAYER Metal2 ; + PORT + LAYER Metal2 ; + RECT 527.135 0 527.395 0.26 ; + END + END B_BIST_BM[22] + PIN B_BIST_BM[9] + DIRECTION INPUT ; + USE SIGNAL ; + ANTENNAPARTIALMETALAREA 0.7007 LAYER Metal2 ; + ANTENNAMODEL OXIDE1 ; + ANTENNAGATEAREA 0.20085 LAYER Metal2 ; + ANTENNAMAXAREACAR 4.394822 LAYER Metal2 ; + PORT + LAYER Metal2 ; + RECT 175.435 0 175.695 0.26 ; + END + END B_BIST_BM[9] + PIN B_DOUT[22] + DIRECTION OUTPUT ; + USE SIGNAL ; + ANTENNAPARTIALMETALAREA 4.836 LAYER Metal2 ; + ANTENNADIFFAREA 0.988 LAYER Metal2 ; + PORT + LAYER Metal2 ; + RECT 541.26 0 541.52 0.26 ; + END + END B_DOUT[22] + PIN B_DOUT[9] + DIRECTION OUTPUT ; + USE SIGNAL ; + ANTENNAPARTIALMETALAREA 4.836 LAYER Metal2 ; + ANTENNADIFFAREA 0.988 LAYER Metal2 ; + PORT + LAYER Metal2 ; + RECT 161.31 0 161.57 0.26 ; + END + END B_DOUT[9] + PIN A_DIN[23] + DIRECTION INPUT ; + USE SIGNAL ; + ANTENNAPARTIALMETALAREA 3.9091 LAYER Metal2 ; + ANTENNAMODEL OXIDE1 ; + ANTENNAGATEAREA 0.20085 LAYER Metal2 ; + ANTENNAMAXAREACAR 20.368932 LAYER Metal2 ; + PORT + LAYER Metal2 ; + RECT 549.25 0 549.51 0.26 ; + END + END A_DIN[23] + PIN A_DIN[8] + DIRECTION INPUT ; + USE SIGNAL ; + ANTENNAPARTIALMETALAREA 3.9091 LAYER Metal2 ; + ANTENNAMODEL OXIDE1 ; + ANTENNAGATEAREA 0.20085 LAYER Metal2 ; + ANTENNAMAXAREACAR 20.368932 LAYER Metal2 ; + PORT + LAYER Metal2 ; + RECT 153.32 0 153.58 0.26 ; + END + END A_DIN[8] + PIN A_BIST_DIN[23] + DIRECTION INPUT ; + USE SIGNAL ; + ANTENNAPARTIALMETALAREA 4.136375 LAYER Metal2 ; + ANTENNAMODEL OXIDE1 ; + ANTENNAGATEAREA 0.20085 LAYER Metal2 ; + ANTENNAMAXAREACAR 21.874907 LAYER Metal2 ; + PORT + LAYER Metal2 ; + RECT 549.76 0 550.02 0.26 ; + END + END A_BIST_DIN[23] + PIN A_BIST_DIN[8] + DIRECTION INPUT ; + USE SIGNAL ; + ANTENNAPARTIALMETALAREA 4.136375 LAYER Metal2 ; + ANTENNAMODEL OXIDE1 ; + ANTENNAGATEAREA 0.20085 LAYER Metal2 ; + ANTENNAMAXAREACAR 21.874907 LAYER Metal2 ; + PORT + LAYER Metal2 ; + RECT 152.81 0 153.07 0.26 ; + END + END A_BIST_DIN[8] + PIN A_BM[23] + DIRECTION INPUT ; + USE SIGNAL ; + ANTENNAPARTIALMETALAREA 1.7264 LAYER Metal2 ; + ANTENNAMODEL OXIDE1 ; + ANTENNAGATEAREA 0.20085 LAYER Metal2 ; + ANTENNAMAXAREACAR 9.501618 LAYER Metal2 ; + PORT + LAYER Metal2 ; + RECT 557.92 0 558.18 0.26 ; + END + END A_BM[23] + PIN A_BM[8] + DIRECTION INPUT ; + USE SIGNAL ; + ANTENNAPARTIALMETALAREA 1.7264 LAYER Metal2 ; + ANTENNAMODEL OXIDE1 ; + ANTENNAGATEAREA 0.20085 LAYER Metal2 ; + ANTENNAMAXAREACAR 9.501618 LAYER Metal2 ; + PORT + LAYER Metal2 ; + RECT 144.65 0 144.91 0.26 ; + END + END A_BM[8] + PIN A_BIST_BM[23] + DIRECTION INPUT ; + USE SIGNAL ; + ANTENNAPARTIALMETALAREA 1.7602 LAYER Metal2 ; + ANTENNAMODEL OXIDE1 ; + ANTENNAGATEAREA 0.20085 LAYER Metal2 ; + ANTENNAMAXAREACAR 9.678367 LAYER Metal2 ; + PORT + LAYER Metal2 ; + RECT 556.545 0 556.805 0.26 ; + END + END A_BIST_BM[23] + PIN A_BIST_BM[8] + DIRECTION INPUT ; + USE SIGNAL ; + ANTENNAPARTIALMETALAREA 1.7602 LAYER Metal2 ; + ANTENNAMODEL OXIDE1 ; + ANTENNAGATEAREA 0.20085 LAYER Metal2 ; + ANTENNAMAXAREACAR 9.678367 LAYER Metal2 ; + PORT + LAYER Metal2 ; + RECT 146.025 0 146.285 0.26 ; + END + END A_BIST_BM[8] + PIN A_DOUT[23] + DIRECTION OUTPUT ; + USE SIGNAL ; + ANTENNAPARTIALMETALAREA 4.8256 LAYER Metal2 ; + ANTENNADIFFAREA 0.988 LAYER Metal2 ; + PORT + LAYER Metal2 ; + RECT 542.11 0 542.37 0.26 ; + END + END A_DOUT[23] + PIN A_DOUT[8] + DIRECTION OUTPUT ; + USE SIGNAL ; + ANTENNAPARTIALMETALAREA 4.8256 LAYER Metal2 ; + ANTENNADIFFAREA 0.988 LAYER Metal2 ; + PORT + LAYER Metal2 ; + RECT 160.46 0 160.72 0.26 ; + END + END A_DOUT[8] + PIN B_DIN[23] + DIRECTION INPUT ; + USE SIGNAL ; + ANTENNAPARTIALMETALAREA 2.925 LAYER Metal2 ; + ANTENNAMODEL OXIDE1 ; + ANTENNAGATEAREA 0.20085 LAYER Metal2 ; + ANTENNAMAXAREACAR 15.469256 LAYER Metal2 ; + PORT + LAYER Metal2 ; + RECT 551.8 0 552.06 0.26 ; + END + END B_DIN[23] + PIN B_DIN[8] + DIRECTION INPUT ; + USE SIGNAL ; + ANTENNAPARTIALMETALAREA 2.925 LAYER Metal2 ; + ANTENNAMODEL OXIDE1 ; + ANTENNAGATEAREA 0.20085 LAYER Metal2 ; + ANTENNAMAXAREACAR 15.469256 LAYER Metal2 ; + PORT + LAYER Metal2 ; + RECT 150.77 0 151.03 0.26 ; + END + END B_DIN[8] + PIN B_BIST_DIN[23] + DIRECTION INPUT ; + USE SIGNAL ; + ANTENNAPARTIALMETALAREA 2.9445 LAYER Metal2 ; + ANTENNAMODEL OXIDE1 ; + ANTENNAGATEAREA 0.20085 LAYER Metal2 ; + ANTENNAMAXAREACAR 15.929052 LAYER Metal2 ; + PORT + LAYER Metal2 ; + RECT 550.27 0 550.53 0.26 ; + END + END B_BIST_DIN[23] + PIN B_BIST_DIN[8] + DIRECTION INPUT ; + USE SIGNAL ; + ANTENNAPARTIALMETALAREA 2.9445 LAYER Metal2 ; + ANTENNAMODEL OXIDE1 ; + ANTENNAGATEAREA 0.20085 LAYER Metal2 ; + ANTENNAMAXAREACAR 15.929052 LAYER Metal2 ; + PORT + LAYER Metal2 ; + RECT 152.3 0 152.56 0.26 ; + END + END B_BIST_DIN[8] + PIN B_BM[23] + DIRECTION INPUT ; + USE SIGNAL ; + ANTENNAPARTIALMETALAREA 0.7007 LAYER Metal2 ; + ANTENNAMODEL OXIDE1 ; + ANTENNAGATEAREA 0.20085 LAYER Metal2 ; + ANTENNAMAXAREACAR 4.394822 LAYER Metal2 ; + PORT + LAYER Metal2 ; + RECT 543.285 0 543.545 0.26 ; + END + END B_BM[23] + PIN B_BM[8] + DIRECTION INPUT ; + USE SIGNAL ; + ANTENNAPARTIALMETALAREA 0.7007 LAYER Metal2 ; + ANTENNAMODEL OXIDE1 ; + ANTENNAGATEAREA 0.20085 LAYER Metal2 ; + ANTENNAMAXAREACAR 4.394822 LAYER Metal2 ; + PORT + LAYER Metal2 ; + RECT 159.285 0 159.545 0.26 ; + END + END B_BM[8] + PIN B_BIST_BM[23] + DIRECTION INPUT ; + USE SIGNAL ; + ANTENNAPARTIALMETALAREA 0.7007 LAYER Metal2 ; + ANTENNAMODEL OXIDE1 ; + ANTENNAGATEAREA 0.20085 LAYER Metal2 ; + ANTENNAMAXAREACAR 4.394822 LAYER Metal2 ; + PORT + LAYER Metal2 ; + RECT 544.815 0 545.075 0.26 ; + END + END B_BIST_BM[23] + PIN B_BIST_BM[8] + DIRECTION INPUT ; + USE SIGNAL ; + ANTENNAPARTIALMETALAREA 0.7007 LAYER Metal2 ; + ANTENNAMODEL OXIDE1 ; + ANTENNAGATEAREA 0.20085 LAYER Metal2 ; + ANTENNAMAXAREACAR 4.394822 LAYER Metal2 ; + PORT + LAYER Metal2 ; + RECT 157.755 0 158.015 0.26 ; + END + END B_BIST_BM[8] + PIN B_DOUT[23] + DIRECTION OUTPUT ; + USE SIGNAL ; + ANTENNAPARTIALMETALAREA 4.836 LAYER Metal2 ; + ANTENNADIFFAREA 0.988 LAYER Metal2 ; + PORT + LAYER Metal2 ; + RECT 558.94 0 559.2 0.26 ; + END + END B_DOUT[23] + PIN B_DOUT[8] + DIRECTION OUTPUT ; + USE SIGNAL ; + ANTENNAPARTIALMETALAREA 4.836 LAYER Metal2 ; + ANTENNADIFFAREA 0.988 LAYER Metal2 ; + PORT + LAYER Metal2 ; + RECT 143.63 0 143.89 0.26 ; + END + END B_DOUT[8] + PIN A_DIN[24] + DIRECTION INPUT ; + USE SIGNAL ; + ANTENNAPARTIALMETALAREA 3.9091 LAYER Metal2 ; + ANTENNAMODEL OXIDE1 ; + ANTENNAGATEAREA 0.20085 LAYER Metal2 ; + ANTENNAMAXAREACAR 20.368932 LAYER Metal2 ; + PORT + LAYER Metal2 ; + RECT 566.93 0 567.19 0.26 ; + END + END A_DIN[24] + PIN A_DIN[7] + DIRECTION INPUT ; + USE SIGNAL ; + ANTENNAPARTIALMETALAREA 3.9091 LAYER Metal2 ; + ANTENNAMODEL OXIDE1 ; + ANTENNAGATEAREA 0.20085 LAYER Metal2 ; + ANTENNAMAXAREACAR 20.368932 LAYER Metal2 ; + PORT + LAYER Metal2 ; + RECT 135.64 0 135.9 0.26 ; + END + END A_DIN[7] + PIN A_BIST_DIN[24] + DIRECTION INPUT ; + USE SIGNAL ; + ANTENNAPARTIALMETALAREA 4.136375 LAYER Metal2 ; + ANTENNAMODEL OXIDE1 ; + ANTENNAGATEAREA 0.20085 LAYER Metal2 ; + ANTENNAMAXAREACAR 21.874907 LAYER Metal2 ; + PORT + LAYER Metal2 ; + RECT 567.44 0 567.7 0.26 ; + END + END A_BIST_DIN[24] + PIN A_BIST_DIN[7] + DIRECTION INPUT ; + USE SIGNAL ; + ANTENNAPARTIALMETALAREA 4.136375 LAYER Metal2 ; + ANTENNAMODEL OXIDE1 ; + ANTENNAGATEAREA 0.20085 LAYER Metal2 ; + ANTENNAMAXAREACAR 21.874907 LAYER Metal2 ; + PORT + LAYER Metal2 ; + RECT 135.13 0 135.39 0.26 ; + END + END A_BIST_DIN[7] + PIN A_BM[24] + DIRECTION INPUT ; + USE SIGNAL ; + ANTENNAPARTIALMETALAREA 1.7264 LAYER Metal2 ; + ANTENNAMODEL OXIDE1 ; + ANTENNAGATEAREA 0.20085 LAYER Metal2 ; + ANTENNAMAXAREACAR 9.501618 LAYER Metal2 ; + PORT + LAYER Metal2 ; + RECT 575.6 0 575.86 0.26 ; + END + END A_BM[24] + PIN A_BM[7] + DIRECTION INPUT ; + USE SIGNAL ; + ANTENNAPARTIALMETALAREA 1.7264 LAYER Metal2 ; + ANTENNAMODEL OXIDE1 ; + ANTENNAGATEAREA 0.20085 LAYER Metal2 ; + ANTENNAMAXAREACAR 9.501618 LAYER Metal2 ; + PORT + LAYER Metal2 ; + RECT 126.97 0 127.23 0.26 ; + END + END A_BM[7] + PIN A_BIST_BM[24] + DIRECTION INPUT ; + USE SIGNAL ; + ANTENNAPARTIALMETALAREA 1.7602 LAYER Metal2 ; + ANTENNAMODEL OXIDE1 ; + ANTENNAGATEAREA 0.20085 LAYER Metal2 ; + ANTENNAMAXAREACAR 9.678367 LAYER Metal2 ; + PORT + LAYER Metal2 ; + RECT 574.225 0 574.485 0.26 ; + END + END A_BIST_BM[24] + PIN A_BIST_BM[7] + DIRECTION INPUT ; + USE SIGNAL ; + ANTENNAPARTIALMETALAREA 1.7602 LAYER Metal2 ; + ANTENNAMODEL OXIDE1 ; + ANTENNAGATEAREA 0.20085 LAYER Metal2 ; + ANTENNAMAXAREACAR 9.678367 LAYER Metal2 ; + PORT + LAYER Metal2 ; + RECT 128.345 0 128.605 0.26 ; + END + END A_BIST_BM[7] + PIN A_DOUT[24] + DIRECTION OUTPUT ; + USE SIGNAL ; + ANTENNAPARTIALMETALAREA 4.8256 LAYER Metal2 ; + ANTENNADIFFAREA 0.988 LAYER Metal2 ; + PORT + LAYER Metal2 ; + RECT 559.79 0 560.05 0.26 ; + END + END A_DOUT[24] + PIN A_DOUT[7] + DIRECTION OUTPUT ; + USE SIGNAL ; + ANTENNAPARTIALMETALAREA 4.8256 LAYER Metal2 ; + ANTENNADIFFAREA 0.988 LAYER Metal2 ; + PORT + LAYER Metal2 ; + RECT 142.78 0 143.04 0.26 ; + END + END A_DOUT[7] + PIN B_DIN[24] + DIRECTION INPUT ; + USE SIGNAL ; + ANTENNAPARTIALMETALAREA 2.925 LAYER Metal2 ; + ANTENNAMODEL OXIDE1 ; + ANTENNAGATEAREA 0.20085 LAYER Metal2 ; + ANTENNAMAXAREACAR 15.469256 LAYER Metal2 ; + PORT + LAYER Metal2 ; + RECT 569.48 0 569.74 0.26 ; + END + END B_DIN[24] + PIN B_DIN[7] + DIRECTION INPUT ; + USE SIGNAL ; + ANTENNAPARTIALMETALAREA 2.925 LAYER Metal2 ; + ANTENNAMODEL OXIDE1 ; + ANTENNAGATEAREA 0.20085 LAYER Metal2 ; + ANTENNAMAXAREACAR 15.469256 LAYER Metal2 ; + PORT + LAYER Metal2 ; + RECT 133.09 0 133.35 0.26 ; + END + END B_DIN[7] + PIN B_BIST_DIN[24] + DIRECTION INPUT ; + USE SIGNAL ; + ANTENNAPARTIALMETALAREA 2.9445 LAYER Metal2 ; + ANTENNAMODEL OXIDE1 ; + ANTENNAGATEAREA 0.20085 LAYER Metal2 ; + ANTENNAMAXAREACAR 15.929052 LAYER Metal2 ; + PORT + LAYER Metal2 ; + RECT 567.95 0 568.21 0.26 ; + END + END B_BIST_DIN[24] + PIN B_BIST_DIN[7] + DIRECTION INPUT ; + USE SIGNAL ; + ANTENNAPARTIALMETALAREA 2.9445 LAYER Metal2 ; + ANTENNAMODEL OXIDE1 ; + ANTENNAGATEAREA 0.20085 LAYER Metal2 ; + ANTENNAMAXAREACAR 15.929052 LAYER Metal2 ; + PORT + LAYER Metal2 ; + RECT 134.62 0 134.88 0.26 ; + END + END B_BIST_DIN[7] + PIN B_BM[24] + DIRECTION INPUT ; + USE SIGNAL ; + ANTENNAPARTIALMETALAREA 0.7007 LAYER Metal2 ; + ANTENNAMODEL OXIDE1 ; + ANTENNAGATEAREA 0.20085 LAYER Metal2 ; + ANTENNAMAXAREACAR 4.394822 LAYER Metal2 ; + PORT + LAYER Metal2 ; + RECT 560.965 0 561.225 0.26 ; + END + END B_BM[24] + PIN B_BM[7] + DIRECTION INPUT ; + USE SIGNAL ; + ANTENNAPARTIALMETALAREA 0.7007 LAYER Metal2 ; + ANTENNAMODEL OXIDE1 ; + ANTENNAGATEAREA 0.20085 LAYER Metal2 ; + ANTENNAMAXAREACAR 4.394822 LAYER Metal2 ; + PORT + LAYER Metal2 ; + RECT 141.605 0 141.865 0.26 ; + END + END B_BM[7] + PIN B_BIST_BM[24] + DIRECTION INPUT ; + USE SIGNAL ; + ANTENNAPARTIALMETALAREA 0.7007 LAYER Metal2 ; + ANTENNAMODEL OXIDE1 ; + ANTENNAGATEAREA 0.20085 LAYER Metal2 ; + ANTENNAMAXAREACAR 4.394822 LAYER Metal2 ; + PORT + LAYER Metal2 ; + RECT 562.495 0 562.755 0.26 ; + END + END B_BIST_BM[24] + PIN B_BIST_BM[7] + DIRECTION INPUT ; + USE SIGNAL ; + ANTENNAPARTIALMETALAREA 0.7007 LAYER Metal2 ; + ANTENNAMODEL OXIDE1 ; + ANTENNAGATEAREA 0.20085 LAYER Metal2 ; + ANTENNAMAXAREACAR 4.394822 LAYER Metal2 ; + PORT + LAYER Metal2 ; + RECT 140.075 0 140.335 0.26 ; + END + END B_BIST_BM[7] + PIN B_DOUT[24] + DIRECTION OUTPUT ; + USE SIGNAL ; + ANTENNAPARTIALMETALAREA 4.836 LAYER Metal2 ; + ANTENNADIFFAREA 0.988 LAYER Metal2 ; + PORT + LAYER Metal2 ; + RECT 576.62 0 576.88 0.26 ; + END + END B_DOUT[24] + PIN B_DOUT[7] + DIRECTION OUTPUT ; + USE SIGNAL ; + ANTENNAPARTIALMETALAREA 4.836 LAYER Metal2 ; + ANTENNADIFFAREA 0.988 LAYER Metal2 ; + PORT + LAYER Metal2 ; + RECT 125.95 0 126.21 0.26 ; + END + END B_DOUT[7] + PIN A_DIN[25] + DIRECTION INPUT ; + USE SIGNAL ; + ANTENNAPARTIALMETALAREA 3.9091 LAYER Metal2 ; + ANTENNAMODEL OXIDE1 ; + ANTENNAGATEAREA 0.20085 LAYER Metal2 ; + ANTENNAMAXAREACAR 20.368932 LAYER Metal2 ; + PORT + LAYER Metal2 ; + RECT 584.61 0 584.87 0.26 ; + END + END A_DIN[25] + PIN A_DIN[6] + DIRECTION INPUT ; + USE SIGNAL ; + ANTENNAPARTIALMETALAREA 3.9091 LAYER Metal2 ; + ANTENNAMODEL OXIDE1 ; + ANTENNAGATEAREA 0.20085 LAYER Metal2 ; + ANTENNAMAXAREACAR 20.368932 LAYER Metal2 ; + PORT + LAYER Metal2 ; + RECT 117.96 0 118.22 0.26 ; + END + END A_DIN[6] + PIN A_BIST_DIN[25] + DIRECTION INPUT ; + USE SIGNAL ; + ANTENNAPARTIALMETALAREA 4.136375 LAYER Metal2 ; + ANTENNAMODEL OXIDE1 ; + ANTENNAGATEAREA 0.20085 LAYER Metal2 ; + ANTENNAMAXAREACAR 21.874907 LAYER Metal2 ; + PORT + LAYER Metal2 ; + RECT 585.12 0 585.38 0.26 ; + END + END A_BIST_DIN[25] + PIN A_BIST_DIN[6] + DIRECTION INPUT ; + USE SIGNAL ; + ANTENNAPARTIALMETALAREA 4.136375 LAYER Metal2 ; + ANTENNAMODEL OXIDE1 ; + ANTENNAGATEAREA 0.20085 LAYER Metal2 ; + ANTENNAMAXAREACAR 21.874907 LAYER Metal2 ; + PORT + LAYER Metal2 ; + RECT 117.45 0 117.71 0.26 ; + END + END A_BIST_DIN[6] + PIN A_BM[25] + DIRECTION INPUT ; + USE SIGNAL ; + ANTENNAPARTIALMETALAREA 1.7264 LAYER Metal2 ; + ANTENNAMODEL OXIDE1 ; + ANTENNAGATEAREA 0.20085 LAYER Metal2 ; + ANTENNAMAXAREACAR 9.501618 LAYER Metal2 ; + PORT + LAYER Metal2 ; + RECT 593.28 0 593.54 0.26 ; + END + END A_BM[25] + PIN A_BM[6] + DIRECTION INPUT ; + USE SIGNAL ; + ANTENNAPARTIALMETALAREA 1.7264 LAYER Metal2 ; + ANTENNAMODEL OXIDE1 ; + ANTENNAGATEAREA 0.20085 LAYER Metal2 ; + ANTENNAMAXAREACAR 9.501618 LAYER Metal2 ; + PORT + LAYER Metal2 ; + RECT 109.29 0 109.55 0.26 ; + END + END A_BM[6] + PIN A_BIST_BM[25] + DIRECTION INPUT ; + USE SIGNAL ; + ANTENNAPARTIALMETALAREA 1.7602 LAYER Metal2 ; + ANTENNAMODEL OXIDE1 ; + ANTENNAGATEAREA 0.20085 LAYER Metal2 ; + ANTENNAMAXAREACAR 9.678367 LAYER Metal2 ; + PORT + LAYER Metal2 ; + RECT 591.905 0 592.165 0.26 ; + END + END A_BIST_BM[25] + PIN A_BIST_BM[6] + DIRECTION INPUT ; + USE SIGNAL ; + ANTENNAPARTIALMETALAREA 1.7602 LAYER Metal2 ; + ANTENNAMODEL OXIDE1 ; + ANTENNAGATEAREA 0.20085 LAYER Metal2 ; + ANTENNAMAXAREACAR 9.678367 LAYER Metal2 ; + PORT + LAYER Metal2 ; + RECT 110.665 0 110.925 0.26 ; + END + END A_BIST_BM[6] + PIN A_DOUT[25] + DIRECTION OUTPUT ; + USE SIGNAL ; + ANTENNAPARTIALMETALAREA 4.8256 LAYER Metal2 ; + ANTENNADIFFAREA 0.988 LAYER Metal2 ; + PORT + LAYER Metal2 ; + RECT 577.47 0 577.73 0.26 ; + END + END A_DOUT[25] + PIN A_DOUT[6] + DIRECTION OUTPUT ; + USE SIGNAL ; + ANTENNAPARTIALMETALAREA 4.8256 LAYER Metal2 ; + ANTENNADIFFAREA 0.988 LAYER Metal2 ; + PORT + LAYER Metal2 ; + RECT 125.1 0 125.36 0.26 ; + END + END A_DOUT[6] + PIN B_DIN[25] + DIRECTION INPUT ; + USE SIGNAL ; + ANTENNAPARTIALMETALAREA 2.925 LAYER Metal2 ; + ANTENNAMODEL OXIDE1 ; + ANTENNAGATEAREA 0.20085 LAYER Metal2 ; + ANTENNAMAXAREACAR 15.469256 LAYER Metal2 ; + PORT + LAYER Metal2 ; + RECT 587.16 0 587.42 0.26 ; + END + END B_DIN[25] + PIN B_DIN[6] + DIRECTION INPUT ; + USE SIGNAL ; + ANTENNAPARTIALMETALAREA 2.925 LAYER Metal2 ; + ANTENNAMODEL OXIDE1 ; + ANTENNAGATEAREA 0.20085 LAYER Metal2 ; + ANTENNAMAXAREACAR 15.469256 LAYER Metal2 ; + PORT + LAYER Metal2 ; + RECT 115.41 0 115.67 0.26 ; + END + END B_DIN[6] + PIN B_BIST_DIN[25] + DIRECTION INPUT ; + USE SIGNAL ; + ANTENNAPARTIALMETALAREA 2.9445 LAYER Metal2 ; + ANTENNAMODEL OXIDE1 ; + ANTENNAGATEAREA 0.20085 LAYER Metal2 ; + ANTENNAMAXAREACAR 15.929052 LAYER Metal2 ; + PORT + LAYER Metal2 ; + RECT 585.63 0 585.89 0.26 ; + END + END B_BIST_DIN[25] + PIN B_BIST_DIN[6] + DIRECTION INPUT ; + USE SIGNAL ; + ANTENNAPARTIALMETALAREA 2.9445 LAYER Metal2 ; + ANTENNAMODEL OXIDE1 ; + ANTENNAGATEAREA 0.20085 LAYER Metal2 ; + ANTENNAMAXAREACAR 15.929052 LAYER Metal2 ; + PORT + LAYER Metal2 ; + RECT 116.94 0 117.2 0.26 ; + END + END B_BIST_DIN[6] + PIN B_BM[25] + DIRECTION INPUT ; + USE SIGNAL ; + ANTENNAPARTIALMETALAREA 0.7007 LAYER Metal2 ; + ANTENNAMODEL OXIDE1 ; + ANTENNAGATEAREA 0.20085 LAYER Metal2 ; + ANTENNAMAXAREACAR 4.394822 LAYER Metal2 ; + PORT + LAYER Metal2 ; + RECT 578.645 0 578.905 0.26 ; + END + END B_BM[25] + PIN B_BM[6] + DIRECTION INPUT ; + USE SIGNAL ; + ANTENNAPARTIALMETALAREA 0.7007 LAYER Metal2 ; + ANTENNAMODEL OXIDE1 ; + ANTENNAGATEAREA 0.20085 LAYER Metal2 ; + ANTENNAMAXAREACAR 4.394822 LAYER Metal2 ; + PORT + LAYER Metal2 ; + RECT 123.925 0 124.185 0.26 ; + END + END B_BM[6] + PIN B_BIST_BM[25] + DIRECTION INPUT ; + USE SIGNAL ; + ANTENNAPARTIALMETALAREA 0.7007 LAYER Metal2 ; + ANTENNAMODEL OXIDE1 ; + ANTENNAGATEAREA 0.20085 LAYER Metal2 ; + ANTENNAMAXAREACAR 4.394822 LAYER Metal2 ; + PORT + LAYER Metal2 ; + RECT 580.175 0 580.435 0.26 ; + END + END B_BIST_BM[25] + PIN B_BIST_BM[6] + DIRECTION INPUT ; + USE SIGNAL ; + ANTENNAPARTIALMETALAREA 0.7007 LAYER Metal2 ; + ANTENNAMODEL OXIDE1 ; + ANTENNAGATEAREA 0.20085 LAYER Metal2 ; + ANTENNAMAXAREACAR 4.394822 LAYER Metal2 ; + PORT + LAYER Metal2 ; + RECT 122.395 0 122.655 0.26 ; + END + END B_BIST_BM[6] + PIN B_DOUT[25] + DIRECTION OUTPUT ; + USE SIGNAL ; + ANTENNAPARTIALMETALAREA 4.836 LAYER Metal2 ; + ANTENNADIFFAREA 0.988 LAYER Metal2 ; + PORT + LAYER Metal2 ; + RECT 594.3 0 594.56 0.26 ; + END + END B_DOUT[25] + PIN B_DOUT[6] + DIRECTION OUTPUT ; + USE SIGNAL ; + ANTENNAPARTIALMETALAREA 4.836 LAYER Metal2 ; + ANTENNADIFFAREA 0.988 LAYER Metal2 ; + PORT + LAYER Metal2 ; + RECT 108.27 0 108.53 0.26 ; + END + END B_DOUT[6] + PIN A_DIN[26] + DIRECTION INPUT ; + USE SIGNAL ; + ANTENNAPARTIALMETALAREA 3.9091 LAYER Metal2 ; + ANTENNAMODEL OXIDE1 ; + ANTENNAGATEAREA 0.20085 LAYER Metal2 ; + ANTENNAMAXAREACAR 20.368932 LAYER Metal2 ; + PORT + LAYER Metal2 ; + RECT 602.29 0 602.55 0.26 ; + END + END A_DIN[26] + PIN A_DIN[5] + DIRECTION INPUT ; + USE SIGNAL ; + ANTENNAPARTIALMETALAREA 3.9091 LAYER Metal2 ; + ANTENNAMODEL OXIDE1 ; + ANTENNAGATEAREA 0.20085 LAYER Metal2 ; + ANTENNAMAXAREACAR 20.368932 LAYER Metal2 ; + PORT + LAYER Metal2 ; + RECT 100.28 0 100.54 0.26 ; + END + END A_DIN[5] + PIN A_BIST_DIN[26] + DIRECTION INPUT ; + USE SIGNAL ; + ANTENNAPARTIALMETALAREA 4.136375 LAYER Metal2 ; + ANTENNAMODEL OXIDE1 ; + ANTENNAGATEAREA 0.20085 LAYER Metal2 ; + ANTENNAMAXAREACAR 21.874907 LAYER Metal2 ; + PORT + LAYER Metal2 ; + RECT 602.8 0 603.06 0.26 ; + END + END A_BIST_DIN[26] + PIN A_BIST_DIN[5] + DIRECTION INPUT ; + USE SIGNAL ; + ANTENNAPARTIALMETALAREA 4.136375 LAYER Metal2 ; + ANTENNAMODEL OXIDE1 ; + ANTENNAGATEAREA 0.20085 LAYER Metal2 ; + ANTENNAMAXAREACAR 21.874907 LAYER Metal2 ; + PORT + LAYER Metal2 ; + RECT 99.77 0 100.03 0.26 ; + END + END A_BIST_DIN[5] + PIN A_BM[26] + DIRECTION INPUT ; + USE SIGNAL ; + ANTENNAPARTIALMETALAREA 1.7264 LAYER Metal2 ; + ANTENNAMODEL OXIDE1 ; + ANTENNAGATEAREA 0.20085 LAYER Metal2 ; + ANTENNAMAXAREACAR 9.501618 LAYER Metal2 ; + PORT + LAYER Metal2 ; + RECT 610.96 0 611.22 0.26 ; + END + END A_BM[26] + PIN A_BM[5] + DIRECTION INPUT ; + USE SIGNAL ; + ANTENNAPARTIALMETALAREA 1.7264 LAYER Metal2 ; + ANTENNAMODEL OXIDE1 ; + ANTENNAGATEAREA 0.20085 LAYER Metal2 ; + ANTENNAMAXAREACAR 9.501618 LAYER Metal2 ; + PORT + LAYER Metal2 ; + RECT 91.61 0 91.87 0.26 ; + END + END A_BM[5] + PIN A_BIST_BM[26] + DIRECTION INPUT ; + USE SIGNAL ; + ANTENNAPARTIALMETALAREA 1.7602 LAYER Metal2 ; + ANTENNAMODEL OXIDE1 ; + ANTENNAGATEAREA 0.20085 LAYER Metal2 ; + ANTENNAMAXAREACAR 9.678367 LAYER Metal2 ; + PORT + LAYER Metal2 ; + RECT 609.585 0 609.845 0.26 ; + END + END A_BIST_BM[26] + PIN A_BIST_BM[5] + DIRECTION INPUT ; + USE SIGNAL ; + ANTENNAPARTIALMETALAREA 1.7602 LAYER Metal2 ; + ANTENNAMODEL OXIDE1 ; + ANTENNAGATEAREA 0.20085 LAYER Metal2 ; + ANTENNAMAXAREACAR 9.678367 LAYER Metal2 ; + PORT + LAYER Metal2 ; + RECT 92.985 0 93.245 0.26 ; + END + END A_BIST_BM[5] + PIN A_DOUT[26] + DIRECTION OUTPUT ; + USE SIGNAL ; + ANTENNAPARTIALMETALAREA 4.8256 LAYER Metal2 ; + ANTENNADIFFAREA 0.988 LAYER Metal2 ; + PORT + LAYER Metal2 ; + RECT 595.15 0 595.41 0.26 ; + END + END A_DOUT[26] + PIN A_DOUT[5] + DIRECTION OUTPUT ; + USE SIGNAL ; + ANTENNAPARTIALMETALAREA 4.8256 LAYER Metal2 ; + ANTENNADIFFAREA 0.988 LAYER Metal2 ; + PORT + LAYER Metal2 ; + RECT 107.42 0 107.68 0.26 ; + END + END A_DOUT[5] + PIN B_DIN[26] + DIRECTION INPUT ; + USE SIGNAL ; + ANTENNAPARTIALMETALAREA 2.925 LAYER Metal2 ; + ANTENNAMODEL OXIDE1 ; + ANTENNAGATEAREA 0.20085 LAYER Metal2 ; + ANTENNAMAXAREACAR 15.469256 LAYER Metal2 ; + PORT + LAYER Metal2 ; + RECT 604.84 0 605.1 0.26 ; + END + END B_DIN[26] + PIN B_DIN[5] + DIRECTION INPUT ; + USE SIGNAL ; + ANTENNAPARTIALMETALAREA 2.925 LAYER Metal2 ; + ANTENNAMODEL OXIDE1 ; + ANTENNAGATEAREA 0.20085 LAYER Metal2 ; + ANTENNAMAXAREACAR 15.469256 LAYER Metal2 ; + PORT + LAYER Metal2 ; + RECT 97.73 0 97.99 0.26 ; + END + END B_DIN[5] + PIN B_BIST_DIN[26] + DIRECTION INPUT ; + USE SIGNAL ; + ANTENNAPARTIALMETALAREA 2.9445 LAYER Metal2 ; + ANTENNAMODEL OXIDE1 ; + ANTENNAGATEAREA 0.20085 LAYER Metal2 ; + ANTENNAMAXAREACAR 15.929052 LAYER Metal2 ; + PORT + LAYER Metal2 ; + RECT 603.31 0 603.57 0.26 ; + END + END B_BIST_DIN[26] + PIN B_BIST_DIN[5] + DIRECTION INPUT ; + USE SIGNAL ; + ANTENNAPARTIALMETALAREA 2.9445 LAYER Metal2 ; + ANTENNAMODEL OXIDE1 ; + ANTENNAGATEAREA 0.20085 LAYER Metal2 ; + ANTENNAMAXAREACAR 15.929052 LAYER Metal2 ; + PORT + LAYER Metal2 ; + RECT 99.26 0 99.52 0.26 ; + END + END B_BIST_DIN[5] + PIN B_BM[26] + DIRECTION INPUT ; + USE SIGNAL ; + ANTENNAPARTIALMETALAREA 0.7007 LAYER Metal2 ; + ANTENNAMODEL OXIDE1 ; + ANTENNAGATEAREA 0.20085 LAYER Metal2 ; + ANTENNAMAXAREACAR 4.394822 LAYER Metal2 ; + PORT + LAYER Metal2 ; + RECT 596.325 0 596.585 0.26 ; + END + END B_BM[26] + PIN B_BM[5] + DIRECTION INPUT ; + USE SIGNAL ; + ANTENNAPARTIALMETALAREA 0.7007 LAYER Metal2 ; + ANTENNAMODEL OXIDE1 ; + ANTENNAGATEAREA 0.20085 LAYER Metal2 ; + ANTENNAMAXAREACAR 4.394822 LAYER Metal2 ; + PORT + LAYER Metal2 ; + RECT 106.245 0 106.505 0.26 ; + END + END B_BM[5] + PIN B_BIST_BM[26] + DIRECTION INPUT ; + USE SIGNAL ; + ANTENNAPARTIALMETALAREA 0.7007 LAYER Metal2 ; + ANTENNAMODEL OXIDE1 ; + ANTENNAGATEAREA 0.20085 LAYER Metal2 ; + ANTENNAMAXAREACAR 4.394822 LAYER Metal2 ; + PORT + LAYER Metal2 ; + RECT 597.855 0 598.115 0.26 ; + END + END B_BIST_BM[26] + PIN B_BIST_BM[5] + DIRECTION INPUT ; + USE SIGNAL ; + ANTENNAPARTIALMETALAREA 0.7007 LAYER Metal2 ; + ANTENNAMODEL OXIDE1 ; + ANTENNAGATEAREA 0.20085 LAYER Metal2 ; + ANTENNAMAXAREACAR 4.394822 LAYER Metal2 ; + PORT + LAYER Metal2 ; + RECT 104.715 0 104.975 0.26 ; + END + END B_BIST_BM[5] + PIN B_DOUT[26] + DIRECTION OUTPUT ; + USE SIGNAL ; + ANTENNAPARTIALMETALAREA 4.836 LAYER Metal2 ; + ANTENNADIFFAREA 0.988 LAYER Metal2 ; + PORT + LAYER Metal2 ; + RECT 611.98 0 612.24 0.26 ; + END + END B_DOUT[26] + PIN B_DOUT[5] + DIRECTION OUTPUT ; + USE SIGNAL ; + ANTENNAPARTIALMETALAREA 4.836 LAYER Metal2 ; + ANTENNADIFFAREA 0.988 LAYER Metal2 ; + PORT + LAYER Metal2 ; + RECT 90.59 0 90.85 0.26 ; + END + END B_DOUT[5] + PIN A_DIN[27] + DIRECTION INPUT ; + USE SIGNAL ; + ANTENNAPARTIALMETALAREA 3.9091 LAYER Metal2 ; + ANTENNAMODEL OXIDE1 ; + ANTENNAGATEAREA 0.20085 LAYER Metal2 ; + ANTENNAMAXAREACAR 20.368932 LAYER Metal2 ; + PORT + LAYER Metal2 ; + RECT 619.97 0 620.23 0.26 ; + END + END A_DIN[27] + PIN A_DIN[4] + DIRECTION INPUT ; + USE SIGNAL ; + ANTENNAPARTIALMETALAREA 3.9091 LAYER Metal2 ; + ANTENNAMODEL OXIDE1 ; + ANTENNAGATEAREA 0.20085 LAYER Metal2 ; + ANTENNAMAXAREACAR 20.368932 LAYER Metal2 ; + PORT + LAYER Metal2 ; + RECT 82.6 0 82.86 0.26 ; + END + END A_DIN[4] + PIN A_BIST_DIN[27] + DIRECTION INPUT ; + USE SIGNAL ; + ANTENNAPARTIALMETALAREA 4.136375 LAYER Metal2 ; + ANTENNAMODEL OXIDE1 ; + ANTENNAGATEAREA 0.20085 LAYER Metal2 ; + ANTENNAMAXAREACAR 21.874907 LAYER Metal2 ; + PORT + LAYER Metal2 ; + RECT 620.48 0 620.74 0.26 ; + END + END A_BIST_DIN[27] + PIN A_BIST_DIN[4] + DIRECTION INPUT ; + USE SIGNAL ; + ANTENNAPARTIALMETALAREA 4.136375 LAYER Metal2 ; + ANTENNAMODEL OXIDE1 ; + ANTENNAGATEAREA 0.20085 LAYER Metal2 ; + ANTENNAMAXAREACAR 21.874907 LAYER Metal2 ; + PORT + LAYER Metal2 ; + RECT 82.09 0 82.35 0.26 ; + END + END A_BIST_DIN[4] + PIN A_BM[27] + DIRECTION INPUT ; + USE SIGNAL ; + ANTENNAPARTIALMETALAREA 1.7264 LAYER Metal2 ; + ANTENNAMODEL OXIDE1 ; + ANTENNAGATEAREA 0.20085 LAYER Metal2 ; + ANTENNAMAXAREACAR 9.501618 LAYER Metal2 ; + PORT + LAYER Metal2 ; + RECT 628.64 0 628.9 0.26 ; + END + END A_BM[27] + PIN A_BM[4] + DIRECTION INPUT ; + USE SIGNAL ; + ANTENNAPARTIALMETALAREA 1.7264 LAYER Metal2 ; + ANTENNAMODEL OXIDE1 ; + ANTENNAGATEAREA 0.20085 LAYER Metal2 ; + ANTENNAMAXAREACAR 9.501618 LAYER Metal2 ; + PORT + LAYER Metal2 ; + RECT 73.93 0 74.19 0.26 ; + END + END A_BM[4] + PIN A_BIST_BM[27] + DIRECTION INPUT ; + USE SIGNAL ; + ANTENNAPARTIALMETALAREA 1.7602 LAYER Metal2 ; + ANTENNAMODEL OXIDE1 ; + ANTENNAGATEAREA 0.20085 LAYER Metal2 ; + ANTENNAMAXAREACAR 9.678367 LAYER Metal2 ; + PORT + LAYER Metal2 ; + RECT 627.265 0 627.525 0.26 ; + END + END A_BIST_BM[27] + PIN A_BIST_BM[4] + DIRECTION INPUT ; + USE SIGNAL ; + ANTENNAPARTIALMETALAREA 1.7602 LAYER Metal2 ; + ANTENNAMODEL OXIDE1 ; + ANTENNAGATEAREA 0.20085 LAYER Metal2 ; + ANTENNAMAXAREACAR 9.678367 LAYER Metal2 ; + PORT + LAYER Metal2 ; + RECT 75.305 0 75.565 0.26 ; + END + END A_BIST_BM[4] + PIN A_DOUT[27] + DIRECTION OUTPUT ; + USE SIGNAL ; + ANTENNAPARTIALMETALAREA 4.8256 LAYER Metal2 ; + ANTENNADIFFAREA 0.988 LAYER Metal2 ; + PORT + LAYER Metal2 ; + RECT 612.83 0 613.09 0.26 ; + END + END A_DOUT[27] + PIN A_DOUT[4] + DIRECTION OUTPUT ; + USE SIGNAL ; + ANTENNAPARTIALMETALAREA 4.8256 LAYER Metal2 ; + ANTENNADIFFAREA 0.988 LAYER Metal2 ; + PORT + LAYER Metal2 ; + RECT 89.74 0 90 0.26 ; + END + END A_DOUT[4] + PIN B_DIN[27] + DIRECTION INPUT ; + USE SIGNAL ; + ANTENNAPARTIALMETALAREA 2.925 LAYER Metal2 ; + ANTENNAMODEL OXIDE1 ; + ANTENNAGATEAREA 0.20085 LAYER Metal2 ; + ANTENNAMAXAREACAR 15.469256 LAYER Metal2 ; + PORT + LAYER Metal2 ; + RECT 622.52 0 622.78 0.26 ; + END + END B_DIN[27] + PIN B_DIN[4] + DIRECTION INPUT ; + USE SIGNAL ; + ANTENNAPARTIALMETALAREA 2.925 LAYER Metal2 ; + ANTENNAMODEL OXIDE1 ; + ANTENNAGATEAREA 0.20085 LAYER Metal2 ; + ANTENNAMAXAREACAR 15.469256 LAYER Metal2 ; + PORT + LAYER Metal2 ; + RECT 80.05 0 80.31 0.26 ; + END + END B_DIN[4] + PIN B_BIST_DIN[27] + DIRECTION INPUT ; + USE SIGNAL ; + ANTENNAPARTIALMETALAREA 2.9445 LAYER Metal2 ; + ANTENNAMODEL OXIDE1 ; + ANTENNAGATEAREA 0.20085 LAYER Metal2 ; + ANTENNAMAXAREACAR 15.929052 LAYER Metal2 ; + PORT + LAYER Metal2 ; + RECT 620.99 0 621.25 0.26 ; + END + END B_BIST_DIN[27] + PIN B_BIST_DIN[4] + DIRECTION INPUT ; + USE SIGNAL ; + ANTENNAPARTIALMETALAREA 2.9445 LAYER Metal2 ; + ANTENNAMODEL OXIDE1 ; + ANTENNAGATEAREA 0.20085 LAYER Metal2 ; + ANTENNAMAXAREACAR 15.929052 LAYER Metal2 ; + PORT + LAYER Metal2 ; + RECT 81.58 0 81.84 0.26 ; + END + END B_BIST_DIN[4] + PIN B_BM[27] + DIRECTION INPUT ; + USE SIGNAL ; + ANTENNAPARTIALMETALAREA 0.7007 LAYER Metal2 ; + ANTENNAMODEL OXIDE1 ; + ANTENNAGATEAREA 0.20085 LAYER Metal2 ; + ANTENNAMAXAREACAR 4.394822 LAYER Metal2 ; + PORT + LAYER Metal2 ; + RECT 614.005 0 614.265 0.26 ; + END + END B_BM[27] + PIN B_BM[4] + DIRECTION INPUT ; + USE SIGNAL ; + ANTENNAPARTIALMETALAREA 0.7007 LAYER Metal2 ; + ANTENNAMODEL OXIDE1 ; + ANTENNAGATEAREA 0.20085 LAYER Metal2 ; + ANTENNAMAXAREACAR 4.394822 LAYER Metal2 ; + PORT + LAYER Metal2 ; + RECT 88.565 0 88.825 0.26 ; + END + END B_BM[4] + PIN B_BIST_BM[27] + DIRECTION INPUT ; + USE SIGNAL ; + ANTENNAPARTIALMETALAREA 0.7007 LAYER Metal2 ; + ANTENNAMODEL OXIDE1 ; + ANTENNAGATEAREA 0.20085 LAYER Metal2 ; + ANTENNAMAXAREACAR 4.394822 LAYER Metal2 ; + PORT + LAYER Metal2 ; + RECT 615.535 0 615.795 0.26 ; + END + END B_BIST_BM[27] + PIN B_BIST_BM[4] + DIRECTION INPUT ; + USE SIGNAL ; + ANTENNAPARTIALMETALAREA 0.7007 LAYER Metal2 ; + ANTENNAMODEL OXIDE1 ; + ANTENNAGATEAREA 0.20085 LAYER Metal2 ; + ANTENNAMAXAREACAR 4.394822 LAYER Metal2 ; + PORT + LAYER Metal2 ; + RECT 87.035 0 87.295 0.26 ; + END + END B_BIST_BM[4] + PIN B_DOUT[27] + DIRECTION OUTPUT ; + USE SIGNAL ; + ANTENNAPARTIALMETALAREA 4.836 LAYER Metal2 ; + ANTENNADIFFAREA 0.988 LAYER Metal2 ; + PORT + LAYER Metal2 ; + RECT 629.66 0 629.92 0.26 ; + END + END B_DOUT[27] + PIN B_DOUT[4] + DIRECTION OUTPUT ; + USE SIGNAL ; + ANTENNAPARTIALMETALAREA 4.836 LAYER Metal2 ; + ANTENNADIFFAREA 0.988 LAYER Metal2 ; + PORT + LAYER Metal2 ; + RECT 72.91 0 73.17 0.26 ; + END + END B_DOUT[4] + PIN A_DIN[28] + DIRECTION INPUT ; + USE SIGNAL ; + ANTENNAPARTIALMETALAREA 3.9091 LAYER Metal2 ; + ANTENNAMODEL OXIDE1 ; + ANTENNAGATEAREA 0.20085 LAYER Metal2 ; + ANTENNAMAXAREACAR 20.368932 LAYER Metal2 ; + PORT + LAYER Metal2 ; + RECT 637.65 0 637.91 0.26 ; + END + END A_DIN[28] + PIN A_DIN[3] + DIRECTION INPUT ; + USE SIGNAL ; + ANTENNAPARTIALMETALAREA 3.9091 LAYER Metal2 ; + ANTENNAMODEL OXIDE1 ; + ANTENNAGATEAREA 0.20085 LAYER Metal2 ; + ANTENNAMAXAREACAR 20.368932 LAYER Metal2 ; + PORT + LAYER Metal2 ; + RECT 64.92 0 65.18 0.26 ; + END + END A_DIN[3] + PIN A_BIST_DIN[28] + DIRECTION INPUT ; + USE SIGNAL ; + ANTENNAPARTIALMETALAREA 4.136375 LAYER Metal2 ; + ANTENNAMODEL OXIDE1 ; + ANTENNAGATEAREA 0.20085 LAYER Metal2 ; + ANTENNAMAXAREACAR 21.874907 LAYER Metal2 ; + PORT + LAYER Metal2 ; + RECT 638.16 0 638.42 0.26 ; + END + END A_BIST_DIN[28] + PIN A_BIST_DIN[3] + DIRECTION INPUT ; + USE SIGNAL ; + ANTENNAPARTIALMETALAREA 4.136375 LAYER Metal2 ; + ANTENNAMODEL OXIDE1 ; + ANTENNAGATEAREA 0.20085 LAYER Metal2 ; + ANTENNAMAXAREACAR 21.874907 LAYER Metal2 ; + PORT + LAYER Metal2 ; + RECT 64.41 0 64.67 0.26 ; + END + END A_BIST_DIN[3] + PIN A_BM[28] + DIRECTION INPUT ; + USE SIGNAL ; + ANTENNAPARTIALMETALAREA 1.7264 LAYER Metal2 ; + ANTENNAMODEL OXIDE1 ; + ANTENNAGATEAREA 0.20085 LAYER Metal2 ; + ANTENNAMAXAREACAR 9.501618 LAYER Metal2 ; + PORT + LAYER Metal2 ; + RECT 646.32 0 646.58 0.26 ; + END + END A_BM[28] + PIN A_BM[3] + DIRECTION INPUT ; + USE SIGNAL ; + ANTENNAPARTIALMETALAREA 1.7264 LAYER Metal2 ; + ANTENNAMODEL OXIDE1 ; + ANTENNAGATEAREA 0.20085 LAYER Metal2 ; + ANTENNAMAXAREACAR 9.501618 LAYER Metal2 ; + PORT + LAYER Metal2 ; + RECT 56.25 0 56.51 0.26 ; + END + END A_BM[3] + PIN A_BIST_BM[28] + DIRECTION INPUT ; + USE SIGNAL ; + ANTENNAPARTIALMETALAREA 1.7602 LAYER Metal2 ; + ANTENNAMODEL OXIDE1 ; + ANTENNAGATEAREA 0.20085 LAYER Metal2 ; + ANTENNAMAXAREACAR 9.678367 LAYER Metal2 ; + PORT + LAYER Metal2 ; + RECT 644.945 0 645.205 0.26 ; + END + END A_BIST_BM[28] + PIN A_BIST_BM[3] + DIRECTION INPUT ; + USE SIGNAL ; + ANTENNAPARTIALMETALAREA 1.7602 LAYER Metal2 ; + ANTENNAMODEL OXIDE1 ; + ANTENNAGATEAREA 0.20085 LAYER Metal2 ; + ANTENNAMAXAREACAR 9.678367 LAYER Metal2 ; + PORT + LAYER Metal2 ; + RECT 57.625 0 57.885 0.26 ; + END + END A_BIST_BM[3] + PIN A_DOUT[28] + DIRECTION OUTPUT ; + USE SIGNAL ; + ANTENNAPARTIALMETALAREA 4.8256 LAYER Metal2 ; + ANTENNADIFFAREA 0.988 LAYER Metal2 ; + PORT + LAYER Metal2 ; + RECT 630.51 0 630.77 0.26 ; + END + END A_DOUT[28] + PIN A_DOUT[3] + DIRECTION OUTPUT ; + USE SIGNAL ; + ANTENNAPARTIALMETALAREA 4.8256 LAYER Metal2 ; + ANTENNADIFFAREA 0.988 LAYER Metal2 ; + PORT + LAYER Metal2 ; + RECT 72.06 0 72.32 0.26 ; + END + END A_DOUT[3] + PIN B_DIN[28] + DIRECTION INPUT ; + USE SIGNAL ; + ANTENNAPARTIALMETALAREA 2.925 LAYER Metal2 ; + ANTENNAMODEL OXIDE1 ; + ANTENNAGATEAREA 0.20085 LAYER Metal2 ; + ANTENNAMAXAREACAR 15.469256 LAYER Metal2 ; + PORT + LAYER Metal2 ; + RECT 640.2 0 640.46 0.26 ; + END + END B_DIN[28] + PIN B_DIN[3] + DIRECTION INPUT ; + USE SIGNAL ; + ANTENNAPARTIALMETALAREA 2.925 LAYER Metal2 ; + ANTENNAMODEL OXIDE1 ; + ANTENNAGATEAREA 0.20085 LAYER Metal2 ; + ANTENNAMAXAREACAR 15.469256 LAYER Metal2 ; + PORT + LAYER Metal2 ; + RECT 62.37 0 62.63 0.26 ; + END + END B_DIN[3] + PIN B_BIST_DIN[28] + DIRECTION INPUT ; + USE SIGNAL ; + ANTENNAPARTIALMETALAREA 2.9445 LAYER Metal2 ; + ANTENNAMODEL OXIDE1 ; + ANTENNAGATEAREA 0.20085 LAYER Metal2 ; + ANTENNAMAXAREACAR 15.929052 LAYER Metal2 ; + PORT + LAYER Metal2 ; + RECT 638.67 0 638.93 0.26 ; + END + END B_BIST_DIN[28] + PIN B_BIST_DIN[3] + DIRECTION INPUT ; + USE SIGNAL ; + ANTENNAPARTIALMETALAREA 2.9445 LAYER Metal2 ; + ANTENNAMODEL OXIDE1 ; + ANTENNAGATEAREA 0.20085 LAYER Metal2 ; + ANTENNAMAXAREACAR 15.929052 LAYER Metal2 ; + PORT + LAYER Metal2 ; + RECT 63.9 0 64.16 0.26 ; + END + END B_BIST_DIN[3] + PIN B_BM[28] + DIRECTION INPUT ; + USE SIGNAL ; + ANTENNAPARTIALMETALAREA 0.7007 LAYER Metal2 ; + ANTENNAMODEL OXIDE1 ; + ANTENNAGATEAREA 0.20085 LAYER Metal2 ; + ANTENNAMAXAREACAR 4.394822 LAYER Metal2 ; + PORT + LAYER Metal2 ; + RECT 631.685 0 631.945 0.26 ; + END + END B_BM[28] + PIN B_BM[3] + DIRECTION INPUT ; + USE SIGNAL ; + ANTENNAPARTIALMETALAREA 0.7007 LAYER Metal2 ; + ANTENNAMODEL OXIDE1 ; + ANTENNAGATEAREA 0.20085 LAYER Metal2 ; + ANTENNAMAXAREACAR 4.394822 LAYER Metal2 ; + PORT + LAYER Metal2 ; + RECT 70.885 0 71.145 0.26 ; + END + END B_BM[3] + PIN B_BIST_BM[28] + DIRECTION INPUT ; + USE SIGNAL ; + ANTENNAPARTIALMETALAREA 0.7007 LAYER Metal2 ; + ANTENNAMODEL OXIDE1 ; + ANTENNAGATEAREA 0.20085 LAYER Metal2 ; + ANTENNAMAXAREACAR 4.394822 LAYER Metal2 ; + PORT + LAYER Metal2 ; + RECT 633.215 0 633.475 0.26 ; + END + END B_BIST_BM[28] + PIN B_BIST_BM[3] + DIRECTION INPUT ; + USE SIGNAL ; + ANTENNAPARTIALMETALAREA 0.7007 LAYER Metal2 ; + ANTENNAMODEL OXIDE1 ; + ANTENNAGATEAREA 0.20085 LAYER Metal2 ; + ANTENNAMAXAREACAR 4.394822 LAYER Metal2 ; + PORT + LAYER Metal2 ; + RECT 69.355 0 69.615 0.26 ; + END + END B_BIST_BM[3] + PIN B_DOUT[28] + DIRECTION OUTPUT ; + USE SIGNAL ; + ANTENNAPARTIALMETALAREA 4.836 LAYER Metal2 ; + ANTENNADIFFAREA 0.988 LAYER Metal2 ; + PORT + LAYER Metal2 ; + RECT 647.34 0 647.6 0.26 ; + END + END B_DOUT[28] + PIN B_DOUT[3] + DIRECTION OUTPUT ; + USE SIGNAL ; + ANTENNAPARTIALMETALAREA 4.836 LAYER Metal2 ; + ANTENNADIFFAREA 0.988 LAYER Metal2 ; + PORT + LAYER Metal2 ; + RECT 55.23 0 55.49 0.26 ; + END + END B_DOUT[3] + PIN A_DIN[29] + DIRECTION INPUT ; + USE SIGNAL ; + ANTENNAPARTIALMETALAREA 3.9091 LAYER Metal2 ; + ANTENNAMODEL OXIDE1 ; + ANTENNAGATEAREA 0.20085 LAYER Metal2 ; + ANTENNAMAXAREACAR 20.368932 LAYER Metal2 ; + PORT + LAYER Metal2 ; + RECT 655.33 0 655.59 0.26 ; + END + END A_DIN[29] + PIN A_DIN[2] + DIRECTION INPUT ; + USE SIGNAL ; + ANTENNAPARTIALMETALAREA 3.9091 LAYER Metal2 ; + ANTENNAMODEL OXIDE1 ; + ANTENNAGATEAREA 0.20085 LAYER Metal2 ; + ANTENNAMAXAREACAR 20.368932 LAYER Metal2 ; + PORT + LAYER Metal2 ; + RECT 47.24 0 47.5 0.26 ; + END + END A_DIN[2] + PIN A_BIST_DIN[29] + DIRECTION INPUT ; + USE SIGNAL ; + ANTENNAPARTIALMETALAREA 4.136375 LAYER Metal2 ; + ANTENNAMODEL OXIDE1 ; + ANTENNAGATEAREA 0.20085 LAYER Metal2 ; + ANTENNAMAXAREACAR 21.874907 LAYER Metal2 ; + PORT + LAYER Metal2 ; + RECT 655.84 0 656.1 0.26 ; + END + END A_BIST_DIN[29] + PIN A_BIST_DIN[2] + DIRECTION INPUT ; + USE SIGNAL ; + ANTENNAPARTIALMETALAREA 4.136375 LAYER Metal2 ; + ANTENNAMODEL OXIDE1 ; + ANTENNAGATEAREA 0.20085 LAYER Metal2 ; + ANTENNAMAXAREACAR 21.874907 LAYER Metal2 ; + PORT + LAYER Metal2 ; + RECT 46.73 0 46.99 0.26 ; + END + END A_BIST_DIN[2] + PIN A_BM[29] + DIRECTION INPUT ; + USE SIGNAL ; + ANTENNAPARTIALMETALAREA 1.7264 LAYER Metal2 ; + ANTENNAMODEL OXIDE1 ; + ANTENNAGATEAREA 0.20085 LAYER Metal2 ; + ANTENNAMAXAREACAR 9.501618 LAYER Metal2 ; + PORT + LAYER Metal2 ; + RECT 664 0 664.26 0.26 ; + END + END A_BM[29] + PIN A_BM[2] + DIRECTION INPUT ; + USE SIGNAL ; + ANTENNAPARTIALMETALAREA 1.7264 LAYER Metal2 ; + ANTENNAMODEL OXIDE1 ; + ANTENNAGATEAREA 0.20085 LAYER Metal2 ; + ANTENNAMAXAREACAR 9.501618 LAYER Metal2 ; + PORT + LAYER Metal2 ; + RECT 38.57 0 38.83 0.26 ; + END + END A_BM[2] + PIN A_BIST_BM[29] + DIRECTION INPUT ; + USE SIGNAL ; + ANTENNAPARTIALMETALAREA 1.7602 LAYER Metal2 ; + ANTENNAMODEL OXIDE1 ; + ANTENNAGATEAREA 0.20085 LAYER Metal2 ; + ANTENNAMAXAREACAR 9.678367 LAYER Metal2 ; + PORT + LAYER Metal2 ; + RECT 662.625 0 662.885 0.26 ; + END + END A_BIST_BM[29] + PIN A_BIST_BM[2] + DIRECTION INPUT ; + USE SIGNAL ; + ANTENNAPARTIALMETALAREA 1.7602 LAYER Metal2 ; + ANTENNAMODEL OXIDE1 ; + ANTENNAGATEAREA 0.20085 LAYER Metal2 ; + ANTENNAMAXAREACAR 9.678367 LAYER Metal2 ; + PORT + LAYER Metal2 ; + RECT 39.945 0 40.205 0.26 ; + END + END A_BIST_BM[2] + PIN A_DOUT[29] + DIRECTION OUTPUT ; + USE SIGNAL ; + ANTENNAPARTIALMETALAREA 4.8256 LAYER Metal2 ; + ANTENNADIFFAREA 0.988 LAYER Metal2 ; + PORT + LAYER Metal2 ; + RECT 648.19 0 648.45 0.26 ; + END + END A_DOUT[29] + PIN A_DOUT[2] + DIRECTION OUTPUT ; + USE SIGNAL ; + ANTENNAPARTIALMETALAREA 4.8256 LAYER Metal2 ; + ANTENNADIFFAREA 0.988 LAYER Metal2 ; + PORT + LAYER Metal2 ; + RECT 54.38 0 54.64 0.26 ; + END + END A_DOUT[2] + PIN B_DIN[29] + DIRECTION INPUT ; + USE SIGNAL ; + ANTENNAPARTIALMETALAREA 2.925 LAYER Metal2 ; + ANTENNAMODEL OXIDE1 ; + ANTENNAGATEAREA 0.20085 LAYER Metal2 ; + ANTENNAMAXAREACAR 15.469256 LAYER Metal2 ; + PORT + LAYER Metal2 ; + RECT 657.88 0 658.14 0.26 ; + END + END B_DIN[29] + PIN B_DIN[2] + DIRECTION INPUT ; + USE SIGNAL ; + ANTENNAPARTIALMETALAREA 2.925 LAYER Metal2 ; + ANTENNAMODEL OXIDE1 ; + ANTENNAGATEAREA 0.20085 LAYER Metal2 ; + ANTENNAMAXAREACAR 15.469256 LAYER Metal2 ; + PORT + LAYER Metal2 ; + RECT 44.69 0 44.95 0.26 ; + END + END B_DIN[2] + PIN B_BIST_DIN[29] + DIRECTION INPUT ; + USE SIGNAL ; + ANTENNAPARTIALMETALAREA 2.9445 LAYER Metal2 ; + ANTENNAMODEL OXIDE1 ; + ANTENNAGATEAREA 0.20085 LAYER Metal2 ; + ANTENNAMAXAREACAR 15.929052 LAYER Metal2 ; + PORT + LAYER Metal2 ; + RECT 656.35 0 656.61 0.26 ; + END + END B_BIST_DIN[29] + PIN B_BIST_DIN[2] + DIRECTION INPUT ; + USE SIGNAL ; + ANTENNAPARTIALMETALAREA 2.9445 LAYER Metal2 ; + ANTENNAMODEL OXIDE1 ; + ANTENNAGATEAREA 0.20085 LAYER Metal2 ; + ANTENNAMAXAREACAR 15.929052 LAYER Metal2 ; + PORT + LAYER Metal2 ; + RECT 46.22 0 46.48 0.26 ; + END + END B_BIST_DIN[2] + PIN B_BM[29] + DIRECTION INPUT ; + USE SIGNAL ; + ANTENNAPARTIALMETALAREA 0.7007 LAYER Metal2 ; + ANTENNAMODEL OXIDE1 ; + ANTENNAGATEAREA 0.20085 LAYER Metal2 ; + ANTENNAMAXAREACAR 4.394822 LAYER Metal2 ; + PORT + LAYER Metal2 ; + RECT 649.365 0 649.625 0.26 ; + END + END B_BM[29] + PIN B_BM[2] + DIRECTION INPUT ; + USE SIGNAL ; + ANTENNAPARTIALMETALAREA 0.7007 LAYER Metal2 ; + ANTENNAMODEL OXIDE1 ; + ANTENNAGATEAREA 0.20085 LAYER Metal2 ; + ANTENNAMAXAREACAR 4.394822 LAYER Metal2 ; + PORT + LAYER Metal2 ; + RECT 53.205 0 53.465 0.26 ; + END + END B_BM[2] + PIN B_BIST_BM[29] + DIRECTION INPUT ; + USE SIGNAL ; + ANTENNAPARTIALMETALAREA 0.7007 LAYER Metal2 ; + ANTENNAMODEL OXIDE1 ; + ANTENNAGATEAREA 0.20085 LAYER Metal2 ; + ANTENNAMAXAREACAR 4.394822 LAYER Metal2 ; + PORT + LAYER Metal2 ; + RECT 650.895 0 651.155 0.26 ; + END + END B_BIST_BM[29] + PIN B_BIST_BM[2] + DIRECTION INPUT ; + USE SIGNAL ; + ANTENNAPARTIALMETALAREA 0.7007 LAYER Metal2 ; + ANTENNAMODEL OXIDE1 ; + ANTENNAGATEAREA 0.20085 LAYER Metal2 ; + ANTENNAMAXAREACAR 4.394822 LAYER Metal2 ; + PORT + LAYER Metal2 ; + RECT 51.675 0 51.935 0.26 ; + END + END B_BIST_BM[2] + PIN B_DOUT[29] + DIRECTION OUTPUT ; + USE SIGNAL ; + ANTENNAPARTIALMETALAREA 4.836 LAYER Metal2 ; + ANTENNADIFFAREA 0.988 LAYER Metal2 ; + PORT + LAYER Metal2 ; + RECT 665.02 0 665.28 0.26 ; + END + END B_DOUT[29] + PIN B_DOUT[2] + DIRECTION OUTPUT ; + USE SIGNAL ; + ANTENNAPARTIALMETALAREA 4.836 LAYER Metal2 ; + ANTENNADIFFAREA 0.988 LAYER Metal2 ; + PORT + LAYER Metal2 ; + RECT 37.55 0 37.81 0.26 ; + END + END B_DOUT[2] + PIN A_DIN[30] + DIRECTION INPUT ; + USE SIGNAL ; + ANTENNAPARTIALMETALAREA 3.9091 LAYER Metal2 ; + ANTENNAMODEL OXIDE1 ; + ANTENNAGATEAREA 0.20085 LAYER Metal2 ; + ANTENNAMAXAREACAR 20.368932 LAYER Metal2 ; + PORT + LAYER Metal2 ; + RECT 673.01 0 673.27 0.26 ; + END + END A_DIN[30] + PIN A_DIN[1] + DIRECTION INPUT ; + USE SIGNAL ; + ANTENNAPARTIALMETALAREA 3.9091 LAYER Metal2 ; + ANTENNAMODEL OXIDE1 ; + ANTENNAGATEAREA 0.20085 LAYER Metal2 ; + ANTENNAMAXAREACAR 20.368932 LAYER Metal2 ; + PORT + LAYER Metal2 ; + RECT 29.56 0 29.82 0.26 ; + END + END A_DIN[1] + PIN A_BIST_DIN[30] + DIRECTION INPUT ; + USE SIGNAL ; + ANTENNAPARTIALMETALAREA 4.136375 LAYER Metal2 ; + ANTENNAMODEL OXIDE1 ; + ANTENNAGATEAREA 0.20085 LAYER Metal2 ; + ANTENNAMAXAREACAR 21.874907 LAYER Metal2 ; + PORT + LAYER Metal2 ; + RECT 673.52 0 673.78 0.26 ; + END + END A_BIST_DIN[30] + PIN A_BIST_DIN[1] + DIRECTION INPUT ; + USE SIGNAL ; + ANTENNAPARTIALMETALAREA 4.136375 LAYER Metal2 ; + ANTENNAMODEL OXIDE1 ; + ANTENNAGATEAREA 0.20085 LAYER Metal2 ; + ANTENNAMAXAREACAR 21.874907 LAYER Metal2 ; + PORT + LAYER Metal2 ; + RECT 29.05 0 29.31 0.26 ; + END + END A_BIST_DIN[1] + PIN A_BM[30] + DIRECTION INPUT ; + USE SIGNAL ; + ANTENNAPARTIALMETALAREA 1.7264 LAYER Metal2 ; + ANTENNAMODEL OXIDE1 ; + ANTENNAGATEAREA 0.20085 LAYER Metal2 ; + ANTENNAMAXAREACAR 9.501618 LAYER Metal2 ; + PORT + LAYER Metal2 ; + RECT 681.68 0 681.94 0.26 ; + END + END A_BM[30] + PIN A_BM[1] + DIRECTION INPUT ; + USE SIGNAL ; + ANTENNAPARTIALMETALAREA 1.7264 LAYER Metal2 ; + ANTENNAMODEL OXIDE1 ; + ANTENNAGATEAREA 0.20085 LAYER Metal2 ; + ANTENNAMAXAREACAR 9.501618 LAYER Metal2 ; + PORT + LAYER Metal2 ; + RECT 20.89 0 21.15 0.26 ; + END + END A_BM[1] + PIN A_BIST_BM[30] + DIRECTION INPUT ; + USE SIGNAL ; + ANTENNAPARTIALMETALAREA 1.7602 LAYER Metal2 ; + ANTENNAMODEL OXIDE1 ; + ANTENNAGATEAREA 0.20085 LAYER Metal2 ; + ANTENNAMAXAREACAR 9.678367 LAYER Metal2 ; + PORT + LAYER Metal2 ; + RECT 680.305 0 680.565 0.26 ; + END + END A_BIST_BM[30] + PIN A_BIST_BM[1] + DIRECTION INPUT ; + USE SIGNAL ; + ANTENNAPARTIALMETALAREA 1.7602 LAYER Metal2 ; + ANTENNAMODEL OXIDE1 ; + ANTENNAGATEAREA 0.20085 LAYER Metal2 ; + ANTENNAMAXAREACAR 9.678367 LAYER Metal2 ; + PORT + LAYER Metal2 ; + RECT 22.265 0 22.525 0.26 ; + END + END A_BIST_BM[1] + PIN A_DOUT[30] + DIRECTION OUTPUT ; + USE SIGNAL ; + ANTENNAPARTIALMETALAREA 4.8256 LAYER Metal2 ; + ANTENNADIFFAREA 0.988 LAYER Metal2 ; + PORT + LAYER Metal2 ; + RECT 665.87 0 666.13 0.26 ; + END + END A_DOUT[30] + PIN A_DOUT[1] + DIRECTION OUTPUT ; + USE SIGNAL ; + ANTENNAPARTIALMETALAREA 4.8256 LAYER Metal2 ; + ANTENNADIFFAREA 0.988 LAYER Metal2 ; + PORT + LAYER Metal2 ; + RECT 36.7 0 36.96 0.26 ; + END + END A_DOUT[1] + PIN B_DIN[30] + DIRECTION INPUT ; + USE SIGNAL ; + ANTENNAPARTIALMETALAREA 2.925 LAYER Metal2 ; + ANTENNAMODEL OXIDE1 ; + ANTENNAGATEAREA 0.20085 LAYER Metal2 ; + ANTENNAMAXAREACAR 15.469256 LAYER Metal2 ; + PORT + LAYER Metal2 ; + RECT 675.56 0 675.82 0.26 ; + END + END B_DIN[30] + PIN B_DIN[1] + DIRECTION INPUT ; + USE SIGNAL ; + ANTENNAPARTIALMETALAREA 2.925 LAYER Metal2 ; + ANTENNAMODEL OXIDE1 ; + ANTENNAGATEAREA 0.20085 LAYER Metal2 ; + ANTENNAMAXAREACAR 15.469256 LAYER Metal2 ; + PORT + LAYER Metal2 ; + RECT 27.01 0 27.27 0.26 ; + END + END B_DIN[1] + PIN B_BIST_DIN[30] + DIRECTION INPUT ; + USE SIGNAL ; + ANTENNAPARTIALMETALAREA 2.9445 LAYER Metal2 ; + ANTENNAMODEL OXIDE1 ; + ANTENNAGATEAREA 0.20085 LAYER Metal2 ; + ANTENNAMAXAREACAR 15.929052 LAYER Metal2 ; + PORT + LAYER Metal2 ; + RECT 674.03 0 674.29 0.26 ; + END + END B_BIST_DIN[30] + PIN B_BIST_DIN[1] + DIRECTION INPUT ; + USE SIGNAL ; + ANTENNAPARTIALMETALAREA 2.9445 LAYER Metal2 ; + ANTENNAMODEL OXIDE1 ; + ANTENNAGATEAREA 0.20085 LAYER Metal2 ; + ANTENNAMAXAREACAR 15.929052 LAYER Metal2 ; + PORT + LAYER Metal2 ; + RECT 28.54 0 28.8 0.26 ; + END + END B_BIST_DIN[1] + PIN B_BM[30] + DIRECTION INPUT ; + USE SIGNAL ; + ANTENNAPARTIALMETALAREA 0.7007 LAYER Metal2 ; + ANTENNAMODEL OXIDE1 ; + ANTENNAGATEAREA 0.20085 LAYER Metal2 ; + ANTENNAMAXAREACAR 4.394822 LAYER Metal2 ; + PORT + LAYER Metal2 ; + RECT 667.045 0 667.305 0.26 ; + END + END B_BM[30] + PIN B_BM[1] + DIRECTION INPUT ; + USE SIGNAL ; + ANTENNAPARTIALMETALAREA 0.7007 LAYER Metal2 ; + ANTENNAMODEL OXIDE1 ; + ANTENNAGATEAREA 0.20085 LAYER Metal2 ; + ANTENNAMAXAREACAR 4.394822 LAYER Metal2 ; + PORT + LAYER Metal2 ; + RECT 35.525 0 35.785 0.26 ; + END + END B_BM[1] + PIN B_BIST_BM[30] + DIRECTION INPUT ; + USE SIGNAL ; + ANTENNAPARTIALMETALAREA 0.7007 LAYER Metal2 ; + ANTENNAMODEL OXIDE1 ; + ANTENNAGATEAREA 0.20085 LAYER Metal2 ; + ANTENNAMAXAREACAR 4.394822 LAYER Metal2 ; + PORT + LAYER Metal2 ; + RECT 668.575 0 668.835 0.26 ; + END + END B_BIST_BM[30] + PIN B_BIST_BM[1] + DIRECTION INPUT ; + USE SIGNAL ; + ANTENNAPARTIALMETALAREA 0.7007 LAYER Metal2 ; + ANTENNAMODEL OXIDE1 ; + ANTENNAGATEAREA 0.20085 LAYER Metal2 ; + ANTENNAMAXAREACAR 4.394822 LAYER Metal2 ; + PORT + LAYER Metal2 ; + RECT 33.995 0 34.255 0.26 ; + END + END B_BIST_BM[1] + PIN B_DOUT[30] + DIRECTION OUTPUT ; + USE SIGNAL ; + ANTENNAPARTIALMETALAREA 4.836 LAYER Metal2 ; + ANTENNADIFFAREA 0.988 LAYER Metal2 ; + PORT + LAYER Metal2 ; + RECT 682.7 0 682.96 0.26 ; + END + END B_DOUT[30] + PIN B_DOUT[1] + DIRECTION OUTPUT ; + USE SIGNAL ; + ANTENNAPARTIALMETALAREA 4.836 LAYER Metal2 ; + ANTENNADIFFAREA 0.988 LAYER Metal2 ; + PORT + LAYER Metal2 ; + RECT 19.87 0 20.13 0.26 ; + END + END B_DOUT[1] + PIN A_DIN[31] + DIRECTION INPUT ; + USE SIGNAL ; + ANTENNAPARTIALMETALAREA 3.9091 LAYER Metal2 ; + ANTENNAMODEL OXIDE1 ; + ANTENNAGATEAREA 0.20085 LAYER Metal2 ; + ANTENNAMAXAREACAR 20.368932 LAYER Metal2 ; + PORT + LAYER Metal2 ; + RECT 690.69 0 690.95 0.26 ; + END + END A_DIN[31] + PIN A_DIN[0] + DIRECTION INPUT ; + USE SIGNAL ; + ANTENNAPARTIALMETALAREA 3.9091 LAYER Metal2 ; + ANTENNAMODEL OXIDE1 ; + ANTENNAGATEAREA 0.20085 LAYER Metal2 ; + ANTENNAMAXAREACAR 20.368932 LAYER Metal2 ; + PORT + LAYER Metal2 ; + RECT 11.88 0 12.14 0.26 ; + END + END A_DIN[0] + PIN A_BIST_DIN[31] + DIRECTION INPUT ; + USE SIGNAL ; + ANTENNAPARTIALMETALAREA 4.136375 LAYER Metal2 ; + ANTENNAMODEL OXIDE1 ; + ANTENNAGATEAREA 0.20085 LAYER Metal2 ; + ANTENNAMAXAREACAR 21.874907 LAYER Metal2 ; + PORT + LAYER Metal2 ; + RECT 691.2 0 691.46 0.26 ; + END + END A_BIST_DIN[31] + PIN A_BIST_DIN[0] + DIRECTION INPUT ; + USE SIGNAL ; + ANTENNAPARTIALMETALAREA 4.136375 LAYER Metal2 ; + ANTENNAMODEL OXIDE1 ; + ANTENNAGATEAREA 0.20085 LAYER Metal2 ; + ANTENNAMAXAREACAR 21.874907 LAYER Metal2 ; + PORT + LAYER Metal2 ; + RECT 11.37 0 11.63 0.26 ; + END + END A_BIST_DIN[0] + PIN A_BM[31] + DIRECTION INPUT ; + USE SIGNAL ; + ANTENNAPARTIALMETALAREA 1.7264 LAYER Metal2 ; + ANTENNAMODEL OXIDE1 ; + ANTENNAGATEAREA 0.20085 LAYER Metal2 ; + ANTENNAMAXAREACAR 9.501618 LAYER Metal2 ; + PORT + LAYER Metal2 ; + RECT 699.36 0 699.62 0.26 ; + END + END A_BM[31] + PIN A_BM[0] + DIRECTION INPUT ; + USE SIGNAL ; + ANTENNAPARTIALMETALAREA 1.7264 LAYER Metal2 ; + ANTENNAMODEL OXIDE1 ; + ANTENNAGATEAREA 0.20085 LAYER Metal2 ; + ANTENNAMAXAREACAR 9.501618 LAYER Metal2 ; + PORT + LAYER Metal2 ; + RECT 3.21 0 3.47 0.26 ; + END + END A_BM[0] + PIN A_BIST_BM[31] + DIRECTION INPUT ; + USE SIGNAL ; + ANTENNAPARTIALMETALAREA 1.7602 LAYER Metal2 ; + ANTENNAMODEL OXIDE1 ; + ANTENNAGATEAREA 0.20085 LAYER Metal2 ; + ANTENNAMAXAREACAR 9.678367 LAYER Metal2 ; + PORT + LAYER Metal2 ; + RECT 697.985 0 698.245 0.26 ; + END + END A_BIST_BM[31] + PIN A_BIST_BM[0] + DIRECTION INPUT ; + USE SIGNAL ; + ANTENNAPARTIALMETALAREA 1.7602 LAYER Metal2 ; + ANTENNAMODEL OXIDE1 ; + ANTENNAGATEAREA 0.20085 LAYER Metal2 ; + ANTENNAMAXAREACAR 9.678367 LAYER Metal2 ; + PORT + LAYER Metal2 ; + RECT 4.585 0 4.845 0.26 ; + END + END A_BIST_BM[0] + PIN A_DOUT[31] + DIRECTION OUTPUT ; + USE SIGNAL ; + ANTENNAPARTIALMETALAREA 4.8256 LAYER Metal2 ; + ANTENNADIFFAREA 0.988 LAYER Metal2 ; + PORT + LAYER Metal2 ; + RECT 683.55 0 683.81 0.26 ; + END + END A_DOUT[31] + PIN A_DOUT[0] + DIRECTION OUTPUT ; + USE SIGNAL ; + ANTENNAPARTIALMETALAREA 4.8256 LAYER Metal2 ; + ANTENNADIFFAREA 0.988 LAYER Metal2 ; + PORT + LAYER Metal2 ; + RECT 19.02 0 19.28 0.26 ; + END + END A_DOUT[0] + PIN B_DIN[31] + DIRECTION INPUT ; + USE SIGNAL ; + ANTENNAPARTIALMETALAREA 2.925 LAYER Metal2 ; + ANTENNAMODEL OXIDE1 ; + ANTENNAGATEAREA 0.20085 LAYER Metal2 ; + ANTENNAMAXAREACAR 15.469256 LAYER Metal2 ; + PORT + LAYER Metal2 ; + RECT 693.24 0 693.5 0.26 ; + END + END B_DIN[31] + PIN B_DIN[0] + DIRECTION INPUT ; + USE SIGNAL ; + ANTENNAPARTIALMETALAREA 2.925 LAYER Metal2 ; + ANTENNAMODEL OXIDE1 ; + ANTENNAGATEAREA 0.20085 LAYER Metal2 ; + ANTENNAMAXAREACAR 15.469256 LAYER Metal2 ; + PORT + LAYER Metal2 ; + RECT 9.33 0 9.59 0.26 ; + END + END B_DIN[0] + PIN B_BIST_DIN[31] + DIRECTION INPUT ; + USE SIGNAL ; + ANTENNAPARTIALMETALAREA 2.9445 LAYER Metal2 ; + ANTENNAMODEL OXIDE1 ; + ANTENNAGATEAREA 0.20085 LAYER Metal2 ; + ANTENNAMAXAREACAR 15.929052 LAYER Metal2 ; + PORT + LAYER Metal2 ; + RECT 691.71 0 691.97 0.26 ; + END + END B_BIST_DIN[31] + PIN B_BIST_DIN[0] + DIRECTION INPUT ; + USE SIGNAL ; + ANTENNAPARTIALMETALAREA 2.9445 LAYER Metal2 ; + ANTENNAMODEL OXIDE1 ; + ANTENNAGATEAREA 0.20085 LAYER Metal2 ; + ANTENNAMAXAREACAR 15.929052 LAYER Metal2 ; + PORT + LAYER Metal2 ; + RECT 10.86 0 11.12 0.26 ; + END + END B_BIST_DIN[0] + PIN B_BM[31] + DIRECTION INPUT ; + USE SIGNAL ; + ANTENNAPARTIALMETALAREA 0.7007 LAYER Metal2 ; + ANTENNAMODEL OXIDE1 ; + ANTENNAGATEAREA 0.20085 LAYER Metal2 ; + ANTENNAMAXAREACAR 4.394822 LAYER Metal2 ; + PORT + LAYER Metal2 ; + RECT 684.725 0 684.985 0.26 ; + END + END B_BM[31] + PIN B_BM[0] + DIRECTION INPUT ; + USE SIGNAL ; + ANTENNAPARTIALMETALAREA 0.7007 LAYER Metal2 ; + ANTENNAMODEL OXIDE1 ; + ANTENNAGATEAREA 0.20085 LAYER Metal2 ; + ANTENNAMAXAREACAR 4.394822 LAYER Metal2 ; + PORT + LAYER Metal2 ; + RECT 17.845 0 18.105 0.26 ; + END + END B_BM[0] + PIN B_BIST_BM[31] + DIRECTION INPUT ; + USE SIGNAL ; + ANTENNAPARTIALMETALAREA 0.7007 LAYER Metal2 ; + ANTENNAMODEL OXIDE1 ; + ANTENNAGATEAREA 0.20085 LAYER Metal2 ; + ANTENNAMAXAREACAR 4.394822 LAYER Metal2 ; + PORT + LAYER Metal2 ; + RECT 686.255 0 686.515 0.26 ; + END + END B_BIST_BM[31] + PIN B_BIST_BM[0] + DIRECTION INPUT ; + USE SIGNAL ; + ANTENNAPARTIALMETALAREA 0.7007 LAYER Metal2 ; + ANTENNAMODEL OXIDE1 ; + ANTENNAGATEAREA 0.20085 LAYER Metal2 ; + ANTENNAMAXAREACAR 4.394822 LAYER Metal2 ; + PORT + LAYER Metal2 ; + RECT 16.315 0 16.575 0.26 ; + END + END B_BIST_BM[0] + PIN B_DOUT[31] + DIRECTION OUTPUT ; + USE SIGNAL ; + ANTENNAPARTIALMETALAREA 4.836 LAYER Metal2 ; + ANTENNADIFFAREA 0.988 LAYER Metal2 ; + PORT + LAYER Metal2 ; + RECT 700.38 0 700.64 0.26 ; + END + END B_DOUT[31] + PIN B_DOUT[0] + DIRECTION OUTPUT ; + USE SIGNAL ; + ANTENNAPARTIALMETALAREA 4.836 LAYER Metal2 ; + ANTENNADIFFAREA 0.988 LAYER Metal2 ; + PORT + LAYER Metal2 ; + RECT 2.19 0 2.45 0.26 ; + END + END B_DOUT[0] + PIN A_ADDR[0] + DIRECTION INPUT ; + USE SIGNAL ; + ANTENNAPARTIALMETALAREA 8.7685 LAYER Metal2 ; + ANTENNAMODEL OXIDE1 ; + ANTENNAGATEAREA 0.20085 LAYER Metal2 ; + ANTENNAMAXAREACAR 44.563107 LAYER Metal2 ; + PORT + LAYER Metal2 ; + RECT 367.505 0 367.765 0.26 ; + END + END A_ADDR[0] + PIN A_BIST_ADDR[0] + DIRECTION INPUT ; + USE SIGNAL ; + ANTENNAPARTIALMETALAREA 9.8293 LAYER Metal2 ; + ANTENNAMODEL OXIDE1 ; + ANTENNAGATEAREA 0.20085 LAYER Metal2 ; + ANTENNAMAXAREACAR 49.84466 LAYER Metal2 ; + PORT + LAYER Metal2 ; + RECT 373.115 0 373.375 0.26 ; + END + END A_BIST_ADDR[0] + PIN B_ADDR[0] + DIRECTION INPUT ; + USE SIGNAL ; + ANTENNAPARTIALMETALAREA 8.7685 LAYER Metal2 ; + ANTENNAMODEL OXIDE1 ; + ANTENNAGATEAREA 0.20085 LAYER Metal2 ; + ANTENNAMAXAREACAR 44.563107 LAYER Metal2 ; + PORT + LAYER Metal2 ; + RECT 335.065 0 335.325 0.26 ; + END + END B_ADDR[0] + PIN B_BIST_ADDR[0] + DIRECTION INPUT ; + USE SIGNAL ; + ANTENNAPARTIALMETALAREA 9.8293 LAYER Metal2 ; + ANTENNAMODEL OXIDE1 ; + ANTENNAGATEAREA 0.20085 LAYER Metal2 ; + ANTENNAMAXAREACAR 49.84466 LAYER Metal2 ; + PORT + LAYER Metal2 ; + RECT 329.455 0 329.715 0.26 ; + END + END B_BIST_ADDR[0] + PIN A_ADDR[1] + DIRECTION INPUT ; + USE SIGNAL ; + ANTENNAPARTIALMETALAREA 11.0851 LAYER Metal2 ; + ANTENNAMODEL OXIDE1 ; + ANTENNAGATEAREA 0.20085 LAYER Metal2 ; + ANTENNAMAXAREACAR 56.097087 LAYER Metal2 ; + PORT + LAYER Metal2 ; + RECT 368.015 0 368.275 0.26 ; + END + END A_ADDR[1] + PIN A_BIST_ADDR[1] + DIRECTION INPUT ; + USE SIGNAL ; + ANTENNAPARTIALMETALAREA 12.1459 LAYER Metal2 ; + ANTENNAMODEL OXIDE1 ; + ANTENNAGATEAREA 0.20085 LAYER Metal2 ; + ANTENNAMAXAREACAR 61.378641 LAYER Metal2 ; + PORT + LAYER Metal2 ; + RECT 373.625 0 373.885 0.26 ; + END + END A_BIST_ADDR[1] + PIN B_ADDR[1] + DIRECTION INPUT ; + USE SIGNAL ; + ANTENNAPARTIALMETALAREA 11.0851 LAYER Metal2 ; + ANTENNAMODEL OXIDE1 ; + ANTENNAGATEAREA 0.20085 LAYER Metal2 ; + ANTENNAMAXAREACAR 56.097087 LAYER Metal2 ; + PORT + LAYER Metal2 ; + RECT 334.555 0 334.815 0.26 ; + END + END B_ADDR[1] + PIN B_BIST_ADDR[1] + DIRECTION INPUT ; + USE SIGNAL ; + ANTENNAPARTIALMETALAREA 12.1459 LAYER Metal2 ; + ANTENNAMODEL OXIDE1 ; + ANTENNAGATEAREA 0.20085 LAYER Metal2 ; + ANTENNAMAXAREACAR 61.378641 LAYER Metal2 ; + PORT + LAYER Metal2 ; + RECT 328.945 0 329.205 0.26 ; + END + END B_BIST_ADDR[1] + PIN A_ADDR[2] + DIRECTION INPUT ; + USE SIGNAL ; + ANTENNAPARTIALMETALAREA 13.0819 LAYER Metal2 ; + ANTENNAPARTIALMETALAREA 1.5246 LAYER Metal3 ; + ANTENNAPARTIALCUTAREA 0.0722 LAYER Via2 ; + ANTENNAMODEL OXIDE1 ; + ANTENNAGATEAREA 0.20085 LAYER Metal3 ; + ANTENNAMAXAREACAR 9.415982 LAYER Metal3 ; + PORT + LAYER Metal2 ; + RECT 376.685 0 376.945 0.26 ; + END + END A_ADDR[2] + PIN A_BIST_ADDR[2] + DIRECTION INPUT ; + USE SIGNAL ; + ANTENNAPARTIALMETALAREA 13.0819 LAYER Metal2 ; + ANTENNAPARTIALMETALAREA 1.0962 LAYER Metal3 ; + ANTENNAPARTIALCUTAREA 0.0722 LAYER Via2 ; + ANTENNAMODEL OXIDE1 ; + ANTENNAGATEAREA 0.20085 LAYER Metal3 ; + ANTENNAMAXAREACAR 7.813791 LAYER Metal3 ; + PORT + LAYER Metal2 ; + RECT 377.195 0 377.455 0.26 ; + END + END A_BIST_ADDR[2] + PIN B_ADDR[2] + DIRECTION INPUT ; + USE SIGNAL ; + ANTENNAPARTIALMETALAREA 13.0819 LAYER Metal2 ; + ANTENNAPARTIALMETALAREA 1.5246 LAYER Metal3 ; + ANTENNAPARTIALCUTAREA 0.0722 LAYER Via2 ; + ANTENNAMODEL OXIDE1 ; + ANTENNAGATEAREA 0.20085 LAYER Metal3 ; + ANTENNAMAXAREACAR 9.415982 LAYER Metal3 ; + PORT + LAYER Metal2 ; + RECT 325.885 0 326.145 0.26 ; + END + END B_ADDR[2] + PIN B_BIST_ADDR[2] + DIRECTION INPUT ; + USE SIGNAL ; + ANTENNAPARTIALMETALAREA 13.0819 LAYER Metal2 ; + ANTENNAPARTIALMETALAREA 1.0962 LAYER Metal3 ; + ANTENNAPARTIALCUTAREA 0.0722 LAYER Via2 ; + ANTENNAMODEL OXIDE1 ; + ANTENNAGATEAREA 0.20085 LAYER Metal3 ; + ANTENNAMAXAREACAR 7.813791 LAYER Metal3 ; + PORT + LAYER Metal2 ; + RECT 325.375 0 325.635 0.26 ; + END + END B_BIST_ADDR[2] + PIN A_ADDR[3] + DIRECTION INPUT ; + USE SIGNAL ; + ANTENNAPARTIALMETALAREA 13.0819 LAYER Metal2 ; + ANTENNAPARTIALMETALAREA 3.9459 LAYER Metal3 ; + ANTENNAPARTIALCUTAREA 0.0722 LAYER Via2 ; + ANTENNAMODEL OXIDE1 ; + ANTENNAGATEAREA 0.20085 LAYER Metal3 ; + ANTENNAMAXAREACAR 21.471247 LAYER Metal3 ; + PORT + LAYER Metal2 ; + RECT 375.665 0 375.925 0.26 ; + END + END A_ADDR[3] + PIN A_BIST_ADDR[3] + DIRECTION INPUT ; + USE SIGNAL ; + ANTENNAPARTIALMETALAREA 13.0819 LAYER Metal2 ; + ANTENNAPARTIALMETALAREA 3.7317 LAYER Metal3 ; + ANTENNAPARTIALCUTAREA 0.0722 LAYER Via2 ; + ANTENNAMODEL OXIDE1 ; + ANTENNAGATEAREA 0.20085 LAYER Metal3 ; + ANTENNAMAXAREACAR 20.935524 LAYER Metal3 ; + PORT + LAYER Metal2 ; + RECT 376.175 0 376.435 0.26 ; + END + END A_BIST_ADDR[3] + PIN B_ADDR[3] + DIRECTION INPUT ; + USE SIGNAL ; + ANTENNAPARTIALMETALAREA 13.0819 LAYER Metal2 ; + ANTENNAPARTIALMETALAREA 3.9459 LAYER Metal3 ; + ANTENNAPARTIALCUTAREA 0.0722 LAYER Via2 ; + ANTENNAMODEL OXIDE1 ; + ANTENNAGATEAREA 0.20085 LAYER Metal3 ; + ANTENNAMAXAREACAR 21.471247 LAYER Metal3 ; + PORT + LAYER Metal2 ; + RECT 326.905 0 327.165 0.26 ; + END + END B_ADDR[3] + PIN B_BIST_ADDR[3] + DIRECTION INPUT ; + USE SIGNAL ; + ANTENNAPARTIALMETALAREA 13.0819 LAYER Metal2 ; + ANTENNAPARTIALMETALAREA 3.7317 LAYER Metal3 ; + ANTENNAPARTIALCUTAREA 0.0722 LAYER Via2 ; + ANTENNAMODEL OXIDE1 ; + ANTENNAGATEAREA 0.20085 LAYER Metal3 ; + ANTENNAMAXAREACAR 20.935524 LAYER Metal3 ; + PORT + LAYER Metal2 ; + RECT 326.395 0 326.655 0.26 ; + END + END B_BIST_ADDR[3] + PIN A_ADDR[4] + DIRECTION INPUT ; + USE SIGNAL ; + ANTENNAPARTIALMETALAREA 14.7329 LAYER Metal2 ; + ANTENNAMODEL OXIDE1 ; + ANTENNAGATEAREA 0.20085 LAYER Metal2 ; + ANTENNAMAXAREACAR 74.2589 LAYER Metal2 ; + PORT + LAYER Metal2 ; + RECT 356.285 0 356.545 0.26 ; + END + END A_ADDR[4] + PIN A_BIST_ADDR[4] + DIRECTION INPUT ; + USE SIGNAL ; + ANTENNAPARTIALMETALAREA 14.4677 LAYER Metal2 ; + ANTENNAMODEL OXIDE1 ; + ANTENNAGATEAREA 0.20085 LAYER Metal2 ; + ANTENNAMAXAREACAR 72.938511 LAYER Metal2 ; + PORT + LAYER Metal2 ; + RECT 356.795 0 357.055 0.26 ; + END + END A_BIST_ADDR[4] + PIN B_ADDR[4] + DIRECTION INPUT ; + USE SIGNAL ; + ANTENNAPARTIALMETALAREA 14.7329 LAYER Metal2 ; + ANTENNAMODEL OXIDE1 ; + ANTENNAGATEAREA 0.20085 LAYER Metal2 ; + ANTENNAMAXAREACAR 74.2589 LAYER Metal2 ; + PORT + LAYER Metal2 ; + RECT 346.285 0 346.545 0.26 ; + END + END B_ADDR[4] + PIN B_BIST_ADDR[4] + DIRECTION INPUT ; + USE SIGNAL ; + ANTENNAPARTIALMETALAREA 14.4677 LAYER Metal2 ; + ANTENNAMODEL OXIDE1 ; + ANTENNAGATEAREA 0.20085 LAYER Metal2 ; + ANTENNAMAXAREACAR 72.938511 LAYER Metal2 ; + PORT + LAYER Metal2 ; + RECT 345.775 0 346.035 0.26 ; + END + END B_BIST_ADDR[4] + PIN A_ADDR[5] + DIRECTION INPUT ; + USE SIGNAL ; + ANTENNAPARTIALMETALAREA 13.2691 LAYER Metal2 ; + ANTENNAMODEL OXIDE1 ; + ANTENNAGATEAREA 0.20085 LAYER Metal2 ; + ANTENNAMAXAREACAR 66.970874 LAYER Metal2 ; + PORT + LAYER Metal2 ; + RECT 355.265 0 355.525 0.26 ; + END + END A_ADDR[5] + PIN A_BIST_ADDR[5] + DIRECTION INPUT ; + USE SIGNAL ; + ANTENNAPARTIALMETALAREA 12.9937 LAYER Metal2 ; + ANTENNAMODEL OXIDE1 ; + ANTENNAGATEAREA 0.20085 LAYER Metal2 ; + ANTENNAMAXAREACAR 65.599701 LAYER Metal2 ; + PORT + LAYER Metal2 ; + RECT 355.775 0 356.035 0.26 ; + END + END A_BIST_ADDR[5] + PIN B_ADDR[5] + DIRECTION INPUT ; + USE SIGNAL ; + ANTENNAPARTIALMETALAREA 13.2691 LAYER Metal2 ; + ANTENNAMODEL OXIDE1 ; + ANTENNAGATEAREA 0.20085 LAYER Metal2 ; + ANTENNAMAXAREACAR 66.970874 LAYER Metal2 ; + PORT + LAYER Metal2 ; + RECT 347.305 0 347.565 0.26 ; + END + END B_ADDR[5] + PIN B_BIST_ADDR[5] + DIRECTION INPUT ; + USE SIGNAL ; + ANTENNAPARTIALMETALAREA 12.9937 LAYER Metal2 ; + ANTENNAMODEL OXIDE1 ; + ANTENNAGATEAREA 0.20085 LAYER Metal2 ; + ANTENNAMAXAREACAR 65.599701 LAYER Metal2 ; + PORT + LAYER Metal2 ; + RECT 346.795 0 347.055 0.26 ; + END + END B_BIST_ADDR[5] + PIN A_ADDR[6] + DIRECTION INPUT ; + USE SIGNAL ; + ANTENNAPARTIALMETALAREA 14.3819 LAYER Metal2 ; + ANTENNAMODEL OXIDE1 ; + ANTENNAGATEAREA 0.20085 LAYER Metal2 ; + ANTENNAMAXAREACAR 72.511327 LAYER Metal2 ; + PORT + LAYER Metal2 ; + RECT 379.235 0 379.495 0.26 ; + END + END A_ADDR[6] + PIN A_BIST_ADDR[6] + DIRECTION INPUT ; + USE SIGNAL ; + ANTENNAPARTIALMETALAREA 14.1167 LAYER Metal2 ; + ANTENNAMODEL OXIDE1 ; + ANTENNAGATEAREA 0.20085 LAYER Metal2 ; + ANTENNAMAXAREACAR 71.190939 LAYER Metal2 ; + PORT + LAYER Metal2 ; + RECT 378.725 0 378.985 0.26 ; + END + END A_BIST_ADDR[6] + PIN B_ADDR[6] + DIRECTION INPUT ; + USE SIGNAL ; + ANTENNAPARTIALMETALAREA 14.3819 LAYER Metal2 ; + ANTENNAMODEL OXIDE1 ; + ANTENNAGATEAREA 0.20085 LAYER Metal2 ; + ANTENNAMAXAREACAR 72.511327 LAYER Metal2 ; + PORT + LAYER Metal2 ; + RECT 323.335 0 323.595 0.26 ; + END + END B_ADDR[6] + PIN B_BIST_ADDR[6] + DIRECTION INPUT ; + USE SIGNAL ; + ANTENNAPARTIALMETALAREA 14.1167 LAYER Metal2 ; + ANTENNAMODEL OXIDE1 ; + ANTENNAGATEAREA 0.20085 LAYER Metal2 ; + ANTENNAMAXAREACAR 71.190939 LAYER Metal2 ; + PORT + LAYER Metal2 ; + RECT 323.845 0 324.105 0.26 ; + END + END B_BIST_ADDR[6] + PIN A_ADDR[7] + DIRECTION INPUT ; + USE SIGNAL ; + ANTENNAPARTIALMETALAREA 16.3761 LAYER Metal2 ; + ANTENNAMODEL OXIDE1 ; + ANTENNAGATEAREA 0.20085 LAYER Metal2 ; + ANTENNAMAXAREACAR 82.440129 LAYER Metal2 ; + PORT + LAYER Metal2 ; + RECT 378.215 0 378.475 0.26 ; + END + END A_ADDR[7] + PIN A_BIST_ADDR[7] + DIRECTION INPUT ; + USE SIGNAL ; + ANTENNAPARTIALMETALAREA 16.1109 LAYER Metal2 ; + ANTENNAMODEL OXIDE1 ; + ANTENNAGATEAREA 0.20085 LAYER Metal2 ; + ANTENNAMAXAREACAR 81.119741 LAYER Metal2 ; + PORT + LAYER Metal2 ; + RECT 377.705 0 377.965 0.26 ; + END + END A_BIST_ADDR[7] + PIN B_ADDR[7] + DIRECTION INPUT ; + USE SIGNAL ; + ANTENNAPARTIALMETALAREA 16.3761 LAYER Metal2 ; + ANTENNAMODEL OXIDE1 ; + ANTENNAGATEAREA 0.20085 LAYER Metal2 ; + ANTENNAMAXAREACAR 82.440129 LAYER Metal2 ; + PORT + LAYER Metal2 ; + RECT 324.355 0 324.615 0.26 ; + END + END B_ADDR[7] + PIN B_BIST_ADDR[7] + DIRECTION INPUT ; + USE SIGNAL ; + ANTENNAPARTIALMETALAREA 16.1109 LAYER Metal2 ; + ANTENNAMODEL OXIDE1 ; + ANTENNAGATEAREA 0.20085 LAYER Metal2 ; + ANTENNAMAXAREACAR 81.119741 LAYER Metal2 ; + PORT + LAYER Metal2 ; + RECT 324.865 0 325.125 0.26 ; + END + END B_BIST_ADDR[7] + PIN A_CLK + DIRECTION INPUT ; + USE SIGNAL ; + ANTENNAPARTIALMETALAREA 4.0547 LAYER Metal2 ; + ANTENNAMODEL OXIDE1 ; + ANTENNAGATEAREA 0.20085 LAYER Metal2 ; + ANTENNAMAXAREACAR 21.093851 LAYER Metal2 ; + PORT + LAYER Metal2 ; + RECT 365.975 0 366.235 0.26 ; + END + END A_CLK + PIN A_REN + DIRECTION INPUT ; + USE SIGNAL ; + ANTENNAPARTIALMETALAREA 3.98465 LAYER Metal2 ; + ANTENNAMODEL OXIDE1 ; + ANTENNAGATEAREA 0.20085 LAYER Metal2 ; + ANTENNAMAXAREACAR 20.745083 LAYER Metal2 ; + PORT + LAYER Metal2 ; + RECT 369.545 0 369.805 0.26 ; + END + END A_REN + PIN A_WEN + DIRECTION INPUT ; + USE SIGNAL ; + ANTENNAPARTIALMETALAREA 2.8847 LAYER Metal2 ; + ANTENNAMODEL OXIDE1 ; + ANTENNAGATEAREA 0.20085 LAYER Metal2 ; + ANTENNAMAXAREACAR 15.268608 LAYER Metal2 ; + PORT + LAYER Metal2 ; + RECT 369.035 0 369.295 0.26 ; + END + END A_WEN + PIN A_MEN + DIRECTION INPUT ; + USE SIGNAL ; + ANTENNAPARTIALMETALAREA 3.0247 LAYER Metal2 ; + ANTENNAMODEL OXIDE1 ; + ANTENNAGATEAREA 0.20085 LAYER Metal2 ; + ANTENNAMAXAREACAR 15.965646 LAYER Metal2 ; + PORT + LAYER Metal2 ; + RECT 366.485 0 366.745 0.26 ; + END + END A_MEN + PIN A_DLY + DIRECTION INPUT ; + USE SIGNAL ; + ANTENNAPARTIALMETALAREA 7.7792 LAYER Metal2 ; + ANTENNAMODEL OXIDE1 ; + ANTENNAGATEAREA 0.3367 LAYER Metal2 ; + ANTENNAMAXAREACAR 23.644788 LAYER Metal2 ; + PORT + LAYER Metal2 ; + RECT 386.885 0 387.145 0.26 ; + END + END A_DLY + PIN B_CLK + DIRECTION INPUT ; + USE SIGNAL ; + ANTENNAPARTIALMETALAREA 4.0547 LAYER Metal2 ; + ANTENNAMODEL OXIDE1 ; + ANTENNAGATEAREA 0.20085 LAYER Metal2 ; + ANTENNAMAXAREACAR 21.093851 LAYER Metal2 ; + PORT + LAYER Metal2 ; + RECT 336.595 0 336.855 0.26 ; + END + END B_CLK + PIN B_REN + DIRECTION INPUT ; + USE SIGNAL ; + ANTENNAPARTIALMETALAREA 3.98465 LAYER Metal2 ; + ANTENNAMODEL OXIDE1 ; + ANTENNAGATEAREA 0.20085 LAYER Metal2 ; + ANTENNAMAXAREACAR 20.745083 LAYER Metal2 ; + PORT + LAYER Metal2 ; + RECT 333.025 0 333.285 0.26 ; + END + END B_REN + PIN B_WEN + DIRECTION INPUT ; + USE SIGNAL ; + ANTENNAPARTIALMETALAREA 2.8847 LAYER Metal2 ; + ANTENNAMODEL OXIDE1 ; + ANTENNAGATEAREA 0.20085 LAYER Metal2 ; + ANTENNAMAXAREACAR 15.268608 LAYER Metal2 ; + PORT + LAYER Metal2 ; + RECT 333.535 0 333.795 0.26 ; + END + END B_WEN + PIN B_MEN + DIRECTION INPUT ; + USE SIGNAL ; + ANTENNAPARTIALMETALAREA 3.0247 LAYER Metal2 ; + ANTENNAMODEL OXIDE1 ; + ANTENNAGATEAREA 0.20085 LAYER Metal2 ; + ANTENNAMAXAREACAR 15.965646 LAYER Metal2 ; + PORT + LAYER Metal2 ; + RECT 336.085 0 336.345 0.26 ; + END + END B_MEN + PIN B_DLY + DIRECTION INPUT ; + USE SIGNAL ; + ANTENNAPARTIALMETALAREA 7.7792 LAYER Metal2 ; + ANTENNAMODEL OXIDE1 ; + ANTENNAGATEAREA 0.3367 LAYER Metal2 ; + ANTENNAMAXAREACAR 23.644788 LAYER Metal2 ; + PORT + LAYER Metal2 ; + RECT 315.685 0 315.945 0.26 ; + END + END B_DLY + PIN A_BIST_EN + DIRECTION INPUT ; + USE SIGNAL ; + ANTENNAPARTIALMETALAREA 4.0634 LAYER Metal2 ; + ANTENNAPARTIALMETALAREA 258.2003 LAYER Metal3 ; + ANTENNAPARTIALCUTAREA 0.0722 LAYER Via2 ; + ANTENNAMODEL OXIDE1 ; + ANTENNAGATEAREA 1.43 LAYER Metal2 ; + ANTENNAGATEAREA 27.17 LAYER Metal3 ; + ANTENNAMAXAREACAR 3.266993 LAYER Metal2 ; + ANTENNAMAXAREACAR 20.674515 LAYER Metal3 ; + ANTENNAMAXCUTCAR 0.151469 LAYER Via2 ; + PORT + LAYER Metal2 ; + RECT 368.525 0 368.785 0.26 ; + END + END A_BIST_EN + PIN A_BIST_CLK + DIRECTION INPUT ; + USE SIGNAL ; + ANTENNAPARTIALMETALAREA 4.1639 LAYER Metal2 ; + ANTENNAMODEL OXIDE1 ; + ANTENNAGATEAREA 0.20085 LAYER Metal2 ; + ANTENNAMAXAREACAR 21.953448 LAYER Metal2 ; + PORT + LAYER Metal2 ; + RECT 364.445 0 364.705 0.26 ; + END + END A_BIST_CLK + PIN A_BIST_REN + DIRECTION INPUT ; + USE SIGNAL ; + ANTENNAPARTIALMETALAREA 4.1119 LAYER Metal2 ; + ANTENNAMODEL OXIDE1 ; + ANTENNAGATEAREA 0.20085 LAYER Metal2 ; + ANTENNAMAXAREACAR 21.694548 LAYER Metal2 ; + PORT + LAYER Metal2 ; + RECT 371.075 0 371.335 0.26 ; + END + END A_BIST_REN + PIN A_BIST_WEN + DIRECTION INPUT ; + USE SIGNAL ; + ANTENNAPARTIALMETALAREA 2.9051 LAYER Metal2 ; + ANTENNAMODEL OXIDE1 ; + ANTENNAGATEAREA 0.20085 LAYER Metal2 ; + ANTENNAMAXAREACAR 15.686084 LAYER Metal2 ; + PORT + LAYER Metal2 ; + RECT 370.565 0 370.825 0.26 ; + END + END A_BIST_WEN + PIN A_BIST_MEN + DIRECTION INPUT ; + USE SIGNAL ; + ANTENNAPARTIALMETALAREA 2.8977 LAYER Metal2 ; + ANTENNAMODEL OXIDE1 ; + ANTENNAGATEAREA 0.20085 LAYER Metal2 ; + ANTENNAMAXAREACAR 15.649241 LAYER Metal2 ; + PORT + LAYER Metal2 ; + RECT 364.955 0 365.215 0.26 ; + END + END A_BIST_MEN + PIN B_BIST_EN + DIRECTION INPUT ; + USE SIGNAL ; + ANTENNAPARTIALMETALAREA 3.9646 LAYER Metal2 ; + ANTENNAPARTIALMETALAREA 258.7774 LAYER Metal3 ; + ANTENNAPARTIALCUTAREA 0.0722 LAYER Via2 ; + ANTENNAMODEL OXIDE1 ; + ANTENNAGATEAREA 1.43 LAYER Metal2 ; + ANTENNAGATEAREA 27.17 LAYER Metal3 ; + ANTENNAMAXAREACAR 3.197902 LAYER Metal2 ; + ANTENNAMAXAREACAR 20.695755 LAYER Metal3 ; + ANTENNAMAXCUTCAR 0.151469 LAYER Via2 ; + PORT + LAYER Metal2 ; + RECT 334.045 0 334.305 0.26 ; + END + END B_BIST_EN + PIN B_BIST_CLK + DIRECTION INPUT ; + USE SIGNAL ; + ANTENNAPARTIALMETALAREA 4.1639 LAYER Metal2 ; + ANTENNAMODEL OXIDE1 ; + ANTENNAGATEAREA 0.20085 LAYER Metal2 ; + ANTENNAMAXAREACAR 21.953448 LAYER Metal2 ; + PORT + LAYER Metal2 ; + RECT 338.125 0 338.385 0.26 ; + END + END B_BIST_CLK + PIN B_BIST_REN + DIRECTION INPUT ; + USE SIGNAL ; + ANTENNAPARTIALMETALAREA 4.1119 LAYER Metal2 ; + ANTENNAMODEL OXIDE1 ; + ANTENNAGATEAREA 0.20085 LAYER Metal2 ; + ANTENNAMAXAREACAR 21.694548 LAYER Metal2 ; + PORT + LAYER Metal2 ; + RECT 331.495 0 331.755 0.26 ; + END + END B_BIST_REN + PIN B_BIST_WEN + DIRECTION INPUT ; + USE SIGNAL ; + ANTENNAPARTIALMETALAREA 2.9051 LAYER Metal2 ; + ANTENNAMODEL OXIDE1 ; + ANTENNAGATEAREA 0.20085 LAYER Metal2 ; + ANTENNAMAXAREACAR 15.686084 LAYER Metal2 ; + PORT + LAYER Metal2 ; + RECT 332.005 0 332.265 0.26 ; + END + END B_BIST_WEN + PIN B_BIST_MEN + DIRECTION INPUT ; + USE SIGNAL ; + ANTENNAPARTIALMETALAREA 2.8977 LAYER Metal2 ; + ANTENNAMODEL OXIDE1 ; + ANTENNAGATEAREA 0.20085 LAYER Metal2 ; + ANTENNAMAXAREACAR 15.649241 LAYER Metal2 ; + PORT + LAYER Metal2 ; + RECT 337.615 0 337.875 0.26 ; + END + END B_BIST_MEN + OBS + LAYER Metal1 ; + RECT 0 0 702.83 136.97 ; + LAYER Metal2 ; + RECT 0.31 53.41 0.51 136.94 ; + RECT 1.135 136.21 1.335 136.94 ; + RECT 1.545 136.21 1.905 136.94 ; + RECT 2.115 136.21 2.315 136.94 ; + RECT 2.19 0.52 2.45 7.78 ; + RECT 2.7 0.3 2.96 5.235 ; + RECT 2.77 136.21 2.97 136.94 ; + RECT 3.21 0.52 3.47 5.57 ; + RECT 3.18 136.21 3.54 136.94 ; + RECT 3.835 136.21 4.035 136.94 ; + RECT 4.33 136.21 4.69 136.94 ; + RECT 4.585 0.52 4.845 6.28 ; + RECT 4.9 136.21 5.1 136.94 ; + RECT 5.555 136.21 5.755 136.94 ; + RECT 5.965 136.21 6.325 136.94 ; + RECT 6.535 136.21 6.735 136.94 ; + RECT 6.27 0.18 7.04 0.88 ; + RECT 7.19 136.21 7.39 136.94 ; + RECT 7.29 0.3 7.55 8.7 ; + RECT 7.6 136.21 7.96 136.94 ; + RECT 8.255 136.21 8.455 136.94 ; + RECT 8.75 136.21 9.11 136.94 ; + RECT 9.84 0.155 10.61 0.445 ; + RECT 9.84 0.155 10.1 8.665 ; + RECT 10.35 0.155 10.61 8.665 ; + RECT 9.32 136.21 9.52 136.94 ; + RECT 9.33 0.52 9.59 9.955 ; + RECT 9.975 136.21 10.175 136.94 ; + RECT 10.385 136.21 10.745 136.94 ; + RECT 10.86 0.52 11.12 11.315 ; + RECT 10.955 136.21 11.155 136.94 ; + RECT 11.37 0.52 11.63 13.45 ; + RECT 11.61 136.21 11.81 136.94 ; + RECT 11.88 0.52 12.14 14.115 ; + RECT 12.02 136.21 12.38 136.94 ; + RECT 12.675 136.21 12.875 136.94 ; + RECT 14.075 0.155 14.845 0.445 ; + RECT 14.075 0.155 14.335 13.21 ; + RECT 14.585 0.155 14.845 13.21 ; + RECT 13.17 136.21 13.53 136.94 ; + RECT 13.74 136.21 13.94 136.94 ; + RECT 15.095 0.18 15.865 0.88 ; + RECT 15.095 0.18 15.355 12.9 ; + RECT 15.605 0.18 15.865 12.9 ; + RECT 14.395 136.21 14.595 136.94 ; + RECT 14.805 136.21 15.165 136.94 ; + RECT 15.375 136.21 15.575 136.94 ; + RECT 16.03 136.21 16.23 136.94 ; + RECT 16.315 0.52 16.575 2.82 ; + RECT 16.44 136.21 16.8 136.94 ; + RECT 17.095 136.21 17.295 136.94 ; + RECT 17.59 136.21 17.95 136.94 ; + RECT 17.845 0.52 18.105 2.82 ; + RECT 18.16 136.21 18.36 136.94 ; + RECT 18.815 136.21 19.015 136.94 ; + RECT 19.02 0.52 19.28 4.315 ; + RECT 19.225 136.21 19.585 136.94 ; + RECT 19.795 136.21 19.995 136.94 ; + RECT 19.87 0.52 20.13 7.78 ; + RECT 20.38 0.3 20.64 5.235 ; + RECT 20.45 136.21 20.65 136.94 ; + RECT 20.89 0.52 21.15 5.57 ; + RECT 20.86 136.21 21.22 136.94 ; + RECT 21.515 136.21 21.715 136.94 ; + RECT 22.01 136.21 22.37 136.94 ; + RECT 22.265 0.52 22.525 6.28 ; + RECT 22.58 136.21 22.78 136.94 ; + RECT 23.235 136.21 23.435 136.94 ; + RECT 23.645 136.21 24.005 136.94 ; + RECT 24.215 136.21 24.415 136.94 ; + RECT 23.95 0.18 24.72 0.88 ; + RECT 24.87 136.21 25.07 136.94 ; + RECT 24.97 0.3 25.23 8.7 ; + RECT 25.28 136.21 25.64 136.94 ; + RECT 25.935 136.21 26.135 136.94 ; + RECT 26.43 136.21 26.79 136.94 ; + RECT 27.52 0.155 28.29 0.445 ; + RECT 27.52 0.155 27.78 8.665 ; + RECT 28.03 0.155 28.29 8.665 ; + RECT 27 136.21 27.2 136.94 ; + RECT 27.01 0.52 27.27 9.955 ; + RECT 27.655 136.21 27.855 136.94 ; + RECT 28.065 136.21 28.425 136.94 ; + RECT 28.54 0.52 28.8 11.315 ; + RECT 28.635 136.21 28.835 136.94 ; + RECT 29.05 0.52 29.31 13.45 ; + RECT 29.29 136.21 29.49 136.94 ; + RECT 29.56 0.52 29.82 14.115 ; + RECT 29.7 136.21 30.06 136.94 ; + RECT 30.355 136.21 30.555 136.94 ; + RECT 31.755 0.155 32.525 0.445 ; + RECT 31.755 0.155 32.015 13.21 ; + RECT 32.265 0.155 32.525 13.21 ; + RECT 30.85 136.21 31.21 136.94 ; + RECT 31.42 136.21 31.62 136.94 ; + RECT 32.775 0.18 33.545 0.88 ; + RECT 32.775 0.18 33.035 12.9 ; + RECT 33.285 0.18 33.545 12.9 ; + RECT 32.075 136.21 32.275 136.94 ; + RECT 32.485 136.21 32.845 136.94 ; + RECT 33.055 136.21 33.255 136.94 ; + RECT 33.71 136.21 33.91 136.94 ; + RECT 33.995 0.52 34.255 2.82 ; + RECT 34.12 136.21 34.48 136.94 ; + RECT 34.775 136.21 34.975 136.94 ; + RECT 35.27 136.21 35.63 136.94 ; + RECT 35.525 0.52 35.785 2.82 ; + RECT 35.84 136.21 36.04 136.94 ; + RECT 36.495 136.21 36.695 136.94 ; + RECT 36.7 0.52 36.96 4.315 ; + RECT 36.905 136.21 37.265 136.94 ; + RECT 37.475 136.21 37.675 136.94 ; + RECT 37.55 0.52 37.81 7.78 ; + RECT 38.06 0.3 38.32 5.235 ; + RECT 38.13 136.21 38.33 136.94 ; + RECT 38.57 0.52 38.83 5.57 ; + RECT 38.54 136.21 38.9 136.94 ; + RECT 39.195 136.21 39.395 136.94 ; + RECT 39.69 136.21 40.05 136.94 ; + RECT 39.945 0.52 40.205 6.28 ; + RECT 40.26 136.21 40.46 136.94 ; + RECT 40.915 136.21 41.115 136.94 ; + RECT 41.325 136.21 41.685 136.94 ; + RECT 41.895 136.21 42.095 136.94 ; + RECT 41.63 0.18 42.4 0.88 ; + RECT 42.55 136.21 42.75 136.94 ; + RECT 42.65 0.3 42.91 8.7 ; + RECT 42.96 136.21 43.32 136.94 ; + RECT 43.615 136.21 43.815 136.94 ; + RECT 44.11 136.21 44.47 136.94 ; + RECT 45.2 0.155 45.97 0.445 ; + RECT 45.2 0.155 45.46 8.665 ; + RECT 45.71 0.155 45.97 8.665 ; + RECT 44.68 136.21 44.88 136.94 ; + RECT 44.69 0.52 44.95 9.955 ; + RECT 45.335 136.21 45.535 136.94 ; + RECT 45.745 136.21 46.105 136.94 ; + RECT 46.22 0.52 46.48 11.315 ; + RECT 46.315 136.21 46.515 136.94 ; + RECT 46.73 0.52 46.99 13.45 ; + RECT 46.97 136.21 47.17 136.94 ; + RECT 47.24 0.52 47.5 14.115 ; + RECT 47.38 136.21 47.74 136.94 ; + RECT 48.035 136.21 48.235 136.94 ; + RECT 49.435 0.155 50.205 0.445 ; + RECT 49.435 0.155 49.695 13.21 ; + RECT 49.945 0.155 50.205 13.21 ; + RECT 48.53 136.21 48.89 136.94 ; + RECT 49.1 136.21 49.3 136.94 ; + RECT 50.455 0.18 51.225 0.88 ; + RECT 50.455 0.18 50.715 12.9 ; + RECT 50.965 0.18 51.225 12.9 ; + RECT 49.755 136.21 49.955 136.94 ; + RECT 50.165 136.21 50.525 136.94 ; + RECT 50.735 136.21 50.935 136.94 ; + RECT 51.39 136.21 51.59 136.94 ; + RECT 51.675 0.52 51.935 2.82 ; + RECT 51.8 136.21 52.16 136.94 ; + RECT 52.455 136.21 52.655 136.94 ; + RECT 52.95 136.21 53.31 136.94 ; + RECT 53.205 0.52 53.465 2.82 ; + RECT 53.52 136.21 53.72 136.94 ; + RECT 54.175 136.21 54.375 136.94 ; + RECT 54.38 0.52 54.64 4.315 ; + RECT 54.585 136.21 54.945 136.94 ; + RECT 55.155 136.21 55.355 136.94 ; + RECT 55.23 0.52 55.49 7.78 ; + RECT 55.74 0.3 56 5.235 ; + RECT 55.81 136.21 56.01 136.94 ; + RECT 56.25 0.52 56.51 5.57 ; + RECT 56.22 136.21 56.58 136.94 ; + RECT 56.875 136.21 57.075 136.94 ; + RECT 57.37 136.21 57.73 136.94 ; + RECT 57.625 0.52 57.885 6.28 ; + RECT 57.94 136.21 58.14 136.94 ; + RECT 58.595 136.21 58.795 136.94 ; + RECT 59.005 136.21 59.365 136.94 ; + RECT 59.575 136.21 59.775 136.94 ; + RECT 59.31 0.18 60.08 0.88 ; + RECT 60.23 136.21 60.43 136.94 ; + RECT 60.33 0.3 60.59 8.7 ; + RECT 60.64 136.21 61 136.94 ; + RECT 61.295 136.21 61.495 136.94 ; + RECT 61.79 136.21 62.15 136.94 ; + RECT 62.88 0.155 63.65 0.445 ; + RECT 62.88 0.155 63.14 8.665 ; + RECT 63.39 0.155 63.65 8.665 ; + RECT 62.36 136.21 62.56 136.94 ; + RECT 62.37 0.52 62.63 9.955 ; + RECT 63.015 136.21 63.215 136.94 ; + RECT 63.425 136.21 63.785 136.94 ; + RECT 63.9 0.52 64.16 11.315 ; + RECT 63.995 136.21 64.195 136.94 ; + RECT 64.41 0.52 64.67 13.45 ; + RECT 64.65 136.21 64.85 136.94 ; + RECT 64.92 0.52 65.18 14.115 ; + RECT 65.06 136.21 65.42 136.94 ; + RECT 65.715 136.21 65.915 136.94 ; + RECT 67.115 0.155 67.885 0.445 ; + RECT 67.115 0.155 67.375 13.21 ; + RECT 67.625 0.155 67.885 13.21 ; + RECT 66.21 136.21 66.57 136.94 ; + RECT 66.78 136.21 66.98 136.94 ; + RECT 68.135 0.18 68.905 0.88 ; + RECT 68.135 0.18 68.395 12.9 ; + RECT 68.645 0.18 68.905 12.9 ; + RECT 67.435 136.21 67.635 136.94 ; + RECT 67.845 136.21 68.205 136.94 ; + RECT 68.415 136.21 68.615 136.94 ; + RECT 69.07 136.21 69.27 136.94 ; + RECT 69.355 0.52 69.615 2.82 ; + RECT 69.48 136.21 69.84 136.94 ; + RECT 70.135 136.21 70.335 136.94 ; + RECT 70.63 136.21 70.99 136.94 ; + RECT 70.885 0.52 71.145 2.82 ; + RECT 71.2 136.21 71.4 136.94 ; + RECT 71.855 136.21 72.055 136.94 ; + RECT 72.06 0.52 72.32 4.315 ; + RECT 72.265 136.21 72.625 136.94 ; + RECT 72.835 136.21 73.035 136.94 ; + RECT 72.91 0.52 73.17 7.78 ; + RECT 73.42 0.3 73.68 5.235 ; + RECT 73.49 136.21 73.69 136.94 ; + RECT 73.93 0.52 74.19 5.57 ; + RECT 73.9 136.21 74.26 136.94 ; + RECT 74.555 136.21 74.755 136.94 ; + RECT 75.05 136.21 75.41 136.94 ; + RECT 75.305 0.52 75.565 6.28 ; + RECT 75.62 136.21 75.82 136.94 ; + RECT 76.275 136.21 76.475 136.94 ; + RECT 76.685 136.21 77.045 136.94 ; + RECT 77.255 136.21 77.455 136.94 ; + RECT 76.99 0.18 77.76 0.88 ; + RECT 77.91 136.21 78.11 136.94 ; + RECT 78.01 0.3 78.27 8.7 ; + RECT 78.32 136.21 78.68 136.94 ; + RECT 78.975 136.21 79.175 136.94 ; + RECT 79.47 136.21 79.83 136.94 ; + RECT 80.56 0.155 81.33 0.445 ; + RECT 80.56 0.155 80.82 8.665 ; + RECT 81.07 0.155 81.33 8.665 ; + RECT 80.04 136.21 80.24 136.94 ; + RECT 80.05 0.52 80.31 9.955 ; + RECT 80.695 136.21 80.895 136.94 ; + RECT 81.105 136.21 81.465 136.94 ; + RECT 81.58 0.52 81.84 11.315 ; + RECT 81.675 136.21 81.875 136.94 ; + RECT 82.09 0.52 82.35 13.45 ; + RECT 82.33 136.21 82.53 136.94 ; + RECT 82.6 0.52 82.86 14.115 ; + RECT 82.74 136.21 83.1 136.94 ; + RECT 83.395 136.21 83.595 136.94 ; + RECT 84.795 0.155 85.565 0.445 ; + RECT 84.795 0.155 85.055 13.21 ; + RECT 85.305 0.155 85.565 13.21 ; + RECT 83.89 136.21 84.25 136.94 ; + RECT 84.46 136.21 84.66 136.94 ; + RECT 85.815 0.18 86.585 0.88 ; + RECT 85.815 0.18 86.075 12.9 ; + RECT 86.325 0.18 86.585 12.9 ; + RECT 85.115 136.21 85.315 136.94 ; + RECT 85.525 136.21 85.885 136.94 ; + RECT 86.095 136.21 86.295 136.94 ; + RECT 86.75 136.21 86.95 136.94 ; + RECT 87.035 0.52 87.295 2.82 ; + RECT 87.16 136.21 87.52 136.94 ; + RECT 87.815 136.21 88.015 136.94 ; + RECT 88.31 136.21 88.67 136.94 ; + RECT 88.565 0.52 88.825 2.82 ; + RECT 88.88 136.21 89.08 136.94 ; + RECT 89.535 136.21 89.735 136.94 ; + RECT 89.74 0.52 90 4.315 ; + RECT 89.945 136.21 90.305 136.94 ; + RECT 90.515 136.21 90.715 136.94 ; + RECT 90.59 0.52 90.85 7.78 ; + RECT 91.1 0.3 91.36 5.235 ; + RECT 91.17 136.21 91.37 136.94 ; + RECT 91.61 0.52 91.87 5.57 ; + RECT 91.58 136.21 91.94 136.94 ; + RECT 92.235 136.21 92.435 136.94 ; + RECT 92.73 136.21 93.09 136.94 ; + RECT 92.985 0.52 93.245 6.28 ; + RECT 93.3 136.21 93.5 136.94 ; + RECT 93.955 136.21 94.155 136.94 ; + RECT 94.365 136.21 94.725 136.94 ; + RECT 94.935 136.21 95.135 136.94 ; + RECT 94.67 0.18 95.44 0.88 ; + RECT 95.59 136.21 95.79 136.94 ; + RECT 95.69 0.3 95.95 8.7 ; + RECT 96 136.21 96.36 136.94 ; + RECT 96.655 136.21 96.855 136.94 ; + RECT 97.15 136.21 97.51 136.94 ; + RECT 98.24 0.155 99.01 0.445 ; + RECT 98.24 0.155 98.5 8.665 ; + RECT 98.75 0.155 99.01 8.665 ; + RECT 97.72 136.21 97.92 136.94 ; + RECT 97.73 0.52 97.99 9.955 ; + RECT 98.375 136.21 98.575 136.94 ; + RECT 98.785 136.21 99.145 136.94 ; + RECT 99.26 0.52 99.52 11.315 ; + RECT 99.355 136.21 99.555 136.94 ; + RECT 99.77 0.52 100.03 13.45 ; + RECT 100.01 136.21 100.21 136.94 ; + RECT 100.28 0.52 100.54 14.115 ; + RECT 100.42 136.21 100.78 136.94 ; + RECT 101.075 136.21 101.275 136.94 ; + RECT 102.475 0.155 103.245 0.445 ; + RECT 102.475 0.155 102.735 13.21 ; + RECT 102.985 0.155 103.245 13.21 ; + RECT 101.57 136.21 101.93 136.94 ; + RECT 102.14 136.21 102.34 136.94 ; + RECT 103.495 0.18 104.265 0.88 ; + RECT 103.495 0.18 103.755 12.9 ; + RECT 104.005 0.18 104.265 12.9 ; + RECT 102.795 136.21 102.995 136.94 ; + RECT 103.205 136.21 103.565 136.94 ; + RECT 103.775 136.21 103.975 136.94 ; + RECT 104.43 136.21 104.63 136.94 ; + RECT 104.715 0.52 104.975 2.82 ; + RECT 104.84 136.21 105.2 136.94 ; + RECT 105.495 136.21 105.695 136.94 ; + RECT 105.99 136.21 106.35 136.94 ; + RECT 106.245 0.52 106.505 2.82 ; + RECT 106.56 136.21 106.76 136.94 ; + RECT 107.215 136.21 107.415 136.94 ; + RECT 107.42 0.52 107.68 4.315 ; + RECT 107.625 136.21 107.985 136.94 ; + RECT 108.195 136.21 108.395 136.94 ; + RECT 108.27 0.52 108.53 7.78 ; + RECT 108.78 0.3 109.04 5.235 ; + RECT 108.85 136.21 109.05 136.94 ; + RECT 109.29 0.52 109.55 5.57 ; + RECT 109.26 136.21 109.62 136.94 ; + RECT 109.915 136.21 110.115 136.94 ; + RECT 110.41 136.21 110.77 136.94 ; + RECT 110.665 0.52 110.925 6.28 ; + RECT 110.98 136.21 111.18 136.94 ; + RECT 111.635 136.21 111.835 136.94 ; + RECT 112.045 136.21 112.405 136.94 ; + RECT 112.615 136.21 112.815 136.94 ; + RECT 112.35 0.18 113.12 0.88 ; + RECT 113.27 136.21 113.47 136.94 ; + RECT 113.37 0.3 113.63 8.7 ; + RECT 113.68 136.21 114.04 136.94 ; + RECT 114.335 136.21 114.535 136.94 ; + RECT 114.83 136.21 115.19 136.94 ; + RECT 115.92 0.155 116.69 0.445 ; + RECT 115.92 0.155 116.18 8.665 ; + RECT 116.43 0.155 116.69 8.665 ; + RECT 115.4 136.21 115.6 136.94 ; + RECT 115.41 0.52 115.67 9.955 ; + RECT 116.055 136.21 116.255 136.94 ; + RECT 116.465 136.21 116.825 136.94 ; + RECT 116.94 0.52 117.2 11.315 ; + RECT 117.035 136.21 117.235 136.94 ; + RECT 117.45 0.52 117.71 13.45 ; + RECT 117.69 136.21 117.89 136.94 ; + RECT 117.96 0.52 118.22 14.115 ; + RECT 118.1 136.21 118.46 136.94 ; + RECT 118.755 136.21 118.955 136.94 ; + RECT 120.155 0.155 120.925 0.445 ; + RECT 120.155 0.155 120.415 13.21 ; + RECT 120.665 0.155 120.925 13.21 ; + RECT 119.25 136.21 119.61 136.94 ; + RECT 119.82 136.21 120.02 136.94 ; + RECT 121.175 0.18 121.945 0.88 ; + RECT 121.175 0.18 121.435 12.9 ; + RECT 121.685 0.18 121.945 12.9 ; + RECT 120.475 136.21 120.675 136.94 ; + RECT 120.885 136.21 121.245 136.94 ; + RECT 121.455 136.21 121.655 136.94 ; + RECT 122.11 136.21 122.31 136.94 ; + RECT 122.395 0.52 122.655 2.82 ; + RECT 122.52 136.21 122.88 136.94 ; + RECT 123.175 136.21 123.375 136.94 ; + RECT 123.67 136.21 124.03 136.94 ; + RECT 123.925 0.52 124.185 2.82 ; + RECT 124.24 136.21 124.44 136.94 ; + RECT 124.895 136.21 125.095 136.94 ; + RECT 125.1 0.52 125.36 4.315 ; + RECT 125.305 136.21 125.665 136.94 ; + RECT 125.875 136.21 126.075 136.94 ; + RECT 125.95 0.52 126.21 7.78 ; + RECT 126.46 0.3 126.72 5.235 ; + RECT 126.53 136.21 126.73 136.94 ; + RECT 126.97 0.52 127.23 5.57 ; + RECT 126.94 136.21 127.3 136.94 ; + RECT 127.595 136.21 127.795 136.94 ; + RECT 128.09 136.21 128.45 136.94 ; + RECT 128.345 0.52 128.605 6.28 ; + RECT 128.66 136.21 128.86 136.94 ; + RECT 129.315 136.21 129.515 136.94 ; + RECT 129.725 136.21 130.085 136.94 ; + RECT 130.295 136.21 130.495 136.94 ; + RECT 130.03 0.18 130.8 0.88 ; + RECT 130.95 136.21 131.15 136.94 ; + RECT 131.05 0.3 131.31 8.7 ; + RECT 131.36 136.21 131.72 136.94 ; + RECT 132.015 136.21 132.215 136.94 ; + RECT 132.51 136.21 132.87 136.94 ; + RECT 133.6 0.155 134.37 0.445 ; + RECT 133.6 0.155 133.86 8.665 ; + RECT 134.11 0.155 134.37 8.665 ; + RECT 133.08 136.21 133.28 136.94 ; + RECT 133.09 0.52 133.35 9.955 ; + RECT 133.735 136.21 133.935 136.94 ; + RECT 134.145 136.21 134.505 136.94 ; + RECT 134.62 0.52 134.88 11.315 ; + RECT 134.715 136.21 134.915 136.94 ; + RECT 135.13 0.52 135.39 13.45 ; + RECT 135.37 136.21 135.57 136.94 ; + RECT 135.64 0.52 135.9 14.115 ; + RECT 135.78 136.21 136.14 136.94 ; + RECT 136.435 136.21 136.635 136.94 ; + RECT 137.835 0.155 138.605 0.445 ; + RECT 137.835 0.155 138.095 13.21 ; + RECT 138.345 0.155 138.605 13.21 ; + RECT 136.93 136.21 137.29 136.94 ; + RECT 137.5 136.21 137.7 136.94 ; + RECT 138.855 0.18 139.625 0.88 ; + RECT 138.855 0.18 139.115 12.9 ; + RECT 139.365 0.18 139.625 12.9 ; + RECT 138.155 136.21 138.355 136.94 ; + RECT 138.565 136.21 138.925 136.94 ; + RECT 139.135 136.21 139.335 136.94 ; + RECT 139.79 136.21 139.99 136.94 ; + RECT 140.075 0.52 140.335 2.82 ; + RECT 140.2 136.21 140.56 136.94 ; + RECT 140.855 136.21 141.055 136.94 ; + RECT 141.35 136.21 141.71 136.94 ; + RECT 141.605 0.52 141.865 2.82 ; + RECT 141.92 136.21 142.12 136.94 ; + RECT 142.575 136.21 142.775 136.94 ; + RECT 142.78 0.52 143.04 4.315 ; + RECT 142.985 136.21 143.345 136.94 ; + RECT 143.555 136.21 143.755 136.94 ; + RECT 143.63 0.52 143.89 7.78 ; + RECT 144.14 0.3 144.4 5.235 ; + RECT 144.21 136.21 144.41 136.94 ; + RECT 144.65 0.52 144.91 5.57 ; + RECT 144.62 136.21 144.98 136.94 ; + RECT 145.275 136.21 145.475 136.94 ; + RECT 145.77 136.21 146.13 136.94 ; + RECT 146.025 0.52 146.285 6.28 ; + RECT 146.34 136.21 146.54 136.94 ; + RECT 146.995 136.21 147.195 136.94 ; + RECT 147.405 136.21 147.765 136.94 ; + RECT 147.975 136.21 148.175 136.94 ; + RECT 147.71 0.18 148.48 0.88 ; + RECT 148.63 136.21 148.83 136.94 ; + RECT 148.73 0.3 148.99 8.7 ; + RECT 149.04 136.21 149.4 136.94 ; + RECT 149.695 136.21 149.895 136.94 ; + RECT 150.19 136.21 150.55 136.94 ; + RECT 151.28 0.155 152.05 0.445 ; + RECT 151.28 0.155 151.54 8.665 ; + RECT 151.79 0.155 152.05 8.665 ; + RECT 150.76 136.21 150.96 136.94 ; + RECT 150.77 0.52 151.03 9.955 ; + RECT 151.415 136.21 151.615 136.94 ; + RECT 151.825 136.21 152.185 136.94 ; + RECT 152.3 0.52 152.56 11.315 ; + RECT 152.395 136.21 152.595 136.94 ; + RECT 152.81 0.52 153.07 13.45 ; + RECT 153.05 136.21 153.25 136.94 ; + RECT 153.32 0.52 153.58 14.115 ; + RECT 153.46 136.21 153.82 136.94 ; + RECT 154.115 136.21 154.315 136.94 ; + RECT 155.515 0.155 156.285 0.445 ; + RECT 155.515 0.155 155.775 13.21 ; + RECT 156.025 0.155 156.285 13.21 ; + RECT 154.61 136.21 154.97 136.94 ; + RECT 155.18 136.21 155.38 136.94 ; + RECT 156.535 0.18 157.305 0.88 ; + RECT 156.535 0.18 156.795 12.9 ; + RECT 157.045 0.18 157.305 12.9 ; + RECT 155.835 136.21 156.035 136.94 ; + RECT 156.245 136.21 156.605 136.94 ; + RECT 156.815 136.21 157.015 136.94 ; + RECT 157.47 136.21 157.67 136.94 ; + RECT 157.755 0.52 158.015 2.82 ; + RECT 157.88 136.21 158.24 136.94 ; + RECT 158.535 136.21 158.735 136.94 ; + RECT 159.03 136.21 159.39 136.94 ; + RECT 159.285 0.52 159.545 2.82 ; + RECT 159.6 136.21 159.8 136.94 ; + RECT 160.255 136.21 160.455 136.94 ; + RECT 160.46 0.52 160.72 4.315 ; + RECT 160.665 136.21 161.025 136.94 ; + RECT 161.235 136.21 161.435 136.94 ; + RECT 161.31 0.52 161.57 7.78 ; + RECT 161.82 0.3 162.08 5.235 ; + RECT 161.89 136.21 162.09 136.94 ; + RECT 162.33 0.52 162.59 5.57 ; + RECT 162.3 136.21 162.66 136.94 ; + RECT 162.955 136.21 163.155 136.94 ; + RECT 163.45 136.21 163.81 136.94 ; + RECT 163.705 0.52 163.965 6.28 ; + RECT 164.02 136.21 164.22 136.94 ; + RECT 164.675 136.21 164.875 136.94 ; + RECT 165.085 136.21 165.445 136.94 ; + RECT 165.655 136.21 165.855 136.94 ; + RECT 165.39 0.18 166.16 0.88 ; + RECT 166.31 136.21 166.51 136.94 ; + RECT 166.41 0.3 166.67 8.7 ; + RECT 166.72 136.21 167.08 136.94 ; + RECT 167.375 136.21 167.575 136.94 ; + RECT 167.87 136.21 168.23 136.94 ; + RECT 168.96 0.155 169.73 0.445 ; + RECT 168.96 0.155 169.22 8.665 ; + RECT 169.47 0.155 169.73 8.665 ; + RECT 168.44 136.21 168.64 136.94 ; + RECT 168.45 0.52 168.71 9.955 ; + RECT 169.095 136.21 169.295 136.94 ; + RECT 169.505 136.21 169.865 136.94 ; + RECT 169.98 0.52 170.24 11.315 ; + RECT 170.075 136.21 170.275 136.94 ; + RECT 170.49 0.52 170.75 13.45 ; + RECT 170.73 136.21 170.93 136.94 ; + RECT 171 0.52 171.26 14.115 ; + RECT 171.14 136.21 171.5 136.94 ; + RECT 171.795 136.21 171.995 136.94 ; + RECT 173.195 0.155 173.965 0.445 ; + RECT 173.195 0.155 173.455 13.21 ; + RECT 173.705 0.155 173.965 13.21 ; + RECT 172.29 136.21 172.65 136.94 ; + RECT 172.86 136.21 173.06 136.94 ; + RECT 174.215 0.18 174.985 0.88 ; + RECT 174.215 0.18 174.475 12.9 ; + RECT 174.725 0.18 174.985 12.9 ; + RECT 173.515 136.21 173.715 136.94 ; + RECT 173.925 136.21 174.285 136.94 ; + RECT 174.495 136.21 174.695 136.94 ; + RECT 175.15 136.21 175.35 136.94 ; + RECT 175.435 0.52 175.695 2.82 ; + RECT 175.56 136.21 175.92 136.94 ; + RECT 176.215 136.21 176.415 136.94 ; + RECT 176.71 136.21 177.07 136.94 ; + RECT 176.965 0.52 177.225 2.82 ; + RECT 177.28 136.21 177.48 136.94 ; + RECT 177.935 136.21 178.135 136.94 ; + RECT 178.14 0.52 178.4 4.315 ; + RECT 178.345 136.21 178.705 136.94 ; + RECT 178.915 136.21 179.115 136.94 ; + RECT 178.99 0.52 179.25 7.78 ; + RECT 179.5 0.3 179.76 5.235 ; + RECT 179.57 136.21 179.77 136.94 ; + RECT 180.01 0.52 180.27 5.57 ; + RECT 179.98 136.21 180.34 136.94 ; + RECT 180.635 136.21 180.835 136.94 ; + RECT 181.13 136.21 181.49 136.94 ; + RECT 181.385 0.52 181.645 6.28 ; + RECT 181.7 136.21 181.9 136.94 ; + RECT 182.355 136.21 182.555 136.94 ; + RECT 182.765 136.21 183.125 136.94 ; + RECT 183.335 136.21 183.535 136.94 ; + RECT 183.07 0.18 183.84 0.88 ; + RECT 183.99 136.21 184.19 136.94 ; + RECT 184.09 0.3 184.35 8.7 ; + RECT 184.4 136.21 184.76 136.94 ; + RECT 185.055 136.21 185.255 136.94 ; + RECT 185.55 136.21 185.91 136.94 ; + RECT 186.64 0.155 187.41 0.445 ; + RECT 186.64 0.155 186.9 8.665 ; + RECT 187.15 0.155 187.41 8.665 ; + RECT 186.12 136.21 186.32 136.94 ; + RECT 186.13 0.52 186.39 9.955 ; + RECT 186.775 136.21 186.975 136.94 ; + RECT 187.185 136.21 187.545 136.94 ; + RECT 187.66 0.52 187.92 11.315 ; + RECT 187.755 136.21 187.955 136.94 ; + RECT 188.17 0.52 188.43 13.45 ; + RECT 188.41 136.21 188.61 136.94 ; + RECT 188.68 0.52 188.94 14.115 ; + RECT 188.82 136.21 189.18 136.94 ; + RECT 189.475 136.21 189.675 136.94 ; + RECT 190.875 0.155 191.645 0.445 ; + RECT 190.875 0.155 191.135 13.21 ; + RECT 191.385 0.155 191.645 13.21 ; + RECT 189.97 136.21 190.33 136.94 ; + RECT 190.54 136.21 190.74 136.94 ; + RECT 191.895 0.18 192.665 0.88 ; + RECT 191.895 0.18 192.155 12.9 ; + RECT 192.405 0.18 192.665 12.9 ; + RECT 191.195 136.21 191.395 136.94 ; + RECT 191.605 136.21 191.965 136.94 ; + RECT 192.175 136.21 192.375 136.94 ; + RECT 192.83 136.21 193.03 136.94 ; + RECT 193.115 0.52 193.375 2.82 ; + RECT 193.24 136.21 193.6 136.94 ; + RECT 193.895 136.21 194.095 136.94 ; + RECT 194.39 136.21 194.75 136.94 ; + RECT 194.645 0.52 194.905 2.82 ; + RECT 194.96 136.21 195.16 136.94 ; + RECT 195.615 136.21 195.815 136.94 ; + RECT 195.82 0.52 196.08 4.315 ; + RECT 196.025 136.21 196.385 136.94 ; + RECT 196.595 136.21 196.795 136.94 ; + RECT 196.67 0.52 196.93 7.78 ; + RECT 197.18 0.3 197.44 5.235 ; + RECT 197.25 136.21 197.45 136.94 ; + RECT 197.69 0.52 197.95 5.57 ; + RECT 197.66 136.21 198.02 136.94 ; + RECT 198.315 136.21 198.515 136.94 ; + RECT 198.81 136.21 199.17 136.94 ; + RECT 199.065 0.52 199.325 6.28 ; + RECT 199.38 136.21 199.58 136.94 ; + RECT 200.035 136.21 200.235 136.94 ; + RECT 200.445 136.21 200.805 136.94 ; + RECT 201.015 136.21 201.215 136.94 ; + RECT 200.75 0.18 201.52 0.88 ; + RECT 201.67 136.21 201.87 136.94 ; + RECT 201.77 0.3 202.03 8.7 ; + RECT 202.08 136.21 202.44 136.94 ; + RECT 202.735 136.21 202.935 136.94 ; + RECT 203.23 136.21 203.59 136.94 ; + RECT 204.32 0.155 205.09 0.445 ; + RECT 204.32 0.155 204.58 8.665 ; + RECT 204.83 0.155 205.09 8.665 ; + RECT 203.8 136.21 204 136.94 ; + RECT 203.81 0.52 204.07 9.955 ; + RECT 204.455 136.21 204.655 136.94 ; + RECT 204.865 136.21 205.225 136.94 ; + RECT 205.34 0.52 205.6 11.315 ; + RECT 205.435 136.21 205.635 136.94 ; + RECT 205.85 0.52 206.11 13.45 ; + RECT 206.09 136.21 206.29 136.94 ; + RECT 206.36 0.52 206.62 14.115 ; + RECT 206.5 136.21 206.86 136.94 ; + RECT 207.155 136.21 207.355 136.94 ; + RECT 208.555 0.155 209.325 0.445 ; + RECT 208.555 0.155 208.815 13.21 ; + RECT 209.065 0.155 209.325 13.21 ; + RECT 207.65 136.21 208.01 136.94 ; + RECT 208.22 136.21 208.42 136.94 ; + RECT 209.575 0.18 210.345 0.88 ; + RECT 209.575 0.18 209.835 12.9 ; + RECT 210.085 0.18 210.345 12.9 ; + RECT 208.875 136.21 209.075 136.94 ; + RECT 209.285 136.21 209.645 136.94 ; + RECT 209.855 136.21 210.055 136.94 ; + RECT 210.51 136.21 210.71 136.94 ; + RECT 210.795 0.52 211.055 2.82 ; + RECT 210.92 136.21 211.28 136.94 ; + RECT 211.575 136.21 211.775 136.94 ; + RECT 212.07 136.21 212.43 136.94 ; + RECT 212.325 0.52 212.585 2.82 ; + RECT 212.64 136.21 212.84 136.94 ; + RECT 213.295 136.21 213.495 136.94 ; + RECT 213.5 0.52 213.76 4.315 ; + RECT 213.705 136.21 214.065 136.94 ; + RECT 214.275 136.21 214.475 136.94 ; + RECT 214.35 0.52 214.61 7.78 ; + RECT 214.86 0.3 215.12 5.235 ; + RECT 214.93 136.21 215.13 136.94 ; + RECT 215.37 0.52 215.63 5.57 ; + RECT 215.34 136.21 215.7 136.94 ; + RECT 215.995 136.21 216.195 136.94 ; + RECT 216.49 136.21 216.85 136.94 ; + RECT 216.745 0.52 217.005 6.28 ; + RECT 217.06 136.21 217.26 136.94 ; + RECT 217.715 136.21 217.915 136.94 ; + RECT 218.125 136.21 218.485 136.94 ; + RECT 218.695 136.21 218.895 136.94 ; + RECT 218.43 0.18 219.2 0.88 ; + RECT 219.35 136.21 219.55 136.94 ; + RECT 219.45 0.3 219.71 8.7 ; + RECT 219.76 136.21 220.12 136.94 ; + RECT 220.415 136.21 220.615 136.94 ; + RECT 220.91 136.21 221.27 136.94 ; + RECT 222 0.155 222.77 0.445 ; + RECT 222 0.155 222.26 8.665 ; + RECT 222.51 0.155 222.77 8.665 ; + RECT 221.48 136.21 221.68 136.94 ; + RECT 221.49 0.52 221.75 9.955 ; + RECT 222.135 136.21 222.335 136.94 ; + RECT 222.545 136.21 222.905 136.94 ; + RECT 223.02 0.52 223.28 11.315 ; + RECT 223.115 136.21 223.315 136.94 ; + RECT 223.53 0.52 223.79 13.45 ; + RECT 223.77 136.21 223.97 136.94 ; + RECT 224.04 0.52 224.3 14.115 ; + RECT 224.18 136.21 224.54 136.94 ; + RECT 224.835 136.21 225.035 136.94 ; + RECT 226.235 0.155 227.005 0.445 ; + RECT 226.235 0.155 226.495 13.21 ; + RECT 226.745 0.155 227.005 13.21 ; + RECT 225.33 136.21 225.69 136.94 ; + RECT 225.9 136.21 226.1 136.94 ; + RECT 227.255 0.18 228.025 0.88 ; + RECT 227.255 0.18 227.515 12.9 ; + RECT 227.765 0.18 228.025 12.9 ; + RECT 226.555 136.21 226.755 136.94 ; + RECT 226.965 136.21 227.325 136.94 ; + RECT 227.535 136.21 227.735 136.94 ; + RECT 228.19 136.21 228.39 136.94 ; + RECT 228.475 0.52 228.735 2.82 ; + RECT 228.6 136.21 228.96 136.94 ; + RECT 229.255 136.21 229.455 136.94 ; + RECT 229.75 136.21 230.11 136.94 ; + RECT 230.005 0.52 230.265 2.82 ; + RECT 230.32 136.21 230.52 136.94 ; + RECT 230.975 136.21 231.175 136.94 ; + RECT 231.18 0.52 231.44 4.315 ; + RECT 231.385 136.21 231.745 136.94 ; + RECT 231.955 136.21 232.155 136.94 ; + RECT 232.03 0.52 232.29 7.78 ; + RECT 232.54 0.3 232.8 5.235 ; + RECT 232.61 136.21 232.81 136.94 ; + RECT 233.05 0.52 233.31 5.57 ; + RECT 233.02 136.21 233.38 136.94 ; + RECT 233.675 136.21 233.875 136.94 ; + RECT 234.17 136.21 234.53 136.94 ; + RECT 234.425 0.52 234.685 6.28 ; + RECT 234.74 136.21 234.94 136.94 ; + RECT 235.395 136.21 235.595 136.94 ; + RECT 235.805 136.21 236.165 136.94 ; + RECT 236.375 136.21 236.575 136.94 ; + RECT 236.11 0.18 236.88 0.88 ; + RECT 237.03 136.21 237.23 136.94 ; + RECT 237.13 0.3 237.39 8.7 ; + RECT 237.44 136.21 237.8 136.94 ; + RECT 238.095 136.21 238.295 136.94 ; + RECT 238.59 136.21 238.95 136.94 ; + RECT 239.68 0.155 240.45 0.445 ; + RECT 239.68 0.155 239.94 8.665 ; + RECT 240.19 0.155 240.45 8.665 ; + RECT 239.16 136.21 239.36 136.94 ; + RECT 239.17 0.52 239.43 9.955 ; + RECT 239.815 136.21 240.015 136.94 ; + RECT 240.225 136.21 240.585 136.94 ; + RECT 240.7 0.52 240.96 11.315 ; + RECT 240.795 136.21 240.995 136.94 ; + RECT 241.21 0.52 241.47 13.45 ; + RECT 241.45 136.21 241.65 136.94 ; + RECT 241.72 0.52 241.98 14.115 ; + RECT 241.86 136.21 242.22 136.94 ; + RECT 242.515 136.21 242.715 136.94 ; + RECT 243.915 0.155 244.685 0.445 ; + RECT 243.915 0.155 244.175 13.21 ; + RECT 244.425 0.155 244.685 13.21 ; + RECT 243.01 136.21 243.37 136.94 ; + RECT 243.58 136.21 243.78 136.94 ; + RECT 244.935 0.18 245.705 0.88 ; + RECT 244.935 0.18 245.195 12.9 ; + RECT 245.445 0.18 245.705 12.9 ; + RECT 244.235 136.21 244.435 136.94 ; + RECT 244.645 136.21 245.005 136.94 ; + RECT 245.215 136.21 245.415 136.94 ; + RECT 245.87 136.21 246.07 136.94 ; + RECT 246.155 0.52 246.415 2.82 ; + RECT 246.28 136.21 246.64 136.94 ; + RECT 246.935 136.21 247.135 136.94 ; + RECT 247.43 136.21 247.79 136.94 ; + RECT 247.685 0.52 247.945 2.82 ; + RECT 248 136.21 248.2 136.94 ; + RECT 248.655 136.21 248.855 136.94 ; + RECT 248.86 0.52 249.12 4.315 ; + RECT 249.065 136.21 249.425 136.94 ; + RECT 249.635 136.21 249.835 136.94 ; + RECT 249.71 0.52 249.97 7.78 ; + RECT 250.22 0.3 250.48 5.235 ; + RECT 250.29 136.21 250.49 136.94 ; + RECT 250.73 0.52 250.99 5.57 ; + RECT 250.7 136.21 251.06 136.94 ; + RECT 251.355 136.21 251.555 136.94 ; + RECT 251.85 136.21 252.21 136.94 ; + RECT 252.105 0.52 252.365 6.28 ; + RECT 252.42 136.21 252.62 136.94 ; + RECT 253.075 136.21 253.275 136.94 ; + RECT 253.485 136.21 253.845 136.94 ; + RECT 254.055 136.21 254.255 136.94 ; + RECT 253.79 0.18 254.56 0.88 ; + RECT 254.71 136.21 254.91 136.94 ; + RECT 254.81 0.3 255.07 8.7 ; + RECT 255.12 136.21 255.48 136.94 ; + RECT 255.775 136.21 255.975 136.94 ; + RECT 256.27 136.21 256.63 136.94 ; + RECT 257.36 0.155 258.13 0.445 ; + RECT 257.36 0.155 257.62 8.665 ; + RECT 257.87 0.155 258.13 8.665 ; + RECT 256.84 136.21 257.04 136.94 ; + RECT 256.85 0.52 257.11 9.955 ; + RECT 257.495 136.21 257.695 136.94 ; + RECT 257.905 136.21 258.265 136.94 ; + RECT 258.38 0.52 258.64 11.315 ; + RECT 258.475 136.21 258.675 136.94 ; + RECT 258.89 0.52 259.15 13.45 ; + RECT 259.13 136.21 259.33 136.94 ; + RECT 259.4 0.52 259.66 14.115 ; + RECT 259.54 136.21 259.9 136.94 ; + RECT 260.195 136.21 260.395 136.94 ; + RECT 261.595 0.155 262.365 0.445 ; + RECT 261.595 0.155 261.855 13.21 ; + RECT 262.105 0.155 262.365 13.21 ; + RECT 260.69 136.21 261.05 136.94 ; + RECT 261.26 136.21 261.46 136.94 ; + RECT 262.615 0.18 263.385 0.88 ; + RECT 262.615 0.18 262.875 12.9 ; + RECT 263.125 0.18 263.385 12.9 ; + RECT 261.915 136.21 262.115 136.94 ; + RECT 262.325 136.21 262.685 136.94 ; + RECT 262.895 136.21 263.095 136.94 ; + RECT 263.55 136.21 263.75 136.94 ; + RECT 263.835 0.52 264.095 2.82 ; + RECT 263.96 136.21 264.32 136.94 ; + RECT 264.615 136.21 264.815 136.94 ; + RECT 265.11 136.21 265.47 136.94 ; + RECT 265.365 0.52 265.625 2.82 ; + RECT 265.68 136.21 265.88 136.94 ; + RECT 266.335 136.21 266.535 136.94 ; + RECT 266.54 0.52 266.8 4.315 ; + RECT 266.745 136.21 267.105 136.94 ; + RECT 267.315 136.21 267.515 136.94 ; + RECT 267.39 0.52 267.65 7.78 ; + RECT 267.9 0.3 268.16 5.235 ; + RECT 267.97 136.21 268.17 136.94 ; + RECT 268.41 0.52 268.67 5.57 ; + RECT 268.38 136.21 268.74 136.94 ; + RECT 269.035 136.21 269.235 136.94 ; + RECT 269.53 136.21 269.89 136.94 ; + RECT 269.785 0.52 270.045 6.28 ; + RECT 270.1 136.21 270.3 136.94 ; + RECT 270.755 136.21 270.955 136.94 ; + RECT 271.165 136.21 271.525 136.94 ; + RECT 271.735 136.21 271.935 136.94 ; + RECT 271.47 0.18 272.24 0.88 ; + RECT 272.39 136.21 272.59 136.94 ; + RECT 272.49 0.3 272.75 8.7 ; + RECT 272.8 136.21 273.16 136.94 ; + RECT 273.455 136.21 273.655 136.94 ; + RECT 273.95 136.21 274.31 136.94 ; + RECT 275.04 0.155 275.81 0.445 ; + RECT 275.04 0.155 275.3 8.665 ; + RECT 275.55 0.155 275.81 8.665 ; + RECT 274.52 136.21 274.72 136.94 ; + RECT 274.53 0.52 274.79 9.955 ; + RECT 275.175 136.21 275.375 136.94 ; + RECT 275.585 136.21 275.945 136.94 ; + RECT 276.06 0.52 276.32 11.315 ; + RECT 276.155 136.21 276.355 136.94 ; + RECT 276.57 0.52 276.83 13.45 ; + RECT 276.81 136.21 277.01 136.94 ; + RECT 277.08 0.52 277.34 14.115 ; + RECT 277.22 136.21 277.58 136.94 ; + RECT 277.875 136.21 278.075 136.94 ; + RECT 279.275 0.155 280.045 0.445 ; + RECT 279.275 0.155 279.535 13.21 ; + RECT 279.785 0.155 280.045 13.21 ; + RECT 278.37 136.21 278.73 136.94 ; + RECT 278.94 136.21 279.14 136.94 ; + RECT 280.295 0.18 281.065 0.88 ; + RECT 280.295 0.18 280.555 12.9 ; + RECT 280.805 0.18 281.065 12.9 ; + RECT 279.595 136.21 279.795 136.94 ; + RECT 280.005 136.21 280.365 136.94 ; + RECT 280.575 136.21 280.775 136.94 ; + RECT 281.23 136.21 281.43 136.94 ; + RECT 281.515 0.52 281.775 2.82 ; + RECT 281.64 136.21 282 136.94 ; + RECT 282.295 136.21 282.495 136.94 ; + RECT 282.79 136.21 283.15 136.94 ; + RECT 283.045 0.52 283.305 2.82 ; + RECT 283.36 136.21 283.56 136.94 ; + RECT 284.015 136.21 284.215 136.94 ; + RECT 284.22 0.52 284.48 4.315 ; + RECT 285.75 0.17 286.52 0.43 ; + RECT 285.75 0.17 286.01 8.7 ; + RECT 286.26 0.17 286.52 8.7 ; + RECT 286.77 0.18 287.54 0.88 ; + RECT 286.77 0.18 287.03 8.7 ; + RECT 287.28 0.18 287.54 8.7 ; + RECT 287.79 0.17 288.56 0.43 ; + RECT 287.79 0.17 288.05 8.7 ; + RECT 288.3 0.17 288.56 8.7 ; + RECT 288.81 0.18 289.58 0.88 ; + RECT 288.81 0.18 289.07 8.7 ; + RECT 289.32 0.18 289.58 8.7 ; + RECT 289.83 0.17 290.6 0.43 ; + RECT 289.83 0.17 290.09 8.7 ; + RECT 290.34 0.17 290.6 8.7 ; + RECT 290.85 0.18 291.62 0.88 ; + RECT 290.85 0.18 291.11 8.7 ; + RECT 291.36 0.18 291.62 8.7 ; + RECT 291.87 0.17 292.64 0.43 ; + RECT 291.87 0.17 292.13 8.7 ; + RECT 292.38 0.17 292.64 8.7 ; + RECT 292.89 0.18 293.66 0.88 ; + RECT 292.89 0.18 293.15 8.7 ; + RECT 293.4 0.18 293.66 8.7 ; + RECT 293.91 0.17 294.68 0.43 ; + RECT 293.91 0.17 294.17 8.7 ; + RECT 294.42 0.17 294.68 8.7 ; + RECT 294.93 0.18 295.7 0.88 ; + RECT 294.93 0.18 295.19 8.7 ; + RECT 295.44 0.18 295.7 8.7 ; + RECT 295.95 0.17 296.72 0.43 ; + RECT 295.95 0.17 296.21 8.7 ; + RECT 296.46 0.17 296.72 8.7 ; + RECT 296.97 0.18 297.74 0.88 ; + RECT 296.97 0.18 297.23 8.7 ; + RECT 297.48 0.18 297.74 8.7 ; + RECT 297.99 0.17 298.76 0.43 ; + RECT 297.99 0.17 298.25 8.7 ; + RECT 298.5 0.17 298.76 8.7 ; + RECT 299.01 0.18 299.78 0.88 ; + RECT 299.01 0.18 299.27 8.7 ; + RECT 299.52 0.18 299.78 8.7 ; + RECT 300.03 0.17 300.8 0.43 ; + RECT 300.03 0.17 300.29 8.7 ; + RECT 300.54 0.17 300.8 8.7 ; + RECT 301.05 0.18 301.82 0.88 ; + RECT 301.05 0.18 301.31 8.7 ; + RECT 301.56 0.18 301.82 8.7 ; + RECT 302.07 0.17 302.84 0.43 ; + RECT 302.07 0.17 302.33 8.7 ; + RECT 302.58 0.17 302.84 8.7 ; + RECT 303.09 0.18 303.86 0.88 ; + RECT 303.09 0.18 303.35 8.7 ; + RECT 303.6 0.18 303.86 8.7 ; + RECT 304.11 0.17 304.88 0.43 ; + RECT 304.11 0.17 304.37 8.7 ; + RECT 304.62 0.17 304.88 8.7 ; + RECT 305.13 0.18 305.9 0.88 ; + RECT 305.13 0.18 305.39 8.7 ; + RECT 305.64 0.18 305.9 8.7 ; + RECT 306.15 0.17 306.92 0.43 ; + RECT 306.15 0.17 306.41 8.7 ; + RECT 306.66 0.17 306.92 8.7 ; + RECT 307.17 0.18 307.94 0.88 ; + RECT 307.17 0.18 307.43 8.7 ; + RECT 307.68 0.18 307.94 8.7 ; + RECT 308.19 0.17 308.96 0.43 ; + RECT 308.19 0.17 308.45 8.7 ; + RECT 308.7 0.17 308.96 8.7 ; + RECT 309.21 0.18 309.98 0.88 ; + RECT 309.21 0.18 309.47 8.7 ; + RECT 309.72 0.18 309.98 8.7 ; + RECT 284.425 136.21 284.785 136.94 ; + RECT 284.995 136.21 285.195 136.94 ; + RECT 311.605 0.18 312.375 0.88 ; + RECT 311.605 0.18 311.865 8.7 ; + RECT 312.115 0.18 312.375 8.7 ; + RECT 312.625 0.17 313.395 0.43 ; + RECT 312.625 0.17 312.885 8.7 ; + RECT 313.135 0.17 313.395 8.7 ; + RECT 285.82 136.13 286.02 136.94 ; + RECT 310.585 0.3 310.845 8.7 ; + RECT 314.665 0.18 315.435 0.88 ; + RECT 314.665 0.18 314.925 8.7 ; + RECT 315.175 0.18 315.435 8.7 ; + RECT 311.095 0.3 311.355 8.7 ; + RECT 313.645 0 313.905 8.7 ; + RECT 314.155 0 314.415 8.7 ; + RECT 315.685 0.52 315.945 8.7 ; + RECT 316.195 0.3 316.455 8.7 ; + RECT 316.705 0.3 316.965 8.7 ; + RECT 317.215 0.3 317.475 8.7 ; + RECT 317.725 0.3 317.985 8.7 ; + RECT 318.235 0.3 318.495 8.7 ; + RECT 318.745 0.3 319.005 8.7 ; + RECT 319.255 0.3 319.515 8.7 ; + RECT 321.295 0.18 322.065 0.88 ; + RECT 321.295 0.18 321.555 8.7 ; + RECT 321.805 0.18 322.065 8.7 ; + RECT 319.765 0.3 320.025 8.7 ; + RECT 320.275 0 320.535 8.7 ; + RECT 320.785 0 321.045 8.7 ; + RECT 322.315 0 322.575 8.7 ; + RECT 322.825 0 323.085 8.7 ; + RECT 323.335 0.52 323.595 8.7 ; + RECT 323.845 0.52 324.105 8.7 ; + RECT 324.355 0.52 324.615 8.7 ; + RECT 324.865 0.52 325.125 8.7 ; + RECT 325.375 0.52 325.635 8.7 ; + RECT 325.885 0.52 326.145 8.7 ; + RECT 326.395 0.52 326.655 8.7 ; + RECT 326.905 0.52 327.165 8.7 ; + RECT 327.415 0.3 327.675 8.7 ; + RECT 327.925 0.3 328.185 8.7 ; + RECT 328.435 0.3 328.695 8.7 ; + RECT 328.945 0.52 329.205 8.7 ; + RECT 329.455 0.52 329.715 8.7 ; + RECT 329.965 0.3 330.225 8.7 ; + RECT 330.475 0.3 330.735 8.7 ; + RECT 330.985 0.3 331.245 8.7 ; + RECT 331.495 0.52 331.755 8.7 ; + RECT 332.005 0.52 332.265 8.7 ; + RECT 332.515 0.3 332.775 8.7 ; + RECT 333.025 0.52 333.285 8.7 ; + RECT 333.535 0.52 333.795 8.7 ; + RECT 334.045 0.52 334.305 8.7 ; + RECT 334.555 0.52 334.815 8.7 ; + RECT 335.065 0.52 335.325 8.7 ; + RECT 335.575 0.3 335.835 8.7 ; + RECT 336.085 0.52 336.345 8.7 ; + RECT 336.595 0.52 336.855 8.7 ; + RECT 337.105 0.3 337.365 8.7 ; + RECT 337.615 0.52 337.875 8.7 ; + RECT 339.655 0.17 340.425 0.43 ; + RECT 339.655 0.17 339.915 8.7 ; + RECT 340.165 0.17 340.425 8.7 ; + RECT 338.125 0.52 338.385 8.7 ; + RECT 338.635 0.3 338.895 8.7 ; + RECT 339.145 0.3 339.405 8.7 ; + RECT 342.205 0.17 342.975 0.43 ; + RECT 342.205 0.17 342.465 8.7 ; + RECT 342.715 0.17 342.975 8.7 ; + RECT 340.675 0.3 340.935 8.7 ; + RECT 343.735 0.18 344.505 0.88 ; + RECT 343.735 0.18 343.995 8.7 ; + RECT 344.245 0.18 344.505 8.7 ; + RECT 341.185 0.3 341.445 8.7 ; + RECT 341.695 0.3 341.955 8.7 ; + RECT 343.225 0.3 343.485 8.7 ; + RECT 344.755 0 345.015 8.7 ; + RECT 345.265 0 345.525 8.7 ; + RECT 345.775 0.52 346.035 8.7 ; + RECT 346.285 0.52 346.545 8.7 ; + RECT 346.795 0.52 347.055 8.7 ; + RECT 347.305 0.52 347.565 8.7 ; + RECT 347.815 0 348.075 8.7 ; + RECT 348.325 0 348.585 8.7 ; + RECT 348.835 0.3 349.095 8.7 ; + RECT 349.345 0.3 349.605 8.7 ; + RECT 349.855 0 350.115 8.7 ; + RECT 350.365 0 350.625 8.7 ; + RECT 350.875 0.3 351.135 8.7 ; + RECT 351.695 0.3 351.955 8.7 ; + RECT 352.205 0 352.465 8.7 ; + RECT 352.715 0 352.975 8.7 ; + RECT 353.225 0.3 353.485 8.7 ; + RECT 353.735 0.3 353.995 8.7 ; + RECT 354.245 0 354.505 8.7 ; + RECT 354.755 0 355.015 8.7 ; + RECT 355.265 0.52 355.525 8.7 ; + RECT 355.775 0.52 356.035 8.7 ; + RECT 356.285 0.52 356.545 8.7 ; + RECT 358.325 0.18 359.095 0.88 ; + RECT 358.325 0.18 358.585 8.7 ; + RECT 358.835 0.18 359.095 8.7 ; + RECT 356.795 0.52 357.055 8.7 ; + RECT 359.855 0.17 360.625 0.43 ; + RECT 359.855 0.17 360.115 8.7 ; + RECT 360.365 0.17 360.625 8.7 ; + RECT 357.305 0 357.565 8.7 ; + RECT 357.815 0 358.075 8.7 ; + RECT 359.345 0.3 359.605 8.7 ; + RECT 362.405 0.17 363.175 0.43 ; + RECT 362.405 0.17 362.665 8.7 ; + RECT 362.915 0.17 363.175 8.7 ; + RECT 360.875 0.3 361.135 8.7 ; + RECT 361.385 0.3 361.645 8.7 ; + RECT 361.895 0.3 362.155 8.7 ; + RECT 363.425 0.3 363.685 8.7 ; + RECT 363.935 0.3 364.195 8.7 ; + RECT 364.445 0.52 364.705 8.7 ; + RECT 364.955 0.52 365.215 8.7 ; + RECT 365.465 0.3 365.725 8.7 ; + RECT 365.975 0.52 366.235 8.7 ; + RECT 366.485 0.52 366.745 8.7 ; + RECT 366.995 0.3 367.255 8.7 ; + RECT 367.505 0.52 367.765 8.7 ; + RECT 368.015 0.52 368.275 8.7 ; + RECT 368.525 0.52 368.785 8.7 ; + RECT 369.035 0.52 369.295 8.7 ; + RECT 369.545 0.52 369.805 8.7 ; + RECT 370.055 0.3 370.315 8.7 ; + RECT 370.565 0.52 370.825 8.7 ; + RECT 371.075 0.52 371.335 8.7 ; + RECT 371.585 0.3 371.845 8.7 ; + RECT 372.095 0.3 372.355 8.7 ; + RECT 372.605 0.3 372.865 8.7 ; + RECT 373.115 0.52 373.375 8.7 ; + RECT 373.625 0.52 373.885 8.7 ; + RECT 374.135 0.3 374.395 8.7 ; + RECT 374.645 0.3 374.905 8.7 ; + RECT 375.155 0.3 375.415 8.7 ; + RECT 375.665 0.52 375.925 8.7 ; + RECT 376.175 0.52 376.435 8.7 ; + RECT 376.685 0.52 376.945 8.7 ; + RECT 377.195 0.52 377.455 8.7 ; + RECT 377.705 0.52 377.965 8.7 ; + RECT 378.215 0.52 378.475 8.7 ; + RECT 378.725 0.52 378.985 8.7 ; + RECT 380.765 0.18 381.535 0.88 ; + RECT 380.765 0.18 381.025 8.7 ; + RECT 381.275 0.18 381.535 8.7 ; + RECT 379.235 0.52 379.495 8.7 ; + RECT 379.745 0 380.005 8.7 ; + RECT 380.255 0 380.515 8.7 ; + RECT 381.785 0 382.045 8.7 ; + RECT 382.295 0 382.555 8.7 ; + RECT 382.805 0.3 383.065 8.7 ; + RECT 383.315 0.3 383.575 8.7 ; + RECT 383.825 0.3 384.085 8.7 ; + RECT 384.335 0.3 384.595 8.7 ; + RECT 384.845 0.3 385.105 8.7 ; + RECT 385.355 0.3 385.615 8.7 ; + RECT 387.395 0.18 388.165 0.88 ; + RECT 387.395 0.18 387.655 8.7 ; + RECT 387.905 0.18 388.165 8.7 ; + RECT 385.865 0.3 386.125 8.7 ; + RECT 386.375 0.3 386.635 8.7 ; + RECT 389.435 0.17 390.205 0.43 ; + RECT 389.435 0.17 389.695 8.7 ; + RECT 389.945 0.17 390.205 8.7 ; + RECT 390.455 0.18 391.225 0.88 ; + RECT 390.455 0.18 390.715 8.7 ; + RECT 390.965 0.18 391.225 8.7 ; + RECT 386.885 0.52 387.145 8.7 ; + RECT 388.415 0 388.675 8.7 ; + RECT 392.85 0.18 393.62 0.88 ; + RECT 392.85 0.18 393.11 8.7 ; + RECT 393.36 0.18 393.62 8.7 ; + RECT 393.87 0.17 394.64 0.43 ; + RECT 393.87 0.17 394.13 8.7 ; + RECT 394.38 0.17 394.64 8.7 ; + RECT 394.89 0.18 395.66 0.88 ; + RECT 394.89 0.18 395.15 8.7 ; + RECT 395.4 0.18 395.66 8.7 ; + RECT 395.91 0.17 396.68 0.43 ; + RECT 395.91 0.17 396.17 8.7 ; + RECT 396.42 0.17 396.68 8.7 ; + RECT 396.93 0.18 397.7 0.88 ; + RECT 396.93 0.18 397.19 8.7 ; + RECT 397.44 0.18 397.7 8.7 ; + RECT 397.95 0.17 398.72 0.43 ; + RECT 397.95 0.17 398.21 8.7 ; + RECT 398.46 0.17 398.72 8.7 ; + RECT 398.97 0.18 399.74 0.88 ; + RECT 398.97 0.18 399.23 8.7 ; + RECT 399.48 0.18 399.74 8.7 ; + RECT 399.99 0.17 400.76 0.43 ; + RECT 399.99 0.17 400.25 8.7 ; + RECT 400.5 0.17 400.76 8.7 ; + RECT 401.01 0.18 401.78 0.88 ; + RECT 401.01 0.18 401.27 8.7 ; + RECT 401.52 0.18 401.78 8.7 ; + RECT 402.03 0.17 402.8 0.43 ; + RECT 402.03 0.17 402.29 8.7 ; + RECT 402.54 0.17 402.8 8.7 ; + RECT 403.05 0.18 403.82 0.88 ; + RECT 403.05 0.18 403.31 8.7 ; + RECT 403.56 0.18 403.82 8.7 ; + RECT 404.07 0.17 404.84 0.43 ; + RECT 404.07 0.17 404.33 8.7 ; + RECT 404.58 0.17 404.84 8.7 ; + RECT 405.09 0.18 405.86 0.88 ; + RECT 405.09 0.18 405.35 8.7 ; + RECT 405.6 0.18 405.86 8.7 ; + RECT 406.11 0.17 406.88 0.43 ; + RECT 406.11 0.17 406.37 8.7 ; + RECT 406.62 0.17 406.88 8.7 ; + RECT 407.13 0.18 407.9 0.88 ; + RECT 407.13 0.18 407.39 8.7 ; + RECT 407.64 0.18 407.9 8.7 ; + RECT 408.15 0.17 408.92 0.43 ; + RECT 408.15 0.17 408.41 8.7 ; + RECT 408.66 0.17 408.92 8.7 ; + RECT 409.17 0.18 409.94 0.88 ; + RECT 409.17 0.18 409.43 8.7 ; + RECT 409.68 0.18 409.94 8.7 ; + RECT 410.19 0.17 410.96 0.43 ; + RECT 410.19 0.17 410.45 8.7 ; + RECT 410.7 0.17 410.96 8.7 ; + RECT 411.21 0.18 411.98 0.88 ; + RECT 411.21 0.18 411.47 8.7 ; + RECT 411.72 0.18 411.98 8.7 ; + RECT 412.23 0.17 413 0.43 ; + RECT 412.23 0.17 412.49 8.7 ; + RECT 412.74 0.17 413 8.7 ; + RECT 413.25 0.18 414.02 0.88 ; + RECT 413.25 0.18 413.51 8.7 ; + RECT 413.76 0.18 414.02 8.7 ; + RECT 414.27 0.17 415.04 0.43 ; + RECT 414.27 0.17 414.53 8.7 ; + RECT 414.78 0.17 415.04 8.7 ; + RECT 415.29 0.18 416.06 0.88 ; + RECT 415.29 0.18 415.55 8.7 ; + RECT 415.8 0.18 416.06 8.7 ; + RECT 388.925 0 389.185 8.7 ; + RECT 416.31 0.17 417.08 0.43 ; + RECT 416.31 0.17 416.57 8.7 ; + RECT 416.82 0.17 417.08 8.7 ; + RECT 391.475 0.3 391.735 8.7 ; + RECT 391.985 0.3 392.245 8.7 ; + RECT 416.81 136.13 417.01 136.94 ; + RECT 417.635 136.21 417.835 136.94 ; + RECT 418.045 136.21 418.405 136.94 ; + RECT 418.35 0.52 418.61 4.315 ; + RECT 418.615 136.21 418.815 136.94 ; + RECT 419.27 136.21 419.47 136.94 ; + RECT 419.525 0.52 419.785 2.82 ; + RECT 419.68 136.21 420.04 136.94 ; + RECT 420.335 136.21 420.535 136.94 ; + RECT 420.83 136.21 421.19 136.94 ; + RECT 421.765 0.18 422.535 0.88 ; + RECT 421.765 0.18 422.025 12.9 ; + RECT 422.275 0.18 422.535 12.9 ; + RECT 421.055 0.52 421.315 2.82 ; + RECT 421.4 136.21 421.6 136.94 ; + RECT 422.785 0.155 423.555 0.445 ; + RECT 422.785 0.155 423.045 13.21 ; + RECT 423.295 0.155 423.555 13.21 ; + RECT 422.055 136.21 422.255 136.94 ; + RECT 422.465 136.21 422.825 136.94 ; + RECT 423.035 136.21 423.235 136.94 ; + RECT 423.69 136.21 423.89 136.94 ; + RECT 424.1 136.21 424.46 136.94 ; + RECT 424.755 136.21 424.955 136.94 ; + RECT 425.25 136.21 425.61 136.94 ; + RECT 425.49 0.52 425.75 14.115 ; + RECT 425.82 136.21 426.02 136.94 ; + RECT 426 0.52 426.26 13.45 ; + RECT 426.475 136.21 426.675 136.94 ; + RECT 427.02 0.155 427.79 0.445 ; + RECT 427.02 0.155 427.28 8.665 ; + RECT 427.53 0.155 427.79 8.665 ; + RECT 426.51 0.52 426.77 11.315 ; + RECT 426.885 136.21 427.245 136.94 ; + RECT 427.455 136.21 427.655 136.94 ; + RECT 428.04 0.52 428.3 9.955 ; + RECT 428.11 136.21 428.31 136.94 ; + RECT 428.52 136.21 428.88 136.94 ; + RECT 429.175 136.21 429.375 136.94 ; + RECT 429.67 136.21 430.03 136.94 ; + RECT 430.08 0.3 430.34 8.7 ; + RECT 430.24 136.21 430.44 136.94 ; + RECT 430.895 136.21 431.095 136.94 ; + RECT 430.59 0.18 431.36 0.88 ; + RECT 431.305 136.21 431.665 136.94 ; + RECT 431.875 136.21 432.075 136.94 ; + RECT 432.53 136.21 432.73 136.94 ; + RECT 432.785 0.52 433.045 6.28 ; + RECT 432.94 136.21 433.3 136.94 ; + RECT 433.595 136.21 433.795 136.94 ; + RECT 434.16 0.52 434.42 5.57 ; + RECT 434.09 136.21 434.45 136.94 ; + RECT 434.66 136.21 434.86 136.94 ; + RECT 434.67 0.3 434.93 5.235 ; + RECT 435.18 0.52 435.44 7.78 ; + RECT 435.315 136.21 435.515 136.94 ; + RECT 435.725 136.21 436.085 136.94 ; + RECT 436.03 0.52 436.29 4.315 ; + RECT 436.295 136.21 436.495 136.94 ; + RECT 436.95 136.21 437.15 136.94 ; + RECT 437.205 0.52 437.465 2.82 ; + RECT 437.36 136.21 437.72 136.94 ; + RECT 438.015 136.21 438.215 136.94 ; + RECT 438.51 136.21 438.87 136.94 ; + RECT 439.445 0.18 440.215 0.88 ; + RECT 439.445 0.18 439.705 12.9 ; + RECT 439.955 0.18 440.215 12.9 ; + RECT 438.735 0.52 438.995 2.82 ; + RECT 439.08 136.21 439.28 136.94 ; + RECT 440.465 0.155 441.235 0.445 ; + RECT 440.465 0.155 440.725 13.21 ; + RECT 440.975 0.155 441.235 13.21 ; + RECT 439.735 136.21 439.935 136.94 ; + RECT 440.145 136.21 440.505 136.94 ; + RECT 440.715 136.21 440.915 136.94 ; + RECT 441.37 136.21 441.57 136.94 ; + RECT 441.78 136.21 442.14 136.94 ; + RECT 442.435 136.21 442.635 136.94 ; + RECT 442.93 136.21 443.29 136.94 ; + RECT 443.17 0.52 443.43 14.115 ; + RECT 443.5 136.21 443.7 136.94 ; + RECT 443.68 0.52 443.94 13.45 ; + RECT 444.155 136.21 444.355 136.94 ; + RECT 444.7 0.155 445.47 0.445 ; + RECT 444.7 0.155 444.96 8.665 ; + RECT 445.21 0.155 445.47 8.665 ; + RECT 444.19 0.52 444.45 11.315 ; + RECT 444.565 136.21 444.925 136.94 ; + RECT 445.135 136.21 445.335 136.94 ; + RECT 445.72 0.52 445.98 9.955 ; + RECT 445.79 136.21 445.99 136.94 ; + RECT 446.2 136.21 446.56 136.94 ; + RECT 446.855 136.21 447.055 136.94 ; + RECT 447.35 136.21 447.71 136.94 ; + RECT 447.76 0.3 448.02 8.7 ; + RECT 447.92 136.21 448.12 136.94 ; + RECT 448.575 136.21 448.775 136.94 ; + RECT 448.27 0.18 449.04 0.88 ; + RECT 448.985 136.21 449.345 136.94 ; + RECT 449.555 136.21 449.755 136.94 ; + RECT 450.21 136.21 450.41 136.94 ; + RECT 450.465 0.52 450.725 6.28 ; + RECT 450.62 136.21 450.98 136.94 ; + RECT 451.275 136.21 451.475 136.94 ; + RECT 451.84 0.52 452.1 5.57 ; + RECT 451.77 136.21 452.13 136.94 ; + RECT 452.34 136.21 452.54 136.94 ; + RECT 452.35 0.3 452.61 5.235 ; + RECT 452.86 0.52 453.12 7.78 ; + RECT 452.995 136.21 453.195 136.94 ; + RECT 453.405 136.21 453.765 136.94 ; + RECT 453.71 0.52 453.97 4.315 ; + RECT 453.975 136.21 454.175 136.94 ; + RECT 454.63 136.21 454.83 136.94 ; + RECT 454.885 0.52 455.145 2.82 ; + RECT 455.04 136.21 455.4 136.94 ; + RECT 455.695 136.21 455.895 136.94 ; + RECT 456.19 136.21 456.55 136.94 ; + RECT 457.125 0.18 457.895 0.88 ; + RECT 457.125 0.18 457.385 12.9 ; + RECT 457.635 0.18 457.895 12.9 ; + RECT 456.415 0.52 456.675 2.82 ; + RECT 456.76 136.21 456.96 136.94 ; + RECT 458.145 0.155 458.915 0.445 ; + RECT 458.145 0.155 458.405 13.21 ; + RECT 458.655 0.155 458.915 13.21 ; + RECT 457.415 136.21 457.615 136.94 ; + RECT 457.825 136.21 458.185 136.94 ; + RECT 458.395 136.21 458.595 136.94 ; + RECT 459.05 136.21 459.25 136.94 ; + RECT 459.46 136.21 459.82 136.94 ; + RECT 460.115 136.21 460.315 136.94 ; + RECT 460.61 136.21 460.97 136.94 ; + RECT 460.85 0.52 461.11 14.115 ; + RECT 461.18 136.21 461.38 136.94 ; + RECT 461.36 0.52 461.62 13.45 ; + RECT 461.835 136.21 462.035 136.94 ; + RECT 462.38 0.155 463.15 0.445 ; + RECT 462.38 0.155 462.64 8.665 ; + RECT 462.89 0.155 463.15 8.665 ; + RECT 461.87 0.52 462.13 11.315 ; + RECT 462.245 136.21 462.605 136.94 ; + RECT 462.815 136.21 463.015 136.94 ; + RECT 463.4 0.52 463.66 9.955 ; + RECT 463.47 136.21 463.67 136.94 ; + RECT 463.88 136.21 464.24 136.94 ; + RECT 464.535 136.21 464.735 136.94 ; + RECT 465.03 136.21 465.39 136.94 ; + RECT 465.44 0.3 465.7 8.7 ; + RECT 465.6 136.21 465.8 136.94 ; + RECT 466.255 136.21 466.455 136.94 ; + RECT 465.95 0.18 466.72 0.88 ; + RECT 466.665 136.21 467.025 136.94 ; + RECT 467.235 136.21 467.435 136.94 ; + RECT 467.89 136.21 468.09 136.94 ; + RECT 468.145 0.52 468.405 6.28 ; + RECT 468.3 136.21 468.66 136.94 ; + RECT 468.955 136.21 469.155 136.94 ; + RECT 469.52 0.52 469.78 5.57 ; + RECT 469.45 136.21 469.81 136.94 ; + RECT 470.02 136.21 470.22 136.94 ; + RECT 470.03 0.3 470.29 5.235 ; + RECT 470.54 0.52 470.8 7.78 ; + RECT 470.675 136.21 470.875 136.94 ; + RECT 471.085 136.21 471.445 136.94 ; + RECT 471.39 0.52 471.65 4.315 ; + RECT 471.655 136.21 471.855 136.94 ; + RECT 472.31 136.21 472.51 136.94 ; + RECT 472.565 0.52 472.825 2.82 ; + RECT 472.72 136.21 473.08 136.94 ; + RECT 473.375 136.21 473.575 136.94 ; + RECT 473.87 136.21 474.23 136.94 ; + RECT 474.805 0.18 475.575 0.88 ; + RECT 474.805 0.18 475.065 12.9 ; + RECT 475.315 0.18 475.575 12.9 ; + RECT 474.095 0.52 474.355 2.82 ; + RECT 474.44 136.21 474.64 136.94 ; + RECT 475.825 0.155 476.595 0.445 ; + RECT 475.825 0.155 476.085 13.21 ; + RECT 476.335 0.155 476.595 13.21 ; + RECT 475.095 136.21 475.295 136.94 ; + RECT 475.505 136.21 475.865 136.94 ; + RECT 476.075 136.21 476.275 136.94 ; + RECT 476.73 136.21 476.93 136.94 ; + RECT 477.14 136.21 477.5 136.94 ; + RECT 477.795 136.21 477.995 136.94 ; + RECT 478.29 136.21 478.65 136.94 ; + RECT 478.53 0.52 478.79 14.115 ; + RECT 478.86 136.21 479.06 136.94 ; + RECT 479.04 0.52 479.3 13.45 ; + RECT 479.515 136.21 479.715 136.94 ; + RECT 480.06 0.155 480.83 0.445 ; + RECT 480.06 0.155 480.32 8.665 ; + RECT 480.57 0.155 480.83 8.665 ; + RECT 479.55 0.52 479.81 11.315 ; + RECT 479.925 136.21 480.285 136.94 ; + RECT 480.495 136.21 480.695 136.94 ; + RECT 481.08 0.52 481.34 9.955 ; + RECT 481.15 136.21 481.35 136.94 ; + RECT 481.56 136.21 481.92 136.94 ; + RECT 482.215 136.21 482.415 136.94 ; + RECT 482.71 136.21 483.07 136.94 ; + RECT 483.12 0.3 483.38 8.7 ; + RECT 483.28 136.21 483.48 136.94 ; + RECT 483.935 136.21 484.135 136.94 ; + RECT 483.63 0.18 484.4 0.88 ; + RECT 484.345 136.21 484.705 136.94 ; + RECT 484.915 136.21 485.115 136.94 ; + RECT 485.57 136.21 485.77 136.94 ; + RECT 485.825 0.52 486.085 6.28 ; + RECT 485.98 136.21 486.34 136.94 ; + RECT 486.635 136.21 486.835 136.94 ; + RECT 487.2 0.52 487.46 5.57 ; + RECT 487.13 136.21 487.49 136.94 ; + RECT 487.7 136.21 487.9 136.94 ; + RECT 487.71 0.3 487.97 5.235 ; + RECT 488.22 0.52 488.48 7.78 ; + RECT 488.355 136.21 488.555 136.94 ; + RECT 488.765 136.21 489.125 136.94 ; + RECT 489.07 0.52 489.33 4.315 ; + RECT 489.335 136.21 489.535 136.94 ; + RECT 489.99 136.21 490.19 136.94 ; + RECT 490.245 0.52 490.505 2.82 ; + RECT 490.4 136.21 490.76 136.94 ; + RECT 491.055 136.21 491.255 136.94 ; + RECT 491.55 136.21 491.91 136.94 ; + RECT 492.485 0.18 493.255 0.88 ; + RECT 492.485 0.18 492.745 12.9 ; + RECT 492.995 0.18 493.255 12.9 ; + RECT 491.775 0.52 492.035 2.82 ; + RECT 492.12 136.21 492.32 136.94 ; + RECT 493.505 0.155 494.275 0.445 ; + RECT 493.505 0.155 493.765 13.21 ; + RECT 494.015 0.155 494.275 13.21 ; + RECT 492.775 136.21 492.975 136.94 ; + RECT 493.185 136.21 493.545 136.94 ; + RECT 493.755 136.21 493.955 136.94 ; + RECT 494.41 136.21 494.61 136.94 ; + RECT 494.82 136.21 495.18 136.94 ; + RECT 495.475 136.21 495.675 136.94 ; + RECT 495.97 136.21 496.33 136.94 ; + RECT 496.21 0.52 496.47 14.115 ; + RECT 496.54 136.21 496.74 136.94 ; + RECT 496.72 0.52 496.98 13.45 ; + RECT 497.195 136.21 497.395 136.94 ; + RECT 497.74 0.155 498.51 0.445 ; + RECT 497.74 0.155 498 8.665 ; + RECT 498.25 0.155 498.51 8.665 ; + RECT 497.23 0.52 497.49 11.315 ; + RECT 497.605 136.21 497.965 136.94 ; + RECT 498.175 136.21 498.375 136.94 ; + RECT 498.76 0.52 499.02 9.955 ; + RECT 498.83 136.21 499.03 136.94 ; + RECT 499.24 136.21 499.6 136.94 ; + RECT 499.895 136.21 500.095 136.94 ; + RECT 500.39 136.21 500.75 136.94 ; + RECT 500.8 0.3 501.06 8.7 ; + RECT 500.96 136.21 501.16 136.94 ; + RECT 501.615 136.21 501.815 136.94 ; + RECT 501.31 0.18 502.08 0.88 ; + RECT 502.025 136.21 502.385 136.94 ; + RECT 502.595 136.21 502.795 136.94 ; + RECT 503.25 136.21 503.45 136.94 ; + RECT 503.505 0.52 503.765 6.28 ; + RECT 503.66 136.21 504.02 136.94 ; + RECT 504.315 136.21 504.515 136.94 ; + RECT 504.88 0.52 505.14 5.57 ; + RECT 504.81 136.21 505.17 136.94 ; + RECT 505.38 136.21 505.58 136.94 ; + RECT 505.39 0.3 505.65 5.235 ; + RECT 505.9 0.52 506.16 7.78 ; + RECT 506.035 136.21 506.235 136.94 ; + RECT 506.445 136.21 506.805 136.94 ; + RECT 506.75 0.52 507.01 4.315 ; + RECT 507.015 136.21 507.215 136.94 ; + RECT 507.67 136.21 507.87 136.94 ; + RECT 507.925 0.52 508.185 2.82 ; + RECT 508.08 136.21 508.44 136.94 ; + RECT 508.735 136.21 508.935 136.94 ; + RECT 509.23 136.21 509.59 136.94 ; + RECT 510.165 0.18 510.935 0.88 ; + RECT 510.165 0.18 510.425 12.9 ; + RECT 510.675 0.18 510.935 12.9 ; + RECT 509.455 0.52 509.715 2.82 ; + RECT 509.8 136.21 510 136.94 ; + RECT 511.185 0.155 511.955 0.445 ; + RECT 511.185 0.155 511.445 13.21 ; + RECT 511.695 0.155 511.955 13.21 ; + RECT 510.455 136.21 510.655 136.94 ; + RECT 510.865 136.21 511.225 136.94 ; + RECT 511.435 136.21 511.635 136.94 ; + RECT 512.09 136.21 512.29 136.94 ; + RECT 512.5 136.21 512.86 136.94 ; + RECT 513.155 136.21 513.355 136.94 ; + RECT 513.65 136.21 514.01 136.94 ; + RECT 513.89 0.52 514.15 14.115 ; + RECT 514.22 136.21 514.42 136.94 ; + RECT 514.4 0.52 514.66 13.45 ; + RECT 514.875 136.21 515.075 136.94 ; + RECT 515.42 0.155 516.19 0.445 ; + RECT 515.42 0.155 515.68 8.665 ; + RECT 515.93 0.155 516.19 8.665 ; + RECT 514.91 0.52 515.17 11.315 ; + RECT 515.285 136.21 515.645 136.94 ; + RECT 515.855 136.21 516.055 136.94 ; + RECT 516.44 0.52 516.7 9.955 ; + RECT 516.51 136.21 516.71 136.94 ; + RECT 516.92 136.21 517.28 136.94 ; + RECT 517.575 136.21 517.775 136.94 ; + RECT 518.07 136.21 518.43 136.94 ; + RECT 518.48 0.3 518.74 8.7 ; + RECT 518.64 136.21 518.84 136.94 ; + RECT 519.295 136.21 519.495 136.94 ; + RECT 518.99 0.18 519.76 0.88 ; + RECT 519.705 136.21 520.065 136.94 ; + RECT 520.275 136.21 520.475 136.94 ; + RECT 520.93 136.21 521.13 136.94 ; + RECT 521.185 0.52 521.445 6.28 ; + RECT 521.34 136.21 521.7 136.94 ; + RECT 521.995 136.21 522.195 136.94 ; + RECT 522.56 0.52 522.82 5.57 ; + RECT 522.49 136.21 522.85 136.94 ; + RECT 523.06 136.21 523.26 136.94 ; + RECT 523.07 0.3 523.33 5.235 ; + RECT 523.58 0.52 523.84 7.78 ; + RECT 523.715 136.21 523.915 136.94 ; + RECT 524.125 136.21 524.485 136.94 ; + RECT 524.43 0.52 524.69 4.315 ; + RECT 524.695 136.21 524.895 136.94 ; + RECT 525.35 136.21 525.55 136.94 ; + RECT 525.605 0.52 525.865 2.82 ; + RECT 525.76 136.21 526.12 136.94 ; + RECT 526.415 136.21 526.615 136.94 ; + RECT 526.91 136.21 527.27 136.94 ; + RECT 527.845 0.18 528.615 0.88 ; + RECT 527.845 0.18 528.105 12.9 ; + RECT 528.355 0.18 528.615 12.9 ; + RECT 527.135 0.52 527.395 2.82 ; + RECT 527.48 136.21 527.68 136.94 ; + RECT 528.865 0.155 529.635 0.445 ; + RECT 528.865 0.155 529.125 13.21 ; + RECT 529.375 0.155 529.635 13.21 ; + RECT 528.135 136.21 528.335 136.94 ; + RECT 528.545 136.21 528.905 136.94 ; + RECT 529.115 136.21 529.315 136.94 ; + RECT 529.77 136.21 529.97 136.94 ; + RECT 530.18 136.21 530.54 136.94 ; + RECT 530.835 136.21 531.035 136.94 ; + RECT 531.33 136.21 531.69 136.94 ; + RECT 531.57 0.52 531.83 14.115 ; + RECT 531.9 136.21 532.1 136.94 ; + RECT 532.08 0.52 532.34 13.45 ; + RECT 532.555 136.21 532.755 136.94 ; + RECT 533.1 0.155 533.87 0.445 ; + RECT 533.1 0.155 533.36 8.665 ; + RECT 533.61 0.155 533.87 8.665 ; + RECT 532.59 0.52 532.85 11.315 ; + RECT 532.965 136.21 533.325 136.94 ; + RECT 533.535 136.21 533.735 136.94 ; + RECT 534.12 0.52 534.38 9.955 ; + RECT 534.19 136.21 534.39 136.94 ; + RECT 534.6 136.21 534.96 136.94 ; + RECT 535.255 136.21 535.455 136.94 ; + RECT 535.75 136.21 536.11 136.94 ; + RECT 536.16 0.3 536.42 8.7 ; + RECT 536.32 136.21 536.52 136.94 ; + RECT 536.975 136.21 537.175 136.94 ; + RECT 536.67 0.18 537.44 0.88 ; + RECT 537.385 136.21 537.745 136.94 ; + RECT 537.955 136.21 538.155 136.94 ; + RECT 538.61 136.21 538.81 136.94 ; + RECT 538.865 0.52 539.125 6.28 ; + RECT 539.02 136.21 539.38 136.94 ; + RECT 539.675 136.21 539.875 136.94 ; + RECT 540.24 0.52 540.5 5.57 ; + RECT 540.17 136.21 540.53 136.94 ; + RECT 540.74 136.21 540.94 136.94 ; + RECT 540.75 0.3 541.01 5.235 ; + RECT 541.26 0.52 541.52 7.78 ; + RECT 541.395 136.21 541.595 136.94 ; + RECT 541.805 136.21 542.165 136.94 ; + RECT 542.11 0.52 542.37 4.315 ; + RECT 542.375 136.21 542.575 136.94 ; + RECT 543.03 136.21 543.23 136.94 ; + RECT 543.285 0.52 543.545 2.82 ; + RECT 543.44 136.21 543.8 136.94 ; + RECT 544.095 136.21 544.295 136.94 ; + RECT 544.59 136.21 544.95 136.94 ; + RECT 545.525 0.18 546.295 0.88 ; + RECT 545.525 0.18 545.785 12.9 ; + RECT 546.035 0.18 546.295 12.9 ; + RECT 544.815 0.52 545.075 2.82 ; + RECT 545.16 136.21 545.36 136.94 ; + RECT 546.545 0.155 547.315 0.445 ; + RECT 546.545 0.155 546.805 13.21 ; + RECT 547.055 0.155 547.315 13.21 ; + RECT 545.815 136.21 546.015 136.94 ; + RECT 546.225 136.21 546.585 136.94 ; + RECT 546.795 136.21 546.995 136.94 ; + RECT 547.45 136.21 547.65 136.94 ; + RECT 547.86 136.21 548.22 136.94 ; + RECT 548.515 136.21 548.715 136.94 ; + RECT 549.01 136.21 549.37 136.94 ; + RECT 549.25 0.52 549.51 14.115 ; + RECT 549.58 136.21 549.78 136.94 ; + RECT 549.76 0.52 550.02 13.45 ; + RECT 550.235 136.21 550.435 136.94 ; + RECT 550.78 0.155 551.55 0.445 ; + RECT 550.78 0.155 551.04 8.665 ; + RECT 551.29 0.155 551.55 8.665 ; + RECT 550.27 0.52 550.53 11.315 ; + RECT 550.645 136.21 551.005 136.94 ; + RECT 551.215 136.21 551.415 136.94 ; + RECT 551.8 0.52 552.06 9.955 ; + RECT 551.87 136.21 552.07 136.94 ; + RECT 552.28 136.21 552.64 136.94 ; + RECT 552.935 136.21 553.135 136.94 ; + RECT 553.43 136.21 553.79 136.94 ; + RECT 553.84 0.3 554.1 8.7 ; + RECT 554 136.21 554.2 136.94 ; + RECT 554.655 136.21 554.855 136.94 ; + RECT 554.35 0.18 555.12 0.88 ; + RECT 555.065 136.21 555.425 136.94 ; + RECT 555.635 136.21 555.835 136.94 ; + RECT 556.29 136.21 556.49 136.94 ; + RECT 556.545 0.52 556.805 6.28 ; + RECT 556.7 136.21 557.06 136.94 ; + RECT 557.355 136.21 557.555 136.94 ; + RECT 557.92 0.52 558.18 5.57 ; + RECT 557.85 136.21 558.21 136.94 ; + RECT 558.42 136.21 558.62 136.94 ; + RECT 558.43 0.3 558.69 5.235 ; + RECT 558.94 0.52 559.2 7.78 ; + RECT 559.075 136.21 559.275 136.94 ; + RECT 559.485 136.21 559.845 136.94 ; + RECT 559.79 0.52 560.05 4.315 ; + RECT 560.055 136.21 560.255 136.94 ; + RECT 560.71 136.21 560.91 136.94 ; + RECT 560.965 0.52 561.225 2.82 ; + RECT 561.12 136.21 561.48 136.94 ; + RECT 561.775 136.21 561.975 136.94 ; + RECT 562.27 136.21 562.63 136.94 ; + RECT 563.205 0.18 563.975 0.88 ; + RECT 563.205 0.18 563.465 12.9 ; + RECT 563.715 0.18 563.975 12.9 ; + RECT 562.495 0.52 562.755 2.82 ; + RECT 562.84 136.21 563.04 136.94 ; + RECT 564.225 0.155 564.995 0.445 ; + RECT 564.225 0.155 564.485 13.21 ; + RECT 564.735 0.155 564.995 13.21 ; + RECT 563.495 136.21 563.695 136.94 ; + RECT 563.905 136.21 564.265 136.94 ; + RECT 564.475 136.21 564.675 136.94 ; + RECT 565.13 136.21 565.33 136.94 ; + RECT 565.54 136.21 565.9 136.94 ; + RECT 566.195 136.21 566.395 136.94 ; + RECT 566.69 136.21 567.05 136.94 ; + RECT 566.93 0.52 567.19 14.115 ; + RECT 567.26 136.21 567.46 136.94 ; + RECT 567.44 0.52 567.7 13.45 ; + RECT 567.915 136.21 568.115 136.94 ; + RECT 568.46 0.155 569.23 0.445 ; + RECT 568.46 0.155 568.72 8.665 ; + RECT 568.97 0.155 569.23 8.665 ; + RECT 567.95 0.52 568.21 11.315 ; + RECT 568.325 136.21 568.685 136.94 ; + RECT 568.895 136.21 569.095 136.94 ; + RECT 569.48 0.52 569.74 9.955 ; + RECT 569.55 136.21 569.75 136.94 ; + RECT 569.96 136.21 570.32 136.94 ; + RECT 570.615 136.21 570.815 136.94 ; + RECT 571.11 136.21 571.47 136.94 ; + RECT 571.52 0.3 571.78 8.7 ; + RECT 571.68 136.21 571.88 136.94 ; + RECT 572.335 136.21 572.535 136.94 ; + RECT 572.03 0.18 572.8 0.88 ; + RECT 572.745 136.21 573.105 136.94 ; + RECT 573.315 136.21 573.515 136.94 ; + RECT 573.97 136.21 574.17 136.94 ; + RECT 574.225 0.52 574.485 6.28 ; + RECT 574.38 136.21 574.74 136.94 ; + RECT 575.035 136.21 575.235 136.94 ; + RECT 575.6 0.52 575.86 5.57 ; + RECT 575.53 136.21 575.89 136.94 ; + RECT 576.1 136.21 576.3 136.94 ; + RECT 576.11 0.3 576.37 5.235 ; + RECT 576.62 0.52 576.88 7.78 ; + RECT 576.755 136.21 576.955 136.94 ; + RECT 577.165 136.21 577.525 136.94 ; + RECT 577.47 0.52 577.73 4.315 ; + RECT 577.735 136.21 577.935 136.94 ; + RECT 578.39 136.21 578.59 136.94 ; + RECT 578.645 0.52 578.905 2.82 ; + RECT 578.8 136.21 579.16 136.94 ; + RECT 579.455 136.21 579.655 136.94 ; + RECT 579.95 136.21 580.31 136.94 ; + RECT 580.885 0.18 581.655 0.88 ; + RECT 580.885 0.18 581.145 12.9 ; + RECT 581.395 0.18 581.655 12.9 ; + RECT 580.175 0.52 580.435 2.82 ; + RECT 580.52 136.21 580.72 136.94 ; + RECT 581.905 0.155 582.675 0.445 ; + RECT 581.905 0.155 582.165 13.21 ; + RECT 582.415 0.155 582.675 13.21 ; + RECT 581.175 136.21 581.375 136.94 ; + RECT 581.585 136.21 581.945 136.94 ; + RECT 582.155 136.21 582.355 136.94 ; + RECT 582.81 136.21 583.01 136.94 ; + RECT 583.22 136.21 583.58 136.94 ; + RECT 583.875 136.21 584.075 136.94 ; + RECT 584.37 136.21 584.73 136.94 ; + RECT 584.61 0.52 584.87 14.115 ; + RECT 584.94 136.21 585.14 136.94 ; + RECT 585.12 0.52 585.38 13.45 ; + RECT 585.595 136.21 585.795 136.94 ; + RECT 586.14 0.155 586.91 0.445 ; + RECT 586.14 0.155 586.4 8.665 ; + RECT 586.65 0.155 586.91 8.665 ; + RECT 585.63 0.52 585.89 11.315 ; + RECT 586.005 136.21 586.365 136.94 ; + RECT 586.575 136.21 586.775 136.94 ; + RECT 587.16 0.52 587.42 9.955 ; + RECT 587.23 136.21 587.43 136.94 ; + RECT 587.64 136.21 588 136.94 ; + RECT 588.295 136.21 588.495 136.94 ; + RECT 588.79 136.21 589.15 136.94 ; + RECT 589.2 0.3 589.46 8.7 ; + RECT 589.36 136.21 589.56 136.94 ; + RECT 590.015 136.21 590.215 136.94 ; + RECT 589.71 0.18 590.48 0.88 ; + RECT 590.425 136.21 590.785 136.94 ; + RECT 590.995 136.21 591.195 136.94 ; + RECT 591.65 136.21 591.85 136.94 ; + RECT 591.905 0.52 592.165 6.28 ; + RECT 592.06 136.21 592.42 136.94 ; + RECT 592.715 136.21 592.915 136.94 ; + RECT 593.28 0.52 593.54 5.57 ; + RECT 593.21 136.21 593.57 136.94 ; + RECT 593.78 136.21 593.98 136.94 ; + RECT 593.79 0.3 594.05 5.235 ; + RECT 594.3 0.52 594.56 7.78 ; + RECT 594.435 136.21 594.635 136.94 ; + RECT 594.845 136.21 595.205 136.94 ; + RECT 595.15 0.52 595.41 4.315 ; + RECT 595.415 136.21 595.615 136.94 ; + RECT 596.07 136.21 596.27 136.94 ; + RECT 596.325 0.52 596.585 2.82 ; + RECT 596.48 136.21 596.84 136.94 ; + RECT 597.135 136.21 597.335 136.94 ; + RECT 597.63 136.21 597.99 136.94 ; + RECT 598.565 0.18 599.335 0.88 ; + RECT 598.565 0.18 598.825 12.9 ; + RECT 599.075 0.18 599.335 12.9 ; + RECT 597.855 0.52 598.115 2.82 ; + RECT 598.2 136.21 598.4 136.94 ; + RECT 599.585 0.155 600.355 0.445 ; + RECT 599.585 0.155 599.845 13.21 ; + RECT 600.095 0.155 600.355 13.21 ; + RECT 598.855 136.21 599.055 136.94 ; + RECT 599.265 136.21 599.625 136.94 ; + RECT 599.835 136.21 600.035 136.94 ; + RECT 600.49 136.21 600.69 136.94 ; + RECT 600.9 136.21 601.26 136.94 ; + RECT 601.555 136.21 601.755 136.94 ; + RECT 602.05 136.21 602.41 136.94 ; + RECT 602.29 0.52 602.55 14.115 ; + RECT 602.62 136.21 602.82 136.94 ; + RECT 602.8 0.52 603.06 13.45 ; + RECT 603.275 136.21 603.475 136.94 ; + RECT 603.82 0.155 604.59 0.445 ; + RECT 603.82 0.155 604.08 8.665 ; + RECT 604.33 0.155 604.59 8.665 ; + RECT 603.31 0.52 603.57 11.315 ; + RECT 603.685 136.21 604.045 136.94 ; + RECT 604.255 136.21 604.455 136.94 ; + RECT 604.84 0.52 605.1 9.955 ; + RECT 604.91 136.21 605.11 136.94 ; + RECT 605.32 136.21 605.68 136.94 ; + RECT 605.975 136.21 606.175 136.94 ; + RECT 606.47 136.21 606.83 136.94 ; + RECT 606.88 0.3 607.14 8.7 ; + RECT 607.04 136.21 607.24 136.94 ; + RECT 607.695 136.21 607.895 136.94 ; + RECT 607.39 0.18 608.16 0.88 ; + RECT 608.105 136.21 608.465 136.94 ; + RECT 608.675 136.21 608.875 136.94 ; + RECT 609.33 136.21 609.53 136.94 ; + RECT 609.585 0.52 609.845 6.28 ; + RECT 609.74 136.21 610.1 136.94 ; + RECT 610.395 136.21 610.595 136.94 ; + RECT 610.96 0.52 611.22 5.57 ; + RECT 610.89 136.21 611.25 136.94 ; + RECT 611.46 136.21 611.66 136.94 ; + RECT 611.47 0.3 611.73 5.235 ; + RECT 611.98 0.52 612.24 7.78 ; + RECT 612.115 136.21 612.315 136.94 ; + RECT 612.525 136.21 612.885 136.94 ; + RECT 612.83 0.52 613.09 4.315 ; + RECT 613.095 136.21 613.295 136.94 ; + RECT 613.75 136.21 613.95 136.94 ; + RECT 614.005 0.52 614.265 2.82 ; + RECT 614.16 136.21 614.52 136.94 ; + RECT 614.815 136.21 615.015 136.94 ; + RECT 615.31 136.21 615.67 136.94 ; + RECT 616.245 0.18 617.015 0.88 ; + RECT 616.245 0.18 616.505 12.9 ; + RECT 616.755 0.18 617.015 12.9 ; + RECT 615.535 0.52 615.795 2.82 ; + RECT 615.88 136.21 616.08 136.94 ; + RECT 617.265 0.155 618.035 0.445 ; + RECT 617.265 0.155 617.525 13.21 ; + RECT 617.775 0.155 618.035 13.21 ; + RECT 616.535 136.21 616.735 136.94 ; + RECT 616.945 136.21 617.305 136.94 ; + RECT 617.515 136.21 617.715 136.94 ; + RECT 618.17 136.21 618.37 136.94 ; + RECT 618.58 136.21 618.94 136.94 ; + RECT 619.235 136.21 619.435 136.94 ; + RECT 619.73 136.21 620.09 136.94 ; + RECT 619.97 0.52 620.23 14.115 ; + RECT 620.3 136.21 620.5 136.94 ; + RECT 620.48 0.52 620.74 13.45 ; + RECT 620.955 136.21 621.155 136.94 ; + RECT 621.5 0.155 622.27 0.445 ; + RECT 621.5 0.155 621.76 8.665 ; + RECT 622.01 0.155 622.27 8.665 ; + RECT 620.99 0.52 621.25 11.315 ; + RECT 621.365 136.21 621.725 136.94 ; + RECT 621.935 136.21 622.135 136.94 ; + RECT 622.52 0.52 622.78 9.955 ; + RECT 622.59 136.21 622.79 136.94 ; + RECT 623 136.21 623.36 136.94 ; + RECT 623.655 136.21 623.855 136.94 ; + RECT 624.15 136.21 624.51 136.94 ; + RECT 624.56 0.3 624.82 8.7 ; + RECT 624.72 136.21 624.92 136.94 ; + RECT 625.375 136.21 625.575 136.94 ; + RECT 625.07 0.18 625.84 0.88 ; + RECT 625.785 136.21 626.145 136.94 ; + RECT 626.355 136.21 626.555 136.94 ; + RECT 627.01 136.21 627.21 136.94 ; + RECT 627.265 0.52 627.525 6.28 ; + RECT 627.42 136.21 627.78 136.94 ; + RECT 628.075 136.21 628.275 136.94 ; + RECT 628.64 0.52 628.9 5.57 ; + RECT 628.57 136.21 628.93 136.94 ; + RECT 629.14 136.21 629.34 136.94 ; + RECT 629.15 0.3 629.41 5.235 ; + RECT 629.66 0.52 629.92 7.78 ; + RECT 629.795 136.21 629.995 136.94 ; + RECT 630.205 136.21 630.565 136.94 ; + RECT 630.51 0.52 630.77 4.315 ; + RECT 630.775 136.21 630.975 136.94 ; + RECT 631.43 136.21 631.63 136.94 ; + RECT 631.685 0.52 631.945 2.82 ; + RECT 631.84 136.21 632.2 136.94 ; + RECT 632.495 136.21 632.695 136.94 ; + RECT 632.99 136.21 633.35 136.94 ; + RECT 633.925 0.18 634.695 0.88 ; + RECT 633.925 0.18 634.185 12.9 ; + RECT 634.435 0.18 634.695 12.9 ; + RECT 633.215 0.52 633.475 2.82 ; + RECT 633.56 136.21 633.76 136.94 ; + RECT 634.945 0.155 635.715 0.445 ; + RECT 634.945 0.155 635.205 13.21 ; + RECT 635.455 0.155 635.715 13.21 ; + RECT 634.215 136.21 634.415 136.94 ; + RECT 634.625 136.21 634.985 136.94 ; + RECT 635.195 136.21 635.395 136.94 ; + RECT 635.85 136.21 636.05 136.94 ; + RECT 636.26 136.21 636.62 136.94 ; + RECT 636.915 136.21 637.115 136.94 ; + RECT 637.41 136.21 637.77 136.94 ; + RECT 637.65 0.52 637.91 14.115 ; + RECT 637.98 136.21 638.18 136.94 ; + RECT 638.16 0.52 638.42 13.45 ; + RECT 638.635 136.21 638.835 136.94 ; + RECT 639.18 0.155 639.95 0.445 ; + RECT 639.18 0.155 639.44 8.665 ; + RECT 639.69 0.155 639.95 8.665 ; + RECT 638.67 0.52 638.93 11.315 ; + RECT 639.045 136.21 639.405 136.94 ; + RECT 639.615 136.21 639.815 136.94 ; + RECT 640.2 0.52 640.46 9.955 ; + RECT 640.27 136.21 640.47 136.94 ; + RECT 640.68 136.21 641.04 136.94 ; + RECT 641.335 136.21 641.535 136.94 ; + RECT 641.83 136.21 642.19 136.94 ; + RECT 642.24 0.3 642.5 8.7 ; + RECT 642.4 136.21 642.6 136.94 ; + RECT 643.055 136.21 643.255 136.94 ; + RECT 642.75 0.18 643.52 0.88 ; + RECT 643.465 136.21 643.825 136.94 ; + RECT 644.035 136.21 644.235 136.94 ; + RECT 644.69 136.21 644.89 136.94 ; + RECT 644.945 0.52 645.205 6.28 ; + RECT 645.1 136.21 645.46 136.94 ; + RECT 645.755 136.21 645.955 136.94 ; + RECT 646.32 0.52 646.58 5.57 ; + RECT 646.25 136.21 646.61 136.94 ; + RECT 646.82 136.21 647.02 136.94 ; + RECT 646.83 0.3 647.09 5.235 ; + RECT 647.34 0.52 647.6 7.78 ; + RECT 647.475 136.21 647.675 136.94 ; + RECT 647.885 136.21 648.245 136.94 ; + RECT 648.19 0.52 648.45 4.315 ; + RECT 648.455 136.21 648.655 136.94 ; + RECT 649.11 136.21 649.31 136.94 ; + RECT 649.365 0.52 649.625 2.82 ; + RECT 649.52 136.21 649.88 136.94 ; + RECT 650.175 136.21 650.375 136.94 ; + RECT 650.67 136.21 651.03 136.94 ; + RECT 651.605 0.18 652.375 0.88 ; + RECT 651.605 0.18 651.865 12.9 ; + RECT 652.115 0.18 652.375 12.9 ; + RECT 650.895 0.52 651.155 2.82 ; + RECT 651.24 136.21 651.44 136.94 ; + RECT 652.625 0.155 653.395 0.445 ; + RECT 652.625 0.155 652.885 13.21 ; + RECT 653.135 0.155 653.395 13.21 ; + RECT 651.895 136.21 652.095 136.94 ; + RECT 652.305 136.21 652.665 136.94 ; + RECT 652.875 136.21 653.075 136.94 ; + RECT 653.53 136.21 653.73 136.94 ; + RECT 653.94 136.21 654.3 136.94 ; + RECT 654.595 136.21 654.795 136.94 ; + RECT 655.09 136.21 655.45 136.94 ; + RECT 655.33 0.52 655.59 14.115 ; + RECT 655.66 136.21 655.86 136.94 ; + RECT 655.84 0.52 656.1 13.45 ; + RECT 656.315 136.21 656.515 136.94 ; + RECT 656.86 0.155 657.63 0.445 ; + RECT 656.86 0.155 657.12 8.665 ; + RECT 657.37 0.155 657.63 8.665 ; + RECT 656.35 0.52 656.61 11.315 ; + RECT 656.725 136.21 657.085 136.94 ; + RECT 657.295 136.21 657.495 136.94 ; + RECT 657.88 0.52 658.14 9.955 ; + RECT 657.95 136.21 658.15 136.94 ; + RECT 658.36 136.21 658.72 136.94 ; + RECT 659.015 136.21 659.215 136.94 ; + RECT 659.51 136.21 659.87 136.94 ; + RECT 659.92 0.3 660.18 8.7 ; + RECT 660.08 136.21 660.28 136.94 ; + RECT 660.735 136.21 660.935 136.94 ; + RECT 660.43 0.18 661.2 0.88 ; + RECT 661.145 136.21 661.505 136.94 ; + RECT 661.715 136.21 661.915 136.94 ; + RECT 662.37 136.21 662.57 136.94 ; + RECT 662.625 0.52 662.885 6.28 ; + RECT 662.78 136.21 663.14 136.94 ; + RECT 663.435 136.21 663.635 136.94 ; + RECT 664 0.52 664.26 5.57 ; + RECT 663.93 136.21 664.29 136.94 ; + RECT 664.5 136.21 664.7 136.94 ; + RECT 664.51 0.3 664.77 5.235 ; + RECT 665.02 0.52 665.28 7.78 ; + RECT 665.155 136.21 665.355 136.94 ; + RECT 665.565 136.21 665.925 136.94 ; + RECT 665.87 0.52 666.13 4.315 ; + RECT 666.135 136.21 666.335 136.94 ; + RECT 666.79 136.21 666.99 136.94 ; + RECT 667.045 0.52 667.305 2.82 ; + RECT 667.2 136.21 667.56 136.94 ; + RECT 667.855 136.21 668.055 136.94 ; + RECT 668.35 136.21 668.71 136.94 ; + RECT 669.285 0.18 670.055 0.88 ; + RECT 669.285 0.18 669.545 12.9 ; + RECT 669.795 0.18 670.055 12.9 ; + RECT 668.575 0.52 668.835 2.82 ; + RECT 668.92 136.21 669.12 136.94 ; + RECT 670.305 0.155 671.075 0.445 ; + RECT 670.305 0.155 670.565 13.21 ; + RECT 670.815 0.155 671.075 13.21 ; + RECT 669.575 136.21 669.775 136.94 ; + RECT 669.985 136.21 670.345 136.94 ; + RECT 670.555 136.21 670.755 136.94 ; + RECT 671.21 136.21 671.41 136.94 ; + RECT 671.62 136.21 671.98 136.94 ; + RECT 672.275 136.21 672.475 136.94 ; + RECT 672.77 136.21 673.13 136.94 ; + RECT 673.01 0.52 673.27 14.115 ; + RECT 673.34 136.21 673.54 136.94 ; + RECT 673.52 0.52 673.78 13.45 ; + RECT 673.995 136.21 674.195 136.94 ; + RECT 674.54 0.155 675.31 0.445 ; + RECT 674.54 0.155 674.8 8.665 ; + RECT 675.05 0.155 675.31 8.665 ; + RECT 674.03 0.52 674.29 11.315 ; + RECT 674.405 136.21 674.765 136.94 ; + RECT 674.975 136.21 675.175 136.94 ; + RECT 675.56 0.52 675.82 9.955 ; + RECT 675.63 136.21 675.83 136.94 ; + RECT 676.04 136.21 676.4 136.94 ; + RECT 676.695 136.21 676.895 136.94 ; + RECT 677.19 136.21 677.55 136.94 ; + RECT 677.6 0.3 677.86 8.7 ; + RECT 677.76 136.21 677.96 136.94 ; + RECT 678.415 136.21 678.615 136.94 ; + RECT 678.11 0.18 678.88 0.88 ; + RECT 678.825 136.21 679.185 136.94 ; + RECT 679.395 136.21 679.595 136.94 ; + RECT 680.05 136.21 680.25 136.94 ; + RECT 680.305 0.52 680.565 6.28 ; + RECT 680.46 136.21 680.82 136.94 ; + RECT 681.115 136.21 681.315 136.94 ; + RECT 681.68 0.52 681.94 5.57 ; + RECT 681.61 136.21 681.97 136.94 ; + RECT 682.18 136.21 682.38 136.94 ; + RECT 682.19 0.3 682.45 5.235 ; + RECT 682.7 0.52 682.96 7.78 ; + RECT 682.835 136.21 683.035 136.94 ; + RECT 683.245 136.21 683.605 136.94 ; + RECT 683.55 0.52 683.81 4.315 ; + RECT 683.815 136.21 684.015 136.94 ; + RECT 684.47 136.21 684.67 136.94 ; + RECT 684.725 0.52 684.985 2.82 ; + RECT 684.88 136.21 685.24 136.94 ; + RECT 685.535 136.21 685.735 136.94 ; + RECT 686.03 136.21 686.39 136.94 ; + RECT 686.965 0.18 687.735 0.88 ; + RECT 686.965 0.18 687.225 12.9 ; + RECT 687.475 0.18 687.735 12.9 ; + RECT 686.255 0.52 686.515 2.82 ; + RECT 686.6 136.21 686.8 136.94 ; + RECT 687.985 0.155 688.755 0.445 ; + RECT 687.985 0.155 688.245 13.21 ; + RECT 688.495 0.155 688.755 13.21 ; + RECT 687.255 136.21 687.455 136.94 ; + RECT 687.665 136.21 688.025 136.94 ; + RECT 688.235 136.21 688.435 136.94 ; + RECT 688.89 136.21 689.09 136.94 ; + RECT 689.3 136.21 689.66 136.94 ; + RECT 689.955 136.21 690.155 136.94 ; + RECT 690.45 136.21 690.81 136.94 ; + RECT 690.69 0.52 690.95 14.115 ; + RECT 691.02 136.21 691.22 136.94 ; + RECT 691.2 0.52 691.46 13.45 ; + RECT 691.675 136.21 691.875 136.94 ; + RECT 692.22 0.155 692.99 0.445 ; + RECT 692.22 0.155 692.48 8.665 ; + RECT 692.73 0.155 692.99 8.665 ; + RECT 691.71 0.52 691.97 11.315 ; + RECT 692.085 136.21 692.445 136.94 ; + RECT 692.655 136.21 692.855 136.94 ; + RECT 693.24 0.52 693.5 9.955 ; + RECT 693.31 136.21 693.51 136.94 ; + RECT 693.72 136.21 694.08 136.94 ; + RECT 694.375 136.21 694.575 136.94 ; + RECT 694.87 136.21 695.23 136.94 ; + RECT 695.28 0.3 695.54 8.7 ; + RECT 695.44 136.21 695.64 136.94 ; + RECT 696.095 136.21 696.295 136.94 ; + RECT 695.79 0.18 696.56 0.88 ; + RECT 696.505 136.21 696.865 136.94 ; + RECT 697.075 136.21 697.275 136.94 ; + RECT 697.73 136.21 697.93 136.94 ; + RECT 697.985 0.52 698.245 6.28 ; + RECT 698.14 136.21 698.5 136.94 ; + RECT 698.795 136.21 698.995 136.94 ; + RECT 699.36 0.52 699.62 5.57 ; + RECT 699.29 136.21 699.65 136.94 ; + RECT 699.86 136.21 700.06 136.94 ; + RECT 699.87 0.3 700.13 5.235 ; + RECT 700.38 0.52 700.64 7.78 ; + RECT 700.515 136.21 700.715 136.94 ; + RECT 700.925 136.21 701.285 136.94 ; + RECT 701.495 136.21 701.695 136.94 ; + RECT 702.32 53.41 702.52 136.94 ; + LAYER Metal2 SPACING 0.21 ; + RECT 698.505 0 699.1 136.97 ; + RECT 699.87 0.3 700.13 136.97 ; + RECT 700.9 0 702.83 136.97 ; + RECT 0 0.52 702.83 136.97 ; + RECT 693.76 0 697.725 136.97 ; + RECT 692.22 0.155 692.99 136.97 ; + RECT 686.775 0 690.43 136.97 ; + RECT 685.245 0 685.995 136.97 ; + RECT 684.07 0 684.465 136.97 ; + RECT 682.19 0.3 682.45 136.97 ; + RECT 680.825 0 681.42 136.97 ; + RECT 676.08 0 680.045 136.97 ; + RECT 674.54 0.155 675.31 136.97 ; + RECT 669.095 0 672.75 136.97 ; + RECT 667.565 0 668.315 136.97 ; + RECT 666.39 0 666.785 136.97 ; + RECT 664.51 0.3 664.77 136.97 ; + RECT 663.145 0 663.74 136.97 ; + RECT 658.4 0 662.365 136.97 ; + RECT 656.86 0.155 657.63 136.97 ; + RECT 651.415 0 655.07 136.97 ; + RECT 649.885 0 650.635 136.97 ; + RECT 648.71 0 649.105 136.97 ; + RECT 646.83 0.3 647.09 136.97 ; + RECT 645.465 0 646.06 136.97 ; + RECT 640.72 0 644.685 136.97 ; + RECT 639.18 0.155 639.95 136.97 ; + RECT 633.735 0 637.39 136.97 ; + RECT 632.205 0 632.955 136.97 ; + RECT 631.03 0 631.425 136.97 ; + RECT 629.15 0.3 629.41 136.97 ; + RECT 627.785 0 628.38 136.97 ; + RECT 623.04 0 627.005 136.97 ; + RECT 621.5 0.155 622.27 136.97 ; + RECT 616.055 0 619.71 136.97 ; + RECT 614.525 0 615.275 136.97 ; + RECT 613.35 0 613.745 136.97 ; + RECT 611.47 0.3 611.73 136.97 ; + RECT 610.105 0 610.7 136.97 ; + RECT 605.36 0 609.325 136.97 ; + RECT 603.82 0.155 604.59 136.97 ; + RECT 598.375 0 602.03 136.97 ; + RECT 596.845 0 597.595 136.97 ; + RECT 595.67 0 596.065 136.97 ; + RECT 593.79 0.3 594.05 136.97 ; + RECT 592.425 0 593.02 136.97 ; + RECT 587.68 0 591.645 136.97 ; + RECT 586.14 0.155 586.91 136.97 ; + RECT 580.695 0 584.35 136.97 ; + RECT 579.165 0 579.915 136.97 ; + RECT 577.99 0 578.385 136.97 ; + RECT 576.11 0.3 576.37 136.97 ; + RECT 574.745 0 575.34 136.97 ; + RECT 570 0 573.965 136.97 ; + RECT 568.46 0.155 569.23 136.97 ; + RECT 563.015 0 566.67 136.97 ; + RECT 561.485 0 562.235 136.97 ; + RECT 560.31 0 560.705 136.97 ; + RECT 558.43 0.3 558.69 136.97 ; + RECT 557.065 0 557.66 136.97 ; + RECT 552.32 0 556.285 136.97 ; + RECT 550.78 0.155 551.55 136.97 ; + RECT 545.335 0 548.99 136.97 ; + RECT 543.805 0 544.555 136.97 ; + RECT 542.63 0 543.025 136.97 ; + RECT 540.75 0.3 541.01 136.97 ; + RECT 539.385 0 539.98 136.97 ; + RECT 534.64 0 538.605 136.97 ; + RECT 533.1 0.155 533.87 136.97 ; + RECT 527.655 0 531.31 136.97 ; + RECT 526.125 0 526.875 136.97 ; + RECT 524.95 0 525.345 136.97 ; + RECT 523.07 0.3 523.33 136.97 ; + RECT 521.705 0 522.3 136.97 ; + RECT 516.96 0 520.925 136.97 ; + RECT 515.42 0.155 516.19 136.97 ; + RECT 509.975 0 513.63 136.97 ; + RECT 508.445 0 509.195 136.97 ; + RECT 507.27 0 507.665 136.97 ; + RECT 505.39 0.3 505.65 136.97 ; + RECT 504.025 0 504.62 136.97 ; + RECT 499.28 0 503.245 136.97 ; + RECT 497.74 0.155 498.51 136.97 ; + RECT 492.295 0 495.95 136.97 ; + RECT 490.765 0 491.515 136.97 ; + RECT 489.59 0 489.985 136.97 ; + RECT 487.71 0.3 487.97 136.97 ; + RECT 486.345 0 486.94 136.97 ; + RECT 481.6 0 485.565 136.97 ; + RECT 480.06 0.155 480.83 136.97 ; + RECT 474.615 0 478.27 136.97 ; + RECT 473.085 0 473.835 136.97 ; + RECT 471.91 0 472.305 136.97 ; + RECT 470.03 0.3 470.29 136.97 ; + RECT 468.665 0 469.26 136.97 ; + RECT 463.92 0 467.885 136.97 ; + RECT 462.38 0.155 463.15 136.97 ; + RECT 456.935 0 460.59 136.97 ; + RECT 455.405 0 456.155 136.97 ; + RECT 454.23 0 454.625 136.97 ; + RECT 452.35 0.3 452.61 136.97 ; + RECT 450.985 0 451.58 136.97 ; + RECT 446.24 0 450.205 136.97 ; + RECT 444.7 0.155 445.47 136.97 ; + RECT 439.255 0 442.91 136.97 ; + RECT 437.725 0 438.475 136.97 ; + RECT 436.55 0 436.945 136.97 ; + RECT 434.67 0.3 434.93 136.97 ; + RECT 433.305 0 433.9 136.97 ; + RECT 428.56 0 432.525 136.97 ; + RECT 427.02 0.155 427.79 136.97 ; + RECT 421.575 0 425.23 136.97 ; + RECT 420.045 0 420.795 136.97 ; + RECT 418.87 0 419.265 136.97 ; + RECT 387.395 0.18 418.09 136.97 ; + RECT 387.405 0 418.09 136.97 ; + RECT 379.745 0.3 386.635 136.97 ; + RECT 374.135 0.3 375.415 136.97 ; + RECT 371.585 0.3 372.865 136.97 ; + RECT 370.055 0.3 370.315 136.97 ; + RECT 366.995 0.3 367.255 136.97 ; + RECT 365.465 0.3 365.725 136.97 ; + RECT 357.305 0.3 364.195 136.97 ; + RECT 347.815 0 355.015 136.97 ; + RECT 338.635 0.3 345.525 136.97 ; + RECT 338.645 0 345.525 136.97 ; + RECT 337.105 0.3 337.365 136.97 ; + RECT 335.575 0.3 335.835 136.97 ; + RECT 332.515 0.3 332.775 136.97 ; + RECT 329.965 0.3 331.245 136.97 ; + RECT 327.415 0.3 328.695 136.97 ; + RECT 316.195 0.3 323.085 136.97 ; + RECT 316.205 0 323.085 136.97 ; + RECT 284.74 0.18 315.435 136.97 ; + RECT 283.565 0 283.96 136.97 ; + RECT 282.035 0 282.785 136.97 ; + RECT 277.6 0 281.255 136.97 ; + RECT 275.04 0.155 275.81 136.97 ; + RECT 270.305 0 274.27 136.97 ; + RECT 268.93 0 269.525 136.97 ; + RECT 267.9 0.3 268.16 136.97 ; + RECT 265.885 0 266.28 136.97 ; + RECT 264.355 0 265.105 136.97 ; + RECT 259.92 0 263.575 136.97 ; + RECT 257.36 0.155 258.13 136.97 ; + RECT 252.625 0 256.59 136.97 ; + RECT 251.25 0 251.845 136.97 ; + RECT 250.22 0.3 250.48 136.97 ; + RECT 248.205 0 248.6 136.97 ; + RECT 246.675 0 247.425 136.97 ; + RECT 242.24 0 245.895 136.97 ; + RECT 239.68 0.155 240.45 136.97 ; + RECT 234.945 0 238.91 136.97 ; + RECT 233.57 0 234.165 136.97 ; + RECT 232.54 0.3 232.8 136.97 ; + RECT 230.525 0 230.92 136.97 ; + RECT 228.995 0 229.745 136.97 ; + RECT 224.56 0 228.215 136.97 ; + RECT 222 0.155 222.77 136.97 ; + RECT 217.265 0 221.23 136.97 ; + RECT 215.89 0 216.485 136.97 ; + RECT 214.86 0.3 215.12 136.97 ; + RECT 212.845 0 213.24 136.97 ; + RECT 211.315 0 212.065 136.97 ; + RECT 206.88 0 210.535 136.97 ; + RECT 204.32 0.155 205.09 136.97 ; + RECT 199.585 0 203.55 136.97 ; + RECT 198.21 0 198.805 136.97 ; + RECT 197.18 0.3 197.44 136.97 ; + RECT 195.165 0 195.56 136.97 ; + RECT 193.635 0 194.385 136.97 ; + RECT 189.2 0 192.855 136.97 ; + RECT 186.64 0.155 187.41 136.97 ; + RECT 181.905 0 185.87 136.97 ; + RECT 180.53 0 181.125 136.97 ; + RECT 179.5 0.3 179.76 136.97 ; + RECT 177.485 0 177.88 136.97 ; + RECT 175.955 0 176.705 136.97 ; + RECT 171.52 0 175.175 136.97 ; + RECT 168.96 0.155 169.73 136.97 ; + RECT 164.225 0 168.19 136.97 ; + RECT 162.85 0 163.445 136.97 ; + RECT 161.82 0.3 162.08 136.97 ; + RECT 159.805 0 160.2 136.97 ; + RECT 158.275 0 159.025 136.97 ; + RECT 153.84 0 157.495 136.97 ; + RECT 151.28 0.155 152.05 136.97 ; + RECT 146.545 0 150.51 136.97 ; + RECT 145.17 0 145.765 136.97 ; + RECT 144.14 0.3 144.4 136.97 ; + RECT 142.125 0 142.52 136.97 ; + RECT 140.595 0 141.345 136.97 ; + RECT 136.16 0 139.815 136.97 ; + RECT 133.6 0.155 134.37 136.97 ; + RECT 128.865 0 132.83 136.97 ; + RECT 127.49 0 128.085 136.97 ; + RECT 126.46 0.3 126.72 136.97 ; + RECT 124.445 0 124.84 136.97 ; + RECT 122.915 0 123.665 136.97 ; + RECT 118.48 0 122.135 136.97 ; + RECT 115.92 0.155 116.69 136.97 ; + RECT 111.185 0 115.15 136.97 ; + RECT 109.81 0 110.405 136.97 ; + RECT 108.78 0.3 109.04 136.97 ; + RECT 106.765 0 107.16 136.97 ; + RECT 105.235 0 105.985 136.97 ; + RECT 100.8 0 104.455 136.97 ; + RECT 98.24 0.155 99.01 136.97 ; + RECT 93.505 0 97.47 136.97 ; + RECT 92.13 0 92.725 136.97 ; + RECT 91.1 0.3 91.36 136.97 ; + RECT 89.085 0 89.48 136.97 ; + RECT 87.555 0 88.305 136.97 ; + RECT 83.12 0 86.775 136.97 ; + RECT 80.56 0.155 81.33 136.97 ; + RECT 75.825 0 79.79 136.97 ; + RECT 74.45 0 75.045 136.97 ; + RECT 73.42 0.3 73.68 136.97 ; + RECT 71.405 0 71.8 136.97 ; + RECT 69.875 0 70.625 136.97 ; + RECT 65.44 0 69.095 136.97 ; + RECT 62.88 0.155 63.65 136.97 ; + RECT 58.145 0 62.11 136.97 ; + RECT 56.77 0 57.365 136.97 ; + RECT 55.74 0.3 56 136.97 ; + RECT 53.725 0 54.12 136.97 ; + RECT 52.195 0 52.945 136.97 ; + RECT 47.76 0 51.415 136.97 ; + RECT 45.2 0.155 45.97 136.97 ; + RECT 40.465 0 44.43 136.97 ; + RECT 39.09 0 39.685 136.97 ; + RECT 38.06 0.3 38.32 136.97 ; + RECT 36.045 0 36.44 136.97 ; + RECT 34.515 0 35.265 136.97 ; + RECT 30.08 0 33.735 136.97 ; + RECT 27.52 0.155 28.29 136.97 ; + RECT 22.785 0 26.75 136.97 ; + RECT 21.41 0 22.005 136.97 ; + RECT 20.38 0.3 20.64 136.97 ; + RECT 18.365 0 18.76 136.97 ; + RECT 16.835 0 17.585 136.97 ; + RECT 12.4 0 16.055 136.97 ; + RECT 9.84 0.155 10.61 136.97 ; + RECT 5.105 0 9.07 136.97 ; + RECT 3.73 0 4.325 136.97 ; + RECT 2.7 0.3 2.96 136.97 ; + RECT 0 0 1.93 136.97 ; + RECT 699.88 0 700.12 136.97 ; + RECT 682.2 0 682.44 136.97 ; + RECT 664.52 0 664.76 136.97 ; + RECT 646.84 0 647.08 136.97 ; + RECT 629.16 0 629.4 136.97 ; + RECT 611.48 0 611.72 136.97 ; + RECT 593.8 0 594.04 136.97 ; + RECT 576.12 0 576.36 136.97 ; + RECT 558.44 0 558.68 136.97 ; + RECT 540.76 0 541 136.97 ; + RECT 523.08 0 523.32 136.97 ; + RECT 505.4 0 505.64 136.97 ; + RECT 487.72 0 487.96 136.97 ; + RECT 470.04 0 470.28 136.97 ; + RECT 452.36 0 452.6 136.97 ; + RECT 434.68 0 434.92 136.97 ; + RECT 379.745 0 386.625 136.97 ; + RECT 374.145 0 375.405 136.97 ; + RECT 371.595 0 372.855 136.97 ; + RECT 370.065 0 370.305 136.97 ; + RECT 367.005 0 367.245 136.97 ; + RECT 365.475 0 365.715 136.97 ; + RECT 357.305 0 364.185 136.97 ; + RECT 337.115 0 337.355 136.97 ; + RECT 335.585 0 335.825 136.97 ; + RECT 332.525 0 332.765 136.97 ; + RECT 329.975 0 331.235 136.97 ; + RECT 327.425 0 328.685 136.97 ; + RECT 267.91 0 268.15 136.97 ; + RECT 250.23 0 250.47 136.97 ; + RECT 232.55 0 232.79 136.97 ; + RECT 214.87 0 215.11 136.97 ; + RECT 197.19 0 197.43 136.97 ; + RECT 179.51 0 179.75 136.97 ; + RECT 161.83 0 162.07 136.97 ; + RECT 144.15 0 144.39 136.97 ; + RECT 126.47 0 126.71 136.97 ; + RECT 108.79 0 109.03 136.97 ; + RECT 91.11 0 91.35 136.97 ; + RECT 73.43 0 73.67 136.97 ; + RECT 55.75 0 55.99 136.97 ; + RECT 38.07 0 38.31 136.97 ; + RECT 20.39 0 20.63 136.97 ; + RECT 2.71 0 2.95 136.97 ; + RECT 284.74 0 315.425 136.97 ; + RECT 692.23 0 692.98 136.97 ; + RECT 674.55 0 675.3 136.97 ; + RECT 656.87 0 657.62 136.97 ; + RECT 639.19 0 639.94 136.97 ; + RECT 621.51 0 622.26 136.97 ; + RECT 603.83 0 604.58 136.97 ; + RECT 586.15 0 586.9 136.97 ; + RECT 568.47 0 569.22 136.97 ; + RECT 550.79 0 551.54 136.97 ; + RECT 533.11 0 533.86 136.97 ; + RECT 515.43 0 516.18 136.97 ; + RECT 497.75 0 498.5 136.97 ; + RECT 480.07 0 480.82 136.97 ; + RECT 462.39 0 463.14 136.97 ; + RECT 444.71 0 445.46 136.97 ; + RECT 427.03 0 427.78 136.97 ; + RECT 275.05 0 275.8 136.97 ; + RECT 257.37 0 258.12 136.97 ; + RECT 239.69 0 240.44 136.97 ; + RECT 222.01 0 222.76 136.97 ; + RECT 204.33 0 205.08 136.97 ; + RECT 186.65 0 187.4 136.97 ; + RECT 168.97 0 169.72 136.97 ; + RECT 151.29 0 152.04 136.97 ; + RECT 133.61 0 134.36 136.97 ; + RECT 115.93 0 116.68 136.97 ; + RECT 98.25 0 99 136.97 ; + RECT 80.57 0 81.32 136.97 ; + RECT 62.89 0 63.64 136.97 ; + RECT 45.21 0 45.96 136.97 ; + RECT 27.53 0 28.28 136.97 ; + RECT 9.85 0 10.6 136.97 ; + LAYER Metal3 ; + RECT 0 0 702.83 136.97 ; + LAYER Metal4 SPACING 0.21 ; + RECT 391.705 0 417.965 136.97 ; + RECT 386.555 0 388.375 136.97 ; + RECT 381.405 0 383.225 136.97 ; + RECT 696.945 0 702.83 136.97 ; + RECT 688.105 0 692.005 136.97 ; + RECT 688.105 47.305 702.83 53.15 ; + RECT 679.265 0 683.165 136.97 ; + RECT 670.425 0 674.325 136.97 ; + RECT 670.425 47.305 683.165 53.15 ; + RECT 661.585 0 665.485 136.97 ; + RECT 652.745 0 656.645 136.97 ; + RECT 652.745 47.305 665.485 53.15 ; + RECT 643.905 0 647.805 136.97 ; + RECT 635.065 0 638.965 136.97 ; + RECT 635.065 47.305 647.805 53.15 ; + RECT 626.225 0 630.125 136.97 ; + RECT 617.385 0 621.285 136.97 ; + RECT 617.385 47.305 630.125 53.15 ; + RECT 608.545 0 612.445 136.97 ; + RECT 599.705 0 603.605 136.97 ; + RECT 599.705 47.305 612.445 53.15 ; + RECT 590.865 0 594.765 136.97 ; + RECT 582.025 0 585.925 136.97 ; + RECT 582.025 47.305 594.765 53.15 ; + RECT 573.185 0 577.085 136.97 ; + RECT 564.345 0 568.245 136.97 ; + RECT 564.345 47.305 577.085 53.15 ; + RECT 555.505 0 559.405 136.97 ; + RECT 546.665 0 550.565 136.97 ; + RECT 546.665 47.305 559.405 53.15 ; + RECT 537.825 0 541.725 136.97 ; + RECT 528.985 0 532.885 136.97 ; + RECT 528.985 47.305 541.725 53.15 ; + RECT 520.145 0 524.045 136.97 ; + RECT 511.305 0 515.205 136.97 ; + RECT 511.305 47.305 524.045 53.15 ; + RECT 502.465 0 506.365 136.97 ; + RECT 493.625 0 497.525 136.97 ; + RECT 493.625 47.305 506.365 53.15 ; + RECT 484.785 0 488.685 136.97 ; + RECT 475.945 0 479.845 136.97 ; + RECT 475.945 47.305 488.685 53.15 ; + RECT 467.105 0 471.005 136.97 ; + RECT 458.265 0 462.165 136.97 ; + RECT 458.265 47.305 471.005 53.15 ; + RECT 449.425 0 453.325 136.97 ; + RECT 440.585 0 444.485 136.97 ; + RECT 440.585 47.305 453.325 53.15 ; + RECT 431.745 0 435.645 136.97 ; + RECT 422.905 0 426.805 136.97 ; + RECT 422.905 47.305 435.645 53.15 ; + RECT 376.255 0 378.075 136.97 ; + RECT 371.105 0 372.925 136.97 ; + RECT 365.955 0 367.775 136.97 ; + RECT 360.805 0 362.625 136.97 ; + RECT 355.655 0 357.475 136.97 ; + RECT 350.505 0 352.325 136.97 ; + RECT 345.355 0 347.175 136.97 ; + RECT 340.205 0 342.025 136.97 ; + RECT 335.055 0 336.875 136.97 ; + RECT 329.905 0 331.725 136.97 ; + RECT 324.755 0 326.575 136.97 ; + RECT 319.605 0 321.425 136.97 ; + RECT 314.455 0 316.275 136.97 ; + RECT 284.865 0 311.125 136.97 ; + RECT 276.025 0 279.925 136.97 ; + RECT 267.185 0 271.085 136.97 ; + RECT 267.185 47.305 279.925 53.15 ; + RECT 258.345 0 262.245 136.97 ; + RECT 249.505 0 253.405 136.97 ; + RECT 249.505 47.305 262.245 53.15 ; + RECT 240.665 0 244.565 136.97 ; + RECT 231.825 0 235.725 136.97 ; + RECT 231.825 47.305 244.565 53.15 ; + RECT 222.985 0 226.885 136.97 ; + RECT 214.145 0 218.045 136.97 ; + RECT 214.145 47.305 226.885 53.15 ; + RECT 205.305 0 209.205 136.97 ; + RECT 196.465 0 200.365 136.97 ; + RECT 196.465 47.305 209.205 53.15 ; + RECT 187.625 0 191.525 136.97 ; + RECT 178.785 0 182.685 136.97 ; + RECT 178.785 47.305 191.525 53.15 ; + RECT 169.945 0 173.845 136.97 ; + RECT 161.105 0 165.005 136.97 ; + RECT 161.105 47.305 173.845 53.15 ; + RECT 152.265 0 156.165 136.97 ; + RECT 143.425 0 147.325 136.97 ; + RECT 143.425 47.305 156.165 53.15 ; + RECT 134.585 0 138.485 136.97 ; + RECT 125.745 0 129.645 136.97 ; + RECT 125.745 47.305 138.485 53.15 ; + RECT 116.905 0 120.805 136.97 ; + RECT 108.065 0 111.965 136.97 ; + RECT 108.065 47.305 120.805 53.15 ; + RECT 99.225 0 103.125 136.97 ; + RECT 90.385 0 94.285 136.97 ; + RECT 90.385 47.305 103.125 53.15 ; + RECT 81.545 0 85.445 136.97 ; + RECT 72.705 0 76.605 136.97 ; + RECT 72.705 47.305 85.445 53.15 ; + RECT 63.865 0 67.765 136.97 ; + RECT 55.025 0 58.925 136.97 ; + RECT 55.025 47.305 67.765 53.15 ; + RECT 46.185 0 50.085 136.97 ; + RECT 37.345 0 41.245 136.97 ; + RECT 37.345 47.305 50.085 53.15 ; + RECT 28.505 0 32.405 136.97 ; + RECT 19.665 0 23.565 136.97 ; + RECT 19.665 47.305 32.405 53.15 ; + RECT 10.825 0 14.725 136.97 ; + RECT 0 0 5.885 136.97 ; + RECT 0 47.305 14.725 53.15 ; + END +END RM_IHPSG13_2P_256x32_c2_bm_bist + +END LIBRARY diff --git a/flow/platforms/ihp-sg13g2/lef/RM_IHPSG13_2P_256x8_c2_bm_bist.lef b/flow/platforms/ihp-sg13g2/lef/RM_IHPSG13_2P_256x8_c2_bm_bist.lef new file mode 100644 index 0000000000..e4d9972fc6 --- /dev/null +++ b/flow/platforms/ihp-sg13g2/lef/RM_IHPSG13_2P_256x8_c2_bm_bist.lef @@ -0,0 +1,2703 @@ +# ------------------------------------------------------ +# +# Copyright 2025 IHP PDK Authors +# +# Licensed under the Apache License, Version 2.0 (the "License"); +# you may not use this file except in compliance with the License. +# You may obtain a copy of the License at +# +# https://www.apache.org/licenses/LICENSE-2.0 +# +# Unless required by applicable law or agreed to in writing, software +# distributed under the License is distributed on an "AS IS" BASIS, +# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +# See the License for the specific language governing permissions and +# limitations under the License. +# +# Generated on Wed Aug 27 13:36:37 2025 +# +# ------------------------------------------------------ +VERSION 5.7 ; +BUSBITCHARS "[]" ; +DIVIDERCHAR "/" ; + +MACRO RM_IHPSG13_2P_256x8_c2_bm_bist + CLASS BLOCK ; + ORIGIN 0 0 ; + FOREIGN RM_IHPSG13_2P_256x8_c2_bm_bist 0 0 ; + SIZE 278.51 BY 136.97 ; + SYMMETRY X Y R90 ; + PIN A_DIN[4] + DIRECTION INPUT ; + USE SIGNAL ; + ANTENNAPARTIALMETALAREA 3.9091 LAYER Metal2 ; + ANTENNAMODEL OXIDE1 ; + ANTENNAGATEAREA 0.20085 LAYER Metal2 ; + ANTENNAMAXAREACAR 20.368932 LAYER Metal2 ; + PORT + LAYER Metal2 ; + RECT 213.33 0 213.59 0.26 ; + END + END A_DIN[4] + PIN A_DIN[3] + DIRECTION INPUT ; + USE SIGNAL ; + ANTENNAPARTIALMETALAREA 3.9091 LAYER Metal2 ; + ANTENNAMODEL OXIDE1 ; + ANTENNAGATEAREA 0.20085 LAYER Metal2 ; + ANTENNAMAXAREACAR 20.368932 LAYER Metal2 ; + PORT + LAYER Metal2 ; + RECT 64.92 0 65.18 0.26 ; + END + END A_DIN[3] + PIN A_BIST_DIN[4] + DIRECTION INPUT ; + USE SIGNAL ; + ANTENNAPARTIALMETALAREA 4.136375 LAYER Metal2 ; + ANTENNAMODEL OXIDE1 ; + ANTENNAGATEAREA 0.20085 LAYER Metal2 ; + ANTENNAMAXAREACAR 21.874907 LAYER Metal2 ; + PORT + LAYER Metal2 ; + RECT 213.84 0 214.1 0.26 ; + END + END A_BIST_DIN[4] + PIN A_BIST_DIN[3] + DIRECTION INPUT ; + USE SIGNAL ; + ANTENNAPARTIALMETALAREA 4.136375 LAYER Metal2 ; + ANTENNAMODEL OXIDE1 ; + ANTENNAGATEAREA 0.20085 LAYER Metal2 ; + ANTENNAMAXAREACAR 21.874907 LAYER Metal2 ; + PORT + LAYER Metal2 ; + RECT 64.41 0 64.67 0.26 ; + END + END A_BIST_DIN[3] + PIN A_BM[4] + DIRECTION INPUT ; + USE SIGNAL ; + ANTENNAPARTIALMETALAREA 1.7264 LAYER Metal2 ; + ANTENNAMODEL OXIDE1 ; + ANTENNAGATEAREA 0.20085 LAYER Metal2 ; + ANTENNAMAXAREACAR 9.501618 LAYER Metal2 ; + PORT + LAYER Metal2 ; + RECT 222 0 222.26 0.26 ; + END + END A_BM[4] + PIN A_BM[3] + DIRECTION INPUT ; + USE SIGNAL ; + ANTENNAPARTIALMETALAREA 1.7264 LAYER Metal2 ; + ANTENNAMODEL OXIDE1 ; + ANTENNAGATEAREA 0.20085 LAYER Metal2 ; + ANTENNAMAXAREACAR 9.501618 LAYER Metal2 ; + PORT + LAYER Metal2 ; + RECT 56.25 0 56.51 0.26 ; + END + END A_BM[3] + PIN A_BIST_BM[4] + DIRECTION INPUT ; + USE SIGNAL ; + ANTENNAPARTIALMETALAREA 1.7602 LAYER Metal2 ; + ANTENNAMODEL OXIDE1 ; + ANTENNAGATEAREA 0.20085 LAYER Metal2 ; + ANTENNAMAXAREACAR 9.678367 LAYER Metal2 ; + PORT + LAYER Metal2 ; + RECT 220.625 0 220.885 0.26 ; + END + END A_BIST_BM[4] + PIN A_BIST_BM[3] + DIRECTION INPUT ; + USE SIGNAL ; + ANTENNAPARTIALMETALAREA 1.7602 LAYER Metal2 ; + ANTENNAMODEL OXIDE1 ; + ANTENNAGATEAREA 0.20085 LAYER Metal2 ; + ANTENNAMAXAREACAR 9.678367 LAYER Metal2 ; + PORT + LAYER Metal2 ; + RECT 57.625 0 57.885 0.26 ; + END + END A_BIST_BM[3] + PIN A_DOUT[4] + DIRECTION OUTPUT ; + USE SIGNAL ; + ANTENNAPARTIALMETALAREA 4.8256 LAYER Metal2 ; + ANTENNADIFFAREA 0.988 LAYER Metal2 ; + PORT + LAYER Metal2 ; + RECT 206.19 0 206.45 0.26 ; + END + END A_DOUT[4] + PIN A_DOUT[3] + DIRECTION OUTPUT ; + USE SIGNAL ; + ANTENNAPARTIALMETALAREA 4.8256 LAYER Metal2 ; + ANTENNADIFFAREA 0.988 LAYER Metal2 ; + PORT + LAYER Metal2 ; + RECT 72.06 0 72.32 0.26 ; + END + END A_DOUT[3] + PIN B_DIN[4] + DIRECTION INPUT ; + USE SIGNAL ; + ANTENNAPARTIALMETALAREA 2.925 LAYER Metal2 ; + ANTENNAMODEL OXIDE1 ; + ANTENNAGATEAREA 0.20085 LAYER Metal2 ; + ANTENNAMAXAREACAR 15.469256 LAYER Metal2 ; + PORT + LAYER Metal2 ; + RECT 215.88 0 216.14 0.26 ; + END + END B_DIN[4] + PIN B_DIN[3] + DIRECTION INPUT ; + USE SIGNAL ; + ANTENNAPARTIALMETALAREA 2.925 LAYER Metal2 ; + ANTENNAMODEL OXIDE1 ; + ANTENNAGATEAREA 0.20085 LAYER Metal2 ; + ANTENNAMAXAREACAR 15.469256 LAYER Metal2 ; + PORT + LAYER Metal2 ; + RECT 62.37 0 62.63 0.26 ; + END + END B_DIN[3] + PIN B_BIST_DIN[4] + DIRECTION INPUT ; + USE SIGNAL ; + ANTENNAPARTIALMETALAREA 2.9445 LAYER Metal2 ; + ANTENNAMODEL OXIDE1 ; + ANTENNAGATEAREA 0.20085 LAYER Metal2 ; + ANTENNAMAXAREACAR 15.929052 LAYER Metal2 ; + PORT + LAYER Metal2 ; + RECT 214.35 0 214.61 0.26 ; + END + END B_BIST_DIN[4] + PIN B_BIST_DIN[3] + DIRECTION INPUT ; + USE SIGNAL ; + ANTENNAPARTIALMETALAREA 2.9445 LAYER Metal2 ; + ANTENNAMODEL OXIDE1 ; + ANTENNAGATEAREA 0.20085 LAYER Metal2 ; + ANTENNAMAXAREACAR 15.929052 LAYER Metal2 ; + PORT + LAYER Metal2 ; + RECT 63.9 0 64.16 0.26 ; + END + END B_BIST_DIN[3] + PIN B_BM[4] + DIRECTION INPUT ; + USE SIGNAL ; + ANTENNAPARTIALMETALAREA 0.7007 LAYER Metal2 ; + ANTENNAMODEL OXIDE1 ; + ANTENNAGATEAREA 0.20085 LAYER Metal2 ; + ANTENNAMAXAREACAR 4.394822 LAYER Metal2 ; + PORT + LAYER Metal2 ; + RECT 207.365 0 207.625 0.26 ; + END + END B_BM[4] + PIN B_BM[3] + DIRECTION INPUT ; + USE SIGNAL ; + ANTENNAPARTIALMETALAREA 0.7007 LAYER Metal2 ; + ANTENNAMODEL OXIDE1 ; + ANTENNAGATEAREA 0.20085 LAYER Metal2 ; + ANTENNAMAXAREACAR 4.394822 LAYER Metal2 ; + PORT + LAYER Metal2 ; + RECT 70.885 0 71.145 0.26 ; + END + END B_BM[3] + PIN B_BIST_BM[4] + DIRECTION INPUT ; + USE SIGNAL ; + ANTENNAPARTIALMETALAREA 0.7007 LAYER Metal2 ; + ANTENNAMODEL OXIDE1 ; + ANTENNAGATEAREA 0.20085 LAYER Metal2 ; + ANTENNAMAXAREACAR 4.394822 LAYER Metal2 ; + PORT + LAYER Metal2 ; + RECT 208.895 0 209.155 0.26 ; + END + END B_BIST_BM[4] + PIN B_BIST_BM[3] + DIRECTION INPUT ; + USE SIGNAL ; + ANTENNAPARTIALMETALAREA 0.7007 LAYER Metal2 ; + ANTENNAMODEL OXIDE1 ; + ANTENNAGATEAREA 0.20085 LAYER Metal2 ; + ANTENNAMAXAREACAR 4.394822 LAYER Metal2 ; + PORT + LAYER Metal2 ; + RECT 69.355 0 69.615 0.26 ; + END + END B_BIST_BM[3] + PIN B_DOUT[4] + DIRECTION OUTPUT ; + USE SIGNAL ; + ANTENNAPARTIALMETALAREA 4.836 LAYER Metal2 ; + ANTENNADIFFAREA 0.988 LAYER Metal2 ; + PORT + LAYER Metal2 ; + RECT 223.02 0 223.28 0.26 ; + END + END B_DOUT[4] + PIN B_DOUT[3] + DIRECTION OUTPUT ; + USE SIGNAL ; + ANTENNAPARTIALMETALAREA 4.836 LAYER Metal2 ; + ANTENNADIFFAREA 0.988 LAYER Metal2 ; + PORT + LAYER Metal2 ; + RECT 55.23 0 55.49 0.26 ; + END + END B_DOUT[3] + PIN VSS! + DIRECTION INOUT ; + USE GROUND ; + NETEXPR "vss VSS!" ; + PORT + LAYER Metal4 ; + RECT 259.105 0 263.525 136.97 ; + END + PORT + LAYER Metal4 ; + RECT 241.425 0 245.845 136.97 ; + END + PORT + LAYER Metal4 ; + RECT 223.745 0 228.165 136.97 ; + END + PORT + LAYER Metal4 ; + RECT 206.065 0 210.485 136.97 ; + END + PORT + LAYER Metal4 ; + RECT 176.475 0 179.285 136.97 ; + END + PORT + LAYER Metal4 ; + RECT 166.175 0 168.985 136.97 ; + END + PORT + LAYER Metal4 ; + RECT 150.725 0 153.535 136.97 ; + END + PORT + LAYER Metal4 ; + RECT 140.425 0 143.235 136.97 ; + END + PORT + LAYER Metal4 ; + RECT 135.275 0 138.085 136.97 ; + END + PORT + LAYER Metal4 ; + RECT 124.975 0 127.785 136.97 ; + END + PORT + LAYER Metal4 ; + RECT 109.525 0 112.335 136.97 ; + END + PORT + LAYER Metal4 ; + RECT 99.225 0 102.035 136.97 ; + END + PORT + LAYER Metal4 ; + RECT 68.025 0 72.445 136.97 ; + END + PORT + LAYER Metal4 ; + RECT 50.345 0 54.765 136.97 ; + END + PORT + LAYER Metal4 ; + RECT 32.665 0 37.085 136.97 ; + END + PORT + LAYER Metal4 ; + RECT 14.985 0 19.405 136.97 ; + END + END VSS! + PIN VDD! + DIRECTION INOUT ; + USE POWER ; + NETEXPR "vdd VDD!" ; + PORT + LAYER Metal4 ; + RECT 267.945 0 272.365 47.045 ; + END + PORT + LAYER Metal4 ; + RECT 250.265 0 254.685 47.045 ; + END + PORT + LAYER Metal4 ; + RECT 232.585 0 237.005 47.045 ; + END + PORT + LAYER Metal4 ; + RECT 214.905 0 219.325 47.045 ; + END + PORT + LAYER Metal4 ; + RECT 171.325 0 174.135 136.97 ; + END + PORT + LAYER Metal4 ; + RECT 161.025 0 163.835 136.97 ; + END + PORT + LAYER Metal4 ; + RECT 155.875 0 158.685 136.97 ; + END + PORT + LAYER Metal4 ; + RECT 145.575 0 148.385 136.97 ; + END + PORT + LAYER Metal4 ; + RECT 130.125 0 132.935 136.97 ; + END + PORT + LAYER Metal4 ; + RECT 119.825 0 122.635 136.97 ; + END + PORT + LAYER Metal4 ; + RECT 114.675 0 117.485 136.97 ; + END + PORT + LAYER Metal4 ; + RECT 104.375 0 107.185 136.97 ; + END + PORT + LAYER Metal4 ; + RECT 59.185 0 63.605 47.045 ; + END + PORT + LAYER Metal4 ; + RECT 41.505 0 45.925 47.045 ; + END + PORT + LAYER Metal4 ; + RECT 23.825 0 28.245 47.045 ; + END + PORT + LAYER Metal4 ; + RECT 6.145 0 10.565 47.045 ; + END + END VDD! + PIN VDDARRAY! + DIRECTION INOUT ; + USE POWER ; + NETEXPR "vddarray VDDARRAY!" ; + PORT + LAYER Metal4 ; + RECT 267.945 53.41 272.365 136.97 ; + END + PORT + LAYER Metal4 ; + RECT 250.265 53.41 254.685 136.97 ; + END + PORT + LAYER Metal4 ; + RECT 232.585 53.41 237.005 136.97 ; + END + PORT + LAYER Metal4 ; + RECT 214.905 53.41 219.325 136.97 ; + END + PORT + LAYER Metal4 ; + RECT 59.185 53.41 63.605 136.97 ; + END + PORT + LAYER Metal4 ; + RECT 41.505 53.41 45.925 136.97 ; + END + PORT + LAYER Metal4 ; + RECT 23.825 53.41 28.245 136.97 ; + END + PORT + LAYER Metal4 ; + RECT 6.145 53.41 10.565 136.97 ; + END + END VDDARRAY! + PIN A_DIN[5] + DIRECTION INPUT ; + USE SIGNAL ; + ANTENNAPARTIALMETALAREA 3.9091 LAYER Metal2 ; + ANTENNAMODEL OXIDE1 ; + ANTENNAGATEAREA 0.20085 LAYER Metal2 ; + ANTENNAMAXAREACAR 20.368932 LAYER Metal2 ; + PORT + LAYER Metal2 ; + RECT 231.01 0 231.27 0.26 ; + END + END A_DIN[5] + PIN A_DIN[2] + DIRECTION INPUT ; + USE SIGNAL ; + ANTENNAPARTIALMETALAREA 3.9091 LAYER Metal2 ; + ANTENNAMODEL OXIDE1 ; + ANTENNAGATEAREA 0.20085 LAYER Metal2 ; + ANTENNAMAXAREACAR 20.368932 LAYER Metal2 ; + PORT + LAYER Metal2 ; + RECT 47.24 0 47.5 0.26 ; + END + END A_DIN[2] + PIN A_BIST_DIN[5] + DIRECTION INPUT ; + USE SIGNAL ; + ANTENNAPARTIALMETALAREA 4.136375 LAYER Metal2 ; + ANTENNAMODEL OXIDE1 ; + ANTENNAGATEAREA 0.20085 LAYER Metal2 ; + ANTENNAMAXAREACAR 21.874907 LAYER Metal2 ; + PORT + LAYER Metal2 ; + RECT 231.52 0 231.78 0.26 ; + END + END A_BIST_DIN[5] + PIN A_BIST_DIN[2] + DIRECTION INPUT ; + USE SIGNAL ; + ANTENNAPARTIALMETALAREA 4.136375 LAYER Metal2 ; + ANTENNAMODEL OXIDE1 ; + ANTENNAGATEAREA 0.20085 LAYER Metal2 ; + ANTENNAMAXAREACAR 21.874907 LAYER Metal2 ; + PORT + LAYER Metal2 ; + RECT 46.73 0 46.99 0.26 ; + END + END A_BIST_DIN[2] + PIN A_BM[5] + DIRECTION INPUT ; + USE SIGNAL ; + ANTENNAPARTIALMETALAREA 1.7264 LAYER Metal2 ; + ANTENNAMODEL OXIDE1 ; + ANTENNAGATEAREA 0.20085 LAYER Metal2 ; + ANTENNAMAXAREACAR 9.501618 LAYER Metal2 ; + PORT + LAYER Metal2 ; + RECT 239.68 0 239.94 0.26 ; + END + END A_BM[5] + PIN A_BM[2] + DIRECTION INPUT ; + USE SIGNAL ; + ANTENNAPARTIALMETALAREA 1.7264 LAYER Metal2 ; + ANTENNAMODEL OXIDE1 ; + ANTENNAGATEAREA 0.20085 LAYER Metal2 ; + ANTENNAMAXAREACAR 9.501618 LAYER Metal2 ; + PORT + LAYER Metal2 ; + RECT 38.57 0 38.83 0.26 ; + END + END A_BM[2] + PIN A_BIST_BM[5] + DIRECTION INPUT ; + USE SIGNAL ; + ANTENNAPARTIALMETALAREA 1.7602 LAYER Metal2 ; + ANTENNAMODEL OXIDE1 ; + ANTENNAGATEAREA 0.20085 LAYER Metal2 ; + ANTENNAMAXAREACAR 9.678367 LAYER Metal2 ; + PORT + LAYER Metal2 ; + RECT 238.305 0 238.565 0.26 ; + END + END A_BIST_BM[5] + PIN A_BIST_BM[2] + DIRECTION INPUT ; + USE SIGNAL ; + ANTENNAPARTIALMETALAREA 1.7602 LAYER Metal2 ; + ANTENNAMODEL OXIDE1 ; + ANTENNAGATEAREA 0.20085 LAYER Metal2 ; + ANTENNAMAXAREACAR 9.678367 LAYER Metal2 ; + PORT + LAYER Metal2 ; + RECT 39.945 0 40.205 0.26 ; + END + END A_BIST_BM[2] + PIN A_DOUT[5] + DIRECTION OUTPUT ; + USE SIGNAL ; + ANTENNAPARTIALMETALAREA 4.8256 LAYER Metal2 ; + ANTENNADIFFAREA 0.988 LAYER Metal2 ; + PORT + LAYER Metal2 ; + RECT 223.87 0 224.13 0.26 ; + END + END A_DOUT[5] + PIN A_DOUT[2] + DIRECTION OUTPUT ; + USE SIGNAL ; + ANTENNAPARTIALMETALAREA 4.8256 LAYER Metal2 ; + ANTENNADIFFAREA 0.988 LAYER Metal2 ; + PORT + LAYER Metal2 ; + RECT 54.38 0 54.64 0.26 ; + END + END A_DOUT[2] + PIN B_DIN[5] + DIRECTION INPUT ; + USE SIGNAL ; + ANTENNAPARTIALMETALAREA 2.925 LAYER Metal2 ; + ANTENNAMODEL OXIDE1 ; + ANTENNAGATEAREA 0.20085 LAYER Metal2 ; + ANTENNAMAXAREACAR 15.469256 LAYER Metal2 ; + PORT + LAYER Metal2 ; + RECT 233.56 0 233.82 0.26 ; + END + END B_DIN[5] + PIN B_DIN[2] + DIRECTION INPUT ; + USE SIGNAL ; + ANTENNAPARTIALMETALAREA 2.925 LAYER Metal2 ; + ANTENNAMODEL OXIDE1 ; + ANTENNAGATEAREA 0.20085 LAYER Metal2 ; + ANTENNAMAXAREACAR 15.469256 LAYER Metal2 ; + PORT + LAYER Metal2 ; + RECT 44.69 0 44.95 0.26 ; + END + END B_DIN[2] + PIN B_BIST_DIN[5] + DIRECTION INPUT ; + USE SIGNAL ; + ANTENNAPARTIALMETALAREA 2.9445 LAYER Metal2 ; + ANTENNAMODEL OXIDE1 ; + ANTENNAGATEAREA 0.20085 LAYER Metal2 ; + ANTENNAMAXAREACAR 15.929052 LAYER Metal2 ; + PORT + LAYER Metal2 ; + RECT 232.03 0 232.29 0.26 ; + END + END B_BIST_DIN[5] + PIN B_BIST_DIN[2] + DIRECTION INPUT ; + USE SIGNAL ; + ANTENNAPARTIALMETALAREA 2.9445 LAYER Metal2 ; + ANTENNAMODEL OXIDE1 ; + ANTENNAGATEAREA 0.20085 LAYER Metal2 ; + ANTENNAMAXAREACAR 15.929052 LAYER Metal2 ; + PORT + LAYER Metal2 ; + RECT 46.22 0 46.48 0.26 ; + END + END B_BIST_DIN[2] + PIN B_BM[5] + DIRECTION INPUT ; + USE SIGNAL ; + ANTENNAPARTIALMETALAREA 0.7007 LAYER Metal2 ; + ANTENNAMODEL OXIDE1 ; + ANTENNAGATEAREA 0.20085 LAYER Metal2 ; + ANTENNAMAXAREACAR 4.394822 LAYER Metal2 ; + PORT + LAYER Metal2 ; + RECT 225.045 0 225.305 0.26 ; + END + END B_BM[5] + PIN B_BM[2] + DIRECTION INPUT ; + USE SIGNAL ; + ANTENNAPARTIALMETALAREA 0.7007 LAYER Metal2 ; + ANTENNAMODEL OXIDE1 ; + ANTENNAGATEAREA 0.20085 LAYER Metal2 ; + ANTENNAMAXAREACAR 4.394822 LAYER Metal2 ; + PORT + LAYER Metal2 ; + RECT 53.205 0 53.465 0.26 ; + END + END B_BM[2] + PIN B_BIST_BM[5] + DIRECTION INPUT ; + USE SIGNAL ; + ANTENNAPARTIALMETALAREA 0.7007 LAYER Metal2 ; + ANTENNAMODEL OXIDE1 ; + ANTENNAGATEAREA 0.20085 LAYER Metal2 ; + ANTENNAMAXAREACAR 4.394822 LAYER Metal2 ; + PORT + LAYER Metal2 ; + RECT 226.575 0 226.835 0.26 ; + END + END B_BIST_BM[5] + PIN B_BIST_BM[2] + DIRECTION INPUT ; + USE SIGNAL ; + ANTENNAPARTIALMETALAREA 0.7007 LAYER Metal2 ; + ANTENNAMODEL OXIDE1 ; + ANTENNAGATEAREA 0.20085 LAYER Metal2 ; + ANTENNAMAXAREACAR 4.394822 LAYER Metal2 ; + PORT + LAYER Metal2 ; + RECT 51.675 0 51.935 0.26 ; + END + END B_BIST_BM[2] + PIN B_DOUT[5] + DIRECTION OUTPUT ; + USE SIGNAL ; + ANTENNAPARTIALMETALAREA 4.836 LAYER Metal2 ; + ANTENNADIFFAREA 0.988 LAYER Metal2 ; + PORT + LAYER Metal2 ; + RECT 240.7 0 240.96 0.26 ; + END + END B_DOUT[5] + PIN B_DOUT[2] + DIRECTION OUTPUT ; + USE SIGNAL ; + ANTENNAPARTIALMETALAREA 4.836 LAYER Metal2 ; + ANTENNADIFFAREA 0.988 LAYER Metal2 ; + PORT + LAYER Metal2 ; + RECT 37.55 0 37.81 0.26 ; + END + END B_DOUT[2] + PIN A_DIN[6] + DIRECTION INPUT ; + USE SIGNAL ; + ANTENNAPARTIALMETALAREA 3.9091 LAYER Metal2 ; + ANTENNAMODEL OXIDE1 ; + ANTENNAGATEAREA 0.20085 LAYER Metal2 ; + ANTENNAMAXAREACAR 20.368932 LAYER Metal2 ; + PORT + LAYER Metal2 ; + RECT 248.69 0 248.95 0.26 ; + END + END A_DIN[6] + PIN A_DIN[1] + DIRECTION INPUT ; + USE SIGNAL ; + ANTENNAPARTIALMETALAREA 3.9091 LAYER Metal2 ; + ANTENNAMODEL OXIDE1 ; + ANTENNAGATEAREA 0.20085 LAYER Metal2 ; + ANTENNAMAXAREACAR 20.368932 LAYER Metal2 ; + PORT + LAYER Metal2 ; + RECT 29.56 0 29.82 0.26 ; + END + END A_DIN[1] + PIN A_BIST_DIN[6] + DIRECTION INPUT ; + USE SIGNAL ; + ANTENNAPARTIALMETALAREA 4.136375 LAYER Metal2 ; + ANTENNAMODEL OXIDE1 ; + ANTENNAGATEAREA 0.20085 LAYER Metal2 ; + ANTENNAMAXAREACAR 21.874907 LAYER Metal2 ; + PORT + LAYER Metal2 ; + RECT 249.2 0 249.46 0.26 ; + END + END A_BIST_DIN[6] + PIN A_BIST_DIN[1] + DIRECTION INPUT ; + USE SIGNAL ; + ANTENNAPARTIALMETALAREA 4.136375 LAYER Metal2 ; + ANTENNAMODEL OXIDE1 ; + ANTENNAGATEAREA 0.20085 LAYER Metal2 ; + ANTENNAMAXAREACAR 21.874907 LAYER Metal2 ; + PORT + LAYER Metal2 ; + RECT 29.05 0 29.31 0.26 ; + END + END A_BIST_DIN[1] + PIN A_BM[6] + DIRECTION INPUT ; + USE SIGNAL ; + ANTENNAPARTIALMETALAREA 1.7264 LAYER Metal2 ; + ANTENNAMODEL OXIDE1 ; + ANTENNAGATEAREA 0.20085 LAYER Metal2 ; + ANTENNAMAXAREACAR 9.501618 LAYER Metal2 ; + PORT + LAYER Metal2 ; + RECT 257.36 0 257.62 0.26 ; + END + END A_BM[6] + PIN A_BM[1] + DIRECTION INPUT ; + USE SIGNAL ; + ANTENNAPARTIALMETALAREA 1.7264 LAYER Metal2 ; + ANTENNAMODEL OXIDE1 ; + ANTENNAGATEAREA 0.20085 LAYER Metal2 ; + ANTENNAMAXAREACAR 9.501618 LAYER Metal2 ; + PORT + LAYER Metal2 ; + RECT 20.89 0 21.15 0.26 ; + END + END A_BM[1] + PIN A_BIST_BM[6] + DIRECTION INPUT ; + USE SIGNAL ; + ANTENNAPARTIALMETALAREA 1.7602 LAYER Metal2 ; + ANTENNAMODEL OXIDE1 ; + ANTENNAGATEAREA 0.20085 LAYER Metal2 ; + ANTENNAMAXAREACAR 9.678367 LAYER Metal2 ; + PORT + LAYER Metal2 ; + RECT 255.985 0 256.245 0.26 ; + END + END A_BIST_BM[6] + PIN A_BIST_BM[1] + DIRECTION INPUT ; + USE SIGNAL ; + ANTENNAPARTIALMETALAREA 1.7602 LAYER Metal2 ; + ANTENNAMODEL OXIDE1 ; + ANTENNAGATEAREA 0.20085 LAYER Metal2 ; + ANTENNAMAXAREACAR 9.678367 LAYER Metal2 ; + PORT + LAYER Metal2 ; + RECT 22.265 0 22.525 0.26 ; + END + END A_BIST_BM[1] + PIN A_DOUT[6] + DIRECTION OUTPUT ; + USE SIGNAL ; + ANTENNAPARTIALMETALAREA 4.8256 LAYER Metal2 ; + ANTENNADIFFAREA 0.988 LAYER Metal2 ; + PORT + LAYER Metal2 ; + RECT 241.55 0 241.81 0.26 ; + END + END A_DOUT[6] + PIN A_DOUT[1] + DIRECTION OUTPUT ; + USE SIGNAL ; + ANTENNAPARTIALMETALAREA 4.8256 LAYER Metal2 ; + ANTENNADIFFAREA 0.988 LAYER Metal2 ; + PORT + LAYER Metal2 ; + RECT 36.7 0 36.96 0.26 ; + END + END A_DOUT[1] + PIN B_DIN[6] + DIRECTION INPUT ; + USE SIGNAL ; + ANTENNAPARTIALMETALAREA 2.925 LAYER Metal2 ; + ANTENNAMODEL OXIDE1 ; + ANTENNAGATEAREA 0.20085 LAYER Metal2 ; + ANTENNAMAXAREACAR 15.469256 LAYER Metal2 ; + PORT + LAYER Metal2 ; + RECT 251.24 0 251.5 0.26 ; + END + END B_DIN[6] + PIN B_DIN[1] + DIRECTION INPUT ; + USE SIGNAL ; + ANTENNAPARTIALMETALAREA 2.925 LAYER Metal2 ; + ANTENNAMODEL OXIDE1 ; + ANTENNAGATEAREA 0.20085 LAYER Metal2 ; + ANTENNAMAXAREACAR 15.469256 LAYER Metal2 ; + PORT + LAYER Metal2 ; + RECT 27.01 0 27.27 0.26 ; + END + END B_DIN[1] + PIN B_BIST_DIN[6] + DIRECTION INPUT ; + USE SIGNAL ; + ANTENNAPARTIALMETALAREA 2.9445 LAYER Metal2 ; + ANTENNAMODEL OXIDE1 ; + ANTENNAGATEAREA 0.20085 LAYER Metal2 ; + ANTENNAMAXAREACAR 15.929052 LAYER Metal2 ; + PORT + LAYER Metal2 ; + RECT 249.71 0 249.97 0.26 ; + END + END B_BIST_DIN[6] + PIN B_BIST_DIN[1] + DIRECTION INPUT ; + USE SIGNAL ; + ANTENNAPARTIALMETALAREA 2.9445 LAYER Metal2 ; + ANTENNAMODEL OXIDE1 ; + ANTENNAGATEAREA 0.20085 LAYER Metal2 ; + ANTENNAMAXAREACAR 15.929052 LAYER Metal2 ; + PORT + LAYER Metal2 ; + RECT 28.54 0 28.8 0.26 ; + END + END B_BIST_DIN[1] + PIN B_BM[6] + DIRECTION INPUT ; + USE SIGNAL ; + ANTENNAPARTIALMETALAREA 0.7007 LAYER Metal2 ; + ANTENNAMODEL OXIDE1 ; + ANTENNAGATEAREA 0.20085 LAYER Metal2 ; + ANTENNAMAXAREACAR 4.394822 LAYER Metal2 ; + PORT + LAYER Metal2 ; + RECT 242.725 0 242.985 0.26 ; + END + END B_BM[6] + PIN B_BM[1] + DIRECTION INPUT ; + USE SIGNAL ; + ANTENNAPARTIALMETALAREA 0.7007 LAYER Metal2 ; + ANTENNAMODEL OXIDE1 ; + ANTENNAGATEAREA 0.20085 LAYER Metal2 ; + ANTENNAMAXAREACAR 4.394822 LAYER Metal2 ; + PORT + LAYER Metal2 ; + RECT 35.525 0 35.785 0.26 ; + END + END B_BM[1] + PIN B_BIST_BM[6] + DIRECTION INPUT ; + USE SIGNAL ; + ANTENNAPARTIALMETALAREA 0.7007 LAYER Metal2 ; + ANTENNAMODEL OXIDE1 ; + ANTENNAGATEAREA 0.20085 LAYER Metal2 ; + ANTENNAMAXAREACAR 4.394822 LAYER Metal2 ; + PORT + LAYER Metal2 ; + RECT 244.255 0 244.515 0.26 ; + END + END B_BIST_BM[6] + PIN B_BIST_BM[1] + DIRECTION INPUT ; + USE SIGNAL ; + ANTENNAPARTIALMETALAREA 0.7007 LAYER Metal2 ; + ANTENNAMODEL OXIDE1 ; + ANTENNAGATEAREA 0.20085 LAYER Metal2 ; + ANTENNAMAXAREACAR 4.394822 LAYER Metal2 ; + PORT + LAYER Metal2 ; + RECT 33.995 0 34.255 0.26 ; + END + END B_BIST_BM[1] + PIN B_DOUT[6] + DIRECTION OUTPUT ; + USE SIGNAL ; + ANTENNAPARTIALMETALAREA 4.836 LAYER Metal2 ; + ANTENNADIFFAREA 0.988 LAYER Metal2 ; + PORT + LAYER Metal2 ; + RECT 258.38 0 258.64 0.26 ; + END + END B_DOUT[6] + PIN B_DOUT[1] + DIRECTION OUTPUT ; + USE SIGNAL ; + ANTENNAPARTIALMETALAREA 4.836 LAYER Metal2 ; + ANTENNADIFFAREA 0.988 LAYER Metal2 ; + PORT + LAYER Metal2 ; + RECT 19.87 0 20.13 0.26 ; + END + END B_DOUT[1] + PIN A_DIN[7] + DIRECTION INPUT ; + USE SIGNAL ; + ANTENNAPARTIALMETALAREA 3.9091 LAYER Metal2 ; + ANTENNAMODEL OXIDE1 ; + ANTENNAGATEAREA 0.20085 LAYER Metal2 ; + ANTENNAMAXAREACAR 20.368932 LAYER Metal2 ; + PORT + LAYER Metal2 ; + RECT 266.37 0 266.63 0.26 ; + END + END A_DIN[7] + PIN A_DIN[0] + DIRECTION INPUT ; + USE SIGNAL ; + ANTENNAPARTIALMETALAREA 3.9091 LAYER Metal2 ; + ANTENNAMODEL OXIDE1 ; + ANTENNAGATEAREA 0.20085 LAYER Metal2 ; + ANTENNAMAXAREACAR 20.368932 LAYER Metal2 ; + PORT + LAYER Metal2 ; + RECT 11.88 0 12.14 0.26 ; + END + END A_DIN[0] + PIN A_BIST_DIN[7] + DIRECTION INPUT ; + USE SIGNAL ; + ANTENNAPARTIALMETALAREA 4.136375 LAYER Metal2 ; + ANTENNAMODEL OXIDE1 ; + ANTENNAGATEAREA 0.20085 LAYER Metal2 ; + ANTENNAMAXAREACAR 21.874907 LAYER Metal2 ; + PORT + LAYER Metal2 ; + RECT 266.88 0 267.14 0.26 ; + END + END A_BIST_DIN[7] + PIN A_BIST_DIN[0] + DIRECTION INPUT ; + USE SIGNAL ; + ANTENNAPARTIALMETALAREA 4.136375 LAYER Metal2 ; + ANTENNAMODEL OXIDE1 ; + ANTENNAGATEAREA 0.20085 LAYER Metal2 ; + ANTENNAMAXAREACAR 21.874907 LAYER Metal2 ; + PORT + LAYER Metal2 ; + RECT 11.37 0 11.63 0.26 ; + END + END A_BIST_DIN[0] + PIN A_BM[7] + DIRECTION INPUT ; + USE SIGNAL ; + ANTENNAPARTIALMETALAREA 1.7264 LAYER Metal2 ; + ANTENNAMODEL OXIDE1 ; + ANTENNAGATEAREA 0.20085 LAYER Metal2 ; + ANTENNAMAXAREACAR 9.501618 LAYER Metal2 ; + PORT + LAYER Metal2 ; + RECT 275.04 0 275.3 0.26 ; + END + END A_BM[7] + PIN A_BM[0] + DIRECTION INPUT ; + USE SIGNAL ; + ANTENNAPARTIALMETALAREA 1.7264 LAYER Metal2 ; + ANTENNAMODEL OXIDE1 ; + ANTENNAGATEAREA 0.20085 LAYER Metal2 ; + ANTENNAMAXAREACAR 9.501618 LAYER Metal2 ; + PORT + LAYER Metal2 ; + RECT 3.21 0 3.47 0.26 ; + END + END A_BM[0] + PIN A_BIST_BM[7] + DIRECTION INPUT ; + USE SIGNAL ; + ANTENNAPARTIALMETALAREA 1.7602 LAYER Metal2 ; + ANTENNAMODEL OXIDE1 ; + ANTENNAGATEAREA 0.20085 LAYER Metal2 ; + ANTENNAMAXAREACAR 9.678367 LAYER Metal2 ; + PORT + LAYER Metal2 ; + RECT 273.665 0 273.925 0.26 ; + END + END A_BIST_BM[7] + PIN A_BIST_BM[0] + DIRECTION INPUT ; + USE SIGNAL ; + ANTENNAPARTIALMETALAREA 1.7602 LAYER Metal2 ; + ANTENNAMODEL OXIDE1 ; + ANTENNAGATEAREA 0.20085 LAYER Metal2 ; + ANTENNAMAXAREACAR 9.678367 LAYER Metal2 ; + PORT + LAYER Metal2 ; + RECT 4.585 0 4.845 0.26 ; + END + END A_BIST_BM[0] + PIN A_DOUT[7] + DIRECTION OUTPUT ; + USE SIGNAL ; + ANTENNAPARTIALMETALAREA 4.8256 LAYER Metal2 ; + ANTENNADIFFAREA 0.988 LAYER Metal2 ; + PORT + LAYER Metal2 ; + RECT 259.23 0 259.49 0.26 ; + END + END A_DOUT[7] + PIN A_DOUT[0] + DIRECTION OUTPUT ; + USE SIGNAL ; + ANTENNAPARTIALMETALAREA 4.8256 LAYER Metal2 ; + ANTENNADIFFAREA 0.988 LAYER Metal2 ; + PORT + LAYER Metal2 ; + RECT 19.02 0 19.28 0.26 ; + END + END A_DOUT[0] + PIN B_DIN[7] + DIRECTION INPUT ; + USE SIGNAL ; + ANTENNAPARTIALMETALAREA 2.925 LAYER Metal2 ; + ANTENNAMODEL OXIDE1 ; + ANTENNAGATEAREA 0.20085 LAYER Metal2 ; + ANTENNAMAXAREACAR 15.469256 LAYER Metal2 ; + PORT + LAYER Metal2 ; + RECT 268.92 0 269.18 0.26 ; + END + END B_DIN[7] + PIN B_DIN[0] + DIRECTION INPUT ; + USE SIGNAL ; + ANTENNAPARTIALMETALAREA 2.925 LAYER Metal2 ; + ANTENNAMODEL OXIDE1 ; + ANTENNAGATEAREA 0.20085 LAYER Metal2 ; + ANTENNAMAXAREACAR 15.469256 LAYER Metal2 ; + PORT + LAYER Metal2 ; + RECT 9.33 0 9.59 0.26 ; + END + END B_DIN[0] + PIN B_BIST_DIN[7] + DIRECTION INPUT ; + USE SIGNAL ; + ANTENNAPARTIALMETALAREA 2.9445 LAYER Metal2 ; + ANTENNAMODEL OXIDE1 ; + ANTENNAGATEAREA 0.20085 LAYER Metal2 ; + ANTENNAMAXAREACAR 15.929052 LAYER Metal2 ; + PORT + LAYER Metal2 ; + RECT 267.39 0 267.65 0.26 ; + END + END B_BIST_DIN[7] + PIN B_BIST_DIN[0] + DIRECTION INPUT ; + USE SIGNAL ; + ANTENNAPARTIALMETALAREA 2.9445 LAYER Metal2 ; + ANTENNAMODEL OXIDE1 ; + ANTENNAGATEAREA 0.20085 LAYER Metal2 ; + ANTENNAMAXAREACAR 15.929052 LAYER Metal2 ; + PORT + LAYER Metal2 ; + RECT 10.86 0 11.12 0.26 ; + END + END B_BIST_DIN[0] + PIN B_BM[7] + DIRECTION INPUT ; + USE SIGNAL ; + ANTENNAPARTIALMETALAREA 0.7007 LAYER Metal2 ; + ANTENNAMODEL OXIDE1 ; + ANTENNAGATEAREA 0.20085 LAYER Metal2 ; + ANTENNAMAXAREACAR 4.394822 LAYER Metal2 ; + PORT + LAYER Metal2 ; + RECT 260.405 0 260.665 0.26 ; + END + END B_BM[7] + PIN B_BM[0] + DIRECTION INPUT ; + USE SIGNAL ; + ANTENNAPARTIALMETALAREA 0.7007 LAYER Metal2 ; + ANTENNAMODEL OXIDE1 ; + ANTENNAGATEAREA 0.20085 LAYER Metal2 ; + ANTENNAMAXAREACAR 4.394822 LAYER Metal2 ; + PORT + LAYER Metal2 ; + RECT 17.845 0 18.105 0.26 ; + END + END B_BM[0] + PIN B_BIST_BM[7] + DIRECTION INPUT ; + USE SIGNAL ; + ANTENNAPARTIALMETALAREA 0.7007 LAYER Metal2 ; + ANTENNAMODEL OXIDE1 ; + ANTENNAGATEAREA 0.20085 LAYER Metal2 ; + ANTENNAMAXAREACAR 4.394822 LAYER Metal2 ; + PORT + LAYER Metal2 ; + RECT 261.935 0 262.195 0.26 ; + END + END B_BIST_BM[7] + PIN B_BIST_BM[0] + DIRECTION INPUT ; + USE SIGNAL ; + ANTENNAPARTIALMETALAREA 0.7007 LAYER Metal2 ; + ANTENNAMODEL OXIDE1 ; + ANTENNAGATEAREA 0.20085 LAYER Metal2 ; + ANTENNAMAXAREACAR 4.394822 LAYER Metal2 ; + PORT + LAYER Metal2 ; + RECT 16.315 0 16.575 0.26 ; + END + END B_BIST_BM[0] + PIN B_DOUT[7] + DIRECTION OUTPUT ; + USE SIGNAL ; + ANTENNAPARTIALMETALAREA 4.836 LAYER Metal2 ; + ANTENNADIFFAREA 0.988 LAYER Metal2 ; + PORT + LAYER Metal2 ; + RECT 276.06 0 276.32 0.26 ; + END + END B_DOUT[7] + PIN B_DOUT[0] + DIRECTION OUTPUT ; + USE SIGNAL ; + ANTENNAPARTIALMETALAREA 4.836 LAYER Metal2 ; + ANTENNADIFFAREA 0.988 LAYER Metal2 ; + PORT + LAYER Metal2 ; + RECT 2.19 0 2.45 0.26 ; + END + END B_DOUT[0] + PIN A_ADDR[0] + DIRECTION INPUT ; + USE SIGNAL ; + ANTENNAPARTIALMETALAREA 8.7685 LAYER Metal2 ; + ANTENNAMODEL OXIDE1 ; + ANTENNAGATEAREA 0.20085 LAYER Metal2 ; + ANTENNAMAXAREACAR 44.563107 LAYER Metal2 ; + PORT + LAYER Metal2 ; + RECT 155.345 0 155.605 0.26 ; + END + END A_ADDR[0] + PIN A_BIST_ADDR[0] + DIRECTION INPUT ; + USE SIGNAL ; + ANTENNAPARTIALMETALAREA 9.8293 LAYER Metal2 ; + ANTENNAMODEL OXIDE1 ; + ANTENNAGATEAREA 0.20085 LAYER Metal2 ; + ANTENNAMAXAREACAR 49.84466 LAYER Metal2 ; + PORT + LAYER Metal2 ; + RECT 160.955 0 161.215 0.26 ; + END + END A_BIST_ADDR[0] + PIN B_ADDR[0] + DIRECTION INPUT ; + USE SIGNAL ; + ANTENNAPARTIALMETALAREA 8.7685 LAYER Metal2 ; + ANTENNAMODEL OXIDE1 ; + ANTENNAGATEAREA 0.20085 LAYER Metal2 ; + ANTENNAMAXAREACAR 44.563107 LAYER Metal2 ; + PORT + LAYER Metal2 ; + RECT 122.905 0 123.165 0.26 ; + END + END B_ADDR[0] + PIN B_BIST_ADDR[0] + DIRECTION INPUT ; + USE SIGNAL ; + ANTENNAPARTIALMETALAREA 9.8293 LAYER Metal2 ; + ANTENNAMODEL OXIDE1 ; + ANTENNAGATEAREA 0.20085 LAYER Metal2 ; + ANTENNAMAXAREACAR 49.84466 LAYER Metal2 ; + PORT + LAYER Metal2 ; + RECT 117.295 0 117.555 0.26 ; + END + END B_BIST_ADDR[0] + PIN A_ADDR[1] + DIRECTION INPUT ; + USE SIGNAL ; + ANTENNAPARTIALMETALAREA 11.0851 LAYER Metal2 ; + ANTENNAMODEL OXIDE1 ; + ANTENNAGATEAREA 0.20085 LAYER Metal2 ; + ANTENNAMAXAREACAR 56.097087 LAYER Metal2 ; + PORT + LAYER Metal2 ; + RECT 155.855 0 156.115 0.26 ; + END + END A_ADDR[1] + PIN A_BIST_ADDR[1] + DIRECTION INPUT ; + USE SIGNAL ; + ANTENNAPARTIALMETALAREA 12.1459 LAYER Metal2 ; + ANTENNAMODEL OXIDE1 ; + ANTENNAGATEAREA 0.20085 LAYER Metal2 ; + ANTENNAMAXAREACAR 61.378641 LAYER Metal2 ; + PORT + LAYER Metal2 ; + RECT 161.465 0 161.725 0.26 ; + END + END A_BIST_ADDR[1] + PIN B_ADDR[1] + DIRECTION INPUT ; + USE SIGNAL ; + ANTENNAPARTIALMETALAREA 11.0851 LAYER Metal2 ; + ANTENNAMODEL OXIDE1 ; + ANTENNAGATEAREA 0.20085 LAYER Metal2 ; + ANTENNAMAXAREACAR 56.097087 LAYER Metal2 ; + PORT + LAYER Metal2 ; + RECT 122.395 0 122.655 0.26 ; + END + END B_ADDR[1] + PIN B_BIST_ADDR[1] + DIRECTION INPUT ; + USE SIGNAL ; + ANTENNAPARTIALMETALAREA 12.1459 LAYER Metal2 ; + ANTENNAMODEL OXIDE1 ; + ANTENNAGATEAREA 0.20085 LAYER Metal2 ; + ANTENNAMAXAREACAR 61.378641 LAYER Metal2 ; + PORT + LAYER Metal2 ; + RECT 116.785 0 117.045 0.26 ; + END + END B_BIST_ADDR[1] + PIN A_ADDR[2] + DIRECTION INPUT ; + USE SIGNAL ; + ANTENNAPARTIALMETALAREA 13.0819 LAYER Metal2 ; + ANTENNAPARTIALMETALAREA 1.5246 LAYER Metal3 ; + ANTENNAPARTIALCUTAREA 0.0722 LAYER Via2 ; + ANTENNAMODEL OXIDE1 ; + ANTENNAGATEAREA 0.20085 LAYER Metal3 ; + ANTENNAMAXAREACAR 9.415982 LAYER Metal3 ; + PORT + LAYER Metal2 ; + RECT 164.525 0 164.785 0.26 ; + END + END A_ADDR[2] + PIN A_BIST_ADDR[2] + DIRECTION INPUT ; + USE SIGNAL ; + ANTENNAPARTIALMETALAREA 13.0819 LAYER Metal2 ; + ANTENNAPARTIALMETALAREA 1.0962 LAYER Metal3 ; + ANTENNAPARTIALCUTAREA 0.0722 LAYER Via2 ; + ANTENNAMODEL OXIDE1 ; + ANTENNAGATEAREA 0.20085 LAYER Metal3 ; + ANTENNAMAXAREACAR 7.813791 LAYER Metal3 ; + PORT + LAYER Metal2 ; + RECT 165.035 0 165.295 0.26 ; + END + END A_BIST_ADDR[2] + PIN B_ADDR[2] + DIRECTION INPUT ; + USE SIGNAL ; + ANTENNAPARTIALMETALAREA 13.0819 LAYER Metal2 ; + ANTENNAPARTIALMETALAREA 1.5246 LAYER Metal3 ; + ANTENNAPARTIALCUTAREA 0.0722 LAYER Via2 ; + ANTENNAMODEL OXIDE1 ; + ANTENNAGATEAREA 0.20085 LAYER Metal3 ; + ANTENNAMAXAREACAR 9.415982 LAYER Metal3 ; + PORT + LAYER Metal2 ; + RECT 113.725 0 113.985 0.26 ; + END + END B_ADDR[2] + PIN B_BIST_ADDR[2] + DIRECTION INPUT ; + USE SIGNAL ; + ANTENNAPARTIALMETALAREA 13.0819 LAYER Metal2 ; + ANTENNAPARTIALMETALAREA 1.0962 LAYER Metal3 ; + ANTENNAPARTIALCUTAREA 0.0722 LAYER Via2 ; + ANTENNAMODEL OXIDE1 ; + ANTENNAGATEAREA 0.20085 LAYER Metal3 ; + ANTENNAMAXAREACAR 7.813791 LAYER Metal3 ; + PORT + LAYER Metal2 ; + RECT 113.215 0 113.475 0.26 ; + END + END B_BIST_ADDR[2] + PIN A_ADDR[3] + DIRECTION INPUT ; + USE SIGNAL ; + ANTENNAPARTIALMETALAREA 13.0819 LAYER Metal2 ; + ANTENNAPARTIALMETALAREA 3.9459 LAYER Metal3 ; + ANTENNAPARTIALCUTAREA 0.0722 LAYER Via2 ; + ANTENNAMODEL OXIDE1 ; + ANTENNAGATEAREA 0.20085 LAYER Metal3 ; + ANTENNAMAXAREACAR 21.471247 LAYER Metal3 ; + PORT + LAYER Metal2 ; + RECT 163.505 0 163.765 0.26 ; + END + END A_ADDR[3] + PIN A_BIST_ADDR[3] + DIRECTION INPUT ; + USE SIGNAL ; + ANTENNAPARTIALMETALAREA 13.0819 LAYER Metal2 ; + ANTENNAPARTIALMETALAREA 3.7317 LAYER Metal3 ; + ANTENNAPARTIALCUTAREA 0.0722 LAYER Via2 ; + ANTENNAMODEL OXIDE1 ; + ANTENNAGATEAREA 0.20085 LAYER Metal3 ; + ANTENNAMAXAREACAR 20.935524 LAYER Metal3 ; + PORT + LAYER Metal2 ; + RECT 164.015 0 164.275 0.26 ; + END + END A_BIST_ADDR[3] + PIN B_ADDR[3] + DIRECTION INPUT ; + USE SIGNAL ; + ANTENNAPARTIALMETALAREA 13.0819 LAYER Metal2 ; + ANTENNAPARTIALMETALAREA 3.9459 LAYER Metal3 ; + ANTENNAPARTIALCUTAREA 0.0722 LAYER Via2 ; + ANTENNAMODEL OXIDE1 ; + ANTENNAGATEAREA 0.20085 LAYER Metal3 ; + ANTENNAMAXAREACAR 21.471247 LAYER Metal3 ; + PORT + LAYER Metal2 ; + RECT 114.745 0 115.005 0.26 ; + END + END B_ADDR[3] + PIN B_BIST_ADDR[3] + DIRECTION INPUT ; + USE SIGNAL ; + ANTENNAPARTIALMETALAREA 13.0819 LAYER Metal2 ; + ANTENNAPARTIALMETALAREA 3.7317 LAYER Metal3 ; + ANTENNAPARTIALCUTAREA 0.0722 LAYER Via2 ; + ANTENNAMODEL OXIDE1 ; + ANTENNAGATEAREA 0.20085 LAYER Metal3 ; + ANTENNAMAXAREACAR 20.935524 LAYER Metal3 ; + PORT + LAYER Metal2 ; + RECT 114.235 0 114.495 0.26 ; + END + END B_BIST_ADDR[3] + PIN A_ADDR[4] + DIRECTION INPUT ; + USE SIGNAL ; + ANTENNAPARTIALMETALAREA 14.7329 LAYER Metal2 ; + ANTENNAMODEL OXIDE1 ; + ANTENNAGATEAREA 0.20085 LAYER Metal2 ; + ANTENNAMAXAREACAR 74.2589 LAYER Metal2 ; + PORT + LAYER Metal2 ; + RECT 144.125 0 144.385 0.26 ; + END + END A_ADDR[4] + PIN A_BIST_ADDR[4] + DIRECTION INPUT ; + USE SIGNAL ; + ANTENNAPARTIALMETALAREA 14.4677 LAYER Metal2 ; + ANTENNAMODEL OXIDE1 ; + ANTENNAGATEAREA 0.20085 LAYER Metal2 ; + ANTENNAMAXAREACAR 72.938511 LAYER Metal2 ; + PORT + LAYER Metal2 ; + RECT 144.635 0 144.895 0.26 ; + END + END A_BIST_ADDR[4] + PIN B_ADDR[4] + DIRECTION INPUT ; + USE SIGNAL ; + ANTENNAPARTIALMETALAREA 14.7329 LAYER Metal2 ; + ANTENNAMODEL OXIDE1 ; + ANTENNAGATEAREA 0.20085 LAYER Metal2 ; + ANTENNAMAXAREACAR 74.2589 LAYER Metal2 ; + PORT + LAYER Metal2 ; + RECT 134.125 0 134.385 0.26 ; + END + END B_ADDR[4] + PIN B_BIST_ADDR[4] + DIRECTION INPUT ; + USE SIGNAL ; + ANTENNAPARTIALMETALAREA 14.4677 LAYER Metal2 ; + ANTENNAMODEL OXIDE1 ; + ANTENNAGATEAREA 0.20085 LAYER Metal2 ; + ANTENNAMAXAREACAR 72.938511 LAYER Metal2 ; + PORT + LAYER Metal2 ; + RECT 133.615 0 133.875 0.26 ; + END + END B_BIST_ADDR[4] + PIN A_ADDR[5] + DIRECTION INPUT ; + USE SIGNAL ; + ANTENNAPARTIALMETALAREA 13.2691 LAYER Metal2 ; + ANTENNAMODEL OXIDE1 ; + ANTENNAGATEAREA 0.20085 LAYER Metal2 ; + ANTENNAMAXAREACAR 66.970874 LAYER Metal2 ; + PORT + LAYER Metal2 ; + RECT 143.105 0 143.365 0.26 ; + END + END A_ADDR[5] + PIN A_BIST_ADDR[5] + DIRECTION INPUT ; + USE SIGNAL ; + ANTENNAPARTIALMETALAREA 12.9937 LAYER Metal2 ; + ANTENNAMODEL OXIDE1 ; + ANTENNAGATEAREA 0.20085 LAYER Metal2 ; + ANTENNAMAXAREACAR 65.599701 LAYER Metal2 ; + PORT + LAYER Metal2 ; + RECT 143.615 0 143.875 0.26 ; + END + END A_BIST_ADDR[5] + PIN B_ADDR[5] + DIRECTION INPUT ; + USE SIGNAL ; + ANTENNAPARTIALMETALAREA 13.2691 LAYER Metal2 ; + ANTENNAMODEL OXIDE1 ; + ANTENNAGATEAREA 0.20085 LAYER Metal2 ; + ANTENNAMAXAREACAR 66.970874 LAYER Metal2 ; + PORT + LAYER Metal2 ; + RECT 135.145 0 135.405 0.26 ; + END + END B_ADDR[5] + PIN B_BIST_ADDR[5] + DIRECTION INPUT ; + USE SIGNAL ; + ANTENNAPARTIALMETALAREA 12.9937 LAYER Metal2 ; + ANTENNAMODEL OXIDE1 ; + ANTENNAGATEAREA 0.20085 LAYER Metal2 ; + ANTENNAMAXAREACAR 65.599701 LAYER Metal2 ; + PORT + LAYER Metal2 ; + RECT 134.635 0 134.895 0.26 ; + END + END B_BIST_ADDR[5] + PIN A_ADDR[6] + DIRECTION INPUT ; + USE SIGNAL ; + ANTENNAPARTIALMETALAREA 14.3819 LAYER Metal2 ; + ANTENNAMODEL OXIDE1 ; + ANTENNAGATEAREA 0.20085 LAYER Metal2 ; + ANTENNAMAXAREACAR 72.511327 LAYER Metal2 ; + PORT + LAYER Metal2 ; + RECT 167.075 0 167.335 0.26 ; + END + END A_ADDR[6] + PIN A_BIST_ADDR[6] + DIRECTION INPUT ; + USE SIGNAL ; + ANTENNAPARTIALMETALAREA 14.1167 LAYER Metal2 ; + ANTENNAMODEL OXIDE1 ; + ANTENNAGATEAREA 0.20085 LAYER Metal2 ; + ANTENNAMAXAREACAR 71.190939 LAYER Metal2 ; + PORT + LAYER Metal2 ; + RECT 166.565 0 166.825 0.26 ; + END + END A_BIST_ADDR[6] + PIN B_ADDR[6] + DIRECTION INPUT ; + USE SIGNAL ; + ANTENNAPARTIALMETALAREA 14.3819 LAYER Metal2 ; + ANTENNAMODEL OXIDE1 ; + ANTENNAGATEAREA 0.20085 LAYER Metal2 ; + ANTENNAMAXAREACAR 72.511327 LAYER Metal2 ; + PORT + LAYER Metal2 ; + RECT 111.175 0 111.435 0.26 ; + END + END B_ADDR[6] + PIN B_BIST_ADDR[6] + DIRECTION INPUT ; + USE SIGNAL ; + ANTENNAPARTIALMETALAREA 14.1167 LAYER Metal2 ; + ANTENNAMODEL OXIDE1 ; + ANTENNAGATEAREA 0.20085 LAYER Metal2 ; + ANTENNAMAXAREACAR 71.190939 LAYER Metal2 ; + PORT + LAYER Metal2 ; + RECT 111.685 0 111.945 0.26 ; + END + END B_BIST_ADDR[6] + PIN A_ADDR[7] + DIRECTION INPUT ; + USE SIGNAL ; + ANTENNAPARTIALMETALAREA 16.3761 LAYER Metal2 ; + ANTENNAMODEL OXIDE1 ; + ANTENNAGATEAREA 0.20085 LAYER Metal2 ; + ANTENNAMAXAREACAR 82.440129 LAYER Metal2 ; + PORT + LAYER Metal2 ; + RECT 166.055 0 166.315 0.26 ; + END + END A_ADDR[7] + PIN A_BIST_ADDR[7] + DIRECTION INPUT ; + USE SIGNAL ; + ANTENNAPARTIALMETALAREA 16.1109 LAYER Metal2 ; + ANTENNAMODEL OXIDE1 ; + ANTENNAGATEAREA 0.20085 LAYER Metal2 ; + ANTENNAMAXAREACAR 81.119741 LAYER Metal2 ; + PORT + LAYER Metal2 ; + RECT 165.545 0 165.805 0.26 ; + END + END A_BIST_ADDR[7] + PIN B_ADDR[7] + DIRECTION INPUT ; + USE SIGNAL ; + ANTENNAPARTIALMETALAREA 16.3761 LAYER Metal2 ; + ANTENNAMODEL OXIDE1 ; + ANTENNAGATEAREA 0.20085 LAYER Metal2 ; + ANTENNAMAXAREACAR 82.440129 LAYER Metal2 ; + PORT + LAYER Metal2 ; + RECT 112.195 0 112.455 0.26 ; + END + END B_ADDR[7] + PIN B_BIST_ADDR[7] + DIRECTION INPUT ; + USE SIGNAL ; + ANTENNAPARTIALMETALAREA 16.1109 LAYER Metal2 ; + ANTENNAMODEL OXIDE1 ; + ANTENNAGATEAREA 0.20085 LAYER Metal2 ; + ANTENNAMAXAREACAR 81.119741 LAYER Metal2 ; + PORT + LAYER Metal2 ; + RECT 112.705 0 112.965 0.26 ; + END + END B_BIST_ADDR[7] + PIN A_CLK + DIRECTION INPUT ; + USE SIGNAL ; + ANTENNAPARTIALMETALAREA 4.0547 LAYER Metal2 ; + ANTENNAMODEL OXIDE1 ; + ANTENNAGATEAREA 0.20085 LAYER Metal2 ; + ANTENNAMAXAREACAR 21.093851 LAYER Metal2 ; + PORT + LAYER Metal2 ; + RECT 153.815 0 154.075 0.26 ; + END + END A_CLK + PIN A_REN + DIRECTION INPUT ; + USE SIGNAL ; + ANTENNAPARTIALMETALAREA 3.98465 LAYER Metal2 ; + ANTENNAMODEL OXIDE1 ; + ANTENNAGATEAREA 0.20085 LAYER Metal2 ; + ANTENNAMAXAREACAR 20.745083 LAYER Metal2 ; + PORT + LAYER Metal2 ; + RECT 157.385 0 157.645 0.26 ; + END + END A_REN + PIN A_WEN + DIRECTION INPUT ; + USE SIGNAL ; + ANTENNAPARTIALMETALAREA 2.8847 LAYER Metal2 ; + ANTENNAMODEL OXIDE1 ; + ANTENNAGATEAREA 0.20085 LAYER Metal2 ; + ANTENNAMAXAREACAR 15.268608 LAYER Metal2 ; + PORT + LAYER Metal2 ; + RECT 156.875 0 157.135 0.26 ; + END + END A_WEN + PIN A_MEN + DIRECTION INPUT ; + USE SIGNAL ; + ANTENNAPARTIALMETALAREA 3.0247 LAYER Metal2 ; + ANTENNAMODEL OXIDE1 ; + ANTENNAGATEAREA 0.20085 LAYER Metal2 ; + ANTENNAMAXAREACAR 15.965646 LAYER Metal2 ; + PORT + LAYER Metal2 ; + RECT 154.325 0 154.585 0.26 ; + END + END A_MEN + PIN A_DLY + DIRECTION INPUT ; + USE SIGNAL ; + ANTENNAPARTIALMETALAREA 7.7792 LAYER Metal2 ; + ANTENNAMODEL OXIDE1 ; + ANTENNAGATEAREA 0.3367 LAYER Metal2 ; + ANTENNAMAXAREACAR 23.644788 LAYER Metal2 ; + PORT + LAYER Metal2 ; + RECT 174.725 0 174.985 0.26 ; + END + END A_DLY + PIN B_CLK + DIRECTION INPUT ; + USE SIGNAL ; + ANTENNAPARTIALMETALAREA 4.0547 LAYER Metal2 ; + ANTENNAMODEL OXIDE1 ; + ANTENNAGATEAREA 0.20085 LAYER Metal2 ; + ANTENNAMAXAREACAR 21.093851 LAYER Metal2 ; + PORT + LAYER Metal2 ; + RECT 124.435 0 124.695 0.26 ; + END + END B_CLK + PIN B_REN + DIRECTION INPUT ; + USE SIGNAL ; + ANTENNAPARTIALMETALAREA 3.98465 LAYER Metal2 ; + ANTENNAMODEL OXIDE1 ; + ANTENNAGATEAREA 0.20085 LAYER Metal2 ; + ANTENNAMAXAREACAR 20.745083 LAYER Metal2 ; + PORT + LAYER Metal2 ; + RECT 120.865 0 121.125 0.26 ; + END + END B_REN + PIN B_WEN + DIRECTION INPUT ; + USE SIGNAL ; + ANTENNAPARTIALMETALAREA 2.8847 LAYER Metal2 ; + ANTENNAMODEL OXIDE1 ; + ANTENNAGATEAREA 0.20085 LAYER Metal2 ; + ANTENNAMAXAREACAR 15.268608 LAYER Metal2 ; + PORT + LAYER Metal2 ; + RECT 121.375 0 121.635 0.26 ; + END + END B_WEN + PIN B_MEN + DIRECTION INPUT ; + USE SIGNAL ; + ANTENNAPARTIALMETALAREA 3.0247 LAYER Metal2 ; + ANTENNAMODEL OXIDE1 ; + ANTENNAGATEAREA 0.20085 LAYER Metal2 ; + ANTENNAMAXAREACAR 15.965646 LAYER Metal2 ; + PORT + LAYER Metal2 ; + RECT 123.925 0 124.185 0.26 ; + END + END B_MEN + PIN B_DLY + DIRECTION INPUT ; + USE SIGNAL ; + ANTENNAPARTIALMETALAREA 7.7792 LAYER Metal2 ; + ANTENNAMODEL OXIDE1 ; + ANTENNAGATEAREA 0.3367 LAYER Metal2 ; + ANTENNAMAXAREACAR 23.644788 LAYER Metal2 ; + PORT + LAYER Metal2 ; + RECT 103.525 0 103.785 0.26 ; + END + END B_DLY + PIN A_BIST_EN + DIRECTION INPUT ; + USE SIGNAL ; + ANTENNAPARTIALMETALAREA 4.0634 LAYER Metal2 ; + ANTENNAPARTIALMETALAREA 96.5171 LAYER Metal3 ; + ANTENNAPARTIALCUTAREA 0.0722 LAYER Via2 ; + ANTENNAMODEL OXIDE1 ; + ANTENNAGATEAREA 1.43 LAYER Metal2 ; + ANTENNAGATEAREA 10.01 LAYER Metal3 ; + ANTENNAMAXAREACAR 3.266993 LAYER Metal2 ; + ANTENNAMAXAREACAR 20.813443 LAYER Metal3 ; + ANTENNAMAXCUTCAR 0.151469 LAYER Via2 ; + PORT + LAYER Metal2 ; + RECT 156.365 0 156.625 0.26 ; + END + END A_BIST_EN + PIN A_BIST_CLK + DIRECTION INPUT ; + USE SIGNAL ; + ANTENNAPARTIALMETALAREA 4.1639 LAYER Metal2 ; + ANTENNAMODEL OXIDE1 ; + ANTENNAGATEAREA 0.20085 LAYER Metal2 ; + ANTENNAMAXAREACAR 21.953448 LAYER Metal2 ; + PORT + LAYER Metal2 ; + RECT 152.285 0 152.545 0.26 ; + END + END A_BIST_CLK + PIN A_BIST_REN + DIRECTION INPUT ; + USE SIGNAL ; + ANTENNAPARTIALMETALAREA 4.1119 LAYER Metal2 ; + ANTENNAMODEL OXIDE1 ; + ANTENNAGATEAREA 0.20085 LAYER Metal2 ; + ANTENNAMAXAREACAR 21.694548 LAYER Metal2 ; + PORT + LAYER Metal2 ; + RECT 158.915 0 159.175 0.26 ; + END + END A_BIST_REN + PIN A_BIST_WEN + DIRECTION INPUT ; + USE SIGNAL ; + ANTENNAPARTIALMETALAREA 2.9051 LAYER Metal2 ; + ANTENNAMODEL OXIDE1 ; + ANTENNAGATEAREA 0.20085 LAYER Metal2 ; + ANTENNAMAXAREACAR 15.686084 LAYER Metal2 ; + PORT + LAYER Metal2 ; + RECT 158.405 0 158.665 0.26 ; + END + END A_BIST_WEN + PIN A_BIST_MEN + DIRECTION INPUT ; + USE SIGNAL ; + ANTENNAPARTIALMETALAREA 2.8977 LAYER Metal2 ; + ANTENNAMODEL OXIDE1 ; + ANTENNAGATEAREA 0.20085 LAYER Metal2 ; + ANTENNAMAXAREACAR 15.649241 LAYER Metal2 ; + PORT + LAYER Metal2 ; + RECT 152.795 0 153.055 0.26 ; + END + END A_BIST_MEN + PIN B_BIST_EN + DIRECTION INPUT ; + USE SIGNAL ; + ANTENNAPARTIALMETALAREA 3.9646 LAYER Metal2 ; + ANTENNAPARTIALMETALAREA 97.0942 LAYER Metal3 ; + ANTENNAPARTIALCUTAREA 0.0722 LAYER Via2 ; + ANTENNAMODEL OXIDE1 ; + ANTENNAGATEAREA 1.43 LAYER Metal2 ; + ANTENNAGATEAREA 10.01 LAYER Metal3 ; + ANTENNAMAXAREACAR 3.197902 LAYER Metal2 ; + ANTENNAMAXAREACAR 20.871096 LAYER Metal3 ; + ANTENNAMAXCUTCAR 0.151469 LAYER Via2 ; + PORT + LAYER Metal2 ; + RECT 121.885 0 122.145 0.26 ; + END + END B_BIST_EN + PIN B_BIST_CLK + DIRECTION INPUT ; + USE SIGNAL ; + ANTENNAPARTIALMETALAREA 4.1639 LAYER Metal2 ; + ANTENNAMODEL OXIDE1 ; + ANTENNAGATEAREA 0.20085 LAYER Metal2 ; + ANTENNAMAXAREACAR 21.953448 LAYER Metal2 ; + PORT + LAYER Metal2 ; + RECT 125.965 0 126.225 0.26 ; + END + END B_BIST_CLK + PIN B_BIST_REN + DIRECTION INPUT ; + USE SIGNAL ; + ANTENNAPARTIALMETALAREA 4.1119 LAYER Metal2 ; + ANTENNAMODEL OXIDE1 ; + ANTENNAGATEAREA 0.20085 LAYER Metal2 ; + ANTENNAMAXAREACAR 21.694548 LAYER Metal2 ; + PORT + LAYER Metal2 ; + RECT 119.335 0 119.595 0.26 ; + END + END B_BIST_REN + PIN B_BIST_WEN + DIRECTION INPUT ; + USE SIGNAL ; + ANTENNAPARTIALMETALAREA 2.9051 LAYER Metal2 ; + ANTENNAMODEL OXIDE1 ; + ANTENNAGATEAREA 0.20085 LAYER Metal2 ; + ANTENNAMAXAREACAR 15.686084 LAYER Metal2 ; + PORT + LAYER Metal2 ; + RECT 119.845 0 120.105 0.26 ; + END + END B_BIST_WEN + PIN B_BIST_MEN + DIRECTION INPUT ; + USE SIGNAL ; + ANTENNAPARTIALMETALAREA 2.8977 LAYER Metal2 ; + ANTENNAMODEL OXIDE1 ; + ANTENNAGATEAREA 0.20085 LAYER Metal2 ; + ANTENNAMAXAREACAR 15.649241 LAYER Metal2 ; + PORT + LAYER Metal2 ; + RECT 125.455 0 125.715 0.26 ; + END + END B_BIST_MEN + OBS + LAYER Metal1 ; + RECT 0 0 278.51 136.97 ; + LAYER Metal2 ; + RECT 0.31 53.41 0.51 136.94 ; + RECT 1.135 136.21 1.335 136.94 ; + RECT 1.545 136.21 1.905 136.94 ; + RECT 2.115 136.21 2.315 136.94 ; + RECT 2.19 0.52 2.45 7.78 ; + RECT 2.7 0.3 2.96 5.235 ; + RECT 2.77 136.21 2.97 136.94 ; + RECT 3.21 0.52 3.47 5.57 ; + RECT 3.18 136.21 3.54 136.94 ; + RECT 3.835 136.21 4.035 136.94 ; + RECT 4.33 136.21 4.69 136.94 ; + RECT 4.585 0.52 4.845 6.28 ; + RECT 4.9 136.21 5.1 136.94 ; + RECT 5.555 136.21 5.755 136.94 ; + RECT 5.965 136.21 6.325 136.94 ; + RECT 6.535 136.21 6.735 136.94 ; + RECT 6.27 0.18 7.04 0.88 ; + RECT 7.19 136.21 7.39 136.94 ; + RECT 7.29 0.3 7.55 8.7 ; + RECT 7.6 136.21 7.96 136.94 ; + RECT 8.255 136.21 8.455 136.94 ; + RECT 8.75 136.21 9.11 136.94 ; + RECT 9.84 0.155 10.61 0.445 ; + RECT 9.84 0.155 10.1 8.665 ; + RECT 10.35 0.155 10.61 8.665 ; + RECT 9.32 136.21 9.52 136.94 ; + RECT 9.33 0.52 9.59 9.955 ; + RECT 9.975 136.21 10.175 136.94 ; + RECT 10.385 136.21 10.745 136.94 ; + RECT 10.86 0.52 11.12 11.315 ; + RECT 10.955 136.21 11.155 136.94 ; + RECT 11.37 0.52 11.63 13.45 ; + RECT 11.61 136.21 11.81 136.94 ; + RECT 11.88 0.52 12.14 14.115 ; + RECT 12.02 136.21 12.38 136.94 ; + RECT 12.675 136.21 12.875 136.94 ; + RECT 14.075 0.155 14.845 0.445 ; + RECT 14.075 0.155 14.335 13.21 ; + RECT 14.585 0.155 14.845 13.21 ; + RECT 13.17 136.21 13.53 136.94 ; + RECT 13.74 136.21 13.94 136.94 ; + RECT 15.095 0.18 15.865 0.88 ; + RECT 15.095 0.18 15.355 12.9 ; + RECT 15.605 0.18 15.865 12.9 ; + RECT 14.395 136.21 14.595 136.94 ; + RECT 14.805 136.21 15.165 136.94 ; + RECT 15.375 136.21 15.575 136.94 ; + RECT 16.03 136.21 16.23 136.94 ; + RECT 16.315 0.52 16.575 2.82 ; + RECT 16.44 136.21 16.8 136.94 ; + RECT 17.095 136.21 17.295 136.94 ; + RECT 17.59 136.21 17.95 136.94 ; + RECT 17.845 0.52 18.105 2.82 ; + RECT 18.16 136.21 18.36 136.94 ; + RECT 18.815 136.21 19.015 136.94 ; + RECT 19.02 0.52 19.28 4.315 ; + RECT 19.225 136.21 19.585 136.94 ; + RECT 19.795 136.21 19.995 136.94 ; + RECT 19.87 0.52 20.13 7.78 ; + RECT 20.38 0.3 20.64 5.235 ; + RECT 20.45 136.21 20.65 136.94 ; + RECT 20.89 0.52 21.15 5.57 ; + RECT 20.86 136.21 21.22 136.94 ; + RECT 21.515 136.21 21.715 136.94 ; + RECT 22.01 136.21 22.37 136.94 ; + RECT 22.265 0.52 22.525 6.28 ; + RECT 22.58 136.21 22.78 136.94 ; + RECT 23.235 136.21 23.435 136.94 ; + RECT 23.645 136.21 24.005 136.94 ; + RECT 24.215 136.21 24.415 136.94 ; + RECT 23.95 0.18 24.72 0.88 ; + RECT 24.87 136.21 25.07 136.94 ; + RECT 24.97 0.3 25.23 8.7 ; + RECT 25.28 136.21 25.64 136.94 ; + RECT 25.935 136.21 26.135 136.94 ; + RECT 26.43 136.21 26.79 136.94 ; + RECT 27.52 0.155 28.29 0.445 ; + RECT 27.52 0.155 27.78 8.665 ; + RECT 28.03 0.155 28.29 8.665 ; + RECT 27 136.21 27.2 136.94 ; + RECT 27.01 0.52 27.27 9.955 ; + RECT 27.655 136.21 27.855 136.94 ; + RECT 28.065 136.21 28.425 136.94 ; + RECT 28.54 0.52 28.8 11.315 ; + RECT 28.635 136.21 28.835 136.94 ; + RECT 29.05 0.52 29.31 13.45 ; + RECT 29.29 136.21 29.49 136.94 ; + RECT 29.56 0.52 29.82 14.115 ; + RECT 29.7 136.21 30.06 136.94 ; + RECT 30.355 136.21 30.555 136.94 ; + RECT 31.755 0.155 32.525 0.445 ; + RECT 31.755 0.155 32.015 13.21 ; + RECT 32.265 0.155 32.525 13.21 ; + RECT 30.85 136.21 31.21 136.94 ; + RECT 31.42 136.21 31.62 136.94 ; + RECT 32.775 0.18 33.545 0.88 ; + RECT 32.775 0.18 33.035 12.9 ; + RECT 33.285 0.18 33.545 12.9 ; + RECT 32.075 136.21 32.275 136.94 ; + RECT 32.485 136.21 32.845 136.94 ; + RECT 33.055 136.21 33.255 136.94 ; + RECT 33.71 136.21 33.91 136.94 ; + RECT 33.995 0.52 34.255 2.82 ; + RECT 34.12 136.21 34.48 136.94 ; + RECT 34.775 136.21 34.975 136.94 ; + RECT 35.27 136.21 35.63 136.94 ; + RECT 35.525 0.52 35.785 2.82 ; + RECT 35.84 136.21 36.04 136.94 ; + RECT 36.495 136.21 36.695 136.94 ; + RECT 36.7 0.52 36.96 4.315 ; + RECT 36.905 136.21 37.265 136.94 ; + RECT 37.475 136.21 37.675 136.94 ; + RECT 37.55 0.52 37.81 7.78 ; + RECT 38.06 0.3 38.32 5.235 ; + RECT 38.13 136.21 38.33 136.94 ; + RECT 38.57 0.52 38.83 5.57 ; + RECT 38.54 136.21 38.9 136.94 ; + RECT 39.195 136.21 39.395 136.94 ; + RECT 39.69 136.21 40.05 136.94 ; + RECT 39.945 0.52 40.205 6.28 ; + RECT 40.26 136.21 40.46 136.94 ; + RECT 40.915 136.21 41.115 136.94 ; + RECT 41.325 136.21 41.685 136.94 ; + RECT 41.895 136.21 42.095 136.94 ; + RECT 41.63 0.18 42.4 0.88 ; + RECT 42.55 136.21 42.75 136.94 ; + RECT 42.65 0.3 42.91 8.7 ; + RECT 42.96 136.21 43.32 136.94 ; + RECT 43.615 136.21 43.815 136.94 ; + RECT 44.11 136.21 44.47 136.94 ; + RECT 45.2 0.155 45.97 0.445 ; + RECT 45.2 0.155 45.46 8.665 ; + RECT 45.71 0.155 45.97 8.665 ; + RECT 44.68 136.21 44.88 136.94 ; + RECT 44.69 0.52 44.95 9.955 ; + RECT 45.335 136.21 45.535 136.94 ; + RECT 45.745 136.21 46.105 136.94 ; + RECT 46.22 0.52 46.48 11.315 ; + RECT 46.315 136.21 46.515 136.94 ; + RECT 46.73 0.52 46.99 13.45 ; + RECT 46.97 136.21 47.17 136.94 ; + RECT 47.24 0.52 47.5 14.115 ; + RECT 47.38 136.21 47.74 136.94 ; + RECT 48.035 136.21 48.235 136.94 ; + RECT 49.435 0.155 50.205 0.445 ; + RECT 49.435 0.155 49.695 13.21 ; + RECT 49.945 0.155 50.205 13.21 ; + RECT 48.53 136.21 48.89 136.94 ; + RECT 49.1 136.21 49.3 136.94 ; + RECT 50.455 0.18 51.225 0.88 ; + RECT 50.455 0.18 50.715 12.9 ; + RECT 50.965 0.18 51.225 12.9 ; + RECT 49.755 136.21 49.955 136.94 ; + RECT 50.165 136.21 50.525 136.94 ; + RECT 50.735 136.21 50.935 136.94 ; + RECT 51.39 136.21 51.59 136.94 ; + RECT 51.675 0.52 51.935 2.82 ; + RECT 51.8 136.21 52.16 136.94 ; + RECT 52.455 136.21 52.655 136.94 ; + RECT 52.95 136.21 53.31 136.94 ; + RECT 53.205 0.52 53.465 2.82 ; + RECT 53.52 136.21 53.72 136.94 ; + RECT 54.175 136.21 54.375 136.94 ; + RECT 54.38 0.52 54.64 4.315 ; + RECT 54.585 136.21 54.945 136.94 ; + RECT 55.155 136.21 55.355 136.94 ; + RECT 55.23 0.52 55.49 7.78 ; + RECT 55.74 0.3 56 5.235 ; + RECT 55.81 136.21 56.01 136.94 ; + RECT 56.25 0.52 56.51 5.57 ; + RECT 56.22 136.21 56.58 136.94 ; + RECT 56.875 136.21 57.075 136.94 ; + RECT 57.37 136.21 57.73 136.94 ; + RECT 57.625 0.52 57.885 6.28 ; + RECT 57.94 136.21 58.14 136.94 ; + RECT 58.595 136.21 58.795 136.94 ; + RECT 59.005 136.21 59.365 136.94 ; + RECT 59.575 136.21 59.775 136.94 ; + RECT 59.31 0.18 60.08 0.88 ; + RECT 60.23 136.21 60.43 136.94 ; + RECT 60.33 0.3 60.59 8.7 ; + RECT 60.64 136.21 61 136.94 ; + RECT 61.295 136.21 61.495 136.94 ; + RECT 61.79 136.21 62.15 136.94 ; + RECT 62.88 0.155 63.65 0.445 ; + RECT 62.88 0.155 63.14 8.665 ; + RECT 63.39 0.155 63.65 8.665 ; + RECT 62.36 136.21 62.56 136.94 ; + RECT 62.37 0.52 62.63 9.955 ; + RECT 63.015 136.21 63.215 136.94 ; + RECT 63.425 136.21 63.785 136.94 ; + RECT 63.9 0.52 64.16 11.315 ; + RECT 63.995 136.21 64.195 136.94 ; + RECT 64.41 0.52 64.67 13.45 ; + RECT 64.65 136.21 64.85 136.94 ; + RECT 64.92 0.52 65.18 14.115 ; + RECT 65.06 136.21 65.42 136.94 ; + RECT 65.715 136.21 65.915 136.94 ; + RECT 67.115 0.155 67.885 0.445 ; + RECT 67.115 0.155 67.375 13.21 ; + RECT 67.625 0.155 67.885 13.21 ; + RECT 66.21 136.21 66.57 136.94 ; + RECT 66.78 136.21 66.98 136.94 ; + RECT 68.135 0.18 68.905 0.88 ; + RECT 68.135 0.18 68.395 12.9 ; + RECT 68.645 0.18 68.905 12.9 ; + RECT 67.435 136.21 67.635 136.94 ; + RECT 67.845 136.21 68.205 136.94 ; + RECT 68.415 136.21 68.615 136.94 ; + RECT 69.07 136.21 69.27 136.94 ; + RECT 69.355 0.52 69.615 2.82 ; + RECT 69.48 136.21 69.84 136.94 ; + RECT 70.135 136.21 70.335 136.94 ; + RECT 70.63 136.21 70.99 136.94 ; + RECT 70.885 0.52 71.145 2.82 ; + RECT 71.2 136.21 71.4 136.94 ; + RECT 71.855 136.21 72.055 136.94 ; + RECT 72.06 0.52 72.32 4.315 ; + RECT 73.59 0.17 74.36 0.43 ; + RECT 73.59 0.17 73.85 8.7 ; + RECT 74.1 0.17 74.36 8.7 ; + RECT 74.61 0.18 75.38 0.88 ; + RECT 74.61 0.18 74.87 8.7 ; + RECT 75.12 0.18 75.38 8.7 ; + RECT 75.63 0.17 76.4 0.43 ; + RECT 75.63 0.17 75.89 8.7 ; + RECT 76.14 0.17 76.4 8.7 ; + RECT 76.65 0.18 77.42 0.88 ; + RECT 76.65 0.18 76.91 8.7 ; + RECT 77.16 0.18 77.42 8.7 ; + RECT 77.67 0.17 78.44 0.43 ; + RECT 77.67 0.17 77.93 8.7 ; + RECT 78.18 0.17 78.44 8.7 ; + RECT 78.69 0.18 79.46 0.88 ; + RECT 78.69 0.18 78.95 8.7 ; + RECT 79.2 0.18 79.46 8.7 ; + RECT 79.71 0.17 80.48 0.43 ; + RECT 79.71 0.17 79.97 8.7 ; + RECT 80.22 0.17 80.48 8.7 ; + RECT 80.73 0.18 81.5 0.88 ; + RECT 80.73 0.18 80.99 8.7 ; + RECT 81.24 0.18 81.5 8.7 ; + RECT 81.75 0.17 82.52 0.43 ; + RECT 81.75 0.17 82.01 8.7 ; + RECT 82.26 0.17 82.52 8.7 ; + RECT 82.77 0.18 83.54 0.88 ; + RECT 82.77 0.18 83.03 8.7 ; + RECT 83.28 0.18 83.54 8.7 ; + RECT 83.79 0.17 84.56 0.43 ; + RECT 83.79 0.17 84.05 8.7 ; + RECT 84.3 0.17 84.56 8.7 ; + RECT 84.81 0.18 85.58 0.88 ; + RECT 84.81 0.18 85.07 8.7 ; + RECT 85.32 0.18 85.58 8.7 ; + RECT 85.83 0.17 86.6 0.43 ; + RECT 85.83 0.17 86.09 8.7 ; + RECT 86.34 0.17 86.6 8.7 ; + RECT 86.85 0.18 87.62 0.88 ; + RECT 86.85 0.18 87.11 8.7 ; + RECT 87.36 0.18 87.62 8.7 ; + RECT 87.87 0.17 88.64 0.43 ; + RECT 87.87 0.17 88.13 8.7 ; + RECT 88.38 0.17 88.64 8.7 ; + RECT 88.89 0.18 89.66 0.88 ; + RECT 88.89 0.18 89.15 8.7 ; + RECT 89.4 0.18 89.66 8.7 ; + RECT 89.91 0.17 90.68 0.43 ; + RECT 89.91 0.17 90.17 8.7 ; + RECT 90.42 0.17 90.68 8.7 ; + RECT 90.93 0.18 91.7 0.88 ; + RECT 90.93 0.18 91.19 8.7 ; + RECT 91.44 0.18 91.7 8.7 ; + RECT 91.95 0.17 92.72 0.43 ; + RECT 91.95 0.17 92.21 8.7 ; + RECT 92.46 0.17 92.72 8.7 ; + RECT 92.97 0.18 93.74 0.88 ; + RECT 92.97 0.18 93.23 8.7 ; + RECT 93.48 0.18 93.74 8.7 ; + RECT 93.99 0.17 94.76 0.43 ; + RECT 93.99 0.17 94.25 8.7 ; + RECT 94.5 0.17 94.76 8.7 ; + RECT 95.01 0.18 95.78 0.88 ; + RECT 95.01 0.18 95.27 8.7 ; + RECT 95.52 0.18 95.78 8.7 ; + RECT 96.03 0.17 96.8 0.43 ; + RECT 96.03 0.17 96.29 8.7 ; + RECT 96.54 0.17 96.8 8.7 ; + RECT 97.05 0.18 97.82 0.88 ; + RECT 97.05 0.18 97.31 8.7 ; + RECT 97.56 0.18 97.82 8.7 ; + RECT 72.265 136.21 72.625 136.94 ; + RECT 72.835 136.21 73.035 136.94 ; + RECT 99.445 0.18 100.215 0.88 ; + RECT 99.445 0.18 99.705 8.7 ; + RECT 99.955 0.18 100.215 8.7 ; + RECT 100.465 0.17 101.235 0.43 ; + RECT 100.465 0.17 100.725 8.7 ; + RECT 100.975 0.17 101.235 8.7 ; + RECT 73.66 136.13 73.86 136.94 ; + RECT 98.425 0.3 98.685 8.7 ; + RECT 102.505 0.18 103.275 0.88 ; + RECT 102.505 0.18 102.765 8.7 ; + RECT 103.015 0.18 103.275 8.7 ; + RECT 98.935 0.3 99.195 8.7 ; + RECT 101.485 0 101.745 8.7 ; + RECT 101.995 0 102.255 8.7 ; + RECT 103.525 0.52 103.785 8.7 ; + RECT 104.035 0.3 104.295 8.7 ; + RECT 104.545 0.3 104.805 8.7 ; + RECT 105.055 0.3 105.315 8.7 ; + RECT 105.565 0.3 105.825 8.7 ; + RECT 106.075 0.3 106.335 8.7 ; + RECT 106.585 0.3 106.845 8.7 ; + RECT 107.095 0.3 107.355 8.7 ; + RECT 109.135 0.18 109.905 0.88 ; + RECT 109.135 0.18 109.395 8.7 ; + RECT 109.645 0.18 109.905 8.7 ; + RECT 107.605 0.3 107.865 8.7 ; + RECT 108.115 0 108.375 8.7 ; + RECT 108.625 0 108.885 8.7 ; + RECT 110.155 0 110.415 8.7 ; + RECT 110.665 0 110.925 8.7 ; + RECT 111.175 0.52 111.435 8.7 ; + RECT 111.685 0.52 111.945 8.7 ; + RECT 112.195 0.52 112.455 8.7 ; + RECT 112.705 0.52 112.965 8.7 ; + RECT 113.215 0.52 113.475 8.7 ; + RECT 113.725 0.52 113.985 8.7 ; + RECT 114.235 0.52 114.495 8.7 ; + RECT 114.745 0.52 115.005 8.7 ; + RECT 115.255 0.3 115.515 8.7 ; + RECT 115.765 0.3 116.025 8.7 ; + RECT 116.275 0.3 116.535 8.7 ; + RECT 116.785 0.52 117.045 8.7 ; + RECT 117.295 0.52 117.555 8.7 ; + RECT 117.805 0.3 118.065 8.7 ; + RECT 118.315 0.3 118.575 8.7 ; + RECT 118.825 0.3 119.085 8.7 ; + RECT 119.335 0.52 119.595 8.7 ; + RECT 119.845 0.52 120.105 8.7 ; + RECT 120.355 0.3 120.615 8.7 ; + RECT 120.865 0.52 121.125 8.7 ; + RECT 121.375 0.52 121.635 8.7 ; + RECT 121.885 0.52 122.145 8.7 ; + RECT 122.395 0.52 122.655 8.7 ; + RECT 122.905 0.52 123.165 8.7 ; + RECT 123.415 0.3 123.675 8.7 ; + RECT 123.925 0.52 124.185 8.7 ; + RECT 124.435 0.52 124.695 8.7 ; + RECT 124.945 0.3 125.205 8.7 ; + RECT 125.455 0.52 125.715 8.7 ; + RECT 127.495 0.17 128.265 0.43 ; + RECT 127.495 0.17 127.755 8.7 ; + RECT 128.005 0.17 128.265 8.7 ; + RECT 125.965 0.52 126.225 8.7 ; + RECT 126.475 0.3 126.735 8.7 ; + RECT 126.985 0.3 127.245 8.7 ; + RECT 130.045 0.17 130.815 0.43 ; + RECT 130.045 0.17 130.305 8.7 ; + RECT 130.555 0.17 130.815 8.7 ; + RECT 128.515 0.3 128.775 8.7 ; + RECT 131.575 0.18 132.345 0.88 ; + RECT 131.575 0.18 131.835 8.7 ; + RECT 132.085 0.18 132.345 8.7 ; + RECT 129.025 0.3 129.285 8.7 ; + RECT 129.535 0.3 129.795 8.7 ; + RECT 131.065 0.3 131.325 8.7 ; + RECT 132.595 0 132.855 8.7 ; + RECT 133.105 0 133.365 8.7 ; + RECT 133.615 0.52 133.875 8.7 ; + RECT 134.125 0.52 134.385 8.7 ; + RECT 134.635 0.52 134.895 8.7 ; + RECT 135.145 0.52 135.405 8.7 ; + RECT 135.655 0 135.915 8.7 ; + RECT 136.165 0 136.425 8.7 ; + RECT 136.675 0.3 136.935 8.7 ; + RECT 137.185 0.3 137.445 8.7 ; + RECT 137.695 0 137.955 8.7 ; + RECT 138.205 0 138.465 8.7 ; + RECT 138.715 0.3 138.975 8.7 ; + RECT 139.535 0.3 139.795 8.7 ; + RECT 140.045 0 140.305 8.7 ; + RECT 140.555 0 140.815 8.7 ; + RECT 141.065 0.3 141.325 8.7 ; + RECT 141.575 0.3 141.835 8.7 ; + RECT 142.085 0 142.345 8.7 ; + RECT 142.595 0 142.855 8.7 ; + RECT 143.105 0.52 143.365 8.7 ; + RECT 143.615 0.52 143.875 8.7 ; + RECT 144.125 0.52 144.385 8.7 ; + RECT 146.165 0.18 146.935 0.88 ; + RECT 146.165 0.18 146.425 8.7 ; + RECT 146.675 0.18 146.935 8.7 ; + RECT 144.635 0.52 144.895 8.7 ; + RECT 147.695 0.17 148.465 0.43 ; + RECT 147.695 0.17 147.955 8.7 ; + RECT 148.205 0.17 148.465 8.7 ; + RECT 145.145 0 145.405 8.7 ; + RECT 145.655 0 145.915 8.7 ; + RECT 147.185 0.3 147.445 8.7 ; + RECT 150.245 0.17 151.015 0.43 ; + RECT 150.245 0.17 150.505 8.7 ; + RECT 150.755 0.17 151.015 8.7 ; + RECT 148.715 0.3 148.975 8.7 ; + RECT 149.225 0.3 149.485 8.7 ; + RECT 149.735 0.3 149.995 8.7 ; + RECT 151.265 0.3 151.525 8.7 ; + RECT 151.775 0.3 152.035 8.7 ; + RECT 152.285 0.52 152.545 8.7 ; + RECT 152.795 0.52 153.055 8.7 ; + RECT 153.305 0.3 153.565 8.7 ; + RECT 153.815 0.52 154.075 8.7 ; + RECT 154.325 0.52 154.585 8.7 ; + RECT 154.835 0.3 155.095 8.7 ; + RECT 155.345 0.52 155.605 8.7 ; + RECT 155.855 0.52 156.115 8.7 ; + RECT 156.365 0.52 156.625 8.7 ; + RECT 156.875 0.52 157.135 8.7 ; + RECT 157.385 0.52 157.645 8.7 ; + RECT 157.895 0.3 158.155 8.7 ; + RECT 158.405 0.52 158.665 8.7 ; + RECT 158.915 0.52 159.175 8.7 ; + RECT 159.425 0.3 159.685 8.7 ; + RECT 159.935 0.3 160.195 8.7 ; + RECT 160.445 0.3 160.705 8.7 ; + RECT 160.955 0.52 161.215 8.7 ; + RECT 161.465 0.52 161.725 8.7 ; + RECT 161.975 0.3 162.235 8.7 ; + RECT 162.485 0.3 162.745 8.7 ; + RECT 162.995 0.3 163.255 8.7 ; + RECT 163.505 0.52 163.765 8.7 ; + RECT 164.015 0.52 164.275 8.7 ; + RECT 164.525 0.52 164.785 8.7 ; + RECT 165.035 0.52 165.295 8.7 ; + RECT 165.545 0.52 165.805 8.7 ; + RECT 166.055 0.52 166.315 8.7 ; + RECT 166.565 0.52 166.825 8.7 ; + RECT 168.605 0.18 169.375 0.88 ; + RECT 168.605 0.18 168.865 8.7 ; + RECT 169.115 0.18 169.375 8.7 ; + RECT 167.075 0.52 167.335 8.7 ; + RECT 167.585 0 167.845 8.7 ; + RECT 168.095 0 168.355 8.7 ; + RECT 169.625 0 169.885 8.7 ; + RECT 170.135 0 170.395 8.7 ; + RECT 170.645 0.3 170.905 8.7 ; + RECT 171.155 0.3 171.415 8.7 ; + RECT 171.665 0.3 171.925 8.7 ; + RECT 172.175 0.3 172.435 8.7 ; + RECT 172.685 0.3 172.945 8.7 ; + RECT 173.195 0.3 173.455 8.7 ; + RECT 175.235 0.18 176.005 0.88 ; + RECT 175.235 0.18 175.495 8.7 ; + RECT 175.745 0.18 176.005 8.7 ; + RECT 173.705 0.3 173.965 8.7 ; + RECT 174.215 0.3 174.475 8.7 ; + RECT 177.275 0.17 178.045 0.43 ; + RECT 177.275 0.17 177.535 8.7 ; + RECT 177.785 0.17 178.045 8.7 ; + RECT 178.295 0.18 179.065 0.88 ; + RECT 178.295 0.18 178.555 8.7 ; + RECT 178.805 0.18 179.065 8.7 ; + RECT 174.725 0.52 174.985 8.7 ; + RECT 176.255 0 176.515 8.7 ; + RECT 180.69 0.18 181.46 0.88 ; + RECT 180.69 0.18 180.95 8.7 ; + RECT 181.2 0.18 181.46 8.7 ; + RECT 181.71 0.17 182.48 0.43 ; + RECT 181.71 0.17 181.97 8.7 ; + RECT 182.22 0.17 182.48 8.7 ; + RECT 182.73 0.18 183.5 0.88 ; + RECT 182.73 0.18 182.99 8.7 ; + RECT 183.24 0.18 183.5 8.7 ; + RECT 183.75 0.17 184.52 0.43 ; + RECT 183.75 0.17 184.01 8.7 ; + RECT 184.26 0.17 184.52 8.7 ; + RECT 184.77 0.18 185.54 0.88 ; + RECT 184.77 0.18 185.03 8.7 ; + RECT 185.28 0.18 185.54 8.7 ; + RECT 185.79 0.17 186.56 0.43 ; + RECT 185.79 0.17 186.05 8.7 ; + RECT 186.3 0.17 186.56 8.7 ; + RECT 186.81 0.18 187.58 0.88 ; + RECT 186.81 0.18 187.07 8.7 ; + RECT 187.32 0.18 187.58 8.7 ; + RECT 187.83 0.17 188.6 0.43 ; + RECT 187.83 0.17 188.09 8.7 ; + RECT 188.34 0.17 188.6 8.7 ; + RECT 188.85 0.18 189.62 0.88 ; + RECT 188.85 0.18 189.11 8.7 ; + RECT 189.36 0.18 189.62 8.7 ; + RECT 189.87 0.17 190.64 0.43 ; + RECT 189.87 0.17 190.13 8.7 ; + RECT 190.38 0.17 190.64 8.7 ; + RECT 190.89 0.18 191.66 0.88 ; + RECT 190.89 0.18 191.15 8.7 ; + RECT 191.4 0.18 191.66 8.7 ; + RECT 191.91 0.17 192.68 0.43 ; + RECT 191.91 0.17 192.17 8.7 ; + RECT 192.42 0.17 192.68 8.7 ; + RECT 192.93 0.18 193.7 0.88 ; + RECT 192.93 0.18 193.19 8.7 ; + RECT 193.44 0.18 193.7 8.7 ; + RECT 193.95 0.17 194.72 0.43 ; + RECT 193.95 0.17 194.21 8.7 ; + RECT 194.46 0.17 194.72 8.7 ; + RECT 194.97 0.18 195.74 0.88 ; + RECT 194.97 0.18 195.23 8.7 ; + RECT 195.48 0.18 195.74 8.7 ; + RECT 195.99 0.17 196.76 0.43 ; + RECT 195.99 0.17 196.25 8.7 ; + RECT 196.5 0.17 196.76 8.7 ; + RECT 197.01 0.18 197.78 0.88 ; + RECT 197.01 0.18 197.27 8.7 ; + RECT 197.52 0.18 197.78 8.7 ; + RECT 198.03 0.17 198.8 0.43 ; + RECT 198.03 0.17 198.29 8.7 ; + RECT 198.54 0.17 198.8 8.7 ; + RECT 199.05 0.18 199.82 0.88 ; + RECT 199.05 0.18 199.31 8.7 ; + RECT 199.56 0.18 199.82 8.7 ; + RECT 200.07 0.17 200.84 0.43 ; + RECT 200.07 0.17 200.33 8.7 ; + RECT 200.58 0.17 200.84 8.7 ; + RECT 201.09 0.18 201.86 0.88 ; + RECT 201.09 0.18 201.35 8.7 ; + RECT 201.6 0.18 201.86 8.7 ; + RECT 202.11 0.17 202.88 0.43 ; + RECT 202.11 0.17 202.37 8.7 ; + RECT 202.62 0.17 202.88 8.7 ; + RECT 203.13 0.18 203.9 0.88 ; + RECT 203.13 0.18 203.39 8.7 ; + RECT 203.64 0.18 203.9 8.7 ; + RECT 176.765 0 177.025 8.7 ; + RECT 204.15 0.17 204.92 0.43 ; + RECT 204.15 0.17 204.41 8.7 ; + RECT 204.66 0.17 204.92 8.7 ; + RECT 179.315 0.3 179.575 8.7 ; + RECT 179.825 0.3 180.085 8.7 ; + RECT 204.65 136.13 204.85 136.94 ; + RECT 205.475 136.21 205.675 136.94 ; + RECT 205.885 136.21 206.245 136.94 ; + RECT 206.19 0.52 206.45 4.315 ; + RECT 206.455 136.21 206.655 136.94 ; + RECT 207.11 136.21 207.31 136.94 ; + RECT 207.365 0.52 207.625 2.82 ; + RECT 207.52 136.21 207.88 136.94 ; + RECT 208.175 136.21 208.375 136.94 ; + RECT 208.67 136.21 209.03 136.94 ; + RECT 209.605 0.18 210.375 0.88 ; + RECT 209.605 0.18 209.865 12.9 ; + RECT 210.115 0.18 210.375 12.9 ; + RECT 208.895 0.52 209.155 2.82 ; + RECT 209.24 136.21 209.44 136.94 ; + RECT 210.625 0.155 211.395 0.445 ; + RECT 210.625 0.155 210.885 13.21 ; + RECT 211.135 0.155 211.395 13.21 ; + RECT 209.895 136.21 210.095 136.94 ; + RECT 210.305 136.21 210.665 136.94 ; + RECT 210.875 136.21 211.075 136.94 ; + RECT 211.53 136.21 211.73 136.94 ; + RECT 211.94 136.21 212.3 136.94 ; + RECT 212.595 136.21 212.795 136.94 ; + RECT 213.09 136.21 213.45 136.94 ; + RECT 213.33 0.52 213.59 14.115 ; + RECT 213.66 136.21 213.86 136.94 ; + RECT 213.84 0.52 214.1 13.45 ; + RECT 214.315 136.21 214.515 136.94 ; + RECT 214.86 0.155 215.63 0.445 ; + RECT 214.86 0.155 215.12 8.665 ; + RECT 215.37 0.155 215.63 8.665 ; + RECT 214.35 0.52 214.61 11.315 ; + RECT 214.725 136.21 215.085 136.94 ; + RECT 215.295 136.21 215.495 136.94 ; + RECT 215.88 0.52 216.14 9.955 ; + RECT 215.95 136.21 216.15 136.94 ; + RECT 216.36 136.21 216.72 136.94 ; + RECT 217.015 136.21 217.215 136.94 ; + RECT 217.51 136.21 217.87 136.94 ; + RECT 217.92 0.3 218.18 8.7 ; + RECT 218.08 136.21 218.28 136.94 ; + RECT 218.735 136.21 218.935 136.94 ; + RECT 218.43 0.18 219.2 0.88 ; + RECT 219.145 136.21 219.505 136.94 ; + RECT 219.715 136.21 219.915 136.94 ; + RECT 220.37 136.21 220.57 136.94 ; + RECT 220.625 0.52 220.885 6.28 ; + RECT 220.78 136.21 221.14 136.94 ; + RECT 221.435 136.21 221.635 136.94 ; + RECT 222 0.52 222.26 5.57 ; + RECT 221.93 136.21 222.29 136.94 ; + RECT 222.5 136.21 222.7 136.94 ; + RECT 222.51 0.3 222.77 5.235 ; + RECT 223.02 0.52 223.28 7.78 ; + RECT 223.155 136.21 223.355 136.94 ; + RECT 223.565 136.21 223.925 136.94 ; + RECT 223.87 0.52 224.13 4.315 ; + RECT 224.135 136.21 224.335 136.94 ; + RECT 224.79 136.21 224.99 136.94 ; + RECT 225.045 0.52 225.305 2.82 ; + RECT 225.2 136.21 225.56 136.94 ; + RECT 225.855 136.21 226.055 136.94 ; + RECT 226.35 136.21 226.71 136.94 ; + RECT 227.285 0.18 228.055 0.88 ; + RECT 227.285 0.18 227.545 12.9 ; + RECT 227.795 0.18 228.055 12.9 ; + RECT 226.575 0.52 226.835 2.82 ; + RECT 226.92 136.21 227.12 136.94 ; + RECT 228.305 0.155 229.075 0.445 ; + RECT 228.305 0.155 228.565 13.21 ; + RECT 228.815 0.155 229.075 13.21 ; + RECT 227.575 136.21 227.775 136.94 ; + RECT 227.985 136.21 228.345 136.94 ; + RECT 228.555 136.21 228.755 136.94 ; + RECT 229.21 136.21 229.41 136.94 ; + RECT 229.62 136.21 229.98 136.94 ; + RECT 230.275 136.21 230.475 136.94 ; + RECT 230.77 136.21 231.13 136.94 ; + RECT 231.01 0.52 231.27 14.115 ; + RECT 231.34 136.21 231.54 136.94 ; + RECT 231.52 0.52 231.78 13.45 ; + RECT 231.995 136.21 232.195 136.94 ; + RECT 232.54 0.155 233.31 0.445 ; + RECT 232.54 0.155 232.8 8.665 ; + RECT 233.05 0.155 233.31 8.665 ; + RECT 232.03 0.52 232.29 11.315 ; + RECT 232.405 136.21 232.765 136.94 ; + RECT 232.975 136.21 233.175 136.94 ; + RECT 233.56 0.52 233.82 9.955 ; + RECT 233.63 136.21 233.83 136.94 ; + RECT 234.04 136.21 234.4 136.94 ; + RECT 234.695 136.21 234.895 136.94 ; + RECT 235.19 136.21 235.55 136.94 ; + RECT 235.6 0.3 235.86 8.7 ; + RECT 235.76 136.21 235.96 136.94 ; + RECT 236.415 136.21 236.615 136.94 ; + RECT 236.11 0.18 236.88 0.88 ; + RECT 236.825 136.21 237.185 136.94 ; + RECT 237.395 136.21 237.595 136.94 ; + RECT 238.05 136.21 238.25 136.94 ; + RECT 238.305 0.52 238.565 6.28 ; + RECT 238.46 136.21 238.82 136.94 ; + RECT 239.115 136.21 239.315 136.94 ; + RECT 239.68 0.52 239.94 5.57 ; + RECT 239.61 136.21 239.97 136.94 ; + RECT 240.18 136.21 240.38 136.94 ; + RECT 240.19 0.3 240.45 5.235 ; + RECT 240.7 0.52 240.96 7.78 ; + RECT 240.835 136.21 241.035 136.94 ; + RECT 241.245 136.21 241.605 136.94 ; + RECT 241.55 0.52 241.81 4.315 ; + RECT 241.815 136.21 242.015 136.94 ; + RECT 242.47 136.21 242.67 136.94 ; + RECT 242.725 0.52 242.985 2.82 ; + RECT 242.88 136.21 243.24 136.94 ; + RECT 243.535 136.21 243.735 136.94 ; + RECT 244.03 136.21 244.39 136.94 ; + RECT 244.965 0.18 245.735 0.88 ; + RECT 244.965 0.18 245.225 12.9 ; + RECT 245.475 0.18 245.735 12.9 ; + RECT 244.255 0.52 244.515 2.82 ; + RECT 244.6 136.21 244.8 136.94 ; + RECT 245.985 0.155 246.755 0.445 ; + RECT 245.985 0.155 246.245 13.21 ; + RECT 246.495 0.155 246.755 13.21 ; + RECT 245.255 136.21 245.455 136.94 ; + RECT 245.665 136.21 246.025 136.94 ; + RECT 246.235 136.21 246.435 136.94 ; + RECT 246.89 136.21 247.09 136.94 ; + RECT 247.3 136.21 247.66 136.94 ; + RECT 247.955 136.21 248.155 136.94 ; + RECT 248.45 136.21 248.81 136.94 ; + RECT 248.69 0.52 248.95 14.115 ; + RECT 249.02 136.21 249.22 136.94 ; + RECT 249.2 0.52 249.46 13.45 ; + RECT 249.675 136.21 249.875 136.94 ; + RECT 250.22 0.155 250.99 0.445 ; + RECT 250.22 0.155 250.48 8.665 ; + RECT 250.73 0.155 250.99 8.665 ; + RECT 249.71 0.52 249.97 11.315 ; + RECT 250.085 136.21 250.445 136.94 ; + RECT 250.655 136.21 250.855 136.94 ; + RECT 251.24 0.52 251.5 9.955 ; + RECT 251.31 136.21 251.51 136.94 ; + RECT 251.72 136.21 252.08 136.94 ; + RECT 252.375 136.21 252.575 136.94 ; + RECT 252.87 136.21 253.23 136.94 ; + RECT 253.28 0.3 253.54 8.7 ; + RECT 253.44 136.21 253.64 136.94 ; + RECT 254.095 136.21 254.295 136.94 ; + RECT 253.79 0.18 254.56 0.88 ; + RECT 254.505 136.21 254.865 136.94 ; + RECT 255.075 136.21 255.275 136.94 ; + RECT 255.73 136.21 255.93 136.94 ; + RECT 255.985 0.52 256.245 6.28 ; + RECT 256.14 136.21 256.5 136.94 ; + RECT 256.795 136.21 256.995 136.94 ; + RECT 257.36 0.52 257.62 5.57 ; + RECT 257.29 136.21 257.65 136.94 ; + RECT 257.86 136.21 258.06 136.94 ; + RECT 257.87 0.3 258.13 5.235 ; + RECT 258.38 0.52 258.64 7.78 ; + RECT 258.515 136.21 258.715 136.94 ; + RECT 258.925 136.21 259.285 136.94 ; + RECT 259.23 0.52 259.49 4.315 ; + RECT 259.495 136.21 259.695 136.94 ; + RECT 260.15 136.21 260.35 136.94 ; + RECT 260.405 0.52 260.665 2.82 ; + RECT 260.56 136.21 260.92 136.94 ; + RECT 261.215 136.21 261.415 136.94 ; + RECT 261.71 136.21 262.07 136.94 ; + RECT 262.645 0.18 263.415 0.88 ; + RECT 262.645 0.18 262.905 12.9 ; + RECT 263.155 0.18 263.415 12.9 ; + RECT 261.935 0.52 262.195 2.82 ; + RECT 262.28 136.21 262.48 136.94 ; + RECT 263.665 0.155 264.435 0.445 ; + RECT 263.665 0.155 263.925 13.21 ; + RECT 264.175 0.155 264.435 13.21 ; + RECT 262.935 136.21 263.135 136.94 ; + RECT 263.345 136.21 263.705 136.94 ; + RECT 263.915 136.21 264.115 136.94 ; + RECT 264.57 136.21 264.77 136.94 ; + RECT 264.98 136.21 265.34 136.94 ; + RECT 265.635 136.21 265.835 136.94 ; + RECT 266.13 136.21 266.49 136.94 ; + RECT 266.37 0.52 266.63 14.115 ; + RECT 266.7 136.21 266.9 136.94 ; + RECT 266.88 0.52 267.14 13.45 ; + RECT 267.355 136.21 267.555 136.94 ; + RECT 267.9 0.155 268.67 0.445 ; + RECT 267.9 0.155 268.16 8.665 ; + RECT 268.41 0.155 268.67 8.665 ; + RECT 267.39 0.52 267.65 11.315 ; + RECT 267.765 136.21 268.125 136.94 ; + RECT 268.335 136.21 268.535 136.94 ; + RECT 268.92 0.52 269.18 9.955 ; + RECT 268.99 136.21 269.19 136.94 ; + RECT 269.4 136.21 269.76 136.94 ; + RECT 270.055 136.21 270.255 136.94 ; + RECT 270.55 136.21 270.91 136.94 ; + RECT 270.96 0.3 271.22 8.7 ; + RECT 271.12 136.21 271.32 136.94 ; + RECT 271.775 136.21 271.975 136.94 ; + RECT 271.47 0.18 272.24 0.88 ; + RECT 272.185 136.21 272.545 136.94 ; + RECT 272.755 136.21 272.955 136.94 ; + RECT 273.41 136.21 273.61 136.94 ; + RECT 273.665 0.52 273.925 6.28 ; + RECT 273.82 136.21 274.18 136.94 ; + RECT 274.475 136.21 274.675 136.94 ; + RECT 275.04 0.52 275.3 5.57 ; + RECT 274.97 136.21 275.33 136.94 ; + RECT 275.54 136.21 275.74 136.94 ; + RECT 275.55 0.3 275.81 5.235 ; + RECT 276.06 0.52 276.32 7.78 ; + RECT 276.195 136.21 276.395 136.94 ; + RECT 276.605 136.21 276.965 136.94 ; + RECT 277.175 136.21 277.375 136.94 ; + RECT 278 53.41 278.2 136.94 ; + LAYER Metal2 SPACING 0.21 ; + RECT 274.185 0 274.78 136.97 ; + RECT 275.55 0.3 275.81 136.97 ; + RECT 276.58 0 278.51 136.97 ; + RECT 0 0.52 278.51 136.97 ; + RECT 269.44 0 273.405 136.97 ; + RECT 267.9 0.155 268.67 136.97 ; + RECT 262.455 0 266.11 136.97 ; + RECT 260.925 0 261.675 136.97 ; + RECT 259.75 0 260.145 136.97 ; + RECT 257.87 0.3 258.13 136.97 ; + RECT 256.505 0 257.1 136.97 ; + RECT 251.76 0 255.725 136.97 ; + RECT 250.22 0.155 250.99 136.97 ; + RECT 244.775 0 248.43 136.97 ; + RECT 243.245 0 243.995 136.97 ; + RECT 242.07 0 242.465 136.97 ; + RECT 240.19 0.3 240.45 136.97 ; + RECT 238.825 0 239.42 136.97 ; + RECT 234.08 0 238.045 136.97 ; + RECT 232.54 0.155 233.31 136.97 ; + RECT 227.095 0 230.75 136.97 ; + RECT 225.565 0 226.315 136.97 ; + RECT 224.39 0 224.785 136.97 ; + RECT 222.51 0.3 222.77 136.97 ; + RECT 221.145 0 221.74 136.97 ; + RECT 216.4 0 220.365 136.97 ; + RECT 214.86 0.155 215.63 136.97 ; + RECT 209.415 0 213.07 136.97 ; + RECT 207.885 0 208.635 136.97 ; + RECT 206.71 0 207.105 136.97 ; + RECT 175.235 0.18 205.93 136.97 ; + RECT 175.245 0 205.93 136.97 ; + RECT 167.585 0.3 174.475 136.97 ; + RECT 161.975 0.3 163.255 136.97 ; + RECT 159.425 0.3 160.705 136.97 ; + RECT 157.895 0.3 158.155 136.97 ; + RECT 154.835 0.3 155.095 136.97 ; + RECT 153.305 0.3 153.565 136.97 ; + RECT 145.145 0.3 152.035 136.97 ; + RECT 135.655 0 142.855 136.97 ; + RECT 126.475 0.3 133.365 136.97 ; + RECT 126.485 0 133.365 136.97 ; + RECT 124.945 0.3 125.205 136.97 ; + RECT 123.415 0.3 123.675 136.97 ; + RECT 120.355 0.3 120.615 136.97 ; + RECT 117.805 0.3 119.085 136.97 ; + RECT 115.255 0.3 116.535 136.97 ; + RECT 104.035 0.3 110.925 136.97 ; + RECT 104.045 0 110.925 136.97 ; + RECT 72.58 0.18 103.275 136.97 ; + RECT 71.405 0 71.8 136.97 ; + RECT 69.875 0 70.625 136.97 ; + RECT 65.44 0 69.095 136.97 ; + RECT 62.88 0.155 63.65 136.97 ; + RECT 58.145 0 62.11 136.97 ; + RECT 56.77 0 57.365 136.97 ; + RECT 55.74 0.3 56 136.97 ; + RECT 53.725 0 54.12 136.97 ; + RECT 52.195 0 52.945 136.97 ; + RECT 47.76 0 51.415 136.97 ; + RECT 45.2 0.155 45.97 136.97 ; + RECT 40.465 0 44.43 136.97 ; + RECT 39.09 0 39.685 136.97 ; + RECT 38.06 0.3 38.32 136.97 ; + RECT 36.045 0 36.44 136.97 ; + RECT 34.515 0 35.265 136.97 ; + RECT 30.08 0 33.735 136.97 ; + RECT 27.52 0.155 28.29 136.97 ; + RECT 22.785 0 26.75 136.97 ; + RECT 21.41 0 22.005 136.97 ; + RECT 20.38 0.3 20.64 136.97 ; + RECT 18.365 0 18.76 136.97 ; + RECT 16.835 0 17.585 136.97 ; + RECT 12.4 0 16.055 136.97 ; + RECT 9.84 0.155 10.61 136.97 ; + RECT 5.105 0 9.07 136.97 ; + RECT 3.73 0 4.325 136.97 ; + RECT 2.7 0.3 2.96 136.97 ; + RECT 0 0 1.93 136.97 ; + RECT 275.56 0 275.8 136.97 ; + RECT 257.88 0 258.12 136.97 ; + RECT 240.2 0 240.44 136.97 ; + RECT 222.52 0 222.76 136.97 ; + RECT 167.585 0 174.465 136.97 ; + RECT 161.985 0 163.245 136.97 ; + RECT 159.435 0 160.695 136.97 ; + RECT 157.905 0 158.145 136.97 ; + RECT 154.845 0 155.085 136.97 ; + RECT 153.315 0 153.555 136.97 ; + RECT 145.145 0 152.025 136.97 ; + RECT 124.955 0 125.195 136.97 ; + RECT 123.425 0 123.665 136.97 ; + RECT 120.365 0 120.605 136.97 ; + RECT 117.815 0 119.075 136.97 ; + RECT 115.265 0 116.525 136.97 ; + RECT 55.75 0 55.99 136.97 ; + RECT 38.07 0 38.31 136.97 ; + RECT 20.39 0 20.63 136.97 ; + RECT 2.71 0 2.95 136.97 ; + RECT 72.58 0 103.265 136.97 ; + RECT 267.91 0 268.66 136.97 ; + RECT 250.23 0 250.98 136.97 ; + RECT 232.55 0 233.3 136.97 ; + RECT 214.87 0 215.62 136.97 ; + RECT 62.89 0 63.64 136.97 ; + RECT 45.21 0 45.96 136.97 ; + RECT 27.53 0 28.28 136.97 ; + RECT 9.85 0 10.6 136.97 ; + LAYER Metal3 ; + RECT 0 0 278.51 136.97 ; + LAYER Metal4 SPACING 0.21 ; + RECT 179.545 0 205.805 136.97 ; + RECT 174.395 0 176.215 136.97 ; + RECT 169.245 0 171.065 136.97 ; + RECT 272.625 0 278.51 136.97 ; + RECT 263.785 0 267.685 136.97 ; + RECT 263.785 47.305 278.51 53.15 ; + RECT 254.945 0 258.845 136.97 ; + RECT 246.105 0 250.005 136.97 ; + RECT 246.105 47.305 258.845 53.15 ; + RECT 237.265 0 241.165 136.97 ; + RECT 228.425 0 232.325 136.97 ; + RECT 228.425 47.305 241.165 53.15 ; + RECT 219.585 0 223.485 136.97 ; + RECT 210.745 0 214.645 136.97 ; + RECT 210.745 47.305 223.485 53.15 ; + RECT 164.095 0 165.915 136.97 ; + RECT 158.945 0 160.765 136.97 ; + RECT 153.795 0 155.615 136.97 ; + RECT 148.645 0 150.465 136.97 ; + RECT 143.495 0 145.315 136.97 ; + RECT 138.345 0 140.165 136.97 ; + RECT 133.195 0 135.015 136.97 ; + RECT 128.045 0 129.865 136.97 ; + RECT 122.895 0 124.715 136.97 ; + RECT 117.745 0 119.565 136.97 ; + RECT 112.595 0 114.415 136.97 ; + RECT 107.445 0 109.265 136.97 ; + RECT 102.295 0 104.115 136.97 ; + RECT 72.705 0 98.965 136.97 ; + RECT 63.865 0 67.765 136.97 ; + RECT 55.025 0 58.925 136.97 ; + RECT 55.025 47.305 67.765 53.15 ; + RECT 46.185 0 50.085 136.97 ; + RECT 37.345 0 41.245 136.97 ; + RECT 37.345 47.305 50.085 53.15 ; + RECT 28.505 0 32.405 136.97 ; + RECT 19.665 0 23.565 136.97 ; + RECT 19.665 47.305 32.405 53.15 ; + RECT 10.825 0 14.725 136.97 ; + RECT 0 0 5.885 136.97 ; + RECT 0 47.305 14.725 53.15 ; + END +END RM_IHPSG13_2P_256x8_c2_bm_bist + +END LIBRARY diff --git a/flow/platforms/ihp-sg13g2/lef/RM_IHPSG13_2P_512x16_c2_bm_bist.lef b/flow/platforms/ihp-sg13g2/lef/RM_IHPSG13_2P_512x16_c2_bm_bist.lef new file mode 100644 index 0000000000..4766af7880 --- /dev/null +++ b/flow/platforms/ihp-sg13g2/lef/RM_IHPSG13_2P_512x16_c2_bm_bist.lef @@ -0,0 +1,4259 @@ +# ------------------------------------------------------ +# +# Copyright 2025 IHP PDK Authors +# +# Licensed under the Apache License, Version 2.0 (the "License"); +# you may not use this file except in compliance with the License. +# You may obtain a copy of the License at +# +# https://www.apache.org/licenses/LICENSE-2.0 +# +# Unless required by applicable law or agreed to in writing, software +# distributed under the License is distributed on an "AS IS" BASIS, +# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +# See the License for the specific language governing permissions and +# limitations under the License. +# +# Generated on Wed Aug 27 13:18:16 2025 +# +# ------------------------------------------------------ +VERSION 5.7 ; +BUSBITCHARS "[]" ; +DIVIDERCHAR "/" ; + +MACRO RM_IHPSG13_2P_512x16_c2_bm_bist + CLASS BLOCK ; + ORIGIN 0 0 ; + FOREIGN RM_IHPSG13_2P_512x16_c2_bm_bist 0 0 ; + SIZE 402.61 BY 219.77 ; + SYMMETRY X Y R90 ; + PIN A_DIN[8] + DIRECTION INPUT ; + USE SIGNAL ; + ANTENNAPARTIALMETALAREA 3.9091 LAYER Metal2 ; + ANTENNAMODEL OXIDE1 ; + ANTENNAGATEAREA 0.20085 LAYER Metal2 ; + ANTENNAMAXAREACAR 20.368932 LAYER Metal2 ; + PORT + LAYER Metal2 ; + RECT 266.71 0 266.97 0.26 ; + END + END A_DIN[8] + PIN A_DIN[7] + DIRECTION INPUT ; + USE SIGNAL ; + ANTENNAPARTIALMETALAREA 3.9091 LAYER Metal2 ; + ANTENNAMODEL OXIDE1 ; + ANTENNAGATEAREA 0.20085 LAYER Metal2 ; + ANTENNAMAXAREACAR 20.368932 LAYER Metal2 ; + PORT + LAYER Metal2 ; + RECT 135.64 0 135.9 0.26 ; + END + END A_DIN[7] + PIN A_BIST_DIN[8] + DIRECTION INPUT ; + USE SIGNAL ; + ANTENNAPARTIALMETALAREA 4.136375 LAYER Metal2 ; + ANTENNAMODEL OXIDE1 ; + ANTENNAGATEAREA 0.20085 LAYER Metal2 ; + ANTENNAMAXAREACAR 21.874907 LAYER Metal2 ; + PORT + LAYER Metal2 ; + RECT 267.22 0 267.48 0.26 ; + END + END A_BIST_DIN[8] + PIN A_BIST_DIN[7] + DIRECTION INPUT ; + USE SIGNAL ; + ANTENNAPARTIALMETALAREA 4.136375 LAYER Metal2 ; + ANTENNAMODEL OXIDE1 ; + ANTENNAGATEAREA 0.20085 LAYER Metal2 ; + ANTENNAMAXAREACAR 21.874907 LAYER Metal2 ; + PORT + LAYER Metal2 ; + RECT 135.13 0 135.39 0.26 ; + END + END A_BIST_DIN[7] + PIN A_BM[8] + DIRECTION INPUT ; + USE SIGNAL ; + ANTENNAPARTIALMETALAREA 1.7264 LAYER Metal2 ; + ANTENNAMODEL OXIDE1 ; + ANTENNAGATEAREA 0.20085 LAYER Metal2 ; + ANTENNAMAXAREACAR 9.501618 LAYER Metal2 ; + PORT + LAYER Metal2 ; + RECT 275.38 0 275.64 0.26 ; + END + END A_BM[8] + PIN A_BM[7] + DIRECTION INPUT ; + USE SIGNAL ; + ANTENNAPARTIALMETALAREA 1.7264 LAYER Metal2 ; + ANTENNAMODEL OXIDE1 ; + ANTENNAGATEAREA 0.20085 LAYER Metal2 ; + ANTENNAMAXAREACAR 9.501618 LAYER Metal2 ; + PORT + LAYER Metal2 ; + RECT 126.97 0 127.23 0.26 ; + END + END A_BM[7] + PIN A_BIST_BM[8] + DIRECTION INPUT ; + USE SIGNAL ; + ANTENNAPARTIALMETALAREA 1.7602 LAYER Metal2 ; + ANTENNAMODEL OXIDE1 ; + ANTENNAGATEAREA 0.20085 LAYER Metal2 ; + ANTENNAMAXAREACAR 9.678367 LAYER Metal2 ; + PORT + LAYER Metal2 ; + RECT 274.005 0 274.265 0.26 ; + END + END A_BIST_BM[8] + PIN A_BIST_BM[7] + DIRECTION INPUT ; + USE SIGNAL ; + ANTENNAPARTIALMETALAREA 1.7602 LAYER Metal2 ; + ANTENNAMODEL OXIDE1 ; + ANTENNAGATEAREA 0.20085 LAYER Metal2 ; + ANTENNAMAXAREACAR 9.678367 LAYER Metal2 ; + PORT + LAYER Metal2 ; + RECT 128.345 0 128.605 0.26 ; + END + END A_BIST_BM[7] + PIN A_DOUT[8] + DIRECTION OUTPUT ; + USE SIGNAL ; + ANTENNAPARTIALMETALAREA 4.8256 LAYER Metal2 ; + ANTENNADIFFAREA 0.988 LAYER Metal2 ; + PORT + LAYER Metal2 ; + RECT 259.57 0 259.83 0.26 ; + END + END A_DOUT[8] + PIN A_DOUT[7] + DIRECTION OUTPUT ; + USE SIGNAL ; + ANTENNAPARTIALMETALAREA 4.8256 LAYER Metal2 ; + ANTENNADIFFAREA 0.988 LAYER Metal2 ; + PORT + LAYER Metal2 ; + RECT 142.78 0 143.04 0.26 ; + END + END A_DOUT[7] + PIN B_DIN[8] + DIRECTION INPUT ; + USE SIGNAL ; + ANTENNAPARTIALMETALAREA 2.925 LAYER Metal2 ; + ANTENNAMODEL OXIDE1 ; + ANTENNAGATEAREA 0.20085 LAYER Metal2 ; + ANTENNAMAXAREACAR 15.469256 LAYER Metal2 ; + PORT + LAYER Metal2 ; + RECT 269.26 0 269.52 0.26 ; + END + END B_DIN[8] + PIN B_DIN[7] + DIRECTION INPUT ; + USE SIGNAL ; + ANTENNAPARTIALMETALAREA 2.925 LAYER Metal2 ; + ANTENNAMODEL OXIDE1 ; + ANTENNAGATEAREA 0.20085 LAYER Metal2 ; + ANTENNAMAXAREACAR 15.469256 LAYER Metal2 ; + PORT + LAYER Metal2 ; + RECT 133.09 0 133.35 0.26 ; + END + END B_DIN[7] + PIN B_BIST_DIN[8] + DIRECTION INPUT ; + USE SIGNAL ; + ANTENNAPARTIALMETALAREA 2.9445 LAYER Metal2 ; + ANTENNAMODEL OXIDE1 ; + ANTENNAGATEAREA 0.20085 LAYER Metal2 ; + ANTENNAMAXAREACAR 15.929052 LAYER Metal2 ; + PORT + LAYER Metal2 ; + RECT 267.73 0 267.99 0.26 ; + END + END B_BIST_DIN[8] + PIN B_BIST_DIN[7] + DIRECTION INPUT ; + USE SIGNAL ; + ANTENNAPARTIALMETALAREA 2.9445 LAYER Metal2 ; + ANTENNAMODEL OXIDE1 ; + ANTENNAGATEAREA 0.20085 LAYER Metal2 ; + ANTENNAMAXAREACAR 15.929052 LAYER Metal2 ; + PORT + LAYER Metal2 ; + RECT 134.62 0 134.88 0.26 ; + END + END B_BIST_DIN[7] + PIN B_BM[8] + DIRECTION INPUT ; + USE SIGNAL ; + ANTENNAPARTIALMETALAREA 0.7007 LAYER Metal2 ; + ANTENNAMODEL OXIDE1 ; + ANTENNAGATEAREA 0.20085 LAYER Metal2 ; + ANTENNAMAXAREACAR 4.394822 LAYER Metal2 ; + PORT + LAYER Metal2 ; + RECT 260.745 0 261.005 0.26 ; + END + END B_BM[8] + PIN B_BM[7] + DIRECTION INPUT ; + USE SIGNAL ; + ANTENNAPARTIALMETALAREA 0.7007 LAYER Metal2 ; + ANTENNAMODEL OXIDE1 ; + ANTENNAGATEAREA 0.20085 LAYER Metal2 ; + ANTENNAMAXAREACAR 4.394822 LAYER Metal2 ; + PORT + LAYER Metal2 ; + RECT 141.605 0 141.865 0.26 ; + END + END B_BM[7] + PIN B_BIST_BM[8] + DIRECTION INPUT ; + USE SIGNAL ; + ANTENNAPARTIALMETALAREA 0.7007 LAYER Metal2 ; + ANTENNAMODEL OXIDE1 ; + ANTENNAGATEAREA 0.20085 LAYER Metal2 ; + ANTENNAMAXAREACAR 4.394822 LAYER Metal2 ; + PORT + LAYER Metal2 ; + RECT 262.275 0 262.535 0.26 ; + END + END B_BIST_BM[8] + PIN B_BIST_BM[7] + DIRECTION INPUT ; + USE SIGNAL ; + ANTENNAPARTIALMETALAREA 0.7007 LAYER Metal2 ; + ANTENNAMODEL OXIDE1 ; + ANTENNAGATEAREA 0.20085 LAYER Metal2 ; + ANTENNAMAXAREACAR 4.394822 LAYER Metal2 ; + PORT + LAYER Metal2 ; + RECT 140.075 0 140.335 0.26 ; + END + END B_BIST_BM[7] + PIN B_DOUT[8] + DIRECTION OUTPUT ; + USE SIGNAL ; + ANTENNAPARTIALMETALAREA 4.836 LAYER Metal2 ; + ANTENNADIFFAREA 0.988 LAYER Metal2 ; + PORT + LAYER Metal2 ; + RECT 276.4 0 276.66 0.26 ; + END + END B_DOUT[8] + PIN B_DOUT[7] + DIRECTION OUTPUT ; + USE SIGNAL ; + ANTENNAPARTIALMETALAREA 4.836 LAYER Metal2 ; + ANTENNADIFFAREA 0.988 LAYER Metal2 ; + PORT + LAYER Metal2 ; + RECT 125.95 0 126.21 0.26 ; + END + END B_DOUT[7] + PIN VSS! + DIRECTION INOUT ; + USE GROUND ; + NETEXPR "vss VSS!" ; + PORT + LAYER Metal4 ; + RECT 383.205 0 387.625 219.77 ; + END + PORT + LAYER Metal4 ; + RECT 365.525 0 369.945 219.77 ; + END + PORT + LAYER Metal4 ; + RECT 347.845 0 352.265 219.77 ; + END + PORT + LAYER Metal4 ; + RECT 330.165 0 334.585 219.77 ; + END + PORT + LAYER Metal4 ; + RECT 312.485 0 316.905 219.77 ; + END + PORT + LAYER Metal4 ; + RECT 294.805 0 299.225 219.77 ; + END + PORT + LAYER Metal4 ; + RECT 277.125 0 281.545 219.77 ; + END + PORT + LAYER Metal4 ; + RECT 259.445 0 263.865 219.77 ; + END + PORT + LAYER Metal4 ; + RECT 238.525 0 241.335 219.77 ; + END + PORT + LAYER Metal4 ; + RECT 228.225 0 231.035 219.77 ; + END + PORT + LAYER Metal4 ; + RECT 212.775 0 215.585 219.77 ; + END + PORT + LAYER Metal4 ; + RECT 202.475 0 205.285 219.77 ; + END + PORT + LAYER Metal4 ; + RECT 197.325 0 200.135 219.77 ; + END + PORT + LAYER Metal4 ; + RECT 187.025 0 189.835 219.77 ; + END + PORT + LAYER Metal4 ; + RECT 171.575 0 174.385 219.77 ; + END + PORT + LAYER Metal4 ; + RECT 161.275 0 164.085 219.77 ; + END + PORT + LAYER Metal4 ; + RECT 138.745 0 143.165 219.77 ; + END + PORT + LAYER Metal4 ; + RECT 121.065 0 125.485 219.77 ; + END + PORT + LAYER Metal4 ; + RECT 103.385 0 107.805 219.77 ; + END + PORT + LAYER Metal4 ; + RECT 85.705 0 90.125 219.77 ; + END + PORT + LAYER Metal4 ; + RECT 68.025 0 72.445 219.77 ; + END + PORT + LAYER Metal4 ; + RECT 50.345 0 54.765 219.77 ; + END + PORT + LAYER Metal4 ; + RECT 32.665 0 37.085 219.77 ; + END + PORT + LAYER Metal4 ; + RECT 14.985 0 19.405 219.77 ; + END + END VSS! + PIN VDD! + DIRECTION INOUT ; + USE POWER ; + NETEXPR "vdd VDD!" ; + PORT + LAYER Metal4 ; + RECT 392.045 0 396.465 47.045 ; + END + PORT + LAYER Metal4 ; + RECT 374.365 0 378.785 47.045 ; + END + PORT + LAYER Metal4 ; + RECT 356.685 0 361.105 47.045 ; + END + PORT + LAYER Metal4 ; + RECT 339.005 0 343.425 47.045 ; + END + PORT + LAYER Metal4 ; + RECT 321.325 0 325.745 47.045 ; + END + PORT + LAYER Metal4 ; + RECT 303.645 0 308.065 47.045 ; + END + PORT + LAYER Metal4 ; + RECT 285.965 0 290.385 47.045 ; + END + PORT + LAYER Metal4 ; + RECT 268.285 0 272.705 47.045 ; + END + PORT + LAYER Metal4 ; + RECT 233.375 0 236.185 219.77 ; + END + PORT + LAYER Metal4 ; + RECT 223.075 0 225.885 219.77 ; + END + PORT + LAYER Metal4 ; + RECT 217.925 0 220.735 219.77 ; + END + PORT + LAYER Metal4 ; + RECT 207.625 0 210.435 219.77 ; + END + PORT + LAYER Metal4 ; + RECT 192.175 0 194.985 219.77 ; + END + PORT + LAYER Metal4 ; + RECT 181.875 0 184.685 219.77 ; + END + PORT + LAYER Metal4 ; + RECT 176.725 0 179.535 219.77 ; + END + PORT + LAYER Metal4 ; + RECT 166.425 0 169.235 219.77 ; + END + PORT + LAYER Metal4 ; + RECT 129.905 0 134.325 47.045 ; + END + PORT + LAYER Metal4 ; + RECT 112.225 0 116.645 47.045 ; + END + PORT + LAYER Metal4 ; + RECT 94.545 0 98.965 47.045 ; + END + PORT + LAYER Metal4 ; + RECT 76.865 0 81.285 47.045 ; + END + PORT + LAYER Metal4 ; + RECT 59.185 0 63.605 47.045 ; + END + PORT + LAYER Metal4 ; + RECT 41.505 0 45.925 47.045 ; + END + PORT + LAYER Metal4 ; + RECT 23.825 0 28.245 47.045 ; + END + PORT + LAYER Metal4 ; + RECT 6.145 0 10.565 47.045 ; + END + END VDD! + PIN VDDARRAY! + DIRECTION INOUT ; + USE POWER ; + NETEXPR "vddarray VDDARRAY!" ; + PORT + LAYER Metal4 ; + RECT 392.045 53.41 396.465 219.77 ; + END + PORT + LAYER Metal4 ; + RECT 374.365 53.41 378.785 219.77 ; + END + PORT + LAYER Metal4 ; + RECT 356.685 53.41 361.105 219.77 ; + END + PORT + LAYER Metal4 ; + RECT 339.005 53.41 343.425 219.77 ; + END + PORT + LAYER Metal4 ; + RECT 321.325 53.41 325.745 219.77 ; + END + PORT + LAYER Metal4 ; + RECT 303.645 53.41 308.065 219.77 ; + END + PORT + LAYER Metal4 ; + RECT 285.965 53.41 290.385 219.77 ; + END + PORT + LAYER Metal4 ; + RECT 268.285 53.41 272.705 219.77 ; + END + PORT + LAYER Metal4 ; + RECT 129.905 53.41 134.325 219.77 ; + END + PORT + LAYER Metal4 ; + RECT 112.225 53.41 116.645 219.77 ; + END + PORT + LAYER Metal4 ; + RECT 94.545 53.41 98.965 219.77 ; + END + PORT + LAYER Metal4 ; + RECT 76.865 53.41 81.285 219.77 ; + END + PORT + LAYER Metal4 ; + RECT 59.185 53.41 63.605 219.77 ; + END + PORT + LAYER Metal4 ; + RECT 41.505 53.41 45.925 219.77 ; + END + PORT + LAYER Metal4 ; + RECT 23.825 53.41 28.245 219.77 ; + END + PORT + LAYER Metal4 ; + RECT 6.145 53.41 10.565 219.77 ; + END + END VDDARRAY! + PIN A_DIN[9] + DIRECTION INPUT ; + USE SIGNAL ; + ANTENNAPARTIALMETALAREA 3.9091 LAYER Metal2 ; + ANTENNAMODEL OXIDE1 ; + ANTENNAGATEAREA 0.20085 LAYER Metal2 ; + ANTENNAMAXAREACAR 20.368932 LAYER Metal2 ; + PORT + LAYER Metal2 ; + RECT 284.39 0 284.65 0.26 ; + END + END A_DIN[9] + PIN A_DIN[6] + DIRECTION INPUT ; + USE SIGNAL ; + ANTENNAPARTIALMETALAREA 3.9091 LAYER Metal2 ; + ANTENNAMODEL OXIDE1 ; + ANTENNAGATEAREA 0.20085 LAYER Metal2 ; + ANTENNAMAXAREACAR 20.368932 LAYER Metal2 ; + PORT + LAYER Metal2 ; + RECT 117.96 0 118.22 0.26 ; + END + END A_DIN[6] + PIN A_BIST_DIN[9] + DIRECTION INPUT ; + USE SIGNAL ; + ANTENNAPARTIALMETALAREA 4.136375 LAYER Metal2 ; + ANTENNAMODEL OXIDE1 ; + ANTENNAGATEAREA 0.20085 LAYER Metal2 ; + ANTENNAMAXAREACAR 21.874907 LAYER Metal2 ; + PORT + LAYER Metal2 ; + RECT 284.9 0 285.16 0.26 ; + END + END A_BIST_DIN[9] + PIN A_BIST_DIN[6] + DIRECTION INPUT ; + USE SIGNAL ; + ANTENNAPARTIALMETALAREA 4.136375 LAYER Metal2 ; + ANTENNAMODEL OXIDE1 ; + ANTENNAGATEAREA 0.20085 LAYER Metal2 ; + ANTENNAMAXAREACAR 21.874907 LAYER Metal2 ; + PORT + LAYER Metal2 ; + RECT 117.45 0 117.71 0.26 ; + END + END A_BIST_DIN[6] + PIN A_BM[9] + DIRECTION INPUT ; + USE SIGNAL ; + ANTENNAPARTIALMETALAREA 1.7264 LAYER Metal2 ; + ANTENNAMODEL OXIDE1 ; + ANTENNAGATEAREA 0.20085 LAYER Metal2 ; + ANTENNAMAXAREACAR 9.501618 LAYER Metal2 ; + PORT + LAYER Metal2 ; + RECT 293.06 0 293.32 0.26 ; + END + END A_BM[9] + PIN A_BM[6] + DIRECTION INPUT ; + USE SIGNAL ; + ANTENNAPARTIALMETALAREA 1.7264 LAYER Metal2 ; + ANTENNAMODEL OXIDE1 ; + ANTENNAGATEAREA 0.20085 LAYER Metal2 ; + ANTENNAMAXAREACAR 9.501618 LAYER Metal2 ; + PORT + LAYER Metal2 ; + RECT 109.29 0 109.55 0.26 ; + END + END A_BM[6] + PIN A_BIST_BM[9] + DIRECTION INPUT ; + USE SIGNAL ; + ANTENNAPARTIALMETALAREA 1.7602 LAYER Metal2 ; + ANTENNAMODEL OXIDE1 ; + ANTENNAGATEAREA 0.20085 LAYER Metal2 ; + ANTENNAMAXAREACAR 9.678367 LAYER Metal2 ; + PORT + LAYER Metal2 ; + RECT 291.685 0 291.945 0.26 ; + END + END A_BIST_BM[9] + PIN A_BIST_BM[6] + DIRECTION INPUT ; + USE SIGNAL ; + ANTENNAPARTIALMETALAREA 1.7602 LAYER Metal2 ; + ANTENNAMODEL OXIDE1 ; + ANTENNAGATEAREA 0.20085 LAYER Metal2 ; + ANTENNAMAXAREACAR 9.678367 LAYER Metal2 ; + PORT + LAYER Metal2 ; + RECT 110.665 0 110.925 0.26 ; + END + END A_BIST_BM[6] + PIN A_DOUT[9] + DIRECTION OUTPUT ; + USE SIGNAL ; + ANTENNAPARTIALMETALAREA 4.8256 LAYER Metal2 ; + ANTENNADIFFAREA 0.988 LAYER Metal2 ; + PORT + LAYER Metal2 ; + RECT 277.25 0 277.51 0.26 ; + END + END A_DOUT[9] + PIN A_DOUT[6] + DIRECTION OUTPUT ; + USE SIGNAL ; + ANTENNAPARTIALMETALAREA 4.8256 LAYER Metal2 ; + ANTENNADIFFAREA 0.988 LAYER Metal2 ; + PORT + LAYER Metal2 ; + RECT 125.1 0 125.36 0.26 ; + END + END A_DOUT[6] + PIN B_DIN[9] + DIRECTION INPUT ; + USE SIGNAL ; + ANTENNAPARTIALMETALAREA 2.925 LAYER Metal2 ; + ANTENNAMODEL OXIDE1 ; + ANTENNAGATEAREA 0.20085 LAYER Metal2 ; + ANTENNAMAXAREACAR 15.469256 LAYER Metal2 ; + PORT + LAYER Metal2 ; + RECT 286.94 0 287.2 0.26 ; + END + END B_DIN[9] + PIN B_DIN[6] + DIRECTION INPUT ; + USE SIGNAL ; + ANTENNAPARTIALMETALAREA 2.925 LAYER Metal2 ; + ANTENNAMODEL OXIDE1 ; + ANTENNAGATEAREA 0.20085 LAYER Metal2 ; + ANTENNAMAXAREACAR 15.469256 LAYER Metal2 ; + PORT + LAYER Metal2 ; + RECT 115.41 0 115.67 0.26 ; + END + END B_DIN[6] + PIN B_BIST_DIN[9] + DIRECTION INPUT ; + USE SIGNAL ; + ANTENNAPARTIALMETALAREA 2.9445 LAYER Metal2 ; + ANTENNAMODEL OXIDE1 ; + ANTENNAGATEAREA 0.20085 LAYER Metal2 ; + ANTENNAMAXAREACAR 15.929052 LAYER Metal2 ; + PORT + LAYER Metal2 ; + RECT 285.41 0 285.67 0.26 ; + END + END B_BIST_DIN[9] + PIN B_BIST_DIN[6] + DIRECTION INPUT ; + USE SIGNAL ; + ANTENNAPARTIALMETALAREA 2.9445 LAYER Metal2 ; + ANTENNAMODEL OXIDE1 ; + ANTENNAGATEAREA 0.20085 LAYER Metal2 ; + ANTENNAMAXAREACAR 15.929052 LAYER Metal2 ; + PORT + LAYER Metal2 ; + RECT 116.94 0 117.2 0.26 ; + END + END B_BIST_DIN[6] + PIN B_BM[9] + DIRECTION INPUT ; + USE SIGNAL ; + ANTENNAPARTIALMETALAREA 0.7007 LAYER Metal2 ; + ANTENNAMODEL OXIDE1 ; + ANTENNAGATEAREA 0.20085 LAYER Metal2 ; + ANTENNAMAXAREACAR 4.394822 LAYER Metal2 ; + PORT + LAYER Metal2 ; + RECT 278.425 0 278.685 0.26 ; + END + END B_BM[9] + PIN B_BM[6] + DIRECTION INPUT ; + USE SIGNAL ; + ANTENNAPARTIALMETALAREA 0.7007 LAYER Metal2 ; + ANTENNAMODEL OXIDE1 ; + ANTENNAGATEAREA 0.20085 LAYER Metal2 ; + ANTENNAMAXAREACAR 4.394822 LAYER Metal2 ; + PORT + LAYER Metal2 ; + RECT 123.925 0 124.185 0.26 ; + END + END B_BM[6] + PIN B_BIST_BM[9] + DIRECTION INPUT ; + USE SIGNAL ; + ANTENNAPARTIALMETALAREA 0.7007 LAYER Metal2 ; + ANTENNAMODEL OXIDE1 ; + ANTENNAGATEAREA 0.20085 LAYER Metal2 ; + ANTENNAMAXAREACAR 4.394822 LAYER Metal2 ; + PORT + LAYER Metal2 ; + RECT 279.955 0 280.215 0.26 ; + END + END B_BIST_BM[9] + PIN B_BIST_BM[6] + DIRECTION INPUT ; + USE SIGNAL ; + ANTENNAPARTIALMETALAREA 0.7007 LAYER Metal2 ; + ANTENNAMODEL OXIDE1 ; + ANTENNAGATEAREA 0.20085 LAYER Metal2 ; + ANTENNAMAXAREACAR 4.394822 LAYER Metal2 ; + PORT + LAYER Metal2 ; + RECT 122.395 0 122.655 0.26 ; + END + END B_BIST_BM[6] + PIN B_DOUT[9] + DIRECTION OUTPUT ; + USE SIGNAL ; + ANTENNAPARTIALMETALAREA 4.836 LAYER Metal2 ; + ANTENNADIFFAREA 0.988 LAYER Metal2 ; + PORT + LAYER Metal2 ; + RECT 294.08 0 294.34 0.26 ; + END + END B_DOUT[9] + PIN B_DOUT[6] + DIRECTION OUTPUT ; + USE SIGNAL ; + ANTENNAPARTIALMETALAREA 4.836 LAYER Metal2 ; + ANTENNADIFFAREA 0.988 LAYER Metal2 ; + PORT + LAYER Metal2 ; + RECT 108.27 0 108.53 0.26 ; + END + END B_DOUT[6] + PIN A_DIN[10] + DIRECTION INPUT ; + USE SIGNAL ; + ANTENNAPARTIALMETALAREA 3.9091 LAYER Metal2 ; + ANTENNAMODEL OXIDE1 ; + ANTENNAGATEAREA 0.20085 LAYER Metal2 ; + ANTENNAMAXAREACAR 20.368932 LAYER Metal2 ; + PORT + LAYER Metal2 ; + RECT 302.07 0 302.33 0.26 ; + END + END A_DIN[10] + PIN A_DIN[5] + DIRECTION INPUT ; + USE SIGNAL ; + ANTENNAPARTIALMETALAREA 3.9091 LAYER Metal2 ; + ANTENNAMODEL OXIDE1 ; + ANTENNAGATEAREA 0.20085 LAYER Metal2 ; + ANTENNAMAXAREACAR 20.368932 LAYER Metal2 ; + PORT + LAYER Metal2 ; + RECT 100.28 0 100.54 0.26 ; + END + END A_DIN[5] + PIN A_BIST_DIN[10] + DIRECTION INPUT ; + USE SIGNAL ; + ANTENNAPARTIALMETALAREA 4.136375 LAYER Metal2 ; + ANTENNAMODEL OXIDE1 ; + ANTENNAGATEAREA 0.20085 LAYER Metal2 ; + ANTENNAMAXAREACAR 21.874907 LAYER Metal2 ; + PORT + LAYER Metal2 ; + RECT 302.58 0 302.84 0.26 ; + END + END A_BIST_DIN[10] + PIN A_BIST_DIN[5] + DIRECTION INPUT ; + USE SIGNAL ; + ANTENNAPARTIALMETALAREA 4.136375 LAYER Metal2 ; + ANTENNAMODEL OXIDE1 ; + ANTENNAGATEAREA 0.20085 LAYER Metal2 ; + ANTENNAMAXAREACAR 21.874907 LAYER Metal2 ; + PORT + LAYER Metal2 ; + RECT 99.77 0 100.03 0.26 ; + END + END A_BIST_DIN[5] + PIN A_BM[10] + DIRECTION INPUT ; + USE SIGNAL ; + ANTENNAPARTIALMETALAREA 1.7264 LAYER Metal2 ; + ANTENNAMODEL OXIDE1 ; + ANTENNAGATEAREA 0.20085 LAYER Metal2 ; + ANTENNAMAXAREACAR 9.501618 LAYER Metal2 ; + PORT + LAYER Metal2 ; + RECT 310.74 0 311 0.26 ; + END + END A_BM[10] + PIN A_BM[5] + DIRECTION INPUT ; + USE SIGNAL ; + ANTENNAPARTIALMETALAREA 1.7264 LAYER Metal2 ; + ANTENNAMODEL OXIDE1 ; + ANTENNAGATEAREA 0.20085 LAYER Metal2 ; + ANTENNAMAXAREACAR 9.501618 LAYER Metal2 ; + PORT + LAYER Metal2 ; + RECT 91.61 0 91.87 0.26 ; + END + END A_BM[5] + PIN A_BIST_BM[10] + DIRECTION INPUT ; + USE SIGNAL ; + ANTENNAPARTIALMETALAREA 1.7602 LAYER Metal2 ; + ANTENNAMODEL OXIDE1 ; + ANTENNAGATEAREA 0.20085 LAYER Metal2 ; + ANTENNAMAXAREACAR 9.678367 LAYER Metal2 ; + PORT + LAYER Metal2 ; + RECT 309.365 0 309.625 0.26 ; + END + END A_BIST_BM[10] + PIN A_BIST_BM[5] + DIRECTION INPUT ; + USE SIGNAL ; + ANTENNAPARTIALMETALAREA 1.7602 LAYER Metal2 ; + ANTENNAMODEL OXIDE1 ; + ANTENNAGATEAREA 0.20085 LAYER Metal2 ; + ANTENNAMAXAREACAR 9.678367 LAYER Metal2 ; + PORT + LAYER Metal2 ; + RECT 92.985 0 93.245 0.26 ; + END + END A_BIST_BM[5] + PIN A_DOUT[10] + DIRECTION OUTPUT ; + USE SIGNAL ; + ANTENNAPARTIALMETALAREA 4.8256 LAYER Metal2 ; + ANTENNADIFFAREA 0.988 LAYER Metal2 ; + PORT + LAYER Metal2 ; + RECT 294.93 0 295.19 0.26 ; + END + END A_DOUT[10] + PIN A_DOUT[5] + DIRECTION OUTPUT ; + USE SIGNAL ; + ANTENNAPARTIALMETALAREA 4.8256 LAYER Metal2 ; + ANTENNADIFFAREA 0.988 LAYER Metal2 ; + PORT + LAYER Metal2 ; + RECT 107.42 0 107.68 0.26 ; + END + END A_DOUT[5] + PIN B_DIN[10] + DIRECTION INPUT ; + USE SIGNAL ; + ANTENNAPARTIALMETALAREA 2.925 LAYER Metal2 ; + ANTENNAMODEL OXIDE1 ; + ANTENNAGATEAREA 0.20085 LAYER Metal2 ; + ANTENNAMAXAREACAR 15.469256 LAYER Metal2 ; + PORT + LAYER Metal2 ; + RECT 304.62 0 304.88 0.26 ; + END + END B_DIN[10] + PIN B_DIN[5] + DIRECTION INPUT ; + USE SIGNAL ; + ANTENNAPARTIALMETALAREA 2.925 LAYER Metal2 ; + ANTENNAMODEL OXIDE1 ; + ANTENNAGATEAREA 0.20085 LAYER Metal2 ; + ANTENNAMAXAREACAR 15.469256 LAYER Metal2 ; + PORT + LAYER Metal2 ; + RECT 97.73 0 97.99 0.26 ; + END + END B_DIN[5] + PIN B_BIST_DIN[10] + DIRECTION INPUT ; + USE SIGNAL ; + ANTENNAPARTIALMETALAREA 2.9445 LAYER Metal2 ; + ANTENNAMODEL OXIDE1 ; + ANTENNAGATEAREA 0.20085 LAYER Metal2 ; + ANTENNAMAXAREACAR 15.929052 LAYER Metal2 ; + PORT + LAYER Metal2 ; + RECT 303.09 0 303.35 0.26 ; + END + END B_BIST_DIN[10] + PIN B_BIST_DIN[5] + DIRECTION INPUT ; + USE SIGNAL ; + ANTENNAPARTIALMETALAREA 2.9445 LAYER Metal2 ; + ANTENNAMODEL OXIDE1 ; + ANTENNAGATEAREA 0.20085 LAYER Metal2 ; + ANTENNAMAXAREACAR 15.929052 LAYER Metal2 ; + PORT + LAYER Metal2 ; + RECT 99.26 0 99.52 0.26 ; + END + END B_BIST_DIN[5] + PIN B_BM[10] + DIRECTION INPUT ; + USE SIGNAL ; + ANTENNAPARTIALMETALAREA 0.7007 LAYER Metal2 ; + ANTENNAMODEL OXIDE1 ; + ANTENNAGATEAREA 0.20085 LAYER Metal2 ; + ANTENNAMAXAREACAR 4.394822 LAYER Metal2 ; + PORT + LAYER Metal2 ; + RECT 296.105 0 296.365 0.26 ; + END + END B_BM[10] + PIN B_BM[5] + DIRECTION INPUT ; + USE SIGNAL ; + ANTENNAPARTIALMETALAREA 0.7007 LAYER Metal2 ; + ANTENNAMODEL OXIDE1 ; + ANTENNAGATEAREA 0.20085 LAYER Metal2 ; + ANTENNAMAXAREACAR 4.394822 LAYER Metal2 ; + PORT + LAYER Metal2 ; + RECT 106.245 0 106.505 0.26 ; + END + END B_BM[5] + PIN B_BIST_BM[10] + DIRECTION INPUT ; + USE SIGNAL ; + ANTENNAPARTIALMETALAREA 0.7007 LAYER Metal2 ; + ANTENNAMODEL OXIDE1 ; + ANTENNAGATEAREA 0.20085 LAYER Metal2 ; + ANTENNAMAXAREACAR 4.394822 LAYER Metal2 ; + PORT + LAYER Metal2 ; + RECT 297.635 0 297.895 0.26 ; + END + END B_BIST_BM[10] + PIN B_BIST_BM[5] + DIRECTION INPUT ; + USE SIGNAL ; + ANTENNAPARTIALMETALAREA 0.7007 LAYER Metal2 ; + ANTENNAMODEL OXIDE1 ; + ANTENNAGATEAREA 0.20085 LAYER Metal2 ; + ANTENNAMAXAREACAR 4.394822 LAYER Metal2 ; + PORT + LAYER Metal2 ; + RECT 104.715 0 104.975 0.26 ; + END + END B_BIST_BM[5] + PIN B_DOUT[10] + DIRECTION OUTPUT ; + USE SIGNAL ; + ANTENNAPARTIALMETALAREA 4.836 LAYER Metal2 ; + ANTENNADIFFAREA 0.988 LAYER Metal2 ; + PORT + LAYER Metal2 ; + RECT 311.76 0 312.02 0.26 ; + END + END B_DOUT[10] + PIN B_DOUT[5] + DIRECTION OUTPUT ; + USE SIGNAL ; + ANTENNAPARTIALMETALAREA 4.836 LAYER Metal2 ; + ANTENNADIFFAREA 0.988 LAYER Metal2 ; + PORT + LAYER Metal2 ; + RECT 90.59 0 90.85 0.26 ; + END + END B_DOUT[5] + PIN A_DIN[11] + DIRECTION INPUT ; + USE SIGNAL ; + ANTENNAPARTIALMETALAREA 3.9091 LAYER Metal2 ; + ANTENNAMODEL OXIDE1 ; + ANTENNAGATEAREA 0.20085 LAYER Metal2 ; + ANTENNAMAXAREACAR 20.368932 LAYER Metal2 ; + PORT + LAYER Metal2 ; + RECT 319.75 0 320.01 0.26 ; + END + END A_DIN[11] + PIN A_DIN[4] + DIRECTION INPUT ; + USE SIGNAL ; + ANTENNAPARTIALMETALAREA 3.9091 LAYER Metal2 ; + ANTENNAMODEL OXIDE1 ; + ANTENNAGATEAREA 0.20085 LAYER Metal2 ; + ANTENNAMAXAREACAR 20.368932 LAYER Metal2 ; + PORT + LAYER Metal2 ; + RECT 82.6 0 82.86 0.26 ; + END + END A_DIN[4] + PIN A_BIST_DIN[11] + DIRECTION INPUT ; + USE SIGNAL ; + ANTENNAPARTIALMETALAREA 4.136375 LAYER Metal2 ; + ANTENNAMODEL OXIDE1 ; + ANTENNAGATEAREA 0.20085 LAYER Metal2 ; + ANTENNAMAXAREACAR 21.874907 LAYER Metal2 ; + PORT + LAYER Metal2 ; + RECT 320.26 0 320.52 0.26 ; + END + END A_BIST_DIN[11] + PIN A_BIST_DIN[4] + DIRECTION INPUT ; + USE SIGNAL ; + ANTENNAPARTIALMETALAREA 4.136375 LAYER Metal2 ; + ANTENNAMODEL OXIDE1 ; + ANTENNAGATEAREA 0.20085 LAYER Metal2 ; + ANTENNAMAXAREACAR 21.874907 LAYER Metal2 ; + PORT + LAYER Metal2 ; + RECT 82.09 0 82.35 0.26 ; + END + END A_BIST_DIN[4] + PIN A_BM[11] + DIRECTION INPUT ; + USE SIGNAL ; + ANTENNAPARTIALMETALAREA 1.7264 LAYER Metal2 ; + ANTENNAMODEL OXIDE1 ; + ANTENNAGATEAREA 0.20085 LAYER Metal2 ; + ANTENNAMAXAREACAR 9.501618 LAYER Metal2 ; + PORT + LAYER Metal2 ; + RECT 328.42 0 328.68 0.26 ; + END + END A_BM[11] + PIN A_BM[4] + DIRECTION INPUT ; + USE SIGNAL ; + ANTENNAPARTIALMETALAREA 1.7264 LAYER Metal2 ; + ANTENNAMODEL OXIDE1 ; + ANTENNAGATEAREA 0.20085 LAYER Metal2 ; + ANTENNAMAXAREACAR 9.501618 LAYER Metal2 ; + PORT + LAYER Metal2 ; + RECT 73.93 0 74.19 0.26 ; + END + END A_BM[4] + PIN A_BIST_BM[11] + DIRECTION INPUT ; + USE SIGNAL ; + ANTENNAPARTIALMETALAREA 1.7602 LAYER Metal2 ; + ANTENNAMODEL OXIDE1 ; + ANTENNAGATEAREA 0.20085 LAYER Metal2 ; + ANTENNAMAXAREACAR 9.678367 LAYER Metal2 ; + PORT + LAYER Metal2 ; + RECT 327.045 0 327.305 0.26 ; + END + END A_BIST_BM[11] + PIN A_BIST_BM[4] + DIRECTION INPUT ; + USE SIGNAL ; + ANTENNAPARTIALMETALAREA 1.7602 LAYER Metal2 ; + ANTENNAMODEL OXIDE1 ; + ANTENNAGATEAREA 0.20085 LAYER Metal2 ; + ANTENNAMAXAREACAR 9.678367 LAYER Metal2 ; + PORT + LAYER Metal2 ; + RECT 75.305 0 75.565 0.26 ; + END + END A_BIST_BM[4] + PIN A_DOUT[11] + DIRECTION OUTPUT ; + USE SIGNAL ; + ANTENNAPARTIALMETALAREA 4.8256 LAYER Metal2 ; + ANTENNADIFFAREA 0.988 LAYER Metal2 ; + PORT + LAYER Metal2 ; + RECT 312.61 0 312.87 0.26 ; + END + END A_DOUT[11] + PIN A_DOUT[4] + DIRECTION OUTPUT ; + USE SIGNAL ; + ANTENNAPARTIALMETALAREA 4.8256 LAYER Metal2 ; + ANTENNADIFFAREA 0.988 LAYER Metal2 ; + PORT + LAYER Metal2 ; + RECT 89.74 0 90 0.26 ; + END + END A_DOUT[4] + PIN B_DIN[11] + DIRECTION INPUT ; + USE SIGNAL ; + ANTENNAPARTIALMETALAREA 2.925 LAYER Metal2 ; + ANTENNAMODEL OXIDE1 ; + ANTENNAGATEAREA 0.20085 LAYER Metal2 ; + ANTENNAMAXAREACAR 15.469256 LAYER Metal2 ; + PORT + LAYER Metal2 ; + RECT 322.3 0 322.56 0.26 ; + END + END B_DIN[11] + PIN B_DIN[4] + DIRECTION INPUT ; + USE SIGNAL ; + ANTENNAPARTIALMETALAREA 2.925 LAYER Metal2 ; + ANTENNAMODEL OXIDE1 ; + ANTENNAGATEAREA 0.20085 LAYER Metal2 ; + ANTENNAMAXAREACAR 15.469256 LAYER Metal2 ; + PORT + LAYER Metal2 ; + RECT 80.05 0 80.31 0.26 ; + END + END B_DIN[4] + PIN B_BIST_DIN[11] + DIRECTION INPUT ; + USE SIGNAL ; + ANTENNAPARTIALMETALAREA 2.9445 LAYER Metal2 ; + ANTENNAMODEL OXIDE1 ; + ANTENNAGATEAREA 0.20085 LAYER Metal2 ; + ANTENNAMAXAREACAR 15.929052 LAYER Metal2 ; + PORT + LAYER Metal2 ; + RECT 320.77 0 321.03 0.26 ; + END + END B_BIST_DIN[11] + PIN B_BIST_DIN[4] + DIRECTION INPUT ; + USE SIGNAL ; + ANTENNAPARTIALMETALAREA 2.9445 LAYER Metal2 ; + ANTENNAMODEL OXIDE1 ; + ANTENNAGATEAREA 0.20085 LAYER Metal2 ; + ANTENNAMAXAREACAR 15.929052 LAYER Metal2 ; + PORT + LAYER Metal2 ; + RECT 81.58 0 81.84 0.26 ; + END + END B_BIST_DIN[4] + PIN B_BM[11] + DIRECTION INPUT ; + USE SIGNAL ; + ANTENNAPARTIALMETALAREA 0.7007 LAYER Metal2 ; + ANTENNAMODEL OXIDE1 ; + ANTENNAGATEAREA 0.20085 LAYER Metal2 ; + ANTENNAMAXAREACAR 4.394822 LAYER Metal2 ; + PORT + LAYER Metal2 ; + RECT 313.785 0 314.045 0.26 ; + END + END B_BM[11] + PIN B_BM[4] + DIRECTION INPUT ; + USE SIGNAL ; + ANTENNAPARTIALMETALAREA 0.7007 LAYER Metal2 ; + ANTENNAMODEL OXIDE1 ; + ANTENNAGATEAREA 0.20085 LAYER Metal2 ; + ANTENNAMAXAREACAR 4.394822 LAYER Metal2 ; + PORT + LAYER Metal2 ; + RECT 88.565 0 88.825 0.26 ; + END + END B_BM[4] + PIN B_BIST_BM[11] + DIRECTION INPUT ; + USE SIGNAL ; + ANTENNAPARTIALMETALAREA 0.7007 LAYER Metal2 ; + ANTENNAMODEL OXIDE1 ; + ANTENNAGATEAREA 0.20085 LAYER Metal2 ; + ANTENNAMAXAREACAR 4.394822 LAYER Metal2 ; + PORT + LAYER Metal2 ; + RECT 315.315 0 315.575 0.26 ; + END + END B_BIST_BM[11] + PIN B_BIST_BM[4] + DIRECTION INPUT ; + USE SIGNAL ; + ANTENNAPARTIALMETALAREA 0.7007 LAYER Metal2 ; + ANTENNAMODEL OXIDE1 ; + ANTENNAGATEAREA 0.20085 LAYER Metal2 ; + ANTENNAMAXAREACAR 4.394822 LAYER Metal2 ; + PORT + LAYER Metal2 ; + RECT 87.035 0 87.295 0.26 ; + END + END B_BIST_BM[4] + PIN B_DOUT[11] + DIRECTION OUTPUT ; + USE SIGNAL ; + ANTENNAPARTIALMETALAREA 4.836 LAYER Metal2 ; + ANTENNADIFFAREA 0.988 LAYER Metal2 ; + PORT + LAYER Metal2 ; + RECT 329.44 0 329.7 0.26 ; + END + END B_DOUT[11] + PIN B_DOUT[4] + DIRECTION OUTPUT ; + USE SIGNAL ; + ANTENNAPARTIALMETALAREA 4.836 LAYER Metal2 ; + ANTENNADIFFAREA 0.988 LAYER Metal2 ; + PORT + LAYER Metal2 ; + RECT 72.91 0 73.17 0.26 ; + END + END B_DOUT[4] + PIN A_DIN[12] + DIRECTION INPUT ; + USE SIGNAL ; + ANTENNAPARTIALMETALAREA 3.9091 LAYER Metal2 ; + ANTENNAMODEL OXIDE1 ; + ANTENNAGATEAREA 0.20085 LAYER Metal2 ; + ANTENNAMAXAREACAR 20.368932 LAYER Metal2 ; + PORT + LAYER Metal2 ; + RECT 337.43 0 337.69 0.26 ; + END + END A_DIN[12] + PIN A_DIN[3] + DIRECTION INPUT ; + USE SIGNAL ; + ANTENNAPARTIALMETALAREA 3.9091 LAYER Metal2 ; + ANTENNAMODEL OXIDE1 ; + ANTENNAGATEAREA 0.20085 LAYER Metal2 ; + ANTENNAMAXAREACAR 20.368932 LAYER Metal2 ; + PORT + LAYER Metal2 ; + RECT 64.92 0 65.18 0.26 ; + END + END A_DIN[3] + PIN A_BIST_DIN[12] + DIRECTION INPUT ; + USE SIGNAL ; + ANTENNAPARTIALMETALAREA 4.136375 LAYER Metal2 ; + ANTENNAMODEL OXIDE1 ; + ANTENNAGATEAREA 0.20085 LAYER Metal2 ; + ANTENNAMAXAREACAR 21.874907 LAYER Metal2 ; + PORT + LAYER Metal2 ; + RECT 337.94 0 338.2 0.26 ; + END + END A_BIST_DIN[12] + PIN A_BIST_DIN[3] + DIRECTION INPUT ; + USE SIGNAL ; + ANTENNAPARTIALMETALAREA 4.136375 LAYER Metal2 ; + ANTENNAMODEL OXIDE1 ; + ANTENNAGATEAREA 0.20085 LAYER Metal2 ; + ANTENNAMAXAREACAR 21.874907 LAYER Metal2 ; + PORT + LAYER Metal2 ; + RECT 64.41 0 64.67 0.26 ; + END + END A_BIST_DIN[3] + PIN A_BM[12] + DIRECTION INPUT ; + USE SIGNAL ; + ANTENNAPARTIALMETALAREA 1.7264 LAYER Metal2 ; + ANTENNAMODEL OXIDE1 ; + ANTENNAGATEAREA 0.20085 LAYER Metal2 ; + ANTENNAMAXAREACAR 9.501618 LAYER Metal2 ; + PORT + LAYER Metal2 ; + RECT 346.1 0 346.36 0.26 ; + END + END A_BM[12] + PIN A_BM[3] + DIRECTION INPUT ; + USE SIGNAL ; + ANTENNAPARTIALMETALAREA 1.7264 LAYER Metal2 ; + ANTENNAMODEL OXIDE1 ; + ANTENNAGATEAREA 0.20085 LAYER Metal2 ; + ANTENNAMAXAREACAR 9.501618 LAYER Metal2 ; + PORT + LAYER Metal2 ; + RECT 56.25 0 56.51 0.26 ; + END + END A_BM[3] + PIN A_BIST_BM[12] + DIRECTION INPUT ; + USE SIGNAL ; + ANTENNAPARTIALMETALAREA 1.7602 LAYER Metal2 ; + ANTENNAMODEL OXIDE1 ; + ANTENNAGATEAREA 0.20085 LAYER Metal2 ; + ANTENNAMAXAREACAR 9.678367 LAYER Metal2 ; + PORT + LAYER Metal2 ; + RECT 344.725 0 344.985 0.26 ; + END + END A_BIST_BM[12] + PIN A_BIST_BM[3] + DIRECTION INPUT ; + USE SIGNAL ; + ANTENNAPARTIALMETALAREA 1.7602 LAYER Metal2 ; + ANTENNAMODEL OXIDE1 ; + ANTENNAGATEAREA 0.20085 LAYER Metal2 ; + ANTENNAMAXAREACAR 9.678367 LAYER Metal2 ; + PORT + LAYER Metal2 ; + RECT 57.625 0 57.885 0.26 ; + END + END A_BIST_BM[3] + PIN A_DOUT[12] + DIRECTION OUTPUT ; + USE SIGNAL ; + ANTENNAPARTIALMETALAREA 4.8256 LAYER Metal2 ; + ANTENNADIFFAREA 0.988 LAYER Metal2 ; + PORT + LAYER Metal2 ; + RECT 330.29 0 330.55 0.26 ; + END + END A_DOUT[12] + PIN A_DOUT[3] + DIRECTION OUTPUT ; + USE SIGNAL ; + ANTENNAPARTIALMETALAREA 4.8256 LAYER Metal2 ; + ANTENNADIFFAREA 0.988 LAYER Metal2 ; + PORT + LAYER Metal2 ; + RECT 72.06 0 72.32 0.26 ; + END + END A_DOUT[3] + PIN B_DIN[12] + DIRECTION INPUT ; + USE SIGNAL ; + ANTENNAPARTIALMETALAREA 2.925 LAYER Metal2 ; + ANTENNAMODEL OXIDE1 ; + ANTENNAGATEAREA 0.20085 LAYER Metal2 ; + ANTENNAMAXAREACAR 15.469256 LAYER Metal2 ; + PORT + LAYER Metal2 ; + RECT 339.98 0 340.24 0.26 ; + END + END B_DIN[12] + PIN B_DIN[3] + DIRECTION INPUT ; + USE SIGNAL ; + ANTENNAPARTIALMETALAREA 2.925 LAYER Metal2 ; + ANTENNAMODEL OXIDE1 ; + ANTENNAGATEAREA 0.20085 LAYER Metal2 ; + ANTENNAMAXAREACAR 15.469256 LAYER Metal2 ; + PORT + LAYER Metal2 ; + RECT 62.37 0 62.63 0.26 ; + END + END B_DIN[3] + PIN B_BIST_DIN[12] + DIRECTION INPUT ; + USE SIGNAL ; + ANTENNAPARTIALMETALAREA 2.9445 LAYER Metal2 ; + ANTENNAMODEL OXIDE1 ; + ANTENNAGATEAREA 0.20085 LAYER Metal2 ; + ANTENNAMAXAREACAR 15.929052 LAYER Metal2 ; + PORT + LAYER Metal2 ; + RECT 338.45 0 338.71 0.26 ; + END + END B_BIST_DIN[12] + PIN B_BIST_DIN[3] + DIRECTION INPUT ; + USE SIGNAL ; + ANTENNAPARTIALMETALAREA 2.9445 LAYER Metal2 ; + ANTENNAMODEL OXIDE1 ; + ANTENNAGATEAREA 0.20085 LAYER Metal2 ; + ANTENNAMAXAREACAR 15.929052 LAYER Metal2 ; + PORT + LAYER Metal2 ; + RECT 63.9 0 64.16 0.26 ; + END + END B_BIST_DIN[3] + PIN B_BM[12] + DIRECTION INPUT ; + USE SIGNAL ; + ANTENNAPARTIALMETALAREA 0.7007 LAYER Metal2 ; + ANTENNAMODEL OXIDE1 ; + ANTENNAGATEAREA 0.20085 LAYER Metal2 ; + ANTENNAMAXAREACAR 4.394822 LAYER Metal2 ; + PORT + LAYER Metal2 ; + RECT 331.465 0 331.725 0.26 ; + END + END B_BM[12] + PIN B_BM[3] + DIRECTION INPUT ; + USE SIGNAL ; + ANTENNAPARTIALMETALAREA 0.7007 LAYER Metal2 ; + ANTENNAMODEL OXIDE1 ; + ANTENNAGATEAREA 0.20085 LAYER Metal2 ; + ANTENNAMAXAREACAR 4.394822 LAYER Metal2 ; + PORT + LAYER Metal2 ; + RECT 70.885 0 71.145 0.26 ; + END + END B_BM[3] + PIN B_BIST_BM[12] + DIRECTION INPUT ; + USE SIGNAL ; + ANTENNAPARTIALMETALAREA 0.7007 LAYER Metal2 ; + ANTENNAMODEL OXIDE1 ; + ANTENNAGATEAREA 0.20085 LAYER Metal2 ; + ANTENNAMAXAREACAR 4.394822 LAYER Metal2 ; + PORT + LAYER Metal2 ; + RECT 332.995 0 333.255 0.26 ; + END + END B_BIST_BM[12] + PIN B_BIST_BM[3] + DIRECTION INPUT ; + USE SIGNAL ; + ANTENNAPARTIALMETALAREA 0.7007 LAYER Metal2 ; + ANTENNAMODEL OXIDE1 ; + ANTENNAGATEAREA 0.20085 LAYER Metal2 ; + ANTENNAMAXAREACAR 4.394822 LAYER Metal2 ; + PORT + LAYER Metal2 ; + RECT 69.355 0 69.615 0.26 ; + END + END B_BIST_BM[3] + PIN B_DOUT[12] + DIRECTION OUTPUT ; + USE SIGNAL ; + ANTENNAPARTIALMETALAREA 4.836 LAYER Metal2 ; + ANTENNADIFFAREA 0.988 LAYER Metal2 ; + PORT + LAYER Metal2 ; + RECT 347.12 0 347.38 0.26 ; + END + END B_DOUT[12] + PIN B_DOUT[3] + DIRECTION OUTPUT ; + USE SIGNAL ; + ANTENNAPARTIALMETALAREA 4.836 LAYER Metal2 ; + ANTENNADIFFAREA 0.988 LAYER Metal2 ; + PORT + LAYER Metal2 ; + RECT 55.23 0 55.49 0.26 ; + END + END B_DOUT[3] + PIN A_DIN[13] + DIRECTION INPUT ; + USE SIGNAL ; + ANTENNAPARTIALMETALAREA 3.9091 LAYER Metal2 ; + ANTENNAMODEL OXIDE1 ; + ANTENNAGATEAREA 0.20085 LAYER Metal2 ; + ANTENNAMAXAREACAR 20.368932 LAYER Metal2 ; + PORT + LAYER Metal2 ; + RECT 355.11 0 355.37 0.26 ; + END + END A_DIN[13] + PIN A_DIN[2] + DIRECTION INPUT ; + USE SIGNAL ; + ANTENNAPARTIALMETALAREA 3.9091 LAYER Metal2 ; + ANTENNAMODEL OXIDE1 ; + ANTENNAGATEAREA 0.20085 LAYER Metal2 ; + ANTENNAMAXAREACAR 20.368932 LAYER Metal2 ; + PORT + LAYER Metal2 ; + RECT 47.24 0 47.5 0.26 ; + END + END A_DIN[2] + PIN A_BIST_DIN[13] + DIRECTION INPUT ; + USE SIGNAL ; + ANTENNAPARTIALMETALAREA 4.136375 LAYER Metal2 ; + ANTENNAMODEL OXIDE1 ; + ANTENNAGATEAREA 0.20085 LAYER Metal2 ; + ANTENNAMAXAREACAR 21.874907 LAYER Metal2 ; + PORT + LAYER Metal2 ; + RECT 355.62 0 355.88 0.26 ; + END + END A_BIST_DIN[13] + PIN A_BIST_DIN[2] + DIRECTION INPUT ; + USE SIGNAL ; + ANTENNAPARTIALMETALAREA 4.136375 LAYER Metal2 ; + ANTENNAMODEL OXIDE1 ; + ANTENNAGATEAREA 0.20085 LAYER Metal2 ; + ANTENNAMAXAREACAR 21.874907 LAYER Metal2 ; + PORT + LAYER Metal2 ; + RECT 46.73 0 46.99 0.26 ; + END + END A_BIST_DIN[2] + PIN A_BM[13] + DIRECTION INPUT ; + USE SIGNAL ; + ANTENNAPARTIALMETALAREA 1.7264 LAYER Metal2 ; + ANTENNAMODEL OXIDE1 ; + ANTENNAGATEAREA 0.20085 LAYER Metal2 ; + ANTENNAMAXAREACAR 9.501618 LAYER Metal2 ; + PORT + LAYER Metal2 ; + RECT 363.78 0 364.04 0.26 ; + END + END A_BM[13] + PIN A_BM[2] + DIRECTION INPUT ; + USE SIGNAL ; + ANTENNAPARTIALMETALAREA 1.7264 LAYER Metal2 ; + ANTENNAMODEL OXIDE1 ; + ANTENNAGATEAREA 0.20085 LAYER Metal2 ; + ANTENNAMAXAREACAR 9.501618 LAYER Metal2 ; + PORT + LAYER Metal2 ; + RECT 38.57 0 38.83 0.26 ; + END + END A_BM[2] + PIN A_BIST_BM[13] + DIRECTION INPUT ; + USE SIGNAL ; + ANTENNAPARTIALMETALAREA 1.7602 LAYER Metal2 ; + ANTENNAMODEL OXIDE1 ; + ANTENNAGATEAREA 0.20085 LAYER Metal2 ; + ANTENNAMAXAREACAR 9.678367 LAYER Metal2 ; + PORT + LAYER Metal2 ; + RECT 362.405 0 362.665 0.26 ; + END + END A_BIST_BM[13] + PIN A_BIST_BM[2] + DIRECTION INPUT ; + USE SIGNAL ; + ANTENNAPARTIALMETALAREA 1.7602 LAYER Metal2 ; + ANTENNAMODEL OXIDE1 ; + ANTENNAGATEAREA 0.20085 LAYER Metal2 ; + ANTENNAMAXAREACAR 9.678367 LAYER Metal2 ; + PORT + LAYER Metal2 ; + RECT 39.945 0 40.205 0.26 ; + END + END A_BIST_BM[2] + PIN A_DOUT[13] + DIRECTION OUTPUT ; + USE SIGNAL ; + ANTENNAPARTIALMETALAREA 4.8256 LAYER Metal2 ; + ANTENNADIFFAREA 0.988 LAYER Metal2 ; + PORT + LAYER Metal2 ; + RECT 347.97 0 348.23 0.26 ; + END + END A_DOUT[13] + PIN A_DOUT[2] + DIRECTION OUTPUT ; + USE SIGNAL ; + ANTENNAPARTIALMETALAREA 4.8256 LAYER Metal2 ; + ANTENNADIFFAREA 0.988 LAYER Metal2 ; + PORT + LAYER Metal2 ; + RECT 54.38 0 54.64 0.26 ; + END + END A_DOUT[2] + PIN B_DIN[13] + DIRECTION INPUT ; + USE SIGNAL ; + ANTENNAPARTIALMETALAREA 2.925 LAYER Metal2 ; + ANTENNAMODEL OXIDE1 ; + ANTENNAGATEAREA 0.20085 LAYER Metal2 ; + ANTENNAMAXAREACAR 15.469256 LAYER Metal2 ; + PORT + LAYER Metal2 ; + RECT 357.66 0 357.92 0.26 ; + END + END B_DIN[13] + PIN B_DIN[2] + DIRECTION INPUT ; + USE SIGNAL ; + ANTENNAPARTIALMETALAREA 2.925 LAYER Metal2 ; + ANTENNAMODEL OXIDE1 ; + ANTENNAGATEAREA 0.20085 LAYER Metal2 ; + ANTENNAMAXAREACAR 15.469256 LAYER Metal2 ; + PORT + LAYER Metal2 ; + RECT 44.69 0 44.95 0.26 ; + END + END B_DIN[2] + PIN B_BIST_DIN[13] + DIRECTION INPUT ; + USE SIGNAL ; + ANTENNAPARTIALMETALAREA 2.9445 LAYER Metal2 ; + ANTENNAMODEL OXIDE1 ; + ANTENNAGATEAREA 0.20085 LAYER Metal2 ; + ANTENNAMAXAREACAR 15.929052 LAYER Metal2 ; + PORT + LAYER Metal2 ; + RECT 356.13 0 356.39 0.26 ; + END + END B_BIST_DIN[13] + PIN B_BIST_DIN[2] + DIRECTION INPUT ; + USE SIGNAL ; + ANTENNAPARTIALMETALAREA 2.9445 LAYER Metal2 ; + ANTENNAMODEL OXIDE1 ; + ANTENNAGATEAREA 0.20085 LAYER Metal2 ; + ANTENNAMAXAREACAR 15.929052 LAYER Metal2 ; + PORT + LAYER Metal2 ; + RECT 46.22 0 46.48 0.26 ; + END + END B_BIST_DIN[2] + PIN B_BM[13] + DIRECTION INPUT ; + USE SIGNAL ; + ANTENNAPARTIALMETALAREA 0.7007 LAYER Metal2 ; + ANTENNAMODEL OXIDE1 ; + ANTENNAGATEAREA 0.20085 LAYER Metal2 ; + ANTENNAMAXAREACAR 4.394822 LAYER Metal2 ; + PORT + LAYER Metal2 ; + RECT 349.145 0 349.405 0.26 ; + END + END B_BM[13] + PIN B_BM[2] + DIRECTION INPUT ; + USE SIGNAL ; + ANTENNAPARTIALMETALAREA 0.7007 LAYER Metal2 ; + ANTENNAMODEL OXIDE1 ; + ANTENNAGATEAREA 0.20085 LAYER Metal2 ; + ANTENNAMAXAREACAR 4.394822 LAYER Metal2 ; + PORT + LAYER Metal2 ; + RECT 53.205 0 53.465 0.26 ; + END + END B_BM[2] + PIN B_BIST_BM[13] + DIRECTION INPUT ; + USE SIGNAL ; + ANTENNAPARTIALMETALAREA 0.7007 LAYER Metal2 ; + ANTENNAMODEL OXIDE1 ; + ANTENNAGATEAREA 0.20085 LAYER Metal2 ; + ANTENNAMAXAREACAR 4.394822 LAYER Metal2 ; + PORT + LAYER Metal2 ; + RECT 350.675 0 350.935 0.26 ; + END + END B_BIST_BM[13] + PIN B_BIST_BM[2] + DIRECTION INPUT ; + USE SIGNAL ; + ANTENNAPARTIALMETALAREA 0.7007 LAYER Metal2 ; + ANTENNAMODEL OXIDE1 ; + ANTENNAGATEAREA 0.20085 LAYER Metal2 ; + ANTENNAMAXAREACAR 4.394822 LAYER Metal2 ; + PORT + LAYER Metal2 ; + RECT 51.675 0 51.935 0.26 ; + END + END B_BIST_BM[2] + PIN B_DOUT[13] + DIRECTION OUTPUT ; + USE SIGNAL ; + ANTENNAPARTIALMETALAREA 4.836 LAYER Metal2 ; + ANTENNADIFFAREA 0.988 LAYER Metal2 ; + PORT + LAYER Metal2 ; + RECT 364.8 0 365.06 0.26 ; + END + END B_DOUT[13] + PIN B_DOUT[2] + DIRECTION OUTPUT ; + USE SIGNAL ; + ANTENNAPARTIALMETALAREA 4.836 LAYER Metal2 ; + ANTENNADIFFAREA 0.988 LAYER Metal2 ; + PORT + LAYER Metal2 ; + RECT 37.55 0 37.81 0.26 ; + END + END B_DOUT[2] + PIN A_DIN[14] + DIRECTION INPUT ; + USE SIGNAL ; + ANTENNAPARTIALMETALAREA 3.9091 LAYER Metal2 ; + ANTENNAMODEL OXIDE1 ; + ANTENNAGATEAREA 0.20085 LAYER Metal2 ; + ANTENNAMAXAREACAR 20.368932 LAYER Metal2 ; + PORT + LAYER Metal2 ; + RECT 372.79 0 373.05 0.26 ; + END + END A_DIN[14] + PIN A_DIN[1] + DIRECTION INPUT ; + USE SIGNAL ; + ANTENNAPARTIALMETALAREA 3.9091 LAYER Metal2 ; + ANTENNAMODEL OXIDE1 ; + ANTENNAGATEAREA 0.20085 LAYER Metal2 ; + ANTENNAMAXAREACAR 20.368932 LAYER Metal2 ; + PORT + LAYER Metal2 ; + RECT 29.56 0 29.82 0.26 ; + END + END A_DIN[1] + PIN A_BIST_DIN[14] + DIRECTION INPUT ; + USE SIGNAL ; + ANTENNAPARTIALMETALAREA 4.136375 LAYER Metal2 ; + ANTENNAMODEL OXIDE1 ; + ANTENNAGATEAREA 0.20085 LAYER Metal2 ; + ANTENNAMAXAREACAR 21.874907 LAYER Metal2 ; + PORT + LAYER Metal2 ; + RECT 373.3 0 373.56 0.26 ; + END + END A_BIST_DIN[14] + PIN A_BIST_DIN[1] + DIRECTION INPUT ; + USE SIGNAL ; + ANTENNAPARTIALMETALAREA 4.136375 LAYER Metal2 ; + ANTENNAMODEL OXIDE1 ; + ANTENNAGATEAREA 0.20085 LAYER Metal2 ; + ANTENNAMAXAREACAR 21.874907 LAYER Metal2 ; + PORT + LAYER Metal2 ; + RECT 29.05 0 29.31 0.26 ; + END + END A_BIST_DIN[1] + PIN A_BM[14] + DIRECTION INPUT ; + USE SIGNAL ; + ANTENNAPARTIALMETALAREA 1.7264 LAYER Metal2 ; + ANTENNAMODEL OXIDE1 ; + ANTENNAGATEAREA 0.20085 LAYER Metal2 ; + ANTENNAMAXAREACAR 9.501618 LAYER Metal2 ; + PORT + LAYER Metal2 ; + RECT 381.46 0 381.72 0.26 ; + END + END A_BM[14] + PIN A_BM[1] + DIRECTION INPUT ; + USE SIGNAL ; + ANTENNAPARTIALMETALAREA 1.7264 LAYER Metal2 ; + ANTENNAMODEL OXIDE1 ; + ANTENNAGATEAREA 0.20085 LAYER Metal2 ; + ANTENNAMAXAREACAR 9.501618 LAYER Metal2 ; + PORT + LAYER Metal2 ; + RECT 20.89 0 21.15 0.26 ; + END + END A_BM[1] + PIN A_BIST_BM[14] + DIRECTION INPUT ; + USE SIGNAL ; + ANTENNAPARTIALMETALAREA 1.7602 LAYER Metal2 ; + ANTENNAMODEL OXIDE1 ; + ANTENNAGATEAREA 0.20085 LAYER Metal2 ; + ANTENNAMAXAREACAR 9.678367 LAYER Metal2 ; + PORT + LAYER Metal2 ; + RECT 380.085 0 380.345 0.26 ; + END + END A_BIST_BM[14] + PIN A_BIST_BM[1] + DIRECTION INPUT ; + USE SIGNAL ; + ANTENNAPARTIALMETALAREA 1.7602 LAYER Metal2 ; + ANTENNAMODEL OXIDE1 ; + ANTENNAGATEAREA 0.20085 LAYER Metal2 ; + ANTENNAMAXAREACAR 9.678367 LAYER Metal2 ; + PORT + LAYER Metal2 ; + RECT 22.265 0 22.525 0.26 ; + END + END A_BIST_BM[1] + PIN A_DOUT[14] + DIRECTION OUTPUT ; + USE SIGNAL ; + ANTENNAPARTIALMETALAREA 4.8256 LAYER Metal2 ; + ANTENNADIFFAREA 0.988 LAYER Metal2 ; + PORT + LAYER Metal2 ; + RECT 365.65 0 365.91 0.26 ; + END + END A_DOUT[14] + PIN A_DOUT[1] + DIRECTION OUTPUT ; + USE SIGNAL ; + ANTENNAPARTIALMETALAREA 4.8256 LAYER Metal2 ; + ANTENNADIFFAREA 0.988 LAYER Metal2 ; + PORT + LAYER Metal2 ; + RECT 36.7 0 36.96 0.26 ; + END + END A_DOUT[1] + PIN B_DIN[14] + DIRECTION INPUT ; + USE SIGNAL ; + ANTENNAPARTIALMETALAREA 2.925 LAYER Metal2 ; + ANTENNAMODEL OXIDE1 ; + ANTENNAGATEAREA 0.20085 LAYER Metal2 ; + ANTENNAMAXAREACAR 15.469256 LAYER Metal2 ; + PORT + LAYER Metal2 ; + RECT 375.34 0 375.6 0.26 ; + END + END B_DIN[14] + PIN B_DIN[1] + DIRECTION INPUT ; + USE SIGNAL ; + ANTENNAPARTIALMETALAREA 2.925 LAYER Metal2 ; + ANTENNAMODEL OXIDE1 ; + ANTENNAGATEAREA 0.20085 LAYER Metal2 ; + ANTENNAMAXAREACAR 15.469256 LAYER Metal2 ; + PORT + LAYER Metal2 ; + RECT 27.01 0 27.27 0.26 ; + END + END B_DIN[1] + PIN B_BIST_DIN[14] + DIRECTION INPUT ; + USE SIGNAL ; + ANTENNAPARTIALMETALAREA 2.9445 LAYER Metal2 ; + ANTENNAMODEL OXIDE1 ; + ANTENNAGATEAREA 0.20085 LAYER Metal2 ; + ANTENNAMAXAREACAR 15.929052 LAYER Metal2 ; + PORT + LAYER Metal2 ; + RECT 373.81 0 374.07 0.26 ; + END + END B_BIST_DIN[14] + PIN B_BIST_DIN[1] + DIRECTION INPUT ; + USE SIGNAL ; + ANTENNAPARTIALMETALAREA 2.9445 LAYER Metal2 ; + ANTENNAMODEL OXIDE1 ; + ANTENNAGATEAREA 0.20085 LAYER Metal2 ; + ANTENNAMAXAREACAR 15.929052 LAYER Metal2 ; + PORT + LAYER Metal2 ; + RECT 28.54 0 28.8 0.26 ; + END + END B_BIST_DIN[1] + PIN B_BM[14] + DIRECTION INPUT ; + USE SIGNAL ; + ANTENNAPARTIALMETALAREA 0.7007 LAYER Metal2 ; + ANTENNAMODEL OXIDE1 ; + ANTENNAGATEAREA 0.20085 LAYER Metal2 ; + ANTENNAMAXAREACAR 4.394822 LAYER Metal2 ; + PORT + LAYER Metal2 ; + RECT 366.825 0 367.085 0.26 ; + END + END B_BM[14] + PIN B_BM[1] + DIRECTION INPUT ; + USE SIGNAL ; + ANTENNAPARTIALMETALAREA 0.7007 LAYER Metal2 ; + ANTENNAMODEL OXIDE1 ; + ANTENNAGATEAREA 0.20085 LAYER Metal2 ; + ANTENNAMAXAREACAR 4.394822 LAYER Metal2 ; + PORT + LAYER Metal2 ; + RECT 35.525 0 35.785 0.26 ; + END + END B_BM[1] + PIN B_BIST_BM[14] + DIRECTION INPUT ; + USE SIGNAL ; + ANTENNAPARTIALMETALAREA 0.7007 LAYER Metal2 ; + ANTENNAMODEL OXIDE1 ; + ANTENNAGATEAREA 0.20085 LAYER Metal2 ; + ANTENNAMAXAREACAR 4.394822 LAYER Metal2 ; + PORT + LAYER Metal2 ; + RECT 368.355 0 368.615 0.26 ; + END + END B_BIST_BM[14] + PIN B_BIST_BM[1] + DIRECTION INPUT ; + USE SIGNAL ; + ANTENNAPARTIALMETALAREA 0.7007 LAYER Metal2 ; + ANTENNAMODEL OXIDE1 ; + ANTENNAGATEAREA 0.20085 LAYER Metal2 ; + ANTENNAMAXAREACAR 4.394822 LAYER Metal2 ; + PORT + LAYER Metal2 ; + RECT 33.995 0 34.255 0.26 ; + END + END B_BIST_BM[1] + PIN B_DOUT[14] + DIRECTION OUTPUT ; + USE SIGNAL ; + ANTENNAPARTIALMETALAREA 4.836 LAYER Metal2 ; + ANTENNADIFFAREA 0.988 LAYER Metal2 ; + PORT + LAYER Metal2 ; + RECT 382.48 0 382.74 0.26 ; + END + END B_DOUT[14] + PIN B_DOUT[1] + DIRECTION OUTPUT ; + USE SIGNAL ; + ANTENNAPARTIALMETALAREA 4.836 LAYER Metal2 ; + ANTENNADIFFAREA 0.988 LAYER Metal2 ; + PORT + LAYER Metal2 ; + RECT 19.87 0 20.13 0.26 ; + END + END B_DOUT[1] + PIN A_DIN[15] + DIRECTION INPUT ; + USE SIGNAL ; + ANTENNAPARTIALMETALAREA 3.9091 LAYER Metal2 ; + ANTENNAMODEL OXIDE1 ; + ANTENNAGATEAREA 0.20085 LAYER Metal2 ; + ANTENNAMAXAREACAR 20.368932 LAYER Metal2 ; + PORT + LAYER Metal2 ; + RECT 390.47 0 390.73 0.26 ; + END + END A_DIN[15] + PIN A_DIN[0] + DIRECTION INPUT ; + USE SIGNAL ; + ANTENNAPARTIALMETALAREA 3.9091 LAYER Metal2 ; + ANTENNAMODEL OXIDE1 ; + ANTENNAGATEAREA 0.20085 LAYER Metal2 ; + ANTENNAMAXAREACAR 20.368932 LAYER Metal2 ; + PORT + LAYER Metal2 ; + RECT 11.88 0 12.14 0.26 ; + END + END A_DIN[0] + PIN A_BIST_DIN[15] + DIRECTION INPUT ; + USE SIGNAL ; + ANTENNAPARTIALMETALAREA 4.136375 LAYER Metal2 ; + ANTENNAMODEL OXIDE1 ; + ANTENNAGATEAREA 0.20085 LAYER Metal2 ; + ANTENNAMAXAREACAR 21.874907 LAYER Metal2 ; + PORT + LAYER Metal2 ; + RECT 390.98 0 391.24 0.26 ; + END + END A_BIST_DIN[15] + PIN A_BIST_DIN[0] + DIRECTION INPUT ; + USE SIGNAL ; + ANTENNAPARTIALMETALAREA 4.136375 LAYER Metal2 ; + ANTENNAMODEL OXIDE1 ; + ANTENNAGATEAREA 0.20085 LAYER Metal2 ; + ANTENNAMAXAREACAR 21.874907 LAYER Metal2 ; + PORT + LAYER Metal2 ; + RECT 11.37 0 11.63 0.26 ; + END + END A_BIST_DIN[0] + PIN A_BM[15] + DIRECTION INPUT ; + USE SIGNAL ; + ANTENNAPARTIALMETALAREA 1.7264 LAYER Metal2 ; + ANTENNAMODEL OXIDE1 ; + ANTENNAGATEAREA 0.20085 LAYER Metal2 ; + ANTENNAMAXAREACAR 9.501618 LAYER Metal2 ; + PORT + LAYER Metal2 ; + RECT 399.14 0 399.4 0.26 ; + END + END A_BM[15] + PIN A_BM[0] + DIRECTION INPUT ; + USE SIGNAL ; + ANTENNAPARTIALMETALAREA 1.7264 LAYER Metal2 ; + ANTENNAMODEL OXIDE1 ; + ANTENNAGATEAREA 0.20085 LAYER Metal2 ; + ANTENNAMAXAREACAR 9.501618 LAYER Metal2 ; + PORT + LAYER Metal2 ; + RECT 3.21 0 3.47 0.26 ; + END + END A_BM[0] + PIN A_BIST_BM[15] + DIRECTION INPUT ; + USE SIGNAL ; + ANTENNAPARTIALMETALAREA 1.7602 LAYER Metal2 ; + ANTENNAMODEL OXIDE1 ; + ANTENNAGATEAREA 0.20085 LAYER Metal2 ; + ANTENNAMAXAREACAR 9.678367 LAYER Metal2 ; + PORT + LAYER Metal2 ; + RECT 397.765 0 398.025 0.26 ; + END + END A_BIST_BM[15] + PIN A_BIST_BM[0] + DIRECTION INPUT ; + USE SIGNAL ; + ANTENNAPARTIALMETALAREA 1.7602 LAYER Metal2 ; + ANTENNAMODEL OXIDE1 ; + ANTENNAGATEAREA 0.20085 LAYER Metal2 ; + ANTENNAMAXAREACAR 9.678367 LAYER Metal2 ; + PORT + LAYER Metal2 ; + RECT 4.585 0 4.845 0.26 ; + END + END A_BIST_BM[0] + PIN A_DOUT[15] + DIRECTION OUTPUT ; + USE SIGNAL ; + ANTENNAPARTIALMETALAREA 4.8256 LAYER Metal2 ; + ANTENNADIFFAREA 0.988 LAYER Metal2 ; + PORT + LAYER Metal2 ; + RECT 383.33 0 383.59 0.26 ; + END + END A_DOUT[15] + PIN A_DOUT[0] + DIRECTION OUTPUT ; + USE SIGNAL ; + ANTENNAPARTIALMETALAREA 4.8256 LAYER Metal2 ; + ANTENNADIFFAREA 0.988 LAYER Metal2 ; + PORT + LAYER Metal2 ; + RECT 19.02 0 19.28 0.26 ; + END + END A_DOUT[0] + PIN B_DIN[15] + DIRECTION INPUT ; + USE SIGNAL ; + ANTENNAPARTIALMETALAREA 2.925 LAYER Metal2 ; + ANTENNAMODEL OXIDE1 ; + ANTENNAGATEAREA 0.20085 LAYER Metal2 ; + ANTENNAMAXAREACAR 15.469256 LAYER Metal2 ; + PORT + LAYER Metal2 ; + RECT 393.02 0 393.28 0.26 ; + END + END B_DIN[15] + PIN B_DIN[0] + DIRECTION INPUT ; + USE SIGNAL ; + ANTENNAPARTIALMETALAREA 2.925 LAYER Metal2 ; + ANTENNAMODEL OXIDE1 ; + ANTENNAGATEAREA 0.20085 LAYER Metal2 ; + ANTENNAMAXAREACAR 15.469256 LAYER Metal2 ; + PORT + LAYER Metal2 ; + RECT 9.33 0 9.59 0.26 ; + END + END B_DIN[0] + PIN B_BIST_DIN[15] + DIRECTION INPUT ; + USE SIGNAL ; + ANTENNAPARTIALMETALAREA 2.9445 LAYER Metal2 ; + ANTENNAMODEL OXIDE1 ; + ANTENNAGATEAREA 0.20085 LAYER Metal2 ; + ANTENNAMAXAREACAR 15.929052 LAYER Metal2 ; + PORT + LAYER Metal2 ; + RECT 391.49 0 391.75 0.26 ; + END + END B_BIST_DIN[15] + PIN B_BIST_DIN[0] + DIRECTION INPUT ; + USE SIGNAL ; + ANTENNAPARTIALMETALAREA 2.9445 LAYER Metal2 ; + ANTENNAMODEL OXIDE1 ; + ANTENNAGATEAREA 0.20085 LAYER Metal2 ; + ANTENNAMAXAREACAR 15.929052 LAYER Metal2 ; + PORT + LAYER Metal2 ; + RECT 10.86 0 11.12 0.26 ; + END + END B_BIST_DIN[0] + PIN B_BM[15] + DIRECTION INPUT ; + USE SIGNAL ; + ANTENNAPARTIALMETALAREA 0.7007 LAYER Metal2 ; + ANTENNAMODEL OXIDE1 ; + ANTENNAGATEAREA 0.20085 LAYER Metal2 ; + ANTENNAMAXAREACAR 4.394822 LAYER Metal2 ; + PORT + LAYER Metal2 ; + RECT 384.505 0 384.765 0.26 ; + END + END B_BM[15] + PIN B_BM[0] + DIRECTION INPUT ; + USE SIGNAL ; + ANTENNAPARTIALMETALAREA 0.7007 LAYER Metal2 ; + ANTENNAMODEL OXIDE1 ; + ANTENNAGATEAREA 0.20085 LAYER Metal2 ; + ANTENNAMAXAREACAR 4.394822 LAYER Metal2 ; + PORT + LAYER Metal2 ; + RECT 17.845 0 18.105 0.26 ; + END + END B_BM[0] + PIN B_BIST_BM[15] + DIRECTION INPUT ; + USE SIGNAL ; + ANTENNAPARTIALMETALAREA 0.7007 LAYER Metal2 ; + ANTENNAMODEL OXIDE1 ; + ANTENNAGATEAREA 0.20085 LAYER Metal2 ; + ANTENNAMAXAREACAR 4.394822 LAYER Metal2 ; + PORT + LAYER Metal2 ; + RECT 386.035 0 386.295 0.26 ; + END + END B_BIST_BM[15] + PIN B_BIST_BM[0] + DIRECTION INPUT ; + USE SIGNAL ; + ANTENNAPARTIALMETALAREA 0.7007 LAYER Metal2 ; + ANTENNAMODEL OXIDE1 ; + ANTENNAGATEAREA 0.20085 LAYER Metal2 ; + ANTENNAMAXAREACAR 4.394822 LAYER Metal2 ; + PORT + LAYER Metal2 ; + RECT 16.315 0 16.575 0.26 ; + END + END B_BIST_BM[0] + PIN B_DOUT[15] + DIRECTION OUTPUT ; + USE SIGNAL ; + ANTENNAPARTIALMETALAREA 4.836 LAYER Metal2 ; + ANTENNADIFFAREA 0.988 LAYER Metal2 ; + PORT + LAYER Metal2 ; + RECT 400.16 0 400.42 0.26 ; + END + END B_DOUT[15] + PIN B_DOUT[0] + DIRECTION OUTPUT ; + USE SIGNAL ; + ANTENNAPARTIALMETALAREA 4.836 LAYER Metal2 ; + ANTENNADIFFAREA 0.988 LAYER Metal2 ; + PORT + LAYER Metal2 ; + RECT 2.19 0 2.45 0.26 ; + END + END B_DOUT[0] + PIN A_ADDR[0] + DIRECTION INPUT ; + USE SIGNAL ; + ANTENNAPARTIALMETALAREA 8.7685 LAYER Metal2 ; + ANTENNAMODEL OXIDE1 ; + ANTENNAGATEAREA 0.20085 LAYER Metal2 ; + ANTENNAMAXAREACAR 44.563107 LAYER Metal2 ; + PORT + LAYER Metal2 ; + RECT 217.395 0 217.655 0.26 ; + END + END A_ADDR[0] + PIN A_BIST_ADDR[0] + DIRECTION INPUT ; + USE SIGNAL ; + ANTENNAPARTIALMETALAREA 9.8293 LAYER Metal2 ; + ANTENNAMODEL OXIDE1 ; + ANTENNAGATEAREA 0.20085 LAYER Metal2 ; + ANTENNAMAXAREACAR 49.84466 LAYER Metal2 ; + PORT + LAYER Metal2 ; + RECT 223.005 0 223.265 0.26 ; + END + END A_BIST_ADDR[0] + PIN B_ADDR[0] + DIRECTION INPUT ; + USE SIGNAL ; + ANTENNAPARTIALMETALAREA 8.7685 LAYER Metal2 ; + ANTENNAMODEL OXIDE1 ; + ANTENNAGATEAREA 0.20085 LAYER Metal2 ; + ANTENNAMAXAREACAR 44.563107 LAYER Metal2 ; + PORT + LAYER Metal2 ; + RECT 184.955 0 185.215 0.26 ; + END + END B_ADDR[0] + PIN B_BIST_ADDR[0] + DIRECTION INPUT ; + USE SIGNAL ; + ANTENNAPARTIALMETALAREA 9.8293 LAYER Metal2 ; + ANTENNAMODEL OXIDE1 ; + ANTENNAGATEAREA 0.20085 LAYER Metal2 ; + ANTENNAMAXAREACAR 49.84466 LAYER Metal2 ; + PORT + LAYER Metal2 ; + RECT 179.345 0 179.605 0.26 ; + END + END B_BIST_ADDR[0] + PIN A_ADDR[1] + DIRECTION INPUT ; + USE SIGNAL ; + ANTENNAPARTIALMETALAREA 11.0851 LAYER Metal2 ; + ANTENNAMODEL OXIDE1 ; + ANTENNAGATEAREA 0.20085 LAYER Metal2 ; + ANTENNAMAXAREACAR 56.097087 LAYER Metal2 ; + PORT + LAYER Metal2 ; + RECT 217.905 0 218.165 0.26 ; + END + END A_ADDR[1] + PIN A_BIST_ADDR[1] + DIRECTION INPUT ; + USE SIGNAL ; + ANTENNAPARTIALMETALAREA 12.1459 LAYER Metal2 ; + ANTENNAMODEL OXIDE1 ; + ANTENNAGATEAREA 0.20085 LAYER Metal2 ; + ANTENNAMAXAREACAR 61.378641 LAYER Metal2 ; + PORT + LAYER Metal2 ; + RECT 223.515 0 223.775 0.26 ; + END + END A_BIST_ADDR[1] + PIN B_ADDR[1] + DIRECTION INPUT ; + USE SIGNAL ; + ANTENNAPARTIALMETALAREA 11.0851 LAYER Metal2 ; + ANTENNAMODEL OXIDE1 ; + ANTENNAGATEAREA 0.20085 LAYER Metal2 ; + ANTENNAMAXAREACAR 56.097087 LAYER Metal2 ; + PORT + LAYER Metal2 ; + RECT 184.445 0 184.705 0.26 ; + END + END B_ADDR[1] + PIN B_BIST_ADDR[1] + DIRECTION INPUT ; + USE SIGNAL ; + ANTENNAPARTIALMETALAREA 12.1459 LAYER Metal2 ; + ANTENNAMODEL OXIDE1 ; + ANTENNAGATEAREA 0.20085 LAYER Metal2 ; + ANTENNAMAXAREACAR 61.378641 LAYER Metal2 ; + PORT + LAYER Metal2 ; + RECT 178.835 0 179.095 0.26 ; + END + END B_BIST_ADDR[1] + PIN A_ADDR[2] + DIRECTION INPUT ; + USE SIGNAL ; + ANTENNAPARTIALMETALAREA 13.0819 LAYER Metal2 ; + ANTENNAPARTIALMETALAREA 1.5246 LAYER Metal3 ; + ANTENNAPARTIALCUTAREA 0.0722 LAYER Via2 ; + ANTENNAMODEL OXIDE1 ; + ANTENNAGATEAREA 0.20085 LAYER Metal3 ; + ANTENNAMAXAREACAR 9.415982 LAYER Metal3 ; + PORT + LAYER Metal2 ; + RECT 226.575 0 226.835 0.26 ; + END + END A_ADDR[2] + PIN A_BIST_ADDR[2] + DIRECTION INPUT ; + USE SIGNAL ; + ANTENNAPARTIALMETALAREA 13.0819 LAYER Metal2 ; + ANTENNAPARTIALMETALAREA 1.0962 LAYER Metal3 ; + ANTENNAPARTIALCUTAREA 0.0722 LAYER Via2 ; + ANTENNAMODEL OXIDE1 ; + ANTENNAGATEAREA 0.20085 LAYER Metal3 ; + ANTENNAMAXAREACAR 7.813791 LAYER Metal3 ; + PORT + LAYER Metal2 ; + RECT 227.085 0 227.345 0.26 ; + END + END A_BIST_ADDR[2] + PIN B_ADDR[2] + DIRECTION INPUT ; + USE SIGNAL ; + ANTENNAPARTIALMETALAREA 13.0819 LAYER Metal2 ; + ANTENNAPARTIALMETALAREA 1.5246 LAYER Metal3 ; + ANTENNAPARTIALCUTAREA 0.0722 LAYER Via2 ; + ANTENNAMODEL OXIDE1 ; + ANTENNAGATEAREA 0.20085 LAYER Metal3 ; + ANTENNAMAXAREACAR 9.415982 LAYER Metal3 ; + PORT + LAYER Metal2 ; + RECT 175.775 0 176.035 0.26 ; + END + END B_ADDR[2] + PIN B_BIST_ADDR[2] + DIRECTION INPUT ; + USE SIGNAL ; + ANTENNAPARTIALMETALAREA 13.0819 LAYER Metal2 ; + ANTENNAPARTIALMETALAREA 1.0962 LAYER Metal3 ; + ANTENNAPARTIALCUTAREA 0.0722 LAYER Via2 ; + ANTENNAMODEL OXIDE1 ; + ANTENNAGATEAREA 0.20085 LAYER Metal3 ; + ANTENNAMAXAREACAR 7.813791 LAYER Metal3 ; + PORT + LAYER Metal2 ; + RECT 175.265 0 175.525 0.26 ; + END + END B_BIST_ADDR[2] + PIN A_ADDR[3] + DIRECTION INPUT ; + USE SIGNAL ; + ANTENNAPARTIALMETALAREA 13.0819 LAYER Metal2 ; + ANTENNAPARTIALMETALAREA 3.9459 LAYER Metal3 ; + ANTENNAPARTIALCUTAREA 0.0722 LAYER Via2 ; + ANTENNAMODEL OXIDE1 ; + ANTENNAGATEAREA 0.20085 LAYER Metal3 ; + ANTENNAMAXAREACAR 21.471247 LAYER Metal3 ; + PORT + LAYER Metal2 ; + RECT 225.555 0 225.815 0.26 ; + END + END A_ADDR[3] + PIN A_BIST_ADDR[3] + DIRECTION INPUT ; + USE SIGNAL ; + ANTENNAPARTIALMETALAREA 13.0819 LAYER Metal2 ; + ANTENNAPARTIALMETALAREA 3.7317 LAYER Metal3 ; + ANTENNAPARTIALCUTAREA 0.0722 LAYER Via2 ; + ANTENNAMODEL OXIDE1 ; + ANTENNAGATEAREA 0.20085 LAYER Metal3 ; + ANTENNAMAXAREACAR 20.935524 LAYER Metal3 ; + PORT + LAYER Metal2 ; + RECT 226.065 0 226.325 0.26 ; + END + END A_BIST_ADDR[3] + PIN B_ADDR[3] + DIRECTION INPUT ; + USE SIGNAL ; + ANTENNAPARTIALMETALAREA 13.0819 LAYER Metal2 ; + ANTENNAPARTIALMETALAREA 3.9459 LAYER Metal3 ; + ANTENNAPARTIALCUTAREA 0.0722 LAYER Via2 ; + ANTENNAMODEL OXIDE1 ; + ANTENNAGATEAREA 0.20085 LAYER Metal3 ; + ANTENNAMAXAREACAR 21.471247 LAYER Metal3 ; + PORT + LAYER Metal2 ; + RECT 176.795 0 177.055 0.26 ; + END + END B_ADDR[3] + PIN B_BIST_ADDR[3] + DIRECTION INPUT ; + USE SIGNAL ; + ANTENNAPARTIALMETALAREA 13.0819 LAYER Metal2 ; + ANTENNAPARTIALMETALAREA 3.7317 LAYER Metal3 ; + ANTENNAPARTIALCUTAREA 0.0722 LAYER Via2 ; + ANTENNAMODEL OXIDE1 ; + ANTENNAGATEAREA 0.20085 LAYER Metal3 ; + ANTENNAMAXAREACAR 20.935524 LAYER Metal3 ; + PORT + LAYER Metal2 ; + RECT 176.285 0 176.545 0.26 ; + END + END B_BIST_ADDR[3] + PIN A_ADDR[4] + DIRECTION INPUT ; + USE SIGNAL ; + ANTENNAPARTIALMETALAREA 14.7329 LAYER Metal2 ; + ANTENNAMODEL OXIDE1 ; + ANTENNAGATEAREA 0.20085 LAYER Metal2 ; + ANTENNAMAXAREACAR 74.2589 LAYER Metal2 ; + PORT + LAYER Metal2 ; + RECT 206.175 0 206.435 0.26 ; + END + END A_ADDR[4] + PIN A_BIST_ADDR[4] + DIRECTION INPUT ; + USE SIGNAL ; + ANTENNAPARTIALMETALAREA 14.4677 LAYER Metal2 ; + ANTENNAMODEL OXIDE1 ; + ANTENNAGATEAREA 0.20085 LAYER Metal2 ; + ANTENNAMAXAREACAR 72.938511 LAYER Metal2 ; + PORT + LAYER Metal2 ; + RECT 206.685 0 206.945 0.26 ; + END + END A_BIST_ADDR[4] + PIN B_ADDR[4] + DIRECTION INPUT ; + USE SIGNAL ; + ANTENNAPARTIALMETALAREA 14.7329 LAYER Metal2 ; + ANTENNAMODEL OXIDE1 ; + ANTENNAGATEAREA 0.20085 LAYER Metal2 ; + ANTENNAMAXAREACAR 74.2589 LAYER Metal2 ; + PORT + LAYER Metal2 ; + RECT 196.175 0 196.435 0.26 ; + END + END B_ADDR[4] + PIN B_BIST_ADDR[4] + DIRECTION INPUT ; + USE SIGNAL ; + ANTENNAPARTIALMETALAREA 14.4677 LAYER Metal2 ; + ANTENNAMODEL OXIDE1 ; + ANTENNAGATEAREA 0.20085 LAYER Metal2 ; + ANTENNAMAXAREACAR 72.938511 LAYER Metal2 ; + PORT + LAYER Metal2 ; + RECT 195.665 0 195.925 0.26 ; + END + END B_BIST_ADDR[4] + PIN A_ADDR[5] + DIRECTION INPUT ; + USE SIGNAL ; + ANTENNAPARTIALMETALAREA 13.2691 LAYER Metal2 ; + ANTENNAMODEL OXIDE1 ; + ANTENNAGATEAREA 0.20085 LAYER Metal2 ; + ANTENNAMAXAREACAR 66.970874 LAYER Metal2 ; + PORT + LAYER Metal2 ; + RECT 205.155 0 205.415 0.26 ; + END + END A_ADDR[5] + PIN A_BIST_ADDR[5] + DIRECTION INPUT ; + USE SIGNAL ; + ANTENNAPARTIALMETALAREA 12.9937 LAYER Metal2 ; + ANTENNAMODEL OXIDE1 ; + ANTENNAGATEAREA 0.20085 LAYER Metal2 ; + ANTENNAMAXAREACAR 65.599701 LAYER Metal2 ; + PORT + LAYER Metal2 ; + RECT 205.665 0 205.925 0.26 ; + END + END A_BIST_ADDR[5] + PIN B_ADDR[5] + DIRECTION INPUT ; + USE SIGNAL ; + ANTENNAPARTIALMETALAREA 13.2691 LAYER Metal2 ; + ANTENNAMODEL OXIDE1 ; + ANTENNAGATEAREA 0.20085 LAYER Metal2 ; + ANTENNAMAXAREACAR 66.970874 LAYER Metal2 ; + PORT + LAYER Metal2 ; + RECT 197.195 0 197.455 0.26 ; + END + END B_ADDR[5] + PIN B_BIST_ADDR[5] + DIRECTION INPUT ; + USE SIGNAL ; + ANTENNAPARTIALMETALAREA 12.9937 LAYER Metal2 ; + ANTENNAMODEL OXIDE1 ; + ANTENNAGATEAREA 0.20085 LAYER Metal2 ; + ANTENNAMAXAREACAR 65.599701 LAYER Metal2 ; + PORT + LAYER Metal2 ; + RECT 196.685 0 196.945 0.26 ; + END + END B_BIST_ADDR[5] + PIN A_ADDR[6] + DIRECTION INPUT ; + USE SIGNAL ; + ANTENNAPARTIALMETALAREA 14.3819 LAYER Metal2 ; + ANTENNAMODEL OXIDE1 ; + ANTENNAGATEAREA 0.20085 LAYER Metal2 ; + ANTENNAMAXAREACAR 72.511327 LAYER Metal2 ; + PORT + LAYER Metal2 ; + RECT 229.125 0 229.385 0.26 ; + END + END A_ADDR[6] + PIN A_BIST_ADDR[6] + DIRECTION INPUT ; + USE SIGNAL ; + ANTENNAPARTIALMETALAREA 14.1167 LAYER Metal2 ; + ANTENNAMODEL OXIDE1 ; + ANTENNAGATEAREA 0.20085 LAYER Metal2 ; + ANTENNAMAXAREACAR 71.190939 LAYER Metal2 ; + PORT + LAYER Metal2 ; + RECT 228.615 0 228.875 0.26 ; + END + END A_BIST_ADDR[6] + PIN B_ADDR[6] + DIRECTION INPUT ; + USE SIGNAL ; + ANTENNAPARTIALMETALAREA 14.3819 LAYER Metal2 ; + ANTENNAMODEL OXIDE1 ; + ANTENNAGATEAREA 0.20085 LAYER Metal2 ; + ANTENNAMAXAREACAR 72.511327 LAYER Metal2 ; + PORT + LAYER Metal2 ; + RECT 173.225 0 173.485 0.26 ; + END + END B_ADDR[6] + PIN B_BIST_ADDR[6] + DIRECTION INPUT ; + USE SIGNAL ; + ANTENNAPARTIALMETALAREA 14.1167 LAYER Metal2 ; + ANTENNAMODEL OXIDE1 ; + ANTENNAGATEAREA 0.20085 LAYER Metal2 ; + ANTENNAMAXAREACAR 71.190939 LAYER Metal2 ; + PORT + LAYER Metal2 ; + RECT 173.735 0 173.995 0.26 ; + END + END B_BIST_ADDR[6] + PIN A_ADDR[7] + DIRECTION INPUT ; + USE SIGNAL ; + ANTENNAPARTIALMETALAREA 16.3761 LAYER Metal2 ; + ANTENNAMODEL OXIDE1 ; + ANTENNAGATEAREA 0.20085 LAYER Metal2 ; + ANTENNAMAXAREACAR 82.440129 LAYER Metal2 ; + PORT + LAYER Metal2 ; + RECT 228.105 0 228.365 0.26 ; + END + END A_ADDR[7] + PIN A_BIST_ADDR[7] + DIRECTION INPUT ; + USE SIGNAL ; + ANTENNAPARTIALMETALAREA 16.1109 LAYER Metal2 ; + ANTENNAMODEL OXIDE1 ; + ANTENNAGATEAREA 0.20085 LAYER Metal2 ; + ANTENNAMAXAREACAR 81.119741 LAYER Metal2 ; + PORT + LAYER Metal2 ; + RECT 227.595 0 227.855 0.26 ; + END + END A_BIST_ADDR[7] + PIN B_ADDR[7] + DIRECTION INPUT ; + USE SIGNAL ; + ANTENNAPARTIALMETALAREA 16.3761 LAYER Metal2 ; + ANTENNAMODEL OXIDE1 ; + ANTENNAGATEAREA 0.20085 LAYER Metal2 ; + ANTENNAMAXAREACAR 82.440129 LAYER Metal2 ; + PORT + LAYER Metal2 ; + RECT 174.245 0 174.505 0.26 ; + END + END B_ADDR[7] + PIN B_BIST_ADDR[7] + DIRECTION INPUT ; + USE SIGNAL ; + ANTENNAPARTIALMETALAREA 16.1109 LAYER Metal2 ; + ANTENNAMODEL OXIDE1 ; + ANTENNAGATEAREA 0.20085 LAYER Metal2 ; + ANTENNAMAXAREACAR 81.119741 LAYER Metal2 ; + PORT + LAYER Metal2 ; + RECT 174.755 0 175.015 0.26 ; + END + END B_BIST_ADDR[7] + PIN A_ADDR[8] + DIRECTION INPUT ; + USE SIGNAL ; + ANTENNAPARTIALMETALAREA 14.4422 LAYER Metal2 ; + ANTENNAMODEL OXIDE1 ; + ANTENNAGATEAREA 0.20085 LAYER Metal2 ; + ANTENNAMAXAREACAR 72.811551 LAYER Metal2 ; + PORT + LAYER Metal2 ; + RECT 231.675 0 231.935 0.26 ; + END + END A_ADDR[8] + PIN A_BIST_ADDR[8] + DIRECTION INPUT ; + USE SIGNAL ; + ANTENNAPARTIALMETALAREA 14.1872 LAYER Metal2 ; + ANTENNAMODEL OXIDE1 ; + ANTENNAGATEAREA 0.20085 LAYER Metal2 ; + ANTENNAMAXAREACAR 71.541947 LAYER Metal2 ; + PORT + LAYER Metal2 ; + RECT 232.185 0 232.445 0.26 ; + END + END A_BIST_ADDR[8] + PIN B_ADDR[8] + DIRECTION INPUT ; + USE SIGNAL ; + ANTENNAPARTIALMETALAREA 14.4422 LAYER Metal2 ; + ANTENNAMODEL OXIDE1 ; + ANTENNAGATEAREA 0.20085 LAYER Metal2 ; + ANTENNAMAXAREACAR 72.811551 LAYER Metal2 ; + PORT + LAYER Metal2 ; + RECT 170.675 0 170.935 0.26 ; + END + END B_ADDR[8] + PIN B_BIST_ADDR[8] + DIRECTION INPUT ; + USE SIGNAL ; + ANTENNAPARTIALMETALAREA 14.1872 LAYER Metal2 ; + ANTENNAMODEL OXIDE1 ; + ANTENNAGATEAREA 0.20085 LAYER Metal2 ; + ANTENNAMAXAREACAR 71.541947 LAYER Metal2 ; + PORT + LAYER Metal2 ; + RECT 170.165 0 170.425 0.26 ; + END + END B_BIST_ADDR[8] + PIN A_CLK + DIRECTION INPUT ; + USE SIGNAL ; + ANTENNAPARTIALMETALAREA 4.0547 LAYER Metal2 ; + ANTENNAMODEL OXIDE1 ; + ANTENNAGATEAREA 0.20085 LAYER Metal2 ; + ANTENNAMAXAREACAR 21.093851 LAYER Metal2 ; + PORT + LAYER Metal2 ; + RECT 215.865 0 216.125 0.26 ; + END + END A_CLK + PIN A_REN + DIRECTION INPUT ; + USE SIGNAL ; + ANTENNAPARTIALMETALAREA 3.98465 LAYER Metal2 ; + ANTENNAMODEL OXIDE1 ; + ANTENNAGATEAREA 0.20085 LAYER Metal2 ; + ANTENNAMAXAREACAR 20.745083 LAYER Metal2 ; + PORT + LAYER Metal2 ; + RECT 219.435 0 219.695 0.26 ; + END + END A_REN + PIN A_WEN + DIRECTION INPUT ; + USE SIGNAL ; + ANTENNAPARTIALMETALAREA 2.8847 LAYER Metal2 ; + ANTENNAMODEL OXIDE1 ; + ANTENNAGATEAREA 0.20085 LAYER Metal2 ; + ANTENNAMAXAREACAR 15.268608 LAYER Metal2 ; + PORT + LAYER Metal2 ; + RECT 218.925 0 219.185 0.26 ; + END + END A_WEN + PIN A_MEN + DIRECTION INPUT ; + USE SIGNAL ; + ANTENNAPARTIALMETALAREA 3.0247 LAYER Metal2 ; + ANTENNAMODEL OXIDE1 ; + ANTENNAGATEAREA 0.20085 LAYER Metal2 ; + ANTENNAMAXAREACAR 15.965646 LAYER Metal2 ; + PORT + LAYER Metal2 ; + RECT 216.375 0 216.635 0.26 ; + END + END A_MEN + PIN A_DLY + DIRECTION INPUT ; + USE SIGNAL ; + ANTENNAPARTIALMETALAREA 7.7792 LAYER Metal2 ; + ANTENNAMODEL OXIDE1 ; + ANTENNAGATEAREA 0.3367 LAYER Metal2 ; + ANTENNAMAXAREACAR 23.644788 LAYER Metal2 ; + PORT + LAYER Metal2 ; + RECT 236.775 0 237.035 0.26 ; + END + END A_DLY + PIN B_CLK + DIRECTION INPUT ; + USE SIGNAL ; + ANTENNAPARTIALMETALAREA 4.0547 LAYER Metal2 ; + ANTENNAMODEL OXIDE1 ; + ANTENNAGATEAREA 0.20085 LAYER Metal2 ; + ANTENNAMAXAREACAR 21.093851 LAYER Metal2 ; + PORT + LAYER Metal2 ; + RECT 186.485 0 186.745 0.26 ; + END + END B_CLK + PIN B_REN + DIRECTION INPUT ; + USE SIGNAL ; + ANTENNAPARTIALMETALAREA 3.98465 LAYER Metal2 ; + ANTENNAMODEL OXIDE1 ; + ANTENNAGATEAREA 0.20085 LAYER Metal2 ; + ANTENNAMAXAREACAR 20.745083 LAYER Metal2 ; + PORT + LAYER Metal2 ; + RECT 182.915 0 183.175 0.26 ; + END + END B_REN + PIN B_WEN + DIRECTION INPUT ; + USE SIGNAL ; + ANTENNAPARTIALMETALAREA 2.8847 LAYER Metal2 ; + ANTENNAMODEL OXIDE1 ; + ANTENNAGATEAREA 0.20085 LAYER Metal2 ; + ANTENNAMAXAREACAR 15.268608 LAYER Metal2 ; + PORT + LAYER Metal2 ; + RECT 183.425 0 183.685 0.26 ; + END + END B_WEN + PIN B_MEN + DIRECTION INPUT ; + USE SIGNAL ; + ANTENNAPARTIALMETALAREA 3.0247 LAYER Metal2 ; + ANTENNAMODEL OXIDE1 ; + ANTENNAGATEAREA 0.20085 LAYER Metal2 ; + ANTENNAMAXAREACAR 15.965646 LAYER Metal2 ; + PORT + LAYER Metal2 ; + RECT 185.975 0 186.235 0.26 ; + END + END B_MEN + PIN B_DLY + DIRECTION INPUT ; + USE SIGNAL ; + ANTENNAPARTIALMETALAREA 7.7792 LAYER Metal2 ; + ANTENNAMODEL OXIDE1 ; + ANTENNAGATEAREA 0.3367 LAYER Metal2 ; + ANTENNAMAXAREACAR 23.644788 LAYER Metal2 ; + PORT + LAYER Metal2 ; + RECT 165.575 0 165.835 0.26 ; + END + END B_DLY + PIN A_BIST_EN + DIRECTION INPUT ; + USE SIGNAL ; + ANTENNAPARTIALMETALAREA 4.0634 LAYER Metal2 ; + ANTENNAPARTIALMETALAREA 146.7701 LAYER Metal3 ; + ANTENNAPARTIALCUTAREA 0.0722 LAYER Via2 ; + ANTENNAMODEL OXIDE1 ; + ANTENNAGATEAREA 1.43 LAYER Metal2 ; + ANTENNAGATEAREA 16.0875 LAYER Metal3 ; + ANTENNAMAXAREACAR 3.266993 LAYER Metal2 ; + ANTENNAMAXAREACAR 20.294614 LAYER Metal3 ; + ANTENNAMAXCUTCAR 0.151469 LAYER Via2 ; + PORT + LAYER Metal2 ; + RECT 218.415 0 218.675 0.26 ; + END + END A_BIST_EN + PIN A_BIST_CLK + DIRECTION INPUT ; + USE SIGNAL ; + ANTENNAPARTIALMETALAREA 4.1639 LAYER Metal2 ; + ANTENNAMODEL OXIDE1 ; + ANTENNAGATEAREA 0.20085 LAYER Metal2 ; + ANTENNAMAXAREACAR 21.953448 LAYER Metal2 ; + PORT + LAYER Metal2 ; + RECT 214.335 0 214.595 0.26 ; + END + END A_BIST_CLK + PIN A_BIST_REN + DIRECTION INPUT ; + USE SIGNAL ; + ANTENNAPARTIALMETALAREA 4.1119 LAYER Metal2 ; + ANTENNAMODEL OXIDE1 ; + ANTENNAGATEAREA 0.20085 LAYER Metal2 ; + ANTENNAMAXAREACAR 21.694548 LAYER Metal2 ; + PORT + LAYER Metal2 ; + RECT 220.965 0 221.225 0.26 ; + END + END A_BIST_REN + PIN A_BIST_WEN + DIRECTION INPUT ; + USE SIGNAL ; + ANTENNAPARTIALMETALAREA 2.9051 LAYER Metal2 ; + ANTENNAMODEL OXIDE1 ; + ANTENNAGATEAREA 0.20085 LAYER Metal2 ; + ANTENNAMAXAREACAR 15.686084 LAYER Metal2 ; + PORT + LAYER Metal2 ; + RECT 220.455 0 220.715 0.26 ; + END + END A_BIST_WEN + PIN A_BIST_MEN + DIRECTION INPUT ; + USE SIGNAL ; + ANTENNAPARTIALMETALAREA 2.8977 LAYER Metal2 ; + ANTENNAMODEL OXIDE1 ; + ANTENNAGATEAREA 0.20085 LAYER Metal2 ; + ANTENNAMAXAREACAR 15.649241 LAYER Metal2 ; + PORT + LAYER Metal2 ; + RECT 214.845 0 215.105 0.26 ; + END + END A_BIST_MEN + PIN B_BIST_EN + DIRECTION INPUT ; + USE SIGNAL ; + ANTENNAPARTIALMETALAREA 3.9646 LAYER Metal2 ; + ANTENNAPARTIALMETALAREA 147.2093 LAYER Metal3 ; + ANTENNAPARTIALCUTAREA 0.0722 LAYER Via2 ; + ANTENNAMODEL OXIDE1 ; + ANTENNAGATEAREA 1.43 LAYER Metal2 ; + ANTENNAGATEAREA 16.0875 LAYER Metal3 ; + ANTENNAMAXAREACAR 3.197902 LAYER Metal2 ; + ANTENNAMAXAREACAR 20.321915 LAYER Metal3 ; + ANTENNAMAXCUTCAR 0.151469 LAYER Via2 ; + PORT + LAYER Metal2 ; + RECT 183.935 0 184.195 0.26 ; + END + END B_BIST_EN + PIN B_BIST_CLK + DIRECTION INPUT ; + USE SIGNAL ; + ANTENNAPARTIALMETALAREA 4.1639 LAYER Metal2 ; + ANTENNAMODEL OXIDE1 ; + ANTENNAGATEAREA 0.20085 LAYER Metal2 ; + ANTENNAMAXAREACAR 21.953448 LAYER Metal2 ; + PORT + LAYER Metal2 ; + RECT 188.015 0 188.275 0.26 ; + END + END B_BIST_CLK + PIN B_BIST_REN + DIRECTION INPUT ; + USE SIGNAL ; + ANTENNAPARTIALMETALAREA 4.1119 LAYER Metal2 ; + ANTENNAMODEL OXIDE1 ; + ANTENNAGATEAREA 0.20085 LAYER Metal2 ; + ANTENNAMAXAREACAR 21.694548 LAYER Metal2 ; + PORT + LAYER Metal2 ; + RECT 181.385 0 181.645 0.26 ; + END + END B_BIST_REN + PIN B_BIST_WEN + DIRECTION INPUT ; + USE SIGNAL ; + ANTENNAPARTIALMETALAREA 2.9051 LAYER Metal2 ; + ANTENNAMODEL OXIDE1 ; + ANTENNAGATEAREA 0.20085 LAYER Metal2 ; + ANTENNAMAXAREACAR 15.686084 LAYER Metal2 ; + PORT + LAYER Metal2 ; + RECT 181.895 0 182.155 0.26 ; + END + END B_BIST_WEN + PIN B_BIST_MEN + DIRECTION INPUT ; + USE SIGNAL ; + ANTENNAPARTIALMETALAREA 2.8977 LAYER Metal2 ; + ANTENNAMODEL OXIDE1 ; + ANTENNAGATEAREA 0.20085 LAYER Metal2 ; + ANTENNAMAXAREACAR 15.649241 LAYER Metal2 ; + PORT + LAYER Metal2 ; + RECT 187.505 0 187.765 0.26 ; + END + END B_BIST_MEN + OBS + LAYER Metal1 ; + RECT 0 0 402.61 219.77 ; + LAYER Metal2 ; + RECT 0.31 53.41 0.51 219.74 ; + RECT 1.135 219.01 1.335 219.74 ; + RECT 1.545 219.01 1.905 219.74 ; + RECT 2.115 219.01 2.315 219.74 ; + RECT 2.19 0.52 2.45 7.78 ; + RECT 2.7 0.3 2.96 5.235 ; + RECT 2.77 219.01 2.97 219.74 ; + RECT 3.21 0.52 3.47 5.57 ; + RECT 3.18 219.01 3.54 219.74 ; + RECT 3.835 219.01 4.035 219.74 ; + RECT 4.33 219.01 4.69 219.74 ; + RECT 4.585 0.52 4.845 6.28 ; + RECT 4.9 219.01 5.1 219.74 ; + RECT 5.555 219.01 5.755 219.74 ; + RECT 5.965 219.01 6.325 219.74 ; + RECT 6.535 219.01 6.735 219.74 ; + RECT 6.27 0.18 7.04 0.88 ; + RECT 7.19 219.01 7.39 219.74 ; + RECT 7.29 0.3 7.55 8.7 ; + RECT 7.6 219.01 7.96 219.74 ; + RECT 8.255 219.01 8.455 219.74 ; + RECT 8.75 219.01 9.11 219.74 ; + RECT 9.84 0.155 10.61 0.445 ; + RECT 9.84 0.155 10.1 8.665 ; + RECT 10.35 0.155 10.61 8.665 ; + RECT 9.32 219.01 9.52 219.74 ; + RECT 9.33 0.52 9.59 9.955 ; + RECT 9.975 219.01 10.175 219.74 ; + RECT 10.385 219.01 10.745 219.74 ; + RECT 10.86 0.52 11.12 11.315 ; + RECT 10.955 219.01 11.155 219.74 ; + RECT 11.37 0.52 11.63 13.45 ; + RECT 11.61 219.01 11.81 219.74 ; + RECT 11.88 0.52 12.14 14.115 ; + RECT 12.02 219.01 12.38 219.74 ; + RECT 12.675 219.01 12.875 219.74 ; + RECT 14.075 0.155 14.845 0.445 ; + RECT 14.075 0.155 14.335 13.21 ; + RECT 14.585 0.155 14.845 13.21 ; + RECT 13.17 219.01 13.53 219.74 ; + RECT 13.74 219.01 13.94 219.74 ; + RECT 15.095 0.18 15.865 0.88 ; + RECT 15.095 0.18 15.355 12.9 ; + RECT 15.605 0.18 15.865 12.9 ; + RECT 14.395 219.01 14.595 219.74 ; + RECT 14.805 219.01 15.165 219.74 ; + RECT 15.375 219.01 15.575 219.74 ; + RECT 16.03 219.01 16.23 219.74 ; + RECT 16.315 0.52 16.575 2.82 ; + RECT 16.44 219.01 16.8 219.74 ; + RECT 17.095 219.01 17.295 219.74 ; + RECT 17.59 219.01 17.95 219.74 ; + RECT 17.845 0.52 18.105 2.82 ; + RECT 18.16 219.01 18.36 219.74 ; + RECT 18.815 219.01 19.015 219.74 ; + RECT 19.02 0.52 19.28 4.315 ; + RECT 19.225 219.01 19.585 219.74 ; + RECT 19.795 219.01 19.995 219.74 ; + RECT 19.87 0.52 20.13 7.78 ; + RECT 20.38 0.3 20.64 5.235 ; + RECT 20.45 219.01 20.65 219.74 ; + RECT 20.89 0.52 21.15 5.57 ; + RECT 20.86 219.01 21.22 219.74 ; + RECT 21.515 219.01 21.715 219.74 ; + RECT 22.01 219.01 22.37 219.74 ; + RECT 22.265 0.52 22.525 6.28 ; + RECT 22.58 219.01 22.78 219.74 ; + RECT 23.235 219.01 23.435 219.74 ; + RECT 23.645 219.01 24.005 219.74 ; + RECT 24.215 219.01 24.415 219.74 ; + RECT 23.95 0.18 24.72 0.88 ; + RECT 24.87 219.01 25.07 219.74 ; + RECT 24.97 0.3 25.23 8.7 ; + RECT 25.28 219.01 25.64 219.74 ; + RECT 25.935 219.01 26.135 219.74 ; + RECT 26.43 219.01 26.79 219.74 ; + RECT 27.52 0.155 28.29 0.445 ; + RECT 27.52 0.155 27.78 8.665 ; + RECT 28.03 0.155 28.29 8.665 ; + RECT 27 219.01 27.2 219.74 ; + RECT 27.01 0.52 27.27 9.955 ; + RECT 27.655 219.01 27.855 219.74 ; + RECT 28.065 219.01 28.425 219.74 ; + RECT 28.54 0.52 28.8 11.315 ; + RECT 28.635 219.01 28.835 219.74 ; + RECT 29.05 0.52 29.31 13.45 ; + RECT 29.29 219.01 29.49 219.74 ; + RECT 29.56 0.52 29.82 14.115 ; + RECT 29.7 219.01 30.06 219.74 ; + RECT 30.355 219.01 30.555 219.74 ; + RECT 31.755 0.155 32.525 0.445 ; + RECT 31.755 0.155 32.015 13.21 ; + RECT 32.265 0.155 32.525 13.21 ; + RECT 30.85 219.01 31.21 219.74 ; + RECT 31.42 219.01 31.62 219.74 ; + RECT 32.775 0.18 33.545 0.88 ; + RECT 32.775 0.18 33.035 12.9 ; + RECT 33.285 0.18 33.545 12.9 ; + RECT 32.075 219.01 32.275 219.74 ; + RECT 32.485 219.01 32.845 219.74 ; + RECT 33.055 219.01 33.255 219.74 ; + RECT 33.71 219.01 33.91 219.74 ; + RECT 33.995 0.52 34.255 2.82 ; + RECT 34.12 219.01 34.48 219.74 ; + RECT 34.775 219.01 34.975 219.74 ; + RECT 35.27 219.01 35.63 219.74 ; + RECT 35.525 0.52 35.785 2.82 ; + RECT 35.84 219.01 36.04 219.74 ; + RECT 36.495 219.01 36.695 219.74 ; + RECT 36.7 0.52 36.96 4.315 ; + RECT 36.905 219.01 37.265 219.74 ; + RECT 37.475 219.01 37.675 219.74 ; + RECT 37.55 0.52 37.81 7.78 ; + RECT 38.06 0.3 38.32 5.235 ; + RECT 38.13 219.01 38.33 219.74 ; + RECT 38.57 0.52 38.83 5.57 ; + RECT 38.54 219.01 38.9 219.74 ; + RECT 39.195 219.01 39.395 219.74 ; + RECT 39.69 219.01 40.05 219.74 ; + RECT 39.945 0.52 40.205 6.28 ; + RECT 40.26 219.01 40.46 219.74 ; + RECT 40.915 219.01 41.115 219.74 ; + RECT 41.325 219.01 41.685 219.74 ; + RECT 41.895 219.01 42.095 219.74 ; + RECT 41.63 0.18 42.4 0.88 ; + RECT 42.55 219.01 42.75 219.74 ; + RECT 42.65 0.3 42.91 8.7 ; + RECT 42.96 219.01 43.32 219.74 ; + RECT 43.615 219.01 43.815 219.74 ; + RECT 44.11 219.01 44.47 219.74 ; + RECT 45.2 0.155 45.97 0.445 ; + RECT 45.2 0.155 45.46 8.665 ; + RECT 45.71 0.155 45.97 8.665 ; + RECT 44.68 219.01 44.88 219.74 ; + RECT 44.69 0.52 44.95 9.955 ; + RECT 45.335 219.01 45.535 219.74 ; + RECT 45.745 219.01 46.105 219.74 ; + RECT 46.22 0.52 46.48 11.315 ; + RECT 46.315 219.01 46.515 219.74 ; + RECT 46.73 0.52 46.99 13.45 ; + RECT 46.97 219.01 47.17 219.74 ; + RECT 47.24 0.52 47.5 14.115 ; + RECT 47.38 219.01 47.74 219.74 ; + RECT 48.035 219.01 48.235 219.74 ; + RECT 49.435 0.155 50.205 0.445 ; + RECT 49.435 0.155 49.695 13.21 ; + RECT 49.945 0.155 50.205 13.21 ; + RECT 48.53 219.01 48.89 219.74 ; + RECT 49.1 219.01 49.3 219.74 ; + RECT 50.455 0.18 51.225 0.88 ; + RECT 50.455 0.18 50.715 12.9 ; + RECT 50.965 0.18 51.225 12.9 ; + RECT 49.755 219.01 49.955 219.74 ; + RECT 50.165 219.01 50.525 219.74 ; + RECT 50.735 219.01 50.935 219.74 ; + RECT 51.39 219.01 51.59 219.74 ; + RECT 51.675 0.52 51.935 2.82 ; + RECT 51.8 219.01 52.16 219.74 ; + RECT 52.455 219.01 52.655 219.74 ; + RECT 52.95 219.01 53.31 219.74 ; + RECT 53.205 0.52 53.465 2.82 ; + RECT 53.52 219.01 53.72 219.74 ; + RECT 54.175 219.01 54.375 219.74 ; + RECT 54.38 0.52 54.64 4.315 ; + RECT 54.585 219.01 54.945 219.74 ; + RECT 55.155 219.01 55.355 219.74 ; + RECT 55.23 0.52 55.49 7.78 ; + RECT 55.74 0.3 56 5.235 ; + RECT 55.81 219.01 56.01 219.74 ; + RECT 56.25 0.52 56.51 5.57 ; + RECT 56.22 219.01 56.58 219.74 ; + RECT 56.875 219.01 57.075 219.74 ; + RECT 57.37 219.01 57.73 219.74 ; + RECT 57.625 0.52 57.885 6.28 ; + RECT 57.94 219.01 58.14 219.74 ; + RECT 58.595 219.01 58.795 219.74 ; + RECT 59.005 219.01 59.365 219.74 ; + RECT 59.575 219.01 59.775 219.74 ; + RECT 59.31 0.18 60.08 0.88 ; + RECT 60.23 219.01 60.43 219.74 ; + RECT 60.33 0.3 60.59 8.7 ; + RECT 60.64 219.01 61 219.74 ; + RECT 61.295 219.01 61.495 219.74 ; + RECT 61.79 219.01 62.15 219.74 ; + RECT 62.88 0.155 63.65 0.445 ; + RECT 62.88 0.155 63.14 8.665 ; + RECT 63.39 0.155 63.65 8.665 ; + RECT 62.36 219.01 62.56 219.74 ; + RECT 62.37 0.52 62.63 9.955 ; + RECT 63.015 219.01 63.215 219.74 ; + RECT 63.425 219.01 63.785 219.74 ; + RECT 63.9 0.52 64.16 11.315 ; + RECT 63.995 219.01 64.195 219.74 ; + RECT 64.41 0.52 64.67 13.45 ; + RECT 64.65 219.01 64.85 219.74 ; + RECT 64.92 0.52 65.18 14.115 ; + RECT 65.06 219.01 65.42 219.74 ; + RECT 65.715 219.01 65.915 219.74 ; + RECT 67.115 0.155 67.885 0.445 ; + RECT 67.115 0.155 67.375 13.21 ; + RECT 67.625 0.155 67.885 13.21 ; + RECT 66.21 219.01 66.57 219.74 ; + RECT 66.78 219.01 66.98 219.74 ; + RECT 68.135 0.18 68.905 0.88 ; + RECT 68.135 0.18 68.395 12.9 ; + RECT 68.645 0.18 68.905 12.9 ; + RECT 67.435 219.01 67.635 219.74 ; + RECT 67.845 219.01 68.205 219.74 ; + RECT 68.415 219.01 68.615 219.74 ; + RECT 69.07 219.01 69.27 219.74 ; + RECT 69.355 0.52 69.615 2.82 ; + RECT 69.48 219.01 69.84 219.74 ; + RECT 70.135 219.01 70.335 219.74 ; + RECT 70.63 219.01 70.99 219.74 ; + RECT 70.885 0.52 71.145 2.82 ; + RECT 71.2 219.01 71.4 219.74 ; + RECT 71.855 219.01 72.055 219.74 ; + RECT 72.06 0.52 72.32 4.315 ; + RECT 72.265 219.01 72.625 219.74 ; + RECT 72.835 219.01 73.035 219.74 ; + RECT 72.91 0.52 73.17 7.78 ; + RECT 73.42 0.3 73.68 5.235 ; + RECT 73.49 219.01 73.69 219.74 ; + RECT 73.93 0.52 74.19 5.57 ; + RECT 73.9 219.01 74.26 219.74 ; + RECT 74.555 219.01 74.755 219.74 ; + RECT 75.05 219.01 75.41 219.74 ; + RECT 75.305 0.52 75.565 6.28 ; + RECT 75.62 219.01 75.82 219.74 ; + RECT 76.275 219.01 76.475 219.74 ; + RECT 76.685 219.01 77.045 219.74 ; + RECT 77.255 219.01 77.455 219.74 ; + RECT 76.99 0.18 77.76 0.88 ; + RECT 77.91 219.01 78.11 219.74 ; + RECT 78.01 0.3 78.27 8.7 ; + RECT 78.32 219.01 78.68 219.74 ; + RECT 78.975 219.01 79.175 219.74 ; + RECT 79.47 219.01 79.83 219.74 ; + RECT 80.56 0.155 81.33 0.445 ; + RECT 80.56 0.155 80.82 8.665 ; + RECT 81.07 0.155 81.33 8.665 ; + RECT 80.04 219.01 80.24 219.74 ; + RECT 80.05 0.52 80.31 9.955 ; + RECT 80.695 219.01 80.895 219.74 ; + RECT 81.105 219.01 81.465 219.74 ; + RECT 81.58 0.52 81.84 11.315 ; + RECT 81.675 219.01 81.875 219.74 ; + RECT 82.09 0.52 82.35 13.45 ; + RECT 82.33 219.01 82.53 219.74 ; + RECT 82.6 0.52 82.86 14.115 ; + RECT 82.74 219.01 83.1 219.74 ; + RECT 83.395 219.01 83.595 219.74 ; + RECT 84.795 0.155 85.565 0.445 ; + RECT 84.795 0.155 85.055 13.21 ; + RECT 85.305 0.155 85.565 13.21 ; + RECT 83.89 219.01 84.25 219.74 ; + RECT 84.46 219.01 84.66 219.74 ; + RECT 85.815 0.18 86.585 0.88 ; + RECT 85.815 0.18 86.075 12.9 ; + RECT 86.325 0.18 86.585 12.9 ; + RECT 85.115 219.01 85.315 219.74 ; + RECT 85.525 219.01 85.885 219.74 ; + RECT 86.095 219.01 86.295 219.74 ; + RECT 86.75 219.01 86.95 219.74 ; + RECT 87.035 0.52 87.295 2.82 ; + RECT 87.16 219.01 87.52 219.74 ; + RECT 87.815 219.01 88.015 219.74 ; + RECT 88.31 219.01 88.67 219.74 ; + RECT 88.565 0.52 88.825 2.82 ; + RECT 88.88 219.01 89.08 219.74 ; + RECT 89.535 219.01 89.735 219.74 ; + RECT 89.74 0.52 90 4.315 ; + RECT 89.945 219.01 90.305 219.74 ; + RECT 90.515 219.01 90.715 219.74 ; + RECT 90.59 0.52 90.85 7.78 ; + RECT 91.1 0.3 91.36 5.235 ; + RECT 91.17 219.01 91.37 219.74 ; + RECT 91.61 0.52 91.87 5.57 ; + RECT 91.58 219.01 91.94 219.74 ; + RECT 92.235 219.01 92.435 219.74 ; + RECT 92.73 219.01 93.09 219.74 ; + RECT 92.985 0.52 93.245 6.28 ; + RECT 93.3 219.01 93.5 219.74 ; + RECT 93.955 219.01 94.155 219.74 ; + RECT 94.365 219.01 94.725 219.74 ; + RECT 94.935 219.01 95.135 219.74 ; + RECT 94.67 0.18 95.44 0.88 ; + RECT 95.59 219.01 95.79 219.74 ; + RECT 95.69 0.3 95.95 8.7 ; + RECT 96 219.01 96.36 219.74 ; + RECT 96.655 219.01 96.855 219.74 ; + RECT 97.15 219.01 97.51 219.74 ; + RECT 98.24 0.155 99.01 0.445 ; + RECT 98.24 0.155 98.5 8.665 ; + RECT 98.75 0.155 99.01 8.665 ; + RECT 97.72 219.01 97.92 219.74 ; + RECT 97.73 0.52 97.99 9.955 ; + RECT 98.375 219.01 98.575 219.74 ; + RECT 98.785 219.01 99.145 219.74 ; + RECT 99.26 0.52 99.52 11.315 ; + RECT 99.355 219.01 99.555 219.74 ; + RECT 99.77 0.52 100.03 13.45 ; + RECT 100.01 219.01 100.21 219.74 ; + RECT 100.28 0.52 100.54 14.115 ; + RECT 100.42 219.01 100.78 219.74 ; + RECT 101.075 219.01 101.275 219.74 ; + RECT 102.475 0.155 103.245 0.445 ; + RECT 102.475 0.155 102.735 13.21 ; + RECT 102.985 0.155 103.245 13.21 ; + RECT 101.57 219.01 101.93 219.74 ; + RECT 102.14 219.01 102.34 219.74 ; + RECT 103.495 0.18 104.265 0.88 ; + RECT 103.495 0.18 103.755 12.9 ; + RECT 104.005 0.18 104.265 12.9 ; + RECT 102.795 219.01 102.995 219.74 ; + RECT 103.205 219.01 103.565 219.74 ; + RECT 103.775 219.01 103.975 219.74 ; + RECT 104.43 219.01 104.63 219.74 ; + RECT 104.715 0.52 104.975 2.82 ; + RECT 104.84 219.01 105.2 219.74 ; + RECT 105.495 219.01 105.695 219.74 ; + RECT 105.99 219.01 106.35 219.74 ; + RECT 106.245 0.52 106.505 2.82 ; + RECT 106.56 219.01 106.76 219.74 ; + RECT 107.215 219.01 107.415 219.74 ; + RECT 107.42 0.52 107.68 4.315 ; + RECT 107.625 219.01 107.985 219.74 ; + RECT 108.195 219.01 108.395 219.74 ; + RECT 108.27 0.52 108.53 7.78 ; + RECT 108.78 0.3 109.04 5.235 ; + RECT 108.85 219.01 109.05 219.74 ; + RECT 109.29 0.52 109.55 5.57 ; + RECT 109.26 219.01 109.62 219.74 ; + RECT 109.915 219.01 110.115 219.74 ; + RECT 110.41 219.01 110.77 219.74 ; + RECT 110.665 0.52 110.925 6.28 ; + RECT 110.98 219.01 111.18 219.74 ; + RECT 111.635 219.01 111.835 219.74 ; + RECT 112.045 219.01 112.405 219.74 ; + RECT 112.615 219.01 112.815 219.74 ; + RECT 112.35 0.18 113.12 0.88 ; + RECT 113.27 219.01 113.47 219.74 ; + RECT 113.37 0.3 113.63 8.7 ; + RECT 113.68 219.01 114.04 219.74 ; + RECT 114.335 219.01 114.535 219.74 ; + RECT 114.83 219.01 115.19 219.74 ; + RECT 115.92 0.155 116.69 0.445 ; + RECT 115.92 0.155 116.18 8.665 ; + RECT 116.43 0.155 116.69 8.665 ; + RECT 115.4 219.01 115.6 219.74 ; + RECT 115.41 0.52 115.67 9.955 ; + RECT 116.055 219.01 116.255 219.74 ; + RECT 116.465 219.01 116.825 219.74 ; + RECT 116.94 0.52 117.2 11.315 ; + RECT 117.035 219.01 117.235 219.74 ; + RECT 117.45 0.52 117.71 13.45 ; + RECT 117.69 219.01 117.89 219.74 ; + RECT 117.96 0.52 118.22 14.115 ; + RECT 118.1 219.01 118.46 219.74 ; + RECT 118.755 219.01 118.955 219.74 ; + RECT 120.155 0.155 120.925 0.445 ; + RECT 120.155 0.155 120.415 13.21 ; + RECT 120.665 0.155 120.925 13.21 ; + RECT 119.25 219.01 119.61 219.74 ; + RECT 119.82 219.01 120.02 219.74 ; + RECT 121.175 0.18 121.945 0.88 ; + RECT 121.175 0.18 121.435 12.9 ; + RECT 121.685 0.18 121.945 12.9 ; + RECT 120.475 219.01 120.675 219.74 ; + RECT 120.885 219.01 121.245 219.74 ; + RECT 121.455 219.01 121.655 219.74 ; + RECT 122.11 219.01 122.31 219.74 ; + RECT 122.395 0.52 122.655 2.82 ; + RECT 122.52 219.01 122.88 219.74 ; + RECT 123.175 219.01 123.375 219.74 ; + RECT 123.67 219.01 124.03 219.74 ; + RECT 123.925 0.52 124.185 2.82 ; + RECT 124.24 219.01 124.44 219.74 ; + RECT 124.895 219.01 125.095 219.74 ; + RECT 125.1 0.52 125.36 4.315 ; + RECT 125.305 219.01 125.665 219.74 ; + RECT 125.875 219.01 126.075 219.74 ; + RECT 125.95 0.52 126.21 7.78 ; + RECT 126.46 0.3 126.72 5.235 ; + RECT 126.53 219.01 126.73 219.74 ; + RECT 126.97 0.52 127.23 5.57 ; + RECT 126.94 219.01 127.3 219.74 ; + RECT 127.595 219.01 127.795 219.74 ; + RECT 128.09 219.01 128.45 219.74 ; + RECT 128.345 0.52 128.605 6.28 ; + RECT 128.66 219.01 128.86 219.74 ; + RECT 129.315 219.01 129.515 219.74 ; + RECT 129.725 219.01 130.085 219.74 ; + RECT 130.295 219.01 130.495 219.74 ; + RECT 130.03 0.18 130.8 0.88 ; + RECT 130.95 219.01 131.15 219.74 ; + RECT 131.05 0.3 131.31 8.7 ; + RECT 131.36 219.01 131.72 219.74 ; + RECT 132.015 219.01 132.215 219.74 ; + RECT 132.51 219.01 132.87 219.74 ; + RECT 133.6 0.155 134.37 0.445 ; + RECT 133.6 0.155 133.86 8.665 ; + RECT 134.11 0.155 134.37 8.665 ; + RECT 133.08 219.01 133.28 219.74 ; + RECT 133.09 0.52 133.35 9.955 ; + RECT 133.735 219.01 133.935 219.74 ; + RECT 134.145 219.01 134.505 219.74 ; + RECT 134.62 0.52 134.88 11.315 ; + RECT 134.715 219.01 134.915 219.74 ; + RECT 135.13 0.52 135.39 13.45 ; + RECT 135.37 219.01 135.57 219.74 ; + RECT 135.64 0.52 135.9 14.115 ; + RECT 135.78 219.01 136.14 219.74 ; + RECT 136.435 219.01 136.635 219.74 ; + RECT 137.835 0.155 138.605 0.445 ; + RECT 137.835 0.155 138.095 13.21 ; + RECT 138.345 0.155 138.605 13.21 ; + RECT 136.93 219.01 137.29 219.74 ; + RECT 137.5 219.01 137.7 219.74 ; + RECT 138.855 0.18 139.625 0.88 ; + RECT 138.855 0.18 139.115 12.9 ; + RECT 139.365 0.18 139.625 12.9 ; + RECT 138.155 219.01 138.355 219.74 ; + RECT 138.565 219.01 138.925 219.74 ; + RECT 139.135 219.01 139.335 219.74 ; + RECT 139.79 219.01 139.99 219.74 ; + RECT 140.075 0.52 140.335 2.82 ; + RECT 140.2 219.01 140.56 219.74 ; + RECT 140.855 219.01 141.055 219.74 ; + RECT 141.35 219.01 141.71 219.74 ; + RECT 141.605 0.52 141.865 2.82 ; + RECT 141.92 219.01 142.12 219.74 ; + RECT 142.575 219.01 142.775 219.74 ; + RECT 143.8 0.17 144.57 0.43 ; + RECT 143.8 0.17 144.06 8.7 ; + RECT 144.31 0.17 144.57 8.7 ; + RECT 142.78 0.52 143.04 4.315 ; + RECT 144.82 0.18 145.59 0.88 ; + RECT 144.82 0.18 145.08 8.7 ; + RECT 145.33 0.18 145.59 8.7 ; + RECT 145.84 0.17 146.61 0.43 ; + RECT 145.84 0.17 146.1 8.7 ; + RECT 146.35 0.17 146.61 8.7 ; + RECT 146.86 0.18 147.63 0.88 ; + RECT 146.86 0.18 147.12 8.7 ; + RECT 147.37 0.18 147.63 8.7 ; + RECT 147.88 0.17 148.65 0.43 ; + RECT 147.88 0.17 148.14 8.7 ; + RECT 148.39 0.17 148.65 8.7 ; + RECT 148.9 0.18 149.67 0.88 ; + RECT 148.9 0.18 149.16 8.7 ; + RECT 149.41 0.18 149.67 8.7 ; + RECT 149.92 0.17 150.69 0.43 ; + RECT 149.92 0.17 150.18 8.7 ; + RECT 150.43 0.17 150.69 8.7 ; + RECT 150.94 0.18 151.71 0.88 ; + RECT 150.94 0.18 151.2 8.7 ; + RECT 151.45 0.18 151.71 8.7 ; + RECT 151.96 0.17 152.73 0.43 ; + RECT 151.96 0.17 152.22 8.7 ; + RECT 152.47 0.17 152.73 8.7 ; + RECT 152.98 0.18 153.75 0.88 ; + RECT 152.98 0.18 153.24 8.7 ; + RECT 153.49 0.18 153.75 8.7 ; + RECT 154 0.17 154.77 0.43 ; + RECT 154 0.17 154.26 8.7 ; + RECT 154.51 0.17 154.77 8.7 ; + RECT 155.02 0.18 155.79 0.88 ; + RECT 155.02 0.18 155.28 8.7 ; + RECT 155.53 0.18 155.79 8.7 ; + RECT 156.04 0.17 156.81 0.43 ; + RECT 156.04 0.17 156.3 8.7 ; + RECT 156.55 0.17 156.81 8.7 ; + RECT 157.06 0.18 157.83 0.88 ; + RECT 157.06 0.18 157.32 8.7 ; + RECT 157.57 0.18 157.83 8.7 ; + RECT 158.08 0.17 158.85 0.43 ; + RECT 158.08 0.17 158.34 8.7 ; + RECT 158.59 0.17 158.85 8.7 ; + RECT 159.1 0.18 159.87 0.88 ; + RECT 159.1 0.18 159.36 8.7 ; + RECT 159.61 0.18 159.87 8.7 ; + RECT 142.985 219.01 143.345 219.74 ; + RECT 143.555 219.01 143.755 219.74 ; + RECT 161.495 0.18 162.265 0.88 ; + RECT 161.495 0.18 161.755 8.7 ; + RECT 162.005 0.18 162.265 8.7 ; + RECT 162.515 0.17 163.285 0.43 ; + RECT 162.515 0.17 162.775 8.7 ; + RECT 163.025 0.17 163.285 8.7 ; + RECT 144.38 218.93 144.58 219.74 ; + RECT 160.475 0.3 160.735 8.7 ; + RECT 164.555 0.18 165.325 0.88 ; + RECT 164.555 0.18 164.815 8.7 ; + RECT 165.065 0.18 165.325 8.7 ; + RECT 160.985 0.3 161.245 8.7 ; + RECT 163.535 0 163.795 8.7 ; + RECT 164.045 0 164.305 8.7 ; + RECT 165.575 0.52 165.835 8.7 ; + RECT 166.085 0.3 166.345 8.7 ; + RECT 166.595 0.3 166.855 8.7 ; + RECT 167.105 0.3 167.365 8.7 ; + RECT 167.615 0.3 167.875 8.7 ; + RECT 168.125 0.3 168.385 8.7 ; + RECT 168.635 0.3 168.895 8.7 ; + RECT 169.145 0.3 169.405 8.7 ; + RECT 171.185 0.18 171.955 0.88 ; + RECT 171.185 0.18 171.445 8.7 ; + RECT 171.695 0.18 171.955 8.7 ; + RECT 169.655 0.3 169.915 8.7 ; + RECT 170.165 0.52 170.425 8.7 ; + RECT 170.675 0.52 170.935 8.7 ; + RECT 172.205 0 172.465 8.7 ; + RECT 172.715 0 172.975 8.7 ; + RECT 173.225 0.52 173.485 8.7 ; + RECT 173.735 0.52 173.995 8.7 ; + RECT 174.245 0.52 174.505 8.7 ; + RECT 174.755 0.52 175.015 8.7 ; + RECT 175.265 0.52 175.525 8.7 ; + RECT 175.775 0.52 176.035 8.7 ; + RECT 176.285 0.52 176.545 8.7 ; + RECT 176.795 0.52 177.055 8.7 ; + RECT 177.305 0.3 177.565 8.7 ; + RECT 177.815 0.3 178.075 8.7 ; + RECT 178.325 0.3 178.585 8.7 ; + RECT 178.835 0.52 179.095 8.7 ; + RECT 179.345 0.52 179.605 8.7 ; + RECT 179.855 0.3 180.115 8.7 ; + RECT 180.365 0.3 180.625 8.7 ; + RECT 180.875 0.3 181.135 8.7 ; + RECT 181.385 0.52 181.645 8.7 ; + RECT 181.895 0.52 182.155 8.7 ; + RECT 182.405 0.3 182.665 8.7 ; + RECT 182.915 0.52 183.175 8.7 ; + RECT 183.425 0.52 183.685 8.7 ; + RECT 183.935 0.52 184.195 8.7 ; + RECT 184.445 0.52 184.705 8.7 ; + RECT 184.955 0.52 185.215 8.7 ; + RECT 185.465 0.3 185.725 8.7 ; + RECT 185.975 0.52 186.235 8.7 ; + RECT 186.485 0.52 186.745 8.7 ; + RECT 186.995 0.3 187.255 8.7 ; + RECT 187.505 0.52 187.765 8.7 ; + RECT 189.545 0.17 190.315 0.43 ; + RECT 189.545 0.17 189.805 8.7 ; + RECT 190.055 0.17 190.315 8.7 ; + RECT 188.015 0.52 188.275 8.7 ; + RECT 188.525 0.3 188.785 8.7 ; + RECT 189.035 0.3 189.295 8.7 ; + RECT 192.095 0.17 192.865 0.43 ; + RECT 192.095 0.17 192.355 8.7 ; + RECT 192.605 0.17 192.865 8.7 ; + RECT 190.565 0.3 190.825 8.7 ; + RECT 193.625 0.18 194.395 0.88 ; + RECT 193.625 0.18 193.885 8.7 ; + RECT 194.135 0.18 194.395 8.7 ; + RECT 191.075 0.3 191.335 8.7 ; + RECT 191.585 0.3 191.845 8.7 ; + RECT 193.115 0.3 193.375 8.7 ; + RECT 194.645 0 194.905 8.7 ; + RECT 195.155 0 195.415 8.7 ; + RECT 195.665 0.52 195.925 8.7 ; + RECT 196.175 0.52 196.435 8.7 ; + RECT 196.685 0.52 196.945 8.7 ; + RECT 197.195 0.52 197.455 8.7 ; + RECT 197.705 0 197.965 8.7 ; + RECT 198.215 0 198.475 8.7 ; + RECT 198.725 0.3 198.985 8.7 ; + RECT 199.235 0.3 199.495 8.7 ; + RECT 199.745 0 200.005 8.7 ; + RECT 200.255 0 200.515 8.7 ; + RECT 200.765 0.3 201.025 8.7 ; + RECT 201.585 0.3 201.845 8.7 ; + RECT 202.095 0 202.355 8.7 ; + RECT 202.605 0 202.865 8.7 ; + RECT 203.115 0.3 203.375 8.7 ; + RECT 203.625 0.3 203.885 8.7 ; + RECT 204.135 0 204.395 8.7 ; + RECT 204.645 0 204.905 8.7 ; + RECT 205.155 0.52 205.415 8.7 ; + RECT 205.665 0.52 205.925 8.7 ; + RECT 206.175 0.52 206.435 8.7 ; + RECT 208.215 0.18 208.985 0.88 ; + RECT 208.215 0.18 208.475 8.7 ; + RECT 208.725 0.18 208.985 8.7 ; + RECT 206.685 0.52 206.945 8.7 ; + RECT 209.745 0.17 210.515 0.43 ; + RECT 209.745 0.17 210.005 8.7 ; + RECT 210.255 0.17 210.515 8.7 ; + RECT 207.195 0 207.455 8.7 ; + RECT 207.705 0 207.965 8.7 ; + RECT 209.235 0.3 209.495 8.7 ; + RECT 212.295 0.17 213.065 0.43 ; + RECT 212.295 0.17 212.555 8.7 ; + RECT 212.805 0.17 213.065 8.7 ; + RECT 210.765 0.3 211.025 8.7 ; + RECT 211.275 0.3 211.535 8.7 ; + RECT 211.785 0.3 212.045 8.7 ; + RECT 213.315 0.3 213.575 8.7 ; + RECT 213.825 0.3 214.085 8.7 ; + RECT 214.335 0.52 214.595 8.7 ; + RECT 214.845 0.52 215.105 8.7 ; + RECT 215.355 0.3 215.615 8.7 ; + RECT 215.865 0.52 216.125 8.7 ; + RECT 216.375 0.52 216.635 8.7 ; + RECT 216.885 0.3 217.145 8.7 ; + RECT 217.395 0.52 217.655 8.7 ; + RECT 217.905 0.52 218.165 8.7 ; + RECT 218.415 0.52 218.675 8.7 ; + RECT 218.925 0.52 219.185 8.7 ; + RECT 219.435 0.52 219.695 8.7 ; + RECT 219.945 0.3 220.205 8.7 ; + RECT 220.455 0.52 220.715 8.7 ; + RECT 220.965 0.52 221.225 8.7 ; + RECT 221.475 0.3 221.735 8.7 ; + RECT 221.985 0.3 222.245 8.7 ; + RECT 222.495 0.3 222.755 8.7 ; + RECT 223.005 0.52 223.265 8.7 ; + RECT 223.515 0.52 223.775 8.7 ; + RECT 224.025 0.3 224.285 8.7 ; + RECT 224.535 0.3 224.795 8.7 ; + RECT 225.045 0.3 225.305 8.7 ; + RECT 225.555 0.52 225.815 8.7 ; + RECT 226.065 0.52 226.325 8.7 ; + RECT 226.575 0.52 226.835 8.7 ; + RECT 227.085 0.52 227.345 8.7 ; + RECT 227.595 0.52 227.855 8.7 ; + RECT 228.105 0.52 228.365 8.7 ; + RECT 228.615 0.52 228.875 8.7 ; + RECT 230.655 0.18 231.425 0.88 ; + RECT 230.655 0.18 230.915 8.7 ; + RECT 231.165 0.18 231.425 8.7 ; + RECT 229.125 0.52 229.385 8.7 ; + RECT 229.635 0 229.895 8.7 ; + RECT 230.145 0 230.405 8.7 ; + RECT 231.675 0.52 231.935 8.7 ; + RECT 232.185 0.52 232.445 8.7 ; + RECT 232.695 0.3 232.955 8.7 ; + RECT 233.205 0.3 233.465 8.7 ; + RECT 233.715 0.3 233.975 8.7 ; + RECT 234.225 0.3 234.485 8.7 ; + RECT 234.735 0.3 234.995 8.7 ; + RECT 235.245 0.3 235.505 8.7 ; + RECT 237.285 0.18 238.055 0.88 ; + RECT 237.285 0.18 237.545 8.7 ; + RECT 237.795 0.18 238.055 8.7 ; + RECT 235.755 0.3 236.015 8.7 ; + RECT 236.265 0.3 236.525 8.7 ; + RECT 239.325 0.17 240.095 0.43 ; + RECT 239.325 0.17 239.585 8.7 ; + RECT 239.835 0.17 240.095 8.7 ; + RECT 240.345 0.18 241.115 0.88 ; + RECT 240.345 0.18 240.605 8.7 ; + RECT 240.855 0.18 241.115 8.7 ; + RECT 236.775 0.52 237.035 8.7 ; + RECT 238.305 0 238.565 8.7 ; + RECT 242.74 0.18 243.51 0.88 ; + RECT 242.74 0.18 243 8.7 ; + RECT 243.25 0.18 243.51 8.7 ; + RECT 243.76 0.17 244.53 0.43 ; + RECT 243.76 0.17 244.02 8.7 ; + RECT 244.27 0.17 244.53 8.7 ; + RECT 244.78 0.18 245.55 0.88 ; + RECT 244.78 0.18 245.04 8.7 ; + RECT 245.29 0.18 245.55 8.7 ; + RECT 245.8 0.17 246.57 0.43 ; + RECT 245.8 0.17 246.06 8.7 ; + RECT 246.31 0.17 246.57 8.7 ; + RECT 246.82 0.18 247.59 0.88 ; + RECT 246.82 0.18 247.08 8.7 ; + RECT 247.33 0.18 247.59 8.7 ; + RECT 247.84 0.17 248.61 0.43 ; + RECT 247.84 0.17 248.1 8.7 ; + RECT 248.35 0.17 248.61 8.7 ; + RECT 248.86 0.18 249.63 0.88 ; + RECT 248.86 0.18 249.12 8.7 ; + RECT 249.37 0.18 249.63 8.7 ; + RECT 249.88 0.17 250.65 0.43 ; + RECT 249.88 0.17 250.14 8.7 ; + RECT 250.39 0.17 250.65 8.7 ; + RECT 250.9 0.18 251.67 0.88 ; + RECT 250.9 0.18 251.16 8.7 ; + RECT 251.41 0.18 251.67 8.7 ; + RECT 251.92 0.17 252.69 0.43 ; + RECT 251.92 0.17 252.18 8.7 ; + RECT 252.43 0.17 252.69 8.7 ; + RECT 252.94 0.18 253.71 0.88 ; + RECT 252.94 0.18 253.2 8.7 ; + RECT 253.45 0.18 253.71 8.7 ; + RECT 253.96 0.17 254.73 0.43 ; + RECT 253.96 0.17 254.22 8.7 ; + RECT 254.47 0.17 254.73 8.7 ; + RECT 254.98 0.18 255.75 0.88 ; + RECT 254.98 0.18 255.24 8.7 ; + RECT 255.49 0.18 255.75 8.7 ; + RECT 256 0.17 256.77 0.43 ; + RECT 256 0.17 256.26 8.7 ; + RECT 256.51 0.17 256.77 8.7 ; + RECT 257.02 0.18 257.79 0.88 ; + RECT 257.02 0.18 257.28 8.7 ; + RECT 257.53 0.18 257.79 8.7 ; + RECT 238.815 0 239.075 8.7 ; + RECT 258.04 0.17 258.81 0.43 ; + RECT 258.04 0.17 258.3 8.7 ; + RECT 258.55 0.17 258.81 8.7 ; + RECT 241.365 0.3 241.625 8.7 ; + RECT 241.875 0.3 242.135 8.7 ; + RECT 258.03 218.93 258.23 219.74 ; + RECT 258.855 219.01 259.055 219.74 ; + RECT 259.265 219.01 259.625 219.74 ; + RECT 259.57 0.52 259.83 4.315 ; + RECT 259.835 219.01 260.035 219.74 ; + RECT 260.49 219.01 260.69 219.74 ; + RECT 260.745 0.52 261.005 2.82 ; + RECT 260.9 219.01 261.26 219.74 ; + RECT 261.555 219.01 261.755 219.74 ; + RECT 262.05 219.01 262.41 219.74 ; + RECT 262.985 0.18 263.755 0.88 ; + RECT 262.985 0.18 263.245 12.9 ; + RECT 263.495 0.18 263.755 12.9 ; + RECT 262.275 0.52 262.535 2.82 ; + RECT 262.62 219.01 262.82 219.74 ; + RECT 264.005 0.155 264.775 0.445 ; + RECT 264.005 0.155 264.265 13.21 ; + RECT 264.515 0.155 264.775 13.21 ; + RECT 263.275 219.01 263.475 219.74 ; + RECT 263.685 219.01 264.045 219.74 ; + RECT 264.255 219.01 264.455 219.74 ; + RECT 264.91 219.01 265.11 219.74 ; + RECT 265.32 219.01 265.68 219.74 ; + RECT 265.975 219.01 266.175 219.74 ; + RECT 266.47 219.01 266.83 219.74 ; + RECT 266.71 0.52 266.97 14.115 ; + RECT 267.04 219.01 267.24 219.74 ; + RECT 267.22 0.52 267.48 13.45 ; + RECT 267.695 219.01 267.895 219.74 ; + RECT 268.24 0.155 269.01 0.445 ; + RECT 268.24 0.155 268.5 8.665 ; + RECT 268.75 0.155 269.01 8.665 ; + RECT 267.73 0.52 267.99 11.315 ; + RECT 268.105 219.01 268.465 219.74 ; + RECT 268.675 219.01 268.875 219.74 ; + RECT 269.26 0.52 269.52 9.955 ; + RECT 269.33 219.01 269.53 219.74 ; + RECT 269.74 219.01 270.1 219.74 ; + RECT 270.395 219.01 270.595 219.74 ; + RECT 270.89 219.01 271.25 219.74 ; + RECT 271.3 0.3 271.56 8.7 ; + RECT 271.46 219.01 271.66 219.74 ; + RECT 272.115 219.01 272.315 219.74 ; + RECT 271.81 0.18 272.58 0.88 ; + RECT 272.525 219.01 272.885 219.74 ; + RECT 273.095 219.01 273.295 219.74 ; + RECT 273.75 219.01 273.95 219.74 ; + RECT 274.005 0.52 274.265 6.28 ; + RECT 274.16 219.01 274.52 219.74 ; + RECT 274.815 219.01 275.015 219.74 ; + RECT 275.38 0.52 275.64 5.57 ; + RECT 275.31 219.01 275.67 219.74 ; + RECT 275.88 219.01 276.08 219.74 ; + RECT 275.89 0.3 276.15 5.235 ; + RECT 276.4 0.52 276.66 7.78 ; + RECT 276.535 219.01 276.735 219.74 ; + RECT 276.945 219.01 277.305 219.74 ; + RECT 277.25 0.52 277.51 4.315 ; + RECT 277.515 219.01 277.715 219.74 ; + RECT 278.17 219.01 278.37 219.74 ; + RECT 278.425 0.52 278.685 2.82 ; + RECT 278.58 219.01 278.94 219.74 ; + RECT 279.235 219.01 279.435 219.74 ; + RECT 279.73 219.01 280.09 219.74 ; + RECT 280.665 0.18 281.435 0.88 ; + RECT 280.665 0.18 280.925 12.9 ; + RECT 281.175 0.18 281.435 12.9 ; + RECT 279.955 0.52 280.215 2.82 ; + RECT 280.3 219.01 280.5 219.74 ; + RECT 281.685 0.155 282.455 0.445 ; + RECT 281.685 0.155 281.945 13.21 ; + RECT 282.195 0.155 282.455 13.21 ; + RECT 280.955 219.01 281.155 219.74 ; + RECT 281.365 219.01 281.725 219.74 ; + RECT 281.935 219.01 282.135 219.74 ; + RECT 282.59 219.01 282.79 219.74 ; + RECT 283 219.01 283.36 219.74 ; + RECT 283.655 219.01 283.855 219.74 ; + RECT 284.15 219.01 284.51 219.74 ; + RECT 284.39 0.52 284.65 14.115 ; + RECT 284.72 219.01 284.92 219.74 ; + RECT 284.9 0.52 285.16 13.45 ; + RECT 285.375 219.01 285.575 219.74 ; + RECT 285.92 0.155 286.69 0.445 ; + RECT 285.92 0.155 286.18 8.665 ; + RECT 286.43 0.155 286.69 8.665 ; + RECT 285.41 0.52 285.67 11.315 ; + RECT 285.785 219.01 286.145 219.74 ; + RECT 286.355 219.01 286.555 219.74 ; + RECT 286.94 0.52 287.2 9.955 ; + RECT 287.01 219.01 287.21 219.74 ; + RECT 287.42 219.01 287.78 219.74 ; + RECT 288.075 219.01 288.275 219.74 ; + RECT 288.57 219.01 288.93 219.74 ; + RECT 288.98 0.3 289.24 8.7 ; + RECT 289.14 219.01 289.34 219.74 ; + RECT 289.795 219.01 289.995 219.74 ; + RECT 289.49 0.18 290.26 0.88 ; + RECT 290.205 219.01 290.565 219.74 ; + RECT 290.775 219.01 290.975 219.74 ; + RECT 291.43 219.01 291.63 219.74 ; + RECT 291.685 0.52 291.945 6.28 ; + RECT 291.84 219.01 292.2 219.74 ; + RECT 292.495 219.01 292.695 219.74 ; + RECT 293.06 0.52 293.32 5.57 ; + RECT 292.99 219.01 293.35 219.74 ; + RECT 293.56 219.01 293.76 219.74 ; + RECT 293.57 0.3 293.83 5.235 ; + RECT 294.08 0.52 294.34 7.78 ; + RECT 294.215 219.01 294.415 219.74 ; + RECT 294.625 219.01 294.985 219.74 ; + RECT 294.93 0.52 295.19 4.315 ; + RECT 295.195 219.01 295.395 219.74 ; + RECT 295.85 219.01 296.05 219.74 ; + RECT 296.105 0.52 296.365 2.82 ; + RECT 296.26 219.01 296.62 219.74 ; + RECT 296.915 219.01 297.115 219.74 ; + RECT 297.41 219.01 297.77 219.74 ; + RECT 298.345 0.18 299.115 0.88 ; + RECT 298.345 0.18 298.605 12.9 ; + RECT 298.855 0.18 299.115 12.9 ; + RECT 297.635 0.52 297.895 2.82 ; + RECT 297.98 219.01 298.18 219.74 ; + RECT 299.365 0.155 300.135 0.445 ; + RECT 299.365 0.155 299.625 13.21 ; + RECT 299.875 0.155 300.135 13.21 ; + RECT 298.635 219.01 298.835 219.74 ; + RECT 299.045 219.01 299.405 219.74 ; + RECT 299.615 219.01 299.815 219.74 ; + RECT 300.27 219.01 300.47 219.74 ; + RECT 300.68 219.01 301.04 219.74 ; + RECT 301.335 219.01 301.535 219.74 ; + RECT 301.83 219.01 302.19 219.74 ; + RECT 302.07 0.52 302.33 14.115 ; + RECT 302.4 219.01 302.6 219.74 ; + RECT 302.58 0.52 302.84 13.45 ; + RECT 303.055 219.01 303.255 219.74 ; + RECT 303.6 0.155 304.37 0.445 ; + RECT 303.6 0.155 303.86 8.665 ; + RECT 304.11 0.155 304.37 8.665 ; + RECT 303.09 0.52 303.35 11.315 ; + RECT 303.465 219.01 303.825 219.74 ; + RECT 304.035 219.01 304.235 219.74 ; + RECT 304.62 0.52 304.88 9.955 ; + RECT 304.69 219.01 304.89 219.74 ; + RECT 305.1 219.01 305.46 219.74 ; + RECT 305.755 219.01 305.955 219.74 ; + RECT 306.25 219.01 306.61 219.74 ; + RECT 306.66 0.3 306.92 8.7 ; + RECT 306.82 219.01 307.02 219.74 ; + RECT 307.475 219.01 307.675 219.74 ; + RECT 307.17 0.18 307.94 0.88 ; + RECT 307.885 219.01 308.245 219.74 ; + RECT 308.455 219.01 308.655 219.74 ; + RECT 309.11 219.01 309.31 219.74 ; + RECT 309.365 0.52 309.625 6.28 ; + RECT 309.52 219.01 309.88 219.74 ; + RECT 310.175 219.01 310.375 219.74 ; + RECT 310.74 0.52 311 5.57 ; + RECT 310.67 219.01 311.03 219.74 ; + RECT 311.24 219.01 311.44 219.74 ; + RECT 311.25 0.3 311.51 5.235 ; + RECT 311.76 0.52 312.02 7.78 ; + RECT 311.895 219.01 312.095 219.74 ; + RECT 312.305 219.01 312.665 219.74 ; + RECT 312.61 0.52 312.87 4.315 ; + RECT 312.875 219.01 313.075 219.74 ; + RECT 313.53 219.01 313.73 219.74 ; + RECT 313.785 0.52 314.045 2.82 ; + RECT 313.94 219.01 314.3 219.74 ; + RECT 314.595 219.01 314.795 219.74 ; + RECT 315.09 219.01 315.45 219.74 ; + RECT 316.025 0.18 316.795 0.88 ; + RECT 316.025 0.18 316.285 12.9 ; + RECT 316.535 0.18 316.795 12.9 ; + RECT 315.315 0.52 315.575 2.82 ; + RECT 315.66 219.01 315.86 219.74 ; + RECT 317.045 0.155 317.815 0.445 ; + RECT 317.045 0.155 317.305 13.21 ; + RECT 317.555 0.155 317.815 13.21 ; + RECT 316.315 219.01 316.515 219.74 ; + RECT 316.725 219.01 317.085 219.74 ; + RECT 317.295 219.01 317.495 219.74 ; + RECT 317.95 219.01 318.15 219.74 ; + RECT 318.36 219.01 318.72 219.74 ; + RECT 319.015 219.01 319.215 219.74 ; + RECT 319.51 219.01 319.87 219.74 ; + RECT 319.75 0.52 320.01 14.115 ; + RECT 320.08 219.01 320.28 219.74 ; + RECT 320.26 0.52 320.52 13.45 ; + RECT 320.735 219.01 320.935 219.74 ; + RECT 321.28 0.155 322.05 0.445 ; + RECT 321.28 0.155 321.54 8.665 ; + RECT 321.79 0.155 322.05 8.665 ; + RECT 320.77 0.52 321.03 11.315 ; + RECT 321.145 219.01 321.505 219.74 ; + RECT 321.715 219.01 321.915 219.74 ; + RECT 322.3 0.52 322.56 9.955 ; + RECT 322.37 219.01 322.57 219.74 ; + RECT 322.78 219.01 323.14 219.74 ; + RECT 323.435 219.01 323.635 219.74 ; + RECT 323.93 219.01 324.29 219.74 ; + RECT 324.34 0.3 324.6 8.7 ; + RECT 324.5 219.01 324.7 219.74 ; + RECT 325.155 219.01 325.355 219.74 ; + RECT 324.85 0.18 325.62 0.88 ; + RECT 325.565 219.01 325.925 219.74 ; + RECT 326.135 219.01 326.335 219.74 ; + RECT 326.79 219.01 326.99 219.74 ; + RECT 327.045 0.52 327.305 6.28 ; + RECT 327.2 219.01 327.56 219.74 ; + RECT 327.855 219.01 328.055 219.74 ; + RECT 328.42 0.52 328.68 5.57 ; + RECT 328.35 219.01 328.71 219.74 ; + RECT 328.92 219.01 329.12 219.74 ; + RECT 328.93 0.3 329.19 5.235 ; + RECT 329.44 0.52 329.7 7.78 ; + RECT 329.575 219.01 329.775 219.74 ; + RECT 329.985 219.01 330.345 219.74 ; + RECT 330.29 0.52 330.55 4.315 ; + RECT 330.555 219.01 330.755 219.74 ; + RECT 331.21 219.01 331.41 219.74 ; + RECT 331.465 0.52 331.725 2.82 ; + RECT 331.62 219.01 331.98 219.74 ; + RECT 332.275 219.01 332.475 219.74 ; + RECT 332.77 219.01 333.13 219.74 ; + RECT 333.705 0.18 334.475 0.88 ; + RECT 333.705 0.18 333.965 12.9 ; + RECT 334.215 0.18 334.475 12.9 ; + RECT 332.995 0.52 333.255 2.82 ; + RECT 333.34 219.01 333.54 219.74 ; + RECT 334.725 0.155 335.495 0.445 ; + RECT 334.725 0.155 334.985 13.21 ; + RECT 335.235 0.155 335.495 13.21 ; + RECT 333.995 219.01 334.195 219.74 ; + RECT 334.405 219.01 334.765 219.74 ; + RECT 334.975 219.01 335.175 219.74 ; + RECT 335.63 219.01 335.83 219.74 ; + RECT 336.04 219.01 336.4 219.74 ; + RECT 336.695 219.01 336.895 219.74 ; + RECT 337.19 219.01 337.55 219.74 ; + RECT 337.43 0.52 337.69 14.115 ; + RECT 337.76 219.01 337.96 219.74 ; + RECT 337.94 0.52 338.2 13.45 ; + RECT 338.415 219.01 338.615 219.74 ; + RECT 338.96 0.155 339.73 0.445 ; + RECT 338.96 0.155 339.22 8.665 ; + RECT 339.47 0.155 339.73 8.665 ; + RECT 338.45 0.52 338.71 11.315 ; + RECT 338.825 219.01 339.185 219.74 ; + RECT 339.395 219.01 339.595 219.74 ; + RECT 339.98 0.52 340.24 9.955 ; + RECT 340.05 219.01 340.25 219.74 ; + RECT 340.46 219.01 340.82 219.74 ; + RECT 341.115 219.01 341.315 219.74 ; + RECT 341.61 219.01 341.97 219.74 ; + RECT 342.02 0.3 342.28 8.7 ; + RECT 342.18 219.01 342.38 219.74 ; + RECT 342.835 219.01 343.035 219.74 ; + RECT 342.53 0.18 343.3 0.88 ; + RECT 343.245 219.01 343.605 219.74 ; + RECT 343.815 219.01 344.015 219.74 ; + RECT 344.47 219.01 344.67 219.74 ; + RECT 344.725 0.52 344.985 6.28 ; + RECT 344.88 219.01 345.24 219.74 ; + RECT 345.535 219.01 345.735 219.74 ; + RECT 346.1 0.52 346.36 5.57 ; + RECT 346.03 219.01 346.39 219.74 ; + RECT 346.6 219.01 346.8 219.74 ; + RECT 346.61 0.3 346.87 5.235 ; + RECT 347.12 0.52 347.38 7.78 ; + RECT 347.255 219.01 347.455 219.74 ; + RECT 347.665 219.01 348.025 219.74 ; + RECT 347.97 0.52 348.23 4.315 ; + RECT 348.235 219.01 348.435 219.74 ; + RECT 348.89 219.01 349.09 219.74 ; + RECT 349.145 0.52 349.405 2.82 ; + RECT 349.3 219.01 349.66 219.74 ; + RECT 349.955 219.01 350.155 219.74 ; + RECT 350.45 219.01 350.81 219.74 ; + RECT 351.385 0.18 352.155 0.88 ; + RECT 351.385 0.18 351.645 12.9 ; + RECT 351.895 0.18 352.155 12.9 ; + RECT 350.675 0.52 350.935 2.82 ; + RECT 351.02 219.01 351.22 219.74 ; + RECT 352.405 0.155 353.175 0.445 ; + RECT 352.405 0.155 352.665 13.21 ; + RECT 352.915 0.155 353.175 13.21 ; + RECT 351.675 219.01 351.875 219.74 ; + RECT 352.085 219.01 352.445 219.74 ; + RECT 352.655 219.01 352.855 219.74 ; + RECT 353.31 219.01 353.51 219.74 ; + RECT 353.72 219.01 354.08 219.74 ; + RECT 354.375 219.01 354.575 219.74 ; + RECT 354.87 219.01 355.23 219.74 ; + RECT 355.11 0.52 355.37 14.115 ; + RECT 355.44 219.01 355.64 219.74 ; + RECT 355.62 0.52 355.88 13.45 ; + RECT 356.095 219.01 356.295 219.74 ; + RECT 356.64 0.155 357.41 0.445 ; + RECT 356.64 0.155 356.9 8.665 ; + RECT 357.15 0.155 357.41 8.665 ; + RECT 356.13 0.52 356.39 11.315 ; + RECT 356.505 219.01 356.865 219.74 ; + RECT 357.075 219.01 357.275 219.74 ; + RECT 357.66 0.52 357.92 9.955 ; + RECT 357.73 219.01 357.93 219.74 ; + RECT 358.14 219.01 358.5 219.74 ; + RECT 358.795 219.01 358.995 219.74 ; + RECT 359.29 219.01 359.65 219.74 ; + RECT 359.7 0.3 359.96 8.7 ; + RECT 359.86 219.01 360.06 219.74 ; + RECT 360.515 219.01 360.715 219.74 ; + RECT 360.21 0.18 360.98 0.88 ; + RECT 360.925 219.01 361.285 219.74 ; + RECT 361.495 219.01 361.695 219.74 ; + RECT 362.15 219.01 362.35 219.74 ; + RECT 362.405 0.52 362.665 6.28 ; + RECT 362.56 219.01 362.92 219.74 ; + RECT 363.215 219.01 363.415 219.74 ; + RECT 363.78 0.52 364.04 5.57 ; + RECT 363.71 219.01 364.07 219.74 ; + RECT 364.28 219.01 364.48 219.74 ; + RECT 364.29 0.3 364.55 5.235 ; + RECT 364.8 0.52 365.06 7.78 ; + RECT 364.935 219.01 365.135 219.74 ; + RECT 365.345 219.01 365.705 219.74 ; + RECT 365.65 0.52 365.91 4.315 ; + RECT 365.915 219.01 366.115 219.74 ; + RECT 366.57 219.01 366.77 219.74 ; + RECT 366.825 0.52 367.085 2.82 ; + RECT 366.98 219.01 367.34 219.74 ; + RECT 367.635 219.01 367.835 219.74 ; + RECT 368.13 219.01 368.49 219.74 ; + RECT 369.065 0.18 369.835 0.88 ; + RECT 369.065 0.18 369.325 12.9 ; + RECT 369.575 0.18 369.835 12.9 ; + RECT 368.355 0.52 368.615 2.82 ; + RECT 368.7 219.01 368.9 219.74 ; + RECT 370.085 0.155 370.855 0.445 ; + RECT 370.085 0.155 370.345 13.21 ; + RECT 370.595 0.155 370.855 13.21 ; + RECT 369.355 219.01 369.555 219.74 ; + RECT 369.765 219.01 370.125 219.74 ; + RECT 370.335 219.01 370.535 219.74 ; + RECT 370.99 219.01 371.19 219.74 ; + RECT 371.4 219.01 371.76 219.74 ; + RECT 372.055 219.01 372.255 219.74 ; + RECT 372.55 219.01 372.91 219.74 ; + RECT 372.79 0.52 373.05 14.115 ; + RECT 373.12 219.01 373.32 219.74 ; + RECT 373.3 0.52 373.56 13.45 ; + RECT 373.775 219.01 373.975 219.74 ; + RECT 374.32 0.155 375.09 0.445 ; + RECT 374.32 0.155 374.58 8.665 ; + RECT 374.83 0.155 375.09 8.665 ; + RECT 373.81 0.52 374.07 11.315 ; + RECT 374.185 219.01 374.545 219.74 ; + RECT 374.755 219.01 374.955 219.74 ; + RECT 375.34 0.52 375.6 9.955 ; + RECT 375.41 219.01 375.61 219.74 ; + RECT 375.82 219.01 376.18 219.74 ; + RECT 376.475 219.01 376.675 219.74 ; + RECT 376.97 219.01 377.33 219.74 ; + RECT 377.38 0.3 377.64 8.7 ; + RECT 377.54 219.01 377.74 219.74 ; + RECT 378.195 219.01 378.395 219.74 ; + RECT 377.89 0.18 378.66 0.88 ; + RECT 378.605 219.01 378.965 219.74 ; + RECT 379.175 219.01 379.375 219.74 ; + RECT 379.83 219.01 380.03 219.74 ; + RECT 380.085 0.52 380.345 6.28 ; + RECT 380.24 219.01 380.6 219.74 ; + RECT 380.895 219.01 381.095 219.74 ; + RECT 381.46 0.52 381.72 5.57 ; + RECT 381.39 219.01 381.75 219.74 ; + RECT 381.96 219.01 382.16 219.74 ; + RECT 381.97 0.3 382.23 5.235 ; + RECT 382.48 0.52 382.74 7.78 ; + RECT 382.615 219.01 382.815 219.74 ; + RECT 383.025 219.01 383.385 219.74 ; + RECT 383.33 0.52 383.59 4.315 ; + RECT 383.595 219.01 383.795 219.74 ; + RECT 384.25 219.01 384.45 219.74 ; + RECT 384.505 0.52 384.765 2.82 ; + RECT 384.66 219.01 385.02 219.74 ; + RECT 385.315 219.01 385.515 219.74 ; + RECT 385.81 219.01 386.17 219.74 ; + RECT 386.745 0.18 387.515 0.88 ; + RECT 386.745 0.18 387.005 12.9 ; + RECT 387.255 0.18 387.515 12.9 ; + RECT 386.035 0.52 386.295 2.82 ; + RECT 386.38 219.01 386.58 219.74 ; + RECT 387.765 0.155 388.535 0.445 ; + RECT 387.765 0.155 388.025 13.21 ; + RECT 388.275 0.155 388.535 13.21 ; + RECT 387.035 219.01 387.235 219.74 ; + RECT 387.445 219.01 387.805 219.74 ; + RECT 388.015 219.01 388.215 219.74 ; + RECT 388.67 219.01 388.87 219.74 ; + RECT 389.08 219.01 389.44 219.74 ; + RECT 389.735 219.01 389.935 219.74 ; + RECT 390.23 219.01 390.59 219.74 ; + RECT 390.47 0.52 390.73 14.115 ; + RECT 390.8 219.01 391 219.74 ; + RECT 390.98 0.52 391.24 13.45 ; + RECT 391.455 219.01 391.655 219.74 ; + RECT 392 0.155 392.77 0.445 ; + RECT 392 0.155 392.26 8.665 ; + RECT 392.51 0.155 392.77 8.665 ; + RECT 391.49 0.52 391.75 11.315 ; + RECT 391.865 219.01 392.225 219.74 ; + RECT 392.435 219.01 392.635 219.74 ; + RECT 393.02 0.52 393.28 9.955 ; + RECT 393.09 219.01 393.29 219.74 ; + RECT 393.5 219.01 393.86 219.74 ; + RECT 394.155 219.01 394.355 219.74 ; + RECT 394.65 219.01 395.01 219.74 ; + RECT 395.06 0.3 395.32 8.7 ; + RECT 395.22 219.01 395.42 219.74 ; + RECT 395.875 219.01 396.075 219.74 ; + RECT 395.57 0.18 396.34 0.88 ; + RECT 396.285 219.01 396.645 219.74 ; + RECT 396.855 219.01 397.055 219.74 ; + RECT 397.51 219.01 397.71 219.74 ; + RECT 397.765 0.52 398.025 6.28 ; + RECT 397.92 219.01 398.28 219.74 ; + RECT 398.575 219.01 398.775 219.74 ; + RECT 399.14 0.52 399.4 5.57 ; + RECT 399.07 219.01 399.43 219.74 ; + RECT 399.64 219.01 399.84 219.74 ; + RECT 399.65 0.3 399.91 5.235 ; + RECT 400.16 0.52 400.42 7.78 ; + RECT 400.295 219.01 400.495 219.74 ; + RECT 400.705 219.01 401.065 219.74 ; + RECT 401.275 219.01 401.475 219.74 ; + RECT 402.1 53.41 402.3 219.74 ; + LAYER Metal2 SPACING 0.21 ; + RECT 400.68 0 402.61 219.77 ; + RECT 0 0.52 402.61 219.77 ; + RECT 399.65 0.3 399.91 219.77 ; + RECT 398.285 0 398.88 219.77 ; + RECT 393.54 0 397.505 219.77 ; + RECT 392 0.155 392.77 219.77 ; + RECT 386.555 0 390.21 219.77 ; + RECT 385.025 0 385.775 219.77 ; + RECT 383.85 0 384.245 219.77 ; + RECT 381.97 0.3 382.23 219.77 ; + RECT 380.605 0 381.2 219.77 ; + RECT 375.86 0 379.825 219.77 ; + RECT 374.32 0.155 375.09 219.77 ; + RECT 368.875 0 372.53 219.77 ; + RECT 367.345 0 368.095 219.77 ; + RECT 366.17 0 366.565 219.77 ; + RECT 364.29 0.3 364.55 219.77 ; + RECT 362.925 0 363.52 219.77 ; + RECT 358.18 0 362.145 219.77 ; + RECT 356.64 0.155 357.41 219.77 ; + RECT 351.195 0 354.85 219.77 ; + RECT 349.665 0 350.415 219.77 ; + RECT 348.49 0 348.885 219.77 ; + RECT 346.61 0.3 346.87 219.77 ; + RECT 345.245 0 345.84 219.77 ; + RECT 340.5 0 344.465 219.77 ; + RECT 338.96 0.155 339.73 219.77 ; + RECT 333.515 0 337.17 219.77 ; + RECT 331.985 0 332.735 219.77 ; + RECT 330.81 0 331.205 219.77 ; + RECT 328.93 0.3 329.19 219.77 ; + RECT 327.565 0 328.16 219.77 ; + RECT 322.82 0 326.785 219.77 ; + RECT 321.28 0.155 322.05 219.77 ; + RECT 315.835 0 319.49 219.77 ; + RECT 314.305 0 315.055 219.77 ; + RECT 313.13 0 313.525 219.77 ; + RECT 311.25 0.3 311.51 219.77 ; + RECT 309.885 0 310.48 219.77 ; + RECT 305.14 0 309.105 219.77 ; + RECT 303.6 0.155 304.37 219.77 ; + RECT 298.155 0 301.81 219.77 ; + RECT 296.625 0 297.375 219.77 ; + RECT 295.45 0 295.845 219.77 ; + RECT 293.57 0.3 293.83 219.77 ; + RECT 292.205 0 292.8 219.77 ; + RECT 287.46 0 291.425 219.77 ; + RECT 285.92 0.155 286.69 219.77 ; + RECT 280.475 0 284.13 219.77 ; + RECT 278.945 0 279.695 219.77 ; + RECT 277.77 0 278.165 219.77 ; + RECT 275.89 0.3 276.15 219.77 ; + RECT 274.525 0 275.12 219.77 ; + RECT 269.78 0 273.745 219.77 ; + RECT 268.24 0.155 269.01 219.77 ; + RECT 262.795 0 266.45 219.77 ; + RECT 261.265 0 262.015 219.77 ; + RECT 260.09 0 260.485 219.77 ; + RECT 237.285 0.18 259.31 219.77 ; + RECT 237.295 0 259.31 219.77 ; + RECT 232.695 0.3 236.525 219.77 ; + RECT 229.635 0.18 231.425 219.77 ; + RECT 224.025 0.3 225.305 219.77 ; + RECT 221.475 0.3 222.755 219.77 ; + RECT 219.945 0.3 220.205 219.77 ; + RECT 216.885 0.3 217.145 219.77 ; + RECT 215.355 0.3 215.615 219.77 ; + RECT 207.195 0.3 214.085 219.77 ; + RECT 197.705 0 204.905 219.77 ; + RECT 188.525 0.3 195.415 219.77 ; + RECT 188.535 0 195.415 219.77 ; + RECT 186.995 0.3 187.255 219.77 ; + RECT 185.465 0.3 185.725 219.77 ; + RECT 182.405 0.3 182.665 219.77 ; + RECT 179.855 0.3 181.135 219.77 ; + RECT 177.305 0.3 178.585 219.77 ; + RECT 171.185 0.18 172.975 219.77 ; + RECT 171.195 0 172.975 219.77 ; + RECT 166.085 0.3 169.915 219.77 ; + RECT 143.3 0.18 165.325 219.77 ; + RECT 142.125 0 142.52 219.77 ; + RECT 140.595 0 141.345 219.77 ; + RECT 136.16 0 139.815 219.77 ; + RECT 133.6 0.155 134.37 219.77 ; + RECT 128.865 0 132.83 219.77 ; + RECT 127.49 0 128.085 219.77 ; + RECT 126.46 0.3 126.72 219.77 ; + RECT 124.445 0 124.84 219.77 ; + RECT 122.915 0 123.665 219.77 ; + RECT 118.48 0 122.135 219.77 ; + RECT 115.92 0.155 116.69 219.77 ; + RECT 111.185 0 115.15 219.77 ; + RECT 109.81 0 110.405 219.77 ; + RECT 108.78 0.3 109.04 219.77 ; + RECT 106.765 0 107.16 219.77 ; + RECT 105.235 0 105.985 219.77 ; + RECT 100.8 0 104.455 219.77 ; + RECT 98.24 0.155 99.01 219.77 ; + RECT 93.505 0 97.47 219.77 ; + RECT 92.13 0 92.725 219.77 ; + RECT 91.1 0.3 91.36 219.77 ; + RECT 89.085 0 89.48 219.77 ; + RECT 87.555 0 88.305 219.77 ; + RECT 83.12 0 86.775 219.77 ; + RECT 80.56 0.155 81.33 219.77 ; + RECT 75.825 0 79.79 219.77 ; + RECT 74.45 0 75.045 219.77 ; + RECT 73.42 0.3 73.68 219.77 ; + RECT 71.405 0 71.8 219.77 ; + RECT 69.875 0 70.625 219.77 ; + RECT 65.44 0 69.095 219.77 ; + RECT 62.88 0.155 63.65 219.77 ; + RECT 58.145 0 62.11 219.77 ; + RECT 56.77 0 57.365 219.77 ; + RECT 55.74 0.3 56 219.77 ; + RECT 53.725 0 54.12 219.77 ; + RECT 52.195 0 52.945 219.77 ; + RECT 47.76 0 51.415 219.77 ; + RECT 45.2 0.155 45.97 219.77 ; + RECT 40.465 0 44.43 219.77 ; + RECT 39.09 0 39.685 219.77 ; + RECT 38.06 0.3 38.32 219.77 ; + RECT 36.045 0 36.44 219.77 ; + RECT 34.515 0 35.265 219.77 ; + RECT 30.08 0 33.735 219.77 ; + RECT 27.52 0.155 28.29 219.77 ; + RECT 22.785 0 26.75 219.77 ; + RECT 21.41 0 22.005 219.77 ; + RECT 20.38 0.3 20.64 219.77 ; + RECT 18.365 0 18.76 219.77 ; + RECT 16.835 0 17.585 219.77 ; + RECT 12.4 0 16.055 219.77 ; + RECT 9.84 0.155 10.61 219.77 ; + RECT 5.105 0 9.07 219.77 ; + RECT 3.73 0 4.325 219.77 ; + RECT 2.7 0.3 2.96 219.77 ; + RECT 0 0 1.93 219.77 ; + RECT 399.66 0 399.9 219.77 ; + RECT 381.98 0 382.22 219.77 ; + RECT 364.3 0 364.54 219.77 ; + RECT 346.62 0 346.86 219.77 ; + RECT 328.94 0 329.18 219.77 ; + RECT 311.26 0 311.5 219.77 ; + RECT 293.58 0 293.82 219.77 ; + RECT 275.9 0 276.14 219.77 ; + RECT 232.705 0 236.515 219.77 ; + RECT 224.035 0 225.295 219.77 ; + RECT 221.485 0 222.745 219.77 ; + RECT 219.955 0 220.195 219.77 ; + RECT 216.895 0 217.135 219.77 ; + RECT 215.365 0 215.605 219.77 ; + RECT 207.195 0 214.075 219.77 ; + RECT 187.005 0 187.245 219.77 ; + RECT 185.475 0 185.715 219.77 ; + RECT 182.415 0 182.655 219.77 ; + RECT 179.865 0 181.125 219.77 ; + RECT 177.315 0 178.575 219.77 ; + RECT 166.095 0 169.905 219.77 ; + RECT 126.47 0 126.71 219.77 ; + RECT 108.79 0 109.03 219.77 ; + RECT 91.11 0 91.35 219.77 ; + RECT 73.43 0 73.67 219.77 ; + RECT 55.75 0 55.99 219.77 ; + RECT 38.07 0 38.31 219.77 ; + RECT 20.39 0 20.63 219.77 ; + RECT 2.71 0 2.95 219.77 ; + RECT 229.635 0 231.415 219.77 ; + RECT 143.3 0 165.315 219.77 ; + RECT 392.01 0 392.76 219.77 ; + RECT 374.33 0 375.08 219.77 ; + RECT 356.65 0 357.4 219.77 ; + RECT 338.97 0 339.72 219.77 ; + RECT 321.29 0 322.04 219.77 ; + RECT 303.61 0 304.36 219.77 ; + RECT 285.93 0 286.68 219.77 ; + RECT 268.25 0 269 219.77 ; + RECT 133.61 0 134.36 219.77 ; + RECT 115.93 0 116.68 219.77 ; + RECT 98.25 0 99 219.77 ; + RECT 80.57 0 81.32 219.77 ; + RECT 62.89 0 63.64 219.77 ; + RECT 45.21 0 45.96 219.77 ; + RECT 27.53 0 28.28 219.77 ; + RECT 9.85 0 10.6 219.77 ; + LAYER Metal3 ; + RECT 0 0 402.61 219.77 ; + LAYER Metal4 SPACING 0.21 ; + RECT 241.595 0 259.185 219.77 ; + RECT 236.445 0 238.265 219.77 ; + RECT 231.295 0 233.115 219.77 ; + RECT 396.725 0 402.61 219.77 ; + RECT 387.885 0 391.785 219.77 ; + RECT 387.885 47.305 402.61 53.15 ; + RECT 379.045 0 382.945 219.77 ; + RECT 370.205 0 374.105 219.77 ; + RECT 370.205 47.305 382.945 53.15 ; + RECT 361.365 0 365.265 219.77 ; + RECT 352.525 0 356.425 219.77 ; + RECT 352.525 47.305 365.265 53.15 ; + RECT 343.685 0 347.585 219.77 ; + RECT 334.845 0 338.745 219.77 ; + RECT 334.845 47.305 347.585 53.15 ; + RECT 326.005 0 329.905 219.77 ; + RECT 317.165 0 321.065 219.77 ; + RECT 317.165 47.305 329.905 53.15 ; + RECT 308.325 0 312.225 219.77 ; + RECT 299.485 0 303.385 219.77 ; + RECT 299.485 47.305 312.225 53.15 ; + RECT 290.645 0 294.545 219.77 ; + RECT 281.805 0 285.705 219.77 ; + RECT 281.805 47.305 294.545 53.15 ; + RECT 272.965 0 276.865 219.77 ; + RECT 264.125 0 268.025 219.77 ; + RECT 264.125 47.305 276.865 53.15 ; + RECT 226.145 0 227.965 219.77 ; + RECT 220.995 0 222.815 219.77 ; + RECT 215.845 0 217.665 219.77 ; + RECT 210.695 0 212.515 219.77 ; + RECT 205.545 0 207.365 219.77 ; + RECT 200.395 0 202.215 219.77 ; + RECT 195.245 0 197.065 219.77 ; + RECT 190.095 0 191.915 219.77 ; + RECT 184.945 0 186.765 219.77 ; + RECT 179.795 0 181.615 219.77 ; + RECT 174.645 0 176.465 219.77 ; + RECT 169.495 0 171.315 219.77 ; + RECT 164.345 0 166.165 219.77 ; + RECT 143.425 0 161.015 219.77 ; + RECT 134.585 0 138.485 219.77 ; + RECT 125.745 0 129.645 219.77 ; + RECT 125.745 47.305 138.485 53.15 ; + RECT 116.905 0 120.805 219.77 ; + RECT 108.065 0 111.965 219.77 ; + RECT 108.065 47.305 120.805 53.15 ; + RECT 99.225 0 103.125 219.77 ; + RECT 90.385 0 94.285 219.77 ; + RECT 90.385 47.305 103.125 53.15 ; + RECT 81.545 0 85.445 219.77 ; + RECT 72.705 0 76.605 219.77 ; + RECT 72.705 47.305 85.445 53.15 ; + RECT 63.865 0 67.765 219.77 ; + RECT 55.025 0 58.925 219.77 ; + RECT 55.025 47.305 67.765 53.15 ; + RECT 46.185 0 50.085 219.77 ; + RECT 37.345 0 41.245 219.77 ; + RECT 37.345 47.305 50.085 53.15 ; + RECT 28.505 0 32.405 219.77 ; + RECT 19.665 0 23.565 219.77 ; + RECT 19.665 47.305 32.405 53.15 ; + RECT 10.825 0 14.725 219.77 ; + RECT 0 0 5.885 219.77 ; + RECT 0 47.305 14.725 53.15 ; + END +END RM_IHPSG13_2P_512x16_c2_bm_bist + +END LIBRARY diff --git a/flow/platforms/ihp-sg13g2/lef/RM_IHPSG13_2P_512x32_c2_bm_bist.lef b/flow/platforms/ihp-sg13g2/lef/RM_IHPSG13_2P_512x32_c2_bm_bist.lef new file mode 100644 index 0000000000..ea4437ff1f --- /dev/null +++ b/flow/platforms/ihp-sg13g2/lef/RM_IHPSG13_2P_512x32_c2_bm_bist.lef @@ -0,0 +1,7363 @@ +# ------------------------------------------------------ +# +# Copyright 2025 IHP PDK Authors +# +# Licensed under the Apache License, Version 2.0 (the "License"); +# you may not use this file except in compliance with the License. +# You may obtain a copy of the License at +# +# https://www.apache.org/licenses/LICENSE-2.0 +# +# Unless required by applicable law or agreed to in writing, software +# distributed under the License is distributed on an "AS IS" BASIS, +# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +# See the License for the specific language governing permissions and +# limitations under the License. +# +# Generated on Wed Aug 27 13:11:35 2025 +# +# ------------------------------------------------------ +VERSION 5.7 ; +BUSBITCHARS "[]" ; +DIVIDERCHAR "/" ; + +MACRO RM_IHPSG13_2P_512x32_c2_bm_bist + CLASS BLOCK ; + ORIGIN 0 0 ; + FOREIGN RM_IHPSG13_2P_512x32_c2_bm_bist 0 0 ; + SIZE 685.49 BY 219.77 ; + SYMMETRY X Y R90 ; + PIN A_DIN[16] + DIRECTION INPUT ; + USE SIGNAL ; + ANTENNAPARTIALMETALAREA 3.9091 LAYER Metal2 ; + ANTENNAMODEL OXIDE1 ; + ANTENNAGATEAREA 0.20085 LAYER Metal2 ; + ANTENNAMAXAREACAR 20.368932 LAYER Metal2 ; + PORT + LAYER Metal2 ; + RECT 408.15 0 408.41 0.26 ; + END + END A_DIN[16] + PIN A_DIN[15] + DIRECTION INPUT ; + USE SIGNAL ; + ANTENNAPARTIALMETALAREA 3.9091 LAYER Metal2 ; + ANTENNAMODEL OXIDE1 ; + ANTENNAGATEAREA 0.20085 LAYER Metal2 ; + ANTENNAMAXAREACAR 20.368932 LAYER Metal2 ; + PORT + LAYER Metal2 ; + RECT 277.08 0 277.34 0.26 ; + END + END A_DIN[15] + PIN A_BIST_DIN[16] + DIRECTION INPUT ; + USE SIGNAL ; + ANTENNAPARTIALMETALAREA 4.136375 LAYER Metal2 ; + ANTENNAMODEL OXIDE1 ; + ANTENNAGATEAREA 0.20085 LAYER Metal2 ; + ANTENNAMAXAREACAR 21.874907 LAYER Metal2 ; + PORT + LAYER Metal2 ; + RECT 408.66 0 408.92 0.26 ; + END + END A_BIST_DIN[16] + PIN A_BIST_DIN[15] + DIRECTION INPUT ; + USE SIGNAL ; + ANTENNAPARTIALMETALAREA 4.136375 LAYER Metal2 ; + ANTENNAMODEL OXIDE1 ; + ANTENNAGATEAREA 0.20085 LAYER Metal2 ; + ANTENNAMAXAREACAR 21.874907 LAYER Metal2 ; + PORT + LAYER Metal2 ; + RECT 276.57 0 276.83 0.26 ; + END + END A_BIST_DIN[15] + PIN A_BM[16] + DIRECTION INPUT ; + USE SIGNAL ; + ANTENNAPARTIALMETALAREA 1.7264 LAYER Metal2 ; + ANTENNAMODEL OXIDE1 ; + ANTENNAGATEAREA 0.20085 LAYER Metal2 ; + ANTENNAMAXAREACAR 9.501618 LAYER Metal2 ; + PORT + LAYER Metal2 ; + RECT 416.82 0 417.08 0.26 ; + END + END A_BM[16] + PIN A_BM[15] + DIRECTION INPUT ; + USE SIGNAL ; + ANTENNAPARTIALMETALAREA 1.7264 LAYER Metal2 ; + ANTENNAMODEL OXIDE1 ; + ANTENNAGATEAREA 0.20085 LAYER Metal2 ; + ANTENNAMAXAREACAR 9.501618 LAYER Metal2 ; + PORT + LAYER Metal2 ; + RECT 268.41 0 268.67 0.26 ; + END + END A_BM[15] + PIN A_BIST_BM[16] + DIRECTION INPUT ; + USE SIGNAL ; + ANTENNAPARTIALMETALAREA 1.7602 LAYER Metal2 ; + ANTENNAMODEL OXIDE1 ; + ANTENNAGATEAREA 0.20085 LAYER Metal2 ; + ANTENNAMAXAREACAR 9.678367 LAYER Metal2 ; + PORT + LAYER Metal2 ; + RECT 415.445 0 415.705 0.26 ; + END + END A_BIST_BM[16] + PIN A_BIST_BM[15] + DIRECTION INPUT ; + USE SIGNAL ; + ANTENNAPARTIALMETALAREA 1.7602 LAYER Metal2 ; + ANTENNAMODEL OXIDE1 ; + ANTENNAGATEAREA 0.20085 LAYER Metal2 ; + ANTENNAMAXAREACAR 9.678367 LAYER Metal2 ; + PORT + LAYER Metal2 ; + RECT 269.785 0 270.045 0.26 ; + END + END A_BIST_BM[15] + PIN A_DOUT[16] + DIRECTION OUTPUT ; + USE SIGNAL ; + ANTENNAPARTIALMETALAREA 4.8256 LAYER Metal2 ; + ANTENNADIFFAREA 0.988 LAYER Metal2 ; + PORT + LAYER Metal2 ; + RECT 401.01 0 401.27 0.26 ; + END + END A_DOUT[16] + PIN A_DOUT[15] + DIRECTION OUTPUT ; + USE SIGNAL ; + ANTENNAPARTIALMETALAREA 4.8256 LAYER Metal2 ; + ANTENNADIFFAREA 0.988 LAYER Metal2 ; + PORT + LAYER Metal2 ; + RECT 284.22 0 284.48 0.26 ; + END + END A_DOUT[15] + PIN B_DIN[16] + DIRECTION INPUT ; + USE SIGNAL ; + ANTENNAPARTIALMETALAREA 2.925 LAYER Metal2 ; + ANTENNAMODEL OXIDE1 ; + ANTENNAGATEAREA 0.20085 LAYER Metal2 ; + ANTENNAMAXAREACAR 15.469256 LAYER Metal2 ; + PORT + LAYER Metal2 ; + RECT 410.7 0 410.96 0.26 ; + END + END B_DIN[16] + PIN B_DIN[15] + DIRECTION INPUT ; + USE SIGNAL ; + ANTENNAPARTIALMETALAREA 2.925 LAYER Metal2 ; + ANTENNAMODEL OXIDE1 ; + ANTENNAGATEAREA 0.20085 LAYER Metal2 ; + ANTENNAMAXAREACAR 15.469256 LAYER Metal2 ; + PORT + LAYER Metal2 ; + RECT 274.53 0 274.79 0.26 ; + END + END B_DIN[15] + PIN B_BIST_DIN[16] + DIRECTION INPUT ; + USE SIGNAL ; + ANTENNAPARTIALMETALAREA 2.9445 LAYER Metal2 ; + ANTENNAMODEL OXIDE1 ; + ANTENNAGATEAREA 0.20085 LAYER Metal2 ; + ANTENNAMAXAREACAR 15.929052 LAYER Metal2 ; + PORT + LAYER Metal2 ; + RECT 409.17 0 409.43 0.26 ; + END + END B_BIST_DIN[16] + PIN B_BIST_DIN[15] + DIRECTION INPUT ; + USE SIGNAL ; + ANTENNAPARTIALMETALAREA 2.9445 LAYER Metal2 ; + ANTENNAMODEL OXIDE1 ; + ANTENNAGATEAREA 0.20085 LAYER Metal2 ; + ANTENNAMAXAREACAR 15.929052 LAYER Metal2 ; + PORT + LAYER Metal2 ; + RECT 276.06 0 276.32 0.26 ; + END + END B_BIST_DIN[15] + PIN B_BM[16] + DIRECTION INPUT ; + USE SIGNAL ; + ANTENNAPARTIALMETALAREA 0.7007 LAYER Metal2 ; + ANTENNAMODEL OXIDE1 ; + ANTENNAGATEAREA 0.20085 LAYER Metal2 ; + ANTENNAMAXAREACAR 4.394822 LAYER Metal2 ; + PORT + LAYER Metal2 ; + RECT 402.185 0 402.445 0.26 ; + END + END B_BM[16] + PIN B_BM[15] + DIRECTION INPUT ; + USE SIGNAL ; + ANTENNAPARTIALMETALAREA 0.7007 LAYER Metal2 ; + ANTENNAMODEL OXIDE1 ; + ANTENNAGATEAREA 0.20085 LAYER Metal2 ; + ANTENNAMAXAREACAR 4.394822 LAYER Metal2 ; + PORT + LAYER Metal2 ; + RECT 283.045 0 283.305 0.26 ; + END + END B_BM[15] + PIN B_BIST_BM[16] + DIRECTION INPUT ; + USE SIGNAL ; + ANTENNAPARTIALMETALAREA 0.7007 LAYER Metal2 ; + ANTENNAMODEL OXIDE1 ; + ANTENNAGATEAREA 0.20085 LAYER Metal2 ; + ANTENNAMAXAREACAR 4.394822 LAYER Metal2 ; + PORT + LAYER Metal2 ; + RECT 403.715 0 403.975 0.26 ; + END + END B_BIST_BM[16] + PIN B_BIST_BM[15] + DIRECTION INPUT ; + USE SIGNAL ; + ANTENNAPARTIALMETALAREA 0.7007 LAYER Metal2 ; + ANTENNAMODEL OXIDE1 ; + ANTENNAGATEAREA 0.20085 LAYER Metal2 ; + ANTENNAMAXAREACAR 4.394822 LAYER Metal2 ; + PORT + LAYER Metal2 ; + RECT 281.515 0 281.775 0.26 ; + END + END B_BIST_BM[15] + PIN B_DOUT[16] + DIRECTION OUTPUT ; + USE SIGNAL ; + ANTENNAPARTIALMETALAREA 4.836 LAYER Metal2 ; + ANTENNADIFFAREA 0.988 LAYER Metal2 ; + PORT + LAYER Metal2 ; + RECT 417.84 0 418.1 0.26 ; + END + END B_DOUT[16] + PIN B_DOUT[15] + DIRECTION OUTPUT ; + USE SIGNAL ; + ANTENNAPARTIALMETALAREA 4.836 LAYER Metal2 ; + ANTENNADIFFAREA 0.988 LAYER Metal2 ; + PORT + LAYER Metal2 ; + RECT 267.39 0 267.65 0.26 ; + END + END B_DOUT[15] + PIN VSS! + DIRECTION INOUT ; + USE GROUND ; + NETEXPR "vss VSS!" ; + PORT + LAYER Metal4 ; + RECT 666.085 0 670.505 219.77 ; + END + PORT + LAYER Metal4 ; + RECT 648.405 0 652.825 219.77 ; + END + PORT + LAYER Metal4 ; + RECT 630.725 0 635.145 219.77 ; + END + PORT + LAYER Metal4 ; + RECT 613.045 0 617.465 219.77 ; + END + PORT + LAYER Metal4 ; + RECT 595.365 0 599.785 219.77 ; + END + PORT + LAYER Metal4 ; + RECT 577.685 0 582.105 219.77 ; + END + PORT + LAYER Metal4 ; + RECT 560.005 0 564.425 219.77 ; + END + PORT + LAYER Metal4 ; + RECT 542.325 0 546.745 219.77 ; + END + PORT + LAYER Metal4 ; + RECT 524.645 0 529.065 219.77 ; + END + PORT + LAYER Metal4 ; + RECT 506.965 0 511.385 219.77 ; + END + PORT + LAYER Metal4 ; + RECT 489.285 0 493.705 219.77 ; + END + PORT + LAYER Metal4 ; + RECT 471.605 0 476.025 219.77 ; + END + PORT + LAYER Metal4 ; + RECT 453.925 0 458.345 219.77 ; + END + PORT + LAYER Metal4 ; + RECT 436.245 0 440.665 219.77 ; + END + PORT + LAYER Metal4 ; + RECT 418.565 0 422.985 219.77 ; + END + PORT + LAYER Metal4 ; + RECT 400.885 0 405.305 219.77 ; + END + PORT + LAYER Metal4 ; + RECT 379.965 0 382.775 219.77 ; + END + PORT + LAYER Metal4 ; + RECT 369.665 0 372.475 219.77 ; + END + PORT + LAYER Metal4 ; + RECT 354.215 0 357.025 219.77 ; + END + PORT + LAYER Metal4 ; + RECT 343.915 0 346.725 219.77 ; + END + PORT + LAYER Metal4 ; + RECT 338.765 0 341.575 219.77 ; + END + PORT + LAYER Metal4 ; + RECT 328.465 0 331.275 219.77 ; + END + PORT + LAYER Metal4 ; + RECT 313.015 0 315.825 219.77 ; + END + PORT + LAYER Metal4 ; + RECT 302.715 0 305.525 219.77 ; + END + PORT + LAYER Metal4 ; + RECT 280.185 0 284.605 219.77 ; + END + PORT + LAYER Metal4 ; + RECT 262.505 0 266.925 219.77 ; + END + PORT + LAYER Metal4 ; + RECT 244.825 0 249.245 219.77 ; + END + PORT + LAYER Metal4 ; + RECT 227.145 0 231.565 219.77 ; + END + PORT + LAYER Metal4 ; + RECT 209.465 0 213.885 219.77 ; + END + PORT + LAYER Metal4 ; + RECT 191.785 0 196.205 219.77 ; + END + PORT + LAYER Metal4 ; + RECT 174.105 0 178.525 219.77 ; + END + PORT + LAYER Metal4 ; + RECT 156.425 0 160.845 219.77 ; + END + PORT + LAYER Metal4 ; + RECT 138.745 0 143.165 219.77 ; + END + PORT + LAYER Metal4 ; + RECT 121.065 0 125.485 219.77 ; + END + PORT + LAYER Metal4 ; + RECT 103.385 0 107.805 219.77 ; + END + PORT + LAYER Metal4 ; + RECT 85.705 0 90.125 219.77 ; + END + PORT + LAYER Metal4 ; + RECT 68.025 0 72.445 219.77 ; + END + PORT + LAYER Metal4 ; + RECT 50.345 0 54.765 219.77 ; + END + PORT + LAYER Metal4 ; + RECT 32.665 0 37.085 219.77 ; + END + PORT + LAYER Metal4 ; + RECT 14.985 0 19.405 219.77 ; + END + END VSS! + PIN VDD! + DIRECTION INOUT ; + USE POWER ; + NETEXPR "vdd VDD!" ; + PORT + LAYER Metal4 ; + RECT 674.925 0 679.345 47.045 ; + END + PORT + LAYER Metal4 ; + RECT 657.245 0 661.665 47.045 ; + END + PORT + LAYER Metal4 ; + RECT 639.565 0 643.985 47.045 ; + END + PORT + LAYER Metal4 ; + RECT 621.885 0 626.305 47.045 ; + END + PORT + LAYER Metal4 ; + RECT 604.205 0 608.625 47.045 ; + END + PORT + LAYER Metal4 ; + RECT 586.525 0 590.945 47.045 ; + END + PORT + LAYER Metal4 ; + RECT 568.845 0 573.265 47.045 ; + END + PORT + LAYER Metal4 ; + RECT 551.165 0 555.585 47.045 ; + END + PORT + LAYER Metal4 ; + RECT 533.485 0 537.905 47.045 ; + END + PORT + LAYER Metal4 ; + RECT 515.805 0 520.225 47.045 ; + END + PORT + LAYER Metal4 ; + RECT 498.125 0 502.545 47.045 ; + END + PORT + LAYER Metal4 ; + RECT 480.445 0 484.865 47.045 ; + END + PORT + LAYER Metal4 ; + RECT 462.765 0 467.185 47.045 ; + END + PORT + LAYER Metal4 ; + RECT 445.085 0 449.505 47.045 ; + END + PORT + LAYER Metal4 ; + RECT 427.405 0 431.825 47.045 ; + END + PORT + LAYER Metal4 ; + RECT 409.725 0 414.145 47.045 ; + END + PORT + LAYER Metal4 ; + RECT 374.815 0 377.625 219.77 ; + END + PORT + LAYER Metal4 ; + RECT 364.515 0 367.325 219.77 ; + END + PORT + LAYER Metal4 ; + RECT 359.365 0 362.175 219.77 ; + END + PORT + LAYER Metal4 ; + RECT 349.065 0 351.875 219.77 ; + END + PORT + LAYER Metal4 ; + RECT 333.615 0 336.425 219.77 ; + END + PORT + LAYER Metal4 ; + RECT 323.315 0 326.125 219.77 ; + END + PORT + LAYER Metal4 ; + RECT 318.165 0 320.975 219.77 ; + END + PORT + LAYER Metal4 ; + RECT 307.865 0 310.675 219.77 ; + END + PORT + LAYER Metal4 ; + RECT 271.345 0 275.765 47.045 ; + END + PORT + LAYER Metal4 ; + RECT 253.665 0 258.085 47.045 ; + END + PORT + LAYER Metal4 ; + RECT 235.985 0 240.405 47.045 ; + END + PORT + LAYER Metal4 ; + RECT 218.305 0 222.725 47.045 ; + END + PORT + LAYER Metal4 ; + RECT 200.625 0 205.045 47.045 ; + END + PORT + LAYER Metal4 ; + RECT 182.945 0 187.365 47.045 ; + END + PORT + LAYER Metal4 ; + RECT 165.265 0 169.685 47.045 ; + END + PORT + LAYER Metal4 ; + RECT 147.585 0 152.005 47.045 ; + END + PORT + LAYER Metal4 ; + RECT 129.905 0 134.325 47.045 ; + END + PORT + LAYER Metal4 ; + RECT 112.225 0 116.645 47.045 ; + END + PORT + LAYER Metal4 ; + RECT 94.545 0 98.965 47.045 ; + END + PORT + LAYER Metal4 ; + RECT 76.865 0 81.285 47.045 ; + END + PORT + LAYER Metal4 ; + RECT 59.185 0 63.605 47.045 ; + END + PORT + LAYER Metal4 ; + RECT 41.505 0 45.925 47.045 ; + END + PORT + LAYER Metal4 ; + RECT 23.825 0 28.245 47.045 ; + END + PORT + LAYER Metal4 ; + RECT 6.145 0 10.565 47.045 ; + END + END VDD! + PIN VDDARRAY! + DIRECTION INOUT ; + USE POWER ; + NETEXPR "vddarray VDDARRAY!" ; + PORT + LAYER Metal4 ; + RECT 674.925 53.41 679.345 219.77 ; + END + PORT + LAYER Metal4 ; + RECT 657.245 53.41 661.665 219.77 ; + END + PORT + LAYER Metal4 ; + RECT 639.565 53.41 643.985 219.77 ; + END + PORT + LAYER Metal4 ; + RECT 621.885 53.41 626.305 219.77 ; + END + PORT + LAYER Metal4 ; + RECT 604.205 53.41 608.625 219.77 ; + END + PORT + LAYER Metal4 ; + RECT 586.525 53.41 590.945 219.77 ; + END + PORT + LAYER Metal4 ; + RECT 568.845 53.41 573.265 219.77 ; + END + PORT + LAYER Metal4 ; + RECT 551.165 53.41 555.585 219.77 ; + END + PORT + LAYER Metal4 ; + RECT 533.485 53.41 537.905 219.77 ; + END + PORT + LAYER Metal4 ; + RECT 515.805 53.41 520.225 219.77 ; + END + PORT + LAYER Metal4 ; + RECT 498.125 53.41 502.545 219.77 ; + END + PORT + LAYER Metal4 ; + RECT 480.445 53.41 484.865 219.77 ; + END + PORT + LAYER Metal4 ; + RECT 462.765 53.41 467.185 219.77 ; + END + PORT + LAYER Metal4 ; + RECT 445.085 53.41 449.505 219.77 ; + END + PORT + LAYER Metal4 ; + RECT 427.405 53.41 431.825 219.77 ; + END + PORT + LAYER Metal4 ; + RECT 409.725 53.41 414.145 219.77 ; + END + PORT + LAYER Metal4 ; + RECT 271.345 53.41 275.765 219.77 ; + END + PORT + LAYER Metal4 ; + RECT 253.665 53.41 258.085 219.77 ; + END + PORT + LAYER Metal4 ; + RECT 235.985 53.41 240.405 219.77 ; + END + PORT + LAYER Metal4 ; + RECT 218.305 53.41 222.725 219.77 ; + END + PORT + LAYER Metal4 ; + RECT 200.625 53.41 205.045 219.77 ; + END + PORT + LAYER Metal4 ; + RECT 182.945 53.41 187.365 219.77 ; + END + PORT + LAYER Metal4 ; + RECT 165.265 53.41 169.685 219.77 ; + END + PORT + LAYER Metal4 ; + RECT 147.585 53.41 152.005 219.77 ; + END + PORT + LAYER Metal4 ; + RECT 129.905 53.41 134.325 219.77 ; + END + PORT + LAYER Metal4 ; + RECT 112.225 53.41 116.645 219.77 ; + END + PORT + LAYER Metal4 ; + RECT 94.545 53.41 98.965 219.77 ; + END + PORT + LAYER Metal4 ; + RECT 76.865 53.41 81.285 219.77 ; + END + PORT + LAYER Metal4 ; + RECT 59.185 53.41 63.605 219.77 ; + END + PORT + LAYER Metal4 ; + RECT 41.505 53.41 45.925 219.77 ; + END + PORT + LAYER Metal4 ; + RECT 23.825 53.41 28.245 219.77 ; + END + PORT + LAYER Metal4 ; + RECT 6.145 53.41 10.565 219.77 ; + END + END VDDARRAY! + PIN A_DIN[17] + DIRECTION INPUT ; + USE SIGNAL ; + ANTENNAPARTIALMETALAREA 3.9091 LAYER Metal2 ; + ANTENNAMODEL OXIDE1 ; + ANTENNAGATEAREA 0.20085 LAYER Metal2 ; + ANTENNAMAXAREACAR 20.368932 LAYER Metal2 ; + PORT + LAYER Metal2 ; + RECT 425.83 0 426.09 0.26 ; + END + END A_DIN[17] + PIN A_DIN[14] + DIRECTION INPUT ; + USE SIGNAL ; + ANTENNAPARTIALMETALAREA 3.9091 LAYER Metal2 ; + ANTENNAMODEL OXIDE1 ; + ANTENNAGATEAREA 0.20085 LAYER Metal2 ; + ANTENNAMAXAREACAR 20.368932 LAYER Metal2 ; + PORT + LAYER Metal2 ; + RECT 259.4 0 259.66 0.26 ; + END + END A_DIN[14] + PIN A_BIST_DIN[17] + DIRECTION INPUT ; + USE SIGNAL ; + ANTENNAPARTIALMETALAREA 4.136375 LAYER Metal2 ; + ANTENNAMODEL OXIDE1 ; + ANTENNAGATEAREA 0.20085 LAYER Metal2 ; + ANTENNAMAXAREACAR 21.874907 LAYER Metal2 ; + PORT + LAYER Metal2 ; + RECT 426.34 0 426.6 0.26 ; + END + END A_BIST_DIN[17] + PIN A_BIST_DIN[14] + DIRECTION INPUT ; + USE SIGNAL ; + ANTENNAPARTIALMETALAREA 4.136375 LAYER Metal2 ; + ANTENNAMODEL OXIDE1 ; + ANTENNAGATEAREA 0.20085 LAYER Metal2 ; + ANTENNAMAXAREACAR 21.874907 LAYER Metal2 ; + PORT + LAYER Metal2 ; + RECT 258.89 0 259.15 0.26 ; + END + END A_BIST_DIN[14] + PIN A_BM[17] + DIRECTION INPUT ; + USE SIGNAL ; + ANTENNAPARTIALMETALAREA 1.7264 LAYER Metal2 ; + ANTENNAMODEL OXIDE1 ; + ANTENNAGATEAREA 0.20085 LAYER Metal2 ; + ANTENNAMAXAREACAR 9.501618 LAYER Metal2 ; + PORT + LAYER Metal2 ; + RECT 434.5 0 434.76 0.26 ; + END + END A_BM[17] + PIN A_BM[14] + DIRECTION INPUT ; + USE SIGNAL ; + ANTENNAPARTIALMETALAREA 1.7264 LAYER Metal2 ; + ANTENNAMODEL OXIDE1 ; + ANTENNAGATEAREA 0.20085 LAYER Metal2 ; + ANTENNAMAXAREACAR 9.501618 LAYER Metal2 ; + PORT + LAYER Metal2 ; + RECT 250.73 0 250.99 0.26 ; + END + END A_BM[14] + PIN A_BIST_BM[17] + DIRECTION INPUT ; + USE SIGNAL ; + ANTENNAPARTIALMETALAREA 1.7602 LAYER Metal2 ; + ANTENNAMODEL OXIDE1 ; + ANTENNAGATEAREA 0.20085 LAYER Metal2 ; + ANTENNAMAXAREACAR 9.678367 LAYER Metal2 ; + PORT + LAYER Metal2 ; + RECT 433.125 0 433.385 0.26 ; + END + END A_BIST_BM[17] + PIN A_BIST_BM[14] + DIRECTION INPUT ; + USE SIGNAL ; + ANTENNAPARTIALMETALAREA 1.7602 LAYER Metal2 ; + ANTENNAMODEL OXIDE1 ; + ANTENNAGATEAREA 0.20085 LAYER Metal2 ; + ANTENNAMAXAREACAR 9.678367 LAYER Metal2 ; + PORT + LAYER Metal2 ; + RECT 252.105 0 252.365 0.26 ; + END + END A_BIST_BM[14] + PIN A_DOUT[17] + DIRECTION OUTPUT ; + USE SIGNAL ; + ANTENNAPARTIALMETALAREA 4.8256 LAYER Metal2 ; + ANTENNADIFFAREA 0.988 LAYER Metal2 ; + PORT + LAYER Metal2 ; + RECT 418.69 0 418.95 0.26 ; + END + END A_DOUT[17] + PIN A_DOUT[14] + DIRECTION OUTPUT ; + USE SIGNAL ; + ANTENNAPARTIALMETALAREA 4.8256 LAYER Metal2 ; + ANTENNADIFFAREA 0.988 LAYER Metal2 ; + PORT + LAYER Metal2 ; + RECT 266.54 0 266.8 0.26 ; + END + END A_DOUT[14] + PIN B_DIN[17] + DIRECTION INPUT ; + USE SIGNAL ; + ANTENNAPARTIALMETALAREA 2.925 LAYER Metal2 ; + ANTENNAMODEL OXIDE1 ; + ANTENNAGATEAREA 0.20085 LAYER Metal2 ; + ANTENNAMAXAREACAR 15.469256 LAYER Metal2 ; + PORT + LAYER Metal2 ; + RECT 428.38 0 428.64 0.26 ; + END + END B_DIN[17] + PIN B_DIN[14] + DIRECTION INPUT ; + USE SIGNAL ; + ANTENNAPARTIALMETALAREA 2.925 LAYER Metal2 ; + ANTENNAMODEL OXIDE1 ; + ANTENNAGATEAREA 0.20085 LAYER Metal2 ; + ANTENNAMAXAREACAR 15.469256 LAYER Metal2 ; + PORT + LAYER Metal2 ; + RECT 256.85 0 257.11 0.26 ; + END + END B_DIN[14] + PIN B_BIST_DIN[17] + DIRECTION INPUT ; + USE SIGNAL ; + ANTENNAPARTIALMETALAREA 2.9445 LAYER Metal2 ; + ANTENNAMODEL OXIDE1 ; + ANTENNAGATEAREA 0.20085 LAYER Metal2 ; + ANTENNAMAXAREACAR 15.929052 LAYER Metal2 ; + PORT + LAYER Metal2 ; + RECT 426.85 0 427.11 0.26 ; + END + END B_BIST_DIN[17] + PIN B_BIST_DIN[14] + DIRECTION INPUT ; + USE SIGNAL ; + ANTENNAPARTIALMETALAREA 2.9445 LAYER Metal2 ; + ANTENNAMODEL OXIDE1 ; + ANTENNAGATEAREA 0.20085 LAYER Metal2 ; + ANTENNAMAXAREACAR 15.929052 LAYER Metal2 ; + PORT + LAYER Metal2 ; + RECT 258.38 0 258.64 0.26 ; + END + END B_BIST_DIN[14] + PIN B_BM[17] + DIRECTION INPUT ; + USE SIGNAL ; + ANTENNAPARTIALMETALAREA 0.7007 LAYER Metal2 ; + ANTENNAMODEL OXIDE1 ; + ANTENNAGATEAREA 0.20085 LAYER Metal2 ; + ANTENNAMAXAREACAR 4.394822 LAYER Metal2 ; + PORT + LAYER Metal2 ; + RECT 419.865 0 420.125 0.26 ; + END + END B_BM[17] + PIN B_BM[14] + DIRECTION INPUT ; + USE SIGNAL ; + ANTENNAPARTIALMETALAREA 0.7007 LAYER Metal2 ; + ANTENNAMODEL OXIDE1 ; + ANTENNAGATEAREA 0.20085 LAYER Metal2 ; + ANTENNAMAXAREACAR 4.394822 LAYER Metal2 ; + PORT + LAYER Metal2 ; + RECT 265.365 0 265.625 0.26 ; + END + END B_BM[14] + PIN B_BIST_BM[17] + DIRECTION INPUT ; + USE SIGNAL ; + ANTENNAPARTIALMETALAREA 0.7007 LAYER Metal2 ; + ANTENNAMODEL OXIDE1 ; + ANTENNAGATEAREA 0.20085 LAYER Metal2 ; + ANTENNAMAXAREACAR 4.394822 LAYER Metal2 ; + PORT + LAYER Metal2 ; + RECT 421.395 0 421.655 0.26 ; + END + END B_BIST_BM[17] + PIN B_BIST_BM[14] + DIRECTION INPUT ; + USE SIGNAL ; + ANTENNAPARTIALMETALAREA 0.7007 LAYER Metal2 ; + ANTENNAMODEL OXIDE1 ; + ANTENNAGATEAREA 0.20085 LAYER Metal2 ; + ANTENNAMAXAREACAR 4.394822 LAYER Metal2 ; + PORT + LAYER Metal2 ; + RECT 263.835 0 264.095 0.26 ; + END + END B_BIST_BM[14] + PIN B_DOUT[17] + DIRECTION OUTPUT ; + USE SIGNAL ; + ANTENNAPARTIALMETALAREA 4.836 LAYER Metal2 ; + ANTENNADIFFAREA 0.988 LAYER Metal2 ; + PORT + LAYER Metal2 ; + RECT 435.52 0 435.78 0.26 ; + END + END B_DOUT[17] + PIN B_DOUT[14] + DIRECTION OUTPUT ; + USE SIGNAL ; + ANTENNAPARTIALMETALAREA 4.836 LAYER Metal2 ; + ANTENNADIFFAREA 0.988 LAYER Metal2 ; + PORT + LAYER Metal2 ; + RECT 249.71 0 249.97 0.26 ; + END + END B_DOUT[14] + PIN A_DIN[18] + DIRECTION INPUT ; + USE SIGNAL ; + ANTENNAPARTIALMETALAREA 3.9091 LAYER Metal2 ; + ANTENNAMODEL OXIDE1 ; + ANTENNAGATEAREA 0.20085 LAYER Metal2 ; + ANTENNAMAXAREACAR 20.368932 LAYER Metal2 ; + PORT + LAYER Metal2 ; + RECT 443.51 0 443.77 0.26 ; + END + END A_DIN[18] + PIN A_DIN[13] + DIRECTION INPUT ; + USE SIGNAL ; + ANTENNAPARTIALMETALAREA 3.9091 LAYER Metal2 ; + ANTENNAMODEL OXIDE1 ; + ANTENNAGATEAREA 0.20085 LAYER Metal2 ; + ANTENNAMAXAREACAR 20.368932 LAYER Metal2 ; + PORT + LAYER Metal2 ; + RECT 241.72 0 241.98 0.26 ; + END + END A_DIN[13] + PIN A_BIST_DIN[18] + DIRECTION INPUT ; + USE SIGNAL ; + ANTENNAPARTIALMETALAREA 4.136375 LAYER Metal2 ; + ANTENNAMODEL OXIDE1 ; + ANTENNAGATEAREA 0.20085 LAYER Metal2 ; + ANTENNAMAXAREACAR 21.874907 LAYER Metal2 ; + PORT + LAYER Metal2 ; + RECT 444.02 0 444.28 0.26 ; + END + END A_BIST_DIN[18] + PIN A_BIST_DIN[13] + DIRECTION INPUT ; + USE SIGNAL ; + ANTENNAPARTIALMETALAREA 4.136375 LAYER Metal2 ; + ANTENNAMODEL OXIDE1 ; + ANTENNAGATEAREA 0.20085 LAYER Metal2 ; + ANTENNAMAXAREACAR 21.874907 LAYER Metal2 ; + PORT + LAYER Metal2 ; + RECT 241.21 0 241.47 0.26 ; + END + END A_BIST_DIN[13] + PIN A_BM[18] + DIRECTION INPUT ; + USE SIGNAL ; + ANTENNAPARTIALMETALAREA 1.7264 LAYER Metal2 ; + ANTENNAMODEL OXIDE1 ; + ANTENNAGATEAREA 0.20085 LAYER Metal2 ; + ANTENNAMAXAREACAR 9.501618 LAYER Metal2 ; + PORT + LAYER Metal2 ; + RECT 452.18 0 452.44 0.26 ; + END + END A_BM[18] + PIN A_BM[13] + DIRECTION INPUT ; + USE SIGNAL ; + ANTENNAPARTIALMETALAREA 1.7264 LAYER Metal2 ; + ANTENNAMODEL OXIDE1 ; + ANTENNAGATEAREA 0.20085 LAYER Metal2 ; + ANTENNAMAXAREACAR 9.501618 LAYER Metal2 ; + PORT + LAYER Metal2 ; + RECT 233.05 0 233.31 0.26 ; + END + END A_BM[13] + PIN A_BIST_BM[18] + DIRECTION INPUT ; + USE SIGNAL ; + ANTENNAPARTIALMETALAREA 1.7602 LAYER Metal2 ; + ANTENNAMODEL OXIDE1 ; + ANTENNAGATEAREA 0.20085 LAYER Metal2 ; + ANTENNAMAXAREACAR 9.678367 LAYER Metal2 ; + PORT + LAYER Metal2 ; + RECT 450.805 0 451.065 0.26 ; + END + END A_BIST_BM[18] + PIN A_BIST_BM[13] + DIRECTION INPUT ; + USE SIGNAL ; + ANTENNAPARTIALMETALAREA 1.7602 LAYER Metal2 ; + ANTENNAMODEL OXIDE1 ; + ANTENNAGATEAREA 0.20085 LAYER Metal2 ; + ANTENNAMAXAREACAR 9.678367 LAYER Metal2 ; + PORT + LAYER Metal2 ; + RECT 234.425 0 234.685 0.26 ; + END + END A_BIST_BM[13] + PIN A_DOUT[18] + DIRECTION OUTPUT ; + USE SIGNAL ; + ANTENNAPARTIALMETALAREA 4.8256 LAYER Metal2 ; + ANTENNADIFFAREA 0.988 LAYER Metal2 ; + PORT + LAYER Metal2 ; + RECT 436.37 0 436.63 0.26 ; + END + END A_DOUT[18] + PIN A_DOUT[13] + DIRECTION OUTPUT ; + USE SIGNAL ; + ANTENNAPARTIALMETALAREA 4.8256 LAYER Metal2 ; + ANTENNADIFFAREA 0.988 LAYER Metal2 ; + PORT + LAYER Metal2 ; + RECT 248.86 0 249.12 0.26 ; + END + END A_DOUT[13] + PIN B_DIN[18] + DIRECTION INPUT ; + USE SIGNAL ; + ANTENNAPARTIALMETALAREA 2.925 LAYER Metal2 ; + ANTENNAMODEL OXIDE1 ; + ANTENNAGATEAREA 0.20085 LAYER Metal2 ; + ANTENNAMAXAREACAR 15.469256 LAYER Metal2 ; + PORT + LAYER Metal2 ; + RECT 446.06 0 446.32 0.26 ; + END + END B_DIN[18] + PIN B_DIN[13] + DIRECTION INPUT ; + USE SIGNAL ; + ANTENNAPARTIALMETALAREA 2.925 LAYER Metal2 ; + ANTENNAMODEL OXIDE1 ; + ANTENNAGATEAREA 0.20085 LAYER Metal2 ; + ANTENNAMAXAREACAR 15.469256 LAYER Metal2 ; + PORT + LAYER Metal2 ; + RECT 239.17 0 239.43 0.26 ; + END + END B_DIN[13] + PIN B_BIST_DIN[18] + DIRECTION INPUT ; + USE SIGNAL ; + ANTENNAPARTIALMETALAREA 2.9445 LAYER Metal2 ; + ANTENNAMODEL OXIDE1 ; + ANTENNAGATEAREA 0.20085 LAYER Metal2 ; + ANTENNAMAXAREACAR 15.929052 LAYER Metal2 ; + PORT + LAYER Metal2 ; + RECT 444.53 0 444.79 0.26 ; + END + END B_BIST_DIN[18] + PIN B_BIST_DIN[13] + DIRECTION INPUT ; + USE SIGNAL ; + ANTENNAPARTIALMETALAREA 2.9445 LAYER Metal2 ; + ANTENNAMODEL OXIDE1 ; + ANTENNAGATEAREA 0.20085 LAYER Metal2 ; + ANTENNAMAXAREACAR 15.929052 LAYER Metal2 ; + PORT + LAYER Metal2 ; + RECT 240.7 0 240.96 0.26 ; + END + END B_BIST_DIN[13] + PIN B_BM[18] + DIRECTION INPUT ; + USE SIGNAL ; + ANTENNAPARTIALMETALAREA 0.7007 LAYER Metal2 ; + ANTENNAMODEL OXIDE1 ; + ANTENNAGATEAREA 0.20085 LAYER Metal2 ; + ANTENNAMAXAREACAR 4.394822 LAYER Metal2 ; + PORT + LAYER Metal2 ; + RECT 437.545 0 437.805 0.26 ; + END + END B_BM[18] + PIN B_BM[13] + DIRECTION INPUT ; + USE SIGNAL ; + ANTENNAPARTIALMETALAREA 0.7007 LAYER Metal2 ; + ANTENNAMODEL OXIDE1 ; + ANTENNAGATEAREA 0.20085 LAYER Metal2 ; + ANTENNAMAXAREACAR 4.394822 LAYER Metal2 ; + PORT + LAYER Metal2 ; + RECT 247.685 0 247.945 0.26 ; + END + END B_BM[13] + PIN B_BIST_BM[18] + DIRECTION INPUT ; + USE SIGNAL ; + ANTENNAPARTIALMETALAREA 0.7007 LAYER Metal2 ; + ANTENNAMODEL OXIDE1 ; + ANTENNAGATEAREA 0.20085 LAYER Metal2 ; + ANTENNAMAXAREACAR 4.394822 LAYER Metal2 ; + PORT + LAYER Metal2 ; + RECT 439.075 0 439.335 0.26 ; + END + END B_BIST_BM[18] + PIN B_BIST_BM[13] + DIRECTION INPUT ; + USE SIGNAL ; + ANTENNAPARTIALMETALAREA 0.7007 LAYER Metal2 ; + ANTENNAMODEL OXIDE1 ; + ANTENNAGATEAREA 0.20085 LAYER Metal2 ; + ANTENNAMAXAREACAR 4.394822 LAYER Metal2 ; + PORT + LAYER Metal2 ; + RECT 246.155 0 246.415 0.26 ; + END + END B_BIST_BM[13] + PIN B_DOUT[18] + DIRECTION OUTPUT ; + USE SIGNAL ; + ANTENNAPARTIALMETALAREA 4.836 LAYER Metal2 ; + ANTENNADIFFAREA 0.988 LAYER Metal2 ; + PORT + LAYER Metal2 ; + RECT 453.2 0 453.46 0.26 ; + END + END B_DOUT[18] + PIN B_DOUT[13] + DIRECTION OUTPUT ; + USE SIGNAL ; + ANTENNAPARTIALMETALAREA 4.836 LAYER Metal2 ; + ANTENNADIFFAREA 0.988 LAYER Metal2 ; + PORT + LAYER Metal2 ; + RECT 232.03 0 232.29 0.26 ; + END + END B_DOUT[13] + PIN A_DIN[19] + DIRECTION INPUT ; + USE SIGNAL ; + ANTENNAPARTIALMETALAREA 3.9091 LAYER Metal2 ; + ANTENNAMODEL OXIDE1 ; + ANTENNAGATEAREA 0.20085 LAYER Metal2 ; + ANTENNAMAXAREACAR 20.368932 LAYER Metal2 ; + PORT + LAYER Metal2 ; + RECT 461.19 0 461.45 0.26 ; + END + END A_DIN[19] + PIN A_DIN[12] + DIRECTION INPUT ; + USE SIGNAL ; + ANTENNAPARTIALMETALAREA 3.9091 LAYER Metal2 ; + ANTENNAMODEL OXIDE1 ; + ANTENNAGATEAREA 0.20085 LAYER Metal2 ; + ANTENNAMAXAREACAR 20.368932 LAYER Metal2 ; + PORT + LAYER Metal2 ; + RECT 224.04 0 224.3 0.26 ; + END + END A_DIN[12] + PIN A_BIST_DIN[19] + DIRECTION INPUT ; + USE SIGNAL ; + ANTENNAPARTIALMETALAREA 4.136375 LAYER Metal2 ; + ANTENNAMODEL OXIDE1 ; + ANTENNAGATEAREA 0.20085 LAYER Metal2 ; + ANTENNAMAXAREACAR 21.874907 LAYER Metal2 ; + PORT + LAYER Metal2 ; + RECT 461.7 0 461.96 0.26 ; + END + END A_BIST_DIN[19] + PIN A_BIST_DIN[12] + DIRECTION INPUT ; + USE SIGNAL ; + ANTENNAPARTIALMETALAREA 4.136375 LAYER Metal2 ; + ANTENNAMODEL OXIDE1 ; + ANTENNAGATEAREA 0.20085 LAYER Metal2 ; + ANTENNAMAXAREACAR 21.874907 LAYER Metal2 ; + PORT + LAYER Metal2 ; + RECT 223.53 0 223.79 0.26 ; + END + END A_BIST_DIN[12] + PIN A_BM[19] + DIRECTION INPUT ; + USE SIGNAL ; + ANTENNAPARTIALMETALAREA 1.7264 LAYER Metal2 ; + ANTENNAMODEL OXIDE1 ; + ANTENNAGATEAREA 0.20085 LAYER Metal2 ; + ANTENNAMAXAREACAR 9.501618 LAYER Metal2 ; + PORT + LAYER Metal2 ; + RECT 469.86 0 470.12 0.26 ; + END + END A_BM[19] + PIN A_BM[12] + DIRECTION INPUT ; + USE SIGNAL ; + ANTENNAPARTIALMETALAREA 1.7264 LAYER Metal2 ; + ANTENNAMODEL OXIDE1 ; + ANTENNAGATEAREA 0.20085 LAYER Metal2 ; + ANTENNAMAXAREACAR 9.501618 LAYER Metal2 ; + PORT + LAYER Metal2 ; + RECT 215.37 0 215.63 0.26 ; + END + END A_BM[12] + PIN A_BIST_BM[19] + DIRECTION INPUT ; + USE SIGNAL ; + ANTENNAPARTIALMETALAREA 1.7602 LAYER Metal2 ; + ANTENNAMODEL OXIDE1 ; + ANTENNAGATEAREA 0.20085 LAYER Metal2 ; + ANTENNAMAXAREACAR 9.678367 LAYER Metal2 ; + PORT + LAYER Metal2 ; + RECT 468.485 0 468.745 0.26 ; + END + END A_BIST_BM[19] + PIN A_BIST_BM[12] + DIRECTION INPUT ; + USE SIGNAL ; + ANTENNAPARTIALMETALAREA 1.7602 LAYER Metal2 ; + ANTENNAMODEL OXIDE1 ; + ANTENNAGATEAREA 0.20085 LAYER Metal2 ; + ANTENNAMAXAREACAR 9.678367 LAYER Metal2 ; + PORT + LAYER Metal2 ; + RECT 216.745 0 217.005 0.26 ; + END + END A_BIST_BM[12] + PIN A_DOUT[19] + DIRECTION OUTPUT ; + USE SIGNAL ; + ANTENNAPARTIALMETALAREA 4.8256 LAYER Metal2 ; + ANTENNADIFFAREA 0.988 LAYER Metal2 ; + PORT + LAYER Metal2 ; + RECT 454.05 0 454.31 0.26 ; + END + END A_DOUT[19] + PIN A_DOUT[12] + DIRECTION OUTPUT ; + USE SIGNAL ; + ANTENNAPARTIALMETALAREA 4.8256 LAYER Metal2 ; + ANTENNADIFFAREA 0.988 LAYER Metal2 ; + PORT + LAYER Metal2 ; + RECT 231.18 0 231.44 0.26 ; + END + END A_DOUT[12] + PIN B_DIN[19] + DIRECTION INPUT ; + USE SIGNAL ; + ANTENNAPARTIALMETALAREA 2.925 LAYER Metal2 ; + ANTENNAMODEL OXIDE1 ; + ANTENNAGATEAREA 0.20085 LAYER Metal2 ; + ANTENNAMAXAREACAR 15.469256 LAYER Metal2 ; + PORT + LAYER Metal2 ; + RECT 463.74 0 464 0.26 ; + END + END B_DIN[19] + PIN B_DIN[12] + DIRECTION INPUT ; + USE SIGNAL ; + ANTENNAPARTIALMETALAREA 2.925 LAYER Metal2 ; + ANTENNAMODEL OXIDE1 ; + ANTENNAGATEAREA 0.20085 LAYER Metal2 ; + ANTENNAMAXAREACAR 15.469256 LAYER Metal2 ; + PORT + LAYER Metal2 ; + RECT 221.49 0 221.75 0.26 ; + END + END B_DIN[12] + PIN B_BIST_DIN[19] + DIRECTION INPUT ; + USE SIGNAL ; + ANTENNAPARTIALMETALAREA 2.9445 LAYER Metal2 ; + ANTENNAMODEL OXIDE1 ; + ANTENNAGATEAREA 0.20085 LAYER Metal2 ; + ANTENNAMAXAREACAR 15.929052 LAYER Metal2 ; + PORT + LAYER Metal2 ; + RECT 462.21 0 462.47 0.26 ; + END + END B_BIST_DIN[19] + PIN B_BIST_DIN[12] + DIRECTION INPUT ; + USE SIGNAL ; + ANTENNAPARTIALMETALAREA 2.9445 LAYER Metal2 ; + ANTENNAMODEL OXIDE1 ; + ANTENNAGATEAREA 0.20085 LAYER Metal2 ; + ANTENNAMAXAREACAR 15.929052 LAYER Metal2 ; + PORT + LAYER Metal2 ; + RECT 223.02 0 223.28 0.26 ; + END + END B_BIST_DIN[12] + PIN B_BM[19] + DIRECTION INPUT ; + USE SIGNAL ; + ANTENNAPARTIALMETALAREA 0.7007 LAYER Metal2 ; + ANTENNAMODEL OXIDE1 ; + ANTENNAGATEAREA 0.20085 LAYER Metal2 ; + ANTENNAMAXAREACAR 4.394822 LAYER Metal2 ; + PORT + LAYER Metal2 ; + RECT 455.225 0 455.485 0.26 ; + END + END B_BM[19] + PIN B_BM[12] + DIRECTION INPUT ; + USE SIGNAL ; + ANTENNAPARTIALMETALAREA 0.7007 LAYER Metal2 ; + ANTENNAMODEL OXIDE1 ; + ANTENNAGATEAREA 0.20085 LAYER Metal2 ; + ANTENNAMAXAREACAR 4.394822 LAYER Metal2 ; + PORT + LAYER Metal2 ; + RECT 230.005 0 230.265 0.26 ; + END + END B_BM[12] + PIN B_BIST_BM[19] + DIRECTION INPUT ; + USE SIGNAL ; + ANTENNAPARTIALMETALAREA 0.7007 LAYER Metal2 ; + ANTENNAMODEL OXIDE1 ; + ANTENNAGATEAREA 0.20085 LAYER Metal2 ; + ANTENNAMAXAREACAR 4.394822 LAYER Metal2 ; + PORT + LAYER Metal2 ; + RECT 456.755 0 457.015 0.26 ; + END + END B_BIST_BM[19] + PIN B_BIST_BM[12] + DIRECTION INPUT ; + USE SIGNAL ; + ANTENNAPARTIALMETALAREA 0.7007 LAYER Metal2 ; + ANTENNAMODEL OXIDE1 ; + ANTENNAGATEAREA 0.20085 LAYER Metal2 ; + ANTENNAMAXAREACAR 4.394822 LAYER Metal2 ; + PORT + LAYER Metal2 ; + RECT 228.475 0 228.735 0.26 ; + END + END B_BIST_BM[12] + PIN B_DOUT[19] + DIRECTION OUTPUT ; + USE SIGNAL ; + ANTENNAPARTIALMETALAREA 4.836 LAYER Metal2 ; + ANTENNADIFFAREA 0.988 LAYER Metal2 ; + PORT + LAYER Metal2 ; + RECT 470.88 0 471.14 0.26 ; + END + END B_DOUT[19] + PIN B_DOUT[12] + DIRECTION OUTPUT ; + USE SIGNAL ; + ANTENNAPARTIALMETALAREA 4.836 LAYER Metal2 ; + ANTENNADIFFAREA 0.988 LAYER Metal2 ; + PORT + LAYER Metal2 ; + RECT 214.35 0 214.61 0.26 ; + END + END B_DOUT[12] + PIN A_DIN[20] + DIRECTION INPUT ; + USE SIGNAL ; + ANTENNAPARTIALMETALAREA 3.9091 LAYER Metal2 ; + ANTENNAMODEL OXIDE1 ; + ANTENNAGATEAREA 0.20085 LAYER Metal2 ; + ANTENNAMAXAREACAR 20.368932 LAYER Metal2 ; + PORT + LAYER Metal2 ; + RECT 478.87 0 479.13 0.26 ; + END + END A_DIN[20] + PIN A_DIN[11] + DIRECTION INPUT ; + USE SIGNAL ; + ANTENNAPARTIALMETALAREA 3.9091 LAYER Metal2 ; + ANTENNAMODEL OXIDE1 ; + ANTENNAGATEAREA 0.20085 LAYER Metal2 ; + ANTENNAMAXAREACAR 20.368932 LAYER Metal2 ; + PORT + LAYER Metal2 ; + RECT 206.36 0 206.62 0.26 ; + END + END A_DIN[11] + PIN A_BIST_DIN[20] + DIRECTION INPUT ; + USE SIGNAL ; + ANTENNAPARTIALMETALAREA 4.136375 LAYER Metal2 ; + ANTENNAMODEL OXIDE1 ; + ANTENNAGATEAREA 0.20085 LAYER Metal2 ; + ANTENNAMAXAREACAR 21.874907 LAYER Metal2 ; + PORT + LAYER Metal2 ; + RECT 479.38 0 479.64 0.26 ; + END + END A_BIST_DIN[20] + PIN A_BIST_DIN[11] + DIRECTION INPUT ; + USE SIGNAL ; + ANTENNAPARTIALMETALAREA 4.136375 LAYER Metal2 ; + ANTENNAMODEL OXIDE1 ; + ANTENNAGATEAREA 0.20085 LAYER Metal2 ; + ANTENNAMAXAREACAR 21.874907 LAYER Metal2 ; + PORT + LAYER Metal2 ; + RECT 205.85 0 206.11 0.26 ; + END + END A_BIST_DIN[11] + PIN A_BM[20] + DIRECTION INPUT ; + USE SIGNAL ; + ANTENNAPARTIALMETALAREA 1.7264 LAYER Metal2 ; + ANTENNAMODEL OXIDE1 ; + ANTENNAGATEAREA 0.20085 LAYER Metal2 ; + ANTENNAMAXAREACAR 9.501618 LAYER Metal2 ; + PORT + LAYER Metal2 ; + RECT 487.54 0 487.8 0.26 ; + END + END A_BM[20] + PIN A_BM[11] + DIRECTION INPUT ; + USE SIGNAL ; + ANTENNAPARTIALMETALAREA 1.7264 LAYER Metal2 ; + ANTENNAMODEL OXIDE1 ; + ANTENNAGATEAREA 0.20085 LAYER Metal2 ; + ANTENNAMAXAREACAR 9.501618 LAYER Metal2 ; + PORT + LAYER Metal2 ; + RECT 197.69 0 197.95 0.26 ; + END + END A_BM[11] + PIN A_BIST_BM[20] + DIRECTION INPUT ; + USE SIGNAL ; + ANTENNAPARTIALMETALAREA 1.7602 LAYER Metal2 ; + ANTENNAMODEL OXIDE1 ; + ANTENNAGATEAREA 0.20085 LAYER Metal2 ; + ANTENNAMAXAREACAR 9.678367 LAYER Metal2 ; + PORT + LAYER Metal2 ; + RECT 486.165 0 486.425 0.26 ; + END + END A_BIST_BM[20] + PIN A_BIST_BM[11] + DIRECTION INPUT ; + USE SIGNAL ; + ANTENNAPARTIALMETALAREA 1.7602 LAYER Metal2 ; + ANTENNAMODEL OXIDE1 ; + ANTENNAGATEAREA 0.20085 LAYER Metal2 ; + ANTENNAMAXAREACAR 9.678367 LAYER Metal2 ; + PORT + LAYER Metal2 ; + RECT 199.065 0 199.325 0.26 ; + END + END A_BIST_BM[11] + PIN A_DOUT[20] + DIRECTION OUTPUT ; + USE SIGNAL ; + ANTENNAPARTIALMETALAREA 4.8256 LAYER Metal2 ; + ANTENNADIFFAREA 0.988 LAYER Metal2 ; + PORT + LAYER Metal2 ; + RECT 471.73 0 471.99 0.26 ; + END + END A_DOUT[20] + PIN A_DOUT[11] + DIRECTION OUTPUT ; + USE SIGNAL ; + ANTENNAPARTIALMETALAREA 4.8256 LAYER Metal2 ; + ANTENNADIFFAREA 0.988 LAYER Metal2 ; + PORT + LAYER Metal2 ; + RECT 213.5 0 213.76 0.26 ; + END + END A_DOUT[11] + PIN B_DIN[20] + DIRECTION INPUT ; + USE SIGNAL ; + ANTENNAPARTIALMETALAREA 2.925 LAYER Metal2 ; + ANTENNAMODEL OXIDE1 ; + ANTENNAGATEAREA 0.20085 LAYER Metal2 ; + ANTENNAMAXAREACAR 15.469256 LAYER Metal2 ; + PORT + LAYER Metal2 ; + RECT 481.42 0 481.68 0.26 ; + END + END B_DIN[20] + PIN B_DIN[11] + DIRECTION INPUT ; + USE SIGNAL ; + ANTENNAPARTIALMETALAREA 2.925 LAYER Metal2 ; + ANTENNAMODEL OXIDE1 ; + ANTENNAGATEAREA 0.20085 LAYER Metal2 ; + ANTENNAMAXAREACAR 15.469256 LAYER Metal2 ; + PORT + LAYER Metal2 ; + RECT 203.81 0 204.07 0.26 ; + END + END B_DIN[11] + PIN B_BIST_DIN[20] + DIRECTION INPUT ; + USE SIGNAL ; + ANTENNAPARTIALMETALAREA 2.9445 LAYER Metal2 ; + ANTENNAMODEL OXIDE1 ; + ANTENNAGATEAREA 0.20085 LAYER Metal2 ; + ANTENNAMAXAREACAR 15.929052 LAYER Metal2 ; + PORT + LAYER Metal2 ; + RECT 479.89 0 480.15 0.26 ; + END + END B_BIST_DIN[20] + PIN B_BIST_DIN[11] + DIRECTION INPUT ; + USE SIGNAL ; + ANTENNAPARTIALMETALAREA 2.9445 LAYER Metal2 ; + ANTENNAMODEL OXIDE1 ; + ANTENNAGATEAREA 0.20085 LAYER Metal2 ; + ANTENNAMAXAREACAR 15.929052 LAYER Metal2 ; + PORT + LAYER Metal2 ; + RECT 205.34 0 205.6 0.26 ; + END + END B_BIST_DIN[11] + PIN B_BM[20] + DIRECTION INPUT ; + USE SIGNAL ; + ANTENNAPARTIALMETALAREA 0.7007 LAYER Metal2 ; + ANTENNAMODEL OXIDE1 ; + ANTENNAGATEAREA 0.20085 LAYER Metal2 ; + ANTENNAMAXAREACAR 4.394822 LAYER Metal2 ; + PORT + LAYER Metal2 ; + RECT 472.905 0 473.165 0.26 ; + END + END B_BM[20] + PIN B_BM[11] + DIRECTION INPUT ; + USE SIGNAL ; + ANTENNAPARTIALMETALAREA 0.7007 LAYER Metal2 ; + ANTENNAMODEL OXIDE1 ; + ANTENNAGATEAREA 0.20085 LAYER Metal2 ; + ANTENNAMAXAREACAR 4.394822 LAYER Metal2 ; + PORT + LAYER Metal2 ; + RECT 212.325 0 212.585 0.26 ; + END + END B_BM[11] + PIN B_BIST_BM[20] + DIRECTION INPUT ; + USE SIGNAL ; + ANTENNAPARTIALMETALAREA 0.7007 LAYER Metal2 ; + ANTENNAMODEL OXIDE1 ; + ANTENNAGATEAREA 0.20085 LAYER Metal2 ; + ANTENNAMAXAREACAR 4.394822 LAYER Metal2 ; + PORT + LAYER Metal2 ; + RECT 474.435 0 474.695 0.26 ; + END + END B_BIST_BM[20] + PIN B_BIST_BM[11] + DIRECTION INPUT ; + USE SIGNAL ; + ANTENNAPARTIALMETALAREA 0.7007 LAYER Metal2 ; + ANTENNAMODEL OXIDE1 ; + ANTENNAGATEAREA 0.20085 LAYER Metal2 ; + ANTENNAMAXAREACAR 4.394822 LAYER Metal2 ; + PORT + LAYER Metal2 ; + RECT 210.795 0 211.055 0.26 ; + END + END B_BIST_BM[11] + PIN B_DOUT[20] + DIRECTION OUTPUT ; + USE SIGNAL ; + ANTENNAPARTIALMETALAREA 4.836 LAYER Metal2 ; + ANTENNADIFFAREA 0.988 LAYER Metal2 ; + PORT + LAYER Metal2 ; + RECT 488.56 0 488.82 0.26 ; + END + END B_DOUT[20] + PIN B_DOUT[11] + DIRECTION OUTPUT ; + USE SIGNAL ; + ANTENNAPARTIALMETALAREA 4.836 LAYER Metal2 ; + ANTENNADIFFAREA 0.988 LAYER Metal2 ; + PORT + LAYER Metal2 ; + RECT 196.67 0 196.93 0.26 ; + END + END B_DOUT[11] + PIN A_DIN[21] + DIRECTION INPUT ; + USE SIGNAL ; + ANTENNAPARTIALMETALAREA 3.9091 LAYER Metal2 ; + ANTENNAMODEL OXIDE1 ; + ANTENNAGATEAREA 0.20085 LAYER Metal2 ; + ANTENNAMAXAREACAR 20.368932 LAYER Metal2 ; + PORT + LAYER Metal2 ; + RECT 496.55 0 496.81 0.26 ; + END + END A_DIN[21] + PIN A_DIN[10] + DIRECTION INPUT ; + USE SIGNAL ; + ANTENNAPARTIALMETALAREA 3.9091 LAYER Metal2 ; + ANTENNAMODEL OXIDE1 ; + ANTENNAGATEAREA 0.20085 LAYER Metal2 ; + ANTENNAMAXAREACAR 20.368932 LAYER Metal2 ; + PORT + LAYER Metal2 ; + RECT 188.68 0 188.94 0.26 ; + END + END A_DIN[10] + PIN A_BIST_DIN[21] + DIRECTION INPUT ; + USE SIGNAL ; + ANTENNAPARTIALMETALAREA 4.136375 LAYER Metal2 ; + ANTENNAMODEL OXIDE1 ; + ANTENNAGATEAREA 0.20085 LAYER Metal2 ; + ANTENNAMAXAREACAR 21.874907 LAYER Metal2 ; + PORT + LAYER Metal2 ; + RECT 497.06 0 497.32 0.26 ; + END + END A_BIST_DIN[21] + PIN A_BIST_DIN[10] + DIRECTION INPUT ; + USE SIGNAL ; + ANTENNAPARTIALMETALAREA 4.136375 LAYER Metal2 ; + ANTENNAMODEL OXIDE1 ; + ANTENNAGATEAREA 0.20085 LAYER Metal2 ; + ANTENNAMAXAREACAR 21.874907 LAYER Metal2 ; + PORT + LAYER Metal2 ; + RECT 188.17 0 188.43 0.26 ; + END + END A_BIST_DIN[10] + PIN A_BM[21] + DIRECTION INPUT ; + USE SIGNAL ; + ANTENNAPARTIALMETALAREA 1.7264 LAYER Metal2 ; + ANTENNAMODEL OXIDE1 ; + ANTENNAGATEAREA 0.20085 LAYER Metal2 ; + ANTENNAMAXAREACAR 9.501618 LAYER Metal2 ; + PORT + LAYER Metal2 ; + RECT 505.22 0 505.48 0.26 ; + END + END A_BM[21] + PIN A_BM[10] + DIRECTION INPUT ; + USE SIGNAL ; + ANTENNAPARTIALMETALAREA 1.7264 LAYER Metal2 ; + ANTENNAMODEL OXIDE1 ; + ANTENNAGATEAREA 0.20085 LAYER Metal2 ; + ANTENNAMAXAREACAR 9.501618 LAYER Metal2 ; + PORT + LAYER Metal2 ; + RECT 180.01 0 180.27 0.26 ; + END + END A_BM[10] + PIN A_BIST_BM[21] + DIRECTION INPUT ; + USE SIGNAL ; + ANTENNAPARTIALMETALAREA 1.7602 LAYER Metal2 ; + ANTENNAMODEL OXIDE1 ; + ANTENNAGATEAREA 0.20085 LAYER Metal2 ; + ANTENNAMAXAREACAR 9.678367 LAYER Metal2 ; + PORT + LAYER Metal2 ; + RECT 503.845 0 504.105 0.26 ; + END + END A_BIST_BM[21] + PIN A_BIST_BM[10] + DIRECTION INPUT ; + USE SIGNAL ; + ANTENNAPARTIALMETALAREA 1.7602 LAYER Metal2 ; + ANTENNAMODEL OXIDE1 ; + ANTENNAGATEAREA 0.20085 LAYER Metal2 ; + ANTENNAMAXAREACAR 9.678367 LAYER Metal2 ; + PORT + LAYER Metal2 ; + RECT 181.385 0 181.645 0.26 ; + END + END A_BIST_BM[10] + PIN A_DOUT[21] + DIRECTION OUTPUT ; + USE SIGNAL ; + ANTENNAPARTIALMETALAREA 4.8256 LAYER Metal2 ; + ANTENNADIFFAREA 0.988 LAYER Metal2 ; + PORT + LAYER Metal2 ; + RECT 489.41 0 489.67 0.26 ; + END + END A_DOUT[21] + PIN A_DOUT[10] + DIRECTION OUTPUT ; + USE SIGNAL ; + ANTENNAPARTIALMETALAREA 4.8256 LAYER Metal2 ; + ANTENNADIFFAREA 0.988 LAYER Metal2 ; + PORT + LAYER Metal2 ; + RECT 195.82 0 196.08 0.26 ; + END + END A_DOUT[10] + PIN B_DIN[21] + DIRECTION INPUT ; + USE SIGNAL ; + ANTENNAPARTIALMETALAREA 2.925 LAYER Metal2 ; + ANTENNAMODEL OXIDE1 ; + ANTENNAGATEAREA 0.20085 LAYER Metal2 ; + ANTENNAMAXAREACAR 15.469256 LAYER Metal2 ; + PORT + LAYER Metal2 ; + RECT 499.1 0 499.36 0.26 ; + END + END B_DIN[21] + PIN B_DIN[10] + DIRECTION INPUT ; + USE SIGNAL ; + ANTENNAPARTIALMETALAREA 2.925 LAYER Metal2 ; + ANTENNAMODEL OXIDE1 ; + ANTENNAGATEAREA 0.20085 LAYER Metal2 ; + ANTENNAMAXAREACAR 15.469256 LAYER Metal2 ; + PORT + LAYER Metal2 ; + RECT 186.13 0 186.39 0.26 ; + END + END B_DIN[10] + PIN B_BIST_DIN[21] + DIRECTION INPUT ; + USE SIGNAL ; + ANTENNAPARTIALMETALAREA 2.9445 LAYER Metal2 ; + ANTENNAMODEL OXIDE1 ; + ANTENNAGATEAREA 0.20085 LAYER Metal2 ; + ANTENNAMAXAREACAR 15.929052 LAYER Metal2 ; + PORT + LAYER Metal2 ; + RECT 497.57 0 497.83 0.26 ; + END + END B_BIST_DIN[21] + PIN B_BIST_DIN[10] + DIRECTION INPUT ; + USE SIGNAL ; + ANTENNAPARTIALMETALAREA 2.9445 LAYER Metal2 ; + ANTENNAMODEL OXIDE1 ; + ANTENNAGATEAREA 0.20085 LAYER Metal2 ; + ANTENNAMAXAREACAR 15.929052 LAYER Metal2 ; + PORT + LAYER Metal2 ; + RECT 187.66 0 187.92 0.26 ; + END + END B_BIST_DIN[10] + PIN B_BM[21] + DIRECTION INPUT ; + USE SIGNAL ; + ANTENNAPARTIALMETALAREA 0.7007 LAYER Metal2 ; + ANTENNAMODEL OXIDE1 ; + ANTENNAGATEAREA 0.20085 LAYER Metal2 ; + ANTENNAMAXAREACAR 4.394822 LAYER Metal2 ; + PORT + LAYER Metal2 ; + RECT 490.585 0 490.845 0.26 ; + END + END B_BM[21] + PIN B_BM[10] + DIRECTION INPUT ; + USE SIGNAL ; + ANTENNAPARTIALMETALAREA 0.7007 LAYER Metal2 ; + ANTENNAMODEL OXIDE1 ; + ANTENNAGATEAREA 0.20085 LAYER Metal2 ; + ANTENNAMAXAREACAR 4.394822 LAYER Metal2 ; + PORT + LAYER Metal2 ; + RECT 194.645 0 194.905 0.26 ; + END + END B_BM[10] + PIN B_BIST_BM[21] + DIRECTION INPUT ; + USE SIGNAL ; + ANTENNAPARTIALMETALAREA 0.7007 LAYER Metal2 ; + ANTENNAMODEL OXIDE1 ; + ANTENNAGATEAREA 0.20085 LAYER Metal2 ; + ANTENNAMAXAREACAR 4.394822 LAYER Metal2 ; + PORT + LAYER Metal2 ; + RECT 492.115 0 492.375 0.26 ; + END + END B_BIST_BM[21] + PIN B_BIST_BM[10] + DIRECTION INPUT ; + USE SIGNAL ; + ANTENNAPARTIALMETALAREA 0.7007 LAYER Metal2 ; + ANTENNAMODEL OXIDE1 ; + ANTENNAGATEAREA 0.20085 LAYER Metal2 ; + ANTENNAMAXAREACAR 4.394822 LAYER Metal2 ; + PORT + LAYER Metal2 ; + RECT 193.115 0 193.375 0.26 ; + END + END B_BIST_BM[10] + PIN B_DOUT[21] + DIRECTION OUTPUT ; + USE SIGNAL ; + ANTENNAPARTIALMETALAREA 4.836 LAYER Metal2 ; + ANTENNADIFFAREA 0.988 LAYER Metal2 ; + PORT + LAYER Metal2 ; + RECT 506.24 0 506.5 0.26 ; + END + END B_DOUT[21] + PIN B_DOUT[10] + DIRECTION OUTPUT ; + USE SIGNAL ; + ANTENNAPARTIALMETALAREA 4.836 LAYER Metal2 ; + ANTENNADIFFAREA 0.988 LAYER Metal2 ; + PORT + LAYER Metal2 ; + RECT 178.99 0 179.25 0.26 ; + END + END B_DOUT[10] + PIN A_DIN[22] + DIRECTION INPUT ; + USE SIGNAL ; + ANTENNAPARTIALMETALAREA 3.9091 LAYER Metal2 ; + ANTENNAMODEL OXIDE1 ; + ANTENNAGATEAREA 0.20085 LAYER Metal2 ; + ANTENNAMAXAREACAR 20.368932 LAYER Metal2 ; + PORT + LAYER Metal2 ; + RECT 514.23 0 514.49 0.26 ; + END + END A_DIN[22] + PIN A_DIN[9] + DIRECTION INPUT ; + USE SIGNAL ; + ANTENNAPARTIALMETALAREA 3.9091 LAYER Metal2 ; + ANTENNAMODEL OXIDE1 ; + ANTENNAGATEAREA 0.20085 LAYER Metal2 ; + ANTENNAMAXAREACAR 20.368932 LAYER Metal2 ; + PORT + LAYER Metal2 ; + RECT 171 0 171.26 0.26 ; + END + END A_DIN[9] + PIN A_BIST_DIN[22] + DIRECTION INPUT ; + USE SIGNAL ; + ANTENNAPARTIALMETALAREA 4.136375 LAYER Metal2 ; + ANTENNAMODEL OXIDE1 ; + ANTENNAGATEAREA 0.20085 LAYER Metal2 ; + ANTENNAMAXAREACAR 21.874907 LAYER Metal2 ; + PORT + LAYER Metal2 ; + RECT 514.74 0 515 0.26 ; + END + END A_BIST_DIN[22] + PIN A_BIST_DIN[9] + DIRECTION INPUT ; + USE SIGNAL ; + ANTENNAPARTIALMETALAREA 4.136375 LAYER Metal2 ; + ANTENNAMODEL OXIDE1 ; + ANTENNAGATEAREA 0.20085 LAYER Metal2 ; + ANTENNAMAXAREACAR 21.874907 LAYER Metal2 ; + PORT + LAYER Metal2 ; + RECT 170.49 0 170.75 0.26 ; + END + END A_BIST_DIN[9] + PIN A_BM[22] + DIRECTION INPUT ; + USE SIGNAL ; + ANTENNAPARTIALMETALAREA 1.7264 LAYER Metal2 ; + ANTENNAMODEL OXIDE1 ; + ANTENNAGATEAREA 0.20085 LAYER Metal2 ; + ANTENNAMAXAREACAR 9.501618 LAYER Metal2 ; + PORT + LAYER Metal2 ; + RECT 522.9 0 523.16 0.26 ; + END + END A_BM[22] + PIN A_BM[9] + DIRECTION INPUT ; + USE SIGNAL ; + ANTENNAPARTIALMETALAREA 1.7264 LAYER Metal2 ; + ANTENNAMODEL OXIDE1 ; + ANTENNAGATEAREA 0.20085 LAYER Metal2 ; + ANTENNAMAXAREACAR 9.501618 LAYER Metal2 ; + PORT + LAYER Metal2 ; + RECT 162.33 0 162.59 0.26 ; + END + END A_BM[9] + PIN A_BIST_BM[22] + DIRECTION INPUT ; + USE SIGNAL ; + ANTENNAPARTIALMETALAREA 1.7602 LAYER Metal2 ; + ANTENNAMODEL OXIDE1 ; + ANTENNAGATEAREA 0.20085 LAYER Metal2 ; + ANTENNAMAXAREACAR 9.678367 LAYER Metal2 ; + PORT + LAYER Metal2 ; + RECT 521.525 0 521.785 0.26 ; + END + END A_BIST_BM[22] + PIN A_BIST_BM[9] + DIRECTION INPUT ; + USE SIGNAL ; + ANTENNAPARTIALMETALAREA 1.7602 LAYER Metal2 ; + ANTENNAMODEL OXIDE1 ; + ANTENNAGATEAREA 0.20085 LAYER Metal2 ; + ANTENNAMAXAREACAR 9.678367 LAYER Metal2 ; + PORT + LAYER Metal2 ; + RECT 163.705 0 163.965 0.26 ; + END + END A_BIST_BM[9] + PIN A_DOUT[22] + DIRECTION OUTPUT ; + USE SIGNAL ; + ANTENNAPARTIALMETALAREA 4.8256 LAYER Metal2 ; + ANTENNADIFFAREA 0.988 LAYER Metal2 ; + PORT + LAYER Metal2 ; + RECT 507.09 0 507.35 0.26 ; + END + END A_DOUT[22] + PIN A_DOUT[9] + DIRECTION OUTPUT ; + USE SIGNAL ; + ANTENNAPARTIALMETALAREA 4.8256 LAYER Metal2 ; + ANTENNADIFFAREA 0.988 LAYER Metal2 ; + PORT + LAYER Metal2 ; + RECT 178.14 0 178.4 0.26 ; + END + END A_DOUT[9] + PIN B_DIN[22] + DIRECTION INPUT ; + USE SIGNAL ; + ANTENNAPARTIALMETALAREA 2.925 LAYER Metal2 ; + ANTENNAMODEL OXIDE1 ; + ANTENNAGATEAREA 0.20085 LAYER Metal2 ; + ANTENNAMAXAREACAR 15.469256 LAYER Metal2 ; + PORT + LAYER Metal2 ; + RECT 516.78 0 517.04 0.26 ; + END + END B_DIN[22] + PIN B_DIN[9] + DIRECTION INPUT ; + USE SIGNAL ; + ANTENNAPARTIALMETALAREA 2.925 LAYER Metal2 ; + ANTENNAMODEL OXIDE1 ; + ANTENNAGATEAREA 0.20085 LAYER Metal2 ; + ANTENNAMAXAREACAR 15.469256 LAYER Metal2 ; + PORT + LAYER Metal2 ; + RECT 168.45 0 168.71 0.26 ; + END + END B_DIN[9] + PIN B_BIST_DIN[22] + DIRECTION INPUT ; + USE SIGNAL ; + ANTENNAPARTIALMETALAREA 2.9445 LAYER Metal2 ; + ANTENNAMODEL OXIDE1 ; + ANTENNAGATEAREA 0.20085 LAYER Metal2 ; + ANTENNAMAXAREACAR 15.929052 LAYER Metal2 ; + PORT + LAYER Metal2 ; + RECT 515.25 0 515.51 0.26 ; + END + END B_BIST_DIN[22] + PIN B_BIST_DIN[9] + DIRECTION INPUT ; + USE SIGNAL ; + ANTENNAPARTIALMETALAREA 2.9445 LAYER Metal2 ; + ANTENNAMODEL OXIDE1 ; + ANTENNAGATEAREA 0.20085 LAYER Metal2 ; + ANTENNAMAXAREACAR 15.929052 LAYER Metal2 ; + PORT + LAYER Metal2 ; + RECT 169.98 0 170.24 0.26 ; + END + END B_BIST_DIN[9] + PIN B_BM[22] + DIRECTION INPUT ; + USE SIGNAL ; + ANTENNAPARTIALMETALAREA 0.7007 LAYER Metal2 ; + ANTENNAMODEL OXIDE1 ; + ANTENNAGATEAREA 0.20085 LAYER Metal2 ; + ANTENNAMAXAREACAR 4.394822 LAYER Metal2 ; + PORT + LAYER Metal2 ; + RECT 508.265 0 508.525 0.26 ; + END + END B_BM[22] + PIN B_BM[9] + DIRECTION INPUT ; + USE SIGNAL ; + ANTENNAPARTIALMETALAREA 0.7007 LAYER Metal2 ; + ANTENNAMODEL OXIDE1 ; + ANTENNAGATEAREA 0.20085 LAYER Metal2 ; + ANTENNAMAXAREACAR 4.394822 LAYER Metal2 ; + PORT + LAYER Metal2 ; + RECT 176.965 0 177.225 0.26 ; + END + END B_BM[9] + PIN B_BIST_BM[22] + DIRECTION INPUT ; + USE SIGNAL ; + ANTENNAPARTIALMETALAREA 0.7007 LAYER Metal2 ; + ANTENNAMODEL OXIDE1 ; + ANTENNAGATEAREA 0.20085 LAYER Metal2 ; + ANTENNAMAXAREACAR 4.394822 LAYER Metal2 ; + PORT + LAYER Metal2 ; + RECT 509.795 0 510.055 0.26 ; + END + END B_BIST_BM[22] + PIN B_BIST_BM[9] + DIRECTION INPUT ; + USE SIGNAL ; + ANTENNAPARTIALMETALAREA 0.7007 LAYER Metal2 ; + ANTENNAMODEL OXIDE1 ; + ANTENNAGATEAREA 0.20085 LAYER Metal2 ; + ANTENNAMAXAREACAR 4.394822 LAYER Metal2 ; + PORT + LAYER Metal2 ; + RECT 175.435 0 175.695 0.26 ; + END + END B_BIST_BM[9] + PIN B_DOUT[22] + DIRECTION OUTPUT ; + USE SIGNAL ; + ANTENNAPARTIALMETALAREA 4.836 LAYER Metal2 ; + ANTENNADIFFAREA 0.988 LAYER Metal2 ; + PORT + LAYER Metal2 ; + RECT 523.92 0 524.18 0.26 ; + END + END B_DOUT[22] + PIN B_DOUT[9] + DIRECTION OUTPUT ; + USE SIGNAL ; + ANTENNAPARTIALMETALAREA 4.836 LAYER Metal2 ; + ANTENNADIFFAREA 0.988 LAYER Metal2 ; + PORT + LAYER Metal2 ; + RECT 161.31 0 161.57 0.26 ; + END + END B_DOUT[9] + PIN A_DIN[23] + DIRECTION INPUT ; + USE SIGNAL ; + ANTENNAPARTIALMETALAREA 3.9091 LAYER Metal2 ; + ANTENNAMODEL OXIDE1 ; + ANTENNAGATEAREA 0.20085 LAYER Metal2 ; + ANTENNAMAXAREACAR 20.368932 LAYER Metal2 ; + PORT + LAYER Metal2 ; + RECT 531.91 0 532.17 0.26 ; + END + END A_DIN[23] + PIN A_DIN[8] + DIRECTION INPUT ; + USE SIGNAL ; + ANTENNAPARTIALMETALAREA 3.9091 LAYER Metal2 ; + ANTENNAMODEL OXIDE1 ; + ANTENNAGATEAREA 0.20085 LAYER Metal2 ; + ANTENNAMAXAREACAR 20.368932 LAYER Metal2 ; + PORT + LAYER Metal2 ; + RECT 153.32 0 153.58 0.26 ; + END + END A_DIN[8] + PIN A_BIST_DIN[23] + DIRECTION INPUT ; + USE SIGNAL ; + ANTENNAPARTIALMETALAREA 4.136375 LAYER Metal2 ; + ANTENNAMODEL OXIDE1 ; + ANTENNAGATEAREA 0.20085 LAYER Metal2 ; + ANTENNAMAXAREACAR 21.874907 LAYER Metal2 ; + PORT + LAYER Metal2 ; + RECT 532.42 0 532.68 0.26 ; + END + END A_BIST_DIN[23] + PIN A_BIST_DIN[8] + DIRECTION INPUT ; + USE SIGNAL ; + ANTENNAPARTIALMETALAREA 4.136375 LAYER Metal2 ; + ANTENNAMODEL OXIDE1 ; + ANTENNAGATEAREA 0.20085 LAYER Metal2 ; + ANTENNAMAXAREACAR 21.874907 LAYER Metal2 ; + PORT + LAYER Metal2 ; + RECT 152.81 0 153.07 0.26 ; + END + END A_BIST_DIN[8] + PIN A_BM[23] + DIRECTION INPUT ; + USE SIGNAL ; + ANTENNAPARTIALMETALAREA 1.7264 LAYER Metal2 ; + ANTENNAMODEL OXIDE1 ; + ANTENNAGATEAREA 0.20085 LAYER Metal2 ; + ANTENNAMAXAREACAR 9.501618 LAYER Metal2 ; + PORT + LAYER Metal2 ; + RECT 540.58 0 540.84 0.26 ; + END + END A_BM[23] + PIN A_BM[8] + DIRECTION INPUT ; + USE SIGNAL ; + ANTENNAPARTIALMETALAREA 1.7264 LAYER Metal2 ; + ANTENNAMODEL OXIDE1 ; + ANTENNAGATEAREA 0.20085 LAYER Metal2 ; + ANTENNAMAXAREACAR 9.501618 LAYER Metal2 ; + PORT + LAYER Metal2 ; + RECT 144.65 0 144.91 0.26 ; + END + END A_BM[8] + PIN A_BIST_BM[23] + DIRECTION INPUT ; + USE SIGNAL ; + ANTENNAPARTIALMETALAREA 1.7602 LAYER Metal2 ; + ANTENNAMODEL OXIDE1 ; + ANTENNAGATEAREA 0.20085 LAYER Metal2 ; + ANTENNAMAXAREACAR 9.678367 LAYER Metal2 ; + PORT + LAYER Metal2 ; + RECT 539.205 0 539.465 0.26 ; + END + END A_BIST_BM[23] + PIN A_BIST_BM[8] + DIRECTION INPUT ; + USE SIGNAL ; + ANTENNAPARTIALMETALAREA 1.7602 LAYER Metal2 ; + ANTENNAMODEL OXIDE1 ; + ANTENNAGATEAREA 0.20085 LAYER Metal2 ; + ANTENNAMAXAREACAR 9.678367 LAYER Metal2 ; + PORT + LAYER Metal2 ; + RECT 146.025 0 146.285 0.26 ; + END + END A_BIST_BM[8] + PIN A_DOUT[23] + DIRECTION OUTPUT ; + USE SIGNAL ; + ANTENNAPARTIALMETALAREA 4.8256 LAYER Metal2 ; + ANTENNADIFFAREA 0.988 LAYER Metal2 ; + PORT + LAYER Metal2 ; + RECT 524.77 0 525.03 0.26 ; + END + END A_DOUT[23] + PIN A_DOUT[8] + DIRECTION OUTPUT ; + USE SIGNAL ; + ANTENNAPARTIALMETALAREA 4.8256 LAYER Metal2 ; + ANTENNADIFFAREA 0.988 LAYER Metal2 ; + PORT + LAYER Metal2 ; + RECT 160.46 0 160.72 0.26 ; + END + END A_DOUT[8] + PIN B_DIN[23] + DIRECTION INPUT ; + USE SIGNAL ; + ANTENNAPARTIALMETALAREA 2.925 LAYER Metal2 ; + ANTENNAMODEL OXIDE1 ; + ANTENNAGATEAREA 0.20085 LAYER Metal2 ; + ANTENNAMAXAREACAR 15.469256 LAYER Metal2 ; + PORT + LAYER Metal2 ; + RECT 534.46 0 534.72 0.26 ; + END + END B_DIN[23] + PIN B_DIN[8] + DIRECTION INPUT ; + USE SIGNAL ; + ANTENNAPARTIALMETALAREA 2.925 LAYER Metal2 ; + ANTENNAMODEL OXIDE1 ; + ANTENNAGATEAREA 0.20085 LAYER Metal2 ; + ANTENNAMAXAREACAR 15.469256 LAYER Metal2 ; + PORT + LAYER Metal2 ; + RECT 150.77 0 151.03 0.26 ; + END + END B_DIN[8] + PIN B_BIST_DIN[23] + DIRECTION INPUT ; + USE SIGNAL ; + ANTENNAPARTIALMETALAREA 2.9445 LAYER Metal2 ; + ANTENNAMODEL OXIDE1 ; + ANTENNAGATEAREA 0.20085 LAYER Metal2 ; + ANTENNAMAXAREACAR 15.929052 LAYER Metal2 ; + PORT + LAYER Metal2 ; + RECT 532.93 0 533.19 0.26 ; + END + END B_BIST_DIN[23] + PIN B_BIST_DIN[8] + DIRECTION INPUT ; + USE SIGNAL ; + ANTENNAPARTIALMETALAREA 2.9445 LAYER Metal2 ; + ANTENNAMODEL OXIDE1 ; + ANTENNAGATEAREA 0.20085 LAYER Metal2 ; + ANTENNAMAXAREACAR 15.929052 LAYER Metal2 ; + PORT + LAYER Metal2 ; + RECT 152.3 0 152.56 0.26 ; + END + END B_BIST_DIN[8] + PIN B_BM[23] + DIRECTION INPUT ; + USE SIGNAL ; + ANTENNAPARTIALMETALAREA 0.7007 LAYER Metal2 ; + ANTENNAMODEL OXIDE1 ; + ANTENNAGATEAREA 0.20085 LAYER Metal2 ; + ANTENNAMAXAREACAR 4.394822 LAYER Metal2 ; + PORT + LAYER Metal2 ; + RECT 525.945 0 526.205 0.26 ; + END + END B_BM[23] + PIN B_BM[8] + DIRECTION INPUT ; + USE SIGNAL ; + ANTENNAPARTIALMETALAREA 0.7007 LAYER Metal2 ; + ANTENNAMODEL OXIDE1 ; + ANTENNAGATEAREA 0.20085 LAYER Metal2 ; + ANTENNAMAXAREACAR 4.394822 LAYER Metal2 ; + PORT + LAYER Metal2 ; + RECT 159.285 0 159.545 0.26 ; + END + END B_BM[8] + PIN B_BIST_BM[23] + DIRECTION INPUT ; + USE SIGNAL ; + ANTENNAPARTIALMETALAREA 0.7007 LAYER Metal2 ; + ANTENNAMODEL OXIDE1 ; + ANTENNAGATEAREA 0.20085 LAYER Metal2 ; + ANTENNAMAXAREACAR 4.394822 LAYER Metal2 ; + PORT + LAYER Metal2 ; + RECT 527.475 0 527.735 0.26 ; + END + END B_BIST_BM[23] + PIN B_BIST_BM[8] + DIRECTION INPUT ; + USE SIGNAL ; + ANTENNAPARTIALMETALAREA 0.7007 LAYER Metal2 ; + ANTENNAMODEL OXIDE1 ; + ANTENNAGATEAREA 0.20085 LAYER Metal2 ; + ANTENNAMAXAREACAR 4.394822 LAYER Metal2 ; + PORT + LAYER Metal2 ; + RECT 157.755 0 158.015 0.26 ; + END + END B_BIST_BM[8] + PIN B_DOUT[23] + DIRECTION OUTPUT ; + USE SIGNAL ; + ANTENNAPARTIALMETALAREA 4.836 LAYER Metal2 ; + ANTENNADIFFAREA 0.988 LAYER Metal2 ; + PORT + LAYER Metal2 ; + RECT 541.6 0 541.86 0.26 ; + END + END B_DOUT[23] + PIN B_DOUT[8] + DIRECTION OUTPUT ; + USE SIGNAL ; + ANTENNAPARTIALMETALAREA 4.836 LAYER Metal2 ; + ANTENNADIFFAREA 0.988 LAYER Metal2 ; + PORT + LAYER Metal2 ; + RECT 143.63 0 143.89 0.26 ; + END + END B_DOUT[8] + PIN A_DIN[24] + DIRECTION INPUT ; + USE SIGNAL ; + ANTENNAPARTIALMETALAREA 3.9091 LAYER Metal2 ; + ANTENNAMODEL OXIDE1 ; + ANTENNAGATEAREA 0.20085 LAYER Metal2 ; + ANTENNAMAXAREACAR 20.368932 LAYER Metal2 ; + PORT + LAYER Metal2 ; + RECT 549.59 0 549.85 0.26 ; + END + END A_DIN[24] + PIN A_DIN[7] + DIRECTION INPUT ; + USE SIGNAL ; + ANTENNAPARTIALMETALAREA 3.9091 LAYER Metal2 ; + ANTENNAMODEL OXIDE1 ; + ANTENNAGATEAREA 0.20085 LAYER Metal2 ; + ANTENNAMAXAREACAR 20.368932 LAYER Metal2 ; + PORT + LAYER Metal2 ; + RECT 135.64 0 135.9 0.26 ; + END + END A_DIN[7] + PIN A_BIST_DIN[24] + DIRECTION INPUT ; + USE SIGNAL ; + ANTENNAPARTIALMETALAREA 4.136375 LAYER Metal2 ; + ANTENNAMODEL OXIDE1 ; + ANTENNAGATEAREA 0.20085 LAYER Metal2 ; + ANTENNAMAXAREACAR 21.874907 LAYER Metal2 ; + PORT + LAYER Metal2 ; + RECT 550.1 0 550.36 0.26 ; + END + END A_BIST_DIN[24] + PIN A_BIST_DIN[7] + DIRECTION INPUT ; + USE SIGNAL ; + ANTENNAPARTIALMETALAREA 4.136375 LAYER Metal2 ; + ANTENNAMODEL OXIDE1 ; + ANTENNAGATEAREA 0.20085 LAYER Metal2 ; + ANTENNAMAXAREACAR 21.874907 LAYER Metal2 ; + PORT + LAYER Metal2 ; + RECT 135.13 0 135.39 0.26 ; + END + END A_BIST_DIN[7] + PIN A_BM[24] + DIRECTION INPUT ; + USE SIGNAL ; + ANTENNAPARTIALMETALAREA 1.7264 LAYER Metal2 ; + ANTENNAMODEL OXIDE1 ; + ANTENNAGATEAREA 0.20085 LAYER Metal2 ; + ANTENNAMAXAREACAR 9.501618 LAYER Metal2 ; + PORT + LAYER Metal2 ; + RECT 558.26 0 558.52 0.26 ; + END + END A_BM[24] + PIN A_BM[7] + DIRECTION INPUT ; + USE SIGNAL ; + ANTENNAPARTIALMETALAREA 1.7264 LAYER Metal2 ; + ANTENNAMODEL OXIDE1 ; + ANTENNAGATEAREA 0.20085 LAYER Metal2 ; + ANTENNAMAXAREACAR 9.501618 LAYER Metal2 ; + PORT + LAYER Metal2 ; + RECT 126.97 0 127.23 0.26 ; + END + END A_BM[7] + PIN A_BIST_BM[24] + DIRECTION INPUT ; + USE SIGNAL ; + ANTENNAPARTIALMETALAREA 1.7602 LAYER Metal2 ; + ANTENNAMODEL OXIDE1 ; + ANTENNAGATEAREA 0.20085 LAYER Metal2 ; + ANTENNAMAXAREACAR 9.678367 LAYER Metal2 ; + PORT + LAYER Metal2 ; + RECT 556.885 0 557.145 0.26 ; + END + END A_BIST_BM[24] + PIN A_BIST_BM[7] + DIRECTION INPUT ; + USE SIGNAL ; + ANTENNAPARTIALMETALAREA 1.7602 LAYER Metal2 ; + ANTENNAMODEL OXIDE1 ; + ANTENNAGATEAREA 0.20085 LAYER Metal2 ; + ANTENNAMAXAREACAR 9.678367 LAYER Metal2 ; + PORT + LAYER Metal2 ; + RECT 128.345 0 128.605 0.26 ; + END + END A_BIST_BM[7] + PIN A_DOUT[24] + DIRECTION OUTPUT ; + USE SIGNAL ; + ANTENNAPARTIALMETALAREA 4.8256 LAYER Metal2 ; + ANTENNADIFFAREA 0.988 LAYER Metal2 ; + PORT + LAYER Metal2 ; + RECT 542.45 0 542.71 0.26 ; + END + END A_DOUT[24] + PIN A_DOUT[7] + DIRECTION OUTPUT ; + USE SIGNAL ; + ANTENNAPARTIALMETALAREA 4.8256 LAYER Metal2 ; + ANTENNADIFFAREA 0.988 LAYER Metal2 ; + PORT + LAYER Metal2 ; + RECT 142.78 0 143.04 0.26 ; + END + END A_DOUT[7] + PIN B_DIN[24] + DIRECTION INPUT ; + USE SIGNAL ; + ANTENNAPARTIALMETALAREA 2.925 LAYER Metal2 ; + ANTENNAMODEL OXIDE1 ; + ANTENNAGATEAREA 0.20085 LAYER Metal2 ; + ANTENNAMAXAREACAR 15.469256 LAYER Metal2 ; + PORT + LAYER Metal2 ; + RECT 552.14 0 552.4 0.26 ; + END + END B_DIN[24] + PIN B_DIN[7] + DIRECTION INPUT ; + USE SIGNAL ; + ANTENNAPARTIALMETALAREA 2.925 LAYER Metal2 ; + ANTENNAMODEL OXIDE1 ; + ANTENNAGATEAREA 0.20085 LAYER Metal2 ; + ANTENNAMAXAREACAR 15.469256 LAYER Metal2 ; + PORT + LAYER Metal2 ; + RECT 133.09 0 133.35 0.26 ; + END + END B_DIN[7] + PIN B_BIST_DIN[24] + DIRECTION INPUT ; + USE SIGNAL ; + ANTENNAPARTIALMETALAREA 2.9445 LAYER Metal2 ; + ANTENNAMODEL OXIDE1 ; + ANTENNAGATEAREA 0.20085 LAYER Metal2 ; + ANTENNAMAXAREACAR 15.929052 LAYER Metal2 ; + PORT + LAYER Metal2 ; + RECT 550.61 0 550.87 0.26 ; + END + END B_BIST_DIN[24] + PIN B_BIST_DIN[7] + DIRECTION INPUT ; + USE SIGNAL ; + ANTENNAPARTIALMETALAREA 2.9445 LAYER Metal2 ; + ANTENNAMODEL OXIDE1 ; + ANTENNAGATEAREA 0.20085 LAYER Metal2 ; + ANTENNAMAXAREACAR 15.929052 LAYER Metal2 ; + PORT + LAYER Metal2 ; + RECT 134.62 0 134.88 0.26 ; + END + END B_BIST_DIN[7] + PIN B_BM[24] + DIRECTION INPUT ; + USE SIGNAL ; + ANTENNAPARTIALMETALAREA 0.7007 LAYER Metal2 ; + ANTENNAMODEL OXIDE1 ; + ANTENNAGATEAREA 0.20085 LAYER Metal2 ; + ANTENNAMAXAREACAR 4.394822 LAYER Metal2 ; + PORT + LAYER Metal2 ; + RECT 543.625 0 543.885 0.26 ; + END + END B_BM[24] + PIN B_BM[7] + DIRECTION INPUT ; + USE SIGNAL ; + ANTENNAPARTIALMETALAREA 0.7007 LAYER Metal2 ; + ANTENNAMODEL OXIDE1 ; + ANTENNAGATEAREA 0.20085 LAYER Metal2 ; + ANTENNAMAXAREACAR 4.394822 LAYER Metal2 ; + PORT + LAYER Metal2 ; + RECT 141.605 0 141.865 0.26 ; + END + END B_BM[7] + PIN B_BIST_BM[24] + DIRECTION INPUT ; + USE SIGNAL ; + ANTENNAPARTIALMETALAREA 0.7007 LAYER Metal2 ; + ANTENNAMODEL OXIDE1 ; + ANTENNAGATEAREA 0.20085 LAYER Metal2 ; + ANTENNAMAXAREACAR 4.394822 LAYER Metal2 ; + PORT + LAYER Metal2 ; + RECT 545.155 0 545.415 0.26 ; + END + END B_BIST_BM[24] + PIN B_BIST_BM[7] + DIRECTION INPUT ; + USE SIGNAL ; + ANTENNAPARTIALMETALAREA 0.7007 LAYER Metal2 ; + ANTENNAMODEL OXIDE1 ; + ANTENNAGATEAREA 0.20085 LAYER Metal2 ; + ANTENNAMAXAREACAR 4.394822 LAYER Metal2 ; + PORT + LAYER Metal2 ; + RECT 140.075 0 140.335 0.26 ; + END + END B_BIST_BM[7] + PIN B_DOUT[24] + DIRECTION OUTPUT ; + USE SIGNAL ; + ANTENNAPARTIALMETALAREA 4.836 LAYER Metal2 ; + ANTENNADIFFAREA 0.988 LAYER Metal2 ; + PORT + LAYER Metal2 ; + RECT 559.28 0 559.54 0.26 ; + END + END B_DOUT[24] + PIN B_DOUT[7] + DIRECTION OUTPUT ; + USE SIGNAL ; + ANTENNAPARTIALMETALAREA 4.836 LAYER Metal2 ; + ANTENNADIFFAREA 0.988 LAYER Metal2 ; + PORT + LAYER Metal2 ; + RECT 125.95 0 126.21 0.26 ; + END + END B_DOUT[7] + PIN A_DIN[25] + DIRECTION INPUT ; + USE SIGNAL ; + ANTENNAPARTIALMETALAREA 3.9091 LAYER Metal2 ; + ANTENNAMODEL OXIDE1 ; + ANTENNAGATEAREA 0.20085 LAYER Metal2 ; + ANTENNAMAXAREACAR 20.368932 LAYER Metal2 ; + PORT + LAYER Metal2 ; + RECT 567.27 0 567.53 0.26 ; + END + END A_DIN[25] + PIN A_DIN[6] + DIRECTION INPUT ; + USE SIGNAL ; + ANTENNAPARTIALMETALAREA 3.9091 LAYER Metal2 ; + ANTENNAMODEL OXIDE1 ; + ANTENNAGATEAREA 0.20085 LAYER Metal2 ; + ANTENNAMAXAREACAR 20.368932 LAYER Metal2 ; + PORT + LAYER Metal2 ; + RECT 117.96 0 118.22 0.26 ; + END + END A_DIN[6] + PIN A_BIST_DIN[25] + DIRECTION INPUT ; + USE SIGNAL ; + ANTENNAPARTIALMETALAREA 4.136375 LAYER Metal2 ; + ANTENNAMODEL OXIDE1 ; + ANTENNAGATEAREA 0.20085 LAYER Metal2 ; + ANTENNAMAXAREACAR 21.874907 LAYER Metal2 ; + PORT + LAYER Metal2 ; + RECT 567.78 0 568.04 0.26 ; + END + END A_BIST_DIN[25] + PIN A_BIST_DIN[6] + DIRECTION INPUT ; + USE SIGNAL ; + ANTENNAPARTIALMETALAREA 4.136375 LAYER Metal2 ; + ANTENNAMODEL OXIDE1 ; + ANTENNAGATEAREA 0.20085 LAYER Metal2 ; + ANTENNAMAXAREACAR 21.874907 LAYER Metal2 ; + PORT + LAYER Metal2 ; + RECT 117.45 0 117.71 0.26 ; + END + END A_BIST_DIN[6] + PIN A_BM[25] + DIRECTION INPUT ; + USE SIGNAL ; + ANTENNAPARTIALMETALAREA 1.7264 LAYER Metal2 ; + ANTENNAMODEL OXIDE1 ; + ANTENNAGATEAREA 0.20085 LAYER Metal2 ; + ANTENNAMAXAREACAR 9.501618 LAYER Metal2 ; + PORT + LAYER Metal2 ; + RECT 575.94 0 576.2 0.26 ; + END + END A_BM[25] + PIN A_BM[6] + DIRECTION INPUT ; + USE SIGNAL ; + ANTENNAPARTIALMETALAREA 1.7264 LAYER Metal2 ; + ANTENNAMODEL OXIDE1 ; + ANTENNAGATEAREA 0.20085 LAYER Metal2 ; + ANTENNAMAXAREACAR 9.501618 LAYER Metal2 ; + PORT + LAYER Metal2 ; + RECT 109.29 0 109.55 0.26 ; + END + END A_BM[6] + PIN A_BIST_BM[25] + DIRECTION INPUT ; + USE SIGNAL ; + ANTENNAPARTIALMETALAREA 1.7602 LAYER Metal2 ; + ANTENNAMODEL OXIDE1 ; + ANTENNAGATEAREA 0.20085 LAYER Metal2 ; + ANTENNAMAXAREACAR 9.678367 LAYER Metal2 ; + PORT + LAYER Metal2 ; + RECT 574.565 0 574.825 0.26 ; + END + END A_BIST_BM[25] + PIN A_BIST_BM[6] + DIRECTION INPUT ; + USE SIGNAL ; + ANTENNAPARTIALMETALAREA 1.7602 LAYER Metal2 ; + ANTENNAMODEL OXIDE1 ; + ANTENNAGATEAREA 0.20085 LAYER Metal2 ; + ANTENNAMAXAREACAR 9.678367 LAYER Metal2 ; + PORT + LAYER Metal2 ; + RECT 110.665 0 110.925 0.26 ; + END + END A_BIST_BM[6] + PIN A_DOUT[25] + DIRECTION OUTPUT ; + USE SIGNAL ; + ANTENNAPARTIALMETALAREA 4.8256 LAYER Metal2 ; + ANTENNADIFFAREA 0.988 LAYER Metal2 ; + PORT + LAYER Metal2 ; + RECT 560.13 0 560.39 0.26 ; + END + END A_DOUT[25] + PIN A_DOUT[6] + DIRECTION OUTPUT ; + USE SIGNAL ; + ANTENNAPARTIALMETALAREA 4.8256 LAYER Metal2 ; + ANTENNADIFFAREA 0.988 LAYER Metal2 ; + PORT + LAYER Metal2 ; + RECT 125.1 0 125.36 0.26 ; + END + END A_DOUT[6] + PIN B_DIN[25] + DIRECTION INPUT ; + USE SIGNAL ; + ANTENNAPARTIALMETALAREA 2.925 LAYER Metal2 ; + ANTENNAMODEL OXIDE1 ; + ANTENNAGATEAREA 0.20085 LAYER Metal2 ; + ANTENNAMAXAREACAR 15.469256 LAYER Metal2 ; + PORT + LAYER Metal2 ; + RECT 569.82 0 570.08 0.26 ; + END + END B_DIN[25] + PIN B_DIN[6] + DIRECTION INPUT ; + USE SIGNAL ; + ANTENNAPARTIALMETALAREA 2.925 LAYER Metal2 ; + ANTENNAMODEL OXIDE1 ; + ANTENNAGATEAREA 0.20085 LAYER Metal2 ; + ANTENNAMAXAREACAR 15.469256 LAYER Metal2 ; + PORT + LAYER Metal2 ; + RECT 115.41 0 115.67 0.26 ; + END + END B_DIN[6] + PIN B_BIST_DIN[25] + DIRECTION INPUT ; + USE SIGNAL ; + ANTENNAPARTIALMETALAREA 2.9445 LAYER Metal2 ; + ANTENNAMODEL OXIDE1 ; + ANTENNAGATEAREA 0.20085 LAYER Metal2 ; + ANTENNAMAXAREACAR 15.929052 LAYER Metal2 ; + PORT + LAYER Metal2 ; + RECT 568.29 0 568.55 0.26 ; + END + END B_BIST_DIN[25] + PIN B_BIST_DIN[6] + DIRECTION INPUT ; + USE SIGNAL ; + ANTENNAPARTIALMETALAREA 2.9445 LAYER Metal2 ; + ANTENNAMODEL OXIDE1 ; + ANTENNAGATEAREA 0.20085 LAYER Metal2 ; + ANTENNAMAXAREACAR 15.929052 LAYER Metal2 ; + PORT + LAYER Metal2 ; + RECT 116.94 0 117.2 0.26 ; + END + END B_BIST_DIN[6] + PIN B_BM[25] + DIRECTION INPUT ; + USE SIGNAL ; + ANTENNAPARTIALMETALAREA 0.7007 LAYER Metal2 ; + ANTENNAMODEL OXIDE1 ; + ANTENNAGATEAREA 0.20085 LAYER Metal2 ; + ANTENNAMAXAREACAR 4.394822 LAYER Metal2 ; + PORT + LAYER Metal2 ; + RECT 561.305 0 561.565 0.26 ; + END + END B_BM[25] + PIN B_BM[6] + DIRECTION INPUT ; + USE SIGNAL ; + ANTENNAPARTIALMETALAREA 0.7007 LAYER Metal2 ; + ANTENNAMODEL OXIDE1 ; + ANTENNAGATEAREA 0.20085 LAYER Metal2 ; + ANTENNAMAXAREACAR 4.394822 LAYER Metal2 ; + PORT + LAYER Metal2 ; + RECT 123.925 0 124.185 0.26 ; + END + END B_BM[6] + PIN B_BIST_BM[25] + DIRECTION INPUT ; + USE SIGNAL ; + ANTENNAPARTIALMETALAREA 0.7007 LAYER Metal2 ; + ANTENNAMODEL OXIDE1 ; + ANTENNAGATEAREA 0.20085 LAYER Metal2 ; + ANTENNAMAXAREACAR 4.394822 LAYER Metal2 ; + PORT + LAYER Metal2 ; + RECT 562.835 0 563.095 0.26 ; + END + END B_BIST_BM[25] + PIN B_BIST_BM[6] + DIRECTION INPUT ; + USE SIGNAL ; + ANTENNAPARTIALMETALAREA 0.7007 LAYER Metal2 ; + ANTENNAMODEL OXIDE1 ; + ANTENNAGATEAREA 0.20085 LAYER Metal2 ; + ANTENNAMAXAREACAR 4.394822 LAYER Metal2 ; + PORT + LAYER Metal2 ; + RECT 122.395 0 122.655 0.26 ; + END + END B_BIST_BM[6] + PIN B_DOUT[25] + DIRECTION OUTPUT ; + USE SIGNAL ; + ANTENNAPARTIALMETALAREA 4.836 LAYER Metal2 ; + ANTENNADIFFAREA 0.988 LAYER Metal2 ; + PORT + LAYER Metal2 ; + RECT 576.96 0 577.22 0.26 ; + END + END B_DOUT[25] + PIN B_DOUT[6] + DIRECTION OUTPUT ; + USE SIGNAL ; + ANTENNAPARTIALMETALAREA 4.836 LAYER Metal2 ; + ANTENNADIFFAREA 0.988 LAYER Metal2 ; + PORT + LAYER Metal2 ; + RECT 108.27 0 108.53 0.26 ; + END + END B_DOUT[6] + PIN A_DIN[26] + DIRECTION INPUT ; + USE SIGNAL ; + ANTENNAPARTIALMETALAREA 3.9091 LAYER Metal2 ; + ANTENNAMODEL OXIDE1 ; + ANTENNAGATEAREA 0.20085 LAYER Metal2 ; + ANTENNAMAXAREACAR 20.368932 LAYER Metal2 ; + PORT + LAYER Metal2 ; + RECT 584.95 0 585.21 0.26 ; + END + END A_DIN[26] + PIN A_DIN[5] + DIRECTION INPUT ; + USE SIGNAL ; + ANTENNAPARTIALMETALAREA 3.9091 LAYER Metal2 ; + ANTENNAMODEL OXIDE1 ; + ANTENNAGATEAREA 0.20085 LAYER Metal2 ; + ANTENNAMAXAREACAR 20.368932 LAYER Metal2 ; + PORT + LAYER Metal2 ; + RECT 100.28 0 100.54 0.26 ; + END + END A_DIN[5] + PIN A_BIST_DIN[26] + DIRECTION INPUT ; + USE SIGNAL ; + ANTENNAPARTIALMETALAREA 4.136375 LAYER Metal2 ; + ANTENNAMODEL OXIDE1 ; + ANTENNAGATEAREA 0.20085 LAYER Metal2 ; + ANTENNAMAXAREACAR 21.874907 LAYER Metal2 ; + PORT + LAYER Metal2 ; + RECT 585.46 0 585.72 0.26 ; + END + END A_BIST_DIN[26] + PIN A_BIST_DIN[5] + DIRECTION INPUT ; + USE SIGNAL ; + ANTENNAPARTIALMETALAREA 4.136375 LAYER Metal2 ; + ANTENNAMODEL OXIDE1 ; + ANTENNAGATEAREA 0.20085 LAYER Metal2 ; + ANTENNAMAXAREACAR 21.874907 LAYER Metal2 ; + PORT + LAYER Metal2 ; + RECT 99.77 0 100.03 0.26 ; + END + END A_BIST_DIN[5] + PIN A_BM[26] + DIRECTION INPUT ; + USE SIGNAL ; + ANTENNAPARTIALMETALAREA 1.7264 LAYER Metal2 ; + ANTENNAMODEL OXIDE1 ; + ANTENNAGATEAREA 0.20085 LAYER Metal2 ; + ANTENNAMAXAREACAR 9.501618 LAYER Metal2 ; + PORT + LAYER Metal2 ; + RECT 593.62 0 593.88 0.26 ; + END + END A_BM[26] + PIN A_BM[5] + DIRECTION INPUT ; + USE SIGNAL ; + ANTENNAPARTIALMETALAREA 1.7264 LAYER Metal2 ; + ANTENNAMODEL OXIDE1 ; + ANTENNAGATEAREA 0.20085 LAYER Metal2 ; + ANTENNAMAXAREACAR 9.501618 LAYER Metal2 ; + PORT + LAYER Metal2 ; + RECT 91.61 0 91.87 0.26 ; + END + END A_BM[5] + PIN A_BIST_BM[26] + DIRECTION INPUT ; + USE SIGNAL ; + ANTENNAPARTIALMETALAREA 1.7602 LAYER Metal2 ; + ANTENNAMODEL OXIDE1 ; + ANTENNAGATEAREA 0.20085 LAYER Metal2 ; + ANTENNAMAXAREACAR 9.678367 LAYER Metal2 ; + PORT + LAYER Metal2 ; + RECT 592.245 0 592.505 0.26 ; + END + END A_BIST_BM[26] + PIN A_BIST_BM[5] + DIRECTION INPUT ; + USE SIGNAL ; + ANTENNAPARTIALMETALAREA 1.7602 LAYER Metal2 ; + ANTENNAMODEL OXIDE1 ; + ANTENNAGATEAREA 0.20085 LAYER Metal2 ; + ANTENNAMAXAREACAR 9.678367 LAYER Metal2 ; + PORT + LAYER Metal2 ; + RECT 92.985 0 93.245 0.26 ; + END + END A_BIST_BM[5] + PIN A_DOUT[26] + DIRECTION OUTPUT ; + USE SIGNAL ; + ANTENNAPARTIALMETALAREA 4.8256 LAYER Metal2 ; + ANTENNADIFFAREA 0.988 LAYER Metal2 ; + PORT + LAYER Metal2 ; + RECT 577.81 0 578.07 0.26 ; + END + END A_DOUT[26] + PIN A_DOUT[5] + DIRECTION OUTPUT ; + USE SIGNAL ; + ANTENNAPARTIALMETALAREA 4.8256 LAYER Metal2 ; + ANTENNADIFFAREA 0.988 LAYER Metal2 ; + PORT + LAYER Metal2 ; + RECT 107.42 0 107.68 0.26 ; + END + END A_DOUT[5] + PIN B_DIN[26] + DIRECTION INPUT ; + USE SIGNAL ; + ANTENNAPARTIALMETALAREA 2.925 LAYER Metal2 ; + ANTENNAMODEL OXIDE1 ; + ANTENNAGATEAREA 0.20085 LAYER Metal2 ; + ANTENNAMAXAREACAR 15.469256 LAYER Metal2 ; + PORT + LAYER Metal2 ; + RECT 587.5 0 587.76 0.26 ; + END + END B_DIN[26] + PIN B_DIN[5] + DIRECTION INPUT ; + USE SIGNAL ; + ANTENNAPARTIALMETALAREA 2.925 LAYER Metal2 ; + ANTENNAMODEL OXIDE1 ; + ANTENNAGATEAREA 0.20085 LAYER Metal2 ; + ANTENNAMAXAREACAR 15.469256 LAYER Metal2 ; + PORT + LAYER Metal2 ; + RECT 97.73 0 97.99 0.26 ; + END + END B_DIN[5] + PIN B_BIST_DIN[26] + DIRECTION INPUT ; + USE SIGNAL ; + ANTENNAPARTIALMETALAREA 2.9445 LAYER Metal2 ; + ANTENNAMODEL OXIDE1 ; + ANTENNAGATEAREA 0.20085 LAYER Metal2 ; + ANTENNAMAXAREACAR 15.929052 LAYER Metal2 ; + PORT + LAYER Metal2 ; + RECT 585.97 0 586.23 0.26 ; + END + END B_BIST_DIN[26] + PIN B_BIST_DIN[5] + DIRECTION INPUT ; + USE SIGNAL ; + ANTENNAPARTIALMETALAREA 2.9445 LAYER Metal2 ; + ANTENNAMODEL OXIDE1 ; + ANTENNAGATEAREA 0.20085 LAYER Metal2 ; + ANTENNAMAXAREACAR 15.929052 LAYER Metal2 ; + PORT + LAYER Metal2 ; + RECT 99.26 0 99.52 0.26 ; + END + END B_BIST_DIN[5] + PIN B_BM[26] + DIRECTION INPUT ; + USE SIGNAL ; + ANTENNAPARTIALMETALAREA 0.7007 LAYER Metal2 ; + ANTENNAMODEL OXIDE1 ; + ANTENNAGATEAREA 0.20085 LAYER Metal2 ; + ANTENNAMAXAREACAR 4.394822 LAYER Metal2 ; + PORT + LAYER Metal2 ; + RECT 578.985 0 579.245 0.26 ; + END + END B_BM[26] + PIN B_BM[5] + DIRECTION INPUT ; + USE SIGNAL ; + ANTENNAPARTIALMETALAREA 0.7007 LAYER Metal2 ; + ANTENNAMODEL OXIDE1 ; + ANTENNAGATEAREA 0.20085 LAYER Metal2 ; + ANTENNAMAXAREACAR 4.394822 LAYER Metal2 ; + PORT + LAYER Metal2 ; + RECT 106.245 0 106.505 0.26 ; + END + END B_BM[5] + PIN B_BIST_BM[26] + DIRECTION INPUT ; + USE SIGNAL ; + ANTENNAPARTIALMETALAREA 0.7007 LAYER Metal2 ; + ANTENNAMODEL OXIDE1 ; + ANTENNAGATEAREA 0.20085 LAYER Metal2 ; + ANTENNAMAXAREACAR 4.394822 LAYER Metal2 ; + PORT + LAYER Metal2 ; + RECT 580.515 0 580.775 0.26 ; + END + END B_BIST_BM[26] + PIN B_BIST_BM[5] + DIRECTION INPUT ; + USE SIGNAL ; + ANTENNAPARTIALMETALAREA 0.7007 LAYER Metal2 ; + ANTENNAMODEL OXIDE1 ; + ANTENNAGATEAREA 0.20085 LAYER Metal2 ; + ANTENNAMAXAREACAR 4.394822 LAYER Metal2 ; + PORT + LAYER Metal2 ; + RECT 104.715 0 104.975 0.26 ; + END + END B_BIST_BM[5] + PIN B_DOUT[26] + DIRECTION OUTPUT ; + USE SIGNAL ; + ANTENNAPARTIALMETALAREA 4.836 LAYER Metal2 ; + ANTENNADIFFAREA 0.988 LAYER Metal2 ; + PORT + LAYER Metal2 ; + RECT 594.64 0 594.9 0.26 ; + END + END B_DOUT[26] + PIN B_DOUT[5] + DIRECTION OUTPUT ; + USE SIGNAL ; + ANTENNAPARTIALMETALAREA 4.836 LAYER Metal2 ; + ANTENNADIFFAREA 0.988 LAYER Metal2 ; + PORT + LAYER Metal2 ; + RECT 90.59 0 90.85 0.26 ; + END + END B_DOUT[5] + PIN A_DIN[27] + DIRECTION INPUT ; + USE SIGNAL ; + ANTENNAPARTIALMETALAREA 3.9091 LAYER Metal2 ; + ANTENNAMODEL OXIDE1 ; + ANTENNAGATEAREA 0.20085 LAYER Metal2 ; + ANTENNAMAXAREACAR 20.368932 LAYER Metal2 ; + PORT + LAYER Metal2 ; + RECT 602.63 0 602.89 0.26 ; + END + END A_DIN[27] + PIN A_DIN[4] + DIRECTION INPUT ; + USE SIGNAL ; + ANTENNAPARTIALMETALAREA 3.9091 LAYER Metal2 ; + ANTENNAMODEL OXIDE1 ; + ANTENNAGATEAREA 0.20085 LAYER Metal2 ; + ANTENNAMAXAREACAR 20.368932 LAYER Metal2 ; + PORT + LAYER Metal2 ; + RECT 82.6 0 82.86 0.26 ; + END + END A_DIN[4] + PIN A_BIST_DIN[27] + DIRECTION INPUT ; + USE SIGNAL ; + ANTENNAPARTIALMETALAREA 4.136375 LAYER Metal2 ; + ANTENNAMODEL OXIDE1 ; + ANTENNAGATEAREA 0.20085 LAYER Metal2 ; + ANTENNAMAXAREACAR 21.874907 LAYER Metal2 ; + PORT + LAYER Metal2 ; + RECT 603.14 0 603.4 0.26 ; + END + END A_BIST_DIN[27] + PIN A_BIST_DIN[4] + DIRECTION INPUT ; + USE SIGNAL ; + ANTENNAPARTIALMETALAREA 4.136375 LAYER Metal2 ; + ANTENNAMODEL OXIDE1 ; + ANTENNAGATEAREA 0.20085 LAYER Metal2 ; + ANTENNAMAXAREACAR 21.874907 LAYER Metal2 ; + PORT + LAYER Metal2 ; + RECT 82.09 0 82.35 0.26 ; + END + END A_BIST_DIN[4] + PIN A_BM[27] + DIRECTION INPUT ; + USE SIGNAL ; + ANTENNAPARTIALMETALAREA 1.7264 LAYER Metal2 ; + ANTENNAMODEL OXIDE1 ; + ANTENNAGATEAREA 0.20085 LAYER Metal2 ; + ANTENNAMAXAREACAR 9.501618 LAYER Metal2 ; + PORT + LAYER Metal2 ; + RECT 611.3 0 611.56 0.26 ; + END + END A_BM[27] + PIN A_BM[4] + DIRECTION INPUT ; + USE SIGNAL ; + ANTENNAPARTIALMETALAREA 1.7264 LAYER Metal2 ; + ANTENNAMODEL OXIDE1 ; + ANTENNAGATEAREA 0.20085 LAYER Metal2 ; + ANTENNAMAXAREACAR 9.501618 LAYER Metal2 ; + PORT + LAYER Metal2 ; + RECT 73.93 0 74.19 0.26 ; + END + END A_BM[4] + PIN A_BIST_BM[27] + DIRECTION INPUT ; + USE SIGNAL ; + ANTENNAPARTIALMETALAREA 1.7602 LAYER Metal2 ; + ANTENNAMODEL OXIDE1 ; + ANTENNAGATEAREA 0.20085 LAYER Metal2 ; + ANTENNAMAXAREACAR 9.678367 LAYER Metal2 ; + PORT + LAYER Metal2 ; + RECT 609.925 0 610.185 0.26 ; + END + END A_BIST_BM[27] + PIN A_BIST_BM[4] + DIRECTION INPUT ; + USE SIGNAL ; + ANTENNAPARTIALMETALAREA 1.7602 LAYER Metal2 ; + ANTENNAMODEL OXIDE1 ; + ANTENNAGATEAREA 0.20085 LAYER Metal2 ; + ANTENNAMAXAREACAR 9.678367 LAYER Metal2 ; + PORT + LAYER Metal2 ; + RECT 75.305 0 75.565 0.26 ; + END + END A_BIST_BM[4] + PIN A_DOUT[27] + DIRECTION OUTPUT ; + USE SIGNAL ; + ANTENNAPARTIALMETALAREA 4.8256 LAYER Metal2 ; + ANTENNADIFFAREA 0.988 LAYER Metal2 ; + PORT + LAYER Metal2 ; + RECT 595.49 0 595.75 0.26 ; + END + END A_DOUT[27] + PIN A_DOUT[4] + DIRECTION OUTPUT ; + USE SIGNAL ; + ANTENNAPARTIALMETALAREA 4.8256 LAYER Metal2 ; + ANTENNADIFFAREA 0.988 LAYER Metal2 ; + PORT + LAYER Metal2 ; + RECT 89.74 0 90 0.26 ; + END + END A_DOUT[4] + PIN B_DIN[27] + DIRECTION INPUT ; + USE SIGNAL ; + ANTENNAPARTIALMETALAREA 2.925 LAYER Metal2 ; + ANTENNAMODEL OXIDE1 ; + ANTENNAGATEAREA 0.20085 LAYER Metal2 ; + ANTENNAMAXAREACAR 15.469256 LAYER Metal2 ; + PORT + LAYER Metal2 ; + RECT 605.18 0 605.44 0.26 ; + END + END B_DIN[27] + PIN B_DIN[4] + DIRECTION INPUT ; + USE SIGNAL ; + ANTENNAPARTIALMETALAREA 2.925 LAYER Metal2 ; + ANTENNAMODEL OXIDE1 ; + ANTENNAGATEAREA 0.20085 LAYER Metal2 ; + ANTENNAMAXAREACAR 15.469256 LAYER Metal2 ; + PORT + LAYER Metal2 ; + RECT 80.05 0 80.31 0.26 ; + END + END B_DIN[4] + PIN B_BIST_DIN[27] + DIRECTION INPUT ; + USE SIGNAL ; + ANTENNAPARTIALMETALAREA 2.9445 LAYER Metal2 ; + ANTENNAMODEL OXIDE1 ; + ANTENNAGATEAREA 0.20085 LAYER Metal2 ; + ANTENNAMAXAREACAR 15.929052 LAYER Metal2 ; + PORT + LAYER Metal2 ; + RECT 603.65 0 603.91 0.26 ; + END + END B_BIST_DIN[27] + PIN B_BIST_DIN[4] + DIRECTION INPUT ; + USE SIGNAL ; + ANTENNAPARTIALMETALAREA 2.9445 LAYER Metal2 ; + ANTENNAMODEL OXIDE1 ; + ANTENNAGATEAREA 0.20085 LAYER Metal2 ; + ANTENNAMAXAREACAR 15.929052 LAYER Metal2 ; + PORT + LAYER Metal2 ; + RECT 81.58 0 81.84 0.26 ; + END + END B_BIST_DIN[4] + PIN B_BM[27] + DIRECTION INPUT ; + USE SIGNAL ; + ANTENNAPARTIALMETALAREA 0.7007 LAYER Metal2 ; + ANTENNAMODEL OXIDE1 ; + ANTENNAGATEAREA 0.20085 LAYER Metal2 ; + ANTENNAMAXAREACAR 4.394822 LAYER Metal2 ; + PORT + LAYER Metal2 ; + RECT 596.665 0 596.925 0.26 ; + END + END B_BM[27] + PIN B_BM[4] + DIRECTION INPUT ; + USE SIGNAL ; + ANTENNAPARTIALMETALAREA 0.7007 LAYER Metal2 ; + ANTENNAMODEL OXIDE1 ; + ANTENNAGATEAREA 0.20085 LAYER Metal2 ; + ANTENNAMAXAREACAR 4.394822 LAYER Metal2 ; + PORT + LAYER Metal2 ; + RECT 88.565 0 88.825 0.26 ; + END + END B_BM[4] + PIN B_BIST_BM[27] + DIRECTION INPUT ; + USE SIGNAL ; + ANTENNAPARTIALMETALAREA 0.7007 LAYER Metal2 ; + ANTENNAMODEL OXIDE1 ; + ANTENNAGATEAREA 0.20085 LAYER Metal2 ; + ANTENNAMAXAREACAR 4.394822 LAYER Metal2 ; + PORT + LAYER Metal2 ; + RECT 598.195 0 598.455 0.26 ; + END + END B_BIST_BM[27] + PIN B_BIST_BM[4] + DIRECTION INPUT ; + USE SIGNAL ; + ANTENNAPARTIALMETALAREA 0.7007 LAYER Metal2 ; + ANTENNAMODEL OXIDE1 ; + ANTENNAGATEAREA 0.20085 LAYER Metal2 ; + ANTENNAMAXAREACAR 4.394822 LAYER Metal2 ; + PORT + LAYER Metal2 ; + RECT 87.035 0 87.295 0.26 ; + END + END B_BIST_BM[4] + PIN B_DOUT[27] + DIRECTION OUTPUT ; + USE SIGNAL ; + ANTENNAPARTIALMETALAREA 4.836 LAYER Metal2 ; + ANTENNADIFFAREA 0.988 LAYER Metal2 ; + PORT + LAYER Metal2 ; + RECT 612.32 0 612.58 0.26 ; + END + END B_DOUT[27] + PIN B_DOUT[4] + DIRECTION OUTPUT ; + USE SIGNAL ; + ANTENNAPARTIALMETALAREA 4.836 LAYER Metal2 ; + ANTENNADIFFAREA 0.988 LAYER Metal2 ; + PORT + LAYER Metal2 ; + RECT 72.91 0 73.17 0.26 ; + END + END B_DOUT[4] + PIN A_DIN[28] + DIRECTION INPUT ; + USE SIGNAL ; + ANTENNAPARTIALMETALAREA 3.9091 LAYER Metal2 ; + ANTENNAMODEL OXIDE1 ; + ANTENNAGATEAREA 0.20085 LAYER Metal2 ; + ANTENNAMAXAREACAR 20.368932 LAYER Metal2 ; + PORT + LAYER Metal2 ; + RECT 620.31 0 620.57 0.26 ; + END + END A_DIN[28] + PIN A_DIN[3] + DIRECTION INPUT ; + USE SIGNAL ; + ANTENNAPARTIALMETALAREA 3.9091 LAYER Metal2 ; + ANTENNAMODEL OXIDE1 ; + ANTENNAGATEAREA 0.20085 LAYER Metal2 ; + ANTENNAMAXAREACAR 20.368932 LAYER Metal2 ; + PORT + LAYER Metal2 ; + RECT 64.92 0 65.18 0.26 ; + END + END A_DIN[3] + PIN A_BIST_DIN[28] + DIRECTION INPUT ; + USE SIGNAL ; + ANTENNAPARTIALMETALAREA 4.136375 LAYER Metal2 ; + ANTENNAMODEL OXIDE1 ; + ANTENNAGATEAREA 0.20085 LAYER Metal2 ; + ANTENNAMAXAREACAR 21.874907 LAYER Metal2 ; + PORT + LAYER Metal2 ; + RECT 620.82 0 621.08 0.26 ; + END + END A_BIST_DIN[28] + PIN A_BIST_DIN[3] + DIRECTION INPUT ; + USE SIGNAL ; + ANTENNAPARTIALMETALAREA 4.136375 LAYER Metal2 ; + ANTENNAMODEL OXIDE1 ; + ANTENNAGATEAREA 0.20085 LAYER Metal2 ; + ANTENNAMAXAREACAR 21.874907 LAYER Metal2 ; + PORT + LAYER Metal2 ; + RECT 64.41 0 64.67 0.26 ; + END + END A_BIST_DIN[3] + PIN A_BM[28] + DIRECTION INPUT ; + USE SIGNAL ; + ANTENNAPARTIALMETALAREA 1.7264 LAYER Metal2 ; + ANTENNAMODEL OXIDE1 ; + ANTENNAGATEAREA 0.20085 LAYER Metal2 ; + ANTENNAMAXAREACAR 9.501618 LAYER Metal2 ; + PORT + LAYER Metal2 ; + RECT 628.98 0 629.24 0.26 ; + END + END A_BM[28] + PIN A_BM[3] + DIRECTION INPUT ; + USE SIGNAL ; + ANTENNAPARTIALMETALAREA 1.7264 LAYER Metal2 ; + ANTENNAMODEL OXIDE1 ; + ANTENNAGATEAREA 0.20085 LAYER Metal2 ; + ANTENNAMAXAREACAR 9.501618 LAYER Metal2 ; + PORT + LAYER Metal2 ; + RECT 56.25 0 56.51 0.26 ; + END + END A_BM[3] + PIN A_BIST_BM[28] + DIRECTION INPUT ; + USE SIGNAL ; + ANTENNAPARTIALMETALAREA 1.7602 LAYER Metal2 ; + ANTENNAMODEL OXIDE1 ; + ANTENNAGATEAREA 0.20085 LAYER Metal2 ; + ANTENNAMAXAREACAR 9.678367 LAYER Metal2 ; + PORT + LAYER Metal2 ; + RECT 627.605 0 627.865 0.26 ; + END + END A_BIST_BM[28] + PIN A_BIST_BM[3] + DIRECTION INPUT ; + USE SIGNAL ; + ANTENNAPARTIALMETALAREA 1.7602 LAYER Metal2 ; + ANTENNAMODEL OXIDE1 ; + ANTENNAGATEAREA 0.20085 LAYER Metal2 ; + ANTENNAMAXAREACAR 9.678367 LAYER Metal2 ; + PORT + LAYER Metal2 ; + RECT 57.625 0 57.885 0.26 ; + END + END A_BIST_BM[3] + PIN A_DOUT[28] + DIRECTION OUTPUT ; + USE SIGNAL ; + ANTENNAPARTIALMETALAREA 4.8256 LAYER Metal2 ; + ANTENNADIFFAREA 0.988 LAYER Metal2 ; + PORT + LAYER Metal2 ; + RECT 613.17 0 613.43 0.26 ; + END + END A_DOUT[28] + PIN A_DOUT[3] + DIRECTION OUTPUT ; + USE SIGNAL ; + ANTENNAPARTIALMETALAREA 4.8256 LAYER Metal2 ; + ANTENNADIFFAREA 0.988 LAYER Metal2 ; + PORT + LAYER Metal2 ; + RECT 72.06 0 72.32 0.26 ; + END + END A_DOUT[3] + PIN B_DIN[28] + DIRECTION INPUT ; + USE SIGNAL ; + ANTENNAPARTIALMETALAREA 2.925 LAYER Metal2 ; + ANTENNAMODEL OXIDE1 ; + ANTENNAGATEAREA 0.20085 LAYER Metal2 ; + ANTENNAMAXAREACAR 15.469256 LAYER Metal2 ; + PORT + LAYER Metal2 ; + RECT 622.86 0 623.12 0.26 ; + END + END B_DIN[28] + PIN B_DIN[3] + DIRECTION INPUT ; + USE SIGNAL ; + ANTENNAPARTIALMETALAREA 2.925 LAYER Metal2 ; + ANTENNAMODEL OXIDE1 ; + ANTENNAGATEAREA 0.20085 LAYER Metal2 ; + ANTENNAMAXAREACAR 15.469256 LAYER Metal2 ; + PORT + LAYER Metal2 ; + RECT 62.37 0 62.63 0.26 ; + END + END B_DIN[3] + PIN B_BIST_DIN[28] + DIRECTION INPUT ; + USE SIGNAL ; + ANTENNAPARTIALMETALAREA 2.9445 LAYER Metal2 ; + ANTENNAMODEL OXIDE1 ; + ANTENNAGATEAREA 0.20085 LAYER Metal2 ; + ANTENNAMAXAREACAR 15.929052 LAYER Metal2 ; + PORT + LAYER Metal2 ; + RECT 621.33 0 621.59 0.26 ; + END + END B_BIST_DIN[28] + PIN B_BIST_DIN[3] + DIRECTION INPUT ; + USE SIGNAL ; + ANTENNAPARTIALMETALAREA 2.9445 LAYER Metal2 ; + ANTENNAMODEL OXIDE1 ; + ANTENNAGATEAREA 0.20085 LAYER Metal2 ; + ANTENNAMAXAREACAR 15.929052 LAYER Metal2 ; + PORT + LAYER Metal2 ; + RECT 63.9 0 64.16 0.26 ; + END + END B_BIST_DIN[3] + PIN B_BM[28] + DIRECTION INPUT ; + USE SIGNAL ; + ANTENNAPARTIALMETALAREA 0.7007 LAYER Metal2 ; + ANTENNAMODEL OXIDE1 ; + ANTENNAGATEAREA 0.20085 LAYER Metal2 ; + ANTENNAMAXAREACAR 4.394822 LAYER Metal2 ; + PORT + LAYER Metal2 ; + RECT 614.345 0 614.605 0.26 ; + END + END B_BM[28] + PIN B_BM[3] + DIRECTION INPUT ; + USE SIGNAL ; + ANTENNAPARTIALMETALAREA 0.7007 LAYER Metal2 ; + ANTENNAMODEL OXIDE1 ; + ANTENNAGATEAREA 0.20085 LAYER Metal2 ; + ANTENNAMAXAREACAR 4.394822 LAYER Metal2 ; + PORT + LAYER Metal2 ; + RECT 70.885 0 71.145 0.26 ; + END + END B_BM[3] + PIN B_BIST_BM[28] + DIRECTION INPUT ; + USE SIGNAL ; + ANTENNAPARTIALMETALAREA 0.7007 LAYER Metal2 ; + ANTENNAMODEL OXIDE1 ; + ANTENNAGATEAREA 0.20085 LAYER Metal2 ; + ANTENNAMAXAREACAR 4.394822 LAYER Metal2 ; + PORT + LAYER Metal2 ; + RECT 615.875 0 616.135 0.26 ; + END + END B_BIST_BM[28] + PIN B_BIST_BM[3] + DIRECTION INPUT ; + USE SIGNAL ; + ANTENNAPARTIALMETALAREA 0.7007 LAYER Metal2 ; + ANTENNAMODEL OXIDE1 ; + ANTENNAGATEAREA 0.20085 LAYER Metal2 ; + ANTENNAMAXAREACAR 4.394822 LAYER Metal2 ; + PORT + LAYER Metal2 ; + RECT 69.355 0 69.615 0.26 ; + END + END B_BIST_BM[3] + PIN B_DOUT[28] + DIRECTION OUTPUT ; + USE SIGNAL ; + ANTENNAPARTIALMETALAREA 4.836 LAYER Metal2 ; + ANTENNADIFFAREA 0.988 LAYER Metal2 ; + PORT + LAYER Metal2 ; + RECT 630 0 630.26 0.26 ; + END + END B_DOUT[28] + PIN B_DOUT[3] + DIRECTION OUTPUT ; + USE SIGNAL ; + ANTENNAPARTIALMETALAREA 4.836 LAYER Metal2 ; + ANTENNADIFFAREA 0.988 LAYER Metal2 ; + PORT + LAYER Metal2 ; + RECT 55.23 0 55.49 0.26 ; + END + END B_DOUT[3] + PIN A_DIN[29] + DIRECTION INPUT ; + USE SIGNAL ; + ANTENNAPARTIALMETALAREA 3.9091 LAYER Metal2 ; + ANTENNAMODEL OXIDE1 ; + ANTENNAGATEAREA 0.20085 LAYER Metal2 ; + ANTENNAMAXAREACAR 20.368932 LAYER Metal2 ; + PORT + LAYER Metal2 ; + RECT 637.99 0 638.25 0.26 ; + END + END A_DIN[29] + PIN A_DIN[2] + DIRECTION INPUT ; + USE SIGNAL ; + ANTENNAPARTIALMETALAREA 3.9091 LAYER Metal2 ; + ANTENNAMODEL OXIDE1 ; + ANTENNAGATEAREA 0.20085 LAYER Metal2 ; + ANTENNAMAXAREACAR 20.368932 LAYER Metal2 ; + PORT + LAYER Metal2 ; + RECT 47.24 0 47.5 0.26 ; + END + END A_DIN[2] + PIN A_BIST_DIN[29] + DIRECTION INPUT ; + USE SIGNAL ; + ANTENNAPARTIALMETALAREA 4.136375 LAYER Metal2 ; + ANTENNAMODEL OXIDE1 ; + ANTENNAGATEAREA 0.20085 LAYER Metal2 ; + ANTENNAMAXAREACAR 21.874907 LAYER Metal2 ; + PORT + LAYER Metal2 ; + RECT 638.5 0 638.76 0.26 ; + END + END A_BIST_DIN[29] + PIN A_BIST_DIN[2] + DIRECTION INPUT ; + USE SIGNAL ; + ANTENNAPARTIALMETALAREA 4.136375 LAYER Metal2 ; + ANTENNAMODEL OXIDE1 ; + ANTENNAGATEAREA 0.20085 LAYER Metal2 ; + ANTENNAMAXAREACAR 21.874907 LAYER Metal2 ; + PORT + LAYER Metal2 ; + RECT 46.73 0 46.99 0.26 ; + END + END A_BIST_DIN[2] + PIN A_BM[29] + DIRECTION INPUT ; + USE SIGNAL ; + ANTENNAPARTIALMETALAREA 1.7264 LAYER Metal2 ; + ANTENNAMODEL OXIDE1 ; + ANTENNAGATEAREA 0.20085 LAYER Metal2 ; + ANTENNAMAXAREACAR 9.501618 LAYER Metal2 ; + PORT + LAYER Metal2 ; + RECT 646.66 0 646.92 0.26 ; + END + END A_BM[29] + PIN A_BM[2] + DIRECTION INPUT ; + USE SIGNAL ; + ANTENNAPARTIALMETALAREA 1.7264 LAYER Metal2 ; + ANTENNAMODEL OXIDE1 ; + ANTENNAGATEAREA 0.20085 LAYER Metal2 ; + ANTENNAMAXAREACAR 9.501618 LAYER Metal2 ; + PORT + LAYER Metal2 ; + RECT 38.57 0 38.83 0.26 ; + END + END A_BM[2] + PIN A_BIST_BM[29] + DIRECTION INPUT ; + USE SIGNAL ; + ANTENNAPARTIALMETALAREA 1.7602 LAYER Metal2 ; + ANTENNAMODEL OXIDE1 ; + ANTENNAGATEAREA 0.20085 LAYER Metal2 ; + ANTENNAMAXAREACAR 9.678367 LAYER Metal2 ; + PORT + LAYER Metal2 ; + RECT 645.285 0 645.545 0.26 ; + END + END A_BIST_BM[29] + PIN A_BIST_BM[2] + DIRECTION INPUT ; + USE SIGNAL ; + ANTENNAPARTIALMETALAREA 1.7602 LAYER Metal2 ; + ANTENNAMODEL OXIDE1 ; + ANTENNAGATEAREA 0.20085 LAYER Metal2 ; + ANTENNAMAXAREACAR 9.678367 LAYER Metal2 ; + PORT + LAYER Metal2 ; + RECT 39.945 0 40.205 0.26 ; + END + END A_BIST_BM[2] + PIN A_DOUT[29] + DIRECTION OUTPUT ; + USE SIGNAL ; + ANTENNAPARTIALMETALAREA 4.8256 LAYER Metal2 ; + ANTENNADIFFAREA 0.988 LAYER Metal2 ; + PORT + LAYER Metal2 ; + RECT 630.85 0 631.11 0.26 ; + END + END A_DOUT[29] + PIN A_DOUT[2] + DIRECTION OUTPUT ; + USE SIGNAL ; + ANTENNAPARTIALMETALAREA 4.8256 LAYER Metal2 ; + ANTENNADIFFAREA 0.988 LAYER Metal2 ; + PORT + LAYER Metal2 ; + RECT 54.38 0 54.64 0.26 ; + END + END A_DOUT[2] + PIN B_DIN[29] + DIRECTION INPUT ; + USE SIGNAL ; + ANTENNAPARTIALMETALAREA 2.925 LAYER Metal2 ; + ANTENNAMODEL OXIDE1 ; + ANTENNAGATEAREA 0.20085 LAYER Metal2 ; + ANTENNAMAXAREACAR 15.469256 LAYER Metal2 ; + PORT + LAYER Metal2 ; + RECT 640.54 0 640.8 0.26 ; + END + END B_DIN[29] + PIN B_DIN[2] + DIRECTION INPUT ; + USE SIGNAL ; + ANTENNAPARTIALMETALAREA 2.925 LAYER Metal2 ; + ANTENNAMODEL OXIDE1 ; + ANTENNAGATEAREA 0.20085 LAYER Metal2 ; + ANTENNAMAXAREACAR 15.469256 LAYER Metal2 ; + PORT + LAYER Metal2 ; + RECT 44.69 0 44.95 0.26 ; + END + END B_DIN[2] + PIN B_BIST_DIN[29] + DIRECTION INPUT ; + USE SIGNAL ; + ANTENNAPARTIALMETALAREA 2.9445 LAYER Metal2 ; + ANTENNAMODEL OXIDE1 ; + ANTENNAGATEAREA 0.20085 LAYER Metal2 ; + ANTENNAMAXAREACAR 15.929052 LAYER Metal2 ; + PORT + LAYER Metal2 ; + RECT 639.01 0 639.27 0.26 ; + END + END B_BIST_DIN[29] + PIN B_BIST_DIN[2] + DIRECTION INPUT ; + USE SIGNAL ; + ANTENNAPARTIALMETALAREA 2.9445 LAYER Metal2 ; + ANTENNAMODEL OXIDE1 ; + ANTENNAGATEAREA 0.20085 LAYER Metal2 ; + ANTENNAMAXAREACAR 15.929052 LAYER Metal2 ; + PORT + LAYER Metal2 ; + RECT 46.22 0 46.48 0.26 ; + END + END B_BIST_DIN[2] + PIN B_BM[29] + DIRECTION INPUT ; + USE SIGNAL ; + ANTENNAPARTIALMETALAREA 0.7007 LAYER Metal2 ; + ANTENNAMODEL OXIDE1 ; + ANTENNAGATEAREA 0.20085 LAYER Metal2 ; + ANTENNAMAXAREACAR 4.394822 LAYER Metal2 ; + PORT + LAYER Metal2 ; + RECT 632.025 0 632.285 0.26 ; + END + END B_BM[29] + PIN B_BM[2] + DIRECTION INPUT ; + USE SIGNAL ; + ANTENNAPARTIALMETALAREA 0.7007 LAYER Metal2 ; + ANTENNAMODEL OXIDE1 ; + ANTENNAGATEAREA 0.20085 LAYER Metal2 ; + ANTENNAMAXAREACAR 4.394822 LAYER Metal2 ; + PORT + LAYER Metal2 ; + RECT 53.205 0 53.465 0.26 ; + END + END B_BM[2] + PIN B_BIST_BM[29] + DIRECTION INPUT ; + USE SIGNAL ; + ANTENNAPARTIALMETALAREA 0.7007 LAYER Metal2 ; + ANTENNAMODEL OXIDE1 ; + ANTENNAGATEAREA 0.20085 LAYER Metal2 ; + ANTENNAMAXAREACAR 4.394822 LAYER Metal2 ; + PORT + LAYER Metal2 ; + RECT 633.555 0 633.815 0.26 ; + END + END B_BIST_BM[29] + PIN B_BIST_BM[2] + DIRECTION INPUT ; + USE SIGNAL ; + ANTENNAPARTIALMETALAREA 0.7007 LAYER Metal2 ; + ANTENNAMODEL OXIDE1 ; + ANTENNAGATEAREA 0.20085 LAYER Metal2 ; + ANTENNAMAXAREACAR 4.394822 LAYER Metal2 ; + PORT + LAYER Metal2 ; + RECT 51.675 0 51.935 0.26 ; + END + END B_BIST_BM[2] + PIN B_DOUT[29] + DIRECTION OUTPUT ; + USE SIGNAL ; + ANTENNAPARTIALMETALAREA 4.836 LAYER Metal2 ; + ANTENNADIFFAREA 0.988 LAYER Metal2 ; + PORT + LAYER Metal2 ; + RECT 647.68 0 647.94 0.26 ; + END + END B_DOUT[29] + PIN B_DOUT[2] + DIRECTION OUTPUT ; + USE SIGNAL ; + ANTENNAPARTIALMETALAREA 4.836 LAYER Metal2 ; + ANTENNADIFFAREA 0.988 LAYER Metal2 ; + PORT + LAYER Metal2 ; + RECT 37.55 0 37.81 0.26 ; + END + END B_DOUT[2] + PIN A_DIN[30] + DIRECTION INPUT ; + USE SIGNAL ; + ANTENNAPARTIALMETALAREA 3.9091 LAYER Metal2 ; + ANTENNAMODEL OXIDE1 ; + ANTENNAGATEAREA 0.20085 LAYER Metal2 ; + ANTENNAMAXAREACAR 20.368932 LAYER Metal2 ; + PORT + LAYER Metal2 ; + RECT 655.67 0 655.93 0.26 ; + END + END A_DIN[30] + PIN A_DIN[1] + DIRECTION INPUT ; + USE SIGNAL ; + ANTENNAPARTIALMETALAREA 3.9091 LAYER Metal2 ; + ANTENNAMODEL OXIDE1 ; + ANTENNAGATEAREA 0.20085 LAYER Metal2 ; + ANTENNAMAXAREACAR 20.368932 LAYER Metal2 ; + PORT + LAYER Metal2 ; + RECT 29.56 0 29.82 0.26 ; + END + END A_DIN[1] + PIN A_BIST_DIN[30] + DIRECTION INPUT ; + USE SIGNAL ; + ANTENNAPARTIALMETALAREA 4.136375 LAYER Metal2 ; + ANTENNAMODEL OXIDE1 ; + ANTENNAGATEAREA 0.20085 LAYER Metal2 ; + ANTENNAMAXAREACAR 21.874907 LAYER Metal2 ; + PORT + LAYER Metal2 ; + RECT 656.18 0 656.44 0.26 ; + END + END A_BIST_DIN[30] + PIN A_BIST_DIN[1] + DIRECTION INPUT ; + USE SIGNAL ; + ANTENNAPARTIALMETALAREA 4.136375 LAYER Metal2 ; + ANTENNAMODEL OXIDE1 ; + ANTENNAGATEAREA 0.20085 LAYER Metal2 ; + ANTENNAMAXAREACAR 21.874907 LAYER Metal2 ; + PORT + LAYER Metal2 ; + RECT 29.05 0 29.31 0.26 ; + END + END A_BIST_DIN[1] + PIN A_BM[30] + DIRECTION INPUT ; + USE SIGNAL ; + ANTENNAPARTIALMETALAREA 1.7264 LAYER Metal2 ; + ANTENNAMODEL OXIDE1 ; + ANTENNAGATEAREA 0.20085 LAYER Metal2 ; + ANTENNAMAXAREACAR 9.501618 LAYER Metal2 ; + PORT + LAYER Metal2 ; + RECT 664.34 0 664.6 0.26 ; + END + END A_BM[30] + PIN A_BM[1] + DIRECTION INPUT ; + USE SIGNAL ; + ANTENNAPARTIALMETALAREA 1.7264 LAYER Metal2 ; + ANTENNAMODEL OXIDE1 ; + ANTENNAGATEAREA 0.20085 LAYER Metal2 ; + ANTENNAMAXAREACAR 9.501618 LAYER Metal2 ; + PORT + LAYER Metal2 ; + RECT 20.89 0 21.15 0.26 ; + END + END A_BM[1] + PIN A_BIST_BM[30] + DIRECTION INPUT ; + USE SIGNAL ; + ANTENNAPARTIALMETALAREA 1.7602 LAYER Metal2 ; + ANTENNAMODEL OXIDE1 ; + ANTENNAGATEAREA 0.20085 LAYER Metal2 ; + ANTENNAMAXAREACAR 9.678367 LAYER Metal2 ; + PORT + LAYER Metal2 ; + RECT 662.965 0 663.225 0.26 ; + END + END A_BIST_BM[30] + PIN A_BIST_BM[1] + DIRECTION INPUT ; + USE SIGNAL ; + ANTENNAPARTIALMETALAREA 1.7602 LAYER Metal2 ; + ANTENNAMODEL OXIDE1 ; + ANTENNAGATEAREA 0.20085 LAYER Metal2 ; + ANTENNAMAXAREACAR 9.678367 LAYER Metal2 ; + PORT + LAYER Metal2 ; + RECT 22.265 0 22.525 0.26 ; + END + END A_BIST_BM[1] + PIN A_DOUT[30] + DIRECTION OUTPUT ; + USE SIGNAL ; + ANTENNAPARTIALMETALAREA 4.8256 LAYER Metal2 ; + ANTENNADIFFAREA 0.988 LAYER Metal2 ; + PORT + LAYER Metal2 ; + RECT 648.53 0 648.79 0.26 ; + END + END A_DOUT[30] + PIN A_DOUT[1] + DIRECTION OUTPUT ; + USE SIGNAL ; + ANTENNAPARTIALMETALAREA 4.8256 LAYER Metal2 ; + ANTENNADIFFAREA 0.988 LAYER Metal2 ; + PORT + LAYER Metal2 ; + RECT 36.7 0 36.96 0.26 ; + END + END A_DOUT[1] + PIN B_DIN[30] + DIRECTION INPUT ; + USE SIGNAL ; + ANTENNAPARTIALMETALAREA 2.925 LAYER Metal2 ; + ANTENNAMODEL OXIDE1 ; + ANTENNAGATEAREA 0.20085 LAYER Metal2 ; + ANTENNAMAXAREACAR 15.469256 LAYER Metal2 ; + PORT + LAYER Metal2 ; + RECT 658.22 0 658.48 0.26 ; + END + END B_DIN[30] + PIN B_DIN[1] + DIRECTION INPUT ; + USE SIGNAL ; + ANTENNAPARTIALMETALAREA 2.925 LAYER Metal2 ; + ANTENNAMODEL OXIDE1 ; + ANTENNAGATEAREA 0.20085 LAYER Metal2 ; + ANTENNAMAXAREACAR 15.469256 LAYER Metal2 ; + PORT + LAYER Metal2 ; + RECT 27.01 0 27.27 0.26 ; + END + END B_DIN[1] + PIN B_BIST_DIN[30] + DIRECTION INPUT ; + USE SIGNAL ; + ANTENNAPARTIALMETALAREA 2.9445 LAYER Metal2 ; + ANTENNAMODEL OXIDE1 ; + ANTENNAGATEAREA 0.20085 LAYER Metal2 ; + ANTENNAMAXAREACAR 15.929052 LAYER Metal2 ; + PORT + LAYER Metal2 ; + RECT 656.69 0 656.95 0.26 ; + END + END B_BIST_DIN[30] + PIN B_BIST_DIN[1] + DIRECTION INPUT ; + USE SIGNAL ; + ANTENNAPARTIALMETALAREA 2.9445 LAYER Metal2 ; + ANTENNAMODEL OXIDE1 ; + ANTENNAGATEAREA 0.20085 LAYER Metal2 ; + ANTENNAMAXAREACAR 15.929052 LAYER Metal2 ; + PORT + LAYER Metal2 ; + RECT 28.54 0 28.8 0.26 ; + END + END B_BIST_DIN[1] + PIN B_BM[30] + DIRECTION INPUT ; + USE SIGNAL ; + ANTENNAPARTIALMETALAREA 0.7007 LAYER Metal2 ; + ANTENNAMODEL OXIDE1 ; + ANTENNAGATEAREA 0.20085 LAYER Metal2 ; + ANTENNAMAXAREACAR 4.394822 LAYER Metal2 ; + PORT + LAYER Metal2 ; + RECT 649.705 0 649.965 0.26 ; + END + END B_BM[30] + PIN B_BM[1] + DIRECTION INPUT ; + USE SIGNAL ; + ANTENNAPARTIALMETALAREA 0.7007 LAYER Metal2 ; + ANTENNAMODEL OXIDE1 ; + ANTENNAGATEAREA 0.20085 LAYER Metal2 ; + ANTENNAMAXAREACAR 4.394822 LAYER Metal2 ; + PORT + LAYER Metal2 ; + RECT 35.525 0 35.785 0.26 ; + END + END B_BM[1] + PIN B_BIST_BM[30] + DIRECTION INPUT ; + USE SIGNAL ; + ANTENNAPARTIALMETALAREA 0.7007 LAYER Metal2 ; + ANTENNAMODEL OXIDE1 ; + ANTENNAGATEAREA 0.20085 LAYER Metal2 ; + ANTENNAMAXAREACAR 4.394822 LAYER Metal2 ; + PORT + LAYER Metal2 ; + RECT 651.235 0 651.495 0.26 ; + END + END B_BIST_BM[30] + PIN B_BIST_BM[1] + DIRECTION INPUT ; + USE SIGNAL ; + ANTENNAPARTIALMETALAREA 0.7007 LAYER Metal2 ; + ANTENNAMODEL OXIDE1 ; + ANTENNAGATEAREA 0.20085 LAYER Metal2 ; + ANTENNAMAXAREACAR 4.394822 LAYER Metal2 ; + PORT + LAYER Metal2 ; + RECT 33.995 0 34.255 0.26 ; + END + END B_BIST_BM[1] + PIN B_DOUT[30] + DIRECTION OUTPUT ; + USE SIGNAL ; + ANTENNAPARTIALMETALAREA 4.836 LAYER Metal2 ; + ANTENNADIFFAREA 0.988 LAYER Metal2 ; + PORT + LAYER Metal2 ; + RECT 665.36 0 665.62 0.26 ; + END + END B_DOUT[30] + PIN B_DOUT[1] + DIRECTION OUTPUT ; + USE SIGNAL ; + ANTENNAPARTIALMETALAREA 4.836 LAYER Metal2 ; + ANTENNADIFFAREA 0.988 LAYER Metal2 ; + PORT + LAYER Metal2 ; + RECT 19.87 0 20.13 0.26 ; + END + END B_DOUT[1] + PIN A_DIN[31] + DIRECTION INPUT ; + USE SIGNAL ; + ANTENNAPARTIALMETALAREA 3.9091 LAYER Metal2 ; + ANTENNAMODEL OXIDE1 ; + ANTENNAGATEAREA 0.20085 LAYER Metal2 ; + ANTENNAMAXAREACAR 20.368932 LAYER Metal2 ; + PORT + LAYER Metal2 ; + RECT 673.35 0 673.61 0.26 ; + END + END A_DIN[31] + PIN A_DIN[0] + DIRECTION INPUT ; + USE SIGNAL ; + ANTENNAPARTIALMETALAREA 3.9091 LAYER Metal2 ; + ANTENNAMODEL OXIDE1 ; + ANTENNAGATEAREA 0.20085 LAYER Metal2 ; + ANTENNAMAXAREACAR 20.368932 LAYER Metal2 ; + PORT + LAYER Metal2 ; + RECT 11.88 0 12.14 0.26 ; + END + END A_DIN[0] + PIN A_BIST_DIN[31] + DIRECTION INPUT ; + USE SIGNAL ; + ANTENNAPARTIALMETALAREA 4.136375 LAYER Metal2 ; + ANTENNAMODEL OXIDE1 ; + ANTENNAGATEAREA 0.20085 LAYER Metal2 ; + ANTENNAMAXAREACAR 21.874907 LAYER Metal2 ; + PORT + LAYER Metal2 ; + RECT 673.86 0 674.12 0.26 ; + END + END A_BIST_DIN[31] + PIN A_BIST_DIN[0] + DIRECTION INPUT ; + USE SIGNAL ; + ANTENNAPARTIALMETALAREA 4.136375 LAYER Metal2 ; + ANTENNAMODEL OXIDE1 ; + ANTENNAGATEAREA 0.20085 LAYER Metal2 ; + ANTENNAMAXAREACAR 21.874907 LAYER Metal2 ; + PORT + LAYER Metal2 ; + RECT 11.37 0 11.63 0.26 ; + END + END A_BIST_DIN[0] + PIN A_BM[31] + DIRECTION INPUT ; + USE SIGNAL ; + ANTENNAPARTIALMETALAREA 1.7264 LAYER Metal2 ; + ANTENNAMODEL OXIDE1 ; + ANTENNAGATEAREA 0.20085 LAYER Metal2 ; + ANTENNAMAXAREACAR 9.501618 LAYER Metal2 ; + PORT + LAYER Metal2 ; + RECT 682.02 0 682.28 0.26 ; + END + END A_BM[31] + PIN A_BM[0] + DIRECTION INPUT ; + USE SIGNAL ; + ANTENNAPARTIALMETALAREA 1.7264 LAYER Metal2 ; + ANTENNAMODEL OXIDE1 ; + ANTENNAGATEAREA 0.20085 LAYER Metal2 ; + ANTENNAMAXAREACAR 9.501618 LAYER Metal2 ; + PORT + LAYER Metal2 ; + RECT 3.21 0 3.47 0.26 ; + END + END A_BM[0] + PIN A_BIST_BM[31] + DIRECTION INPUT ; + USE SIGNAL ; + ANTENNAPARTIALMETALAREA 1.7602 LAYER Metal2 ; + ANTENNAMODEL OXIDE1 ; + ANTENNAGATEAREA 0.20085 LAYER Metal2 ; + ANTENNAMAXAREACAR 9.678367 LAYER Metal2 ; + PORT + LAYER Metal2 ; + RECT 680.645 0 680.905 0.26 ; + END + END A_BIST_BM[31] + PIN A_BIST_BM[0] + DIRECTION INPUT ; + USE SIGNAL ; + ANTENNAPARTIALMETALAREA 1.7602 LAYER Metal2 ; + ANTENNAMODEL OXIDE1 ; + ANTENNAGATEAREA 0.20085 LAYER Metal2 ; + ANTENNAMAXAREACAR 9.678367 LAYER Metal2 ; + PORT + LAYER Metal2 ; + RECT 4.585 0 4.845 0.26 ; + END + END A_BIST_BM[0] + PIN A_DOUT[31] + DIRECTION OUTPUT ; + USE SIGNAL ; + ANTENNAPARTIALMETALAREA 4.8256 LAYER Metal2 ; + ANTENNADIFFAREA 0.988 LAYER Metal2 ; + PORT + LAYER Metal2 ; + RECT 666.21 0 666.47 0.26 ; + END + END A_DOUT[31] + PIN A_DOUT[0] + DIRECTION OUTPUT ; + USE SIGNAL ; + ANTENNAPARTIALMETALAREA 4.8256 LAYER Metal2 ; + ANTENNADIFFAREA 0.988 LAYER Metal2 ; + PORT + LAYER Metal2 ; + RECT 19.02 0 19.28 0.26 ; + END + END A_DOUT[0] + PIN B_DIN[31] + DIRECTION INPUT ; + USE SIGNAL ; + ANTENNAPARTIALMETALAREA 2.925 LAYER Metal2 ; + ANTENNAMODEL OXIDE1 ; + ANTENNAGATEAREA 0.20085 LAYER Metal2 ; + ANTENNAMAXAREACAR 15.469256 LAYER Metal2 ; + PORT + LAYER Metal2 ; + RECT 675.9 0 676.16 0.26 ; + END + END B_DIN[31] + PIN B_DIN[0] + DIRECTION INPUT ; + USE SIGNAL ; + ANTENNAPARTIALMETALAREA 2.925 LAYER Metal2 ; + ANTENNAMODEL OXIDE1 ; + ANTENNAGATEAREA 0.20085 LAYER Metal2 ; + ANTENNAMAXAREACAR 15.469256 LAYER Metal2 ; + PORT + LAYER Metal2 ; + RECT 9.33 0 9.59 0.26 ; + END + END B_DIN[0] + PIN B_BIST_DIN[31] + DIRECTION INPUT ; + USE SIGNAL ; + ANTENNAPARTIALMETALAREA 2.9445 LAYER Metal2 ; + ANTENNAMODEL OXIDE1 ; + ANTENNAGATEAREA 0.20085 LAYER Metal2 ; + ANTENNAMAXAREACAR 15.929052 LAYER Metal2 ; + PORT + LAYER Metal2 ; + RECT 674.37 0 674.63 0.26 ; + END + END B_BIST_DIN[31] + PIN B_BIST_DIN[0] + DIRECTION INPUT ; + USE SIGNAL ; + ANTENNAPARTIALMETALAREA 2.9445 LAYER Metal2 ; + ANTENNAMODEL OXIDE1 ; + ANTENNAGATEAREA 0.20085 LAYER Metal2 ; + ANTENNAMAXAREACAR 15.929052 LAYER Metal2 ; + PORT + LAYER Metal2 ; + RECT 10.86 0 11.12 0.26 ; + END + END B_BIST_DIN[0] + PIN B_BM[31] + DIRECTION INPUT ; + USE SIGNAL ; + ANTENNAPARTIALMETALAREA 0.7007 LAYER Metal2 ; + ANTENNAMODEL OXIDE1 ; + ANTENNAGATEAREA 0.20085 LAYER Metal2 ; + ANTENNAMAXAREACAR 4.394822 LAYER Metal2 ; + PORT + LAYER Metal2 ; + RECT 667.385 0 667.645 0.26 ; + END + END B_BM[31] + PIN B_BM[0] + DIRECTION INPUT ; + USE SIGNAL ; + ANTENNAPARTIALMETALAREA 0.7007 LAYER Metal2 ; + ANTENNAMODEL OXIDE1 ; + ANTENNAGATEAREA 0.20085 LAYER Metal2 ; + ANTENNAMAXAREACAR 4.394822 LAYER Metal2 ; + PORT + LAYER Metal2 ; + RECT 17.845 0 18.105 0.26 ; + END + END B_BM[0] + PIN B_BIST_BM[31] + DIRECTION INPUT ; + USE SIGNAL ; + ANTENNAPARTIALMETALAREA 0.7007 LAYER Metal2 ; + ANTENNAMODEL OXIDE1 ; + ANTENNAGATEAREA 0.20085 LAYER Metal2 ; + ANTENNAMAXAREACAR 4.394822 LAYER Metal2 ; + PORT + LAYER Metal2 ; + RECT 668.915 0 669.175 0.26 ; + END + END B_BIST_BM[31] + PIN B_BIST_BM[0] + DIRECTION INPUT ; + USE SIGNAL ; + ANTENNAPARTIALMETALAREA 0.7007 LAYER Metal2 ; + ANTENNAMODEL OXIDE1 ; + ANTENNAGATEAREA 0.20085 LAYER Metal2 ; + ANTENNAMAXAREACAR 4.394822 LAYER Metal2 ; + PORT + LAYER Metal2 ; + RECT 16.315 0 16.575 0.26 ; + END + END B_BIST_BM[0] + PIN B_DOUT[31] + DIRECTION OUTPUT ; + USE SIGNAL ; + ANTENNAPARTIALMETALAREA 4.836 LAYER Metal2 ; + ANTENNADIFFAREA 0.988 LAYER Metal2 ; + PORT + LAYER Metal2 ; + RECT 683.04 0 683.3 0.26 ; + END + END B_DOUT[31] + PIN B_DOUT[0] + DIRECTION OUTPUT ; + USE SIGNAL ; + ANTENNAPARTIALMETALAREA 4.836 LAYER Metal2 ; + ANTENNADIFFAREA 0.988 LAYER Metal2 ; + PORT + LAYER Metal2 ; + RECT 2.19 0 2.45 0.26 ; + END + END B_DOUT[0] + PIN A_ADDR[0] + DIRECTION INPUT ; + USE SIGNAL ; + ANTENNAPARTIALMETALAREA 8.7685 LAYER Metal2 ; + ANTENNAMODEL OXIDE1 ; + ANTENNAGATEAREA 0.20085 LAYER Metal2 ; + ANTENNAMAXAREACAR 44.563107 LAYER Metal2 ; + PORT + LAYER Metal2 ; + RECT 358.835 0 359.095 0.26 ; + END + END A_ADDR[0] + PIN A_BIST_ADDR[0] + DIRECTION INPUT ; + USE SIGNAL ; + ANTENNAPARTIALMETALAREA 9.8293 LAYER Metal2 ; + ANTENNAMODEL OXIDE1 ; + ANTENNAGATEAREA 0.20085 LAYER Metal2 ; + ANTENNAMAXAREACAR 49.84466 LAYER Metal2 ; + PORT + LAYER Metal2 ; + RECT 364.445 0 364.705 0.26 ; + END + END A_BIST_ADDR[0] + PIN B_ADDR[0] + DIRECTION INPUT ; + USE SIGNAL ; + ANTENNAPARTIALMETALAREA 8.7685 LAYER Metal2 ; + ANTENNAMODEL OXIDE1 ; + ANTENNAGATEAREA 0.20085 LAYER Metal2 ; + ANTENNAMAXAREACAR 44.563107 LAYER Metal2 ; + PORT + LAYER Metal2 ; + RECT 326.395 0 326.655 0.26 ; + END + END B_ADDR[0] + PIN B_BIST_ADDR[0] + DIRECTION INPUT ; + USE SIGNAL ; + ANTENNAPARTIALMETALAREA 9.8293 LAYER Metal2 ; + ANTENNAMODEL OXIDE1 ; + ANTENNAGATEAREA 0.20085 LAYER Metal2 ; + ANTENNAMAXAREACAR 49.84466 LAYER Metal2 ; + PORT + LAYER Metal2 ; + RECT 320.785 0 321.045 0.26 ; + END + END B_BIST_ADDR[0] + PIN A_ADDR[1] + DIRECTION INPUT ; + USE SIGNAL ; + ANTENNAPARTIALMETALAREA 11.0851 LAYER Metal2 ; + ANTENNAMODEL OXIDE1 ; + ANTENNAGATEAREA 0.20085 LAYER Metal2 ; + ANTENNAMAXAREACAR 56.097087 LAYER Metal2 ; + PORT + LAYER Metal2 ; + RECT 359.345 0 359.605 0.26 ; + END + END A_ADDR[1] + PIN A_BIST_ADDR[1] + DIRECTION INPUT ; + USE SIGNAL ; + ANTENNAPARTIALMETALAREA 12.1459 LAYER Metal2 ; + ANTENNAMODEL OXIDE1 ; + ANTENNAGATEAREA 0.20085 LAYER Metal2 ; + ANTENNAMAXAREACAR 61.378641 LAYER Metal2 ; + PORT + LAYER Metal2 ; + RECT 364.955 0 365.215 0.26 ; + END + END A_BIST_ADDR[1] + PIN B_ADDR[1] + DIRECTION INPUT ; + USE SIGNAL ; + ANTENNAPARTIALMETALAREA 11.0851 LAYER Metal2 ; + ANTENNAMODEL OXIDE1 ; + ANTENNAGATEAREA 0.20085 LAYER Metal2 ; + ANTENNAMAXAREACAR 56.097087 LAYER Metal2 ; + PORT + LAYER Metal2 ; + RECT 325.885 0 326.145 0.26 ; + END + END B_ADDR[1] + PIN B_BIST_ADDR[1] + DIRECTION INPUT ; + USE SIGNAL ; + ANTENNAPARTIALMETALAREA 12.1459 LAYER Metal2 ; + ANTENNAMODEL OXIDE1 ; + ANTENNAGATEAREA 0.20085 LAYER Metal2 ; + ANTENNAMAXAREACAR 61.378641 LAYER Metal2 ; + PORT + LAYER Metal2 ; + RECT 320.275 0 320.535 0.26 ; + END + END B_BIST_ADDR[1] + PIN A_ADDR[2] + DIRECTION INPUT ; + USE SIGNAL ; + ANTENNAPARTIALMETALAREA 13.0819 LAYER Metal2 ; + ANTENNAPARTIALMETALAREA 1.5246 LAYER Metal3 ; + ANTENNAPARTIALCUTAREA 0.0722 LAYER Via2 ; + ANTENNAMODEL OXIDE1 ; + ANTENNAGATEAREA 0.20085 LAYER Metal3 ; + ANTENNAMAXAREACAR 9.415982 LAYER Metal3 ; + PORT + LAYER Metal2 ; + RECT 368.015 0 368.275 0.26 ; + END + END A_ADDR[2] + PIN A_BIST_ADDR[2] + DIRECTION INPUT ; + USE SIGNAL ; + ANTENNAPARTIALMETALAREA 13.0819 LAYER Metal2 ; + ANTENNAPARTIALMETALAREA 1.0962 LAYER Metal3 ; + ANTENNAPARTIALCUTAREA 0.0722 LAYER Via2 ; + ANTENNAMODEL OXIDE1 ; + ANTENNAGATEAREA 0.20085 LAYER Metal3 ; + ANTENNAMAXAREACAR 7.813791 LAYER Metal3 ; + PORT + LAYER Metal2 ; + RECT 368.525 0 368.785 0.26 ; + END + END A_BIST_ADDR[2] + PIN B_ADDR[2] + DIRECTION INPUT ; + USE SIGNAL ; + ANTENNAPARTIALMETALAREA 13.0819 LAYER Metal2 ; + ANTENNAPARTIALMETALAREA 1.5246 LAYER Metal3 ; + ANTENNAPARTIALCUTAREA 0.0722 LAYER Via2 ; + ANTENNAMODEL OXIDE1 ; + ANTENNAGATEAREA 0.20085 LAYER Metal3 ; + ANTENNAMAXAREACAR 9.415982 LAYER Metal3 ; + PORT + LAYER Metal2 ; + RECT 317.215 0 317.475 0.26 ; + END + END B_ADDR[2] + PIN B_BIST_ADDR[2] + DIRECTION INPUT ; + USE SIGNAL ; + ANTENNAPARTIALMETALAREA 13.0819 LAYER Metal2 ; + ANTENNAPARTIALMETALAREA 1.0962 LAYER Metal3 ; + ANTENNAPARTIALCUTAREA 0.0722 LAYER Via2 ; + ANTENNAMODEL OXIDE1 ; + ANTENNAGATEAREA 0.20085 LAYER Metal3 ; + ANTENNAMAXAREACAR 7.813791 LAYER Metal3 ; + PORT + LAYER Metal2 ; + RECT 316.705 0 316.965 0.26 ; + END + END B_BIST_ADDR[2] + PIN A_ADDR[3] + DIRECTION INPUT ; + USE SIGNAL ; + ANTENNAPARTIALMETALAREA 13.0819 LAYER Metal2 ; + ANTENNAPARTIALMETALAREA 3.9459 LAYER Metal3 ; + ANTENNAPARTIALCUTAREA 0.0722 LAYER Via2 ; + ANTENNAMODEL OXIDE1 ; + ANTENNAGATEAREA 0.20085 LAYER Metal3 ; + ANTENNAMAXAREACAR 21.471247 LAYER Metal3 ; + PORT + LAYER Metal2 ; + RECT 366.995 0 367.255 0.26 ; + END + END A_ADDR[3] + PIN A_BIST_ADDR[3] + DIRECTION INPUT ; + USE SIGNAL ; + ANTENNAPARTIALMETALAREA 13.0819 LAYER Metal2 ; + ANTENNAPARTIALMETALAREA 3.7317 LAYER Metal3 ; + ANTENNAPARTIALCUTAREA 0.0722 LAYER Via2 ; + ANTENNAMODEL OXIDE1 ; + ANTENNAGATEAREA 0.20085 LAYER Metal3 ; + ANTENNAMAXAREACAR 20.935524 LAYER Metal3 ; + PORT + LAYER Metal2 ; + RECT 367.505 0 367.765 0.26 ; + END + END A_BIST_ADDR[3] + PIN B_ADDR[3] + DIRECTION INPUT ; + USE SIGNAL ; + ANTENNAPARTIALMETALAREA 13.0819 LAYER Metal2 ; + ANTENNAPARTIALMETALAREA 3.9459 LAYER Metal3 ; + ANTENNAPARTIALCUTAREA 0.0722 LAYER Via2 ; + ANTENNAMODEL OXIDE1 ; + ANTENNAGATEAREA 0.20085 LAYER Metal3 ; + ANTENNAMAXAREACAR 21.471247 LAYER Metal3 ; + PORT + LAYER Metal2 ; + RECT 318.235 0 318.495 0.26 ; + END + END B_ADDR[3] + PIN B_BIST_ADDR[3] + DIRECTION INPUT ; + USE SIGNAL ; + ANTENNAPARTIALMETALAREA 13.0819 LAYER Metal2 ; + ANTENNAPARTIALMETALAREA 3.7317 LAYER Metal3 ; + ANTENNAPARTIALCUTAREA 0.0722 LAYER Via2 ; + ANTENNAMODEL OXIDE1 ; + ANTENNAGATEAREA 0.20085 LAYER Metal3 ; + ANTENNAMAXAREACAR 20.935524 LAYER Metal3 ; + PORT + LAYER Metal2 ; + RECT 317.725 0 317.985 0.26 ; + END + END B_BIST_ADDR[3] + PIN A_ADDR[4] + DIRECTION INPUT ; + USE SIGNAL ; + ANTENNAPARTIALMETALAREA 14.7329 LAYER Metal2 ; + ANTENNAMODEL OXIDE1 ; + ANTENNAGATEAREA 0.20085 LAYER Metal2 ; + ANTENNAMAXAREACAR 74.2589 LAYER Metal2 ; + PORT + LAYER Metal2 ; + RECT 347.615 0 347.875 0.26 ; + END + END A_ADDR[4] + PIN A_BIST_ADDR[4] + DIRECTION INPUT ; + USE SIGNAL ; + ANTENNAPARTIALMETALAREA 14.4677 LAYER Metal2 ; + ANTENNAMODEL OXIDE1 ; + ANTENNAGATEAREA 0.20085 LAYER Metal2 ; + ANTENNAMAXAREACAR 72.938511 LAYER Metal2 ; + PORT + LAYER Metal2 ; + RECT 348.125 0 348.385 0.26 ; + END + END A_BIST_ADDR[4] + PIN B_ADDR[4] + DIRECTION INPUT ; + USE SIGNAL ; + ANTENNAPARTIALMETALAREA 14.7329 LAYER Metal2 ; + ANTENNAMODEL OXIDE1 ; + ANTENNAGATEAREA 0.20085 LAYER Metal2 ; + ANTENNAMAXAREACAR 74.2589 LAYER Metal2 ; + PORT + LAYER Metal2 ; + RECT 337.615 0 337.875 0.26 ; + END + END B_ADDR[4] + PIN B_BIST_ADDR[4] + DIRECTION INPUT ; + USE SIGNAL ; + ANTENNAPARTIALMETALAREA 14.4677 LAYER Metal2 ; + ANTENNAMODEL OXIDE1 ; + ANTENNAGATEAREA 0.20085 LAYER Metal2 ; + ANTENNAMAXAREACAR 72.938511 LAYER Metal2 ; + PORT + LAYER Metal2 ; + RECT 337.105 0 337.365 0.26 ; + END + END B_BIST_ADDR[4] + PIN A_ADDR[5] + DIRECTION INPUT ; + USE SIGNAL ; + ANTENNAPARTIALMETALAREA 13.2691 LAYER Metal2 ; + ANTENNAMODEL OXIDE1 ; + ANTENNAGATEAREA 0.20085 LAYER Metal2 ; + ANTENNAMAXAREACAR 66.970874 LAYER Metal2 ; + PORT + LAYER Metal2 ; + RECT 346.595 0 346.855 0.26 ; + END + END A_ADDR[5] + PIN A_BIST_ADDR[5] + DIRECTION INPUT ; + USE SIGNAL ; + ANTENNAPARTIALMETALAREA 12.9937 LAYER Metal2 ; + ANTENNAMODEL OXIDE1 ; + ANTENNAGATEAREA 0.20085 LAYER Metal2 ; + ANTENNAMAXAREACAR 65.599701 LAYER Metal2 ; + PORT + LAYER Metal2 ; + RECT 347.105 0 347.365 0.26 ; + END + END A_BIST_ADDR[5] + PIN B_ADDR[5] + DIRECTION INPUT ; + USE SIGNAL ; + ANTENNAPARTIALMETALAREA 13.2691 LAYER Metal2 ; + ANTENNAMODEL OXIDE1 ; + ANTENNAGATEAREA 0.20085 LAYER Metal2 ; + ANTENNAMAXAREACAR 66.970874 LAYER Metal2 ; + PORT + LAYER Metal2 ; + RECT 338.635 0 338.895 0.26 ; + END + END B_ADDR[5] + PIN B_BIST_ADDR[5] + DIRECTION INPUT ; + USE SIGNAL ; + ANTENNAPARTIALMETALAREA 12.9937 LAYER Metal2 ; + ANTENNAMODEL OXIDE1 ; + ANTENNAGATEAREA 0.20085 LAYER Metal2 ; + ANTENNAMAXAREACAR 65.599701 LAYER Metal2 ; + PORT + LAYER Metal2 ; + RECT 338.125 0 338.385 0.26 ; + END + END B_BIST_ADDR[5] + PIN A_ADDR[6] + DIRECTION INPUT ; + USE SIGNAL ; + ANTENNAPARTIALMETALAREA 14.3819 LAYER Metal2 ; + ANTENNAMODEL OXIDE1 ; + ANTENNAGATEAREA 0.20085 LAYER Metal2 ; + ANTENNAMAXAREACAR 72.511327 LAYER Metal2 ; + PORT + LAYER Metal2 ; + RECT 370.565 0 370.825 0.26 ; + END + END A_ADDR[6] + PIN A_BIST_ADDR[6] + DIRECTION INPUT ; + USE SIGNAL ; + ANTENNAPARTIALMETALAREA 14.1167 LAYER Metal2 ; + ANTENNAMODEL OXIDE1 ; + ANTENNAGATEAREA 0.20085 LAYER Metal2 ; + ANTENNAMAXAREACAR 71.190939 LAYER Metal2 ; + PORT + LAYER Metal2 ; + RECT 370.055 0 370.315 0.26 ; + END + END A_BIST_ADDR[6] + PIN B_ADDR[6] + DIRECTION INPUT ; + USE SIGNAL ; + ANTENNAPARTIALMETALAREA 14.3819 LAYER Metal2 ; + ANTENNAMODEL OXIDE1 ; + ANTENNAGATEAREA 0.20085 LAYER Metal2 ; + ANTENNAMAXAREACAR 72.511327 LAYER Metal2 ; + PORT + LAYER Metal2 ; + RECT 314.665 0 314.925 0.26 ; + END + END B_ADDR[6] + PIN B_BIST_ADDR[6] + DIRECTION INPUT ; + USE SIGNAL ; + ANTENNAPARTIALMETALAREA 14.1167 LAYER Metal2 ; + ANTENNAMODEL OXIDE1 ; + ANTENNAGATEAREA 0.20085 LAYER Metal2 ; + ANTENNAMAXAREACAR 71.190939 LAYER Metal2 ; + PORT + LAYER Metal2 ; + RECT 315.175 0 315.435 0.26 ; + END + END B_BIST_ADDR[6] + PIN A_ADDR[7] + DIRECTION INPUT ; + USE SIGNAL ; + ANTENNAPARTIALMETALAREA 16.3761 LAYER Metal2 ; + ANTENNAMODEL OXIDE1 ; + ANTENNAGATEAREA 0.20085 LAYER Metal2 ; + ANTENNAMAXAREACAR 82.440129 LAYER Metal2 ; + PORT + LAYER Metal2 ; + RECT 369.545 0 369.805 0.26 ; + END + END A_ADDR[7] + PIN A_BIST_ADDR[7] + DIRECTION INPUT ; + USE SIGNAL ; + ANTENNAPARTIALMETALAREA 16.1109 LAYER Metal2 ; + ANTENNAMODEL OXIDE1 ; + ANTENNAGATEAREA 0.20085 LAYER Metal2 ; + ANTENNAMAXAREACAR 81.119741 LAYER Metal2 ; + PORT + LAYER Metal2 ; + RECT 369.035 0 369.295 0.26 ; + END + END A_BIST_ADDR[7] + PIN B_ADDR[7] + DIRECTION INPUT ; + USE SIGNAL ; + ANTENNAPARTIALMETALAREA 16.3761 LAYER Metal2 ; + ANTENNAMODEL OXIDE1 ; + ANTENNAGATEAREA 0.20085 LAYER Metal2 ; + ANTENNAMAXAREACAR 82.440129 LAYER Metal2 ; + PORT + LAYER Metal2 ; + RECT 315.685 0 315.945 0.26 ; + END + END B_ADDR[7] + PIN B_BIST_ADDR[7] + DIRECTION INPUT ; + USE SIGNAL ; + ANTENNAPARTIALMETALAREA 16.1109 LAYER Metal2 ; + ANTENNAMODEL OXIDE1 ; + ANTENNAGATEAREA 0.20085 LAYER Metal2 ; + ANTENNAMAXAREACAR 81.119741 LAYER Metal2 ; + PORT + LAYER Metal2 ; + RECT 316.195 0 316.455 0.26 ; + END + END B_BIST_ADDR[7] + PIN A_ADDR[8] + DIRECTION INPUT ; + USE SIGNAL ; + ANTENNAPARTIALMETALAREA 14.4422 LAYER Metal2 ; + ANTENNAMODEL OXIDE1 ; + ANTENNAGATEAREA 0.20085 LAYER Metal2 ; + ANTENNAMAXAREACAR 72.811551 LAYER Metal2 ; + PORT + LAYER Metal2 ; + RECT 373.115 0 373.375 0.26 ; + END + END A_ADDR[8] + PIN A_BIST_ADDR[8] + DIRECTION INPUT ; + USE SIGNAL ; + ANTENNAPARTIALMETALAREA 14.1872 LAYER Metal2 ; + ANTENNAMODEL OXIDE1 ; + ANTENNAGATEAREA 0.20085 LAYER Metal2 ; + ANTENNAMAXAREACAR 71.541947 LAYER Metal2 ; + PORT + LAYER Metal2 ; + RECT 373.625 0 373.885 0.26 ; + END + END A_BIST_ADDR[8] + PIN B_ADDR[8] + DIRECTION INPUT ; + USE SIGNAL ; + ANTENNAPARTIALMETALAREA 14.4422 LAYER Metal2 ; + ANTENNAMODEL OXIDE1 ; + ANTENNAGATEAREA 0.20085 LAYER Metal2 ; + ANTENNAMAXAREACAR 72.811551 LAYER Metal2 ; + PORT + LAYER Metal2 ; + RECT 312.115 0 312.375 0.26 ; + END + END B_ADDR[8] + PIN B_BIST_ADDR[8] + DIRECTION INPUT ; + USE SIGNAL ; + ANTENNAPARTIALMETALAREA 14.1872 LAYER Metal2 ; + ANTENNAMODEL OXIDE1 ; + ANTENNAGATEAREA 0.20085 LAYER Metal2 ; + ANTENNAMAXAREACAR 71.541947 LAYER Metal2 ; + PORT + LAYER Metal2 ; + RECT 311.605 0 311.865 0.26 ; + END + END B_BIST_ADDR[8] + PIN A_CLK + DIRECTION INPUT ; + USE SIGNAL ; + ANTENNAPARTIALMETALAREA 4.0547 LAYER Metal2 ; + ANTENNAMODEL OXIDE1 ; + ANTENNAGATEAREA 0.20085 LAYER Metal2 ; + ANTENNAMAXAREACAR 21.093851 LAYER Metal2 ; + PORT + LAYER Metal2 ; + RECT 357.305 0 357.565 0.26 ; + END + END A_CLK + PIN A_REN + DIRECTION INPUT ; + USE SIGNAL ; + ANTENNAPARTIALMETALAREA 3.98465 LAYER Metal2 ; + ANTENNAMODEL OXIDE1 ; + ANTENNAGATEAREA 0.20085 LAYER Metal2 ; + ANTENNAMAXAREACAR 20.745083 LAYER Metal2 ; + PORT + LAYER Metal2 ; + RECT 360.875 0 361.135 0.26 ; + END + END A_REN + PIN A_WEN + DIRECTION INPUT ; + USE SIGNAL ; + ANTENNAPARTIALMETALAREA 2.8847 LAYER Metal2 ; + ANTENNAMODEL OXIDE1 ; + ANTENNAGATEAREA 0.20085 LAYER Metal2 ; + ANTENNAMAXAREACAR 15.268608 LAYER Metal2 ; + PORT + LAYER Metal2 ; + RECT 360.365 0 360.625 0.26 ; + END + END A_WEN + PIN A_MEN + DIRECTION INPUT ; + USE SIGNAL ; + ANTENNAPARTIALMETALAREA 3.0247 LAYER Metal2 ; + ANTENNAMODEL OXIDE1 ; + ANTENNAGATEAREA 0.20085 LAYER Metal2 ; + ANTENNAMAXAREACAR 15.965646 LAYER Metal2 ; + PORT + LAYER Metal2 ; + RECT 357.815 0 358.075 0.26 ; + END + END A_MEN + PIN A_DLY + DIRECTION INPUT ; + USE SIGNAL ; + ANTENNAPARTIALMETALAREA 7.7792 LAYER Metal2 ; + ANTENNAMODEL OXIDE1 ; + ANTENNAGATEAREA 0.3367 LAYER Metal2 ; + ANTENNAMAXAREACAR 23.644788 LAYER Metal2 ; + PORT + LAYER Metal2 ; + RECT 378.215 0 378.475 0.26 ; + END + END A_DLY + PIN B_CLK + DIRECTION INPUT ; + USE SIGNAL ; + ANTENNAPARTIALMETALAREA 4.0547 LAYER Metal2 ; + ANTENNAMODEL OXIDE1 ; + ANTENNAGATEAREA 0.20085 LAYER Metal2 ; + ANTENNAMAXAREACAR 21.093851 LAYER Metal2 ; + PORT + LAYER Metal2 ; + RECT 327.925 0 328.185 0.26 ; + END + END B_CLK + PIN B_REN + DIRECTION INPUT ; + USE SIGNAL ; + ANTENNAPARTIALMETALAREA 3.98465 LAYER Metal2 ; + ANTENNAMODEL OXIDE1 ; + ANTENNAGATEAREA 0.20085 LAYER Metal2 ; + ANTENNAMAXAREACAR 20.745083 LAYER Metal2 ; + PORT + LAYER Metal2 ; + RECT 324.355 0 324.615 0.26 ; + END + END B_REN + PIN B_WEN + DIRECTION INPUT ; + USE SIGNAL ; + ANTENNAPARTIALMETALAREA 2.8847 LAYER Metal2 ; + ANTENNAMODEL OXIDE1 ; + ANTENNAGATEAREA 0.20085 LAYER Metal2 ; + ANTENNAMAXAREACAR 15.268608 LAYER Metal2 ; + PORT + LAYER Metal2 ; + RECT 324.865 0 325.125 0.26 ; + END + END B_WEN + PIN B_MEN + DIRECTION INPUT ; + USE SIGNAL ; + ANTENNAPARTIALMETALAREA 3.0247 LAYER Metal2 ; + ANTENNAMODEL OXIDE1 ; + ANTENNAGATEAREA 0.20085 LAYER Metal2 ; + ANTENNAMAXAREACAR 15.965646 LAYER Metal2 ; + PORT + LAYER Metal2 ; + RECT 327.415 0 327.675 0.26 ; + END + END B_MEN + PIN B_DLY + DIRECTION INPUT ; + USE SIGNAL ; + ANTENNAPARTIALMETALAREA 7.7792 LAYER Metal2 ; + ANTENNAMODEL OXIDE1 ; + ANTENNAGATEAREA 0.3367 LAYER Metal2 ; + ANTENNAMAXAREACAR 23.644788 LAYER Metal2 ; + PORT + LAYER Metal2 ; + RECT 307.015 0 307.275 0.26 ; + END + END B_DLY + PIN A_BIST_EN + DIRECTION INPUT ; + USE SIGNAL ; + ANTENNAPARTIALMETALAREA 4.0634 LAYER Metal2 ; + ANTENNAPARTIALMETALAREA 254.5589 LAYER Metal3 ; + ANTENNAPARTIALCUTAREA 0.0722 LAYER Via2 ; + ANTENNAMODEL OXIDE1 ; + ANTENNAGATEAREA 1.43 LAYER Metal2 ; + ANTENNAGATEAREA 27.5275 LAYER Metal3 ; + ANTENNAMAXAREACAR 3.266993 LAYER Metal2 ; + ANTENNAMAXAREACAR 20.418815 LAYER Metal3 ; + ANTENNAMAXCUTCAR 0.151469 LAYER Via2 ; + PORT + LAYER Metal2 ; + RECT 359.855 0 360.115 0.26 ; + END + END A_BIST_EN + PIN A_BIST_CLK + DIRECTION INPUT ; + USE SIGNAL ; + ANTENNAPARTIALMETALAREA 4.1639 LAYER Metal2 ; + ANTENNAMODEL OXIDE1 ; + ANTENNAGATEAREA 0.20085 LAYER Metal2 ; + ANTENNAMAXAREACAR 21.953448 LAYER Metal2 ; + PORT + LAYER Metal2 ; + RECT 355.775 0 356.035 0.26 ; + END + END A_BIST_CLK + PIN A_BIST_REN + DIRECTION INPUT ; + USE SIGNAL ; + ANTENNAPARTIALMETALAREA 4.1119 LAYER Metal2 ; + ANTENNAMODEL OXIDE1 ; + ANTENNAGATEAREA 0.20085 LAYER Metal2 ; + ANTENNAMAXAREACAR 21.694548 LAYER Metal2 ; + PORT + LAYER Metal2 ; + RECT 362.405 0 362.665 0.26 ; + END + END A_BIST_REN + PIN A_BIST_WEN + DIRECTION INPUT ; + USE SIGNAL ; + ANTENNAPARTIALMETALAREA 2.9051 LAYER Metal2 ; + ANTENNAMODEL OXIDE1 ; + ANTENNAGATEAREA 0.20085 LAYER Metal2 ; + ANTENNAMAXAREACAR 15.686084 LAYER Metal2 ; + PORT + LAYER Metal2 ; + RECT 361.895 0 362.155 0.26 ; + END + END A_BIST_WEN + PIN A_BIST_MEN + DIRECTION INPUT ; + USE SIGNAL ; + ANTENNAPARTIALMETALAREA 2.8977 LAYER Metal2 ; + ANTENNAMODEL OXIDE1 ; + ANTENNAGATEAREA 0.20085 LAYER Metal2 ; + ANTENNAMAXAREACAR 15.649241 LAYER Metal2 ; + PORT + LAYER Metal2 ; + RECT 356.285 0 356.545 0.26 ; + END + END A_BIST_MEN + PIN B_BIST_EN + DIRECTION INPUT ; + USE SIGNAL ; + ANTENNAPARTIALMETALAREA 3.9646 LAYER Metal2 ; + ANTENNAPARTIALMETALAREA 254.9981 LAYER Metal3 ; + ANTENNAPARTIALCUTAREA 0.0722 LAYER Via2 ; + ANTENNAMODEL OXIDE1 ; + ANTENNAGATEAREA 1.43 LAYER Metal2 ; + ANTENNAGATEAREA 27.5275 LAYER Metal3 ; + ANTENNAMAXAREACAR 3.197902 LAYER Metal2 ; + ANTENNAMAXAREACAR 20.43477 LAYER Metal3 ; + ANTENNAMAXCUTCAR 0.151469 LAYER Via2 ; + PORT + LAYER Metal2 ; + RECT 325.375 0 325.635 0.26 ; + END + END B_BIST_EN + PIN B_BIST_CLK + DIRECTION INPUT ; + USE SIGNAL ; + ANTENNAPARTIALMETALAREA 4.1639 LAYER Metal2 ; + ANTENNAMODEL OXIDE1 ; + ANTENNAGATEAREA 0.20085 LAYER Metal2 ; + ANTENNAMAXAREACAR 21.953448 LAYER Metal2 ; + PORT + LAYER Metal2 ; + RECT 329.455 0 329.715 0.26 ; + END + END B_BIST_CLK + PIN B_BIST_REN + DIRECTION INPUT ; + USE SIGNAL ; + ANTENNAPARTIALMETALAREA 4.1119 LAYER Metal2 ; + ANTENNAMODEL OXIDE1 ; + ANTENNAGATEAREA 0.20085 LAYER Metal2 ; + ANTENNAMAXAREACAR 21.694548 LAYER Metal2 ; + PORT + LAYER Metal2 ; + RECT 322.825 0 323.085 0.26 ; + END + END B_BIST_REN + PIN B_BIST_WEN + DIRECTION INPUT ; + USE SIGNAL ; + ANTENNAPARTIALMETALAREA 2.9051 LAYER Metal2 ; + ANTENNAMODEL OXIDE1 ; + ANTENNAGATEAREA 0.20085 LAYER Metal2 ; + ANTENNAMAXAREACAR 15.686084 LAYER Metal2 ; + PORT + LAYER Metal2 ; + RECT 323.335 0 323.595 0.26 ; + END + END B_BIST_WEN + PIN B_BIST_MEN + DIRECTION INPUT ; + USE SIGNAL ; + ANTENNAPARTIALMETALAREA 2.8977 LAYER Metal2 ; + ANTENNAMODEL OXIDE1 ; + ANTENNAGATEAREA 0.20085 LAYER Metal2 ; + ANTENNAMAXAREACAR 15.649241 LAYER Metal2 ; + PORT + LAYER Metal2 ; + RECT 328.945 0 329.205 0.26 ; + END + END B_BIST_MEN + OBS + LAYER Metal1 ; + RECT 0 0 685.49 219.77 ; + LAYER Metal2 ; + RECT 0.31 53.41 0.51 219.74 ; + RECT 1.135 219.01 1.335 219.74 ; + RECT 1.545 219.01 1.905 219.74 ; + RECT 2.115 219.01 2.315 219.74 ; + RECT 2.19 0.52 2.45 7.78 ; + RECT 2.7 0.3 2.96 5.235 ; + RECT 2.77 219.01 2.97 219.74 ; + RECT 3.21 0.52 3.47 5.57 ; + RECT 3.18 219.01 3.54 219.74 ; + RECT 3.835 219.01 4.035 219.74 ; + RECT 4.33 219.01 4.69 219.74 ; + RECT 4.585 0.52 4.845 6.28 ; + RECT 4.9 219.01 5.1 219.74 ; + RECT 5.555 219.01 5.755 219.74 ; + RECT 5.965 219.01 6.325 219.74 ; + RECT 6.535 219.01 6.735 219.74 ; + RECT 6.27 0.18 7.04 0.88 ; + RECT 7.19 219.01 7.39 219.74 ; + RECT 7.29 0.3 7.55 8.7 ; + RECT 7.6 219.01 7.96 219.74 ; + RECT 8.255 219.01 8.455 219.74 ; + RECT 8.75 219.01 9.11 219.74 ; + RECT 9.84 0.155 10.61 0.445 ; + RECT 9.84 0.155 10.1 8.665 ; + RECT 10.35 0.155 10.61 8.665 ; + RECT 9.32 219.01 9.52 219.74 ; + RECT 9.33 0.52 9.59 9.955 ; + RECT 9.975 219.01 10.175 219.74 ; + RECT 10.385 219.01 10.745 219.74 ; + RECT 10.86 0.52 11.12 11.315 ; + RECT 10.955 219.01 11.155 219.74 ; + RECT 11.37 0.52 11.63 13.45 ; + RECT 11.61 219.01 11.81 219.74 ; + RECT 11.88 0.52 12.14 14.115 ; + RECT 12.02 219.01 12.38 219.74 ; + RECT 12.675 219.01 12.875 219.74 ; + RECT 14.075 0.155 14.845 0.445 ; + RECT 14.075 0.155 14.335 13.21 ; + RECT 14.585 0.155 14.845 13.21 ; + RECT 13.17 219.01 13.53 219.74 ; + RECT 13.74 219.01 13.94 219.74 ; + RECT 15.095 0.18 15.865 0.88 ; + RECT 15.095 0.18 15.355 12.9 ; + RECT 15.605 0.18 15.865 12.9 ; + RECT 14.395 219.01 14.595 219.74 ; + RECT 14.805 219.01 15.165 219.74 ; + RECT 15.375 219.01 15.575 219.74 ; + RECT 16.03 219.01 16.23 219.74 ; + RECT 16.315 0.52 16.575 2.82 ; + RECT 16.44 219.01 16.8 219.74 ; + RECT 17.095 219.01 17.295 219.74 ; + RECT 17.59 219.01 17.95 219.74 ; + RECT 17.845 0.52 18.105 2.82 ; + RECT 18.16 219.01 18.36 219.74 ; + RECT 18.815 219.01 19.015 219.74 ; + RECT 19.02 0.52 19.28 4.315 ; + RECT 19.225 219.01 19.585 219.74 ; + RECT 19.795 219.01 19.995 219.74 ; + RECT 19.87 0.52 20.13 7.78 ; + RECT 20.38 0.3 20.64 5.235 ; + RECT 20.45 219.01 20.65 219.74 ; + RECT 20.89 0.52 21.15 5.57 ; + RECT 20.86 219.01 21.22 219.74 ; + RECT 21.515 219.01 21.715 219.74 ; + RECT 22.01 219.01 22.37 219.74 ; + RECT 22.265 0.52 22.525 6.28 ; + RECT 22.58 219.01 22.78 219.74 ; + RECT 23.235 219.01 23.435 219.74 ; + RECT 23.645 219.01 24.005 219.74 ; + RECT 24.215 219.01 24.415 219.74 ; + RECT 23.95 0.18 24.72 0.88 ; + RECT 24.87 219.01 25.07 219.74 ; + RECT 24.97 0.3 25.23 8.7 ; + RECT 25.28 219.01 25.64 219.74 ; + RECT 25.935 219.01 26.135 219.74 ; + RECT 26.43 219.01 26.79 219.74 ; + RECT 27.52 0.155 28.29 0.445 ; + RECT 27.52 0.155 27.78 8.665 ; + RECT 28.03 0.155 28.29 8.665 ; + RECT 27 219.01 27.2 219.74 ; + RECT 27.01 0.52 27.27 9.955 ; + RECT 27.655 219.01 27.855 219.74 ; + RECT 28.065 219.01 28.425 219.74 ; + RECT 28.54 0.52 28.8 11.315 ; + RECT 28.635 219.01 28.835 219.74 ; + RECT 29.05 0.52 29.31 13.45 ; + RECT 29.29 219.01 29.49 219.74 ; + RECT 29.56 0.52 29.82 14.115 ; + RECT 29.7 219.01 30.06 219.74 ; + RECT 30.355 219.01 30.555 219.74 ; + RECT 31.755 0.155 32.525 0.445 ; + RECT 31.755 0.155 32.015 13.21 ; + RECT 32.265 0.155 32.525 13.21 ; + RECT 30.85 219.01 31.21 219.74 ; + RECT 31.42 219.01 31.62 219.74 ; + RECT 32.775 0.18 33.545 0.88 ; + RECT 32.775 0.18 33.035 12.9 ; + RECT 33.285 0.18 33.545 12.9 ; + RECT 32.075 219.01 32.275 219.74 ; + RECT 32.485 219.01 32.845 219.74 ; + RECT 33.055 219.01 33.255 219.74 ; + RECT 33.71 219.01 33.91 219.74 ; + RECT 33.995 0.52 34.255 2.82 ; + RECT 34.12 219.01 34.48 219.74 ; + RECT 34.775 219.01 34.975 219.74 ; + RECT 35.27 219.01 35.63 219.74 ; + RECT 35.525 0.52 35.785 2.82 ; + RECT 35.84 219.01 36.04 219.74 ; + RECT 36.495 219.01 36.695 219.74 ; + RECT 36.7 0.52 36.96 4.315 ; + RECT 36.905 219.01 37.265 219.74 ; + RECT 37.475 219.01 37.675 219.74 ; + RECT 37.55 0.52 37.81 7.78 ; + RECT 38.06 0.3 38.32 5.235 ; + RECT 38.13 219.01 38.33 219.74 ; + RECT 38.57 0.52 38.83 5.57 ; + RECT 38.54 219.01 38.9 219.74 ; + RECT 39.195 219.01 39.395 219.74 ; + RECT 39.69 219.01 40.05 219.74 ; + RECT 39.945 0.52 40.205 6.28 ; + RECT 40.26 219.01 40.46 219.74 ; + RECT 40.915 219.01 41.115 219.74 ; + RECT 41.325 219.01 41.685 219.74 ; + RECT 41.895 219.01 42.095 219.74 ; + RECT 41.63 0.18 42.4 0.88 ; + RECT 42.55 219.01 42.75 219.74 ; + RECT 42.65 0.3 42.91 8.7 ; + RECT 42.96 219.01 43.32 219.74 ; + RECT 43.615 219.01 43.815 219.74 ; + RECT 44.11 219.01 44.47 219.74 ; + RECT 45.2 0.155 45.97 0.445 ; + RECT 45.2 0.155 45.46 8.665 ; + RECT 45.71 0.155 45.97 8.665 ; + RECT 44.68 219.01 44.88 219.74 ; + RECT 44.69 0.52 44.95 9.955 ; + RECT 45.335 219.01 45.535 219.74 ; + RECT 45.745 219.01 46.105 219.74 ; + RECT 46.22 0.52 46.48 11.315 ; + RECT 46.315 219.01 46.515 219.74 ; + RECT 46.73 0.52 46.99 13.45 ; + RECT 46.97 219.01 47.17 219.74 ; + RECT 47.24 0.52 47.5 14.115 ; + RECT 47.38 219.01 47.74 219.74 ; + RECT 48.035 219.01 48.235 219.74 ; + RECT 49.435 0.155 50.205 0.445 ; + RECT 49.435 0.155 49.695 13.21 ; + RECT 49.945 0.155 50.205 13.21 ; + RECT 48.53 219.01 48.89 219.74 ; + RECT 49.1 219.01 49.3 219.74 ; + RECT 50.455 0.18 51.225 0.88 ; + RECT 50.455 0.18 50.715 12.9 ; + RECT 50.965 0.18 51.225 12.9 ; + RECT 49.755 219.01 49.955 219.74 ; + RECT 50.165 219.01 50.525 219.74 ; + RECT 50.735 219.01 50.935 219.74 ; + RECT 51.39 219.01 51.59 219.74 ; + RECT 51.675 0.52 51.935 2.82 ; + RECT 51.8 219.01 52.16 219.74 ; + RECT 52.455 219.01 52.655 219.74 ; + RECT 52.95 219.01 53.31 219.74 ; + RECT 53.205 0.52 53.465 2.82 ; + RECT 53.52 219.01 53.72 219.74 ; + RECT 54.175 219.01 54.375 219.74 ; + RECT 54.38 0.52 54.64 4.315 ; + RECT 54.585 219.01 54.945 219.74 ; + RECT 55.155 219.01 55.355 219.74 ; + RECT 55.23 0.52 55.49 7.78 ; + RECT 55.74 0.3 56 5.235 ; + RECT 55.81 219.01 56.01 219.74 ; + RECT 56.25 0.52 56.51 5.57 ; + RECT 56.22 219.01 56.58 219.74 ; + RECT 56.875 219.01 57.075 219.74 ; + RECT 57.37 219.01 57.73 219.74 ; + RECT 57.625 0.52 57.885 6.28 ; + RECT 57.94 219.01 58.14 219.74 ; + RECT 58.595 219.01 58.795 219.74 ; + RECT 59.005 219.01 59.365 219.74 ; + RECT 59.575 219.01 59.775 219.74 ; + RECT 59.31 0.18 60.08 0.88 ; + RECT 60.23 219.01 60.43 219.74 ; + RECT 60.33 0.3 60.59 8.7 ; + RECT 60.64 219.01 61 219.74 ; + RECT 61.295 219.01 61.495 219.74 ; + RECT 61.79 219.01 62.15 219.74 ; + RECT 62.88 0.155 63.65 0.445 ; + RECT 62.88 0.155 63.14 8.665 ; + RECT 63.39 0.155 63.65 8.665 ; + RECT 62.36 219.01 62.56 219.74 ; + RECT 62.37 0.52 62.63 9.955 ; + RECT 63.015 219.01 63.215 219.74 ; + RECT 63.425 219.01 63.785 219.74 ; + RECT 63.9 0.52 64.16 11.315 ; + RECT 63.995 219.01 64.195 219.74 ; + RECT 64.41 0.52 64.67 13.45 ; + RECT 64.65 219.01 64.85 219.74 ; + RECT 64.92 0.52 65.18 14.115 ; + RECT 65.06 219.01 65.42 219.74 ; + RECT 65.715 219.01 65.915 219.74 ; + RECT 67.115 0.155 67.885 0.445 ; + RECT 67.115 0.155 67.375 13.21 ; + RECT 67.625 0.155 67.885 13.21 ; + RECT 66.21 219.01 66.57 219.74 ; + RECT 66.78 219.01 66.98 219.74 ; + RECT 68.135 0.18 68.905 0.88 ; + RECT 68.135 0.18 68.395 12.9 ; + RECT 68.645 0.18 68.905 12.9 ; + RECT 67.435 219.01 67.635 219.74 ; + RECT 67.845 219.01 68.205 219.74 ; + RECT 68.415 219.01 68.615 219.74 ; + RECT 69.07 219.01 69.27 219.74 ; + RECT 69.355 0.52 69.615 2.82 ; + RECT 69.48 219.01 69.84 219.74 ; + RECT 70.135 219.01 70.335 219.74 ; + RECT 70.63 219.01 70.99 219.74 ; + RECT 70.885 0.52 71.145 2.82 ; + RECT 71.2 219.01 71.4 219.74 ; + RECT 71.855 219.01 72.055 219.74 ; + RECT 72.06 0.52 72.32 4.315 ; + RECT 72.265 219.01 72.625 219.74 ; + RECT 72.835 219.01 73.035 219.74 ; + RECT 72.91 0.52 73.17 7.78 ; + RECT 73.42 0.3 73.68 5.235 ; + RECT 73.49 219.01 73.69 219.74 ; + RECT 73.93 0.52 74.19 5.57 ; + RECT 73.9 219.01 74.26 219.74 ; + RECT 74.555 219.01 74.755 219.74 ; + RECT 75.05 219.01 75.41 219.74 ; + RECT 75.305 0.52 75.565 6.28 ; + RECT 75.62 219.01 75.82 219.74 ; + RECT 76.275 219.01 76.475 219.74 ; + RECT 76.685 219.01 77.045 219.74 ; + RECT 77.255 219.01 77.455 219.74 ; + RECT 76.99 0.18 77.76 0.88 ; + RECT 77.91 219.01 78.11 219.74 ; + RECT 78.01 0.3 78.27 8.7 ; + RECT 78.32 219.01 78.68 219.74 ; + RECT 78.975 219.01 79.175 219.74 ; + RECT 79.47 219.01 79.83 219.74 ; + RECT 80.56 0.155 81.33 0.445 ; + RECT 80.56 0.155 80.82 8.665 ; + RECT 81.07 0.155 81.33 8.665 ; + RECT 80.04 219.01 80.24 219.74 ; + RECT 80.05 0.52 80.31 9.955 ; + RECT 80.695 219.01 80.895 219.74 ; + RECT 81.105 219.01 81.465 219.74 ; + RECT 81.58 0.52 81.84 11.315 ; + RECT 81.675 219.01 81.875 219.74 ; + RECT 82.09 0.52 82.35 13.45 ; + RECT 82.33 219.01 82.53 219.74 ; + RECT 82.6 0.52 82.86 14.115 ; + RECT 82.74 219.01 83.1 219.74 ; + RECT 83.395 219.01 83.595 219.74 ; + RECT 84.795 0.155 85.565 0.445 ; + RECT 84.795 0.155 85.055 13.21 ; + RECT 85.305 0.155 85.565 13.21 ; + RECT 83.89 219.01 84.25 219.74 ; + RECT 84.46 219.01 84.66 219.74 ; + RECT 85.815 0.18 86.585 0.88 ; + RECT 85.815 0.18 86.075 12.9 ; + RECT 86.325 0.18 86.585 12.9 ; + RECT 85.115 219.01 85.315 219.74 ; + RECT 85.525 219.01 85.885 219.74 ; + RECT 86.095 219.01 86.295 219.74 ; + RECT 86.75 219.01 86.95 219.74 ; + RECT 87.035 0.52 87.295 2.82 ; + RECT 87.16 219.01 87.52 219.74 ; + RECT 87.815 219.01 88.015 219.74 ; + RECT 88.31 219.01 88.67 219.74 ; + RECT 88.565 0.52 88.825 2.82 ; + RECT 88.88 219.01 89.08 219.74 ; + RECT 89.535 219.01 89.735 219.74 ; + RECT 89.74 0.52 90 4.315 ; + RECT 89.945 219.01 90.305 219.74 ; + RECT 90.515 219.01 90.715 219.74 ; + RECT 90.59 0.52 90.85 7.78 ; + RECT 91.1 0.3 91.36 5.235 ; + RECT 91.17 219.01 91.37 219.74 ; + RECT 91.61 0.52 91.87 5.57 ; + RECT 91.58 219.01 91.94 219.74 ; + RECT 92.235 219.01 92.435 219.74 ; + RECT 92.73 219.01 93.09 219.74 ; + RECT 92.985 0.52 93.245 6.28 ; + RECT 93.3 219.01 93.5 219.74 ; + RECT 93.955 219.01 94.155 219.74 ; + RECT 94.365 219.01 94.725 219.74 ; + RECT 94.935 219.01 95.135 219.74 ; + RECT 94.67 0.18 95.44 0.88 ; + RECT 95.59 219.01 95.79 219.74 ; + RECT 95.69 0.3 95.95 8.7 ; + RECT 96 219.01 96.36 219.74 ; + RECT 96.655 219.01 96.855 219.74 ; + RECT 97.15 219.01 97.51 219.74 ; + RECT 98.24 0.155 99.01 0.445 ; + RECT 98.24 0.155 98.5 8.665 ; + RECT 98.75 0.155 99.01 8.665 ; + RECT 97.72 219.01 97.92 219.74 ; + RECT 97.73 0.52 97.99 9.955 ; + RECT 98.375 219.01 98.575 219.74 ; + RECT 98.785 219.01 99.145 219.74 ; + RECT 99.26 0.52 99.52 11.315 ; + RECT 99.355 219.01 99.555 219.74 ; + RECT 99.77 0.52 100.03 13.45 ; + RECT 100.01 219.01 100.21 219.74 ; + RECT 100.28 0.52 100.54 14.115 ; + RECT 100.42 219.01 100.78 219.74 ; + RECT 101.075 219.01 101.275 219.74 ; + RECT 102.475 0.155 103.245 0.445 ; + RECT 102.475 0.155 102.735 13.21 ; + RECT 102.985 0.155 103.245 13.21 ; + RECT 101.57 219.01 101.93 219.74 ; + RECT 102.14 219.01 102.34 219.74 ; + RECT 103.495 0.18 104.265 0.88 ; + RECT 103.495 0.18 103.755 12.9 ; + RECT 104.005 0.18 104.265 12.9 ; + RECT 102.795 219.01 102.995 219.74 ; + RECT 103.205 219.01 103.565 219.74 ; + RECT 103.775 219.01 103.975 219.74 ; + RECT 104.43 219.01 104.63 219.74 ; + RECT 104.715 0.52 104.975 2.82 ; + RECT 104.84 219.01 105.2 219.74 ; + RECT 105.495 219.01 105.695 219.74 ; + RECT 105.99 219.01 106.35 219.74 ; + RECT 106.245 0.52 106.505 2.82 ; + RECT 106.56 219.01 106.76 219.74 ; + RECT 107.215 219.01 107.415 219.74 ; + RECT 107.42 0.52 107.68 4.315 ; + RECT 107.625 219.01 107.985 219.74 ; + RECT 108.195 219.01 108.395 219.74 ; + RECT 108.27 0.52 108.53 7.78 ; + RECT 108.78 0.3 109.04 5.235 ; + RECT 108.85 219.01 109.05 219.74 ; + RECT 109.29 0.52 109.55 5.57 ; + RECT 109.26 219.01 109.62 219.74 ; + RECT 109.915 219.01 110.115 219.74 ; + RECT 110.41 219.01 110.77 219.74 ; + RECT 110.665 0.52 110.925 6.28 ; + RECT 110.98 219.01 111.18 219.74 ; + RECT 111.635 219.01 111.835 219.74 ; + RECT 112.045 219.01 112.405 219.74 ; + RECT 112.615 219.01 112.815 219.74 ; + RECT 112.35 0.18 113.12 0.88 ; + RECT 113.27 219.01 113.47 219.74 ; + RECT 113.37 0.3 113.63 8.7 ; + RECT 113.68 219.01 114.04 219.74 ; + RECT 114.335 219.01 114.535 219.74 ; + RECT 114.83 219.01 115.19 219.74 ; + RECT 115.92 0.155 116.69 0.445 ; + RECT 115.92 0.155 116.18 8.665 ; + RECT 116.43 0.155 116.69 8.665 ; + RECT 115.4 219.01 115.6 219.74 ; + RECT 115.41 0.52 115.67 9.955 ; + RECT 116.055 219.01 116.255 219.74 ; + RECT 116.465 219.01 116.825 219.74 ; + RECT 116.94 0.52 117.2 11.315 ; + RECT 117.035 219.01 117.235 219.74 ; + RECT 117.45 0.52 117.71 13.45 ; + RECT 117.69 219.01 117.89 219.74 ; + RECT 117.96 0.52 118.22 14.115 ; + RECT 118.1 219.01 118.46 219.74 ; + RECT 118.755 219.01 118.955 219.74 ; + RECT 120.155 0.155 120.925 0.445 ; + RECT 120.155 0.155 120.415 13.21 ; + RECT 120.665 0.155 120.925 13.21 ; + RECT 119.25 219.01 119.61 219.74 ; + RECT 119.82 219.01 120.02 219.74 ; + RECT 121.175 0.18 121.945 0.88 ; + RECT 121.175 0.18 121.435 12.9 ; + RECT 121.685 0.18 121.945 12.9 ; + RECT 120.475 219.01 120.675 219.74 ; + RECT 120.885 219.01 121.245 219.74 ; + RECT 121.455 219.01 121.655 219.74 ; + RECT 122.11 219.01 122.31 219.74 ; + RECT 122.395 0.52 122.655 2.82 ; + RECT 122.52 219.01 122.88 219.74 ; + RECT 123.175 219.01 123.375 219.74 ; + RECT 123.67 219.01 124.03 219.74 ; + RECT 123.925 0.52 124.185 2.82 ; + RECT 124.24 219.01 124.44 219.74 ; + RECT 124.895 219.01 125.095 219.74 ; + RECT 125.1 0.52 125.36 4.315 ; + RECT 125.305 219.01 125.665 219.74 ; + RECT 125.875 219.01 126.075 219.74 ; + RECT 125.95 0.52 126.21 7.78 ; + RECT 126.46 0.3 126.72 5.235 ; + RECT 126.53 219.01 126.73 219.74 ; + RECT 126.97 0.52 127.23 5.57 ; + RECT 126.94 219.01 127.3 219.74 ; + RECT 127.595 219.01 127.795 219.74 ; + RECT 128.09 219.01 128.45 219.74 ; + RECT 128.345 0.52 128.605 6.28 ; + RECT 128.66 219.01 128.86 219.74 ; + RECT 129.315 219.01 129.515 219.74 ; + RECT 129.725 219.01 130.085 219.74 ; + RECT 130.295 219.01 130.495 219.74 ; + RECT 130.03 0.18 130.8 0.88 ; + RECT 130.95 219.01 131.15 219.74 ; + RECT 131.05 0.3 131.31 8.7 ; + RECT 131.36 219.01 131.72 219.74 ; + RECT 132.015 219.01 132.215 219.74 ; + RECT 132.51 219.01 132.87 219.74 ; + RECT 133.6 0.155 134.37 0.445 ; + RECT 133.6 0.155 133.86 8.665 ; + RECT 134.11 0.155 134.37 8.665 ; + RECT 133.08 219.01 133.28 219.74 ; + RECT 133.09 0.52 133.35 9.955 ; + RECT 133.735 219.01 133.935 219.74 ; + RECT 134.145 219.01 134.505 219.74 ; + RECT 134.62 0.52 134.88 11.315 ; + RECT 134.715 219.01 134.915 219.74 ; + RECT 135.13 0.52 135.39 13.45 ; + RECT 135.37 219.01 135.57 219.74 ; + RECT 135.64 0.52 135.9 14.115 ; + RECT 135.78 219.01 136.14 219.74 ; + RECT 136.435 219.01 136.635 219.74 ; + RECT 137.835 0.155 138.605 0.445 ; + RECT 137.835 0.155 138.095 13.21 ; + RECT 138.345 0.155 138.605 13.21 ; + RECT 136.93 219.01 137.29 219.74 ; + RECT 137.5 219.01 137.7 219.74 ; + RECT 138.855 0.18 139.625 0.88 ; + RECT 138.855 0.18 139.115 12.9 ; + RECT 139.365 0.18 139.625 12.9 ; + RECT 138.155 219.01 138.355 219.74 ; + RECT 138.565 219.01 138.925 219.74 ; + RECT 139.135 219.01 139.335 219.74 ; + RECT 139.79 219.01 139.99 219.74 ; + RECT 140.075 0.52 140.335 2.82 ; + RECT 140.2 219.01 140.56 219.74 ; + RECT 140.855 219.01 141.055 219.74 ; + RECT 141.35 219.01 141.71 219.74 ; + RECT 141.605 0.52 141.865 2.82 ; + RECT 141.92 219.01 142.12 219.74 ; + RECT 142.575 219.01 142.775 219.74 ; + RECT 142.78 0.52 143.04 4.315 ; + RECT 142.985 219.01 143.345 219.74 ; + RECT 143.555 219.01 143.755 219.74 ; + RECT 143.63 0.52 143.89 7.78 ; + RECT 144.14 0.3 144.4 5.235 ; + RECT 144.21 219.01 144.41 219.74 ; + RECT 144.65 0.52 144.91 5.57 ; + RECT 144.62 219.01 144.98 219.74 ; + RECT 145.275 219.01 145.475 219.74 ; + RECT 145.77 219.01 146.13 219.74 ; + RECT 146.025 0.52 146.285 6.28 ; + RECT 146.34 219.01 146.54 219.74 ; + RECT 146.995 219.01 147.195 219.74 ; + RECT 147.405 219.01 147.765 219.74 ; + RECT 147.975 219.01 148.175 219.74 ; + RECT 147.71 0.18 148.48 0.88 ; + RECT 148.63 219.01 148.83 219.74 ; + RECT 148.73 0.3 148.99 8.7 ; + RECT 149.04 219.01 149.4 219.74 ; + RECT 149.695 219.01 149.895 219.74 ; + RECT 150.19 219.01 150.55 219.74 ; + RECT 151.28 0.155 152.05 0.445 ; + RECT 151.28 0.155 151.54 8.665 ; + RECT 151.79 0.155 152.05 8.665 ; + RECT 150.76 219.01 150.96 219.74 ; + RECT 150.77 0.52 151.03 9.955 ; + RECT 151.415 219.01 151.615 219.74 ; + RECT 151.825 219.01 152.185 219.74 ; + RECT 152.3 0.52 152.56 11.315 ; + RECT 152.395 219.01 152.595 219.74 ; + RECT 152.81 0.52 153.07 13.45 ; + RECT 153.05 219.01 153.25 219.74 ; + RECT 153.32 0.52 153.58 14.115 ; + RECT 153.46 219.01 153.82 219.74 ; + RECT 154.115 219.01 154.315 219.74 ; + RECT 155.515 0.155 156.285 0.445 ; + RECT 155.515 0.155 155.775 13.21 ; + RECT 156.025 0.155 156.285 13.21 ; + RECT 154.61 219.01 154.97 219.74 ; + RECT 155.18 219.01 155.38 219.74 ; + RECT 156.535 0.18 157.305 0.88 ; + RECT 156.535 0.18 156.795 12.9 ; + RECT 157.045 0.18 157.305 12.9 ; + RECT 155.835 219.01 156.035 219.74 ; + RECT 156.245 219.01 156.605 219.74 ; + RECT 156.815 219.01 157.015 219.74 ; + RECT 157.47 219.01 157.67 219.74 ; + RECT 157.755 0.52 158.015 2.82 ; + RECT 157.88 219.01 158.24 219.74 ; + RECT 158.535 219.01 158.735 219.74 ; + RECT 159.03 219.01 159.39 219.74 ; + RECT 159.285 0.52 159.545 2.82 ; + RECT 159.6 219.01 159.8 219.74 ; + RECT 160.255 219.01 160.455 219.74 ; + RECT 160.46 0.52 160.72 4.315 ; + RECT 160.665 219.01 161.025 219.74 ; + RECT 161.235 219.01 161.435 219.74 ; + RECT 161.31 0.52 161.57 7.78 ; + RECT 161.82 0.3 162.08 5.235 ; + RECT 161.89 219.01 162.09 219.74 ; + RECT 162.33 0.52 162.59 5.57 ; + RECT 162.3 219.01 162.66 219.74 ; + RECT 162.955 219.01 163.155 219.74 ; + RECT 163.45 219.01 163.81 219.74 ; + RECT 163.705 0.52 163.965 6.28 ; + RECT 164.02 219.01 164.22 219.74 ; + RECT 164.675 219.01 164.875 219.74 ; + RECT 165.085 219.01 165.445 219.74 ; + RECT 165.655 219.01 165.855 219.74 ; + RECT 165.39 0.18 166.16 0.88 ; + RECT 166.31 219.01 166.51 219.74 ; + RECT 166.41 0.3 166.67 8.7 ; + RECT 166.72 219.01 167.08 219.74 ; + RECT 167.375 219.01 167.575 219.74 ; + RECT 167.87 219.01 168.23 219.74 ; + RECT 168.96 0.155 169.73 0.445 ; + RECT 168.96 0.155 169.22 8.665 ; + RECT 169.47 0.155 169.73 8.665 ; + RECT 168.44 219.01 168.64 219.74 ; + RECT 168.45 0.52 168.71 9.955 ; + RECT 169.095 219.01 169.295 219.74 ; + RECT 169.505 219.01 169.865 219.74 ; + RECT 169.98 0.52 170.24 11.315 ; + RECT 170.075 219.01 170.275 219.74 ; + RECT 170.49 0.52 170.75 13.45 ; + RECT 170.73 219.01 170.93 219.74 ; + RECT 171 0.52 171.26 14.115 ; + RECT 171.14 219.01 171.5 219.74 ; + RECT 171.795 219.01 171.995 219.74 ; + RECT 173.195 0.155 173.965 0.445 ; + RECT 173.195 0.155 173.455 13.21 ; + RECT 173.705 0.155 173.965 13.21 ; + RECT 172.29 219.01 172.65 219.74 ; + RECT 172.86 219.01 173.06 219.74 ; + RECT 174.215 0.18 174.985 0.88 ; + RECT 174.215 0.18 174.475 12.9 ; + RECT 174.725 0.18 174.985 12.9 ; + RECT 173.515 219.01 173.715 219.74 ; + RECT 173.925 219.01 174.285 219.74 ; + RECT 174.495 219.01 174.695 219.74 ; + RECT 175.15 219.01 175.35 219.74 ; + RECT 175.435 0.52 175.695 2.82 ; + RECT 175.56 219.01 175.92 219.74 ; + RECT 176.215 219.01 176.415 219.74 ; + RECT 176.71 219.01 177.07 219.74 ; + RECT 176.965 0.52 177.225 2.82 ; + RECT 177.28 219.01 177.48 219.74 ; + RECT 177.935 219.01 178.135 219.74 ; + RECT 178.14 0.52 178.4 4.315 ; + RECT 178.345 219.01 178.705 219.74 ; + RECT 178.915 219.01 179.115 219.74 ; + RECT 178.99 0.52 179.25 7.78 ; + RECT 179.5 0.3 179.76 5.235 ; + RECT 179.57 219.01 179.77 219.74 ; + RECT 180.01 0.52 180.27 5.57 ; + RECT 179.98 219.01 180.34 219.74 ; + RECT 180.635 219.01 180.835 219.74 ; + RECT 181.13 219.01 181.49 219.74 ; + RECT 181.385 0.52 181.645 6.28 ; + RECT 181.7 219.01 181.9 219.74 ; + RECT 182.355 219.01 182.555 219.74 ; + RECT 182.765 219.01 183.125 219.74 ; + RECT 183.335 219.01 183.535 219.74 ; + RECT 183.07 0.18 183.84 0.88 ; + RECT 183.99 219.01 184.19 219.74 ; + RECT 184.09 0.3 184.35 8.7 ; + RECT 184.4 219.01 184.76 219.74 ; + RECT 185.055 219.01 185.255 219.74 ; + RECT 185.55 219.01 185.91 219.74 ; + RECT 186.64 0.155 187.41 0.445 ; + RECT 186.64 0.155 186.9 8.665 ; + RECT 187.15 0.155 187.41 8.665 ; + RECT 186.12 219.01 186.32 219.74 ; + RECT 186.13 0.52 186.39 9.955 ; + RECT 186.775 219.01 186.975 219.74 ; + RECT 187.185 219.01 187.545 219.74 ; + RECT 187.66 0.52 187.92 11.315 ; + RECT 187.755 219.01 187.955 219.74 ; + RECT 188.17 0.52 188.43 13.45 ; + RECT 188.41 219.01 188.61 219.74 ; + RECT 188.68 0.52 188.94 14.115 ; + RECT 188.82 219.01 189.18 219.74 ; + RECT 189.475 219.01 189.675 219.74 ; + RECT 190.875 0.155 191.645 0.445 ; + RECT 190.875 0.155 191.135 13.21 ; + RECT 191.385 0.155 191.645 13.21 ; + RECT 189.97 219.01 190.33 219.74 ; + RECT 190.54 219.01 190.74 219.74 ; + RECT 191.895 0.18 192.665 0.88 ; + RECT 191.895 0.18 192.155 12.9 ; + RECT 192.405 0.18 192.665 12.9 ; + RECT 191.195 219.01 191.395 219.74 ; + RECT 191.605 219.01 191.965 219.74 ; + RECT 192.175 219.01 192.375 219.74 ; + RECT 192.83 219.01 193.03 219.74 ; + RECT 193.115 0.52 193.375 2.82 ; + RECT 193.24 219.01 193.6 219.74 ; + RECT 193.895 219.01 194.095 219.74 ; + RECT 194.39 219.01 194.75 219.74 ; + RECT 194.645 0.52 194.905 2.82 ; + RECT 194.96 219.01 195.16 219.74 ; + RECT 195.615 219.01 195.815 219.74 ; + RECT 195.82 0.52 196.08 4.315 ; + RECT 196.025 219.01 196.385 219.74 ; + RECT 196.595 219.01 196.795 219.74 ; + RECT 196.67 0.52 196.93 7.78 ; + RECT 197.18 0.3 197.44 5.235 ; + RECT 197.25 219.01 197.45 219.74 ; + RECT 197.69 0.52 197.95 5.57 ; + RECT 197.66 219.01 198.02 219.74 ; + RECT 198.315 219.01 198.515 219.74 ; + RECT 198.81 219.01 199.17 219.74 ; + RECT 199.065 0.52 199.325 6.28 ; + RECT 199.38 219.01 199.58 219.74 ; + RECT 200.035 219.01 200.235 219.74 ; + RECT 200.445 219.01 200.805 219.74 ; + RECT 201.015 219.01 201.215 219.74 ; + RECT 200.75 0.18 201.52 0.88 ; + RECT 201.67 219.01 201.87 219.74 ; + RECT 201.77 0.3 202.03 8.7 ; + RECT 202.08 219.01 202.44 219.74 ; + RECT 202.735 219.01 202.935 219.74 ; + RECT 203.23 219.01 203.59 219.74 ; + RECT 204.32 0.155 205.09 0.445 ; + RECT 204.32 0.155 204.58 8.665 ; + RECT 204.83 0.155 205.09 8.665 ; + RECT 203.8 219.01 204 219.74 ; + RECT 203.81 0.52 204.07 9.955 ; + RECT 204.455 219.01 204.655 219.74 ; + RECT 204.865 219.01 205.225 219.74 ; + RECT 205.34 0.52 205.6 11.315 ; + RECT 205.435 219.01 205.635 219.74 ; + RECT 205.85 0.52 206.11 13.45 ; + RECT 206.09 219.01 206.29 219.74 ; + RECT 206.36 0.52 206.62 14.115 ; + RECT 206.5 219.01 206.86 219.74 ; + RECT 207.155 219.01 207.355 219.74 ; + RECT 208.555 0.155 209.325 0.445 ; + RECT 208.555 0.155 208.815 13.21 ; + RECT 209.065 0.155 209.325 13.21 ; + RECT 207.65 219.01 208.01 219.74 ; + RECT 208.22 219.01 208.42 219.74 ; + RECT 209.575 0.18 210.345 0.88 ; + RECT 209.575 0.18 209.835 12.9 ; + RECT 210.085 0.18 210.345 12.9 ; + RECT 208.875 219.01 209.075 219.74 ; + RECT 209.285 219.01 209.645 219.74 ; + RECT 209.855 219.01 210.055 219.74 ; + RECT 210.51 219.01 210.71 219.74 ; + RECT 210.795 0.52 211.055 2.82 ; + RECT 210.92 219.01 211.28 219.74 ; + RECT 211.575 219.01 211.775 219.74 ; + RECT 212.07 219.01 212.43 219.74 ; + RECT 212.325 0.52 212.585 2.82 ; + RECT 212.64 219.01 212.84 219.74 ; + RECT 213.295 219.01 213.495 219.74 ; + RECT 213.5 0.52 213.76 4.315 ; + RECT 213.705 219.01 214.065 219.74 ; + RECT 214.275 219.01 214.475 219.74 ; + RECT 214.35 0.52 214.61 7.78 ; + RECT 214.86 0.3 215.12 5.235 ; + RECT 214.93 219.01 215.13 219.74 ; + RECT 215.37 0.52 215.63 5.57 ; + RECT 215.34 219.01 215.7 219.74 ; + RECT 215.995 219.01 216.195 219.74 ; + RECT 216.49 219.01 216.85 219.74 ; + RECT 216.745 0.52 217.005 6.28 ; + RECT 217.06 219.01 217.26 219.74 ; + RECT 217.715 219.01 217.915 219.74 ; + RECT 218.125 219.01 218.485 219.74 ; + RECT 218.695 219.01 218.895 219.74 ; + RECT 218.43 0.18 219.2 0.88 ; + RECT 219.35 219.01 219.55 219.74 ; + RECT 219.45 0.3 219.71 8.7 ; + RECT 219.76 219.01 220.12 219.74 ; + RECT 220.415 219.01 220.615 219.74 ; + RECT 220.91 219.01 221.27 219.74 ; + RECT 222 0.155 222.77 0.445 ; + RECT 222 0.155 222.26 8.665 ; + RECT 222.51 0.155 222.77 8.665 ; + RECT 221.48 219.01 221.68 219.74 ; + RECT 221.49 0.52 221.75 9.955 ; + RECT 222.135 219.01 222.335 219.74 ; + RECT 222.545 219.01 222.905 219.74 ; + RECT 223.02 0.52 223.28 11.315 ; + RECT 223.115 219.01 223.315 219.74 ; + RECT 223.53 0.52 223.79 13.45 ; + RECT 223.77 219.01 223.97 219.74 ; + RECT 224.04 0.52 224.3 14.115 ; + RECT 224.18 219.01 224.54 219.74 ; + RECT 224.835 219.01 225.035 219.74 ; + RECT 226.235 0.155 227.005 0.445 ; + RECT 226.235 0.155 226.495 13.21 ; + RECT 226.745 0.155 227.005 13.21 ; + RECT 225.33 219.01 225.69 219.74 ; + RECT 225.9 219.01 226.1 219.74 ; + RECT 227.255 0.18 228.025 0.88 ; + RECT 227.255 0.18 227.515 12.9 ; + RECT 227.765 0.18 228.025 12.9 ; + RECT 226.555 219.01 226.755 219.74 ; + RECT 226.965 219.01 227.325 219.74 ; + RECT 227.535 219.01 227.735 219.74 ; + RECT 228.19 219.01 228.39 219.74 ; + RECT 228.475 0.52 228.735 2.82 ; + RECT 228.6 219.01 228.96 219.74 ; + RECT 229.255 219.01 229.455 219.74 ; + RECT 229.75 219.01 230.11 219.74 ; + RECT 230.005 0.52 230.265 2.82 ; + RECT 230.32 219.01 230.52 219.74 ; + RECT 230.975 219.01 231.175 219.74 ; + RECT 231.18 0.52 231.44 4.315 ; + RECT 231.385 219.01 231.745 219.74 ; + RECT 231.955 219.01 232.155 219.74 ; + RECT 232.03 0.52 232.29 7.78 ; + RECT 232.54 0.3 232.8 5.235 ; + RECT 232.61 219.01 232.81 219.74 ; + RECT 233.05 0.52 233.31 5.57 ; + RECT 233.02 219.01 233.38 219.74 ; + RECT 233.675 219.01 233.875 219.74 ; + RECT 234.17 219.01 234.53 219.74 ; + RECT 234.425 0.52 234.685 6.28 ; + RECT 234.74 219.01 234.94 219.74 ; + RECT 235.395 219.01 235.595 219.74 ; + RECT 235.805 219.01 236.165 219.74 ; + RECT 236.375 219.01 236.575 219.74 ; + RECT 236.11 0.18 236.88 0.88 ; + RECT 237.03 219.01 237.23 219.74 ; + RECT 237.13 0.3 237.39 8.7 ; + RECT 237.44 219.01 237.8 219.74 ; + RECT 238.095 219.01 238.295 219.74 ; + RECT 238.59 219.01 238.95 219.74 ; + RECT 239.68 0.155 240.45 0.445 ; + RECT 239.68 0.155 239.94 8.665 ; + RECT 240.19 0.155 240.45 8.665 ; + RECT 239.16 219.01 239.36 219.74 ; + RECT 239.17 0.52 239.43 9.955 ; + RECT 239.815 219.01 240.015 219.74 ; + RECT 240.225 219.01 240.585 219.74 ; + RECT 240.7 0.52 240.96 11.315 ; + RECT 240.795 219.01 240.995 219.74 ; + RECT 241.21 0.52 241.47 13.45 ; + RECT 241.45 219.01 241.65 219.74 ; + RECT 241.72 0.52 241.98 14.115 ; + RECT 241.86 219.01 242.22 219.74 ; + RECT 242.515 219.01 242.715 219.74 ; + RECT 243.915 0.155 244.685 0.445 ; + RECT 243.915 0.155 244.175 13.21 ; + RECT 244.425 0.155 244.685 13.21 ; + RECT 243.01 219.01 243.37 219.74 ; + RECT 243.58 219.01 243.78 219.74 ; + RECT 244.935 0.18 245.705 0.88 ; + RECT 244.935 0.18 245.195 12.9 ; + RECT 245.445 0.18 245.705 12.9 ; + RECT 244.235 219.01 244.435 219.74 ; + RECT 244.645 219.01 245.005 219.74 ; + RECT 245.215 219.01 245.415 219.74 ; + RECT 245.87 219.01 246.07 219.74 ; + RECT 246.155 0.52 246.415 2.82 ; + RECT 246.28 219.01 246.64 219.74 ; + RECT 246.935 219.01 247.135 219.74 ; + RECT 247.43 219.01 247.79 219.74 ; + RECT 247.685 0.52 247.945 2.82 ; + RECT 248 219.01 248.2 219.74 ; + RECT 248.655 219.01 248.855 219.74 ; + RECT 248.86 0.52 249.12 4.315 ; + RECT 249.065 219.01 249.425 219.74 ; + RECT 249.635 219.01 249.835 219.74 ; + RECT 249.71 0.52 249.97 7.78 ; + RECT 250.22 0.3 250.48 5.235 ; + RECT 250.29 219.01 250.49 219.74 ; + RECT 250.73 0.52 250.99 5.57 ; + RECT 250.7 219.01 251.06 219.74 ; + RECT 251.355 219.01 251.555 219.74 ; + RECT 251.85 219.01 252.21 219.74 ; + RECT 252.105 0.52 252.365 6.28 ; + RECT 252.42 219.01 252.62 219.74 ; + RECT 253.075 219.01 253.275 219.74 ; + RECT 253.485 219.01 253.845 219.74 ; + RECT 254.055 219.01 254.255 219.74 ; + RECT 253.79 0.18 254.56 0.88 ; + RECT 254.71 219.01 254.91 219.74 ; + RECT 254.81 0.3 255.07 8.7 ; + RECT 255.12 219.01 255.48 219.74 ; + RECT 255.775 219.01 255.975 219.74 ; + RECT 256.27 219.01 256.63 219.74 ; + RECT 257.36 0.155 258.13 0.445 ; + RECT 257.36 0.155 257.62 8.665 ; + RECT 257.87 0.155 258.13 8.665 ; + RECT 256.84 219.01 257.04 219.74 ; + RECT 256.85 0.52 257.11 9.955 ; + RECT 257.495 219.01 257.695 219.74 ; + RECT 257.905 219.01 258.265 219.74 ; + RECT 258.38 0.52 258.64 11.315 ; + RECT 258.475 219.01 258.675 219.74 ; + RECT 258.89 0.52 259.15 13.45 ; + RECT 259.13 219.01 259.33 219.74 ; + RECT 259.4 0.52 259.66 14.115 ; + RECT 259.54 219.01 259.9 219.74 ; + RECT 260.195 219.01 260.395 219.74 ; + RECT 261.595 0.155 262.365 0.445 ; + RECT 261.595 0.155 261.855 13.21 ; + RECT 262.105 0.155 262.365 13.21 ; + RECT 260.69 219.01 261.05 219.74 ; + RECT 261.26 219.01 261.46 219.74 ; + RECT 262.615 0.18 263.385 0.88 ; + RECT 262.615 0.18 262.875 12.9 ; + RECT 263.125 0.18 263.385 12.9 ; + RECT 261.915 219.01 262.115 219.74 ; + RECT 262.325 219.01 262.685 219.74 ; + RECT 262.895 219.01 263.095 219.74 ; + RECT 263.55 219.01 263.75 219.74 ; + RECT 263.835 0.52 264.095 2.82 ; + RECT 263.96 219.01 264.32 219.74 ; + RECT 264.615 219.01 264.815 219.74 ; + RECT 265.11 219.01 265.47 219.74 ; + RECT 265.365 0.52 265.625 2.82 ; + RECT 265.68 219.01 265.88 219.74 ; + RECT 266.335 219.01 266.535 219.74 ; + RECT 266.54 0.52 266.8 4.315 ; + RECT 266.745 219.01 267.105 219.74 ; + RECT 267.315 219.01 267.515 219.74 ; + RECT 267.39 0.52 267.65 7.78 ; + RECT 267.9 0.3 268.16 5.235 ; + RECT 267.97 219.01 268.17 219.74 ; + RECT 268.41 0.52 268.67 5.57 ; + RECT 268.38 219.01 268.74 219.74 ; + RECT 269.035 219.01 269.235 219.74 ; + RECT 269.53 219.01 269.89 219.74 ; + RECT 269.785 0.52 270.045 6.28 ; + RECT 270.1 219.01 270.3 219.74 ; + RECT 270.755 219.01 270.955 219.74 ; + RECT 271.165 219.01 271.525 219.74 ; + RECT 271.735 219.01 271.935 219.74 ; + RECT 271.47 0.18 272.24 0.88 ; + RECT 272.39 219.01 272.59 219.74 ; + RECT 272.49 0.3 272.75 8.7 ; + RECT 272.8 219.01 273.16 219.74 ; + RECT 273.455 219.01 273.655 219.74 ; + RECT 273.95 219.01 274.31 219.74 ; + RECT 275.04 0.155 275.81 0.445 ; + RECT 275.04 0.155 275.3 8.665 ; + RECT 275.55 0.155 275.81 8.665 ; + RECT 274.52 219.01 274.72 219.74 ; + RECT 274.53 0.52 274.79 9.955 ; + RECT 275.175 219.01 275.375 219.74 ; + RECT 275.585 219.01 275.945 219.74 ; + RECT 276.06 0.52 276.32 11.315 ; + RECT 276.155 219.01 276.355 219.74 ; + RECT 276.57 0.52 276.83 13.45 ; + RECT 276.81 219.01 277.01 219.74 ; + RECT 277.08 0.52 277.34 14.115 ; + RECT 277.22 219.01 277.58 219.74 ; + RECT 277.875 219.01 278.075 219.74 ; + RECT 279.275 0.155 280.045 0.445 ; + RECT 279.275 0.155 279.535 13.21 ; + RECT 279.785 0.155 280.045 13.21 ; + RECT 278.37 219.01 278.73 219.74 ; + RECT 278.94 219.01 279.14 219.74 ; + RECT 280.295 0.18 281.065 0.88 ; + RECT 280.295 0.18 280.555 12.9 ; + RECT 280.805 0.18 281.065 12.9 ; + RECT 279.595 219.01 279.795 219.74 ; + RECT 280.005 219.01 280.365 219.74 ; + RECT 280.575 219.01 280.775 219.74 ; + RECT 281.23 219.01 281.43 219.74 ; + RECT 281.515 0.52 281.775 2.82 ; + RECT 281.64 219.01 282 219.74 ; + RECT 282.295 219.01 282.495 219.74 ; + RECT 282.79 219.01 283.15 219.74 ; + RECT 283.045 0.52 283.305 2.82 ; + RECT 283.36 219.01 283.56 219.74 ; + RECT 284.015 219.01 284.215 219.74 ; + RECT 285.24 0.17 286.01 0.43 ; + RECT 285.24 0.17 285.5 8.7 ; + RECT 285.75 0.17 286.01 8.7 ; + RECT 284.22 0.52 284.48 4.315 ; + RECT 286.26 0.18 287.03 0.88 ; + RECT 286.26 0.18 286.52 8.7 ; + RECT 286.77 0.18 287.03 8.7 ; + RECT 287.28 0.17 288.05 0.43 ; + RECT 287.28 0.17 287.54 8.7 ; + RECT 287.79 0.17 288.05 8.7 ; + RECT 288.3 0.18 289.07 0.88 ; + RECT 288.3 0.18 288.56 8.7 ; + RECT 288.81 0.18 289.07 8.7 ; + RECT 289.32 0.17 290.09 0.43 ; + RECT 289.32 0.17 289.58 8.7 ; + RECT 289.83 0.17 290.09 8.7 ; + RECT 290.34 0.18 291.11 0.88 ; + RECT 290.34 0.18 290.6 8.7 ; + RECT 290.85 0.18 291.11 8.7 ; + RECT 291.36 0.17 292.13 0.43 ; + RECT 291.36 0.17 291.62 8.7 ; + RECT 291.87 0.17 292.13 8.7 ; + RECT 292.38 0.18 293.15 0.88 ; + RECT 292.38 0.18 292.64 8.7 ; + RECT 292.89 0.18 293.15 8.7 ; + RECT 293.4 0.17 294.17 0.43 ; + RECT 293.4 0.17 293.66 8.7 ; + RECT 293.91 0.17 294.17 8.7 ; + RECT 294.42 0.18 295.19 0.88 ; + RECT 294.42 0.18 294.68 8.7 ; + RECT 294.93 0.18 295.19 8.7 ; + RECT 295.44 0.17 296.21 0.43 ; + RECT 295.44 0.17 295.7 8.7 ; + RECT 295.95 0.17 296.21 8.7 ; + RECT 296.46 0.18 297.23 0.88 ; + RECT 296.46 0.18 296.72 8.7 ; + RECT 296.97 0.18 297.23 8.7 ; + RECT 297.48 0.17 298.25 0.43 ; + RECT 297.48 0.17 297.74 8.7 ; + RECT 297.99 0.17 298.25 8.7 ; + RECT 298.5 0.18 299.27 0.88 ; + RECT 298.5 0.18 298.76 8.7 ; + RECT 299.01 0.18 299.27 8.7 ; + RECT 299.52 0.17 300.29 0.43 ; + RECT 299.52 0.17 299.78 8.7 ; + RECT 300.03 0.17 300.29 8.7 ; + RECT 300.54 0.18 301.31 0.88 ; + RECT 300.54 0.18 300.8 8.7 ; + RECT 301.05 0.18 301.31 8.7 ; + RECT 284.425 219.01 284.785 219.74 ; + RECT 284.995 219.01 285.195 219.74 ; + RECT 302.935 0.18 303.705 0.88 ; + RECT 302.935 0.18 303.195 8.7 ; + RECT 303.445 0.18 303.705 8.7 ; + RECT 303.955 0.17 304.725 0.43 ; + RECT 303.955 0.17 304.215 8.7 ; + RECT 304.465 0.17 304.725 8.7 ; + RECT 285.82 218.93 286.02 219.74 ; + RECT 301.915 0.3 302.175 8.7 ; + RECT 305.995 0.18 306.765 0.88 ; + RECT 305.995 0.18 306.255 8.7 ; + RECT 306.505 0.18 306.765 8.7 ; + RECT 302.425 0.3 302.685 8.7 ; + RECT 304.975 0 305.235 8.7 ; + RECT 305.485 0 305.745 8.7 ; + RECT 307.015 0.52 307.275 8.7 ; + RECT 307.525 0.3 307.785 8.7 ; + RECT 308.035 0.3 308.295 8.7 ; + RECT 308.545 0.3 308.805 8.7 ; + RECT 309.055 0.3 309.315 8.7 ; + RECT 309.565 0.3 309.825 8.7 ; + RECT 310.075 0.3 310.335 8.7 ; + RECT 310.585 0.3 310.845 8.7 ; + RECT 312.625 0.18 313.395 0.88 ; + RECT 312.625 0.18 312.885 8.7 ; + RECT 313.135 0.18 313.395 8.7 ; + RECT 311.095 0.3 311.355 8.7 ; + RECT 311.605 0.52 311.865 8.7 ; + RECT 312.115 0.52 312.375 8.7 ; + RECT 313.645 0 313.905 8.7 ; + RECT 314.155 0 314.415 8.7 ; + RECT 314.665 0.52 314.925 8.7 ; + RECT 315.175 0.52 315.435 8.7 ; + RECT 315.685 0.52 315.945 8.7 ; + RECT 316.195 0.52 316.455 8.7 ; + RECT 316.705 0.52 316.965 8.7 ; + RECT 317.215 0.52 317.475 8.7 ; + RECT 317.725 0.52 317.985 8.7 ; + RECT 318.235 0.52 318.495 8.7 ; + RECT 318.745 0.3 319.005 8.7 ; + RECT 319.255 0.3 319.515 8.7 ; + RECT 319.765 0.3 320.025 8.7 ; + RECT 320.275 0.52 320.535 8.7 ; + RECT 320.785 0.52 321.045 8.7 ; + RECT 321.295 0.3 321.555 8.7 ; + RECT 321.805 0.3 322.065 8.7 ; + RECT 322.315 0.3 322.575 8.7 ; + RECT 322.825 0.52 323.085 8.7 ; + RECT 323.335 0.52 323.595 8.7 ; + RECT 323.845 0.3 324.105 8.7 ; + RECT 324.355 0.52 324.615 8.7 ; + RECT 324.865 0.52 325.125 8.7 ; + RECT 325.375 0.52 325.635 8.7 ; + RECT 325.885 0.52 326.145 8.7 ; + RECT 326.395 0.52 326.655 8.7 ; + RECT 326.905 0.3 327.165 8.7 ; + RECT 327.415 0.52 327.675 8.7 ; + RECT 327.925 0.52 328.185 8.7 ; + RECT 328.435 0.3 328.695 8.7 ; + RECT 328.945 0.52 329.205 8.7 ; + RECT 330.985 0.17 331.755 0.43 ; + RECT 330.985 0.17 331.245 8.7 ; + RECT 331.495 0.17 331.755 8.7 ; + RECT 329.455 0.52 329.715 8.7 ; + RECT 329.965 0.3 330.225 8.7 ; + RECT 330.475 0.3 330.735 8.7 ; + RECT 333.535 0.17 334.305 0.43 ; + RECT 333.535 0.17 333.795 8.7 ; + RECT 334.045 0.17 334.305 8.7 ; + RECT 332.005 0.3 332.265 8.7 ; + RECT 335.065 0.18 335.835 0.88 ; + RECT 335.065 0.18 335.325 8.7 ; + RECT 335.575 0.18 335.835 8.7 ; + RECT 332.515 0.3 332.775 8.7 ; + RECT 333.025 0.3 333.285 8.7 ; + RECT 334.555 0.3 334.815 8.7 ; + RECT 336.085 0 336.345 8.7 ; + RECT 336.595 0 336.855 8.7 ; + RECT 337.105 0.52 337.365 8.7 ; + RECT 337.615 0.52 337.875 8.7 ; + RECT 338.125 0.52 338.385 8.7 ; + RECT 338.635 0.52 338.895 8.7 ; + RECT 339.145 0 339.405 8.7 ; + RECT 339.655 0 339.915 8.7 ; + RECT 340.165 0.3 340.425 8.7 ; + RECT 340.675 0.3 340.935 8.7 ; + RECT 341.185 0 341.445 8.7 ; + RECT 341.695 0 341.955 8.7 ; + RECT 342.205 0.3 342.465 8.7 ; + RECT 343.025 0.3 343.285 8.7 ; + RECT 343.535 0 343.795 8.7 ; + RECT 344.045 0 344.305 8.7 ; + RECT 344.555 0.3 344.815 8.7 ; + RECT 345.065 0.3 345.325 8.7 ; + RECT 345.575 0 345.835 8.7 ; + RECT 346.085 0 346.345 8.7 ; + RECT 346.595 0.52 346.855 8.7 ; + RECT 347.105 0.52 347.365 8.7 ; + RECT 347.615 0.52 347.875 8.7 ; + RECT 349.655 0.18 350.425 0.88 ; + RECT 349.655 0.18 349.915 8.7 ; + RECT 350.165 0.18 350.425 8.7 ; + RECT 348.125 0.52 348.385 8.7 ; + RECT 351.185 0.17 351.955 0.43 ; + RECT 351.185 0.17 351.445 8.7 ; + RECT 351.695 0.17 351.955 8.7 ; + RECT 348.635 0 348.895 8.7 ; + RECT 349.145 0 349.405 8.7 ; + RECT 350.675 0.3 350.935 8.7 ; + RECT 353.735 0.17 354.505 0.43 ; + RECT 353.735 0.17 353.995 8.7 ; + RECT 354.245 0.17 354.505 8.7 ; + RECT 352.205 0.3 352.465 8.7 ; + RECT 352.715 0.3 352.975 8.7 ; + RECT 353.225 0.3 353.485 8.7 ; + RECT 354.755 0.3 355.015 8.7 ; + RECT 355.265 0.3 355.525 8.7 ; + RECT 355.775 0.52 356.035 8.7 ; + RECT 356.285 0.52 356.545 8.7 ; + RECT 356.795 0.3 357.055 8.7 ; + RECT 357.305 0.52 357.565 8.7 ; + RECT 357.815 0.52 358.075 8.7 ; + RECT 358.325 0.3 358.585 8.7 ; + RECT 358.835 0.52 359.095 8.7 ; + RECT 359.345 0.52 359.605 8.7 ; + RECT 359.855 0.52 360.115 8.7 ; + RECT 360.365 0.52 360.625 8.7 ; + RECT 360.875 0.52 361.135 8.7 ; + RECT 361.385 0.3 361.645 8.7 ; + RECT 361.895 0.52 362.155 8.7 ; + RECT 362.405 0.52 362.665 8.7 ; + RECT 362.915 0.3 363.175 8.7 ; + RECT 363.425 0.3 363.685 8.7 ; + RECT 363.935 0.3 364.195 8.7 ; + RECT 364.445 0.52 364.705 8.7 ; + RECT 364.955 0.52 365.215 8.7 ; + RECT 365.465 0.3 365.725 8.7 ; + RECT 365.975 0.3 366.235 8.7 ; + RECT 366.485 0.3 366.745 8.7 ; + RECT 366.995 0.52 367.255 8.7 ; + RECT 367.505 0.52 367.765 8.7 ; + RECT 368.015 0.52 368.275 8.7 ; + RECT 368.525 0.52 368.785 8.7 ; + RECT 369.035 0.52 369.295 8.7 ; + RECT 369.545 0.52 369.805 8.7 ; + RECT 370.055 0.52 370.315 8.7 ; + RECT 372.095 0.18 372.865 0.88 ; + RECT 372.095 0.18 372.355 8.7 ; + RECT 372.605 0.18 372.865 8.7 ; + RECT 370.565 0.52 370.825 8.7 ; + RECT 371.075 0 371.335 8.7 ; + RECT 371.585 0 371.845 8.7 ; + RECT 373.115 0.52 373.375 8.7 ; + RECT 373.625 0.52 373.885 8.7 ; + RECT 374.135 0.3 374.395 8.7 ; + RECT 374.645 0.3 374.905 8.7 ; + RECT 375.155 0.3 375.415 8.7 ; + RECT 375.665 0.3 375.925 8.7 ; + RECT 376.175 0.3 376.435 8.7 ; + RECT 376.685 0.3 376.945 8.7 ; + RECT 378.725 0.18 379.495 0.88 ; + RECT 378.725 0.18 378.985 8.7 ; + RECT 379.235 0.18 379.495 8.7 ; + RECT 377.195 0.3 377.455 8.7 ; + RECT 377.705 0.3 377.965 8.7 ; + RECT 380.765 0.17 381.535 0.43 ; + RECT 380.765 0.17 381.025 8.7 ; + RECT 381.275 0.17 381.535 8.7 ; + RECT 381.785 0.18 382.555 0.88 ; + RECT 381.785 0.18 382.045 8.7 ; + RECT 382.295 0.18 382.555 8.7 ; + RECT 378.215 0.52 378.475 8.7 ; + RECT 379.745 0 380.005 8.7 ; + RECT 384.18 0.18 384.95 0.88 ; + RECT 384.18 0.18 384.44 8.7 ; + RECT 384.69 0.18 384.95 8.7 ; + RECT 385.2 0.17 385.97 0.43 ; + RECT 385.2 0.17 385.46 8.7 ; + RECT 385.71 0.17 385.97 8.7 ; + RECT 386.22 0.18 386.99 0.88 ; + RECT 386.22 0.18 386.48 8.7 ; + RECT 386.73 0.18 386.99 8.7 ; + RECT 387.24 0.17 388.01 0.43 ; + RECT 387.24 0.17 387.5 8.7 ; + RECT 387.75 0.17 388.01 8.7 ; + RECT 388.26 0.18 389.03 0.88 ; + RECT 388.26 0.18 388.52 8.7 ; + RECT 388.77 0.18 389.03 8.7 ; + RECT 389.28 0.17 390.05 0.43 ; + RECT 389.28 0.17 389.54 8.7 ; + RECT 389.79 0.17 390.05 8.7 ; + RECT 390.3 0.18 391.07 0.88 ; + RECT 390.3 0.18 390.56 8.7 ; + RECT 390.81 0.18 391.07 8.7 ; + RECT 391.32 0.17 392.09 0.43 ; + RECT 391.32 0.17 391.58 8.7 ; + RECT 391.83 0.17 392.09 8.7 ; + RECT 392.34 0.18 393.11 0.88 ; + RECT 392.34 0.18 392.6 8.7 ; + RECT 392.85 0.18 393.11 8.7 ; + RECT 393.36 0.17 394.13 0.43 ; + RECT 393.36 0.17 393.62 8.7 ; + RECT 393.87 0.17 394.13 8.7 ; + RECT 394.38 0.18 395.15 0.88 ; + RECT 394.38 0.18 394.64 8.7 ; + RECT 394.89 0.18 395.15 8.7 ; + RECT 395.4 0.17 396.17 0.43 ; + RECT 395.4 0.17 395.66 8.7 ; + RECT 395.91 0.17 396.17 8.7 ; + RECT 396.42 0.18 397.19 0.88 ; + RECT 396.42 0.18 396.68 8.7 ; + RECT 396.93 0.18 397.19 8.7 ; + RECT 397.44 0.17 398.21 0.43 ; + RECT 397.44 0.17 397.7 8.7 ; + RECT 397.95 0.17 398.21 8.7 ; + RECT 398.46 0.18 399.23 0.88 ; + RECT 398.46 0.18 398.72 8.7 ; + RECT 398.97 0.18 399.23 8.7 ; + RECT 380.255 0 380.515 8.7 ; + RECT 399.48 0.17 400.25 0.43 ; + RECT 399.48 0.17 399.74 8.7 ; + RECT 399.99 0.17 400.25 8.7 ; + RECT 382.805 0.3 383.065 8.7 ; + RECT 383.315 0.3 383.575 8.7 ; + RECT 399.47 218.93 399.67 219.74 ; + RECT 400.295 219.01 400.495 219.74 ; + RECT 400.705 219.01 401.065 219.74 ; + RECT 401.01 0.52 401.27 4.315 ; + RECT 401.275 219.01 401.475 219.74 ; + RECT 401.93 219.01 402.13 219.74 ; + RECT 402.185 0.52 402.445 2.82 ; + RECT 402.34 219.01 402.7 219.74 ; + RECT 402.995 219.01 403.195 219.74 ; + RECT 403.49 219.01 403.85 219.74 ; + RECT 404.425 0.18 405.195 0.88 ; + RECT 404.425 0.18 404.685 12.9 ; + RECT 404.935 0.18 405.195 12.9 ; + RECT 403.715 0.52 403.975 2.82 ; + RECT 404.06 219.01 404.26 219.74 ; + RECT 405.445 0.155 406.215 0.445 ; + RECT 405.445 0.155 405.705 13.21 ; + RECT 405.955 0.155 406.215 13.21 ; + RECT 404.715 219.01 404.915 219.74 ; + RECT 405.125 219.01 405.485 219.74 ; + RECT 405.695 219.01 405.895 219.74 ; + RECT 406.35 219.01 406.55 219.74 ; + RECT 406.76 219.01 407.12 219.74 ; + RECT 407.415 219.01 407.615 219.74 ; + RECT 407.91 219.01 408.27 219.74 ; + RECT 408.15 0.52 408.41 14.115 ; + RECT 408.48 219.01 408.68 219.74 ; + RECT 408.66 0.52 408.92 13.45 ; + RECT 409.135 219.01 409.335 219.74 ; + RECT 409.68 0.155 410.45 0.445 ; + RECT 409.68 0.155 409.94 8.665 ; + RECT 410.19 0.155 410.45 8.665 ; + RECT 409.17 0.52 409.43 11.315 ; + RECT 409.545 219.01 409.905 219.74 ; + RECT 410.115 219.01 410.315 219.74 ; + RECT 410.7 0.52 410.96 9.955 ; + RECT 410.77 219.01 410.97 219.74 ; + RECT 411.18 219.01 411.54 219.74 ; + RECT 411.835 219.01 412.035 219.74 ; + RECT 412.33 219.01 412.69 219.74 ; + RECT 412.74 0.3 413 8.7 ; + RECT 412.9 219.01 413.1 219.74 ; + RECT 413.555 219.01 413.755 219.74 ; + RECT 413.25 0.18 414.02 0.88 ; + RECT 413.965 219.01 414.325 219.74 ; + RECT 414.535 219.01 414.735 219.74 ; + RECT 415.19 219.01 415.39 219.74 ; + RECT 415.445 0.52 415.705 6.28 ; + RECT 415.6 219.01 415.96 219.74 ; + RECT 416.255 219.01 416.455 219.74 ; + RECT 416.82 0.52 417.08 5.57 ; + RECT 416.75 219.01 417.11 219.74 ; + RECT 417.32 219.01 417.52 219.74 ; + RECT 417.33 0.3 417.59 5.235 ; + RECT 417.84 0.52 418.1 7.78 ; + RECT 417.975 219.01 418.175 219.74 ; + RECT 418.385 219.01 418.745 219.74 ; + RECT 418.69 0.52 418.95 4.315 ; + RECT 418.955 219.01 419.155 219.74 ; + RECT 419.61 219.01 419.81 219.74 ; + RECT 419.865 0.52 420.125 2.82 ; + RECT 420.02 219.01 420.38 219.74 ; + RECT 420.675 219.01 420.875 219.74 ; + RECT 421.17 219.01 421.53 219.74 ; + RECT 422.105 0.18 422.875 0.88 ; + RECT 422.105 0.18 422.365 12.9 ; + RECT 422.615 0.18 422.875 12.9 ; + RECT 421.395 0.52 421.655 2.82 ; + RECT 421.74 219.01 421.94 219.74 ; + RECT 423.125 0.155 423.895 0.445 ; + RECT 423.125 0.155 423.385 13.21 ; + RECT 423.635 0.155 423.895 13.21 ; + RECT 422.395 219.01 422.595 219.74 ; + RECT 422.805 219.01 423.165 219.74 ; + RECT 423.375 219.01 423.575 219.74 ; + RECT 424.03 219.01 424.23 219.74 ; + RECT 424.44 219.01 424.8 219.74 ; + RECT 425.095 219.01 425.295 219.74 ; + RECT 425.59 219.01 425.95 219.74 ; + RECT 425.83 0.52 426.09 14.115 ; + RECT 426.16 219.01 426.36 219.74 ; + RECT 426.34 0.52 426.6 13.45 ; + RECT 426.815 219.01 427.015 219.74 ; + RECT 427.36 0.155 428.13 0.445 ; + RECT 427.36 0.155 427.62 8.665 ; + RECT 427.87 0.155 428.13 8.665 ; + RECT 426.85 0.52 427.11 11.315 ; + RECT 427.225 219.01 427.585 219.74 ; + RECT 427.795 219.01 427.995 219.74 ; + RECT 428.38 0.52 428.64 9.955 ; + RECT 428.45 219.01 428.65 219.74 ; + RECT 428.86 219.01 429.22 219.74 ; + RECT 429.515 219.01 429.715 219.74 ; + RECT 430.01 219.01 430.37 219.74 ; + RECT 430.42 0.3 430.68 8.7 ; + RECT 430.58 219.01 430.78 219.74 ; + RECT 431.235 219.01 431.435 219.74 ; + RECT 430.93 0.18 431.7 0.88 ; + RECT 431.645 219.01 432.005 219.74 ; + RECT 432.215 219.01 432.415 219.74 ; + RECT 432.87 219.01 433.07 219.74 ; + RECT 433.125 0.52 433.385 6.28 ; + RECT 433.28 219.01 433.64 219.74 ; + RECT 433.935 219.01 434.135 219.74 ; + RECT 434.5 0.52 434.76 5.57 ; + RECT 434.43 219.01 434.79 219.74 ; + RECT 435 219.01 435.2 219.74 ; + RECT 435.01 0.3 435.27 5.235 ; + RECT 435.52 0.52 435.78 7.78 ; + RECT 435.655 219.01 435.855 219.74 ; + RECT 436.065 219.01 436.425 219.74 ; + RECT 436.37 0.52 436.63 4.315 ; + RECT 436.635 219.01 436.835 219.74 ; + RECT 437.29 219.01 437.49 219.74 ; + RECT 437.545 0.52 437.805 2.82 ; + RECT 437.7 219.01 438.06 219.74 ; + RECT 438.355 219.01 438.555 219.74 ; + RECT 438.85 219.01 439.21 219.74 ; + RECT 439.785 0.18 440.555 0.88 ; + RECT 439.785 0.18 440.045 12.9 ; + RECT 440.295 0.18 440.555 12.9 ; + RECT 439.075 0.52 439.335 2.82 ; + RECT 439.42 219.01 439.62 219.74 ; + RECT 440.805 0.155 441.575 0.445 ; + RECT 440.805 0.155 441.065 13.21 ; + RECT 441.315 0.155 441.575 13.21 ; + RECT 440.075 219.01 440.275 219.74 ; + RECT 440.485 219.01 440.845 219.74 ; + RECT 441.055 219.01 441.255 219.74 ; + RECT 441.71 219.01 441.91 219.74 ; + RECT 442.12 219.01 442.48 219.74 ; + RECT 442.775 219.01 442.975 219.74 ; + RECT 443.27 219.01 443.63 219.74 ; + RECT 443.51 0.52 443.77 14.115 ; + RECT 443.84 219.01 444.04 219.74 ; + RECT 444.02 0.52 444.28 13.45 ; + RECT 444.495 219.01 444.695 219.74 ; + RECT 445.04 0.155 445.81 0.445 ; + RECT 445.04 0.155 445.3 8.665 ; + RECT 445.55 0.155 445.81 8.665 ; + RECT 444.53 0.52 444.79 11.315 ; + RECT 444.905 219.01 445.265 219.74 ; + RECT 445.475 219.01 445.675 219.74 ; + RECT 446.06 0.52 446.32 9.955 ; + RECT 446.13 219.01 446.33 219.74 ; + RECT 446.54 219.01 446.9 219.74 ; + RECT 447.195 219.01 447.395 219.74 ; + RECT 447.69 219.01 448.05 219.74 ; + RECT 448.1 0.3 448.36 8.7 ; + RECT 448.26 219.01 448.46 219.74 ; + RECT 448.915 219.01 449.115 219.74 ; + RECT 448.61 0.18 449.38 0.88 ; + RECT 449.325 219.01 449.685 219.74 ; + RECT 449.895 219.01 450.095 219.74 ; + RECT 450.55 219.01 450.75 219.74 ; + RECT 450.805 0.52 451.065 6.28 ; + RECT 450.96 219.01 451.32 219.74 ; + RECT 451.615 219.01 451.815 219.74 ; + RECT 452.18 0.52 452.44 5.57 ; + RECT 452.11 219.01 452.47 219.74 ; + RECT 452.68 219.01 452.88 219.74 ; + RECT 452.69 0.3 452.95 5.235 ; + RECT 453.2 0.52 453.46 7.78 ; + RECT 453.335 219.01 453.535 219.74 ; + RECT 453.745 219.01 454.105 219.74 ; + RECT 454.05 0.52 454.31 4.315 ; + RECT 454.315 219.01 454.515 219.74 ; + RECT 454.97 219.01 455.17 219.74 ; + RECT 455.225 0.52 455.485 2.82 ; + RECT 455.38 219.01 455.74 219.74 ; + RECT 456.035 219.01 456.235 219.74 ; + RECT 456.53 219.01 456.89 219.74 ; + RECT 457.465 0.18 458.235 0.88 ; + RECT 457.465 0.18 457.725 12.9 ; + RECT 457.975 0.18 458.235 12.9 ; + RECT 456.755 0.52 457.015 2.82 ; + RECT 457.1 219.01 457.3 219.74 ; + RECT 458.485 0.155 459.255 0.445 ; + RECT 458.485 0.155 458.745 13.21 ; + RECT 458.995 0.155 459.255 13.21 ; + RECT 457.755 219.01 457.955 219.74 ; + RECT 458.165 219.01 458.525 219.74 ; + RECT 458.735 219.01 458.935 219.74 ; + RECT 459.39 219.01 459.59 219.74 ; + RECT 459.8 219.01 460.16 219.74 ; + RECT 460.455 219.01 460.655 219.74 ; + RECT 460.95 219.01 461.31 219.74 ; + RECT 461.19 0.52 461.45 14.115 ; + RECT 461.52 219.01 461.72 219.74 ; + RECT 461.7 0.52 461.96 13.45 ; + RECT 462.175 219.01 462.375 219.74 ; + RECT 462.72 0.155 463.49 0.445 ; + RECT 462.72 0.155 462.98 8.665 ; + RECT 463.23 0.155 463.49 8.665 ; + RECT 462.21 0.52 462.47 11.315 ; + RECT 462.585 219.01 462.945 219.74 ; + RECT 463.155 219.01 463.355 219.74 ; + RECT 463.74 0.52 464 9.955 ; + RECT 463.81 219.01 464.01 219.74 ; + RECT 464.22 219.01 464.58 219.74 ; + RECT 464.875 219.01 465.075 219.74 ; + RECT 465.37 219.01 465.73 219.74 ; + RECT 465.78 0.3 466.04 8.7 ; + RECT 465.94 219.01 466.14 219.74 ; + RECT 466.595 219.01 466.795 219.74 ; + RECT 466.29 0.18 467.06 0.88 ; + RECT 467.005 219.01 467.365 219.74 ; + RECT 467.575 219.01 467.775 219.74 ; + RECT 468.23 219.01 468.43 219.74 ; + RECT 468.485 0.52 468.745 6.28 ; + RECT 468.64 219.01 469 219.74 ; + RECT 469.295 219.01 469.495 219.74 ; + RECT 469.86 0.52 470.12 5.57 ; + RECT 469.79 219.01 470.15 219.74 ; + RECT 470.36 219.01 470.56 219.74 ; + RECT 470.37 0.3 470.63 5.235 ; + RECT 470.88 0.52 471.14 7.78 ; + RECT 471.015 219.01 471.215 219.74 ; + RECT 471.425 219.01 471.785 219.74 ; + RECT 471.73 0.52 471.99 4.315 ; + RECT 471.995 219.01 472.195 219.74 ; + RECT 472.65 219.01 472.85 219.74 ; + RECT 472.905 0.52 473.165 2.82 ; + RECT 473.06 219.01 473.42 219.74 ; + RECT 473.715 219.01 473.915 219.74 ; + RECT 474.21 219.01 474.57 219.74 ; + RECT 475.145 0.18 475.915 0.88 ; + RECT 475.145 0.18 475.405 12.9 ; + RECT 475.655 0.18 475.915 12.9 ; + RECT 474.435 0.52 474.695 2.82 ; + RECT 474.78 219.01 474.98 219.74 ; + RECT 476.165 0.155 476.935 0.445 ; + RECT 476.165 0.155 476.425 13.21 ; + RECT 476.675 0.155 476.935 13.21 ; + RECT 475.435 219.01 475.635 219.74 ; + RECT 475.845 219.01 476.205 219.74 ; + RECT 476.415 219.01 476.615 219.74 ; + RECT 477.07 219.01 477.27 219.74 ; + RECT 477.48 219.01 477.84 219.74 ; + RECT 478.135 219.01 478.335 219.74 ; + RECT 478.63 219.01 478.99 219.74 ; + RECT 478.87 0.52 479.13 14.115 ; + RECT 479.2 219.01 479.4 219.74 ; + RECT 479.38 0.52 479.64 13.45 ; + RECT 479.855 219.01 480.055 219.74 ; + RECT 480.4 0.155 481.17 0.445 ; + RECT 480.4 0.155 480.66 8.665 ; + RECT 480.91 0.155 481.17 8.665 ; + RECT 479.89 0.52 480.15 11.315 ; + RECT 480.265 219.01 480.625 219.74 ; + RECT 480.835 219.01 481.035 219.74 ; + RECT 481.42 0.52 481.68 9.955 ; + RECT 481.49 219.01 481.69 219.74 ; + RECT 481.9 219.01 482.26 219.74 ; + RECT 482.555 219.01 482.755 219.74 ; + RECT 483.05 219.01 483.41 219.74 ; + RECT 483.46 0.3 483.72 8.7 ; + RECT 483.62 219.01 483.82 219.74 ; + RECT 484.275 219.01 484.475 219.74 ; + RECT 483.97 0.18 484.74 0.88 ; + RECT 484.685 219.01 485.045 219.74 ; + RECT 485.255 219.01 485.455 219.74 ; + RECT 485.91 219.01 486.11 219.74 ; + RECT 486.165 0.52 486.425 6.28 ; + RECT 486.32 219.01 486.68 219.74 ; + RECT 486.975 219.01 487.175 219.74 ; + RECT 487.54 0.52 487.8 5.57 ; + RECT 487.47 219.01 487.83 219.74 ; + RECT 488.04 219.01 488.24 219.74 ; + RECT 488.05 0.3 488.31 5.235 ; + RECT 488.56 0.52 488.82 7.78 ; + RECT 488.695 219.01 488.895 219.74 ; + RECT 489.105 219.01 489.465 219.74 ; + RECT 489.41 0.52 489.67 4.315 ; + RECT 489.675 219.01 489.875 219.74 ; + RECT 490.33 219.01 490.53 219.74 ; + RECT 490.585 0.52 490.845 2.82 ; + RECT 490.74 219.01 491.1 219.74 ; + RECT 491.395 219.01 491.595 219.74 ; + RECT 491.89 219.01 492.25 219.74 ; + RECT 492.825 0.18 493.595 0.88 ; + RECT 492.825 0.18 493.085 12.9 ; + RECT 493.335 0.18 493.595 12.9 ; + RECT 492.115 0.52 492.375 2.82 ; + RECT 492.46 219.01 492.66 219.74 ; + RECT 493.845 0.155 494.615 0.445 ; + RECT 493.845 0.155 494.105 13.21 ; + RECT 494.355 0.155 494.615 13.21 ; + RECT 493.115 219.01 493.315 219.74 ; + RECT 493.525 219.01 493.885 219.74 ; + RECT 494.095 219.01 494.295 219.74 ; + RECT 494.75 219.01 494.95 219.74 ; + RECT 495.16 219.01 495.52 219.74 ; + RECT 495.815 219.01 496.015 219.74 ; + RECT 496.31 219.01 496.67 219.74 ; + RECT 496.55 0.52 496.81 14.115 ; + RECT 496.88 219.01 497.08 219.74 ; + RECT 497.06 0.52 497.32 13.45 ; + RECT 497.535 219.01 497.735 219.74 ; + RECT 498.08 0.155 498.85 0.445 ; + RECT 498.08 0.155 498.34 8.665 ; + RECT 498.59 0.155 498.85 8.665 ; + RECT 497.57 0.52 497.83 11.315 ; + RECT 497.945 219.01 498.305 219.74 ; + RECT 498.515 219.01 498.715 219.74 ; + RECT 499.1 0.52 499.36 9.955 ; + RECT 499.17 219.01 499.37 219.74 ; + RECT 499.58 219.01 499.94 219.74 ; + RECT 500.235 219.01 500.435 219.74 ; + RECT 500.73 219.01 501.09 219.74 ; + RECT 501.14 0.3 501.4 8.7 ; + RECT 501.3 219.01 501.5 219.74 ; + RECT 501.955 219.01 502.155 219.74 ; + RECT 501.65 0.18 502.42 0.88 ; + RECT 502.365 219.01 502.725 219.74 ; + RECT 502.935 219.01 503.135 219.74 ; + RECT 503.59 219.01 503.79 219.74 ; + RECT 503.845 0.52 504.105 6.28 ; + RECT 504 219.01 504.36 219.74 ; + RECT 504.655 219.01 504.855 219.74 ; + RECT 505.22 0.52 505.48 5.57 ; + RECT 505.15 219.01 505.51 219.74 ; + RECT 505.72 219.01 505.92 219.74 ; + RECT 505.73 0.3 505.99 5.235 ; + RECT 506.24 0.52 506.5 7.78 ; + RECT 506.375 219.01 506.575 219.74 ; + RECT 506.785 219.01 507.145 219.74 ; + RECT 507.09 0.52 507.35 4.315 ; + RECT 507.355 219.01 507.555 219.74 ; + RECT 508.01 219.01 508.21 219.74 ; + RECT 508.265 0.52 508.525 2.82 ; + RECT 508.42 219.01 508.78 219.74 ; + RECT 509.075 219.01 509.275 219.74 ; + RECT 509.57 219.01 509.93 219.74 ; + RECT 510.505 0.18 511.275 0.88 ; + RECT 510.505 0.18 510.765 12.9 ; + RECT 511.015 0.18 511.275 12.9 ; + RECT 509.795 0.52 510.055 2.82 ; + RECT 510.14 219.01 510.34 219.74 ; + RECT 511.525 0.155 512.295 0.445 ; + RECT 511.525 0.155 511.785 13.21 ; + RECT 512.035 0.155 512.295 13.21 ; + RECT 510.795 219.01 510.995 219.74 ; + RECT 511.205 219.01 511.565 219.74 ; + RECT 511.775 219.01 511.975 219.74 ; + RECT 512.43 219.01 512.63 219.74 ; + RECT 512.84 219.01 513.2 219.74 ; + RECT 513.495 219.01 513.695 219.74 ; + RECT 513.99 219.01 514.35 219.74 ; + RECT 514.23 0.52 514.49 14.115 ; + RECT 514.56 219.01 514.76 219.74 ; + RECT 514.74 0.52 515 13.45 ; + RECT 515.215 219.01 515.415 219.74 ; + RECT 515.76 0.155 516.53 0.445 ; + RECT 515.76 0.155 516.02 8.665 ; + RECT 516.27 0.155 516.53 8.665 ; + RECT 515.25 0.52 515.51 11.315 ; + RECT 515.625 219.01 515.985 219.74 ; + RECT 516.195 219.01 516.395 219.74 ; + RECT 516.78 0.52 517.04 9.955 ; + RECT 516.85 219.01 517.05 219.74 ; + RECT 517.26 219.01 517.62 219.74 ; + RECT 517.915 219.01 518.115 219.74 ; + RECT 518.41 219.01 518.77 219.74 ; + RECT 518.82 0.3 519.08 8.7 ; + RECT 518.98 219.01 519.18 219.74 ; + RECT 519.635 219.01 519.835 219.74 ; + RECT 519.33 0.18 520.1 0.88 ; + RECT 520.045 219.01 520.405 219.74 ; + RECT 520.615 219.01 520.815 219.74 ; + RECT 521.27 219.01 521.47 219.74 ; + RECT 521.525 0.52 521.785 6.28 ; + RECT 521.68 219.01 522.04 219.74 ; + RECT 522.335 219.01 522.535 219.74 ; + RECT 522.9 0.52 523.16 5.57 ; + RECT 522.83 219.01 523.19 219.74 ; + RECT 523.4 219.01 523.6 219.74 ; + RECT 523.41 0.3 523.67 5.235 ; + RECT 523.92 0.52 524.18 7.78 ; + RECT 524.055 219.01 524.255 219.74 ; + RECT 524.465 219.01 524.825 219.74 ; + RECT 524.77 0.52 525.03 4.315 ; + RECT 525.035 219.01 525.235 219.74 ; + RECT 525.69 219.01 525.89 219.74 ; + RECT 525.945 0.52 526.205 2.82 ; + RECT 526.1 219.01 526.46 219.74 ; + RECT 526.755 219.01 526.955 219.74 ; + RECT 527.25 219.01 527.61 219.74 ; + RECT 528.185 0.18 528.955 0.88 ; + RECT 528.185 0.18 528.445 12.9 ; + RECT 528.695 0.18 528.955 12.9 ; + RECT 527.475 0.52 527.735 2.82 ; + RECT 527.82 219.01 528.02 219.74 ; + RECT 529.205 0.155 529.975 0.445 ; + RECT 529.205 0.155 529.465 13.21 ; + RECT 529.715 0.155 529.975 13.21 ; + RECT 528.475 219.01 528.675 219.74 ; + RECT 528.885 219.01 529.245 219.74 ; + RECT 529.455 219.01 529.655 219.74 ; + RECT 530.11 219.01 530.31 219.74 ; + RECT 530.52 219.01 530.88 219.74 ; + RECT 531.175 219.01 531.375 219.74 ; + RECT 531.67 219.01 532.03 219.74 ; + RECT 531.91 0.52 532.17 14.115 ; + RECT 532.24 219.01 532.44 219.74 ; + RECT 532.42 0.52 532.68 13.45 ; + RECT 532.895 219.01 533.095 219.74 ; + RECT 533.44 0.155 534.21 0.445 ; + RECT 533.44 0.155 533.7 8.665 ; + RECT 533.95 0.155 534.21 8.665 ; + RECT 532.93 0.52 533.19 11.315 ; + RECT 533.305 219.01 533.665 219.74 ; + RECT 533.875 219.01 534.075 219.74 ; + RECT 534.46 0.52 534.72 9.955 ; + RECT 534.53 219.01 534.73 219.74 ; + RECT 534.94 219.01 535.3 219.74 ; + RECT 535.595 219.01 535.795 219.74 ; + RECT 536.09 219.01 536.45 219.74 ; + RECT 536.5 0.3 536.76 8.7 ; + RECT 536.66 219.01 536.86 219.74 ; + RECT 537.315 219.01 537.515 219.74 ; + RECT 537.01 0.18 537.78 0.88 ; + RECT 537.725 219.01 538.085 219.74 ; + RECT 538.295 219.01 538.495 219.74 ; + RECT 538.95 219.01 539.15 219.74 ; + RECT 539.205 0.52 539.465 6.28 ; + RECT 539.36 219.01 539.72 219.74 ; + RECT 540.015 219.01 540.215 219.74 ; + RECT 540.58 0.52 540.84 5.57 ; + RECT 540.51 219.01 540.87 219.74 ; + RECT 541.08 219.01 541.28 219.74 ; + RECT 541.09 0.3 541.35 5.235 ; + RECT 541.6 0.52 541.86 7.78 ; + RECT 541.735 219.01 541.935 219.74 ; + RECT 542.145 219.01 542.505 219.74 ; + RECT 542.45 0.52 542.71 4.315 ; + RECT 542.715 219.01 542.915 219.74 ; + RECT 543.37 219.01 543.57 219.74 ; + RECT 543.625 0.52 543.885 2.82 ; + RECT 543.78 219.01 544.14 219.74 ; + RECT 544.435 219.01 544.635 219.74 ; + RECT 544.93 219.01 545.29 219.74 ; + RECT 545.865 0.18 546.635 0.88 ; + RECT 545.865 0.18 546.125 12.9 ; + RECT 546.375 0.18 546.635 12.9 ; + RECT 545.155 0.52 545.415 2.82 ; + RECT 545.5 219.01 545.7 219.74 ; + RECT 546.885 0.155 547.655 0.445 ; + RECT 546.885 0.155 547.145 13.21 ; + RECT 547.395 0.155 547.655 13.21 ; + RECT 546.155 219.01 546.355 219.74 ; + RECT 546.565 219.01 546.925 219.74 ; + RECT 547.135 219.01 547.335 219.74 ; + RECT 547.79 219.01 547.99 219.74 ; + RECT 548.2 219.01 548.56 219.74 ; + RECT 548.855 219.01 549.055 219.74 ; + RECT 549.35 219.01 549.71 219.74 ; + RECT 549.59 0.52 549.85 14.115 ; + RECT 549.92 219.01 550.12 219.74 ; + RECT 550.1 0.52 550.36 13.45 ; + RECT 550.575 219.01 550.775 219.74 ; + RECT 551.12 0.155 551.89 0.445 ; + RECT 551.12 0.155 551.38 8.665 ; + RECT 551.63 0.155 551.89 8.665 ; + RECT 550.61 0.52 550.87 11.315 ; + RECT 550.985 219.01 551.345 219.74 ; + RECT 551.555 219.01 551.755 219.74 ; + RECT 552.14 0.52 552.4 9.955 ; + RECT 552.21 219.01 552.41 219.74 ; + RECT 552.62 219.01 552.98 219.74 ; + RECT 553.275 219.01 553.475 219.74 ; + RECT 553.77 219.01 554.13 219.74 ; + RECT 554.18 0.3 554.44 8.7 ; + RECT 554.34 219.01 554.54 219.74 ; + RECT 554.995 219.01 555.195 219.74 ; + RECT 554.69 0.18 555.46 0.88 ; + RECT 555.405 219.01 555.765 219.74 ; + RECT 555.975 219.01 556.175 219.74 ; + RECT 556.63 219.01 556.83 219.74 ; + RECT 556.885 0.52 557.145 6.28 ; + RECT 557.04 219.01 557.4 219.74 ; + RECT 557.695 219.01 557.895 219.74 ; + RECT 558.26 0.52 558.52 5.57 ; + RECT 558.19 219.01 558.55 219.74 ; + RECT 558.76 219.01 558.96 219.74 ; + RECT 558.77 0.3 559.03 5.235 ; + RECT 559.28 0.52 559.54 7.78 ; + RECT 559.415 219.01 559.615 219.74 ; + RECT 559.825 219.01 560.185 219.74 ; + RECT 560.13 0.52 560.39 4.315 ; + RECT 560.395 219.01 560.595 219.74 ; + RECT 561.05 219.01 561.25 219.74 ; + RECT 561.305 0.52 561.565 2.82 ; + RECT 561.46 219.01 561.82 219.74 ; + RECT 562.115 219.01 562.315 219.74 ; + RECT 562.61 219.01 562.97 219.74 ; + RECT 563.545 0.18 564.315 0.88 ; + RECT 563.545 0.18 563.805 12.9 ; + RECT 564.055 0.18 564.315 12.9 ; + RECT 562.835 0.52 563.095 2.82 ; + RECT 563.18 219.01 563.38 219.74 ; + RECT 564.565 0.155 565.335 0.445 ; + RECT 564.565 0.155 564.825 13.21 ; + RECT 565.075 0.155 565.335 13.21 ; + RECT 563.835 219.01 564.035 219.74 ; + RECT 564.245 219.01 564.605 219.74 ; + RECT 564.815 219.01 565.015 219.74 ; + RECT 565.47 219.01 565.67 219.74 ; + RECT 565.88 219.01 566.24 219.74 ; + RECT 566.535 219.01 566.735 219.74 ; + RECT 567.03 219.01 567.39 219.74 ; + RECT 567.27 0.52 567.53 14.115 ; + RECT 567.6 219.01 567.8 219.74 ; + RECT 567.78 0.52 568.04 13.45 ; + RECT 568.255 219.01 568.455 219.74 ; + RECT 568.8 0.155 569.57 0.445 ; + RECT 568.8 0.155 569.06 8.665 ; + RECT 569.31 0.155 569.57 8.665 ; + RECT 568.29 0.52 568.55 11.315 ; + RECT 568.665 219.01 569.025 219.74 ; + RECT 569.235 219.01 569.435 219.74 ; + RECT 569.82 0.52 570.08 9.955 ; + RECT 569.89 219.01 570.09 219.74 ; + RECT 570.3 219.01 570.66 219.74 ; + RECT 570.955 219.01 571.155 219.74 ; + RECT 571.45 219.01 571.81 219.74 ; + RECT 571.86 0.3 572.12 8.7 ; + RECT 572.02 219.01 572.22 219.74 ; + RECT 572.675 219.01 572.875 219.74 ; + RECT 572.37 0.18 573.14 0.88 ; + RECT 573.085 219.01 573.445 219.74 ; + RECT 573.655 219.01 573.855 219.74 ; + RECT 574.31 219.01 574.51 219.74 ; + RECT 574.565 0.52 574.825 6.28 ; + RECT 574.72 219.01 575.08 219.74 ; + RECT 575.375 219.01 575.575 219.74 ; + RECT 575.94 0.52 576.2 5.57 ; + RECT 575.87 219.01 576.23 219.74 ; + RECT 576.44 219.01 576.64 219.74 ; + RECT 576.45 0.3 576.71 5.235 ; + RECT 576.96 0.52 577.22 7.78 ; + RECT 577.095 219.01 577.295 219.74 ; + RECT 577.505 219.01 577.865 219.74 ; + RECT 577.81 0.52 578.07 4.315 ; + RECT 578.075 219.01 578.275 219.74 ; + RECT 578.73 219.01 578.93 219.74 ; + RECT 578.985 0.52 579.245 2.82 ; + RECT 579.14 219.01 579.5 219.74 ; + RECT 579.795 219.01 579.995 219.74 ; + RECT 580.29 219.01 580.65 219.74 ; + RECT 581.225 0.18 581.995 0.88 ; + RECT 581.225 0.18 581.485 12.9 ; + RECT 581.735 0.18 581.995 12.9 ; + RECT 580.515 0.52 580.775 2.82 ; + RECT 580.86 219.01 581.06 219.74 ; + RECT 582.245 0.155 583.015 0.445 ; + RECT 582.245 0.155 582.505 13.21 ; + RECT 582.755 0.155 583.015 13.21 ; + RECT 581.515 219.01 581.715 219.74 ; + RECT 581.925 219.01 582.285 219.74 ; + RECT 582.495 219.01 582.695 219.74 ; + RECT 583.15 219.01 583.35 219.74 ; + RECT 583.56 219.01 583.92 219.74 ; + RECT 584.215 219.01 584.415 219.74 ; + RECT 584.71 219.01 585.07 219.74 ; + RECT 584.95 0.52 585.21 14.115 ; + RECT 585.28 219.01 585.48 219.74 ; + RECT 585.46 0.52 585.72 13.45 ; + RECT 585.935 219.01 586.135 219.74 ; + RECT 586.48 0.155 587.25 0.445 ; + RECT 586.48 0.155 586.74 8.665 ; + RECT 586.99 0.155 587.25 8.665 ; + RECT 585.97 0.52 586.23 11.315 ; + RECT 586.345 219.01 586.705 219.74 ; + RECT 586.915 219.01 587.115 219.74 ; + RECT 587.5 0.52 587.76 9.955 ; + RECT 587.57 219.01 587.77 219.74 ; + RECT 587.98 219.01 588.34 219.74 ; + RECT 588.635 219.01 588.835 219.74 ; + RECT 589.13 219.01 589.49 219.74 ; + RECT 589.54 0.3 589.8 8.7 ; + RECT 589.7 219.01 589.9 219.74 ; + RECT 590.355 219.01 590.555 219.74 ; + RECT 590.05 0.18 590.82 0.88 ; + RECT 590.765 219.01 591.125 219.74 ; + RECT 591.335 219.01 591.535 219.74 ; + RECT 591.99 219.01 592.19 219.74 ; + RECT 592.245 0.52 592.505 6.28 ; + RECT 592.4 219.01 592.76 219.74 ; + RECT 593.055 219.01 593.255 219.74 ; + RECT 593.62 0.52 593.88 5.57 ; + RECT 593.55 219.01 593.91 219.74 ; + RECT 594.12 219.01 594.32 219.74 ; + RECT 594.13 0.3 594.39 5.235 ; + RECT 594.64 0.52 594.9 7.78 ; + RECT 594.775 219.01 594.975 219.74 ; + RECT 595.185 219.01 595.545 219.74 ; + RECT 595.49 0.52 595.75 4.315 ; + RECT 595.755 219.01 595.955 219.74 ; + RECT 596.41 219.01 596.61 219.74 ; + RECT 596.665 0.52 596.925 2.82 ; + RECT 596.82 219.01 597.18 219.74 ; + RECT 597.475 219.01 597.675 219.74 ; + RECT 597.97 219.01 598.33 219.74 ; + RECT 598.905 0.18 599.675 0.88 ; + RECT 598.905 0.18 599.165 12.9 ; + RECT 599.415 0.18 599.675 12.9 ; + RECT 598.195 0.52 598.455 2.82 ; + RECT 598.54 219.01 598.74 219.74 ; + RECT 599.925 0.155 600.695 0.445 ; + RECT 599.925 0.155 600.185 13.21 ; + RECT 600.435 0.155 600.695 13.21 ; + RECT 599.195 219.01 599.395 219.74 ; + RECT 599.605 219.01 599.965 219.74 ; + RECT 600.175 219.01 600.375 219.74 ; + RECT 600.83 219.01 601.03 219.74 ; + RECT 601.24 219.01 601.6 219.74 ; + RECT 601.895 219.01 602.095 219.74 ; + RECT 602.39 219.01 602.75 219.74 ; + RECT 602.63 0.52 602.89 14.115 ; + RECT 602.96 219.01 603.16 219.74 ; + RECT 603.14 0.52 603.4 13.45 ; + RECT 603.615 219.01 603.815 219.74 ; + RECT 604.16 0.155 604.93 0.445 ; + RECT 604.16 0.155 604.42 8.665 ; + RECT 604.67 0.155 604.93 8.665 ; + RECT 603.65 0.52 603.91 11.315 ; + RECT 604.025 219.01 604.385 219.74 ; + RECT 604.595 219.01 604.795 219.74 ; + RECT 605.18 0.52 605.44 9.955 ; + RECT 605.25 219.01 605.45 219.74 ; + RECT 605.66 219.01 606.02 219.74 ; + RECT 606.315 219.01 606.515 219.74 ; + RECT 606.81 219.01 607.17 219.74 ; + RECT 607.22 0.3 607.48 8.7 ; + RECT 607.38 219.01 607.58 219.74 ; + RECT 608.035 219.01 608.235 219.74 ; + RECT 607.73 0.18 608.5 0.88 ; + RECT 608.445 219.01 608.805 219.74 ; + RECT 609.015 219.01 609.215 219.74 ; + RECT 609.67 219.01 609.87 219.74 ; + RECT 609.925 0.52 610.185 6.28 ; + RECT 610.08 219.01 610.44 219.74 ; + RECT 610.735 219.01 610.935 219.74 ; + RECT 611.3 0.52 611.56 5.57 ; + RECT 611.23 219.01 611.59 219.74 ; + RECT 611.8 219.01 612 219.74 ; + RECT 611.81 0.3 612.07 5.235 ; + RECT 612.32 0.52 612.58 7.78 ; + RECT 612.455 219.01 612.655 219.74 ; + RECT 612.865 219.01 613.225 219.74 ; + RECT 613.17 0.52 613.43 4.315 ; + RECT 613.435 219.01 613.635 219.74 ; + RECT 614.09 219.01 614.29 219.74 ; + RECT 614.345 0.52 614.605 2.82 ; + RECT 614.5 219.01 614.86 219.74 ; + RECT 615.155 219.01 615.355 219.74 ; + RECT 615.65 219.01 616.01 219.74 ; + RECT 616.585 0.18 617.355 0.88 ; + RECT 616.585 0.18 616.845 12.9 ; + RECT 617.095 0.18 617.355 12.9 ; + RECT 615.875 0.52 616.135 2.82 ; + RECT 616.22 219.01 616.42 219.74 ; + RECT 617.605 0.155 618.375 0.445 ; + RECT 617.605 0.155 617.865 13.21 ; + RECT 618.115 0.155 618.375 13.21 ; + RECT 616.875 219.01 617.075 219.74 ; + RECT 617.285 219.01 617.645 219.74 ; + RECT 617.855 219.01 618.055 219.74 ; + RECT 618.51 219.01 618.71 219.74 ; + RECT 618.92 219.01 619.28 219.74 ; + RECT 619.575 219.01 619.775 219.74 ; + RECT 620.07 219.01 620.43 219.74 ; + RECT 620.31 0.52 620.57 14.115 ; + RECT 620.64 219.01 620.84 219.74 ; + RECT 620.82 0.52 621.08 13.45 ; + RECT 621.295 219.01 621.495 219.74 ; + RECT 621.84 0.155 622.61 0.445 ; + RECT 621.84 0.155 622.1 8.665 ; + RECT 622.35 0.155 622.61 8.665 ; + RECT 621.33 0.52 621.59 11.315 ; + RECT 621.705 219.01 622.065 219.74 ; + RECT 622.275 219.01 622.475 219.74 ; + RECT 622.86 0.52 623.12 9.955 ; + RECT 622.93 219.01 623.13 219.74 ; + RECT 623.34 219.01 623.7 219.74 ; + RECT 623.995 219.01 624.195 219.74 ; + RECT 624.49 219.01 624.85 219.74 ; + RECT 624.9 0.3 625.16 8.7 ; + RECT 625.06 219.01 625.26 219.74 ; + RECT 625.715 219.01 625.915 219.74 ; + RECT 625.41 0.18 626.18 0.88 ; + RECT 626.125 219.01 626.485 219.74 ; + RECT 626.695 219.01 626.895 219.74 ; + RECT 627.35 219.01 627.55 219.74 ; + RECT 627.605 0.52 627.865 6.28 ; + RECT 627.76 219.01 628.12 219.74 ; + RECT 628.415 219.01 628.615 219.74 ; + RECT 628.98 0.52 629.24 5.57 ; + RECT 628.91 219.01 629.27 219.74 ; + RECT 629.48 219.01 629.68 219.74 ; + RECT 629.49 0.3 629.75 5.235 ; + RECT 630 0.52 630.26 7.78 ; + RECT 630.135 219.01 630.335 219.74 ; + RECT 630.545 219.01 630.905 219.74 ; + RECT 630.85 0.52 631.11 4.315 ; + RECT 631.115 219.01 631.315 219.74 ; + RECT 631.77 219.01 631.97 219.74 ; + RECT 632.025 0.52 632.285 2.82 ; + RECT 632.18 219.01 632.54 219.74 ; + RECT 632.835 219.01 633.035 219.74 ; + RECT 633.33 219.01 633.69 219.74 ; + RECT 634.265 0.18 635.035 0.88 ; + RECT 634.265 0.18 634.525 12.9 ; + RECT 634.775 0.18 635.035 12.9 ; + RECT 633.555 0.52 633.815 2.82 ; + RECT 633.9 219.01 634.1 219.74 ; + RECT 635.285 0.155 636.055 0.445 ; + RECT 635.285 0.155 635.545 13.21 ; + RECT 635.795 0.155 636.055 13.21 ; + RECT 634.555 219.01 634.755 219.74 ; + RECT 634.965 219.01 635.325 219.74 ; + RECT 635.535 219.01 635.735 219.74 ; + RECT 636.19 219.01 636.39 219.74 ; + RECT 636.6 219.01 636.96 219.74 ; + RECT 637.255 219.01 637.455 219.74 ; + RECT 637.75 219.01 638.11 219.74 ; + RECT 637.99 0.52 638.25 14.115 ; + RECT 638.32 219.01 638.52 219.74 ; + RECT 638.5 0.52 638.76 13.45 ; + RECT 638.975 219.01 639.175 219.74 ; + RECT 639.52 0.155 640.29 0.445 ; + RECT 639.52 0.155 639.78 8.665 ; + RECT 640.03 0.155 640.29 8.665 ; + RECT 639.01 0.52 639.27 11.315 ; + RECT 639.385 219.01 639.745 219.74 ; + RECT 639.955 219.01 640.155 219.74 ; + RECT 640.54 0.52 640.8 9.955 ; + RECT 640.61 219.01 640.81 219.74 ; + RECT 641.02 219.01 641.38 219.74 ; + RECT 641.675 219.01 641.875 219.74 ; + RECT 642.17 219.01 642.53 219.74 ; + RECT 642.58 0.3 642.84 8.7 ; + RECT 642.74 219.01 642.94 219.74 ; + RECT 643.395 219.01 643.595 219.74 ; + RECT 643.09 0.18 643.86 0.88 ; + RECT 643.805 219.01 644.165 219.74 ; + RECT 644.375 219.01 644.575 219.74 ; + RECT 645.03 219.01 645.23 219.74 ; + RECT 645.285 0.52 645.545 6.28 ; + RECT 645.44 219.01 645.8 219.74 ; + RECT 646.095 219.01 646.295 219.74 ; + RECT 646.66 0.52 646.92 5.57 ; + RECT 646.59 219.01 646.95 219.74 ; + RECT 647.16 219.01 647.36 219.74 ; + RECT 647.17 0.3 647.43 5.235 ; + RECT 647.68 0.52 647.94 7.78 ; + RECT 647.815 219.01 648.015 219.74 ; + RECT 648.225 219.01 648.585 219.74 ; + RECT 648.53 0.52 648.79 4.315 ; + RECT 648.795 219.01 648.995 219.74 ; + RECT 649.45 219.01 649.65 219.74 ; + RECT 649.705 0.52 649.965 2.82 ; + RECT 649.86 219.01 650.22 219.74 ; + RECT 650.515 219.01 650.715 219.74 ; + RECT 651.01 219.01 651.37 219.74 ; + RECT 651.945 0.18 652.715 0.88 ; + RECT 651.945 0.18 652.205 12.9 ; + RECT 652.455 0.18 652.715 12.9 ; + RECT 651.235 0.52 651.495 2.82 ; + RECT 651.58 219.01 651.78 219.74 ; + RECT 652.965 0.155 653.735 0.445 ; + RECT 652.965 0.155 653.225 13.21 ; + RECT 653.475 0.155 653.735 13.21 ; + RECT 652.235 219.01 652.435 219.74 ; + RECT 652.645 219.01 653.005 219.74 ; + RECT 653.215 219.01 653.415 219.74 ; + RECT 653.87 219.01 654.07 219.74 ; + RECT 654.28 219.01 654.64 219.74 ; + RECT 654.935 219.01 655.135 219.74 ; + RECT 655.43 219.01 655.79 219.74 ; + RECT 655.67 0.52 655.93 14.115 ; + RECT 656 219.01 656.2 219.74 ; + RECT 656.18 0.52 656.44 13.45 ; + RECT 656.655 219.01 656.855 219.74 ; + RECT 657.2 0.155 657.97 0.445 ; + RECT 657.2 0.155 657.46 8.665 ; + RECT 657.71 0.155 657.97 8.665 ; + RECT 656.69 0.52 656.95 11.315 ; + RECT 657.065 219.01 657.425 219.74 ; + RECT 657.635 219.01 657.835 219.74 ; + RECT 658.22 0.52 658.48 9.955 ; + RECT 658.29 219.01 658.49 219.74 ; + RECT 658.7 219.01 659.06 219.74 ; + RECT 659.355 219.01 659.555 219.74 ; + RECT 659.85 219.01 660.21 219.74 ; + RECT 660.26 0.3 660.52 8.7 ; + RECT 660.42 219.01 660.62 219.74 ; + RECT 661.075 219.01 661.275 219.74 ; + RECT 660.77 0.18 661.54 0.88 ; + RECT 661.485 219.01 661.845 219.74 ; + RECT 662.055 219.01 662.255 219.74 ; + RECT 662.71 219.01 662.91 219.74 ; + RECT 662.965 0.52 663.225 6.28 ; + RECT 663.12 219.01 663.48 219.74 ; + RECT 663.775 219.01 663.975 219.74 ; + RECT 664.34 0.52 664.6 5.57 ; + RECT 664.27 219.01 664.63 219.74 ; + RECT 664.84 219.01 665.04 219.74 ; + RECT 664.85 0.3 665.11 5.235 ; + RECT 665.36 0.52 665.62 7.78 ; + RECT 665.495 219.01 665.695 219.74 ; + RECT 665.905 219.01 666.265 219.74 ; + RECT 666.21 0.52 666.47 4.315 ; + RECT 666.475 219.01 666.675 219.74 ; + RECT 667.13 219.01 667.33 219.74 ; + RECT 667.385 0.52 667.645 2.82 ; + RECT 667.54 219.01 667.9 219.74 ; + RECT 668.195 219.01 668.395 219.74 ; + RECT 668.69 219.01 669.05 219.74 ; + RECT 669.625 0.18 670.395 0.88 ; + RECT 669.625 0.18 669.885 12.9 ; + RECT 670.135 0.18 670.395 12.9 ; + RECT 668.915 0.52 669.175 2.82 ; + RECT 669.26 219.01 669.46 219.74 ; + RECT 670.645 0.155 671.415 0.445 ; + RECT 670.645 0.155 670.905 13.21 ; + RECT 671.155 0.155 671.415 13.21 ; + RECT 669.915 219.01 670.115 219.74 ; + RECT 670.325 219.01 670.685 219.74 ; + RECT 670.895 219.01 671.095 219.74 ; + RECT 671.55 219.01 671.75 219.74 ; + RECT 671.96 219.01 672.32 219.74 ; + RECT 672.615 219.01 672.815 219.74 ; + RECT 673.11 219.01 673.47 219.74 ; + RECT 673.35 0.52 673.61 14.115 ; + RECT 673.68 219.01 673.88 219.74 ; + RECT 673.86 0.52 674.12 13.45 ; + RECT 674.335 219.01 674.535 219.74 ; + RECT 674.88 0.155 675.65 0.445 ; + RECT 674.88 0.155 675.14 8.665 ; + RECT 675.39 0.155 675.65 8.665 ; + RECT 674.37 0.52 674.63 11.315 ; + RECT 674.745 219.01 675.105 219.74 ; + RECT 675.315 219.01 675.515 219.74 ; + RECT 675.9 0.52 676.16 9.955 ; + RECT 675.97 219.01 676.17 219.74 ; + RECT 676.38 219.01 676.74 219.74 ; + RECT 677.035 219.01 677.235 219.74 ; + RECT 677.53 219.01 677.89 219.74 ; + RECT 677.94 0.3 678.2 8.7 ; + RECT 678.1 219.01 678.3 219.74 ; + RECT 678.755 219.01 678.955 219.74 ; + RECT 678.45 0.18 679.22 0.88 ; + RECT 679.165 219.01 679.525 219.74 ; + RECT 679.735 219.01 679.935 219.74 ; + RECT 680.39 219.01 680.59 219.74 ; + RECT 680.645 0.52 680.905 6.28 ; + RECT 680.8 219.01 681.16 219.74 ; + RECT 681.455 219.01 681.655 219.74 ; + RECT 682.02 0.52 682.28 5.57 ; + RECT 681.95 219.01 682.31 219.74 ; + RECT 682.52 219.01 682.72 219.74 ; + RECT 682.53 0.3 682.79 5.235 ; + RECT 683.04 0.52 683.3 7.78 ; + RECT 683.175 219.01 683.375 219.74 ; + RECT 683.585 219.01 683.945 219.74 ; + RECT 684.155 219.01 684.355 219.74 ; + RECT 684.98 53.41 685.18 219.74 ; + LAYER Metal2 SPACING 0.21 ; + RECT 683.56 0 685.49 219.77 ; + RECT 0 0.52 685.49 219.77 ; + RECT 682.53 0.3 682.79 219.77 ; + RECT 681.165 0 681.76 219.77 ; + RECT 676.42 0 680.385 219.77 ; + RECT 674.88 0.155 675.65 219.77 ; + RECT 669.435 0 673.09 219.77 ; + RECT 667.905 0 668.655 219.77 ; + RECT 666.73 0 667.125 219.77 ; + RECT 664.85 0.3 665.11 219.77 ; + RECT 663.485 0 664.08 219.77 ; + RECT 658.74 0 662.705 219.77 ; + RECT 657.2 0.155 657.97 219.77 ; + RECT 651.755 0 655.41 219.77 ; + RECT 650.225 0 650.975 219.77 ; + RECT 649.05 0 649.445 219.77 ; + RECT 647.17 0.3 647.43 219.77 ; + RECT 645.805 0 646.4 219.77 ; + RECT 641.06 0 645.025 219.77 ; + RECT 639.52 0.155 640.29 219.77 ; + RECT 634.075 0 637.73 219.77 ; + RECT 632.545 0 633.295 219.77 ; + RECT 631.37 0 631.765 219.77 ; + RECT 629.49 0.3 629.75 219.77 ; + RECT 628.125 0 628.72 219.77 ; + RECT 623.38 0 627.345 219.77 ; + RECT 621.84 0.155 622.61 219.77 ; + RECT 616.395 0 620.05 219.77 ; + RECT 614.865 0 615.615 219.77 ; + RECT 613.69 0 614.085 219.77 ; + RECT 611.81 0.3 612.07 219.77 ; + RECT 610.445 0 611.04 219.77 ; + RECT 605.7 0 609.665 219.77 ; + RECT 604.16 0.155 604.93 219.77 ; + RECT 598.715 0 602.37 219.77 ; + RECT 597.185 0 597.935 219.77 ; + RECT 596.01 0 596.405 219.77 ; + RECT 594.13 0.3 594.39 219.77 ; + RECT 592.765 0 593.36 219.77 ; + RECT 588.02 0 591.985 219.77 ; + RECT 586.48 0.155 587.25 219.77 ; + RECT 581.035 0 584.69 219.77 ; + RECT 579.505 0 580.255 219.77 ; + RECT 578.33 0 578.725 219.77 ; + RECT 576.45 0.3 576.71 219.77 ; + RECT 575.085 0 575.68 219.77 ; + RECT 570.34 0 574.305 219.77 ; + RECT 568.8 0.155 569.57 219.77 ; + RECT 563.355 0 567.01 219.77 ; + RECT 561.825 0 562.575 219.77 ; + RECT 560.65 0 561.045 219.77 ; + RECT 558.77 0.3 559.03 219.77 ; + RECT 557.405 0 558 219.77 ; + RECT 552.66 0 556.625 219.77 ; + RECT 551.12 0.155 551.89 219.77 ; + RECT 545.675 0 549.33 219.77 ; + RECT 544.145 0 544.895 219.77 ; + RECT 542.97 0 543.365 219.77 ; + RECT 541.09 0.3 541.35 219.77 ; + RECT 539.725 0 540.32 219.77 ; + RECT 534.98 0 538.945 219.77 ; + RECT 533.44 0.155 534.21 219.77 ; + RECT 527.995 0 531.65 219.77 ; + RECT 526.465 0 527.215 219.77 ; + RECT 525.29 0 525.685 219.77 ; + RECT 523.41 0.3 523.67 219.77 ; + RECT 522.045 0 522.64 219.77 ; + RECT 517.3 0 521.265 219.77 ; + RECT 515.76 0.155 516.53 219.77 ; + RECT 510.315 0 513.97 219.77 ; + RECT 508.785 0 509.535 219.77 ; + RECT 507.61 0 508.005 219.77 ; + RECT 505.73 0.3 505.99 219.77 ; + RECT 504.365 0 504.96 219.77 ; + RECT 499.62 0 503.585 219.77 ; + RECT 498.08 0.155 498.85 219.77 ; + RECT 492.635 0 496.29 219.77 ; + RECT 491.105 0 491.855 219.77 ; + RECT 489.93 0 490.325 219.77 ; + RECT 488.05 0.3 488.31 219.77 ; + RECT 486.685 0 487.28 219.77 ; + RECT 481.94 0 485.905 219.77 ; + RECT 480.4 0.155 481.17 219.77 ; + RECT 474.955 0 478.61 219.77 ; + RECT 473.425 0 474.175 219.77 ; + RECT 472.25 0 472.645 219.77 ; + RECT 470.37 0.3 470.63 219.77 ; + RECT 469.005 0 469.6 219.77 ; + RECT 464.26 0 468.225 219.77 ; + RECT 462.72 0.155 463.49 219.77 ; + RECT 457.275 0 460.93 219.77 ; + RECT 455.745 0 456.495 219.77 ; + RECT 454.57 0 454.965 219.77 ; + RECT 452.69 0.3 452.95 219.77 ; + RECT 451.325 0 451.92 219.77 ; + RECT 446.58 0 450.545 219.77 ; + RECT 445.04 0.155 445.81 219.77 ; + RECT 439.595 0 443.25 219.77 ; + RECT 438.065 0 438.815 219.77 ; + RECT 436.89 0 437.285 219.77 ; + RECT 435.01 0.3 435.27 219.77 ; + RECT 433.645 0 434.24 219.77 ; + RECT 428.9 0 432.865 219.77 ; + RECT 427.36 0.155 428.13 219.77 ; + RECT 421.915 0 425.57 219.77 ; + RECT 420.385 0 421.135 219.77 ; + RECT 419.21 0 419.605 219.77 ; + RECT 417.33 0.3 417.59 219.77 ; + RECT 415.965 0 416.56 219.77 ; + RECT 411.22 0 415.185 219.77 ; + RECT 409.68 0.155 410.45 219.77 ; + RECT 404.235 0 407.89 219.77 ; + RECT 402.705 0 403.455 219.77 ; + RECT 401.53 0 401.925 219.77 ; + RECT 378.725 0.18 400.75 219.77 ; + RECT 378.735 0 400.75 219.77 ; + RECT 374.135 0.3 377.965 219.77 ; + RECT 371.075 0.18 372.865 219.77 ; + RECT 365.465 0.3 366.745 219.77 ; + RECT 362.915 0.3 364.195 219.77 ; + RECT 361.385 0.3 361.645 219.77 ; + RECT 358.325 0.3 358.585 219.77 ; + RECT 356.795 0.3 357.055 219.77 ; + RECT 348.635 0.3 355.525 219.77 ; + RECT 339.145 0 346.345 219.77 ; + RECT 329.965 0.3 336.855 219.77 ; + RECT 329.975 0 336.855 219.77 ; + RECT 328.435 0.3 328.695 219.77 ; + RECT 326.905 0.3 327.165 219.77 ; + RECT 323.845 0.3 324.105 219.77 ; + RECT 321.295 0.3 322.575 219.77 ; + RECT 318.745 0.3 320.025 219.77 ; + RECT 312.625 0.18 314.415 219.77 ; + RECT 312.635 0 314.415 219.77 ; + RECT 307.525 0.3 311.355 219.77 ; + RECT 284.74 0.18 306.765 219.77 ; + RECT 283.565 0 283.96 219.77 ; + RECT 282.035 0 282.785 219.77 ; + RECT 277.6 0 281.255 219.77 ; + RECT 275.04 0.155 275.81 219.77 ; + RECT 270.305 0 274.27 219.77 ; + RECT 268.93 0 269.525 219.77 ; + RECT 267.9 0.3 268.16 219.77 ; + RECT 265.885 0 266.28 219.77 ; + RECT 264.355 0 265.105 219.77 ; + RECT 259.92 0 263.575 219.77 ; + RECT 257.36 0.155 258.13 219.77 ; + RECT 252.625 0 256.59 219.77 ; + RECT 251.25 0 251.845 219.77 ; + RECT 250.22 0.3 250.48 219.77 ; + RECT 248.205 0 248.6 219.77 ; + RECT 246.675 0 247.425 219.77 ; + RECT 242.24 0 245.895 219.77 ; + RECT 239.68 0.155 240.45 219.77 ; + RECT 234.945 0 238.91 219.77 ; + RECT 233.57 0 234.165 219.77 ; + RECT 232.54 0.3 232.8 219.77 ; + RECT 230.525 0 230.92 219.77 ; + RECT 228.995 0 229.745 219.77 ; + RECT 224.56 0 228.215 219.77 ; + RECT 222 0.155 222.77 219.77 ; + RECT 217.265 0 221.23 219.77 ; + RECT 215.89 0 216.485 219.77 ; + RECT 214.86 0.3 215.12 219.77 ; + RECT 212.845 0 213.24 219.77 ; + RECT 211.315 0 212.065 219.77 ; + RECT 206.88 0 210.535 219.77 ; + RECT 204.32 0.155 205.09 219.77 ; + RECT 199.585 0 203.55 219.77 ; + RECT 198.21 0 198.805 219.77 ; + RECT 197.18 0.3 197.44 219.77 ; + RECT 195.165 0 195.56 219.77 ; + RECT 193.635 0 194.385 219.77 ; + RECT 189.2 0 192.855 219.77 ; + RECT 186.64 0.155 187.41 219.77 ; + RECT 181.905 0 185.87 219.77 ; + RECT 180.53 0 181.125 219.77 ; + RECT 179.5 0.3 179.76 219.77 ; + RECT 177.485 0 177.88 219.77 ; + RECT 175.955 0 176.705 219.77 ; + RECT 171.52 0 175.175 219.77 ; + RECT 168.96 0.155 169.73 219.77 ; + RECT 164.225 0 168.19 219.77 ; + RECT 162.85 0 163.445 219.77 ; + RECT 161.82 0.3 162.08 219.77 ; + RECT 159.805 0 160.2 219.77 ; + RECT 158.275 0 159.025 219.77 ; + RECT 153.84 0 157.495 219.77 ; + RECT 151.28 0.155 152.05 219.77 ; + RECT 146.545 0 150.51 219.77 ; + RECT 145.17 0 145.765 219.77 ; + RECT 144.14 0.3 144.4 219.77 ; + RECT 142.125 0 142.52 219.77 ; + RECT 140.595 0 141.345 219.77 ; + RECT 136.16 0 139.815 219.77 ; + RECT 133.6 0.155 134.37 219.77 ; + RECT 128.865 0 132.83 219.77 ; + RECT 127.49 0 128.085 219.77 ; + RECT 126.46 0.3 126.72 219.77 ; + RECT 124.445 0 124.84 219.77 ; + RECT 122.915 0 123.665 219.77 ; + RECT 118.48 0 122.135 219.77 ; + RECT 115.92 0.155 116.69 219.77 ; + RECT 111.185 0 115.15 219.77 ; + RECT 109.81 0 110.405 219.77 ; + RECT 108.78 0.3 109.04 219.77 ; + RECT 106.765 0 107.16 219.77 ; + RECT 105.235 0 105.985 219.77 ; + RECT 100.8 0 104.455 219.77 ; + RECT 98.24 0.155 99.01 219.77 ; + RECT 93.505 0 97.47 219.77 ; + RECT 92.13 0 92.725 219.77 ; + RECT 91.1 0.3 91.36 219.77 ; + RECT 89.085 0 89.48 219.77 ; + RECT 87.555 0 88.305 219.77 ; + RECT 83.12 0 86.775 219.77 ; + RECT 80.56 0.155 81.33 219.77 ; + RECT 75.825 0 79.79 219.77 ; + RECT 74.45 0 75.045 219.77 ; + RECT 73.42 0.3 73.68 219.77 ; + RECT 71.405 0 71.8 219.77 ; + RECT 69.875 0 70.625 219.77 ; + RECT 65.44 0 69.095 219.77 ; + RECT 62.88 0.155 63.65 219.77 ; + RECT 58.145 0 62.11 219.77 ; + RECT 56.77 0 57.365 219.77 ; + RECT 55.74 0.3 56 219.77 ; + RECT 53.725 0 54.12 219.77 ; + RECT 52.195 0 52.945 219.77 ; + RECT 47.76 0 51.415 219.77 ; + RECT 45.2 0.155 45.97 219.77 ; + RECT 40.465 0 44.43 219.77 ; + RECT 39.09 0 39.685 219.77 ; + RECT 38.06 0.3 38.32 219.77 ; + RECT 36.045 0 36.44 219.77 ; + RECT 34.515 0 35.265 219.77 ; + RECT 30.08 0 33.735 219.77 ; + RECT 27.52 0.155 28.29 219.77 ; + RECT 22.785 0 26.75 219.77 ; + RECT 21.41 0 22.005 219.77 ; + RECT 20.38 0.3 20.64 219.77 ; + RECT 18.365 0 18.76 219.77 ; + RECT 16.835 0 17.585 219.77 ; + RECT 12.4 0 16.055 219.77 ; + RECT 9.84 0.155 10.61 219.77 ; + RECT 5.105 0 9.07 219.77 ; + RECT 3.73 0 4.325 219.77 ; + RECT 2.7 0.3 2.96 219.77 ; + RECT 0 0 1.93 219.77 ; + RECT 682.54 0 682.78 219.77 ; + RECT 664.86 0 665.1 219.77 ; + RECT 647.18 0 647.42 219.77 ; + RECT 629.5 0 629.74 219.77 ; + RECT 611.82 0 612.06 219.77 ; + RECT 594.14 0 594.38 219.77 ; + RECT 576.46 0 576.7 219.77 ; + RECT 558.78 0 559.02 219.77 ; + RECT 541.1 0 541.34 219.77 ; + RECT 523.42 0 523.66 219.77 ; + RECT 505.74 0 505.98 219.77 ; + RECT 488.06 0 488.3 219.77 ; + RECT 470.38 0 470.62 219.77 ; + RECT 452.7 0 452.94 219.77 ; + RECT 435.02 0 435.26 219.77 ; + RECT 417.34 0 417.58 219.77 ; + RECT 374.145 0 377.955 219.77 ; + RECT 365.475 0 366.735 219.77 ; + RECT 362.925 0 364.185 219.77 ; + RECT 361.395 0 361.635 219.77 ; + RECT 358.335 0 358.575 219.77 ; + RECT 356.805 0 357.045 219.77 ; + RECT 348.635 0 355.515 219.77 ; + RECT 328.445 0 328.685 219.77 ; + RECT 326.915 0 327.155 219.77 ; + RECT 323.855 0 324.095 219.77 ; + RECT 321.305 0 322.565 219.77 ; + RECT 318.755 0 320.015 219.77 ; + RECT 307.535 0 311.345 219.77 ; + RECT 267.91 0 268.15 219.77 ; + RECT 250.23 0 250.47 219.77 ; + RECT 232.55 0 232.79 219.77 ; + RECT 214.87 0 215.11 219.77 ; + RECT 197.19 0 197.43 219.77 ; + RECT 179.51 0 179.75 219.77 ; + RECT 161.83 0 162.07 219.77 ; + RECT 144.15 0 144.39 219.77 ; + RECT 126.47 0 126.71 219.77 ; + RECT 108.79 0 109.03 219.77 ; + RECT 91.11 0 91.35 219.77 ; + RECT 73.43 0 73.67 219.77 ; + RECT 55.75 0 55.99 219.77 ; + RECT 38.07 0 38.31 219.77 ; + RECT 20.39 0 20.63 219.77 ; + RECT 2.71 0 2.95 219.77 ; + RECT 371.075 0 372.855 219.77 ; + RECT 284.74 0 306.755 219.77 ; + RECT 674.89 0 675.64 219.77 ; + RECT 657.21 0 657.96 219.77 ; + RECT 639.53 0 640.28 219.77 ; + RECT 621.85 0 622.6 219.77 ; + RECT 604.17 0 604.92 219.77 ; + RECT 586.49 0 587.24 219.77 ; + RECT 568.81 0 569.56 219.77 ; + RECT 551.13 0 551.88 219.77 ; + RECT 533.45 0 534.2 219.77 ; + RECT 515.77 0 516.52 219.77 ; + RECT 498.09 0 498.84 219.77 ; + RECT 480.41 0 481.16 219.77 ; + RECT 462.73 0 463.48 219.77 ; + RECT 445.05 0 445.8 219.77 ; + RECT 427.37 0 428.12 219.77 ; + RECT 409.69 0 410.44 219.77 ; + RECT 275.05 0 275.8 219.77 ; + RECT 257.37 0 258.12 219.77 ; + RECT 239.69 0 240.44 219.77 ; + RECT 222.01 0 222.76 219.77 ; + RECT 204.33 0 205.08 219.77 ; + RECT 186.65 0 187.4 219.77 ; + RECT 168.97 0 169.72 219.77 ; + RECT 151.29 0 152.04 219.77 ; + RECT 133.61 0 134.36 219.77 ; + RECT 115.93 0 116.68 219.77 ; + RECT 98.25 0 99 219.77 ; + RECT 80.57 0 81.32 219.77 ; + RECT 62.89 0 63.64 219.77 ; + RECT 45.21 0 45.96 219.77 ; + RECT 27.53 0 28.28 219.77 ; + RECT 9.85 0 10.6 219.77 ; + LAYER Metal3 ; + RECT 0 0 685.49 219.77 ; + LAYER Metal4 SPACING 0.21 ; + RECT 383.035 0 400.625 219.77 ; + RECT 377.885 0 379.705 219.77 ; + RECT 372.735 0 374.555 219.77 ; + RECT 679.605 0 685.49 219.77 ; + RECT 670.765 0 674.665 219.77 ; + RECT 670.765 47.305 685.49 53.15 ; + RECT 661.925 0 665.825 219.77 ; + RECT 653.085 0 656.985 219.77 ; + RECT 653.085 47.305 665.825 53.15 ; + RECT 644.245 0 648.145 219.77 ; + RECT 635.405 0 639.305 219.77 ; + RECT 635.405 47.305 648.145 53.15 ; + RECT 626.565 0 630.465 219.77 ; + RECT 617.725 0 621.625 219.77 ; + RECT 617.725 47.305 630.465 53.15 ; + RECT 608.885 0 612.785 219.77 ; + RECT 600.045 0 603.945 219.77 ; + RECT 600.045 47.305 612.785 53.15 ; + RECT 591.205 0 595.105 219.77 ; + RECT 582.365 0 586.265 219.77 ; + RECT 582.365 47.305 595.105 53.15 ; + RECT 573.525 0 577.425 219.77 ; + RECT 564.685 0 568.585 219.77 ; + RECT 564.685 47.305 577.425 53.15 ; + RECT 555.845 0 559.745 219.77 ; + RECT 547.005 0 550.905 219.77 ; + RECT 547.005 47.305 559.745 53.15 ; + RECT 538.165 0 542.065 219.77 ; + RECT 529.325 0 533.225 219.77 ; + RECT 529.325 47.305 542.065 53.15 ; + RECT 520.485 0 524.385 219.77 ; + RECT 511.645 0 515.545 219.77 ; + RECT 511.645 47.305 524.385 53.15 ; + RECT 502.805 0 506.705 219.77 ; + RECT 493.965 0 497.865 219.77 ; + RECT 493.965 47.305 506.705 53.15 ; + RECT 485.125 0 489.025 219.77 ; + RECT 476.285 0 480.185 219.77 ; + RECT 476.285 47.305 489.025 53.15 ; + RECT 467.445 0 471.345 219.77 ; + RECT 458.605 0 462.505 219.77 ; + RECT 458.605 47.305 471.345 53.15 ; + RECT 449.765 0 453.665 219.77 ; + RECT 440.925 0 444.825 219.77 ; + RECT 440.925 47.305 453.665 53.15 ; + RECT 432.085 0 435.985 219.77 ; + RECT 423.245 0 427.145 219.77 ; + RECT 423.245 47.305 435.985 53.15 ; + RECT 414.405 0 418.305 219.77 ; + RECT 405.565 0 409.465 219.77 ; + RECT 405.565 47.305 418.305 53.15 ; + RECT 367.585 0 369.405 219.77 ; + RECT 362.435 0 364.255 219.77 ; + RECT 357.285 0 359.105 219.77 ; + RECT 352.135 0 353.955 219.77 ; + RECT 346.985 0 348.805 219.77 ; + RECT 341.835 0 343.655 219.77 ; + RECT 336.685 0 338.505 219.77 ; + RECT 331.535 0 333.355 219.77 ; + RECT 326.385 0 328.205 219.77 ; + RECT 321.235 0 323.055 219.77 ; + RECT 316.085 0 317.905 219.77 ; + RECT 310.935 0 312.755 219.77 ; + RECT 305.785 0 307.605 219.77 ; + RECT 284.865 0 302.455 219.77 ; + RECT 276.025 0 279.925 219.77 ; + RECT 267.185 0 271.085 219.77 ; + RECT 267.185 47.305 279.925 53.15 ; + RECT 258.345 0 262.245 219.77 ; + RECT 249.505 0 253.405 219.77 ; + RECT 249.505 47.305 262.245 53.15 ; + RECT 240.665 0 244.565 219.77 ; + RECT 231.825 0 235.725 219.77 ; + RECT 231.825 47.305 244.565 53.15 ; + RECT 222.985 0 226.885 219.77 ; + RECT 214.145 0 218.045 219.77 ; + RECT 214.145 47.305 226.885 53.15 ; + RECT 205.305 0 209.205 219.77 ; + RECT 196.465 0 200.365 219.77 ; + RECT 196.465 47.305 209.205 53.15 ; + RECT 187.625 0 191.525 219.77 ; + RECT 178.785 0 182.685 219.77 ; + RECT 178.785 47.305 191.525 53.15 ; + RECT 169.945 0 173.845 219.77 ; + RECT 161.105 0 165.005 219.77 ; + RECT 161.105 47.305 173.845 53.15 ; + RECT 152.265 0 156.165 219.77 ; + RECT 143.425 0 147.325 219.77 ; + RECT 143.425 47.305 156.165 53.15 ; + RECT 134.585 0 138.485 219.77 ; + RECT 125.745 0 129.645 219.77 ; + RECT 125.745 47.305 138.485 53.15 ; + RECT 116.905 0 120.805 219.77 ; + RECT 108.065 0 111.965 219.77 ; + RECT 108.065 47.305 120.805 53.15 ; + RECT 99.225 0 103.125 219.77 ; + RECT 90.385 0 94.285 219.77 ; + RECT 90.385 47.305 103.125 53.15 ; + RECT 81.545 0 85.445 219.77 ; + RECT 72.705 0 76.605 219.77 ; + RECT 72.705 47.305 85.445 53.15 ; + RECT 63.865 0 67.765 219.77 ; + RECT 55.025 0 58.925 219.77 ; + RECT 55.025 47.305 67.765 53.15 ; + RECT 46.185 0 50.085 219.77 ; + RECT 37.345 0 41.245 219.77 ; + RECT 37.345 47.305 50.085 53.15 ; + RECT 28.505 0 32.405 219.77 ; + RECT 19.665 0 23.565 219.77 ; + RECT 19.665 47.305 32.405 53.15 ; + RECT 10.825 0 14.725 219.77 ; + RECT 0 0 5.885 219.77 ; + RECT 0 47.305 14.725 53.15 ; + END +END RM_IHPSG13_2P_512x32_c2_bm_bist + +END LIBRARY diff --git a/flow/platforms/ihp-sg13g2/lef/RM_IHPSG13_2P_512x8_c2_bm_bist.lef b/flow/platforms/ihp-sg13g2/lef/RM_IHPSG13_2P_512x8_c2_bm_bist.lef new file mode 100644 index 0000000000..41288ddbf5 --- /dev/null +++ b/flow/platforms/ihp-sg13g2/lef/RM_IHPSG13_2P_512x8_c2_bm_bist.lef @@ -0,0 +1,2707 @@ +# ------------------------------------------------------ +# +# Copyright 2025 IHP PDK Authors +# +# Licensed under the Apache License, Version 2.0 (the "License"); +# you may not use this file except in compliance with the License. +# You may obtain a copy of the License at +# +# https://www.apache.org/licenses/LICENSE-2.0 +# +# Unless required by applicable law or agreed to in writing, software +# distributed under the License is distributed on an "AS IS" BASIS, +# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +# See the License for the specific language governing permissions and +# limitations under the License. +# +# Generated on Wed Aug 27 13:34:44 2025 +# +# ------------------------------------------------------ +VERSION 5.7 ; +BUSBITCHARS "[]" ; +DIVIDERCHAR "/" ; + +MACRO RM_IHPSG13_2P_512x8_c2_bm_bist + CLASS BLOCK ; + ORIGIN 0 0 ; + FOREIGN RM_IHPSG13_2P_512x8_c2_bm_bist 0 0 ; + SIZE 261.17 BY 219.77 ; + SYMMETRY X Y R90 ; + PIN A_DIN[4] + DIRECTION INPUT ; + USE SIGNAL ; + ANTENNAPARTIALMETALAREA 3.9091 LAYER Metal2 ; + ANTENNAMODEL OXIDE1 ; + ANTENNAGATEAREA 0.20085 LAYER Metal2 ; + ANTENNAMAXAREACAR 20.368932 LAYER Metal2 ; + PORT + LAYER Metal2 ; + RECT 195.99 0 196.25 0.26 ; + END + END A_DIN[4] + PIN A_DIN[3] + DIRECTION INPUT ; + USE SIGNAL ; + ANTENNAPARTIALMETALAREA 3.9091 LAYER Metal2 ; + ANTENNAMODEL OXIDE1 ; + ANTENNAGATEAREA 0.20085 LAYER Metal2 ; + ANTENNAMAXAREACAR 20.368932 LAYER Metal2 ; + PORT + LAYER Metal2 ; + RECT 64.92 0 65.18 0.26 ; + END + END A_DIN[3] + PIN A_BIST_DIN[4] + DIRECTION INPUT ; + USE SIGNAL ; + ANTENNAPARTIALMETALAREA 4.136375 LAYER Metal2 ; + ANTENNAMODEL OXIDE1 ; + ANTENNAGATEAREA 0.20085 LAYER Metal2 ; + ANTENNAMAXAREACAR 21.874907 LAYER Metal2 ; + PORT + LAYER Metal2 ; + RECT 196.5 0 196.76 0.26 ; + END + END A_BIST_DIN[4] + PIN A_BIST_DIN[3] + DIRECTION INPUT ; + USE SIGNAL ; + ANTENNAPARTIALMETALAREA 4.136375 LAYER Metal2 ; + ANTENNAMODEL OXIDE1 ; + ANTENNAGATEAREA 0.20085 LAYER Metal2 ; + ANTENNAMAXAREACAR 21.874907 LAYER Metal2 ; + PORT + LAYER Metal2 ; + RECT 64.41 0 64.67 0.26 ; + END + END A_BIST_DIN[3] + PIN A_BM[4] + DIRECTION INPUT ; + USE SIGNAL ; + ANTENNAPARTIALMETALAREA 1.7264 LAYER Metal2 ; + ANTENNAMODEL OXIDE1 ; + ANTENNAGATEAREA 0.20085 LAYER Metal2 ; + ANTENNAMAXAREACAR 9.501618 LAYER Metal2 ; + PORT + LAYER Metal2 ; + RECT 204.66 0 204.92 0.26 ; + END + END A_BM[4] + PIN A_BM[3] + DIRECTION INPUT ; + USE SIGNAL ; + ANTENNAPARTIALMETALAREA 1.7264 LAYER Metal2 ; + ANTENNAMODEL OXIDE1 ; + ANTENNAGATEAREA 0.20085 LAYER Metal2 ; + ANTENNAMAXAREACAR 9.501618 LAYER Metal2 ; + PORT + LAYER Metal2 ; + RECT 56.25 0 56.51 0.26 ; + END + END A_BM[3] + PIN A_BIST_BM[4] + DIRECTION INPUT ; + USE SIGNAL ; + ANTENNAPARTIALMETALAREA 1.7602 LAYER Metal2 ; + ANTENNAMODEL OXIDE1 ; + ANTENNAGATEAREA 0.20085 LAYER Metal2 ; + ANTENNAMAXAREACAR 9.678367 LAYER Metal2 ; + PORT + LAYER Metal2 ; + RECT 203.285 0 203.545 0.26 ; + END + END A_BIST_BM[4] + PIN A_BIST_BM[3] + DIRECTION INPUT ; + USE SIGNAL ; + ANTENNAPARTIALMETALAREA 1.7602 LAYER Metal2 ; + ANTENNAMODEL OXIDE1 ; + ANTENNAGATEAREA 0.20085 LAYER Metal2 ; + ANTENNAMAXAREACAR 9.678367 LAYER Metal2 ; + PORT + LAYER Metal2 ; + RECT 57.625 0 57.885 0.26 ; + END + END A_BIST_BM[3] + PIN A_DOUT[4] + DIRECTION OUTPUT ; + USE SIGNAL ; + ANTENNAPARTIALMETALAREA 4.8256 LAYER Metal2 ; + ANTENNADIFFAREA 0.988 LAYER Metal2 ; + PORT + LAYER Metal2 ; + RECT 188.85 0 189.11 0.26 ; + END + END A_DOUT[4] + PIN A_DOUT[3] + DIRECTION OUTPUT ; + USE SIGNAL ; + ANTENNAPARTIALMETALAREA 4.8256 LAYER Metal2 ; + ANTENNADIFFAREA 0.988 LAYER Metal2 ; + PORT + LAYER Metal2 ; + RECT 72.06 0 72.32 0.26 ; + END + END A_DOUT[3] + PIN B_DIN[4] + DIRECTION INPUT ; + USE SIGNAL ; + ANTENNAPARTIALMETALAREA 2.925 LAYER Metal2 ; + ANTENNAMODEL OXIDE1 ; + ANTENNAGATEAREA 0.20085 LAYER Metal2 ; + ANTENNAMAXAREACAR 15.469256 LAYER Metal2 ; + PORT + LAYER Metal2 ; + RECT 198.54 0 198.8 0.26 ; + END + END B_DIN[4] + PIN B_DIN[3] + DIRECTION INPUT ; + USE SIGNAL ; + ANTENNAPARTIALMETALAREA 2.925 LAYER Metal2 ; + ANTENNAMODEL OXIDE1 ; + ANTENNAGATEAREA 0.20085 LAYER Metal2 ; + ANTENNAMAXAREACAR 15.469256 LAYER Metal2 ; + PORT + LAYER Metal2 ; + RECT 62.37 0 62.63 0.26 ; + END + END B_DIN[3] + PIN B_BIST_DIN[4] + DIRECTION INPUT ; + USE SIGNAL ; + ANTENNAPARTIALMETALAREA 2.9445 LAYER Metal2 ; + ANTENNAMODEL OXIDE1 ; + ANTENNAGATEAREA 0.20085 LAYER Metal2 ; + ANTENNAMAXAREACAR 15.929052 LAYER Metal2 ; + PORT + LAYER Metal2 ; + RECT 197.01 0 197.27 0.26 ; + END + END B_BIST_DIN[4] + PIN B_BIST_DIN[3] + DIRECTION INPUT ; + USE SIGNAL ; + ANTENNAPARTIALMETALAREA 2.9445 LAYER Metal2 ; + ANTENNAMODEL OXIDE1 ; + ANTENNAGATEAREA 0.20085 LAYER Metal2 ; + ANTENNAMAXAREACAR 15.929052 LAYER Metal2 ; + PORT + LAYER Metal2 ; + RECT 63.9 0 64.16 0.26 ; + END + END B_BIST_DIN[3] + PIN B_BM[4] + DIRECTION INPUT ; + USE SIGNAL ; + ANTENNAPARTIALMETALAREA 0.7007 LAYER Metal2 ; + ANTENNAMODEL OXIDE1 ; + ANTENNAGATEAREA 0.20085 LAYER Metal2 ; + ANTENNAMAXAREACAR 4.394822 LAYER Metal2 ; + PORT + LAYER Metal2 ; + RECT 190.025 0 190.285 0.26 ; + END + END B_BM[4] + PIN B_BM[3] + DIRECTION INPUT ; + USE SIGNAL ; + ANTENNAPARTIALMETALAREA 0.7007 LAYER Metal2 ; + ANTENNAMODEL OXIDE1 ; + ANTENNAGATEAREA 0.20085 LAYER Metal2 ; + ANTENNAMAXAREACAR 4.394822 LAYER Metal2 ; + PORT + LAYER Metal2 ; + RECT 70.885 0 71.145 0.26 ; + END + END B_BM[3] + PIN B_BIST_BM[4] + DIRECTION INPUT ; + USE SIGNAL ; + ANTENNAPARTIALMETALAREA 0.7007 LAYER Metal2 ; + ANTENNAMODEL OXIDE1 ; + ANTENNAGATEAREA 0.20085 LAYER Metal2 ; + ANTENNAMAXAREACAR 4.394822 LAYER Metal2 ; + PORT + LAYER Metal2 ; + RECT 191.555 0 191.815 0.26 ; + END + END B_BIST_BM[4] + PIN B_BIST_BM[3] + DIRECTION INPUT ; + USE SIGNAL ; + ANTENNAPARTIALMETALAREA 0.7007 LAYER Metal2 ; + ANTENNAMODEL OXIDE1 ; + ANTENNAGATEAREA 0.20085 LAYER Metal2 ; + ANTENNAMAXAREACAR 4.394822 LAYER Metal2 ; + PORT + LAYER Metal2 ; + RECT 69.355 0 69.615 0.26 ; + END + END B_BIST_BM[3] + PIN B_DOUT[4] + DIRECTION OUTPUT ; + USE SIGNAL ; + ANTENNAPARTIALMETALAREA 4.836 LAYER Metal2 ; + ANTENNADIFFAREA 0.988 LAYER Metal2 ; + PORT + LAYER Metal2 ; + RECT 205.68 0 205.94 0.26 ; + END + END B_DOUT[4] + PIN B_DOUT[3] + DIRECTION OUTPUT ; + USE SIGNAL ; + ANTENNAPARTIALMETALAREA 4.836 LAYER Metal2 ; + ANTENNADIFFAREA 0.988 LAYER Metal2 ; + PORT + LAYER Metal2 ; + RECT 55.23 0 55.49 0.26 ; + END + END B_DOUT[3] + PIN VSS! + DIRECTION INOUT ; + USE GROUND ; + NETEXPR "vss VSS!" ; + PORT + LAYER Metal4 ; + RECT 241.765 0 246.185 219.77 ; + END + PORT + LAYER Metal4 ; + RECT 224.085 0 228.505 219.77 ; + END + PORT + LAYER Metal4 ; + RECT 206.405 0 210.825 219.77 ; + END + PORT + LAYER Metal4 ; + RECT 188.725 0 193.145 219.77 ; + END + PORT + LAYER Metal4 ; + RECT 167.805 0 170.615 219.77 ; + END + PORT + LAYER Metal4 ; + RECT 157.505 0 160.315 219.77 ; + END + PORT + LAYER Metal4 ; + RECT 142.055 0 144.865 219.77 ; + END + PORT + LAYER Metal4 ; + RECT 131.755 0 134.565 219.77 ; + END + PORT + LAYER Metal4 ; + RECT 126.605 0 129.415 219.77 ; + END + PORT + LAYER Metal4 ; + RECT 116.305 0 119.115 219.77 ; + END + PORT + LAYER Metal4 ; + RECT 100.855 0 103.665 219.77 ; + END + PORT + LAYER Metal4 ; + RECT 90.555 0 93.365 219.77 ; + END + PORT + LAYER Metal4 ; + RECT 68.025 0 72.445 219.77 ; + END + PORT + LAYER Metal4 ; + RECT 50.345 0 54.765 219.77 ; + END + PORT + LAYER Metal4 ; + RECT 32.665 0 37.085 219.77 ; + END + PORT + LAYER Metal4 ; + RECT 14.985 0 19.405 219.77 ; + END + END VSS! + PIN VDD! + DIRECTION INOUT ; + USE POWER ; + NETEXPR "vdd VDD!" ; + PORT + LAYER Metal4 ; + RECT 250.605 0 255.025 47.045 ; + END + PORT + LAYER Metal4 ; + RECT 232.925 0 237.345 47.045 ; + END + PORT + LAYER Metal4 ; + RECT 215.245 0 219.665 47.045 ; + END + PORT + LAYER Metal4 ; + RECT 197.565 0 201.985 47.045 ; + END + PORT + LAYER Metal4 ; + RECT 162.655 0 165.465 219.77 ; + END + PORT + LAYER Metal4 ; + RECT 152.355 0 155.165 219.77 ; + END + PORT + LAYER Metal4 ; + RECT 147.205 0 150.015 219.77 ; + END + PORT + LAYER Metal4 ; + RECT 136.905 0 139.715 219.77 ; + END + PORT + LAYER Metal4 ; + RECT 121.455 0 124.265 219.77 ; + END + PORT + LAYER Metal4 ; + RECT 111.155 0 113.965 219.77 ; + END + PORT + LAYER Metal4 ; + RECT 106.005 0 108.815 219.77 ; + END + PORT + LAYER Metal4 ; + RECT 95.705 0 98.515 219.77 ; + END + PORT + LAYER Metal4 ; + RECT 59.185 0 63.605 47.045 ; + END + PORT + LAYER Metal4 ; + RECT 41.505 0 45.925 47.045 ; + END + PORT + LAYER Metal4 ; + RECT 23.825 0 28.245 47.045 ; + END + PORT + LAYER Metal4 ; + RECT 6.145 0 10.565 47.045 ; + END + END VDD! + PIN VDDARRAY! + DIRECTION INOUT ; + USE POWER ; + NETEXPR "vddarray VDDARRAY!" ; + PORT + LAYER Metal4 ; + RECT 250.605 53.41 255.025 219.77 ; + END + PORT + LAYER Metal4 ; + RECT 232.925 53.41 237.345 219.77 ; + END + PORT + LAYER Metal4 ; + RECT 215.245 53.41 219.665 219.77 ; + END + PORT + LAYER Metal4 ; + RECT 197.565 53.41 201.985 219.77 ; + END + PORT + LAYER Metal4 ; + RECT 59.185 53.41 63.605 219.77 ; + END + PORT + LAYER Metal4 ; + RECT 41.505 53.41 45.925 219.77 ; + END + PORT + LAYER Metal4 ; + RECT 23.825 53.41 28.245 219.77 ; + END + PORT + LAYER Metal4 ; + RECT 6.145 53.41 10.565 219.77 ; + END + END VDDARRAY! + PIN A_DIN[5] + DIRECTION INPUT ; + USE SIGNAL ; + ANTENNAPARTIALMETALAREA 3.9091 LAYER Metal2 ; + ANTENNAMODEL OXIDE1 ; + ANTENNAGATEAREA 0.20085 LAYER Metal2 ; + ANTENNAMAXAREACAR 20.368932 LAYER Metal2 ; + PORT + LAYER Metal2 ; + RECT 213.67 0 213.93 0.26 ; + END + END A_DIN[5] + PIN A_DIN[2] + DIRECTION INPUT ; + USE SIGNAL ; + ANTENNAPARTIALMETALAREA 3.9091 LAYER Metal2 ; + ANTENNAMODEL OXIDE1 ; + ANTENNAGATEAREA 0.20085 LAYER Metal2 ; + ANTENNAMAXAREACAR 20.368932 LAYER Metal2 ; + PORT + LAYER Metal2 ; + RECT 47.24 0 47.5 0.26 ; + END + END A_DIN[2] + PIN A_BIST_DIN[5] + DIRECTION INPUT ; + USE SIGNAL ; + ANTENNAPARTIALMETALAREA 4.136375 LAYER Metal2 ; + ANTENNAMODEL OXIDE1 ; + ANTENNAGATEAREA 0.20085 LAYER Metal2 ; + ANTENNAMAXAREACAR 21.874907 LAYER Metal2 ; + PORT + LAYER Metal2 ; + RECT 214.18 0 214.44 0.26 ; + END + END A_BIST_DIN[5] + PIN A_BIST_DIN[2] + DIRECTION INPUT ; + USE SIGNAL ; + ANTENNAPARTIALMETALAREA 4.136375 LAYER Metal2 ; + ANTENNAMODEL OXIDE1 ; + ANTENNAGATEAREA 0.20085 LAYER Metal2 ; + ANTENNAMAXAREACAR 21.874907 LAYER Metal2 ; + PORT + LAYER Metal2 ; + RECT 46.73 0 46.99 0.26 ; + END + END A_BIST_DIN[2] + PIN A_BM[5] + DIRECTION INPUT ; + USE SIGNAL ; + ANTENNAPARTIALMETALAREA 1.7264 LAYER Metal2 ; + ANTENNAMODEL OXIDE1 ; + ANTENNAGATEAREA 0.20085 LAYER Metal2 ; + ANTENNAMAXAREACAR 9.501618 LAYER Metal2 ; + PORT + LAYER Metal2 ; + RECT 222.34 0 222.6 0.26 ; + END + END A_BM[5] + PIN A_BM[2] + DIRECTION INPUT ; + USE SIGNAL ; + ANTENNAPARTIALMETALAREA 1.7264 LAYER Metal2 ; + ANTENNAMODEL OXIDE1 ; + ANTENNAGATEAREA 0.20085 LAYER Metal2 ; + ANTENNAMAXAREACAR 9.501618 LAYER Metal2 ; + PORT + LAYER Metal2 ; + RECT 38.57 0 38.83 0.26 ; + END + END A_BM[2] + PIN A_BIST_BM[5] + DIRECTION INPUT ; + USE SIGNAL ; + ANTENNAPARTIALMETALAREA 1.7602 LAYER Metal2 ; + ANTENNAMODEL OXIDE1 ; + ANTENNAGATEAREA 0.20085 LAYER Metal2 ; + ANTENNAMAXAREACAR 9.678367 LAYER Metal2 ; + PORT + LAYER Metal2 ; + RECT 220.965 0 221.225 0.26 ; + END + END A_BIST_BM[5] + PIN A_BIST_BM[2] + DIRECTION INPUT ; + USE SIGNAL ; + ANTENNAPARTIALMETALAREA 1.7602 LAYER Metal2 ; + ANTENNAMODEL OXIDE1 ; + ANTENNAGATEAREA 0.20085 LAYER Metal2 ; + ANTENNAMAXAREACAR 9.678367 LAYER Metal2 ; + PORT + LAYER Metal2 ; + RECT 39.945 0 40.205 0.26 ; + END + END A_BIST_BM[2] + PIN A_DOUT[5] + DIRECTION OUTPUT ; + USE SIGNAL ; + ANTENNAPARTIALMETALAREA 4.8256 LAYER Metal2 ; + ANTENNADIFFAREA 0.988 LAYER Metal2 ; + PORT + LAYER Metal2 ; + RECT 206.53 0 206.79 0.26 ; + END + END A_DOUT[5] + PIN A_DOUT[2] + DIRECTION OUTPUT ; + USE SIGNAL ; + ANTENNAPARTIALMETALAREA 4.8256 LAYER Metal2 ; + ANTENNADIFFAREA 0.988 LAYER Metal2 ; + PORT + LAYER Metal2 ; + RECT 54.38 0 54.64 0.26 ; + END + END A_DOUT[2] + PIN B_DIN[5] + DIRECTION INPUT ; + USE SIGNAL ; + ANTENNAPARTIALMETALAREA 2.925 LAYER Metal2 ; + ANTENNAMODEL OXIDE1 ; + ANTENNAGATEAREA 0.20085 LAYER Metal2 ; + ANTENNAMAXAREACAR 15.469256 LAYER Metal2 ; + PORT + LAYER Metal2 ; + RECT 216.22 0 216.48 0.26 ; + END + END B_DIN[5] + PIN B_DIN[2] + DIRECTION INPUT ; + USE SIGNAL ; + ANTENNAPARTIALMETALAREA 2.925 LAYER Metal2 ; + ANTENNAMODEL OXIDE1 ; + ANTENNAGATEAREA 0.20085 LAYER Metal2 ; + ANTENNAMAXAREACAR 15.469256 LAYER Metal2 ; + PORT + LAYER Metal2 ; + RECT 44.69 0 44.95 0.26 ; + END + END B_DIN[2] + PIN B_BIST_DIN[5] + DIRECTION INPUT ; + USE SIGNAL ; + ANTENNAPARTIALMETALAREA 2.9445 LAYER Metal2 ; + ANTENNAMODEL OXIDE1 ; + ANTENNAGATEAREA 0.20085 LAYER Metal2 ; + ANTENNAMAXAREACAR 15.929052 LAYER Metal2 ; + PORT + LAYER Metal2 ; + RECT 214.69 0 214.95 0.26 ; + END + END B_BIST_DIN[5] + PIN B_BIST_DIN[2] + DIRECTION INPUT ; + USE SIGNAL ; + ANTENNAPARTIALMETALAREA 2.9445 LAYER Metal2 ; + ANTENNAMODEL OXIDE1 ; + ANTENNAGATEAREA 0.20085 LAYER Metal2 ; + ANTENNAMAXAREACAR 15.929052 LAYER Metal2 ; + PORT + LAYER Metal2 ; + RECT 46.22 0 46.48 0.26 ; + END + END B_BIST_DIN[2] + PIN B_BM[5] + DIRECTION INPUT ; + USE SIGNAL ; + ANTENNAPARTIALMETALAREA 0.7007 LAYER Metal2 ; + ANTENNAMODEL OXIDE1 ; + ANTENNAGATEAREA 0.20085 LAYER Metal2 ; + ANTENNAMAXAREACAR 4.394822 LAYER Metal2 ; + PORT + LAYER Metal2 ; + RECT 207.705 0 207.965 0.26 ; + END + END B_BM[5] + PIN B_BM[2] + DIRECTION INPUT ; + USE SIGNAL ; + ANTENNAPARTIALMETALAREA 0.7007 LAYER Metal2 ; + ANTENNAMODEL OXIDE1 ; + ANTENNAGATEAREA 0.20085 LAYER Metal2 ; + ANTENNAMAXAREACAR 4.394822 LAYER Metal2 ; + PORT + LAYER Metal2 ; + RECT 53.205 0 53.465 0.26 ; + END + END B_BM[2] + PIN B_BIST_BM[5] + DIRECTION INPUT ; + USE SIGNAL ; + ANTENNAPARTIALMETALAREA 0.7007 LAYER Metal2 ; + ANTENNAMODEL OXIDE1 ; + ANTENNAGATEAREA 0.20085 LAYER Metal2 ; + ANTENNAMAXAREACAR 4.394822 LAYER Metal2 ; + PORT + LAYER Metal2 ; + RECT 209.235 0 209.495 0.26 ; + END + END B_BIST_BM[5] + PIN B_BIST_BM[2] + DIRECTION INPUT ; + USE SIGNAL ; + ANTENNAPARTIALMETALAREA 0.7007 LAYER Metal2 ; + ANTENNAMODEL OXIDE1 ; + ANTENNAGATEAREA 0.20085 LAYER Metal2 ; + ANTENNAMAXAREACAR 4.394822 LAYER Metal2 ; + PORT + LAYER Metal2 ; + RECT 51.675 0 51.935 0.26 ; + END + END B_BIST_BM[2] + PIN B_DOUT[5] + DIRECTION OUTPUT ; + USE SIGNAL ; + ANTENNAPARTIALMETALAREA 4.836 LAYER Metal2 ; + ANTENNADIFFAREA 0.988 LAYER Metal2 ; + PORT + LAYER Metal2 ; + RECT 223.36 0 223.62 0.26 ; + END + END B_DOUT[5] + PIN B_DOUT[2] + DIRECTION OUTPUT ; + USE SIGNAL ; + ANTENNAPARTIALMETALAREA 4.836 LAYER Metal2 ; + ANTENNADIFFAREA 0.988 LAYER Metal2 ; + PORT + LAYER Metal2 ; + RECT 37.55 0 37.81 0.26 ; + END + END B_DOUT[2] + PIN A_DIN[6] + DIRECTION INPUT ; + USE SIGNAL ; + ANTENNAPARTIALMETALAREA 3.9091 LAYER Metal2 ; + ANTENNAMODEL OXIDE1 ; + ANTENNAGATEAREA 0.20085 LAYER Metal2 ; + ANTENNAMAXAREACAR 20.368932 LAYER Metal2 ; + PORT + LAYER Metal2 ; + RECT 231.35 0 231.61 0.26 ; + END + END A_DIN[6] + PIN A_DIN[1] + DIRECTION INPUT ; + USE SIGNAL ; + ANTENNAPARTIALMETALAREA 3.9091 LAYER Metal2 ; + ANTENNAMODEL OXIDE1 ; + ANTENNAGATEAREA 0.20085 LAYER Metal2 ; + ANTENNAMAXAREACAR 20.368932 LAYER Metal2 ; + PORT + LAYER Metal2 ; + RECT 29.56 0 29.82 0.26 ; + END + END A_DIN[1] + PIN A_BIST_DIN[6] + DIRECTION INPUT ; + USE SIGNAL ; + ANTENNAPARTIALMETALAREA 4.136375 LAYER Metal2 ; + ANTENNAMODEL OXIDE1 ; + ANTENNAGATEAREA 0.20085 LAYER Metal2 ; + ANTENNAMAXAREACAR 21.874907 LAYER Metal2 ; + PORT + LAYER Metal2 ; + RECT 231.86 0 232.12 0.26 ; + END + END A_BIST_DIN[6] + PIN A_BIST_DIN[1] + DIRECTION INPUT ; + USE SIGNAL ; + ANTENNAPARTIALMETALAREA 4.136375 LAYER Metal2 ; + ANTENNAMODEL OXIDE1 ; + ANTENNAGATEAREA 0.20085 LAYER Metal2 ; + ANTENNAMAXAREACAR 21.874907 LAYER Metal2 ; + PORT + LAYER Metal2 ; + RECT 29.05 0 29.31 0.26 ; + END + END A_BIST_DIN[1] + PIN A_BM[6] + DIRECTION INPUT ; + USE SIGNAL ; + ANTENNAPARTIALMETALAREA 1.7264 LAYER Metal2 ; + ANTENNAMODEL OXIDE1 ; + ANTENNAGATEAREA 0.20085 LAYER Metal2 ; + ANTENNAMAXAREACAR 9.501618 LAYER Metal2 ; + PORT + LAYER Metal2 ; + RECT 240.02 0 240.28 0.26 ; + END + END A_BM[6] + PIN A_BM[1] + DIRECTION INPUT ; + USE SIGNAL ; + ANTENNAPARTIALMETALAREA 1.7264 LAYER Metal2 ; + ANTENNAMODEL OXIDE1 ; + ANTENNAGATEAREA 0.20085 LAYER Metal2 ; + ANTENNAMAXAREACAR 9.501618 LAYER Metal2 ; + PORT + LAYER Metal2 ; + RECT 20.89 0 21.15 0.26 ; + END + END A_BM[1] + PIN A_BIST_BM[6] + DIRECTION INPUT ; + USE SIGNAL ; + ANTENNAPARTIALMETALAREA 1.7602 LAYER Metal2 ; + ANTENNAMODEL OXIDE1 ; + ANTENNAGATEAREA 0.20085 LAYER Metal2 ; + ANTENNAMAXAREACAR 9.678367 LAYER Metal2 ; + PORT + LAYER Metal2 ; + RECT 238.645 0 238.905 0.26 ; + END + END A_BIST_BM[6] + PIN A_BIST_BM[1] + DIRECTION INPUT ; + USE SIGNAL ; + ANTENNAPARTIALMETALAREA 1.7602 LAYER Metal2 ; + ANTENNAMODEL OXIDE1 ; + ANTENNAGATEAREA 0.20085 LAYER Metal2 ; + ANTENNAMAXAREACAR 9.678367 LAYER Metal2 ; + PORT + LAYER Metal2 ; + RECT 22.265 0 22.525 0.26 ; + END + END A_BIST_BM[1] + PIN A_DOUT[6] + DIRECTION OUTPUT ; + USE SIGNAL ; + ANTENNAPARTIALMETALAREA 4.8256 LAYER Metal2 ; + ANTENNADIFFAREA 0.988 LAYER Metal2 ; + PORT + LAYER Metal2 ; + RECT 224.21 0 224.47 0.26 ; + END + END A_DOUT[6] + PIN A_DOUT[1] + DIRECTION OUTPUT ; + USE SIGNAL ; + ANTENNAPARTIALMETALAREA 4.8256 LAYER Metal2 ; + ANTENNADIFFAREA 0.988 LAYER Metal2 ; + PORT + LAYER Metal2 ; + RECT 36.7 0 36.96 0.26 ; + END + END A_DOUT[1] + PIN B_DIN[6] + DIRECTION INPUT ; + USE SIGNAL ; + ANTENNAPARTIALMETALAREA 2.925 LAYER Metal2 ; + ANTENNAMODEL OXIDE1 ; + ANTENNAGATEAREA 0.20085 LAYER Metal2 ; + ANTENNAMAXAREACAR 15.469256 LAYER Metal2 ; + PORT + LAYER Metal2 ; + RECT 233.9 0 234.16 0.26 ; + END + END B_DIN[6] + PIN B_DIN[1] + DIRECTION INPUT ; + USE SIGNAL ; + ANTENNAPARTIALMETALAREA 2.925 LAYER Metal2 ; + ANTENNAMODEL OXIDE1 ; + ANTENNAGATEAREA 0.20085 LAYER Metal2 ; + ANTENNAMAXAREACAR 15.469256 LAYER Metal2 ; + PORT + LAYER Metal2 ; + RECT 27.01 0 27.27 0.26 ; + END + END B_DIN[1] + PIN B_BIST_DIN[6] + DIRECTION INPUT ; + USE SIGNAL ; + ANTENNAPARTIALMETALAREA 2.9445 LAYER Metal2 ; + ANTENNAMODEL OXIDE1 ; + ANTENNAGATEAREA 0.20085 LAYER Metal2 ; + ANTENNAMAXAREACAR 15.929052 LAYER Metal2 ; + PORT + LAYER Metal2 ; + RECT 232.37 0 232.63 0.26 ; + END + END B_BIST_DIN[6] + PIN B_BIST_DIN[1] + DIRECTION INPUT ; + USE SIGNAL ; + ANTENNAPARTIALMETALAREA 2.9445 LAYER Metal2 ; + ANTENNAMODEL OXIDE1 ; + ANTENNAGATEAREA 0.20085 LAYER Metal2 ; + ANTENNAMAXAREACAR 15.929052 LAYER Metal2 ; + PORT + LAYER Metal2 ; + RECT 28.54 0 28.8 0.26 ; + END + END B_BIST_DIN[1] + PIN B_BM[6] + DIRECTION INPUT ; + USE SIGNAL ; + ANTENNAPARTIALMETALAREA 0.7007 LAYER Metal2 ; + ANTENNAMODEL OXIDE1 ; + ANTENNAGATEAREA 0.20085 LAYER Metal2 ; + ANTENNAMAXAREACAR 4.394822 LAYER Metal2 ; + PORT + LAYER Metal2 ; + RECT 225.385 0 225.645 0.26 ; + END + END B_BM[6] + PIN B_BM[1] + DIRECTION INPUT ; + USE SIGNAL ; + ANTENNAPARTIALMETALAREA 0.7007 LAYER Metal2 ; + ANTENNAMODEL OXIDE1 ; + ANTENNAGATEAREA 0.20085 LAYER Metal2 ; + ANTENNAMAXAREACAR 4.394822 LAYER Metal2 ; + PORT + LAYER Metal2 ; + RECT 35.525 0 35.785 0.26 ; + END + END B_BM[1] + PIN B_BIST_BM[6] + DIRECTION INPUT ; + USE SIGNAL ; + ANTENNAPARTIALMETALAREA 0.7007 LAYER Metal2 ; + ANTENNAMODEL OXIDE1 ; + ANTENNAGATEAREA 0.20085 LAYER Metal2 ; + ANTENNAMAXAREACAR 4.394822 LAYER Metal2 ; + PORT + LAYER Metal2 ; + RECT 226.915 0 227.175 0.26 ; + END + END B_BIST_BM[6] + PIN B_BIST_BM[1] + DIRECTION INPUT ; + USE SIGNAL ; + ANTENNAPARTIALMETALAREA 0.7007 LAYER Metal2 ; + ANTENNAMODEL OXIDE1 ; + ANTENNAGATEAREA 0.20085 LAYER Metal2 ; + ANTENNAMAXAREACAR 4.394822 LAYER Metal2 ; + PORT + LAYER Metal2 ; + RECT 33.995 0 34.255 0.26 ; + END + END B_BIST_BM[1] + PIN B_DOUT[6] + DIRECTION OUTPUT ; + USE SIGNAL ; + ANTENNAPARTIALMETALAREA 4.836 LAYER Metal2 ; + ANTENNADIFFAREA 0.988 LAYER Metal2 ; + PORT + LAYER Metal2 ; + RECT 241.04 0 241.3 0.26 ; + END + END B_DOUT[6] + PIN B_DOUT[1] + DIRECTION OUTPUT ; + USE SIGNAL ; + ANTENNAPARTIALMETALAREA 4.836 LAYER Metal2 ; + ANTENNADIFFAREA 0.988 LAYER Metal2 ; + PORT + LAYER Metal2 ; + RECT 19.87 0 20.13 0.26 ; + END + END B_DOUT[1] + PIN A_DIN[7] + DIRECTION INPUT ; + USE SIGNAL ; + ANTENNAPARTIALMETALAREA 3.9091 LAYER Metal2 ; + ANTENNAMODEL OXIDE1 ; + ANTENNAGATEAREA 0.20085 LAYER Metal2 ; + ANTENNAMAXAREACAR 20.368932 LAYER Metal2 ; + PORT + LAYER Metal2 ; + RECT 249.03 0 249.29 0.26 ; + END + END A_DIN[7] + PIN A_DIN[0] + DIRECTION INPUT ; + USE SIGNAL ; + ANTENNAPARTIALMETALAREA 3.9091 LAYER Metal2 ; + ANTENNAMODEL OXIDE1 ; + ANTENNAGATEAREA 0.20085 LAYER Metal2 ; + ANTENNAMAXAREACAR 20.368932 LAYER Metal2 ; + PORT + LAYER Metal2 ; + RECT 11.88 0 12.14 0.26 ; + END + END A_DIN[0] + PIN A_BIST_DIN[7] + DIRECTION INPUT ; + USE SIGNAL ; + ANTENNAPARTIALMETALAREA 4.136375 LAYER Metal2 ; + ANTENNAMODEL OXIDE1 ; + ANTENNAGATEAREA 0.20085 LAYER Metal2 ; + ANTENNAMAXAREACAR 21.874907 LAYER Metal2 ; + PORT + LAYER Metal2 ; + RECT 249.54 0 249.8 0.26 ; + END + END A_BIST_DIN[7] + PIN A_BIST_DIN[0] + DIRECTION INPUT ; + USE SIGNAL ; + ANTENNAPARTIALMETALAREA 4.136375 LAYER Metal2 ; + ANTENNAMODEL OXIDE1 ; + ANTENNAGATEAREA 0.20085 LAYER Metal2 ; + ANTENNAMAXAREACAR 21.874907 LAYER Metal2 ; + PORT + LAYER Metal2 ; + RECT 11.37 0 11.63 0.26 ; + END + END A_BIST_DIN[0] + PIN A_BM[7] + DIRECTION INPUT ; + USE SIGNAL ; + ANTENNAPARTIALMETALAREA 1.7264 LAYER Metal2 ; + ANTENNAMODEL OXIDE1 ; + ANTENNAGATEAREA 0.20085 LAYER Metal2 ; + ANTENNAMAXAREACAR 9.501618 LAYER Metal2 ; + PORT + LAYER Metal2 ; + RECT 257.7 0 257.96 0.26 ; + END + END A_BM[7] + PIN A_BM[0] + DIRECTION INPUT ; + USE SIGNAL ; + ANTENNAPARTIALMETALAREA 1.7264 LAYER Metal2 ; + ANTENNAMODEL OXIDE1 ; + ANTENNAGATEAREA 0.20085 LAYER Metal2 ; + ANTENNAMAXAREACAR 9.501618 LAYER Metal2 ; + PORT + LAYER Metal2 ; + RECT 3.21 0 3.47 0.26 ; + END + END A_BM[0] + PIN A_BIST_BM[7] + DIRECTION INPUT ; + USE SIGNAL ; + ANTENNAPARTIALMETALAREA 1.7602 LAYER Metal2 ; + ANTENNAMODEL OXIDE1 ; + ANTENNAGATEAREA 0.20085 LAYER Metal2 ; + ANTENNAMAXAREACAR 9.678367 LAYER Metal2 ; + PORT + LAYER Metal2 ; + RECT 256.325 0 256.585 0.26 ; + END + END A_BIST_BM[7] + PIN A_BIST_BM[0] + DIRECTION INPUT ; + USE SIGNAL ; + ANTENNAPARTIALMETALAREA 1.7602 LAYER Metal2 ; + ANTENNAMODEL OXIDE1 ; + ANTENNAGATEAREA 0.20085 LAYER Metal2 ; + ANTENNAMAXAREACAR 9.678367 LAYER Metal2 ; + PORT + LAYER Metal2 ; + RECT 4.585 0 4.845 0.26 ; + END + END A_BIST_BM[0] + PIN A_DOUT[7] + DIRECTION OUTPUT ; + USE SIGNAL ; + ANTENNAPARTIALMETALAREA 4.8256 LAYER Metal2 ; + ANTENNADIFFAREA 0.988 LAYER Metal2 ; + PORT + LAYER Metal2 ; + RECT 241.89 0 242.15 0.26 ; + END + END A_DOUT[7] + PIN A_DOUT[0] + DIRECTION OUTPUT ; + USE SIGNAL ; + ANTENNAPARTIALMETALAREA 4.8256 LAYER Metal2 ; + ANTENNADIFFAREA 0.988 LAYER Metal2 ; + PORT + LAYER Metal2 ; + RECT 19.02 0 19.28 0.26 ; + END + END A_DOUT[0] + PIN B_DIN[7] + DIRECTION INPUT ; + USE SIGNAL ; + ANTENNAPARTIALMETALAREA 2.925 LAYER Metal2 ; + ANTENNAMODEL OXIDE1 ; + ANTENNAGATEAREA 0.20085 LAYER Metal2 ; + ANTENNAMAXAREACAR 15.469256 LAYER Metal2 ; + PORT + LAYER Metal2 ; + RECT 251.58 0 251.84 0.26 ; + END + END B_DIN[7] + PIN B_DIN[0] + DIRECTION INPUT ; + USE SIGNAL ; + ANTENNAPARTIALMETALAREA 2.925 LAYER Metal2 ; + ANTENNAMODEL OXIDE1 ; + ANTENNAGATEAREA 0.20085 LAYER Metal2 ; + ANTENNAMAXAREACAR 15.469256 LAYER Metal2 ; + PORT + LAYER Metal2 ; + RECT 9.33 0 9.59 0.26 ; + END + END B_DIN[0] + PIN B_BIST_DIN[7] + DIRECTION INPUT ; + USE SIGNAL ; + ANTENNAPARTIALMETALAREA 2.9445 LAYER Metal2 ; + ANTENNAMODEL OXIDE1 ; + ANTENNAGATEAREA 0.20085 LAYER Metal2 ; + ANTENNAMAXAREACAR 15.929052 LAYER Metal2 ; + PORT + LAYER Metal2 ; + RECT 250.05 0 250.31 0.26 ; + END + END B_BIST_DIN[7] + PIN B_BIST_DIN[0] + DIRECTION INPUT ; + USE SIGNAL ; + ANTENNAPARTIALMETALAREA 2.9445 LAYER Metal2 ; + ANTENNAMODEL OXIDE1 ; + ANTENNAGATEAREA 0.20085 LAYER Metal2 ; + ANTENNAMAXAREACAR 15.929052 LAYER Metal2 ; + PORT + LAYER Metal2 ; + RECT 10.86 0 11.12 0.26 ; + END + END B_BIST_DIN[0] + PIN B_BM[7] + DIRECTION INPUT ; + USE SIGNAL ; + ANTENNAPARTIALMETALAREA 0.7007 LAYER Metal2 ; + ANTENNAMODEL OXIDE1 ; + ANTENNAGATEAREA 0.20085 LAYER Metal2 ; + ANTENNAMAXAREACAR 4.394822 LAYER Metal2 ; + PORT + LAYER Metal2 ; + RECT 243.065 0 243.325 0.26 ; + END + END B_BM[7] + PIN B_BM[0] + DIRECTION INPUT ; + USE SIGNAL ; + ANTENNAPARTIALMETALAREA 0.7007 LAYER Metal2 ; + ANTENNAMODEL OXIDE1 ; + ANTENNAGATEAREA 0.20085 LAYER Metal2 ; + ANTENNAMAXAREACAR 4.394822 LAYER Metal2 ; + PORT + LAYER Metal2 ; + RECT 17.845 0 18.105 0.26 ; + END + END B_BM[0] + PIN B_BIST_BM[7] + DIRECTION INPUT ; + USE SIGNAL ; + ANTENNAPARTIALMETALAREA 0.7007 LAYER Metal2 ; + ANTENNAMODEL OXIDE1 ; + ANTENNAGATEAREA 0.20085 LAYER Metal2 ; + ANTENNAMAXAREACAR 4.394822 LAYER Metal2 ; + PORT + LAYER Metal2 ; + RECT 244.595 0 244.855 0.26 ; + END + END B_BIST_BM[7] + PIN B_BIST_BM[0] + DIRECTION INPUT ; + USE SIGNAL ; + ANTENNAPARTIALMETALAREA 0.7007 LAYER Metal2 ; + ANTENNAMODEL OXIDE1 ; + ANTENNAGATEAREA 0.20085 LAYER Metal2 ; + ANTENNAMAXAREACAR 4.394822 LAYER Metal2 ; + PORT + LAYER Metal2 ; + RECT 16.315 0 16.575 0.26 ; + END + END B_BIST_BM[0] + PIN B_DOUT[7] + DIRECTION OUTPUT ; + USE SIGNAL ; + ANTENNAPARTIALMETALAREA 4.836 LAYER Metal2 ; + ANTENNADIFFAREA 0.988 LAYER Metal2 ; + PORT + LAYER Metal2 ; + RECT 258.72 0 258.98 0.26 ; + END + END B_DOUT[7] + PIN B_DOUT[0] + DIRECTION OUTPUT ; + USE SIGNAL ; + ANTENNAPARTIALMETALAREA 4.836 LAYER Metal2 ; + ANTENNADIFFAREA 0.988 LAYER Metal2 ; + PORT + LAYER Metal2 ; + RECT 2.19 0 2.45 0.26 ; + END + END B_DOUT[0] + PIN A_ADDR[0] + DIRECTION INPUT ; + USE SIGNAL ; + ANTENNAPARTIALMETALAREA 8.7685 LAYER Metal2 ; + ANTENNAMODEL OXIDE1 ; + ANTENNAGATEAREA 0.20085 LAYER Metal2 ; + ANTENNAMAXAREACAR 44.563107 LAYER Metal2 ; + PORT + LAYER Metal2 ; + RECT 146.675 0 146.935 0.26 ; + END + END A_ADDR[0] + PIN A_BIST_ADDR[0] + DIRECTION INPUT ; + USE SIGNAL ; + ANTENNAPARTIALMETALAREA 9.8293 LAYER Metal2 ; + ANTENNAMODEL OXIDE1 ; + ANTENNAGATEAREA 0.20085 LAYER Metal2 ; + ANTENNAMAXAREACAR 49.84466 LAYER Metal2 ; + PORT + LAYER Metal2 ; + RECT 152.285 0 152.545 0.26 ; + END + END A_BIST_ADDR[0] + PIN B_ADDR[0] + DIRECTION INPUT ; + USE SIGNAL ; + ANTENNAPARTIALMETALAREA 8.7685 LAYER Metal2 ; + ANTENNAMODEL OXIDE1 ; + ANTENNAGATEAREA 0.20085 LAYER Metal2 ; + ANTENNAMAXAREACAR 44.563107 LAYER Metal2 ; + PORT + LAYER Metal2 ; + RECT 114.235 0 114.495 0.26 ; + END + END B_ADDR[0] + PIN B_BIST_ADDR[0] + DIRECTION INPUT ; + USE SIGNAL ; + ANTENNAPARTIALMETALAREA 9.8293 LAYER Metal2 ; + ANTENNAMODEL OXIDE1 ; + ANTENNAGATEAREA 0.20085 LAYER Metal2 ; + ANTENNAMAXAREACAR 49.84466 LAYER Metal2 ; + PORT + LAYER Metal2 ; + RECT 108.625 0 108.885 0.26 ; + END + END B_BIST_ADDR[0] + PIN A_ADDR[1] + DIRECTION INPUT ; + USE SIGNAL ; + ANTENNAPARTIALMETALAREA 11.0851 LAYER Metal2 ; + ANTENNAMODEL OXIDE1 ; + ANTENNAGATEAREA 0.20085 LAYER Metal2 ; + ANTENNAMAXAREACAR 56.097087 LAYER Metal2 ; + PORT + LAYER Metal2 ; + RECT 147.185 0 147.445 0.26 ; + END + END A_ADDR[1] + PIN A_BIST_ADDR[1] + DIRECTION INPUT ; + USE SIGNAL ; + ANTENNAPARTIALMETALAREA 12.1459 LAYER Metal2 ; + ANTENNAMODEL OXIDE1 ; + ANTENNAGATEAREA 0.20085 LAYER Metal2 ; + ANTENNAMAXAREACAR 61.378641 LAYER Metal2 ; + PORT + LAYER Metal2 ; + RECT 152.795 0 153.055 0.26 ; + END + END A_BIST_ADDR[1] + PIN B_ADDR[1] + DIRECTION INPUT ; + USE SIGNAL ; + ANTENNAPARTIALMETALAREA 11.0851 LAYER Metal2 ; + ANTENNAMODEL OXIDE1 ; + ANTENNAGATEAREA 0.20085 LAYER Metal2 ; + ANTENNAMAXAREACAR 56.097087 LAYER Metal2 ; + PORT + LAYER Metal2 ; + RECT 113.725 0 113.985 0.26 ; + END + END B_ADDR[1] + PIN B_BIST_ADDR[1] + DIRECTION INPUT ; + USE SIGNAL ; + ANTENNAPARTIALMETALAREA 12.1459 LAYER Metal2 ; + ANTENNAMODEL OXIDE1 ; + ANTENNAGATEAREA 0.20085 LAYER Metal2 ; + ANTENNAMAXAREACAR 61.378641 LAYER Metal2 ; + PORT + LAYER Metal2 ; + RECT 108.115 0 108.375 0.26 ; + END + END B_BIST_ADDR[1] + PIN A_ADDR[2] + DIRECTION INPUT ; + USE SIGNAL ; + ANTENNAPARTIALMETALAREA 13.0819 LAYER Metal2 ; + ANTENNAPARTIALMETALAREA 1.5246 LAYER Metal3 ; + ANTENNAPARTIALCUTAREA 0.0722 LAYER Via2 ; + ANTENNAMODEL OXIDE1 ; + ANTENNAGATEAREA 0.20085 LAYER Metal3 ; + ANTENNAMAXAREACAR 9.415982 LAYER Metal3 ; + PORT + LAYER Metal2 ; + RECT 155.855 0 156.115 0.26 ; + END + END A_ADDR[2] + PIN A_BIST_ADDR[2] + DIRECTION INPUT ; + USE SIGNAL ; + ANTENNAPARTIALMETALAREA 13.0819 LAYER Metal2 ; + ANTENNAPARTIALMETALAREA 1.0962 LAYER Metal3 ; + ANTENNAPARTIALCUTAREA 0.0722 LAYER Via2 ; + ANTENNAMODEL OXIDE1 ; + ANTENNAGATEAREA 0.20085 LAYER Metal3 ; + ANTENNAMAXAREACAR 7.813791 LAYER Metal3 ; + PORT + LAYER Metal2 ; + RECT 156.365 0 156.625 0.26 ; + END + END A_BIST_ADDR[2] + PIN B_ADDR[2] + DIRECTION INPUT ; + USE SIGNAL ; + ANTENNAPARTIALMETALAREA 13.0819 LAYER Metal2 ; + ANTENNAPARTIALMETALAREA 1.5246 LAYER Metal3 ; + ANTENNAPARTIALCUTAREA 0.0722 LAYER Via2 ; + ANTENNAMODEL OXIDE1 ; + ANTENNAGATEAREA 0.20085 LAYER Metal3 ; + ANTENNAMAXAREACAR 9.415982 LAYER Metal3 ; + PORT + LAYER Metal2 ; + RECT 105.055 0 105.315 0.26 ; + END + END B_ADDR[2] + PIN B_BIST_ADDR[2] + DIRECTION INPUT ; + USE SIGNAL ; + ANTENNAPARTIALMETALAREA 13.0819 LAYER Metal2 ; + ANTENNAPARTIALMETALAREA 1.0962 LAYER Metal3 ; + ANTENNAPARTIALCUTAREA 0.0722 LAYER Via2 ; + ANTENNAMODEL OXIDE1 ; + ANTENNAGATEAREA 0.20085 LAYER Metal3 ; + ANTENNAMAXAREACAR 7.813791 LAYER Metal3 ; + PORT + LAYER Metal2 ; + RECT 104.545 0 104.805 0.26 ; + END + END B_BIST_ADDR[2] + PIN A_ADDR[3] + DIRECTION INPUT ; + USE SIGNAL ; + ANTENNAPARTIALMETALAREA 13.0819 LAYER Metal2 ; + ANTENNAPARTIALMETALAREA 3.9459 LAYER Metal3 ; + ANTENNAPARTIALCUTAREA 0.0722 LAYER Via2 ; + ANTENNAMODEL OXIDE1 ; + ANTENNAGATEAREA 0.20085 LAYER Metal3 ; + ANTENNAMAXAREACAR 21.471247 LAYER Metal3 ; + PORT + LAYER Metal2 ; + RECT 154.835 0 155.095 0.26 ; + END + END A_ADDR[3] + PIN A_BIST_ADDR[3] + DIRECTION INPUT ; + USE SIGNAL ; + ANTENNAPARTIALMETALAREA 13.0819 LAYER Metal2 ; + ANTENNAPARTIALMETALAREA 3.7317 LAYER Metal3 ; + ANTENNAPARTIALCUTAREA 0.0722 LAYER Via2 ; + ANTENNAMODEL OXIDE1 ; + ANTENNAGATEAREA 0.20085 LAYER Metal3 ; + ANTENNAMAXAREACAR 20.935524 LAYER Metal3 ; + PORT + LAYER Metal2 ; + RECT 155.345 0 155.605 0.26 ; + END + END A_BIST_ADDR[3] + PIN B_ADDR[3] + DIRECTION INPUT ; + USE SIGNAL ; + ANTENNAPARTIALMETALAREA 13.0819 LAYER Metal2 ; + ANTENNAPARTIALMETALAREA 3.9459 LAYER Metal3 ; + ANTENNAPARTIALCUTAREA 0.0722 LAYER Via2 ; + ANTENNAMODEL OXIDE1 ; + ANTENNAGATEAREA 0.20085 LAYER Metal3 ; + ANTENNAMAXAREACAR 21.471247 LAYER Metal3 ; + PORT + LAYER Metal2 ; + RECT 106.075 0 106.335 0.26 ; + END + END B_ADDR[3] + PIN B_BIST_ADDR[3] + DIRECTION INPUT ; + USE SIGNAL ; + ANTENNAPARTIALMETALAREA 13.0819 LAYER Metal2 ; + ANTENNAPARTIALMETALAREA 3.7317 LAYER Metal3 ; + ANTENNAPARTIALCUTAREA 0.0722 LAYER Via2 ; + ANTENNAMODEL OXIDE1 ; + ANTENNAGATEAREA 0.20085 LAYER Metal3 ; + ANTENNAMAXAREACAR 20.935524 LAYER Metal3 ; + PORT + LAYER Metal2 ; + RECT 105.565 0 105.825 0.26 ; + END + END B_BIST_ADDR[3] + PIN A_ADDR[4] + DIRECTION INPUT ; + USE SIGNAL ; + ANTENNAPARTIALMETALAREA 14.7329 LAYER Metal2 ; + ANTENNAMODEL OXIDE1 ; + ANTENNAGATEAREA 0.20085 LAYER Metal2 ; + ANTENNAMAXAREACAR 74.2589 LAYER Metal2 ; + PORT + LAYER Metal2 ; + RECT 135.455 0 135.715 0.26 ; + END + END A_ADDR[4] + PIN A_BIST_ADDR[4] + DIRECTION INPUT ; + USE SIGNAL ; + ANTENNAPARTIALMETALAREA 14.4677 LAYER Metal2 ; + ANTENNAMODEL OXIDE1 ; + ANTENNAGATEAREA 0.20085 LAYER Metal2 ; + ANTENNAMAXAREACAR 72.938511 LAYER Metal2 ; + PORT + LAYER Metal2 ; + RECT 135.965 0 136.225 0.26 ; + END + END A_BIST_ADDR[4] + PIN B_ADDR[4] + DIRECTION INPUT ; + USE SIGNAL ; + ANTENNAPARTIALMETALAREA 14.7329 LAYER Metal2 ; + ANTENNAMODEL OXIDE1 ; + ANTENNAGATEAREA 0.20085 LAYER Metal2 ; + ANTENNAMAXAREACAR 74.2589 LAYER Metal2 ; + PORT + LAYER Metal2 ; + RECT 125.455 0 125.715 0.26 ; + END + END B_ADDR[4] + PIN B_BIST_ADDR[4] + DIRECTION INPUT ; + USE SIGNAL ; + ANTENNAPARTIALMETALAREA 14.4677 LAYER Metal2 ; + ANTENNAMODEL OXIDE1 ; + ANTENNAGATEAREA 0.20085 LAYER Metal2 ; + ANTENNAMAXAREACAR 72.938511 LAYER Metal2 ; + PORT + LAYER Metal2 ; + RECT 124.945 0 125.205 0.26 ; + END + END B_BIST_ADDR[4] + PIN A_ADDR[5] + DIRECTION INPUT ; + USE SIGNAL ; + ANTENNAPARTIALMETALAREA 13.2691 LAYER Metal2 ; + ANTENNAMODEL OXIDE1 ; + ANTENNAGATEAREA 0.20085 LAYER Metal2 ; + ANTENNAMAXAREACAR 66.970874 LAYER Metal2 ; + PORT + LAYER Metal2 ; + RECT 134.435 0 134.695 0.26 ; + END + END A_ADDR[5] + PIN A_BIST_ADDR[5] + DIRECTION INPUT ; + USE SIGNAL ; + ANTENNAPARTIALMETALAREA 12.9937 LAYER Metal2 ; + ANTENNAMODEL OXIDE1 ; + ANTENNAGATEAREA 0.20085 LAYER Metal2 ; + ANTENNAMAXAREACAR 65.599701 LAYER Metal2 ; + PORT + LAYER Metal2 ; + RECT 134.945 0 135.205 0.26 ; + END + END A_BIST_ADDR[5] + PIN B_ADDR[5] + DIRECTION INPUT ; + USE SIGNAL ; + ANTENNAPARTIALMETALAREA 13.2691 LAYER Metal2 ; + ANTENNAMODEL OXIDE1 ; + ANTENNAGATEAREA 0.20085 LAYER Metal2 ; + ANTENNAMAXAREACAR 66.970874 LAYER Metal2 ; + PORT + LAYER Metal2 ; + RECT 126.475 0 126.735 0.26 ; + END + END B_ADDR[5] + PIN B_BIST_ADDR[5] + DIRECTION INPUT ; + USE SIGNAL ; + ANTENNAPARTIALMETALAREA 12.9937 LAYER Metal2 ; + ANTENNAMODEL OXIDE1 ; + ANTENNAGATEAREA 0.20085 LAYER Metal2 ; + ANTENNAMAXAREACAR 65.599701 LAYER Metal2 ; + PORT + LAYER Metal2 ; + RECT 125.965 0 126.225 0.26 ; + END + END B_BIST_ADDR[5] + PIN A_ADDR[6] + DIRECTION INPUT ; + USE SIGNAL ; + ANTENNAPARTIALMETALAREA 14.3819 LAYER Metal2 ; + ANTENNAMODEL OXIDE1 ; + ANTENNAGATEAREA 0.20085 LAYER Metal2 ; + ANTENNAMAXAREACAR 72.511327 LAYER Metal2 ; + PORT + LAYER Metal2 ; + RECT 158.405 0 158.665 0.26 ; + END + END A_ADDR[6] + PIN A_BIST_ADDR[6] + DIRECTION INPUT ; + USE SIGNAL ; + ANTENNAPARTIALMETALAREA 14.1167 LAYER Metal2 ; + ANTENNAMODEL OXIDE1 ; + ANTENNAGATEAREA 0.20085 LAYER Metal2 ; + ANTENNAMAXAREACAR 71.190939 LAYER Metal2 ; + PORT + LAYER Metal2 ; + RECT 157.895 0 158.155 0.26 ; + END + END A_BIST_ADDR[6] + PIN B_ADDR[6] + DIRECTION INPUT ; + USE SIGNAL ; + ANTENNAPARTIALMETALAREA 14.3819 LAYER Metal2 ; + ANTENNAMODEL OXIDE1 ; + ANTENNAGATEAREA 0.20085 LAYER Metal2 ; + ANTENNAMAXAREACAR 72.511327 LAYER Metal2 ; + PORT + LAYER Metal2 ; + RECT 102.505 0 102.765 0.26 ; + END + END B_ADDR[6] + PIN B_BIST_ADDR[6] + DIRECTION INPUT ; + USE SIGNAL ; + ANTENNAPARTIALMETALAREA 14.1167 LAYER Metal2 ; + ANTENNAMODEL OXIDE1 ; + ANTENNAGATEAREA 0.20085 LAYER Metal2 ; + ANTENNAMAXAREACAR 71.190939 LAYER Metal2 ; + PORT + LAYER Metal2 ; + RECT 103.015 0 103.275 0.26 ; + END + END B_BIST_ADDR[6] + PIN A_ADDR[7] + DIRECTION INPUT ; + USE SIGNAL ; + ANTENNAPARTIALMETALAREA 16.3761 LAYER Metal2 ; + ANTENNAMODEL OXIDE1 ; + ANTENNAGATEAREA 0.20085 LAYER Metal2 ; + ANTENNAMAXAREACAR 82.440129 LAYER Metal2 ; + PORT + LAYER Metal2 ; + RECT 157.385 0 157.645 0.26 ; + END + END A_ADDR[7] + PIN A_BIST_ADDR[7] + DIRECTION INPUT ; + USE SIGNAL ; + ANTENNAPARTIALMETALAREA 16.1109 LAYER Metal2 ; + ANTENNAMODEL OXIDE1 ; + ANTENNAGATEAREA 0.20085 LAYER Metal2 ; + ANTENNAMAXAREACAR 81.119741 LAYER Metal2 ; + PORT + LAYER Metal2 ; + RECT 156.875 0 157.135 0.26 ; + END + END A_BIST_ADDR[7] + PIN B_ADDR[7] + DIRECTION INPUT ; + USE SIGNAL ; + ANTENNAPARTIALMETALAREA 16.3761 LAYER Metal2 ; + ANTENNAMODEL OXIDE1 ; + ANTENNAGATEAREA 0.20085 LAYER Metal2 ; + ANTENNAMAXAREACAR 82.440129 LAYER Metal2 ; + PORT + LAYER Metal2 ; + RECT 103.525 0 103.785 0.26 ; + END + END B_ADDR[7] + PIN B_BIST_ADDR[7] + DIRECTION INPUT ; + USE SIGNAL ; + ANTENNAPARTIALMETALAREA 16.1109 LAYER Metal2 ; + ANTENNAMODEL OXIDE1 ; + ANTENNAGATEAREA 0.20085 LAYER Metal2 ; + ANTENNAMAXAREACAR 81.119741 LAYER Metal2 ; + PORT + LAYER Metal2 ; + RECT 104.035 0 104.295 0.26 ; + END + END B_BIST_ADDR[7] + PIN A_ADDR[8] + DIRECTION INPUT ; + USE SIGNAL ; + ANTENNAPARTIALMETALAREA 14.4422 LAYER Metal2 ; + ANTENNAMODEL OXIDE1 ; + ANTENNAGATEAREA 0.20085 LAYER Metal2 ; + ANTENNAMAXAREACAR 72.811551 LAYER Metal2 ; + PORT + LAYER Metal2 ; + RECT 160.955 0 161.215 0.26 ; + END + END A_ADDR[8] + PIN A_BIST_ADDR[8] + DIRECTION INPUT ; + USE SIGNAL ; + ANTENNAPARTIALMETALAREA 14.1872 LAYER Metal2 ; + ANTENNAMODEL OXIDE1 ; + ANTENNAGATEAREA 0.20085 LAYER Metal2 ; + ANTENNAMAXAREACAR 71.541947 LAYER Metal2 ; + PORT + LAYER Metal2 ; + RECT 161.465 0 161.725 0.26 ; + END + END A_BIST_ADDR[8] + PIN B_ADDR[8] + DIRECTION INPUT ; + USE SIGNAL ; + ANTENNAPARTIALMETALAREA 14.4422 LAYER Metal2 ; + ANTENNAMODEL OXIDE1 ; + ANTENNAGATEAREA 0.20085 LAYER Metal2 ; + ANTENNAMAXAREACAR 72.811551 LAYER Metal2 ; + PORT + LAYER Metal2 ; + RECT 99.955 0 100.215 0.26 ; + END + END B_ADDR[8] + PIN B_BIST_ADDR[8] + DIRECTION INPUT ; + USE SIGNAL ; + ANTENNAPARTIALMETALAREA 14.1872 LAYER Metal2 ; + ANTENNAMODEL OXIDE1 ; + ANTENNAGATEAREA 0.20085 LAYER Metal2 ; + ANTENNAMAXAREACAR 71.541947 LAYER Metal2 ; + PORT + LAYER Metal2 ; + RECT 99.445 0 99.705 0.26 ; + END + END B_BIST_ADDR[8] + PIN A_CLK + DIRECTION INPUT ; + USE SIGNAL ; + ANTENNAPARTIALMETALAREA 4.0547 LAYER Metal2 ; + ANTENNAMODEL OXIDE1 ; + ANTENNAGATEAREA 0.20085 LAYER Metal2 ; + ANTENNAMAXAREACAR 21.093851 LAYER Metal2 ; + PORT + LAYER Metal2 ; + RECT 145.145 0 145.405 0.26 ; + END + END A_CLK + PIN A_REN + DIRECTION INPUT ; + USE SIGNAL ; + ANTENNAPARTIALMETALAREA 3.98465 LAYER Metal2 ; + ANTENNAMODEL OXIDE1 ; + ANTENNAGATEAREA 0.20085 LAYER Metal2 ; + ANTENNAMAXAREACAR 20.745083 LAYER Metal2 ; + PORT + LAYER Metal2 ; + RECT 148.715 0 148.975 0.26 ; + END + END A_REN + PIN A_WEN + DIRECTION INPUT ; + USE SIGNAL ; + ANTENNAPARTIALMETALAREA 2.8847 LAYER Metal2 ; + ANTENNAMODEL OXIDE1 ; + ANTENNAGATEAREA 0.20085 LAYER Metal2 ; + ANTENNAMAXAREACAR 15.268608 LAYER Metal2 ; + PORT + LAYER Metal2 ; + RECT 148.205 0 148.465 0.26 ; + END + END A_WEN + PIN A_MEN + DIRECTION INPUT ; + USE SIGNAL ; + ANTENNAPARTIALMETALAREA 3.0247 LAYER Metal2 ; + ANTENNAMODEL OXIDE1 ; + ANTENNAGATEAREA 0.20085 LAYER Metal2 ; + ANTENNAMAXAREACAR 15.965646 LAYER Metal2 ; + PORT + LAYER Metal2 ; + RECT 145.655 0 145.915 0.26 ; + END + END A_MEN + PIN A_DLY + DIRECTION INPUT ; + USE SIGNAL ; + ANTENNAPARTIALMETALAREA 7.7792 LAYER Metal2 ; + ANTENNAMODEL OXIDE1 ; + ANTENNAGATEAREA 0.3367 LAYER Metal2 ; + ANTENNAMAXAREACAR 23.644788 LAYER Metal2 ; + PORT + LAYER Metal2 ; + RECT 166.055 0 166.315 0.26 ; + END + END A_DLY + PIN B_CLK + DIRECTION INPUT ; + USE SIGNAL ; + ANTENNAPARTIALMETALAREA 4.0547 LAYER Metal2 ; + ANTENNAMODEL OXIDE1 ; + ANTENNAGATEAREA 0.20085 LAYER Metal2 ; + ANTENNAMAXAREACAR 21.093851 LAYER Metal2 ; + PORT + LAYER Metal2 ; + RECT 115.765 0 116.025 0.26 ; + END + END B_CLK + PIN B_REN + DIRECTION INPUT ; + USE SIGNAL ; + ANTENNAPARTIALMETALAREA 3.98465 LAYER Metal2 ; + ANTENNAMODEL OXIDE1 ; + ANTENNAGATEAREA 0.20085 LAYER Metal2 ; + ANTENNAMAXAREACAR 20.745083 LAYER Metal2 ; + PORT + LAYER Metal2 ; + RECT 112.195 0 112.455 0.26 ; + END + END B_REN + PIN B_WEN + DIRECTION INPUT ; + USE SIGNAL ; + ANTENNAPARTIALMETALAREA 2.8847 LAYER Metal2 ; + ANTENNAMODEL OXIDE1 ; + ANTENNAGATEAREA 0.20085 LAYER Metal2 ; + ANTENNAMAXAREACAR 15.268608 LAYER Metal2 ; + PORT + LAYER Metal2 ; + RECT 112.705 0 112.965 0.26 ; + END + END B_WEN + PIN B_MEN + DIRECTION INPUT ; + USE SIGNAL ; + ANTENNAPARTIALMETALAREA 3.0247 LAYER Metal2 ; + ANTENNAMODEL OXIDE1 ; + ANTENNAGATEAREA 0.20085 LAYER Metal2 ; + ANTENNAMAXAREACAR 15.965646 LAYER Metal2 ; + PORT + LAYER Metal2 ; + RECT 115.255 0 115.515 0.26 ; + END + END B_MEN + PIN B_DLY + DIRECTION INPUT ; + USE SIGNAL ; + ANTENNAPARTIALMETALAREA 7.7792 LAYER Metal2 ; + ANTENNAMODEL OXIDE1 ; + ANTENNAGATEAREA 0.3367 LAYER Metal2 ; + ANTENNAMAXAREACAR 23.644788 LAYER Metal2 ; + PORT + LAYER Metal2 ; + RECT 94.855 0 95.115 0.26 ; + END + END B_DLY + PIN A_BIST_EN + DIRECTION INPUT ; + USE SIGNAL ; + ANTENNAPARTIALMETALAREA 4.0634 LAYER Metal2 ; + ANTENNAPARTIALMETALAREA 92.8757 LAYER Metal3 ; + ANTENNAPARTIALCUTAREA 0.0722 LAYER Via2 ; + ANTENNAMODEL OXIDE1 ; + ANTENNAGATEAREA 1.43 LAYER Metal2 ; + ANTENNAGATEAREA 10.3675 LAYER Metal3 ; + ANTENNAMAXAREACAR 3.266993 LAYER Metal2 ; + ANTENNAMAXAREACAR 20.129726 LAYER Metal3 ; + ANTENNAMAXCUTCAR 0.151469 LAYER Via2 ; + PORT + LAYER Metal2 ; + RECT 147.695 0 147.955 0.26 ; + END + END A_BIST_EN + PIN A_BIST_CLK + DIRECTION INPUT ; + USE SIGNAL ; + ANTENNAPARTIALMETALAREA 4.1639 LAYER Metal2 ; + ANTENNAMODEL OXIDE1 ; + ANTENNAGATEAREA 0.20085 LAYER Metal2 ; + ANTENNAMAXAREACAR 21.953448 LAYER Metal2 ; + PORT + LAYER Metal2 ; + RECT 143.615 0 143.875 0.26 ; + END + END A_BIST_CLK + PIN A_BIST_REN + DIRECTION INPUT ; + USE SIGNAL ; + ANTENNAPARTIALMETALAREA 4.1119 LAYER Metal2 ; + ANTENNAMODEL OXIDE1 ; + ANTENNAGATEAREA 0.20085 LAYER Metal2 ; + ANTENNAMAXAREACAR 21.694548 LAYER Metal2 ; + PORT + LAYER Metal2 ; + RECT 150.245 0 150.505 0.26 ; + END + END A_BIST_REN + PIN A_BIST_WEN + DIRECTION INPUT ; + USE SIGNAL ; + ANTENNAPARTIALMETALAREA 2.9051 LAYER Metal2 ; + ANTENNAMODEL OXIDE1 ; + ANTENNAGATEAREA 0.20085 LAYER Metal2 ; + ANTENNAMAXAREACAR 15.686084 LAYER Metal2 ; + PORT + LAYER Metal2 ; + RECT 149.735 0 149.995 0.26 ; + END + END A_BIST_WEN + PIN A_BIST_MEN + DIRECTION INPUT ; + USE SIGNAL ; + ANTENNAPARTIALMETALAREA 2.8977 LAYER Metal2 ; + ANTENNAMODEL OXIDE1 ; + ANTENNAGATEAREA 0.20085 LAYER Metal2 ; + ANTENNAMAXAREACAR 15.649241 LAYER Metal2 ; + PORT + LAYER Metal2 ; + RECT 144.125 0 144.385 0.26 ; + END + END A_BIST_MEN + PIN B_BIST_EN + DIRECTION INPUT ; + USE SIGNAL ; + ANTENNAPARTIALMETALAREA 3.9646 LAYER Metal2 ; + ANTENNAPARTIALMETALAREA 93.3149 LAYER Metal3 ; + ANTENNAPARTIALCUTAREA 0.0722 LAYER Via2 ; + ANTENNAMODEL OXIDE1 ; + ANTENNAGATEAREA 1.43 LAYER Metal2 ; + ANTENNAGATEAREA 10.3675 LAYER Metal3 ; + ANTENNAMAXAREACAR 3.197902 LAYER Metal2 ; + ANTENNAMAXAREACAR 20.172089 LAYER Metal3 ; + ANTENNAMAXCUTCAR 0.151469 LAYER Via2 ; + PORT + LAYER Metal2 ; + RECT 113.215 0 113.475 0.26 ; + END + END B_BIST_EN + PIN B_BIST_CLK + DIRECTION INPUT ; + USE SIGNAL ; + ANTENNAPARTIALMETALAREA 4.1639 LAYER Metal2 ; + ANTENNAMODEL OXIDE1 ; + ANTENNAGATEAREA 0.20085 LAYER Metal2 ; + ANTENNAMAXAREACAR 21.953448 LAYER Metal2 ; + PORT + LAYER Metal2 ; + RECT 117.295 0 117.555 0.26 ; + END + END B_BIST_CLK + PIN B_BIST_REN + DIRECTION INPUT ; + USE SIGNAL ; + ANTENNAPARTIALMETALAREA 4.1119 LAYER Metal2 ; + ANTENNAMODEL OXIDE1 ; + ANTENNAGATEAREA 0.20085 LAYER Metal2 ; + ANTENNAMAXAREACAR 21.694548 LAYER Metal2 ; + PORT + LAYER Metal2 ; + RECT 110.665 0 110.925 0.26 ; + END + END B_BIST_REN + PIN B_BIST_WEN + DIRECTION INPUT ; + USE SIGNAL ; + ANTENNAPARTIALMETALAREA 2.9051 LAYER Metal2 ; + ANTENNAMODEL OXIDE1 ; + ANTENNAGATEAREA 0.20085 LAYER Metal2 ; + ANTENNAMAXAREACAR 15.686084 LAYER Metal2 ; + PORT + LAYER Metal2 ; + RECT 111.175 0 111.435 0.26 ; + END + END B_BIST_WEN + PIN B_BIST_MEN + DIRECTION INPUT ; + USE SIGNAL ; + ANTENNAPARTIALMETALAREA 2.8977 LAYER Metal2 ; + ANTENNAMODEL OXIDE1 ; + ANTENNAGATEAREA 0.20085 LAYER Metal2 ; + ANTENNAMAXAREACAR 15.649241 LAYER Metal2 ; + PORT + LAYER Metal2 ; + RECT 116.785 0 117.045 0.26 ; + END + END B_BIST_MEN + OBS + LAYER Metal1 ; + RECT 0 0 261.17 219.77 ; + LAYER Metal2 ; + RECT 0.31 53.41 0.51 219.74 ; + RECT 1.135 219.01 1.335 219.74 ; + RECT 1.545 219.01 1.905 219.74 ; + RECT 2.115 219.01 2.315 219.74 ; + RECT 2.19 0.52 2.45 7.78 ; + RECT 2.7 0.3 2.96 5.235 ; + RECT 2.77 219.01 2.97 219.74 ; + RECT 3.21 0.52 3.47 5.57 ; + RECT 3.18 219.01 3.54 219.74 ; + RECT 3.835 219.01 4.035 219.74 ; + RECT 4.33 219.01 4.69 219.74 ; + RECT 4.585 0.52 4.845 6.28 ; + RECT 4.9 219.01 5.1 219.74 ; + RECT 5.555 219.01 5.755 219.74 ; + RECT 5.965 219.01 6.325 219.74 ; + RECT 6.535 219.01 6.735 219.74 ; + RECT 6.27 0.18 7.04 0.88 ; + RECT 7.19 219.01 7.39 219.74 ; + RECT 7.29 0.3 7.55 8.7 ; + RECT 7.6 219.01 7.96 219.74 ; + RECT 8.255 219.01 8.455 219.74 ; + RECT 8.75 219.01 9.11 219.74 ; + RECT 9.84 0.155 10.61 0.445 ; + RECT 9.84 0.155 10.1 8.665 ; + RECT 10.35 0.155 10.61 8.665 ; + RECT 9.32 219.01 9.52 219.74 ; + RECT 9.33 0.52 9.59 9.955 ; + RECT 9.975 219.01 10.175 219.74 ; + RECT 10.385 219.01 10.745 219.74 ; + RECT 10.86 0.52 11.12 11.315 ; + RECT 10.955 219.01 11.155 219.74 ; + RECT 11.37 0.52 11.63 13.45 ; + RECT 11.61 219.01 11.81 219.74 ; + RECT 11.88 0.52 12.14 14.115 ; + RECT 12.02 219.01 12.38 219.74 ; + RECT 12.675 219.01 12.875 219.74 ; + RECT 14.075 0.155 14.845 0.445 ; + RECT 14.075 0.155 14.335 13.21 ; + RECT 14.585 0.155 14.845 13.21 ; + RECT 13.17 219.01 13.53 219.74 ; + RECT 13.74 219.01 13.94 219.74 ; + RECT 15.095 0.18 15.865 0.88 ; + RECT 15.095 0.18 15.355 12.9 ; + RECT 15.605 0.18 15.865 12.9 ; + RECT 14.395 219.01 14.595 219.74 ; + RECT 14.805 219.01 15.165 219.74 ; + RECT 15.375 219.01 15.575 219.74 ; + RECT 16.03 219.01 16.23 219.74 ; + RECT 16.315 0.52 16.575 2.82 ; + RECT 16.44 219.01 16.8 219.74 ; + RECT 17.095 219.01 17.295 219.74 ; + RECT 17.59 219.01 17.95 219.74 ; + RECT 17.845 0.52 18.105 2.82 ; + RECT 18.16 219.01 18.36 219.74 ; + RECT 18.815 219.01 19.015 219.74 ; + RECT 19.02 0.52 19.28 4.315 ; + RECT 19.225 219.01 19.585 219.74 ; + RECT 19.795 219.01 19.995 219.74 ; + RECT 19.87 0.52 20.13 7.78 ; + RECT 20.38 0.3 20.64 5.235 ; + RECT 20.45 219.01 20.65 219.74 ; + RECT 20.89 0.52 21.15 5.57 ; + RECT 20.86 219.01 21.22 219.74 ; + RECT 21.515 219.01 21.715 219.74 ; + RECT 22.01 219.01 22.37 219.74 ; + RECT 22.265 0.52 22.525 6.28 ; + RECT 22.58 219.01 22.78 219.74 ; + RECT 23.235 219.01 23.435 219.74 ; + RECT 23.645 219.01 24.005 219.74 ; + RECT 24.215 219.01 24.415 219.74 ; + RECT 23.95 0.18 24.72 0.88 ; + RECT 24.87 219.01 25.07 219.74 ; + RECT 24.97 0.3 25.23 8.7 ; + RECT 25.28 219.01 25.64 219.74 ; + RECT 25.935 219.01 26.135 219.74 ; + RECT 26.43 219.01 26.79 219.74 ; + RECT 27.52 0.155 28.29 0.445 ; + RECT 27.52 0.155 27.78 8.665 ; + RECT 28.03 0.155 28.29 8.665 ; + RECT 27 219.01 27.2 219.74 ; + RECT 27.01 0.52 27.27 9.955 ; + RECT 27.655 219.01 27.855 219.74 ; + RECT 28.065 219.01 28.425 219.74 ; + RECT 28.54 0.52 28.8 11.315 ; + RECT 28.635 219.01 28.835 219.74 ; + RECT 29.05 0.52 29.31 13.45 ; + RECT 29.29 219.01 29.49 219.74 ; + RECT 29.56 0.52 29.82 14.115 ; + RECT 29.7 219.01 30.06 219.74 ; + RECT 30.355 219.01 30.555 219.74 ; + RECT 31.755 0.155 32.525 0.445 ; + RECT 31.755 0.155 32.015 13.21 ; + RECT 32.265 0.155 32.525 13.21 ; + RECT 30.85 219.01 31.21 219.74 ; + RECT 31.42 219.01 31.62 219.74 ; + RECT 32.775 0.18 33.545 0.88 ; + RECT 32.775 0.18 33.035 12.9 ; + RECT 33.285 0.18 33.545 12.9 ; + RECT 32.075 219.01 32.275 219.74 ; + RECT 32.485 219.01 32.845 219.74 ; + RECT 33.055 219.01 33.255 219.74 ; + RECT 33.71 219.01 33.91 219.74 ; + RECT 33.995 0.52 34.255 2.82 ; + RECT 34.12 219.01 34.48 219.74 ; + RECT 34.775 219.01 34.975 219.74 ; + RECT 35.27 219.01 35.63 219.74 ; + RECT 35.525 0.52 35.785 2.82 ; + RECT 35.84 219.01 36.04 219.74 ; + RECT 36.495 219.01 36.695 219.74 ; + RECT 36.7 0.52 36.96 4.315 ; + RECT 36.905 219.01 37.265 219.74 ; + RECT 37.475 219.01 37.675 219.74 ; + RECT 37.55 0.52 37.81 7.78 ; + RECT 38.06 0.3 38.32 5.235 ; + RECT 38.13 219.01 38.33 219.74 ; + RECT 38.57 0.52 38.83 5.57 ; + RECT 38.54 219.01 38.9 219.74 ; + RECT 39.195 219.01 39.395 219.74 ; + RECT 39.69 219.01 40.05 219.74 ; + RECT 39.945 0.52 40.205 6.28 ; + RECT 40.26 219.01 40.46 219.74 ; + RECT 40.915 219.01 41.115 219.74 ; + RECT 41.325 219.01 41.685 219.74 ; + RECT 41.895 219.01 42.095 219.74 ; + RECT 41.63 0.18 42.4 0.88 ; + RECT 42.55 219.01 42.75 219.74 ; + RECT 42.65 0.3 42.91 8.7 ; + RECT 42.96 219.01 43.32 219.74 ; + RECT 43.615 219.01 43.815 219.74 ; + RECT 44.11 219.01 44.47 219.74 ; + RECT 45.2 0.155 45.97 0.445 ; + RECT 45.2 0.155 45.46 8.665 ; + RECT 45.71 0.155 45.97 8.665 ; + RECT 44.68 219.01 44.88 219.74 ; + RECT 44.69 0.52 44.95 9.955 ; + RECT 45.335 219.01 45.535 219.74 ; + RECT 45.745 219.01 46.105 219.74 ; + RECT 46.22 0.52 46.48 11.315 ; + RECT 46.315 219.01 46.515 219.74 ; + RECT 46.73 0.52 46.99 13.45 ; + RECT 46.97 219.01 47.17 219.74 ; + RECT 47.24 0.52 47.5 14.115 ; + RECT 47.38 219.01 47.74 219.74 ; + RECT 48.035 219.01 48.235 219.74 ; + RECT 49.435 0.155 50.205 0.445 ; + RECT 49.435 0.155 49.695 13.21 ; + RECT 49.945 0.155 50.205 13.21 ; + RECT 48.53 219.01 48.89 219.74 ; + RECT 49.1 219.01 49.3 219.74 ; + RECT 50.455 0.18 51.225 0.88 ; + RECT 50.455 0.18 50.715 12.9 ; + RECT 50.965 0.18 51.225 12.9 ; + RECT 49.755 219.01 49.955 219.74 ; + RECT 50.165 219.01 50.525 219.74 ; + RECT 50.735 219.01 50.935 219.74 ; + RECT 51.39 219.01 51.59 219.74 ; + RECT 51.675 0.52 51.935 2.82 ; + RECT 51.8 219.01 52.16 219.74 ; + RECT 52.455 219.01 52.655 219.74 ; + RECT 52.95 219.01 53.31 219.74 ; + RECT 53.205 0.52 53.465 2.82 ; + RECT 53.52 219.01 53.72 219.74 ; + RECT 54.175 219.01 54.375 219.74 ; + RECT 54.38 0.52 54.64 4.315 ; + RECT 54.585 219.01 54.945 219.74 ; + RECT 55.155 219.01 55.355 219.74 ; + RECT 55.23 0.52 55.49 7.78 ; + RECT 55.74 0.3 56 5.235 ; + RECT 55.81 219.01 56.01 219.74 ; + RECT 56.25 0.52 56.51 5.57 ; + RECT 56.22 219.01 56.58 219.74 ; + RECT 56.875 219.01 57.075 219.74 ; + RECT 57.37 219.01 57.73 219.74 ; + RECT 57.625 0.52 57.885 6.28 ; + RECT 57.94 219.01 58.14 219.74 ; + RECT 58.595 219.01 58.795 219.74 ; + RECT 59.005 219.01 59.365 219.74 ; + RECT 59.575 219.01 59.775 219.74 ; + RECT 59.31 0.18 60.08 0.88 ; + RECT 60.23 219.01 60.43 219.74 ; + RECT 60.33 0.3 60.59 8.7 ; + RECT 60.64 219.01 61 219.74 ; + RECT 61.295 219.01 61.495 219.74 ; + RECT 61.79 219.01 62.15 219.74 ; + RECT 62.88 0.155 63.65 0.445 ; + RECT 62.88 0.155 63.14 8.665 ; + RECT 63.39 0.155 63.65 8.665 ; + RECT 62.36 219.01 62.56 219.74 ; + RECT 62.37 0.52 62.63 9.955 ; + RECT 63.015 219.01 63.215 219.74 ; + RECT 63.425 219.01 63.785 219.74 ; + RECT 63.9 0.52 64.16 11.315 ; + RECT 63.995 219.01 64.195 219.74 ; + RECT 64.41 0.52 64.67 13.45 ; + RECT 64.65 219.01 64.85 219.74 ; + RECT 64.92 0.52 65.18 14.115 ; + RECT 65.06 219.01 65.42 219.74 ; + RECT 65.715 219.01 65.915 219.74 ; + RECT 67.115 0.155 67.885 0.445 ; + RECT 67.115 0.155 67.375 13.21 ; + RECT 67.625 0.155 67.885 13.21 ; + RECT 66.21 219.01 66.57 219.74 ; + RECT 66.78 219.01 66.98 219.74 ; + RECT 68.135 0.18 68.905 0.88 ; + RECT 68.135 0.18 68.395 12.9 ; + RECT 68.645 0.18 68.905 12.9 ; + RECT 67.435 219.01 67.635 219.74 ; + RECT 67.845 219.01 68.205 219.74 ; + RECT 68.415 219.01 68.615 219.74 ; + RECT 69.07 219.01 69.27 219.74 ; + RECT 69.355 0.52 69.615 2.82 ; + RECT 69.48 219.01 69.84 219.74 ; + RECT 70.135 219.01 70.335 219.74 ; + RECT 70.63 219.01 70.99 219.74 ; + RECT 70.885 0.52 71.145 2.82 ; + RECT 71.2 219.01 71.4 219.74 ; + RECT 71.855 219.01 72.055 219.74 ; + RECT 73.08 0.17 73.85 0.43 ; + RECT 73.08 0.17 73.34 8.7 ; + RECT 73.59 0.17 73.85 8.7 ; + RECT 72.06 0.52 72.32 4.315 ; + RECT 74.1 0.18 74.87 0.88 ; + RECT 74.1 0.18 74.36 8.7 ; + RECT 74.61 0.18 74.87 8.7 ; + RECT 75.12 0.17 75.89 0.43 ; + RECT 75.12 0.17 75.38 8.7 ; + RECT 75.63 0.17 75.89 8.7 ; + RECT 76.14 0.18 76.91 0.88 ; + RECT 76.14 0.18 76.4 8.7 ; + RECT 76.65 0.18 76.91 8.7 ; + RECT 77.16 0.17 77.93 0.43 ; + RECT 77.16 0.17 77.42 8.7 ; + RECT 77.67 0.17 77.93 8.7 ; + RECT 78.18 0.18 78.95 0.88 ; + RECT 78.18 0.18 78.44 8.7 ; + RECT 78.69 0.18 78.95 8.7 ; + RECT 79.2 0.17 79.97 0.43 ; + RECT 79.2 0.17 79.46 8.7 ; + RECT 79.71 0.17 79.97 8.7 ; + RECT 80.22 0.18 80.99 0.88 ; + RECT 80.22 0.18 80.48 8.7 ; + RECT 80.73 0.18 80.99 8.7 ; + RECT 81.24 0.17 82.01 0.43 ; + RECT 81.24 0.17 81.5 8.7 ; + RECT 81.75 0.17 82.01 8.7 ; + RECT 82.26 0.18 83.03 0.88 ; + RECT 82.26 0.18 82.52 8.7 ; + RECT 82.77 0.18 83.03 8.7 ; + RECT 83.28 0.17 84.05 0.43 ; + RECT 83.28 0.17 83.54 8.7 ; + RECT 83.79 0.17 84.05 8.7 ; + RECT 84.3 0.18 85.07 0.88 ; + RECT 84.3 0.18 84.56 8.7 ; + RECT 84.81 0.18 85.07 8.7 ; + RECT 85.32 0.17 86.09 0.43 ; + RECT 85.32 0.17 85.58 8.7 ; + RECT 85.83 0.17 86.09 8.7 ; + RECT 86.34 0.18 87.11 0.88 ; + RECT 86.34 0.18 86.6 8.7 ; + RECT 86.85 0.18 87.11 8.7 ; + RECT 87.36 0.17 88.13 0.43 ; + RECT 87.36 0.17 87.62 8.7 ; + RECT 87.87 0.17 88.13 8.7 ; + RECT 88.38 0.18 89.15 0.88 ; + RECT 88.38 0.18 88.64 8.7 ; + RECT 88.89 0.18 89.15 8.7 ; + RECT 72.265 219.01 72.625 219.74 ; + RECT 72.835 219.01 73.035 219.74 ; + RECT 90.775 0.18 91.545 0.88 ; + RECT 90.775 0.18 91.035 8.7 ; + RECT 91.285 0.18 91.545 8.7 ; + RECT 91.795 0.17 92.565 0.43 ; + RECT 91.795 0.17 92.055 8.7 ; + RECT 92.305 0.17 92.565 8.7 ; + RECT 73.66 218.93 73.86 219.74 ; + RECT 89.755 0.3 90.015 8.7 ; + RECT 93.835 0.18 94.605 0.88 ; + RECT 93.835 0.18 94.095 8.7 ; + RECT 94.345 0.18 94.605 8.7 ; + RECT 90.265 0.3 90.525 8.7 ; + RECT 92.815 0 93.075 8.7 ; + RECT 93.325 0 93.585 8.7 ; + RECT 94.855 0.52 95.115 8.7 ; + RECT 95.365 0.3 95.625 8.7 ; + RECT 95.875 0.3 96.135 8.7 ; + RECT 96.385 0.3 96.645 8.7 ; + RECT 96.895 0.3 97.155 8.7 ; + RECT 97.405 0.3 97.665 8.7 ; + RECT 97.915 0.3 98.175 8.7 ; + RECT 98.425 0.3 98.685 8.7 ; + RECT 100.465 0.18 101.235 0.88 ; + RECT 100.465 0.18 100.725 8.7 ; + RECT 100.975 0.18 101.235 8.7 ; + RECT 98.935 0.3 99.195 8.7 ; + RECT 99.445 0.52 99.705 8.7 ; + RECT 99.955 0.52 100.215 8.7 ; + RECT 101.485 0 101.745 8.7 ; + RECT 101.995 0 102.255 8.7 ; + RECT 102.505 0.52 102.765 8.7 ; + RECT 103.015 0.52 103.275 8.7 ; + RECT 103.525 0.52 103.785 8.7 ; + RECT 104.035 0.52 104.295 8.7 ; + RECT 104.545 0.52 104.805 8.7 ; + RECT 105.055 0.52 105.315 8.7 ; + RECT 105.565 0.52 105.825 8.7 ; + RECT 106.075 0.52 106.335 8.7 ; + RECT 106.585 0.3 106.845 8.7 ; + RECT 107.095 0.3 107.355 8.7 ; + RECT 107.605 0.3 107.865 8.7 ; + RECT 108.115 0.52 108.375 8.7 ; + RECT 108.625 0.52 108.885 8.7 ; + RECT 109.135 0.3 109.395 8.7 ; + RECT 109.645 0.3 109.905 8.7 ; + RECT 110.155 0.3 110.415 8.7 ; + RECT 110.665 0.52 110.925 8.7 ; + RECT 111.175 0.52 111.435 8.7 ; + RECT 111.685 0.3 111.945 8.7 ; + RECT 112.195 0.52 112.455 8.7 ; + RECT 112.705 0.52 112.965 8.7 ; + RECT 113.215 0.52 113.475 8.7 ; + RECT 113.725 0.52 113.985 8.7 ; + RECT 114.235 0.52 114.495 8.7 ; + RECT 114.745 0.3 115.005 8.7 ; + RECT 115.255 0.52 115.515 8.7 ; + RECT 115.765 0.52 116.025 8.7 ; + RECT 116.275 0.3 116.535 8.7 ; + RECT 116.785 0.52 117.045 8.7 ; + RECT 118.825 0.17 119.595 0.43 ; + RECT 118.825 0.17 119.085 8.7 ; + RECT 119.335 0.17 119.595 8.7 ; + RECT 117.295 0.52 117.555 8.7 ; + RECT 117.805 0.3 118.065 8.7 ; + RECT 118.315 0.3 118.575 8.7 ; + RECT 121.375 0.17 122.145 0.43 ; + RECT 121.375 0.17 121.635 8.7 ; + RECT 121.885 0.17 122.145 8.7 ; + RECT 119.845 0.3 120.105 8.7 ; + RECT 122.905 0.18 123.675 0.88 ; + RECT 122.905 0.18 123.165 8.7 ; + RECT 123.415 0.18 123.675 8.7 ; + RECT 120.355 0.3 120.615 8.7 ; + RECT 120.865 0.3 121.125 8.7 ; + RECT 122.395 0.3 122.655 8.7 ; + RECT 123.925 0 124.185 8.7 ; + RECT 124.435 0 124.695 8.7 ; + RECT 124.945 0.52 125.205 8.7 ; + RECT 125.455 0.52 125.715 8.7 ; + RECT 125.965 0.52 126.225 8.7 ; + RECT 126.475 0.52 126.735 8.7 ; + RECT 126.985 0 127.245 8.7 ; + RECT 127.495 0 127.755 8.7 ; + RECT 128.005 0.3 128.265 8.7 ; + RECT 128.515 0.3 128.775 8.7 ; + RECT 129.025 0 129.285 8.7 ; + RECT 129.535 0 129.795 8.7 ; + RECT 130.045 0.3 130.305 8.7 ; + RECT 130.865 0.3 131.125 8.7 ; + RECT 131.375 0 131.635 8.7 ; + RECT 131.885 0 132.145 8.7 ; + RECT 132.395 0.3 132.655 8.7 ; + RECT 132.905 0.3 133.165 8.7 ; + RECT 133.415 0 133.675 8.7 ; + RECT 133.925 0 134.185 8.7 ; + RECT 134.435 0.52 134.695 8.7 ; + RECT 134.945 0.52 135.205 8.7 ; + RECT 135.455 0.52 135.715 8.7 ; + RECT 137.495 0.18 138.265 0.88 ; + RECT 137.495 0.18 137.755 8.7 ; + RECT 138.005 0.18 138.265 8.7 ; + RECT 135.965 0.52 136.225 8.7 ; + RECT 139.025 0.17 139.795 0.43 ; + RECT 139.025 0.17 139.285 8.7 ; + RECT 139.535 0.17 139.795 8.7 ; + RECT 136.475 0 136.735 8.7 ; + RECT 136.985 0 137.245 8.7 ; + RECT 138.515 0.3 138.775 8.7 ; + RECT 141.575 0.17 142.345 0.43 ; + RECT 141.575 0.17 141.835 8.7 ; + RECT 142.085 0.17 142.345 8.7 ; + RECT 140.045 0.3 140.305 8.7 ; + RECT 140.555 0.3 140.815 8.7 ; + RECT 141.065 0.3 141.325 8.7 ; + RECT 142.595 0.3 142.855 8.7 ; + RECT 143.105 0.3 143.365 8.7 ; + RECT 143.615 0.52 143.875 8.7 ; + RECT 144.125 0.52 144.385 8.7 ; + RECT 144.635 0.3 144.895 8.7 ; + RECT 145.145 0.52 145.405 8.7 ; + RECT 145.655 0.52 145.915 8.7 ; + RECT 146.165 0.3 146.425 8.7 ; + RECT 146.675 0.52 146.935 8.7 ; + RECT 147.185 0.52 147.445 8.7 ; + RECT 147.695 0.52 147.955 8.7 ; + RECT 148.205 0.52 148.465 8.7 ; + RECT 148.715 0.52 148.975 8.7 ; + RECT 149.225 0.3 149.485 8.7 ; + RECT 149.735 0.52 149.995 8.7 ; + RECT 150.245 0.52 150.505 8.7 ; + RECT 150.755 0.3 151.015 8.7 ; + RECT 151.265 0.3 151.525 8.7 ; + RECT 151.775 0.3 152.035 8.7 ; + RECT 152.285 0.52 152.545 8.7 ; + RECT 152.795 0.52 153.055 8.7 ; + RECT 153.305 0.3 153.565 8.7 ; + RECT 153.815 0.3 154.075 8.7 ; + RECT 154.325 0.3 154.585 8.7 ; + RECT 154.835 0.52 155.095 8.7 ; + RECT 155.345 0.52 155.605 8.7 ; + RECT 155.855 0.52 156.115 8.7 ; + RECT 156.365 0.52 156.625 8.7 ; + RECT 156.875 0.52 157.135 8.7 ; + RECT 157.385 0.52 157.645 8.7 ; + RECT 157.895 0.52 158.155 8.7 ; + RECT 159.935 0.18 160.705 0.88 ; + RECT 159.935 0.18 160.195 8.7 ; + RECT 160.445 0.18 160.705 8.7 ; + RECT 158.405 0.52 158.665 8.7 ; + RECT 158.915 0 159.175 8.7 ; + RECT 159.425 0 159.685 8.7 ; + RECT 160.955 0.52 161.215 8.7 ; + RECT 161.465 0.52 161.725 8.7 ; + RECT 161.975 0.3 162.235 8.7 ; + RECT 162.485 0.3 162.745 8.7 ; + RECT 162.995 0.3 163.255 8.7 ; + RECT 163.505 0.3 163.765 8.7 ; + RECT 164.015 0.3 164.275 8.7 ; + RECT 164.525 0.3 164.785 8.7 ; + RECT 166.565 0.18 167.335 0.88 ; + RECT 166.565 0.18 166.825 8.7 ; + RECT 167.075 0.18 167.335 8.7 ; + RECT 165.035 0.3 165.295 8.7 ; + RECT 165.545 0.3 165.805 8.7 ; + RECT 168.605 0.17 169.375 0.43 ; + RECT 168.605 0.17 168.865 8.7 ; + RECT 169.115 0.17 169.375 8.7 ; + RECT 169.625 0.18 170.395 0.88 ; + RECT 169.625 0.18 169.885 8.7 ; + RECT 170.135 0.18 170.395 8.7 ; + RECT 166.055 0.52 166.315 8.7 ; + RECT 167.585 0 167.845 8.7 ; + RECT 172.02 0.18 172.79 0.88 ; + RECT 172.02 0.18 172.28 8.7 ; + RECT 172.53 0.18 172.79 8.7 ; + RECT 173.04 0.17 173.81 0.43 ; + RECT 173.04 0.17 173.3 8.7 ; + RECT 173.55 0.17 173.81 8.7 ; + RECT 174.06 0.18 174.83 0.88 ; + RECT 174.06 0.18 174.32 8.7 ; + RECT 174.57 0.18 174.83 8.7 ; + RECT 175.08 0.17 175.85 0.43 ; + RECT 175.08 0.17 175.34 8.7 ; + RECT 175.59 0.17 175.85 8.7 ; + RECT 176.1 0.18 176.87 0.88 ; + RECT 176.1 0.18 176.36 8.7 ; + RECT 176.61 0.18 176.87 8.7 ; + RECT 177.12 0.17 177.89 0.43 ; + RECT 177.12 0.17 177.38 8.7 ; + RECT 177.63 0.17 177.89 8.7 ; + RECT 178.14 0.18 178.91 0.88 ; + RECT 178.14 0.18 178.4 8.7 ; + RECT 178.65 0.18 178.91 8.7 ; + RECT 179.16 0.17 179.93 0.43 ; + RECT 179.16 0.17 179.42 8.7 ; + RECT 179.67 0.17 179.93 8.7 ; + RECT 180.18 0.18 180.95 0.88 ; + RECT 180.18 0.18 180.44 8.7 ; + RECT 180.69 0.18 180.95 8.7 ; + RECT 181.2 0.17 181.97 0.43 ; + RECT 181.2 0.17 181.46 8.7 ; + RECT 181.71 0.17 181.97 8.7 ; + RECT 182.22 0.18 182.99 0.88 ; + RECT 182.22 0.18 182.48 8.7 ; + RECT 182.73 0.18 182.99 8.7 ; + RECT 183.24 0.17 184.01 0.43 ; + RECT 183.24 0.17 183.5 8.7 ; + RECT 183.75 0.17 184.01 8.7 ; + RECT 184.26 0.18 185.03 0.88 ; + RECT 184.26 0.18 184.52 8.7 ; + RECT 184.77 0.18 185.03 8.7 ; + RECT 185.28 0.17 186.05 0.43 ; + RECT 185.28 0.17 185.54 8.7 ; + RECT 185.79 0.17 186.05 8.7 ; + RECT 186.3 0.18 187.07 0.88 ; + RECT 186.3 0.18 186.56 8.7 ; + RECT 186.81 0.18 187.07 8.7 ; + RECT 168.095 0 168.355 8.7 ; + RECT 187.32 0.17 188.09 0.43 ; + RECT 187.32 0.17 187.58 8.7 ; + RECT 187.83 0.17 188.09 8.7 ; + RECT 170.645 0.3 170.905 8.7 ; + RECT 171.155 0.3 171.415 8.7 ; + RECT 187.31 218.93 187.51 219.74 ; + RECT 188.135 219.01 188.335 219.74 ; + RECT 188.545 219.01 188.905 219.74 ; + RECT 188.85 0.52 189.11 4.315 ; + RECT 189.115 219.01 189.315 219.74 ; + RECT 189.77 219.01 189.97 219.74 ; + RECT 190.025 0.52 190.285 2.82 ; + RECT 190.18 219.01 190.54 219.74 ; + RECT 190.835 219.01 191.035 219.74 ; + RECT 191.33 219.01 191.69 219.74 ; + RECT 192.265 0.18 193.035 0.88 ; + RECT 192.265 0.18 192.525 12.9 ; + RECT 192.775 0.18 193.035 12.9 ; + RECT 191.555 0.52 191.815 2.82 ; + RECT 191.9 219.01 192.1 219.74 ; + RECT 193.285 0.155 194.055 0.445 ; + RECT 193.285 0.155 193.545 13.21 ; + RECT 193.795 0.155 194.055 13.21 ; + RECT 192.555 219.01 192.755 219.74 ; + RECT 192.965 219.01 193.325 219.74 ; + RECT 193.535 219.01 193.735 219.74 ; + RECT 194.19 219.01 194.39 219.74 ; + RECT 194.6 219.01 194.96 219.74 ; + RECT 195.255 219.01 195.455 219.74 ; + RECT 195.75 219.01 196.11 219.74 ; + RECT 195.99 0.52 196.25 14.115 ; + RECT 196.32 219.01 196.52 219.74 ; + RECT 196.5 0.52 196.76 13.45 ; + RECT 196.975 219.01 197.175 219.74 ; + RECT 197.52 0.155 198.29 0.445 ; + RECT 197.52 0.155 197.78 8.665 ; + RECT 198.03 0.155 198.29 8.665 ; + RECT 197.01 0.52 197.27 11.315 ; + RECT 197.385 219.01 197.745 219.74 ; + RECT 197.955 219.01 198.155 219.74 ; + RECT 198.54 0.52 198.8 9.955 ; + RECT 198.61 219.01 198.81 219.74 ; + RECT 199.02 219.01 199.38 219.74 ; + RECT 199.675 219.01 199.875 219.74 ; + RECT 200.17 219.01 200.53 219.74 ; + RECT 200.58 0.3 200.84 8.7 ; + RECT 200.74 219.01 200.94 219.74 ; + RECT 201.395 219.01 201.595 219.74 ; + RECT 201.09 0.18 201.86 0.88 ; + RECT 201.805 219.01 202.165 219.74 ; + RECT 202.375 219.01 202.575 219.74 ; + RECT 203.03 219.01 203.23 219.74 ; + RECT 203.285 0.52 203.545 6.28 ; + RECT 203.44 219.01 203.8 219.74 ; + RECT 204.095 219.01 204.295 219.74 ; + RECT 204.66 0.52 204.92 5.57 ; + RECT 204.59 219.01 204.95 219.74 ; + RECT 205.16 219.01 205.36 219.74 ; + RECT 205.17 0.3 205.43 5.235 ; + RECT 205.68 0.52 205.94 7.78 ; + RECT 205.815 219.01 206.015 219.74 ; + RECT 206.225 219.01 206.585 219.74 ; + RECT 206.53 0.52 206.79 4.315 ; + RECT 206.795 219.01 206.995 219.74 ; + RECT 207.45 219.01 207.65 219.74 ; + RECT 207.705 0.52 207.965 2.82 ; + RECT 207.86 219.01 208.22 219.74 ; + RECT 208.515 219.01 208.715 219.74 ; + RECT 209.01 219.01 209.37 219.74 ; + RECT 209.945 0.18 210.715 0.88 ; + RECT 209.945 0.18 210.205 12.9 ; + RECT 210.455 0.18 210.715 12.9 ; + RECT 209.235 0.52 209.495 2.82 ; + RECT 209.58 219.01 209.78 219.74 ; + RECT 210.965 0.155 211.735 0.445 ; + RECT 210.965 0.155 211.225 13.21 ; + RECT 211.475 0.155 211.735 13.21 ; + RECT 210.235 219.01 210.435 219.74 ; + RECT 210.645 219.01 211.005 219.74 ; + RECT 211.215 219.01 211.415 219.74 ; + RECT 211.87 219.01 212.07 219.74 ; + RECT 212.28 219.01 212.64 219.74 ; + RECT 212.935 219.01 213.135 219.74 ; + RECT 213.43 219.01 213.79 219.74 ; + RECT 213.67 0.52 213.93 14.115 ; + RECT 214 219.01 214.2 219.74 ; + RECT 214.18 0.52 214.44 13.45 ; + RECT 214.655 219.01 214.855 219.74 ; + RECT 215.2 0.155 215.97 0.445 ; + RECT 215.2 0.155 215.46 8.665 ; + RECT 215.71 0.155 215.97 8.665 ; + RECT 214.69 0.52 214.95 11.315 ; + RECT 215.065 219.01 215.425 219.74 ; + RECT 215.635 219.01 215.835 219.74 ; + RECT 216.22 0.52 216.48 9.955 ; + RECT 216.29 219.01 216.49 219.74 ; + RECT 216.7 219.01 217.06 219.74 ; + RECT 217.355 219.01 217.555 219.74 ; + RECT 217.85 219.01 218.21 219.74 ; + RECT 218.26 0.3 218.52 8.7 ; + RECT 218.42 219.01 218.62 219.74 ; + RECT 219.075 219.01 219.275 219.74 ; + RECT 218.77 0.18 219.54 0.88 ; + RECT 219.485 219.01 219.845 219.74 ; + RECT 220.055 219.01 220.255 219.74 ; + RECT 220.71 219.01 220.91 219.74 ; + RECT 220.965 0.52 221.225 6.28 ; + RECT 221.12 219.01 221.48 219.74 ; + RECT 221.775 219.01 221.975 219.74 ; + RECT 222.34 0.52 222.6 5.57 ; + RECT 222.27 219.01 222.63 219.74 ; + RECT 222.84 219.01 223.04 219.74 ; + RECT 222.85 0.3 223.11 5.235 ; + RECT 223.36 0.52 223.62 7.78 ; + RECT 223.495 219.01 223.695 219.74 ; + RECT 223.905 219.01 224.265 219.74 ; + RECT 224.21 0.52 224.47 4.315 ; + RECT 224.475 219.01 224.675 219.74 ; + RECT 225.13 219.01 225.33 219.74 ; + RECT 225.385 0.52 225.645 2.82 ; + RECT 225.54 219.01 225.9 219.74 ; + RECT 226.195 219.01 226.395 219.74 ; + RECT 226.69 219.01 227.05 219.74 ; + RECT 227.625 0.18 228.395 0.88 ; + RECT 227.625 0.18 227.885 12.9 ; + RECT 228.135 0.18 228.395 12.9 ; + RECT 226.915 0.52 227.175 2.82 ; + RECT 227.26 219.01 227.46 219.74 ; + RECT 228.645 0.155 229.415 0.445 ; + RECT 228.645 0.155 228.905 13.21 ; + RECT 229.155 0.155 229.415 13.21 ; + RECT 227.915 219.01 228.115 219.74 ; + RECT 228.325 219.01 228.685 219.74 ; + RECT 228.895 219.01 229.095 219.74 ; + RECT 229.55 219.01 229.75 219.74 ; + RECT 229.96 219.01 230.32 219.74 ; + RECT 230.615 219.01 230.815 219.74 ; + RECT 231.11 219.01 231.47 219.74 ; + RECT 231.35 0.52 231.61 14.115 ; + RECT 231.68 219.01 231.88 219.74 ; + RECT 231.86 0.52 232.12 13.45 ; + RECT 232.335 219.01 232.535 219.74 ; + RECT 232.88 0.155 233.65 0.445 ; + RECT 232.88 0.155 233.14 8.665 ; + RECT 233.39 0.155 233.65 8.665 ; + RECT 232.37 0.52 232.63 11.315 ; + RECT 232.745 219.01 233.105 219.74 ; + RECT 233.315 219.01 233.515 219.74 ; + RECT 233.9 0.52 234.16 9.955 ; + RECT 233.97 219.01 234.17 219.74 ; + RECT 234.38 219.01 234.74 219.74 ; + RECT 235.035 219.01 235.235 219.74 ; + RECT 235.53 219.01 235.89 219.74 ; + RECT 235.94 0.3 236.2 8.7 ; + RECT 236.1 219.01 236.3 219.74 ; + RECT 236.755 219.01 236.955 219.74 ; + RECT 236.45 0.18 237.22 0.88 ; + RECT 237.165 219.01 237.525 219.74 ; + RECT 237.735 219.01 237.935 219.74 ; + RECT 238.39 219.01 238.59 219.74 ; + RECT 238.645 0.52 238.905 6.28 ; + RECT 238.8 219.01 239.16 219.74 ; + RECT 239.455 219.01 239.655 219.74 ; + RECT 240.02 0.52 240.28 5.57 ; + RECT 239.95 219.01 240.31 219.74 ; + RECT 240.52 219.01 240.72 219.74 ; + RECT 240.53 0.3 240.79 5.235 ; + RECT 241.04 0.52 241.3 7.78 ; + RECT 241.175 219.01 241.375 219.74 ; + RECT 241.585 219.01 241.945 219.74 ; + RECT 241.89 0.52 242.15 4.315 ; + RECT 242.155 219.01 242.355 219.74 ; + RECT 242.81 219.01 243.01 219.74 ; + RECT 243.065 0.52 243.325 2.82 ; + RECT 243.22 219.01 243.58 219.74 ; + RECT 243.875 219.01 244.075 219.74 ; + RECT 244.37 219.01 244.73 219.74 ; + RECT 245.305 0.18 246.075 0.88 ; + RECT 245.305 0.18 245.565 12.9 ; + RECT 245.815 0.18 246.075 12.9 ; + RECT 244.595 0.52 244.855 2.82 ; + RECT 244.94 219.01 245.14 219.74 ; + RECT 246.325 0.155 247.095 0.445 ; + RECT 246.325 0.155 246.585 13.21 ; + RECT 246.835 0.155 247.095 13.21 ; + RECT 245.595 219.01 245.795 219.74 ; + RECT 246.005 219.01 246.365 219.74 ; + RECT 246.575 219.01 246.775 219.74 ; + RECT 247.23 219.01 247.43 219.74 ; + RECT 247.64 219.01 248 219.74 ; + RECT 248.295 219.01 248.495 219.74 ; + RECT 248.79 219.01 249.15 219.74 ; + RECT 249.03 0.52 249.29 14.115 ; + RECT 249.36 219.01 249.56 219.74 ; + RECT 249.54 0.52 249.8 13.45 ; + RECT 250.015 219.01 250.215 219.74 ; + RECT 250.56 0.155 251.33 0.445 ; + RECT 250.56 0.155 250.82 8.665 ; + RECT 251.07 0.155 251.33 8.665 ; + RECT 250.05 0.52 250.31 11.315 ; + RECT 250.425 219.01 250.785 219.74 ; + RECT 250.995 219.01 251.195 219.74 ; + RECT 251.58 0.52 251.84 9.955 ; + RECT 251.65 219.01 251.85 219.74 ; + RECT 252.06 219.01 252.42 219.74 ; + RECT 252.715 219.01 252.915 219.74 ; + RECT 253.21 219.01 253.57 219.74 ; + RECT 253.62 0.3 253.88 8.7 ; + RECT 253.78 219.01 253.98 219.74 ; + RECT 254.435 219.01 254.635 219.74 ; + RECT 254.13 0.18 254.9 0.88 ; + RECT 254.845 219.01 255.205 219.74 ; + RECT 255.415 219.01 255.615 219.74 ; + RECT 256.07 219.01 256.27 219.74 ; + RECT 256.325 0.52 256.585 6.28 ; + RECT 256.48 219.01 256.84 219.74 ; + RECT 257.135 219.01 257.335 219.74 ; + RECT 257.7 0.52 257.96 5.57 ; + RECT 257.63 219.01 257.99 219.74 ; + RECT 258.2 219.01 258.4 219.74 ; + RECT 258.21 0.3 258.47 5.235 ; + RECT 258.72 0.52 258.98 7.78 ; + RECT 258.855 219.01 259.055 219.74 ; + RECT 259.265 219.01 259.625 219.74 ; + RECT 259.835 219.01 260.035 219.74 ; + RECT 260.66 53.41 260.86 219.74 ; + LAYER Metal2 SPACING 0.21 ; + RECT 259.24 0 261.17 219.77 ; + RECT 0 0.52 261.17 219.77 ; + RECT 258.21 0.3 258.47 219.77 ; + RECT 256.845 0 257.44 219.77 ; + RECT 252.1 0 256.065 219.77 ; + RECT 250.56 0.155 251.33 219.77 ; + RECT 245.115 0 248.77 219.77 ; + RECT 243.585 0 244.335 219.77 ; + RECT 242.41 0 242.805 219.77 ; + RECT 240.53 0.3 240.79 219.77 ; + RECT 239.165 0 239.76 219.77 ; + RECT 234.42 0 238.385 219.77 ; + RECT 232.88 0.155 233.65 219.77 ; + RECT 227.435 0 231.09 219.77 ; + RECT 225.905 0 226.655 219.77 ; + RECT 224.73 0 225.125 219.77 ; + RECT 222.85 0.3 223.11 219.77 ; + RECT 221.485 0 222.08 219.77 ; + RECT 216.74 0 220.705 219.77 ; + RECT 215.2 0.155 215.97 219.77 ; + RECT 209.755 0 213.41 219.77 ; + RECT 208.225 0 208.975 219.77 ; + RECT 207.05 0 207.445 219.77 ; + RECT 205.17 0.3 205.43 219.77 ; + RECT 203.805 0 204.4 219.77 ; + RECT 199.06 0 203.025 219.77 ; + RECT 197.52 0.155 198.29 219.77 ; + RECT 192.075 0 195.73 219.77 ; + RECT 190.545 0 191.295 219.77 ; + RECT 189.37 0 189.765 219.77 ; + RECT 166.565 0.18 188.59 219.77 ; + RECT 166.575 0 188.59 219.77 ; + RECT 161.975 0.3 165.805 219.77 ; + RECT 158.915 0.18 160.705 219.77 ; + RECT 153.305 0.3 154.585 219.77 ; + RECT 150.755 0.3 152.035 219.77 ; + RECT 149.225 0.3 149.485 219.77 ; + RECT 146.165 0.3 146.425 219.77 ; + RECT 144.635 0.3 144.895 219.77 ; + RECT 136.475 0.3 143.365 219.77 ; + RECT 126.985 0 134.185 219.77 ; + RECT 117.805 0.3 124.695 219.77 ; + RECT 117.815 0 124.695 219.77 ; + RECT 116.275 0.3 116.535 219.77 ; + RECT 114.745 0.3 115.005 219.77 ; + RECT 111.685 0.3 111.945 219.77 ; + RECT 109.135 0.3 110.415 219.77 ; + RECT 106.585 0.3 107.865 219.77 ; + RECT 100.465 0.18 102.255 219.77 ; + RECT 100.475 0 102.255 219.77 ; + RECT 95.365 0.3 99.195 219.77 ; + RECT 72.58 0.18 94.605 219.77 ; + RECT 71.405 0 71.8 219.77 ; + RECT 69.875 0 70.625 219.77 ; + RECT 65.44 0 69.095 219.77 ; + RECT 62.88 0.155 63.65 219.77 ; + RECT 58.145 0 62.11 219.77 ; + RECT 56.77 0 57.365 219.77 ; + RECT 55.74 0.3 56 219.77 ; + RECT 53.725 0 54.12 219.77 ; + RECT 52.195 0 52.945 219.77 ; + RECT 47.76 0 51.415 219.77 ; + RECT 45.2 0.155 45.97 219.77 ; + RECT 40.465 0 44.43 219.77 ; + RECT 39.09 0 39.685 219.77 ; + RECT 38.06 0.3 38.32 219.77 ; + RECT 36.045 0 36.44 219.77 ; + RECT 34.515 0 35.265 219.77 ; + RECT 30.08 0 33.735 219.77 ; + RECT 27.52 0.155 28.29 219.77 ; + RECT 22.785 0 26.75 219.77 ; + RECT 21.41 0 22.005 219.77 ; + RECT 20.38 0.3 20.64 219.77 ; + RECT 18.365 0 18.76 219.77 ; + RECT 16.835 0 17.585 219.77 ; + RECT 12.4 0 16.055 219.77 ; + RECT 9.84 0.155 10.61 219.77 ; + RECT 5.105 0 9.07 219.77 ; + RECT 3.73 0 4.325 219.77 ; + RECT 2.7 0.3 2.96 219.77 ; + RECT 0 0 1.93 219.77 ; + RECT 258.22 0 258.46 219.77 ; + RECT 240.54 0 240.78 219.77 ; + RECT 222.86 0 223.1 219.77 ; + RECT 205.18 0 205.42 219.77 ; + RECT 161.985 0 165.795 219.77 ; + RECT 153.315 0 154.575 219.77 ; + RECT 150.765 0 152.025 219.77 ; + RECT 149.235 0 149.475 219.77 ; + RECT 146.175 0 146.415 219.77 ; + RECT 144.645 0 144.885 219.77 ; + RECT 136.475 0 143.355 219.77 ; + RECT 116.285 0 116.525 219.77 ; + RECT 114.755 0 114.995 219.77 ; + RECT 111.695 0 111.935 219.77 ; + RECT 109.145 0 110.405 219.77 ; + RECT 106.595 0 107.855 219.77 ; + RECT 95.375 0 99.185 219.77 ; + RECT 55.75 0 55.99 219.77 ; + RECT 38.07 0 38.31 219.77 ; + RECT 20.39 0 20.63 219.77 ; + RECT 2.71 0 2.95 219.77 ; + RECT 158.915 0 160.695 219.77 ; + RECT 72.58 0 94.595 219.77 ; + RECT 250.57 0 251.32 219.77 ; + RECT 232.89 0 233.64 219.77 ; + RECT 215.21 0 215.96 219.77 ; + RECT 197.53 0 198.28 219.77 ; + RECT 62.89 0 63.64 219.77 ; + RECT 45.21 0 45.96 219.77 ; + RECT 27.53 0 28.28 219.77 ; + RECT 9.85 0 10.6 219.77 ; + LAYER Metal3 ; + RECT 0 0 261.17 219.77 ; + LAYER Metal4 SPACING 0.21 ; + RECT 170.875 0 188.465 219.77 ; + RECT 165.725 0 167.545 219.77 ; + RECT 160.575 0 162.395 219.77 ; + RECT 255.285 0 261.17 219.77 ; + RECT 246.445 0 250.345 219.77 ; + RECT 246.445 47.305 261.17 53.15 ; + RECT 237.605 0 241.505 219.77 ; + RECT 228.765 0 232.665 219.77 ; + RECT 228.765 47.305 241.505 53.15 ; + RECT 219.925 0 223.825 219.77 ; + RECT 211.085 0 214.985 219.77 ; + RECT 211.085 47.305 223.825 53.15 ; + RECT 202.245 0 206.145 219.77 ; + RECT 193.405 0 197.305 219.77 ; + RECT 193.405 47.305 206.145 53.15 ; + RECT 155.425 0 157.245 219.77 ; + RECT 150.275 0 152.095 219.77 ; + RECT 145.125 0 146.945 219.77 ; + RECT 139.975 0 141.795 219.77 ; + RECT 134.825 0 136.645 219.77 ; + RECT 129.675 0 131.495 219.77 ; + RECT 124.525 0 126.345 219.77 ; + RECT 119.375 0 121.195 219.77 ; + RECT 114.225 0 116.045 219.77 ; + RECT 109.075 0 110.895 219.77 ; + RECT 103.925 0 105.745 219.77 ; + RECT 98.775 0 100.595 219.77 ; + RECT 93.625 0 95.445 219.77 ; + RECT 72.705 0 90.295 219.77 ; + RECT 63.865 0 67.765 219.77 ; + RECT 55.025 0 58.925 219.77 ; + RECT 55.025 47.305 67.765 53.15 ; + RECT 46.185 0 50.085 219.77 ; + RECT 37.345 0 41.245 219.77 ; + RECT 37.345 47.305 50.085 53.15 ; + RECT 28.505 0 32.405 219.77 ; + RECT 19.665 0 23.565 219.77 ; + RECT 19.665 47.305 32.405 53.15 ; + RECT 10.825 0 14.725 219.77 ; + RECT 0 0 5.885 219.77 ; + RECT 0 47.305 14.725 53.15 ; + END +END RM_IHPSG13_2P_512x8_c2_bm_bist + +END LIBRARY diff --git a/flow/platforms/ihp-sg13g2/lef/RM_IHPSG13_2P_64x32_c2.lef b/flow/platforms/ihp-sg13g2/lef/RM_IHPSG13_2P_64x32_c2.lef new file mode 100644 index 0000000000..3b53196a41 --- /dev/null +++ b/flow/platforms/ihp-sg13g2/lef/RM_IHPSG13_2P_64x32_c2.lef @@ -0,0 +1,4543 @@ +# ------------------------------------------------------ +# +# Copyright 2023 IHP PDK Authors +# +# Licensed under the Apache License, Version 2.0 (the "License"); +# you may not use this file except in compliance with the License. +# You may obtain a copy of the License at +# +# https://www.apache.org/licenses/LICENSE-2.0 +# +# Unless required by applicable law or agreed to in writing, software +# distributed under the License is distributed on an "AS IS" BASIS, +# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +# See the License for the specific language governing permissions and +# limitations under the License. +# +# Generated on Thu Jun 12 11:08:54 2025 +# +# ------------------------------------------------------ +VERSION 5.7 ; +BUSBITCHARS "[]" ; +DIVIDERCHAR "/" ; + +MACRO RM_IHPSG13_2P_64x32_c2 + CLASS BLOCK ; + ORIGIN 0 0 ; + FOREIGN RM_IHPSG13_2P_64x32_c2 0 0 ; + SIZE 702.83 BY 74.87 ; + SYMMETRY X Y R90 ; + PIN A_DIN[16] + DIRECTION INPUT ; + USE SIGNAL ; + ANTENNAPARTIALMETALAREA 3.9091 LAYER Metal2 ; + ANTENNAMODEL OXIDE1 ; + ANTENNAGATEAREA 0.20085 LAYER Metal2 ; + ANTENNAMAXAREACAR 20.368932 LAYER Metal2 ; + PORT + LAYER Metal2 ; + RECT 425.49 0 425.75 0.26 ; + END + END A_DIN[16] + PIN A_DIN[15] + DIRECTION INPUT ; + USE SIGNAL ; + ANTENNAPARTIALMETALAREA 3.9091 LAYER Metal2 ; + ANTENNAMODEL OXIDE1 ; + ANTENNAGATEAREA 0.20085 LAYER Metal2 ; + ANTENNAMAXAREACAR 20.368932 LAYER Metal2 ; + PORT + LAYER Metal2 ; + RECT 277.08 0 277.34 0.26 ; + END + END A_DIN[15] + PIN A_DOUT[16] + DIRECTION OUTPUT ; + USE SIGNAL ; + ANTENNAPARTIALMETALAREA 4.8256 LAYER Metal2 ; + ANTENNADIFFAREA 0.988 LAYER Metal2 ; + PORT + LAYER Metal2 ; + RECT 418.35 0 418.61 0.26 ; + END + END A_DOUT[16] + PIN A_DOUT[15] + DIRECTION OUTPUT ; + USE SIGNAL ; + ANTENNAPARTIALMETALAREA 4.8256 LAYER Metal2 ; + ANTENNADIFFAREA 0.988 LAYER Metal2 ; + PORT + LAYER Metal2 ; + RECT 284.22 0 284.48 0.26 ; + END + END A_DOUT[15] + PIN B_DIN[16] + DIRECTION INPUT ; + USE SIGNAL ; + ANTENNAPARTIALMETALAREA 2.925 LAYER Metal2 ; + ANTENNAMODEL OXIDE1 ; + ANTENNAGATEAREA 0.20085 LAYER Metal2 ; + ANTENNAMAXAREACAR 15.469256 LAYER Metal2 ; + PORT + LAYER Metal2 ; + RECT 428.04 0 428.3 0.26 ; + END + END B_DIN[16] + PIN B_DIN[15] + DIRECTION INPUT ; + USE SIGNAL ; + ANTENNAPARTIALMETALAREA 2.925 LAYER Metal2 ; + ANTENNAMODEL OXIDE1 ; + ANTENNAGATEAREA 0.20085 LAYER Metal2 ; + ANTENNAMAXAREACAR 15.469256 LAYER Metal2 ; + PORT + LAYER Metal2 ; + RECT 274.53 0 274.79 0.26 ; + END + END B_DIN[15] + PIN B_DOUT[16] + DIRECTION OUTPUT ; + USE SIGNAL ; + ANTENNAPARTIALMETALAREA 4.836 LAYER Metal2 ; + ANTENNADIFFAREA 0.988 LAYER Metal2 ; + PORT + LAYER Metal2 ; + RECT 435.18 0 435.44 0.26 ; + END + END B_DOUT[16] + PIN B_DOUT[15] + DIRECTION OUTPUT ; + USE SIGNAL ; + ANTENNAPARTIALMETALAREA 4.836 LAYER Metal2 ; + ANTENNADIFFAREA 0.988 LAYER Metal2 ; + PORT + LAYER Metal2 ; + RECT 267.39 0 267.65 0.26 ; + END + END B_DOUT[15] + PIN VSS! + DIRECTION INOUT ; + USE GROUND ; + NETEXPR "vss VSS!" ; + PORT + LAYER Metal4 ; + RECT 683.425 0 687.845 74.87 ; + END + PORT + LAYER Metal4 ; + RECT 665.745 0 670.165 74.87 ; + END + PORT + LAYER Metal4 ; + RECT 648.065 0 652.485 74.87 ; + END + PORT + LAYER Metal4 ; + RECT 630.385 0 634.805 74.87 ; + END + PORT + LAYER Metal4 ; + RECT 612.705 0 617.125 74.87 ; + END + PORT + LAYER Metal4 ; + RECT 595.025 0 599.445 74.87 ; + END + PORT + LAYER Metal4 ; + RECT 577.345 0 581.765 74.87 ; + END + PORT + LAYER Metal4 ; + RECT 559.665 0 564.085 74.87 ; + END + PORT + LAYER Metal4 ; + RECT 541.985 0 546.405 74.87 ; + END + PORT + LAYER Metal4 ; + RECT 524.305 0 528.725 74.87 ; + END + PORT + LAYER Metal4 ; + RECT 506.625 0 511.045 74.87 ; + END + PORT + LAYER Metal4 ; + RECT 488.945 0 493.365 74.87 ; + END + PORT + LAYER Metal4 ; + RECT 471.265 0 475.685 74.87 ; + END + PORT + LAYER Metal4 ; + RECT 453.585 0 458.005 74.87 ; + END + PORT + LAYER Metal4 ; + RECT 435.905 0 440.325 74.87 ; + END + PORT + LAYER Metal4 ; + RECT 418.225 0 422.645 74.87 ; + END + PORT + LAYER Metal4 ; + RECT 388.635 0 391.445 74.87 ; + END + PORT + LAYER Metal4 ; + RECT 378.335 0 381.145 74.87 ; + END + PORT + LAYER Metal4 ; + RECT 362.885 0 365.695 74.87 ; + END + PORT + LAYER Metal4 ; + RECT 352.585 0 355.395 74.87 ; + END + PORT + LAYER Metal4 ; + RECT 347.435 0 350.245 74.87 ; + END + PORT + LAYER Metal4 ; + RECT 337.135 0 339.945 74.87 ; + END + PORT + LAYER Metal4 ; + RECT 321.685 0 324.495 74.87 ; + END + PORT + LAYER Metal4 ; + RECT 311.385 0 314.195 74.87 ; + END + PORT + LAYER Metal4 ; + RECT 280.185 0 284.605 74.87 ; + END + PORT + LAYER Metal4 ; + RECT 262.505 0 266.925 74.87 ; + END + PORT + LAYER Metal4 ; + RECT 244.825 0 249.245 74.87 ; + END + PORT + LAYER Metal4 ; + RECT 227.145 0 231.565 74.87 ; + END + PORT + LAYER Metal4 ; + RECT 209.465 0 213.885 74.87 ; + END + PORT + LAYER Metal4 ; + RECT 191.785 0 196.205 74.87 ; + END + PORT + LAYER Metal4 ; + RECT 174.105 0 178.525 74.87 ; + END + PORT + LAYER Metal4 ; + RECT 156.425 0 160.845 74.87 ; + END + PORT + LAYER Metal4 ; + RECT 138.745 0 143.165 74.87 ; + END + PORT + LAYER Metal4 ; + RECT 121.065 0 125.485 74.87 ; + END + PORT + LAYER Metal4 ; + RECT 103.385 0 107.805 74.87 ; + END + PORT + LAYER Metal4 ; + RECT 85.705 0 90.125 74.87 ; + END + PORT + LAYER Metal4 ; + RECT 68.025 0 72.445 74.87 ; + END + PORT + LAYER Metal4 ; + RECT 50.345 0 54.765 74.87 ; + END + PORT + LAYER Metal4 ; + RECT 32.665 0 37.085 74.87 ; + END + PORT + LAYER Metal4 ; + RECT 14.985 0 19.405 74.87 ; + END + END VSS! + PIN VDD! + DIRECTION INOUT ; + USE POWER ; + NETEXPR "vdd VDD!" ; + PORT + LAYER Metal4 ; + RECT 692.265 0 696.685 47.045 ; + END + PORT + LAYER Metal4 ; + RECT 674.585 0 679.005 47.045 ; + END + PORT + LAYER Metal4 ; + RECT 656.905 0 661.325 47.045 ; + END + PORT + LAYER Metal4 ; + RECT 639.225 0 643.645 47.045 ; + END + PORT + LAYER Metal4 ; + RECT 621.545 0 625.965 47.045 ; + END + PORT + LAYER Metal4 ; + RECT 603.865 0 608.285 47.045 ; + END + PORT + LAYER Metal4 ; + RECT 586.185 0 590.605 47.045 ; + END + PORT + LAYER Metal4 ; + RECT 568.505 0 572.925 47.045 ; + END + PORT + LAYER Metal4 ; + RECT 550.825 0 555.245 47.045 ; + END + PORT + LAYER Metal4 ; + RECT 533.145 0 537.565 47.045 ; + END + PORT + LAYER Metal4 ; + RECT 515.465 0 519.885 47.045 ; + END + PORT + LAYER Metal4 ; + RECT 497.785 0 502.205 47.045 ; + END + PORT + LAYER Metal4 ; + RECT 480.105 0 484.525 47.045 ; + END + PORT + LAYER Metal4 ; + RECT 462.425 0 466.845 47.045 ; + END + PORT + LAYER Metal4 ; + RECT 444.745 0 449.165 47.045 ; + END + PORT + LAYER Metal4 ; + RECT 427.065 0 431.485 47.045 ; + END + PORT + LAYER Metal4 ; + RECT 383.485 0 386.295 74.87 ; + END + PORT + LAYER Metal4 ; + RECT 373.185 0 375.995 74.87 ; + END + PORT + LAYER Metal4 ; + RECT 368.035 0 370.845 74.87 ; + END + PORT + LAYER Metal4 ; + RECT 357.735 0 360.545 74.87 ; + END + PORT + LAYER Metal4 ; + RECT 342.285 0 345.095 74.87 ; + END + PORT + LAYER Metal4 ; + RECT 331.985 0 334.795 74.87 ; + END + PORT + LAYER Metal4 ; + RECT 326.835 0 329.645 74.87 ; + END + PORT + LAYER Metal4 ; + RECT 316.535 0 319.345 74.87 ; + END + PORT + LAYER Metal4 ; + RECT 271.345 0 275.765 47.045 ; + END + PORT + LAYER Metal4 ; + RECT 253.665 0 258.085 47.045 ; + END + PORT + LAYER Metal4 ; + RECT 235.985 0 240.405 47.045 ; + END + PORT + LAYER Metal4 ; + RECT 218.305 0 222.725 47.045 ; + END + PORT + LAYER Metal4 ; + RECT 200.625 0 205.045 47.045 ; + END + PORT + LAYER Metal4 ; + RECT 182.945 0 187.365 47.045 ; + END + PORT + LAYER Metal4 ; + RECT 165.265 0 169.685 47.045 ; + END + PORT + LAYER Metal4 ; + RECT 147.585 0 152.005 47.045 ; + END + PORT + LAYER Metal4 ; + RECT 129.905 0 134.325 47.045 ; + END + PORT + LAYER Metal4 ; + RECT 112.225 0 116.645 47.045 ; + END + PORT + LAYER Metal4 ; + RECT 94.545 0 98.965 47.045 ; + END + PORT + LAYER Metal4 ; + RECT 76.865 0 81.285 47.045 ; + END + PORT + LAYER Metal4 ; + RECT 59.185 0 63.605 47.045 ; + END + PORT + LAYER Metal4 ; + RECT 41.505 0 45.925 47.045 ; + END + PORT + LAYER Metal4 ; + RECT 23.825 0 28.245 47.045 ; + END + PORT + LAYER Metal4 ; + RECT 6.145 0 10.565 47.045 ; + END + END VDD! + PIN VDDARRAY! + DIRECTION INOUT ; + USE POWER ; + NETEXPR "vddarray VDDARRAY!" ; + PORT + LAYER Metal4 ; + RECT 692.265 53.41 696.685 74.87 ; + END + PORT + LAYER Metal4 ; + RECT 674.585 53.41 679.005 74.87 ; + END + PORT + LAYER Metal4 ; + RECT 656.905 53.41 661.325 74.87 ; + END + PORT + LAYER Metal4 ; + RECT 639.225 53.41 643.645 74.87 ; + END + PORT + LAYER Metal4 ; + RECT 621.545 53.41 625.965 74.87 ; + END + PORT + LAYER Metal4 ; + RECT 603.865 53.41 608.285 74.87 ; + END + PORT + LAYER Metal4 ; + RECT 586.185 53.41 590.605 74.87 ; + END + PORT + LAYER Metal4 ; + RECT 568.505 53.41 572.925 74.87 ; + END + PORT + LAYER Metal4 ; + RECT 550.825 53.41 555.245 74.87 ; + END + PORT + LAYER Metal4 ; + RECT 533.145 53.41 537.565 74.87 ; + END + PORT + LAYER Metal4 ; + RECT 515.465 53.41 519.885 74.87 ; + END + PORT + LAYER Metal4 ; + RECT 497.785 53.41 502.205 74.87 ; + END + PORT + LAYER Metal4 ; + RECT 480.105 53.41 484.525 74.87 ; + END + PORT + LAYER Metal4 ; + RECT 462.425 53.41 466.845 74.87 ; + END + PORT + LAYER Metal4 ; + RECT 444.745 53.41 449.165 74.87 ; + END + PORT + LAYER Metal4 ; + RECT 427.065 53.41 431.485 74.87 ; + END + PORT + LAYER Metal4 ; + RECT 271.345 53.41 275.765 74.87 ; + END + PORT + LAYER Metal4 ; + RECT 253.665 53.41 258.085 74.87 ; + END + PORT + LAYER Metal4 ; + RECT 235.985 53.41 240.405 74.87 ; + END + PORT + LAYER Metal4 ; + RECT 218.305 53.41 222.725 74.87 ; + END + PORT + LAYER Metal4 ; + RECT 200.625 53.41 205.045 74.87 ; + END + PORT + LAYER Metal4 ; + RECT 182.945 53.41 187.365 74.87 ; + END + PORT + LAYER Metal4 ; + RECT 165.265 53.41 169.685 74.87 ; + END + PORT + LAYER Metal4 ; + RECT 147.585 53.41 152.005 74.87 ; + END + PORT + LAYER Metal4 ; + RECT 129.905 53.41 134.325 74.87 ; + END + PORT + LAYER Metal4 ; + RECT 112.225 53.41 116.645 74.87 ; + END + PORT + LAYER Metal4 ; + RECT 94.545 53.41 98.965 74.87 ; + END + PORT + LAYER Metal4 ; + RECT 76.865 53.41 81.285 74.87 ; + END + PORT + LAYER Metal4 ; + RECT 59.185 53.41 63.605 74.87 ; + END + PORT + LAYER Metal4 ; + RECT 41.505 53.41 45.925 74.87 ; + END + PORT + LAYER Metal4 ; + RECT 23.825 53.41 28.245 74.87 ; + END + PORT + LAYER Metal4 ; + RECT 6.145 53.41 10.565 74.87 ; + END + END VDDARRAY! + PIN A_DIN[17] + DIRECTION INPUT ; + USE SIGNAL ; + ANTENNAPARTIALMETALAREA 3.9091 LAYER Metal2 ; + ANTENNAMODEL OXIDE1 ; + ANTENNAGATEAREA 0.20085 LAYER Metal2 ; + ANTENNAMAXAREACAR 20.368932 LAYER Metal2 ; + PORT + LAYER Metal2 ; + RECT 443.17 0 443.43 0.26 ; + END + END A_DIN[17] + PIN A_DIN[14] + DIRECTION INPUT ; + USE SIGNAL ; + ANTENNAPARTIALMETALAREA 3.9091 LAYER Metal2 ; + ANTENNAMODEL OXIDE1 ; + ANTENNAGATEAREA 0.20085 LAYER Metal2 ; + ANTENNAMAXAREACAR 20.368932 LAYER Metal2 ; + PORT + LAYER Metal2 ; + RECT 259.4 0 259.66 0.26 ; + END + END A_DIN[14] + PIN A_DOUT[17] + DIRECTION OUTPUT ; + USE SIGNAL ; + ANTENNAPARTIALMETALAREA 4.8256 LAYER Metal2 ; + ANTENNADIFFAREA 0.988 LAYER Metal2 ; + PORT + LAYER Metal2 ; + RECT 436.03 0 436.29 0.26 ; + END + END A_DOUT[17] + PIN A_DOUT[14] + DIRECTION OUTPUT ; + USE SIGNAL ; + ANTENNAPARTIALMETALAREA 4.8256 LAYER Metal2 ; + ANTENNADIFFAREA 0.988 LAYER Metal2 ; + PORT + LAYER Metal2 ; + RECT 266.54 0 266.8 0.26 ; + END + END A_DOUT[14] + PIN B_DIN[17] + DIRECTION INPUT ; + USE SIGNAL ; + ANTENNAPARTIALMETALAREA 2.925 LAYER Metal2 ; + ANTENNAMODEL OXIDE1 ; + ANTENNAGATEAREA 0.20085 LAYER Metal2 ; + ANTENNAMAXAREACAR 15.469256 LAYER Metal2 ; + PORT + LAYER Metal2 ; + RECT 445.72 0 445.98 0.26 ; + END + END B_DIN[17] + PIN B_DIN[14] + DIRECTION INPUT ; + USE SIGNAL ; + ANTENNAPARTIALMETALAREA 2.925 LAYER Metal2 ; + ANTENNAMODEL OXIDE1 ; + ANTENNAGATEAREA 0.20085 LAYER Metal2 ; + ANTENNAMAXAREACAR 15.469256 LAYER Metal2 ; + PORT + LAYER Metal2 ; + RECT 256.85 0 257.11 0.26 ; + END + END B_DIN[14] + PIN B_DOUT[17] + DIRECTION OUTPUT ; + USE SIGNAL ; + ANTENNAPARTIALMETALAREA 4.836 LAYER Metal2 ; + ANTENNADIFFAREA 0.988 LAYER Metal2 ; + PORT + LAYER Metal2 ; + RECT 452.86 0 453.12 0.26 ; + END + END B_DOUT[17] + PIN B_DOUT[14] + DIRECTION OUTPUT ; + USE SIGNAL ; + ANTENNAPARTIALMETALAREA 4.836 LAYER Metal2 ; + ANTENNADIFFAREA 0.988 LAYER Metal2 ; + PORT + LAYER Metal2 ; + RECT 249.71 0 249.97 0.26 ; + END + END B_DOUT[14] + PIN A_DIN[18] + DIRECTION INPUT ; + USE SIGNAL ; + ANTENNAPARTIALMETALAREA 3.9091 LAYER Metal2 ; + ANTENNAMODEL OXIDE1 ; + ANTENNAGATEAREA 0.20085 LAYER Metal2 ; + ANTENNAMAXAREACAR 20.368932 LAYER Metal2 ; + PORT + LAYER Metal2 ; + RECT 460.85 0 461.11 0.26 ; + END + END A_DIN[18] + PIN A_DIN[13] + DIRECTION INPUT ; + USE SIGNAL ; + ANTENNAPARTIALMETALAREA 3.9091 LAYER Metal2 ; + ANTENNAMODEL OXIDE1 ; + ANTENNAGATEAREA 0.20085 LAYER Metal2 ; + ANTENNAMAXAREACAR 20.368932 LAYER Metal2 ; + PORT + LAYER Metal2 ; + RECT 241.72 0 241.98 0.26 ; + END + END A_DIN[13] + PIN A_DOUT[18] + DIRECTION OUTPUT ; + USE SIGNAL ; + ANTENNAPARTIALMETALAREA 4.8256 LAYER Metal2 ; + ANTENNADIFFAREA 0.988 LAYER Metal2 ; + PORT + LAYER Metal2 ; + RECT 453.71 0 453.97 0.26 ; + END + END A_DOUT[18] + PIN A_DOUT[13] + DIRECTION OUTPUT ; + USE SIGNAL ; + ANTENNAPARTIALMETALAREA 4.8256 LAYER Metal2 ; + ANTENNADIFFAREA 0.988 LAYER Metal2 ; + PORT + LAYER Metal2 ; + RECT 248.86 0 249.12 0.26 ; + END + END A_DOUT[13] + PIN B_DIN[18] + DIRECTION INPUT ; + USE SIGNAL ; + ANTENNAPARTIALMETALAREA 2.925 LAYER Metal2 ; + ANTENNAMODEL OXIDE1 ; + ANTENNAGATEAREA 0.20085 LAYER Metal2 ; + ANTENNAMAXAREACAR 15.469256 LAYER Metal2 ; + PORT + LAYER Metal2 ; + RECT 463.4 0 463.66 0.26 ; + END + END B_DIN[18] + PIN B_DIN[13] + DIRECTION INPUT ; + USE SIGNAL ; + ANTENNAPARTIALMETALAREA 2.925 LAYER Metal2 ; + ANTENNAMODEL OXIDE1 ; + ANTENNAGATEAREA 0.20085 LAYER Metal2 ; + ANTENNAMAXAREACAR 15.469256 LAYER Metal2 ; + PORT + LAYER Metal2 ; + RECT 239.17 0 239.43 0.26 ; + END + END B_DIN[13] + PIN B_DOUT[18] + DIRECTION OUTPUT ; + USE SIGNAL ; + ANTENNAPARTIALMETALAREA 4.836 LAYER Metal2 ; + ANTENNADIFFAREA 0.988 LAYER Metal2 ; + PORT + LAYER Metal2 ; + RECT 470.54 0 470.8 0.26 ; + END + END B_DOUT[18] + PIN B_DOUT[13] + DIRECTION OUTPUT ; + USE SIGNAL ; + ANTENNAPARTIALMETALAREA 4.836 LAYER Metal2 ; + ANTENNADIFFAREA 0.988 LAYER Metal2 ; + PORT + LAYER Metal2 ; + RECT 232.03 0 232.29 0.26 ; + END + END B_DOUT[13] + PIN A_DIN[19] + DIRECTION INPUT ; + USE SIGNAL ; + ANTENNAPARTIALMETALAREA 3.9091 LAYER Metal2 ; + ANTENNAMODEL OXIDE1 ; + ANTENNAGATEAREA 0.20085 LAYER Metal2 ; + ANTENNAMAXAREACAR 20.368932 LAYER Metal2 ; + PORT + LAYER Metal2 ; + RECT 478.53 0 478.79 0.26 ; + END + END A_DIN[19] + PIN A_DIN[12] + DIRECTION INPUT ; + USE SIGNAL ; + ANTENNAPARTIALMETALAREA 3.9091 LAYER Metal2 ; + ANTENNAMODEL OXIDE1 ; + ANTENNAGATEAREA 0.20085 LAYER Metal2 ; + ANTENNAMAXAREACAR 20.368932 LAYER Metal2 ; + PORT + LAYER Metal2 ; + RECT 224.04 0 224.3 0.26 ; + END + END A_DIN[12] + PIN A_DOUT[19] + DIRECTION OUTPUT ; + USE SIGNAL ; + ANTENNAPARTIALMETALAREA 4.8256 LAYER Metal2 ; + ANTENNADIFFAREA 0.988 LAYER Metal2 ; + PORT + LAYER Metal2 ; + RECT 471.39 0 471.65 0.26 ; + END + END A_DOUT[19] + PIN A_DOUT[12] + DIRECTION OUTPUT ; + USE SIGNAL ; + ANTENNAPARTIALMETALAREA 4.8256 LAYER Metal2 ; + ANTENNADIFFAREA 0.988 LAYER Metal2 ; + PORT + LAYER Metal2 ; + RECT 231.18 0 231.44 0.26 ; + END + END A_DOUT[12] + PIN B_DIN[19] + DIRECTION INPUT ; + USE SIGNAL ; + ANTENNAPARTIALMETALAREA 2.925 LAYER Metal2 ; + ANTENNAMODEL OXIDE1 ; + ANTENNAGATEAREA 0.20085 LAYER Metal2 ; + ANTENNAMAXAREACAR 15.469256 LAYER Metal2 ; + PORT + LAYER Metal2 ; + RECT 481.08 0 481.34 0.26 ; + END + END B_DIN[19] + PIN B_DIN[12] + DIRECTION INPUT ; + USE SIGNAL ; + ANTENNAPARTIALMETALAREA 2.925 LAYER Metal2 ; + ANTENNAMODEL OXIDE1 ; + ANTENNAGATEAREA 0.20085 LAYER Metal2 ; + ANTENNAMAXAREACAR 15.469256 LAYER Metal2 ; + PORT + LAYER Metal2 ; + RECT 221.49 0 221.75 0.26 ; + END + END B_DIN[12] + PIN B_DOUT[19] + DIRECTION OUTPUT ; + USE SIGNAL ; + ANTENNAPARTIALMETALAREA 4.836 LAYER Metal2 ; + ANTENNADIFFAREA 0.988 LAYER Metal2 ; + PORT + LAYER Metal2 ; + RECT 488.22 0 488.48 0.26 ; + END + END B_DOUT[19] + PIN B_DOUT[12] + DIRECTION OUTPUT ; + USE SIGNAL ; + ANTENNAPARTIALMETALAREA 4.836 LAYER Metal2 ; + ANTENNADIFFAREA 0.988 LAYER Metal2 ; + PORT + LAYER Metal2 ; + RECT 214.35 0 214.61 0.26 ; + END + END B_DOUT[12] + PIN A_DIN[20] + DIRECTION INPUT ; + USE SIGNAL ; + ANTENNAPARTIALMETALAREA 3.9091 LAYER Metal2 ; + ANTENNAMODEL OXIDE1 ; + ANTENNAGATEAREA 0.20085 LAYER Metal2 ; + ANTENNAMAXAREACAR 20.368932 LAYER Metal2 ; + PORT + LAYER Metal2 ; + RECT 496.21 0 496.47 0.26 ; + END + END A_DIN[20] + PIN A_DIN[11] + DIRECTION INPUT ; + USE SIGNAL ; + ANTENNAPARTIALMETALAREA 3.9091 LAYER Metal2 ; + ANTENNAMODEL OXIDE1 ; + ANTENNAGATEAREA 0.20085 LAYER Metal2 ; + ANTENNAMAXAREACAR 20.368932 LAYER Metal2 ; + PORT + LAYER Metal2 ; + RECT 206.36 0 206.62 0.26 ; + END + END A_DIN[11] + PIN A_DOUT[20] + DIRECTION OUTPUT ; + USE SIGNAL ; + ANTENNAPARTIALMETALAREA 4.8256 LAYER Metal2 ; + ANTENNADIFFAREA 0.988 LAYER Metal2 ; + PORT + LAYER Metal2 ; + RECT 489.07 0 489.33 0.26 ; + END + END A_DOUT[20] + PIN A_DOUT[11] + DIRECTION OUTPUT ; + USE SIGNAL ; + ANTENNAPARTIALMETALAREA 4.8256 LAYER Metal2 ; + ANTENNADIFFAREA 0.988 LAYER Metal2 ; + PORT + LAYER Metal2 ; + RECT 213.5 0 213.76 0.26 ; + END + END A_DOUT[11] + PIN B_DIN[20] + DIRECTION INPUT ; + USE SIGNAL ; + ANTENNAPARTIALMETALAREA 2.925 LAYER Metal2 ; + ANTENNAMODEL OXIDE1 ; + ANTENNAGATEAREA 0.20085 LAYER Metal2 ; + ANTENNAMAXAREACAR 15.469256 LAYER Metal2 ; + PORT + LAYER Metal2 ; + RECT 498.76 0 499.02 0.26 ; + END + END B_DIN[20] + PIN B_DIN[11] + DIRECTION INPUT ; + USE SIGNAL ; + ANTENNAPARTIALMETALAREA 2.925 LAYER Metal2 ; + ANTENNAMODEL OXIDE1 ; + ANTENNAGATEAREA 0.20085 LAYER Metal2 ; + ANTENNAMAXAREACAR 15.469256 LAYER Metal2 ; + PORT + LAYER Metal2 ; + RECT 203.81 0 204.07 0.26 ; + END + END B_DIN[11] + PIN B_DOUT[20] + DIRECTION OUTPUT ; + USE SIGNAL ; + ANTENNAPARTIALMETALAREA 4.836 LAYER Metal2 ; + ANTENNADIFFAREA 0.988 LAYER Metal2 ; + PORT + LAYER Metal2 ; + RECT 505.9 0 506.16 0.26 ; + END + END B_DOUT[20] + PIN B_DOUT[11] + DIRECTION OUTPUT ; + USE SIGNAL ; + ANTENNAPARTIALMETALAREA 4.836 LAYER Metal2 ; + ANTENNADIFFAREA 0.988 LAYER Metal2 ; + PORT + LAYER Metal2 ; + RECT 196.67 0 196.93 0.26 ; + END + END B_DOUT[11] + PIN A_DIN[21] + DIRECTION INPUT ; + USE SIGNAL ; + ANTENNAPARTIALMETALAREA 3.9091 LAYER Metal2 ; + ANTENNAMODEL OXIDE1 ; + ANTENNAGATEAREA 0.20085 LAYER Metal2 ; + ANTENNAMAXAREACAR 20.368932 LAYER Metal2 ; + PORT + LAYER Metal2 ; + RECT 513.89 0 514.15 0.26 ; + END + END A_DIN[21] + PIN A_DIN[10] + DIRECTION INPUT ; + USE SIGNAL ; + ANTENNAPARTIALMETALAREA 3.9091 LAYER Metal2 ; + ANTENNAMODEL OXIDE1 ; + ANTENNAGATEAREA 0.20085 LAYER Metal2 ; + ANTENNAMAXAREACAR 20.368932 LAYER Metal2 ; + PORT + LAYER Metal2 ; + RECT 188.68 0 188.94 0.26 ; + END + END A_DIN[10] + PIN A_DOUT[21] + DIRECTION OUTPUT ; + USE SIGNAL ; + ANTENNAPARTIALMETALAREA 4.8256 LAYER Metal2 ; + ANTENNADIFFAREA 0.988 LAYER Metal2 ; + PORT + LAYER Metal2 ; + RECT 506.75 0 507.01 0.26 ; + END + END A_DOUT[21] + PIN A_DOUT[10] + DIRECTION OUTPUT ; + USE SIGNAL ; + ANTENNAPARTIALMETALAREA 4.8256 LAYER Metal2 ; + ANTENNADIFFAREA 0.988 LAYER Metal2 ; + PORT + LAYER Metal2 ; + RECT 195.82 0 196.08 0.26 ; + END + END A_DOUT[10] + PIN B_DIN[21] + DIRECTION INPUT ; + USE SIGNAL ; + ANTENNAPARTIALMETALAREA 2.925 LAYER Metal2 ; + ANTENNAMODEL OXIDE1 ; + ANTENNAGATEAREA 0.20085 LAYER Metal2 ; + ANTENNAMAXAREACAR 15.469256 LAYER Metal2 ; + PORT + LAYER Metal2 ; + RECT 516.44 0 516.7 0.26 ; + END + END B_DIN[21] + PIN B_DIN[10] + DIRECTION INPUT ; + USE SIGNAL ; + ANTENNAPARTIALMETALAREA 2.925 LAYER Metal2 ; + ANTENNAMODEL OXIDE1 ; + ANTENNAGATEAREA 0.20085 LAYER Metal2 ; + ANTENNAMAXAREACAR 15.469256 LAYER Metal2 ; + PORT + LAYER Metal2 ; + RECT 186.13 0 186.39 0.26 ; + END + END B_DIN[10] + PIN B_DOUT[21] + DIRECTION OUTPUT ; + USE SIGNAL ; + ANTENNAPARTIALMETALAREA 4.836 LAYER Metal2 ; + ANTENNADIFFAREA 0.988 LAYER Metal2 ; + PORT + LAYER Metal2 ; + RECT 523.58 0 523.84 0.26 ; + END + END B_DOUT[21] + PIN B_DOUT[10] + DIRECTION OUTPUT ; + USE SIGNAL ; + ANTENNAPARTIALMETALAREA 4.836 LAYER Metal2 ; + ANTENNADIFFAREA 0.988 LAYER Metal2 ; + PORT + LAYER Metal2 ; + RECT 178.99 0 179.25 0.26 ; + END + END B_DOUT[10] + PIN A_DIN[22] + DIRECTION INPUT ; + USE SIGNAL ; + ANTENNAPARTIALMETALAREA 3.9091 LAYER Metal2 ; + ANTENNAMODEL OXIDE1 ; + ANTENNAGATEAREA 0.20085 LAYER Metal2 ; + ANTENNAMAXAREACAR 20.368932 LAYER Metal2 ; + PORT + LAYER Metal2 ; + RECT 531.57 0 531.83 0.26 ; + END + END A_DIN[22] + PIN A_DIN[9] + DIRECTION INPUT ; + USE SIGNAL ; + ANTENNAPARTIALMETALAREA 3.9091 LAYER Metal2 ; + ANTENNAMODEL OXIDE1 ; + ANTENNAGATEAREA 0.20085 LAYER Metal2 ; + ANTENNAMAXAREACAR 20.368932 LAYER Metal2 ; + PORT + LAYER Metal2 ; + RECT 171 0 171.26 0.26 ; + END + END A_DIN[9] + PIN A_DOUT[22] + DIRECTION OUTPUT ; + USE SIGNAL ; + ANTENNAPARTIALMETALAREA 4.8256 LAYER Metal2 ; + ANTENNADIFFAREA 0.988 LAYER Metal2 ; + PORT + LAYER Metal2 ; + RECT 524.43 0 524.69 0.26 ; + END + END A_DOUT[22] + PIN A_DOUT[9] + DIRECTION OUTPUT ; + USE SIGNAL ; + ANTENNAPARTIALMETALAREA 4.8256 LAYER Metal2 ; + ANTENNADIFFAREA 0.988 LAYER Metal2 ; + PORT + LAYER Metal2 ; + RECT 178.14 0 178.4 0.26 ; + END + END A_DOUT[9] + PIN B_DIN[22] + DIRECTION INPUT ; + USE SIGNAL ; + ANTENNAPARTIALMETALAREA 2.925 LAYER Metal2 ; + ANTENNAMODEL OXIDE1 ; + ANTENNAGATEAREA 0.20085 LAYER Metal2 ; + ANTENNAMAXAREACAR 15.469256 LAYER Metal2 ; + PORT + LAYER Metal2 ; + RECT 534.12 0 534.38 0.26 ; + END + END B_DIN[22] + PIN B_DIN[9] + DIRECTION INPUT ; + USE SIGNAL ; + ANTENNAPARTIALMETALAREA 2.925 LAYER Metal2 ; + ANTENNAMODEL OXIDE1 ; + ANTENNAGATEAREA 0.20085 LAYER Metal2 ; + ANTENNAMAXAREACAR 15.469256 LAYER Metal2 ; + PORT + LAYER Metal2 ; + RECT 168.45 0 168.71 0.26 ; + END + END B_DIN[9] + PIN B_DOUT[22] + DIRECTION OUTPUT ; + USE SIGNAL ; + ANTENNAPARTIALMETALAREA 4.836 LAYER Metal2 ; + ANTENNADIFFAREA 0.988 LAYER Metal2 ; + PORT + LAYER Metal2 ; + RECT 541.26 0 541.52 0.26 ; + END + END B_DOUT[22] + PIN B_DOUT[9] + DIRECTION OUTPUT ; + USE SIGNAL ; + ANTENNAPARTIALMETALAREA 4.836 LAYER Metal2 ; + ANTENNADIFFAREA 0.988 LAYER Metal2 ; + PORT + LAYER Metal2 ; + RECT 161.31 0 161.57 0.26 ; + END + END B_DOUT[9] + PIN A_DIN[23] + DIRECTION INPUT ; + USE SIGNAL ; + ANTENNAPARTIALMETALAREA 3.9091 LAYER Metal2 ; + ANTENNAMODEL OXIDE1 ; + ANTENNAGATEAREA 0.20085 LAYER Metal2 ; + ANTENNAMAXAREACAR 20.368932 LAYER Metal2 ; + PORT + LAYER Metal2 ; + RECT 549.25 0 549.51 0.26 ; + END + END A_DIN[23] + PIN A_DIN[8] + DIRECTION INPUT ; + USE SIGNAL ; + ANTENNAPARTIALMETALAREA 3.9091 LAYER Metal2 ; + ANTENNAMODEL OXIDE1 ; + ANTENNAGATEAREA 0.20085 LAYER Metal2 ; + ANTENNAMAXAREACAR 20.368932 LAYER Metal2 ; + PORT + LAYER Metal2 ; + RECT 153.32 0 153.58 0.26 ; + END + END A_DIN[8] + PIN A_DOUT[23] + DIRECTION OUTPUT ; + USE SIGNAL ; + ANTENNAPARTIALMETALAREA 4.8256 LAYER Metal2 ; + ANTENNADIFFAREA 0.988 LAYER Metal2 ; + PORT + LAYER Metal2 ; + RECT 542.11 0 542.37 0.26 ; + END + END A_DOUT[23] + PIN A_DOUT[8] + DIRECTION OUTPUT ; + USE SIGNAL ; + ANTENNAPARTIALMETALAREA 4.8256 LAYER Metal2 ; + ANTENNADIFFAREA 0.988 LAYER Metal2 ; + PORT + LAYER Metal2 ; + RECT 160.46 0 160.72 0.26 ; + END + END A_DOUT[8] + PIN B_DIN[23] + DIRECTION INPUT ; + USE SIGNAL ; + ANTENNAPARTIALMETALAREA 2.925 LAYER Metal2 ; + ANTENNAMODEL OXIDE1 ; + ANTENNAGATEAREA 0.20085 LAYER Metal2 ; + ANTENNAMAXAREACAR 15.469256 LAYER Metal2 ; + PORT + LAYER Metal2 ; + RECT 551.8 0 552.06 0.26 ; + END + END B_DIN[23] + PIN B_DIN[8] + DIRECTION INPUT ; + USE SIGNAL ; + ANTENNAPARTIALMETALAREA 2.925 LAYER Metal2 ; + ANTENNAMODEL OXIDE1 ; + ANTENNAGATEAREA 0.20085 LAYER Metal2 ; + ANTENNAMAXAREACAR 15.469256 LAYER Metal2 ; + PORT + LAYER Metal2 ; + RECT 150.77 0 151.03 0.26 ; + END + END B_DIN[8] + PIN B_DOUT[23] + DIRECTION OUTPUT ; + USE SIGNAL ; + ANTENNAPARTIALMETALAREA 4.836 LAYER Metal2 ; + ANTENNADIFFAREA 0.988 LAYER Metal2 ; + PORT + LAYER Metal2 ; + RECT 558.94 0 559.2 0.26 ; + END + END B_DOUT[23] + PIN B_DOUT[8] + DIRECTION OUTPUT ; + USE SIGNAL ; + ANTENNAPARTIALMETALAREA 4.836 LAYER Metal2 ; + ANTENNADIFFAREA 0.988 LAYER Metal2 ; + PORT + LAYER Metal2 ; + RECT 143.63 0 143.89 0.26 ; + END + END B_DOUT[8] + PIN A_DIN[24] + DIRECTION INPUT ; + USE SIGNAL ; + ANTENNAPARTIALMETALAREA 3.9091 LAYER Metal2 ; + ANTENNAMODEL OXIDE1 ; + ANTENNAGATEAREA 0.20085 LAYER Metal2 ; + ANTENNAMAXAREACAR 20.368932 LAYER Metal2 ; + PORT + LAYER Metal2 ; + RECT 566.93 0 567.19 0.26 ; + END + END A_DIN[24] + PIN A_DIN[7] + DIRECTION INPUT ; + USE SIGNAL ; + ANTENNAPARTIALMETALAREA 3.9091 LAYER Metal2 ; + ANTENNAMODEL OXIDE1 ; + ANTENNAGATEAREA 0.20085 LAYER Metal2 ; + ANTENNAMAXAREACAR 20.368932 LAYER Metal2 ; + PORT + LAYER Metal2 ; + RECT 135.64 0 135.9 0.26 ; + END + END A_DIN[7] + PIN A_DOUT[24] + DIRECTION OUTPUT ; + USE SIGNAL ; + ANTENNAPARTIALMETALAREA 4.8256 LAYER Metal2 ; + ANTENNADIFFAREA 0.988 LAYER Metal2 ; + PORT + LAYER Metal2 ; + RECT 559.79 0 560.05 0.26 ; + END + END A_DOUT[24] + PIN A_DOUT[7] + DIRECTION OUTPUT ; + USE SIGNAL ; + ANTENNAPARTIALMETALAREA 4.8256 LAYER Metal2 ; + ANTENNADIFFAREA 0.988 LAYER Metal2 ; + PORT + LAYER Metal2 ; + RECT 142.78 0 143.04 0.26 ; + END + END A_DOUT[7] + PIN B_DIN[24] + DIRECTION INPUT ; + USE SIGNAL ; + ANTENNAPARTIALMETALAREA 2.925 LAYER Metal2 ; + ANTENNAMODEL OXIDE1 ; + ANTENNAGATEAREA 0.20085 LAYER Metal2 ; + ANTENNAMAXAREACAR 15.469256 LAYER Metal2 ; + PORT + LAYER Metal2 ; + RECT 569.48 0 569.74 0.26 ; + END + END B_DIN[24] + PIN B_DIN[7] + DIRECTION INPUT ; + USE SIGNAL ; + ANTENNAPARTIALMETALAREA 2.925 LAYER Metal2 ; + ANTENNAMODEL OXIDE1 ; + ANTENNAGATEAREA 0.20085 LAYER Metal2 ; + ANTENNAMAXAREACAR 15.469256 LAYER Metal2 ; + PORT + LAYER Metal2 ; + RECT 133.09 0 133.35 0.26 ; + END + END B_DIN[7] + PIN B_DOUT[24] + DIRECTION OUTPUT ; + USE SIGNAL ; + ANTENNAPARTIALMETALAREA 4.836 LAYER Metal2 ; + ANTENNADIFFAREA 0.988 LAYER Metal2 ; + PORT + LAYER Metal2 ; + RECT 576.62 0 576.88 0.26 ; + END + END B_DOUT[24] + PIN B_DOUT[7] + DIRECTION OUTPUT ; + USE SIGNAL ; + ANTENNAPARTIALMETALAREA 4.836 LAYER Metal2 ; + ANTENNADIFFAREA 0.988 LAYER Metal2 ; + PORT + LAYER Metal2 ; + RECT 125.95 0 126.21 0.26 ; + END + END B_DOUT[7] + PIN A_DIN[25] + DIRECTION INPUT ; + USE SIGNAL ; + ANTENNAPARTIALMETALAREA 3.9091 LAYER Metal2 ; + ANTENNAMODEL OXIDE1 ; + ANTENNAGATEAREA 0.20085 LAYER Metal2 ; + ANTENNAMAXAREACAR 20.368932 LAYER Metal2 ; + PORT + LAYER Metal2 ; + RECT 584.61 0 584.87 0.26 ; + END + END A_DIN[25] + PIN A_DIN[6] + DIRECTION INPUT ; + USE SIGNAL ; + ANTENNAPARTIALMETALAREA 3.9091 LAYER Metal2 ; + ANTENNAMODEL OXIDE1 ; + ANTENNAGATEAREA 0.20085 LAYER Metal2 ; + ANTENNAMAXAREACAR 20.368932 LAYER Metal2 ; + PORT + LAYER Metal2 ; + RECT 117.96 0 118.22 0.26 ; + END + END A_DIN[6] + PIN A_DOUT[25] + DIRECTION OUTPUT ; + USE SIGNAL ; + ANTENNAPARTIALMETALAREA 4.8256 LAYER Metal2 ; + ANTENNADIFFAREA 0.988 LAYER Metal2 ; + PORT + LAYER Metal2 ; + RECT 577.47 0 577.73 0.26 ; + END + END A_DOUT[25] + PIN A_DOUT[6] + DIRECTION OUTPUT ; + USE SIGNAL ; + ANTENNAPARTIALMETALAREA 4.8256 LAYER Metal2 ; + ANTENNADIFFAREA 0.988 LAYER Metal2 ; + PORT + LAYER Metal2 ; + RECT 125.1 0 125.36 0.26 ; + END + END A_DOUT[6] + PIN B_DIN[25] + DIRECTION INPUT ; + USE SIGNAL ; + ANTENNAPARTIALMETALAREA 2.925 LAYER Metal2 ; + ANTENNAMODEL OXIDE1 ; + ANTENNAGATEAREA 0.20085 LAYER Metal2 ; + ANTENNAMAXAREACAR 15.469256 LAYER Metal2 ; + PORT + LAYER Metal2 ; + RECT 587.16 0 587.42 0.26 ; + END + END B_DIN[25] + PIN B_DIN[6] + DIRECTION INPUT ; + USE SIGNAL ; + ANTENNAPARTIALMETALAREA 2.925 LAYER Metal2 ; + ANTENNAMODEL OXIDE1 ; + ANTENNAGATEAREA 0.20085 LAYER Metal2 ; + ANTENNAMAXAREACAR 15.469256 LAYER Metal2 ; + PORT + LAYER Metal2 ; + RECT 115.41 0 115.67 0.26 ; + END + END B_DIN[6] + PIN B_DOUT[25] + DIRECTION OUTPUT ; + USE SIGNAL ; + ANTENNAPARTIALMETALAREA 4.836 LAYER Metal2 ; + ANTENNADIFFAREA 0.988 LAYER Metal2 ; + PORT + LAYER Metal2 ; + RECT 594.3 0 594.56 0.26 ; + END + END B_DOUT[25] + PIN B_DOUT[6] + DIRECTION OUTPUT ; + USE SIGNAL ; + ANTENNAPARTIALMETALAREA 4.836 LAYER Metal2 ; + ANTENNADIFFAREA 0.988 LAYER Metal2 ; + PORT + LAYER Metal2 ; + RECT 108.27 0 108.53 0.26 ; + END + END B_DOUT[6] + PIN A_DIN[26] + DIRECTION INPUT ; + USE SIGNAL ; + ANTENNAPARTIALMETALAREA 3.9091 LAYER Metal2 ; + ANTENNAMODEL OXIDE1 ; + ANTENNAGATEAREA 0.20085 LAYER Metal2 ; + ANTENNAMAXAREACAR 20.368932 LAYER Metal2 ; + PORT + LAYER Metal2 ; + RECT 602.29 0 602.55 0.26 ; + END + END A_DIN[26] + PIN A_DIN[5] + DIRECTION INPUT ; + USE SIGNAL ; + ANTENNAPARTIALMETALAREA 3.9091 LAYER Metal2 ; + ANTENNAMODEL OXIDE1 ; + ANTENNAGATEAREA 0.20085 LAYER Metal2 ; + ANTENNAMAXAREACAR 20.368932 LAYER Metal2 ; + PORT + LAYER Metal2 ; + RECT 100.28 0 100.54 0.26 ; + END + END A_DIN[5] + PIN A_DOUT[26] + DIRECTION OUTPUT ; + USE SIGNAL ; + ANTENNAPARTIALMETALAREA 4.8256 LAYER Metal2 ; + ANTENNADIFFAREA 0.988 LAYER Metal2 ; + PORT + LAYER Metal2 ; + RECT 595.15 0 595.41 0.26 ; + END + END A_DOUT[26] + PIN A_DOUT[5] + DIRECTION OUTPUT ; + USE SIGNAL ; + ANTENNAPARTIALMETALAREA 4.8256 LAYER Metal2 ; + ANTENNADIFFAREA 0.988 LAYER Metal2 ; + PORT + LAYER Metal2 ; + RECT 107.42 0 107.68 0.26 ; + END + END A_DOUT[5] + PIN B_DIN[26] + DIRECTION INPUT ; + USE SIGNAL ; + ANTENNAPARTIALMETALAREA 2.925 LAYER Metal2 ; + ANTENNAMODEL OXIDE1 ; + ANTENNAGATEAREA 0.20085 LAYER Metal2 ; + ANTENNAMAXAREACAR 15.469256 LAYER Metal2 ; + PORT + LAYER Metal2 ; + RECT 604.84 0 605.1 0.26 ; + END + END B_DIN[26] + PIN B_DIN[5] + DIRECTION INPUT ; + USE SIGNAL ; + ANTENNAPARTIALMETALAREA 2.925 LAYER Metal2 ; + ANTENNAMODEL OXIDE1 ; + ANTENNAGATEAREA 0.20085 LAYER Metal2 ; + ANTENNAMAXAREACAR 15.469256 LAYER Metal2 ; + PORT + LAYER Metal2 ; + RECT 97.73 0 97.99 0.26 ; + END + END B_DIN[5] + PIN B_DOUT[26] + DIRECTION OUTPUT ; + USE SIGNAL ; + ANTENNAPARTIALMETALAREA 4.836 LAYER Metal2 ; + ANTENNADIFFAREA 0.988 LAYER Metal2 ; + PORT + LAYER Metal2 ; + RECT 611.98 0 612.24 0.26 ; + END + END B_DOUT[26] + PIN B_DOUT[5] + DIRECTION OUTPUT ; + USE SIGNAL ; + ANTENNAPARTIALMETALAREA 4.836 LAYER Metal2 ; + ANTENNADIFFAREA 0.988 LAYER Metal2 ; + PORT + LAYER Metal2 ; + RECT 90.59 0 90.85 0.26 ; + END + END B_DOUT[5] + PIN A_DIN[27] + DIRECTION INPUT ; + USE SIGNAL ; + ANTENNAPARTIALMETALAREA 3.9091 LAYER Metal2 ; + ANTENNAMODEL OXIDE1 ; + ANTENNAGATEAREA 0.20085 LAYER Metal2 ; + ANTENNAMAXAREACAR 20.368932 LAYER Metal2 ; + PORT + LAYER Metal2 ; + RECT 619.97 0 620.23 0.26 ; + END + END A_DIN[27] + PIN A_DIN[4] + DIRECTION INPUT ; + USE SIGNAL ; + ANTENNAPARTIALMETALAREA 3.9091 LAYER Metal2 ; + ANTENNAMODEL OXIDE1 ; + ANTENNAGATEAREA 0.20085 LAYER Metal2 ; + ANTENNAMAXAREACAR 20.368932 LAYER Metal2 ; + PORT + LAYER Metal2 ; + RECT 82.6 0 82.86 0.26 ; + END + END A_DIN[4] + PIN A_DOUT[27] + DIRECTION OUTPUT ; + USE SIGNAL ; + ANTENNAPARTIALMETALAREA 4.8256 LAYER Metal2 ; + ANTENNADIFFAREA 0.988 LAYER Metal2 ; + PORT + LAYER Metal2 ; + RECT 612.83 0 613.09 0.26 ; + END + END A_DOUT[27] + PIN A_DOUT[4] + DIRECTION OUTPUT ; + USE SIGNAL ; + ANTENNAPARTIALMETALAREA 4.8256 LAYER Metal2 ; + ANTENNADIFFAREA 0.988 LAYER Metal2 ; + PORT + LAYER Metal2 ; + RECT 89.74 0 90 0.26 ; + END + END A_DOUT[4] + PIN B_DIN[27] + DIRECTION INPUT ; + USE SIGNAL ; + ANTENNAPARTIALMETALAREA 2.925 LAYER Metal2 ; + ANTENNAMODEL OXIDE1 ; + ANTENNAGATEAREA 0.20085 LAYER Metal2 ; + ANTENNAMAXAREACAR 15.469256 LAYER Metal2 ; + PORT + LAYER Metal2 ; + RECT 622.52 0 622.78 0.26 ; + END + END B_DIN[27] + PIN B_DIN[4] + DIRECTION INPUT ; + USE SIGNAL ; + ANTENNAPARTIALMETALAREA 2.925 LAYER Metal2 ; + ANTENNAMODEL OXIDE1 ; + ANTENNAGATEAREA 0.20085 LAYER Metal2 ; + ANTENNAMAXAREACAR 15.469256 LAYER Metal2 ; + PORT + LAYER Metal2 ; + RECT 80.05 0 80.31 0.26 ; + END + END B_DIN[4] + PIN B_DOUT[27] + DIRECTION OUTPUT ; + USE SIGNAL ; + ANTENNAPARTIALMETALAREA 4.836 LAYER Metal2 ; + ANTENNADIFFAREA 0.988 LAYER Metal2 ; + PORT + LAYER Metal2 ; + RECT 629.66 0 629.92 0.26 ; + END + END B_DOUT[27] + PIN B_DOUT[4] + DIRECTION OUTPUT ; + USE SIGNAL ; + ANTENNAPARTIALMETALAREA 4.836 LAYER Metal2 ; + ANTENNADIFFAREA 0.988 LAYER Metal2 ; + PORT + LAYER Metal2 ; + RECT 72.91 0 73.17 0.26 ; + END + END B_DOUT[4] + PIN A_DIN[28] + DIRECTION INPUT ; + USE SIGNAL ; + ANTENNAPARTIALMETALAREA 3.9091 LAYER Metal2 ; + ANTENNAMODEL OXIDE1 ; + ANTENNAGATEAREA 0.20085 LAYER Metal2 ; + ANTENNAMAXAREACAR 20.368932 LAYER Metal2 ; + PORT + LAYER Metal2 ; + RECT 637.65 0 637.91 0.26 ; + END + END A_DIN[28] + PIN A_DIN[3] + DIRECTION INPUT ; + USE SIGNAL ; + ANTENNAPARTIALMETALAREA 3.9091 LAYER Metal2 ; + ANTENNAMODEL OXIDE1 ; + ANTENNAGATEAREA 0.20085 LAYER Metal2 ; + ANTENNAMAXAREACAR 20.368932 LAYER Metal2 ; + PORT + LAYER Metal2 ; + RECT 64.92 0 65.18 0.26 ; + END + END A_DIN[3] + PIN A_DOUT[28] + DIRECTION OUTPUT ; + USE SIGNAL ; + ANTENNAPARTIALMETALAREA 4.8256 LAYER Metal2 ; + ANTENNADIFFAREA 0.988 LAYER Metal2 ; + PORT + LAYER Metal2 ; + RECT 630.51 0 630.77 0.26 ; + END + END A_DOUT[28] + PIN A_DOUT[3] + DIRECTION OUTPUT ; + USE SIGNAL ; + ANTENNAPARTIALMETALAREA 4.8256 LAYER Metal2 ; + ANTENNADIFFAREA 0.988 LAYER Metal2 ; + PORT + LAYER Metal2 ; + RECT 72.06 0 72.32 0.26 ; + END + END A_DOUT[3] + PIN B_DIN[28] + DIRECTION INPUT ; + USE SIGNAL ; + ANTENNAPARTIALMETALAREA 2.925 LAYER Metal2 ; + ANTENNAMODEL OXIDE1 ; + ANTENNAGATEAREA 0.20085 LAYER Metal2 ; + ANTENNAMAXAREACAR 15.469256 LAYER Metal2 ; + PORT + LAYER Metal2 ; + RECT 640.2 0 640.46 0.26 ; + END + END B_DIN[28] + PIN B_DIN[3] + DIRECTION INPUT ; + USE SIGNAL ; + ANTENNAPARTIALMETALAREA 2.925 LAYER Metal2 ; + ANTENNAMODEL OXIDE1 ; + ANTENNAGATEAREA 0.20085 LAYER Metal2 ; + ANTENNAMAXAREACAR 15.469256 LAYER Metal2 ; + PORT + LAYER Metal2 ; + RECT 62.37 0 62.63 0.26 ; + END + END B_DIN[3] + PIN B_DOUT[28] + DIRECTION OUTPUT ; + USE SIGNAL ; + ANTENNAPARTIALMETALAREA 4.836 LAYER Metal2 ; + ANTENNADIFFAREA 0.988 LAYER Metal2 ; + PORT + LAYER Metal2 ; + RECT 647.34 0 647.6 0.26 ; + END + END B_DOUT[28] + PIN B_DOUT[3] + DIRECTION OUTPUT ; + USE SIGNAL ; + ANTENNAPARTIALMETALAREA 4.836 LAYER Metal2 ; + ANTENNADIFFAREA 0.988 LAYER Metal2 ; + PORT + LAYER Metal2 ; + RECT 55.23 0 55.49 0.26 ; + END + END B_DOUT[3] + PIN A_DIN[29] + DIRECTION INPUT ; + USE SIGNAL ; + ANTENNAPARTIALMETALAREA 3.9091 LAYER Metal2 ; + ANTENNAMODEL OXIDE1 ; + ANTENNAGATEAREA 0.20085 LAYER Metal2 ; + ANTENNAMAXAREACAR 20.368932 LAYER Metal2 ; + PORT + LAYER Metal2 ; + RECT 655.33 0 655.59 0.26 ; + END + END A_DIN[29] + PIN A_DIN[2] + DIRECTION INPUT ; + USE SIGNAL ; + ANTENNAPARTIALMETALAREA 3.9091 LAYER Metal2 ; + ANTENNAMODEL OXIDE1 ; + ANTENNAGATEAREA 0.20085 LAYER Metal2 ; + ANTENNAMAXAREACAR 20.368932 LAYER Metal2 ; + PORT + LAYER Metal2 ; + RECT 47.24 0 47.5 0.26 ; + END + END A_DIN[2] + PIN A_DOUT[29] + DIRECTION OUTPUT ; + USE SIGNAL ; + ANTENNAPARTIALMETALAREA 4.8256 LAYER Metal2 ; + ANTENNADIFFAREA 0.988 LAYER Metal2 ; + PORT + LAYER Metal2 ; + RECT 648.19 0 648.45 0.26 ; + END + END A_DOUT[29] + PIN A_DOUT[2] + DIRECTION OUTPUT ; + USE SIGNAL ; + ANTENNAPARTIALMETALAREA 4.8256 LAYER Metal2 ; + ANTENNADIFFAREA 0.988 LAYER Metal2 ; + PORT + LAYER Metal2 ; + RECT 54.38 0 54.64 0.26 ; + END + END A_DOUT[2] + PIN B_DIN[29] + DIRECTION INPUT ; + USE SIGNAL ; + ANTENNAPARTIALMETALAREA 2.925 LAYER Metal2 ; + ANTENNAMODEL OXIDE1 ; + ANTENNAGATEAREA 0.20085 LAYER Metal2 ; + ANTENNAMAXAREACAR 15.469256 LAYER Metal2 ; + PORT + LAYER Metal2 ; + RECT 657.88 0 658.14 0.26 ; + END + END B_DIN[29] + PIN B_DIN[2] + DIRECTION INPUT ; + USE SIGNAL ; + ANTENNAPARTIALMETALAREA 2.925 LAYER Metal2 ; + ANTENNAMODEL OXIDE1 ; + ANTENNAGATEAREA 0.20085 LAYER Metal2 ; + ANTENNAMAXAREACAR 15.469256 LAYER Metal2 ; + PORT + LAYER Metal2 ; + RECT 44.69 0 44.95 0.26 ; + END + END B_DIN[2] + PIN B_DOUT[29] + DIRECTION OUTPUT ; + USE SIGNAL ; + ANTENNAPARTIALMETALAREA 4.836 LAYER Metal2 ; + ANTENNADIFFAREA 0.988 LAYER Metal2 ; + PORT + LAYER Metal2 ; + RECT 665.02 0 665.28 0.26 ; + END + END B_DOUT[29] + PIN B_DOUT[2] + DIRECTION OUTPUT ; + USE SIGNAL ; + ANTENNAPARTIALMETALAREA 4.836 LAYER Metal2 ; + ANTENNADIFFAREA 0.988 LAYER Metal2 ; + PORT + LAYER Metal2 ; + RECT 37.55 0 37.81 0.26 ; + END + END B_DOUT[2] + PIN A_DIN[30] + DIRECTION INPUT ; + USE SIGNAL ; + ANTENNAPARTIALMETALAREA 3.9091 LAYER Metal2 ; + ANTENNAMODEL OXIDE1 ; + ANTENNAGATEAREA 0.20085 LAYER Metal2 ; + ANTENNAMAXAREACAR 20.368932 LAYER Metal2 ; + PORT + LAYER Metal2 ; + RECT 673.01 0 673.27 0.26 ; + END + END A_DIN[30] + PIN A_DIN[1] + DIRECTION INPUT ; + USE SIGNAL ; + ANTENNAPARTIALMETALAREA 3.9091 LAYER Metal2 ; + ANTENNAMODEL OXIDE1 ; + ANTENNAGATEAREA 0.20085 LAYER Metal2 ; + ANTENNAMAXAREACAR 20.368932 LAYER Metal2 ; + PORT + LAYER Metal2 ; + RECT 29.56 0 29.82 0.26 ; + END + END A_DIN[1] + PIN A_DOUT[30] + DIRECTION OUTPUT ; + USE SIGNAL ; + ANTENNAPARTIALMETALAREA 4.8256 LAYER Metal2 ; + ANTENNADIFFAREA 0.988 LAYER Metal2 ; + PORT + LAYER Metal2 ; + RECT 665.87 0 666.13 0.26 ; + END + END A_DOUT[30] + PIN A_DOUT[1] + DIRECTION OUTPUT ; + USE SIGNAL ; + ANTENNAPARTIALMETALAREA 4.8256 LAYER Metal2 ; + ANTENNADIFFAREA 0.988 LAYER Metal2 ; + PORT + LAYER Metal2 ; + RECT 36.7 0 36.96 0.26 ; + END + END A_DOUT[1] + PIN B_DIN[30] + DIRECTION INPUT ; + USE SIGNAL ; + ANTENNAPARTIALMETALAREA 2.925 LAYER Metal2 ; + ANTENNAMODEL OXIDE1 ; + ANTENNAGATEAREA 0.20085 LAYER Metal2 ; + ANTENNAMAXAREACAR 15.469256 LAYER Metal2 ; + PORT + LAYER Metal2 ; + RECT 675.56 0 675.82 0.26 ; + END + END B_DIN[30] + PIN B_DIN[1] + DIRECTION INPUT ; + USE SIGNAL ; + ANTENNAPARTIALMETALAREA 2.925 LAYER Metal2 ; + ANTENNAMODEL OXIDE1 ; + ANTENNAGATEAREA 0.20085 LAYER Metal2 ; + ANTENNAMAXAREACAR 15.469256 LAYER Metal2 ; + PORT + LAYER Metal2 ; + RECT 27.01 0 27.27 0.26 ; + END + END B_DIN[1] + PIN B_DOUT[30] + DIRECTION OUTPUT ; + USE SIGNAL ; + ANTENNAPARTIALMETALAREA 4.836 LAYER Metal2 ; + ANTENNADIFFAREA 0.988 LAYER Metal2 ; + PORT + LAYER Metal2 ; + RECT 682.7 0 682.96 0.26 ; + END + END B_DOUT[30] + PIN B_DOUT[1] + DIRECTION OUTPUT ; + USE SIGNAL ; + ANTENNAPARTIALMETALAREA 4.836 LAYER Metal2 ; + ANTENNADIFFAREA 0.988 LAYER Metal2 ; + PORT + LAYER Metal2 ; + RECT 19.87 0 20.13 0.26 ; + END + END B_DOUT[1] + PIN A_DIN[31] + DIRECTION INPUT ; + USE SIGNAL ; + ANTENNAPARTIALMETALAREA 3.9091 LAYER Metal2 ; + ANTENNAMODEL OXIDE1 ; + ANTENNAGATEAREA 0.20085 LAYER Metal2 ; + ANTENNAMAXAREACAR 20.368932 LAYER Metal2 ; + PORT + LAYER Metal2 ; + RECT 690.69 0 690.95 0.26 ; + END + END A_DIN[31] + PIN A_DIN[0] + DIRECTION INPUT ; + USE SIGNAL ; + ANTENNAPARTIALMETALAREA 3.9091 LAYER Metal2 ; + ANTENNAMODEL OXIDE1 ; + ANTENNAGATEAREA 0.20085 LAYER Metal2 ; + ANTENNAMAXAREACAR 20.368932 LAYER Metal2 ; + PORT + LAYER Metal2 ; + RECT 11.88 0 12.14 0.26 ; + END + END A_DIN[0] + PIN A_DOUT[31] + DIRECTION OUTPUT ; + USE SIGNAL ; + ANTENNAPARTIALMETALAREA 4.8256 LAYER Metal2 ; + ANTENNADIFFAREA 0.988 LAYER Metal2 ; + PORT + LAYER Metal2 ; + RECT 683.55 0 683.81 0.26 ; + END + END A_DOUT[31] + PIN A_DOUT[0] + DIRECTION OUTPUT ; + USE SIGNAL ; + ANTENNAPARTIALMETALAREA 4.8256 LAYER Metal2 ; + ANTENNADIFFAREA 0.988 LAYER Metal2 ; + PORT + LAYER Metal2 ; + RECT 19.02 0 19.28 0.26 ; + END + END A_DOUT[0] + PIN B_DIN[31] + DIRECTION INPUT ; + USE SIGNAL ; + ANTENNAPARTIALMETALAREA 2.925 LAYER Metal2 ; + ANTENNAMODEL OXIDE1 ; + ANTENNAGATEAREA 0.20085 LAYER Metal2 ; + ANTENNAMAXAREACAR 15.469256 LAYER Metal2 ; + PORT + LAYER Metal2 ; + RECT 693.24 0 693.5 0.26 ; + END + END B_DIN[31] + PIN B_DIN[0] + DIRECTION INPUT ; + USE SIGNAL ; + ANTENNAPARTIALMETALAREA 2.925 LAYER Metal2 ; + ANTENNAMODEL OXIDE1 ; + ANTENNAGATEAREA 0.20085 LAYER Metal2 ; + ANTENNAMAXAREACAR 15.469256 LAYER Metal2 ; + PORT + LAYER Metal2 ; + RECT 9.33 0 9.59 0.26 ; + END + END B_DIN[0] + PIN B_DOUT[31] + DIRECTION OUTPUT ; + USE SIGNAL ; + ANTENNAPARTIALMETALAREA 4.836 LAYER Metal2 ; + ANTENNADIFFAREA 0.988 LAYER Metal2 ; + PORT + LAYER Metal2 ; + RECT 700.38 0 700.64 0.26 ; + END + END B_DOUT[31] + PIN B_DOUT[0] + DIRECTION OUTPUT ; + USE SIGNAL ; + ANTENNAPARTIALMETALAREA 4.836 LAYER Metal2 ; + ANTENNADIFFAREA 0.988 LAYER Metal2 ; + PORT + LAYER Metal2 ; + RECT 2.19 0 2.45 0.26 ; + END + END B_DOUT[0] + PIN A_ADDR[0] + DIRECTION INPUT ; + USE SIGNAL ; + ANTENNAPARTIALMETALAREA 8.7685 LAYER Metal2 ; + ANTENNAMODEL OXIDE1 ; + ANTENNAGATEAREA 0.20085 LAYER Metal2 ; + ANTENNAMAXAREACAR 44.563107 LAYER Metal2 ; + PORT + LAYER Metal2 ; + RECT 367.505 0 367.765 0.26 ; + END + END A_ADDR[0] + PIN B_ADDR[0] + DIRECTION INPUT ; + USE SIGNAL ; + ANTENNAPARTIALMETALAREA 8.7685 LAYER Metal2 ; + ANTENNAMODEL OXIDE1 ; + ANTENNAGATEAREA 0.20085 LAYER Metal2 ; + ANTENNAMAXAREACAR 44.563107 LAYER Metal2 ; + PORT + LAYER Metal2 ; + RECT 335.065 0 335.325 0.26 ; + END + END B_ADDR[0] + PIN A_ADDR[1] + DIRECTION INPUT ; + USE SIGNAL ; + ANTENNAPARTIALMETALAREA 11.0851 LAYER Metal2 ; + ANTENNAMODEL OXIDE1 ; + ANTENNAGATEAREA 0.20085 LAYER Metal2 ; + ANTENNAMAXAREACAR 56.097087 LAYER Metal2 ; + PORT + LAYER Metal2 ; + RECT 368.015 0 368.275 0.26 ; + END + END A_ADDR[1] + PIN B_ADDR[1] + DIRECTION INPUT ; + USE SIGNAL ; + ANTENNAPARTIALMETALAREA 11.0851 LAYER Metal2 ; + ANTENNAMODEL OXIDE1 ; + ANTENNAGATEAREA 0.20085 LAYER Metal2 ; + ANTENNAMAXAREACAR 56.097087 LAYER Metal2 ; + PORT + LAYER Metal2 ; + RECT 334.555 0 334.815 0.26 ; + END + END B_ADDR[1] + PIN A_ADDR[2] + DIRECTION INPUT ; + USE SIGNAL ; + ANTENNAPARTIALMETALAREA 13.0819 LAYER Metal2 ; + ANTENNAPARTIALMETALAREA 1.5246 LAYER Metal3 ; + ANTENNAPARTIALCUTAREA 0.0722 LAYER Via2 ; + ANTENNAMODEL OXIDE1 ; + ANTENNAGATEAREA 0.20085 LAYER Metal3 ; + ANTENNAMAXAREACAR 9.415982 LAYER Metal3 ; + PORT + LAYER Metal2 ; + RECT 376.685 0 376.945 0.26 ; + END + END A_ADDR[2] + PIN B_ADDR[2] + DIRECTION INPUT ; + USE SIGNAL ; + ANTENNAPARTIALMETALAREA 13.0819 LAYER Metal2 ; + ANTENNAPARTIALMETALAREA 1.5246 LAYER Metal3 ; + ANTENNAPARTIALCUTAREA 0.0722 LAYER Via2 ; + ANTENNAMODEL OXIDE1 ; + ANTENNAGATEAREA 0.20085 LAYER Metal3 ; + ANTENNAMAXAREACAR 9.415982 LAYER Metal3 ; + PORT + LAYER Metal2 ; + RECT 325.885 0 326.145 0.26 ; + END + END B_ADDR[2] + PIN A_ADDR[3] + DIRECTION INPUT ; + USE SIGNAL ; + ANTENNAPARTIALMETALAREA 13.0819 LAYER Metal2 ; + ANTENNAPARTIALMETALAREA 3.9459 LAYER Metal3 ; + ANTENNAPARTIALCUTAREA 0.0722 LAYER Via2 ; + ANTENNAMODEL OXIDE1 ; + ANTENNAGATEAREA 0.20085 LAYER Metal3 ; + ANTENNAMAXAREACAR 21.471247 LAYER Metal3 ; + PORT + LAYER Metal2 ; + RECT 375.665 0 375.925 0.26 ; + END + END A_ADDR[3] + PIN B_ADDR[3] + DIRECTION INPUT ; + USE SIGNAL ; + ANTENNAPARTIALMETALAREA 13.0819 LAYER Metal2 ; + ANTENNAPARTIALMETALAREA 3.9459 LAYER Metal3 ; + ANTENNAPARTIALCUTAREA 0.0722 LAYER Via2 ; + ANTENNAMODEL OXIDE1 ; + ANTENNAGATEAREA 0.20085 LAYER Metal3 ; + ANTENNAMAXAREACAR 21.471247 LAYER Metal3 ; + PORT + LAYER Metal2 ; + RECT 326.905 0 327.165 0.26 ; + END + END B_ADDR[3] + PIN A_ADDR[4] + DIRECTION INPUT ; + USE SIGNAL ; + ANTENNAPARTIALMETALAREA 14.7329 LAYER Metal2 ; + ANTENNAMODEL OXIDE1 ; + ANTENNAGATEAREA 0.20085 LAYER Metal2 ; + ANTENNAMAXAREACAR 74.2589 LAYER Metal2 ; + PORT + LAYER Metal2 ; + RECT 356.285 0 356.545 0.26 ; + END + END A_ADDR[4] + PIN B_ADDR[4] + DIRECTION INPUT ; + USE SIGNAL ; + ANTENNAPARTIALMETALAREA 14.7329 LAYER Metal2 ; + ANTENNAMODEL OXIDE1 ; + ANTENNAGATEAREA 0.20085 LAYER Metal2 ; + ANTENNAMAXAREACAR 74.2589 LAYER Metal2 ; + PORT + LAYER Metal2 ; + RECT 346.285 0 346.545 0.26 ; + END + END B_ADDR[4] + PIN A_ADDR[5] + DIRECTION INPUT ; + USE SIGNAL ; + ANTENNAPARTIALMETALAREA 13.2691 LAYER Metal2 ; + ANTENNAMODEL OXIDE1 ; + ANTENNAGATEAREA 0.20085 LAYER Metal2 ; + ANTENNAMAXAREACAR 66.970874 LAYER Metal2 ; + PORT + LAYER Metal2 ; + RECT 355.265 0 355.525 0.26 ; + END + END A_ADDR[5] + PIN B_ADDR[5] + DIRECTION INPUT ; + USE SIGNAL ; + ANTENNAPARTIALMETALAREA 13.2691 LAYER Metal2 ; + ANTENNAMODEL OXIDE1 ; + ANTENNAGATEAREA 0.20085 LAYER Metal2 ; + ANTENNAMAXAREACAR 66.970874 LAYER Metal2 ; + PORT + LAYER Metal2 ; + RECT 347.305 0 347.565 0.26 ; + END + END B_ADDR[5] + PIN A_CLK + DIRECTION INPUT ; + USE SIGNAL ; + ANTENNAPARTIALMETALAREA 4.0547 LAYER Metal2 ; + ANTENNAMODEL OXIDE1 ; + ANTENNAGATEAREA 0.20085 LAYER Metal2 ; + ANTENNAMAXAREACAR 21.093851 LAYER Metal2 ; + PORT + LAYER Metal2 ; + RECT 365.975 0 366.235 0.26 ; + END + END A_CLK + PIN A_REN + DIRECTION INPUT ; + USE SIGNAL ; + ANTENNAPARTIALMETALAREA 3.98465 LAYER Metal2 ; + ANTENNAMODEL OXIDE1 ; + ANTENNAGATEAREA 0.20085 LAYER Metal2 ; + ANTENNAMAXAREACAR 20.745083 LAYER Metal2 ; + PORT + LAYER Metal2 ; + RECT 369.545 0 369.805 0.26 ; + END + END A_REN + PIN A_WEN + DIRECTION INPUT ; + USE SIGNAL ; + ANTENNAPARTIALMETALAREA 2.8847 LAYER Metal2 ; + ANTENNAMODEL OXIDE1 ; + ANTENNAGATEAREA 0.20085 LAYER Metal2 ; + ANTENNAMAXAREACAR 15.268608 LAYER Metal2 ; + PORT + LAYER Metal2 ; + RECT 369.035 0 369.295 0.26 ; + END + END A_WEN + PIN A_MEN + DIRECTION INPUT ; + USE SIGNAL ; + ANTENNAPARTIALMETALAREA 3.0247 LAYER Metal2 ; + ANTENNAMODEL OXIDE1 ; + ANTENNAGATEAREA 0.20085 LAYER Metal2 ; + ANTENNAMAXAREACAR 15.965646 LAYER Metal2 ; + PORT + LAYER Metal2 ; + RECT 366.485 0 366.745 0.26 ; + END + END A_MEN + PIN A_DLY + DIRECTION INPUT ; + USE SIGNAL ; + ANTENNAPARTIALMETALAREA 7.7792 LAYER Metal2 ; + ANTENNAMODEL OXIDE1 ; + ANTENNAGATEAREA 0.3367 LAYER Metal2 ; + ANTENNAMAXAREACAR 23.644788 LAYER Metal2 ; + PORT + LAYER Metal2 ; + RECT 386.885 0 387.145 0.26 ; + END + END A_DLY + PIN B_CLK + DIRECTION INPUT ; + USE SIGNAL ; + ANTENNAPARTIALMETALAREA 4.0547 LAYER Metal2 ; + ANTENNAMODEL OXIDE1 ; + ANTENNAGATEAREA 0.20085 LAYER Metal2 ; + ANTENNAMAXAREACAR 21.093851 LAYER Metal2 ; + PORT + LAYER Metal2 ; + RECT 336.595 0 336.855 0.26 ; + END + END B_CLK + PIN B_REN + DIRECTION INPUT ; + USE SIGNAL ; + ANTENNAPARTIALMETALAREA 3.98465 LAYER Metal2 ; + ANTENNAMODEL OXIDE1 ; + ANTENNAGATEAREA 0.20085 LAYER Metal2 ; + ANTENNAMAXAREACAR 20.745083 LAYER Metal2 ; + PORT + LAYER Metal2 ; + RECT 333.025 0 333.285 0.26 ; + END + END B_REN + PIN B_WEN + DIRECTION INPUT ; + USE SIGNAL ; + ANTENNAPARTIALMETALAREA 2.8847 LAYER Metal2 ; + ANTENNAMODEL OXIDE1 ; + ANTENNAGATEAREA 0.20085 LAYER Metal2 ; + ANTENNAMAXAREACAR 15.268608 LAYER Metal2 ; + PORT + LAYER Metal2 ; + RECT 333.535 0 333.795 0.26 ; + END + END B_WEN + PIN B_MEN + DIRECTION INPUT ; + USE SIGNAL ; + ANTENNAPARTIALMETALAREA 3.0247 LAYER Metal2 ; + ANTENNAMODEL OXIDE1 ; + ANTENNAGATEAREA 0.20085 LAYER Metal2 ; + ANTENNAMAXAREACAR 15.965646 LAYER Metal2 ; + PORT + LAYER Metal2 ; + RECT 336.085 0 336.345 0.26 ; + END + END B_MEN + PIN B_DLY + DIRECTION INPUT ; + USE SIGNAL ; + ANTENNAPARTIALMETALAREA 7.7792 LAYER Metal2 ; + ANTENNAMODEL OXIDE1 ; + ANTENNAGATEAREA 0.3367 LAYER Metal2 ; + ANTENNAMAXAREACAR 23.644788 LAYER Metal2 ; + PORT + LAYER Metal2 ; + RECT 315.685 0 315.945 0.26 ; + END + END B_DLY + OBS + LAYER Metal1 ; + RECT 0 0 702.83 74.87 ; + LAYER Metal2 ; + RECT 0.31 53.41 0.51 74.84 ; + RECT 1.135 74.11 1.335 74.84 ; + RECT 1.545 74.11 1.905 74.84 ; + RECT 2.115 74.11 2.315 74.84 ; + RECT 2.19 0.52 2.45 7.78 ; + RECT 2.7 0.3 2.96 5.235 ; + RECT 2.77 74.11 2.97 74.84 ; + RECT 3.21 0 3.47 5.57 ; + RECT 3.18 74.11 3.54 74.84 ; + RECT 3.835 74.11 4.035 74.84 ; + RECT 4.33 74.11 4.69 74.84 ; + RECT 4.585 0 4.845 6.28 ; + RECT 4.9 74.11 5.1 74.84 ; + RECT 5.555 74.11 5.755 74.84 ; + RECT 5.965 74.11 6.325 74.84 ; + RECT 6.535 74.11 6.735 74.84 ; + RECT 6.27 0.18 7.04 0.88 ; + RECT 7.19 74.11 7.39 74.84 ; + RECT 7.29 0.3 7.55 8.7 ; + RECT 7.6 74.11 7.96 74.84 ; + RECT 8.255 74.11 8.455 74.84 ; + RECT 8.75 74.11 9.11 74.84 ; + RECT 9.84 0.155 10.61 0.445 ; + RECT 9.84 0.155 10.1 8.665 ; + RECT 10.35 0.155 10.61 8.665 ; + RECT 9.32 74.11 9.52 74.84 ; + RECT 9.33 0.52 9.59 9.955 ; + RECT 9.975 74.11 10.175 74.84 ; + RECT 10.385 74.11 10.745 74.84 ; + RECT 10.86 0 11.12 11.315 ; + RECT 10.955 74.11 11.155 74.84 ; + RECT 11.37 0 11.63 13.45 ; + RECT 11.61 74.11 11.81 74.84 ; + RECT 11.88 0.52 12.14 14.115 ; + RECT 12.02 74.11 12.38 74.84 ; + RECT 12.675 74.11 12.875 74.84 ; + RECT 14.075 0.155 14.845 0.445 ; + RECT 14.075 0.155 14.335 13.21 ; + RECT 14.585 0.155 14.845 13.21 ; + RECT 13.17 74.11 13.53 74.84 ; + RECT 13.74 74.11 13.94 74.84 ; + RECT 15.095 0.18 15.865 0.88 ; + RECT 15.095 0.18 15.355 12.9 ; + RECT 15.605 0.18 15.865 12.9 ; + RECT 14.395 74.11 14.595 74.84 ; + RECT 14.805 74.11 15.165 74.84 ; + RECT 15.375 74.11 15.575 74.84 ; + RECT 16.03 74.11 16.23 74.84 ; + RECT 16.315 0 16.575 2.82 ; + RECT 16.44 74.11 16.8 74.84 ; + RECT 17.095 74.11 17.295 74.84 ; + RECT 17.59 74.11 17.95 74.84 ; + RECT 17.845 0 18.105 2.82 ; + RECT 18.16 74.11 18.36 74.84 ; + RECT 18.815 74.11 19.015 74.84 ; + RECT 19.02 0.52 19.28 4.315 ; + RECT 19.225 74.11 19.585 74.84 ; + RECT 19.795 74.11 19.995 74.84 ; + RECT 19.87 0.52 20.13 7.78 ; + RECT 20.38 0.3 20.64 5.235 ; + RECT 20.45 74.11 20.65 74.84 ; + RECT 20.89 0 21.15 5.57 ; + RECT 20.86 74.11 21.22 74.84 ; + RECT 21.515 74.11 21.715 74.84 ; + RECT 22.01 74.11 22.37 74.84 ; + RECT 22.265 0 22.525 6.28 ; + RECT 22.58 74.11 22.78 74.84 ; + RECT 23.235 74.11 23.435 74.84 ; + RECT 23.645 74.11 24.005 74.84 ; + RECT 24.215 74.11 24.415 74.84 ; + RECT 23.95 0.18 24.72 0.88 ; + RECT 24.87 74.11 25.07 74.84 ; + RECT 24.97 0.3 25.23 8.7 ; + RECT 25.28 74.11 25.64 74.84 ; + RECT 25.935 74.11 26.135 74.84 ; + RECT 26.43 74.11 26.79 74.84 ; + RECT 27.52 0.155 28.29 0.445 ; + RECT 27.52 0.155 27.78 8.665 ; + RECT 28.03 0.155 28.29 8.665 ; + RECT 27 74.11 27.2 74.84 ; + RECT 27.01 0.52 27.27 9.955 ; + RECT 27.655 74.11 27.855 74.84 ; + RECT 28.065 74.11 28.425 74.84 ; + RECT 28.54 0 28.8 11.315 ; + RECT 28.635 74.11 28.835 74.84 ; + RECT 29.05 0 29.31 13.45 ; + RECT 29.29 74.11 29.49 74.84 ; + RECT 29.56 0.52 29.82 14.115 ; + RECT 29.7 74.11 30.06 74.84 ; + RECT 30.355 74.11 30.555 74.84 ; + RECT 31.755 0.155 32.525 0.445 ; + RECT 31.755 0.155 32.015 13.21 ; + RECT 32.265 0.155 32.525 13.21 ; + RECT 30.85 74.11 31.21 74.84 ; + RECT 31.42 74.11 31.62 74.84 ; + RECT 32.775 0.18 33.545 0.88 ; + RECT 32.775 0.18 33.035 12.9 ; + RECT 33.285 0.18 33.545 12.9 ; + RECT 32.075 74.11 32.275 74.84 ; + RECT 32.485 74.11 32.845 74.84 ; + RECT 33.055 74.11 33.255 74.84 ; + RECT 33.71 74.11 33.91 74.84 ; + RECT 33.995 0 34.255 2.82 ; + RECT 34.12 74.11 34.48 74.84 ; + RECT 34.775 74.11 34.975 74.84 ; + RECT 35.27 74.11 35.63 74.84 ; + RECT 35.525 0 35.785 2.82 ; + RECT 35.84 74.11 36.04 74.84 ; + RECT 36.495 74.11 36.695 74.84 ; + RECT 36.7 0.52 36.96 4.315 ; + RECT 36.905 74.11 37.265 74.84 ; + RECT 37.475 74.11 37.675 74.84 ; + RECT 37.55 0.52 37.81 7.78 ; + RECT 38.06 0.3 38.32 5.235 ; + RECT 38.13 74.11 38.33 74.84 ; + RECT 38.57 0 38.83 5.57 ; + RECT 38.54 74.11 38.9 74.84 ; + RECT 39.195 74.11 39.395 74.84 ; + RECT 39.69 74.11 40.05 74.84 ; + RECT 39.945 0 40.205 6.28 ; + RECT 40.26 74.11 40.46 74.84 ; + RECT 40.915 74.11 41.115 74.84 ; + RECT 41.325 74.11 41.685 74.84 ; + RECT 41.895 74.11 42.095 74.84 ; + RECT 41.63 0.18 42.4 0.88 ; + RECT 42.55 74.11 42.75 74.84 ; + RECT 42.65 0.3 42.91 8.7 ; + RECT 42.96 74.11 43.32 74.84 ; + RECT 43.615 74.11 43.815 74.84 ; + RECT 44.11 74.11 44.47 74.84 ; + RECT 45.2 0.155 45.97 0.445 ; + RECT 45.2 0.155 45.46 8.665 ; + RECT 45.71 0.155 45.97 8.665 ; + RECT 44.68 74.11 44.88 74.84 ; + RECT 44.69 0.52 44.95 9.955 ; + RECT 45.335 74.11 45.535 74.84 ; + RECT 45.745 74.11 46.105 74.84 ; + RECT 46.22 0 46.48 11.315 ; + RECT 46.315 74.11 46.515 74.84 ; + RECT 46.73 0 46.99 13.45 ; + RECT 46.97 74.11 47.17 74.84 ; + RECT 47.24 0.52 47.5 14.115 ; + RECT 47.38 74.11 47.74 74.84 ; + RECT 48.035 74.11 48.235 74.84 ; + RECT 49.435 0.155 50.205 0.445 ; + RECT 49.435 0.155 49.695 13.21 ; + RECT 49.945 0.155 50.205 13.21 ; + RECT 48.53 74.11 48.89 74.84 ; + RECT 49.1 74.11 49.3 74.84 ; + RECT 50.455 0.18 51.225 0.88 ; + RECT 50.455 0.18 50.715 12.9 ; + RECT 50.965 0.18 51.225 12.9 ; + RECT 49.755 74.11 49.955 74.84 ; + RECT 50.165 74.11 50.525 74.84 ; + RECT 50.735 74.11 50.935 74.84 ; + RECT 51.39 74.11 51.59 74.84 ; + RECT 51.675 0 51.935 2.82 ; + RECT 51.8 74.11 52.16 74.84 ; + RECT 52.455 74.11 52.655 74.84 ; + RECT 52.95 74.11 53.31 74.84 ; + RECT 53.205 0 53.465 2.82 ; + RECT 53.52 74.11 53.72 74.84 ; + RECT 54.175 74.11 54.375 74.84 ; + RECT 54.38 0.52 54.64 4.315 ; + RECT 54.585 74.11 54.945 74.84 ; + RECT 55.155 74.11 55.355 74.84 ; + RECT 55.23 0.52 55.49 7.78 ; + RECT 55.74 0.3 56 5.235 ; + RECT 55.81 74.11 56.01 74.84 ; + RECT 56.25 0 56.51 5.57 ; + RECT 56.22 74.11 56.58 74.84 ; + RECT 56.875 74.11 57.075 74.84 ; + RECT 57.37 74.11 57.73 74.84 ; + RECT 57.625 0 57.885 6.28 ; + RECT 57.94 74.11 58.14 74.84 ; + RECT 58.595 74.11 58.795 74.84 ; + RECT 59.005 74.11 59.365 74.84 ; + RECT 59.575 74.11 59.775 74.84 ; + RECT 59.31 0.18 60.08 0.88 ; + RECT 60.23 74.11 60.43 74.84 ; + RECT 60.33 0.3 60.59 8.7 ; + RECT 60.64 74.11 61 74.84 ; + RECT 61.295 74.11 61.495 74.84 ; + RECT 61.79 74.11 62.15 74.84 ; + RECT 62.88 0.155 63.65 0.445 ; + RECT 62.88 0.155 63.14 8.665 ; + RECT 63.39 0.155 63.65 8.665 ; + RECT 62.36 74.11 62.56 74.84 ; + RECT 62.37 0.52 62.63 9.955 ; + RECT 63.015 74.11 63.215 74.84 ; + RECT 63.425 74.11 63.785 74.84 ; + RECT 63.9 0 64.16 11.315 ; + RECT 63.995 74.11 64.195 74.84 ; + RECT 64.41 0 64.67 13.45 ; + RECT 64.65 74.11 64.85 74.84 ; + RECT 64.92 0.52 65.18 14.115 ; + RECT 65.06 74.11 65.42 74.84 ; + RECT 65.715 74.11 65.915 74.84 ; + RECT 67.115 0.155 67.885 0.445 ; + RECT 67.115 0.155 67.375 13.21 ; + RECT 67.625 0.155 67.885 13.21 ; + RECT 66.21 74.11 66.57 74.84 ; + RECT 66.78 74.11 66.98 74.84 ; + RECT 68.135 0.18 68.905 0.88 ; + RECT 68.135 0.18 68.395 12.9 ; + RECT 68.645 0.18 68.905 12.9 ; + RECT 67.435 74.11 67.635 74.84 ; + RECT 67.845 74.11 68.205 74.84 ; + RECT 68.415 74.11 68.615 74.84 ; + RECT 69.07 74.11 69.27 74.84 ; + RECT 69.355 0 69.615 2.82 ; + RECT 69.48 74.11 69.84 74.84 ; + RECT 70.135 74.11 70.335 74.84 ; + RECT 70.63 74.11 70.99 74.84 ; + RECT 70.885 0 71.145 2.82 ; + RECT 71.2 74.11 71.4 74.84 ; + RECT 71.855 74.11 72.055 74.84 ; + RECT 72.06 0.52 72.32 4.315 ; + RECT 72.265 74.11 72.625 74.84 ; + RECT 72.835 74.11 73.035 74.84 ; + RECT 72.91 0.52 73.17 7.78 ; + RECT 73.42 0.3 73.68 5.235 ; + RECT 73.49 74.11 73.69 74.84 ; + RECT 73.93 0 74.19 5.57 ; + RECT 73.9 74.11 74.26 74.84 ; + RECT 74.555 74.11 74.755 74.84 ; + RECT 75.05 74.11 75.41 74.84 ; + RECT 75.305 0 75.565 6.28 ; + RECT 75.62 74.11 75.82 74.84 ; + RECT 76.275 74.11 76.475 74.84 ; + RECT 76.685 74.11 77.045 74.84 ; + RECT 77.255 74.11 77.455 74.84 ; + RECT 76.99 0.18 77.76 0.88 ; + RECT 77.91 74.11 78.11 74.84 ; + RECT 78.01 0.3 78.27 8.7 ; + RECT 78.32 74.11 78.68 74.84 ; + RECT 78.975 74.11 79.175 74.84 ; + RECT 79.47 74.11 79.83 74.84 ; + RECT 80.56 0.155 81.33 0.445 ; + RECT 80.56 0.155 80.82 8.665 ; + RECT 81.07 0.155 81.33 8.665 ; + RECT 80.04 74.11 80.24 74.84 ; + RECT 80.05 0.52 80.31 9.955 ; + RECT 80.695 74.11 80.895 74.84 ; + RECT 81.105 74.11 81.465 74.84 ; + RECT 81.58 0 81.84 11.315 ; + RECT 81.675 74.11 81.875 74.84 ; + RECT 82.09 0 82.35 13.45 ; + RECT 82.33 74.11 82.53 74.84 ; + RECT 82.6 0.52 82.86 14.115 ; + RECT 82.74 74.11 83.1 74.84 ; + RECT 83.395 74.11 83.595 74.84 ; + RECT 84.795 0.155 85.565 0.445 ; + RECT 84.795 0.155 85.055 13.21 ; + RECT 85.305 0.155 85.565 13.21 ; + RECT 83.89 74.11 84.25 74.84 ; + RECT 84.46 74.11 84.66 74.84 ; + RECT 85.815 0.18 86.585 0.88 ; + RECT 85.815 0.18 86.075 12.9 ; + RECT 86.325 0.18 86.585 12.9 ; + RECT 85.115 74.11 85.315 74.84 ; + RECT 85.525 74.11 85.885 74.84 ; + RECT 86.095 74.11 86.295 74.84 ; + RECT 86.75 74.11 86.95 74.84 ; + RECT 87.035 0 87.295 2.82 ; + RECT 87.16 74.11 87.52 74.84 ; + RECT 87.815 74.11 88.015 74.84 ; + RECT 88.31 74.11 88.67 74.84 ; + RECT 88.565 0 88.825 2.82 ; + RECT 88.88 74.11 89.08 74.84 ; + RECT 89.535 74.11 89.735 74.84 ; + RECT 89.74 0.52 90 4.315 ; + RECT 89.945 74.11 90.305 74.84 ; + RECT 90.515 74.11 90.715 74.84 ; + RECT 90.59 0.52 90.85 7.78 ; + RECT 91.1 0.3 91.36 5.235 ; + RECT 91.17 74.11 91.37 74.84 ; + RECT 91.61 0 91.87 5.57 ; + RECT 91.58 74.11 91.94 74.84 ; + RECT 92.235 74.11 92.435 74.84 ; + RECT 92.73 74.11 93.09 74.84 ; + RECT 92.985 0 93.245 6.28 ; + RECT 93.3 74.11 93.5 74.84 ; + RECT 93.955 74.11 94.155 74.84 ; + RECT 94.365 74.11 94.725 74.84 ; + RECT 94.935 74.11 95.135 74.84 ; + RECT 94.67 0.18 95.44 0.88 ; + RECT 95.59 74.11 95.79 74.84 ; + RECT 95.69 0.3 95.95 8.7 ; + RECT 96 74.11 96.36 74.84 ; + RECT 96.655 74.11 96.855 74.84 ; + RECT 97.15 74.11 97.51 74.84 ; + RECT 98.24 0.155 99.01 0.445 ; + RECT 98.24 0.155 98.5 8.665 ; + RECT 98.75 0.155 99.01 8.665 ; + RECT 97.72 74.11 97.92 74.84 ; + RECT 97.73 0.52 97.99 9.955 ; + RECT 98.375 74.11 98.575 74.84 ; + RECT 98.785 74.11 99.145 74.84 ; + RECT 99.26 0 99.52 11.315 ; + RECT 99.355 74.11 99.555 74.84 ; + RECT 99.77 0 100.03 13.45 ; + RECT 100.01 74.11 100.21 74.84 ; + RECT 100.28 0.52 100.54 14.115 ; + RECT 100.42 74.11 100.78 74.84 ; + RECT 101.075 74.11 101.275 74.84 ; + RECT 102.475 0.155 103.245 0.445 ; + RECT 102.475 0.155 102.735 13.21 ; + RECT 102.985 0.155 103.245 13.21 ; + RECT 101.57 74.11 101.93 74.84 ; + RECT 102.14 74.11 102.34 74.84 ; + RECT 103.495 0.18 104.265 0.88 ; + RECT 103.495 0.18 103.755 12.9 ; + RECT 104.005 0.18 104.265 12.9 ; + RECT 102.795 74.11 102.995 74.84 ; + RECT 103.205 74.11 103.565 74.84 ; + RECT 103.775 74.11 103.975 74.84 ; + RECT 104.43 74.11 104.63 74.84 ; + RECT 104.715 0 104.975 2.82 ; + RECT 104.84 74.11 105.2 74.84 ; + RECT 105.495 74.11 105.695 74.84 ; + RECT 105.99 74.11 106.35 74.84 ; + RECT 106.245 0 106.505 2.82 ; + RECT 106.56 74.11 106.76 74.84 ; + RECT 107.215 74.11 107.415 74.84 ; + RECT 107.42 0.52 107.68 4.315 ; + RECT 107.625 74.11 107.985 74.84 ; + RECT 108.195 74.11 108.395 74.84 ; + RECT 108.27 0.52 108.53 7.78 ; + RECT 108.78 0.3 109.04 5.235 ; + RECT 108.85 74.11 109.05 74.84 ; + RECT 109.29 0 109.55 5.57 ; + RECT 109.26 74.11 109.62 74.84 ; + RECT 109.915 74.11 110.115 74.84 ; + RECT 110.41 74.11 110.77 74.84 ; + RECT 110.665 0 110.925 6.28 ; + RECT 110.98 74.11 111.18 74.84 ; + RECT 111.635 74.11 111.835 74.84 ; + RECT 112.045 74.11 112.405 74.84 ; + RECT 112.615 74.11 112.815 74.84 ; + RECT 112.35 0.18 113.12 0.88 ; + RECT 113.27 74.11 113.47 74.84 ; + RECT 113.37 0.3 113.63 8.7 ; + RECT 113.68 74.11 114.04 74.84 ; + RECT 114.335 74.11 114.535 74.84 ; + RECT 114.83 74.11 115.19 74.84 ; + RECT 115.92 0.155 116.69 0.445 ; + RECT 115.92 0.155 116.18 8.665 ; + RECT 116.43 0.155 116.69 8.665 ; + RECT 115.4 74.11 115.6 74.84 ; + RECT 115.41 0.52 115.67 9.955 ; + RECT 116.055 74.11 116.255 74.84 ; + RECT 116.465 74.11 116.825 74.84 ; + RECT 116.94 0 117.2 11.315 ; + RECT 117.035 74.11 117.235 74.84 ; + RECT 117.45 0 117.71 13.45 ; + RECT 117.69 74.11 117.89 74.84 ; + RECT 117.96 0.52 118.22 14.115 ; + RECT 118.1 74.11 118.46 74.84 ; + RECT 118.755 74.11 118.955 74.84 ; + RECT 120.155 0.155 120.925 0.445 ; + RECT 120.155 0.155 120.415 13.21 ; + RECT 120.665 0.155 120.925 13.21 ; + RECT 119.25 74.11 119.61 74.84 ; + RECT 119.82 74.11 120.02 74.84 ; + RECT 121.175 0.18 121.945 0.88 ; + RECT 121.175 0.18 121.435 12.9 ; + RECT 121.685 0.18 121.945 12.9 ; + RECT 120.475 74.11 120.675 74.84 ; + RECT 120.885 74.11 121.245 74.84 ; + RECT 121.455 74.11 121.655 74.84 ; + RECT 122.11 74.11 122.31 74.84 ; + RECT 122.395 0 122.655 2.82 ; + RECT 122.52 74.11 122.88 74.84 ; + RECT 123.175 74.11 123.375 74.84 ; + RECT 123.67 74.11 124.03 74.84 ; + RECT 123.925 0 124.185 2.82 ; + RECT 124.24 74.11 124.44 74.84 ; + RECT 124.895 74.11 125.095 74.84 ; + RECT 125.1 0.52 125.36 4.315 ; + RECT 125.305 74.11 125.665 74.84 ; + RECT 125.875 74.11 126.075 74.84 ; + RECT 125.95 0.52 126.21 7.78 ; + RECT 126.46 0.3 126.72 5.235 ; + RECT 126.53 74.11 126.73 74.84 ; + RECT 126.97 0 127.23 5.57 ; + RECT 126.94 74.11 127.3 74.84 ; + RECT 127.595 74.11 127.795 74.84 ; + RECT 128.09 74.11 128.45 74.84 ; + RECT 128.345 0 128.605 6.28 ; + RECT 128.66 74.11 128.86 74.84 ; + RECT 129.315 74.11 129.515 74.84 ; + RECT 129.725 74.11 130.085 74.84 ; + RECT 130.295 74.11 130.495 74.84 ; + RECT 130.03 0.18 130.8 0.88 ; + RECT 130.95 74.11 131.15 74.84 ; + RECT 131.05 0.3 131.31 8.7 ; + RECT 131.36 74.11 131.72 74.84 ; + RECT 132.015 74.11 132.215 74.84 ; + RECT 132.51 74.11 132.87 74.84 ; + RECT 133.6 0.155 134.37 0.445 ; + RECT 133.6 0.155 133.86 8.665 ; + RECT 134.11 0.155 134.37 8.665 ; + RECT 133.08 74.11 133.28 74.84 ; + RECT 133.09 0.52 133.35 9.955 ; + RECT 133.735 74.11 133.935 74.84 ; + RECT 134.145 74.11 134.505 74.84 ; + RECT 134.62 0 134.88 11.315 ; + RECT 134.715 74.11 134.915 74.84 ; + RECT 135.13 0 135.39 13.45 ; + RECT 135.37 74.11 135.57 74.84 ; + RECT 135.64 0.52 135.9 14.115 ; + RECT 135.78 74.11 136.14 74.84 ; + RECT 136.435 74.11 136.635 74.84 ; + RECT 137.835 0.155 138.605 0.445 ; + RECT 137.835 0.155 138.095 13.21 ; + RECT 138.345 0.155 138.605 13.21 ; + RECT 136.93 74.11 137.29 74.84 ; + RECT 137.5 74.11 137.7 74.84 ; + RECT 138.855 0.18 139.625 0.88 ; + RECT 138.855 0.18 139.115 12.9 ; + RECT 139.365 0.18 139.625 12.9 ; + RECT 138.155 74.11 138.355 74.84 ; + RECT 138.565 74.11 138.925 74.84 ; + RECT 139.135 74.11 139.335 74.84 ; + RECT 139.79 74.11 139.99 74.84 ; + RECT 140.075 0 140.335 2.82 ; + RECT 140.2 74.11 140.56 74.84 ; + RECT 140.855 74.11 141.055 74.84 ; + RECT 141.35 74.11 141.71 74.84 ; + RECT 141.605 0 141.865 2.82 ; + RECT 141.92 74.11 142.12 74.84 ; + RECT 142.575 74.11 142.775 74.84 ; + RECT 142.78 0.52 143.04 4.315 ; + RECT 142.985 74.11 143.345 74.84 ; + RECT 143.555 74.11 143.755 74.84 ; + RECT 143.63 0.52 143.89 7.78 ; + RECT 144.14 0.3 144.4 5.235 ; + RECT 144.21 74.11 144.41 74.84 ; + RECT 144.65 0 144.91 5.57 ; + RECT 144.62 74.11 144.98 74.84 ; + RECT 145.275 74.11 145.475 74.84 ; + RECT 145.77 74.11 146.13 74.84 ; + RECT 146.025 0 146.285 6.28 ; + RECT 146.34 74.11 146.54 74.84 ; + RECT 146.995 74.11 147.195 74.84 ; + RECT 147.405 74.11 147.765 74.84 ; + RECT 147.975 74.11 148.175 74.84 ; + RECT 147.71 0.18 148.48 0.88 ; + RECT 148.63 74.11 148.83 74.84 ; + RECT 148.73 0.3 148.99 8.7 ; + RECT 149.04 74.11 149.4 74.84 ; + RECT 149.695 74.11 149.895 74.84 ; + RECT 150.19 74.11 150.55 74.84 ; + RECT 151.28 0.155 152.05 0.445 ; + RECT 151.28 0.155 151.54 8.665 ; + RECT 151.79 0.155 152.05 8.665 ; + RECT 150.76 74.11 150.96 74.84 ; + RECT 150.77 0.52 151.03 9.955 ; + RECT 151.415 74.11 151.615 74.84 ; + RECT 151.825 74.11 152.185 74.84 ; + RECT 152.3 0 152.56 11.315 ; + RECT 152.395 74.11 152.595 74.84 ; + RECT 152.81 0 153.07 13.45 ; + RECT 153.05 74.11 153.25 74.84 ; + RECT 153.32 0.52 153.58 14.115 ; + RECT 153.46 74.11 153.82 74.84 ; + RECT 154.115 74.11 154.315 74.84 ; + RECT 155.515 0.155 156.285 0.445 ; + RECT 155.515 0.155 155.775 13.21 ; + RECT 156.025 0.155 156.285 13.21 ; + RECT 154.61 74.11 154.97 74.84 ; + RECT 155.18 74.11 155.38 74.84 ; + RECT 156.535 0.18 157.305 0.88 ; + RECT 156.535 0.18 156.795 12.9 ; + RECT 157.045 0.18 157.305 12.9 ; + RECT 155.835 74.11 156.035 74.84 ; + RECT 156.245 74.11 156.605 74.84 ; + RECT 156.815 74.11 157.015 74.84 ; + RECT 157.47 74.11 157.67 74.84 ; + RECT 157.755 0 158.015 2.82 ; + RECT 157.88 74.11 158.24 74.84 ; + RECT 158.535 74.11 158.735 74.84 ; + RECT 159.03 74.11 159.39 74.84 ; + RECT 159.285 0 159.545 2.82 ; + RECT 159.6 74.11 159.8 74.84 ; + RECT 160.255 74.11 160.455 74.84 ; + RECT 160.46 0.52 160.72 4.315 ; + RECT 160.665 74.11 161.025 74.84 ; + RECT 161.235 74.11 161.435 74.84 ; + RECT 161.31 0.52 161.57 7.78 ; + RECT 161.82 0.3 162.08 5.235 ; + RECT 161.89 74.11 162.09 74.84 ; + RECT 162.33 0 162.59 5.57 ; + RECT 162.3 74.11 162.66 74.84 ; + RECT 162.955 74.11 163.155 74.84 ; + RECT 163.45 74.11 163.81 74.84 ; + RECT 163.705 0 163.965 6.28 ; + RECT 164.02 74.11 164.22 74.84 ; + RECT 164.675 74.11 164.875 74.84 ; + RECT 165.085 74.11 165.445 74.84 ; + RECT 165.655 74.11 165.855 74.84 ; + RECT 165.39 0.18 166.16 0.88 ; + RECT 166.31 74.11 166.51 74.84 ; + RECT 166.41 0.3 166.67 8.7 ; + RECT 166.72 74.11 167.08 74.84 ; + RECT 167.375 74.11 167.575 74.84 ; + RECT 167.87 74.11 168.23 74.84 ; + RECT 168.96 0.155 169.73 0.445 ; + RECT 168.96 0.155 169.22 8.665 ; + RECT 169.47 0.155 169.73 8.665 ; + RECT 168.44 74.11 168.64 74.84 ; + RECT 168.45 0.52 168.71 9.955 ; + RECT 169.095 74.11 169.295 74.84 ; + RECT 169.505 74.11 169.865 74.84 ; + RECT 169.98 0 170.24 11.315 ; + RECT 170.075 74.11 170.275 74.84 ; + RECT 170.49 0 170.75 13.45 ; + RECT 170.73 74.11 170.93 74.84 ; + RECT 171 0.52 171.26 14.115 ; + RECT 171.14 74.11 171.5 74.84 ; + RECT 171.795 74.11 171.995 74.84 ; + RECT 173.195 0.155 173.965 0.445 ; + RECT 173.195 0.155 173.455 13.21 ; + RECT 173.705 0.155 173.965 13.21 ; + RECT 172.29 74.11 172.65 74.84 ; + RECT 172.86 74.11 173.06 74.84 ; + RECT 174.215 0.18 174.985 0.88 ; + RECT 174.215 0.18 174.475 12.9 ; + RECT 174.725 0.18 174.985 12.9 ; + RECT 173.515 74.11 173.715 74.84 ; + RECT 173.925 74.11 174.285 74.84 ; + RECT 174.495 74.11 174.695 74.84 ; + RECT 175.15 74.11 175.35 74.84 ; + RECT 175.435 0 175.695 2.82 ; + RECT 175.56 74.11 175.92 74.84 ; + RECT 176.215 74.11 176.415 74.84 ; + RECT 176.71 74.11 177.07 74.84 ; + RECT 176.965 0 177.225 2.82 ; + RECT 177.28 74.11 177.48 74.84 ; + RECT 177.935 74.11 178.135 74.84 ; + RECT 178.14 0.52 178.4 4.315 ; + RECT 178.345 74.11 178.705 74.84 ; + RECT 178.915 74.11 179.115 74.84 ; + RECT 178.99 0.52 179.25 7.78 ; + RECT 179.5 0.3 179.76 5.235 ; + RECT 179.57 74.11 179.77 74.84 ; + RECT 180.01 0 180.27 5.57 ; + RECT 179.98 74.11 180.34 74.84 ; + RECT 180.635 74.11 180.835 74.84 ; + RECT 181.13 74.11 181.49 74.84 ; + RECT 181.385 0 181.645 6.28 ; + RECT 181.7 74.11 181.9 74.84 ; + RECT 182.355 74.11 182.555 74.84 ; + RECT 182.765 74.11 183.125 74.84 ; + RECT 183.335 74.11 183.535 74.84 ; + RECT 183.07 0.18 183.84 0.88 ; + RECT 183.99 74.11 184.19 74.84 ; + RECT 184.09 0.3 184.35 8.7 ; + RECT 184.4 74.11 184.76 74.84 ; + RECT 185.055 74.11 185.255 74.84 ; + RECT 185.55 74.11 185.91 74.84 ; + RECT 186.64 0.155 187.41 0.445 ; + RECT 186.64 0.155 186.9 8.665 ; + RECT 187.15 0.155 187.41 8.665 ; + RECT 186.12 74.11 186.32 74.84 ; + RECT 186.13 0.52 186.39 9.955 ; + RECT 186.775 74.11 186.975 74.84 ; + RECT 187.185 74.11 187.545 74.84 ; + RECT 187.66 0 187.92 11.315 ; + RECT 187.755 74.11 187.955 74.84 ; + RECT 188.17 0 188.43 13.45 ; + RECT 188.41 74.11 188.61 74.84 ; + RECT 188.68 0.52 188.94 14.115 ; + RECT 188.82 74.11 189.18 74.84 ; + RECT 189.475 74.11 189.675 74.84 ; + RECT 190.875 0.155 191.645 0.445 ; + RECT 190.875 0.155 191.135 13.21 ; + RECT 191.385 0.155 191.645 13.21 ; + RECT 189.97 74.11 190.33 74.84 ; + RECT 190.54 74.11 190.74 74.84 ; + RECT 191.895 0.18 192.665 0.88 ; + RECT 191.895 0.18 192.155 12.9 ; + RECT 192.405 0.18 192.665 12.9 ; + RECT 191.195 74.11 191.395 74.84 ; + RECT 191.605 74.11 191.965 74.84 ; + RECT 192.175 74.11 192.375 74.84 ; + RECT 192.83 74.11 193.03 74.84 ; + RECT 193.115 0 193.375 2.82 ; + RECT 193.24 74.11 193.6 74.84 ; + RECT 193.895 74.11 194.095 74.84 ; + RECT 194.39 74.11 194.75 74.84 ; + RECT 194.645 0 194.905 2.82 ; + RECT 194.96 74.11 195.16 74.84 ; + RECT 195.615 74.11 195.815 74.84 ; + RECT 195.82 0.52 196.08 4.315 ; + RECT 196.025 74.11 196.385 74.84 ; + RECT 196.595 74.11 196.795 74.84 ; + RECT 196.67 0.52 196.93 7.78 ; + RECT 197.18 0.3 197.44 5.235 ; + RECT 197.25 74.11 197.45 74.84 ; + RECT 197.69 0 197.95 5.57 ; + RECT 197.66 74.11 198.02 74.84 ; + RECT 198.315 74.11 198.515 74.84 ; + RECT 198.81 74.11 199.17 74.84 ; + RECT 199.065 0 199.325 6.28 ; + RECT 199.38 74.11 199.58 74.84 ; + RECT 200.035 74.11 200.235 74.84 ; + RECT 200.445 74.11 200.805 74.84 ; + RECT 201.015 74.11 201.215 74.84 ; + RECT 200.75 0.18 201.52 0.88 ; + RECT 201.67 74.11 201.87 74.84 ; + RECT 201.77 0.3 202.03 8.7 ; + RECT 202.08 74.11 202.44 74.84 ; + RECT 202.735 74.11 202.935 74.84 ; + RECT 203.23 74.11 203.59 74.84 ; + RECT 204.32 0.155 205.09 0.445 ; + RECT 204.32 0.155 204.58 8.665 ; + RECT 204.83 0.155 205.09 8.665 ; + RECT 203.8 74.11 204 74.84 ; + RECT 203.81 0.52 204.07 9.955 ; + RECT 204.455 74.11 204.655 74.84 ; + RECT 204.865 74.11 205.225 74.84 ; + RECT 205.34 0 205.6 11.315 ; + RECT 205.435 74.11 205.635 74.84 ; + RECT 205.85 0 206.11 13.45 ; + RECT 206.09 74.11 206.29 74.84 ; + RECT 206.36 0.52 206.62 14.115 ; + RECT 206.5 74.11 206.86 74.84 ; + RECT 207.155 74.11 207.355 74.84 ; + RECT 208.555 0.155 209.325 0.445 ; + RECT 208.555 0.155 208.815 13.21 ; + RECT 209.065 0.155 209.325 13.21 ; + RECT 207.65 74.11 208.01 74.84 ; + RECT 208.22 74.11 208.42 74.84 ; + RECT 209.575 0.18 210.345 0.88 ; + RECT 209.575 0.18 209.835 12.9 ; + RECT 210.085 0.18 210.345 12.9 ; + RECT 208.875 74.11 209.075 74.84 ; + RECT 209.285 74.11 209.645 74.84 ; + RECT 209.855 74.11 210.055 74.84 ; + RECT 210.51 74.11 210.71 74.84 ; + RECT 210.795 0 211.055 2.82 ; + RECT 210.92 74.11 211.28 74.84 ; + RECT 211.575 74.11 211.775 74.84 ; + RECT 212.07 74.11 212.43 74.84 ; + RECT 212.325 0 212.585 2.82 ; + RECT 212.64 74.11 212.84 74.84 ; + RECT 213.295 74.11 213.495 74.84 ; + RECT 213.5 0.52 213.76 4.315 ; + RECT 213.705 74.11 214.065 74.84 ; + RECT 214.275 74.11 214.475 74.84 ; + RECT 214.35 0.52 214.61 7.78 ; + RECT 214.86 0.3 215.12 5.235 ; + RECT 214.93 74.11 215.13 74.84 ; + RECT 215.37 0 215.63 5.57 ; + RECT 215.34 74.11 215.7 74.84 ; + RECT 215.995 74.11 216.195 74.84 ; + RECT 216.49 74.11 216.85 74.84 ; + RECT 216.745 0 217.005 6.28 ; + RECT 217.06 74.11 217.26 74.84 ; + RECT 217.715 74.11 217.915 74.84 ; + RECT 218.125 74.11 218.485 74.84 ; + RECT 218.695 74.11 218.895 74.84 ; + RECT 218.43 0.18 219.2 0.88 ; + RECT 219.35 74.11 219.55 74.84 ; + RECT 219.45 0.3 219.71 8.7 ; + RECT 219.76 74.11 220.12 74.84 ; + RECT 220.415 74.11 220.615 74.84 ; + RECT 220.91 74.11 221.27 74.84 ; + RECT 222 0.155 222.77 0.445 ; + RECT 222 0.155 222.26 8.665 ; + RECT 222.51 0.155 222.77 8.665 ; + RECT 221.48 74.11 221.68 74.84 ; + RECT 221.49 0.52 221.75 9.955 ; + RECT 222.135 74.11 222.335 74.84 ; + RECT 222.545 74.11 222.905 74.84 ; + RECT 223.02 0 223.28 11.315 ; + RECT 223.115 74.11 223.315 74.84 ; + RECT 223.53 0 223.79 13.45 ; + RECT 223.77 74.11 223.97 74.84 ; + RECT 224.04 0.52 224.3 14.115 ; + RECT 224.18 74.11 224.54 74.84 ; + RECT 224.835 74.11 225.035 74.84 ; + RECT 226.235 0.155 227.005 0.445 ; + RECT 226.235 0.155 226.495 13.21 ; + RECT 226.745 0.155 227.005 13.21 ; + RECT 225.33 74.11 225.69 74.84 ; + RECT 225.9 74.11 226.1 74.84 ; + RECT 227.255 0.18 228.025 0.88 ; + RECT 227.255 0.18 227.515 12.9 ; + RECT 227.765 0.18 228.025 12.9 ; + RECT 226.555 74.11 226.755 74.84 ; + RECT 226.965 74.11 227.325 74.84 ; + RECT 227.535 74.11 227.735 74.84 ; + RECT 228.19 74.11 228.39 74.84 ; + RECT 228.475 0 228.735 2.82 ; + RECT 228.6 74.11 228.96 74.84 ; + RECT 229.255 74.11 229.455 74.84 ; + RECT 229.75 74.11 230.11 74.84 ; + RECT 230.005 0 230.265 2.82 ; + RECT 230.32 74.11 230.52 74.84 ; + RECT 230.975 74.11 231.175 74.84 ; + RECT 231.18 0.52 231.44 4.315 ; + RECT 231.385 74.11 231.745 74.84 ; + RECT 231.955 74.11 232.155 74.84 ; + RECT 232.03 0.52 232.29 7.78 ; + RECT 232.54 0.3 232.8 5.235 ; + RECT 232.61 74.11 232.81 74.84 ; + RECT 233.05 0 233.31 5.57 ; + RECT 233.02 74.11 233.38 74.84 ; + RECT 233.675 74.11 233.875 74.84 ; + RECT 234.17 74.11 234.53 74.84 ; + RECT 234.425 0 234.685 6.28 ; + RECT 234.74 74.11 234.94 74.84 ; + RECT 235.395 74.11 235.595 74.84 ; + RECT 235.805 74.11 236.165 74.84 ; + RECT 236.375 74.11 236.575 74.84 ; + RECT 236.11 0.18 236.88 0.88 ; + RECT 237.03 74.11 237.23 74.84 ; + RECT 237.13 0.3 237.39 8.7 ; + RECT 237.44 74.11 237.8 74.84 ; + RECT 238.095 74.11 238.295 74.84 ; + RECT 238.59 74.11 238.95 74.84 ; + RECT 239.68 0.155 240.45 0.445 ; + RECT 239.68 0.155 239.94 8.665 ; + RECT 240.19 0.155 240.45 8.665 ; + RECT 239.16 74.11 239.36 74.84 ; + RECT 239.17 0.52 239.43 9.955 ; + RECT 239.815 74.11 240.015 74.84 ; + RECT 240.225 74.11 240.585 74.84 ; + RECT 240.7 0 240.96 11.315 ; + RECT 240.795 74.11 240.995 74.84 ; + RECT 241.21 0 241.47 13.45 ; + RECT 241.45 74.11 241.65 74.84 ; + RECT 241.72 0.52 241.98 14.115 ; + RECT 241.86 74.11 242.22 74.84 ; + RECT 242.515 74.11 242.715 74.84 ; + RECT 243.915 0.155 244.685 0.445 ; + RECT 243.915 0.155 244.175 13.21 ; + RECT 244.425 0.155 244.685 13.21 ; + RECT 243.01 74.11 243.37 74.84 ; + RECT 243.58 74.11 243.78 74.84 ; + RECT 244.935 0.18 245.705 0.88 ; + RECT 244.935 0.18 245.195 12.9 ; + RECT 245.445 0.18 245.705 12.9 ; + RECT 244.235 74.11 244.435 74.84 ; + RECT 244.645 74.11 245.005 74.84 ; + RECT 245.215 74.11 245.415 74.84 ; + RECT 245.87 74.11 246.07 74.84 ; + RECT 246.155 0 246.415 2.82 ; + RECT 246.28 74.11 246.64 74.84 ; + RECT 246.935 74.11 247.135 74.84 ; + RECT 247.43 74.11 247.79 74.84 ; + RECT 247.685 0 247.945 2.82 ; + RECT 248 74.11 248.2 74.84 ; + RECT 248.655 74.11 248.855 74.84 ; + RECT 248.86 0.52 249.12 4.315 ; + RECT 249.065 74.11 249.425 74.84 ; + RECT 249.635 74.11 249.835 74.84 ; + RECT 249.71 0.52 249.97 7.78 ; + RECT 250.22 0.3 250.48 5.235 ; + RECT 250.29 74.11 250.49 74.84 ; + RECT 250.73 0 250.99 5.57 ; + RECT 250.7 74.11 251.06 74.84 ; + RECT 251.355 74.11 251.555 74.84 ; + RECT 251.85 74.11 252.21 74.84 ; + RECT 252.105 0 252.365 6.28 ; + RECT 252.42 74.11 252.62 74.84 ; + RECT 253.075 74.11 253.275 74.84 ; + RECT 253.485 74.11 253.845 74.84 ; + RECT 254.055 74.11 254.255 74.84 ; + RECT 253.79 0.18 254.56 0.88 ; + RECT 254.71 74.11 254.91 74.84 ; + RECT 254.81 0.3 255.07 8.7 ; + RECT 255.12 74.11 255.48 74.84 ; + RECT 255.775 74.11 255.975 74.84 ; + RECT 256.27 74.11 256.63 74.84 ; + RECT 257.36 0.155 258.13 0.445 ; + RECT 257.36 0.155 257.62 8.665 ; + RECT 257.87 0.155 258.13 8.665 ; + RECT 256.84 74.11 257.04 74.84 ; + RECT 256.85 0.52 257.11 9.955 ; + RECT 257.495 74.11 257.695 74.84 ; + RECT 257.905 74.11 258.265 74.84 ; + RECT 258.38 0 258.64 11.315 ; + RECT 258.475 74.11 258.675 74.84 ; + RECT 258.89 0 259.15 13.45 ; + RECT 259.13 74.11 259.33 74.84 ; + RECT 259.4 0.52 259.66 14.115 ; + RECT 259.54 74.11 259.9 74.84 ; + RECT 260.195 74.11 260.395 74.84 ; + RECT 261.595 0.155 262.365 0.445 ; + RECT 261.595 0.155 261.855 13.21 ; + RECT 262.105 0.155 262.365 13.21 ; + RECT 260.69 74.11 261.05 74.84 ; + RECT 261.26 74.11 261.46 74.84 ; + RECT 262.615 0.18 263.385 0.88 ; + RECT 262.615 0.18 262.875 12.9 ; + RECT 263.125 0.18 263.385 12.9 ; + RECT 261.915 74.11 262.115 74.84 ; + RECT 262.325 74.11 262.685 74.84 ; + RECT 262.895 74.11 263.095 74.84 ; + RECT 263.55 74.11 263.75 74.84 ; + RECT 263.835 0 264.095 2.82 ; + RECT 263.96 74.11 264.32 74.84 ; + RECT 264.615 74.11 264.815 74.84 ; + RECT 265.11 74.11 265.47 74.84 ; + RECT 265.365 0 265.625 2.82 ; + RECT 265.68 74.11 265.88 74.84 ; + RECT 266.335 74.11 266.535 74.84 ; + RECT 266.54 0.52 266.8 4.315 ; + RECT 266.745 74.11 267.105 74.84 ; + RECT 267.315 74.11 267.515 74.84 ; + RECT 267.39 0.52 267.65 7.78 ; + RECT 267.9 0.3 268.16 5.235 ; + RECT 267.97 74.11 268.17 74.84 ; + RECT 268.41 0 268.67 5.57 ; + RECT 268.38 74.11 268.74 74.84 ; + RECT 269.035 74.11 269.235 74.84 ; + RECT 269.53 74.11 269.89 74.84 ; + RECT 269.785 0 270.045 6.28 ; + RECT 270.1 74.11 270.3 74.84 ; + RECT 270.755 74.11 270.955 74.84 ; + RECT 271.165 74.11 271.525 74.84 ; + RECT 271.735 74.11 271.935 74.84 ; + RECT 271.47 0.18 272.24 0.88 ; + RECT 272.39 74.11 272.59 74.84 ; + RECT 272.49 0.3 272.75 8.7 ; + RECT 272.8 74.11 273.16 74.84 ; + RECT 273.455 74.11 273.655 74.84 ; + RECT 273.95 74.11 274.31 74.84 ; + RECT 275.04 0.155 275.81 0.445 ; + RECT 275.04 0.155 275.3 8.665 ; + RECT 275.55 0.155 275.81 8.665 ; + RECT 274.52 74.11 274.72 74.84 ; + RECT 274.53 0.52 274.79 9.955 ; + RECT 275.175 74.11 275.375 74.84 ; + RECT 275.585 74.11 275.945 74.84 ; + RECT 276.06 0 276.32 11.315 ; + RECT 276.155 74.11 276.355 74.84 ; + RECT 276.57 0 276.83 13.45 ; + RECT 276.81 74.11 277.01 74.84 ; + RECT 277.08 0.52 277.34 14.115 ; + RECT 277.22 74.11 277.58 74.84 ; + RECT 277.875 74.11 278.075 74.84 ; + RECT 279.275 0.155 280.045 0.445 ; + RECT 279.275 0.155 279.535 13.21 ; + RECT 279.785 0.155 280.045 13.21 ; + RECT 278.37 74.11 278.73 74.84 ; + RECT 278.94 74.11 279.14 74.84 ; + RECT 280.295 0.18 281.065 0.88 ; + RECT 280.295 0.18 280.555 12.9 ; + RECT 280.805 0.18 281.065 12.9 ; + RECT 279.595 74.11 279.795 74.84 ; + RECT 280.005 74.11 280.365 74.84 ; + RECT 280.575 74.11 280.775 74.84 ; + RECT 281.23 74.11 281.43 74.84 ; + RECT 281.515 0 281.775 2.82 ; + RECT 281.64 74.11 282 74.84 ; + RECT 282.295 74.11 282.495 74.84 ; + RECT 282.79 74.11 283.15 74.84 ; + RECT 283.045 0 283.305 2.82 ; + RECT 283.36 74.11 283.56 74.84 ; + RECT 284.015 74.11 284.215 74.84 ; + RECT 284.22 0.52 284.48 4.315 ; + RECT 285.75 0.17 286.52 0.43 ; + RECT 285.75 0.17 286.01 8.7 ; + RECT 286.26 0.17 286.52 8.7 ; + RECT 286.77 0.18 287.54 0.88 ; + RECT 286.77 0.18 287.03 8.7 ; + RECT 287.28 0.18 287.54 8.7 ; + RECT 287.79 0.17 288.56 0.43 ; + RECT 287.79 0.17 288.05 8.7 ; + RECT 288.3 0.17 288.56 8.7 ; + RECT 288.81 0.18 289.58 0.88 ; + RECT 288.81 0.18 289.07 8.7 ; + RECT 289.32 0.18 289.58 8.7 ; + RECT 289.83 0.17 290.6 0.43 ; + RECT 289.83 0.17 290.09 8.7 ; + RECT 290.34 0.17 290.6 8.7 ; + RECT 290.85 0.18 291.62 0.88 ; + RECT 290.85 0.18 291.11 8.7 ; + RECT 291.36 0.18 291.62 8.7 ; + RECT 291.87 0.17 292.64 0.43 ; + RECT 291.87 0.17 292.13 8.7 ; + RECT 292.38 0.17 292.64 8.7 ; + RECT 292.89 0.18 293.66 0.88 ; + RECT 292.89 0.18 293.15 8.7 ; + RECT 293.4 0.18 293.66 8.7 ; + RECT 293.91 0.17 294.68 0.43 ; + RECT 293.91 0.17 294.17 8.7 ; + RECT 294.42 0.17 294.68 8.7 ; + RECT 294.93 0.18 295.7 0.88 ; + RECT 294.93 0.18 295.19 8.7 ; + RECT 295.44 0.18 295.7 8.7 ; + RECT 295.95 0.17 296.72 0.43 ; + RECT 295.95 0.17 296.21 8.7 ; + RECT 296.46 0.17 296.72 8.7 ; + RECT 296.97 0.18 297.74 0.88 ; + RECT 296.97 0.18 297.23 8.7 ; + RECT 297.48 0.18 297.74 8.7 ; + RECT 297.99 0.17 298.76 0.43 ; + RECT 297.99 0.17 298.25 8.7 ; + RECT 298.5 0.17 298.76 8.7 ; + RECT 299.01 0.18 299.78 0.88 ; + RECT 299.01 0.18 299.27 8.7 ; + RECT 299.52 0.18 299.78 8.7 ; + RECT 300.03 0.17 300.8 0.43 ; + RECT 300.03 0.17 300.29 8.7 ; + RECT 300.54 0.17 300.8 8.7 ; + RECT 301.05 0.18 301.82 0.88 ; + RECT 301.05 0.18 301.31 8.7 ; + RECT 301.56 0.18 301.82 8.7 ; + RECT 302.07 0.17 302.84 0.43 ; + RECT 302.07 0.17 302.33 8.7 ; + RECT 302.58 0.17 302.84 8.7 ; + RECT 303.09 0.18 303.86 0.88 ; + RECT 303.09 0.18 303.35 8.7 ; + RECT 303.6 0.18 303.86 8.7 ; + RECT 304.11 0.17 304.88 0.43 ; + RECT 304.11 0.17 304.37 8.7 ; + RECT 304.62 0.17 304.88 8.7 ; + RECT 305.13 0.18 305.9 0.88 ; + RECT 305.13 0.18 305.39 8.7 ; + RECT 305.64 0.18 305.9 8.7 ; + RECT 306.15 0.17 306.92 0.43 ; + RECT 306.15 0.17 306.41 8.7 ; + RECT 306.66 0.17 306.92 8.7 ; + RECT 307.17 0.18 307.94 0.88 ; + RECT 307.17 0.18 307.43 8.7 ; + RECT 307.68 0.18 307.94 8.7 ; + RECT 308.19 0.17 308.96 0.43 ; + RECT 308.19 0.17 308.45 8.7 ; + RECT 308.7 0.17 308.96 8.7 ; + RECT 309.21 0.18 309.98 0.88 ; + RECT 309.21 0.18 309.47 8.7 ; + RECT 309.72 0.18 309.98 8.7 ; + RECT 284.425 74.11 284.785 74.84 ; + RECT 284.995 74.11 285.195 74.84 ; + RECT 311.605 0.18 312.375 0.88 ; + RECT 311.605 0.18 311.865 8.7 ; + RECT 312.115 0.18 312.375 8.7 ; + RECT 312.625 0.17 313.395 0.43 ; + RECT 312.625 0.17 312.885 8.7 ; + RECT 313.135 0.17 313.395 8.7 ; + RECT 285.82 74.03 286.02 74.84 ; + RECT 310.585 0.3 310.845 8.7 ; + RECT 314.665 0.18 315.435 0.88 ; + RECT 314.665 0.18 314.925 8.7 ; + RECT 315.175 0.18 315.435 8.7 ; + RECT 311.095 0.3 311.355 8.7 ; + RECT 313.645 0 313.905 8.7 ; + RECT 314.155 0 314.415 8.7 ; + RECT 315.685 0.52 315.945 8.7 ; + RECT 316.195 0.3 316.455 8.7 ; + RECT 316.705 0.3 316.965 8.7 ; + RECT 317.215 0.3 317.475 8.7 ; + RECT 317.725 0.3 317.985 8.7 ; + RECT 318.235 0.3 318.495 8.7 ; + RECT 318.745 0.3 319.005 8.7 ; + RECT 319.255 0.3 319.515 8.7 ; + RECT 321.295 0.18 322.065 0.88 ; + RECT 321.295 0.18 321.555 8.7 ; + RECT 321.805 0.18 322.065 8.7 ; + RECT 319.765 0.3 320.025 8.7 ; + RECT 320.275 0 320.535 8.7 ; + RECT 320.785 0 321.045 8.7 ; + RECT 322.315 0 322.575 8.7 ; + RECT 322.825 0 323.085 8.7 ; + RECT 323.335 0 323.595 8.7 ; + RECT 323.845 0 324.105 8.7 ; + RECT 324.355 0 324.615 8.7 ; + RECT 324.865 0 325.125 8.7 ; + RECT 325.375 0 325.635 8.7 ; + RECT 325.885 0.52 326.145 8.7 ; + RECT 326.395 0 326.655 8.7 ; + RECT 326.905 0.52 327.165 8.7 ; + RECT 327.415 0.3 327.675 8.7 ; + RECT 327.925 0.3 328.185 8.7 ; + RECT 328.435 0.3 328.695 8.7 ; + RECT 328.945 0 329.205 8.7 ; + RECT 329.455 0 329.715 8.7 ; + RECT 329.965 0.3 330.225 8.7 ; + RECT 330.475 0.3 330.735 8.7 ; + RECT 330.985 0.3 331.245 8.7 ; + RECT 331.495 0 331.755 8.7 ; + RECT 332.005 0 332.265 8.7 ; + RECT 332.515 0.3 332.775 8.7 ; + RECT 333.025 0.52 333.285 8.7 ; + RECT 333.535 0.52 333.795 8.7 ; + RECT 334.045 0 334.305 8.7 ; + RECT 334.555 0.52 334.815 8.7 ; + RECT 335.065 0.52 335.325 8.7 ; + RECT 335.575 0.3 335.835 8.7 ; + RECT 336.085 0.52 336.345 8.7 ; + RECT 336.595 0.52 336.855 8.7 ; + RECT 337.105 0.3 337.365 8.7 ; + RECT 337.615 0 337.875 8.7 ; + RECT 339.655 0.17 340.425 0.43 ; + RECT 339.655 0.17 339.915 8.7 ; + RECT 340.165 0.17 340.425 8.7 ; + RECT 338.125 0 338.385 8.7 ; + RECT 338.635 0.3 338.895 8.7 ; + RECT 339.145 0.3 339.405 8.7 ; + RECT 342.205 0.17 342.975 0.43 ; + RECT 342.205 0.17 342.465 8.7 ; + RECT 342.715 0.17 342.975 8.7 ; + RECT 340.675 0.3 340.935 8.7 ; + RECT 343.735 0.18 344.505 0.88 ; + RECT 343.735 0.18 343.995 8.7 ; + RECT 344.245 0.18 344.505 8.7 ; + RECT 341.185 0.3 341.445 8.7 ; + RECT 341.695 0.3 341.955 8.7 ; + RECT 343.225 0.3 343.485 8.7 ; + RECT 344.755 0 345.015 8.7 ; + RECT 345.265 0 345.525 8.7 ; + RECT 345.775 0 346.035 8.7 ; + RECT 346.285 0.52 346.545 8.7 ; + RECT 346.795 0 347.055 8.7 ; + RECT 347.305 0.52 347.565 8.7 ; + RECT 347.815 0 348.075 8.7 ; + RECT 348.325 0 348.585 8.7 ; + RECT 348.835 0.3 349.095 8.7 ; + RECT 349.345 0.3 349.605 8.7 ; + RECT 349.855 0 350.115 8.7 ; + RECT 350.365 0 350.625 8.7 ; + RECT 350.875 0.3 351.135 8.7 ; + RECT 351.695 0.3 351.955 8.7 ; + RECT 352.205 0 352.465 8.7 ; + RECT 352.715 0 352.975 8.7 ; + RECT 353.225 0.3 353.485 8.7 ; + RECT 353.735 0.3 353.995 8.7 ; + RECT 354.245 0 354.505 8.7 ; + RECT 354.755 0 355.015 8.7 ; + RECT 355.265 0.52 355.525 8.7 ; + RECT 355.775 0 356.035 8.7 ; + RECT 356.285 0.52 356.545 8.7 ; + RECT 358.325 0.18 359.095 0.88 ; + RECT 358.325 0.18 358.585 8.7 ; + RECT 358.835 0.18 359.095 8.7 ; + RECT 356.795 0 357.055 8.7 ; + RECT 359.855 0.17 360.625 0.43 ; + RECT 359.855 0.17 360.115 8.7 ; + RECT 360.365 0.17 360.625 8.7 ; + RECT 357.305 0 357.565 8.7 ; + RECT 357.815 0 358.075 8.7 ; + RECT 359.345 0.3 359.605 8.7 ; + RECT 362.405 0.17 363.175 0.43 ; + RECT 362.405 0.17 362.665 8.7 ; + RECT 362.915 0.17 363.175 8.7 ; + RECT 360.875 0.3 361.135 8.7 ; + RECT 361.385 0.3 361.645 8.7 ; + RECT 361.895 0.3 362.155 8.7 ; + RECT 363.425 0.3 363.685 8.7 ; + RECT 363.935 0.3 364.195 8.7 ; + RECT 364.445 0 364.705 8.7 ; + RECT 364.955 0 365.215 8.7 ; + RECT 365.465 0.3 365.725 8.7 ; + RECT 365.975 0.52 366.235 8.7 ; + RECT 366.485 0.52 366.745 8.7 ; + RECT 366.995 0.3 367.255 8.7 ; + RECT 367.505 0.52 367.765 8.7 ; + RECT 368.015 0.52 368.275 8.7 ; + RECT 368.525 0 368.785 8.7 ; + RECT 369.035 0.52 369.295 8.7 ; + RECT 369.545 0.52 369.805 8.7 ; + RECT 370.055 0.3 370.315 8.7 ; + RECT 370.565 0 370.825 8.7 ; + RECT 371.075 0 371.335 8.7 ; + RECT 371.585 0.3 371.845 8.7 ; + RECT 372.095 0.3 372.355 8.7 ; + RECT 372.605 0.3 372.865 8.7 ; + RECT 373.115 0 373.375 8.7 ; + RECT 373.625 0 373.885 8.7 ; + RECT 374.135 0.3 374.395 8.7 ; + RECT 374.645 0.3 374.905 8.7 ; + RECT 375.155 0.3 375.415 8.7 ; + RECT 375.665 0.52 375.925 8.7 ; + RECT 376.175 0 376.435 8.7 ; + RECT 376.685 0.52 376.945 8.7 ; + RECT 377.195 0 377.455 8.7 ; + RECT 377.705 0 377.965 8.7 ; + RECT 378.215 0 378.475 8.7 ; + RECT 378.725 0 378.985 8.7 ; + RECT 380.765 0.18 381.535 0.88 ; + RECT 380.765 0.18 381.025 8.7 ; + RECT 381.275 0.18 381.535 8.7 ; + RECT 379.235 0 379.495 8.7 ; + RECT 379.745 0 380.005 8.7 ; + RECT 380.255 0 380.515 8.7 ; + RECT 381.785 0 382.045 8.7 ; + RECT 382.295 0 382.555 8.7 ; + RECT 382.805 0.3 383.065 8.7 ; + RECT 383.315 0.3 383.575 8.7 ; + RECT 383.825 0.3 384.085 8.7 ; + RECT 384.335 0.3 384.595 8.7 ; + RECT 384.845 0.3 385.105 8.7 ; + RECT 385.355 0.3 385.615 8.7 ; + RECT 387.395 0.18 388.165 0.88 ; + RECT 387.395 0.18 387.655 8.7 ; + RECT 387.905 0.18 388.165 8.7 ; + RECT 385.865 0.3 386.125 8.7 ; + RECT 386.375 0.3 386.635 8.7 ; + RECT 389.435 0.17 390.205 0.43 ; + RECT 389.435 0.17 389.695 8.7 ; + RECT 389.945 0.17 390.205 8.7 ; + RECT 390.455 0.18 391.225 0.88 ; + RECT 390.455 0.18 390.715 8.7 ; + RECT 390.965 0.18 391.225 8.7 ; + RECT 386.885 0.52 387.145 8.7 ; + RECT 388.415 0 388.675 8.7 ; + RECT 392.85 0.18 393.62 0.88 ; + RECT 392.85 0.18 393.11 8.7 ; + RECT 393.36 0.18 393.62 8.7 ; + RECT 393.87 0.17 394.64 0.43 ; + RECT 393.87 0.17 394.13 8.7 ; + RECT 394.38 0.17 394.64 8.7 ; + RECT 394.89 0.18 395.66 0.88 ; + RECT 394.89 0.18 395.15 8.7 ; + RECT 395.4 0.18 395.66 8.7 ; + RECT 395.91 0.17 396.68 0.43 ; + RECT 395.91 0.17 396.17 8.7 ; + RECT 396.42 0.17 396.68 8.7 ; + RECT 396.93 0.18 397.7 0.88 ; + RECT 396.93 0.18 397.19 8.7 ; + RECT 397.44 0.18 397.7 8.7 ; + RECT 397.95 0.17 398.72 0.43 ; + RECT 397.95 0.17 398.21 8.7 ; + RECT 398.46 0.17 398.72 8.7 ; + RECT 398.97 0.18 399.74 0.88 ; + RECT 398.97 0.18 399.23 8.7 ; + RECT 399.48 0.18 399.74 8.7 ; + RECT 399.99 0.17 400.76 0.43 ; + RECT 399.99 0.17 400.25 8.7 ; + RECT 400.5 0.17 400.76 8.7 ; + RECT 401.01 0.18 401.78 0.88 ; + RECT 401.01 0.18 401.27 8.7 ; + RECT 401.52 0.18 401.78 8.7 ; + RECT 402.03 0.17 402.8 0.43 ; + RECT 402.03 0.17 402.29 8.7 ; + RECT 402.54 0.17 402.8 8.7 ; + RECT 403.05 0.18 403.82 0.88 ; + RECT 403.05 0.18 403.31 8.7 ; + RECT 403.56 0.18 403.82 8.7 ; + RECT 404.07 0.17 404.84 0.43 ; + RECT 404.07 0.17 404.33 8.7 ; + RECT 404.58 0.17 404.84 8.7 ; + RECT 405.09 0.18 405.86 0.88 ; + RECT 405.09 0.18 405.35 8.7 ; + RECT 405.6 0.18 405.86 8.7 ; + RECT 406.11 0.17 406.88 0.43 ; + RECT 406.11 0.17 406.37 8.7 ; + RECT 406.62 0.17 406.88 8.7 ; + RECT 407.13 0.18 407.9 0.88 ; + RECT 407.13 0.18 407.39 8.7 ; + RECT 407.64 0.18 407.9 8.7 ; + RECT 408.15 0.17 408.92 0.43 ; + RECT 408.15 0.17 408.41 8.7 ; + RECT 408.66 0.17 408.92 8.7 ; + RECT 409.17 0.18 409.94 0.88 ; + RECT 409.17 0.18 409.43 8.7 ; + RECT 409.68 0.18 409.94 8.7 ; + RECT 410.19 0.17 410.96 0.43 ; + RECT 410.19 0.17 410.45 8.7 ; + RECT 410.7 0.17 410.96 8.7 ; + RECT 411.21 0.18 411.98 0.88 ; + RECT 411.21 0.18 411.47 8.7 ; + RECT 411.72 0.18 411.98 8.7 ; + RECT 412.23 0.17 413 0.43 ; + RECT 412.23 0.17 412.49 8.7 ; + RECT 412.74 0.17 413 8.7 ; + RECT 413.25 0.18 414.02 0.88 ; + RECT 413.25 0.18 413.51 8.7 ; + RECT 413.76 0.18 414.02 8.7 ; + RECT 414.27 0.17 415.04 0.43 ; + RECT 414.27 0.17 414.53 8.7 ; + RECT 414.78 0.17 415.04 8.7 ; + RECT 415.29 0.18 416.06 0.88 ; + RECT 415.29 0.18 415.55 8.7 ; + RECT 415.8 0.18 416.06 8.7 ; + RECT 388.925 0 389.185 8.7 ; + RECT 416.31 0.17 417.08 0.43 ; + RECT 416.31 0.17 416.57 8.7 ; + RECT 416.82 0.17 417.08 8.7 ; + RECT 391.475 0.3 391.735 8.7 ; + RECT 391.985 0.3 392.245 8.7 ; + RECT 416.81 74.03 417.01 74.84 ; + RECT 417.635 74.11 417.835 74.84 ; + RECT 418.045 74.11 418.405 74.84 ; + RECT 418.35 0.52 418.61 4.315 ; + RECT 418.615 74.11 418.815 74.84 ; + RECT 419.27 74.11 419.47 74.84 ; + RECT 419.525 0 419.785 2.82 ; + RECT 419.68 74.11 420.04 74.84 ; + RECT 420.335 74.11 420.535 74.84 ; + RECT 420.83 74.11 421.19 74.84 ; + RECT 421.765 0.18 422.535 0.88 ; + RECT 421.765 0.18 422.025 12.9 ; + RECT 422.275 0.18 422.535 12.9 ; + RECT 421.055 0 421.315 2.82 ; + RECT 421.4 74.11 421.6 74.84 ; + RECT 422.785 0.155 423.555 0.445 ; + RECT 422.785 0.155 423.045 13.21 ; + RECT 423.295 0.155 423.555 13.21 ; + RECT 422.055 74.11 422.255 74.84 ; + RECT 422.465 74.11 422.825 74.84 ; + RECT 423.035 74.11 423.235 74.84 ; + RECT 423.69 74.11 423.89 74.84 ; + RECT 424.1 74.11 424.46 74.84 ; + RECT 424.755 74.11 424.955 74.84 ; + RECT 425.25 74.11 425.61 74.84 ; + RECT 425.49 0.52 425.75 14.115 ; + RECT 425.82 74.11 426.02 74.84 ; + RECT 426 0 426.26 13.45 ; + RECT 426.475 74.11 426.675 74.84 ; + RECT 427.02 0.155 427.79 0.445 ; + RECT 427.02 0.155 427.28 8.665 ; + RECT 427.53 0.155 427.79 8.665 ; + RECT 426.51 0 426.77 11.315 ; + RECT 426.885 74.11 427.245 74.84 ; + RECT 427.455 74.11 427.655 74.84 ; + RECT 428.04 0.52 428.3 9.955 ; + RECT 428.11 74.11 428.31 74.84 ; + RECT 428.52 74.11 428.88 74.84 ; + RECT 429.175 74.11 429.375 74.84 ; + RECT 429.67 74.11 430.03 74.84 ; + RECT 430.08 0.3 430.34 8.7 ; + RECT 430.24 74.11 430.44 74.84 ; + RECT 430.895 74.11 431.095 74.84 ; + RECT 430.59 0.18 431.36 0.88 ; + RECT 431.305 74.11 431.665 74.84 ; + RECT 431.875 74.11 432.075 74.84 ; + RECT 432.53 74.11 432.73 74.84 ; + RECT 432.785 0 433.045 6.28 ; + RECT 432.94 74.11 433.3 74.84 ; + RECT 433.595 74.11 433.795 74.84 ; + RECT 434.16 0 434.42 5.57 ; + RECT 434.09 74.11 434.45 74.84 ; + RECT 434.66 74.11 434.86 74.84 ; + RECT 434.67 0.3 434.93 5.235 ; + RECT 435.18 0.52 435.44 7.78 ; + RECT 435.315 74.11 435.515 74.84 ; + RECT 435.725 74.11 436.085 74.84 ; + RECT 436.03 0.52 436.29 4.315 ; + RECT 436.295 74.11 436.495 74.84 ; + RECT 436.95 74.11 437.15 74.84 ; + RECT 437.205 0 437.465 2.82 ; + RECT 437.36 74.11 437.72 74.84 ; + RECT 438.015 74.11 438.215 74.84 ; + RECT 438.51 74.11 438.87 74.84 ; + RECT 439.445 0.18 440.215 0.88 ; + RECT 439.445 0.18 439.705 12.9 ; + RECT 439.955 0.18 440.215 12.9 ; + RECT 438.735 0 438.995 2.82 ; + RECT 439.08 74.11 439.28 74.84 ; + RECT 440.465 0.155 441.235 0.445 ; + RECT 440.465 0.155 440.725 13.21 ; + RECT 440.975 0.155 441.235 13.21 ; + RECT 439.735 74.11 439.935 74.84 ; + RECT 440.145 74.11 440.505 74.84 ; + RECT 440.715 74.11 440.915 74.84 ; + RECT 441.37 74.11 441.57 74.84 ; + RECT 441.78 74.11 442.14 74.84 ; + RECT 442.435 74.11 442.635 74.84 ; + RECT 442.93 74.11 443.29 74.84 ; + RECT 443.17 0.52 443.43 14.115 ; + RECT 443.5 74.11 443.7 74.84 ; + RECT 443.68 0 443.94 13.45 ; + RECT 444.155 74.11 444.355 74.84 ; + RECT 444.7 0.155 445.47 0.445 ; + RECT 444.7 0.155 444.96 8.665 ; + RECT 445.21 0.155 445.47 8.665 ; + RECT 444.19 0 444.45 11.315 ; + RECT 444.565 74.11 444.925 74.84 ; + RECT 445.135 74.11 445.335 74.84 ; + RECT 445.72 0.52 445.98 9.955 ; + RECT 445.79 74.11 445.99 74.84 ; + RECT 446.2 74.11 446.56 74.84 ; + RECT 446.855 74.11 447.055 74.84 ; + RECT 447.35 74.11 447.71 74.84 ; + RECT 447.76 0.3 448.02 8.7 ; + RECT 447.92 74.11 448.12 74.84 ; + RECT 448.575 74.11 448.775 74.84 ; + RECT 448.27 0.18 449.04 0.88 ; + RECT 448.985 74.11 449.345 74.84 ; + RECT 449.555 74.11 449.755 74.84 ; + RECT 450.21 74.11 450.41 74.84 ; + RECT 450.465 0 450.725 6.28 ; + RECT 450.62 74.11 450.98 74.84 ; + RECT 451.275 74.11 451.475 74.84 ; + RECT 451.84 0 452.1 5.57 ; + RECT 451.77 74.11 452.13 74.84 ; + RECT 452.34 74.11 452.54 74.84 ; + RECT 452.35 0.3 452.61 5.235 ; + RECT 452.86 0.52 453.12 7.78 ; + RECT 452.995 74.11 453.195 74.84 ; + RECT 453.405 74.11 453.765 74.84 ; + RECT 453.71 0.52 453.97 4.315 ; + RECT 453.975 74.11 454.175 74.84 ; + RECT 454.63 74.11 454.83 74.84 ; + RECT 454.885 0 455.145 2.82 ; + RECT 455.04 74.11 455.4 74.84 ; + RECT 455.695 74.11 455.895 74.84 ; + RECT 456.19 74.11 456.55 74.84 ; + RECT 457.125 0.18 457.895 0.88 ; + RECT 457.125 0.18 457.385 12.9 ; + RECT 457.635 0.18 457.895 12.9 ; + RECT 456.415 0 456.675 2.82 ; + RECT 456.76 74.11 456.96 74.84 ; + RECT 458.145 0.155 458.915 0.445 ; + RECT 458.145 0.155 458.405 13.21 ; + RECT 458.655 0.155 458.915 13.21 ; + RECT 457.415 74.11 457.615 74.84 ; + RECT 457.825 74.11 458.185 74.84 ; + RECT 458.395 74.11 458.595 74.84 ; + RECT 459.05 74.11 459.25 74.84 ; + RECT 459.46 74.11 459.82 74.84 ; + RECT 460.115 74.11 460.315 74.84 ; + RECT 460.61 74.11 460.97 74.84 ; + RECT 460.85 0.52 461.11 14.115 ; + RECT 461.18 74.11 461.38 74.84 ; + RECT 461.36 0 461.62 13.45 ; + RECT 461.835 74.11 462.035 74.84 ; + RECT 462.38 0.155 463.15 0.445 ; + RECT 462.38 0.155 462.64 8.665 ; + RECT 462.89 0.155 463.15 8.665 ; + RECT 461.87 0 462.13 11.315 ; + RECT 462.245 74.11 462.605 74.84 ; + RECT 462.815 74.11 463.015 74.84 ; + RECT 463.4 0.52 463.66 9.955 ; + RECT 463.47 74.11 463.67 74.84 ; + RECT 463.88 74.11 464.24 74.84 ; + RECT 464.535 74.11 464.735 74.84 ; + RECT 465.03 74.11 465.39 74.84 ; + RECT 465.44 0.3 465.7 8.7 ; + RECT 465.6 74.11 465.8 74.84 ; + RECT 466.255 74.11 466.455 74.84 ; + RECT 465.95 0.18 466.72 0.88 ; + RECT 466.665 74.11 467.025 74.84 ; + RECT 467.235 74.11 467.435 74.84 ; + RECT 467.89 74.11 468.09 74.84 ; + RECT 468.145 0 468.405 6.28 ; + RECT 468.3 74.11 468.66 74.84 ; + RECT 468.955 74.11 469.155 74.84 ; + RECT 469.52 0 469.78 5.57 ; + RECT 469.45 74.11 469.81 74.84 ; + RECT 470.02 74.11 470.22 74.84 ; + RECT 470.03 0.3 470.29 5.235 ; + RECT 470.54 0.52 470.8 7.78 ; + RECT 470.675 74.11 470.875 74.84 ; + RECT 471.085 74.11 471.445 74.84 ; + RECT 471.39 0.52 471.65 4.315 ; + RECT 471.655 74.11 471.855 74.84 ; + RECT 472.31 74.11 472.51 74.84 ; + RECT 472.565 0 472.825 2.82 ; + RECT 472.72 74.11 473.08 74.84 ; + RECT 473.375 74.11 473.575 74.84 ; + RECT 473.87 74.11 474.23 74.84 ; + RECT 474.805 0.18 475.575 0.88 ; + RECT 474.805 0.18 475.065 12.9 ; + RECT 475.315 0.18 475.575 12.9 ; + RECT 474.095 0 474.355 2.82 ; + RECT 474.44 74.11 474.64 74.84 ; + RECT 475.825 0.155 476.595 0.445 ; + RECT 475.825 0.155 476.085 13.21 ; + RECT 476.335 0.155 476.595 13.21 ; + RECT 475.095 74.11 475.295 74.84 ; + RECT 475.505 74.11 475.865 74.84 ; + RECT 476.075 74.11 476.275 74.84 ; + RECT 476.73 74.11 476.93 74.84 ; + RECT 477.14 74.11 477.5 74.84 ; + RECT 477.795 74.11 477.995 74.84 ; + RECT 478.29 74.11 478.65 74.84 ; + RECT 478.53 0.52 478.79 14.115 ; + RECT 478.86 74.11 479.06 74.84 ; + RECT 479.04 0 479.3 13.45 ; + RECT 479.515 74.11 479.715 74.84 ; + RECT 480.06 0.155 480.83 0.445 ; + RECT 480.06 0.155 480.32 8.665 ; + RECT 480.57 0.155 480.83 8.665 ; + RECT 479.55 0 479.81 11.315 ; + RECT 479.925 74.11 480.285 74.84 ; + RECT 480.495 74.11 480.695 74.84 ; + RECT 481.08 0.52 481.34 9.955 ; + RECT 481.15 74.11 481.35 74.84 ; + RECT 481.56 74.11 481.92 74.84 ; + RECT 482.215 74.11 482.415 74.84 ; + RECT 482.71 74.11 483.07 74.84 ; + RECT 483.12 0.3 483.38 8.7 ; + RECT 483.28 74.11 483.48 74.84 ; + RECT 483.935 74.11 484.135 74.84 ; + RECT 483.63 0.18 484.4 0.88 ; + RECT 484.345 74.11 484.705 74.84 ; + RECT 484.915 74.11 485.115 74.84 ; + RECT 485.57 74.11 485.77 74.84 ; + RECT 485.825 0 486.085 6.28 ; + RECT 485.98 74.11 486.34 74.84 ; + RECT 486.635 74.11 486.835 74.84 ; + RECT 487.2 0 487.46 5.57 ; + RECT 487.13 74.11 487.49 74.84 ; + RECT 487.7 74.11 487.9 74.84 ; + RECT 487.71 0.3 487.97 5.235 ; + RECT 488.22 0.52 488.48 7.78 ; + RECT 488.355 74.11 488.555 74.84 ; + RECT 488.765 74.11 489.125 74.84 ; + RECT 489.07 0.52 489.33 4.315 ; + RECT 489.335 74.11 489.535 74.84 ; + RECT 489.99 74.11 490.19 74.84 ; + RECT 490.245 0 490.505 2.82 ; + RECT 490.4 74.11 490.76 74.84 ; + RECT 491.055 74.11 491.255 74.84 ; + RECT 491.55 74.11 491.91 74.84 ; + RECT 492.485 0.18 493.255 0.88 ; + RECT 492.485 0.18 492.745 12.9 ; + RECT 492.995 0.18 493.255 12.9 ; + RECT 491.775 0 492.035 2.82 ; + RECT 492.12 74.11 492.32 74.84 ; + RECT 493.505 0.155 494.275 0.445 ; + RECT 493.505 0.155 493.765 13.21 ; + RECT 494.015 0.155 494.275 13.21 ; + RECT 492.775 74.11 492.975 74.84 ; + RECT 493.185 74.11 493.545 74.84 ; + RECT 493.755 74.11 493.955 74.84 ; + RECT 494.41 74.11 494.61 74.84 ; + RECT 494.82 74.11 495.18 74.84 ; + RECT 495.475 74.11 495.675 74.84 ; + RECT 495.97 74.11 496.33 74.84 ; + RECT 496.21 0.52 496.47 14.115 ; + RECT 496.54 74.11 496.74 74.84 ; + RECT 496.72 0 496.98 13.45 ; + RECT 497.195 74.11 497.395 74.84 ; + RECT 497.74 0.155 498.51 0.445 ; + RECT 497.74 0.155 498 8.665 ; + RECT 498.25 0.155 498.51 8.665 ; + RECT 497.23 0 497.49 11.315 ; + RECT 497.605 74.11 497.965 74.84 ; + RECT 498.175 74.11 498.375 74.84 ; + RECT 498.76 0.52 499.02 9.955 ; + RECT 498.83 74.11 499.03 74.84 ; + RECT 499.24 74.11 499.6 74.84 ; + RECT 499.895 74.11 500.095 74.84 ; + RECT 500.39 74.11 500.75 74.84 ; + RECT 500.8 0.3 501.06 8.7 ; + RECT 500.96 74.11 501.16 74.84 ; + RECT 501.615 74.11 501.815 74.84 ; + RECT 501.31 0.18 502.08 0.88 ; + RECT 502.025 74.11 502.385 74.84 ; + RECT 502.595 74.11 502.795 74.84 ; + RECT 503.25 74.11 503.45 74.84 ; + RECT 503.505 0 503.765 6.28 ; + RECT 503.66 74.11 504.02 74.84 ; + RECT 504.315 74.11 504.515 74.84 ; + RECT 504.88 0 505.14 5.57 ; + RECT 504.81 74.11 505.17 74.84 ; + RECT 505.38 74.11 505.58 74.84 ; + RECT 505.39 0.3 505.65 5.235 ; + RECT 505.9 0.52 506.16 7.78 ; + RECT 506.035 74.11 506.235 74.84 ; + RECT 506.445 74.11 506.805 74.84 ; + RECT 506.75 0.52 507.01 4.315 ; + RECT 507.015 74.11 507.215 74.84 ; + RECT 507.67 74.11 507.87 74.84 ; + RECT 507.925 0 508.185 2.82 ; + RECT 508.08 74.11 508.44 74.84 ; + RECT 508.735 74.11 508.935 74.84 ; + RECT 509.23 74.11 509.59 74.84 ; + RECT 510.165 0.18 510.935 0.88 ; + RECT 510.165 0.18 510.425 12.9 ; + RECT 510.675 0.18 510.935 12.9 ; + RECT 509.455 0 509.715 2.82 ; + RECT 509.8 74.11 510 74.84 ; + RECT 511.185 0.155 511.955 0.445 ; + RECT 511.185 0.155 511.445 13.21 ; + RECT 511.695 0.155 511.955 13.21 ; + RECT 510.455 74.11 510.655 74.84 ; + RECT 510.865 74.11 511.225 74.84 ; + RECT 511.435 74.11 511.635 74.84 ; + RECT 512.09 74.11 512.29 74.84 ; + RECT 512.5 74.11 512.86 74.84 ; + RECT 513.155 74.11 513.355 74.84 ; + RECT 513.65 74.11 514.01 74.84 ; + RECT 513.89 0.52 514.15 14.115 ; + RECT 514.22 74.11 514.42 74.84 ; + RECT 514.4 0 514.66 13.45 ; + RECT 514.875 74.11 515.075 74.84 ; + RECT 515.42 0.155 516.19 0.445 ; + RECT 515.42 0.155 515.68 8.665 ; + RECT 515.93 0.155 516.19 8.665 ; + RECT 514.91 0 515.17 11.315 ; + RECT 515.285 74.11 515.645 74.84 ; + RECT 515.855 74.11 516.055 74.84 ; + RECT 516.44 0.52 516.7 9.955 ; + RECT 516.51 74.11 516.71 74.84 ; + RECT 516.92 74.11 517.28 74.84 ; + RECT 517.575 74.11 517.775 74.84 ; + RECT 518.07 74.11 518.43 74.84 ; + RECT 518.48 0.3 518.74 8.7 ; + RECT 518.64 74.11 518.84 74.84 ; + RECT 519.295 74.11 519.495 74.84 ; + RECT 518.99 0.18 519.76 0.88 ; + RECT 519.705 74.11 520.065 74.84 ; + RECT 520.275 74.11 520.475 74.84 ; + RECT 520.93 74.11 521.13 74.84 ; + RECT 521.185 0 521.445 6.28 ; + RECT 521.34 74.11 521.7 74.84 ; + RECT 521.995 74.11 522.195 74.84 ; + RECT 522.56 0 522.82 5.57 ; + RECT 522.49 74.11 522.85 74.84 ; + RECT 523.06 74.11 523.26 74.84 ; + RECT 523.07 0.3 523.33 5.235 ; + RECT 523.58 0.52 523.84 7.78 ; + RECT 523.715 74.11 523.915 74.84 ; + RECT 524.125 74.11 524.485 74.84 ; + RECT 524.43 0.52 524.69 4.315 ; + RECT 524.695 74.11 524.895 74.84 ; + RECT 525.35 74.11 525.55 74.84 ; + RECT 525.605 0 525.865 2.82 ; + RECT 525.76 74.11 526.12 74.84 ; + RECT 526.415 74.11 526.615 74.84 ; + RECT 526.91 74.11 527.27 74.84 ; + RECT 527.845 0.18 528.615 0.88 ; + RECT 527.845 0.18 528.105 12.9 ; + RECT 528.355 0.18 528.615 12.9 ; + RECT 527.135 0 527.395 2.82 ; + RECT 527.48 74.11 527.68 74.84 ; + RECT 528.865 0.155 529.635 0.445 ; + RECT 528.865 0.155 529.125 13.21 ; + RECT 529.375 0.155 529.635 13.21 ; + RECT 528.135 74.11 528.335 74.84 ; + RECT 528.545 74.11 528.905 74.84 ; + RECT 529.115 74.11 529.315 74.84 ; + RECT 529.77 74.11 529.97 74.84 ; + RECT 530.18 74.11 530.54 74.84 ; + RECT 530.835 74.11 531.035 74.84 ; + RECT 531.33 74.11 531.69 74.84 ; + RECT 531.57 0.52 531.83 14.115 ; + RECT 531.9 74.11 532.1 74.84 ; + RECT 532.08 0 532.34 13.45 ; + RECT 532.555 74.11 532.755 74.84 ; + RECT 533.1 0.155 533.87 0.445 ; + RECT 533.1 0.155 533.36 8.665 ; + RECT 533.61 0.155 533.87 8.665 ; + RECT 532.59 0 532.85 11.315 ; + RECT 532.965 74.11 533.325 74.84 ; + RECT 533.535 74.11 533.735 74.84 ; + RECT 534.12 0.52 534.38 9.955 ; + RECT 534.19 74.11 534.39 74.84 ; + RECT 534.6 74.11 534.96 74.84 ; + RECT 535.255 74.11 535.455 74.84 ; + RECT 535.75 74.11 536.11 74.84 ; + RECT 536.16 0.3 536.42 8.7 ; + RECT 536.32 74.11 536.52 74.84 ; + RECT 536.975 74.11 537.175 74.84 ; + RECT 536.67 0.18 537.44 0.88 ; + RECT 537.385 74.11 537.745 74.84 ; + RECT 537.955 74.11 538.155 74.84 ; + RECT 538.61 74.11 538.81 74.84 ; + RECT 538.865 0 539.125 6.28 ; + RECT 539.02 74.11 539.38 74.84 ; + RECT 539.675 74.11 539.875 74.84 ; + RECT 540.24 0 540.5 5.57 ; + RECT 540.17 74.11 540.53 74.84 ; + RECT 540.74 74.11 540.94 74.84 ; + RECT 540.75 0.3 541.01 5.235 ; + RECT 541.26 0.52 541.52 7.78 ; + RECT 541.395 74.11 541.595 74.84 ; + RECT 541.805 74.11 542.165 74.84 ; + RECT 542.11 0.52 542.37 4.315 ; + RECT 542.375 74.11 542.575 74.84 ; + RECT 543.03 74.11 543.23 74.84 ; + RECT 543.285 0 543.545 2.82 ; + RECT 543.44 74.11 543.8 74.84 ; + RECT 544.095 74.11 544.295 74.84 ; + RECT 544.59 74.11 544.95 74.84 ; + RECT 545.525 0.18 546.295 0.88 ; + RECT 545.525 0.18 545.785 12.9 ; + RECT 546.035 0.18 546.295 12.9 ; + RECT 544.815 0 545.075 2.82 ; + RECT 545.16 74.11 545.36 74.84 ; + RECT 546.545 0.155 547.315 0.445 ; + RECT 546.545 0.155 546.805 13.21 ; + RECT 547.055 0.155 547.315 13.21 ; + RECT 545.815 74.11 546.015 74.84 ; + RECT 546.225 74.11 546.585 74.84 ; + RECT 546.795 74.11 546.995 74.84 ; + RECT 547.45 74.11 547.65 74.84 ; + RECT 547.86 74.11 548.22 74.84 ; + RECT 548.515 74.11 548.715 74.84 ; + RECT 549.01 74.11 549.37 74.84 ; + RECT 549.25 0.52 549.51 14.115 ; + RECT 549.58 74.11 549.78 74.84 ; + RECT 549.76 0 550.02 13.45 ; + RECT 550.235 74.11 550.435 74.84 ; + RECT 550.78 0.155 551.55 0.445 ; + RECT 550.78 0.155 551.04 8.665 ; + RECT 551.29 0.155 551.55 8.665 ; + RECT 550.27 0 550.53 11.315 ; + RECT 550.645 74.11 551.005 74.84 ; + RECT 551.215 74.11 551.415 74.84 ; + RECT 551.8 0.52 552.06 9.955 ; + RECT 551.87 74.11 552.07 74.84 ; + RECT 552.28 74.11 552.64 74.84 ; + RECT 552.935 74.11 553.135 74.84 ; + RECT 553.43 74.11 553.79 74.84 ; + RECT 553.84 0.3 554.1 8.7 ; + RECT 554 74.11 554.2 74.84 ; + RECT 554.655 74.11 554.855 74.84 ; + RECT 554.35 0.18 555.12 0.88 ; + RECT 555.065 74.11 555.425 74.84 ; + RECT 555.635 74.11 555.835 74.84 ; + RECT 556.29 74.11 556.49 74.84 ; + RECT 556.545 0 556.805 6.28 ; + RECT 556.7 74.11 557.06 74.84 ; + RECT 557.355 74.11 557.555 74.84 ; + RECT 557.92 0 558.18 5.57 ; + RECT 557.85 74.11 558.21 74.84 ; + RECT 558.42 74.11 558.62 74.84 ; + RECT 558.43 0.3 558.69 5.235 ; + RECT 558.94 0.52 559.2 7.78 ; + RECT 559.075 74.11 559.275 74.84 ; + RECT 559.485 74.11 559.845 74.84 ; + RECT 559.79 0.52 560.05 4.315 ; + RECT 560.055 74.11 560.255 74.84 ; + RECT 560.71 74.11 560.91 74.84 ; + RECT 560.965 0 561.225 2.82 ; + RECT 561.12 74.11 561.48 74.84 ; + RECT 561.775 74.11 561.975 74.84 ; + RECT 562.27 74.11 562.63 74.84 ; + RECT 563.205 0.18 563.975 0.88 ; + RECT 563.205 0.18 563.465 12.9 ; + RECT 563.715 0.18 563.975 12.9 ; + RECT 562.495 0 562.755 2.82 ; + RECT 562.84 74.11 563.04 74.84 ; + RECT 564.225 0.155 564.995 0.445 ; + RECT 564.225 0.155 564.485 13.21 ; + RECT 564.735 0.155 564.995 13.21 ; + RECT 563.495 74.11 563.695 74.84 ; + RECT 563.905 74.11 564.265 74.84 ; + RECT 564.475 74.11 564.675 74.84 ; + RECT 565.13 74.11 565.33 74.84 ; + RECT 565.54 74.11 565.9 74.84 ; + RECT 566.195 74.11 566.395 74.84 ; + RECT 566.69 74.11 567.05 74.84 ; + RECT 566.93 0.52 567.19 14.115 ; + RECT 567.26 74.11 567.46 74.84 ; + RECT 567.44 0 567.7 13.45 ; + RECT 567.915 74.11 568.115 74.84 ; + RECT 568.46 0.155 569.23 0.445 ; + RECT 568.46 0.155 568.72 8.665 ; + RECT 568.97 0.155 569.23 8.665 ; + RECT 567.95 0 568.21 11.315 ; + RECT 568.325 74.11 568.685 74.84 ; + RECT 568.895 74.11 569.095 74.84 ; + RECT 569.48 0.52 569.74 9.955 ; + RECT 569.55 74.11 569.75 74.84 ; + RECT 569.96 74.11 570.32 74.84 ; + RECT 570.615 74.11 570.815 74.84 ; + RECT 571.11 74.11 571.47 74.84 ; + RECT 571.52 0.3 571.78 8.7 ; + RECT 571.68 74.11 571.88 74.84 ; + RECT 572.335 74.11 572.535 74.84 ; + RECT 572.03 0.18 572.8 0.88 ; + RECT 572.745 74.11 573.105 74.84 ; + RECT 573.315 74.11 573.515 74.84 ; + RECT 573.97 74.11 574.17 74.84 ; + RECT 574.225 0 574.485 6.28 ; + RECT 574.38 74.11 574.74 74.84 ; + RECT 575.035 74.11 575.235 74.84 ; + RECT 575.6 0 575.86 5.57 ; + RECT 575.53 74.11 575.89 74.84 ; + RECT 576.1 74.11 576.3 74.84 ; + RECT 576.11 0.3 576.37 5.235 ; + RECT 576.62 0.52 576.88 7.78 ; + RECT 576.755 74.11 576.955 74.84 ; + RECT 577.165 74.11 577.525 74.84 ; + RECT 577.47 0.52 577.73 4.315 ; + RECT 577.735 74.11 577.935 74.84 ; + RECT 578.39 74.11 578.59 74.84 ; + RECT 578.645 0 578.905 2.82 ; + RECT 578.8 74.11 579.16 74.84 ; + RECT 579.455 74.11 579.655 74.84 ; + RECT 579.95 74.11 580.31 74.84 ; + RECT 580.885 0.18 581.655 0.88 ; + RECT 580.885 0.18 581.145 12.9 ; + RECT 581.395 0.18 581.655 12.9 ; + RECT 580.175 0 580.435 2.82 ; + RECT 580.52 74.11 580.72 74.84 ; + RECT 581.905 0.155 582.675 0.445 ; + RECT 581.905 0.155 582.165 13.21 ; + RECT 582.415 0.155 582.675 13.21 ; + RECT 581.175 74.11 581.375 74.84 ; + RECT 581.585 74.11 581.945 74.84 ; + RECT 582.155 74.11 582.355 74.84 ; + RECT 582.81 74.11 583.01 74.84 ; + RECT 583.22 74.11 583.58 74.84 ; + RECT 583.875 74.11 584.075 74.84 ; + RECT 584.37 74.11 584.73 74.84 ; + RECT 584.61 0.52 584.87 14.115 ; + RECT 584.94 74.11 585.14 74.84 ; + RECT 585.12 0 585.38 13.45 ; + RECT 585.595 74.11 585.795 74.84 ; + RECT 586.14 0.155 586.91 0.445 ; + RECT 586.14 0.155 586.4 8.665 ; + RECT 586.65 0.155 586.91 8.665 ; + RECT 585.63 0 585.89 11.315 ; + RECT 586.005 74.11 586.365 74.84 ; + RECT 586.575 74.11 586.775 74.84 ; + RECT 587.16 0.52 587.42 9.955 ; + RECT 587.23 74.11 587.43 74.84 ; + RECT 587.64 74.11 588 74.84 ; + RECT 588.295 74.11 588.495 74.84 ; + RECT 588.79 74.11 589.15 74.84 ; + RECT 589.2 0.3 589.46 8.7 ; + RECT 589.36 74.11 589.56 74.84 ; + RECT 590.015 74.11 590.215 74.84 ; + RECT 589.71 0.18 590.48 0.88 ; + RECT 590.425 74.11 590.785 74.84 ; + RECT 590.995 74.11 591.195 74.84 ; + RECT 591.65 74.11 591.85 74.84 ; + RECT 591.905 0 592.165 6.28 ; + RECT 592.06 74.11 592.42 74.84 ; + RECT 592.715 74.11 592.915 74.84 ; + RECT 593.28 0 593.54 5.57 ; + RECT 593.21 74.11 593.57 74.84 ; + RECT 593.78 74.11 593.98 74.84 ; + RECT 593.79 0.3 594.05 5.235 ; + RECT 594.3 0.52 594.56 7.78 ; + RECT 594.435 74.11 594.635 74.84 ; + RECT 594.845 74.11 595.205 74.84 ; + RECT 595.15 0.52 595.41 4.315 ; + RECT 595.415 74.11 595.615 74.84 ; + RECT 596.07 74.11 596.27 74.84 ; + RECT 596.325 0 596.585 2.82 ; + RECT 596.48 74.11 596.84 74.84 ; + RECT 597.135 74.11 597.335 74.84 ; + RECT 597.63 74.11 597.99 74.84 ; + RECT 598.565 0.18 599.335 0.88 ; + RECT 598.565 0.18 598.825 12.9 ; + RECT 599.075 0.18 599.335 12.9 ; + RECT 597.855 0 598.115 2.82 ; + RECT 598.2 74.11 598.4 74.84 ; + RECT 599.585 0.155 600.355 0.445 ; + RECT 599.585 0.155 599.845 13.21 ; + RECT 600.095 0.155 600.355 13.21 ; + RECT 598.855 74.11 599.055 74.84 ; + RECT 599.265 74.11 599.625 74.84 ; + RECT 599.835 74.11 600.035 74.84 ; + RECT 600.49 74.11 600.69 74.84 ; + RECT 600.9 74.11 601.26 74.84 ; + RECT 601.555 74.11 601.755 74.84 ; + RECT 602.05 74.11 602.41 74.84 ; + RECT 602.29 0.52 602.55 14.115 ; + RECT 602.62 74.11 602.82 74.84 ; + RECT 602.8 0 603.06 13.45 ; + RECT 603.275 74.11 603.475 74.84 ; + RECT 603.82 0.155 604.59 0.445 ; + RECT 603.82 0.155 604.08 8.665 ; + RECT 604.33 0.155 604.59 8.665 ; + RECT 603.31 0 603.57 11.315 ; + RECT 603.685 74.11 604.045 74.84 ; + RECT 604.255 74.11 604.455 74.84 ; + RECT 604.84 0.52 605.1 9.955 ; + RECT 604.91 74.11 605.11 74.84 ; + RECT 605.32 74.11 605.68 74.84 ; + RECT 605.975 74.11 606.175 74.84 ; + RECT 606.47 74.11 606.83 74.84 ; + RECT 606.88 0.3 607.14 8.7 ; + RECT 607.04 74.11 607.24 74.84 ; + RECT 607.695 74.11 607.895 74.84 ; + RECT 607.39 0.18 608.16 0.88 ; + RECT 608.105 74.11 608.465 74.84 ; + RECT 608.675 74.11 608.875 74.84 ; + RECT 609.33 74.11 609.53 74.84 ; + RECT 609.585 0 609.845 6.28 ; + RECT 609.74 74.11 610.1 74.84 ; + RECT 610.395 74.11 610.595 74.84 ; + RECT 610.96 0 611.22 5.57 ; + RECT 610.89 74.11 611.25 74.84 ; + RECT 611.46 74.11 611.66 74.84 ; + RECT 611.47 0.3 611.73 5.235 ; + RECT 611.98 0.52 612.24 7.78 ; + RECT 612.115 74.11 612.315 74.84 ; + RECT 612.525 74.11 612.885 74.84 ; + RECT 612.83 0.52 613.09 4.315 ; + RECT 613.095 74.11 613.295 74.84 ; + RECT 613.75 74.11 613.95 74.84 ; + RECT 614.005 0 614.265 2.82 ; + RECT 614.16 74.11 614.52 74.84 ; + RECT 614.815 74.11 615.015 74.84 ; + RECT 615.31 74.11 615.67 74.84 ; + RECT 616.245 0.18 617.015 0.88 ; + RECT 616.245 0.18 616.505 12.9 ; + RECT 616.755 0.18 617.015 12.9 ; + RECT 615.535 0 615.795 2.82 ; + RECT 615.88 74.11 616.08 74.84 ; + RECT 617.265 0.155 618.035 0.445 ; + RECT 617.265 0.155 617.525 13.21 ; + RECT 617.775 0.155 618.035 13.21 ; + RECT 616.535 74.11 616.735 74.84 ; + RECT 616.945 74.11 617.305 74.84 ; + RECT 617.515 74.11 617.715 74.84 ; + RECT 618.17 74.11 618.37 74.84 ; + RECT 618.58 74.11 618.94 74.84 ; + RECT 619.235 74.11 619.435 74.84 ; + RECT 619.73 74.11 620.09 74.84 ; + RECT 619.97 0.52 620.23 14.115 ; + RECT 620.3 74.11 620.5 74.84 ; + RECT 620.48 0 620.74 13.45 ; + RECT 620.955 74.11 621.155 74.84 ; + RECT 621.5 0.155 622.27 0.445 ; + RECT 621.5 0.155 621.76 8.665 ; + RECT 622.01 0.155 622.27 8.665 ; + RECT 620.99 0 621.25 11.315 ; + RECT 621.365 74.11 621.725 74.84 ; + RECT 621.935 74.11 622.135 74.84 ; + RECT 622.52 0.52 622.78 9.955 ; + RECT 622.59 74.11 622.79 74.84 ; + RECT 623 74.11 623.36 74.84 ; + RECT 623.655 74.11 623.855 74.84 ; + RECT 624.15 74.11 624.51 74.84 ; + RECT 624.56 0.3 624.82 8.7 ; + RECT 624.72 74.11 624.92 74.84 ; + RECT 625.375 74.11 625.575 74.84 ; + RECT 625.07 0.18 625.84 0.88 ; + RECT 625.785 74.11 626.145 74.84 ; + RECT 626.355 74.11 626.555 74.84 ; + RECT 627.01 74.11 627.21 74.84 ; + RECT 627.265 0 627.525 6.28 ; + RECT 627.42 74.11 627.78 74.84 ; + RECT 628.075 74.11 628.275 74.84 ; + RECT 628.64 0 628.9 5.57 ; + RECT 628.57 74.11 628.93 74.84 ; + RECT 629.14 74.11 629.34 74.84 ; + RECT 629.15 0.3 629.41 5.235 ; + RECT 629.66 0.52 629.92 7.78 ; + RECT 629.795 74.11 629.995 74.84 ; + RECT 630.205 74.11 630.565 74.84 ; + RECT 630.51 0.52 630.77 4.315 ; + RECT 630.775 74.11 630.975 74.84 ; + RECT 631.43 74.11 631.63 74.84 ; + RECT 631.685 0 631.945 2.82 ; + RECT 631.84 74.11 632.2 74.84 ; + RECT 632.495 74.11 632.695 74.84 ; + RECT 632.99 74.11 633.35 74.84 ; + RECT 633.925 0.18 634.695 0.88 ; + RECT 633.925 0.18 634.185 12.9 ; + RECT 634.435 0.18 634.695 12.9 ; + RECT 633.215 0 633.475 2.82 ; + RECT 633.56 74.11 633.76 74.84 ; + RECT 634.945 0.155 635.715 0.445 ; + RECT 634.945 0.155 635.205 13.21 ; + RECT 635.455 0.155 635.715 13.21 ; + RECT 634.215 74.11 634.415 74.84 ; + RECT 634.625 74.11 634.985 74.84 ; + RECT 635.195 74.11 635.395 74.84 ; + RECT 635.85 74.11 636.05 74.84 ; + RECT 636.26 74.11 636.62 74.84 ; + RECT 636.915 74.11 637.115 74.84 ; + RECT 637.41 74.11 637.77 74.84 ; + RECT 637.65 0.52 637.91 14.115 ; + RECT 637.98 74.11 638.18 74.84 ; + RECT 638.16 0 638.42 13.45 ; + RECT 638.635 74.11 638.835 74.84 ; + RECT 639.18 0.155 639.95 0.445 ; + RECT 639.18 0.155 639.44 8.665 ; + RECT 639.69 0.155 639.95 8.665 ; + RECT 638.67 0 638.93 11.315 ; + RECT 639.045 74.11 639.405 74.84 ; + RECT 639.615 74.11 639.815 74.84 ; + RECT 640.2 0.52 640.46 9.955 ; + RECT 640.27 74.11 640.47 74.84 ; + RECT 640.68 74.11 641.04 74.84 ; + RECT 641.335 74.11 641.535 74.84 ; + RECT 641.83 74.11 642.19 74.84 ; + RECT 642.24 0.3 642.5 8.7 ; + RECT 642.4 74.11 642.6 74.84 ; + RECT 643.055 74.11 643.255 74.84 ; + RECT 642.75 0.18 643.52 0.88 ; + RECT 643.465 74.11 643.825 74.84 ; + RECT 644.035 74.11 644.235 74.84 ; + RECT 644.69 74.11 644.89 74.84 ; + RECT 644.945 0 645.205 6.28 ; + RECT 645.1 74.11 645.46 74.84 ; + RECT 645.755 74.11 645.955 74.84 ; + RECT 646.32 0 646.58 5.57 ; + RECT 646.25 74.11 646.61 74.84 ; + RECT 646.82 74.11 647.02 74.84 ; + RECT 646.83 0.3 647.09 5.235 ; + RECT 647.34 0.52 647.6 7.78 ; + RECT 647.475 74.11 647.675 74.84 ; + RECT 647.885 74.11 648.245 74.84 ; + RECT 648.19 0.52 648.45 4.315 ; + RECT 648.455 74.11 648.655 74.84 ; + RECT 649.11 74.11 649.31 74.84 ; + RECT 649.365 0 649.625 2.82 ; + RECT 649.52 74.11 649.88 74.84 ; + RECT 650.175 74.11 650.375 74.84 ; + RECT 650.67 74.11 651.03 74.84 ; + RECT 651.605 0.18 652.375 0.88 ; + RECT 651.605 0.18 651.865 12.9 ; + RECT 652.115 0.18 652.375 12.9 ; + RECT 650.895 0 651.155 2.82 ; + RECT 651.24 74.11 651.44 74.84 ; + RECT 652.625 0.155 653.395 0.445 ; + RECT 652.625 0.155 652.885 13.21 ; + RECT 653.135 0.155 653.395 13.21 ; + RECT 651.895 74.11 652.095 74.84 ; + RECT 652.305 74.11 652.665 74.84 ; + RECT 652.875 74.11 653.075 74.84 ; + RECT 653.53 74.11 653.73 74.84 ; + RECT 653.94 74.11 654.3 74.84 ; + RECT 654.595 74.11 654.795 74.84 ; + RECT 655.09 74.11 655.45 74.84 ; + RECT 655.33 0.52 655.59 14.115 ; + RECT 655.66 74.11 655.86 74.84 ; + RECT 655.84 0 656.1 13.45 ; + RECT 656.315 74.11 656.515 74.84 ; + RECT 656.86 0.155 657.63 0.445 ; + RECT 656.86 0.155 657.12 8.665 ; + RECT 657.37 0.155 657.63 8.665 ; + RECT 656.35 0 656.61 11.315 ; + RECT 656.725 74.11 657.085 74.84 ; + RECT 657.295 74.11 657.495 74.84 ; + RECT 657.88 0.52 658.14 9.955 ; + RECT 657.95 74.11 658.15 74.84 ; + RECT 658.36 74.11 658.72 74.84 ; + RECT 659.015 74.11 659.215 74.84 ; + RECT 659.51 74.11 659.87 74.84 ; + RECT 659.92 0.3 660.18 8.7 ; + RECT 660.08 74.11 660.28 74.84 ; + RECT 660.735 74.11 660.935 74.84 ; + RECT 660.43 0.18 661.2 0.88 ; + RECT 661.145 74.11 661.505 74.84 ; + RECT 661.715 74.11 661.915 74.84 ; + RECT 662.37 74.11 662.57 74.84 ; + RECT 662.625 0 662.885 6.28 ; + RECT 662.78 74.11 663.14 74.84 ; + RECT 663.435 74.11 663.635 74.84 ; + RECT 664 0 664.26 5.57 ; + RECT 663.93 74.11 664.29 74.84 ; + RECT 664.5 74.11 664.7 74.84 ; + RECT 664.51 0.3 664.77 5.235 ; + RECT 665.02 0.52 665.28 7.78 ; + RECT 665.155 74.11 665.355 74.84 ; + RECT 665.565 74.11 665.925 74.84 ; + RECT 665.87 0.52 666.13 4.315 ; + RECT 666.135 74.11 666.335 74.84 ; + RECT 666.79 74.11 666.99 74.84 ; + RECT 667.045 0 667.305 2.82 ; + RECT 667.2 74.11 667.56 74.84 ; + RECT 667.855 74.11 668.055 74.84 ; + RECT 668.35 74.11 668.71 74.84 ; + RECT 669.285 0.18 670.055 0.88 ; + RECT 669.285 0.18 669.545 12.9 ; + RECT 669.795 0.18 670.055 12.9 ; + RECT 668.575 0 668.835 2.82 ; + RECT 668.92 74.11 669.12 74.84 ; + RECT 670.305 0.155 671.075 0.445 ; + RECT 670.305 0.155 670.565 13.21 ; + RECT 670.815 0.155 671.075 13.21 ; + RECT 669.575 74.11 669.775 74.84 ; + RECT 669.985 74.11 670.345 74.84 ; + RECT 670.555 74.11 670.755 74.84 ; + RECT 671.21 74.11 671.41 74.84 ; + RECT 671.62 74.11 671.98 74.84 ; + RECT 672.275 74.11 672.475 74.84 ; + RECT 672.77 74.11 673.13 74.84 ; + RECT 673.01 0.52 673.27 14.115 ; + RECT 673.34 74.11 673.54 74.84 ; + RECT 673.52 0 673.78 13.45 ; + RECT 673.995 74.11 674.195 74.84 ; + RECT 674.54 0.155 675.31 0.445 ; + RECT 674.54 0.155 674.8 8.665 ; + RECT 675.05 0.155 675.31 8.665 ; + RECT 674.03 0 674.29 11.315 ; + RECT 674.405 74.11 674.765 74.84 ; + RECT 674.975 74.11 675.175 74.84 ; + RECT 675.56 0.52 675.82 9.955 ; + RECT 675.63 74.11 675.83 74.84 ; + RECT 676.04 74.11 676.4 74.84 ; + RECT 676.695 74.11 676.895 74.84 ; + RECT 677.19 74.11 677.55 74.84 ; + RECT 677.6 0.3 677.86 8.7 ; + RECT 677.76 74.11 677.96 74.84 ; + RECT 678.415 74.11 678.615 74.84 ; + RECT 678.11 0.18 678.88 0.88 ; + RECT 678.825 74.11 679.185 74.84 ; + RECT 679.395 74.11 679.595 74.84 ; + RECT 680.05 74.11 680.25 74.84 ; + RECT 680.305 0 680.565 6.28 ; + RECT 680.46 74.11 680.82 74.84 ; + RECT 681.115 74.11 681.315 74.84 ; + RECT 681.68 0 681.94 5.57 ; + RECT 681.61 74.11 681.97 74.84 ; + RECT 682.18 74.11 682.38 74.84 ; + RECT 682.19 0.3 682.45 5.235 ; + RECT 682.7 0.52 682.96 7.78 ; + RECT 682.835 74.11 683.035 74.84 ; + RECT 683.245 74.11 683.605 74.84 ; + RECT 683.55 0.52 683.81 4.315 ; + RECT 683.815 74.11 684.015 74.84 ; + RECT 684.47 74.11 684.67 74.84 ; + RECT 684.725 0 684.985 2.82 ; + RECT 684.88 74.11 685.24 74.84 ; + RECT 685.535 74.11 685.735 74.84 ; + RECT 686.03 74.11 686.39 74.84 ; + RECT 686.965 0.18 687.735 0.88 ; + RECT 686.965 0.18 687.225 12.9 ; + RECT 687.475 0.18 687.735 12.9 ; + RECT 686.255 0 686.515 2.82 ; + RECT 686.6 74.11 686.8 74.84 ; + RECT 687.985 0.155 688.755 0.445 ; + RECT 687.985 0.155 688.245 13.21 ; + RECT 688.495 0.155 688.755 13.21 ; + RECT 687.255 74.11 687.455 74.84 ; + RECT 687.665 74.11 688.025 74.84 ; + RECT 688.235 74.11 688.435 74.84 ; + RECT 688.89 74.11 689.09 74.84 ; + RECT 689.3 74.11 689.66 74.84 ; + RECT 689.955 74.11 690.155 74.84 ; + RECT 690.45 74.11 690.81 74.84 ; + RECT 690.69 0.52 690.95 14.115 ; + RECT 691.02 74.11 691.22 74.84 ; + RECT 691.2 0 691.46 13.45 ; + RECT 691.675 74.11 691.875 74.84 ; + RECT 692.22 0.155 692.99 0.445 ; + RECT 692.22 0.155 692.48 8.665 ; + RECT 692.73 0.155 692.99 8.665 ; + RECT 691.71 0 691.97 11.315 ; + RECT 692.085 74.11 692.445 74.84 ; + RECT 692.655 74.11 692.855 74.84 ; + RECT 693.24 0.52 693.5 9.955 ; + RECT 693.31 74.11 693.51 74.84 ; + RECT 693.72 74.11 694.08 74.84 ; + RECT 694.375 74.11 694.575 74.84 ; + RECT 694.87 74.11 695.23 74.84 ; + RECT 695.28 0.3 695.54 8.7 ; + RECT 695.44 74.11 695.64 74.84 ; + RECT 696.095 74.11 696.295 74.84 ; + RECT 695.79 0.18 696.56 0.88 ; + RECT 696.505 74.11 696.865 74.84 ; + RECT 697.075 74.11 697.275 74.84 ; + RECT 697.73 74.11 697.93 74.84 ; + RECT 697.985 0 698.245 6.28 ; + RECT 698.14 74.11 698.5 74.84 ; + RECT 698.795 74.11 698.995 74.84 ; + RECT 699.36 0 699.62 5.57 ; + RECT 699.29 74.11 699.65 74.84 ; + RECT 699.86 74.11 700.06 74.84 ; + RECT 699.87 0.3 700.13 5.235 ; + RECT 700.38 0.52 700.64 7.78 ; + RECT 700.515 74.11 700.715 74.84 ; + RECT 700.925 74.11 701.285 74.84 ; + RECT 701.495 74.11 701.695 74.84 ; + RECT 702.32 53.41 702.52 74.84 ; + LAYER Metal2 SPACING 0.21 ; + RECT 426 0 427.78 74.87 ; + RECT 443.68 0 445.46 74.87 ; + RECT 461.36 0 463.14 74.87 ; + RECT 479.04 0 480.82 74.87 ; + RECT 496.72 0 498.5 74.87 ; + RECT 514.4 0 516.18 74.87 ; + RECT 532.08 0 533.86 74.87 ; + RECT 549.76 0 551.54 74.87 ; + RECT 567.44 0 569.22 74.87 ; + RECT 585.12 0 586.9 74.87 ; + RECT 602.8 0 604.58 74.87 ; + RECT 620.48 0 622.26 74.87 ; + RECT 638.16 0 639.94 74.87 ; + RECT 655.84 0 657.62 74.87 ; + RECT 673.52 0 675.3 74.87 ; + RECT 691.2 0 692.98 74.87 ; + RECT 284.74 0 315.425 74.87 ; + RECT 327.425 0 332.765 74.87 ; + RECT 335.585 0 335.825 74.87 ; + RECT 356.795 0 365.715 74.87 ; + RECT 367.005 0 367.245 74.87 ; + RECT 370.065 0 375.405 74.87 ; + RECT 377.195 0 386.625 74.87 ; + RECT 428.56 0 434.92 74.87 ; + RECT 446.24 0 452.6 74.87 ; + RECT 463.92 0 470.28 74.87 ; + RECT 481.6 0 487.96 74.87 ; + RECT 499.28 0 505.64 74.87 ; + RECT 516.96 0 523.32 74.87 ; + RECT 534.64 0 541 74.87 ; + RECT 552.32 0 558.68 74.87 ; + RECT 570 0 576.36 74.87 ; + RECT 587.68 0 594.04 74.87 ; + RECT 605.36 0 611.72 74.87 ; + RECT 623.04 0 629.4 74.87 ; + RECT 640.72 0 647.08 74.87 ; + RECT 658.4 0 664.76 74.87 ; + RECT 676.08 0 682.44 74.87 ; + RECT 693.76 0 700.12 74.87 ; + RECT 0 0 1.93 74.87 ; + RECT 2.71 0 9.07 74.87 ; + RECT 2.7 0.3 9.07 74.87 ; + RECT 9.85 0 11.63 74.87 ; + RECT 9.84 0.155 11.63 74.87 ; + RECT 12.4 0 18.76 74.87 ; + RECT 20.39 0 26.75 74.87 ; + RECT 20.38 0.3 26.75 74.87 ; + RECT 27.53 0 29.31 74.87 ; + RECT 27.52 0.155 29.31 74.87 ; + RECT 30.08 0 36.44 74.87 ; + RECT 38.07 0 44.43 74.87 ; + RECT 38.06 0.3 44.43 74.87 ; + RECT 45.21 0 46.99 74.87 ; + RECT 45.2 0.155 46.99 74.87 ; + RECT 47.76 0 54.12 74.87 ; + RECT 55.75 0 62.11 74.87 ; + RECT 55.74 0.3 62.11 74.87 ; + RECT 62.89 0 64.67 74.87 ; + RECT 62.88 0.155 64.67 74.87 ; + RECT 65.44 0 71.8 74.87 ; + RECT 73.43 0 79.79 74.87 ; + RECT 73.42 0.3 79.79 74.87 ; + RECT 80.57 0 82.35 74.87 ; + RECT 80.56 0.155 82.35 74.87 ; + RECT 83.12 0 89.48 74.87 ; + RECT 91.11 0 97.47 74.87 ; + RECT 91.1 0.3 97.47 74.87 ; + RECT 98.25 0 100.03 74.87 ; + RECT 98.24 0.155 100.03 74.87 ; + RECT 100.8 0 107.16 74.87 ; + RECT 108.79 0 115.15 74.87 ; + RECT 108.78 0.3 115.15 74.87 ; + RECT 115.93 0 117.71 74.87 ; + RECT 115.92 0.155 117.71 74.87 ; + RECT 118.48 0 124.84 74.87 ; + RECT 126.47 0 132.83 74.87 ; + RECT 126.46 0.3 132.83 74.87 ; + RECT 133.61 0 135.39 74.87 ; + RECT 133.6 0.155 135.39 74.87 ; + RECT 136.16 0 142.52 74.87 ; + RECT 144.15 0 150.51 74.87 ; + RECT 144.14 0.3 150.51 74.87 ; + RECT 151.29 0 153.07 74.87 ; + RECT 151.28 0.155 153.07 74.87 ; + RECT 153.84 0 160.2 74.87 ; + RECT 161.83 0 168.19 74.87 ; + RECT 161.82 0.3 168.19 74.87 ; + RECT 168.97 0 170.75 74.87 ; + RECT 168.96 0.155 170.75 74.87 ; + RECT 171.52 0 177.88 74.87 ; + RECT 179.51 0 185.87 74.87 ; + RECT 179.5 0.3 185.87 74.87 ; + RECT 186.65 0 188.43 74.87 ; + RECT 186.64 0.155 188.43 74.87 ; + RECT 189.2 0 195.56 74.87 ; + RECT 197.19 0 203.55 74.87 ; + RECT 197.18 0.3 203.55 74.87 ; + RECT 204.33 0 206.11 74.87 ; + RECT 204.32 0.155 206.11 74.87 ; + RECT 206.88 0 213.24 74.87 ; + RECT 214.87 0 221.23 74.87 ; + RECT 214.86 0.3 221.23 74.87 ; + RECT 222.01 0 223.79 74.87 ; + RECT 222 0.155 223.79 74.87 ; + RECT 224.56 0 230.92 74.87 ; + RECT 232.55 0 238.91 74.87 ; + RECT 232.54 0.3 238.91 74.87 ; + RECT 239.69 0 241.47 74.87 ; + RECT 239.68 0.155 241.47 74.87 ; + RECT 242.24 0 248.6 74.87 ; + RECT 250.23 0 256.59 74.87 ; + RECT 250.22 0.3 256.59 74.87 ; + RECT 257.37 0 259.15 74.87 ; + RECT 257.36 0.155 259.15 74.87 ; + RECT 259.92 0 266.28 74.87 ; + RECT 267.91 0 274.27 74.87 ; + RECT 267.9 0.3 274.27 74.87 ; + RECT 275.05 0 276.83 74.87 ; + RECT 275.04 0.155 276.83 74.87 ; + RECT 277.6 0 283.96 74.87 ; + RECT 284.74 0.18 315.435 74.87 ; + RECT 316.205 0 325.635 74.87 ; + RECT 316.195 0.3 325.635 74.87 ; + RECT 326.395 0 326.655 74.87 ; + RECT 327.415 0.3 332.775 74.87 ; + RECT 334.045 0 334.305 74.87 ; + RECT 335.575 0.3 335.835 74.87 ; + RECT 337.115 0 346.035 74.87 ; + RECT 337.105 0.3 346.035 74.87 ; + RECT 346.795 0 347.055 74.87 ; + RECT 347.815 0 355.015 74.87 ; + RECT 355.775 0 356.035 74.87 ; + RECT 356.795 0.3 365.725 74.87 ; + RECT 366.995 0.3 367.255 74.87 ; + RECT 368.525 0 368.785 74.87 ; + RECT 370.055 0.3 375.415 74.87 ; + RECT 376.175 0 376.435 74.87 ; + RECT 377.195 0.3 386.635 74.87 ; + RECT 387.405 0 418.09 74.87 ; + RECT 387.395 0.18 418.09 74.87 ; + RECT 418.87 0 425.23 74.87 ; + RECT 426 0.155 427.79 74.87 ; + RECT 428.56 0.3 434.93 74.87 ; + RECT 436.55 0 442.91 74.87 ; + RECT 443.68 0.155 445.47 74.87 ; + RECT 446.24 0.3 452.61 74.87 ; + RECT 454.23 0 460.59 74.87 ; + RECT 461.36 0.155 463.15 74.87 ; + RECT 463.92 0.3 470.29 74.87 ; + RECT 471.91 0 478.27 74.87 ; + RECT 479.04 0.155 480.83 74.87 ; + RECT 481.6 0.3 487.97 74.87 ; + RECT 489.59 0 495.95 74.87 ; + RECT 496.72 0.155 498.51 74.87 ; + RECT 499.28 0.3 505.65 74.87 ; + RECT 507.27 0 513.63 74.87 ; + RECT 514.4 0.155 516.19 74.87 ; + RECT 516.96 0.3 523.33 74.87 ; + RECT 524.95 0 531.31 74.87 ; + RECT 532.08 0.155 533.87 74.87 ; + RECT 534.64 0.3 541.01 74.87 ; + RECT 542.63 0 548.99 74.87 ; + RECT 549.76 0.155 551.55 74.87 ; + RECT 552.32 0.3 558.69 74.87 ; + RECT 560.31 0 566.67 74.87 ; + RECT 567.44 0.155 569.23 74.87 ; + RECT 570 0.3 576.37 74.87 ; + RECT 577.99 0 584.35 74.87 ; + RECT 585.12 0.155 586.91 74.87 ; + RECT 587.68 0.3 594.05 74.87 ; + RECT 595.67 0 602.03 74.87 ; + RECT 602.8 0.155 604.59 74.87 ; + RECT 605.36 0.3 611.73 74.87 ; + RECT 613.35 0 619.71 74.87 ; + RECT 620.48 0.155 622.27 74.87 ; + RECT 623.04 0.3 629.41 74.87 ; + RECT 631.03 0 637.39 74.87 ; + RECT 638.16 0.155 639.95 74.87 ; + RECT 640.72 0.3 647.09 74.87 ; + RECT 648.71 0 655.07 74.87 ; + RECT 655.84 0.155 657.63 74.87 ; + RECT 658.4 0.3 664.77 74.87 ; + RECT 666.39 0 672.75 74.87 ; + RECT 673.52 0.155 675.31 74.87 ; + RECT 676.08 0.3 682.45 74.87 ; + RECT 684.07 0 690.43 74.87 ; + RECT 691.2 0.155 692.99 74.87 ; + RECT 693.76 0.3 700.13 74.87 ; + RECT 700.9 0 702.83 74.87 ; + RECT 0 0.52 702.83 74.87 ; + LAYER Metal3 ; + RECT 0 0 702.83 74.87 ; + LAYER Metal4 SPACING 0.21 ; + RECT 0 47.305 14.725 53.15 ; + RECT 0 0 5.885 74.87 ; + RECT 10.825 0 14.725 74.87 ; + RECT 19.665 47.305 32.405 53.15 ; + RECT 19.665 0 23.565 74.87 ; + RECT 28.505 0 32.405 74.87 ; + RECT 37.345 47.305 50.085 53.15 ; + RECT 37.345 0 41.245 74.87 ; + RECT 46.185 0 50.085 74.87 ; + RECT 55.025 47.305 67.765 53.15 ; + RECT 55.025 0 58.925 74.87 ; + RECT 63.865 0 67.765 74.87 ; + RECT 72.705 47.305 85.445 53.15 ; + RECT 72.705 0 76.605 74.87 ; + RECT 81.545 0 85.445 74.87 ; + RECT 90.385 47.305 103.125 53.15 ; + RECT 90.385 0 94.285 74.87 ; + RECT 99.225 0 103.125 74.87 ; + RECT 108.065 47.305 120.805 53.15 ; + RECT 108.065 0 111.965 74.87 ; + RECT 116.905 0 120.805 74.87 ; + RECT 125.745 47.305 138.485 53.15 ; + RECT 125.745 0 129.645 74.87 ; + RECT 134.585 0 138.485 74.87 ; + RECT 143.425 47.305 156.165 53.15 ; + RECT 143.425 0 147.325 74.87 ; + RECT 152.265 0 156.165 74.87 ; + RECT 161.105 47.305 173.845 53.15 ; + RECT 161.105 0 165.005 74.87 ; + RECT 169.945 0 173.845 74.87 ; + RECT 178.785 47.305 191.525 53.15 ; + RECT 178.785 0 182.685 74.87 ; + RECT 187.625 0 191.525 74.87 ; + RECT 196.465 47.305 209.205 53.15 ; + RECT 196.465 0 200.365 74.87 ; + RECT 205.305 0 209.205 74.87 ; + RECT 214.145 47.305 226.885 53.15 ; + RECT 214.145 0 218.045 74.87 ; + RECT 222.985 0 226.885 74.87 ; + RECT 231.825 47.305 244.565 53.15 ; + RECT 231.825 0 235.725 74.87 ; + RECT 240.665 0 244.565 74.87 ; + RECT 249.505 47.305 262.245 53.15 ; + RECT 249.505 0 253.405 74.87 ; + RECT 258.345 0 262.245 74.87 ; + RECT 267.185 47.305 279.925 53.15 ; + RECT 267.185 0 271.085 74.87 ; + RECT 276.025 0 279.925 74.87 ; + RECT 284.865 0 311.125 74.87 ; + RECT 314.455 0 316.275 74.87 ; + RECT 319.605 0 321.425 74.87 ; + RECT 324.755 0 326.575 74.87 ; + RECT 329.905 0 331.725 74.87 ; + RECT 335.055 0 336.875 74.87 ; + RECT 340.205 0 342.025 74.87 ; + RECT 345.355 0 347.175 74.87 ; + RECT 350.505 0 352.325 74.87 ; + RECT 355.655 0 357.475 74.87 ; + RECT 360.805 0 362.625 74.87 ; + RECT 365.955 0 367.775 74.87 ; + RECT 371.105 0 372.925 74.87 ; + RECT 376.255 0 378.075 74.87 ; + RECT 422.905 47.305 435.645 53.15 ; + RECT 422.905 0 426.805 74.87 ; + RECT 431.745 0 435.645 74.87 ; + RECT 440.585 47.305 453.325 53.15 ; + RECT 440.585 0 444.485 74.87 ; + RECT 449.425 0 453.325 74.87 ; + RECT 458.265 47.305 471.005 53.15 ; + RECT 458.265 0 462.165 74.87 ; + RECT 467.105 0 471.005 74.87 ; + RECT 475.945 47.305 488.685 53.15 ; + RECT 475.945 0 479.845 74.87 ; + RECT 484.785 0 488.685 74.87 ; + RECT 493.625 47.305 506.365 53.15 ; + RECT 493.625 0 497.525 74.87 ; + RECT 502.465 0 506.365 74.87 ; + RECT 511.305 47.305 524.045 53.15 ; + RECT 511.305 0 515.205 74.87 ; + RECT 520.145 0 524.045 74.87 ; + RECT 528.985 47.305 541.725 53.15 ; + RECT 528.985 0 532.885 74.87 ; + RECT 537.825 0 541.725 74.87 ; + RECT 546.665 47.305 559.405 53.15 ; + RECT 546.665 0 550.565 74.87 ; + RECT 555.505 0 559.405 74.87 ; + RECT 564.345 47.305 577.085 53.15 ; + RECT 564.345 0 568.245 74.87 ; + RECT 573.185 0 577.085 74.87 ; + RECT 582.025 47.305 594.765 53.15 ; + RECT 582.025 0 585.925 74.87 ; + RECT 590.865 0 594.765 74.87 ; + RECT 599.705 47.305 612.445 53.15 ; + RECT 599.705 0 603.605 74.87 ; + RECT 608.545 0 612.445 74.87 ; + RECT 617.385 47.305 630.125 53.15 ; + RECT 617.385 0 621.285 74.87 ; + RECT 626.225 0 630.125 74.87 ; + RECT 635.065 47.305 647.805 53.15 ; + RECT 635.065 0 638.965 74.87 ; + RECT 643.905 0 647.805 74.87 ; + RECT 652.745 47.305 665.485 53.15 ; + RECT 652.745 0 656.645 74.87 ; + RECT 661.585 0 665.485 74.87 ; + RECT 670.425 47.305 683.165 53.15 ; + RECT 670.425 0 674.325 74.87 ; + RECT 679.265 0 683.165 74.87 ; + RECT 688.105 47.305 702.83 53.15 ; + RECT 688.105 0 692.005 74.87 ; + RECT 696.945 0 702.83 74.87 ; + RECT 381.405 0 383.225 74.87 ; + RECT 386.555 0 388.375 74.87 ; + RECT 391.705 0 417.965 74.87 ; + END +END RM_IHPSG13_2P_64x32_c2 + +END LIBRARY diff --git a/flow/platforms/ihp-sg13g2/lef/sg13g2_io.lef b/flow/platforms/ihp-sg13g2/lef/sg13g2_io.lef index 7ce62d50f9..be2dd21340 100644 --- a/flow/platforms/ihp-sg13g2/lef/sg13g2_io.lef +++ b/flow/platforms/ihp-sg13g2/lef/sg13g2_io.lef @@ -27,13 +27,19 @@ SITE sg13g2_ioSite SIZE 1.00 BY 180.00 ; END sg13g2_ioSite +SITE sg13g2_cornerSite + CLASS PAD ; + SYMMETRY R90 ; + SIZE 180.00 BY 180.00 ; +END sg13g2_cornerSite + MACRO sg13g2_Corner CLASS PAD SPACER ; ORIGIN 0.000 0.000 ; FOREIGN sg13g2_Corner 0.000 0.000 ; SIZE 180.000 BY 180.000 ; SYMMETRY X Y R90 ; - SITE sg13g2_ioSite ; + SITE sg13g2_cornerSite ; PIN iovdd DIRECTION INOUT ; USE POWER ; @@ -497,13 +503,13 @@ MACRO sg13g2_Filler200 LAYER Metal2 ; RECT 0.000 0.000 1.000 180.000 ; LAYER Metal3 ; - RECT 0.000 0.000 80.000 178.000 ; + RECT 0.000 0.000 1.000 178.000 ; LAYER Metal4 ; - RECT 0.000 0.000 80.000 178.000 ; + RECT 0.000 0.000 1.000 178.000 ; LAYER Metal5 ; - RECT 0.000 0.000 80.000 178.000 ; + RECT 0.000 0.000 1.000 178.000 ; LAYER TopMetal1 ; - RECT 0.000 0.000 80.000 178.000 ; + RECT 0.000 0.000 1.000 178.000 ; LAYER TopMetal2 ; RECT 0.000 8.500 1.000 132.500 ; LAYER Via1 ; @@ -674,13 +680,13 @@ MACRO sg13g2_Filler400 LAYER Metal2 ; RECT 0.000 0.000 2.000 180.000 ; LAYER Metal3 ; - RECT 0.000 0.000 80.000 178.000 ; + RECT 0.000 0.000 2.000 178.000 ; LAYER Metal4 ; - RECT 0.000 0.000 80.000 178.000 ; + RECT 0.000 0.000 2.000 178.000 ; LAYER Metal5 ; - RECT 0.000 0.000 80.000 178.000 ; + RECT 0.000 0.000 2.000 178.000 ; LAYER TopMetal1 ; - RECT 0.000 0.000 80.000 178.000 ; + RECT 0.000 0.000 2.000 178.000 ; LAYER TopMetal2 ; RECT 0.000 8.500 2.000 132.500 ; LAYER Via1 ; @@ -851,13 +857,13 @@ MACRO sg13g2_Filler1000 LAYER Metal2 ; RECT 0.000 0.000 5.000 180.000 ; LAYER Metal3 ; - RECT 0.000 0.000 80.000 178.000 ; + RECT 0.000 0.000 5.000 178.000 ; LAYER Metal4 ; - RECT 0.000 0.000 80.000 178.000 ; + RECT 0.000 0.000 5.000 178.000 ; LAYER Metal5 ; - RECT 0.000 0.000 80.000 178.000 ; + RECT 0.000 0.000 5.000 178.000 ; LAYER TopMetal1 ; - RECT 0.000 0.000 80.000 178.000 ; + RECT 0.000 0.000 5.000 178.000 ; LAYER TopMetal2 ; RECT 0.000 8.500 5.000 132.500 ; LAYER Via1 ; @@ -1028,13 +1034,13 @@ MACRO sg13g2_Filler2000 LAYER Metal2 ; RECT 0.000 0.000 10.000 180.000 ; LAYER Metal3 ; - RECT 0.000 0.000 80.000 178.000 ; + RECT 0.000 0.000 10.000 178.000 ; LAYER Metal4 ; - RECT 0.000 0.000 80.000 178.000 ; + RECT 0.000 0.000 10.000 178.000 ; LAYER Metal5 ; - RECT 0.000 0.000 80.000 178.000 ; + RECT 0.000 0.000 10.000 178.000 ; LAYER TopMetal1 ; - RECT 0.000 0.000 80.000 178.000 ; + RECT 0.000 0.000 10.000 178.000 ; LAYER TopMetal2 ; RECT 0.000 8.500 10.000 132.500 ; LAYER Via1 ; @@ -1205,13 +1211,13 @@ MACRO sg13g2_Filler4000 LAYER Metal2 ; RECT 0.000 0.000 20.000 180.000 ; LAYER Metal3 ; - RECT 0.000 0.000 80.000 178.000 ; + RECT 0.000 0.000 20.000 178.000 ; LAYER Metal4 ; - RECT 0.000 0.000 80.000 178.000 ; + RECT 0.000 0.000 20.000 178.000 ; LAYER Metal5 ; - RECT 0.000 0.000 80.000 178.000 ; + RECT 0.000 0.000 20.000 178.000 ; LAYER TopMetal1 ; - RECT 0.000 0.000 80.000 178.000 ; + RECT 0.000 0.000 20.000 178.000 ; LAYER TopMetal2 ; RECT 0.000 8.500 20.000 132.500 ; LAYER Via1 ; @@ -1382,13 +1388,13 @@ MACRO sg13g2_Filler10000 LAYER Metal2 ; RECT 0.000 0.000 50.000 180.000 ; LAYER Metal3 ; - RECT 0.000 0.000 80.000 178.000 ; + RECT 0.000 0.000 50.000 178.000 ; LAYER Metal4 ; - RECT 0.000 0.000 80.000 178.000 ; + RECT 0.000 0.000 50.000 178.000 ; LAYER Metal5 ; - RECT 0.000 0.000 80.000 178.000 ; + RECT 0.000 0.000 50.000 178.000 ; LAYER TopMetal1 ; - RECT 0.000 0.000 80.000 178.000 ; + RECT 0.000 0.000 50.000 178.000 ; LAYER TopMetal2 ; RECT 0.000 8.500 50.000 132.500 ; LAYER Via1 ; diff --git a/flow/platforms/ihp-sg13g2/lef/sg13g2_stdcell.lef b/flow/platforms/ihp-sg13g2/lef/sg13g2_stdcell.lef index 4dd096a420..bbb2db627d 100644 --- a/flow/platforms/ihp-sg13g2/lef/sg13g2_stdcell.lef +++ b/flow/platforms/ihp-sg13g2/lef/sg13g2_stdcell.lef @@ -17,7 +17,7 @@ ######################################################################## VERSION 5.7 ; -BUSBITCHARS "<>" ; +BUSBITCHARS "[]" ; DIVIDERCHAR "/" ; PROPERTYDEFINITIONS diff --git a/flow/platforms/ihp-sg13g2/lef/sg13g2_tech.lef b/flow/platforms/ihp-sg13g2/lef/sg13g2_tech.lef index ed737fa20f..35d6474566 100644 --- a/flow/platforms/ihp-sg13g2/lef/sg13g2_tech.lef +++ b/flow/platforms/ihp-sg13g2/lef/sg13g2_tech.lef @@ -133,7 +133,6 @@ LAYER Metal2 THICKNESS 0.450 ; ANTENNACUMAREARATIO 200 ; ANTENNACUMDIFFAREARATIO PWL ( ( 0 200 ) ( 0.159 200 ) ( 0.16 3200 ) ( 100 2000000 ) ) ; - WIREEXTENSION 0.10 ; RESISTANCE RPERSQ 0.103 ; CAPACITANCE CPERSQDIST 1.81E-05 ; EDGECAPACITANCE 4.47E-05 ; @@ -279,7 +278,7 @@ END TopVia1 LAYER TopMetal1 TYPE ROUTING ; DIRECTION VERTICAL ; - PITCH 2.28 ; + PITCH 3.28 ; OFFSET 1.64 ; WIDTH 1.64 ; MINIMUMDENSITY 25.0 ; @@ -321,6 +320,10 @@ LAYER TopMetal2 DENSITYCHECKSTEP 100 ; DENSITYCHECKWINDOW 200 200 ; SPACING 2 ; + SPACINGTABLE + PARALLELRUNLENGTH 0.00 50.00 + WIDTH 0.00 2.0 2.0 + WIDTH 5.00 2.0 5.0 ; HEIGHT 11.160 ; # CURRENTDEN 0 ; THICKNESS 3.0 ; @@ -425,7 +428,7 @@ Via Via1_s DEFAULT RECT -0.19 -0.19 0.19 0.19 ; END Via1_s -####### Definitions of Via1 duoble cut ######## +####### Definitions of Via1 double cut ######## Via Via1_DC1B DEFAULT RESISTANCE 20.0 ; @@ -616,7 +619,7 @@ Via Via2_s DEFAULT RECT -0.19 -0.19 0.19 0.19 ; END Via2_s -####### Definitions of Via2 duoble cut ############## +####### Definitions of Via2 double cut ############## Via Via2_DC1B DEFAULT RESISTANCE 20.0 ; @@ -807,7 +810,7 @@ Via Via3_s DEFAULT RECT -0.19 -0.19 0.19 0.19 ; END Via3_s -####### Definitions of Via3 duoble cut ############## +####### Definitions of Via3 double cut ############## Via Via3_DC1B DEFAULT RESISTANCE 20.0 ; @@ -998,7 +1001,7 @@ Via Via4_s DEFAULT RECT -0.19 -0.19 0.19 0.19 ; END Via4_s -####### Definitions of Via4 duoble cut ############## +####### Definitions of Via4 double cut ############## Via Via4_DC1B DEFAULT RESISTANCE 20.0 ; @@ -1172,26 +1175,26 @@ ViaRULE via4Array GENERATE RESISTANCE 20.0 ; END via4Array ########################################### -ViaRULE viagen56 GENERATE +ViaRULE viaTop1Array GENERATE LAYER Metal5 ; - ENCLOSURE 0 0 ; + ENCLOSURE 0.1 0.1 ; LAYER TopMetal1 ; - ENCLOSURE 0.61 0.61 ; + ENCLOSURE 0.42 0.42 ; LAYER TopVia1 ; RECT -0.21 -0.21 0.21 0.21 ; SPACING 0.84 BY 0.84 ; RESISTANCE 4.0 ; -END viagen56 +END viaTop1Array -ViaRULE viagen67 GENERATE +ViaRULE viaTop2Array GENERATE LAYER TopMetal1 ; ENCLOSURE 0.5 0.5 ; LAYER TopMetal2 ; - ENCLOSURE 0.55 0.55 ; + ENCLOSURE 0.5 0.5 ; LAYER TopVia2 ; RECT -0.45 -0.45 0.45 0.45 ; SPACING 1.96 BY 1.96 ; RESISTANCE 2.2 ; -END viagen67 +END viaTop2Array END LIBRARY diff --git a/flow/platforms/ihp-sg13g2/lib/RM_IHPSG13_1P_1024x16_c2_bm_bist_fast_1p32V_m55C.lib b/flow/platforms/ihp-sg13g2/lib/RM_IHPSG13_1P_1024x16_c2_bm_bist_fast_1p32V_m55C.lib index dbe648f098..c4f42f0e24 100644 --- a/flow/platforms/ihp-sg13g2/lib/RM_IHPSG13_1P_1024x16_c2_bm_bist_fast_1p32V_m55C.lib +++ b/flow/platforms/ihp-sg13g2/lib/RM_IHPSG13_1P_1024x16_c2_bm_bist_fast_1p32V_m55C.lib @@ -1466,7 +1466,7 @@ bus(A_DOUT) { bus_type : D_15_0; direction : output ; capacitance : 0 ; - max_capacitance : "6.4e-14" ; + max_capacitance : 0.064 ; memory_read() { address : A_ADDR ; } diff --git a/flow/platforms/ihp-sg13g2/lib/RM_IHPSG13_1P_1024x16_c2_bm_bist_slow_1p08V_125C.lib b/flow/platforms/ihp-sg13g2/lib/RM_IHPSG13_1P_1024x16_c2_bm_bist_slow_1p08V_125C.lib index 7f909869ac..4e6692f593 100644 --- a/flow/platforms/ihp-sg13g2/lib/RM_IHPSG13_1P_1024x16_c2_bm_bist_slow_1p08V_125C.lib +++ b/flow/platforms/ihp-sg13g2/lib/RM_IHPSG13_1P_1024x16_c2_bm_bist_slow_1p08V_125C.lib @@ -1466,7 +1466,7 @@ bus(A_DOUT) { bus_type : D_15_0; direction : output ; capacitance : 0 ; - max_capacitance : "6.4e-14" ; + max_capacitance : 0.064 ; memory_read() { address : A_ADDR ; } diff --git a/flow/platforms/ihp-sg13g2/lib/RM_IHPSG13_1P_1024x16_c2_bm_bist_typ_1p20V_25C.lib b/flow/platforms/ihp-sg13g2/lib/RM_IHPSG13_1P_1024x16_c2_bm_bist_typ_1p20V_25C.lib index 258eea0af1..67d55bd26e 100644 --- a/flow/platforms/ihp-sg13g2/lib/RM_IHPSG13_1P_1024x16_c2_bm_bist_typ_1p20V_25C.lib +++ b/flow/platforms/ihp-sg13g2/lib/RM_IHPSG13_1P_1024x16_c2_bm_bist_typ_1p20V_25C.lib @@ -1466,7 +1466,7 @@ bus(A_DOUT) { bus_type : D_15_0; direction : output ; capacitance : 0 ; - max_capacitance : "6.4e-14" ; + max_capacitance : 0.064 ; memory_read() { address : A_ADDR ; } diff --git a/flow/platforms/ihp-sg13g2/lib/RM_IHPSG13_1P_1024x32_c2_bm_bist_fast_1p32V_m55C.lib b/flow/platforms/ihp-sg13g2/lib/RM_IHPSG13_1P_1024x32_c2_bm_bist_fast_1p32V_m55C.lib new file mode 100644 index 0000000000..e790240733 --- /dev/null +++ b/flow/platforms/ihp-sg13g2/lib/RM_IHPSG13_1P_1024x32_c2_bm_bist_fast_1p32V_m55C.lib @@ -0,0 +1,1525 @@ +/* ------------------------------------------------------*/ +/**/ +/* Copyright 2025 IHP PDK Authors*/ +/**/ +/* Licensed under the Apache License, Version 2.0 (the "License");*/ +/* you may not use this file except in compliance with the License.*/ +/* You may obtain a copy of the License at*/ +/* */ +/* https://www.apache.org/licenses/LICENSE-2.0*/ +/* */ +/* Unless required by applicable law or agreed to in writing, software*/ +/* distributed under the License is distributed on an "AS IS" BASIS,*/ +/* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.*/ +/* See the License for the specific language governing permissions and*/ +/* limitations under the License.*/ +/* */ +/* Generated on Thu Aug 21 20:48:24 2025 */ +/* */ +/* ------------------------------------------------------ */ +library(RM_IHPSG13_1P_1024x32_c2_bm_bist_fast_1p32V_m55C) { + technology (cmos) ; + delay_model : table_lookup ; + define ("add_pg_pin_to_lib", "library", "boolean"); + add_pg_pin_to_lib : true; + voltage_map ( VDD, 1.32); + voltage_map ( VDDARRAY, 1.32); + voltage_map ( VSS, 0.000000 ); + + date : "Thu Aug 21 20:48:22 2025" ; + comment : "IHP Microelectronics GmbH, 2023" ; + revision : 1.0.0 ; + simulation : true ; + nom_process : 1 ; + nom_temperature : -55 ; + nom_voltage : 1.32 ; + + operating_conditions("fast_1p32V_m55C"){ + process : 1 ; + temperature : -55 ; + voltage : 1.32 ; + tree_type : "balanced_tree" ; + } + + default_operating_conditions : fast_1p32V_m55C ; + default_max_transition : 1.0 ; + default_fanout_load : 1.0 ; + default_inout_pin_cap : 0.0 ; + default_input_pin_cap : 0.0 ; + default_output_pin_cap : 0.0 ; + default_cell_leakage_power : 0.0 ; + default_leakage_power_density : 0.0 ; + + slew_lower_threshold_pct_rise : 30 ; + slew_upper_threshold_pct_rise : 70 ; + input_threshold_pct_fall : 50 ; + output_threshold_pct_fall : 50 ; + input_threshold_pct_rise : 50 ; + output_threshold_pct_rise : 50 ; + slew_lower_threshold_pct_fall : 30 ; + slew_upper_threshold_pct_fall : 70 ; + slew_derate_from_library : 0.5; + k_volt_cell_leakage_power : 0.0 ; + k_temp_cell_leakage_power : 0.0 ; + k_process_cell_leakage_power : 0.0 ; + k_volt_internal_power : 0.0 ; + k_temp_internal_power : 0.0 ; + k_process_internal_power : 0.0 ; + + capacitive_load_unit (1,pf) ; + voltage_unit : "1V" ; + current_unit : "1uA" ; + time_unit : "1ns" ; + leakage_power_unit : "1nW" ; + pulling_resistance_unit : "1kohm"; + /* + ------------------------------------------------------------------------------------------ + implicit units overview: + cell_area unit : "um" + internal_power unit : "1e-12 * J/toggle = 1 * uW/MHz" + (capacitive_load_unit * voltage_unit^2) per toggle event + ------------------------------------------------------------------------------------------ + */ + library_features(report_delay_calculation); + define_cell_area (pad_drivers,pad_driver_sites) ; + + lu_table_template(CLKTRAN_constraint_template) { + variable_1 : constrained_pin_transition; + index_1 ( "0.010, 0.050, 0.200, 0.400, 1.000" ); + } + lu_table_template(SRAM_load_template) { + variable_1 : total_output_net_capacitance; + index_1 ( "0.0008,0.0014,0.0051,0.0100,0.0339,0.0640" ); + } + lu_table_template(SIG2SRAM_constraint_template) { + variable_1 : related_pin_transition; + variable_2 : constrained_pin_transition; + index_1 ( "0.0040,0.0176,0.0344,0.0656,0.1120,0.2016,0.3800" ); + index_2 ( "0.0040,0.0176,0.0344,0.0656,0.1120,0.2016,0.3800" ); + } + + lu_table_template(SIG2SRAM_delay_template) { + variable_1 : input_net_transition; + variable_2 : total_output_net_capacitance; + index_1 ( "0.0040,0.0176,0.0344,0.0656,0.1120,0.2016,0.3800" ); + index_2 ( "0.0008,0.0014,0.0051,0.0100,0.0339,0.0640" ); + } + + type (D_31_0) { + base_type : array; + data_type : bit; + bit_width : 32; + bit_from : 31; + bit_to : 0; + downto : true; + } + + type (A_9_0) { + base_type : array; + data_type : bit; + bit_width : 10; + bit_from : 9; + bit_to : 0; + downto : true; + } + +cell(RM_IHPSG13_1P_1024x32_c2_bm_bist) { +pg_pin (VDD) { + pg_type : primary_power; + voltage_name : VDD; +} +pg_pin (VDDARRAY) { + pg_type : primary_power; + voltage_name : VDDARRAY; +} +pg_pin (VSS) { + pg_type : primary_ground; + voltage_name : VSS; +} + +memory() { + type : ram; + address_width : 10; + word_width : 32; +} + +interface_timing : false; +bus_naming_style : "%s[%d]" ; +area : 140182.6944 ; + + pin(A_DLY) { + direction : input ; + capacitance : 0.00421562 ; + max_transition : "1" ; + related_power_pin : VDD; + related_ground_pin : VSS; + internal_power() { + rise_power("scalar") { + values (0); + } + fall_power("scalar") { + values (0); + } + } + } + +bus(A_ADDR) { + bus_type : A_9_0; + direction : input ; + capacitance : 0.00691085 ; + pin(A_ADDR[0]) { + capacitance : 0.00562034 ; + } + pin(A_ADDR[1]) { + capacitance : 0.00462655 ; + } + pin(A_ADDR[2]) { + capacitance : 0.00594295 ; + } + pin(A_ADDR[3]) { + capacitance : 0.00723434 ; + } + pin(A_ADDR[4]) { + capacitance : 0.00481603 ; + } + pin(A_ADDR[5]) { + capacitance : 0.00868123 ; + } + pin(A_ADDR[6]) { + capacitance : 0.010187 ; + } + pin(A_ADDR[7]) { + capacitance : 0.00734489 ; + } + pin(A_ADDR[8]) { + capacitance : 0.00904175 ; + } + max_transition : "0.38" ; + pin(A_ADDR[9:0]) { + related_power_pin : VDD; + related_ground_pin : VSS; + internal_power() { + when : "A_MEN"; + rise_power("scalar"){ + values (0.4735); + } + fall_power("scalar"){ + values (0.6259); + } + } + internal_power() { + when : "!A_MEN"; + rise_power("scalar"){ + values (0.0322); + } + fall_power("scalar"){ + values (0.0023); + } + } + } + timing() { + timing_type : setup_rising; + related_pin : "A_CLK"; + when : "((A_WEN | A_REN)& A_MEN)" + sdf_cond : "A_RW_ACCESS" + + rise_constraint("SIG2SRAM_constraint_template") { + index_1("0.0040,0.0176,0.0344,0.0656,0.1120,0.2016,0.3800"); + index_2("0.0040,0.0176,0.0344,0.0656,0.1120,0.2016,0.3800"); + values ("-0.2371,-0.2215,-0.2098,-0.1824,-0.1434,-0.0691,0.0676",\ +"-0.2449,-0.2332,-0.2176,-0.1902,-0.1551,-0.0770,0.0559",\ +"-0.2605,-0.2488,-0.2332,-0.2059,-0.1707,-0.0965,0.0441",\ +"-0.2879,-0.2723,-0.2605,-0.2332,-0.1941,-0.1199,0.0168",\ +"-0.3230,-0.3113,-0.2996,-0.2723,-0.2332,-0.1590,-0.0184",\ +"-0.4012,-0.3895,-0.3738,-0.3465,-0.3074,-0.2332,-0.0965",\ +"-0.5379,-0.5262,-0.5105,-0.4832,-0.4480,-0.3699,-0.2332"); + } + + fall_constraint("SIG2SRAM_constraint_template") { + index_1("0.0040,0.0176,0.0344,0.0656,0.1120,0.2016,0.3800"); + index_2("0.0040,0.0176,0.0344,0.0656,0.1120,0.2016,0.3800"); + values ("-0.1785,-0.1707,-0.1551,-0.1277,-0.0887,-0.0184,0.1145",\ +"-0.1902,-0.1785,-0.1629,-0.1355,-0.1004,-0.0262,0.1027",\ +"-0.2059,-0.1941,-0.1785,-0.1512,-0.1160,-0.0418,0.0871",\ +"-0.2293,-0.2176,-0.2059,-0.1785,-0.1434,-0.0691,0.0598",\ +"-0.2684,-0.2566,-0.2449,-0.2176,-0.1824,-0.1082,0.0207",\ +"-0.3465,-0.3348,-0.3191,-0.2918,-0.2566,-0.1824,-0.0535",\ +"-0.4832,-0.4715,-0.4559,-0.4324,-0.3934,-0.3191,-0.1902"); + } + } + + + timing() { + timing_type : hold_rising; + related_pin : "A_CLK"; + when : "((A_WEN | A_REN)& A_MEN)" + sdf_cond : "A_RW_ACCESS" + + rise_constraint("SIG2SRAM_constraint_template") { + index_1("0.0040,0.0176,0.0344,0.0656,0.1120,0.2016,0.3800"); + index_2("0.0040,0.0176,0.0344,0.0656,0.1120,0.2016,0.3800"); + values ("0.3410,0.3293,0.3137,0.2863,0.2473,0.1730,0.0324",\ +"0.3488,0.3371,0.3215,0.2941,0.2590,0.1809,0.0480",\ +"0.3684,0.3527,0.3371,0.3098,0.2746,0.1965,0.0598",\ +"0.3918,0.3762,0.3645,0.3371,0.2980,0.2238,0.0871",\ +"0.4309,0.4152,0.4035,0.3762,0.3371,0.2629,0.1223",\ +"0.5051,0.4934,0.4777,0.4504,0.4113,0.3371,0.1965",\ +"0.6418,0.6262,0.6145,0.5871,0.5520,0.4738,0.3332"); + } + + fall_constraint("SIG2SRAM_constraint_template") { + index_1("0.0040,0.0176,0.0344,0.0656,0.1120,0.2016,0.3800"); + index_2("0.0040,0.0176,0.0344,0.0656,0.1120,0.2016,0.3800"); + values ("0.2824,0.2707,0.2551,0.2277,0.1926,0.1184,-0.0105",\ +"0.2902,0.2785,0.2668,0.2395,0.2043,0.1301,0.0012",\ +"0.3059,0.2941,0.2824,0.2551,0.2199,0.1457,0.0168",\ +"0.3332,0.3215,0.3059,0.2785,0.2434,0.1691,0.0402",\ +"0.3723,0.3605,0.3449,0.3176,0.2824,0.2121,0.0793",\ +"0.4465,0.4348,0.4230,0.3918,0.3566,0.2824,0.1535",\ +"0.5832,0.5715,0.5598,0.5324,0.4934,0.4191,0.2902"); + } + } +} +pin(A_WEN) { + direction : input ; + capacitance : 0.00341384 ; + max_transition : "0.38" ; + related_power_pin : VDD; + related_ground_pin : VSS; + internal_power() { + when : "A_MEN"; + rise_power("scalar"){ + values (0.9384); + } + fall_power("scalar"){ + values (0.0212); + } + } + internal_power() { + when : "!A_MEN"; + rise_power("scalar"){ + values (0.0069); + } + fall_power("scalar"){ + values (0.0124); + } + } + timing() { + timing_type : setup_rising; + related_pin : "A_CLK"; + when : "A_MEN" + sdf_cond : "A_MEN" + + rise_constraint("SIG2SRAM_constraint_template") { + index_1("0.0040,0.0176,0.0344,0.0656,0.1120,0.2016,0.3800"); + index_2("0.0040,0.0176,0.0344,0.0656,0.1120,0.2016,0.3800"); + values ("0.1418,0.1496,0.1652,0.1887,0.2316,0.3059,0.4465",\ +"0.1301,0.1379,0.1535,0.1809,0.2199,0.2941,0.4348",\ +"0.1145,0.1262,0.1379,0.1652,0.2043,0.2785,0.4191",\ +"0.0871,0.0949,0.1105,0.1379,0.1770,0.2512,0.3879",\ +"0.0480,0.0598,0.0754,0.0988,0.1379,0.2082,0.3527",\ +"-0.0262,-0.0145,0.0012,0.0246,0.0676,0.1379,0.2785",\ +"-0.1668,-0.1551,-0.1395,-0.1121,-0.0730,0.0012,0.1418"); + } + + fall_constraint("SIG2SRAM_constraint_template") { + index_1("0.0040,0.0176,0.0344,0.0656,0.1120,0.2016,0.3800"); + index_2("0.0040,0.0176,0.0344,0.0656,0.1120,0.2016,0.3800"); + values ("0.2082,0.2160,0.2316,0.2590,0.2941,0.3684,0.5012",\ +"0.1926,0.2043,0.2199,0.2473,0.2824,0.3566,0.4895",\ +"0.1770,0.1887,0.2043,0.2316,0.2668,0.3410,0.4777",\ +"0.1535,0.1652,0.1770,0.2043,0.2395,0.3137,0.4504",\ +"0.1145,0.1262,0.1379,0.1652,0.2043,0.2746,0.4113",\ +"0.0402,0.0520,0.0676,0.0910,0.1262,0.2004,0.3332",\ +"-0.0965,-0.0848,-0.0730,-0.0457,-0.0066,0.0637,0.2004"); + } + } + + + timing() { + timing_type : hold_rising; + related_pin : "A_CLK"; + when : "A_MEN" + sdf_cond : "A_MEN" + + rise_constraint("SIG2SRAM_constraint_template") { + index_1("0.0040,0.0176,0.0344,0.0656,0.1120,0.2016,0.3800"); + index_2("0.0040,0.0176,0.0344,0.0656,0.1120,0.2016,0.3800"); + values ("0.1770,0.1652,0.1496,0.1223,0.0793,0.0090,-0.1316",\ +"0.1848,0.1730,0.1574,0.1301,0.0910,0.0168,-0.1199",\ +"0.2004,0.1887,0.1770,0.1496,0.1066,0.0363,-0.1043",\ +"0.2277,0.2160,0.2004,0.1730,0.1340,0.0598,-0.0809",\ +"0.2668,0.2551,0.2395,0.2121,0.1730,0.0988,-0.0418",\ +"0.3410,0.3293,0.3137,0.2863,0.2434,0.1730,0.0324",\ +"0.4816,0.4699,0.4543,0.4230,0.3801,0.3098,0.1730"); + } + + fall_constraint("SIG2SRAM_constraint_template") { + index_1("0.0040,0.0176,0.0344,0.0656,0.1120,0.2016,0.3800"); + index_2("0.0040,0.0176,0.0344,0.0656,0.1120,0.2016,0.3800"); + values ("0.1613,0.1496,0.1379,0.1066,0.0715,0.0012,-0.1355",\ +"0.1730,0.1613,0.1457,0.1184,0.0832,0.0129,-0.1238",\ +"0.1887,0.1770,0.1613,0.1340,0.0988,0.0246,-0.1121",\ +"0.2121,0.2043,0.1887,0.1613,0.1223,0.0520,-0.0848",\ +"0.2512,0.2434,0.2277,0.2004,0.1613,0.0910,-0.0457",\ +"0.3254,0.3176,0.3020,0.2746,0.2355,0.1652,0.0324",\ +"0.4660,0.4543,0.4387,0.4113,0.3723,0.3020,0.1691"); + } + } + } +pin(A_REN) { + direction : input ; + capacitance : 0.00390661 ; + max_transition : "0.38" ; + related_power_pin : VDD; + related_ground_pin : VSS; + internal_power() { + when : "A_MEN"; + rise_power("scalar"){ + values (0.0154); + } + fall_power("scalar"){ + values (0.0113); + } + } + internal_power() { + when : "!A_MEN"; + rise_power("scalar"){ + values (0.0276); + } + fall_power("scalar"){ + values (0.0235); + } + } + timing() { + timing_type : setup_rising; + related_pin : "A_CLK"; + when : "A_MEN" + sdf_cond : "A_MEN" + + rise_constraint("SIG2SRAM_constraint_template") { + index_1("0.0040,0.0176,0.0344,0.0656,0.1120,0.2016,0.3800"); + index_2("0.0040,0.0176,0.0344,0.0656,0.1120,0.2016,0.3800"); + values ("-0.0027,0.0090,0.0246,0.0520,0.0910,0.1613,0.3020",\ +"-0.0105,0.0012,0.0129,0.0363,0.0793,0.1535,0.2902",\ +"-0.0262,-0.0145,-0.0027,0.0246,0.0637,0.1379,0.2785",\ +"-0.0535,-0.0418,-0.0262,0.0012,0.0363,0.1105,0.2512",\ +"-0.0926,-0.0809,-0.0652,-0.0418,-0.0027,0.0715,0.2121",\ +"-0.1668,-0.1551,-0.1395,-0.1082,-0.0770,-0.0027,0.1379",\ +"-0.3035,-0.2918,-0.2762,-0.2488,-0.2137,-0.1434,-0.0027"); + } + + fall_constraint("SIG2SRAM_constraint_template") { + index_1("0.0040,0.0176,0.0344,0.0656,0.1120,0.2016,0.3800"); + index_2("0.0040,0.0176,0.0344,0.0656,0.1120,0.2016,0.3800"); + values ("0.0832,0.0949,0.1105,0.1379,0.1730,0.2473,0.3801",\ +"0.0754,0.0832,0.0988,0.1223,0.1613,0.2355,0.3684",\ +"0.0598,0.0676,0.0832,0.1066,0.1457,0.2121,0.3527",\ +"0.0324,0.0441,0.0598,0.0871,0.1223,0.1926,0.3293",\ +"-0.0066,0.0051,0.0168,0.0480,0.0832,0.1535,0.2902",\ +"-0.0809,-0.0691,-0.0574,-0.0301,0.0090,0.0832,0.2121",\ +"-0.2176,-0.2059,-0.1941,-0.1668,-0.1277,-0.0574,0.0793"); + } + } + + + timing() { + timing_type : hold_rising; + related_pin : "A_CLK"; + when : "A_MEN" + sdf_cond : "A_MEN" + + rise_constraint("SIG2SRAM_constraint_template") { + index_1("0.0040,0.0176,0.0344,0.0656,0.1120,0.2016,0.3800"); + index_2("0.0040,0.0176,0.0344,0.0656,0.1120,0.2016,0.3800"); + values ("0.1887,0.1770,0.1613,0.1340,0.0949,0.0207,-0.1160",\ +"0.1965,0.1848,0.1730,0.1457,0.1027,0.0324,-0.1082",\ +"0.2160,0.2004,0.1887,0.1613,0.1184,0.0480,-0.0926",\ +"0.2395,0.2277,0.2121,0.1848,0.1457,0.0715,-0.0652",\ +"0.2785,0.2668,0.2512,0.2238,0.1848,0.1105,-0.0262",\ +"0.3527,0.3410,0.3254,0.2980,0.2551,0.1848,0.0480",\ +"0.4934,0.4816,0.4660,0.4387,0.3957,0.3254,0.1887"); + } + + fall_constraint("SIG2SRAM_constraint_template") { + index_1("0.0040,0.0176,0.0344,0.0656,0.1120,0.2016,0.3800"); + index_2("0.0040,0.0176,0.0344,0.0656,0.1120,0.2016,0.3800"); + values ("0.1730,0.1613,0.1496,0.1184,0.0793,0.0129,-0.1238",\ +"0.1848,0.1730,0.1574,0.1301,0.0910,0.0207,-0.1121",\ +"0.2004,0.1887,0.1730,0.1457,0.1066,0.0363,-0.1004",\ +"0.2238,0.2121,0.2004,0.1691,0.1340,0.0598,-0.0730",\ +"0.2629,0.2512,0.2395,0.2121,0.1691,0.0988,-0.0340",\ +"0.3371,0.3254,0.3137,0.2863,0.2434,0.1730,0.0402",\ +"0.4777,0.4660,0.4504,0.4230,0.3840,0.3137,0.1809"); + } + } + } +pin(A_MEN) { + direction : input ; + capacitance : 0.00326046 ; + max_transition : "0.38" ; + related_power_pin : VDD; + related_ground_pin : VSS; + internal_power() { + rise_power("scalar"){ + values (0.2886); + } + fall_power("scalar"){ + values (0.4759); + } + } + timing() { + timing_type : setup_rising; + related_pin : "A_CLK"; + + rise_constraint("SIG2SRAM_constraint_template") { + index_1("0.0040,0.0176,0.0344,0.0656,0.1120,0.2016,0.3800"); + index_2("0.0040,0.0176,0.0344,0.0656,0.1120,0.2016,0.3800"); + values ("0.1418,0.1496,0.1652,0.1926,0.2316,0.3059,0.4465",\ +"0.1301,0.1379,0.1535,0.1809,0.2199,0.2941,0.4348",\ +"0.1145,0.1262,0.1418,0.1652,0.2043,0.2785,0.4191",\ +"0.0871,0.0949,0.1105,0.1379,0.1770,0.2512,0.3879",\ +"0.0480,0.0598,0.0754,0.0988,0.1379,0.2082,0.3488",\ +"-0.0262,-0.0145,0.0012,0.0285,0.0676,0.1379,0.2785",\ +"-0.1668,-0.1551,-0.1395,-0.1121,-0.0730,0.0012,0.1379"); + } + + fall_constraint("SIG2SRAM_constraint_template") { + index_1("0.0040,0.0176,0.0344,0.0656,0.1120,0.2016,0.3800"); + index_2("0.0040,0.0176,0.0344,0.0656,0.1120,0.2016,0.3800"); + values ("0.2082,0.2199,0.2316,0.2590,0.2980,0.3723,0.5051",\ +"0.1965,0.2082,0.2199,0.2473,0.2863,0.3605,0.4934",\ +"0.1809,0.1926,0.2043,0.2316,0.2707,0.3449,0.4777",\ +"0.1574,0.1691,0.1809,0.2082,0.2434,0.3176,0.4543",\ +"0.1145,0.1262,0.1418,0.1691,0.2043,0.2785,0.4113",\ +"0.0441,0.0559,0.0676,0.0949,0.1301,0.2004,0.3332",\ +"-0.0965,-0.0848,-0.0691,-0.0418,-0.0066,0.0676,0.2004"); + } + } + + + timing() { + timing_type : hold_rising; + related_pin : "A_CLK"; + + rise_constraint("SIG2SRAM_constraint_template") { + index_1("0.0040,0.0176,0.0344,0.0656,0.1120,0.2016,0.3800"); + index_2("0.0040,0.0176,0.0344,0.0656,0.1120,0.2016,0.3800"); + values ("0.1770,0.1652,0.1535,0.1262,0.0832,0.0129,-0.1277",\ +"0.1887,0.1770,0.1613,0.1340,0.0949,0.0207,-0.1199",\ +"0.2043,0.1926,0.1770,0.1496,0.1105,0.0363,-0.1043",\ +"0.2277,0.2160,0.2043,0.1770,0.1379,0.0598,-0.0770",\ +"0.2668,0.2551,0.2434,0.2160,0.1730,0.0988,-0.0379",\ +"0.3449,0.3332,0.3176,0.2902,0.2473,0.1730,0.0363",\ +"0.4816,0.4699,0.4543,0.4270,0.3840,0.3098,0.1770"); + } + + fall_constraint("SIG2SRAM_constraint_template") { + index_1("0.0040,0.0176,0.0344,0.0656,0.1120,0.2016,0.3800"); + index_2("0.0040,0.0176,0.0344,0.0656,0.1120,0.2016,0.3800"); + values ("0.1613,0.1496,0.1379,0.1105,0.0715,0.0012,-0.1355",\ +"0.1730,0.1613,0.1496,0.1184,0.0832,0.0129,-0.1238",\ +"0.1887,0.1770,0.1652,0.1340,0.0988,0.0285,-0.1121",\ +"0.2121,0.2043,0.1887,0.1613,0.1223,0.0520,-0.0848",\ +"0.2551,0.2434,0.2277,0.2004,0.1613,0.0910,-0.0418",\ +"0.3293,0.3176,0.3020,0.2746,0.2395,0.1652,0.0324",\ +"0.4660,0.4543,0.4426,0.4113,0.3762,0.3020,0.1691"); + } + } + } +bus(A_BM) { + bus_type : D_31_0; + direction : input ; + capacitance : 0.00310985 ; + max_transition : "0.38" ; + pin(A_BM[31:0]) { + related_power_pin : VDD; + related_ground_pin : VSS; + internal_power() { + when : "A_MEN"; + rise_power("scalar"){ + values (0.1512); + } + fall_power("scalar"){ + values (0.1660); + } + } + internal_power() { + when : "!A_MEN"; + rise_power("scalar"){ + values (0.1918); + } + fall_power("scalar"){ + values (0.1601); + } + } + } + timing() { + timing_type : setup_rising; + related_pin : "A_CLK"; + when : "(A_WEN & A_MEN)" + sdf_cond : "A_RW_ACCESS" + + rise_constraint("SIG2SRAM_constraint_template") { + index_1("0.0040,0.0176,0.0344,0.0656,0.1120,0.2016,0.3800"); + index_2("0.0040,0.0176,0.0344,0.0656,0.1120,0.2016,0.3800"); + values ("-0.2520,-0.2412,-0.2256,-0.1993,-0.1592,-0.0889,0.0459",\ +"-0.2559,-0.2451,-0.2295,-0.2031,-0.1631,-0.0928,0.0420",\ +"-0.2597,-0.2489,-0.2333,-0.2069,-0.1669,-0.0966,0.0382",\ +"-0.2629,-0.2522,-0.2366,-0.2102,-0.1702,-0.0998,0.0349",\ +"-0.2754,-0.2646,-0.2490,-0.2226,-0.1826,-0.1123,0.0225",\ +"-0.2928,-0.2821,-0.2665,-0.2401,-0.2001,-0.1297,0.0050",\ +"-0.3205,-0.3097,-0.2941,-0.2678,-0.2277,-0.1574,-0.0226"); + } + + fall_constraint("SIG2SRAM_constraint_template") { + index_1("0.0040,0.0176,0.0344,0.0656,0.1120,0.2016,0.3800"); + index_2("0.0040,0.0176,0.0344,0.0656,0.1120,0.2016,0.3800"); + values ("-0.2295,-0.2188,-0.2051,-0.1778,-0.1407,-0.0684,0.0615",\ +"-0.2334,-0.2227,-0.2090,-0.1817,-0.1445,-0.0723,0.0576",\ +"-0.2372,-0.2265,-0.2128,-0.1855,-0.1483,-0.0761,0.0538",\ +"-0.2405,-0.2297,-0.2160,-0.1887,-0.1516,-0.0793,0.0505",\ +"-0.2529,-0.2422,-0.2285,-0.2011,-0.1640,-0.0918,0.0381",\ +"-0.2704,-0.2596,-0.2460,-0.2186,-0.1815,-0.1092,0.0206",\ +"-0.2980,-0.2873,-0.2736,-0.2463,-0.2092,-0.1369,-0.0070"); + } + } + + + timing() { + timing_type : hold_rising; + related_pin : "A_CLK"; + when : "(A_WEN & A_MEN)" + sdf_cond : "A_RW_ACCESS" + + rise_constraint("SIG2SRAM_constraint_template") { + index_1("0.0040,0.0176,0.0344,0.0656,0.1120,0.2016,0.3800"); + index_2("0.0040,0.0176,0.0344,0.0656,0.1120,0.2016,0.3800"); + values ("0.3581,0.3463,0.3317,0.3053,0.2653,0.1940,0.0573",\ +"0.3619,0.3502,0.3356,0.3092,0.2692,0.1979,0.0612",\ +"0.3657,0.3540,0.3394,0.3130,0.2730,0.2017,0.0650",\ +"0.3690,0.3573,0.3426,0.3163,0.2762,0.2049,0.0682",\ +"0.3814,0.3697,0.3551,0.3287,0.2887,0.2174,0.0807",\ +"0.3989,0.3872,0.3725,0.3462,0.3061,0.2348,0.0981",\ +"0.4266,0.4148,0.4002,0.3738,0.3338,0.2625,0.1258"); + } + + fall_constraint("SIG2SRAM_constraint_template") { + index_1("0.0040,0.0176,0.0344,0.0656,0.1120,0.2016,0.3800"); + index_2("0.0040,0.0176,0.0344,0.0656,0.1120,0.2016,0.3800"); + values ("0.3297,0.3200,0.3053,0.2790,0.2418,0.1686,0.0407",\ +"0.3336,0.3239,0.3092,0.2828,0.2457,0.1725,0.0446",\ +"0.3374,0.3276,0.3130,0.2866,0.2495,0.1763,0.0484",\ +"0.3407,0.3309,0.3163,0.2899,0.2528,0.1795,0.0516",\ +"0.3531,0.3433,0.3287,0.3023,0.2652,0.1920,0.0641",\ +"0.3706,0.3608,0.3462,0.3198,0.2827,0.2094,0.0815",\ +"0.3982,0.3885,0.3738,0.3474,0.3103,0.2371,0.1092"); + } + } +} + pin(A_CLK) { + direction : input; + capacitance : 0.00389386; + max_transition : "0.38"; + clock : "true" ; + pin_func_type : active_rising ; + + timing () { + timing_type : "min_pulse_width"; + related_pin : "A_CLK"; + rise_constraint("CLKTRAN_constraint_template") { + index_1("0.004,0.38"); + values("0.12,0.12"); + } + } + + related_power_pin : VDD; + related_ground_pin : VSS; + + internal_power() { + when : "!A_MEN & !A_WEN & !A_REN"; + rise_power("scalar"){ + values (0); + } + fall_power("scalar"){ + values (0); + } + } + internal_power() { + when : "!A_MEN & A_WEN & !A_REN"; + rise_power("scalar"){ + values (0.7228); + } + fall_power("scalar"){ + values (0); + } + } + internal_power() { + when : "A_MEN & A_WEN & !A_REN"; + rise_power("scalar"){ + values (73.7434); + } + fall_power("scalar"){ + values (0); + } + } + internal_power() { + when : "A_MEN & A_WEN & A_REN"; + rise_power("scalar"){ + values (76.2622); + } + fall_power("scalar"){ + values (0); + } + } + internal_power() { + when : "A_MEN & !A_WEN & A_REN"; + rise_power("scalar"){ + values (61.9692); + } + fall_power("scalar"){ + values (0); + } + } + internal_power() { + when : "!A_MEN & !A_WEN & A_REN"; + rise_power("scalar"){ + values (0.4287); + } + fall_power("scalar"){ + values (0); + } + } + internal_power() { + when : "!A_MEN & A_WEN & A_REN"; + rise_power("scalar"){ + values (1.4323); + } + fall_power("scalar"){ + values (0); + } + } + internal_power() { + when : "A_MEN & !A_WEN & !A_REN"; + rise_power("scalar"){ + values (0); + } + fall_power("scalar"){ + values (0); + } + } + } + bus(A_DIN) { + bus_type : D_31_0; + direction : input ; + capacitance : 0.00387207 ; + memory_write() { + address : A_ADDR ; + clocked_on : A_CLK; + } + + max_transition : "0.38" ; + pin(A_DIN[31:0]) { + related_power_pin : VDD; + related_ground_pin : VSS; + internal_power() { + when : "A_MEN"; + rise_power("scalar"){ + values (0.1512); + } + fall_power("scalar"){ + values (0.1660); + } + } + internal_power() { + when : "!A_MEN"; + rise_power("scalar"){ + values (0.1918); + } + fall_power("scalar"){ + values (0.1601); + } + } + } + timing() { + timing_type : setup_rising; + related_pin : "A_CLK"; + when : "(A_WEN & A_MEN)"; + sdf_cond : "A_W_ACCESS"; + + rise_constraint("SIG2SRAM_constraint_template") { + index_1("0.0040,0.0176,0.0344,0.0656,0.1120,0.2016,0.3800"); + index_2("0.0040,0.0176,0.0344,0.0656,0.1120,0.2016,0.3800"); + values ("-0.2520,-0.2412,-0.2256,-0.1993,-0.1592,-0.0889,0.0459",\ +"-0.2559,-0.2451,-0.2295,-0.2031,-0.1631,-0.0928,0.0420",\ +"-0.2597,-0.2489,-0.2333,-0.2069,-0.1669,-0.0966,0.0382",\ +"-0.2629,-0.2522,-0.2366,-0.2102,-0.1702,-0.0998,0.0349",\ +"-0.2754,-0.2646,-0.2490,-0.2226,-0.1826,-0.1123,0.0225",\ +"-0.2928,-0.2821,-0.2665,-0.2401,-0.2001,-0.1297,0.0050",\ +"-0.3205,-0.3097,-0.2941,-0.2678,-0.2277,-0.1574,-0.0226"); + } + + fall_constraint("SIG2SRAM_constraint_template") { + index_1("0.0040,0.0176,0.0344,0.0656,0.1120,0.2016,0.3800"); + index_2("0.0040,0.0176,0.0344,0.0656,0.1120,0.2016,0.3800"); + values ("-0.2295,-0.2188,-0.2051,-0.1778,-0.1407,-0.0684,0.0615",\ +"-0.2334,-0.2227,-0.2090,-0.1817,-0.1445,-0.0723,0.0576",\ +"-0.2372,-0.2265,-0.2128,-0.1855,-0.1483,-0.0761,0.0538",\ +"-0.2405,-0.2297,-0.2160,-0.1887,-0.1516,-0.0793,0.0505",\ +"-0.2529,-0.2422,-0.2285,-0.2011,-0.1640,-0.0918,0.0381",\ +"-0.2704,-0.2596,-0.2460,-0.2186,-0.1815,-0.1092,0.0206",\ +"-0.2980,-0.2873,-0.2736,-0.2463,-0.2092,-0.1369,-0.0070"); + } + } + + timing() { + timing_type : hold_rising; + related_pin : "A_CLK"; + when : "(A_WEN & A_MEN)"; + sdf_cond : "A_W_ACCESS"; + + rise_constraint("SIG2SRAM_constraint_template") { + index_1("0.0040,0.0176,0.0344,0.0656,0.1120,0.2016,0.3800"); + index_2("0.0040,0.0176,0.0344,0.0656,0.1120,0.2016,0.3800"); + values ("0.3581,0.3463,0.3317,0.3053,0.2653,0.1940,0.0573",\ +"0.3619,0.3502,0.3356,0.3092,0.2692,0.1979,0.0612",\ +"0.3657,0.3540,0.3394,0.3130,0.2730,0.2017,0.0650",\ +"0.3690,0.3573,0.3426,0.3163,0.2762,0.2049,0.0682",\ +"0.3814,0.3697,0.3551,0.3287,0.2887,0.2174,0.0807",\ +"0.3989,0.3872,0.3725,0.3462,0.3061,0.2348,0.0981",\ +"0.4266,0.4148,0.4002,0.3738,0.3338,0.2625,0.1258"); + } + + fall_constraint("SIG2SRAM_constraint_template") { + index_1("0.0040,0.0176,0.0344,0.0656,0.1120,0.2016,0.3800"); + index_2("0.0040,0.0176,0.0344,0.0656,0.1120,0.2016,0.3800"); + values ("0.3297,0.3200,0.3053,0.2790,0.2418,0.1686,0.0407",\ +"0.3336,0.3239,0.3092,0.2828,0.2457,0.1725,0.0446",\ +"0.3374,0.3276,0.3130,0.2866,0.2495,0.1763,0.0484",\ +"0.3407,0.3309,0.3163,0.2899,0.2528,0.1795,0.0516",\ +"0.3531,0.3433,0.3287,0.3023,0.2652,0.1920,0.0641",\ +"0.3706,0.3608,0.3462,0.3198,0.2827,0.2094,0.0815",\ +"0.3982,0.3885,0.3738,0.3474,0.3103,0.2371,0.1092"); + } + } + } + + pin(A_BIST_EN) { + direction : input ; + capacitance : 0.00421562 ; + max_transition : "1" ; + related_power_pin : VDD; + related_ground_pin : VSS; + internal_power() { + rise_power("scalar") { + values (0); + } + fall_power("scalar") { + values (0); + } + } + } + +bus(A_BIST_ADDR) { + bus_type : A_9_0; + direction : input ; + capacitance : 0.00691085 ; + pin(A_BIST_ADDR[0]) { + capacitance : 0.00562034 ; + } + pin(A_BIST_ADDR[1]) { + capacitance : 0.00462655 ; + } + pin(A_BIST_ADDR[2]) { + capacitance : 0.00594295 ; + } + pin(A_BIST_ADDR[3]) { + capacitance : 0.00723434 ; + } + pin(A_BIST_ADDR[4]) { + capacitance : 0.00481603 ; + } + pin(A_BIST_ADDR[5]) { + capacitance : 0.00868123 ; + } + pin(A_BIST_ADDR[6]) { + capacitance : 0.010187 ; + } + pin(A_BIST_ADDR[7]) { + capacitance : 0.00734489 ; + } + pin(A_BIST_ADDR[8]) { + capacitance : 0.00904175 ; + } + max_transition : "0.38" ; + pin(A_BIST_ADDR[9:0]) { + related_power_pin : VDD; + related_ground_pin : VSS; + internal_power() { + when : "A_BIST_MEN"; + rise_power("scalar"){ + values (0.4735); + } + fall_power("scalar"){ + values (0.6259); + } + } + internal_power() { + when : "!A_BIST_MEN"; + rise_power("scalar"){ + values (0.0322); + } + fall_power("scalar"){ + values (0.0023); + } + } + } + timing() { + timing_type : setup_rising; + related_pin : "A_BIST_CLK"; + when : "((A_BIST_WEN | A_BIST_REN)& A_BIST_MEN)" + sdf_cond : "A_BIST_RW_ACCESS" + + rise_constraint("SIG2SRAM_constraint_template") { + index_1("0.0040,0.0176,0.0344,0.0656,0.1120,0.2016,0.3800"); + index_2("0.0040,0.0176,0.0344,0.0656,0.1120,0.2016,0.3800"); + values ("-0.2371,-0.2215,-0.2098,-0.1824,-0.1434,-0.0691,0.0676",\ +"-0.2449,-0.2332,-0.2176,-0.1902,-0.1551,-0.0770,0.0559",\ +"-0.2605,-0.2488,-0.2332,-0.2059,-0.1707,-0.0965,0.0441",\ +"-0.2879,-0.2723,-0.2605,-0.2332,-0.1941,-0.1199,0.0168",\ +"-0.3230,-0.3113,-0.2996,-0.2723,-0.2332,-0.1590,-0.0184",\ +"-0.4012,-0.3895,-0.3738,-0.3465,-0.3074,-0.2332,-0.0965",\ +"-0.5379,-0.5262,-0.5105,-0.4832,-0.4480,-0.3699,-0.2332"); + } + + fall_constraint("SIG2SRAM_constraint_template") { + index_1("0.0040,0.0176,0.0344,0.0656,0.1120,0.2016,0.3800"); + index_2("0.0040,0.0176,0.0344,0.0656,0.1120,0.2016,0.3800"); + values ("-0.1785,-0.1707,-0.1551,-0.1277,-0.0887,-0.0184,0.1145",\ +"-0.1902,-0.1785,-0.1629,-0.1355,-0.1004,-0.0262,0.1027",\ +"-0.2059,-0.1941,-0.1785,-0.1512,-0.1160,-0.0418,0.0871",\ +"-0.2293,-0.2176,-0.2059,-0.1785,-0.1434,-0.0691,0.0598",\ +"-0.2684,-0.2566,-0.2449,-0.2176,-0.1824,-0.1082,0.0207",\ +"-0.3465,-0.3348,-0.3191,-0.2918,-0.2566,-0.1824,-0.0535",\ +"-0.4832,-0.4715,-0.4559,-0.4324,-0.3934,-0.3191,-0.1902"); + } + } + + + timing() { + timing_type : hold_rising; + related_pin : "A_BIST_CLK"; + when : "((A_BIST_WEN | A_BIST_REN)& A_BIST_MEN)" + sdf_cond : "A_BIST_RW_ACCESS" + + rise_constraint("SIG2SRAM_constraint_template") { + index_1("0.0040,0.0176,0.0344,0.0656,0.1120,0.2016,0.3800"); + index_2("0.0040,0.0176,0.0344,0.0656,0.1120,0.2016,0.3800"); + values ("0.3410,0.3293,0.3137,0.2863,0.2473,0.1730,0.0324",\ +"0.3488,0.3371,0.3215,0.2941,0.2590,0.1809,0.0480",\ +"0.3684,0.3527,0.3371,0.3098,0.2746,0.1965,0.0598",\ +"0.3918,0.3762,0.3645,0.3371,0.2980,0.2238,0.0871",\ +"0.4309,0.4152,0.4035,0.3762,0.3371,0.2629,0.1223",\ +"0.5051,0.4934,0.4777,0.4504,0.4113,0.3371,0.1965",\ +"0.6418,0.6262,0.6145,0.5871,0.5520,0.4738,0.3332"); + } + + fall_constraint("SIG2SRAM_constraint_template") { + index_1("0.0040,0.0176,0.0344,0.0656,0.1120,0.2016,0.3800"); + index_2("0.0040,0.0176,0.0344,0.0656,0.1120,0.2016,0.3800"); + values ("0.2824,0.2707,0.2551,0.2277,0.1926,0.1184,-0.0105",\ +"0.2902,0.2785,0.2668,0.2395,0.2043,0.1301,0.0012",\ +"0.3059,0.2941,0.2824,0.2551,0.2199,0.1457,0.0168",\ +"0.3332,0.3215,0.3059,0.2785,0.2434,0.1691,0.0402",\ +"0.3723,0.3605,0.3449,0.3176,0.2824,0.2121,0.0793",\ +"0.4465,0.4348,0.4230,0.3918,0.3566,0.2824,0.1535",\ +"0.5832,0.5715,0.5598,0.5324,0.4934,0.4191,0.2902"); + } + } +} +pin(A_BIST_WEN) { + direction : input ; + capacitance : 0.00341384 ; + max_transition : "0.38" ; + related_power_pin : VDD; + related_ground_pin : VSS; + internal_power() { + when : "A_BIST_MEN"; + rise_power("scalar"){ + values (0.9384); + } + fall_power("scalar"){ + values (0.0212); + } + } + internal_power() { + when : "!A_BIST_MEN"; + rise_power("scalar"){ + values (0.0069); + } + fall_power("scalar"){ + values (0.0124); + } + } + timing() { + timing_type : setup_rising; + related_pin : "A_BIST_CLK"; + when : "A_BIST_MEN" + sdf_cond : "A_BIST_MEN" + + rise_constraint("SIG2SRAM_constraint_template") { + index_1("0.0040,0.0176,0.0344,0.0656,0.1120,0.2016,0.3800"); + index_2("0.0040,0.0176,0.0344,0.0656,0.1120,0.2016,0.3800"); + values ("0.1418,0.1496,0.1652,0.1887,0.2316,0.3059,0.4465",\ +"0.1301,0.1379,0.1535,0.1809,0.2199,0.2941,0.4348",\ +"0.1145,0.1262,0.1379,0.1652,0.2043,0.2785,0.4191",\ +"0.0871,0.0949,0.1105,0.1379,0.1770,0.2512,0.3879",\ +"0.0480,0.0598,0.0754,0.0988,0.1379,0.2082,0.3527",\ +"-0.0262,-0.0145,0.0012,0.0246,0.0676,0.1379,0.2785",\ +"-0.1668,-0.1551,-0.1395,-0.1121,-0.0730,0.0012,0.1418"); + } + + fall_constraint("SIG2SRAM_constraint_template") { + index_1("0.0040,0.0176,0.0344,0.0656,0.1120,0.2016,0.3800"); + index_2("0.0040,0.0176,0.0344,0.0656,0.1120,0.2016,0.3800"); + values ("0.2082,0.2160,0.2316,0.2590,0.2941,0.3684,0.5012",\ +"0.1926,0.2043,0.2199,0.2473,0.2824,0.3566,0.4895",\ +"0.1770,0.1887,0.2043,0.2316,0.2668,0.3410,0.4777",\ +"0.1535,0.1652,0.1770,0.2043,0.2395,0.3137,0.4504",\ +"0.1145,0.1262,0.1379,0.1652,0.2043,0.2746,0.4113",\ +"0.0402,0.0520,0.0676,0.0910,0.1262,0.2004,0.3332",\ +"-0.0965,-0.0848,-0.0730,-0.0457,-0.0066,0.0637,0.2004"); + } + } + + + timing() { + timing_type : hold_rising; + related_pin : "A_BIST_CLK"; + when : "A_BIST_MEN" + sdf_cond : "A_BIST_MEN" + + rise_constraint("SIG2SRAM_constraint_template") { + index_1("0.0040,0.0176,0.0344,0.0656,0.1120,0.2016,0.3800"); + index_2("0.0040,0.0176,0.0344,0.0656,0.1120,0.2016,0.3800"); + values ("0.1770,0.1652,0.1496,0.1223,0.0793,0.0090,-0.1316",\ +"0.1848,0.1730,0.1574,0.1301,0.0910,0.0168,-0.1199",\ +"0.2004,0.1887,0.1770,0.1496,0.1066,0.0363,-0.1043",\ +"0.2277,0.2160,0.2004,0.1730,0.1340,0.0598,-0.0809",\ +"0.2668,0.2551,0.2395,0.2121,0.1730,0.0988,-0.0418",\ +"0.3410,0.3293,0.3137,0.2863,0.2434,0.1730,0.0324",\ +"0.4816,0.4699,0.4543,0.4230,0.3801,0.3098,0.1730"); + } + + fall_constraint("SIG2SRAM_constraint_template") { + index_1("0.0040,0.0176,0.0344,0.0656,0.1120,0.2016,0.3800"); + index_2("0.0040,0.0176,0.0344,0.0656,0.1120,0.2016,0.3800"); + values ("0.1613,0.1496,0.1379,0.1066,0.0715,0.0012,-0.1355",\ +"0.1730,0.1613,0.1457,0.1184,0.0832,0.0129,-0.1238",\ +"0.1887,0.1770,0.1613,0.1340,0.0988,0.0246,-0.1121",\ +"0.2121,0.2043,0.1887,0.1613,0.1223,0.0520,-0.0848",\ +"0.2512,0.2434,0.2277,0.2004,0.1613,0.0910,-0.0457",\ +"0.3254,0.3176,0.3020,0.2746,0.2355,0.1652,0.0324",\ +"0.4660,0.4543,0.4387,0.4113,0.3723,0.3020,0.1691"); + } + } + } +pin(A_BIST_REN) { + direction : input ; + capacitance : 0.00390661 ; + max_transition : "0.38" ; + related_power_pin : VDD; + related_ground_pin : VSS; + internal_power() { + when : "A_BIST_MEN"; + rise_power("scalar"){ + values (0.0154); + } + fall_power("scalar"){ + values (0.0113); + } + } + internal_power() { + when : "!A_BIST_MEN"; + rise_power("scalar"){ + values (0.0276); + } + fall_power("scalar"){ + values (0.0235); + } + } + timing() { + timing_type : setup_rising; + related_pin : "A_BIST_CLK"; + when : "A_BIST_MEN" + sdf_cond : "A_BIST_MEN" + + rise_constraint("SIG2SRAM_constraint_template") { + index_1("0.0040,0.0176,0.0344,0.0656,0.1120,0.2016,0.3800"); + index_2("0.0040,0.0176,0.0344,0.0656,0.1120,0.2016,0.3800"); + values ("-0.0027,0.0090,0.0246,0.0520,0.0910,0.1613,0.3020",\ +"-0.0105,0.0012,0.0129,0.0363,0.0793,0.1535,0.2902",\ +"-0.0262,-0.0145,-0.0027,0.0246,0.0637,0.1379,0.2785",\ +"-0.0535,-0.0418,-0.0262,0.0012,0.0363,0.1105,0.2512",\ +"-0.0926,-0.0809,-0.0652,-0.0418,-0.0027,0.0715,0.2121",\ +"-0.1668,-0.1551,-0.1395,-0.1082,-0.0770,-0.0027,0.1379",\ +"-0.3035,-0.2918,-0.2762,-0.2488,-0.2137,-0.1434,-0.0027"); + } + + fall_constraint("SIG2SRAM_constraint_template") { + index_1("0.0040,0.0176,0.0344,0.0656,0.1120,0.2016,0.3800"); + index_2("0.0040,0.0176,0.0344,0.0656,0.1120,0.2016,0.3800"); + values ("0.0832,0.0949,0.1105,0.1379,0.1730,0.2473,0.3801",\ +"0.0754,0.0832,0.0988,0.1223,0.1613,0.2355,0.3684",\ +"0.0598,0.0676,0.0832,0.1066,0.1457,0.2121,0.3527",\ +"0.0324,0.0441,0.0598,0.0871,0.1223,0.1926,0.3293",\ +"-0.0066,0.0051,0.0168,0.0480,0.0832,0.1535,0.2902",\ +"-0.0809,-0.0691,-0.0574,-0.0301,0.0090,0.0832,0.2121",\ +"-0.2176,-0.2059,-0.1941,-0.1668,-0.1277,-0.0574,0.0793"); + } + } + + + timing() { + timing_type : hold_rising; + related_pin : "A_BIST_CLK"; + when : "A_BIST_MEN" + sdf_cond : "A_BIST_MEN" + + rise_constraint("SIG2SRAM_constraint_template") { + index_1("0.0040,0.0176,0.0344,0.0656,0.1120,0.2016,0.3800"); + index_2("0.0040,0.0176,0.0344,0.0656,0.1120,0.2016,0.3800"); + values ("0.1887,0.1770,0.1613,0.1340,0.0949,0.0207,-0.1160",\ +"0.1965,0.1848,0.1730,0.1457,0.1027,0.0324,-0.1082",\ +"0.2160,0.2004,0.1887,0.1613,0.1184,0.0480,-0.0926",\ +"0.2395,0.2277,0.2121,0.1848,0.1457,0.0715,-0.0652",\ +"0.2785,0.2668,0.2512,0.2238,0.1848,0.1105,-0.0262",\ +"0.3527,0.3410,0.3254,0.2980,0.2551,0.1848,0.0480",\ +"0.4934,0.4816,0.4660,0.4387,0.3957,0.3254,0.1887"); + } + + fall_constraint("SIG2SRAM_constraint_template") { + index_1("0.0040,0.0176,0.0344,0.0656,0.1120,0.2016,0.3800"); + index_2("0.0040,0.0176,0.0344,0.0656,0.1120,0.2016,0.3800"); + values ("0.1730,0.1613,0.1496,0.1184,0.0793,0.0129,-0.1238",\ +"0.1848,0.1730,0.1574,0.1301,0.0910,0.0207,-0.1121",\ +"0.2004,0.1887,0.1730,0.1457,0.1066,0.0363,-0.1004",\ +"0.2238,0.2121,0.2004,0.1691,0.1340,0.0598,-0.0730",\ +"0.2629,0.2512,0.2395,0.2121,0.1691,0.0988,-0.0340",\ +"0.3371,0.3254,0.3137,0.2863,0.2434,0.1730,0.0402",\ +"0.4777,0.4660,0.4504,0.4230,0.3840,0.3137,0.1809"); + } + } + } +pin(A_BIST_MEN) { + direction : input ; + capacitance : 0.00326046 ; + max_transition : "0.38" ; + related_power_pin : VDD; + related_ground_pin : VSS; + internal_power() { + rise_power("scalar"){ + values (0.2886); + } + fall_power("scalar"){ + values (0.4759); + } + } + timing() { + timing_type : setup_rising; + related_pin : "A_BIST_CLK"; + + rise_constraint("SIG2SRAM_constraint_template") { + index_1("0.0040,0.0176,0.0344,0.0656,0.1120,0.2016,0.3800"); + index_2("0.0040,0.0176,0.0344,0.0656,0.1120,0.2016,0.3800"); + values ("0.1418,0.1496,0.1652,0.1926,0.2316,0.3059,0.4465",\ +"0.1301,0.1379,0.1535,0.1809,0.2199,0.2941,0.4348",\ +"0.1145,0.1262,0.1418,0.1652,0.2043,0.2785,0.4191",\ +"0.0871,0.0949,0.1105,0.1379,0.1770,0.2512,0.3879",\ +"0.0480,0.0598,0.0754,0.0988,0.1379,0.2082,0.3488",\ +"-0.0262,-0.0145,0.0012,0.0285,0.0676,0.1379,0.2785",\ +"-0.1668,-0.1551,-0.1395,-0.1121,-0.0730,0.0012,0.1379"); + } + + fall_constraint("SIG2SRAM_constraint_template") { + index_1("0.0040,0.0176,0.0344,0.0656,0.1120,0.2016,0.3800"); + index_2("0.0040,0.0176,0.0344,0.0656,0.1120,0.2016,0.3800"); + values ("0.2082,0.2199,0.2316,0.2590,0.2980,0.3723,0.5051",\ +"0.1965,0.2082,0.2199,0.2473,0.2863,0.3605,0.4934",\ +"0.1809,0.1926,0.2043,0.2316,0.2707,0.3449,0.4777",\ +"0.1574,0.1691,0.1809,0.2082,0.2434,0.3176,0.4543",\ +"0.1145,0.1262,0.1418,0.1691,0.2043,0.2785,0.4113",\ +"0.0441,0.0559,0.0676,0.0949,0.1301,0.2004,0.3332",\ +"-0.0965,-0.0848,-0.0691,-0.0418,-0.0066,0.0676,0.2004"); + } + } + + + timing() { + timing_type : hold_rising; + related_pin : "A_BIST_CLK"; + + rise_constraint("SIG2SRAM_constraint_template") { + index_1("0.0040,0.0176,0.0344,0.0656,0.1120,0.2016,0.3800"); + index_2("0.0040,0.0176,0.0344,0.0656,0.1120,0.2016,0.3800"); + values ("0.1770,0.1652,0.1535,0.1262,0.0832,0.0129,-0.1277",\ +"0.1887,0.1770,0.1613,0.1340,0.0949,0.0207,-0.1199",\ +"0.2043,0.1926,0.1770,0.1496,0.1105,0.0363,-0.1043",\ +"0.2277,0.2160,0.2043,0.1770,0.1379,0.0598,-0.0770",\ +"0.2668,0.2551,0.2434,0.2160,0.1730,0.0988,-0.0379",\ +"0.3449,0.3332,0.3176,0.2902,0.2473,0.1730,0.0363",\ +"0.4816,0.4699,0.4543,0.4270,0.3840,0.3098,0.1770"); + } + + fall_constraint("SIG2SRAM_constraint_template") { + index_1("0.0040,0.0176,0.0344,0.0656,0.1120,0.2016,0.3800"); + index_2("0.0040,0.0176,0.0344,0.0656,0.1120,0.2016,0.3800"); + values ("0.1613,0.1496,0.1379,0.1105,0.0715,0.0012,-0.1355",\ +"0.1730,0.1613,0.1496,0.1184,0.0832,0.0129,-0.1238",\ +"0.1887,0.1770,0.1652,0.1340,0.0988,0.0285,-0.1121",\ +"0.2121,0.2043,0.1887,0.1613,0.1223,0.0520,-0.0848",\ +"0.2551,0.2434,0.2277,0.2004,0.1613,0.0910,-0.0418",\ +"0.3293,0.3176,0.3020,0.2746,0.2395,0.1652,0.0324",\ +"0.4660,0.4543,0.4426,0.4113,0.3762,0.3020,0.1691"); + } + } + } +bus(A_BIST_BM) { + bus_type : D_31_0; + direction : input ; + capacitance : 0.00253457 ; + max_transition : "0.38" ; + pin(A_BIST_BM[31:0]) { + related_power_pin : VDD; + related_ground_pin : VSS; + internal_power() { + when : "A_BIST_MEN"; + rise_power("scalar"){ + values (0.1512); + } + fall_power("scalar"){ + values (0.1660); + } + } + internal_power() { + when : "!A_BIST_MEN"; + rise_power("scalar"){ + values (0.1918); + } + fall_power("scalar"){ + values (0.1601); + } + } + } + timing() { + timing_type : setup_rising; + related_pin : "A_BIST_CLK"; + when : "(A_BIST_WEN & A_BIST_MEN)" + sdf_cond : "A_BIST_RW_ACCESS" + + rise_constraint("SIG2SRAM_constraint_template") { + index_1("0.0040,0.0176,0.0344,0.0656,0.1120,0.2016,0.3800"); + index_2("0.0040,0.0176,0.0344,0.0656,0.1120,0.2016,0.3800"); + values ("-0.2520,-0.2412,-0.2256,-0.1993,-0.1592,-0.0889,0.0459",\ +"-0.2559,-0.2451,-0.2295,-0.2031,-0.1631,-0.0928,0.0420",\ +"-0.2597,-0.2489,-0.2333,-0.2069,-0.1669,-0.0966,0.0382",\ +"-0.2629,-0.2522,-0.2366,-0.2102,-0.1702,-0.0998,0.0349",\ +"-0.2754,-0.2646,-0.2490,-0.2226,-0.1826,-0.1123,0.0225",\ +"-0.2928,-0.2821,-0.2665,-0.2401,-0.2001,-0.1297,0.0050",\ +"-0.3205,-0.3097,-0.2941,-0.2678,-0.2277,-0.1574,-0.0226"); + } + + fall_constraint("SIG2SRAM_constraint_template") { + index_1("0.0040,0.0176,0.0344,0.0656,0.1120,0.2016,0.3800"); + index_2("0.0040,0.0176,0.0344,0.0656,0.1120,0.2016,0.3800"); + values ("-0.2295,-0.2188,-0.2051,-0.1778,-0.1407,-0.0684,0.0615",\ +"-0.2334,-0.2227,-0.2090,-0.1817,-0.1445,-0.0723,0.0576",\ +"-0.2372,-0.2265,-0.2128,-0.1855,-0.1483,-0.0761,0.0538",\ +"-0.2405,-0.2297,-0.2160,-0.1887,-0.1516,-0.0793,0.0505",\ +"-0.2529,-0.2422,-0.2285,-0.2011,-0.1640,-0.0918,0.0381",\ +"-0.2704,-0.2596,-0.2460,-0.2186,-0.1815,-0.1092,0.0206",\ +"-0.2980,-0.2873,-0.2736,-0.2463,-0.2092,-0.1369,-0.0070"); + } + } + + + timing() { + timing_type : hold_rising; + related_pin : "A_BIST_CLK"; + when : "(A_BIST_WEN & A_BIST_MEN)" + sdf_cond : "A_BIST_RW_ACCESS" + + rise_constraint("SIG2SRAM_constraint_template") { + index_1("0.0040,0.0176,0.0344,0.0656,0.1120,0.2016,0.3800"); + index_2("0.0040,0.0176,0.0344,0.0656,0.1120,0.2016,0.3800"); + values ("0.3581,0.3463,0.3317,0.3053,0.2653,0.1940,0.0573",\ +"0.3619,0.3502,0.3356,0.3092,0.2692,0.1979,0.0612",\ +"0.3657,0.3540,0.3394,0.3130,0.2730,0.2017,0.0650",\ +"0.3690,0.3573,0.3426,0.3163,0.2762,0.2049,0.0682",\ +"0.3814,0.3697,0.3551,0.3287,0.2887,0.2174,0.0807",\ +"0.3989,0.3872,0.3725,0.3462,0.3061,0.2348,0.0981",\ +"0.4266,0.4148,0.4002,0.3738,0.3338,0.2625,0.1258"); + } + + fall_constraint("SIG2SRAM_constraint_template") { + index_1("0.0040,0.0176,0.0344,0.0656,0.1120,0.2016,0.3800"); + index_2("0.0040,0.0176,0.0344,0.0656,0.1120,0.2016,0.3800"); + values ("0.3297,0.3200,0.3053,0.2790,0.2418,0.1686,0.0407",\ +"0.3336,0.3239,0.3092,0.2828,0.2457,0.1725,0.0446",\ +"0.3374,0.3276,0.3130,0.2866,0.2495,0.1763,0.0484",\ +"0.3407,0.3309,0.3163,0.2899,0.2528,0.1795,0.0516",\ +"0.3531,0.3433,0.3287,0.3023,0.2652,0.1920,0.0641",\ +"0.3706,0.3608,0.3462,0.3198,0.2827,0.2094,0.0815",\ +"0.3982,0.3885,0.3738,0.3474,0.3103,0.2371,0.1092"); + } + } +} + pin(A_BIST_CLK) { + direction : input; + capacitance : 0.00389386; + max_transition : "0.38"; + clock : "true" ; + pin_func_type : active_rising ; + + timing () { + timing_type : "min_pulse_width"; + related_pin : "A_BIST_CLK"; + rise_constraint("CLKTRAN_constraint_template") { + index_1("0.004,0.38"); + values("0.12,0.12"); + } + } + + related_power_pin : VDD; + related_ground_pin : VSS; + + internal_power() { + when : "!A_BIST_MEN & !A_BIST_WEN & !A_BIST_REN"; + rise_power("scalar"){ + values (0); + } + fall_power("scalar"){ + values (0); + } + } + internal_power() { + when : "!A_BIST_MEN & A_BIST_WEN & !A_BIST_REN"; + rise_power("scalar"){ + values (0.7228); + } + fall_power("scalar"){ + values (0); + } + } + internal_power() { + when : "A_BIST_MEN & A_BIST_WEN & !A_BIST_REN"; + rise_power("scalar"){ + values (73.7434); + } + fall_power("scalar"){ + values (0); + } + } + internal_power() { + when : "A_BIST_MEN & A_BIST_WEN & A_BIST_REN"; + rise_power("scalar"){ + values (76.2622); + } + fall_power("scalar"){ + values (0); + } + } + internal_power() { + when : "A_BIST_MEN & !A_BIST_WEN & A_BIST_REN"; + rise_power("scalar"){ + values (61.9692); + } + fall_power("scalar"){ + values (0); + } + } + internal_power() { + when : "!A_BIST_MEN & !A_BIST_WEN & A_BIST_REN"; + rise_power("scalar"){ + values (0.4287); + } + fall_power("scalar"){ + values (0); + } + } + internal_power() { + when : "!A_BIST_MEN & A_BIST_WEN & A_BIST_REN"; + rise_power("scalar"){ + values (1.4323); + } + fall_power("scalar"){ + values (0); + } + } + internal_power() { + when : "A_BIST_MEN & !A_BIST_WEN & !A_BIST_REN"; + rise_power("scalar"){ + values (0); + } + fall_power("scalar"){ + values (0); + } + } + } + bus(A_BIST_DIN) { + bus_type : D_31_0; + direction : input ; + capacitance : 0.00252927 ; + memory_write() { + address : A_BIST_ADDR ; + clocked_on : A_BIST_CLK; + } + + max_transition : "0.38" ; + pin(A_BIST_DIN[31:0]) { + related_power_pin : VDD; + related_ground_pin : VSS; + internal_power() { + when : "A_BIST_MEN"; + rise_power("scalar"){ + values (0.1512); + } + fall_power("scalar"){ + values (0.1660); + } + } + internal_power() { + when : "!A_BIST_MEN"; + rise_power("scalar"){ + values (0.1918); + } + fall_power("scalar"){ + values (0.1601); + } + } + } + timing() { + timing_type : setup_rising; + related_pin : "A_BIST_CLK"; + when : "(A_BIST_WEN & A_BIST_MEN)"; + sdf_cond : "A_BIST_W_ACCESS"; + + rise_constraint("SIG2SRAM_constraint_template") { + index_1("0.0040,0.0176,0.0344,0.0656,0.1120,0.2016,0.3800"); + index_2("0.0040,0.0176,0.0344,0.0656,0.1120,0.2016,0.3800"); + values ("-0.2520,-0.2412,-0.2256,-0.1993,-0.1592,-0.0889,0.0459",\ +"-0.2559,-0.2451,-0.2295,-0.2031,-0.1631,-0.0928,0.0420",\ +"-0.2597,-0.2489,-0.2333,-0.2069,-0.1669,-0.0966,0.0382",\ +"-0.2629,-0.2522,-0.2366,-0.2102,-0.1702,-0.0998,0.0349",\ +"-0.2754,-0.2646,-0.2490,-0.2226,-0.1826,-0.1123,0.0225",\ +"-0.2928,-0.2821,-0.2665,-0.2401,-0.2001,-0.1297,0.0050",\ +"-0.3205,-0.3097,-0.2941,-0.2678,-0.2277,-0.1574,-0.0226"); + } + + fall_constraint("SIG2SRAM_constraint_template") { + index_1("0.0040,0.0176,0.0344,0.0656,0.1120,0.2016,0.3800"); + index_2("0.0040,0.0176,0.0344,0.0656,0.1120,0.2016,0.3800"); + values ("-0.2295,-0.2188,-0.2051,-0.1778,-0.1407,-0.0684,0.0615",\ +"-0.2334,-0.2227,-0.2090,-0.1817,-0.1445,-0.0723,0.0576",\ +"-0.2372,-0.2265,-0.2128,-0.1855,-0.1483,-0.0761,0.0538",\ +"-0.2405,-0.2297,-0.2160,-0.1887,-0.1516,-0.0793,0.0505",\ +"-0.2529,-0.2422,-0.2285,-0.2011,-0.1640,-0.0918,0.0381",\ +"-0.2704,-0.2596,-0.2460,-0.2186,-0.1815,-0.1092,0.0206",\ +"-0.2980,-0.2873,-0.2736,-0.2463,-0.2092,-0.1369,-0.0070"); + } + } + + timing() { + timing_type : hold_rising; + related_pin : "A_BIST_CLK"; + when : "(A_BIST_WEN & A_BIST_MEN)"; + sdf_cond : "A_BIST_W_ACCESS"; + + rise_constraint("SIG2SRAM_constraint_template") { + index_1("0.0040,0.0176,0.0344,0.0656,0.1120,0.2016,0.3800"); + index_2("0.0040,0.0176,0.0344,0.0656,0.1120,0.2016,0.3800"); + values ("0.3581,0.3463,0.3317,0.3053,0.2653,0.1940,0.0573",\ +"0.3619,0.3502,0.3356,0.3092,0.2692,0.1979,0.0612",\ +"0.3657,0.3540,0.3394,0.3130,0.2730,0.2017,0.0650",\ +"0.3690,0.3573,0.3426,0.3163,0.2762,0.2049,0.0682",\ +"0.3814,0.3697,0.3551,0.3287,0.2887,0.2174,0.0807",\ +"0.3989,0.3872,0.3725,0.3462,0.3061,0.2348,0.0981",\ +"0.4266,0.4148,0.4002,0.3738,0.3338,0.2625,0.1258"); + } + + fall_constraint("SIG2SRAM_constraint_template") { + index_1("0.0040,0.0176,0.0344,0.0656,0.1120,0.2016,0.3800"); + index_2("0.0040,0.0176,0.0344,0.0656,0.1120,0.2016,0.3800"); + values ("0.3297,0.3200,0.3053,0.2790,0.2418,0.1686,0.0407",\ +"0.3336,0.3239,0.3092,0.2828,0.2457,0.1725,0.0446",\ +"0.3374,0.3276,0.3130,0.2866,0.2495,0.1763,0.0484",\ +"0.3407,0.3309,0.3163,0.2899,0.2528,0.1795,0.0516",\ +"0.3531,0.3433,0.3287,0.3023,0.2652,0.1920,0.0641",\ +"0.3706,0.3608,0.3462,0.3198,0.2827,0.2094,0.0815",\ +"0.3982,0.3885,0.3738,0.3474,0.3103,0.2371,0.1092"); + } + } + } + +bus(A_DOUT) { + + bus_type : D_31_0; + direction : output ; + capacitance : 0 ; + max_capacitance : 0.064 ; + memory_read() { + address : A_ADDR ; + } + pin(A_DOUT[31:0]) { + related_power_pin : VDD; + related_ground_pin : VSS; + internal_power() { + rise_power("scalar") { + values (0); + } + fall_power("scalar") { + values (0); + } + } + } + timing() { + related_pin : "A_CLK"; + timing_type : rising_edge ; + timing_sense : non_unate ; + + cell_rise(SIG2SRAM_delay_template) { + index_1("0.0040,0.0176,0.0344,0.0656,0.1120,0.2016,0.3800"); + index_2("0.0008,0.0014,0.0051,0.0100,0.0339,0.0640"); + values ("2.6628,2.6638,2.6687,2.6742,2.6951,2.7186",\ +"2.6700,2.6711,2.6759,2.6814,2.7023,2.7258",\ +"2.6715,2.6725,2.6773,2.6829,2.7038,2.7273",\ +"2.6749,2.6759,2.6807,2.6862,2.7071,2.7306",\ +"2.6877,2.6887,2.6935,2.6990,2.7199,2.7434",\ +"2.7054,2.7065,2.7113,2.7168,2.7377,2.7612",\ +"2.7308,2.7318,2.7367,2.7422,2.7631,2.7866"); + } + cell_fall(SIG2SRAM_delay_template) { + index_1("0.0040,0.0176,0.0344,0.0656,0.1120,0.2016,0.3800"); + index_2("0.0008,0.0014,0.0051,0.0100,0.0339,0.0640"); + values ("2.6285,2.6294,2.6334,2.6380,2.6551,2.6718",\ +"2.6358,2.6366,2.6407,2.6452,2.6623,2.6790",\ +"2.6372,2.6381,2.6421,2.6467,2.6638,2.6805",\ +"2.6406,2.6414,2.6455,2.6500,2.6671,2.6838",\ +"2.6534,2.6542,2.6583,2.6628,2.6799,2.6966",\ +"2.6712,2.6720,2.6761,2.6806,2.6977,2.7144",\ +"2.6965,2.6974,2.7014,2.7060,2.7231,2.7398"); + } + + rise_transition(SRAM_load_template) { + index_1("0.0008,0.0014,0.0051,0.0100,0.0339,0.0640"); + values ("0.0206,0.0210,0.0265,0.0323,0.0606,0.0955"); + } + fall_transition(SRAM_load_template) { + index_1("0.0008,0.0014,0.0051,0.0100,0.0339,0.0640"); + values ("0.0170,0.0177,0.0222,0.0270,0.0451,0.0644"); + } + } +} +cell_leakage_power : 939.1882; +} +} diff --git a/flow/platforms/ihp-sg13g2/lib/RM_IHPSG13_1P_1024x32_c2_bm_bist_slow_1p08V_125C.lib b/flow/platforms/ihp-sg13g2/lib/RM_IHPSG13_1P_1024x32_c2_bm_bist_slow_1p08V_125C.lib new file mode 100644 index 0000000000..44897ec041 --- /dev/null +++ b/flow/platforms/ihp-sg13g2/lib/RM_IHPSG13_1P_1024x32_c2_bm_bist_slow_1p08V_125C.lib @@ -0,0 +1,1525 @@ +/* ------------------------------------------------------*/ +/**/ +/* Copyright 2025 IHP PDK Authors*/ +/**/ +/* Licensed under the Apache License, Version 2.0 (the "License");*/ +/* you may not use this file except in compliance with the License.*/ +/* You may obtain a copy of the License at*/ +/* */ +/* https://www.apache.org/licenses/LICENSE-2.0*/ +/* */ +/* Unless required by applicable law or agreed to in writing, software*/ +/* distributed under the License is distributed on an "AS IS" BASIS,*/ +/* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.*/ +/* See the License for the specific language governing permissions and*/ +/* limitations under the License.*/ +/* */ +/* Generated on Thu Aug 21 20:48:23 2025 */ +/* */ +/* ------------------------------------------------------ */ +library(RM_IHPSG13_1P_1024x32_c2_bm_bist_slow_1p08V_125C) { + technology (cmos) ; + delay_model : table_lookup ; + define ("add_pg_pin_to_lib", "library", "boolean"); + add_pg_pin_to_lib : true; + voltage_map ( VDD, 1.08); + voltage_map ( VDDARRAY, 1.08); + voltage_map ( VSS, 0.000000 ); + + date : "Thu Aug 21 20:48:22 2025" ; + comment : "IHP Microelectronics GmbH, 2023" ; + revision : 1.0.0 ; + simulation : true ; + nom_process : 1 ; + nom_temperature : 125 ; + nom_voltage : 1.08 ; + + operating_conditions("slow_1p08V_125C"){ + process : 1 ; + temperature : 125 ; + voltage : 1.08 ; + tree_type : "balanced_tree" ; + } + + default_operating_conditions : slow_1p08V_125C ; + default_max_transition : 1.0 ; + default_fanout_load : 1.0 ; + default_inout_pin_cap : 0.0 ; + default_input_pin_cap : 0.0 ; + default_output_pin_cap : 0.0 ; + default_cell_leakage_power : 0.0 ; + default_leakage_power_density : 0.0 ; + + slew_lower_threshold_pct_rise : 30 ; + slew_upper_threshold_pct_rise : 70 ; + input_threshold_pct_fall : 50 ; + output_threshold_pct_fall : 50 ; + input_threshold_pct_rise : 50 ; + output_threshold_pct_rise : 50 ; + slew_lower_threshold_pct_fall : 30 ; + slew_upper_threshold_pct_fall : 70 ; + slew_derate_from_library : 0.5; + k_volt_cell_leakage_power : 0.0 ; + k_temp_cell_leakage_power : 0.0 ; + k_process_cell_leakage_power : 0.0 ; + k_volt_internal_power : 0.0 ; + k_temp_internal_power : 0.0 ; + k_process_internal_power : 0.0 ; + + capacitive_load_unit (1,pf) ; + voltage_unit : "1V" ; + current_unit : "1uA" ; + time_unit : "1ns" ; + leakage_power_unit : "1nW" ; + pulling_resistance_unit : "1kohm"; + /* + ------------------------------------------------------------------------------------------ + implicit units overview: + cell_area unit : "um" + internal_power unit : "1e-12 * J/toggle = 1 * uW/MHz" + (capacitive_load_unit * voltage_unit^2) per toggle event + ------------------------------------------------------------------------------------------ + */ + library_features(report_delay_calculation); + define_cell_area (pad_drivers,pad_driver_sites) ; + + lu_table_template(CLKTRAN_constraint_template) { + variable_1 : constrained_pin_transition; + index_1 ( "0.010, 0.050, 0.200, 0.400, 1.000" ); + } + lu_table_template(SRAM_load_template) { + variable_1 : total_output_net_capacitance; + index_1 ( "0.0008,0.0014,0.0051,0.0100,0.0339,0.0640" ); + } + lu_table_template(SIG2SRAM_constraint_template) { + variable_1 : related_pin_transition; + variable_2 : constrained_pin_transition; + index_1 ( "0.0080,0.0288,0.0616,0.1072,0.1920,0.3496,0.5952" ); + index_2 ( "0.0080,0.0288,0.0616,0.1072,0.1920,0.3496,0.5952" ); + } + + lu_table_template(SIG2SRAM_delay_template) { + variable_1 : input_net_transition; + variable_2 : total_output_net_capacitance; + index_1 ( "0.0080,0.0288,0.0616,0.1072,0.1920,0.3496,0.5952" ); + index_2 ( "0.0008,0.0014,0.0051,0.0100,0.0339,0.0640" ); + } + + type (D_31_0) { + base_type : array; + data_type : bit; + bit_width : 32; + bit_from : 31; + bit_to : 0; + downto : true; + } + + type (A_9_0) { + base_type : array; + data_type : bit; + bit_width : 10; + bit_from : 9; + bit_to : 0; + downto : true; + } + +cell(RM_IHPSG13_1P_1024x32_c2_bm_bist) { +pg_pin (VDD) { + pg_type : primary_power; + voltage_name : VDD; +} +pg_pin (VDDARRAY) { + pg_type : primary_power; + voltage_name : VDDARRAY; +} +pg_pin (VSS) { + pg_type : primary_ground; + voltage_name : VSS; +} + +memory() { + type : ram; + address_width : 10; + word_width : 32; +} + +interface_timing : false; +bus_naming_style : "%s[%d]" ; +area : 140182.6944 ; + + pin(A_DLY) { + direction : input ; + capacitance : 0.00387999 ; + max_transition : "1" ; + related_power_pin : VDD; + related_ground_pin : VSS; + internal_power() { + rise_power("scalar") { + values (0); + } + fall_power("scalar") { + values (0); + } + } + } + +bus(A_ADDR) { + bus_type : A_9_0; + direction : input ; + capacitance : 0.0077013 ; + pin(A_ADDR[0]) { + capacitance : 0.00625349 ; + } + pin(A_ADDR[1]) { + capacitance : 0.00507435 ; + } + pin(A_ADDR[2]) { + capacitance : 0.00656707 ; + } + pin(A_ADDR[3]) { + capacitance : 0.0083133 ; + } + pin(A_ADDR[4]) { + capacitance : 0.00507219 ; + } + pin(A_ADDR[5]) { + capacitance : 0.00964344 ; + } + pin(A_ADDR[6]) { + capacitance : 0.0119653 ; + } + pin(A_ADDR[7]) { + capacitance : 0.00827606 ; + } + pin(A_ADDR[8]) { + capacitance : 0.0110771 ; + } + max_transition : "0.5952" ; + pin(A_ADDR[9:0]) { + related_power_pin : VDD; + related_ground_pin : VSS; + internal_power() { + when : "A_MEN"; + rise_power("scalar"){ + values (0.0195); + } + fall_power("scalar"){ + values (0.0388); + } + } + internal_power() { + when : "!A_MEN"; + rise_power("scalar"){ + values (0.0129); + } + fall_power("scalar"){ + values (0.0238); + } + } + } + timing() { + timing_type : setup_rising; + related_pin : "A_CLK"; + when : "((A_WEN | A_REN)& A_MEN)" + sdf_cond : "A_RW_ACCESS" + + rise_constraint("SIG2SRAM_constraint_template") { + index_1("0.0080,0.0288,0.0616,0.1072,0.1920,0.3496,0.5952"); + index_2("0.0080,0.0288,0.0616,0.1072,0.1920,0.3496,0.5952"); + values ("-0.7371,-0.7176,-0.6863,-0.6434,-0.5652,-0.4168,-0.1980",\ +"-0.7566,-0.7371,-0.7059,-0.6629,-0.5848,-0.4363,-0.2137",\ +"-0.7879,-0.7645,-0.7332,-0.6902,-0.6121,-0.4637,-0.2449",\ +"-0.8309,-0.8074,-0.7762,-0.7332,-0.6551,-0.5066,-0.2879",\ +"-0.9051,-0.8895,-0.8543,-0.8113,-0.7332,-0.5887,-0.3660",\ +"-1.0418,-1.0262,-0.9949,-0.9480,-0.8699,-0.7293,-0.5027",\ +"-1.2684,-1.2449,-1.2176,-1.1707,-1.0965,-0.9480,-0.7293"); + } + + fall_constraint("SIG2SRAM_constraint_template") { + index_1("0.0080,0.0288,0.0616,0.1072,0.1920,0.3496,0.5952"); + index_2("0.0080,0.0288,0.0616,0.1072,0.1920,0.3496,0.5952"); + values ("-0.5926,-0.5730,-0.5418,-0.4988,-0.4246,-0.2879,-0.0730",\ +"-0.6121,-0.5926,-0.5613,-0.5223,-0.4441,-0.3074,-0.0887",\ +"-0.6395,-0.6199,-0.5926,-0.5496,-0.4715,-0.3348,-0.1160",\ +"-0.6863,-0.6668,-0.6355,-0.5965,-0.5184,-0.3777,-0.1590",\ +"-0.7605,-0.7410,-0.7137,-0.6746,-0.5926,-0.4559,-0.2410",\ +"-0.9012,-0.8816,-0.8504,-0.8113,-0.7332,-0.5926,-0.3895",\ +"-1.1238,-1.1043,-1.0769,-1.0379,-0.9559,-0.8191,-0.6004"); + } + } + + + timing() { + timing_type : hold_rising; + related_pin : "A_CLK"; + when : "((A_WEN | A_REN)& A_MEN)" + sdf_cond : "A_RW_ACCESS" + + rise_constraint("SIG2SRAM_constraint_template") { + index_1("0.0080,0.0288,0.0616,0.1072,0.1920,0.3496,0.5952"); + index_2("0.0080,0.0288,0.0616,0.1072,0.1920,0.3496,0.5952"); + values ("0.8488,0.8293,0.7980,0.7551,0.6730,0.5285,0.3098",\ +"0.8684,0.8488,0.8176,0.7746,0.6926,0.5480,0.3254",\ +"0.8996,0.8801,0.8449,0.8020,0.7238,0.5754,0.3527",\ +"0.9426,0.9191,0.8918,0.8488,0.7668,0.6223,0.3996",\ +"1.0168,1.0012,0.9699,0.9230,0.8449,0.7004,0.4777",\ +"1.1574,1.1379,1.1105,1.0598,0.9816,0.8371,0.6184",\ +"1.3801,1.3605,1.3254,1.2980,1.2043,1.0637,0.8371"); + } + + fall_constraint("SIG2SRAM_constraint_template") { + index_1("0.0080,0.0288,0.0616,0.1072,0.1920,0.3496,0.5952"); + index_2("0.0080,0.0288,0.0616,0.1072,0.1920,0.3496,0.5952"); + values ("0.6965,0.6770,0.6496,0.6066,0.5246,0.3918,0.1730",\ +"0.7160,0.6965,0.6652,0.6262,0.5441,0.4113,0.1965",\ +"0.7473,0.7277,0.6965,0.6535,0.5754,0.4426,0.2238",\ +"0.7863,0.7707,0.7395,0.7004,0.6223,0.4855,0.2629",\ +"0.8684,0.8449,0.8176,0.7785,0.7004,0.5637,0.3449",\ +"1.0051,0.9855,0.9855,0.9113,0.8332,0.7004,0.4895",\ +"1.2277,1.2082,1.1809,1.1379,1.0598,0.9230,0.7004"); + } + } +} +pin(A_WEN) { + direction : input ; + capacitance : 0.00313551 ; + max_transition : "0.5952" ; + related_power_pin : VDD; + related_ground_pin : VSS; + internal_power() { + when : "A_MEN"; + rise_power("scalar"){ + values (0.0268); + } + fall_power("scalar"){ + values (0.0213); + } + } + internal_power() { + when : "!A_MEN"; + rise_power("scalar"){ + values (0.0484); + } + fall_power("scalar"){ + values (0.0885); + } + } + timing() { + timing_type : setup_rising; + related_pin : "A_CLK"; + when : "A_MEN" + sdf_cond : "A_MEN" + + rise_constraint("SIG2SRAM_constraint_template") { + index_1("0.0080,0.0288,0.0616,0.1072,0.1920,0.3496,0.5952"); + index_2("0.0080,0.0288,0.0616,0.1072,0.1920,0.3496,0.5952"); + values ("0.3137,0.3332,0.3605,0.4035,0.4816,0.6223,0.8488",\ +"0.2980,0.3176,0.3410,0.3840,0.4660,0.6027,0.8293",\ +"0.2629,0.2824,0.3098,0.3527,0.4348,0.5754,0.7980",\ +"0.2199,0.2395,0.2668,0.3098,0.3918,0.5324,0.7590",\ +"0.1418,0.1613,0.1887,0.2316,0.3137,0.4348,0.6730",\ +"0.0012,0.0207,0.0520,0.0910,0.1730,0.3098,0.5285",\ +"-0.2215,-0.2020,-0.1746,-0.1277,-0.0496,0.0910,0.3098"); + } + + fall_constraint("SIG2SRAM_constraint_template") { + index_1("0.0080,0.0288,0.0616,0.1072,0.1920,0.3496,0.5952"); + index_2("0.0080,0.0288,0.0616,0.1072,0.1920,0.3496,0.5952"); + values ("0.4504,0.4699,0.4973,0.5324,0.6027,0.7355,0.9699",\ +"0.4309,0.4504,0.4777,0.5129,0.5910,0.7160,0.9504",\ +"0.3996,0.4191,0.4465,0.4816,0.5520,0.6848,0.9191",\ +"0.3605,0.3762,0.4035,0.4387,0.5168,0.6418,0.8723",\ +"0.2785,0.2980,0.3215,0.3605,0.4348,0.5637,0.7980",\ +"0.1379,0.1574,0.1809,0.2199,0.2980,0.4309,0.6457",\ +"-0.0809,-0.0613,-0.0340,0.0051,0.0832,0.2160,0.4191"); + } + } + + + timing() { + timing_type : hold_rising; + related_pin : "A_CLK"; + when : "A_MEN" + sdf_cond : "A_MEN" + + rise_constraint("SIG2SRAM_constraint_template") { + index_1("0.0080,0.0288,0.0616,0.1072,0.1920,0.3496,0.5952"); + index_2("0.0080,0.0288,0.0616,0.1072,0.1920,0.3496,0.5952"); + values ("0.3723,0.3527,0.3215,0.2785,0.1965,0.0559,-0.1668",\ +"0.3918,0.3723,0.3449,0.2980,0.2160,0.0754,-0.1473",\ +"0.4152,0.3996,0.3684,0.3254,0.2434,0.1066,-0.1199",\ +"0.4621,0.4465,0.4152,0.3723,0.2863,0.1496,-0.0730",\ +"0.5324,0.5207,0.4895,0.4465,0.3645,0.2199,0.0051",\ +"0.6770,0.6535,0.6301,0.5832,0.5090,0.3605,0.1418",\ +"0.9035,0.8879,0.8566,0.8137,0.7316,0.5871,0.3684"); + } + + fall_constraint("SIG2SRAM_constraint_template") { + index_1("0.0080,0.0288,0.0616,0.1072,0.1920,0.3496,0.5952"); + index_2("0.0080,0.0288,0.0616,0.1072,0.1920,0.3496,0.5952"); + values ("0.3762,0.3566,0.3293,0.2863,0.2043,0.0676,-0.1434",\ +"0.3957,0.3762,0.3488,0.3059,0.2238,0.0871,-0.1199",\ +"0.4230,0.4035,0.3723,0.3332,0.2512,0.1184,-0.0965",\ +"0.4660,0.4465,0.4191,0.3762,0.2941,0.1613,-0.0496",\ +"0.5324,0.5168,0.4973,0.4543,0.3723,0.2316,0.0285",\ +"0.6809,0.6613,0.6340,0.5910,0.5129,0.3645,0.1652",\ +"0.9113,0.8918,0.8605,0.8176,0.7395,0.5988,0.3879"); + } + } + } +pin(A_REN) { + direction : input ; + capacitance : 0.00381144 ; + max_transition : "0.5952" ; + related_power_pin : VDD; + related_ground_pin : VSS; + internal_power() { + when : "A_MEN"; + rise_power("scalar"){ + values (0.0263); + } + fall_power("scalar"){ + values (0.0112); + } + } + internal_power() { + when : "!A_MEN"; + rise_power("scalar"){ + values (0.0042); + } + fall_power("scalar"){ + values (0.0039); + } + } + timing() { + timing_type : setup_rising; + related_pin : "A_CLK"; + when : "A_MEN" + sdf_cond : "A_MEN" + + rise_constraint("SIG2SRAM_constraint_template") { + index_1("0.0080,0.0288,0.0616,0.1072,0.1920,0.3496,0.5952"); + index_2("0.0080,0.0288,0.0616,0.1072,0.1920,0.3496,0.5952"); + values ("-0.0770,-0.0574,-0.0262,0.0168,0.0949,0.2355,0.4582",\ +"-0.0965,-0.0770,-0.0457,-0.0027,0.0754,0.2160,0.4387",\ +"-0.1199,-0.1004,-0.0730,-0.0262,0.0520,0.1887,0.4113",\ +"-0.1590,-0.1434,-0.1160,-0.0730,0.0051,0.1457,0.3645",\ +"-0.2449,-0.2254,-0.1941,-0.1473,-0.0770,0.0676,0.2863",\ +"-0.3816,-0.3699,-0.3387,-0.2801,-0.2215,-0.0770,0.1457",\ +"-0.6121,-0.5926,-0.5613,-0.5145,-0.4363,-0.2996,-0.0730"); + } + + fall_constraint("SIG2SRAM_constraint_template") { + index_1("0.0080,0.0288,0.0616,0.1072,0.1920,0.3496,0.5952"); + index_2("0.0080,0.0288,0.0616,0.1072,0.1920,0.3496,0.5952"); + values ("0.1262,0.1457,0.1691,0.2121,0.2824,0.4191,0.6457",\ +"0.1105,0.1262,0.1496,0.1887,0.2629,0.3996,0.6262",\ +"0.0793,0.0949,0.1223,0.1652,0.2395,0.3684,0.5949",\ +"0.0363,0.0559,0.0793,0.1223,0.2004,0.3410,0.5520",\ +"-0.0457,-0.0262,0.0012,0.0441,0.1301,0.2629,0.4738",\ +"-0.1902,-0.1746,-0.1434,-0.1043,-0.0184,0.1223,0.3332",\ +"-0.4129,-0.3934,-0.3660,-0.3230,-0.2449,-0.1043,0.1105"); + } + } + + + timing() { + timing_type : hold_rising; + related_pin : "A_CLK"; + when : "A_MEN" + sdf_cond : "A_MEN" + + rise_constraint("SIG2SRAM_constraint_template") { + index_1("0.0080,0.0288,0.0616,0.1072,0.1920,0.3496,0.5952"); + index_2("0.0080,0.0288,0.0616,0.1072,0.1920,0.3496,0.5952"); + values ("0.4113,0.3918,0.3645,0.3176,0.2395,0.0988,-0.1238",\ +"0.4309,0.4113,0.3840,0.3371,0.2590,0.1184,-0.1043",\ +"0.4582,0.4387,0.4113,0.3645,0.2824,0.1457,-0.0770",\ +"0.5051,0.4816,0.4543,0.4074,0.3293,0.1887,-0.0340",\ +"0.5715,0.5598,0.5324,0.4895,0.4035,0.2512,0.0441",\ +"0.7043,0.7004,0.6730,0.6262,0.5402,0.3957,0.1809",\ +"0.9387,0.9270,0.8957,0.8527,0.7746,0.6262,0.4074"); + } + + fall_constraint("SIG2SRAM_constraint_template") { + index_1("0.0080,0.0288,0.0616,0.1072,0.1920,0.3496,0.5952"); + index_2("0.0080,0.0288,0.0616,0.1072,0.1920,0.3496,0.5952"); + values ("0.4152,0.3918,0.3645,0.3215,0.2395,0.1027,-0.1082",\ +"0.4309,0.4113,0.3801,0.3410,0.2590,0.1223,-0.0926",\ +"0.4582,0.4387,0.4074,0.3684,0.2863,0.1496,-0.0613",\ +"0.5012,0.4816,0.4504,0.4074,0.3293,0.1887,-0.0145",\ +"0.5715,0.5559,0.5285,0.4816,0.3996,0.2512,0.0598",\ +"0.7160,0.7004,0.6691,0.6262,0.5520,0.4035,0.2004",\ +"0.9387,0.9191,0.8957,0.8488,0.7707,0.6262,0.4113"); + } + } + } +pin(A_MEN) { + direction : input ; + capacitance : 0.00300347 ; + max_transition : "0.5952" ; + related_power_pin : VDD; + related_ground_pin : VSS; + internal_power() { + rise_power("scalar"){ + values (0.0005); + } + fall_power("scalar"){ + values (0.0301); + } + } + timing() { + timing_type : setup_rising; + related_pin : "A_CLK"; + + rise_constraint("SIG2SRAM_constraint_template") { + index_1("0.0080,0.0288,0.0616,0.1072,0.1920,0.3496,0.5952"); + index_2("0.0080,0.0288,0.0616,0.1072,0.1920,0.3496,0.5952"); + values ("0.3215,0.3449,0.3684,0.4113,0.4895,0.6301,0.8527",\ +"0.3059,0.3254,0.3527,0.3957,0.4738,0.6145,0.8371",\ +"0.2746,0.2941,0.3215,0.3645,0.4426,0.5871,0.8059",\ +"0.2316,0.2512,0.2785,0.3215,0.3996,0.5402,0.7629",\ +"0.1496,0.1730,0.1965,0.2395,0.3215,0.4660,0.6848",\ +"0.0090,0.0285,0.0598,0.1027,0.1809,0.3176,0.5402",\ +"-0.2098,-0.1902,-0.1668,-0.1199,-0.0418,0.0988,0.3137"); + } + + fall_constraint("SIG2SRAM_constraint_template") { + index_1("0.0080,0.0288,0.0616,0.1072,0.1920,0.3496,0.5952"); + index_2("0.0080,0.0288,0.0616,0.1072,0.1920,0.3496,0.5952"); + values ("0.4582,0.4738,0.5012,0.5363,0.6145,0.7395,0.9738",\ +"0.4387,0.4543,0.4816,0.5207,0.5910,0.7199,0.9582",\ +"0.4035,0.4230,0.4504,0.4855,0.5637,0.6887,0.9230",\ +"0.3645,0.3840,0.4074,0.4465,0.5285,0.6496,0.8840",\ +"0.2824,0.3020,0.3254,0.3645,0.4465,0.5715,0.7980",\ +"0.1418,0.1613,0.1887,0.2238,0.3020,0.4309,0.6496",\ +"-0.0770,-0.0574,-0.0301,0.0090,0.0910,0.2238,0.4191"); + } + } + + + timing() { + timing_type : hold_rising; + related_pin : "A_CLK"; + + rise_constraint("SIG2SRAM_constraint_template") { + index_1("0.0080,0.0288,0.0616,0.1072,0.1920,0.3496,0.5952"); + index_2("0.0080,0.0288,0.0616,0.1072,0.1920,0.3496,0.5952"); + values ("0.3762,0.3605,0.3293,0.2863,0.2043,0.0637,-0.1629",\ +"0.3996,0.3801,0.3488,0.3020,0.2238,0.0832,-0.1395",\ +"0.4230,0.4074,0.3723,0.3293,0.2473,0.1105,-0.1121",\ +"0.4621,0.4465,0.4152,0.3762,0.2941,0.1535,-0.0691",\ +"0.5441,0.5285,0.4973,0.4465,0.3684,0.2316,0.0090",\ +"0.6848,0.6652,0.6301,0.5910,0.5129,0.3605,0.1496",\ +"0.9074,0.8918,0.8566,0.8215,0.7395,0.5910,0.3723"); + } + + fall_constraint("SIG2SRAM_constraint_template") { + index_1("0.0080,0.0288,0.0616,0.1072,0.1920,0.3496,0.5952"); + index_2("0.0080,0.0288,0.0616,0.1072,0.1920,0.3496,0.5952"); + values ("0.3762,0.3605,0.3332,0.2863,0.2043,0.0715,-0.1395",\ +"0.3996,0.3762,0.3488,0.3059,0.2238,0.0910,-0.1199",\ +"0.4270,0.4035,0.3762,0.3332,0.2512,0.1184,-0.0965",\ +"0.4699,0.4504,0.4191,0.3762,0.2941,0.1613,-0.0496",\ +"0.5441,0.5285,0.4973,0.4543,0.3762,0.2355,0.0324",\ +"0.6770,0.6613,0.6340,0.5949,0.5207,0.3762,0.1652",\ +"0.9074,0.8918,0.8605,0.8176,0.7395,0.6027,0.3918"); + } + } + } +bus(A_BM) { + bus_type : D_31_0; + direction : input ; + capacitance : 0.00263802 ; + max_transition : "0.5952" ; + pin(A_BM[31:0]) { + related_power_pin : VDD; + related_ground_pin : VSS; + internal_power() { + when : "A_MEN"; + rise_power("scalar"){ + values (0.0632); + } + fall_power("scalar"){ + values (0.0448); + } + } + internal_power() { + when : "!A_MEN"; + rise_power("scalar"){ + values (0.0895); + } + fall_power("scalar"){ + values (0.0291); + } + } + } + timing() { + timing_type : setup_rising; + related_pin : "A_CLK"; + when : "(A_WEN & A_MEN)" + sdf_cond : "A_RW_ACCESS" + + rise_constraint("SIG2SRAM_constraint_template") { + index_1("0.0080,0.0288,0.0616,0.1072,0.1920,0.3496,0.5952"); + index_2("0.0080,0.0288,0.0616,0.1072,0.1920,0.3496,0.5952"); + values ("-0.7914,-0.7719,-0.7455,-0.7035,-0.6224,-0.4779,-0.2572",\ +"-0.7994,-0.7799,-0.7535,-0.7115,-0.6305,-0.4859,-0.2652",\ +"-0.8084,-0.7889,-0.7625,-0.7205,-0.6395,-0.4950,-0.2742",\ +"-0.8216,-0.8020,-0.7757,-0.7337,-0.6526,-0.5081,-0.2874",\ +"-0.8459,-0.8263,-0.8000,-0.7580,-0.6769,-0.5324,-0.3117",\ +"-0.8764,-0.8568,-0.8305,-0.7885,-0.7074,-0.5629,-0.3422",\ +"-0.9578,-0.9383,-0.9119,-0.8699,-0.7889,-0.6443,-0.4236"); + } + + fall_constraint("SIG2SRAM_constraint_template") { + index_1("0.0080,0.0288,0.0616,0.1072,0.1920,0.3496,0.5952"); + index_2("0.0080,0.0288,0.0616,0.1072,0.1920,0.3496,0.5952"); + values ("-0.7357,-0.7201,-0.6918,-0.6527,-0.5717,-0.4340,-0.2221",\ +"-0.7438,-0.7281,-0.6998,-0.6607,-0.5797,-0.4420,-0.2301",\ +"-0.7528,-0.7371,-0.7088,-0.6698,-0.5887,-0.4510,-0.2391",\ +"-0.7659,-0.7503,-0.7220,-0.6829,-0.6019,-0.4642,-0.2523",\ +"-0.7902,-0.7746,-0.7462,-0.7072,-0.6261,-0.4884,-0.2765",\ +"-0.8207,-0.8051,-0.7768,-0.7377,-0.6566,-0.5190,-0.3070",\ +"-0.9022,-0.8865,-0.8582,-0.8191,-0.7381,-0.6004,-0.3885"); + } + } + + + timing() { + timing_type : hold_rising; + related_pin : "A_CLK"; + when : "(A_WEN & A_MEN)" + sdf_cond : "A_RW_ACCESS" + + rise_constraint("SIG2SRAM_constraint_template") { + index_1("0.0080,0.0288,0.0616,0.1072,0.1920,0.3496,0.5952"); + index_2("0.0080,0.0288,0.0616,0.1072,0.1920,0.3496,0.5952"); + values ("0.9084,0.8869,0.8605,0.8176,0.7385,0.5930,0.3674",\ +"0.9164,0.8949,0.8686,0.8256,0.7465,0.6010,0.3754",\ +"0.9254,0.9039,0.8776,0.8346,0.7555,0.6100,0.3844",\ +"0.9386,0.9171,0.8907,0.8478,0.7687,0.6232,0.3976",\ +"0.9629,0.9414,0.9150,0.8720,0.7929,0.6474,0.4218",\ +"0.9934,0.9719,0.9455,0.9025,0.8234,0.6779,0.4524",\ +"1.0748,1.0533,1.0270,0.9840,0.9049,0.7594,0.5338"); + } + + fall_constraint("SIG2SRAM_constraint_template") { + index_1("0.0080,0.0288,0.0616,0.1072,0.1920,0.3496,0.5952"); + index_2("0.0080,0.0288,0.0616,0.1072,0.1920,0.3496,0.5952"); + values ("0.8400,0.8234,0.7951,0.7512,0.6740,0.5363,0.3264",\ +"0.8481,0.8315,0.8031,0.7592,0.6820,0.5443,0.3344",\ +"0.8571,0.8405,0.8121,0.7682,0.6910,0.5534,0.3434",\ +"0.8702,0.8536,0.8253,0.7814,0.7042,0.5665,0.3565",\ +"0.8945,0.8779,0.8496,0.8056,0.7285,0.5908,0.3808",\ +"0.9250,0.9084,0.8801,0.8361,0.7590,0.6213,0.4113",\ +"1.0065,0.9899,0.9615,0.9176,0.8404,0.7028,0.4928"); + } + } +} + pin(A_CLK) { + direction : input; + capacitance : 0.00378957; + max_transition : "0.5952"; + clock : "true" ; + pin_func_type : active_rising ; + + timing () { + timing_type : "min_pulse_width"; + related_pin : "A_CLK"; + rise_constraint("CLKTRAN_constraint_template") { + index_1("0.008,0.5952"); + values("0.4,0.4"); + } + } + + related_power_pin : VDD; + related_ground_pin : VSS; + + internal_power() { + when : "!A_MEN & !A_WEN & !A_REN"; + rise_power("scalar"){ + values (0); + } + fall_power("scalar"){ + values (0); + } + } + internal_power() { + when : "!A_MEN & A_WEN & !A_REN"; + rise_power("scalar"){ + values (0.6568); + } + fall_power("scalar"){ + values (0); + } + } + internal_power() { + when : "A_MEN & A_WEN & !A_REN"; + rise_power("scalar"){ + values (46.0330); + } + fall_power("scalar"){ + values (0); + } + } + internal_power() { + when : "A_MEN & A_WEN & A_REN"; + rise_power("scalar"){ + values (49.3119); + } + fall_power("scalar"){ + values (0); + } + } + internal_power() { + when : "A_MEN & !A_WEN & A_REN"; + rise_power("scalar"){ + values (36.0779); + } + fall_power("scalar"){ + values (0); + } + } + internal_power() { + when : "!A_MEN & !A_WEN & A_REN"; + rise_power("scalar"){ + values (0.4418); + } + fall_power("scalar"){ + values (0); + } + } + internal_power() { + when : "!A_MEN & A_WEN & A_REN"; + rise_power("scalar"){ + values (1.1609); + } + fall_power("scalar"){ + values (0); + } + } + internal_power() { + when : "A_MEN & !A_WEN & !A_REN"; + rise_power("scalar"){ + values (0); + } + fall_power("scalar"){ + values (0); + } + } + } + bus(A_DIN) { + bus_type : D_31_0; + direction : input ; + capacitance : 0.00358485 ; + memory_write() { + address : A_ADDR ; + clocked_on : A_CLK; + } + + max_transition : "0.5952" ; + pin(A_DIN[31:0]) { + related_power_pin : VDD; + related_ground_pin : VSS; + internal_power() { + when : "A_MEN"; + rise_power("scalar"){ + values (0.0632); + } + fall_power("scalar"){ + values (0.0448); + } + } + internal_power() { + when : "!A_MEN"; + rise_power("scalar"){ + values (0.0895); + } + fall_power("scalar"){ + values (0.0291); + } + } + } + timing() { + timing_type : setup_rising; + related_pin : "A_CLK"; + when : "(A_WEN & A_MEN)"; + sdf_cond : "A_W_ACCESS"; + + rise_constraint("SIG2SRAM_constraint_template") { + index_1("0.0080,0.0288,0.0616,0.1072,0.1920,0.3496,0.5952"); + index_2("0.0080,0.0288,0.0616,0.1072,0.1920,0.3496,0.5952"); + values ("-0.7914,-0.7719,-0.7455,-0.7035,-0.6224,-0.4779,-0.2572",\ +"-0.7994,-0.7799,-0.7535,-0.7115,-0.6305,-0.4859,-0.2652",\ +"-0.8084,-0.7889,-0.7625,-0.7205,-0.6395,-0.4950,-0.2742",\ +"-0.8216,-0.8020,-0.7757,-0.7337,-0.6526,-0.5081,-0.2874",\ +"-0.8459,-0.8263,-0.8000,-0.7580,-0.6769,-0.5324,-0.3117",\ +"-0.8764,-0.8568,-0.8305,-0.7885,-0.7074,-0.5629,-0.3422",\ +"-0.9578,-0.9383,-0.9119,-0.8699,-0.7889,-0.6443,-0.4236"); + } + + fall_constraint("SIG2SRAM_constraint_template") { + index_1("0.0080,0.0288,0.0616,0.1072,0.1920,0.3496,0.5952"); + index_2("0.0080,0.0288,0.0616,0.1072,0.1920,0.3496,0.5952"); + values ("-0.7357,-0.7201,-0.6918,-0.6527,-0.5717,-0.4340,-0.2221",\ +"-0.7438,-0.7281,-0.6998,-0.6607,-0.5797,-0.4420,-0.2301",\ +"-0.7528,-0.7371,-0.7088,-0.6698,-0.5887,-0.4510,-0.2391",\ +"-0.7659,-0.7503,-0.7220,-0.6829,-0.6019,-0.4642,-0.2523",\ +"-0.7902,-0.7746,-0.7462,-0.7072,-0.6261,-0.4884,-0.2765",\ +"-0.8207,-0.8051,-0.7768,-0.7377,-0.6566,-0.5190,-0.3070",\ +"-0.9022,-0.8865,-0.8582,-0.8191,-0.7381,-0.6004,-0.3885"); + } + } + + timing() { + timing_type : hold_rising; + related_pin : "A_CLK"; + when : "(A_WEN & A_MEN)"; + sdf_cond : "A_W_ACCESS"; + + rise_constraint("SIG2SRAM_constraint_template") { + index_1("0.0080,0.0288,0.0616,0.1072,0.1920,0.3496,0.5952"); + index_2("0.0080,0.0288,0.0616,0.1072,0.1920,0.3496,0.5952"); + values ("0.9084,0.8869,0.8605,0.8176,0.7385,0.5930,0.3674",\ +"0.9164,0.8949,0.8686,0.8256,0.7465,0.6010,0.3754",\ +"0.9254,0.9039,0.8776,0.8346,0.7555,0.6100,0.3844",\ +"0.9386,0.9171,0.8907,0.8478,0.7687,0.6232,0.3976",\ +"0.9629,0.9414,0.9150,0.8720,0.7929,0.6474,0.4218",\ +"0.9934,0.9719,0.9455,0.9025,0.8234,0.6779,0.4524",\ +"1.0748,1.0533,1.0270,0.9840,0.9049,0.7594,0.5338"); + } + + fall_constraint("SIG2SRAM_constraint_template") { + index_1("0.0080,0.0288,0.0616,0.1072,0.1920,0.3496,0.5952"); + index_2("0.0080,0.0288,0.0616,0.1072,0.1920,0.3496,0.5952"); + values ("0.8400,0.8234,0.7951,0.7512,0.6740,0.5363,0.3264",\ +"0.8481,0.8315,0.8031,0.7592,0.6820,0.5443,0.3344",\ +"0.8571,0.8405,0.8121,0.7682,0.6910,0.5534,0.3434",\ +"0.8702,0.8536,0.8253,0.7814,0.7042,0.5665,0.3565",\ +"0.8945,0.8779,0.8496,0.8056,0.7285,0.5908,0.3808",\ +"0.9250,0.9084,0.8801,0.8361,0.7590,0.6213,0.4113",\ +"1.0065,0.9899,0.9615,0.9176,0.8404,0.7028,0.4928"); + } + } + } + + pin(A_BIST_EN) { + direction : input ; + capacitance : 0.00387999 ; + max_transition : "1" ; + related_power_pin : VDD; + related_ground_pin : VSS; + internal_power() { + rise_power("scalar") { + values (0); + } + fall_power("scalar") { + values (0); + } + } + } + +bus(A_BIST_ADDR) { + bus_type : A_9_0; + direction : input ; + capacitance : 0.0077013 ; + pin(A_BIST_ADDR[0]) { + capacitance : 0.00625349 ; + } + pin(A_BIST_ADDR[1]) { + capacitance : 0.00507435 ; + } + pin(A_BIST_ADDR[2]) { + capacitance : 0.00656707 ; + } + pin(A_BIST_ADDR[3]) { + capacitance : 0.0083133 ; + } + pin(A_BIST_ADDR[4]) { + capacitance : 0.00507219 ; + } + pin(A_BIST_ADDR[5]) { + capacitance : 0.00964344 ; + } + pin(A_BIST_ADDR[6]) { + capacitance : 0.0119653 ; + } + pin(A_BIST_ADDR[7]) { + capacitance : 0.00827606 ; + } + pin(A_BIST_ADDR[8]) { + capacitance : 0.0110771 ; + } + max_transition : "0.5952" ; + pin(A_BIST_ADDR[9:0]) { + related_power_pin : VDD; + related_ground_pin : VSS; + internal_power() { + when : "A_BIST_MEN"; + rise_power("scalar"){ + values (0.0195); + } + fall_power("scalar"){ + values (0.0388); + } + } + internal_power() { + when : "!A_BIST_MEN"; + rise_power("scalar"){ + values (0.0129); + } + fall_power("scalar"){ + values (0.0238); + } + } + } + timing() { + timing_type : setup_rising; + related_pin : "A_BIST_CLK"; + when : "((A_BIST_WEN | A_BIST_REN)& A_BIST_MEN)" + sdf_cond : "A_BIST_RW_ACCESS" + + rise_constraint("SIG2SRAM_constraint_template") { + index_1("0.0080,0.0288,0.0616,0.1072,0.1920,0.3496,0.5952"); + index_2("0.0080,0.0288,0.0616,0.1072,0.1920,0.3496,0.5952"); + values ("-0.7371,-0.7176,-0.6863,-0.6434,-0.5652,-0.4168,-0.1980",\ +"-0.7566,-0.7371,-0.7059,-0.6629,-0.5848,-0.4363,-0.2137",\ +"-0.7879,-0.7645,-0.7332,-0.6902,-0.6121,-0.4637,-0.2449",\ +"-0.8309,-0.8074,-0.7762,-0.7332,-0.6551,-0.5066,-0.2879",\ +"-0.9051,-0.8895,-0.8543,-0.8113,-0.7332,-0.5887,-0.3660",\ +"-1.0418,-1.0262,-0.9949,-0.9480,-0.8699,-0.7293,-0.5027",\ +"-1.2684,-1.2449,-1.2176,-1.1707,-1.0965,-0.9480,-0.7293"); + } + + fall_constraint("SIG2SRAM_constraint_template") { + index_1("0.0080,0.0288,0.0616,0.1072,0.1920,0.3496,0.5952"); + index_2("0.0080,0.0288,0.0616,0.1072,0.1920,0.3496,0.5952"); + values ("-0.5926,-0.5730,-0.5418,-0.4988,-0.4246,-0.2879,-0.0730",\ +"-0.6121,-0.5926,-0.5613,-0.5223,-0.4441,-0.3074,-0.0887",\ +"-0.6395,-0.6199,-0.5926,-0.5496,-0.4715,-0.3348,-0.1160",\ +"-0.6863,-0.6668,-0.6355,-0.5965,-0.5184,-0.3777,-0.1590",\ +"-0.7605,-0.7410,-0.7137,-0.6746,-0.5926,-0.4559,-0.2410",\ +"-0.9012,-0.8816,-0.8504,-0.8113,-0.7332,-0.5926,-0.3895",\ +"-1.1238,-1.1043,-1.0769,-1.0379,-0.9559,-0.8191,-0.6004"); + } + } + + + timing() { + timing_type : hold_rising; + related_pin : "A_BIST_CLK"; + when : "((A_BIST_WEN | A_BIST_REN)& A_BIST_MEN)" + sdf_cond : "A_BIST_RW_ACCESS" + + rise_constraint("SIG2SRAM_constraint_template") { + index_1("0.0080,0.0288,0.0616,0.1072,0.1920,0.3496,0.5952"); + index_2("0.0080,0.0288,0.0616,0.1072,0.1920,0.3496,0.5952"); + values ("0.8488,0.8293,0.7980,0.7551,0.6730,0.5285,0.3098",\ +"0.8684,0.8488,0.8176,0.7746,0.6926,0.5480,0.3254",\ +"0.8996,0.8801,0.8449,0.8020,0.7238,0.5754,0.3527",\ +"0.9426,0.9191,0.8918,0.8488,0.7668,0.6223,0.3996",\ +"1.0168,1.0012,0.9699,0.9230,0.8449,0.7004,0.4777",\ +"1.1574,1.1379,1.1105,1.0598,0.9816,0.8371,0.6184",\ +"1.3801,1.3605,1.3254,1.2980,1.2043,1.0637,0.8371"); + } + + fall_constraint("SIG2SRAM_constraint_template") { + index_1("0.0080,0.0288,0.0616,0.1072,0.1920,0.3496,0.5952"); + index_2("0.0080,0.0288,0.0616,0.1072,0.1920,0.3496,0.5952"); + values ("0.6965,0.6770,0.6496,0.6066,0.5246,0.3918,0.1730",\ +"0.7160,0.6965,0.6652,0.6262,0.5441,0.4113,0.1965",\ +"0.7473,0.7277,0.6965,0.6535,0.5754,0.4426,0.2238",\ +"0.7863,0.7707,0.7395,0.7004,0.6223,0.4855,0.2629",\ +"0.8684,0.8449,0.8176,0.7785,0.7004,0.5637,0.3449",\ +"1.0051,0.9855,0.9855,0.9113,0.8332,0.7004,0.4895",\ +"1.2277,1.2082,1.1809,1.1379,1.0598,0.9230,0.7004"); + } + } +} +pin(A_BIST_WEN) { + direction : input ; + capacitance : 0.00313551 ; + max_transition : "0.5952" ; + related_power_pin : VDD; + related_ground_pin : VSS; + internal_power() { + when : "A_BIST_MEN"; + rise_power("scalar"){ + values (0.0268); + } + fall_power("scalar"){ + values (0.0213); + } + } + internal_power() { + when : "!A_BIST_MEN"; + rise_power("scalar"){ + values (0.0484); + } + fall_power("scalar"){ + values (0.0885); + } + } + timing() { + timing_type : setup_rising; + related_pin : "A_BIST_CLK"; + when : "A_BIST_MEN" + sdf_cond : "A_BIST_MEN" + + rise_constraint("SIG2SRAM_constraint_template") { + index_1("0.0080,0.0288,0.0616,0.1072,0.1920,0.3496,0.5952"); + index_2("0.0080,0.0288,0.0616,0.1072,0.1920,0.3496,0.5952"); + values ("0.3137,0.3332,0.3605,0.4035,0.4816,0.6223,0.8488",\ +"0.2980,0.3176,0.3410,0.3840,0.4660,0.6027,0.8293",\ +"0.2629,0.2824,0.3098,0.3527,0.4348,0.5754,0.7980",\ +"0.2199,0.2395,0.2668,0.3098,0.3918,0.5324,0.7590",\ +"0.1418,0.1613,0.1887,0.2316,0.3137,0.4348,0.6730",\ +"0.0012,0.0207,0.0520,0.0910,0.1730,0.3098,0.5285",\ +"-0.2215,-0.2020,-0.1746,-0.1277,-0.0496,0.0910,0.3098"); + } + + fall_constraint("SIG2SRAM_constraint_template") { + index_1("0.0080,0.0288,0.0616,0.1072,0.1920,0.3496,0.5952"); + index_2("0.0080,0.0288,0.0616,0.1072,0.1920,0.3496,0.5952"); + values ("0.4504,0.4699,0.4973,0.5324,0.6027,0.7355,0.9699",\ +"0.4309,0.4504,0.4777,0.5129,0.5910,0.7160,0.9504",\ +"0.3996,0.4191,0.4465,0.4816,0.5520,0.6848,0.9191",\ +"0.3605,0.3762,0.4035,0.4387,0.5168,0.6418,0.8723",\ +"0.2785,0.2980,0.3215,0.3605,0.4348,0.5637,0.7980",\ +"0.1379,0.1574,0.1809,0.2199,0.2980,0.4309,0.6457",\ +"-0.0809,-0.0613,-0.0340,0.0051,0.0832,0.2160,0.4191"); + } + } + + + timing() { + timing_type : hold_rising; + related_pin : "A_BIST_CLK"; + when : "A_BIST_MEN" + sdf_cond : "A_BIST_MEN" + + rise_constraint("SIG2SRAM_constraint_template") { + index_1("0.0080,0.0288,0.0616,0.1072,0.1920,0.3496,0.5952"); + index_2("0.0080,0.0288,0.0616,0.1072,0.1920,0.3496,0.5952"); + values ("0.3723,0.3527,0.3215,0.2785,0.1965,0.0559,-0.1668",\ +"0.3918,0.3723,0.3449,0.2980,0.2160,0.0754,-0.1473",\ +"0.4152,0.3996,0.3684,0.3254,0.2434,0.1066,-0.1199",\ +"0.4621,0.4465,0.4152,0.3723,0.2863,0.1496,-0.0730",\ +"0.5324,0.5207,0.4895,0.4465,0.3645,0.2199,0.0051",\ +"0.6770,0.6535,0.6301,0.5832,0.5090,0.3605,0.1418",\ +"0.9035,0.8879,0.8566,0.8137,0.7316,0.5871,0.3684"); + } + + fall_constraint("SIG2SRAM_constraint_template") { + index_1("0.0080,0.0288,0.0616,0.1072,0.1920,0.3496,0.5952"); + index_2("0.0080,0.0288,0.0616,0.1072,0.1920,0.3496,0.5952"); + values ("0.3762,0.3566,0.3293,0.2863,0.2043,0.0676,-0.1434",\ +"0.3957,0.3762,0.3488,0.3059,0.2238,0.0871,-0.1199",\ +"0.4230,0.4035,0.3723,0.3332,0.2512,0.1184,-0.0965",\ +"0.4660,0.4465,0.4191,0.3762,0.2941,0.1613,-0.0496",\ +"0.5324,0.5168,0.4973,0.4543,0.3723,0.2316,0.0285",\ +"0.6809,0.6613,0.6340,0.5910,0.5129,0.3645,0.1652",\ +"0.9113,0.8918,0.8605,0.8176,0.7395,0.5988,0.3879"); + } + } + } +pin(A_BIST_REN) { + direction : input ; + capacitance : 0.00381144 ; + max_transition : "0.5952" ; + related_power_pin : VDD; + related_ground_pin : VSS; + internal_power() { + when : "A_BIST_MEN"; + rise_power("scalar"){ + values (0.0263); + } + fall_power("scalar"){ + values (0.0112); + } + } + internal_power() { + when : "!A_BIST_MEN"; + rise_power("scalar"){ + values (0.0042); + } + fall_power("scalar"){ + values (0.0039); + } + } + timing() { + timing_type : setup_rising; + related_pin : "A_BIST_CLK"; + when : "A_BIST_MEN" + sdf_cond : "A_BIST_MEN" + + rise_constraint("SIG2SRAM_constraint_template") { + index_1("0.0080,0.0288,0.0616,0.1072,0.1920,0.3496,0.5952"); + index_2("0.0080,0.0288,0.0616,0.1072,0.1920,0.3496,0.5952"); + values ("-0.0770,-0.0574,-0.0262,0.0168,0.0949,0.2355,0.4582",\ +"-0.0965,-0.0770,-0.0457,-0.0027,0.0754,0.2160,0.4387",\ +"-0.1199,-0.1004,-0.0730,-0.0262,0.0520,0.1887,0.4113",\ +"-0.1590,-0.1434,-0.1160,-0.0730,0.0051,0.1457,0.3645",\ +"-0.2449,-0.2254,-0.1941,-0.1473,-0.0770,0.0676,0.2863",\ +"-0.3816,-0.3699,-0.3387,-0.2801,-0.2215,-0.0770,0.1457",\ +"-0.6121,-0.5926,-0.5613,-0.5145,-0.4363,-0.2996,-0.0730"); + } + + fall_constraint("SIG2SRAM_constraint_template") { + index_1("0.0080,0.0288,0.0616,0.1072,0.1920,0.3496,0.5952"); + index_2("0.0080,0.0288,0.0616,0.1072,0.1920,0.3496,0.5952"); + values ("0.1262,0.1457,0.1691,0.2121,0.2824,0.4191,0.6457",\ +"0.1105,0.1262,0.1496,0.1887,0.2629,0.3996,0.6262",\ +"0.0793,0.0949,0.1223,0.1652,0.2395,0.3684,0.5949",\ +"0.0363,0.0559,0.0793,0.1223,0.2004,0.3410,0.5520",\ +"-0.0457,-0.0262,0.0012,0.0441,0.1301,0.2629,0.4738",\ +"-0.1902,-0.1746,-0.1434,-0.1043,-0.0184,0.1223,0.3332",\ +"-0.4129,-0.3934,-0.3660,-0.3230,-0.2449,-0.1043,0.1105"); + } + } + + + timing() { + timing_type : hold_rising; + related_pin : "A_BIST_CLK"; + when : "A_BIST_MEN" + sdf_cond : "A_BIST_MEN" + + rise_constraint("SIG2SRAM_constraint_template") { + index_1("0.0080,0.0288,0.0616,0.1072,0.1920,0.3496,0.5952"); + index_2("0.0080,0.0288,0.0616,0.1072,0.1920,0.3496,0.5952"); + values ("0.4113,0.3918,0.3645,0.3176,0.2395,0.0988,-0.1238",\ +"0.4309,0.4113,0.3840,0.3371,0.2590,0.1184,-0.1043",\ +"0.4582,0.4387,0.4113,0.3645,0.2824,0.1457,-0.0770",\ +"0.5051,0.4816,0.4543,0.4074,0.3293,0.1887,-0.0340",\ +"0.5715,0.5598,0.5324,0.4895,0.4035,0.2512,0.0441",\ +"0.7043,0.7004,0.6730,0.6262,0.5402,0.3957,0.1809",\ +"0.9387,0.9270,0.8957,0.8527,0.7746,0.6262,0.4074"); + } + + fall_constraint("SIG2SRAM_constraint_template") { + index_1("0.0080,0.0288,0.0616,0.1072,0.1920,0.3496,0.5952"); + index_2("0.0080,0.0288,0.0616,0.1072,0.1920,0.3496,0.5952"); + values ("0.4152,0.3918,0.3645,0.3215,0.2395,0.1027,-0.1082",\ +"0.4309,0.4113,0.3801,0.3410,0.2590,0.1223,-0.0926",\ +"0.4582,0.4387,0.4074,0.3684,0.2863,0.1496,-0.0613",\ +"0.5012,0.4816,0.4504,0.4074,0.3293,0.1887,-0.0145",\ +"0.5715,0.5559,0.5285,0.4816,0.3996,0.2512,0.0598",\ +"0.7160,0.7004,0.6691,0.6262,0.5520,0.4035,0.2004",\ +"0.9387,0.9191,0.8957,0.8488,0.7707,0.6262,0.4113"); + } + } + } +pin(A_BIST_MEN) { + direction : input ; + capacitance : 0.00300347 ; + max_transition : "0.5952" ; + related_power_pin : VDD; + related_ground_pin : VSS; + internal_power() { + rise_power("scalar"){ + values (0.0005); + } + fall_power("scalar"){ + values (0.0301); + } + } + timing() { + timing_type : setup_rising; + related_pin : "A_BIST_CLK"; + + rise_constraint("SIG2SRAM_constraint_template") { + index_1("0.0080,0.0288,0.0616,0.1072,0.1920,0.3496,0.5952"); + index_2("0.0080,0.0288,0.0616,0.1072,0.1920,0.3496,0.5952"); + values ("0.3215,0.3449,0.3684,0.4113,0.4895,0.6301,0.8527",\ +"0.3059,0.3254,0.3527,0.3957,0.4738,0.6145,0.8371",\ +"0.2746,0.2941,0.3215,0.3645,0.4426,0.5871,0.8059",\ +"0.2316,0.2512,0.2785,0.3215,0.3996,0.5402,0.7629",\ +"0.1496,0.1730,0.1965,0.2395,0.3215,0.4660,0.6848",\ +"0.0090,0.0285,0.0598,0.1027,0.1809,0.3176,0.5402",\ +"-0.2098,-0.1902,-0.1668,-0.1199,-0.0418,0.0988,0.3137"); + } + + fall_constraint("SIG2SRAM_constraint_template") { + index_1("0.0080,0.0288,0.0616,0.1072,0.1920,0.3496,0.5952"); + index_2("0.0080,0.0288,0.0616,0.1072,0.1920,0.3496,0.5952"); + values ("0.4582,0.4738,0.5012,0.5363,0.6145,0.7395,0.9738",\ +"0.4387,0.4543,0.4816,0.5207,0.5910,0.7199,0.9582",\ +"0.4035,0.4230,0.4504,0.4855,0.5637,0.6887,0.9230",\ +"0.3645,0.3840,0.4074,0.4465,0.5285,0.6496,0.8840",\ +"0.2824,0.3020,0.3254,0.3645,0.4465,0.5715,0.7980",\ +"0.1418,0.1613,0.1887,0.2238,0.3020,0.4309,0.6496",\ +"-0.0770,-0.0574,-0.0301,0.0090,0.0910,0.2238,0.4191"); + } + } + + + timing() { + timing_type : hold_rising; + related_pin : "A_BIST_CLK"; + + rise_constraint("SIG2SRAM_constraint_template") { + index_1("0.0080,0.0288,0.0616,0.1072,0.1920,0.3496,0.5952"); + index_2("0.0080,0.0288,0.0616,0.1072,0.1920,0.3496,0.5952"); + values ("0.3762,0.3605,0.3293,0.2863,0.2043,0.0637,-0.1629",\ +"0.3996,0.3801,0.3488,0.3020,0.2238,0.0832,-0.1395",\ +"0.4230,0.4074,0.3723,0.3293,0.2473,0.1105,-0.1121",\ +"0.4621,0.4465,0.4152,0.3762,0.2941,0.1535,-0.0691",\ +"0.5441,0.5285,0.4973,0.4465,0.3684,0.2316,0.0090",\ +"0.6848,0.6652,0.6301,0.5910,0.5129,0.3605,0.1496",\ +"0.9074,0.8918,0.8566,0.8215,0.7395,0.5910,0.3723"); + } + + fall_constraint("SIG2SRAM_constraint_template") { + index_1("0.0080,0.0288,0.0616,0.1072,0.1920,0.3496,0.5952"); + index_2("0.0080,0.0288,0.0616,0.1072,0.1920,0.3496,0.5952"); + values ("0.3762,0.3605,0.3332,0.2863,0.2043,0.0715,-0.1395",\ +"0.3996,0.3762,0.3488,0.3059,0.2238,0.0910,-0.1199",\ +"0.4270,0.4035,0.3762,0.3332,0.2512,0.1184,-0.0965",\ +"0.4699,0.4504,0.4191,0.3762,0.2941,0.1613,-0.0496",\ +"0.5441,0.5285,0.4973,0.4543,0.3762,0.2355,0.0324",\ +"0.6770,0.6613,0.6340,0.5949,0.5207,0.3762,0.1652",\ +"0.9074,0.8918,0.8605,0.8176,0.7395,0.6027,0.3918"); + } + } + } +bus(A_BIST_BM) { + bus_type : D_31_0; + direction : input ; + capacitance : 0.00225269 ; + max_transition : "0.5952" ; + pin(A_BIST_BM[31:0]) { + related_power_pin : VDD; + related_ground_pin : VSS; + internal_power() { + when : "A_BIST_MEN"; + rise_power("scalar"){ + values (0.0632); + } + fall_power("scalar"){ + values (0.0448); + } + } + internal_power() { + when : "!A_BIST_MEN"; + rise_power("scalar"){ + values (0.0895); + } + fall_power("scalar"){ + values (0.0291); + } + } + } + timing() { + timing_type : setup_rising; + related_pin : "A_BIST_CLK"; + when : "(A_BIST_WEN & A_BIST_MEN)" + sdf_cond : "A_BIST_RW_ACCESS" + + rise_constraint("SIG2SRAM_constraint_template") { + index_1("0.0080,0.0288,0.0616,0.1072,0.1920,0.3496,0.5952"); + index_2("0.0080,0.0288,0.0616,0.1072,0.1920,0.3496,0.5952"); + values ("-0.7914,-0.7719,-0.7455,-0.7035,-0.6224,-0.4779,-0.2572",\ +"-0.7994,-0.7799,-0.7535,-0.7115,-0.6305,-0.4859,-0.2652",\ +"-0.8084,-0.7889,-0.7625,-0.7205,-0.6395,-0.4950,-0.2742",\ +"-0.8216,-0.8020,-0.7757,-0.7337,-0.6526,-0.5081,-0.2874",\ +"-0.8459,-0.8263,-0.8000,-0.7580,-0.6769,-0.5324,-0.3117",\ +"-0.8764,-0.8568,-0.8305,-0.7885,-0.7074,-0.5629,-0.3422",\ +"-0.9578,-0.9383,-0.9119,-0.8699,-0.7889,-0.6443,-0.4236"); + } + + fall_constraint("SIG2SRAM_constraint_template") { + index_1("0.0080,0.0288,0.0616,0.1072,0.1920,0.3496,0.5952"); + index_2("0.0080,0.0288,0.0616,0.1072,0.1920,0.3496,0.5952"); + values ("-0.7357,-0.7201,-0.6918,-0.6527,-0.5717,-0.4340,-0.2221",\ +"-0.7438,-0.7281,-0.6998,-0.6607,-0.5797,-0.4420,-0.2301",\ +"-0.7528,-0.7371,-0.7088,-0.6698,-0.5887,-0.4510,-0.2391",\ +"-0.7659,-0.7503,-0.7220,-0.6829,-0.6019,-0.4642,-0.2523",\ +"-0.7902,-0.7746,-0.7462,-0.7072,-0.6261,-0.4884,-0.2765",\ +"-0.8207,-0.8051,-0.7768,-0.7377,-0.6566,-0.5190,-0.3070",\ +"-0.9022,-0.8865,-0.8582,-0.8191,-0.7381,-0.6004,-0.3885"); + } + } + + + timing() { + timing_type : hold_rising; + related_pin : "A_BIST_CLK"; + when : "(A_BIST_WEN & A_BIST_MEN)" + sdf_cond : "A_BIST_RW_ACCESS" + + rise_constraint("SIG2SRAM_constraint_template") { + index_1("0.0080,0.0288,0.0616,0.1072,0.1920,0.3496,0.5952"); + index_2("0.0080,0.0288,0.0616,0.1072,0.1920,0.3496,0.5952"); + values ("0.9084,0.8869,0.8605,0.8176,0.7385,0.5930,0.3674",\ +"0.9164,0.8949,0.8686,0.8256,0.7465,0.6010,0.3754",\ +"0.9254,0.9039,0.8776,0.8346,0.7555,0.6100,0.3844",\ +"0.9386,0.9171,0.8907,0.8478,0.7687,0.6232,0.3976",\ +"0.9629,0.9414,0.9150,0.8720,0.7929,0.6474,0.4218",\ +"0.9934,0.9719,0.9455,0.9025,0.8234,0.6779,0.4524",\ +"1.0748,1.0533,1.0270,0.9840,0.9049,0.7594,0.5338"); + } + + fall_constraint("SIG2SRAM_constraint_template") { + index_1("0.0080,0.0288,0.0616,0.1072,0.1920,0.3496,0.5952"); + index_2("0.0080,0.0288,0.0616,0.1072,0.1920,0.3496,0.5952"); + values ("0.8400,0.8234,0.7951,0.7512,0.6740,0.5363,0.3264",\ +"0.8481,0.8315,0.8031,0.7592,0.6820,0.5443,0.3344",\ +"0.8571,0.8405,0.8121,0.7682,0.6910,0.5534,0.3434",\ +"0.8702,0.8536,0.8253,0.7814,0.7042,0.5665,0.3565",\ +"0.8945,0.8779,0.8496,0.8056,0.7285,0.5908,0.3808",\ +"0.9250,0.9084,0.8801,0.8361,0.7590,0.6213,0.4113",\ +"1.0065,0.9899,0.9615,0.9176,0.8404,0.7028,0.4928"); + } + } +} + pin(A_BIST_CLK) { + direction : input; + capacitance : 0.00378957; + max_transition : "0.5952"; + clock : "true" ; + pin_func_type : active_rising ; + + timing () { + timing_type : "min_pulse_width"; + related_pin : "A_BIST_CLK"; + rise_constraint("CLKTRAN_constraint_template") { + index_1("0.008,0.5952"); + values("0.4,0.4"); + } + } + + related_power_pin : VDD; + related_ground_pin : VSS; + + internal_power() { + when : "!A_BIST_MEN & !A_BIST_WEN & !A_BIST_REN"; + rise_power("scalar"){ + values (0); + } + fall_power("scalar"){ + values (0); + } + } + internal_power() { + when : "!A_BIST_MEN & A_BIST_WEN & !A_BIST_REN"; + rise_power("scalar"){ + values (0.6568); + } + fall_power("scalar"){ + values (0); + } + } + internal_power() { + when : "A_BIST_MEN & A_BIST_WEN & !A_BIST_REN"; + rise_power("scalar"){ + values (46.0330); + } + fall_power("scalar"){ + values (0); + } + } + internal_power() { + when : "A_BIST_MEN & A_BIST_WEN & A_BIST_REN"; + rise_power("scalar"){ + values (49.3119); + } + fall_power("scalar"){ + values (0); + } + } + internal_power() { + when : "A_BIST_MEN & !A_BIST_WEN & A_BIST_REN"; + rise_power("scalar"){ + values (36.0779); + } + fall_power("scalar"){ + values (0); + } + } + internal_power() { + when : "!A_BIST_MEN & !A_BIST_WEN & A_BIST_REN"; + rise_power("scalar"){ + values (0.4418); + } + fall_power("scalar"){ + values (0); + } + } + internal_power() { + when : "!A_BIST_MEN & A_BIST_WEN & A_BIST_REN"; + rise_power("scalar"){ + values (1.1609); + } + fall_power("scalar"){ + values (0); + } + } + internal_power() { + when : "A_BIST_MEN & !A_BIST_WEN & !A_BIST_REN"; + rise_power("scalar"){ + values (0); + } + fall_power("scalar"){ + values (0); + } + } + } + bus(A_BIST_DIN) { + bus_type : D_31_0; + direction : input ; + capacitance : 0.00226348 ; + memory_write() { + address : A_BIST_ADDR ; + clocked_on : A_BIST_CLK; + } + + max_transition : "0.5952" ; + pin(A_BIST_DIN[31:0]) { + related_power_pin : VDD; + related_ground_pin : VSS; + internal_power() { + when : "A_BIST_MEN"; + rise_power("scalar"){ + values (0.0632); + } + fall_power("scalar"){ + values (0.0448); + } + } + internal_power() { + when : "!A_BIST_MEN"; + rise_power("scalar"){ + values (0.0895); + } + fall_power("scalar"){ + values (0.0291); + } + } + } + timing() { + timing_type : setup_rising; + related_pin : "A_BIST_CLK"; + when : "(A_BIST_WEN & A_BIST_MEN)"; + sdf_cond : "A_BIST_W_ACCESS"; + + rise_constraint("SIG2SRAM_constraint_template") { + index_1("0.0080,0.0288,0.0616,0.1072,0.1920,0.3496,0.5952"); + index_2("0.0080,0.0288,0.0616,0.1072,0.1920,0.3496,0.5952"); + values ("-0.7914,-0.7719,-0.7455,-0.7035,-0.6224,-0.4779,-0.2572",\ +"-0.7994,-0.7799,-0.7535,-0.7115,-0.6305,-0.4859,-0.2652",\ +"-0.8084,-0.7889,-0.7625,-0.7205,-0.6395,-0.4950,-0.2742",\ +"-0.8216,-0.8020,-0.7757,-0.7337,-0.6526,-0.5081,-0.2874",\ +"-0.8459,-0.8263,-0.8000,-0.7580,-0.6769,-0.5324,-0.3117",\ +"-0.8764,-0.8568,-0.8305,-0.7885,-0.7074,-0.5629,-0.3422",\ +"-0.9578,-0.9383,-0.9119,-0.8699,-0.7889,-0.6443,-0.4236"); + } + + fall_constraint("SIG2SRAM_constraint_template") { + index_1("0.0080,0.0288,0.0616,0.1072,0.1920,0.3496,0.5952"); + index_2("0.0080,0.0288,0.0616,0.1072,0.1920,0.3496,0.5952"); + values ("-0.7357,-0.7201,-0.6918,-0.6527,-0.5717,-0.4340,-0.2221",\ +"-0.7438,-0.7281,-0.6998,-0.6607,-0.5797,-0.4420,-0.2301",\ +"-0.7528,-0.7371,-0.7088,-0.6698,-0.5887,-0.4510,-0.2391",\ +"-0.7659,-0.7503,-0.7220,-0.6829,-0.6019,-0.4642,-0.2523",\ +"-0.7902,-0.7746,-0.7462,-0.7072,-0.6261,-0.4884,-0.2765",\ +"-0.8207,-0.8051,-0.7768,-0.7377,-0.6566,-0.5190,-0.3070",\ +"-0.9022,-0.8865,-0.8582,-0.8191,-0.7381,-0.6004,-0.3885"); + } + } + + timing() { + timing_type : hold_rising; + related_pin : "A_BIST_CLK"; + when : "(A_BIST_WEN & A_BIST_MEN)"; + sdf_cond : "A_BIST_W_ACCESS"; + + rise_constraint("SIG2SRAM_constraint_template") { + index_1("0.0080,0.0288,0.0616,0.1072,0.1920,0.3496,0.5952"); + index_2("0.0080,0.0288,0.0616,0.1072,0.1920,0.3496,0.5952"); + values ("0.9084,0.8869,0.8605,0.8176,0.7385,0.5930,0.3674",\ +"0.9164,0.8949,0.8686,0.8256,0.7465,0.6010,0.3754",\ +"0.9254,0.9039,0.8776,0.8346,0.7555,0.6100,0.3844",\ +"0.9386,0.9171,0.8907,0.8478,0.7687,0.6232,0.3976",\ +"0.9629,0.9414,0.9150,0.8720,0.7929,0.6474,0.4218",\ +"0.9934,0.9719,0.9455,0.9025,0.8234,0.6779,0.4524",\ +"1.0748,1.0533,1.0270,0.9840,0.9049,0.7594,0.5338"); + } + + fall_constraint("SIG2SRAM_constraint_template") { + index_1("0.0080,0.0288,0.0616,0.1072,0.1920,0.3496,0.5952"); + index_2("0.0080,0.0288,0.0616,0.1072,0.1920,0.3496,0.5952"); + values ("0.8400,0.8234,0.7951,0.7512,0.6740,0.5363,0.3264",\ +"0.8481,0.8315,0.8031,0.7592,0.6820,0.5443,0.3344",\ +"0.8571,0.8405,0.8121,0.7682,0.6910,0.5534,0.3434",\ +"0.8702,0.8536,0.8253,0.7814,0.7042,0.5665,0.3565",\ +"0.8945,0.8779,0.8496,0.8056,0.7285,0.5908,0.3808",\ +"0.9250,0.9084,0.8801,0.8361,0.7590,0.6213,0.4113",\ +"1.0065,0.9899,0.9615,0.9176,0.8404,0.7028,0.4928"); + } + } + } + +bus(A_DOUT) { + + bus_type : D_31_0; + direction : output ; + capacitance : 0 ; + max_capacitance : 0.064 ; + memory_read() { + address : A_ADDR ; + } + pin(A_DOUT[31:0]) { + related_power_pin : VDD; + related_ground_pin : VSS; + internal_power() { + rise_power("scalar") { + values (0); + } + fall_power("scalar") { + values (0); + } + } + } + timing() { + related_pin : "A_CLK"; + timing_type : rising_edge ; + timing_sense : non_unate ; + + cell_rise(SIG2SRAM_delay_template) { + index_1("0.0080,0.0288,0.0616,0.1072,0.1920,0.3496,0.5952"); + index_2("0.0008,0.0014,0.0051,0.0100,0.0339,0.0640"); + values ("7.2485,7.2513,7.2634,7.2776,7.3302,7.3852",\ +"7.2640,7.2667,7.2788,7.2931,7.3456,7.4006",\ +"7.2703,7.2730,7.2852,7.2994,7.3520,7.4069",\ +"7.2910,7.2937,7.3059,7.3201,7.3727,7.4276",\ +"7.3084,7.3111,7.3233,7.3375,7.3901,7.4451",\ +"7.3442,7.3469,7.3591,7.3733,7.4259,7.4808",\ +"7.4146,7.4173,7.4294,7.4437,7.4962,7.5512"); + } + cell_fall(SIG2SRAM_delay_template) { + index_1("0.0080,0.0288,0.0616,0.1072,0.1920,0.3496,0.5952"); + index_2("0.0008,0.0014,0.0051,0.0100,0.0339,0.0640"); + values ("7.1384,7.1405,7.1503,7.1621,7.2057,7.2494",\ +"7.1538,7.1560,7.1657,7.1776,7.2211,7.2648",\ +"7.1601,7.1623,7.1721,7.1839,7.2274,7.2712",\ +"7.1808,7.1830,7.1927,7.2046,7.2481,7.2918",\ +"7.1982,7.2004,7.2102,7.2220,7.2656,7.3093",\ +"7.2340,7.2362,7.2459,7.2578,7.3013,7.3451",\ +"7.3044,7.3066,7.3163,7.3282,7.3717,7.4154"); + } + + rise_transition(SRAM_load_template) { + index_1("0.0008,0.0014,0.0051,0.0100,0.0339,0.0640"); + values ("0.0560,0.0583,0.0696,0.0816,0.1519,0.2335"); + } + fall_transition(SRAM_load_template) { + index_1("0.0008,0.0014,0.0051,0.0100,0.0339,0.0640"); + values ("0.0428,0.0445,0.0538,0.0658,0.1181,0.1751"); + } + } +} +cell_leakage_power : 2613.1763; +} +} diff --git a/flow/platforms/ihp-sg13g2/lib/RM_IHPSG13_1P_1024x32_c2_bm_bist_typ_1p20V_25C.lib b/flow/platforms/ihp-sg13g2/lib/RM_IHPSG13_1P_1024x32_c2_bm_bist_typ_1p20V_25C.lib new file mode 100644 index 0000000000..c1fcd064be --- /dev/null +++ b/flow/platforms/ihp-sg13g2/lib/RM_IHPSG13_1P_1024x32_c2_bm_bist_typ_1p20V_25C.lib @@ -0,0 +1,1525 @@ +/* ------------------------------------------------------*/ +/**/ +/* Copyright 2025 IHP PDK Authors*/ +/**/ +/* Licensed under the Apache License, Version 2.0 (the "License");*/ +/* you may not use this file except in compliance with the License.*/ +/* You may obtain a copy of the License at*/ +/* */ +/* https://www.apache.org/licenses/LICENSE-2.0*/ +/* */ +/* Unless required by applicable law or agreed to in writing, software*/ +/* distributed under the License is distributed on an "AS IS" BASIS,*/ +/* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.*/ +/* See the License for the specific language governing permissions and*/ +/* limitations under the License.*/ +/* */ +/* Generated on Thu Aug 21 20:48:24 2025 */ +/* */ +/* ------------------------------------------------------ */ +library(RM_IHPSG13_1P_1024x32_c2_bm_bist_typ_1p20V_25C) { + technology (cmos) ; + delay_model : table_lookup ; + define ("add_pg_pin_to_lib", "library", "boolean"); + add_pg_pin_to_lib : true; + voltage_map ( VDD, 1.20); + voltage_map ( VDDARRAY, 1.20); + voltage_map ( VSS, 0.000000 ); + + date : "Thu Aug 21 20:48:22 2025" ; + comment : "IHP Microelectronics GmbH, 2023" ; + revision : 1.0.0 ; + simulation : true ; + nom_process : 1 ; + nom_temperature : 25 ; + nom_voltage : 1.20 ; + + operating_conditions("typ_1p20V_25C"){ + process : 1 ; + temperature : 25 ; + voltage : 1.20 ; + tree_type : "balanced_tree" ; + } + + default_operating_conditions : typ_1p20V_25C ; + default_max_transition : 1.0 ; + default_fanout_load : 1.0 ; + default_inout_pin_cap : 0.0 ; + default_input_pin_cap : 0.0 ; + default_output_pin_cap : 0.0 ; + default_cell_leakage_power : 0.0 ; + default_leakage_power_density : 0.0 ; + + slew_lower_threshold_pct_rise : 30 ; + slew_upper_threshold_pct_rise : 70 ; + input_threshold_pct_fall : 50 ; + output_threshold_pct_fall : 50 ; + input_threshold_pct_rise : 50 ; + output_threshold_pct_rise : 50 ; + slew_lower_threshold_pct_fall : 30 ; + slew_upper_threshold_pct_fall : 70 ; + slew_derate_from_library : 0.5; + k_volt_cell_leakage_power : 0.0 ; + k_temp_cell_leakage_power : 0.0 ; + k_process_cell_leakage_power : 0.0 ; + k_volt_internal_power : 0.0 ; + k_temp_internal_power : 0.0 ; + k_process_internal_power : 0.0 ; + + capacitive_load_unit (1,pf) ; + voltage_unit : "1V" ; + current_unit : "1uA" ; + time_unit : "1ns" ; + leakage_power_unit : "1nW" ; + pulling_resistance_unit : "1kohm"; + /* + ------------------------------------------------------------------------------------------ + implicit units overview: + cell_area unit : "um" + internal_power unit : "1e-12 * J/toggle = 1 * uW/MHz" + (capacitive_load_unit * voltage_unit^2) per toggle event + ------------------------------------------------------------------------------------------ + */ + library_features(report_delay_calculation); + define_cell_area (pad_drivers,pad_driver_sites) ; + + lu_table_template(CLKTRAN_constraint_template) { + variable_1 : constrained_pin_transition; + index_1 ( "0.010, 0.050, 0.200, 0.400, 1.000" ); + } + lu_table_template(SRAM_load_template) { + variable_1 : total_output_net_capacitance; + index_1 ( "0.0008,0.0014,0.0051,0.0100,0.0339,0.0640" ); + } + lu_table_template(SIG2SRAM_constraint_template) { + variable_1 : related_pin_transition; + variable_2 : constrained_pin_transition; + index_1 ( "0.0056,0.0232,0.0400,0.0728,0.1280,0.2440,0.4760" ); + index_2 ( "0.0056,0.0232,0.0400,0.0728,0.1280,0.2440,0.4760" ); + } + + lu_table_template(SIG2SRAM_delay_template) { + variable_1 : input_net_transition; + variable_2 : total_output_net_capacitance; + index_1 ( "0.0056,0.0232,0.0400,0.0728,0.1280,0.2440,0.4760" ); + index_2 ( "0.0008,0.0014,0.0051,0.0100,0.0339,0.0640" ); + } + + type (D_31_0) { + base_type : array; + data_type : bit; + bit_width : 32; + bit_from : 31; + bit_to : 0; + downto : true; + } + + type (A_9_0) { + base_type : array; + data_type : bit; + bit_width : 10; + bit_from : 9; + bit_to : 0; + downto : true; + } + +cell(RM_IHPSG13_1P_1024x32_c2_bm_bist) { +pg_pin (VDD) { + pg_type : primary_power; + voltage_name : VDD; +} +pg_pin (VDDARRAY) { + pg_type : primary_power; + voltage_name : VDDARRAY; +} +pg_pin (VSS) { + pg_type : primary_ground; + voltage_name : VSS; +} + +memory() { + type : ram; + address_width : 10; + word_width : 32; +} + +interface_timing : false; +bus_naming_style : "%s[%d]" ; +area : 140182.6944 ; + + pin(A_DLY) { + direction : input ; + capacitance : 0.00401111 ; + max_transition : "1" ; + related_power_pin : VDD; + related_ground_pin : VSS; + internal_power() { + rise_power("scalar") { + values (0); + } + fall_power("scalar") { + values (0); + } + } + } + +bus(A_ADDR) { + bus_type : A_9_0; + direction : input ; + capacitance : 0.00721489 ; + pin(A_ADDR[0]) { + capacitance : 0.00593979 ; + } + pin(A_ADDR[1]) { + capacitance : 0.00483009 ; + } + pin(A_ADDR[2]) { + capacitance : 0.006215 ; + } + pin(A_ADDR[3]) { + capacitance : 0.00766726 ; + } + pin(A_ADDR[4]) { + capacitance : 0.00488951 ; + } + pin(A_ADDR[5]) { + capacitance : 0.0091523 ; + } + pin(A_ADDR[6]) { + capacitance : 0.0109212 ; + } + pin(A_ADDR[7]) { + capacitance : 0.00774122 ; + } + pin(A_ADDR[8]) { + capacitance : 0.0101403 ; + } + max_transition : "0.476" ; + pin(A_ADDR[9:0]) { + related_power_pin : VDD; + related_ground_pin : VSS; + internal_power() { + when : "A_MEN"; + rise_power("scalar"){ + values (0.0115); + } + fall_power("scalar"){ + values (0.0061); + } + } + internal_power() { + when : "!A_MEN"; + rise_power("scalar"){ + values (0.0201); + } + fall_power("scalar"){ + values (0.0005); + } + } + } + timing() { + timing_type : setup_rising; + related_pin : "A_CLK"; + when : "((A_WEN | A_REN)& A_MEN)" + sdf_cond : "A_RW_ACCESS" + + rise_constraint("SIG2SRAM_constraint_template") { + index_1("0.0056,0.0232,0.0400,0.0728,0.1280,0.2440,0.4760"); + index_2("0.0056,0.0232,0.0400,0.0728,0.1280,0.2440,0.4760"); + values ("-0.4168,-0.3973,-0.3855,-0.3543,-0.3074,-0.2020,-0.0027",\ +"-0.4324,-0.4129,-0.4012,-0.3699,-0.3191,-0.2176,-0.0184",\ +"-0.4441,-0.4285,-0.4129,-0.3816,-0.3309,-0.2293,-0.0301",\ +"-0.4793,-0.4598,-0.4441,-0.4129,-0.3660,-0.2645,-0.0652",\ +"-0.5223,-0.5066,-0.4910,-0.4598,-0.4129,-0.3074,-0.1121",\ +"-0.6199,-0.6082,-0.5926,-0.5613,-0.5145,-0.4129,-0.2137",\ +"-0.8191,-0.8074,-0.7840,-0.7566,-0.7098,-0.6082,-0.4051"); + } + + fall_constraint("SIG2SRAM_constraint_template") { + index_1("0.0056,0.0232,0.0400,0.0728,0.1280,0.2440,0.4760"); + index_2("0.0056,0.0232,0.0400,0.0728,0.1280,0.2440,0.4760"); + values ("-0.3309,-0.3113,-0.2996,-0.2684,-0.2176,-0.1238,0.0637",\ +"-0.3465,-0.3309,-0.3152,-0.2840,-0.2332,-0.1395,0.0480",\ +"-0.3582,-0.3426,-0.3270,-0.2996,-0.2488,-0.1512,0.0324",\ +"-0.3895,-0.3738,-0.3582,-0.3309,-0.2801,-0.1863,0.0051",\ +"-0.4363,-0.4207,-0.4051,-0.3777,-0.3230,-0.2293,-0.0379",\ +"-0.5379,-0.5223,-0.5066,-0.4793,-0.4285,-0.3309,-0.1434",\ +"-0.7332,-0.7176,-0.7020,-0.6746,-0.6238,-0.5262,-0.3387"); + } + } + + + timing() { + timing_type : hold_rising; + related_pin : "A_CLK"; + when : "((A_WEN | A_REN)& A_MEN)" + sdf_cond : "A_RW_ACCESS" + + rise_constraint("SIG2SRAM_constraint_template") { + index_1("0.0056,0.0232,0.0400,0.0728,0.1280,0.2440,0.4760"); + index_2("0.0056,0.0232,0.0400,0.0728,0.1280,0.2440,0.4760"); + values ("0.5246,0.5051,0.4895,0.4582,0.4113,0.3059,0.1066",\ +"0.5402,0.5207,0.5051,0.4777,0.4270,0.3215,0.1223",\ +"0.5520,0.5324,0.5168,0.4895,0.4387,0.3371,0.1340",\ +"0.5832,0.5676,0.5520,0.5207,0.4738,0.3684,0.1691",\ +"0.6301,0.6105,0.5949,0.5676,0.5168,0.4113,0.2160",\ +"0.7316,0.7121,0.7004,0.6691,0.6223,0.5168,0.3176",\ +"0.9270,0.9230,0.8957,0.8645,0.8137,0.7121,0.5168"); + } + + fall_constraint("SIG2SRAM_constraint_template") { + index_1("0.0056,0.0232,0.0400,0.0728,0.1280,0.2440,0.4760"); + index_2("0.0056,0.0232,0.0400,0.0728,0.1280,0.2440,0.4760"); + values ("0.4309,0.4152,0.4035,0.3684,0.3215,0.2277,0.0363",\ +"0.4465,0.4309,0.4152,0.3879,0.3371,0.2395,0.0559",\ +"0.4582,0.4426,0.4309,0.3996,0.3488,0.2551,0.0715",\ +"0.4934,0.4777,0.4621,0.4348,0.3840,0.2863,0.0988",\ +"0.5363,0.5207,0.5051,0.4777,0.4270,0.3332,0.1418",\ +"0.6379,0.6262,0.6105,0.5793,0.5324,0.4348,0.2434",\ +"0.8332,0.8215,0.8059,0.7707,0.7238,0.6301,0.4387"); + } + } +} +pin(A_WEN) { + direction : input ; + capacitance : 0.00324098 ; + max_transition : "0.476" ; + related_power_pin : VDD; + related_ground_pin : VSS; + internal_power() { + when : "A_MEN"; + rise_power("scalar"){ + values (0.0046); + } + fall_power("scalar"){ + values (0.0040); + } + } + internal_power() { + when : "!A_MEN"; + rise_power("scalar"){ + values (0.0045); + } + fall_power("scalar"){ + values (0.0043); + } + } + timing() { + timing_type : setup_rising; + related_pin : "A_CLK"; + when : "A_MEN" + sdf_cond : "A_MEN" + + rise_constraint("SIG2SRAM_constraint_template") { + index_1("0.0056,0.0232,0.0400,0.0728,0.1280,0.2440,0.4760"); + index_2("0.0056,0.0232,0.0400,0.0728,0.1280,0.2440,0.4760"); + values ("0.2043,0.2199,0.2316,0.2629,0.3059,0.4113,0.6066",\ +"0.1887,0.2043,0.2160,0.2473,0.2941,0.3957,0.5949",\ +"0.1691,0.1848,0.2004,0.2316,0.2785,0.3801,0.5754",\ +"0.1379,0.1574,0.1691,0.2004,0.2473,0.3527,0.5480",\ +"0.0910,0.1066,0.1223,0.1535,0.2004,0.2980,0.4973",\ +"-0.0105,0.0051,0.0207,0.0520,0.0949,0.2004,0.3957",\ +"-0.2059,-0.1902,-0.1746,-0.1473,-0.1004,0.0051,0.2004"); + } + + fall_constraint("SIG2SRAM_constraint_template") { + index_1("0.0056,0.0232,0.0400,0.0728,0.1280,0.2440,0.4760"); + index_2("0.0056,0.0232,0.0400,0.0728,0.1280,0.2440,0.4760"); + values ("0.2941,0.3098,0.3215,0.3488,0.4035,0.4973,0.6887",\ +"0.2785,0.2941,0.3059,0.3332,0.3840,0.4816,0.6691",\ +"0.2629,0.2785,0.2902,0.3176,0.3684,0.4660,0.6535",\ +"0.2316,0.2473,0.2590,0.2863,0.3410,0.4348,0.6262",\ +"0.1848,0.2004,0.2121,0.2395,0.2902,0.3879,0.5754",\ +"0.0832,0.0988,0.1105,0.1379,0.1809,0.2746,0.4699",\ +"-0.1121,-0.0965,-0.0848,-0.0535,-0.0066,0.0910,0.2824"); + } + } + + + timing() { + timing_type : hold_rising; + related_pin : "A_CLK"; + when : "A_MEN" + sdf_cond : "A_MEN" + + rise_constraint("SIG2SRAM_constraint_template") { + index_1("0.0056,0.0232,0.0400,0.0728,0.1280,0.2440,0.4760"); + index_2("0.0056,0.0232,0.0400,0.0728,0.1280,0.2440,0.4760"); + values ("0.2473,0.2316,0.2160,0.1887,0.1379,0.0363,-0.1629",\ +"0.2629,0.2473,0.2316,0.2043,0.1535,0.0520,-0.1473",\ +"0.2785,0.2590,0.2434,0.2160,0.1652,0.0676,-0.1355",\ +"0.3098,0.2941,0.2785,0.2473,0.1965,0.0910,-0.1043",\ +"0.3527,0.3371,0.3215,0.2941,0.2434,0.1418,-0.0574",\ +"0.4582,0.4426,0.4270,0.3957,0.3488,0.2434,0.0480",\ +"0.6535,0.6379,0.6184,0.5910,0.5402,0.4426,0.2434"); + } + + fall_constraint("SIG2SRAM_constraint_template") { + index_1("0.0056,0.0232,0.0400,0.0728,0.1280,0.2440,0.4760"); + index_2("0.0056,0.0232,0.0400,0.0728,0.1280,0.2440,0.4760"); + values ("0.2395,0.2238,0.2121,0.1809,0.1301,0.0324,-0.1551",\ +"0.2551,0.2395,0.2277,0.1965,0.1457,0.0480,-0.1395",\ +"0.2668,0.2551,0.2395,0.2082,0.1574,0.0637,-0.1277",\ +"0.3020,0.2863,0.2707,0.2395,0.1887,0.0910,-0.0965",\ +"0.3449,0.3293,0.3176,0.2863,0.2355,0.1379,-0.0496",\ +"0.4504,0.4348,0.4191,0.3879,0.3371,0.2395,0.0559",\ +"0.6457,0.6301,0.6145,0.5871,0.5324,0.4309,0.2512"); + } + } + } +pin(A_REN) { + direction : input ; + capacitance : 0.00381634 ; + max_transition : "0.476" ; + related_power_pin : VDD; + related_ground_pin : VSS; + internal_power() { + when : "A_MEN"; + rise_power("scalar"){ + values (0.0061); + } + fall_power("scalar"){ + values (0.0022); + } + } + internal_power() { + when : "!A_MEN"; + rise_power("scalar"){ + values (0.0064); + } + fall_power("scalar"){ + values (0.0027); + } + } + timing() { + timing_type : setup_rising; + related_pin : "A_CLK"; + when : "A_MEN" + sdf_cond : "A_MEN" + + rise_constraint("SIG2SRAM_constraint_template") { + index_1("0.0056,0.0232,0.0400,0.0728,0.1280,0.2440,0.4760"); + index_2("0.0056,0.0232,0.0400,0.0728,0.1280,0.2440,0.4760"); + values ("-0.0301,-0.0145,0.0012,0.0324,0.0793,0.1809,0.3762",\ +"-0.0457,-0.0301,-0.0145,0.0168,0.0637,0.1613,0.3605",\ +"-0.0574,-0.0418,-0.0262,0.0051,0.0520,0.1496,0.3449",\ +"-0.0926,-0.0730,-0.0574,-0.0262,0.0207,0.1184,0.3137",\ +"-0.1395,-0.1238,-0.1082,-0.0770,-0.0301,0.0715,0.2707",\ +"-0.2410,-0.2254,-0.2098,-0.1746,-0.1355,-0.0340,0.1652",\ +"-0.4402,-0.4207,-0.4051,-0.3738,-0.3270,-0.2293,-0.0340"); + } + + fall_constraint("SIG2SRAM_constraint_template") { + index_1("0.0056,0.0232,0.0400,0.0728,0.1280,0.2440,0.4760"); + index_2("0.0056,0.0232,0.0400,0.0728,0.1280,0.2440,0.4760"); + values ("0.0988,0.1145,0.1262,0.1535,0.2043,0.3020,0.4855",\ +"0.0832,0.0988,0.1105,0.1418,0.1848,0.2824,0.4738",\ +"0.0676,0.0832,0.0949,0.1262,0.1730,0.2668,0.4621",\ +"0.0402,0.0559,0.0676,0.0988,0.1457,0.2434,0.4191",\ +"-0.0105,0.0012,0.0168,0.0480,0.0988,0.1965,0.3840",\ +"-0.1160,-0.0965,-0.0848,-0.0535,-0.0066,0.0988,0.2824",\ +"-0.3113,-0.2957,-0.2801,-0.2527,-0.2059,-0.1043,0.0832"); + } + } + + + timing() { + timing_type : hold_rising; + related_pin : "A_CLK"; + when : "A_MEN" + sdf_cond : "A_MEN" + + rise_constraint("SIG2SRAM_constraint_template") { + index_1("0.0056,0.0232,0.0400,0.0728,0.1280,0.2440,0.4760"); + index_2("0.0056,0.0232,0.0400,0.0728,0.1280,0.2440,0.4760"); + values ("0.2707,0.2551,0.2395,0.2121,0.1613,0.0598,-0.1395",\ +"0.2863,0.2707,0.2551,0.2238,0.1730,0.0715,-0.1238",\ +"0.2980,0.2824,0.2668,0.2395,0.1887,0.0871,-0.1121",\ +"0.3332,0.3176,0.3020,0.2707,0.2199,0.1184,-0.0809",\ +"0.3762,0.3605,0.3449,0.3176,0.2668,0.1613,-0.0340",\ +"0.4816,0.4621,0.4504,0.4191,0.3723,0.2629,0.0715",\ +"0.6770,0.6613,0.6418,0.6184,0.5637,0.4699,0.2629"); + } + + fall_constraint("SIG2SRAM_constraint_template") { + index_1("0.0056,0.0232,0.0400,0.0728,0.1280,0.2440,0.4760"); + index_2("0.0056,0.0232,0.0400,0.0728,0.1280,0.2440,0.4760"); + values ("0.2590,0.2434,0.2316,0.2004,0.1457,0.0520,-0.1355",\ +"0.2746,0.2590,0.2434,0.2160,0.1613,0.0676,-0.1199",\ +"0.2863,0.2707,0.2590,0.2277,0.1730,0.0832,-0.1082",\ +"0.3215,0.3059,0.2902,0.2590,0.2082,0.1105,-0.0770",\ +"0.3645,0.3488,0.3332,0.3059,0.2551,0.1535,-0.0340",\ +"0.4699,0.4543,0.4387,0.4074,0.3605,0.2551,0.0715",\ +"0.6652,0.6496,0.6340,0.6027,0.5520,0.4621,0.2707"); + } + } + } +pin(A_MEN) { + direction : input ; + capacitance : 0.00309605 ; + max_transition : "0.476" ; + related_power_pin : VDD; + related_ground_pin : VSS; + internal_power() { + rise_power("scalar"){ + values (0.0870); + } + fall_power("scalar"){ + values (0.0053); + } + } + timing() { + timing_type : setup_rising; + related_pin : "A_CLK"; + + rise_constraint("SIG2SRAM_constraint_template") { + index_1("0.0056,0.0232,0.0400,0.0728,0.1280,0.2440,0.4760"); + index_2("0.0056,0.0232,0.0400,0.0728,0.1280,0.2440,0.4760"); + values ("0.2043,0.2199,0.2316,0.2668,0.3098,0.4152,0.6066",\ +"0.1887,0.2043,0.2199,0.2512,0.2941,0.3996,0.5949",\ +"0.1730,0.1887,0.2043,0.2355,0.2824,0.3840,0.5793",\ +"0.1418,0.1574,0.1730,0.2043,0.2512,0.3566,0.5480",\ +"0.0949,0.1105,0.1262,0.1574,0.2043,0.3020,0.5051",\ +"-0.0066,0.0090,0.0246,0.0520,0.0988,0.2043,0.3996",\ +"-0.2020,-0.1863,-0.1746,-0.1434,-0.0965,0.0090,0.2082"); + } + + fall_constraint("SIG2SRAM_constraint_template") { + index_1("0.0056,0.0232,0.0400,0.0728,0.1280,0.2440,0.4760"); + index_2("0.0056,0.0232,0.0400,0.0728,0.1280,0.2440,0.4760"); + values ("0.2980,0.3137,0.3254,0.3527,0.4035,0.5012,0.6887",\ +"0.2824,0.2980,0.3098,0.3371,0.3879,0.4855,0.6730",\ +"0.2668,0.2824,0.2941,0.3215,0.3723,0.4699,0.6574",\ +"0.2355,0.2473,0.2629,0.2902,0.3410,0.4387,0.6262",\ +"0.1887,0.2004,0.2160,0.2395,0.2941,0.3918,0.5793",\ +"0.0871,0.1027,0.1145,0.1418,0.1848,0.2746,0.4816",\ +"-0.1082,-0.0965,-0.0809,-0.0496,-0.0027,0.0949,0.2863"); + } + } + + + timing() { + timing_type : hold_rising; + related_pin : "A_CLK"; + + rise_constraint("SIG2SRAM_constraint_template") { + index_1("0.0056,0.0232,0.0400,0.0728,0.1280,0.2440,0.4760"); + index_2("0.0056,0.0232,0.0400,0.0728,0.1280,0.2440,0.4760"); + values ("0.2512,0.2355,0.2199,0.1926,0.1418,0.0402,-0.1590",\ +"0.2668,0.2512,0.2355,0.2082,0.1574,0.0559,-0.1434",\ +"0.2824,0.2629,0.2512,0.2199,0.1691,0.0715,-0.1316",\ +"0.3137,0.2980,0.2824,0.2512,0.2004,0.0988,-0.0965",\ +"0.3566,0.3410,0.3254,0.2980,0.2473,0.1418,-0.0535",\ +"0.4621,0.4426,0.4309,0.3996,0.3527,0.2473,0.0520",\ +"0.6574,0.6418,0.6262,0.5949,0.5441,0.4465,0.2473"); + } + + fall_constraint("SIG2SRAM_constraint_template") { + index_1("0.0056,0.0232,0.0400,0.0728,0.1280,0.2440,0.4760"); + index_2("0.0056,0.0232,0.0400,0.0728,0.1280,0.2440,0.4760"); + values ("0.2395,0.2238,0.2121,0.1809,0.1301,0.0324,-0.1551",\ +"0.2551,0.2434,0.2277,0.1965,0.1457,0.0480,-0.1395",\ +"0.2707,0.2551,0.2395,0.2082,0.1574,0.0637,-0.1277",\ +"0.3020,0.2863,0.2707,0.2434,0.1926,0.0910,-0.0965",\ +"0.3449,0.3332,0.3176,0.2863,0.2355,0.1379,-0.0496",\ +"0.4504,0.4348,0.4230,0.3918,0.3410,0.2434,0.0559",\ +"0.6457,0.6301,0.6145,0.5910,0.5324,0.4387,0.2512"); + } + } + } +bus(A_BM) { + bus_type : D_31_0; + direction : input ; + capacitance : 0.00285703 ; + max_transition : "0.476" ; + pin(A_BM[31:0]) { + related_power_pin : VDD; + related_ground_pin : VSS; + internal_power() { + when : "A_MEN"; + rise_power("scalar"){ + values (0.1177); + } + fall_power("scalar"){ + values (0.0495); + } + } + internal_power() { + when : "!A_MEN"; + rise_power("scalar"){ + values (0.1175); + } + fall_power("scalar"){ + values (0.0489); + } + } + } + timing() { + timing_type : setup_rising; + related_pin : "A_CLK"; + when : "(A_WEN & A_MEN)" + sdf_cond : "A_RW_ACCESS" + + rise_constraint("SIG2SRAM_constraint_template") { + index_1("0.0056,0.0232,0.0400,0.0728,0.1280,0.2440,0.4760"); + index_2("0.0056,0.0232,0.0400,0.0728,0.1280,0.2440,0.4760"); + values ("-0.4430,-0.4264,-0.4137,-0.3815,-0.3346,-0.2301,-0.0377",\ +"-0.4480,-0.4314,-0.4187,-0.3865,-0.3396,-0.2351,-0.0427",\ +"-0.4524,-0.4358,-0.4231,-0.3909,-0.3440,-0.2395,-0.0472",\ +"-0.4623,-0.4457,-0.4330,-0.4008,-0.3539,-0.2494,-0.0570",\ +"-0.4686,-0.4520,-0.4393,-0.4071,-0.3602,-0.2557,-0.0634",\ +"-0.5051,-0.4885,-0.4758,-0.4436,-0.3967,-0.2922,-0.0998",\ +"-0.5560,-0.5394,-0.5267,-0.4945,-0.4476,-0.3431,-0.1507"); + } + + fall_constraint("SIG2SRAM_constraint_template") { + index_1("0.0056,0.0232,0.0400,0.0728,0.1280,0.2440,0.4760"); + index_2("0.0056,0.0232,0.0400,0.0728,0.1280,0.2440,0.4760"); + values ("-0.4108,-0.3952,-0.3825,-0.3541,-0.3034,-0.2047,-0.0260",\ +"-0.4158,-0.4002,-0.3875,-0.3591,-0.3084,-0.2097,-0.0310",\ +"-0.4202,-0.4046,-0.3919,-0.3636,-0.3128,-0.2142,-0.0355",\ +"-0.4301,-0.4144,-0.4017,-0.3734,-0.3226,-0.2240,-0.0453",\ +"-0.4364,-0.4208,-0.4081,-0.3798,-0.3290,-0.2303,-0.0516",\ +"-0.4729,-0.4573,-0.4446,-0.4163,-0.3655,-0.2668,-0.0881",\ +"-0.5238,-0.5081,-0.4954,-0.4671,-0.4163,-0.3177,-0.1390"); + } + } + + + timing() { + timing_type : hold_rising; + related_pin : "A_CLK"; + when : "(A_WEN & A_MEN)" + sdf_cond : "A_RW_ACCESS" + + rise_constraint("SIG2SRAM_constraint_template") { + index_1("0.0056,0.0232,0.0400,0.0728,0.1280,0.2440,0.4760"); + index_2("0.0056,0.0232,0.0400,0.0728,0.1280,0.2440,0.4760"); + values ("0.5521,0.5365,0.5238,0.4915,0.4427,0.3441,0.1478",\ +"0.5571,0.5415,0.5288,0.4966,0.4477,0.3491,0.1528",\ +"0.5615,0.5459,0.5332,0.5010,0.4522,0.3535,0.1572",\ +"0.5714,0.5558,0.5431,0.5108,0.4620,0.3634,0.1671",\ +"0.5777,0.5621,0.5494,0.5172,0.4683,0.3697,0.1734",\ +"0.6142,0.5986,0.5859,0.5537,0.5048,0.4062,0.2099",\ +"0.6651,0.6495,0.6368,0.6045,0.5557,0.4571,0.2608"); + } + + fall_constraint("SIG2SRAM_constraint_template") { + index_1("0.0056,0.0232,0.0400,0.0728,0.1280,0.2440,0.4760"); + index_2("0.0056,0.0232,0.0400,0.0728,0.1280,0.2440,0.4760"); + values ("0.5120,0.4974,0.4837,0.4554,0.4046,0.3119,0.1234",\ +"0.5171,0.5024,0.4887,0.4604,0.4096,0.3169,0.1284",\ +"0.5215,0.5069,0.4932,0.4648,0.4141,0.3213,0.1328",\ +"0.5313,0.5167,0.5030,0.4747,0.4239,0.3311,0.1427",\ +"0.5377,0.5230,0.5094,0.4810,0.4303,0.3375,0.1490",\ +"0.5742,0.5595,0.5459,0.5175,0.4667,0.3740,0.1855",\ +"0.6250,0.6104,0.5967,0.5684,0.5176,0.4249,0.2364"); + } + } +} + pin(A_CLK) { + direction : input; + capacitance : 0.00380014; + max_transition : "0.476"; + clock : "true" ; + pin_func_type : active_rising ; + + timing () { + timing_type : "min_pulse_width"; + related_pin : "A_CLK"; + rise_constraint("CLKTRAN_constraint_template") { + index_1("0.0056,0.476"); + values("0.21,0.21"); + } + } + + related_power_pin : VDD; + related_ground_pin : VSS; + + internal_power() { + when : "!A_MEN & !A_WEN & !A_REN"; + rise_power("scalar"){ + values (0); + } + fall_power("scalar"){ + values (0); + } + } + internal_power() { + when : "!A_MEN & A_WEN & !A_REN"; + rise_power("scalar"){ + values (0.5298); + } + fall_power("scalar"){ + values (0); + } + } + internal_power() { + when : "A_MEN & A_WEN & !A_REN"; + rise_power("scalar"){ + values (58.9183); + } + fall_power("scalar"){ + values (0); + } + } + internal_power() { + when : "A_MEN & A_WEN & A_REN"; + rise_power("scalar"){ + values (61.8765); + } + fall_power("scalar"){ + values (0); + } + } + internal_power() { + when : "A_MEN & !A_WEN & A_REN"; + rise_power("scalar"){ + values (48.2666); + } + fall_power("scalar"){ + values (0); + } + } + internal_power() { + when : "!A_MEN & !A_WEN & A_REN"; + rise_power("scalar"){ + values (0.3622); + } + fall_power("scalar"){ + values (0); + } + } + internal_power() { + when : "!A_MEN & A_WEN & A_REN"; + rise_power("scalar"){ + values (1.2134); + } + fall_power("scalar"){ + values (0); + } + } + internal_power() { + when : "A_MEN & !A_WEN & !A_REN"; + rise_power("scalar"){ + values (0); + } + fall_power("scalar"){ + values (0); + } + } + } + bus(A_DIN) { + bus_type : D_31_0; + direction : input ; + capacitance : 0.00365723 ; + memory_write() { + address : A_ADDR ; + clocked_on : A_CLK; + } + + max_transition : "0.476" ; + pin(A_DIN[31:0]) { + related_power_pin : VDD; + related_ground_pin : VSS; + internal_power() { + when : "A_MEN"; + rise_power("scalar"){ + values (0.1177); + } + fall_power("scalar"){ + values (0.0495); + } + } + internal_power() { + when : "!A_MEN"; + rise_power("scalar"){ + values (0.1175); + } + fall_power("scalar"){ + values (0.0489); + } + } + } + timing() { + timing_type : setup_rising; + related_pin : "A_CLK"; + when : "(A_WEN & A_MEN)"; + sdf_cond : "A_W_ACCESS"; + + rise_constraint("SIG2SRAM_constraint_template") { + index_1("0.0056,0.0232,0.0400,0.0728,0.1280,0.2440,0.4760"); + index_2("0.0056,0.0232,0.0400,0.0728,0.1280,0.2440,0.4760"); + values ("-0.4430,-0.4264,-0.4137,-0.3815,-0.3346,-0.2301,-0.0377",\ +"-0.4480,-0.4314,-0.4187,-0.3865,-0.3396,-0.2351,-0.0427",\ +"-0.4524,-0.4358,-0.4231,-0.3909,-0.3440,-0.2395,-0.0472",\ +"-0.4623,-0.4457,-0.4330,-0.4008,-0.3539,-0.2494,-0.0570",\ +"-0.4686,-0.4520,-0.4393,-0.4071,-0.3602,-0.2557,-0.0634",\ +"-0.5051,-0.4885,-0.4758,-0.4436,-0.3967,-0.2922,-0.0998",\ +"-0.5560,-0.5394,-0.5267,-0.4945,-0.4476,-0.3431,-0.1507"); + } + + fall_constraint("SIG2SRAM_constraint_template") { + index_1("0.0056,0.0232,0.0400,0.0728,0.1280,0.2440,0.4760"); + index_2("0.0056,0.0232,0.0400,0.0728,0.1280,0.2440,0.4760"); + values ("-0.4108,-0.3952,-0.3825,-0.3541,-0.3034,-0.2047,-0.0260",\ +"-0.4158,-0.4002,-0.3875,-0.3591,-0.3084,-0.2097,-0.0310",\ +"-0.4202,-0.4046,-0.3919,-0.3636,-0.3128,-0.2142,-0.0355",\ +"-0.4301,-0.4144,-0.4017,-0.3734,-0.3226,-0.2240,-0.0453",\ +"-0.4364,-0.4208,-0.4081,-0.3798,-0.3290,-0.2303,-0.0516",\ +"-0.4729,-0.4573,-0.4446,-0.4163,-0.3655,-0.2668,-0.0881",\ +"-0.5238,-0.5081,-0.4954,-0.4671,-0.4163,-0.3177,-0.1390"); + } + } + + timing() { + timing_type : hold_rising; + related_pin : "A_CLK"; + when : "(A_WEN & A_MEN)"; + sdf_cond : "A_W_ACCESS"; + + rise_constraint("SIG2SRAM_constraint_template") { + index_1("0.0056,0.0232,0.0400,0.0728,0.1280,0.2440,0.4760"); + index_2("0.0056,0.0232,0.0400,0.0728,0.1280,0.2440,0.4760"); + values ("0.5521,0.5365,0.5238,0.4915,0.4427,0.3441,0.1478",\ +"0.5571,0.5415,0.5288,0.4966,0.4477,0.3491,0.1528",\ +"0.5615,0.5459,0.5332,0.5010,0.4522,0.3535,0.1572",\ +"0.5714,0.5558,0.5431,0.5108,0.4620,0.3634,0.1671",\ +"0.5777,0.5621,0.5494,0.5172,0.4683,0.3697,0.1734",\ +"0.6142,0.5986,0.5859,0.5537,0.5048,0.4062,0.2099",\ +"0.6651,0.6495,0.6368,0.6045,0.5557,0.4571,0.2608"); + } + + fall_constraint("SIG2SRAM_constraint_template") { + index_1("0.0056,0.0232,0.0400,0.0728,0.1280,0.2440,0.4760"); + index_2("0.0056,0.0232,0.0400,0.0728,0.1280,0.2440,0.4760"); + values ("0.5120,0.4974,0.4837,0.4554,0.4046,0.3119,0.1234",\ +"0.5171,0.5024,0.4887,0.4604,0.4096,0.3169,0.1284",\ +"0.5215,0.5069,0.4932,0.4648,0.4141,0.3213,0.1328",\ +"0.5313,0.5167,0.5030,0.4747,0.4239,0.3311,0.1427",\ +"0.5377,0.5230,0.5094,0.4810,0.4303,0.3375,0.1490",\ +"0.5742,0.5595,0.5459,0.5175,0.4667,0.3740,0.1855",\ +"0.6250,0.6104,0.5967,0.5684,0.5176,0.4249,0.2364"); + } + } + } + + pin(A_BIST_EN) { + direction : input ; + capacitance : 0.00401111 ; + max_transition : "1" ; + related_power_pin : VDD; + related_ground_pin : VSS; + internal_power() { + rise_power("scalar") { + values (0); + } + fall_power("scalar") { + values (0); + } + } + } + +bus(A_BIST_ADDR) { + bus_type : A_9_0; + direction : input ; + capacitance : 0.00721489 ; + pin(A_BIST_ADDR[0]) { + capacitance : 0.00593979 ; + } + pin(A_BIST_ADDR[1]) { + capacitance : 0.00483009 ; + } + pin(A_BIST_ADDR[2]) { + capacitance : 0.006215 ; + } + pin(A_BIST_ADDR[3]) { + capacitance : 0.00766726 ; + } + pin(A_BIST_ADDR[4]) { + capacitance : 0.00488951 ; + } + pin(A_BIST_ADDR[5]) { + capacitance : 0.0091523 ; + } + pin(A_BIST_ADDR[6]) { + capacitance : 0.0109212 ; + } + pin(A_BIST_ADDR[7]) { + capacitance : 0.00774122 ; + } + pin(A_BIST_ADDR[8]) { + capacitance : 0.0101403 ; + } + max_transition : "0.476" ; + pin(A_BIST_ADDR[9:0]) { + related_power_pin : VDD; + related_ground_pin : VSS; + internal_power() { + when : "A_BIST_MEN"; + rise_power("scalar"){ + values (0.0115); + } + fall_power("scalar"){ + values (0.0061); + } + } + internal_power() { + when : "!A_BIST_MEN"; + rise_power("scalar"){ + values (0.0201); + } + fall_power("scalar"){ + values (0.0005); + } + } + } + timing() { + timing_type : setup_rising; + related_pin : "A_BIST_CLK"; + when : "((A_BIST_WEN | A_BIST_REN)& A_BIST_MEN)" + sdf_cond : "A_BIST_RW_ACCESS" + + rise_constraint("SIG2SRAM_constraint_template") { + index_1("0.0056,0.0232,0.0400,0.0728,0.1280,0.2440,0.4760"); + index_2("0.0056,0.0232,0.0400,0.0728,0.1280,0.2440,0.4760"); + values ("-0.4168,-0.3973,-0.3855,-0.3543,-0.3074,-0.2020,-0.0027",\ +"-0.4324,-0.4129,-0.4012,-0.3699,-0.3191,-0.2176,-0.0184",\ +"-0.4441,-0.4285,-0.4129,-0.3816,-0.3309,-0.2293,-0.0301",\ +"-0.4793,-0.4598,-0.4441,-0.4129,-0.3660,-0.2645,-0.0652",\ +"-0.5223,-0.5066,-0.4910,-0.4598,-0.4129,-0.3074,-0.1121",\ +"-0.6199,-0.6082,-0.5926,-0.5613,-0.5145,-0.4129,-0.2137",\ +"-0.8191,-0.8074,-0.7840,-0.7566,-0.7098,-0.6082,-0.4051"); + } + + fall_constraint("SIG2SRAM_constraint_template") { + index_1("0.0056,0.0232,0.0400,0.0728,0.1280,0.2440,0.4760"); + index_2("0.0056,0.0232,0.0400,0.0728,0.1280,0.2440,0.4760"); + values ("-0.3309,-0.3113,-0.2996,-0.2684,-0.2176,-0.1238,0.0637",\ +"-0.3465,-0.3309,-0.3152,-0.2840,-0.2332,-0.1395,0.0480",\ +"-0.3582,-0.3426,-0.3270,-0.2996,-0.2488,-0.1512,0.0324",\ +"-0.3895,-0.3738,-0.3582,-0.3309,-0.2801,-0.1863,0.0051",\ +"-0.4363,-0.4207,-0.4051,-0.3777,-0.3230,-0.2293,-0.0379",\ +"-0.5379,-0.5223,-0.5066,-0.4793,-0.4285,-0.3309,-0.1434",\ +"-0.7332,-0.7176,-0.7020,-0.6746,-0.6238,-0.5262,-0.3387"); + } + } + + + timing() { + timing_type : hold_rising; + related_pin : "A_BIST_CLK"; + when : "((A_BIST_WEN | A_BIST_REN)& A_BIST_MEN)" + sdf_cond : "A_BIST_RW_ACCESS" + + rise_constraint("SIG2SRAM_constraint_template") { + index_1("0.0056,0.0232,0.0400,0.0728,0.1280,0.2440,0.4760"); + index_2("0.0056,0.0232,0.0400,0.0728,0.1280,0.2440,0.4760"); + values ("0.5246,0.5051,0.4895,0.4582,0.4113,0.3059,0.1066",\ +"0.5402,0.5207,0.5051,0.4777,0.4270,0.3215,0.1223",\ +"0.5520,0.5324,0.5168,0.4895,0.4387,0.3371,0.1340",\ +"0.5832,0.5676,0.5520,0.5207,0.4738,0.3684,0.1691",\ +"0.6301,0.6105,0.5949,0.5676,0.5168,0.4113,0.2160",\ +"0.7316,0.7121,0.7004,0.6691,0.6223,0.5168,0.3176",\ +"0.9270,0.9230,0.8957,0.8645,0.8137,0.7121,0.5168"); + } + + fall_constraint("SIG2SRAM_constraint_template") { + index_1("0.0056,0.0232,0.0400,0.0728,0.1280,0.2440,0.4760"); + index_2("0.0056,0.0232,0.0400,0.0728,0.1280,0.2440,0.4760"); + values ("0.4309,0.4152,0.4035,0.3684,0.3215,0.2277,0.0363",\ +"0.4465,0.4309,0.4152,0.3879,0.3371,0.2395,0.0559",\ +"0.4582,0.4426,0.4309,0.3996,0.3488,0.2551,0.0715",\ +"0.4934,0.4777,0.4621,0.4348,0.3840,0.2863,0.0988",\ +"0.5363,0.5207,0.5051,0.4777,0.4270,0.3332,0.1418",\ +"0.6379,0.6262,0.6105,0.5793,0.5324,0.4348,0.2434",\ +"0.8332,0.8215,0.8059,0.7707,0.7238,0.6301,0.4387"); + } + } +} +pin(A_BIST_WEN) { + direction : input ; + capacitance : 0.00324098 ; + max_transition : "0.476" ; + related_power_pin : VDD; + related_ground_pin : VSS; + internal_power() { + when : "A_BIST_MEN"; + rise_power("scalar"){ + values (0.0046); + } + fall_power("scalar"){ + values (0.0040); + } + } + internal_power() { + when : "!A_BIST_MEN"; + rise_power("scalar"){ + values (0.0045); + } + fall_power("scalar"){ + values (0.0043); + } + } + timing() { + timing_type : setup_rising; + related_pin : "A_BIST_CLK"; + when : "A_BIST_MEN" + sdf_cond : "A_BIST_MEN" + + rise_constraint("SIG2SRAM_constraint_template") { + index_1("0.0056,0.0232,0.0400,0.0728,0.1280,0.2440,0.4760"); + index_2("0.0056,0.0232,0.0400,0.0728,0.1280,0.2440,0.4760"); + values ("0.2043,0.2199,0.2316,0.2629,0.3059,0.4113,0.6066",\ +"0.1887,0.2043,0.2160,0.2473,0.2941,0.3957,0.5949",\ +"0.1691,0.1848,0.2004,0.2316,0.2785,0.3801,0.5754",\ +"0.1379,0.1574,0.1691,0.2004,0.2473,0.3527,0.5480",\ +"0.0910,0.1066,0.1223,0.1535,0.2004,0.2980,0.4973",\ +"-0.0105,0.0051,0.0207,0.0520,0.0949,0.2004,0.3957",\ +"-0.2059,-0.1902,-0.1746,-0.1473,-0.1004,0.0051,0.2004"); + } + + fall_constraint("SIG2SRAM_constraint_template") { + index_1("0.0056,0.0232,0.0400,0.0728,0.1280,0.2440,0.4760"); + index_2("0.0056,0.0232,0.0400,0.0728,0.1280,0.2440,0.4760"); + values ("0.2941,0.3098,0.3215,0.3488,0.4035,0.4973,0.6887",\ +"0.2785,0.2941,0.3059,0.3332,0.3840,0.4816,0.6691",\ +"0.2629,0.2785,0.2902,0.3176,0.3684,0.4660,0.6535",\ +"0.2316,0.2473,0.2590,0.2863,0.3410,0.4348,0.6262",\ +"0.1848,0.2004,0.2121,0.2395,0.2902,0.3879,0.5754",\ +"0.0832,0.0988,0.1105,0.1379,0.1809,0.2746,0.4699",\ +"-0.1121,-0.0965,-0.0848,-0.0535,-0.0066,0.0910,0.2824"); + } + } + + + timing() { + timing_type : hold_rising; + related_pin : "A_BIST_CLK"; + when : "A_BIST_MEN" + sdf_cond : "A_BIST_MEN" + + rise_constraint("SIG2SRAM_constraint_template") { + index_1("0.0056,0.0232,0.0400,0.0728,0.1280,0.2440,0.4760"); + index_2("0.0056,0.0232,0.0400,0.0728,0.1280,0.2440,0.4760"); + values ("0.2473,0.2316,0.2160,0.1887,0.1379,0.0363,-0.1629",\ +"0.2629,0.2473,0.2316,0.2043,0.1535,0.0520,-0.1473",\ +"0.2785,0.2590,0.2434,0.2160,0.1652,0.0676,-0.1355",\ +"0.3098,0.2941,0.2785,0.2473,0.1965,0.0910,-0.1043",\ +"0.3527,0.3371,0.3215,0.2941,0.2434,0.1418,-0.0574",\ +"0.4582,0.4426,0.4270,0.3957,0.3488,0.2434,0.0480",\ +"0.6535,0.6379,0.6184,0.5910,0.5402,0.4426,0.2434"); + } + + fall_constraint("SIG2SRAM_constraint_template") { + index_1("0.0056,0.0232,0.0400,0.0728,0.1280,0.2440,0.4760"); + index_2("0.0056,0.0232,0.0400,0.0728,0.1280,0.2440,0.4760"); + values ("0.2395,0.2238,0.2121,0.1809,0.1301,0.0324,-0.1551",\ +"0.2551,0.2395,0.2277,0.1965,0.1457,0.0480,-0.1395",\ +"0.2668,0.2551,0.2395,0.2082,0.1574,0.0637,-0.1277",\ +"0.3020,0.2863,0.2707,0.2395,0.1887,0.0910,-0.0965",\ +"0.3449,0.3293,0.3176,0.2863,0.2355,0.1379,-0.0496",\ +"0.4504,0.4348,0.4191,0.3879,0.3371,0.2395,0.0559",\ +"0.6457,0.6301,0.6145,0.5871,0.5324,0.4309,0.2512"); + } + } + } +pin(A_BIST_REN) { + direction : input ; + capacitance : 0.00381634 ; + max_transition : "0.476" ; + related_power_pin : VDD; + related_ground_pin : VSS; + internal_power() { + when : "A_BIST_MEN"; + rise_power("scalar"){ + values (0.0061); + } + fall_power("scalar"){ + values (0.0022); + } + } + internal_power() { + when : "!A_BIST_MEN"; + rise_power("scalar"){ + values (0.0064); + } + fall_power("scalar"){ + values (0.0027); + } + } + timing() { + timing_type : setup_rising; + related_pin : "A_BIST_CLK"; + when : "A_BIST_MEN" + sdf_cond : "A_BIST_MEN" + + rise_constraint("SIG2SRAM_constraint_template") { + index_1("0.0056,0.0232,0.0400,0.0728,0.1280,0.2440,0.4760"); + index_2("0.0056,0.0232,0.0400,0.0728,0.1280,0.2440,0.4760"); + values ("-0.0301,-0.0145,0.0012,0.0324,0.0793,0.1809,0.3762",\ +"-0.0457,-0.0301,-0.0145,0.0168,0.0637,0.1613,0.3605",\ +"-0.0574,-0.0418,-0.0262,0.0051,0.0520,0.1496,0.3449",\ +"-0.0926,-0.0730,-0.0574,-0.0262,0.0207,0.1184,0.3137",\ +"-0.1395,-0.1238,-0.1082,-0.0770,-0.0301,0.0715,0.2707",\ +"-0.2410,-0.2254,-0.2098,-0.1746,-0.1355,-0.0340,0.1652",\ +"-0.4402,-0.4207,-0.4051,-0.3738,-0.3270,-0.2293,-0.0340"); + } + + fall_constraint("SIG2SRAM_constraint_template") { + index_1("0.0056,0.0232,0.0400,0.0728,0.1280,0.2440,0.4760"); + index_2("0.0056,0.0232,0.0400,0.0728,0.1280,0.2440,0.4760"); + values ("0.0988,0.1145,0.1262,0.1535,0.2043,0.3020,0.4855",\ +"0.0832,0.0988,0.1105,0.1418,0.1848,0.2824,0.4738",\ +"0.0676,0.0832,0.0949,0.1262,0.1730,0.2668,0.4621",\ +"0.0402,0.0559,0.0676,0.0988,0.1457,0.2434,0.4191",\ +"-0.0105,0.0012,0.0168,0.0480,0.0988,0.1965,0.3840",\ +"-0.1160,-0.0965,-0.0848,-0.0535,-0.0066,0.0988,0.2824",\ +"-0.3113,-0.2957,-0.2801,-0.2527,-0.2059,-0.1043,0.0832"); + } + } + + + timing() { + timing_type : hold_rising; + related_pin : "A_BIST_CLK"; + when : "A_BIST_MEN" + sdf_cond : "A_BIST_MEN" + + rise_constraint("SIG2SRAM_constraint_template") { + index_1("0.0056,0.0232,0.0400,0.0728,0.1280,0.2440,0.4760"); + index_2("0.0056,0.0232,0.0400,0.0728,0.1280,0.2440,0.4760"); + values ("0.2707,0.2551,0.2395,0.2121,0.1613,0.0598,-0.1395",\ +"0.2863,0.2707,0.2551,0.2238,0.1730,0.0715,-0.1238",\ +"0.2980,0.2824,0.2668,0.2395,0.1887,0.0871,-0.1121",\ +"0.3332,0.3176,0.3020,0.2707,0.2199,0.1184,-0.0809",\ +"0.3762,0.3605,0.3449,0.3176,0.2668,0.1613,-0.0340",\ +"0.4816,0.4621,0.4504,0.4191,0.3723,0.2629,0.0715",\ +"0.6770,0.6613,0.6418,0.6184,0.5637,0.4699,0.2629"); + } + + fall_constraint("SIG2SRAM_constraint_template") { + index_1("0.0056,0.0232,0.0400,0.0728,0.1280,0.2440,0.4760"); + index_2("0.0056,0.0232,0.0400,0.0728,0.1280,0.2440,0.4760"); + values ("0.2590,0.2434,0.2316,0.2004,0.1457,0.0520,-0.1355",\ +"0.2746,0.2590,0.2434,0.2160,0.1613,0.0676,-0.1199",\ +"0.2863,0.2707,0.2590,0.2277,0.1730,0.0832,-0.1082",\ +"0.3215,0.3059,0.2902,0.2590,0.2082,0.1105,-0.0770",\ +"0.3645,0.3488,0.3332,0.3059,0.2551,0.1535,-0.0340",\ +"0.4699,0.4543,0.4387,0.4074,0.3605,0.2551,0.0715",\ +"0.6652,0.6496,0.6340,0.6027,0.5520,0.4621,0.2707"); + } + } + } +pin(A_BIST_MEN) { + direction : input ; + capacitance : 0.00309605 ; + max_transition : "0.476" ; + related_power_pin : VDD; + related_ground_pin : VSS; + internal_power() { + rise_power("scalar"){ + values (0.0870); + } + fall_power("scalar"){ + values (0.0053); + } + } + timing() { + timing_type : setup_rising; + related_pin : "A_BIST_CLK"; + + rise_constraint("SIG2SRAM_constraint_template") { + index_1("0.0056,0.0232,0.0400,0.0728,0.1280,0.2440,0.4760"); + index_2("0.0056,0.0232,0.0400,0.0728,0.1280,0.2440,0.4760"); + values ("0.2043,0.2199,0.2316,0.2668,0.3098,0.4152,0.6066",\ +"0.1887,0.2043,0.2199,0.2512,0.2941,0.3996,0.5949",\ +"0.1730,0.1887,0.2043,0.2355,0.2824,0.3840,0.5793",\ +"0.1418,0.1574,0.1730,0.2043,0.2512,0.3566,0.5480",\ +"0.0949,0.1105,0.1262,0.1574,0.2043,0.3020,0.5051",\ +"-0.0066,0.0090,0.0246,0.0520,0.0988,0.2043,0.3996",\ +"-0.2020,-0.1863,-0.1746,-0.1434,-0.0965,0.0090,0.2082"); + } + + fall_constraint("SIG2SRAM_constraint_template") { + index_1("0.0056,0.0232,0.0400,0.0728,0.1280,0.2440,0.4760"); + index_2("0.0056,0.0232,0.0400,0.0728,0.1280,0.2440,0.4760"); + values ("0.2980,0.3137,0.3254,0.3527,0.4035,0.5012,0.6887",\ +"0.2824,0.2980,0.3098,0.3371,0.3879,0.4855,0.6730",\ +"0.2668,0.2824,0.2941,0.3215,0.3723,0.4699,0.6574",\ +"0.2355,0.2473,0.2629,0.2902,0.3410,0.4387,0.6262",\ +"0.1887,0.2004,0.2160,0.2395,0.2941,0.3918,0.5793",\ +"0.0871,0.1027,0.1145,0.1418,0.1848,0.2746,0.4816",\ +"-0.1082,-0.0965,-0.0809,-0.0496,-0.0027,0.0949,0.2863"); + } + } + + + timing() { + timing_type : hold_rising; + related_pin : "A_BIST_CLK"; + + rise_constraint("SIG2SRAM_constraint_template") { + index_1("0.0056,0.0232,0.0400,0.0728,0.1280,0.2440,0.4760"); + index_2("0.0056,0.0232,0.0400,0.0728,0.1280,0.2440,0.4760"); + values ("0.2512,0.2355,0.2199,0.1926,0.1418,0.0402,-0.1590",\ +"0.2668,0.2512,0.2355,0.2082,0.1574,0.0559,-0.1434",\ +"0.2824,0.2629,0.2512,0.2199,0.1691,0.0715,-0.1316",\ +"0.3137,0.2980,0.2824,0.2512,0.2004,0.0988,-0.0965",\ +"0.3566,0.3410,0.3254,0.2980,0.2473,0.1418,-0.0535",\ +"0.4621,0.4426,0.4309,0.3996,0.3527,0.2473,0.0520",\ +"0.6574,0.6418,0.6262,0.5949,0.5441,0.4465,0.2473"); + } + + fall_constraint("SIG2SRAM_constraint_template") { + index_1("0.0056,0.0232,0.0400,0.0728,0.1280,0.2440,0.4760"); + index_2("0.0056,0.0232,0.0400,0.0728,0.1280,0.2440,0.4760"); + values ("0.2395,0.2238,0.2121,0.1809,0.1301,0.0324,-0.1551",\ +"0.2551,0.2434,0.2277,0.1965,0.1457,0.0480,-0.1395",\ +"0.2707,0.2551,0.2395,0.2082,0.1574,0.0637,-0.1277",\ +"0.3020,0.2863,0.2707,0.2434,0.1926,0.0910,-0.0965",\ +"0.3449,0.3332,0.3176,0.2863,0.2355,0.1379,-0.0496",\ +"0.4504,0.4348,0.4230,0.3918,0.3410,0.2434,0.0559",\ +"0.6457,0.6301,0.6145,0.5910,0.5324,0.4387,0.2512"); + } + } + } +bus(A_BIST_BM) { + bus_type : D_31_0; + direction : input ; + capacitance : 0.00238379 ; + max_transition : "0.476" ; + pin(A_BIST_BM[31:0]) { + related_power_pin : VDD; + related_ground_pin : VSS; + internal_power() { + when : "A_BIST_MEN"; + rise_power("scalar"){ + values (0.1177); + } + fall_power("scalar"){ + values (0.0495); + } + } + internal_power() { + when : "!A_BIST_MEN"; + rise_power("scalar"){ + values (0.1175); + } + fall_power("scalar"){ + values (0.0489); + } + } + } + timing() { + timing_type : setup_rising; + related_pin : "A_BIST_CLK"; + when : "(A_BIST_WEN & A_BIST_MEN)" + sdf_cond : "A_BIST_RW_ACCESS" + + rise_constraint("SIG2SRAM_constraint_template") { + index_1("0.0056,0.0232,0.0400,0.0728,0.1280,0.2440,0.4760"); + index_2("0.0056,0.0232,0.0400,0.0728,0.1280,0.2440,0.4760"); + values ("-0.4430,-0.4264,-0.4137,-0.3815,-0.3346,-0.2301,-0.0377",\ +"-0.4480,-0.4314,-0.4187,-0.3865,-0.3396,-0.2351,-0.0427",\ +"-0.4524,-0.4358,-0.4231,-0.3909,-0.3440,-0.2395,-0.0472",\ +"-0.4623,-0.4457,-0.4330,-0.4008,-0.3539,-0.2494,-0.0570",\ +"-0.4686,-0.4520,-0.4393,-0.4071,-0.3602,-0.2557,-0.0634",\ +"-0.5051,-0.4885,-0.4758,-0.4436,-0.3967,-0.2922,-0.0998",\ +"-0.5560,-0.5394,-0.5267,-0.4945,-0.4476,-0.3431,-0.1507"); + } + + fall_constraint("SIG2SRAM_constraint_template") { + index_1("0.0056,0.0232,0.0400,0.0728,0.1280,0.2440,0.4760"); + index_2("0.0056,0.0232,0.0400,0.0728,0.1280,0.2440,0.4760"); + values ("-0.4108,-0.3952,-0.3825,-0.3541,-0.3034,-0.2047,-0.0260",\ +"-0.4158,-0.4002,-0.3875,-0.3591,-0.3084,-0.2097,-0.0310",\ +"-0.4202,-0.4046,-0.3919,-0.3636,-0.3128,-0.2142,-0.0355",\ +"-0.4301,-0.4144,-0.4017,-0.3734,-0.3226,-0.2240,-0.0453",\ +"-0.4364,-0.4208,-0.4081,-0.3798,-0.3290,-0.2303,-0.0516",\ +"-0.4729,-0.4573,-0.4446,-0.4163,-0.3655,-0.2668,-0.0881",\ +"-0.5238,-0.5081,-0.4954,-0.4671,-0.4163,-0.3177,-0.1390"); + } + } + + + timing() { + timing_type : hold_rising; + related_pin : "A_BIST_CLK"; + when : "(A_BIST_WEN & A_BIST_MEN)" + sdf_cond : "A_BIST_RW_ACCESS" + + rise_constraint("SIG2SRAM_constraint_template") { + index_1("0.0056,0.0232,0.0400,0.0728,0.1280,0.2440,0.4760"); + index_2("0.0056,0.0232,0.0400,0.0728,0.1280,0.2440,0.4760"); + values ("0.5521,0.5365,0.5238,0.4915,0.4427,0.3441,0.1478",\ +"0.5571,0.5415,0.5288,0.4966,0.4477,0.3491,0.1528",\ +"0.5615,0.5459,0.5332,0.5010,0.4522,0.3535,0.1572",\ +"0.5714,0.5558,0.5431,0.5108,0.4620,0.3634,0.1671",\ +"0.5777,0.5621,0.5494,0.5172,0.4683,0.3697,0.1734",\ +"0.6142,0.5986,0.5859,0.5537,0.5048,0.4062,0.2099",\ +"0.6651,0.6495,0.6368,0.6045,0.5557,0.4571,0.2608"); + } + + fall_constraint("SIG2SRAM_constraint_template") { + index_1("0.0056,0.0232,0.0400,0.0728,0.1280,0.2440,0.4760"); + index_2("0.0056,0.0232,0.0400,0.0728,0.1280,0.2440,0.4760"); + values ("0.5120,0.4974,0.4837,0.4554,0.4046,0.3119,0.1234",\ +"0.5171,0.5024,0.4887,0.4604,0.4096,0.3169,0.1284",\ +"0.5215,0.5069,0.4932,0.4648,0.4141,0.3213,0.1328",\ +"0.5313,0.5167,0.5030,0.4747,0.4239,0.3311,0.1427",\ +"0.5377,0.5230,0.5094,0.4810,0.4303,0.3375,0.1490",\ +"0.5742,0.5595,0.5459,0.5175,0.4667,0.3740,0.1855",\ +"0.6250,0.6104,0.5967,0.5684,0.5176,0.4249,0.2364"); + } + } +} + pin(A_BIST_CLK) { + direction : input; + capacitance : 0.00380014; + max_transition : "0.476"; + clock : "true" ; + pin_func_type : active_rising ; + + timing () { + timing_type : "min_pulse_width"; + related_pin : "A_BIST_CLK"; + rise_constraint("CLKTRAN_constraint_template") { + index_1("0.0056,0.476"); + values("0.21,0.21"); + } + } + + related_power_pin : VDD; + related_ground_pin : VSS; + + internal_power() { + when : "!A_BIST_MEN & !A_BIST_WEN & !A_BIST_REN"; + rise_power("scalar"){ + values (0); + } + fall_power("scalar"){ + values (0); + } + } + internal_power() { + when : "!A_BIST_MEN & A_BIST_WEN & !A_BIST_REN"; + rise_power("scalar"){ + values (0.5298); + } + fall_power("scalar"){ + values (0); + } + } + internal_power() { + when : "A_BIST_MEN & A_BIST_WEN & !A_BIST_REN"; + rise_power("scalar"){ + values (58.9183); + } + fall_power("scalar"){ + values (0); + } + } + internal_power() { + when : "A_BIST_MEN & A_BIST_WEN & A_BIST_REN"; + rise_power("scalar"){ + values (61.8765); + } + fall_power("scalar"){ + values (0); + } + } + internal_power() { + when : "A_BIST_MEN & !A_BIST_WEN & A_BIST_REN"; + rise_power("scalar"){ + values (48.2666); + } + fall_power("scalar"){ + values (0); + } + } + internal_power() { + when : "!A_BIST_MEN & !A_BIST_WEN & A_BIST_REN"; + rise_power("scalar"){ + values (0.3622); + } + fall_power("scalar"){ + values (0); + } + } + internal_power() { + when : "!A_BIST_MEN & A_BIST_WEN & A_BIST_REN"; + rise_power("scalar"){ + values (1.2134); + } + fall_power("scalar"){ + values (0); + } + } + internal_power() { + when : "A_BIST_MEN & !A_BIST_WEN & !A_BIST_REN"; + rise_power("scalar"){ + values (0); + } + fall_power("scalar"){ + values (0); + } + } + } + bus(A_BIST_DIN) { + bus_type : D_31_0; + direction : input ; + capacitance : 0.00233858 ; + memory_write() { + address : A_BIST_ADDR ; + clocked_on : A_BIST_CLK; + } + + max_transition : "0.476" ; + pin(A_BIST_DIN[31:0]) { + related_power_pin : VDD; + related_ground_pin : VSS; + internal_power() { + when : "A_BIST_MEN"; + rise_power("scalar"){ + values (0.1177); + } + fall_power("scalar"){ + values (0.0495); + } + } + internal_power() { + when : "!A_BIST_MEN"; + rise_power("scalar"){ + values (0.1175); + } + fall_power("scalar"){ + values (0.0489); + } + } + } + timing() { + timing_type : setup_rising; + related_pin : "A_BIST_CLK"; + when : "(A_BIST_WEN & A_BIST_MEN)"; + sdf_cond : "A_BIST_W_ACCESS"; + + rise_constraint("SIG2SRAM_constraint_template") { + index_1("0.0056,0.0232,0.0400,0.0728,0.1280,0.2440,0.4760"); + index_2("0.0056,0.0232,0.0400,0.0728,0.1280,0.2440,0.4760"); + values ("-0.4430,-0.4264,-0.4137,-0.3815,-0.3346,-0.2301,-0.0377",\ +"-0.4480,-0.4314,-0.4187,-0.3865,-0.3396,-0.2351,-0.0427",\ +"-0.4524,-0.4358,-0.4231,-0.3909,-0.3440,-0.2395,-0.0472",\ +"-0.4623,-0.4457,-0.4330,-0.4008,-0.3539,-0.2494,-0.0570",\ +"-0.4686,-0.4520,-0.4393,-0.4071,-0.3602,-0.2557,-0.0634",\ +"-0.5051,-0.4885,-0.4758,-0.4436,-0.3967,-0.2922,-0.0998",\ +"-0.5560,-0.5394,-0.5267,-0.4945,-0.4476,-0.3431,-0.1507"); + } + + fall_constraint("SIG2SRAM_constraint_template") { + index_1("0.0056,0.0232,0.0400,0.0728,0.1280,0.2440,0.4760"); + index_2("0.0056,0.0232,0.0400,0.0728,0.1280,0.2440,0.4760"); + values ("-0.4108,-0.3952,-0.3825,-0.3541,-0.3034,-0.2047,-0.0260",\ +"-0.4158,-0.4002,-0.3875,-0.3591,-0.3084,-0.2097,-0.0310",\ +"-0.4202,-0.4046,-0.3919,-0.3636,-0.3128,-0.2142,-0.0355",\ +"-0.4301,-0.4144,-0.4017,-0.3734,-0.3226,-0.2240,-0.0453",\ +"-0.4364,-0.4208,-0.4081,-0.3798,-0.3290,-0.2303,-0.0516",\ +"-0.4729,-0.4573,-0.4446,-0.4163,-0.3655,-0.2668,-0.0881",\ +"-0.5238,-0.5081,-0.4954,-0.4671,-0.4163,-0.3177,-0.1390"); + } + } + + timing() { + timing_type : hold_rising; + related_pin : "A_BIST_CLK"; + when : "(A_BIST_WEN & A_BIST_MEN)"; + sdf_cond : "A_BIST_W_ACCESS"; + + rise_constraint("SIG2SRAM_constraint_template") { + index_1("0.0056,0.0232,0.0400,0.0728,0.1280,0.2440,0.4760"); + index_2("0.0056,0.0232,0.0400,0.0728,0.1280,0.2440,0.4760"); + values ("0.5521,0.5365,0.5238,0.4915,0.4427,0.3441,0.1478",\ +"0.5571,0.5415,0.5288,0.4966,0.4477,0.3491,0.1528",\ +"0.5615,0.5459,0.5332,0.5010,0.4522,0.3535,0.1572",\ +"0.5714,0.5558,0.5431,0.5108,0.4620,0.3634,0.1671",\ +"0.5777,0.5621,0.5494,0.5172,0.4683,0.3697,0.1734",\ +"0.6142,0.5986,0.5859,0.5537,0.5048,0.4062,0.2099",\ +"0.6651,0.6495,0.6368,0.6045,0.5557,0.4571,0.2608"); + } + + fall_constraint("SIG2SRAM_constraint_template") { + index_1("0.0056,0.0232,0.0400,0.0728,0.1280,0.2440,0.4760"); + index_2("0.0056,0.0232,0.0400,0.0728,0.1280,0.2440,0.4760"); + values ("0.5120,0.4974,0.4837,0.4554,0.4046,0.3119,0.1234",\ +"0.5171,0.5024,0.4887,0.4604,0.4096,0.3169,0.1284",\ +"0.5215,0.5069,0.4932,0.4648,0.4141,0.3213,0.1328",\ +"0.5313,0.5167,0.5030,0.4747,0.4239,0.3311,0.1427",\ +"0.5377,0.5230,0.5094,0.4810,0.4303,0.3375,0.1490",\ +"0.5742,0.5595,0.5459,0.5175,0.4667,0.3740,0.1855",\ +"0.6250,0.6104,0.5967,0.5684,0.5176,0.4249,0.2364"); + } + } + } + +bus(A_DOUT) { + + bus_type : D_31_0; + direction : output ; + capacitance : 0 ; + max_capacitance : 0.064 ; + memory_read() { + address : A_ADDR ; + } + pin(A_DOUT[31:0]) { + related_power_pin : VDD; + related_ground_pin : VSS; + internal_power() { + rise_power("scalar") { + values (0); + } + fall_power("scalar") { + values (0); + } + } + } + timing() { + related_pin : "A_CLK"; + timing_type : rising_edge ; + timing_sense : non_unate ; + + cell_rise(SIG2SRAM_delay_template) { + index_1("0.0056,0.0232,0.0400,0.0728,0.1280,0.2440,0.4760"); + index_2("0.0008,0.0014,0.0051,0.0100,0.0339,0.0640"); + values ("4.3286,4.3302,4.3379,4.3466,4.3790,4.4149",\ +"4.3387,4.3403,4.3480,4.3567,4.3891,4.4250",\ +"4.3433,4.3449,4.3526,4.3613,4.3937,4.4296",\ +"4.3511,4.3527,4.3604,4.3691,4.4015,4.4374",\ +"4.3587,4.3603,4.3680,4.3767,4.4091,4.4450",\ +"4.3938,4.3954,4.4030,4.4117,4.4442,4.4800",\ +"4.4471,4.4487,4.4564,4.4651,4.4975,4.5334"); + } + cell_fall(SIG2SRAM_delay_template) { + index_1("0.0056,0.0232,0.0400,0.0728,0.1280,0.2440,0.4760"); + index_2("0.0008,0.0014,0.0051,0.0100,0.0339,0.0640"); + values ("4.2675,4.2689,4.2749,4.2820,4.3085,4.3351",\ +"4.2776,4.2790,4.2850,4.2921,4.3186,4.3453",\ +"4.2823,4.2836,4.2896,4.2967,4.3232,4.3499",\ +"4.2901,4.2914,4.2974,4.3045,4.3310,4.3577",\ +"4.2976,4.2989,4.3049,4.3121,4.3386,4.3652",\ +"4.3327,4.3340,4.3400,4.3472,4.3737,4.4003",\ +"4.3860,4.3874,4.3934,4.4005,4.4270,4.4536"); + } + + rise_transition(SRAM_load_template) { + index_1("0.0008,0.0014,0.0051,0.0100,0.0339,0.0640"); + values ("0.0326,0.0341,0.0428,0.0518,0.0923,0.1492"); + } + fall_transition(SRAM_load_template) { + index_1("0.0008,0.0014,0.0051,0.0100,0.0339,0.0640"); + values ("0.0254,0.0265,0.0335,0.0402,0.0707,0.1039"); + } + } +} +cell_leakage_power : 396.0310; +} +} diff --git a/flow/platforms/ihp-sg13g2/lib/RM_IHPSG13_1P_1024x64_c2_bm_bist_fast_1p32V_m55C.lib b/flow/platforms/ihp-sg13g2/lib/RM_IHPSG13_1P_1024x64_c2_bm_bist_fast_1p32V_m55C.lib index 4db1b3ed6e..c97438fca3 100644 --- a/flow/platforms/ihp-sg13g2/lib/RM_IHPSG13_1P_1024x64_c2_bm_bist_fast_1p32V_m55C.lib +++ b/flow/platforms/ihp-sg13g2/lib/RM_IHPSG13_1P_1024x64_c2_bm_bist_fast_1p32V_m55C.lib @@ -1465,7 +1465,7 @@ bus(A_DOUT) { bus_type : D_63_0; direction : output ; capacitance : 0 ; - max_capacitance : "6.4e-14" ; + max_capacitance : 0.064 ; memory_read() { address : A_ADDR ; } diff --git a/flow/platforms/ihp-sg13g2/lib/RM_IHPSG13_1P_1024x64_c2_bm_bist_slow_1p08V_125C.lib b/flow/platforms/ihp-sg13g2/lib/RM_IHPSG13_1P_1024x64_c2_bm_bist_slow_1p08V_125C.lib index e1476bf229..39bd644ba7 100644 --- a/flow/platforms/ihp-sg13g2/lib/RM_IHPSG13_1P_1024x64_c2_bm_bist_slow_1p08V_125C.lib +++ b/flow/platforms/ihp-sg13g2/lib/RM_IHPSG13_1P_1024x64_c2_bm_bist_slow_1p08V_125C.lib @@ -1465,7 +1465,7 @@ bus(A_DOUT) { bus_type : D_63_0; direction : output ; capacitance : 0 ; - max_capacitance : "6.4e-14" ; + max_capacitance : 0.064 ; memory_read() { address : A_ADDR ; } diff --git a/flow/platforms/ihp-sg13g2/lib/RM_IHPSG13_1P_1024x64_c2_bm_bist_typ_1p20V_25C.lib b/flow/platforms/ihp-sg13g2/lib/RM_IHPSG13_1P_1024x64_c2_bm_bist_typ_1p20V_25C.lib index 008b510e6c..d61fa07f87 100644 --- a/flow/platforms/ihp-sg13g2/lib/RM_IHPSG13_1P_1024x64_c2_bm_bist_typ_1p20V_25C.lib +++ b/flow/platforms/ihp-sg13g2/lib/RM_IHPSG13_1P_1024x64_c2_bm_bist_typ_1p20V_25C.lib @@ -1465,7 +1465,7 @@ bus(A_DOUT) { bus_type : D_63_0; direction : output ; capacitance : 0 ; - max_capacitance : "6.4e-14" ; + max_capacitance : 0.064 ; memory_read() { address : A_ADDR ; } diff --git a/flow/platforms/ihp-sg13g2/lib/RM_IHPSG13_1P_1024x8_c2_bm_bist_fast_1p32V_m55C.lib b/flow/platforms/ihp-sg13g2/lib/RM_IHPSG13_1P_1024x8_c2_bm_bist_fast_1p32V_m55C.lib index 1010183c63..c7718f0095 100644 --- a/flow/platforms/ihp-sg13g2/lib/RM_IHPSG13_1P_1024x8_c2_bm_bist_fast_1p32V_m55C.lib +++ b/flow/platforms/ihp-sg13g2/lib/RM_IHPSG13_1P_1024x8_c2_bm_bist_fast_1p32V_m55C.lib @@ -1466,7 +1466,7 @@ bus(A_DOUT) { bus_type : D_7_0; direction : output ; capacitance : 0 ; - max_capacitance : "6.4e-14" ; + max_capacitance : 0.064 ; memory_read() { address : A_ADDR ; } diff --git a/flow/platforms/ihp-sg13g2/lib/RM_IHPSG13_1P_1024x8_c2_bm_bist_slow_1p08V_125C.lib b/flow/platforms/ihp-sg13g2/lib/RM_IHPSG13_1P_1024x8_c2_bm_bist_slow_1p08V_125C.lib index 66a85022b1..99ec3ac0a9 100644 --- a/flow/platforms/ihp-sg13g2/lib/RM_IHPSG13_1P_1024x8_c2_bm_bist_slow_1p08V_125C.lib +++ b/flow/platforms/ihp-sg13g2/lib/RM_IHPSG13_1P_1024x8_c2_bm_bist_slow_1p08V_125C.lib @@ -1466,7 +1466,7 @@ bus(A_DOUT) { bus_type : D_7_0; direction : output ; capacitance : 0 ; - max_capacitance : "6.4e-14" ; + max_capacitance : 0.064 ; memory_read() { address : A_ADDR ; } diff --git a/flow/platforms/ihp-sg13g2/lib/RM_IHPSG13_1P_1024x8_c2_bm_bist_typ_1p20V_25C.lib b/flow/platforms/ihp-sg13g2/lib/RM_IHPSG13_1P_1024x8_c2_bm_bist_typ_1p20V_25C.lib index 2f551b9b5e..a8bc9411b3 100644 --- a/flow/platforms/ihp-sg13g2/lib/RM_IHPSG13_1P_1024x8_c2_bm_bist_typ_1p20V_25C.lib +++ b/flow/platforms/ihp-sg13g2/lib/RM_IHPSG13_1P_1024x8_c2_bm_bist_typ_1p20V_25C.lib @@ -1466,7 +1466,7 @@ bus(A_DOUT) { bus_type : D_7_0; direction : output ; capacitance : 0 ; - max_capacitance : "6.4e-14" ; + max_capacitance : 0.064 ; memory_read() { address : A_ADDR ; } diff --git a/flow/platforms/ihp-sg13g2/lib/RM_IHPSG13_1P_2048x64_c2_bm_bist_fast_1p32V_m55C.lib b/flow/platforms/ihp-sg13g2/lib/RM_IHPSG13_1P_2048x64_c2_bm_bist_fast_1p32V_m55C.lib index 5024686ad0..112d3b4346 100644 --- a/flow/platforms/ihp-sg13g2/lib/RM_IHPSG13_1P_2048x64_c2_bm_bist_fast_1p32V_m55C.lib +++ b/flow/platforms/ihp-sg13g2/lib/RM_IHPSG13_1P_2048x64_c2_bm_bist_fast_1p32V_m55C.lib @@ -1471,7 +1471,7 @@ bus(A_DOUT) { bus_type : D_63_0; direction : output ; capacitance : 0 ; - max_capacitance : "6.4e-14" ; + max_capacitance : 0.064 ; memory_read() { address : A_ADDR ; } diff --git a/flow/platforms/ihp-sg13g2/lib/RM_IHPSG13_1P_2048x64_c2_bm_bist_slow_1p08V_125C.lib b/flow/platforms/ihp-sg13g2/lib/RM_IHPSG13_1P_2048x64_c2_bm_bist_slow_1p08V_125C.lib index e103d31041..d90cb793fe 100644 --- a/flow/platforms/ihp-sg13g2/lib/RM_IHPSG13_1P_2048x64_c2_bm_bist_slow_1p08V_125C.lib +++ b/flow/platforms/ihp-sg13g2/lib/RM_IHPSG13_1P_2048x64_c2_bm_bist_slow_1p08V_125C.lib @@ -1471,7 +1471,7 @@ bus(A_DOUT) { bus_type : D_63_0; direction : output ; capacitance : 0 ; - max_capacitance : "6.4e-14" ; + max_capacitance : 0.064 ; memory_read() { address : A_ADDR ; } diff --git a/flow/platforms/ihp-sg13g2/lib/RM_IHPSG13_1P_2048x64_c2_bm_bist_typ_1p20V_25C.lib b/flow/platforms/ihp-sg13g2/lib/RM_IHPSG13_1P_2048x64_c2_bm_bist_typ_1p20V_25C.lib index 58681e95cd..356aeced2e 100644 --- a/flow/platforms/ihp-sg13g2/lib/RM_IHPSG13_1P_2048x64_c2_bm_bist_typ_1p20V_25C.lib +++ b/flow/platforms/ihp-sg13g2/lib/RM_IHPSG13_1P_2048x64_c2_bm_bist_typ_1p20V_25C.lib @@ -1471,7 +1471,7 @@ bus(A_DOUT) { bus_type : D_63_0; direction : output ; capacitance : 0 ; - max_capacitance : "6.4e-14" ; + max_capacitance : 0.064 ; memory_read() { address : A_ADDR ; } diff --git a/flow/platforms/ihp-sg13g2/lib/RM_IHPSG13_1P_256x16_c2_bm_bist_fast_1p32V_m55C.lib b/flow/platforms/ihp-sg13g2/lib/RM_IHPSG13_1P_256x16_c2_bm_bist_fast_1p32V_m55C.lib new file mode 100644 index 0000000000..2deda34fe3 --- /dev/null +++ b/flow/platforms/ihp-sg13g2/lib/RM_IHPSG13_1P_256x16_c2_bm_bist_fast_1p32V_m55C.lib @@ -0,0 +1,1513 @@ +/* ------------------------------------------------------*/ +/**/ +/* Copyright 2025 IHP PDK Authors*/ +/**/ +/* Licensed under the Apache License, Version 2.0 (the "License");*/ +/* you may not use this file except in compliance with the License.*/ +/* You may obtain a copy of the License at*/ +/* */ +/* https://www.apache.org/licenses/LICENSE-2.0*/ +/* */ +/* Unless required by applicable law or agreed to in writing, software*/ +/* distributed under the License is distributed on an "AS IS" BASIS,*/ +/* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.*/ +/* See the License for the specific language governing permissions and*/ +/* limitations under the License.*/ +/* */ +/* Generated on Wed Aug 27 12:14:47 2025 */ +/* */ +/* ------------------------------------------------------ */ +library(RM_IHPSG13_1P_256x16_c2_bm_bist_fast_1p32V_m55C) { + technology (cmos) ; + delay_model : table_lookup ; + define ("add_pg_pin_to_lib", "library", "boolean"); + add_pg_pin_to_lib : true; + voltage_map ( VDD, 1.32); + voltage_map ( VDDARRAY, 1.32); + voltage_map ( VSS, 0.000000 ); + + date : "Wed Aug 27 12:14:46 2025" ; + comment : "IHP Microelectronics GmbH, 2023" ; + revision : 1.0.0 ; + simulation : true ; + nom_process : 1 ; + nom_temperature : -55 ; + nom_voltage : 1.32 ; + + operating_conditions("fast_1p32V_m55C"){ + process : 1 ; + temperature : -55 ; + voltage : 1.32 ; + tree_type : "balanced_tree" ; + } + + default_operating_conditions : fast_1p32V_m55C ; + default_max_transition : 1.0 ; + default_fanout_load : 1.0 ; + default_inout_pin_cap : 0.0 ; + default_input_pin_cap : 0.0 ; + default_output_pin_cap : 0.0 ; + default_cell_leakage_power : 0.0 ; + default_leakage_power_density : 0.0 ; + + slew_lower_threshold_pct_rise : 30 ; + slew_upper_threshold_pct_rise : 70 ; + input_threshold_pct_fall : 50 ; + output_threshold_pct_fall : 50 ; + input_threshold_pct_rise : 50 ; + output_threshold_pct_rise : 50 ; + slew_lower_threshold_pct_fall : 30 ; + slew_upper_threshold_pct_fall : 70 ; + slew_derate_from_library : 0.5; + k_volt_cell_leakage_power : 0.0 ; + k_temp_cell_leakage_power : 0.0 ; + k_process_cell_leakage_power : 0.0 ; + k_volt_internal_power : 0.0 ; + k_temp_internal_power : 0.0 ; + k_process_internal_power : 0.0 ; + + capacitive_load_unit (1,pf) ; + voltage_unit : "1V" ; + current_unit : "1uA" ; + time_unit : "1ns" ; + leakage_power_unit : "1nW" ; + pulling_resistance_unit : "1kohm"; + /* + ------------------------------------------------------------------------------------------ + implicit units overview: + cell_area unit : "um" + internal_power unit : "1e-12 * J/toggle = 1 * uW/MHz" + (capacitive_load_unit * voltage_unit^2) per toggle event + ------------------------------------------------------------------------------------------ + */ + library_features(report_delay_calculation); + define_cell_area (pad_drivers,pad_driver_sites) ; + + lu_table_template(CLKTRAN_constraint_template) { + variable_1 : constrained_pin_transition; + index_1 ( "0.010, 0.050, 0.200, 0.400, 1.000" ); + } + lu_table_template(SRAM_load_template) { + variable_1 : total_output_net_capacitance; + index_1 ( "0.0008,0.0014,0.0051,0.0100,0.0339,0.0640" ); + } + lu_table_template(SIG2SRAM_constraint_template) { + variable_1 : related_pin_transition; + variable_2 : constrained_pin_transition; + index_1 ( "0.0040,0.0176,0.0344,0.0656,0.1120,0.2016,0.3800" ); + index_2 ( "0.0040,0.0176,0.0344,0.0656,0.1120,0.2016,0.3800" ); + } + + lu_table_template(SIG2SRAM_delay_template) { + variable_1 : input_net_transition; + variable_2 : total_output_net_capacitance; + index_1 ( "0.0040,0.0176,0.0344,0.0656,0.1120,0.2016,0.3800" ); + index_2 ( "0.0008,0.0014,0.0051,0.0100,0.0339,0.0640" ); + } + + type (D_15_0) { + base_type : array; + data_type : bit; + bit_width : 16; + bit_from : 15; + bit_to : 0; + downto : true; + } + + type (A_7_0) { + base_type : array; + data_type : bit; + bit_width : 8; + bit_from : 7; + bit_to : 0; + downto : true; + } + +cell(RM_IHPSG13_1P_256x16_c2_bm_bist) { +pg_pin (VDD) { + pg_type : primary_power; + voltage_name : VDD; +} +pg_pin (VDDARRAY) { + pg_type : primary_power; + voltage_name : VDDARRAY; +} +pg_pin (VSS) { + pg_type : primary_ground; + voltage_name : VSS; +} + +memory() { + type : ram; + address_width : 8; + word_width : 16; +} + +interface_timing : false; +bus_naming_style : "%s[%d]" ; +area : 28127.104 ; + + pin(A_DLY) { + direction : input ; + capacitance : 0.00421562 ; + max_transition : "1" ; + related_power_pin : VDD; + related_ground_pin : VSS; + internal_power() { + rise_power("scalar") { + values (0); + } + fall_power("scalar") { + values (0); + } + } + } + +bus(A_ADDR) { + bus_type : A_7_0; + direction : input ; + capacitance : 0.00691085 ; + pin(A_ADDR[0]) { + capacitance : 0.00562034 ; + } + pin(A_ADDR[1]) { + capacitance : 0.00462655 ; + } + pin(A_ADDR[2]) { + capacitance : 0.00594295 ; + } + pin(A_ADDR[3]) { + capacitance : 0.00723434 ; + } + pin(A_ADDR[4]) { + capacitance : 0.00481603 ; + } + pin(A_ADDR[5]) { + capacitance : 0.00868123 ; + } + pin(A_ADDR[6]) { + capacitance : 0.010187 ; + } + max_transition : "0.38" ; + pin(A_ADDR[7:0]) { + related_power_pin : VDD; + related_ground_pin : VSS; + internal_power() { + when : "A_MEN"; + rise_power("scalar"){ + values (0.0119); + } + fall_power("scalar"){ + values (0.0026); + } + } + internal_power() { + when : "!A_MEN"; + rise_power("scalar"){ + values (0.0264); + } + fall_power("scalar"){ + values (0.0021); + } + } + } + timing() { + timing_type : setup_rising; + related_pin : "A_CLK"; + when : "((A_WEN | A_REN)& A_MEN)" + sdf_cond : "A_RW_ACCESS" + + rise_constraint("SIG2SRAM_constraint_template") { + index_1("0.0040,0.0176,0.0344,0.0656,0.1120,0.2016,0.3800"); + index_2("0.0040,0.0176,0.0344,0.0656,0.1120,0.2016,0.3800"); + values ("-0.2371,-0.2215,-0.2098,-0.1824,-0.1434,-0.0691,0.0676",\ +"-0.2449,-0.2332,-0.2176,-0.1902,-0.1551,-0.0770,0.0559",\ +"-0.2605,-0.2488,-0.2332,-0.2059,-0.1707,-0.0965,0.0441",\ +"-0.2879,-0.2723,-0.2605,-0.2332,-0.1941,-0.1199,0.0168",\ +"-0.3230,-0.3113,-0.2996,-0.2723,-0.2332,-0.1590,-0.0184",\ +"-0.4012,-0.3895,-0.3738,-0.3465,-0.3074,-0.2332,-0.0965",\ +"-0.5379,-0.5262,-0.5105,-0.4832,-0.4480,-0.3699,-0.2332"); + } + + fall_constraint("SIG2SRAM_constraint_template") { + index_1("0.0040,0.0176,0.0344,0.0656,0.1120,0.2016,0.3800"); + index_2("0.0040,0.0176,0.0344,0.0656,0.1120,0.2016,0.3800"); + values ("-0.1785,-0.1707,-0.1551,-0.1277,-0.0887,-0.0184,0.1145",\ +"-0.1902,-0.1785,-0.1629,-0.1355,-0.1004,-0.0262,0.1027",\ +"-0.2059,-0.1941,-0.1785,-0.1512,-0.1160,-0.0418,0.0871",\ +"-0.2293,-0.2176,-0.2059,-0.1785,-0.1434,-0.0691,0.0598",\ +"-0.2684,-0.2566,-0.2449,-0.2176,-0.1824,-0.1082,0.0207",\ +"-0.3465,-0.3348,-0.3191,-0.2918,-0.2566,-0.1824,-0.0535",\ +"-0.4832,-0.4715,-0.4559,-0.4324,-0.3934,-0.3191,-0.1902"); + } + } + + + timing() { + timing_type : hold_rising; + related_pin : "A_CLK"; + when : "((A_WEN | A_REN)& A_MEN)" + sdf_cond : "A_RW_ACCESS" + + rise_constraint("SIG2SRAM_constraint_template") { + index_1("0.0040,0.0176,0.0344,0.0656,0.1120,0.2016,0.3800"); + index_2("0.0040,0.0176,0.0344,0.0656,0.1120,0.2016,0.3800"); + values ("0.3410,0.3293,0.3137,0.2863,0.2473,0.1730,0.0324",\ +"0.3488,0.3371,0.3215,0.2941,0.2590,0.1809,0.0480",\ +"0.3684,0.3527,0.3371,0.3098,0.2746,0.1965,0.0598",\ +"0.3918,0.3762,0.3645,0.3371,0.2980,0.2238,0.0871",\ +"0.4309,0.4152,0.4035,0.3762,0.3371,0.2629,0.1223",\ +"0.5051,0.4934,0.4777,0.4504,0.4113,0.3371,0.1965",\ +"0.6418,0.6262,0.6145,0.5871,0.5520,0.4738,0.3332"); + } + + fall_constraint("SIG2SRAM_constraint_template") { + index_1("0.0040,0.0176,0.0344,0.0656,0.1120,0.2016,0.3800"); + index_2("0.0040,0.0176,0.0344,0.0656,0.1120,0.2016,0.3800"); + values ("0.2824,0.2707,0.2551,0.2277,0.1926,0.1184,-0.0105",\ +"0.2902,0.2785,0.2668,0.2395,0.2043,0.1301,0.0012",\ +"0.3059,0.2941,0.2824,0.2551,0.2199,0.1457,0.0168",\ +"0.3332,0.3215,0.3059,0.2785,0.2434,0.1691,0.0402",\ +"0.3723,0.3605,0.3449,0.3176,0.2824,0.2121,0.0793",\ +"0.4465,0.4348,0.4230,0.3918,0.3566,0.2824,0.1535",\ +"0.5832,0.5715,0.5598,0.5324,0.4934,0.4191,0.2902"); + } + } +} +pin(A_WEN) { + direction : input ; + capacitance : 0.00341384 ; + max_transition : "0.38" ; + related_power_pin : VDD; + related_ground_pin : VSS; + internal_power() { + when : "A_MEN"; + rise_power("scalar"){ + values (0.0061); + } + fall_power("scalar"){ + values (0.0158); + } + } + internal_power() { + when : "!A_MEN"; + rise_power("scalar"){ + values (0.0054); + } + fall_power("scalar"){ + values (0.0210); + } + } + timing() { + timing_type : setup_rising; + related_pin : "A_CLK"; + when : "A_MEN" + sdf_cond : "A_MEN" + + rise_constraint("SIG2SRAM_constraint_template") { + index_1("0.0040,0.0176,0.0344,0.0656,0.1120,0.2016,0.3800"); + index_2("0.0040,0.0176,0.0344,0.0656,0.1120,0.2016,0.3800"); + values ("0.1418,0.1496,0.1652,0.1887,0.2316,0.3059,0.4465",\ +"0.1301,0.1379,0.1535,0.1809,0.2199,0.2941,0.4348",\ +"0.1145,0.1262,0.1379,0.1652,0.2043,0.2785,0.4191",\ +"0.0871,0.0949,0.1105,0.1379,0.1770,0.2512,0.3879",\ +"0.0480,0.0598,0.0754,0.0988,0.1379,0.2082,0.3527",\ +"-0.0262,-0.0145,0.0012,0.0246,0.0676,0.1379,0.2785",\ +"-0.1668,-0.1551,-0.1395,-0.1121,-0.0730,0.0012,0.1418"); + } + + fall_constraint("SIG2SRAM_constraint_template") { + index_1("0.0040,0.0176,0.0344,0.0656,0.1120,0.2016,0.3800"); + index_2("0.0040,0.0176,0.0344,0.0656,0.1120,0.2016,0.3800"); + values ("0.2082,0.2160,0.2316,0.2590,0.2941,0.3684,0.5012",\ +"0.1926,0.2043,0.2199,0.2473,0.2824,0.3566,0.4895",\ +"0.1770,0.1887,0.2043,0.2316,0.2668,0.3410,0.4777",\ +"0.1535,0.1652,0.1770,0.2043,0.2395,0.3137,0.4504",\ +"0.1145,0.1262,0.1379,0.1652,0.2043,0.2746,0.4113",\ +"0.0402,0.0520,0.0676,0.0910,0.1262,0.2004,0.3332",\ +"-0.0965,-0.0848,-0.0730,-0.0457,-0.0066,0.0637,0.2004"); + } + } + + + timing() { + timing_type : hold_rising; + related_pin : "A_CLK"; + when : "A_MEN" + sdf_cond : "A_MEN" + + rise_constraint("SIG2SRAM_constraint_template") { + index_1("0.0040,0.0176,0.0344,0.0656,0.1120,0.2016,0.3800"); + index_2("0.0040,0.0176,0.0344,0.0656,0.1120,0.2016,0.3800"); + values ("0.1770,0.1652,0.1496,0.1223,0.0793,0.0090,-0.1316",\ +"0.1848,0.1730,0.1574,0.1301,0.0910,0.0168,-0.1199",\ +"0.2004,0.1887,0.1770,0.1496,0.1066,0.0363,-0.1043",\ +"0.2277,0.2160,0.2004,0.1730,0.1340,0.0598,-0.0809",\ +"0.2668,0.2551,0.2395,0.2121,0.1730,0.0988,-0.0418",\ +"0.3410,0.3293,0.3137,0.2863,0.2434,0.1730,0.0324",\ +"0.4816,0.4699,0.4543,0.4230,0.3801,0.3098,0.1730"); + } + + fall_constraint("SIG2SRAM_constraint_template") { + index_1("0.0040,0.0176,0.0344,0.0656,0.1120,0.2016,0.3800"); + index_2("0.0040,0.0176,0.0344,0.0656,0.1120,0.2016,0.3800"); + values ("0.1613,0.1496,0.1379,0.1066,0.0715,0.0012,-0.1355",\ +"0.1730,0.1613,0.1457,0.1184,0.0832,0.0129,-0.1238",\ +"0.1887,0.1770,0.1613,0.1340,0.0988,0.0246,-0.1121",\ +"0.2121,0.2043,0.1887,0.1613,0.1223,0.0520,-0.0848",\ +"0.2512,0.2434,0.2277,0.2004,0.1613,0.0910,-0.0457",\ +"0.3254,0.3176,0.3020,0.2746,0.2355,0.1652,0.0324",\ +"0.4660,0.4543,0.4387,0.4113,0.3723,0.3020,0.1691"); + } + } + } +pin(A_REN) { + direction : input ; + capacitance : 0.00390661 ; + max_transition : "0.38" ; + related_power_pin : VDD; + related_ground_pin : VSS; + internal_power() { + when : "A_MEN"; + rise_power("scalar"){ + values (0.0108); + } + fall_power("scalar"){ + values (0.0104); + } + } + internal_power() { + when : "!A_MEN"; + rise_power("scalar"){ + values (0.0222); + } + fall_power("scalar"){ + values (0.0197); + } + } + timing() { + timing_type : setup_rising; + related_pin : "A_CLK"; + when : "A_MEN" + sdf_cond : "A_MEN" + + rise_constraint("SIG2SRAM_constraint_template") { + index_1("0.0040,0.0176,0.0344,0.0656,0.1120,0.2016,0.3800"); + index_2("0.0040,0.0176,0.0344,0.0656,0.1120,0.2016,0.3800"); + values ("-0.0027,0.0090,0.0246,0.0520,0.0910,0.1613,0.3020",\ +"-0.0105,0.0012,0.0129,0.0363,0.0793,0.1535,0.2902",\ +"-0.0262,-0.0145,-0.0027,0.0246,0.0637,0.1379,0.2785",\ +"-0.0535,-0.0418,-0.0262,0.0012,0.0363,0.1105,0.2512",\ +"-0.0926,-0.0809,-0.0652,-0.0418,-0.0027,0.0715,0.2121",\ +"-0.1668,-0.1551,-0.1395,-0.1082,-0.0770,-0.0027,0.1379",\ +"-0.3035,-0.2918,-0.2762,-0.2488,-0.2137,-0.1434,-0.0027"); + } + + fall_constraint("SIG2SRAM_constraint_template") { + index_1("0.0040,0.0176,0.0344,0.0656,0.1120,0.2016,0.3800"); + index_2("0.0040,0.0176,0.0344,0.0656,0.1120,0.2016,0.3800"); + values ("0.0832,0.0949,0.1105,0.1379,0.1730,0.2473,0.3801",\ +"0.0754,0.0832,0.0988,0.1223,0.1613,0.2355,0.3684",\ +"0.0598,0.0676,0.0832,0.1066,0.1457,0.2121,0.3527",\ +"0.0324,0.0441,0.0598,0.0871,0.1223,0.1926,0.3293",\ +"-0.0066,0.0051,0.0168,0.0480,0.0832,0.1535,0.2902",\ +"-0.0809,-0.0691,-0.0574,-0.0301,0.0090,0.0832,0.2121",\ +"-0.2176,-0.2059,-0.1941,-0.1668,-0.1277,-0.0574,0.0793"); + } + } + + + timing() { + timing_type : hold_rising; + related_pin : "A_CLK"; + when : "A_MEN" + sdf_cond : "A_MEN" + + rise_constraint("SIG2SRAM_constraint_template") { + index_1("0.0040,0.0176,0.0344,0.0656,0.1120,0.2016,0.3800"); + index_2("0.0040,0.0176,0.0344,0.0656,0.1120,0.2016,0.3800"); + values ("0.1887,0.1770,0.1613,0.1340,0.0949,0.0207,-0.1160",\ +"0.1965,0.1848,0.1730,0.1457,0.1027,0.0324,-0.1082",\ +"0.2160,0.2004,0.1887,0.1613,0.1184,0.0480,-0.0926",\ +"0.2395,0.2277,0.2121,0.1848,0.1457,0.0715,-0.0652",\ +"0.2785,0.2668,0.2512,0.2238,0.1848,0.1105,-0.0262",\ +"0.3527,0.3410,0.3254,0.2980,0.2551,0.1848,0.0480",\ +"0.4934,0.4816,0.4660,0.4387,0.3957,0.3254,0.1887"); + } + + fall_constraint("SIG2SRAM_constraint_template") { + index_1("0.0040,0.0176,0.0344,0.0656,0.1120,0.2016,0.3800"); + index_2("0.0040,0.0176,0.0344,0.0656,0.1120,0.2016,0.3800"); + values ("0.1730,0.1613,0.1496,0.1184,0.0793,0.0129,-0.1238",\ +"0.1848,0.1730,0.1574,0.1301,0.0910,0.0207,-0.1121",\ +"0.2004,0.1887,0.1730,0.1457,0.1066,0.0363,-0.1004",\ +"0.2238,0.2121,0.2004,0.1691,0.1340,0.0598,-0.0730",\ +"0.2629,0.2512,0.2395,0.2121,0.1691,0.0988,-0.0340",\ +"0.3371,0.3254,0.3137,0.2863,0.2434,0.1730,0.0402",\ +"0.4777,0.4660,0.4504,0.4230,0.3840,0.3137,0.1809"); + } + } + } +pin(A_MEN) { + direction : input ; + capacitance : 0.00326046 ; + max_transition : "0.38" ; + related_power_pin : VDD; + related_ground_pin : VSS; + internal_power() { + rise_power("scalar"){ + values (0.1424); + } + fall_power("scalar"){ + values (0.0108); + } + } + timing() { + timing_type : setup_rising; + related_pin : "A_CLK"; + + rise_constraint("SIG2SRAM_constraint_template") { + index_1("0.0040,0.0176,0.0344,0.0656,0.1120,0.2016,0.3800"); + index_2("0.0040,0.0176,0.0344,0.0656,0.1120,0.2016,0.3800"); + values ("0.1418,0.1496,0.1652,0.1926,0.2316,0.3059,0.4465",\ +"0.1301,0.1379,0.1535,0.1809,0.2199,0.2941,0.4348",\ +"0.1145,0.1262,0.1418,0.1652,0.2043,0.2785,0.4191",\ +"0.0871,0.0949,0.1105,0.1379,0.1770,0.2512,0.3879",\ +"0.0480,0.0598,0.0754,0.0988,0.1379,0.2082,0.3488",\ +"-0.0262,-0.0145,0.0012,0.0285,0.0676,0.1379,0.2785",\ +"-0.1668,-0.1551,-0.1395,-0.1121,-0.0730,0.0012,0.1379"); + } + + fall_constraint("SIG2SRAM_constraint_template") { + index_1("0.0040,0.0176,0.0344,0.0656,0.1120,0.2016,0.3800"); + index_2("0.0040,0.0176,0.0344,0.0656,0.1120,0.2016,0.3800"); + values ("0.2082,0.2199,0.2316,0.2590,0.2980,0.3723,0.5051",\ +"0.1965,0.2082,0.2199,0.2473,0.2863,0.3605,0.4934",\ +"0.1809,0.1926,0.2043,0.2316,0.2707,0.3449,0.4777",\ +"0.1574,0.1691,0.1809,0.2082,0.2434,0.3176,0.4543",\ +"0.1145,0.1262,0.1418,0.1691,0.2043,0.2785,0.4113",\ +"0.0441,0.0559,0.0676,0.0949,0.1301,0.2004,0.3332",\ +"-0.0965,-0.0848,-0.0691,-0.0418,-0.0066,0.0676,0.2004"); + } + } + + + timing() { + timing_type : hold_rising; + related_pin : "A_CLK"; + + rise_constraint("SIG2SRAM_constraint_template") { + index_1("0.0040,0.0176,0.0344,0.0656,0.1120,0.2016,0.3800"); + index_2("0.0040,0.0176,0.0344,0.0656,0.1120,0.2016,0.3800"); + values ("0.1770,0.1652,0.1535,0.1262,0.0832,0.0129,-0.1277",\ +"0.1887,0.1770,0.1613,0.1340,0.0949,0.0207,-0.1199",\ +"0.2043,0.1926,0.1770,0.1496,0.1105,0.0363,-0.1043",\ +"0.2277,0.2160,0.2043,0.1770,0.1379,0.0598,-0.0770",\ +"0.2668,0.2551,0.2434,0.2160,0.1730,0.0988,-0.0379",\ +"0.3449,0.3332,0.3176,0.2902,0.2473,0.1730,0.0363",\ +"0.4816,0.4699,0.4543,0.4270,0.3840,0.3098,0.1770"); + } + + fall_constraint("SIG2SRAM_constraint_template") { + index_1("0.0040,0.0176,0.0344,0.0656,0.1120,0.2016,0.3800"); + index_2("0.0040,0.0176,0.0344,0.0656,0.1120,0.2016,0.3800"); + values ("0.1613,0.1496,0.1379,0.1105,0.0715,0.0012,-0.1355",\ +"0.1730,0.1613,0.1496,0.1184,0.0832,0.0129,-0.1238",\ +"0.1887,0.1770,0.1652,0.1340,0.0988,0.0285,-0.1121",\ +"0.2121,0.2043,0.1887,0.1613,0.1223,0.0520,-0.0848",\ +"0.2551,0.2434,0.2277,0.2004,0.1613,0.0910,-0.0418",\ +"0.3293,0.3176,0.3020,0.2746,0.2395,0.1652,0.0324",\ +"0.4660,0.4543,0.4426,0.4113,0.3762,0.3020,0.1691"); + } + } + } +bus(A_BM) { + bus_type : D_15_0; + direction : input ; + capacitance : 0.00310985 ; + max_transition : "0.38" ; + pin(A_BM[15:0]) { + related_power_pin : VDD; + related_ground_pin : VSS; + internal_power() { + when : "A_MEN"; + rise_power("scalar"){ + values (0.0914); + } + fall_power("scalar"){ + values (0.0775); + } + } + internal_power() { + when : "!A_MEN"; + rise_power("scalar"){ + values (0.0871); + } + fall_power("scalar"){ + values (0.0796); + } + } + } + timing() { + timing_type : setup_rising; + related_pin : "A_CLK"; + when : "(A_WEN & A_MEN)" + sdf_cond : "A_RW_ACCESS" + + rise_constraint("SIG2SRAM_constraint_template") { + index_1("0.0040,0.0176,0.0344,0.0656,0.1120,0.2016,0.3800"); + index_2("0.0040,0.0176,0.0344,0.0656,0.1120,0.2016,0.3800"); + values ("-0.1890,-0.1783,-0.1627,-0.1363,-0.0963,-0.0260,0.1088",\ +"-0.1929,-0.1822,-0.1666,-0.1402,-0.1002,-0.0299,0.1049",\ +"-0.1966,-0.1859,-0.1702,-0.1439,-0.1038,-0.0335,0.1012",\ +"-0.1998,-0.1891,-0.1734,-0.1471,-0.1070,-0.0367,0.0980",\ +"-0.2124,-0.2017,-0.1861,-0.1597,-0.1197,-0.0493,0.0854",\ +"-0.2300,-0.2193,-0.2037,-0.1773,-0.1373,-0.0670,0.0678",\ +"-0.2576,-0.2468,-0.2312,-0.2048,-0.1648,-0.0945,0.0403"); + } + + fall_constraint("SIG2SRAM_constraint_template") { + index_1("0.0040,0.0176,0.0344,0.0656,0.1120,0.2016,0.3800"); + index_2("0.0040,0.0176,0.0344,0.0656,0.1120,0.2016,0.3800"); + values ("-0.1666,-0.1558,-0.1422,-0.1148,-0.0777,-0.0055,0.1244",\ +"-0.1705,-0.1597,-0.1461,-0.1187,-0.0816,-0.0093,0.1205",\ +"-0.1742,-0.1634,-0.1497,-0.1224,-0.0853,-0.0130,0.1169",\ +"-0.1774,-0.1666,-0.1529,-0.1256,-0.0885,-0.0162,0.1137",\ +"-0.1900,-0.1792,-0.1656,-0.1382,-0.1011,-0.0288,0.1010",\ +"-0.2076,-0.1968,-0.1832,-0.1558,-0.1187,-0.0464,0.0834",\ +"-0.2351,-0.2243,-0.2107,-0.1833,-0.1462,-0.0740,0.0559"); + } + } + + + timing() { + timing_type : hold_rising; + related_pin : "A_CLK"; + when : "(A_WEN & A_MEN)" + sdf_cond : "A_RW_ACCESS" + + rise_constraint("SIG2SRAM_constraint_template") { + index_1("0.0040,0.0176,0.0344,0.0656,0.1120,0.2016,0.3800"); + index_2("0.0040,0.0176,0.0344,0.0656,0.1120,0.2016,0.3800"); + values ("0.2950,0.2833,0.2686,0.2423,0.2022,0.1309,-0.0058",\ +"0.2989,0.2872,0.2725,0.2462,0.2061,0.1348,-0.0019",\ +"0.3026,0.2908,0.2762,0.2498,0.2098,0.1385,0.0018",\ +"0.3058,0.2940,0.2794,0.2530,0.2130,0.1417,0.0050",\ +"0.3184,0.3067,0.2920,0.2656,0.2256,0.1543,0.0176",\ +"0.3360,0.3243,0.3096,0.2833,0.2432,0.1719,0.0352",\ +"0.3635,0.3518,0.3371,0.3108,0.2707,0.1994,0.0627"); + } + + fall_constraint("SIG2SRAM_constraint_template") { + index_1("0.0040,0.0176,0.0344,0.0656,0.1120,0.2016,0.3800"); + index_2("0.0040,0.0176,0.0344,0.0656,0.1120,0.2016,0.3800"); + values ("0.2667,0.2569,0.2423,0.2159,0.1788,0.1056,-0.0224",\ +"0.2706,0.2608,0.2462,0.2198,0.1827,0.1094,-0.0185",\ +"0.2742,0.2645,0.2498,0.2235,0.1864,0.1131,-0.0148",\ +"0.2774,0.2677,0.2530,0.2267,0.1895,0.1163,-0.0116",\ +"0.2901,0.2803,0.2656,0.2393,0.2022,0.1289,0.0010",\ +"0.3077,0.2979,0.2833,0.2569,0.2198,0.1465,0.0186",\ +"0.3352,0.3254,0.3108,0.2844,0.2473,0.1740,0.0461"); + } + } +} + pin(A_CLK) { + direction : input; + capacitance : 0.00389386; + max_transition : "0.38"; + clock : "true" ; + pin_func_type : active_rising ; + + timing () { + timing_type : "min_pulse_width"; + related_pin : "A_CLK"; + rise_constraint("CLKTRAN_constraint_template") { + index_1("0.004,0.38"); + values("0.12,0.12"); + } + } + + related_power_pin : VDD; + related_ground_pin : VSS; + + internal_power() { + when : "!A_MEN & !A_WEN & !A_REN"; + rise_power("scalar"){ + values (0); + } + fall_power("scalar"){ + values (0); + } + } + internal_power() { + when : "!A_MEN & A_WEN & !A_REN"; + rise_power("scalar"){ + values (0.6406); + } + fall_power("scalar"){ + values (0); + } + } + internal_power() { + when : "A_MEN & A_WEN & !A_REN"; + rise_power("scalar"){ + values (22.6954); + } + fall_power("scalar"){ + values (0); + } + } + internal_power() { + when : "A_MEN & A_WEN & A_REN"; + rise_power("scalar"){ + values (24.9897); + } + fall_power("scalar"){ + values (0); + } + } + internal_power() { + when : "A_MEN & !A_WEN & A_REN"; + rise_power("scalar"){ + values (18.3238); + } + fall_power("scalar"){ + values (0); + } + } + internal_power() { + when : "!A_MEN & !A_WEN & A_REN"; + rise_power("scalar"){ + values (0.3904); + } + fall_power("scalar"){ + values (0); + } + } + internal_power() { + when : "!A_MEN & A_WEN & A_REN"; + rise_power("scalar"){ + values (0.8744); + } + fall_power("scalar"){ + values (0); + } + } + internal_power() { + when : "A_MEN & !A_WEN & !A_REN"; + rise_power("scalar"){ + values (0); + } + fall_power("scalar"){ + values (0); + } + } + } + bus(A_DIN) { + bus_type : D_15_0; + direction : input ; + capacitance : 0.00387207 ; + memory_write() { + address : A_ADDR ; + clocked_on : A_CLK; + } + + max_transition : "0.38" ; + pin(A_DIN[15:0]) { + related_power_pin : VDD; + related_ground_pin : VSS; + internal_power() { + when : "A_MEN"; + rise_power("scalar"){ + values (0.0914); + } + fall_power("scalar"){ + values (0.0775); + } + } + internal_power() { + when : "!A_MEN"; + rise_power("scalar"){ + values (0.0871); + } + fall_power("scalar"){ + values (0.0796); + } + } + } + timing() { + timing_type : setup_rising; + related_pin : "A_CLK"; + when : "(A_WEN & A_MEN)"; + sdf_cond : "A_W_ACCESS"; + + rise_constraint("SIG2SRAM_constraint_template") { + index_1("0.0040,0.0176,0.0344,0.0656,0.1120,0.2016,0.3800"); + index_2("0.0040,0.0176,0.0344,0.0656,0.1120,0.2016,0.3800"); + values ("-0.1890,-0.1783,-0.1627,-0.1363,-0.0963,-0.0260,0.1088",\ +"-0.1929,-0.1822,-0.1666,-0.1402,-0.1002,-0.0299,0.1049",\ +"-0.1966,-0.1859,-0.1702,-0.1439,-0.1038,-0.0335,0.1012",\ +"-0.1998,-0.1891,-0.1734,-0.1471,-0.1070,-0.0367,0.0980",\ +"-0.2124,-0.2017,-0.1861,-0.1597,-0.1197,-0.0493,0.0854",\ +"-0.2300,-0.2193,-0.2037,-0.1773,-0.1373,-0.0670,0.0678",\ +"-0.2576,-0.2468,-0.2312,-0.2048,-0.1648,-0.0945,0.0403"); + } + + fall_constraint("SIG2SRAM_constraint_template") { + index_1("0.0040,0.0176,0.0344,0.0656,0.1120,0.2016,0.3800"); + index_2("0.0040,0.0176,0.0344,0.0656,0.1120,0.2016,0.3800"); + values ("-0.1666,-0.1558,-0.1422,-0.1148,-0.0777,-0.0055,0.1244",\ +"-0.1705,-0.1597,-0.1461,-0.1187,-0.0816,-0.0093,0.1205",\ +"-0.1742,-0.1634,-0.1497,-0.1224,-0.0853,-0.0130,0.1169",\ +"-0.1774,-0.1666,-0.1529,-0.1256,-0.0885,-0.0162,0.1137",\ +"-0.1900,-0.1792,-0.1656,-0.1382,-0.1011,-0.0288,0.1010",\ +"-0.2076,-0.1968,-0.1832,-0.1558,-0.1187,-0.0464,0.0834",\ +"-0.2351,-0.2243,-0.2107,-0.1833,-0.1462,-0.0740,0.0559"); + } + } + + timing() { + timing_type : hold_rising; + related_pin : "A_CLK"; + when : "(A_WEN & A_MEN)"; + sdf_cond : "A_W_ACCESS"; + + rise_constraint("SIG2SRAM_constraint_template") { + index_1("0.0040,0.0176,0.0344,0.0656,0.1120,0.2016,0.3800"); + index_2("0.0040,0.0176,0.0344,0.0656,0.1120,0.2016,0.3800"); + values ("0.2950,0.2833,0.2686,0.2423,0.2022,0.1309,-0.0058",\ +"0.2989,0.2872,0.2725,0.2462,0.2061,0.1348,-0.0019",\ +"0.3026,0.2908,0.2762,0.2498,0.2098,0.1385,0.0018",\ +"0.3058,0.2940,0.2794,0.2530,0.2130,0.1417,0.0050",\ +"0.3184,0.3067,0.2920,0.2656,0.2256,0.1543,0.0176",\ +"0.3360,0.3243,0.3096,0.2833,0.2432,0.1719,0.0352",\ +"0.3635,0.3518,0.3371,0.3108,0.2707,0.1994,0.0627"); + } + + fall_constraint("SIG2SRAM_constraint_template") { + index_1("0.0040,0.0176,0.0344,0.0656,0.1120,0.2016,0.3800"); + index_2("0.0040,0.0176,0.0344,0.0656,0.1120,0.2016,0.3800"); + values ("0.2667,0.2569,0.2423,0.2159,0.1788,0.1056,-0.0224",\ +"0.2706,0.2608,0.2462,0.2198,0.1827,0.1094,-0.0185",\ +"0.2742,0.2645,0.2498,0.2235,0.1864,0.1131,-0.0148",\ +"0.2774,0.2677,0.2530,0.2267,0.1895,0.1163,-0.0116",\ +"0.2901,0.2803,0.2656,0.2393,0.2022,0.1289,0.0010",\ +"0.3077,0.2979,0.2833,0.2569,0.2198,0.1465,0.0186",\ +"0.3352,0.3254,0.3108,0.2844,0.2473,0.1740,0.0461"); + } + } + } + + pin(A_BIST_EN) { + direction : input ; + capacitance : 0.00421562 ; + max_transition : "1" ; + related_power_pin : VDD; + related_ground_pin : VSS; + internal_power() { + rise_power("scalar") { + values (0); + } + fall_power("scalar") { + values (0); + } + } + } + +bus(A_BIST_ADDR) { + bus_type : A_7_0; + direction : input ; + capacitance : 0.00691085 ; + pin(A_BIST_ADDR[0]) { + capacitance : 0.00562034 ; + } + pin(A_BIST_ADDR[1]) { + capacitance : 0.00462655 ; + } + pin(A_BIST_ADDR[2]) { + capacitance : 0.00594295 ; + } + pin(A_BIST_ADDR[3]) { + capacitance : 0.00723434 ; + } + pin(A_BIST_ADDR[4]) { + capacitance : 0.00481603 ; + } + pin(A_BIST_ADDR[5]) { + capacitance : 0.00868123 ; + } + pin(A_BIST_ADDR[6]) { + capacitance : 0.010187 ; + } + max_transition : "0.38" ; + pin(A_BIST_ADDR[7:0]) { + related_power_pin : VDD; + related_ground_pin : VSS; + internal_power() { + when : "A_BIST_MEN"; + rise_power("scalar"){ + values (0.0119); + } + fall_power("scalar"){ + values (0.0026); + } + } + internal_power() { + when : "!A_BIST_MEN"; + rise_power("scalar"){ + values (0.0264); + } + fall_power("scalar"){ + values (0.0021); + } + } + } + timing() { + timing_type : setup_rising; + related_pin : "A_BIST_CLK"; + when : "((A_BIST_WEN | A_BIST_REN)& A_BIST_MEN)" + sdf_cond : "A_BIST_RW_ACCESS" + + rise_constraint("SIG2SRAM_constraint_template") { + index_1("0.0040,0.0176,0.0344,0.0656,0.1120,0.2016,0.3800"); + index_2("0.0040,0.0176,0.0344,0.0656,0.1120,0.2016,0.3800"); + values ("-0.2371,-0.2215,-0.2098,-0.1824,-0.1434,-0.0691,0.0676",\ +"-0.2449,-0.2332,-0.2176,-0.1902,-0.1551,-0.0770,0.0559",\ +"-0.2605,-0.2488,-0.2332,-0.2059,-0.1707,-0.0965,0.0441",\ +"-0.2879,-0.2723,-0.2605,-0.2332,-0.1941,-0.1199,0.0168",\ +"-0.3230,-0.3113,-0.2996,-0.2723,-0.2332,-0.1590,-0.0184",\ +"-0.4012,-0.3895,-0.3738,-0.3465,-0.3074,-0.2332,-0.0965",\ +"-0.5379,-0.5262,-0.5105,-0.4832,-0.4480,-0.3699,-0.2332"); + } + + fall_constraint("SIG2SRAM_constraint_template") { + index_1("0.0040,0.0176,0.0344,0.0656,0.1120,0.2016,0.3800"); + index_2("0.0040,0.0176,0.0344,0.0656,0.1120,0.2016,0.3800"); + values ("-0.1785,-0.1707,-0.1551,-0.1277,-0.0887,-0.0184,0.1145",\ +"-0.1902,-0.1785,-0.1629,-0.1355,-0.1004,-0.0262,0.1027",\ +"-0.2059,-0.1941,-0.1785,-0.1512,-0.1160,-0.0418,0.0871",\ +"-0.2293,-0.2176,-0.2059,-0.1785,-0.1434,-0.0691,0.0598",\ +"-0.2684,-0.2566,-0.2449,-0.2176,-0.1824,-0.1082,0.0207",\ +"-0.3465,-0.3348,-0.3191,-0.2918,-0.2566,-0.1824,-0.0535",\ +"-0.4832,-0.4715,-0.4559,-0.4324,-0.3934,-0.3191,-0.1902"); + } + } + + + timing() { + timing_type : hold_rising; + related_pin : "A_BIST_CLK"; + when : "((A_BIST_WEN | A_BIST_REN)& A_BIST_MEN)" + sdf_cond : "A_BIST_RW_ACCESS" + + rise_constraint("SIG2SRAM_constraint_template") { + index_1("0.0040,0.0176,0.0344,0.0656,0.1120,0.2016,0.3800"); + index_2("0.0040,0.0176,0.0344,0.0656,0.1120,0.2016,0.3800"); + values ("0.3410,0.3293,0.3137,0.2863,0.2473,0.1730,0.0324",\ +"0.3488,0.3371,0.3215,0.2941,0.2590,0.1809,0.0480",\ +"0.3684,0.3527,0.3371,0.3098,0.2746,0.1965,0.0598",\ +"0.3918,0.3762,0.3645,0.3371,0.2980,0.2238,0.0871",\ +"0.4309,0.4152,0.4035,0.3762,0.3371,0.2629,0.1223",\ +"0.5051,0.4934,0.4777,0.4504,0.4113,0.3371,0.1965",\ +"0.6418,0.6262,0.6145,0.5871,0.5520,0.4738,0.3332"); + } + + fall_constraint("SIG2SRAM_constraint_template") { + index_1("0.0040,0.0176,0.0344,0.0656,0.1120,0.2016,0.3800"); + index_2("0.0040,0.0176,0.0344,0.0656,0.1120,0.2016,0.3800"); + values ("0.2824,0.2707,0.2551,0.2277,0.1926,0.1184,-0.0105",\ +"0.2902,0.2785,0.2668,0.2395,0.2043,0.1301,0.0012",\ +"0.3059,0.2941,0.2824,0.2551,0.2199,0.1457,0.0168",\ +"0.3332,0.3215,0.3059,0.2785,0.2434,0.1691,0.0402",\ +"0.3723,0.3605,0.3449,0.3176,0.2824,0.2121,0.0793",\ +"0.4465,0.4348,0.4230,0.3918,0.3566,0.2824,0.1535",\ +"0.5832,0.5715,0.5598,0.5324,0.4934,0.4191,0.2902"); + } + } +} +pin(A_BIST_WEN) { + direction : input ; + capacitance : 0.00341384 ; + max_transition : "0.38" ; + related_power_pin : VDD; + related_ground_pin : VSS; + internal_power() { + when : "A_BIST_MEN"; + rise_power("scalar"){ + values (0.0061); + } + fall_power("scalar"){ + values (0.0158); + } + } + internal_power() { + when : "!A_BIST_MEN"; + rise_power("scalar"){ + values (0.0054); + } + fall_power("scalar"){ + values (0.0210); + } + } + timing() { + timing_type : setup_rising; + related_pin : "A_BIST_CLK"; + when : "A_BIST_MEN" + sdf_cond : "A_BIST_MEN" + + rise_constraint("SIG2SRAM_constraint_template") { + index_1("0.0040,0.0176,0.0344,0.0656,0.1120,0.2016,0.3800"); + index_2("0.0040,0.0176,0.0344,0.0656,0.1120,0.2016,0.3800"); + values ("0.1418,0.1496,0.1652,0.1887,0.2316,0.3059,0.4465",\ +"0.1301,0.1379,0.1535,0.1809,0.2199,0.2941,0.4348",\ +"0.1145,0.1262,0.1379,0.1652,0.2043,0.2785,0.4191",\ +"0.0871,0.0949,0.1105,0.1379,0.1770,0.2512,0.3879",\ +"0.0480,0.0598,0.0754,0.0988,0.1379,0.2082,0.3527",\ +"-0.0262,-0.0145,0.0012,0.0246,0.0676,0.1379,0.2785",\ +"-0.1668,-0.1551,-0.1395,-0.1121,-0.0730,0.0012,0.1418"); + } + + fall_constraint("SIG2SRAM_constraint_template") { + index_1("0.0040,0.0176,0.0344,0.0656,0.1120,0.2016,0.3800"); + index_2("0.0040,0.0176,0.0344,0.0656,0.1120,0.2016,0.3800"); + values ("0.2082,0.2160,0.2316,0.2590,0.2941,0.3684,0.5012",\ +"0.1926,0.2043,0.2199,0.2473,0.2824,0.3566,0.4895",\ +"0.1770,0.1887,0.2043,0.2316,0.2668,0.3410,0.4777",\ +"0.1535,0.1652,0.1770,0.2043,0.2395,0.3137,0.4504",\ +"0.1145,0.1262,0.1379,0.1652,0.2043,0.2746,0.4113",\ +"0.0402,0.0520,0.0676,0.0910,0.1262,0.2004,0.3332",\ +"-0.0965,-0.0848,-0.0730,-0.0457,-0.0066,0.0637,0.2004"); + } + } + + + timing() { + timing_type : hold_rising; + related_pin : "A_BIST_CLK"; + when : "A_BIST_MEN" + sdf_cond : "A_BIST_MEN" + + rise_constraint("SIG2SRAM_constraint_template") { + index_1("0.0040,0.0176,0.0344,0.0656,0.1120,0.2016,0.3800"); + index_2("0.0040,0.0176,0.0344,0.0656,0.1120,0.2016,0.3800"); + values ("0.1770,0.1652,0.1496,0.1223,0.0793,0.0090,-0.1316",\ +"0.1848,0.1730,0.1574,0.1301,0.0910,0.0168,-0.1199",\ +"0.2004,0.1887,0.1770,0.1496,0.1066,0.0363,-0.1043",\ +"0.2277,0.2160,0.2004,0.1730,0.1340,0.0598,-0.0809",\ +"0.2668,0.2551,0.2395,0.2121,0.1730,0.0988,-0.0418",\ +"0.3410,0.3293,0.3137,0.2863,0.2434,0.1730,0.0324",\ +"0.4816,0.4699,0.4543,0.4230,0.3801,0.3098,0.1730"); + } + + fall_constraint("SIG2SRAM_constraint_template") { + index_1("0.0040,0.0176,0.0344,0.0656,0.1120,0.2016,0.3800"); + index_2("0.0040,0.0176,0.0344,0.0656,0.1120,0.2016,0.3800"); + values ("0.1613,0.1496,0.1379,0.1066,0.0715,0.0012,-0.1355",\ +"0.1730,0.1613,0.1457,0.1184,0.0832,0.0129,-0.1238",\ +"0.1887,0.1770,0.1613,0.1340,0.0988,0.0246,-0.1121",\ +"0.2121,0.2043,0.1887,0.1613,0.1223,0.0520,-0.0848",\ +"0.2512,0.2434,0.2277,0.2004,0.1613,0.0910,-0.0457",\ +"0.3254,0.3176,0.3020,0.2746,0.2355,0.1652,0.0324",\ +"0.4660,0.4543,0.4387,0.4113,0.3723,0.3020,0.1691"); + } + } + } +pin(A_BIST_REN) { + direction : input ; + capacitance : 0.00390661 ; + max_transition : "0.38" ; + related_power_pin : VDD; + related_ground_pin : VSS; + internal_power() { + when : "A_BIST_MEN"; + rise_power("scalar"){ + values (0.0108); + } + fall_power("scalar"){ + values (0.0104); + } + } + internal_power() { + when : "!A_BIST_MEN"; + rise_power("scalar"){ + values (0.0222); + } + fall_power("scalar"){ + values (0.0197); + } + } + timing() { + timing_type : setup_rising; + related_pin : "A_BIST_CLK"; + when : "A_BIST_MEN" + sdf_cond : "A_BIST_MEN" + + rise_constraint("SIG2SRAM_constraint_template") { + index_1("0.0040,0.0176,0.0344,0.0656,0.1120,0.2016,0.3800"); + index_2("0.0040,0.0176,0.0344,0.0656,0.1120,0.2016,0.3800"); + values ("-0.0027,0.0090,0.0246,0.0520,0.0910,0.1613,0.3020",\ +"-0.0105,0.0012,0.0129,0.0363,0.0793,0.1535,0.2902",\ +"-0.0262,-0.0145,-0.0027,0.0246,0.0637,0.1379,0.2785",\ +"-0.0535,-0.0418,-0.0262,0.0012,0.0363,0.1105,0.2512",\ +"-0.0926,-0.0809,-0.0652,-0.0418,-0.0027,0.0715,0.2121",\ +"-0.1668,-0.1551,-0.1395,-0.1082,-0.0770,-0.0027,0.1379",\ +"-0.3035,-0.2918,-0.2762,-0.2488,-0.2137,-0.1434,-0.0027"); + } + + fall_constraint("SIG2SRAM_constraint_template") { + index_1("0.0040,0.0176,0.0344,0.0656,0.1120,0.2016,0.3800"); + index_2("0.0040,0.0176,0.0344,0.0656,0.1120,0.2016,0.3800"); + values ("0.0832,0.0949,0.1105,0.1379,0.1730,0.2473,0.3801",\ +"0.0754,0.0832,0.0988,0.1223,0.1613,0.2355,0.3684",\ +"0.0598,0.0676,0.0832,0.1066,0.1457,0.2121,0.3527",\ +"0.0324,0.0441,0.0598,0.0871,0.1223,0.1926,0.3293",\ +"-0.0066,0.0051,0.0168,0.0480,0.0832,0.1535,0.2902",\ +"-0.0809,-0.0691,-0.0574,-0.0301,0.0090,0.0832,0.2121",\ +"-0.2176,-0.2059,-0.1941,-0.1668,-0.1277,-0.0574,0.0793"); + } + } + + + timing() { + timing_type : hold_rising; + related_pin : "A_BIST_CLK"; + when : "A_BIST_MEN" + sdf_cond : "A_BIST_MEN" + + rise_constraint("SIG2SRAM_constraint_template") { + index_1("0.0040,0.0176,0.0344,0.0656,0.1120,0.2016,0.3800"); + index_2("0.0040,0.0176,0.0344,0.0656,0.1120,0.2016,0.3800"); + values ("0.1887,0.1770,0.1613,0.1340,0.0949,0.0207,-0.1160",\ +"0.1965,0.1848,0.1730,0.1457,0.1027,0.0324,-0.1082",\ +"0.2160,0.2004,0.1887,0.1613,0.1184,0.0480,-0.0926",\ +"0.2395,0.2277,0.2121,0.1848,0.1457,0.0715,-0.0652",\ +"0.2785,0.2668,0.2512,0.2238,0.1848,0.1105,-0.0262",\ +"0.3527,0.3410,0.3254,0.2980,0.2551,0.1848,0.0480",\ +"0.4934,0.4816,0.4660,0.4387,0.3957,0.3254,0.1887"); + } + + fall_constraint("SIG2SRAM_constraint_template") { + index_1("0.0040,0.0176,0.0344,0.0656,0.1120,0.2016,0.3800"); + index_2("0.0040,0.0176,0.0344,0.0656,0.1120,0.2016,0.3800"); + values ("0.1730,0.1613,0.1496,0.1184,0.0793,0.0129,-0.1238",\ +"0.1848,0.1730,0.1574,0.1301,0.0910,0.0207,-0.1121",\ +"0.2004,0.1887,0.1730,0.1457,0.1066,0.0363,-0.1004",\ +"0.2238,0.2121,0.2004,0.1691,0.1340,0.0598,-0.0730",\ +"0.2629,0.2512,0.2395,0.2121,0.1691,0.0988,-0.0340",\ +"0.3371,0.3254,0.3137,0.2863,0.2434,0.1730,0.0402",\ +"0.4777,0.4660,0.4504,0.4230,0.3840,0.3137,0.1809"); + } + } + } +pin(A_BIST_MEN) { + direction : input ; + capacitance : 0.00326046 ; + max_transition : "0.38" ; + related_power_pin : VDD; + related_ground_pin : VSS; + internal_power() { + rise_power("scalar"){ + values (0.1424); + } + fall_power("scalar"){ + values (0.0108); + } + } + timing() { + timing_type : setup_rising; + related_pin : "A_BIST_CLK"; + + rise_constraint("SIG2SRAM_constraint_template") { + index_1("0.0040,0.0176,0.0344,0.0656,0.1120,0.2016,0.3800"); + index_2("0.0040,0.0176,0.0344,0.0656,0.1120,0.2016,0.3800"); + values ("0.1418,0.1496,0.1652,0.1926,0.2316,0.3059,0.4465",\ +"0.1301,0.1379,0.1535,0.1809,0.2199,0.2941,0.4348",\ +"0.1145,0.1262,0.1418,0.1652,0.2043,0.2785,0.4191",\ +"0.0871,0.0949,0.1105,0.1379,0.1770,0.2512,0.3879",\ +"0.0480,0.0598,0.0754,0.0988,0.1379,0.2082,0.3488",\ +"-0.0262,-0.0145,0.0012,0.0285,0.0676,0.1379,0.2785",\ +"-0.1668,-0.1551,-0.1395,-0.1121,-0.0730,0.0012,0.1379"); + } + + fall_constraint("SIG2SRAM_constraint_template") { + index_1("0.0040,0.0176,0.0344,0.0656,0.1120,0.2016,0.3800"); + index_2("0.0040,0.0176,0.0344,0.0656,0.1120,0.2016,0.3800"); + values ("0.2082,0.2199,0.2316,0.2590,0.2980,0.3723,0.5051",\ +"0.1965,0.2082,0.2199,0.2473,0.2863,0.3605,0.4934",\ +"0.1809,0.1926,0.2043,0.2316,0.2707,0.3449,0.4777",\ +"0.1574,0.1691,0.1809,0.2082,0.2434,0.3176,0.4543",\ +"0.1145,0.1262,0.1418,0.1691,0.2043,0.2785,0.4113",\ +"0.0441,0.0559,0.0676,0.0949,0.1301,0.2004,0.3332",\ +"-0.0965,-0.0848,-0.0691,-0.0418,-0.0066,0.0676,0.2004"); + } + } + + + timing() { + timing_type : hold_rising; + related_pin : "A_BIST_CLK"; + + rise_constraint("SIG2SRAM_constraint_template") { + index_1("0.0040,0.0176,0.0344,0.0656,0.1120,0.2016,0.3800"); + index_2("0.0040,0.0176,0.0344,0.0656,0.1120,0.2016,0.3800"); + values ("0.1770,0.1652,0.1535,0.1262,0.0832,0.0129,-0.1277",\ +"0.1887,0.1770,0.1613,0.1340,0.0949,0.0207,-0.1199",\ +"0.2043,0.1926,0.1770,0.1496,0.1105,0.0363,-0.1043",\ +"0.2277,0.2160,0.2043,0.1770,0.1379,0.0598,-0.0770",\ +"0.2668,0.2551,0.2434,0.2160,0.1730,0.0988,-0.0379",\ +"0.3449,0.3332,0.3176,0.2902,0.2473,0.1730,0.0363",\ +"0.4816,0.4699,0.4543,0.4270,0.3840,0.3098,0.1770"); + } + + fall_constraint("SIG2SRAM_constraint_template") { + index_1("0.0040,0.0176,0.0344,0.0656,0.1120,0.2016,0.3800"); + index_2("0.0040,0.0176,0.0344,0.0656,0.1120,0.2016,0.3800"); + values ("0.1613,0.1496,0.1379,0.1105,0.0715,0.0012,-0.1355",\ +"0.1730,0.1613,0.1496,0.1184,0.0832,0.0129,-0.1238",\ +"0.1887,0.1770,0.1652,0.1340,0.0988,0.0285,-0.1121",\ +"0.2121,0.2043,0.1887,0.1613,0.1223,0.0520,-0.0848",\ +"0.2551,0.2434,0.2277,0.2004,0.1613,0.0910,-0.0418",\ +"0.3293,0.3176,0.3020,0.2746,0.2395,0.1652,0.0324",\ +"0.4660,0.4543,0.4426,0.4113,0.3762,0.3020,0.1691"); + } + } + } +bus(A_BIST_BM) { + bus_type : D_15_0; + direction : input ; + capacitance : 0.00253457 ; + max_transition : "0.38" ; + pin(A_BIST_BM[15:0]) { + related_power_pin : VDD; + related_ground_pin : VSS; + internal_power() { + when : "A_BIST_MEN"; + rise_power("scalar"){ + values (0.0914); + } + fall_power("scalar"){ + values (0.0775); + } + } + internal_power() { + when : "!A_BIST_MEN"; + rise_power("scalar"){ + values (0.0871); + } + fall_power("scalar"){ + values (0.0796); + } + } + } + timing() { + timing_type : setup_rising; + related_pin : "A_BIST_CLK"; + when : "(A_BIST_WEN & A_BIST_MEN)" + sdf_cond : "A_BIST_RW_ACCESS" + + rise_constraint("SIG2SRAM_constraint_template") { + index_1("0.0040,0.0176,0.0344,0.0656,0.1120,0.2016,0.3800"); + index_2("0.0040,0.0176,0.0344,0.0656,0.1120,0.2016,0.3800"); + values ("-0.1890,-0.1783,-0.1627,-0.1363,-0.0963,-0.0260,0.1088",\ +"-0.1929,-0.1822,-0.1666,-0.1402,-0.1002,-0.0299,0.1049",\ +"-0.1966,-0.1859,-0.1702,-0.1439,-0.1038,-0.0335,0.1012",\ +"-0.1998,-0.1891,-0.1734,-0.1471,-0.1070,-0.0367,0.0980",\ +"-0.2124,-0.2017,-0.1861,-0.1597,-0.1197,-0.0493,0.0854",\ +"-0.2300,-0.2193,-0.2037,-0.1773,-0.1373,-0.0670,0.0678",\ +"-0.2576,-0.2468,-0.2312,-0.2048,-0.1648,-0.0945,0.0403"); + } + + fall_constraint("SIG2SRAM_constraint_template") { + index_1("0.0040,0.0176,0.0344,0.0656,0.1120,0.2016,0.3800"); + index_2("0.0040,0.0176,0.0344,0.0656,0.1120,0.2016,0.3800"); + values ("-0.1666,-0.1558,-0.1422,-0.1148,-0.0777,-0.0055,0.1244",\ +"-0.1705,-0.1597,-0.1461,-0.1187,-0.0816,-0.0093,0.1205",\ +"-0.1742,-0.1634,-0.1497,-0.1224,-0.0853,-0.0130,0.1169",\ +"-0.1774,-0.1666,-0.1529,-0.1256,-0.0885,-0.0162,0.1137",\ +"-0.1900,-0.1792,-0.1656,-0.1382,-0.1011,-0.0288,0.1010",\ +"-0.2076,-0.1968,-0.1832,-0.1558,-0.1187,-0.0464,0.0834",\ +"-0.2351,-0.2243,-0.2107,-0.1833,-0.1462,-0.0740,0.0559"); + } + } + + + timing() { + timing_type : hold_rising; + related_pin : "A_BIST_CLK"; + when : "(A_BIST_WEN & A_BIST_MEN)" + sdf_cond : "A_BIST_RW_ACCESS" + + rise_constraint("SIG2SRAM_constraint_template") { + index_1("0.0040,0.0176,0.0344,0.0656,0.1120,0.2016,0.3800"); + index_2("0.0040,0.0176,0.0344,0.0656,0.1120,0.2016,0.3800"); + values ("0.2950,0.2833,0.2686,0.2423,0.2022,0.1309,-0.0058",\ +"0.2989,0.2872,0.2725,0.2462,0.2061,0.1348,-0.0019",\ +"0.3026,0.2908,0.2762,0.2498,0.2098,0.1385,0.0018",\ +"0.3058,0.2940,0.2794,0.2530,0.2130,0.1417,0.0050",\ +"0.3184,0.3067,0.2920,0.2656,0.2256,0.1543,0.0176",\ +"0.3360,0.3243,0.3096,0.2833,0.2432,0.1719,0.0352",\ +"0.3635,0.3518,0.3371,0.3108,0.2707,0.1994,0.0627"); + } + + fall_constraint("SIG2SRAM_constraint_template") { + index_1("0.0040,0.0176,0.0344,0.0656,0.1120,0.2016,0.3800"); + index_2("0.0040,0.0176,0.0344,0.0656,0.1120,0.2016,0.3800"); + values ("0.2667,0.2569,0.2423,0.2159,0.1788,0.1056,-0.0224",\ +"0.2706,0.2608,0.2462,0.2198,0.1827,0.1094,-0.0185",\ +"0.2742,0.2645,0.2498,0.2235,0.1864,0.1131,-0.0148",\ +"0.2774,0.2677,0.2530,0.2267,0.1895,0.1163,-0.0116",\ +"0.2901,0.2803,0.2656,0.2393,0.2022,0.1289,0.0010",\ +"0.3077,0.2979,0.2833,0.2569,0.2198,0.1465,0.0186",\ +"0.3352,0.3254,0.3108,0.2844,0.2473,0.1740,0.0461"); + } + } +} + pin(A_BIST_CLK) { + direction : input; + capacitance : 0.00389386; + max_transition : "0.38"; + clock : "true" ; + pin_func_type : active_rising ; + + timing () { + timing_type : "min_pulse_width"; + related_pin : "A_BIST_CLK"; + rise_constraint("CLKTRAN_constraint_template") { + index_1("0.004,0.38"); + values("0.12,0.12"); + } + } + + related_power_pin : VDD; + related_ground_pin : VSS; + + internal_power() { + when : "!A_BIST_MEN & !A_BIST_WEN & !A_BIST_REN"; + rise_power("scalar"){ + values (0); + } + fall_power("scalar"){ + values (0); + } + } + internal_power() { + when : "!A_BIST_MEN & A_BIST_WEN & !A_BIST_REN"; + rise_power("scalar"){ + values (0.6406); + } + fall_power("scalar"){ + values (0); + } + } + internal_power() { + when : "A_BIST_MEN & A_BIST_WEN & !A_BIST_REN"; + rise_power("scalar"){ + values (22.6954); + } + fall_power("scalar"){ + values (0); + } + } + internal_power() { + when : "A_BIST_MEN & A_BIST_WEN & A_BIST_REN"; + rise_power("scalar"){ + values (24.9897); + } + fall_power("scalar"){ + values (0); + } + } + internal_power() { + when : "A_BIST_MEN & !A_BIST_WEN & A_BIST_REN"; + rise_power("scalar"){ + values (18.3238); + } + fall_power("scalar"){ + values (0); + } + } + internal_power() { + when : "!A_BIST_MEN & !A_BIST_WEN & A_BIST_REN"; + rise_power("scalar"){ + values (0.3904); + } + fall_power("scalar"){ + values (0); + } + } + internal_power() { + when : "!A_BIST_MEN & A_BIST_WEN & A_BIST_REN"; + rise_power("scalar"){ + values (0.8744); + } + fall_power("scalar"){ + values (0); + } + } + internal_power() { + when : "A_BIST_MEN & !A_BIST_WEN & !A_BIST_REN"; + rise_power("scalar"){ + values (0); + } + fall_power("scalar"){ + values (0); + } + } + } + bus(A_BIST_DIN) { + bus_type : D_15_0; + direction : input ; + capacitance : 0.00252927 ; + memory_write() { + address : A_BIST_ADDR ; + clocked_on : A_BIST_CLK; + } + + max_transition : "0.38" ; + pin(A_BIST_DIN[15:0]) { + related_power_pin : VDD; + related_ground_pin : VSS; + internal_power() { + when : "A_BIST_MEN"; + rise_power("scalar"){ + values (0.0914); + } + fall_power("scalar"){ + values (0.0775); + } + } + internal_power() { + when : "!A_BIST_MEN"; + rise_power("scalar"){ + values (0.0871); + } + fall_power("scalar"){ + values (0.0796); + } + } + } + timing() { + timing_type : setup_rising; + related_pin : "A_BIST_CLK"; + when : "(A_BIST_WEN & A_BIST_MEN)"; + sdf_cond : "A_BIST_W_ACCESS"; + + rise_constraint("SIG2SRAM_constraint_template") { + index_1("0.0040,0.0176,0.0344,0.0656,0.1120,0.2016,0.3800"); + index_2("0.0040,0.0176,0.0344,0.0656,0.1120,0.2016,0.3800"); + values ("-0.1890,-0.1783,-0.1627,-0.1363,-0.0963,-0.0260,0.1088",\ +"-0.1929,-0.1822,-0.1666,-0.1402,-0.1002,-0.0299,0.1049",\ +"-0.1966,-0.1859,-0.1702,-0.1439,-0.1038,-0.0335,0.1012",\ +"-0.1998,-0.1891,-0.1734,-0.1471,-0.1070,-0.0367,0.0980",\ +"-0.2124,-0.2017,-0.1861,-0.1597,-0.1197,-0.0493,0.0854",\ +"-0.2300,-0.2193,-0.2037,-0.1773,-0.1373,-0.0670,0.0678",\ +"-0.2576,-0.2468,-0.2312,-0.2048,-0.1648,-0.0945,0.0403"); + } + + fall_constraint("SIG2SRAM_constraint_template") { + index_1("0.0040,0.0176,0.0344,0.0656,0.1120,0.2016,0.3800"); + index_2("0.0040,0.0176,0.0344,0.0656,0.1120,0.2016,0.3800"); + values ("-0.1666,-0.1558,-0.1422,-0.1148,-0.0777,-0.0055,0.1244",\ +"-0.1705,-0.1597,-0.1461,-0.1187,-0.0816,-0.0093,0.1205",\ +"-0.1742,-0.1634,-0.1497,-0.1224,-0.0853,-0.0130,0.1169",\ +"-0.1774,-0.1666,-0.1529,-0.1256,-0.0885,-0.0162,0.1137",\ +"-0.1900,-0.1792,-0.1656,-0.1382,-0.1011,-0.0288,0.1010",\ +"-0.2076,-0.1968,-0.1832,-0.1558,-0.1187,-0.0464,0.0834",\ +"-0.2351,-0.2243,-0.2107,-0.1833,-0.1462,-0.0740,0.0559"); + } + } + + timing() { + timing_type : hold_rising; + related_pin : "A_BIST_CLK"; + when : "(A_BIST_WEN & A_BIST_MEN)"; + sdf_cond : "A_BIST_W_ACCESS"; + + rise_constraint("SIG2SRAM_constraint_template") { + index_1("0.0040,0.0176,0.0344,0.0656,0.1120,0.2016,0.3800"); + index_2("0.0040,0.0176,0.0344,0.0656,0.1120,0.2016,0.3800"); + values ("0.2950,0.2833,0.2686,0.2423,0.2022,0.1309,-0.0058",\ +"0.2989,0.2872,0.2725,0.2462,0.2061,0.1348,-0.0019",\ +"0.3026,0.2908,0.2762,0.2498,0.2098,0.1385,0.0018",\ +"0.3058,0.2940,0.2794,0.2530,0.2130,0.1417,0.0050",\ +"0.3184,0.3067,0.2920,0.2656,0.2256,0.1543,0.0176",\ +"0.3360,0.3243,0.3096,0.2833,0.2432,0.1719,0.0352",\ +"0.3635,0.3518,0.3371,0.3108,0.2707,0.1994,0.0627"); + } + + fall_constraint("SIG2SRAM_constraint_template") { + index_1("0.0040,0.0176,0.0344,0.0656,0.1120,0.2016,0.3800"); + index_2("0.0040,0.0176,0.0344,0.0656,0.1120,0.2016,0.3800"); + values ("0.2667,0.2569,0.2423,0.2159,0.1788,0.1056,-0.0224",\ +"0.2706,0.2608,0.2462,0.2198,0.1827,0.1094,-0.0185",\ +"0.2742,0.2645,0.2498,0.2235,0.1864,0.1131,-0.0148",\ +"0.2774,0.2677,0.2530,0.2267,0.1895,0.1163,-0.0116",\ +"0.2901,0.2803,0.2656,0.2393,0.2022,0.1289,0.0010",\ +"0.3077,0.2979,0.2833,0.2569,0.2198,0.1465,0.0186",\ +"0.3352,0.3254,0.3108,0.2844,0.2473,0.1740,0.0461"); + } + } + } + +bus(A_DOUT) { + + bus_type : D_15_0; + direction : output ; + capacitance : 0 ; + max_capacitance : 0.064 ; + memory_read() { + address : A_ADDR ; + } + pin(A_DOUT[15:0]) { + related_power_pin : VDD; + related_ground_pin : VSS; + internal_power() { + rise_power("scalar") { + values (0); + } + fall_power("scalar") { + values (0); + } + } + } + timing() { + related_pin : "A_CLK"; + timing_type : rising_edge ; + timing_sense : non_unate ; + + cell_rise(SIG2SRAM_delay_template) { + index_1("0.0040,0.0176,0.0344,0.0656,0.1120,0.2016,0.3800"); + index_2("0.0008,0.0014,0.0051,0.0100,0.0339,0.0640"); + values ("1.8312,1.8322,1.8370,1.8425,1.8634,1.8869",\ +"1.8371,1.8381,1.8429,1.8485,1.8694,1.8929",\ +"1.8399,1.8409,1.8457,1.8512,1.8721,1.8956",\ +"1.8441,1.8451,1.8499,1.8554,1.8763,1.8998",\ +"1.8557,1.8567,1.8615,1.8670,1.8879,1.9114",\ +"1.8748,1.8758,1.8806,1.8861,1.9071,1.9306",\ +"1.9012,1.9022,1.9070,1.9125,1.9334,1.9569"); + } + cell_fall(SIG2SRAM_delay_template) { + index_1("0.0040,0.0176,0.0344,0.0656,0.1120,0.2016,0.3800"); + index_2("0.0008,0.0014,0.0051,0.0100,0.0339,0.0640"); + values ("1.7969,1.7977,1.8018,1.8063,1.8234,1.8401",\ +"1.8028,1.8037,1.8077,1.8123,1.8294,1.8461",\ +"1.8056,1.8064,1.8105,1.8150,1.8321,1.8488",\ +"1.8098,1.8106,1.8147,1.8192,1.8363,1.8530",\ +"1.8214,1.8223,1.8263,1.8308,1.8479,1.8647",\ +"1.8405,1.8414,1.8454,1.8500,1.8671,1.8838",\ +"1.8669,1.8678,1.8718,1.8763,1.8934,1.9102"); + } + + rise_transition(SRAM_load_template) { + index_1("0.0008,0.0014,0.0051,0.0100,0.0339,0.0640"); + values ("0.0206,0.0210,0.0265,0.0323,0.0606,0.0955"); + } + fall_transition(SRAM_load_template) { + index_1("0.0008,0.0014,0.0051,0.0100,0.0339,0.0640"); + values ("0.0170,0.0177,0.0222,0.0270,0.0451,0.0644"); + } + } +} +cell_leakage_power : 117.3985; +} +} diff --git a/flow/platforms/ihp-sg13g2/lib/RM_IHPSG13_1P_256x16_c2_bm_bist_slow_1p08V_125C.lib b/flow/platforms/ihp-sg13g2/lib/RM_IHPSG13_1P_256x16_c2_bm_bist_slow_1p08V_125C.lib new file mode 100644 index 0000000000..9a517d0dc7 --- /dev/null +++ b/flow/platforms/ihp-sg13g2/lib/RM_IHPSG13_1P_256x16_c2_bm_bist_slow_1p08V_125C.lib @@ -0,0 +1,1513 @@ +/* ------------------------------------------------------*/ +/**/ +/* Copyright 2025 IHP PDK Authors*/ +/**/ +/* Licensed under the Apache License, Version 2.0 (the "License");*/ +/* you may not use this file except in compliance with the License.*/ +/* You may obtain a copy of the License at*/ +/* */ +/* https://www.apache.org/licenses/LICENSE-2.0*/ +/* */ +/* Unless required by applicable law or agreed to in writing, software*/ +/* distributed under the License is distributed on an "AS IS" BASIS,*/ +/* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.*/ +/* See the License for the specific language governing permissions and*/ +/* limitations under the License.*/ +/* */ +/* Generated on Wed Aug 27 12:14:46 2025 */ +/* */ +/* ------------------------------------------------------ */ +library(RM_IHPSG13_1P_256x16_c2_bm_bist_slow_1p08V_125C) { + technology (cmos) ; + delay_model : table_lookup ; + define ("add_pg_pin_to_lib", "library", "boolean"); + add_pg_pin_to_lib : true; + voltage_map ( VDD, 1.08); + voltage_map ( VDDARRAY, 1.08); + voltage_map ( VSS, 0.000000 ); + + date : "Wed Aug 27 12:14:46 2025" ; + comment : "IHP Microelectronics GmbH, 2023" ; + revision : 1.0.0 ; + simulation : true ; + nom_process : 1 ; + nom_temperature : 125 ; + nom_voltage : 1.08 ; + + operating_conditions("slow_1p08V_125C"){ + process : 1 ; + temperature : 125 ; + voltage : 1.08 ; + tree_type : "balanced_tree" ; + } + + default_operating_conditions : slow_1p08V_125C ; + default_max_transition : 1.0 ; + default_fanout_load : 1.0 ; + default_inout_pin_cap : 0.0 ; + default_input_pin_cap : 0.0 ; + default_output_pin_cap : 0.0 ; + default_cell_leakage_power : 0.0 ; + default_leakage_power_density : 0.0 ; + + slew_lower_threshold_pct_rise : 30 ; + slew_upper_threshold_pct_rise : 70 ; + input_threshold_pct_fall : 50 ; + output_threshold_pct_fall : 50 ; + input_threshold_pct_rise : 50 ; + output_threshold_pct_rise : 50 ; + slew_lower_threshold_pct_fall : 30 ; + slew_upper_threshold_pct_fall : 70 ; + slew_derate_from_library : 0.5; + k_volt_cell_leakage_power : 0.0 ; + k_temp_cell_leakage_power : 0.0 ; + k_process_cell_leakage_power : 0.0 ; + k_volt_internal_power : 0.0 ; + k_temp_internal_power : 0.0 ; + k_process_internal_power : 0.0 ; + + capacitive_load_unit (1,pf) ; + voltage_unit : "1V" ; + current_unit : "1uA" ; + time_unit : "1ns" ; + leakage_power_unit : "1nW" ; + pulling_resistance_unit : "1kohm"; + /* + ------------------------------------------------------------------------------------------ + implicit units overview: + cell_area unit : "um" + internal_power unit : "1e-12 * J/toggle = 1 * uW/MHz" + (capacitive_load_unit * voltage_unit^2) per toggle event + ------------------------------------------------------------------------------------------ + */ + library_features(report_delay_calculation); + define_cell_area (pad_drivers,pad_driver_sites) ; + + lu_table_template(CLKTRAN_constraint_template) { + variable_1 : constrained_pin_transition; + index_1 ( "0.010, 0.050, 0.200, 0.400, 1.000" ); + } + lu_table_template(SRAM_load_template) { + variable_1 : total_output_net_capacitance; + index_1 ( "0.0008,0.0014,0.0051,0.0100,0.0339,0.0640" ); + } + lu_table_template(SIG2SRAM_constraint_template) { + variable_1 : related_pin_transition; + variable_2 : constrained_pin_transition; + index_1 ( "0.0080,0.0288,0.0616,0.1072,0.1920,0.3496,0.5952" ); + index_2 ( "0.0080,0.0288,0.0616,0.1072,0.1920,0.3496,0.5952" ); + } + + lu_table_template(SIG2SRAM_delay_template) { + variable_1 : input_net_transition; + variable_2 : total_output_net_capacitance; + index_1 ( "0.0080,0.0288,0.0616,0.1072,0.1920,0.3496,0.5952" ); + index_2 ( "0.0008,0.0014,0.0051,0.0100,0.0339,0.0640" ); + } + + type (D_15_0) { + base_type : array; + data_type : bit; + bit_width : 16; + bit_from : 15; + bit_to : 0; + downto : true; + } + + type (A_7_0) { + base_type : array; + data_type : bit; + bit_width : 8; + bit_from : 7; + bit_to : 0; + downto : true; + } + +cell(RM_IHPSG13_1P_256x16_c2_bm_bist) { +pg_pin (VDD) { + pg_type : primary_power; + voltage_name : VDD; +} +pg_pin (VDDARRAY) { + pg_type : primary_power; + voltage_name : VDDARRAY; +} +pg_pin (VSS) { + pg_type : primary_ground; + voltage_name : VSS; +} + +memory() { + type : ram; + address_width : 8; + word_width : 16; +} + +interface_timing : false; +bus_naming_style : "%s[%d]" ; +area : 28127.104 ; + + pin(A_DLY) { + direction : input ; + capacitance : 0.00387999 ; + max_transition : "1" ; + related_power_pin : VDD; + related_ground_pin : VSS; + internal_power() { + rise_power("scalar") { + values (0); + } + fall_power("scalar") { + values (0); + } + } + } + +bus(A_ADDR) { + bus_type : A_7_0; + direction : input ; + capacitance : 0.0077013 ; + pin(A_ADDR[0]) { + capacitance : 0.00625349 ; + } + pin(A_ADDR[1]) { + capacitance : 0.00507435 ; + } + pin(A_ADDR[2]) { + capacitance : 0.00656707 ; + } + pin(A_ADDR[3]) { + capacitance : 0.0083133 ; + } + pin(A_ADDR[4]) { + capacitance : 0.00507219 ; + } + pin(A_ADDR[5]) { + capacitance : 0.00964344 ; + } + pin(A_ADDR[6]) { + capacitance : 0.0119653 ; + } + max_transition : "0.5952" ; + pin(A_ADDR[7:0]) { + related_power_pin : VDD; + related_ground_pin : VSS; + internal_power() { + when : "A_MEN"; + rise_power("scalar"){ + values (0.0102); + } + fall_power("scalar"){ + values (0.0077); + } + } + internal_power() { + when : "!A_MEN"; + rise_power("scalar"){ + values (0.0150); + } + fall_power("scalar"){ + values (0.0029); + } + } + } + timing() { + timing_type : setup_rising; + related_pin : "A_CLK"; + when : "((A_WEN | A_REN)& A_MEN)" + sdf_cond : "A_RW_ACCESS" + + rise_constraint("SIG2SRAM_constraint_template") { + index_1("0.0080,0.0288,0.0616,0.1072,0.1920,0.3496,0.5952"); + index_2("0.0080,0.0288,0.0616,0.1072,0.1920,0.3496,0.5952"); + values ("-0.7371,-0.7176,-0.6863,-0.6434,-0.5652,-0.4168,-0.1980",\ +"-0.7566,-0.7371,-0.7059,-0.6629,-0.5848,-0.4363,-0.2137",\ +"-0.7879,-0.7645,-0.7332,-0.6902,-0.6121,-0.4637,-0.2449",\ +"-0.8309,-0.8074,-0.7762,-0.7332,-0.6551,-0.5066,-0.2879",\ +"-0.9051,-0.8895,-0.8543,-0.8113,-0.7332,-0.5887,-0.3660",\ +"-1.0418,-1.0262,-0.9949,-0.9480,-0.8699,-0.7293,-0.5027",\ +"-1.2684,-1.2449,-1.2176,-1.1707,-1.0965,-0.9480,-0.7293"); + } + + fall_constraint("SIG2SRAM_constraint_template") { + index_1("0.0080,0.0288,0.0616,0.1072,0.1920,0.3496,0.5952"); + index_2("0.0080,0.0288,0.0616,0.1072,0.1920,0.3496,0.5952"); + values ("-0.5926,-0.5730,-0.5418,-0.4988,-0.4246,-0.2879,-0.0730",\ +"-0.6121,-0.5926,-0.5613,-0.5223,-0.4441,-0.3074,-0.0887",\ +"-0.6395,-0.6199,-0.5926,-0.5496,-0.4715,-0.3348,-0.1160",\ +"-0.6863,-0.6668,-0.6355,-0.5965,-0.5184,-0.3777,-0.1590",\ +"-0.7605,-0.7410,-0.7137,-0.6746,-0.5926,-0.4559,-0.2410",\ +"-0.9012,-0.8816,-0.8504,-0.8113,-0.7332,-0.5926,-0.3895",\ +"-1.1238,-1.1043,-1.0769,-1.0379,-0.9559,-0.8191,-0.6004"); + } + } + + + timing() { + timing_type : hold_rising; + related_pin : "A_CLK"; + when : "((A_WEN | A_REN)& A_MEN)" + sdf_cond : "A_RW_ACCESS" + + rise_constraint("SIG2SRAM_constraint_template") { + index_1("0.0080,0.0288,0.0616,0.1072,0.1920,0.3496,0.5952"); + index_2("0.0080,0.0288,0.0616,0.1072,0.1920,0.3496,0.5952"); + values ("0.8488,0.8293,0.7980,0.7551,0.6730,0.5285,0.3059",\ +"0.8684,0.8488,0.8176,0.7746,0.6926,0.5480,0.3254",\ +"0.8996,0.8801,0.8449,0.8020,0.7238,0.5754,0.3527",\ +"0.9426,0.9191,0.8918,0.8488,0.7668,0.6223,0.3996",\ +"1.0168,1.0012,0.9699,0.9230,0.8449,0.7004,0.4777",\ +"1.1574,1.1379,1.1105,1.0598,0.9816,0.8371,0.6184",\ +"1.3801,1.3605,1.3254,1.2980,1.2043,1.0637,0.8371"); + } + + fall_constraint("SIG2SRAM_constraint_template") { + index_1("0.0080,0.0288,0.0616,0.1072,0.1920,0.3496,0.5952"); + index_2("0.0080,0.0288,0.0616,0.1072,0.1920,0.3496,0.5952"); + values ("0.6965,0.6770,0.6496,0.6066,0.5246,0.3918,0.1730",\ +"0.7160,0.6965,0.6652,0.6262,0.5441,0.4113,0.1965",\ +"0.7473,0.7277,0.6965,0.6535,0.5754,0.4426,0.2238",\ +"0.7863,0.7707,0.7395,0.7004,0.6223,0.4855,0.2629",\ +"0.8684,0.8449,0.8176,0.7785,0.7004,0.5637,0.3449",\ +"1.0051,0.9855,0.9855,0.9113,0.8332,0.7004,0.4895",\ +"1.2277,1.2082,1.1809,1.1379,1.0598,0.9230,0.7004"); + } + } +} +pin(A_WEN) { + direction : input ; + capacitance : 0.00313551 ; + max_transition : "0.5952" ; + related_power_pin : VDD; + related_ground_pin : VSS; + internal_power() { + when : "A_MEN"; + rise_power("scalar"){ + values (0.0036); + } + fall_power("scalar"){ + values (0.0007); + } + } + internal_power() { + when : "!A_MEN"; + rise_power("scalar"){ + values (0.0050); + } + fall_power("scalar"){ + values (0.0002); + } + } + timing() { + timing_type : setup_rising; + related_pin : "A_CLK"; + when : "A_MEN" + sdf_cond : "A_MEN" + + rise_constraint("SIG2SRAM_constraint_template") { + index_1("0.0080,0.0288,0.0616,0.1072,0.1920,0.3496,0.5952"); + index_2("0.0080,0.0288,0.0616,0.1072,0.1920,0.3496,0.5952"); + values ("0.3137,0.3332,0.3605,0.4035,0.4816,0.6223,0.8488",\ +"0.2980,0.3176,0.3410,0.3840,0.4660,0.6027,0.8293",\ +"0.2629,0.2824,0.3098,0.3527,0.4348,0.5754,0.7980",\ +"0.2199,0.2395,0.2668,0.3098,0.3918,0.5324,0.7590",\ +"0.1418,0.1613,0.1887,0.2316,0.3137,0.4348,0.6730",\ +"0.0012,0.0207,0.0520,0.0910,0.1730,0.3098,0.5285",\ +"-0.2215,-0.2020,-0.1746,-0.1277,-0.0496,0.0910,0.3098"); + } + + fall_constraint("SIG2SRAM_constraint_template") { + index_1("0.0080,0.0288,0.0616,0.1072,0.1920,0.3496,0.5952"); + index_2("0.0080,0.0288,0.0616,0.1072,0.1920,0.3496,0.5952"); + values ("0.4504,0.4699,0.4973,0.5324,0.6027,0.7355,0.9699",\ +"0.4309,0.4504,0.4777,0.5129,0.5910,0.7160,0.9504",\ +"0.3996,0.4191,0.4465,0.4816,0.5520,0.6848,0.9191",\ +"0.3605,0.3762,0.4035,0.4387,0.5168,0.6418,0.8723",\ +"0.2785,0.2980,0.3215,0.3605,0.4348,0.5637,0.7980",\ +"0.1379,0.1574,0.1809,0.2199,0.2980,0.4309,0.6457",\ +"-0.0809,-0.0613,-0.0340,0.0051,0.0832,0.2160,0.4191"); + } + } + + + timing() { + timing_type : hold_rising; + related_pin : "A_CLK"; + when : "A_MEN" + sdf_cond : "A_MEN" + + rise_constraint("SIG2SRAM_constraint_template") { + index_1("0.0080,0.0288,0.0616,0.1072,0.1920,0.3496,0.5952"); + index_2("0.0080,0.0288,0.0616,0.1072,0.1920,0.3496,0.5952"); + values ("0.3723,0.3527,0.3215,0.2785,0.1965,0.0559,-0.1668",\ +"0.3918,0.3723,0.3449,0.2980,0.2160,0.0754,-0.1473",\ +"0.4152,0.3996,0.3684,0.3254,0.2434,0.1066,-0.1199",\ +"0.4621,0.4465,0.4152,0.3723,0.2863,0.1496,-0.0730",\ +"0.5324,0.5207,0.4895,0.4465,0.3645,0.2199,0.0051",\ +"0.6770,0.6535,0.6301,0.5832,0.5090,0.3605,0.1418",\ +"0.9035,0.8879,0.8566,0.8137,0.7316,0.5871,0.3684"); + } + + fall_constraint("SIG2SRAM_constraint_template") { + index_1("0.0080,0.0288,0.0616,0.1072,0.1920,0.3496,0.5952"); + index_2("0.0080,0.0288,0.0616,0.1072,0.1920,0.3496,0.5952"); + values ("0.3762,0.3566,0.3293,0.2863,0.2043,0.0676,-0.1434",\ +"0.3957,0.3762,0.3488,0.3059,0.2238,0.0871,-0.1199",\ +"0.4230,0.4035,0.3723,0.3332,0.2512,0.1184,-0.0965",\ +"0.4660,0.4465,0.4191,0.3762,0.2941,0.1613,-0.0496",\ +"0.5324,0.5168,0.4973,0.4543,0.3723,0.2316,0.0285",\ +"0.6809,0.6613,0.6340,0.5910,0.5129,0.3645,0.1652",\ +"0.9113,0.8918,0.8605,0.8176,0.7395,0.5988,0.3879"); + } + } + } +pin(A_REN) { + direction : input ; + capacitance : 0.00381144 ; + max_transition : "0.5952" ; + related_power_pin : VDD; + related_ground_pin : VSS; + internal_power() { + when : "A_MEN"; + rise_power("scalar"){ + values (0.0040); + } + fall_power("scalar"){ + values (0.0015); + } + } + internal_power() { + when : "!A_MEN"; + rise_power("scalar"){ + values (0.0040); + } + fall_power("scalar"){ + values (0.0013); + } + } + timing() { + timing_type : setup_rising; + related_pin : "A_CLK"; + when : "A_MEN" + sdf_cond : "A_MEN" + + rise_constraint("SIG2SRAM_constraint_template") { + index_1("0.0080,0.0288,0.0616,0.1072,0.1920,0.3496,0.5952"); + index_2("0.0080,0.0288,0.0616,0.1072,0.1920,0.3496,0.5952"); + values ("-0.0770,-0.0574,-0.0262,0.0168,0.0949,0.2355,0.4582",\ +"-0.0965,-0.0770,-0.0457,-0.0027,0.0754,0.2160,0.4387",\ +"-0.1199,-0.1004,-0.0730,-0.0262,0.0520,0.1887,0.4113",\ +"-0.1590,-0.1434,-0.1160,-0.0730,0.0051,0.1457,0.3645",\ +"-0.2449,-0.2254,-0.1941,-0.1473,-0.0770,0.0676,0.2863",\ +"-0.3816,-0.3699,-0.3387,-0.2801,-0.2215,-0.0770,0.1457",\ +"-0.6121,-0.5926,-0.5613,-0.5145,-0.4363,-0.2996,-0.0730"); + } + + fall_constraint("SIG2SRAM_constraint_template") { + index_1("0.0080,0.0288,0.0616,0.1072,0.1920,0.3496,0.5952"); + index_2("0.0080,0.0288,0.0616,0.1072,0.1920,0.3496,0.5952"); + values ("0.1262,0.1457,0.1691,0.2121,0.2824,0.4191,0.6457",\ +"0.1105,0.1262,0.1496,0.1887,0.2629,0.3996,0.6262",\ +"0.0793,0.0949,0.1223,0.1652,0.2395,0.3684,0.5949",\ +"0.0363,0.0559,0.0793,0.1223,0.2004,0.3410,0.5520",\ +"-0.0457,-0.0262,0.0012,0.0441,0.1301,0.2629,0.4738",\ +"-0.1902,-0.1746,-0.1434,-0.1043,-0.0184,0.1223,0.3332",\ +"-0.4129,-0.3934,-0.3660,-0.3230,-0.2449,-0.1043,0.1105"); + } + } + + + timing() { + timing_type : hold_rising; + related_pin : "A_CLK"; + when : "A_MEN" + sdf_cond : "A_MEN" + + rise_constraint("SIG2SRAM_constraint_template") { + index_1("0.0080,0.0288,0.0616,0.1072,0.1920,0.3496,0.5952"); + index_2("0.0080,0.0288,0.0616,0.1072,0.1920,0.3496,0.5952"); + values ("0.4113,0.3918,0.3645,0.3176,0.2395,0.0988,-0.1238",\ +"0.4309,0.4113,0.3840,0.3371,0.2590,0.1184,-0.1043",\ +"0.4582,0.4387,0.4113,0.3645,0.2824,0.1457,-0.0770",\ +"0.5051,0.4816,0.4543,0.4074,0.3293,0.1887,-0.0340",\ +"0.5715,0.5598,0.5324,0.4895,0.4035,0.2512,0.0441",\ +"0.7043,0.7004,0.6730,0.6262,0.5402,0.3957,0.1809",\ +"0.9387,0.9270,0.8957,0.8527,0.7746,0.6262,0.4074"); + } + + fall_constraint("SIG2SRAM_constraint_template") { + index_1("0.0080,0.0288,0.0616,0.1072,0.1920,0.3496,0.5952"); + index_2("0.0080,0.0288,0.0616,0.1072,0.1920,0.3496,0.5952"); + values ("0.4152,0.3918,0.3645,0.3215,0.2395,0.1027,-0.1082",\ +"0.4309,0.4113,0.3801,0.3410,0.2590,0.1223,-0.0926",\ +"0.4582,0.4387,0.4074,0.3684,0.2863,0.1496,-0.0613",\ +"0.5012,0.4816,0.4504,0.4074,0.3293,0.1887,-0.0145",\ +"0.5715,0.5559,0.5285,0.4816,0.3996,0.2512,0.0598",\ +"0.7160,0.7004,0.6691,0.6262,0.5520,0.4035,0.2004",\ +"0.9387,0.9191,0.8957,0.8488,0.7707,0.6262,0.4113"); + } + } + } +pin(A_MEN) { + direction : input ; + capacitance : 0.00300347 ; + max_transition : "0.5952" ; + related_power_pin : VDD; + related_ground_pin : VSS; + internal_power() { + rise_power("scalar"){ + values (0.0161); + } + fall_power("scalar"){ + values (0.0002); + } + } + timing() { + timing_type : setup_rising; + related_pin : "A_CLK"; + + rise_constraint("SIG2SRAM_constraint_template") { + index_1("0.0080,0.0288,0.0616,0.1072,0.1920,0.3496,0.5952"); + index_2("0.0080,0.0288,0.0616,0.1072,0.1920,0.3496,0.5952"); + values ("0.3215,0.3449,0.3684,0.4113,0.4895,0.6301,0.8527",\ +"0.3059,0.3254,0.3527,0.3957,0.4738,0.6145,0.8371",\ +"0.2746,0.2941,0.3215,0.3645,0.4426,0.5871,0.8059",\ +"0.2316,0.2512,0.2785,0.3215,0.3996,0.5402,0.7629",\ +"0.1496,0.1730,0.1965,0.2395,0.3215,0.4660,0.6848",\ +"0.0090,0.0285,0.0598,0.1027,0.1809,0.3176,0.5402",\ +"-0.2098,-0.1902,-0.1668,-0.1199,-0.0418,0.0988,0.3137"); + } + + fall_constraint("SIG2SRAM_constraint_template") { + index_1("0.0080,0.0288,0.0616,0.1072,0.1920,0.3496,0.5952"); + index_2("0.0080,0.0288,0.0616,0.1072,0.1920,0.3496,0.5952"); + values ("0.4582,0.4738,0.5012,0.5363,0.6145,0.7395,0.9738",\ +"0.4387,0.4543,0.4816,0.5207,0.5910,0.7199,0.9582",\ +"0.4035,0.4230,0.4504,0.4855,0.5637,0.6887,0.9230",\ +"0.3645,0.3840,0.4074,0.4465,0.5285,0.6496,0.8840",\ +"0.2824,0.3020,0.3254,0.3645,0.4465,0.5715,0.7980",\ +"0.1418,0.1613,0.1887,0.2238,0.3020,0.4309,0.6496",\ +"-0.0770,-0.0574,-0.0301,0.0090,0.0910,0.2238,0.4191"); + } + } + + + timing() { + timing_type : hold_rising; + related_pin : "A_CLK"; + + rise_constraint("SIG2SRAM_constraint_template") { + index_1("0.0080,0.0288,0.0616,0.1072,0.1920,0.3496,0.5952"); + index_2("0.0080,0.0288,0.0616,0.1072,0.1920,0.3496,0.5952"); + values ("0.3762,0.3605,0.3293,0.2863,0.2043,0.0637,-0.1629",\ +"0.3996,0.3801,0.3488,0.3020,0.2238,0.0832,-0.1395",\ +"0.4230,0.4074,0.3723,0.3293,0.2473,0.1105,-0.1121",\ +"0.4621,0.4465,0.4152,0.3762,0.2941,0.1535,-0.0691",\ +"0.5441,0.5285,0.4973,0.4465,0.3684,0.2316,0.0090",\ +"0.6848,0.6652,0.6301,0.5910,0.5129,0.3605,0.1496",\ +"0.9074,0.8918,0.8566,0.8215,0.7395,0.5910,0.3723"); + } + + fall_constraint("SIG2SRAM_constraint_template") { + index_1("0.0080,0.0288,0.0616,0.1072,0.1920,0.3496,0.5952"); + index_2("0.0080,0.0288,0.0616,0.1072,0.1920,0.3496,0.5952"); + values ("0.3762,0.3605,0.3332,0.2863,0.2043,0.0715,-0.1395",\ +"0.3996,0.3762,0.3488,0.3059,0.2238,0.0910,-0.1199",\ +"0.4270,0.4035,0.3762,0.3332,0.2512,0.1184,-0.0965",\ +"0.4699,0.4504,0.4191,0.3762,0.2941,0.1613,-0.0496",\ +"0.5441,0.5285,0.4973,0.4543,0.3762,0.2355,0.0324",\ +"0.6770,0.6613,0.6340,0.5949,0.5207,0.3762,0.1652",\ +"0.9074,0.8918,0.8605,0.8176,0.7395,0.6027,0.3918"); + } + } + } +bus(A_BM) { + bus_type : D_15_0; + direction : input ; + capacitance : 0.00263802 ; + max_transition : "0.5952" ; + pin(A_BM[15:0]) { + related_power_pin : VDD; + related_ground_pin : VSS; + internal_power() { + when : "A_MEN"; + rise_power("scalar"){ + values (0.0469); + } + fall_power("scalar"){ + values (0.0152); + } + } + internal_power() { + when : "!A_MEN"; + rise_power("scalar"){ + values (0.0453); + } + fall_power("scalar"){ + values (0.0145); + } + } + } + timing() { + timing_type : setup_rising; + related_pin : "A_CLK"; + when : "(A_WEN & A_MEN)" + sdf_cond : "A_RW_ACCESS" + + rise_constraint("SIG2SRAM_constraint_template") { + index_1("0.0080,0.0288,0.0616,0.1072,0.1920,0.3496,0.5952"); + index_2("0.0080,0.0288,0.0616,0.1072,0.1920,0.3496,0.5952"); + values ("-0.6209,-0.6013,-0.5750,-0.5330,-0.4519,-0.3074,-0.0867",\ +"-0.6288,-0.6092,-0.5829,-0.5409,-0.4598,-0.3153,-0.0946",\ +"-0.6379,-0.6184,-0.5920,-0.5500,-0.4690,-0.3244,-0.1037",\ +"-0.6529,-0.6334,-0.6070,-0.5650,-0.4839,-0.3394,-0.1187",\ +"-0.6753,-0.6557,-0.6294,-0.5874,-0.5063,-0.3618,-0.1411",\ +"-0.7189,-0.6993,-0.6730,-0.6310,-0.5499,-0.4054,-0.1847",\ +"-0.7881,-0.7685,-0.7422,-0.7002,-0.6191,-0.4746,-0.2539"); + } + + fall_constraint("SIG2SRAM_constraint_template") { + index_1("0.0080,0.0288,0.0616,0.1072,0.1920,0.3496,0.5952"); + index_2("0.0080,0.0288,0.0616,0.1072,0.1920,0.3496,0.5952"); + values ("-0.5652,-0.5496,-0.5212,-0.4822,-0.4011,-0.2634,-0.0515",\ +"-0.5731,-0.5575,-0.5292,-0.4901,-0.4090,-0.2714,-0.0594",\ +"-0.5823,-0.5666,-0.5383,-0.4992,-0.4182,-0.2805,-0.0686",\ +"-0.5972,-0.5816,-0.5533,-0.5142,-0.4332,-0.2955,-0.0836",\ +"-0.6196,-0.6040,-0.5757,-0.5366,-0.4556,-0.3179,-0.1059",\ +"-0.6632,-0.6476,-0.6193,-0.5802,-0.4992,-0.3615,-0.1495",\ +"-0.7324,-0.7168,-0.6885,-0.6494,-0.5683,-0.4306,-0.2187"); + } + } + + + timing() { + timing_type : hold_rising; + related_pin : "A_CLK"; + when : "(A_WEN & A_MEN)" + sdf_cond : "A_RW_ACCESS" + + rise_constraint("SIG2SRAM_constraint_template") { + index_1("0.0080,0.0288,0.0616,0.1072,0.1920,0.3496,0.5952"); + index_2("0.0080,0.0288,0.0616,0.1072,0.1920,0.3496,0.5952"); + values ("0.7376,0.7161,0.6898,0.6468,0.5677,0.4222,0.1966",\ +"0.7455,0.7241,0.6977,0.6547,0.5756,0.4301,0.2045",\ +"0.7547,0.7332,0.7068,0.6639,0.5848,0.4393,0.2137",\ +"0.7697,0.7482,0.7218,0.6788,0.5998,0.4542,0.2287",\ +"0.7921,0.7706,0.7442,0.7012,0.6221,0.4766,0.2510",\ +"0.8357,0.8142,0.7878,0.7448,0.6657,0.5202,0.2946",\ +"0.9048,0.8833,0.8570,0.8140,0.7349,0.5894,0.3638"); + } + + fall_constraint("SIG2SRAM_constraint_template") { + index_1("0.0080,0.0288,0.0616,0.1072,0.1920,0.3496,0.5952"); + index_2("0.0080,0.0288,0.0616,0.1072,0.1920,0.3496,0.5952"); + values ("0.6693,0.6527,0.6243,0.5804,0.5033,0.3656,0.1556",\ +"0.6772,0.6606,0.6323,0.5883,0.5112,0.3735,0.1635",\ +"0.6863,0.6697,0.6414,0.5975,0.5203,0.3826,0.1727",\ +"0.7013,0.6847,0.6564,0.6124,0.5353,0.3976,0.1876",\ +"0.7237,0.7071,0.6788,0.6348,0.5577,0.4200,0.2100",\ +"0.7673,0.7507,0.7224,0.6784,0.6013,0.4636,0.2536",\ +"0.8365,0.8199,0.7916,0.7476,0.6705,0.5328,0.3228"); + } + } +} + pin(A_CLK) { + direction : input; + capacitance : 0.00378957; + max_transition : "0.5952"; + clock : "true" ; + pin_func_type : active_rising ; + + timing () { + timing_type : "min_pulse_width"; + related_pin : "A_CLK"; + rise_constraint("CLKTRAN_constraint_template") { + index_1("0.008,0.5952"); + values("0.4,0.4"); + } + } + + related_power_pin : VDD; + related_ground_pin : VSS; + + internal_power() { + when : "!A_MEN & !A_WEN & !A_REN"; + rise_power("scalar"){ + values (0); + } + fall_power("scalar"){ + values (0); + } + } + internal_power() { + when : "!A_MEN & A_WEN & !A_REN"; + rise_power("scalar"){ + values (0.4498); + } + fall_power("scalar"){ + values (0); + } + } + internal_power() { + when : "A_MEN & A_WEN & !A_REN"; + rise_power("scalar"){ + values (15.3644); + } + fall_power("scalar"){ + values (0); + } + } + internal_power() { + when : "A_MEN & A_WEN & A_REN"; + rise_power("scalar"){ + values (16.3884); + } + fall_power("scalar"){ + values (0); + } + } + internal_power() { + when : "A_MEN & !A_WEN & A_REN"; + rise_power("scalar"){ + values (11.8557); + } + fall_power("scalar"){ + values (0); + } + } + internal_power() { + when : "!A_MEN & !A_WEN & A_REN"; + rise_power("scalar"){ + values (0.2837); + } + fall_power("scalar"){ + values (0); + } + } + internal_power() { + when : "!A_MEN & A_WEN & A_REN"; + rise_power("scalar"){ + values (0.6730); + } + fall_power("scalar"){ + values (0); + } + } + internal_power() { + when : "A_MEN & !A_WEN & !A_REN"; + rise_power("scalar"){ + values (0); + } + fall_power("scalar"){ + values (0); + } + } + } + bus(A_DIN) { + bus_type : D_15_0; + direction : input ; + capacitance : 0.00358485 ; + memory_write() { + address : A_ADDR ; + clocked_on : A_CLK; + } + + max_transition : "0.5952" ; + pin(A_DIN[15:0]) { + related_power_pin : VDD; + related_ground_pin : VSS; + internal_power() { + when : "A_MEN"; + rise_power("scalar"){ + values (0.0469); + } + fall_power("scalar"){ + values (0.0152); + } + } + internal_power() { + when : "!A_MEN"; + rise_power("scalar"){ + values (0.0453); + } + fall_power("scalar"){ + values (0.0145); + } + } + } + timing() { + timing_type : setup_rising; + related_pin : "A_CLK"; + when : "(A_WEN & A_MEN)"; + sdf_cond : "A_W_ACCESS"; + + rise_constraint("SIG2SRAM_constraint_template") { + index_1("0.0080,0.0288,0.0616,0.1072,0.1920,0.3496,0.5952"); + index_2("0.0080,0.0288,0.0616,0.1072,0.1920,0.3496,0.5952"); + values ("-0.6209,-0.6013,-0.5750,-0.5330,-0.4519,-0.3074,-0.0867",\ +"-0.6288,-0.6092,-0.5829,-0.5409,-0.4598,-0.3153,-0.0946",\ +"-0.6379,-0.6184,-0.5920,-0.5500,-0.4690,-0.3244,-0.1037",\ +"-0.6529,-0.6334,-0.6070,-0.5650,-0.4839,-0.3394,-0.1187",\ +"-0.6753,-0.6557,-0.6294,-0.5874,-0.5063,-0.3618,-0.1411",\ +"-0.7189,-0.6993,-0.6730,-0.6310,-0.5499,-0.4054,-0.1847",\ +"-0.7881,-0.7685,-0.7422,-0.7002,-0.6191,-0.4746,-0.2539"); + } + + fall_constraint("SIG2SRAM_constraint_template") { + index_1("0.0080,0.0288,0.0616,0.1072,0.1920,0.3496,0.5952"); + index_2("0.0080,0.0288,0.0616,0.1072,0.1920,0.3496,0.5952"); + values ("-0.5652,-0.5496,-0.5212,-0.4822,-0.4011,-0.2634,-0.0515",\ +"-0.5731,-0.5575,-0.5292,-0.4901,-0.4090,-0.2714,-0.0594",\ +"-0.5823,-0.5666,-0.5383,-0.4992,-0.4182,-0.2805,-0.0686",\ +"-0.5972,-0.5816,-0.5533,-0.5142,-0.4332,-0.2955,-0.0836",\ +"-0.6196,-0.6040,-0.5757,-0.5366,-0.4556,-0.3179,-0.1059",\ +"-0.6632,-0.6476,-0.6193,-0.5802,-0.4992,-0.3615,-0.1495",\ +"-0.7324,-0.7168,-0.6885,-0.6494,-0.5683,-0.4306,-0.2187"); + } + } + + timing() { + timing_type : hold_rising; + related_pin : "A_CLK"; + when : "(A_WEN & A_MEN)"; + sdf_cond : "A_W_ACCESS"; + + rise_constraint("SIG2SRAM_constraint_template") { + index_1("0.0080,0.0288,0.0616,0.1072,0.1920,0.3496,0.5952"); + index_2("0.0080,0.0288,0.0616,0.1072,0.1920,0.3496,0.5952"); + values ("0.7376,0.7161,0.6898,0.6468,0.5677,0.4222,0.1966",\ +"0.7455,0.7241,0.6977,0.6547,0.5756,0.4301,0.2045",\ +"0.7547,0.7332,0.7068,0.6639,0.5848,0.4393,0.2137",\ +"0.7697,0.7482,0.7218,0.6788,0.5998,0.4542,0.2287",\ +"0.7921,0.7706,0.7442,0.7012,0.6221,0.4766,0.2510",\ +"0.8357,0.8142,0.7878,0.7448,0.6657,0.5202,0.2946",\ +"0.9048,0.8833,0.8570,0.8140,0.7349,0.5894,0.3638"); + } + + fall_constraint("SIG2SRAM_constraint_template") { + index_1("0.0080,0.0288,0.0616,0.1072,0.1920,0.3496,0.5952"); + index_2("0.0080,0.0288,0.0616,0.1072,0.1920,0.3496,0.5952"); + values ("0.6693,0.6527,0.6243,0.5804,0.5033,0.3656,0.1556",\ +"0.6772,0.6606,0.6323,0.5883,0.5112,0.3735,0.1635",\ +"0.6863,0.6697,0.6414,0.5975,0.5203,0.3826,0.1727",\ +"0.7013,0.6847,0.6564,0.6124,0.5353,0.3976,0.1876",\ +"0.7237,0.7071,0.6788,0.6348,0.5577,0.4200,0.2100",\ +"0.7673,0.7507,0.7224,0.6784,0.6013,0.4636,0.2536",\ +"0.8365,0.8199,0.7916,0.7476,0.6705,0.5328,0.3228"); + } + } + } + + pin(A_BIST_EN) { + direction : input ; + capacitance : 0.00387999 ; + max_transition : "1" ; + related_power_pin : VDD; + related_ground_pin : VSS; + internal_power() { + rise_power("scalar") { + values (0); + } + fall_power("scalar") { + values (0); + } + } + } + +bus(A_BIST_ADDR) { + bus_type : A_7_0; + direction : input ; + capacitance : 0.0077013 ; + pin(A_BIST_ADDR[0]) { + capacitance : 0.00625349 ; + } + pin(A_BIST_ADDR[1]) { + capacitance : 0.00507435 ; + } + pin(A_BIST_ADDR[2]) { + capacitance : 0.00656707 ; + } + pin(A_BIST_ADDR[3]) { + capacitance : 0.0083133 ; + } + pin(A_BIST_ADDR[4]) { + capacitance : 0.00507219 ; + } + pin(A_BIST_ADDR[5]) { + capacitance : 0.00964344 ; + } + pin(A_BIST_ADDR[6]) { + capacitance : 0.0119653 ; + } + max_transition : "0.5952" ; + pin(A_BIST_ADDR[7:0]) { + related_power_pin : VDD; + related_ground_pin : VSS; + internal_power() { + when : "A_BIST_MEN"; + rise_power("scalar"){ + values (0.0102); + } + fall_power("scalar"){ + values (0.0077); + } + } + internal_power() { + when : "!A_BIST_MEN"; + rise_power("scalar"){ + values (0.0150); + } + fall_power("scalar"){ + values (0.0029); + } + } + } + timing() { + timing_type : setup_rising; + related_pin : "A_BIST_CLK"; + when : "((A_BIST_WEN | A_BIST_REN)& A_BIST_MEN)" + sdf_cond : "A_BIST_RW_ACCESS" + + rise_constraint("SIG2SRAM_constraint_template") { + index_1("0.0080,0.0288,0.0616,0.1072,0.1920,0.3496,0.5952"); + index_2("0.0080,0.0288,0.0616,0.1072,0.1920,0.3496,0.5952"); + values ("-0.7371,-0.7176,-0.6863,-0.6434,-0.5652,-0.4168,-0.1980",\ +"-0.7566,-0.7371,-0.7059,-0.6629,-0.5848,-0.4363,-0.2137",\ +"-0.7879,-0.7645,-0.7332,-0.6902,-0.6121,-0.4637,-0.2449",\ +"-0.8309,-0.8074,-0.7762,-0.7332,-0.6551,-0.5066,-0.2879",\ +"-0.9051,-0.8895,-0.8543,-0.8113,-0.7332,-0.5887,-0.3660",\ +"-1.0418,-1.0262,-0.9949,-0.9480,-0.8699,-0.7293,-0.5027",\ +"-1.2684,-1.2449,-1.2176,-1.1707,-1.0965,-0.9480,-0.7293"); + } + + fall_constraint("SIG2SRAM_constraint_template") { + index_1("0.0080,0.0288,0.0616,0.1072,0.1920,0.3496,0.5952"); + index_2("0.0080,0.0288,0.0616,0.1072,0.1920,0.3496,0.5952"); + values ("-0.5926,-0.5730,-0.5418,-0.4988,-0.4246,-0.2879,-0.0730",\ +"-0.6121,-0.5926,-0.5613,-0.5223,-0.4441,-0.3074,-0.0887",\ +"-0.6395,-0.6199,-0.5926,-0.5496,-0.4715,-0.3348,-0.1160",\ +"-0.6863,-0.6668,-0.6355,-0.5965,-0.5184,-0.3777,-0.1590",\ +"-0.7605,-0.7410,-0.7137,-0.6746,-0.5926,-0.4559,-0.2410",\ +"-0.9012,-0.8816,-0.8504,-0.8113,-0.7332,-0.5926,-0.3895",\ +"-1.1238,-1.1043,-1.0769,-1.0379,-0.9559,-0.8191,-0.6004"); + } + } + + + timing() { + timing_type : hold_rising; + related_pin : "A_BIST_CLK"; + when : "((A_BIST_WEN | A_BIST_REN)& A_BIST_MEN)" + sdf_cond : "A_BIST_RW_ACCESS" + + rise_constraint("SIG2SRAM_constraint_template") { + index_1("0.0080,0.0288,0.0616,0.1072,0.1920,0.3496,0.5952"); + index_2("0.0080,0.0288,0.0616,0.1072,0.1920,0.3496,0.5952"); + values ("0.8488,0.8293,0.7980,0.7551,0.6730,0.5285,0.3059",\ +"0.8684,0.8488,0.8176,0.7746,0.6926,0.5480,0.3254",\ +"0.8996,0.8801,0.8449,0.8020,0.7238,0.5754,0.3527",\ +"0.9426,0.9191,0.8918,0.8488,0.7668,0.6223,0.3996",\ +"1.0168,1.0012,0.9699,0.9230,0.8449,0.7004,0.4777",\ +"1.1574,1.1379,1.1105,1.0598,0.9816,0.8371,0.6184",\ +"1.3801,1.3605,1.3254,1.2980,1.2043,1.0637,0.8371"); + } + + fall_constraint("SIG2SRAM_constraint_template") { + index_1("0.0080,0.0288,0.0616,0.1072,0.1920,0.3496,0.5952"); + index_2("0.0080,0.0288,0.0616,0.1072,0.1920,0.3496,0.5952"); + values ("0.6965,0.6770,0.6496,0.6066,0.5246,0.3918,0.1730",\ +"0.7160,0.6965,0.6652,0.6262,0.5441,0.4113,0.1965",\ +"0.7473,0.7277,0.6965,0.6535,0.5754,0.4426,0.2238",\ +"0.7863,0.7707,0.7395,0.7004,0.6223,0.4855,0.2629",\ +"0.8684,0.8449,0.8176,0.7785,0.7004,0.5637,0.3449",\ +"1.0051,0.9855,0.9855,0.9113,0.8332,0.7004,0.4895",\ +"1.2277,1.2082,1.1809,1.1379,1.0598,0.9230,0.7004"); + } + } +} +pin(A_BIST_WEN) { + direction : input ; + capacitance : 0.00313551 ; + max_transition : "0.5952" ; + related_power_pin : VDD; + related_ground_pin : VSS; + internal_power() { + when : "A_BIST_MEN"; + rise_power("scalar"){ + values (0.0036); + } + fall_power("scalar"){ + values (0.0007); + } + } + internal_power() { + when : "!A_BIST_MEN"; + rise_power("scalar"){ + values (0.0050); + } + fall_power("scalar"){ + values (0.0002); + } + } + timing() { + timing_type : setup_rising; + related_pin : "A_BIST_CLK"; + when : "A_BIST_MEN" + sdf_cond : "A_BIST_MEN" + + rise_constraint("SIG2SRAM_constraint_template") { + index_1("0.0080,0.0288,0.0616,0.1072,0.1920,0.3496,0.5952"); + index_2("0.0080,0.0288,0.0616,0.1072,0.1920,0.3496,0.5952"); + values ("0.3137,0.3332,0.3605,0.4035,0.4816,0.6223,0.8488",\ +"0.2980,0.3176,0.3410,0.3840,0.4660,0.6027,0.8293",\ +"0.2629,0.2824,0.3098,0.3527,0.4348,0.5754,0.7980",\ +"0.2199,0.2395,0.2668,0.3098,0.3918,0.5324,0.7590",\ +"0.1418,0.1613,0.1887,0.2316,0.3137,0.4348,0.6730",\ +"0.0012,0.0207,0.0520,0.0910,0.1730,0.3098,0.5285",\ +"-0.2215,-0.2020,-0.1746,-0.1277,-0.0496,0.0910,0.3098"); + } + + fall_constraint("SIG2SRAM_constraint_template") { + index_1("0.0080,0.0288,0.0616,0.1072,0.1920,0.3496,0.5952"); + index_2("0.0080,0.0288,0.0616,0.1072,0.1920,0.3496,0.5952"); + values ("0.4504,0.4699,0.4973,0.5324,0.6027,0.7355,0.9699",\ +"0.4309,0.4504,0.4777,0.5129,0.5910,0.7160,0.9504",\ +"0.3996,0.4191,0.4465,0.4816,0.5520,0.6848,0.9191",\ +"0.3605,0.3762,0.4035,0.4387,0.5168,0.6418,0.8723",\ +"0.2785,0.2980,0.3215,0.3605,0.4348,0.5637,0.7980",\ +"0.1379,0.1574,0.1809,0.2199,0.2980,0.4309,0.6457",\ +"-0.0809,-0.0613,-0.0340,0.0051,0.0832,0.2160,0.4191"); + } + } + + + timing() { + timing_type : hold_rising; + related_pin : "A_BIST_CLK"; + when : "A_BIST_MEN" + sdf_cond : "A_BIST_MEN" + + rise_constraint("SIG2SRAM_constraint_template") { + index_1("0.0080,0.0288,0.0616,0.1072,0.1920,0.3496,0.5952"); + index_2("0.0080,0.0288,0.0616,0.1072,0.1920,0.3496,0.5952"); + values ("0.3723,0.3527,0.3215,0.2785,0.1965,0.0559,-0.1668",\ +"0.3918,0.3723,0.3449,0.2980,0.2160,0.0754,-0.1473",\ +"0.4152,0.3996,0.3684,0.3254,0.2434,0.1066,-0.1199",\ +"0.4621,0.4465,0.4152,0.3723,0.2863,0.1496,-0.0730",\ +"0.5324,0.5207,0.4895,0.4465,0.3645,0.2199,0.0051",\ +"0.6770,0.6535,0.6301,0.5832,0.5090,0.3605,0.1418",\ +"0.9035,0.8879,0.8566,0.8137,0.7316,0.5871,0.3684"); + } + + fall_constraint("SIG2SRAM_constraint_template") { + index_1("0.0080,0.0288,0.0616,0.1072,0.1920,0.3496,0.5952"); + index_2("0.0080,0.0288,0.0616,0.1072,0.1920,0.3496,0.5952"); + values ("0.3762,0.3566,0.3293,0.2863,0.2043,0.0676,-0.1434",\ +"0.3957,0.3762,0.3488,0.3059,0.2238,0.0871,-0.1199",\ +"0.4230,0.4035,0.3723,0.3332,0.2512,0.1184,-0.0965",\ +"0.4660,0.4465,0.4191,0.3762,0.2941,0.1613,-0.0496",\ +"0.5324,0.5168,0.4973,0.4543,0.3723,0.2316,0.0285",\ +"0.6809,0.6613,0.6340,0.5910,0.5129,0.3645,0.1652",\ +"0.9113,0.8918,0.8605,0.8176,0.7395,0.5988,0.3879"); + } + } + } +pin(A_BIST_REN) { + direction : input ; + capacitance : 0.00381144 ; + max_transition : "0.5952" ; + related_power_pin : VDD; + related_ground_pin : VSS; + internal_power() { + when : "A_BIST_MEN"; + rise_power("scalar"){ + values (0.0040); + } + fall_power("scalar"){ + values (0.0015); + } + } + internal_power() { + when : "!A_BIST_MEN"; + rise_power("scalar"){ + values (0.0040); + } + fall_power("scalar"){ + values (0.0013); + } + } + timing() { + timing_type : setup_rising; + related_pin : "A_BIST_CLK"; + when : "A_BIST_MEN" + sdf_cond : "A_BIST_MEN" + + rise_constraint("SIG2SRAM_constraint_template") { + index_1("0.0080,0.0288,0.0616,0.1072,0.1920,0.3496,0.5952"); + index_2("0.0080,0.0288,0.0616,0.1072,0.1920,0.3496,0.5952"); + values ("-0.0770,-0.0574,-0.0262,0.0168,0.0949,0.2355,0.4582",\ +"-0.0965,-0.0770,-0.0457,-0.0027,0.0754,0.2160,0.4387",\ +"-0.1199,-0.1004,-0.0730,-0.0262,0.0520,0.1887,0.4113",\ +"-0.1590,-0.1434,-0.1160,-0.0730,0.0051,0.1457,0.3645",\ +"-0.2449,-0.2254,-0.1941,-0.1473,-0.0770,0.0676,0.2863",\ +"-0.3816,-0.3699,-0.3387,-0.2801,-0.2215,-0.0770,0.1457",\ +"-0.6121,-0.5926,-0.5613,-0.5145,-0.4363,-0.2996,-0.0730"); + } + + fall_constraint("SIG2SRAM_constraint_template") { + index_1("0.0080,0.0288,0.0616,0.1072,0.1920,0.3496,0.5952"); + index_2("0.0080,0.0288,0.0616,0.1072,0.1920,0.3496,0.5952"); + values ("0.1262,0.1457,0.1691,0.2121,0.2824,0.4191,0.6457",\ +"0.1105,0.1262,0.1496,0.1887,0.2629,0.3996,0.6262",\ +"0.0793,0.0949,0.1223,0.1652,0.2395,0.3684,0.5949",\ +"0.0363,0.0559,0.0793,0.1223,0.2004,0.3410,0.5520",\ +"-0.0457,-0.0262,0.0012,0.0441,0.1301,0.2629,0.4738",\ +"-0.1902,-0.1746,-0.1434,-0.1043,-0.0184,0.1223,0.3332",\ +"-0.4129,-0.3934,-0.3660,-0.3230,-0.2449,-0.1043,0.1105"); + } + } + + + timing() { + timing_type : hold_rising; + related_pin : "A_BIST_CLK"; + when : "A_BIST_MEN" + sdf_cond : "A_BIST_MEN" + + rise_constraint("SIG2SRAM_constraint_template") { + index_1("0.0080,0.0288,0.0616,0.1072,0.1920,0.3496,0.5952"); + index_2("0.0080,0.0288,0.0616,0.1072,0.1920,0.3496,0.5952"); + values ("0.4113,0.3918,0.3645,0.3176,0.2395,0.0988,-0.1238",\ +"0.4309,0.4113,0.3840,0.3371,0.2590,0.1184,-0.1043",\ +"0.4582,0.4387,0.4113,0.3645,0.2824,0.1457,-0.0770",\ +"0.5051,0.4816,0.4543,0.4074,0.3293,0.1887,-0.0340",\ +"0.5715,0.5598,0.5324,0.4895,0.4035,0.2512,0.0441",\ +"0.7043,0.7004,0.6730,0.6262,0.5402,0.3957,0.1809",\ +"0.9387,0.9270,0.8957,0.8527,0.7746,0.6262,0.4074"); + } + + fall_constraint("SIG2SRAM_constraint_template") { + index_1("0.0080,0.0288,0.0616,0.1072,0.1920,0.3496,0.5952"); + index_2("0.0080,0.0288,0.0616,0.1072,0.1920,0.3496,0.5952"); + values ("0.4152,0.3918,0.3645,0.3215,0.2395,0.1027,-0.1082",\ +"0.4309,0.4113,0.3801,0.3410,0.2590,0.1223,-0.0926",\ +"0.4582,0.4387,0.4074,0.3684,0.2863,0.1496,-0.0613",\ +"0.5012,0.4816,0.4504,0.4074,0.3293,0.1887,-0.0145",\ +"0.5715,0.5559,0.5285,0.4816,0.3996,0.2512,0.0598",\ +"0.7160,0.7004,0.6691,0.6262,0.5520,0.4035,0.2004",\ +"0.9387,0.9191,0.8957,0.8488,0.7707,0.6262,0.4113"); + } + } + } +pin(A_BIST_MEN) { + direction : input ; + capacitance : 0.00300347 ; + max_transition : "0.5952" ; + related_power_pin : VDD; + related_ground_pin : VSS; + internal_power() { + rise_power("scalar"){ + values (0.0161); + } + fall_power("scalar"){ + values (0.0002); + } + } + timing() { + timing_type : setup_rising; + related_pin : "A_BIST_CLK"; + + rise_constraint("SIG2SRAM_constraint_template") { + index_1("0.0080,0.0288,0.0616,0.1072,0.1920,0.3496,0.5952"); + index_2("0.0080,0.0288,0.0616,0.1072,0.1920,0.3496,0.5952"); + values ("0.3215,0.3449,0.3684,0.4113,0.4895,0.6301,0.8527",\ +"0.3059,0.3254,0.3527,0.3957,0.4738,0.6145,0.8371",\ +"0.2746,0.2941,0.3215,0.3645,0.4426,0.5871,0.8059",\ +"0.2316,0.2512,0.2785,0.3215,0.3996,0.5402,0.7629",\ +"0.1496,0.1730,0.1965,0.2395,0.3215,0.4660,0.6848",\ +"0.0090,0.0285,0.0598,0.1027,0.1809,0.3176,0.5402",\ +"-0.2098,-0.1902,-0.1668,-0.1199,-0.0418,0.0988,0.3137"); + } + + fall_constraint("SIG2SRAM_constraint_template") { + index_1("0.0080,0.0288,0.0616,0.1072,0.1920,0.3496,0.5952"); + index_2("0.0080,0.0288,0.0616,0.1072,0.1920,0.3496,0.5952"); + values ("0.4582,0.4738,0.5012,0.5363,0.6145,0.7395,0.9738",\ +"0.4387,0.4543,0.4816,0.5207,0.5910,0.7199,0.9582",\ +"0.4035,0.4230,0.4504,0.4855,0.5637,0.6887,0.9230",\ +"0.3645,0.3840,0.4074,0.4465,0.5285,0.6496,0.8840",\ +"0.2824,0.3020,0.3254,0.3645,0.4465,0.5715,0.7980",\ +"0.1418,0.1613,0.1887,0.2238,0.3020,0.4309,0.6496",\ +"-0.0770,-0.0574,-0.0301,0.0090,0.0910,0.2238,0.4191"); + } + } + + + timing() { + timing_type : hold_rising; + related_pin : "A_BIST_CLK"; + + rise_constraint("SIG2SRAM_constraint_template") { + index_1("0.0080,0.0288,0.0616,0.1072,0.1920,0.3496,0.5952"); + index_2("0.0080,0.0288,0.0616,0.1072,0.1920,0.3496,0.5952"); + values ("0.3762,0.3605,0.3293,0.2863,0.2043,0.0637,-0.1629",\ +"0.3996,0.3801,0.3488,0.3020,0.2238,0.0832,-0.1395",\ +"0.4230,0.4074,0.3723,0.3293,0.2473,0.1105,-0.1121",\ +"0.4621,0.4465,0.4152,0.3762,0.2941,0.1535,-0.0691",\ +"0.5441,0.5285,0.4973,0.4465,0.3684,0.2316,0.0090",\ +"0.6848,0.6652,0.6301,0.5910,0.5129,0.3605,0.1496",\ +"0.9074,0.8918,0.8566,0.8215,0.7395,0.5910,0.3723"); + } + + fall_constraint("SIG2SRAM_constraint_template") { + index_1("0.0080,0.0288,0.0616,0.1072,0.1920,0.3496,0.5952"); + index_2("0.0080,0.0288,0.0616,0.1072,0.1920,0.3496,0.5952"); + values ("0.3762,0.3605,0.3332,0.2863,0.2043,0.0715,-0.1395",\ +"0.3996,0.3762,0.3488,0.3059,0.2238,0.0910,-0.1199",\ +"0.4270,0.4035,0.3762,0.3332,0.2512,0.1184,-0.0965",\ +"0.4699,0.4504,0.4191,0.3762,0.2941,0.1613,-0.0496",\ +"0.5441,0.5285,0.4973,0.4543,0.3762,0.2355,0.0324",\ +"0.6770,0.6613,0.6340,0.5949,0.5207,0.3762,0.1652",\ +"0.9074,0.8918,0.8605,0.8176,0.7395,0.6027,0.3918"); + } + } + } +bus(A_BIST_BM) { + bus_type : D_15_0; + direction : input ; + capacitance : 0.00225269 ; + max_transition : "0.5952" ; + pin(A_BIST_BM[15:0]) { + related_power_pin : VDD; + related_ground_pin : VSS; + internal_power() { + when : "A_BIST_MEN"; + rise_power("scalar"){ + values (0.0469); + } + fall_power("scalar"){ + values (0.0152); + } + } + internal_power() { + when : "!A_BIST_MEN"; + rise_power("scalar"){ + values (0.0453); + } + fall_power("scalar"){ + values (0.0145); + } + } + } + timing() { + timing_type : setup_rising; + related_pin : "A_BIST_CLK"; + when : "(A_BIST_WEN & A_BIST_MEN)" + sdf_cond : "A_BIST_RW_ACCESS" + + rise_constraint("SIG2SRAM_constraint_template") { + index_1("0.0080,0.0288,0.0616,0.1072,0.1920,0.3496,0.5952"); + index_2("0.0080,0.0288,0.0616,0.1072,0.1920,0.3496,0.5952"); + values ("-0.6209,-0.6013,-0.5750,-0.5330,-0.4519,-0.3074,-0.0867",\ +"-0.6288,-0.6092,-0.5829,-0.5409,-0.4598,-0.3153,-0.0946",\ +"-0.6379,-0.6184,-0.5920,-0.5500,-0.4690,-0.3244,-0.1037",\ +"-0.6529,-0.6334,-0.6070,-0.5650,-0.4839,-0.3394,-0.1187",\ +"-0.6753,-0.6557,-0.6294,-0.5874,-0.5063,-0.3618,-0.1411",\ +"-0.7189,-0.6993,-0.6730,-0.6310,-0.5499,-0.4054,-0.1847",\ +"-0.7881,-0.7685,-0.7422,-0.7002,-0.6191,-0.4746,-0.2539"); + } + + fall_constraint("SIG2SRAM_constraint_template") { + index_1("0.0080,0.0288,0.0616,0.1072,0.1920,0.3496,0.5952"); + index_2("0.0080,0.0288,0.0616,0.1072,0.1920,0.3496,0.5952"); + values ("-0.5652,-0.5496,-0.5212,-0.4822,-0.4011,-0.2634,-0.0515",\ +"-0.5731,-0.5575,-0.5292,-0.4901,-0.4090,-0.2714,-0.0594",\ +"-0.5823,-0.5666,-0.5383,-0.4992,-0.4182,-0.2805,-0.0686",\ +"-0.5972,-0.5816,-0.5533,-0.5142,-0.4332,-0.2955,-0.0836",\ +"-0.6196,-0.6040,-0.5757,-0.5366,-0.4556,-0.3179,-0.1059",\ +"-0.6632,-0.6476,-0.6193,-0.5802,-0.4992,-0.3615,-0.1495",\ +"-0.7324,-0.7168,-0.6885,-0.6494,-0.5683,-0.4306,-0.2187"); + } + } + + + timing() { + timing_type : hold_rising; + related_pin : "A_BIST_CLK"; + when : "(A_BIST_WEN & A_BIST_MEN)" + sdf_cond : "A_BIST_RW_ACCESS" + + rise_constraint("SIG2SRAM_constraint_template") { + index_1("0.0080,0.0288,0.0616,0.1072,0.1920,0.3496,0.5952"); + index_2("0.0080,0.0288,0.0616,0.1072,0.1920,0.3496,0.5952"); + values ("0.7376,0.7161,0.6898,0.6468,0.5677,0.4222,0.1966",\ +"0.7455,0.7241,0.6977,0.6547,0.5756,0.4301,0.2045",\ +"0.7547,0.7332,0.7068,0.6639,0.5848,0.4393,0.2137",\ +"0.7697,0.7482,0.7218,0.6788,0.5998,0.4542,0.2287",\ +"0.7921,0.7706,0.7442,0.7012,0.6221,0.4766,0.2510",\ +"0.8357,0.8142,0.7878,0.7448,0.6657,0.5202,0.2946",\ +"0.9048,0.8833,0.8570,0.8140,0.7349,0.5894,0.3638"); + } + + fall_constraint("SIG2SRAM_constraint_template") { + index_1("0.0080,0.0288,0.0616,0.1072,0.1920,0.3496,0.5952"); + index_2("0.0080,0.0288,0.0616,0.1072,0.1920,0.3496,0.5952"); + values ("0.6693,0.6527,0.6243,0.5804,0.5033,0.3656,0.1556",\ +"0.6772,0.6606,0.6323,0.5883,0.5112,0.3735,0.1635",\ +"0.6863,0.6697,0.6414,0.5975,0.5203,0.3826,0.1727",\ +"0.7013,0.6847,0.6564,0.6124,0.5353,0.3976,0.1876",\ +"0.7237,0.7071,0.6788,0.6348,0.5577,0.4200,0.2100",\ +"0.7673,0.7507,0.7224,0.6784,0.6013,0.4636,0.2536",\ +"0.8365,0.8199,0.7916,0.7476,0.6705,0.5328,0.3228"); + } + } +} + pin(A_BIST_CLK) { + direction : input; + capacitance : 0.00378957; + max_transition : "0.5952"; + clock : "true" ; + pin_func_type : active_rising ; + + timing () { + timing_type : "min_pulse_width"; + related_pin : "A_BIST_CLK"; + rise_constraint("CLKTRAN_constraint_template") { + index_1("0.008,0.5952"); + values("0.4,0.4"); + } + } + + related_power_pin : VDD; + related_ground_pin : VSS; + + internal_power() { + when : "!A_BIST_MEN & !A_BIST_WEN & !A_BIST_REN"; + rise_power("scalar"){ + values (0); + } + fall_power("scalar"){ + values (0); + } + } + internal_power() { + when : "!A_BIST_MEN & A_BIST_WEN & !A_BIST_REN"; + rise_power("scalar"){ + values (0.4498); + } + fall_power("scalar"){ + values (0); + } + } + internal_power() { + when : "A_BIST_MEN & A_BIST_WEN & !A_BIST_REN"; + rise_power("scalar"){ + values (15.3644); + } + fall_power("scalar"){ + values (0); + } + } + internal_power() { + when : "A_BIST_MEN & A_BIST_WEN & A_BIST_REN"; + rise_power("scalar"){ + values (16.3884); + } + fall_power("scalar"){ + values (0); + } + } + internal_power() { + when : "A_BIST_MEN & !A_BIST_WEN & A_BIST_REN"; + rise_power("scalar"){ + values (11.8557); + } + fall_power("scalar"){ + values (0); + } + } + internal_power() { + when : "!A_BIST_MEN & !A_BIST_WEN & A_BIST_REN"; + rise_power("scalar"){ + values (0.2837); + } + fall_power("scalar"){ + values (0); + } + } + internal_power() { + when : "!A_BIST_MEN & A_BIST_WEN & A_BIST_REN"; + rise_power("scalar"){ + values (0.6730); + } + fall_power("scalar"){ + values (0); + } + } + internal_power() { + when : "A_BIST_MEN & !A_BIST_WEN & !A_BIST_REN"; + rise_power("scalar"){ + values (0); + } + fall_power("scalar"){ + values (0); + } + } + } + bus(A_BIST_DIN) { + bus_type : D_15_0; + direction : input ; + capacitance : 0.00226348 ; + memory_write() { + address : A_BIST_ADDR ; + clocked_on : A_BIST_CLK; + } + + max_transition : "0.5952" ; + pin(A_BIST_DIN[15:0]) { + related_power_pin : VDD; + related_ground_pin : VSS; + internal_power() { + when : "A_BIST_MEN"; + rise_power("scalar"){ + values (0.0469); + } + fall_power("scalar"){ + values (0.0152); + } + } + internal_power() { + when : "!A_BIST_MEN"; + rise_power("scalar"){ + values (0.0453); + } + fall_power("scalar"){ + values (0.0145); + } + } + } + timing() { + timing_type : setup_rising; + related_pin : "A_BIST_CLK"; + when : "(A_BIST_WEN & A_BIST_MEN)"; + sdf_cond : "A_BIST_W_ACCESS"; + + rise_constraint("SIG2SRAM_constraint_template") { + index_1("0.0080,0.0288,0.0616,0.1072,0.1920,0.3496,0.5952"); + index_2("0.0080,0.0288,0.0616,0.1072,0.1920,0.3496,0.5952"); + values ("-0.6209,-0.6013,-0.5750,-0.5330,-0.4519,-0.3074,-0.0867",\ +"-0.6288,-0.6092,-0.5829,-0.5409,-0.4598,-0.3153,-0.0946",\ +"-0.6379,-0.6184,-0.5920,-0.5500,-0.4690,-0.3244,-0.1037",\ +"-0.6529,-0.6334,-0.6070,-0.5650,-0.4839,-0.3394,-0.1187",\ +"-0.6753,-0.6557,-0.6294,-0.5874,-0.5063,-0.3618,-0.1411",\ +"-0.7189,-0.6993,-0.6730,-0.6310,-0.5499,-0.4054,-0.1847",\ +"-0.7881,-0.7685,-0.7422,-0.7002,-0.6191,-0.4746,-0.2539"); + } + + fall_constraint("SIG2SRAM_constraint_template") { + index_1("0.0080,0.0288,0.0616,0.1072,0.1920,0.3496,0.5952"); + index_2("0.0080,0.0288,0.0616,0.1072,0.1920,0.3496,0.5952"); + values ("-0.5652,-0.5496,-0.5212,-0.4822,-0.4011,-0.2634,-0.0515",\ +"-0.5731,-0.5575,-0.5292,-0.4901,-0.4090,-0.2714,-0.0594",\ +"-0.5823,-0.5666,-0.5383,-0.4992,-0.4182,-0.2805,-0.0686",\ +"-0.5972,-0.5816,-0.5533,-0.5142,-0.4332,-0.2955,-0.0836",\ +"-0.6196,-0.6040,-0.5757,-0.5366,-0.4556,-0.3179,-0.1059",\ +"-0.6632,-0.6476,-0.6193,-0.5802,-0.4992,-0.3615,-0.1495",\ +"-0.7324,-0.7168,-0.6885,-0.6494,-0.5683,-0.4306,-0.2187"); + } + } + + timing() { + timing_type : hold_rising; + related_pin : "A_BIST_CLK"; + when : "(A_BIST_WEN & A_BIST_MEN)"; + sdf_cond : "A_BIST_W_ACCESS"; + + rise_constraint("SIG2SRAM_constraint_template") { + index_1("0.0080,0.0288,0.0616,0.1072,0.1920,0.3496,0.5952"); + index_2("0.0080,0.0288,0.0616,0.1072,0.1920,0.3496,0.5952"); + values ("0.7376,0.7161,0.6898,0.6468,0.5677,0.4222,0.1966",\ +"0.7455,0.7241,0.6977,0.6547,0.5756,0.4301,0.2045",\ +"0.7547,0.7332,0.7068,0.6639,0.5848,0.4393,0.2137",\ +"0.7697,0.7482,0.7218,0.6788,0.5998,0.4542,0.2287",\ +"0.7921,0.7706,0.7442,0.7012,0.6221,0.4766,0.2510",\ +"0.8357,0.8142,0.7878,0.7448,0.6657,0.5202,0.2946",\ +"0.9048,0.8833,0.8570,0.8140,0.7349,0.5894,0.3638"); + } + + fall_constraint("SIG2SRAM_constraint_template") { + index_1("0.0080,0.0288,0.0616,0.1072,0.1920,0.3496,0.5952"); + index_2("0.0080,0.0288,0.0616,0.1072,0.1920,0.3496,0.5952"); + values ("0.6693,0.6527,0.6243,0.5804,0.5033,0.3656,0.1556",\ +"0.6772,0.6606,0.6323,0.5883,0.5112,0.3735,0.1635",\ +"0.6863,0.6697,0.6414,0.5975,0.5203,0.3826,0.1727",\ +"0.7013,0.6847,0.6564,0.6124,0.5353,0.3976,0.1876",\ +"0.7237,0.7071,0.6788,0.6348,0.5577,0.4200,0.2100",\ +"0.7673,0.7507,0.7224,0.6784,0.6013,0.4636,0.2536",\ +"0.8365,0.8199,0.7916,0.7476,0.6705,0.5328,0.3228"); + } + } + } + +bus(A_DOUT) { + + bus_type : D_15_0; + direction : output ; + capacitance : 0 ; + max_capacitance : 0.064 ; + memory_read() { + address : A_ADDR ; + } + pin(A_DOUT[15:0]) { + related_power_pin : VDD; + related_ground_pin : VSS; + internal_power() { + rise_power("scalar") { + values (0); + } + fall_power("scalar") { + values (0); + } + } + } + timing() { + related_pin : "A_CLK"; + timing_type : rising_edge ; + timing_sense : non_unate ; + + cell_rise(SIG2SRAM_delay_template) { + index_1("0.0080,0.0288,0.0616,0.1072,0.1920,0.3496,0.5952"); + index_2("0.0008,0.0014,0.0051,0.0100,0.0339,0.0640"); + values ("4.9940,4.9967,5.0089,5.0231,5.0757,5.1307",\ +"5.0079,5.0106,5.0228,5.0370,5.0896,5.1446",\ +"5.0178,5.0205,5.0326,5.0469,5.0994,5.1544",\ +"5.0311,5.0338,5.0459,5.0602,5.1127,5.1677",\ +"5.0543,5.0570,5.0692,5.0834,5.1360,5.1910",\ +"5.0991,5.1018,5.1140,5.1282,5.1808,5.2357",\ +"5.1663,5.1691,5.1812,5.1954,5.2480,5.3030"); + } + cell_fall(SIG2SRAM_delay_template) { + index_1("0.0080,0.0288,0.0616,0.1072,0.1920,0.3496,0.5952"); + index_2("0.0008,0.0014,0.0051,0.0100,0.0339,0.0640"); + values ("4.8838,4.8860,4.8958,4.9076,4.9512,4.9949",\ +"4.8977,4.8999,4.9097,4.9215,4.9651,5.0088",\ +"4.9076,4.9098,4.9195,4.9314,4.9749,5.0186",\ +"4.9209,4.9230,4.9328,4.9446,4.9882,5.0319",\ +"4.9441,4.9463,4.9561,4.9679,5.0115,5.0552",\ +"4.9889,4.9911,5.0008,5.0127,5.0562,5.1000",\ +"5.0562,5.0583,5.0681,5.0799,5.1235,5.1672"); + } + + rise_transition(SRAM_load_template) { + index_1("0.0008,0.0014,0.0051,0.0100,0.0339,0.0640"); + values ("0.0560,0.0583,0.0696,0.0816,0.1519,0.2335"); + } + fall_transition(SRAM_load_template) { + index_1("0.0008,0.0014,0.0051,0.0100,0.0339,0.0640"); + values ("0.0428,0.0445,0.0538,0.0658,0.1181,0.1751"); + } + } +} +cell_leakage_power : 326.6470; +} +} diff --git a/flow/platforms/ihp-sg13g2/lib/RM_IHPSG13_1P_256x16_c2_bm_bist_typ_1p20V_25C.lib b/flow/platforms/ihp-sg13g2/lib/RM_IHPSG13_1P_256x16_c2_bm_bist_typ_1p20V_25C.lib new file mode 100644 index 0000000000..05ac4b8904 --- /dev/null +++ b/flow/platforms/ihp-sg13g2/lib/RM_IHPSG13_1P_256x16_c2_bm_bist_typ_1p20V_25C.lib @@ -0,0 +1,1513 @@ +/* ------------------------------------------------------*/ +/**/ +/* Copyright 2025 IHP PDK Authors*/ +/**/ +/* Licensed under the Apache License, Version 2.0 (the "License");*/ +/* you may not use this file except in compliance with the License.*/ +/* You may obtain a copy of the License at*/ +/* */ +/* https://www.apache.org/licenses/LICENSE-2.0*/ +/* */ +/* Unless required by applicable law or agreed to in writing, software*/ +/* distributed under the License is distributed on an "AS IS" BASIS,*/ +/* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.*/ +/* See the License for the specific language governing permissions and*/ +/* limitations under the License.*/ +/* */ +/* Generated on Wed Aug 27 12:14:48 2025 */ +/* */ +/* ------------------------------------------------------ */ +library(RM_IHPSG13_1P_256x16_c2_bm_bist_typ_1p20V_25C) { + technology (cmos) ; + delay_model : table_lookup ; + define ("add_pg_pin_to_lib", "library", "boolean"); + add_pg_pin_to_lib : true; + voltage_map ( VDD, 1.20); + voltage_map ( VDDARRAY, 1.20); + voltage_map ( VSS, 0.000000 ); + + date : "Wed Aug 27 12:14:46 2025" ; + comment : "IHP Microelectronics GmbH, 2023" ; + revision : 1.0.0 ; + simulation : true ; + nom_process : 1 ; + nom_temperature : 25 ; + nom_voltage : 1.20 ; + + operating_conditions("typ_1p20V_25C"){ + process : 1 ; + temperature : 25 ; + voltage : 1.20 ; + tree_type : "balanced_tree" ; + } + + default_operating_conditions : typ_1p20V_25C ; + default_max_transition : 1.0 ; + default_fanout_load : 1.0 ; + default_inout_pin_cap : 0.0 ; + default_input_pin_cap : 0.0 ; + default_output_pin_cap : 0.0 ; + default_cell_leakage_power : 0.0 ; + default_leakage_power_density : 0.0 ; + + slew_lower_threshold_pct_rise : 30 ; + slew_upper_threshold_pct_rise : 70 ; + input_threshold_pct_fall : 50 ; + output_threshold_pct_fall : 50 ; + input_threshold_pct_rise : 50 ; + output_threshold_pct_rise : 50 ; + slew_lower_threshold_pct_fall : 30 ; + slew_upper_threshold_pct_fall : 70 ; + slew_derate_from_library : 0.5; + k_volt_cell_leakage_power : 0.0 ; + k_temp_cell_leakage_power : 0.0 ; + k_process_cell_leakage_power : 0.0 ; + k_volt_internal_power : 0.0 ; + k_temp_internal_power : 0.0 ; + k_process_internal_power : 0.0 ; + + capacitive_load_unit (1,pf) ; + voltage_unit : "1V" ; + current_unit : "1uA" ; + time_unit : "1ns" ; + leakage_power_unit : "1nW" ; + pulling_resistance_unit : "1kohm"; + /* + ------------------------------------------------------------------------------------------ + implicit units overview: + cell_area unit : "um" + internal_power unit : "1e-12 * J/toggle = 1 * uW/MHz" + (capacitive_load_unit * voltage_unit^2) per toggle event + ------------------------------------------------------------------------------------------ + */ + library_features(report_delay_calculation); + define_cell_area (pad_drivers,pad_driver_sites) ; + + lu_table_template(CLKTRAN_constraint_template) { + variable_1 : constrained_pin_transition; + index_1 ( "0.010, 0.050, 0.200, 0.400, 1.000" ); + } + lu_table_template(SRAM_load_template) { + variable_1 : total_output_net_capacitance; + index_1 ( "0.0008,0.0014,0.0051,0.0100,0.0339,0.0640" ); + } + lu_table_template(SIG2SRAM_constraint_template) { + variable_1 : related_pin_transition; + variable_2 : constrained_pin_transition; + index_1 ( "0.0056,0.0232,0.0400,0.0728,0.1280,0.2440,0.4760" ); + index_2 ( "0.0056,0.0232,0.0400,0.0728,0.1280,0.2440,0.4760" ); + } + + lu_table_template(SIG2SRAM_delay_template) { + variable_1 : input_net_transition; + variable_2 : total_output_net_capacitance; + index_1 ( "0.0056,0.0232,0.0400,0.0728,0.1280,0.2440,0.4760" ); + index_2 ( "0.0008,0.0014,0.0051,0.0100,0.0339,0.0640" ); + } + + type (D_15_0) { + base_type : array; + data_type : bit; + bit_width : 16; + bit_from : 15; + bit_to : 0; + downto : true; + } + + type (A_7_0) { + base_type : array; + data_type : bit; + bit_width : 8; + bit_from : 7; + bit_to : 0; + downto : true; + } + +cell(RM_IHPSG13_1P_256x16_c2_bm_bist) { +pg_pin (VDD) { + pg_type : primary_power; + voltage_name : VDD; +} +pg_pin (VDDARRAY) { + pg_type : primary_power; + voltage_name : VDDARRAY; +} +pg_pin (VSS) { + pg_type : primary_ground; + voltage_name : VSS; +} + +memory() { + type : ram; + address_width : 8; + word_width : 16; +} + +interface_timing : false; +bus_naming_style : "%s[%d]" ; +area : 28127.104 ; + + pin(A_DLY) { + direction : input ; + capacitance : 0.00401111 ; + max_transition : "1" ; + related_power_pin : VDD; + related_ground_pin : VSS; + internal_power() { + rise_power("scalar") { + values (0); + } + fall_power("scalar") { + values (0); + } + } + } + +bus(A_ADDR) { + bus_type : A_7_0; + direction : input ; + capacitance : 0.00721489 ; + pin(A_ADDR[0]) { + capacitance : 0.00593979 ; + } + pin(A_ADDR[1]) { + capacitance : 0.00483009 ; + } + pin(A_ADDR[2]) { + capacitance : 0.006215 ; + } + pin(A_ADDR[3]) { + capacitance : 0.00766726 ; + } + pin(A_ADDR[4]) { + capacitance : 0.00488951 ; + } + pin(A_ADDR[5]) { + capacitance : 0.0091523 ; + } + pin(A_ADDR[6]) { + capacitance : 0.0109212 ; + } + max_transition : "0.476" ; + pin(A_ADDR[7:0]) { + related_power_pin : VDD; + related_ground_pin : VSS; + internal_power() { + when : "A_MEN"; + rise_power("scalar"){ + values (0.0109); + } + fall_power("scalar"){ + values (0.0051); + } + } + internal_power() { + when : "!A_MEN"; + rise_power("scalar"){ + values (0.0190); + } + fall_power("scalar"){ + values (0.0000); + } + } + } + timing() { + timing_type : setup_rising; + related_pin : "A_CLK"; + when : "((A_WEN | A_REN)& A_MEN)" + sdf_cond : "A_RW_ACCESS" + + rise_constraint("SIG2SRAM_constraint_template") { + index_1("0.0056,0.0232,0.0400,0.0728,0.1280,0.2440,0.4760"); + index_2("0.0056,0.0232,0.0400,0.0728,0.1280,0.2440,0.4760"); + values ("-0.4168,-0.3973,-0.3855,-0.3543,-0.3074,-0.2020,-0.0027",\ +"-0.4324,-0.4129,-0.4012,-0.3699,-0.3191,-0.2176,-0.0184",\ +"-0.4441,-0.4285,-0.4129,-0.3816,-0.3309,-0.2293,-0.0301",\ +"-0.4793,-0.4598,-0.4441,-0.4129,-0.3660,-0.2645,-0.0652",\ +"-0.5223,-0.5066,-0.4910,-0.4598,-0.4129,-0.3074,-0.1121",\ +"-0.6199,-0.6082,-0.5926,-0.5613,-0.5145,-0.4129,-0.2137",\ +"-0.8191,-0.8074,-0.7840,-0.7566,-0.7098,-0.6082,-0.4051"); + } + + fall_constraint("SIG2SRAM_constraint_template") { + index_1("0.0056,0.0232,0.0400,0.0728,0.1280,0.2440,0.4760"); + index_2("0.0056,0.0232,0.0400,0.0728,0.1280,0.2440,0.4760"); + values ("-0.3309,-0.3113,-0.2996,-0.2684,-0.2176,-0.1238,0.0637",\ +"-0.3465,-0.3309,-0.3152,-0.2840,-0.2332,-0.1395,0.0480",\ +"-0.3582,-0.3426,-0.3270,-0.2996,-0.2488,-0.1512,0.0324",\ +"-0.3895,-0.3738,-0.3582,-0.3309,-0.2801,-0.1863,0.0051",\ +"-0.4363,-0.4207,-0.4051,-0.3777,-0.3230,-0.2293,-0.0379",\ +"-0.5379,-0.5223,-0.5066,-0.4793,-0.4285,-0.3309,-0.1434",\ +"-0.7332,-0.7176,-0.7020,-0.6746,-0.6238,-0.5262,-0.3387"); + } + } + + + timing() { + timing_type : hold_rising; + related_pin : "A_CLK"; + when : "((A_WEN | A_REN)& A_MEN)" + sdf_cond : "A_RW_ACCESS" + + rise_constraint("SIG2SRAM_constraint_template") { + index_1("0.0056,0.0232,0.0400,0.0728,0.1280,0.2440,0.4760"); + index_2("0.0056,0.0232,0.0400,0.0728,0.1280,0.2440,0.4760"); + values ("0.5246,0.5051,0.4895,0.4582,0.4113,0.3059,0.1066",\ +"0.5402,0.5207,0.5051,0.4777,0.4270,0.3215,0.1223",\ +"0.5520,0.5324,0.5168,0.4895,0.4387,0.3371,0.1340",\ +"0.5832,0.5676,0.5520,0.5207,0.4738,0.3684,0.1691",\ +"0.6301,0.6105,0.5949,0.5676,0.5168,0.4113,0.2160",\ +"0.7316,0.7121,0.7004,0.6691,0.6223,0.5168,0.3176",\ +"0.9270,0.9230,0.8957,0.8645,0.8137,0.7121,0.5168"); + } + + fall_constraint("SIG2SRAM_constraint_template") { + index_1("0.0056,0.0232,0.0400,0.0728,0.1280,0.2440,0.4760"); + index_2("0.0056,0.0232,0.0400,0.0728,0.1280,0.2440,0.4760"); + values ("0.4309,0.4152,0.4035,0.3684,0.3215,0.2277,0.0363",\ +"0.4465,0.4309,0.4152,0.3879,0.3371,0.2395,0.0559",\ +"0.4582,0.4426,0.4309,0.3996,0.3488,0.2551,0.0715",\ +"0.4934,0.4777,0.4621,0.4348,0.3840,0.2863,0.0988",\ +"0.5363,0.5207,0.5051,0.4777,0.4270,0.3332,0.1418",\ +"0.6379,0.6262,0.6105,0.5793,0.5324,0.4348,0.2434",\ +"0.8332,0.8215,0.8059,0.7707,0.7238,0.6301,0.4387"); + } + } +} +pin(A_WEN) { + direction : input ; + capacitance : 0.00324098 ; + max_transition : "0.476" ; + related_power_pin : VDD; + related_ground_pin : VSS; + internal_power() { + when : "A_MEN"; + rise_power("scalar"){ + values (0.0046); + } + fall_power("scalar"){ + values (0.0038); + } + } + internal_power() { + when : "!A_MEN"; + rise_power("scalar"){ + values (0.0042); + } + fall_power("scalar"){ + values (0.0039); + } + } + timing() { + timing_type : setup_rising; + related_pin : "A_CLK"; + when : "A_MEN" + sdf_cond : "A_MEN" + + rise_constraint("SIG2SRAM_constraint_template") { + index_1("0.0056,0.0232,0.0400,0.0728,0.1280,0.2440,0.4760"); + index_2("0.0056,0.0232,0.0400,0.0728,0.1280,0.2440,0.4760"); + values ("0.2043,0.2199,0.2316,0.2629,0.3059,0.4113,0.6066",\ +"0.1887,0.2043,0.2160,0.2473,0.2941,0.3957,0.5949",\ +"0.1691,0.1848,0.2004,0.2316,0.2785,0.3801,0.5754",\ +"0.1379,0.1574,0.1691,0.2004,0.2473,0.3527,0.5480",\ +"0.0910,0.1066,0.1223,0.1535,0.2004,0.2980,0.4973",\ +"-0.0105,0.0051,0.0207,0.0520,0.0949,0.2004,0.3957",\ +"-0.2059,-0.1902,-0.1746,-0.1473,-0.1004,0.0051,0.2004"); + } + + fall_constraint("SIG2SRAM_constraint_template") { + index_1("0.0056,0.0232,0.0400,0.0728,0.1280,0.2440,0.4760"); + index_2("0.0056,0.0232,0.0400,0.0728,0.1280,0.2440,0.4760"); + values ("0.2941,0.3098,0.3215,0.3488,0.4035,0.4973,0.6887",\ +"0.2785,0.2941,0.3059,0.3332,0.3840,0.4816,0.6691",\ +"0.2629,0.2785,0.2902,0.3176,0.3684,0.4660,0.6535",\ +"0.2316,0.2473,0.2590,0.2863,0.3410,0.4348,0.6262",\ +"0.1848,0.2004,0.2121,0.2395,0.2902,0.3879,0.5754",\ +"0.0832,0.0988,0.1105,0.1379,0.1809,0.2746,0.4699",\ +"-0.1121,-0.0965,-0.0848,-0.0535,-0.0066,0.0910,0.2824"); + } + } + + + timing() { + timing_type : hold_rising; + related_pin : "A_CLK"; + when : "A_MEN" + sdf_cond : "A_MEN" + + rise_constraint("SIG2SRAM_constraint_template") { + index_1("0.0056,0.0232,0.0400,0.0728,0.1280,0.2440,0.4760"); + index_2("0.0056,0.0232,0.0400,0.0728,0.1280,0.2440,0.4760"); + values ("0.2473,0.2316,0.2160,0.1887,0.1379,0.0363,-0.1629",\ +"0.2629,0.2473,0.2316,0.2043,0.1535,0.0520,-0.1473",\ +"0.2785,0.2590,0.2434,0.2160,0.1652,0.0676,-0.1355",\ +"0.3098,0.2941,0.2785,0.2473,0.1965,0.0910,-0.1043",\ +"0.3527,0.3371,0.3215,0.2941,0.2434,0.1418,-0.0574",\ +"0.4582,0.4426,0.4270,0.3957,0.3488,0.2434,0.0480",\ +"0.6535,0.6379,0.6184,0.5910,0.5402,0.4426,0.2434"); + } + + fall_constraint("SIG2SRAM_constraint_template") { + index_1("0.0056,0.0232,0.0400,0.0728,0.1280,0.2440,0.4760"); + index_2("0.0056,0.0232,0.0400,0.0728,0.1280,0.2440,0.4760"); + values ("0.2395,0.2238,0.2121,0.1809,0.1301,0.0324,-0.1551",\ +"0.2551,0.2395,0.2277,0.1965,0.1457,0.0480,-0.1395",\ +"0.2668,0.2551,0.2395,0.2082,0.1574,0.0637,-0.1277",\ +"0.3020,0.2863,0.2707,0.2395,0.1887,0.0910,-0.0965",\ +"0.3449,0.3293,0.3176,0.2863,0.2355,0.1379,-0.0496",\ +"0.4504,0.4348,0.4191,0.3879,0.3371,0.2395,0.0559",\ +"0.6457,0.6301,0.6145,0.5871,0.5324,0.4309,0.2512"); + } + } + } +pin(A_REN) { + direction : input ; + capacitance : 0.00381634 ; + max_transition : "0.476" ; + related_power_pin : VDD; + related_ground_pin : VSS; + internal_power() { + when : "A_MEN"; + rise_power("scalar"){ + values (0.0061); + } + fall_power("scalar"){ + values (0.0020); + } + } + internal_power() { + when : "!A_MEN"; + rise_power("scalar"){ + values (0.0062); + } + fall_power("scalar"){ + values (0.0025); + } + } + timing() { + timing_type : setup_rising; + related_pin : "A_CLK"; + when : "A_MEN" + sdf_cond : "A_MEN" + + rise_constraint("SIG2SRAM_constraint_template") { + index_1("0.0056,0.0232,0.0400,0.0728,0.1280,0.2440,0.4760"); + index_2("0.0056,0.0232,0.0400,0.0728,0.1280,0.2440,0.4760"); + values ("-0.0301,-0.0145,0.0012,0.0324,0.0793,0.1809,0.3762",\ +"-0.0457,-0.0301,-0.0145,0.0168,0.0637,0.1613,0.3605",\ +"-0.0574,-0.0418,-0.0262,0.0051,0.0520,0.1496,0.3449",\ +"-0.0926,-0.0730,-0.0574,-0.0262,0.0207,0.1184,0.3137",\ +"-0.1395,-0.1238,-0.1082,-0.0770,-0.0301,0.0715,0.2707",\ +"-0.2410,-0.2254,-0.2098,-0.1746,-0.1355,-0.0340,0.1652",\ +"-0.4402,-0.4207,-0.4051,-0.3738,-0.3270,-0.2293,-0.0340"); + } + + fall_constraint("SIG2SRAM_constraint_template") { + index_1("0.0056,0.0232,0.0400,0.0728,0.1280,0.2440,0.4760"); + index_2("0.0056,0.0232,0.0400,0.0728,0.1280,0.2440,0.4760"); + values ("0.0988,0.1145,0.1262,0.1535,0.2043,0.3020,0.4855",\ +"0.0832,0.0988,0.1105,0.1418,0.1848,0.2824,0.4738",\ +"0.0676,0.0832,0.0949,0.1262,0.1730,0.2668,0.4621",\ +"0.0402,0.0559,0.0676,0.0988,0.1457,0.2434,0.4191",\ +"-0.0105,0.0012,0.0168,0.0480,0.0988,0.1965,0.3840",\ +"-0.1160,-0.0965,-0.0848,-0.0535,-0.0066,0.0988,0.2824",\ +"-0.3113,-0.2957,-0.2801,-0.2527,-0.2059,-0.1043,0.0832"); + } + } + + + timing() { + timing_type : hold_rising; + related_pin : "A_CLK"; + when : "A_MEN" + sdf_cond : "A_MEN" + + rise_constraint("SIG2SRAM_constraint_template") { + index_1("0.0056,0.0232,0.0400,0.0728,0.1280,0.2440,0.4760"); + index_2("0.0056,0.0232,0.0400,0.0728,0.1280,0.2440,0.4760"); + values ("0.2707,0.2551,0.2395,0.2121,0.1613,0.0598,-0.1395",\ +"0.2863,0.2707,0.2551,0.2238,0.1730,0.0715,-0.1238",\ +"0.2980,0.2824,0.2668,0.2395,0.1887,0.0871,-0.1121",\ +"0.3332,0.3176,0.3020,0.2707,0.2199,0.1184,-0.0809",\ +"0.3762,0.3605,0.3449,0.3176,0.2668,0.1613,-0.0340",\ +"0.4816,0.4621,0.4504,0.4191,0.3723,0.2629,0.0715",\ +"0.6770,0.6613,0.6418,0.6184,0.5637,0.4699,0.2629"); + } + + fall_constraint("SIG2SRAM_constraint_template") { + index_1("0.0056,0.0232,0.0400,0.0728,0.1280,0.2440,0.4760"); + index_2("0.0056,0.0232,0.0400,0.0728,0.1280,0.2440,0.4760"); + values ("0.2590,0.2434,0.2316,0.2004,0.1457,0.0520,-0.1355",\ +"0.2746,0.2590,0.2434,0.2160,0.1613,0.0676,-0.1199",\ +"0.2863,0.2707,0.2590,0.2277,0.1730,0.0832,-0.1082",\ +"0.3215,0.3059,0.2902,0.2590,0.2082,0.1105,-0.0770",\ +"0.3645,0.3488,0.3332,0.3059,0.2551,0.1535,-0.0340",\ +"0.4699,0.4543,0.4387,0.4074,0.3605,0.2551,0.0715",\ +"0.6652,0.6496,0.6340,0.6027,0.5520,0.4621,0.2707"); + } + } + } +pin(A_MEN) { + direction : input ; + capacitance : 0.00309605 ; + max_transition : "0.476" ; + related_power_pin : VDD; + related_ground_pin : VSS; + internal_power() { + rise_power("scalar"){ + values (0.0447); + } + fall_power("scalar"){ + values (0.0052); + } + } + timing() { + timing_type : setup_rising; + related_pin : "A_CLK"; + + rise_constraint("SIG2SRAM_constraint_template") { + index_1("0.0056,0.0232,0.0400,0.0728,0.1280,0.2440,0.4760"); + index_2("0.0056,0.0232,0.0400,0.0728,0.1280,0.2440,0.4760"); + values ("0.2043,0.2199,0.2316,0.2668,0.3098,0.4152,0.6066",\ +"0.1887,0.2043,0.2199,0.2512,0.2941,0.3996,0.5949",\ +"0.1730,0.1887,0.2043,0.2355,0.2824,0.3840,0.5793",\ +"0.1418,0.1574,0.1730,0.2043,0.2512,0.3566,0.5480",\ +"0.0949,0.1105,0.1262,0.1574,0.2043,0.3020,0.5051",\ +"-0.0066,0.0090,0.0246,0.0520,0.0988,0.2043,0.3996",\ +"-0.2020,-0.1863,-0.1746,-0.1434,-0.0965,0.0090,0.2082"); + } + + fall_constraint("SIG2SRAM_constraint_template") { + index_1("0.0056,0.0232,0.0400,0.0728,0.1280,0.2440,0.4760"); + index_2("0.0056,0.0232,0.0400,0.0728,0.1280,0.2440,0.4760"); + values ("0.2980,0.3137,0.3254,0.3527,0.4035,0.5012,0.6887",\ +"0.2824,0.2980,0.3098,0.3371,0.3879,0.4855,0.6730",\ +"0.2668,0.2824,0.2941,0.3215,0.3723,0.4699,0.6574",\ +"0.2355,0.2473,0.2629,0.2902,0.3410,0.4387,0.6262",\ +"0.1887,0.2004,0.2160,0.2395,0.2941,0.3918,0.5793",\ +"0.0871,0.1027,0.1145,0.1418,0.1848,0.2746,0.4816",\ +"-0.1082,-0.0965,-0.0809,-0.0496,-0.0027,0.0949,0.2863"); + } + } + + + timing() { + timing_type : hold_rising; + related_pin : "A_CLK"; + + rise_constraint("SIG2SRAM_constraint_template") { + index_1("0.0056,0.0232,0.0400,0.0728,0.1280,0.2440,0.4760"); + index_2("0.0056,0.0232,0.0400,0.0728,0.1280,0.2440,0.4760"); + values ("0.2512,0.2355,0.2199,0.1926,0.1418,0.0402,-0.1590",\ +"0.2668,0.2512,0.2355,0.2082,0.1574,0.0559,-0.1434",\ +"0.2824,0.2629,0.2512,0.2199,0.1691,0.0715,-0.1316",\ +"0.3137,0.2980,0.2824,0.2512,0.2004,0.0988,-0.0965",\ +"0.3566,0.3410,0.3254,0.2980,0.2473,0.1418,-0.0535",\ +"0.4621,0.4426,0.4309,0.3996,0.3527,0.2473,0.0520",\ +"0.6574,0.6418,0.6262,0.5949,0.5441,0.4465,0.2473"); + } + + fall_constraint("SIG2SRAM_constraint_template") { + index_1("0.0056,0.0232,0.0400,0.0728,0.1280,0.2440,0.4760"); + index_2("0.0056,0.0232,0.0400,0.0728,0.1280,0.2440,0.4760"); + values ("0.2395,0.2238,0.2121,0.1809,0.1301,0.0324,-0.1551",\ +"0.2551,0.2434,0.2277,0.1965,0.1457,0.0480,-0.1395",\ +"0.2707,0.2551,0.2395,0.2082,0.1574,0.0637,-0.1277",\ +"0.3020,0.2863,0.2707,0.2434,0.1926,0.0910,-0.0965",\ +"0.3449,0.3332,0.3176,0.2863,0.2355,0.1379,-0.0496",\ +"0.4504,0.4348,0.4230,0.3918,0.3410,0.2434,0.0559",\ +"0.6457,0.6301,0.6145,0.5910,0.5324,0.4387,0.2512"); + } + } + } +bus(A_BM) { + bus_type : D_15_0; + direction : input ; + capacitance : 0.00285703 ; + max_transition : "0.476" ; + pin(A_BM[15:0]) { + related_power_pin : VDD; + related_ground_pin : VSS; + internal_power() { + when : "A_MEN"; + rise_power("scalar"){ + values (0.0591); + } + fall_power("scalar"){ + values (0.0246); + } + } + internal_power() { + when : "!A_MEN"; + rise_power("scalar"){ + values (0.0602); + } + fall_power("scalar"){ + values (0.0244); + } + } + } + timing() { + timing_type : setup_rising; + related_pin : "A_CLK"; + when : "(A_WEN & A_MEN)" + sdf_cond : "A_RW_ACCESS" + + rise_constraint("SIG2SRAM_constraint_template") { + index_1("0.0056,0.0232,0.0400,0.0728,0.1280,0.2440,0.4760"); + index_2("0.0056,0.0232,0.0400,0.0728,0.1280,0.2440,0.4760"); + values ("-0.3412,-0.3246,-0.3119,-0.2797,-0.2328,-0.1283,0.0641",\ +"-0.3462,-0.3296,-0.3169,-0.2847,-0.2378,-0.1333,0.0591",\ +"-0.3507,-0.3341,-0.3214,-0.2892,-0.2423,-0.1378,0.0546",\ +"-0.3598,-0.3432,-0.3305,-0.2983,-0.2514,-0.1469,0.0455",\ +"-0.3670,-0.3504,-0.3377,-0.3055,-0.2586,-0.1541,0.0383",\ +"-0.3967,-0.3801,-0.3674,-0.3352,-0.2883,-0.1838,0.0086",\ +"-0.4547,-0.4381,-0.4254,-0.3932,-0.3463,-0.2418,-0.0495"); + } + + fall_constraint("SIG2SRAM_constraint_template") { + index_1("0.0056,0.0232,0.0400,0.0728,0.1280,0.2440,0.4760"); + index_2("0.0056,0.0232,0.0400,0.0728,0.1280,0.2440,0.4760"); + values ("-0.3090,-0.2934,-0.2807,-0.2523,-0.2016,-0.1029,0.0758",\ +"-0.3140,-0.2984,-0.2857,-0.2573,-0.2066,-0.1079,0.0708",\ +"-0.3185,-0.3028,-0.2901,-0.2618,-0.2110,-0.1124,0.0663",\ +"-0.3276,-0.3120,-0.2993,-0.2709,-0.2202,-0.1215,0.0572",\ +"-0.3348,-0.3192,-0.3065,-0.2782,-0.2274,-0.1287,0.0500",\ +"-0.3644,-0.3488,-0.3361,-0.3078,-0.2570,-0.1584,0.0203",\ +"-0.4225,-0.4069,-0.3942,-0.3659,-0.3151,-0.2165,-0.0377"); + } + } + + + timing() { + timing_type : hold_rising; + related_pin : "A_CLK"; + when : "(A_WEN & A_MEN)" + sdf_cond : "A_RW_ACCESS" + + rise_constraint("SIG2SRAM_constraint_template") { + index_1("0.0056,0.0232,0.0400,0.0728,0.1280,0.2440,0.4760"); + index_2("0.0056,0.0232,0.0400,0.0728,0.1280,0.2440,0.4760"); + values ("0.4501,0.4345,0.4218,0.3896,0.3408,0.2421,0.0458",\ +"0.4551,0.4395,0.4268,0.3946,0.3458,0.2471,0.0508",\ +"0.4596,0.4440,0.4313,0.3991,0.3502,0.2516,0.0553",\ +"0.4687,0.4531,0.4404,0.4082,0.3594,0.2607,0.0644",\ +"0.4759,0.4603,0.4476,0.4154,0.3666,0.2679,0.0716",\ +"0.5056,0.4900,0.4773,0.4451,0.3962,0.2976,0.1013",\ +"0.5637,0.5480,0.5353,0.5031,0.4543,0.3556,0.1594"); + } + + fall_constraint("SIG2SRAM_constraint_template") { + index_1("0.0056,0.0232,0.0400,0.0728,0.1280,0.2440,0.4760"); + index_2("0.0056,0.0232,0.0400,0.0728,0.1280,0.2440,0.4760"); + values ("0.4101,0.3954,0.3818,0.3534,0.3027,0.2099,0.0214",\ +"0.4151,0.4004,0.3868,0.3585,0.3077,0.2149,0.0264",\ +"0.4196,0.4049,0.3912,0.3629,0.3121,0.2194,0.0309",\ +"0.4287,0.4140,0.4004,0.3720,0.3213,0.2285,0.0400",\ +"0.4359,0.4212,0.4076,0.3792,0.3285,0.2357,0.0472",\ +"0.4656,0.4509,0.4372,0.4089,0.3581,0.2654,0.0769",\ +"0.5236,0.5090,0.4953,0.4670,0.4162,0.3234,0.1349"); + } + } +} + pin(A_CLK) { + direction : input; + capacitance : 0.00380014; + max_transition : "0.476"; + clock : "true" ; + pin_func_type : active_rising ; + + timing () { + timing_type : "min_pulse_width"; + related_pin : "A_CLK"; + rise_constraint("CLKTRAN_constraint_template") { + index_1("0.0056,0.476"); + values("0.21,0.21"); + } + } + + related_power_pin : VDD; + related_ground_pin : VSS; + + internal_power() { + when : "!A_MEN & !A_WEN & !A_REN"; + rise_power("scalar"){ + values (0); + } + fall_power("scalar"){ + values (0); + } + } + internal_power() { + when : "!A_MEN & A_WEN & !A_REN"; + rise_power("scalar"){ + values (0.4920); + } + fall_power("scalar"){ + values (0); + } + } + internal_power() { + when : "A_MEN & A_WEN & !A_REN"; + rise_power("scalar"){ + values (18.4562); + } + fall_power("scalar"){ + values (0); + } + } + internal_power() { + when : "A_MEN & A_WEN & A_REN"; + rise_power("scalar"){ + values (20.3138); + } + fall_power("scalar"){ + values (0); + } + } + internal_power() { + when : "A_MEN & !A_WEN & A_REN"; + rise_power("scalar"){ + values (14.1920); + } + fall_power("scalar"){ + values (0); + } + } + internal_power() { + when : "!A_MEN & !A_WEN & A_REN"; + rise_power("scalar"){ + values (0.2984); + } + fall_power("scalar"){ + values (0); + } + } + internal_power() { + when : "!A_MEN & A_WEN & A_REN"; + rise_power("scalar"){ + values (0.7334); + } + fall_power("scalar"){ + values (0); + } + } + internal_power() { + when : "A_MEN & !A_WEN & !A_REN"; + rise_power("scalar"){ + values (0); + } + fall_power("scalar"){ + values (0); + } + } + } + bus(A_DIN) { + bus_type : D_15_0; + direction : input ; + capacitance : 0.00365723 ; + memory_write() { + address : A_ADDR ; + clocked_on : A_CLK; + } + + max_transition : "0.476" ; + pin(A_DIN[15:0]) { + related_power_pin : VDD; + related_ground_pin : VSS; + internal_power() { + when : "A_MEN"; + rise_power("scalar"){ + values (0.0591); + } + fall_power("scalar"){ + values (0.0246); + } + } + internal_power() { + when : "!A_MEN"; + rise_power("scalar"){ + values (0.0602); + } + fall_power("scalar"){ + values (0.0244); + } + } + } + timing() { + timing_type : setup_rising; + related_pin : "A_CLK"; + when : "(A_WEN & A_MEN)"; + sdf_cond : "A_W_ACCESS"; + + rise_constraint("SIG2SRAM_constraint_template") { + index_1("0.0056,0.0232,0.0400,0.0728,0.1280,0.2440,0.4760"); + index_2("0.0056,0.0232,0.0400,0.0728,0.1280,0.2440,0.4760"); + values ("-0.3412,-0.3246,-0.3119,-0.2797,-0.2328,-0.1283,0.0641",\ +"-0.3462,-0.3296,-0.3169,-0.2847,-0.2378,-0.1333,0.0591",\ +"-0.3507,-0.3341,-0.3214,-0.2892,-0.2423,-0.1378,0.0546",\ +"-0.3598,-0.3432,-0.3305,-0.2983,-0.2514,-0.1469,0.0455",\ +"-0.3670,-0.3504,-0.3377,-0.3055,-0.2586,-0.1541,0.0383",\ +"-0.3967,-0.3801,-0.3674,-0.3352,-0.2883,-0.1838,0.0086",\ +"-0.4547,-0.4381,-0.4254,-0.3932,-0.3463,-0.2418,-0.0495"); + } + + fall_constraint("SIG2SRAM_constraint_template") { + index_1("0.0056,0.0232,0.0400,0.0728,0.1280,0.2440,0.4760"); + index_2("0.0056,0.0232,0.0400,0.0728,0.1280,0.2440,0.4760"); + values ("-0.3090,-0.2934,-0.2807,-0.2523,-0.2016,-0.1029,0.0758",\ +"-0.3140,-0.2984,-0.2857,-0.2573,-0.2066,-0.1079,0.0708",\ +"-0.3185,-0.3028,-0.2901,-0.2618,-0.2110,-0.1124,0.0663",\ +"-0.3276,-0.3120,-0.2993,-0.2709,-0.2202,-0.1215,0.0572",\ +"-0.3348,-0.3192,-0.3065,-0.2782,-0.2274,-0.1287,0.0500",\ +"-0.3644,-0.3488,-0.3361,-0.3078,-0.2570,-0.1584,0.0203",\ +"-0.4225,-0.4069,-0.3942,-0.3659,-0.3151,-0.2165,-0.0377"); + } + } + + timing() { + timing_type : hold_rising; + related_pin : "A_CLK"; + when : "(A_WEN & A_MEN)"; + sdf_cond : "A_W_ACCESS"; + + rise_constraint("SIG2SRAM_constraint_template") { + index_1("0.0056,0.0232,0.0400,0.0728,0.1280,0.2440,0.4760"); + index_2("0.0056,0.0232,0.0400,0.0728,0.1280,0.2440,0.4760"); + values ("0.4501,0.4345,0.4218,0.3896,0.3408,0.2421,0.0458",\ +"0.4551,0.4395,0.4268,0.3946,0.3458,0.2471,0.0508",\ +"0.4596,0.4440,0.4313,0.3991,0.3502,0.2516,0.0553",\ +"0.4687,0.4531,0.4404,0.4082,0.3594,0.2607,0.0644",\ +"0.4759,0.4603,0.4476,0.4154,0.3666,0.2679,0.0716",\ +"0.5056,0.4900,0.4773,0.4451,0.3962,0.2976,0.1013",\ +"0.5637,0.5480,0.5353,0.5031,0.4543,0.3556,0.1594"); + } + + fall_constraint("SIG2SRAM_constraint_template") { + index_1("0.0056,0.0232,0.0400,0.0728,0.1280,0.2440,0.4760"); + index_2("0.0056,0.0232,0.0400,0.0728,0.1280,0.2440,0.4760"); + values ("0.4101,0.3954,0.3818,0.3534,0.3027,0.2099,0.0214",\ +"0.4151,0.4004,0.3868,0.3585,0.3077,0.2149,0.0264",\ +"0.4196,0.4049,0.3912,0.3629,0.3121,0.2194,0.0309",\ +"0.4287,0.4140,0.4004,0.3720,0.3213,0.2285,0.0400",\ +"0.4359,0.4212,0.4076,0.3792,0.3285,0.2357,0.0472",\ +"0.4656,0.4509,0.4372,0.4089,0.3581,0.2654,0.0769",\ +"0.5236,0.5090,0.4953,0.4670,0.4162,0.3234,0.1349"); + } + } + } + + pin(A_BIST_EN) { + direction : input ; + capacitance : 0.00401111 ; + max_transition : "1" ; + related_power_pin : VDD; + related_ground_pin : VSS; + internal_power() { + rise_power("scalar") { + values (0); + } + fall_power("scalar") { + values (0); + } + } + } + +bus(A_BIST_ADDR) { + bus_type : A_7_0; + direction : input ; + capacitance : 0.00721489 ; + pin(A_BIST_ADDR[0]) { + capacitance : 0.00593979 ; + } + pin(A_BIST_ADDR[1]) { + capacitance : 0.00483009 ; + } + pin(A_BIST_ADDR[2]) { + capacitance : 0.006215 ; + } + pin(A_BIST_ADDR[3]) { + capacitance : 0.00766726 ; + } + pin(A_BIST_ADDR[4]) { + capacitance : 0.00488951 ; + } + pin(A_BIST_ADDR[5]) { + capacitance : 0.0091523 ; + } + pin(A_BIST_ADDR[6]) { + capacitance : 0.0109212 ; + } + max_transition : "0.476" ; + pin(A_BIST_ADDR[7:0]) { + related_power_pin : VDD; + related_ground_pin : VSS; + internal_power() { + when : "A_BIST_MEN"; + rise_power("scalar"){ + values (0.0109); + } + fall_power("scalar"){ + values (0.0051); + } + } + internal_power() { + when : "!A_BIST_MEN"; + rise_power("scalar"){ + values (0.0190); + } + fall_power("scalar"){ + values (0.0000); + } + } + } + timing() { + timing_type : setup_rising; + related_pin : "A_BIST_CLK"; + when : "((A_BIST_WEN | A_BIST_REN)& A_BIST_MEN)" + sdf_cond : "A_BIST_RW_ACCESS" + + rise_constraint("SIG2SRAM_constraint_template") { + index_1("0.0056,0.0232,0.0400,0.0728,0.1280,0.2440,0.4760"); + index_2("0.0056,0.0232,0.0400,0.0728,0.1280,0.2440,0.4760"); + values ("-0.4168,-0.3973,-0.3855,-0.3543,-0.3074,-0.2020,-0.0027",\ +"-0.4324,-0.4129,-0.4012,-0.3699,-0.3191,-0.2176,-0.0184",\ +"-0.4441,-0.4285,-0.4129,-0.3816,-0.3309,-0.2293,-0.0301",\ +"-0.4793,-0.4598,-0.4441,-0.4129,-0.3660,-0.2645,-0.0652",\ +"-0.5223,-0.5066,-0.4910,-0.4598,-0.4129,-0.3074,-0.1121",\ +"-0.6199,-0.6082,-0.5926,-0.5613,-0.5145,-0.4129,-0.2137",\ +"-0.8191,-0.8074,-0.7840,-0.7566,-0.7098,-0.6082,-0.4051"); + } + + fall_constraint("SIG2SRAM_constraint_template") { + index_1("0.0056,0.0232,0.0400,0.0728,0.1280,0.2440,0.4760"); + index_2("0.0056,0.0232,0.0400,0.0728,0.1280,0.2440,0.4760"); + values ("-0.3309,-0.3113,-0.2996,-0.2684,-0.2176,-0.1238,0.0637",\ +"-0.3465,-0.3309,-0.3152,-0.2840,-0.2332,-0.1395,0.0480",\ +"-0.3582,-0.3426,-0.3270,-0.2996,-0.2488,-0.1512,0.0324",\ +"-0.3895,-0.3738,-0.3582,-0.3309,-0.2801,-0.1863,0.0051",\ +"-0.4363,-0.4207,-0.4051,-0.3777,-0.3230,-0.2293,-0.0379",\ +"-0.5379,-0.5223,-0.5066,-0.4793,-0.4285,-0.3309,-0.1434",\ +"-0.7332,-0.7176,-0.7020,-0.6746,-0.6238,-0.5262,-0.3387"); + } + } + + + timing() { + timing_type : hold_rising; + related_pin : "A_BIST_CLK"; + when : "((A_BIST_WEN | A_BIST_REN)& A_BIST_MEN)" + sdf_cond : "A_BIST_RW_ACCESS" + + rise_constraint("SIG2SRAM_constraint_template") { + index_1("0.0056,0.0232,0.0400,0.0728,0.1280,0.2440,0.4760"); + index_2("0.0056,0.0232,0.0400,0.0728,0.1280,0.2440,0.4760"); + values ("0.5246,0.5051,0.4895,0.4582,0.4113,0.3059,0.1066",\ +"0.5402,0.5207,0.5051,0.4777,0.4270,0.3215,0.1223",\ +"0.5520,0.5324,0.5168,0.4895,0.4387,0.3371,0.1340",\ +"0.5832,0.5676,0.5520,0.5207,0.4738,0.3684,0.1691",\ +"0.6301,0.6105,0.5949,0.5676,0.5168,0.4113,0.2160",\ +"0.7316,0.7121,0.7004,0.6691,0.6223,0.5168,0.3176",\ +"0.9270,0.9230,0.8957,0.8645,0.8137,0.7121,0.5168"); + } + + fall_constraint("SIG2SRAM_constraint_template") { + index_1("0.0056,0.0232,0.0400,0.0728,0.1280,0.2440,0.4760"); + index_2("0.0056,0.0232,0.0400,0.0728,0.1280,0.2440,0.4760"); + values ("0.4309,0.4152,0.4035,0.3684,0.3215,0.2277,0.0363",\ +"0.4465,0.4309,0.4152,0.3879,0.3371,0.2395,0.0559",\ +"0.4582,0.4426,0.4309,0.3996,0.3488,0.2551,0.0715",\ +"0.4934,0.4777,0.4621,0.4348,0.3840,0.2863,0.0988",\ +"0.5363,0.5207,0.5051,0.4777,0.4270,0.3332,0.1418",\ +"0.6379,0.6262,0.6105,0.5793,0.5324,0.4348,0.2434",\ +"0.8332,0.8215,0.8059,0.7707,0.7238,0.6301,0.4387"); + } + } +} +pin(A_BIST_WEN) { + direction : input ; + capacitance : 0.00324098 ; + max_transition : "0.476" ; + related_power_pin : VDD; + related_ground_pin : VSS; + internal_power() { + when : "A_BIST_MEN"; + rise_power("scalar"){ + values (0.0046); + } + fall_power("scalar"){ + values (0.0038); + } + } + internal_power() { + when : "!A_BIST_MEN"; + rise_power("scalar"){ + values (0.0042); + } + fall_power("scalar"){ + values (0.0039); + } + } + timing() { + timing_type : setup_rising; + related_pin : "A_BIST_CLK"; + when : "A_BIST_MEN" + sdf_cond : "A_BIST_MEN" + + rise_constraint("SIG2SRAM_constraint_template") { + index_1("0.0056,0.0232,0.0400,0.0728,0.1280,0.2440,0.4760"); + index_2("0.0056,0.0232,0.0400,0.0728,0.1280,0.2440,0.4760"); + values ("0.2043,0.2199,0.2316,0.2629,0.3059,0.4113,0.6066",\ +"0.1887,0.2043,0.2160,0.2473,0.2941,0.3957,0.5949",\ +"0.1691,0.1848,0.2004,0.2316,0.2785,0.3801,0.5754",\ +"0.1379,0.1574,0.1691,0.2004,0.2473,0.3527,0.5480",\ +"0.0910,0.1066,0.1223,0.1535,0.2004,0.2980,0.4973",\ +"-0.0105,0.0051,0.0207,0.0520,0.0949,0.2004,0.3957",\ +"-0.2059,-0.1902,-0.1746,-0.1473,-0.1004,0.0051,0.2004"); + } + + fall_constraint("SIG2SRAM_constraint_template") { + index_1("0.0056,0.0232,0.0400,0.0728,0.1280,0.2440,0.4760"); + index_2("0.0056,0.0232,0.0400,0.0728,0.1280,0.2440,0.4760"); + values ("0.2941,0.3098,0.3215,0.3488,0.4035,0.4973,0.6887",\ +"0.2785,0.2941,0.3059,0.3332,0.3840,0.4816,0.6691",\ +"0.2629,0.2785,0.2902,0.3176,0.3684,0.4660,0.6535",\ +"0.2316,0.2473,0.2590,0.2863,0.3410,0.4348,0.6262",\ +"0.1848,0.2004,0.2121,0.2395,0.2902,0.3879,0.5754",\ +"0.0832,0.0988,0.1105,0.1379,0.1809,0.2746,0.4699",\ +"-0.1121,-0.0965,-0.0848,-0.0535,-0.0066,0.0910,0.2824"); + } + } + + + timing() { + timing_type : hold_rising; + related_pin : "A_BIST_CLK"; + when : "A_BIST_MEN" + sdf_cond : "A_BIST_MEN" + + rise_constraint("SIG2SRAM_constraint_template") { + index_1("0.0056,0.0232,0.0400,0.0728,0.1280,0.2440,0.4760"); + index_2("0.0056,0.0232,0.0400,0.0728,0.1280,0.2440,0.4760"); + values ("0.2473,0.2316,0.2160,0.1887,0.1379,0.0363,-0.1629",\ +"0.2629,0.2473,0.2316,0.2043,0.1535,0.0520,-0.1473",\ +"0.2785,0.2590,0.2434,0.2160,0.1652,0.0676,-0.1355",\ +"0.3098,0.2941,0.2785,0.2473,0.1965,0.0910,-0.1043",\ +"0.3527,0.3371,0.3215,0.2941,0.2434,0.1418,-0.0574",\ +"0.4582,0.4426,0.4270,0.3957,0.3488,0.2434,0.0480",\ +"0.6535,0.6379,0.6184,0.5910,0.5402,0.4426,0.2434"); + } + + fall_constraint("SIG2SRAM_constraint_template") { + index_1("0.0056,0.0232,0.0400,0.0728,0.1280,0.2440,0.4760"); + index_2("0.0056,0.0232,0.0400,0.0728,0.1280,0.2440,0.4760"); + values ("0.2395,0.2238,0.2121,0.1809,0.1301,0.0324,-0.1551",\ +"0.2551,0.2395,0.2277,0.1965,0.1457,0.0480,-0.1395",\ +"0.2668,0.2551,0.2395,0.2082,0.1574,0.0637,-0.1277",\ +"0.3020,0.2863,0.2707,0.2395,0.1887,0.0910,-0.0965",\ +"0.3449,0.3293,0.3176,0.2863,0.2355,0.1379,-0.0496",\ +"0.4504,0.4348,0.4191,0.3879,0.3371,0.2395,0.0559",\ +"0.6457,0.6301,0.6145,0.5871,0.5324,0.4309,0.2512"); + } + } + } +pin(A_BIST_REN) { + direction : input ; + capacitance : 0.00381634 ; + max_transition : "0.476" ; + related_power_pin : VDD; + related_ground_pin : VSS; + internal_power() { + when : "A_BIST_MEN"; + rise_power("scalar"){ + values (0.0061); + } + fall_power("scalar"){ + values (0.0020); + } + } + internal_power() { + when : "!A_BIST_MEN"; + rise_power("scalar"){ + values (0.0062); + } + fall_power("scalar"){ + values (0.0025); + } + } + timing() { + timing_type : setup_rising; + related_pin : "A_BIST_CLK"; + when : "A_BIST_MEN" + sdf_cond : "A_BIST_MEN" + + rise_constraint("SIG2SRAM_constraint_template") { + index_1("0.0056,0.0232,0.0400,0.0728,0.1280,0.2440,0.4760"); + index_2("0.0056,0.0232,0.0400,0.0728,0.1280,0.2440,0.4760"); + values ("-0.0301,-0.0145,0.0012,0.0324,0.0793,0.1809,0.3762",\ +"-0.0457,-0.0301,-0.0145,0.0168,0.0637,0.1613,0.3605",\ +"-0.0574,-0.0418,-0.0262,0.0051,0.0520,0.1496,0.3449",\ +"-0.0926,-0.0730,-0.0574,-0.0262,0.0207,0.1184,0.3137",\ +"-0.1395,-0.1238,-0.1082,-0.0770,-0.0301,0.0715,0.2707",\ +"-0.2410,-0.2254,-0.2098,-0.1746,-0.1355,-0.0340,0.1652",\ +"-0.4402,-0.4207,-0.4051,-0.3738,-0.3270,-0.2293,-0.0340"); + } + + fall_constraint("SIG2SRAM_constraint_template") { + index_1("0.0056,0.0232,0.0400,0.0728,0.1280,0.2440,0.4760"); + index_2("0.0056,0.0232,0.0400,0.0728,0.1280,0.2440,0.4760"); + values ("0.0988,0.1145,0.1262,0.1535,0.2043,0.3020,0.4855",\ +"0.0832,0.0988,0.1105,0.1418,0.1848,0.2824,0.4738",\ +"0.0676,0.0832,0.0949,0.1262,0.1730,0.2668,0.4621",\ +"0.0402,0.0559,0.0676,0.0988,0.1457,0.2434,0.4191",\ +"-0.0105,0.0012,0.0168,0.0480,0.0988,0.1965,0.3840",\ +"-0.1160,-0.0965,-0.0848,-0.0535,-0.0066,0.0988,0.2824",\ +"-0.3113,-0.2957,-0.2801,-0.2527,-0.2059,-0.1043,0.0832"); + } + } + + + timing() { + timing_type : hold_rising; + related_pin : "A_BIST_CLK"; + when : "A_BIST_MEN" + sdf_cond : "A_BIST_MEN" + + rise_constraint("SIG2SRAM_constraint_template") { + index_1("0.0056,0.0232,0.0400,0.0728,0.1280,0.2440,0.4760"); + index_2("0.0056,0.0232,0.0400,0.0728,0.1280,0.2440,0.4760"); + values ("0.2707,0.2551,0.2395,0.2121,0.1613,0.0598,-0.1395",\ +"0.2863,0.2707,0.2551,0.2238,0.1730,0.0715,-0.1238",\ +"0.2980,0.2824,0.2668,0.2395,0.1887,0.0871,-0.1121",\ +"0.3332,0.3176,0.3020,0.2707,0.2199,0.1184,-0.0809",\ +"0.3762,0.3605,0.3449,0.3176,0.2668,0.1613,-0.0340",\ +"0.4816,0.4621,0.4504,0.4191,0.3723,0.2629,0.0715",\ +"0.6770,0.6613,0.6418,0.6184,0.5637,0.4699,0.2629"); + } + + fall_constraint("SIG2SRAM_constraint_template") { + index_1("0.0056,0.0232,0.0400,0.0728,0.1280,0.2440,0.4760"); + index_2("0.0056,0.0232,0.0400,0.0728,0.1280,0.2440,0.4760"); + values ("0.2590,0.2434,0.2316,0.2004,0.1457,0.0520,-0.1355",\ +"0.2746,0.2590,0.2434,0.2160,0.1613,0.0676,-0.1199",\ +"0.2863,0.2707,0.2590,0.2277,0.1730,0.0832,-0.1082",\ +"0.3215,0.3059,0.2902,0.2590,0.2082,0.1105,-0.0770",\ +"0.3645,0.3488,0.3332,0.3059,0.2551,0.1535,-0.0340",\ +"0.4699,0.4543,0.4387,0.4074,0.3605,0.2551,0.0715",\ +"0.6652,0.6496,0.6340,0.6027,0.5520,0.4621,0.2707"); + } + } + } +pin(A_BIST_MEN) { + direction : input ; + capacitance : 0.00309605 ; + max_transition : "0.476" ; + related_power_pin : VDD; + related_ground_pin : VSS; + internal_power() { + rise_power("scalar"){ + values (0.0447); + } + fall_power("scalar"){ + values (0.0052); + } + } + timing() { + timing_type : setup_rising; + related_pin : "A_BIST_CLK"; + + rise_constraint("SIG2SRAM_constraint_template") { + index_1("0.0056,0.0232,0.0400,0.0728,0.1280,0.2440,0.4760"); + index_2("0.0056,0.0232,0.0400,0.0728,0.1280,0.2440,0.4760"); + values ("0.2043,0.2199,0.2316,0.2668,0.3098,0.4152,0.6066",\ +"0.1887,0.2043,0.2199,0.2512,0.2941,0.3996,0.5949",\ +"0.1730,0.1887,0.2043,0.2355,0.2824,0.3840,0.5793",\ +"0.1418,0.1574,0.1730,0.2043,0.2512,0.3566,0.5480",\ +"0.0949,0.1105,0.1262,0.1574,0.2043,0.3020,0.5051",\ +"-0.0066,0.0090,0.0246,0.0520,0.0988,0.2043,0.3996",\ +"-0.2020,-0.1863,-0.1746,-0.1434,-0.0965,0.0090,0.2082"); + } + + fall_constraint("SIG2SRAM_constraint_template") { + index_1("0.0056,0.0232,0.0400,0.0728,0.1280,0.2440,0.4760"); + index_2("0.0056,0.0232,0.0400,0.0728,0.1280,0.2440,0.4760"); + values ("0.2980,0.3137,0.3254,0.3527,0.4035,0.5012,0.6887",\ +"0.2824,0.2980,0.3098,0.3371,0.3879,0.4855,0.6730",\ +"0.2668,0.2824,0.2941,0.3215,0.3723,0.4699,0.6574",\ +"0.2355,0.2473,0.2629,0.2902,0.3410,0.4387,0.6262",\ +"0.1887,0.2004,0.2160,0.2395,0.2941,0.3918,0.5793",\ +"0.0871,0.1027,0.1145,0.1418,0.1848,0.2746,0.4816",\ +"-0.1082,-0.0965,-0.0809,-0.0496,-0.0027,0.0949,0.2863"); + } + } + + + timing() { + timing_type : hold_rising; + related_pin : "A_BIST_CLK"; + + rise_constraint("SIG2SRAM_constraint_template") { + index_1("0.0056,0.0232,0.0400,0.0728,0.1280,0.2440,0.4760"); + index_2("0.0056,0.0232,0.0400,0.0728,0.1280,0.2440,0.4760"); + values ("0.2512,0.2355,0.2199,0.1926,0.1418,0.0402,-0.1590",\ +"0.2668,0.2512,0.2355,0.2082,0.1574,0.0559,-0.1434",\ +"0.2824,0.2629,0.2512,0.2199,0.1691,0.0715,-0.1316",\ +"0.3137,0.2980,0.2824,0.2512,0.2004,0.0988,-0.0965",\ +"0.3566,0.3410,0.3254,0.2980,0.2473,0.1418,-0.0535",\ +"0.4621,0.4426,0.4309,0.3996,0.3527,0.2473,0.0520",\ +"0.6574,0.6418,0.6262,0.5949,0.5441,0.4465,0.2473"); + } + + fall_constraint("SIG2SRAM_constraint_template") { + index_1("0.0056,0.0232,0.0400,0.0728,0.1280,0.2440,0.4760"); + index_2("0.0056,0.0232,0.0400,0.0728,0.1280,0.2440,0.4760"); + values ("0.2395,0.2238,0.2121,0.1809,0.1301,0.0324,-0.1551",\ +"0.2551,0.2434,0.2277,0.1965,0.1457,0.0480,-0.1395",\ +"0.2707,0.2551,0.2395,0.2082,0.1574,0.0637,-0.1277",\ +"0.3020,0.2863,0.2707,0.2434,0.1926,0.0910,-0.0965",\ +"0.3449,0.3332,0.3176,0.2863,0.2355,0.1379,-0.0496",\ +"0.4504,0.4348,0.4230,0.3918,0.3410,0.2434,0.0559",\ +"0.6457,0.6301,0.6145,0.5910,0.5324,0.4387,0.2512"); + } + } + } +bus(A_BIST_BM) { + bus_type : D_15_0; + direction : input ; + capacitance : 0.00238379 ; + max_transition : "0.476" ; + pin(A_BIST_BM[15:0]) { + related_power_pin : VDD; + related_ground_pin : VSS; + internal_power() { + when : "A_BIST_MEN"; + rise_power("scalar"){ + values (0.0591); + } + fall_power("scalar"){ + values (0.0246); + } + } + internal_power() { + when : "!A_BIST_MEN"; + rise_power("scalar"){ + values (0.0602); + } + fall_power("scalar"){ + values (0.0244); + } + } + } + timing() { + timing_type : setup_rising; + related_pin : "A_BIST_CLK"; + when : "(A_BIST_WEN & A_BIST_MEN)" + sdf_cond : "A_BIST_RW_ACCESS" + + rise_constraint("SIG2SRAM_constraint_template") { + index_1("0.0056,0.0232,0.0400,0.0728,0.1280,0.2440,0.4760"); + index_2("0.0056,0.0232,0.0400,0.0728,0.1280,0.2440,0.4760"); + values ("-0.3412,-0.3246,-0.3119,-0.2797,-0.2328,-0.1283,0.0641",\ +"-0.3462,-0.3296,-0.3169,-0.2847,-0.2378,-0.1333,0.0591",\ +"-0.3507,-0.3341,-0.3214,-0.2892,-0.2423,-0.1378,0.0546",\ +"-0.3598,-0.3432,-0.3305,-0.2983,-0.2514,-0.1469,0.0455",\ +"-0.3670,-0.3504,-0.3377,-0.3055,-0.2586,-0.1541,0.0383",\ +"-0.3967,-0.3801,-0.3674,-0.3352,-0.2883,-0.1838,0.0086",\ +"-0.4547,-0.4381,-0.4254,-0.3932,-0.3463,-0.2418,-0.0495"); + } + + fall_constraint("SIG2SRAM_constraint_template") { + index_1("0.0056,0.0232,0.0400,0.0728,0.1280,0.2440,0.4760"); + index_2("0.0056,0.0232,0.0400,0.0728,0.1280,0.2440,0.4760"); + values ("-0.3090,-0.2934,-0.2807,-0.2523,-0.2016,-0.1029,0.0758",\ +"-0.3140,-0.2984,-0.2857,-0.2573,-0.2066,-0.1079,0.0708",\ +"-0.3185,-0.3028,-0.2901,-0.2618,-0.2110,-0.1124,0.0663",\ +"-0.3276,-0.3120,-0.2993,-0.2709,-0.2202,-0.1215,0.0572",\ +"-0.3348,-0.3192,-0.3065,-0.2782,-0.2274,-0.1287,0.0500",\ +"-0.3644,-0.3488,-0.3361,-0.3078,-0.2570,-0.1584,0.0203",\ +"-0.4225,-0.4069,-0.3942,-0.3659,-0.3151,-0.2165,-0.0377"); + } + } + + + timing() { + timing_type : hold_rising; + related_pin : "A_BIST_CLK"; + when : "(A_BIST_WEN & A_BIST_MEN)" + sdf_cond : "A_BIST_RW_ACCESS" + + rise_constraint("SIG2SRAM_constraint_template") { + index_1("0.0056,0.0232,0.0400,0.0728,0.1280,0.2440,0.4760"); + index_2("0.0056,0.0232,0.0400,0.0728,0.1280,0.2440,0.4760"); + values ("0.4501,0.4345,0.4218,0.3896,0.3408,0.2421,0.0458",\ +"0.4551,0.4395,0.4268,0.3946,0.3458,0.2471,0.0508",\ +"0.4596,0.4440,0.4313,0.3991,0.3502,0.2516,0.0553",\ +"0.4687,0.4531,0.4404,0.4082,0.3594,0.2607,0.0644",\ +"0.4759,0.4603,0.4476,0.4154,0.3666,0.2679,0.0716",\ +"0.5056,0.4900,0.4773,0.4451,0.3962,0.2976,0.1013",\ +"0.5637,0.5480,0.5353,0.5031,0.4543,0.3556,0.1594"); + } + + fall_constraint("SIG2SRAM_constraint_template") { + index_1("0.0056,0.0232,0.0400,0.0728,0.1280,0.2440,0.4760"); + index_2("0.0056,0.0232,0.0400,0.0728,0.1280,0.2440,0.4760"); + values ("0.4101,0.3954,0.3818,0.3534,0.3027,0.2099,0.0214",\ +"0.4151,0.4004,0.3868,0.3585,0.3077,0.2149,0.0264",\ +"0.4196,0.4049,0.3912,0.3629,0.3121,0.2194,0.0309",\ +"0.4287,0.4140,0.4004,0.3720,0.3213,0.2285,0.0400",\ +"0.4359,0.4212,0.4076,0.3792,0.3285,0.2357,0.0472",\ +"0.4656,0.4509,0.4372,0.4089,0.3581,0.2654,0.0769",\ +"0.5236,0.5090,0.4953,0.4670,0.4162,0.3234,0.1349"); + } + } +} + pin(A_BIST_CLK) { + direction : input; + capacitance : 0.00380014; + max_transition : "0.476"; + clock : "true" ; + pin_func_type : active_rising ; + + timing () { + timing_type : "min_pulse_width"; + related_pin : "A_BIST_CLK"; + rise_constraint("CLKTRAN_constraint_template") { + index_1("0.0056,0.476"); + values("0.21,0.21"); + } + } + + related_power_pin : VDD; + related_ground_pin : VSS; + + internal_power() { + when : "!A_BIST_MEN & !A_BIST_WEN & !A_BIST_REN"; + rise_power("scalar"){ + values (0); + } + fall_power("scalar"){ + values (0); + } + } + internal_power() { + when : "!A_BIST_MEN & A_BIST_WEN & !A_BIST_REN"; + rise_power("scalar"){ + values (0.4920); + } + fall_power("scalar"){ + values (0); + } + } + internal_power() { + when : "A_BIST_MEN & A_BIST_WEN & !A_BIST_REN"; + rise_power("scalar"){ + values (18.4562); + } + fall_power("scalar"){ + values (0); + } + } + internal_power() { + when : "A_BIST_MEN & A_BIST_WEN & A_BIST_REN"; + rise_power("scalar"){ + values (20.3138); + } + fall_power("scalar"){ + values (0); + } + } + internal_power() { + when : "A_BIST_MEN & !A_BIST_WEN & A_BIST_REN"; + rise_power("scalar"){ + values (14.1920); + } + fall_power("scalar"){ + values (0); + } + } + internal_power() { + when : "!A_BIST_MEN & !A_BIST_WEN & A_BIST_REN"; + rise_power("scalar"){ + values (0.2984); + } + fall_power("scalar"){ + values (0); + } + } + internal_power() { + when : "!A_BIST_MEN & A_BIST_WEN & A_BIST_REN"; + rise_power("scalar"){ + values (0.7334); + } + fall_power("scalar"){ + values (0); + } + } + internal_power() { + when : "A_BIST_MEN & !A_BIST_WEN & !A_BIST_REN"; + rise_power("scalar"){ + values (0); + } + fall_power("scalar"){ + values (0); + } + } + } + bus(A_BIST_DIN) { + bus_type : D_15_0; + direction : input ; + capacitance : 0.00233858 ; + memory_write() { + address : A_BIST_ADDR ; + clocked_on : A_BIST_CLK; + } + + max_transition : "0.476" ; + pin(A_BIST_DIN[15:0]) { + related_power_pin : VDD; + related_ground_pin : VSS; + internal_power() { + when : "A_BIST_MEN"; + rise_power("scalar"){ + values (0.0591); + } + fall_power("scalar"){ + values (0.0246); + } + } + internal_power() { + when : "!A_BIST_MEN"; + rise_power("scalar"){ + values (0.0602); + } + fall_power("scalar"){ + values (0.0244); + } + } + } + timing() { + timing_type : setup_rising; + related_pin : "A_BIST_CLK"; + when : "(A_BIST_WEN & A_BIST_MEN)"; + sdf_cond : "A_BIST_W_ACCESS"; + + rise_constraint("SIG2SRAM_constraint_template") { + index_1("0.0056,0.0232,0.0400,0.0728,0.1280,0.2440,0.4760"); + index_2("0.0056,0.0232,0.0400,0.0728,0.1280,0.2440,0.4760"); + values ("-0.3412,-0.3246,-0.3119,-0.2797,-0.2328,-0.1283,0.0641",\ +"-0.3462,-0.3296,-0.3169,-0.2847,-0.2378,-0.1333,0.0591",\ +"-0.3507,-0.3341,-0.3214,-0.2892,-0.2423,-0.1378,0.0546",\ +"-0.3598,-0.3432,-0.3305,-0.2983,-0.2514,-0.1469,0.0455",\ +"-0.3670,-0.3504,-0.3377,-0.3055,-0.2586,-0.1541,0.0383",\ +"-0.3967,-0.3801,-0.3674,-0.3352,-0.2883,-0.1838,0.0086",\ +"-0.4547,-0.4381,-0.4254,-0.3932,-0.3463,-0.2418,-0.0495"); + } + + fall_constraint("SIG2SRAM_constraint_template") { + index_1("0.0056,0.0232,0.0400,0.0728,0.1280,0.2440,0.4760"); + index_2("0.0056,0.0232,0.0400,0.0728,0.1280,0.2440,0.4760"); + values ("-0.3090,-0.2934,-0.2807,-0.2523,-0.2016,-0.1029,0.0758",\ +"-0.3140,-0.2984,-0.2857,-0.2573,-0.2066,-0.1079,0.0708",\ +"-0.3185,-0.3028,-0.2901,-0.2618,-0.2110,-0.1124,0.0663",\ +"-0.3276,-0.3120,-0.2993,-0.2709,-0.2202,-0.1215,0.0572",\ +"-0.3348,-0.3192,-0.3065,-0.2782,-0.2274,-0.1287,0.0500",\ +"-0.3644,-0.3488,-0.3361,-0.3078,-0.2570,-0.1584,0.0203",\ +"-0.4225,-0.4069,-0.3942,-0.3659,-0.3151,-0.2165,-0.0377"); + } + } + + timing() { + timing_type : hold_rising; + related_pin : "A_BIST_CLK"; + when : "(A_BIST_WEN & A_BIST_MEN)"; + sdf_cond : "A_BIST_W_ACCESS"; + + rise_constraint("SIG2SRAM_constraint_template") { + index_1("0.0056,0.0232,0.0400,0.0728,0.1280,0.2440,0.4760"); + index_2("0.0056,0.0232,0.0400,0.0728,0.1280,0.2440,0.4760"); + values ("0.4501,0.4345,0.4218,0.3896,0.3408,0.2421,0.0458",\ +"0.4551,0.4395,0.4268,0.3946,0.3458,0.2471,0.0508",\ +"0.4596,0.4440,0.4313,0.3991,0.3502,0.2516,0.0553",\ +"0.4687,0.4531,0.4404,0.4082,0.3594,0.2607,0.0644",\ +"0.4759,0.4603,0.4476,0.4154,0.3666,0.2679,0.0716",\ +"0.5056,0.4900,0.4773,0.4451,0.3962,0.2976,0.1013",\ +"0.5637,0.5480,0.5353,0.5031,0.4543,0.3556,0.1594"); + } + + fall_constraint("SIG2SRAM_constraint_template") { + index_1("0.0056,0.0232,0.0400,0.0728,0.1280,0.2440,0.4760"); + index_2("0.0056,0.0232,0.0400,0.0728,0.1280,0.2440,0.4760"); + values ("0.4101,0.3954,0.3818,0.3534,0.3027,0.2099,0.0214",\ +"0.4151,0.4004,0.3868,0.3585,0.3077,0.2149,0.0264",\ +"0.4196,0.4049,0.3912,0.3629,0.3121,0.2194,0.0309",\ +"0.4287,0.4140,0.4004,0.3720,0.3213,0.2285,0.0400",\ +"0.4359,0.4212,0.4076,0.3792,0.3285,0.2357,0.0472",\ +"0.4656,0.4509,0.4372,0.4089,0.3581,0.2654,0.0769",\ +"0.5236,0.5090,0.4953,0.4670,0.4162,0.3234,0.1349"); + } + } + } + +bus(A_DOUT) { + + bus_type : D_15_0; + direction : output ; + capacitance : 0 ; + max_capacitance : 0.064 ; + memory_read() { + address : A_ADDR ; + } + pin(A_DOUT[15:0]) { + related_power_pin : VDD; + related_ground_pin : VSS; + internal_power() { + rise_power("scalar") { + values (0); + } + fall_power("scalar") { + values (0); + } + } + } + timing() { + related_pin : "A_CLK"; + timing_type : rising_edge ; + timing_sense : non_unate ; + + cell_rise(SIG2SRAM_delay_template) { + index_1("0.0056,0.0232,0.0400,0.0728,0.1280,0.2440,0.4760"); + index_2("0.0008,0.0014,0.0051,0.0100,0.0339,0.0640"); + values ("2.9759,2.9775,2.9851,2.9938,3.0263,3.0621",\ +"2.9822,2.9838,2.9915,3.0002,3.0326,3.0685",\ +"2.9843,2.9859,2.9936,3.0023,3.0347,3.0706",\ +"2.9974,2.9990,3.0066,3.0153,3.0478,3.0836",\ +"3.0036,3.0052,3.0128,3.0215,3.0540,3.0898",\ +"3.0350,3.0366,3.0443,3.0530,3.0854,3.1213",\ +"3.0895,3.0911,3.0988,3.1075,3.1399,3.1758"); + } + cell_fall(SIG2SRAM_delay_template) { + index_1("0.0056,0.0232,0.0400,0.0728,0.1280,0.2440,0.4760"); + index_2("0.0008,0.0014,0.0051,0.0100,0.0339,0.0640"); + values ("2.9148,2.9161,2.9221,2.9293,2.9558,2.9824",\ +"2.9211,2.9225,2.9285,2.9356,2.9621,2.9887",\ +"2.9232,2.9246,2.9306,2.9377,2.9642,2.9908",\ +"2.9363,2.9376,2.9436,2.9508,2.9773,3.0039",\ +"2.9425,2.9438,2.9498,2.9570,2.9835,3.0101",\ +"2.9739,2.9753,2.9813,2.9884,3.0149,3.0416",\ +"3.0285,3.0298,3.0358,3.0429,3.0694,3.0961"); + } + + rise_transition(SRAM_load_template) { + index_1("0.0008,0.0014,0.0051,0.0100,0.0339,0.0640"); + values ("0.0326,0.0341,0.0428,0.0518,0.0923,0.1492"); + } + fall_transition(SRAM_load_template) { + index_1("0.0008,0.0014,0.0051,0.0100,0.0339,0.0640"); + values ("0.0254,0.0265,0.0335,0.0402,0.0707,0.1039"); + } + } +} +cell_leakage_power : 49.5039; +} +} diff --git a/flow/platforms/ihp-sg13g2/lib/RM_IHPSG13_1P_256x32_c2_bm_bist_fast_1p32V_m55C.lib b/flow/platforms/ihp-sg13g2/lib/RM_IHPSG13_1P_256x32_c2_bm_bist_fast_1p32V_m55C.lib new file mode 100644 index 0000000000..457e85a6c6 --- /dev/null +++ b/flow/platforms/ihp-sg13g2/lib/RM_IHPSG13_1P_256x32_c2_bm_bist_fast_1p32V_m55C.lib @@ -0,0 +1,1513 @@ +/* ------------------------------------------------------*/ +/**/ +/* Copyright 2025 IHP PDK Authors*/ +/**/ +/* Licensed under the Apache License, Version 2.0 (the "License");*/ +/* you may not use this file except in compliance with the License.*/ +/* You may obtain a copy of the License at*/ +/* */ +/* https://www.apache.org/licenses/LICENSE-2.0*/ +/* */ +/* Unless required by applicable law or agreed to in writing, software*/ +/* distributed under the License is distributed on an "AS IS" BASIS,*/ +/* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.*/ +/* See the License for the specific language governing permissions and*/ +/* limitations under the License.*/ +/* */ +/* Generated on Thu Aug 21 20:49:08 2025 */ +/* */ +/* ------------------------------------------------------ */ +library(RM_IHPSG13_1P_256x32_c2_bm_bist_fast_1p32V_m55C) { + technology (cmos) ; + delay_model : table_lookup ; + define ("add_pg_pin_to_lib", "library", "boolean"); + add_pg_pin_to_lib : true; + voltage_map ( VDD, 1.32); + voltage_map ( VDDARRAY, 1.32); + voltage_map ( VSS, 0.000000 ); + + date : "Thu Aug 21 20:49:06 2025" ; + comment : "IHP Microelectronics GmbH, 2023" ; + revision : 1.0.0 ; + simulation : true ; + nom_process : 1 ; + nom_temperature : -55 ; + nom_voltage : 1.32 ; + + operating_conditions("fast_1p32V_m55C"){ + process : 1 ; + temperature : -55 ; + voltage : 1.32 ; + tree_type : "balanced_tree" ; + } + + default_operating_conditions : fast_1p32V_m55C ; + default_max_transition : 1.0 ; + default_fanout_load : 1.0 ; + default_inout_pin_cap : 0.0 ; + default_input_pin_cap : 0.0 ; + default_output_pin_cap : 0.0 ; + default_cell_leakage_power : 0.0 ; + default_leakage_power_density : 0.0 ; + + slew_lower_threshold_pct_rise : 30 ; + slew_upper_threshold_pct_rise : 70 ; + input_threshold_pct_fall : 50 ; + output_threshold_pct_fall : 50 ; + input_threshold_pct_rise : 50 ; + output_threshold_pct_rise : 50 ; + slew_lower_threshold_pct_fall : 30 ; + slew_upper_threshold_pct_fall : 70 ; + slew_derate_from_library : 0.5; + k_volt_cell_leakage_power : 0.0 ; + k_temp_cell_leakage_power : 0.0 ; + k_process_cell_leakage_power : 0.0 ; + k_volt_internal_power : 0.0 ; + k_temp_internal_power : 0.0 ; + k_process_internal_power : 0.0 ; + + capacitive_load_unit (1,pf) ; + voltage_unit : "1V" ; + current_unit : "1uA" ; + time_unit : "1ns" ; + leakage_power_unit : "1nW" ; + pulling_resistance_unit : "1kohm"; + /* + ------------------------------------------------------------------------------------------ + implicit units overview: + cell_area unit : "um" + internal_power unit : "1e-12 * J/toggle = 1 * uW/MHz" + (capacitive_load_unit * voltage_unit^2) per toggle event + ------------------------------------------------------------------------------------------ + */ + library_features(report_delay_calculation); + define_cell_area (pad_drivers,pad_driver_sites) ; + + lu_table_template(CLKTRAN_constraint_template) { + variable_1 : constrained_pin_transition; + index_1 ( "0.010, 0.050, 0.200, 0.400, 1.000" ); + } + lu_table_template(SRAM_load_template) { + variable_1 : total_output_net_capacitance; + index_1 ( "0.0008,0.0014,0.0051,0.0100,0.0339,0.0640" ); + } + lu_table_template(SIG2SRAM_constraint_template) { + variable_1 : related_pin_transition; + variable_2 : constrained_pin_transition; + index_1 ( "0.0040,0.0176,0.0344,0.0656,0.1120,0.2016,0.3800" ); + index_2 ( "0.0040,0.0176,0.0344,0.0656,0.1120,0.2016,0.3800" ); + } + + lu_table_template(SIG2SRAM_delay_template) { + variable_1 : input_net_transition; + variable_2 : total_output_net_capacitance; + index_1 ( "0.0040,0.0176,0.0344,0.0656,0.1120,0.2016,0.3800" ); + index_2 ( "0.0008,0.0014,0.0051,0.0100,0.0339,0.0640" ); + } + + type (D_31_0) { + base_type : array; + data_type : bit; + bit_width : 32; + bit_from : 31; + bit_to : 0; + downto : true; + } + + type (A_7_0) { + base_type : array; + data_type : bit; + bit_width : 8; + bit_from : 7; + bit_to : 0; + downto : true; + } + +cell(RM_IHPSG13_1P_256x32_c2_bm_bist) { +pg_pin (VDD) { + pg_type : primary_power; + voltage_name : VDD; +} +pg_pin (VDDARRAY) { + pg_type : primary_power; + voltage_name : VDDARRAY; +} +pg_pin (VSS) { + pg_type : primary_ground; + voltage_name : VSS; +} + +memory() { + type : ram; + address_width : 8; + word_width : 32; +} + +interface_timing : false; +bus_naming_style : "%s[%d]" ; +area : 49488.4992 ; + + pin(A_DLY) { + direction : input ; + capacitance : 0.00421562 ; + max_transition : "1" ; + related_power_pin : VDD; + related_ground_pin : VSS; + internal_power() { + rise_power("scalar") { + values (0); + } + fall_power("scalar") { + values (0); + } + } + } + +bus(A_ADDR) { + bus_type : A_7_0; + direction : input ; + capacitance : 0.00691085 ; + pin(A_ADDR[0]) { + capacitance : 0.00562034 ; + } + pin(A_ADDR[1]) { + capacitance : 0.00462655 ; + } + pin(A_ADDR[2]) { + capacitance : 0.00594295 ; + } + pin(A_ADDR[3]) { + capacitance : 0.00723434 ; + } + pin(A_ADDR[4]) { + capacitance : 0.00481603 ; + } + pin(A_ADDR[5]) { + capacitance : 0.00868123 ; + } + pin(A_ADDR[6]) { + capacitance : 0.010187 ; + } + max_transition : "0.38" ; + pin(A_ADDR[7:0]) { + related_power_pin : VDD; + related_ground_pin : VSS; + internal_power() { + when : "A_MEN"; + rise_power("scalar"){ + values (0.0108); + } + fall_power("scalar"){ + values (0.0034); + } + } + internal_power() { + when : "!A_MEN"; + rise_power("scalar"){ + values (0.0264); + } + fall_power("scalar"){ + values (0.0033); + } + } + } + timing() { + timing_type : setup_rising; + related_pin : "A_CLK"; + when : "((A_WEN | A_REN)& A_MEN)" + sdf_cond : "A_RW_ACCESS" + + rise_constraint("SIG2SRAM_constraint_template") { + index_1("0.0040,0.0176,0.0344,0.0656,0.1120,0.2016,0.3800"); + index_2("0.0040,0.0176,0.0344,0.0656,0.1120,0.2016,0.3800"); + values ("-0.2371,-0.2215,-0.2098,-0.1824,-0.1434,-0.0691,0.0676",\ +"-0.2449,-0.2332,-0.2176,-0.1902,-0.1551,-0.0770,0.0559",\ +"-0.2605,-0.2488,-0.2332,-0.2059,-0.1707,-0.0965,0.0441",\ +"-0.2879,-0.2723,-0.2605,-0.2332,-0.1941,-0.1199,0.0168",\ +"-0.3230,-0.3113,-0.2996,-0.2723,-0.2332,-0.1590,-0.0184",\ +"-0.4012,-0.3895,-0.3738,-0.3465,-0.3074,-0.2332,-0.0965",\ +"-0.5379,-0.5262,-0.5105,-0.4832,-0.4480,-0.3699,-0.2332"); + } + + fall_constraint("SIG2SRAM_constraint_template") { + index_1("0.0040,0.0176,0.0344,0.0656,0.1120,0.2016,0.3800"); + index_2("0.0040,0.0176,0.0344,0.0656,0.1120,0.2016,0.3800"); + values ("-0.1785,-0.1707,-0.1551,-0.1277,-0.0887,-0.0184,0.1145",\ +"-0.1902,-0.1785,-0.1629,-0.1355,-0.1004,-0.0262,0.1027",\ +"-0.2059,-0.1941,-0.1785,-0.1512,-0.1160,-0.0418,0.0871",\ +"-0.2293,-0.2176,-0.2059,-0.1785,-0.1434,-0.0691,0.0598",\ +"-0.2684,-0.2566,-0.2449,-0.2176,-0.1824,-0.1082,0.0207",\ +"-0.3465,-0.3348,-0.3191,-0.2918,-0.2566,-0.1824,-0.0535",\ +"-0.4832,-0.4715,-0.4559,-0.4324,-0.3934,-0.3191,-0.1902"); + } + } + + + timing() { + timing_type : hold_rising; + related_pin : "A_CLK"; + when : "((A_WEN | A_REN)& A_MEN)" + sdf_cond : "A_RW_ACCESS" + + rise_constraint("SIG2SRAM_constraint_template") { + index_1("0.0040,0.0176,0.0344,0.0656,0.1120,0.2016,0.3800"); + index_2("0.0040,0.0176,0.0344,0.0656,0.1120,0.2016,0.3800"); + values ("0.3410,0.3293,0.3137,0.2863,0.2473,0.1730,0.0324",\ +"0.3488,0.3371,0.3215,0.2941,0.2590,0.1809,0.0480",\ +"0.3684,0.3527,0.3371,0.3098,0.2746,0.1965,0.0598",\ +"0.3918,0.3762,0.3645,0.3371,0.2980,0.2238,0.0871",\ +"0.4309,0.4152,0.4035,0.3762,0.3371,0.2629,0.1223",\ +"0.5051,0.4934,0.4777,0.4504,0.4113,0.3371,0.1965",\ +"0.6418,0.6262,0.6145,0.5871,0.5520,0.4738,0.3332"); + } + + fall_constraint("SIG2SRAM_constraint_template") { + index_1("0.0040,0.0176,0.0344,0.0656,0.1120,0.2016,0.3800"); + index_2("0.0040,0.0176,0.0344,0.0656,0.1120,0.2016,0.3800"); + values ("0.2824,0.2707,0.2551,0.2277,0.1926,0.1184,-0.0105",\ +"0.2902,0.2785,0.2668,0.2395,0.2043,0.1301,0.0012",\ +"0.3059,0.2941,0.2824,0.2551,0.2199,0.1457,0.0168",\ +"0.3332,0.3215,0.3059,0.2785,0.2434,0.1691,0.0402",\ +"0.3723,0.3605,0.3449,0.3176,0.2824,0.2121,0.0793",\ +"0.4465,0.4348,0.4230,0.3918,0.3566,0.2824,0.1535",\ +"0.5832,0.5715,0.5598,0.5324,0.4934,0.4191,0.2902"); + } + } +} +pin(A_WEN) { + direction : input ; + capacitance : 0.00341384 ; + max_transition : "0.38" ; + related_power_pin : VDD; + related_ground_pin : VSS; + internal_power() { + when : "A_MEN"; + rise_power("scalar"){ + values (0.0040); + } + fall_power("scalar"){ + values (0.0171); + } + } + internal_power() { + when : "!A_MEN"; + rise_power("scalar"){ + values (0.0050); + } + fall_power("scalar"){ + values (0.0218); + } + } + timing() { + timing_type : setup_rising; + related_pin : "A_CLK"; + when : "A_MEN" + sdf_cond : "A_MEN" + + rise_constraint("SIG2SRAM_constraint_template") { + index_1("0.0040,0.0176,0.0344,0.0656,0.1120,0.2016,0.3800"); + index_2("0.0040,0.0176,0.0344,0.0656,0.1120,0.2016,0.3800"); + values ("0.1418,0.1496,0.1652,0.1887,0.2316,0.3059,0.4465",\ +"0.1301,0.1379,0.1535,0.1809,0.2199,0.2941,0.4348",\ +"0.1145,0.1262,0.1379,0.1652,0.2043,0.2785,0.4191",\ +"0.0871,0.0949,0.1105,0.1379,0.1770,0.2512,0.3879",\ +"0.0480,0.0598,0.0754,0.0988,0.1379,0.2082,0.3527",\ +"-0.0262,-0.0145,0.0012,0.0246,0.0676,0.1379,0.2785",\ +"-0.1668,-0.1551,-0.1395,-0.1121,-0.0730,0.0012,0.1418"); + } + + fall_constraint("SIG2SRAM_constraint_template") { + index_1("0.0040,0.0176,0.0344,0.0656,0.1120,0.2016,0.3800"); + index_2("0.0040,0.0176,0.0344,0.0656,0.1120,0.2016,0.3800"); + values ("0.2082,0.2160,0.2316,0.2590,0.2941,0.3684,0.5012",\ +"0.1926,0.2043,0.2199,0.2473,0.2824,0.3566,0.4895",\ +"0.1770,0.1887,0.2043,0.2316,0.2668,0.3410,0.4777",\ +"0.1535,0.1652,0.1770,0.2043,0.2395,0.3137,0.4504",\ +"0.1145,0.1262,0.1379,0.1652,0.2043,0.2746,0.4113",\ +"0.0402,0.0520,0.0676,0.0910,0.1262,0.2004,0.3332",\ +"-0.0965,-0.0848,-0.0730,-0.0457,-0.0066,0.0637,0.2004"); + } + } + + + timing() { + timing_type : hold_rising; + related_pin : "A_CLK"; + when : "A_MEN" + sdf_cond : "A_MEN" + + rise_constraint("SIG2SRAM_constraint_template") { + index_1("0.0040,0.0176,0.0344,0.0656,0.1120,0.2016,0.3800"); + index_2("0.0040,0.0176,0.0344,0.0656,0.1120,0.2016,0.3800"); + values ("0.1770,0.1652,0.1496,0.1223,0.0793,0.0090,-0.1316",\ +"0.1848,0.1730,0.1574,0.1301,0.0910,0.0168,-0.1199",\ +"0.2004,0.1887,0.1770,0.1496,0.1066,0.0363,-0.1043",\ +"0.2277,0.2160,0.2004,0.1730,0.1340,0.0598,-0.0809",\ +"0.2668,0.2551,0.2395,0.2121,0.1730,0.0988,-0.0418",\ +"0.3410,0.3293,0.3137,0.2863,0.2434,0.1730,0.0324",\ +"0.4816,0.4699,0.4543,0.4230,0.3801,0.3098,0.1730"); + } + + fall_constraint("SIG2SRAM_constraint_template") { + index_1("0.0040,0.0176,0.0344,0.0656,0.1120,0.2016,0.3800"); + index_2("0.0040,0.0176,0.0344,0.0656,0.1120,0.2016,0.3800"); + values ("0.1613,0.1496,0.1379,0.1066,0.0715,0.0012,-0.1355",\ +"0.1730,0.1613,0.1457,0.1184,0.0832,0.0129,-0.1238",\ +"0.1887,0.1770,0.1613,0.1340,0.0988,0.0246,-0.1121",\ +"0.2121,0.2043,0.1887,0.1613,0.1223,0.0520,-0.0848",\ +"0.2512,0.2434,0.2277,0.2004,0.1613,0.0910,-0.0457",\ +"0.3254,0.3176,0.3020,0.2746,0.2355,0.1652,0.0324",\ +"0.4660,0.4543,0.4387,0.4113,0.3723,0.3020,0.1691"); + } + } + } +pin(A_REN) { + direction : input ; + capacitance : 0.00390661 ; + max_transition : "0.38" ; + related_power_pin : VDD; + related_ground_pin : VSS; + internal_power() { + when : "A_MEN"; + rise_power("scalar"){ + values (0.0122); + } + fall_power("scalar"){ + values (0.0105); + } + } + internal_power() { + when : "!A_MEN"; + rise_power("scalar"){ + values (0.0181); + } + fall_power("scalar"){ + values (0.0202); + } + } + timing() { + timing_type : setup_rising; + related_pin : "A_CLK"; + when : "A_MEN" + sdf_cond : "A_MEN" + + rise_constraint("SIG2SRAM_constraint_template") { + index_1("0.0040,0.0176,0.0344,0.0656,0.1120,0.2016,0.3800"); + index_2("0.0040,0.0176,0.0344,0.0656,0.1120,0.2016,0.3800"); + values ("-0.0027,0.0090,0.0246,0.0520,0.0910,0.1613,0.3020",\ +"-0.0105,0.0012,0.0129,0.0363,0.0793,0.1535,0.2902",\ +"-0.0262,-0.0145,-0.0027,0.0246,0.0637,0.1379,0.2785",\ +"-0.0535,-0.0418,-0.0262,0.0012,0.0363,0.1105,0.2512",\ +"-0.0926,-0.0809,-0.0652,-0.0418,-0.0027,0.0715,0.2121",\ +"-0.1668,-0.1551,-0.1395,-0.1082,-0.0770,-0.0027,0.1379",\ +"-0.3035,-0.2918,-0.2762,-0.2488,-0.2137,-0.1434,-0.0027"); + } + + fall_constraint("SIG2SRAM_constraint_template") { + index_1("0.0040,0.0176,0.0344,0.0656,0.1120,0.2016,0.3800"); + index_2("0.0040,0.0176,0.0344,0.0656,0.1120,0.2016,0.3800"); + values ("0.0832,0.0949,0.1105,0.1379,0.1730,0.2473,0.3801",\ +"0.0754,0.0832,0.0988,0.1223,0.1613,0.2355,0.3684",\ +"0.0598,0.0676,0.0832,0.1066,0.1457,0.2121,0.3527",\ +"0.0324,0.0441,0.0598,0.0871,0.1223,0.1926,0.3293",\ +"-0.0066,0.0051,0.0168,0.0480,0.0832,0.1535,0.2902",\ +"-0.0809,-0.0691,-0.0574,-0.0301,0.0090,0.0832,0.2121",\ +"-0.2176,-0.2059,-0.1941,-0.1668,-0.1277,-0.0574,0.0793"); + } + } + + + timing() { + timing_type : hold_rising; + related_pin : "A_CLK"; + when : "A_MEN" + sdf_cond : "A_MEN" + + rise_constraint("SIG2SRAM_constraint_template") { + index_1("0.0040,0.0176,0.0344,0.0656,0.1120,0.2016,0.3800"); + index_2("0.0040,0.0176,0.0344,0.0656,0.1120,0.2016,0.3800"); + values ("0.1887,0.1770,0.1613,0.1340,0.0949,0.0207,-0.1160",\ +"0.1965,0.1848,0.1730,0.1457,0.1027,0.0324,-0.1082",\ +"0.2160,0.2004,0.1887,0.1613,0.1184,0.0480,-0.0926",\ +"0.2395,0.2277,0.2121,0.1848,0.1457,0.0715,-0.0652",\ +"0.2785,0.2668,0.2512,0.2238,0.1848,0.1105,-0.0262",\ +"0.3527,0.3410,0.3254,0.2980,0.2551,0.1848,0.0480",\ +"0.4934,0.4816,0.4660,0.4387,0.3957,0.3254,0.1887"); + } + + fall_constraint("SIG2SRAM_constraint_template") { + index_1("0.0040,0.0176,0.0344,0.0656,0.1120,0.2016,0.3800"); + index_2("0.0040,0.0176,0.0344,0.0656,0.1120,0.2016,0.3800"); + values ("0.1730,0.1613,0.1496,0.1184,0.0793,0.0129,-0.1238",\ +"0.1848,0.1730,0.1574,0.1301,0.0910,0.0207,-0.1121",\ +"0.2004,0.1887,0.1730,0.1457,0.1066,0.0363,-0.1004",\ +"0.2238,0.2121,0.2004,0.1691,0.1340,0.0598,-0.0730",\ +"0.2629,0.2512,0.2395,0.2121,0.1691,0.0988,-0.0340",\ +"0.3371,0.3254,0.3137,0.2863,0.2434,0.1730,0.0402",\ +"0.4777,0.4660,0.4504,0.4230,0.3840,0.3137,0.1809"); + } + } + } +pin(A_MEN) { + direction : input ; + capacitance : 0.00326046 ; + max_transition : "0.38" ; + related_power_pin : VDD; + related_ground_pin : VSS; + internal_power() { + rise_power("scalar"){ + values (0.2714); + } + fall_power("scalar"){ + values (0.0108); + } + } + timing() { + timing_type : setup_rising; + related_pin : "A_CLK"; + + rise_constraint("SIG2SRAM_constraint_template") { + index_1("0.0040,0.0176,0.0344,0.0656,0.1120,0.2016,0.3800"); + index_2("0.0040,0.0176,0.0344,0.0656,0.1120,0.2016,0.3800"); + values ("0.1418,0.1496,0.1652,0.1926,0.2316,0.3059,0.4465",\ +"0.1301,0.1379,0.1535,0.1809,0.2199,0.2941,0.4348",\ +"0.1145,0.1262,0.1418,0.1652,0.2043,0.2785,0.4191",\ +"0.0871,0.0949,0.1105,0.1379,0.1770,0.2512,0.3879",\ +"0.0480,0.0598,0.0754,0.0988,0.1379,0.2082,0.3488",\ +"-0.0262,-0.0145,0.0012,0.0285,0.0676,0.1379,0.2785",\ +"-0.1668,-0.1551,-0.1395,-0.1121,-0.0730,0.0012,0.1379"); + } + + fall_constraint("SIG2SRAM_constraint_template") { + index_1("0.0040,0.0176,0.0344,0.0656,0.1120,0.2016,0.3800"); + index_2("0.0040,0.0176,0.0344,0.0656,0.1120,0.2016,0.3800"); + values ("0.2082,0.2199,0.2316,0.2590,0.2980,0.3723,0.5051",\ +"0.1965,0.2082,0.2199,0.2473,0.2863,0.3605,0.4934",\ +"0.1809,0.1926,0.2043,0.2316,0.2707,0.3449,0.4777",\ +"0.1574,0.1691,0.1809,0.2082,0.2434,0.3176,0.4543",\ +"0.1145,0.1262,0.1418,0.1691,0.2043,0.2785,0.4113",\ +"0.0441,0.0559,0.0676,0.0949,0.1301,0.2004,0.3332",\ +"-0.0965,-0.0848,-0.0691,-0.0418,-0.0066,0.0676,0.2004"); + } + } + + + timing() { + timing_type : hold_rising; + related_pin : "A_CLK"; + + rise_constraint("SIG2SRAM_constraint_template") { + index_1("0.0040,0.0176,0.0344,0.0656,0.1120,0.2016,0.3800"); + index_2("0.0040,0.0176,0.0344,0.0656,0.1120,0.2016,0.3800"); + values ("0.1770,0.1652,0.1535,0.1262,0.0832,0.0129,-0.1277",\ +"0.1887,0.1770,0.1613,0.1340,0.0949,0.0207,-0.1199",\ +"0.2043,0.1926,0.1770,0.1496,0.1105,0.0363,-0.1043",\ +"0.2277,0.2160,0.2043,0.1770,0.1379,0.0598,-0.0770",\ +"0.2668,0.2551,0.2434,0.2160,0.1730,0.0988,-0.0379",\ +"0.3449,0.3332,0.3176,0.2902,0.2473,0.1730,0.0363",\ +"0.4816,0.4699,0.4543,0.4270,0.3840,0.3098,0.1770"); + } + + fall_constraint("SIG2SRAM_constraint_template") { + index_1("0.0040,0.0176,0.0344,0.0656,0.1120,0.2016,0.3800"); + index_2("0.0040,0.0176,0.0344,0.0656,0.1120,0.2016,0.3800"); + values ("0.1613,0.1496,0.1379,0.1105,0.0715,0.0012,-0.1355",\ +"0.1730,0.1613,0.1496,0.1184,0.0832,0.0129,-0.1238",\ +"0.1887,0.1770,0.1652,0.1340,0.0988,0.0285,-0.1121",\ +"0.2121,0.2043,0.1887,0.1613,0.1223,0.0520,-0.0848",\ +"0.2551,0.2434,0.2277,0.2004,0.1613,0.0910,-0.0418",\ +"0.3293,0.3176,0.3020,0.2746,0.2395,0.1652,0.0324",\ +"0.4660,0.4543,0.4426,0.4113,0.3762,0.3020,0.1691"); + } + } + } +bus(A_BM) { + bus_type : D_31_0; + direction : input ; + capacitance : 0.00310985 ; + max_transition : "0.38" ; + pin(A_BM[31:0]) { + related_power_pin : VDD; + related_ground_pin : VSS; + internal_power() { + when : "A_MEN"; + rise_power("scalar"){ + values (0.1809); + } + fall_power("scalar"){ + values (0.1563); + } + } + internal_power() { + when : "!A_MEN"; + rise_power("scalar"){ + values (0.1509); + } + fall_power("scalar"){ + values (0.1509); + } + } + } + timing() { + timing_type : setup_rising; + related_pin : "A_CLK"; + when : "(A_WEN & A_MEN)" + sdf_cond : "A_RW_ACCESS" + + rise_constraint("SIG2SRAM_constraint_template") { + index_1("0.0040,0.0176,0.0344,0.0656,0.1120,0.2016,0.3800"); + index_2("0.0040,0.0176,0.0344,0.0656,0.1120,0.2016,0.3800"); + values ("-0.2520,-0.2412,-0.2256,-0.1993,-0.1592,-0.0889,0.0459",\ +"-0.2559,-0.2451,-0.2295,-0.2031,-0.1631,-0.0928,0.0420",\ +"-0.2596,-0.2488,-0.2332,-0.2068,-0.1668,-0.0965,0.0383",\ +"-0.2628,-0.2520,-0.2364,-0.2100,-0.1700,-0.0997,0.0351",\ +"-0.2754,-0.2646,-0.2490,-0.2226,-0.1826,-0.1123,0.0225",\ +"-0.2930,-0.2822,-0.2666,-0.2402,-0.2002,-0.1299,0.0049",\ +"-0.3205,-0.3097,-0.2941,-0.2678,-0.2277,-0.1574,-0.0226"); + } + + fall_constraint("SIG2SRAM_constraint_template") { + index_1("0.0040,0.0176,0.0344,0.0656,0.1120,0.2016,0.3800"); + index_2("0.0040,0.0176,0.0344,0.0656,0.1120,0.2016,0.3800"); + values ("-0.2295,-0.2188,-0.2051,-0.1778,-0.1407,-0.0684,0.0615",\ +"-0.2334,-0.2227,-0.2090,-0.1817,-0.1445,-0.0723,0.0576",\ +"-0.2371,-0.2264,-0.2127,-0.1853,-0.1482,-0.0760,0.0539",\ +"-0.2403,-0.2295,-0.2159,-0.1885,-0.1514,-0.0792,0.0507",\ +"-0.2529,-0.2422,-0.2285,-0.2012,-0.1641,-0.0918,0.0381",\ +"-0.2705,-0.2598,-0.2461,-0.2188,-0.1817,-0.1094,0.0205",\ +"-0.2980,-0.2873,-0.2736,-0.2463,-0.2092,-0.1369,-0.0070"); + } + } + + + timing() { + timing_type : hold_rising; + related_pin : "A_CLK"; + when : "(A_WEN & A_MEN)" + sdf_cond : "A_RW_ACCESS" + + rise_constraint("SIG2SRAM_constraint_template") { + index_1("0.0040,0.0176,0.0344,0.0656,0.1120,0.2016,0.3800"); + index_2("0.0040,0.0176,0.0344,0.0656,0.1120,0.2016,0.3800"); + values ("0.3581,0.3463,0.3317,0.3053,0.2653,0.1940,0.0573",\ +"0.3619,0.3502,0.3356,0.3092,0.2692,0.1979,0.0612",\ +"0.3656,0.3539,0.3393,0.3129,0.2728,0.2016,0.0648",\ +"0.3688,0.3571,0.3425,0.3161,0.2760,0.2048,0.0680",\ +"0.3814,0.3697,0.3551,0.3287,0.2887,0.2174,0.0807",\ +"0.3990,0.3873,0.3727,0.3463,0.3063,0.2350,0.0983",\ +"0.4266,0.4148,0.4002,0.3738,0.3338,0.2625,0.1258"); + } + + fall_constraint("SIG2SRAM_constraint_template") { + index_1("0.0040,0.0176,0.0344,0.0656,0.1120,0.2016,0.3800"); + index_2("0.0040,0.0176,0.0344,0.0656,0.1120,0.2016,0.3800"); + values ("0.3297,0.3200,0.3053,0.2790,0.2418,0.1686,0.0407",\ +"0.3336,0.3239,0.3092,0.2828,0.2457,0.1725,0.0446",\ +"0.3373,0.3275,0.3129,0.2865,0.2494,0.1762,0.0482",\ +"0.3405,0.3307,0.3161,0.2897,0.2526,0.1794,0.0514",\ +"0.3531,0.3434,0.3287,0.3023,0.2652,0.1920,0.0641",\ +"0.3707,0.3610,0.3463,0.3199,0.2828,0.2096,0.0817",\ +"0.3982,0.3885,0.3738,0.3475,0.3103,0.2371,0.1092"); + } + } +} + pin(A_CLK) { + direction : input; + capacitance : 0.00389386; + max_transition : "0.38"; + clock : "true" ; + pin_func_type : active_rising ; + + timing () { + timing_type : "min_pulse_width"; + related_pin : "A_CLK"; + rise_constraint("CLKTRAN_constraint_template") { + index_1("0.004,0.38"); + values("0.12,0.12"); + } + } + + related_power_pin : VDD; + related_ground_pin : VSS; + + internal_power() { + when : "!A_MEN & !A_WEN & !A_REN"; + rise_power("scalar"){ + values (0); + } + fall_power("scalar"){ + values (0); + } + } + internal_power() { + when : "!A_MEN & A_WEN & !A_REN"; + rise_power("scalar"){ + values (0.6783); + } + fall_power("scalar"){ + values (0); + } + } + internal_power() { + when : "A_MEN & A_WEN & !A_REN"; + rise_power("scalar"){ + values (41.2558); + } + fall_power("scalar"){ + values (0); + } + } + internal_power() { + when : "A_MEN & A_WEN & A_REN"; + rise_power("scalar"){ + values (46.5325); + } + fall_power("scalar"){ + values (0); + } + } + internal_power() { + when : "A_MEN & !A_WEN & A_REN"; + rise_power("scalar"){ + values (34.0312); + } + fall_power("scalar"){ + values (0); + } + } + internal_power() { + when : "!A_MEN & !A_WEN & A_REN"; + rise_power("scalar"){ + values (0.4087); + } + fall_power("scalar"){ + values (0); + } + } + internal_power() { + when : "!A_MEN & A_WEN & A_REN"; + rise_power("scalar"){ + values (1.3353); + } + fall_power("scalar"){ + values (0); + } + } + internal_power() { + when : "A_MEN & !A_WEN & !A_REN"; + rise_power("scalar"){ + values (0); + } + fall_power("scalar"){ + values (0); + } + } + } + bus(A_DIN) { + bus_type : D_31_0; + direction : input ; + capacitance : 0.00387207 ; + memory_write() { + address : A_ADDR ; + clocked_on : A_CLK; + } + + max_transition : "0.38" ; + pin(A_DIN[31:0]) { + related_power_pin : VDD; + related_ground_pin : VSS; + internal_power() { + when : "A_MEN"; + rise_power("scalar"){ + values (0.1809); + } + fall_power("scalar"){ + values (0.1563); + } + } + internal_power() { + when : "!A_MEN"; + rise_power("scalar"){ + values (0.1509); + } + fall_power("scalar"){ + values (0.1509); + } + } + } + timing() { + timing_type : setup_rising; + related_pin : "A_CLK"; + when : "(A_WEN & A_MEN)"; + sdf_cond : "A_W_ACCESS"; + + rise_constraint("SIG2SRAM_constraint_template") { + index_1("0.0040,0.0176,0.0344,0.0656,0.1120,0.2016,0.3800"); + index_2("0.0040,0.0176,0.0344,0.0656,0.1120,0.2016,0.3800"); + values ("-0.2520,-0.2412,-0.2256,-0.1993,-0.1592,-0.0889,0.0459",\ +"-0.2559,-0.2451,-0.2295,-0.2031,-0.1631,-0.0928,0.0420",\ +"-0.2596,-0.2488,-0.2332,-0.2068,-0.1668,-0.0965,0.0383",\ +"-0.2628,-0.2520,-0.2364,-0.2100,-0.1700,-0.0997,0.0351",\ +"-0.2754,-0.2646,-0.2490,-0.2226,-0.1826,-0.1123,0.0225",\ +"-0.2930,-0.2822,-0.2666,-0.2402,-0.2002,-0.1299,0.0049",\ +"-0.3205,-0.3097,-0.2941,-0.2678,-0.2277,-0.1574,-0.0226"); + } + + fall_constraint("SIG2SRAM_constraint_template") { + index_1("0.0040,0.0176,0.0344,0.0656,0.1120,0.2016,0.3800"); + index_2("0.0040,0.0176,0.0344,0.0656,0.1120,0.2016,0.3800"); + values ("-0.2295,-0.2188,-0.2051,-0.1778,-0.1407,-0.0684,0.0615",\ +"-0.2334,-0.2227,-0.2090,-0.1817,-0.1445,-0.0723,0.0576",\ +"-0.2371,-0.2264,-0.2127,-0.1853,-0.1482,-0.0760,0.0539",\ +"-0.2403,-0.2295,-0.2159,-0.1885,-0.1514,-0.0792,0.0507",\ +"-0.2529,-0.2422,-0.2285,-0.2012,-0.1641,-0.0918,0.0381",\ +"-0.2705,-0.2598,-0.2461,-0.2188,-0.1817,-0.1094,0.0205",\ +"-0.2980,-0.2873,-0.2736,-0.2463,-0.2092,-0.1369,-0.0070"); + } + } + + timing() { + timing_type : hold_rising; + related_pin : "A_CLK"; + when : "(A_WEN & A_MEN)"; + sdf_cond : "A_W_ACCESS"; + + rise_constraint("SIG2SRAM_constraint_template") { + index_1("0.0040,0.0176,0.0344,0.0656,0.1120,0.2016,0.3800"); + index_2("0.0040,0.0176,0.0344,0.0656,0.1120,0.2016,0.3800"); + values ("0.3581,0.3463,0.3317,0.3053,0.2653,0.1940,0.0573",\ +"0.3619,0.3502,0.3356,0.3092,0.2692,0.1979,0.0612",\ +"0.3656,0.3539,0.3393,0.3129,0.2728,0.2016,0.0648",\ +"0.3688,0.3571,0.3425,0.3161,0.2760,0.2048,0.0680",\ +"0.3814,0.3697,0.3551,0.3287,0.2887,0.2174,0.0807",\ +"0.3990,0.3873,0.3727,0.3463,0.3063,0.2350,0.0983",\ +"0.4266,0.4148,0.4002,0.3738,0.3338,0.2625,0.1258"); + } + + fall_constraint("SIG2SRAM_constraint_template") { + index_1("0.0040,0.0176,0.0344,0.0656,0.1120,0.2016,0.3800"); + index_2("0.0040,0.0176,0.0344,0.0656,0.1120,0.2016,0.3800"); + values ("0.3297,0.3200,0.3053,0.2790,0.2418,0.1686,0.0407",\ +"0.3336,0.3239,0.3092,0.2828,0.2457,0.1725,0.0446",\ +"0.3373,0.3275,0.3129,0.2865,0.2494,0.1762,0.0482",\ +"0.3405,0.3307,0.3161,0.2897,0.2526,0.1794,0.0514",\ +"0.3531,0.3434,0.3287,0.3023,0.2652,0.1920,0.0641",\ +"0.3707,0.3610,0.3463,0.3199,0.2828,0.2096,0.0817",\ +"0.3982,0.3885,0.3738,0.3475,0.3103,0.2371,0.1092"); + } + } + } + + pin(A_BIST_EN) { + direction : input ; + capacitance : 0.00421562 ; + max_transition : "1" ; + related_power_pin : VDD; + related_ground_pin : VSS; + internal_power() { + rise_power("scalar") { + values (0); + } + fall_power("scalar") { + values (0); + } + } + } + +bus(A_BIST_ADDR) { + bus_type : A_7_0; + direction : input ; + capacitance : 0.00691085 ; + pin(A_BIST_ADDR[0]) { + capacitance : 0.00562034 ; + } + pin(A_BIST_ADDR[1]) { + capacitance : 0.00462655 ; + } + pin(A_BIST_ADDR[2]) { + capacitance : 0.00594295 ; + } + pin(A_BIST_ADDR[3]) { + capacitance : 0.00723434 ; + } + pin(A_BIST_ADDR[4]) { + capacitance : 0.00481603 ; + } + pin(A_BIST_ADDR[5]) { + capacitance : 0.00868123 ; + } + pin(A_BIST_ADDR[6]) { + capacitance : 0.010187 ; + } + max_transition : "0.38" ; + pin(A_BIST_ADDR[7:0]) { + related_power_pin : VDD; + related_ground_pin : VSS; + internal_power() { + when : "A_BIST_MEN"; + rise_power("scalar"){ + values (0.0108); + } + fall_power("scalar"){ + values (0.0034); + } + } + internal_power() { + when : "!A_BIST_MEN"; + rise_power("scalar"){ + values (0.0264); + } + fall_power("scalar"){ + values (0.0033); + } + } + } + timing() { + timing_type : setup_rising; + related_pin : "A_BIST_CLK"; + when : "((A_BIST_WEN | A_BIST_REN)& A_BIST_MEN)" + sdf_cond : "A_BIST_RW_ACCESS" + + rise_constraint("SIG2SRAM_constraint_template") { + index_1("0.0040,0.0176,0.0344,0.0656,0.1120,0.2016,0.3800"); + index_2("0.0040,0.0176,0.0344,0.0656,0.1120,0.2016,0.3800"); + values ("-0.2371,-0.2215,-0.2098,-0.1824,-0.1434,-0.0691,0.0676",\ +"-0.2449,-0.2332,-0.2176,-0.1902,-0.1551,-0.0770,0.0559",\ +"-0.2605,-0.2488,-0.2332,-0.2059,-0.1707,-0.0965,0.0441",\ +"-0.2879,-0.2723,-0.2605,-0.2332,-0.1941,-0.1199,0.0168",\ +"-0.3230,-0.3113,-0.2996,-0.2723,-0.2332,-0.1590,-0.0184",\ +"-0.4012,-0.3895,-0.3738,-0.3465,-0.3074,-0.2332,-0.0965",\ +"-0.5379,-0.5262,-0.5105,-0.4832,-0.4480,-0.3699,-0.2332"); + } + + fall_constraint("SIG2SRAM_constraint_template") { + index_1("0.0040,0.0176,0.0344,0.0656,0.1120,0.2016,0.3800"); + index_2("0.0040,0.0176,0.0344,0.0656,0.1120,0.2016,0.3800"); + values ("-0.1785,-0.1707,-0.1551,-0.1277,-0.0887,-0.0184,0.1145",\ +"-0.1902,-0.1785,-0.1629,-0.1355,-0.1004,-0.0262,0.1027",\ +"-0.2059,-0.1941,-0.1785,-0.1512,-0.1160,-0.0418,0.0871",\ +"-0.2293,-0.2176,-0.2059,-0.1785,-0.1434,-0.0691,0.0598",\ +"-0.2684,-0.2566,-0.2449,-0.2176,-0.1824,-0.1082,0.0207",\ +"-0.3465,-0.3348,-0.3191,-0.2918,-0.2566,-0.1824,-0.0535",\ +"-0.4832,-0.4715,-0.4559,-0.4324,-0.3934,-0.3191,-0.1902"); + } + } + + + timing() { + timing_type : hold_rising; + related_pin : "A_BIST_CLK"; + when : "((A_BIST_WEN | A_BIST_REN)& A_BIST_MEN)" + sdf_cond : "A_BIST_RW_ACCESS" + + rise_constraint("SIG2SRAM_constraint_template") { + index_1("0.0040,0.0176,0.0344,0.0656,0.1120,0.2016,0.3800"); + index_2("0.0040,0.0176,0.0344,0.0656,0.1120,0.2016,0.3800"); + values ("0.3410,0.3293,0.3137,0.2863,0.2473,0.1730,0.0324",\ +"0.3488,0.3371,0.3215,0.2941,0.2590,0.1809,0.0480",\ +"0.3684,0.3527,0.3371,0.3098,0.2746,0.1965,0.0598",\ +"0.3918,0.3762,0.3645,0.3371,0.2980,0.2238,0.0871",\ +"0.4309,0.4152,0.4035,0.3762,0.3371,0.2629,0.1223",\ +"0.5051,0.4934,0.4777,0.4504,0.4113,0.3371,0.1965",\ +"0.6418,0.6262,0.6145,0.5871,0.5520,0.4738,0.3332"); + } + + fall_constraint("SIG2SRAM_constraint_template") { + index_1("0.0040,0.0176,0.0344,0.0656,0.1120,0.2016,0.3800"); + index_2("0.0040,0.0176,0.0344,0.0656,0.1120,0.2016,0.3800"); + values ("0.2824,0.2707,0.2551,0.2277,0.1926,0.1184,-0.0105",\ +"0.2902,0.2785,0.2668,0.2395,0.2043,0.1301,0.0012",\ +"0.3059,0.2941,0.2824,0.2551,0.2199,0.1457,0.0168",\ +"0.3332,0.3215,0.3059,0.2785,0.2434,0.1691,0.0402",\ +"0.3723,0.3605,0.3449,0.3176,0.2824,0.2121,0.0793",\ +"0.4465,0.4348,0.4230,0.3918,0.3566,0.2824,0.1535",\ +"0.5832,0.5715,0.5598,0.5324,0.4934,0.4191,0.2902"); + } + } +} +pin(A_BIST_WEN) { + direction : input ; + capacitance : 0.00341384 ; + max_transition : "0.38" ; + related_power_pin : VDD; + related_ground_pin : VSS; + internal_power() { + when : "A_BIST_MEN"; + rise_power("scalar"){ + values (0.0040); + } + fall_power("scalar"){ + values (0.0171); + } + } + internal_power() { + when : "!A_BIST_MEN"; + rise_power("scalar"){ + values (0.0050); + } + fall_power("scalar"){ + values (0.0218); + } + } + timing() { + timing_type : setup_rising; + related_pin : "A_BIST_CLK"; + when : "A_BIST_MEN" + sdf_cond : "A_BIST_MEN" + + rise_constraint("SIG2SRAM_constraint_template") { + index_1("0.0040,0.0176,0.0344,0.0656,0.1120,0.2016,0.3800"); + index_2("0.0040,0.0176,0.0344,0.0656,0.1120,0.2016,0.3800"); + values ("0.1418,0.1496,0.1652,0.1887,0.2316,0.3059,0.4465",\ +"0.1301,0.1379,0.1535,0.1809,0.2199,0.2941,0.4348",\ +"0.1145,0.1262,0.1379,0.1652,0.2043,0.2785,0.4191",\ +"0.0871,0.0949,0.1105,0.1379,0.1770,0.2512,0.3879",\ +"0.0480,0.0598,0.0754,0.0988,0.1379,0.2082,0.3527",\ +"-0.0262,-0.0145,0.0012,0.0246,0.0676,0.1379,0.2785",\ +"-0.1668,-0.1551,-0.1395,-0.1121,-0.0730,0.0012,0.1418"); + } + + fall_constraint("SIG2SRAM_constraint_template") { + index_1("0.0040,0.0176,0.0344,0.0656,0.1120,0.2016,0.3800"); + index_2("0.0040,0.0176,0.0344,0.0656,0.1120,0.2016,0.3800"); + values ("0.2082,0.2160,0.2316,0.2590,0.2941,0.3684,0.5012",\ +"0.1926,0.2043,0.2199,0.2473,0.2824,0.3566,0.4895",\ +"0.1770,0.1887,0.2043,0.2316,0.2668,0.3410,0.4777",\ +"0.1535,0.1652,0.1770,0.2043,0.2395,0.3137,0.4504",\ +"0.1145,0.1262,0.1379,0.1652,0.2043,0.2746,0.4113",\ +"0.0402,0.0520,0.0676,0.0910,0.1262,0.2004,0.3332",\ +"-0.0965,-0.0848,-0.0730,-0.0457,-0.0066,0.0637,0.2004"); + } + } + + + timing() { + timing_type : hold_rising; + related_pin : "A_BIST_CLK"; + when : "A_BIST_MEN" + sdf_cond : "A_BIST_MEN" + + rise_constraint("SIG2SRAM_constraint_template") { + index_1("0.0040,0.0176,0.0344,0.0656,0.1120,0.2016,0.3800"); + index_2("0.0040,0.0176,0.0344,0.0656,0.1120,0.2016,0.3800"); + values ("0.1770,0.1652,0.1496,0.1223,0.0793,0.0090,-0.1316",\ +"0.1848,0.1730,0.1574,0.1301,0.0910,0.0168,-0.1199",\ +"0.2004,0.1887,0.1770,0.1496,0.1066,0.0363,-0.1043",\ +"0.2277,0.2160,0.2004,0.1730,0.1340,0.0598,-0.0809",\ +"0.2668,0.2551,0.2395,0.2121,0.1730,0.0988,-0.0418",\ +"0.3410,0.3293,0.3137,0.2863,0.2434,0.1730,0.0324",\ +"0.4816,0.4699,0.4543,0.4230,0.3801,0.3098,0.1730"); + } + + fall_constraint("SIG2SRAM_constraint_template") { + index_1("0.0040,0.0176,0.0344,0.0656,0.1120,0.2016,0.3800"); + index_2("0.0040,0.0176,0.0344,0.0656,0.1120,0.2016,0.3800"); + values ("0.1613,0.1496,0.1379,0.1066,0.0715,0.0012,-0.1355",\ +"0.1730,0.1613,0.1457,0.1184,0.0832,0.0129,-0.1238",\ +"0.1887,0.1770,0.1613,0.1340,0.0988,0.0246,-0.1121",\ +"0.2121,0.2043,0.1887,0.1613,0.1223,0.0520,-0.0848",\ +"0.2512,0.2434,0.2277,0.2004,0.1613,0.0910,-0.0457",\ +"0.3254,0.3176,0.3020,0.2746,0.2355,0.1652,0.0324",\ +"0.4660,0.4543,0.4387,0.4113,0.3723,0.3020,0.1691"); + } + } + } +pin(A_BIST_REN) { + direction : input ; + capacitance : 0.00390661 ; + max_transition : "0.38" ; + related_power_pin : VDD; + related_ground_pin : VSS; + internal_power() { + when : "A_BIST_MEN"; + rise_power("scalar"){ + values (0.0122); + } + fall_power("scalar"){ + values (0.0105); + } + } + internal_power() { + when : "!A_BIST_MEN"; + rise_power("scalar"){ + values (0.0181); + } + fall_power("scalar"){ + values (0.0202); + } + } + timing() { + timing_type : setup_rising; + related_pin : "A_BIST_CLK"; + when : "A_BIST_MEN" + sdf_cond : "A_BIST_MEN" + + rise_constraint("SIG2SRAM_constraint_template") { + index_1("0.0040,0.0176,0.0344,0.0656,0.1120,0.2016,0.3800"); + index_2("0.0040,0.0176,0.0344,0.0656,0.1120,0.2016,0.3800"); + values ("-0.0027,0.0090,0.0246,0.0520,0.0910,0.1613,0.3020",\ +"-0.0105,0.0012,0.0129,0.0363,0.0793,0.1535,0.2902",\ +"-0.0262,-0.0145,-0.0027,0.0246,0.0637,0.1379,0.2785",\ +"-0.0535,-0.0418,-0.0262,0.0012,0.0363,0.1105,0.2512",\ +"-0.0926,-0.0809,-0.0652,-0.0418,-0.0027,0.0715,0.2121",\ +"-0.1668,-0.1551,-0.1395,-0.1082,-0.0770,-0.0027,0.1379",\ +"-0.3035,-0.2918,-0.2762,-0.2488,-0.2137,-0.1434,-0.0027"); + } + + fall_constraint("SIG2SRAM_constraint_template") { + index_1("0.0040,0.0176,0.0344,0.0656,0.1120,0.2016,0.3800"); + index_2("0.0040,0.0176,0.0344,0.0656,0.1120,0.2016,0.3800"); + values ("0.0832,0.0949,0.1105,0.1379,0.1730,0.2473,0.3801",\ +"0.0754,0.0832,0.0988,0.1223,0.1613,0.2355,0.3684",\ +"0.0598,0.0676,0.0832,0.1066,0.1457,0.2121,0.3527",\ +"0.0324,0.0441,0.0598,0.0871,0.1223,0.1926,0.3293",\ +"-0.0066,0.0051,0.0168,0.0480,0.0832,0.1535,0.2902",\ +"-0.0809,-0.0691,-0.0574,-0.0301,0.0090,0.0832,0.2121",\ +"-0.2176,-0.2059,-0.1941,-0.1668,-0.1277,-0.0574,0.0793"); + } + } + + + timing() { + timing_type : hold_rising; + related_pin : "A_BIST_CLK"; + when : "A_BIST_MEN" + sdf_cond : "A_BIST_MEN" + + rise_constraint("SIG2SRAM_constraint_template") { + index_1("0.0040,0.0176,0.0344,0.0656,0.1120,0.2016,0.3800"); + index_2("0.0040,0.0176,0.0344,0.0656,0.1120,0.2016,0.3800"); + values ("0.1887,0.1770,0.1613,0.1340,0.0949,0.0207,-0.1160",\ +"0.1965,0.1848,0.1730,0.1457,0.1027,0.0324,-0.1082",\ +"0.2160,0.2004,0.1887,0.1613,0.1184,0.0480,-0.0926",\ +"0.2395,0.2277,0.2121,0.1848,0.1457,0.0715,-0.0652",\ +"0.2785,0.2668,0.2512,0.2238,0.1848,0.1105,-0.0262",\ +"0.3527,0.3410,0.3254,0.2980,0.2551,0.1848,0.0480",\ +"0.4934,0.4816,0.4660,0.4387,0.3957,0.3254,0.1887"); + } + + fall_constraint("SIG2SRAM_constraint_template") { + index_1("0.0040,0.0176,0.0344,0.0656,0.1120,0.2016,0.3800"); + index_2("0.0040,0.0176,0.0344,0.0656,0.1120,0.2016,0.3800"); + values ("0.1730,0.1613,0.1496,0.1184,0.0793,0.0129,-0.1238",\ +"0.1848,0.1730,0.1574,0.1301,0.0910,0.0207,-0.1121",\ +"0.2004,0.1887,0.1730,0.1457,0.1066,0.0363,-0.1004",\ +"0.2238,0.2121,0.2004,0.1691,0.1340,0.0598,-0.0730",\ +"0.2629,0.2512,0.2395,0.2121,0.1691,0.0988,-0.0340",\ +"0.3371,0.3254,0.3137,0.2863,0.2434,0.1730,0.0402",\ +"0.4777,0.4660,0.4504,0.4230,0.3840,0.3137,0.1809"); + } + } + } +pin(A_BIST_MEN) { + direction : input ; + capacitance : 0.00326046 ; + max_transition : "0.38" ; + related_power_pin : VDD; + related_ground_pin : VSS; + internal_power() { + rise_power("scalar"){ + values (0.2714); + } + fall_power("scalar"){ + values (0.0108); + } + } + timing() { + timing_type : setup_rising; + related_pin : "A_BIST_CLK"; + + rise_constraint("SIG2SRAM_constraint_template") { + index_1("0.0040,0.0176,0.0344,0.0656,0.1120,0.2016,0.3800"); + index_2("0.0040,0.0176,0.0344,0.0656,0.1120,0.2016,0.3800"); + values ("0.1418,0.1496,0.1652,0.1926,0.2316,0.3059,0.4465",\ +"0.1301,0.1379,0.1535,0.1809,0.2199,0.2941,0.4348",\ +"0.1145,0.1262,0.1418,0.1652,0.2043,0.2785,0.4191",\ +"0.0871,0.0949,0.1105,0.1379,0.1770,0.2512,0.3879",\ +"0.0480,0.0598,0.0754,0.0988,0.1379,0.2082,0.3488",\ +"-0.0262,-0.0145,0.0012,0.0285,0.0676,0.1379,0.2785",\ +"-0.1668,-0.1551,-0.1395,-0.1121,-0.0730,0.0012,0.1379"); + } + + fall_constraint("SIG2SRAM_constraint_template") { + index_1("0.0040,0.0176,0.0344,0.0656,0.1120,0.2016,0.3800"); + index_2("0.0040,0.0176,0.0344,0.0656,0.1120,0.2016,0.3800"); + values ("0.2082,0.2199,0.2316,0.2590,0.2980,0.3723,0.5051",\ +"0.1965,0.2082,0.2199,0.2473,0.2863,0.3605,0.4934",\ +"0.1809,0.1926,0.2043,0.2316,0.2707,0.3449,0.4777",\ +"0.1574,0.1691,0.1809,0.2082,0.2434,0.3176,0.4543",\ +"0.1145,0.1262,0.1418,0.1691,0.2043,0.2785,0.4113",\ +"0.0441,0.0559,0.0676,0.0949,0.1301,0.2004,0.3332",\ +"-0.0965,-0.0848,-0.0691,-0.0418,-0.0066,0.0676,0.2004"); + } + } + + + timing() { + timing_type : hold_rising; + related_pin : "A_BIST_CLK"; + + rise_constraint("SIG2SRAM_constraint_template") { + index_1("0.0040,0.0176,0.0344,0.0656,0.1120,0.2016,0.3800"); + index_2("0.0040,0.0176,0.0344,0.0656,0.1120,0.2016,0.3800"); + values ("0.1770,0.1652,0.1535,0.1262,0.0832,0.0129,-0.1277",\ +"0.1887,0.1770,0.1613,0.1340,0.0949,0.0207,-0.1199",\ +"0.2043,0.1926,0.1770,0.1496,0.1105,0.0363,-0.1043",\ +"0.2277,0.2160,0.2043,0.1770,0.1379,0.0598,-0.0770",\ +"0.2668,0.2551,0.2434,0.2160,0.1730,0.0988,-0.0379",\ +"0.3449,0.3332,0.3176,0.2902,0.2473,0.1730,0.0363",\ +"0.4816,0.4699,0.4543,0.4270,0.3840,0.3098,0.1770"); + } + + fall_constraint("SIG2SRAM_constraint_template") { + index_1("0.0040,0.0176,0.0344,0.0656,0.1120,0.2016,0.3800"); + index_2("0.0040,0.0176,0.0344,0.0656,0.1120,0.2016,0.3800"); + values ("0.1613,0.1496,0.1379,0.1105,0.0715,0.0012,-0.1355",\ +"0.1730,0.1613,0.1496,0.1184,0.0832,0.0129,-0.1238",\ +"0.1887,0.1770,0.1652,0.1340,0.0988,0.0285,-0.1121",\ +"0.2121,0.2043,0.1887,0.1613,0.1223,0.0520,-0.0848",\ +"0.2551,0.2434,0.2277,0.2004,0.1613,0.0910,-0.0418",\ +"0.3293,0.3176,0.3020,0.2746,0.2395,0.1652,0.0324",\ +"0.4660,0.4543,0.4426,0.4113,0.3762,0.3020,0.1691"); + } + } + } +bus(A_BIST_BM) { + bus_type : D_31_0; + direction : input ; + capacitance : 0.00253457 ; + max_transition : "0.38" ; + pin(A_BIST_BM[31:0]) { + related_power_pin : VDD; + related_ground_pin : VSS; + internal_power() { + when : "A_BIST_MEN"; + rise_power("scalar"){ + values (0.1809); + } + fall_power("scalar"){ + values (0.1563); + } + } + internal_power() { + when : "!A_BIST_MEN"; + rise_power("scalar"){ + values (0.1509); + } + fall_power("scalar"){ + values (0.1509); + } + } + } + timing() { + timing_type : setup_rising; + related_pin : "A_BIST_CLK"; + when : "(A_BIST_WEN & A_BIST_MEN)" + sdf_cond : "A_BIST_RW_ACCESS" + + rise_constraint("SIG2SRAM_constraint_template") { + index_1("0.0040,0.0176,0.0344,0.0656,0.1120,0.2016,0.3800"); + index_2("0.0040,0.0176,0.0344,0.0656,0.1120,0.2016,0.3800"); + values ("-0.2520,-0.2412,-0.2256,-0.1993,-0.1592,-0.0889,0.0459",\ +"-0.2559,-0.2451,-0.2295,-0.2031,-0.1631,-0.0928,0.0420",\ +"-0.2596,-0.2488,-0.2332,-0.2068,-0.1668,-0.0965,0.0383",\ +"-0.2628,-0.2520,-0.2364,-0.2100,-0.1700,-0.0997,0.0351",\ +"-0.2754,-0.2646,-0.2490,-0.2226,-0.1826,-0.1123,0.0225",\ +"-0.2930,-0.2822,-0.2666,-0.2402,-0.2002,-0.1299,0.0049",\ +"-0.3205,-0.3097,-0.2941,-0.2678,-0.2277,-0.1574,-0.0226"); + } + + fall_constraint("SIG2SRAM_constraint_template") { + index_1("0.0040,0.0176,0.0344,0.0656,0.1120,0.2016,0.3800"); + index_2("0.0040,0.0176,0.0344,0.0656,0.1120,0.2016,0.3800"); + values ("-0.2295,-0.2188,-0.2051,-0.1778,-0.1407,-0.0684,0.0615",\ +"-0.2334,-0.2227,-0.2090,-0.1817,-0.1445,-0.0723,0.0576",\ +"-0.2371,-0.2264,-0.2127,-0.1853,-0.1482,-0.0760,0.0539",\ +"-0.2403,-0.2295,-0.2159,-0.1885,-0.1514,-0.0792,0.0507",\ +"-0.2529,-0.2422,-0.2285,-0.2012,-0.1641,-0.0918,0.0381",\ +"-0.2705,-0.2598,-0.2461,-0.2188,-0.1817,-0.1094,0.0205",\ +"-0.2980,-0.2873,-0.2736,-0.2463,-0.2092,-0.1369,-0.0070"); + } + } + + + timing() { + timing_type : hold_rising; + related_pin : "A_BIST_CLK"; + when : "(A_BIST_WEN & A_BIST_MEN)" + sdf_cond : "A_BIST_RW_ACCESS" + + rise_constraint("SIG2SRAM_constraint_template") { + index_1("0.0040,0.0176,0.0344,0.0656,0.1120,0.2016,0.3800"); + index_2("0.0040,0.0176,0.0344,0.0656,0.1120,0.2016,0.3800"); + values ("0.3581,0.3463,0.3317,0.3053,0.2653,0.1940,0.0573",\ +"0.3619,0.3502,0.3356,0.3092,0.2692,0.1979,0.0612",\ +"0.3656,0.3539,0.3393,0.3129,0.2728,0.2016,0.0648",\ +"0.3688,0.3571,0.3425,0.3161,0.2760,0.2048,0.0680",\ +"0.3814,0.3697,0.3551,0.3287,0.2887,0.2174,0.0807",\ +"0.3990,0.3873,0.3727,0.3463,0.3063,0.2350,0.0983",\ +"0.4266,0.4148,0.4002,0.3738,0.3338,0.2625,0.1258"); + } + + fall_constraint("SIG2SRAM_constraint_template") { + index_1("0.0040,0.0176,0.0344,0.0656,0.1120,0.2016,0.3800"); + index_2("0.0040,0.0176,0.0344,0.0656,0.1120,0.2016,0.3800"); + values ("0.3297,0.3200,0.3053,0.2790,0.2418,0.1686,0.0407",\ +"0.3336,0.3239,0.3092,0.2828,0.2457,0.1725,0.0446",\ +"0.3373,0.3275,0.3129,0.2865,0.2494,0.1762,0.0482",\ +"0.3405,0.3307,0.3161,0.2897,0.2526,0.1794,0.0514",\ +"0.3531,0.3434,0.3287,0.3023,0.2652,0.1920,0.0641",\ +"0.3707,0.3610,0.3463,0.3199,0.2828,0.2096,0.0817",\ +"0.3982,0.3885,0.3738,0.3475,0.3103,0.2371,0.1092"); + } + } +} + pin(A_BIST_CLK) { + direction : input; + capacitance : 0.00389386; + max_transition : "0.38"; + clock : "true" ; + pin_func_type : active_rising ; + + timing () { + timing_type : "min_pulse_width"; + related_pin : "A_BIST_CLK"; + rise_constraint("CLKTRAN_constraint_template") { + index_1("0.004,0.38"); + values("0.12,0.12"); + } + } + + related_power_pin : VDD; + related_ground_pin : VSS; + + internal_power() { + when : "!A_BIST_MEN & !A_BIST_WEN & !A_BIST_REN"; + rise_power("scalar"){ + values (0); + } + fall_power("scalar"){ + values (0); + } + } + internal_power() { + when : "!A_BIST_MEN & A_BIST_WEN & !A_BIST_REN"; + rise_power("scalar"){ + values (0.6783); + } + fall_power("scalar"){ + values (0); + } + } + internal_power() { + when : "A_BIST_MEN & A_BIST_WEN & !A_BIST_REN"; + rise_power("scalar"){ + values (41.2558); + } + fall_power("scalar"){ + values (0); + } + } + internal_power() { + when : "A_BIST_MEN & A_BIST_WEN & A_BIST_REN"; + rise_power("scalar"){ + values (46.5325); + } + fall_power("scalar"){ + values (0); + } + } + internal_power() { + when : "A_BIST_MEN & !A_BIST_WEN & A_BIST_REN"; + rise_power("scalar"){ + values (34.0312); + } + fall_power("scalar"){ + values (0); + } + } + internal_power() { + when : "!A_BIST_MEN & !A_BIST_WEN & A_BIST_REN"; + rise_power("scalar"){ + values (0.4087); + } + fall_power("scalar"){ + values (0); + } + } + internal_power() { + when : "!A_BIST_MEN & A_BIST_WEN & A_BIST_REN"; + rise_power("scalar"){ + values (1.3353); + } + fall_power("scalar"){ + values (0); + } + } + internal_power() { + when : "A_BIST_MEN & !A_BIST_WEN & !A_BIST_REN"; + rise_power("scalar"){ + values (0); + } + fall_power("scalar"){ + values (0); + } + } + } + bus(A_BIST_DIN) { + bus_type : D_31_0; + direction : input ; + capacitance : 0.00252927 ; + memory_write() { + address : A_BIST_ADDR ; + clocked_on : A_BIST_CLK; + } + + max_transition : "0.38" ; + pin(A_BIST_DIN[31:0]) { + related_power_pin : VDD; + related_ground_pin : VSS; + internal_power() { + when : "A_BIST_MEN"; + rise_power("scalar"){ + values (0.1809); + } + fall_power("scalar"){ + values (0.1563); + } + } + internal_power() { + when : "!A_BIST_MEN"; + rise_power("scalar"){ + values (0.1509); + } + fall_power("scalar"){ + values (0.1509); + } + } + } + timing() { + timing_type : setup_rising; + related_pin : "A_BIST_CLK"; + when : "(A_BIST_WEN & A_BIST_MEN)"; + sdf_cond : "A_BIST_W_ACCESS"; + + rise_constraint("SIG2SRAM_constraint_template") { + index_1("0.0040,0.0176,0.0344,0.0656,0.1120,0.2016,0.3800"); + index_2("0.0040,0.0176,0.0344,0.0656,0.1120,0.2016,0.3800"); + values ("-0.2520,-0.2412,-0.2256,-0.1993,-0.1592,-0.0889,0.0459",\ +"-0.2559,-0.2451,-0.2295,-0.2031,-0.1631,-0.0928,0.0420",\ +"-0.2596,-0.2488,-0.2332,-0.2068,-0.1668,-0.0965,0.0383",\ +"-0.2628,-0.2520,-0.2364,-0.2100,-0.1700,-0.0997,0.0351",\ +"-0.2754,-0.2646,-0.2490,-0.2226,-0.1826,-0.1123,0.0225",\ +"-0.2930,-0.2822,-0.2666,-0.2402,-0.2002,-0.1299,0.0049",\ +"-0.3205,-0.3097,-0.2941,-0.2678,-0.2277,-0.1574,-0.0226"); + } + + fall_constraint("SIG2SRAM_constraint_template") { + index_1("0.0040,0.0176,0.0344,0.0656,0.1120,0.2016,0.3800"); + index_2("0.0040,0.0176,0.0344,0.0656,0.1120,0.2016,0.3800"); + values ("-0.2295,-0.2188,-0.2051,-0.1778,-0.1407,-0.0684,0.0615",\ +"-0.2334,-0.2227,-0.2090,-0.1817,-0.1445,-0.0723,0.0576",\ +"-0.2371,-0.2264,-0.2127,-0.1853,-0.1482,-0.0760,0.0539",\ +"-0.2403,-0.2295,-0.2159,-0.1885,-0.1514,-0.0792,0.0507",\ +"-0.2529,-0.2422,-0.2285,-0.2012,-0.1641,-0.0918,0.0381",\ +"-0.2705,-0.2598,-0.2461,-0.2188,-0.1817,-0.1094,0.0205",\ +"-0.2980,-0.2873,-0.2736,-0.2463,-0.2092,-0.1369,-0.0070"); + } + } + + timing() { + timing_type : hold_rising; + related_pin : "A_BIST_CLK"; + when : "(A_BIST_WEN & A_BIST_MEN)"; + sdf_cond : "A_BIST_W_ACCESS"; + + rise_constraint("SIG2SRAM_constraint_template") { + index_1("0.0040,0.0176,0.0344,0.0656,0.1120,0.2016,0.3800"); + index_2("0.0040,0.0176,0.0344,0.0656,0.1120,0.2016,0.3800"); + values ("0.3581,0.3463,0.3317,0.3053,0.2653,0.1940,0.0573",\ +"0.3619,0.3502,0.3356,0.3092,0.2692,0.1979,0.0612",\ +"0.3656,0.3539,0.3393,0.3129,0.2728,0.2016,0.0648",\ +"0.3688,0.3571,0.3425,0.3161,0.2760,0.2048,0.0680",\ +"0.3814,0.3697,0.3551,0.3287,0.2887,0.2174,0.0807",\ +"0.3990,0.3873,0.3727,0.3463,0.3063,0.2350,0.0983",\ +"0.4266,0.4148,0.4002,0.3738,0.3338,0.2625,0.1258"); + } + + fall_constraint("SIG2SRAM_constraint_template") { + index_1("0.0040,0.0176,0.0344,0.0656,0.1120,0.2016,0.3800"); + index_2("0.0040,0.0176,0.0344,0.0656,0.1120,0.2016,0.3800"); + values ("0.3297,0.3200,0.3053,0.2790,0.2418,0.1686,0.0407",\ +"0.3336,0.3239,0.3092,0.2828,0.2457,0.1725,0.0446",\ +"0.3373,0.3275,0.3129,0.2865,0.2494,0.1762,0.0482",\ +"0.3405,0.3307,0.3161,0.2897,0.2526,0.1794,0.0514",\ +"0.3531,0.3434,0.3287,0.3023,0.2652,0.1920,0.0641",\ +"0.3707,0.3610,0.3463,0.3199,0.2828,0.2096,0.0817",\ +"0.3982,0.3885,0.3738,0.3475,0.3103,0.2371,0.1092"); + } + } + } + +bus(A_DOUT) { + + bus_type : D_31_0; + direction : output ; + capacitance : 0 ; + max_capacitance : 0.064 ; + memory_read() { + address : A_ADDR ; + } + pin(A_DOUT[31:0]) { + related_power_pin : VDD; + related_ground_pin : VSS; + internal_power() { + rise_power("scalar") { + values (0); + } + fall_power("scalar") { + values (0); + } + } + } + timing() { + related_pin : "A_CLK"; + timing_type : rising_edge ; + timing_sense : non_unate ; + + cell_rise(SIG2SRAM_delay_template) { + index_1("0.0040,0.0176,0.0344,0.0656,0.1120,0.2016,0.3800"); + index_2("0.0008,0.0014,0.0051,0.0100,0.0339,0.0640"); + values ("1.8757,1.8768,1.8816,1.8871,1.9080,1.9315",\ +"1.8817,1.8827,1.8875,1.8930,1.9139,1.9374",\ +"1.8844,1.8855,1.8903,1.8958,1.9167,1.9402",\ +"1.8887,1.8897,1.8945,1.9000,1.9209,1.9444",\ +"1.9003,1.9013,1.9061,1.9116,1.9325,1.9560",\ +"1.9194,1.9204,1.9252,1.9307,1.9516,1.9751",\ +"1.9458,1.9468,1.9516,1.9571,1.9780,2.0015"); + } + cell_fall(SIG2SRAM_delay_template) { + index_1("0.0040,0.0176,0.0344,0.0656,0.1120,0.2016,0.3800"); + index_2("0.0008,0.0014,0.0051,0.0100,0.0339,0.0640"); + values ("1.8415,1.8423,1.8464,1.8509,1.8680,1.8847",\ +"1.8474,1.8483,1.8523,1.8568,1.8739,1.8907",\ +"1.8502,1.8510,1.8551,1.8596,1.8767,1.8934",\ +"1.8544,1.8552,1.8593,1.8638,1.8809,1.8976",\ +"1.8660,1.8668,1.8709,1.8754,1.8925,1.9092",\ +"1.8851,1.8859,1.8900,1.8945,1.9116,1.9283",\ +"1.9115,1.9123,1.9164,1.9209,1.9380,1.9547"); + } + + rise_transition(SRAM_load_template) { + index_1("0.0008,0.0014,0.0051,0.0100,0.0339,0.0640"); + values ("0.0206,0.0210,0.0265,0.0323,0.0606,0.0955"); + } + fall_transition(SRAM_load_template) { + index_1("0.0008,0.0014,0.0051,0.0100,0.0339,0.0640"); + values ("0.0170,0.0177,0.0222,0.0270,0.0451,0.0644"); + } + } +} +cell_leakage_power : 234.7971; +} +} diff --git a/flow/platforms/ihp-sg13g2/lib/RM_IHPSG13_1P_256x32_c2_bm_bist_slow_1p08V_125C.lib b/flow/platforms/ihp-sg13g2/lib/RM_IHPSG13_1P_256x32_c2_bm_bist_slow_1p08V_125C.lib new file mode 100644 index 0000000000..3f763c6c58 --- /dev/null +++ b/flow/platforms/ihp-sg13g2/lib/RM_IHPSG13_1P_256x32_c2_bm_bist_slow_1p08V_125C.lib @@ -0,0 +1,1513 @@ +/* ------------------------------------------------------*/ +/**/ +/* Copyright 2025 IHP PDK Authors*/ +/**/ +/* Licensed under the Apache License, Version 2.0 (the "License");*/ +/* you may not use this file except in compliance with the License.*/ +/* You may obtain a copy of the License at*/ +/* */ +/* https://www.apache.org/licenses/LICENSE-2.0*/ +/* */ +/* Unless required by applicable law or agreed to in writing, software*/ +/* distributed under the License is distributed on an "AS IS" BASIS,*/ +/* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.*/ +/* See the License for the specific language governing permissions and*/ +/* limitations under the License.*/ +/* */ +/* Generated on Thu Aug 21 20:49:07 2025 */ +/* */ +/* ------------------------------------------------------ */ +library(RM_IHPSG13_1P_256x32_c2_bm_bist_slow_1p08V_125C) { + technology (cmos) ; + delay_model : table_lookup ; + define ("add_pg_pin_to_lib", "library", "boolean"); + add_pg_pin_to_lib : true; + voltage_map ( VDD, 1.08); + voltage_map ( VDDARRAY, 1.08); + voltage_map ( VSS, 0.000000 ); + + date : "Thu Aug 21 20:49:06 2025" ; + comment : "IHP Microelectronics GmbH, 2023" ; + revision : 1.0.0 ; + simulation : true ; + nom_process : 1 ; + nom_temperature : 125 ; + nom_voltage : 1.08 ; + + operating_conditions("slow_1p08V_125C"){ + process : 1 ; + temperature : 125 ; + voltage : 1.08 ; + tree_type : "balanced_tree" ; + } + + default_operating_conditions : slow_1p08V_125C ; + default_max_transition : 1.0 ; + default_fanout_load : 1.0 ; + default_inout_pin_cap : 0.0 ; + default_input_pin_cap : 0.0 ; + default_output_pin_cap : 0.0 ; + default_cell_leakage_power : 0.0 ; + default_leakage_power_density : 0.0 ; + + slew_lower_threshold_pct_rise : 30 ; + slew_upper_threshold_pct_rise : 70 ; + input_threshold_pct_fall : 50 ; + output_threshold_pct_fall : 50 ; + input_threshold_pct_rise : 50 ; + output_threshold_pct_rise : 50 ; + slew_lower_threshold_pct_fall : 30 ; + slew_upper_threshold_pct_fall : 70 ; + slew_derate_from_library : 0.5; + k_volt_cell_leakage_power : 0.0 ; + k_temp_cell_leakage_power : 0.0 ; + k_process_cell_leakage_power : 0.0 ; + k_volt_internal_power : 0.0 ; + k_temp_internal_power : 0.0 ; + k_process_internal_power : 0.0 ; + + capacitive_load_unit (1,pf) ; + voltage_unit : "1V" ; + current_unit : "1uA" ; + time_unit : "1ns" ; + leakage_power_unit : "1nW" ; + pulling_resistance_unit : "1kohm"; + /* + ------------------------------------------------------------------------------------------ + implicit units overview: + cell_area unit : "um" + internal_power unit : "1e-12 * J/toggle = 1 * uW/MHz" + (capacitive_load_unit * voltage_unit^2) per toggle event + ------------------------------------------------------------------------------------------ + */ + library_features(report_delay_calculation); + define_cell_area (pad_drivers,pad_driver_sites) ; + + lu_table_template(CLKTRAN_constraint_template) { + variable_1 : constrained_pin_transition; + index_1 ( "0.010, 0.050, 0.200, 0.400, 1.000" ); + } + lu_table_template(SRAM_load_template) { + variable_1 : total_output_net_capacitance; + index_1 ( "0.0008,0.0014,0.0051,0.0100,0.0339,0.0640" ); + } + lu_table_template(SIG2SRAM_constraint_template) { + variable_1 : related_pin_transition; + variable_2 : constrained_pin_transition; + index_1 ( "0.0080,0.0288,0.0616,0.1072,0.1920,0.3496,0.5952" ); + index_2 ( "0.0080,0.0288,0.0616,0.1072,0.1920,0.3496,0.5952" ); + } + + lu_table_template(SIG2SRAM_delay_template) { + variable_1 : input_net_transition; + variable_2 : total_output_net_capacitance; + index_1 ( "0.0080,0.0288,0.0616,0.1072,0.1920,0.3496,0.5952" ); + index_2 ( "0.0008,0.0014,0.0051,0.0100,0.0339,0.0640" ); + } + + type (D_31_0) { + base_type : array; + data_type : bit; + bit_width : 32; + bit_from : 31; + bit_to : 0; + downto : true; + } + + type (A_7_0) { + base_type : array; + data_type : bit; + bit_width : 8; + bit_from : 7; + bit_to : 0; + downto : true; + } + +cell(RM_IHPSG13_1P_256x32_c2_bm_bist) { +pg_pin (VDD) { + pg_type : primary_power; + voltage_name : VDD; +} +pg_pin (VDDARRAY) { + pg_type : primary_power; + voltage_name : VDDARRAY; +} +pg_pin (VSS) { + pg_type : primary_ground; + voltage_name : VSS; +} + +memory() { + type : ram; + address_width : 8; + word_width : 32; +} + +interface_timing : false; +bus_naming_style : "%s[%d]" ; +area : 49488.4992 ; + + pin(A_DLY) { + direction : input ; + capacitance : 0.00387999 ; + max_transition : "1" ; + related_power_pin : VDD; + related_ground_pin : VSS; + internal_power() { + rise_power("scalar") { + values (0); + } + fall_power("scalar") { + values (0); + } + } + } + +bus(A_ADDR) { + bus_type : A_7_0; + direction : input ; + capacitance : 0.0077013 ; + pin(A_ADDR[0]) { + capacitance : 0.00625349 ; + } + pin(A_ADDR[1]) { + capacitance : 0.00507435 ; + } + pin(A_ADDR[2]) { + capacitance : 0.00656707 ; + } + pin(A_ADDR[3]) { + capacitance : 0.0083133 ; + } + pin(A_ADDR[4]) { + capacitance : 0.00507219 ; + } + pin(A_ADDR[5]) { + capacitance : 0.00964344 ; + } + pin(A_ADDR[6]) { + capacitance : 0.0119653 ; + } + max_transition : "0.5952" ; + pin(A_ADDR[7:0]) { + related_power_pin : VDD; + related_ground_pin : VSS; + internal_power() { + when : "A_MEN"; + rise_power("scalar"){ + values (0.0097); + } + fall_power("scalar"){ + values (0.0074); + } + } + internal_power() { + when : "!A_MEN"; + rise_power("scalar"){ + values (0.0163); + } + fall_power("scalar"){ + values (0.0021); + } + } + } + timing() { + timing_type : setup_rising; + related_pin : "A_CLK"; + when : "((A_WEN | A_REN)& A_MEN)" + sdf_cond : "A_RW_ACCESS" + + rise_constraint("SIG2SRAM_constraint_template") { + index_1("0.0080,0.0288,0.0616,0.1072,0.1920,0.3496,0.5952"); + index_2("0.0080,0.0288,0.0616,0.1072,0.1920,0.3496,0.5952"); + values ("-0.7371,-0.7176,-0.6863,-0.6434,-0.5652,-0.4168,-0.1980",\ +"-0.7566,-0.7371,-0.7059,-0.6629,-0.5848,-0.4363,-0.2137",\ +"-0.7879,-0.7645,-0.7332,-0.6902,-0.6121,-0.4637,-0.2449",\ +"-0.8309,-0.8074,-0.7762,-0.7332,-0.6551,-0.5066,-0.2879",\ +"-0.9051,-0.8895,-0.8543,-0.8113,-0.7332,-0.5887,-0.3660",\ +"-1.0418,-1.0262,-0.9949,-0.9480,-0.8699,-0.7293,-0.5027",\ +"-1.2684,-1.2449,-1.2176,-1.1707,-1.0965,-0.9480,-0.7293"); + } + + fall_constraint("SIG2SRAM_constraint_template") { + index_1("0.0080,0.0288,0.0616,0.1072,0.1920,0.3496,0.5952"); + index_2("0.0080,0.0288,0.0616,0.1072,0.1920,0.3496,0.5952"); + values ("-0.5926,-0.5730,-0.5418,-0.4988,-0.4246,-0.2879,-0.0730",\ +"-0.6121,-0.5926,-0.5613,-0.5223,-0.4441,-0.3074,-0.0887",\ +"-0.6395,-0.6199,-0.5926,-0.5496,-0.4715,-0.3348,-0.1160",\ +"-0.6863,-0.6668,-0.6355,-0.5965,-0.5184,-0.3777,-0.1590",\ +"-0.7605,-0.7410,-0.7137,-0.6746,-0.5926,-0.4559,-0.2410",\ +"-0.9012,-0.8816,-0.8504,-0.8113,-0.7332,-0.5926,-0.3895",\ +"-1.1238,-1.1043,-1.0769,-1.0379,-0.9559,-0.8191,-0.6004"); + } + } + + + timing() { + timing_type : hold_rising; + related_pin : "A_CLK"; + when : "((A_WEN | A_REN)& A_MEN)" + sdf_cond : "A_RW_ACCESS" + + rise_constraint("SIG2SRAM_constraint_template") { + index_1("0.0080,0.0288,0.0616,0.1072,0.1920,0.3496,0.5952"); + index_2("0.0080,0.0288,0.0616,0.1072,0.1920,0.3496,0.5952"); + values ("0.8488,0.8293,0.7980,0.7551,0.6730,0.5285,0.3059",\ +"0.8684,0.8488,0.8176,0.7746,0.6926,0.5480,0.3254",\ +"0.8996,0.8801,0.8449,0.8020,0.7238,0.5754,0.3527",\ +"0.9426,0.9191,0.8918,0.8488,0.7668,0.6223,0.3996",\ +"1.0168,1.0012,0.9699,0.9230,0.8449,0.7004,0.4777",\ +"1.1574,1.1379,1.1105,1.0598,0.9816,0.8371,0.6184",\ +"1.3801,1.3605,1.3254,1.2980,1.2043,1.0637,0.8371"); + } + + fall_constraint("SIG2SRAM_constraint_template") { + index_1("0.0080,0.0288,0.0616,0.1072,0.1920,0.3496,0.5952"); + index_2("0.0080,0.0288,0.0616,0.1072,0.1920,0.3496,0.5952"); + values ("0.6965,0.6770,0.6496,0.6066,0.5246,0.3918,0.1730",\ +"0.7160,0.6965,0.6652,0.6262,0.5441,0.4113,0.1965",\ +"0.7473,0.7277,0.6965,0.6535,0.5754,0.4426,0.2238",\ +"0.7863,0.7707,0.7395,0.7004,0.6223,0.4855,0.2629",\ +"0.8684,0.8449,0.8176,0.7785,0.7004,0.5637,0.3449",\ +"1.0051,0.9855,0.9855,0.9113,0.8332,0.7004,0.4895",\ +"1.2277,1.2082,1.1809,1.1379,1.0598,0.9230,0.7004"); + } + } +} +pin(A_WEN) { + direction : input ; + capacitance : 0.00313551 ; + max_transition : "0.5952" ; + related_power_pin : VDD; + related_ground_pin : VSS; + internal_power() { + when : "A_MEN"; + rise_power("scalar"){ + values (0.0036); + } + fall_power("scalar"){ + values (0.0005); + } + } + internal_power() { + when : "!A_MEN"; + rise_power("scalar"){ + values (0.0052); + } + fall_power("scalar"){ + values (0.0001); + } + } + timing() { + timing_type : setup_rising; + related_pin : "A_CLK"; + when : "A_MEN" + sdf_cond : "A_MEN" + + rise_constraint("SIG2SRAM_constraint_template") { + index_1("0.0080,0.0288,0.0616,0.1072,0.1920,0.3496,0.5952"); + index_2("0.0080,0.0288,0.0616,0.1072,0.1920,0.3496,0.5952"); + values ("0.3137,0.3332,0.3605,0.4035,0.4816,0.6223,0.8488",\ +"0.2980,0.3176,0.3410,0.3840,0.4660,0.6027,0.8293",\ +"0.2629,0.2824,0.3098,0.3527,0.4348,0.5754,0.7980",\ +"0.2199,0.2395,0.2668,0.3098,0.3918,0.5324,0.7590",\ +"0.1418,0.1613,0.1887,0.2316,0.3137,0.4348,0.6730",\ +"0.0012,0.0207,0.0520,0.0910,0.1730,0.3098,0.5285",\ +"-0.2215,-0.2020,-0.1746,-0.1277,-0.0496,0.0910,0.3098"); + } + + fall_constraint("SIG2SRAM_constraint_template") { + index_1("0.0080,0.0288,0.0616,0.1072,0.1920,0.3496,0.5952"); + index_2("0.0080,0.0288,0.0616,0.1072,0.1920,0.3496,0.5952"); + values ("0.4504,0.4699,0.4973,0.5324,0.6027,0.7355,0.9699",\ +"0.4309,0.4504,0.4777,0.5129,0.5910,0.7160,0.9504",\ +"0.3996,0.4191,0.4465,0.4816,0.5520,0.6848,0.9191",\ +"0.3605,0.3762,0.4035,0.4387,0.5168,0.6418,0.8723",\ +"0.2785,0.2980,0.3215,0.3605,0.4348,0.5637,0.7980",\ +"0.1379,0.1574,0.1809,0.2199,0.2980,0.4309,0.6457",\ +"-0.0809,-0.0613,-0.0340,0.0051,0.0832,0.2160,0.4191"); + } + } + + + timing() { + timing_type : hold_rising; + related_pin : "A_CLK"; + when : "A_MEN" + sdf_cond : "A_MEN" + + rise_constraint("SIG2SRAM_constraint_template") { + index_1("0.0080,0.0288,0.0616,0.1072,0.1920,0.3496,0.5952"); + index_2("0.0080,0.0288,0.0616,0.1072,0.1920,0.3496,0.5952"); + values ("0.3723,0.3527,0.3215,0.2785,0.1965,0.0559,-0.1668",\ +"0.3918,0.3723,0.3449,0.2980,0.2160,0.0754,-0.1473",\ +"0.4152,0.3996,0.3684,0.3254,0.2434,0.1066,-0.1199",\ +"0.4621,0.4465,0.4152,0.3723,0.2863,0.1496,-0.0730",\ +"0.5324,0.5207,0.4895,0.4465,0.3645,0.2199,0.0051",\ +"0.6770,0.6535,0.6301,0.5832,0.5090,0.3605,0.1418",\ +"0.9035,0.8879,0.8566,0.8137,0.7316,0.5871,0.3684"); + } + + fall_constraint("SIG2SRAM_constraint_template") { + index_1("0.0080,0.0288,0.0616,0.1072,0.1920,0.3496,0.5952"); + index_2("0.0080,0.0288,0.0616,0.1072,0.1920,0.3496,0.5952"); + values ("0.3762,0.3566,0.3293,0.2863,0.2043,0.0676,-0.1434",\ +"0.3957,0.3762,0.3488,0.3059,0.2238,0.0871,-0.1199",\ +"0.4230,0.4035,0.3723,0.3332,0.2512,0.1184,-0.0965",\ +"0.4660,0.4465,0.4191,0.3762,0.2941,0.1613,-0.0496",\ +"0.5324,0.5168,0.4973,0.4543,0.3723,0.2316,0.0285",\ +"0.6809,0.6613,0.6340,0.5910,0.5129,0.3645,0.1652",\ +"0.9113,0.8918,0.8605,0.8176,0.7395,0.5988,0.3879"); + } + } + } +pin(A_REN) { + direction : input ; + capacitance : 0.00381144 ; + max_transition : "0.5952" ; + related_power_pin : VDD; + related_ground_pin : VSS; + internal_power() { + when : "A_MEN"; + rise_power("scalar"){ + values (0.0041); + } + fall_power("scalar"){ + values (0.0013); + } + } + internal_power() { + when : "!A_MEN"; + rise_power("scalar"){ + values (0.0042); + } + fall_power("scalar"){ + values (0.0010); + } + } + timing() { + timing_type : setup_rising; + related_pin : "A_CLK"; + when : "A_MEN" + sdf_cond : "A_MEN" + + rise_constraint("SIG2SRAM_constraint_template") { + index_1("0.0080,0.0288,0.0616,0.1072,0.1920,0.3496,0.5952"); + index_2("0.0080,0.0288,0.0616,0.1072,0.1920,0.3496,0.5952"); + values ("-0.0770,-0.0574,-0.0262,0.0168,0.0949,0.2355,0.4582",\ +"-0.0965,-0.0770,-0.0457,-0.0027,0.0754,0.2160,0.4387",\ +"-0.1199,-0.1004,-0.0730,-0.0262,0.0520,0.1887,0.4113",\ +"-0.1590,-0.1434,-0.1160,-0.0730,0.0051,0.1457,0.3645",\ +"-0.2449,-0.2254,-0.1941,-0.1473,-0.0770,0.0676,0.2863",\ +"-0.3816,-0.3699,-0.3387,-0.2801,-0.2215,-0.0770,0.1457",\ +"-0.6121,-0.5926,-0.5613,-0.5145,-0.4363,-0.2996,-0.0730"); + } + + fall_constraint("SIG2SRAM_constraint_template") { + index_1("0.0080,0.0288,0.0616,0.1072,0.1920,0.3496,0.5952"); + index_2("0.0080,0.0288,0.0616,0.1072,0.1920,0.3496,0.5952"); + values ("0.1262,0.1457,0.1691,0.2121,0.2824,0.4191,0.6457",\ +"0.1105,0.1262,0.1496,0.1887,0.2629,0.3996,0.6262",\ +"0.0793,0.0949,0.1223,0.1652,0.2395,0.3684,0.5949",\ +"0.0363,0.0559,0.0793,0.1223,0.2004,0.3410,0.5520",\ +"-0.0457,-0.0262,0.0012,0.0441,0.1301,0.2629,0.4738",\ +"-0.1902,-0.1746,-0.1434,-0.1043,-0.0184,0.1223,0.3332",\ +"-0.4129,-0.3934,-0.3660,-0.3230,-0.2449,-0.1043,0.1105"); + } + } + + + timing() { + timing_type : hold_rising; + related_pin : "A_CLK"; + when : "A_MEN" + sdf_cond : "A_MEN" + + rise_constraint("SIG2SRAM_constraint_template") { + index_1("0.0080,0.0288,0.0616,0.1072,0.1920,0.3496,0.5952"); + index_2("0.0080,0.0288,0.0616,0.1072,0.1920,0.3496,0.5952"); + values ("0.4113,0.3918,0.3645,0.3176,0.2395,0.0988,-0.1238",\ +"0.4309,0.4113,0.3840,0.3371,0.2590,0.1184,-0.1043",\ +"0.4582,0.4387,0.4113,0.3645,0.2824,0.1457,-0.0770",\ +"0.5051,0.4816,0.4543,0.4074,0.3293,0.1887,-0.0340",\ +"0.5715,0.5598,0.5324,0.4895,0.4035,0.2512,0.0441",\ +"0.7043,0.7004,0.6730,0.6262,0.5402,0.3957,0.1809",\ +"0.9387,0.9270,0.8957,0.8527,0.7746,0.6262,0.4074"); + } + + fall_constraint("SIG2SRAM_constraint_template") { + index_1("0.0080,0.0288,0.0616,0.1072,0.1920,0.3496,0.5952"); + index_2("0.0080,0.0288,0.0616,0.1072,0.1920,0.3496,0.5952"); + values ("0.4152,0.3918,0.3645,0.3215,0.2395,0.1027,-0.1082",\ +"0.4309,0.4113,0.3801,0.3410,0.2590,0.1223,-0.0926",\ +"0.4582,0.4387,0.4074,0.3684,0.2863,0.1496,-0.0613",\ +"0.5012,0.4816,0.4504,0.4074,0.3293,0.1887,-0.0145",\ +"0.5715,0.5559,0.5285,0.4816,0.3996,0.2512,0.0598",\ +"0.7160,0.7004,0.6691,0.6262,0.5520,0.4035,0.2004",\ +"0.9387,0.9191,0.8957,0.8488,0.7707,0.6262,0.4113"); + } + } + } +pin(A_MEN) { + direction : input ; + capacitance : 0.00300347 ; + max_transition : "0.5952" ; + related_power_pin : VDD; + related_ground_pin : VSS; + internal_power() { + rise_power("scalar"){ + values (0.0300); + } + fall_power("scalar"){ + values (0.0003); + } + } + timing() { + timing_type : setup_rising; + related_pin : "A_CLK"; + + rise_constraint("SIG2SRAM_constraint_template") { + index_1("0.0080,0.0288,0.0616,0.1072,0.1920,0.3496,0.5952"); + index_2("0.0080,0.0288,0.0616,0.1072,0.1920,0.3496,0.5952"); + values ("0.3215,0.3449,0.3684,0.4113,0.4895,0.6301,0.8527",\ +"0.3059,0.3254,0.3527,0.3957,0.4738,0.6145,0.8371",\ +"0.2746,0.2941,0.3215,0.3645,0.4426,0.5871,0.8059",\ +"0.2316,0.2512,0.2785,0.3215,0.3996,0.5402,0.7629",\ +"0.1496,0.1730,0.1965,0.2395,0.3215,0.4660,0.6848",\ +"0.0090,0.0285,0.0598,0.1027,0.1809,0.3176,0.5402",\ +"-0.2098,-0.1902,-0.1668,-0.1199,-0.0418,0.0988,0.3137"); + } + + fall_constraint("SIG2SRAM_constraint_template") { + index_1("0.0080,0.0288,0.0616,0.1072,0.1920,0.3496,0.5952"); + index_2("0.0080,0.0288,0.0616,0.1072,0.1920,0.3496,0.5952"); + values ("0.4582,0.4738,0.5012,0.5363,0.6145,0.7395,0.9738",\ +"0.4387,0.4543,0.4816,0.5207,0.5910,0.7199,0.9582",\ +"0.4035,0.4230,0.4504,0.4855,0.5637,0.6887,0.9230",\ +"0.3645,0.3840,0.4074,0.4465,0.5285,0.6496,0.8840",\ +"0.2824,0.3020,0.3254,0.3645,0.4465,0.5715,0.7980",\ +"0.1418,0.1613,0.1887,0.2238,0.3020,0.4309,0.6496",\ +"-0.0770,-0.0574,-0.0301,0.0090,0.0910,0.2238,0.4191"); + } + } + + + timing() { + timing_type : hold_rising; + related_pin : "A_CLK"; + + rise_constraint("SIG2SRAM_constraint_template") { + index_1("0.0080,0.0288,0.0616,0.1072,0.1920,0.3496,0.5952"); + index_2("0.0080,0.0288,0.0616,0.1072,0.1920,0.3496,0.5952"); + values ("0.3762,0.3605,0.3293,0.2863,0.2043,0.0637,-0.1629",\ +"0.3996,0.3801,0.3488,0.3020,0.2238,0.0832,-0.1395",\ +"0.4230,0.4074,0.3723,0.3293,0.2473,0.1105,-0.1121",\ +"0.4621,0.4465,0.4152,0.3762,0.2941,0.1535,-0.0691",\ +"0.5441,0.5285,0.4973,0.4465,0.3684,0.2316,0.0090",\ +"0.6848,0.6652,0.6301,0.5910,0.5129,0.3605,0.1496",\ +"0.9074,0.8918,0.8566,0.8215,0.7395,0.5910,0.3723"); + } + + fall_constraint("SIG2SRAM_constraint_template") { + index_1("0.0080,0.0288,0.0616,0.1072,0.1920,0.3496,0.5952"); + index_2("0.0080,0.0288,0.0616,0.1072,0.1920,0.3496,0.5952"); + values ("0.3762,0.3605,0.3332,0.2863,0.2043,0.0715,-0.1395",\ +"0.3996,0.3762,0.3488,0.3059,0.2238,0.0910,-0.1199",\ +"0.4270,0.4035,0.3762,0.3332,0.2512,0.1184,-0.0965",\ +"0.4699,0.4504,0.4191,0.3762,0.2941,0.1613,-0.0496",\ +"0.5441,0.5285,0.4973,0.4543,0.3762,0.2355,0.0324",\ +"0.6770,0.6613,0.6340,0.5949,0.5207,0.3762,0.1652",\ +"0.9074,0.8918,0.8605,0.8176,0.7395,0.6027,0.3918"); + } + } + } +bus(A_BM) { + bus_type : D_31_0; + direction : input ; + capacitance : 0.00263802 ; + max_transition : "0.5952" ; + pin(A_BM[31:0]) { + related_power_pin : VDD; + related_ground_pin : VSS; + internal_power() { + when : "A_MEN"; + rise_power("scalar"){ + values (0.0936); + } + fall_power("scalar"){ + values (0.0304); + } + } + internal_power() { + when : "!A_MEN"; + rise_power("scalar"){ + values (0.0900); + } + fall_power("scalar"){ + values (0.0290); + } + } + } + timing() { + timing_type : setup_rising; + related_pin : "A_CLK"; + when : "(A_WEN & A_MEN)" + sdf_cond : "A_RW_ACCESS" + + rise_constraint("SIG2SRAM_constraint_template") { + index_1("0.0080,0.0288,0.0616,0.1072,0.1920,0.3496,0.5952"); + index_2("0.0080,0.0288,0.0616,0.1072,0.1920,0.3496,0.5952"); + values ("-0.7914,-0.7719,-0.7455,-0.7035,-0.6225,-0.4779,-0.2572",\ +"-0.7993,-0.7798,-0.7534,-0.7115,-0.6304,-0.4859,-0.2652",\ +"-0.8085,-0.7889,-0.7626,-0.7206,-0.6395,-0.4950,-0.2743",\ +"-0.8235,-0.8039,-0.7776,-0.7356,-0.6545,-0.5100,-0.2893",\ +"-0.8458,-0.8263,-0.8000,-0.7580,-0.6769,-0.5324,-0.3117",\ +"-0.8894,-0.8699,-0.8435,-0.8015,-0.7205,-0.5760,-0.3553",\ +"-0.9586,-0.9391,-0.9127,-0.8707,-0.7897,-0.6451,-0.4244"); + } + + fall_constraint("SIG2SRAM_constraint_template") { + index_1("0.0080,0.0288,0.0616,0.1072,0.1920,0.3496,0.5952"); + index_2("0.0080,0.0288,0.0616,0.1072,0.1920,0.3496,0.5952"); + values ("-0.7358,-0.7201,-0.6918,-0.6527,-0.5717,-0.4340,-0.2221",\ +"-0.7437,-0.7280,-0.6997,-0.6607,-0.5796,-0.4419,-0.2300",\ +"-0.7528,-0.7372,-0.7089,-0.6698,-0.5888,-0.4511,-0.2391",\ +"-0.7678,-0.7522,-0.7238,-0.6848,-0.6037,-0.4660,-0.2541",\ +"-0.7902,-0.7746,-0.7462,-0.7072,-0.6261,-0.4884,-0.2765",\ +"-0.8338,-0.8181,-0.7898,-0.7508,-0.6697,-0.5320,-0.3201",\ +"-0.9030,-0.8873,-0.8590,-0.8199,-0.7389,-0.6012,-0.3893"); + } + } + + + timing() { + timing_type : hold_rising; + related_pin : "A_CLK"; + when : "(A_WEN & A_MEN)" + sdf_cond : "A_RW_ACCESS" + + rise_constraint("SIG2SRAM_constraint_template") { + index_1("0.0080,0.0288,0.0616,0.1072,0.1920,0.3496,0.5952"); + index_2("0.0080,0.0288,0.0616,0.1072,0.1920,0.3496,0.5952"); + values ("0.9084,0.8869,0.8606,0.8176,0.7385,0.5930,0.3674",\ +"0.9163,0.8949,0.8685,0.8255,0.7464,0.6009,0.3753",\ +"0.9255,0.9040,0.8776,0.8347,0.7556,0.6101,0.3845",\ +"0.9405,0.9190,0.8926,0.8496,0.7705,0.6250,0.3994",\ +"0.9628,0.9414,0.9150,0.8720,0.7929,0.6474,0.4218",\ +"1.0064,0.9850,0.9586,0.9156,0.8365,0.6910,0.4654",\ +"1.0756,1.0541,1.0278,0.9848,0.9057,0.7602,0.5346"); + } + + fall_constraint("SIG2SRAM_constraint_template") { + index_1("0.0080,0.0288,0.0616,0.1072,0.1920,0.3496,0.5952"); + index_2("0.0080,0.0288,0.0616,0.1072,0.1920,0.3496,0.5952"); + values ("0.8401,0.8235,0.7952,0.7512,0.6740,0.5364,0.3264",\ +"0.8480,0.8314,0.8031,0.7591,0.6820,0.5443,0.3343",\ +"0.8571,0.8405,0.8122,0.7683,0.6911,0.5534,0.3435",\ +"0.8721,0.8555,0.8272,0.7832,0.7061,0.5684,0.3584",\ +"0.8945,0.8779,0.8496,0.8056,0.7285,0.5908,0.3808",\ +"0.9381,0.9215,0.8932,0.8492,0.7721,0.6344,0.4244",\ +"1.0073,0.9907,0.9623,0.9184,0.8412,0.7036,0.4936"); + } + } +} + pin(A_CLK) { + direction : input; + capacitance : 0.00378957; + max_transition : "0.5952"; + clock : "true" ; + pin_func_type : active_rising ; + + timing () { + timing_type : "min_pulse_width"; + related_pin : "A_CLK"; + rise_constraint("CLKTRAN_constraint_template") { + index_1("0.008,0.5952"); + values("0.4,0.4"); + } + } + + related_power_pin : VDD; + related_ground_pin : VSS; + + internal_power() { + when : "!A_MEN & !A_WEN & !A_REN"; + rise_power("scalar"){ + values (0); + } + fall_power("scalar"){ + values (0); + } + } + internal_power() { + when : "!A_MEN & A_WEN & !A_REN"; + rise_power("scalar"){ + values (0.4981); + } + fall_power("scalar"){ + values (0); + } + } + internal_power() { + when : "A_MEN & A_WEN & !A_REN"; + rise_power("scalar"){ + values (28.0075); + } + fall_power("scalar"){ + values (0); + } + } + internal_power() { + when : "A_MEN & A_WEN & A_REN"; + rise_power("scalar"){ + values (30.3621); + } + fall_power("scalar"){ + values (0); + } + } + internal_power() { + when : "A_MEN & !A_WEN & A_REN"; + rise_power("scalar"){ + values (21.9513); + } + fall_power("scalar"){ + values (0); + } + } + internal_power() { + when : "!A_MEN & !A_WEN & A_REN"; + rise_power("scalar"){ + values (0.3219); + } + fall_power("scalar"){ + values (0); + } + } + internal_power() { + when : "!A_MEN & A_WEN & A_REN"; + rise_power("scalar"){ + values (1.0771); + } + fall_power("scalar"){ + values (0); + } + } + internal_power() { + when : "A_MEN & !A_WEN & !A_REN"; + rise_power("scalar"){ + values (0); + } + fall_power("scalar"){ + values (0); + } + } + } + bus(A_DIN) { + bus_type : D_31_0; + direction : input ; + capacitance : 0.00358485 ; + memory_write() { + address : A_ADDR ; + clocked_on : A_CLK; + } + + max_transition : "0.5952" ; + pin(A_DIN[31:0]) { + related_power_pin : VDD; + related_ground_pin : VSS; + internal_power() { + when : "A_MEN"; + rise_power("scalar"){ + values (0.0936); + } + fall_power("scalar"){ + values (0.0304); + } + } + internal_power() { + when : "!A_MEN"; + rise_power("scalar"){ + values (0.0900); + } + fall_power("scalar"){ + values (0.0290); + } + } + } + timing() { + timing_type : setup_rising; + related_pin : "A_CLK"; + when : "(A_WEN & A_MEN)"; + sdf_cond : "A_W_ACCESS"; + + rise_constraint("SIG2SRAM_constraint_template") { + index_1("0.0080,0.0288,0.0616,0.1072,0.1920,0.3496,0.5952"); + index_2("0.0080,0.0288,0.0616,0.1072,0.1920,0.3496,0.5952"); + values ("-0.7914,-0.7719,-0.7455,-0.7035,-0.6225,-0.4779,-0.2572",\ +"-0.7993,-0.7798,-0.7534,-0.7115,-0.6304,-0.4859,-0.2652",\ +"-0.8085,-0.7889,-0.7626,-0.7206,-0.6395,-0.4950,-0.2743",\ +"-0.8235,-0.8039,-0.7776,-0.7356,-0.6545,-0.5100,-0.2893",\ +"-0.8458,-0.8263,-0.8000,-0.7580,-0.6769,-0.5324,-0.3117",\ +"-0.8894,-0.8699,-0.8435,-0.8015,-0.7205,-0.5760,-0.3553",\ +"-0.9586,-0.9391,-0.9127,-0.8707,-0.7897,-0.6451,-0.4244"); + } + + fall_constraint("SIG2SRAM_constraint_template") { + index_1("0.0080,0.0288,0.0616,0.1072,0.1920,0.3496,0.5952"); + index_2("0.0080,0.0288,0.0616,0.1072,0.1920,0.3496,0.5952"); + values ("-0.7358,-0.7201,-0.6918,-0.6527,-0.5717,-0.4340,-0.2221",\ +"-0.7437,-0.7280,-0.6997,-0.6607,-0.5796,-0.4419,-0.2300",\ +"-0.7528,-0.7372,-0.7089,-0.6698,-0.5888,-0.4511,-0.2391",\ +"-0.7678,-0.7522,-0.7238,-0.6848,-0.6037,-0.4660,-0.2541",\ +"-0.7902,-0.7746,-0.7462,-0.7072,-0.6261,-0.4884,-0.2765",\ +"-0.8338,-0.8181,-0.7898,-0.7508,-0.6697,-0.5320,-0.3201",\ +"-0.9030,-0.8873,-0.8590,-0.8199,-0.7389,-0.6012,-0.3893"); + } + } + + timing() { + timing_type : hold_rising; + related_pin : "A_CLK"; + when : "(A_WEN & A_MEN)"; + sdf_cond : "A_W_ACCESS"; + + rise_constraint("SIG2SRAM_constraint_template") { + index_1("0.0080,0.0288,0.0616,0.1072,0.1920,0.3496,0.5952"); + index_2("0.0080,0.0288,0.0616,0.1072,0.1920,0.3496,0.5952"); + values ("0.9084,0.8869,0.8606,0.8176,0.7385,0.5930,0.3674",\ +"0.9163,0.8949,0.8685,0.8255,0.7464,0.6009,0.3753",\ +"0.9255,0.9040,0.8776,0.8347,0.7556,0.6101,0.3845",\ +"0.9405,0.9190,0.8926,0.8496,0.7705,0.6250,0.3994",\ +"0.9628,0.9414,0.9150,0.8720,0.7929,0.6474,0.4218",\ +"1.0064,0.9850,0.9586,0.9156,0.8365,0.6910,0.4654",\ +"1.0756,1.0541,1.0278,0.9848,0.9057,0.7602,0.5346"); + } + + fall_constraint("SIG2SRAM_constraint_template") { + index_1("0.0080,0.0288,0.0616,0.1072,0.1920,0.3496,0.5952"); + index_2("0.0080,0.0288,0.0616,0.1072,0.1920,0.3496,0.5952"); + values ("0.8401,0.8235,0.7952,0.7512,0.6740,0.5364,0.3264",\ +"0.8480,0.8314,0.8031,0.7591,0.6820,0.5443,0.3343",\ +"0.8571,0.8405,0.8122,0.7683,0.6911,0.5534,0.3435",\ +"0.8721,0.8555,0.8272,0.7832,0.7061,0.5684,0.3584",\ +"0.8945,0.8779,0.8496,0.8056,0.7285,0.5908,0.3808",\ +"0.9381,0.9215,0.8932,0.8492,0.7721,0.6344,0.4244",\ +"1.0073,0.9907,0.9623,0.9184,0.8412,0.7036,0.4936"); + } + } + } + + pin(A_BIST_EN) { + direction : input ; + capacitance : 0.00387999 ; + max_transition : "1" ; + related_power_pin : VDD; + related_ground_pin : VSS; + internal_power() { + rise_power("scalar") { + values (0); + } + fall_power("scalar") { + values (0); + } + } + } + +bus(A_BIST_ADDR) { + bus_type : A_7_0; + direction : input ; + capacitance : 0.0077013 ; + pin(A_BIST_ADDR[0]) { + capacitance : 0.00625349 ; + } + pin(A_BIST_ADDR[1]) { + capacitance : 0.00507435 ; + } + pin(A_BIST_ADDR[2]) { + capacitance : 0.00656707 ; + } + pin(A_BIST_ADDR[3]) { + capacitance : 0.0083133 ; + } + pin(A_BIST_ADDR[4]) { + capacitance : 0.00507219 ; + } + pin(A_BIST_ADDR[5]) { + capacitance : 0.00964344 ; + } + pin(A_BIST_ADDR[6]) { + capacitance : 0.0119653 ; + } + max_transition : "0.5952" ; + pin(A_BIST_ADDR[7:0]) { + related_power_pin : VDD; + related_ground_pin : VSS; + internal_power() { + when : "A_BIST_MEN"; + rise_power("scalar"){ + values (0.0097); + } + fall_power("scalar"){ + values (0.0074); + } + } + internal_power() { + when : "!A_BIST_MEN"; + rise_power("scalar"){ + values (0.0163); + } + fall_power("scalar"){ + values (0.0021); + } + } + } + timing() { + timing_type : setup_rising; + related_pin : "A_BIST_CLK"; + when : "((A_BIST_WEN | A_BIST_REN)& A_BIST_MEN)" + sdf_cond : "A_BIST_RW_ACCESS" + + rise_constraint("SIG2SRAM_constraint_template") { + index_1("0.0080,0.0288,0.0616,0.1072,0.1920,0.3496,0.5952"); + index_2("0.0080,0.0288,0.0616,0.1072,0.1920,0.3496,0.5952"); + values ("-0.7371,-0.7176,-0.6863,-0.6434,-0.5652,-0.4168,-0.1980",\ +"-0.7566,-0.7371,-0.7059,-0.6629,-0.5848,-0.4363,-0.2137",\ +"-0.7879,-0.7645,-0.7332,-0.6902,-0.6121,-0.4637,-0.2449",\ +"-0.8309,-0.8074,-0.7762,-0.7332,-0.6551,-0.5066,-0.2879",\ +"-0.9051,-0.8895,-0.8543,-0.8113,-0.7332,-0.5887,-0.3660",\ +"-1.0418,-1.0262,-0.9949,-0.9480,-0.8699,-0.7293,-0.5027",\ +"-1.2684,-1.2449,-1.2176,-1.1707,-1.0965,-0.9480,-0.7293"); + } + + fall_constraint("SIG2SRAM_constraint_template") { + index_1("0.0080,0.0288,0.0616,0.1072,0.1920,0.3496,0.5952"); + index_2("0.0080,0.0288,0.0616,0.1072,0.1920,0.3496,0.5952"); + values ("-0.5926,-0.5730,-0.5418,-0.4988,-0.4246,-0.2879,-0.0730",\ +"-0.6121,-0.5926,-0.5613,-0.5223,-0.4441,-0.3074,-0.0887",\ +"-0.6395,-0.6199,-0.5926,-0.5496,-0.4715,-0.3348,-0.1160",\ +"-0.6863,-0.6668,-0.6355,-0.5965,-0.5184,-0.3777,-0.1590",\ +"-0.7605,-0.7410,-0.7137,-0.6746,-0.5926,-0.4559,-0.2410",\ +"-0.9012,-0.8816,-0.8504,-0.8113,-0.7332,-0.5926,-0.3895",\ +"-1.1238,-1.1043,-1.0769,-1.0379,-0.9559,-0.8191,-0.6004"); + } + } + + + timing() { + timing_type : hold_rising; + related_pin : "A_BIST_CLK"; + when : "((A_BIST_WEN | A_BIST_REN)& A_BIST_MEN)" + sdf_cond : "A_BIST_RW_ACCESS" + + rise_constraint("SIG2SRAM_constraint_template") { + index_1("0.0080,0.0288,0.0616,0.1072,0.1920,0.3496,0.5952"); + index_2("0.0080,0.0288,0.0616,0.1072,0.1920,0.3496,0.5952"); + values ("0.8488,0.8293,0.7980,0.7551,0.6730,0.5285,0.3059",\ +"0.8684,0.8488,0.8176,0.7746,0.6926,0.5480,0.3254",\ +"0.8996,0.8801,0.8449,0.8020,0.7238,0.5754,0.3527",\ +"0.9426,0.9191,0.8918,0.8488,0.7668,0.6223,0.3996",\ +"1.0168,1.0012,0.9699,0.9230,0.8449,0.7004,0.4777",\ +"1.1574,1.1379,1.1105,1.0598,0.9816,0.8371,0.6184",\ +"1.3801,1.3605,1.3254,1.2980,1.2043,1.0637,0.8371"); + } + + fall_constraint("SIG2SRAM_constraint_template") { + index_1("0.0080,0.0288,0.0616,0.1072,0.1920,0.3496,0.5952"); + index_2("0.0080,0.0288,0.0616,0.1072,0.1920,0.3496,0.5952"); + values ("0.6965,0.6770,0.6496,0.6066,0.5246,0.3918,0.1730",\ +"0.7160,0.6965,0.6652,0.6262,0.5441,0.4113,0.1965",\ +"0.7473,0.7277,0.6965,0.6535,0.5754,0.4426,0.2238",\ +"0.7863,0.7707,0.7395,0.7004,0.6223,0.4855,0.2629",\ +"0.8684,0.8449,0.8176,0.7785,0.7004,0.5637,0.3449",\ +"1.0051,0.9855,0.9855,0.9113,0.8332,0.7004,0.4895",\ +"1.2277,1.2082,1.1809,1.1379,1.0598,0.9230,0.7004"); + } + } +} +pin(A_BIST_WEN) { + direction : input ; + capacitance : 0.00313551 ; + max_transition : "0.5952" ; + related_power_pin : VDD; + related_ground_pin : VSS; + internal_power() { + when : "A_BIST_MEN"; + rise_power("scalar"){ + values (0.0036); + } + fall_power("scalar"){ + values (0.0005); + } + } + internal_power() { + when : "!A_BIST_MEN"; + rise_power("scalar"){ + values (0.0052); + } + fall_power("scalar"){ + values (0.0001); + } + } + timing() { + timing_type : setup_rising; + related_pin : "A_BIST_CLK"; + when : "A_BIST_MEN" + sdf_cond : "A_BIST_MEN" + + rise_constraint("SIG2SRAM_constraint_template") { + index_1("0.0080,0.0288,0.0616,0.1072,0.1920,0.3496,0.5952"); + index_2("0.0080,0.0288,0.0616,0.1072,0.1920,0.3496,0.5952"); + values ("0.3137,0.3332,0.3605,0.4035,0.4816,0.6223,0.8488",\ +"0.2980,0.3176,0.3410,0.3840,0.4660,0.6027,0.8293",\ +"0.2629,0.2824,0.3098,0.3527,0.4348,0.5754,0.7980",\ +"0.2199,0.2395,0.2668,0.3098,0.3918,0.5324,0.7590",\ +"0.1418,0.1613,0.1887,0.2316,0.3137,0.4348,0.6730",\ +"0.0012,0.0207,0.0520,0.0910,0.1730,0.3098,0.5285",\ +"-0.2215,-0.2020,-0.1746,-0.1277,-0.0496,0.0910,0.3098"); + } + + fall_constraint("SIG2SRAM_constraint_template") { + index_1("0.0080,0.0288,0.0616,0.1072,0.1920,0.3496,0.5952"); + index_2("0.0080,0.0288,0.0616,0.1072,0.1920,0.3496,0.5952"); + values ("0.4504,0.4699,0.4973,0.5324,0.6027,0.7355,0.9699",\ +"0.4309,0.4504,0.4777,0.5129,0.5910,0.7160,0.9504",\ +"0.3996,0.4191,0.4465,0.4816,0.5520,0.6848,0.9191",\ +"0.3605,0.3762,0.4035,0.4387,0.5168,0.6418,0.8723",\ +"0.2785,0.2980,0.3215,0.3605,0.4348,0.5637,0.7980",\ +"0.1379,0.1574,0.1809,0.2199,0.2980,0.4309,0.6457",\ +"-0.0809,-0.0613,-0.0340,0.0051,0.0832,0.2160,0.4191"); + } + } + + + timing() { + timing_type : hold_rising; + related_pin : "A_BIST_CLK"; + when : "A_BIST_MEN" + sdf_cond : "A_BIST_MEN" + + rise_constraint("SIG2SRAM_constraint_template") { + index_1("0.0080,0.0288,0.0616,0.1072,0.1920,0.3496,0.5952"); + index_2("0.0080,0.0288,0.0616,0.1072,0.1920,0.3496,0.5952"); + values ("0.3723,0.3527,0.3215,0.2785,0.1965,0.0559,-0.1668",\ +"0.3918,0.3723,0.3449,0.2980,0.2160,0.0754,-0.1473",\ +"0.4152,0.3996,0.3684,0.3254,0.2434,0.1066,-0.1199",\ +"0.4621,0.4465,0.4152,0.3723,0.2863,0.1496,-0.0730",\ +"0.5324,0.5207,0.4895,0.4465,0.3645,0.2199,0.0051",\ +"0.6770,0.6535,0.6301,0.5832,0.5090,0.3605,0.1418",\ +"0.9035,0.8879,0.8566,0.8137,0.7316,0.5871,0.3684"); + } + + fall_constraint("SIG2SRAM_constraint_template") { + index_1("0.0080,0.0288,0.0616,0.1072,0.1920,0.3496,0.5952"); + index_2("0.0080,0.0288,0.0616,0.1072,0.1920,0.3496,0.5952"); + values ("0.3762,0.3566,0.3293,0.2863,0.2043,0.0676,-0.1434",\ +"0.3957,0.3762,0.3488,0.3059,0.2238,0.0871,-0.1199",\ +"0.4230,0.4035,0.3723,0.3332,0.2512,0.1184,-0.0965",\ +"0.4660,0.4465,0.4191,0.3762,0.2941,0.1613,-0.0496",\ +"0.5324,0.5168,0.4973,0.4543,0.3723,0.2316,0.0285",\ +"0.6809,0.6613,0.6340,0.5910,0.5129,0.3645,0.1652",\ +"0.9113,0.8918,0.8605,0.8176,0.7395,0.5988,0.3879"); + } + } + } +pin(A_BIST_REN) { + direction : input ; + capacitance : 0.00381144 ; + max_transition : "0.5952" ; + related_power_pin : VDD; + related_ground_pin : VSS; + internal_power() { + when : "A_BIST_MEN"; + rise_power("scalar"){ + values (0.0041); + } + fall_power("scalar"){ + values (0.0013); + } + } + internal_power() { + when : "!A_BIST_MEN"; + rise_power("scalar"){ + values (0.0042); + } + fall_power("scalar"){ + values (0.0010); + } + } + timing() { + timing_type : setup_rising; + related_pin : "A_BIST_CLK"; + when : "A_BIST_MEN" + sdf_cond : "A_BIST_MEN" + + rise_constraint("SIG2SRAM_constraint_template") { + index_1("0.0080,0.0288,0.0616,0.1072,0.1920,0.3496,0.5952"); + index_2("0.0080,0.0288,0.0616,0.1072,0.1920,0.3496,0.5952"); + values ("-0.0770,-0.0574,-0.0262,0.0168,0.0949,0.2355,0.4582",\ +"-0.0965,-0.0770,-0.0457,-0.0027,0.0754,0.2160,0.4387",\ +"-0.1199,-0.1004,-0.0730,-0.0262,0.0520,0.1887,0.4113",\ +"-0.1590,-0.1434,-0.1160,-0.0730,0.0051,0.1457,0.3645",\ +"-0.2449,-0.2254,-0.1941,-0.1473,-0.0770,0.0676,0.2863",\ +"-0.3816,-0.3699,-0.3387,-0.2801,-0.2215,-0.0770,0.1457",\ +"-0.6121,-0.5926,-0.5613,-0.5145,-0.4363,-0.2996,-0.0730"); + } + + fall_constraint("SIG2SRAM_constraint_template") { + index_1("0.0080,0.0288,0.0616,0.1072,0.1920,0.3496,0.5952"); + index_2("0.0080,0.0288,0.0616,0.1072,0.1920,0.3496,0.5952"); + values ("0.1262,0.1457,0.1691,0.2121,0.2824,0.4191,0.6457",\ +"0.1105,0.1262,0.1496,0.1887,0.2629,0.3996,0.6262",\ +"0.0793,0.0949,0.1223,0.1652,0.2395,0.3684,0.5949",\ +"0.0363,0.0559,0.0793,0.1223,0.2004,0.3410,0.5520",\ +"-0.0457,-0.0262,0.0012,0.0441,0.1301,0.2629,0.4738",\ +"-0.1902,-0.1746,-0.1434,-0.1043,-0.0184,0.1223,0.3332",\ +"-0.4129,-0.3934,-0.3660,-0.3230,-0.2449,-0.1043,0.1105"); + } + } + + + timing() { + timing_type : hold_rising; + related_pin : "A_BIST_CLK"; + when : "A_BIST_MEN" + sdf_cond : "A_BIST_MEN" + + rise_constraint("SIG2SRAM_constraint_template") { + index_1("0.0080,0.0288,0.0616,0.1072,0.1920,0.3496,0.5952"); + index_2("0.0080,0.0288,0.0616,0.1072,0.1920,0.3496,0.5952"); + values ("0.4113,0.3918,0.3645,0.3176,0.2395,0.0988,-0.1238",\ +"0.4309,0.4113,0.3840,0.3371,0.2590,0.1184,-0.1043",\ +"0.4582,0.4387,0.4113,0.3645,0.2824,0.1457,-0.0770",\ +"0.5051,0.4816,0.4543,0.4074,0.3293,0.1887,-0.0340",\ +"0.5715,0.5598,0.5324,0.4895,0.4035,0.2512,0.0441",\ +"0.7043,0.7004,0.6730,0.6262,0.5402,0.3957,0.1809",\ +"0.9387,0.9270,0.8957,0.8527,0.7746,0.6262,0.4074"); + } + + fall_constraint("SIG2SRAM_constraint_template") { + index_1("0.0080,0.0288,0.0616,0.1072,0.1920,0.3496,0.5952"); + index_2("0.0080,0.0288,0.0616,0.1072,0.1920,0.3496,0.5952"); + values ("0.4152,0.3918,0.3645,0.3215,0.2395,0.1027,-0.1082",\ +"0.4309,0.4113,0.3801,0.3410,0.2590,0.1223,-0.0926",\ +"0.4582,0.4387,0.4074,0.3684,0.2863,0.1496,-0.0613",\ +"0.5012,0.4816,0.4504,0.4074,0.3293,0.1887,-0.0145",\ +"0.5715,0.5559,0.5285,0.4816,0.3996,0.2512,0.0598",\ +"0.7160,0.7004,0.6691,0.6262,0.5520,0.4035,0.2004",\ +"0.9387,0.9191,0.8957,0.8488,0.7707,0.6262,0.4113"); + } + } + } +pin(A_BIST_MEN) { + direction : input ; + capacitance : 0.00300347 ; + max_transition : "0.5952" ; + related_power_pin : VDD; + related_ground_pin : VSS; + internal_power() { + rise_power("scalar"){ + values (0.0300); + } + fall_power("scalar"){ + values (0.0003); + } + } + timing() { + timing_type : setup_rising; + related_pin : "A_BIST_CLK"; + + rise_constraint("SIG2SRAM_constraint_template") { + index_1("0.0080,0.0288,0.0616,0.1072,0.1920,0.3496,0.5952"); + index_2("0.0080,0.0288,0.0616,0.1072,0.1920,0.3496,0.5952"); + values ("0.3215,0.3449,0.3684,0.4113,0.4895,0.6301,0.8527",\ +"0.3059,0.3254,0.3527,0.3957,0.4738,0.6145,0.8371",\ +"0.2746,0.2941,0.3215,0.3645,0.4426,0.5871,0.8059",\ +"0.2316,0.2512,0.2785,0.3215,0.3996,0.5402,0.7629",\ +"0.1496,0.1730,0.1965,0.2395,0.3215,0.4660,0.6848",\ +"0.0090,0.0285,0.0598,0.1027,0.1809,0.3176,0.5402",\ +"-0.2098,-0.1902,-0.1668,-0.1199,-0.0418,0.0988,0.3137"); + } + + fall_constraint("SIG2SRAM_constraint_template") { + index_1("0.0080,0.0288,0.0616,0.1072,0.1920,0.3496,0.5952"); + index_2("0.0080,0.0288,0.0616,0.1072,0.1920,0.3496,0.5952"); + values ("0.4582,0.4738,0.5012,0.5363,0.6145,0.7395,0.9738",\ +"0.4387,0.4543,0.4816,0.5207,0.5910,0.7199,0.9582",\ +"0.4035,0.4230,0.4504,0.4855,0.5637,0.6887,0.9230",\ +"0.3645,0.3840,0.4074,0.4465,0.5285,0.6496,0.8840",\ +"0.2824,0.3020,0.3254,0.3645,0.4465,0.5715,0.7980",\ +"0.1418,0.1613,0.1887,0.2238,0.3020,0.4309,0.6496",\ +"-0.0770,-0.0574,-0.0301,0.0090,0.0910,0.2238,0.4191"); + } + } + + + timing() { + timing_type : hold_rising; + related_pin : "A_BIST_CLK"; + + rise_constraint("SIG2SRAM_constraint_template") { + index_1("0.0080,0.0288,0.0616,0.1072,0.1920,0.3496,0.5952"); + index_2("0.0080,0.0288,0.0616,0.1072,0.1920,0.3496,0.5952"); + values ("0.3762,0.3605,0.3293,0.2863,0.2043,0.0637,-0.1629",\ +"0.3996,0.3801,0.3488,0.3020,0.2238,0.0832,-0.1395",\ +"0.4230,0.4074,0.3723,0.3293,0.2473,0.1105,-0.1121",\ +"0.4621,0.4465,0.4152,0.3762,0.2941,0.1535,-0.0691",\ +"0.5441,0.5285,0.4973,0.4465,0.3684,0.2316,0.0090",\ +"0.6848,0.6652,0.6301,0.5910,0.5129,0.3605,0.1496",\ +"0.9074,0.8918,0.8566,0.8215,0.7395,0.5910,0.3723"); + } + + fall_constraint("SIG2SRAM_constraint_template") { + index_1("0.0080,0.0288,0.0616,0.1072,0.1920,0.3496,0.5952"); + index_2("0.0080,0.0288,0.0616,0.1072,0.1920,0.3496,0.5952"); + values ("0.3762,0.3605,0.3332,0.2863,0.2043,0.0715,-0.1395",\ +"0.3996,0.3762,0.3488,0.3059,0.2238,0.0910,-0.1199",\ +"0.4270,0.4035,0.3762,0.3332,0.2512,0.1184,-0.0965",\ +"0.4699,0.4504,0.4191,0.3762,0.2941,0.1613,-0.0496",\ +"0.5441,0.5285,0.4973,0.4543,0.3762,0.2355,0.0324",\ +"0.6770,0.6613,0.6340,0.5949,0.5207,0.3762,0.1652",\ +"0.9074,0.8918,0.8605,0.8176,0.7395,0.6027,0.3918"); + } + } + } +bus(A_BIST_BM) { + bus_type : D_31_0; + direction : input ; + capacitance : 0.00225269 ; + max_transition : "0.5952" ; + pin(A_BIST_BM[31:0]) { + related_power_pin : VDD; + related_ground_pin : VSS; + internal_power() { + when : "A_BIST_MEN"; + rise_power("scalar"){ + values (0.0936); + } + fall_power("scalar"){ + values (0.0304); + } + } + internal_power() { + when : "!A_BIST_MEN"; + rise_power("scalar"){ + values (0.0900); + } + fall_power("scalar"){ + values (0.0290); + } + } + } + timing() { + timing_type : setup_rising; + related_pin : "A_BIST_CLK"; + when : "(A_BIST_WEN & A_BIST_MEN)" + sdf_cond : "A_BIST_RW_ACCESS" + + rise_constraint("SIG2SRAM_constraint_template") { + index_1("0.0080,0.0288,0.0616,0.1072,0.1920,0.3496,0.5952"); + index_2("0.0080,0.0288,0.0616,0.1072,0.1920,0.3496,0.5952"); + values ("-0.7914,-0.7719,-0.7455,-0.7035,-0.6225,-0.4779,-0.2572",\ +"-0.7993,-0.7798,-0.7534,-0.7115,-0.6304,-0.4859,-0.2652",\ +"-0.8085,-0.7889,-0.7626,-0.7206,-0.6395,-0.4950,-0.2743",\ +"-0.8235,-0.8039,-0.7776,-0.7356,-0.6545,-0.5100,-0.2893",\ +"-0.8458,-0.8263,-0.8000,-0.7580,-0.6769,-0.5324,-0.3117",\ +"-0.8894,-0.8699,-0.8435,-0.8015,-0.7205,-0.5760,-0.3553",\ +"-0.9586,-0.9391,-0.9127,-0.8707,-0.7897,-0.6451,-0.4244"); + } + + fall_constraint("SIG2SRAM_constraint_template") { + index_1("0.0080,0.0288,0.0616,0.1072,0.1920,0.3496,0.5952"); + index_2("0.0080,0.0288,0.0616,0.1072,0.1920,0.3496,0.5952"); + values ("-0.7358,-0.7201,-0.6918,-0.6527,-0.5717,-0.4340,-0.2221",\ +"-0.7437,-0.7280,-0.6997,-0.6607,-0.5796,-0.4419,-0.2300",\ +"-0.7528,-0.7372,-0.7089,-0.6698,-0.5888,-0.4511,-0.2391",\ +"-0.7678,-0.7522,-0.7238,-0.6848,-0.6037,-0.4660,-0.2541",\ +"-0.7902,-0.7746,-0.7462,-0.7072,-0.6261,-0.4884,-0.2765",\ +"-0.8338,-0.8181,-0.7898,-0.7508,-0.6697,-0.5320,-0.3201",\ +"-0.9030,-0.8873,-0.8590,-0.8199,-0.7389,-0.6012,-0.3893"); + } + } + + + timing() { + timing_type : hold_rising; + related_pin : "A_BIST_CLK"; + when : "(A_BIST_WEN & A_BIST_MEN)" + sdf_cond : "A_BIST_RW_ACCESS" + + rise_constraint("SIG2SRAM_constraint_template") { + index_1("0.0080,0.0288,0.0616,0.1072,0.1920,0.3496,0.5952"); + index_2("0.0080,0.0288,0.0616,0.1072,0.1920,0.3496,0.5952"); + values ("0.9084,0.8869,0.8606,0.8176,0.7385,0.5930,0.3674",\ +"0.9163,0.8949,0.8685,0.8255,0.7464,0.6009,0.3753",\ +"0.9255,0.9040,0.8776,0.8347,0.7556,0.6101,0.3845",\ +"0.9405,0.9190,0.8926,0.8496,0.7705,0.6250,0.3994",\ +"0.9628,0.9414,0.9150,0.8720,0.7929,0.6474,0.4218",\ +"1.0064,0.9850,0.9586,0.9156,0.8365,0.6910,0.4654",\ +"1.0756,1.0541,1.0278,0.9848,0.9057,0.7602,0.5346"); + } + + fall_constraint("SIG2SRAM_constraint_template") { + index_1("0.0080,0.0288,0.0616,0.1072,0.1920,0.3496,0.5952"); + index_2("0.0080,0.0288,0.0616,0.1072,0.1920,0.3496,0.5952"); + values ("0.8401,0.8235,0.7952,0.7512,0.6740,0.5364,0.3264",\ +"0.8480,0.8314,0.8031,0.7591,0.6820,0.5443,0.3343",\ +"0.8571,0.8405,0.8122,0.7683,0.6911,0.5534,0.3435",\ +"0.8721,0.8555,0.8272,0.7832,0.7061,0.5684,0.3584",\ +"0.8945,0.8779,0.8496,0.8056,0.7285,0.5908,0.3808",\ +"0.9381,0.9215,0.8932,0.8492,0.7721,0.6344,0.4244",\ +"1.0073,0.9907,0.9623,0.9184,0.8412,0.7036,0.4936"); + } + } +} + pin(A_BIST_CLK) { + direction : input; + capacitance : 0.00378957; + max_transition : "0.5952"; + clock : "true" ; + pin_func_type : active_rising ; + + timing () { + timing_type : "min_pulse_width"; + related_pin : "A_BIST_CLK"; + rise_constraint("CLKTRAN_constraint_template") { + index_1("0.008,0.5952"); + values("0.4,0.4"); + } + } + + related_power_pin : VDD; + related_ground_pin : VSS; + + internal_power() { + when : "!A_BIST_MEN & !A_BIST_WEN & !A_BIST_REN"; + rise_power("scalar"){ + values (0); + } + fall_power("scalar"){ + values (0); + } + } + internal_power() { + when : "!A_BIST_MEN & A_BIST_WEN & !A_BIST_REN"; + rise_power("scalar"){ + values (0.4981); + } + fall_power("scalar"){ + values (0); + } + } + internal_power() { + when : "A_BIST_MEN & A_BIST_WEN & !A_BIST_REN"; + rise_power("scalar"){ + values (28.0075); + } + fall_power("scalar"){ + values (0); + } + } + internal_power() { + when : "A_BIST_MEN & A_BIST_WEN & A_BIST_REN"; + rise_power("scalar"){ + values (30.3621); + } + fall_power("scalar"){ + values (0); + } + } + internal_power() { + when : "A_BIST_MEN & !A_BIST_WEN & A_BIST_REN"; + rise_power("scalar"){ + values (21.9513); + } + fall_power("scalar"){ + values (0); + } + } + internal_power() { + when : "!A_BIST_MEN & !A_BIST_WEN & A_BIST_REN"; + rise_power("scalar"){ + values (0.3219); + } + fall_power("scalar"){ + values (0); + } + } + internal_power() { + when : "!A_BIST_MEN & A_BIST_WEN & A_BIST_REN"; + rise_power("scalar"){ + values (1.0771); + } + fall_power("scalar"){ + values (0); + } + } + internal_power() { + when : "A_BIST_MEN & !A_BIST_WEN & !A_BIST_REN"; + rise_power("scalar"){ + values (0); + } + fall_power("scalar"){ + values (0); + } + } + } + bus(A_BIST_DIN) { + bus_type : D_31_0; + direction : input ; + capacitance : 0.00226348 ; + memory_write() { + address : A_BIST_ADDR ; + clocked_on : A_BIST_CLK; + } + + max_transition : "0.5952" ; + pin(A_BIST_DIN[31:0]) { + related_power_pin : VDD; + related_ground_pin : VSS; + internal_power() { + when : "A_BIST_MEN"; + rise_power("scalar"){ + values (0.0936); + } + fall_power("scalar"){ + values (0.0304); + } + } + internal_power() { + when : "!A_BIST_MEN"; + rise_power("scalar"){ + values (0.0900); + } + fall_power("scalar"){ + values (0.0290); + } + } + } + timing() { + timing_type : setup_rising; + related_pin : "A_BIST_CLK"; + when : "(A_BIST_WEN & A_BIST_MEN)"; + sdf_cond : "A_BIST_W_ACCESS"; + + rise_constraint("SIG2SRAM_constraint_template") { + index_1("0.0080,0.0288,0.0616,0.1072,0.1920,0.3496,0.5952"); + index_2("0.0080,0.0288,0.0616,0.1072,0.1920,0.3496,0.5952"); + values ("-0.7914,-0.7719,-0.7455,-0.7035,-0.6225,-0.4779,-0.2572",\ +"-0.7993,-0.7798,-0.7534,-0.7115,-0.6304,-0.4859,-0.2652",\ +"-0.8085,-0.7889,-0.7626,-0.7206,-0.6395,-0.4950,-0.2743",\ +"-0.8235,-0.8039,-0.7776,-0.7356,-0.6545,-0.5100,-0.2893",\ +"-0.8458,-0.8263,-0.8000,-0.7580,-0.6769,-0.5324,-0.3117",\ +"-0.8894,-0.8699,-0.8435,-0.8015,-0.7205,-0.5760,-0.3553",\ +"-0.9586,-0.9391,-0.9127,-0.8707,-0.7897,-0.6451,-0.4244"); + } + + fall_constraint("SIG2SRAM_constraint_template") { + index_1("0.0080,0.0288,0.0616,0.1072,0.1920,0.3496,0.5952"); + index_2("0.0080,0.0288,0.0616,0.1072,0.1920,0.3496,0.5952"); + values ("-0.7358,-0.7201,-0.6918,-0.6527,-0.5717,-0.4340,-0.2221",\ +"-0.7437,-0.7280,-0.6997,-0.6607,-0.5796,-0.4419,-0.2300",\ +"-0.7528,-0.7372,-0.7089,-0.6698,-0.5888,-0.4511,-0.2391",\ +"-0.7678,-0.7522,-0.7238,-0.6848,-0.6037,-0.4660,-0.2541",\ +"-0.7902,-0.7746,-0.7462,-0.7072,-0.6261,-0.4884,-0.2765",\ +"-0.8338,-0.8181,-0.7898,-0.7508,-0.6697,-0.5320,-0.3201",\ +"-0.9030,-0.8873,-0.8590,-0.8199,-0.7389,-0.6012,-0.3893"); + } + } + + timing() { + timing_type : hold_rising; + related_pin : "A_BIST_CLK"; + when : "(A_BIST_WEN & A_BIST_MEN)"; + sdf_cond : "A_BIST_W_ACCESS"; + + rise_constraint("SIG2SRAM_constraint_template") { + index_1("0.0080,0.0288,0.0616,0.1072,0.1920,0.3496,0.5952"); + index_2("0.0080,0.0288,0.0616,0.1072,0.1920,0.3496,0.5952"); + values ("0.9084,0.8869,0.8606,0.8176,0.7385,0.5930,0.3674",\ +"0.9163,0.8949,0.8685,0.8255,0.7464,0.6009,0.3753",\ +"0.9255,0.9040,0.8776,0.8347,0.7556,0.6101,0.3845",\ +"0.9405,0.9190,0.8926,0.8496,0.7705,0.6250,0.3994",\ +"0.9628,0.9414,0.9150,0.8720,0.7929,0.6474,0.4218",\ +"1.0064,0.9850,0.9586,0.9156,0.8365,0.6910,0.4654",\ +"1.0756,1.0541,1.0278,0.9848,0.9057,0.7602,0.5346"); + } + + fall_constraint("SIG2SRAM_constraint_template") { + index_1("0.0080,0.0288,0.0616,0.1072,0.1920,0.3496,0.5952"); + index_2("0.0080,0.0288,0.0616,0.1072,0.1920,0.3496,0.5952"); + values ("0.8401,0.8235,0.7952,0.7512,0.6740,0.5364,0.3264",\ +"0.8480,0.8314,0.8031,0.7591,0.6820,0.5443,0.3343",\ +"0.8571,0.8405,0.8122,0.7683,0.6911,0.5534,0.3435",\ +"0.8721,0.8555,0.8272,0.7832,0.7061,0.5684,0.3584",\ +"0.8945,0.8779,0.8496,0.8056,0.7285,0.5908,0.3808",\ +"0.9381,0.9215,0.8932,0.8492,0.7721,0.6344,0.4244",\ +"1.0073,0.9907,0.9623,0.9184,0.8412,0.7036,0.4936"); + } + } + } + +bus(A_DOUT) { + + bus_type : D_31_0; + direction : output ; + capacitance : 0 ; + max_capacitance : 0.064 ; + memory_read() { + address : A_ADDR ; + } + pin(A_DOUT[31:0]) { + related_power_pin : VDD; + related_ground_pin : VSS; + internal_power() { + rise_power("scalar") { + values (0); + } + fall_power("scalar") { + values (0); + } + } + } + timing() { + related_pin : "A_CLK"; + timing_type : rising_edge ; + timing_sense : non_unate ; + + cell_rise(SIG2SRAM_delay_template) { + index_1("0.0080,0.0288,0.0616,0.1072,0.1920,0.3496,0.5952"); + index_2("0.0008,0.0014,0.0051,0.0100,0.0339,0.0640"); + values ("5.1263,5.1290,5.1412,5.1554,5.2080,5.2630",\ +"5.1402,5.1429,5.1551,5.1693,5.2219,5.2769",\ +"5.1501,5.1528,5.1650,5.1792,5.2318,5.2867",\ +"5.1634,5.1661,5.1782,5.1925,5.2450,5.3000",\ +"5.1866,5.1894,5.2015,5.2157,5.2683,5.3233",\ +"5.2314,5.2341,5.2463,5.2605,5.3131,5.3680",\ +"5.2987,5.3014,5.3135,5.3277,5.3803,5.4353"); + } + cell_fall(SIG2SRAM_delay_template) { + index_1("0.0080,0.0288,0.0616,0.1072,0.1920,0.3496,0.5952"); + index_2("0.0008,0.0014,0.0051,0.0100,0.0339,0.0640"); + values ("5.0161,5.0183,5.0281,5.0399,5.0835,5.1272",\ +"5.0300,5.0322,5.0420,5.0538,5.0974,5.1411",\ +"5.0399,5.0421,5.0518,5.0637,5.1072,5.1509",\ +"5.0532,5.0554,5.0651,5.0770,5.1205,5.1642",\ +"5.0765,5.0786,5.0884,5.1002,5.1438,5.1875",\ +"5.1212,5.1234,5.1331,5.1450,5.1885,5.2323",\ +"5.1885,5.1906,5.2004,5.2122,5.2558,5.2995"); + } + + rise_transition(SRAM_load_template) { + index_1("0.0008,0.0014,0.0051,0.0100,0.0339,0.0640"); + values ("0.0560,0.0583,0.0696,0.0816,0.1519,0.2335"); + } + fall_transition(SRAM_load_template) { + index_1("0.0008,0.0014,0.0051,0.0100,0.0339,0.0640"); + values ("0.0428,0.0445,0.0538,0.0658,0.1181,0.1751"); + } + } +} +cell_leakage_power : 653.2941; +} +} diff --git a/flow/platforms/ihp-sg13g2/lib/RM_IHPSG13_1P_256x32_c2_bm_bist_typ_1p20V_25C.lib b/flow/platforms/ihp-sg13g2/lib/RM_IHPSG13_1P_256x32_c2_bm_bist_typ_1p20V_25C.lib new file mode 100644 index 0000000000..3215764cfe --- /dev/null +++ b/flow/platforms/ihp-sg13g2/lib/RM_IHPSG13_1P_256x32_c2_bm_bist_typ_1p20V_25C.lib @@ -0,0 +1,1513 @@ +/* ------------------------------------------------------*/ +/**/ +/* Copyright 2025 IHP PDK Authors*/ +/**/ +/* Licensed under the Apache License, Version 2.0 (the "License");*/ +/* you may not use this file except in compliance with the License.*/ +/* You may obtain a copy of the License at*/ +/* */ +/* https://www.apache.org/licenses/LICENSE-2.0*/ +/* */ +/* Unless required by applicable law or agreed to in writing, software*/ +/* distributed under the License is distributed on an "AS IS" BASIS,*/ +/* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.*/ +/* See the License for the specific language governing permissions and*/ +/* limitations under the License.*/ +/* */ +/* Generated on Thu Aug 21 20:49:09 2025 */ +/* */ +/* ------------------------------------------------------ */ +library(RM_IHPSG13_1P_256x32_c2_bm_bist_typ_1p20V_25C) { + technology (cmos) ; + delay_model : table_lookup ; + define ("add_pg_pin_to_lib", "library", "boolean"); + add_pg_pin_to_lib : true; + voltage_map ( VDD, 1.20); + voltage_map ( VDDARRAY, 1.20); + voltage_map ( VSS, 0.000000 ); + + date : "Thu Aug 21 20:49:06 2025" ; + comment : "IHP Microelectronics GmbH, 2023" ; + revision : 1.0.0 ; + simulation : true ; + nom_process : 1 ; + nom_temperature : 25 ; + nom_voltage : 1.20 ; + + operating_conditions("typ_1p20V_25C"){ + process : 1 ; + temperature : 25 ; + voltage : 1.20 ; + tree_type : "balanced_tree" ; + } + + default_operating_conditions : typ_1p20V_25C ; + default_max_transition : 1.0 ; + default_fanout_load : 1.0 ; + default_inout_pin_cap : 0.0 ; + default_input_pin_cap : 0.0 ; + default_output_pin_cap : 0.0 ; + default_cell_leakage_power : 0.0 ; + default_leakage_power_density : 0.0 ; + + slew_lower_threshold_pct_rise : 30 ; + slew_upper_threshold_pct_rise : 70 ; + input_threshold_pct_fall : 50 ; + output_threshold_pct_fall : 50 ; + input_threshold_pct_rise : 50 ; + output_threshold_pct_rise : 50 ; + slew_lower_threshold_pct_fall : 30 ; + slew_upper_threshold_pct_fall : 70 ; + slew_derate_from_library : 0.5; + k_volt_cell_leakage_power : 0.0 ; + k_temp_cell_leakage_power : 0.0 ; + k_process_cell_leakage_power : 0.0 ; + k_volt_internal_power : 0.0 ; + k_temp_internal_power : 0.0 ; + k_process_internal_power : 0.0 ; + + capacitive_load_unit (1,pf) ; + voltage_unit : "1V" ; + current_unit : "1uA" ; + time_unit : "1ns" ; + leakage_power_unit : "1nW" ; + pulling_resistance_unit : "1kohm"; + /* + ------------------------------------------------------------------------------------------ + implicit units overview: + cell_area unit : "um" + internal_power unit : "1e-12 * J/toggle = 1 * uW/MHz" + (capacitive_load_unit * voltage_unit^2) per toggle event + ------------------------------------------------------------------------------------------ + */ + library_features(report_delay_calculation); + define_cell_area (pad_drivers,pad_driver_sites) ; + + lu_table_template(CLKTRAN_constraint_template) { + variable_1 : constrained_pin_transition; + index_1 ( "0.010, 0.050, 0.200, 0.400, 1.000" ); + } + lu_table_template(SRAM_load_template) { + variable_1 : total_output_net_capacitance; + index_1 ( "0.0008,0.0014,0.0051,0.0100,0.0339,0.0640" ); + } + lu_table_template(SIG2SRAM_constraint_template) { + variable_1 : related_pin_transition; + variable_2 : constrained_pin_transition; + index_1 ( "0.0056,0.0232,0.0400,0.0728,0.1280,0.2440,0.4760" ); + index_2 ( "0.0056,0.0232,0.0400,0.0728,0.1280,0.2440,0.4760" ); + } + + lu_table_template(SIG2SRAM_delay_template) { + variable_1 : input_net_transition; + variable_2 : total_output_net_capacitance; + index_1 ( "0.0056,0.0232,0.0400,0.0728,0.1280,0.2440,0.4760" ); + index_2 ( "0.0008,0.0014,0.0051,0.0100,0.0339,0.0640" ); + } + + type (D_31_0) { + base_type : array; + data_type : bit; + bit_width : 32; + bit_from : 31; + bit_to : 0; + downto : true; + } + + type (A_7_0) { + base_type : array; + data_type : bit; + bit_width : 8; + bit_from : 7; + bit_to : 0; + downto : true; + } + +cell(RM_IHPSG13_1P_256x32_c2_bm_bist) { +pg_pin (VDD) { + pg_type : primary_power; + voltage_name : VDD; +} +pg_pin (VDDARRAY) { + pg_type : primary_power; + voltage_name : VDDARRAY; +} +pg_pin (VSS) { + pg_type : primary_ground; + voltage_name : VSS; +} + +memory() { + type : ram; + address_width : 8; + word_width : 32; +} + +interface_timing : false; +bus_naming_style : "%s[%d]" ; +area : 49488.4992 ; + + pin(A_DLY) { + direction : input ; + capacitance : 0.00401111 ; + max_transition : "1" ; + related_power_pin : VDD; + related_ground_pin : VSS; + internal_power() { + rise_power("scalar") { + values (0); + } + fall_power("scalar") { + values (0); + } + } + } + +bus(A_ADDR) { + bus_type : A_7_0; + direction : input ; + capacitance : 0.00721489 ; + pin(A_ADDR[0]) { + capacitance : 0.00593979 ; + } + pin(A_ADDR[1]) { + capacitance : 0.00483009 ; + } + pin(A_ADDR[2]) { + capacitance : 0.006215 ; + } + pin(A_ADDR[3]) { + capacitance : 0.00766726 ; + } + pin(A_ADDR[4]) { + capacitance : 0.00488951 ; + } + pin(A_ADDR[5]) { + capacitance : 0.0091523 ; + } + pin(A_ADDR[6]) { + capacitance : 0.0109212 ; + } + max_transition : "0.476" ; + pin(A_ADDR[7:0]) { + related_power_pin : VDD; + related_ground_pin : VSS; + internal_power() { + when : "A_MEN"; + rise_power("scalar"){ + values (0.0100); + } + fall_power("scalar"){ + values (0.0047); + } + } + internal_power() { + when : "!A_MEN"; + rise_power("scalar"){ + values (0.0183); + } + fall_power("scalar"){ + values (0.0010); + } + } + } + timing() { + timing_type : setup_rising; + related_pin : "A_CLK"; + when : "((A_WEN | A_REN)& A_MEN)" + sdf_cond : "A_RW_ACCESS" + + rise_constraint("SIG2SRAM_constraint_template") { + index_1("0.0056,0.0232,0.0400,0.0728,0.1280,0.2440,0.4760"); + index_2("0.0056,0.0232,0.0400,0.0728,0.1280,0.2440,0.4760"); + values ("-0.4168,-0.3973,-0.3855,-0.3543,-0.3074,-0.2020,-0.0027",\ +"-0.4324,-0.4129,-0.4012,-0.3699,-0.3191,-0.2176,-0.0184",\ +"-0.4441,-0.4285,-0.4129,-0.3816,-0.3309,-0.2293,-0.0301",\ +"-0.4793,-0.4598,-0.4441,-0.4129,-0.3660,-0.2645,-0.0652",\ +"-0.5223,-0.5066,-0.4910,-0.4598,-0.4129,-0.3074,-0.1121",\ +"-0.6199,-0.6082,-0.5926,-0.5613,-0.5145,-0.4129,-0.2137",\ +"-0.8191,-0.8074,-0.7840,-0.7566,-0.7098,-0.6082,-0.4051"); + } + + fall_constraint("SIG2SRAM_constraint_template") { + index_1("0.0056,0.0232,0.0400,0.0728,0.1280,0.2440,0.4760"); + index_2("0.0056,0.0232,0.0400,0.0728,0.1280,0.2440,0.4760"); + values ("-0.3309,-0.3113,-0.2996,-0.2684,-0.2176,-0.1238,0.0637",\ +"-0.3465,-0.3309,-0.3152,-0.2840,-0.2332,-0.1395,0.0480",\ +"-0.3582,-0.3426,-0.3270,-0.2996,-0.2488,-0.1512,0.0324",\ +"-0.3895,-0.3738,-0.3582,-0.3309,-0.2801,-0.1863,0.0051",\ +"-0.4363,-0.4207,-0.4051,-0.3777,-0.3230,-0.2293,-0.0379",\ +"-0.5379,-0.5223,-0.5066,-0.4793,-0.4285,-0.3309,-0.1434",\ +"-0.7332,-0.7176,-0.7020,-0.6746,-0.6238,-0.5262,-0.3387"); + } + } + + + timing() { + timing_type : hold_rising; + related_pin : "A_CLK"; + when : "((A_WEN | A_REN)& A_MEN)" + sdf_cond : "A_RW_ACCESS" + + rise_constraint("SIG2SRAM_constraint_template") { + index_1("0.0056,0.0232,0.0400,0.0728,0.1280,0.2440,0.4760"); + index_2("0.0056,0.0232,0.0400,0.0728,0.1280,0.2440,0.4760"); + values ("0.5246,0.5051,0.4895,0.4582,0.4113,0.3059,0.1066",\ +"0.5402,0.5207,0.5051,0.4777,0.4270,0.3215,0.1223",\ +"0.5520,0.5324,0.5168,0.4895,0.4387,0.3371,0.1340",\ +"0.5832,0.5676,0.5520,0.5207,0.4738,0.3684,0.1691",\ +"0.6301,0.6105,0.5949,0.5676,0.5168,0.4113,0.2160",\ +"0.7316,0.7121,0.7004,0.6691,0.6223,0.5168,0.3176",\ +"0.9270,0.9230,0.8957,0.8645,0.8137,0.7121,0.5168"); + } + + fall_constraint("SIG2SRAM_constraint_template") { + index_1("0.0056,0.0232,0.0400,0.0728,0.1280,0.2440,0.4760"); + index_2("0.0056,0.0232,0.0400,0.0728,0.1280,0.2440,0.4760"); + values ("0.4309,0.4152,0.4035,0.3684,0.3215,0.2277,0.0363",\ +"0.4465,0.4309,0.4152,0.3879,0.3371,0.2395,0.0559",\ +"0.4582,0.4426,0.4309,0.3996,0.3488,0.2551,0.0715",\ +"0.4934,0.4777,0.4621,0.4348,0.3840,0.2863,0.0988",\ +"0.5363,0.5207,0.5051,0.4777,0.4270,0.3332,0.1418",\ +"0.6379,0.6262,0.6105,0.5793,0.5324,0.4348,0.2434",\ +"0.8332,0.8215,0.8059,0.7707,0.7238,0.6301,0.4387"); + } + } +} +pin(A_WEN) { + direction : input ; + capacitance : 0.00324098 ; + max_transition : "0.476" ; + related_power_pin : VDD; + related_ground_pin : VSS; + internal_power() { + when : "A_MEN"; + rise_power("scalar"){ + values (0.0047); + } + fall_power("scalar"){ + values (0.0041); + } + } + internal_power() { + when : "!A_MEN"; + rise_power("scalar"){ + values (0.0045); + } + fall_power("scalar"){ + values (0.0043); + } + } + timing() { + timing_type : setup_rising; + related_pin : "A_CLK"; + when : "A_MEN" + sdf_cond : "A_MEN" + + rise_constraint("SIG2SRAM_constraint_template") { + index_1("0.0056,0.0232,0.0400,0.0728,0.1280,0.2440,0.4760"); + index_2("0.0056,0.0232,0.0400,0.0728,0.1280,0.2440,0.4760"); + values ("0.2043,0.2199,0.2316,0.2629,0.3059,0.4113,0.6066",\ +"0.1887,0.2043,0.2160,0.2473,0.2941,0.3957,0.5949",\ +"0.1691,0.1848,0.2004,0.2316,0.2785,0.3801,0.5754",\ +"0.1379,0.1574,0.1691,0.2004,0.2473,0.3527,0.5480",\ +"0.0910,0.1066,0.1223,0.1535,0.2004,0.2980,0.4973",\ +"-0.0105,0.0051,0.0207,0.0520,0.0949,0.2004,0.3957",\ +"-0.2059,-0.1902,-0.1746,-0.1473,-0.1004,0.0051,0.2004"); + } + + fall_constraint("SIG2SRAM_constraint_template") { + index_1("0.0056,0.0232,0.0400,0.0728,0.1280,0.2440,0.4760"); + index_2("0.0056,0.0232,0.0400,0.0728,0.1280,0.2440,0.4760"); + values ("0.2941,0.3098,0.3215,0.3488,0.4035,0.4973,0.6887",\ +"0.2785,0.2941,0.3059,0.3332,0.3840,0.4816,0.6691",\ +"0.2629,0.2785,0.2902,0.3176,0.3684,0.4660,0.6535",\ +"0.2316,0.2473,0.2590,0.2863,0.3410,0.4348,0.6262",\ +"0.1848,0.2004,0.2121,0.2395,0.2902,0.3879,0.5754",\ +"0.0832,0.0988,0.1105,0.1379,0.1809,0.2746,0.4699",\ +"-0.1121,-0.0965,-0.0848,-0.0535,-0.0066,0.0910,0.2824"); + } + } + + + timing() { + timing_type : hold_rising; + related_pin : "A_CLK"; + when : "A_MEN" + sdf_cond : "A_MEN" + + rise_constraint("SIG2SRAM_constraint_template") { + index_1("0.0056,0.0232,0.0400,0.0728,0.1280,0.2440,0.4760"); + index_2("0.0056,0.0232,0.0400,0.0728,0.1280,0.2440,0.4760"); + values ("0.2473,0.2316,0.2160,0.1887,0.1379,0.0363,-0.1629",\ +"0.2629,0.2473,0.2316,0.2043,0.1535,0.0520,-0.1473",\ +"0.2785,0.2590,0.2434,0.2160,0.1652,0.0676,-0.1355",\ +"0.3098,0.2941,0.2785,0.2473,0.1965,0.0910,-0.1043",\ +"0.3527,0.3371,0.3215,0.2941,0.2434,0.1418,-0.0574",\ +"0.4582,0.4426,0.4270,0.3957,0.3488,0.2434,0.0480",\ +"0.6535,0.6379,0.6184,0.5910,0.5402,0.4426,0.2434"); + } + + fall_constraint("SIG2SRAM_constraint_template") { + index_1("0.0056,0.0232,0.0400,0.0728,0.1280,0.2440,0.4760"); + index_2("0.0056,0.0232,0.0400,0.0728,0.1280,0.2440,0.4760"); + values ("0.2395,0.2238,0.2121,0.1809,0.1301,0.0324,-0.1551",\ +"0.2551,0.2395,0.2277,0.1965,0.1457,0.0480,-0.1395",\ +"0.2668,0.2551,0.2395,0.2082,0.1574,0.0637,-0.1277",\ +"0.3020,0.2863,0.2707,0.2395,0.1887,0.0910,-0.0965",\ +"0.3449,0.3293,0.3176,0.2863,0.2355,0.1379,-0.0496",\ +"0.4504,0.4348,0.4191,0.3879,0.3371,0.2395,0.0559",\ +"0.6457,0.6301,0.6145,0.5871,0.5324,0.4309,0.2512"); + } + } + } +pin(A_REN) { + direction : input ; + capacitance : 0.00381634 ; + max_transition : "0.476" ; + related_power_pin : VDD; + related_ground_pin : VSS; + internal_power() { + when : "A_MEN"; + rise_power("scalar"){ + values (0.0061); + } + fall_power("scalar"){ + values (0.0022); + } + } + internal_power() { + when : "!A_MEN"; + rise_power("scalar"){ + values (0.0063); + } + fall_power("scalar"){ + values (0.0027); + } + } + timing() { + timing_type : setup_rising; + related_pin : "A_CLK"; + when : "A_MEN" + sdf_cond : "A_MEN" + + rise_constraint("SIG2SRAM_constraint_template") { + index_1("0.0056,0.0232,0.0400,0.0728,0.1280,0.2440,0.4760"); + index_2("0.0056,0.0232,0.0400,0.0728,0.1280,0.2440,0.4760"); + values ("-0.0301,-0.0145,0.0012,0.0324,0.0793,0.1809,0.3762",\ +"-0.0457,-0.0301,-0.0145,0.0168,0.0637,0.1613,0.3605",\ +"-0.0574,-0.0418,-0.0262,0.0051,0.0520,0.1496,0.3449",\ +"-0.0926,-0.0730,-0.0574,-0.0262,0.0207,0.1184,0.3137",\ +"-0.1395,-0.1238,-0.1082,-0.0770,-0.0301,0.0715,0.2707",\ +"-0.2410,-0.2254,-0.2098,-0.1746,-0.1355,-0.0340,0.1652",\ +"-0.4402,-0.4207,-0.4051,-0.3738,-0.3270,-0.2293,-0.0340"); + } + + fall_constraint("SIG2SRAM_constraint_template") { + index_1("0.0056,0.0232,0.0400,0.0728,0.1280,0.2440,0.4760"); + index_2("0.0056,0.0232,0.0400,0.0728,0.1280,0.2440,0.4760"); + values ("0.0988,0.1145,0.1262,0.1535,0.2043,0.3020,0.4855",\ +"0.0832,0.0988,0.1105,0.1418,0.1848,0.2824,0.4738",\ +"0.0676,0.0832,0.0949,0.1262,0.1730,0.2668,0.4621",\ +"0.0402,0.0559,0.0676,0.0988,0.1457,0.2434,0.4191",\ +"-0.0105,0.0012,0.0168,0.0480,0.0988,0.1965,0.3840",\ +"-0.1160,-0.0965,-0.0848,-0.0535,-0.0066,0.0988,0.2824",\ +"-0.3113,-0.2957,-0.2801,-0.2527,-0.2059,-0.1043,0.0832"); + } + } + + + timing() { + timing_type : hold_rising; + related_pin : "A_CLK"; + when : "A_MEN" + sdf_cond : "A_MEN" + + rise_constraint("SIG2SRAM_constraint_template") { + index_1("0.0056,0.0232,0.0400,0.0728,0.1280,0.2440,0.4760"); + index_2("0.0056,0.0232,0.0400,0.0728,0.1280,0.2440,0.4760"); + values ("0.2707,0.2551,0.2395,0.2121,0.1613,0.0598,-0.1395",\ +"0.2863,0.2707,0.2551,0.2238,0.1730,0.0715,-0.1238",\ +"0.2980,0.2824,0.2668,0.2395,0.1887,0.0871,-0.1121",\ +"0.3332,0.3176,0.3020,0.2707,0.2199,0.1184,-0.0809",\ +"0.3762,0.3605,0.3449,0.3176,0.2668,0.1613,-0.0340",\ +"0.4816,0.4621,0.4504,0.4191,0.3723,0.2629,0.0715",\ +"0.6770,0.6613,0.6418,0.6184,0.5637,0.4699,0.2629"); + } + + fall_constraint("SIG2SRAM_constraint_template") { + index_1("0.0056,0.0232,0.0400,0.0728,0.1280,0.2440,0.4760"); + index_2("0.0056,0.0232,0.0400,0.0728,0.1280,0.2440,0.4760"); + values ("0.2590,0.2434,0.2316,0.2004,0.1457,0.0520,-0.1355",\ +"0.2746,0.2590,0.2434,0.2160,0.1613,0.0676,-0.1199",\ +"0.2863,0.2707,0.2590,0.2277,0.1730,0.0832,-0.1082",\ +"0.3215,0.3059,0.2902,0.2590,0.2082,0.1105,-0.0770",\ +"0.3645,0.3488,0.3332,0.3059,0.2551,0.1535,-0.0340",\ +"0.4699,0.4543,0.4387,0.4074,0.3605,0.2551,0.0715",\ +"0.6652,0.6496,0.6340,0.6027,0.5520,0.4621,0.2707"); + } + } + } +pin(A_MEN) { + direction : input ; + capacitance : 0.00309605 ; + max_transition : "0.476" ; + related_power_pin : VDD; + related_ground_pin : VSS; + internal_power() { + rise_power("scalar"){ + values (0.0870); + } + fall_power("scalar"){ + values (0.0053); + } + } + timing() { + timing_type : setup_rising; + related_pin : "A_CLK"; + + rise_constraint("SIG2SRAM_constraint_template") { + index_1("0.0056,0.0232,0.0400,0.0728,0.1280,0.2440,0.4760"); + index_2("0.0056,0.0232,0.0400,0.0728,0.1280,0.2440,0.4760"); + values ("0.2043,0.2199,0.2316,0.2668,0.3098,0.4152,0.6066",\ +"0.1887,0.2043,0.2199,0.2512,0.2941,0.3996,0.5949",\ +"0.1730,0.1887,0.2043,0.2355,0.2824,0.3840,0.5793",\ +"0.1418,0.1574,0.1730,0.2043,0.2512,0.3566,0.5480",\ +"0.0949,0.1105,0.1262,0.1574,0.2043,0.3020,0.5051",\ +"-0.0066,0.0090,0.0246,0.0520,0.0988,0.2043,0.3996",\ +"-0.2020,-0.1863,-0.1746,-0.1434,-0.0965,0.0090,0.2082"); + } + + fall_constraint("SIG2SRAM_constraint_template") { + index_1("0.0056,0.0232,0.0400,0.0728,0.1280,0.2440,0.4760"); + index_2("0.0056,0.0232,0.0400,0.0728,0.1280,0.2440,0.4760"); + values ("0.2980,0.3137,0.3254,0.3527,0.4035,0.5012,0.6887",\ +"0.2824,0.2980,0.3098,0.3371,0.3879,0.4855,0.6730",\ +"0.2668,0.2824,0.2941,0.3215,0.3723,0.4699,0.6574",\ +"0.2355,0.2473,0.2629,0.2902,0.3410,0.4387,0.6262",\ +"0.1887,0.2004,0.2160,0.2395,0.2941,0.3918,0.5793",\ +"0.0871,0.1027,0.1145,0.1418,0.1848,0.2746,0.4816",\ +"-0.1082,-0.0965,-0.0809,-0.0496,-0.0027,0.0949,0.2863"); + } + } + + + timing() { + timing_type : hold_rising; + related_pin : "A_CLK"; + + rise_constraint("SIG2SRAM_constraint_template") { + index_1("0.0056,0.0232,0.0400,0.0728,0.1280,0.2440,0.4760"); + index_2("0.0056,0.0232,0.0400,0.0728,0.1280,0.2440,0.4760"); + values ("0.2512,0.2355,0.2199,0.1926,0.1418,0.0402,-0.1590",\ +"0.2668,0.2512,0.2355,0.2082,0.1574,0.0559,-0.1434",\ +"0.2824,0.2629,0.2512,0.2199,0.1691,0.0715,-0.1316",\ +"0.3137,0.2980,0.2824,0.2512,0.2004,0.0988,-0.0965",\ +"0.3566,0.3410,0.3254,0.2980,0.2473,0.1418,-0.0535",\ +"0.4621,0.4426,0.4309,0.3996,0.3527,0.2473,0.0520",\ +"0.6574,0.6418,0.6262,0.5949,0.5441,0.4465,0.2473"); + } + + fall_constraint("SIG2SRAM_constraint_template") { + index_1("0.0056,0.0232,0.0400,0.0728,0.1280,0.2440,0.4760"); + index_2("0.0056,0.0232,0.0400,0.0728,0.1280,0.2440,0.4760"); + values ("0.2395,0.2238,0.2121,0.1809,0.1301,0.0324,-0.1551",\ +"0.2551,0.2434,0.2277,0.1965,0.1457,0.0480,-0.1395",\ +"0.2707,0.2551,0.2395,0.2082,0.1574,0.0637,-0.1277",\ +"0.3020,0.2863,0.2707,0.2434,0.1926,0.0910,-0.0965",\ +"0.3449,0.3332,0.3176,0.2863,0.2355,0.1379,-0.0496",\ +"0.4504,0.4348,0.4230,0.3918,0.3410,0.2434,0.0559",\ +"0.6457,0.6301,0.6145,0.5910,0.5324,0.4387,0.2512"); + } + } + } +bus(A_BM) { + bus_type : D_31_0; + direction : input ; + capacitance : 0.00285703 ; + max_transition : "0.476" ; + pin(A_BM[31:0]) { + related_power_pin : VDD; + related_ground_pin : VSS; + internal_power() { + when : "A_MEN"; + rise_power("scalar"){ + values (0.1176); + } + fall_power("scalar"){ + values (0.0493); + } + } + internal_power() { + when : "!A_MEN"; + rise_power("scalar"){ + values (0.1174); + } + fall_power("scalar"){ + values (0.0488); + } + } + } + timing() { + timing_type : setup_rising; + related_pin : "A_CLK"; + when : "(A_WEN & A_MEN)" + sdf_cond : "A_RW_ACCESS" + + rise_constraint("SIG2SRAM_constraint_template") { + index_1("0.0056,0.0232,0.0400,0.0728,0.1280,0.2440,0.4760"); + index_2("0.0056,0.0232,0.0400,0.0728,0.1280,0.2440,0.4760"); + values ("-0.4430,-0.4264,-0.4137,-0.3815,-0.3346,-0.2301,-0.0378",\ +"-0.4480,-0.4314,-0.4187,-0.3865,-0.3396,-0.2351,-0.0428",\ +"-0.4525,-0.4359,-0.4232,-0.3910,-0.3441,-0.2396,-0.0472",\ +"-0.4616,-0.4450,-0.4323,-0.4001,-0.3532,-0.2487,-0.0564",\ +"-0.4688,-0.4522,-0.4395,-0.4073,-0.3604,-0.2559,-0.0635",\ +"-0.4985,-0.4819,-0.4692,-0.4370,-0.3901,-0.2856,-0.0932",\ +"-0.5566,-0.5400,-0.5273,-0.4950,-0.4482,-0.3437,-0.1513"); + } + + fall_constraint("SIG2SRAM_constraint_template") { + index_1("0.0056,0.0232,0.0400,0.0728,0.1280,0.2440,0.4760"); + index_2("0.0056,0.0232,0.0400,0.0728,0.1280,0.2440,0.4760"); + values ("-0.4108,-0.3952,-0.3825,-0.3542,-0.3034,-0.2047,-0.0260",\ +"-0.4158,-0.4002,-0.3875,-0.3592,-0.3084,-0.2097,-0.0310",\ +"-0.4203,-0.4047,-0.3920,-0.3636,-0.3129,-0.2142,-0.0355",\ +"-0.4294,-0.4138,-0.4011,-0.3728,-0.3220,-0.2233,-0.0446",\ +"-0.4366,-0.4210,-0.4083,-0.3800,-0.3292,-0.2305,-0.0518",\ +"-0.4663,-0.4506,-0.4379,-0.4096,-0.3588,-0.2602,-0.0815",\ +"-0.5243,-0.5087,-0.4960,-0.4677,-0.4169,-0.3183,-0.1396"); + } + } + + + timing() { + timing_type : hold_rising; + related_pin : "A_CLK"; + when : "(A_WEN & A_MEN)" + sdf_cond : "A_RW_ACCESS" + + rise_constraint("SIG2SRAM_constraint_template") { + index_1("0.0056,0.0232,0.0400,0.0728,0.1280,0.2440,0.4760"); + index_2("0.0056,0.0232,0.0400,0.0728,0.1280,0.2440,0.4760"); + values ("0.5521,0.5365,0.5238,0.4916,0.4427,0.3441,0.1478",\ +"0.5571,0.5415,0.5288,0.4966,0.4477,0.3491,0.1528",\ +"0.5616,0.5460,0.5333,0.5010,0.4522,0.3536,0.1573",\ +"0.5707,0.5551,0.5424,0.5102,0.4613,0.3627,0.1664",\ +"0.5779,0.5623,0.5496,0.5174,0.4685,0.3699,0.1736",\ +"0.6076,0.5920,0.5793,0.5470,0.4982,0.3996,0.2033",\ +"0.6656,0.6500,0.6373,0.6051,0.5563,0.4576,0.2614"); + } + + fall_constraint("SIG2SRAM_constraint_template") { + index_1("0.0056,0.0232,0.0400,0.0728,0.1280,0.2440,0.4760"); + index_2("0.0056,0.0232,0.0400,0.0728,0.1280,0.2440,0.4760"); + values ("0.5121,0.4974,0.4838,0.4554,0.4047,0.3119,0.1234",\ +"0.5171,0.5024,0.4888,0.4604,0.4097,0.3169,0.1284",\ +"0.5216,0.5069,0.4932,0.4649,0.4141,0.3214,0.1329",\ +"0.5307,0.5160,0.5024,0.4740,0.4233,0.3305,0.1420",\ +"0.5379,0.5232,0.5096,0.4812,0.4305,0.3377,0.1492",\ +"0.5675,0.5529,0.5392,0.5109,0.4601,0.3673,0.1789",\ +"0.6256,0.6110,0.5973,0.5690,0.5182,0.4254,0.2369"); + } + } +} + pin(A_CLK) { + direction : input; + capacitance : 0.00380014; + max_transition : "0.476"; + clock : "true" ; + pin_func_type : active_rising ; + + timing () { + timing_type : "min_pulse_width"; + related_pin : "A_CLK"; + rise_constraint("CLKTRAN_constraint_template") { + index_1("0.0056,0.476"); + values("0.21,0.21"); + } + } + + related_power_pin : VDD; + related_ground_pin : VSS; + + internal_power() { + when : "!A_MEN & !A_WEN & !A_REN"; + rise_power("scalar"){ + values (0); + } + fall_power("scalar"){ + values (0); + } + } + internal_power() { + when : "!A_MEN & A_WEN & !A_REN"; + rise_power("scalar"){ + values (0.5036); + } + fall_power("scalar"){ + values (0); + } + } + internal_power() { + when : "A_MEN & A_WEN & !A_REN"; + rise_power("scalar"){ + values (33.4496); + } + fall_power("scalar"){ + values (0); + } + } + internal_power() { + when : "A_MEN & A_WEN & A_REN"; + rise_power("scalar"){ + values (37.7280); + } + fall_power("scalar"){ + values (0); + } + } + internal_power() { + when : "A_MEN & !A_WEN & A_REN"; + rise_power("scalar"){ + values (26.0060); + } + fall_power("scalar"){ + values (0); + } + } + internal_power() { + when : "!A_MEN & !A_WEN & A_REN"; + rise_power("scalar"){ + values (0.3024); + } + fall_power("scalar"){ + values (0); + } + } + internal_power() { + when : "!A_MEN & A_WEN & A_REN"; + rise_power("scalar"){ + values (1.1356); + } + fall_power("scalar"){ + values (0); + } + } + internal_power() { + when : "A_MEN & !A_WEN & !A_REN"; + rise_power("scalar"){ + values (0); + } + fall_power("scalar"){ + values (0); + } + } + } + bus(A_DIN) { + bus_type : D_31_0; + direction : input ; + capacitance : 0.00365723 ; + memory_write() { + address : A_ADDR ; + clocked_on : A_CLK; + } + + max_transition : "0.476" ; + pin(A_DIN[31:0]) { + related_power_pin : VDD; + related_ground_pin : VSS; + internal_power() { + when : "A_MEN"; + rise_power("scalar"){ + values (0.1176); + } + fall_power("scalar"){ + values (0.0493); + } + } + internal_power() { + when : "!A_MEN"; + rise_power("scalar"){ + values (0.1174); + } + fall_power("scalar"){ + values (0.0488); + } + } + } + timing() { + timing_type : setup_rising; + related_pin : "A_CLK"; + when : "(A_WEN & A_MEN)"; + sdf_cond : "A_W_ACCESS"; + + rise_constraint("SIG2SRAM_constraint_template") { + index_1("0.0056,0.0232,0.0400,0.0728,0.1280,0.2440,0.4760"); + index_2("0.0056,0.0232,0.0400,0.0728,0.1280,0.2440,0.4760"); + values ("-0.4430,-0.4264,-0.4137,-0.3815,-0.3346,-0.2301,-0.0378",\ +"-0.4480,-0.4314,-0.4187,-0.3865,-0.3396,-0.2351,-0.0428",\ +"-0.4525,-0.4359,-0.4232,-0.3910,-0.3441,-0.2396,-0.0472",\ +"-0.4616,-0.4450,-0.4323,-0.4001,-0.3532,-0.2487,-0.0564",\ +"-0.4688,-0.4522,-0.4395,-0.4073,-0.3604,-0.2559,-0.0635",\ +"-0.4985,-0.4819,-0.4692,-0.4370,-0.3901,-0.2856,-0.0932",\ +"-0.5566,-0.5400,-0.5273,-0.4950,-0.4482,-0.3437,-0.1513"); + } + + fall_constraint("SIG2SRAM_constraint_template") { + index_1("0.0056,0.0232,0.0400,0.0728,0.1280,0.2440,0.4760"); + index_2("0.0056,0.0232,0.0400,0.0728,0.1280,0.2440,0.4760"); + values ("-0.4108,-0.3952,-0.3825,-0.3542,-0.3034,-0.2047,-0.0260",\ +"-0.4158,-0.4002,-0.3875,-0.3592,-0.3084,-0.2097,-0.0310",\ +"-0.4203,-0.4047,-0.3920,-0.3636,-0.3129,-0.2142,-0.0355",\ +"-0.4294,-0.4138,-0.4011,-0.3728,-0.3220,-0.2233,-0.0446",\ +"-0.4366,-0.4210,-0.4083,-0.3800,-0.3292,-0.2305,-0.0518",\ +"-0.4663,-0.4506,-0.4379,-0.4096,-0.3588,-0.2602,-0.0815",\ +"-0.5243,-0.5087,-0.4960,-0.4677,-0.4169,-0.3183,-0.1396"); + } + } + + timing() { + timing_type : hold_rising; + related_pin : "A_CLK"; + when : "(A_WEN & A_MEN)"; + sdf_cond : "A_W_ACCESS"; + + rise_constraint("SIG2SRAM_constraint_template") { + index_1("0.0056,0.0232,0.0400,0.0728,0.1280,0.2440,0.4760"); + index_2("0.0056,0.0232,0.0400,0.0728,0.1280,0.2440,0.4760"); + values ("0.5521,0.5365,0.5238,0.4916,0.4427,0.3441,0.1478",\ +"0.5571,0.5415,0.5288,0.4966,0.4477,0.3491,0.1528",\ +"0.5616,0.5460,0.5333,0.5010,0.4522,0.3536,0.1573",\ +"0.5707,0.5551,0.5424,0.5102,0.4613,0.3627,0.1664",\ +"0.5779,0.5623,0.5496,0.5174,0.4685,0.3699,0.1736",\ +"0.6076,0.5920,0.5793,0.5470,0.4982,0.3996,0.2033",\ +"0.6656,0.6500,0.6373,0.6051,0.5563,0.4576,0.2614"); + } + + fall_constraint("SIG2SRAM_constraint_template") { + index_1("0.0056,0.0232,0.0400,0.0728,0.1280,0.2440,0.4760"); + index_2("0.0056,0.0232,0.0400,0.0728,0.1280,0.2440,0.4760"); + values ("0.5121,0.4974,0.4838,0.4554,0.4047,0.3119,0.1234",\ +"0.5171,0.5024,0.4888,0.4604,0.4097,0.3169,0.1284",\ +"0.5216,0.5069,0.4932,0.4649,0.4141,0.3214,0.1329",\ +"0.5307,0.5160,0.5024,0.4740,0.4233,0.3305,0.1420",\ +"0.5379,0.5232,0.5096,0.4812,0.4305,0.3377,0.1492",\ +"0.5675,0.5529,0.5392,0.5109,0.4601,0.3673,0.1789",\ +"0.6256,0.6110,0.5973,0.5690,0.5182,0.4254,0.2369"); + } + } + } + + pin(A_BIST_EN) { + direction : input ; + capacitance : 0.00401111 ; + max_transition : "1" ; + related_power_pin : VDD; + related_ground_pin : VSS; + internal_power() { + rise_power("scalar") { + values (0); + } + fall_power("scalar") { + values (0); + } + } + } + +bus(A_BIST_ADDR) { + bus_type : A_7_0; + direction : input ; + capacitance : 0.00721489 ; + pin(A_BIST_ADDR[0]) { + capacitance : 0.00593979 ; + } + pin(A_BIST_ADDR[1]) { + capacitance : 0.00483009 ; + } + pin(A_BIST_ADDR[2]) { + capacitance : 0.006215 ; + } + pin(A_BIST_ADDR[3]) { + capacitance : 0.00766726 ; + } + pin(A_BIST_ADDR[4]) { + capacitance : 0.00488951 ; + } + pin(A_BIST_ADDR[5]) { + capacitance : 0.0091523 ; + } + pin(A_BIST_ADDR[6]) { + capacitance : 0.0109212 ; + } + max_transition : "0.476" ; + pin(A_BIST_ADDR[7:0]) { + related_power_pin : VDD; + related_ground_pin : VSS; + internal_power() { + when : "A_BIST_MEN"; + rise_power("scalar"){ + values (0.0100); + } + fall_power("scalar"){ + values (0.0047); + } + } + internal_power() { + when : "!A_BIST_MEN"; + rise_power("scalar"){ + values (0.0183); + } + fall_power("scalar"){ + values (0.0010); + } + } + } + timing() { + timing_type : setup_rising; + related_pin : "A_BIST_CLK"; + when : "((A_BIST_WEN | A_BIST_REN)& A_BIST_MEN)" + sdf_cond : "A_BIST_RW_ACCESS" + + rise_constraint("SIG2SRAM_constraint_template") { + index_1("0.0056,0.0232,0.0400,0.0728,0.1280,0.2440,0.4760"); + index_2("0.0056,0.0232,0.0400,0.0728,0.1280,0.2440,0.4760"); + values ("-0.4168,-0.3973,-0.3855,-0.3543,-0.3074,-0.2020,-0.0027",\ +"-0.4324,-0.4129,-0.4012,-0.3699,-0.3191,-0.2176,-0.0184",\ +"-0.4441,-0.4285,-0.4129,-0.3816,-0.3309,-0.2293,-0.0301",\ +"-0.4793,-0.4598,-0.4441,-0.4129,-0.3660,-0.2645,-0.0652",\ +"-0.5223,-0.5066,-0.4910,-0.4598,-0.4129,-0.3074,-0.1121",\ +"-0.6199,-0.6082,-0.5926,-0.5613,-0.5145,-0.4129,-0.2137",\ +"-0.8191,-0.8074,-0.7840,-0.7566,-0.7098,-0.6082,-0.4051"); + } + + fall_constraint("SIG2SRAM_constraint_template") { + index_1("0.0056,0.0232,0.0400,0.0728,0.1280,0.2440,0.4760"); + index_2("0.0056,0.0232,0.0400,0.0728,0.1280,0.2440,0.4760"); + values ("-0.3309,-0.3113,-0.2996,-0.2684,-0.2176,-0.1238,0.0637",\ +"-0.3465,-0.3309,-0.3152,-0.2840,-0.2332,-0.1395,0.0480",\ +"-0.3582,-0.3426,-0.3270,-0.2996,-0.2488,-0.1512,0.0324",\ +"-0.3895,-0.3738,-0.3582,-0.3309,-0.2801,-0.1863,0.0051",\ +"-0.4363,-0.4207,-0.4051,-0.3777,-0.3230,-0.2293,-0.0379",\ +"-0.5379,-0.5223,-0.5066,-0.4793,-0.4285,-0.3309,-0.1434",\ +"-0.7332,-0.7176,-0.7020,-0.6746,-0.6238,-0.5262,-0.3387"); + } + } + + + timing() { + timing_type : hold_rising; + related_pin : "A_BIST_CLK"; + when : "((A_BIST_WEN | A_BIST_REN)& A_BIST_MEN)" + sdf_cond : "A_BIST_RW_ACCESS" + + rise_constraint("SIG2SRAM_constraint_template") { + index_1("0.0056,0.0232,0.0400,0.0728,0.1280,0.2440,0.4760"); + index_2("0.0056,0.0232,0.0400,0.0728,0.1280,0.2440,0.4760"); + values ("0.5246,0.5051,0.4895,0.4582,0.4113,0.3059,0.1066",\ +"0.5402,0.5207,0.5051,0.4777,0.4270,0.3215,0.1223",\ +"0.5520,0.5324,0.5168,0.4895,0.4387,0.3371,0.1340",\ +"0.5832,0.5676,0.5520,0.5207,0.4738,0.3684,0.1691",\ +"0.6301,0.6105,0.5949,0.5676,0.5168,0.4113,0.2160",\ +"0.7316,0.7121,0.7004,0.6691,0.6223,0.5168,0.3176",\ +"0.9270,0.9230,0.8957,0.8645,0.8137,0.7121,0.5168"); + } + + fall_constraint("SIG2SRAM_constraint_template") { + index_1("0.0056,0.0232,0.0400,0.0728,0.1280,0.2440,0.4760"); + index_2("0.0056,0.0232,0.0400,0.0728,0.1280,0.2440,0.4760"); + values ("0.4309,0.4152,0.4035,0.3684,0.3215,0.2277,0.0363",\ +"0.4465,0.4309,0.4152,0.3879,0.3371,0.2395,0.0559",\ +"0.4582,0.4426,0.4309,0.3996,0.3488,0.2551,0.0715",\ +"0.4934,0.4777,0.4621,0.4348,0.3840,0.2863,0.0988",\ +"0.5363,0.5207,0.5051,0.4777,0.4270,0.3332,0.1418",\ +"0.6379,0.6262,0.6105,0.5793,0.5324,0.4348,0.2434",\ +"0.8332,0.8215,0.8059,0.7707,0.7238,0.6301,0.4387"); + } + } +} +pin(A_BIST_WEN) { + direction : input ; + capacitance : 0.00324098 ; + max_transition : "0.476" ; + related_power_pin : VDD; + related_ground_pin : VSS; + internal_power() { + when : "A_BIST_MEN"; + rise_power("scalar"){ + values (0.0047); + } + fall_power("scalar"){ + values (0.0041); + } + } + internal_power() { + when : "!A_BIST_MEN"; + rise_power("scalar"){ + values (0.0045); + } + fall_power("scalar"){ + values (0.0043); + } + } + timing() { + timing_type : setup_rising; + related_pin : "A_BIST_CLK"; + when : "A_BIST_MEN" + sdf_cond : "A_BIST_MEN" + + rise_constraint("SIG2SRAM_constraint_template") { + index_1("0.0056,0.0232,0.0400,0.0728,0.1280,0.2440,0.4760"); + index_2("0.0056,0.0232,0.0400,0.0728,0.1280,0.2440,0.4760"); + values ("0.2043,0.2199,0.2316,0.2629,0.3059,0.4113,0.6066",\ +"0.1887,0.2043,0.2160,0.2473,0.2941,0.3957,0.5949",\ +"0.1691,0.1848,0.2004,0.2316,0.2785,0.3801,0.5754",\ +"0.1379,0.1574,0.1691,0.2004,0.2473,0.3527,0.5480",\ +"0.0910,0.1066,0.1223,0.1535,0.2004,0.2980,0.4973",\ +"-0.0105,0.0051,0.0207,0.0520,0.0949,0.2004,0.3957",\ +"-0.2059,-0.1902,-0.1746,-0.1473,-0.1004,0.0051,0.2004"); + } + + fall_constraint("SIG2SRAM_constraint_template") { + index_1("0.0056,0.0232,0.0400,0.0728,0.1280,0.2440,0.4760"); + index_2("0.0056,0.0232,0.0400,0.0728,0.1280,0.2440,0.4760"); + values ("0.2941,0.3098,0.3215,0.3488,0.4035,0.4973,0.6887",\ +"0.2785,0.2941,0.3059,0.3332,0.3840,0.4816,0.6691",\ +"0.2629,0.2785,0.2902,0.3176,0.3684,0.4660,0.6535",\ +"0.2316,0.2473,0.2590,0.2863,0.3410,0.4348,0.6262",\ +"0.1848,0.2004,0.2121,0.2395,0.2902,0.3879,0.5754",\ +"0.0832,0.0988,0.1105,0.1379,0.1809,0.2746,0.4699",\ +"-0.1121,-0.0965,-0.0848,-0.0535,-0.0066,0.0910,0.2824"); + } + } + + + timing() { + timing_type : hold_rising; + related_pin : "A_BIST_CLK"; + when : "A_BIST_MEN" + sdf_cond : "A_BIST_MEN" + + rise_constraint("SIG2SRAM_constraint_template") { + index_1("0.0056,0.0232,0.0400,0.0728,0.1280,0.2440,0.4760"); + index_2("0.0056,0.0232,0.0400,0.0728,0.1280,0.2440,0.4760"); + values ("0.2473,0.2316,0.2160,0.1887,0.1379,0.0363,-0.1629",\ +"0.2629,0.2473,0.2316,0.2043,0.1535,0.0520,-0.1473",\ +"0.2785,0.2590,0.2434,0.2160,0.1652,0.0676,-0.1355",\ +"0.3098,0.2941,0.2785,0.2473,0.1965,0.0910,-0.1043",\ +"0.3527,0.3371,0.3215,0.2941,0.2434,0.1418,-0.0574",\ +"0.4582,0.4426,0.4270,0.3957,0.3488,0.2434,0.0480",\ +"0.6535,0.6379,0.6184,0.5910,0.5402,0.4426,0.2434"); + } + + fall_constraint("SIG2SRAM_constraint_template") { + index_1("0.0056,0.0232,0.0400,0.0728,0.1280,0.2440,0.4760"); + index_2("0.0056,0.0232,0.0400,0.0728,0.1280,0.2440,0.4760"); + values ("0.2395,0.2238,0.2121,0.1809,0.1301,0.0324,-0.1551",\ +"0.2551,0.2395,0.2277,0.1965,0.1457,0.0480,-0.1395",\ +"0.2668,0.2551,0.2395,0.2082,0.1574,0.0637,-0.1277",\ +"0.3020,0.2863,0.2707,0.2395,0.1887,0.0910,-0.0965",\ +"0.3449,0.3293,0.3176,0.2863,0.2355,0.1379,-0.0496",\ +"0.4504,0.4348,0.4191,0.3879,0.3371,0.2395,0.0559",\ +"0.6457,0.6301,0.6145,0.5871,0.5324,0.4309,0.2512"); + } + } + } +pin(A_BIST_REN) { + direction : input ; + capacitance : 0.00381634 ; + max_transition : "0.476" ; + related_power_pin : VDD; + related_ground_pin : VSS; + internal_power() { + when : "A_BIST_MEN"; + rise_power("scalar"){ + values (0.0061); + } + fall_power("scalar"){ + values (0.0022); + } + } + internal_power() { + when : "!A_BIST_MEN"; + rise_power("scalar"){ + values (0.0063); + } + fall_power("scalar"){ + values (0.0027); + } + } + timing() { + timing_type : setup_rising; + related_pin : "A_BIST_CLK"; + when : "A_BIST_MEN" + sdf_cond : "A_BIST_MEN" + + rise_constraint("SIG2SRAM_constraint_template") { + index_1("0.0056,0.0232,0.0400,0.0728,0.1280,0.2440,0.4760"); + index_2("0.0056,0.0232,0.0400,0.0728,0.1280,0.2440,0.4760"); + values ("-0.0301,-0.0145,0.0012,0.0324,0.0793,0.1809,0.3762",\ +"-0.0457,-0.0301,-0.0145,0.0168,0.0637,0.1613,0.3605",\ +"-0.0574,-0.0418,-0.0262,0.0051,0.0520,0.1496,0.3449",\ +"-0.0926,-0.0730,-0.0574,-0.0262,0.0207,0.1184,0.3137",\ +"-0.1395,-0.1238,-0.1082,-0.0770,-0.0301,0.0715,0.2707",\ +"-0.2410,-0.2254,-0.2098,-0.1746,-0.1355,-0.0340,0.1652",\ +"-0.4402,-0.4207,-0.4051,-0.3738,-0.3270,-0.2293,-0.0340"); + } + + fall_constraint("SIG2SRAM_constraint_template") { + index_1("0.0056,0.0232,0.0400,0.0728,0.1280,0.2440,0.4760"); + index_2("0.0056,0.0232,0.0400,0.0728,0.1280,0.2440,0.4760"); + values ("0.0988,0.1145,0.1262,0.1535,0.2043,0.3020,0.4855",\ +"0.0832,0.0988,0.1105,0.1418,0.1848,0.2824,0.4738",\ +"0.0676,0.0832,0.0949,0.1262,0.1730,0.2668,0.4621",\ +"0.0402,0.0559,0.0676,0.0988,0.1457,0.2434,0.4191",\ +"-0.0105,0.0012,0.0168,0.0480,0.0988,0.1965,0.3840",\ +"-0.1160,-0.0965,-0.0848,-0.0535,-0.0066,0.0988,0.2824",\ +"-0.3113,-0.2957,-0.2801,-0.2527,-0.2059,-0.1043,0.0832"); + } + } + + + timing() { + timing_type : hold_rising; + related_pin : "A_BIST_CLK"; + when : "A_BIST_MEN" + sdf_cond : "A_BIST_MEN" + + rise_constraint("SIG2SRAM_constraint_template") { + index_1("0.0056,0.0232,0.0400,0.0728,0.1280,0.2440,0.4760"); + index_2("0.0056,0.0232,0.0400,0.0728,0.1280,0.2440,0.4760"); + values ("0.2707,0.2551,0.2395,0.2121,0.1613,0.0598,-0.1395",\ +"0.2863,0.2707,0.2551,0.2238,0.1730,0.0715,-0.1238",\ +"0.2980,0.2824,0.2668,0.2395,0.1887,0.0871,-0.1121",\ +"0.3332,0.3176,0.3020,0.2707,0.2199,0.1184,-0.0809",\ +"0.3762,0.3605,0.3449,0.3176,0.2668,0.1613,-0.0340",\ +"0.4816,0.4621,0.4504,0.4191,0.3723,0.2629,0.0715",\ +"0.6770,0.6613,0.6418,0.6184,0.5637,0.4699,0.2629"); + } + + fall_constraint("SIG2SRAM_constraint_template") { + index_1("0.0056,0.0232,0.0400,0.0728,0.1280,0.2440,0.4760"); + index_2("0.0056,0.0232,0.0400,0.0728,0.1280,0.2440,0.4760"); + values ("0.2590,0.2434,0.2316,0.2004,0.1457,0.0520,-0.1355",\ +"0.2746,0.2590,0.2434,0.2160,0.1613,0.0676,-0.1199",\ +"0.2863,0.2707,0.2590,0.2277,0.1730,0.0832,-0.1082",\ +"0.3215,0.3059,0.2902,0.2590,0.2082,0.1105,-0.0770",\ +"0.3645,0.3488,0.3332,0.3059,0.2551,0.1535,-0.0340",\ +"0.4699,0.4543,0.4387,0.4074,0.3605,0.2551,0.0715",\ +"0.6652,0.6496,0.6340,0.6027,0.5520,0.4621,0.2707"); + } + } + } +pin(A_BIST_MEN) { + direction : input ; + capacitance : 0.00309605 ; + max_transition : "0.476" ; + related_power_pin : VDD; + related_ground_pin : VSS; + internal_power() { + rise_power("scalar"){ + values (0.0870); + } + fall_power("scalar"){ + values (0.0053); + } + } + timing() { + timing_type : setup_rising; + related_pin : "A_BIST_CLK"; + + rise_constraint("SIG2SRAM_constraint_template") { + index_1("0.0056,0.0232,0.0400,0.0728,0.1280,0.2440,0.4760"); + index_2("0.0056,0.0232,0.0400,0.0728,0.1280,0.2440,0.4760"); + values ("0.2043,0.2199,0.2316,0.2668,0.3098,0.4152,0.6066",\ +"0.1887,0.2043,0.2199,0.2512,0.2941,0.3996,0.5949",\ +"0.1730,0.1887,0.2043,0.2355,0.2824,0.3840,0.5793",\ +"0.1418,0.1574,0.1730,0.2043,0.2512,0.3566,0.5480",\ +"0.0949,0.1105,0.1262,0.1574,0.2043,0.3020,0.5051",\ +"-0.0066,0.0090,0.0246,0.0520,0.0988,0.2043,0.3996",\ +"-0.2020,-0.1863,-0.1746,-0.1434,-0.0965,0.0090,0.2082"); + } + + fall_constraint("SIG2SRAM_constraint_template") { + index_1("0.0056,0.0232,0.0400,0.0728,0.1280,0.2440,0.4760"); + index_2("0.0056,0.0232,0.0400,0.0728,0.1280,0.2440,0.4760"); + values ("0.2980,0.3137,0.3254,0.3527,0.4035,0.5012,0.6887",\ +"0.2824,0.2980,0.3098,0.3371,0.3879,0.4855,0.6730",\ +"0.2668,0.2824,0.2941,0.3215,0.3723,0.4699,0.6574",\ +"0.2355,0.2473,0.2629,0.2902,0.3410,0.4387,0.6262",\ +"0.1887,0.2004,0.2160,0.2395,0.2941,0.3918,0.5793",\ +"0.0871,0.1027,0.1145,0.1418,0.1848,0.2746,0.4816",\ +"-0.1082,-0.0965,-0.0809,-0.0496,-0.0027,0.0949,0.2863"); + } + } + + + timing() { + timing_type : hold_rising; + related_pin : "A_BIST_CLK"; + + rise_constraint("SIG2SRAM_constraint_template") { + index_1("0.0056,0.0232,0.0400,0.0728,0.1280,0.2440,0.4760"); + index_2("0.0056,0.0232,0.0400,0.0728,0.1280,0.2440,0.4760"); + values ("0.2512,0.2355,0.2199,0.1926,0.1418,0.0402,-0.1590",\ +"0.2668,0.2512,0.2355,0.2082,0.1574,0.0559,-0.1434",\ +"0.2824,0.2629,0.2512,0.2199,0.1691,0.0715,-0.1316",\ +"0.3137,0.2980,0.2824,0.2512,0.2004,0.0988,-0.0965",\ +"0.3566,0.3410,0.3254,0.2980,0.2473,0.1418,-0.0535",\ +"0.4621,0.4426,0.4309,0.3996,0.3527,0.2473,0.0520",\ +"0.6574,0.6418,0.6262,0.5949,0.5441,0.4465,0.2473"); + } + + fall_constraint("SIG2SRAM_constraint_template") { + index_1("0.0056,0.0232,0.0400,0.0728,0.1280,0.2440,0.4760"); + index_2("0.0056,0.0232,0.0400,0.0728,0.1280,0.2440,0.4760"); + values ("0.2395,0.2238,0.2121,0.1809,0.1301,0.0324,-0.1551",\ +"0.2551,0.2434,0.2277,0.1965,0.1457,0.0480,-0.1395",\ +"0.2707,0.2551,0.2395,0.2082,0.1574,0.0637,-0.1277",\ +"0.3020,0.2863,0.2707,0.2434,0.1926,0.0910,-0.0965",\ +"0.3449,0.3332,0.3176,0.2863,0.2355,0.1379,-0.0496",\ +"0.4504,0.4348,0.4230,0.3918,0.3410,0.2434,0.0559",\ +"0.6457,0.6301,0.6145,0.5910,0.5324,0.4387,0.2512"); + } + } + } +bus(A_BIST_BM) { + bus_type : D_31_0; + direction : input ; + capacitance : 0.00238379 ; + max_transition : "0.476" ; + pin(A_BIST_BM[31:0]) { + related_power_pin : VDD; + related_ground_pin : VSS; + internal_power() { + when : "A_BIST_MEN"; + rise_power("scalar"){ + values (0.1176); + } + fall_power("scalar"){ + values (0.0493); + } + } + internal_power() { + when : "!A_BIST_MEN"; + rise_power("scalar"){ + values (0.1174); + } + fall_power("scalar"){ + values (0.0488); + } + } + } + timing() { + timing_type : setup_rising; + related_pin : "A_BIST_CLK"; + when : "(A_BIST_WEN & A_BIST_MEN)" + sdf_cond : "A_BIST_RW_ACCESS" + + rise_constraint("SIG2SRAM_constraint_template") { + index_1("0.0056,0.0232,0.0400,0.0728,0.1280,0.2440,0.4760"); + index_2("0.0056,0.0232,0.0400,0.0728,0.1280,0.2440,0.4760"); + values ("-0.4430,-0.4264,-0.4137,-0.3815,-0.3346,-0.2301,-0.0378",\ +"-0.4480,-0.4314,-0.4187,-0.3865,-0.3396,-0.2351,-0.0428",\ +"-0.4525,-0.4359,-0.4232,-0.3910,-0.3441,-0.2396,-0.0472",\ +"-0.4616,-0.4450,-0.4323,-0.4001,-0.3532,-0.2487,-0.0564",\ +"-0.4688,-0.4522,-0.4395,-0.4073,-0.3604,-0.2559,-0.0635",\ +"-0.4985,-0.4819,-0.4692,-0.4370,-0.3901,-0.2856,-0.0932",\ +"-0.5566,-0.5400,-0.5273,-0.4950,-0.4482,-0.3437,-0.1513"); + } + + fall_constraint("SIG2SRAM_constraint_template") { + index_1("0.0056,0.0232,0.0400,0.0728,0.1280,0.2440,0.4760"); + index_2("0.0056,0.0232,0.0400,0.0728,0.1280,0.2440,0.4760"); + values ("-0.4108,-0.3952,-0.3825,-0.3542,-0.3034,-0.2047,-0.0260",\ +"-0.4158,-0.4002,-0.3875,-0.3592,-0.3084,-0.2097,-0.0310",\ +"-0.4203,-0.4047,-0.3920,-0.3636,-0.3129,-0.2142,-0.0355",\ +"-0.4294,-0.4138,-0.4011,-0.3728,-0.3220,-0.2233,-0.0446",\ +"-0.4366,-0.4210,-0.4083,-0.3800,-0.3292,-0.2305,-0.0518",\ +"-0.4663,-0.4506,-0.4379,-0.4096,-0.3588,-0.2602,-0.0815",\ +"-0.5243,-0.5087,-0.4960,-0.4677,-0.4169,-0.3183,-0.1396"); + } + } + + + timing() { + timing_type : hold_rising; + related_pin : "A_BIST_CLK"; + when : "(A_BIST_WEN & A_BIST_MEN)" + sdf_cond : "A_BIST_RW_ACCESS" + + rise_constraint("SIG2SRAM_constraint_template") { + index_1("0.0056,0.0232,0.0400,0.0728,0.1280,0.2440,0.4760"); + index_2("0.0056,0.0232,0.0400,0.0728,0.1280,0.2440,0.4760"); + values ("0.5521,0.5365,0.5238,0.4916,0.4427,0.3441,0.1478",\ +"0.5571,0.5415,0.5288,0.4966,0.4477,0.3491,0.1528",\ +"0.5616,0.5460,0.5333,0.5010,0.4522,0.3536,0.1573",\ +"0.5707,0.5551,0.5424,0.5102,0.4613,0.3627,0.1664",\ +"0.5779,0.5623,0.5496,0.5174,0.4685,0.3699,0.1736",\ +"0.6076,0.5920,0.5793,0.5470,0.4982,0.3996,0.2033",\ +"0.6656,0.6500,0.6373,0.6051,0.5563,0.4576,0.2614"); + } + + fall_constraint("SIG2SRAM_constraint_template") { + index_1("0.0056,0.0232,0.0400,0.0728,0.1280,0.2440,0.4760"); + index_2("0.0056,0.0232,0.0400,0.0728,0.1280,0.2440,0.4760"); + values ("0.5121,0.4974,0.4838,0.4554,0.4047,0.3119,0.1234",\ +"0.5171,0.5024,0.4888,0.4604,0.4097,0.3169,0.1284",\ +"0.5216,0.5069,0.4932,0.4649,0.4141,0.3214,0.1329",\ +"0.5307,0.5160,0.5024,0.4740,0.4233,0.3305,0.1420",\ +"0.5379,0.5232,0.5096,0.4812,0.4305,0.3377,0.1492",\ +"0.5675,0.5529,0.5392,0.5109,0.4601,0.3673,0.1789",\ +"0.6256,0.6110,0.5973,0.5690,0.5182,0.4254,0.2369"); + } + } +} + pin(A_BIST_CLK) { + direction : input; + capacitance : 0.00380014; + max_transition : "0.476"; + clock : "true" ; + pin_func_type : active_rising ; + + timing () { + timing_type : "min_pulse_width"; + related_pin : "A_BIST_CLK"; + rise_constraint("CLKTRAN_constraint_template") { + index_1("0.0056,0.476"); + values("0.21,0.21"); + } + } + + related_power_pin : VDD; + related_ground_pin : VSS; + + internal_power() { + when : "!A_BIST_MEN & !A_BIST_WEN & !A_BIST_REN"; + rise_power("scalar"){ + values (0); + } + fall_power("scalar"){ + values (0); + } + } + internal_power() { + when : "!A_BIST_MEN & A_BIST_WEN & !A_BIST_REN"; + rise_power("scalar"){ + values (0.5036); + } + fall_power("scalar"){ + values (0); + } + } + internal_power() { + when : "A_BIST_MEN & A_BIST_WEN & !A_BIST_REN"; + rise_power("scalar"){ + values (33.4496); + } + fall_power("scalar"){ + values (0); + } + } + internal_power() { + when : "A_BIST_MEN & A_BIST_WEN & A_BIST_REN"; + rise_power("scalar"){ + values (37.7280); + } + fall_power("scalar"){ + values (0); + } + } + internal_power() { + when : "A_BIST_MEN & !A_BIST_WEN & A_BIST_REN"; + rise_power("scalar"){ + values (26.0060); + } + fall_power("scalar"){ + values (0); + } + } + internal_power() { + when : "!A_BIST_MEN & !A_BIST_WEN & A_BIST_REN"; + rise_power("scalar"){ + values (0.3024); + } + fall_power("scalar"){ + values (0); + } + } + internal_power() { + when : "!A_BIST_MEN & A_BIST_WEN & A_BIST_REN"; + rise_power("scalar"){ + values (1.1356); + } + fall_power("scalar"){ + values (0); + } + } + internal_power() { + when : "A_BIST_MEN & !A_BIST_WEN & !A_BIST_REN"; + rise_power("scalar"){ + values (0); + } + fall_power("scalar"){ + values (0); + } + } + } + bus(A_BIST_DIN) { + bus_type : D_31_0; + direction : input ; + capacitance : 0.00233858 ; + memory_write() { + address : A_BIST_ADDR ; + clocked_on : A_BIST_CLK; + } + + max_transition : "0.476" ; + pin(A_BIST_DIN[31:0]) { + related_power_pin : VDD; + related_ground_pin : VSS; + internal_power() { + when : "A_BIST_MEN"; + rise_power("scalar"){ + values (0.1176); + } + fall_power("scalar"){ + values (0.0493); + } + } + internal_power() { + when : "!A_BIST_MEN"; + rise_power("scalar"){ + values (0.1174); + } + fall_power("scalar"){ + values (0.0488); + } + } + } + timing() { + timing_type : setup_rising; + related_pin : "A_BIST_CLK"; + when : "(A_BIST_WEN & A_BIST_MEN)"; + sdf_cond : "A_BIST_W_ACCESS"; + + rise_constraint("SIG2SRAM_constraint_template") { + index_1("0.0056,0.0232,0.0400,0.0728,0.1280,0.2440,0.4760"); + index_2("0.0056,0.0232,0.0400,0.0728,0.1280,0.2440,0.4760"); + values ("-0.4430,-0.4264,-0.4137,-0.3815,-0.3346,-0.2301,-0.0378",\ +"-0.4480,-0.4314,-0.4187,-0.3865,-0.3396,-0.2351,-0.0428",\ +"-0.4525,-0.4359,-0.4232,-0.3910,-0.3441,-0.2396,-0.0472",\ +"-0.4616,-0.4450,-0.4323,-0.4001,-0.3532,-0.2487,-0.0564",\ +"-0.4688,-0.4522,-0.4395,-0.4073,-0.3604,-0.2559,-0.0635",\ +"-0.4985,-0.4819,-0.4692,-0.4370,-0.3901,-0.2856,-0.0932",\ +"-0.5566,-0.5400,-0.5273,-0.4950,-0.4482,-0.3437,-0.1513"); + } + + fall_constraint("SIG2SRAM_constraint_template") { + index_1("0.0056,0.0232,0.0400,0.0728,0.1280,0.2440,0.4760"); + index_2("0.0056,0.0232,0.0400,0.0728,0.1280,0.2440,0.4760"); + values ("-0.4108,-0.3952,-0.3825,-0.3542,-0.3034,-0.2047,-0.0260",\ +"-0.4158,-0.4002,-0.3875,-0.3592,-0.3084,-0.2097,-0.0310",\ +"-0.4203,-0.4047,-0.3920,-0.3636,-0.3129,-0.2142,-0.0355",\ +"-0.4294,-0.4138,-0.4011,-0.3728,-0.3220,-0.2233,-0.0446",\ +"-0.4366,-0.4210,-0.4083,-0.3800,-0.3292,-0.2305,-0.0518",\ +"-0.4663,-0.4506,-0.4379,-0.4096,-0.3588,-0.2602,-0.0815",\ +"-0.5243,-0.5087,-0.4960,-0.4677,-0.4169,-0.3183,-0.1396"); + } + } + + timing() { + timing_type : hold_rising; + related_pin : "A_BIST_CLK"; + when : "(A_BIST_WEN & A_BIST_MEN)"; + sdf_cond : "A_BIST_W_ACCESS"; + + rise_constraint("SIG2SRAM_constraint_template") { + index_1("0.0056,0.0232,0.0400,0.0728,0.1280,0.2440,0.4760"); + index_2("0.0056,0.0232,0.0400,0.0728,0.1280,0.2440,0.4760"); + values ("0.5521,0.5365,0.5238,0.4916,0.4427,0.3441,0.1478",\ +"0.5571,0.5415,0.5288,0.4966,0.4477,0.3491,0.1528",\ +"0.5616,0.5460,0.5333,0.5010,0.4522,0.3536,0.1573",\ +"0.5707,0.5551,0.5424,0.5102,0.4613,0.3627,0.1664",\ +"0.5779,0.5623,0.5496,0.5174,0.4685,0.3699,0.1736",\ +"0.6076,0.5920,0.5793,0.5470,0.4982,0.3996,0.2033",\ +"0.6656,0.6500,0.6373,0.6051,0.5563,0.4576,0.2614"); + } + + fall_constraint("SIG2SRAM_constraint_template") { + index_1("0.0056,0.0232,0.0400,0.0728,0.1280,0.2440,0.4760"); + index_2("0.0056,0.0232,0.0400,0.0728,0.1280,0.2440,0.4760"); + values ("0.5121,0.4974,0.4838,0.4554,0.4047,0.3119,0.1234",\ +"0.5171,0.5024,0.4888,0.4604,0.4097,0.3169,0.1284",\ +"0.5216,0.5069,0.4932,0.4649,0.4141,0.3214,0.1329",\ +"0.5307,0.5160,0.5024,0.4740,0.4233,0.3305,0.1420",\ +"0.5379,0.5232,0.5096,0.4812,0.4305,0.3377,0.1492",\ +"0.5675,0.5529,0.5392,0.5109,0.4601,0.3673,0.1789",\ +"0.6256,0.6110,0.5973,0.5690,0.5182,0.4254,0.2369"); + } + } + } + +bus(A_DOUT) { + + bus_type : D_31_0; + direction : output ; + capacitance : 0 ; + max_capacitance : 0.064 ; + memory_read() { + address : A_ADDR ; + } + pin(A_DOUT[31:0]) { + related_power_pin : VDD; + related_ground_pin : VSS; + internal_power() { + rise_power("scalar") { + values (0); + } + fall_power("scalar") { + values (0); + } + } + } + timing() { + related_pin : "A_CLK"; + timing_type : rising_edge ; + timing_sense : non_unate ; + + cell_rise(SIG2SRAM_delay_template) { + index_1("0.0056,0.0232,0.0400,0.0728,0.1280,0.2440,0.4760"); + index_2("0.0008,0.0014,0.0051,0.0100,0.0339,0.0640"); + values ("3.0500,3.0516,3.0593,3.0680,3.1004,3.1363",\ +"3.0564,3.0580,3.0656,3.0743,3.1068,3.1426",\ +"3.0585,3.0601,3.0677,3.0764,3.1089,3.1447",\ +"3.0715,3.0731,3.0808,3.0895,3.1219,3.1578",\ +"3.0777,3.0793,3.0870,3.0957,3.1281,3.1640",\ +"3.1092,3.1108,3.1184,3.1271,3.1596,3.1954",\ +"3.1637,3.1653,3.1730,3.1817,3.2141,3.2500"); + } + cell_fall(SIG2SRAM_delay_template) { + index_1("0.0056,0.0232,0.0400,0.0728,0.1280,0.2440,0.4760"); + index_2("0.0008,0.0014,0.0051,0.0100,0.0339,0.0640"); + values ("2.9889,2.9903,2.9963,3.0034,3.0299,3.0566",\ +"2.9953,2.9966,3.0026,3.0098,3.0363,3.0629",\ +"2.9974,2.9987,3.0047,3.0119,3.0384,3.0650",\ +"3.0104,3.0118,3.0178,3.0249,3.0514,3.0780",\ +"3.0166,3.0180,3.0240,3.0311,3.0576,3.0842",\ +"3.0481,3.0494,3.0554,3.0626,3.0891,3.1157",\ +"3.1026,3.1039,3.1099,3.1171,3.1436,3.1702"); + } + + rise_transition(SRAM_load_template) { + index_1("0.0008,0.0014,0.0051,0.0100,0.0339,0.0640"); + values ("0.0326,0.0341,0.0428,0.0518,0.0923,0.1492"); + } + fall_transition(SRAM_load_template) { + index_1("0.0008,0.0014,0.0051,0.0100,0.0339,0.0640"); + values ("0.0254,0.0265,0.0335,0.0402,0.0707,0.1039"); + } + } +} +cell_leakage_power : 99.0077; +} +} diff --git a/flow/platforms/ihp-sg13g2/lib/RM_IHPSG13_1P_256x48_c2_bm_bist_fast_1p32V_m55C.lib b/flow/platforms/ihp-sg13g2/lib/RM_IHPSG13_1P_256x48_c2_bm_bist_fast_1p32V_m55C.lib index 040bb957eb..e84e4de874 100644 --- a/flow/platforms/ihp-sg13g2/lib/RM_IHPSG13_1P_256x48_c2_bm_bist_fast_1p32V_m55C.lib +++ b/flow/platforms/ihp-sg13g2/lib/RM_IHPSG13_1P_256x48_c2_bm_bist_fast_1p32V_m55C.lib @@ -1453,7 +1453,7 @@ bus(A_DOUT) { bus_type : D_47_0; direction : output ; capacitance : 0 ; - max_capacitance : "6.4e-14" ; + max_capacitance : 0.064 ; memory_read() { address : A_ADDR ; } diff --git a/flow/platforms/ihp-sg13g2/lib/RM_IHPSG13_1P_256x48_c2_bm_bist_slow_1p08V_125C.lib b/flow/platforms/ihp-sg13g2/lib/RM_IHPSG13_1P_256x48_c2_bm_bist_slow_1p08V_125C.lib index d164716b4c..f4597c1b95 100644 --- a/flow/platforms/ihp-sg13g2/lib/RM_IHPSG13_1P_256x48_c2_bm_bist_slow_1p08V_125C.lib +++ b/flow/platforms/ihp-sg13g2/lib/RM_IHPSG13_1P_256x48_c2_bm_bist_slow_1p08V_125C.lib @@ -1453,7 +1453,7 @@ bus(A_DOUT) { bus_type : D_47_0; direction : output ; capacitance : 0 ; - max_capacitance : "6.4e-14" ; + max_capacitance : 0.064 ; memory_read() { address : A_ADDR ; } diff --git a/flow/platforms/ihp-sg13g2/lib/RM_IHPSG13_1P_256x48_c2_bm_bist_typ_1p20V_25C.lib b/flow/platforms/ihp-sg13g2/lib/RM_IHPSG13_1P_256x48_c2_bm_bist_typ_1p20V_25C.lib index d43186a0f7..815379ef18 100644 --- a/flow/platforms/ihp-sg13g2/lib/RM_IHPSG13_1P_256x48_c2_bm_bist_typ_1p20V_25C.lib +++ b/flow/platforms/ihp-sg13g2/lib/RM_IHPSG13_1P_256x48_c2_bm_bist_typ_1p20V_25C.lib @@ -1453,7 +1453,7 @@ bus(A_DOUT) { bus_type : D_47_0; direction : output ; capacitance : 0 ; - max_capacitance : "6.4e-14" ; + max_capacitance : 0.064 ; memory_read() { address : A_ADDR ; } diff --git a/flow/platforms/ihp-sg13g2/lib/RM_IHPSG13_1P_256x64_c2_bm_bist_fast_1p32V_m55C.lib b/flow/platforms/ihp-sg13g2/lib/RM_IHPSG13_1P_256x64_c2_bm_bist_fast_1p32V_m55C.lib index 4e4746872a..2251c874b6 100644 --- a/flow/platforms/ihp-sg13g2/lib/RM_IHPSG13_1P_256x64_c2_bm_bist_fast_1p32V_m55C.lib +++ b/flow/platforms/ihp-sg13g2/lib/RM_IHPSG13_1P_256x64_c2_bm_bist_fast_1p32V_m55C.lib @@ -1453,7 +1453,7 @@ bus(A_DOUT) { bus_type : D_63_0; direction : output ; capacitance : 0 ; - max_capacitance : "6.4e-14" ; + max_capacitance : 0.064 ; memory_read() { address : A_ADDR ; } diff --git a/flow/platforms/ihp-sg13g2/lib/RM_IHPSG13_1P_256x64_c2_bm_bist_slow_1p08V_125C.lib b/flow/platforms/ihp-sg13g2/lib/RM_IHPSG13_1P_256x64_c2_bm_bist_slow_1p08V_125C.lib index d480e623d8..087f0c197d 100644 --- a/flow/platforms/ihp-sg13g2/lib/RM_IHPSG13_1P_256x64_c2_bm_bist_slow_1p08V_125C.lib +++ b/flow/platforms/ihp-sg13g2/lib/RM_IHPSG13_1P_256x64_c2_bm_bist_slow_1p08V_125C.lib @@ -1453,7 +1453,7 @@ bus(A_DOUT) { bus_type : D_63_0; direction : output ; capacitance : 0 ; - max_capacitance : "6.4e-14" ; + max_capacitance : 0.064 ; memory_read() { address : A_ADDR ; } diff --git a/flow/platforms/ihp-sg13g2/lib/RM_IHPSG13_1P_256x64_c2_bm_bist_typ_1p20V_25C.lib b/flow/platforms/ihp-sg13g2/lib/RM_IHPSG13_1P_256x64_c2_bm_bist_typ_1p20V_25C.lib index b369e4fb64..256fdb5904 100644 --- a/flow/platforms/ihp-sg13g2/lib/RM_IHPSG13_1P_256x64_c2_bm_bist_typ_1p20V_25C.lib +++ b/flow/platforms/ihp-sg13g2/lib/RM_IHPSG13_1P_256x64_c2_bm_bist_typ_1p20V_25C.lib @@ -1453,7 +1453,7 @@ bus(A_DOUT) { bus_type : D_63_0; direction : output ; capacitance : 0 ; - max_capacitance : "6.4e-14" ; + max_capacitance : 0.064 ; memory_read() { address : A_ADDR ; } diff --git a/flow/platforms/ihp-sg13g2/lib/RM_IHPSG13_1P_256x8_c3_bm_bist_fast_1p32V_m55C.lib b/flow/platforms/ihp-sg13g2/lib/RM_IHPSG13_1P_256x8_c3_bm_bist_fast_1p32V_m55C.lib new file mode 100644 index 0000000000..661cdc8057 --- /dev/null +++ b/flow/platforms/ihp-sg13g2/lib/RM_IHPSG13_1P_256x8_c3_bm_bist_fast_1p32V_m55C.lib @@ -0,0 +1,1513 @@ +/* ------------------------------------------------------*/ +/**/ +/* Copyright 2025 IHP PDK Authors*/ +/**/ +/* Licensed under the Apache License, Version 2.0 (the "License");*/ +/* you may not use this file except in compliance with the License.*/ +/* You may obtain a copy of the License at*/ +/* */ +/* https://www.apache.org/licenses/LICENSE-2.0*/ +/* */ +/* Unless required by applicable law or agreed to in writing, software*/ +/* distributed under the License is distributed on an "AS IS" BASIS,*/ +/* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.*/ +/* See the License for the specific language governing permissions and*/ +/* limitations under the License.*/ +/* */ +/* Generated on Wed Aug 27 16:22:41 2025 */ +/* */ +/* ------------------------------------------------------ */ +library(RM_IHPSG13_1P_256x8_c3_bm_bist_fast_1p32V_m55C) { + technology (cmos) ; + delay_model : table_lookup ; + define ("add_pg_pin_to_lib", "library", "boolean"); + add_pg_pin_to_lib : true; + voltage_map ( VDD, 1.32); + voltage_map ( VDDARRAY, 1.32); + voltage_map ( VSS, 0.000000 ); + + date : "Wed Aug 27 16:22:39 2025" ; + comment : "IHP Microelectronics GmbH, 2023" ; + revision : 1.0.0 ; + simulation : true ; + nom_process : 1 ; + nom_temperature : -55 ; + nom_voltage : 1.32 ; + + operating_conditions("fast_1p32V_m55C"){ + process : 1 ; + temperature : -55 ; + voltage : 1.32 ; + tree_type : "balanced_tree" ; + } + + default_operating_conditions : fast_1p32V_m55C ; + default_max_transition : 1.0 ; + default_fanout_load : 1.0 ; + default_inout_pin_cap : 0.0 ; + default_input_pin_cap : 0.0 ; + default_output_pin_cap : 0.0 ; + default_cell_leakage_power : 0.0 ; + default_leakage_power_density : 0.0 ; + + slew_lower_threshold_pct_rise : 30 ; + slew_upper_threshold_pct_rise : 70 ; + input_threshold_pct_fall : 50 ; + output_threshold_pct_fall : 50 ; + input_threshold_pct_rise : 50 ; + output_threshold_pct_rise : 50 ; + slew_lower_threshold_pct_fall : 30 ; + slew_upper_threshold_pct_fall : 70 ; + slew_derate_from_library : 0.5; + k_volt_cell_leakage_power : 0.0 ; + k_temp_cell_leakage_power : 0.0 ; + k_process_cell_leakage_power : 0.0 ; + k_volt_internal_power : 0.0 ; + k_temp_internal_power : 0.0 ; + k_process_internal_power : 0.0 ; + + capacitive_load_unit (1,pf) ; + voltage_unit : "1V" ; + current_unit : "1uA" ; + time_unit : "1ns" ; + leakage_power_unit : "1nW" ; + pulling_resistance_unit : "1kohm"; + /* + ------------------------------------------------------------------------------------------ + implicit units overview: + cell_area unit : "um" + internal_power unit : "1e-12 * J/toggle = 1 * uW/MHz" + (capacitive_load_unit * voltage_unit^2) per toggle event + ------------------------------------------------------------------------------------------ + */ + library_features(report_delay_calculation); + define_cell_area (pad_drivers,pad_driver_sites) ; + + lu_table_template(CLKTRAN_constraint_template) { + variable_1 : constrained_pin_transition; + index_1 ( "0.010, 0.050, 0.200, 0.400, 1.000" ); + } + lu_table_template(SRAM_load_template) { + variable_1 : total_output_net_capacitance; + index_1 ( "0.0008,0.0014,0.0051,0.0100,0.0339,0.0640" ); + } + lu_table_template(SIG2SRAM_constraint_template) { + variable_1 : related_pin_transition; + variable_2 : constrained_pin_transition; + index_1 ( "0.0040,0.0176,0.0344,0.0656,0.1120,0.2016,0.3800" ); + index_2 ( "0.0040,0.0176,0.0344,0.0656,0.1120,0.2016,0.3800" ); + } + + lu_table_template(SIG2SRAM_delay_template) { + variable_1 : input_net_transition; + variable_2 : total_output_net_capacitance; + index_1 ( "0.0040,0.0176,0.0344,0.0656,0.1120,0.2016,0.3800" ); + index_2 ( "0.0008,0.0014,0.0051,0.0100,0.0339,0.0640" ); + } + + type (D_7_0) { + base_type : array; + data_type : bit; + bit_width : 8; + bit_from : 7; + bit_to : 0; + downto : true; + } + + type (A_7_0) { + base_type : array; + data_type : bit; + bit_width : 8; + bit_from : 7; + bit_to : 0; + downto : true; + } + +cell(RM_IHPSG13_1P_256x8_c3_bm_bist) { +pg_pin (VDD) { + pg_type : primary_power; + voltage_name : VDD; +} +pg_pin (VDDARRAY) { + pg_type : primary_power; + voltage_name : VDDARRAY; +} +pg_pin (VSS) { + pg_type : primary_ground; + voltage_name : VSS; +} + +memory() { + type : ram; + address_width : 8; + word_width : 8; +} + +interface_timing : false; +bus_naming_style : "%s[%d]" ; +area : 17546.88 ; + + pin(A_DLY) { + direction : input ; + capacitance : 0.00421562 ; + max_transition : "1" ; + related_power_pin : VDD; + related_ground_pin : VSS; + internal_power() { + rise_power("scalar") { + values (0); + } + fall_power("scalar") { + values (0); + } + } + } + +bus(A_ADDR) { + bus_type : A_7_0; + direction : input ; + capacitance : 0.00691085 ; + pin(A_ADDR[0]) { + capacitance : 0.00562034 ; + } + pin(A_ADDR[1]) { + capacitance : 0.00462655 ; + } + pin(A_ADDR[2]) { + capacitance : 0.00594295 ; + } + pin(A_ADDR[3]) { + capacitance : 0.00723434 ; + } + pin(A_ADDR[4]) { + capacitance : 0.00481603 ; + } + pin(A_ADDR[5]) { + capacitance : 0.00868123 ; + } + pin(A_ADDR[6]) { + capacitance : 0.010187 ; + } + max_transition : "0.38" ; + pin(A_ADDR[7:0]) { + related_power_pin : VDD; + related_ground_pin : VSS; + internal_power() { + when : "A_MEN"; + rise_power("scalar"){ + values (0.0727); + } + fall_power("scalar"){ + values (0.0037); + } + } + internal_power() { + when : "!A_MEN"; + rise_power("scalar"){ + values (0.0228); + } + fall_power("scalar"){ + values (0.0010); + } + } + } + timing() { + timing_type : setup_rising; + related_pin : "A_CLK"; + when : "((A_WEN | A_REN)& A_MEN)" + sdf_cond : "A_RW_ACCESS" + + rise_constraint("SIG2SRAM_constraint_template") { + index_1("0.0040,0.0176,0.0344,0.0656,0.1120,0.2016,0.3800"); + index_2("0.0040,0.0176,0.0344,0.0656,0.1120,0.2016,0.3800"); + values ("-0.2371,-0.2215,-0.2098,-0.1824,-0.1434,-0.0691,0.0676",\ +"-0.2449,-0.2332,-0.2176,-0.1902,-0.1551,-0.0770,0.0559",\ +"-0.2605,-0.2488,-0.2332,-0.2059,-0.1707,-0.0965,0.0441",\ +"-0.2879,-0.2723,-0.2605,-0.2332,-0.1941,-0.1199,0.0168",\ +"-0.3230,-0.3113,-0.2996,-0.2723,-0.2332,-0.1590,-0.0184",\ +"-0.4012,-0.3895,-0.3738,-0.3465,-0.3074,-0.2332,-0.0965",\ +"-0.5379,-0.5262,-0.5105,-0.4832,-0.4480,-0.3699,-0.2332"); + } + + fall_constraint("SIG2SRAM_constraint_template") { + index_1("0.0040,0.0176,0.0344,0.0656,0.1120,0.2016,0.3800"); + index_2("0.0040,0.0176,0.0344,0.0656,0.1120,0.2016,0.3800"); + values ("-0.1785,-0.1707,-0.1551,-0.1277,-0.0887,-0.0184,0.1145",\ +"-0.1902,-0.1785,-0.1629,-0.1355,-0.1004,-0.0262,0.1027",\ +"-0.2059,-0.1941,-0.1785,-0.1512,-0.1160,-0.0418,0.0871",\ +"-0.2293,-0.2176,-0.2059,-0.1785,-0.1434,-0.0691,0.0598",\ +"-0.2684,-0.2566,-0.2449,-0.2176,-0.1824,-0.1082,0.0207",\ +"-0.3465,-0.3348,-0.3191,-0.2918,-0.2566,-0.1824,-0.0535",\ +"-0.4832,-0.4715,-0.4559,-0.4324,-0.3934,-0.3191,-0.1902"); + } + } + + + timing() { + timing_type : hold_rising; + related_pin : "A_CLK"; + when : "((A_WEN | A_REN)& A_MEN)" + sdf_cond : "A_RW_ACCESS" + + rise_constraint("SIG2SRAM_constraint_template") { + index_1("0.0040,0.0176,0.0344,0.0656,0.1120,0.2016,0.3800"); + index_2("0.0040,0.0176,0.0344,0.0656,0.1120,0.2016,0.3800"); + values ("0.3410,0.3293,0.3137,0.2863,0.2473,0.1730,0.0324",\ +"0.3488,0.3371,0.3215,0.2941,0.2590,0.1809,0.0480",\ +"0.3684,0.3527,0.3371,0.3098,0.2746,0.1965,0.0598",\ +"0.3918,0.3762,0.3645,0.3371,0.2980,0.2238,0.0871",\ +"0.4309,0.4152,0.4035,0.3762,0.3371,0.2629,0.1223",\ +"0.5051,0.4934,0.4777,0.4504,0.4113,0.3371,0.1965",\ +"0.6418,0.6262,0.6145,0.5871,0.5520,0.4738,0.3332"); + } + + fall_constraint("SIG2SRAM_constraint_template") { + index_1("0.0040,0.0176,0.0344,0.0656,0.1120,0.2016,0.3800"); + index_2("0.0040,0.0176,0.0344,0.0656,0.1120,0.2016,0.3800"); + values ("0.2824,0.2707,0.2551,0.2277,0.1926,0.1184,-0.0105",\ +"0.2902,0.2785,0.2668,0.2395,0.2043,0.1301,0.0012",\ +"0.3059,0.2941,0.2824,0.2551,0.2199,0.1457,0.0168",\ +"0.3332,0.3215,0.3059,0.2785,0.2434,0.1691,0.0402",\ +"0.3723,0.3605,0.3449,0.3176,0.2824,0.2121,0.0793",\ +"0.4465,0.4348,0.4230,0.3918,0.3566,0.2824,0.1535",\ +"0.5832,0.5715,0.5598,0.5324,0.4934,0.4191,0.2902"); + } + } +} +pin(A_WEN) { + direction : input ; + capacitance : 0.00341384 ; + max_transition : "0.38" ; + related_power_pin : VDD; + related_ground_pin : VSS; + internal_power() { + when : "A_MEN"; + rise_power("scalar"){ + values (0.0067); + } + fall_power("scalar"){ + values (0.0158); + } + } + internal_power() { + when : "!A_MEN"; + rise_power("scalar"){ + values (0.0043); + } + fall_power("scalar"){ + values (0.0211); + } + } + timing() { + timing_type : setup_rising; + related_pin : "A_CLK"; + when : "A_MEN" + sdf_cond : "A_MEN" + + rise_constraint("SIG2SRAM_constraint_template") { + index_1("0.0040,0.0176,0.0344,0.0656,0.1120,0.2016,0.3800"); + index_2("0.0040,0.0176,0.0344,0.0656,0.1120,0.2016,0.3800"); + values ("0.1418,0.1496,0.1652,0.1887,0.2316,0.3059,0.4465",\ +"0.1301,0.1379,0.1535,0.1809,0.2199,0.2941,0.4348",\ +"0.1145,0.1262,0.1379,0.1652,0.2043,0.2785,0.4191",\ +"0.0871,0.0949,0.1105,0.1379,0.1770,0.2512,0.3879",\ +"0.0480,0.0598,0.0754,0.0988,0.1379,0.2082,0.3527",\ +"-0.0262,-0.0145,0.0012,0.0246,0.0676,0.1379,0.2785",\ +"-0.1668,-0.1551,-0.1395,-0.1121,-0.0730,0.0012,0.1418"); + } + + fall_constraint("SIG2SRAM_constraint_template") { + index_1("0.0040,0.0176,0.0344,0.0656,0.1120,0.2016,0.3800"); + index_2("0.0040,0.0176,0.0344,0.0656,0.1120,0.2016,0.3800"); + values ("0.2082,0.2160,0.2316,0.2590,0.2941,0.3684,0.5012",\ +"0.1926,0.2043,0.2199,0.2473,0.2824,0.3566,0.4895",\ +"0.1770,0.1887,0.2043,0.2316,0.2668,0.3410,0.4777",\ +"0.1535,0.1652,0.1770,0.2043,0.2395,0.3137,0.4504",\ +"0.1145,0.1262,0.1379,0.1652,0.2043,0.2746,0.4113",\ +"0.0402,0.0520,0.0676,0.0910,0.1262,0.2004,0.3332",\ +"-0.0965,-0.0848,-0.0730,-0.0457,-0.0066,0.0637,0.2004"); + } + } + + + timing() { + timing_type : hold_rising; + related_pin : "A_CLK"; + when : "A_MEN" + sdf_cond : "A_MEN" + + rise_constraint("SIG2SRAM_constraint_template") { + index_1("0.0040,0.0176,0.0344,0.0656,0.1120,0.2016,0.3800"); + index_2("0.0040,0.0176,0.0344,0.0656,0.1120,0.2016,0.3800"); + values ("0.1770,0.1652,0.1496,0.1223,0.0793,0.0090,-0.1316",\ +"0.1848,0.1730,0.1574,0.1301,0.0910,0.0168,-0.1199",\ +"0.2004,0.1887,0.1770,0.1496,0.1066,0.0363,-0.1043",\ +"0.2277,0.2160,0.2004,0.1730,0.1340,0.0598,-0.0809",\ +"0.2668,0.2551,0.2395,0.2121,0.1730,0.0988,-0.0418",\ +"0.3410,0.3293,0.3137,0.2863,0.2434,0.1730,0.0324",\ +"0.4816,0.4699,0.4543,0.4230,0.3801,0.3098,0.1730"); + } + + fall_constraint("SIG2SRAM_constraint_template") { + index_1("0.0040,0.0176,0.0344,0.0656,0.1120,0.2016,0.3800"); + index_2("0.0040,0.0176,0.0344,0.0656,0.1120,0.2016,0.3800"); + values ("0.1613,0.1496,0.1379,0.1066,0.0715,0.0012,-0.1355",\ +"0.1730,0.1613,0.1457,0.1184,0.0832,0.0129,-0.1238",\ +"0.1887,0.1770,0.1613,0.1340,0.0988,0.0246,-0.1121",\ +"0.2121,0.2043,0.1887,0.1613,0.1223,0.0520,-0.0848",\ +"0.2512,0.2434,0.2277,0.2004,0.1613,0.0910,-0.0457",\ +"0.3254,0.3176,0.3020,0.2746,0.2355,0.1652,0.0324",\ +"0.4660,0.4543,0.4387,0.4113,0.3723,0.3020,0.1691"); + } + } + } +pin(A_REN) { + direction : input ; + capacitance : 0.00390661 ; + max_transition : "0.38" ; + related_power_pin : VDD; + related_ground_pin : VSS; + internal_power() { + when : "A_MEN"; + rise_power("scalar"){ + values (0.0101); + } + fall_power("scalar"){ + values (0.0113); + } + } + internal_power() { + when : "!A_MEN"; + rise_power("scalar"){ + values (0.0244); + } + fall_power("scalar"){ + values (0.0204); + } + } + timing() { + timing_type : setup_rising; + related_pin : "A_CLK"; + when : "A_MEN" + sdf_cond : "A_MEN" + + rise_constraint("SIG2SRAM_constraint_template") { + index_1("0.0040,0.0176,0.0344,0.0656,0.1120,0.2016,0.3800"); + index_2("0.0040,0.0176,0.0344,0.0656,0.1120,0.2016,0.3800"); + values ("-0.0027,0.0090,0.0246,0.0520,0.0910,0.1613,0.3020",\ +"-0.0105,0.0012,0.0129,0.0363,0.0793,0.1535,0.2902",\ +"-0.0262,-0.0145,-0.0027,0.0246,0.0637,0.1379,0.2785",\ +"-0.0535,-0.0418,-0.0262,0.0012,0.0363,0.1105,0.2512",\ +"-0.0926,-0.0809,-0.0652,-0.0418,-0.0027,0.0715,0.2121",\ +"-0.1668,-0.1551,-0.1395,-0.1082,-0.0770,-0.0027,0.1379",\ +"-0.3035,-0.2918,-0.2762,-0.2488,-0.2137,-0.1434,-0.0027"); + } + + fall_constraint("SIG2SRAM_constraint_template") { + index_1("0.0040,0.0176,0.0344,0.0656,0.1120,0.2016,0.3800"); + index_2("0.0040,0.0176,0.0344,0.0656,0.1120,0.2016,0.3800"); + values ("0.0832,0.0949,0.1105,0.1379,0.1730,0.2473,0.3801",\ +"0.0754,0.0832,0.0988,0.1223,0.1613,0.2355,0.3684",\ +"0.0598,0.0676,0.0832,0.1066,0.1457,0.2121,0.3527",\ +"0.0324,0.0441,0.0598,0.0871,0.1223,0.1926,0.3293",\ +"-0.0066,0.0051,0.0168,0.0480,0.0832,0.1535,0.2902",\ +"-0.0809,-0.0691,-0.0574,-0.0301,0.0090,0.0832,0.2121",\ +"-0.2176,-0.2059,-0.1941,-0.1668,-0.1277,-0.0574,0.0793"); + } + } + + + timing() { + timing_type : hold_rising; + related_pin : "A_CLK"; + when : "A_MEN" + sdf_cond : "A_MEN" + + rise_constraint("SIG2SRAM_constraint_template") { + index_1("0.0040,0.0176,0.0344,0.0656,0.1120,0.2016,0.3800"); + index_2("0.0040,0.0176,0.0344,0.0656,0.1120,0.2016,0.3800"); + values ("0.1887,0.1770,0.1613,0.1340,0.0949,0.0207,-0.1160",\ +"0.1965,0.1848,0.1730,0.1457,0.1027,0.0324,-0.1082",\ +"0.2160,0.2004,0.1887,0.1613,0.1184,0.0480,-0.0926",\ +"0.2395,0.2277,0.2121,0.1848,0.1457,0.0715,-0.0652",\ +"0.2785,0.2668,0.2512,0.2238,0.1848,0.1105,-0.0262",\ +"0.3527,0.3410,0.3254,0.2980,0.2551,0.1848,0.0480",\ +"0.4934,0.4816,0.4660,0.4387,0.3957,0.3254,0.1887"); + } + + fall_constraint("SIG2SRAM_constraint_template") { + index_1("0.0040,0.0176,0.0344,0.0656,0.1120,0.2016,0.3800"); + index_2("0.0040,0.0176,0.0344,0.0656,0.1120,0.2016,0.3800"); + values ("0.1730,0.1613,0.1496,0.1184,0.0793,0.0129,-0.1238",\ +"0.1848,0.1730,0.1574,0.1301,0.0910,0.0207,-0.1121",\ +"0.2004,0.1887,0.1730,0.1457,0.1066,0.0363,-0.1004",\ +"0.2238,0.2121,0.2004,0.1691,0.1340,0.0598,-0.0730",\ +"0.2629,0.2512,0.2395,0.2121,0.1691,0.0988,-0.0340",\ +"0.3371,0.3254,0.3137,0.2863,0.2434,0.1730,0.0402",\ +"0.4777,0.4660,0.4504,0.4230,0.3840,0.3137,0.1809"); + } + } + } +pin(A_MEN) { + direction : input ; + capacitance : 0.00326046 ; + max_transition : "0.38" ; + related_power_pin : VDD; + related_ground_pin : VSS; + internal_power() { + rise_power("scalar"){ + values (0.0869); + } + fall_power("scalar"){ + values (0.0777); + } + } + timing() { + timing_type : setup_rising; + related_pin : "A_CLK"; + + rise_constraint("SIG2SRAM_constraint_template") { + index_1("0.0040,0.0176,0.0344,0.0656,0.1120,0.2016,0.3800"); + index_2("0.0040,0.0176,0.0344,0.0656,0.1120,0.2016,0.3800"); + values ("0.1418,0.1496,0.1652,0.1926,0.2316,0.3059,0.4465",\ +"0.1301,0.1379,0.1535,0.1809,0.2199,0.2941,0.4348",\ +"0.1145,0.1262,0.1418,0.1652,0.2043,0.2785,0.4191",\ +"0.0871,0.0949,0.1105,0.1379,0.1770,0.2512,0.3879",\ +"0.0480,0.0598,0.0754,0.0988,0.1379,0.2082,0.3488",\ +"-0.0262,-0.0145,0.0012,0.0285,0.0676,0.1379,0.2785",\ +"-0.1668,-0.1551,-0.1395,-0.1121,-0.0730,0.0012,0.1379"); + } + + fall_constraint("SIG2SRAM_constraint_template") { + index_1("0.0040,0.0176,0.0344,0.0656,0.1120,0.2016,0.3800"); + index_2("0.0040,0.0176,0.0344,0.0656,0.1120,0.2016,0.3800"); + values ("0.2082,0.2199,0.2316,0.2590,0.2980,0.3723,0.5051",\ +"0.1965,0.2082,0.2199,0.2473,0.2863,0.3605,0.4934",\ +"0.1809,0.1926,0.2043,0.2316,0.2707,0.3449,0.4777",\ +"0.1574,0.1691,0.1809,0.2082,0.2434,0.3176,0.4543",\ +"0.1145,0.1262,0.1418,0.1691,0.2043,0.2785,0.4113",\ +"0.0441,0.0559,0.0676,0.0949,0.1301,0.2004,0.3332",\ +"-0.0965,-0.0848,-0.0691,-0.0418,-0.0066,0.0676,0.2004"); + } + } + + + timing() { + timing_type : hold_rising; + related_pin : "A_CLK"; + + rise_constraint("SIG2SRAM_constraint_template") { + index_1("0.0040,0.0176,0.0344,0.0656,0.1120,0.2016,0.3800"); + index_2("0.0040,0.0176,0.0344,0.0656,0.1120,0.2016,0.3800"); + values ("0.1770,0.1652,0.1535,0.1262,0.0832,0.0129,-0.1277",\ +"0.1887,0.1770,0.1613,0.1340,0.0949,0.0207,-0.1199",\ +"0.2043,0.1926,0.1770,0.1496,0.1105,0.0363,-0.1043",\ +"0.2277,0.2160,0.2043,0.1770,0.1379,0.0598,-0.0770",\ +"0.2668,0.2551,0.2434,0.2160,0.1730,0.0988,-0.0379",\ +"0.3449,0.3332,0.3176,0.2902,0.2473,0.1730,0.0363",\ +"0.4816,0.4699,0.4543,0.4270,0.3840,0.3098,0.1770"); + } + + fall_constraint("SIG2SRAM_constraint_template") { + index_1("0.0040,0.0176,0.0344,0.0656,0.1120,0.2016,0.3800"); + index_2("0.0040,0.0176,0.0344,0.0656,0.1120,0.2016,0.3800"); + values ("0.1613,0.1496,0.1379,0.1105,0.0715,0.0012,-0.1355",\ +"0.1730,0.1613,0.1496,0.1184,0.0832,0.0129,-0.1238",\ +"0.1887,0.1770,0.1652,0.1340,0.0988,0.0285,-0.1121",\ +"0.2121,0.2043,0.1887,0.1613,0.1223,0.0520,-0.0848",\ +"0.2551,0.2434,0.2277,0.2004,0.1613,0.0910,-0.0418",\ +"0.3293,0.3176,0.3020,0.2746,0.2395,0.1652,0.0324",\ +"0.4660,0.4543,0.4426,0.4113,0.3762,0.3020,0.1691"); + } + } + } +bus(A_BM) { + bus_type : D_7_0; + direction : input ; + capacitance : 0.00318267 ; + max_transition : "0.38" ; + pin(A_BM[7:0]) { + related_power_pin : VDD; + related_ground_pin : VSS; + internal_power() { + when : "A_MEN"; + rise_power("scalar"){ + values (0.0324); + } + fall_power("scalar"){ + values (0.0401); + } + } + internal_power() { + when : "!A_MEN"; + rise_power("scalar"){ + values (0.0522); + } + fall_power("scalar"){ + values (0.0509); + } + } + } + timing() { + timing_type : setup_rising; + related_pin : "A_CLK"; + when : "(A_WEN & A_MEN)" + sdf_cond : "A_RW_ACCESS" + + rise_constraint("SIG2SRAM_constraint_template") { + index_1("0.0040,0.0176,0.0344,0.0656,0.1120,0.2016,0.3800"); + index_2("0.0040,0.0176,0.0344,0.0656,0.1120,0.2016,0.3800"); + values ("-0.1737,-0.1630,-0.1473,-0.1219,-0.0809,-0.0077,0.1271",\ +"-0.1776,-0.1668,-0.1512,-0.1258,-0.0848,-0.0116,0.1232",\ +"-0.1813,-0.1705,-0.1549,-0.1295,-0.0885,-0.0153,0.1195",\ +"-0.1845,-0.1737,-0.1581,-0.1327,-0.0917,-0.0185,0.1163",\ +"-0.1971,-0.1863,-0.1707,-0.1453,-0.1043,-0.0311,0.1037",\ +"-0.2147,-0.2040,-0.1883,-0.1629,-0.1219,-0.0487,0.0861",\ +"-0.2422,-0.2315,-0.2158,-0.1904,-0.1494,-0.0762,0.0586"); + } + + fall_constraint("SIG2SRAM_constraint_template") { + index_1("0.0040,0.0176,0.0344,0.0656,0.1120,0.2016,0.3800"); + index_2("0.0040,0.0176,0.0344,0.0656,0.1120,0.2016,0.3800"); + values ("-0.1503,-0.1385,-0.1259,-0.0985,-0.0614,0.0118,0.1398",\ +"-0.1542,-0.1424,-0.1297,-0.1024,-0.0653,0.0080,0.1359",\ +"-0.1578,-0.1461,-0.1334,-0.1061,-0.0690,0.0043,0.1322",\ +"-0.1610,-0.1493,-0.1366,-0.1093,-0.0722,0.0011,0.1290",\ +"-0.1736,-0.1619,-0.1492,-0.1219,-0.0848,-0.0115,0.1164",\ +"-0.1913,-0.1795,-0.1668,-0.1395,-0.1024,-0.0292,0.0988",\ +"-0.2188,-0.2070,-0.1943,-0.1670,-0.1299,-0.0567,0.0713"); + } + } + + + timing() { + timing_type : hold_rising; + related_pin : "A_CLK"; + when : "(A_WEN & A_MEN)" + sdf_cond : "A_RW_ACCESS" + + rise_constraint("SIG2SRAM_constraint_template") { + index_1("0.0040,0.0176,0.0344,0.0656,0.1120,0.2016,0.3800"); + index_2("0.0040,0.0176,0.0344,0.0656,0.1120,0.2016,0.3800"); + values ("0.2787,0.2689,0.2533,0.2269,0.1898,0.1156,-0.0192",\ +"0.2826,0.2728,0.2572,0.2308,0.1937,0.1195,-0.0153",\ +"0.2863,0.2765,0.2609,0.2345,0.1974,0.1232,-0.0116",\ +"0.2895,0.2797,0.2641,0.2377,0.2006,0.1264,-0.0084",\ +"0.3021,0.2923,0.2767,0.2503,0.2132,0.1390,0.0042",\ +"0.3197,0.3099,0.2943,0.2679,0.2308,0.1566,0.0218",\ +"0.3472,0.3374,0.3218,0.2954,0.2583,0.1841,0.0493"); + } + + fall_constraint("SIG2SRAM_constraint_template") { + index_1("0.0040,0.0176,0.0344,0.0656,0.1120,0.2016,0.3800"); + index_2("0.0040,0.0176,0.0344,0.0656,0.1120,0.2016,0.3800"); + values ("0.2504,0.2396,0.2260,0.1986,0.1625,0.0902,-0.0397",\ +"0.2543,0.2435,0.2298,0.2025,0.1664,0.0941,-0.0358",\ +"0.2579,0.2472,0.2335,0.2062,0.1700,0.0978,-0.0321",\ +"0.2611,0.2504,0.2367,0.2094,0.1732,0.1010,-0.0289",\ +"0.2738,0.2630,0.2493,0.2220,0.1859,0.1136,-0.0163",\ +"0.2914,0.2806,0.2669,0.2396,0.2035,0.1312,0.0013",\ +"0.3189,0.3081,0.2945,0.2671,0.2310,0.1587,0.0288"); + } + } +} + pin(A_CLK) { + direction : input; + capacitance : 0.00389386; + max_transition : "0.38"; + clock : "true" ; + pin_func_type : active_rising ; + + timing () { + timing_type : "min_pulse_width"; + related_pin : "A_CLK"; + rise_constraint("CLKTRAN_constraint_template") { + index_1("0.004,0.38"); + values("0.12,0.12"); + } + } + + related_power_pin : VDD; + related_ground_pin : VSS; + + internal_power() { + when : "!A_MEN & !A_WEN & !A_REN"; + rise_power("scalar"){ + values (0); + } + fall_power("scalar"){ + values (0); + } + } + internal_power() { + when : "!A_MEN & A_WEN & !A_REN"; + rise_power("scalar"){ + values (0.6006); + } + fall_power("scalar"){ + values (0); + } + } + internal_power() { + when : "A_MEN & A_WEN & !A_REN"; + rise_power("scalar"){ + values (15.9843); + } + fall_power("scalar"){ + values (0); + } + } + internal_power() { + when : "A_MEN & A_WEN & A_REN"; + rise_power("scalar"){ + values (16.1453); + } + fall_power("scalar"){ + values (0); + } + } + internal_power() { + when : "A_MEN & !A_WEN & A_REN"; + rise_power("scalar"){ + values (11.9622); + } + fall_power("scalar"){ + values (0); + } + } + internal_power() { + when : "!A_MEN & !A_WEN & A_REN"; + rise_power("scalar"){ + values (0.3950); + } + fall_power("scalar"){ + values (0); + } + } + internal_power() { + when : "!A_MEN & A_WEN & A_REN"; + rise_power("scalar"){ + values (0.6485); + } + fall_power("scalar"){ + values (0); + } + } + internal_power() { + when : "A_MEN & !A_WEN & !A_REN"; + rise_power("scalar"){ + values (0); + } + fall_power("scalar"){ + values (0); + } + } + } + bus(A_DIN) { + bus_type : D_7_0; + direction : input ; + capacitance : 0.00332733 ; + memory_write() { + address : A_ADDR ; + clocked_on : A_CLK; + } + + max_transition : "0.38" ; + pin(A_DIN[7:0]) { + related_power_pin : VDD; + related_ground_pin : VSS; + internal_power() { + when : "A_MEN"; + rise_power("scalar"){ + values (0.0324); + } + fall_power("scalar"){ + values (0.0401); + } + } + internal_power() { + when : "!A_MEN"; + rise_power("scalar"){ + values (0.0522); + } + fall_power("scalar"){ + values (0.0509); + } + } + } + timing() { + timing_type : setup_rising; + related_pin : "A_CLK"; + when : "(A_WEN & A_MEN)"; + sdf_cond : "A_W_ACCESS"; + + rise_constraint("SIG2SRAM_constraint_template") { + index_1("0.0040,0.0176,0.0344,0.0656,0.1120,0.2016,0.3800"); + index_2("0.0040,0.0176,0.0344,0.0656,0.1120,0.2016,0.3800"); + values ("-0.1737,-0.1630,-0.1473,-0.1219,-0.0809,-0.0077,0.1271",\ +"-0.1776,-0.1668,-0.1512,-0.1258,-0.0848,-0.0116,0.1232",\ +"-0.1813,-0.1705,-0.1549,-0.1295,-0.0885,-0.0153,0.1195",\ +"-0.1845,-0.1737,-0.1581,-0.1327,-0.0917,-0.0185,0.1163",\ +"-0.1971,-0.1863,-0.1707,-0.1453,-0.1043,-0.0311,0.1037",\ +"-0.2147,-0.2040,-0.1883,-0.1629,-0.1219,-0.0487,0.0861",\ +"-0.2422,-0.2315,-0.2158,-0.1904,-0.1494,-0.0762,0.0586"); + } + + fall_constraint("SIG2SRAM_constraint_template") { + index_1("0.0040,0.0176,0.0344,0.0656,0.1120,0.2016,0.3800"); + index_2("0.0040,0.0176,0.0344,0.0656,0.1120,0.2016,0.3800"); + values ("-0.1503,-0.1385,-0.1259,-0.0985,-0.0614,0.0118,0.1398",\ +"-0.1542,-0.1424,-0.1297,-0.1024,-0.0653,0.0080,0.1359",\ +"-0.1578,-0.1461,-0.1334,-0.1061,-0.0690,0.0043,0.1322",\ +"-0.1610,-0.1493,-0.1366,-0.1093,-0.0722,0.0011,0.1290",\ +"-0.1736,-0.1619,-0.1492,-0.1219,-0.0848,-0.0115,0.1164",\ +"-0.1913,-0.1795,-0.1668,-0.1395,-0.1024,-0.0292,0.0988",\ +"-0.2188,-0.2070,-0.1943,-0.1670,-0.1299,-0.0567,0.0713"); + } + } + + timing() { + timing_type : hold_rising; + related_pin : "A_CLK"; + when : "(A_WEN & A_MEN)"; + sdf_cond : "A_W_ACCESS"; + + rise_constraint("SIG2SRAM_constraint_template") { + index_1("0.0040,0.0176,0.0344,0.0656,0.1120,0.2016,0.3800"); + index_2("0.0040,0.0176,0.0344,0.0656,0.1120,0.2016,0.3800"); + values ("0.2787,0.2689,0.2533,0.2269,0.1898,0.1156,-0.0192",\ +"0.2826,0.2728,0.2572,0.2308,0.1937,0.1195,-0.0153",\ +"0.2863,0.2765,0.2609,0.2345,0.1974,0.1232,-0.0116",\ +"0.2895,0.2797,0.2641,0.2377,0.2006,0.1264,-0.0084",\ +"0.3021,0.2923,0.2767,0.2503,0.2132,0.1390,0.0042",\ +"0.3197,0.3099,0.2943,0.2679,0.2308,0.1566,0.0218",\ +"0.3472,0.3374,0.3218,0.2954,0.2583,0.1841,0.0493"); + } + + fall_constraint("SIG2SRAM_constraint_template") { + index_1("0.0040,0.0176,0.0344,0.0656,0.1120,0.2016,0.3800"); + index_2("0.0040,0.0176,0.0344,0.0656,0.1120,0.2016,0.3800"); + values ("0.2504,0.2396,0.2260,0.1986,0.1625,0.0902,-0.0397",\ +"0.2543,0.2435,0.2298,0.2025,0.1664,0.0941,-0.0358",\ +"0.2579,0.2472,0.2335,0.2062,0.1700,0.0978,-0.0321",\ +"0.2611,0.2504,0.2367,0.2094,0.1732,0.1010,-0.0289",\ +"0.2738,0.2630,0.2493,0.2220,0.1859,0.1136,-0.0163",\ +"0.2914,0.2806,0.2669,0.2396,0.2035,0.1312,0.0013",\ +"0.3189,0.3081,0.2945,0.2671,0.2310,0.1587,0.0288"); + } + } + } + + pin(A_BIST_EN) { + direction : input ; + capacitance : 0.00421562 ; + max_transition : "1" ; + related_power_pin : VDD; + related_ground_pin : VSS; + internal_power() { + rise_power("scalar") { + values (0); + } + fall_power("scalar") { + values (0); + } + } + } + +bus(A_BIST_ADDR) { + bus_type : A_7_0; + direction : input ; + capacitance : 0.00691085 ; + pin(A_BIST_ADDR[0]) { + capacitance : 0.00562034 ; + } + pin(A_BIST_ADDR[1]) { + capacitance : 0.00462655 ; + } + pin(A_BIST_ADDR[2]) { + capacitance : 0.00594295 ; + } + pin(A_BIST_ADDR[3]) { + capacitance : 0.00723434 ; + } + pin(A_BIST_ADDR[4]) { + capacitance : 0.00481603 ; + } + pin(A_BIST_ADDR[5]) { + capacitance : 0.00868123 ; + } + pin(A_BIST_ADDR[6]) { + capacitance : 0.010187 ; + } + max_transition : "0.38" ; + pin(A_BIST_ADDR[7:0]) { + related_power_pin : VDD; + related_ground_pin : VSS; + internal_power() { + when : "A_BIST_MEN"; + rise_power("scalar"){ + values (0.0727); + } + fall_power("scalar"){ + values (0.0037); + } + } + internal_power() { + when : "!A_BIST_MEN"; + rise_power("scalar"){ + values (0.0228); + } + fall_power("scalar"){ + values (0.0010); + } + } + } + timing() { + timing_type : setup_rising; + related_pin : "A_BIST_CLK"; + when : "((A_BIST_WEN | A_BIST_REN)& A_BIST_MEN)" + sdf_cond : "A_BIST_RW_ACCESS" + + rise_constraint("SIG2SRAM_constraint_template") { + index_1("0.0040,0.0176,0.0344,0.0656,0.1120,0.2016,0.3800"); + index_2("0.0040,0.0176,0.0344,0.0656,0.1120,0.2016,0.3800"); + values ("-0.2371,-0.2215,-0.2098,-0.1824,-0.1434,-0.0691,0.0676",\ +"-0.2449,-0.2332,-0.2176,-0.1902,-0.1551,-0.0770,0.0559",\ +"-0.2605,-0.2488,-0.2332,-0.2059,-0.1707,-0.0965,0.0441",\ +"-0.2879,-0.2723,-0.2605,-0.2332,-0.1941,-0.1199,0.0168",\ +"-0.3230,-0.3113,-0.2996,-0.2723,-0.2332,-0.1590,-0.0184",\ +"-0.4012,-0.3895,-0.3738,-0.3465,-0.3074,-0.2332,-0.0965",\ +"-0.5379,-0.5262,-0.5105,-0.4832,-0.4480,-0.3699,-0.2332"); + } + + fall_constraint("SIG2SRAM_constraint_template") { + index_1("0.0040,0.0176,0.0344,0.0656,0.1120,0.2016,0.3800"); + index_2("0.0040,0.0176,0.0344,0.0656,0.1120,0.2016,0.3800"); + values ("-0.1785,-0.1707,-0.1551,-0.1277,-0.0887,-0.0184,0.1145",\ +"-0.1902,-0.1785,-0.1629,-0.1355,-0.1004,-0.0262,0.1027",\ +"-0.2059,-0.1941,-0.1785,-0.1512,-0.1160,-0.0418,0.0871",\ +"-0.2293,-0.2176,-0.2059,-0.1785,-0.1434,-0.0691,0.0598",\ +"-0.2684,-0.2566,-0.2449,-0.2176,-0.1824,-0.1082,0.0207",\ +"-0.3465,-0.3348,-0.3191,-0.2918,-0.2566,-0.1824,-0.0535",\ +"-0.4832,-0.4715,-0.4559,-0.4324,-0.3934,-0.3191,-0.1902"); + } + } + + + timing() { + timing_type : hold_rising; + related_pin : "A_BIST_CLK"; + when : "((A_BIST_WEN | A_BIST_REN)& A_BIST_MEN)" + sdf_cond : "A_BIST_RW_ACCESS" + + rise_constraint("SIG2SRAM_constraint_template") { + index_1("0.0040,0.0176,0.0344,0.0656,0.1120,0.2016,0.3800"); + index_2("0.0040,0.0176,0.0344,0.0656,0.1120,0.2016,0.3800"); + values ("0.3410,0.3293,0.3137,0.2863,0.2473,0.1730,0.0324",\ +"0.3488,0.3371,0.3215,0.2941,0.2590,0.1809,0.0480",\ +"0.3684,0.3527,0.3371,0.3098,0.2746,0.1965,0.0598",\ +"0.3918,0.3762,0.3645,0.3371,0.2980,0.2238,0.0871",\ +"0.4309,0.4152,0.4035,0.3762,0.3371,0.2629,0.1223",\ +"0.5051,0.4934,0.4777,0.4504,0.4113,0.3371,0.1965",\ +"0.6418,0.6262,0.6145,0.5871,0.5520,0.4738,0.3332"); + } + + fall_constraint("SIG2SRAM_constraint_template") { + index_1("0.0040,0.0176,0.0344,0.0656,0.1120,0.2016,0.3800"); + index_2("0.0040,0.0176,0.0344,0.0656,0.1120,0.2016,0.3800"); + values ("0.2824,0.2707,0.2551,0.2277,0.1926,0.1184,-0.0105",\ +"0.2902,0.2785,0.2668,0.2395,0.2043,0.1301,0.0012",\ +"0.3059,0.2941,0.2824,0.2551,0.2199,0.1457,0.0168",\ +"0.3332,0.3215,0.3059,0.2785,0.2434,0.1691,0.0402",\ +"0.3723,0.3605,0.3449,0.3176,0.2824,0.2121,0.0793",\ +"0.4465,0.4348,0.4230,0.3918,0.3566,0.2824,0.1535",\ +"0.5832,0.5715,0.5598,0.5324,0.4934,0.4191,0.2902"); + } + } +} +pin(A_BIST_WEN) { + direction : input ; + capacitance : 0.00341384 ; + max_transition : "0.38" ; + related_power_pin : VDD; + related_ground_pin : VSS; + internal_power() { + when : "A_BIST_MEN"; + rise_power("scalar"){ + values (0.0067); + } + fall_power("scalar"){ + values (0.0158); + } + } + internal_power() { + when : "!A_BIST_MEN"; + rise_power("scalar"){ + values (0.0043); + } + fall_power("scalar"){ + values (0.0211); + } + } + timing() { + timing_type : setup_rising; + related_pin : "A_BIST_CLK"; + when : "A_BIST_MEN" + sdf_cond : "A_BIST_MEN" + + rise_constraint("SIG2SRAM_constraint_template") { + index_1("0.0040,0.0176,0.0344,0.0656,0.1120,0.2016,0.3800"); + index_2("0.0040,0.0176,0.0344,0.0656,0.1120,0.2016,0.3800"); + values ("0.1418,0.1496,0.1652,0.1887,0.2316,0.3059,0.4465",\ +"0.1301,0.1379,0.1535,0.1809,0.2199,0.2941,0.4348",\ +"0.1145,0.1262,0.1379,0.1652,0.2043,0.2785,0.4191",\ +"0.0871,0.0949,0.1105,0.1379,0.1770,0.2512,0.3879",\ +"0.0480,0.0598,0.0754,0.0988,0.1379,0.2082,0.3527",\ +"-0.0262,-0.0145,0.0012,0.0246,0.0676,0.1379,0.2785",\ +"-0.1668,-0.1551,-0.1395,-0.1121,-0.0730,0.0012,0.1418"); + } + + fall_constraint("SIG2SRAM_constraint_template") { + index_1("0.0040,0.0176,0.0344,0.0656,0.1120,0.2016,0.3800"); + index_2("0.0040,0.0176,0.0344,0.0656,0.1120,0.2016,0.3800"); + values ("0.2082,0.2160,0.2316,0.2590,0.2941,0.3684,0.5012",\ +"0.1926,0.2043,0.2199,0.2473,0.2824,0.3566,0.4895",\ +"0.1770,0.1887,0.2043,0.2316,0.2668,0.3410,0.4777",\ +"0.1535,0.1652,0.1770,0.2043,0.2395,0.3137,0.4504",\ +"0.1145,0.1262,0.1379,0.1652,0.2043,0.2746,0.4113",\ +"0.0402,0.0520,0.0676,0.0910,0.1262,0.2004,0.3332",\ +"-0.0965,-0.0848,-0.0730,-0.0457,-0.0066,0.0637,0.2004"); + } + } + + + timing() { + timing_type : hold_rising; + related_pin : "A_BIST_CLK"; + when : "A_BIST_MEN" + sdf_cond : "A_BIST_MEN" + + rise_constraint("SIG2SRAM_constraint_template") { + index_1("0.0040,0.0176,0.0344,0.0656,0.1120,0.2016,0.3800"); + index_2("0.0040,0.0176,0.0344,0.0656,0.1120,0.2016,0.3800"); + values ("0.1770,0.1652,0.1496,0.1223,0.0793,0.0090,-0.1316",\ +"0.1848,0.1730,0.1574,0.1301,0.0910,0.0168,-0.1199",\ +"0.2004,0.1887,0.1770,0.1496,0.1066,0.0363,-0.1043",\ +"0.2277,0.2160,0.2004,0.1730,0.1340,0.0598,-0.0809",\ +"0.2668,0.2551,0.2395,0.2121,0.1730,0.0988,-0.0418",\ +"0.3410,0.3293,0.3137,0.2863,0.2434,0.1730,0.0324",\ +"0.4816,0.4699,0.4543,0.4230,0.3801,0.3098,0.1730"); + } + + fall_constraint("SIG2SRAM_constraint_template") { + index_1("0.0040,0.0176,0.0344,0.0656,0.1120,0.2016,0.3800"); + index_2("0.0040,0.0176,0.0344,0.0656,0.1120,0.2016,0.3800"); + values ("0.1613,0.1496,0.1379,0.1066,0.0715,0.0012,-0.1355",\ +"0.1730,0.1613,0.1457,0.1184,0.0832,0.0129,-0.1238",\ +"0.1887,0.1770,0.1613,0.1340,0.0988,0.0246,-0.1121",\ +"0.2121,0.2043,0.1887,0.1613,0.1223,0.0520,-0.0848",\ +"0.2512,0.2434,0.2277,0.2004,0.1613,0.0910,-0.0457",\ +"0.3254,0.3176,0.3020,0.2746,0.2355,0.1652,0.0324",\ +"0.4660,0.4543,0.4387,0.4113,0.3723,0.3020,0.1691"); + } + } + } +pin(A_BIST_REN) { + direction : input ; + capacitance : 0.00390661 ; + max_transition : "0.38" ; + related_power_pin : VDD; + related_ground_pin : VSS; + internal_power() { + when : "A_BIST_MEN"; + rise_power("scalar"){ + values (0.0101); + } + fall_power("scalar"){ + values (0.0113); + } + } + internal_power() { + when : "!A_BIST_MEN"; + rise_power("scalar"){ + values (0.0244); + } + fall_power("scalar"){ + values (0.0204); + } + } + timing() { + timing_type : setup_rising; + related_pin : "A_BIST_CLK"; + when : "A_BIST_MEN" + sdf_cond : "A_BIST_MEN" + + rise_constraint("SIG2SRAM_constraint_template") { + index_1("0.0040,0.0176,0.0344,0.0656,0.1120,0.2016,0.3800"); + index_2("0.0040,0.0176,0.0344,0.0656,0.1120,0.2016,0.3800"); + values ("-0.0027,0.0090,0.0246,0.0520,0.0910,0.1613,0.3020",\ +"-0.0105,0.0012,0.0129,0.0363,0.0793,0.1535,0.2902",\ +"-0.0262,-0.0145,-0.0027,0.0246,0.0637,0.1379,0.2785",\ +"-0.0535,-0.0418,-0.0262,0.0012,0.0363,0.1105,0.2512",\ +"-0.0926,-0.0809,-0.0652,-0.0418,-0.0027,0.0715,0.2121",\ +"-0.1668,-0.1551,-0.1395,-0.1082,-0.0770,-0.0027,0.1379",\ +"-0.3035,-0.2918,-0.2762,-0.2488,-0.2137,-0.1434,-0.0027"); + } + + fall_constraint("SIG2SRAM_constraint_template") { + index_1("0.0040,0.0176,0.0344,0.0656,0.1120,0.2016,0.3800"); + index_2("0.0040,0.0176,0.0344,0.0656,0.1120,0.2016,0.3800"); + values ("0.0832,0.0949,0.1105,0.1379,0.1730,0.2473,0.3801",\ +"0.0754,0.0832,0.0988,0.1223,0.1613,0.2355,0.3684",\ +"0.0598,0.0676,0.0832,0.1066,0.1457,0.2121,0.3527",\ +"0.0324,0.0441,0.0598,0.0871,0.1223,0.1926,0.3293",\ +"-0.0066,0.0051,0.0168,0.0480,0.0832,0.1535,0.2902",\ +"-0.0809,-0.0691,-0.0574,-0.0301,0.0090,0.0832,0.2121",\ +"-0.2176,-0.2059,-0.1941,-0.1668,-0.1277,-0.0574,0.0793"); + } + } + + + timing() { + timing_type : hold_rising; + related_pin : "A_BIST_CLK"; + when : "A_BIST_MEN" + sdf_cond : "A_BIST_MEN" + + rise_constraint("SIG2SRAM_constraint_template") { + index_1("0.0040,0.0176,0.0344,0.0656,0.1120,0.2016,0.3800"); + index_2("0.0040,0.0176,0.0344,0.0656,0.1120,0.2016,0.3800"); + values ("0.1887,0.1770,0.1613,0.1340,0.0949,0.0207,-0.1160",\ +"0.1965,0.1848,0.1730,0.1457,0.1027,0.0324,-0.1082",\ +"0.2160,0.2004,0.1887,0.1613,0.1184,0.0480,-0.0926",\ +"0.2395,0.2277,0.2121,0.1848,0.1457,0.0715,-0.0652",\ +"0.2785,0.2668,0.2512,0.2238,0.1848,0.1105,-0.0262",\ +"0.3527,0.3410,0.3254,0.2980,0.2551,0.1848,0.0480",\ +"0.4934,0.4816,0.4660,0.4387,0.3957,0.3254,0.1887"); + } + + fall_constraint("SIG2SRAM_constraint_template") { + index_1("0.0040,0.0176,0.0344,0.0656,0.1120,0.2016,0.3800"); + index_2("0.0040,0.0176,0.0344,0.0656,0.1120,0.2016,0.3800"); + values ("0.1730,0.1613,0.1496,0.1184,0.0793,0.0129,-0.1238",\ +"0.1848,0.1730,0.1574,0.1301,0.0910,0.0207,-0.1121",\ +"0.2004,0.1887,0.1730,0.1457,0.1066,0.0363,-0.1004",\ +"0.2238,0.2121,0.2004,0.1691,0.1340,0.0598,-0.0730",\ +"0.2629,0.2512,0.2395,0.2121,0.1691,0.0988,-0.0340",\ +"0.3371,0.3254,0.3137,0.2863,0.2434,0.1730,0.0402",\ +"0.4777,0.4660,0.4504,0.4230,0.3840,0.3137,0.1809"); + } + } + } +pin(A_BIST_MEN) { + direction : input ; + capacitance : 0.00326046 ; + max_transition : "0.38" ; + related_power_pin : VDD; + related_ground_pin : VSS; + internal_power() { + rise_power("scalar"){ + values (0.0869); + } + fall_power("scalar"){ + values (0.0777); + } + } + timing() { + timing_type : setup_rising; + related_pin : "A_BIST_CLK"; + + rise_constraint("SIG2SRAM_constraint_template") { + index_1("0.0040,0.0176,0.0344,0.0656,0.1120,0.2016,0.3800"); + index_2("0.0040,0.0176,0.0344,0.0656,0.1120,0.2016,0.3800"); + values ("0.1418,0.1496,0.1652,0.1926,0.2316,0.3059,0.4465",\ +"0.1301,0.1379,0.1535,0.1809,0.2199,0.2941,0.4348",\ +"0.1145,0.1262,0.1418,0.1652,0.2043,0.2785,0.4191",\ +"0.0871,0.0949,0.1105,0.1379,0.1770,0.2512,0.3879",\ +"0.0480,0.0598,0.0754,0.0988,0.1379,0.2082,0.3488",\ +"-0.0262,-0.0145,0.0012,0.0285,0.0676,0.1379,0.2785",\ +"-0.1668,-0.1551,-0.1395,-0.1121,-0.0730,0.0012,0.1379"); + } + + fall_constraint("SIG2SRAM_constraint_template") { + index_1("0.0040,0.0176,0.0344,0.0656,0.1120,0.2016,0.3800"); + index_2("0.0040,0.0176,0.0344,0.0656,0.1120,0.2016,0.3800"); + values ("0.2082,0.2199,0.2316,0.2590,0.2980,0.3723,0.5051",\ +"0.1965,0.2082,0.2199,0.2473,0.2863,0.3605,0.4934",\ +"0.1809,0.1926,0.2043,0.2316,0.2707,0.3449,0.4777",\ +"0.1574,0.1691,0.1809,0.2082,0.2434,0.3176,0.4543",\ +"0.1145,0.1262,0.1418,0.1691,0.2043,0.2785,0.4113",\ +"0.0441,0.0559,0.0676,0.0949,0.1301,0.2004,0.3332",\ +"-0.0965,-0.0848,-0.0691,-0.0418,-0.0066,0.0676,0.2004"); + } + } + + + timing() { + timing_type : hold_rising; + related_pin : "A_BIST_CLK"; + + rise_constraint("SIG2SRAM_constraint_template") { + index_1("0.0040,0.0176,0.0344,0.0656,0.1120,0.2016,0.3800"); + index_2("0.0040,0.0176,0.0344,0.0656,0.1120,0.2016,0.3800"); + values ("0.1770,0.1652,0.1535,0.1262,0.0832,0.0129,-0.1277",\ +"0.1887,0.1770,0.1613,0.1340,0.0949,0.0207,-0.1199",\ +"0.2043,0.1926,0.1770,0.1496,0.1105,0.0363,-0.1043",\ +"0.2277,0.2160,0.2043,0.1770,0.1379,0.0598,-0.0770",\ +"0.2668,0.2551,0.2434,0.2160,0.1730,0.0988,-0.0379",\ +"0.3449,0.3332,0.3176,0.2902,0.2473,0.1730,0.0363",\ +"0.4816,0.4699,0.4543,0.4270,0.3840,0.3098,0.1770"); + } + + fall_constraint("SIG2SRAM_constraint_template") { + index_1("0.0040,0.0176,0.0344,0.0656,0.1120,0.2016,0.3800"); + index_2("0.0040,0.0176,0.0344,0.0656,0.1120,0.2016,0.3800"); + values ("0.1613,0.1496,0.1379,0.1105,0.0715,0.0012,-0.1355",\ +"0.1730,0.1613,0.1496,0.1184,0.0832,0.0129,-0.1238",\ +"0.1887,0.1770,0.1652,0.1340,0.0988,0.0285,-0.1121",\ +"0.2121,0.2043,0.1887,0.1613,0.1223,0.0520,-0.0848",\ +"0.2551,0.2434,0.2277,0.2004,0.1613,0.0910,-0.0418",\ +"0.3293,0.3176,0.3020,0.2746,0.2395,0.1652,0.0324",\ +"0.4660,0.4543,0.4426,0.4113,0.3762,0.3020,0.1691"); + } + } + } +bus(A_BIST_BM) { + bus_type : D_7_0; + direction : input ; + capacitance : 0.00252172 ; + max_transition : "0.38" ; + pin(A_BIST_BM[7:0]) { + related_power_pin : VDD; + related_ground_pin : VSS; + internal_power() { + when : "A_BIST_MEN"; + rise_power("scalar"){ + values (0.0324); + } + fall_power("scalar"){ + values (0.0401); + } + } + internal_power() { + when : "!A_BIST_MEN"; + rise_power("scalar"){ + values (0.0522); + } + fall_power("scalar"){ + values (0.0509); + } + } + } + timing() { + timing_type : setup_rising; + related_pin : "A_BIST_CLK"; + when : "(A_BIST_WEN & A_BIST_MEN)" + sdf_cond : "A_BIST_RW_ACCESS" + + rise_constraint("SIG2SRAM_constraint_template") { + index_1("0.0040,0.0176,0.0344,0.0656,0.1120,0.2016,0.3800"); + index_2("0.0040,0.0176,0.0344,0.0656,0.1120,0.2016,0.3800"); + values ("-0.1737,-0.1630,-0.1473,-0.1219,-0.0809,-0.0077,0.1271",\ +"-0.1776,-0.1668,-0.1512,-0.1258,-0.0848,-0.0116,0.1232",\ +"-0.1813,-0.1705,-0.1549,-0.1295,-0.0885,-0.0153,0.1195",\ +"-0.1845,-0.1737,-0.1581,-0.1327,-0.0917,-0.0185,0.1163",\ +"-0.1971,-0.1863,-0.1707,-0.1453,-0.1043,-0.0311,0.1037",\ +"-0.2147,-0.2040,-0.1883,-0.1629,-0.1219,-0.0487,0.0861",\ +"-0.2422,-0.2315,-0.2158,-0.1904,-0.1494,-0.0762,0.0586"); + } + + fall_constraint("SIG2SRAM_constraint_template") { + index_1("0.0040,0.0176,0.0344,0.0656,0.1120,0.2016,0.3800"); + index_2("0.0040,0.0176,0.0344,0.0656,0.1120,0.2016,0.3800"); + values ("-0.1503,-0.1385,-0.1259,-0.0985,-0.0614,0.0118,0.1398",\ +"-0.1542,-0.1424,-0.1297,-0.1024,-0.0653,0.0080,0.1359",\ +"-0.1578,-0.1461,-0.1334,-0.1061,-0.0690,0.0043,0.1322",\ +"-0.1610,-0.1493,-0.1366,-0.1093,-0.0722,0.0011,0.1290",\ +"-0.1736,-0.1619,-0.1492,-0.1219,-0.0848,-0.0115,0.1164",\ +"-0.1913,-0.1795,-0.1668,-0.1395,-0.1024,-0.0292,0.0988",\ +"-0.2188,-0.2070,-0.1943,-0.1670,-0.1299,-0.0567,0.0713"); + } + } + + + timing() { + timing_type : hold_rising; + related_pin : "A_BIST_CLK"; + when : "(A_BIST_WEN & A_BIST_MEN)" + sdf_cond : "A_BIST_RW_ACCESS" + + rise_constraint("SIG2SRAM_constraint_template") { + index_1("0.0040,0.0176,0.0344,0.0656,0.1120,0.2016,0.3800"); + index_2("0.0040,0.0176,0.0344,0.0656,0.1120,0.2016,0.3800"); + values ("0.2787,0.2689,0.2533,0.2269,0.1898,0.1156,-0.0192",\ +"0.2826,0.2728,0.2572,0.2308,0.1937,0.1195,-0.0153",\ +"0.2863,0.2765,0.2609,0.2345,0.1974,0.1232,-0.0116",\ +"0.2895,0.2797,0.2641,0.2377,0.2006,0.1264,-0.0084",\ +"0.3021,0.2923,0.2767,0.2503,0.2132,0.1390,0.0042",\ +"0.3197,0.3099,0.2943,0.2679,0.2308,0.1566,0.0218",\ +"0.3472,0.3374,0.3218,0.2954,0.2583,0.1841,0.0493"); + } + + fall_constraint("SIG2SRAM_constraint_template") { + index_1("0.0040,0.0176,0.0344,0.0656,0.1120,0.2016,0.3800"); + index_2("0.0040,0.0176,0.0344,0.0656,0.1120,0.2016,0.3800"); + values ("0.2504,0.2396,0.2260,0.1986,0.1625,0.0902,-0.0397",\ +"0.2543,0.2435,0.2298,0.2025,0.1664,0.0941,-0.0358",\ +"0.2579,0.2472,0.2335,0.2062,0.1700,0.0978,-0.0321",\ +"0.2611,0.2504,0.2367,0.2094,0.1732,0.1010,-0.0289",\ +"0.2738,0.2630,0.2493,0.2220,0.1859,0.1136,-0.0163",\ +"0.2914,0.2806,0.2669,0.2396,0.2035,0.1312,0.0013",\ +"0.3189,0.3081,0.2945,0.2671,0.2310,0.1587,0.0288"); + } + } +} + pin(A_BIST_CLK) { + direction : input; + capacitance : 0.00389386; + max_transition : "0.38"; + clock : "true" ; + pin_func_type : active_rising ; + + timing () { + timing_type : "min_pulse_width"; + related_pin : "A_BIST_CLK"; + rise_constraint("CLKTRAN_constraint_template") { + index_1("0.004,0.38"); + values("0.12,0.12"); + } + } + + related_power_pin : VDD; + related_ground_pin : VSS; + + internal_power() { + when : "!A_BIST_MEN & !A_BIST_WEN & !A_BIST_REN"; + rise_power("scalar"){ + values (0); + } + fall_power("scalar"){ + values (0); + } + } + internal_power() { + when : "!A_BIST_MEN & A_BIST_WEN & !A_BIST_REN"; + rise_power("scalar"){ + values (0.6006); + } + fall_power("scalar"){ + values (0); + } + } + internal_power() { + when : "A_BIST_MEN & A_BIST_WEN & !A_BIST_REN"; + rise_power("scalar"){ + values (15.9843); + } + fall_power("scalar"){ + values (0); + } + } + internal_power() { + when : "A_BIST_MEN & A_BIST_WEN & A_BIST_REN"; + rise_power("scalar"){ + values (16.1453); + } + fall_power("scalar"){ + values (0); + } + } + internal_power() { + when : "A_BIST_MEN & !A_BIST_WEN & A_BIST_REN"; + rise_power("scalar"){ + values (11.9622); + } + fall_power("scalar"){ + values (0); + } + } + internal_power() { + when : "!A_BIST_MEN & !A_BIST_WEN & A_BIST_REN"; + rise_power("scalar"){ + values (0.3950); + } + fall_power("scalar"){ + values (0); + } + } + internal_power() { + when : "!A_BIST_MEN & A_BIST_WEN & A_BIST_REN"; + rise_power("scalar"){ + values (0.6485); + } + fall_power("scalar"){ + values (0); + } + } + internal_power() { + when : "A_BIST_MEN & !A_BIST_WEN & !A_BIST_REN"; + rise_power("scalar"){ + values (0); + } + fall_power("scalar"){ + values (0); + } + } + } + bus(A_BIST_DIN) { + bus_type : D_7_0; + direction : input ; + capacitance : 0.00252023 ; + memory_write() { + address : A_BIST_ADDR ; + clocked_on : A_BIST_CLK; + } + + max_transition : "0.38" ; + pin(A_BIST_DIN[7:0]) { + related_power_pin : VDD; + related_ground_pin : VSS; + internal_power() { + when : "A_BIST_MEN"; + rise_power("scalar"){ + values (0.0324); + } + fall_power("scalar"){ + values (0.0401); + } + } + internal_power() { + when : "!A_BIST_MEN"; + rise_power("scalar"){ + values (0.0522); + } + fall_power("scalar"){ + values (0.0509); + } + } + } + timing() { + timing_type : setup_rising; + related_pin : "A_BIST_CLK"; + when : "(A_BIST_WEN & A_BIST_MEN)"; + sdf_cond : "A_BIST_W_ACCESS"; + + rise_constraint("SIG2SRAM_constraint_template") { + index_1("0.0040,0.0176,0.0344,0.0656,0.1120,0.2016,0.3800"); + index_2("0.0040,0.0176,0.0344,0.0656,0.1120,0.2016,0.3800"); + values ("-0.1737,-0.1630,-0.1473,-0.1219,-0.0809,-0.0077,0.1271",\ +"-0.1776,-0.1668,-0.1512,-0.1258,-0.0848,-0.0116,0.1232",\ +"-0.1813,-0.1705,-0.1549,-0.1295,-0.0885,-0.0153,0.1195",\ +"-0.1845,-0.1737,-0.1581,-0.1327,-0.0917,-0.0185,0.1163",\ +"-0.1971,-0.1863,-0.1707,-0.1453,-0.1043,-0.0311,0.1037",\ +"-0.2147,-0.2040,-0.1883,-0.1629,-0.1219,-0.0487,0.0861",\ +"-0.2422,-0.2315,-0.2158,-0.1904,-0.1494,-0.0762,0.0586"); + } + + fall_constraint("SIG2SRAM_constraint_template") { + index_1("0.0040,0.0176,0.0344,0.0656,0.1120,0.2016,0.3800"); + index_2("0.0040,0.0176,0.0344,0.0656,0.1120,0.2016,0.3800"); + values ("-0.1503,-0.1385,-0.1259,-0.0985,-0.0614,0.0118,0.1398",\ +"-0.1542,-0.1424,-0.1297,-0.1024,-0.0653,0.0080,0.1359",\ +"-0.1578,-0.1461,-0.1334,-0.1061,-0.0690,0.0043,0.1322",\ +"-0.1610,-0.1493,-0.1366,-0.1093,-0.0722,0.0011,0.1290",\ +"-0.1736,-0.1619,-0.1492,-0.1219,-0.0848,-0.0115,0.1164",\ +"-0.1913,-0.1795,-0.1668,-0.1395,-0.1024,-0.0292,0.0988",\ +"-0.2188,-0.2070,-0.1943,-0.1670,-0.1299,-0.0567,0.0713"); + } + } + + timing() { + timing_type : hold_rising; + related_pin : "A_BIST_CLK"; + when : "(A_BIST_WEN & A_BIST_MEN)"; + sdf_cond : "A_BIST_W_ACCESS"; + + rise_constraint("SIG2SRAM_constraint_template") { + index_1("0.0040,0.0176,0.0344,0.0656,0.1120,0.2016,0.3800"); + index_2("0.0040,0.0176,0.0344,0.0656,0.1120,0.2016,0.3800"); + values ("0.2787,0.2689,0.2533,0.2269,0.1898,0.1156,-0.0192",\ +"0.2826,0.2728,0.2572,0.2308,0.1937,0.1195,-0.0153",\ +"0.2863,0.2765,0.2609,0.2345,0.1974,0.1232,-0.0116",\ +"0.2895,0.2797,0.2641,0.2377,0.2006,0.1264,-0.0084",\ +"0.3021,0.2923,0.2767,0.2503,0.2132,0.1390,0.0042",\ +"0.3197,0.3099,0.2943,0.2679,0.2308,0.1566,0.0218",\ +"0.3472,0.3374,0.3218,0.2954,0.2583,0.1841,0.0493"); + } + + fall_constraint("SIG2SRAM_constraint_template") { + index_1("0.0040,0.0176,0.0344,0.0656,0.1120,0.2016,0.3800"); + index_2("0.0040,0.0176,0.0344,0.0656,0.1120,0.2016,0.3800"); + values ("0.2504,0.2396,0.2260,0.1986,0.1625,0.0902,-0.0397",\ +"0.2543,0.2435,0.2298,0.2025,0.1664,0.0941,-0.0358",\ +"0.2579,0.2472,0.2335,0.2062,0.1700,0.0978,-0.0321",\ +"0.2611,0.2504,0.2367,0.2094,0.1732,0.1010,-0.0289",\ +"0.2738,0.2630,0.2493,0.2220,0.1859,0.1136,-0.0163",\ +"0.2914,0.2806,0.2669,0.2396,0.2035,0.1312,0.0013",\ +"0.3189,0.3081,0.2945,0.2671,0.2310,0.1587,0.0288"); + } + } + } + +bus(A_DOUT) { + + bus_type : D_7_0; + direction : output ; + capacitance : 0 ; + max_capacitance : 0.064 ; + memory_read() { + address : A_ADDR ; + } + pin(A_DOUT[7:0]) { + related_power_pin : VDD; + related_ground_pin : VSS; + internal_power() { + rise_power("scalar") { + values (0); + } + fall_power("scalar") { + values (0); + } + } + } + timing() { + related_pin : "A_CLK"; + timing_type : rising_edge ; + timing_sense : non_unate ; + + cell_rise(SIG2SRAM_delay_template) { + index_1("0.0040,0.0176,0.0344,0.0656,0.1120,0.2016,0.3800"); + index_2("0.0008,0.0014,0.0051,0.0100,0.0339,0.0640"); + values ("1.8180,1.8190,1.8238,1.8293,1.8502,1.8737",\ +"1.8239,1.8249,1.8297,1.8352,1.8562,1.8797",\ +"1.8267,1.8277,1.8325,1.8380,1.8589,1.8824",\ +"1.8309,1.8319,1.8367,1.8422,1.8631,1.8866",\ +"1.8425,1.8435,1.8483,1.8538,1.8747,1.8982",\ +"1.8616,1.8626,1.8674,1.8729,1.8938,1.9173",\ +"1.8880,1.8890,1.8938,1.8993,1.9202,1.9437"); + } + cell_fall(SIG2SRAM_delay_template) { + index_1("0.0040,0.0176,0.0344,0.0656,0.1120,0.2016,0.3800"); + index_2("0.0008,0.0014,0.0051,0.0100,0.0339,0.0640"); + values ("1.7837,1.7845,1.7886,1.7931,1.8102,1.8269",\ +"1.7896,1.7905,1.7945,1.7991,1.8162,1.8329",\ +"1.7924,1.7932,1.7973,1.8018,1.8189,1.8356",\ +"1.7966,1.7974,1.8015,1.8060,1.8231,1.8398",\ +"1.8082,1.8090,1.8131,1.8176,1.8347,1.8514",\ +"1.8273,1.8282,1.8322,1.8368,1.8538,1.8706",\ +"1.8537,1.8545,1.8586,1.8631,1.8802,1.8969"); + } + + rise_transition(SRAM_load_template) { + index_1("0.0008,0.0014,0.0051,0.0100,0.0339,0.0640"); + values ("0.0206,0.0210,0.0265,0.0323,0.0606,0.0955"); + } + fall_transition(SRAM_load_template) { + index_1("0.0008,0.0014,0.0051,0.0100,0.0339,0.0640"); + values ("0.0170,0.0177,0.0222,0.0270,0.0451,0.0644"); + } + } +} +cell_leakage_power : 58.6993; +} +} diff --git a/flow/platforms/ihp-sg13g2/lib/RM_IHPSG13_1P_256x8_c3_bm_bist_slow_1p08V_125C.lib b/flow/platforms/ihp-sg13g2/lib/RM_IHPSG13_1P_256x8_c3_bm_bist_slow_1p08V_125C.lib new file mode 100644 index 0000000000..03be2ca100 --- /dev/null +++ b/flow/platforms/ihp-sg13g2/lib/RM_IHPSG13_1P_256x8_c3_bm_bist_slow_1p08V_125C.lib @@ -0,0 +1,1513 @@ +/* ------------------------------------------------------*/ +/**/ +/* Copyright 2025 IHP PDK Authors*/ +/**/ +/* Licensed under the Apache License, Version 2.0 (the "License");*/ +/* you may not use this file except in compliance with the License.*/ +/* You may obtain a copy of the License at*/ +/* */ +/* https://www.apache.org/licenses/LICENSE-2.0*/ +/* */ +/* Unless required by applicable law or agreed to in writing, software*/ +/* distributed under the License is distributed on an "AS IS" BASIS,*/ +/* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.*/ +/* See the License for the specific language governing permissions and*/ +/* limitations under the License.*/ +/* */ +/* Generated on Wed Aug 27 16:22:40 2025 */ +/* */ +/* ------------------------------------------------------ */ +library(RM_IHPSG13_1P_256x8_c3_bm_bist_slow_1p08V_125C) { + technology (cmos) ; + delay_model : table_lookup ; + define ("add_pg_pin_to_lib", "library", "boolean"); + add_pg_pin_to_lib : true; + voltage_map ( VDD, 1.08); + voltage_map ( VDDARRAY, 1.08); + voltage_map ( VSS, 0.000000 ); + + date : "Wed Aug 27 16:22:39 2025" ; + comment : "IHP Microelectronics GmbH, 2023" ; + revision : 1.0.0 ; + simulation : true ; + nom_process : 1 ; + nom_temperature : 125 ; + nom_voltage : 1.08 ; + + operating_conditions("slow_1p08V_125C"){ + process : 1 ; + temperature : 125 ; + voltage : 1.08 ; + tree_type : "balanced_tree" ; + } + + default_operating_conditions : slow_1p08V_125C ; + default_max_transition : 1.0 ; + default_fanout_load : 1.0 ; + default_inout_pin_cap : 0.0 ; + default_input_pin_cap : 0.0 ; + default_output_pin_cap : 0.0 ; + default_cell_leakage_power : 0.0 ; + default_leakage_power_density : 0.0 ; + + slew_lower_threshold_pct_rise : 30 ; + slew_upper_threshold_pct_rise : 70 ; + input_threshold_pct_fall : 50 ; + output_threshold_pct_fall : 50 ; + input_threshold_pct_rise : 50 ; + output_threshold_pct_rise : 50 ; + slew_lower_threshold_pct_fall : 30 ; + slew_upper_threshold_pct_fall : 70 ; + slew_derate_from_library : 0.5; + k_volt_cell_leakage_power : 0.0 ; + k_temp_cell_leakage_power : 0.0 ; + k_process_cell_leakage_power : 0.0 ; + k_volt_internal_power : 0.0 ; + k_temp_internal_power : 0.0 ; + k_process_internal_power : 0.0 ; + + capacitive_load_unit (1,pf) ; + voltage_unit : "1V" ; + current_unit : "1uA" ; + time_unit : "1ns" ; + leakage_power_unit : "1nW" ; + pulling_resistance_unit : "1kohm"; + /* + ------------------------------------------------------------------------------------------ + implicit units overview: + cell_area unit : "um" + internal_power unit : "1e-12 * J/toggle = 1 * uW/MHz" + (capacitive_load_unit * voltage_unit^2) per toggle event + ------------------------------------------------------------------------------------------ + */ + library_features(report_delay_calculation); + define_cell_area (pad_drivers,pad_driver_sites) ; + + lu_table_template(CLKTRAN_constraint_template) { + variable_1 : constrained_pin_transition; + index_1 ( "0.010, 0.050, 0.200, 0.400, 1.000" ); + } + lu_table_template(SRAM_load_template) { + variable_1 : total_output_net_capacitance; + index_1 ( "0.0008,0.0014,0.0051,0.0100,0.0339,0.0640" ); + } + lu_table_template(SIG2SRAM_constraint_template) { + variable_1 : related_pin_transition; + variable_2 : constrained_pin_transition; + index_1 ( "0.0080,0.0288,0.0616,0.1072,0.1920,0.3496,0.5952" ); + index_2 ( "0.0080,0.0288,0.0616,0.1072,0.1920,0.3496,0.5952" ); + } + + lu_table_template(SIG2SRAM_delay_template) { + variable_1 : input_net_transition; + variable_2 : total_output_net_capacitance; + index_1 ( "0.0080,0.0288,0.0616,0.1072,0.1920,0.3496,0.5952" ); + index_2 ( "0.0008,0.0014,0.0051,0.0100,0.0339,0.0640" ); + } + + type (D_7_0) { + base_type : array; + data_type : bit; + bit_width : 8; + bit_from : 7; + bit_to : 0; + downto : true; + } + + type (A_7_0) { + base_type : array; + data_type : bit; + bit_width : 8; + bit_from : 7; + bit_to : 0; + downto : true; + } + +cell(RM_IHPSG13_1P_256x8_c3_bm_bist) { +pg_pin (VDD) { + pg_type : primary_power; + voltage_name : VDD; +} +pg_pin (VDDARRAY) { + pg_type : primary_power; + voltage_name : VDDARRAY; +} +pg_pin (VSS) { + pg_type : primary_ground; + voltage_name : VSS; +} + +memory() { + type : ram; + address_width : 8; + word_width : 8; +} + +interface_timing : false; +bus_naming_style : "%s[%d]" ; +area : 17546.88 ; + + pin(A_DLY) { + direction : input ; + capacitance : 0.00387999 ; + max_transition : "1" ; + related_power_pin : VDD; + related_ground_pin : VSS; + internal_power() { + rise_power("scalar") { + values (0); + } + fall_power("scalar") { + values (0); + } + } + } + +bus(A_ADDR) { + bus_type : A_7_0; + direction : input ; + capacitance : 0.0077013 ; + pin(A_ADDR[0]) { + capacitance : 0.00625349 ; + } + pin(A_ADDR[1]) { + capacitance : 0.00507435 ; + } + pin(A_ADDR[2]) { + capacitance : 0.00656707 ; + } + pin(A_ADDR[3]) { + capacitance : 0.0083133 ; + } + pin(A_ADDR[4]) { + capacitance : 0.00507219 ; + } + pin(A_ADDR[5]) { + capacitance : 0.00964344 ; + } + pin(A_ADDR[6]) { + capacitance : 0.0119653 ; + } + max_transition : "0.5952" ; + pin(A_ADDR[7:0]) { + related_power_pin : VDD; + related_ground_pin : VSS; + internal_power() { + when : "A_MEN"; + rise_power("scalar"){ + values (0.0182); + } + fall_power("scalar"){ + values (0.0047); + } + } + internal_power() { + when : "!A_MEN"; + rise_power("scalar"){ + values (0.0159); + } + fall_power("scalar"){ + values (0.0002); + } + } + } + timing() { + timing_type : setup_rising; + related_pin : "A_CLK"; + when : "((A_WEN | A_REN)& A_MEN)" + sdf_cond : "A_RW_ACCESS" + + rise_constraint("SIG2SRAM_constraint_template") { + index_1("0.0080,0.0288,0.0616,0.1072,0.1920,0.3496,0.5952"); + index_2("0.0080,0.0288,0.0616,0.1072,0.1920,0.3496,0.5952"); + values ("-0.7371,-0.7176,-0.6863,-0.6434,-0.5652,-0.4168,-0.1980",\ +"-0.7566,-0.7371,-0.7059,-0.6629,-0.5848,-0.4363,-0.2137",\ +"-0.7879,-0.7645,-0.7332,-0.6902,-0.6121,-0.4637,-0.2449",\ +"-0.8309,-0.8074,-0.7762,-0.7332,-0.6551,-0.5066,-0.2879",\ +"-0.9051,-0.8895,-0.8543,-0.8113,-0.7332,-0.5887,-0.3660",\ +"-1.0418,-1.0262,-0.9949,-0.9480,-0.8699,-0.7293,-0.5027",\ +"-1.2684,-1.2449,-1.2176,-1.1707,-1.0965,-0.9480,-0.7293"); + } + + fall_constraint("SIG2SRAM_constraint_template") { + index_1("0.0080,0.0288,0.0616,0.1072,0.1920,0.3496,0.5952"); + index_2("0.0080,0.0288,0.0616,0.1072,0.1920,0.3496,0.5952"); + values ("-0.5926,-0.5730,-0.5418,-0.4988,-0.4246,-0.2879,-0.0730",\ +"-0.6121,-0.5926,-0.5613,-0.5223,-0.4441,-0.3074,-0.0887",\ +"-0.6395,-0.6199,-0.5926,-0.5496,-0.4715,-0.3348,-0.1160",\ +"-0.6863,-0.6668,-0.6355,-0.5965,-0.5184,-0.3777,-0.1590",\ +"-0.7605,-0.7410,-0.7137,-0.6746,-0.5926,-0.4559,-0.2410",\ +"-0.9012,-0.8816,-0.8504,-0.8113,-0.7332,-0.5926,-0.3895",\ +"-1.1238,-1.1043,-1.0769,-1.0379,-0.9559,-0.8191,-0.6004"); + } + } + + + timing() { + timing_type : hold_rising; + related_pin : "A_CLK"; + when : "((A_WEN | A_REN)& A_MEN)" + sdf_cond : "A_RW_ACCESS" + + rise_constraint("SIG2SRAM_constraint_template") { + index_1("0.0080,0.0288,0.0616,0.1072,0.1920,0.3496,0.5952"); + index_2("0.0080,0.0288,0.0616,0.1072,0.1920,0.3496,0.5952"); + values ("0.8488,0.8293,0.7980,0.7551,0.6730,0.5285,0.3059",\ +"0.8684,0.8488,0.8176,0.7746,0.6926,0.5480,0.3254",\ +"0.8996,0.8801,0.8449,0.8020,0.7238,0.5754,0.3527",\ +"0.9426,0.9191,0.8918,0.8488,0.7668,0.6223,0.3996",\ +"1.0168,1.0012,0.9699,0.9230,0.8449,0.7004,0.4777",\ +"1.1574,1.1379,1.1105,1.0598,0.9816,0.8371,0.6184",\ +"1.3801,1.3605,1.3254,1.2980,1.2043,1.0637,0.8371"); + } + + fall_constraint("SIG2SRAM_constraint_template") { + index_1("0.0080,0.0288,0.0616,0.1072,0.1920,0.3496,0.5952"); + index_2("0.0080,0.0288,0.0616,0.1072,0.1920,0.3496,0.5952"); + values ("0.6965,0.6770,0.6496,0.6066,0.5246,0.3918,0.1730",\ +"0.7160,0.6965,0.6652,0.6262,0.5441,0.4113,0.1965",\ +"0.7473,0.7277,0.6965,0.6535,0.5754,0.4426,0.2238",\ +"0.7863,0.7707,0.7395,0.7004,0.6223,0.4855,0.2629",\ +"0.8684,0.8449,0.8176,0.7785,0.7004,0.5637,0.3449",\ +"1.0051,0.9855,0.9855,0.9113,0.8332,0.7004,0.4895",\ +"1.2277,1.2082,1.1809,1.1379,1.0598,0.9230,0.7004"); + } + } +} +pin(A_WEN) { + direction : input ; + capacitance : 0.00313551 ; + max_transition : "0.5952" ; + related_power_pin : VDD; + related_ground_pin : VSS; + internal_power() { + when : "A_MEN"; + rise_power("scalar"){ + values (0.0127); + } + fall_power("scalar"){ + values (0.0103); + } + } + internal_power() { + when : "!A_MEN"; + rise_power("scalar"){ + values (0.0040); + } + fall_power("scalar"){ + values (0.0006); + } + } + timing() { + timing_type : setup_rising; + related_pin : "A_CLK"; + when : "A_MEN" + sdf_cond : "A_MEN" + + rise_constraint("SIG2SRAM_constraint_template") { + index_1("0.0080,0.0288,0.0616,0.1072,0.1920,0.3496,0.5952"); + index_2("0.0080,0.0288,0.0616,0.1072,0.1920,0.3496,0.5952"); + values ("0.3137,0.3332,0.3605,0.4035,0.4816,0.6223,0.8488",\ +"0.2980,0.3176,0.3410,0.3840,0.4660,0.6027,0.8293",\ +"0.2629,0.2824,0.3098,0.3527,0.4348,0.5754,0.7980",\ +"0.2199,0.2395,0.2668,0.3098,0.3918,0.5324,0.7590",\ +"0.1418,0.1613,0.1887,0.2316,0.3137,0.4348,0.6730",\ +"0.0012,0.0207,0.0520,0.0910,0.1730,0.3098,0.5285",\ +"-0.2215,-0.2020,-0.1746,-0.1277,-0.0496,0.0910,0.3098"); + } + + fall_constraint("SIG2SRAM_constraint_template") { + index_1("0.0080,0.0288,0.0616,0.1072,0.1920,0.3496,0.5952"); + index_2("0.0080,0.0288,0.0616,0.1072,0.1920,0.3496,0.5952"); + values ("0.4504,0.4699,0.4973,0.5324,0.6027,0.7355,0.9699",\ +"0.4309,0.4504,0.4777,0.5129,0.5910,0.7160,0.9504",\ +"0.3996,0.4191,0.4465,0.4816,0.5520,0.6848,0.9191",\ +"0.3605,0.3762,0.4035,0.4387,0.5168,0.6418,0.8723",\ +"0.2785,0.2980,0.3215,0.3605,0.4348,0.5637,0.7980",\ +"0.1379,0.1574,0.1809,0.2199,0.2980,0.4309,0.6457",\ +"-0.0809,-0.0613,-0.0340,0.0051,0.0832,0.2160,0.4191"); + } + } + + + timing() { + timing_type : hold_rising; + related_pin : "A_CLK"; + when : "A_MEN" + sdf_cond : "A_MEN" + + rise_constraint("SIG2SRAM_constraint_template") { + index_1("0.0080,0.0288,0.0616,0.1072,0.1920,0.3496,0.5952"); + index_2("0.0080,0.0288,0.0616,0.1072,0.1920,0.3496,0.5952"); + values ("0.3723,0.3527,0.3215,0.2785,0.1965,0.0559,-0.1668",\ +"0.3918,0.3723,0.3449,0.2980,0.2160,0.0754,-0.1473",\ +"0.4152,0.3996,0.3684,0.3254,0.2434,0.1066,-0.1199",\ +"0.4621,0.4465,0.4152,0.3723,0.2863,0.1496,-0.0730",\ +"0.5324,0.5207,0.4895,0.4465,0.3645,0.2199,0.0051",\ +"0.6770,0.6535,0.6301,0.5832,0.5090,0.3605,0.1418",\ +"0.9035,0.8879,0.8566,0.8137,0.7316,0.5871,0.3684"); + } + + fall_constraint("SIG2SRAM_constraint_template") { + index_1("0.0080,0.0288,0.0616,0.1072,0.1920,0.3496,0.5952"); + index_2("0.0080,0.0288,0.0616,0.1072,0.1920,0.3496,0.5952"); + values ("0.3762,0.3566,0.3293,0.2863,0.2043,0.0676,-0.1434",\ +"0.3957,0.3762,0.3488,0.3059,0.2238,0.0871,-0.1199",\ +"0.4230,0.4035,0.3723,0.3332,0.2512,0.1184,-0.0965",\ +"0.4660,0.4465,0.4191,0.3762,0.2941,0.1613,-0.0496",\ +"0.5324,0.5168,0.4973,0.4543,0.3723,0.2316,0.0285",\ +"0.6809,0.6613,0.6340,0.5910,0.5129,0.3645,0.1652",\ +"0.9113,0.8918,0.8605,0.8176,0.7395,0.5988,0.3879"); + } + } + } +pin(A_REN) { + direction : input ; + capacitance : 0.00381144 ; + max_transition : "0.5952" ; + related_power_pin : VDD; + related_ground_pin : VSS; + internal_power() { + when : "A_MEN"; + rise_power("scalar"){ + values (0.0132); + } + fall_power("scalar"){ + values (0.0097); + } + } + internal_power() { + when : "!A_MEN"; + rise_power("scalar"){ + values (0.0030); + } + fall_power("scalar"){ + values (0.0004); + } + } + timing() { + timing_type : setup_rising; + related_pin : "A_CLK"; + when : "A_MEN" + sdf_cond : "A_MEN" + + rise_constraint("SIG2SRAM_constraint_template") { + index_1("0.0080,0.0288,0.0616,0.1072,0.1920,0.3496,0.5952"); + index_2("0.0080,0.0288,0.0616,0.1072,0.1920,0.3496,0.5952"); + values ("-0.0770,-0.0574,-0.0262,0.0168,0.0949,0.2355,0.4582",\ +"-0.0965,-0.0770,-0.0457,-0.0027,0.0754,0.2160,0.4387",\ +"-0.1199,-0.1004,-0.0730,-0.0262,0.0520,0.1887,0.4113",\ +"-0.1590,-0.1434,-0.1160,-0.0730,0.0051,0.1457,0.3645",\ +"-0.2449,-0.2254,-0.1941,-0.1473,-0.0770,0.0676,0.2863",\ +"-0.3816,-0.3699,-0.3387,-0.2801,-0.2215,-0.0770,0.1457",\ +"-0.6121,-0.5926,-0.5613,-0.5145,-0.4363,-0.2996,-0.0730"); + } + + fall_constraint("SIG2SRAM_constraint_template") { + index_1("0.0080,0.0288,0.0616,0.1072,0.1920,0.3496,0.5952"); + index_2("0.0080,0.0288,0.0616,0.1072,0.1920,0.3496,0.5952"); + values ("0.1262,0.1457,0.1691,0.2121,0.2824,0.4191,0.6457",\ +"0.1105,0.1262,0.1496,0.1887,0.2629,0.3996,0.6262",\ +"0.0793,0.0949,0.1223,0.1652,0.2395,0.3684,0.5949",\ +"0.0363,0.0559,0.0793,0.1223,0.2004,0.3410,0.5520",\ +"-0.0457,-0.0262,0.0012,0.0441,0.1301,0.2629,0.4738",\ +"-0.1902,-0.1746,-0.1434,-0.1043,-0.0184,0.1223,0.3332",\ +"-0.4129,-0.3934,-0.3660,-0.3230,-0.2449,-0.1043,0.1105"); + } + } + + + timing() { + timing_type : hold_rising; + related_pin : "A_CLK"; + when : "A_MEN" + sdf_cond : "A_MEN" + + rise_constraint("SIG2SRAM_constraint_template") { + index_1("0.0080,0.0288,0.0616,0.1072,0.1920,0.3496,0.5952"); + index_2("0.0080,0.0288,0.0616,0.1072,0.1920,0.3496,0.5952"); + values ("0.4113,0.3918,0.3645,0.3176,0.2395,0.0988,-0.1238",\ +"0.4309,0.4113,0.3840,0.3371,0.2590,0.1184,-0.1043",\ +"0.4582,0.4387,0.4113,0.3645,0.2824,0.1457,-0.0770",\ +"0.5051,0.4816,0.4543,0.4074,0.3293,0.1887,-0.0340",\ +"0.5715,0.5598,0.5324,0.4895,0.4035,0.2512,0.0441",\ +"0.7043,0.7004,0.6730,0.6262,0.5402,0.3957,0.1809",\ +"0.9387,0.9270,0.8957,0.8527,0.7746,0.6262,0.4074"); + } + + fall_constraint("SIG2SRAM_constraint_template") { + index_1("0.0080,0.0288,0.0616,0.1072,0.1920,0.3496,0.5952"); + index_2("0.0080,0.0288,0.0616,0.1072,0.1920,0.3496,0.5952"); + values ("0.4152,0.3918,0.3645,0.3215,0.2395,0.1027,-0.1082",\ +"0.4309,0.4113,0.3801,0.3410,0.2590,0.1223,-0.0926",\ +"0.4582,0.4387,0.4074,0.3684,0.2863,0.1496,-0.0613",\ +"0.5012,0.4816,0.4504,0.4074,0.3293,0.1887,-0.0145",\ +"0.5715,0.5559,0.5285,0.4816,0.3996,0.2512,0.0598",\ +"0.7160,0.7004,0.6691,0.6262,0.5520,0.4035,0.2004",\ +"0.9387,0.9191,0.8957,0.8488,0.7707,0.6262,0.4113"); + } + } + } +pin(A_MEN) { + direction : input ; + capacitance : 0.00300347 ; + max_transition : "0.5952" ; + related_power_pin : VDD; + related_ground_pin : VSS; + internal_power() { + rise_power("scalar"){ + values (0.0418); + } + fall_power("scalar"){ + values (0.0110); + } + } + timing() { + timing_type : setup_rising; + related_pin : "A_CLK"; + + rise_constraint("SIG2SRAM_constraint_template") { + index_1("0.0080,0.0288,0.0616,0.1072,0.1920,0.3496,0.5952"); + index_2("0.0080,0.0288,0.0616,0.1072,0.1920,0.3496,0.5952"); + values ("0.3215,0.3449,0.3684,0.4113,0.4895,0.6301,0.8527",\ +"0.3059,0.3254,0.3527,0.3957,0.4738,0.6145,0.8371",\ +"0.2746,0.2941,0.3215,0.3645,0.4426,0.5871,0.8059",\ +"0.2316,0.2512,0.2785,0.3215,0.3996,0.5402,0.7629",\ +"0.1496,0.1730,0.1965,0.2395,0.3215,0.4660,0.6848",\ +"0.0090,0.0285,0.0598,0.1027,0.1809,0.3176,0.5402",\ +"-0.2098,-0.1902,-0.1668,-0.1199,-0.0418,0.0988,0.3137"); + } + + fall_constraint("SIG2SRAM_constraint_template") { + index_1("0.0080,0.0288,0.0616,0.1072,0.1920,0.3496,0.5952"); + index_2("0.0080,0.0288,0.0616,0.1072,0.1920,0.3496,0.5952"); + values ("0.4582,0.4738,0.5012,0.5363,0.6145,0.7395,0.9738",\ +"0.4387,0.4543,0.4816,0.5207,0.5910,0.7199,0.9582",\ +"0.4035,0.4230,0.4504,0.4855,0.5637,0.6887,0.9230",\ +"0.3645,0.3840,0.4074,0.4465,0.5285,0.6496,0.8840",\ +"0.2824,0.3020,0.3254,0.3645,0.4465,0.5715,0.7980",\ +"0.1418,0.1613,0.1887,0.2238,0.3020,0.4309,0.6496",\ +"-0.0770,-0.0574,-0.0301,0.0090,0.0910,0.2238,0.4191"); + } + } + + + timing() { + timing_type : hold_rising; + related_pin : "A_CLK"; + + rise_constraint("SIG2SRAM_constraint_template") { + index_1("0.0080,0.0288,0.0616,0.1072,0.1920,0.3496,0.5952"); + index_2("0.0080,0.0288,0.0616,0.1072,0.1920,0.3496,0.5952"); + values ("0.3762,0.3605,0.3293,0.2863,0.2043,0.0637,-0.1629",\ +"0.3996,0.3801,0.3488,0.3020,0.2238,0.0832,-0.1395",\ +"0.4230,0.4074,0.3723,0.3293,0.2473,0.1105,-0.1121",\ +"0.4621,0.4465,0.4152,0.3762,0.2941,0.1535,-0.0691",\ +"0.5441,0.5285,0.4973,0.4465,0.3684,0.2316,0.0090",\ +"0.6848,0.6652,0.6301,0.5910,0.5129,0.3605,0.1496",\ +"0.9074,0.8918,0.8566,0.8215,0.7395,0.5910,0.3723"); + } + + fall_constraint("SIG2SRAM_constraint_template") { + index_1("0.0080,0.0288,0.0616,0.1072,0.1920,0.3496,0.5952"); + index_2("0.0080,0.0288,0.0616,0.1072,0.1920,0.3496,0.5952"); + values ("0.3762,0.3605,0.3332,0.2863,0.2043,0.0715,-0.1395",\ +"0.3996,0.3762,0.3488,0.3059,0.2238,0.0910,-0.1199",\ +"0.4270,0.4035,0.3762,0.3332,0.2512,0.1184,-0.0965",\ +"0.4699,0.4504,0.4191,0.3762,0.2941,0.1613,-0.0496",\ +"0.5441,0.5285,0.4973,0.4543,0.3762,0.2355,0.0324",\ +"0.6770,0.6613,0.6340,0.5949,0.5207,0.3762,0.1652",\ +"0.9074,0.8918,0.8605,0.8176,0.7395,0.6027,0.3918"); + } + } + } +bus(A_BM) { + bus_type : D_7_0; + direction : input ; + capacitance : 0.00272583 ; + max_transition : "0.5952" ; + pin(A_BM[7:0]) { + related_power_pin : VDD; + related_ground_pin : VSS; + internal_power() { + when : "A_MEN"; + rise_power("scalar"){ + values (0.0335); + } + fall_power("scalar"){ + values (0.0287); + } + } + internal_power() { + when : "!A_MEN"; + rise_power("scalar"){ + values (0.0171); + } + fall_power("scalar"){ + values (0.0008); + } + } + } + timing() { + timing_type : setup_rising; + related_pin : "A_CLK"; + when : "(A_WEN & A_MEN)" + sdf_cond : "A_RW_ACCESS" + + rise_constraint("SIG2SRAM_constraint_template") { + index_1("0.0080,0.0288,0.0616,0.1072,0.1920,0.3496,0.5952"); + index_2("0.0080,0.0288,0.0616,0.1072,0.1920,0.3496,0.5952"); + values ("-0.5975,-0.5780,-0.5516,-0.5086,-0.4286,-0.2811,-0.0604",\ +"-0.6054,-0.5859,-0.5595,-0.5166,-0.4365,-0.2890,-0.0683",\ +"-0.6146,-0.5950,-0.5687,-0.5257,-0.4456,-0.2982,-0.0775",\ +"-0.6296,-0.6100,-0.5837,-0.5407,-0.4606,-0.3131,-0.0924",\ +"-0.6519,-0.6324,-0.6060,-0.5631,-0.4830,-0.3355,-0.1148",\ +"-0.6955,-0.6760,-0.6496,-0.6067,-0.5266,-0.3791,-0.1584",\ +"-0.7647,-0.7452,-0.7188,-0.6758,-0.5958,-0.4483,-0.2276"); + } + + fall_constraint("SIG2SRAM_constraint_template") { + index_1("0.0080,0.0288,0.0616,0.1072,0.1920,0.3496,0.5952"); + index_2("0.0080,0.0288,0.0616,0.1072,0.1920,0.3496,0.5952"); + values ("-0.5331,-0.5135,-0.4872,-0.4491,-0.3661,-0.2293,-0.0174",\ +"-0.5410,-0.5214,-0.4951,-0.4570,-0.3740,-0.2373,-0.0254",\ +"-0.5501,-0.5306,-0.5042,-0.4661,-0.3831,-0.2464,-0.0345",\ +"-0.5651,-0.5456,-0.5192,-0.4811,-0.3981,-0.2614,-0.0495",\ +"-0.5875,-0.5680,-0.5416,-0.5035,-0.4205,-0.2838,-0.0719",\ +"-0.6311,-0.6115,-0.5852,-0.5471,-0.4641,-0.3274,-0.1155",\ +"-0.7003,-0.6807,-0.6544,-0.6163,-0.5333,-0.3966,-0.1846"); + } + } + + + timing() { + timing_type : hold_rising; + related_pin : "A_CLK"; + when : "(A_WEN & A_MEN)" + sdf_cond : "A_RW_ACCESS" + + rise_constraint("SIG2SRAM_constraint_template") { + index_1("0.0080,0.0288,0.0616,0.1072,0.1920,0.3496,0.5952"); + index_2("0.0080,0.0288,0.0616,0.1072,0.1920,0.3496,0.5952"); + values ("0.7095,0.6890,0.6636,0.6206,0.5425,0.3960,0.1733",\ +"0.7174,0.6969,0.6715,0.6285,0.5504,0.4039,0.1812",\ +"0.7265,0.7060,0.6806,0.6377,0.5595,0.4130,0.1904",\ +"0.7415,0.7210,0.6956,0.6526,0.5745,0.4280,0.2054",\ +"0.7639,0.7434,0.7180,0.6750,0.5969,0.4504,0.2277",\ +"0.8075,0.7870,0.7616,0.7186,0.6405,0.4940,0.2713",\ +"0.8767,0.8562,0.8308,0.7878,0.7097,0.5632,0.3405"); + } + + fall_constraint("SIG2SRAM_constraint_template") { + index_1("0.0080,0.0288,0.0616,0.1072,0.1920,0.3496,0.5952"); + index_2("0.0080,0.0288,0.0616,0.1072,0.1920,0.3496,0.5952"); + values ("0.6362,0.6186,0.5903,0.5493,0.4692,0.3315,0.1206",\ +"0.6441,0.6266,0.5982,0.5572,0.4772,0.3394,0.1285",\ +"0.6533,0.6357,0.6074,0.5664,0.4863,0.3486,0.1377",\ +"0.6683,0.6507,0.6224,0.5814,0.5013,0.3636,0.1526",\ +"0.6906,0.6731,0.6447,0.6037,0.5236,0.3860,0.1750",\ +"0.7342,0.7167,0.6883,0.6473,0.5673,0.4296,0.2186",\ +"0.8034,0.7858,0.7575,0.7165,0.6364,0.4987,0.2878"); + } + } +} + pin(A_CLK) { + direction : input; + capacitance : 0.00378957; + max_transition : "0.5952"; + clock : "true" ; + pin_func_type : active_rising ; + + timing () { + timing_type : "min_pulse_width"; + related_pin : "A_CLK"; + rise_constraint("CLKTRAN_constraint_template") { + index_1("0.008,0.5952"); + values("0.4,0.4"); + } + } + + related_power_pin : VDD; + related_ground_pin : VSS; + + internal_power() { + when : "!A_MEN & !A_WEN & !A_REN"; + rise_power("scalar"){ + values (0); + } + fall_power("scalar"){ + values (0); + } + } + internal_power() { + when : "!A_MEN & A_WEN & !A_REN"; + rise_power("scalar"){ + values (1.2527); + } + fall_power("scalar"){ + values (0); + } + } + internal_power() { + when : "A_MEN & A_WEN & !A_REN"; + rise_power("scalar"){ + values (10.6488); + } + fall_power("scalar"){ + values (0); + } + } + internal_power() { + when : "A_MEN & A_WEN & A_REN"; + rise_power("scalar"){ + values (11.0607); + } + fall_power("scalar"){ + values (0); + } + } + internal_power() { + when : "A_MEN & !A_WEN & A_REN"; + rise_power("scalar"){ + values (8.3379); + } + fall_power("scalar"){ + values (0); + } + } + internal_power() { + when : "!A_MEN & !A_WEN & A_REN"; + rise_power("scalar"){ + values (0.2701); + } + fall_power("scalar"){ + values (0); + } + } + internal_power() { + when : "!A_MEN & A_WEN & A_REN"; + rise_power("scalar"){ + values (0.4551); + } + fall_power("scalar"){ + values (0); + } + } + internal_power() { + when : "A_MEN & !A_WEN & !A_REN"; + rise_power("scalar"){ + values (0); + } + fall_power("scalar"){ + values (0); + } + } + } + bus(A_DIN) { + bus_type : D_7_0; + direction : input ; + capacitance : 0.00290547 ; + memory_write() { + address : A_ADDR ; + clocked_on : A_CLK; + } + + max_transition : "0.5952" ; + pin(A_DIN[7:0]) { + related_power_pin : VDD; + related_ground_pin : VSS; + internal_power() { + when : "A_MEN"; + rise_power("scalar"){ + values (0.0335); + } + fall_power("scalar"){ + values (0.0287); + } + } + internal_power() { + when : "!A_MEN"; + rise_power("scalar"){ + values (0.0171); + } + fall_power("scalar"){ + values (0.0008); + } + } + } + timing() { + timing_type : setup_rising; + related_pin : "A_CLK"; + when : "(A_WEN & A_MEN)"; + sdf_cond : "A_W_ACCESS"; + + rise_constraint("SIG2SRAM_constraint_template") { + index_1("0.0080,0.0288,0.0616,0.1072,0.1920,0.3496,0.5952"); + index_2("0.0080,0.0288,0.0616,0.1072,0.1920,0.3496,0.5952"); + values ("-0.5975,-0.5780,-0.5516,-0.5086,-0.4286,-0.2811,-0.0604",\ +"-0.6054,-0.5859,-0.5595,-0.5166,-0.4365,-0.2890,-0.0683",\ +"-0.6146,-0.5950,-0.5687,-0.5257,-0.4456,-0.2982,-0.0775",\ +"-0.6296,-0.6100,-0.5837,-0.5407,-0.4606,-0.3131,-0.0924",\ +"-0.6519,-0.6324,-0.6060,-0.5631,-0.4830,-0.3355,-0.1148",\ +"-0.6955,-0.6760,-0.6496,-0.6067,-0.5266,-0.3791,-0.1584",\ +"-0.7647,-0.7452,-0.7188,-0.6758,-0.5958,-0.4483,-0.2276"); + } + + fall_constraint("SIG2SRAM_constraint_template") { + index_1("0.0080,0.0288,0.0616,0.1072,0.1920,0.3496,0.5952"); + index_2("0.0080,0.0288,0.0616,0.1072,0.1920,0.3496,0.5952"); + values ("-0.5331,-0.5135,-0.4872,-0.4491,-0.3661,-0.2293,-0.0174",\ +"-0.5410,-0.5214,-0.4951,-0.4570,-0.3740,-0.2373,-0.0254",\ +"-0.5501,-0.5306,-0.5042,-0.4661,-0.3831,-0.2464,-0.0345",\ +"-0.5651,-0.5456,-0.5192,-0.4811,-0.3981,-0.2614,-0.0495",\ +"-0.5875,-0.5680,-0.5416,-0.5035,-0.4205,-0.2838,-0.0719",\ +"-0.6311,-0.6115,-0.5852,-0.5471,-0.4641,-0.3274,-0.1155",\ +"-0.7003,-0.6807,-0.6544,-0.6163,-0.5333,-0.3966,-0.1846"); + } + } + + timing() { + timing_type : hold_rising; + related_pin : "A_CLK"; + when : "(A_WEN & A_MEN)"; + sdf_cond : "A_W_ACCESS"; + + rise_constraint("SIG2SRAM_constraint_template") { + index_1("0.0080,0.0288,0.0616,0.1072,0.1920,0.3496,0.5952"); + index_2("0.0080,0.0288,0.0616,0.1072,0.1920,0.3496,0.5952"); + values ("0.7095,0.6890,0.6636,0.6206,0.5425,0.3960,0.1733",\ +"0.7174,0.6969,0.6715,0.6285,0.5504,0.4039,0.1812",\ +"0.7265,0.7060,0.6806,0.6377,0.5595,0.4130,0.1904",\ +"0.7415,0.7210,0.6956,0.6526,0.5745,0.4280,0.2054",\ +"0.7639,0.7434,0.7180,0.6750,0.5969,0.4504,0.2277",\ +"0.8075,0.7870,0.7616,0.7186,0.6405,0.4940,0.2713",\ +"0.8767,0.8562,0.8308,0.7878,0.7097,0.5632,0.3405"); + } + + fall_constraint("SIG2SRAM_constraint_template") { + index_1("0.0080,0.0288,0.0616,0.1072,0.1920,0.3496,0.5952"); + index_2("0.0080,0.0288,0.0616,0.1072,0.1920,0.3496,0.5952"); + values ("0.6362,0.6186,0.5903,0.5493,0.4692,0.3315,0.1206",\ +"0.6441,0.6266,0.5982,0.5572,0.4772,0.3394,0.1285",\ +"0.6533,0.6357,0.6074,0.5664,0.4863,0.3486,0.1377",\ +"0.6683,0.6507,0.6224,0.5814,0.5013,0.3636,0.1526",\ +"0.6906,0.6731,0.6447,0.6037,0.5236,0.3860,0.1750",\ +"0.7342,0.7167,0.6883,0.6473,0.5673,0.4296,0.2186",\ +"0.8034,0.7858,0.7575,0.7165,0.6364,0.4987,0.2878"); + } + } + } + + pin(A_BIST_EN) { + direction : input ; + capacitance : 0.00387999 ; + max_transition : "1" ; + related_power_pin : VDD; + related_ground_pin : VSS; + internal_power() { + rise_power("scalar") { + values (0); + } + fall_power("scalar") { + values (0); + } + } + } + +bus(A_BIST_ADDR) { + bus_type : A_7_0; + direction : input ; + capacitance : 0.0077013 ; + pin(A_BIST_ADDR[0]) { + capacitance : 0.00625349 ; + } + pin(A_BIST_ADDR[1]) { + capacitance : 0.00507435 ; + } + pin(A_BIST_ADDR[2]) { + capacitance : 0.00656707 ; + } + pin(A_BIST_ADDR[3]) { + capacitance : 0.0083133 ; + } + pin(A_BIST_ADDR[4]) { + capacitance : 0.00507219 ; + } + pin(A_BIST_ADDR[5]) { + capacitance : 0.00964344 ; + } + pin(A_BIST_ADDR[6]) { + capacitance : 0.0119653 ; + } + max_transition : "0.5952" ; + pin(A_BIST_ADDR[7:0]) { + related_power_pin : VDD; + related_ground_pin : VSS; + internal_power() { + when : "A_BIST_MEN"; + rise_power("scalar"){ + values (0.0182); + } + fall_power("scalar"){ + values (0.0047); + } + } + internal_power() { + when : "!A_BIST_MEN"; + rise_power("scalar"){ + values (0.0159); + } + fall_power("scalar"){ + values (0.0002); + } + } + } + timing() { + timing_type : setup_rising; + related_pin : "A_BIST_CLK"; + when : "((A_BIST_WEN | A_BIST_REN)& A_BIST_MEN)" + sdf_cond : "A_BIST_RW_ACCESS" + + rise_constraint("SIG2SRAM_constraint_template") { + index_1("0.0080,0.0288,0.0616,0.1072,0.1920,0.3496,0.5952"); + index_2("0.0080,0.0288,0.0616,0.1072,0.1920,0.3496,0.5952"); + values ("-0.7371,-0.7176,-0.6863,-0.6434,-0.5652,-0.4168,-0.1980",\ +"-0.7566,-0.7371,-0.7059,-0.6629,-0.5848,-0.4363,-0.2137",\ +"-0.7879,-0.7645,-0.7332,-0.6902,-0.6121,-0.4637,-0.2449",\ +"-0.8309,-0.8074,-0.7762,-0.7332,-0.6551,-0.5066,-0.2879",\ +"-0.9051,-0.8895,-0.8543,-0.8113,-0.7332,-0.5887,-0.3660",\ +"-1.0418,-1.0262,-0.9949,-0.9480,-0.8699,-0.7293,-0.5027",\ +"-1.2684,-1.2449,-1.2176,-1.1707,-1.0965,-0.9480,-0.7293"); + } + + fall_constraint("SIG2SRAM_constraint_template") { + index_1("0.0080,0.0288,0.0616,0.1072,0.1920,0.3496,0.5952"); + index_2("0.0080,0.0288,0.0616,0.1072,0.1920,0.3496,0.5952"); + values ("-0.5926,-0.5730,-0.5418,-0.4988,-0.4246,-0.2879,-0.0730",\ +"-0.6121,-0.5926,-0.5613,-0.5223,-0.4441,-0.3074,-0.0887",\ +"-0.6395,-0.6199,-0.5926,-0.5496,-0.4715,-0.3348,-0.1160",\ +"-0.6863,-0.6668,-0.6355,-0.5965,-0.5184,-0.3777,-0.1590",\ +"-0.7605,-0.7410,-0.7137,-0.6746,-0.5926,-0.4559,-0.2410",\ +"-0.9012,-0.8816,-0.8504,-0.8113,-0.7332,-0.5926,-0.3895",\ +"-1.1238,-1.1043,-1.0769,-1.0379,-0.9559,-0.8191,-0.6004"); + } + } + + + timing() { + timing_type : hold_rising; + related_pin : "A_BIST_CLK"; + when : "((A_BIST_WEN | A_BIST_REN)& A_BIST_MEN)" + sdf_cond : "A_BIST_RW_ACCESS" + + rise_constraint("SIG2SRAM_constraint_template") { + index_1("0.0080,0.0288,0.0616,0.1072,0.1920,0.3496,0.5952"); + index_2("0.0080,0.0288,0.0616,0.1072,0.1920,0.3496,0.5952"); + values ("0.8488,0.8293,0.7980,0.7551,0.6730,0.5285,0.3059",\ +"0.8684,0.8488,0.8176,0.7746,0.6926,0.5480,0.3254",\ +"0.8996,0.8801,0.8449,0.8020,0.7238,0.5754,0.3527",\ +"0.9426,0.9191,0.8918,0.8488,0.7668,0.6223,0.3996",\ +"1.0168,1.0012,0.9699,0.9230,0.8449,0.7004,0.4777",\ +"1.1574,1.1379,1.1105,1.0598,0.9816,0.8371,0.6184",\ +"1.3801,1.3605,1.3254,1.2980,1.2043,1.0637,0.8371"); + } + + fall_constraint("SIG2SRAM_constraint_template") { + index_1("0.0080,0.0288,0.0616,0.1072,0.1920,0.3496,0.5952"); + index_2("0.0080,0.0288,0.0616,0.1072,0.1920,0.3496,0.5952"); + values ("0.6965,0.6770,0.6496,0.6066,0.5246,0.3918,0.1730",\ +"0.7160,0.6965,0.6652,0.6262,0.5441,0.4113,0.1965",\ +"0.7473,0.7277,0.6965,0.6535,0.5754,0.4426,0.2238",\ +"0.7863,0.7707,0.7395,0.7004,0.6223,0.4855,0.2629",\ +"0.8684,0.8449,0.8176,0.7785,0.7004,0.5637,0.3449",\ +"1.0051,0.9855,0.9855,0.9113,0.8332,0.7004,0.4895",\ +"1.2277,1.2082,1.1809,1.1379,1.0598,0.9230,0.7004"); + } + } +} +pin(A_BIST_WEN) { + direction : input ; + capacitance : 0.00313551 ; + max_transition : "0.5952" ; + related_power_pin : VDD; + related_ground_pin : VSS; + internal_power() { + when : "A_BIST_MEN"; + rise_power("scalar"){ + values (0.0127); + } + fall_power("scalar"){ + values (0.0103); + } + } + internal_power() { + when : "!A_BIST_MEN"; + rise_power("scalar"){ + values (0.0040); + } + fall_power("scalar"){ + values (0.0006); + } + } + timing() { + timing_type : setup_rising; + related_pin : "A_BIST_CLK"; + when : "A_BIST_MEN" + sdf_cond : "A_BIST_MEN" + + rise_constraint("SIG2SRAM_constraint_template") { + index_1("0.0080,0.0288,0.0616,0.1072,0.1920,0.3496,0.5952"); + index_2("0.0080,0.0288,0.0616,0.1072,0.1920,0.3496,0.5952"); + values ("0.3137,0.3332,0.3605,0.4035,0.4816,0.6223,0.8488",\ +"0.2980,0.3176,0.3410,0.3840,0.4660,0.6027,0.8293",\ +"0.2629,0.2824,0.3098,0.3527,0.4348,0.5754,0.7980",\ +"0.2199,0.2395,0.2668,0.3098,0.3918,0.5324,0.7590",\ +"0.1418,0.1613,0.1887,0.2316,0.3137,0.4348,0.6730",\ +"0.0012,0.0207,0.0520,0.0910,0.1730,0.3098,0.5285",\ +"-0.2215,-0.2020,-0.1746,-0.1277,-0.0496,0.0910,0.3098"); + } + + fall_constraint("SIG2SRAM_constraint_template") { + index_1("0.0080,0.0288,0.0616,0.1072,0.1920,0.3496,0.5952"); + index_2("0.0080,0.0288,0.0616,0.1072,0.1920,0.3496,0.5952"); + values ("0.4504,0.4699,0.4973,0.5324,0.6027,0.7355,0.9699",\ +"0.4309,0.4504,0.4777,0.5129,0.5910,0.7160,0.9504",\ +"0.3996,0.4191,0.4465,0.4816,0.5520,0.6848,0.9191",\ +"0.3605,0.3762,0.4035,0.4387,0.5168,0.6418,0.8723",\ +"0.2785,0.2980,0.3215,0.3605,0.4348,0.5637,0.7980",\ +"0.1379,0.1574,0.1809,0.2199,0.2980,0.4309,0.6457",\ +"-0.0809,-0.0613,-0.0340,0.0051,0.0832,0.2160,0.4191"); + } + } + + + timing() { + timing_type : hold_rising; + related_pin : "A_BIST_CLK"; + when : "A_BIST_MEN" + sdf_cond : "A_BIST_MEN" + + rise_constraint("SIG2SRAM_constraint_template") { + index_1("0.0080,0.0288,0.0616,0.1072,0.1920,0.3496,0.5952"); + index_2("0.0080,0.0288,0.0616,0.1072,0.1920,0.3496,0.5952"); + values ("0.3723,0.3527,0.3215,0.2785,0.1965,0.0559,-0.1668",\ +"0.3918,0.3723,0.3449,0.2980,0.2160,0.0754,-0.1473",\ +"0.4152,0.3996,0.3684,0.3254,0.2434,0.1066,-0.1199",\ +"0.4621,0.4465,0.4152,0.3723,0.2863,0.1496,-0.0730",\ +"0.5324,0.5207,0.4895,0.4465,0.3645,0.2199,0.0051",\ +"0.6770,0.6535,0.6301,0.5832,0.5090,0.3605,0.1418",\ +"0.9035,0.8879,0.8566,0.8137,0.7316,0.5871,0.3684"); + } + + fall_constraint("SIG2SRAM_constraint_template") { + index_1("0.0080,0.0288,0.0616,0.1072,0.1920,0.3496,0.5952"); + index_2("0.0080,0.0288,0.0616,0.1072,0.1920,0.3496,0.5952"); + values ("0.3762,0.3566,0.3293,0.2863,0.2043,0.0676,-0.1434",\ +"0.3957,0.3762,0.3488,0.3059,0.2238,0.0871,-0.1199",\ +"0.4230,0.4035,0.3723,0.3332,0.2512,0.1184,-0.0965",\ +"0.4660,0.4465,0.4191,0.3762,0.2941,0.1613,-0.0496",\ +"0.5324,0.5168,0.4973,0.4543,0.3723,0.2316,0.0285",\ +"0.6809,0.6613,0.6340,0.5910,0.5129,0.3645,0.1652",\ +"0.9113,0.8918,0.8605,0.8176,0.7395,0.5988,0.3879"); + } + } + } +pin(A_BIST_REN) { + direction : input ; + capacitance : 0.00381144 ; + max_transition : "0.5952" ; + related_power_pin : VDD; + related_ground_pin : VSS; + internal_power() { + when : "A_BIST_MEN"; + rise_power("scalar"){ + values (0.0132); + } + fall_power("scalar"){ + values (0.0097); + } + } + internal_power() { + when : "!A_BIST_MEN"; + rise_power("scalar"){ + values (0.0030); + } + fall_power("scalar"){ + values (0.0004); + } + } + timing() { + timing_type : setup_rising; + related_pin : "A_BIST_CLK"; + when : "A_BIST_MEN" + sdf_cond : "A_BIST_MEN" + + rise_constraint("SIG2SRAM_constraint_template") { + index_1("0.0080,0.0288,0.0616,0.1072,0.1920,0.3496,0.5952"); + index_2("0.0080,0.0288,0.0616,0.1072,0.1920,0.3496,0.5952"); + values ("-0.0770,-0.0574,-0.0262,0.0168,0.0949,0.2355,0.4582",\ +"-0.0965,-0.0770,-0.0457,-0.0027,0.0754,0.2160,0.4387",\ +"-0.1199,-0.1004,-0.0730,-0.0262,0.0520,0.1887,0.4113",\ +"-0.1590,-0.1434,-0.1160,-0.0730,0.0051,0.1457,0.3645",\ +"-0.2449,-0.2254,-0.1941,-0.1473,-0.0770,0.0676,0.2863",\ +"-0.3816,-0.3699,-0.3387,-0.2801,-0.2215,-0.0770,0.1457",\ +"-0.6121,-0.5926,-0.5613,-0.5145,-0.4363,-0.2996,-0.0730"); + } + + fall_constraint("SIG2SRAM_constraint_template") { + index_1("0.0080,0.0288,0.0616,0.1072,0.1920,0.3496,0.5952"); + index_2("0.0080,0.0288,0.0616,0.1072,0.1920,0.3496,0.5952"); + values ("0.1262,0.1457,0.1691,0.2121,0.2824,0.4191,0.6457",\ +"0.1105,0.1262,0.1496,0.1887,0.2629,0.3996,0.6262",\ +"0.0793,0.0949,0.1223,0.1652,0.2395,0.3684,0.5949",\ +"0.0363,0.0559,0.0793,0.1223,0.2004,0.3410,0.5520",\ +"-0.0457,-0.0262,0.0012,0.0441,0.1301,0.2629,0.4738",\ +"-0.1902,-0.1746,-0.1434,-0.1043,-0.0184,0.1223,0.3332",\ +"-0.4129,-0.3934,-0.3660,-0.3230,-0.2449,-0.1043,0.1105"); + } + } + + + timing() { + timing_type : hold_rising; + related_pin : "A_BIST_CLK"; + when : "A_BIST_MEN" + sdf_cond : "A_BIST_MEN" + + rise_constraint("SIG2SRAM_constraint_template") { + index_1("0.0080,0.0288,0.0616,0.1072,0.1920,0.3496,0.5952"); + index_2("0.0080,0.0288,0.0616,0.1072,0.1920,0.3496,0.5952"); + values ("0.4113,0.3918,0.3645,0.3176,0.2395,0.0988,-0.1238",\ +"0.4309,0.4113,0.3840,0.3371,0.2590,0.1184,-0.1043",\ +"0.4582,0.4387,0.4113,0.3645,0.2824,0.1457,-0.0770",\ +"0.5051,0.4816,0.4543,0.4074,0.3293,0.1887,-0.0340",\ +"0.5715,0.5598,0.5324,0.4895,0.4035,0.2512,0.0441",\ +"0.7043,0.7004,0.6730,0.6262,0.5402,0.3957,0.1809",\ +"0.9387,0.9270,0.8957,0.8527,0.7746,0.6262,0.4074"); + } + + fall_constraint("SIG2SRAM_constraint_template") { + index_1("0.0080,0.0288,0.0616,0.1072,0.1920,0.3496,0.5952"); + index_2("0.0080,0.0288,0.0616,0.1072,0.1920,0.3496,0.5952"); + values ("0.4152,0.3918,0.3645,0.3215,0.2395,0.1027,-0.1082",\ +"0.4309,0.4113,0.3801,0.3410,0.2590,0.1223,-0.0926",\ +"0.4582,0.4387,0.4074,0.3684,0.2863,0.1496,-0.0613",\ +"0.5012,0.4816,0.4504,0.4074,0.3293,0.1887,-0.0145",\ +"0.5715,0.5559,0.5285,0.4816,0.3996,0.2512,0.0598",\ +"0.7160,0.7004,0.6691,0.6262,0.5520,0.4035,0.2004",\ +"0.9387,0.9191,0.8957,0.8488,0.7707,0.6262,0.4113"); + } + } + } +pin(A_BIST_MEN) { + direction : input ; + capacitance : 0.00300347 ; + max_transition : "0.5952" ; + related_power_pin : VDD; + related_ground_pin : VSS; + internal_power() { + rise_power("scalar"){ + values (0.0418); + } + fall_power("scalar"){ + values (0.0110); + } + } + timing() { + timing_type : setup_rising; + related_pin : "A_BIST_CLK"; + + rise_constraint("SIG2SRAM_constraint_template") { + index_1("0.0080,0.0288,0.0616,0.1072,0.1920,0.3496,0.5952"); + index_2("0.0080,0.0288,0.0616,0.1072,0.1920,0.3496,0.5952"); + values ("0.3215,0.3449,0.3684,0.4113,0.4895,0.6301,0.8527",\ +"0.3059,0.3254,0.3527,0.3957,0.4738,0.6145,0.8371",\ +"0.2746,0.2941,0.3215,0.3645,0.4426,0.5871,0.8059",\ +"0.2316,0.2512,0.2785,0.3215,0.3996,0.5402,0.7629",\ +"0.1496,0.1730,0.1965,0.2395,0.3215,0.4660,0.6848",\ +"0.0090,0.0285,0.0598,0.1027,0.1809,0.3176,0.5402",\ +"-0.2098,-0.1902,-0.1668,-0.1199,-0.0418,0.0988,0.3137"); + } + + fall_constraint("SIG2SRAM_constraint_template") { + index_1("0.0080,0.0288,0.0616,0.1072,0.1920,0.3496,0.5952"); + index_2("0.0080,0.0288,0.0616,0.1072,0.1920,0.3496,0.5952"); + values ("0.4582,0.4738,0.5012,0.5363,0.6145,0.7395,0.9738",\ +"0.4387,0.4543,0.4816,0.5207,0.5910,0.7199,0.9582",\ +"0.4035,0.4230,0.4504,0.4855,0.5637,0.6887,0.9230",\ +"0.3645,0.3840,0.4074,0.4465,0.5285,0.6496,0.8840",\ +"0.2824,0.3020,0.3254,0.3645,0.4465,0.5715,0.7980",\ +"0.1418,0.1613,0.1887,0.2238,0.3020,0.4309,0.6496",\ +"-0.0770,-0.0574,-0.0301,0.0090,0.0910,0.2238,0.4191"); + } + } + + + timing() { + timing_type : hold_rising; + related_pin : "A_BIST_CLK"; + + rise_constraint("SIG2SRAM_constraint_template") { + index_1("0.0080,0.0288,0.0616,0.1072,0.1920,0.3496,0.5952"); + index_2("0.0080,0.0288,0.0616,0.1072,0.1920,0.3496,0.5952"); + values ("0.3762,0.3605,0.3293,0.2863,0.2043,0.0637,-0.1629",\ +"0.3996,0.3801,0.3488,0.3020,0.2238,0.0832,-0.1395",\ +"0.4230,0.4074,0.3723,0.3293,0.2473,0.1105,-0.1121",\ +"0.4621,0.4465,0.4152,0.3762,0.2941,0.1535,-0.0691",\ +"0.5441,0.5285,0.4973,0.4465,0.3684,0.2316,0.0090",\ +"0.6848,0.6652,0.6301,0.5910,0.5129,0.3605,0.1496",\ +"0.9074,0.8918,0.8566,0.8215,0.7395,0.5910,0.3723"); + } + + fall_constraint("SIG2SRAM_constraint_template") { + index_1("0.0080,0.0288,0.0616,0.1072,0.1920,0.3496,0.5952"); + index_2("0.0080,0.0288,0.0616,0.1072,0.1920,0.3496,0.5952"); + values ("0.3762,0.3605,0.3332,0.2863,0.2043,0.0715,-0.1395",\ +"0.3996,0.3762,0.3488,0.3059,0.2238,0.0910,-0.1199",\ +"0.4270,0.4035,0.3762,0.3332,0.2512,0.1184,-0.0965",\ +"0.4699,0.4504,0.4191,0.3762,0.2941,0.1613,-0.0496",\ +"0.5441,0.5285,0.4973,0.4543,0.3762,0.2355,0.0324",\ +"0.6770,0.6613,0.6340,0.5949,0.5207,0.3762,0.1652",\ +"0.9074,0.8918,0.8605,0.8176,0.7395,0.6027,0.3918"); + } + } + } +bus(A_BIST_BM) { + bus_type : D_7_0; + direction : input ; + capacitance : 0.00223339 ; + max_transition : "0.5952" ; + pin(A_BIST_BM[7:0]) { + related_power_pin : VDD; + related_ground_pin : VSS; + internal_power() { + when : "A_BIST_MEN"; + rise_power("scalar"){ + values (0.0335); + } + fall_power("scalar"){ + values (0.0287); + } + } + internal_power() { + when : "!A_BIST_MEN"; + rise_power("scalar"){ + values (0.0171); + } + fall_power("scalar"){ + values (0.0008); + } + } + } + timing() { + timing_type : setup_rising; + related_pin : "A_BIST_CLK"; + when : "(A_BIST_WEN & A_BIST_MEN)" + sdf_cond : "A_BIST_RW_ACCESS" + + rise_constraint("SIG2SRAM_constraint_template") { + index_1("0.0080,0.0288,0.0616,0.1072,0.1920,0.3496,0.5952"); + index_2("0.0080,0.0288,0.0616,0.1072,0.1920,0.3496,0.5952"); + values ("-0.5975,-0.5780,-0.5516,-0.5086,-0.4286,-0.2811,-0.0604",\ +"-0.6054,-0.5859,-0.5595,-0.5166,-0.4365,-0.2890,-0.0683",\ +"-0.6146,-0.5950,-0.5687,-0.5257,-0.4456,-0.2982,-0.0775",\ +"-0.6296,-0.6100,-0.5837,-0.5407,-0.4606,-0.3131,-0.0924",\ +"-0.6519,-0.6324,-0.6060,-0.5631,-0.4830,-0.3355,-0.1148",\ +"-0.6955,-0.6760,-0.6496,-0.6067,-0.5266,-0.3791,-0.1584",\ +"-0.7647,-0.7452,-0.7188,-0.6758,-0.5958,-0.4483,-0.2276"); + } + + fall_constraint("SIG2SRAM_constraint_template") { + index_1("0.0080,0.0288,0.0616,0.1072,0.1920,0.3496,0.5952"); + index_2("0.0080,0.0288,0.0616,0.1072,0.1920,0.3496,0.5952"); + values ("-0.5331,-0.5135,-0.4872,-0.4491,-0.3661,-0.2293,-0.0174",\ +"-0.5410,-0.5214,-0.4951,-0.4570,-0.3740,-0.2373,-0.0254",\ +"-0.5501,-0.5306,-0.5042,-0.4661,-0.3831,-0.2464,-0.0345",\ +"-0.5651,-0.5456,-0.5192,-0.4811,-0.3981,-0.2614,-0.0495",\ +"-0.5875,-0.5680,-0.5416,-0.5035,-0.4205,-0.2838,-0.0719",\ +"-0.6311,-0.6115,-0.5852,-0.5471,-0.4641,-0.3274,-0.1155",\ +"-0.7003,-0.6807,-0.6544,-0.6163,-0.5333,-0.3966,-0.1846"); + } + } + + + timing() { + timing_type : hold_rising; + related_pin : "A_BIST_CLK"; + when : "(A_BIST_WEN & A_BIST_MEN)" + sdf_cond : "A_BIST_RW_ACCESS" + + rise_constraint("SIG2SRAM_constraint_template") { + index_1("0.0080,0.0288,0.0616,0.1072,0.1920,0.3496,0.5952"); + index_2("0.0080,0.0288,0.0616,0.1072,0.1920,0.3496,0.5952"); + values ("0.7095,0.6890,0.6636,0.6206,0.5425,0.3960,0.1733",\ +"0.7174,0.6969,0.6715,0.6285,0.5504,0.4039,0.1812",\ +"0.7265,0.7060,0.6806,0.6377,0.5595,0.4130,0.1904",\ +"0.7415,0.7210,0.6956,0.6526,0.5745,0.4280,0.2054",\ +"0.7639,0.7434,0.7180,0.6750,0.5969,0.4504,0.2277",\ +"0.8075,0.7870,0.7616,0.7186,0.6405,0.4940,0.2713",\ +"0.8767,0.8562,0.8308,0.7878,0.7097,0.5632,0.3405"); + } + + fall_constraint("SIG2SRAM_constraint_template") { + index_1("0.0080,0.0288,0.0616,0.1072,0.1920,0.3496,0.5952"); + index_2("0.0080,0.0288,0.0616,0.1072,0.1920,0.3496,0.5952"); + values ("0.6362,0.6186,0.5903,0.5493,0.4692,0.3315,0.1206",\ +"0.6441,0.6266,0.5982,0.5572,0.4772,0.3394,0.1285",\ +"0.6533,0.6357,0.6074,0.5664,0.4863,0.3486,0.1377",\ +"0.6683,0.6507,0.6224,0.5814,0.5013,0.3636,0.1526",\ +"0.6906,0.6731,0.6447,0.6037,0.5236,0.3860,0.1750",\ +"0.7342,0.7167,0.6883,0.6473,0.5673,0.4296,0.2186",\ +"0.8034,0.7858,0.7575,0.7165,0.6364,0.4987,0.2878"); + } + } +} + pin(A_BIST_CLK) { + direction : input; + capacitance : 0.00378957; + max_transition : "0.5952"; + clock : "true" ; + pin_func_type : active_rising ; + + timing () { + timing_type : "min_pulse_width"; + related_pin : "A_BIST_CLK"; + rise_constraint("CLKTRAN_constraint_template") { + index_1("0.008,0.5952"); + values("0.4,0.4"); + } + } + + related_power_pin : VDD; + related_ground_pin : VSS; + + internal_power() { + when : "!A_BIST_MEN & !A_BIST_WEN & !A_BIST_REN"; + rise_power("scalar"){ + values (0); + } + fall_power("scalar"){ + values (0); + } + } + internal_power() { + when : "!A_BIST_MEN & A_BIST_WEN & !A_BIST_REN"; + rise_power("scalar"){ + values (1.2527); + } + fall_power("scalar"){ + values (0); + } + } + internal_power() { + when : "A_BIST_MEN & A_BIST_WEN & !A_BIST_REN"; + rise_power("scalar"){ + values (10.6488); + } + fall_power("scalar"){ + values (0); + } + } + internal_power() { + when : "A_BIST_MEN & A_BIST_WEN & A_BIST_REN"; + rise_power("scalar"){ + values (11.0607); + } + fall_power("scalar"){ + values (0); + } + } + internal_power() { + when : "A_BIST_MEN & !A_BIST_WEN & A_BIST_REN"; + rise_power("scalar"){ + values (8.3379); + } + fall_power("scalar"){ + values (0); + } + } + internal_power() { + when : "!A_BIST_MEN & !A_BIST_WEN & A_BIST_REN"; + rise_power("scalar"){ + values (0.2701); + } + fall_power("scalar"){ + values (0); + } + } + internal_power() { + when : "!A_BIST_MEN & A_BIST_WEN & A_BIST_REN"; + rise_power("scalar"){ + values (0.4551); + } + fall_power("scalar"){ + values (0); + } + } + internal_power() { + when : "A_BIST_MEN & !A_BIST_WEN & !A_BIST_REN"; + rise_power("scalar"){ + values (0); + } + fall_power("scalar"){ + values (0); + } + } + } + bus(A_BIST_DIN) { + bus_type : D_7_0; + direction : input ; + capacitance : 0.00223473 ; + memory_write() { + address : A_BIST_ADDR ; + clocked_on : A_BIST_CLK; + } + + max_transition : "0.5952" ; + pin(A_BIST_DIN[7:0]) { + related_power_pin : VDD; + related_ground_pin : VSS; + internal_power() { + when : "A_BIST_MEN"; + rise_power("scalar"){ + values (0.0335); + } + fall_power("scalar"){ + values (0.0287); + } + } + internal_power() { + when : "!A_BIST_MEN"; + rise_power("scalar"){ + values (0.0171); + } + fall_power("scalar"){ + values (0.0008); + } + } + } + timing() { + timing_type : setup_rising; + related_pin : "A_BIST_CLK"; + when : "(A_BIST_WEN & A_BIST_MEN)"; + sdf_cond : "A_BIST_W_ACCESS"; + + rise_constraint("SIG2SRAM_constraint_template") { + index_1("0.0080,0.0288,0.0616,0.1072,0.1920,0.3496,0.5952"); + index_2("0.0080,0.0288,0.0616,0.1072,0.1920,0.3496,0.5952"); + values ("-0.5975,-0.5780,-0.5516,-0.5086,-0.4286,-0.2811,-0.0604",\ +"-0.6054,-0.5859,-0.5595,-0.5166,-0.4365,-0.2890,-0.0683",\ +"-0.6146,-0.5950,-0.5687,-0.5257,-0.4456,-0.2982,-0.0775",\ +"-0.6296,-0.6100,-0.5837,-0.5407,-0.4606,-0.3131,-0.0924",\ +"-0.6519,-0.6324,-0.6060,-0.5631,-0.4830,-0.3355,-0.1148",\ +"-0.6955,-0.6760,-0.6496,-0.6067,-0.5266,-0.3791,-0.1584",\ +"-0.7647,-0.7452,-0.7188,-0.6758,-0.5958,-0.4483,-0.2276"); + } + + fall_constraint("SIG2SRAM_constraint_template") { + index_1("0.0080,0.0288,0.0616,0.1072,0.1920,0.3496,0.5952"); + index_2("0.0080,0.0288,0.0616,0.1072,0.1920,0.3496,0.5952"); + values ("-0.5331,-0.5135,-0.4872,-0.4491,-0.3661,-0.2293,-0.0174",\ +"-0.5410,-0.5214,-0.4951,-0.4570,-0.3740,-0.2373,-0.0254",\ +"-0.5501,-0.5306,-0.5042,-0.4661,-0.3831,-0.2464,-0.0345",\ +"-0.5651,-0.5456,-0.5192,-0.4811,-0.3981,-0.2614,-0.0495",\ +"-0.5875,-0.5680,-0.5416,-0.5035,-0.4205,-0.2838,-0.0719",\ +"-0.6311,-0.6115,-0.5852,-0.5471,-0.4641,-0.3274,-0.1155",\ +"-0.7003,-0.6807,-0.6544,-0.6163,-0.5333,-0.3966,-0.1846"); + } + } + + timing() { + timing_type : hold_rising; + related_pin : "A_BIST_CLK"; + when : "(A_BIST_WEN & A_BIST_MEN)"; + sdf_cond : "A_BIST_W_ACCESS"; + + rise_constraint("SIG2SRAM_constraint_template") { + index_1("0.0080,0.0288,0.0616,0.1072,0.1920,0.3496,0.5952"); + index_2("0.0080,0.0288,0.0616,0.1072,0.1920,0.3496,0.5952"); + values ("0.7095,0.6890,0.6636,0.6206,0.5425,0.3960,0.1733",\ +"0.7174,0.6969,0.6715,0.6285,0.5504,0.4039,0.1812",\ +"0.7265,0.7060,0.6806,0.6377,0.5595,0.4130,0.1904",\ +"0.7415,0.7210,0.6956,0.6526,0.5745,0.4280,0.2054",\ +"0.7639,0.7434,0.7180,0.6750,0.5969,0.4504,0.2277",\ +"0.8075,0.7870,0.7616,0.7186,0.6405,0.4940,0.2713",\ +"0.8767,0.8562,0.8308,0.7878,0.7097,0.5632,0.3405"); + } + + fall_constraint("SIG2SRAM_constraint_template") { + index_1("0.0080,0.0288,0.0616,0.1072,0.1920,0.3496,0.5952"); + index_2("0.0080,0.0288,0.0616,0.1072,0.1920,0.3496,0.5952"); + values ("0.6362,0.6186,0.5903,0.5493,0.4692,0.3315,0.1206",\ +"0.6441,0.6266,0.5982,0.5572,0.4772,0.3394,0.1285",\ +"0.6533,0.6357,0.6074,0.5664,0.4863,0.3486,0.1377",\ +"0.6683,0.6507,0.6224,0.5814,0.5013,0.3636,0.1526",\ +"0.6906,0.6731,0.6447,0.6037,0.5236,0.3860,0.1750",\ +"0.7342,0.7167,0.6883,0.6473,0.5673,0.4296,0.2186",\ +"0.8034,0.7858,0.7575,0.7165,0.6364,0.4987,0.2878"); + } + } + } + +bus(A_DOUT) { + + bus_type : D_7_0; + direction : output ; + capacitance : 0 ; + max_capacitance : 0.064 ; + memory_read() { + address : A_ADDR ; + } + pin(A_DOUT[7:0]) { + related_power_pin : VDD; + related_ground_pin : VSS; + internal_power() { + rise_power("scalar") { + values (0); + } + fall_power("scalar") { + values (0); + } + } + } + timing() { + related_pin : "A_CLK"; + timing_type : rising_edge ; + timing_sense : non_unate ; + + cell_rise(SIG2SRAM_delay_template) { + index_1("0.0080,0.0288,0.0616,0.1072,0.1920,0.3496,0.5952"); + index_2("0.0008,0.0014,0.0051,0.0100,0.0339,0.0640"); + values ("4.9619,4.9646,4.9768,4.9910,5.0436,5.0985",\ +"4.9758,4.9785,4.9907,5.0049,5.0575,5.1124",\ +"4.9857,4.9884,5.0005,5.0147,5.0673,5.1223",\ +"4.9989,5.0017,5.0138,5.0280,5.0806,5.1356",\ +"5.0222,5.0249,5.0371,5.0513,5.1039,5.1588",\ +"5.0670,5.0697,5.0818,5.0960,5.1486,5.2036",\ +"5.1342,5.1369,5.1491,5.1633,5.2159,5.2709"); + } + cell_fall(SIG2SRAM_delay_template) { + index_1("0.0080,0.0288,0.0616,0.1072,0.1920,0.3496,0.5952"); + index_2("0.0008,0.0014,0.0051,0.0100,0.0339,0.0640"); + values ("4.8517,4.8539,4.8636,4.8755,4.9190,4.9628",\ +"4.8656,4.8678,4.8776,4.8894,4.9329,4.9767",\ +"4.8755,4.8776,4.8874,4.8992,4.9428,4.9865",\ +"4.8888,4.8909,4.9007,4.9125,4.9561,4.9998",\ +"4.9120,4.9142,4.9240,4.9358,4.9793,5.0231",\ +"4.9568,4.9589,4.9687,4.9805,5.0241,5.0678",\ +"5.0240,5.0262,5.0360,5.0478,5.0914,5.1351"); + } + + rise_transition(SRAM_load_template) { + index_1("0.0008,0.0014,0.0051,0.0100,0.0339,0.0640"); + values ("0.0560,0.0583,0.0696,0.0816,0.1519,0.2335"); + } + fall_transition(SRAM_load_template) { + index_1("0.0008,0.0014,0.0051,0.0100,0.0339,0.0640"); + values ("0.0428,0.0445,0.0538,0.0658,0.1181,0.1751"); + } + } +} +cell_leakage_power : 163.3235; +} +} diff --git a/flow/platforms/ihp-sg13g2/lib/RM_IHPSG13_1P_256x8_c3_bm_bist_typ_1p20V_25C.lib b/flow/platforms/ihp-sg13g2/lib/RM_IHPSG13_1P_256x8_c3_bm_bist_typ_1p20V_25C.lib new file mode 100644 index 0000000000..a3543626a6 --- /dev/null +++ b/flow/platforms/ihp-sg13g2/lib/RM_IHPSG13_1P_256x8_c3_bm_bist_typ_1p20V_25C.lib @@ -0,0 +1,1513 @@ +/* ------------------------------------------------------*/ +/**/ +/* Copyright 2025 IHP PDK Authors*/ +/**/ +/* Licensed under the Apache License, Version 2.0 (the "License");*/ +/* you may not use this file except in compliance with the License.*/ +/* You may obtain a copy of the License at*/ +/* */ +/* https://www.apache.org/licenses/LICENSE-2.0*/ +/* */ +/* Unless required by applicable law or agreed to in writing, software*/ +/* distributed under the License is distributed on an "AS IS" BASIS,*/ +/* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.*/ +/* See the License for the specific language governing permissions and*/ +/* limitations under the License.*/ +/* */ +/* Generated on Wed Aug 27 16:22:42 2025 */ +/* */ +/* ------------------------------------------------------ */ +library(RM_IHPSG13_1P_256x8_c3_bm_bist_typ_1p20V_25C) { + technology (cmos) ; + delay_model : table_lookup ; + define ("add_pg_pin_to_lib", "library", "boolean"); + add_pg_pin_to_lib : true; + voltage_map ( VDD, 1.20); + voltage_map ( VDDARRAY, 1.20); + voltage_map ( VSS, 0.000000 ); + + date : "Wed Aug 27 16:22:39 2025" ; + comment : "IHP Microelectronics GmbH, 2023" ; + revision : 1.0.0 ; + simulation : true ; + nom_process : 1 ; + nom_temperature : 25 ; + nom_voltage : 1.20 ; + + operating_conditions("typ_1p20V_25C"){ + process : 1 ; + temperature : 25 ; + voltage : 1.20 ; + tree_type : "balanced_tree" ; + } + + default_operating_conditions : typ_1p20V_25C ; + default_max_transition : 1.0 ; + default_fanout_load : 1.0 ; + default_inout_pin_cap : 0.0 ; + default_input_pin_cap : 0.0 ; + default_output_pin_cap : 0.0 ; + default_cell_leakage_power : 0.0 ; + default_leakage_power_density : 0.0 ; + + slew_lower_threshold_pct_rise : 30 ; + slew_upper_threshold_pct_rise : 70 ; + input_threshold_pct_fall : 50 ; + output_threshold_pct_fall : 50 ; + input_threshold_pct_rise : 50 ; + output_threshold_pct_rise : 50 ; + slew_lower_threshold_pct_fall : 30 ; + slew_upper_threshold_pct_fall : 70 ; + slew_derate_from_library : 0.5; + k_volt_cell_leakage_power : 0.0 ; + k_temp_cell_leakage_power : 0.0 ; + k_process_cell_leakage_power : 0.0 ; + k_volt_internal_power : 0.0 ; + k_temp_internal_power : 0.0 ; + k_process_internal_power : 0.0 ; + + capacitive_load_unit (1,pf) ; + voltage_unit : "1V" ; + current_unit : "1uA" ; + time_unit : "1ns" ; + leakage_power_unit : "1nW" ; + pulling_resistance_unit : "1kohm"; + /* + ------------------------------------------------------------------------------------------ + implicit units overview: + cell_area unit : "um" + internal_power unit : "1e-12 * J/toggle = 1 * uW/MHz" + (capacitive_load_unit * voltage_unit^2) per toggle event + ------------------------------------------------------------------------------------------ + */ + library_features(report_delay_calculation); + define_cell_area (pad_drivers,pad_driver_sites) ; + + lu_table_template(CLKTRAN_constraint_template) { + variable_1 : constrained_pin_transition; + index_1 ( "0.010, 0.050, 0.200, 0.400, 1.000" ); + } + lu_table_template(SRAM_load_template) { + variable_1 : total_output_net_capacitance; + index_1 ( "0.0008,0.0014,0.0051,0.0100,0.0339,0.0640" ); + } + lu_table_template(SIG2SRAM_constraint_template) { + variable_1 : related_pin_transition; + variable_2 : constrained_pin_transition; + index_1 ( "0.0056,0.0232,0.0400,0.0728,0.1280,0.2440,0.4760" ); + index_2 ( "0.0056,0.0232,0.0400,0.0728,0.1280,0.2440,0.4760" ); + } + + lu_table_template(SIG2SRAM_delay_template) { + variable_1 : input_net_transition; + variable_2 : total_output_net_capacitance; + index_1 ( "0.0056,0.0232,0.0400,0.0728,0.1280,0.2440,0.4760" ); + index_2 ( "0.0008,0.0014,0.0051,0.0100,0.0339,0.0640" ); + } + + type (D_7_0) { + base_type : array; + data_type : bit; + bit_width : 8; + bit_from : 7; + bit_to : 0; + downto : true; + } + + type (A_7_0) { + base_type : array; + data_type : bit; + bit_width : 8; + bit_from : 7; + bit_to : 0; + downto : true; + } + +cell(RM_IHPSG13_1P_256x8_c3_bm_bist) { +pg_pin (VDD) { + pg_type : primary_power; + voltage_name : VDD; +} +pg_pin (VDDARRAY) { + pg_type : primary_power; + voltage_name : VDDARRAY; +} +pg_pin (VSS) { + pg_type : primary_ground; + voltage_name : VSS; +} + +memory() { + type : ram; + address_width : 8; + word_width : 8; +} + +interface_timing : false; +bus_naming_style : "%s[%d]" ; +area : 17546.88 ; + + pin(A_DLY) { + direction : input ; + capacitance : 0.00401111 ; + max_transition : "1" ; + related_power_pin : VDD; + related_ground_pin : VSS; + internal_power() { + rise_power("scalar") { + values (0); + } + fall_power("scalar") { + values (0); + } + } + } + +bus(A_ADDR) { + bus_type : A_7_0; + direction : input ; + capacitance : 0.00721489 ; + pin(A_ADDR[0]) { + capacitance : 0.00593979 ; + } + pin(A_ADDR[1]) { + capacitance : 0.00483009 ; + } + pin(A_ADDR[2]) { + capacitance : 0.006215 ; + } + pin(A_ADDR[3]) { + capacitance : 0.00766726 ; + } + pin(A_ADDR[4]) { + capacitance : 0.00488951 ; + } + pin(A_ADDR[5]) { + capacitance : 0.0091523 ; + } + pin(A_ADDR[6]) { + capacitance : 0.0109212 ; + } + max_transition : "0.476" ; + pin(A_ADDR[7:0]) { + related_power_pin : VDD; + related_ground_pin : VSS; + internal_power() { + when : "A_MEN"; + rise_power("scalar"){ + values (0.0333); + } + fall_power("scalar"){ + values (0.0214); + } + } + internal_power() { + when : "!A_MEN"; + rise_power("scalar"){ + values (0.0169); + } + fall_power("scalar"){ + values (0.0017); + } + } + } + timing() { + timing_type : setup_rising; + related_pin : "A_CLK"; + when : "((A_WEN | A_REN)& A_MEN)" + sdf_cond : "A_RW_ACCESS" + + rise_constraint("SIG2SRAM_constraint_template") { + index_1("0.0056,0.0232,0.0400,0.0728,0.1280,0.2440,0.4760"); + index_2("0.0056,0.0232,0.0400,0.0728,0.1280,0.2440,0.4760"); + values ("-0.4168,-0.3973,-0.3855,-0.3543,-0.3074,-0.2020,-0.0027",\ +"-0.4324,-0.4129,-0.4012,-0.3699,-0.3191,-0.2176,-0.0184",\ +"-0.4441,-0.4285,-0.4129,-0.3816,-0.3309,-0.2293,-0.0301",\ +"-0.4793,-0.4598,-0.4441,-0.4129,-0.3660,-0.2645,-0.0652",\ +"-0.5223,-0.5066,-0.4910,-0.4598,-0.4129,-0.3074,-0.1121",\ +"-0.6199,-0.6082,-0.5926,-0.5613,-0.5145,-0.4129,-0.2137",\ +"-0.8191,-0.8074,-0.7840,-0.7566,-0.7098,-0.6082,-0.4051"); + } + + fall_constraint("SIG2SRAM_constraint_template") { + index_1("0.0056,0.0232,0.0400,0.0728,0.1280,0.2440,0.4760"); + index_2("0.0056,0.0232,0.0400,0.0728,0.1280,0.2440,0.4760"); + values ("-0.3309,-0.3113,-0.2996,-0.2684,-0.2176,-0.1238,0.0637",\ +"-0.3465,-0.3309,-0.3152,-0.2840,-0.2332,-0.1395,0.0480",\ +"-0.3582,-0.3426,-0.3270,-0.2996,-0.2488,-0.1512,0.0324",\ +"-0.3895,-0.3738,-0.3582,-0.3309,-0.2801,-0.1863,0.0051",\ +"-0.4363,-0.4207,-0.4051,-0.3777,-0.3230,-0.2293,-0.0379",\ +"-0.5379,-0.5223,-0.5066,-0.4793,-0.4285,-0.3309,-0.1434",\ +"-0.7332,-0.7176,-0.7020,-0.6746,-0.6238,-0.5262,-0.3387"); + } + } + + + timing() { + timing_type : hold_rising; + related_pin : "A_CLK"; + when : "((A_WEN | A_REN)& A_MEN)" + sdf_cond : "A_RW_ACCESS" + + rise_constraint("SIG2SRAM_constraint_template") { + index_1("0.0056,0.0232,0.0400,0.0728,0.1280,0.2440,0.4760"); + index_2("0.0056,0.0232,0.0400,0.0728,0.1280,0.2440,0.4760"); + values ("0.5246,0.5051,0.4895,0.4582,0.4113,0.3059,0.1066",\ +"0.5402,0.5207,0.5051,0.4777,0.4270,0.3215,0.1223",\ +"0.5520,0.5324,0.5168,0.4895,0.4387,0.3371,0.1340",\ +"0.5832,0.5676,0.5520,0.5207,0.4738,0.3684,0.1691",\ +"0.6301,0.6105,0.5949,0.5676,0.5168,0.4113,0.2160",\ +"0.7316,0.7121,0.7004,0.6691,0.6223,0.5168,0.3176",\ +"0.9270,0.9230,0.8957,0.8645,0.8137,0.7121,0.5168"); + } + + fall_constraint("SIG2SRAM_constraint_template") { + index_1("0.0056,0.0232,0.0400,0.0728,0.1280,0.2440,0.4760"); + index_2("0.0056,0.0232,0.0400,0.0728,0.1280,0.2440,0.4760"); + values ("0.4309,0.4152,0.4035,0.3684,0.3215,0.2277,0.0363",\ +"0.4465,0.4309,0.4152,0.3879,0.3371,0.2395,0.0559",\ +"0.4582,0.4426,0.4309,0.3996,0.3488,0.2551,0.0715",\ +"0.4934,0.4777,0.4621,0.4348,0.3840,0.2863,0.0988",\ +"0.5363,0.5207,0.5051,0.4777,0.4270,0.3332,0.1418",\ +"0.6379,0.6262,0.6105,0.5793,0.5324,0.4348,0.2434",\ +"0.8332,0.8215,0.8059,0.7707,0.7238,0.6301,0.4387"); + } + } +} +pin(A_WEN) { + direction : input ; + capacitance : 0.00324098 ; + max_transition : "0.476" ; + related_power_pin : VDD; + related_ground_pin : VSS; + internal_power() { + when : "A_MEN"; + rise_power("scalar"){ + values (0.0386); + } + fall_power("scalar"){ + values (0.0676); + } + } + internal_power() { + when : "!A_MEN"; + rise_power("scalar"){ + values (0.0032); + } + fall_power("scalar"){ + values (0.0048); + } + } + timing() { + timing_type : setup_rising; + related_pin : "A_CLK"; + when : "A_MEN" + sdf_cond : "A_MEN" + + rise_constraint("SIG2SRAM_constraint_template") { + index_1("0.0056,0.0232,0.0400,0.0728,0.1280,0.2440,0.4760"); + index_2("0.0056,0.0232,0.0400,0.0728,0.1280,0.2440,0.4760"); + values ("0.2043,0.2199,0.2316,0.2629,0.3059,0.4113,0.6066",\ +"0.1887,0.2043,0.2160,0.2473,0.2941,0.3957,0.5949",\ +"0.1691,0.1848,0.2004,0.2316,0.2785,0.3801,0.5754",\ +"0.1379,0.1574,0.1691,0.2004,0.2473,0.3527,0.5480",\ +"0.0910,0.1066,0.1223,0.1535,0.2004,0.2980,0.4973",\ +"-0.0105,0.0051,0.0207,0.0520,0.0949,0.2004,0.3957",\ +"-0.2059,-0.1902,-0.1746,-0.1473,-0.1004,0.0051,0.2004"); + } + + fall_constraint("SIG2SRAM_constraint_template") { + index_1("0.0056,0.0232,0.0400,0.0728,0.1280,0.2440,0.4760"); + index_2("0.0056,0.0232,0.0400,0.0728,0.1280,0.2440,0.4760"); + values ("0.2941,0.3098,0.3215,0.3488,0.4035,0.4973,0.6887",\ +"0.2785,0.2941,0.3059,0.3332,0.3840,0.4816,0.6691",\ +"0.2629,0.2785,0.2902,0.3176,0.3684,0.4660,0.6535",\ +"0.2316,0.2473,0.2590,0.2863,0.3410,0.4348,0.6262",\ +"0.1848,0.2004,0.2121,0.2395,0.2902,0.3879,0.5754",\ +"0.0832,0.0988,0.1105,0.1379,0.1809,0.2746,0.4699",\ +"-0.1121,-0.0965,-0.0848,-0.0535,-0.0066,0.0910,0.2824"); + } + } + + + timing() { + timing_type : hold_rising; + related_pin : "A_CLK"; + when : "A_MEN" + sdf_cond : "A_MEN" + + rise_constraint("SIG2SRAM_constraint_template") { + index_1("0.0056,0.0232,0.0400,0.0728,0.1280,0.2440,0.4760"); + index_2("0.0056,0.0232,0.0400,0.0728,0.1280,0.2440,0.4760"); + values ("0.2473,0.2316,0.2160,0.1887,0.1379,0.0363,-0.1629",\ +"0.2629,0.2473,0.2316,0.2043,0.1535,0.0520,-0.1473",\ +"0.2785,0.2590,0.2434,0.2160,0.1652,0.0676,-0.1355",\ +"0.3098,0.2941,0.2785,0.2473,0.1965,0.0910,-0.1043",\ +"0.3527,0.3371,0.3215,0.2941,0.2434,0.1418,-0.0574",\ +"0.4582,0.4426,0.4270,0.3957,0.3488,0.2434,0.0480",\ +"0.6535,0.6379,0.6184,0.5910,0.5402,0.4426,0.2434"); + } + + fall_constraint("SIG2SRAM_constraint_template") { + index_1("0.0056,0.0232,0.0400,0.0728,0.1280,0.2440,0.4760"); + index_2("0.0056,0.0232,0.0400,0.0728,0.1280,0.2440,0.4760"); + values ("0.2395,0.2238,0.2121,0.1809,0.1301,0.0324,-0.1551",\ +"0.2551,0.2395,0.2277,0.1965,0.1457,0.0480,-0.1395",\ +"0.2668,0.2551,0.2395,0.2082,0.1574,0.0637,-0.1277",\ +"0.3020,0.2863,0.2707,0.2395,0.1887,0.0910,-0.0965",\ +"0.3449,0.3293,0.3176,0.2863,0.2355,0.1379,-0.0496",\ +"0.4504,0.4348,0.4191,0.3879,0.3371,0.2395,0.0559",\ +"0.6457,0.6301,0.6145,0.5871,0.5324,0.4309,0.2512"); + } + } + } +pin(A_REN) { + direction : input ; + capacitance : 0.00381634 ; + max_transition : "0.476" ; + related_power_pin : VDD; + related_ground_pin : VSS; + internal_power() { + when : "A_MEN"; + rise_power("scalar"){ + values (0.0055); + } + fall_power("scalar"){ + values (0.0031); + } + } + internal_power() { + when : "!A_MEN"; + rise_power("scalar"){ + values (0.0052); + } + fall_power("scalar"){ + values (0.0034); + } + } + timing() { + timing_type : setup_rising; + related_pin : "A_CLK"; + when : "A_MEN" + sdf_cond : "A_MEN" + + rise_constraint("SIG2SRAM_constraint_template") { + index_1("0.0056,0.0232,0.0400,0.0728,0.1280,0.2440,0.4760"); + index_2("0.0056,0.0232,0.0400,0.0728,0.1280,0.2440,0.4760"); + values ("-0.0301,-0.0145,0.0012,0.0324,0.0793,0.1809,0.3762",\ +"-0.0457,-0.0301,-0.0145,0.0168,0.0637,0.1613,0.3605",\ +"-0.0574,-0.0418,-0.0262,0.0051,0.0520,0.1496,0.3449",\ +"-0.0926,-0.0730,-0.0574,-0.0262,0.0207,0.1184,0.3137",\ +"-0.1395,-0.1238,-0.1082,-0.0770,-0.0301,0.0715,0.2707",\ +"-0.2410,-0.2254,-0.2098,-0.1746,-0.1355,-0.0340,0.1652",\ +"-0.4402,-0.4207,-0.4051,-0.3738,-0.3270,-0.2293,-0.0340"); + } + + fall_constraint("SIG2SRAM_constraint_template") { + index_1("0.0056,0.0232,0.0400,0.0728,0.1280,0.2440,0.4760"); + index_2("0.0056,0.0232,0.0400,0.0728,0.1280,0.2440,0.4760"); + values ("0.0988,0.1145,0.1262,0.1535,0.2043,0.3020,0.4855",\ +"0.0832,0.0988,0.1105,0.1418,0.1848,0.2824,0.4738",\ +"0.0676,0.0832,0.0949,0.1262,0.1730,0.2668,0.4621",\ +"0.0402,0.0559,0.0676,0.0988,0.1457,0.2434,0.4191",\ +"-0.0105,0.0012,0.0168,0.0480,0.0988,0.1965,0.3840",\ +"-0.1160,-0.0965,-0.0848,-0.0535,-0.0066,0.0988,0.2824",\ +"-0.3113,-0.2957,-0.2801,-0.2527,-0.2059,-0.1043,0.0832"); + } + } + + + timing() { + timing_type : hold_rising; + related_pin : "A_CLK"; + when : "A_MEN" + sdf_cond : "A_MEN" + + rise_constraint("SIG2SRAM_constraint_template") { + index_1("0.0056,0.0232,0.0400,0.0728,0.1280,0.2440,0.4760"); + index_2("0.0056,0.0232,0.0400,0.0728,0.1280,0.2440,0.4760"); + values ("0.2707,0.2551,0.2395,0.2121,0.1613,0.0598,-0.1395",\ +"0.2863,0.2707,0.2551,0.2238,0.1730,0.0715,-0.1238",\ +"0.2980,0.2824,0.2668,0.2395,0.1887,0.0871,-0.1121",\ +"0.3332,0.3176,0.3020,0.2707,0.2199,0.1184,-0.0809",\ +"0.3762,0.3605,0.3449,0.3176,0.2668,0.1613,-0.0340",\ +"0.4816,0.4621,0.4504,0.4191,0.3723,0.2629,0.0715",\ +"0.6770,0.6613,0.6418,0.6184,0.5637,0.4699,0.2629"); + } + + fall_constraint("SIG2SRAM_constraint_template") { + index_1("0.0056,0.0232,0.0400,0.0728,0.1280,0.2440,0.4760"); + index_2("0.0056,0.0232,0.0400,0.0728,0.1280,0.2440,0.4760"); + values ("0.2590,0.2434,0.2316,0.2004,0.1457,0.0520,-0.1355",\ +"0.2746,0.2590,0.2434,0.2160,0.1613,0.0676,-0.1199",\ +"0.2863,0.2707,0.2590,0.2277,0.1730,0.0832,-0.1082",\ +"0.3215,0.3059,0.2902,0.2590,0.2082,0.1105,-0.0770",\ +"0.3645,0.3488,0.3332,0.3059,0.2551,0.1535,-0.0340",\ +"0.4699,0.4543,0.4387,0.4074,0.3605,0.2551,0.0715",\ +"0.6652,0.6496,0.6340,0.6027,0.5520,0.4621,0.2707"); + } + } + } +pin(A_MEN) { + direction : input ; + capacitance : 0.00309605 ; + max_transition : "0.476" ; + related_power_pin : VDD; + related_ground_pin : VSS; + internal_power() { + rise_power("scalar"){ + values (0.0228); + } + fall_power("scalar"){ + values (0.0303); + } + } + timing() { + timing_type : setup_rising; + related_pin : "A_CLK"; + + rise_constraint("SIG2SRAM_constraint_template") { + index_1("0.0056,0.0232,0.0400,0.0728,0.1280,0.2440,0.4760"); + index_2("0.0056,0.0232,0.0400,0.0728,0.1280,0.2440,0.4760"); + values ("0.2043,0.2199,0.2316,0.2668,0.3098,0.4152,0.6066",\ +"0.1887,0.2043,0.2199,0.2512,0.2941,0.3996,0.5949",\ +"0.1730,0.1887,0.2043,0.2355,0.2824,0.3840,0.5793",\ +"0.1418,0.1574,0.1730,0.2043,0.2512,0.3566,0.5480",\ +"0.0949,0.1105,0.1262,0.1574,0.2043,0.3020,0.5051",\ +"-0.0066,0.0090,0.0246,0.0520,0.0988,0.2043,0.3996",\ +"-0.2020,-0.1863,-0.1746,-0.1434,-0.0965,0.0090,0.2082"); + } + + fall_constraint("SIG2SRAM_constraint_template") { + index_1("0.0056,0.0232,0.0400,0.0728,0.1280,0.2440,0.4760"); + index_2("0.0056,0.0232,0.0400,0.0728,0.1280,0.2440,0.4760"); + values ("0.2980,0.3137,0.3254,0.3527,0.4035,0.5012,0.6887",\ +"0.2824,0.2980,0.3098,0.3371,0.3879,0.4855,0.6730",\ +"0.2668,0.2824,0.2941,0.3215,0.3723,0.4699,0.6574",\ +"0.2355,0.2473,0.2629,0.2902,0.3410,0.4387,0.6262",\ +"0.1887,0.2004,0.2160,0.2395,0.2941,0.3918,0.5793",\ +"0.0871,0.1027,0.1145,0.1418,0.1848,0.2746,0.4816",\ +"-0.1082,-0.0965,-0.0809,-0.0496,-0.0027,0.0949,0.2863"); + } + } + + + timing() { + timing_type : hold_rising; + related_pin : "A_CLK"; + + rise_constraint("SIG2SRAM_constraint_template") { + index_1("0.0056,0.0232,0.0400,0.0728,0.1280,0.2440,0.4760"); + index_2("0.0056,0.0232,0.0400,0.0728,0.1280,0.2440,0.4760"); + values ("0.2512,0.2355,0.2199,0.1926,0.1418,0.0402,-0.1590",\ +"0.2668,0.2512,0.2355,0.2082,0.1574,0.0559,-0.1434",\ +"0.2824,0.2629,0.2512,0.2199,0.1691,0.0715,-0.1316",\ +"0.3137,0.2980,0.2824,0.2512,0.2004,0.0988,-0.0965",\ +"0.3566,0.3410,0.3254,0.2980,0.2473,0.1418,-0.0535",\ +"0.4621,0.4426,0.4309,0.3996,0.3527,0.2473,0.0520",\ +"0.6574,0.6418,0.6262,0.5949,0.5441,0.4465,0.2473"); + } + + fall_constraint("SIG2SRAM_constraint_template") { + index_1("0.0056,0.0232,0.0400,0.0728,0.1280,0.2440,0.4760"); + index_2("0.0056,0.0232,0.0400,0.0728,0.1280,0.2440,0.4760"); + values ("0.2395,0.2238,0.2121,0.1809,0.1301,0.0324,-0.1551",\ +"0.2551,0.2434,0.2277,0.1965,0.1457,0.0480,-0.1395",\ +"0.2707,0.2551,0.2395,0.2082,0.1574,0.0637,-0.1277",\ +"0.3020,0.2863,0.2707,0.2434,0.1926,0.0910,-0.0965",\ +"0.3449,0.3332,0.3176,0.2863,0.2355,0.1379,-0.0496",\ +"0.4504,0.4348,0.4230,0.3918,0.3410,0.2434,0.0559",\ +"0.6457,0.6301,0.6145,0.5910,0.5324,0.4387,0.2512"); + } + } + } +bus(A_BM) { + bus_type : D_7_0; + direction : input ; + capacitance : 0.00293842 ; + max_transition : "0.476" ; + pin(A_BM[7:0]) { + related_power_pin : VDD; + related_ground_pin : VSS; + internal_power() { + when : "A_MEN"; + rise_power("scalar"){ + values (0.0223); + } + fall_power("scalar"){ + values (0.0190); + } + } + internal_power() { + when : "!A_MEN"; + rise_power("scalar"){ + values (0.0256); + } + fall_power("scalar"){ + values (0.0189); + } + } + } + timing() { + timing_type : setup_rising; + related_pin : "A_CLK"; + when : "(A_WEN & A_MEN)" + sdf_cond : "A_RW_ACCESS" + + rise_constraint("SIG2SRAM_constraint_template") { + index_1("0.0056,0.0232,0.0400,0.0728,0.1280,0.2440,0.4760"); + index_2("0.0056,0.0232,0.0400,0.0728,0.1280,0.2440,0.4760"); + values ("-0.3245,-0.3089,-0.2952,-0.2630,-0.2161,-0.1116,0.0798",\ +"-0.3295,-0.3139,-0.3002,-0.2680,-0.2211,-0.1166,0.0748",\ +"-0.3340,-0.3184,-0.3047,-0.2725,-0.2256,-0.1211,0.0703",\ +"-0.3431,-0.3275,-0.3138,-0.2816,-0.2347,-0.1302,0.0612",\ +"-0.3503,-0.3347,-0.3210,-0.2888,-0.2419,-0.1374,0.0540",\ +"-0.3800,-0.3643,-0.3507,-0.3185,-0.2716,-0.1671,0.0243",\ +"-0.4380,-0.4224,-0.4087,-0.3765,-0.3296,-0.2251,-0.0337"); + } + + fall_constraint("SIG2SRAM_constraint_template") { + index_1("0.0056,0.0232,0.0400,0.0728,0.1280,0.2440,0.4760"); + index_2("0.0056,0.0232,0.0400,0.0728,0.1280,0.2440,0.4760"); + values ("-0.2864,-0.2718,-0.2581,-0.2298,-0.1790,-0.0813,0.1013",\ +"-0.2914,-0.2768,-0.2631,-0.2348,-0.1840,-0.0863,0.0963",\ +"-0.2959,-0.2812,-0.2676,-0.2393,-0.1885,-0.0908,0.0918",\ +"-0.3050,-0.2904,-0.2767,-0.2484,-0.1976,-0.0999,0.0827",\ +"-0.3122,-0.2976,-0.2839,-0.2556,-0.2048,-0.1071,0.0755",\ +"-0.3419,-0.3272,-0.3136,-0.2852,-0.2345,-0.1368,0.0458",\ +"-0.3999,-0.3853,-0.3716,-0.3433,-0.2925,-0.1949,-0.0123"); + } + } + + + timing() { + timing_type : hold_rising; + related_pin : "A_CLK"; + when : "(A_WEN & A_MEN)" + sdf_cond : "A_RW_ACCESS" + + rise_constraint("SIG2SRAM_constraint_template") { + index_1("0.0056,0.0232,0.0400,0.0728,0.1280,0.2440,0.4760"); + index_2("0.0056,0.0232,0.0400,0.0728,0.1280,0.2440,0.4760"); + values ("0.4334,0.4168,0.4042,0.3719,0.3241,0.2206,0.0282",\ +"0.4385,0.4219,0.4092,0.3769,0.3291,0.2256,0.0332",\ +"0.4429,0.4263,0.4136,0.3814,0.3336,0.2300,0.0377",\ +"0.4521,0.4355,0.4228,0.3905,0.3427,0.2392,0.0468",\ +"0.4592,0.4426,0.4300,0.3977,0.3499,0.2464,0.0540",\ +"0.4889,0.4723,0.4596,0.4274,0.3795,0.2760,0.0836",\ +"0.5470,0.5304,0.5177,0.4855,0.4376,0.3341,0.1417"); + } + + fall_constraint("SIG2SRAM_constraint_template") { + index_1("0.0056,0.0232,0.0400,0.0728,0.1280,0.2440,0.4760"); + index_2("0.0056,0.0232,0.0400,0.0728,0.1280,0.2440,0.4760"); + values ("0.3876,0.3729,0.3592,0.3309,0.2811,0.1883,0.0038",\ +"0.3926,0.3779,0.3642,0.3359,0.2861,0.1933,0.0088",\ +"0.3970,0.3824,0.3687,0.3404,0.2906,0.1978,0.0132",\ +"0.4062,0.3915,0.3778,0.3495,0.2997,0.2069,0.0224",\ +"0.4134,0.3987,0.3850,0.3567,0.3069,0.2141,0.0296",\ +"0.4430,0.4284,0.4147,0.3864,0.3366,0.2438,0.0592",\ +"0.5011,0.4864,0.4728,0.4444,0.3946,0.3019,0.1173"); + } + } +} + pin(A_CLK) { + direction : input; + capacitance : 0.00380014; + max_transition : "0.476"; + clock : "true" ; + pin_func_type : active_rising ; + + timing () { + timing_type : "min_pulse_width"; + related_pin : "A_CLK"; + rise_constraint("CLKTRAN_constraint_template") { + index_1("0.0056,0.476"); + values("0.21,0.21"); + } + } + + related_power_pin : VDD; + related_ground_pin : VSS; + + internal_power() { + when : "!A_MEN & !A_WEN & !A_REN"; + rise_power("scalar"){ + values (0); + } + fall_power("scalar"){ + values (0); + } + } + internal_power() { + when : "!A_MEN & A_WEN & !A_REN"; + rise_power("scalar"){ + values (0.9849); + } + fall_power("scalar"){ + values (0); + } + } + internal_power() { + when : "A_MEN & A_WEN & !A_REN"; + rise_power("scalar"){ + values (13.5065); + } + fall_power("scalar"){ + values (0); + } + } + internal_power() { + when : "A_MEN & A_WEN & A_REN"; + rise_power("scalar"){ + values (13.2907); + } + fall_power("scalar"){ + values (0); + } + } + internal_power() { + when : "A_MEN & !A_WEN & A_REN"; + rise_power("scalar"){ + values (10.2059); + } + fall_power("scalar"){ + values (0); + } + } + internal_power() { + when : "!A_MEN & !A_WEN & A_REN"; + rise_power("scalar"){ + values (0.2958); + } + fall_power("scalar"){ + values (0); + } + } + internal_power() { + when : "!A_MEN & A_WEN & A_REN"; + rise_power("scalar"){ + values (0.5186); + } + fall_power("scalar"){ + values (0); + } + } + internal_power() { + when : "A_MEN & !A_WEN & !A_REN"; + rise_power("scalar"){ + values (0); + } + fall_power("scalar"){ + values (0); + } + } + } + bus(A_DIN) { + bus_type : D_7_0; + direction : input ; + capacitance : 0.0030602 ; + memory_write() { + address : A_ADDR ; + clocked_on : A_CLK; + } + + max_transition : "0.476" ; + pin(A_DIN[7:0]) { + related_power_pin : VDD; + related_ground_pin : VSS; + internal_power() { + when : "A_MEN"; + rise_power("scalar"){ + values (0.0223); + } + fall_power("scalar"){ + values (0.0190); + } + } + internal_power() { + when : "!A_MEN"; + rise_power("scalar"){ + values (0.0256); + } + fall_power("scalar"){ + values (0.0189); + } + } + } + timing() { + timing_type : setup_rising; + related_pin : "A_CLK"; + when : "(A_WEN & A_MEN)"; + sdf_cond : "A_W_ACCESS"; + + rise_constraint("SIG2SRAM_constraint_template") { + index_1("0.0056,0.0232,0.0400,0.0728,0.1280,0.2440,0.4760"); + index_2("0.0056,0.0232,0.0400,0.0728,0.1280,0.2440,0.4760"); + values ("-0.3245,-0.3089,-0.2952,-0.2630,-0.2161,-0.1116,0.0798",\ +"-0.3295,-0.3139,-0.3002,-0.2680,-0.2211,-0.1166,0.0748",\ +"-0.3340,-0.3184,-0.3047,-0.2725,-0.2256,-0.1211,0.0703",\ +"-0.3431,-0.3275,-0.3138,-0.2816,-0.2347,-0.1302,0.0612",\ +"-0.3503,-0.3347,-0.3210,-0.2888,-0.2419,-0.1374,0.0540",\ +"-0.3800,-0.3643,-0.3507,-0.3185,-0.2716,-0.1671,0.0243",\ +"-0.4380,-0.4224,-0.4087,-0.3765,-0.3296,-0.2251,-0.0337"); + } + + fall_constraint("SIG2SRAM_constraint_template") { + index_1("0.0056,0.0232,0.0400,0.0728,0.1280,0.2440,0.4760"); + index_2("0.0056,0.0232,0.0400,0.0728,0.1280,0.2440,0.4760"); + values ("-0.2864,-0.2718,-0.2581,-0.2298,-0.1790,-0.0813,0.1013",\ +"-0.2914,-0.2768,-0.2631,-0.2348,-0.1840,-0.0863,0.0963",\ +"-0.2959,-0.2812,-0.2676,-0.2393,-0.1885,-0.0908,0.0918",\ +"-0.3050,-0.2904,-0.2767,-0.2484,-0.1976,-0.0999,0.0827",\ +"-0.3122,-0.2976,-0.2839,-0.2556,-0.2048,-0.1071,0.0755",\ +"-0.3419,-0.3272,-0.3136,-0.2852,-0.2345,-0.1368,0.0458",\ +"-0.3999,-0.3853,-0.3716,-0.3433,-0.2925,-0.1949,-0.0123"); + } + } + + timing() { + timing_type : hold_rising; + related_pin : "A_CLK"; + when : "(A_WEN & A_MEN)"; + sdf_cond : "A_W_ACCESS"; + + rise_constraint("SIG2SRAM_constraint_template") { + index_1("0.0056,0.0232,0.0400,0.0728,0.1280,0.2440,0.4760"); + index_2("0.0056,0.0232,0.0400,0.0728,0.1280,0.2440,0.4760"); + values ("0.4334,0.4168,0.4042,0.3719,0.3241,0.2206,0.0282",\ +"0.4385,0.4219,0.4092,0.3769,0.3291,0.2256,0.0332",\ +"0.4429,0.4263,0.4136,0.3814,0.3336,0.2300,0.0377",\ +"0.4521,0.4355,0.4228,0.3905,0.3427,0.2392,0.0468",\ +"0.4592,0.4426,0.4300,0.3977,0.3499,0.2464,0.0540",\ +"0.4889,0.4723,0.4596,0.4274,0.3795,0.2760,0.0836",\ +"0.5470,0.5304,0.5177,0.4855,0.4376,0.3341,0.1417"); + } + + fall_constraint("SIG2SRAM_constraint_template") { + index_1("0.0056,0.0232,0.0400,0.0728,0.1280,0.2440,0.4760"); + index_2("0.0056,0.0232,0.0400,0.0728,0.1280,0.2440,0.4760"); + values ("0.3876,0.3729,0.3592,0.3309,0.2811,0.1883,0.0038",\ +"0.3926,0.3779,0.3642,0.3359,0.2861,0.1933,0.0088",\ +"0.3970,0.3824,0.3687,0.3404,0.2906,0.1978,0.0132",\ +"0.4062,0.3915,0.3778,0.3495,0.2997,0.2069,0.0224",\ +"0.4134,0.3987,0.3850,0.3567,0.3069,0.2141,0.0296",\ +"0.4430,0.4284,0.4147,0.3864,0.3366,0.2438,0.0592",\ +"0.5011,0.4864,0.4728,0.4444,0.3946,0.3019,0.1173"); + } + } + } + + pin(A_BIST_EN) { + direction : input ; + capacitance : 0.00401111 ; + max_transition : "1" ; + related_power_pin : VDD; + related_ground_pin : VSS; + internal_power() { + rise_power("scalar") { + values (0); + } + fall_power("scalar") { + values (0); + } + } + } + +bus(A_BIST_ADDR) { + bus_type : A_7_0; + direction : input ; + capacitance : 0.00721489 ; + pin(A_BIST_ADDR[0]) { + capacitance : 0.00593979 ; + } + pin(A_BIST_ADDR[1]) { + capacitance : 0.00483009 ; + } + pin(A_BIST_ADDR[2]) { + capacitance : 0.006215 ; + } + pin(A_BIST_ADDR[3]) { + capacitance : 0.00766726 ; + } + pin(A_BIST_ADDR[4]) { + capacitance : 0.00488951 ; + } + pin(A_BIST_ADDR[5]) { + capacitance : 0.0091523 ; + } + pin(A_BIST_ADDR[6]) { + capacitance : 0.0109212 ; + } + max_transition : "0.476" ; + pin(A_BIST_ADDR[7:0]) { + related_power_pin : VDD; + related_ground_pin : VSS; + internal_power() { + when : "A_BIST_MEN"; + rise_power("scalar"){ + values (0.0333); + } + fall_power("scalar"){ + values (0.0214); + } + } + internal_power() { + when : "!A_BIST_MEN"; + rise_power("scalar"){ + values (0.0169); + } + fall_power("scalar"){ + values (0.0017); + } + } + } + timing() { + timing_type : setup_rising; + related_pin : "A_BIST_CLK"; + when : "((A_BIST_WEN | A_BIST_REN)& A_BIST_MEN)" + sdf_cond : "A_BIST_RW_ACCESS" + + rise_constraint("SIG2SRAM_constraint_template") { + index_1("0.0056,0.0232,0.0400,0.0728,0.1280,0.2440,0.4760"); + index_2("0.0056,0.0232,0.0400,0.0728,0.1280,0.2440,0.4760"); + values ("-0.4168,-0.3973,-0.3855,-0.3543,-0.3074,-0.2020,-0.0027",\ +"-0.4324,-0.4129,-0.4012,-0.3699,-0.3191,-0.2176,-0.0184",\ +"-0.4441,-0.4285,-0.4129,-0.3816,-0.3309,-0.2293,-0.0301",\ +"-0.4793,-0.4598,-0.4441,-0.4129,-0.3660,-0.2645,-0.0652",\ +"-0.5223,-0.5066,-0.4910,-0.4598,-0.4129,-0.3074,-0.1121",\ +"-0.6199,-0.6082,-0.5926,-0.5613,-0.5145,-0.4129,-0.2137",\ +"-0.8191,-0.8074,-0.7840,-0.7566,-0.7098,-0.6082,-0.4051"); + } + + fall_constraint("SIG2SRAM_constraint_template") { + index_1("0.0056,0.0232,0.0400,0.0728,0.1280,0.2440,0.4760"); + index_2("0.0056,0.0232,0.0400,0.0728,0.1280,0.2440,0.4760"); + values ("-0.3309,-0.3113,-0.2996,-0.2684,-0.2176,-0.1238,0.0637",\ +"-0.3465,-0.3309,-0.3152,-0.2840,-0.2332,-0.1395,0.0480",\ +"-0.3582,-0.3426,-0.3270,-0.2996,-0.2488,-0.1512,0.0324",\ +"-0.3895,-0.3738,-0.3582,-0.3309,-0.2801,-0.1863,0.0051",\ +"-0.4363,-0.4207,-0.4051,-0.3777,-0.3230,-0.2293,-0.0379",\ +"-0.5379,-0.5223,-0.5066,-0.4793,-0.4285,-0.3309,-0.1434",\ +"-0.7332,-0.7176,-0.7020,-0.6746,-0.6238,-0.5262,-0.3387"); + } + } + + + timing() { + timing_type : hold_rising; + related_pin : "A_BIST_CLK"; + when : "((A_BIST_WEN | A_BIST_REN)& A_BIST_MEN)" + sdf_cond : "A_BIST_RW_ACCESS" + + rise_constraint("SIG2SRAM_constraint_template") { + index_1("0.0056,0.0232,0.0400,0.0728,0.1280,0.2440,0.4760"); + index_2("0.0056,0.0232,0.0400,0.0728,0.1280,0.2440,0.4760"); + values ("0.5246,0.5051,0.4895,0.4582,0.4113,0.3059,0.1066",\ +"0.5402,0.5207,0.5051,0.4777,0.4270,0.3215,0.1223",\ +"0.5520,0.5324,0.5168,0.4895,0.4387,0.3371,0.1340",\ +"0.5832,0.5676,0.5520,0.5207,0.4738,0.3684,0.1691",\ +"0.6301,0.6105,0.5949,0.5676,0.5168,0.4113,0.2160",\ +"0.7316,0.7121,0.7004,0.6691,0.6223,0.5168,0.3176",\ +"0.9270,0.9230,0.8957,0.8645,0.8137,0.7121,0.5168"); + } + + fall_constraint("SIG2SRAM_constraint_template") { + index_1("0.0056,0.0232,0.0400,0.0728,0.1280,0.2440,0.4760"); + index_2("0.0056,0.0232,0.0400,0.0728,0.1280,0.2440,0.4760"); + values ("0.4309,0.4152,0.4035,0.3684,0.3215,0.2277,0.0363",\ +"0.4465,0.4309,0.4152,0.3879,0.3371,0.2395,0.0559",\ +"0.4582,0.4426,0.4309,0.3996,0.3488,0.2551,0.0715",\ +"0.4934,0.4777,0.4621,0.4348,0.3840,0.2863,0.0988",\ +"0.5363,0.5207,0.5051,0.4777,0.4270,0.3332,0.1418",\ +"0.6379,0.6262,0.6105,0.5793,0.5324,0.4348,0.2434",\ +"0.8332,0.8215,0.8059,0.7707,0.7238,0.6301,0.4387"); + } + } +} +pin(A_BIST_WEN) { + direction : input ; + capacitance : 0.00324098 ; + max_transition : "0.476" ; + related_power_pin : VDD; + related_ground_pin : VSS; + internal_power() { + when : "A_BIST_MEN"; + rise_power("scalar"){ + values (0.0386); + } + fall_power("scalar"){ + values (0.0676); + } + } + internal_power() { + when : "!A_BIST_MEN"; + rise_power("scalar"){ + values (0.0032); + } + fall_power("scalar"){ + values (0.0048); + } + } + timing() { + timing_type : setup_rising; + related_pin : "A_BIST_CLK"; + when : "A_BIST_MEN" + sdf_cond : "A_BIST_MEN" + + rise_constraint("SIG2SRAM_constraint_template") { + index_1("0.0056,0.0232,0.0400,0.0728,0.1280,0.2440,0.4760"); + index_2("0.0056,0.0232,0.0400,0.0728,0.1280,0.2440,0.4760"); + values ("0.2043,0.2199,0.2316,0.2629,0.3059,0.4113,0.6066",\ +"0.1887,0.2043,0.2160,0.2473,0.2941,0.3957,0.5949",\ +"0.1691,0.1848,0.2004,0.2316,0.2785,0.3801,0.5754",\ +"0.1379,0.1574,0.1691,0.2004,0.2473,0.3527,0.5480",\ +"0.0910,0.1066,0.1223,0.1535,0.2004,0.2980,0.4973",\ +"-0.0105,0.0051,0.0207,0.0520,0.0949,0.2004,0.3957",\ +"-0.2059,-0.1902,-0.1746,-0.1473,-0.1004,0.0051,0.2004"); + } + + fall_constraint("SIG2SRAM_constraint_template") { + index_1("0.0056,0.0232,0.0400,0.0728,0.1280,0.2440,0.4760"); + index_2("0.0056,0.0232,0.0400,0.0728,0.1280,0.2440,0.4760"); + values ("0.2941,0.3098,0.3215,0.3488,0.4035,0.4973,0.6887",\ +"0.2785,0.2941,0.3059,0.3332,0.3840,0.4816,0.6691",\ +"0.2629,0.2785,0.2902,0.3176,0.3684,0.4660,0.6535",\ +"0.2316,0.2473,0.2590,0.2863,0.3410,0.4348,0.6262",\ +"0.1848,0.2004,0.2121,0.2395,0.2902,0.3879,0.5754",\ +"0.0832,0.0988,0.1105,0.1379,0.1809,0.2746,0.4699",\ +"-0.1121,-0.0965,-0.0848,-0.0535,-0.0066,0.0910,0.2824"); + } + } + + + timing() { + timing_type : hold_rising; + related_pin : "A_BIST_CLK"; + when : "A_BIST_MEN" + sdf_cond : "A_BIST_MEN" + + rise_constraint("SIG2SRAM_constraint_template") { + index_1("0.0056,0.0232,0.0400,0.0728,0.1280,0.2440,0.4760"); + index_2("0.0056,0.0232,0.0400,0.0728,0.1280,0.2440,0.4760"); + values ("0.2473,0.2316,0.2160,0.1887,0.1379,0.0363,-0.1629",\ +"0.2629,0.2473,0.2316,0.2043,0.1535,0.0520,-0.1473",\ +"0.2785,0.2590,0.2434,0.2160,0.1652,0.0676,-0.1355",\ +"0.3098,0.2941,0.2785,0.2473,0.1965,0.0910,-0.1043",\ +"0.3527,0.3371,0.3215,0.2941,0.2434,0.1418,-0.0574",\ +"0.4582,0.4426,0.4270,0.3957,0.3488,0.2434,0.0480",\ +"0.6535,0.6379,0.6184,0.5910,0.5402,0.4426,0.2434"); + } + + fall_constraint("SIG2SRAM_constraint_template") { + index_1("0.0056,0.0232,0.0400,0.0728,0.1280,0.2440,0.4760"); + index_2("0.0056,0.0232,0.0400,0.0728,0.1280,0.2440,0.4760"); + values ("0.2395,0.2238,0.2121,0.1809,0.1301,0.0324,-0.1551",\ +"0.2551,0.2395,0.2277,0.1965,0.1457,0.0480,-0.1395",\ +"0.2668,0.2551,0.2395,0.2082,0.1574,0.0637,-0.1277",\ +"0.3020,0.2863,0.2707,0.2395,0.1887,0.0910,-0.0965",\ +"0.3449,0.3293,0.3176,0.2863,0.2355,0.1379,-0.0496",\ +"0.4504,0.4348,0.4191,0.3879,0.3371,0.2395,0.0559",\ +"0.6457,0.6301,0.6145,0.5871,0.5324,0.4309,0.2512"); + } + } + } +pin(A_BIST_REN) { + direction : input ; + capacitance : 0.00381634 ; + max_transition : "0.476" ; + related_power_pin : VDD; + related_ground_pin : VSS; + internal_power() { + when : "A_BIST_MEN"; + rise_power("scalar"){ + values (0.0055); + } + fall_power("scalar"){ + values (0.0031); + } + } + internal_power() { + when : "!A_BIST_MEN"; + rise_power("scalar"){ + values (0.0052); + } + fall_power("scalar"){ + values (0.0034); + } + } + timing() { + timing_type : setup_rising; + related_pin : "A_BIST_CLK"; + when : "A_BIST_MEN" + sdf_cond : "A_BIST_MEN" + + rise_constraint("SIG2SRAM_constraint_template") { + index_1("0.0056,0.0232,0.0400,0.0728,0.1280,0.2440,0.4760"); + index_2("0.0056,0.0232,0.0400,0.0728,0.1280,0.2440,0.4760"); + values ("-0.0301,-0.0145,0.0012,0.0324,0.0793,0.1809,0.3762",\ +"-0.0457,-0.0301,-0.0145,0.0168,0.0637,0.1613,0.3605",\ +"-0.0574,-0.0418,-0.0262,0.0051,0.0520,0.1496,0.3449",\ +"-0.0926,-0.0730,-0.0574,-0.0262,0.0207,0.1184,0.3137",\ +"-0.1395,-0.1238,-0.1082,-0.0770,-0.0301,0.0715,0.2707",\ +"-0.2410,-0.2254,-0.2098,-0.1746,-0.1355,-0.0340,0.1652",\ +"-0.4402,-0.4207,-0.4051,-0.3738,-0.3270,-0.2293,-0.0340"); + } + + fall_constraint("SIG2SRAM_constraint_template") { + index_1("0.0056,0.0232,0.0400,0.0728,0.1280,0.2440,0.4760"); + index_2("0.0056,0.0232,0.0400,0.0728,0.1280,0.2440,0.4760"); + values ("0.0988,0.1145,0.1262,0.1535,0.2043,0.3020,0.4855",\ +"0.0832,0.0988,0.1105,0.1418,0.1848,0.2824,0.4738",\ +"0.0676,0.0832,0.0949,0.1262,0.1730,0.2668,0.4621",\ +"0.0402,0.0559,0.0676,0.0988,0.1457,0.2434,0.4191",\ +"-0.0105,0.0012,0.0168,0.0480,0.0988,0.1965,0.3840",\ +"-0.1160,-0.0965,-0.0848,-0.0535,-0.0066,0.0988,0.2824",\ +"-0.3113,-0.2957,-0.2801,-0.2527,-0.2059,-0.1043,0.0832"); + } + } + + + timing() { + timing_type : hold_rising; + related_pin : "A_BIST_CLK"; + when : "A_BIST_MEN" + sdf_cond : "A_BIST_MEN" + + rise_constraint("SIG2SRAM_constraint_template") { + index_1("0.0056,0.0232,0.0400,0.0728,0.1280,0.2440,0.4760"); + index_2("0.0056,0.0232,0.0400,0.0728,0.1280,0.2440,0.4760"); + values ("0.2707,0.2551,0.2395,0.2121,0.1613,0.0598,-0.1395",\ +"0.2863,0.2707,0.2551,0.2238,0.1730,0.0715,-0.1238",\ +"0.2980,0.2824,0.2668,0.2395,0.1887,0.0871,-0.1121",\ +"0.3332,0.3176,0.3020,0.2707,0.2199,0.1184,-0.0809",\ +"0.3762,0.3605,0.3449,0.3176,0.2668,0.1613,-0.0340",\ +"0.4816,0.4621,0.4504,0.4191,0.3723,0.2629,0.0715",\ +"0.6770,0.6613,0.6418,0.6184,0.5637,0.4699,0.2629"); + } + + fall_constraint("SIG2SRAM_constraint_template") { + index_1("0.0056,0.0232,0.0400,0.0728,0.1280,0.2440,0.4760"); + index_2("0.0056,0.0232,0.0400,0.0728,0.1280,0.2440,0.4760"); + values ("0.2590,0.2434,0.2316,0.2004,0.1457,0.0520,-0.1355",\ +"0.2746,0.2590,0.2434,0.2160,0.1613,0.0676,-0.1199",\ +"0.2863,0.2707,0.2590,0.2277,0.1730,0.0832,-0.1082",\ +"0.3215,0.3059,0.2902,0.2590,0.2082,0.1105,-0.0770",\ +"0.3645,0.3488,0.3332,0.3059,0.2551,0.1535,-0.0340",\ +"0.4699,0.4543,0.4387,0.4074,0.3605,0.2551,0.0715",\ +"0.6652,0.6496,0.6340,0.6027,0.5520,0.4621,0.2707"); + } + } + } +pin(A_BIST_MEN) { + direction : input ; + capacitance : 0.00309605 ; + max_transition : "0.476" ; + related_power_pin : VDD; + related_ground_pin : VSS; + internal_power() { + rise_power("scalar"){ + values (0.0228); + } + fall_power("scalar"){ + values (0.0303); + } + } + timing() { + timing_type : setup_rising; + related_pin : "A_BIST_CLK"; + + rise_constraint("SIG2SRAM_constraint_template") { + index_1("0.0056,0.0232,0.0400,0.0728,0.1280,0.2440,0.4760"); + index_2("0.0056,0.0232,0.0400,0.0728,0.1280,0.2440,0.4760"); + values ("0.2043,0.2199,0.2316,0.2668,0.3098,0.4152,0.6066",\ +"0.1887,0.2043,0.2199,0.2512,0.2941,0.3996,0.5949",\ +"0.1730,0.1887,0.2043,0.2355,0.2824,0.3840,0.5793",\ +"0.1418,0.1574,0.1730,0.2043,0.2512,0.3566,0.5480",\ +"0.0949,0.1105,0.1262,0.1574,0.2043,0.3020,0.5051",\ +"-0.0066,0.0090,0.0246,0.0520,0.0988,0.2043,0.3996",\ +"-0.2020,-0.1863,-0.1746,-0.1434,-0.0965,0.0090,0.2082"); + } + + fall_constraint("SIG2SRAM_constraint_template") { + index_1("0.0056,0.0232,0.0400,0.0728,0.1280,0.2440,0.4760"); + index_2("0.0056,0.0232,0.0400,0.0728,0.1280,0.2440,0.4760"); + values ("0.2980,0.3137,0.3254,0.3527,0.4035,0.5012,0.6887",\ +"0.2824,0.2980,0.3098,0.3371,0.3879,0.4855,0.6730",\ +"0.2668,0.2824,0.2941,0.3215,0.3723,0.4699,0.6574",\ +"0.2355,0.2473,0.2629,0.2902,0.3410,0.4387,0.6262",\ +"0.1887,0.2004,0.2160,0.2395,0.2941,0.3918,0.5793",\ +"0.0871,0.1027,0.1145,0.1418,0.1848,0.2746,0.4816",\ +"-0.1082,-0.0965,-0.0809,-0.0496,-0.0027,0.0949,0.2863"); + } + } + + + timing() { + timing_type : hold_rising; + related_pin : "A_BIST_CLK"; + + rise_constraint("SIG2SRAM_constraint_template") { + index_1("0.0056,0.0232,0.0400,0.0728,0.1280,0.2440,0.4760"); + index_2("0.0056,0.0232,0.0400,0.0728,0.1280,0.2440,0.4760"); + values ("0.2512,0.2355,0.2199,0.1926,0.1418,0.0402,-0.1590",\ +"0.2668,0.2512,0.2355,0.2082,0.1574,0.0559,-0.1434",\ +"0.2824,0.2629,0.2512,0.2199,0.1691,0.0715,-0.1316",\ +"0.3137,0.2980,0.2824,0.2512,0.2004,0.0988,-0.0965",\ +"0.3566,0.3410,0.3254,0.2980,0.2473,0.1418,-0.0535",\ +"0.4621,0.4426,0.4309,0.3996,0.3527,0.2473,0.0520",\ +"0.6574,0.6418,0.6262,0.5949,0.5441,0.4465,0.2473"); + } + + fall_constraint("SIG2SRAM_constraint_template") { + index_1("0.0056,0.0232,0.0400,0.0728,0.1280,0.2440,0.4760"); + index_2("0.0056,0.0232,0.0400,0.0728,0.1280,0.2440,0.4760"); + values ("0.2395,0.2238,0.2121,0.1809,0.1301,0.0324,-0.1551",\ +"0.2551,0.2434,0.2277,0.1965,0.1457,0.0480,-0.1395",\ +"0.2707,0.2551,0.2395,0.2082,0.1574,0.0637,-0.1277",\ +"0.3020,0.2863,0.2707,0.2434,0.1926,0.0910,-0.0965",\ +"0.3449,0.3332,0.3176,0.2863,0.2355,0.1379,-0.0496",\ +"0.4504,0.4348,0.4230,0.3918,0.3410,0.2434,0.0559",\ +"0.6457,0.6301,0.6145,0.5910,0.5324,0.4387,0.2512"); + } + } + } +bus(A_BIST_BM) { + bus_type : D_7_0; + direction : input ; + capacitance : 0.00236845 ; + max_transition : "0.476" ; + pin(A_BIST_BM[7:0]) { + related_power_pin : VDD; + related_ground_pin : VSS; + internal_power() { + when : "A_BIST_MEN"; + rise_power("scalar"){ + values (0.0223); + } + fall_power("scalar"){ + values (0.0190); + } + } + internal_power() { + when : "!A_BIST_MEN"; + rise_power("scalar"){ + values (0.0256); + } + fall_power("scalar"){ + values (0.0189); + } + } + } + timing() { + timing_type : setup_rising; + related_pin : "A_BIST_CLK"; + when : "(A_BIST_WEN & A_BIST_MEN)" + sdf_cond : "A_BIST_RW_ACCESS" + + rise_constraint("SIG2SRAM_constraint_template") { + index_1("0.0056,0.0232,0.0400,0.0728,0.1280,0.2440,0.4760"); + index_2("0.0056,0.0232,0.0400,0.0728,0.1280,0.2440,0.4760"); + values ("-0.3245,-0.3089,-0.2952,-0.2630,-0.2161,-0.1116,0.0798",\ +"-0.3295,-0.3139,-0.3002,-0.2680,-0.2211,-0.1166,0.0748",\ +"-0.3340,-0.3184,-0.3047,-0.2725,-0.2256,-0.1211,0.0703",\ +"-0.3431,-0.3275,-0.3138,-0.2816,-0.2347,-0.1302,0.0612",\ +"-0.3503,-0.3347,-0.3210,-0.2888,-0.2419,-0.1374,0.0540",\ +"-0.3800,-0.3643,-0.3507,-0.3185,-0.2716,-0.1671,0.0243",\ +"-0.4380,-0.4224,-0.4087,-0.3765,-0.3296,-0.2251,-0.0337"); + } + + fall_constraint("SIG2SRAM_constraint_template") { + index_1("0.0056,0.0232,0.0400,0.0728,0.1280,0.2440,0.4760"); + index_2("0.0056,0.0232,0.0400,0.0728,0.1280,0.2440,0.4760"); + values ("-0.2864,-0.2718,-0.2581,-0.2298,-0.1790,-0.0813,0.1013",\ +"-0.2914,-0.2768,-0.2631,-0.2348,-0.1840,-0.0863,0.0963",\ +"-0.2959,-0.2812,-0.2676,-0.2393,-0.1885,-0.0908,0.0918",\ +"-0.3050,-0.2904,-0.2767,-0.2484,-0.1976,-0.0999,0.0827",\ +"-0.3122,-0.2976,-0.2839,-0.2556,-0.2048,-0.1071,0.0755",\ +"-0.3419,-0.3272,-0.3136,-0.2852,-0.2345,-0.1368,0.0458",\ +"-0.3999,-0.3853,-0.3716,-0.3433,-0.2925,-0.1949,-0.0123"); + } + } + + + timing() { + timing_type : hold_rising; + related_pin : "A_BIST_CLK"; + when : "(A_BIST_WEN & A_BIST_MEN)" + sdf_cond : "A_BIST_RW_ACCESS" + + rise_constraint("SIG2SRAM_constraint_template") { + index_1("0.0056,0.0232,0.0400,0.0728,0.1280,0.2440,0.4760"); + index_2("0.0056,0.0232,0.0400,0.0728,0.1280,0.2440,0.4760"); + values ("0.4334,0.4168,0.4042,0.3719,0.3241,0.2206,0.0282",\ +"0.4385,0.4219,0.4092,0.3769,0.3291,0.2256,0.0332",\ +"0.4429,0.4263,0.4136,0.3814,0.3336,0.2300,0.0377",\ +"0.4521,0.4355,0.4228,0.3905,0.3427,0.2392,0.0468",\ +"0.4592,0.4426,0.4300,0.3977,0.3499,0.2464,0.0540",\ +"0.4889,0.4723,0.4596,0.4274,0.3795,0.2760,0.0836",\ +"0.5470,0.5304,0.5177,0.4855,0.4376,0.3341,0.1417"); + } + + fall_constraint("SIG2SRAM_constraint_template") { + index_1("0.0056,0.0232,0.0400,0.0728,0.1280,0.2440,0.4760"); + index_2("0.0056,0.0232,0.0400,0.0728,0.1280,0.2440,0.4760"); + values ("0.3876,0.3729,0.3592,0.3309,0.2811,0.1883,0.0038",\ +"0.3926,0.3779,0.3642,0.3359,0.2861,0.1933,0.0088",\ +"0.3970,0.3824,0.3687,0.3404,0.2906,0.1978,0.0132",\ +"0.4062,0.3915,0.3778,0.3495,0.2997,0.2069,0.0224",\ +"0.4134,0.3987,0.3850,0.3567,0.3069,0.2141,0.0296",\ +"0.4430,0.4284,0.4147,0.3864,0.3366,0.2438,0.0592",\ +"0.5011,0.4864,0.4728,0.4444,0.3946,0.3019,0.1173"); + } + } +} + pin(A_BIST_CLK) { + direction : input; + capacitance : 0.00380014; + max_transition : "0.476"; + clock : "true" ; + pin_func_type : active_rising ; + + timing () { + timing_type : "min_pulse_width"; + related_pin : "A_BIST_CLK"; + rise_constraint("CLKTRAN_constraint_template") { + index_1("0.0056,0.476"); + values("0.21,0.21"); + } + } + + related_power_pin : VDD; + related_ground_pin : VSS; + + internal_power() { + when : "!A_BIST_MEN & !A_BIST_WEN & !A_BIST_REN"; + rise_power("scalar"){ + values (0); + } + fall_power("scalar"){ + values (0); + } + } + internal_power() { + when : "!A_BIST_MEN & A_BIST_WEN & !A_BIST_REN"; + rise_power("scalar"){ + values (0.9849); + } + fall_power("scalar"){ + values (0); + } + } + internal_power() { + when : "A_BIST_MEN & A_BIST_WEN & !A_BIST_REN"; + rise_power("scalar"){ + values (13.5065); + } + fall_power("scalar"){ + values (0); + } + } + internal_power() { + when : "A_BIST_MEN & A_BIST_WEN & A_BIST_REN"; + rise_power("scalar"){ + values (13.2907); + } + fall_power("scalar"){ + values (0); + } + } + internal_power() { + when : "A_BIST_MEN & !A_BIST_WEN & A_BIST_REN"; + rise_power("scalar"){ + values (10.2059); + } + fall_power("scalar"){ + values (0); + } + } + internal_power() { + when : "!A_BIST_MEN & !A_BIST_WEN & A_BIST_REN"; + rise_power("scalar"){ + values (0.2958); + } + fall_power("scalar"){ + values (0); + } + } + internal_power() { + when : "!A_BIST_MEN & A_BIST_WEN & A_BIST_REN"; + rise_power("scalar"){ + values (0.5186); + } + fall_power("scalar"){ + values (0); + } + } + internal_power() { + when : "A_BIST_MEN & !A_BIST_WEN & !A_BIST_REN"; + rise_power("scalar"){ + values (0); + } + fall_power("scalar"){ + values (0); + } + } + } + bus(A_BIST_DIN) { + bus_type : D_7_0; + direction : input ; + capacitance : 0.00232602 ; + memory_write() { + address : A_BIST_ADDR ; + clocked_on : A_BIST_CLK; + } + + max_transition : "0.476" ; + pin(A_BIST_DIN[7:0]) { + related_power_pin : VDD; + related_ground_pin : VSS; + internal_power() { + when : "A_BIST_MEN"; + rise_power("scalar"){ + values (0.0223); + } + fall_power("scalar"){ + values (0.0190); + } + } + internal_power() { + when : "!A_BIST_MEN"; + rise_power("scalar"){ + values (0.0256); + } + fall_power("scalar"){ + values (0.0189); + } + } + } + timing() { + timing_type : setup_rising; + related_pin : "A_BIST_CLK"; + when : "(A_BIST_WEN & A_BIST_MEN)"; + sdf_cond : "A_BIST_W_ACCESS"; + + rise_constraint("SIG2SRAM_constraint_template") { + index_1("0.0056,0.0232,0.0400,0.0728,0.1280,0.2440,0.4760"); + index_2("0.0056,0.0232,0.0400,0.0728,0.1280,0.2440,0.4760"); + values ("-0.3245,-0.3089,-0.2952,-0.2630,-0.2161,-0.1116,0.0798",\ +"-0.3295,-0.3139,-0.3002,-0.2680,-0.2211,-0.1166,0.0748",\ +"-0.3340,-0.3184,-0.3047,-0.2725,-0.2256,-0.1211,0.0703",\ +"-0.3431,-0.3275,-0.3138,-0.2816,-0.2347,-0.1302,0.0612",\ +"-0.3503,-0.3347,-0.3210,-0.2888,-0.2419,-0.1374,0.0540",\ +"-0.3800,-0.3643,-0.3507,-0.3185,-0.2716,-0.1671,0.0243",\ +"-0.4380,-0.4224,-0.4087,-0.3765,-0.3296,-0.2251,-0.0337"); + } + + fall_constraint("SIG2SRAM_constraint_template") { + index_1("0.0056,0.0232,0.0400,0.0728,0.1280,0.2440,0.4760"); + index_2("0.0056,0.0232,0.0400,0.0728,0.1280,0.2440,0.4760"); + values ("-0.2864,-0.2718,-0.2581,-0.2298,-0.1790,-0.0813,0.1013",\ +"-0.2914,-0.2768,-0.2631,-0.2348,-0.1840,-0.0863,0.0963",\ +"-0.2959,-0.2812,-0.2676,-0.2393,-0.1885,-0.0908,0.0918",\ +"-0.3050,-0.2904,-0.2767,-0.2484,-0.1976,-0.0999,0.0827",\ +"-0.3122,-0.2976,-0.2839,-0.2556,-0.2048,-0.1071,0.0755",\ +"-0.3419,-0.3272,-0.3136,-0.2852,-0.2345,-0.1368,0.0458",\ +"-0.3999,-0.3853,-0.3716,-0.3433,-0.2925,-0.1949,-0.0123"); + } + } + + timing() { + timing_type : hold_rising; + related_pin : "A_BIST_CLK"; + when : "(A_BIST_WEN & A_BIST_MEN)"; + sdf_cond : "A_BIST_W_ACCESS"; + + rise_constraint("SIG2SRAM_constraint_template") { + index_1("0.0056,0.0232,0.0400,0.0728,0.1280,0.2440,0.4760"); + index_2("0.0056,0.0232,0.0400,0.0728,0.1280,0.2440,0.4760"); + values ("0.4334,0.4168,0.4042,0.3719,0.3241,0.2206,0.0282",\ +"0.4385,0.4219,0.4092,0.3769,0.3291,0.2256,0.0332",\ +"0.4429,0.4263,0.4136,0.3814,0.3336,0.2300,0.0377",\ +"0.4521,0.4355,0.4228,0.3905,0.3427,0.2392,0.0468",\ +"0.4592,0.4426,0.4300,0.3977,0.3499,0.2464,0.0540",\ +"0.4889,0.4723,0.4596,0.4274,0.3795,0.2760,0.0836",\ +"0.5470,0.5304,0.5177,0.4855,0.4376,0.3341,0.1417"); + } + + fall_constraint("SIG2SRAM_constraint_template") { + index_1("0.0056,0.0232,0.0400,0.0728,0.1280,0.2440,0.4760"); + index_2("0.0056,0.0232,0.0400,0.0728,0.1280,0.2440,0.4760"); + values ("0.3876,0.3729,0.3592,0.3309,0.2811,0.1883,0.0038",\ +"0.3926,0.3779,0.3642,0.3359,0.2861,0.1933,0.0088",\ +"0.3970,0.3824,0.3687,0.3404,0.2906,0.1978,0.0132",\ +"0.4062,0.3915,0.3778,0.3495,0.2997,0.2069,0.0224",\ +"0.4134,0.3987,0.3850,0.3567,0.3069,0.2141,0.0296",\ +"0.4430,0.4284,0.4147,0.3864,0.3366,0.2438,0.0592",\ +"0.5011,0.4864,0.4728,0.4444,0.3946,0.3019,0.1173"); + } + } + } + +bus(A_DOUT) { + + bus_type : D_7_0; + direction : output ; + capacitance : 0 ; + max_capacitance : 0.064 ; + memory_read() { + address : A_ADDR ; + } + pin(A_DOUT[7:0]) { + related_power_pin : VDD; + related_ground_pin : VSS; + internal_power() { + rise_power("scalar") { + values (0); + } + fall_power("scalar") { + values (0); + } + } + } + timing() { + related_pin : "A_CLK"; + timing_type : rising_edge ; + timing_sense : non_unate ; + + cell_rise(SIG2SRAM_delay_template) { + index_1("0.0056,0.0232,0.0400,0.0728,0.1280,0.2440,0.4760"); + index_2("0.0008,0.0014,0.0051,0.0100,0.0339,0.0640"); + values ("2.9577,2.9593,2.9670,2.9757,3.0081,3.0440",\ +"2.9641,2.9657,2.9733,2.9820,3.0145,3.0503",\ +"2.9662,2.9678,2.9754,2.9841,3.0166,3.0524",\ +"2.9792,2.9808,2.9885,2.9972,3.0296,3.0655",\ +"2.9854,2.9870,2.9947,3.0034,3.0358,3.0717",\ +"3.0169,3.0185,3.0262,3.0349,3.0673,3.1032",\ +"3.0714,3.0730,3.0807,3.0894,3.1218,3.1577"); + } + cell_fall(SIG2SRAM_delay_template) { + index_1("0.0056,0.0232,0.0400,0.0728,0.1280,0.2440,0.4760"); + index_2("0.0008,0.0014,0.0051,0.0100,0.0339,0.0640"); + values ("2.8967,2.8980,2.9040,2.9111,2.9376,2.9643",\ +"2.9030,2.9043,2.9103,2.9175,2.9440,2.9706",\ +"2.9051,2.9064,2.9124,2.9196,2.9461,2.9727",\ +"2.9181,2.9195,2.9255,2.9326,2.9591,2.9858",\ +"2.9243,2.9257,2.9317,2.9388,2.9653,2.9920",\ +"2.9558,2.9571,2.9631,2.9703,2.9968,3.0234",\ +"3.0103,3.0117,3.0177,3.0248,3.0513,3.0779"); + } + + rise_transition(SRAM_load_template) { + index_1("0.0008,0.0014,0.0051,0.0100,0.0339,0.0640"); + values ("0.0326,0.0341,0.0428,0.0518,0.0923,0.1492"); + } + fall_transition(SRAM_load_template) { + index_1("0.0008,0.0014,0.0051,0.0100,0.0339,0.0640"); + values ("0.0254,0.0265,0.0335,0.0402,0.0707,0.1039"); + } + } +} +cell_leakage_power : 24.7519; +} +} diff --git a/flow/platforms/ihp-sg13g2/lib/RM_IHPSG13_1P_4096x16_c3_bm_bist_fast_1p32V_m55C.lib b/flow/platforms/ihp-sg13g2/lib/RM_IHPSG13_1P_4096x16_c3_bm_bist_fast_1p32V_m55C.lib index aafc0b323c..71cbdff412 100644 --- a/flow/platforms/ihp-sg13g2/lib/RM_IHPSG13_1P_4096x16_c3_bm_bist_fast_1p32V_m55C.lib +++ b/flow/platforms/ihp-sg13g2/lib/RM_IHPSG13_1P_4096x16_c3_bm_bist_fast_1p32V_m55C.lib @@ -1478,7 +1478,7 @@ bus(A_DOUT) { bus_type : D_15_0; direction : output ; capacitance : 0 ; - max_capacitance : "6.4e-14" ; + max_capacitance : 0.064 ; memory_read() { address : A_ADDR ; } diff --git a/flow/platforms/ihp-sg13g2/lib/RM_IHPSG13_1P_4096x16_c3_bm_bist_slow_1p08V_125C.lib b/flow/platforms/ihp-sg13g2/lib/RM_IHPSG13_1P_4096x16_c3_bm_bist_slow_1p08V_125C.lib index acf9678138..844f3ed18f 100644 --- a/flow/platforms/ihp-sg13g2/lib/RM_IHPSG13_1P_4096x16_c3_bm_bist_slow_1p08V_125C.lib +++ b/flow/platforms/ihp-sg13g2/lib/RM_IHPSG13_1P_4096x16_c3_bm_bist_slow_1p08V_125C.lib @@ -1478,7 +1478,7 @@ bus(A_DOUT) { bus_type : D_15_0; direction : output ; capacitance : 0 ; - max_capacitance : "6.4e-14" ; + max_capacitance : 0.064 ; memory_read() { address : A_ADDR ; } diff --git a/flow/platforms/ihp-sg13g2/lib/RM_IHPSG13_1P_4096x16_c3_bm_bist_typ_1p20V_25C.lib b/flow/platforms/ihp-sg13g2/lib/RM_IHPSG13_1P_4096x16_c3_bm_bist_typ_1p20V_25C.lib index 86dafef075..60f07831e5 100644 --- a/flow/platforms/ihp-sg13g2/lib/RM_IHPSG13_1P_4096x16_c3_bm_bist_typ_1p20V_25C.lib +++ b/flow/platforms/ihp-sg13g2/lib/RM_IHPSG13_1P_4096x16_c3_bm_bist_typ_1p20V_25C.lib @@ -1478,7 +1478,7 @@ bus(A_DOUT) { bus_type : D_15_0; direction : output ; capacitance : 0 ; - max_capacitance : "6.4e-14" ; + max_capacitance : 0.064 ; memory_read() { address : A_ADDR ; } diff --git a/flow/platforms/ihp-sg13g2/lib/RM_IHPSG13_1P_4096x8_c3_bm_bist_fast_1p32V_m55C.lib b/flow/platforms/ihp-sg13g2/lib/RM_IHPSG13_1P_4096x8_c3_bm_bist_fast_1p32V_m55C.lib index 4aff53a01f..7ca4d0866a 100644 --- a/flow/platforms/ihp-sg13g2/lib/RM_IHPSG13_1P_4096x8_c3_bm_bist_fast_1p32V_m55C.lib +++ b/flow/platforms/ihp-sg13g2/lib/RM_IHPSG13_1P_4096x8_c3_bm_bist_fast_1p32V_m55C.lib @@ -1478,7 +1478,7 @@ bus(A_DOUT) { bus_type : D_7_0; direction : output ; capacitance : 0 ; - max_capacitance : "6.4e-14" ; + max_capacitance : 0.064 ; memory_read() { address : A_ADDR ; } diff --git a/flow/platforms/ihp-sg13g2/lib/RM_IHPSG13_1P_4096x8_c3_bm_bist_slow_1p08V_125C.lib b/flow/platforms/ihp-sg13g2/lib/RM_IHPSG13_1P_4096x8_c3_bm_bist_slow_1p08V_125C.lib index 236e4866c9..1ca264d81c 100644 --- a/flow/platforms/ihp-sg13g2/lib/RM_IHPSG13_1P_4096x8_c3_bm_bist_slow_1p08V_125C.lib +++ b/flow/platforms/ihp-sg13g2/lib/RM_IHPSG13_1P_4096x8_c3_bm_bist_slow_1p08V_125C.lib @@ -1478,7 +1478,7 @@ bus(A_DOUT) { bus_type : D_7_0; direction : output ; capacitance : 0 ; - max_capacitance : "6.4e-14" ; + max_capacitance : 0.064 ; memory_read() { address : A_ADDR ; } diff --git a/flow/platforms/ihp-sg13g2/lib/RM_IHPSG13_1P_4096x8_c3_bm_bist_typ_1p20V_25C.lib b/flow/platforms/ihp-sg13g2/lib/RM_IHPSG13_1P_4096x8_c3_bm_bist_typ_1p20V_25C.lib index 0dd7037c33..fd0b3e7395 100644 --- a/flow/platforms/ihp-sg13g2/lib/RM_IHPSG13_1P_4096x8_c3_bm_bist_typ_1p20V_25C.lib +++ b/flow/platforms/ihp-sg13g2/lib/RM_IHPSG13_1P_4096x8_c3_bm_bist_typ_1p20V_25C.lib @@ -1478,7 +1478,7 @@ bus(A_DOUT) { bus_type : D_7_0; direction : output ; capacitance : 0 ; - max_capacitance : "6.4e-14" ; + max_capacitance : 0.064 ; memory_read() { address : A_ADDR ; } diff --git a/flow/platforms/ihp-sg13g2/lib/RM_IHPSG13_1P_512x16_c2_bm_bist_fast_1p32V_m55C.lib b/flow/platforms/ihp-sg13g2/lib/RM_IHPSG13_1P_512x16_c2_bm_bist_fast_1p32V_m55C.lib new file mode 100644 index 0000000000..fb69d39286 --- /dev/null +++ b/flow/platforms/ihp-sg13g2/lib/RM_IHPSG13_1P_512x16_c2_bm_bist_fast_1p32V_m55C.lib @@ -0,0 +1,1519 @@ +/* ------------------------------------------------------*/ +/**/ +/* Copyright 2025 IHP PDK Authors*/ +/**/ +/* Licensed under the Apache License, Version 2.0 (the "License");*/ +/* you may not use this file except in compliance with the License.*/ +/* You may obtain a copy of the License at*/ +/* */ +/* https://www.apache.org/licenses/LICENSE-2.0*/ +/* */ +/* Unless required by applicable law or agreed to in writing, software*/ +/* distributed under the License is distributed on an "AS IS" BASIS,*/ +/* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.*/ +/* See the License for the specific language governing permissions and*/ +/* limitations under the License.*/ +/* */ +/* Generated on Wed Aug 27 12:16:34 2025 */ +/* */ +/* ------------------------------------------------------ */ +library(RM_IHPSG13_1P_512x16_c2_bm_bist_fast_1p32V_m55C) { + technology (cmos) ; + delay_model : table_lookup ; + define ("add_pg_pin_to_lib", "library", "boolean"); + add_pg_pin_to_lib : true; + voltage_map ( VDD, 1.32); + voltage_map ( VDDARRAY, 1.32); + voltage_map ( VSS, 0.000000 ); + + date : "Wed Aug 27 12:16:33 2025" ; + comment : "IHP Microelectronics GmbH, 2023" ; + revision : 1.0.0 ; + simulation : true ; + nom_process : 1 ; + nom_temperature : -55 ; + nom_voltage : 1.32 ; + + operating_conditions("fast_1p32V_m55C"){ + process : 1 ; + temperature : -55 ; + voltage : 1.32 ; + tree_type : "balanced_tree" ; + } + + default_operating_conditions : fast_1p32V_m55C ; + default_max_transition : 1.0 ; + default_fanout_load : 1.0 ; + default_inout_pin_cap : 0.0 ; + default_input_pin_cap : 0.0 ; + default_output_pin_cap : 0.0 ; + default_cell_leakage_power : 0.0 ; + default_leakage_power_density : 0.0 ; + + slew_lower_threshold_pct_rise : 30 ; + slew_upper_threshold_pct_rise : 70 ; + input_threshold_pct_fall : 50 ; + output_threshold_pct_fall : 50 ; + input_threshold_pct_rise : 50 ; + output_threshold_pct_rise : 50 ; + slew_lower_threshold_pct_fall : 30 ; + slew_upper_threshold_pct_fall : 70 ; + slew_derate_from_library : 0.5; + k_volt_cell_leakage_power : 0.0 ; + k_temp_cell_leakage_power : 0.0 ; + k_process_cell_leakage_power : 0.0 ; + k_volt_internal_power : 0.0 ; + k_temp_internal_power : 0.0 ; + k_process_internal_power : 0.0 ; + + capacitive_load_unit (1,pf) ; + voltage_unit : "1V" ; + current_unit : "1uA" ; + time_unit : "1ns" ; + leakage_power_unit : "1nW" ; + pulling_resistance_unit : "1kohm"; + /* + ------------------------------------------------------------------------------------------ + implicit units overview: + cell_area unit : "um" + internal_power unit : "1e-12 * J/toggle = 1 * uW/MHz" + (capacitive_load_unit * voltage_unit^2) per toggle event + ------------------------------------------------------------------------------------------ + */ + library_features(report_delay_calculation); + define_cell_area (pad_drivers,pad_driver_sites) ; + + lu_table_template(CLKTRAN_constraint_template) { + variable_1 : constrained_pin_transition; + index_1 ( "0.010, 0.050, 0.200, 0.400, 1.000" ); + } + lu_table_template(SRAM_load_template) { + variable_1 : total_output_net_capacitance; + index_1 ( "0.0008,0.0014,0.0051,0.0100,0.0339,0.0640" ); + } + lu_table_template(SIG2SRAM_constraint_template) { + variable_1 : related_pin_transition; + variable_2 : constrained_pin_transition; + index_1 ( "0.0040,0.0176,0.0344,0.0656,0.1120,0.2016,0.3800" ); + index_2 ( "0.0040,0.0176,0.0344,0.0656,0.1120,0.2016,0.3800" ); + } + + lu_table_template(SIG2SRAM_delay_template) { + variable_1 : input_net_transition; + variable_2 : total_output_net_capacitance; + index_1 ( "0.0040,0.0176,0.0344,0.0656,0.1120,0.2016,0.3800" ); + index_2 ( "0.0008,0.0014,0.0051,0.0100,0.0339,0.0640" ); + } + + type (D_15_0) { + base_type : array; + data_type : bit; + bit_width : 16; + bit_from : 15; + bit_to : 0; + downto : true; + } + + type (A_8_0) { + base_type : array; + data_type : bit; + bit_width : 9; + bit_from : 8; + bit_to : 0; + downto : true; + } + +cell(RM_IHPSG13_1P_512x16_c2_bm_bist) { +pg_pin (VDD) { + pg_type : primary_power; + voltage_name : VDD; +} +pg_pin (VDDARRAY) { + pg_type : primary_power; + voltage_name : VDDARRAY; +} +pg_pin (VSS) { + pg_type : primary_ground; + voltage_name : VSS; +} + +memory() { + type : ram; + address_width : 9; + word_width : 16; +} + +interface_timing : false; +bus_naming_style : "%s[%d]" ; +area : 45309.312 ; + + pin(A_DLY) { + direction : input ; + capacitance : 0.00421562 ; + max_transition : "1" ; + related_power_pin : VDD; + related_ground_pin : VSS; + internal_power() { + rise_power("scalar") { + values (0); + } + fall_power("scalar") { + values (0); + } + } + } + +bus(A_ADDR) { + bus_type : A_8_0; + direction : input ; + capacitance : 0.00691085 ; + pin(A_ADDR[0]) { + capacitance : 0.00562034 ; + } + pin(A_ADDR[1]) { + capacitance : 0.00462655 ; + } + pin(A_ADDR[2]) { + capacitance : 0.00594295 ; + } + pin(A_ADDR[3]) { + capacitance : 0.00723434 ; + } + pin(A_ADDR[4]) { + capacitance : 0.00481603 ; + } + pin(A_ADDR[5]) { + capacitance : 0.00868123 ; + } + pin(A_ADDR[6]) { + capacitance : 0.010187 ; + } + pin(A_ADDR[7]) { + capacitance : 0.00734489 ; + } + max_transition : "0.38" ; + pin(A_ADDR[8:0]) { + related_power_pin : VDD; + related_ground_pin : VSS; + internal_power() { + when : "A_MEN"; + rise_power("scalar"){ + values (0.0125); + } + fall_power("scalar"){ + values (0.0025); + } + } + internal_power() { + when : "!A_MEN"; + rise_power("scalar"){ + values (0.0288); + } + fall_power("scalar"){ + values (0.0013); + } + } + } + timing() { + timing_type : setup_rising; + related_pin : "A_CLK"; + when : "((A_WEN | A_REN)& A_MEN)" + sdf_cond : "A_RW_ACCESS" + + rise_constraint("SIG2SRAM_constraint_template") { + index_1("0.0040,0.0176,0.0344,0.0656,0.1120,0.2016,0.3800"); + index_2("0.0040,0.0176,0.0344,0.0656,0.1120,0.2016,0.3800"); + values ("-0.2371,-0.2215,-0.2098,-0.1824,-0.1434,-0.0691,0.0676",\ +"-0.2449,-0.2332,-0.2176,-0.1902,-0.1551,-0.0770,0.0559",\ +"-0.2605,-0.2488,-0.2332,-0.2059,-0.1707,-0.0965,0.0441",\ +"-0.2879,-0.2723,-0.2605,-0.2332,-0.1941,-0.1199,0.0168",\ +"-0.3230,-0.3113,-0.2996,-0.2723,-0.2332,-0.1590,-0.0184",\ +"-0.4012,-0.3895,-0.3738,-0.3465,-0.3074,-0.2332,-0.0965",\ +"-0.5379,-0.5262,-0.5105,-0.4832,-0.4480,-0.3699,-0.2332"); + } + + fall_constraint("SIG2SRAM_constraint_template") { + index_1("0.0040,0.0176,0.0344,0.0656,0.1120,0.2016,0.3800"); + index_2("0.0040,0.0176,0.0344,0.0656,0.1120,0.2016,0.3800"); + values ("-0.1785,-0.1707,-0.1551,-0.1277,-0.0887,-0.0184,0.1145",\ +"-0.1902,-0.1785,-0.1629,-0.1355,-0.1004,-0.0262,0.1027",\ +"-0.2059,-0.1941,-0.1785,-0.1512,-0.1160,-0.0418,0.0871",\ +"-0.2293,-0.2176,-0.2059,-0.1785,-0.1434,-0.0691,0.0598",\ +"-0.2684,-0.2566,-0.2449,-0.2176,-0.1824,-0.1082,0.0207",\ +"-0.3465,-0.3348,-0.3191,-0.2918,-0.2566,-0.1824,-0.0535",\ +"-0.4832,-0.4715,-0.4559,-0.4324,-0.3934,-0.3191,-0.1902"); + } + } + + + timing() { + timing_type : hold_rising; + related_pin : "A_CLK"; + when : "((A_WEN | A_REN)& A_MEN)" + sdf_cond : "A_RW_ACCESS" + + rise_constraint("SIG2SRAM_constraint_template") { + index_1("0.0040,0.0176,0.0344,0.0656,0.1120,0.2016,0.3800"); + index_2("0.0040,0.0176,0.0344,0.0656,0.1120,0.2016,0.3800"); + values ("0.3410,0.3293,0.3137,0.2863,0.2473,0.1730,0.0324",\ +"0.3488,0.3371,0.3215,0.2941,0.2590,0.1809,0.0480",\ +"0.3684,0.3527,0.3371,0.3098,0.2746,0.1965,0.0598",\ +"0.3918,0.3762,0.3645,0.3371,0.2980,0.2238,0.0871",\ +"0.4309,0.4152,0.4035,0.3762,0.3371,0.2629,0.1223",\ +"0.5051,0.4934,0.4777,0.4504,0.4113,0.3371,0.1965",\ +"0.6418,0.6262,0.6145,0.5871,0.5520,0.4738,0.3332"); + } + + fall_constraint("SIG2SRAM_constraint_template") { + index_1("0.0040,0.0176,0.0344,0.0656,0.1120,0.2016,0.3800"); + index_2("0.0040,0.0176,0.0344,0.0656,0.1120,0.2016,0.3800"); + values ("0.2824,0.2707,0.2551,0.2277,0.1926,0.1184,-0.0105",\ +"0.2902,0.2785,0.2668,0.2395,0.2043,0.1301,0.0012",\ +"0.3059,0.2941,0.2824,0.2551,0.2199,0.1457,0.0168",\ +"0.3332,0.3215,0.3059,0.2785,0.2434,0.1691,0.0402",\ +"0.3723,0.3605,0.3449,0.3176,0.2824,0.2121,0.0793",\ +"0.4465,0.4348,0.4230,0.3918,0.3566,0.2824,0.1535",\ +"0.5832,0.5715,0.5598,0.5324,0.4934,0.4191,0.2902"); + } + } +} +pin(A_WEN) { + direction : input ; + capacitance : 0.00341384 ; + max_transition : "0.38" ; + related_power_pin : VDD; + related_ground_pin : VSS; + internal_power() { + when : "A_MEN"; + rise_power("scalar"){ + values (0.0076); + } + fall_power("scalar"){ + values (0.0137); + } + } + internal_power() { + when : "!A_MEN"; + rise_power("scalar"){ + values (0.0073); + } + fall_power("scalar"){ + values (0.0261); + } + } + timing() { + timing_type : setup_rising; + related_pin : "A_CLK"; + when : "A_MEN" + sdf_cond : "A_MEN" + + rise_constraint("SIG2SRAM_constraint_template") { + index_1("0.0040,0.0176,0.0344,0.0656,0.1120,0.2016,0.3800"); + index_2("0.0040,0.0176,0.0344,0.0656,0.1120,0.2016,0.3800"); + values ("0.1418,0.1496,0.1652,0.1887,0.2316,0.3059,0.4465",\ +"0.1301,0.1379,0.1535,0.1809,0.2199,0.2941,0.4348",\ +"0.1145,0.1262,0.1379,0.1652,0.2043,0.2785,0.4191",\ +"0.0871,0.0949,0.1105,0.1379,0.1770,0.2512,0.3879",\ +"0.0480,0.0598,0.0754,0.0988,0.1379,0.2082,0.3527",\ +"-0.0262,-0.0145,0.0012,0.0246,0.0676,0.1379,0.2785",\ +"-0.1668,-0.1551,-0.1395,-0.1121,-0.0730,0.0012,0.1418"); + } + + fall_constraint("SIG2SRAM_constraint_template") { + index_1("0.0040,0.0176,0.0344,0.0656,0.1120,0.2016,0.3800"); + index_2("0.0040,0.0176,0.0344,0.0656,0.1120,0.2016,0.3800"); + values ("0.2082,0.2160,0.2316,0.2590,0.2941,0.3684,0.5012",\ +"0.1926,0.2043,0.2199,0.2473,0.2824,0.3566,0.4895",\ +"0.1770,0.1887,0.2043,0.2316,0.2668,0.3410,0.4777",\ +"0.1535,0.1652,0.1770,0.2043,0.2395,0.3137,0.4504",\ +"0.1145,0.1262,0.1379,0.1652,0.2043,0.2746,0.4113",\ +"0.0402,0.0520,0.0676,0.0910,0.1262,0.2004,0.3332",\ +"-0.0965,-0.0848,-0.0730,-0.0457,-0.0066,0.0637,0.2004"); + } + } + + + timing() { + timing_type : hold_rising; + related_pin : "A_CLK"; + when : "A_MEN" + sdf_cond : "A_MEN" + + rise_constraint("SIG2SRAM_constraint_template") { + index_1("0.0040,0.0176,0.0344,0.0656,0.1120,0.2016,0.3800"); + index_2("0.0040,0.0176,0.0344,0.0656,0.1120,0.2016,0.3800"); + values ("0.1770,0.1652,0.1496,0.1223,0.0793,0.0090,-0.1316",\ +"0.1848,0.1730,0.1574,0.1301,0.0910,0.0168,-0.1199",\ +"0.2004,0.1887,0.1770,0.1496,0.1066,0.0363,-0.1043",\ +"0.2277,0.2160,0.2004,0.1730,0.1340,0.0598,-0.0809",\ +"0.2668,0.2551,0.2395,0.2121,0.1730,0.0988,-0.0418",\ +"0.3410,0.3293,0.3137,0.2863,0.2434,0.1730,0.0324",\ +"0.4816,0.4699,0.4543,0.4230,0.3801,0.3098,0.1730"); + } + + fall_constraint("SIG2SRAM_constraint_template") { + index_1("0.0040,0.0176,0.0344,0.0656,0.1120,0.2016,0.3800"); + index_2("0.0040,0.0176,0.0344,0.0656,0.1120,0.2016,0.3800"); + values ("0.1613,0.1496,0.1379,0.1066,0.0715,0.0012,-0.1355",\ +"0.1730,0.1613,0.1457,0.1184,0.0832,0.0129,-0.1238",\ +"0.1887,0.1770,0.1613,0.1340,0.0988,0.0246,-0.1121",\ +"0.2121,0.2043,0.1887,0.1613,0.1223,0.0520,-0.0848",\ +"0.2512,0.2434,0.2277,0.2004,0.1613,0.0910,-0.0457",\ +"0.3254,0.3176,0.3020,0.2746,0.2355,0.1652,0.0324",\ +"0.4660,0.4543,0.4387,0.4113,0.3723,0.3020,0.1691"); + } + } + } +pin(A_REN) { + direction : input ; + capacitance : 0.00390661 ; + max_transition : "0.38" ; + related_power_pin : VDD; + related_ground_pin : VSS; + internal_power() { + when : "A_MEN"; + rise_power("scalar"){ + values (0.0069); + } + fall_power("scalar"){ + values (0.0122); + } + } + internal_power() { + when : "!A_MEN"; + rise_power("scalar"){ + values (0.0243); + } + fall_power("scalar"){ + values (0.0202); + } + } + timing() { + timing_type : setup_rising; + related_pin : "A_CLK"; + when : "A_MEN" + sdf_cond : "A_MEN" + + rise_constraint("SIG2SRAM_constraint_template") { + index_1("0.0040,0.0176,0.0344,0.0656,0.1120,0.2016,0.3800"); + index_2("0.0040,0.0176,0.0344,0.0656,0.1120,0.2016,0.3800"); + values ("-0.0027,0.0090,0.0246,0.0520,0.0910,0.1613,0.3020",\ +"-0.0105,0.0012,0.0129,0.0363,0.0793,0.1535,0.2902",\ +"-0.0262,-0.0145,-0.0027,0.0246,0.0637,0.1379,0.2785",\ +"-0.0535,-0.0418,-0.0262,0.0012,0.0363,0.1105,0.2512",\ +"-0.0926,-0.0809,-0.0652,-0.0418,-0.0027,0.0715,0.2121",\ +"-0.1668,-0.1551,-0.1395,-0.1082,-0.0770,-0.0027,0.1379",\ +"-0.3035,-0.2918,-0.2762,-0.2488,-0.2137,-0.1434,-0.0027"); + } + + fall_constraint("SIG2SRAM_constraint_template") { + index_1("0.0040,0.0176,0.0344,0.0656,0.1120,0.2016,0.3800"); + index_2("0.0040,0.0176,0.0344,0.0656,0.1120,0.2016,0.3800"); + values ("0.0832,0.0949,0.1105,0.1379,0.1730,0.2473,0.3801",\ +"0.0754,0.0832,0.0988,0.1223,0.1613,0.2355,0.3684",\ +"0.0598,0.0676,0.0832,0.1066,0.1457,0.2121,0.3527",\ +"0.0324,0.0441,0.0598,0.0871,0.1223,0.1926,0.3293",\ +"-0.0066,0.0051,0.0168,0.0480,0.0832,0.1535,0.2902",\ +"-0.0809,-0.0691,-0.0574,-0.0301,0.0090,0.0832,0.2121",\ +"-0.2176,-0.2059,-0.1941,-0.1668,-0.1277,-0.0574,0.0793"); + } + } + + + timing() { + timing_type : hold_rising; + related_pin : "A_CLK"; + when : "A_MEN" + sdf_cond : "A_MEN" + + rise_constraint("SIG2SRAM_constraint_template") { + index_1("0.0040,0.0176,0.0344,0.0656,0.1120,0.2016,0.3800"); + index_2("0.0040,0.0176,0.0344,0.0656,0.1120,0.2016,0.3800"); + values ("0.1887,0.1770,0.1613,0.1340,0.0949,0.0207,-0.1160",\ +"0.1965,0.1848,0.1730,0.1457,0.1027,0.0324,-0.1082",\ +"0.2160,0.2004,0.1887,0.1613,0.1184,0.0480,-0.0926",\ +"0.2395,0.2277,0.2121,0.1848,0.1457,0.0715,-0.0652",\ +"0.2785,0.2668,0.2512,0.2238,0.1848,0.1105,-0.0262",\ +"0.3527,0.3410,0.3254,0.2980,0.2551,0.1848,0.0480",\ +"0.4934,0.4816,0.4660,0.4387,0.3957,0.3254,0.1887"); + } + + fall_constraint("SIG2SRAM_constraint_template") { + index_1("0.0040,0.0176,0.0344,0.0656,0.1120,0.2016,0.3800"); + index_2("0.0040,0.0176,0.0344,0.0656,0.1120,0.2016,0.3800"); + values ("0.1730,0.1613,0.1496,0.1184,0.0793,0.0129,-0.1238",\ +"0.1848,0.1730,0.1574,0.1301,0.0910,0.0207,-0.1121",\ +"0.2004,0.1887,0.1730,0.1457,0.1066,0.0363,-0.1004",\ +"0.2238,0.2121,0.2004,0.1691,0.1340,0.0598,-0.0730",\ +"0.2629,0.2512,0.2395,0.2121,0.1691,0.0988,-0.0340",\ +"0.3371,0.3254,0.3137,0.2863,0.2434,0.1730,0.0402",\ +"0.4777,0.4660,0.4504,0.4230,0.3840,0.3137,0.1809"); + } + } + } +pin(A_MEN) { + direction : input ; + capacitance : 0.00326046 ; + max_transition : "0.38" ; + related_power_pin : VDD; + related_ground_pin : VSS; + internal_power() { + rise_power("scalar"){ + values (0.1674); + } + fall_power("scalar"){ + values (0.0108); + } + } + timing() { + timing_type : setup_rising; + related_pin : "A_CLK"; + + rise_constraint("SIG2SRAM_constraint_template") { + index_1("0.0040,0.0176,0.0344,0.0656,0.1120,0.2016,0.3800"); + index_2("0.0040,0.0176,0.0344,0.0656,0.1120,0.2016,0.3800"); + values ("0.1418,0.1496,0.1652,0.1926,0.2316,0.3059,0.4465",\ +"0.1301,0.1379,0.1535,0.1809,0.2199,0.2941,0.4348",\ +"0.1145,0.1262,0.1418,0.1652,0.2043,0.2785,0.4191",\ +"0.0871,0.0949,0.1105,0.1379,0.1770,0.2512,0.3879",\ +"0.0480,0.0598,0.0754,0.0988,0.1379,0.2082,0.3488",\ +"-0.0262,-0.0145,0.0012,0.0285,0.0676,0.1379,0.2785",\ +"-0.1668,-0.1551,-0.1395,-0.1121,-0.0730,0.0012,0.1379"); + } + + fall_constraint("SIG2SRAM_constraint_template") { + index_1("0.0040,0.0176,0.0344,0.0656,0.1120,0.2016,0.3800"); + index_2("0.0040,0.0176,0.0344,0.0656,0.1120,0.2016,0.3800"); + values ("0.2082,0.2199,0.2316,0.2590,0.2980,0.3723,0.5051",\ +"0.1965,0.2082,0.2199,0.2473,0.2863,0.3605,0.4934",\ +"0.1809,0.1926,0.2043,0.2316,0.2707,0.3449,0.4777",\ +"0.1574,0.1691,0.1809,0.2082,0.2434,0.3176,0.4543",\ +"0.1145,0.1262,0.1418,0.1691,0.2043,0.2785,0.4113",\ +"0.0441,0.0559,0.0676,0.0949,0.1301,0.2004,0.3332",\ +"-0.0965,-0.0848,-0.0691,-0.0418,-0.0066,0.0676,0.2004"); + } + } + + + timing() { + timing_type : hold_rising; + related_pin : "A_CLK"; + + rise_constraint("SIG2SRAM_constraint_template") { + index_1("0.0040,0.0176,0.0344,0.0656,0.1120,0.2016,0.3800"); + index_2("0.0040,0.0176,0.0344,0.0656,0.1120,0.2016,0.3800"); + values ("0.1770,0.1652,0.1535,0.1262,0.0832,0.0129,-0.1277",\ +"0.1887,0.1770,0.1613,0.1340,0.0949,0.0207,-0.1199",\ +"0.2043,0.1926,0.1770,0.1496,0.1105,0.0363,-0.1043",\ +"0.2277,0.2160,0.2043,0.1770,0.1379,0.0598,-0.0770",\ +"0.2668,0.2551,0.2434,0.2160,0.1730,0.0988,-0.0379",\ +"0.3449,0.3332,0.3176,0.2902,0.2473,0.1730,0.0363",\ +"0.4816,0.4699,0.4543,0.4270,0.3840,0.3098,0.1770"); + } + + fall_constraint("SIG2SRAM_constraint_template") { + index_1("0.0040,0.0176,0.0344,0.0656,0.1120,0.2016,0.3800"); + index_2("0.0040,0.0176,0.0344,0.0656,0.1120,0.2016,0.3800"); + values ("0.1613,0.1496,0.1379,0.1105,0.0715,0.0012,-0.1355",\ +"0.1730,0.1613,0.1496,0.1184,0.0832,0.0129,-0.1238",\ +"0.1887,0.1770,0.1652,0.1340,0.0988,0.0285,-0.1121",\ +"0.2121,0.2043,0.1887,0.1613,0.1223,0.0520,-0.0848",\ +"0.2551,0.2434,0.2277,0.2004,0.1613,0.0910,-0.0418",\ +"0.3293,0.3176,0.3020,0.2746,0.2395,0.1652,0.0324",\ +"0.4660,0.4543,0.4426,0.4113,0.3762,0.3020,0.1691"); + } + } + } +bus(A_BM) { + bus_type : D_15_0; + direction : input ; + capacitance : 0.00310985 ; + max_transition : "0.38" ; + pin(A_BM[15:0]) { + related_power_pin : VDD; + related_ground_pin : VSS; + internal_power() { + when : "A_MEN"; + rise_power("scalar"){ + values (0.0757); + } + fall_power("scalar"){ + values (0.0696); + } + } + internal_power() { + when : "!A_MEN"; + rise_power("scalar"){ + values (0.0977); + } + fall_power("scalar"){ + values (0.0801); + } + } + } + timing() { + timing_type : setup_rising; + related_pin : "A_CLK"; + when : "(A_WEN & A_MEN)" + sdf_cond : "A_RW_ACCESS" + + rise_constraint("SIG2SRAM_constraint_template") { + index_1("0.0040,0.0176,0.0344,0.0656,0.1120,0.2016,0.3800"); + index_2("0.0040,0.0176,0.0344,0.0656,0.1120,0.2016,0.3800"); + values ("-0.1890,-0.1783,-0.1627,-0.1363,-0.0963,-0.0260,0.1088",\ +"-0.1929,-0.1822,-0.1666,-0.1402,-0.1002,-0.0298,0.1049",\ +"-0.1967,-0.1860,-0.1704,-0.1440,-0.1040,-0.0336,0.1011",\ +"-0.2000,-0.1892,-0.1736,-0.1472,-0.1072,-0.0369,0.0979",\ +"-0.2124,-0.2017,-0.1861,-0.1597,-0.1196,-0.0493,0.0854",\ +"-0.2300,-0.2193,-0.2037,-0.1773,-0.1373,-0.0669,0.0678",\ +"-0.2576,-0.2468,-0.2312,-0.2048,-0.1648,-0.0945,0.0403"); + } + + fall_constraint("SIG2SRAM_constraint_template") { + index_1("0.0040,0.0176,0.0344,0.0656,0.1120,0.2016,0.3800"); + index_2("0.0040,0.0176,0.0344,0.0656,0.1120,0.2016,0.3800"); + values ("-0.1666,-0.1558,-0.1422,-0.1148,-0.0777,-0.0055,0.1244",\ +"-0.1705,-0.1597,-0.1461,-0.1187,-0.0816,-0.0093,0.1205",\ +"-0.1743,-0.1635,-0.1499,-0.1225,-0.0854,-0.0131,0.1167",\ +"-0.1775,-0.1668,-0.1531,-0.1258,-0.0887,-0.0164,0.1135",\ +"-0.1900,-0.1792,-0.1656,-0.1382,-0.1011,-0.0288,0.1010",\ +"-0.2076,-0.1968,-0.1832,-0.1558,-0.1187,-0.0464,0.0834",\ +"-0.2351,-0.2243,-0.2107,-0.1833,-0.1462,-0.0739,0.0559"); + } + } + + + timing() { + timing_type : hold_rising; + related_pin : "A_CLK"; + when : "(A_WEN & A_MEN)" + sdf_cond : "A_RW_ACCESS" + + rise_constraint("SIG2SRAM_constraint_template") { + index_1("0.0040,0.0176,0.0344,0.0656,0.1120,0.2016,0.3800"); + index_2("0.0040,0.0176,0.0344,0.0656,0.1120,0.2016,0.3800"); + values ("0.2950,0.2833,0.2686,0.2423,0.2022,0.1309,-0.0058",\ +"0.2989,0.2872,0.2725,0.2462,0.2061,0.1348,-0.0019",\ +"0.3027,0.2910,0.2763,0.2499,0.2099,0.1386,0.0019",\ +"0.3059,0.2942,0.2796,0.2532,0.2132,0.1419,0.0052",\ +"0.3184,0.3067,0.2920,0.2656,0.2256,0.1543,0.0176",\ +"0.3360,0.3243,0.3096,0.2833,0.2432,0.1719,0.0352",\ +"0.3635,0.3518,0.3371,0.3108,0.2707,0.1994,0.0627"); + } + + fall_constraint("SIG2SRAM_constraint_template") { + index_1("0.0040,0.0176,0.0344,0.0656,0.1120,0.2016,0.3800"); + index_2("0.0040,0.0176,0.0344,0.0656,0.1120,0.2016,0.3800"); + values ("0.2667,0.2569,0.2423,0.2159,0.1788,0.1055,-0.0224",\ +"0.2706,0.2608,0.2462,0.2198,0.1827,0.1094,-0.0185",\ +"0.2744,0.2646,0.2499,0.2236,0.1865,0.1132,-0.0147",\ +"0.2776,0.2678,0.2532,0.2268,0.1897,0.1165,-0.0114",\ +"0.2901,0.2803,0.2656,0.2393,0.2022,0.1289,0.0010",\ +"0.3077,0.2979,0.2833,0.2569,0.2198,0.1465,0.0186",\ +"0.3352,0.3254,0.3108,0.2844,0.2473,0.1740,0.0461"); + } + } +} + pin(A_CLK) { + direction : input; + capacitance : 0.00389386; + max_transition : "0.38"; + clock : "true" ; + pin_func_type : active_rising ; + + timing () { + timing_type : "min_pulse_width"; + related_pin : "A_CLK"; + rise_constraint("CLKTRAN_constraint_template") { + index_1("0.004,0.38"); + values("0.12,0.12"); + } + } + + related_power_pin : VDD; + related_ground_pin : VSS; + + internal_power() { + when : "!A_MEN & !A_WEN & !A_REN"; + rise_power("scalar"){ + values (0); + } + fall_power("scalar"){ + values (0); + } + } + internal_power() { + when : "!A_MEN & A_WEN & !A_REN"; + rise_power("scalar"){ + values (0.6697); + } + fall_power("scalar"){ + values (0); + } + } + internal_power() { + when : "A_MEN & A_WEN & !A_REN"; + rise_power("scalar"){ + values (29.9728); + } + fall_power("scalar"){ + values (0); + } + } + internal_power() { + when : "A_MEN & A_WEN & A_REN"; + rise_power("scalar"){ + values (30.7463); + } + fall_power("scalar"){ + values (0); + } + } + internal_power() { + when : "A_MEN & !A_WEN & A_REN"; + rise_power("scalar"){ + values (24.5331); + } + fall_power("scalar"){ + values (0); + } + } + internal_power() { + when : "!A_MEN & !A_WEN & A_REN"; + rise_power("scalar"){ + values (0.4084); + } + fall_power("scalar"){ + values (0); + } + } + internal_power() { + when : "!A_MEN & A_WEN & A_REN"; + rise_power("scalar"){ + values (1.0137); + } + fall_power("scalar"){ + values (0); + } + } + internal_power() { + when : "A_MEN & !A_WEN & !A_REN"; + rise_power("scalar"){ + values (0); + } + fall_power("scalar"){ + values (0); + } + } + } + bus(A_DIN) { + bus_type : D_15_0; + direction : input ; + capacitance : 0.00387207 ; + memory_write() { + address : A_ADDR ; + clocked_on : A_CLK; + } + + max_transition : "0.38" ; + pin(A_DIN[15:0]) { + related_power_pin : VDD; + related_ground_pin : VSS; + internal_power() { + when : "A_MEN"; + rise_power("scalar"){ + values (0.0757); + } + fall_power("scalar"){ + values (0.0696); + } + } + internal_power() { + when : "!A_MEN"; + rise_power("scalar"){ + values (0.0977); + } + fall_power("scalar"){ + values (0.0801); + } + } + } + timing() { + timing_type : setup_rising; + related_pin : "A_CLK"; + when : "(A_WEN & A_MEN)"; + sdf_cond : "A_W_ACCESS"; + + rise_constraint("SIG2SRAM_constraint_template") { + index_1("0.0040,0.0176,0.0344,0.0656,0.1120,0.2016,0.3800"); + index_2("0.0040,0.0176,0.0344,0.0656,0.1120,0.2016,0.3800"); + values ("-0.1890,-0.1783,-0.1627,-0.1363,-0.0963,-0.0260,0.1088",\ +"-0.1929,-0.1822,-0.1666,-0.1402,-0.1002,-0.0298,0.1049",\ +"-0.1967,-0.1860,-0.1704,-0.1440,-0.1040,-0.0336,0.1011",\ +"-0.2000,-0.1892,-0.1736,-0.1472,-0.1072,-0.0369,0.0979",\ +"-0.2124,-0.2017,-0.1861,-0.1597,-0.1196,-0.0493,0.0854",\ +"-0.2300,-0.2193,-0.2037,-0.1773,-0.1373,-0.0669,0.0678",\ +"-0.2576,-0.2468,-0.2312,-0.2048,-0.1648,-0.0945,0.0403"); + } + + fall_constraint("SIG2SRAM_constraint_template") { + index_1("0.0040,0.0176,0.0344,0.0656,0.1120,0.2016,0.3800"); + index_2("0.0040,0.0176,0.0344,0.0656,0.1120,0.2016,0.3800"); + values ("-0.1666,-0.1558,-0.1422,-0.1148,-0.0777,-0.0055,0.1244",\ +"-0.1705,-0.1597,-0.1461,-0.1187,-0.0816,-0.0093,0.1205",\ +"-0.1743,-0.1635,-0.1499,-0.1225,-0.0854,-0.0131,0.1167",\ +"-0.1775,-0.1668,-0.1531,-0.1258,-0.0887,-0.0164,0.1135",\ +"-0.1900,-0.1792,-0.1656,-0.1382,-0.1011,-0.0288,0.1010",\ +"-0.2076,-0.1968,-0.1832,-0.1558,-0.1187,-0.0464,0.0834",\ +"-0.2351,-0.2243,-0.2107,-0.1833,-0.1462,-0.0739,0.0559"); + } + } + + timing() { + timing_type : hold_rising; + related_pin : "A_CLK"; + when : "(A_WEN & A_MEN)"; + sdf_cond : "A_W_ACCESS"; + + rise_constraint("SIG2SRAM_constraint_template") { + index_1("0.0040,0.0176,0.0344,0.0656,0.1120,0.2016,0.3800"); + index_2("0.0040,0.0176,0.0344,0.0656,0.1120,0.2016,0.3800"); + values ("0.2950,0.2833,0.2686,0.2423,0.2022,0.1309,-0.0058",\ +"0.2989,0.2872,0.2725,0.2462,0.2061,0.1348,-0.0019",\ +"0.3027,0.2910,0.2763,0.2499,0.2099,0.1386,0.0019",\ +"0.3059,0.2942,0.2796,0.2532,0.2132,0.1419,0.0052",\ +"0.3184,0.3067,0.2920,0.2656,0.2256,0.1543,0.0176",\ +"0.3360,0.3243,0.3096,0.2833,0.2432,0.1719,0.0352",\ +"0.3635,0.3518,0.3371,0.3108,0.2707,0.1994,0.0627"); + } + + fall_constraint("SIG2SRAM_constraint_template") { + index_1("0.0040,0.0176,0.0344,0.0656,0.1120,0.2016,0.3800"); + index_2("0.0040,0.0176,0.0344,0.0656,0.1120,0.2016,0.3800"); + values ("0.2667,0.2569,0.2423,0.2159,0.1788,0.1055,-0.0224",\ +"0.2706,0.2608,0.2462,0.2198,0.1827,0.1094,-0.0185",\ +"0.2744,0.2646,0.2499,0.2236,0.1865,0.1132,-0.0147",\ +"0.2776,0.2678,0.2532,0.2268,0.1897,0.1165,-0.0114",\ +"0.2901,0.2803,0.2656,0.2393,0.2022,0.1289,0.0010",\ +"0.3077,0.2979,0.2833,0.2569,0.2198,0.1465,0.0186",\ +"0.3352,0.3254,0.3108,0.2844,0.2473,0.1740,0.0461"); + } + } + } + + pin(A_BIST_EN) { + direction : input ; + capacitance : 0.00421562 ; + max_transition : "1" ; + related_power_pin : VDD; + related_ground_pin : VSS; + internal_power() { + rise_power("scalar") { + values (0); + } + fall_power("scalar") { + values (0); + } + } + } + +bus(A_BIST_ADDR) { + bus_type : A_8_0; + direction : input ; + capacitance : 0.00691085 ; + pin(A_BIST_ADDR[0]) { + capacitance : 0.00562034 ; + } + pin(A_BIST_ADDR[1]) { + capacitance : 0.00462655 ; + } + pin(A_BIST_ADDR[2]) { + capacitance : 0.00594295 ; + } + pin(A_BIST_ADDR[3]) { + capacitance : 0.00723434 ; + } + pin(A_BIST_ADDR[4]) { + capacitance : 0.00481603 ; + } + pin(A_BIST_ADDR[5]) { + capacitance : 0.00868123 ; + } + pin(A_BIST_ADDR[6]) { + capacitance : 0.010187 ; + } + pin(A_BIST_ADDR[7]) { + capacitance : 0.00734489 ; + } + max_transition : "0.38" ; + pin(A_BIST_ADDR[8:0]) { + related_power_pin : VDD; + related_ground_pin : VSS; + internal_power() { + when : "A_BIST_MEN"; + rise_power("scalar"){ + values (0.0125); + } + fall_power("scalar"){ + values (0.0025); + } + } + internal_power() { + when : "!A_BIST_MEN"; + rise_power("scalar"){ + values (0.0288); + } + fall_power("scalar"){ + values (0.0013); + } + } + } + timing() { + timing_type : setup_rising; + related_pin : "A_BIST_CLK"; + when : "((A_BIST_WEN | A_BIST_REN)& A_BIST_MEN)" + sdf_cond : "A_BIST_RW_ACCESS" + + rise_constraint("SIG2SRAM_constraint_template") { + index_1("0.0040,0.0176,0.0344,0.0656,0.1120,0.2016,0.3800"); + index_2("0.0040,0.0176,0.0344,0.0656,0.1120,0.2016,0.3800"); + values ("-0.2371,-0.2215,-0.2098,-0.1824,-0.1434,-0.0691,0.0676",\ +"-0.2449,-0.2332,-0.2176,-0.1902,-0.1551,-0.0770,0.0559",\ +"-0.2605,-0.2488,-0.2332,-0.2059,-0.1707,-0.0965,0.0441",\ +"-0.2879,-0.2723,-0.2605,-0.2332,-0.1941,-0.1199,0.0168",\ +"-0.3230,-0.3113,-0.2996,-0.2723,-0.2332,-0.1590,-0.0184",\ +"-0.4012,-0.3895,-0.3738,-0.3465,-0.3074,-0.2332,-0.0965",\ +"-0.5379,-0.5262,-0.5105,-0.4832,-0.4480,-0.3699,-0.2332"); + } + + fall_constraint("SIG2SRAM_constraint_template") { + index_1("0.0040,0.0176,0.0344,0.0656,0.1120,0.2016,0.3800"); + index_2("0.0040,0.0176,0.0344,0.0656,0.1120,0.2016,0.3800"); + values ("-0.1785,-0.1707,-0.1551,-0.1277,-0.0887,-0.0184,0.1145",\ +"-0.1902,-0.1785,-0.1629,-0.1355,-0.1004,-0.0262,0.1027",\ +"-0.2059,-0.1941,-0.1785,-0.1512,-0.1160,-0.0418,0.0871",\ +"-0.2293,-0.2176,-0.2059,-0.1785,-0.1434,-0.0691,0.0598",\ +"-0.2684,-0.2566,-0.2449,-0.2176,-0.1824,-0.1082,0.0207",\ +"-0.3465,-0.3348,-0.3191,-0.2918,-0.2566,-0.1824,-0.0535",\ +"-0.4832,-0.4715,-0.4559,-0.4324,-0.3934,-0.3191,-0.1902"); + } + } + + + timing() { + timing_type : hold_rising; + related_pin : "A_BIST_CLK"; + when : "((A_BIST_WEN | A_BIST_REN)& A_BIST_MEN)" + sdf_cond : "A_BIST_RW_ACCESS" + + rise_constraint("SIG2SRAM_constraint_template") { + index_1("0.0040,0.0176,0.0344,0.0656,0.1120,0.2016,0.3800"); + index_2("0.0040,0.0176,0.0344,0.0656,0.1120,0.2016,0.3800"); + values ("0.3410,0.3293,0.3137,0.2863,0.2473,0.1730,0.0324",\ +"0.3488,0.3371,0.3215,0.2941,0.2590,0.1809,0.0480",\ +"0.3684,0.3527,0.3371,0.3098,0.2746,0.1965,0.0598",\ +"0.3918,0.3762,0.3645,0.3371,0.2980,0.2238,0.0871",\ +"0.4309,0.4152,0.4035,0.3762,0.3371,0.2629,0.1223",\ +"0.5051,0.4934,0.4777,0.4504,0.4113,0.3371,0.1965",\ +"0.6418,0.6262,0.6145,0.5871,0.5520,0.4738,0.3332"); + } + + fall_constraint("SIG2SRAM_constraint_template") { + index_1("0.0040,0.0176,0.0344,0.0656,0.1120,0.2016,0.3800"); + index_2("0.0040,0.0176,0.0344,0.0656,0.1120,0.2016,0.3800"); + values ("0.2824,0.2707,0.2551,0.2277,0.1926,0.1184,-0.0105",\ +"0.2902,0.2785,0.2668,0.2395,0.2043,0.1301,0.0012",\ +"0.3059,0.2941,0.2824,0.2551,0.2199,0.1457,0.0168",\ +"0.3332,0.3215,0.3059,0.2785,0.2434,0.1691,0.0402",\ +"0.3723,0.3605,0.3449,0.3176,0.2824,0.2121,0.0793",\ +"0.4465,0.4348,0.4230,0.3918,0.3566,0.2824,0.1535",\ +"0.5832,0.5715,0.5598,0.5324,0.4934,0.4191,0.2902"); + } + } +} +pin(A_BIST_WEN) { + direction : input ; + capacitance : 0.00341384 ; + max_transition : "0.38" ; + related_power_pin : VDD; + related_ground_pin : VSS; + internal_power() { + when : "A_BIST_MEN"; + rise_power("scalar"){ + values (0.0076); + } + fall_power("scalar"){ + values (0.0137); + } + } + internal_power() { + when : "!A_BIST_MEN"; + rise_power("scalar"){ + values (0.0073); + } + fall_power("scalar"){ + values (0.0261); + } + } + timing() { + timing_type : setup_rising; + related_pin : "A_BIST_CLK"; + when : "A_BIST_MEN" + sdf_cond : "A_BIST_MEN" + + rise_constraint("SIG2SRAM_constraint_template") { + index_1("0.0040,0.0176,0.0344,0.0656,0.1120,0.2016,0.3800"); + index_2("0.0040,0.0176,0.0344,0.0656,0.1120,0.2016,0.3800"); + values ("0.1418,0.1496,0.1652,0.1887,0.2316,0.3059,0.4465",\ +"0.1301,0.1379,0.1535,0.1809,0.2199,0.2941,0.4348",\ +"0.1145,0.1262,0.1379,0.1652,0.2043,0.2785,0.4191",\ +"0.0871,0.0949,0.1105,0.1379,0.1770,0.2512,0.3879",\ +"0.0480,0.0598,0.0754,0.0988,0.1379,0.2082,0.3527",\ +"-0.0262,-0.0145,0.0012,0.0246,0.0676,0.1379,0.2785",\ +"-0.1668,-0.1551,-0.1395,-0.1121,-0.0730,0.0012,0.1418"); + } + + fall_constraint("SIG2SRAM_constraint_template") { + index_1("0.0040,0.0176,0.0344,0.0656,0.1120,0.2016,0.3800"); + index_2("0.0040,0.0176,0.0344,0.0656,0.1120,0.2016,0.3800"); + values ("0.2082,0.2160,0.2316,0.2590,0.2941,0.3684,0.5012",\ +"0.1926,0.2043,0.2199,0.2473,0.2824,0.3566,0.4895",\ +"0.1770,0.1887,0.2043,0.2316,0.2668,0.3410,0.4777",\ +"0.1535,0.1652,0.1770,0.2043,0.2395,0.3137,0.4504",\ +"0.1145,0.1262,0.1379,0.1652,0.2043,0.2746,0.4113",\ +"0.0402,0.0520,0.0676,0.0910,0.1262,0.2004,0.3332",\ +"-0.0965,-0.0848,-0.0730,-0.0457,-0.0066,0.0637,0.2004"); + } + } + + + timing() { + timing_type : hold_rising; + related_pin : "A_BIST_CLK"; + when : "A_BIST_MEN" + sdf_cond : "A_BIST_MEN" + + rise_constraint("SIG2SRAM_constraint_template") { + index_1("0.0040,0.0176,0.0344,0.0656,0.1120,0.2016,0.3800"); + index_2("0.0040,0.0176,0.0344,0.0656,0.1120,0.2016,0.3800"); + values ("0.1770,0.1652,0.1496,0.1223,0.0793,0.0090,-0.1316",\ +"0.1848,0.1730,0.1574,0.1301,0.0910,0.0168,-0.1199",\ +"0.2004,0.1887,0.1770,0.1496,0.1066,0.0363,-0.1043",\ +"0.2277,0.2160,0.2004,0.1730,0.1340,0.0598,-0.0809",\ +"0.2668,0.2551,0.2395,0.2121,0.1730,0.0988,-0.0418",\ +"0.3410,0.3293,0.3137,0.2863,0.2434,0.1730,0.0324",\ +"0.4816,0.4699,0.4543,0.4230,0.3801,0.3098,0.1730"); + } + + fall_constraint("SIG2SRAM_constraint_template") { + index_1("0.0040,0.0176,0.0344,0.0656,0.1120,0.2016,0.3800"); + index_2("0.0040,0.0176,0.0344,0.0656,0.1120,0.2016,0.3800"); + values ("0.1613,0.1496,0.1379,0.1066,0.0715,0.0012,-0.1355",\ +"0.1730,0.1613,0.1457,0.1184,0.0832,0.0129,-0.1238",\ +"0.1887,0.1770,0.1613,0.1340,0.0988,0.0246,-0.1121",\ +"0.2121,0.2043,0.1887,0.1613,0.1223,0.0520,-0.0848",\ +"0.2512,0.2434,0.2277,0.2004,0.1613,0.0910,-0.0457",\ +"0.3254,0.3176,0.3020,0.2746,0.2355,0.1652,0.0324",\ +"0.4660,0.4543,0.4387,0.4113,0.3723,0.3020,0.1691"); + } + } + } +pin(A_BIST_REN) { + direction : input ; + capacitance : 0.00390661 ; + max_transition : "0.38" ; + related_power_pin : VDD; + related_ground_pin : VSS; + internal_power() { + when : "A_BIST_MEN"; + rise_power("scalar"){ + values (0.0069); + } + fall_power("scalar"){ + values (0.0122); + } + } + internal_power() { + when : "!A_BIST_MEN"; + rise_power("scalar"){ + values (0.0243); + } + fall_power("scalar"){ + values (0.0202); + } + } + timing() { + timing_type : setup_rising; + related_pin : "A_BIST_CLK"; + when : "A_BIST_MEN" + sdf_cond : "A_BIST_MEN" + + rise_constraint("SIG2SRAM_constraint_template") { + index_1("0.0040,0.0176,0.0344,0.0656,0.1120,0.2016,0.3800"); + index_2("0.0040,0.0176,0.0344,0.0656,0.1120,0.2016,0.3800"); + values ("-0.0027,0.0090,0.0246,0.0520,0.0910,0.1613,0.3020",\ +"-0.0105,0.0012,0.0129,0.0363,0.0793,0.1535,0.2902",\ +"-0.0262,-0.0145,-0.0027,0.0246,0.0637,0.1379,0.2785",\ +"-0.0535,-0.0418,-0.0262,0.0012,0.0363,0.1105,0.2512",\ +"-0.0926,-0.0809,-0.0652,-0.0418,-0.0027,0.0715,0.2121",\ +"-0.1668,-0.1551,-0.1395,-0.1082,-0.0770,-0.0027,0.1379",\ +"-0.3035,-0.2918,-0.2762,-0.2488,-0.2137,-0.1434,-0.0027"); + } + + fall_constraint("SIG2SRAM_constraint_template") { + index_1("0.0040,0.0176,0.0344,0.0656,0.1120,0.2016,0.3800"); + index_2("0.0040,0.0176,0.0344,0.0656,0.1120,0.2016,0.3800"); + values ("0.0832,0.0949,0.1105,0.1379,0.1730,0.2473,0.3801",\ +"0.0754,0.0832,0.0988,0.1223,0.1613,0.2355,0.3684",\ +"0.0598,0.0676,0.0832,0.1066,0.1457,0.2121,0.3527",\ +"0.0324,0.0441,0.0598,0.0871,0.1223,0.1926,0.3293",\ +"-0.0066,0.0051,0.0168,0.0480,0.0832,0.1535,0.2902",\ +"-0.0809,-0.0691,-0.0574,-0.0301,0.0090,0.0832,0.2121",\ +"-0.2176,-0.2059,-0.1941,-0.1668,-0.1277,-0.0574,0.0793"); + } + } + + + timing() { + timing_type : hold_rising; + related_pin : "A_BIST_CLK"; + when : "A_BIST_MEN" + sdf_cond : "A_BIST_MEN" + + rise_constraint("SIG2SRAM_constraint_template") { + index_1("0.0040,0.0176,0.0344,0.0656,0.1120,0.2016,0.3800"); + index_2("0.0040,0.0176,0.0344,0.0656,0.1120,0.2016,0.3800"); + values ("0.1887,0.1770,0.1613,0.1340,0.0949,0.0207,-0.1160",\ +"0.1965,0.1848,0.1730,0.1457,0.1027,0.0324,-0.1082",\ +"0.2160,0.2004,0.1887,0.1613,0.1184,0.0480,-0.0926",\ +"0.2395,0.2277,0.2121,0.1848,0.1457,0.0715,-0.0652",\ +"0.2785,0.2668,0.2512,0.2238,0.1848,0.1105,-0.0262",\ +"0.3527,0.3410,0.3254,0.2980,0.2551,0.1848,0.0480",\ +"0.4934,0.4816,0.4660,0.4387,0.3957,0.3254,0.1887"); + } + + fall_constraint("SIG2SRAM_constraint_template") { + index_1("0.0040,0.0176,0.0344,0.0656,0.1120,0.2016,0.3800"); + index_2("0.0040,0.0176,0.0344,0.0656,0.1120,0.2016,0.3800"); + values ("0.1730,0.1613,0.1496,0.1184,0.0793,0.0129,-0.1238",\ +"0.1848,0.1730,0.1574,0.1301,0.0910,0.0207,-0.1121",\ +"0.2004,0.1887,0.1730,0.1457,0.1066,0.0363,-0.1004",\ +"0.2238,0.2121,0.2004,0.1691,0.1340,0.0598,-0.0730",\ +"0.2629,0.2512,0.2395,0.2121,0.1691,0.0988,-0.0340",\ +"0.3371,0.3254,0.3137,0.2863,0.2434,0.1730,0.0402",\ +"0.4777,0.4660,0.4504,0.4230,0.3840,0.3137,0.1809"); + } + } + } +pin(A_BIST_MEN) { + direction : input ; + capacitance : 0.00326046 ; + max_transition : "0.38" ; + related_power_pin : VDD; + related_ground_pin : VSS; + internal_power() { + rise_power("scalar"){ + values (0.1674); + } + fall_power("scalar"){ + values (0.0108); + } + } + timing() { + timing_type : setup_rising; + related_pin : "A_BIST_CLK"; + + rise_constraint("SIG2SRAM_constraint_template") { + index_1("0.0040,0.0176,0.0344,0.0656,0.1120,0.2016,0.3800"); + index_2("0.0040,0.0176,0.0344,0.0656,0.1120,0.2016,0.3800"); + values ("0.1418,0.1496,0.1652,0.1926,0.2316,0.3059,0.4465",\ +"0.1301,0.1379,0.1535,0.1809,0.2199,0.2941,0.4348",\ +"0.1145,0.1262,0.1418,0.1652,0.2043,0.2785,0.4191",\ +"0.0871,0.0949,0.1105,0.1379,0.1770,0.2512,0.3879",\ +"0.0480,0.0598,0.0754,0.0988,0.1379,0.2082,0.3488",\ +"-0.0262,-0.0145,0.0012,0.0285,0.0676,0.1379,0.2785",\ +"-0.1668,-0.1551,-0.1395,-0.1121,-0.0730,0.0012,0.1379"); + } + + fall_constraint("SIG2SRAM_constraint_template") { + index_1("0.0040,0.0176,0.0344,0.0656,0.1120,0.2016,0.3800"); + index_2("0.0040,0.0176,0.0344,0.0656,0.1120,0.2016,0.3800"); + values ("0.2082,0.2199,0.2316,0.2590,0.2980,0.3723,0.5051",\ +"0.1965,0.2082,0.2199,0.2473,0.2863,0.3605,0.4934",\ +"0.1809,0.1926,0.2043,0.2316,0.2707,0.3449,0.4777",\ +"0.1574,0.1691,0.1809,0.2082,0.2434,0.3176,0.4543",\ +"0.1145,0.1262,0.1418,0.1691,0.2043,0.2785,0.4113",\ +"0.0441,0.0559,0.0676,0.0949,0.1301,0.2004,0.3332",\ +"-0.0965,-0.0848,-0.0691,-0.0418,-0.0066,0.0676,0.2004"); + } + } + + + timing() { + timing_type : hold_rising; + related_pin : "A_BIST_CLK"; + + rise_constraint("SIG2SRAM_constraint_template") { + index_1("0.0040,0.0176,0.0344,0.0656,0.1120,0.2016,0.3800"); + index_2("0.0040,0.0176,0.0344,0.0656,0.1120,0.2016,0.3800"); + values ("0.1770,0.1652,0.1535,0.1262,0.0832,0.0129,-0.1277",\ +"0.1887,0.1770,0.1613,0.1340,0.0949,0.0207,-0.1199",\ +"0.2043,0.1926,0.1770,0.1496,0.1105,0.0363,-0.1043",\ +"0.2277,0.2160,0.2043,0.1770,0.1379,0.0598,-0.0770",\ +"0.2668,0.2551,0.2434,0.2160,0.1730,0.0988,-0.0379",\ +"0.3449,0.3332,0.3176,0.2902,0.2473,0.1730,0.0363",\ +"0.4816,0.4699,0.4543,0.4270,0.3840,0.3098,0.1770"); + } + + fall_constraint("SIG2SRAM_constraint_template") { + index_1("0.0040,0.0176,0.0344,0.0656,0.1120,0.2016,0.3800"); + index_2("0.0040,0.0176,0.0344,0.0656,0.1120,0.2016,0.3800"); + values ("0.1613,0.1496,0.1379,0.1105,0.0715,0.0012,-0.1355",\ +"0.1730,0.1613,0.1496,0.1184,0.0832,0.0129,-0.1238",\ +"0.1887,0.1770,0.1652,0.1340,0.0988,0.0285,-0.1121",\ +"0.2121,0.2043,0.1887,0.1613,0.1223,0.0520,-0.0848",\ +"0.2551,0.2434,0.2277,0.2004,0.1613,0.0910,-0.0418",\ +"0.3293,0.3176,0.3020,0.2746,0.2395,0.1652,0.0324",\ +"0.4660,0.4543,0.4426,0.4113,0.3762,0.3020,0.1691"); + } + } + } +bus(A_BIST_BM) { + bus_type : D_15_0; + direction : input ; + capacitance : 0.00253457 ; + max_transition : "0.38" ; + pin(A_BIST_BM[15:0]) { + related_power_pin : VDD; + related_ground_pin : VSS; + internal_power() { + when : "A_BIST_MEN"; + rise_power("scalar"){ + values (0.0757); + } + fall_power("scalar"){ + values (0.0696); + } + } + internal_power() { + when : "!A_BIST_MEN"; + rise_power("scalar"){ + values (0.0977); + } + fall_power("scalar"){ + values (0.0801); + } + } + } + timing() { + timing_type : setup_rising; + related_pin : "A_BIST_CLK"; + when : "(A_BIST_WEN & A_BIST_MEN)" + sdf_cond : "A_BIST_RW_ACCESS" + + rise_constraint("SIG2SRAM_constraint_template") { + index_1("0.0040,0.0176,0.0344,0.0656,0.1120,0.2016,0.3800"); + index_2("0.0040,0.0176,0.0344,0.0656,0.1120,0.2016,0.3800"); + values ("-0.1890,-0.1783,-0.1627,-0.1363,-0.0963,-0.0260,0.1088",\ +"-0.1929,-0.1822,-0.1666,-0.1402,-0.1002,-0.0298,0.1049",\ +"-0.1967,-0.1860,-0.1704,-0.1440,-0.1040,-0.0336,0.1011",\ +"-0.2000,-0.1892,-0.1736,-0.1472,-0.1072,-0.0369,0.0979",\ +"-0.2124,-0.2017,-0.1861,-0.1597,-0.1196,-0.0493,0.0854",\ +"-0.2300,-0.2193,-0.2037,-0.1773,-0.1373,-0.0669,0.0678",\ +"-0.2576,-0.2468,-0.2312,-0.2048,-0.1648,-0.0945,0.0403"); + } + + fall_constraint("SIG2SRAM_constraint_template") { + index_1("0.0040,0.0176,0.0344,0.0656,0.1120,0.2016,0.3800"); + index_2("0.0040,0.0176,0.0344,0.0656,0.1120,0.2016,0.3800"); + values ("-0.1666,-0.1558,-0.1422,-0.1148,-0.0777,-0.0055,0.1244",\ +"-0.1705,-0.1597,-0.1461,-0.1187,-0.0816,-0.0093,0.1205",\ +"-0.1743,-0.1635,-0.1499,-0.1225,-0.0854,-0.0131,0.1167",\ +"-0.1775,-0.1668,-0.1531,-0.1258,-0.0887,-0.0164,0.1135",\ +"-0.1900,-0.1792,-0.1656,-0.1382,-0.1011,-0.0288,0.1010",\ +"-0.2076,-0.1968,-0.1832,-0.1558,-0.1187,-0.0464,0.0834",\ +"-0.2351,-0.2243,-0.2107,-0.1833,-0.1462,-0.0739,0.0559"); + } + } + + + timing() { + timing_type : hold_rising; + related_pin : "A_BIST_CLK"; + when : "(A_BIST_WEN & A_BIST_MEN)" + sdf_cond : "A_BIST_RW_ACCESS" + + rise_constraint("SIG2SRAM_constraint_template") { + index_1("0.0040,0.0176,0.0344,0.0656,0.1120,0.2016,0.3800"); + index_2("0.0040,0.0176,0.0344,0.0656,0.1120,0.2016,0.3800"); + values ("0.2950,0.2833,0.2686,0.2423,0.2022,0.1309,-0.0058",\ +"0.2989,0.2872,0.2725,0.2462,0.2061,0.1348,-0.0019",\ +"0.3027,0.2910,0.2763,0.2499,0.2099,0.1386,0.0019",\ +"0.3059,0.2942,0.2796,0.2532,0.2132,0.1419,0.0052",\ +"0.3184,0.3067,0.2920,0.2656,0.2256,0.1543,0.0176",\ +"0.3360,0.3243,0.3096,0.2833,0.2432,0.1719,0.0352",\ +"0.3635,0.3518,0.3371,0.3108,0.2707,0.1994,0.0627"); + } + + fall_constraint("SIG2SRAM_constraint_template") { + index_1("0.0040,0.0176,0.0344,0.0656,0.1120,0.2016,0.3800"); + index_2("0.0040,0.0176,0.0344,0.0656,0.1120,0.2016,0.3800"); + values ("0.2667,0.2569,0.2423,0.2159,0.1788,0.1055,-0.0224",\ +"0.2706,0.2608,0.2462,0.2198,0.1827,0.1094,-0.0185",\ +"0.2744,0.2646,0.2499,0.2236,0.1865,0.1132,-0.0147",\ +"0.2776,0.2678,0.2532,0.2268,0.1897,0.1165,-0.0114",\ +"0.2901,0.2803,0.2656,0.2393,0.2022,0.1289,0.0010",\ +"0.3077,0.2979,0.2833,0.2569,0.2198,0.1465,0.0186",\ +"0.3352,0.3254,0.3108,0.2844,0.2473,0.1740,0.0461"); + } + } +} + pin(A_BIST_CLK) { + direction : input; + capacitance : 0.00389386; + max_transition : "0.38"; + clock : "true" ; + pin_func_type : active_rising ; + + timing () { + timing_type : "min_pulse_width"; + related_pin : "A_BIST_CLK"; + rise_constraint("CLKTRAN_constraint_template") { + index_1("0.004,0.38"); + values("0.12,0.12"); + } + } + + related_power_pin : VDD; + related_ground_pin : VSS; + + internal_power() { + when : "!A_BIST_MEN & !A_BIST_WEN & !A_BIST_REN"; + rise_power("scalar"){ + values (0); + } + fall_power("scalar"){ + values (0); + } + } + internal_power() { + when : "!A_BIST_MEN & A_BIST_WEN & !A_BIST_REN"; + rise_power("scalar"){ + values (0.6697); + } + fall_power("scalar"){ + values (0); + } + } + internal_power() { + when : "A_BIST_MEN & A_BIST_WEN & !A_BIST_REN"; + rise_power("scalar"){ + values (29.9728); + } + fall_power("scalar"){ + values (0); + } + } + internal_power() { + when : "A_BIST_MEN & A_BIST_WEN & A_BIST_REN"; + rise_power("scalar"){ + values (30.7463); + } + fall_power("scalar"){ + values (0); + } + } + internal_power() { + when : "A_BIST_MEN & !A_BIST_WEN & A_BIST_REN"; + rise_power("scalar"){ + values (24.5331); + } + fall_power("scalar"){ + values (0); + } + } + internal_power() { + when : "!A_BIST_MEN & !A_BIST_WEN & A_BIST_REN"; + rise_power("scalar"){ + values (0.4084); + } + fall_power("scalar"){ + values (0); + } + } + internal_power() { + when : "!A_BIST_MEN & A_BIST_WEN & A_BIST_REN"; + rise_power("scalar"){ + values (1.0137); + } + fall_power("scalar"){ + values (0); + } + } + internal_power() { + when : "A_BIST_MEN & !A_BIST_WEN & !A_BIST_REN"; + rise_power("scalar"){ + values (0); + } + fall_power("scalar"){ + values (0); + } + } + } + bus(A_BIST_DIN) { + bus_type : D_15_0; + direction : input ; + capacitance : 0.00252927 ; + memory_write() { + address : A_BIST_ADDR ; + clocked_on : A_BIST_CLK; + } + + max_transition : "0.38" ; + pin(A_BIST_DIN[15:0]) { + related_power_pin : VDD; + related_ground_pin : VSS; + internal_power() { + when : "A_BIST_MEN"; + rise_power("scalar"){ + values (0.0757); + } + fall_power("scalar"){ + values (0.0696); + } + } + internal_power() { + when : "!A_BIST_MEN"; + rise_power("scalar"){ + values (0.0977); + } + fall_power("scalar"){ + values (0.0801); + } + } + } + timing() { + timing_type : setup_rising; + related_pin : "A_BIST_CLK"; + when : "(A_BIST_WEN & A_BIST_MEN)"; + sdf_cond : "A_BIST_W_ACCESS"; + + rise_constraint("SIG2SRAM_constraint_template") { + index_1("0.0040,0.0176,0.0344,0.0656,0.1120,0.2016,0.3800"); + index_2("0.0040,0.0176,0.0344,0.0656,0.1120,0.2016,0.3800"); + values ("-0.1890,-0.1783,-0.1627,-0.1363,-0.0963,-0.0260,0.1088",\ +"-0.1929,-0.1822,-0.1666,-0.1402,-0.1002,-0.0298,0.1049",\ +"-0.1967,-0.1860,-0.1704,-0.1440,-0.1040,-0.0336,0.1011",\ +"-0.2000,-0.1892,-0.1736,-0.1472,-0.1072,-0.0369,0.0979",\ +"-0.2124,-0.2017,-0.1861,-0.1597,-0.1196,-0.0493,0.0854",\ +"-0.2300,-0.2193,-0.2037,-0.1773,-0.1373,-0.0669,0.0678",\ +"-0.2576,-0.2468,-0.2312,-0.2048,-0.1648,-0.0945,0.0403"); + } + + fall_constraint("SIG2SRAM_constraint_template") { + index_1("0.0040,0.0176,0.0344,0.0656,0.1120,0.2016,0.3800"); + index_2("0.0040,0.0176,0.0344,0.0656,0.1120,0.2016,0.3800"); + values ("-0.1666,-0.1558,-0.1422,-0.1148,-0.0777,-0.0055,0.1244",\ +"-0.1705,-0.1597,-0.1461,-0.1187,-0.0816,-0.0093,0.1205",\ +"-0.1743,-0.1635,-0.1499,-0.1225,-0.0854,-0.0131,0.1167",\ +"-0.1775,-0.1668,-0.1531,-0.1258,-0.0887,-0.0164,0.1135",\ +"-0.1900,-0.1792,-0.1656,-0.1382,-0.1011,-0.0288,0.1010",\ +"-0.2076,-0.1968,-0.1832,-0.1558,-0.1187,-0.0464,0.0834",\ +"-0.2351,-0.2243,-0.2107,-0.1833,-0.1462,-0.0739,0.0559"); + } + } + + timing() { + timing_type : hold_rising; + related_pin : "A_BIST_CLK"; + when : "(A_BIST_WEN & A_BIST_MEN)"; + sdf_cond : "A_BIST_W_ACCESS"; + + rise_constraint("SIG2SRAM_constraint_template") { + index_1("0.0040,0.0176,0.0344,0.0656,0.1120,0.2016,0.3800"); + index_2("0.0040,0.0176,0.0344,0.0656,0.1120,0.2016,0.3800"); + values ("0.2950,0.2833,0.2686,0.2423,0.2022,0.1309,-0.0058",\ +"0.2989,0.2872,0.2725,0.2462,0.2061,0.1348,-0.0019",\ +"0.3027,0.2910,0.2763,0.2499,0.2099,0.1386,0.0019",\ +"0.3059,0.2942,0.2796,0.2532,0.2132,0.1419,0.0052",\ +"0.3184,0.3067,0.2920,0.2656,0.2256,0.1543,0.0176",\ +"0.3360,0.3243,0.3096,0.2833,0.2432,0.1719,0.0352",\ +"0.3635,0.3518,0.3371,0.3108,0.2707,0.1994,0.0627"); + } + + fall_constraint("SIG2SRAM_constraint_template") { + index_1("0.0040,0.0176,0.0344,0.0656,0.1120,0.2016,0.3800"); + index_2("0.0040,0.0176,0.0344,0.0656,0.1120,0.2016,0.3800"); + values ("0.2667,0.2569,0.2423,0.2159,0.1788,0.1055,-0.0224",\ +"0.2706,0.2608,0.2462,0.2198,0.1827,0.1094,-0.0185",\ +"0.2744,0.2646,0.2499,0.2236,0.1865,0.1132,-0.0147",\ +"0.2776,0.2678,0.2532,0.2268,0.1897,0.1165,-0.0114",\ +"0.2901,0.2803,0.2656,0.2393,0.2022,0.1289,0.0010",\ +"0.3077,0.2979,0.2833,0.2569,0.2198,0.1465,0.0186",\ +"0.3352,0.3254,0.3108,0.2844,0.2473,0.1740,0.0461"); + } + } + } + +bus(A_DOUT) { + + bus_type : D_15_0; + direction : output ; + capacitance : 0 ; + max_capacitance : 0.064 ; + memory_read() { + address : A_ADDR ; + } + pin(A_DOUT[15:0]) { + related_power_pin : VDD; + related_ground_pin : VSS; + internal_power() { + rise_power("scalar") { + values (0); + } + fall_power("scalar") { + values (0); + } + } + } + timing() { + related_pin : "A_CLK"; + timing_type : rising_edge ; + timing_sense : non_unate ; + + cell_rise(SIG2SRAM_delay_template) { + index_1("0.0040,0.0176,0.0344,0.0656,0.1120,0.2016,0.3800"); + index_2("0.0008,0.0014,0.0051,0.0100,0.0339,0.0640"); + values ("2.2920,2.2930,2.2978,2.3033,2.3242,2.3477",\ +"2.2984,2.2994,2.3042,2.3097,2.3306,2.3541",\ +"2.3000,2.3010,2.3058,2.3113,2.3322,2.3557",\ +"2.3043,2.3053,2.3101,2.3156,2.3366,2.3601",\ +"2.3175,2.3185,2.3233,2.3288,2.3497,2.3732",\ +"2.3360,2.3370,2.3418,2.3474,2.3683,2.3918",\ +"2.3625,2.3636,2.3684,2.3739,2.3948,2.4183"); + } + cell_fall(SIG2SRAM_delay_template) { + index_1("0.0040,0.0176,0.0344,0.0656,0.1120,0.2016,0.3800"); + index_2("0.0008,0.0014,0.0051,0.0100,0.0339,0.0640"); + values ("2.2577,2.2586,2.2626,2.2671,2.2842,2.3010",\ +"2.2641,2.2649,2.2690,2.2735,2.2906,2.3073",\ +"2.2657,2.2665,2.2706,2.2751,2.2922,2.3089",\ +"2.2700,2.2709,2.2749,2.2795,2.2965,2.3133",\ +"2.2832,2.2840,2.2881,2.2926,2.3097,2.3264",\ +"2.3017,2.3026,2.3066,2.3112,2.3283,2.3450",\ +"2.3283,2.3291,2.3332,2.3377,2.3548,2.3715"); + } + + rise_transition(SRAM_load_template) { + index_1("0.0008,0.0014,0.0051,0.0100,0.0339,0.0640"); + values ("0.0206,0.0210,0.0265,0.0323,0.0606,0.0955"); + } + fall_transition(SRAM_load_template) { + index_1("0.0008,0.0014,0.0051,0.0100,0.0339,0.0640"); + values ("0.0170,0.0177,0.0222,0.0270,0.0451,0.0644"); + } + } +} +cell_leakage_power : 234.7971; +} +} diff --git a/flow/platforms/ihp-sg13g2/lib/RM_IHPSG13_1P_512x16_c2_bm_bist_slow_1p08V_125C.lib b/flow/platforms/ihp-sg13g2/lib/RM_IHPSG13_1P_512x16_c2_bm_bist_slow_1p08V_125C.lib new file mode 100644 index 0000000000..60e2e9291d --- /dev/null +++ b/flow/platforms/ihp-sg13g2/lib/RM_IHPSG13_1P_512x16_c2_bm_bist_slow_1p08V_125C.lib @@ -0,0 +1,1519 @@ +/* ------------------------------------------------------*/ +/**/ +/* Copyright 2025 IHP PDK Authors*/ +/**/ +/* Licensed under the Apache License, Version 2.0 (the "License");*/ +/* you may not use this file except in compliance with the License.*/ +/* You may obtain a copy of the License at*/ +/* */ +/* https://www.apache.org/licenses/LICENSE-2.0*/ +/* */ +/* Unless required by applicable law or agreed to in writing, software*/ +/* distributed under the License is distributed on an "AS IS" BASIS,*/ +/* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.*/ +/* See the License for the specific language governing permissions and*/ +/* limitations under the License.*/ +/* */ +/* Generated on Wed Aug 27 12:16:34 2025 */ +/* */ +/* ------------------------------------------------------ */ +library(RM_IHPSG13_1P_512x16_c2_bm_bist_slow_1p08V_125C) { + technology (cmos) ; + delay_model : table_lookup ; + define ("add_pg_pin_to_lib", "library", "boolean"); + add_pg_pin_to_lib : true; + voltage_map ( VDD, 1.08); + voltage_map ( VDDARRAY, 1.08); + voltage_map ( VSS, 0.000000 ); + + date : "Wed Aug 27 12:16:33 2025" ; + comment : "IHP Microelectronics GmbH, 2023" ; + revision : 1.0.0 ; + simulation : true ; + nom_process : 1 ; + nom_temperature : 125 ; + nom_voltage : 1.08 ; + + operating_conditions("slow_1p08V_125C"){ + process : 1 ; + temperature : 125 ; + voltage : 1.08 ; + tree_type : "balanced_tree" ; + } + + default_operating_conditions : slow_1p08V_125C ; + default_max_transition : 1.0 ; + default_fanout_load : 1.0 ; + default_inout_pin_cap : 0.0 ; + default_input_pin_cap : 0.0 ; + default_output_pin_cap : 0.0 ; + default_cell_leakage_power : 0.0 ; + default_leakage_power_density : 0.0 ; + + slew_lower_threshold_pct_rise : 30 ; + slew_upper_threshold_pct_rise : 70 ; + input_threshold_pct_fall : 50 ; + output_threshold_pct_fall : 50 ; + input_threshold_pct_rise : 50 ; + output_threshold_pct_rise : 50 ; + slew_lower_threshold_pct_fall : 30 ; + slew_upper_threshold_pct_fall : 70 ; + slew_derate_from_library : 0.5; + k_volt_cell_leakage_power : 0.0 ; + k_temp_cell_leakage_power : 0.0 ; + k_process_cell_leakage_power : 0.0 ; + k_volt_internal_power : 0.0 ; + k_temp_internal_power : 0.0 ; + k_process_internal_power : 0.0 ; + + capacitive_load_unit (1,pf) ; + voltage_unit : "1V" ; + current_unit : "1uA" ; + time_unit : "1ns" ; + leakage_power_unit : "1nW" ; + pulling_resistance_unit : "1kohm"; + /* + ------------------------------------------------------------------------------------------ + implicit units overview: + cell_area unit : "um" + internal_power unit : "1e-12 * J/toggle = 1 * uW/MHz" + (capacitive_load_unit * voltage_unit^2) per toggle event + ------------------------------------------------------------------------------------------ + */ + library_features(report_delay_calculation); + define_cell_area (pad_drivers,pad_driver_sites) ; + + lu_table_template(CLKTRAN_constraint_template) { + variable_1 : constrained_pin_transition; + index_1 ( "0.010, 0.050, 0.200, 0.400, 1.000" ); + } + lu_table_template(SRAM_load_template) { + variable_1 : total_output_net_capacitance; + index_1 ( "0.0008,0.0014,0.0051,0.0100,0.0339,0.0640" ); + } + lu_table_template(SIG2SRAM_constraint_template) { + variable_1 : related_pin_transition; + variable_2 : constrained_pin_transition; + index_1 ( "0.0080,0.0288,0.0616,0.1072,0.1920,0.3496,0.5952" ); + index_2 ( "0.0080,0.0288,0.0616,0.1072,0.1920,0.3496,0.5952" ); + } + + lu_table_template(SIG2SRAM_delay_template) { + variable_1 : input_net_transition; + variable_2 : total_output_net_capacitance; + index_1 ( "0.0080,0.0288,0.0616,0.1072,0.1920,0.3496,0.5952" ); + index_2 ( "0.0008,0.0014,0.0051,0.0100,0.0339,0.0640" ); + } + + type (D_15_0) { + base_type : array; + data_type : bit; + bit_width : 16; + bit_from : 15; + bit_to : 0; + downto : true; + } + + type (A_8_0) { + base_type : array; + data_type : bit; + bit_width : 9; + bit_from : 8; + bit_to : 0; + downto : true; + } + +cell(RM_IHPSG13_1P_512x16_c2_bm_bist) { +pg_pin (VDD) { + pg_type : primary_power; + voltage_name : VDD; +} +pg_pin (VDDARRAY) { + pg_type : primary_power; + voltage_name : VDDARRAY; +} +pg_pin (VSS) { + pg_type : primary_ground; + voltage_name : VSS; +} + +memory() { + type : ram; + address_width : 9; + word_width : 16; +} + +interface_timing : false; +bus_naming_style : "%s[%d]" ; +area : 45309.312 ; + + pin(A_DLY) { + direction : input ; + capacitance : 0.00387999 ; + max_transition : "1" ; + related_power_pin : VDD; + related_ground_pin : VSS; + internal_power() { + rise_power("scalar") { + values (0); + } + fall_power("scalar") { + values (0); + } + } + } + +bus(A_ADDR) { + bus_type : A_8_0; + direction : input ; + capacitance : 0.0077013 ; + pin(A_ADDR[0]) { + capacitance : 0.00625349 ; + } + pin(A_ADDR[1]) { + capacitance : 0.00507435 ; + } + pin(A_ADDR[2]) { + capacitance : 0.00656707 ; + } + pin(A_ADDR[3]) { + capacitance : 0.0083133 ; + } + pin(A_ADDR[4]) { + capacitance : 0.00507219 ; + } + pin(A_ADDR[5]) { + capacitance : 0.00964344 ; + } + pin(A_ADDR[6]) { + capacitance : 0.0119653 ; + } + pin(A_ADDR[7]) { + capacitance : 0.00827606 ; + } + max_transition : "0.5952" ; + pin(A_ADDR[8:0]) { + related_power_pin : VDD; + related_ground_pin : VSS; + internal_power() { + when : "A_MEN"; + rise_power("scalar"){ + values (0.0102); + } + fall_power("scalar"){ + values (0.0078); + } + } + internal_power() { + when : "!A_MEN"; + rise_power("scalar"){ + values (0.0149); + } + fall_power("scalar"){ + values (0.0029); + } + } + } + timing() { + timing_type : setup_rising; + related_pin : "A_CLK"; + when : "((A_WEN | A_REN)& A_MEN)" + sdf_cond : "A_RW_ACCESS" + + rise_constraint("SIG2SRAM_constraint_template") { + index_1("0.0080,0.0288,0.0616,0.1072,0.1920,0.3496,0.5952"); + index_2("0.0080,0.0288,0.0616,0.1072,0.1920,0.3496,0.5952"); + values ("-0.7371,-0.7176,-0.6863,-0.6434,-0.5652,-0.4168,-0.1980",\ +"-0.7566,-0.7371,-0.7059,-0.6629,-0.5848,-0.4363,-0.2137",\ +"-0.7879,-0.7645,-0.7332,-0.6902,-0.6121,-0.4637,-0.2449",\ +"-0.8309,-0.8074,-0.7762,-0.7332,-0.6551,-0.5066,-0.2879",\ +"-0.9051,-0.8895,-0.8543,-0.8113,-0.7332,-0.5887,-0.3660",\ +"-1.0418,-1.0262,-0.9949,-0.9480,-0.8699,-0.7293,-0.5027",\ +"-1.2684,-1.2449,-1.2176,-1.1707,-1.0965,-0.9480,-0.7293"); + } + + fall_constraint("SIG2SRAM_constraint_template") { + index_1("0.0080,0.0288,0.0616,0.1072,0.1920,0.3496,0.5952"); + index_2("0.0080,0.0288,0.0616,0.1072,0.1920,0.3496,0.5952"); + values ("-0.5926,-0.5730,-0.5418,-0.4988,-0.4246,-0.2879,-0.0730",\ +"-0.6121,-0.5926,-0.5613,-0.5223,-0.4441,-0.3074,-0.0887",\ +"-0.6395,-0.6199,-0.5926,-0.5496,-0.4715,-0.3348,-0.1160",\ +"-0.6863,-0.6668,-0.6355,-0.5965,-0.5184,-0.3777,-0.1590",\ +"-0.7605,-0.7410,-0.7137,-0.6746,-0.5926,-0.4559,-0.2410",\ +"-0.9012,-0.8816,-0.8504,-0.8113,-0.7332,-0.5926,-0.3895",\ +"-1.1238,-1.1043,-1.0769,-1.0379,-0.9559,-0.8191,-0.6004"); + } + } + + + timing() { + timing_type : hold_rising; + related_pin : "A_CLK"; + when : "((A_WEN | A_REN)& A_MEN)" + sdf_cond : "A_RW_ACCESS" + + rise_constraint("SIG2SRAM_constraint_template") { + index_1("0.0080,0.0288,0.0616,0.1072,0.1920,0.3496,0.5952"); + index_2("0.0080,0.0288,0.0616,0.1072,0.1920,0.3496,0.5952"); + values ("0.8488,0.8293,0.7980,0.7551,0.6730,0.5285,0.3059",\ +"0.8684,0.8488,0.8176,0.7746,0.6926,0.5480,0.3254",\ +"0.8996,0.8801,0.8449,0.8020,0.7238,0.5754,0.3527",\ +"0.9426,0.9191,0.8918,0.8488,0.7668,0.6223,0.3996",\ +"1.0168,1.0012,0.9699,0.9230,0.8449,0.7004,0.4777",\ +"1.1574,1.1379,1.1105,1.0598,0.9816,0.8371,0.6184",\ +"1.3801,1.3605,1.3254,1.2980,1.2043,1.0637,0.8371"); + } + + fall_constraint("SIG2SRAM_constraint_template") { + index_1("0.0080,0.0288,0.0616,0.1072,0.1920,0.3496,0.5952"); + index_2("0.0080,0.0288,0.0616,0.1072,0.1920,0.3496,0.5952"); + values ("0.6965,0.6770,0.6496,0.6066,0.5246,0.3918,0.1730",\ +"0.7160,0.6965,0.6652,0.6262,0.5441,0.4113,0.1965",\ +"0.7473,0.7277,0.6965,0.6535,0.5754,0.4426,0.2238",\ +"0.7863,0.7707,0.7395,0.7004,0.6223,0.4855,0.2629",\ +"0.8684,0.8449,0.8176,0.7785,0.7004,0.5637,0.3449",\ +"1.0051,0.9855,0.9855,0.9113,0.8332,0.7004,0.4895",\ +"1.2277,1.2082,1.1809,1.1379,1.0598,0.9230,0.7004"); + } + } +} +pin(A_WEN) { + direction : input ; + capacitance : 0.00313551 ; + max_transition : "0.5952" ; + related_power_pin : VDD; + related_ground_pin : VSS; + internal_power() { + when : "A_MEN"; + rise_power("scalar"){ + values (0.0036); + } + fall_power("scalar"){ + values (0.0006); + } + } + internal_power() { + when : "!A_MEN"; + rise_power("scalar"){ + values (0.0050); + } + fall_power("scalar"){ + values (0.0002); + } + } + timing() { + timing_type : setup_rising; + related_pin : "A_CLK"; + when : "A_MEN" + sdf_cond : "A_MEN" + + rise_constraint("SIG2SRAM_constraint_template") { + index_1("0.0080,0.0288,0.0616,0.1072,0.1920,0.3496,0.5952"); + index_2("0.0080,0.0288,0.0616,0.1072,0.1920,0.3496,0.5952"); + values ("0.3137,0.3332,0.3605,0.4035,0.4816,0.6223,0.8488",\ +"0.2980,0.3176,0.3410,0.3840,0.4660,0.6027,0.8293",\ +"0.2629,0.2824,0.3098,0.3527,0.4348,0.5754,0.7980",\ +"0.2199,0.2395,0.2668,0.3098,0.3918,0.5324,0.7590",\ +"0.1418,0.1613,0.1887,0.2316,0.3137,0.4348,0.6730",\ +"0.0012,0.0207,0.0520,0.0910,0.1730,0.3098,0.5285",\ +"-0.2215,-0.2020,-0.1746,-0.1277,-0.0496,0.0910,0.3098"); + } + + fall_constraint("SIG2SRAM_constraint_template") { + index_1("0.0080,0.0288,0.0616,0.1072,0.1920,0.3496,0.5952"); + index_2("0.0080,0.0288,0.0616,0.1072,0.1920,0.3496,0.5952"); + values ("0.4504,0.4699,0.4973,0.5324,0.6027,0.7355,0.9699",\ +"0.4309,0.4504,0.4777,0.5129,0.5910,0.7160,0.9504",\ +"0.3996,0.4191,0.4465,0.4816,0.5520,0.6848,0.9191",\ +"0.3605,0.3762,0.4035,0.4387,0.5168,0.6418,0.8723",\ +"0.2785,0.2980,0.3215,0.3605,0.4348,0.5637,0.7980",\ +"0.1379,0.1574,0.1809,0.2199,0.2980,0.4309,0.6457",\ +"-0.0809,-0.0613,-0.0340,0.0051,0.0832,0.2160,0.4191"); + } + } + + + timing() { + timing_type : hold_rising; + related_pin : "A_CLK"; + when : "A_MEN" + sdf_cond : "A_MEN" + + rise_constraint("SIG2SRAM_constraint_template") { + index_1("0.0080,0.0288,0.0616,0.1072,0.1920,0.3496,0.5952"); + index_2("0.0080,0.0288,0.0616,0.1072,0.1920,0.3496,0.5952"); + values ("0.3723,0.3527,0.3215,0.2785,0.1965,0.0559,-0.1668",\ +"0.3918,0.3723,0.3449,0.2980,0.2160,0.0754,-0.1473",\ +"0.4152,0.3996,0.3684,0.3254,0.2434,0.1066,-0.1199",\ +"0.4621,0.4465,0.4152,0.3723,0.2863,0.1496,-0.0730",\ +"0.5324,0.5207,0.4895,0.4465,0.3645,0.2199,0.0051",\ +"0.6770,0.6535,0.6301,0.5832,0.5090,0.3605,0.1418",\ +"0.9035,0.8879,0.8566,0.8137,0.7316,0.5871,0.3684"); + } + + fall_constraint("SIG2SRAM_constraint_template") { + index_1("0.0080,0.0288,0.0616,0.1072,0.1920,0.3496,0.5952"); + index_2("0.0080,0.0288,0.0616,0.1072,0.1920,0.3496,0.5952"); + values ("0.3762,0.3566,0.3293,0.2863,0.2043,0.0676,-0.1434",\ +"0.3957,0.3762,0.3488,0.3059,0.2238,0.0871,-0.1199",\ +"0.4230,0.4035,0.3723,0.3332,0.2512,0.1184,-0.0965",\ +"0.4660,0.4465,0.4191,0.3762,0.2941,0.1613,-0.0496",\ +"0.5324,0.5168,0.4973,0.4543,0.3723,0.2316,0.0285",\ +"0.6809,0.6613,0.6340,0.5910,0.5129,0.3645,0.1652",\ +"0.9113,0.8918,0.8605,0.8176,0.7395,0.5988,0.3879"); + } + } + } +pin(A_REN) { + direction : input ; + capacitance : 0.00381144 ; + max_transition : "0.5952" ; + related_power_pin : VDD; + related_ground_pin : VSS; + internal_power() { + when : "A_MEN"; + rise_power("scalar"){ + values (0.0041); + } + fall_power("scalar"){ + values (0.0014); + } + } + internal_power() { + when : "!A_MEN"; + rise_power("scalar"){ + values (0.0041); + } + fall_power("scalar"){ + values (0.0012); + } + } + timing() { + timing_type : setup_rising; + related_pin : "A_CLK"; + when : "A_MEN" + sdf_cond : "A_MEN" + + rise_constraint("SIG2SRAM_constraint_template") { + index_1("0.0080,0.0288,0.0616,0.1072,0.1920,0.3496,0.5952"); + index_2("0.0080,0.0288,0.0616,0.1072,0.1920,0.3496,0.5952"); + values ("-0.0770,-0.0574,-0.0262,0.0168,0.0949,0.2355,0.4582",\ +"-0.0965,-0.0770,-0.0457,-0.0027,0.0754,0.2160,0.4387",\ +"-0.1199,-0.1004,-0.0730,-0.0262,0.0520,0.1887,0.4113",\ +"-0.1590,-0.1434,-0.1160,-0.0730,0.0051,0.1457,0.3645",\ +"-0.2449,-0.2254,-0.1941,-0.1473,-0.0770,0.0676,0.2863",\ +"-0.3816,-0.3699,-0.3387,-0.2801,-0.2215,-0.0770,0.1457",\ +"-0.6121,-0.5926,-0.5613,-0.5145,-0.4363,-0.2996,-0.0730"); + } + + fall_constraint("SIG2SRAM_constraint_template") { + index_1("0.0080,0.0288,0.0616,0.1072,0.1920,0.3496,0.5952"); + index_2("0.0080,0.0288,0.0616,0.1072,0.1920,0.3496,0.5952"); + values ("0.1262,0.1457,0.1691,0.2121,0.2824,0.4191,0.6457",\ +"0.1105,0.1262,0.1496,0.1887,0.2629,0.3996,0.6262",\ +"0.0793,0.0949,0.1223,0.1652,0.2395,0.3684,0.5949",\ +"0.0363,0.0559,0.0793,0.1223,0.2004,0.3410,0.5520",\ +"-0.0457,-0.0262,0.0012,0.0441,0.1301,0.2629,0.4738",\ +"-0.1902,-0.1746,-0.1434,-0.1043,-0.0184,0.1223,0.3332",\ +"-0.4129,-0.3934,-0.3660,-0.3230,-0.2449,-0.1043,0.1105"); + } + } + + + timing() { + timing_type : hold_rising; + related_pin : "A_CLK"; + when : "A_MEN" + sdf_cond : "A_MEN" + + rise_constraint("SIG2SRAM_constraint_template") { + index_1("0.0080,0.0288,0.0616,0.1072,0.1920,0.3496,0.5952"); + index_2("0.0080,0.0288,0.0616,0.1072,0.1920,0.3496,0.5952"); + values ("0.4113,0.3918,0.3645,0.3176,0.2395,0.0988,-0.1238",\ +"0.4309,0.4113,0.3840,0.3371,0.2590,0.1184,-0.1043",\ +"0.4582,0.4387,0.4113,0.3645,0.2824,0.1457,-0.0770",\ +"0.5051,0.4816,0.4543,0.4074,0.3293,0.1887,-0.0340",\ +"0.5715,0.5598,0.5324,0.4895,0.4035,0.2512,0.0441",\ +"0.7043,0.7004,0.6730,0.6262,0.5402,0.3957,0.1809",\ +"0.9387,0.9270,0.8957,0.8527,0.7746,0.6262,0.4074"); + } + + fall_constraint("SIG2SRAM_constraint_template") { + index_1("0.0080,0.0288,0.0616,0.1072,0.1920,0.3496,0.5952"); + index_2("0.0080,0.0288,0.0616,0.1072,0.1920,0.3496,0.5952"); + values ("0.4152,0.3918,0.3645,0.3215,0.2395,0.1027,-0.1082",\ +"0.4309,0.4113,0.3801,0.3410,0.2590,0.1223,-0.0926",\ +"0.4582,0.4387,0.4074,0.3684,0.2863,0.1496,-0.0613",\ +"0.5012,0.4816,0.4504,0.4074,0.3293,0.1887,-0.0145",\ +"0.5715,0.5559,0.5285,0.4816,0.3996,0.2512,0.0598",\ +"0.7160,0.7004,0.6691,0.6262,0.5520,0.4035,0.2004",\ +"0.9387,0.9191,0.8957,0.8488,0.7707,0.6262,0.4113"); + } + } + } +pin(A_MEN) { + direction : input ; + capacitance : 0.00300347 ; + max_transition : "0.5952" ; + related_power_pin : VDD; + related_ground_pin : VSS; + internal_power() { + rise_power("scalar"){ + values (0.0161); + } + fall_power("scalar"){ + values (0.0002); + } + } + timing() { + timing_type : setup_rising; + related_pin : "A_CLK"; + + rise_constraint("SIG2SRAM_constraint_template") { + index_1("0.0080,0.0288,0.0616,0.1072,0.1920,0.3496,0.5952"); + index_2("0.0080,0.0288,0.0616,0.1072,0.1920,0.3496,0.5952"); + values ("0.3215,0.3449,0.3684,0.4113,0.4895,0.6301,0.8527",\ +"0.3059,0.3254,0.3527,0.3957,0.4738,0.6145,0.8371",\ +"0.2746,0.2941,0.3215,0.3645,0.4426,0.5871,0.8059",\ +"0.2316,0.2512,0.2785,0.3215,0.3996,0.5402,0.7629",\ +"0.1496,0.1730,0.1965,0.2395,0.3215,0.4660,0.6848",\ +"0.0090,0.0285,0.0598,0.1027,0.1809,0.3176,0.5402",\ +"-0.2098,-0.1902,-0.1668,-0.1199,-0.0418,0.0988,0.3137"); + } + + fall_constraint("SIG2SRAM_constraint_template") { + index_1("0.0080,0.0288,0.0616,0.1072,0.1920,0.3496,0.5952"); + index_2("0.0080,0.0288,0.0616,0.1072,0.1920,0.3496,0.5952"); + values ("0.4582,0.4738,0.5012,0.5363,0.6145,0.7395,0.9738",\ +"0.4387,0.4543,0.4816,0.5207,0.5910,0.7199,0.9582",\ +"0.4035,0.4230,0.4504,0.4855,0.5637,0.6887,0.9230",\ +"0.3645,0.3840,0.4074,0.4465,0.5285,0.6496,0.8840",\ +"0.2824,0.3020,0.3254,0.3645,0.4465,0.5715,0.7980",\ +"0.1418,0.1613,0.1887,0.2238,0.3020,0.4309,0.6496",\ +"-0.0770,-0.0574,-0.0301,0.0090,0.0910,0.2238,0.4191"); + } + } + + + timing() { + timing_type : hold_rising; + related_pin : "A_CLK"; + + rise_constraint("SIG2SRAM_constraint_template") { + index_1("0.0080,0.0288,0.0616,0.1072,0.1920,0.3496,0.5952"); + index_2("0.0080,0.0288,0.0616,0.1072,0.1920,0.3496,0.5952"); + values ("0.3762,0.3605,0.3293,0.2863,0.2043,0.0637,-0.1629",\ +"0.3996,0.3801,0.3488,0.3020,0.2238,0.0832,-0.1395",\ +"0.4230,0.4074,0.3723,0.3293,0.2473,0.1105,-0.1121",\ +"0.4621,0.4465,0.4152,0.3762,0.2941,0.1535,-0.0691",\ +"0.5441,0.5285,0.4973,0.4465,0.3684,0.2316,0.0090",\ +"0.6848,0.6652,0.6301,0.5910,0.5129,0.3605,0.1496",\ +"0.9074,0.8918,0.8566,0.8215,0.7395,0.5910,0.3723"); + } + + fall_constraint("SIG2SRAM_constraint_template") { + index_1("0.0080,0.0288,0.0616,0.1072,0.1920,0.3496,0.5952"); + index_2("0.0080,0.0288,0.0616,0.1072,0.1920,0.3496,0.5952"); + values ("0.3762,0.3605,0.3332,0.2863,0.2043,0.0715,-0.1395",\ +"0.3996,0.3762,0.3488,0.3059,0.2238,0.0910,-0.1199",\ +"0.4270,0.4035,0.3762,0.3332,0.2512,0.1184,-0.0965",\ +"0.4699,0.4504,0.4191,0.3762,0.2941,0.1613,-0.0496",\ +"0.5441,0.5285,0.4973,0.4543,0.3762,0.2355,0.0324",\ +"0.6770,0.6613,0.6340,0.5949,0.5207,0.3762,0.1652",\ +"0.9074,0.8918,0.8605,0.8176,0.7395,0.6027,0.3918"); + } + } + } +bus(A_BM) { + bus_type : D_15_0; + direction : input ; + capacitance : 0.00263802 ; + max_transition : "0.5952" ; + pin(A_BM[15:0]) { + related_power_pin : VDD; + related_ground_pin : VSS; + internal_power() { + when : "A_MEN"; + rise_power("scalar"){ + values (0.0469); + } + fall_power("scalar"){ + values (0.0152); + } + } + internal_power() { + when : "!A_MEN"; + rise_power("scalar"){ + values (0.0453); + } + fall_power("scalar"){ + values (0.0145); + } + } + } + timing() { + timing_type : setup_rising; + related_pin : "A_CLK"; + when : "(A_WEN & A_MEN)" + sdf_cond : "A_RW_ACCESS" + + rise_constraint("SIG2SRAM_constraint_template") { + index_1("0.0080,0.0288,0.0616,0.1072,0.1920,0.3496,0.5952"); + index_2("0.0080,0.0288,0.0616,0.1072,0.1920,0.3496,0.5952"); + values ("-0.6208,-0.6013,-0.5749,-0.5329,-0.4519,-0.3073,-0.0866",\ +"-0.6283,-0.6088,-0.5824,-0.5404,-0.4593,-0.3148,-0.0941",\ +"-0.6379,-0.6183,-0.5920,-0.5500,-0.4689,-0.3244,-0.1037",\ +"-0.6510,-0.6315,-0.6051,-0.5631,-0.4821,-0.3375,-0.1168",\ +"-0.6753,-0.6557,-0.6294,-0.5874,-0.5063,-0.3618,-0.1411",\ +"-0.7057,-0.6862,-0.6598,-0.6178,-0.5368,-0.3922,-0.1715",\ +"-0.7873,-0.7678,-0.7414,-0.6994,-0.6184,-0.4738,-0.2531"); + } + + fall_constraint("SIG2SRAM_constraint_template") { + index_1("0.0080,0.0288,0.0616,0.1072,0.1920,0.3496,0.5952"); + index_2("0.0080,0.0288,0.0616,0.1072,0.1920,0.3496,0.5952"); + values ("-0.5652,-0.5495,-0.5212,-0.4821,-0.4011,-0.2634,-0.0515",\ +"-0.5726,-0.5570,-0.5287,-0.4896,-0.4086,-0.2709,-0.0589",\ +"-0.5822,-0.5666,-0.5383,-0.4992,-0.4181,-0.2804,-0.0685",\ +"-0.5954,-0.5797,-0.5514,-0.5123,-0.4313,-0.2936,-0.0817",\ +"-0.6196,-0.6040,-0.5757,-0.5366,-0.4555,-0.3178,-0.1059",\ +"-0.6500,-0.6344,-0.6061,-0.5670,-0.4860,-0.3483,-0.1364",\ +"-0.7317,-0.7160,-0.6877,-0.6487,-0.5676,-0.4299,-0.2180"); + } + } + + + timing() { + timing_type : hold_rising; + related_pin : "A_CLK"; + when : "(A_WEN & A_MEN)" + sdf_cond : "A_RW_ACCESS" + + rise_constraint("SIG2SRAM_constraint_template") { + index_1("0.0080,0.0288,0.0616,0.1072,0.1920,0.3496,0.5952"); + index_2("0.0080,0.0288,0.0616,0.1072,0.1920,0.3496,0.5952"); + values ("0.7376,0.7161,0.6897,0.6468,0.5677,0.4222,0.1966",\ +"0.7451,0.7236,0.6972,0.6542,0.5751,0.4296,0.2040",\ +"0.7546,0.7332,0.7068,0.6638,0.5847,0.4392,0.2136",\ +"0.7678,0.7463,0.7199,0.6770,0.5979,0.4524,0.2268",\ +"0.7921,0.7706,0.7442,0.7012,0.6221,0.4766,0.2510",\ +"0.8225,0.8010,0.7746,0.7317,0.6526,0.5071,0.2815",\ +"0.9041,0.8826,0.8562,0.8133,0.7342,0.5887,0.3631"); + } + + fall_constraint("SIG2SRAM_constraint_template") { + index_1("0.0080,0.0288,0.0616,0.1072,0.1920,0.3496,0.5952"); + index_2("0.0080,0.0288,0.0616,0.1072,0.1920,0.3496,0.5952"); + values ("0.6692,0.6526,0.6243,0.5804,0.5032,0.3655,0.1556",\ +"0.6767,0.6601,0.6318,0.5878,0.5107,0.3730,0.1630",\ +"0.6863,0.6697,0.6414,0.5974,0.5203,0.3826,0.1726",\ +"0.6994,0.6828,0.6545,0.6106,0.5334,0.3957,0.1858",\ +"0.7237,0.7071,0.6788,0.6348,0.5577,0.4200,0.2100",\ +"0.7541,0.7375,0.7092,0.6653,0.5881,0.4504,0.2404",\ +"0.8357,0.8191,0.7908,0.7469,0.6697,0.5320,0.3221"); + } + } +} + pin(A_CLK) { + direction : input; + capacitance : 0.00378957; + max_transition : "0.5952"; + clock : "true" ; + pin_func_type : active_rising ; + + timing () { + timing_type : "min_pulse_width"; + related_pin : "A_CLK"; + rise_constraint("CLKTRAN_constraint_template") { + index_1("0.008,0.5952"); + values("0.4,0.4"); + } + } + + related_power_pin : VDD; + related_ground_pin : VSS; + + internal_power() { + when : "!A_MEN & !A_WEN & !A_REN"; + rise_power("scalar"){ + values (0); + } + fall_power("scalar"){ + values (0); + } + } + internal_power() { + when : "!A_MEN & A_WEN & !A_REN"; + rise_power("scalar"){ + values (0.5014); + } + fall_power("scalar"){ + values (0); + } + } + internal_power() { + when : "A_MEN & A_WEN & !A_REN"; + rise_power("scalar"){ + values (19.4302); + } + fall_power("scalar"){ + values (0); + } + } + internal_power() { + when : "A_MEN & A_WEN & A_REN"; + rise_power("scalar"){ + values (20.3865); + } + fall_power("scalar"){ + values (0); + } + } + internal_power() { + when : "A_MEN & !A_WEN & A_REN"; + rise_power("scalar"){ + values (15.8142); + } + fall_power("scalar"){ + values (0); + } + } + internal_power() { + when : "!A_MEN & !A_WEN & A_REN"; + rise_power("scalar"){ + values (0.3165); + } + fall_power("scalar"){ + values (0); + } + } + internal_power() { + when : "!A_MEN & A_WEN & A_REN"; + rise_power("scalar"){ + values (0.6909); + } + fall_power("scalar"){ + values (0); + } + } + internal_power() { + when : "A_MEN & !A_WEN & !A_REN"; + rise_power("scalar"){ + values (0); + } + fall_power("scalar"){ + values (0); + } + } + } + bus(A_DIN) { + bus_type : D_15_0; + direction : input ; + capacitance : 0.00358485 ; + memory_write() { + address : A_ADDR ; + clocked_on : A_CLK; + } + + max_transition : "0.5952" ; + pin(A_DIN[15:0]) { + related_power_pin : VDD; + related_ground_pin : VSS; + internal_power() { + when : "A_MEN"; + rise_power("scalar"){ + values (0.0469); + } + fall_power("scalar"){ + values (0.0152); + } + } + internal_power() { + when : "!A_MEN"; + rise_power("scalar"){ + values (0.0453); + } + fall_power("scalar"){ + values (0.0145); + } + } + } + timing() { + timing_type : setup_rising; + related_pin : "A_CLK"; + when : "(A_WEN & A_MEN)"; + sdf_cond : "A_W_ACCESS"; + + rise_constraint("SIG2SRAM_constraint_template") { + index_1("0.0080,0.0288,0.0616,0.1072,0.1920,0.3496,0.5952"); + index_2("0.0080,0.0288,0.0616,0.1072,0.1920,0.3496,0.5952"); + values ("-0.6208,-0.6013,-0.5749,-0.5329,-0.4519,-0.3073,-0.0866",\ +"-0.6283,-0.6088,-0.5824,-0.5404,-0.4593,-0.3148,-0.0941",\ +"-0.6379,-0.6183,-0.5920,-0.5500,-0.4689,-0.3244,-0.1037",\ +"-0.6510,-0.6315,-0.6051,-0.5631,-0.4821,-0.3375,-0.1168",\ +"-0.6753,-0.6557,-0.6294,-0.5874,-0.5063,-0.3618,-0.1411",\ +"-0.7057,-0.6862,-0.6598,-0.6178,-0.5368,-0.3922,-0.1715",\ +"-0.7873,-0.7678,-0.7414,-0.6994,-0.6184,-0.4738,-0.2531"); + } + + fall_constraint("SIG2SRAM_constraint_template") { + index_1("0.0080,0.0288,0.0616,0.1072,0.1920,0.3496,0.5952"); + index_2("0.0080,0.0288,0.0616,0.1072,0.1920,0.3496,0.5952"); + values ("-0.5652,-0.5495,-0.5212,-0.4821,-0.4011,-0.2634,-0.0515",\ +"-0.5726,-0.5570,-0.5287,-0.4896,-0.4086,-0.2709,-0.0589",\ +"-0.5822,-0.5666,-0.5383,-0.4992,-0.4181,-0.2804,-0.0685",\ +"-0.5954,-0.5797,-0.5514,-0.5123,-0.4313,-0.2936,-0.0817",\ +"-0.6196,-0.6040,-0.5757,-0.5366,-0.4555,-0.3178,-0.1059",\ +"-0.6500,-0.6344,-0.6061,-0.5670,-0.4860,-0.3483,-0.1364",\ +"-0.7317,-0.7160,-0.6877,-0.6487,-0.5676,-0.4299,-0.2180"); + } + } + + timing() { + timing_type : hold_rising; + related_pin : "A_CLK"; + when : "(A_WEN & A_MEN)"; + sdf_cond : "A_W_ACCESS"; + + rise_constraint("SIG2SRAM_constraint_template") { + index_1("0.0080,0.0288,0.0616,0.1072,0.1920,0.3496,0.5952"); + index_2("0.0080,0.0288,0.0616,0.1072,0.1920,0.3496,0.5952"); + values ("0.7376,0.7161,0.6897,0.6468,0.5677,0.4222,0.1966",\ +"0.7451,0.7236,0.6972,0.6542,0.5751,0.4296,0.2040",\ +"0.7546,0.7332,0.7068,0.6638,0.5847,0.4392,0.2136",\ +"0.7678,0.7463,0.7199,0.6770,0.5979,0.4524,0.2268",\ +"0.7921,0.7706,0.7442,0.7012,0.6221,0.4766,0.2510",\ +"0.8225,0.8010,0.7746,0.7317,0.6526,0.5071,0.2815",\ +"0.9041,0.8826,0.8562,0.8133,0.7342,0.5887,0.3631"); + } + + fall_constraint("SIG2SRAM_constraint_template") { + index_1("0.0080,0.0288,0.0616,0.1072,0.1920,0.3496,0.5952"); + index_2("0.0080,0.0288,0.0616,0.1072,0.1920,0.3496,0.5952"); + values ("0.6692,0.6526,0.6243,0.5804,0.5032,0.3655,0.1556",\ +"0.6767,0.6601,0.6318,0.5878,0.5107,0.3730,0.1630",\ +"0.6863,0.6697,0.6414,0.5974,0.5203,0.3826,0.1726",\ +"0.6994,0.6828,0.6545,0.6106,0.5334,0.3957,0.1858",\ +"0.7237,0.7071,0.6788,0.6348,0.5577,0.4200,0.2100",\ +"0.7541,0.7375,0.7092,0.6653,0.5881,0.4504,0.2404",\ +"0.8357,0.8191,0.7908,0.7469,0.6697,0.5320,0.3221"); + } + } + } + + pin(A_BIST_EN) { + direction : input ; + capacitance : 0.00387999 ; + max_transition : "1" ; + related_power_pin : VDD; + related_ground_pin : VSS; + internal_power() { + rise_power("scalar") { + values (0); + } + fall_power("scalar") { + values (0); + } + } + } + +bus(A_BIST_ADDR) { + bus_type : A_8_0; + direction : input ; + capacitance : 0.0077013 ; + pin(A_BIST_ADDR[0]) { + capacitance : 0.00625349 ; + } + pin(A_BIST_ADDR[1]) { + capacitance : 0.00507435 ; + } + pin(A_BIST_ADDR[2]) { + capacitance : 0.00656707 ; + } + pin(A_BIST_ADDR[3]) { + capacitance : 0.0083133 ; + } + pin(A_BIST_ADDR[4]) { + capacitance : 0.00507219 ; + } + pin(A_BIST_ADDR[5]) { + capacitance : 0.00964344 ; + } + pin(A_BIST_ADDR[6]) { + capacitance : 0.0119653 ; + } + pin(A_BIST_ADDR[7]) { + capacitance : 0.00827606 ; + } + max_transition : "0.5952" ; + pin(A_BIST_ADDR[8:0]) { + related_power_pin : VDD; + related_ground_pin : VSS; + internal_power() { + when : "A_BIST_MEN"; + rise_power("scalar"){ + values (0.0102); + } + fall_power("scalar"){ + values (0.0078); + } + } + internal_power() { + when : "!A_BIST_MEN"; + rise_power("scalar"){ + values (0.0149); + } + fall_power("scalar"){ + values (0.0029); + } + } + } + timing() { + timing_type : setup_rising; + related_pin : "A_BIST_CLK"; + when : "((A_BIST_WEN | A_BIST_REN)& A_BIST_MEN)" + sdf_cond : "A_BIST_RW_ACCESS" + + rise_constraint("SIG2SRAM_constraint_template") { + index_1("0.0080,0.0288,0.0616,0.1072,0.1920,0.3496,0.5952"); + index_2("0.0080,0.0288,0.0616,0.1072,0.1920,0.3496,0.5952"); + values ("-0.7371,-0.7176,-0.6863,-0.6434,-0.5652,-0.4168,-0.1980",\ +"-0.7566,-0.7371,-0.7059,-0.6629,-0.5848,-0.4363,-0.2137",\ +"-0.7879,-0.7645,-0.7332,-0.6902,-0.6121,-0.4637,-0.2449",\ +"-0.8309,-0.8074,-0.7762,-0.7332,-0.6551,-0.5066,-0.2879",\ +"-0.9051,-0.8895,-0.8543,-0.8113,-0.7332,-0.5887,-0.3660",\ +"-1.0418,-1.0262,-0.9949,-0.9480,-0.8699,-0.7293,-0.5027",\ +"-1.2684,-1.2449,-1.2176,-1.1707,-1.0965,-0.9480,-0.7293"); + } + + fall_constraint("SIG2SRAM_constraint_template") { + index_1("0.0080,0.0288,0.0616,0.1072,0.1920,0.3496,0.5952"); + index_2("0.0080,0.0288,0.0616,0.1072,0.1920,0.3496,0.5952"); + values ("-0.5926,-0.5730,-0.5418,-0.4988,-0.4246,-0.2879,-0.0730",\ +"-0.6121,-0.5926,-0.5613,-0.5223,-0.4441,-0.3074,-0.0887",\ +"-0.6395,-0.6199,-0.5926,-0.5496,-0.4715,-0.3348,-0.1160",\ +"-0.6863,-0.6668,-0.6355,-0.5965,-0.5184,-0.3777,-0.1590",\ +"-0.7605,-0.7410,-0.7137,-0.6746,-0.5926,-0.4559,-0.2410",\ +"-0.9012,-0.8816,-0.8504,-0.8113,-0.7332,-0.5926,-0.3895",\ +"-1.1238,-1.1043,-1.0769,-1.0379,-0.9559,-0.8191,-0.6004"); + } + } + + + timing() { + timing_type : hold_rising; + related_pin : "A_BIST_CLK"; + when : "((A_BIST_WEN | A_BIST_REN)& A_BIST_MEN)" + sdf_cond : "A_BIST_RW_ACCESS" + + rise_constraint("SIG2SRAM_constraint_template") { + index_1("0.0080,0.0288,0.0616,0.1072,0.1920,0.3496,0.5952"); + index_2("0.0080,0.0288,0.0616,0.1072,0.1920,0.3496,0.5952"); + values ("0.8488,0.8293,0.7980,0.7551,0.6730,0.5285,0.3059",\ +"0.8684,0.8488,0.8176,0.7746,0.6926,0.5480,0.3254",\ +"0.8996,0.8801,0.8449,0.8020,0.7238,0.5754,0.3527",\ +"0.9426,0.9191,0.8918,0.8488,0.7668,0.6223,0.3996",\ +"1.0168,1.0012,0.9699,0.9230,0.8449,0.7004,0.4777",\ +"1.1574,1.1379,1.1105,1.0598,0.9816,0.8371,0.6184",\ +"1.3801,1.3605,1.3254,1.2980,1.2043,1.0637,0.8371"); + } + + fall_constraint("SIG2SRAM_constraint_template") { + index_1("0.0080,0.0288,0.0616,0.1072,0.1920,0.3496,0.5952"); + index_2("0.0080,0.0288,0.0616,0.1072,0.1920,0.3496,0.5952"); + values ("0.6965,0.6770,0.6496,0.6066,0.5246,0.3918,0.1730",\ +"0.7160,0.6965,0.6652,0.6262,0.5441,0.4113,0.1965",\ +"0.7473,0.7277,0.6965,0.6535,0.5754,0.4426,0.2238",\ +"0.7863,0.7707,0.7395,0.7004,0.6223,0.4855,0.2629",\ +"0.8684,0.8449,0.8176,0.7785,0.7004,0.5637,0.3449",\ +"1.0051,0.9855,0.9855,0.9113,0.8332,0.7004,0.4895",\ +"1.2277,1.2082,1.1809,1.1379,1.0598,0.9230,0.7004"); + } + } +} +pin(A_BIST_WEN) { + direction : input ; + capacitance : 0.00313551 ; + max_transition : "0.5952" ; + related_power_pin : VDD; + related_ground_pin : VSS; + internal_power() { + when : "A_BIST_MEN"; + rise_power("scalar"){ + values (0.0036); + } + fall_power("scalar"){ + values (0.0006); + } + } + internal_power() { + when : "!A_BIST_MEN"; + rise_power("scalar"){ + values (0.0050); + } + fall_power("scalar"){ + values (0.0002); + } + } + timing() { + timing_type : setup_rising; + related_pin : "A_BIST_CLK"; + when : "A_BIST_MEN" + sdf_cond : "A_BIST_MEN" + + rise_constraint("SIG2SRAM_constraint_template") { + index_1("0.0080,0.0288,0.0616,0.1072,0.1920,0.3496,0.5952"); + index_2("0.0080,0.0288,0.0616,0.1072,0.1920,0.3496,0.5952"); + values ("0.3137,0.3332,0.3605,0.4035,0.4816,0.6223,0.8488",\ +"0.2980,0.3176,0.3410,0.3840,0.4660,0.6027,0.8293",\ +"0.2629,0.2824,0.3098,0.3527,0.4348,0.5754,0.7980",\ +"0.2199,0.2395,0.2668,0.3098,0.3918,0.5324,0.7590",\ +"0.1418,0.1613,0.1887,0.2316,0.3137,0.4348,0.6730",\ +"0.0012,0.0207,0.0520,0.0910,0.1730,0.3098,0.5285",\ +"-0.2215,-0.2020,-0.1746,-0.1277,-0.0496,0.0910,0.3098"); + } + + fall_constraint("SIG2SRAM_constraint_template") { + index_1("0.0080,0.0288,0.0616,0.1072,0.1920,0.3496,0.5952"); + index_2("0.0080,0.0288,0.0616,0.1072,0.1920,0.3496,0.5952"); + values ("0.4504,0.4699,0.4973,0.5324,0.6027,0.7355,0.9699",\ +"0.4309,0.4504,0.4777,0.5129,0.5910,0.7160,0.9504",\ +"0.3996,0.4191,0.4465,0.4816,0.5520,0.6848,0.9191",\ +"0.3605,0.3762,0.4035,0.4387,0.5168,0.6418,0.8723",\ +"0.2785,0.2980,0.3215,0.3605,0.4348,0.5637,0.7980",\ +"0.1379,0.1574,0.1809,0.2199,0.2980,0.4309,0.6457",\ +"-0.0809,-0.0613,-0.0340,0.0051,0.0832,0.2160,0.4191"); + } + } + + + timing() { + timing_type : hold_rising; + related_pin : "A_BIST_CLK"; + when : "A_BIST_MEN" + sdf_cond : "A_BIST_MEN" + + rise_constraint("SIG2SRAM_constraint_template") { + index_1("0.0080,0.0288,0.0616,0.1072,0.1920,0.3496,0.5952"); + index_2("0.0080,0.0288,0.0616,0.1072,0.1920,0.3496,0.5952"); + values ("0.3723,0.3527,0.3215,0.2785,0.1965,0.0559,-0.1668",\ +"0.3918,0.3723,0.3449,0.2980,0.2160,0.0754,-0.1473",\ +"0.4152,0.3996,0.3684,0.3254,0.2434,0.1066,-0.1199",\ +"0.4621,0.4465,0.4152,0.3723,0.2863,0.1496,-0.0730",\ +"0.5324,0.5207,0.4895,0.4465,0.3645,0.2199,0.0051",\ +"0.6770,0.6535,0.6301,0.5832,0.5090,0.3605,0.1418",\ +"0.9035,0.8879,0.8566,0.8137,0.7316,0.5871,0.3684"); + } + + fall_constraint("SIG2SRAM_constraint_template") { + index_1("0.0080,0.0288,0.0616,0.1072,0.1920,0.3496,0.5952"); + index_2("0.0080,0.0288,0.0616,0.1072,0.1920,0.3496,0.5952"); + values ("0.3762,0.3566,0.3293,0.2863,0.2043,0.0676,-0.1434",\ +"0.3957,0.3762,0.3488,0.3059,0.2238,0.0871,-0.1199",\ +"0.4230,0.4035,0.3723,0.3332,0.2512,0.1184,-0.0965",\ +"0.4660,0.4465,0.4191,0.3762,0.2941,0.1613,-0.0496",\ +"0.5324,0.5168,0.4973,0.4543,0.3723,0.2316,0.0285",\ +"0.6809,0.6613,0.6340,0.5910,0.5129,0.3645,0.1652",\ +"0.9113,0.8918,0.8605,0.8176,0.7395,0.5988,0.3879"); + } + } + } +pin(A_BIST_REN) { + direction : input ; + capacitance : 0.00381144 ; + max_transition : "0.5952" ; + related_power_pin : VDD; + related_ground_pin : VSS; + internal_power() { + when : "A_BIST_MEN"; + rise_power("scalar"){ + values (0.0041); + } + fall_power("scalar"){ + values (0.0014); + } + } + internal_power() { + when : "!A_BIST_MEN"; + rise_power("scalar"){ + values (0.0041); + } + fall_power("scalar"){ + values (0.0012); + } + } + timing() { + timing_type : setup_rising; + related_pin : "A_BIST_CLK"; + when : "A_BIST_MEN" + sdf_cond : "A_BIST_MEN" + + rise_constraint("SIG2SRAM_constraint_template") { + index_1("0.0080,0.0288,0.0616,0.1072,0.1920,0.3496,0.5952"); + index_2("0.0080,0.0288,0.0616,0.1072,0.1920,0.3496,0.5952"); + values ("-0.0770,-0.0574,-0.0262,0.0168,0.0949,0.2355,0.4582",\ +"-0.0965,-0.0770,-0.0457,-0.0027,0.0754,0.2160,0.4387",\ +"-0.1199,-0.1004,-0.0730,-0.0262,0.0520,0.1887,0.4113",\ +"-0.1590,-0.1434,-0.1160,-0.0730,0.0051,0.1457,0.3645",\ +"-0.2449,-0.2254,-0.1941,-0.1473,-0.0770,0.0676,0.2863",\ +"-0.3816,-0.3699,-0.3387,-0.2801,-0.2215,-0.0770,0.1457",\ +"-0.6121,-0.5926,-0.5613,-0.5145,-0.4363,-0.2996,-0.0730"); + } + + fall_constraint("SIG2SRAM_constraint_template") { + index_1("0.0080,0.0288,0.0616,0.1072,0.1920,0.3496,0.5952"); + index_2("0.0080,0.0288,0.0616,0.1072,0.1920,0.3496,0.5952"); + values ("0.1262,0.1457,0.1691,0.2121,0.2824,0.4191,0.6457",\ +"0.1105,0.1262,0.1496,0.1887,0.2629,0.3996,0.6262",\ +"0.0793,0.0949,0.1223,0.1652,0.2395,0.3684,0.5949",\ +"0.0363,0.0559,0.0793,0.1223,0.2004,0.3410,0.5520",\ +"-0.0457,-0.0262,0.0012,0.0441,0.1301,0.2629,0.4738",\ +"-0.1902,-0.1746,-0.1434,-0.1043,-0.0184,0.1223,0.3332",\ +"-0.4129,-0.3934,-0.3660,-0.3230,-0.2449,-0.1043,0.1105"); + } + } + + + timing() { + timing_type : hold_rising; + related_pin : "A_BIST_CLK"; + when : "A_BIST_MEN" + sdf_cond : "A_BIST_MEN" + + rise_constraint("SIG2SRAM_constraint_template") { + index_1("0.0080,0.0288,0.0616,0.1072,0.1920,0.3496,0.5952"); + index_2("0.0080,0.0288,0.0616,0.1072,0.1920,0.3496,0.5952"); + values ("0.4113,0.3918,0.3645,0.3176,0.2395,0.0988,-0.1238",\ +"0.4309,0.4113,0.3840,0.3371,0.2590,0.1184,-0.1043",\ +"0.4582,0.4387,0.4113,0.3645,0.2824,0.1457,-0.0770",\ +"0.5051,0.4816,0.4543,0.4074,0.3293,0.1887,-0.0340",\ +"0.5715,0.5598,0.5324,0.4895,0.4035,0.2512,0.0441",\ +"0.7043,0.7004,0.6730,0.6262,0.5402,0.3957,0.1809",\ +"0.9387,0.9270,0.8957,0.8527,0.7746,0.6262,0.4074"); + } + + fall_constraint("SIG2SRAM_constraint_template") { + index_1("0.0080,0.0288,0.0616,0.1072,0.1920,0.3496,0.5952"); + index_2("0.0080,0.0288,0.0616,0.1072,0.1920,0.3496,0.5952"); + values ("0.4152,0.3918,0.3645,0.3215,0.2395,0.1027,-0.1082",\ +"0.4309,0.4113,0.3801,0.3410,0.2590,0.1223,-0.0926",\ +"0.4582,0.4387,0.4074,0.3684,0.2863,0.1496,-0.0613",\ +"0.5012,0.4816,0.4504,0.4074,0.3293,0.1887,-0.0145",\ +"0.5715,0.5559,0.5285,0.4816,0.3996,0.2512,0.0598",\ +"0.7160,0.7004,0.6691,0.6262,0.5520,0.4035,0.2004",\ +"0.9387,0.9191,0.8957,0.8488,0.7707,0.6262,0.4113"); + } + } + } +pin(A_BIST_MEN) { + direction : input ; + capacitance : 0.00300347 ; + max_transition : "0.5952" ; + related_power_pin : VDD; + related_ground_pin : VSS; + internal_power() { + rise_power("scalar"){ + values (0.0161); + } + fall_power("scalar"){ + values (0.0002); + } + } + timing() { + timing_type : setup_rising; + related_pin : "A_BIST_CLK"; + + rise_constraint("SIG2SRAM_constraint_template") { + index_1("0.0080,0.0288,0.0616,0.1072,0.1920,0.3496,0.5952"); + index_2("0.0080,0.0288,0.0616,0.1072,0.1920,0.3496,0.5952"); + values ("0.3215,0.3449,0.3684,0.4113,0.4895,0.6301,0.8527",\ +"0.3059,0.3254,0.3527,0.3957,0.4738,0.6145,0.8371",\ +"0.2746,0.2941,0.3215,0.3645,0.4426,0.5871,0.8059",\ +"0.2316,0.2512,0.2785,0.3215,0.3996,0.5402,0.7629",\ +"0.1496,0.1730,0.1965,0.2395,0.3215,0.4660,0.6848",\ +"0.0090,0.0285,0.0598,0.1027,0.1809,0.3176,0.5402",\ +"-0.2098,-0.1902,-0.1668,-0.1199,-0.0418,0.0988,0.3137"); + } + + fall_constraint("SIG2SRAM_constraint_template") { + index_1("0.0080,0.0288,0.0616,0.1072,0.1920,0.3496,0.5952"); + index_2("0.0080,0.0288,0.0616,0.1072,0.1920,0.3496,0.5952"); + values ("0.4582,0.4738,0.5012,0.5363,0.6145,0.7395,0.9738",\ +"0.4387,0.4543,0.4816,0.5207,0.5910,0.7199,0.9582",\ +"0.4035,0.4230,0.4504,0.4855,0.5637,0.6887,0.9230",\ +"0.3645,0.3840,0.4074,0.4465,0.5285,0.6496,0.8840",\ +"0.2824,0.3020,0.3254,0.3645,0.4465,0.5715,0.7980",\ +"0.1418,0.1613,0.1887,0.2238,0.3020,0.4309,0.6496",\ +"-0.0770,-0.0574,-0.0301,0.0090,0.0910,0.2238,0.4191"); + } + } + + + timing() { + timing_type : hold_rising; + related_pin : "A_BIST_CLK"; + + rise_constraint("SIG2SRAM_constraint_template") { + index_1("0.0080,0.0288,0.0616,0.1072,0.1920,0.3496,0.5952"); + index_2("0.0080,0.0288,0.0616,0.1072,0.1920,0.3496,0.5952"); + values ("0.3762,0.3605,0.3293,0.2863,0.2043,0.0637,-0.1629",\ +"0.3996,0.3801,0.3488,0.3020,0.2238,0.0832,-0.1395",\ +"0.4230,0.4074,0.3723,0.3293,0.2473,0.1105,-0.1121",\ +"0.4621,0.4465,0.4152,0.3762,0.2941,0.1535,-0.0691",\ +"0.5441,0.5285,0.4973,0.4465,0.3684,0.2316,0.0090",\ +"0.6848,0.6652,0.6301,0.5910,0.5129,0.3605,0.1496",\ +"0.9074,0.8918,0.8566,0.8215,0.7395,0.5910,0.3723"); + } + + fall_constraint("SIG2SRAM_constraint_template") { + index_1("0.0080,0.0288,0.0616,0.1072,0.1920,0.3496,0.5952"); + index_2("0.0080,0.0288,0.0616,0.1072,0.1920,0.3496,0.5952"); + values ("0.3762,0.3605,0.3332,0.2863,0.2043,0.0715,-0.1395",\ +"0.3996,0.3762,0.3488,0.3059,0.2238,0.0910,-0.1199",\ +"0.4270,0.4035,0.3762,0.3332,0.2512,0.1184,-0.0965",\ +"0.4699,0.4504,0.4191,0.3762,0.2941,0.1613,-0.0496",\ +"0.5441,0.5285,0.4973,0.4543,0.3762,0.2355,0.0324",\ +"0.6770,0.6613,0.6340,0.5949,0.5207,0.3762,0.1652",\ +"0.9074,0.8918,0.8605,0.8176,0.7395,0.6027,0.3918"); + } + } + } +bus(A_BIST_BM) { + bus_type : D_15_0; + direction : input ; + capacitance : 0.00225269 ; + max_transition : "0.5952" ; + pin(A_BIST_BM[15:0]) { + related_power_pin : VDD; + related_ground_pin : VSS; + internal_power() { + when : "A_BIST_MEN"; + rise_power("scalar"){ + values (0.0469); + } + fall_power("scalar"){ + values (0.0152); + } + } + internal_power() { + when : "!A_BIST_MEN"; + rise_power("scalar"){ + values (0.0453); + } + fall_power("scalar"){ + values (0.0145); + } + } + } + timing() { + timing_type : setup_rising; + related_pin : "A_BIST_CLK"; + when : "(A_BIST_WEN & A_BIST_MEN)" + sdf_cond : "A_BIST_RW_ACCESS" + + rise_constraint("SIG2SRAM_constraint_template") { + index_1("0.0080,0.0288,0.0616,0.1072,0.1920,0.3496,0.5952"); + index_2("0.0080,0.0288,0.0616,0.1072,0.1920,0.3496,0.5952"); + values ("-0.6208,-0.6013,-0.5749,-0.5329,-0.4519,-0.3073,-0.0866",\ +"-0.6283,-0.6088,-0.5824,-0.5404,-0.4593,-0.3148,-0.0941",\ +"-0.6379,-0.6183,-0.5920,-0.5500,-0.4689,-0.3244,-0.1037",\ +"-0.6510,-0.6315,-0.6051,-0.5631,-0.4821,-0.3375,-0.1168",\ +"-0.6753,-0.6557,-0.6294,-0.5874,-0.5063,-0.3618,-0.1411",\ +"-0.7057,-0.6862,-0.6598,-0.6178,-0.5368,-0.3922,-0.1715",\ +"-0.7873,-0.7678,-0.7414,-0.6994,-0.6184,-0.4738,-0.2531"); + } + + fall_constraint("SIG2SRAM_constraint_template") { + index_1("0.0080,0.0288,0.0616,0.1072,0.1920,0.3496,0.5952"); + index_2("0.0080,0.0288,0.0616,0.1072,0.1920,0.3496,0.5952"); + values ("-0.5652,-0.5495,-0.5212,-0.4821,-0.4011,-0.2634,-0.0515",\ +"-0.5726,-0.5570,-0.5287,-0.4896,-0.4086,-0.2709,-0.0589",\ +"-0.5822,-0.5666,-0.5383,-0.4992,-0.4181,-0.2804,-0.0685",\ +"-0.5954,-0.5797,-0.5514,-0.5123,-0.4313,-0.2936,-0.0817",\ +"-0.6196,-0.6040,-0.5757,-0.5366,-0.4555,-0.3178,-0.1059",\ +"-0.6500,-0.6344,-0.6061,-0.5670,-0.4860,-0.3483,-0.1364",\ +"-0.7317,-0.7160,-0.6877,-0.6487,-0.5676,-0.4299,-0.2180"); + } + } + + + timing() { + timing_type : hold_rising; + related_pin : "A_BIST_CLK"; + when : "(A_BIST_WEN & A_BIST_MEN)" + sdf_cond : "A_BIST_RW_ACCESS" + + rise_constraint("SIG2SRAM_constraint_template") { + index_1("0.0080,0.0288,0.0616,0.1072,0.1920,0.3496,0.5952"); + index_2("0.0080,0.0288,0.0616,0.1072,0.1920,0.3496,0.5952"); + values ("0.7376,0.7161,0.6897,0.6468,0.5677,0.4222,0.1966",\ +"0.7451,0.7236,0.6972,0.6542,0.5751,0.4296,0.2040",\ +"0.7546,0.7332,0.7068,0.6638,0.5847,0.4392,0.2136",\ +"0.7678,0.7463,0.7199,0.6770,0.5979,0.4524,0.2268",\ +"0.7921,0.7706,0.7442,0.7012,0.6221,0.4766,0.2510",\ +"0.8225,0.8010,0.7746,0.7317,0.6526,0.5071,0.2815",\ +"0.9041,0.8826,0.8562,0.8133,0.7342,0.5887,0.3631"); + } + + fall_constraint("SIG2SRAM_constraint_template") { + index_1("0.0080,0.0288,0.0616,0.1072,0.1920,0.3496,0.5952"); + index_2("0.0080,0.0288,0.0616,0.1072,0.1920,0.3496,0.5952"); + values ("0.6692,0.6526,0.6243,0.5804,0.5032,0.3655,0.1556",\ +"0.6767,0.6601,0.6318,0.5878,0.5107,0.3730,0.1630",\ +"0.6863,0.6697,0.6414,0.5974,0.5203,0.3826,0.1726",\ +"0.6994,0.6828,0.6545,0.6106,0.5334,0.3957,0.1858",\ +"0.7237,0.7071,0.6788,0.6348,0.5577,0.4200,0.2100",\ +"0.7541,0.7375,0.7092,0.6653,0.5881,0.4504,0.2404",\ +"0.8357,0.8191,0.7908,0.7469,0.6697,0.5320,0.3221"); + } + } +} + pin(A_BIST_CLK) { + direction : input; + capacitance : 0.00378957; + max_transition : "0.5952"; + clock : "true" ; + pin_func_type : active_rising ; + + timing () { + timing_type : "min_pulse_width"; + related_pin : "A_BIST_CLK"; + rise_constraint("CLKTRAN_constraint_template") { + index_1("0.008,0.5952"); + values("0.4,0.4"); + } + } + + related_power_pin : VDD; + related_ground_pin : VSS; + + internal_power() { + when : "!A_BIST_MEN & !A_BIST_WEN & !A_BIST_REN"; + rise_power("scalar"){ + values (0); + } + fall_power("scalar"){ + values (0); + } + } + internal_power() { + when : "!A_BIST_MEN & A_BIST_WEN & !A_BIST_REN"; + rise_power("scalar"){ + values (0.5014); + } + fall_power("scalar"){ + values (0); + } + } + internal_power() { + when : "A_BIST_MEN & A_BIST_WEN & !A_BIST_REN"; + rise_power("scalar"){ + values (19.4302); + } + fall_power("scalar"){ + values (0); + } + } + internal_power() { + when : "A_BIST_MEN & A_BIST_WEN & A_BIST_REN"; + rise_power("scalar"){ + values (20.3865); + } + fall_power("scalar"){ + values (0); + } + } + internal_power() { + when : "A_BIST_MEN & !A_BIST_WEN & A_BIST_REN"; + rise_power("scalar"){ + values (15.8142); + } + fall_power("scalar"){ + values (0); + } + } + internal_power() { + when : "!A_BIST_MEN & !A_BIST_WEN & A_BIST_REN"; + rise_power("scalar"){ + values (0.3165); + } + fall_power("scalar"){ + values (0); + } + } + internal_power() { + when : "!A_BIST_MEN & A_BIST_WEN & A_BIST_REN"; + rise_power("scalar"){ + values (0.6909); + } + fall_power("scalar"){ + values (0); + } + } + internal_power() { + when : "A_BIST_MEN & !A_BIST_WEN & !A_BIST_REN"; + rise_power("scalar"){ + values (0); + } + fall_power("scalar"){ + values (0); + } + } + } + bus(A_BIST_DIN) { + bus_type : D_15_0; + direction : input ; + capacitance : 0.00226348 ; + memory_write() { + address : A_BIST_ADDR ; + clocked_on : A_BIST_CLK; + } + + max_transition : "0.5952" ; + pin(A_BIST_DIN[15:0]) { + related_power_pin : VDD; + related_ground_pin : VSS; + internal_power() { + when : "A_BIST_MEN"; + rise_power("scalar"){ + values (0.0469); + } + fall_power("scalar"){ + values (0.0152); + } + } + internal_power() { + when : "!A_BIST_MEN"; + rise_power("scalar"){ + values (0.0453); + } + fall_power("scalar"){ + values (0.0145); + } + } + } + timing() { + timing_type : setup_rising; + related_pin : "A_BIST_CLK"; + when : "(A_BIST_WEN & A_BIST_MEN)"; + sdf_cond : "A_BIST_W_ACCESS"; + + rise_constraint("SIG2SRAM_constraint_template") { + index_1("0.0080,0.0288,0.0616,0.1072,0.1920,0.3496,0.5952"); + index_2("0.0080,0.0288,0.0616,0.1072,0.1920,0.3496,0.5952"); + values ("-0.6208,-0.6013,-0.5749,-0.5329,-0.4519,-0.3073,-0.0866",\ +"-0.6283,-0.6088,-0.5824,-0.5404,-0.4593,-0.3148,-0.0941",\ +"-0.6379,-0.6183,-0.5920,-0.5500,-0.4689,-0.3244,-0.1037",\ +"-0.6510,-0.6315,-0.6051,-0.5631,-0.4821,-0.3375,-0.1168",\ +"-0.6753,-0.6557,-0.6294,-0.5874,-0.5063,-0.3618,-0.1411",\ +"-0.7057,-0.6862,-0.6598,-0.6178,-0.5368,-0.3922,-0.1715",\ +"-0.7873,-0.7678,-0.7414,-0.6994,-0.6184,-0.4738,-0.2531"); + } + + fall_constraint("SIG2SRAM_constraint_template") { + index_1("0.0080,0.0288,0.0616,0.1072,0.1920,0.3496,0.5952"); + index_2("0.0080,0.0288,0.0616,0.1072,0.1920,0.3496,0.5952"); + values ("-0.5652,-0.5495,-0.5212,-0.4821,-0.4011,-0.2634,-0.0515",\ +"-0.5726,-0.5570,-0.5287,-0.4896,-0.4086,-0.2709,-0.0589",\ +"-0.5822,-0.5666,-0.5383,-0.4992,-0.4181,-0.2804,-0.0685",\ +"-0.5954,-0.5797,-0.5514,-0.5123,-0.4313,-0.2936,-0.0817",\ +"-0.6196,-0.6040,-0.5757,-0.5366,-0.4555,-0.3178,-0.1059",\ +"-0.6500,-0.6344,-0.6061,-0.5670,-0.4860,-0.3483,-0.1364",\ +"-0.7317,-0.7160,-0.6877,-0.6487,-0.5676,-0.4299,-0.2180"); + } + } + + timing() { + timing_type : hold_rising; + related_pin : "A_BIST_CLK"; + when : "(A_BIST_WEN & A_BIST_MEN)"; + sdf_cond : "A_BIST_W_ACCESS"; + + rise_constraint("SIG2SRAM_constraint_template") { + index_1("0.0080,0.0288,0.0616,0.1072,0.1920,0.3496,0.5952"); + index_2("0.0080,0.0288,0.0616,0.1072,0.1920,0.3496,0.5952"); + values ("0.7376,0.7161,0.6897,0.6468,0.5677,0.4222,0.1966",\ +"0.7451,0.7236,0.6972,0.6542,0.5751,0.4296,0.2040",\ +"0.7546,0.7332,0.7068,0.6638,0.5847,0.4392,0.2136",\ +"0.7678,0.7463,0.7199,0.6770,0.5979,0.4524,0.2268",\ +"0.7921,0.7706,0.7442,0.7012,0.6221,0.4766,0.2510",\ +"0.8225,0.8010,0.7746,0.7317,0.6526,0.5071,0.2815",\ +"0.9041,0.8826,0.8562,0.8133,0.7342,0.5887,0.3631"); + } + + fall_constraint("SIG2SRAM_constraint_template") { + index_1("0.0080,0.0288,0.0616,0.1072,0.1920,0.3496,0.5952"); + index_2("0.0080,0.0288,0.0616,0.1072,0.1920,0.3496,0.5952"); + values ("0.6692,0.6526,0.6243,0.5804,0.5032,0.3655,0.1556",\ +"0.6767,0.6601,0.6318,0.5878,0.5107,0.3730,0.1630",\ +"0.6863,0.6697,0.6414,0.5974,0.5203,0.3826,0.1726",\ +"0.6994,0.6828,0.6545,0.6106,0.5334,0.3957,0.1858",\ +"0.7237,0.7071,0.6788,0.6348,0.5577,0.4200,0.2100",\ +"0.7541,0.7375,0.7092,0.6653,0.5881,0.4504,0.2404",\ +"0.8357,0.8191,0.7908,0.7469,0.6697,0.5320,0.3221"); + } + } + } + +bus(A_DOUT) { + + bus_type : D_15_0; + direction : output ; + capacitance : 0 ; + max_capacitance : 0.064 ; + memory_read() { + address : A_ADDR ; + } + pin(A_DOUT[15:0]) { + related_power_pin : VDD; + related_ground_pin : VSS; + internal_power() { + rise_power("scalar") { + values (0); + } + fall_power("scalar") { + values (0); + } + } + } + timing() { + related_pin : "A_CLK"; + timing_type : rising_edge ; + timing_sense : non_unate ; + + cell_rise(SIG2SRAM_delay_template) { + index_1("0.0080,0.0288,0.0616,0.1072,0.1920,0.3496,0.5952"); + index_2("0.0008,0.0014,0.0051,0.0100,0.0339,0.0640"); + values ("6.2500,6.2527,6.2649,6.2791,6.3317,6.3866",\ +"6.2544,6.2571,6.2692,6.2835,6.3360,6.3910",\ +"6.2648,6.2675,6.2797,6.2939,6.3465,6.4014",\ +"6.2854,6.2882,6.3003,6.3145,6.3671,6.4221",\ +"6.2997,6.3024,6.3146,6.3288,6.3814,6.4364",\ +"6.3331,6.3359,6.3480,6.3622,6.4148,6.4698",\ +"6.4188,6.4216,6.4337,6.4479,6.5005,6.5555"); + } + cell_fall(SIG2SRAM_delay_template) { + index_1("0.0080,0.0288,0.0616,0.1072,0.1920,0.3496,0.5952"); + index_2("0.0008,0.0014,0.0051,0.0100,0.0339,0.0640"); + values ("6.1398,6.1420,6.1517,6.1636,6.2071,6.2509",\ +"6.1442,6.1463,6.1561,6.1679,6.2115,6.2552",\ +"6.1546,6.1568,6.1665,6.1784,6.2219,6.2657",\ +"6.1753,6.1774,6.1872,6.1990,6.2426,6.2863",\ +"6.1895,6.1917,6.2015,6.2133,6.2569,6.3006",\ +"6.2230,6.2251,6.2349,6.2467,6.2903,6.3340",\ +"6.3087,6.3108,6.3206,6.3324,6.3760,6.4197"); + } + + rise_transition(SRAM_load_template) { + index_1("0.0008,0.0014,0.0051,0.0100,0.0339,0.0640"); + values ("0.0560,0.0583,0.0696,0.0816,0.1519,0.2335"); + } + fall_transition(SRAM_load_template) { + index_1("0.0008,0.0014,0.0051,0.0100,0.0339,0.0640"); + values ("0.0428,0.0445,0.0538,0.0658,0.1181,0.1751"); + } + } +} +cell_leakage_power : 653.2941; +} +} diff --git a/flow/platforms/ihp-sg13g2/lib/RM_IHPSG13_1P_512x16_c2_bm_bist_typ_1p20V_25C.lib b/flow/platforms/ihp-sg13g2/lib/RM_IHPSG13_1P_512x16_c2_bm_bist_typ_1p20V_25C.lib new file mode 100644 index 0000000000..747d149602 --- /dev/null +++ b/flow/platforms/ihp-sg13g2/lib/RM_IHPSG13_1P_512x16_c2_bm_bist_typ_1p20V_25C.lib @@ -0,0 +1,1519 @@ +/* ------------------------------------------------------*/ +/**/ +/* Copyright 2025 IHP PDK Authors*/ +/**/ +/* Licensed under the Apache License, Version 2.0 (the "License");*/ +/* you may not use this file except in compliance with the License.*/ +/* You may obtain a copy of the License at*/ +/* */ +/* https://www.apache.org/licenses/LICENSE-2.0*/ +/* */ +/* Unless required by applicable law or agreed to in writing, software*/ +/* distributed under the License is distributed on an "AS IS" BASIS,*/ +/* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.*/ +/* See the License for the specific language governing permissions and*/ +/* limitations under the License.*/ +/* */ +/* Generated on Wed Aug 27 12:16:35 2025 */ +/* */ +/* ------------------------------------------------------ */ +library(RM_IHPSG13_1P_512x16_c2_bm_bist_typ_1p20V_25C) { + technology (cmos) ; + delay_model : table_lookup ; + define ("add_pg_pin_to_lib", "library", "boolean"); + add_pg_pin_to_lib : true; + voltage_map ( VDD, 1.20); + voltage_map ( VDDARRAY, 1.20); + voltage_map ( VSS, 0.000000 ); + + date : "Wed Aug 27 12:16:33 2025" ; + comment : "IHP Microelectronics GmbH, 2023" ; + revision : 1.0.0 ; + simulation : true ; + nom_process : 1 ; + nom_temperature : 25 ; + nom_voltage : 1.20 ; + + operating_conditions("typ_1p20V_25C"){ + process : 1 ; + temperature : 25 ; + voltage : 1.20 ; + tree_type : "balanced_tree" ; + } + + default_operating_conditions : typ_1p20V_25C ; + default_max_transition : 1.0 ; + default_fanout_load : 1.0 ; + default_inout_pin_cap : 0.0 ; + default_input_pin_cap : 0.0 ; + default_output_pin_cap : 0.0 ; + default_cell_leakage_power : 0.0 ; + default_leakage_power_density : 0.0 ; + + slew_lower_threshold_pct_rise : 30 ; + slew_upper_threshold_pct_rise : 70 ; + input_threshold_pct_fall : 50 ; + output_threshold_pct_fall : 50 ; + input_threshold_pct_rise : 50 ; + output_threshold_pct_rise : 50 ; + slew_lower_threshold_pct_fall : 30 ; + slew_upper_threshold_pct_fall : 70 ; + slew_derate_from_library : 0.5; + k_volt_cell_leakage_power : 0.0 ; + k_temp_cell_leakage_power : 0.0 ; + k_process_cell_leakage_power : 0.0 ; + k_volt_internal_power : 0.0 ; + k_temp_internal_power : 0.0 ; + k_process_internal_power : 0.0 ; + + capacitive_load_unit (1,pf) ; + voltage_unit : "1V" ; + current_unit : "1uA" ; + time_unit : "1ns" ; + leakage_power_unit : "1nW" ; + pulling_resistance_unit : "1kohm"; + /* + ------------------------------------------------------------------------------------------ + implicit units overview: + cell_area unit : "um" + internal_power unit : "1e-12 * J/toggle = 1 * uW/MHz" + (capacitive_load_unit * voltage_unit^2) per toggle event + ------------------------------------------------------------------------------------------ + */ + library_features(report_delay_calculation); + define_cell_area (pad_drivers,pad_driver_sites) ; + + lu_table_template(CLKTRAN_constraint_template) { + variable_1 : constrained_pin_transition; + index_1 ( "0.010, 0.050, 0.200, 0.400, 1.000" ); + } + lu_table_template(SRAM_load_template) { + variable_1 : total_output_net_capacitance; + index_1 ( "0.0008,0.0014,0.0051,0.0100,0.0339,0.0640" ); + } + lu_table_template(SIG2SRAM_constraint_template) { + variable_1 : related_pin_transition; + variable_2 : constrained_pin_transition; + index_1 ( "0.0056,0.0232,0.0400,0.0728,0.1280,0.2440,0.4760" ); + index_2 ( "0.0056,0.0232,0.0400,0.0728,0.1280,0.2440,0.4760" ); + } + + lu_table_template(SIG2SRAM_delay_template) { + variable_1 : input_net_transition; + variable_2 : total_output_net_capacitance; + index_1 ( "0.0056,0.0232,0.0400,0.0728,0.1280,0.2440,0.4760" ); + index_2 ( "0.0008,0.0014,0.0051,0.0100,0.0339,0.0640" ); + } + + type (D_15_0) { + base_type : array; + data_type : bit; + bit_width : 16; + bit_from : 15; + bit_to : 0; + downto : true; + } + + type (A_8_0) { + base_type : array; + data_type : bit; + bit_width : 9; + bit_from : 8; + bit_to : 0; + downto : true; + } + +cell(RM_IHPSG13_1P_512x16_c2_bm_bist) { +pg_pin (VDD) { + pg_type : primary_power; + voltage_name : VDD; +} +pg_pin (VDDARRAY) { + pg_type : primary_power; + voltage_name : VDDARRAY; +} +pg_pin (VSS) { + pg_type : primary_ground; + voltage_name : VSS; +} + +memory() { + type : ram; + address_width : 9; + word_width : 16; +} + +interface_timing : false; +bus_naming_style : "%s[%d]" ; +area : 45309.312 ; + + pin(A_DLY) { + direction : input ; + capacitance : 0.00401111 ; + max_transition : "1" ; + related_power_pin : VDD; + related_ground_pin : VSS; + internal_power() { + rise_power("scalar") { + values (0); + } + fall_power("scalar") { + values (0); + } + } + } + +bus(A_ADDR) { + bus_type : A_8_0; + direction : input ; + capacitance : 0.00721489 ; + pin(A_ADDR[0]) { + capacitance : 0.00593979 ; + } + pin(A_ADDR[1]) { + capacitance : 0.00483009 ; + } + pin(A_ADDR[2]) { + capacitance : 0.006215 ; + } + pin(A_ADDR[3]) { + capacitance : 0.00766726 ; + } + pin(A_ADDR[4]) { + capacitance : 0.00488951 ; + } + pin(A_ADDR[5]) { + capacitance : 0.0091523 ; + } + pin(A_ADDR[6]) { + capacitance : 0.0109212 ; + } + pin(A_ADDR[7]) { + capacitance : 0.00774122 ; + } + max_transition : "0.476" ; + pin(A_ADDR[8:0]) { + related_power_pin : VDD; + related_ground_pin : VSS; + internal_power() { + when : "A_MEN"; + rise_power("scalar"){ + values (0.0110); + } + fall_power("scalar"){ + values (0.0056); + } + } + internal_power() { + when : "!A_MEN"; + rise_power("scalar"){ + values (0.0168); + } + fall_power("scalar"){ + values (0.0004); + } + } + } + timing() { + timing_type : setup_rising; + related_pin : "A_CLK"; + when : "((A_WEN | A_REN)& A_MEN)" + sdf_cond : "A_RW_ACCESS" + + rise_constraint("SIG2SRAM_constraint_template") { + index_1("0.0056,0.0232,0.0400,0.0728,0.1280,0.2440,0.4760"); + index_2("0.0056,0.0232,0.0400,0.0728,0.1280,0.2440,0.4760"); + values ("-0.4168,-0.3973,-0.3855,-0.3543,-0.3074,-0.2020,-0.0027",\ +"-0.4324,-0.4129,-0.4012,-0.3699,-0.3191,-0.2176,-0.0184",\ +"-0.4441,-0.4285,-0.4129,-0.3816,-0.3309,-0.2293,-0.0301",\ +"-0.4793,-0.4598,-0.4441,-0.4129,-0.3660,-0.2645,-0.0652",\ +"-0.5223,-0.5066,-0.4910,-0.4598,-0.4129,-0.3074,-0.1121",\ +"-0.6199,-0.6082,-0.5926,-0.5613,-0.5145,-0.4129,-0.2137",\ +"-0.8191,-0.8074,-0.7840,-0.7566,-0.7098,-0.6082,-0.4051"); + } + + fall_constraint("SIG2SRAM_constraint_template") { + index_1("0.0056,0.0232,0.0400,0.0728,0.1280,0.2440,0.4760"); + index_2("0.0056,0.0232,0.0400,0.0728,0.1280,0.2440,0.4760"); + values ("-0.3309,-0.3113,-0.2996,-0.2684,-0.2176,-0.1238,0.0637",\ +"-0.3465,-0.3309,-0.3152,-0.2840,-0.2332,-0.1395,0.0480",\ +"-0.3582,-0.3426,-0.3270,-0.2996,-0.2488,-0.1512,0.0324",\ +"-0.3895,-0.3738,-0.3582,-0.3309,-0.2801,-0.1863,0.0051",\ +"-0.4363,-0.4207,-0.4051,-0.3777,-0.3230,-0.2293,-0.0379",\ +"-0.5379,-0.5223,-0.5066,-0.4793,-0.4285,-0.3309,-0.1434",\ +"-0.7332,-0.7176,-0.7020,-0.6746,-0.6238,-0.5262,-0.3387"); + } + } + + + timing() { + timing_type : hold_rising; + related_pin : "A_CLK"; + when : "((A_WEN | A_REN)& A_MEN)" + sdf_cond : "A_RW_ACCESS" + + rise_constraint("SIG2SRAM_constraint_template") { + index_1("0.0056,0.0232,0.0400,0.0728,0.1280,0.2440,0.4760"); + index_2("0.0056,0.0232,0.0400,0.0728,0.1280,0.2440,0.4760"); + values ("0.5246,0.5051,0.4895,0.4582,0.4113,0.3059,0.1066",\ +"0.5402,0.5207,0.5051,0.4777,0.4270,0.3215,0.1223",\ +"0.5520,0.5324,0.5168,0.4895,0.4387,0.3371,0.1340",\ +"0.5832,0.5676,0.5520,0.5207,0.4738,0.3684,0.1691",\ +"0.6301,0.6105,0.5949,0.5676,0.5168,0.4113,0.2160",\ +"0.7316,0.7121,0.7004,0.6691,0.6223,0.5168,0.3176",\ +"0.9270,0.9230,0.8957,0.8645,0.8137,0.7121,0.5168"); + } + + fall_constraint("SIG2SRAM_constraint_template") { + index_1("0.0056,0.0232,0.0400,0.0728,0.1280,0.2440,0.4760"); + index_2("0.0056,0.0232,0.0400,0.0728,0.1280,0.2440,0.4760"); + values ("0.4309,0.4152,0.4035,0.3684,0.3215,0.2277,0.0363",\ +"0.4465,0.4309,0.4152,0.3879,0.3371,0.2395,0.0559",\ +"0.4582,0.4426,0.4309,0.3996,0.3488,0.2551,0.0715",\ +"0.4934,0.4777,0.4621,0.4348,0.3840,0.2863,0.0988",\ +"0.5363,0.5207,0.5051,0.4777,0.4270,0.3332,0.1418",\ +"0.6379,0.6262,0.6105,0.5793,0.5324,0.4348,0.2434",\ +"0.8332,0.8215,0.8059,0.7707,0.7238,0.6301,0.4387"); + } + } +} +pin(A_WEN) { + direction : input ; + capacitance : 0.00324098 ; + max_transition : "0.476" ; + related_power_pin : VDD; + related_ground_pin : VSS; + internal_power() { + when : "A_MEN"; + rise_power("scalar"){ + values (0.0046); + } + fall_power("scalar"){ + values (0.0039); + } + } + internal_power() { + when : "!A_MEN"; + rise_power("scalar"){ + values (0.0043); + } + fall_power("scalar"){ + values (0.0040); + } + } + timing() { + timing_type : setup_rising; + related_pin : "A_CLK"; + when : "A_MEN" + sdf_cond : "A_MEN" + + rise_constraint("SIG2SRAM_constraint_template") { + index_1("0.0056,0.0232,0.0400,0.0728,0.1280,0.2440,0.4760"); + index_2("0.0056,0.0232,0.0400,0.0728,0.1280,0.2440,0.4760"); + values ("0.2043,0.2199,0.2316,0.2629,0.3059,0.4113,0.6066",\ +"0.1887,0.2043,0.2160,0.2473,0.2941,0.3957,0.5949",\ +"0.1691,0.1848,0.2004,0.2316,0.2785,0.3801,0.5754",\ +"0.1379,0.1574,0.1691,0.2004,0.2473,0.3527,0.5480",\ +"0.0910,0.1066,0.1223,0.1535,0.2004,0.2980,0.4973",\ +"-0.0105,0.0051,0.0207,0.0520,0.0949,0.2004,0.3957",\ +"-0.2059,-0.1902,-0.1746,-0.1473,-0.1004,0.0051,0.2004"); + } + + fall_constraint("SIG2SRAM_constraint_template") { + index_1("0.0056,0.0232,0.0400,0.0728,0.1280,0.2440,0.4760"); + index_2("0.0056,0.0232,0.0400,0.0728,0.1280,0.2440,0.4760"); + values ("0.2941,0.3098,0.3215,0.3488,0.4035,0.4973,0.6887",\ +"0.2785,0.2941,0.3059,0.3332,0.3840,0.4816,0.6691",\ +"0.2629,0.2785,0.2902,0.3176,0.3684,0.4660,0.6535",\ +"0.2316,0.2473,0.2590,0.2863,0.3410,0.4348,0.6262",\ +"0.1848,0.2004,0.2121,0.2395,0.2902,0.3879,0.5754",\ +"0.0832,0.0988,0.1105,0.1379,0.1809,0.2746,0.4699",\ +"-0.1121,-0.0965,-0.0848,-0.0535,-0.0066,0.0910,0.2824"); + } + } + + + timing() { + timing_type : hold_rising; + related_pin : "A_CLK"; + when : "A_MEN" + sdf_cond : "A_MEN" + + rise_constraint("SIG2SRAM_constraint_template") { + index_1("0.0056,0.0232,0.0400,0.0728,0.1280,0.2440,0.4760"); + index_2("0.0056,0.0232,0.0400,0.0728,0.1280,0.2440,0.4760"); + values ("0.2473,0.2316,0.2160,0.1887,0.1379,0.0363,-0.1629",\ +"0.2629,0.2473,0.2316,0.2043,0.1535,0.0520,-0.1473",\ +"0.2785,0.2590,0.2434,0.2160,0.1652,0.0676,-0.1355",\ +"0.3098,0.2941,0.2785,0.2473,0.1965,0.0910,-0.1043",\ +"0.3527,0.3371,0.3215,0.2941,0.2434,0.1418,-0.0574",\ +"0.4582,0.4426,0.4270,0.3957,0.3488,0.2434,0.0480",\ +"0.6535,0.6379,0.6184,0.5910,0.5402,0.4426,0.2434"); + } + + fall_constraint("SIG2SRAM_constraint_template") { + index_1("0.0056,0.0232,0.0400,0.0728,0.1280,0.2440,0.4760"); + index_2("0.0056,0.0232,0.0400,0.0728,0.1280,0.2440,0.4760"); + values ("0.2395,0.2238,0.2121,0.1809,0.1301,0.0324,-0.1551",\ +"0.2551,0.2395,0.2277,0.1965,0.1457,0.0480,-0.1395",\ +"0.2668,0.2551,0.2395,0.2082,0.1574,0.0637,-0.1277",\ +"0.3020,0.2863,0.2707,0.2395,0.1887,0.0910,-0.0965",\ +"0.3449,0.3293,0.3176,0.2863,0.2355,0.1379,-0.0496",\ +"0.4504,0.4348,0.4191,0.3879,0.3371,0.2395,0.0559",\ +"0.6457,0.6301,0.6145,0.5871,0.5324,0.4309,0.2512"); + } + } + } +pin(A_REN) { + direction : input ; + capacitance : 0.00381634 ; + max_transition : "0.476" ; + related_power_pin : VDD; + related_ground_pin : VSS; + internal_power() { + when : "A_MEN"; + rise_power("scalar"){ + values (0.0061); + } + fall_power("scalar"){ + values (0.0021); + } + } + internal_power() { + when : "!A_MEN"; + rise_power("scalar"){ + values (0.0062); + } + fall_power("scalar"){ + values (0.0025); + } + } + timing() { + timing_type : setup_rising; + related_pin : "A_CLK"; + when : "A_MEN" + sdf_cond : "A_MEN" + + rise_constraint("SIG2SRAM_constraint_template") { + index_1("0.0056,0.0232,0.0400,0.0728,0.1280,0.2440,0.4760"); + index_2("0.0056,0.0232,0.0400,0.0728,0.1280,0.2440,0.4760"); + values ("-0.0301,-0.0145,0.0012,0.0324,0.0793,0.1809,0.3762",\ +"-0.0457,-0.0301,-0.0145,0.0168,0.0637,0.1613,0.3605",\ +"-0.0574,-0.0418,-0.0262,0.0051,0.0520,0.1496,0.3449",\ +"-0.0926,-0.0730,-0.0574,-0.0262,0.0207,0.1184,0.3137",\ +"-0.1395,-0.1238,-0.1082,-0.0770,-0.0301,0.0715,0.2707",\ +"-0.2410,-0.2254,-0.2098,-0.1746,-0.1355,-0.0340,0.1652",\ +"-0.4402,-0.4207,-0.4051,-0.3738,-0.3270,-0.2293,-0.0340"); + } + + fall_constraint("SIG2SRAM_constraint_template") { + index_1("0.0056,0.0232,0.0400,0.0728,0.1280,0.2440,0.4760"); + index_2("0.0056,0.0232,0.0400,0.0728,0.1280,0.2440,0.4760"); + values ("0.0988,0.1145,0.1262,0.1535,0.2043,0.3020,0.4855",\ +"0.0832,0.0988,0.1105,0.1418,0.1848,0.2824,0.4738",\ +"0.0676,0.0832,0.0949,0.1262,0.1730,0.2668,0.4621",\ +"0.0402,0.0559,0.0676,0.0988,0.1457,0.2434,0.4191",\ +"-0.0105,0.0012,0.0168,0.0480,0.0988,0.1965,0.3840",\ +"-0.1160,-0.0965,-0.0848,-0.0535,-0.0066,0.0988,0.2824",\ +"-0.3113,-0.2957,-0.2801,-0.2527,-0.2059,-0.1043,0.0832"); + } + } + + + timing() { + timing_type : hold_rising; + related_pin : "A_CLK"; + when : "A_MEN" + sdf_cond : "A_MEN" + + rise_constraint("SIG2SRAM_constraint_template") { + index_1("0.0056,0.0232,0.0400,0.0728,0.1280,0.2440,0.4760"); + index_2("0.0056,0.0232,0.0400,0.0728,0.1280,0.2440,0.4760"); + values ("0.2707,0.2551,0.2395,0.2121,0.1613,0.0598,-0.1395",\ +"0.2863,0.2707,0.2551,0.2238,0.1730,0.0715,-0.1238",\ +"0.2980,0.2824,0.2668,0.2395,0.1887,0.0871,-0.1121",\ +"0.3332,0.3176,0.3020,0.2707,0.2199,0.1184,-0.0809",\ +"0.3762,0.3605,0.3449,0.3176,0.2668,0.1613,-0.0340",\ +"0.4816,0.4621,0.4504,0.4191,0.3723,0.2629,0.0715",\ +"0.6770,0.6613,0.6418,0.6184,0.5637,0.4699,0.2629"); + } + + fall_constraint("SIG2SRAM_constraint_template") { + index_1("0.0056,0.0232,0.0400,0.0728,0.1280,0.2440,0.4760"); + index_2("0.0056,0.0232,0.0400,0.0728,0.1280,0.2440,0.4760"); + values ("0.2590,0.2434,0.2316,0.2004,0.1457,0.0520,-0.1355",\ +"0.2746,0.2590,0.2434,0.2160,0.1613,0.0676,-0.1199",\ +"0.2863,0.2707,0.2590,0.2277,0.1730,0.0832,-0.1082",\ +"0.3215,0.3059,0.2902,0.2590,0.2082,0.1105,-0.0770",\ +"0.3645,0.3488,0.3332,0.3059,0.2551,0.1535,-0.0340",\ +"0.4699,0.4543,0.4387,0.4074,0.3605,0.2551,0.0715",\ +"0.6652,0.6496,0.6340,0.6027,0.5520,0.4621,0.2707"); + } + } + } +pin(A_MEN) { + direction : input ; + capacitance : 0.00309605 ; + max_transition : "0.476" ; + related_power_pin : VDD; + related_ground_pin : VSS; + internal_power() { + rise_power("scalar"){ + values (0.0449); + } + fall_power("scalar"){ + values (0.0052); + } + } + timing() { + timing_type : setup_rising; + related_pin : "A_CLK"; + + rise_constraint("SIG2SRAM_constraint_template") { + index_1("0.0056,0.0232,0.0400,0.0728,0.1280,0.2440,0.4760"); + index_2("0.0056,0.0232,0.0400,0.0728,0.1280,0.2440,0.4760"); + values ("0.2043,0.2199,0.2316,0.2668,0.3098,0.4152,0.6066",\ +"0.1887,0.2043,0.2199,0.2512,0.2941,0.3996,0.5949",\ +"0.1730,0.1887,0.2043,0.2355,0.2824,0.3840,0.5793",\ +"0.1418,0.1574,0.1730,0.2043,0.2512,0.3566,0.5480",\ +"0.0949,0.1105,0.1262,0.1574,0.2043,0.3020,0.5051",\ +"-0.0066,0.0090,0.0246,0.0520,0.0988,0.2043,0.3996",\ +"-0.2020,-0.1863,-0.1746,-0.1434,-0.0965,0.0090,0.2082"); + } + + fall_constraint("SIG2SRAM_constraint_template") { + index_1("0.0056,0.0232,0.0400,0.0728,0.1280,0.2440,0.4760"); + index_2("0.0056,0.0232,0.0400,0.0728,0.1280,0.2440,0.4760"); + values ("0.2980,0.3137,0.3254,0.3527,0.4035,0.5012,0.6887",\ +"0.2824,0.2980,0.3098,0.3371,0.3879,0.4855,0.6730",\ +"0.2668,0.2824,0.2941,0.3215,0.3723,0.4699,0.6574",\ +"0.2355,0.2473,0.2629,0.2902,0.3410,0.4387,0.6262",\ +"0.1887,0.2004,0.2160,0.2395,0.2941,0.3918,0.5793",\ +"0.0871,0.1027,0.1145,0.1418,0.1848,0.2746,0.4816",\ +"-0.1082,-0.0965,-0.0809,-0.0496,-0.0027,0.0949,0.2863"); + } + } + + + timing() { + timing_type : hold_rising; + related_pin : "A_CLK"; + + rise_constraint("SIG2SRAM_constraint_template") { + index_1("0.0056,0.0232,0.0400,0.0728,0.1280,0.2440,0.4760"); + index_2("0.0056,0.0232,0.0400,0.0728,0.1280,0.2440,0.4760"); + values ("0.2512,0.2355,0.2199,0.1926,0.1418,0.0402,-0.1590",\ +"0.2668,0.2512,0.2355,0.2082,0.1574,0.0559,-0.1434",\ +"0.2824,0.2629,0.2512,0.2199,0.1691,0.0715,-0.1316",\ +"0.3137,0.2980,0.2824,0.2512,0.2004,0.0988,-0.0965",\ +"0.3566,0.3410,0.3254,0.2980,0.2473,0.1418,-0.0535",\ +"0.4621,0.4426,0.4309,0.3996,0.3527,0.2473,0.0520",\ +"0.6574,0.6418,0.6262,0.5949,0.5441,0.4465,0.2473"); + } + + fall_constraint("SIG2SRAM_constraint_template") { + index_1("0.0056,0.0232,0.0400,0.0728,0.1280,0.2440,0.4760"); + index_2("0.0056,0.0232,0.0400,0.0728,0.1280,0.2440,0.4760"); + values ("0.2395,0.2238,0.2121,0.1809,0.1301,0.0324,-0.1551",\ +"0.2551,0.2434,0.2277,0.1965,0.1457,0.0480,-0.1395",\ +"0.2707,0.2551,0.2395,0.2082,0.1574,0.0637,-0.1277",\ +"0.3020,0.2863,0.2707,0.2434,0.1926,0.0910,-0.0965",\ +"0.3449,0.3332,0.3176,0.2863,0.2355,0.1379,-0.0496",\ +"0.4504,0.4348,0.4230,0.3918,0.3410,0.2434,0.0559",\ +"0.6457,0.6301,0.6145,0.5910,0.5324,0.4387,0.2512"); + } + } + } +bus(A_BM) { + bus_type : D_15_0; + direction : input ; + capacitance : 0.00285703 ; + max_transition : "0.476" ; + pin(A_BM[15:0]) { + related_power_pin : VDD; + related_ground_pin : VSS; + internal_power() { + when : "A_MEN"; + rise_power("scalar"){ + values (0.0570); + } + fall_power("scalar"){ + values (0.0255); + } + } + internal_power() { + when : "!A_MEN"; + rise_power("scalar"){ + values (0.0603); + } + fall_power("scalar"){ + values (0.0244); + } + } + } + timing() { + timing_type : setup_rising; + related_pin : "A_CLK"; + when : "(A_WEN & A_MEN)" + sdf_cond : "A_RW_ACCESS" + + rise_constraint("SIG2SRAM_constraint_template") { + index_1("0.0056,0.0232,0.0400,0.0728,0.1280,0.2440,0.4760"); + index_2("0.0056,0.0232,0.0400,0.0728,0.1280,0.2440,0.4760"); + values ("-0.3411,-0.3245,-0.3118,-0.2796,-0.2327,-0.1282,0.0642",\ +"-0.3461,-0.3295,-0.3168,-0.2846,-0.2377,-0.1332,0.0592",\ +"-0.3506,-0.3340,-0.3213,-0.2890,-0.2422,-0.1377,0.0547",\ +"-0.3597,-0.3431,-0.3304,-0.2981,-0.2513,-0.1468,0.0456",\ +"-0.3669,-0.3503,-0.3376,-0.3054,-0.2585,-0.1540,0.0383",\ +"-0.3970,-0.3804,-0.3677,-0.3355,-0.2886,-0.1841,0.0083",\ +"-0.4546,-0.4380,-0.4253,-0.3931,-0.3462,-0.2417,-0.0493"); + } + + fall_constraint("SIG2SRAM_constraint_template") { + index_1("0.0056,0.0232,0.0400,0.0728,0.1280,0.2440,0.4760"); + index_2("0.0056,0.0232,0.0400,0.0728,0.1280,0.2440,0.4760"); + values ("-0.3089,-0.2932,-0.2805,-0.2522,-0.2014,-0.1028,0.0759",\ +"-0.3139,-0.2982,-0.2855,-0.2572,-0.2064,-0.1078,0.0709",\ +"-0.3183,-0.3027,-0.2900,-0.2617,-0.2109,-0.1123,0.0664",\ +"-0.3274,-0.3118,-0.2991,-0.2708,-0.2200,-0.1214,0.0573",\ +"-0.3347,-0.3191,-0.3064,-0.2781,-0.2273,-0.1287,0.0501",\ +"-0.3648,-0.3492,-0.3365,-0.3081,-0.2574,-0.1587,0.0200",\ +"-0.4224,-0.4068,-0.3941,-0.3657,-0.3150,-0.2163,-0.0376"); + } + } + + + timing() { + timing_type : hold_rising; + related_pin : "A_CLK"; + when : "(A_WEN & A_MEN)" + sdf_cond : "A_RW_ACCESS" + + rise_constraint("SIG2SRAM_constraint_template") { + index_1("0.0056,0.0232,0.0400,0.0728,0.1280,0.2440,0.4760"); + index_2("0.0056,0.0232,0.0400,0.0728,0.1280,0.2440,0.4760"); + values ("0.4500,0.4344,0.4217,0.3895,0.3406,0.2420,0.0457",\ +"0.4550,0.4394,0.4267,0.3945,0.3456,0.2470,0.0507",\ +"0.4595,0.4439,0.4312,0.3989,0.3501,0.2515,0.0552",\ +"0.4686,0.4530,0.4403,0.4080,0.3592,0.2606,0.0643",\ +"0.4758,0.4602,0.4475,0.4153,0.3665,0.2678,0.0716",\ +"0.5059,0.4903,0.4776,0.4454,0.3966,0.2979,0.1016",\ +"0.5635,0.5479,0.5352,0.5030,0.4542,0.3555,0.1592"); + } + + fall_constraint("SIG2SRAM_constraint_template") { + index_1("0.0056,0.0232,0.0400,0.0728,0.1280,0.2440,0.4760"); + index_2("0.0056,0.0232,0.0400,0.0728,0.1280,0.2440,0.4760"); + values ("0.4100,0.3953,0.3816,0.3533,0.3025,0.2098,0.0213",\ +"0.4150,0.4003,0.3866,0.3583,0.3075,0.2148,0.0263",\ +"0.4194,0.4048,0.3911,0.3628,0.3120,0.2193,0.0308",\ +"0.4285,0.4139,0.4002,0.3719,0.3211,0.2283,0.0399",\ +"0.4358,0.4212,0.4075,0.3792,0.3284,0.2356,0.0471",\ +"0.4659,0.4512,0.4376,0.4093,0.3585,0.2657,0.0772",\ +"0.5235,0.5089,0.4952,0.4669,0.4161,0.3233,0.1348"); + } + } +} + pin(A_CLK) { + direction : input; + capacitance : 0.00380014; + max_transition : "0.476"; + clock : "true" ; + pin_func_type : active_rising ; + + timing () { + timing_type : "min_pulse_width"; + related_pin : "A_CLK"; + rise_constraint("CLKTRAN_constraint_template") { + index_1("0.0056,0.476"); + values("0.21,0.21"); + } + } + + related_power_pin : VDD; + related_ground_pin : VSS; + + internal_power() { + when : "!A_MEN & !A_WEN & !A_REN"; + rise_power("scalar"){ + values (0); + } + fall_power("scalar"){ + values (0); + } + } + internal_power() { + when : "!A_MEN & A_WEN & !A_REN"; + rise_power("scalar"){ + values (0.5315); + } + fall_power("scalar"){ + values (0); + } + } + internal_power() { + when : "A_MEN & A_WEN & !A_REN"; + rise_power("scalar"){ + values (23.4667); + } + fall_power("scalar"){ + values (0); + } + } + internal_power() { + when : "A_MEN & A_WEN & A_REN"; + rise_power("scalar"){ + values (25.7036); + } + fall_power("scalar"){ + values (0); + } + } + internal_power() { + when : "A_MEN & !A_WEN & A_REN"; + rise_power("scalar"){ + values (19.5664); + } + fall_power("scalar"){ + values (0); + } + } + internal_power() { + when : "!A_MEN & !A_WEN & A_REN"; + rise_power("scalar"){ + values (0.3077); + } + fall_power("scalar"){ + values (0); + } + } + internal_power() { + when : "!A_MEN & A_WEN & A_REN"; + rise_power("scalar"){ + values (0.7640); + } + fall_power("scalar"){ + values (0); + } + } + internal_power() { + when : "A_MEN & !A_WEN & !A_REN"; + rise_power("scalar"){ + values (0); + } + fall_power("scalar"){ + values (0); + } + } + } + bus(A_DIN) { + bus_type : D_15_0; + direction : input ; + capacitance : 0.00365723 ; + memory_write() { + address : A_ADDR ; + clocked_on : A_CLK; + } + + max_transition : "0.476" ; + pin(A_DIN[15:0]) { + related_power_pin : VDD; + related_ground_pin : VSS; + internal_power() { + when : "A_MEN"; + rise_power("scalar"){ + values (0.0570); + } + fall_power("scalar"){ + values (0.0255); + } + } + internal_power() { + when : "!A_MEN"; + rise_power("scalar"){ + values (0.0603); + } + fall_power("scalar"){ + values (0.0244); + } + } + } + timing() { + timing_type : setup_rising; + related_pin : "A_CLK"; + when : "(A_WEN & A_MEN)"; + sdf_cond : "A_W_ACCESS"; + + rise_constraint("SIG2SRAM_constraint_template") { + index_1("0.0056,0.0232,0.0400,0.0728,0.1280,0.2440,0.4760"); + index_2("0.0056,0.0232,0.0400,0.0728,0.1280,0.2440,0.4760"); + values ("-0.3411,-0.3245,-0.3118,-0.2796,-0.2327,-0.1282,0.0642",\ +"-0.3461,-0.3295,-0.3168,-0.2846,-0.2377,-0.1332,0.0592",\ +"-0.3506,-0.3340,-0.3213,-0.2890,-0.2422,-0.1377,0.0547",\ +"-0.3597,-0.3431,-0.3304,-0.2981,-0.2513,-0.1468,0.0456",\ +"-0.3669,-0.3503,-0.3376,-0.3054,-0.2585,-0.1540,0.0383",\ +"-0.3970,-0.3804,-0.3677,-0.3355,-0.2886,-0.1841,0.0083",\ +"-0.4546,-0.4380,-0.4253,-0.3931,-0.3462,-0.2417,-0.0493"); + } + + fall_constraint("SIG2SRAM_constraint_template") { + index_1("0.0056,0.0232,0.0400,0.0728,0.1280,0.2440,0.4760"); + index_2("0.0056,0.0232,0.0400,0.0728,0.1280,0.2440,0.4760"); + values ("-0.3089,-0.2932,-0.2805,-0.2522,-0.2014,-0.1028,0.0759",\ +"-0.3139,-0.2982,-0.2855,-0.2572,-0.2064,-0.1078,0.0709",\ +"-0.3183,-0.3027,-0.2900,-0.2617,-0.2109,-0.1123,0.0664",\ +"-0.3274,-0.3118,-0.2991,-0.2708,-0.2200,-0.1214,0.0573",\ +"-0.3347,-0.3191,-0.3064,-0.2781,-0.2273,-0.1287,0.0501",\ +"-0.3648,-0.3492,-0.3365,-0.3081,-0.2574,-0.1587,0.0200",\ +"-0.4224,-0.4068,-0.3941,-0.3657,-0.3150,-0.2163,-0.0376"); + } + } + + timing() { + timing_type : hold_rising; + related_pin : "A_CLK"; + when : "(A_WEN & A_MEN)"; + sdf_cond : "A_W_ACCESS"; + + rise_constraint("SIG2SRAM_constraint_template") { + index_1("0.0056,0.0232,0.0400,0.0728,0.1280,0.2440,0.4760"); + index_2("0.0056,0.0232,0.0400,0.0728,0.1280,0.2440,0.4760"); + values ("0.4500,0.4344,0.4217,0.3895,0.3406,0.2420,0.0457",\ +"0.4550,0.4394,0.4267,0.3945,0.3456,0.2470,0.0507",\ +"0.4595,0.4439,0.4312,0.3989,0.3501,0.2515,0.0552",\ +"0.4686,0.4530,0.4403,0.4080,0.3592,0.2606,0.0643",\ +"0.4758,0.4602,0.4475,0.4153,0.3665,0.2678,0.0716",\ +"0.5059,0.4903,0.4776,0.4454,0.3966,0.2979,0.1016",\ +"0.5635,0.5479,0.5352,0.5030,0.4542,0.3555,0.1592"); + } + + fall_constraint("SIG2SRAM_constraint_template") { + index_1("0.0056,0.0232,0.0400,0.0728,0.1280,0.2440,0.4760"); + index_2("0.0056,0.0232,0.0400,0.0728,0.1280,0.2440,0.4760"); + values ("0.4100,0.3953,0.3816,0.3533,0.3025,0.2098,0.0213",\ +"0.4150,0.4003,0.3866,0.3583,0.3075,0.2148,0.0263",\ +"0.4194,0.4048,0.3911,0.3628,0.3120,0.2193,0.0308",\ +"0.4285,0.4139,0.4002,0.3719,0.3211,0.2283,0.0399",\ +"0.4358,0.4212,0.4075,0.3792,0.3284,0.2356,0.0471",\ +"0.4659,0.4512,0.4376,0.4093,0.3585,0.2657,0.0772",\ +"0.5235,0.5089,0.4952,0.4669,0.4161,0.3233,0.1348"); + } + } + } + + pin(A_BIST_EN) { + direction : input ; + capacitance : 0.00401111 ; + max_transition : "1" ; + related_power_pin : VDD; + related_ground_pin : VSS; + internal_power() { + rise_power("scalar") { + values (0); + } + fall_power("scalar") { + values (0); + } + } + } + +bus(A_BIST_ADDR) { + bus_type : A_8_0; + direction : input ; + capacitance : 0.00721489 ; + pin(A_BIST_ADDR[0]) { + capacitance : 0.00593979 ; + } + pin(A_BIST_ADDR[1]) { + capacitance : 0.00483009 ; + } + pin(A_BIST_ADDR[2]) { + capacitance : 0.006215 ; + } + pin(A_BIST_ADDR[3]) { + capacitance : 0.00766726 ; + } + pin(A_BIST_ADDR[4]) { + capacitance : 0.00488951 ; + } + pin(A_BIST_ADDR[5]) { + capacitance : 0.0091523 ; + } + pin(A_BIST_ADDR[6]) { + capacitance : 0.0109212 ; + } + pin(A_BIST_ADDR[7]) { + capacitance : 0.00774122 ; + } + max_transition : "0.476" ; + pin(A_BIST_ADDR[8:0]) { + related_power_pin : VDD; + related_ground_pin : VSS; + internal_power() { + when : "A_BIST_MEN"; + rise_power("scalar"){ + values (0.0110); + } + fall_power("scalar"){ + values (0.0056); + } + } + internal_power() { + when : "!A_BIST_MEN"; + rise_power("scalar"){ + values (0.0168); + } + fall_power("scalar"){ + values (0.0004); + } + } + } + timing() { + timing_type : setup_rising; + related_pin : "A_BIST_CLK"; + when : "((A_BIST_WEN | A_BIST_REN)& A_BIST_MEN)" + sdf_cond : "A_BIST_RW_ACCESS" + + rise_constraint("SIG2SRAM_constraint_template") { + index_1("0.0056,0.0232,0.0400,0.0728,0.1280,0.2440,0.4760"); + index_2("0.0056,0.0232,0.0400,0.0728,0.1280,0.2440,0.4760"); + values ("-0.4168,-0.3973,-0.3855,-0.3543,-0.3074,-0.2020,-0.0027",\ +"-0.4324,-0.4129,-0.4012,-0.3699,-0.3191,-0.2176,-0.0184",\ +"-0.4441,-0.4285,-0.4129,-0.3816,-0.3309,-0.2293,-0.0301",\ +"-0.4793,-0.4598,-0.4441,-0.4129,-0.3660,-0.2645,-0.0652",\ +"-0.5223,-0.5066,-0.4910,-0.4598,-0.4129,-0.3074,-0.1121",\ +"-0.6199,-0.6082,-0.5926,-0.5613,-0.5145,-0.4129,-0.2137",\ +"-0.8191,-0.8074,-0.7840,-0.7566,-0.7098,-0.6082,-0.4051"); + } + + fall_constraint("SIG2SRAM_constraint_template") { + index_1("0.0056,0.0232,0.0400,0.0728,0.1280,0.2440,0.4760"); + index_2("0.0056,0.0232,0.0400,0.0728,0.1280,0.2440,0.4760"); + values ("-0.3309,-0.3113,-0.2996,-0.2684,-0.2176,-0.1238,0.0637",\ +"-0.3465,-0.3309,-0.3152,-0.2840,-0.2332,-0.1395,0.0480",\ +"-0.3582,-0.3426,-0.3270,-0.2996,-0.2488,-0.1512,0.0324",\ +"-0.3895,-0.3738,-0.3582,-0.3309,-0.2801,-0.1863,0.0051",\ +"-0.4363,-0.4207,-0.4051,-0.3777,-0.3230,-0.2293,-0.0379",\ +"-0.5379,-0.5223,-0.5066,-0.4793,-0.4285,-0.3309,-0.1434",\ +"-0.7332,-0.7176,-0.7020,-0.6746,-0.6238,-0.5262,-0.3387"); + } + } + + + timing() { + timing_type : hold_rising; + related_pin : "A_BIST_CLK"; + when : "((A_BIST_WEN | A_BIST_REN)& A_BIST_MEN)" + sdf_cond : "A_BIST_RW_ACCESS" + + rise_constraint("SIG2SRAM_constraint_template") { + index_1("0.0056,0.0232,0.0400,0.0728,0.1280,0.2440,0.4760"); + index_2("0.0056,0.0232,0.0400,0.0728,0.1280,0.2440,0.4760"); + values ("0.5246,0.5051,0.4895,0.4582,0.4113,0.3059,0.1066",\ +"0.5402,0.5207,0.5051,0.4777,0.4270,0.3215,0.1223",\ +"0.5520,0.5324,0.5168,0.4895,0.4387,0.3371,0.1340",\ +"0.5832,0.5676,0.5520,0.5207,0.4738,0.3684,0.1691",\ +"0.6301,0.6105,0.5949,0.5676,0.5168,0.4113,0.2160",\ +"0.7316,0.7121,0.7004,0.6691,0.6223,0.5168,0.3176",\ +"0.9270,0.9230,0.8957,0.8645,0.8137,0.7121,0.5168"); + } + + fall_constraint("SIG2SRAM_constraint_template") { + index_1("0.0056,0.0232,0.0400,0.0728,0.1280,0.2440,0.4760"); + index_2("0.0056,0.0232,0.0400,0.0728,0.1280,0.2440,0.4760"); + values ("0.4309,0.4152,0.4035,0.3684,0.3215,0.2277,0.0363",\ +"0.4465,0.4309,0.4152,0.3879,0.3371,0.2395,0.0559",\ +"0.4582,0.4426,0.4309,0.3996,0.3488,0.2551,0.0715",\ +"0.4934,0.4777,0.4621,0.4348,0.3840,0.2863,0.0988",\ +"0.5363,0.5207,0.5051,0.4777,0.4270,0.3332,0.1418",\ +"0.6379,0.6262,0.6105,0.5793,0.5324,0.4348,0.2434",\ +"0.8332,0.8215,0.8059,0.7707,0.7238,0.6301,0.4387"); + } + } +} +pin(A_BIST_WEN) { + direction : input ; + capacitance : 0.00324098 ; + max_transition : "0.476" ; + related_power_pin : VDD; + related_ground_pin : VSS; + internal_power() { + when : "A_BIST_MEN"; + rise_power("scalar"){ + values (0.0046); + } + fall_power("scalar"){ + values (0.0039); + } + } + internal_power() { + when : "!A_BIST_MEN"; + rise_power("scalar"){ + values (0.0043); + } + fall_power("scalar"){ + values (0.0040); + } + } + timing() { + timing_type : setup_rising; + related_pin : "A_BIST_CLK"; + when : "A_BIST_MEN" + sdf_cond : "A_BIST_MEN" + + rise_constraint("SIG2SRAM_constraint_template") { + index_1("0.0056,0.0232,0.0400,0.0728,0.1280,0.2440,0.4760"); + index_2("0.0056,0.0232,0.0400,0.0728,0.1280,0.2440,0.4760"); + values ("0.2043,0.2199,0.2316,0.2629,0.3059,0.4113,0.6066",\ +"0.1887,0.2043,0.2160,0.2473,0.2941,0.3957,0.5949",\ +"0.1691,0.1848,0.2004,0.2316,0.2785,0.3801,0.5754",\ +"0.1379,0.1574,0.1691,0.2004,0.2473,0.3527,0.5480",\ +"0.0910,0.1066,0.1223,0.1535,0.2004,0.2980,0.4973",\ +"-0.0105,0.0051,0.0207,0.0520,0.0949,0.2004,0.3957",\ +"-0.2059,-0.1902,-0.1746,-0.1473,-0.1004,0.0051,0.2004"); + } + + fall_constraint("SIG2SRAM_constraint_template") { + index_1("0.0056,0.0232,0.0400,0.0728,0.1280,0.2440,0.4760"); + index_2("0.0056,0.0232,0.0400,0.0728,0.1280,0.2440,0.4760"); + values ("0.2941,0.3098,0.3215,0.3488,0.4035,0.4973,0.6887",\ +"0.2785,0.2941,0.3059,0.3332,0.3840,0.4816,0.6691",\ +"0.2629,0.2785,0.2902,0.3176,0.3684,0.4660,0.6535",\ +"0.2316,0.2473,0.2590,0.2863,0.3410,0.4348,0.6262",\ +"0.1848,0.2004,0.2121,0.2395,0.2902,0.3879,0.5754",\ +"0.0832,0.0988,0.1105,0.1379,0.1809,0.2746,0.4699",\ +"-0.1121,-0.0965,-0.0848,-0.0535,-0.0066,0.0910,0.2824"); + } + } + + + timing() { + timing_type : hold_rising; + related_pin : "A_BIST_CLK"; + when : "A_BIST_MEN" + sdf_cond : "A_BIST_MEN" + + rise_constraint("SIG2SRAM_constraint_template") { + index_1("0.0056,0.0232,0.0400,0.0728,0.1280,0.2440,0.4760"); + index_2("0.0056,0.0232,0.0400,0.0728,0.1280,0.2440,0.4760"); + values ("0.2473,0.2316,0.2160,0.1887,0.1379,0.0363,-0.1629",\ +"0.2629,0.2473,0.2316,0.2043,0.1535,0.0520,-0.1473",\ +"0.2785,0.2590,0.2434,0.2160,0.1652,0.0676,-0.1355",\ +"0.3098,0.2941,0.2785,0.2473,0.1965,0.0910,-0.1043",\ +"0.3527,0.3371,0.3215,0.2941,0.2434,0.1418,-0.0574",\ +"0.4582,0.4426,0.4270,0.3957,0.3488,0.2434,0.0480",\ +"0.6535,0.6379,0.6184,0.5910,0.5402,0.4426,0.2434"); + } + + fall_constraint("SIG2SRAM_constraint_template") { + index_1("0.0056,0.0232,0.0400,0.0728,0.1280,0.2440,0.4760"); + index_2("0.0056,0.0232,0.0400,0.0728,0.1280,0.2440,0.4760"); + values ("0.2395,0.2238,0.2121,0.1809,0.1301,0.0324,-0.1551",\ +"0.2551,0.2395,0.2277,0.1965,0.1457,0.0480,-0.1395",\ +"0.2668,0.2551,0.2395,0.2082,0.1574,0.0637,-0.1277",\ +"0.3020,0.2863,0.2707,0.2395,0.1887,0.0910,-0.0965",\ +"0.3449,0.3293,0.3176,0.2863,0.2355,0.1379,-0.0496",\ +"0.4504,0.4348,0.4191,0.3879,0.3371,0.2395,0.0559",\ +"0.6457,0.6301,0.6145,0.5871,0.5324,0.4309,0.2512"); + } + } + } +pin(A_BIST_REN) { + direction : input ; + capacitance : 0.00381634 ; + max_transition : "0.476" ; + related_power_pin : VDD; + related_ground_pin : VSS; + internal_power() { + when : "A_BIST_MEN"; + rise_power("scalar"){ + values (0.0061); + } + fall_power("scalar"){ + values (0.0021); + } + } + internal_power() { + when : "!A_BIST_MEN"; + rise_power("scalar"){ + values (0.0062); + } + fall_power("scalar"){ + values (0.0025); + } + } + timing() { + timing_type : setup_rising; + related_pin : "A_BIST_CLK"; + when : "A_BIST_MEN" + sdf_cond : "A_BIST_MEN" + + rise_constraint("SIG2SRAM_constraint_template") { + index_1("0.0056,0.0232,0.0400,0.0728,0.1280,0.2440,0.4760"); + index_2("0.0056,0.0232,0.0400,0.0728,0.1280,0.2440,0.4760"); + values ("-0.0301,-0.0145,0.0012,0.0324,0.0793,0.1809,0.3762",\ +"-0.0457,-0.0301,-0.0145,0.0168,0.0637,0.1613,0.3605",\ +"-0.0574,-0.0418,-0.0262,0.0051,0.0520,0.1496,0.3449",\ +"-0.0926,-0.0730,-0.0574,-0.0262,0.0207,0.1184,0.3137",\ +"-0.1395,-0.1238,-0.1082,-0.0770,-0.0301,0.0715,0.2707",\ +"-0.2410,-0.2254,-0.2098,-0.1746,-0.1355,-0.0340,0.1652",\ +"-0.4402,-0.4207,-0.4051,-0.3738,-0.3270,-0.2293,-0.0340"); + } + + fall_constraint("SIG2SRAM_constraint_template") { + index_1("0.0056,0.0232,0.0400,0.0728,0.1280,0.2440,0.4760"); + index_2("0.0056,0.0232,0.0400,0.0728,0.1280,0.2440,0.4760"); + values ("0.0988,0.1145,0.1262,0.1535,0.2043,0.3020,0.4855",\ +"0.0832,0.0988,0.1105,0.1418,0.1848,0.2824,0.4738",\ +"0.0676,0.0832,0.0949,0.1262,0.1730,0.2668,0.4621",\ +"0.0402,0.0559,0.0676,0.0988,0.1457,0.2434,0.4191",\ +"-0.0105,0.0012,0.0168,0.0480,0.0988,0.1965,0.3840",\ +"-0.1160,-0.0965,-0.0848,-0.0535,-0.0066,0.0988,0.2824",\ +"-0.3113,-0.2957,-0.2801,-0.2527,-0.2059,-0.1043,0.0832"); + } + } + + + timing() { + timing_type : hold_rising; + related_pin : "A_BIST_CLK"; + when : "A_BIST_MEN" + sdf_cond : "A_BIST_MEN" + + rise_constraint("SIG2SRAM_constraint_template") { + index_1("0.0056,0.0232,0.0400,0.0728,0.1280,0.2440,0.4760"); + index_2("0.0056,0.0232,0.0400,0.0728,0.1280,0.2440,0.4760"); + values ("0.2707,0.2551,0.2395,0.2121,0.1613,0.0598,-0.1395",\ +"0.2863,0.2707,0.2551,0.2238,0.1730,0.0715,-0.1238",\ +"0.2980,0.2824,0.2668,0.2395,0.1887,0.0871,-0.1121",\ +"0.3332,0.3176,0.3020,0.2707,0.2199,0.1184,-0.0809",\ +"0.3762,0.3605,0.3449,0.3176,0.2668,0.1613,-0.0340",\ +"0.4816,0.4621,0.4504,0.4191,0.3723,0.2629,0.0715",\ +"0.6770,0.6613,0.6418,0.6184,0.5637,0.4699,0.2629"); + } + + fall_constraint("SIG2SRAM_constraint_template") { + index_1("0.0056,0.0232,0.0400,0.0728,0.1280,0.2440,0.4760"); + index_2("0.0056,0.0232,0.0400,0.0728,0.1280,0.2440,0.4760"); + values ("0.2590,0.2434,0.2316,0.2004,0.1457,0.0520,-0.1355",\ +"0.2746,0.2590,0.2434,0.2160,0.1613,0.0676,-0.1199",\ +"0.2863,0.2707,0.2590,0.2277,0.1730,0.0832,-0.1082",\ +"0.3215,0.3059,0.2902,0.2590,0.2082,0.1105,-0.0770",\ +"0.3645,0.3488,0.3332,0.3059,0.2551,0.1535,-0.0340",\ +"0.4699,0.4543,0.4387,0.4074,0.3605,0.2551,0.0715",\ +"0.6652,0.6496,0.6340,0.6027,0.5520,0.4621,0.2707"); + } + } + } +pin(A_BIST_MEN) { + direction : input ; + capacitance : 0.00309605 ; + max_transition : "0.476" ; + related_power_pin : VDD; + related_ground_pin : VSS; + internal_power() { + rise_power("scalar"){ + values (0.0449); + } + fall_power("scalar"){ + values (0.0052); + } + } + timing() { + timing_type : setup_rising; + related_pin : "A_BIST_CLK"; + + rise_constraint("SIG2SRAM_constraint_template") { + index_1("0.0056,0.0232,0.0400,0.0728,0.1280,0.2440,0.4760"); + index_2("0.0056,0.0232,0.0400,0.0728,0.1280,0.2440,0.4760"); + values ("0.2043,0.2199,0.2316,0.2668,0.3098,0.4152,0.6066",\ +"0.1887,0.2043,0.2199,0.2512,0.2941,0.3996,0.5949",\ +"0.1730,0.1887,0.2043,0.2355,0.2824,0.3840,0.5793",\ +"0.1418,0.1574,0.1730,0.2043,0.2512,0.3566,0.5480",\ +"0.0949,0.1105,0.1262,0.1574,0.2043,0.3020,0.5051",\ +"-0.0066,0.0090,0.0246,0.0520,0.0988,0.2043,0.3996",\ +"-0.2020,-0.1863,-0.1746,-0.1434,-0.0965,0.0090,0.2082"); + } + + fall_constraint("SIG2SRAM_constraint_template") { + index_1("0.0056,0.0232,0.0400,0.0728,0.1280,0.2440,0.4760"); + index_2("0.0056,0.0232,0.0400,0.0728,0.1280,0.2440,0.4760"); + values ("0.2980,0.3137,0.3254,0.3527,0.4035,0.5012,0.6887",\ +"0.2824,0.2980,0.3098,0.3371,0.3879,0.4855,0.6730",\ +"0.2668,0.2824,0.2941,0.3215,0.3723,0.4699,0.6574",\ +"0.2355,0.2473,0.2629,0.2902,0.3410,0.4387,0.6262",\ +"0.1887,0.2004,0.2160,0.2395,0.2941,0.3918,0.5793",\ +"0.0871,0.1027,0.1145,0.1418,0.1848,0.2746,0.4816",\ +"-0.1082,-0.0965,-0.0809,-0.0496,-0.0027,0.0949,0.2863"); + } + } + + + timing() { + timing_type : hold_rising; + related_pin : "A_BIST_CLK"; + + rise_constraint("SIG2SRAM_constraint_template") { + index_1("0.0056,0.0232,0.0400,0.0728,0.1280,0.2440,0.4760"); + index_2("0.0056,0.0232,0.0400,0.0728,0.1280,0.2440,0.4760"); + values ("0.2512,0.2355,0.2199,0.1926,0.1418,0.0402,-0.1590",\ +"0.2668,0.2512,0.2355,0.2082,0.1574,0.0559,-0.1434",\ +"0.2824,0.2629,0.2512,0.2199,0.1691,0.0715,-0.1316",\ +"0.3137,0.2980,0.2824,0.2512,0.2004,0.0988,-0.0965",\ +"0.3566,0.3410,0.3254,0.2980,0.2473,0.1418,-0.0535",\ +"0.4621,0.4426,0.4309,0.3996,0.3527,0.2473,0.0520",\ +"0.6574,0.6418,0.6262,0.5949,0.5441,0.4465,0.2473"); + } + + fall_constraint("SIG2SRAM_constraint_template") { + index_1("0.0056,0.0232,0.0400,0.0728,0.1280,0.2440,0.4760"); + index_2("0.0056,0.0232,0.0400,0.0728,0.1280,0.2440,0.4760"); + values ("0.2395,0.2238,0.2121,0.1809,0.1301,0.0324,-0.1551",\ +"0.2551,0.2434,0.2277,0.1965,0.1457,0.0480,-0.1395",\ +"0.2707,0.2551,0.2395,0.2082,0.1574,0.0637,-0.1277",\ +"0.3020,0.2863,0.2707,0.2434,0.1926,0.0910,-0.0965",\ +"0.3449,0.3332,0.3176,0.2863,0.2355,0.1379,-0.0496",\ +"0.4504,0.4348,0.4230,0.3918,0.3410,0.2434,0.0559",\ +"0.6457,0.6301,0.6145,0.5910,0.5324,0.4387,0.2512"); + } + } + } +bus(A_BIST_BM) { + bus_type : D_15_0; + direction : input ; + capacitance : 0.00238379 ; + max_transition : "0.476" ; + pin(A_BIST_BM[15:0]) { + related_power_pin : VDD; + related_ground_pin : VSS; + internal_power() { + when : "A_BIST_MEN"; + rise_power("scalar"){ + values (0.0570); + } + fall_power("scalar"){ + values (0.0255); + } + } + internal_power() { + when : "!A_BIST_MEN"; + rise_power("scalar"){ + values (0.0603); + } + fall_power("scalar"){ + values (0.0244); + } + } + } + timing() { + timing_type : setup_rising; + related_pin : "A_BIST_CLK"; + when : "(A_BIST_WEN & A_BIST_MEN)" + sdf_cond : "A_BIST_RW_ACCESS" + + rise_constraint("SIG2SRAM_constraint_template") { + index_1("0.0056,0.0232,0.0400,0.0728,0.1280,0.2440,0.4760"); + index_2("0.0056,0.0232,0.0400,0.0728,0.1280,0.2440,0.4760"); + values ("-0.3411,-0.3245,-0.3118,-0.2796,-0.2327,-0.1282,0.0642",\ +"-0.3461,-0.3295,-0.3168,-0.2846,-0.2377,-0.1332,0.0592",\ +"-0.3506,-0.3340,-0.3213,-0.2890,-0.2422,-0.1377,0.0547",\ +"-0.3597,-0.3431,-0.3304,-0.2981,-0.2513,-0.1468,0.0456",\ +"-0.3669,-0.3503,-0.3376,-0.3054,-0.2585,-0.1540,0.0383",\ +"-0.3970,-0.3804,-0.3677,-0.3355,-0.2886,-0.1841,0.0083",\ +"-0.4546,-0.4380,-0.4253,-0.3931,-0.3462,-0.2417,-0.0493"); + } + + fall_constraint("SIG2SRAM_constraint_template") { + index_1("0.0056,0.0232,0.0400,0.0728,0.1280,0.2440,0.4760"); + index_2("0.0056,0.0232,0.0400,0.0728,0.1280,0.2440,0.4760"); + values ("-0.3089,-0.2932,-0.2805,-0.2522,-0.2014,-0.1028,0.0759",\ +"-0.3139,-0.2982,-0.2855,-0.2572,-0.2064,-0.1078,0.0709",\ +"-0.3183,-0.3027,-0.2900,-0.2617,-0.2109,-0.1123,0.0664",\ +"-0.3274,-0.3118,-0.2991,-0.2708,-0.2200,-0.1214,0.0573",\ +"-0.3347,-0.3191,-0.3064,-0.2781,-0.2273,-0.1287,0.0501",\ +"-0.3648,-0.3492,-0.3365,-0.3081,-0.2574,-0.1587,0.0200",\ +"-0.4224,-0.4068,-0.3941,-0.3657,-0.3150,-0.2163,-0.0376"); + } + } + + + timing() { + timing_type : hold_rising; + related_pin : "A_BIST_CLK"; + when : "(A_BIST_WEN & A_BIST_MEN)" + sdf_cond : "A_BIST_RW_ACCESS" + + rise_constraint("SIG2SRAM_constraint_template") { + index_1("0.0056,0.0232,0.0400,0.0728,0.1280,0.2440,0.4760"); + index_2("0.0056,0.0232,0.0400,0.0728,0.1280,0.2440,0.4760"); + values ("0.4500,0.4344,0.4217,0.3895,0.3406,0.2420,0.0457",\ +"0.4550,0.4394,0.4267,0.3945,0.3456,0.2470,0.0507",\ +"0.4595,0.4439,0.4312,0.3989,0.3501,0.2515,0.0552",\ +"0.4686,0.4530,0.4403,0.4080,0.3592,0.2606,0.0643",\ +"0.4758,0.4602,0.4475,0.4153,0.3665,0.2678,0.0716",\ +"0.5059,0.4903,0.4776,0.4454,0.3966,0.2979,0.1016",\ +"0.5635,0.5479,0.5352,0.5030,0.4542,0.3555,0.1592"); + } + + fall_constraint("SIG2SRAM_constraint_template") { + index_1("0.0056,0.0232,0.0400,0.0728,0.1280,0.2440,0.4760"); + index_2("0.0056,0.0232,0.0400,0.0728,0.1280,0.2440,0.4760"); + values ("0.4100,0.3953,0.3816,0.3533,0.3025,0.2098,0.0213",\ +"0.4150,0.4003,0.3866,0.3583,0.3075,0.2148,0.0263",\ +"0.4194,0.4048,0.3911,0.3628,0.3120,0.2193,0.0308",\ +"0.4285,0.4139,0.4002,0.3719,0.3211,0.2283,0.0399",\ +"0.4358,0.4212,0.4075,0.3792,0.3284,0.2356,0.0471",\ +"0.4659,0.4512,0.4376,0.4093,0.3585,0.2657,0.0772",\ +"0.5235,0.5089,0.4952,0.4669,0.4161,0.3233,0.1348"); + } + } +} + pin(A_BIST_CLK) { + direction : input; + capacitance : 0.00380014; + max_transition : "0.476"; + clock : "true" ; + pin_func_type : active_rising ; + + timing () { + timing_type : "min_pulse_width"; + related_pin : "A_BIST_CLK"; + rise_constraint("CLKTRAN_constraint_template") { + index_1("0.0056,0.476"); + values("0.21,0.21"); + } + } + + related_power_pin : VDD; + related_ground_pin : VSS; + + internal_power() { + when : "!A_BIST_MEN & !A_BIST_WEN & !A_BIST_REN"; + rise_power("scalar"){ + values (0); + } + fall_power("scalar"){ + values (0); + } + } + internal_power() { + when : "!A_BIST_MEN & A_BIST_WEN & !A_BIST_REN"; + rise_power("scalar"){ + values (0.5315); + } + fall_power("scalar"){ + values (0); + } + } + internal_power() { + when : "A_BIST_MEN & A_BIST_WEN & !A_BIST_REN"; + rise_power("scalar"){ + values (23.4667); + } + fall_power("scalar"){ + values (0); + } + } + internal_power() { + when : "A_BIST_MEN & A_BIST_WEN & A_BIST_REN"; + rise_power("scalar"){ + values (25.7036); + } + fall_power("scalar"){ + values (0); + } + } + internal_power() { + when : "A_BIST_MEN & !A_BIST_WEN & A_BIST_REN"; + rise_power("scalar"){ + values (19.5664); + } + fall_power("scalar"){ + values (0); + } + } + internal_power() { + when : "!A_BIST_MEN & !A_BIST_WEN & A_BIST_REN"; + rise_power("scalar"){ + values (0.3077); + } + fall_power("scalar"){ + values (0); + } + } + internal_power() { + when : "!A_BIST_MEN & A_BIST_WEN & A_BIST_REN"; + rise_power("scalar"){ + values (0.7640); + } + fall_power("scalar"){ + values (0); + } + } + internal_power() { + when : "A_BIST_MEN & !A_BIST_WEN & !A_BIST_REN"; + rise_power("scalar"){ + values (0); + } + fall_power("scalar"){ + values (0); + } + } + } + bus(A_BIST_DIN) { + bus_type : D_15_0; + direction : input ; + capacitance : 0.00233858 ; + memory_write() { + address : A_BIST_ADDR ; + clocked_on : A_BIST_CLK; + } + + max_transition : "0.476" ; + pin(A_BIST_DIN[15:0]) { + related_power_pin : VDD; + related_ground_pin : VSS; + internal_power() { + when : "A_BIST_MEN"; + rise_power("scalar"){ + values (0.0570); + } + fall_power("scalar"){ + values (0.0255); + } + } + internal_power() { + when : "!A_BIST_MEN"; + rise_power("scalar"){ + values (0.0603); + } + fall_power("scalar"){ + values (0.0244); + } + } + } + timing() { + timing_type : setup_rising; + related_pin : "A_BIST_CLK"; + when : "(A_BIST_WEN & A_BIST_MEN)"; + sdf_cond : "A_BIST_W_ACCESS"; + + rise_constraint("SIG2SRAM_constraint_template") { + index_1("0.0056,0.0232,0.0400,0.0728,0.1280,0.2440,0.4760"); + index_2("0.0056,0.0232,0.0400,0.0728,0.1280,0.2440,0.4760"); + values ("-0.3411,-0.3245,-0.3118,-0.2796,-0.2327,-0.1282,0.0642",\ +"-0.3461,-0.3295,-0.3168,-0.2846,-0.2377,-0.1332,0.0592",\ +"-0.3506,-0.3340,-0.3213,-0.2890,-0.2422,-0.1377,0.0547",\ +"-0.3597,-0.3431,-0.3304,-0.2981,-0.2513,-0.1468,0.0456",\ +"-0.3669,-0.3503,-0.3376,-0.3054,-0.2585,-0.1540,0.0383",\ +"-0.3970,-0.3804,-0.3677,-0.3355,-0.2886,-0.1841,0.0083",\ +"-0.4546,-0.4380,-0.4253,-0.3931,-0.3462,-0.2417,-0.0493"); + } + + fall_constraint("SIG2SRAM_constraint_template") { + index_1("0.0056,0.0232,0.0400,0.0728,0.1280,0.2440,0.4760"); + index_2("0.0056,0.0232,0.0400,0.0728,0.1280,0.2440,0.4760"); + values ("-0.3089,-0.2932,-0.2805,-0.2522,-0.2014,-0.1028,0.0759",\ +"-0.3139,-0.2982,-0.2855,-0.2572,-0.2064,-0.1078,0.0709",\ +"-0.3183,-0.3027,-0.2900,-0.2617,-0.2109,-0.1123,0.0664",\ +"-0.3274,-0.3118,-0.2991,-0.2708,-0.2200,-0.1214,0.0573",\ +"-0.3347,-0.3191,-0.3064,-0.2781,-0.2273,-0.1287,0.0501",\ +"-0.3648,-0.3492,-0.3365,-0.3081,-0.2574,-0.1587,0.0200",\ +"-0.4224,-0.4068,-0.3941,-0.3657,-0.3150,-0.2163,-0.0376"); + } + } + + timing() { + timing_type : hold_rising; + related_pin : "A_BIST_CLK"; + when : "(A_BIST_WEN & A_BIST_MEN)"; + sdf_cond : "A_BIST_W_ACCESS"; + + rise_constraint("SIG2SRAM_constraint_template") { + index_1("0.0056,0.0232,0.0400,0.0728,0.1280,0.2440,0.4760"); + index_2("0.0056,0.0232,0.0400,0.0728,0.1280,0.2440,0.4760"); + values ("0.4500,0.4344,0.4217,0.3895,0.3406,0.2420,0.0457",\ +"0.4550,0.4394,0.4267,0.3945,0.3456,0.2470,0.0507",\ +"0.4595,0.4439,0.4312,0.3989,0.3501,0.2515,0.0552",\ +"0.4686,0.4530,0.4403,0.4080,0.3592,0.2606,0.0643",\ +"0.4758,0.4602,0.4475,0.4153,0.3665,0.2678,0.0716",\ +"0.5059,0.4903,0.4776,0.4454,0.3966,0.2979,0.1016",\ +"0.5635,0.5479,0.5352,0.5030,0.4542,0.3555,0.1592"); + } + + fall_constraint("SIG2SRAM_constraint_template") { + index_1("0.0056,0.0232,0.0400,0.0728,0.1280,0.2440,0.4760"); + index_2("0.0056,0.0232,0.0400,0.0728,0.1280,0.2440,0.4760"); + values ("0.4100,0.3953,0.3816,0.3533,0.3025,0.2098,0.0213",\ +"0.4150,0.4003,0.3866,0.3583,0.3075,0.2148,0.0263",\ +"0.4194,0.4048,0.3911,0.3628,0.3120,0.2193,0.0308",\ +"0.4285,0.4139,0.4002,0.3719,0.3211,0.2283,0.0399",\ +"0.4358,0.4212,0.4075,0.3792,0.3284,0.2356,0.0471",\ +"0.4659,0.4512,0.4376,0.4093,0.3585,0.2657,0.0772",\ +"0.5235,0.5089,0.4952,0.4669,0.4161,0.3233,0.1348"); + } + } + } + +bus(A_DOUT) { + + bus_type : D_15_0; + direction : output ; + capacitance : 0 ; + max_capacitance : 0.064 ; + memory_read() { + address : A_ADDR ; + } + pin(A_DOUT[15:0]) { + related_power_pin : VDD; + related_ground_pin : VSS; + internal_power() { + rise_power("scalar") { + values (0); + } + fall_power("scalar") { + values (0); + } + } + } + timing() { + related_pin : "A_CLK"; + timing_type : rising_edge ; + timing_sense : non_unate ; + + cell_rise(SIG2SRAM_delay_template) { + index_1("0.0056,0.0232,0.0400,0.0728,0.1280,0.2440,0.4760"); + index_2("0.0008,0.0014,0.0051,0.0100,0.0339,0.0640"); + values ("3.7316,3.7332,3.7409,3.7496,3.7820,3.8179",\ +"3.7368,3.7384,3.7461,3.7548,3.7872,3.8231",\ +"3.7400,3.7416,3.7492,3.7579,3.7904,3.8262",\ +"3.7524,3.7540,3.7617,3.7704,3.8029,3.8387",\ +"3.7583,3.7599,3.7675,3.7762,3.8087,3.8445",\ +"3.7892,3.7908,3.7985,3.8072,3.8396,3.8755",\ +"3.8449,3.8465,3.8542,3.8629,3.8954,3.9312"); + } + cell_fall(SIG2SRAM_delay_template) { + index_1("0.0056,0.0232,0.0400,0.0728,0.1280,0.2440,0.4760"); + index_2("0.0008,0.0014,0.0051,0.0100,0.0339,0.0640"); + values ("3.6705,3.6719,3.6779,3.6850,3.7115,3.7382",\ +"3.6757,3.6770,3.6830,3.6902,3.7167,3.7433",\ +"3.6789,3.6802,3.6862,3.6934,3.7199,3.7465",\ +"3.6914,3.6927,3.6987,3.7059,3.7324,3.7590",\ +"3.6972,3.6985,3.7045,3.7117,3.7382,3.7648",\ +"3.7282,3.7295,3.7355,3.7426,3.7691,3.7958",\ +"3.7839,3.7852,3.7912,3.7984,3.8249,3.8515"); + } + + rise_transition(SRAM_load_template) { + index_1("0.0008,0.0014,0.0051,0.0100,0.0339,0.0640"); + values ("0.0326,0.0341,0.0428,0.0518,0.0923,0.1492"); + } + fall_transition(SRAM_load_template) { + index_1("0.0008,0.0014,0.0051,0.0100,0.0339,0.0640"); + values ("0.0254,0.0265,0.0335,0.0402,0.0707,0.1039"); + } + } +} +cell_leakage_power : 99.0077; +} +} diff --git a/flow/platforms/ihp-sg13g2/lib/RM_IHPSG13_1P_512x32_c2_bm_bist_fast_1p32V_m55C.lib b/flow/platforms/ihp-sg13g2/lib/RM_IHPSG13_1P_512x32_c2_bm_bist_fast_1p32V_m55C.lib new file mode 100644 index 0000000000..bc51a983f1 --- /dev/null +++ b/flow/platforms/ihp-sg13g2/lib/RM_IHPSG13_1P_512x32_c2_bm_bist_fast_1p32V_m55C.lib @@ -0,0 +1,1519 @@ +/* ------------------------------------------------------*/ +/**/ +/* Copyright 2023 IHP PDK Authors*/ +/**/ +/* Licensed under the Apache License, Version 2.0 (the "License");*/ +/* you may not use this file except in compliance with the License.*/ +/* You may obtain a copy of the License at*/ +/* */ +/* https://www.apache.org/licenses/LICENSE-2.0*/ +/* */ +/* Unless required by applicable law or agreed to in writing, software*/ +/* distributed under the License is distributed on an "AS IS" BASIS,*/ +/* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.*/ +/* See the License for the specific language governing permissions and*/ +/* limitations under the License.*/ +/* */ +/* Generated on Wed Apr 2 16:02:43 2025 */ +/* */ +/* ------------------------------------------------------ */ +library(RM_IHPSG13_1P_512x32_c2_bm_bist_fast_1p32V_m55C) { + technology (cmos) ; + delay_model : table_lookup ; + define ("add_pg_pin_to_lib", "library", "boolean"); + add_pg_pin_to_lib : true; + voltage_map ( VDD, 1.32); + voltage_map ( VDDARRAY, 1.32); + voltage_map ( VSS, 0.000000 ); + + date : "Wed Apr 2 16:02:42 2025" ; + comment : "IHP Microelectronics GmbH, 2023" ; + revision : 1.0.0 ; + simulation : true ; + nom_process : 1 ; + nom_temperature : -55 ; + nom_voltage : 1.32 ; + + operating_conditions("fast_1p32V_m55C"){ + process : 1 ; + temperature : -55 ; + voltage : 1.32 ; + tree_type : "balanced_tree" ; + } + + default_operating_conditions : fast_1p32V_m55C ; + default_max_transition : 1.0 ; + default_fanout_load : 1.0 ; + default_inout_pin_cap : 0.0 ; + default_input_pin_cap : 0.0 ; + default_output_pin_cap : 0.0 ; + default_cell_leakage_power : 0.0 ; + default_leakage_power_density : 0.0 ; + + slew_lower_threshold_pct_rise : 30 ; + slew_upper_threshold_pct_rise : 70 ; + input_threshold_pct_fall : 50 ; + output_threshold_pct_fall : 50 ; + input_threshold_pct_rise : 50 ; + output_threshold_pct_rise : 50 ; + slew_lower_threshold_pct_fall : 30 ; + slew_upper_threshold_pct_fall : 70 ; + slew_derate_from_library : 0.5; + k_volt_cell_leakage_power : 0.0 ; + k_temp_cell_leakage_power : 0.0 ; + k_process_cell_leakage_power : 0.0 ; + k_volt_internal_power : 0.0 ; + k_temp_internal_power : 0.0 ; + k_process_internal_power : 0.0 ; + + capacitive_load_unit (1,pf) ; + voltage_unit : "1V" ; + current_unit : "1uA" ; + time_unit : "1ns" ; + leakage_power_unit : "1nW" ; + pulling_resistance_unit : "1kohm"; + /* + ------------------------------------------------------------------------------------------ + implicit units overview: + cell_area unit : "um" + internal_power unit : "1e-12 * J/toggle = 1 * uW/MHz" + (capacitive_load_unit * voltage_unit^2) per toggle event + ------------------------------------------------------------------------------------------ + */ + library_features(report_delay_calculation); + define_cell_area (pad_drivers,pad_driver_sites) ; + + lu_table_template(CLKTRAN_constraint_template) { + variable_1 : constrained_pin_transition; + index_1 ( "0.010, 0.050, 0.200, 0.400, 1.000" ); + } + lu_table_template(SRAM_load_template) { + variable_1 : total_output_net_capacitance; + index_1 ( "0.0008,0.0014,0.0051,0.0100,0.0339,0.0640" ); + } + lu_table_template(SIG2SRAM_constraint_template) { + variable_1 : related_pin_transition; + variable_2 : constrained_pin_transition; + index_1 ( "0.0040,0.0176,0.0344,0.0656,0.1120,0.2016,0.3800" ); + index_2 ( "0.0040,0.0176,0.0344,0.0656,0.1120,0.2016,0.3800" ); + } + + lu_table_template(SIG2SRAM_delay_template) { + variable_1 : input_net_transition; + variable_2 : total_output_net_capacitance; + index_1 ( "0.0040,0.0176,0.0344,0.0656,0.1120,0.2016,0.3800" ); + index_2 ( "0.0008,0.0014,0.0051,0.0100,0.0339,0.0640" ); + } + + type (D_31_0) { + base_type : array; + data_type : bit; + bit_width : 32; + bit_from : 31; + bit_to : 0; + downto : true; + } + + type (A_8_0) { + base_type : array; + data_type : bit; + bit_width : 9; + bit_from : 8; + bit_to : 0; + downto : true; + } + +cell(RM_IHPSG13_1P_512x32_c2_bm_bist) { +pg_pin (VDD) { + pg_type : primary_power; + voltage_name : VDD; +} +pg_pin (VDDARRAY) { + pg_type : primary_power; + voltage_name : VDDARRAY; +} +pg_pin (VSS) { + pg_type : primary_ground; + voltage_name : VSS; +} + +memory() { + type : ram; + address_width : 9; + word_width : 32; +} + +interface_timing : false; +bus_naming_style : "%s[%d]" ; +area : 79719.8976 ; + + pin(A_DLY) { + direction : input ; + capacitance : 0.00421562 ; + max_transition : "1" ; + related_power_pin : VDD; + related_ground_pin : VSS; + internal_power() { + rise_power("scalar") { + values (0); + } + fall_power("scalar") { + values (0); + } + } + } + +bus(A_ADDR) { + bus_type : A_8_0; + direction : input ; + capacitance : 0.00691085 ; + pin(A_ADDR[0]) { + capacitance : 0.00562034 ; + } + pin(A_ADDR[1]) { + capacitance : 0.00462655 ; + } + pin(A_ADDR[2]) { + capacitance : 0.00594295 ; + } + pin(A_ADDR[3]) { + capacitance : 0.00723434 ; + } + pin(A_ADDR[4]) { + capacitance : 0.00481603 ; + } + pin(A_ADDR[5]) { + capacitance : 0.00868123 ; + } + pin(A_ADDR[6]) { + capacitance : 0.010187 ; + } + pin(A_ADDR[7]) { + capacitance : 0.00734489 ; + } + max_transition : "0.38" ; + pin(A_ADDR[8:0]) { + related_power_pin : VDD; + related_ground_pin : VSS; + internal_power() { + when : "A_MEN"; + rise_power("scalar"){ + values (0.0115); + } + fall_power("scalar"){ + values (0.0021); + } + } + internal_power() { + when : "!A_MEN"; + rise_power("scalar"){ + values (0.0343); + } + fall_power("scalar"){ + values (0.0003); + } + } + } + timing() { + timing_type : setup_rising; + related_pin : "A_CLK"; + when : "((A_WEN | A_REN)& A_MEN)" + sdf_cond : "A_RW_ACCESS" + + rise_constraint("SIG2SRAM_constraint_template") { + index_1("0.0040,0.0176,0.0344,0.0656,0.1120,0.2016,0.3800"); + index_2("0.0040,0.0176,0.0344,0.0656,0.1120,0.2016,0.3800"); + values ("-0.2371,-0.2215,-0.2098,-0.1824,-0.1434,-0.0691,0.0676",\ +"-0.2449,-0.2332,-0.2176,-0.1902,-0.1551,-0.0770,0.0559",\ +"-0.2605,-0.2488,-0.2332,-0.2059,-0.1707,-0.0965,0.0441",\ +"-0.2879,-0.2723,-0.2605,-0.2332,-0.1941,-0.1199,0.0168",\ +"-0.3230,-0.3113,-0.2996,-0.2723,-0.2332,-0.1590,-0.0184",\ +"-0.4012,-0.3895,-0.3738,-0.3465,-0.3074,-0.2332,-0.0965",\ +"-0.5379,-0.5262,-0.5105,-0.4832,-0.4480,-0.3699,-0.2332"); + } + + fall_constraint("SIG2SRAM_constraint_template") { + index_1("0.0040,0.0176,0.0344,0.0656,0.1120,0.2016,0.3800"); + index_2("0.0040,0.0176,0.0344,0.0656,0.1120,0.2016,0.3800"); + values ("-0.1785,-0.1707,-0.1551,-0.1277,-0.0887,-0.0184,0.1145",\ +"-0.1902,-0.1785,-0.1629,-0.1355,-0.1004,-0.0262,0.1027",\ +"-0.2059,-0.1941,-0.1785,-0.1512,-0.1160,-0.0418,0.0871",\ +"-0.2293,-0.2176,-0.2059,-0.1785,-0.1434,-0.0691,0.0598",\ +"-0.2684,-0.2566,-0.2449,-0.2176,-0.1824,-0.1082,0.0207",\ +"-0.3465,-0.3348,-0.3191,-0.2918,-0.2566,-0.1824,-0.0535",\ +"-0.4832,-0.4715,-0.4559,-0.4324,-0.3934,-0.3191,-0.1902"); + } + } + + + timing() { + timing_type : hold_rising; + related_pin : "A_CLK"; + when : "((A_WEN | A_REN)& A_MEN)" + sdf_cond : "A_RW_ACCESS" + + rise_constraint("SIG2SRAM_constraint_template") { + index_1("0.0040,0.0176,0.0344,0.0656,0.1120,0.2016,0.3800"); + index_2("0.0040,0.0176,0.0344,0.0656,0.1120,0.2016,0.3800"); + values ("0.3410,0.3293,0.3137,0.2863,0.2473,0.1730,0.0324",\ +"0.3488,0.3371,0.3215,0.2941,0.2590,0.1809,0.0480",\ +"0.3684,0.3527,0.3371,0.3098,0.2746,0.1965,0.0598",\ +"0.3918,0.3762,0.3645,0.3371,0.2980,0.2238,0.0871",\ +"0.4309,0.4152,0.4035,0.3762,0.3371,0.2629,0.1223",\ +"0.5051,0.4934,0.4777,0.4504,0.4113,0.3371,0.1965",\ +"0.6418,0.6262,0.6145,0.5871,0.5520,0.4738,0.3332"); + } + + fall_constraint("SIG2SRAM_constraint_template") { + index_1("0.0040,0.0176,0.0344,0.0656,0.1120,0.2016,0.3800"); + index_2("0.0040,0.0176,0.0344,0.0656,0.1120,0.2016,0.3800"); + values ("0.2824,0.2707,0.2551,0.2277,0.1926,0.1184,-0.0105",\ +"0.2902,0.2785,0.2668,0.2395,0.2043,0.1301,0.0012",\ +"0.3059,0.2941,0.2824,0.2551,0.2199,0.1457,0.0168",\ +"0.3332,0.3215,0.3059,0.2785,0.2434,0.1691,0.0402",\ +"0.3723,0.3605,0.3449,0.3176,0.2824,0.2121,0.0793",\ +"0.4465,0.4348,0.4230,0.3918,0.3566,0.2824,0.1535",\ +"0.5832,0.5715,0.5598,0.5324,0.4934,0.4191,0.2902"); + } + } +} +pin(A_WEN) { + direction : input ; + capacitance : 0.00341384 ; + max_transition : "0.38" ; + related_power_pin : VDD; + related_ground_pin : VSS; + internal_power() { + when : "A_MEN"; + rise_power("scalar"){ + values (0.0083); + } + fall_power("scalar"){ + values (0.0107); + } + } + internal_power() { + when : "!A_MEN"; + rise_power("scalar"){ + values (0.0099); + } + fall_power("scalar"){ + values (0.0320); + } + } + timing() { + timing_type : setup_rising; + related_pin : "A_CLK"; + when : "A_MEN" + sdf_cond : "A_MEN" + + rise_constraint("SIG2SRAM_constraint_template") { + index_1("0.0040,0.0176,0.0344,0.0656,0.1120,0.2016,0.3800"); + index_2("0.0040,0.0176,0.0344,0.0656,0.1120,0.2016,0.3800"); + values ("0.1418,0.1496,0.1652,0.1887,0.2316,0.3059,0.4465",\ +"0.1301,0.1379,0.1535,0.1809,0.2199,0.2941,0.4348",\ +"0.1145,0.1262,0.1379,0.1652,0.2043,0.2785,0.4191",\ +"0.0871,0.0949,0.1105,0.1379,0.1770,0.2512,0.3879",\ +"0.0480,0.0598,0.0754,0.0988,0.1379,0.2082,0.3527",\ +"-0.0262,-0.0145,0.0012,0.0246,0.0676,0.1379,0.2785",\ +"-0.1668,-0.1551,-0.1395,-0.1121,-0.0730,0.0012,0.1418"); + } + + fall_constraint("SIG2SRAM_constraint_template") { + index_1("0.0040,0.0176,0.0344,0.0656,0.1120,0.2016,0.3800"); + index_2("0.0040,0.0176,0.0344,0.0656,0.1120,0.2016,0.3800"); + values ("0.2082,0.2160,0.2316,0.2590,0.2941,0.3684,0.5012",\ +"0.1926,0.2043,0.2199,0.2473,0.2824,0.3566,0.4895",\ +"0.1770,0.1887,0.2043,0.2316,0.2668,0.3410,0.4777",\ +"0.1535,0.1652,0.1770,0.2043,0.2395,0.3137,0.4504",\ +"0.1145,0.1262,0.1379,0.1652,0.2043,0.2746,0.4113",\ +"0.0402,0.0520,0.0676,0.0910,0.1262,0.2004,0.3332",\ +"-0.0965,-0.0848,-0.0730,-0.0457,-0.0066,0.0637,0.2004"); + } + } + + + timing() { + timing_type : hold_rising; + related_pin : "A_CLK"; + when : "A_MEN" + sdf_cond : "A_MEN" + + rise_constraint("SIG2SRAM_constraint_template") { + index_1("0.0040,0.0176,0.0344,0.0656,0.1120,0.2016,0.3800"); + index_2("0.0040,0.0176,0.0344,0.0656,0.1120,0.2016,0.3800"); + values ("0.1770,0.1652,0.1496,0.1223,0.0793,0.0090,-0.1316",\ +"0.1848,0.1730,0.1574,0.1301,0.0910,0.0168,-0.1199",\ +"0.2004,0.1887,0.1770,0.1496,0.1066,0.0363,-0.1043",\ +"0.2277,0.2160,0.2004,0.1730,0.1340,0.0598,-0.0809",\ +"0.2668,0.2551,0.2395,0.2121,0.1730,0.0988,-0.0418",\ +"0.3410,0.3293,0.3137,0.2863,0.2434,0.1730,0.0324",\ +"0.4816,0.4699,0.4543,0.4230,0.3801,0.3098,0.1730"); + } + + fall_constraint("SIG2SRAM_constraint_template") { + index_1("0.0040,0.0176,0.0344,0.0656,0.1120,0.2016,0.3800"); + index_2("0.0040,0.0176,0.0344,0.0656,0.1120,0.2016,0.3800"); + values ("0.1613,0.1496,0.1379,0.1066,0.0715,0.0012,-0.1355",\ +"0.1730,0.1613,0.1457,0.1184,0.0832,0.0129,-0.1238",\ +"0.1887,0.1770,0.1613,0.1340,0.0988,0.0246,-0.1121",\ +"0.2121,0.2043,0.1887,0.1613,0.1223,0.0520,-0.0848",\ +"0.2512,0.2434,0.2277,0.2004,0.1613,0.0910,-0.0457",\ +"0.3254,0.3176,0.3020,0.2746,0.2355,0.1652,0.0324",\ +"0.4660,0.4543,0.4387,0.4113,0.3723,0.3020,0.1691"); + } + } + } +pin(A_REN) { + direction : input ; + capacitance : 0.00390661 ; + max_transition : "0.38" ; + related_power_pin : VDD; + related_ground_pin : VSS; + internal_power() { + when : "A_MEN"; + rise_power("scalar"){ + values (0.0014); + } + fall_power("scalar"){ + values (0.0139); + } + } + internal_power() { + when : "!A_MEN"; + rise_power("scalar"){ + values (0.0211); + } + fall_power("scalar"){ + values (0.0216); + } + } + timing() { + timing_type : setup_rising; + related_pin : "A_CLK"; + when : "A_MEN" + sdf_cond : "A_MEN" + + rise_constraint("SIG2SRAM_constraint_template") { + index_1("0.0040,0.0176,0.0344,0.0656,0.1120,0.2016,0.3800"); + index_2("0.0040,0.0176,0.0344,0.0656,0.1120,0.2016,0.3800"); + values ("-0.0027,0.0090,0.0246,0.0520,0.0910,0.1613,0.3020",\ +"-0.0105,0.0012,0.0129,0.0363,0.0793,0.1535,0.2902",\ +"-0.0262,-0.0145,-0.0027,0.0246,0.0637,0.1379,0.2785",\ +"-0.0535,-0.0418,-0.0262,0.0012,0.0363,0.1105,0.2512",\ +"-0.0926,-0.0809,-0.0652,-0.0418,-0.0027,0.0715,0.2121",\ +"-0.1668,-0.1551,-0.1395,-0.1082,-0.0770,-0.0027,0.1379",\ +"-0.3035,-0.2918,-0.2762,-0.2488,-0.2137,-0.1434,-0.0027"); + } + + fall_constraint("SIG2SRAM_constraint_template") { + index_1("0.0040,0.0176,0.0344,0.0656,0.1120,0.2016,0.3800"); + index_2("0.0040,0.0176,0.0344,0.0656,0.1120,0.2016,0.3800"); + values ("0.0832,0.0949,0.1105,0.1379,0.1730,0.2473,0.3801",\ +"0.0754,0.0832,0.0988,0.1223,0.1613,0.2355,0.3684",\ +"0.0598,0.0676,0.0832,0.1066,0.1457,0.2121,0.3527",\ +"0.0324,0.0441,0.0598,0.0871,0.1223,0.1926,0.3293",\ +"-0.0066,0.0051,0.0168,0.0480,0.0832,0.1535,0.2902",\ +"-0.0809,-0.0691,-0.0574,-0.0301,0.0090,0.0832,0.2121",\ +"-0.2176,-0.2059,-0.1941,-0.1668,-0.1277,-0.0574,0.0793"); + } + } + + + timing() { + timing_type : hold_rising; + related_pin : "A_CLK"; + when : "A_MEN" + sdf_cond : "A_MEN" + + rise_constraint("SIG2SRAM_constraint_template") { + index_1("0.0040,0.0176,0.0344,0.0656,0.1120,0.2016,0.3800"); + index_2("0.0040,0.0176,0.0344,0.0656,0.1120,0.2016,0.3800"); + values ("0.1887,0.1770,0.1613,0.1340,0.0949,0.0207,-0.1160",\ +"0.1965,0.1848,0.1730,0.1457,0.1027,0.0324,-0.1082",\ +"0.2160,0.2004,0.1887,0.1613,0.1184,0.0480,-0.0926",\ +"0.2395,0.2277,0.2121,0.1848,0.1457,0.0715,-0.0652",\ +"0.2785,0.2668,0.2512,0.2238,0.1848,0.1105,-0.0262",\ +"0.3527,0.3410,0.3254,0.2980,0.2551,0.1848,0.0480",\ +"0.4934,0.4816,0.4660,0.4387,0.3957,0.3254,0.1887"); + } + + fall_constraint("SIG2SRAM_constraint_template") { + index_1("0.0040,0.0176,0.0344,0.0656,0.1120,0.2016,0.3800"); + index_2("0.0040,0.0176,0.0344,0.0656,0.1120,0.2016,0.3800"); + values ("0.1730,0.1613,0.1496,0.1184,0.0793,0.0129,-0.1238",\ +"0.1848,0.1730,0.1574,0.1301,0.0910,0.0207,-0.1121",\ +"0.2004,0.1887,0.1730,0.1457,0.1066,0.0363,-0.1004",\ +"0.2238,0.2121,0.2004,0.1691,0.1340,0.0598,-0.0730",\ +"0.2629,0.2512,0.2395,0.2121,0.1691,0.0988,-0.0340",\ +"0.3371,0.3254,0.3137,0.2863,0.2434,0.1730,0.0402",\ +"0.4777,0.4660,0.4504,0.4230,0.3840,0.3137,0.1809"); + } + } + } +pin(A_MEN) { + direction : input ; + capacitance : 0.00326046 ; + max_transition : "0.38" ; + related_power_pin : VDD; + related_ground_pin : VSS; + internal_power() { + rise_power("scalar"){ + values (0.3360); + } + fall_power("scalar"){ + values (0.0108); + } + } + timing() { + timing_type : setup_rising; + related_pin : "A_CLK"; + + rise_constraint("SIG2SRAM_constraint_template") { + index_1("0.0040,0.0176,0.0344,0.0656,0.1120,0.2016,0.3800"); + index_2("0.0040,0.0176,0.0344,0.0656,0.1120,0.2016,0.3800"); + values ("0.1418,0.1496,0.1652,0.1926,0.2316,0.3059,0.4465",\ +"0.1301,0.1379,0.1535,0.1809,0.2199,0.2941,0.4348",\ +"0.1145,0.1262,0.1418,0.1652,0.2043,0.2785,0.4191",\ +"0.0871,0.0949,0.1105,0.1379,0.1770,0.2512,0.3879",\ +"0.0480,0.0598,0.0754,0.0988,0.1379,0.2082,0.3488",\ +"-0.0262,-0.0145,0.0012,0.0285,0.0676,0.1379,0.2785",\ +"-0.1668,-0.1551,-0.1395,-0.1121,-0.0730,0.0012,0.1379"); + } + + fall_constraint("SIG2SRAM_constraint_template") { + index_1("0.0040,0.0176,0.0344,0.0656,0.1120,0.2016,0.3800"); + index_2("0.0040,0.0176,0.0344,0.0656,0.1120,0.2016,0.3800"); + values ("0.2082,0.2199,0.2316,0.2590,0.2980,0.3723,0.5051",\ +"0.1965,0.2082,0.2199,0.2473,0.2863,0.3605,0.4934",\ +"0.1809,0.1926,0.2043,0.2316,0.2707,0.3449,0.4777",\ +"0.1574,0.1691,0.1809,0.2082,0.2434,0.3176,0.4543",\ +"0.1145,0.1262,0.1418,0.1691,0.2043,0.2785,0.4113",\ +"0.0441,0.0559,0.0676,0.0949,0.1301,0.2004,0.3332",\ +"-0.0965,-0.0848,-0.0691,-0.0418,-0.0066,0.0676,0.2004"); + } + } + + + timing() { + timing_type : hold_rising; + related_pin : "A_CLK"; + + rise_constraint("SIG2SRAM_constraint_template") { + index_1("0.0040,0.0176,0.0344,0.0656,0.1120,0.2016,0.3800"); + index_2("0.0040,0.0176,0.0344,0.0656,0.1120,0.2016,0.3800"); + values ("0.1770,0.1652,0.1535,0.1262,0.0832,0.0129,-0.1277",\ +"0.1887,0.1770,0.1613,0.1340,0.0949,0.0207,-0.1199",\ +"0.2043,0.1926,0.1770,0.1496,0.1105,0.0363,-0.1043",\ +"0.2277,0.2160,0.2043,0.1770,0.1379,0.0598,-0.0770",\ +"0.2668,0.2551,0.2434,0.2160,0.1730,0.0988,-0.0379",\ +"0.3449,0.3332,0.3176,0.2902,0.2473,0.1730,0.0363",\ +"0.4816,0.4699,0.4543,0.4270,0.3840,0.3098,0.1770"); + } + + fall_constraint("SIG2SRAM_constraint_template") { + index_1("0.0040,0.0176,0.0344,0.0656,0.1120,0.2016,0.3800"); + index_2("0.0040,0.0176,0.0344,0.0656,0.1120,0.2016,0.3800"); + values ("0.1613,0.1496,0.1379,0.1105,0.0715,0.0012,-0.1355",\ +"0.1730,0.1613,0.1496,0.1184,0.0832,0.0129,-0.1238",\ +"0.1887,0.1770,0.1652,0.1340,0.0988,0.0285,-0.1121",\ +"0.2121,0.2043,0.1887,0.1613,0.1223,0.0520,-0.0848",\ +"0.2551,0.2434,0.2277,0.2004,0.1613,0.0910,-0.0418",\ +"0.3293,0.3176,0.3020,0.2746,0.2395,0.1652,0.0324",\ +"0.4660,0.4543,0.4426,0.4113,0.3762,0.3020,0.1691"); + } + } + } +bus(A_BM) { + bus_type : D_31_0; + direction : input ; + capacitance : 0.00310985 ; + max_transition : "0.38" ; + pin(A_BM[31:0]) { + related_power_pin : VDD; + related_ground_pin : VSS; + internal_power() { + when : "A_MEN"; + rise_power("scalar"){ + values (0.1471); + } + fall_power("scalar"){ + values (0.1374); + } + } + internal_power() { + when : "!A_MEN"; + rise_power("scalar"){ + values (0.1745); + } + fall_power("scalar"){ + values (0.1522); + } + } + } + timing() { + timing_type : setup_rising; + related_pin : "A_CLK"; + when : "(A_WEN & A_MEN)" + sdf_cond : "A_RW_ACCESS" + + rise_constraint("SIG2SRAM_constraint_template") { + index_1("0.0040,0.0176,0.0344,0.0656,0.1120,0.2016,0.3800"); + index_2("0.0040,0.0176,0.0344,0.0656,0.1120,0.2016,0.3800"); + values ("-0.2520,-0.2412,-0.2256,-0.1993,-0.1592,-0.0889,0.0459",\ +"-0.2559,-0.2451,-0.2295,-0.2031,-0.1631,-0.0928,0.0420",\ +"-0.2597,-0.2489,-0.2333,-0.2069,-0.1669,-0.0966,0.0382",\ +"-0.2629,-0.2522,-0.2366,-0.2102,-0.1701,-0.0998,0.0349",\ +"-0.2754,-0.2646,-0.2490,-0.2226,-0.1826,-0.1123,0.0225",\ +"-0.2930,-0.2822,-0.2666,-0.2402,-0.2002,-0.1299,0.0049",\ +"-0.3205,-0.3097,-0.2941,-0.2677,-0.2277,-0.1574,-0.0226"); + } + + fall_constraint("SIG2SRAM_constraint_template") { + index_1("0.0040,0.0176,0.0344,0.0656,0.1120,0.2016,0.3800"); + index_2("0.0040,0.0176,0.0344,0.0656,0.1120,0.2016,0.3800"); + values ("-0.2295,-0.2188,-0.2051,-0.1778,-0.1407,-0.0684,0.0615",\ +"-0.2334,-0.2227,-0.2090,-0.1817,-0.1445,-0.0723,0.0576",\ +"-0.2372,-0.2265,-0.2128,-0.1855,-0.1483,-0.0761,0.0538",\ +"-0.2405,-0.2297,-0.2160,-0.1887,-0.1516,-0.0793,0.0506",\ +"-0.2529,-0.2422,-0.2285,-0.2011,-0.1640,-0.0918,0.0381",\ +"-0.2705,-0.2598,-0.2461,-0.2188,-0.1816,-0.1094,0.0205",\ +"-0.2980,-0.2873,-0.2736,-0.2463,-0.2092,-0.1369,-0.0070"); + } + } + + + timing() { + timing_type : hold_rising; + related_pin : "A_CLK"; + when : "(A_WEN & A_MEN)" + sdf_cond : "A_RW_ACCESS" + + rise_constraint("SIG2SRAM_constraint_template") { + index_1("0.0040,0.0176,0.0344,0.0656,0.1120,0.2016,0.3800"); + index_2("0.0040,0.0176,0.0344,0.0656,0.1120,0.2016,0.3800"); + values ("0.3581,0.3463,0.3317,0.3053,0.2653,0.1940,0.0573",\ +"0.3619,0.3502,0.3356,0.3092,0.2692,0.1979,0.0612",\ +"0.3657,0.3540,0.3394,0.3130,0.2730,0.2017,0.0650",\ +"0.3690,0.3573,0.3426,0.3163,0.2762,0.2049,0.0682",\ +"0.3814,0.3697,0.3551,0.3287,0.2887,0.2174,0.0807",\ +"0.3990,0.3873,0.3727,0.3463,0.3063,0.2350,0.0983",\ +"0.4266,0.4148,0.4002,0.3738,0.3338,0.2625,0.1258"); + } + + fall_constraint("SIG2SRAM_constraint_template") { + index_1("0.0040,0.0176,0.0344,0.0656,0.1120,0.2016,0.3800"); + index_2("0.0040,0.0176,0.0344,0.0656,0.1120,0.2016,0.3800"); + values ("0.3297,0.3200,0.3053,0.2790,0.2418,0.1686,0.0407",\ +"0.3336,0.3239,0.3092,0.2828,0.2457,0.1725,0.0446",\ +"0.3374,0.3276,0.3130,0.2866,0.2495,0.1763,0.0484",\ +"0.3407,0.3309,0.3163,0.2899,0.2528,0.1795,0.0516",\ +"0.3531,0.3433,0.3287,0.3023,0.2652,0.1920,0.0641",\ +"0.3707,0.3610,0.3463,0.3199,0.2828,0.2096,0.0817",\ +"0.3982,0.3885,0.3738,0.3474,0.3103,0.2371,0.1092"); + } + } +} + pin(A_CLK) { + direction : input; + capacitance : 0.00389386; + max_transition : "0.38"; + clock : "true" ; + pin_func_type : active_rising ; + + timing () { + timing_type : "min_pulse_width"; + related_pin : "A_CLK"; + rise_constraint("CLKTRAN_constraint_template") { + index_1("0.004,0.38"); + values("0.12,0.12"); + } + } + + related_power_pin : VDD; + related_ground_pin : VSS; + + internal_power() { + when : "!A_MEN & !A_WEN & !A_REN"; + rise_power("scalar"){ + values (0); + } + fall_power("scalar"){ + values (0); + } + } + internal_power() { + when : "!A_MEN & A_WEN & !A_REN"; + rise_power("scalar"){ + values (0.6735); + } + fall_power("scalar"){ + values (0); + } + } + internal_power() { + when : "A_MEN & A_WEN & !A_REN"; + rise_power("scalar"){ + values (54.8620); + } + fall_power("scalar"){ + values (0); + } + } + internal_power() { + when : "A_MEN & A_WEN & A_REN"; + rise_power("scalar"){ + values (56.6091); + } + fall_power("scalar"){ + values (0); + } + } + internal_power() { + when : "A_MEN & !A_WEN & A_REN"; + rise_power("scalar"){ + values (45.3648); + } + fall_power("scalar"){ + values (0); + } + } + internal_power() { + when : "!A_MEN & !A_WEN & A_REN"; + rise_power("scalar"){ + values (0.4386); + } + fall_power("scalar"){ + values (0); + } + } + internal_power() { + when : "!A_MEN & A_WEN & A_REN"; + rise_power("scalar"){ + values (1.6639); + } + fall_power("scalar"){ + values (0); + } + } + internal_power() { + when : "A_MEN & !A_WEN & !A_REN"; + rise_power("scalar"){ + values (0); + } + fall_power("scalar"){ + values (0); + } + } + } + bus(A_DIN) { + bus_type : D_31_0; + direction : input ; + capacitance : 0.00387207 ; + memory_write() { + address : A_ADDR ; + clocked_on : A_CLK; + } + + max_transition : "0.38" ; + pin(A_DIN[31:0]) { + related_power_pin : VDD; + related_ground_pin : VSS; + internal_power() { + when : "A_MEN"; + rise_power("scalar"){ + values (0.1471); + } + fall_power("scalar"){ + values (0.1374); + } + } + internal_power() { + when : "!A_MEN"; + rise_power("scalar"){ + values (0.1745); + } + fall_power("scalar"){ + values (0.1522); + } + } + } + timing() { + timing_type : setup_rising; + related_pin : "A_CLK"; + when : "(A_WEN & A_MEN)"; + sdf_cond : "A_W_ACCESS"; + + rise_constraint("SIG2SRAM_constraint_template") { + index_1("0.0040,0.0176,0.0344,0.0656,0.1120,0.2016,0.3800"); + index_2("0.0040,0.0176,0.0344,0.0656,0.1120,0.2016,0.3800"); + values ("-0.2520,-0.2412,-0.2256,-0.1993,-0.1592,-0.0889,0.0459",\ +"-0.2559,-0.2451,-0.2295,-0.2031,-0.1631,-0.0928,0.0420",\ +"-0.2597,-0.2489,-0.2333,-0.2069,-0.1669,-0.0966,0.0382",\ +"-0.2629,-0.2522,-0.2366,-0.2102,-0.1701,-0.0998,0.0349",\ +"-0.2754,-0.2646,-0.2490,-0.2226,-0.1826,-0.1123,0.0225",\ +"-0.2930,-0.2822,-0.2666,-0.2402,-0.2002,-0.1299,0.0049",\ +"-0.3205,-0.3097,-0.2941,-0.2677,-0.2277,-0.1574,-0.0226"); + } + + fall_constraint("SIG2SRAM_constraint_template") { + index_1("0.0040,0.0176,0.0344,0.0656,0.1120,0.2016,0.3800"); + index_2("0.0040,0.0176,0.0344,0.0656,0.1120,0.2016,0.3800"); + values ("-0.2295,-0.2188,-0.2051,-0.1778,-0.1407,-0.0684,0.0615",\ +"-0.2334,-0.2227,-0.2090,-0.1817,-0.1445,-0.0723,0.0576",\ +"-0.2372,-0.2265,-0.2128,-0.1855,-0.1483,-0.0761,0.0538",\ +"-0.2405,-0.2297,-0.2160,-0.1887,-0.1516,-0.0793,0.0506",\ +"-0.2529,-0.2422,-0.2285,-0.2011,-0.1640,-0.0918,0.0381",\ +"-0.2705,-0.2598,-0.2461,-0.2188,-0.1816,-0.1094,0.0205",\ +"-0.2980,-0.2873,-0.2736,-0.2463,-0.2092,-0.1369,-0.0070"); + } + } + + timing() { + timing_type : hold_rising; + related_pin : "A_CLK"; + when : "(A_WEN & A_MEN)"; + sdf_cond : "A_W_ACCESS"; + + rise_constraint("SIG2SRAM_constraint_template") { + index_1("0.0040,0.0176,0.0344,0.0656,0.1120,0.2016,0.3800"); + index_2("0.0040,0.0176,0.0344,0.0656,0.1120,0.2016,0.3800"); + values ("0.3581,0.3463,0.3317,0.3053,0.2653,0.1940,0.0573",\ +"0.3619,0.3502,0.3356,0.3092,0.2692,0.1979,0.0612",\ +"0.3657,0.3540,0.3394,0.3130,0.2730,0.2017,0.0650",\ +"0.3690,0.3573,0.3426,0.3163,0.2762,0.2049,0.0682",\ +"0.3814,0.3697,0.3551,0.3287,0.2887,0.2174,0.0807",\ +"0.3990,0.3873,0.3727,0.3463,0.3063,0.2350,0.0983",\ +"0.4266,0.4148,0.4002,0.3738,0.3338,0.2625,0.1258"); + } + + fall_constraint("SIG2SRAM_constraint_template") { + index_1("0.0040,0.0176,0.0344,0.0656,0.1120,0.2016,0.3800"); + index_2("0.0040,0.0176,0.0344,0.0656,0.1120,0.2016,0.3800"); + values ("0.3297,0.3200,0.3053,0.2790,0.2418,0.1686,0.0407",\ +"0.3336,0.3239,0.3092,0.2828,0.2457,0.1725,0.0446",\ +"0.3374,0.3276,0.3130,0.2866,0.2495,0.1763,0.0484",\ +"0.3407,0.3309,0.3163,0.2899,0.2528,0.1795,0.0516",\ +"0.3531,0.3433,0.3287,0.3023,0.2652,0.1920,0.0641",\ +"0.3707,0.3610,0.3463,0.3199,0.2828,0.2096,0.0817",\ +"0.3982,0.3885,0.3738,0.3474,0.3103,0.2371,0.1092"); + } + } + } + + pin(A_BIST_EN) { + direction : input ; + capacitance : 0.00421562 ; + max_transition : "1" ; + related_power_pin : VDD; + related_ground_pin : VSS; + internal_power() { + rise_power("scalar") { + values (0); + } + fall_power("scalar") { + values (0); + } + } + } + +bus(A_BIST_ADDR) { + bus_type : A_8_0; + direction : input ; + capacitance : 0.00691085 ; + pin(A_BIST_ADDR[0]) { + capacitance : 0.00562034 ; + } + pin(A_BIST_ADDR[1]) { + capacitance : 0.00462655 ; + } + pin(A_BIST_ADDR[2]) { + capacitance : 0.00594295 ; + } + pin(A_BIST_ADDR[3]) { + capacitance : 0.00723434 ; + } + pin(A_BIST_ADDR[4]) { + capacitance : 0.00481603 ; + } + pin(A_BIST_ADDR[5]) { + capacitance : 0.00868123 ; + } + pin(A_BIST_ADDR[6]) { + capacitance : 0.010187 ; + } + pin(A_BIST_ADDR[7]) { + capacitance : 0.00734489 ; + } + max_transition : "0.38" ; + pin(A_BIST_ADDR[8:0]) { + related_power_pin : VDD; + related_ground_pin : VSS; + internal_power() { + when : "A_BIST_MEN"; + rise_power("scalar"){ + values (0.0115); + } + fall_power("scalar"){ + values (0.0021); + } + } + internal_power() { + when : "!A_BIST_MEN"; + rise_power("scalar"){ + values (0.0343); + } + fall_power("scalar"){ + values (0.0003); + } + } + } + timing() { + timing_type : setup_rising; + related_pin : "A_BIST_CLK"; + when : "((A_BIST_WEN | A_BIST_REN)& A_BIST_MEN)" + sdf_cond : "A_BIST_RW_ACCESS" + + rise_constraint("SIG2SRAM_constraint_template") { + index_1("0.0040,0.0176,0.0344,0.0656,0.1120,0.2016,0.3800"); + index_2("0.0040,0.0176,0.0344,0.0656,0.1120,0.2016,0.3800"); + values ("-0.2371,-0.2215,-0.2098,-0.1824,-0.1434,-0.0691,0.0676",\ +"-0.2449,-0.2332,-0.2176,-0.1902,-0.1551,-0.0770,0.0559",\ +"-0.2605,-0.2488,-0.2332,-0.2059,-0.1707,-0.0965,0.0441",\ +"-0.2879,-0.2723,-0.2605,-0.2332,-0.1941,-0.1199,0.0168",\ +"-0.3230,-0.3113,-0.2996,-0.2723,-0.2332,-0.1590,-0.0184",\ +"-0.4012,-0.3895,-0.3738,-0.3465,-0.3074,-0.2332,-0.0965",\ +"-0.5379,-0.5262,-0.5105,-0.4832,-0.4480,-0.3699,-0.2332"); + } + + fall_constraint("SIG2SRAM_constraint_template") { + index_1("0.0040,0.0176,0.0344,0.0656,0.1120,0.2016,0.3800"); + index_2("0.0040,0.0176,0.0344,0.0656,0.1120,0.2016,0.3800"); + values ("-0.1785,-0.1707,-0.1551,-0.1277,-0.0887,-0.0184,0.1145",\ +"-0.1902,-0.1785,-0.1629,-0.1355,-0.1004,-0.0262,0.1027",\ +"-0.2059,-0.1941,-0.1785,-0.1512,-0.1160,-0.0418,0.0871",\ +"-0.2293,-0.2176,-0.2059,-0.1785,-0.1434,-0.0691,0.0598",\ +"-0.2684,-0.2566,-0.2449,-0.2176,-0.1824,-0.1082,0.0207",\ +"-0.3465,-0.3348,-0.3191,-0.2918,-0.2566,-0.1824,-0.0535",\ +"-0.4832,-0.4715,-0.4559,-0.4324,-0.3934,-0.3191,-0.1902"); + } + } + + + timing() { + timing_type : hold_rising; + related_pin : "A_BIST_CLK"; + when : "((A_BIST_WEN | A_BIST_REN)& A_BIST_MEN)" + sdf_cond : "A_BIST_RW_ACCESS" + + rise_constraint("SIG2SRAM_constraint_template") { + index_1("0.0040,0.0176,0.0344,0.0656,0.1120,0.2016,0.3800"); + index_2("0.0040,0.0176,0.0344,0.0656,0.1120,0.2016,0.3800"); + values ("0.3410,0.3293,0.3137,0.2863,0.2473,0.1730,0.0324",\ +"0.3488,0.3371,0.3215,0.2941,0.2590,0.1809,0.0480",\ +"0.3684,0.3527,0.3371,0.3098,0.2746,0.1965,0.0598",\ +"0.3918,0.3762,0.3645,0.3371,0.2980,0.2238,0.0871",\ +"0.4309,0.4152,0.4035,0.3762,0.3371,0.2629,0.1223",\ +"0.5051,0.4934,0.4777,0.4504,0.4113,0.3371,0.1965",\ +"0.6418,0.6262,0.6145,0.5871,0.5520,0.4738,0.3332"); + } + + fall_constraint("SIG2SRAM_constraint_template") { + index_1("0.0040,0.0176,0.0344,0.0656,0.1120,0.2016,0.3800"); + index_2("0.0040,0.0176,0.0344,0.0656,0.1120,0.2016,0.3800"); + values ("0.2824,0.2707,0.2551,0.2277,0.1926,0.1184,-0.0105",\ +"0.2902,0.2785,0.2668,0.2395,0.2043,0.1301,0.0012",\ +"0.3059,0.2941,0.2824,0.2551,0.2199,0.1457,0.0168",\ +"0.3332,0.3215,0.3059,0.2785,0.2434,0.1691,0.0402",\ +"0.3723,0.3605,0.3449,0.3176,0.2824,0.2121,0.0793",\ +"0.4465,0.4348,0.4230,0.3918,0.3566,0.2824,0.1535",\ +"0.5832,0.5715,0.5598,0.5324,0.4934,0.4191,0.2902"); + } + } +} +pin(A_BIST_WEN) { + direction : input ; + capacitance : 0.00341384 ; + max_transition : "0.38" ; + related_power_pin : VDD; + related_ground_pin : VSS; + internal_power() { + when : "A_BIST_MEN"; + rise_power("scalar"){ + values (0.0083); + } + fall_power("scalar"){ + values (0.0107); + } + } + internal_power() { + when : "!A_BIST_MEN"; + rise_power("scalar"){ + values (0.0099); + } + fall_power("scalar"){ + values (0.0320); + } + } + timing() { + timing_type : setup_rising; + related_pin : "A_BIST_CLK"; + when : "A_BIST_MEN" + sdf_cond : "A_BIST_MEN" + + rise_constraint("SIG2SRAM_constraint_template") { + index_1("0.0040,0.0176,0.0344,0.0656,0.1120,0.2016,0.3800"); + index_2("0.0040,0.0176,0.0344,0.0656,0.1120,0.2016,0.3800"); + values ("0.1418,0.1496,0.1652,0.1887,0.2316,0.3059,0.4465",\ +"0.1301,0.1379,0.1535,0.1809,0.2199,0.2941,0.4348",\ +"0.1145,0.1262,0.1379,0.1652,0.2043,0.2785,0.4191",\ +"0.0871,0.0949,0.1105,0.1379,0.1770,0.2512,0.3879",\ +"0.0480,0.0598,0.0754,0.0988,0.1379,0.2082,0.3527",\ +"-0.0262,-0.0145,0.0012,0.0246,0.0676,0.1379,0.2785",\ +"-0.1668,-0.1551,-0.1395,-0.1121,-0.0730,0.0012,0.1418"); + } + + fall_constraint("SIG2SRAM_constraint_template") { + index_1("0.0040,0.0176,0.0344,0.0656,0.1120,0.2016,0.3800"); + index_2("0.0040,0.0176,0.0344,0.0656,0.1120,0.2016,0.3800"); + values ("0.2082,0.2160,0.2316,0.2590,0.2941,0.3684,0.5012",\ +"0.1926,0.2043,0.2199,0.2473,0.2824,0.3566,0.4895",\ +"0.1770,0.1887,0.2043,0.2316,0.2668,0.3410,0.4777",\ +"0.1535,0.1652,0.1770,0.2043,0.2395,0.3137,0.4504",\ +"0.1145,0.1262,0.1379,0.1652,0.2043,0.2746,0.4113",\ +"0.0402,0.0520,0.0676,0.0910,0.1262,0.2004,0.3332",\ +"-0.0965,-0.0848,-0.0730,-0.0457,-0.0066,0.0637,0.2004"); + } + } + + + timing() { + timing_type : hold_rising; + related_pin : "A_BIST_CLK"; + when : "A_BIST_MEN" + sdf_cond : "A_BIST_MEN" + + rise_constraint("SIG2SRAM_constraint_template") { + index_1("0.0040,0.0176,0.0344,0.0656,0.1120,0.2016,0.3800"); + index_2("0.0040,0.0176,0.0344,0.0656,0.1120,0.2016,0.3800"); + values ("0.1770,0.1652,0.1496,0.1223,0.0793,0.0090,-0.1316",\ +"0.1848,0.1730,0.1574,0.1301,0.0910,0.0168,-0.1199",\ +"0.2004,0.1887,0.1770,0.1496,0.1066,0.0363,-0.1043",\ +"0.2277,0.2160,0.2004,0.1730,0.1340,0.0598,-0.0809",\ +"0.2668,0.2551,0.2395,0.2121,0.1730,0.0988,-0.0418",\ +"0.3410,0.3293,0.3137,0.2863,0.2434,0.1730,0.0324",\ +"0.4816,0.4699,0.4543,0.4230,0.3801,0.3098,0.1730"); + } + + fall_constraint("SIG2SRAM_constraint_template") { + index_1("0.0040,0.0176,0.0344,0.0656,0.1120,0.2016,0.3800"); + index_2("0.0040,0.0176,0.0344,0.0656,0.1120,0.2016,0.3800"); + values ("0.1613,0.1496,0.1379,0.1066,0.0715,0.0012,-0.1355",\ +"0.1730,0.1613,0.1457,0.1184,0.0832,0.0129,-0.1238",\ +"0.1887,0.1770,0.1613,0.1340,0.0988,0.0246,-0.1121",\ +"0.2121,0.2043,0.1887,0.1613,0.1223,0.0520,-0.0848",\ +"0.2512,0.2434,0.2277,0.2004,0.1613,0.0910,-0.0457",\ +"0.3254,0.3176,0.3020,0.2746,0.2355,0.1652,0.0324",\ +"0.4660,0.4543,0.4387,0.4113,0.3723,0.3020,0.1691"); + } + } + } +pin(A_BIST_REN) { + direction : input ; + capacitance : 0.00390661 ; + max_transition : "0.38" ; + related_power_pin : VDD; + related_ground_pin : VSS; + internal_power() { + when : "A_BIST_MEN"; + rise_power("scalar"){ + values (0.0014); + } + fall_power("scalar"){ + values (0.0139); + } + } + internal_power() { + when : "!A_BIST_MEN"; + rise_power("scalar"){ + values (0.0211); + } + fall_power("scalar"){ + values (0.0216); + } + } + timing() { + timing_type : setup_rising; + related_pin : "A_BIST_CLK"; + when : "A_BIST_MEN" + sdf_cond : "A_BIST_MEN" + + rise_constraint("SIG2SRAM_constraint_template") { + index_1("0.0040,0.0176,0.0344,0.0656,0.1120,0.2016,0.3800"); + index_2("0.0040,0.0176,0.0344,0.0656,0.1120,0.2016,0.3800"); + values ("-0.0027,0.0090,0.0246,0.0520,0.0910,0.1613,0.3020",\ +"-0.0105,0.0012,0.0129,0.0363,0.0793,0.1535,0.2902",\ +"-0.0262,-0.0145,-0.0027,0.0246,0.0637,0.1379,0.2785",\ +"-0.0535,-0.0418,-0.0262,0.0012,0.0363,0.1105,0.2512",\ +"-0.0926,-0.0809,-0.0652,-0.0418,-0.0027,0.0715,0.2121",\ +"-0.1668,-0.1551,-0.1395,-0.1082,-0.0770,-0.0027,0.1379",\ +"-0.3035,-0.2918,-0.2762,-0.2488,-0.2137,-0.1434,-0.0027"); + } + + fall_constraint("SIG2SRAM_constraint_template") { + index_1("0.0040,0.0176,0.0344,0.0656,0.1120,0.2016,0.3800"); + index_2("0.0040,0.0176,0.0344,0.0656,0.1120,0.2016,0.3800"); + values ("0.0832,0.0949,0.1105,0.1379,0.1730,0.2473,0.3801",\ +"0.0754,0.0832,0.0988,0.1223,0.1613,0.2355,0.3684",\ +"0.0598,0.0676,0.0832,0.1066,0.1457,0.2121,0.3527",\ +"0.0324,0.0441,0.0598,0.0871,0.1223,0.1926,0.3293",\ +"-0.0066,0.0051,0.0168,0.0480,0.0832,0.1535,0.2902",\ +"-0.0809,-0.0691,-0.0574,-0.0301,0.0090,0.0832,0.2121",\ +"-0.2176,-0.2059,-0.1941,-0.1668,-0.1277,-0.0574,0.0793"); + } + } + + + timing() { + timing_type : hold_rising; + related_pin : "A_BIST_CLK"; + when : "A_BIST_MEN" + sdf_cond : "A_BIST_MEN" + + rise_constraint("SIG2SRAM_constraint_template") { + index_1("0.0040,0.0176,0.0344,0.0656,0.1120,0.2016,0.3800"); + index_2("0.0040,0.0176,0.0344,0.0656,0.1120,0.2016,0.3800"); + values ("0.1887,0.1770,0.1613,0.1340,0.0949,0.0207,-0.1160",\ +"0.1965,0.1848,0.1730,0.1457,0.1027,0.0324,-0.1082",\ +"0.2160,0.2004,0.1887,0.1613,0.1184,0.0480,-0.0926",\ +"0.2395,0.2277,0.2121,0.1848,0.1457,0.0715,-0.0652",\ +"0.2785,0.2668,0.2512,0.2238,0.1848,0.1105,-0.0262",\ +"0.3527,0.3410,0.3254,0.2980,0.2551,0.1848,0.0480",\ +"0.4934,0.4816,0.4660,0.4387,0.3957,0.3254,0.1887"); + } + + fall_constraint("SIG2SRAM_constraint_template") { + index_1("0.0040,0.0176,0.0344,0.0656,0.1120,0.2016,0.3800"); + index_2("0.0040,0.0176,0.0344,0.0656,0.1120,0.2016,0.3800"); + values ("0.1730,0.1613,0.1496,0.1184,0.0793,0.0129,-0.1238",\ +"0.1848,0.1730,0.1574,0.1301,0.0910,0.0207,-0.1121",\ +"0.2004,0.1887,0.1730,0.1457,0.1066,0.0363,-0.1004",\ +"0.2238,0.2121,0.2004,0.1691,0.1340,0.0598,-0.0730",\ +"0.2629,0.2512,0.2395,0.2121,0.1691,0.0988,-0.0340",\ +"0.3371,0.3254,0.3137,0.2863,0.2434,0.1730,0.0402",\ +"0.4777,0.4660,0.4504,0.4230,0.3840,0.3137,0.1809"); + } + } + } +pin(A_BIST_MEN) { + direction : input ; + capacitance : 0.00326046 ; + max_transition : "0.38" ; + related_power_pin : VDD; + related_ground_pin : VSS; + internal_power() { + rise_power("scalar"){ + values (0.3360); + } + fall_power("scalar"){ + values (0.0108); + } + } + timing() { + timing_type : setup_rising; + related_pin : "A_BIST_CLK"; + + rise_constraint("SIG2SRAM_constraint_template") { + index_1("0.0040,0.0176,0.0344,0.0656,0.1120,0.2016,0.3800"); + index_2("0.0040,0.0176,0.0344,0.0656,0.1120,0.2016,0.3800"); + values ("0.1418,0.1496,0.1652,0.1926,0.2316,0.3059,0.4465",\ +"0.1301,0.1379,0.1535,0.1809,0.2199,0.2941,0.4348",\ +"0.1145,0.1262,0.1418,0.1652,0.2043,0.2785,0.4191",\ +"0.0871,0.0949,0.1105,0.1379,0.1770,0.2512,0.3879",\ +"0.0480,0.0598,0.0754,0.0988,0.1379,0.2082,0.3488",\ +"-0.0262,-0.0145,0.0012,0.0285,0.0676,0.1379,0.2785",\ +"-0.1668,-0.1551,-0.1395,-0.1121,-0.0730,0.0012,0.1379"); + } + + fall_constraint("SIG2SRAM_constraint_template") { + index_1("0.0040,0.0176,0.0344,0.0656,0.1120,0.2016,0.3800"); + index_2("0.0040,0.0176,0.0344,0.0656,0.1120,0.2016,0.3800"); + values ("0.2082,0.2199,0.2316,0.2590,0.2980,0.3723,0.5051",\ +"0.1965,0.2082,0.2199,0.2473,0.2863,0.3605,0.4934",\ +"0.1809,0.1926,0.2043,0.2316,0.2707,0.3449,0.4777",\ +"0.1574,0.1691,0.1809,0.2082,0.2434,0.3176,0.4543",\ +"0.1145,0.1262,0.1418,0.1691,0.2043,0.2785,0.4113",\ +"0.0441,0.0559,0.0676,0.0949,0.1301,0.2004,0.3332",\ +"-0.0965,-0.0848,-0.0691,-0.0418,-0.0066,0.0676,0.2004"); + } + } + + + timing() { + timing_type : hold_rising; + related_pin : "A_BIST_CLK"; + + rise_constraint("SIG2SRAM_constraint_template") { + index_1("0.0040,0.0176,0.0344,0.0656,0.1120,0.2016,0.3800"); + index_2("0.0040,0.0176,0.0344,0.0656,0.1120,0.2016,0.3800"); + values ("0.1770,0.1652,0.1535,0.1262,0.0832,0.0129,-0.1277",\ +"0.1887,0.1770,0.1613,0.1340,0.0949,0.0207,-0.1199",\ +"0.2043,0.1926,0.1770,0.1496,0.1105,0.0363,-0.1043",\ +"0.2277,0.2160,0.2043,0.1770,0.1379,0.0598,-0.0770",\ +"0.2668,0.2551,0.2434,0.2160,0.1730,0.0988,-0.0379",\ +"0.3449,0.3332,0.3176,0.2902,0.2473,0.1730,0.0363",\ +"0.4816,0.4699,0.4543,0.4270,0.3840,0.3098,0.1770"); + } + + fall_constraint("SIG2SRAM_constraint_template") { + index_1("0.0040,0.0176,0.0344,0.0656,0.1120,0.2016,0.3800"); + index_2("0.0040,0.0176,0.0344,0.0656,0.1120,0.2016,0.3800"); + values ("0.1613,0.1496,0.1379,0.1105,0.0715,0.0012,-0.1355",\ +"0.1730,0.1613,0.1496,0.1184,0.0832,0.0129,-0.1238",\ +"0.1887,0.1770,0.1652,0.1340,0.0988,0.0285,-0.1121",\ +"0.2121,0.2043,0.1887,0.1613,0.1223,0.0520,-0.0848",\ +"0.2551,0.2434,0.2277,0.2004,0.1613,0.0910,-0.0418",\ +"0.3293,0.3176,0.3020,0.2746,0.2395,0.1652,0.0324",\ +"0.4660,0.4543,0.4426,0.4113,0.3762,0.3020,0.1691"); + } + } + } +bus(A_BIST_BM) { + bus_type : D_31_0; + direction : input ; + capacitance : 0.00253457 ; + max_transition : "0.38" ; + pin(A_BIST_BM[31:0]) { + related_power_pin : VDD; + related_ground_pin : VSS; + internal_power() { + when : "A_BIST_MEN"; + rise_power("scalar"){ + values (0.1471); + } + fall_power("scalar"){ + values (0.1374); + } + } + internal_power() { + when : "!A_BIST_MEN"; + rise_power("scalar"){ + values (0.1745); + } + fall_power("scalar"){ + values (0.1522); + } + } + } + timing() { + timing_type : setup_rising; + related_pin : "A_BIST_CLK"; + when : "(A_BIST_WEN & A_BIST_MEN)" + sdf_cond : "A_BIST_RW_ACCESS" + + rise_constraint("SIG2SRAM_constraint_template") { + index_1("0.0040,0.0176,0.0344,0.0656,0.1120,0.2016,0.3800"); + index_2("0.0040,0.0176,0.0344,0.0656,0.1120,0.2016,0.3800"); + values ("-0.2520,-0.2412,-0.2256,-0.1993,-0.1592,-0.0889,0.0459",\ +"-0.2559,-0.2451,-0.2295,-0.2031,-0.1631,-0.0928,0.0420",\ +"-0.2597,-0.2489,-0.2333,-0.2069,-0.1669,-0.0966,0.0382",\ +"-0.2629,-0.2522,-0.2366,-0.2102,-0.1701,-0.0998,0.0349",\ +"-0.2754,-0.2646,-0.2490,-0.2226,-0.1826,-0.1123,0.0225",\ +"-0.2930,-0.2822,-0.2666,-0.2402,-0.2002,-0.1299,0.0049",\ +"-0.3205,-0.3097,-0.2941,-0.2677,-0.2277,-0.1574,-0.0226"); + } + + fall_constraint("SIG2SRAM_constraint_template") { + index_1("0.0040,0.0176,0.0344,0.0656,0.1120,0.2016,0.3800"); + index_2("0.0040,0.0176,0.0344,0.0656,0.1120,0.2016,0.3800"); + values ("-0.2295,-0.2188,-0.2051,-0.1778,-0.1407,-0.0684,0.0615",\ +"-0.2334,-0.2227,-0.2090,-0.1817,-0.1445,-0.0723,0.0576",\ +"-0.2372,-0.2265,-0.2128,-0.1855,-0.1483,-0.0761,0.0538",\ +"-0.2405,-0.2297,-0.2160,-0.1887,-0.1516,-0.0793,0.0506",\ +"-0.2529,-0.2422,-0.2285,-0.2011,-0.1640,-0.0918,0.0381",\ +"-0.2705,-0.2598,-0.2461,-0.2188,-0.1816,-0.1094,0.0205",\ +"-0.2980,-0.2873,-0.2736,-0.2463,-0.2092,-0.1369,-0.0070"); + } + } + + + timing() { + timing_type : hold_rising; + related_pin : "A_BIST_CLK"; + when : "(A_BIST_WEN & A_BIST_MEN)" + sdf_cond : "A_BIST_RW_ACCESS" + + rise_constraint("SIG2SRAM_constraint_template") { + index_1("0.0040,0.0176,0.0344,0.0656,0.1120,0.2016,0.3800"); + index_2("0.0040,0.0176,0.0344,0.0656,0.1120,0.2016,0.3800"); + values ("0.3581,0.3463,0.3317,0.3053,0.2653,0.1940,0.0573",\ +"0.3619,0.3502,0.3356,0.3092,0.2692,0.1979,0.0612",\ +"0.3657,0.3540,0.3394,0.3130,0.2730,0.2017,0.0650",\ +"0.3690,0.3573,0.3426,0.3163,0.2762,0.2049,0.0682",\ +"0.3814,0.3697,0.3551,0.3287,0.2887,0.2174,0.0807",\ +"0.3990,0.3873,0.3727,0.3463,0.3063,0.2350,0.0983",\ +"0.4266,0.4148,0.4002,0.3738,0.3338,0.2625,0.1258"); + } + + fall_constraint("SIG2SRAM_constraint_template") { + index_1("0.0040,0.0176,0.0344,0.0656,0.1120,0.2016,0.3800"); + index_2("0.0040,0.0176,0.0344,0.0656,0.1120,0.2016,0.3800"); + values ("0.3297,0.3200,0.3053,0.2790,0.2418,0.1686,0.0407",\ +"0.3336,0.3239,0.3092,0.2828,0.2457,0.1725,0.0446",\ +"0.3374,0.3276,0.3130,0.2866,0.2495,0.1763,0.0484",\ +"0.3407,0.3309,0.3163,0.2899,0.2528,0.1795,0.0516",\ +"0.3531,0.3433,0.3287,0.3023,0.2652,0.1920,0.0641",\ +"0.3707,0.3610,0.3463,0.3199,0.2828,0.2096,0.0817",\ +"0.3982,0.3885,0.3738,0.3474,0.3103,0.2371,0.1092"); + } + } +} + pin(A_BIST_CLK) { + direction : input; + capacitance : 0.00389386; + max_transition : "0.38"; + clock : "true" ; + pin_func_type : active_rising ; + + timing () { + timing_type : "min_pulse_width"; + related_pin : "A_BIST_CLK"; + rise_constraint("CLKTRAN_constraint_template") { + index_1("0.004,0.38"); + values("0.12,0.12"); + } + } + + related_power_pin : VDD; + related_ground_pin : VSS; + + internal_power() { + when : "!A_BIST_MEN & !A_BIST_WEN & !A_BIST_REN"; + rise_power("scalar"){ + values (0); + } + fall_power("scalar"){ + values (0); + } + } + internal_power() { + when : "!A_BIST_MEN & A_BIST_WEN & !A_BIST_REN"; + rise_power("scalar"){ + values (0.6735); + } + fall_power("scalar"){ + values (0); + } + } + internal_power() { + when : "A_BIST_MEN & A_BIST_WEN & !A_BIST_REN"; + rise_power("scalar"){ + values (54.8620); + } + fall_power("scalar"){ + values (0); + } + } + internal_power() { + when : "A_BIST_MEN & A_BIST_WEN & A_BIST_REN"; + rise_power("scalar"){ + values (56.6091); + } + fall_power("scalar"){ + values (0); + } + } + internal_power() { + when : "A_BIST_MEN & !A_BIST_WEN & A_BIST_REN"; + rise_power("scalar"){ + values (45.3648); + } + fall_power("scalar"){ + values (0); + } + } + internal_power() { + when : "!A_BIST_MEN & !A_BIST_WEN & A_BIST_REN"; + rise_power("scalar"){ + values (0.4386); + } + fall_power("scalar"){ + values (0); + } + } + internal_power() { + when : "!A_BIST_MEN & A_BIST_WEN & A_BIST_REN"; + rise_power("scalar"){ + values (1.6639); + } + fall_power("scalar"){ + values (0); + } + } + internal_power() { + when : "A_BIST_MEN & !A_BIST_WEN & !A_BIST_REN"; + rise_power("scalar"){ + values (0); + } + fall_power("scalar"){ + values (0); + } + } + } + bus(A_BIST_DIN) { + bus_type : D_31_0; + direction : input ; + capacitance : 0.00252927 ; + memory_write() { + address : A_BIST_ADDR ; + clocked_on : A_BIST_CLK; + } + + max_transition : "0.38" ; + pin(A_BIST_DIN[31:0]) { + related_power_pin : VDD; + related_ground_pin : VSS; + internal_power() { + when : "A_BIST_MEN"; + rise_power("scalar"){ + values (0.1471); + } + fall_power("scalar"){ + values (0.1374); + } + } + internal_power() { + when : "!A_BIST_MEN"; + rise_power("scalar"){ + values (0.1745); + } + fall_power("scalar"){ + values (0.1522); + } + } + } + timing() { + timing_type : setup_rising; + related_pin : "A_BIST_CLK"; + when : "(A_BIST_WEN & A_BIST_MEN)"; + sdf_cond : "A_BIST_W_ACCESS"; + + rise_constraint("SIG2SRAM_constraint_template") { + index_1("0.0040,0.0176,0.0344,0.0656,0.1120,0.2016,0.3800"); + index_2("0.0040,0.0176,0.0344,0.0656,0.1120,0.2016,0.3800"); + values ("-0.2520,-0.2412,-0.2256,-0.1993,-0.1592,-0.0889,0.0459",\ +"-0.2559,-0.2451,-0.2295,-0.2031,-0.1631,-0.0928,0.0420",\ +"-0.2597,-0.2489,-0.2333,-0.2069,-0.1669,-0.0966,0.0382",\ +"-0.2629,-0.2522,-0.2366,-0.2102,-0.1701,-0.0998,0.0349",\ +"-0.2754,-0.2646,-0.2490,-0.2226,-0.1826,-0.1123,0.0225",\ +"-0.2930,-0.2822,-0.2666,-0.2402,-0.2002,-0.1299,0.0049",\ +"-0.3205,-0.3097,-0.2941,-0.2677,-0.2277,-0.1574,-0.0226"); + } + + fall_constraint("SIG2SRAM_constraint_template") { + index_1("0.0040,0.0176,0.0344,0.0656,0.1120,0.2016,0.3800"); + index_2("0.0040,0.0176,0.0344,0.0656,0.1120,0.2016,0.3800"); + values ("-0.2295,-0.2188,-0.2051,-0.1778,-0.1407,-0.0684,0.0615",\ +"-0.2334,-0.2227,-0.2090,-0.1817,-0.1445,-0.0723,0.0576",\ +"-0.2372,-0.2265,-0.2128,-0.1855,-0.1483,-0.0761,0.0538",\ +"-0.2405,-0.2297,-0.2160,-0.1887,-0.1516,-0.0793,0.0506",\ +"-0.2529,-0.2422,-0.2285,-0.2011,-0.1640,-0.0918,0.0381",\ +"-0.2705,-0.2598,-0.2461,-0.2188,-0.1816,-0.1094,0.0205",\ +"-0.2980,-0.2873,-0.2736,-0.2463,-0.2092,-0.1369,-0.0070"); + } + } + + timing() { + timing_type : hold_rising; + related_pin : "A_BIST_CLK"; + when : "(A_BIST_WEN & A_BIST_MEN)"; + sdf_cond : "A_BIST_W_ACCESS"; + + rise_constraint("SIG2SRAM_constraint_template") { + index_1("0.0040,0.0176,0.0344,0.0656,0.1120,0.2016,0.3800"); + index_2("0.0040,0.0176,0.0344,0.0656,0.1120,0.2016,0.3800"); + values ("0.3581,0.3463,0.3317,0.3053,0.2653,0.1940,0.0573",\ +"0.3619,0.3502,0.3356,0.3092,0.2692,0.1979,0.0612",\ +"0.3657,0.3540,0.3394,0.3130,0.2730,0.2017,0.0650",\ +"0.3690,0.3573,0.3426,0.3163,0.2762,0.2049,0.0682",\ +"0.3814,0.3697,0.3551,0.3287,0.2887,0.2174,0.0807",\ +"0.3990,0.3873,0.3727,0.3463,0.3063,0.2350,0.0983",\ +"0.4266,0.4148,0.4002,0.3738,0.3338,0.2625,0.1258"); + } + + fall_constraint("SIG2SRAM_constraint_template") { + index_1("0.0040,0.0176,0.0344,0.0656,0.1120,0.2016,0.3800"); + index_2("0.0040,0.0176,0.0344,0.0656,0.1120,0.2016,0.3800"); + values ("0.3297,0.3200,0.3053,0.2790,0.2418,0.1686,0.0407",\ +"0.3336,0.3239,0.3092,0.2828,0.2457,0.1725,0.0446",\ +"0.3374,0.3276,0.3130,0.2866,0.2495,0.1763,0.0484",\ +"0.3407,0.3309,0.3163,0.2899,0.2528,0.1795,0.0516",\ +"0.3531,0.3433,0.3287,0.3023,0.2652,0.1920,0.0641",\ +"0.3707,0.3610,0.3463,0.3199,0.2828,0.2096,0.0817",\ +"0.3982,0.3885,0.3738,0.3474,0.3103,0.2371,0.1092"); + } + } + } + +bus(A_DOUT) { + + bus_type : D_31_0; + direction : output ; + capacitance : 0 ; + max_capacitance : 0.064 ; + memory_read() { + address : A_ADDR ; + } + pin(A_DOUT[31:0]) { + related_power_pin : VDD; + related_ground_pin : VSS; + internal_power() { + rise_power("scalar") { + values (0); + } + fall_power("scalar") { + values (0); + } + } + } + timing() { + related_pin : "A_CLK"; + timing_type : rising_edge ; + timing_sense : non_unate ; + + cell_rise(SIG2SRAM_delay_template) { + index_1("0.0040,0.0176,0.0344,0.0656,0.1120,0.2016,0.3800"); + index_2("0.0008,0.0014,0.0051,0.0100,0.0339,0.0640"); + values ("2.3376,2.3386,2.3434,2.3489,2.3699,2.3934",\ +"2.3440,2.3450,2.3498,2.3553,2.3762,2.3997",\ +"2.3456,2.3466,2.3514,2.3569,2.3778,2.4013",\ +"2.3499,2.3509,2.3557,2.3613,2.3822,2.4057",\ +"2.3631,2.3641,2.3689,2.3744,2.3953,2.4188",\ +"2.3816,2.3826,2.3875,2.3930,2.4139,2.4374",\ +"2.4082,2.4092,2.4140,2.4195,2.4404,2.4639"); + } + cell_fall(SIG2SRAM_delay_template) { + index_1("0.0040,0.0176,0.0344,0.0656,0.1120,0.2016,0.3800"); + index_2("0.0008,0.0014,0.0051,0.0100,0.0339,0.0640"); + values ("2.3033,2.3042,2.3082,2.3128,2.3299,2.3466",\ +"2.3097,2.3106,2.3146,2.3192,2.3362,2.3530",\ +"2.3113,2.3122,2.3162,2.3208,2.3378,2.3546",\ +"2.3156,2.3165,2.3205,2.3251,2.3422,2.3589",\ +"2.3288,2.3297,2.3337,2.3382,2.3553,2.3721",\ +"2.3474,2.3482,2.3522,2.3568,2.3739,2.3906",\ +"2.3739,2.3747,2.3788,2.3833,2.4004,2.4171"); + } + + rise_transition(SRAM_load_template) { + index_1("0.0008,0.0014,0.0051,0.0100,0.0339,0.0640"); + values ("0.0206,0.0210,0.0265,0.0323,0.0606,0.0955"); + } + fall_transition(SRAM_load_template) { + index_1("0.0008,0.0014,0.0051,0.0100,0.0339,0.0640"); + values ("0.0170,0.0177,0.0222,0.0270,0.0451,0.0644"); + } + } +} +cell_leakage_power : 469.5941; +} +} diff --git a/flow/platforms/ihp-sg13g2/lib/RM_IHPSG13_1P_512x32_c2_bm_bist_slow_1p08V_125C.lib b/flow/platforms/ihp-sg13g2/lib/RM_IHPSG13_1P_512x32_c2_bm_bist_slow_1p08V_125C.lib new file mode 100644 index 0000000000..5bf9f229d1 --- /dev/null +++ b/flow/platforms/ihp-sg13g2/lib/RM_IHPSG13_1P_512x32_c2_bm_bist_slow_1p08V_125C.lib @@ -0,0 +1,1519 @@ +/* ------------------------------------------------------*/ +/**/ +/* Copyright 2023 IHP PDK Authors*/ +/**/ +/* Licensed under the Apache License, Version 2.0 (the "License");*/ +/* you may not use this file except in compliance with the License.*/ +/* You may obtain a copy of the License at*/ +/* */ +/* https://www.apache.org/licenses/LICENSE-2.0*/ +/* */ +/* Unless required by applicable law or agreed to in writing, software*/ +/* distributed under the License is distributed on an "AS IS" BASIS,*/ +/* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.*/ +/* See the License for the specific language governing permissions and*/ +/* limitations under the License.*/ +/* */ +/* Generated on Wed Apr 2 16:02:42 2025 */ +/* */ +/* ------------------------------------------------------ */ +library(RM_IHPSG13_1P_512x32_c2_bm_bist_slow_1p08V_125C) { + technology (cmos) ; + delay_model : table_lookup ; + define ("add_pg_pin_to_lib", "library", "boolean"); + add_pg_pin_to_lib : true; + voltage_map ( VDD, 1.08); + voltage_map ( VDDARRAY, 1.08); + voltage_map ( VSS, 0.000000 ); + + date : "Wed Apr 2 16:02:42 2025" ; + comment : "IHP Microelectronics GmbH, 2023" ; + revision : 1.0.0 ; + simulation : true ; + nom_process : 1 ; + nom_temperature : 125 ; + nom_voltage : 1.08 ; + + operating_conditions("slow_1p08V_125C"){ + process : 1 ; + temperature : 125 ; + voltage : 1.08 ; + tree_type : "balanced_tree" ; + } + + default_operating_conditions : slow_1p08V_125C ; + default_max_transition : 1.0 ; + default_fanout_load : 1.0 ; + default_inout_pin_cap : 0.0 ; + default_input_pin_cap : 0.0 ; + default_output_pin_cap : 0.0 ; + default_cell_leakage_power : 0.0 ; + default_leakage_power_density : 0.0 ; + + slew_lower_threshold_pct_rise : 30 ; + slew_upper_threshold_pct_rise : 70 ; + input_threshold_pct_fall : 50 ; + output_threshold_pct_fall : 50 ; + input_threshold_pct_rise : 50 ; + output_threshold_pct_rise : 50 ; + slew_lower_threshold_pct_fall : 30 ; + slew_upper_threshold_pct_fall : 70 ; + slew_derate_from_library : 0.5; + k_volt_cell_leakage_power : 0.0 ; + k_temp_cell_leakage_power : 0.0 ; + k_process_cell_leakage_power : 0.0 ; + k_volt_internal_power : 0.0 ; + k_temp_internal_power : 0.0 ; + k_process_internal_power : 0.0 ; + + capacitive_load_unit (1,pf) ; + voltage_unit : "1V" ; + current_unit : "1uA" ; + time_unit : "1ns" ; + leakage_power_unit : "1nW" ; + pulling_resistance_unit : "1kohm"; + /* + ------------------------------------------------------------------------------------------ + implicit units overview: + cell_area unit : "um" + internal_power unit : "1e-12 * J/toggle = 1 * uW/MHz" + (capacitive_load_unit * voltage_unit^2) per toggle event + ------------------------------------------------------------------------------------------ + */ + library_features(report_delay_calculation); + define_cell_area (pad_drivers,pad_driver_sites) ; + + lu_table_template(CLKTRAN_constraint_template) { + variable_1 : constrained_pin_transition; + index_1 ( "0.010, 0.050, 0.200, 0.400, 1.000" ); + } + lu_table_template(SRAM_load_template) { + variable_1 : total_output_net_capacitance; + index_1 ( "0.0008,0.0014,0.0051,0.0100,0.0339,0.0640" ); + } + lu_table_template(SIG2SRAM_constraint_template) { + variable_1 : related_pin_transition; + variable_2 : constrained_pin_transition; + index_1 ( "0.0080,0.0288,0.0616,0.1072,0.1920,0.3496,0.5952" ); + index_2 ( "0.0080,0.0288,0.0616,0.1072,0.1920,0.3496,0.5952" ); + } + + lu_table_template(SIG2SRAM_delay_template) { + variable_1 : input_net_transition; + variable_2 : total_output_net_capacitance; + index_1 ( "0.0080,0.0288,0.0616,0.1072,0.1920,0.3496,0.5952" ); + index_2 ( "0.0008,0.0014,0.0051,0.0100,0.0339,0.0640" ); + } + + type (D_31_0) { + base_type : array; + data_type : bit; + bit_width : 32; + bit_from : 31; + bit_to : 0; + downto : true; + } + + type (A_8_0) { + base_type : array; + data_type : bit; + bit_width : 9; + bit_from : 8; + bit_to : 0; + downto : true; + } + +cell(RM_IHPSG13_1P_512x32_c2_bm_bist) { +pg_pin (VDD) { + pg_type : primary_power; + voltage_name : VDD; +} +pg_pin (VDDARRAY) { + pg_type : primary_power; + voltage_name : VDDARRAY; +} +pg_pin (VSS) { + pg_type : primary_ground; + voltage_name : VSS; +} + +memory() { + type : ram; + address_width : 9; + word_width : 32; +} + +interface_timing : false; +bus_naming_style : "%s[%d]" ; +area : 79719.8976 ; + + pin(A_DLY) { + direction : input ; + capacitance : 0.00387999 ; + max_transition : "1" ; + related_power_pin : VDD; + related_ground_pin : VSS; + internal_power() { + rise_power("scalar") { + values (0); + } + fall_power("scalar") { + values (0); + } + } + } + +bus(A_ADDR) { + bus_type : A_8_0; + direction : input ; + capacitance : 0.0077013 ; + pin(A_ADDR[0]) { + capacitance : 0.00625349 ; + } + pin(A_ADDR[1]) { + capacitance : 0.00507435 ; + } + pin(A_ADDR[2]) { + capacitance : 0.00656707 ; + } + pin(A_ADDR[3]) { + capacitance : 0.0083133 ; + } + pin(A_ADDR[4]) { + capacitance : 0.00507219 ; + } + pin(A_ADDR[5]) { + capacitance : 0.00964344 ; + } + pin(A_ADDR[6]) { + capacitance : 0.0119653 ; + } + pin(A_ADDR[7]) { + capacitance : 0.00827606 ; + } + max_transition : "0.5952" ; + pin(A_ADDR[8:0]) { + related_power_pin : VDD; + related_ground_pin : VSS; + internal_power() { + when : "A_MEN"; + rise_power("scalar"){ + values (0.0100); + } + fall_power("scalar"){ + values (0.0075); + } + } + internal_power() { + when : "!A_MEN"; + rise_power("scalar"){ + values (0.0165); + } + fall_power("scalar"){ + values (0.0022); + } + } + } + timing() { + timing_type : setup_rising; + related_pin : "A_CLK"; + when : "((A_WEN | A_REN)& A_MEN)" + sdf_cond : "A_RW_ACCESS" + + rise_constraint("SIG2SRAM_constraint_template") { + index_1("0.0080,0.0288,0.0616,0.1072,0.1920,0.3496,0.5952"); + index_2("0.0080,0.0288,0.0616,0.1072,0.1920,0.3496,0.5952"); + values ("-0.7371,-0.7176,-0.6863,-0.6434,-0.5652,-0.4168,-0.1980",\ +"-0.7566,-0.7371,-0.7059,-0.6629,-0.5848,-0.4363,-0.2137",\ +"-0.7879,-0.7645,-0.7332,-0.6902,-0.6121,-0.4637,-0.2449",\ +"-0.8309,-0.8074,-0.7762,-0.7332,-0.6551,-0.5066,-0.2879",\ +"-0.9051,-0.8895,-0.8543,-0.8113,-0.7332,-0.5887,-0.3660",\ +"-1.0418,-1.0262,-0.9949,-0.9480,-0.8699,-0.7293,-0.5027",\ +"-1.2684,-1.2449,-1.2176,-1.1707,-1.0965,-0.9480,-0.7293"); + } + + fall_constraint("SIG2SRAM_constraint_template") { + index_1("0.0080,0.0288,0.0616,0.1072,0.1920,0.3496,0.5952"); + index_2("0.0080,0.0288,0.0616,0.1072,0.1920,0.3496,0.5952"); + values ("-0.5926,-0.5730,-0.5418,-0.4988,-0.4246,-0.2879,-0.0730",\ +"-0.6121,-0.5926,-0.5613,-0.5223,-0.4441,-0.3074,-0.0887",\ +"-0.6395,-0.6199,-0.5926,-0.5496,-0.4715,-0.3348,-0.1160",\ +"-0.6863,-0.6668,-0.6355,-0.5965,-0.5184,-0.3777,-0.1590",\ +"-0.7605,-0.7410,-0.7137,-0.6746,-0.5926,-0.4559,-0.2410",\ +"-0.9012,-0.8816,-0.8504,-0.8113,-0.7332,-0.5926,-0.3895",\ +"-1.1238,-1.1043,-1.0769,-1.0379,-0.9559,-0.8191,-0.6004"); + } + } + + + timing() { + timing_type : hold_rising; + related_pin : "A_CLK"; + when : "((A_WEN | A_REN)& A_MEN)" + sdf_cond : "A_RW_ACCESS" + + rise_constraint("SIG2SRAM_constraint_template") { + index_1("0.0080,0.0288,0.0616,0.1072,0.1920,0.3496,0.5952"); + index_2("0.0080,0.0288,0.0616,0.1072,0.1920,0.3496,0.5952"); + values ("0.8488,0.8293,0.7980,0.7551,0.6730,0.5285,0.3059",\ +"0.8684,0.8488,0.8176,0.7746,0.6926,0.5480,0.3254",\ +"0.8996,0.8801,0.8449,0.8020,0.7238,0.5754,0.3527",\ +"0.9426,0.9191,0.8918,0.8488,0.7668,0.6223,0.3996",\ +"1.0168,1.0012,0.9699,0.9230,0.8449,0.7004,0.4777",\ +"1.1574,1.1379,1.1105,1.0598,0.9816,0.8371,0.6184",\ +"1.3801,1.3605,1.3254,1.2980,1.2043,1.0637,0.8371"); + } + + fall_constraint("SIG2SRAM_constraint_template") { + index_1("0.0080,0.0288,0.0616,0.1072,0.1920,0.3496,0.5952"); + index_2("0.0080,0.0288,0.0616,0.1072,0.1920,0.3496,0.5952"); + values ("0.6965,0.6770,0.6496,0.6066,0.5246,0.3918,0.1730",\ +"0.7160,0.6965,0.6652,0.6262,0.5441,0.4113,0.1965",\ +"0.7473,0.7277,0.6965,0.6535,0.5754,0.4426,0.2238",\ +"0.7863,0.7707,0.7395,0.7004,0.6223,0.4855,0.2629",\ +"0.8684,0.8449,0.8176,0.7785,0.7004,0.5637,0.3449",\ +"1.0051,0.9855,0.9855,0.9113,0.8332,0.7004,0.4895",\ +"1.2277,1.2082,1.1809,1.1379,1.0598,0.9230,0.7004"); + } + } +} +pin(A_WEN) { + direction : input ; + capacitance : 0.00313551 ; + max_transition : "0.5952" ; + related_power_pin : VDD; + related_ground_pin : VSS; + internal_power() { + when : "A_MEN"; + rise_power("scalar"){ + values (0.0036); + } + fall_power("scalar"){ + values (0.0004); + } + } + internal_power() { + when : "!A_MEN"; + rise_power("scalar"){ + values (0.0051); + } + fall_power("scalar"){ + values (0.0001); + } + } + timing() { + timing_type : setup_rising; + related_pin : "A_CLK"; + when : "A_MEN" + sdf_cond : "A_MEN" + + rise_constraint("SIG2SRAM_constraint_template") { + index_1("0.0080,0.0288,0.0616,0.1072,0.1920,0.3496,0.5952"); + index_2("0.0080,0.0288,0.0616,0.1072,0.1920,0.3496,0.5952"); + values ("0.3137,0.3332,0.3605,0.4035,0.4816,0.6223,0.8488",\ +"0.2980,0.3176,0.3410,0.3840,0.4660,0.6027,0.8293",\ +"0.2629,0.2824,0.3098,0.3527,0.4348,0.5754,0.7980",\ +"0.2199,0.2395,0.2668,0.3098,0.3918,0.5324,0.7590",\ +"0.1418,0.1613,0.1887,0.2316,0.3137,0.4348,0.6730",\ +"0.0012,0.0207,0.0520,0.0910,0.1730,0.3098,0.5285",\ +"-0.2215,-0.2020,-0.1746,-0.1277,-0.0496,0.0910,0.3098"); + } + + fall_constraint("SIG2SRAM_constraint_template") { + index_1("0.0080,0.0288,0.0616,0.1072,0.1920,0.3496,0.5952"); + index_2("0.0080,0.0288,0.0616,0.1072,0.1920,0.3496,0.5952"); + values ("0.4504,0.4699,0.4973,0.5324,0.6027,0.7355,0.9699",\ +"0.4309,0.4504,0.4777,0.5129,0.5910,0.7160,0.9504",\ +"0.3996,0.4191,0.4465,0.4816,0.5520,0.6848,0.9191",\ +"0.3605,0.3762,0.4035,0.4387,0.5168,0.6418,0.8723",\ +"0.2785,0.2980,0.3215,0.3605,0.4348,0.5637,0.7980",\ +"0.1379,0.1574,0.1809,0.2199,0.2980,0.4309,0.6457",\ +"-0.0809,-0.0613,-0.0340,0.0051,0.0832,0.2160,0.4191"); + } + } + + + timing() { + timing_type : hold_rising; + related_pin : "A_CLK"; + when : "A_MEN" + sdf_cond : "A_MEN" + + rise_constraint("SIG2SRAM_constraint_template") { + index_1("0.0080,0.0288,0.0616,0.1072,0.1920,0.3496,0.5952"); + index_2("0.0080,0.0288,0.0616,0.1072,0.1920,0.3496,0.5952"); + values ("0.3723,0.3527,0.3215,0.2785,0.1965,0.0559,-0.1668",\ +"0.3918,0.3723,0.3449,0.2980,0.2160,0.0754,-0.1473",\ +"0.4152,0.3996,0.3684,0.3254,0.2434,0.1066,-0.1199",\ +"0.4621,0.4465,0.4152,0.3723,0.2863,0.1496,-0.0730",\ +"0.5324,0.5207,0.4895,0.4465,0.3645,0.2199,0.0051",\ +"0.6770,0.6535,0.6301,0.5832,0.5090,0.3605,0.1418",\ +"0.9035,0.8879,0.8566,0.8137,0.7316,0.5871,0.3684"); + } + + fall_constraint("SIG2SRAM_constraint_template") { + index_1("0.0080,0.0288,0.0616,0.1072,0.1920,0.3496,0.5952"); + index_2("0.0080,0.0288,0.0616,0.1072,0.1920,0.3496,0.5952"); + values ("0.3762,0.3566,0.3293,0.2863,0.2043,0.0676,-0.1434",\ +"0.3957,0.3762,0.3488,0.3059,0.2238,0.0871,-0.1199",\ +"0.4230,0.4035,0.3723,0.3332,0.2512,0.1184,-0.0965",\ +"0.4660,0.4465,0.4191,0.3762,0.2941,0.1613,-0.0496",\ +"0.5324,0.5168,0.4973,0.4543,0.3723,0.2316,0.0285",\ +"0.6809,0.6613,0.6340,0.5910,0.5129,0.3645,0.1652",\ +"0.9113,0.8918,0.8605,0.8176,0.7395,0.5988,0.3879"); + } + } + } +pin(A_REN) { + direction : input ; + capacitance : 0.00381144 ; + max_transition : "0.5952" ; + related_power_pin : VDD; + related_ground_pin : VSS; + internal_power() { + when : "A_MEN"; + rise_power("scalar"){ + values (0.0041); + } + fall_power("scalar"){ + values (0.0013); + } + } + internal_power() { + when : "!A_MEN"; + rise_power("scalar"){ + values (0.0043); + } + fall_power("scalar"){ + values (0.0010); + } + } + timing() { + timing_type : setup_rising; + related_pin : "A_CLK"; + when : "A_MEN" + sdf_cond : "A_MEN" + + rise_constraint("SIG2SRAM_constraint_template") { + index_1("0.0080,0.0288,0.0616,0.1072,0.1920,0.3496,0.5952"); + index_2("0.0080,0.0288,0.0616,0.1072,0.1920,0.3496,0.5952"); + values ("-0.0770,-0.0574,-0.0262,0.0168,0.0949,0.2355,0.4582",\ +"-0.0965,-0.0770,-0.0457,-0.0027,0.0754,0.2160,0.4387",\ +"-0.1199,-0.1004,-0.0730,-0.0262,0.0520,0.1887,0.4113",\ +"-0.1590,-0.1434,-0.1160,-0.0730,0.0051,0.1457,0.3645",\ +"-0.2449,-0.2254,-0.1941,-0.1473,-0.0770,0.0676,0.2863",\ +"-0.3816,-0.3699,-0.3387,-0.2801,-0.2215,-0.0770,0.1457",\ +"-0.6121,-0.5926,-0.5613,-0.5145,-0.4363,-0.2996,-0.0730"); + } + + fall_constraint("SIG2SRAM_constraint_template") { + index_1("0.0080,0.0288,0.0616,0.1072,0.1920,0.3496,0.5952"); + index_2("0.0080,0.0288,0.0616,0.1072,0.1920,0.3496,0.5952"); + values ("0.1262,0.1457,0.1691,0.2121,0.2824,0.4191,0.6457",\ +"0.1105,0.1262,0.1496,0.1887,0.2629,0.3996,0.6262",\ +"0.0793,0.0949,0.1223,0.1652,0.2395,0.3684,0.5949",\ +"0.0363,0.0559,0.0793,0.1223,0.2004,0.3410,0.5520",\ +"-0.0457,-0.0262,0.0012,0.0441,0.1301,0.2629,0.4738",\ +"-0.1902,-0.1746,-0.1434,-0.1043,-0.0184,0.1223,0.3332",\ +"-0.4129,-0.3934,-0.3660,-0.3230,-0.2449,-0.1043,0.1105"); + } + } + + + timing() { + timing_type : hold_rising; + related_pin : "A_CLK"; + when : "A_MEN" + sdf_cond : "A_MEN" + + rise_constraint("SIG2SRAM_constraint_template") { + index_1("0.0080,0.0288,0.0616,0.1072,0.1920,0.3496,0.5952"); + index_2("0.0080,0.0288,0.0616,0.1072,0.1920,0.3496,0.5952"); + values ("0.4113,0.3918,0.3645,0.3176,0.2395,0.0988,-0.1238",\ +"0.4309,0.4113,0.3840,0.3371,0.2590,0.1184,-0.1043",\ +"0.4582,0.4387,0.4113,0.3645,0.2824,0.1457,-0.0770",\ +"0.5051,0.4816,0.4543,0.4074,0.3293,0.1887,-0.0340",\ +"0.5715,0.5598,0.5324,0.4895,0.4035,0.2512,0.0441",\ +"0.7043,0.7004,0.6730,0.6262,0.5402,0.3957,0.1809",\ +"0.9387,0.9270,0.8957,0.8527,0.7746,0.6262,0.4074"); + } + + fall_constraint("SIG2SRAM_constraint_template") { + index_1("0.0080,0.0288,0.0616,0.1072,0.1920,0.3496,0.5952"); + index_2("0.0080,0.0288,0.0616,0.1072,0.1920,0.3496,0.5952"); + values ("0.4152,0.3918,0.3645,0.3215,0.2395,0.1027,-0.1082",\ +"0.4309,0.4113,0.3801,0.3410,0.2590,0.1223,-0.0926",\ +"0.4582,0.4387,0.4074,0.3684,0.2863,0.1496,-0.0613",\ +"0.5012,0.4816,0.4504,0.4074,0.3293,0.1887,-0.0145",\ +"0.5715,0.5559,0.5285,0.4816,0.3996,0.2512,0.0598",\ +"0.7160,0.7004,0.6691,0.6262,0.5520,0.4035,0.2004",\ +"0.9387,0.9191,0.8957,0.8488,0.7707,0.6262,0.4113"); + } + } + } +pin(A_MEN) { + direction : input ; + capacitance : 0.00300347 ; + max_transition : "0.5952" ; + related_power_pin : VDD; + related_ground_pin : VSS; + internal_power() { + rise_power("scalar"){ + values (0.0300); + } + fall_power("scalar"){ + values (0.0003); + } + } + timing() { + timing_type : setup_rising; + related_pin : "A_CLK"; + + rise_constraint("SIG2SRAM_constraint_template") { + index_1("0.0080,0.0288,0.0616,0.1072,0.1920,0.3496,0.5952"); + index_2("0.0080,0.0288,0.0616,0.1072,0.1920,0.3496,0.5952"); + values ("0.3215,0.3449,0.3684,0.4113,0.4895,0.6301,0.8527",\ +"0.3059,0.3254,0.3527,0.3957,0.4738,0.6145,0.8371",\ +"0.2746,0.2941,0.3215,0.3645,0.4426,0.5871,0.8059",\ +"0.2316,0.2512,0.2785,0.3215,0.3996,0.5402,0.7629",\ +"0.1496,0.1730,0.1965,0.2395,0.3215,0.4660,0.6848",\ +"0.0090,0.0285,0.0598,0.1027,0.1809,0.3176,0.5402",\ +"-0.2098,-0.1902,-0.1668,-0.1199,-0.0418,0.0988,0.3137"); + } + + fall_constraint("SIG2SRAM_constraint_template") { + index_1("0.0080,0.0288,0.0616,0.1072,0.1920,0.3496,0.5952"); + index_2("0.0080,0.0288,0.0616,0.1072,0.1920,0.3496,0.5952"); + values ("0.4582,0.4738,0.5012,0.5363,0.6145,0.7395,0.9738",\ +"0.4387,0.4543,0.4816,0.5207,0.5910,0.7199,0.9582",\ +"0.4035,0.4230,0.4504,0.4855,0.5637,0.6887,0.9230",\ +"0.3645,0.3840,0.4074,0.4465,0.5285,0.6496,0.8840",\ +"0.2824,0.3020,0.3254,0.3645,0.4465,0.5715,0.7980",\ +"0.1418,0.1613,0.1887,0.2238,0.3020,0.4309,0.6496",\ +"-0.0770,-0.0574,-0.0301,0.0090,0.0910,0.2238,0.4191"); + } + } + + + timing() { + timing_type : hold_rising; + related_pin : "A_CLK"; + + rise_constraint("SIG2SRAM_constraint_template") { + index_1("0.0080,0.0288,0.0616,0.1072,0.1920,0.3496,0.5952"); + index_2("0.0080,0.0288,0.0616,0.1072,0.1920,0.3496,0.5952"); + values ("0.3762,0.3605,0.3293,0.2863,0.2043,0.0637,-0.1629",\ +"0.3996,0.3801,0.3488,0.3020,0.2238,0.0832,-0.1395",\ +"0.4230,0.4074,0.3723,0.3293,0.2473,0.1105,-0.1121",\ +"0.4621,0.4465,0.4152,0.3762,0.2941,0.1535,-0.0691",\ +"0.5441,0.5285,0.4973,0.4465,0.3684,0.2316,0.0090",\ +"0.6848,0.6652,0.6301,0.5910,0.5129,0.3605,0.1496",\ +"0.9074,0.8918,0.8566,0.8215,0.7395,0.5910,0.3723"); + } + + fall_constraint("SIG2SRAM_constraint_template") { + index_1("0.0080,0.0288,0.0616,0.1072,0.1920,0.3496,0.5952"); + index_2("0.0080,0.0288,0.0616,0.1072,0.1920,0.3496,0.5952"); + values ("0.3762,0.3605,0.3332,0.2863,0.2043,0.0715,-0.1395",\ +"0.3996,0.3762,0.3488,0.3059,0.2238,0.0910,-0.1199",\ +"0.4270,0.4035,0.3762,0.3332,0.2512,0.1184,-0.0965",\ +"0.4699,0.4504,0.4191,0.3762,0.2941,0.1613,-0.0496",\ +"0.5441,0.5285,0.4973,0.4543,0.3762,0.2355,0.0324",\ +"0.6770,0.6613,0.6340,0.5949,0.5207,0.3762,0.1652",\ +"0.9074,0.8918,0.8605,0.8176,0.7395,0.6027,0.3918"); + } + } + } +bus(A_BM) { + bus_type : D_31_0; + direction : input ; + capacitance : 0.00263802 ; + max_transition : "0.5952" ; + pin(A_BM[31:0]) { + related_power_pin : VDD; + related_ground_pin : VSS; + internal_power() { + when : "A_MEN"; + rise_power("scalar"){ + values (0.0936); + } + fall_power("scalar"){ + values (0.0303); + } + } + internal_power() { + when : "!A_MEN"; + rise_power("scalar"){ + values (0.0900); + } + fall_power("scalar"){ + values (0.0290); + } + } + } + timing() { + timing_type : setup_rising; + related_pin : "A_CLK"; + when : "(A_WEN & A_MEN)" + sdf_cond : "A_RW_ACCESS" + + rise_constraint("SIG2SRAM_constraint_template") { + index_1("0.0080,0.0288,0.0616,0.1072,0.1920,0.3496,0.5952"); + index_2("0.0080,0.0288,0.0616,0.1072,0.1920,0.3496,0.5952"); + values ("-0.7914,-0.7719,-0.7455,-0.7035,-0.6225,-0.4779,-0.2572",\ +"-0.7989,-0.7793,-0.7530,-0.7110,-0.6299,-0.4854,-0.2647",\ +"-0.8085,-0.7889,-0.7626,-0.7206,-0.6395,-0.4950,-0.2743",\ +"-0.8216,-0.8021,-0.7757,-0.7337,-0.6527,-0.5081,-0.2874",\ +"-0.8459,-0.8263,-0.8000,-0.7580,-0.6769,-0.5324,-0.3117",\ +"-0.8763,-0.8568,-0.8304,-0.7884,-0.7073,-0.5628,-0.3421",\ +"-0.9579,-0.9384,-0.9120,-0.8700,-0.7890,-0.6444,-0.4237"); + } + + fall_constraint("SIG2SRAM_constraint_template") { + index_1("0.0080,0.0288,0.0616,0.1072,0.1920,0.3496,0.5952"); + index_2("0.0080,0.0288,0.0616,0.1072,0.1920,0.3496,0.5952"); + values ("-0.7358,-0.7201,-0.6918,-0.6527,-0.5717,-0.4340,-0.2221",\ +"-0.7432,-0.7276,-0.6993,-0.6602,-0.5791,-0.4415,-0.2295",\ +"-0.7528,-0.7372,-0.7088,-0.6698,-0.5887,-0.4510,-0.2391",\ +"-0.7659,-0.7503,-0.7220,-0.6829,-0.6019,-0.4642,-0.2523",\ +"-0.7902,-0.7746,-0.7463,-0.7072,-0.6261,-0.4884,-0.2765",\ +"-0.8206,-0.8050,-0.7767,-0.7376,-0.6566,-0.5189,-0.3070",\ +"-0.9022,-0.8866,-0.8583,-0.8192,-0.7382,-0.6005,-0.3886"); + } + } + + + timing() { + timing_type : hold_rising; + related_pin : "A_CLK"; + when : "(A_WEN & A_MEN)" + sdf_cond : "A_RW_ACCESS" + + rise_constraint("SIG2SRAM_constraint_template") { + index_1("0.0080,0.0288,0.0616,0.1072,0.1920,0.3496,0.5952"); + index_2("0.0080,0.0288,0.0616,0.1072,0.1920,0.3496,0.5952"); + values ("0.9084,0.8869,0.8606,0.8176,0.7385,0.5930,0.3674",\ +"0.9159,0.8944,0.8680,0.8251,0.7460,0.6004,0.3749",\ +"0.9255,0.9040,0.8776,0.8346,0.7555,0.6100,0.3844",\ +"0.9386,0.9171,0.8908,0.8478,0.7687,0.6232,0.3976",\ +"0.9629,0.9414,0.9150,0.8720,0.7929,0.6474,0.4218",\ +"0.9933,0.9718,0.9455,0.9025,0.8234,0.6779,0.4523",\ +"1.0749,1.0534,1.0271,0.9841,0.9050,0.7595,0.5339"); + } + + fall_constraint("SIG2SRAM_constraint_template") { + index_1("0.0080,0.0288,0.0616,0.1072,0.1920,0.3496,0.5952"); + index_2("0.0080,0.0288,0.0616,0.1072,0.1920,0.3496,0.5952"); + values ("0.8401,0.8235,0.7951,0.7512,0.6740,0.5363,0.3264",\ +"0.8475,0.8309,0.8026,0.7587,0.6815,0.5438,0.3338",\ +"0.8571,0.8405,0.8122,0.7682,0.6911,0.5534,0.3434",\ +"0.8703,0.8537,0.8253,0.7814,0.7042,0.5665,0.3566",\ +"0.8945,0.8779,0.8496,0.8056,0.7285,0.5908,0.3808",\ +"0.9249,0.9083,0.8800,0.8361,0.7589,0.6212,0.4113",\ +"1.0066,0.9900,0.9616,0.9177,0.8405,0.7028,0.4929"); + } + } +} + pin(A_CLK) { + direction : input; + capacitance : 0.00378957; + max_transition : "0.5952"; + clock : "true" ; + pin_func_type : active_rising ; + + timing () { + timing_type : "min_pulse_width"; + related_pin : "A_CLK"; + rise_constraint("CLKTRAN_constraint_template") { + index_1("0.008,0.5952"); + values("0.4,0.4"); + } + } + + related_power_pin : VDD; + related_ground_pin : VSS; + + internal_power() { + when : "!A_MEN & !A_WEN & !A_REN"; + rise_power("scalar"){ + values (0); + } + fall_power("scalar"){ + values (0); + } + } + internal_power() { + when : "!A_MEN & A_WEN & !A_REN"; + rise_power("scalar"){ + values (0.5614); + } + fall_power("scalar"){ + values (0); + } + } + internal_power() { + when : "A_MEN & A_WEN & !A_REN"; + rise_power("scalar"){ + values (35.0454); + } + fall_power("scalar"){ + values (0); + } + } + internal_power() { + when : "A_MEN & A_WEN & A_REN"; + rise_power("scalar"){ + values (37.3908); + } + fall_power("scalar"){ + values (0); + } + } + internal_power() { + when : "A_MEN & !A_WEN & A_REN"; + rise_power("scalar"){ + values (29.1692); + } + fall_power("scalar"){ + values (0); + } + } + internal_power() { + when : "!A_MEN & !A_WEN & A_REN"; + rise_power("scalar"){ + values (0.3780); + } + fall_power("scalar"){ + values (0); + } + } + internal_power() { + when : "!A_MEN & A_WEN & A_REN"; + rise_power("scalar"){ + values (1.1082); + } + fall_power("scalar"){ + values (0); + } + } + internal_power() { + when : "A_MEN & !A_WEN & !A_REN"; + rise_power("scalar"){ + values (0); + } + fall_power("scalar"){ + values (0); + } + } + } + bus(A_DIN) { + bus_type : D_31_0; + direction : input ; + capacitance : 0.00358485 ; + memory_write() { + address : A_ADDR ; + clocked_on : A_CLK; + } + + max_transition : "0.5952" ; + pin(A_DIN[31:0]) { + related_power_pin : VDD; + related_ground_pin : VSS; + internal_power() { + when : "A_MEN"; + rise_power("scalar"){ + values (0.0936); + } + fall_power("scalar"){ + values (0.0303); + } + } + internal_power() { + when : "!A_MEN"; + rise_power("scalar"){ + values (0.0900); + } + fall_power("scalar"){ + values (0.0290); + } + } + } + timing() { + timing_type : setup_rising; + related_pin : "A_CLK"; + when : "(A_WEN & A_MEN)"; + sdf_cond : "A_W_ACCESS"; + + rise_constraint("SIG2SRAM_constraint_template") { + index_1("0.0080,0.0288,0.0616,0.1072,0.1920,0.3496,0.5952"); + index_2("0.0080,0.0288,0.0616,0.1072,0.1920,0.3496,0.5952"); + values ("-0.7914,-0.7719,-0.7455,-0.7035,-0.6225,-0.4779,-0.2572",\ +"-0.7989,-0.7793,-0.7530,-0.7110,-0.6299,-0.4854,-0.2647",\ +"-0.8085,-0.7889,-0.7626,-0.7206,-0.6395,-0.4950,-0.2743",\ +"-0.8216,-0.8021,-0.7757,-0.7337,-0.6527,-0.5081,-0.2874",\ +"-0.8459,-0.8263,-0.8000,-0.7580,-0.6769,-0.5324,-0.3117",\ +"-0.8763,-0.8568,-0.8304,-0.7884,-0.7073,-0.5628,-0.3421",\ +"-0.9579,-0.9384,-0.9120,-0.8700,-0.7890,-0.6444,-0.4237"); + } + + fall_constraint("SIG2SRAM_constraint_template") { + index_1("0.0080,0.0288,0.0616,0.1072,0.1920,0.3496,0.5952"); + index_2("0.0080,0.0288,0.0616,0.1072,0.1920,0.3496,0.5952"); + values ("-0.7358,-0.7201,-0.6918,-0.6527,-0.5717,-0.4340,-0.2221",\ +"-0.7432,-0.7276,-0.6993,-0.6602,-0.5791,-0.4415,-0.2295",\ +"-0.7528,-0.7372,-0.7088,-0.6698,-0.5887,-0.4510,-0.2391",\ +"-0.7659,-0.7503,-0.7220,-0.6829,-0.6019,-0.4642,-0.2523",\ +"-0.7902,-0.7746,-0.7463,-0.7072,-0.6261,-0.4884,-0.2765",\ +"-0.8206,-0.8050,-0.7767,-0.7376,-0.6566,-0.5189,-0.3070",\ +"-0.9022,-0.8866,-0.8583,-0.8192,-0.7382,-0.6005,-0.3886"); + } + } + + timing() { + timing_type : hold_rising; + related_pin : "A_CLK"; + when : "(A_WEN & A_MEN)"; + sdf_cond : "A_W_ACCESS"; + + rise_constraint("SIG2SRAM_constraint_template") { + index_1("0.0080,0.0288,0.0616,0.1072,0.1920,0.3496,0.5952"); + index_2("0.0080,0.0288,0.0616,0.1072,0.1920,0.3496,0.5952"); + values ("0.9084,0.8869,0.8606,0.8176,0.7385,0.5930,0.3674",\ +"0.9159,0.8944,0.8680,0.8251,0.7460,0.6004,0.3749",\ +"0.9255,0.9040,0.8776,0.8346,0.7555,0.6100,0.3844",\ +"0.9386,0.9171,0.8908,0.8478,0.7687,0.6232,0.3976",\ +"0.9629,0.9414,0.9150,0.8720,0.7929,0.6474,0.4218",\ +"0.9933,0.9718,0.9455,0.9025,0.8234,0.6779,0.4523",\ +"1.0749,1.0534,1.0271,0.9841,0.9050,0.7595,0.5339"); + } + + fall_constraint("SIG2SRAM_constraint_template") { + index_1("0.0080,0.0288,0.0616,0.1072,0.1920,0.3496,0.5952"); + index_2("0.0080,0.0288,0.0616,0.1072,0.1920,0.3496,0.5952"); + values ("0.8401,0.8235,0.7951,0.7512,0.6740,0.5363,0.3264",\ +"0.8475,0.8309,0.8026,0.7587,0.6815,0.5438,0.3338",\ +"0.8571,0.8405,0.8122,0.7682,0.6911,0.5534,0.3434",\ +"0.8703,0.8537,0.8253,0.7814,0.7042,0.5665,0.3566",\ +"0.8945,0.8779,0.8496,0.8056,0.7285,0.5908,0.3808",\ +"0.9249,0.9083,0.8800,0.8361,0.7589,0.6212,0.4113",\ +"1.0066,0.9900,0.9616,0.9177,0.8405,0.7028,0.4929"); + } + } + } + + pin(A_BIST_EN) { + direction : input ; + capacitance : 0.00387999 ; + max_transition : "1" ; + related_power_pin : VDD; + related_ground_pin : VSS; + internal_power() { + rise_power("scalar") { + values (0); + } + fall_power("scalar") { + values (0); + } + } + } + +bus(A_BIST_ADDR) { + bus_type : A_8_0; + direction : input ; + capacitance : 0.0077013 ; + pin(A_BIST_ADDR[0]) { + capacitance : 0.00625349 ; + } + pin(A_BIST_ADDR[1]) { + capacitance : 0.00507435 ; + } + pin(A_BIST_ADDR[2]) { + capacitance : 0.00656707 ; + } + pin(A_BIST_ADDR[3]) { + capacitance : 0.0083133 ; + } + pin(A_BIST_ADDR[4]) { + capacitance : 0.00507219 ; + } + pin(A_BIST_ADDR[5]) { + capacitance : 0.00964344 ; + } + pin(A_BIST_ADDR[6]) { + capacitance : 0.0119653 ; + } + pin(A_BIST_ADDR[7]) { + capacitance : 0.00827606 ; + } + max_transition : "0.5952" ; + pin(A_BIST_ADDR[8:0]) { + related_power_pin : VDD; + related_ground_pin : VSS; + internal_power() { + when : "A_BIST_MEN"; + rise_power("scalar"){ + values (0.0100); + } + fall_power("scalar"){ + values (0.0075); + } + } + internal_power() { + when : "!A_BIST_MEN"; + rise_power("scalar"){ + values (0.0165); + } + fall_power("scalar"){ + values (0.0022); + } + } + } + timing() { + timing_type : setup_rising; + related_pin : "A_BIST_CLK"; + when : "((A_BIST_WEN | A_BIST_REN)& A_BIST_MEN)" + sdf_cond : "A_BIST_RW_ACCESS" + + rise_constraint("SIG2SRAM_constraint_template") { + index_1("0.0080,0.0288,0.0616,0.1072,0.1920,0.3496,0.5952"); + index_2("0.0080,0.0288,0.0616,0.1072,0.1920,0.3496,0.5952"); + values ("-0.7371,-0.7176,-0.6863,-0.6434,-0.5652,-0.4168,-0.1980",\ +"-0.7566,-0.7371,-0.7059,-0.6629,-0.5848,-0.4363,-0.2137",\ +"-0.7879,-0.7645,-0.7332,-0.6902,-0.6121,-0.4637,-0.2449",\ +"-0.8309,-0.8074,-0.7762,-0.7332,-0.6551,-0.5066,-0.2879",\ +"-0.9051,-0.8895,-0.8543,-0.8113,-0.7332,-0.5887,-0.3660",\ +"-1.0418,-1.0262,-0.9949,-0.9480,-0.8699,-0.7293,-0.5027",\ +"-1.2684,-1.2449,-1.2176,-1.1707,-1.0965,-0.9480,-0.7293"); + } + + fall_constraint("SIG2SRAM_constraint_template") { + index_1("0.0080,0.0288,0.0616,0.1072,0.1920,0.3496,0.5952"); + index_2("0.0080,0.0288,0.0616,0.1072,0.1920,0.3496,0.5952"); + values ("-0.5926,-0.5730,-0.5418,-0.4988,-0.4246,-0.2879,-0.0730",\ +"-0.6121,-0.5926,-0.5613,-0.5223,-0.4441,-0.3074,-0.0887",\ +"-0.6395,-0.6199,-0.5926,-0.5496,-0.4715,-0.3348,-0.1160",\ +"-0.6863,-0.6668,-0.6355,-0.5965,-0.5184,-0.3777,-0.1590",\ +"-0.7605,-0.7410,-0.7137,-0.6746,-0.5926,-0.4559,-0.2410",\ +"-0.9012,-0.8816,-0.8504,-0.8113,-0.7332,-0.5926,-0.3895",\ +"-1.1238,-1.1043,-1.0769,-1.0379,-0.9559,-0.8191,-0.6004"); + } + } + + + timing() { + timing_type : hold_rising; + related_pin : "A_BIST_CLK"; + when : "((A_BIST_WEN | A_BIST_REN)& A_BIST_MEN)" + sdf_cond : "A_BIST_RW_ACCESS" + + rise_constraint("SIG2SRAM_constraint_template") { + index_1("0.0080,0.0288,0.0616,0.1072,0.1920,0.3496,0.5952"); + index_2("0.0080,0.0288,0.0616,0.1072,0.1920,0.3496,0.5952"); + values ("0.8488,0.8293,0.7980,0.7551,0.6730,0.5285,0.3059",\ +"0.8684,0.8488,0.8176,0.7746,0.6926,0.5480,0.3254",\ +"0.8996,0.8801,0.8449,0.8020,0.7238,0.5754,0.3527",\ +"0.9426,0.9191,0.8918,0.8488,0.7668,0.6223,0.3996",\ +"1.0168,1.0012,0.9699,0.9230,0.8449,0.7004,0.4777",\ +"1.1574,1.1379,1.1105,1.0598,0.9816,0.8371,0.6184",\ +"1.3801,1.3605,1.3254,1.2980,1.2043,1.0637,0.8371"); + } + + fall_constraint("SIG2SRAM_constraint_template") { + index_1("0.0080,0.0288,0.0616,0.1072,0.1920,0.3496,0.5952"); + index_2("0.0080,0.0288,0.0616,0.1072,0.1920,0.3496,0.5952"); + values ("0.6965,0.6770,0.6496,0.6066,0.5246,0.3918,0.1730",\ +"0.7160,0.6965,0.6652,0.6262,0.5441,0.4113,0.1965",\ +"0.7473,0.7277,0.6965,0.6535,0.5754,0.4426,0.2238",\ +"0.7863,0.7707,0.7395,0.7004,0.6223,0.4855,0.2629",\ +"0.8684,0.8449,0.8176,0.7785,0.7004,0.5637,0.3449",\ +"1.0051,0.9855,0.9855,0.9113,0.8332,0.7004,0.4895",\ +"1.2277,1.2082,1.1809,1.1379,1.0598,0.9230,0.7004"); + } + } +} +pin(A_BIST_WEN) { + direction : input ; + capacitance : 0.00313551 ; + max_transition : "0.5952" ; + related_power_pin : VDD; + related_ground_pin : VSS; + internal_power() { + when : "A_BIST_MEN"; + rise_power("scalar"){ + values (0.0036); + } + fall_power("scalar"){ + values (0.0004); + } + } + internal_power() { + when : "!A_BIST_MEN"; + rise_power("scalar"){ + values (0.0051); + } + fall_power("scalar"){ + values (0.0001); + } + } + timing() { + timing_type : setup_rising; + related_pin : "A_BIST_CLK"; + when : "A_BIST_MEN" + sdf_cond : "A_BIST_MEN" + + rise_constraint("SIG2SRAM_constraint_template") { + index_1("0.0080,0.0288,0.0616,0.1072,0.1920,0.3496,0.5952"); + index_2("0.0080,0.0288,0.0616,0.1072,0.1920,0.3496,0.5952"); + values ("0.3137,0.3332,0.3605,0.4035,0.4816,0.6223,0.8488",\ +"0.2980,0.3176,0.3410,0.3840,0.4660,0.6027,0.8293",\ +"0.2629,0.2824,0.3098,0.3527,0.4348,0.5754,0.7980",\ +"0.2199,0.2395,0.2668,0.3098,0.3918,0.5324,0.7590",\ +"0.1418,0.1613,0.1887,0.2316,0.3137,0.4348,0.6730",\ +"0.0012,0.0207,0.0520,0.0910,0.1730,0.3098,0.5285",\ +"-0.2215,-0.2020,-0.1746,-0.1277,-0.0496,0.0910,0.3098"); + } + + fall_constraint("SIG2SRAM_constraint_template") { + index_1("0.0080,0.0288,0.0616,0.1072,0.1920,0.3496,0.5952"); + index_2("0.0080,0.0288,0.0616,0.1072,0.1920,0.3496,0.5952"); + values ("0.4504,0.4699,0.4973,0.5324,0.6027,0.7355,0.9699",\ +"0.4309,0.4504,0.4777,0.5129,0.5910,0.7160,0.9504",\ +"0.3996,0.4191,0.4465,0.4816,0.5520,0.6848,0.9191",\ +"0.3605,0.3762,0.4035,0.4387,0.5168,0.6418,0.8723",\ +"0.2785,0.2980,0.3215,0.3605,0.4348,0.5637,0.7980",\ +"0.1379,0.1574,0.1809,0.2199,0.2980,0.4309,0.6457",\ +"-0.0809,-0.0613,-0.0340,0.0051,0.0832,0.2160,0.4191"); + } + } + + + timing() { + timing_type : hold_rising; + related_pin : "A_BIST_CLK"; + when : "A_BIST_MEN" + sdf_cond : "A_BIST_MEN" + + rise_constraint("SIG2SRAM_constraint_template") { + index_1("0.0080,0.0288,0.0616,0.1072,0.1920,0.3496,0.5952"); + index_2("0.0080,0.0288,0.0616,0.1072,0.1920,0.3496,0.5952"); + values ("0.3723,0.3527,0.3215,0.2785,0.1965,0.0559,-0.1668",\ +"0.3918,0.3723,0.3449,0.2980,0.2160,0.0754,-0.1473",\ +"0.4152,0.3996,0.3684,0.3254,0.2434,0.1066,-0.1199",\ +"0.4621,0.4465,0.4152,0.3723,0.2863,0.1496,-0.0730",\ +"0.5324,0.5207,0.4895,0.4465,0.3645,0.2199,0.0051",\ +"0.6770,0.6535,0.6301,0.5832,0.5090,0.3605,0.1418",\ +"0.9035,0.8879,0.8566,0.8137,0.7316,0.5871,0.3684"); + } + + fall_constraint("SIG2SRAM_constraint_template") { + index_1("0.0080,0.0288,0.0616,0.1072,0.1920,0.3496,0.5952"); + index_2("0.0080,0.0288,0.0616,0.1072,0.1920,0.3496,0.5952"); + values ("0.3762,0.3566,0.3293,0.2863,0.2043,0.0676,-0.1434",\ +"0.3957,0.3762,0.3488,0.3059,0.2238,0.0871,-0.1199",\ +"0.4230,0.4035,0.3723,0.3332,0.2512,0.1184,-0.0965",\ +"0.4660,0.4465,0.4191,0.3762,0.2941,0.1613,-0.0496",\ +"0.5324,0.5168,0.4973,0.4543,0.3723,0.2316,0.0285",\ +"0.6809,0.6613,0.6340,0.5910,0.5129,0.3645,0.1652",\ +"0.9113,0.8918,0.8605,0.8176,0.7395,0.5988,0.3879"); + } + } + } +pin(A_BIST_REN) { + direction : input ; + capacitance : 0.00381144 ; + max_transition : "0.5952" ; + related_power_pin : VDD; + related_ground_pin : VSS; + internal_power() { + when : "A_BIST_MEN"; + rise_power("scalar"){ + values (0.0041); + } + fall_power("scalar"){ + values (0.0013); + } + } + internal_power() { + when : "!A_BIST_MEN"; + rise_power("scalar"){ + values (0.0043); + } + fall_power("scalar"){ + values (0.0010); + } + } + timing() { + timing_type : setup_rising; + related_pin : "A_BIST_CLK"; + when : "A_BIST_MEN" + sdf_cond : "A_BIST_MEN" + + rise_constraint("SIG2SRAM_constraint_template") { + index_1("0.0080,0.0288,0.0616,0.1072,0.1920,0.3496,0.5952"); + index_2("0.0080,0.0288,0.0616,0.1072,0.1920,0.3496,0.5952"); + values ("-0.0770,-0.0574,-0.0262,0.0168,0.0949,0.2355,0.4582",\ +"-0.0965,-0.0770,-0.0457,-0.0027,0.0754,0.2160,0.4387",\ +"-0.1199,-0.1004,-0.0730,-0.0262,0.0520,0.1887,0.4113",\ +"-0.1590,-0.1434,-0.1160,-0.0730,0.0051,0.1457,0.3645",\ +"-0.2449,-0.2254,-0.1941,-0.1473,-0.0770,0.0676,0.2863",\ +"-0.3816,-0.3699,-0.3387,-0.2801,-0.2215,-0.0770,0.1457",\ +"-0.6121,-0.5926,-0.5613,-0.5145,-0.4363,-0.2996,-0.0730"); + } + + fall_constraint("SIG2SRAM_constraint_template") { + index_1("0.0080,0.0288,0.0616,0.1072,0.1920,0.3496,0.5952"); + index_2("0.0080,0.0288,0.0616,0.1072,0.1920,0.3496,0.5952"); + values ("0.1262,0.1457,0.1691,0.2121,0.2824,0.4191,0.6457",\ +"0.1105,0.1262,0.1496,0.1887,0.2629,0.3996,0.6262",\ +"0.0793,0.0949,0.1223,0.1652,0.2395,0.3684,0.5949",\ +"0.0363,0.0559,0.0793,0.1223,0.2004,0.3410,0.5520",\ +"-0.0457,-0.0262,0.0012,0.0441,0.1301,0.2629,0.4738",\ +"-0.1902,-0.1746,-0.1434,-0.1043,-0.0184,0.1223,0.3332",\ +"-0.4129,-0.3934,-0.3660,-0.3230,-0.2449,-0.1043,0.1105"); + } + } + + + timing() { + timing_type : hold_rising; + related_pin : "A_BIST_CLK"; + when : "A_BIST_MEN" + sdf_cond : "A_BIST_MEN" + + rise_constraint("SIG2SRAM_constraint_template") { + index_1("0.0080,0.0288,0.0616,0.1072,0.1920,0.3496,0.5952"); + index_2("0.0080,0.0288,0.0616,0.1072,0.1920,0.3496,0.5952"); + values ("0.4113,0.3918,0.3645,0.3176,0.2395,0.0988,-0.1238",\ +"0.4309,0.4113,0.3840,0.3371,0.2590,0.1184,-0.1043",\ +"0.4582,0.4387,0.4113,0.3645,0.2824,0.1457,-0.0770",\ +"0.5051,0.4816,0.4543,0.4074,0.3293,0.1887,-0.0340",\ +"0.5715,0.5598,0.5324,0.4895,0.4035,0.2512,0.0441",\ +"0.7043,0.7004,0.6730,0.6262,0.5402,0.3957,0.1809",\ +"0.9387,0.9270,0.8957,0.8527,0.7746,0.6262,0.4074"); + } + + fall_constraint("SIG2SRAM_constraint_template") { + index_1("0.0080,0.0288,0.0616,0.1072,0.1920,0.3496,0.5952"); + index_2("0.0080,0.0288,0.0616,0.1072,0.1920,0.3496,0.5952"); + values ("0.4152,0.3918,0.3645,0.3215,0.2395,0.1027,-0.1082",\ +"0.4309,0.4113,0.3801,0.3410,0.2590,0.1223,-0.0926",\ +"0.4582,0.4387,0.4074,0.3684,0.2863,0.1496,-0.0613",\ +"0.5012,0.4816,0.4504,0.4074,0.3293,0.1887,-0.0145",\ +"0.5715,0.5559,0.5285,0.4816,0.3996,0.2512,0.0598",\ +"0.7160,0.7004,0.6691,0.6262,0.5520,0.4035,0.2004",\ +"0.9387,0.9191,0.8957,0.8488,0.7707,0.6262,0.4113"); + } + } + } +pin(A_BIST_MEN) { + direction : input ; + capacitance : 0.00300347 ; + max_transition : "0.5952" ; + related_power_pin : VDD; + related_ground_pin : VSS; + internal_power() { + rise_power("scalar"){ + values (0.0300); + } + fall_power("scalar"){ + values (0.0003); + } + } + timing() { + timing_type : setup_rising; + related_pin : "A_BIST_CLK"; + + rise_constraint("SIG2SRAM_constraint_template") { + index_1("0.0080,0.0288,0.0616,0.1072,0.1920,0.3496,0.5952"); + index_2("0.0080,0.0288,0.0616,0.1072,0.1920,0.3496,0.5952"); + values ("0.3215,0.3449,0.3684,0.4113,0.4895,0.6301,0.8527",\ +"0.3059,0.3254,0.3527,0.3957,0.4738,0.6145,0.8371",\ +"0.2746,0.2941,0.3215,0.3645,0.4426,0.5871,0.8059",\ +"0.2316,0.2512,0.2785,0.3215,0.3996,0.5402,0.7629",\ +"0.1496,0.1730,0.1965,0.2395,0.3215,0.4660,0.6848",\ +"0.0090,0.0285,0.0598,0.1027,0.1809,0.3176,0.5402",\ +"-0.2098,-0.1902,-0.1668,-0.1199,-0.0418,0.0988,0.3137"); + } + + fall_constraint("SIG2SRAM_constraint_template") { + index_1("0.0080,0.0288,0.0616,0.1072,0.1920,0.3496,0.5952"); + index_2("0.0080,0.0288,0.0616,0.1072,0.1920,0.3496,0.5952"); + values ("0.4582,0.4738,0.5012,0.5363,0.6145,0.7395,0.9738",\ +"0.4387,0.4543,0.4816,0.5207,0.5910,0.7199,0.9582",\ +"0.4035,0.4230,0.4504,0.4855,0.5637,0.6887,0.9230",\ +"0.3645,0.3840,0.4074,0.4465,0.5285,0.6496,0.8840",\ +"0.2824,0.3020,0.3254,0.3645,0.4465,0.5715,0.7980",\ +"0.1418,0.1613,0.1887,0.2238,0.3020,0.4309,0.6496",\ +"-0.0770,-0.0574,-0.0301,0.0090,0.0910,0.2238,0.4191"); + } + } + + + timing() { + timing_type : hold_rising; + related_pin : "A_BIST_CLK"; + + rise_constraint("SIG2SRAM_constraint_template") { + index_1("0.0080,0.0288,0.0616,0.1072,0.1920,0.3496,0.5952"); + index_2("0.0080,0.0288,0.0616,0.1072,0.1920,0.3496,0.5952"); + values ("0.3762,0.3605,0.3293,0.2863,0.2043,0.0637,-0.1629",\ +"0.3996,0.3801,0.3488,0.3020,0.2238,0.0832,-0.1395",\ +"0.4230,0.4074,0.3723,0.3293,0.2473,0.1105,-0.1121",\ +"0.4621,0.4465,0.4152,0.3762,0.2941,0.1535,-0.0691",\ +"0.5441,0.5285,0.4973,0.4465,0.3684,0.2316,0.0090",\ +"0.6848,0.6652,0.6301,0.5910,0.5129,0.3605,0.1496",\ +"0.9074,0.8918,0.8566,0.8215,0.7395,0.5910,0.3723"); + } + + fall_constraint("SIG2SRAM_constraint_template") { + index_1("0.0080,0.0288,0.0616,0.1072,0.1920,0.3496,0.5952"); + index_2("0.0080,0.0288,0.0616,0.1072,0.1920,0.3496,0.5952"); + values ("0.3762,0.3605,0.3332,0.2863,0.2043,0.0715,-0.1395",\ +"0.3996,0.3762,0.3488,0.3059,0.2238,0.0910,-0.1199",\ +"0.4270,0.4035,0.3762,0.3332,0.2512,0.1184,-0.0965",\ +"0.4699,0.4504,0.4191,0.3762,0.2941,0.1613,-0.0496",\ +"0.5441,0.5285,0.4973,0.4543,0.3762,0.2355,0.0324",\ +"0.6770,0.6613,0.6340,0.5949,0.5207,0.3762,0.1652",\ +"0.9074,0.8918,0.8605,0.8176,0.7395,0.6027,0.3918"); + } + } + } +bus(A_BIST_BM) { + bus_type : D_31_0; + direction : input ; + capacitance : 0.00225269 ; + max_transition : "0.5952" ; + pin(A_BIST_BM[31:0]) { + related_power_pin : VDD; + related_ground_pin : VSS; + internal_power() { + when : "A_BIST_MEN"; + rise_power("scalar"){ + values (0.0936); + } + fall_power("scalar"){ + values (0.0303); + } + } + internal_power() { + when : "!A_BIST_MEN"; + rise_power("scalar"){ + values (0.0900); + } + fall_power("scalar"){ + values (0.0290); + } + } + } + timing() { + timing_type : setup_rising; + related_pin : "A_BIST_CLK"; + when : "(A_BIST_WEN & A_BIST_MEN)" + sdf_cond : "A_BIST_RW_ACCESS" + + rise_constraint("SIG2SRAM_constraint_template") { + index_1("0.0080,0.0288,0.0616,0.1072,0.1920,0.3496,0.5952"); + index_2("0.0080,0.0288,0.0616,0.1072,0.1920,0.3496,0.5952"); + values ("-0.7914,-0.7719,-0.7455,-0.7035,-0.6225,-0.4779,-0.2572",\ +"-0.7989,-0.7793,-0.7530,-0.7110,-0.6299,-0.4854,-0.2647",\ +"-0.8085,-0.7889,-0.7626,-0.7206,-0.6395,-0.4950,-0.2743",\ +"-0.8216,-0.8021,-0.7757,-0.7337,-0.6527,-0.5081,-0.2874",\ +"-0.8459,-0.8263,-0.8000,-0.7580,-0.6769,-0.5324,-0.3117",\ +"-0.8763,-0.8568,-0.8304,-0.7884,-0.7073,-0.5628,-0.3421",\ +"-0.9579,-0.9384,-0.9120,-0.8700,-0.7890,-0.6444,-0.4237"); + } + + fall_constraint("SIG2SRAM_constraint_template") { + index_1("0.0080,0.0288,0.0616,0.1072,0.1920,0.3496,0.5952"); + index_2("0.0080,0.0288,0.0616,0.1072,0.1920,0.3496,0.5952"); + values ("-0.7358,-0.7201,-0.6918,-0.6527,-0.5717,-0.4340,-0.2221",\ +"-0.7432,-0.7276,-0.6993,-0.6602,-0.5791,-0.4415,-0.2295",\ +"-0.7528,-0.7372,-0.7088,-0.6698,-0.5887,-0.4510,-0.2391",\ +"-0.7659,-0.7503,-0.7220,-0.6829,-0.6019,-0.4642,-0.2523",\ +"-0.7902,-0.7746,-0.7463,-0.7072,-0.6261,-0.4884,-0.2765",\ +"-0.8206,-0.8050,-0.7767,-0.7376,-0.6566,-0.5189,-0.3070",\ +"-0.9022,-0.8866,-0.8583,-0.8192,-0.7382,-0.6005,-0.3886"); + } + } + + + timing() { + timing_type : hold_rising; + related_pin : "A_BIST_CLK"; + when : "(A_BIST_WEN & A_BIST_MEN)" + sdf_cond : "A_BIST_RW_ACCESS" + + rise_constraint("SIG2SRAM_constraint_template") { + index_1("0.0080,0.0288,0.0616,0.1072,0.1920,0.3496,0.5952"); + index_2("0.0080,0.0288,0.0616,0.1072,0.1920,0.3496,0.5952"); + values ("0.9084,0.8869,0.8606,0.8176,0.7385,0.5930,0.3674",\ +"0.9159,0.8944,0.8680,0.8251,0.7460,0.6004,0.3749",\ +"0.9255,0.9040,0.8776,0.8346,0.7555,0.6100,0.3844",\ +"0.9386,0.9171,0.8908,0.8478,0.7687,0.6232,0.3976",\ +"0.9629,0.9414,0.9150,0.8720,0.7929,0.6474,0.4218",\ +"0.9933,0.9718,0.9455,0.9025,0.8234,0.6779,0.4523",\ +"1.0749,1.0534,1.0271,0.9841,0.9050,0.7595,0.5339"); + } + + fall_constraint("SIG2SRAM_constraint_template") { + index_1("0.0080,0.0288,0.0616,0.1072,0.1920,0.3496,0.5952"); + index_2("0.0080,0.0288,0.0616,0.1072,0.1920,0.3496,0.5952"); + values ("0.8401,0.8235,0.7951,0.7512,0.6740,0.5363,0.3264",\ +"0.8475,0.8309,0.8026,0.7587,0.6815,0.5438,0.3338",\ +"0.8571,0.8405,0.8122,0.7682,0.6911,0.5534,0.3434",\ +"0.8703,0.8537,0.8253,0.7814,0.7042,0.5665,0.3566",\ +"0.8945,0.8779,0.8496,0.8056,0.7285,0.5908,0.3808",\ +"0.9249,0.9083,0.8800,0.8361,0.7589,0.6212,0.4113",\ +"1.0066,0.9900,0.9616,0.9177,0.8405,0.7028,0.4929"); + } + } +} + pin(A_BIST_CLK) { + direction : input; + capacitance : 0.00378957; + max_transition : "0.5952"; + clock : "true" ; + pin_func_type : active_rising ; + + timing () { + timing_type : "min_pulse_width"; + related_pin : "A_BIST_CLK"; + rise_constraint("CLKTRAN_constraint_template") { + index_1("0.008,0.5952"); + values("0.4,0.4"); + } + } + + related_power_pin : VDD; + related_ground_pin : VSS; + + internal_power() { + when : "!A_BIST_MEN & !A_BIST_WEN & !A_BIST_REN"; + rise_power("scalar"){ + values (0); + } + fall_power("scalar"){ + values (0); + } + } + internal_power() { + when : "!A_BIST_MEN & A_BIST_WEN & !A_BIST_REN"; + rise_power("scalar"){ + values (0.5614); + } + fall_power("scalar"){ + values (0); + } + } + internal_power() { + when : "A_BIST_MEN & A_BIST_WEN & !A_BIST_REN"; + rise_power("scalar"){ + values (35.0454); + } + fall_power("scalar"){ + values (0); + } + } + internal_power() { + when : "A_BIST_MEN & A_BIST_WEN & A_BIST_REN"; + rise_power("scalar"){ + values (37.3908); + } + fall_power("scalar"){ + values (0); + } + } + internal_power() { + when : "A_BIST_MEN & !A_BIST_WEN & A_BIST_REN"; + rise_power("scalar"){ + values (29.1692); + } + fall_power("scalar"){ + values (0); + } + } + internal_power() { + when : "!A_BIST_MEN & !A_BIST_WEN & A_BIST_REN"; + rise_power("scalar"){ + values (0.3780); + } + fall_power("scalar"){ + values (0); + } + } + internal_power() { + when : "!A_BIST_MEN & A_BIST_WEN & A_BIST_REN"; + rise_power("scalar"){ + values (1.1082); + } + fall_power("scalar"){ + values (0); + } + } + internal_power() { + when : "A_BIST_MEN & !A_BIST_WEN & !A_BIST_REN"; + rise_power("scalar"){ + values (0); + } + fall_power("scalar"){ + values (0); + } + } + } + bus(A_BIST_DIN) { + bus_type : D_31_0; + direction : input ; + capacitance : 0.00226348 ; + memory_write() { + address : A_BIST_ADDR ; + clocked_on : A_BIST_CLK; + } + + max_transition : "0.5952" ; + pin(A_BIST_DIN[31:0]) { + related_power_pin : VDD; + related_ground_pin : VSS; + internal_power() { + when : "A_BIST_MEN"; + rise_power("scalar"){ + values (0.0936); + } + fall_power("scalar"){ + values (0.0303); + } + } + internal_power() { + when : "!A_BIST_MEN"; + rise_power("scalar"){ + values (0.0900); + } + fall_power("scalar"){ + values (0.0290); + } + } + } + timing() { + timing_type : setup_rising; + related_pin : "A_BIST_CLK"; + when : "(A_BIST_WEN & A_BIST_MEN)"; + sdf_cond : "A_BIST_W_ACCESS"; + + rise_constraint("SIG2SRAM_constraint_template") { + index_1("0.0080,0.0288,0.0616,0.1072,0.1920,0.3496,0.5952"); + index_2("0.0080,0.0288,0.0616,0.1072,0.1920,0.3496,0.5952"); + values ("-0.7914,-0.7719,-0.7455,-0.7035,-0.6225,-0.4779,-0.2572",\ +"-0.7989,-0.7793,-0.7530,-0.7110,-0.6299,-0.4854,-0.2647",\ +"-0.8085,-0.7889,-0.7626,-0.7206,-0.6395,-0.4950,-0.2743",\ +"-0.8216,-0.8021,-0.7757,-0.7337,-0.6527,-0.5081,-0.2874",\ +"-0.8459,-0.8263,-0.8000,-0.7580,-0.6769,-0.5324,-0.3117",\ +"-0.8763,-0.8568,-0.8304,-0.7884,-0.7073,-0.5628,-0.3421",\ +"-0.9579,-0.9384,-0.9120,-0.8700,-0.7890,-0.6444,-0.4237"); + } + + fall_constraint("SIG2SRAM_constraint_template") { + index_1("0.0080,0.0288,0.0616,0.1072,0.1920,0.3496,0.5952"); + index_2("0.0080,0.0288,0.0616,0.1072,0.1920,0.3496,0.5952"); + values ("-0.7358,-0.7201,-0.6918,-0.6527,-0.5717,-0.4340,-0.2221",\ +"-0.7432,-0.7276,-0.6993,-0.6602,-0.5791,-0.4415,-0.2295",\ +"-0.7528,-0.7372,-0.7088,-0.6698,-0.5887,-0.4510,-0.2391",\ +"-0.7659,-0.7503,-0.7220,-0.6829,-0.6019,-0.4642,-0.2523",\ +"-0.7902,-0.7746,-0.7463,-0.7072,-0.6261,-0.4884,-0.2765",\ +"-0.8206,-0.8050,-0.7767,-0.7376,-0.6566,-0.5189,-0.3070",\ +"-0.9022,-0.8866,-0.8583,-0.8192,-0.7382,-0.6005,-0.3886"); + } + } + + timing() { + timing_type : hold_rising; + related_pin : "A_BIST_CLK"; + when : "(A_BIST_WEN & A_BIST_MEN)"; + sdf_cond : "A_BIST_W_ACCESS"; + + rise_constraint("SIG2SRAM_constraint_template") { + index_1("0.0080,0.0288,0.0616,0.1072,0.1920,0.3496,0.5952"); + index_2("0.0080,0.0288,0.0616,0.1072,0.1920,0.3496,0.5952"); + values ("0.9084,0.8869,0.8606,0.8176,0.7385,0.5930,0.3674",\ +"0.9159,0.8944,0.8680,0.8251,0.7460,0.6004,0.3749",\ +"0.9255,0.9040,0.8776,0.8346,0.7555,0.6100,0.3844",\ +"0.9386,0.9171,0.8908,0.8478,0.7687,0.6232,0.3976",\ +"0.9629,0.9414,0.9150,0.8720,0.7929,0.6474,0.4218",\ +"0.9933,0.9718,0.9455,0.9025,0.8234,0.6779,0.4523",\ +"1.0749,1.0534,1.0271,0.9841,0.9050,0.7595,0.5339"); + } + + fall_constraint("SIG2SRAM_constraint_template") { + index_1("0.0080,0.0288,0.0616,0.1072,0.1920,0.3496,0.5952"); + index_2("0.0080,0.0288,0.0616,0.1072,0.1920,0.3496,0.5952"); + values ("0.8401,0.8235,0.7951,0.7512,0.6740,0.5363,0.3264",\ +"0.8475,0.8309,0.8026,0.7587,0.6815,0.5438,0.3338",\ +"0.8571,0.8405,0.8122,0.7682,0.6911,0.5534,0.3434",\ +"0.8703,0.8537,0.8253,0.7814,0.7042,0.5665,0.3566",\ +"0.8945,0.8779,0.8496,0.8056,0.7285,0.5908,0.3808",\ +"0.9249,0.9083,0.8800,0.8361,0.7589,0.6212,0.4113",\ +"1.0066,0.9900,0.9616,0.9177,0.8405,0.7028,0.4929"); + } + } + } + +bus(A_DOUT) { + + bus_type : D_31_0; + direction : output ; + capacitance : 0 ; + max_capacitance : 0.064 ; + memory_read() { + address : A_ADDR ; + } + pin(A_DOUT[31:0]) { + related_power_pin : VDD; + related_ground_pin : VSS; + internal_power() { + rise_power("scalar") { + values (0); + } + fall_power("scalar") { + values (0); + } + } + } + timing() { + related_pin : "A_CLK"; + timing_type : rising_edge ; + timing_sense : non_unate ; + + cell_rise(SIG2SRAM_delay_template) { + index_1("0.0080,0.0288,0.0616,0.1072,0.1920,0.3496,0.5952"); + index_2("0.0008,0.0014,0.0051,0.0100,0.0339,0.0640"); + values ("6.3821,6.3849,6.3970,6.4112,6.4638,6.5188",\ +"6.3865,6.3892,6.4014,6.4156,6.4682,6.5231",\ +"6.3969,6.3997,6.4118,6.4260,6.4786,6.5336",\ +"6.4176,6.4203,6.4325,6.4467,6.4993,6.5542",\ +"6.4319,6.4346,6.4467,6.4609,6.5135,6.5685",\ +"6.4653,6.4680,6.4802,6.4944,6.5470,6.6019",\ +"6.5510,6.5537,6.5659,6.5801,6.6327,6.6876"); + } + cell_fall(SIG2SRAM_delay_template) { + index_1("0.0080,0.0288,0.0616,0.1072,0.1920,0.3496,0.5952"); + index_2("0.0008,0.0014,0.0051,0.0100,0.0339,0.0640"); + values ("6.2720,6.2741,6.2839,6.2957,6.3393,6.3830",\ +"6.2763,6.2785,6.2883,6.3001,6.3436,6.3874",\ +"6.2868,6.2889,6.2987,6.3105,6.3541,6.3978",\ +"6.3074,6.3096,6.3193,6.3312,6.3747,6.4185",\ +"6.3217,6.3238,6.3336,6.3454,6.3890,6.4327",\ +"6.3551,6.3573,6.3670,6.3789,6.4224,6.4662",\ +"6.4408,6.4430,6.4527,6.4646,6.5081,6.5519"); + } + + rise_transition(SRAM_load_template) { + index_1("0.0008,0.0014,0.0051,0.0100,0.0339,0.0640"); + values ("0.0560,0.0583,0.0696,0.0816,0.1519,0.2335"); + } + fall_transition(SRAM_load_template) { + index_1("0.0008,0.0014,0.0051,0.0100,0.0339,0.0640"); + values ("0.0428,0.0445,0.0538,0.0658,0.1181,0.1751"); + } + } +} +cell_leakage_power : 1306.5882; +} +} diff --git a/flow/platforms/ihp-sg13g2/lib/RM_IHPSG13_1P_512x32_c2_bm_bist_typ_1p20V_25C.lib b/flow/platforms/ihp-sg13g2/lib/RM_IHPSG13_1P_512x32_c2_bm_bist_typ_1p20V_25C.lib new file mode 100644 index 0000000000..e749ab275d --- /dev/null +++ b/flow/platforms/ihp-sg13g2/lib/RM_IHPSG13_1P_512x32_c2_bm_bist_typ_1p20V_25C.lib @@ -0,0 +1,1519 @@ +/* ------------------------------------------------------*/ +/**/ +/* Copyright 2023 IHP PDK Authors*/ +/**/ +/* Licensed under the Apache License, Version 2.0 (the "License");*/ +/* you may not use this file except in compliance with the License.*/ +/* You may obtain a copy of the License at*/ +/* */ +/* https://www.apache.org/licenses/LICENSE-2.0*/ +/* */ +/* Unless required by applicable law or agreed to in writing, software*/ +/* distributed under the License is distributed on an "AS IS" BASIS,*/ +/* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.*/ +/* See the License for the specific language governing permissions and*/ +/* limitations under the License.*/ +/* */ +/* Generated on Wed Apr 2 16:02:44 2025 */ +/* */ +/* ------------------------------------------------------ */ +library(RM_IHPSG13_1P_512x32_c2_bm_bist_typ_1p20V_25C) { + technology (cmos) ; + delay_model : table_lookup ; + define ("add_pg_pin_to_lib", "library", "boolean"); + add_pg_pin_to_lib : true; + voltage_map ( VDD, 1.20); + voltage_map ( VDDARRAY, 1.20); + voltage_map ( VSS, 0.000000 ); + + date : "Wed Apr 2 16:02:42 2025" ; + comment : "IHP Microelectronics GmbH, 2023" ; + revision : 1.0.0 ; + simulation : true ; + nom_process : 1 ; + nom_temperature : 25 ; + nom_voltage : 1.20 ; + + operating_conditions("typ_1p20V_25C"){ + process : 1 ; + temperature : 25 ; + voltage : 1.20 ; + tree_type : "balanced_tree" ; + } + + default_operating_conditions : typ_1p20V_25C ; + default_max_transition : 1.0 ; + default_fanout_load : 1.0 ; + default_inout_pin_cap : 0.0 ; + default_input_pin_cap : 0.0 ; + default_output_pin_cap : 0.0 ; + default_cell_leakage_power : 0.0 ; + default_leakage_power_density : 0.0 ; + + slew_lower_threshold_pct_rise : 30 ; + slew_upper_threshold_pct_rise : 70 ; + input_threshold_pct_fall : 50 ; + output_threshold_pct_fall : 50 ; + input_threshold_pct_rise : 50 ; + output_threshold_pct_rise : 50 ; + slew_lower_threshold_pct_fall : 30 ; + slew_upper_threshold_pct_fall : 70 ; + slew_derate_from_library : 0.5; + k_volt_cell_leakage_power : 0.0 ; + k_temp_cell_leakage_power : 0.0 ; + k_process_cell_leakage_power : 0.0 ; + k_volt_internal_power : 0.0 ; + k_temp_internal_power : 0.0 ; + k_process_internal_power : 0.0 ; + + capacitive_load_unit (1,pf) ; + voltage_unit : "1V" ; + current_unit : "1uA" ; + time_unit : "1ns" ; + leakage_power_unit : "1nW" ; + pulling_resistance_unit : "1kohm"; + /* + ------------------------------------------------------------------------------------------ + implicit units overview: + cell_area unit : "um" + internal_power unit : "1e-12 * J/toggle = 1 * uW/MHz" + (capacitive_load_unit * voltage_unit^2) per toggle event + ------------------------------------------------------------------------------------------ + */ + library_features(report_delay_calculation); + define_cell_area (pad_drivers,pad_driver_sites) ; + + lu_table_template(CLKTRAN_constraint_template) { + variable_1 : constrained_pin_transition; + index_1 ( "0.010, 0.050, 0.200, 0.400, 1.000" ); + } + lu_table_template(SRAM_load_template) { + variable_1 : total_output_net_capacitance; + index_1 ( "0.0008,0.0014,0.0051,0.0100,0.0339,0.0640" ); + } + lu_table_template(SIG2SRAM_constraint_template) { + variable_1 : related_pin_transition; + variable_2 : constrained_pin_transition; + index_1 ( "0.0056,0.0232,0.0400,0.0728,0.1280,0.2440,0.4760" ); + index_2 ( "0.0056,0.0232,0.0400,0.0728,0.1280,0.2440,0.4760" ); + } + + lu_table_template(SIG2SRAM_delay_template) { + variable_1 : input_net_transition; + variable_2 : total_output_net_capacitance; + index_1 ( "0.0056,0.0232,0.0400,0.0728,0.1280,0.2440,0.4760" ); + index_2 ( "0.0008,0.0014,0.0051,0.0100,0.0339,0.0640" ); + } + + type (D_31_0) { + base_type : array; + data_type : bit; + bit_width : 32; + bit_from : 31; + bit_to : 0; + downto : true; + } + + type (A_8_0) { + base_type : array; + data_type : bit; + bit_width : 9; + bit_from : 8; + bit_to : 0; + downto : true; + } + +cell(RM_IHPSG13_1P_512x32_c2_bm_bist) { +pg_pin (VDD) { + pg_type : primary_power; + voltage_name : VDD; +} +pg_pin (VDDARRAY) { + pg_type : primary_power; + voltage_name : VDDARRAY; +} +pg_pin (VSS) { + pg_type : primary_ground; + voltage_name : VSS; +} + +memory() { + type : ram; + address_width : 9; + word_width : 32; +} + +interface_timing : false; +bus_naming_style : "%s[%d]" ; +area : 79719.8976 ; + + pin(A_DLY) { + direction : input ; + capacitance : 0.00401111 ; + max_transition : "1" ; + related_power_pin : VDD; + related_ground_pin : VSS; + internal_power() { + rise_power("scalar") { + values (0); + } + fall_power("scalar") { + values (0); + } + } + } + +bus(A_ADDR) { + bus_type : A_8_0; + direction : input ; + capacitance : 0.00721489 ; + pin(A_ADDR[0]) { + capacitance : 0.00593979 ; + } + pin(A_ADDR[1]) { + capacitance : 0.00483009 ; + } + pin(A_ADDR[2]) { + capacitance : 0.006215 ; + } + pin(A_ADDR[3]) { + capacitance : 0.00766726 ; + } + pin(A_ADDR[4]) { + capacitance : 0.00488951 ; + } + pin(A_ADDR[5]) { + capacitance : 0.0091523 ; + } + pin(A_ADDR[6]) { + capacitance : 0.0109212 ; + } + pin(A_ADDR[7]) { + capacitance : 0.00774122 ; + } + max_transition : "0.476" ; + pin(A_ADDR[8:0]) { + related_power_pin : VDD; + related_ground_pin : VSS; + internal_power() { + when : "A_MEN"; + rise_power("scalar"){ + values (0.0106); + } + fall_power("scalar"){ + values (0.0054); + } + } + internal_power() { + when : "!A_MEN"; + rise_power("scalar"){ + values (0.0143); + } + fall_power("scalar"){ + values (0.0003); + } + } + } + timing() { + timing_type : setup_rising; + related_pin : "A_CLK"; + when : "((A_WEN | A_REN)& A_MEN)" + sdf_cond : "A_RW_ACCESS" + + rise_constraint("SIG2SRAM_constraint_template") { + index_1("0.0056,0.0232,0.0400,0.0728,0.1280,0.2440,0.4760"); + index_2("0.0056,0.0232,0.0400,0.0728,0.1280,0.2440,0.4760"); + values ("-0.4168,-0.3973,-0.3855,-0.3543,-0.3074,-0.2020,-0.0027",\ +"-0.4324,-0.4129,-0.4012,-0.3699,-0.3191,-0.2176,-0.0184",\ +"-0.4441,-0.4285,-0.4129,-0.3816,-0.3309,-0.2293,-0.0301",\ +"-0.4793,-0.4598,-0.4441,-0.4129,-0.3660,-0.2645,-0.0652",\ +"-0.5223,-0.5066,-0.4910,-0.4598,-0.4129,-0.3074,-0.1121",\ +"-0.6199,-0.6082,-0.5926,-0.5613,-0.5145,-0.4129,-0.2137",\ +"-0.8191,-0.8074,-0.7840,-0.7566,-0.7098,-0.6082,-0.4051"); + } + + fall_constraint("SIG2SRAM_constraint_template") { + index_1("0.0056,0.0232,0.0400,0.0728,0.1280,0.2440,0.4760"); + index_2("0.0056,0.0232,0.0400,0.0728,0.1280,0.2440,0.4760"); + values ("-0.3309,-0.3113,-0.2996,-0.2684,-0.2176,-0.1238,0.0637",\ +"-0.3465,-0.3309,-0.3152,-0.2840,-0.2332,-0.1395,0.0480",\ +"-0.3582,-0.3426,-0.3270,-0.2996,-0.2488,-0.1512,0.0324",\ +"-0.3895,-0.3738,-0.3582,-0.3309,-0.2801,-0.1863,0.0051",\ +"-0.4363,-0.4207,-0.4051,-0.3777,-0.3230,-0.2293,-0.0379",\ +"-0.5379,-0.5223,-0.5066,-0.4793,-0.4285,-0.3309,-0.1434",\ +"-0.7332,-0.7176,-0.7020,-0.6746,-0.6238,-0.5262,-0.3387"); + } + } + + + timing() { + timing_type : hold_rising; + related_pin : "A_CLK"; + when : "((A_WEN | A_REN)& A_MEN)" + sdf_cond : "A_RW_ACCESS" + + rise_constraint("SIG2SRAM_constraint_template") { + index_1("0.0056,0.0232,0.0400,0.0728,0.1280,0.2440,0.4760"); + index_2("0.0056,0.0232,0.0400,0.0728,0.1280,0.2440,0.4760"); + values ("0.5246,0.5051,0.4895,0.4582,0.4113,0.3059,0.1066",\ +"0.5402,0.5207,0.5051,0.4777,0.4270,0.3215,0.1223",\ +"0.5520,0.5324,0.5168,0.4895,0.4387,0.3371,0.1340",\ +"0.5832,0.5676,0.5520,0.5207,0.4738,0.3684,0.1691",\ +"0.6301,0.6105,0.5949,0.5676,0.5168,0.4113,0.2160",\ +"0.7316,0.7121,0.7004,0.6691,0.6223,0.5168,0.3176",\ +"0.9270,0.9230,0.8957,0.8645,0.8137,0.7121,0.5168"); + } + + fall_constraint("SIG2SRAM_constraint_template") { + index_1("0.0056,0.0232,0.0400,0.0728,0.1280,0.2440,0.4760"); + index_2("0.0056,0.0232,0.0400,0.0728,0.1280,0.2440,0.4760"); + values ("0.4309,0.4152,0.4035,0.3684,0.3215,0.2277,0.0363",\ +"0.4465,0.4309,0.4152,0.3879,0.3371,0.2395,0.0559",\ +"0.4582,0.4426,0.4309,0.3996,0.3488,0.2551,0.0715",\ +"0.4934,0.4777,0.4621,0.4348,0.3840,0.2863,0.0988",\ +"0.5363,0.5207,0.5051,0.4777,0.4270,0.3332,0.1418",\ +"0.6379,0.6262,0.6105,0.5793,0.5324,0.4348,0.2434",\ +"0.8332,0.8215,0.8059,0.7707,0.7238,0.6301,0.4387"); + } + } +} +pin(A_WEN) { + direction : input ; + capacitance : 0.00324098 ; + max_transition : "0.476" ; + related_power_pin : VDD; + related_ground_pin : VSS; + internal_power() { + when : "A_MEN"; + rise_power("scalar"){ + values (0.0046); + } + fall_power("scalar"){ + values (0.0040); + } + } + internal_power() { + when : "!A_MEN"; + rise_power("scalar"){ + values (0.0044); + } + fall_power("scalar"){ + values (0.0043); + } + } + timing() { + timing_type : setup_rising; + related_pin : "A_CLK"; + when : "A_MEN" + sdf_cond : "A_MEN" + + rise_constraint("SIG2SRAM_constraint_template") { + index_1("0.0056,0.0232,0.0400,0.0728,0.1280,0.2440,0.4760"); + index_2("0.0056,0.0232,0.0400,0.0728,0.1280,0.2440,0.4760"); + values ("0.2043,0.2199,0.2316,0.2629,0.3059,0.4113,0.6066",\ +"0.1887,0.2043,0.2160,0.2473,0.2941,0.3957,0.5949",\ +"0.1691,0.1848,0.2004,0.2316,0.2785,0.3801,0.5754",\ +"0.1379,0.1574,0.1691,0.2004,0.2473,0.3527,0.5480",\ +"0.0910,0.1066,0.1223,0.1535,0.2004,0.2980,0.4973",\ +"-0.0105,0.0051,0.0207,0.0520,0.0949,0.2004,0.3957",\ +"-0.2059,-0.1902,-0.1746,-0.1473,-0.1004,0.0051,0.2004"); + } + + fall_constraint("SIG2SRAM_constraint_template") { + index_1("0.0056,0.0232,0.0400,0.0728,0.1280,0.2440,0.4760"); + index_2("0.0056,0.0232,0.0400,0.0728,0.1280,0.2440,0.4760"); + values ("0.2941,0.3098,0.3215,0.3488,0.4035,0.4973,0.6887",\ +"0.2785,0.2941,0.3059,0.3332,0.3840,0.4816,0.6691",\ +"0.2629,0.2785,0.2902,0.3176,0.3684,0.4660,0.6535",\ +"0.2316,0.2473,0.2590,0.2863,0.3410,0.4348,0.6262",\ +"0.1848,0.2004,0.2121,0.2395,0.2902,0.3879,0.5754",\ +"0.0832,0.0988,0.1105,0.1379,0.1809,0.2746,0.4699",\ +"-0.1121,-0.0965,-0.0848,-0.0535,-0.0066,0.0910,0.2824"); + } + } + + + timing() { + timing_type : hold_rising; + related_pin : "A_CLK"; + when : "A_MEN" + sdf_cond : "A_MEN" + + rise_constraint("SIG2SRAM_constraint_template") { + index_1("0.0056,0.0232,0.0400,0.0728,0.1280,0.2440,0.4760"); + index_2("0.0056,0.0232,0.0400,0.0728,0.1280,0.2440,0.4760"); + values ("0.2473,0.2316,0.2160,0.1887,0.1379,0.0363,-0.1629",\ +"0.2629,0.2473,0.2316,0.2043,0.1535,0.0520,-0.1473",\ +"0.2785,0.2590,0.2434,0.2160,0.1652,0.0676,-0.1355",\ +"0.3098,0.2941,0.2785,0.2473,0.1965,0.0910,-0.1043",\ +"0.3527,0.3371,0.3215,0.2941,0.2434,0.1418,-0.0574",\ +"0.4582,0.4426,0.4270,0.3957,0.3488,0.2434,0.0480",\ +"0.6535,0.6379,0.6184,0.5910,0.5402,0.4426,0.2434"); + } + + fall_constraint("SIG2SRAM_constraint_template") { + index_1("0.0056,0.0232,0.0400,0.0728,0.1280,0.2440,0.4760"); + index_2("0.0056,0.0232,0.0400,0.0728,0.1280,0.2440,0.4760"); + values ("0.2395,0.2238,0.2121,0.1809,0.1301,0.0324,-0.1551",\ +"0.2551,0.2395,0.2277,0.1965,0.1457,0.0480,-0.1395",\ +"0.2668,0.2551,0.2395,0.2082,0.1574,0.0637,-0.1277",\ +"0.3020,0.2863,0.2707,0.2395,0.1887,0.0910,-0.0965",\ +"0.3449,0.3293,0.3176,0.2863,0.2355,0.1379,-0.0496",\ +"0.4504,0.4348,0.4191,0.3879,0.3371,0.2395,0.0559",\ +"0.6457,0.6301,0.6145,0.5871,0.5324,0.4309,0.2512"); + } + } + } +pin(A_REN) { + direction : input ; + capacitance : 0.00381634 ; + max_transition : "0.476" ; + related_power_pin : VDD; + related_ground_pin : VSS; + internal_power() { + when : "A_MEN"; + rise_power("scalar"){ + values (0.0061); + } + fall_power("scalar"){ + values (0.0022); + } + } + internal_power() { + when : "!A_MEN"; + rise_power("scalar"){ + values (0.0063); + } + fall_power("scalar"){ + values (0.0027); + } + } + timing() { + timing_type : setup_rising; + related_pin : "A_CLK"; + when : "A_MEN" + sdf_cond : "A_MEN" + + rise_constraint("SIG2SRAM_constraint_template") { + index_1("0.0056,0.0232,0.0400,0.0728,0.1280,0.2440,0.4760"); + index_2("0.0056,0.0232,0.0400,0.0728,0.1280,0.2440,0.4760"); + values ("-0.0301,-0.0145,0.0012,0.0324,0.0793,0.1809,0.3762",\ +"-0.0457,-0.0301,-0.0145,0.0168,0.0637,0.1613,0.3605",\ +"-0.0574,-0.0418,-0.0262,0.0051,0.0520,0.1496,0.3449",\ +"-0.0926,-0.0730,-0.0574,-0.0262,0.0207,0.1184,0.3137",\ +"-0.1395,-0.1238,-0.1082,-0.0770,-0.0301,0.0715,0.2707",\ +"-0.2410,-0.2254,-0.2098,-0.1746,-0.1355,-0.0340,0.1652",\ +"-0.4402,-0.4207,-0.4051,-0.3738,-0.3270,-0.2293,-0.0340"); + } + + fall_constraint("SIG2SRAM_constraint_template") { + index_1("0.0056,0.0232,0.0400,0.0728,0.1280,0.2440,0.4760"); + index_2("0.0056,0.0232,0.0400,0.0728,0.1280,0.2440,0.4760"); + values ("0.0988,0.1145,0.1262,0.1535,0.2043,0.3020,0.4855",\ +"0.0832,0.0988,0.1105,0.1418,0.1848,0.2824,0.4738",\ +"0.0676,0.0832,0.0949,0.1262,0.1730,0.2668,0.4621",\ +"0.0402,0.0559,0.0676,0.0988,0.1457,0.2434,0.4191",\ +"-0.0105,0.0012,0.0168,0.0480,0.0988,0.1965,0.3840",\ +"-0.1160,-0.0965,-0.0848,-0.0535,-0.0066,0.0988,0.2824",\ +"-0.3113,-0.2957,-0.2801,-0.2527,-0.2059,-0.1043,0.0832"); + } + } + + + timing() { + timing_type : hold_rising; + related_pin : "A_CLK"; + when : "A_MEN" + sdf_cond : "A_MEN" + + rise_constraint("SIG2SRAM_constraint_template") { + index_1("0.0056,0.0232,0.0400,0.0728,0.1280,0.2440,0.4760"); + index_2("0.0056,0.0232,0.0400,0.0728,0.1280,0.2440,0.4760"); + values ("0.2707,0.2551,0.2395,0.2121,0.1613,0.0598,-0.1395",\ +"0.2863,0.2707,0.2551,0.2238,0.1730,0.0715,-0.1238",\ +"0.2980,0.2824,0.2668,0.2395,0.1887,0.0871,-0.1121",\ +"0.3332,0.3176,0.3020,0.2707,0.2199,0.1184,-0.0809",\ +"0.3762,0.3605,0.3449,0.3176,0.2668,0.1613,-0.0340",\ +"0.4816,0.4621,0.4504,0.4191,0.3723,0.2629,0.0715",\ +"0.6770,0.6613,0.6418,0.6184,0.5637,0.4699,0.2629"); + } + + fall_constraint("SIG2SRAM_constraint_template") { + index_1("0.0056,0.0232,0.0400,0.0728,0.1280,0.2440,0.4760"); + index_2("0.0056,0.0232,0.0400,0.0728,0.1280,0.2440,0.4760"); + values ("0.2590,0.2434,0.2316,0.2004,0.1457,0.0520,-0.1355",\ +"0.2746,0.2590,0.2434,0.2160,0.1613,0.0676,-0.1199",\ +"0.2863,0.2707,0.2590,0.2277,0.1730,0.0832,-0.1082",\ +"0.3215,0.3059,0.2902,0.2590,0.2082,0.1105,-0.0770",\ +"0.3645,0.3488,0.3332,0.3059,0.2551,0.1535,-0.0340",\ +"0.4699,0.4543,0.4387,0.4074,0.3605,0.2551,0.0715",\ +"0.6652,0.6496,0.6340,0.6027,0.5520,0.4621,0.2707"); + } + } + } +pin(A_MEN) { + direction : input ; + capacitance : 0.00309605 ; + max_transition : "0.476" ; + related_power_pin : VDD; + related_ground_pin : VSS; + internal_power() { + rise_power("scalar"){ + values (0.0874); + } + fall_power("scalar"){ + values (0.0053); + } + } + timing() { + timing_type : setup_rising; + related_pin : "A_CLK"; + + rise_constraint("SIG2SRAM_constraint_template") { + index_1("0.0056,0.0232,0.0400,0.0728,0.1280,0.2440,0.4760"); + index_2("0.0056,0.0232,0.0400,0.0728,0.1280,0.2440,0.4760"); + values ("0.2043,0.2199,0.2316,0.2668,0.3098,0.4152,0.6066",\ +"0.1887,0.2043,0.2199,0.2512,0.2941,0.3996,0.5949",\ +"0.1730,0.1887,0.2043,0.2355,0.2824,0.3840,0.5793",\ +"0.1418,0.1574,0.1730,0.2043,0.2512,0.3566,0.5480",\ +"0.0949,0.1105,0.1262,0.1574,0.2043,0.3020,0.5051",\ +"-0.0066,0.0090,0.0246,0.0520,0.0988,0.2043,0.3996",\ +"-0.2020,-0.1863,-0.1746,-0.1434,-0.0965,0.0090,0.2082"); + } + + fall_constraint("SIG2SRAM_constraint_template") { + index_1("0.0056,0.0232,0.0400,0.0728,0.1280,0.2440,0.4760"); + index_2("0.0056,0.0232,0.0400,0.0728,0.1280,0.2440,0.4760"); + values ("0.2980,0.3137,0.3254,0.3527,0.4035,0.5012,0.6887",\ +"0.2824,0.2980,0.3098,0.3371,0.3879,0.4855,0.6730",\ +"0.2668,0.2824,0.2941,0.3215,0.3723,0.4699,0.6574",\ +"0.2355,0.2473,0.2629,0.2902,0.3410,0.4387,0.6262",\ +"0.1887,0.2004,0.2160,0.2395,0.2941,0.3918,0.5793",\ +"0.0871,0.1027,0.1145,0.1418,0.1848,0.2746,0.4816",\ +"-0.1082,-0.0965,-0.0809,-0.0496,-0.0027,0.0949,0.2863"); + } + } + + + timing() { + timing_type : hold_rising; + related_pin : "A_CLK"; + + rise_constraint("SIG2SRAM_constraint_template") { + index_1("0.0056,0.0232,0.0400,0.0728,0.1280,0.2440,0.4760"); + index_2("0.0056,0.0232,0.0400,0.0728,0.1280,0.2440,0.4760"); + values ("0.2512,0.2355,0.2199,0.1926,0.1418,0.0402,-0.1590",\ +"0.2668,0.2512,0.2355,0.2082,0.1574,0.0559,-0.1434",\ +"0.2824,0.2629,0.2512,0.2199,0.1691,0.0715,-0.1316",\ +"0.3137,0.2980,0.2824,0.2512,0.2004,0.0988,-0.0965",\ +"0.3566,0.3410,0.3254,0.2980,0.2473,0.1418,-0.0535",\ +"0.4621,0.4426,0.4309,0.3996,0.3527,0.2473,0.0520",\ +"0.6574,0.6418,0.6262,0.5949,0.5441,0.4465,0.2473"); + } + + fall_constraint("SIG2SRAM_constraint_template") { + index_1("0.0056,0.0232,0.0400,0.0728,0.1280,0.2440,0.4760"); + index_2("0.0056,0.0232,0.0400,0.0728,0.1280,0.2440,0.4760"); + values ("0.2395,0.2238,0.2121,0.1809,0.1301,0.0324,-0.1551",\ +"0.2551,0.2434,0.2277,0.1965,0.1457,0.0480,-0.1395",\ +"0.2707,0.2551,0.2395,0.2082,0.1574,0.0637,-0.1277",\ +"0.3020,0.2863,0.2707,0.2434,0.1926,0.0910,-0.0965",\ +"0.3449,0.3332,0.3176,0.2863,0.2355,0.1379,-0.0496",\ +"0.4504,0.4348,0.4230,0.3918,0.3410,0.2434,0.0559",\ +"0.6457,0.6301,0.6145,0.5910,0.5324,0.4387,0.2512"); + } + } + } +bus(A_BM) { + bus_type : D_31_0; + direction : input ; + capacitance : 0.00285703 ; + max_transition : "0.476" ; + pin(A_BM[31:0]) { + related_power_pin : VDD; + related_ground_pin : VSS; + internal_power() { + when : "A_MEN"; + rise_power("scalar"){ + values (0.1133); + } + fall_power("scalar"){ + values (0.0512); + } + } + internal_power() { + when : "!A_MEN"; + rise_power("scalar"){ + values (0.1175); + } + fall_power("scalar"){ + values (0.0489); + } + } + } + timing() { + timing_type : setup_rising; + related_pin : "A_CLK"; + when : "(A_WEN & A_MEN)" + sdf_cond : "A_RW_ACCESS" + + rise_constraint("SIG2SRAM_constraint_template") { + index_1("0.0056,0.0232,0.0400,0.0728,0.1280,0.2440,0.4760"); + index_2("0.0056,0.0232,0.0400,0.0728,0.1280,0.2440,0.4760"); + values ("-0.4429,-0.4264,-0.4136,-0.3814,-0.3345,-0.2301,-0.0377",\ +"-0.4479,-0.4313,-0.4186,-0.3864,-0.3395,-0.2351,-0.0427",\ +"-0.4524,-0.4358,-0.4231,-0.3909,-0.3440,-0.2395,-0.0472",\ +"-0.4615,-0.4449,-0.4322,-0.4000,-0.3531,-0.2486,-0.0562",\ +"-0.4688,-0.4522,-0.4395,-0.4073,-0.3604,-0.2559,-0.0635",\ +"-0.4989,-0.4823,-0.4696,-0.4373,-0.3905,-0.2860,-0.0936",\ +"-0.5565,-0.5399,-0.5272,-0.4950,-0.4481,-0.3436,-0.1512"); + } + + fall_constraint("SIG2SRAM_constraint_template") { + index_1("0.0056,0.0232,0.0400,0.0728,0.1280,0.2440,0.4760"); + index_2("0.0056,0.0232,0.0400,0.0728,0.1280,0.2440,0.4760"); + values ("-0.4107,-0.3951,-0.3824,-0.3541,-0.3033,-0.2047,-0.0260",\ +"-0.4157,-0.4001,-0.3874,-0.3591,-0.3083,-0.2097,-0.0310",\ +"-0.4202,-0.4046,-0.3919,-0.3636,-0.3128,-0.2141,-0.0354",\ +"-0.4293,-0.4137,-0.4010,-0.3727,-0.3219,-0.2232,-0.0445",\ +"-0.4366,-0.4209,-0.4082,-0.3799,-0.3291,-0.2305,-0.0518",\ +"-0.4667,-0.4510,-0.4383,-0.4100,-0.3592,-0.2606,-0.0819",\ +"-0.5242,-0.5086,-0.4959,-0.4676,-0.4168,-0.3182,-0.1395"); + } + } + + + timing() { + timing_type : hold_rising; + related_pin : "A_CLK"; + when : "(A_WEN & A_MEN)" + sdf_cond : "A_RW_ACCESS" + + rise_constraint("SIG2SRAM_constraint_template") { + index_1("0.0056,0.0232,0.0400,0.0728,0.1280,0.2440,0.4760"); + index_2("0.0056,0.0232,0.0400,0.0728,0.1280,0.2440,0.4760"); + values ("0.5520,0.5364,0.5237,0.4915,0.4427,0.3440,0.1477",\ +"0.5570,0.5414,0.5287,0.4965,0.4477,0.3490,0.1527",\ +"0.5615,0.5459,0.5332,0.5010,0.4521,0.3535,0.1572",\ +"0.5706,0.5550,0.5423,0.5101,0.4612,0.3626,0.1663",\ +"0.5779,0.5623,0.5496,0.5173,0.4685,0.3699,0.1736",\ +"0.6080,0.5923,0.5796,0.5474,0.4986,0.4000,0.2037",\ +"0.6656,0.6499,0.6372,0.6050,0.5562,0.4576,0.2613"); + } + + fall_constraint("SIG2SRAM_constraint_template") { + index_1("0.0056,0.0232,0.0400,0.0728,0.1280,0.2440,0.4760"); + index_2("0.0056,0.0232,0.0400,0.0728,0.1280,0.2440,0.4760"); + values ("0.5120,0.4973,0.4837,0.4554,0.4046,0.3118,0.1233",\ +"0.5170,0.5023,0.4887,0.4604,0.4096,0.3168,0.1283",\ +"0.5215,0.5068,0.4932,0.4648,0.4141,0.3213,0.1328",\ +"0.5306,0.5159,0.5022,0.4739,0.4231,0.3304,0.1419",\ +"0.5378,0.5232,0.5095,0.4812,0.4304,0.3376,0.1492",\ +"0.5679,0.5533,0.5396,0.5113,0.4605,0.3677,0.1792",\ +"0.6255,0.6109,0.5972,0.5689,0.5181,0.4253,0.2368"); + } + } +} + pin(A_CLK) { + direction : input; + capacitance : 0.00380014; + max_transition : "0.476"; + clock : "true" ; + pin_func_type : active_rising ; + + timing () { + timing_type : "min_pulse_width"; + related_pin : "A_CLK"; + rise_constraint("CLKTRAN_constraint_template") { + index_1("0.0056,0.476"); + values("0.21,0.21"); + } + } + + related_power_pin : VDD; + related_ground_pin : VSS; + + internal_power() { + when : "!A_MEN & !A_WEN & !A_REN"; + rise_power("scalar"){ + values (0); + } + fall_power("scalar"){ + values (0); + } + } + internal_power() { + when : "!A_MEN & A_WEN & !A_REN"; + rise_power("scalar"){ + values (0.5389); + } + fall_power("scalar"){ + values (0); + } + } + internal_power() { + when : "A_MEN & A_WEN & !A_REN"; + rise_power("scalar"){ + values (42.3165); + } + fall_power("scalar"){ + values (0); + } + } + internal_power() { + when : "A_MEN & A_WEN & A_REN"; + rise_power("scalar"){ + values (47.6101); + } + fall_power("scalar"){ + values (0); + } + } + internal_power() { + when : "A_MEN & !A_WEN & A_REN"; + rise_power("scalar"){ + values (36.0099); + } + fall_power("scalar"){ + values (0); + } + } + internal_power() { + when : "!A_MEN & !A_WEN & A_REN"; + rise_power("scalar"){ + values (0.3230); + } + fall_power("scalar"){ + values (0); + } + } + internal_power() { + when : "!A_MEN & A_WEN & A_REN"; + rise_power("scalar"){ + values (1.2182); + } + fall_power("scalar"){ + values (0); + } + } + internal_power() { + when : "A_MEN & !A_WEN & !A_REN"; + rise_power("scalar"){ + values (0); + } + fall_power("scalar"){ + values (0); + } + } + } + bus(A_DIN) { + bus_type : D_31_0; + direction : input ; + capacitance : 0.00365723 ; + memory_write() { + address : A_ADDR ; + clocked_on : A_CLK; + } + + max_transition : "0.476" ; + pin(A_DIN[31:0]) { + related_power_pin : VDD; + related_ground_pin : VSS; + internal_power() { + when : "A_MEN"; + rise_power("scalar"){ + values (0.1133); + } + fall_power("scalar"){ + values (0.0512); + } + } + internal_power() { + when : "!A_MEN"; + rise_power("scalar"){ + values (0.1175); + } + fall_power("scalar"){ + values (0.0489); + } + } + } + timing() { + timing_type : setup_rising; + related_pin : "A_CLK"; + when : "(A_WEN & A_MEN)"; + sdf_cond : "A_W_ACCESS"; + + rise_constraint("SIG2SRAM_constraint_template") { + index_1("0.0056,0.0232,0.0400,0.0728,0.1280,0.2440,0.4760"); + index_2("0.0056,0.0232,0.0400,0.0728,0.1280,0.2440,0.4760"); + values ("-0.4429,-0.4264,-0.4136,-0.3814,-0.3345,-0.2301,-0.0377",\ +"-0.4479,-0.4313,-0.4186,-0.3864,-0.3395,-0.2351,-0.0427",\ +"-0.4524,-0.4358,-0.4231,-0.3909,-0.3440,-0.2395,-0.0472",\ +"-0.4615,-0.4449,-0.4322,-0.4000,-0.3531,-0.2486,-0.0562",\ +"-0.4688,-0.4522,-0.4395,-0.4073,-0.3604,-0.2559,-0.0635",\ +"-0.4989,-0.4823,-0.4696,-0.4373,-0.3905,-0.2860,-0.0936",\ +"-0.5565,-0.5399,-0.5272,-0.4950,-0.4481,-0.3436,-0.1512"); + } + + fall_constraint("SIG2SRAM_constraint_template") { + index_1("0.0056,0.0232,0.0400,0.0728,0.1280,0.2440,0.4760"); + index_2("0.0056,0.0232,0.0400,0.0728,0.1280,0.2440,0.4760"); + values ("-0.4107,-0.3951,-0.3824,-0.3541,-0.3033,-0.2047,-0.0260",\ +"-0.4157,-0.4001,-0.3874,-0.3591,-0.3083,-0.2097,-0.0310",\ +"-0.4202,-0.4046,-0.3919,-0.3636,-0.3128,-0.2141,-0.0354",\ +"-0.4293,-0.4137,-0.4010,-0.3727,-0.3219,-0.2232,-0.0445",\ +"-0.4366,-0.4209,-0.4082,-0.3799,-0.3291,-0.2305,-0.0518",\ +"-0.4667,-0.4510,-0.4383,-0.4100,-0.3592,-0.2606,-0.0819",\ +"-0.5242,-0.5086,-0.4959,-0.4676,-0.4168,-0.3182,-0.1395"); + } + } + + timing() { + timing_type : hold_rising; + related_pin : "A_CLK"; + when : "(A_WEN & A_MEN)"; + sdf_cond : "A_W_ACCESS"; + + rise_constraint("SIG2SRAM_constraint_template") { + index_1("0.0056,0.0232,0.0400,0.0728,0.1280,0.2440,0.4760"); + index_2("0.0056,0.0232,0.0400,0.0728,0.1280,0.2440,0.4760"); + values ("0.5520,0.5364,0.5237,0.4915,0.4427,0.3440,0.1477",\ +"0.5570,0.5414,0.5287,0.4965,0.4477,0.3490,0.1527",\ +"0.5615,0.5459,0.5332,0.5010,0.4521,0.3535,0.1572",\ +"0.5706,0.5550,0.5423,0.5101,0.4612,0.3626,0.1663",\ +"0.5779,0.5623,0.5496,0.5173,0.4685,0.3699,0.1736",\ +"0.6080,0.5923,0.5796,0.5474,0.4986,0.4000,0.2037",\ +"0.6656,0.6499,0.6372,0.6050,0.5562,0.4576,0.2613"); + } + + fall_constraint("SIG2SRAM_constraint_template") { + index_1("0.0056,0.0232,0.0400,0.0728,0.1280,0.2440,0.4760"); + index_2("0.0056,0.0232,0.0400,0.0728,0.1280,0.2440,0.4760"); + values ("0.5120,0.4973,0.4837,0.4554,0.4046,0.3118,0.1233",\ +"0.5170,0.5023,0.4887,0.4604,0.4096,0.3168,0.1283",\ +"0.5215,0.5068,0.4932,0.4648,0.4141,0.3213,0.1328",\ +"0.5306,0.5159,0.5022,0.4739,0.4231,0.3304,0.1419",\ +"0.5378,0.5232,0.5095,0.4812,0.4304,0.3376,0.1492",\ +"0.5679,0.5533,0.5396,0.5113,0.4605,0.3677,0.1792",\ +"0.6255,0.6109,0.5972,0.5689,0.5181,0.4253,0.2368"); + } + } + } + + pin(A_BIST_EN) { + direction : input ; + capacitance : 0.00401111 ; + max_transition : "1" ; + related_power_pin : VDD; + related_ground_pin : VSS; + internal_power() { + rise_power("scalar") { + values (0); + } + fall_power("scalar") { + values (0); + } + } + } + +bus(A_BIST_ADDR) { + bus_type : A_8_0; + direction : input ; + capacitance : 0.00721489 ; + pin(A_BIST_ADDR[0]) { + capacitance : 0.00593979 ; + } + pin(A_BIST_ADDR[1]) { + capacitance : 0.00483009 ; + } + pin(A_BIST_ADDR[2]) { + capacitance : 0.006215 ; + } + pin(A_BIST_ADDR[3]) { + capacitance : 0.00766726 ; + } + pin(A_BIST_ADDR[4]) { + capacitance : 0.00488951 ; + } + pin(A_BIST_ADDR[5]) { + capacitance : 0.0091523 ; + } + pin(A_BIST_ADDR[6]) { + capacitance : 0.0109212 ; + } + pin(A_BIST_ADDR[7]) { + capacitance : 0.00774122 ; + } + max_transition : "0.476" ; + pin(A_BIST_ADDR[8:0]) { + related_power_pin : VDD; + related_ground_pin : VSS; + internal_power() { + when : "A_BIST_MEN"; + rise_power("scalar"){ + values (0.0106); + } + fall_power("scalar"){ + values (0.0054); + } + } + internal_power() { + when : "!A_BIST_MEN"; + rise_power("scalar"){ + values (0.0143); + } + fall_power("scalar"){ + values (0.0003); + } + } + } + timing() { + timing_type : setup_rising; + related_pin : "A_BIST_CLK"; + when : "((A_BIST_WEN | A_BIST_REN)& A_BIST_MEN)" + sdf_cond : "A_BIST_RW_ACCESS" + + rise_constraint("SIG2SRAM_constraint_template") { + index_1("0.0056,0.0232,0.0400,0.0728,0.1280,0.2440,0.4760"); + index_2("0.0056,0.0232,0.0400,0.0728,0.1280,0.2440,0.4760"); + values ("-0.4168,-0.3973,-0.3855,-0.3543,-0.3074,-0.2020,-0.0027",\ +"-0.4324,-0.4129,-0.4012,-0.3699,-0.3191,-0.2176,-0.0184",\ +"-0.4441,-0.4285,-0.4129,-0.3816,-0.3309,-0.2293,-0.0301",\ +"-0.4793,-0.4598,-0.4441,-0.4129,-0.3660,-0.2645,-0.0652",\ +"-0.5223,-0.5066,-0.4910,-0.4598,-0.4129,-0.3074,-0.1121",\ +"-0.6199,-0.6082,-0.5926,-0.5613,-0.5145,-0.4129,-0.2137",\ +"-0.8191,-0.8074,-0.7840,-0.7566,-0.7098,-0.6082,-0.4051"); + } + + fall_constraint("SIG2SRAM_constraint_template") { + index_1("0.0056,0.0232,0.0400,0.0728,0.1280,0.2440,0.4760"); + index_2("0.0056,0.0232,0.0400,0.0728,0.1280,0.2440,0.4760"); + values ("-0.3309,-0.3113,-0.2996,-0.2684,-0.2176,-0.1238,0.0637",\ +"-0.3465,-0.3309,-0.3152,-0.2840,-0.2332,-0.1395,0.0480",\ +"-0.3582,-0.3426,-0.3270,-0.2996,-0.2488,-0.1512,0.0324",\ +"-0.3895,-0.3738,-0.3582,-0.3309,-0.2801,-0.1863,0.0051",\ +"-0.4363,-0.4207,-0.4051,-0.3777,-0.3230,-0.2293,-0.0379",\ +"-0.5379,-0.5223,-0.5066,-0.4793,-0.4285,-0.3309,-0.1434",\ +"-0.7332,-0.7176,-0.7020,-0.6746,-0.6238,-0.5262,-0.3387"); + } + } + + + timing() { + timing_type : hold_rising; + related_pin : "A_BIST_CLK"; + when : "((A_BIST_WEN | A_BIST_REN)& A_BIST_MEN)" + sdf_cond : "A_BIST_RW_ACCESS" + + rise_constraint("SIG2SRAM_constraint_template") { + index_1("0.0056,0.0232,0.0400,0.0728,0.1280,0.2440,0.4760"); + index_2("0.0056,0.0232,0.0400,0.0728,0.1280,0.2440,0.4760"); + values ("0.5246,0.5051,0.4895,0.4582,0.4113,0.3059,0.1066",\ +"0.5402,0.5207,0.5051,0.4777,0.4270,0.3215,0.1223",\ +"0.5520,0.5324,0.5168,0.4895,0.4387,0.3371,0.1340",\ +"0.5832,0.5676,0.5520,0.5207,0.4738,0.3684,0.1691",\ +"0.6301,0.6105,0.5949,0.5676,0.5168,0.4113,0.2160",\ +"0.7316,0.7121,0.7004,0.6691,0.6223,0.5168,0.3176",\ +"0.9270,0.9230,0.8957,0.8645,0.8137,0.7121,0.5168"); + } + + fall_constraint("SIG2SRAM_constraint_template") { + index_1("0.0056,0.0232,0.0400,0.0728,0.1280,0.2440,0.4760"); + index_2("0.0056,0.0232,0.0400,0.0728,0.1280,0.2440,0.4760"); + values ("0.4309,0.4152,0.4035,0.3684,0.3215,0.2277,0.0363",\ +"0.4465,0.4309,0.4152,0.3879,0.3371,0.2395,0.0559",\ +"0.4582,0.4426,0.4309,0.3996,0.3488,0.2551,0.0715",\ +"0.4934,0.4777,0.4621,0.4348,0.3840,0.2863,0.0988",\ +"0.5363,0.5207,0.5051,0.4777,0.4270,0.3332,0.1418",\ +"0.6379,0.6262,0.6105,0.5793,0.5324,0.4348,0.2434",\ +"0.8332,0.8215,0.8059,0.7707,0.7238,0.6301,0.4387"); + } + } +} +pin(A_BIST_WEN) { + direction : input ; + capacitance : 0.00324098 ; + max_transition : "0.476" ; + related_power_pin : VDD; + related_ground_pin : VSS; + internal_power() { + when : "A_BIST_MEN"; + rise_power("scalar"){ + values (0.0046); + } + fall_power("scalar"){ + values (0.0040); + } + } + internal_power() { + when : "!A_BIST_MEN"; + rise_power("scalar"){ + values (0.0044); + } + fall_power("scalar"){ + values (0.0043); + } + } + timing() { + timing_type : setup_rising; + related_pin : "A_BIST_CLK"; + when : "A_BIST_MEN" + sdf_cond : "A_BIST_MEN" + + rise_constraint("SIG2SRAM_constraint_template") { + index_1("0.0056,0.0232,0.0400,0.0728,0.1280,0.2440,0.4760"); + index_2("0.0056,0.0232,0.0400,0.0728,0.1280,0.2440,0.4760"); + values ("0.2043,0.2199,0.2316,0.2629,0.3059,0.4113,0.6066",\ +"0.1887,0.2043,0.2160,0.2473,0.2941,0.3957,0.5949",\ +"0.1691,0.1848,0.2004,0.2316,0.2785,0.3801,0.5754",\ +"0.1379,0.1574,0.1691,0.2004,0.2473,0.3527,0.5480",\ +"0.0910,0.1066,0.1223,0.1535,0.2004,0.2980,0.4973",\ +"-0.0105,0.0051,0.0207,0.0520,0.0949,0.2004,0.3957",\ +"-0.2059,-0.1902,-0.1746,-0.1473,-0.1004,0.0051,0.2004"); + } + + fall_constraint("SIG2SRAM_constraint_template") { + index_1("0.0056,0.0232,0.0400,0.0728,0.1280,0.2440,0.4760"); + index_2("0.0056,0.0232,0.0400,0.0728,0.1280,0.2440,0.4760"); + values ("0.2941,0.3098,0.3215,0.3488,0.4035,0.4973,0.6887",\ +"0.2785,0.2941,0.3059,0.3332,0.3840,0.4816,0.6691",\ +"0.2629,0.2785,0.2902,0.3176,0.3684,0.4660,0.6535",\ +"0.2316,0.2473,0.2590,0.2863,0.3410,0.4348,0.6262",\ +"0.1848,0.2004,0.2121,0.2395,0.2902,0.3879,0.5754",\ +"0.0832,0.0988,0.1105,0.1379,0.1809,0.2746,0.4699",\ +"-0.1121,-0.0965,-0.0848,-0.0535,-0.0066,0.0910,0.2824"); + } + } + + + timing() { + timing_type : hold_rising; + related_pin : "A_BIST_CLK"; + when : "A_BIST_MEN" + sdf_cond : "A_BIST_MEN" + + rise_constraint("SIG2SRAM_constraint_template") { + index_1("0.0056,0.0232,0.0400,0.0728,0.1280,0.2440,0.4760"); + index_2("0.0056,0.0232,0.0400,0.0728,0.1280,0.2440,0.4760"); + values ("0.2473,0.2316,0.2160,0.1887,0.1379,0.0363,-0.1629",\ +"0.2629,0.2473,0.2316,0.2043,0.1535,0.0520,-0.1473",\ +"0.2785,0.2590,0.2434,0.2160,0.1652,0.0676,-0.1355",\ +"0.3098,0.2941,0.2785,0.2473,0.1965,0.0910,-0.1043",\ +"0.3527,0.3371,0.3215,0.2941,0.2434,0.1418,-0.0574",\ +"0.4582,0.4426,0.4270,0.3957,0.3488,0.2434,0.0480",\ +"0.6535,0.6379,0.6184,0.5910,0.5402,0.4426,0.2434"); + } + + fall_constraint("SIG2SRAM_constraint_template") { + index_1("0.0056,0.0232,0.0400,0.0728,0.1280,0.2440,0.4760"); + index_2("0.0056,0.0232,0.0400,0.0728,0.1280,0.2440,0.4760"); + values ("0.2395,0.2238,0.2121,0.1809,0.1301,0.0324,-0.1551",\ +"0.2551,0.2395,0.2277,0.1965,0.1457,0.0480,-0.1395",\ +"0.2668,0.2551,0.2395,0.2082,0.1574,0.0637,-0.1277",\ +"0.3020,0.2863,0.2707,0.2395,0.1887,0.0910,-0.0965",\ +"0.3449,0.3293,0.3176,0.2863,0.2355,0.1379,-0.0496",\ +"0.4504,0.4348,0.4191,0.3879,0.3371,0.2395,0.0559",\ +"0.6457,0.6301,0.6145,0.5871,0.5324,0.4309,0.2512"); + } + } + } +pin(A_BIST_REN) { + direction : input ; + capacitance : 0.00381634 ; + max_transition : "0.476" ; + related_power_pin : VDD; + related_ground_pin : VSS; + internal_power() { + when : "A_BIST_MEN"; + rise_power("scalar"){ + values (0.0061); + } + fall_power("scalar"){ + values (0.0022); + } + } + internal_power() { + when : "!A_BIST_MEN"; + rise_power("scalar"){ + values (0.0063); + } + fall_power("scalar"){ + values (0.0027); + } + } + timing() { + timing_type : setup_rising; + related_pin : "A_BIST_CLK"; + when : "A_BIST_MEN" + sdf_cond : "A_BIST_MEN" + + rise_constraint("SIG2SRAM_constraint_template") { + index_1("0.0056,0.0232,0.0400,0.0728,0.1280,0.2440,0.4760"); + index_2("0.0056,0.0232,0.0400,0.0728,0.1280,0.2440,0.4760"); + values ("-0.0301,-0.0145,0.0012,0.0324,0.0793,0.1809,0.3762",\ +"-0.0457,-0.0301,-0.0145,0.0168,0.0637,0.1613,0.3605",\ +"-0.0574,-0.0418,-0.0262,0.0051,0.0520,0.1496,0.3449",\ +"-0.0926,-0.0730,-0.0574,-0.0262,0.0207,0.1184,0.3137",\ +"-0.1395,-0.1238,-0.1082,-0.0770,-0.0301,0.0715,0.2707",\ +"-0.2410,-0.2254,-0.2098,-0.1746,-0.1355,-0.0340,0.1652",\ +"-0.4402,-0.4207,-0.4051,-0.3738,-0.3270,-0.2293,-0.0340"); + } + + fall_constraint("SIG2SRAM_constraint_template") { + index_1("0.0056,0.0232,0.0400,0.0728,0.1280,0.2440,0.4760"); + index_2("0.0056,0.0232,0.0400,0.0728,0.1280,0.2440,0.4760"); + values ("0.0988,0.1145,0.1262,0.1535,0.2043,0.3020,0.4855",\ +"0.0832,0.0988,0.1105,0.1418,0.1848,0.2824,0.4738",\ +"0.0676,0.0832,0.0949,0.1262,0.1730,0.2668,0.4621",\ +"0.0402,0.0559,0.0676,0.0988,0.1457,0.2434,0.4191",\ +"-0.0105,0.0012,0.0168,0.0480,0.0988,0.1965,0.3840",\ +"-0.1160,-0.0965,-0.0848,-0.0535,-0.0066,0.0988,0.2824",\ +"-0.3113,-0.2957,-0.2801,-0.2527,-0.2059,-0.1043,0.0832"); + } + } + + + timing() { + timing_type : hold_rising; + related_pin : "A_BIST_CLK"; + when : "A_BIST_MEN" + sdf_cond : "A_BIST_MEN" + + rise_constraint("SIG2SRAM_constraint_template") { + index_1("0.0056,0.0232,0.0400,0.0728,0.1280,0.2440,0.4760"); + index_2("0.0056,0.0232,0.0400,0.0728,0.1280,0.2440,0.4760"); + values ("0.2707,0.2551,0.2395,0.2121,0.1613,0.0598,-0.1395",\ +"0.2863,0.2707,0.2551,0.2238,0.1730,0.0715,-0.1238",\ +"0.2980,0.2824,0.2668,0.2395,0.1887,0.0871,-0.1121",\ +"0.3332,0.3176,0.3020,0.2707,0.2199,0.1184,-0.0809",\ +"0.3762,0.3605,0.3449,0.3176,0.2668,0.1613,-0.0340",\ +"0.4816,0.4621,0.4504,0.4191,0.3723,0.2629,0.0715",\ +"0.6770,0.6613,0.6418,0.6184,0.5637,0.4699,0.2629"); + } + + fall_constraint("SIG2SRAM_constraint_template") { + index_1("0.0056,0.0232,0.0400,0.0728,0.1280,0.2440,0.4760"); + index_2("0.0056,0.0232,0.0400,0.0728,0.1280,0.2440,0.4760"); + values ("0.2590,0.2434,0.2316,0.2004,0.1457,0.0520,-0.1355",\ +"0.2746,0.2590,0.2434,0.2160,0.1613,0.0676,-0.1199",\ +"0.2863,0.2707,0.2590,0.2277,0.1730,0.0832,-0.1082",\ +"0.3215,0.3059,0.2902,0.2590,0.2082,0.1105,-0.0770",\ +"0.3645,0.3488,0.3332,0.3059,0.2551,0.1535,-0.0340",\ +"0.4699,0.4543,0.4387,0.4074,0.3605,0.2551,0.0715",\ +"0.6652,0.6496,0.6340,0.6027,0.5520,0.4621,0.2707"); + } + } + } +pin(A_BIST_MEN) { + direction : input ; + capacitance : 0.00309605 ; + max_transition : "0.476" ; + related_power_pin : VDD; + related_ground_pin : VSS; + internal_power() { + rise_power("scalar"){ + values (0.0874); + } + fall_power("scalar"){ + values (0.0053); + } + } + timing() { + timing_type : setup_rising; + related_pin : "A_BIST_CLK"; + + rise_constraint("SIG2SRAM_constraint_template") { + index_1("0.0056,0.0232,0.0400,0.0728,0.1280,0.2440,0.4760"); + index_2("0.0056,0.0232,0.0400,0.0728,0.1280,0.2440,0.4760"); + values ("0.2043,0.2199,0.2316,0.2668,0.3098,0.4152,0.6066",\ +"0.1887,0.2043,0.2199,0.2512,0.2941,0.3996,0.5949",\ +"0.1730,0.1887,0.2043,0.2355,0.2824,0.3840,0.5793",\ +"0.1418,0.1574,0.1730,0.2043,0.2512,0.3566,0.5480",\ +"0.0949,0.1105,0.1262,0.1574,0.2043,0.3020,0.5051",\ +"-0.0066,0.0090,0.0246,0.0520,0.0988,0.2043,0.3996",\ +"-0.2020,-0.1863,-0.1746,-0.1434,-0.0965,0.0090,0.2082"); + } + + fall_constraint("SIG2SRAM_constraint_template") { + index_1("0.0056,0.0232,0.0400,0.0728,0.1280,0.2440,0.4760"); + index_2("0.0056,0.0232,0.0400,0.0728,0.1280,0.2440,0.4760"); + values ("0.2980,0.3137,0.3254,0.3527,0.4035,0.5012,0.6887",\ +"0.2824,0.2980,0.3098,0.3371,0.3879,0.4855,0.6730",\ +"0.2668,0.2824,0.2941,0.3215,0.3723,0.4699,0.6574",\ +"0.2355,0.2473,0.2629,0.2902,0.3410,0.4387,0.6262",\ +"0.1887,0.2004,0.2160,0.2395,0.2941,0.3918,0.5793",\ +"0.0871,0.1027,0.1145,0.1418,0.1848,0.2746,0.4816",\ +"-0.1082,-0.0965,-0.0809,-0.0496,-0.0027,0.0949,0.2863"); + } + } + + + timing() { + timing_type : hold_rising; + related_pin : "A_BIST_CLK"; + + rise_constraint("SIG2SRAM_constraint_template") { + index_1("0.0056,0.0232,0.0400,0.0728,0.1280,0.2440,0.4760"); + index_2("0.0056,0.0232,0.0400,0.0728,0.1280,0.2440,0.4760"); + values ("0.2512,0.2355,0.2199,0.1926,0.1418,0.0402,-0.1590",\ +"0.2668,0.2512,0.2355,0.2082,0.1574,0.0559,-0.1434",\ +"0.2824,0.2629,0.2512,0.2199,0.1691,0.0715,-0.1316",\ +"0.3137,0.2980,0.2824,0.2512,0.2004,0.0988,-0.0965",\ +"0.3566,0.3410,0.3254,0.2980,0.2473,0.1418,-0.0535",\ +"0.4621,0.4426,0.4309,0.3996,0.3527,0.2473,0.0520",\ +"0.6574,0.6418,0.6262,0.5949,0.5441,0.4465,0.2473"); + } + + fall_constraint("SIG2SRAM_constraint_template") { + index_1("0.0056,0.0232,0.0400,0.0728,0.1280,0.2440,0.4760"); + index_2("0.0056,0.0232,0.0400,0.0728,0.1280,0.2440,0.4760"); + values ("0.2395,0.2238,0.2121,0.1809,0.1301,0.0324,-0.1551",\ +"0.2551,0.2434,0.2277,0.1965,0.1457,0.0480,-0.1395",\ +"0.2707,0.2551,0.2395,0.2082,0.1574,0.0637,-0.1277",\ +"0.3020,0.2863,0.2707,0.2434,0.1926,0.0910,-0.0965",\ +"0.3449,0.3332,0.3176,0.2863,0.2355,0.1379,-0.0496",\ +"0.4504,0.4348,0.4230,0.3918,0.3410,0.2434,0.0559",\ +"0.6457,0.6301,0.6145,0.5910,0.5324,0.4387,0.2512"); + } + } + } +bus(A_BIST_BM) { + bus_type : D_31_0; + direction : input ; + capacitance : 0.00238379 ; + max_transition : "0.476" ; + pin(A_BIST_BM[31:0]) { + related_power_pin : VDD; + related_ground_pin : VSS; + internal_power() { + when : "A_BIST_MEN"; + rise_power("scalar"){ + values (0.1133); + } + fall_power("scalar"){ + values (0.0512); + } + } + internal_power() { + when : "!A_BIST_MEN"; + rise_power("scalar"){ + values (0.1175); + } + fall_power("scalar"){ + values (0.0489); + } + } + } + timing() { + timing_type : setup_rising; + related_pin : "A_BIST_CLK"; + when : "(A_BIST_WEN & A_BIST_MEN)" + sdf_cond : "A_BIST_RW_ACCESS" + + rise_constraint("SIG2SRAM_constraint_template") { + index_1("0.0056,0.0232,0.0400,0.0728,0.1280,0.2440,0.4760"); + index_2("0.0056,0.0232,0.0400,0.0728,0.1280,0.2440,0.4760"); + values ("-0.4429,-0.4264,-0.4136,-0.3814,-0.3345,-0.2301,-0.0377",\ +"-0.4479,-0.4313,-0.4186,-0.3864,-0.3395,-0.2351,-0.0427",\ +"-0.4524,-0.4358,-0.4231,-0.3909,-0.3440,-0.2395,-0.0472",\ +"-0.4615,-0.4449,-0.4322,-0.4000,-0.3531,-0.2486,-0.0562",\ +"-0.4688,-0.4522,-0.4395,-0.4073,-0.3604,-0.2559,-0.0635",\ +"-0.4989,-0.4823,-0.4696,-0.4373,-0.3905,-0.2860,-0.0936",\ +"-0.5565,-0.5399,-0.5272,-0.4950,-0.4481,-0.3436,-0.1512"); + } + + fall_constraint("SIG2SRAM_constraint_template") { + index_1("0.0056,0.0232,0.0400,0.0728,0.1280,0.2440,0.4760"); + index_2("0.0056,0.0232,0.0400,0.0728,0.1280,0.2440,0.4760"); + values ("-0.4107,-0.3951,-0.3824,-0.3541,-0.3033,-0.2047,-0.0260",\ +"-0.4157,-0.4001,-0.3874,-0.3591,-0.3083,-0.2097,-0.0310",\ +"-0.4202,-0.4046,-0.3919,-0.3636,-0.3128,-0.2141,-0.0354",\ +"-0.4293,-0.4137,-0.4010,-0.3727,-0.3219,-0.2232,-0.0445",\ +"-0.4366,-0.4209,-0.4082,-0.3799,-0.3291,-0.2305,-0.0518",\ +"-0.4667,-0.4510,-0.4383,-0.4100,-0.3592,-0.2606,-0.0819",\ +"-0.5242,-0.5086,-0.4959,-0.4676,-0.4168,-0.3182,-0.1395"); + } + } + + + timing() { + timing_type : hold_rising; + related_pin : "A_BIST_CLK"; + when : "(A_BIST_WEN & A_BIST_MEN)" + sdf_cond : "A_BIST_RW_ACCESS" + + rise_constraint("SIG2SRAM_constraint_template") { + index_1("0.0056,0.0232,0.0400,0.0728,0.1280,0.2440,0.4760"); + index_2("0.0056,0.0232,0.0400,0.0728,0.1280,0.2440,0.4760"); + values ("0.5520,0.5364,0.5237,0.4915,0.4427,0.3440,0.1477",\ +"0.5570,0.5414,0.5287,0.4965,0.4477,0.3490,0.1527",\ +"0.5615,0.5459,0.5332,0.5010,0.4521,0.3535,0.1572",\ +"0.5706,0.5550,0.5423,0.5101,0.4612,0.3626,0.1663",\ +"0.5779,0.5623,0.5496,0.5173,0.4685,0.3699,0.1736",\ +"0.6080,0.5923,0.5796,0.5474,0.4986,0.4000,0.2037",\ +"0.6656,0.6499,0.6372,0.6050,0.5562,0.4576,0.2613"); + } + + fall_constraint("SIG2SRAM_constraint_template") { + index_1("0.0056,0.0232,0.0400,0.0728,0.1280,0.2440,0.4760"); + index_2("0.0056,0.0232,0.0400,0.0728,0.1280,0.2440,0.4760"); + values ("0.5120,0.4973,0.4837,0.4554,0.4046,0.3118,0.1233",\ +"0.5170,0.5023,0.4887,0.4604,0.4096,0.3168,0.1283",\ +"0.5215,0.5068,0.4932,0.4648,0.4141,0.3213,0.1328",\ +"0.5306,0.5159,0.5022,0.4739,0.4231,0.3304,0.1419",\ +"0.5378,0.5232,0.5095,0.4812,0.4304,0.3376,0.1492",\ +"0.5679,0.5533,0.5396,0.5113,0.4605,0.3677,0.1792",\ +"0.6255,0.6109,0.5972,0.5689,0.5181,0.4253,0.2368"); + } + } +} + pin(A_BIST_CLK) { + direction : input; + capacitance : 0.00380014; + max_transition : "0.476"; + clock : "true" ; + pin_func_type : active_rising ; + + timing () { + timing_type : "min_pulse_width"; + related_pin : "A_BIST_CLK"; + rise_constraint("CLKTRAN_constraint_template") { + index_1("0.0056,0.476"); + values("0.21,0.21"); + } + } + + related_power_pin : VDD; + related_ground_pin : VSS; + + internal_power() { + when : "!A_BIST_MEN & !A_BIST_WEN & !A_BIST_REN"; + rise_power("scalar"){ + values (0); + } + fall_power("scalar"){ + values (0); + } + } + internal_power() { + when : "!A_BIST_MEN & A_BIST_WEN & !A_BIST_REN"; + rise_power("scalar"){ + values (0.5389); + } + fall_power("scalar"){ + values (0); + } + } + internal_power() { + when : "A_BIST_MEN & A_BIST_WEN & !A_BIST_REN"; + rise_power("scalar"){ + values (42.3165); + } + fall_power("scalar"){ + values (0); + } + } + internal_power() { + when : "A_BIST_MEN & A_BIST_WEN & A_BIST_REN"; + rise_power("scalar"){ + values (47.6101); + } + fall_power("scalar"){ + values (0); + } + } + internal_power() { + when : "A_BIST_MEN & !A_BIST_WEN & A_BIST_REN"; + rise_power("scalar"){ + values (36.0099); + } + fall_power("scalar"){ + values (0); + } + } + internal_power() { + when : "!A_BIST_MEN & !A_BIST_WEN & A_BIST_REN"; + rise_power("scalar"){ + values (0.3230); + } + fall_power("scalar"){ + values (0); + } + } + internal_power() { + when : "!A_BIST_MEN & A_BIST_WEN & A_BIST_REN"; + rise_power("scalar"){ + values (1.2182); + } + fall_power("scalar"){ + values (0); + } + } + internal_power() { + when : "A_BIST_MEN & !A_BIST_WEN & !A_BIST_REN"; + rise_power("scalar"){ + values (0); + } + fall_power("scalar"){ + values (0); + } + } + } + bus(A_BIST_DIN) { + bus_type : D_31_0; + direction : input ; + capacitance : 0.00233858 ; + memory_write() { + address : A_BIST_ADDR ; + clocked_on : A_BIST_CLK; + } + + max_transition : "0.476" ; + pin(A_BIST_DIN[31:0]) { + related_power_pin : VDD; + related_ground_pin : VSS; + internal_power() { + when : "A_BIST_MEN"; + rise_power("scalar"){ + values (0.1133); + } + fall_power("scalar"){ + values (0.0512); + } + } + internal_power() { + when : "!A_BIST_MEN"; + rise_power("scalar"){ + values (0.1175); + } + fall_power("scalar"){ + values (0.0489); + } + } + } + timing() { + timing_type : setup_rising; + related_pin : "A_BIST_CLK"; + when : "(A_BIST_WEN & A_BIST_MEN)"; + sdf_cond : "A_BIST_W_ACCESS"; + + rise_constraint("SIG2SRAM_constraint_template") { + index_1("0.0056,0.0232,0.0400,0.0728,0.1280,0.2440,0.4760"); + index_2("0.0056,0.0232,0.0400,0.0728,0.1280,0.2440,0.4760"); + values ("-0.4429,-0.4264,-0.4136,-0.3814,-0.3345,-0.2301,-0.0377",\ +"-0.4479,-0.4313,-0.4186,-0.3864,-0.3395,-0.2351,-0.0427",\ +"-0.4524,-0.4358,-0.4231,-0.3909,-0.3440,-0.2395,-0.0472",\ +"-0.4615,-0.4449,-0.4322,-0.4000,-0.3531,-0.2486,-0.0562",\ +"-0.4688,-0.4522,-0.4395,-0.4073,-0.3604,-0.2559,-0.0635",\ +"-0.4989,-0.4823,-0.4696,-0.4373,-0.3905,-0.2860,-0.0936",\ +"-0.5565,-0.5399,-0.5272,-0.4950,-0.4481,-0.3436,-0.1512"); + } + + fall_constraint("SIG2SRAM_constraint_template") { + index_1("0.0056,0.0232,0.0400,0.0728,0.1280,0.2440,0.4760"); + index_2("0.0056,0.0232,0.0400,0.0728,0.1280,0.2440,0.4760"); + values ("-0.4107,-0.3951,-0.3824,-0.3541,-0.3033,-0.2047,-0.0260",\ +"-0.4157,-0.4001,-0.3874,-0.3591,-0.3083,-0.2097,-0.0310",\ +"-0.4202,-0.4046,-0.3919,-0.3636,-0.3128,-0.2141,-0.0354",\ +"-0.4293,-0.4137,-0.4010,-0.3727,-0.3219,-0.2232,-0.0445",\ +"-0.4366,-0.4209,-0.4082,-0.3799,-0.3291,-0.2305,-0.0518",\ +"-0.4667,-0.4510,-0.4383,-0.4100,-0.3592,-0.2606,-0.0819",\ +"-0.5242,-0.5086,-0.4959,-0.4676,-0.4168,-0.3182,-0.1395"); + } + } + + timing() { + timing_type : hold_rising; + related_pin : "A_BIST_CLK"; + when : "(A_BIST_WEN & A_BIST_MEN)"; + sdf_cond : "A_BIST_W_ACCESS"; + + rise_constraint("SIG2SRAM_constraint_template") { + index_1("0.0056,0.0232,0.0400,0.0728,0.1280,0.2440,0.4760"); + index_2("0.0056,0.0232,0.0400,0.0728,0.1280,0.2440,0.4760"); + values ("0.5520,0.5364,0.5237,0.4915,0.4427,0.3440,0.1477",\ +"0.5570,0.5414,0.5287,0.4965,0.4477,0.3490,0.1527",\ +"0.5615,0.5459,0.5332,0.5010,0.4521,0.3535,0.1572",\ +"0.5706,0.5550,0.5423,0.5101,0.4612,0.3626,0.1663",\ +"0.5779,0.5623,0.5496,0.5173,0.4685,0.3699,0.1736",\ +"0.6080,0.5923,0.5796,0.5474,0.4986,0.4000,0.2037",\ +"0.6656,0.6499,0.6372,0.6050,0.5562,0.4576,0.2613"); + } + + fall_constraint("SIG2SRAM_constraint_template") { + index_1("0.0056,0.0232,0.0400,0.0728,0.1280,0.2440,0.4760"); + index_2("0.0056,0.0232,0.0400,0.0728,0.1280,0.2440,0.4760"); + values ("0.5120,0.4973,0.4837,0.4554,0.4046,0.3118,0.1233",\ +"0.5170,0.5023,0.4887,0.4604,0.4096,0.3168,0.1283",\ +"0.5215,0.5068,0.4932,0.4648,0.4141,0.3213,0.1328",\ +"0.5306,0.5159,0.5022,0.4739,0.4231,0.3304,0.1419",\ +"0.5378,0.5232,0.5095,0.4812,0.4304,0.3376,0.1492",\ +"0.5679,0.5533,0.5396,0.5113,0.4605,0.3677,0.1792",\ +"0.6255,0.6109,0.5972,0.5689,0.5181,0.4253,0.2368"); + } + } + } + +bus(A_DOUT) { + + bus_type : D_31_0; + direction : output ; + capacitance : 0 ; + max_capacitance : 0.064 ; + memory_read() { + address : A_ADDR ; + } + pin(A_DOUT[31:0]) { + related_power_pin : VDD; + related_ground_pin : VSS; + internal_power() { + rise_power("scalar") { + values (0); + } + fall_power("scalar") { + values (0); + } + } + } + timing() { + related_pin : "A_CLK"; + timing_type : rising_edge ; + timing_sense : non_unate ; + + cell_rise(SIG2SRAM_delay_template) { + index_1("0.0056,0.0232,0.0400,0.0728,0.1280,0.2440,0.4760"); + index_2("0.0008,0.0014,0.0051,0.0100,0.0339,0.0640"); + values ("3.8075,3.8091,3.8168,3.8255,3.8579,3.8938",\ +"3.8127,3.8143,3.8219,3.8306,3.8631,3.8989",\ +"3.8159,3.8175,3.8251,3.8338,3.8663,3.9021",\ +"3.8283,3.8299,3.8376,3.8463,3.8787,3.9146",\ +"3.8342,3.8358,3.8434,3.8521,3.8846,3.9204",\ +"3.8651,3.8667,3.8744,3.8831,3.9155,3.9514",\ +"3.9208,3.9224,3.9301,3.9388,3.9712,4.0071"); + } + cell_fall(SIG2SRAM_delay_template) { + index_1("0.0056,0.0232,0.0400,0.0728,0.1280,0.2440,0.4760"); + index_2("0.0008,0.0014,0.0051,0.0100,0.0339,0.0640"); + values ("3.7464,3.7478,3.7538,3.7609,3.7874,3.8140",\ +"3.7516,3.7529,3.7589,3.7661,3.7926,3.8192",\ +"3.7548,3.7561,3.7621,3.7693,3.7958,3.8224",\ +"3.7673,3.7686,3.7746,3.7817,3.8082,3.8349",\ +"3.7731,3.7744,3.7804,3.7876,3.8141,3.8407",\ +"3.8041,3.8054,3.8114,3.8185,3.8450,3.8717",\ +"3.8598,3.8611,3.8671,3.8742,3.9007,3.9274"); + } + + rise_transition(SRAM_load_template) { + index_1("0.0008,0.0014,0.0051,0.0100,0.0339,0.0640"); + values ("0.0326,0.0341,0.0428,0.0518,0.0923,0.1492"); + } + fall_transition(SRAM_load_template) { + index_1("0.0008,0.0014,0.0051,0.0100,0.0339,0.0640"); + values ("0.0254,0.0265,0.0335,0.0402,0.0707,0.1039"); + } + } +} +cell_leakage_power : 198.0155; +} +} diff --git a/flow/platforms/ihp-sg13g2/lib/RM_IHPSG13_1P_512x64_c2_bm_bist_fast_1p32V_m55C.lib b/flow/platforms/ihp-sg13g2/lib/RM_IHPSG13_1P_512x64_c2_bm_bist_fast_1p32V_m55C.lib index 1605c388be..c0cb7226a3 100644 --- a/flow/platforms/ihp-sg13g2/lib/RM_IHPSG13_1P_512x64_c2_bm_bist_fast_1p32V_m55C.lib +++ b/flow/platforms/ihp-sg13g2/lib/RM_IHPSG13_1P_512x64_c2_bm_bist_fast_1p32V_m55C.lib @@ -1459,7 +1459,7 @@ bus(A_DOUT) { bus_type : D_63_0; direction : output ; capacitance : 0 ; - max_capacitance : "6.4e-14" ; + max_capacitance : 0.064 ; memory_read() { address : A_ADDR ; } diff --git a/flow/platforms/ihp-sg13g2/lib/RM_IHPSG13_1P_512x64_c2_bm_bist_slow_1p08V_125C.lib b/flow/platforms/ihp-sg13g2/lib/RM_IHPSG13_1P_512x64_c2_bm_bist_slow_1p08V_125C.lib index 209e271a4a..1f907e69cd 100644 --- a/flow/platforms/ihp-sg13g2/lib/RM_IHPSG13_1P_512x64_c2_bm_bist_slow_1p08V_125C.lib +++ b/flow/platforms/ihp-sg13g2/lib/RM_IHPSG13_1P_512x64_c2_bm_bist_slow_1p08V_125C.lib @@ -1459,7 +1459,7 @@ bus(A_DOUT) { bus_type : D_63_0; direction : output ; capacitance : 0 ; - max_capacitance : "6.4e-14" ; + max_capacitance : 0.064 ; memory_read() { address : A_ADDR ; } diff --git a/flow/platforms/ihp-sg13g2/lib/RM_IHPSG13_1P_512x64_c2_bm_bist_typ_1p20V_25C.lib b/flow/platforms/ihp-sg13g2/lib/RM_IHPSG13_1P_512x64_c2_bm_bist_typ_1p20V_25C.lib index ae1a40d333..e4e636e5e7 100644 --- a/flow/platforms/ihp-sg13g2/lib/RM_IHPSG13_1P_512x64_c2_bm_bist_typ_1p20V_25C.lib +++ b/flow/platforms/ihp-sg13g2/lib/RM_IHPSG13_1P_512x64_c2_bm_bist_typ_1p20V_25C.lib @@ -1459,7 +1459,7 @@ bus(A_DOUT) { bus_type : D_63_0; direction : output ; capacitance : 0 ; - max_capacitance : "6.4e-14" ; + max_capacitance : 0.064 ; memory_read() { address : A_ADDR ; } diff --git a/flow/platforms/ihp-sg13g2/lib/RM_IHPSG13_1P_512x8_c3_bm_bist_fast_1p32V_m55C.lib b/flow/platforms/ihp-sg13g2/lib/RM_IHPSG13_1P_512x8_c3_bm_bist_fast_1p32V_m55C.lib new file mode 100644 index 0000000000..39a1175283 --- /dev/null +++ b/flow/platforms/ihp-sg13g2/lib/RM_IHPSG13_1P_512x8_c3_bm_bist_fast_1p32V_m55C.lib @@ -0,0 +1,1519 @@ +/* ------------------------------------------------------*/ +/**/ +/* Copyright 2025 IHP PDK Authors*/ +/**/ +/* Licensed under the Apache License, Version 2.0 (the "License");*/ +/* you may not use this file except in compliance with the License.*/ +/* You may obtain a copy of the License at*/ +/* */ +/* https://www.apache.org/licenses/LICENSE-2.0*/ +/* */ +/* Unless required by applicable law or agreed to in writing, software*/ +/* distributed under the License is distributed on an "AS IS" BASIS,*/ +/* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.*/ +/* See the License for the specific language governing permissions and*/ +/* limitations under the License.*/ +/* */ +/* Generated on Wed Aug 27 16:20:20 2025 */ +/* */ +/* ------------------------------------------------------ */ +library(RM_IHPSG13_1P_512x8_c3_bm_bist_fast_1p32V_m55C) { + technology (cmos) ; + delay_model : table_lookup ; + define ("add_pg_pin_to_lib", "library", "boolean"); + add_pg_pin_to_lib : true; + voltage_map ( VDD, 1.32); + voltage_map ( VDDARRAY, 1.32); + voltage_map ( VSS, 0.000000 ); + + date : "Wed Aug 27 16:20:18 2025" ; + comment : "IHP Microelectronics GmbH, 2023" ; + revision : 1.0.0 ; + simulation : true ; + nom_process : 1 ; + nom_temperature : -55 ; + nom_voltage : 1.32 ; + + operating_conditions("fast_1p32V_m55C"){ + process : 1 ; + temperature : -55 ; + voltage : 1.32 ; + tree_type : "balanced_tree" ; + } + + default_operating_conditions : fast_1p32V_m55C ; + default_max_transition : 1.0 ; + default_fanout_load : 1.0 ; + default_inout_pin_cap : 0.0 ; + default_input_pin_cap : 0.0 ; + default_output_pin_cap : 0.0 ; + default_cell_leakage_power : 0.0 ; + default_leakage_power_density : 0.0 ; + + slew_lower_threshold_pct_rise : 30 ; + slew_upper_threshold_pct_rise : 70 ; + input_threshold_pct_fall : 50 ; + output_threshold_pct_fall : 50 ; + input_threshold_pct_rise : 50 ; + output_threshold_pct_rise : 50 ; + slew_lower_threshold_pct_fall : 30 ; + slew_upper_threshold_pct_fall : 70 ; + slew_derate_from_library : 0.5; + k_volt_cell_leakage_power : 0.0 ; + k_temp_cell_leakage_power : 0.0 ; + k_process_cell_leakage_power : 0.0 ; + k_volt_internal_power : 0.0 ; + k_temp_internal_power : 0.0 ; + k_process_internal_power : 0.0 ; + + capacitive_load_unit (1,pf) ; + voltage_unit : "1V" ; + current_unit : "1uA" ; + time_unit : "1ns" ; + leakage_power_unit : "1nW" ; + pulling_resistance_unit : "1kohm"; + /* + ------------------------------------------------------------------------------------------ + implicit units overview: + cell_area unit : "um" + internal_power unit : "1e-12 * J/toggle = 1 * uW/MHz" + (capacitive_load_unit * voltage_unit^2) per toggle event + ------------------------------------------------------------------------------------------ + */ + library_features(report_delay_calculation); + define_cell_area (pad_drivers,pad_driver_sites) ; + + lu_table_template(CLKTRAN_constraint_template) { + variable_1 : constrained_pin_transition; + index_1 ( "0.010, 0.050, 0.200, 0.400, 1.000" ); + } + lu_table_template(SRAM_load_template) { + variable_1 : total_output_net_capacitance; + index_1 ( "0.0008,0.0014,0.0051,0.0100,0.0339,0.0640" ); + } + lu_table_template(SIG2SRAM_constraint_template) { + variable_1 : related_pin_transition; + variable_2 : constrained_pin_transition; + index_1 ( "0.0040,0.0176,0.0344,0.0656,0.1120,0.2016,0.3800" ); + index_2 ( "0.0040,0.0176,0.0344,0.0656,0.1120,0.2016,0.3800" ); + } + + lu_table_template(SIG2SRAM_delay_template) { + variable_1 : input_net_transition; + variable_2 : total_output_net_capacitance; + index_1 ( "0.0040,0.0176,0.0344,0.0656,0.1120,0.2016,0.3800" ); + index_2 ( "0.0008,0.0014,0.0051,0.0100,0.0339,0.0640" ); + } + + type (D_7_0) { + base_type : array; + data_type : bit; + bit_width : 8; + bit_from : 7; + bit_to : 0; + downto : true; + } + + type (A_8_0) { + base_type : array; + data_type : bit; + bit_width : 9; + bit_from : 8; + bit_to : 0; + downto : true; + } + +cell(RM_IHPSG13_1P_512x8_c3_bm_bist) { +pg_pin (VDD) { + pg_type : primary_power; + voltage_name : VDD; +} +pg_pin (VDDARRAY) { + pg_type : primary_power; + voltage_name : VDDARRAY; +} +pg_pin (VSS) { + pg_type : primary_ground; + voltage_name : VSS; +} + +memory() { + type : ram; + address_width : 9; + word_width : 8; +} + +interface_timing : false; +bus_naming_style : "%s[%d]" ; +area : 26137.984 ; + + pin(A_DLY) { + direction : input ; + capacitance : 0.00421562 ; + max_transition : "1" ; + related_power_pin : VDD; + related_ground_pin : VSS; + internal_power() { + rise_power("scalar") { + values (0); + } + fall_power("scalar") { + values (0); + } + } + } + +bus(A_ADDR) { + bus_type : A_8_0; + direction : input ; + capacitance : 0.00691085 ; + pin(A_ADDR[0]) { + capacitance : 0.00562034 ; + } + pin(A_ADDR[1]) { + capacitance : 0.00462655 ; + } + pin(A_ADDR[2]) { + capacitance : 0.00594295 ; + } + pin(A_ADDR[3]) { + capacitance : 0.00723434 ; + } + pin(A_ADDR[4]) { + capacitance : 0.00481603 ; + } + pin(A_ADDR[5]) { + capacitance : 0.00868123 ; + } + pin(A_ADDR[6]) { + capacitance : 0.010187 ; + } + pin(A_ADDR[7]) { + capacitance : 0.00734489 ; + } + max_transition : "0.38" ; + pin(A_ADDR[8:0]) { + related_power_pin : VDD; + related_ground_pin : VSS; + internal_power() { + when : "A_MEN"; + rise_power("scalar"){ + values (0.1447); + } + fall_power("scalar"){ + values (0.0095); + } + } + internal_power() { + when : "!A_MEN"; + rise_power("scalar"){ + values (0.0256); + } + fall_power("scalar"){ + values (0.0000); + } + } + } + timing() { + timing_type : setup_rising; + related_pin : "A_CLK"; + when : "((A_WEN | A_REN)& A_MEN)" + sdf_cond : "A_RW_ACCESS" + + rise_constraint("SIG2SRAM_constraint_template") { + index_1("0.0040,0.0176,0.0344,0.0656,0.1120,0.2016,0.3800"); + index_2("0.0040,0.0176,0.0344,0.0656,0.1120,0.2016,0.3800"); + values ("-0.2371,-0.2215,-0.2098,-0.1824,-0.1434,-0.0691,0.0676",\ +"-0.2449,-0.2332,-0.2176,-0.1902,-0.1551,-0.0770,0.0559",\ +"-0.2605,-0.2488,-0.2332,-0.2059,-0.1707,-0.0965,0.0441",\ +"-0.2879,-0.2723,-0.2605,-0.2332,-0.1941,-0.1199,0.0168",\ +"-0.3230,-0.3113,-0.2996,-0.2723,-0.2332,-0.1590,-0.0184",\ +"-0.4012,-0.3895,-0.3738,-0.3465,-0.3074,-0.2332,-0.0965",\ +"-0.5379,-0.5262,-0.5105,-0.4832,-0.4480,-0.3699,-0.2332"); + } + + fall_constraint("SIG2SRAM_constraint_template") { + index_1("0.0040,0.0176,0.0344,0.0656,0.1120,0.2016,0.3800"); + index_2("0.0040,0.0176,0.0344,0.0656,0.1120,0.2016,0.3800"); + values ("-0.1785,-0.1707,-0.1551,-0.1277,-0.0887,-0.0184,0.1145",\ +"-0.1902,-0.1785,-0.1629,-0.1355,-0.1004,-0.0262,0.1027",\ +"-0.2059,-0.1941,-0.1785,-0.1512,-0.1160,-0.0418,0.0871",\ +"-0.2293,-0.2176,-0.2059,-0.1785,-0.1434,-0.0691,0.0598",\ +"-0.2684,-0.2566,-0.2449,-0.2176,-0.1824,-0.1082,0.0207",\ +"-0.3465,-0.3348,-0.3191,-0.2918,-0.2566,-0.1824,-0.0535",\ +"-0.4832,-0.4715,-0.4559,-0.4324,-0.3934,-0.3191,-0.1902"); + } + } + + + timing() { + timing_type : hold_rising; + related_pin : "A_CLK"; + when : "((A_WEN | A_REN)& A_MEN)" + sdf_cond : "A_RW_ACCESS" + + rise_constraint("SIG2SRAM_constraint_template") { + index_1("0.0040,0.0176,0.0344,0.0656,0.1120,0.2016,0.3800"); + index_2("0.0040,0.0176,0.0344,0.0656,0.1120,0.2016,0.3800"); + values ("0.3410,0.3293,0.3137,0.2863,0.2473,0.1730,0.0324",\ +"0.3488,0.3371,0.3215,0.2941,0.2590,0.1809,0.0480",\ +"0.3684,0.3527,0.3371,0.3098,0.2746,0.1965,0.0598",\ +"0.3918,0.3762,0.3645,0.3371,0.2980,0.2238,0.0871",\ +"0.4309,0.4152,0.4035,0.3762,0.3371,0.2629,0.1223",\ +"0.5051,0.4934,0.4777,0.4504,0.4113,0.3371,0.1965",\ +"0.6418,0.6262,0.6145,0.5871,0.5520,0.4738,0.3332"); + } + + fall_constraint("SIG2SRAM_constraint_template") { + index_1("0.0040,0.0176,0.0344,0.0656,0.1120,0.2016,0.3800"); + index_2("0.0040,0.0176,0.0344,0.0656,0.1120,0.2016,0.3800"); + values ("0.2824,0.2707,0.2551,0.2277,0.1926,0.1184,-0.0105",\ +"0.2902,0.2785,0.2668,0.2395,0.2043,0.1301,0.0012",\ +"0.3059,0.2941,0.2824,0.2551,0.2199,0.1457,0.0168",\ +"0.3332,0.3215,0.3059,0.2785,0.2434,0.1691,0.0402",\ +"0.3723,0.3605,0.3449,0.3176,0.2824,0.2121,0.0793",\ +"0.4465,0.4348,0.4230,0.3918,0.3566,0.2824,0.1535",\ +"0.5832,0.5715,0.5598,0.5324,0.4934,0.4191,0.2902"); + } + } +} +pin(A_WEN) { + direction : input ; + capacitance : 0.00341384 ; + max_transition : "0.38" ; + related_power_pin : VDD; + related_ground_pin : VSS; + internal_power() { + when : "A_MEN"; + rise_power("scalar"){ + values (0.0064); + } + fall_power("scalar"){ + values (0.0158); + } + } + internal_power() { + when : "!A_MEN"; + rise_power("scalar"){ + values (0.0047); + } + fall_power("scalar"){ + values (0.0213); + } + } + timing() { + timing_type : setup_rising; + related_pin : "A_CLK"; + when : "A_MEN" + sdf_cond : "A_MEN" + + rise_constraint("SIG2SRAM_constraint_template") { + index_1("0.0040,0.0176,0.0344,0.0656,0.1120,0.2016,0.3800"); + index_2("0.0040,0.0176,0.0344,0.0656,0.1120,0.2016,0.3800"); + values ("0.1418,0.1496,0.1652,0.1887,0.2316,0.3059,0.4465",\ +"0.1301,0.1379,0.1535,0.1809,0.2199,0.2941,0.4348",\ +"0.1145,0.1262,0.1379,0.1652,0.2043,0.2785,0.4191",\ +"0.0871,0.0949,0.1105,0.1379,0.1770,0.2512,0.3879",\ +"0.0480,0.0598,0.0754,0.0988,0.1379,0.2082,0.3527",\ +"-0.0262,-0.0145,0.0012,0.0246,0.0676,0.1379,0.2785",\ +"-0.1668,-0.1551,-0.1395,-0.1121,-0.0730,0.0012,0.1418"); + } + + fall_constraint("SIG2SRAM_constraint_template") { + index_1("0.0040,0.0176,0.0344,0.0656,0.1120,0.2016,0.3800"); + index_2("0.0040,0.0176,0.0344,0.0656,0.1120,0.2016,0.3800"); + values ("0.2082,0.2160,0.2316,0.2590,0.2941,0.3684,0.5012",\ +"0.1926,0.2043,0.2199,0.2473,0.2824,0.3566,0.4895",\ +"0.1770,0.1887,0.2043,0.2316,0.2668,0.3410,0.4777",\ +"0.1535,0.1652,0.1770,0.2043,0.2395,0.3137,0.4504",\ +"0.1145,0.1262,0.1379,0.1652,0.2043,0.2746,0.4113",\ +"0.0402,0.0520,0.0676,0.0910,0.1262,0.2004,0.3332",\ +"-0.0965,-0.0848,-0.0730,-0.0457,-0.0066,0.0637,0.2004"); + } + } + + + timing() { + timing_type : hold_rising; + related_pin : "A_CLK"; + when : "A_MEN" + sdf_cond : "A_MEN" + + rise_constraint("SIG2SRAM_constraint_template") { + index_1("0.0040,0.0176,0.0344,0.0656,0.1120,0.2016,0.3800"); + index_2("0.0040,0.0176,0.0344,0.0656,0.1120,0.2016,0.3800"); + values ("0.1770,0.1652,0.1496,0.1223,0.0793,0.0090,-0.1316",\ +"0.1848,0.1730,0.1574,0.1301,0.0910,0.0168,-0.1199",\ +"0.2004,0.1887,0.1770,0.1496,0.1066,0.0363,-0.1043",\ +"0.2277,0.2160,0.2004,0.1730,0.1340,0.0598,-0.0809",\ +"0.2668,0.2551,0.2395,0.2121,0.1730,0.0988,-0.0418",\ +"0.3410,0.3293,0.3137,0.2863,0.2434,0.1730,0.0324",\ +"0.4816,0.4699,0.4543,0.4230,0.3801,0.3098,0.1730"); + } + + fall_constraint("SIG2SRAM_constraint_template") { + index_1("0.0040,0.0176,0.0344,0.0656,0.1120,0.2016,0.3800"); + index_2("0.0040,0.0176,0.0344,0.0656,0.1120,0.2016,0.3800"); + values ("0.1613,0.1496,0.1379,0.1066,0.0715,0.0012,-0.1355",\ +"0.1730,0.1613,0.1457,0.1184,0.0832,0.0129,-0.1238",\ +"0.1887,0.1770,0.1613,0.1340,0.0988,0.0246,-0.1121",\ +"0.2121,0.2043,0.1887,0.1613,0.1223,0.0520,-0.0848",\ +"0.2512,0.2434,0.2277,0.2004,0.1613,0.0910,-0.0457",\ +"0.3254,0.3176,0.3020,0.2746,0.2355,0.1652,0.0324",\ +"0.4660,0.4543,0.4387,0.4113,0.3723,0.3020,0.1691"); + } + } + } +pin(A_REN) { + direction : input ; + capacitance : 0.00390661 ; + max_transition : "0.38" ; + related_power_pin : VDD; + related_ground_pin : VSS; + internal_power() { + when : "A_MEN"; + rise_power("scalar"){ + values (0.0098); + } + fall_power("scalar"){ + values (0.0114); + } + } + internal_power() { + when : "!A_MEN"; + rise_power("scalar"){ + values (0.0251); + } + fall_power("scalar"){ + values (0.0208); + } + } + timing() { + timing_type : setup_rising; + related_pin : "A_CLK"; + when : "A_MEN" + sdf_cond : "A_MEN" + + rise_constraint("SIG2SRAM_constraint_template") { + index_1("0.0040,0.0176,0.0344,0.0656,0.1120,0.2016,0.3800"); + index_2("0.0040,0.0176,0.0344,0.0656,0.1120,0.2016,0.3800"); + values ("-0.0027,0.0090,0.0246,0.0520,0.0910,0.1613,0.3020",\ +"-0.0105,0.0012,0.0129,0.0363,0.0793,0.1535,0.2902",\ +"-0.0262,-0.0145,-0.0027,0.0246,0.0637,0.1379,0.2785",\ +"-0.0535,-0.0418,-0.0262,0.0012,0.0363,0.1105,0.2512",\ +"-0.0926,-0.0809,-0.0652,-0.0418,-0.0027,0.0715,0.2121",\ +"-0.1668,-0.1551,-0.1395,-0.1082,-0.0770,-0.0027,0.1379",\ +"-0.3035,-0.2918,-0.2762,-0.2488,-0.2137,-0.1434,-0.0027"); + } + + fall_constraint("SIG2SRAM_constraint_template") { + index_1("0.0040,0.0176,0.0344,0.0656,0.1120,0.2016,0.3800"); + index_2("0.0040,0.0176,0.0344,0.0656,0.1120,0.2016,0.3800"); + values ("0.0832,0.0949,0.1105,0.1379,0.1730,0.2473,0.3801",\ +"0.0754,0.0832,0.0988,0.1223,0.1613,0.2355,0.3684",\ +"0.0598,0.0676,0.0832,0.1066,0.1457,0.2121,0.3527",\ +"0.0324,0.0441,0.0598,0.0871,0.1223,0.1926,0.3293",\ +"-0.0066,0.0051,0.0168,0.0480,0.0832,0.1535,0.2902",\ +"-0.0809,-0.0691,-0.0574,-0.0301,0.0090,0.0832,0.2121",\ +"-0.2176,-0.2059,-0.1941,-0.1668,-0.1277,-0.0574,0.0793"); + } + } + + + timing() { + timing_type : hold_rising; + related_pin : "A_CLK"; + when : "A_MEN" + sdf_cond : "A_MEN" + + rise_constraint("SIG2SRAM_constraint_template") { + index_1("0.0040,0.0176,0.0344,0.0656,0.1120,0.2016,0.3800"); + index_2("0.0040,0.0176,0.0344,0.0656,0.1120,0.2016,0.3800"); + values ("0.1887,0.1770,0.1613,0.1340,0.0949,0.0207,-0.1160",\ +"0.1965,0.1848,0.1730,0.1457,0.1027,0.0324,-0.1082",\ +"0.2160,0.2004,0.1887,0.1613,0.1184,0.0480,-0.0926",\ +"0.2395,0.2277,0.2121,0.1848,0.1457,0.0715,-0.0652",\ +"0.2785,0.2668,0.2512,0.2238,0.1848,0.1105,-0.0262",\ +"0.3527,0.3410,0.3254,0.2980,0.2551,0.1848,0.0480",\ +"0.4934,0.4816,0.4660,0.4387,0.3957,0.3254,0.1887"); + } + + fall_constraint("SIG2SRAM_constraint_template") { + index_1("0.0040,0.0176,0.0344,0.0656,0.1120,0.2016,0.3800"); + index_2("0.0040,0.0176,0.0344,0.0656,0.1120,0.2016,0.3800"); + values ("0.1730,0.1613,0.1496,0.1184,0.0793,0.0129,-0.1238",\ +"0.1848,0.1730,0.1574,0.1301,0.0910,0.0207,-0.1121",\ +"0.2004,0.1887,0.1730,0.1457,0.1066,0.0363,-0.1004",\ +"0.2238,0.2121,0.2004,0.1691,0.1340,0.0598,-0.0730",\ +"0.2629,0.2512,0.2395,0.2121,0.1691,0.0988,-0.0340",\ +"0.3371,0.3254,0.3137,0.2863,0.2434,0.1730,0.0402",\ +"0.4777,0.4660,0.4504,0.4230,0.3840,0.3137,0.1809"); + } + } + } +pin(A_MEN) { + direction : input ; + capacitance : 0.00326046 ; + max_transition : "0.38" ; + related_power_pin : VDD; + related_ground_pin : VSS; + internal_power() { + rise_power("scalar"){ + values (0.0779); + } + fall_power("scalar"){ + values (0.0819); + } + } + timing() { + timing_type : setup_rising; + related_pin : "A_CLK"; + + rise_constraint("SIG2SRAM_constraint_template") { + index_1("0.0040,0.0176,0.0344,0.0656,0.1120,0.2016,0.3800"); + index_2("0.0040,0.0176,0.0344,0.0656,0.1120,0.2016,0.3800"); + values ("0.1418,0.1496,0.1652,0.1926,0.2316,0.3059,0.4465",\ +"0.1301,0.1379,0.1535,0.1809,0.2199,0.2941,0.4348",\ +"0.1145,0.1262,0.1418,0.1652,0.2043,0.2785,0.4191",\ +"0.0871,0.0949,0.1105,0.1379,0.1770,0.2512,0.3879",\ +"0.0480,0.0598,0.0754,0.0988,0.1379,0.2082,0.3488",\ +"-0.0262,-0.0145,0.0012,0.0285,0.0676,0.1379,0.2785",\ +"-0.1668,-0.1551,-0.1395,-0.1121,-0.0730,0.0012,0.1379"); + } + + fall_constraint("SIG2SRAM_constraint_template") { + index_1("0.0040,0.0176,0.0344,0.0656,0.1120,0.2016,0.3800"); + index_2("0.0040,0.0176,0.0344,0.0656,0.1120,0.2016,0.3800"); + values ("0.2082,0.2199,0.2316,0.2590,0.2980,0.3723,0.5051",\ +"0.1965,0.2082,0.2199,0.2473,0.2863,0.3605,0.4934",\ +"0.1809,0.1926,0.2043,0.2316,0.2707,0.3449,0.4777",\ +"0.1574,0.1691,0.1809,0.2082,0.2434,0.3176,0.4543",\ +"0.1145,0.1262,0.1418,0.1691,0.2043,0.2785,0.4113",\ +"0.0441,0.0559,0.0676,0.0949,0.1301,0.2004,0.3332",\ +"-0.0965,-0.0848,-0.0691,-0.0418,-0.0066,0.0676,0.2004"); + } + } + + + timing() { + timing_type : hold_rising; + related_pin : "A_CLK"; + + rise_constraint("SIG2SRAM_constraint_template") { + index_1("0.0040,0.0176,0.0344,0.0656,0.1120,0.2016,0.3800"); + index_2("0.0040,0.0176,0.0344,0.0656,0.1120,0.2016,0.3800"); + values ("0.1770,0.1652,0.1535,0.1262,0.0832,0.0129,-0.1277",\ +"0.1887,0.1770,0.1613,0.1340,0.0949,0.0207,-0.1199",\ +"0.2043,0.1926,0.1770,0.1496,0.1105,0.0363,-0.1043",\ +"0.2277,0.2160,0.2043,0.1770,0.1379,0.0598,-0.0770",\ +"0.2668,0.2551,0.2434,0.2160,0.1730,0.0988,-0.0379",\ +"0.3449,0.3332,0.3176,0.2902,0.2473,0.1730,0.0363",\ +"0.4816,0.4699,0.4543,0.4270,0.3840,0.3098,0.1770"); + } + + fall_constraint("SIG2SRAM_constraint_template") { + index_1("0.0040,0.0176,0.0344,0.0656,0.1120,0.2016,0.3800"); + index_2("0.0040,0.0176,0.0344,0.0656,0.1120,0.2016,0.3800"); + values ("0.1613,0.1496,0.1379,0.1105,0.0715,0.0012,-0.1355",\ +"0.1730,0.1613,0.1496,0.1184,0.0832,0.0129,-0.1238",\ +"0.1887,0.1770,0.1652,0.1340,0.0988,0.0285,-0.1121",\ +"0.2121,0.2043,0.1887,0.1613,0.1223,0.0520,-0.0848",\ +"0.2551,0.2434,0.2277,0.2004,0.1613,0.0910,-0.0418",\ +"0.3293,0.3176,0.3020,0.2746,0.2395,0.1652,0.0324",\ +"0.4660,0.4543,0.4426,0.4113,0.3762,0.3020,0.1691"); + } + } + } +bus(A_BM) { + bus_type : D_7_0; + direction : input ; + capacitance : 0.00318267 ; + max_transition : "0.38" ; + pin(A_BM[7:0]) { + related_power_pin : VDD; + related_ground_pin : VSS; + internal_power() { + when : "A_MEN"; + rise_power("scalar"){ + values (0.0370); + } + fall_power("scalar"){ + values (0.0444); + } + } + internal_power() { + when : "!A_MEN"; + rise_power("scalar"){ + values (0.0531); + } + fall_power("scalar"){ + values (0.0511); + } + } + } + timing() { + timing_type : setup_rising; + related_pin : "A_CLK"; + when : "(A_WEN & A_MEN)" + sdf_cond : "A_RW_ACCESS" + + rise_constraint("SIG2SRAM_constraint_template") { + index_1("0.0040,0.0176,0.0344,0.0656,0.1120,0.2016,0.3800"); + index_2("0.0040,0.0176,0.0344,0.0656,0.1120,0.2016,0.3800"); + values ("-0.1742,-0.1634,-0.1478,-0.1224,-0.0814,-0.0082,0.1266",\ +"-0.1781,-0.1673,-0.1517,-0.1263,-0.0853,-0.0121,0.1227",\ +"-0.1817,-0.1710,-0.1554,-0.1300,-0.0890,-0.0157,0.1190",\ +"-0.1850,-0.1742,-0.1586,-0.1332,-0.0922,-0.0189,0.1158",\ +"-0.1976,-0.1868,-0.1712,-0.1458,-0.1048,-0.0315,0.1032",\ +"-0.2152,-0.2044,-0.1888,-0.1634,-0.1224,-0.0492,0.0856",\ +"-0.2427,-0.2319,-0.2163,-0.1909,-0.1499,-0.0767,0.0581"); + } + + fall_constraint("SIG2SRAM_constraint_template") { + index_1("0.0040,0.0176,0.0344,0.0656,0.1120,0.2016,0.3800"); + index_2("0.0040,0.0176,0.0344,0.0656,0.1120,0.2016,0.3800"); + values ("-0.1507,-0.1390,-0.1263,-0.0990,-0.0619,0.0114,0.1393",\ +"-0.1546,-0.1429,-0.1302,-0.1029,-0.0658,0.0075,0.1354",\ +"-0.1583,-0.1466,-0.1339,-0.1065,-0.0694,0.0038,0.1317",\ +"-0.1615,-0.1498,-0.1371,-0.1098,-0.0726,0.0006,0.1285",\ +"-0.1741,-0.1624,-0.1497,-0.1224,-0.0853,-0.0120,0.1159",\ +"-0.1917,-0.1800,-0.1673,-0.1400,-0.1029,-0.0296,0.0983",\ +"-0.2192,-0.2075,-0.1948,-0.1675,-0.1304,-0.0571,0.0708"); + } + } + + + timing() { + timing_type : hold_rising; + related_pin : "A_CLK"; + when : "(A_WEN & A_MEN)" + sdf_cond : "A_RW_ACCESS" + + rise_constraint("SIG2SRAM_constraint_template") { + index_1("0.0040,0.0176,0.0344,0.0656,0.1120,0.2016,0.3800"); + index_2("0.0040,0.0176,0.0344,0.0656,0.1120,0.2016,0.3800"); + values ("0.2792,0.2694,0.2538,0.2274,0.1903,0.1161,-0.0187",\ +"0.2830,0.2733,0.2577,0.2313,0.1942,0.1200,-0.0148",\ +"0.2867,0.2770,0.2613,0.2350,0.1979,0.1236,-0.0111",\ +"0.2899,0.2802,0.2645,0.2382,0.2011,0.1268,-0.0079",\ +"0.3025,0.2928,0.2772,0.2508,0.2137,0.1395,0.0047",\ +"0.3202,0.3104,0.2948,0.2684,0.2313,0.1571,0.0223",\ +"0.3477,0.3379,0.3223,0.2959,0.2588,0.1846,0.0498"); + } + + fall_constraint("SIG2SRAM_constraint_template") { + index_1("0.0040,0.0176,0.0344,0.0656,0.1120,0.2016,0.3800"); + index_2("0.0040,0.0176,0.0344,0.0656,0.1120,0.2016,0.3800"); + values ("0.2508,0.2401,0.2264,0.1991,0.1630,0.0907,-0.0392",\ +"0.2547,0.2440,0.2303,0.2030,0.1668,0.0946,-0.0353",\ +"0.2584,0.2477,0.2340,0.2066,0.1705,0.0983,-0.0316",\ +"0.2616,0.2509,0.2372,0.2098,0.1737,0.1015,-0.0284",\ +"0.2742,0.2635,0.2498,0.2225,0.1863,0.1141,-0.0158",\ +"0.2918,0.2811,0.2674,0.2401,0.2039,0.1317,0.0018",\ +"0.3193,0.3086,0.2949,0.2676,0.2314,0.1592,0.0293"); + } + } +} + pin(A_CLK) { + direction : input; + capacitance : 0.00389386; + max_transition : "0.38"; + clock : "true" ; + pin_func_type : active_rising ; + + timing () { + timing_type : "min_pulse_width"; + related_pin : "A_CLK"; + rise_constraint("CLKTRAN_constraint_template") { + index_1("0.004,0.38"); + values("0.12,0.12"); + } + } + + related_power_pin : VDD; + related_ground_pin : VSS; + + internal_power() { + when : "!A_MEN & !A_WEN & !A_REN"; + rise_power("scalar"){ + values (0); + } + fall_power("scalar"){ + values (0); + } + } + internal_power() { + when : "!A_MEN & A_WEN & !A_REN"; + rise_power("scalar"){ + values (0.6302); + } + fall_power("scalar"){ + values (0); + } + } + internal_power() { + when : "A_MEN & A_WEN & !A_REN"; + rise_power("scalar"){ + values (19.4264); + } + fall_power("scalar"){ + values (0); + } + } + internal_power() { + when : "A_MEN & A_WEN & A_REN"; + rise_power("scalar"){ + values (19.1463); + } + fall_power("scalar"){ + values (0); + } + } + internal_power() { + when : "A_MEN & !A_WEN & A_REN"; + rise_power("scalar"){ + values (14.6404); + } + fall_power("scalar"){ + values (0); + } + } + internal_power() { + when : "!A_MEN & !A_WEN & A_REN"; + rise_power("scalar"){ + values (0.3917); + } + fall_power("scalar"){ + values (0); + } + } + internal_power() { + when : "!A_MEN & A_WEN & A_REN"; + rise_power("scalar"){ + values (0.6655); + } + fall_power("scalar"){ + values (0); + } + } + internal_power() { + when : "A_MEN & !A_WEN & !A_REN"; + rise_power("scalar"){ + values (0); + } + fall_power("scalar"){ + values (0); + } + } + } + bus(A_DIN) { + bus_type : D_7_0; + direction : input ; + capacitance : 0.00332733 ; + memory_write() { + address : A_ADDR ; + clocked_on : A_CLK; + } + + max_transition : "0.38" ; + pin(A_DIN[7:0]) { + related_power_pin : VDD; + related_ground_pin : VSS; + internal_power() { + when : "A_MEN"; + rise_power("scalar"){ + values (0.0370); + } + fall_power("scalar"){ + values (0.0444); + } + } + internal_power() { + when : "!A_MEN"; + rise_power("scalar"){ + values (0.0531); + } + fall_power("scalar"){ + values (0.0511); + } + } + } + timing() { + timing_type : setup_rising; + related_pin : "A_CLK"; + when : "(A_WEN & A_MEN)"; + sdf_cond : "A_W_ACCESS"; + + rise_constraint("SIG2SRAM_constraint_template") { + index_1("0.0040,0.0176,0.0344,0.0656,0.1120,0.2016,0.3800"); + index_2("0.0040,0.0176,0.0344,0.0656,0.1120,0.2016,0.3800"); + values ("-0.1742,-0.1634,-0.1478,-0.1224,-0.0814,-0.0082,0.1266",\ +"-0.1781,-0.1673,-0.1517,-0.1263,-0.0853,-0.0121,0.1227",\ +"-0.1817,-0.1710,-0.1554,-0.1300,-0.0890,-0.0157,0.1190",\ +"-0.1850,-0.1742,-0.1586,-0.1332,-0.0922,-0.0189,0.1158",\ +"-0.1976,-0.1868,-0.1712,-0.1458,-0.1048,-0.0315,0.1032",\ +"-0.2152,-0.2044,-0.1888,-0.1634,-0.1224,-0.0492,0.0856",\ +"-0.2427,-0.2319,-0.2163,-0.1909,-0.1499,-0.0767,0.0581"); + } + + fall_constraint("SIG2SRAM_constraint_template") { + index_1("0.0040,0.0176,0.0344,0.0656,0.1120,0.2016,0.3800"); + index_2("0.0040,0.0176,0.0344,0.0656,0.1120,0.2016,0.3800"); + values ("-0.1507,-0.1390,-0.1263,-0.0990,-0.0619,0.0114,0.1393",\ +"-0.1546,-0.1429,-0.1302,-0.1029,-0.0658,0.0075,0.1354",\ +"-0.1583,-0.1466,-0.1339,-0.1065,-0.0694,0.0038,0.1317",\ +"-0.1615,-0.1498,-0.1371,-0.1098,-0.0726,0.0006,0.1285",\ +"-0.1741,-0.1624,-0.1497,-0.1224,-0.0853,-0.0120,0.1159",\ +"-0.1917,-0.1800,-0.1673,-0.1400,-0.1029,-0.0296,0.0983",\ +"-0.2192,-0.2075,-0.1948,-0.1675,-0.1304,-0.0571,0.0708"); + } + } + + timing() { + timing_type : hold_rising; + related_pin : "A_CLK"; + when : "(A_WEN & A_MEN)"; + sdf_cond : "A_W_ACCESS"; + + rise_constraint("SIG2SRAM_constraint_template") { + index_1("0.0040,0.0176,0.0344,0.0656,0.1120,0.2016,0.3800"); + index_2("0.0040,0.0176,0.0344,0.0656,0.1120,0.2016,0.3800"); + values ("0.2792,0.2694,0.2538,0.2274,0.1903,0.1161,-0.0187",\ +"0.2830,0.2733,0.2577,0.2313,0.1942,0.1200,-0.0148",\ +"0.2867,0.2770,0.2613,0.2350,0.1979,0.1236,-0.0111",\ +"0.2899,0.2802,0.2645,0.2382,0.2011,0.1268,-0.0079",\ +"0.3025,0.2928,0.2772,0.2508,0.2137,0.1395,0.0047",\ +"0.3202,0.3104,0.2948,0.2684,0.2313,0.1571,0.0223",\ +"0.3477,0.3379,0.3223,0.2959,0.2588,0.1846,0.0498"); + } + + fall_constraint("SIG2SRAM_constraint_template") { + index_1("0.0040,0.0176,0.0344,0.0656,0.1120,0.2016,0.3800"); + index_2("0.0040,0.0176,0.0344,0.0656,0.1120,0.2016,0.3800"); + values ("0.2508,0.2401,0.2264,0.1991,0.1630,0.0907,-0.0392",\ +"0.2547,0.2440,0.2303,0.2030,0.1668,0.0946,-0.0353",\ +"0.2584,0.2477,0.2340,0.2066,0.1705,0.0983,-0.0316",\ +"0.2616,0.2509,0.2372,0.2098,0.1737,0.1015,-0.0284",\ +"0.2742,0.2635,0.2498,0.2225,0.1863,0.1141,-0.0158",\ +"0.2918,0.2811,0.2674,0.2401,0.2039,0.1317,0.0018",\ +"0.3193,0.3086,0.2949,0.2676,0.2314,0.1592,0.0293"); + } + } + } + + pin(A_BIST_EN) { + direction : input ; + capacitance : 0.00421562 ; + max_transition : "1" ; + related_power_pin : VDD; + related_ground_pin : VSS; + internal_power() { + rise_power("scalar") { + values (0); + } + fall_power("scalar") { + values (0); + } + } + } + +bus(A_BIST_ADDR) { + bus_type : A_8_0; + direction : input ; + capacitance : 0.00691085 ; + pin(A_BIST_ADDR[0]) { + capacitance : 0.00562034 ; + } + pin(A_BIST_ADDR[1]) { + capacitance : 0.00462655 ; + } + pin(A_BIST_ADDR[2]) { + capacitance : 0.00594295 ; + } + pin(A_BIST_ADDR[3]) { + capacitance : 0.00723434 ; + } + pin(A_BIST_ADDR[4]) { + capacitance : 0.00481603 ; + } + pin(A_BIST_ADDR[5]) { + capacitance : 0.00868123 ; + } + pin(A_BIST_ADDR[6]) { + capacitance : 0.010187 ; + } + pin(A_BIST_ADDR[7]) { + capacitance : 0.00734489 ; + } + max_transition : "0.38" ; + pin(A_BIST_ADDR[8:0]) { + related_power_pin : VDD; + related_ground_pin : VSS; + internal_power() { + when : "A_BIST_MEN"; + rise_power("scalar"){ + values (0.1447); + } + fall_power("scalar"){ + values (0.0095); + } + } + internal_power() { + when : "!A_BIST_MEN"; + rise_power("scalar"){ + values (0.0256); + } + fall_power("scalar"){ + values (0.0000); + } + } + } + timing() { + timing_type : setup_rising; + related_pin : "A_BIST_CLK"; + when : "((A_BIST_WEN | A_BIST_REN)& A_BIST_MEN)" + sdf_cond : "A_BIST_RW_ACCESS" + + rise_constraint("SIG2SRAM_constraint_template") { + index_1("0.0040,0.0176,0.0344,0.0656,0.1120,0.2016,0.3800"); + index_2("0.0040,0.0176,0.0344,0.0656,0.1120,0.2016,0.3800"); + values ("-0.2371,-0.2215,-0.2098,-0.1824,-0.1434,-0.0691,0.0676",\ +"-0.2449,-0.2332,-0.2176,-0.1902,-0.1551,-0.0770,0.0559",\ +"-0.2605,-0.2488,-0.2332,-0.2059,-0.1707,-0.0965,0.0441",\ +"-0.2879,-0.2723,-0.2605,-0.2332,-0.1941,-0.1199,0.0168",\ +"-0.3230,-0.3113,-0.2996,-0.2723,-0.2332,-0.1590,-0.0184",\ +"-0.4012,-0.3895,-0.3738,-0.3465,-0.3074,-0.2332,-0.0965",\ +"-0.5379,-0.5262,-0.5105,-0.4832,-0.4480,-0.3699,-0.2332"); + } + + fall_constraint("SIG2SRAM_constraint_template") { + index_1("0.0040,0.0176,0.0344,0.0656,0.1120,0.2016,0.3800"); + index_2("0.0040,0.0176,0.0344,0.0656,0.1120,0.2016,0.3800"); + values ("-0.1785,-0.1707,-0.1551,-0.1277,-0.0887,-0.0184,0.1145",\ +"-0.1902,-0.1785,-0.1629,-0.1355,-0.1004,-0.0262,0.1027",\ +"-0.2059,-0.1941,-0.1785,-0.1512,-0.1160,-0.0418,0.0871",\ +"-0.2293,-0.2176,-0.2059,-0.1785,-0.1434,-0.0691,0.0598",\ +"-0.2684,-0.2566,-0.2449,-0.2176,-0.1824,-0.1082,0.0207",\ +"-0.3465,-0.3348,-0.3191,-0.2918,-0.2566,-0.1824,-0.0535",\ +"-0.4832,-0.4715,-0.4559,-0.4324,-0.3934,-0.3191,-0.1902"); + } + } + + + timing() { + timing_type : hold_rising; + related_pin : "A_BIST_CLK"; + when : "((A_BIST_WEN | A_BIST_REN)& A_BIST_MEN)" + sdf_cond : "A_BIST_RW_ACCESS" + + rise_constraint("SIG2SRAM_constraint_template") { + index_1("0.0040,0.0176,0.0344,0.0656,0.1120,0.2016,0.3800"); + index_2("0.0040,0.0176,0.0344,0.0656,0.1120,0.2016,0.3800"); + values ("0.3410,0.3293,0.3137,0.2863,0.2473,0.1730,0.0324",\ +"0.3488,0.3371,0.3215,0.2941,0.2590,0.1809,0.0480",\ +"0.3684,0.3527,0.3371,0.3098,0.2746,0.1965,0.0598",\ +"0.3918,0.3762,0.3645,0.3371,0.2980,0.2238,0.0871",\ +"0.4309,0.4152,0.4035,0.3762,0.3371,0.2629,0.1223",\ +"0.5051,0.4934,0.4777,0.4504,0.4113,0.3371,0.1965",\ +"0.6418,0.6262,0.6145,0.5871,0.5520,0.4738,0.3332"); + } + + fall_constraint("SIG2SRAM_constraint_template") { + index_1("0.0040,0.0176,0.0344,0.0656,0.1120,0.2016,0.3800"); + index_2("0.0040,0.0176,0.0344,0.0656,0.1120,0.2016,0.3800"); + values ("0.2824,0.2707,0.2551,0.2277,0.1926,0.1184,-0.0105",\ +"0.2902,0.2785,0.2668,0.2395,0.2043,0.1301,0.0012",\ +"0.3059,0.2941,0.2824,0.2551,0.2199,0.1457,0.0168",\ +"0.3332,0.3215,0.3059,0.2785,0.2434,0.1691,0.0402",\ +"0.3723,0.3605,0.3449,0.3176,0.2824,0.2121,0.0793",\ +"0.4465,0.4348,0.4230,0.3918,0.3566,0.2824,0.1535",\ +"0.5832,0.5715,0.5598,0.5324,0.4934,0.4191,0.2902"); + } + } +} +pin(A_BIST_WEN) { + direction : input ; + capacitance : 0.00341384 ; + max_transition : "0.38" ; + related_power_pin : VDD; + related_ground_pin : VSS; + internal_power() { + when : "A_BIST_MEN"; + rise_power("scalar"){ + values (0.0064); + } + fall_power("scalar"){ + values (0.0158); + } + } + internal_power() { + when : "!A_BIST_MEN"; + rise_power("scalar"){ + values (0.0047); + } + fall_power("scalar"){ + values (0.0213); + } + } + timing() { + timing_type : setup_rising; + related_pin : "A_BIST_CLK"; + when : "A_BIST_MEN" + sdf_cond : "A_BIST_MEN" + + rise_constraint("SIG2SRAM_constraint_template") { + index_1("0.0040,0.0176,0.0344,0.0656,0.1120,0.2016,0.3800"); + index_2("0.0040,0.0176,0.0344,0.0656,0.1120,0.2016,0.3800"); + values ("0.1418,0.1496,0.1652,0.1887,0.2316,0.3059,0.4465",\ +"0.1301,0.1379,0.1535,0.1809,0.2199,0.2941,0.4348",\ +"0.1145,0.1262,0.1379,0.1652,0.2043,0.2785,0.4191",\ +"0.0871,0.0949,0.1105,0.1379,0.1770,0.2512,0.3879",\ +"0.0480,0.0598,0.0754,0.0988,0.1379,0.2082,0.3527",\ +"-0.0262,-0.0145,0.0012,0.0246,0.0676,0.1379,0.2785",\ +"-0.1668,-0.1551,-0.1395,-0.1121,-0.0730,0.0012,0.1418"); + } + + fall_constraint("SIG2SRAM_constraint_template") { + index_1("0.0040,0.0176,0.0344,0.0656,0.1120,0.2016,0.3800"); + index_2("0.0040,0.0176,0.0344,0.0656,0.1120,0.2016,0.3800"); + values ("0.2082,0.2160,0.2316,0.2590,0.2941,0.3684,0.5012",\ +"0.1926,0.2043,0.2199,0.2473,0.2824,0.3566,0.4895",\ +"0.1770,0.1887,0.2043,0.2316,0.2668,0.3410,0.4777",\ +"0.1535,0.1652,0.1770,0.2043,0.2395,0.3137,0.4504",\ +"0.1145,0.1262,0.1379,0.1652,0.2043,0.2746,0.4113",\ +"0.0402,0.0520,0.0676,0.0910,0.1262,0.2004,0.3332",\ +"-0.0965,-0.0848,-0.0730,-0.0457,-0.0066,0.0637,0.2004"); + } + } + + + timing() { + timing_type : hold_rising; + related_pin : "A_BIST_CLK"; + when : "A_BIST_MEN" + sdf_cond : "A_BIST_MEN" + + rise_constraint("SIG2SRAM_constraint_template") { + index_1("0.0040,0.0176,0.0344,0.0656,0.1120,0.2016,0.3800"); + index_2("0.0040,0.0176,0.0344,0.0656,0.1120,0.2016,0.3800"); + values ("0.1770,0.1652,0.1496,0.1223,0.0793,0.0090,-0.1316",\ +"0.1848,0.1730,0.1574,0.1301,0.0910,0.0168,-0.1199",\ +"0.2004,0.1887,0.1770,0.1496,0.1066,0.0363,-0.1043",\ +"0.2277,0.2160,0.2004,0.1730,0.1340,0.0598,-0.0809",\ +"0.2668,0.2551,0.2395,0.2121,0.1730,0.0988,-0.0418",\ +"0.3410,0.3293,0.3137,0.2863,0.2434,0.1730,0.0324",\ +"0.4816,0.4699,0.4543,0.4230,0.3801,0.3098,0.1730"); + } + + fall_constraint("SIG2SRAM_constraint_template") { + index_1("0.0040,0.0176,0.0344,0.0656,0.1120,0.2016,0.3800"); + index_2("0.0040,0.0176,0.0344,0.0656,0.1120,0.2016,0.3800"); + values ("0.1613,0.1496,0.1379,0.1066,0.0715,0.0012,-0.1355",\ +"0.1730,0.1613,0.1457,0.1184,0.0832,0.0129,-0.1238",\ +"0.1887,0.1770,0.1613,0.1340,0.0988,0.0246,-0.1121",\ +"0.2121,0.2043,0.1887,0.1613,0.1223,0.0520,-0.0848",\ +"0.2512,0.2434,0.2277,0.2004,0.1613,0.0910,-0.0457",\ +"0.3254,0.3176,0.3020,0.2746,0.2355,0.1652,0.0324",\ +"0.4660,0.4543,0.4387,0.4113,0.3723,0.3020,0.1691"); + } + } + } +pin(A_BIST_REN) { + direction : input ; + capacitance : 0.00390661 ; + max_transition : "0.38" ; + related_power_pin : VDD; + related_ground_pin : VSS; + internal_power() { + when : "A_BIST_MEN"; + rise_power("scalar"){ + values (0.0098); + } + fall_power("scalar"){ + values (0.0114); + } + } + internal_power() { + when : "!A_BIST_MEN"; + rise_power("scalar"){ + values (0.0251); + } + fall_power("scalar"){ + values (0.0208); + } + } + timing() { + timing_type : setup_rising; + related_pin : "A_BIST_CLK"; + when : "A_BIST_MEN" + sdf_cond : "A_BIST_MEN" + + rise_constraint("SIG2SRAM_constraint_template") { + index_1("0.0040,0.0176,0.0344,0.0656,0.1120,0.2016,0.3800"); + index_2("0.0040,0.0176,0.0344,0.0656,0.1120,0.2016,0.3800"); + values ("-0.0027,0.0090,0.0246,0.0520,0.0910,0.1613,0.3020",\ +"-0.0105,0.0012,0.0129,0.0363,0.0793,0.1535,0.2902",\ +"-0.0262,-0.0145,-0.0027,0.0246,0.0637,0.1379,0.2785",\ +"-0.0535,-0.0418,-0.0262,0.0012,0.0363,0.1105,0.2512",\ +"-0.0926,-0.0809,-0.0652,-0.0418,-0.0027,0.0715,0.2121",\ +"-0.1668,-0.1551,-0.1395,-0.1082,-0.0770,-0.0027,0.1379",\ +"-0.3035,-0.2918,-0.2762,-0.2488,-0.2137,-0.1434,-0.0027"); + } + + fall_constraint("SIG2SRAM_constraint_template") { + index_1("0.0040,0.0176,0.0344,0.0656,0.1120,0.2016,0.3800"); + index_2("0.0040,0.0176,0.0344,0.0656,0.1120,0.2016,0.3800"); + values ("0.0832,0.0949,0.1105,0.1379,0.1730,0.2473,0.3801",\ +"0.0754,0.0832,0.0988,0.1223,0.1613,0.2355,0.3684",\ +"0.0598,0.0676,0.0832,0.1066,0.1457,0.2121,0.3527",\ +"0.0324,0.0441,0.0598,0.0871,0.1223,0.1926,0.3293",\ +"-0.0066,0.0051,0.0168,0.0480,0.0832,0.1535,0.2902",\ +"-0.0809,-0.0691,-0.0574,-0.0301,0.0090,0.0832,0.2121",\ +"-0.2176,-0.2059,-0.1941,-0.1668,-0.1277,-0.0574,0.0793"); + } + } + + + timing() { + timing_type : hold_rising; + related_pin : "A_BIST_CLK"; + when : "A_BIST_MEN" + sdf_cond : "A_BIST_MEN" + + rise_constraint("SIG2SRAM_constraint_template") { + index_1("0.0040,0.0176,0.0344,0.0656,0.1120,0.2016,0.3800"); + index_2("0.0040,0.0176,0.0344,0.0656,0.1120,0.2016,0.3800"); + values ("0.1887,0.1770,0.1613,0.1340,0.0949,0.0207,-0.1160",\ +"0.1965,0.1848,0.1730,0.1457,0.1027,0.0324,-0.1082",\ +"0.2160,0.2004,0.1887,0.1613,0.1184,0.0480,-0.0926",\ +"0.2395,0.2277,0.2121,0.1848,0.1457,0.0715,-0.0652",\ +"0.2785,0.2668,0.2512,0.2238,0.1848,0.1105,-0.0262",\ +"0.3527,0.3410,0.3254,0.2980,0.2551,0.1848,0.0480",\ +"0.4934,0.4816,0.4660,0.4387,0.3957,0.3254,0.1887"); + } + + fall_constraint("SIG2SRAM_constraint_template") { + index_1("0.0040,0.0176,0.0344,0.0656,0.1120,0.2016,0.3800"); + index_2("0.0040,0.0176,0.0344,0.0656,0.1120,0.2016,0.3800"); + values ("0.1730,0.1613,0.1496,0.1184,0.0793,0.0129,-0.1238",\ +"0.1848,0.1730,0.1574,0.1301,0.0910,0.0207,-0.1121",\ +"0.2004,0.1887,0.1730,0.1457,0.1066,0.0363,-0.1004",\ +"0.2238,0.2121,0.2004,0.1691,0.1340,0.0598,-0.0730",\ +"0.2629,0.2512,0.2395,0.2121,0.1691,0.0988,-0.0340",\ +"0.3371,0.3254,0.3137,0.2863,0.2434,0.1730,0.0402",\ +"0.4777,0.4660,0.4504,0.4230,0.3840,0.3137,0.1809"); + } + } + } +pin(A_BIST_MEN) { + direction : input ; + capacitance : 0.00326046 ; + max_transition : "0.38" ; + related_power_pin : VDD; + related_ground_pin : VSS; + internal_power() { + rise_power("scalar"){ + values (0.0779); + } + fall_power("scalar"){ + values (0.0819); + } + } + timing() { + timing_type : setup_rising; + related_pin : "A_BIST_CLK"; + + rise_constraint("SIG2SRAM_constraint_template") { + index_1("0.0040,0.0176,0.0344,0.0656,0.1120,0.2016,0.3800"); + index_2("0.0040,0.0176,0.0344,0.0656,0.1120,0.2016,0.3800"); + values ("0.1418,0.1496,0.1652,0.1926,0.2316,0.3059,0.4465",\ +"0.1301,0.1379,0.1535,0.1809,0.2199,0.2941,0.4348",\ +"0.1145,0.1262,0.1418,0.1652,0.2043,0.2785,0.4191",\ +"0.0871,0.0949,0.1105,0.1379,0.1770,0.2512,0.3879",\ +"0.0480,0.0598,0.0754,0.0988,0.1379,0.2082,0.3488",\ +"-0.0262,-0.0145,0.0012,0.0285,0.0676,0.1379,0.2785",\ +"-0.1668,-0.1551,-0.1395,-0.1121,-0.0730,0.0012,0.1379"); + } + + fall_constraint("SIG2SRAM_constraint_template") { + index_1("0.0040,0.0176,0.0344,0.0656,0.1120,0.2016,0.3800"); + index_2("0.0040,0.0176,0.0344,0.0656,0.1120,0.2016,0.3800"); + values ("0.2082,0.2199,0.2316,0.2590,0.2980,0.3723,0.5051",\ +"0.1965,0.2082,0.2199,0.2473,0.2863,0.3605,0.4934",\ +"0.1809,0.1926,0.2043,0.2316,0.2707,0.3449,0.4777",\ +"0.1574,0.1691,0.1809,0.2082,0.2434,0.3176,0.4543",\ +"0.1145,0.1262,0.1418,0.1691,0.2043,0.2785,0.4113",\ +"0.0441,0.0559,0.0676,0.0949,0.1301,0.2004,0.3332",\ +"-0.0965,-0.0848,-0.0691,-0.0418,-0.0066,0.0676,0.2004"); + } + } + + + timing() { + timing_type : hold_rising; + related_pin : "A_BIST_CLK"; + + rise_constraint("SIG2SRAM_constraint_template") { + index_1("0.0040,0.0176,0.0344,0.0656,0.1120,0.2016,0.3800"); + index_2("0.0040,0.0176,0.0344,0.0656,0.1120,0.2016,0.3800"); + values ("0.1770,0.1652,0.1535,0.1262,0.0832,0.0129,-0.1277",\ +"0.1887,0.1770,0.1613,0.1340,0.0949,0.0207,-0.1199",\ +"0.2043,0.1926,0.1770,0.1496,0.1105,0.0363,-0.1043",\ +"0.2277,0.2160,0.2043,0.1770,0.1379,0.0598,-0.0770",\ +"0.2668,0.2551,0.2434,0.2160,0.1730,0.0988,-0.0379",\ +"0.3449,0.3332,0.3176,0.2902,0.2473,0.1730,0.0363",\ +"0.4816,0.4699,0.4543,0.4270,0.3840,0.3098,0.1770"); + } + + fall_constraint("SIG2SRAM_constraint_template") { + index_1("0.0040,0.0176,0.0344,0.0656,0.1120,0.2016,0.3800"); + index_2("0.0040,0.0176,0.0344,0.0656,0.1120,0.2016,0.3800"); + values ("0.1613,0.1496,0.1379,0.1105,0.0715,0.0012,-0.1355",\ +"0.1730,0.1613,0.1496,0.1184,0.0832,0.0129,-0.1238",\ +"0.1887,0.1770,0.1652,0.1340,0.0988,0.0285,-0.1121",\ +"0.2121,0.2043,0.1887,0.1613,0.1223,0.0520,-0.0848",\ +"0.2551,0.2434,0.2277,0.2004,0.1613,0.0910,-0.0418",\ +"0.3293,0.3176,0.3020,0.2746,0.2395,0.1652,0.0324",\ +"0.4660,0.4543,0.4426,0.4113,0.3762,0.3020,0.1691"); + } + } + } +bus(A_BIST_BM) { + bus_type : D_7_0; + direction : input ; + capacitance : 0.00252172 ; + max_transition : "0.38" ; + pin(A_BIST_BM[7:0]) { + related_power_pin : VDD; + related_ground_pin : VSS; + internal_power() { + when : "A_BIST_MEN"; + rise_power("scalar"){ + values (0.0370); + } + fall_power("scalar"){ + values (0.0444); + } + } + internal_power() { + when : "!A_BIST_MEN"; + rise_power("scalar"){ + values (0.0531); + } + fall_power("scalar"){ + values (0.0511); + } + } + } + timing() { + timing_type : setup_rising; + related_pin : "A_BIST_CLK"; + when : "(A_BIST_WEN & A_BIST_MEN)" + sdf_cond : "A_BIST_RW_ACCESS" + + rise_constraint("SIG2SRAM_constraint_template") { + index_1("0.0040,0.0176,0.0344,0.0656,0.1120,0.2016,0.3800"); + index_2("0.0040,0.0176,0.0344,0.0656,0.1120,0.2016,0.3800"); + values ("-0.1742,-0.1634,-0.1478,-0.1224,-0.0814,-0.0082,0.1266",\ +"-0.1781,-0.1673,-0.1517,-0.1263,-0.0853,-0.0121,0.1227",\ +"-0.1817,-0.1710,-0.1554,-0.1300,-0.0890,-0.0157,0.1190",\ +"-0.1850,-0.1742,-0.1586,-0.1332,-0.0922,-0.0189,0.1158",\ +"-0.1976,-0.1868,-0.1712,-0.1458,-0.1048,-0.0315,0.1032",\ +"-0.2152,-0.2044,-0.1888,-0.1634,-0.1224,-0.0492,0.0856",\ +"-0.2427,-0.2319,-0.2163,-0.1909,-0.1499,-0.0767,0.0581"); + } + + fall_constraint("SIG2SRAM_constraint_template") { + index_1("0.0040,0.0176,0.0344,0.0656,0.1120,0.2016,0.3800"); + index_2("0.0040,0.0176,0.0344,0.0656,0.1120,0.2016,0.3800"); + values ("-0.1507,-0.1390,-0.1263,-0.0990,-0.0619,0.0114,0.1393",\ +"-0.1546,-0.1429,-0.1302,-0.1029,-0.0658,0.0075,0.1354",\ +"-0.1583,-0.1466,-0.1339,-0.1065,-0.0694,0.0038,0.1317",\ +"-0.1615,-0.1498,-0.1371,-0.1098,-0.0726,0.0006,0.1285",\ +"-0.1741,-0.1624,-0.1497,-0.1224,-0.0853,-0.0120,0.1159",\ +"-0.1917,-0.1800,-0.1673,-0.1400,-0.1029,-0.0296,0.0983",\ +"-0.2192,-0.2075,-0.1948,-0.1675,-0.1304,-0.0571,0.0708"); + } + } + + + timing() { + timing_type : hold_rising; + related_pin : "A_BIST_CLK"; + when : "(A_BIST_WEN & A_BIST_MEN)" + sdf_cond : "A_BIST_RW_ACCESS" + + rise_constraint("SIG2SRAM_constraint_template") { + index_1("0.0040,0.0176,0.0344,0.0656,0.1120,0.2016,0.3800"); + index_2("0.0040,0.0176,0.0344,0.0656,0.1120,0.2016,0.3800"); + values ("0.2792,0.2694,0.2538,0.2274,0.1903,0.1161,-0.0187",\ +"0.2830,0.2733,0.2577,0.2313,0.1942,0.1200,-0.0148",\ +"0.2867,0.2770,0.2613,0.2350,0.1979,0.1236,-0.0111",\ +"0.2899,0.2802,0.2645,0.2382,0.2011,0.1268,-0.0079",\ +"0.3025,0.2928,0.2772,0.2508,0.2137,0.1395,0.0047",\ +"0.3202,0.3104,0.2948,0.2684,0.2313,0.1571,0.0223",\ +"0.3477,0.3379,0.3223,0.2959,0.2588,0.1846,0.0498"); + } + + fall_constraint("SIG2SRAM_constraint_template") { + index_1("0.0040,0.0176,0.0344,0.0656,0.1120,0.2016,0.3800"); + index_2("0.0040,0.0176,0.0344,0.0656,0.1120,0.2016,0.3800"); + values ("0.2508,0.2401,0.2264,0.1991,0.1630,0.0907,-0.0392",\ +"0.2547,0.2440,0.2303,0.2030,0.1668,0.0946,-0.0353",\ +"0.2584,0.2477,0.2340,0.2066,0.1705,0.0983,-0.0316",\ +"0.2616,0.2509,0.2372,0.2098,0.1737,0.1015,-0.0284",\ +"0.2742,0.2635,0.2498,0.2225,0.1863,0.1141,-0.0158",\ +"0.2918,0.2811,0.2674,0.2401,0.2039,0.1317,0.0018",\ +"0.3193,0.3086,0.2949,0.2676,0.2314,0.1592,0.0293"); + } + } +} + pin(A_BIST_CLK) { + direction : input; + capacitance : 0.00389386; + max_transition : "0.38"; + clock : "true" ; + pin_func_type : active_rising ; + + timing () { + timing_type : "min_pulse_width"; + related_pin : "A_BIST_CLK"; + rise_constraint("CLKTRAN_constraint_template") { + index_1("0.004,0.38"); + values("0.12,0.12"); + } + } + + related_power_pin : VDD; + related_ground_pin : VSS; + + internal_power() { + when : "!A_BIST_MEN & !A_BIST_WEN & !A_BIST_REN"; + rise_power("scalar"){ + values (0); + } + fall_power("scalar"){ + values (0); + } + } + internal_power() { + when : "!A_BIST_MEN & A_BIST_WEN & !A_BIST_REN"; + rise_power("scalar"){ + values (0.6302); + } + fall_power("scalar"){ + values (0); + } + } + internal_power() { + when : "A_BIST_MEN & A_BIST_WEN & !A_BIST_REN"; + rise_power("scalar"){ + values (19.4264); + } + fall_power("scalar"){ + values (0); + } + } + internal_power() { + when : "A_BIST_MEN & A_BIST_WEN & A_BIST_REN"; + rise_power("scalar"){ + values (19.1463); + } + fall_power("scalar"){ + values (0); + } + } + internal_power() { + when : "A_BIST_MEN & !A_BIST_WEN & A_BIST_REN"; + rise_power("scalar"){ + values (14.6404); + } + fall_power("scalar"){ + values (0); + } + } + internal_power() { + when : "!A_BIST_MEN & !A_BIST_WEN & A_BIST_REN"; + rise_power("scalar"){ + values (0.3917); + } + fall_power("scalar"){ + values (0); + } + } + internal_power() { + when : "!A_BIST_MEN & A_BIST_WEN & A_BIST_REN"; + rise_power("scalar"){ + values (0.6655); + } + fall_power("scalar"){ + values (0); + } + } + internal_power() { + when : "A_BIST_MEN & !A_BIST_WEN & !A_BIST_REN"; + rise_power("scalar"){ + values (0); + } + fall_power("scalar"){ + values (0); + } + } + } + bus(A_BIST_DIN) { + bus_type : D_7_0; + direction : input ; + capacitance : 0.00252023 ; + memory_write() { + address : A_BIST_ADDR ; + clocked_on : A_BIST_CLK; + } + + max_transition : "0.38" ; + pin(A_BIST_DIN[7:0]) { + related_power_pin : VDD; + related_ground_pin : VSS; + internal_power() { + when : "A_BIST_MEN"; + rise_power("scalar"){ + values (0.0370); + } + fall_power("scalar"){ + values (0.0444); + } + } + internal_power() { + when : "!A_BIST_MEN"; + rise_power("scalar"){ + values (0.0531); + } + fall_power("scalar"){ + values (0.0511); + } + } + } + timing() { + timing_type : setup_rising; + related_pin : "A_BIST_CLK"; + when : "(A_BIST_WEN & A_BIST_MEN)"; + sdf_cond : "A_BIST_W_ACCESS"; + + rise_constraint("SIG2SRAM_constraint_template") { + index_1("0.0040,0.0176,0.0344,0.0656,0.1120,0.2016,0.3800"); + index_2("0.0040,0.0176,0.0344,0.0656,0.1120,0.2016,0.3800"); + values ("-0.1742,-0.1634,-0.1478,-0.1224,-0.0814,-0.0082,0.1266",\ +"-0.1781,-0.1673,-0.1517,-0.1263,-0.0853,-0.0121,0.1227",\ +"-0.1817,-0.1710,-0.1554,-0.1300,-0.0890,-0.0157,0.1190",\ +"-0.1850,-0.1742,-0.1586,-0.1332,-0.0922,-0.0189,0.1158",\ +"-0.1976,-0.1868,-0.1712,-0.1458,-0.1048,-0.0315,0.1032",\ +"-0.2152,-0.2044,-0.1888,-0.1634,-0.1224,-0.0492,0.0856",\ +"-0.2427,-0.2319,-0.2163,-0.1909,-0.1499,-0.0767,0.0581"); + } + + fall_constraint("SIG2SRAM_constraint_template") { + index_1("0.0040,0.0176,0.0344,0.0656,0.1120,0.2016,0.3800"); + index_2("0.0040,0.0176,0.0344,0.0656,0.1120,0.2016,0.3800"); + values ("-0.1507,-0.1390,-0.1263,-0.0990,-0.0619,0.0114,0.1393",\ +"-0.1546,-0.1429,-0.1302,-0.1029,-0.0658,0.0075,0.1354",\ +"-0.1583,-0.1466,-0.1339,-0.1065,-0.0694,0.0038,0.1317",\ +"-0.1615,-0.1498,-0.1371,-0.1098,-0.0726,0.0006,0.1285",\ +"-0.1741,-0.1624,-0.1497,-0.1224,-0.0853,-0.0120,0.1159",\ +"-0.1917,-0.1800,-0.1673,-0.1400,-0.1029,-0.0296,0.0983",\ +"-0.2192,-0.2075,-0.1948,-0.1675,-0.1304,-0.0571,0.0708"); + } + } + + timing() { + timing_type : hold_rising; + related_pin : "A_BIST_CLK"; + when : "(A_BIST_WEN & A_BIST_MEN)"; + sdf_cond : "A_BIST_W_ACCESS"; + + rise_constraint("SIG2SRAM_constraint_template") { + index_1("0.0040,0.0176,0.0344,0.0656,0.1120,0.2016,0.3800"); + index_2("0.0040,0.0176,0.0344,0.0656,0.1120,0.2016,0.3800"); + values ("0.2792,0.2694,0.2538,0.2274,0.1903,0.1161,-0.0187",\ +"0.2830,0.2733,0.2577,0.2313,0.1942,0.1200,-0.0148",\ +"0.2867,0.2770,0.2613,0.2350,0.1979,0.1236,-0.0111",\ +"0.2899,0.2802,0.2645,0.2382,0.2011,0.1268,-0.0079",\ +"0.3025,0.2928,0.2772,0.2508,0.2137,0.1395,0.0047",\ +"0.3202,0.3104,0.2948,0.2684,0.2313,0.1571,0.0223",\ +"0.3477,0.3379,0.3223,0.2959,0.2588,0.1846,0.0498"); + } + + fall_constraint("SIG2SRAM_constraint_template") { + index_1("0.0040,0.0176,0.0344,0.0656,0.1120,0.2016,0.3800"); + index_2("0.0040,0.0176,0.0344,0.0656,0.1120,0.2016,0.3800"); + values ("0.2508,0.2401,0.2264,0.1991,0.1630,0.0907,-0.0392",\ +"0.2547,0.2440,0.2303,0.2030,0.1668,0.0946,-0.0353",\ +"0.2584,0.2477,0.2340,0.2066,0.1705,0.0983,-0.0316",\ +"0.2616,0.2509,0.2372,0.2098,0.1737,0.1015,-0.0284",\ +"0.2742,0.2635,0.2498,0.2225,0.1863,0.1141,-0.0158",\ +"0.2918,0.2811,0.2674,0.2401,0.2039,0.1317,0.0018",\ +"0.3193,0.3086,0.2949,0.2676,0.2314,0.1592,0.0293"); + } + } + } + +bus(A_DOUT) { + + bus_type : D_7_0; + direction : output ; + capacitance : 0 ; + max_capacitance : 0.064 ; + memory_read() { + address : A_ADDR ; + } + pin(A_DOUT[7:0]) { + related_power_pin : VDD; + related_ground_pin : VSS; + internal_power() { + rise_power("scalar") { + values (0); + } + fall_power("scalar") { + values (0); + } + } + } + timing() { + related_pin : "A_CLK"; + timing_type : rising_edge ; + timing_sense : non_unate ; + + cell_rise(SIG2SRAM_delay_template) { + index_1("0.0040,0.0176,0.0344,0.0656,0.1120,0.2016,0.3800"); + index_2("0.0008,0.0014,0.0051,0.0100,0.0339,0.0640"); + values ("1.8175,1.8185,1.8233,1.8288,1.8497,1.8732",\ +"1.8234,1.8245,1.8293,1.8348,1.8557,1.8792",\ +"1.8262,1.8272,1.8320,1.8375,1.8584,1.8819",\ +"1.8304,1.8314,1.8362,1.8417,1.8627,1.8862",\ +"1.8420,1.8430,1.8478,1.8534,1.8743,1.8978",\ +"1.8611,1.8621,1.8670,1.8725,1.8934,1.9169",\ +"1.8875,1.8885,1.8933,1.8989,1.9198,1.9433"); + } + cell_fall(SIG2SRAM_delay_template) { + index_1("0.0040,0.0176,0.0344,0.0656,0.1120,0.2016,0.3800"); + index_2("0.0008,0.0014,0.0051,0.0100,0.0339,0.0640"); + values ("1.7832,1.7841,1.7881,1.7926,1.8097,1.8265",\ +"1.7892,1.7900,1.7941,1.7986,1.8157,1.8324",\ +"1.7919,1.7928,1.7968,1.8013,1.8184,1.8352",\ +"1.7961,1.7970,1.8010,1.8056,1.8227,1.8394",\ +"1.8077,1.8086,1.8126,1.8172,1.8343,1.8510",\ +"1.8269,1.8277,1.8317,1.8363,1.8534,1.8701",\ +"1.8532,1.8541,1.8581,1.8627,1.8798,1.8965"); + } + + rise_transition(SRAM_load_template) { + index_1("0.0008,0.0014,0.0051,0.0100,0.0339,0.0640"); + values ("0.0206,0.0210,0.0265,0.0323,0.0606,0.0955"); + } + fall_transition(SRAM_load_template) { + index_1("0.0008,0.0014,0.0051,0.0100,0.0339,0.0640"); + values ("0.0170,0.0177,0.0222,0.0270,0.0451,0.0644"); + } + } +} +cell_leakage_power : 117.3985; +} +} diff --git a/flow/platforms/ihp-sg13g2/lib/RM_IHPSG13_1P_512x8_c3_bm_bist_slow_1p08V_125C.lib b/flow/platforms/ihp-sg13g2/lib/RM_IHPSG13_1P_512x8_c3_bm_bist_slow_1p08V_125C.lib new file mode 100644 index 0000000000..ecab035578 --- /dev/null +++ b/flow/platforms/ihp-sg13g2/lib/RM_IHPSG13_1P_512x8_c3_bm_bist_slow_1p08V_125C.lib @@ -0,0 +1,1519 @@ +/* ------------------------------------------------------*/ +/**/ +/* Copyright 2025 IHP PDK Authors*/ +/**/ +/* Licensed under the Apache License, Version 2.0 (the "License");*/ +/* you may not use this file except in compliance with the License.*/ +/* You may obtain a copy of the License at*/ +/* */ +/* https://www.apache.org/licenses/LICENSE-2.0*/ +/* */ +/* Unless required by applicable law or agreed to in writing, software*/ +/* distributed under the License is distributed on an "AS IS" BASIS,*/ +/* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.*/ +/* See the License for the specific language governing permissions and*/ +/* limitations under the License.*/ +/* */ +/* Generated on Wed Aug 27 16:20:19 2025 */ +/* */ +/* ------------------------------------------------------ */ +library(RM_IHPSG13_1P_512x8_c3_bm_bist_slow_1p08V_125C) { + technology (cmos) ; + delay_model : table_lookup ; + define ("add_pg_pin_to_lib", "library", "boolean"); + add_pg_pin_to_lib : true; + voltage_map ( VDD, 1.08); + voltage_map ( VDDARRAY, 1.08); + voltage_map ( VSS, 0.000000 ); + + date : "Wed Aug 27 16:20:18 2025" ; + comment : "IHP Microelectronics GmbH, 2023" ; + revision : 1.0.0 ; + simulation : true ; + nom_process : 1 ; + nom_temperature : 125 ; + nom_voltage : 1.08 ; + + operating_conditions("slow_1p08V_125C"){ + process : 1 ; + temperature : 125 ; + voltage : 1.08 ; + tree_type : "balanced_tree" ; + } + + default_operating_conditions : slow_1p08V_125C ; + default_max_transition : 1.0 ; + default_fanout_load : 1.0 ; + default_inout_pin_cap : 0.0 ; + default_input_pin_cap : 0.0 ; + default_output_pin_cap : 0.0 ; + default_cell_leakage_power : 0.0 ; + default_leakage_power_density : 0.0 ; + + slew_lower_threshold_pct_rise : 30 ; + slew_upper_threshold_pct_rise : 70 ; + input_threshold_pct_fall : 50 ; + output_threshold_pct_fall : 50 ; + input_threshold_pct_rise : 50 ; + output_threshold_pct_rise : 50 ; + slew_lower_threshold_pct_fall : 30 ; + slew_upper_threshold_pct_fall : 70 ; + slew_derate_from_library : 0.5; + k_volt_cell_leakage_power : 0.0 ; + k_temp_cell_leakage_power : 0.0 ; + k_process_cell_leakage_power : 0.0 ; + k_volt_internal_power : 0.0 ; + k_temp_internal_power : 0.0 ; + k_process_internal_power : 0.0 ; + + capacitive_load_unit (1,pf) ; + voltage_unit : "1V" ; + current_unit : "1uA" ; + time_unit : "1ns" ; + leakage_power_unit : "1nW" ; + pulling_resistance_unit : "1kohm"; + /* + ------------------------------------------------------------------------------------------ + implicit units overview: + cell_area unit : "um" + internal_power unit : "1e-12 * J/toggle = 1 * uW/MHz" + (capacitive_load_unit * voltage_unit^2) per toggle event + ------------------------------------------------------------------------------------------ + */ + library_features(report_delay_calculation); + define_cell_area (pad_drivers,pad_driver_sites) ; + + lu_table_template(CLKTRAN_constraint_template) { + variable_1 : constrained_pin_transition; + index_1 ( "0.010, 0.050, 0.200, 0.400, 1.000" ); + } + lu_table_template(SRAM_load_template) { + variable_1 : total_output_net_capacitance; + index_1 ( "0.0008,0.0014,0.0051,0.0100,0.0339,0.0640" ); + } + lu_table_template(SIG2SRAM_constraint_template) { + variable_1 : related_pin_transition; + variable_2 : constrained_pin_transition; + index_1 ( "0.0080,0.0288,0.0616,0.1072,0.1920,0.3496,0.5952" ); + index_2 ( "0.0080,0.0288,0.0616,0.1072,0.1920,0.3496,0.5952" ); + } + + lu_table_template(SIG2SRAM_delay_template) { + variable_1 : input_net_transition; + variable_2 : total_output_net_capacitance; + index_1 ( "0.0080,0.0288,0.0616,0.1072,0.1920,0.3496,0.5952" ); + index_2 ( "0.0008,0.0014,0.0051,0.0100,0.0339,0.0640" ); + } + + type (D_7_0) { + base_type : array; + data_type : bit; + bit_width : 8; + bit_from : 7; + bit_to : 0; + downto : true; + } + + type (A_8_0) { + base_type : array; + data_type : bit; + bit_width : 9; + bit_from : 8; + bit_to : 0; + downto : true; + } + +cell(RM_IHPSG13_1P_512x8_c3_bm_bist) { +pg_pin (VDD) { + pg_type : primary_power; + voltage_name : VDD; +} +pg_pin (VDDARRAY) { + pg_type : primary_power; + voltage_name : VDDARRAY; +} +pg_pin (VSS) { + pg_type : primary_ground; + voltage_name : VSS; +} + +memory() { + type : ram; + address_width : 9; + word_width : 8; +} + +interface_timing : false; +bus_naming_style : "%s[%d]" ; +area : 26137.984 ; + + pin(A_DLY) { + direction : input ; + capacitance : 0.00387999 ; + max_transition : "1" ; + related_power_pin : VDD; + related_ground_pin : VSS; + internal_power() { + rise_power("scalar") { + values (0); + } + fall_power("scalar") { + values (0); + } + } + } + +bus(A_ADDR) { + bus_type : A_8_0; + direction : input ; + capacitance : 0.0077013 ; + pin(A_ADDR[0]) { + capacitance : 0.00625349 ; + } + pin(A_ADDR[1]) { + capacitance : 0.00507435 ; + } + pin(A_ADDR[2]) { + capacitance : 0.00656707 ; + } + pin(A_ADDR[3]) { + capacitance : 0.0083133 ; + } + pin(A_ADDR[4]) { + capacitance : 0.00507219 ; + } + pin(A_ADDR[5]) { + capacitance : 0.00964344 ; + } + pin(A_ADDR[6]) { + capacitance : 0.0119653 ; + } + pin(A_ADDR[7]) { + capacitance : 0.00827606 ; + } + max_transition : "0.5952" ; + pin(A_ADDR[8:0]) { + related_power_pin : VDD; + related_ground_pin : VSS; + internal_power() { + when : "A_MEN"; + rise_power("scalar"){ + values (0.0094); + } + fall_power("scalar"){ + values (0.0068); + } + } + internal_power() { + when : "!A_MEN"; + rise_power("scalar"){ + values (0.0133); + } + fall_power("scalar"){ + values (0.0021); + } + } + } + timing() { + timing_type : setup_rising; + related_pin : "A_CLK"; + when : "((A_WEN | A_REN)& A_MEN)" + sdf_cond : "A_RW_ACCESS" + + rise_constraint("SIG2SRAM_constraint_template") { + index_1("0.0080,0.0288,0.0616,0.1072,0.1920,0.3496,0.5952"); + index_2("0.0080,0.0288,0.0616,0.1072,0.1920,0.3496,0.5952"); + values ("-0.7371,-0.7176,-0.6863,-0.6434,-0.5652,-0.4168,-0.1980",\ +"-0.7566,-0.7371,-0.7059,-0.6629,-0.5848,-0.4363,-0.2137",\ +"-0.7879,-0.7645,-0.7332,-0.6902,-0.6121,-0.4637,-0.2449",\ +"-0.8309,-0.8074,-0.7762,-0.7332,-0.6551,-0.5066,-0.2879",\ +"-0.9051,-0.8895,-0.8543,-0.8113,-0.7332,-0.5887,-0.3660",\ +"-1.0418,-1.0262,-0.9949,-0.9480,-0.8699,-0.7293,-0.5027",\ +"-1.2684,-1.2449,-1.2176,-1.1707,-1.0965,-0.9480,-0.7293"); + } + + fall_constraint("SIG2SRAM_constraint_template") { + index_1("0.0080,0.0288,0.0616,0.1072,0.1920,0.3496,0.5952"); + index_2("0.0080,0.0288,0.0616,0.1072,0.1920,0.3496,0.5952"); + values ("-0.5926,-0.5730,-0.5418,-0.4988,-0.4246,-0.2879,-0.0730",\ +"-0.6121,-0.5926,-0.5613,-0.5223,-0.4441,-0.3074,-0.0887",\ +"-0.6395,-0.6199,-0.5926,-0.5496,-0.4715,-0.3348,-0.1160",\ +"-0.6863,-0.6668,-0.6355,-0.5965,-0.5184,-0.3777,-0.1590",\ +"-0.7605,-0.7410,-0.7137,-0.6746,-0.5926,-0.4559,-0.2410",\ +"-0.9012,-0.8816,-0.8504,-0.8113,-0.7332,-0.5926,-0.3895",\ +"-1.1238,-1.1043,-1.0769,-1.0379,-0.9559,-0.8191,-0.6004"); + } + } + + + timing() { + timing_type : hold_rising; + related_pin : "A_CLK"; + when : "((A_WEN | A_REN)& A_MEN)" + sdf_cond : "A_RW_ACCESS" + + rise_constraint("SIG2SRAM_constraint_template") { + index_1("0.0080,0.0288,0.0616,0.1072,0.1920,0.3496,0.5952"); + index_2("0.0080,0.0288,0.0616,0.1072,0.1920,0.3496,0.5952"); + values ("0.8488,0.8293,0.7980,0.7551,0.6730,0.5285,0.3059",\ +"0.8684,0.8488,0.8176,0.7746,0.6926,0.5480,0.3254",\ +"0.8996,0.8801,0.8449,0.8020,0.7238,0.5754,0.3527",\ +"0.9426,0.9191,0.8918,0.8488,0.7668,0.6223,0.3996",\ +"1.0168,1.0012,0.9699,0.9230,0.8449,0.7004,0.4777",\ +"1.1574,1.1379,1.1105,1.0598,0.9816,0.8371,0.6184",\ +"1.3801,1.3605,1.3254,1.2980,1.2043,1.0637,0.8371"); + } + + fall_constraint("SIG2SRAM_constraint_template") { + index_1("0.0080,0.0288,0.0616,0.1072,0.1920,0.3496,0.5952"); + index_2("0.0080,0.0288,0.0616,0.1072,0.1920,0.3496,0.5952"); + values ("0.6965,0.6770,0.6496,0.6066,0.5246,0.3918,0.1730",\ +"0.7160,0.6965,0.6652,0.6262,0.5441,0.4113,0.1965",\ +"0.7473,0.7277,0.6965,0.6535,0.5754,0.4426,0.2238",\ +"0.7863,0.7707,0.7395,0.7004,0.6223,0.4855,0.2629",\ +"0.8684,0.8449,0.8176,0.7785,0.7004,0.5637,0.3449",\ +"1.0051,0.9855,0.9855,0.9113,0.8332,0.7004,0.4895",\ +"1.2277,1.2082,1.1809,1.1379,1.0598,0.9230,0.7004"); + } + } +} +pin(A_WEN) { + direction : input ; + capacitance : 0.00313551 ; + max_transition : "0.5952" ; + related_power_pin : VDD; + related_ground_pin : VSS; + internal_power() { + when : "A_MEN"; + rise_power("scalar"){ + values (0.0026); + } + fall_power("scalar"){ + values (0.0002); + } + } + internal_power() { + when : "!A_MEN"; + rise_power("scalar"){ + values (0.0039); + } + fall_power("scalar"){ + values (0.0006); + } + } + timing() { + timing_type : setup_rising; + related_pin : "A_CLK"; + when : "A_MEN" + sdf_cond : "A_MEN" + + rise_constraint("SIG2SRAM_constraint_template") { + index_1("0.0080,0.0288,0.0616,0.1072,0.1920,0.3496,0.5952"); + index_2("0.0080,0.0288,0.0616,0.1072,0.1920,0.3496,0.5952"); + values ("0.3137,0.3332,0.3605,0.4035,0.4816,0.6223,0.8488",\ +"0.2980,0.3176,0.3410,0.3840,0.4660,0.6027,0.8293",\ +"0.2629,0.2824,0.3098,0.3527,0.4348,0.5754,0.7980",\ +"0.2199,0.2395,0.2668,0.3098,0.3918,0.5324,0.7590",\ +"0.1418,0.1613,0.1887,0.2316,0.3137,0.4348,0.6730",\ +"0.0012,0.0207,0.0520,0.0910,0.1730,0.3098,0.5285",\ +"-0.2215,-0.2020,-0.1746,-0.1277,-0.0496,0.0910,0.3098"); + } + + fall_constraint("SIG2SRAM_constraint_template") { + index_1("0.0080,0.0288,0.0616,0.1072,0.1920,0.3496,0.5952"); + index_2("0.0080,0.0288,0.0616,0.1072,0.1920,0.3496,0.5952"); + values ("0.4504,0.4699,0.4973,0.5324,0.6027,0.7355,0.9699",\ +"0.4309,0.4504,0.4777,0.5129,0.5910,0.7160,0.9504",\ +"0.3996,0.4191,0.4465,0.4816,0.5520,0.6848,0.9191",\ +"0.3605,0.3762,0.4035,0.4387,0.5168,0.6418,0.8723",\ +"0.2785,0.2980,0.3215,0.3605,0.4348,0.5637,0.7980",\ +"0.1379,0.1574,0.1809,0.2199,0.2980,0.4309,0.6457",\ +"-0.0809,-0.0613,-0.0340,0.0051,0.0832,0.2160,0.4191"); + } + } + + + timing() { + timing_type : hold_rising; + related_pin : "A_CLK"; + when : "A_MEN" + sdf_cond : "A_MEN" + + rise_constraint("SIG2SRAM_constraint_template") { + index_1("0.0080,0.0288,0.0616,0.1072,0.1920,0.3496,0.5952"); + index_2("0.0080,0.0288,0.0616,0.1072,0.1920,0.3496,0.5952"); + values ("0.3723,0.3527,0.3215,0.2785,0.1965,0.0559,-0.1668",\ +"0.3918,0.3723,0.3449,0.2980,0.2160,0.0754,-0.1473",\ +"0.4152,0.3996,0.3684,0.3254,0.2434,0.1066,-0.1199",\ +"0.4621,0.4465,0.4152,0.3723,0.2863,0.1496,-0.0730",\ +"0.5324,0.5207,0.4895,0.4465,0.3645,0.2199,0.0051",\ +"0.6770,0.6535,0.6301,0.5832,0.5090,0.3605,0.1418",\ +"0.9035,0.8879,0.8566,0.8137,0.7316,0.5871,0.3684"); + } + + fall_constraint("SIG2SRAM_constraint_template") { + index_1("0.0080,0.0288,0.0616,0.1072,0.1920,0.3496,0.5952"); + index_2("0.0080,0.0288,0.0616,0.1072,0.1920,0.3496,0.5952"); + values ("0.3762,0.3566,0.3293,0.2863,0.2043,0.0676,-0.1434",\ +"0.3957,0.3762,0.3488,0.3059,0.2238,0.0871,-0.1199",\ +"0.4230,0.4035,0.3723,0.3332,0.2512,0.1184,-0.0965",\ +"0.4660,0.4465,0.4191,0.3762,0.2941,0.1613,-0.0496",\ +"0.5324,0.5168,0.4973,0.4543,0.3723,0.2316,0.0285",\ +"0.6809,0.6613,0.6340,0.5910,0.5129,0.3645,0.1652",\ +"0.9113,0.8918,0.8605,0.8176,0.7395,0.5988,0.3879"); + } + } + } +pin(A_REN) { + direction : input ; + capacitance : 0.00381144 ; + max_transition : "0.5952" ; + related_power_pin : VDD; + related_ground_pin : VSS; + internal_power() { + when : "A_MEN"; + rise_power("scalar"){ + values (0.0030); + } + fall_power("scalar"){ + values (0.0005); + } + } + internal_power() { + when : "!A_MEN"; + rise_power("scalar"){ + values (0.0030); + } + fall_power("scalar"){ + values (0.0003); + } + } + timing() { + timing_type : setup_rising; + related_pin : "A_CLK"; + when : "A_MEN" + sdf_cond : "A_MEN" + + rise_constraint("SIG2SRAM_constraint_template") { + index_1("0.0080,0.0288,0.0616,0.1072,0.1920,0.3496,0.5952"); + index_2("0.0080,0.0288,0.0616,0.1072,0.1920,0.3496,0.5952"); + values ("-0.0770,-0.0574,-0.0262,0.0168,0.0949,0.2355,0.4582",\ +"-0.0965,-0.0770,-0.0457,-0.0027,0.0754,0.2160,0.4387",\ +"-0.1199,-0.1004,-0.0730,-0.0262,0.0520,0.1887,0.4113",\ +"-0.1590,-0.1434,-0.1160,-0.0730,0.0051,0.1457,0.3645",\ +"-0.2449,-0.2254,-0.1941,-0.1473,-0.0770,0.0676,0.2863",\ +"-0.3816,-0.3699,-0.3387,-0.2801,-0.2215,-0.0770,0.1457",\ +"-0.6121,-0.5926,-0.5613,-0.5145,-0.4363,-0.2996,-0.0730"); + } + + fall_constraint("SIG2SRAM_constraint_template") { + index_1("0.0080,0.0288,0.0616,0.1072,0.1920,0.3496,0.5952"); + index_2("0.0080,0.0288,0.0616,0.1072,0.1920,0.3496,0.5952"); + values ("0.1262,0.1457,0.1691,0.2121,0.2824,0.4191,0.6457",\ +"0.1105,0.1262,0.1496,0.1887,0.2629,0.3996,0.6262",\ +"0.0793,0.0949,0.1223,0.1652,0.2395,0.3684,0.5949",\ +"0.0363,0.0559,0.0793,0.1223,0.2004,0.3410,0.5520",\ +"-0.0457,-0.0262,0.0012,0.0441,0.1301,0.2629,0.4738",\ +"-0.1902,-0.1746,-0.1434,-0.1043,-0.0184,0.1223,0.3332",\ +"-0.4129,-0.3934,-0.3660,-0.3230,-0.2449,-0.1043,0.1105"); + } + } + + + timing() { + timing_type : hold_rising; + related_pin : "A_CLK"; + when : "A_MEN" + sdf_cond : "A_MEN" + + rise_constraint("SIG2SRAM_constraint_template") { + index_1("0.0080,0.0288,0.0616,0.1072,0.1920,0.3496,0.5952"); + index_2("0.0080,0.0288,0.0616,0.1072,0.1920,0.3496,0.5952"); + values ("0.4113,0.3918,0.3645,0.3176,0.2395,0.0988,-0.1238",\ +"0.4309,0.4113,0.3840,0.3371,0.2590,0.1184,-0.1043",\ +"0.4582,0.4387,0.4113,0.3645,0.2824,0.1457,-0.0770",\ +"0.5051,0.4816,0.4543,0.4074,0.3293,0.1887,-0.0340",\ +"0.5715,0.5598,0.5324,0.4895,0.4035,0.2512,0.0441",\ +"0.7043,0.7004,0.6730,0.6262,0.5402,0.3957,0.1809",\ +"0.9387,0.9270,0.8957,0.8527,0.7746,0.6262,0.4074"); + } + + fall_constraint("SIG2SRAM_constraint_template") { + index_1("0.0080,0.0288,0.0616,0.1072,0.1920,0.3496,0.5952"); + index_2("0.0080,0.0288,0.0616,0.1072,0.1920,0.3496,0.5952"); + values ("0.4152,0.3918,0.3645,0.3215,0.2395,0.1027,-0.1082",\ +"0.4309,0.4113,0.3801,0.3410,0.2590,0.1223,-0.0926",\ +"0.4582,0.4387,0.4074,0.3684,0.2863,0.1496,-0.0613",\ +"0.5012,0.4816,0.4504,0.4074,0.3293,0.1887,-0.0145",\ +"0.5715,0.5559,0.5285,0.4816,0.3996,0.2512,0.0598",\ +"0.7160,0.7004,0.6691,0.6262,0.5520,0.4035,0.2004",\ +"0.9387,0.9191,0.8957,0.8488,0.7707,0.6262,0.4113"); + } + } + } +pin(A_MEN) { + direction : input ; + capacitance : 0.00300347 ; + max_transition : "0.5952" ; + related_power_pin : VDD; + related_ground_pin : VSS; + internal_power() { + rise_power("scalar"){ + values (0.0090); + } + fall_power("scalar"){ + values (0.0009); + } + } + timing() { + timing_type : setup_rising; + related_pin : "A_CLK"; + + rise_constraint("SIG2SRAM_constraint_template") { + index_1("0.0080,0.0288,0.0616,0.1072,0.1920,0.3496,0.5952"); + index_2("0.0080,0.0288,0.0616,0.1072,0.1920,0.3496,0.5952"); + values ("0.3215,0.3449,0.3684,0.4113,0.4895,0.6301,0.8527",\ +"0.3059,0.3254,0.3527,0.3957,0.4738,0.6145,0.8371",\ +"0.2746,0.2941,0.3215,0.3645,0.4426,0.5871,0.8059",\ +"0.2316,0.2512,0.2785,0.3215,0.3996,0.5402,0.7629",\ +"0.1496,0.1730,0.1965,0.2395,0.3215,0.4660,0.6848",\ +"0.0090,0.0285,0.0598,0.1027,0.1809,0.3176,0.5402",\ +"-0.2098,-0.1902,-0.1668,-0.1199,-0.0418,0.0988,0.3137"); + } + + fall_constraint("SIG2SRAM_constraint_template") { + index_1("0.0080,0.0288,0.0616,0.1072,0.1920,0.3496,0.5952"); + index_2("0.0080,0.0288,0.0616,0.1072,0.1920,0.3496,0.5952"); + values ("0.4582,0.4738,0.5012,0.5363,0.6145,0.7395,0.9738",\ +"0.4387,0.4543,0.4816,0.5207,0.5910,0.7199,0.9582",\ +"0.4035,0.4230,0.4504,0.4855,0.5637,0.6887,0.9230",\ +"0.3645,0.3840,0.4074,0.4465,0.5285,0.6496,0.8840",\ +"0.2824,0.3020,0.3254,0.3645,0.4465,0.5715,0.7980",\ +"0.1418,0.1613,0.1887,0.2238,0.3020,0.4309,0.6496",\ +"-0.0770,-0.0574,-0.0301,0.0090,0.0910,0.2238,0.4191"); + } + } + + + timing() { + timing_type : hold_rising; + related_pin : "A_CLK"; + + rise_constraint("SIG2SRAM_constraint_template") { + index_1("0.0080,0.0288,0.0616,0.1072,0.1920,0.3496,0.5952"); + index_2("0.0080,0.0288,0.0616,0.1072,0.1920,0.3496,0.5952"); + values ("0.3762,0.3605,0.3293,0.2863,0.2043,0.0637,-0.1629",\ +"0.3996,0.3801,0.3488,0.3020,0.2238,0.0832,-0.1395",\ +"0.4230,0.4074,0.3723,0.3293,0.2473,0.1105,-0.1121",\ +"0.4621,0.4465,0.4152,0.3762,0.2941,0.1535,-0.0691",\ +"0.5441,0.5285,0.4973,0.4465,0.3684,0.2316,0.0090",\ +"0.6848,0.6652,0.6301,0.5910,0.5129,0.3605,0.1496",\ +"0.9074,0.8918,0.8566,0.8215,0.7395,0.5910,0.3723"); + } + + fall_constraint("SIG2SRAM_constraint_template") { + index_1("0.0080,0.0288,0.0616,0.1072,0.1920,0.3496,0.5952"); + index_2("0.0080,0.0288,0.0616,0.1072,0.1920,0.3496,0.5952"); + values ("0.3762,0.3605,0.3332,0.2863,0.2043,0.0715,-0.1395",\ +"0.3996,0.3762,0.3488,0.3059,0.2238,0.0910,-0.1199",\ +"0.4270,0.4035,0.3762,0.3332,0.2512,0.1184,-0.0965",\ +"0.4699,0.4504,0.4191,0.3762,0.2941,0.1613,-0.0496",\ +"0.5441,0.5285,0.4973,0.4543,0.3762,0.2355,0.0324",\ +"0.6770,0.6613,0.6340,0.5949,0.5207,0.3762,0.1652",\ +"0.9074,0.8918,0.8605,0.8176,0.7395,0.6027,0.3918"); + } + } + } +bus(A_BM) { + bus_type : D_7_0; + direction : input ; + capacitance : 0.00272583 ; + max_transition : "0.5952" ; + pin(A_BM[7:0]) { + related_power_pin : VDD; + related_ground_pin : VSS; + internal_power() { + when : "A_MEN"; + rise_power("scalar"){ + values (0.0177); + } + fall_power("scalar"){ + values (0.0015); + } + } + internal_power() { + when : "!A_MEN"; + rise_power("scalar"){ + values (0.0171); + } + fall_power("scalar"){ + values (0.0008); + } + } + } + timing() { + timing_type : setup_rising; + related_pin : "A_CLK"; + when : "(A_WEN & A_MEN)" + sdf_cond : "A_RW_ACCESS" + + rise_constraint("SIG2SRAM_constraint_template") { + index_1("0.0080,0.0288,0.0616,0.1072,0.1920,0.3496,0.5952"); + index_2("0.0080,0.0288,0.0616,0.1072,0.1920,0.3496,0.5952"); + values ("-0.5976,-0.5780,-0.5517,-0.5087,-0.4286,-0.2811,-0.0604",\ +"-0.6055,-0.5859,-0.5596,-0.5166,-0.4365,-0.2891,-0.0684",\ +"-0.6146,-0.5951,-0.5687,-0.5258,-0.4457,-0.2982,-0.0775",\ +"-0.6296,-0.6101,-0.5837,-0.5407,-0.4606,-0.3132,-0.0925",\ +"-0.6520,-0.6324,-0.6061,-0.5631,-0.4830,-0.3356,-0.1149",\ +"-0.6956,-0.6760,-0.6497,-0.6067,-0.5266,-0.3792,-0.1585",\ +"-0.7648,-0.7452,-0.7189,-0.6759,-0.5958,-0.4483,-0.2276"); + } + + fall_constraint("SIG2SRAM_constraint_template") { + index_1("0.0080,0.0288,0.0616,0.1072,0.1920,0.3496,0.5952"); + index_2("0.0080,0.0288,0.0616,0.1072,0.1920,0.3496,0.5952"); + values ("-0.5331,-0.5136,-0.4872,-0.4491,-0.3661,-0.2294,-0.0175",\ +"-0.5410,-0.5215,-0.4951,-0.4570,-0.3740,-0.2373,-0.0254",\ +"-0.5502,-0.5306,-0.5043,-0.4662,-0.3832,-0.2464,-0.0345",\ +"-0.5651,-0.5456,-0.5192,-0.4812,-0.3981,-0.2614,-0.0495",\ +"-0.5875,-0.5680,-0.5416,-0.5035,-0.4205,-0.2838,-0.0719",\ +"-0.6311,-0.6116,-0.5852,-0.5471,-0.4641,-0.3274,-0.1155",\ +"-0.7003,-0.6808,-0.6544,-0.6163,-0.5333,-0.3966,-0.1847"); + } + } + + + timing() { + timing_type : hold_rising; + related_pin : "A_CLK"; + when : "(A_WEN & A_MEN)" + sdf_cond : "A_RW_ACCESS" + + rise_constraint("SIG2SRAM_constraint_template") { + index_1("0.0080,0.0288,0.0616,0.1072,0.1920,0.3496,0.5952"); + index_2("0.0080,0.0288,0.0616,0.1072,0.1920,0.3496,0.5952"); + values ("0.7095,0.6890,0.6636,0.6206,0.5425,0.3960,0.1734",\ +"0.7174,0.6969,0.6715,0.6285,0.5504,0.4039,0.1813",\ +"0.7266,0.7061,0.6807,0.6377,0.5596,0.4131,0.1904",\ +"0.7415,0.7210,0.6956,0.6527,0.5746,0.4281,0.2054",\ +"0.7639,0.7434,0.7180,0.6751,0.5969,0.4504,0.2278",\ +"0.8075,0.7870,0.7616,0.7187,0.6405,0.4940,0.2714",\ +"0.8767,0.8562,0.8308,0.7878,0.7097,0.5632,0.3406"); + } + + fall_constraint("SIG2SRAM_constraint_template") { + index_1("0.0080,0.0288,0.0616,0.1072,0.1920,0.3496,0.5952"); + index_2("0.0080,0.0288,0.0616,0.1072,0.1920,0.3496,0.5952"); + values ("0.6363,0.6187,0.5904,0.5493,0.4693,0.3316,0.1206",\ +"0.6442,0.6266,0.5983,0.5573,0.4772,0.3395,0.1286",\ +"0.6533,0.6357,0.6074,0.5664,0.4863,0.3486,0.1377",\ +"0.6683,0.6507,0.6224,0.5814,0.5013,0.3636,0.1527",\ +"0.6907,0.6731,0.6448,0.6038,0.5237,0.3860,0.1751",\ +"0.7343,0.7167,0.6884,0.6474,0.5673,0.4296,0.2186",\ +"0.8035,0.7859,0.7576,0.7166,0.6365,0.4988,0.2878"); + } + } +} + pin(A_CLK) { + direction : input; + capacitance : 0.00378957; + max_transition : "0.5952"; + clock : "true" ; + pin_func_type : active_rising ; + + timing () { + timing_type : "min_pulse_width"; + related_pin : "A_CLK"; + rise_constraint("CLKTRAN_constraint_template") { + index_1("0.008,0.5952"); + values("0.4,0.4"); + } + } + + related_power_pin : VDD; + related_ground_pin : VSS; + + internal_power() { + when : "!A_MEN & !A_WEN & !A_REN"; + rise_power("scalar"){ + values (0); + } + fall_power("scalar"){ + values (0); + } + } + internal_power() { + when : "!A_MEN & A_WEN & !A_REN"; + rise_power("scalar"){ + values (0.4316); + } + fall_power("scalar"){ + values (0); + } + } + internal_power() { + when : "A_MEN & A_WEN & !A_REN"; + rise_power("scalar"){ + values (13.4315); + } + fall_power("scalar"){ + values (0); + } + } + internal_power() { + when : "A_MEN & A_WEN & A_REN"; + rise_power("scalar"){ + values (12.9360); + } + fall_power("scalar"){ + values (0); + } + } + internal_power() { + when : "A_MEN & !A_WEN & A_REN"; + rise_power("scalar"){ + values (9.8409); + } + fall_power("scalar"){ + values (0); + } + } + internal_power() { + when : "!A_MEN & !A_WEN & A_REN"; + rise_power("scalar"){ + values (0.2799); + } + fall_power("scalar"){ + values (0); + } + } + internal_power() { + when : "!A_MEN & A_WEN & A_REN"; + rise_power("scalar"){ + values (0.4754); + } + fall_power("scalar"){ + values (0); + } + } + internal_power() { + when : "A_MEN & !A_WEN & !A_REN"; + rise_power("scalar"){ + values (0); + } + fall_power("scalar"){ + values (0); + } + } + } + bus(A_DIN) { + bus_type : D_7_0; + direction : input ; + capacitance : 0.00290547 ; + memory_write() { + address : A_ADDR ; + clocked_on : A_CLK; + } + + max_transition : "0.5952" ; + pin(A_DIN[7:0]) { + related_power_pin : VDD; + related_ground_pin : VSS; + internal_power() { + when : "A_MEN"; + rise_power("scalar"){ + values (0.0177); + } + fall_power("scalar"){ + values (0.0015); + } + } + internal_power() { + when : "!A_MEN"; + rise_power("scalar"){ + values (0.0171); + } + fall_power("scalar"){ + values (0.0008); + } + } + } + timing() { + timing_type : setup_rising; + related_pin : "A_CLK"; + when : "(A_WEN & A_MEN)"; + sdf_cond : "A_W_ACCESS"; + + rise_constraint("SIG2SRAM_constraint_template") { + index_1("0.0080,0.0288,0.0616,0.1072,0.1920,0.3496,0.5952"); + index_2("0.0080,0.0288,0.0616,0.1072,0.1920,0.3496,0.5952"); + values ("-0.5976,-0.5780,-0.5517,-0.5087,-0.4286,-0.2811,-0.0604",\ +"-0.6055,-0.5859,-0.5596,-0.5166,-0.4365,-0.2891,-0.0684",\ +"-0.6146,-0.5951,-0.5687,-0.5258,-0.4457,-0.2982,-0.0775",\ +"-0.6296,-0.6101,-0.5837,-0.5407,-0.4606,-0.3132,-0.0925",\ +"-0.6520,-0.6324,-0.6061,-0.5631,-0.4830,-0.3356,-0.1149",\ +"-0.6956,-0.6760,-0.6497,-0.6067,-0.5266,-0.3792,-0.1585",\ +"-0.7648,-0.7452,-0.7189,-0.6759,-0.5958,-0.4483,-0.2276"); + } + + fall_constraint("SIG2SRAM_constraint_template") { + index_1("0.0080,0.0288,0.0616,0.1072,0.1920,0.3496,0.5952"); + index_2("0.0080,0.0288,0.0616,0.1072,0.1920,0.3496,0.5952"); + values ("-0.5331,-0.5136,-0.4872,-0.4491,-0.3661,-0.2294,-0.0175",\ +"-0.5410,-0.5215,-0.4951,-0.4570,-0.3740,-0.2373,-0.0254",\ +"-0.5502,-0.5306,-0.5043,-0.4662,-0.3832,-0.2464,-0.0345",\ +"-0.5651,-0.5456,-0.5192,-0.4812,-0.3981,-0.2614,-0.0495",\ +"-0.5875,-0.5680,-0.5416,-0.5035,-0.4205,-0.2838,-0.0719",\ +"-0.6311,-0.6116,-0.5852,-0.5471,-0.4641,-0.3274,-0.1155",\ +"-0.7003,-0.6808,-0.6544,-0.6163,-0.5333,-0.3966,-0.1847"); + } + } + + timing() { + timing_type : hold_rising; + related_pin : "A_CLK"; + when : "(A_WEN & A_MEN)"; + sdf_cond : "A_W_ACCESS"; + + rise_constraint("SIG2SRAM_constraint_template") { + index_1("0.0080,0.0288,0.0616,0.1072,0.1920,0.3496,0.5952"); + index_2("0.0080,0.0288,0.0616,0.1072,0.1920,0.3496,0.5952"); + values ("0.7095,0.6890,0.6636,0.6206,0.5425,0.3960,0.1734",\ +"0.7174,0.6969,0.6715,0.6285,0.5504,0.4039,0.1813",\ +"0.7266,0.7061,0.6807,0.6377,0.5596,0.4131,0.1904",\ +"0.7415,0.7210,0.6956,0.6527,0.5746,0.4281,0.2054",\ +"0.7639,0.7434,0.7180,0.6751,0.5969,0.4504,0.2278",\ +"0.8075,0.7870,0.7616,0.7187,0.6405,0.4940,0.2714",\ +"0.8767,0.8562,0.8308,0.7878,0.7097,0.5632,0.3406"); + } + + fall_constraint("SIG2SRAM_constraint_template") { + index_1("0.0080,0.0288,0.0616,0.1072,0.1920,0.3496,0.5952"); + index_2("0.0080,0.0288,0.0616,0.1072,0.1920,0.3496,0.5952"); + values ("0.6363,0.6187,0.5904,0.5493,0.4693,0.3316,0.1206",\ +"0.6442,0.6266,0.5983,0.5573,0.4772,0.3395,0.1286",\ +"0.6533,0.6357,0.6074,0.5664,0.4863,0.3486,0.1377",\ +"0.6683,0.6507,0.6224,0.5814,0.5013,0.3636,0.1527",\ +"0.6907,0.6731,0.6448,0.6038,0.5237,0.3860,0.1751",\ +"0.7343,0.7167,0.6884,0.6474,0.5673,0.4296,0.2186",\ +"0.8035,0.7859,0.7576,0.7166,0.6365,0.4988,0.2878"); + } + } + } + + pin(A_BIST_EN) { + direction : input ; + capacitance : 0.00387999 ; + max_transition : "1" ; + related_power_pin : VDD; + related_ground_pin : VSS; + internal_power() { + rise_power("scalar") { + values (0); + } + fall_power("scalar") { + values (0); + } + } + } + +bus(A_BIST_ADDR) { + bus_type : A_8_0; + direction : input ; + capacitance : 0.0077013 ; + pin(A_BIST_ADDR[0]) { + capacitance : 0.00625349 ; + } + pin(A_BIST_ADDR[1]) { + capacitance : 0.00507435 ; + } + pin(A_BIST_ADDR[2]) { + capacitance : 0.00656707 ; + } + pin(A_BIST_ADDR[3]) { + capacitance : 0.0083133 ; + } + pin(A_BIST_ADDR[4]) { + capacitance : 0.00507219 ; + } + pin(A_BIST_ADDR[5]) { + capacitance : 0.00964344 ; + } + pin(A_BIST_ADDR[6]) { + capacitance : 0.0119653 ; + } + pin(A_BIST_ADDR[7]) { + capacitance : 0.00827606 ; + } + max_transition : "0.5952" ; + pin(A_BIST_ADDR[8:0]) { + related_power_pin : VDD; + related_ground_pin : VSS; + internal_power() { + when : "A_BIST_MEN"; + rise_power("scalar"){ + values (0.0094); + } + fall_power("scalar"){ + values (0.0068); + } + } + internal_power() { + when : "!A_BIST_MEN"; + rise_power("scalar"){ + values (0.0133); + } + fall_power("scalar"){ + values (0.0021); + } + } + } + timing() { + timing_type : setup_rising; + related_pin : "A_BIST_CLK"; + when : "((A_BIST_WEN | A_BIST_REN)& A_BIST_MEN)" + sdf_cond : "A_BIST_RW_ACCESS" + + rise_constraint("SIG2SRAM_constraint_template") { + index_1("0.0080,0.0288,0.0616,0.1072,0.1920,0.3496,0.5952"); + index_2("0.0080,0.0288,0.0616,0.1072,0.1920,0.3496,0.5952"); + values ("-0.7371,-0.7176,-0.6863,-0.6434,-0.5652,-0.4168,-0.1980",\ +"-0.7566,-0.7371,-0.7059,-0.6629,-0.5848,-0.4363,-0.2137",\ +"-0.7879,-0.7645,-0.7332,-0.6902,-0.6121,-0.4637,-0.2449",\ +"-0.8309,-0.8074,-0.7762,-0.7332,-0.6551,-0.5066,-0.2879",\ +"-0.9051,-0.8895,-0.8543,-0.8113,-0.7332,-0.5887,-0.3660",\ +"-1.0418,-1.0262,-0.9949,-0.9480,-0.8699,-0.7293,-0.5027",\ +"-1.2684,-1.2449,-1.2176,-1.1707,-1.0965,-0.9480,-0.7293"); + } + + fall_constraint("SIG2SRAM_constraint_template") { + index_1("0.0080,0.0288,0.0616,0.1072,0.1920,0.3496,0.5952"); + index_2("0.0080,0.0288,0.0616,0.1072,0.1920,0.3496,0.5952"); + values ("-0.5926,-0.5730,-0.5418,-0.4988,-0.4246,-0.2879,-0.0730",\ +"-0.6121,-0.5926,-0.5613,-0.5223,-0.4441,-0.3074,-0.0887",\ +"-0.6395,-0.6199,-0.5926,-0.5496,-0.4715,-0.3348,-0.1160",\ +"-0.6863,-0.6668,-0.6355,-0.5965,-0.5184,-0.3777,-0.1590",\ +"-0.7605,-0.7410,-0.7137,-0.6746,-0.5926,-0.4559,-0.2410",\ +"-0.9012,-0.8816,-0.8504,-0.8113,-0.7332,-0.5926,-0.3895",\ +"-1.1238,-1.1043,-1.0769,-1.0379,-0.9559,-0.8191,-0.6004"); + } + } + + + timing() { + timing_type : hold_rising; + related_pin : "A_BIST_CLK"; + when : "((A_BIST_WEN | A_BIST_REN)& A_BIST_MEN)" + sdf_cond : "A_BIST_RW_ACCESS" + + rise_constraint("SIG2SRAM_constraint_template") { + index_1("0.0080,0.0288,0.0616,0.1072,0.1920,0.3496,0.5952"); + index_2("0.0080,0.0288,0.0616,0.1072,0.1920,0.3496,0.5952"); + values ("0.8488,0.8293,0.7980,0.7551,0.6730,0.5285,0.3059",\ +"0.8684,0.8488,0.8176,0.7746,0.6926,0.5480,0.3254",\ +"0.8996,0.8801,0.8449,0.8020,0.7238,0.5754,0.3527",\ +"0.9426,0.9191,0.8918,0.8488,0.7668,0.6223,0.3996",\ +"1.0168,1.0012,0.9699,0.9230,0.8449,0.7004,0.4777",\ +"1.1574,1.1379,1.1105,1.0598,0.9816,0.8371,0.6184",\ +"1.3801,1.3605,1.3254,1.2980,1.2043,1.0637,0.8371"); + } + + fall_constraint("SIG2SRAM_constraint_template") { + index_1("0.0080,0.0288,0.0616,0.1072,0.1920,0.3496,0.5952"); + index_2("0.0080,0.0288,0.0616,0.1072,0.1920,0.3496,0.5952"); + values ("0.6965,0.6770,0.6496,0.6066,0.5246,0.3918,0.1730",\ +"0.7160,0.6965,0.6652,0.6262,0.5441,0.4113,0.1965",\ +"0.7473,0.7277,0.6965,0.6535,0.5754,0.4426,0.2238",\ +"0.7863,0.7707,0.7395,0.7004,0.6223,0.4855,0.2629",\ +"0.8684,0.8449,0.8176,0.7785,0.7004,0.5637,0.3449",\ +"1.0051,0.9855,0.9855,0.9113,0.8332,0.7004,0.4895",\ +"1.2277,1.2082,1.1809,1.1379,1.0598,0.9230,0.7004"); + } + } +} +pin(A_BIST_WEN) { + direction : input ; + capacitance : 0.00313551 ; + max_transition : "0.5952" ; + related_power_pin : VDD; + related_ground_pin : VSS; + internal_power() { + when : "A_BIST_MEN"; + rise_power("scalar"){ + values (0.0026); + } + fall_power("scalar"){ + values (0.0002); + } + } + internal_power() { + when : "!A_BIST_MEN"; + rise_power("scalar"){ + values (0.0039); + } + fall_power("scalar"){ + values (0.0006); + } + } + timing() { + timing_type : setup_rising; + related_pin : "A_BIST_CLK"; + when : "A_BIST_MEN" + sdf_cond : "A_BIST_MEN" + + rise_constraint("SIG2SRAM_constraint_template") { + index_1("0.0080,0.0288,0.0616,0.1072,0.1920,0.3496,0.5952"); + index_2("0.0080,0.0288,0.0616,0.1072,0.1920,0.3496,0.5952"); + values ("0.3137,0.3332,0.3605,0.4035,0.4816,0.6223,0.8488",\ +"0.2980,0.3176,0.3410,0.3840,0.4660,0.6027,0.8293",\ +"0.2629,0.2824,0.3098,0.3527,0.4348,0.5754,0.7980",\ +"0.2199,0.2395,0.2668,0.3098,0.3918,0.5324,0.7590",\ +"0.1418,0.1613,0.1887,0.2316,0.3137,0.4348,0.6730",\ +"0.0012,0.0207,0.0520,0.0910,0.1730,0.3098,0.5285",\ +"-0.2215,-0.2020,-0.1746,-0.1277,-0.0496,0.0910,0.3098"); + } + + fall_constraint("SIG2SRAM_constraint_template") { + index_1("0.0080,0.0288,0.0616,0.1072,0.1920,0.3496,0.5952"); + index_2("0.0080,0.0288,0.0616,0.1072,0.1920,0.3496,0.5952"); + values ("0.4504,0.4699,0.4973,0.5324,0.6027,0.7355,0.9699",\ +"0.4309,0.4504,0.4777,0.5129,0.5910,0.7160,0.9504",\ +"0.3996,0.4191,0.4465,0.4816,0.5520,0.6848,0.9191",\ +"0.3605,0.3762,0.4035,0.4387,0.5168,0.6418,0.8723",\ +"0.2785,0.2980,0.3215,0.3605,0.4348,0.5637,0.7980",\ +"0.1379,0.1574,0.1809,0.2199,0.2980,0.4309,0.6457",\ +"-0.0809,-0.0613,-0.0340,0.0051,0.0832,0.2160,0.4191"); + } + } + + + timing() { + timing_type : hold_rising; + related_pin : "A_BIST_CLK"; + when : "A_BIST_MEN" + sdf_cond : "A_BIST_MEN" + + rise_constraint("SIG2SRAM_constraint_template") { + index_1("0.0080,0.0288,0.0616,0.1072,0.1920,0.3496,0.5952"); + index_2("0.0080,0.0288,0.0616,0.1072,0.1920,0.3496,0.5952"); + values ("0.3723,0.3527,0.3215,0.2785,0.1965,0.0559,-0.1668",\ +"0.3918,0.3723,0.3449,0.2980,0.2160,0.0754,-0.1473",\ +"0.4152,0.3996,0.3684,0.3254,0.2434,0.1066,-0.1199",\ +"0.4621,0.4465,0.4152,0.3723,0.2863,0.1496,-0.0730",\ +"0.5324,0.5207,0.4895,0.4465,0.3645,0.2199,0.0051",\ +"0.6770,0.6535,0.6301,0.5832,0.5090,0.3605,0.1418",\ +"0.9035,0.8879,0.8566,0.8137,0.7316,0.5871,0.3684"); + } + + fall_constraint("SIG2SRAM_constraint_template") { + index_1("0.0080,0.0288,0.0616,0.1072,0.1920,0.3496,0.5952"); + index_2("0.0080,0.0288,0.0616,0.1072,0.1920,0.3496,0.5952"); + values ("0.3762,0.3566,0.3293,0.2863,0.2043,0.0676,-0.1434",\ +"0.3957,0.3762,0.3488,0.3059,0.2238,0.0871,-0.1199",\ +"0.4230,0.4035,0.3723,0.3332,0.2512,0.1184,-0.0965",\ +"0.4660,0.4465,0.4191,0.3762,0.2941,0.1613,-0.0496",\ +"0.5324,0.5168,0.4973,0.4543,0.3723,0.2316,0.0285",\ +"0.6809,0.6613,0.6340,0.5910,0.5129,0.3645,0.1652",\ +"0.9113,0.8918,0.8605,0.8176,0.7395,0.5988,0.3879"); + } + } + } +pin(A_BIST_REN) { + direction : input ; + capacitance : 0.00381144 ; + max_transition : "0.5952" ; + related_power_pin : VDD; + related_ground_pin : VSS; + internal_power() { + when : "A_BIST_MEN"; + rise_power("scalar"){ + values (0.0030); + } + fall_power("scalar"){ + values (0.0005); + } + } + internal_power() { + when : "!A_BIST_MEN"; + rise_power("scalar"){ + values (0.0030); + } + fall_power("scalar"){ + values (0.0003); + } + } + timing() { + timing_type : setup_rising; + related_pin : "A_BIST_CLK"; + when : "A_BIST_MEN" + sdf_cond : "A_BIST_MEN" + + rise_constraint("SIG2SRAM_constraint_template") { + index_1("0.0080,0.0288,0.0616,0.1072,0.1920,0.3496,0.5952"); + index_2("0.0080,0.0288,0.0616,0.1072,0.1920,0.3496,0.5952"); + values ("-0.0770,-0.0574,-0.0262,0.0168,0.0949,0.2355,0.4582",\ +"-0.0965,-0.0770,-0.0457,-0.0027,0.0754,0.2160,0.4387",\ +"-0.1199,-0.1004,-0.0730,-0.0262,0.0520,0.1887,0.4113",\ +"-0.1590,-0.1434,-0.1160,-0.0730,0.0051,0.1457,0.3645",\ +"-0.2449,-0.2254,-0.1941,-0.1473,-0.0770,0.0676,0.2863",\ +"-0.3816,-0.3699,-0.3387,-0.2801,-0.2215,-0.0770,0.1457",\ +"-0.6121,-0.5926,-0.5613,-0.5145,-0.4363,-0.2996,-0.0730"); + } + + fall_constraint("SIG2SRAM_constraint_template") { + index_1("0.0080,0.0288,0.0616,0.1072,0.1920,0.3496,0.5952"); + index_2("0.0080,0.0288,0.0616,0.1072,0.1920,0.3496,0.5952"); + values ("0.1262,0.1457,0.1691,0.2121,0.2824,0.4191,0.6457",\ +"0.1105,0.1262,0.1496,0.1887,0.2629,0.3996,0.6262",\ +"0.0793,0.0949,0.1223,0.1652,0.2395,0.3684,0.5949",\ +"0.0363,0.0559,0.0793,0.1223,0.2004,0.3410,0.5520",\ +"-0.0457,-0.0262,0.0012,0.0441,0.1301,0.2629,0.4738",\ +"-0.1902,-0.1746,-0.1434,-0.1043,-0.0184,0.1223,0.3332",\ +"-0.4129,-0.3934,-0.3660,-0.3230,-0.2449,-0.1043,0.1105"); + } + } + + + timing() { + timing_type : hold_rising; + related_pin : "A_BIST_CLK"; + when : "A_BIST_MEN" + sdf_cond : "A_BIST_MEN" + + rise_constraint("SIG2SRAM_constraint_template") { + index_1("0.0080,0.0288,0.0616,0.1072,0.1920,0.3496,0.5952"); + index_2("0.0080,0.0288,0.0616,0.1072,0.1920,0.3496,0.5952"); + values ("0.4113,0.3918,0.3645,0.3176,0.2395,0.0988,-0.1238",\ +"0.4309,0.4113,0.3840,0.3371,0.2590,0.1184,-0.1043",\ +"0.4582,0.4387,0.4113,0.3645,0.2824,0.1457,-0.0770",\ +"0.5051,0.4816,0.4543,0.4074,0.3293,0.1887,-0.0340",\ +"0.5715,0.5598,0.5324,0.4895,0.4035,0.2512,0.0441",\ +"0.7043,0.7004,0.6730,0.6262,0.5402,0.3957,0.1809",\ +"0.9387,0.9270,0.8957,0.8527,0.7746,0.6262,0.4074"); + } + + fall_constraint("SIG2SRAM_constraint_template") { + index_1("0.0080,0.0288,0.0616,0.1072,0.1920,0.3496,0.5952"); + index_2("0.0080,0.0288,0.0616,0.1072,0.1920,0.3496,0.5952"); + values ("0.4152,0.3918,0.3645,0.3215,0.2395,0.1027,-0.1082",\ +"0.4309,0.4113,0.3801,0.3410,0.2590,0.1223,-0.0926",\ +"0.4582,0.4387,0.4074,0.3684,0.2863,0.1496,-0.0613",\ +"0.5012,0.4816,0.4504,0.4074,0.3293,0.1887,-0.0145",\ +"0.5715,0.5559,0.5285,0.4816,0.3996,0.2512,0.0598",\ +"0.7160,0.7004,0.6691,0.6262,0.5520,0.4035,0.2004",\ +"0.9387,0.9191,0.8957,0.8488,0.7707,0.6262,0.4113"); + } + } + } +pin(A_BIST_MEN) { + direction : input ; + capacitance : 0.00300347 ; + max_transition : "0.5952" ; + related_power_pin : VDD; + related_ground_pin : VSS; + internal_power() { + rise_power("scalar"){ + values (0.0090); + } + fall_power("scalar"){ + values (0.0009); + } + } + timing() { + timing_type : setup_rising; + related_pin : "A_BIST_CLK"; + + rise_constraint("SIG2SRAM_constraint_template") { + index_1("0.0080,0.0288,0.0616,0.1072,0.1920,0.3496,0.5952"); + index_2("0.0080,0.0288,0.0616,0.1072,0.1920,0.3496,0.5952"); + values ("0.3215,0.3449,0.3684,0.4113,0.4895,0.6301,0.8527",\ +"0.3059,0.3254,0.3527,0.3957,0.4738,0.6145,0.8371",\ +"0.2746,0.2941,0.3215,0.3645,0.4426,0.5871,0.8059",\ +"0.2316,0.2512,0.2785,0.3215,0.3996,0.5402,0.7629",\ +"0.1496,0.1730,0.1965,0.2395,0.3215,0.4660,0.6848",\ +"0.0090,0.0285,0.0598,0.1027,0.1809,0.3176,0.5402",\ +"-0.2098,-0.1902,-0.1668,-0.1199,-0.0418,0.0988,0.3137"); + } + + fall_constraint("SIG2SRAM_constraint_template") { + index_1("0.0080,0.0288,0.0616,0.1072,0.1920,0.3496,0.5952"); + index_2("0.0080,0.0288,0.0616,0.1072,0.1920,0.3496,0.5952"); + values ("0.4582,0.4738,0.5012,0.5363,0.6145,0.7395,0.9738",\ +"0.4387,0.4543,0.4816,0.5207,0.5910,0.7199,0.9582",\ +"0.4035,0.4230,0.4504,0.4855,0.5637,0.6887,0.9230",\ +"0.3645,0.3840,0.4074,0.4465,0.5285,0.6496,0.8840",\ +"0.2824,0.3020,0.3254,0.3645,0.4465,0.5715,0.7980",\ +"0.1418,0.1613,0.1887,0.2238,0.3020,0.4309,0.6496",\ +"-0.0770,-0.0574,-0.0301,0.0090,0.0910,0.2238,0.4191"); + } + } + + + timing() { + timing_type : hold_rising; + related_pin : "A_BIST_CLK"; + + rise_constraint("SIG2SRAM_constraint_template") { + index_1("0.0080,0.0288,0.0616,0.1072,0.1920,0.3496,0.5952"); + index_2("0.0080,0.0288,0.0616,0.1072,0.1920,0.3496,0.5952"); + values ("0.3762,0.3605,0.3293,0.2863,0.2043,0.0637,-0.1629",\ +"0.3996,0.3801,0.3488,0.3020,0.2238,0.0832,-0.1395",\ +"0.4230,0.4074,0.3723,0.3293,0.2473,0.1105,-0.1121",\ +"0.4621,0.4465,0.4152,0.3762,0.2941,0.1535,-0.0691",\ +"0.5441,0.5285,0.4973,0.4465,0.3684,0.2316,0.0090",\ +"0.6848,0.6652,0.6301,0.5910,0.5129,0.3605,0.1496",\ +"0.9074,0.8918,0.8566,0.8215,0.7395,0.5910,0.3723"); + } + + fall_constraint("SIG2SRAM_constraint_template") { + index_1("0.0080,0.0288,0.0616,0.1072,0.1920,0.3496,0.5952"); + index_2("0.0080,0.0288,0.0616,0.1072,0.1920,0.3496,0.5952"); + values ("0.3762,0.3605,0.3332,0.2863,0.2043,0.0715,-0.1395",\ +"0.3996,0.3762,0.3488,0.3059,0.2238,0.0910,-0.1199",\ +"0.4270,0.4035,0.3762,0.3332,0.2512,0.1184,-0.0965",\ +"0.4699,0.4504,0.4191,0.3762,0.2941,0.1613,-0.0496",\ +"0.5441,0.5285,0.4973,0.4543,0.3762,0.2355,0.0324",\ +"0.6770,0.6613,0.6340,0.5949,0.5207,0.3762,0.1652",\ +"0.9074,0.8918,0.8605,0.8176,0.7395,0.6027,0.3918"); + } + } + } +bus(A_BIST_BM) { + bus_type : D_7_0; + direction : input ; + capacitance : 0.00223339 ; + max_transition : "0.5952" ; + pin(A_BIST_BM[7:0]) { + related_power_pin : VDD; + related_ground_pin : VSS; + internal_power() { + when : "A_BIST_MEN"; + rise_power("scalar"){ + values (0.0177); + } + fall_power("scalar"){ + values (0.0015); + } + } + internal_power() { + when : "!A_BIST_MEN"; + rise_power("scalar"){ + values (0.0171); + } + fall_power("scalar"){ + values (0.0008); + } + } + } + timing() { + timing_type : setup_rising; + related_pin : "A_BIST_CLK"; + when : "(A_BIST_WEN & A_BIST_MEN)" + sdf_cond : "A_BIST_RW_ACCESS" + + rise_constraint("SIG2SRAM_constraint_template") { + index_1("0.0080,0.0288,0.0616,0.1072,0.1920,0.3496,0.5952"); + index_2("0.0080,0.0288,0.0616,0.1072,0.1920,0.3496,0.5952"); + values ("-0.5976,-0.5780,-0.5517,-0.5087,-0.4286,-0.2811,-0.0604",\ +"-0.6055,-0.5859,-0.5596,-0.5166,-0.4365,-0.2891,-0.0684",\ +"-0.6146,-0.5951,-0.5687,-0.5258,-0.4457,-0.2982,-0.0775",\ +"-0.6296,-0.6101,-0.5837,-0.5407,-0.4606,-0.3132,-0.0925",\ +"-0.6520,-0.6324,-0.6061,-0.5631,-0.4830,-0.3356,-0.1149",\ +"-0.6956,-0.6760,-0.6497,-0.6067,-0.5266,-0.3792,-0.1585",\ +"-0.7648,-0.7452,-0.7189,-0.6759,-0.5958,-0.4483,-0.2276"); + } + + fall_constraint("SIG2SRAM_constraint_template") { + index_1("0.0080,0.0288,0.0616,0.1072,0.1920,0.3496,0.5952"); + index_2("0.0080,0.0288,0.0616,0.1072,0.1920,0.3496,0.5952"); + values ("-0.5331,-0.5136,-0.4872,-0.4491,-0.3661,-0.2294,-0.0175",\ +"-0.5410,-0.5215,-0.4951,-0.4570,-0.3740,-0.2373,-0.0254",\ +"-0.5502,-0.5306,-0.5043,-0.4662,-0.3832,-0.2464,-0.0345",\ +"-0.5651,-0.5456,-0.5192,-0.4812,-0.3981,-0.2614,-0.0495",\ +"-0.5875,-0.5680,-0.5416,-0.5035,-0.4205,-0.2838,-0.0719",\ +"-0.6311,-0.6116,-0.5852,-0.5471,-0.4641,-0.3274,-0.1155",\ +"-0.7003,-0.6808,-0.6544,-0.6163,-0.5333,-0.3966,-0.1847"); + } + } + + + timing() { + timing_type : hold_rising; + related_pin : "A_BIST_CLK"; + when : "(A_BIST_WEN & A_BIST_MEN)" + sdf_cond : "A_BIST_RW_ACCESS" + + rise_constraint("SIG2SRAM_constraint_template") { + index_1("0.0080,0.0288,0.0616,0.1072,0.1920,0.3496,0.5952"); + index_2("0.0080,0.0288,0.0616,0.1072,0.1920,0.3496,0.5952"); + values ("0.7095,0.6890,0.6636,0.6206,0.5425,0.3960,0.1734",\ +"0.7174,0.6969,0.6715,0.6285,0.5504,0.4039,0.1813",\ +"0.7266,0.7061,0.6807,0.6377,0.5596,0.4131,0.1904",\ +"0.7415,0.7210,0.6956,0.6527,0.5746,0.4281,0.2054",\ +"0.7639,0.7434,0.7180,0.6751,0.5969,0.4504,0.2278",\ +"0.8075,0.7870,0.7616,0.7187,0.6405,0.4940,0.2714",\ +"0.8767,0.8562,0.8308,0.7878,0.7097,0.5632,0.3406"); + } + + fall_constraint("SIG2SRAM_constraint_template") { + index_1("0.0080,0.0288,0.0616,0.1072,0.1920,0.3496,0.5952"); + index_2("0.0080,0.0288,0.0616,0.1072,0.1920,0.3496,0.5952"); + values ("0.6363,0.6187,0.5904,0.5493,0.4693,0.3316,0.1206",\ +"0.6442,0.6266,0.5983,0.5573,0.4772,0.3395,0.1286",\ +"0.6533,0.6357,0.6074,0.5664,0.4863,0.3486,0.1377",\ +"0.6683,0.6507,0.6224,0.5814,0.5013,0.3636,0.1527",\ +"0.6907,0.6731,0.6448,0.6038,0.5237,0.3860,0.1751",\ +"0.7343,0.7167,0.6884,0.6474,0.5673,0.4296,0.2186",\ +"0.8035,0.7859,0.7576,0.7166,0.6365,0.4988,0.2878"); + } + } +} + pin(A_BIST_CLK) { + direction : input; + capacitance : 0.00378957; + max_transition : "0.5952"; + clock : "true" ; + pin_func_type : active_rising ; + + timing () { + timing_type : "min_pulse_width"; + related_pin : "A_BIST_CLK"; + rise_constraint("CLKTRAN_constraint_template") { + index_1("0.008,0.5952"); + values("0.4,0.4"); + } + } + + related_power_pin : VDD; + related_ground_pin : VSS; + + internal_power() { + when : "!A_BIST_MEN & !A_BIST_WEN & !A_BIST_REN"; + rise_power("scalar"){ + values (0); + } + fall_power("scalar"){ + values (0); + } + } + internal_power() { + when : "!A_BIST_MEN & A_BIST_WEN & !A_BIST_REN"; + rise_power("scalar"){ + values (0.4316); + } + fall_power("scalar"){ + values (0); + } + } + internal_power() { + when : "A_BIST_MEN & A_BIST_WEN & !A_BIST_REN"; + rise_power("scalar"){ + values (13.4315); + } + fall_power("scalar"){ + values (0); + } + } + internal_power() { + when : "A_BIST_MEN & A_BIST_WEN & A_BIST_REN"; + rise_power("scalar"){ + values (12.9360); + } + fall_power("scalar"){ + values (0); + } + } + internal_power() { + when : "A_BIST_MEN & !A_BIST_WEN & A_BIST_REN"; + rise_power("scalar"){ + values (9.8409); + } + fall_power("scalar"){ + values (0); + } + } + internal_power() { + when : "!A_BIST_MEN & !A_BIST_WEN & A_BIST_REN"; + rise_power("scalar"){ + values (0.2799); + } + fall_power("scalar"){ + values (0); + } + } + internal_power() { + when : "!A_BIST_MEN & A_BIST_WEN & A_BIST_REN"; + rise_power("scalar"){ + values (0.4754); + } + fall_power("scalar"){ + values (0); + } + } + internal_power() { + when : "A_BIST_MEN & !A_BIST_WEN & !A_BIST_REN"; + rise_power("scalar"){ + values (0); + } + fall_power("scalar"){ + values (0); + } + } + } + bus(A_BIST_DIN) { + bus_type : D_7_0; + direction : input ; + capacitance : 0.00223473 ; + memory_write() { + address : A_BIST_ADDR ; + clocked_on : A_BIST_CLK; + } + + max_transition : "0.5952" ; + pin(A_BIST_DIN[7:0]) { + related_power_pin : VDD; + related_ground_pin : VSS; + internal_power() { + when : "A_BIST_MEN"; + rise_power("scalar"){ + values (0.0177); + } + fall_power("scalar"){ + values (0.0015); + } + } + internal_power() { + when : "!A_BIST_MEN"; + rise_power("scalar"){ + values (0.0171); + } + fall_power("scalar"){ + values (0.0008); + } + } + } + timing() { + timing_type : setup_rising; + related_pin : "A_BIST_CLK"; + when : "(A_BIST_WEN & A_BIST_MEN)"; + sdf_cond : "A_BIST_W_ACCESS"; + + rise_constraint("SIG2SRAM_constraint_template") { + index_1("0.0080,0.0288,0.0616,0.1072,0.1920,0.3496,0.5952"); + index_2("0.0080,0.0288,0.0616,0.1072,0.1920,0.3496,0.5952"); + values ("-0.5976,-0.5780,-0.5517,-0.5087,-0.4286,-0.2811,-0.0604",\ +"-0.6055,-0.5859,-0.5596,-0.5166,-0.4365,-0.2891,-0.0684",\ +"-0.6146,-0.5951,-0.5687,-0.5258,-0.4457,-0.2982,-0.0775",\ +"-0.6296,-0.6101,-0.5837,-0.5407,-0.4606,-0.3132,-0.0925",\ +"-0.6520,-0.6324,-0.6061,-0.5631,-0.4830,-0.3356,-0.1149",\ +"-0.6956,-0.6760,-0.6497,-0.6067,-0.5266,-0.3792,-0.1585",\ +"-0.7648,-0.7452,-0.7189,-0.6759,-0.5958,-0.4483,-0.2276"); + } + + fall_constraint("SIG2SRAM_constraint_template") { + index_1("0.0080,0.0288,0.0616,0.1072,0.1920,0.3496,0.5952"); + index_2("0.0080,0.0288,0.0616,0.1072,0.1920,0.3496,0.5952"); + values ("-0.5331,-0.5136,-0.4872,-0.4491,-0.3661,-0.2294,-0.0175",\ +"-0.5410,-0.5215,-0.4951,-0.4570,-0.3740,-0.2373,-0.0254",\ +"-0.5502,-0.5306,-0.5043,-0.4662,-0.3832,-0.2464,-0.0345",\ +"-0.5651,-0.5456,-0.5192,-0.4812,-0.3981,-0.2614,-0.0495",\ +"-0.5875,-0.5680,-0.5416,-0.5035,-0.4205,-0.2838,-0.0719",\ +"-0.6311,-0.6116,-0.5852,-0.5471,-0.4641,-0.3274,-0.1155",\ +"-0.7003,-0.6808,-0.6544,-0.6163,-0.5333,-0.3966,-0.1847"); + } + } + + timing() { + timing_type : hold_rising; + related_pin : "A_BIST_CLK"; + when : "(A_BIST_WEN & A_BIST_MEN)"; + sdf_cond : "A_BIST_W_ACCESS"; + + rise_constraint("SIG2SRAM_constraint_template") { + index_1("0.0080,0.0288,0.0616,0.1072,0.1920,0.3496,0.5952"); + index_2("0.0080,0.0288,0.0616,0.1072,0.1920,0.3496,0.5952"); + values ("0.7095,0.6890,0.6636,0.6206,0.5425,0.3960,0.1734",\ +"0.7174,0.6969,0.6715,0.6285,0.5504,0.4039,0.1813",\ +"0.7266,0.7061,0.6807,0.6377,0.5596,0.4131,0.1904",\ +"0.7415,0.7210,0.6956,0.6527,0.5746,0.4281,0.2054",\ +"0.7639,0.7434,0.7180,0.6751,0.5969,0.4504,0.2278",\ +"0.8075,0.7870,0.7616,0.7187,0.6405,0.4940,0.2714",\ +"0.8767,0.8562,0.8308,0.7878,0.7097,0.5632,0.3406"); + } + + fall_constraint("SIG2SRAM_constraint_template") { + index_1("0.0080,0.0288,0.0616,0.1072,0.1920,0.3496,0.5952"); + index_2("0.0080,0.0288,0.0616,0.1072,0.1920,0.3496,0.5952"); + values ("0.6363,0.6187,0.5904,0.5493,0.4693,0.3316,0.1206",\ +"0.6442,0.6266,0.5983,0.5573,0.4772,0.3395,0.1286",\ +"0.6533,0.6357,0.6074,0.5664,0.4863,0.3486,0.1377",\ +"0.6683,0.6507,0.6224,0.5814,0.5013,0.3636,0.1527",\ +"0.6907,0.6731,0.6448,0.6038,0.5237,0.3860,0.1751",\ +"0.7343,0.7167,0.6884,0.6474,0.5673,0.4296,0.2186",\ +"0.8035,0.7859,0.7576,0.7166,0.6365,0.4988,0.2878"); + } + } + } + +bus(A_DOUT) { + + bus_type : D_7_0; + direction : output ; + capacitance : 0 ; + max_capacitance : 0.064 ; + memory_read() { + address : A_ADDR ; + } + pin(A_DOUT[7:0]) { + related_power_pin : VDD; + related_ground_pin : VSS; + internal_power() { + rise_power("scalar") { + values (0); + } + fall_power("scalar") { + values (0); + } + } + } + timing() { + related_pin : "A_CLK"; + timing_type : rising_edge ; + timing_sense : non_unate ; + + cell_rise(SIG2SRAM_delay_template) { + index_1("0.0080,0.0288,0.0616,0.1072,0.1920,0.3496,0.5952"); + index_2("0.0008,0.0014,0.0051,0.0100,0.0339,0.0640"); + values ("4.9562,4.9590,4.9712,4.9854,5.0374,5.0954",\ +"4.9702,4.9729,4.9851,4.9993,5.0513,5.1094",\ +"4.9800,4.9827,4.9949,5.0091,5.0612,5.1192",\ +"4.9933,4.9960,5.0082,5.0224,5.0745,5.1325",\ +"5.0166,5.0193,5.0315,5.0457,5.0977,5.1558",\ +"5.0613,5.0640,5.0762,5.0904,5.1425,5.2005",\ +"5.1286,5.1313,5.1435,5.1577,5.2097,5.2678"); + } + cell_fall(SIG2SRAM_delay_template) { + index_1("0.0080,0.0288,0.0616,0.1072,0.1920,0.3496,0.5952"); + index_2("0.0008,0.0014,0.0051,0.0100,0.0339,0.0640"); + values ("4.8463,4.8485,4.8581,4.8699,4.9135,4.9572",\ +"4.8602,4.8624,4.8720,4.8838,4.9274,4.9711",\ +"4.8701,4.8722,4.8819,4.8937,4.9372,4.9810",\ +"4.8834,4.8855,4.8952,4.9070,4.9505,4.9943",\ +"4.9066,4.9088,4.9184,4.9302,4.9738,5.0175",\ +"4.9514,4.9536,4.9632,4.9750,5.0186,5.0623",\ +"5.0187,5.0208,5.0304,5.0422,5.0858,5.1295"); + } + + rise_transition(SRAM_load_template) { + index_1("0.0008,0.0014,0.0051,0.0100,0.0339,0.0640"); + values ("0.0560,0.0583,0.0696,0.0816,0.1519,0.2335"); + } + fall_transition(SRAM_load_template) { + index_1("0.0008,0.0014,0.0051,0.0100,0.0339,0.0640"); + values ("0.0428,0.0445,0.0538,0.0658,0.1181,0.1751"); + } + } +} +cell_leakage_power : 326.6470; +} +} diff --git a/flow/platforms/ihp-sg13g2/lib/RM_IHPSG13_1P_512x8_c3_bm_bist_typ_1p20V_25C.lib b/flow/platforms/ihp-sg13g2/lib/RM_IHPSG13_1P_512x8_c3_bm_bist_typ_1p20V_25C.lib new file mode 100644 index 0000000000..407e7b09c8 --- /dev/null +++ b/flow/platforms/ihp-sg13g2/lib/RM_IHPSG13_1P_512x8_c3_bm_bist_typ_1p20V_25C.lib @@ -0,0 +1,1519 @@ +/* ------------------------------------------------------*/ +/**/ +/* Copyright 2025 IHP PDK Authors*/ +/**/ +/* Licensed under the Apache License, Version 2.0 (the "License");*/ +/* you may not use this file except in compliance with the License.*/ +/* You may obtain a copy of the License at*/ +/* */ +/* https://www.apache.org/licenses/LICENSE-2.0*/ +/* */ +/* Unless required by applicable law or agreed to in writing, software*/ +/* distributed under the License is distributed on an "AS IS" BASIS,*/ +/* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.*/ +/* See the License for the specific language governing permissions and*/ +/* limitations under the License.*/ +/* */ +/* Generated on Wed Aug 27 16:20:21 2025 */ +/* */ +/* ------------------------------------------------------ */ +library(RM_IHPSG13_1P_512x8_c3_bm_bist_typ_1p20V_25C) { + technology (cmos) ; + delay_model : table_lookup ; + define ("add_pg_pin_to_lib", "library", "boolean"); + add_pg_pin_to_lib : true; + voltage_map ( VDD, 1.20); + voltage_map ( VDDARRAY, 1.20); + voltage_map ( VSS, 0.000000 ); + + date : "Wed Aug 27 16:20:18 2025" ; + comment : "IHP Microelectronics GmbH, 2023" ; + revision : 1.0.0 ; + simulation : true ; + nom_process : 1 ; + nom_temperature : 25 ; + nom_voltage : 1.20 ; + + operating_conditions("typ_1p20V_25C"){ + process : 1 ; + temperature : 25 ; + voltage : 1.20 ; + tree_type : "balanced_tree" ; + } + + default_operating_conditions : typ_1p20V_25C ; + default_max_transition : 1.0 ; + default_fanout_load : 1.0 ; + default_inout_pin_cap : 0.0 ; + default_input_pin_cap : 0.0 ; + default_output_pin_cap : 0.0 ; + default_cell_leakage_power : 0.0 ; + default_leakage_power_density : 0.0 ; + + slew_lower_threshold_pct_rise : 30 ; + slew_upper_threshold_pct_rise : 70 ; + input_threshold_pct_fall : 50 ; + output_threshold_pct_fall : 50 ; + input_threshold_pct_rise : 50 ; + output_threshold_pct_rise : 50 ; + slew_lower_threshold_pct_fall : 30 ; + slew_upper_threshold_pct_fall : 70 ; + slew_derate_from_library : 0.5; + k_volt_cell_leakage_power : 0.0 ; + k_temp_cell_leakage_power : 0.0 ; + k_process_cell_leakage_power : 0.0 ; + k_volt_internal_power : 0.0 ; + k_temp_internal_power : 0.0 ; + k_process_internal_power : 0.0 ; + + capacitive_load_unit (1,pf) ; + voltage_unit : "1V" ; + current_unit : "1uA" ; + time_unit : "1ns" ; + leakage_power_unit : "1nW" ; + pulling_resistance_unit : "1kohm"; + /* + ------------------------------------------------------------------------------------------ + implicit units overview: + cell_area unit : "um" + internal_power unit : "1e-12 * J/toggle = 1 * uW/MHz" + (capacitive_load_unit * voltage_unit^2) per toggle event + ------------------------------------------------------------------------------------------ + */ + library_features(report_delay_calculation); + define_cell_area (pad_drivers,pad_driver_sites) ; + + lu_table_template(CLKTRAN_constraint_template) { + variable_1 : constrained_pin_transition; + index_1 ( "0.010, 0.050, 0.200, 0.400, 1.000" ); + } + lu_table_template(SRAM_load_template) { + variable_1 : total_output_net_capacitance; + index_1 ( "0.0008,0.0014,0.0051,0.0100,0.0339,0.0640" ); + } + lu_table_template(SIG2SRAM_constraint_template) { + variable_1 : related_pin_transition; + variable_2 : constrained_pin_transition; + index_1 ( "0.0056,0.0232,0.0400,0.0728,0.1280,0.2440,0.4760" ); + index_2 ( "0.0056,0.0232,0.0400,0.0728,0.1280,0.2440,0.4760" ); + } + + lu_table_template(SIG2SRAM_delay_template) { + variable_1 : input_net_transition; + variable_2 : total_output_net_capacitance; + index_1 ( "0.0056,0.0232,0.0400,0.0728,0.1280,0.2440,0.4760" ); + index_2 ( "0.0008,0.0014,0.0051,0.0100,0.0339,0.0640" ); + } + + type (D_7_0) { + base_type : array; + data_type : bit; + bit_width : 8; + bit_from : 7; + bit_to : 0; + downto : true; + } + + type (A_8_0) { + base_type : array; + data_type : bit; + bit_width : 9; + bit_from : 8; + bit_to : 0; + downto : true; + } + +cell(RM_IHPSG13_1P_512x8_c3_bm_bist) { +pg_pin (VDD) { + pg_type : primary_power; + voltage_name : VDD; +} +pg_pin (VDDARRAY) { + pg_type : primary_power; + voltage_name : VDDARRAY; +} +pg_pin (VSS) { + pg_type : primary_ground; + voltage_name : VSS; +} + +memory() { + type : ram; + address_width : 9; + word_width : 8; +} + +interface_timing : false; +bus_naming_style : "%s[%d]" ; +area : 26137.984 ; + + pin(A_DLY) { + direction : input ; + capacitance : 0.00401111 ; + max_transition : "1" ; + related_power_pin : VDD; + related_ground_pin : VSS; + internal_power() { + rise_power("scalar") { + values (0); + } + fall_power("scalar") { + values (0); + } + } + } + +bus(A_ADDR) { + bus_type : A_8_0; + direction : input ; + capacitance : 0.00721489 ; + pin(A_ADDR[0]) { + capacitance : 0.00593979 ; + } + pin(A_ADDR[1]) { + capacitance : 0.00483009 ; + } + pin(A_ADDR[2]) { + capacitance : 0.006215 ; + } + pin(A_ADDR[3]) { + capacitance : 0.00766726 ; + } + pin(A_ADDR[4]) { + capacitance : 0.00488951 ; + } + pin(A_ADDR[5]) { + capacitance : 0.0091523 ; + } + pin(A_ADDR[6]) { + capacitance : 0.0109212 ; + } + pin(A_ADDR[7]) { + capacitance : 0.00774122 ; + } + max_transition : "0.476" ; + pin(A_ADDR[8:0]) { + related_power_pin : VDD; + related_ground_pin : VSS; + internal_power() { + when : "A_MEN"; + rise_power("scalar"){ + values (0.0104); + } + fall_power("scalar"){ + values (0.0041); + } + } + internal_power() { + when : "!A_MEN"; + rise_power("scalar"){ + values (0.0202); + } + fall_power("scalar"){ + values (0.0006); + } + } + } + timing() { + timing_type : setup_rising; + related_pin : "A_CLK"; + when : "((A_WEN | A_REN)& A_MEN)" + sdf_cond : "A_RW_ACCESS" + + rise_constraint("SIG2SRAM_constraint_template") { + index_1("0.0056,0.0232,0.0400,0.0728,0.1280,0.2440,0.4760"); + index_2("0.0056,0.0232,0.0400,0.0728,0.1280,0.2440,0.4760"); + values ("-0.4168,-0.3973,-0.3855,-0.3543,-0.3074,-0.2020,-0.0027",\ +"-0.4324,-0.4129,-0.4012,-0.3699,-0.3191,-0.2176,-0.0184",\ +"-0.4441,-0.4285,-0.4129,-0.3816,-0.3309,-0.2293,-0.0301",\ +"-0.4793,-0.4598,-0.4441,-0.4129,-0.3660,-0.2645,-0.0652",\ +"-0.5223,-0.5066,-0.4910,-0.4598,-0.4129,-0.3074,-0.1121",\ +"-0.6199,-0.6082,-0.5926,-0.5613,-0.5145,-0.4129,-0.2137",\ +"-0.8191,-0.8074,-0.7840,-0.7566,-0.7098,-0.6082,-0.4051"); + } + + fall_constraint("SIG2SRAM_constraint_template") { + index_1("0.0056,0.0232,0.0400,0.0728,0.1280,0.2440,0.4760"); + index_2("0.0056,0.0232,0.0400,0.0728,0.1280,0.2440,0.4760"); + values ("-0.3309,-0.3113,-0.2996,-0.2684,-0.2176,-0.1238,0.0637",\ +"-0.3465,-0.3309,-0.3152,-0.2840,-0.2332,-0.1395,0.0480",\ +"-0.3582,-0.3426,-0.3270,-0.2996,-0.2488,-0.1512,0.0324",\ +"-0.3895,-0.3738,-0.3582,-0.3309,-0.2801,-0.1863,0.0051",\ +"-0.4363,-0.4207,-0.4051,-0.3777,-0.3230,-0.2293,-0.0379",\ +"-0.5379,-0.5223,-0.5066,-0.4793,-0.4285,-0.3309,-0.1434",\ +"-0.7332,-0.7176,-0.7020,-0.6746,-0.6238,-0.5262,-0.3387"); + } + } + + + timing() { + timing_type : hold_rising; + related_pin : "A_CLK"; + when : "((A_WEN | A_REN)& A_MEN)" + sdf_cond : "A_RW_ACCESS" + + rise_constraint("SIG2SRAM_constraint_template") { + index_1("0.0056,0.0232,0.0400,0.0728,0.1280,0.2440,0.4760"); + index_2("0.0056,0.0232,0.0400,0.0728,0.1280,0.2440,0.4760"); + values ("0.5246,0.5051,0.4895,0.4582,0.4113,0.3059,0.1066",\ +"0.5402,0.5207,0.5051,0.4777,0.4270,0.3215,0.1223",\ +"0.5520,0.5324,0.5168,0.4895,0.4387,0.3371,0.1340",\ +"0.5832,0.5676,0.5520,0.5207,0.4738,0.3684,0.1691",\ +"0.6301,0.6105,0.5949,0.5676,0.5168,0.4113,0.2160",\ +"0.7316,0.7121,0.7004,0.6691,0.6223,0.5168,0.3176",\ +"0.9270,0.9230,0.8957,0.8645,0.8137,0.7121,0.5168"); + } + + fall_constraint("SIG2SRAM_constraint_template") { + index_1("0.0056,0.0232,0.0400,0.0728,0.1280,0.2440,0.4760"); + index_2("0.0056,0.0232,0.0400,0.0728,0.1280,0.2440,0.4760"); + values ("0.4309,0.4152,0.4035,0.3684,0.3215,0.2277,0.0363",\ +"0.4465,0.4309,0.4152,0.3879,0.3371,0.2395,0.0559",\ +"0.4582,0.4426,0.4309,0.3996,0.3488,0.2551,0.0715",\ +"0.4934,0.4777,0.4621,0.4348,0.3840,0.2863,0.0988",\ +"0.5363,0.5207,0.5051,0.4777,0.4270,0.3332,0.1418",\ +"0.6379,0.6262,0.6105,0.5793,0.5324,0.4348,0.2434",\ +"0.8332,0.8215,0.8059,0.7707,0.7238,0.6301,0.4387"); + } + } +} +pin(A_WEN) { + direction : input ; + capacitance : 0.00324098 ; + max_transition : "0.476" ; + related_power_pin : VDD; + related_ground_pin : VSS; + internal_power() { + when : "A_MEN"; + rise_power("scalar"){ + values (0.0037); + } + fall_power("scalar"){ + values (0.0047); + } + } + internal_power() { + when : "!A_MEN"; + rise_power("scalar"){ + values (0.0029); + } + fall_power("scalar"){ + values (0.0044); + } + } + timing() { + timing_type : setup_rising; + related_pin : "A_CLK"; + when : "A_MEN" + sdf_cond : "A_MEN" + + rise_constraint("SIG2SRAM_constraint_template") { + index_1("0.0056,0.0232,0.0400,0.0728,0.1280,0.2440,0.4760"); + index_2("0.0056,0.0232,0.0400,0.0728,0.1280,0.2440,0.4760"); + values ("0.2043,0.2199,0.2316,0.2629,0.3059,0.4113,0.6066",\ +"0.1887,0.2043,0.2160,0.2473,0.2941,0.3957,0.5949",\ +"0.1691,0.1848,0.2004,0.2316,0.2785,0.3801,0.5754",\ +"0.1379,0.1574,0.1691,0.2004,0.2473,0.3527,0.5480",\ +"0.0910,0.1066,0.1223,0.1535,0.2004,0.2980,0.4973",\ +"-0.0105,0.0051,0.0207,0.0520,0.0949,0.2004,0.3957",\ +"-0.2059,-0.1902,-0.1746,-0.1473,-0.1004,0.0051,0.2004"); + } + + fall_constraint("SIG2SRAM_constraint_template") { + index_1("0.0056,0.0232,0.0400,0.0728,0.1280,0.2440,0.4760"); + index_2("0.0056,0.0232,0.0400,0.0728,0.1280,0.2440,0.4760"); + values ("0.2941,0.3098,0.3215,0.3488,0.4035,0.4973,0.6887",\ +"0.2785,0.2941,0.3059,0.3332,0.3840,0.4816,0.6691",\ +"0.2629,0.2785,0.2902,0.3176,0.3684,0.4660,0.6535",\ +"0.2316,0.2473,0.2590,0.2863,0.3410,0.4348,0.6262",\ +"0.1848,0.2004,0.2121,0.2395,0.2902,0.3879,0.5754",\ +"0.0832,0.0988,0.1105,0.1379,0.1809,0.2746,0.4699",\ +"-0.1121,-0.0965,-0.0848,-0.0535,-0.0066,0.0910,0.2824"); + } + } + + + timing() { + timing_type : hold_rising; + related_pin : "A_CLK"; + when : "A_MEN" + sdf_cond : "A_MEN" + + rise_constraint("SIG2SRAM_constraint_template") { + index_1("0.0056,0.0232,0.0400,0.0728,0.1280,0.2440,0.4760"); + index_2("0.0056,0.0232,0.0400,0.0728,0.1280,0.2440,0.4760"); + values ("0.2473,0.2316,0.2160,0.1887,0.1379,0.0363,-0.1629",\ +"0.2629,0.2473,0.2316,0.2043,0.1535,0.0520,-0.1473",\ +"0.2785,0.2590,0.2434,0.2160,0.1652,0.0676,-0.1355",\ +"0.3098,0.2941,0.2785,0.2473,0.1965,0.0910,-0.1043",\ +"0.3527,0.3371,0.3215,0.2941,0.2434,0.1418,-0.0574",\ +"0.4582,0.4426,0.4270,0.3957,0.3488,0.2434,0.0480",\ +"0.6535,0.6379,0.6184,0.5910,0.5402,0.4426,0.2434"); + } + + fall_constraint("SIG2SRAM_constraint_template") { + index_1("0.0056,0.0232,0.0400,0.0728,0.1280,0.2440,0.4760"); + index_2("0.0056,0.0232,0.0400,0.0728,0.1280,0.2440,0.4760"); + values ("0.2395,0.2238,0.2121,0.1809,0.1301,0.0324,-0.1551",\ +"0.2551,0.2395,0.2277,0.1965,0.1457,0.0480,-0.1395",\ +"0.2668,0.2551,0.2395,0.2082,0.1574,0.0637,-0.1277",\ +"0.3020,0.2863,0.2707,0.2395,0.1887,0.0910,-0.0965",\ +"0.3449,0.3293,0.3176,0.2863,0.2355,0.1379,-0.0496",\ +"0.4504,0.4348,0.4191,0.3879,0.3371,0.2395,0.0559",\ +"0.6457,0.6301,0.6145,0.5871,0.5324,0.4309,0.2512"); + } + } + } +pin(A_REN) { + direction : input ; + capacitance : 0.00381634 ; + max_transition : "0.476" ; + related_power_pin : VDD; + related_ground_pin : VSS; + internal_power() { + when : "A_MEN"; + rise_power("scalar"){ + values (0.0051); + } + fall_power("scalar"){ + values (0.0030); + } + } + internal_power() { + when : "!A_MEN"; + rise_power("scalar"){ + values (0.0050); + } + fall_power("scalar"){ + values (0.0032); + } + } + timing() { + timing_type : setup_rising; + related_pin : "A_CLK"; + when : "A_MEN" + sdf_cond : "A_MEN" + + rise_constraint("SIG2SRAM_constraint_template") { + index_1("0.0056,0.0232,0.0400,0.0728,0.1280,0.2440,0.4760"); + index_2("0.0056,0.0232,0.0400,0.0728,0.1280,0.2440,0.4760"); + values ("-0.0301,-0.0145,0.0012,0.0324,0.0793,0.1809,0.3762",\ +"-0.0457,-0.0301,-0.0145,0.0168,0.0637,0.1613,0.3605",\ +"-0.0574,-0.0418,-0.0262,0.0051,0.0520,0.1496,0.3449",\ +"-0.0926,-0.0730,-0.0574,-0.0262,0.0207,0.1184,0.3137",\ +"-0.1395,-0.1238,-0.1082,-0.0770,-0.0301,0.0715,0.2707",\ +"-0.2410,-0.2254,-0.2098,-0.1746,-0.1355,-0.0340,0.1652",\ +"-0.4402,-0.4207,-0.4051,-0.3738,-0.3270,-0.2293,-0.0340"); + } + + fall_constraint("SIG2SRAM_constraint_template") { + index_1("0.0056,0.0232,0.0400,0.0728,0.1280,0.2440,0.4760"); + index_2("0.0056,0.0232,0.0400,0.0728,0.1280,0.2440,0.4760"); + values ("0.0988,0.1145,0.1262,0.1535,0.2043,0.3020,0.4855",\ +"0.0832,0.0988,0.1105,0.1418,0.1848,0.2824,0.4738",\ +"0.0676,0.0832,0.0949,0.1262,0.1730,0.2668,0.4621",\ +"0.0402,0.0559,0.0676,0.0988,0.1457,0.2434,0.4191",\ +"-0.0105,0.0012,0.0168,0.0480,0.0988,0.1965,0.3840",\ +"-0.1160,-0.0965,-0.0848,-0.0535,-0.0066,0.0988,0.2824",\ +"-0.3113,-0.2957,-0.2801,-0.2527,-0.2059,-0.1043,0.0832"); + } + } + + + timing() { + timing_type : hold_rising; + related_pin : "A_CLK"; + when : "A_MEN" + sdf_cond : "A_MEN" + + rise_constraint("SIG2SRAM_constraint_template") { + index_1("0.0056,0.0232,0.0400,0.0728,0.1280,0.2440,0.4760"); + index_2("0.0056,0.0232,0.0400,0.0728,0.1280,0.2440,0.4760"); + values ("0.2707,0.2551,0.2395,0.2121,0.1613,0.0598,-0.1395",\ +"0.2863,0.2707,0.2551,0.2238,0.1730,0.0715,-0.1238",\ +"0.2980,0.2824,0.2668,0.2395,0.1887,0.0871,-0.1121",\ +"0.3332,0.3176,0.3020,0.2707,0.2199,0.1184,-0.0809",\ +"0.3762,0.3605,0.3449,0.3176,0.2668,0.1613,-0.0340",\ +"0.4816,0.4621,0.4504,0.4191,0.3723,0.2629,0.0715",\ +"0.6770,0.6613,0.6418,0.6184,0.5637,0.4699,0.2629"); + } + + fall_constraint("SIG2SRAM_constraint_template") { + index_1("0.0056,0.0232,0.0400,0.0728,0.1280,0.2440,0.4760"); + index_2("0.0056,0.0232,0.0400,0.0728,0.1280,0.2440,0.4760"); + values ("0.2590,0.2434,0.2316,0.2004,0.1457,0.0520,-0.1355",\ +"0.2746,0.2590,0.2434,0.2160,0.1613,0.0676,-0.1199",\ +"0.2863,0.2707,0.2590,0.2277,0.1730,0.0832,-0.1082",\ +"0.3215,0.3059,0.2902,0.2590,0.2082,0.1105,-0.0770",\ +"0.3645,0.3488,0.3332,0.3059,0.2551,0.1535,-0.0340",\ +"0.4699,0.4543,0.4387,0.4074,0.3605,0.2551,0.0715",\ +"0.6652,0.6496,0.6340,0.6027,0.5520,0.4621,0.2707"); + } + } + } +pin(A_MEN) { + direction : input ; + capacitance : 0.00309605 ; + max_transition : "0.476" ; + related_power_pin : VDD; + related_ground_pin : VSS; + internal_power() { + rise_power("scalar"){ + values (0.0228); + } + fall_power("scalar"){ + values (0.0059); + } + } + timing() { + timing_type : setup_rising; + related_pin : "A_CLK"; + + rise_constraint("SIG2SRAM_constraint_template") { + index_1("0.0056,0.0232,0.0400,0.0728,0.1280,0.2440,0.4760"); + index_2("0.0056,0.0232,0.0400,0.0728,0.1280,0.2440,0.4760"); + values ("0.2043,0.2199,0.2316,0.2668,0.3098,0.4152,0.6066",\ +"0.1887,0.2043,0.2199,0.2512,0.2941,0.3996,0.5949",\ +"0.1730,0.1887,0.2043,0.2355,0.2824,0.3840,0.5793",\ +"0.1418,0.1574,0.1730,0.2043,0.2512,0.3566,0.5480",\ +"0.0949,0.1105,0.1262,0.1574,0.2043,0.3020,0.5051",\ +"-0.0066,0.0090,0.0246,0.0520,0.0988,0.2043,0.3996",\ +"-0.2020,-0.1863,-0.1746,-0.1434,-0.0965,0.0090,0.2082"); + } + + fall_constraint("SIG2SRAM_constraint_template") { + index_1("0.0056,0.0232,0.0400,0.0728,0.1280,0.2440,0.4760"); + index_2("0.0056,0.0232,0.0400,0.0728,0.1280,0.2440,0.4760"); + values ("0.2980,0.3137,0.3254,0.3527,0.4035,0.5012,0.6887",\ +"0.2824,0.2980,0.3098,0.3371,0.3879,0.4855,0.6730",\ +"0.2668,0.2824,0.2941,0.3215,0.3723,0.4699,0.6574",\ +"0.2355,0.2473,0.2629,0.2902,0.3410,0.4387,0.6262",\ +"0.1887,0.2004,0.2160,0.2395,0.2941,0.3918,0.5793",\ +"0.0871,0.1027,0.1145,0.1418,0.1848,0.2746,0.4816",\ +"-0.1082,-0.0965,-0.0809,-0.0496,-0.0027,0.0949,0.2863"); + } + } + + + timing() { + timing_type : hold_rising; + related_pin : "A_CLK"; + + rise_constraint("SIG2SRAM_constraint_template") { + index_1("0.0056,0.0232,0.0400,0.0728,0.1280,0.2440,0.4760"); + index_2("0.0056,0.0232,0.0400,0.0728,0.1280,0.2440,0.4760"); + values ("0.2512,0.2355,0.2199,0.1926,0.1418,0.0402,-0.1590",\ +"0.2668,0.2512,0.2355,0.2082,0.1574,0.0559,-0.1434",\ +"0.2824,0.2629,0.2512,0.2199,0.1691,0.0715,-0.1316",\ +"0.3137,0.2980,0.2824,0.2512,0.2004,0.0988,-0.0965",\ +"0.3566,0.3410,0.3254,0.2980,0.2473,0.1418,-0.0535",\ +"0.4621,0.4426,0.4309,0.3996,0.3527,0.2473,0.0520",\ +"0.6574,0.6418,0.6262,0.5949,0.5441,0.4465,0.2473"); + } + + fall_constraint("SIG2SRAM_constraint_template") { + index_1("0.0056,0.0232,0.0400,0.0728,0.1280,0.2440,0.4760"); + index_2("0.0056,0.0232,0.0400,0.0728,0.1280,0.2440,0.4760"); + values ("0.2395,0.2238,0.2121,0.1809,0.1301,0.0324,-0.1551",\ +"0.2551,0.2434,0.2277,0.1965,0.1457,0.0480,-0.1395",\ +"0.2707,0.2551,0.2395,0.2082,0.1574,0.0637,-0.1277",\ +"0.3020,0.2863,0.2707,0.2434,0.1926,0.0910,-0.0965",\ +"0.3449,0.3332,0.3176,0.2863,0.2355,0.1379,-0.0496",\ +"0.4504,0.4348,0.4230,0.3918,0.3410,0.2434,0.0559",\ +"0.6457,0.6301,0.6145,0.5910,0.5324,0.4387,0.2512"); + } + } + } +bus(A_BM) { + bus_type : D_7_0; + direction : input ; + capacitance : 0.00293842 ; + max_transition : "0.476" ; + pin(A_BM[7:0]) { + related_power_pin : VDD; + related_ground_pin : VSS; + internal_power() { + when : "A_MEN"; + rise_power("scalar"){ + values (0.0230); + } + fall_power("scalar"){ + values (0.0190); + } + } + internal_power() { + when : "!A_MEN"; + rise_power("scalar"){ + values (0.0251); + } + fall_power("scalar"){ + values (0.0190); + } + } + } + timing() { + timing_type : setup_rising; + related_pin : "A_CLK"; + when : "(A_WEN & A_MEN)" + sdf_cond : "A_RW_ACCESS" + + rise_constraint("SIG2SRAM_constraint_template") { + index_1("0.0056,0.0232,0.0400,0.0728,0.1280,0.2440,0.4760"); + index_2("0.0056,0.0232,0.0400,0.0728,0.1280,0.2440,0.4760"); + values ("-0.3241,-0.3085,-0.2948,-0.2626,-0.2157,-0.1112,0.0802",\ +"-0.3291,-0.3135,-0.2998,-0.2676,-0.2207,-0.1162,0.0752",\ +"-0.3336,-0.3180,-0.3043,-0.2720,-0.2252,-0.1207,0.0707",\ +"-0.3427,-0.3271,-0.3134,-0.2812,-0.2343,-0.1298,0.0616",\ +"-0.3499,-0.3343,-0.3206,-0.2884,-0.2415,-0.1370,0.0544",\ +"-0.3796,-0.3639,-0.3503,-0.3180,-0.2712,-0.1667,0.0247",\ +"-0.4376,-0.4220,-0.4083,-0.3761,-0.3292,-0.2247,-0.0333"); + } + + fall_constraint("SIG2SRAM_constraint_template") { + index_1("0.0056,0.0232,0.0400,0.0728,0.1280,0.2440,0.4760"); + index_2("0.0056,0.0232,0.0400,0.0728,0.1280,0.2440,0.4760"); + values ("-0.2860,-0.2714,-0.2577,-0.2294,-0.1786,-0.0809,0.1017",\ +"-0.2910,-0.2764,-0.2627,-0.2344,-0.1836,-0.0859,0.0967",\ +"-0.2955,-0.2808,-0.2672,-0.2388,-0.1881,-0.0904,0.0922",\ +"-0.3046,-0.2900,-0.2763,-0.2480,-0.1972,-0.0995,0.0831",\ +"-0.3118,-0.2972,-0.2835,-0.2552,-0.2044,-0.1067,0.0759",\ +"-0.3415,-0.3268,-0.3131,-0.2848,-0.2341,-0.1364,0.0462",\ +"-0.3995,-0.3849,-0.3712,-0.3429,-0.2921,-0.1945,-0.0118"); + } + } + + + timing() { + timing_type : hold_rising; + related_pin : "A_CLK"; + when : "(A_WEN & A_MEN)" + sdf_cond : "A_RW_ACCESS" + + rise_constraint("SIG2SRAM_constraint_template") { + index_1("0.0056,0.0232,0.0400,0.0728,0.1280,0.2440,0.4760"); + index_2("0.0056,0.0232,0.0400,0.0728,0.1280,0.2440,0.4760"); + values ("0.4330,0.4164,0.4037,0.3715,0.3237,0.2201,0.0278",\ +"0.4380,0.4214,0.4087,0.3765,0.3287,0.2251,0.0328",\ +"0.4425,0.4259,0.4132,0.3810,0.3331,0.2296,0.0372",\ +"0.4516,0.4350,0.4223,0.3901,0.3423,0.2387,0.0464",\ +"0.4588,0.4422,0.4295,0.3973,0.3495,0.2459,0.0536",\ +"0.4885,0.4719,0.4592,0.4270,0.3791,0.2756,0.0832",\ +"0.5466,0.5300,0.5173,0.4850,0.4372,0.3337,0.1413"); + } + + fall_constraint("SIG2SRAM_constraint_template") { + index_1("0.0056,0.0232,0.0400,0.0728,0.1280,0.2440,0.4760"); + index_2("0.0056,0.0232,0.0400,0.0728,0.1280,0.2440,0.4760"); + values ("0.3871,0.3725,0.3588,0.3305,0.2807,0.1879,0.0034",\ +"0.3921,0.3775,0.3638,0.3355,0.2857,0.1929,0.0084",\ +"0.3966,0.3820,0.3683,0.3400,0.2902,0.1974,0.0128",\ +"0.4057,0.3911,0.3774,0.3491,0.2993,0.2065,0.0220",\ +"0.4129,0.3983,0.3846,0.3563,0.3065,0.2137,0.0292",\ +"0.4426,0.4280,0.4143,0.3860,0.3362,0.2434,0.0588",\ +"0.5007,0.4860,0.4723,0.4440,0.3942,0.3014,0.1169"); + } + } +} + pin(A_CLK) { + direction : input; + capacitance : 0.00380014; + max_transition : "0.476"; + clock : "true" ; + pin_func_type : active_rising ; + + timing () { + timing_type : "min_pulse_width"; + related_pin : "A_CLK"; + rise_constraint("CLKTRAN_constraint_template") { + index_1("0.0056,0.476"); + values("0.21,0.21"); + } + } + + related_power_pin : VDD; + related_ground_pin : VSS; + + internal_power() { + when : "!A_MEN & !A_WEN & !A_REN"; + rise_power("scalar"){ + values (0); + } + fall_power("scalar"){ + values (0); + } + } + internal_power() { + when : "!A_MEN & A_WEN & !A_REN"; + rise_power("scalar"){ + values (1.0053); + } + fall_power("scalar"){ + values (0); + } + } + internal_power() { + when : "A_MEN & A_WEN & !A_REN"; + rise_power("scalar"){ + values (16.0363); + } + fall_power("scalar"){ + values (0); + } + } + internal_power() { + when : "A_MEN & A_WEN & A_REN"; + rise_power("scalar"){ + values (16.0578); + } + fall_power("scalar"){ + values (0); + } + } + internal_power() { + when : "A_MEN & !A_WEN & A_REN"; + rise_power("scalar"){ + values (12.1274); + } + fall_power("scalar"){ + values (0); + } + } + internal_power() { + when : "!A_MEN & !A_WEN & A_REN"; + rise_power("scalar"){ + values (0.2982); + } + fall_power("scalar"){ + values (0); + } + } + internal_power() { + when : "!A_MEN & A_WEN & A_REN"; + rise_power("scalar"){ + values (0.5288); + } + fall_power("scalar"){ + values (0); + } + } + internal_power() { + when : "A_MEN & !A_WEN & !A_REN"; + rise_power("scalar"){ + values (0); + } + fall_power("scalar"){ + values (0); + } + } + } + bus(A_DIN) { + bus_type : D_7_0; + direction : input ; + capacitance : 0.0030602 ; + memory_write() { + address : A_ADDR ; + clocked_on : A_CLK; + } + + max_transition : "0.476" ; + pin(A_DIN[7:0]) { + related_power_pin : VDD; + related_ground_pin : VSS; + internal_power() { + when : "A_MEN"; + rise_power("scalar"){ + values (0.0230); + } + fall_power("scalar"){ + values (0.0190); + } + } + internal_power() { + when : "!A_MEN"; + rise_power("scalar"){ + values (0.0251); + } + fall_power("scalar"){ + values (0.0190); + } + } + } + timing() { + timing_type : setup_rising; + related_pin : "A_CLK"; + when : "(A_WEN & A_MEN)"; + sdf_cond : "A_W_ACCESS"; + + rise_constraint("SIG2SRAM_constraint_template") { + index_1("0.0056,0.0232,0.0400,0.0728,0.1280,0.2440,0.4760"); + index_2("0.0056,0.0232,0.0400,0.0728,0.1280,0.2440,0.4760"); + values ("-0.3241,-0.3085,-0.2948,-0.2626,-0.2157,-0.1112,0.0802",\ +"-0.3291,-0.3135,-0.2998,-0.2676,-0.2207,-0.1162,0.0752",\ +"-0.3336,-0.3180,-0.3043,-0.2720,-0.2252,-0.1207,0.0707",\ +"-0.3427,-0.3271,-0.3134,-0.2812,-0.2343,-0.1298,0.0616",\ +"-0.3499,-0.3343,-0.3206,-0.2884,-0.2415,-0.1370,0.0544",\ +"-0.3796,-0.3639,-0.3503,-0.3180,-0.2712,-0.1667,0.0247",\ +"-0.4376,-0.4220,-0.4083,-0.3761,-0.3292,-0.2247,-0.0333"); + } + + fall_constraint("SIG2SRAM_constraint_template") { + index_1("0.0056,0.0232,0.0400,0.0728,0.1280,0.2440,0.4760"); + index_2("0.0056,0.0232,0.0400,0.0728,0.1280,0.2440,0.4760"); + values ("-0.2860,-0.2714,-0.2577,-0.2294,-0.1786,-0.0809,0.1017",\ +"-0.2910,-0.2764,-0.2627,-0.2344,-0.1836,-0.0859,0.0967",\ +"-0.2955,-0.2808,-0.2672,-0.2388,-0.1881,-0.0904,0.0922",\ +"-0.3046,-0.2900,-0.2763,-0.2480,-0.1972,-0.0995,0.0831",\ +"-0.3118,-0.2972,-0.2835,-0.2552,-0.2044,-0.1067,0.0759",\ +"-0.3415,-0.3268,-0.3131,-0.2848,-0.2341,-0.1364,0.0462",\ +"-0.3995,-0.3849,-0.3712,-0.3429,-0.2921,-0.1945,-0.0118"); + } + } + + timing() { + timing_type : hold_rising; + related_pin : "A_CLK"; + when : "(A_WEN & A_MEN)"; + sdf_cond : "A_W_ACCESS"; + + rise_constraint("SIG2SRAM_constraint_template") { + index_1("0.0056,0.0232,0.0400,0.0728,0.1280,0.2440,0.4760"); + index_2("0.0056,0.0232,0.0400,0.0728,0.1280,0.2440,0.4760"); + values ("0.4330,0.4164,0.4037,0.3715,0.3237,0.2201,0.0278",\ +"0.4380,0.4214,0.4087,0.3765,0.3287,0.2251,0.0328",\ +"0.4425,0.4259,0.4132,0.3810,0.3331,0.2296,0.0372",\ +"0.4516,0.4350,0.4223,0.3901,0.3423,0.2387,0.0464",\ +"0.4588,0.4422,0.4295,0.3973,0.3495,0.2459,0.0536",\ +"0.4885,0.4719,0.4592,0.4270,0.3791,0.2756,0.0832",\ +"0.5466,0.5300,0.5173,0.4850,0.4372,0.3337,0.1413"); + } + + fall_constraint("SIG2SRAM_constraint_template") { + index_1("0.0056,0.0232,0.0400,0.0728,0.1280,0.2440,0.4760"); + index_2("0.0056,0.0232,0.0400,0.0728,0.1280,0.2440,0.4760"); + values ("0.3871,0.3725,0.3588,0.3305,0.2807,0.1879,0.0034",\ +"0.3921,0.3775,0.3638,0.3355,0.2857,0.1929,0.0084",\ +"0.3966,0.3820,0.3683,0.3400,0.2902,0.1974,0.0128",\ +"0.4057,0.3911,0.3774,0.3491,0.2993,0.2065,0.0220",\ +"0.4129,0.3983,0.3846,0.3563,0.3065,0.2137,0.0292",\ +"0.4426,0.4280,0.4143,0.3860,0.3362,0.2434,0.0588",\ +"0.5007,0.4860,0.4723,0.4440,0.3942,0.3014,0.1169"); + } + } + } + + pin(A_BIST_EN) { + direction : input ; + capacitance : 0.00401111 ; + max_transition : "1" ; + related_power_pin : VDD; + related_ground_pin : VSS; + internal_power() { + rise_power("scalar") { + values (0); + } + fall_power("scalar") { + values (0); + } + } + } + +bus(A_BIST_ADDR) { + bus_type : A_8_0; + direction : input ; + capacitance : 0.00721489 ; + pin(A_BIST_ADDR[0]) { + capacitance : 0.00593979 ; + } + pin(A_BIST_ADDR[1]) { + capacitance : 0.00483009 ; + } + pin(A_BIST_ADDR[2]) { + capacitance : 0.006215 ; + } + pin(A_BIST_ADDR[3]) { + capacitance : 0.00766726 ; + } + pin(A_BIST_ADDR[4]) { + capacitance : 0.00488951 ; + } + pin(A_BIST_ADDR[5]) { + capacitance : 0.0091523 ; + } + pin(A_BIST_ADDR[6]) { + capacitance : 0.0109212 ; + } + pin(A_BIST_ADDR[7]) { + capacitance : 0.00774122 ; + } + max_transition : "0.476" ; + pin(A_BIST_ADDR[8:0]) { + related_power_pin : VDD; + related_ground_pin : VSS; + internal_power() { + when : "A_BIST_MEN"; + rise_power("scalar"){ + values (0.0104); + } + fall_power("scalar"){ + values (0.0041); + } + } + internal_power() { + when : "!A_BIST_MEN"; + rise_power("scalar"){ + values (0.0202); + } + fall_power("scalar"){ + values (0.0006); + } + } + } + timing() { + timing_type : setup_rising; + related_pin : "A_BIST_CLK"; + when : "((A_BIST_WEN | A_BIST_REN)& A_BIST_MEN)" + sdf_cond : "A_BIST_RW_ACCESS" + + rise_constraint("SIG2SRAM_constraint_template") { + index_1("0.0056,0.0232,0.0400,0.0728,0.1280,0.2440,0.4760"); + index_2("0.0056,0.0232,0.0400,0.0728,0.1280,0.2440,0.4760"); + values ("-0.4168,-0.3973,-0.3855,-0.3543,-0.3074,-0.2020,-0.0027",\ +"-0.4324,-0.4129,-0.4012,-0.3699,-0.3191,-0.2176,-0.0184",\ +"-0.4441,-0.4285,-0.4129,-0.3816,-0.3309,-0.2293,-0.0301",\ +"-0.4793,-0.4598,-0.4441,-0.4129,-0.3660,-0.2645,-0.0652",\ +"-0.5223,-0.5066,-0.4910,-0.4598,-0.4129,-0.3074,-0.1121",\ +"-0.6199,-0.6082,-0.5926,-0.5613,-0.5145,-0.4129,-0.2137",\ +"-0.8191,-0.8074,-0.7840,-0.7566,-0.7098,-0.6082,-0.4051"); + } + + fall_constraint("SIG2SRAM_constraint_template") { + index_1("0.0056,0.0232,0.0400,0.0728,0.1280,0.2440,0.4760"); + index_2("0.0056,0.0232,0.0400,0.0728,0.1280,0.2440,0.4760"); + values ("-0.3309,-0.3113,-0.2996,-0.2684,-0.2176,-0.1238,0.0637",\ +"-0.3465,-0.3309,-0.3152,-0.2840,-0.2332,-0.1395,0.0480",\ +"-0.3582,-0.3426,-0.3270,-0.2996,-0.2488,-0.1512,0.0324",\ +"-0.3895,-0.3738,-0.3582,-0.3309,-0.2801,-0.1863,0.0051",\ +"-0.4363,-0.4207,-0.4051,-0.3777,-0.3230,-0.2293,-0.0379",\ +"-0.5379,-0.5223,-0.5066,-0.4793,-0.4285,-0.3309,-0.1434",\ +"-0.7332,-0.7176,-0.7020,-0.6746,-0.6238,-0.5262,-0.3387"); + } + } + + + timing() { + timing_type : hold_rising; + related_pin : "A_BIST_CLK"; + when : "((A_BIST_WEN | A_BIST_REN)& A_BIST_MEN)" + sdf_cond : "A_BIST_RW_ACCESS" + + rise_constraint("SIG2SRAM_constraint_template") { + index_1("0.0056,0.0232,0.0400,0.0728,0.1280,0.2440,0.4760"); + index_2("0.0056,0.0232,0.0400,0.0728,0.1280,0.2440,0.4760"); + values ("0.5246,0.5051,0.4895,0.4582,0.4113,0.3059,0.1066",\ +"0.5402,0.5207,0.5051,0.4777,0.4270,0.3215,0.1223",\ +"0.5520,0.5324,0.5168,0.4895,0.4387,0.3371,0.1340",\ +"0.5832,0.5676,0.5520,0.5207,0.4738,0.3684,0.1691",\ +"0.6301,0.6105,0.5949,0.5676,0.5168,0.4113,0.2160",\ +"0.7316,0.7121,0.7004,0.6691,0.6223,0.5168,0.3176",\ +"0.9270,0.9230,0.8957,0.8645,0.8137,0.7121,0.5168"); + } + + fall_constraint("SIG2SRAM_constraint_template") { + index_1("0.0056,0.0232,0.0400,0.0728,0.1280,0.2440,0.4760"); + index_2("0.0056,0.0232,0.0400,0.0728,0.1280,0.2440,0.4760"); + values ("0.4309,0.4152,0.4035,0.3684,0.3215,0.2277,0.0363",\ +"0.4465,0.4309,0.4152,0.3879,0.3371,0.2395,0.0559",\ +"0.4582,0.4426,0.4309,0.3996,0.3488,0.2551,0.0715",\ +"0.4934,0.4777,0.4621,0.4348,0.3840,0.2863,0.0988",\ +"0.5363,0.5207,0.5051,0.4777,0.4270,0.3332,0.1418",\ +"0.6379,0.6262,0.6105,0.5793,0.5324,0.4348,0.2434",\ +"0.8332,0.8215,0.8059,0.7707,0.7238,0.6301,0.4387"); + } + } +} +pin(A_BIST_WEN) { + direction : input ; + capacitance : 0.00324098 ; + max_transition : "0.476" ; + related_power_pin : VDD; + related_ground_pin : VSS; + internal_power() { + when : "A_BIST_MEN"; + rise_power("scalar"){ + values (0.0037); + } + fall_power("scalar"){ + values (0.0047); + } + } + internal_power() { + when : "!A_BIST_MEN"; + rise_power("scalar"){ + values (0.0029); + } + fall_power("scalar"){ + values (0.0044); + } + } + timing() { + timing_type : setup_rising; + related_pin : "A_BIST_CLK"; + when : "A_BIST_MEN" + sdf_cond : "A_BIST_MEN" + + rise_constraint("SIG2SRAM_constraint_template") { + index_1("0.0056,0.0232,0.0400,0.0728,0.1280,0.2440,0.4760"); + index_2("0.0056,0.0232,0.0400,0.0728,0.1280,0.2440,0.4760"); + values ("0.2043,0.2199,0.2316,0.2629,0.3059,0.4113,0.6066",\ +"0.1887,0.2043,0.2160,0.2473,0.2941,0.3957,0.5949",\ +"0.1691,0.1848,0.2004,0.2316,0.2785,0.3801,0.5754",\ +"0.1379,0.1574,0.1691,0.2004,0.2473,0.3527,0.5480",\ +"0.0910,0.1066,0.1223,0.1535,0.2004,0.2980,0.4973",\ +"-0.0105,0.0051,0.0207,0.0520,0.0949,0.2004,0.3957",\ +"-0.2059,-0.1902,-0.1746,-0.1473,-0.1004,0.0051,0.2004"); + } + + fall_constraint("SIG2SRAM_constraint_template") { + index_1("0.0056,0.0232,0.0400,0.0728,0.1280,0.2440,0.4760"); + index_2("0.0056,0.0232,0.0400,0.0728,0.1280,0.2440,0.4760"); + values ("0.2941,0.3098,0.3215,0.3488,0.4035,0.4973,0.6887",\ +"0.2785,0.2941,0.3059,0.3332,0.3840,0.4816,0.6691",\ +"0.2629,0.2785,0.2902,0.3176,0.3684,0.4660,0.6535",\ +"0.2316,0.2473,0.2590,0.2863,0.3410,0.4348,0.6262",\ +"0.1848,0.2004,0.2121,0.2395,0.2902,0.3879,0.5754",\ +"0.0832,0.0988,0.1105,0.1379,0.1809,0.2746,0.4699",\ +"-0.1121,-0.0965,-0.0848,-0.0535,-0.0066,0.0910,0.2824"); + } + } + + + timing() { + timing_type : hold_rising; + related_pin : "A_BIST_CLK"; + when : "A_BIST_MEN" + sdf_cond : "A_BIST_MEN" + + rise_constraint("SIG2SRAM_constraint_template") { + index_1("0.0056,0.0232,0.0400,0.0728,0.1280,0.2440,0.4760"); + index_2("0.0056,0.0232,0.0400,0.0728,0.1280,0.2440,0.4760"); + values ("0.2473,0.2316,0.2160,0.1887,0.1379,0.0363,-0.1629",\ +"0.2629,0.2473,0.2316,0.2043,0.1535,0.0520,-0.1473",\ +"0.2785,0.2590,0.2434,0.2160,0.1652,0.0676,-0.1355",\ +"0.3098,0.2941,0.2785,0.2473,0.1965,0.0910,-0.1043",\ +"0.3527,0.3371,0.3215,0.2941,0.2434,0.1418,-0.0574",\ +"0.4582,0.4426,0.4270,0.3957,0.3488,0.2434,0.0480",\ +"0.6535,0.6379,0.6184,0.5910,0.5402,0.4426,0.2434"); + } + + fall_constraint("SIG2SRAM_constraint_template") { + index_1("0.0056,0.0232,0.0400,0.0728,0.1280,0.2440,0.4760"); + index_2("0.0056,0.0232,0.0400,0.0728,0.1280,0.2440,0.4760"); + values ("0.2395,0.2238,0.2121,0.1809,0.1301,0.0324,-0.1551",\ +"0.2551,0.2395,0.2277,0.1965,0.1457,0.0480,-0.1395",\ +"0.2668,0.2551,0.2395,0.2082,0.1574,0.0637,-0.1277",\ +"0.3020,0.2863,0.2707,0.2395,0.1887,0.0910,-0.0965",\ +"0.3449,0.3293,0.3176,0.2863,0.2355,0.1379,-0.0496",\ +"0.4504,0.4348,0.4191,0.3879,0.3371,0.2395,0.0559",\ +"0.6457,0.6301,0.6145,0.5871,0.5324,0.4309,0.2512"); + } + } + } +pin(A_BIST_REN) { + direction : input ; + capacitance : 0.00381634 ; + max_transition : "0.476" ; + related_power_pin : VDD; + related_ground_pin : VSS; + internal_power() { + when : "A_BIST_MEN"; + rise_power("scalar"){ + values (0.0051); + } + fall_power("scalar"){ + values (0.0030); + } + } + internal_power() { + when : "!A_BIST_MEN"; + rise_power("scalar"){ + values (0.0050); + } + fall_power("scalar"){ + values (0.0032); + } + } + timing() { + timing_type : setup_rising; + related_pin : "A_BIST_CLK"; + when : "A_BIST_MEN" + sdf_cond : "A_BIST_MEN" + + rise_constraint("SIG2SRAM_constraint_template") { + index_1("0.0056,0.0232,0.0400,0.0728,0.1280,0.2440,0.4760"); + index_2("0.0056,0.0232,0.0400,0.0728,0.1280,0.2440,0.4760"); + values ("-0.0301,-0.0145,0.0012,0.0324,0.0793,0.1809,0.3762",\ +"-0.0457,-0.0301,-0.0145,0.0168,0.0637,0.1613,0.3605",\ +"-0.0574,-0.0418,-0.0262,0.0051,0.0520,0.1496,0.3449",\ +"-0.0926,-0.0730,-0.0574,-0.0262,0.0207,0.1184,0.3137",\ +"-0.1395,-0.1238,-0.1082,-0.0770,-0.0301,0.0715,0.2707",\ +"-0.2410,-0.2254,-0.2098,-0.1746,-0.1355,-0.0340,0.1652",\ +"-0.4402,-0.4207,-0.4051,-0.3738,-0.3270,-0.2293,-0.0340"); + } + + fall_constraint("SIG2SRAM_constraint_template") { + index_1("0.0056,0.0232,0.0400,0.0728,0.1280,0.2440,0.4760"); + index_2("0.0056,0.0232,0.0400,0.0728,0.1280,0.2440,0.4760"); + values ("0.0988,0.1145,0.1262,0.1535,0.2043,0.3020,0.4855",\ +"0.0832,0.0988,0.1105,0.1418,0.1848,0.2824,0.4738",\ +"0.0676,0.0832,0.0949,0.1262,0.1730,0.2668,0.4621",\ +"0.0402,0.0559,0.0676,0.0988,0.1457,0.2434,0.4191",\ +"-0.0105,0.0012,0.0168,0.0480,0.0988,0.1965,0.3840",\ +"-0.1160,-0.0965,-0.0848,-0.0535,-0.0066,0.0988,0.2824",\ +"-0.3113,-0.2957,-0.2801,-0.2527,-0.2059,-0.1043,0.0832"); + } + } + + + timing() { + timing_type : hold_rising; + related_pin : "A_BIST_CLK"; + when : "A_BIST_MEN" + sdf_cond : "A_BIST_MEN" + + rise_constraint("SIG2SRAM_constraint_template") { + index_1("0.0056,0.0232,0.0400,0.0728,0.1280,0.2440,0.4760"); + index_2("0.0056,0.0232,0.0400,0.0728,0.1280,0.2440,0.4760"); + values ("0.2707,0.2551,0.2395,0.2121,0.1613,0.0598,-0.1395",\ +"0.2863,0.2707,0.2551,0.2238,0.1730,0.0715,-0.1238",\ +"0.2980,0.2824,0.2668,0.2395,0.1887,0.0871,-0.1121",\ +"0.3332,0.3176,0.3020,0.2707,0.2199,0.1184,-0.0809",\ +"0.3762,0.3605,0.3449,0.3176,0.2668,0.1613,-0.0340",\ +"0.4816,0.4621,0.4504,0.4191,0.3723,0.2629,0.0715",\ +"0.6770,0.6613,0.6418,0.6184,0.5637,0.4699,0.2629"); + } + + fall_constraint("SIG2SRAM_constraint_template") { + index_1("0.0056,0.0232,0.0400,0.0728,0.1280,0.2440,0.4760"); + index_2("0.0056,0.0232,0.0400,0.0728,0.1280,0.2440,0.4760"); + values ("0.2590,0.2434,0.2316,0.2004,0.1457,0.0520,-0.1355",\ +"0.2746,0.2590,0.2434,0.2160,0.1613,0.0676,-0.1199",\ +"0.2863,0.2707,0.2590,0.2277,0.1730,0.0832,-0.1082",\ +"0.3215,0.3059,0.2902,0.2590,0.2082,0.1105,-0.0770",\ +"0.3645,0.3488,0.3332,0.3059,0.2551,0.1535,-0.0340",\ +"0.4699,0.4543,0.4387,0.4074,0.3605,0.2551,0.0715",\ +"0.6652,0.6496,0.6340,0.6027,0.5520,0.4621,0.2707"); + } + } + } +pin(A_BIST_MEN) { + direction : input ; + capacitance : 0.00309605 ; + max_transition : "0.476" ; + related_power_pin : VDD; + related_ground_pin : VSS; + internal_power() { + rise_power("scalar"){ + values (0.0228); + } + fall_power("scalar"){ + values (0.0059); + } + } + timing() { + timing_type : setup_rising; + related_pin : "A_BIST_CLK"; + + rise_constraint("SIG2SRAM_constraint_template") { + index_1("0.0056,0.0232,0.0400,0.0728,0.1280,0.2440,0.4760"); + index_2("0.0056,0.0232,0.0400,0.0728,0.1280,0.2440,0.4760"); + values ("0.2043,0.2199,0.2316,0.2668,0.3098,0.4152,0.6066",\ +"0.1887,0.2043,0.2199,0.2512,0.2941,0.3996,0.5949",\ +"0.1730,0.1887,0.2043,0.2355,0.2824,0.3840,0.5793",\ +"0.1418,0.1574,0.1730,0.2043,0.2512,0.3566,0.5480",\ +"0.0949,0.1105,0.1262,0.1574,0.2043,0.3020,0.5051",\ +"-0.0066,0.0090,0.0246,0.0520,0.0988,0.2043,0.3996",\ +"-0.2020,-0.1863,-0.1746,-0.1434,-0.0965,0.0090,0.2082"); + } + + fall_constraint("SIG2SRAM_constraint_template") { + index_1("0.0056,0.0232,0.0400,0.0728,0.1280,0.2440,0.4760"); + index_2("0.0056,0.0232,0.0400,0.0728,0.1280,0.2440,0.4760"); + values ("0.2980,0.3137,0.3254,0.3527,0.4035,0.5012,0.6887",\ +"0.2824,0.2980,0.3098,0.3371,0.3879,0.4855,0.6730",\ +"0.2668,0.2824,0.2941,0.3215,0.3723,0.4699,0.6574",\ +"0.2355,0.2473,0.2629,0.2902,0.3410,0.4387,0.6262",\ +"0.1887,0.2004,0.2160,0.2395,0.2941,0.3918,0.5793",\ +"0.0871,0.1027,0.1145,0.1418,0.1848,0.2746,0.4816",\ +"-0.1082,-0.0965,-0.0809,-0.0496,-0.0027,0.0949,0.2863"); + } + } + + + timing() { + timing_type : hold_rising; + related_pin : "A_BIST_CLK"; + + rise_constraint("SIG2SRAM_constraint_template") { + index_1("0.0056,0.0232,0.0400,0.0728,0.1280,0.2440,0.4760"); + index_2("0.0056,0.0232,0.0400,0.0728,0.1280,0.2440,0.4760"); + values ("0.2512,0.2355,0.2199,0.1926,0.1418,0.0402,-0.1590",\ +"0.2668,0.2512,0.2355,0.2082,0.1574,0.0559,-0.1434",\ +"0.2824,0.2629,0.2512,0.2199,0.1691,0.0715,-0.1316",\ +"0.3137,0.2980,0.2824,0.2512,0.2004,0.0988,-0.0965",\ +"0.3566,0.3410,0.3254,0.2980,0.2473,0.1418,-0.0535",\ +"0.4621,0.4426,0.4309,0.3996,0.3527,0.2473,0.0520",\ +"0.6574,0.6418,0.6262,0.5949,0.5441,0.4465,0.2473"); + } + + fall_constraint("SIG2SRAM_constraint_template") { + index_1("0.0056,0.0232,0.0400,0.0728,0.1280,0.2440,0.4760"); + index_2("0.0056,0.0232,0.0400,0.0728,0.1280,0.2440,0.4760"); + values ("0.2395,0.2238,0.2121,0.1809,0.1301,0.0324,-0.1551",\ +"0.2551,0.2434,0.2277,0.1965,0.1457,0.0480,-0.1395",\ +"0.2707,0.2551,0.2395,0.2082,0.1574,0.0637,-0.1277",\ +"0.3020,0.2863,0.2707,0.2434,0.1926,0.0910,-0.0965",\ +"0.3449,0.3332,0.3176,0.2863,0.2355,0.1379,-0.0496",\ +"0.4504,0.4348,0.4230,0.3918,0.3410,0.2434,0.0559",\ +"0.6457,0.6301,0.6145,0.5910,0.5324,0.4387,0.2512"); + } + } + } +bus(A_BIST_BM) { + bus_type : D_7_0; + direction : input ; + capacitance : 0.00236845 ; + max_transition : "0.476" ; + pin(A_BIST_BM[7:0]) { + related_power_pin : VDD; + related_ground_pin : VSS; + internal_power() { + when : "A_BIST_MEN"; + rise_power("scalar"){ + values (0.0230); + } + fall_power("scalar"){ + values (0.0190); + } + } + internal_power() { + when : "!A_BIST_MEN"; + rise_power("scalar"){ + values (0.0251); + } + fall_power("scalar"){ + values (0.0190); + } + } + } + timing() { + timing_type : setup_rising; + related_pin : "A_BIST_CLK"; + when : "(A_BIST_WEN & A_BIST_MEN)" + sdf_cond : "A_BIST_RW_ACCESS" + + rise_constraint("SIG2SRAM_constraint_template") { + index_1("0.0056,0.0232,0.0400,0.0728,0.1280,0.2440,0.4760"); + index_2("0.0056,0.0232,0.0400,0.0728,0.1280,0.2440,0.4760"); + values ("-0.3241,-0.3085,-0.2948,-0.2626,-0.2157,-0.1112,0.0802",\ +"-0.3291,-0.3135,-0.2998,-0.2676,-0.2207,-0.1162,0.0752",\ +"-0.3336,-0.3180,-0.3043,-0.2720,-0.2252,-0.1207,0.0707",\ +"-0.3427,-0.3271,-0.3134,-0.2812,-0.2343,-0.1298,0.0616",\ +"-0.3499,-0.3343,-0.3206,-0.2884,-0.2415,-0.1370,0.0544",\ +"-0.3796,-0.3639,-0.3503,-0.3180,-0.2712,-0.1667,0.0247",\ +"-0.4376,-0.4220,-0.4083,-0.3761,-0.3292,-0.2247,-0.0333"); + } + + fall_constraint("SIG2SRAM_constraint_template") { + index_1("0.0056,0.0232,0.0400,0.0728,0.1280,0.2440,0.4760"); + index_2("0.0056,0.0232,0.0400,0.0728,0.1280,0.2440,0.4760"); + values ("-0.2860,-0.2714,-0.2577,-0.2294,-0.1786,-0.0809,0.1017",\ +"-0.2910,-0.2764,-0.2627,-0.2344,-0.1836,-0.0859,0.0967",\ +"-0.2955,-0.2808,-0.2672,-0.2388,-0.1881,-0.0904,0.0922",\ +"-0.3046,-0.2900,-0.2763,-0.2480,-0.1972,-0.0995,0.0831",\ +"-0.3118,-0.2972,-0.2835,-0.2552,-0.2044,-0.1067,0.0759",\ +"-0.3415,-0.3268,-0.3131,-0.2848,-0.2341,-0.1364,0.0462",\ +"-0.3995,-0.3849,-0.3712,-0.3429,-0.2921,-0.1945,-0.0118"); + } + } + + + timing() { + timing_type : hold_rising; + related_pin : "A_BIST_CLK"; + when : "(A_BIST_WEN & A_BIST_MEN)" + sdf_cond : "A_BIST_RW_ACCESS" + + rise_constraint("SIG2SRAM_constraint_template") { + index_1("0.0056,0.0232,0.0400,0.0728,0.1280,0.2440,0.4760"); + index_2("0.0056,0.0232,0.0400,0.0728,0.1280,0.2440,0.4760"); + values ("0.4330,0.4164,0.4037,0.3715,0.3237,0.2201,0.0278",\ +"0.4380,0.4214,0.4087,0.3765,0.3287,0.2251,0.0328",\ +"0.4425,0.4259,0.4132,0.3810,0.3331,0.2296,0.0372",\ +"0.4516,0.4350,0.4223,0.3901,0.3423,0.2387,0.0464",\ +"0.4588,0.4422,0.4295,0.3973,0.3495,0.2459,0.0536",\ +"0.4885,0.4719,0.4592,0.4270,0.3791,0.2756,0.0832",\ +"0.5466,0.5300,0.5173,0.4850,0.4372,0.3337,0.1413"); + } + + fall_constraint("SIG2SRAM_constraint_template") { + index_1("0.0056,0.0232,0.0400,0.0728,0.1280,0.2440,0.4760"); + index_2("0.0056,0.0232,0.0400,0.0728,0.1280,0.2440,0.4760"); + values ("0.3871,0.3725,0.3588,0.3305,0.2807,0.1879,0.0034",\ +"0.3921,0.3775,0.3638,0.3355,0.2857,0.1929,0.0084",\ +"0.3966,0.3820,0.3683,0.3400,0.2902,0.1974,0.0128",\ +"0.4057,0.3911,0.3774,0.3491,0.2993,0.2065,0.0220",\ +"0.4129,0.3983,0.3846,0.3563,0.3065,0.2137,0.0292",\ +"0.4426,0.4280,0.4143,0.3860,0.3362,0.2434,0.0588",\ +"0.5007,0.4860,0.4723,0.4440,0.3942,0.3014,0.1169"); + } + } +} + pin(A_BIST_CLK) { + direction : input; + capacitance : 0.00380014; + max_transition : "0.476"; + clock : "true" ; + pin_func_type : active_rising ; + + timing () { + timing_type : "min_pulse_width"; + related_pin : "A_BIST_CLK"; + rise_constraint("CLKTRAN_constraint_template") { + index_1("0.0056,0.476"); + values("0.21,0.21"); + } + } + + related_power_pin : VDD; + related_ground_pin : VSS; + + internal_power() { + when : "!A_BIST_MEN & !A_BIST_WEN & !A_BIST_REN"; + rise_power("scalar"){ + values (0); + } + fall_power("scalar"){ + values (0); + } + } + internal_power() { + when : "!A_BIST_MEN & A_BIST_WEN & !A_BIST_REN"; + rise_power("scalar"){ + values (1.0053); + } + fall_power("scalar"){ + values (0); + } + } + internal_power() { + when : "A_BIST_MEN & A_BIST_WEN & !A_BIST_REN"; + rise_power("scalar"){ + values (16.0363); + } + fall_power("scalar"){ + values (0); + } + } + internal_power() { + when : "A_BIST_MEN & A_BIST_WEN & A_BIST_REN"; + rise_power("scalar"){ + values (16.0578); + } + fall_power("scalar"){ + values (0); + } + } + internal_power() { + when : "A_BIST_MEN & !A_BIST_WEN & A_BIST_REN"; + rise_power("scalar"){ + values (12.1274); + } + fall_power("scalar"){ + values (0); + } + } + internal_power() { + when : "!A_BIST_MEN & !A_BIST_WEN & A_BIST_REN"; + rise_power("scalar"){ + values (0.2982); + } + fall_power("scalar"){ + values (0); + } + } + internal_power() { + when : "!A_BIST_MEN & A_BIST_WEN & A_BIST_REN"; + rise_power("scalar"){ + values (0.5288); + } + fall_power("scalar"){ + values (0); + } + } + internal_power() { + when : "A_BIST_MEN & !A_BIST_WEN & !A_BIST_REN"; + rise_power("scalar"){ + values (0); + } + fall_power("scalar"){ + values (0); + } + } + } + bus(A_BIST_DIN) { + bus_type : D_7_0; + direction : input ; + capacitance : 0.00232602 ; + memory_write() { + address : A_BIST_ADDR ; + clocked_on : A_BIST_CLK; + } + + max_transition : "0.476" ; + pin(A_BIST_DIN[7:0]) { + related_power_pin : VDD; + related_ground_pin : VSS; + internal_power() { + when : "A_BIST_MEN"; + rise_power("scalar"){ + values (0.0230); + } + fall_power("scalar"){ + values (0.0190); + } + } + internal_power() { + when : "!A_BIST_MEN"; + rise_power("scalar"){ + values (0.0251); + } + fall_power("scalar"){ + values (0.0190); + } + } + } + timing() { + timing_type : setup_rising; + related_pin : "A_BIST_CLK"; + when : "(A_BIST_WEN & A_BIST_MEN)"; + sdf_cond : "A_BIST_W_ACCESS"; + + rise_constraint("SIG2SRAM_constraint_template") { + index_1("0.0056,0.0232,0.0400,0.0728,0.1280,0.2440,0.4760"); + index_2("0.0056,0.0232,0.0400,0.0728,0.1280,0.2440,0.4760"); + values ("-0.3241,-0.3085,-0.2948,-0.2626,-0.2157,-0.1112,0.0802",\ +"-0.3291,-0.3135,-0.2998,-0.2676,-0.2207,-0.1162,0.0752",\ +"-0.3336,-0.3180,-0.3043,-0.2720,-0.2252,-0.1207,0.0707",\ +"-0.3427,-0.3271,-0.3134,-0.2812,-0.2343,-0.1298,0.0616",\ +"-0.3499,-0.3343,-0.3206,-0.2884,-0.2415,-0.1370,0.0544",\ +"-0.3796,-0.3639,-0.3503,-0.3180,-0.2712,-0.1667,0.0247",\ +"-0.4376,-0.4220,-0.4083,-0.3761,-0.3292,-0.2247,-0.0333"); + } + + fall_constraint("SIG2SRAM_constraint_template") { + index_1("0.0056,0.0232,0.0400,0.0728,0.1280,0.2440,0.4760"); + index_2("0.0056,0.0232,0.0400,0.0728,0.1280,0.2440,0.4760"); + values ("-0.2860,-0.2714,-0.2577,-0.2294,-0.1786,-0.0809,0.1017",\ +"-0.2910,-0.2764,-0.2627,-0.2344,-0.1836,-0.0859,0.0967",\ +"-0.2955,-0.2808,-0.2672,-0.2388,-0.1881,-0.0904,0.0922",\ +"-0.3046,-0.2900,-0.2763,-0.2480,-0.1972,-0.0995,0.0831",\ +"-0.3118,-0.2972,-0.2835,-0.2552,-0.2044,-0.1067,0.0759",\ +"-0.3415,-0.3268,-0.3131,-0.2848,-0.2341,-0.1364,0.0462",\ +"-0.3995,-0.3849,-0.3712,-0.3429,-0.2921,-0.1945,-0.0118"); + } + } + + timing() { + timing_type : hold_rising; + related_pin : "A_BIST_CLK"; + when : "(A_BIST_WEN & A_BIST_MEN)"; + sdf_cond : "A_BIST_W_ACCESS"; + + rise_constraint("SIG2SRAM_constraint_template") { + index_1("0.0056,0.0232,0.0400,0.0728,0.1280,0.2440,0.4760"); + index_2("0.0056,0.0232,0.0400,0.0728,0.1280,0.2440,0.4760"); + values ("0.4330,0.4164,0.4037,0.3715,0.3237,0.2201,0.0278",\ +"0.4380,0.4214,0.4087,0.3765,0.3287,0.2251,0.0328",\ +"0.4425,0.4259,0.4132,0.3810,0.3331,0.2296,0.0372",\ +"0.4516,0.4350,0.4223,0.3901,0.3423,0.2387,0.0464",\ +"0.4588,0.4422,0.4295,0.3973,0.3495,0.2459,0.0536",\ +"0.4885,0.4719,0.4592,0.4270,0.3791,0.2756,0.0832",\ +"0.5466,0.5300,0.5173,0.4850,0.4372,0.3337,0.1413"); + } + + fall_constraint("SIG2SRAM_constraint_template") { + index_1("0.0056,0.0232,0.0400,0.0728,0.1280,0.2440,0.4760"); + index_2("0.0056,0.0232,0.0400,0.0728,0.1280,0.2440,0.4760"); + values ("0.3871,0.3725,0.3588,0.3305,0.2807,0.1879,0.0034",\ +"0.3921,0.3775,0.3638,0.3355,0.2857,0.1929,0.0084",\ +"0.3966,0.3820,0.3683,0.3400,0.2902,0.1974,0.0128",\ +"0.4057,0.3911,0.3774,0.3491,0.2993,0.2065,0.0220",\ +"0.4129,0.3983,0.3846,0.3563,0.3065,0.2137,0.0292",\ +"0.4426,0.4280,0.4143,0.3860,0.3362,0.2434,0.0588",\ +"0.5007,0.4860,0.4723,0.4440,0.3942,0.3014,0.1169"); + } + } + } + +bus(A_DOUT) { + + bus_type : D_7_0; + direction : output ; + capacitance : 0 ; + max_capacitance : 0.064 ; + memory_read() { + address : A_ADDR ; + } + pin(A_DOUT[7:0]) { + related_power_pin : VDD; + related_ground_pin : VSS; + internal_power() { + rise_power("scalar") { + values (0); + } + fall_power("scalar") { + values (0); + } + } + } + timing() { + related_pin : "A_CLK"; + timing_type : rising_edge ; + timing_sense : non_unate ; + + cell_rise(SIG2SRAM_delay_template) { + index_1("0.0056,0.0232,0.0400,0.0728,0.1280,0.2440,0.4760"); + index_2("0.0008,0.0014,0.0051,0.0100,0.0339,0.0640"); + values ("2.9590,2.9606,2.9682,2.9769,3.0094,3.0452",\ +"2.9653,2.9669,2.9746,2.9833,3.0157,3.0516",\ +"2.9674,2.9690,2.9767,2.9854,3.0178,3.0537",\ +"2.9805,2.9821,2.9897,2.9984,3.0309,3.0667",\ +"2.9867,2.9883,2.9959,3.0046,3.0371,3.0729",\ +"3.0181,3.0197,3.0274,3.0361,3.0685,3.1044",\ +"3.0726,3.0742,3.0819,3.0906,3.1230,3.1589"); + } + cell_fall(SIG2SRAM_delay_template) { + index_1("0.0056,0.0232,0.0400,0.0728,0.1280,0.2440,0.4760"); + index_2("0.0008,0.0014,0.0051,0.0100,0.0339,0.0640"); + values ("2.8979,2.8992,2.9052,2.9124,2.9389,2.9655",\ +"2.9042,2.9056,2.9116,2.9187,2.9452,2.9718",\ +"2.9063,2.9077,2.9137,2.9208,2.9473,2.9739",\ +"2.9194,2.9207,2.9267,2.9339,2.9604,2.9870",\ +"2.9256,2.9269,2.9329,2.9401,2.9666,2.9932",\ +"2.9570,2.9584,2.9644,2.9715,2.9980,3.0246",\ +"3.0116,3.0129,3.0189,3.0260,3.0525,3.0792"); + } + + rise_transition(SRAM_load_template) { + index_1("0.0008,0.0014,0.0051,0.0100,0.0339,0.0640"); + values ("0.0326,0.0341,0.0428,0.0518,0.0923,0.1492"); + } + fall_transition(SRAM_load_template) { + index_1("0.0008,0.0014,0.0051,0.0100,0.0339,0.0640"); + values ("0.0254,0.0265,0.0335,0.0402,0.0707,0.1039"); + } + } +} +cell_leakage_power : 49.5039; +} +} diff --git a/flow/platforms/ihp-sg13g2/lib/RM_IHPSG13_1P_64x64_c2_bm_bist_fast_1p32V_m55C.lib b/flow/platforms/ihp-sg13g2/lib/RM_IHPSG13_1P_64x64_c2_bm_bist_fast_1p32V_m55C.lib index b96e5c15b5..a05111b808 100644 --- a/flow/platforms/ihp-sg13g2/lib/RM_IHPSG13_1P_64x64_c2_bm_bist_fast_1p32V_m55C.lib +++ b/flow/platforms/ihp-sg13g2/lib/RM_IHPSG13_1P_64x64_c2_bm_bist_fast_1p32V_m55C.lib @@ -1441,7 +1441,7 @@ bus(A_DOUT) { bus_type : D_63_0; direction : output ; capacitance : 0 ; - max_capacitance : "6.4e-14" ; + max_capacitance : 0.064 ; memory_read() { address : A_ADDR ; } diff --git a/flow/platforms/ihp-sg13g2/lib/RM_IHPSG13_1P_64x64_c2_bm_bist_slow_1p08V_125C.lib b/flow/platforms/ihp-sg13g2/lib/RM_IHPSG13_1P_64x64_c2_bm_bist_slow_1p08V_125C.lib index a905e25023..a31f67c95c 100644 --- a/flow/platforms/ihp-sg13g2/lib/RM_IHPSG13_1P_64x64_c2_bm_bist_slow_1p08V_125C.lib +++ b/flow/platforms/ihp-sg13g2/lib/RM_IHPSG13_1P_64x64_c2_bm_bist_slow_1p08V_125C.lib @@ -1441,7 +1441,7 @@ bus(A_DOUT) { bus_type : D_63_0; direction : output ; capacitance : 0 ; - max_capacitance : "6.4e-14" ; + max_capacitance : 0.064 ; memory_read() { address : A_ADDR ; } diff --git a/flow/platforms/ihp-sg13g2/lib/RM_IHPSG13_1P_64x64_c2_bm_bist_typ_1p20V_25C.lib b/flow/platforms/ihp-sg13g2/lib/RM_IHPSG13_1P_64x64_c2_bm_bist_typ_1p20V_25C.lib index 2285a995c5..c03e55faf3 100644 --- a/flow/platforms/ihp-sg13g2/lib/RM_IHPSG13_1P_64x64_c2_bm_bist_typ_1p20V_25C.lib +++ b/flow/platforms/ihp-sg13g2/lib/RM_IHPSG13_1P_64x64_c2_bm_bist_typ_1p20V_25C.lib @@ -1441,7 +1441,7 @@ bus(A_DOUT) { bus_type : D_63_0; direction : output ; capacitance : 0 ; - max_capacitance : "6.4e-14" ; + max_capacitance : 0.064 ; memory_read() { address : A_ADDR ; } diff --git a/flow/platforms/ihp-sg13g2/lib/RM_IHPSG13_1P_8192x32_c4_fast_1p32V_m55C.lib b/flow/platforms/ihp-sg13g2/lib/RM_IHPSG13_1P_8192x32_c4_fast_1p32V_m55C.lib new file mode 100644 index 0000000000..aca9f09181 --- /dev/null +++ b/flow/platforms/ihp-sg13g2/lib/RM_IHPSG13_1P_8192x32_c4_fast_1p32V_m55C.lib @@ -0,0 +1,787 @@ +/* ------------------------------------------------------*/ +/**/ +/* Copyright 2023 IHP PDK Authors*/ +/**/ +/* Licensed under the Apache License, Version 2.0 (the "License");*/ +/* you may not use this file except in compliance with the License.*/ +/* You may obtain a copy of the License at*/ +/* */ +/* https://www.apache.org/licenses/LICENSE-2.0*/ +/* */ +/* Unless required by applicable law or agreed to in writing, software*/ +/* distributed under the License is distributed on an "AS IS" BASIS,*/ +/* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.*/ +/* See the License for the specific language governing permissions and*/ +/* limitations under the License.*/ +/* */ +/* Generated on Mon Apr 7 14:15:43 2025 */ +/* */ +/* ------------------------------------------------------ */ +library(RM_IHPSG13_1P_8192x32_c4_fast_1p32V_m55C) { + technology (cmos) ; + delay_model : table_lookup ; + define ("add_pg_pin_to_lib", "library", "boolean"); + add_pg_pin_to_lib : true; + voltage_map ( VDD, 1.32); + voltage_map ( VDDARRAY, 1.32); + voltage_map ( VSS, 0.000000 ); + + date : "Mon Apr 7 14:15:42 2025" ; + comment : "IHP Microelectronics GmbH, 2023" ; + revision : 1.0.0 ; + simulation : true ; + nom_process : 1 ; + nom_temperature : -55 ; + nom_voltage : 1.32 ; + + operating_conditions("fast_1p32V_m55C"){ + process : 1 ; + temperature : -55 ; + voltage : 1.32 ; + tree_type : "balanced_tree" ; + } + + default_operating_conditions : fast_1p32V_m55C ; + default_max_transition : 1.0 ; + default_fanout_load : 1.0 ; + default_inout_pin_cap : 0.0 ; + default_input_pin_cap : 0.0 ; + default_output_pin_cap : 0.0 ; + default_cell_leakage_power : 0.0 ; + default_leakage_power_density : 0.0 ; + + slew_lower_threshold_pct_rise : 30 ; + slew_upper_threshold_pct_rise : 70 ; + input_threshold_pct_fall : 50 ; + output_threshold_pct_fall : 50 ; + input_threshold_pct_rise : 50 ; + output_threshold_pct_rise : 50 ; + slew_lower_threshold_pct_fall : 30 ; + slew_upper_threshold_pct_fall : 70 ; + slew_derate_from_library : 0.5; + k_volt_cell_leakage_power : 0.0 ; + k_temp_cell_leakage_power : 0.0 ; + k_process_cell_leakage_power : 0.0 ; + k_volt_internal_power : 0.0 ; + k_temp_internal_power : 0.0 ; + k_process_internal_power : 0.0 ; + + capacitive_load_unit (1,pf) ; + voltage_unit : "1V" ; + current_unit : "1uA" ; + time_unit : "1ns" ; + leakage_power_unit : "1nW" ; + pulling_resistance_unit : "1kohm"; + /* + ------------------------------------------------------------------------------------------ + implicit units overview: + cell_area unit : "um" + internal_power unit : "1e-12 * J/toggle = 1 * uW/MHz" + (capacitive_load_unit * voltage_unit^2) per toggle event + ------------------------------------------------------------------------------------------ + */ + library_features(report_delay_calculation); + define_cell_area (pad_drivers,pad_driver_sites) ; + + lu_table_template(CLKTRAN_constraint_template) { + variable_1 : constrained_pin_transition; + index_1 ( "0.010, 0.050, 0.200, 0.400, 1.000" ); + } + lu_table_template(SRAM_load_template) { + variable_1 : total_output_net_capacitance; + index_1 ( "0.0008,0.0014,0.0051,0.0100,0.0339,0.0640" ); + } + lu_table_template(SIG2SRAM_constraint_template) { + variable_1 : related_pin_transition; + variable_2 : constrained_pin_transition; + index_1 ( "0.0040,0.0176,0.0344,0.0656,0.1120,0.2016,0.3800" ); + index_2 ( "0.0040,0.0176,0.0344,0.0656,0.1120,0.2016,0.3800" ); + } + + lu_table_template(SIG2SRAM_delay_template) { + variable_1 : input_net_transition; + variable_2 : total_output_net_capacitance; + index_1 ( "0.0040,0.0176,0.0344,0.0656,0.1120,0.2016,0.3800" ); + index_2 ( "0.0008,0.0014,0.0051,0.0100,0.0339,0.0640" ); + } + + type (D_31_0) { + base_type : array; + data_type : bit; + bit_width : 32; + bit_from : 31; + bit_to : 0; + downto : true; + } + + type (A_12_0) { + base_type : array; + data_type : bit; + bit_width : 13; + bit_from : 12; + bit_to : 0; + downto : true; + } + +cell(RM_IHPSG13_1P_8192x32_c4) { +pg_pin (VDD) { + pg_type : primary_power; + voltage_name : VDD; +} +pg_pin (VDDARRAY) { + pg_type : primary_power; + voltage_name : VDDARRAY; +} +pg_pin (VSS) { + pg_type : primary_ground; + voltage_name : VSS; +} + +memory() { + type : ram; + address_width : 13; + word_width : 32; +} + +interface_timing : false; +bus_naming_style : "%s[%d]" ; +area : 939914.928 ; + + pin(A_DLY) { + direction : input ; + capacitance : 0.00421562 ; + max_transition : "1" ; + related_power_pin : VDD; + related_ground_pin : VSS; + internal_power() { + rise_power("scalar") { + values (0); + } + fall_power("scalar") { + values (0); + } + } + } + +bus(A_ADDR) { + bus_type : A_12_0; + direction : input ; + capacitance : 0.00691085 ; + pin(A_ADDR[0]) { + capacitance : 0.00562034 ; + } + pin(A_ADDR[1]) { + capacitance : 0.00462655 ; + } + pin(A_ADDR[2]) { + capacitance : 0.00594295 ; + } + pin(A_ADDR[3]) { + capacitance : 0.00723434 ; + } + pin(A_ADDR[4]) { + capacitance : 0.00481603 ; + } + pin(A_ADDR[5]) { + capacitance : 0.00868123 ; + } + pin(A_ADDR[6]) { + capacitance : 0.010187 ; + } + pin(A_ADDR[7]) { + capacitance : 0.00734489 ; + } + pin(A_ADDR[8]) { + capacitance : 0.00904175 ; + } + pin(A_ADDR[9]) { + capacitance : 0.0074973 ; + } + pin(A_ADDR[10]) { + capacitance : 0.00825659 ; + } + pin(A_ADDR[11]) { + capacitance : 0.00869568 ; + } + max_transition : "0.38" ; + pin(A_ADDR[12:0]) { + related_power_pin : VDD; + related_ground_pin : VSS; + internal_power() { + when : "A_MEN"; + rise_power("scalar"){ + values (0.0008); + } + fall_power("scalar"){ + values (0.0009); + } + } + internal_power() { + when : "!A_MEN"; + rise_power("scalar"){ + values (0.0190); + } + fall_power("scalar"){ + values (0.0013); + } + } + } + timing() { + timing_type : setup_rising; + related_pin : "A_CLK"; + when : "((A_WEN | A_REN)& A_MEN)" + sdf_cond : "A_RW_ACCESS" + + rise_constraint("SIG2SRAM_constraint_template") { + index_1("0.0040,0.0176,0.0344,0.0656,0.1120,0.2016,0.3800"); + index_2("0.0040,0.0176,0.0344,0.0656,0.1120,0.2016,0.3800"); + values ("-0.2371,-0.2215,-0.2098,-0.1824,-0.1434,-0.0691,0.0676",\ +"-0.2449,-0.2332,-0.2176,-0.1902,-0.1551,-0.0770,0.0559",\ +"-0.2605,-0.2488,-0.2332,-0.2059,-0.1707,-0.0965,0.0441",\ +"-0.2879,-0.2723,-0.2605,-0.2332,-0.1941,-0.1199,0.0168",\ +"-0.3230,-0.3113,-0.2996,-0.2723,-0.2332,-0.1590,-0.0184",\ +"-0.4012,-0.3895,-0.3738,-0.3465,-0.3074,-0.2332,-0.0965",\ +"-0.5379,-0.5262,-0.5105,-0.4832,-0.4480,-0.3699,-0.2332"); + } + + fall_constraint("SIG2SRAM_constraint_template") { + index_1("0.0040,0.0176,0.0344,0.0656,0.1120,0.2016,0.3800"); + index_2("0.0040,0.0176,0.0344,0.0656,0.1120,0.2016,0.3800"); + values ("-0.1785,-0.1707,-0.1551,-0.1277,-0.0887,-0.0184,0.1145",\ +"-0.1902,-0.1785,-0.1629,-0.1355,-0.1004,-0.0262,0.1027",\ +"-0.2059,-0.1941,-0.1785,-0.1512,-0.1160,-0.0418,0.0871",\ +"-0.2293,-0.2176,-0.2059,-0.1785,-0.1434,-0.0691,0.0598",\ +"-0.2684,-0.2566,-0.2449,-0.2176,-0.1824,-0.1082,0.0207",\ +"-0.3465,-0.3348,-0.3191,-0.2918,-0.2566,-0.1824,-0.0535",\ +"-0.4832,-0.4715,-0.4559,-0.4324,-0.3934,-0.3191,-0.1902"); + } + } + + + timing() { + timing_type : hold_rising; + related_pin : "A_CLK"; + when : "((A_WEN | A_REN)& A_MEN)" + sdf_cond : "A_RW_ACCESS" + + rise_constraint("SIG2SRAM_constraint_template") { + index_1("0.0040,0.0176,0.0344,0.0656,0.1120,0.2016,0.3800"); + index_2("0.0040,0.0176,0.0344,0.0656,0.1120,0.2016,0.3800"); + values ("0.3410,0.3293,0.3137,0.2863,0.2473,0.1730,0.0324",\ +"0.3488,0.3371,0.3215,0.2941,0.2590,0.1809,0.0480",\ +"0.3684,0.3527,0.3371,0.3098,0.2746,0.1965,0.0598",\ +"0.3918,0.3762,0.3645,0.3371,0.2980,0.2238,0.0871",\ +"0.4309,0.4152,0.4035,0.3762,0.3371,0.2629,0.1223",\ +"0.5051,0.4934,0.4777,0.4504,0.4113,0.3371,0.1965",\ +"0.6418,0.6262,0.6145,0.5871,0.5520,0.4738,0.3332"); + } + + fall_constraint("SIG2SRAM_constraint_template") { + index_1("0.0040,0.0176,0.0344,0.0656,0.1120,0.2016,0.3800"); + index_2("0.0040,0.0176,0.0344,0.0656,0.1120,0.2016,0.3800"); + values ("0.2824,0.2707,0.2551,0.2277,0.1926,0.1184,-0.0105",\ +"0.2902,0.2785,0.2668,0.2395,0.2043,0.1301,0.0012",\ +"0.3059,0.2941,0.2824,0.2551,0.2199,0.1457,0.0168",\ +"0.3332,0.3215,0.3059,0.2785,0.2434,0.1691,0.0402",\ +"0.3723,0.3605,0.3449,0.3176,0.2824,0.2121,0.0793",\ +"0.4465,0.4348,0.4230,0.3918,0.3566,0.2824,0.1535",\ +"0.5832,0.5715,0.5598,0.5324,0.4934,0.4191,0.2902"); + } + } +} +pin(A_WEN) { + direction : input ; + capacitance : 0.00341384 ; + max_transition : "0.38" ; + related_power_pin : VDD; + related_ground_pin : VSS; + internal_power() { + when : "A_MEN"; + rise_power("scalar"){ + values (0.0017); + } + fall_power("scalar"){ + values (0.0129); + } + } + internal_power() { + when : "!A_MEN"; + rise_power("scalar"){ + values (0.0026); + } + fall_power("scalar"){ + values (0.0312); + } + } + timing() { + timing_type : setup_rising; + related_pin : "A_CLK"; + when : "A_MEN" + sdf_cond : "A_MEN" + + rise_constraint("SIG2SRAM_constraint_template") { + index_1("0.0040,0.0176,0.0344,0.0656,0.1120,0.2016,0.3800"); + index_2("0.0040,0.0176,0.0344,0.0656,0.1120,0.2016,0.3800"); + values ("0.1418,0.1496,0.1652,0.1887,0.2316,0.3059,0.4465",\ +"0.1301,0.1379,0.1535,0.1809,0.2199,0.2941,0.4348",\ +"0.1145,0.1262,0.1379,0.1652,0.2043,0.2785,0.4191",\ +"0.0871,0.0949,0.1105,0.1379,0.1770,0.2512,0.3879",\ +"0.0480,0.0598,0.0754,0.0988,0.1379,0.2082,0.3527",\ +"-0.0262,-0.0145,0.0012,0.0246,0.0676,0.1379,0.2785",\ +"-0.1668,-0.1551,-0.1395,-0.1121,-0.0730,0.0012,0.1418"); + } + + fall_constraint("SIG2SRAM_constraint_template") { + index_1("0.0040,0.0176,0.0344,0.0656,0.1120,0.2016,0.3800"); + index_2("0.0040,0.0176,0.0344,0.0656,0.1120,0.2016,0.3800"); + values ("0.2082,0.2160,0.2316,0.2590,0.2941,0.3684,0.5012",\ +"0.1926,0.2043,0.2199,0.2473,0.2824,0.3566,0.4895",\ +"0.1770,0.1887,0.2043,0.2316,0.2668,0.3410,0.4777",\ +"0.1535,0.1652,0.1770,0.2043,0.2395,0.3137,0.4504",\ +"0.1145,0.1262,0.1379,0.1652,0.2043,0.2746,0.4113",\ +"0.0402,0.0520,0.0676,0.0910,0.1262,0.2004,0.3332",\ +"-0.0965,-0.0848,-0.0730,-0.0457,-0.0066,0.0637,0.2004"); + } + } + + + timing() { + timing_type : hold_rising; + related_pin : "A_CLK"; + when : "A_MEN" + sdf_cond : "A_MEN" + + rise_constraint("SIG2SRAM_constraint_template") { + index_1("0.0040,0.0176,0.0344,0.0656,0.1120,0.2016,0.3800"); + index_2("0.0040,0.0176,0.0344,0.0656,0.1120,0.2016,0.3800"); + values ("0.1770,0.1652,0.1496,0.1223,0.0793,0.0090,-0.1316",\ +"0.1848,0.1730,0.1574,0.1301,0.0910,0.0168,-0.1199",\ +"0.2004,0.1887,0.1770,0.1496,0.1066,0.0363,-0.1043",\ +"0.2277,0.2160,0.2004,0.1730,0.1340,0.0598,-0.0809",\ +"0.2668,0.2551,0.2395,0.2121,0.1730,0.0988,-0.0418",\ +"0.3410,0.3293,0.3137,0.2863,0.2434,0.1730,0.0324",\ +"0.4816,0.4699,0.4543,0.4230,0.3801,0.3098,0.1730"); + } + + fall_constraint("SIG2SRAM_constraint_template") { + index_1("0.0040,0.0176,0.0344,0.0656,0.1120,0.2016,0.3800"); + index_2("0.0040,0.0176,0.0344,0.0656,0.1120,0.2016,0.3800"); + values ("0.1613,0.1496,0.1379,0.1066,0.0715,0.0012,-0.1355",\ +"0.1730,0.1613,0.1457,0.1184,0.0832,0.0129,-0.1238",\ +"0.1887,0.1770,0.1613,0.1340,0.0988,0.0246,-0.1121",\ +"0.2121,0.2043,0.1887,0.1613,0.1223,0.0520,-0.0848",\ +"0.2512,0.2434,0.2277,0.2004,0.1613,0.0910,-0.0457",\ +"0.3254,0.3176,0.3020,0.2746,0.2355,0.1652,0.0324",\ +"0.4660,0.4543,0.4387,0.4113,0.3723,0.3020,0.1691"); + } + } + } +pin(A_REN) { + direction : input ; + capacitance : 0.00390661 ; + max_transition : "0.38" ; + related_power_pin : VDD; + related_ground_pin : VSS; + internal_power() { + when : "A_MEN"; + rise_power("scalar"){ + values (0.0053); + } + fall_power("scalar"){ + values (0.0148); + } + } + internal_power() { + when : "!A_MEN"; + rise_power("scalar"){ + values (0.0413); + } + fall_power("scalar"){ + values (0.0209); + } + } + timing() { + timing_type : setup_rising; + related_pin : "A_CLK"; + when : "A_MEN" + sdf_cond : "A_MEN" + + rise_constraint("SIG2SRAM_constraint_template") { + index_1("0.0040,0.0176,0.0344,0.0656,0.1120,0.2016,0.3800"); + index_2("0.0040,0.0176,0.0344,0.0656,0.1120,0.2016,0.3800"); + values ("-0.0027,0.0090,0.0246,0.0520,0.0910,0.1613,0.3020",\ +"-0.0105,0.0012,0.0129,0.0363,0.0793,0.1535,0.2902",\ +"-0.0262,-0.0145,-0.0027,0.0246,0.0637,0.1379,0.2785",\ +"-0.0535,-0.0418,-0.0262,0.0012,0.0363,0.1105,0.2512",\ +"-0.0926,-0.0809,-0.0652,-0.0418,-0.0027,0.0715,0.2121",\ +"-0.1668,-0.1551,-0.1395,-0.1082,-0.0770,-0.0027,0.1379",\ +"-0.3035,-0.2918,-0.2762,-0.2488,-0.2137,-0.1434,-0.0027"); + } + + fall_constraint("SIG2SRAM_constraint_template") { + index_1("0.0040,0.0176,0.0344,0.0656,0.1120,0.2016,0.3800"); + index_2("0.0040,0.0176,0.0344,0.0656,0.1120,0.2016,0.3800"); + values ("0.0832,0.0949,0.1105,0.1379,0.1730,0.2473,0.3801",\ +"0.0754,0.0832,0.0988,0.1223,0.1613,0.2355,0.3684",\ +"0.0598,0.0676,0.0832,0.1066,0.1457,0.2121,0.3527",\ +"0.0324,0.0441,0.0598,0.0871,0.1223,0.1926,0.3293",\ +"-0.0066,0.0051,0.0168,0.0480,0.0832,0.1535,0.2902",\ +"-0.0809,-0.0691,-0.0574,-0.0301,0.0090,0.0832,0.2121",\ +"-0.2176,-0.2059,-0.1941,-0.1668,-0.1277,-0.0574,0.0793"); + } + } + + + timing() { + timing_type : hold_rising; + related_pin : "A_CLK"; + when : "A_MEN" + sdf_cond : "A_MEN" + + rise_constraint("SIG2SRAM_constraint_template") { + index_1("0.0040,0.0176,0.0344,0.0656,0.1120,0.2016,0.3800"); + index_2("0.0040,0.0176,0.0344,0.0656,0.1120,0.2016,0.3800"); + values ("0.1887,0.1770,0.1613,0.1340,0.0949,0.0207,-0.1160",\ +"0.1965,0.1848,0.1730,0.1457,0.1027,0.0324,-0.1082",\ +"0.2160,0.2004,0.1887,0.1613,0.1184,0.0480,-0.0926",\ +"0.2395,0.2277,0.2121,0.1848,0.1457,0.0715,-0.0652",\ +"0.2785,0.2668,0.2512,0.2238,0.1848,0.1105,-0.0262",\ +"0.3527,0.3410,0.3254,0.2980,0.2551,0.1848,0.0480",\ +"0.4934,0.4816,0.4660,0.4387,0.3957,0.3254,0.1887"); + } + + fall_constraint("SIG2SRAM_constraint_template") { + index_1("0.0040,0.0176,0.0344,0.0656,0.1120,0.2016,0.3800"); + index_2("0.0040,0.0176,0.0344,0.0656,0.1120,0.2016,0.3800"); + values ("0.1730,0.1613,0.1496,0.1184,0.0793,0.0129,-0.1238",\ +"0.1848,0.1730,0.1574,0.1301,0.0910,0.0207,-0.1121",\ +"0.2004,0.1887,0.1730,0.1457,0.1066,0.0363,-0.1004",\ +"0.2238,0.2121,0.2004,0.1691,0.1340,0.0598,-0.0730",\ +"0.2629,0.2512,0.2395,0.2121,0.1691,0.0988,-0.0340",\ +"0.3371,0.3254,0.3137,0.2863,0.2434,0.1730,0.0402",\ +"0.4777,0.4660,0.4504,0.4230,0.3840,0.3137,0.1809"); + } + } + } +pin(A_MEN) { + direction : input ; + capacitance : 0.00326046 ; + max_transition : "0.38" ; + related_power_pin : VDD; + related_ground_pin : VSS; + internal_power() { + rise_power("scalar"){ + values (0.3230); + } + fall_power("scalar"){ + values (0.0171); + } + } + timing() { + timing_type : setup_rising; + related_pin : "A_CLK"; + + rise_constraint("SIG2SRAM_constraint_template") { + index_1("0.0040,0.0176,0.0344,0.0656,0.1120,0.2016,0.3800"); + index_2("0.0040,0.0176,0.0344,0.0656,0.1120,0.2016,0.3800"); + values ("0.1418,0.1496,0.1652,0.1926,0.2316,0.3059,0.4465",\ +"0.1301,0.1379,0.1535,0.1809,0.2199,0.2941,0.4348",\ +"0.1145,0.1262,0.1418,0.1652,0.2043,0.2785,0.4191",\ +"0.0871,0.0949,0.1105,0.1379,0.1770,0.2512,0.3879",\ +"0.0480,0.0598,0.0754,0.0988,0.1379,0.2082,0.3488",\ +"-0.0262,-0.0145,0.0012,0.0285,0.0676,0.1379,0.2785",\ +"-0.1668,-0.1551,-0.1395,-0.1121,-0.0730,0.0012,0.1379"); + } + + fall_constraint("SIG2SRAM_constraint_template") { + index_1("0.0040,0.0176,0.0344,0.0656,0.1120,0.2016,0.3800"); + index_2("0.0040,0.0176,0.0344,0.0656,0.1120,0.2016,0.3800"); + values ("0.2082,0.2199,0.2316,0.2590,0.2980,0.3723,0.5051",\ +"0.1965,0.2082,0.2199,0.2473,0.2863,0.3605,0.4934",\ +"0.1809,0.1926,0.2043,0.2316,0.2707,0.3449,0.4777",\ +"0.1574,0.1691,0.1809,0.2082,0.2434,0.3176,0.4543",\ +"0.1145,0.1262,0.1418,0.1691,0.2043,0.2785,0.4113",\ +"0.0441,0.0559,0.0676,0.0949,0.1301,0.2004,0.3332",\ +"-0.0965,-0.0848,-0.0691,-0.0418,-0.0066,0.0676,0.2004"); + } + } + + + timing() { + timing_type : hold_rising; + related_pin : "A_CLK"; + + rise_constraint("SIG2SRAM_constraint_template") { + index_1("0.0040,0.0176,0.0344,0.0656,0.1120,0.2016,0.3800"); + index_2("0.0040,0.0176,0.0344,0.0656,0.1120,0.2016,0.3800"); + values ("0.1770,0.1652,0.1535,0.1262,0.0832,0.0129,-0.1277",\ +"0.1887,0.1770,0.1613,0.1340,0.0949,0.0207,-0.1199",\ +"0.2043,0.1926,0.1770,0.1496,0.1105,0.0363,-0.1043",\ +"0.2277,0.2160,0.2043,0.1770,0.1379,0.0598,-0.0770",\ +"0.2668,0.2551,0.2434,0.2160,0.1730,0.0988,-0.0379",\ +"0.3449,0.3332,0.3176,0.2902,0.2473,0.1730,0.0363",\ +"0.4816,0.4699,0.4543,0.4270,0.3840,0.3098,0.1770"); + } + + fall_constraint("SIG2SRAM_constraint_template") { + index_1("0.0040,0.0176,0.0344,0.0656,0.1120,0.2016,0.3800"); + index_2("0.0040,0.0176,0.0344,0.0656,0.1120,0.2016,0.3800"); + values ("0.1613,0.1496,0.1379,0.1105,0.0715,0.0012,-0.1355",\ +"0.1730,0.1613,0.1496,0.1184,0.0832,0.0129,-0.1238",\ +"0.1887,0.1770,0.1652,0.1340,0.0988,0.0285,-0.1121",\ +"0.2121,0.2043,0.1887,0.1613,0.1223,0.0520,-0.0848",\ +"0.2551,0.2434,0.2277,0.2004,0.1613,0.0910,-0.0418",\ +"0.3293,0.3176,0.3020,0.2746,0.2395,0.1652,0.0324",\ +"0.4660,0.4543,0.4426,0.4113,0.3762,0.3020,0.1691"); + } + } + } + pin(A_CLK) { + direction : input; + capacitance : 0.00389386; + max_transition : "0.38"; + clock : "true" ; + pin_func_type : active_rising ; + + timing () { + timing_type : "min_pulse_width"; + related_pin : "A_CLK"; + rise_constraint("CLKTRAN_constraint_template") { + index_1("0.004,0.38"); + values("0.12,0.12"); + } + } + + related_power_pin : VDD; + related_ground_pin : VSS; + + internal_power() { + when : "!A_MEN & !A_WEN & !A_REN"; + rise_power("scalar"){ + values (0); + } + fall_power("scalar"){ + values (0); + } + } + internal_power() { + when : "!A_MEN & A_WEN & !A_REN"; + rise_power("scalar"){ + values (3.2671); + } + fall_power("scalar"){ + values (0); + } + } + internal_power() { + when : "A_MEN & A_WEN & !A_REN"; + rise_power("scalar"){ + values (315.7495); + } + fall_power("scalar"){ + values (0); + } + } + internal_power() { + when : "A_MEN & A_WEN & A_REN"; + rise_power("scalar"){ + values (289.6324); + } + fall_power("scalar"){ + values (0); + } + } + internal_power() { + when : "A_MEN & !A_WEN & A_REN"; + rise_power("scalar"){ + values (259.5684); + } + fall_power("scalar"){ + values (0); + } + } + internal_power() { + when : "!A_MEN & !A_WEN & A_REN"; + rise_power("scalar"){ + values (0.8404); + } + fall_power("scalar"){ + values (0); + } + } + internal_power() { + when : "!A_MEN & A_WEN & A_REN"; + rise_power("scalar"){ + values (1.7652); + } + fall_power("scalar"){ + values (0); + } + } + internal_power() { + when : "A_MEN & !A_WEN & !A_REN"; + rise_power("scalar"){ + values (0); + } + fall_power("scalar"){ + values (0); + } + } + } + bus(A_DIN) { + bus_type : D_31_0; + direction : input ; + capacitance : 0.00450445 ; + memory_write() { + address : A_ADDR ; + clocked_on : A_CLK; + } + + max_transition : "0.38" ; + pin(A_DIN[31:0]) { + related_power_pin : VDD; + related_ground_pin : VSS; + internal_power() { + when : "A_MEN"; + rise_power("scalar"){ + values (0.1665); + } + fall_power("scalar"){ + values (0.1326); + } + } + internal_power() { + when : "!A_MEN"; + rise_power("scalar"){ + values (0.2001); + } + fall_power("scalar"){ + values (0.1415); + } + } + } + timing() { + timing_type : setup_rising; + related_pin : "A_CLK"; + when : "(A_WEN & A_MEN)"; + sdf_cond : "A_W_ACCESS"; + + rise_constraint("SIG2SRAM_constraint_template") { + index_1("0.0040,0.0176,0.0344,0.0656,0.1120,0.2016,0.3800"); + index_2("0.0040,0.0176,0.0344,0.0656,0.1120,0.2016,0.3800"); + values ("-0.2404,-0.2306,-0.2140,-0.1876,-0.1515,-0.0773,0.0565",\ +"-0.2443,-0.2345,-0.2179,-0.1915,-0.1554,-0.0812,0.0526",\ +"-0.2482,-0.2384,-0.2218,-0.1954,-0.1593,-0.0851,0.0487",\ +"-0.2513,-0.2415,-0.2249,-0.1986,-0.1624,-0.0882,0.0456",\ +"-0.2637,-0.2540,-0.2374,-0.2110,-0.1749,-0.1007,0.0331",\ +"-0.2812,-0.2715,-0.2548,-0.2285,-0.1923,-0.1181,0.0157",\ +"-0.3089,-0.2991,-0.2825,-0.2561,-0.2200,-0.1458,-0.0120"); + } + + fall_constraint("SIG2SRAM_constraint_template") { + index_1("0.0040,0.0176,0.0344,0.0656,0.1120,0.2016,0.3800"); + index_2("0.0040,0.0176,0.0344,0.0656,0.1120,0.2016,0.3800"); + values ("-0.2101,-0.1994,-0.1857,-0.1583,-0.1212,-0.0509,0.0790",\ +"-0.2140,-0.2032,-0.1896,-0.1622,-0.1251,-0.0548,0.0751",\ +"-0.2179,-0.2072,-0.1935,-0.1661,-0.1290,-0.0587,0.0712",\ +"-0.2210,-0.2103,-0.1966,-0.1693,-0.1322,-0.0619,0.0680",\ +"-0.2335,-0.2227,-0.2091,-0.1817,-0.1446,-0.0743,0.0556",\ +"-0.2509,-0.2402,-0.2265,-0.1992,-0.1621,-0.0918,0.0381",\ +"-0.2786,-0.2678,-0.2542,-0.2268,-0.1897,-0.1194,0.0105"); + } + } + + timing() { + timing_type : hold_rising; + related_pin : "A_CLK"; + when : "(A_WEN & A_MEN)"; + sdf_cond : "A_W_ACCESS"; + + rise_constraint("SIG2SRAM_constraint_template") { + index_1("0.0040,0.0176,0.0344,0.0656,0.1120,0.2016,0.3800"); + index_2("0.0040,0.0176,0.0344,0.0656,0.1120,0.2016,0.3800"); + values ("0.3491,0.3383,0.3237,0.2973,0.2602,0.1840,0.0502",\ +"0.3530,0.3422,0.3276,0.3012,0.2641,0.1879,0.0541",\ +"0.3569,0.3461,0.3315,0.3051,0.2680,0.1918,0.0580",\ +"0.3600,0.3493,0.3346,0.3082,0.2711,0.1950,0.0612",\ +"0.3724,0.3617,0.3471,0.3207,0.2836,0.2074,0.0736",\ +"0.3899,0.3792,0.3645,0.3382,0.3010,0.2249,0.0911",\ +"0.4176,0.4068,0.3922,0.3658,0.3287,0.2525,0.1187"); + } + + fall_constraint("SIG2SRAM_constraint_template") { + index_1("0.0040,0.0176,0.0344,0.0656,0.1120,0.2016,0.3800"); + index_2("0.0040,0.0176,0.0344,0.0656,0.1120,0.2016,0.3800"); + values ("0.3149,0.3041,0.2895,0.2631,0.2260,0.1557,0.0239",\ +"0.3188,0.3080,0.2934,0.2670,0.2299,0.1596,0.0278",\ +"0.3227,0.3119,0.2973,0.2709,0.2338,0.1635,0.0317",\ +"0.3258,0.3151,0.3004,0.2741,0.2370,0.1666,0.0348",\ +"0.3383,0.3275,0.3129,0.2865,0.2494,0.1791,0.0473",\ +"0.3557,0.3450,0.3303,0.3040,0.2669,0.1965,0.0647",\ +"0.3834,0.3726,0.3580,0.3316,0.2945,0.2242,0.0924"); + } + } + } + +bus(A_DOUT) { + + bus_type : D_31_0; + direction : output ; + capacitance : 0 ; + max_capacitance : 0.064 ; + memory_read() { + address : A_ADDR ; + } + pin(A_DOUT[31:0]) { + related_power_pin : VDD; + related_ground_pin : VSS; + internal_power() { + rise_power("scalar") { + values (0); + } + fall_power("scalar") { + values (0); + } + } + } + timing() { + related_pin : "A_CLK"; + timing_type : rising_edge ; + timing_sense : non_unate ; + + cell_rise(SIG2SRAM_delay_template) { + index_1("0.0040,0.0176,0.0344,0.0656,0.1120,0.2016,0.3800"); + index_2("0.0008,0.0014,0.0051,0.0100,0.0339,0.0640"); + values ("3.4575,3.4585,3.4634,3.4689,3.4898,3.5133",\ +"3.4638,3.4648,3.4697,3.4752,3.4961,3.5196",\ +"3.4681,3.4691,3.4739,3.4794,3.5003,3.5238",\ +"3.4673,3.4683,3.4732,3.4787,3.4996,3.5231",\ +"3.4809,3.4819,3.4867,3.4922,3.5131,3.5366",\ +"3.4980,3.4990,3.5038,3.5093,3.5302,3.5538",\ +"3.5258,3.5268,3.5317,3.5372,3.5581,3.5816"); + } + cell_fall(SIG2SRAM_delay_template) { + index_1("0.0040,0.0176,0.0344,0.0656,0.1120,0.2016,0.3800"); + index_2("0.0008,0.0014,0.0051,0.0100,0.0339,0.0640"); + values ("3.4233,3.4241,3.4282,3.4327,3.4498,3.4665",\ +"3.4296,3.4304,3.4345,3.4390,3.4561,3.4728",\ +"3.4338,3.4347,3.4387,3.4432,3.4603,3.4771",\ +"3.4331,3.4339,3.4380,3.4425,3.4596,3.4763",\ +"3.4466,3.4475,3.4515,3.4561,3.4731,3.4899",\ +"3.4637,3.4646,3.4686,3.4732,3.4902,3.5070",\ +"3.4915,3.4924,3.4964,3.5010,3.5181,3.5348"); + } + + rise_transition(SRAM_load_template) { + index_1("0.0008,0.0014,0.0051,0.0100,0.0339,0.0640"); + values ("0.0206,0.0210,0.0265,0.0323,0.0606,0.0955"); + } + fall_transition(SRAM_load_template) { + index_1("0.0008,0.0014,0.0051,0.0100,0.0339,0.0640"); + values ("0.0170,0.0177,0.0222,0.0270,0.0451,0.0644"); + } + } +} +cell_leakage_power : 7513.5058; +} +} diff --git a/flow/platforms/ihp-sg13g2/lib/RM_IHPSG13_1P_8192x32_c4_slow_1p08V_125C.lib b/flow/platforms/ihp-sg13g2/lib/RM_IHPSG13_1P_8192x32_c4_slow_1p08V_125C.lib new file mode 100644 index 0000000000..5bf7026180 --- /dev/null +++ b/flow/platforms/ihp-sg13g2/lib/RM_IHPSG13_1P_8192x32_c4_slow_1p08V_125C.lib @@ -0,0 +1,787 @@ +/* ------------------------------------------------------*/ +/**/ +/* Copyright 2023 IHP PDK Authors*/ +/**/ +/* Licensed under the Apache License, Version 2.0 (the "License");*/ +/* you may not use this file except in compliance with the License.*/ +/* You may obtain a copy of the License at*/ +/* */ +/* https://www.apache.org/licenses/LICENSE-2.0*/ +/* */ +/* Unless required by applicable law or agreed to in writing, software*/ +/* distributed under the License is distributed on an "AS IS" BASIS,*/ +/* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.*/ +/* See the License for the specific language governing permissions and*/ +/* limitations under the License.*/ +/* */ +/* Generated on Mon Apr 7 14:15:42 2025 */ +/* */ +/* ------------------------------------------------------ */ +library(RM_IHPSG13_1P_8192x32_c4_slow_1p08V_125C) { + technology (cmos) ; + delay_model : table_lookup ; + define ("add_pg_pin_to_lib", "library", "boolean"); + add_pg_pin_to_lib : true; + voltage_map ( VDD, 1.08); + voltage_map ( VDDARRAY, 1.08); + voltage_map ( VSS, 0.000000 ); + + date : "Mon Apr 7 14:15:42 2025" ; + comment : "IHP Microelectronics GmbH, 2023" ; + revision : 1.0.0 ; + simulation : true ; + nom_process : 1 ; + nom_temperature : 125 ; + nom_voltage : 1.08 ; + + operating_conditions("slow_1p08V_125C"){ + process : 1 ; + temperature : 125 ; + voltage : 1.08 ; + tree_type : "balanced_tree" ; + } + + default_operating_conditions : slow_1p08V_125C ; + default_max_transition : 1.0 ; + default_fanout_load : 1.0 ; + default_inout_pin_cap : 0.0 ; + default_input_pin_cap : 0.0 ; + default_output_pin_cap : 0.0 ; + default_cell_leakage_power : 0.0 ; + default_leakage_power_density : 0.0 ; + + slew_lower_threshold_pct_rise : 30 ; + slew_upper_threshold_pct_rise : 70 ; + input_threshold_pct_fall : 50 ; + output_threshold_pct_fall : 50 ; + input_threshold_pct_rise : 50 ; + output_threshold_pct_rise : 50 ; + slew_lower_threshold_pct_fall : 30 ; + slew_upper_threshold_pct_fall : 70 ; + slew_derate_from_library : 0.5; + k_volt_cell_leakage_power : 0.0 ; + k_temp_cell_leakage_power : 0.0 ; + k_process_cell_leakage_power : 0.0 ; + k_volt_internal_power : 0.0 ; + k_temp_internal_power : 0.0 ; + k_process_internal_power : 0.0 ; + + capacitive_load_unit (1,pf) ; + voltage_unit : "1V" ; + current_unit : "1uA" ; + time_unit : "1ns" ; + leakage_power_unit : "1nW" ; + pulling_resistance_unit : "1kohm"; + /* + ------------------------------------------------------------------------------------------ + implicit units overview: + cell_area unit : "um" + internal_power unit : "1e-12 * J/toggle = 1 * uW/MHz" + (capacitive_load_unit * voltage_unit^2) per toggle event + ------------------------------------------------------------------------------------------ + */ + library_features(report_delay_calculation); + define_cell_area (pad_drivers,pad_driver_sites) ; + + lu_table_template(CLKTRAN_constraint_template) { + variable_1 : constrained_pin_transition; + index_1 ( "0.010, 0.050, 0.200, 0.400, 1.000" ); + } + lu_table_template(SRAM_load_template) { + variable_1 : total_output_net_capacitance; + index_1 ( "0.0008,0.0014,0.0051,0.0100,0.0339,0.0640" ); + } + lu_table_template(SIG2SRAM_constraint_template) { + variable_1 : related_pin_transition; + variable_2 : constrained_pin_transition; + index_1 ( "0.0080,0.0288,0.0616,0.1072,0.1920,0.3496,0.5952" ); + index_2 ( "0.0080,0.0288,0.0616,0.1072,0.1920,0.3496,0.5952" ); + } + + lu_table_template(SIG2SRAM_delay_template) { + variable_1 : input_net_transition; + variable_2 : total_output_net_capacitance; + index_1 ( "0.0080,0.0288,0.0616,0.1072,0.1920,0.3496,0.5952" ); + index_2 ( "0.0008,0.0014,0.0051,0.0100,0.0339,0.0640" ); + } + + type (D_31_0) { + base_type : array; + data_type : bit; + bit_width : 32; + bit_from : 31; + bit_to : 0; + downto : true; + } + + type (A_12_0) { + base_type : array; + data_type : bit; + bit_width : 13; + bit_from : 12; + bit_to : 0; + downto : true; + } + +cell(RM_IHPSG13_1P_8192x32_c4) { +pg_pin (VDD) { + pg_type : primary_power; + voltage_name : VDD; +} +pg_pin (VDDARRAY) { + pg_type : primary_power; + voltage_name : VDDARRAY; +} +pg_pin (VSS) { + pg_type : primary_ground; + voltage_name : VSS; +} + +memory() { + type : ram; + address_width : 13; + word_width : 32; +} + +interface_timing : false; +bus_naming_style : "%s[%d]" ; +area : 939914.928 ; + + pin(A_DLY) { + direction : input ; + capacitance : 0.00387999 ; + max_transition : "1" ; + related_power_pin : VDD; + related_ground_pin : VSS; + internal_power() { + rise_power("scalar") { + values (0); + } + fall_power("scalar") { + values (0); + } + } + } + +bus(A_ADDR) { + bus_type : A_12_0; + direction : input ; + capacitance : 0.0077013 ; + pin(A_ADDR[0]) { + capacitance : 0.00625349 ; + } + pin(A_ADDR[1]) { + capacitance : 0.00507435 ; + } + pin(A_ADDR[2]) { + capacitance : 0.00656707 ; + } + pin(A_ADDR[3]) { + capacitance : 0.0083133 ; + } + pin(A_ADDR[4]) { + capacitance : 0.00507219 ; + } + pin(A_ADDR[5]) { + capacitance : 0.00964344 ; + } + pin(A_ADDR[6]) { + capacitance : 0.0119653 ; + } + pin(A_ADDR[7]) { + capacitance : 0.00827606 ; + } + pin(A_ADDR[8]) { + capacitance : 0.0110771 ; + } + pin(A_ADDR[9]) { + capacitance : 0.00811634 ; + } + pin(A_ADDR[10]) { + capacitance : 0.00916579 ; + } + pin(A_ADDR[11]) { + capacitance : 0.0103086 ; + } + max_transition : "0.5952" ; + pin(A_ADDR[12:0]) { + related_power_pin : VDD; + related_ground_pin : VSS; + internal_power() { + when : "A_MEN"; + rise_power("scalar"){ + values (0.0795); + } + fall_power("scalar"){ + values (0.0217); + } + } + internal_power() { + when : "!A_MEN"; + rise_power("scalar"){ + values (0.2280); + } + fall_power("scalar"){ + values (0.6252); + } + } + } + timing() { + timing_type : setup_rising; + related_pin : "A_CLK"; + when : "((A_WEN | A_REN)& A_MEN)" + sdf_cond : "A_RW_ACCESS" + + rise_constraint("SIG2SRAM_constraint_template") { + index_1("0.0080,0.0288,0.0616,0.1072,0.1920,0.3496,0.5952"); + index_2("0.0080,0.0288,0.0616,0.1072,0.1920,0.3496,0.5952"); + values ("-0.7371,-0.7176,-0.6863,-0.6434,-0.5652,-0.4168,-0.1980",\ +"-0.7566,-0.7371,-0.7059,-0.6629,-0.5848,-0.4363,-0.2137",\ +"-0.7879,-0.7645,-0.7332,-0.6902,-0.6121,-0.4637,-0.2449",\ +"-0.8309,-0.8074,-0.7762,-0.7332,-0.6551,-0.5066,-0.2879",\ +"-0.9051,-0.8895,-0.8543,-0.8113,-0.7332,-0.5887,-0.3660",\ +"-1.0418,-1.0262,-0.9949,-0.9480,-0.8699,-0.7293,-0.5027",\ +"-1.2684,-1.2449,-1.2176,-1.1707,-1.0965,-0.9480,-0.7293"); + } + + fall_constraint("SIG2SRAM_constraint_template") { + index_1("0.0080,0.0288,0.0616,0.1072,0.1920,0.3496,0.5952"); + index_2("0.0080,0.0288,0.0616,0.1072,0.1920,0.3496,0.5952"); + values ("-0.5926,-0.5730,-0.5418,-0.4988,-0.4246,-0.2879,-0.0730",\ +"-0.6121,-0.5926,-0.5613,-0.5223,-0.4441,-0.3074,-0.0887",\ +"-0.6395,-0.6199,-0.5926,-0.5496,-0.4715,-0.3348,-0.1160",\ +"-0.6863,-0.6668,-0.6355,-0.5965,-0.5184,-0.3777,-0.1590",\ +"-0.7605,-0.7410,-0.7137,-0.6746,-0.5926,-0.4559,-0.2410",\ +"-0.9012,-0.8816,-0.8504,-0.8113,-0.7332,-0.5926,-0.3895",\ +"-1.1238,-1.1043,-1.0769,-1.0379,-0.9559,-0.8191,-0.6004"); + } + } + + + timing() { + timing_type : hold_rising; + related_pin : "A_CLK"; + when : "((A_WEN | A_REN)& A_MEN)" + sdf_cond : "A_RW_ACCESS" + + rise_constraint("SIG2SRAM_constraint_template") { + index_1("0.0080,0.0288,0.0616,0.1072,0.1920,0.3496,0.5952"); + index_2("0.0080,0.0288,0.0616,0.1072,0.1920,0.3496,0.5952"); + values ("0.8488,0.8293,0.7980,0.7551,0.6730,0.5285,0.3098",\ +"0.8684,0.8488,0.8176,0.7746,0.6926,0.5480,0.3254",\ +"0.8996,0.8801,0.8449,0.8020,0.7238,0.5754,0.3527",\ +"0.9426,0.9191,0.8918,0.8488,0.7668,0.6223,0.3996",\ +"1.0168,1.0012,0.9699,0.9230,0.8449,0.7004,0.4777",\ +"1.1574,1.1379,1.1105,1.0598,0.9816,0.8371,0.6184",\ +"1.3801,1.3605,1.3254,1.2980,1.2043,1.0637,0.8371"); + } + + fall_constraint("SIG2SRAM_constraint_template") { + index_1("0.0080,0.0288,0.0616,0.1072,0.1920,0.3496,0.5952"); + index_2("0.0080,0.0288,0.0616,0.1072,0.1920,0.3496,0.5952"); + values ("0.6965,0.6770,0.6496,0.6066,0.5246,0.3918,0.1730",\ +"0.7160,0.6965,0.6652,0.6262,0.5441,0.4113,0.1965",\ +"0.7473,0.7277,0.6965,0.6535,0.5754,0.4426,0.2238",\ +"0.7863,0.7707,0.7395,0.7004,0.6223,0.4855,0.2629",\ +"0.8684,0.8449,0.8176,0.7785,0.7004,0.5637,0.3449",\ +"1.0051,0.9855,0.9855,0.9113,0.8332,0.7004,0.4895",\ +"1.2277,1.2082,1.1809,1.1379,1.0598,0.9230,0.7004"); + } + } +} +pin(A_WEN) { + direction : input ; + capacitance : 0.00313551 ; + max_transition : "0.5952" ; + related_power_pin : VDD; + related_ground_pin : VSS; + internal_power() { + when : "A_MEN"; + rise_power("scalar"){ + values (0.0757); + } + fall_power("scalar"){ + values (0.0732); + } + } + internal_power() { + when : "!A_MEN"; + rise_power("scalar"){ + values (0.1615); + } + fall_power("scalar"){ + values (0.0187); + } + } + timing() { + timing_type : setup_rising; + related_pin : "A_CLK"; + when : "A_MEN" + sdf_cond : "A_MEN" + + rise_constraint("SIG2SRAM_constraint_template") { + index_1("0.0080,0.0288,0.0616,0.1072,0.1920,0.3496,0.5952"); + index_2("0.0080,0.0288,0.0616,0.1072,0.1920,0.3496,0.5952"); + values ("0.3137,0.3332,0.3605,0.4035,0.4816,0.6223,0.8488",\ +"0.2980,0.3176,0.3410,0.3840,0.4660,0.6027,0.8293",\ +"0.2629,0.2824,0.3098,0.3527,0.4348,0.5754,0.7980",\ +"0.2199,0.2395,0.2668,0.3098,0.3918,0.5324,0.7590",\ +"0.1418,0.1613,0.1887,0.2316,0.3137,0.4348,0.6730",\ +"0.0012,0.0207,0.0520,0.0910,0.1730,0.3098,0.5285",\ +"-0.2215,-0.2020,-0.1746,-0.1277,-0.0496,0.0910,0.3098"); + } + + fall_constraint("SIG2SRAM_constraint_template") { + index_1("0.0080,0.0288,0.0616,0.1072,0.1920,0.3496,0.5952"); + index_2("0.0080,0.0288,0.0616,0.1072,0.1920,0.3496,0.5952"); + values ("0.4504,0.4699,0.4973,0.5324,0.6027,0.7355,0.9699",\ +"0.4309,0.4504,0.4777,0.5129,0.5910,0.7160,0.9504",\ +"0.3996,0.4191,0.4465,0.4816,0.5520,0.6848,0.9191",\ +"0.3605,0.3762,0.4035,0.4387,0.5168,0.6418,0.8723",\ +"0.2785,0.2980,0.3215,0.3605,0.4348,0.5637,0.7980",\ +"0.1379,0.1574,0.1809,0.2199,0.2980,0.4309,0.6457",\ +"-0.0809,-0.0613,-0.0340,0.0051,0.0832,0.2160,0.4191"); + } + } + + + timing() { + timing_type : hold_rising; + related_pin : "A_CLK"; + when : "A_MEN" + sdf_cond : "A_MEN" + + rise_constraint("SIG2SRAM_constraint_template") { + index_1("0.0080,0.0288,0.0616,0.1072,0.1920,0.3496,0.5952"); + index_2("0.0080,0.0288,0.0616,0.1072,0.1920,0.3496,0.5952"); + values ("0.3723,0.3527,0.3215,0.2785,0.1965,0.0559,-0.1668",\ +"0.3918,0.3723,0.3449,0.2980,0.2160,0.0754,-0.1473",\ +"0.4152,0.3996,0.3684,0.3254,0.2434,0.1066,-0.1199",\ +"0.4621,0.4465,0.4152,0.3723,0.2863,0.1496,-0.0730",\ +"0.5324,0.5207,0.4895,0.4465,0.3645,0.2199,0.0051",\ +"0.6770,0.6535,0.6301,0.5832,0.5090,0.3605,0.1418",\ +"0.9035,0.8879,0.8566,0.8137,0.7316,0.5871,0.3684"); + } + + fall_constraint("SIG2SRAM_constraint_template") { + index_1("0.0080,0.0288,0.0616,0.1072,0.1920,0.3496,0.5952"); + index_2("0.0080,0.0288,0.0616,0.1072,0.1920,0.3496,0.5952"); + values ("0.3762,0.3566,0.3293,0.2863,0.2043,0.0676,-0.1434",\ +"0.3957,0.3762,0.3488,0.3059,0.2238,0.0871,-0.1199",\ +"0.4230,0.4035,0.3723,0.3332,0.2512,0.1184,-0.0965",\ +"0.4660,0.4465,0.4191,0.3762,0.2941,0.1613,-0.0496",\ +"0.5324,0.5168,0.4973,0.4543,0.3723,0.2316,0.0285",\ +"0.6809,0.6613,0.6340,0.5910,0.5129,0.3645,0.1652",\ +"0.9113,0.8918,0.8605,0.8176,0.7395,0.5988,0.3879"); + } + } + } +pin(A_REN) { + direction : input ; + capacitance : 0.00381144 ; + max_transition : "0.5952" ; + related_power_pin : VDD; + related_ground_pin : VSS; + internal_power() { + when : "A_MEN"; + rise_power("scalar"){ + values (0.0762); + } + fall_power("scalar"){ + values (0.0704); + } + } + internal_power() { + when : "!A_MEN"; + rise_power("scalar"){ + values (0.0057); + } + fall_power("scalar"){ + values (0.0018); + } + } + timing() { + timing_type : setup_rising; + related_pin : "A_CLK"; + when : "A_MEN" + sdf_cond : "A_MEN" + + rise_constraint("SIG2SRAM_constraint_template") { + index_1("0.0080,0.0288,0.0616,0.1072,0.1920,0.3496,0.5952"); + index_2("0.0080,0.0288,0.0616,0.1072,0.1920,0.3496,0.5952"); + values ("-0.0770,-0.0574,-0.0262,0.0168,0.0949,0.2355,0.4582",\ +"-0.0965,-0.0770,-0.0457,-0.0027,0.0754,0.2160,0.4387",\ +"-0.1199,-0.1004,-0.0730,-0.0262,0.0520,0.1887,0.4113",\ +"-0.1590,-0.1434,-0.1160,-0.0730,0.0051,0.1457,0.3645",\ +"-0.2449,-0.2254,-0.1941,-0.1473,-0.0770,0.0676,0.2863",\ +"-0.3816,-0.3699,-0.3387,-0.2801,-0.2215,-0.0770,0.1457",\ +"-0.6121,-0.5926,-0.5613,-0.5145,-0.4363,-0.2996,-0.0730"); + } + + fall_constraint("SIG2SRAM_constraint_template") { + index_1("0.0080,0.0288,0.0616,0.1072,0.1920,0.3496,0.5952"); + index_2("0.0080,0.0288,0.0616,0.1072,0.1920,0.3496,0.5952"); + values ("0.1262,0.1457,0.1691,0.2121,0.2824,0.4191,0.6457",\ +"0.1105,0.1262,0.1496,0.1887,0.2629,0.3996,0.6262",\ +"0.0793,0.0949,0.1223,0.1652,0.2395,0.3684,0.5949",\ +"0.0363,0.0559,0.0793,0.1223,0.2004,0.3410,0.5520",\ +"-0.0457,-0.0262,0.0012,0.0441,0.1301,0.2629,0.4738",\ +"-0.1902,-0.1746,-0.1434,-0.1043,-0.0184,0.1223,0.3332",\ +"-0.4129,-0.3934,-0.3660,-0.3230,-0.2449,-0.1043,0.1105"); + } + } + + + timing() { + timing_type : hold_rising; + related_pin : "A_CLK"; + when : "A_MEN" + sdf_cond : "A_MEN" + + rise_constraint("SIG2SRAM_constraint_template") { + index_1("0.0080,0.0288,0.0616,0.1072,0.1920,0.3496,0.5952"); + index_2("0.0080,0.0288,0.0616,0.1072,0.1920,0.3496,0.5952"); + values ("0.4113,0.3918,0.3645,0.3176,0.2395,0.0988,-0.1238",\ +"0.4309,0.4113,0.3840,0.3371,0.2590,0.1184,-0.1043",\ +"0.4582,0.4387,0.4113,0.3645,0.2824,0.1457,-0.0770",\ +"0.5051,0.4816,0.4543,0.4074,0.3293,0.1887,-0.0340",\ +"0.5715,0.5598,0.5324,0.4895,0.4035,0.2512,0.0441",\ +"0.7043,0.7004,0.6730,0.6262,0.5402,0.3957,0.1809",\ +"0.9387,0.9270,0.8957,0.8527,0.7746,0.6262,0.4074"); + } + + fall_constraint("SIG2SRAM_constraint_template") { + index_1("0.0080,0.0288,0.0616,0.1072,0.1920,0.3496,0.5952"); + index_2("0.0080,0.0288,0.0616,0.1072,0.1920,0.3496,0.5952"); + values ("0.4152,0.3918,0.3645,0.3215,0.2395,0.1027,-0.1082",\ +"0.4309,0.4113,0.3801,0.3410,0.2590,0.1223,-0.0926",\ +"0.4582,0.4387,0.4074,0.3684,0.2863,0.1496,-0.0613",\ +"0.5012,0.4816,0.4504,0.4074,0.3293,0.1887,-0.0145",\ +"0.5715,0.5559,0.5285,0.4816,0.3996,0.2512,0.0598",\ +"0.7160,0.7004,0.6691,0.6262,0.5520,0.4035,0.2004",\ +"0.9387,0.9191,0.8957,0.8488,0.7707,0.6262,0.4113"); + } + } + } +pin(A_MEN) { + direction : input ; + capacitance : 0.00300347 ; + max_transition : "0.5952" ; + related_power_pin : VDD; + related_ground_pin : VSS; + internal_power() { + rise_power("scalar"){ + values (0.1321); + } + fall_power("scalar"){ + values (0.0744); + } + } + timing() { + timing_type : setup_rising; + related_pin : "A_CLK"; + + rise_constraint("SIG2SRAM_constraint_template") { + index_1("0.0080,0.0288,0.0616,0.1072,0.1920,0.3496,0.5952"); + index_2("0.0080,0.0288,0.0616,0.1072,0.1920,0.3496,0.5952"); + values ("0.3215,0.3449,0.3684,0.4113,0.4895,0.6301,0.8527",\ +"0.3059,0.3254,0.3527,0.3957,0.4738,0.6145,0.8371",\ +"0.2746,0.2941,0.3215,0.3645,0.4426,0.5871,0.8059",\ +"0.2316,0.2512,0.2785,0.3215,0.3996,0.5402,0.7629",\ +"0.1496,0.1730,0.1965,0.2395,0.3215,0.4660,0.6848",\ +"0.0090,0.0285,0.0598,0.1027,0.1809,0.3176,0.5402",\ +"-0.2098,-0.1902,-0.1668,-0.1199,-0.0418,0.0988,0.3137"); + } + + fall_constraint("SIG2SRAM_constraint_template") { + index_1("0.0080,0.0288,0.0616,0.1072,0.1920,0.3496,0.5952"); + index_2("0.0080,0.0288,0.0616,0.1072,0.1920,0.3496,0.5952"); + values ("0.4582,0.4738,0.5012,0.5363,0.6145,0.7395,0.9738",\ +"0.4387,0.4543,0.4816,0.5207,0.5910,0.7199,0.9582",\ +"0.4035,0.4230,0.4504,0.4855,0.5637,0.6887,0.9230",\ +"0.3645,0.3840,0.4074,0.4465,0.5285,0.6496,0.8840",\ +"0.2824,0.3020,0.3254,0.3645,0.4465,0.5715,0.7980",\ +"0.1418,0.1613,0.1887,0.2238,0.3020,0.4309,0.6496",\ +"-0.0770,-0.0574,-0.0301,0.0090,0.0910,0.2238,0.4191"); + } + } + + + timing() { + timing_type : hold_rising; + related_pin : "A_CLK"; + + rise_constraint("SIG2SRAM_constraint_template") { + index_1("0.0080,0.0288,0.0616,0.1072,0.1920,0.3496,0.5952"); + index_2("0.0080,0.0288,0.0616,0.1072,0.1920,0.3496,0.5952"); + values ("0.3762,0.3605,0.3293,0.2863,0.2043,0.0637,-0.1629",\ +"0.3996,0.3801,0.3488,0.3020,0.2238,0.0832,-0.1395",\ +"0.4230,0.4074,0.3723,0.3293,0.2473,0.1105,-0.1121",\ +"0.4621,0.4465,0.4152,0.3762,0.2941,0.1535,-0.0691",\ +"0.5441,0.5285,0.4973,0.4465,0.3684,0.2316,0.0090",\ +"0.6848,0.6652,0.6301,0.5910,0.5129,0.3605,0.1496",\ +"0.9074,0.8918,0.8566,0.8215,0.7395,0.5910,0.3723"); + } + + fall_constraint("SIG2SRAM_constraint_template") { + index_1("0.0080,0.0288,0.0616,0.1072,0.1920,0.3496,0.5952"); + index_2("0.0080,0.0288,0.0616,0.1072,0.1920,0.3496,0.5952"); + values ("0.3762,0.3605,0.3332,0.2863,0.2043,0.0715,-0.1395",\ +"0.3996,0.3762,0.3488,0.3059,0.2238,0.0910,-0.1199",\ +"0.4270,0.4035,0.3762,0.3332,0.2512,0.1184,-0.0965",\ +"0.4699,0.4504,0.4191,0.3762,0.2941,0.1613,-0.0496",\ +"0.5441,0.5285,0.4973,0.4543,0.3762,0.2355,0.0324",\ +"0.6770,0.6613,0.6340,0.5949,0.5207,0.3762,0.1652",\ +"0.9074,0.8918,0.8605,0.8176,0.7395,0.6027,0.3918"); + } + } + } + pin(A_CLK) { + direction : input; + capacitance : 0.00378957; + max_transition : "0.5952"; + clock : "true" ; + pin_func_type : active_rising ; + + timing () { + timing_type : "min_pulse_width"; + related_pin : "A_CLK"; + rise_constraint("CLKTRAN_constraint_template") { + index_1("0.008,0.5952"); + values("0.4,0.4"); + } + } + + related_power_pin : VDD; + related_ground_pin : VSS; + + internal_power() { + when : "!A_MEN & !A_WEN & !A_REN"; + rise_power("scalar"){ + values (0); + } + fall_power("scalar"){ + values (0); + } + } + internal_power() { + when : "!A_MEN & A_WEN & !A_REN"; + rise_power("scalar"){ + values (4.3631); + } + fall_power("scalar"){ + values (0); + } + } + internal_power() { + when : "A_MEN & A_WEN & !A_REN"; + rise_power("scalar"){ + values (185.3380); + } + fall_power("scalar"){ + values (0); + } + } + internal_power() { + when : "A_MEN & A_WEN & A_REN"; + rise_power("scalar"){ + values (182.2010); + } + fall_power("scalar"){ + values (0); + } + } + internal_power() { + when : "A_MEN & !A_WEN & A_REN"; + rise_power("scalar"){ + values (154.2699); + } + fall_power("scalar"){ + values (0); + } + } + internal_power() { + when : "!A_MEN & !A_WEN & A_REN"; + rise_power("scalar"){ + values (1.4533); + } + fall_power("scalar"){ + values (0); + } + } + internal_power() { + when : "!A_MEN & A_WEN & A_REN"; + rise_power("scalar"){ + values (2.2272); + } + fall_power("scalar"){ + values (0); + } + } + internal_power() { + when : "A_MEN & !A_WEN & !A_REN"; + rise_power("scalar"){ + values (0); + } + fall_power("scalar"){ + values (0); + } + } + } + bus(A_DIN) { + bus_type : D_31_0; + direction : input ; + capacitance : 0.00433804 ; + memory_write() { + address : A_ADDR ; + clocked_on : A_CLK; + } + + max_transition : "0.5952" ; + pin(A_DIN[31:0]) { + related_power_pin : VDD; + related_ground_pin : VSS; + internal_power() { + when : "A_MEN"; + rise_power("scalar"){ + values (0.1881); + } + fall_power("scalar"){ + values (0.0370); + } + } + internal_power() { + when : "!A_MEN"; + rise_power("scalar"){ + values (0.1146); + } + fall_power("scalar"){ + values (0.0427); + } + } + } + timing() { + timing_type : setup_rising; + related_pin : "A_CLK"; + when : "(A_WEN & A_MEN)"; + sdf_cond : "A_W_ACCESS"; + + rise_constraint("SIG2SRAM_constraint_template") { + index_1("0.0080,0.0288,0.0616,0.1072,0.1920,0.3496,0.5952"); + index_2("0.0080,0.0288,0.0616,0.1072,0.1920,0.3496,0.5952"); + values ("-0.7934,-0.7738,-0.7475,-0.7055,-0.6244,-0.4789,-0.2572",\ +"-0.8014,-0.7819,-0.7555,-0.7135,-0.6324,-0.4869,-0.2653",\ +"-0.8115,-0.7919,-0.7656,-0.7236,-0.6425,-0.4970,-0.2753",\ +"-0.8254,-0.8059,-0.7795,-0.7375,-0.6565,-0.5110,-0.2893",\ +"-0.8488,-0.8293,-0.8029,-0.7610,-0.6799,-0.5344,-0.3127",\ +"-0.8920,-0.8725,-0.8461,-0.8041,-0.7231,-0.5776,-0.3559",\ +"-0.9602,-0.9407,-0.9143,-0.8723,-0.7913,-0.6458,-0.4241"); + } + + fall_constraint("SIG2SRAM_constraint_template") { + index_1("0.0080,0.0288,0.0616,0.1072,0.1920,0.3496,0.5952"); + index_2("0.0080,0.0288,0.0616,0.1072,0.1920,0.3496,0.5952"); + values ("-0.7065,-0.6879,-0.6606,-0.6205,-0.5385,-0.4018,-0.1918",\ +"-0.7145,-0.6959,-0.6686,-0.6285,-0.5465,-0.4098,-0.1998",\ +"-0.7245,-0.7060,-0.6786,-0.6386,-0.5566,-0.4199,-0.2099",\ +"-0.7385,-0.7199,-0.6926,-0.6526,-0.5705,-0.4338,-0.2238",\ +"-0.7619,-0.7434,-0.7160,-0.6760,-0.5940,-0.4572,-0.2473",\ +"-0.8051,-0.7865,-0.7592,-0.7192,-0.6371,-0.5004,-0.2905",\ +"-0.8733,-0.8548,-0.8274,-0.7874,-0.7054,-0.5686,-0.3587"); + } + } + + timing() { + timing_type : hold_rising; + related_pin : "A_CLK"; + when : "(A_WEN & A_MEN)"; + sdf_cond : "A_W_ACCESS"; + + rise_constraint("SIG2SRAM_constraint_template") { + index_1("0.0080,0.0288,0.0616,0.1072,0.1920,0.3496,0.5952"); + index_2("0.0080,0.0288,0.0616,0.1072,0.1920,0.3496,0.5952"); + values ("0.9129,0.8934,0.8670,0.8250,0.7440,0.6043,0.3768",\ +"0.9209,0.9014,0.8750,0.8331,0.7520,0.6123,0.3848",\ +"0.9310,0.9115,0.8851,0.8431,0.7621,0.6224,0.3949",\ +"0.9450,0.9254,0.8991,0.8571,0.7760,0.6364,0.4088",\ +"0.9684,0.9489,0.9225,0.8805,0.7995,0.6598,0.4323",\ +"1.0116,0.9920,0.9657,0.9237,0.8426,0.7030,0.4754",\ +"1.0798,1.0603,1.0339,0.9919,0.9108,0.7712,0.5437"); + } + + fall_constraint("SIG2SRAM_constraint_template") { + index_1("0.0080,0.0288,0.0616,0.1072,0.1920,0.3496,0.5952"); + index_2("0.0080,0.0288,0.0616,0.1072,0.1920,0.3496,0.5952"); + values ("0.8172,0.7996,0.7713,0.7323,0.6502,0.5125,0.3036",\ +"0.8252,0.8077,0.7793,0.7403,0.6582,0.5206,0.3116",\ +"0.8353,0.8177,0.7894,0.7504,0.6683,0.5306,0.3216",\ +"0.8493,0.8317,0.8034,0.7643,0.6823,0.5446,0.3356",\ +"0.8727,0.8551,0.8268,0.7877,0.7057,0.5680,0.3590",\ +"0.9159,0.8983,0.8700,0.8309,0.7489,0.6112,0.4022",\ +"0.9841,0.9665,0.9382,0.8991,0.8171,0.6794,0.4704"); + } + } + } + +bus(A_DOUT) { + + bus_type : D_31_0; + direction : output ; + capacitance : 0 ; + max_capacitance : 0.064 ; + memory_read() { + address : A_ADDR ; + } + pin(A_DOUT[31:0]) { + related_power_pin : VDD; + related_ground_pin : VSS; + internal_power() { + rise_power("scalar") { + values (0); + } + fall_power("scalar") { + values (0); + } + } + } + timing() { + related_pin : "A_CLK"; + timing_type : rising_edge ; + timing_sense : non_unate ; + + cell_rise(SIG2SRAM_delay_template) { + index_1("0.0080,0.0288,0.0616,0.1072,0.1920,0.3496,0.5952"); + index_2("0.0008,0.0014,0.0051,0.0100,0.0339,0.0640"); + values ("9.3689,9.3716,9.3838,9.3980,9.4506,9.5056",\ +"9.3755,9.3782,9.3904,9.4046,9.4572,9.5122",\ +"9.3875,9.3902,9.4024,9.4166,9.4692,9.5241",\ +"9.4029,9.4056,9.4178,9.4320,9.4846,9.5395",\ +"9.4180,9.4207,9.4329,9.4471,9.4997,9.5546",\ +"9.4670,9.4697,9.4819,9.4961,9.5487,9.6036",\ +"9.5245,9.5272,9.5393,9.5535,9.6061,9.6611"); + } + cell_fall(SIG2SRAM_delay_template) { + index_1("0.0080,0.0288,0.0616,0.1072,0.1920,0.3496,0.5952"); + index_2("0.0008,0.0014,0.0051,0.0100,0.0339,0.0640"); + values ("9.2587,9.2609,9.2707,9.2825,9.3261,9.3698",\ +"9.2653,9.2675,9.2773,9.2891,9.3327,9.3764",\ +"9.2773,9.2795,9.2892,9.3011,9.3446,9.3884",\ +"9.2927,9.2949,9.3047,9.3165,9.3600,9.4038",\ +"9.3078,9.3100,9.3198,9.3316,9.3751,9.4189",\ +"9.3568,9.3590,9.3688,9.3806,9.4241,9.4679",\ +"9.4143,9.4164,9.4262,9.4380,9.4816,9.5253"); + } + + rise_transition(SRAM_load_template) { + index_1("0.0008,0.0014,0.0051,0.0100,0.0339,0.0640"); + values ("0.0560,0.0583,0.0696,0.0816,0.1519,0.2335"); + } + fall_transition(SRAM_load_template) { + index_1("0.0008,0.0014,0.0051,0.0100,0.0339,0.0640"); + values ("0.0428,0.0445,0.0538,0.0658,0.1181,0.1751"); + } + } +} +cell_leakage_power : 20905.4106; +} +} diff --git a/flow/platforms/ihp-sg13g2/lib/RM_IHPSG13_1P_8192x32_c4_typ_1p20V_25C.lib b/flow/platforms/ihp-sg13g2/lib/RM_IHPSG13_1P_8192x32_c4_typ_1p20V_25C.lib new file mode 100644 index 0000000000..dd68126139 --- /dev/null +++ b/flow/platforms/ihp-sg13g2/lib/RM_IHPSG13_1P_8192x32_c4_typ_1p20V_25C.lib @@ -0,0 +1,787 @@ +/* ------------------------------------------------------*/ +/**/ +/* Copyright 2023 IHP PDK Authors*/ +/**/ +/* Licensed under the Apache License, Version 2.0 (the "License");*/ +/* you may not use this file except in compliance with the License.*/ +/* You may obtain a copy of the License at*/ +/* */ +/* https://www.apache.org/licenses/LICENSE-2.0*/ +/* */ +/* Unless required by applicable law or agreed to in writing, software*/ +/* distributed under the License is distributed on an "AS IS" BASIS,*/ +/* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.*/ +/* See the License for the specific language governing permissions and*/ +/* limitations under the License.*/ +/* */ +/* Generated on Mon Apr 7 14:15:44 2025 */ +/* */ +/* ------------------------------------------------------ */ +library(RM_IHPSG13_1P_8192x32_c4_typ_1p20V_25C) { + technology (cmos) ; + delay_model : table_lookup ; + define ("add_pg_pin_to_lib", "library", "boolean"); + add_pg_pin_to_lib : true; + voltage_map ( VDD, 1.20); + voltage_map ( VDDARRAY, 1.20); + voltage_map ( VSS, 0.000000 ); + + date : "Mon Apr 7 14:15:42 2025" ; + comment : "IHP Microelectronics GmbH, 2023" ; + revision : 1.0.0 ; + simulation : true ; + nom_process : 1 ; + nom_temperature : 25 ; + nom_voltage : 1.20 ; + + operating_conditions("typ_1p20V_25C"){ + process : 1 ; + temperature : 25 ; + voltage : 1.20 ; + tree_type : "balanced_tree" ; + } + + default_operating_conditions : typ_1p20V_25C ; + default_max_transition : 1.0 ; + default_fanout_load : 1.0 ; + default_inout_pin_cap : 0.0 ; + default_input_pin_cap : 0.0 ; + default_output_pin_cap : 0.0 ; + default_cell_leakage_power : 0.0 ; + default_leakage_power_density : 0.0 ; + + slew_lower_threshold_pct_rise : 30 ; + slew_upper_threshold_pct_rise : 70 ; + input_threshold_pct_fall : 50 ; + output_threshold_pct_fall : 50 ; + input_threshold_pct_rise : 50 ; + output_threshold_pct_rise : 50 ; + slew_lower_threshold_pct_fall : 30 ; + slew_upper_threshold_pct_fall : 70 ; + slew_derate_from_library : 0.5; + k_volt_cell_leakage_power : 0.0 ; + k_temp_cell_leakage_power : 0.0 ; + k_process_cell_leakage_power : 0.0 ; + k_volt_internal_power : 0.0 ; + k_temp_internal_power : 0.0 ; + k_process_internal_power : 0.0 ; + + capacitive_load_unit (1,pf) ; + voltage_unit : "1V" ; + current_unit : "1uA" ; + time_unit : "1ns" ; + leakage_power_unit : "1nW" ; + pulling_resistance_unit : "1kohm"; + /* + ------------------------------------------------------------------------------------------ + implicit units overview: + cell_area unit : "um" + internal_power unit : "1e-12 * J/toggle = 1 * uW/MHz" + (capacitive_load_unit * voltage_unit^2) per toggle event + ------------------------------------------------------------------------------------------ + */ + library_features(report_delay_calculation); + define_cell_area (pad_drivers,pad_driver_sites) ; + + lu_table_template(CLKTRAN_constraint_template) { + variable_1 : constrained_pin_transition; + index_1 ( "0.010, 0.050, 0.200, 0.400, 1.000" ); + } + lu_table_template(SRAM_load_template) { + variable_1 : total_output_net_capacitance; + index_1 ( "0.0008,0.0014,0.0051,0.0100,0.0339,0.0640" ); + } + lu_table_template(SIG2SRAM_constraint_template) { + variable_1 : related_pin_transition; + variable_2 : constrained_pin_transition; + index_1 ( "0.0056,0.0232,0.0400,0.0728,0.1280,0.2440,0.4760" ); + index_2 ( "0.0056,0.0232,0.0400,0.0728,0.1280,0.2440,0.4760" ); + } + + lu_table_template(SIG2SRAM_delay_template) { + variable_1 : input_net_transition; + variable_2 : total_output_net_capacitance; + index_1 ( "0.0056,0.0232,0.0400,0.0728,0.1280,0.2440,0.4760" ); + index_2 ( "0.0008,0.0014,0.0051,0.0100,0.0339,0.0640" ); + } + + type (D_31_0) { + base_type : array; + data_type : bit; + bit_width : 32; + bit_from : 31; + bit_to : 0; + downto : true; + } + + type (A_12_0) { + base_type : array; + data_type : bit; + bit_width : 13; + bit_from : 12; + bit_to : 0; + downto : true; + } + +cell(RM_IHPSG13_1P_8192x32_c4) { +pg_pin (VDD) { + pg_type : primary_power; + voltage_name : VDD; +} +pg_pin (VDDARRAY) { + pg_type : primary_power; + voltage_name : VDDARRAY; +} +pg_pin (VSS) { + pg_type : primary_ground; + voltage_name : VSS; +} + +memory() { + type : ram; + address_width : 13; + word_width : 32; +} + +interface_timing : false; +bus_naming_style : "%s[%d]" ; +area : 939914.928 ; + + pin(A_DLY) { + direction : input ; + capacitance : 0.00401111 ; + max_transition : "1" ; + related_power_pin : VDD; + related_ground_pin : VSS; + internal_power() { + rise_power("scalar") { + values (0); + } + fall_power("scalar") { + values (0); + } + } + } + +bus(A_ADDR) { + bus_type : A_12_0; + direction : input ; + capacitance : 0.00721489 ; + pin(A_ADDR[0]) { + capacitance : 0.00593979 ; + } + pin(A_ADDR[1]) { + capacitance : 0.00483009 ; + } + pin(A_ADDR[2]) { + capacitance : 0.006215 ; + } + pin(A_ADDR[3]) { + capacitance : 0.00766726 ; + } + pin(A_ADDR[4]) { + capacitance : 0.00488951 ; + } + pin(A_ADDR[5]) { + capacitance : 0.0091523 ; + } + pin(A_ADDR[6]) { + capacitance : 0.0109212 ; + } + pin(A_ADDR[7]) { + capacitance : 0.00774122 ; + } + pin(A_ADDR[8]) { + capacitance : 0.0101403 ; + } + pin(A_ADDR[9]) { + capacitance : 0.00771605 ; + } + pin(A_ADDR[10]) { + capacitance : 0.00860549 ; + } + pin(A_ADDR[11]) { + capacitance : 0.00948967 ; + } + max_transition : "0.476" ; + pin(A_ADDR[12:0]) { + related_power_pin : VDD; + related_ground_pin : VSS; + internal_power() { + when : "A_MEN"; + rise_power("scalar"){ + values (0.0075); + } + fall_power("scalar"){ + values (0.0016); + } + } + internal_power() { + when : "!A_MEN"; + rise_power("scalar"){ + values (0.0157); + } + fall_power("scalar"){ + values (0.0046); + } + } + } + timing() { + timing_type : setup_rising; + related_pin : "A_CLK"; + when : "((A_WEN | A_REN)& A_MEN)" + sdf_cond : "A_RW_ACCESS" + + rise_constraint("SIG2SRAM_constraint_template") { + index_1("0.0056,0.0232,0.0400,0.0728,0.1280,0.2440,0.4760"); + index_2("0.0056,0.0232,0.0400,0.0728,0.1280,0.2440,0.4760"); + values ("-0.4168,-0.3973,-0.3855,-0.3543,-0.3074,-0.2020,-0.0027",\ +"-0.4324,-0.4129,-0.4012,-0.3699,-0.3191,-0.2176,-0.0184",\ +"-0.4441,-0.4285,-0.4129,-0.3816,-0.3309,-0.2293,-0.0301",\ +"-0.4793,-0.4598,-0.4441,-0.4129,-0.3660,-0.2645,-0.0652",\ +"-0.5223,-0.5066,-0.4910,-0.4598,-0.4129,-0.3074,-0.1121",\ +"-0.6199,-0.6082,-0.5926,-0.5613,-0.5145,-0.4129,-0.2137",\ +"-0.8191,-0.8074,-0.7840,-0.7566,-0.7098,-0.6082,-0.4051"); + } + + fall_constraint("SIG2SRAM_constraint_template") { + index_1("0.0056,0.0232,0.0400,0.0728,0.1280,0.2440,0.4760"); + index_2("0.0056,0.0232,0.0400,0.0728,0.1280,0.2440,0.4760"); + values ("-0.3309,-0.3113,-0.2996,-0.2684,-0.2176,-0.1238,0.0637",\ +"-0.3465,-0.3309,-0.3152,-0.2840,-0.2332,-0.1395,0.0480",\ +"-0.3582,-0.3426,-0.3270,-0.2996,-0.2488,-0.1512,0.0324",\ +"-0.3895,-0.3738,-0.3582,-0.3309,-0.2801,-0.1863,0.0051",\ +"-0.4363,-0.4207,-0.4051,-0.3777,-0.3230,-0.2293,-0.0379",\ +"-0.5379,-0.5223,-0.5066,-0.4793,-0.4285,-0.3309,-0.1434",\ +"-0.7332,-0.7176,-0.7020,-0.6746,-0.6238,-0.5262,-0.3387"); + } + } + + + timing() { + timing_type : hold_rising; + related_pin : "A_CLK"; + when : "((A_WEN | A_REN)& A_MEN)" + sdf_cond : "A_RW_ACCESS" + + rise_constraint("SIG2SRAM_constraint_template") { + index_1("0.0056,0.0232,0.0400,0.0728,0.1280,0.2440,0.4760"); + index_2("0.0056,0.0232,0.0400,0.0728,0.1280,0.2440,0.4760"); + values ("0.5246,0.5051,0.4895,0.4582,0.4113,0.3059,0.1066",\ +"0.5402,0.5207,0.5051,0.4777,0.4270,0.3215,0.1223",\ +"0.5520,0.5324,0.5168,0.4895,0.4387,0.3371,0.1340",\ +"0.5832,0.5676,0.5520,0.5207,0.4738,0.3684,0.1691",\ +"0.6301,0.6105,0.5949,0.5676,0.5168,0.4113,0.2160",\ +"0.7316,0.7121,0.7004,0.6691,0.6223,0.5168,0.3176",\ +"0.9270,0.9230,0.8957,0.8645,0.8137,0.7121,0.5168"); + } + + fall_constraint("SIG2SRAM_constraint_template") { + index_1("0.0056,0.0232,0.0400,0.0728,0.1280,0.2440,0.4760"); + index_2("0.0056,0.0232,0.0400,0.0728,0.1280,0.2440,0.4760"); + values ("0.4309,0.4152,0.4035,0.3684,0.3215,0.2277,0.0363",\ +"0.4465,0.4309,0.4152,0.3879,0.3371,0.2395,0.0559",\ +"0.4582,0.4426,0.4309,0.3996,0.3488,0.2551,0.0715",\ +"0.4934,0.4777,0.4621,0.4348,0.3840,0.2863,0.0988",\ +"0.5363,0.5207,0.5051,0.4777,0.4270,0.3332,0.1418",\ +"0.6379,0.6262,0.6105,0.5793,0.5324,0.4348,0.2434",\ +"0.8332,0.8215,0.8059,0.7707,0.7238,0.6301,0.4387"); + } + } +} +pin(A_WEN) { + direction : input ; + capacitance : 0.00324098 ; + max_transition : "0.476" ; + related_power_pin : VDD; + related_ground_pin : VSS; + internal_power() { + when : "A_MEN"; + rise_power("scalar"){ + values (0.0039); + } + fall_power("scalar"){ + values (0.0054); + } + } + internal_power() { + when : "!A_MEN"; + rise_power("scalar"){ + values (0.0039); + } + fall_power("scalar"){ + values (0.0055); + } + } + timing() { + timing_type : setup_rising; + related_pin : "A_CLK"; + when : "A_MEN" + sdf_cond : "A_MEN" + + rise_constraint("SIG2SRAM_constraint_template") { + index_1("0.0056,0.0232,0.0400,0.0728,0.1280,0.2440,0.4760"); + index_2("0.0056,0.0232,0.0400,0.0728,0.1280,0.2440,0.4760"); + values ("0.2043,0.2199,0.2316,0.2629,0.3059,0.4113,0.6066",\ +"0.1887,0.2043,0.2160,0.2473,0.2941,0.3957,0.5949",\ +"0.1691,0.1848,0.2004,0.2316,0.2785,0.3801,0.5754",\ +"0.1379,0.1574,0.1691,0.2004,0.2473,0.3527,0.5480",\ +"0.0910,0.1066,0.1223,0.1535,0.2004,0.2980,0.4973",\ +"-0.0105,0.0051,0.0207,0.0520,0.0949,0.2004,0.3957",\ +"-0.2059,-0.1902,-0.1746,-0.1473,-0.1004,0.0051,0.2004"); + } + + fall_constraint("SIG2SRAM_constraint_template") { + index_1("0.0056,0.0232,0.0400,0.0728,0.1280,0.2440,0.4760"); + index_2("0.0056,0.0232,0.0400,0.0728,0.1280,0.2440,0.4760"); + values ("0.2941,0.3098,0.3215,0.3488,0.4035,0.4973,0.6887",\ +"0.2785,0.2941,0.3059,0.3332,0.3840,0.4816,0.6691",\ +"0.2629,0.2785,0.2902,0.3176,0.3684,0.4660,0.6535",\ +"0.2316,0.2473,0.2590,0.2863,0.3410,0.4348,0.6262",\ +"0.1848,0.2004,0.2121,0.2395,0.2902,0.3879,0.5754",\ +"0.0832,0.0988,0.1105,0.1379,0.1809,0.2746,0.4699",\ +"-0.1121,-0.0965,-0.0848,-0.0535,-0.0066,0.0910,0.2824"); + } + } + + + timing() { + timing_type : hold_rising; + related_pin : "A_CLK"; + when : "A_MEN" + sdf_cond : "A_MEN" + + rise_constraint("SIG2SRAM_constraint_template") { + index_1("0.0056,0.0232,0.0400,0.0728,0.1280,0.2440,0.4760"); + index_2("0.0056,0.0232,0.0400,0.0728,0.1280,0.2440,0.4760"); + values ("0.2473,0.2316,0.2160,0.1887,0.1379,0.0363,-0.1629",\ +"0.2629,0.2473,0.2316,0.2043,0.1535,0.0520,-0.1473",\ +"0.2785,0.2590,0.2434,0.2160,0.1652,0.0676,-0.1355",\ +"0.3098,0.2941,0.2785,0.2473,0.1965,0.0910,-0.1043",\ +"0.3527,0.3371,0.3215,0.2941,0.2434,0.1418,-0.0574",\ +"0.4582,0.4426,0.4270,0.3957,0.3488,0.2434,0.0480",\ +"0.6535,0.6379,0.6184,0.5910,0.5402,0.4426,0.2434"); + } + + fall_constraint("SIG2SRAM_constraint_template") { + index_1("0.0056,0.0232,0.0400,0.0728,0.1280,0.2440,0.4760"); + index_2("0.0056,0.0232,0.0400,0.0728,0.1280,0.2440,0.4760"); + values ("0.2395,0.2238,0.2121,0.1809,0.1301,0.0324,-0.1551",\ +"0.2551,0.2395,0.2277,0.1965,0.1457,0.0480,-0.1395",\ +"0.2668,0.2551,0.2395,0.2082,0.1574,0.0637,-0.1277",\ +"0.3020,0.2863,0.2707,0.2395,0.1887,0.0910,-0.0965",\ +"0.3449,0.3293,0.3176,0.2863,0.2355,0.1379,-0.0496",\ +"0.4504,0.4348,0.4191,0.3879,0.3371,0.2395,0.0559",\ +"0.6457,0.6301,0.6145,0.5871,0.5324,0.4309,0.2512"); + } + } + } +pin(A_REN) { + direction : input ; + capacitance : 0.00381634 ; + max_transition : "0.476" ; + related_power_pin : VDD; + related_ground_pin : VSS; + internal_power() { + when : "A_MEN"; + rise_power("scalar"){ + values (0.0053); + } + fall_power("scalar"){ + values (0.0045); + } + } + internal_power() { + when : "!A_MEN"; + rise_power("scalar"){ + values (0.0057); + } + fall_power("scalar"){ + values (0.0040); + } + } + timing() { + timing_type : setup_rising; + related_pin : "A_CLK"; + when : "A_MEN" + sdf_cond : "A_MEN" + + rise_constraint("SIG2SRAM_constraint_template") { + index_1("0.0056,0.0232,0.0400,0.0728,0.1280,0.2440,0.4760"); + index_2("0.0056,0.0232,0.0400,0.0728,0.1280,0.2440,0.4760"); + values ("-0.0301,-0.0145,0.0012,0.0324,0.0793,0.1809,0.3762",\ +"-0.0457,-0.0301,-0.0145,0.0168,0.0637,0.1613,0.3605",\ +"-0.0574,-0.0418,-0.0262,0.0051,0.0520,0.1496,0.3449",\ +"-0.0926,-0.0730,-0.0574,-0.0262,0.0207,0.1184,0.3137",\ +"-0.1395,-0.1238,-0.1082,-0.0770,-0.0301,0.0715,0.2707",\ +"-0.2410,-0.2254,-0.2098,-0.1746,-0.1355,-0.0340,0.1652",\ +"-0.4402,-0.4207,-0.4051,-0.3738,-0.3270,-0.2293,-0.0340"); + } + + fall_constraint("SIG2SRAM_constraint_template") { + index_1("0.0056,0.0232,0.0400,0.0728,0.1280,0.2440,0.4760"); + index_2("0.0056,0.0232,0.0400,0.0728,0.1280,0.2440,0.4760"); + values ("0.0988,0.1145,0.1262,0.1535,0.2043,0.3020,0.4855",\ +"0.0832,0.0988,0.1105,0.1418,0.1848,0.2824,0.4738",\ +"0.0676,0.0832,0.0949,0.1262,0.1730,0.2668,0.4621",\ +"0.0402,0.0559,0.0676,0.0988,0.1457,0.2434,0.4191",\ +"-0.0105,0.0012,0.0168,0.0480,0.0988,0.1965,0.3840",\ +"-0.1160,-0.0965,-0.0848,-0.0535,-0.0066,0.0988,0.2824",\ +"-0.3113,-0.2957,-0.2801,-0.2527,-0.2059,-0.1043,0.0832"); + } + } + + + timing() { + timing_type : hold_rising; + related_pin : "A_CLK"; + when : "A_MEN" + sdf_cond : "A_MEN" + + rise_constraint("SIG2SRAM_constraint_template") { + index_1("0.0056,0.0232,0.0400,0.0728,0.1280,0.2440,0.4760"); + index_2("0.0056,0.0232,0.0400,0.0728,0.1280,0.2440,0.4760"); + values ("0.2707,0.2551,0.2395,0.2121,0.1613,0.0598,-0.1395",\ +"0.2863,0.2707,0.2551,0.2238,0.1730,0.0715,-0.1238",\ +"0.2980,0.2824,0.2668,0.2395,0.1887,0.0871,-0.1121",\ +"0.3332,0.3176,0.3020,0.2707,0.2199,0.1184,-0.0809",\ +"0.3762,0.3605,0.3449,0.3176,0.2668,0.1613,-0.0340",\ +"0.4816,0.4621,0.4504,0.4191,0.3723,0.2629,0.0715",\ +"0.6770,0.6613,0.6418,0.6184,0.5637,0.4699,0.2629"); + } + + fall_constraint("SIG2SRAM_constraint_template") { + index_1("0.0056,0.0232,0.0400,0.0728,0.1280,0.2440,0.4760"); + index_2("0.0056,0.0232,0.0400,0.0728,0.1280,0.2440,0.4760"); + values ("0.2590,0.2434,0.2316,0.2004,0.1457,0.0520,-0.1355",\ +"0.2746,0.2590,0.2434,0.2160,0.1613,0.0676,-0.1199",\ +"0.2863,0.2707,0.2590,0.2277,0.1730,0.0832,-0.1082",\ +"0.3215,0.3059,0.2902,0.2590,0.2082,0.1105,-0.0770",\ +"0.3645,0.3488,0.3332,0.3059,0.2551,0.1535,-0.0340",\ +"0.4699,0.4543,0.4387,0.4074,0.3605,0.2551,0.0715",\ +"0.6652,0.6496,0.6340,0.6027,0.5520,0.4621,0.2707"); + } + } + } +pin(A_MEN) { + direction : input ; + capacitance : 0.00309605 ; + max_transition : "0.476" ; + related_power_pin : VDD; + related_ground_pin : VSS; + internal_power() { + rise_power("scalar"){ + values (0.0874); + } + fall_power("scalar"){ + values (0.0062); + } + } + timing() { + timing_type : setup_rising; + related_pin : "A_CLK"; + + rise_constraint("SIG2SRAM_constraint_template") { + index_1("0.0056,0.0232,0.0400,0.0728,0.1280,0.2440,0.4760"); + index_2("0.0056,0.0232,0.0400,0.0728,0.1280,0.2440,0.4760"); + values ("0.2043,0.2199,0.2316,0.2668,0.3098,0.4152,0.6066",\ +"0.1887,0.2043,0.2199,0.2512,0.2941,0.3996,0.5949",\ +"0.1730,0.1887,0.2043,0.2355,0.2824,0.3840,0.5793",\ +"0.1418,0.1574,0.1730,0.2043,0.2512,0.3566,0.5480",\ +"0.0949,0.1105,0.1262,0.1574,0.2043,0.3020,0.5051",\ +"-0.0066,0.0090,0.0246,0.0520,0.0988,0.2043,0.3996",\ +"-0.2020,-0.1863,-0.1746,-0.1434,-0.0965,0.0090,0.2082"); + } + + fall_constraint("SIG2SRAM_constraint_template") { + index_1("0.0056,0.0232,0.0400,0.0728,0.1280,0.2440,0.4760"); + index_2("0.0056,0.0232,0.0400,0.0728,0.1280,0.2440,0.4760"); + values ("0.2980,0.3137,0.3254,0.3527,0.4035,0.5012,0.6887",\ +"0.2824,0.2980,0.3098,0.3371,0.3879,0.4855,0.6730",\ +"0.2668,0.2824,0.2941,0.3215,0.3723,0.4699,0.6574",\ +"0.2355,0.2473,0.2629,0.2902,0.3410,0.4387,0.6262",\ +"0.1887,0.2004,0.2160,0.2395,0.2941,0.3918,0.5793",\ +"0.0871,0.1027,0.1145,0.1418,0.1848,0.2746,0.4816",\ +"-0.1082,-0.0965,-0.0809,-0.0496,-0.0027,0.0949,0.2863"); + } + } + + + timing() { + timing_type : hold_rising; + related_pin : "A_CLK"; + + rise_constraint("SIG2SRAM_constraint_template") { + index_1("0.0056,0.0232,0.0400,0.0728,0.1280,0.2440,0.4760"); + index_2("0.0056,0.0232,0.0400,0.0728,0.1280,0.2440,0.4760"); + values ("0.2512,0.2355,0.2199,0.1926,0.1418,0.0402,-0.1590",\ +"0.2668,0.2512,0.2355,0.2082,0.1574,0.0559,-0.1434",\ +"0.2824,0.2629,0.2512,0.2199,0.1691,0.0715,-0.1316",\ +"0.3137,0.2980,0.2824,0.2512,0.2004,0.0988,-0.0965",\ +"0.3566,0.3410,0.3254,0.2980,0.2473,0.1418,-0.0535",\ +"0.4621,0.4426,0.4309,0.3996,0.3527,0.2473,0.0520",\ +"0.6574,0.6418,0.6262,0.5949,0.5441,0.4465,0.2473"); + } + + fall_constraint("SIG2SRAM_constraint_template") { + index_1("0.0056,0.0232,0.0400,0.0728,0.1280,0.2440,0.4760"); + index_2("0.0056,0.0232,0.0400,0.0728,0.1280,0.2440,0.4760"); + values ("0.2395,0.2238,0.2121,0.1809,0.1301,0.0324,-0.1551",\ +"0.2551,0.2434,0.2277,0.1965,0.1457,0.0480,-0.1395",\ +"0.2707,0.2551,0.2395,0.2082,0.1574,0.0637,-0.1277",\ +"0.3020,0.2863,0.2707,0.2434,0.1926,0.0910,-0.0965",\ +"0.3449,0.3332,0.3176,0.2863,0.2355,0.1379,-0.0496",\ +"0.4504,0.4348,0.4230,0.3918,0.3410,0.2434,0.0559",\ +"0.6457,0.6301,0.6145,0.5910,0.5324,0.4387,0.2512"); + } + } + } + pin(A_CLK) { + direction : input; + capacitance : 0.00380014; + max_transition : "0.476"; + clock : "true" ; + pin_func_type : active_rising ; + + timing () { + timing_type : "min_pulse_width"; + related_pin : "A_CLK"; + rise_constraint("CLKTRAN_constraint_template") { + index_1("0.0056,0.476"); + values("0.21,0.21"); + } + } + + related_power_pin : VDD; + related_ground_pin : VSS; + + internal_power() { + when : "!A_MEN & !A_WEN & !A_REN"; + rise_power("scalar"){ + values (0); + } + fall_power("scalar"){ + values (0); + } + } + internal_power() { + when : "!A_MEN & A_WEN & !A_REN"; + rise_power("scalar"){ + values (4.5782); + } + fall_power("scalar"){ + values (0); + } + } + internal_power() { + when : "A_MEN & A_WEN & !A_REN"; + rise_power("scalar"){ + values (239.3104); + } + fall_power("scalar"){ + values (0); + } + } + internal_power() { + when : "A_MEN & A_WEN & A_REN"; + rise_power("scalar"){ + values (235.5004); + } + fall_power("scalar"){ + values (0); + } + } + internal_power() { + when : "A_MEN & !A_WEN & A_REN"; + rise_power("scalar"){ + values (230.3533); + } + fall_power("scalar"){ + values (0); + } + } + internal_power() { + when : "!A_MEN & !A_WEN & A_REN"; + rise_power("scalar"){ + values (0.4883); + } + fall_power("scalar"){ + values (0); + } + } + internal_power() { + when : "!A_MEN & A_WEN & A_REN"; + rise_power("scalar"){ + values (1.4210); + } + fall_power("scalar"){ + values (0); + } + } + internal_power() { + when : "A_MEN & !A_WEN & !A_REN"; + rise_power("scalar"){ + values (0); + } + fall_power("scalar"){ + values (0); + } + } + } + bus(A_DIN) { + bus_type : D_31_0; + direction : input ; + capacitance : 0.00435226 ; + memory_write() { + address : A_ADDR ; + clocked_on : A_CLK; + } + + max_transition : "0.476" ; + pin(A_DIN[31:0]) { + related_power_pin : VDD; + related_ground_pin : VSS; + internal_power() { + when : "A_MEN"; + rise_power("scalar"){ + values (0.1353); + } + fall_power("scalar"){ + values (0.0310); + } + } + internal_power() { + when : "!A_MEN"; + rise_power("scalar"){ + values (0.1380); + } + fall_power("scalar"){ + values (0.0300); + } + } + } + timing() { + timing_type : setup_rising; + related_pin : "A_CLK"; + when : "(A_WEN & A_MEN)"; + sdf_cond : "A_W_ACCESS"; + + rise_constraint("SIG2SRAM_constraint_template") { + index_1("0.0056,0.0232,0.0400,0.0728,0.1280,0.2440,0.4760"); + index_2("0.0056,0.0232,0.0400,0.0728,0.1280,0.2440,0.4760"); + values ("-0.4395,-0.4239,-0.4112,-0.3790,-0.3311,-0.2315,-0.0323",\ +"-0.4445,-0.4289,-0.4162,-0.3840,-0.3361,-0.2365,-0.0373",\ +"-0.4496,-0.4340,-0.4213,-0.3891,-0.3412,-0.2416,-0.0424",\ +"-0.4585,-0.4429,-0.4302,-0.3980,-0.3501,-0.2505,-0.0513",\ +"-0.4654,-0.4497,-0.4370,-0.4048,-0.3570,-0.2573,-0.0581",\ +"-0.4963,-0.4807,-0.4680,-0.4357,-0.3879,-0.2883,-0.0891",\ +"-0.5522,-0.5365,-0.5238,-0.4916,-0.4438,-0.3442,-0.1449"); + } + + fall_constraint("SIG2SRAM_constraint_template") { + index_1("0.0056,0.0232,0.0400,0.0728,0.1280,0.2440,0.4760"); + index_2("0.0056,0.0232,0.0400,0.0728,0.1280,0.2440,0.4760"); + values ("-0.3877,-0.3731,-0.3594,-0.3311,-0.2803,-0.1807,-0.0059",\ +"-0.3928,-0.3781,-0.3645,-0.3361,-0.2854,-0.1857,-0.0109",\ +"-0.3979,-0.3832,-0.3695,-0.3412,-0.2904,-0.1908,-0.0160",\ +"-0.4068,-0.3921,-0.3784,-0.3501,-0.2993,-0.1997,-0.0249",\ +"-0.4136,-0.3990,-0.3853,-0.3570,-0.3062,-0.2066,-0.0318",\ +"-0.4445,-0.4299,-0.4162,-0.3879,-0.3371,-0.2375,-0.0627",\ +"-0.5004,-0.4858,-0.4721,-0.4438,-0.3930,-0.2934,-0.1186"); + } + } + + timing() { + timing_type : hold_rising; + related_pin : "A_CLK"; + when : "(A_WEN & A_MEN)"; + sdf_cond : "A_W_ACCESS"; + + rise_constraint("SIG2SRAM_constraint_template") { + index_1("0.0056,0.0232,0.0400,0.0728,0.1280,0.2440,0.4760"); + index_2("0.0056,0.0232,0.0400,0.0728,0.1280,0.2440,0.4760"); + values ("0.5486,0.5329,0.5202,0.4880,0.4411,0.3396,0.1443",\ +"0.5536,0.5380,0.5253,0.4930,0.4462,0.3446,0.1493",\ +"0.5587,0.5430,0.5303,0.4981,0.4512,0.3497,0.1544",\ +"0.5676,0.5519,0.5393,0.5070,0.4601,0.3586,0.1633",\ +"0.5744,0.5588,0.5461,0.5139,0.4670,0.3654,0.1701",\ +"0.6053,0.5897,0.5770,0.5448,0.4979,0.3964,0.2011",\ +"0.6612,0.6456,0.6329,0.6007,0.5538,0.4522,0.2569"); + } + + fall_constraint("SIG2SRAM_constraint_template") { + index_1("0.0056,0.0232,0.0400,0.0728,0.1280,0.2440,0.4760"); + index_2("0.0056,0.0232,0.0400,0.0728,0.1280,0.2440,0.4760"); + values ("0.4939,0.4792,0.4655,0.4372,0.3864,0.2907,0.1062",\ +"0.4989,0.4843,0.4706,0.4423,0.3915,0.2958,0.1112",\ +"0.5040,0.4893,0.4757,0.4473,0.3966,0.3009,0.1163",\ +"0.5129,0.4982,0.4846,0.4562,0.4055,0.3098,0.1252",\ +"0.5197,0.5051,0.4914,0.4631,0.4123,0.3166,0.1320",\ +"0.5507,0.5360,0.5223,0.4940,0.4432,0.3475,0.1630",\ +"0.6065,0.5919,0.5782,0.5499,0.4991,0.4034,0.2188"); + } + } + } + +bus(A_DOUT) { + + bus_type : D_31_0; + direction : output ; + capacitance : 0 ; + max_capacitance : 0.064 ; + memory_read() { + address : A_ADDR ; + } + pin(A_DOUT[31:0]) { + related_power_pin : VDD; + related_ground_pin : VSS; + internal_power() { + rise_power("scalar") { + values (0); + } + fall_power("scalar") { + values (0); + } + } + } + timing() { + related_pin : "A_CLK"; + timing_type : rising_edge ; + timing_sense : non_unate ; + + cell_rise(SIG2SRAM_delay_template) { + index_1("0.0056,0.0232,0.0400,0.0728,0.1280,0.2440,0.4760"); + index_2("0.0008,0.0014,0.0051,0.0100,0.0339,0.0640"); + values ("5.5956,5.5972,5.6048,5.6135,5.6460,5.6818",\ +"5.6061,5.6077,5.6154,5.6241,5.6565,5.6924",\ +"5.6142,5.6158,5.6234,5.6321,5.6646,5.7004",\ +"5.6202,5.6218,5.6295,5.6382,5.6706,5.7065",\ +"5.6260,5.6276,5.6353,5.6440,5.6764,5.7123",\ +"5.6619,5.6635,5.6712,5.6799,5.7123,5.7482",\ +"5.7185,5.7201,5.7278,5.7365,5.7689,5.8048"); + } + cell_fall(SIG2SRAM_delay_template) { + index_1("0.0056,0.0232,0.0400,0.0728,0.1280,0.2440,0.4760"); + index_2("0.0008,0.0014,0.0051,0.0100,0.0339,0.0640"); + values ("5.5345,5.5358,5.5418,5.5490,5.5755,5.6021",\ +"5.5450,5.5464,5.5524,5.5595,5.5860,5.6126",\ +"5.5531,5.5544,5.5604,5.5676,5.5941,5.6207",\ +"5.5592,5.5605,5.5665,5.5736,5.6001,5.6268",\ +"5.5650,5.5663,5.5723,5.5794,5.6059,5.6326",\ +"5.6009,5.6022,5.6082,5.6153,5.6418,5.6685",\ +"5.6574,5.6588,5.6648,5.6719,5.6984,5.7250"); + } + + rise_transition(SRAM_load_template) { + index_1("0.0008,0.0014,0.0051,0.0100,0.0339,0.0640"); + values ("0.0326,0.0341,0.0428,0.0518,0.0923,0.1492"); + } + fall_transition(SRAM_load_template) { + index_1("0.0008,0.0014,0.0051,0.0100,0.0339,0.0640"); + values ("0.0254,0.0265,0.0335,0.0402,0.0707,0.1039"); + } + } +} +cell_leakage_power : 3168.2478; +} +} diff --git a/flow/platforms/ihp-sg13g2/lib/RM_IHPSG13_2P_1024x16_c2_bm_bist_fast_1p32V_m55C.lib b/flow/platforms/ihp-sg13g2/lib/RM_IHPSG13_2P_1024x16_c2_bm_bist_fast_1p32V_m55C.lib new file mode 100644 index 0000000000..483631db7c --- /dev/null +++ b/flow/platforms/ihp-sg13g2/lib/RM_IHPSG13_2P_1024x16_c2_bm_bist_fast_1p32V_m55C.lib @@ -0,0 +1,2898 @@ +/* ------------------------------------------------------*/ +/**/ +/* Copyright 2025 IHP PDK Authors*/ +/**/ +/* Licensed under the Apache License, Version 2.0 (the "License");*/ +/* you may not use this file except in compliance with the License.*/ +/* You may obtain a copy of the License at*/ +/* */ +/* https://www.apache.org/licenses/LICENSE-2.0*/ +/* */ +/* Unless required by applicable law or agreed to in writing, software*/ +/* distributed under the License is distributed on an "AS IS" BASIS,*/ +/* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.*/ +/* See the License for the specific language governing permissions and*/ +/* limitations under the License.*/ +/* */ +/* Generated on Tue Sep 9 10:49:17 2025 */ +/* */ +/* ------------------------------------------------------ */ +library(RM_IHPSG13_2P_1024x16_c2_bm_bist_fast_1p32V_m55C) { + technology (cmos) ; + delay_model : table_lookup ; + define ("add_pg_pin_to_lib", "library", "boolean"); + add_pg_pin_to_lib : true; + voltage_map ( VDD, 1.32); + voltage_map ( VDDARRAY, 1.32); + voltage_map ( VSS, 0.000000 ); + + date : "Tue Sep 9 10:49:15 2025" ; + comment : "IHP Microelectronics GmbH, 2023" ; + revision : 1.0.0 ; + simulation : true ; + nom_process : 1 ; + nom_temperature : -55 ; + nom_voltage : 1.32 ; + + operating_conditions("fast_1p32V_m55C"){ + process : 1 ; + temperature : -55 ; + voltage : 1.32 ; + tree_type : "balanced_tree" ; + } + + default_operating_conditions : fast_1p32V_m55C ; + default_max_transition : 1.0 ; + default_fanout_load : 1.0 ; + default_inout_pin_cap : 0.0 ; + default_input_pin_cap : 0.0 ; + default_output_pin_cap : 0.0 ; + default_cell_leakage_power : 0.0 ; + default_leakage_power_density : 0.0 ; + + slew_lower_threshold_pct_rise : 30 ; + slew_upper_threshold_pct_rise : 70 ; + input_threshold_pct_fall : 50 ; + output_threshold_pct_fall : 50 ; + input_threshold_pct_rise : 50 ; + output_threshold_pct_rise : 50 ; + slew_lower_threshold_pct_fall : 30 ; + slew_upper_threshold_pct_fall : 70 ; + slew_derate_from_library : 0.5; + k_volt_cell_leakage_power : 0.0 ; + k_temp_cell_leakage_power : 0.0 ; + k_process_cell_leakage_power : 0.0 ; + k_volt_internal_power : 0.0 ; + k_temp_internal_power : 0.0 ; + k_process_internal_power : 0.0 ; + + capacitive_load_unit (1,pf) ; + voltage_unit : "1V" ; + current_unit : "1uA" ; + time_unit : "1ns" ; + leakage_power_unit : "1nW" ; + pulling_resistance_unit : "1kohm"; + /* + ------------------------------------------------------------------------------------------ + implicit units overview: + cell_area unit : "um" + internal_power unit : "1e-12 * J/toggle = 1 * uW/MHz" + (capacitive_load_unit * voltage_unit^2) per toggle event + ------------------------------------------------------------------------------------------ + */ + library_features(report_delay_calculation); + define_cell_area (pad_drivers,pad_driver_sites) ; + + lu_table_template(CLKTRAN_constraint_template) { + variable_1 : constrained_pin_transition; + index_1 ( "0.010, 0.050, 0.200, 0.400, 1.000" ); + } + lu_table_template(SRAM_load_template) { + variable_1 : total_output_net_capacitance; + index_1 ( "0.0008,0.0014,0.0051,0.0100,0.0339,0.0640" ); + } + lu_table_template(SIG2SRAM_constraint_template) { + variable_1 : related_pin_transition; + variable_2 : constrained_pin_transition; + index_1 ( "0.0040,0.0176,0.0344,0.0656,0.1120,0.2016,0.3800" ); + index_2 ( "0.0040,0.0176,0.0344,0.0656,0.1120,0.2016,0.3800" ); + } + + lu_table_template(SIG2SRAM_delay_template) { + variable_1 : input_net_transition; + variable_2 : total_output_net_capacitance; + index_1 ( "0.0040,0.0176,0.0344,0.0656,0.1120,0.2016,0.3800" ); + index_2 ( "0.0008,0.0014,0.0051,0.0100,0.0339,0.0640" ); + } + + type (D_15_0) { + base_type : array; + data_type : bit; + bit_width : 16; + bit_from : 15; + bit_to : 0; + downto : true; + } + + type (A_9_0) { + base_type : array; + data_type : bit; + bit_width : 10; + bit_from : 9; + bit_to : 0; + downto : true; + } + +cell(RM_IHPSG13_2P_1024x16_c2_bm_bist) { +pg_pin (VDD) { + pg_type : primary_power; + voltage_name : VDD; +} +pg_pin (VDDARRAY) { + pg_type : primary_power; + voltage_name : VDDARRAY; +} +pg_pin (VSS) { + pg_type : primary_ground; + voltage_name : VSS; +} + +memory() { + type : ram; + address_width : 10; + word_width : 16; +} + +interface_timing : false; +bus_naming_style : "%s[%d]" ; +area : 155153.8157 ; + + pin(A_DLY) { + direction : input ; + capacitance : 0.00421562 ; + max_transition : "1" ; + related_power_pin : VDD; + related_ground_pin : VSS; + internal_power() { + rise_power("scalar") { + values (0); + } + fall_power("scalar") { + values (0); + } + } + } + +bus(A_ADDR) { + bus_type : A_9_0; + direction : input ; + capacitance : 0.0115194 ; + pin(A_ADDR[0]) { + capacitance : 0.00563454 ; + } + pin(A_ADDR[1]) { + capacitance : 0.00744185 ; + } + pin(A_ADDR[2]) { + capacitance : 0.0100611 ; + } + pin(A_ADDR[3]) { + capacitance : 0.00669965 ; + } + pin(A_ADDR[4]) { + capacitance : 0.00614331 ; + } + pin(A_ADDR[5]) { + capacitance : 0.0102172 ; + } + pin(A_ADDR[6]) { + capacitance : 0.0124225 ; + } + pin(A_ADDR[7]) { + capacitance : 0.010114 ; + } + pin(A_ADDR[8]) { + capacitance : 0.0089001 ; + } + max_transition : "0.38" ; + pin(A_ADDR[9:0]) { + related_power_pin : VDD; + related_ground_pin : VSS; + internal_power() { + when : "A_MEN"; + rise_power("scalar"){ + values (0.2111); + } + fall_power("scalar"){ + values (0.2703); + } + } + internal_power() { + when : "!A_MEN"; + rise_power("scalar"){ + values (0.0286); + } + fall_power("scalar"){ + values (0.0026); + } + } + } + timing() { + timing_type : setup_rising; + related_pin : "A_CLK"; + when : "((A_WEN | A_REN)& A_MEN)" + sdf_cond : "A_RW_ACCESS" + + rise_constraint("SIG2SRAM_constraint_template") { + index_1("0.0040,0.0176,0.0344,0.0656,0.1120,0.2016,0.3800"); + index_2("0.0040,0.0176,0.0344,0.0656,0.1120,0.2016,0.3800"); + values ("-0.2371,-0.2215,-0.2098,-0.1824,-0.1434,-0.0691,0.0676",\ +"-0.2449,-0.2332,-0.2176,-0.1902,-0.1551,-0.0770,0.0559",\ +"-0.2605,-0.2488,-0.2332,-0.2059,-0.1707,-0.0965,0.0441",\ +"-0.2879,-0.2723,-0.2605,-0.2332,-0.1941,-0.1199,0.0168",\ +"-0.3230,-0.3113,-0.2996,-0.2723,-0.2332,-0.1590,-0.0184",\ +"-0.4012,-0.3895,-0.3738,-0.3465,-0.3074,-0.2332,-0.0965",\ +"-0.5379,-0.5262,-0.5105,-0.4832,-0.4480,-0.3699,-0.2332"); + } + + fall_constraint("SIG2SRAM_constraint_template") { + index_1("0.0040,0.0176,0.0344,0.0656,0.1120,0.2016,0.3800"); + index_2("0.0040,0.0176,0.0344,0.0656,0.1120,0.2016,0.3800"); + values ("-0.1785,-0.1707,-0.1551,-0.1277,-0.0887,-0.0184,0.1145",\ +"-0.1902,-0.1785,-0.1629,-0.1355,-0.1004,-0.0262,0.1027",\ +"-0.2059,-0.1941,-0.1785,-0.1512,-0.1160,-0.0418,0.0871",\ +"-0.2293,-0.2176,-0.2059,-0.1785,-0.1434,-0.0691,0.0598",\ +"-0.2684,-0.2566,-0.2449,-0.2176,-0.1824,-0.1082,0.0207",\ +"-0.3465,-0.3348,-0.3191,-0.2918,-0.2566,-0.1824,-0.0535",\ +"-0.4832,-0.4715,-0.4559,-0.4324,-0.3934,-0.3191,-0.1902"); + } + } + + + timing() { + timing_type : hold_rising; + related_pin : "A_CLK"; + when : "((A_WEN | A_REN)& A_MEN)" + sdf_cond : "A_RW_ACCESS" + + rise_constraint("SIG2SRAM_constraint_template") { + index_1("0.0040,0.0176,0.0344,0.0656,0.1120,0.2016,0.3800"); + index_2("0.0040,0.0176,0.0344,0.0656,0.1120,0.2016,0.3800"); + values ("0.3410,0.3293,0.3137,0.2863,0.2473,0.1730,0.0324",\ +"0.3488,0.3371,0.3215,0.2941,0.2590,0.1809,0.0480",\ +"0.3684,0.3527,0.3371,0.3098,0.2746,0.1965,0.0598",\ +"0.3918,0.3762,0.3645,0.3371,0.2980,0.2238,0.0871",\ +"0.4309,0.4152,0.4035,0.3762,0.3371,0.2629,0.1223",\ +"0.5051,0.4934,0.4777,0.4504,0.4113,0.3371,0.1965",\ +"0.6418,0.6262,0.6145,0.5871,0.5520,0.4738,0.3332"); + } + + fall_constraint("SIG2SRAM_constraint_template") { + index_1("0.0040,0.0176,0.0344,0.0656,0.1120,0.2016,0.3800"); + index_2("0.0040,0.0176,0.0344,0.0656,0.1120,0.2016,0.3800"); + values ("0.2824,0.2707,0.2551,0.2277,0.1926,0.1184,-0.0105",\ +"0.2902,0.2785,0.2668,0.2395,0.2043,0.1301,0.0012",\ +"0.3059,0.2941,0.2824,0.2551,0.2199,0.1457,0.0168",\ +"0.3332,0.3215,0.3059,0.2785,0.2434,0.1691,0.0402",\ +"0.3723,0.3605,0.3449,0.3176,0.2824,0.2121,0.0793",\ +"0.4465,0.4348,0.4230,0.3918,0.3566,0.2824,0.1535",\ +"0.5832,0.5715,0.5598,0.5324,0.4934,0.4191,0.2902"); + } + } +} +pin(A_WEN) { + direction : input ; + capacitance : 0.00341384 ; + max_transition : "0.38" ; + related_power_pin : VDD; + related_ground_pin : VSS; + internal_power() { + when : "A_MEN"; + rise_power("scalar"){ + values (0.4060); + } + fall_power("scalar"){ + values (0.0178); + } + } + internal_power() { + when : "!A_MEN"; + rise_power("scalar"){ + values (0.0063); + } + fall_power("scalar"){ + values (0.0181); + } + } + timing() { + timing_type : setup_rising; + related_pin : "A_CLK"; + when : "A_MEN" + sdf_cond : "A_MEN" + + rise_constraint("SIG2SRAM_constraint_template") { + index_1("0.0040,0.0176,0.0344,0.0656,0.1120,0.2016,0.3800"); + index_2("0.0040,0.0176,0.0344,0.0656,0.1120,0.2016,0.3800"); + values ("0.1418,0.1496,0.1652,0.1887,0.2316,0.3059,0.4465",\ +"0.1301,0.1379,0.1535,0.1809,0.2199,0.2941,0.4348",\ +"0.1145,0.1262,0.1379,0.1652,0.2043,0.2785,0.4191",\ +"0.0871,0.0949,0.1105,0.1379,0.1770,0.2512,0.3879",\ +"0.0480,0.0598,0.0754,0.0988,0.1379,0.2082,0.3527",\ +"-0.0262,-0.0145,0.0012,0.0246,0.0676,0.1379,0.2785",\ +"-0.1668,-0.1551,-0.1395,-0.1121,-0.0730,0.0012,0.1418"); + } + + fall_constraint("SIG2SRAM_constraint_template") { + index_1("0.0040,0.0176,0.0344,0.0656,0.1120,0.2016,0.3800"); + index_2("0.0040,0.0176,0.0344,0.0656,0.1120,0.2016,0.3800"); + values ("0.2082,0.2160,0.2316,0.2590,0.2941,0.3684,0.5012",\ +"0.1926,0.2043,0.2199,0.2473,0.2824,0.3566,0.4895",\ +"0.1770,0.1887,0.2043,0.2316,0.2668,0.3410,0.4777",\ +"0.1535,0.1652,0.1770,0.2043,0.2395,0.3137,0.4504",\ +"0.1145,0.1262,0.1379,0.1652,0.2043,0.2746,0.4113",\ +"0.0402,0.0520,0.0676,0.0910,0.1262,0.2004,0.3332",\ +"-0.0965,-0.0848,-0.0730,-0.0457,-0.0066,0.0637,0.2004"); + } + } + + + timing() { + timing_type : hold_rising; + related_pin : "A_CLK"; + when : "A_MEN" + sdf_cond : "A_MEN" + + rise_constraint("SIG2SRAM_constraint_template") { + index_1("0.0040,0.0176,0.0344,0.0656,0.1120,0.2016,0.3800"); + index_2("0.0040,0.0176,0.0344,0.0656,0.1120,0.2016,0.3800"); + values ("0.1770,0.1652,0.1496,0.1223,0.0793,0.0090,-0.1316",\ +"0.1848,0.1730,0.1574,0.1301,0.0910,0.0168,-0.1199",\ +"0.2004,0.1887,0.1770,0.1496,0.1066,0.0363,-0.1043",\ +"0.2277,0.2160,0.2004,0.1730,0.1340,0.0598,-0.0809",\ +"0.2668,0.2551,0.2395,0.2121,0.1730,0.0988,-0.0418",\ +"0.3410,0.3293,0.3137,0.2863,0.2434,0.1730,0.0324",\ +"0.4816,0.4699,0.4543,0.4230,0.3801,0.3098,0.1730"); + } + + fall_constraint("SIG2SRAM_constraint_template") { + index_1("0.0040,0.0176,0.0344,0.0656,0.1120,0.2016,0.3800"); + index_2("0.0040,0.0176,0.0344,0.0656,0.1120,0.2016,0.3800"); + values ("0.1613,0.1496,0.1379,0.1066,0.0715,0.0012,-0.1355",\ +"0.1730,0.1613,0.1457,0.1184,0.0832,0.0129,-0.1238",\ +"0.1887,0.1770,0.1613,0.1340,0.0988,0.0246,-0.1121",\ +"0.2121,0.2043,0.1887,0.1613,0.1223,0.0520,-0.0848",\ +"0.2512,0.2434,0.2277,0.2004,0.1613,0.0910,-0.0457",\ +"0.3254,0.3176,0.3020,0.2746,0.2355,0.1652,0.0324",\ +"0.4660,0.4543,0.4387,0.4113,0.3723,0.3020,0.1691"); + } + } + } +pin(A_REN) { + direction : input ; + capacitance : 0.00390661 ; + max_transition : "0.38" ; + related_power_pin : VDD; + related_ground_pin : VSS; + internal_power() { + when : "A_MEN"; + rise_power("scalar"){ + values (0.0125); + } + fall_power("scalar"){ + values (0.0108); + } + } + internal_power() { + when : "!A_MEN"; + rise_power("scalar"){ + values (0.0263); + } + fall_power("scalar"){ + values (0.0211); + } + } + timing() { + timing_type : setup_rising; + related_pin : "A_CLK"; + when : "A_MEN" + sdf_cond : "A_MEN" + + rise_constraint("SIG2SRAM_constraint_template") { + index_1("0.0040,0.0176,0.0344,0.0656,0.1120,0.2016,0.3800"); + index_2("0.0040,0.0176,0.0344,0.0656,0.1120,0.2016,0.3800"); + values ("-0.0027,0.0090,0.0246,0.0520,0.0910,0.1613,0.3020",\ +"-0.0105,0.0012,0.0129,0.0363,0.0793,0.1535,0.2902",\ +"-0.0262,-0.0145,-0.0027,0.0246,0.0637,0.1379,0.2785",\ +"-0.0535,-0.0418,-0.0262,0.0012,0.0363,0.1105,0.2512",\ +"-0.0926,-0.0809,-0.0652,-0.0418,-0.0027,0.0715,0.2121",\ +"-0.1668,-0.1551,-0.1395,-0.1082,-0.0770,-0.0027,0.1379",\ +"-0.3035,-0.2918,-0.2762,-0.2488,-0.2137,-0.1434,-0.0027"); + } + + fall_constraint("SIG2SRAM_constraint_template") { + index_1("0.0040,0.0176,0.0344,0.0656,0.1120,0.2016,0.3800"); + index_2("0.0040,0.0176,0.0344,0.0656,0.1120,0.2016,0.3800"); + values ("0.0832,0.0949,0.1105,0.1379,0.1730,0.2473,0.3801",\ +"0.0754,0.0832,0.0988,0.1223,0.1613,0.2355,0.3684",\ +"0.0598,0.0676,0.0832,0.1066,0.1457,0.2121,0.3527",\ +"0.0324,0.0441,0.0598,0.0871,0.1223,0.1926,0.3293",\ +"-0.0066,0.0051,0.0168,0.0480,0.0832,0.1535,0.2902",\ +"-0.0809,-0.0691,-0.0574,-0.0301,0.0090,0.0832,0.2121",\ +"-0.2176,-0.2059,-0.1941,-0.1668,-0.1277,-0.0574,0.0793"); + } + } + + + timing() { + timing_type : hold_rising; + related_pin : "A_CLK"; + when : "A_MEN" + sdf_cond : "A_MEN" + + rise_constraint("SIG2SRAM_constraint_template") { + index_1("0.0040,0.0176,0.0344,0.0656,0.1120,0.2016,0.3800"); + index_2("0.0040,0.0176,0.0344,0.0656,0.1120,0.2016,0.3800"); + values ("0.1887,0.1770,0.1613,0.1340,0.0949,0.0207,-0.1160",\ +"0.1965,0.1848,0.1730,0.1457,0.1027,0.0324,-0.1082",\ +"0.2160,0.2004,0.1887,0.1613,0.1184,0.0480,-0.0926",\ +"0.2395,0.2277,0.2121,0.1848,0.1457,0.0715,-0.0652",\ +"0.2785,0.2668,0.2512,0.2238,0.1848,0.1105,-0.0262",\ +"0.3527,0.3410,0.3254,0.2980,0.2551,0.1848,0.0480",\ +"0.4934,0.4816,0.4660,0.4387,0.3957,0.3254,0.1887"); + } + + fall_constraint("SIG2SRAM_constraint_template") { + index_1("0.0040,0.0176,0.0344,0.0656,0.1120,0.2016,0.3800"); + index_2("0.0040,0.0176,0.0344,0.0656,0.1120,0.2016,0.3800"); + values ("0.1730,0.1613,0.1496,0.1184,0.0793,0.0129,-0.1238",\ +"0.1848,0.1730,0.1574,0.1301,0.0910,0.0207,-0.1121",\ +"0.2004,0.1887,0.1730,0.1457,0.1066,0.0363,-0.1004",\ +"0.2238,0.2121,0.2004,0.1691,0.1340,0.0598,-0.0730",\ +"0.2629,0.2512,0.2395,0.2121,0.1691,0.0988,-0.0340",\ +"0.3371,0.3254,0.3137,0.2863,0.2434,0.1730,0.0402",\ +"0.4777,0.4660,0.4504,0.4230,0.3840,0.3137,0.1809"); + } + } + } +pin(A_MEN) { + direction : input ; + capacitance : 0.00326046 ; + max_transition : "0.38" ; + related_power_pin : VDD; + related_ground_pin : VSS; + internal_power() { + rise_power("scalar"){ + values (0.1484); + } + fall_power("scalar"){ + values (0.2101); + } + } + timing() { + timing_type : setup_rising; + related_pin : "A_CLK"; + + rise_constraint("SIG2SRAM_constraint_template") { + index_1("0.0040,0.0176,0.0344,0.0656,0.1120,0.2016,0.3800"); + index_2("0.0040,0.0176,0.0344,0.0656,0.1120,0.2016,0.3800"); + values ("0.1418,0.1496,0.1652,0.1926,0.2316,0.3059,0.4465",\ +"0.1301,0.1379,0.1535,0.1809,0.2199,0.2941,0.4348",\ +"0.1145,0.1262,0.1418,0.1652,0.2043,0.2785,0.4191",\ +"0.0871,0.0949,0.1105,0.1379,0.1770,0.2512,0.3879",\ +"0.0480,0.0598,0.0754,0.0988,0.1379,0.2082,0.3488",\ +"-0.0262,-0.0145,0.0012,0.0285,0.0676,0.1379,0.2785",\ +"-0.1668,-0.1551,-0.1395,-0.1121,-0.0730,0.0012,0.1379"); + } + + fall_constraint("SIG2SRAM_constraint_template") { + index_1("0.0040,0.0176,0.0344,0.0656,0.1120,0.2016,0.3800"); + index_2("0.0040,0.0176,0.0344,0.0656,0.1120,0.2016,0.3800"); + values ("0.2082,0.2199,0.2316,0.2590,0.2980,0.3723,0.5051",\ +"0.1965,0.2082,0.2199,0.2473,0.2863,0.3605,0.4934",\ +"0.1809,0.1926,0.2043,0.2316,0.2707,0.3449,0.4777",\ +"0.1574,0.1691,0.1809,0.2082,0.2434,0.3176,0.4543",\ +"0.1145,0.1262,0.1418,0.1691,0.2043,0.2785,0.4113",\ +"0.0441,0.0559,0.0676,0.0949,0.1301,0.2004,0.3332",\ +"-0.0965,-0.0848,-0.0691,-0.0418,-0.0066,0.0676,0.2004"); + } + } + + + timing() { + timing_type : hold_rising; + related_pin : "A_CLK"; + + rise_constraint("SIG2SRAM_constraint_template") { + index_1("0.0040,0.0176,0.0344,0.0656,0.1120,0.2016,0.3800"); + index_2("0.0040,0.0176,0.0344,0.0656,0.1120,0.2016,0.3800"); + values ("0.1770,0.1652,0.1535,0.1262,0.0832,0.0129,-0.1277",\ +"0.1887,0.1770,0.1613,0.1340,0.0949,0.0207,-0.1199",\ +"0.2043,0.1926,0.1770,0.1496,0.1105,0.0363,-0.1043",\ +"0.2277,0.2160,0.2043,0.1770,0.1379,0.0598,-0.0770",\ +"0.2668,0.2551,0.2434,0.2160,0.1730,0.0988,-0.0379",\ +"0.3449,0.3332,0.3176,0.2902,0.2473,0.1730,0.0363",\ +"0.4816,0.4699,0.4543,0.4270,0.3840,0.3098,0.1770"); + } + + fall_constraint("SIG2SRAM_constraint_template") { + index_1("0.0040,0.0176,0.0344,0.0656,0.1120,0.2016,0.3800"); + index_2("0.0040,0.0176,0.0344,0.0656,0.1120,0.2016,0.3800"); + values ("0.1613,0.1496,0.1379,0.1105,0.0715,0.0012,-0.1355",\ +"0.1730,0.1613,0.1496,0.1184,0.0832,0.0129,-0.1238",\ +"0.1887,0.1770,0.1652,0.1340,0.0988,0.0285,-0.1121",\ +"0.2121,0.2043,0.1887,0.1613,0.1223,0.0520,-0.0848",\ +"0.2551,0.2434,0.2277,0.2004,0.1613,0.0910,-0.0418",\ +"0.3293,0.3176,0.3020,0.2746,0.2395,0.1652,0.0324",\ +"0.4660,0.4543,0.4426,0.4113,0.3762,0.3020,0.1691"); + } + } + } +bus(A_BM) { + bus_type : D_15_0; + direction : input ; + capacitance : 0.00388883 ; + max_transition : "0.38" ; + pin(A_BM[15:0]) { + related_power_pin : VDD; + related_ground_pin : VSS; + internal_power() { + when : "A_MEN"; + rise_power("scalar"){ + values (0.0783); + } + fall_power("scalar"){ + values (0.0812); + } + } + internal_power() { + when : "!A_MEN"; + rise_power("scalar"){ + values (0.1034); + } + fall_power("scalar"){ + values (0.0834); + } + } + } + timing() { + timing_type : setup_rising; + related_pin : "A_CLK"; + when : "(A_WEN & A_MEN)" + sdf_cond : "A_RW_ACCESS" + + rise_constraint("SIG2SRAM_constraint_template") { + index_1("0.0040,0.0176,0.0344,0.0656,0.1120,0.2016,0.3800"); + index_2("0.0040,0.0176,0.0344,0.0656,0.1120,0.2016,0.3800"); + values ("-0.2117,-0.2009,-0.1853,-0.1599,-0.1189,-0.0456,0.0891",\ +"-0.2155,-0.2048,-0.1892,-0.1638,-0.1228,-0.0495,0.0852",\ +"-0.2193,-0.2086,-0.1930,-0.1676,-0.1266,-0.0533,0.0814",\ +"-0.2226,-0.2118,-0.1962,-0.1708,-0.1298,-0.0566,0.0782",\ +"-0.2350,-0.2243,-0.2087,-0.1833,-0.1423,-0.0690,0.0657",\ +"-0.2525,-0.2418,-0.2261,-0.2007,-0.1597,-0.0865,0.0483",\ +"-0.2802,-0.2694,-0.2538,-0.2284,-0.1874,-0.1141,0.0206"); + } + + fall_constraint("SIG2SRAM_constraint_template") { + index_1("0.0040,0.0176,0.0344,0.0656,0.1120,0.2016,0.3800"); + index_2("0.0040,0.0176,0.0344,0.0656,0.1120,0.2016,0.3800"); + values ("-0.1882,-0.1765,-0.1638,-0.1365,-0.0994,-0.0261,0.1018",\ +"-0.1921,-0.1804,-0.1677,-0.1404,-0.1032,-0.0300,0.0979",\ +"-0.1959,-0.1842,-0.1715,-0.1441,-0.1070,-0.0338,0.0941",\ +"-0.1992,-0.1874,-0.1747,-0.1474,-0.1103,-0.0370,0.0909",\ +"-0.2116,-0.1999,-0.1872,-0.1598,-0.1227,-0.0495,0.0784",\ +"-0.2291,-0.2173,-0.2046,-0.1773,-0.1402,-0.0669,0.0610",\ +"-0.2567,-0.2450,-0.2323,-0.2050,-0.1678,-0.0946,0.0333"); + } + } + + + timing() { + timing_type : hold_rising; + related_pin : "A_CLK"; + when : "(A_WEN & A_MEN)" + sdf_cond : "A_RW_ACCESS" + + rise_constraint("SIG2SRAM_constraint_template") { + index_1("0.0040,0.0176,0.0344,0.0656,0.1120,0.2016,0.3800"); + index_2("0.0040,0.0176,0.0344,0.0656,0.1120,0.2016,0.3800"); + values ("0.3170,0.3073,0.2916,0.2653,0.2282,0.1539,0.0192",\ +"0.3209,0.3111,0.2955,0.2692,0.2320,0.1578,0.0231",\ +"0.3247,0.3149,0.2993,0.2730,0.2358,0.1616,0.0269",\ +"0.3280,0.3182,0.3026,0.2762,0.2391,0.1649,0.0301",\ +"0.3404,0.3306,0.3150,0.2887,0.2515,0.1773,0.0426",\ +"0.3579,0.3481,0.3325,0.3061,0.2690,0.1948,0.0600",\ +"0.3855,0.3758,0.3601,0.3338,0.2967,0.2224,0.0877"); + } + + fall_constraint("SIG2SRAM_constraint_template") { + index_1("0.0040,0.0176,0.0344,0.0656,0.1120,0.2016,0.3800"); + index_2("0.0040,0.0176,0.0344,0.0656,0.1120,0.2016,0.3800"); + values ("0.2887,0.2780,0.2643,0.2370,0.2008,0.1286,-0.0013",\ +"0.2926,0.2818,0.2682,0.2408,0.2047,0.1324,0.0026",\ +"0.2964,0.2856,0.2720,0.2446,0.2085,0.1362,0.0064",\ +"0.2996,0.2889,0.2752,0.2479,0.2118,0.1395,0.0096",\ +"0.3121,0.3013,0.2877,0.2603,0.2242,0.1519,0.0221",\ +"0.3295,0.3188,0.3051,0.2778,0.2417,0.1694,0.0395",\ +"0.3572,0.3465,0.3328,0.3054,0.2693,0.1970,0.0672"); + } + } +} + pin(A_CLK) { + direction : input; + capacitance : 0.00389386; + max_transition : "0.38"; + clock : "true" ; + pin_func_type : active_rising ; + + timing () { + timing_type : "min_pulse_width"; + related_pin : "A_CLK"; + rise_constraint("CLKTRAN_constraint_template") { + index_1("0.004,0.38"); + values("0.12,0.12"); + } + } + + related_power_pin : VDD; + related_ground_pin : VSS; + + internal_power() { + when : "!A_MEN & !A_WEN & !A_REN"; + rise_power("scalar"){ + values (0); + } + fall_power("scalar"){ + values (0); + } + } + internal_power() { + when : "!A_MEN & A_WEN & !A_REN"; + rise_power("scalar"){ + values (0.7039); + } + fall_power("scalar"){ + values (0); + } + } + internal_power() { + when : "A_MEN & A_WEN & !A_REN"; + rise_power("scalar"){ + values (40.8199); + } + fall_power("scalar"){ + values (0); + } + } + internal_power() { + when : "A_MEN & A_WEN & A_REN"; + rise_power("scalar"){ + values (41.5232); + } + fall_power("scalar"){ + values (0); + } + } + internal_power() { + when : "A_MEN & !A_WEN & A_REN"; + rise_power("scalar"){ + values (33.7892); + } + fall_power("scalar"){ + values (0); + } + } + internal_power() { + when : "!A_MEN & !A_WEN & A_REN"; + rise_power("scalar"){ + values (0.4120); + } + fall_power("scalar"){ + values (0); + } + } + internal_power() { + when : "!A_MEN & A_WEN & A_REN"; + rise_power("scalar"){ + values (0.9290); + } + fall_power("scalar"){ + values (0); + } + } + internal_power() { + when : "A_MEN & !A_WEN & !A_REN"; + rise_power("scalar"){ + values (0); + } + fall_power("scalar"){ + values (0); + } + } + } + bus(A_DIN) { + bus_type : D_15_0; + direction : input ; + capacitance : 0.00505326 ; + memory_write() { + address : A_ADDR ; + clocked_on : A_CLK; + } + + max_transition : "0.38" ; + pin(A_DIN[15:0]) { + related_power_pin : VDD; + related_ground_pin : VSS; + internal_power() { + when : "A_MEN"; + rise_power("scalar"){ + values (0.0783); + } + fall_power("scalar"){ + values (0.0812); + } + } + internal_power() { + when : "!A_MEN"; + rise_power("scalar"){ + values (0.1034); + } + fall_power("scalar"){ + values (0.0834); + } + } + } + timing() { + timing_type : setup_rising; + related_pin : "A_CLK"; + when : "(A_WEN & A_MEN)"; + sdf_cond : "A_W_ACCESS"; + + rise_constraint("SIG2SRAM_constraint_template") { + index_1("0.0040,0.0176,0.0344,0.0656,0.1120,0.2016,0.3800"); + index_2("0.0040,0.0176,0.0344,0.0656,0.1120,0.2016,0.3800"); + values ("-0.2117,-0.2009,-0.1853,-0.1599,-0.1189,-0.0456,0.0891",\ +"-0.2155,-0.2048,-0.1892,-0.1638,-0.1228,-0.0495,0.0852",\ +"-0.2193,-0.2086,-0.1930,-0.1676,-0.1266,-0.0533,0.0814",\ +"-0.2226,-0.2118,-0.1962,-0.1708,-0.1298,-0.0566,0.0782",\ +"-0.2350,-0.2243,-0.2087,-0.1833,-0.1423,-0.0690,0.0657",\ +"-0.2525,-0.2418,-0.2261,-0.2007,-0.1597,-0.0865,0.0483",\ +"-0.2802,-0.2694,-0.2538,-0.2284,-0.1874,-0.1141,0.0206"); + } + + fall_constraint("SIG2SRAM_constraint_template") { + index_1("0.0040,0.0176,0.0344,0.0656,0.1120,0.2016,0.3800"); + index_2("0.0040,0.0176,0.0344,0.0656,0.1120,0.2016,0.3800"); + values ("-0.1882,-0.1765,-0.1638,-0.1365,-0.0994,-0.0261,0.1018",\ +"-0.1921,-0.1804,-0.1677,-0.1404,-0.1032,-0.0300,0.0979",\ +"-0.1959,-0.1842,-0.1715,-0.1441,-0.1070,-0.0338,0.0941",\ +"-0.1992,-0.1874,-0.1747,-0.1474,-0.1103,-0.0370,0.0909",\ +"-0.2116,-0.1999,-0.1872,-0.1598,-0.1227,-0.0495,0.0784",\ +"-0.2291,-0.2173,-0.2046,-0.1773,-0.1402,-0.0669,0.0610",\ +"-0.2567,-0.2450,-0.2323,-0.2050,-0.1678,-0.0946,0.0333"); + } + } + + timing() { + timing_type : hold_rising; + related_pin : "A_CLK"; + when : "(A_WEN & A_MEN)"; + sdf_cond : "A_W_ACCESS"; + + rise_constraint("SIG2SRAM_constraint_template") { + index_1("0.0040,0.0176,0.0344,0.0656,0.1120,0.2016,0.3800"); + index_2("0.0040,0.0176,0.0344,0.0656,0.1120,0.2016,0.3800"); + values ("0.3170,0.3073,0.2916,0.2653,0.2282,0.1539,0.0192",\ +"0.3209,0.3111,0.2955,0.2692,0.2320,0.1578,0.0231",\ +"0.3247,0.3149,0.2993,0.2730,0.2358,0.1616,0.0269",\ +"0.3280,0.3182,0.3026,0.2762,0.2391,0.1649,0.0301",\ +"0.3404,0.3306,0.3150,0.2887,0.2515,0.1773,0.0426",\ +"0.3579,0.3481,0.3325,0.3061,0.2690,0.1948,0.0600",\ +"0.3855,0.3758,0.3601,0.3338,0.2967,0.2224,0.0877"); + } + + fall_constraint("SIG2SRAM_constraint_template") { + index_1("0.0040,0.0176,0.0344,0.0656,0.1120,0.2016,0.3800"); + index_2("0.0040,0.0176,0.0344,0.0656,0.1120,0.2016,0.3800"); + values ("0.2887,0.2780,0.2643,0.2370,0.2008,0.1286,-0.0013",\ +"0.2926,0.2818,0.2682,0.2408,0.2047,0.1324,0.0026",\ +"0.2964,0.2856,0.2720,0.2446,0.2085,0.1362,0.0064",\ +"0.2996,0.2889,0.2752,0.2479,0.2118,0.1395,0.0096",\ +"0.3121,0.3013,0.2877,0.2603,0.2242,0.1519,0.0221",\ +"0.3295,0.3188,0.3051,0.2778,0.2417,0.1694,0.0395",\ +"0.3572,0.3465,0.3328,0.3054,0.2693,0.1970,0.0672"); + } + } + } + + pin(A_BIST_EN) { + direction : input ; + capacitance : 0.00421562 ; + max_transition : "1" ; + related_power_pin : VDD; + related_ground_pin : VSS; + internal_power() { + rise_power("scalar") { + values (0); + } + fall_power("scalar") { + values (0); + } + } + } + +bus(A_BIST_ADDR) { + bus_type : A_9_0; + direction : input ; + capacitance : 0.0115194 ; + pin(A_BIST_ADDR[0]) { + capacitance : 0.00563454 ; + } + pin(A_BIST_ADDR[1]) { + capacitance : 0.00744185 ; + } + pin(A_BIST_ADDR[2]) { + capacitance : 0.0100611 ; + } + pin(A_BIST_ADDR[3]) { + capacitance : 0.00669965 ; + } + pin(A_BIST_ADDR[4]) { + capacitance : 0.00614331 ; + } + pin(A_BIST_ADDR[5]) { + capacitance : 0.0102172 ; + } + pin(A_BIST_ADDR[6]) { + capacitance : 0.0124225 ; + } + pin(A_BIST_ADDR[7]) { + capacitance : 0.010114 ; + } + pin(A_BIST_ADDR[8]) { + capacitance : 0.0089001 ; + } + max_transition : "0.38" ; + pin(A_BIST_ADDR[9:0]) { + related_power_pin : VDD; + related_ground_pin : VSS; + internal_power() { + when : "A_BIST_MEN"; + rise_power("scalar"){ + values (0.2111); + } + fall_power("scalar"){ + values (0.2703); + } + } + internal_power() { + when : "!A_BIST_MEN"; + rise_power("scalar"){ + values (0.0286); + } + fall_power("scalar"){ + values (0.0026); + } + } + } + timing() { + timing_type : setup_rising; + related_pin : "A_BIST_CLK"; + when : "((A_BIST_WEN | A_BIST_REN)& A_BIST_MEN)" + sdf_cond : "A_BIST_RW_ACCESS" + + rise_constraint("SIG2SRAM_constraint_template") { + index_1("0.0040,0.0176,0.0344,0.0656,0.1120,0.2016,0.3800"); + index_2("0.0040,0.0176,0.0344,0.0656,0.1120,0.2016,0.3800"); + values ("-0.2371,-0.2215,-0.2098,-0.1824,-0.1434,-0.0691,0.0676",\ +"-0.2449,-0.2332,-0.2176,-0.1902,-0.1551,-0.0770,0.0559",\ +"-0.2605,-0.2488,-0.2332,-0.2059,-0.1707,-0.0965,0.0441",\ +"-0.2879,-0.2723,-0.2605,-0.2332,-0.1941,-0.1199,0.0168",\ +"-0.3230,-0.3113,-0.2996,-0.2723,-0.2332,-0.1590,-0.0184",\ +"-0.4012,-0.3895,-0.3738,-0.3465,-0.3074,-0.2332,-0.0965",\ +"-0.5379,-0.5262,-0.5105,-0.4832,-0.4480,-0.3699,-0.2332"); + } + + fall_constraint("SIG2SRAM_constraint_template") { + index_1("0.0040,0.0176,0.0344,0.0656,0.1120,0.2016,0.3800"); + index_2("0.0040,0.0176,0.0344,0.0656,0.1120,0.2016,0.3800"); + values ("-0.1785,-0.1707,-0.1551,-0.1277,-0.0887,-0.0184,0.1145",\ +"-0.1902,-0.1785,-0.1629,-0.1355,-0.1004,-0.0262,0.1027",\ +"-0.2059,-0.1941,-0.1785,-0.1512,-0.1160,-0.0418,0.0871",\ +"-0.2293,-0.2176,-0.2059,-0.1785,-0.1434,-0.0691,0.0598",\ +"-0.2684,-0.2566,-0.2449,-0.2176,-0.1824,-0.1082,0.0207",\ +"-0.3465,-0.3348,-0.3191,-0.2918,-0.2566,-0.1824,-0.0535",\ +"-0.4832,-0.4715,-0.4559,-0.4324,-0.3934,-0.3191,-0.1902"); + } + } + + + timing() { + timing_type : hold_rising; + related_pin : "A_BIST_CLK"; + when : "((A_BIST_WEN | A_BIST_REN)& A_BIST_MEN)" + sdf_cond : "A_BIST_RW_ACCESS" + + rise_constraint("SIG2SRAM_constraint_template") { + index_1("0.0040,0.0176,0.0344,0.0656,0.1120,0.2016,0.3800"); + index_2("0.0040,0.0176,0.0344,0.0656,0.1120,0.2016,0.3800"); + values ("0.3410,0.3293,0.3137,0.2863,0.2473,0.1730,0.0324",\ +"0.3488,0.3371,0.3215,0.2941,0.2590,0.1809,0.0480",\ +"0.3684,0.3527,0.3371,0.3098,0.2746,0.1965,0.0598",\ +"0.3918,0.3762,0.3645,0.3371,0.2980,0.2238,0.0871",\ +"0.4309,0.4152,0.4035,0.3762,0.3371,0.2629,0.1223",\ +"0.5051,0.4934,0.4777,0.4504,0.4113,0.3371,0.1965",\ +"0.6418,0.6262,0.6145,0.5871,0.5520,0.4738,0.3332"); + } + + fall_constraint("SIG2SRAM_constraint_template") { + index_1("0.0040,0.0176,0.0344,0.0656,0.1120,0.2016,0.3800"); + index_2("0.0040,0.0176,0.0344,0.0656,0.1120,0.2016,0.3800"); + values ("0.2824,0.2707,0.2551,0.2277,0.1926,0.1184,-0.0105",\ +"0.2902,0.2785,0.2668,0.2395,0.2043,0.1301,0.0012",\ +"0.3059,0.2941,0.2824,0.2551,0.2199,0.1457,0.0168",\ +"0.3332,0.3215,0.3059,0.2785,0.2434,0.1691,0.0402",\ +"0.3723,0.3605,0.3449,0.3176,0.2824,0.2121,0.0793",\ +"0.4465,0.4348,0.4230,0.3918,0.3566,0.2824,0.1535",\ +"0.5832,0.5715,0.5598,0.5324,0.4934,0.4191,0.2902"); + } + } +} +pin(A_BIST_WEN) { + direction : input ; + capacitance : 0.00341384 ; + max_transition : "0.38" ; + related_power_pin : VDD; + related_ground_pin : VSS; + internal_power() { + when : "A_BIST_MEN"; + rise_power("scalar"){ + values (0.4060); + } + fall_power("scalar"){ + values (0.0178); + } + } + internal_power() { + when : "!A_BIST_MEN"; + rise_power("scalar"){ + values (0.0063); + } + fall_power("scalar"){ + values (0.0181); + } + } + timing() { + timing_type : setup_rising; + related_pin : "A_BIST_CLK"; + when : "A_BIST_MEN" + sdf_cond : "A_BIST_MEN" + + rise_constraint("SIG2SRAM_constraint_template") { + index_1("0.0040,0.0176,0.0344,0.0656,0.1120,0.2016,0.3800"); + index_2("0.0040,0.0176,0.0344,0.0656,0.1120,0.2016,0.3800"); + values ("0.1418,0.1496,0.1652,0.1887,0.2316,0.3059,0.4465",\ +"0.1301,0.1379,0.1535,0.1809,0.2199,0.2941,0.4348",\ +"0.1145,0.1262,0.1379,0.1652,0.2043,0.2785,0.4191",\ +"0.0871,0.0949,0.1105,0.1379,0.1770,0.2512,0.3879",\ +"0.0480,0.0598,0.0754,0.0988,0.1379,0.2082,0.3527",\ +"-0.0262,-0.0145,0.0012,0.0246,0.0676,0.1379,0.2785",\ +"-0.1668,-0.1551,-0.1395,-0.1121,-0.0730,0.0012,0.1418"); + } + + fall_constraint("SIG2SRAM_constraint_template") { + index_1("0.0040,0.0176,0.0344,0.0656,0.1120,0.2016,0.3800"); + index_2("0.0040,0.0176,0.0344,0.0656,0.1120,0.2016,0.3800"); + values ("0.2082,0.2160,0.2316,0.2590,0.2941,0.3684,0.5012",\ +"0.1926,0.2043,0.2199,0.2473,0.2824,0.3566,0.4895",\ +"0.1770,0.1887,0.2043,0.2316,0.2668,0.3410,0.4777",\ +"0.1535,0.1652,0.1770,0.2043,0.2395,0.3137,0.4504",\ +"0.1145,0.1262,0.1379,0.1652,0.2043,0.2746,0.4113",\ +"0.0402,0.0520,0.0676,0.0910,0.1262,0.2004,0.3332",\ +"-0.0965,-0.0848,-0.0730,-0.0457,-0.0066,0.0637,0.2004"); + } + } + + + timing() { + timing_type : hold_rising; + related_pin : "A_BIST_CLK"; + when : "A_BIST_MEN" + sdf_cond : "A_BIST_MEN" + + rise_constraint("SIG2SRAM_constraint_template") { + index_1("0.0040,0.0176,0.0344,0.0656,0.1120,0.2016,0.3800"); + index_2("0.0040,0.0176,0.0344,0.0656,0.1120,0.2016,0.3800"); + values ("0.1770,0.1652,0.1496,0.1223,0.0793,0.0090,-0.1316",\ +"0.1848,0.1730,0.1574,0.1301,0.0910,0.0168,-0.1199",\ +"0.2004,0.1887,0.1770,0.1496,0.1066,0.0363,-0.1043",\ +"0.2277,0.2160,0.2004,0.1730,0.1340,0.0598,-0.0809",\ +"0.2668,0.2551,0.2395,0.2121,0.1730,0.0988,-0.0418",\ +"0.3410,0.3293,0.3137,0.2863,0.2434,0.1730,0.0324",\ +"0.4816,0.4699,0.4543,0.4230,0.3801,0.3098,0.1730"); + } + + fall_constraint("SIG2SRAM_constraint_template") { + index_1("0.0040,0.0176,0.0344,0.0656,0.1120,0.2016,0.3800"); + index_2("0.0040,0.0176,0.0344,0.0656,0.1120,0.2016,0.3800"); + values ("0.1613,0.1496,0.1379,0.1066,0.0715,0.0012,-0.1355",\ +"0.1730,0.1613,0.1457,0.1184,0.0832,0.0129,-0.1238",\ +"0.1887,0.1770,0.1613,0.1340,0.0988,0.0246,-0.1121",\ +"0.2121,0.2043,0.1887,0.1613,0.1223,0.0520,-0.0848",\ +"0.2512,0.2434,0.2277,0.2004,0.1613,0.0910,-0.0457",\ +"0.3254,0.3176,0.3020,0.2746,0.2355,0.1652,0.0324",\ +"0.4660,0.4543,0.4387,0.4113,0.3723,0.3020,0.1691"); + } + } + } +pin(A_BIST_REN) { + direction : input ; + capacitance : 0.00390661 ; + max_transition : "0.38" ; + related_power_pin : VDD; + related_ground_pin : VSS; + internal_power() { + when : "A_BIST_MEN"; + rise_power("scalar"){ + values (0.0125); + } + fall_power("scalar"){ + values (0.0108); + } + } + internal_power() { + when : "!A_BIST_MEN"; + rise_power("scalar"){ + values (0.0263); + } + fall_power("scalar"){ + values (0.0211); + } + } + timing() { + timing_type : setup_rising; + related_pin : "A_BIST_CLK"; + when : "A_BIST_MEN" + sdf_cond : "A_BIST_MEN" + + rise_constraint("SIG2SRAM_constraint_template") { + index_1("0.0040,0.0176,0.0344,0.0656,0.1120,0.2016,0.3800"); + index_2("0.0040,0.0176,0.0344,0.0656,0.1120,0.2016,0.3800"); + values ("-0.0027,0.0090,0.0246,0.0520,0.0910,0.1613,0.3020",\ +"-0.0105,0.0012,0.0129,0.0363,0.0793,0.1535,0.2902",\ +"-0.0262,-0.0145,-0.0027,0.0246,0.0637,0.1379,0.2785",\ +"-0.0535,-0.0418,-0.0262,0.0012,0.0363,0.1105,0.2512",\ +"-0.0926,-0.0809,-0.0652,-0.0418,-0.0027,0.0715,0.2121",\ +"-0.1668,-0.1551,-0.1395,-0.1082,-0.0770,-0.0027,0.1379",\ +"-0.3035,-0.2918,-0.2762,-0.2488,-0.2137,-0.1434,-0.0027"); + } + + fall_constraint("SIG2SRAM_constraint_template") { + index_1("0.0040,0.0176,0.0344,0.0656,0.1120,0.2016,0.3800"); + index_2("0.0040,0.0176,0.0344,0.0656,0.1120,0.2016,0.3800"); + values ("0.0832,0.0949,0.1105,0.1379,0.1730,0.2473,0.3801",\ +"0.0754,0.0832,0.0988,0.1223,0.1613,0.2355,0.3684",\ +"0.0598,0.0676,0.0832,0.1066,0.1457,0.2121,0.3527",\ +"0.0324,0.0441,0.0598,0.0871,0.1223,0.1926,0.3293",\ +"-0.0066,0.0051,0.0168,0.0480,0.0832,0.1535,0.2902",\ +"-0.0809,-0.0691,-0.0574,-0.0301,0.0090,0.0832,0.2121",\ +"-0.2176,-0.2059,-0.1941,-0.1668,-0.1277,-0.0574,0.0793"); + } + } + + + timing() { + timing_type : hold_rising; + related_pin : "A_BIST_CLK"; + when : "A_BIST_MEN" + sdf_cond : "A_BIST_MEN" + + rise_constraint("SIG2SRAM_constraint_template") { + index_1("0.0040,0.0176,0.0344,0.0656,0.1120,0.2016,0.3800"); + index_2("0.0040,0.0176,0.0344,0.0656,0.1120,0.2016,0.3800"); + values ("0.1887,0.1770,0.1613,0.1340,0.0949,0.0207,-0.1160",\ +"0.1965,0.1848,0.1730,0.1457,0.1027,0.0324,-0.1082",\ +"0.2160,0.2004,0.1887,0.1613,0.1184,0.0480,-0.0926",\ +"0.2395,0.2277,0.2121,0.1848,0.1457,0.0715,-0.0652",\ +"0.2785,0.2668,0.2512,0.2238,0.1848,0.1105,-0.0262",\ +"0.3527,0.3410,0.3254,0.2980,0.2551,0.1848,0.0480",\ +"0.4934,0.4816,0.4660,0.4387,0.3957,0.3254,0.1887"); + } + + fall_constraint("SIG2SRAM_constraint_template") { + index_1("0.0040,0.0176,0.0344,0.0656,0.1120,0.2016,0.3800"); + index_2("0.0040,0.0176,0.0344,0.0656,0.1120,0.2016,0.3800"); + values ("0.1730,0.1613,0.1496,0.1184,0.0793,0.0129,-0.1238",\ +"0.1848,0.1730,0.1574,0.1301,0.0910,0.0207,-0.1121",\ +"0.2004,0.1887,0.1730,0.1457,0.1066,0.0363,-0.1004",\ +"0.2238,0.2121,0.2004,0.1691,0.1340,0.0598,-0.0730",\ +"0.2629,0.2512,0.2395,0.2121,0.1691,0.0988,-0.0340",\ +"0.3371,0.3254,0.3137,0.2863,0.2434,0.1730,0.0402",\ +"0.4777,0.4660,0.4504,0.4230,0.3840,0.3137,0.1809"); + } + } + } +pin(A_BIST_MEN) { + direction : input ; + capacitance : 0.00326046 ; + max_transition : "0.38" ; + related_power_pin : VDD; + related_ground_pin : VSS; + internal_power() { + rise_power("scalar"){ + values (0.1484); + } + fall_power("scalar"){ + values (0.2101); + } + } + timing() { + timing_type : setup_rising; + related_pin : "A_BIST_CLK"; + + rise_constraint("SIG2SRAM_constraint_template") { + index_1("0.0040,0.0176,0.0344,0.0656,0.1120,0.2016,0.3800"); + index_2("0.0040,0.0176,0.0344,0.0656,0.1120,0.2016,0.3800"); + values ("0.1418,0.1496,0.1652,0.1926,0.2316,0.3059,0.4465",\ +"0.1301,0.1379,0.1535,0.1809,0.2199,0.2941,0.4348",\ +"0.1145,0.1262,0.1418,0.1652,0.2043,0.2785,0.4191",\ +"0.0871,0.0949,0.1105,0.1379,0.1770,0.2512,0.3879",\ +"0.0480,0.0598,0.0754,0.0988,0.1379,0.2082,0.3488",\ +"-0.0262,-0.0145,0.0012,0.0285,0.0676,0.1379,0.2785",\ +"-0.1668,-0.1551,-0.1395,-0.1121,-0.0730,0.0012,0.1379"); + } + + fall_constraint("SIG2SRAM_constraint_template") { + index_1("0.0040,0.0176,0.0344,0.0656,0.1120,0.2016,0.3800"); + index_2("0.0040,0.0176,0.0344,0.0656,0.1120,0.2016,0.3800"); + values ("0.2082,0.2199,0.2316,0.2590,0.2980,0.3723,0.5051",\ +"0.1965,0.2082,0.2199,0.2473,0.2863,0.3605,0.4934",\ +"0.1809,0.1926,0.2043,0.2316,0.2707,0.3449,0.4777",\ +"0.1574,0.1691,0.1809,0.2082,0.2434,0.3176,0.4543",\ +"0.1145,0.1262,0.1418,0.1691,0.2043,0.2785,0.4113",\ +"0.0441,0.0559,0.0676,0.0949,0.1301,0.2004,0.3332",\ +"-0.0965,-0.0848,-0.0691,-0.0418,-0.0066,0.0676,0.2004"); + } + } + + + timing() { + timing_type : hold_rising; + related_pin : "A_BIST_CLK"; + + rise_constraint("SIG2SRAM_constraint_template") { + index_1("0.0040,0.0176,0.0344,0.0656,0.1120,0.2016,0.3800"); + index_2("0.0040,0.0176,0.0344,0.0656,0.1120,0.2016,0.3800"); + values ("0.1770,0.1652,0.1535,0.1262,0.0832,0.0129,-0.1277",\ +"0.1887,0.1770,0.1613,0.1340,0.0949,0.0207,-0.1199",\ +"0.2043,0.1926,0.1770,0.1496,0.1105,0.0363,-0.1043",\ +"0.2277,0.2160,0.2043,0.1770,0.1379,0.0598,-0.0770",\ +"0.2668,0.2551,0.2434,0.2160,0.1730,0.0988,-0.0379",\ +"0.3449,0.3332,0.3176,0.2902,0.2473,0.1730,0.0363",\ +"0.4816,0.4699,0.4543,0.4270,0.3840,0.3098,0.1770"); + } + + fall_constraint("SIG2SRAM_constraint_template") { + index_1("0.0040,0.0176,0.0344,0.0656,0.1120,0.2016,0.3800"); + index_2("0.0040,0.0176,0.0344,0.0656,0.1120,0.2016,0.3800"); + values ("0.1613,0.1496,0.1379,0.1105,0.0715,0.0012,-0.1355",\ +"0.1730,0.1613,0.1496,0.1184,0.0832,0.0129,-0.1238",\ +"0.1887,0.1770,0.1652,0.1340,0.0988,0.0285,-0.1121",\ +"0.2121,0.2043,0.1887,0.1613,0.1223,0.0520,-0.0848",\ +"0.2551,0.2434,0.2277,0.2004,0.1613,0.0910,-0.0418",\ +"0.3293,0.3176,0.3020,0.2746,0.2395,0.1652,0.0324",\ +"0.4660,0.4543,0.4426,0.4113,0.3762,0.3020,0.1691"); + } + } + } +bus(A_BIST_BM) { + bus_type : D_15_0; + direction : input ; + capacitance : 0.00353394 ; + max_transition : "0.38" ; + pin(A_BIST_BM[15:0]) { + related_power_pin : VDD; + related_ground_pin : VSS; + internal_power() { + when : "A_BIST_MEN"; + rise_power("scalar"){ + values (0.0783); + } + fall_power("scalar"){ + values (0.0812); + } + } + internal_power() { + when : "!A_BIST_MEN"; + rise_power("scalar"){ + values (0.1034); + } + fall_power("scalar"){ + values (0.0834); + } + } + } + timing() { + timing_type : setup_rising; + related_pin : "A_BIST_CLK"; + when : "(A_BIST_WEN & A_BIST_MEN)" + sdf_cond : "A_BIST_RW_ACCESS" + + rise_constraint("SIG2SRAM_constraint_template") { + index_1("0.0040,0.0176,0.0344,0.0656,0.1120,0.2016,0.3800"); + index_2("0.0040,0.0176,0.0344,0.0656,0.1120,0.2016,0.3800"); + values ("-0.2117,-0.2009,-0.1853,-0.1599,-0.1189,-0.0456,0.0891",\ +"-0.2155,-0.2048,-0.1892,-0.1638,-0.1228,-0.0495,0.0852",\ +"-0.2193,-0.2086,-0.1930,-0.1676,-0.1266,-0.0533,0.0814",\ +"-0.2226,-0.2118,-0.1962,-0.1708,-0.1298,-0.0566,0.0782",\ +"-0.2350,-0.2243,-0.2087,-0.1833,-0.1423,-0.0690,0.0657",\ +"-0.2525,-0.2418,-0.2261,-0.2007,-0.1597,-0.0865,0.0483",\ +"-0.2802,-0.2694,-0.2538,-0.2284,-0.1874,-0.1141,0.0206"); + } + + fall_constraint("SIG2SRAM_constraint_template") { + index_1("0.0040,0.0176,0.0344,0.0656,0.1120,0.2016,0.3800"); + index_2("0.0040,0.0176,0.0344,0.0656,0.1120,0.2016,0.3800"); + values ("-0.1882,-0.1765,-0.1638,-0.1365,-0.0994,-0.0261,0.1018",\ +"-0.1921,-0.1804,-0.1677,-0.1404,-0.1032,-0.0300,0.0979",\ +"-0.1959,-0.1842,-0.1715,-0.1441,-0.1070,-0.0338,0.0941",\ +"-0.1992,-0.1874,-0.1747,-0.1474,-0.1103,-0.0370,0.0909",\ +"-0.2116,-0.1999,-0.1872,-0.1598,-0.1227,-0.0495,0.0784",\ +"-0.2291,-0.2173,-0.2046,-0.1773,-0.1402,-0.0669,0.0610",\ +"-0.2567,-0.2450,-0.2323,-0.2050,-0.1678,-0.0946,0.0333"); + } + } + + + timing() { + timing_type : hold_rising; + related_pin : "A_BIST_CLK"; + when : "(A_BIST_WEN & A_BIST_MEN)" + sdf_cond : "A_BIST_RW_ACCESS" + + rise_constraint("SIG2SRAM_constraint_template") { + index_1("0.0040,0.0176,0.0344,0.0656,0.1120,0.2016,0.3800"); + index_2("0.0040,0.0176,0.0344,0.0656,0.1120,0.2016,0.3800"); + values ("0.3170,0.3073,0.2916,0.2653,0.2282,0.1539,0.0192",\ +"0.3209,0.3111,0.2955,0.2692,0.2320,0.1578,0.0231",\ +"0.3247,0.3149,0.2993,0.2730,0.2358,0.1616,0.0269",\ +"0.3280,0.3182,0.3026,0.2762,0.2391,0.1649,0.0301",\ +"0.3404,0.3306,0.3150,0.2887,0.2515,0.1773,0.0426",\ +"0.3579,0.3481,0.3325,0.3061,0.2690,0.1948,0.0600",\ +"0.3855,0.3758,0.3601,0.3338,0.2967,0.2224,0.0877"); + } + + fall_constraint("SIG2SRAM_constraint_template") { + index_1("0.0040,0.0176,0.0344,0.0656,0.1120,0.2016,0.3800"); + index_2("0.0040,0.0176,0.0344,0.0656,0.1120,0.2016,0.3800"); + values ("0.2887,0.2780,0.2643,0.2370,0.2008,0.1286,-0.0013",\ +"0.2926,0.2818,0.2682,0.2408,0.2047,0.1324,0.0026",\ +"0.2964,0.2856,0.2720,0.2446,0.2085,0.1362,0.0064",\ +"0.2996,0.2889,0.2752,0.2479,0.2118,0.1395,0.0096",\ +"0.3121,0.3013,0.2877,0.2603,0.2242,0.1519,0.0221",\ +"0.3295,0.3188,0.3051,0.2778,0.2417,0.1694,0.0395",\ +"0.3572,0.3465,0.3328,0.3054,0.2693,0.1970,0.0672"); + } + } +} + pin(A_BIST_CLK) { + direction : input; + capacitance : 0.00389386; + max_transition : "0.38"; + clock : "true" ; + pin_func_type : active_rising ; + + timing () { + timing_type : "min_pulse_width"; + related_pin : "A_BIST_CLK"; + rise_constraint("CLKTRAN_constraint_template") { + index_1("0.004,0.38"); + values("0.12,0.12"); + } + } + + related_power_pin : VDD; + related_ground_pin : VSS; + + internal_power() { + when : "!A_BIST_MEN & !A_BIST_WEN & !A_BIST_REN"; + rise_power("scalar"){ + values (0); + } + fall_power("scalar"){ + values (0); + } + } + internal_power() { + when : "!A_BIST_MEN & A_BIST_WEN & !A_BIST_REN"; + rise_power("scalar"){ + values (0.7039); + } + fall_power("scalar"){ + values (0); + } + } + internal_power() { + when : "A_BIST_MEN & A_BIST_WEN & !A_BIST_REN"; + rise_power("scalar"){ + values (40.8199); + } + fall_power("scalar"){ + values (0); + } + } + internal_power() { + when : "A_BIST_MEN & A_BIST_WEN & A_BIST_REN"; + rise_power("scalar"){ + values (41.5232); + } + fall_power("scalar"){ + values (0); + } + } + internal_power() { + when : "A_BIST_MEN & !A_BIST_WEN & A_BIST_REN"; + rise_power("scalar"){ + values (33.7892); + } + fall_power("scalar"){ + values (0); + } + } + internal_power() { + when : "!A_BIST_MEN & !A_BIST_WEN & A_BIST_REN"; + rise_power("scalar"){ + values (0.4120); + } + fall_power("scalar"){ + values (0); + } + } + internal_power() { + when : "!A_BIST_MEN & A_BIST_WEN & A_BIST_REN"; + rise_power("scalar"){ + values (0.9290); + } + fall_power("scalar"){ + values (0); + } + } + internal_power() { + when : "A_BIST_MEN & !A_BIST_WEN & !A_BIST_REN"; + rise_power("scalar"){ + values (0); + } + fall_power("scalar"){ + values (0); + } + } + } + bus(A_BIST_DIN) { + bus_type : D_15_0; + direction : input ; + capacitance : 0.00397186 ; + memory_write() { + address : A_BIST_ADDR ; + clocked_on : A_BIST_CLK; + } + + max_transition : "0.38" ; + pin(A_BIST_DIN[15:0]) { + related_power_pin : VDD; + related_ground_pin : VSS; + internal_power() { + when : "A_BIST_MEN"; + rise_power("scalar"){ + values (0.0783); + } + fall_power("scalar"){ + values (0.0812); + } + } + internal_power() { + when : "!A_BIST_MEN"; + rise_power("scalar"){ + values (0.1034); + } + fall_power("scalar"){ + values (0.0834); + } + } + } + timing() { + timing_type : setup_rising; + related_pin : "A_BIST_CLK"; + when : "(A_BIST_WEN & A_BIST_MEN)"; + sdf_cond : "A_BIST_W_ACCESS"; + + rise_constraint("SIG2SRAM_constraint_template") { + index_1("0.0040,0.0176,0.0344,0.0656,0.1120,0.2016,0.3800"); + index_2("0.0040,0.0176,0.0344,0.0656,0.1120,0.2016,0.3800"); + values ("-0.2117,-0.2009,-0.1853,-0.1599,-0.1189,-0.0456,0.0891",\ +"-0.2155,-0.2048,-0.1892,-0.1638,-0.1228,-0.0495,0.0852",\ +"-0.2193,-0.2086,-0.1930,-0.1676,-0.1266,-0.0533,0.0814",\ +"-0.2226,-0.2118,-0.1962,-0.1708,-0.1298,-0.0566,0.0782",\ +"-0.2350,-0.2243,-0.2087,-0.1833,-0.1423,-0.0690,0.0657",\ +"-0.2525,-0.2418,-0.2261,-0.2007,-0.1597,-0.0865,0.0483",\ +"-0.2802,-0.2694,-0.2538,-0.2284,-0.1874,-0.1141,0.0206"); + } + + fall_constraint("SIG2SRAM_constraint_template") { + index_1("0.0040,0.0176,0.0344,0.0656,0.1120,0.2016,0.3800"); + index_2("0.0040,0.0176,0.0344,0.0656,0.1120,0.2016,0.3800"); + values ("-0.1882,-0.1765,-0.1638,-0.1365,-0.0994,-0.0261,0.1018",\ +"-0.1921,-0.1804,-0.1677,-0.1404,-0.1032,-0.0300,0.0979",\ +"-0.1959,-0.1842,-0.1715,-0.1441,-0.1070,-0.0338,0.0941",\ +"-0.1992,-0.1874,-0.1747,-0.1474,-0.1103,-0.0370,0.0909",\ +"-0.2116,-0.1999,-0.1872,-0.1598,-0.1227,-0.0495,0.0784",\ +"-0.2291,-0.2173,-0.2046,-0.1773,-0.1402,-0.0669,0.0610",\ +"-0.2567,-0.2450,-0.2323,-0.2050,-0.1678,-0.0946,0.0333"); + } + } + + timing() { + timing_type : hold_rising; + related_pin : "A_BIST_CLK"; + when : "(A_BIST_WEN & A_BIST_MEN)"; + sdf_cond : "A_BIST_W_ACCESS"; + + rise_constraint("SIG2SRAM_constraint_template") { + index_1("0.0040,0.0176,0.0344,0.0656,0.1120,0.2016,0.3800"); + index_2("0.0040,0.0176,0.0344,0.0656,0.1120,0.2016,0.3800"); + values ("0.3170,0.3073,0.2916,0.2653,0.2282,0.1539,0.0192",\ +"0.3209,0.3111,0.2955,0.2692,0.2320,0.1578,0.0231",\ +"0.3247,0.3149,0.2993,0.2730,0.2358,0.1616,0.0269",\ +"0.3280,0.3182,0.3026,0.2762,0.2391,0.1649,0.0301",\ +"0.3404,0.3306,0.3150,0.2887,0.2515,0.1773,0.0426",\ +"0.3579,0.3481,0.3325,0.3061,0.2690,0.1948,0.0600",\ +"0.3855,0.3758,0.3601,0.3338,0.2967,0.2224,0.0877"); + } + + fall_constraint("SIG2SRAM_constraint_template") { + index_1("0.0040,0.0176,0.0344,0.0656,0.1120,0.2016,0.3800"); + index_2("0.0040,0.0176,0.0344,0.0656,0.1120,0.2016,0.3800"); + values ("0.2887,0.2780,0.2643,0.2370,0.2008,0.1286,-0.0013",\ +"0.2926,0.2818,0.2682,0.2408,0.2047,0.1324,0.0026",\ +"0.2964,0.2856,0.2720,0.2446,0.2085,0.1362,0.0064",\ +"0.2996,0.2889,0.2752,0.2479,0.2118,0.1395,0.0096",\ +"0.3121,0.3013,0.2877,0.2603,0.2242,0.1519,0.0221",\ +"0.3295,0.3188,0.3051,0.2778,0.2417,0.1694,0.0395",\ +"0.3572,0.3465,0.3328,0.3054,0.2693,0.1970,0.0672"); + } + } + } + +bus(A_DOUT) { + + bus_type : D_15_0; + direction : output ; + capacitance : 0 ; + max_capacitance : 0.064 ; + memory_read() { + address : A_ADDR ; + } + pin(A_DOUT[15:0]) { + related_power_pin : VDD; + related_ground_pin : VSS; + internal_power() { + rise_power("scalar") { + values (0); + } + fall_power("scalar") { + values (0); + } + } + } + timing() { + related_pin : "A_CLK"; + timing_type : rising_edge ; + timing_sense : non_unate ; + + cell_rise(SIG2SRAM_delay_template) { + index_1("0.0040,0.0176,0.0344,0.0656,0.1120,0.2016,0.3800"); + index_2("0.0008,0.0014,0.0051,0.0100,0.0339,0.0640"); + values ("2.6533,2.6543,2.6591,2.6646,2.6856,2.7091",\ +"2.6605,2.6615,2.6663,2.6719,2.6928,2.7163",\ +"2.6620,2.6630,2.6678,2.6733,2.6942,2.7177",\ +"2.6653,2.6663,2.6712,2.6767,2.6976,2.7211",\ +"2.6782,2.6792,2.6840,2.6895,2.7104,2.7339",\ +"2.6959,2.6969,2.7017,2.7073,2.7282,2.7517",\ +"2.7213,2.7223,2.7271,2.7326,2.7536,2.7771"); + } + cell_fall(SIG2SRAM_delay_template) { + index_1("0.0040,0.0176,0.0344,0.0656,0.1120,0.2016,0.3800"); + index_2("0.0008,0.0014,0.0051,0.0100,0.0339,0.0640"); + values ("2.6190,2.6199,2.6239,2.6285,2.6456,2.6623",\ +"2.6262,2.6271,2.6311,2.6357,2.6528,2.6695",\ +"2.6277,2.6286,2.6326,2.6372,2.6542,2.6710",\ +"2.6311,2.6319,2.6359,2.6405,2.6576,2.6743",\ +"2.6439,2.6447,2.6488,2.6533,2.6704,2.6871",\ +"2.6616,2.6625,2.6665,2.6711,2.6882,2.7049",\ +"2.6870,2.6879,2.6919,2.6965,2.7136,2.7303"); + } + + rise_transition(SRAM_load_template) { + index_1("0.0008,0.0014,0.0051,0.0100,0.0339,0.0640"); + values ("0.0206,0.0210,0.0265,0.0323,0.0606,0.0955"); + } + fall_transition(SRAM_load_template) { + index_1("0.0008,0.0014,0.0051,0.0100,0.0339,0.0640"); + values ("0.0170,0.0177,0.0222,0.0270,0.0451,0.0644"); + } + } +} + pin(B_DLY) { + direction : input ; + capacitance : 0.00421562 ; + max_transition : "1" ; + related_power_pin : VDD; + related_ground_pin : VSS; + internal_power() { + rise_power("scalar") { + values (0); + } + fall_power("scalar") { + values (0); + } + } + } + +bus(B_ADDR) { + bus_type : A_9_0; + direction : input ; + capacitance : 0.0115194 ; + pin(B_ADDR[0]) { + capacitance : 0.0056487 ; + } + pin(B_ADDR[1]) { + capacitance : 0.00741688 ; + } + pin(B_ADDR[2]) { + capacitance : 0.0100613 ; + } + pin(B_ADDR[3]) { + capacitance : 0.00667339 ; + } + pin(B_ADDR[4]) { + capacitance : 0.00620204 ; + } + pin(B_ADDR[5]) { + capacitance : 0.0101975 ; + } + pin(B_ADDR[6]) { + capacitance : 0.0124055 ; + } + pin(B_ADDR[7]) { + capacitance : 0.0101065 ; + } + pin(B_ADDR[8]) { + capacitance : 0.00887215 ; + } + max_transition : "0.38" ; + pin(B_ADDR[9:0]) { + related_power_pin : VDD; + related_ground_pin : VSS; + internal_power() { + when : "B_MEN"; + rise_power("scalar"){ + values (0.2111); + } + fall_power("scalar"){ + values (0.2703); + } + } + internal_power() { + when : "!B_MEN"; + rise_power("scalar"){ + values (0.0286); + } + fall_power("scalar"){ + values (0.0026); + } + } + } + timing() { + timing_type : setup_rising; + related_pin : "B_CLK"; + when : "((B_WEN | B_REN)& B_MEN)" + sdf_cond : "B_RW_ACCESS" + + rise_constraint("SIG2SRAM_constraint_template") { + index_1("0.0040,0.0176,0.0344,0.0656,0.1120,0.2016,0.3800"); + index_2("0.0040,0.0176,0.0344,0.0656,0.1120,0.2016,0.3800"); + values ("-0.2371,-0.2215,-0.2098,-0.1824,-0.1434,-0.0691,0.0676",\ +"-0.2449,-0.2332,-0.2176,-0.1902,-0.1551,-0.0770,0.0559",\ +"-0.2605,-0.2488,-0.2332,-0.2059,-0.1707,-0.0965,0.0441",\ +"-0.2879,-0.2723,-0.2605,-0.2332,-0.1941,-0.1199,0.0168",\ +"-0.3230,-0.3113,-0.2996,-0.2723,-0.2332,-0.1590,-0.0184",\ +"-0.4012,-0.3895,-0.3738,-0.3465,-0.3074,-0.2332,-0.0965",\ +"-0.5379,-0.5262,-0.5105,-0.4832,-0.4480,-0.3699,-0.2332"); + } + + fall_constraint("SIG2SRAM_constraint_template") { + index_1("0.0040,0.0176,0.0344,0.0656,0.1120,0.2016,0.3800"); + index_2("0.0040,0.0176,0.0344,0.0656,0.1120,0.2016,0.3800"); + values ("-0.1785,-0.1707,-0.1551,-0.1277,-0.0887,-0.0184,0.1145",\ +"-0.1902,-0.1785,-0.1629,-0.1355,-0.1004,-0.0262,0.1027",\ +"-0.2059,-0.1941,-0.1785,-0.1512,-0.1160,-0.0418,0.0871",\ +"-0.2293,-0.2176,-0.2059,-0.1785,-0.1434,-0.0691,0.0598",\ +"-0.2684,-0.2566,-0.2449,-0.2176,-0.1824,-0.1082,0.0207",\ +"-0.3465,-0.3348,-0.3191,-0.2918,-0.2566,-0.1824,-0.0535",\ +"-0.4832,-0.4715,-0.4559,-0.4324,-0.3934,-0.3191,-0.1902"); + } + } + + + timing() { + timing_type : hold_rising; + related_pin : "B_CLK"; + when : "((B_WEN | B_REN)& B_MEN)" + sdf_cond : "B_RW_ACCESS" + + rise_constraint("SIG2SRAM_constraint_template") { + index_1("0.0040,0.0176,0.0344,0.0656,0.1120,0.2016,0.3800"); + index_2("0.0040,0.0176,0.0344,0.0656,0.1120,0.2016,0.3800"); + values ("0.3410,0.3293,0.3137,0.2863,0.2473,0.1730,0.0324",\ +"0.3488,0.3371,0.3215,0.2941,0.2590,0.1809,0.0480",\ +"0.3684,0.3527,0.3371,0.3098,0.2746,0.1965,0.0598",\ +"0.3918,0.3762,0.3645,0.3371,0.2980,0.2238,0.0871",\ +"0.4309,0.4152,0.4035,0.3762,0.3371,0.2629,0.1223",\ +"0.5051,0.4934,0.4777,0.4504,0.4113,0.3371,0.1965",\ +"0.6418,0.6262,0.6145,0.5871,0.5520,0.4738,0.3332"); + } + + fall_constraint("SIG2SRAM_constraint_template") { + index_1("0.0040,0.0176,0.0344,0.0656,0.1120,0.2016,0.3800"); + index_2("0.0040,0.0176,0.0344,0.0656,0.1120,0.2016,0.3800"); + values ("0.2824,0.2707,0.2551,0.2277,0.1926,0.1184,-0.0105",\ +"0.2902,0.2785,0.2668,0.2395,0.2043,0.1301,0.0012",\ +"0.3059,0.2941,0.2824,0.2551,0.2199,0.1457,0.0168",\ +"0.3332,0.3215,0.3059,0.2785,0.2434,0.1691,0.0402",\ +"0.3723,0.3605,0.3449,0.3176,0.2824,0.2121,0.0793",\ +"0.4465,0.4348,0.4230,0.3918,0.3566,0.2824,0.1535",\ +"0.5832,0.5715,0.5598,0.5324,0.4934,0.4191,0.2902"); + } + } +} +pin(B_WEN) { + direction : input ; + capacitance : 0.00341384 ; + max_transition : "0.38" ; + related_power_pin : VDD; + related_ground_pin : VSS; + internal_power() { + when : "B_MEN"; + rise_power("scalar"){ + values (0.4060); + } + fall_power("scalar"){ + values (0.0178); + } + } + internal_power() { + when : "!B_MEN"; + rise_power("scalar"){ + values (0.0063); + } + fall_power("scalar"){ + values (0.0181); + } + } + timing() { + timing_type : setup_rising; + related_pin : "B_CLK"; + when : "B_MEN" + sdf_cond : "B_MEN" + + rise_constraint("SIG2SRAM_constraint_template") { + index_1("0.0040,0.0176,0.0344,0.0656,0.1120,0.2016,0.3800"); + index_2("0.0040,0.0176,0.0344,0.0656,0.1120,0.2016,0.3800"); + values ("0.1418,0.1496,0.1652,0.1887,0.2316,0.3059,0.4465",\ +"0.1301,0.1379,0.1535,0.1809,0.2199,0.2941,0.4348",\ +"0.1145,0.1262,0.1379,0.1652,0.2043,0.2785,0.4191",\ +"0.0871,0.0949,0.1105,0.1379,0.1770,0.2512,0.3879",\ +"0.0480,0.0598,0.0754,0.0988,0.1379,0.2082,0.3527",\ +"-0.0262,-0.0145,0.0012,0.0246,0.0676,0.1379,0.2785",\ +"-0.1668,-0.1551,-0.1395,-0.1121,-0.0730,0.0012,0.1418"); + } + + fall_constraint("SIG2SRAM_constraint_template") { + index_1("0.0040,0.0176,0.0344,0.0656,0.1120,0.2016,0.3800"); + index_2("0.0040,0.0176,0.0344,0.0656,0.1120,0.2016,0.3800"); + values ("0.2082,0.2160,0.2316,0.2590,0.2941,0.3684,0.5012",\ +"0.1926,0.2043,0.2199,0.2473,0.2824,0.3566,0.4895",\ +"0.1770,0.1887,0.2043,0.2316,0.2668,0.3410,0.4777",\ +"0.1535,0.1652,0.1770,0.2043,0.2395,0.3137,0.4504",\ +"0.1145,0.1262,0.1379,0.1652,0.2043,0.2746,0.4113",\ +"0.0402,0.0520,0.0676,0.0910,0.1262,0.2004,0.3332",\ +"-0.0965,-0.0848,-0.0730,-0.0457,-0.0066,0.0637,0.2004"); + } + } + + + timing() { + timing_type : hold_rising; + related_pin : "B_CLK"; + when : "B_MEN" + sdf_cond : "B_MEN" + + rise_constraint("SIG2SRAM_constraint_template") { + index_1("0.0040,0.0176,0.0344,0.0656,0.1120,0.2016,0.3800"); + index_2("0.0040,0.0176,0.0344,0.0656,0.1120,0.2016,0.3800"); + values ("0.1770,0.1652,0.1496,0.1223,0.0793,0.0090,-0.1316",\ +"0.1848,0.1730,0.1574,0.1301,0.0910,0.0168,-0.1199",\ +"0.2004,0.1887,0.1770,0.1496,0.1066,0.0363,-0.1043",\ +"0.2277,0.2160,0.2004,0.1730,0.1340,0.0598,-0.0809",\ +"0.2668,0.2551,0.2395,0.2121,0.1730,0.0988,-0.0418",\ +"0.3410,0.3293,0.3137,0.2863,0.2434,0.1730,0.0324",\ +"0.4816,0.4699,0.4543,0.4230,0.3801,0.3098,0.1730"); + } + + fall_constraint("SIG2SRAM_constraint_template") { + index_1("0.0040,0.0176,0.0344,0.0656,0.1120,0.2016,0.3800"); + index_2("0.0040,0.0176,0.0344,0.0656,0.1120,0.2016,0.3800"); + values ("0.1613,0.1496,0.1379,0.1066,0.0715,0.0012,-0.1355",\ +"0.1730,0.1613,0.1457,0.1184,0.0832,0.0129,-0.1238",\ +"0.1887,0.1770,0.1613,0.1340,0.0988,0.0246,-0.1121",\ +"0.2121,0.2043,0.1887,0.1613,0.1223,0.0520,-0.0848",\ +"0.2512,0.2434,0.2277,0.2004,0.1613,0.0910,-0.0457",\ +"0.3254,0.3176,0.3020,0.2746,0.2355,0.1652,0.0324",\ +"0.4660,0.4543,0.4387,0.4113,0.3723,0.3020,0.1691"); + } + } + } +pin(B_REN) { + direction : input ; + capacitance : 0.00390661 ; + max_transition : "0.38" ; + related_power_pin : VDD; + related_ground_pin : VSS; + internal_power() { + when : "B_MEN"; + rise_power("scalar"){ + values (0.0125); + } + fall_power("scalar"){ + values (0.0108); + } + } + internal_power() { + when : "!B_MEN"; + rise_power("scalar"){ + values (0.0263); + } + fall_power("scalar"){ + values (0.0211); + } + } + timing() { + timing_type : setup_rising; + related_pin : "B_CLK"; + when : "B_MEN" + sdf_cond : "B_MEN" + + rise_constraint("SIG2SRAM_constraint_template") { + index_1("0.0040,0.0176,0.0344,0.0656,0.1120,0.2016,0.3800"); + index_2("0.0040,0.0176,0.0344,0.0656,0.1120,0.2016,0.3800"); + values ("-0.0027,0.0090,0.0246,0.0520,0.0910,0.1613,0.3020",\ +"-0.0105,0.0012,0.0129,0.0363,0.0793,0.1535,0.2902",\ +"-0.0262,-0.0145,-0.0027,0.0246,0.0637,0.1379,0.2785",\ +"-0.0535,-0.0418,-0.0262,0.0012,0.0363,0.1105,0.2512",\ +"-0.0926,-0.0809,-0.0652,-0.0418,-0.0027,0.0715,0.2121",\ +"-0.1668,-0.1551,-0.1395,-0.1082,-0.0770,-0.0027,0.1379",\ +"-0.3035,-0.2918,-0.2762,-0.2488,-0.2137,-0.1434,-0.0027"); + } + + fall_constraint("SIG2SRAM_constraint_template") { + index_1("0.0040,0.0176,0.0344,0.0656,0.1120,0.2016,0.3800"); + index_2("0.0040,0.0176,0.0344,0.0656,0.1120,0.2016,0.3800"); + values ("0.0832,0.0949,0.1105,0.1379,0.1730,0.2473,0.3801",\ +"0.0754,0.0832,0.0988,0.1223,0.1613,0.2355,0.3684",\ +"0.0598,0.0676,0.0832,0.1066,0.1457,0.2121,0.3527",\ +"0.0324,0.0441,0.0598,0.0871,0.1223,0.1926,0.3293",\ +"-0.0066,0.0051,0.0168,0.0480,0.0832,0.1535,0.2902",\ +"-0.0809,-0.0691,-0.0574,-0.0301,0.0090,0.0832,0.2121",\ +"-0.2176,-0.2059,-0.1941,-0.1668,-0.1277,-0.0574,0.0793"); + } + } + + + timing() { + timing_type : hold_rising; + related_pin : "B_CLK"; + when : "B_MEN" + sdf_cond : "B_MEN" + + rise_constraint("SIG2SRAM_constraint_template") { + index_1("0.0040,0.0176,0.0344,0.0656,0.1120,0.2016,0.3800"); + index_2("0.0040,0.0176,0.0344,0.0656,0.1120,0.2016,0.3800"); + values ("0.1887,0.1770,0.1613,0.1340,0.0949,0.0207,-0.1160",\ +"0.1965,0.1848,0.1730,0.1457,0.1027,0.0324,-0.1082",\ +"0.2160,0.2004,0.1887,0.1613,0.1184,0.0480,-0.0926",\ +"0.2395,0.2277,0.2121,0.1848,0.1457,0.0715,-0.0652",\ +"0.2785,0.2668,0.2512,0.2238,0.1848,0.1105,-0.0262",\ +"0.3527,0.3410,0.3254,0.2980,0.2551,0.1848,0.0480",\ +"0.4934,0.4816,0.4660,0.4387,0.3957,0.3254,0.1887"); + } + + fall_constraint("SIG2SRAM_constraint_template") { + index_1("0.0040,0.0176,0.0344,0.0656,0.1120,0.2016,0.3800"); + index_2("0.0040,0.0176,0.0344,0.0656,0.1120,0.2016,0.3800"); + values ("0.1730,0.1613,0.1496,0.1184,0.0793,0.0129,-0.1238",\ +"0.1848,0.1730,0.1574,0.1301,0.0910,0.0207,-0.1121",\ +"0.2004,0.1887,0.1730,0.1457,0.1066,0.0363,-0.1004",\ +"0.2238,0.2121,0.2004,0.1691,0.1340,0.0598,-0.0730",\ +"0.2629,0.2512,0.2395,0.2121,0.1691,0.0988,-0.0340",\ +"0.3371,0.3254,0.3137,0.2863,0.2434,0.1730,0.0402",\ +"0.4777,0.4660,0.4504,0.4230,0.3840,0.3137,0.1809"); + } + } + } +pin(B_MEN) { + direction : input ; + capacitance : 0.00326046 ; + max_transition : "0.38" ; + related_power_pin : VDD; + related_ground_pin : VSS; + internal_power() { + rise_power("scalar"){ + values (0.1484); + } + fall_power("scalar"){ + values (0.2101); + } + } + timing() { + timing_type : setup_rising; + related_pin : "B_CLK"; + + rise_constraint("SIG2SRAM_constraint_template") { + index_1("0.0040,0.0176,0.0344,0.0656,0.1120,0.2016,0.3800"); + index_2("0.0040,0.0176,0.0344,0.0656,0.1120,0.2016,0.3800"); + values ("0.1418,0.1496,0.1652,0.1926,0.2316,0.3059,0.4465",\ +"0.1301,0.1379,0.1535,0.1809,0.2199,0.2941,0.4348",\ +"0.1145,0.1262,0.1418,0.1652,0.2043,0.2785,0.4191",\ +"0.0871,0.0949,0.1105,0.1379,0.1770,0.2512,0.3879",\ +"0.0480,0.0598,0.0754,0.0988,0.1379,0.2082,0.3488",\ +"-0.0262,-0.0145,0.0012,0.0285,0.0676,0.1379,0.2785",\ +"-0.1668,-0.1551,-0.1395,-0.1121,-0.0730,0.0012,0.1379"); + } + + fall_constraint("SIG2SRAM_constraint_template") { + index_1("0.0040,0.0176,0.0344,0.0656,0.1120,0.2016,0.3800"); + index_2("0.0040,0.0176,0.0344,0.0656,0.1120,0.2016,0.3800"); + values ("0.2082,0.2199,0.2316,0.2590,0.2980,0.3723,0.5051",\ +"0.1965,0.2082,0.2199,0.2473,0.2863,0.3605,0.4934",\ +"0.1809,0.1926,0.2043,0.2316,0.2707,0.3449,0.4777",\ +"0.1574,0.1691,0.1809,0.2082,0.2434,0.3176,0.4543",\ +"0.1145,0.1262,0.1418,0.1691,0.2043,0.2785,0.4113",\ +"0.0441,0.0559,0.0676,0.0949,0.1301,0.2004,0.3332",\ +"-0.0965,-0.0848,-0.0691,-0.0418,-0.0066,0.0676,0.2004"); + } + } + + + timing() { + timing_type : hold_rising; + related_pin : "B_CLK"; + + rise_constraint("SIG2SRAM_constraint_template") { + index_1("0.0040,0.0176,0.0344,0.0656,0.1120,0.2016,0.3800"); + index_2("0.0040,0.0176,0.0344,0.0656,0.1120,0.2016,0.3800"); + values ("0.1770,0.1652,0.1535,0.1262,0.0832,0.0129,-0.1277",\ +"0.1887,0.1770,0.1613,0.1340,0.0949,0.0207,-0.1199",\ +"0.2043,0.1926,0.1770,0.1496,0.1105,0.0363,-0.1043",\ +"0.2277,0.2160,0.2043,0.1770,0.1379,0.0598,-0.0770",\ +"0.2668,0.2551,0.2434,0.2160,0.1730,0.0988,-0.0379",\ +"0.3449,0.3332,0.3176,0.2902,0.2473,0.1730,0.0363",\ +"0.4816,0.4699,0.4543,0.4270,0.3840,0.3098,0.1770"); + } + + fall_constraint("SIG2SRAM_constraint_template") { + index_1("0.0040,0.0176,0.0344,0.0656,0.1120,0.2016,0.3800"); + index_2("0.0040,0.0176,0.0344,0.0656,0.1120,0.2016,0.3800"); + values ("0.1613,0.1496,0.1379,0.1105,0.0715,0.0012,-0.1355",\ +"0.1730,0.1613,0.1496,0.1184,0.0832,0.0129,-0.1238",\ +"0.1887,0.1770,0.1652,0.1340,0.0988,0.0285,-0.1121",\ +"0.2121,0.2043,0.1887,0.1613,0.1223,0.0520,-0.0848",\ +"0.2551,0.2434,0.2277,0.2004,0.1613,0.0910,-0.0418",\ +"0.3293,0.3176,0.3020,0.2746,0.2395,0.1652,0.0324",\ +"0.4660,0.4543,0.4426,0.4113,0.3762,0.3020,0.1691"); + } + } + } +bus(B_BM) { + bus_type : D_15_0; + direction : input ; + capacitance : 0.00334781 ; + max_transition : "0.38" ; + pin(B_BM[15:0]) { + related_power_pin : VDD; + related_ground_pin : VSS; + internal_power() { + when : "B_MEN"; + rise_power("scalar"){ + values (0.0783); + } + fall_power("scalar"){ + values (0.0812); + } + } + internal_power() { + when : "!B_MEN"; + rise_power("scalar"){ + values (0.1034); + } + fall_power("scalar"){ + values (0.0834); + } + } + } + timing() { + timing_type : setup_rising; + related_pin : "B_CLK"; + when : "(B_WEN & B_MEN)" + sdf_cond : "B_RW_ACCESS" + + rise_constraint("SIG2SRAM_constraint_template") { + index_1("0.0040,0.0176,0.0344,0.0656,0.1120,0.2016,0.3800"); + index_2("0.0040,0.0176,0.0344,0.0656,0.1120,0.2016,0.3800"); + values ("-0.2117,-0.2009,-0.1853,-0.1599,-0.1189,-0.0456,0.0891",\ +"-0.2155,-0.2048,-0.1892,-0.1638,-0.1228,-0.0495,0.0852",\ +"-0.2193,-0.2086,-0.1930,-0.1676,-0.1266,-0.0533,0.0814",\ +"-0.2226,-0.2118,-0.1962,-0.1708,-0.1298,-0.0566,0.0782",\ +"-0.2350,-0.2243,-0.2087,-0.1833,-0.1423,-0.0690,0.0657",\ +"-0.2525,-0.2418,-0.2261,-0.2007,-0.1597,-0.0865,0.0483",\ +"-0.2802,-0.2694,-0.2538,-0.2284,-0.1874,-0.1141,0.0206"); + } + + fall_constraint("SIG2SRAM_constraint_template") { + index_1("0.0040,0.0176,0.0344,0.0656,0.1120,0.2016,0.3800"); + index_2("0.0040,0.0176,0.0344,0.0656,0.1120,0.2016,0.3800"); + values ("-0.1882,-0.1765,-0.1638,-0.1365,-0.0994,-0.0261,0.1018",\ +"-0.1921,-0.1804,-0.1677,-0.1404,-0.1032,-0.0300,0.0979",\ +"-0.1959,-0.1842,-0.1715,-0.1441,-0.1070,-0.0338,0.0941",\ +"-0.1992,-0.1874,-0.1747,-0.1474,-0.1103,-0.0370,0.0909",\ +"-0.2116,-0.1999,-0.1872,-0.1598,-0.1227,-0.0495,0.0784",\ +"-0.2291,-0.2173,-0.2046,-0.1773,-0.1402,-0.0669,0.0610",\ +"-0.2567,-0.2450,-0.2323,-0.2050,-0.1678,-0.0946,0.0333"); + } + } + + + timing() { + timing_type : hold_rising; + related_pin : "B_CLK"; + when : "(B_WEN & B_MEN)" + sdf_cond : "B_RW_ACCESS" + + rise_constraint("SIG2SRAM_constraint_template") { + index_1("0.0040,0.0176,0.0344,0.0656,0.1120,0.2016,0.3800"); + index_2("0.0040,0.0176,0.0344,0.0656,0.1120,0.2016,0.3800"); + values ("0.3170,0.3073,0.2916,0.2653,0.2282,0.1539,0.0192",\ +"0.3209,0.3111,0.2955,0.2692,0.2320,0.1578,0.0231",\ +"0.3247,0.3149,0.2993,0.2730,0.2358,0.1616,0.0269",\ +"0.3280,0.3182,0.3026,0.2762,0.2391,0.1649,0.0301",\ +"0.3404,0.3306,0.3150,0.2887,0.2515,0.1773,0.0426",\ +"0.3579,0.3481,0.3325,0.3061,0.2690,0.1948,0.0600",\ +"0.3855,0.3758,0.3601,0.3338,0.2967,0.2224,0.0877"); + } + + fall_constraint("SIG2SRAM_constraint_template") { + index_1("0.0040,0.0176,0.0344,0.0656,0.1120,0.2016,0.3800"); + index_2("0.0040,0.0176,0.0344,0.0656,0.1120,0.2016,0.3800"); + values ("0.2887,0.2780,0.2643,0.2370,0.2008,0.1286,-0.0013",\ +"0.2926,0.2818,0.2682,0.2408,0.2047,0.1324,0.0026",\ +"0.2964,0.2856,0.2720,0.2446,0.2085,0.1362,0.0064",\ +"0.2996,0.2889,0.2752,0.2479,0.2118,0.1395,0.0096",\ +"0.3121,0.3013,0.2877,0.2603,0.2242,0.1519,0.0221",\ +"0.3295,0.3188,0.3051,0.2778,0.2417,0.1694,0.0395",\ +"0.3572,0.3465,0.3328,0.3054,0.2693,0.1970,0.0672"); + } + } +} + pin(B_CLK) { + direction : input; + capacitance : 0.00389386; + max_transition : "0.38"; + clock : "true" ; + pin_func_type : active_rising ; + + timing () { + timing_type : "min_pulse_width"; + related_pin : "B_CLK"; + rise_constraint("CLKTRAN_constraint_template") { + index_1("0.004,0.38"); + values("0.12,0.12"); + } + } + + related_power_pin : VDD; + related_ground_pin : VSS; + + internal_power() { + when : "!B_MEN & !B_WEN & !B_REN"; + rise_power("scalar"){ + values (0); + } + fall_power("scalar"){ + values (0); + } + } + internal_power() { + when : "!B_MEN & B_WEN & !B_REN"; + rise_power("scalar"){ + values (0.7039); + } + fall_power("scalar"){ + values (0); + } + } + internal_power() { + when : "B_MEN & B_WEN & !B_REN"; + rise_power("scalar"){ + values (40.8199); + } + fall_power("scalar"){ + values (0); + } + } + internal_power() { + when : "B_MEN & B_WEN & B_REN"; + rise_power("scalar"){ + values (41.5232); + } + fall_power("scalar"){ + values (0); + } + } + internal_power() { + when : "B_MEN & !B_WEN & B_REN"; + rise_power("scalar"){ + values (33.7892); + } + fall_power("scalar"){ + values (0); + } + } + internal_power() { + when : "!B_MEN & !B_WEN & B_REN"; + rise_power("scalar"){ + values (0.4120); + } + fall_power("scalar"){ + values (0); + } + } + internal_power() { + when : "!B_MEN & B_WEN & B_REN"; + rise_power("scalar"){ + values (0.9290); + } + fall_power("scalar"){ + values (0); + } + } + internal_power() { + when : "B_MEN & !B_WEN & !B_REN"; + rise_power("scalar"){ + values (0); + } + fall_power("scalar"){ + values (0); + } + } + } + bus(B_DIN) { + bus_type : D_15_0; + direction : input ; + capacitance : 0.00468868 ; + memory_write() { + address : B_ADDR ; + clocked_on : B_CLK; + } + + max_transition : "0.38" ; + pin(B_DIN[15:0]) { + related_power_pin : VDD; + related_ground_pin : VSS; + internal_power() { + when : "B_MEN"; + rise_power("scalar"){ + values (0.0783); + } + fall_power("scalar"){ + values (0.0812); + } + } + internal_power() { + when : "!B_MEN"; + rise_power("scalar"){ + values (0.1034); + } + fall_power("scalar"){ + values (0.0834); + } + } + } + timing() { + timing_type : setup_rising; + related_pin : "B_CLK"; + when : "(B_WEN & B_MEN)"; + sdf_cond : "B_W_ACCESS"; + + rise_constraint("SIG2SRAM_constraint_template") { + index_1("0.0040,0.0176,0.0344,0.0656,0.1120,0.2016,0.3800"); + index_2("0.0040,0.0176,0.0344,0.0656,0.1120,0.2016,0.3800"); + values ("-0.2117,-0.2009,-0.1853,-0.1599,-0.1189,-0.0456,0.0891",\ +"-0.2155,-0.2048,-0.1892,-0.1638,-0.1228,-0.0495,0.0852",\ +"-0.2193,-0.2086,-0.1930,-0.1676,-0.1266,-0.0533,0.0814",\ +"-0.2226,-0.2118,-0.1962,-0.1708,-0.1298,-0.0566,0.0782",\ +"-0.2350,-0.2243,-0.2087,-0.1833,-0.1423,-0.0690,0.0657",\ +"-0.2525,-0.2418,-0.2261,-0.2007,-0.1597,-0.0865,0.0483",\ +"-0.2802,-0.2694,-0.2538,-0.2284,-0.1874,-0.1141,0.0206"); + } + + fall_constraint("SIG2SRAM_constraint_template") { + index_1("0.0040,0.0176,0.0344,0.0656,0.1120,0.2016,0.3800"); + index_2("0.0040,0.0176,0.0344,0.0656,0.1120,0.2016,0.3800"); + values ("-0.1882,-0.1765,-0.1638,-0.1365,-0.0994,-0.0261,0.1018",\ +"-0.1921,-0.1804,-0.1677,-0.1404,-0.1032,-0.0300,0.0979",\ +"-0.1959,-0.1842,-0.1715,-0.1441,-0.1070,-0.0338,0.0941",\ +"-0.1992,-0.1874,-0.1747,-0.1474,-0.1103,-0.0370,0.0909",\ +"-0.2116,-0.1999,-0.1872,-0.1598,-0.1227,-0.0495,0.0784",\ +"-0.2291,-0.2173,-0.2046,-0.1773,-0.1402,-0.0669,0.0610",\ +"-0.2567,-0.2450,-0.2323,-0.2050,-0.1678,-0.0946,0.0333"); + } + } + + timing() { + timing_type : hold_rising; + related_pin : "B_CLK"; + when : "(B_WEN & B_MEN)"; + sdf_cond : "B_W_ACCESS"; + + rise_constraint("SIG2SRAM_constraint_template") { + index_1("0.0040,0.0176,0.0344,0.0656,0.1120,0.2016,0.3800"); + index_2("0.0040,0.0176,0.0344,0.0656,0.1120,0.2016,0.3800"); + values ("0.3170,0.3073,0.2916,0.2653,0.2282,0.1539,0.0192",\ +"0.3209,0.3111,0.2955,0.2692,0.2320,0.1578,0.0231",\ +"0.3247,0.3149,0.2993,0.2730,0.2358,0.1616,0.0269",\ +"0.3280,0.3182,0.3026,0.2762,0.2391,0.1649,0.0301",\ +"0.3404,0.3306,0.3150,0.2887,0.2515,0.1773,0.0426",\ +"0.3579,0.3481,0.3325,0.3061,0.2690,0.1948,0.0600",\ +"0.3855,0.3758,0.3601,0.3338,0.2967,0.2224,0.0877"); + } + + fall_constraint("SIG2SRAM_constraint_template") { + index_1("0.0040,0.0176,0.0344,0.0656,0.1120,0.2016,0.3800"); + index_2("0.0040,0.0176,0.0344,0.0656,0.1120,0.2016,0.3800"); + values ("0.2887,0.2780,0.2643,0.2370,0.2008,0.1286,-0.0013",\ +"0.2926,0.2818,0.2682,0.2408,0.2047,0.1324,0.0026",\ +"0.2964,0.2856,0.2720,0.2446,0.2085,0.1362,0.0064",\ +"0.2996,0.2889,0.2752,0.2479,0.2118,0.1395,0.0096",\ +"0.3121,0.3013,0.2877,0.2603,0.2242,0.1519,0.0221",\ +"0.3295,0.3188,0.3051,0.2778,0.2417,0.1694,0.0395",\ +"0.3572,0.3465,0.3328,0.3054,0.2693,0.1970,0.0672"); + } + } + } + + pin(B_BIST_EN) { + direction : input ; + capacitance : 0.00421562 ; + max_transition : "1" ; + related_power_pin : VDD; + related_ground_pin : VSS; + internal_power() { + rise_power("scalar") { + values (0); + } + fall_power("scalar") { + values (0); + } + } + } + +bus(B_BIST_ADDR) { + bus_type : A_9_0; + direction : input ; + capacitance : 0.0115194 ; + pin(B_BIST_ADDR[0]) { + capacitance : 0.0056487 ; + } + pin(B_BIST_ADDR[1]) { + capacitance : 0.00741688 ; + } + pin(B_BIST_ADDR[2]) { + capacitance : 0.0100613 ; + } + pin(B_BIST_ADDR[3]) { + capacitance : 0.00667339 ; + } + pin(B_BIST_ADDR[4]) { + capacitance : 0.00620204 ; + } + pin(B_BIST_ADDR[5]) { + capacitance : 0.0101975 ; + } + pin(B_BIST_ADDR[6]) { + capacitance : 0.0124055 ; + } + pin(B_BIST_ADDR[7]) { + capacitance : 0.0101065 ; + } + pin(B_BIST_ADDR[8]) { + capacitance : 0.00887215 ; + } + max_transition : "0.38" ; + pin(B_BIST_ADDR[9:0]) { + related_power_pin : VDD; + related_ground_pin : VSS; + internal_power() { + when : "B_BIST_MEN"; + rise_power("scalar"){ + values (0.2111); + } + fall_power("scalar"){ + values (0.2703); + } + } + internal_power() { + when : "!B_BIST_MEN"; + rise_power("scalar"){ + values (0.0286); + } + fall_power("scalar"){ + values (0.0026); + } + } + } + timing() { + timing_type : setup_rising; + related_pin : "B_BIST_CLK"; + when : "((B_BIST_WEN | B_BIST_REN)& B_BIST_MEN)" + sdf_cond : "B_BIST_RW_ACCESS" + + rise_constraint("SIG2SRAM_constraint_template") { + index_1("0.0040,0.0176,0.0344,0.0656,0.1120,0.2016,0.3800"); + index_2("0.0040,0.0176,0.0344,0.0656,0.1120,0.2016,0.3800"); + values ("-0.2371,-0.2215,-0.2098,-0.1824,-0.1434,-0.0691,0.0676",\ +"-0.2449,-0.2332,-0.2176,-0.1902,-0.1551,-0.0770,0.0559",\ +"-0.2605,-0.2488,-0.2332,-0.2059,-0.1707,-0.0965,0.0441",\ +"-0.2879,-0.2723,-0.2605,-0.2332,-0.1941,-0.1199,0.0168",\ +"-0.3230,-0.3113,-0.2996,-0.2723,-0.2332,-0.1590,-0.0184",\ +"-0.4012,-0.3895,-0.3738,-0.3465,-0.3074,-0.2332,-0.0965",\ +"-0.5379,-0.5262,-0.5105,-0.4832,-0.4480,-0.3699,-0.2332"); + } + + fall_constraint("SIG2SRAM_constraint_template") { + index_1("0.0040,0.0176,0.0344,0.0656,0.1120,0.2016,0.3800"); + index_2("0.0040,0.0176,0.0344,0.0656,0.1120,0.2016,0.3800"); + values ("-0.1785,-0.1707,-0.1551,-0.1277,-0.0887,-0.0184,0.1145",\ +"-0.1902,-0.1785,-0.1629,-0.1355,-0.1004,-0.0262,0.1027",\ +"-0.2059,-0.1941,-0.1785,-0.1512,-0.1160,-0.0418,0.0871",\ +"-0.2293,-0.2176,-0.2059,-0.1785,-0.1434,-0.0691,0.0598",\ +"-0.2684,-0.2566,-0.2449,-0.2176,-0.1824,-0.1082,0.0207",\ +"-0.3465,-0.3348,-0.3191,-0.2918,-0.2566,-0.1824,-0.0535",\ +"-0.4832,-0.4715,-0.4559,-0.4324,-0.3934,-0.3191,-0.1902"); + } + } + + + timing() { + timing_type : hold_rising; + related_pin : "B_BIST_CLK"; + when : "((B_BIST_WEN | B_BIST_REN)& B_BIST_MEN)" + sdf_cond : "B_BIST_RW_ACCESS" + + rise_constraint("SIG2SRAM_constraint_template") { + index_1("0.0040,0.0176,0.0344,0.0656,0.1120,0.2016,0.3800"); + index_2("0.0040,0.0176,0.0344,0.0656,0.1120,0.2016,0.3800"); + values ("0.3410,0.3293,0.3137,0.2863,0.2473,0.1730,0.0324",\ +"0.3488,0.3371,0.3215,0.2941,0.2590,0.1809,0.0480",\ +"0.3684,0.3527,0.3371,0.3098,0.2746,0.1965,0.0598",\ +"0.3918,0.3762,0.3645,0.3371,0.2980,0.2238,0.0871",\ +"0.4309,0.4152,0.4035,0.3762,0.3371,0.2629,0.1223",\ +"0.5051,0.4934,0.4777,0.4504,0.4113,0.3371,0.1965",\ +"0.6418,0.6262,0.6145,0.5871,0.5520,0.4738,0.3332"); + } + + fall_constraint("SIG2SRAM_constraint_template") { + index_1("0.0040,0.0176,0.0344,0.0656,0.1120,0.2016,0.3800"); + index_2("0.0040,0.0176,0.0344,0.0656,0.1120,0.2016,0.3800"); + values ("0.2824,0.2707,0.2551,0.2277,0.1926,0.1184,-0.0105",\ +"0.2902,0.2785,0.2668,0.2395,0.2043,0.1301,0.0012",\ +"0.3059,0.2941,0.2824,0.2551,0.2199,0.1457,0.0168",\ +"0.3332,0.3215,0.3059,0.2785,0.2434,0.1691,0.0402",\ +"0.3723,0.3605,0.3449,0.3176,0.2824,0.2121,0.0793",\ +"0.4465,0.4348,0.4230,0.3918,0.3566,0.2824,0.1535",\ +"0.5832,0.5715,0.5598,0.5324,0.4934,0.4191,0.2902"); + } + } +} +pin(B_BIST_WEN) { + direction : input ; + capacitance : 0.00341384 ; + max_transition : "0.38" ; + related_power_pin : VDD; + related_ground_pin : VSS; + internal_power() { + when : "B_BIST_MEN"; + rise_power("scalar"){ + values (0.4060); + } + fall_power("scalar"){ + values (0.0178); + } + } + internal_power() { + when : "!B_BIST_MEN"; + rise_power("scalar"){ + values (0.0063); + } + fall_power("scalar"){ + values (0.0181); + } + } + timing() { + timing_type : setup_rising; + related_pin : "B_BIST_CLK"; + when : "B_BIST_MEN" + sdf_cond : "B_BIST_MEN" + + rise_constraint("SIG2SRAM_constraint_template") { + index_1("0.0040,0.0176,0.0344,0.0656,0.1120,0.2016,0.3800"); + index_2("0.0040,0.0176,0.0344,0.0656,0.1120,0.2016,0.3800"); + values ("0.1418,0.1496,0.1652,0.1887,0.2316,0.3059,0.4465",\ +"0.1301,0.1379,0.1535,0.1809,0.2199,0.2941,0.4348",\ +"0.1145,0.1262,0.1379,0.1652,0.2043,0.2785,0.4191",\ +"0.0871,0.0949,0.1105,0.1379,0.1770,0.2512,0.3879",\ +"0.0480,0.0598,0.0754,0.0988,0.1379,0.2082,0.3527",\ +"-0.0262,-0.0145,0.0012,0.0246,0.0676,0.1379,0.2785",\ +"-0.1668,-0.1551,-0.1395,-0.1121,-0.0730,0.0012,0.1418"); + } + + fall_constraint("SIG2SRAM_constraint_template") { + index_1("0.0040,0.0176,0.0344,0.0656,0.1120,0.2016,0.3800"); + index_2("0.0040,0.0176,0.0344,0.0656,0.1120,0.2016,0.3800"); + values ("0.2082,0.2160,0.2316,0.2590,0.2941,0.3684,0.5012",\ +"0.1926,0.2043,0.2199,0.2473,0.2824,0.3566,0.4895",\ +"0.1770,0.1887,0.2043,0.2316,0.2668,0.3410,0.4777",\ +"0.1535,0.1652,0.1770,0.2043,0.2395,0.3137,0.4504",\ +"0.1145,0.1262,0.1379,0.1652,0.2043,0.2746,0.4113",\ +"0.0402,0.0520,0.0676,0.0910,0.1262,0.2004,0.3332",\ +"-0.0965,-0.0848,-0.0730,-0.0457,-0.0066,0.0637,0.2004"); + } + } + + + timing() { + timing_type : hold_rising; + related_pin : "B_BIST_CLK"; + when : "B_BIST_MEN" + sdf_cond : "B_BIST_MEN" + + rise_constraint("SIG2SRAM_constraint_template") { + index_1("0.0040,0.0176,0.0344,0.0656,0.1120,0.2016,0.3800"); + index_2("0.0040,0.0176,0.0344,0.0656,0.1120,0.2016,0.3800"); + values ("0.1770,0.1652,0.1496,0.1223,0.0793,0.0090,-0.1316",\ +"0.1848,0.1730,0.1574,0.1301,0.0910,0.0168,-0.1199",\ +"0.2004,0.1887,0.1770,0.1496,0.1066,0.0363,-0.1043",\ +"0.2277,0.2160,0.2004,0.1730,0.1340,0.0598,-0.0809",\ +"0.2668,0.2551,0.2395,0.2121,0.1730,0.0988,-0.0418",\ +"0.3410,0.3293,0.3137,0.2863,0.2434,0.1730,0.0324",\ +"0.4816,0.4699,0.4543,0.4230,0.3801,0.3098,0.1730"); + } + + fall_constraint("SIG2SRAM_constraint_template") { + index_1("0.0040,0.0176,0.0344,0.0656,0.1120,0.2016,0.3800"); + index_2("0.0040,0.0176,0.0344,0.0656,0.1120,0.2016,0.3800"); + values ("0.1613,0.1496,0.1379,0.1066,0.0715,0.0012,-0.1355",\ +"0.1730,0.1613,0.1457,0.1184,0.0832,0.0129,-0.1238",\ +"0.1887,0.1770,0.1613,0.1340,0.0988,0.0246,-0.1121",\ +"0.2121,0.2043,0.1887,0.1613,0.1223,0.0520,-0.0848",\ +"0.2512,0.2434,0.2277,0.2004,0.1613,0.0910,-0.0457",\ +"0.3254,0.3176,0.3020,0.2746,0.2355,0.1652,0.0324",\ +"0.4660,0.4543,0.4387,0.4113,0.3723,0.3020,0.1691"); + } + } + } +pin(B_BIST_REN) { + direction : input ; + capacitance : 0.00390661 ; + max_transition : "0.38" ; + related_power_pin : VDD; + related_ground_pin : VSS; + internal_power() { + when : "B_BIST_MEN"; + rise_power("scalar"){ + values (0.0125); + } + fall_power("scalar"){ + values (0.0108); + } + } + internal_power() { + when : "!B_BIST_MEN"; + rise_power("scalar"){ + values (0.0263); + } + fall_power("scalar"){ + values (0.0211); + } + } + timing() { + timing_type : setup_rising; + related_pin : "B_BIST_CLK"; + when : "B_BIST_MEN" + sdf_cond : "B_BIST_MEN" + + rise_constraint("SIG2SRAM_constraint_template") { + index_1("0.0040,0.0176,0.0344,0.0656,0.1120,0.2016,0.3800"); + index_2("0.0040,0.0176,0.0344,0.0656,0.1120,0.2016,0.3800"); + values ("-0.0027,0.0090,0.0246,0.0520,0.0910,0.1613,0.3020",\ +"-0.0105,0.0012,0.0129,0.0363,0.0793,0.1535,0.2902",\ +"-0.0262,-0.0145,-0.0027,0.0246,0.0637,0.1379,0.2785",\ +"-0.0535,-0.0418,-0.0262,0.0012,0.0363,0.1105,0.2512",\ +"-0.0926,-0.0809,-0.0652,-0.0418,-0.0027,0.0715,0.2121",\ +"-0.1668,-0.1551,-0.1395,-0.1082,-0.0770,-0.0027,0.1379",\ +"-0.3035,-0.2918,-0.2762,-0.2488,-0.2137,-0.1434,-0.0027"); + } + + fall_constraint("SIG2SRAM_constraint_template") { + index_1("0.0040,0.0176,0.0344,0.0656,0.1120,0.2016,0.3800"); + index_2("0.0040,0.0176,0.0344,0.0656,0.1120,0.2016,0.3800"); + values ("0.0832,0.0949,0.1105,0.1379,0.1730,0.2473,0.3801",\ +"0.0754,0.0832,0.0988,0.1223,0.1613,0.2355,0.3684",\ +"0.0598,0.0676,0.0832,0.1066,0.1457,0.2121,0.3527",\ +"0.0324,0.0441,0.0598,0.0871,0.1223,0.1926,0.3293",\ +"-0.0066,0.0051,0.0168,0.0480,0.0832,0.1535,0.2902",\ +"-0.0809,-0.0691,-0.0574,-0.0301,0.0090,0.0832,0.2121",\ +"-0.2176,-0.2059,-0.1941,-0.1668,-0.1277,-0.0574,0.0793"); + } + } + + + timing() { + timing_type : hold_rising; + related_pin : "B_BIST_CLK"; + when : "B_BIST_MEN" + sdf_cond : "B_BIST_MEN" + + rise_constraint("SIG2SRAM_constraint_template") { + index_1("0.0040,0.0176,0.0344,0.0656,0.1120,0.2016,0.3800"); + index_2("0.0040,0.0176,0.0344,0.0656,0.1120,0.2016,0.3800"); + values ("0.1887,0.1770,0.1613,0.1340,0.0949,0.0207,-0.1160",\ +"0.1965,0.1848,0.1730,0.1457,0.1027,0.0324,-0.1082",\ +"0.2160,0.2004,0.1887,0.1613,0.1184,0.0480,-0.0926",\ +"0.2395,0.2277,0.2121,0.1848,0.1457,0.0715,-0.0652",\ +"0.2785,0.2668,0.2512,0.2238,0.1848,0.1105,-0.0262",\ +"0.3527,0.3410,0.3254,0.2980,0.2551,0.1848,0.0480",\ +"0.4934,0.4816,0.4660,0.4387,0.3957,0.3254,0.1887"); + } + + fall_constraint("SIG2SRAM_constraint_template") { + index_1("0.0040,0.0176,0.0344,0.0656,0.1120,0.2016,0.3800"); + index_2("0.0040,0.0176,0.0344,0.0656,0.1120,0.2016,0.3800"); + values ("0.1730,0.1613,0.1496,0.1184,0.0793,0.0129,-0.1238",\ +"0.1848,0.1730,0.1574,0.1301,0.0910,0.0207,-0.1121",\ +"0.2004,0.1887,0.1730,0.1457,0.1066,0.0363,-0.1004",\ +"0.2238,0.2121,0.2004,0.1691,0.1340,0.0598,-0.0730",\ +"0.2629,0.2512,0.2395,0.2121,0.1691,0.0988,-0.0340",\ +"0.3371,0.3254,0.3137,0.2863,0.2434,0.1730,0.0402",\ +"0.4777,0.4660,0.4504,0.4230,0.3840,0.3137,0.1809"); + } + } + } +pin(B_BIST_MEN) { + direction : input ; + capacitance : 0.00326046 ; + max_transition : "0.38" ; + related_power_pin : VDD; + related_ground_pin : VSS; + internal_power() { + rise_power("scalar"){ + values (0.1484); + } + fall_power("scalar"){ + values (0.2101); + } + } + timing() { + timing_type : setup_rising; + related_pin : "B_BIST_CLK"; + + rise_constraint("SIG2SRAM_constraint_template") { + index_1("0.0040,0.0176,0.0344,0.0656,0.1120,0.2016,0.3800"); + index_2("0.0040,0.0176,0.0344,0.0656,0.1120,0.2016,0.3800"); + values ("0.1418,0.1496,0.1652,0.1926,0.2316,0.3059,0.4465",\ +"0.1301,0.1379,0.1535,0.1809,0.2199,0.2941,0.4348",\ +"0.1145,0.1262,0.1418,0.1652,0.2043,0.2785,0.4191",\ +"0.0871,0.0949,0.1105,0.1379,0.1770,0.2512,0.3879",\ +"0.0480,0.0598,0.0754,0.0988,0.1379,0.2082,0.3488",\ +"-0.0262,-0.0145,0.0012,0.0285,0.0676,0.1379,0.2785",\ +"-0.1668,-0.1551,-0.1395,-0.1121,-0.0730,0.0012,0.1379"); + } + + fall_constraint("SIG2SRAM_constraint_template") { + index_1("0.0040,0.0176,0.0344,0.0656,0.1120,0.2016,0.3800"); + index_2("0.0040,0.0176,0.0344,0.0656,0.1120,0.2016,0.3800"); + values ("0.2082,0.2199,0.2316,0.2590,0.2980,0.3723,0.5051",\ +"0.1965,0.2082,0.2199,0.2473,0.2863,0.3605,0.4934",\ +"0.1809,0.1926,0.2043,0.2316,0.2707,0.3449,0.4777",\ +"0.1574,0.1691,0.1809,0.2082,0.2434,0.3176,0.4543",\ +"0.1145,0.1262,0.1418,0.1691,0.2043,0.2785,0.4113",\ +"0.0441,0.0559,0.0676,0.0949,0.1301,0.2004,0.3332",\ +"-0.0965,-0.0848,-0.0691,-0.0418,-0.0066,0.0676,0.2004"); + } + } + + + timing() { + timing_type : hold_rising; + related_pin : "B_BIST_CLK"; + + rise_constraint("SIG2SRAM_constraint_template") { + index_1("0.0040,0.0176,0.0344,0.0656,0.1120,0.2016,0.3800"); + index_2("0.0040,0.0176,0.0344,0.0656,0.1120,0.2016,0.3800"); + values ("0.1770,0.1652,0.1535,0.1262,0.0832,0.0129,-0.1277",\ +"0.1887,0.1770,0.1613,0.1340,0.0949,0.0207,-0.1199",\ +"0.2043,0.1926,0.1770,0.1496,0.1105,0.0363,-0.1043",\ +"0.2277,0.2160,0.2043,0.1770,0.1379,0.0598,-0.0770",\ +"0.2668,0.2551,0.2434,0.2160,0.1730,0.0988,-0.0379",\ +"0.3449,0.3332,0.3176,0.2902,0.2473,0.1730,0.0363",\ +"0.4816,0.4699,0.4543,0.4270,0.3840,0.3098,0.1770"); + } + + fall_constraint("SIG2SRAM_constraint_template") { + index_1("0.0040,0.0176,0.0344,0.0656,0.1120,0.2016,0.3800"); + index_2("0.0040,0.0176,0.0344,0.0656,0.1120,0.2016,0.3800"); + values ("0.1613,0.1496,0.1379,0.1105,0.0715,0.0012,-0.1355",\ +"0.1730,0.1613,0.1496,0.1184,0.0832,0.0129,-0.1238",\ +"0.1887,0.1770,0.1652,0.1340,0.0988,0.0285,-0.1121",\ +"0.2121,0.2043,0.1887,0.1613,0.1223,0.0520,-0.0848",\ +"0.2551,0.2434,0.2277,0.2004,0.1613,0.0910,-0.0418",\ +"0.3293,0.3176,0.3020,0.2746,0.2395,0.1652,0.0324",\ +"0.4660,0.4543,0.4426,0.4113,0.3762,0.3020,0.1691"); + } + } + } +bus(B_BIST_BM) { + bus_type : D_15_0; + direction : input ; + capacitance : 0.00290564 ; + max_transition : "0.38" ; + pin(B_BIST_BM[15:0]) { + related_power_pin : VDD; + related_ground_pin : VSS; + internal_power() { + when : "B_BIST_MEN"; + rise_power("scalar"){ + values (0.0783); + } + fall_power("scalar"){ + values (0.0812); + } + } + internal_power() { + when : "!B_BIST_MEN"; + rise_power("scalar"){ + values (0.1034); + } + fall_power("scalar"){ + values (0.0834); + } + } + } + timing() { + timing_type : setup_rising; + related_pin : "B_BIST_CLK"; + when : "(B_BIST_WEN & B_BIST_MEN)" + sdf_cond : "B_BIST_RW_ACCESS" + + rise_constraint("SIG2SRAM_constraint_template") { + index_1("0.0040,0.0176,0.0344,0.0656,0.1120,0.2016,0.3800"); + index_2("0.0040,0.0176,0.0344,0.0656,0.1120,0.2016,0.3800"); + values ("-0.2117,-0.2009,-0.1853,-0.1599,-0.1189,-0.0456,0.0891",\ +"-0.2155,-0.2048,-0.1892,-0.1638,-0.1228,-0.0495,0.0852",\ +"-0.2193,-0.2086,-0.1930,-0.1676,-0.1266,-0.0533,0.0814",\ +"-0.2226,-0.2118,-0.1962,-0.1708,-0.1298,-0.0566,0.0782",\ +"-0.2350,-0.2243,-0.2087,-0.1833,-0.1423,-0.0690,0.0657",\ +"-0.2525,-0.2418,-0.2261,-0.2007,-0.1597,-0.0865,0.0483",\ +"-0.2802,-0.2694,-0.2538,-0.2284,-0.1874,-0.1141,0.0206"); + } + + fall_constraint("SIG2SRAM_constraint_template") { + index_1("0.0040,0.0176,0.0344,0.0656,0.1120,0.2016,0.3800"); + index_2("0.0040,0.0176,0.0344,0.0656,0.1120,0.2016,0.3800"); + values ("-0.1882,-0.1765,-0.1638,-0.1365,-0.0994,-0.0261,0.1018",\ +"-0.1921,-0.1804,-0.1677,-0.1404,-0.1032,-0.0300,0.0979",\ +"-0.1959,-0.1842,-0.1715,-0.1441,-0.1070,-0.0338,0.0941",\ +"-0.1992,-0.1874,-0.1747,-0.1474,-0.1103,-0.0370,0.0909",\ +"-0.2116,-0.1999,-0.1872,-0.1598,-0.1227,-0.0495,0.0784",\ +"-0.2291,-0.2173,-0.2046,-0.1773,-0.1402,-0.0669,0.0610",\ +"-0.2567,-0.2450,-0.2323,-0.2050,-0.1678,-0.0946,0.0333"); + } + } + + + timing() { + timing_type : hold_rising; + related_pin : "B_BIST_CLK"; + when : "(B_BIST_WEN & B_BIST_MEN)" + sdf_cond : "B_BIST_RW_ACCESS" + + rise_constraint("SIG2SRAM_constraint_template") { + index_1("0.0040,0.0176,0.0344,0.0656,0.1120,0.2016,0.3800"); + index_2("0.0040,0.0176,0.0344,0.0656,0.1120,0.2016,0.3800"); + values ("0.3170,0.3073,0.2916,0.2653,0.2282,0.1539,0.0192",\ +"0.3209,0.3111,0.2955,0.2692,0.2320,0.1578,0.0231",\ +"0.3247,0.3149,0.2993,0.2730,0.2358,0.1616,0.0269",\ +"0.3280,0.3182,0.3026,0.2762,0.2391,0.1649,0.0301",\ +"0.3404,0.3306,0.3150,0.2887,0.2515,0.1773,0.0426",\ +"0.3579,0.3481,0.3325,0.3061,0.2690,0.1948,0.0600",\ +"0.3855,0.3758,0.3601,0.3338,0.2967,0.2224,0.0877"); + } + + fall_constraint("SIG2SRAM_constraint_template") { + index_1("0.0040,0.0176,0.0344,0.0656,0.1120,0.2016,0.3800"); + index_2("0.0040,0.0176,0.0344,0.0656,0.1120,0.2016,0.3800"); + values ("0.2887,0.2780,0.2643,0.2370,0.2008,0.1286,-0.0013",\ +"0.2926,0.2818,0.2682,0.2408,0.2047,0.1324,0.0026",\ +"0.2964,0.2856,0.2720,0.2446,0.2085,0.1362,0.0064",\ +"0.2996,0.2889,0.2752,0.2479,0.2118,0.1395,0.0096",\ +"0.3121,0.3013,0.2877,0.2603,0.2242,0.1519,0.0221",\ +"0.3295,0.3188,0.3051,0.2778,0.2417,0.1694,0.0395",\ +"0.3572,0.3465,0.3328,0.3054,0.2693,0.1970,0.0672"); + } + } +} + pin(B_BIST_CLK) { + direction : input; + capacitance : 0.00389386; + max_transition : "0.38"; + clock : "true" ; + pin_func_type : active_rising ; + + timing () { + timing_type : "min_pulse_width"; + related_pin : "B_BIST_CLK"; + rise_constraint("CLKTRAN_constraint_template") { + index_1("0.004,0.38"); + values("0.12,0.12"); + } + } + + related_power_pin : VDD; + related_ground_pin : VSS; + + internal_power() { + when : "!B_BIST_MEN & !B_BIST_WEN & !B_BIST_REN"; + rise_power("scalar"){ + values (0); + } + fall_power("scalar"){ + values (0); + } + } + internal_power() { + when : "!B_BIST_MEN & B_BIST_WEN & !B_BIST_REN"; + rise_power("scalar"){ + values (0.7039); + } + fall_power("scalar"){ + values (0); + } + } + internal_power() { + when : "B_BIST_MEN & B_BIST_WEN & !B_BIST_REN"; + rise_power("scalar"){ + values (40.8199); + } + fall_power("scalar"){ + values (0); + } + } + internal_power() { + when : "B_BIST_MEN & B_BIST_WEN & B_BIST_REN"; + rise_power("scalar"){ + values (41.5232); + } + fall_power("scalar"){ + values (0); + } + } + internal_power() { + when : "B_BIST_MEN & !B_BIST_WEN & B_BIST_REN"; + rise_power("scalar"){ + values (33.7892); + } + fall_power("scalar"){ + values (0); + } + } + internal_power() { + when : "!B_BIST_MEN & !B_BIST_WEN & B_BIST_REN"; + rise_power("scalar"){ + values (0.4120); + } + fall_power("scalar"){ + values (0); + } + } + internal_power() { + when : "!B_BIST_MEN & B_BIST_WEN & B_BIST_REN"; + rise_power("scalar"){ + values (0.9290); + } + fall_power("scalar"){ + values (0); + } + } + internal_power() { + when : "B_BIST_MEN & !B_BIST_WEN & !B_BIST_REN"; + rise_power("scalar"){ + values (0); + } + fall_power("scalar"){ + values (0); + } + } + } + bus(B_BIST_DIN) { + bus_type : D_15_0; + direction : input ; + capacitance : 0.00417898 ; + memory_write() { + address : B_BIST_ADDR ; + clocked_on : B_BIST_CLK; + } + + max_transition : "0.38" ; + pin(B_BIST_DIN[15:0]) { + related_power_pin : VDD; + related_ground_pin : VSS; + internal_power() { + when : "B_BIST_MEN"; + rise_power("scalar"){ + values (0.0783); + } + fall_power("scalar"){ + values (0.0812); + } + } + internal_power() { + when : "!B_BIST_MEN"; + rise_power("scalar"){ + values (0.1034); + } + fall_power("scalar"){ + values (0.0834); + } + } + } + timing() { + timing_type : setup_rising; + related_pin : "B_BIST_CLK"; + when : "(B_BIST_WEN & B_BIST_MEN)"; + sdf_cond : "B_BIST_W_ACCESS"; + + rise_constraint("SIG2SRAM_constraint_template") { + index_1("0.0040,0.0176,0.0344,0.0656,0.1120,0.2016,0.3800"); + index_2("0.0040,0.0176,0.0344,0.0656,0.1120,0.2016,0.3800"); + values ("-0.2117,-0.2009,-0.1853,-0.1599,-0.1189,-0.0456,0.0891",\ +"-0.2155,-0.2048,-0.1892,-0.1638,-0.1228,-0.0495,0.0852",\ +"-0.2193,-0.2086,-0.1930,-0.1676,-0.1266,-0.0533,0.0814",\ +"-0.2226,-0.2118,-0.1962,-0.1708,-0.1298,-0.0566,0.0782",\ +"-0.2350,-0.2243,-0.2087,-0.1833,-0.1423,-0.0690,0.0657",\ +"-0.2525,-0.2418,-0.2261,-0.2007,-0.1597,-0.0865,0.0483",\ +"-0.2802,-0.2694,-0.2538,-0.2284,-0.1874,-0.1141,0.0206"); + } + + fall_constraint("SIG2SRAM_constraint_template") { + index_1("0.0040,0.0176,0.0344,0.0656,0.1120,0.2016,0.3800"); + index_2("0.0040,0.0176,0.0344,0.0656,0.1120,0.2016,0.3800"); + values ("-0.1882,-0.1765,-0.1638,-0.1365,-0.0994,-0.0261,0.1018",\ +"-0.1921,-0.1804,-0.1677,-0.1404,-0.1032,-0.0300,0.0979",\ +"-0.1959,-0.1842,-0.1715,-0.1441,-0.1070,-0.0338,0.0941",\ +"-0.1992,-0.1874,-0.1747,-0.1474,-0.1103,-0.0370,0.0909",\ +"-0.2116,-0.1999,-0.1872,-0.1598,-0.1227,-0.0495,0.0784",\ +"-0.2291,-0.2173,-0.2046,-0.1773,-0.1402,-0.0669,0.0610",\ +"-0.2567,-0.2450,-0.2323,-0.2050,-0.1678,-0.0946,0.0333"); + } + } + + timing() { + timing_type : hold_rising; + related_pin : "B_BIST_CLK"; + when : "(B_BIST_WEN & B_BIST_MEN)"; + sdf_cond : "B_BIST_W_ACCESS"; + + rise_constraint("SIG2SRAM_constraint_template") { + index_1("0.0040,0.0176,0.0344,0.0656,0.1120,0.2016,0.3800"); + index_2("0.0040,0.0176,0.0344,0.0656,0.1120,0.2016,0.3800"); + values ("0.3170,0.3073,0.2916,0.2653,0.2282,0.1539,0.0192",\ +"0.3209,0.3111,0.2955,0.2692,0.2320,0.1578,0.0231",\ +"0.3247,0.3149,0.2993,0.2730,0.2358,0.1616,0.0269",\ +"0.3280,0.3182,0.3026,0.2762,0.2391,0.1649,0.0301",\ +"0.3404,0.3306,0.3150,0.2887,0.2515,0.1773,0.0426",\ +"0.3579,0.3481,0.3325,0.3061,0.2690,0.1948,0.0600",\ +"0.3855,0.3758,0.3601,0.3338,0.2967,0.2224,0.0877"); + } + + fall_constraint("SIG2SRAM_constraint_template") { + index_1("0.0040,0.0176,0.0344,0.0656,0.1120,0.2016,0.3800"); + index_2("0.0040,0.0176,0.0344,0.0656,0.1120,0.2016,0.3800"); + values ("0.2887,0.2780,0.2643,0.2370,0.2008,0.1286,-0.0013",\ +"0.2926,0.2818,0.2682,0.2408,0.2047,0.1324,0.0026",\ +"0.2964,0.2856,0.2720,0.2446,0.2085,0.1362,0.0064",\ +"0.2996,0.2889,0.2752,0.2479,0.2118,0.1395,0.0096",\ +"0.3121,0.3013,0.2877,0.2603,0.2242,0.1519,0.0221",\ +"0.3295,0.3188,0.3051,0.2778,0.2417,0.1694,0.0395",\ +"0.3572,0.3465,0.3328,0.3054,0.2693,0.1970,0.0672"); + } + } + } + +bus(B_DOUT) { + + bus_type : D_15_0; + direction : output ; + capacitance : 0 ; + max_capacitance : 0.064 ; + memory_read() { + address : B_ADDR ; + } + pin(B_DOUT[15:0]) { + related_power_pin : VDD; + related_ground_pin : VSS; + internal_power() { + rise_power("scalar") { + values (0); + } + fall_power("scalar") { + values (0); + } + } + } + timing() { + related_pin : "B_CLK"; + timing_type : rising_edge ; + timing_sense : non_unate ; + + cell_rise(SIG2SRAM_delay_template) { + index_1("0.0040,0.0176,0.0344,0.0656,0.1120,0.2016,0.3800"); + index_2("0.0008,0.0014,0.0051,0.0100,0.0339,0.0640"); + values ("2.6533,2.6543,2.6591,2.6646,2.6856,2.7091",\ +"2.6605,2.6615,2.6663,2.6719,2.6928,2.7163",\ +"2.6620,2.6630,2.6678,2.6733,2.6942,2.7177",\ +"2.6653,2.6663,2.6712,2.6767,2.6976,2.7211",\ +"2.6782,2.6792,2.6840,2.6895,2.7104,2.7339",\ +"2.6959,2.6969,2.7017,2.7073,2.7282,2.7517",\ +"2.7213,2.7223,2.7271,2.7326,2.7536,2.7771"); + } + cell_fall(SIG2SRAM_delay_template) { + index_1("0.0040,0.0176,0.0344,0.0656,0.1120,0.2016,0.3800"); + index_2("0.0008,0.0014,0.0051,0.0100,0.0339,0.0640"); + values ("2.6190,2.6199,2.6239,2.6285,2.6456,2.6623",\ +"2.6262,2.6271,2.6311,2.6357,2.6528,2.6695",\ +"2.6277,2.6286,2.6326,2.6372,2.6542,2.6710",\ +"2.6311,2.6319,2.6359,2.6405,2.6576,2.6743",\ +"2.6439,2.6447,2.6488,2.6533,2.6704,2.6871",\ +"2.6616,2.6625,2.6665,2.6711,2.6882,2.7049",\ +"2.6870,2.6879,2.6919,2.6965,2.7136,2.7303"); + } + + rise_transition(SRAM_load_template) { + index_1("0.0008,0.0014,0.0051,0.0100,0.0339,0.0640"); + values ("0.0206,0.0210,0.0265,0.0323,0.0606,0.0955"); + } + fall_transition(SRAM_load_template) { + index_1("0.0008,0.0014,0.0051,0.0100,0.0339,0.0640"); + values ("0.0170,0.0177,0.0222,0.0270,0.0451,0.0644"); + } + } +} +cell_leakage_power : 903.4138; +} +} diff --git a/flow/platforms/ihp-sg13g2/lib/RM_IHPSG13_2P_1024x16_c2_bm_bist_slow_1p08V_125C.lib b/flow/platforms/ihp-sg13g2/lib/RM_IHPSG13_2P_1024x16_c2_bm_bist_slow_1p08V_125C.lib new file mode 100644 index 0000000000..0f922ce857 --- /dev/null +++ b/flow/platforms/ihp-sg13g2/lib/RM_IHPSG13_2P_1024x16_c2_bm_bist_slow_1p08V_125C.lib @@ -0,0 +1,2898 @@ +/* ------------------------------------------------------*/ +/**/ +/* Copyright 2025 IHP PDK Authors*/ +/**/ +/* Licensed under the Apache License, Version 2.0 (the "License");*/ +/* you may not use this file except in compliance with the License.*/ +/* You may obtain a copy of the License at*/ +/* */ +/* https://www.apache.org/licenses/LICENSE-2.0*/ +/* */ +/* Unless required by applicable law or agreed to in writing, software*/ +/* distributed under the License is distributed on an "AS IS" BASIS,*/ +/* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.*/ +/* See the License for the specific language governing permissions and*/ +/* limitations under the License.*/ +/* */ +/* Generated on Tue Sep 9 10:49:16 2025 */ +/* */ +/* ------------------------------------------------------ */ +library(RM_IHPSG13_2P_1024x16_c2_bm_bist_slow_1p08V_125C) { + technology (cmos) ; + delay_model : table_lookup ; + define ("add_pg_pin_to_lib", "library", "boolean"); + add_pg_pin_to_lib : true; + voltage_map ( VDD, 1.08); + voltage_map ( VDDARRAY, 1.08); + voltage_map ( VSS, 0.000000 ); + + date : "Tue Sep 9 10:49:15 2025" ; + comment : "IHP Microelectronics GmbH, 2023" ; + revision : 1.0.0 ; + simulation : true ; + nom_process : 1 ; + nom_temperature : 125 ; + nom_voltage : 1.08 ; + + operating_conditions("slow_1p08V_125C"){ + process : 1 ; + temperature : 125 ; + voltage : 1.08 ; + tree_type : "balanced_tree" ; + } + + default_operating_conditions : slow_1p08V_125C ; + default_max_transition : 1.0 ; + default_fanout_load : 1.0 ; + default_inout_pin_cap : 0.0 ; + default_input_pin_cap : 0.0 ; + default_output_pin_cap : 0.0 ; + default_cell_leakage_power : 0.0 ; + default_leakage_power_density : 0.0 ; + + slew_lower_threshold_pct_rise : 30 ; + slew_upper_threshold_pct_rise : 70 ; + input_threshold_pct_fall : 50 ; + output_threshold_pct_fall : 50 ; + input_threshold_pct_rise : 50 ; + output_threshold_pct_rise : 50 ; + slew_lower_threshold_pct_fall : 30 ; + slew_upper_threshold_pct_fall : 70 ; + slew_derate_from_library : 0.5; + k_volt_cell_leakage_power : 0.0 ; + k_temp_cell_leakage_power : 0.0 ; + k_process_cell_leakage_power : 0.0 ; + k_volt_internal_power : 0.0 ; + k_temp_internal_power : 0.0 ; + k_process_internal_power : 0.0 ; + + capacitive_load_unit (1,pf) ; + voltage_unit : "1V" ; + current_unit : "1uA" ; + time_unit : "1ns" ; + leakage_power_unit : "1nW" ; + pulling_resistance_unit : "1kohm"; + /* + ------------------------------------------------------------------------------------------ + implicit units overview: + cell_area unit : "um" + internal_power unit : "1e-12 * J/toggle = 1 * uW/MHz" + (capacitive_load_unit * voltage_unit^2) per toggle event + ------------------------------------------------------------------------------------------ + */ + library_features(report_delay_calculation); + define_cell_area (pad_drivers,pad_driver_sites) ; + + lu_table_template(CLKTRAN_constraint_template) { + variable_1 : constrained_pin_transition; + index_1 ( "0.010, 0.050, 0.200, 0.400, 1.000" ); + } + lu_table_template(SRAM_load_template) { + variable_1 : total_output_net_capacitance; + index_1 ( "0.0008,0.0014,0.0051,0.0100,0.0339,0.0640" ); + } + lu_table_template(SIG2SRAM_constraint_template) { + variable_1 : related_pin_transition; + variable_2 : constrained_pin_transition; + index_1 ( "0.0080,0.0288,0.0616,0.1072,0.1920,0.3496,0.5952" ); + index_2 ( "0.0080,0.0288,0.0616,0.1072,0.1920,0.3496,0.5952" ); + } + + lu_table_template(SIG2SRAM_delay_template) { + variable_1 : input_net_transition; + variable_2 : total_output_net_capacitance; + index_1 ( "0.0080,0.0288,0.0616,0.1072,0.1920,0.3496,0.5952" ); + index_2 ( "0.0008,0.0014,0.0051,0.0100,0.0339,0.0640" ); + } + + type (D_15_0) { + base_type : array; + data_type : bit; + bit_width : 16; + bit_from : 15; + bit_to : 0; + downto : true; + } + + type (A_9_0) { + base_type : array; + data_type : bit; + bit_width : 10; + bit_from : 9; + bit_to : 0; + downto : true; + } + +cell(RM_IHPSG13_2P_1024x16_c2_bm_bist) { +pg_pin (VDD) { + pg_type : primary_power; + voltage_name : VDD; +} +pg_pin (VDDARRAY) { + pg_type : primary_power; + voltage_name : VDDARRAY; +} +pg_pin (VSS) { + pg_type : primary_ground; + voltage_name : VSS; +} + +memory() { + type : ram; + address_width : 10; + word_width : 16; +} + +interface_timing : false; +bus_naming_style : "%s[%d]" ; +area : 155153.8157 ; + + pin(A_DLY) { + direction : input ; + capacitance : 0.00387999 ; + max_transition : "1" ; + related_power_pin : VDD; + related_ground_pin : VSS; + internal_power() { + rise_power("scalar") { + values (0); + } + fall_power("scalar") { + values (0); + } + } + } + +bus(A_ADDR) { + bus_type : A_9_0; + direction : input ; + capacitance : 0.0129586 ; + pin(A_ADDR[0]) { + capacitance : 0.0058687 ; + } + pin(A_ADDR[1]) { + capacitance : 0.00807137 ; + } + pin(A_ADDR[2]) { + capacitance : 0.0112051 ; + } + pin(A_ADDR[3]) { + capacitance : 0.00709524 ; + } + pin(A_ADDR[4]) { + capacitance : 0.00648778 ; + } + pin(A_ADDR[5]) { + capacitance : 0.011209 ; + } + pin(A_ADDR[6]) { + capacitance : 0.0140441 ; + } + pin(A_ADDR[7]) { + capacitance : 0.0111199 ; + } + pin(A_ADDR[8]) { + capacitance : 0.00957807 ; + } + max_transition : "0.5952" ; + pin(A_ADDR[9:0]) { + related_power_pin : VDD; + related_ground_pin : VSS; + internal_power() { + when : "A_MEN"; + rise_power("scalar"){ + values (0.0011); + } + fall_power("scalar"){ + values (0.0188); + } + } + internal_power() { + when : "!A_MEN"; + rise_power("scalar"){ + values (0.0058); + } + fall_power("scalar"){ + values (0.0107); + } + } + } + timing() { + timing_type : setup_rising; + related_pin : "A_CLK"; + when : "((A_WEN | A_REN)& A_MEN)" + sdf_cond : "A_RW_ACCESS" + + rise_constraint("SIG2SRAM_constraint_template") { + index_1("0.0080,0.0288,0.0616,0.1072,0.1920,0.3496,0.5952"); + index_2("0.0080,0.0288,0.0616,0.1072,0.1920,0.3496,0.5952"); + values ("-0.7371,-0.7176,-0.6863,-0.6434,-0.5652,-0.4168,-0.1980",\ +"-0.7566,-0.7371,-0.7059,-0.6629,-0.5848,-0.4363,-0.2137",\ +"-0.7879,-0.7645,-0.7332,-0.6902,-0.6121,-0.4637,-0.2449",\ +"-0.8309,-0.8074,-0.7762,-0.7332,-0.6551,-0.5066,-0.2879",\ +"-0.9051,-0.8895,-0.8543,-0.8113,-0.7332,-0.5887,-0.3660",\ +"-1.0418,-1.0262,-0.9949,-0.9480,-0.8699,-0.7293,-0.5027",\ +"-1.2684,-1.2449,-1.2176,-1.1707,-1.0965,-0.9480,-0.7293"); + } + + fall_constraint("SIG2SRAM_constraint_template") { + index_1("0.0080,0.0288,0.0616,0.1072,0.1920,0.3496,0.5952"); + index_2("0.0080,0.0288,0.0616,0.1072,0.1920,0.3496,0.5952"); + values ("-0.5926,-0.5730,-0.5418,-0.4988,-0.4246,-0.2879,-0.0730",\ +"-0.6121,-0.5926,-0.5613,-0.5223,-0.4441,-0.3074,-0.0887",\ +"-0.6395,-0.6199,-0.5926,-0.5496,-0.4715,-0.3348,-0.1160",\ +"-0.6863,-0.6668,-0.6355,-0.5965,-0.5184,-0.3777,-0.1590",\ +"-0.7605,-0.7410,-0.7137,-0.6746,-0.5926,-0.4559,-0.2410",\ +"-0.9012,-0.8816,-0.8504,-0.8113,-0.7332,-0.5926,-0.3895",\ +"-1.1238,-1.1043,-1.0769,-1.0379,-0.9559,-0.8191,-0.6004"); + } + } + + + timing() { + timing_type : hold_rising; + related_pin : "A_CLK"; + when : "((A_WEN | A_REN)& A_MEN)" + sdf_cond : "A_RW_ACCESS" + + rise_constraint("SIG2SRAM_constraint_template") { + index_1("0.0080,0.0288,0.0616,0.1072,0.1920,0.3496,0.5952"); + index_2("0.0080,0.0288,0.0616,0.1072,0.1920,0.3496,0.5952"); + values ("0.8488,0.8293,0.7980,0.7551,0.6730,0.5285,0.3098",\ +"0.8684,0.8488,0.8176,0.7746,0.6926,0.5480,0.3254",\ +"0.8996,0.8801,0.8449,0.8020,0.7238,0.5754,0.3527",\ +"0.9426,0.9191,0.8918,0.8488,0.7668,0.6223,0.3996",\ +"1.0168,1.0012,0.9699,0.9230,0.8449,0.7004,0.4777",\ +"1.1574,1.1379,1.1105,1.0598,0.9816,0.8371,0.6184",\ +"1.3801,1.3605,1.3254,1.2980,1.2043,1.0637,0.8371"); + } + + fall_constraint("SIG2SRAM_constraint_template") { + index_1("0.0080,0.0288,0.0616,0.1072,0.1920,0.3496,0.5952"); + index_2("0.0080,0.0288,0.0616,0.1072,0.1920,0.3496,0.5952"); + values ("0.6965,0.6770,0.6496,0.6066,0.5246,0.3918,0.1730",\ +"0.7160,0.6965,0.6652,0.6262,0.5441,0.4113,0.1965",\ +"0.7473,0.7277,0.6965,0.6535,0.5754,0.4426,0.2238",\ +"0.7863,0.7707,0.7395,0.7004,0.6223,0.4855,0.2629",\ +"0.8684,0.8449,0.8176,0.7785,0.7004,0.5637,0.3449",\ +"1.0051,0.9855,0.9855,0.9113,0.8332,0.7004,0.4895",\ +"1.2277,1.2082,1.1809,1.1379,1.0598,0.9230,0.7004"); + } + } +} +pin(A_WEN) { + direction : input ; + capacitance : 0.00313551 ; + max_transition : "0.5952" ; + related_power_pin : VDD; + related_ground_pin : VSS; + internal_power() { + when : "A_MEN"; + rise_power("scalar"){ + values (0.0065); + } + fall_power("scalar"){ + values (0.0066); + } + } + internal_power() { + when : "!A_MEN"; + rise_power("scalar"){ + values (0.0128); + } + fall_power("scalar"){ + values (0.0293); + } + } + timing() { + timing_type : setup_rising; + related_pin : "A_CLK"; + when : "A_MEN" + sdf_cond : "A_MEN" + + rise_constraint("SIG2SRAM_constraint_template") { + index_1("0.0080,0.0288,0.0616,0.1072,0.1920,0.3496,0.5952"); + index_2("0.0080,0.0288,0.0616,0.1072,0.1920,0.3496,0.5952"); + values ("0.3137,0.3332,0.3605,0.4035,0.4816,0.6223,0.8488",\ +"0.2980,0.3176,0.3410,0.3840,0.4660,0.6027,0.8293",\ +"0.2629,0.2824,0.3098,0.3527,0.4348,0.5754,0.7980",\ +"0.2199,0.2395,0.2668,0.3098,0.3918,0.5324,0.7590",\ +"0.1418,0.1613,0.1887,0.2316,0.3137,0.4348,0.6730",\ +"0.0012,0.0207,0.0520,0.0910,0.1730,0.3098,0.5285",\ +"-0.2215,-0.2020,-0.1746,-0.1277,-0.0496,0.0910,0.3098"); + } + + fall_constraint("SIG2SRAM_constraint_template") { + index_1("0.0080,0.0288,0.0616,0.1072,0.1920,0.3496,0.5952"); + index_2("0.0080,0.0288,0.0616,0.1072,0.1920,0.3496,0.5952"); + values ("0.4504,0.4699,0.4973,0.5324,0.6027,0.7355,0.9699",\ +"0.4309,0.4504,0.4777,0.5129,0.5910,0.7160,0.9504",\ +"0.3996,0.4191,0.4465,0.4816,0.5520,0.6848,0.9191",\ +"0.3605,0.3762,0.4035,0.4387,0.5168,0.6418,0.8723",\ +"0.2785,0.2980,0.3215,0.3605,0.4348,0.5637,0.7980",\ +"0.1379,0.1574,0.1809,0.2199,0.2980,0.4309,0.6457",\ +"-0.0809,-0.0613,-0.0340,0.0051,0.0832,0.2160,0.4191"); + } + } + + + timing() { + timing_type : hold_rising; + related_pin : "A_CLK"; + when : "A_MEN" + sdf_cond : "A_MEN" + + rise_constraint("SIG2SRAM_constraint_template") { + index_1("0.0080,0.0288,0.0616,0.1072,0.1920,0.3496,0.5952"); + index_2("0.0080,0.0288,0.0616,0.1072,0.1920,0.3496,0.5952"); + values ("0.3723,0.3527,0.3215,0.2785,0.1965,0.0559,-0.1668",\ +"0.3918,0.3723,0.3449,0.2980,0.2160,0.0754,-0.1473",\ +"0.4152,0.3996,0.3684,0.3254,0.2434,0.1066,-0.1199",\ +"0.4621,0.4465,0.4152,0.3723,0.2863,0.1496,-0.0730",\ +"0.5324,0.5207,0.4895,0.4465,0.3645,0.2199,0.0051",\ +"0.6770,0.6535,0.6301,0.5832,0.5090,0.3605,0.1418",\ +"0.9035,0.8879,0.8566,0.8137,0.7316,0.5871,0.3684"); + } + + fall_constraint("SIG2SRAM_constraint_template") { + index_1("0.0080,0.0288,0.0616,0.1072,0.1920,0.3496,0.5952"); + index_2("0.0080,0.0288,0.0616,0.1072,0.1920,0.3496,0.5952"); + values ("0.3762,0.3566,0.3293,0.2863,0.2043,0.0676,-0.1434",\ +"0.3957,0.3762,0.3488,0.3059,0.2238,0.0871,-0.1199",\ +"0.4230,0.4035,0.3723,0.3332,0.2512,0.1184,-0.0965",\ +"0.4660,0.4465,0.4191,0.3762,0.2941,0.1613,-0.0496",\ +"0.5324,0.5168,0.4973,0.4543,0.3723,0.2316,0.0285",\ +"0.6809,0.6613,0.6340,0.5910,0.5129,0.3645,0.1652",\ +"0.9113,0.8918,0.8605,0.8176,0.7395,0.5988,0.3879"); + } + } + } +pin(A_REN) { + direction : input ; + capacitance : 0.00381144 ; + max_transition : "0.5952" ; + related_power_pin : VDD; + related_ground_pin : VSS; + internal_power() { + when : "A_MEN"; + rise_power("scalar"){ + values (0.0060); + } + fall_power("scalar"){ + values (0.0027); + } + } + internal_power() { + when : "!A_MEN"; + rise_power("scalar"){ + values (0.0013); + } + fall_power("scalar"){ + values (0.0021); + } + } + timing() { + timing_type : setup_rising; + related_pin : "A_CLK"; + when : "A_MEN" + sdf_cond : "A_MEN" + + rise_constraint("SIG2SRAM_constraint_template") { + index_1("0.0080,0.0288,0.0616,0.1072,0.1920,0.3496,0.5952"); + index_2("0.0080,0.0288,0.0616,0.1072,0.1920,0.3496,0.5952"); + values ("-0.0770,-0.0574,-0.0262,0.0168,0.0949,0.2355,0.4582",\ +"-0.0965,-0.0770,-0.0457,-0.0027,0.0754,0.2160,0.4387",\ +"-0.1199,-0.1004,-0.0730,-0.0262,0.0520,0.1887,0.4113",\ +"-0.1590,-0.1434,-0.1160,-0.0730,0.0051,0.1457,0.3645",\ +"-0.2449,-0.2254,-0.1941,-0.1473,-0.0770,0.0676,0.2863",\ +"-0.3816,-0.3699,-0.3387,-0.2801,-0.2215,-0.0770,0.1457",\ +"-0.6121,-0.5926,-0.5613,-0.5145,-0.4363,-0.2996,-0.0730"); + } + + fall_constraint("SIG2SRAM_constraint_template") { + index_1("0.0080,0.0288,0.0616,0.1072,0.1920,0.3496,0.5952"); + index_2("0.0080,0.0288,0.0616,0.1072,0.1920,0.3496,0.5952"); + values ("0.1262,0.1457,0.1691,0.2121,0.2824,0.4191,0.6457",\ +"0.1105,0.1262,0.1496,0.1887,0.2629,0.3996,0.6262",\ +"0.0793,0.0949,0.1223,0.1652,0.2395,0.3684,0.5949",\ +"0.0363,0.0559,0.0793,0.1223,0.2004,0.3410,0.5520",\ +"-0.0457,-0.0262,0.0012,0.0441,0.1301,0.2629,0.4738",\ +"-0.1902,-0.1746,-0.1434,-0.1043,-0.0184,0.1223,0.3332",\ +"-0.4129,-0.3934,-0.3660,-0.3230,-0.2449,-0.1043,0.1105"); + } + } + + + timing() { + timing_type : hold_rising; + related_pin : "A_CLK"; + when : "A_MEN" + sdf_cond : "A_MEN" + + rise_constraint("SIG2SRAM_constraint_template") { + index_1("0.0080,0.0288,0.0616,0.1072,0.1920,0.3496,0.5952"); + index_2("0.0080,0.0288,0.0616,0.1072,0.1920,0.3496,0.5952"); + values ("0.4113,0.3918,0.3645,0.3176,0.2395,0.0988,-0.1238",\ +"0.4309,0.4113,0.3840,0.3371,0.2590,0.1184,-0.1043",\ +"0.4582,0.4387,0.4113,0.3645,0.2824,0.1457,-0.0770",\ +"0.5051,0.4816,0.4543,0.4074,0.3293,0.1887,-0.0340",\ +"0.5715,0.5598,0.5324,0.4895,0.4035,0.2512,0.0441",\ +"0.7043,0.7004,0.6730,0.6262,0.5402,0.3957,0.1809",\ +"0.9387,0.9270,0.8957,0.8527,0.7746,0.6262,0.4074"); + } + + fall_constraint("SIG2SRAM_constraint_template") { + index_1("0.0080,0.0288,0.0616,0.1072,0.1920,0.3496,0.5952"); + index_2("0.0080,0.0288,0.0616,0.1072,0.1920,0.3496,0.5952"); + values ("0.4152,0.3918,0.3645,0.3215,0.2395,0.1027,-0.1082",\ +"0.4309,0.4113,0.3801,0.3410,0.2590,0.1223,-0.0926",\ +"0.4582,0.4387,0.4074,0.3684,0.2863,0.1496,-0.0613",\ +"0.5012,0.4816,0.4504,0.4074,0.3293,0.1887,-0.0145",\ +"0.5715,0.5559,0.5285,0.4816,0.3996,0.2512,0.0598",\ +"0.7160,0.7004,0.6691,0.6262,0.5520,0.4035,0.2004",\ +"0.9387,0.9191,0.8957,0.8488,0.7707,0.6262,0.4113"); + } + } + } +pin(A_MEN) { + direction : input ; + capacitance : 0.00300347 ; + max_transition : "0.5952" ; + related_power_pin : VDD; + related_ground_pin : VSS; + internal_power() { + rise_power("scalar"){ + values (0.0060); + } + fall_power("scalar"){ + values (0.0099); + } + } + timing() { + timing_type : setup_rising; + related_pin : "A_CLK"; + + rise_constraint("SIG2SRAM_constraint_template") { + index_1("0.0080,0.0288,0.0616,0.1072,0.1920,0.3496,0.5952"); + index_2("0.0080,0.0288,0.0616,0.1072,0.1920,0.3496,0.5952"); + values ("0.3215,0.3449,0.3684,0.4113,0.4895,0.6301,0.8527",\ +"0.3059,0.3254,0.3527,0.3957,0.4738,0.6145,0.8371",\ +"0.2746,0.2941,0.3215,0.3645,0.4426,0.5871,0.8059",\ +"0.2316,0.2512,0.2785,0.3215,0.3996,0.5402,0.7629",\ +"0.1496,0.1730,0.1965,0.2395,0.3215,0.4660,0.6848",\ +"0.0090,0.0285,0.0598,0.1027,0.1809,0.3176,0.5402",\ +"-0.2098,-0.1902,-0.1668,-0.1199,-0.0418,0.0988,0.3137"); + } + + fall_constraint("SIG2SRAM_constraint_template") { + index_1("0.0080,0.0288,0.0616,0.1072,0.1920,0.3496,0.5952"); + index_2("0.0080,0.0288,0.0616,0.1072,0.1920,0.3496,0.5952"); + values ("0.4582,0.4738,0.5012,0.5363,0.6145,0.7395,0.9738",\ +"0.4387,0.4543,0.4816,0.5207,0.5910,0.7199,0.9582",\ +"0.4035,0.4230,0.4504,0.4855,0.5637,0.6887,0.9230",\ +"0.3645,0.3840,0.4074,0.4465,0.5285,0.6496,0.8840",\ +"0.2824,0.3020,0.3254,0.3645,0.4465,0.5715,0.7980",\ +"0.1418,0.1613,0.1887,0.2238,0.3020,0.4309,0.6496",\ +"-0.0770,-0.0574,-0.0301,0.0090,0.0910,0.2238,0.4191"); + } + } + + + timing() { + timing_type : hold_rising; + related_pin : "A_CLK"; + + rise_constraint("SIG2SRAM_constraint_template") { + index_1("0.0080,0.0288,0.0616,0.1072,0.1920,0.3496,0.5952"); + index_2("0.0080,0.0288,0.0616,0.1072,0.1920,0.3496,0.5952"); + values ("0.3762,0.3605,0.3293,0.2863,0.2043,0.0637,-0.1629",\ +"0.3996,0.3801,0.3488,0.3020,0.2238,0.0832,-0.1395",\ +"0.4230,0.4074,0.3723,0.3293,0.2473,0.1105,-0.1121",\ +"0.4621,0.4465,0.4152,0.3762,0.2941,0.1535,-0.0691",\ +"0.5441,0.5285,0.4973,0.4465,0.3684,0.2316,0.0090",\ +"0.6848,0.6652,0.6301,0.5910,0.5129,0.3605,0.1496",\ +"0.9074,0.8918,0.8566,0.8215,0.7395,0.5910,0.3723"); + } + + fall_constraint("SIG2SRAM_constraint_template") { + index_1("0.0080,0.0288,0.0616,0.1072,0.1920,0.3496,0.5952"); + index_2("0.0080,0.0288,0.0616,0.1072,0.1920,0.3496,0.5952"); + values ("0.3762,0.3605,0.3332,0.2863,0.2043,0.0715,-0.1395",\ +"0.3996,0.3762,0.3488,0.3059,0.2238,0.0910,-0.1199",\ +"0.4270,0.4035,0.3762,0.3332,0.2512,0.1184,-0.0965",\ +"0.4699,0.4504,0.4191,0.3762,0.2941,0.1613,-0.0496",\ +"0.5441,0.5285,0.4973,0.4543,0.3762,0.2355,0.0324",\ +"0.6770,0.6613,0.6340,0.5949,0.5207,0.3762,0.1652",\ +"0.9074,0.8918,0.8605,0.8176,0.7395,0.6027,0.3918"); + } + } + } +bus(A_BM) { + bus_type : D_15_0; + direction : input ; + capacitance : 0.00359979 ; + max_transition : "0.5952" ; + pin(A_BM[15:0]) { + related_power_pin : VDD; + related_ground_pin : VSS; + internal_power() { + when : "A_MEN"; + rise_power("scalar"){ + values (0.0368); + } + fall_power("scalar"){ + values (0.0200); + } + } + internal_power() { + when : "!A_MEN"; + rise_power("scalar"){ + values (0.0452); + } + fall_power("scalar"){ + values (0.0145); + } + } + } + timing() { + timing_type : setup_rising; + related_pin : "A_CLK"; + when : "(A_WEN & A_MEN)" + sdf_cond : "A_RW_ACCESS" + + rise_constraint("SIG2SRAM_constraint_template") { + index_1("0.0080,0.0288,0.0616,0.1072,0.1920,0.3496,0.5952"); + index_2("0.0080,0.0288,0.0616,0.1072,0.1920,0.3496,0.5952"); + values ("-0.6982,-0.6787,-0.6533,-0.6104,-0.5293,-0.3838,-0.1611",\ +"-0.7063,-0.6867,-0.6613,-0.6184,-0.5373,-0.3918,-0.1692",\ +"-0.7153,-0.6957,-0.6704,-0.6274,-0.5463,-0.4008,-0.1782",\ +"-0.7284,-0.7089,-0.6835,-0.6405,-0.5595,-0.4140,-0.1913",\ +"-0.7527,-0.7332,-0.7078,-0.6648,-0.5838,-0.4383,-0.2156",\ +"-0.7832,-0.7637,-0.7383,-0.6953,-0.6143,-0.4688,-0.2461",\ +"-0.8647,-0.8451,-0.8198,-0.7768,-0.6957,-0.5502,-0.3276"); + } + + fall_constraint("SIG2SRAM_constraint_template") { + index_1("0.0080,0.0288,0.0616,0.1072,0.1920,0.3496,0.5952"); + index_2("0.0080,0.0288,0.0616,0.1072,0.1920,0.3496,0.5952"); + values ("-0.6357,-0.6182,-0.5908,-0.5518,-0.4688,-0.3330,-0.1211",\ +"-0.6438,-0.6262,-0.5988,-0.5598,-0.4768,-0.3410,-0.1291",\ +"-0.6528,-0.6352,-0.6079,-0.5688,-0.4858,-0.3500,-0.1381",\ +"-0.6659,-0.6484,-0.6210,-0.5819,-0.4989,-0.3632,-0.1513",\ +"-0.6902,-0.6726,-0.6453,-0.6062,-0.5232,-0.3875,-0.1756",\ +"-0.7207,-0.7032,-0.6758,-0.6367,-0.5537,-0.4180,-0.2061",\ +"-0.8022,-0.7846,-0.7573,-0.7182,-0.6352,-0.4994,-0.2875"); + } + } + + + timing() { + timing_type : hold_rising; + related_pin : "A_CLK"; + when : "(A_WEN & A_MEN)" + sdf_cond : "A_RW_ACCESS" + + rise_constraint("SIG2SRAM_constraint_template") { + index_1("0.0080,0.0288,0.0616,0.1072,0.1920,0.3496,0.5952"); + index_2("0.0080,0.0288,0.0616,0.1072,0.1920,0.3496,0.5952"); + values ("0.8139,0.7924,0.7680,0.7250,0.6449,0.4984,0.2758",\ +"0.8219,0.8004,0.7760,0.7330,0.6529,0.5065,0.2838",\ +"0.8309,0.8094,0.7850,0.7420,0.6619,0.5155,0.2928",\ +"0.8440,0.8226,0.7982,0.7552,0.6751,0.5286,0.3060",\ +"0.8683,0.8468,0.8224,0.7795,0.6994,0.5529,0.3302",\ +"0.8988,0.8773,0.8529,0.8100,0.7299,0.5834,0.3607",\ +"0.9803,0.9588,0.9344,0.8914,0.8113,0.6649,0.4422"); + } + + fall_constraint("SIG2SRAM_constraint_template") { + index_1("0.0080,0.0288,0.0616,0.1072,0.1920,0.3496,0.5952"); + index_2("0.0080,0.0288,0.0616,0.1072,0.1920,0.3496,0.5952"); + values ("0.7396,0.7221,0.6947,0.6557,0.5726,0.4359,0.2250",\ +"0.7477,0.7301,0.7027,0.6637,0.5807,0.4440,0.2330",\ +"0.7567,0.7391,0.7117,0.6727,0.5897,0.4530,0.2420",\ +"0.7698,0.7522,0.7249,0.6858,0.6028,0.4661,0.2552",\ +"0.7941,0.7765,0.7492,0.7101,0.6271,0.4904,0.2795",\ +"0.8246,0.8070,0.7797,0.7406,0.6576,0.5209,0.3100",\ +"0.9061,0.8885,0.8611,0.8221,0.7391,0.6024,0.3914"); + } + } +} + pin(A_CLK) { + direction : input; + capacitance : 0.00378957; + max_transition : "0.5952"; + clock : "true" ; + pin_func_type : active_rising ; + + timing () { + timing_type : "min_pulse_width"; + related_pin : "A_CLK"; + rise_constraint("CLKTRAN_constraint_template") { + index_1("0.008,0.5952"); + values("0.4,0.4"); + } + } + + related_power_pin : VDD; + related_ground_pin : VSS; + + internal_power() { + when : "!A_MEN & !A_WEN & !A_REN"; + rise_power("scalar"){ + values (0); + } + fall_power("scalar"){ + values (0); + } + } + internal_power() { + when : "!A_MEN & A_WEN & !A_REN"; + rise_power("scalar"){ + values (0.5660); + } + fall_power("scalar"){ + values (0); + } + } + internal_power() { + when : "A_MEN & A_WEN & !A_REN"; + rise_power("scalar"){ + values (25.9369); + } + fall_power("scalar"){ + values (0); + } + } + internal_power() { + when : "A_MEN & A_WEN & A_REN"; + rise_power("scalar"){ + values (26.9678); + } + fall_power("scalar"){ + values (0); + } + } + internal_power() { + when : "A_MEN & !A_WEN & A_REN"; + rise_power("scalar"){ + values (20.0971); + } + fall_power("scalar"){ + values (0); + } + } + internal_power() { + when : "!A_MEN & !A_WEN & A_REN"; + rise_power("scalar"){ + values (0.3586); + } + fall_power("scalar"){ + values (0); + } + } + internal_power() { + when : "!A_MEN & A_WEN & A_REN"; + rise_power("scalar"){ + values (0.7302); + } + fall_power("scalar"){ + values (0); + } + } + internal_power() { + when : "A_MEN & !A_WEN & !A_REN"; + rise_power("scalar"){ + values (0); + } + fall_power("scalar"){ + values (0); + } + } + } + bus(A_DIN) { + bus_type : D_15_0; + direction : input ; + capacitance : 0.00502163 ; + memory_write() { + address : A_ADDR ; + clocked_on : A_CLK; + } + + max_transition : "0.5952" ; + pin(A_DIN[15:0]) { + related_power_pin : VDD; + related_ground_pin : VSS; + internal_power() { + when : "A_MEN"; + rise_power("scalar"){ + values (0.0368); + } + fall_power("scalar"){ + values (0.0200); + } + } + internal_power() { + when : "!A_MEN"; + rise_power("scalar"){ + values (0.0452); + } + fall_power("scalar"){ + values (0.0145); + } + } + } + timing() { + timing_type : setup_rising; + related_pin : "A_CLK"; + when : "(A_WEN & A_MEN)"; + sdf_cond : "A_W_ACCESS"; + + rise_constraint("SIG2SRAM_constraint_template") { + index_1("0.0080,0.0288,0.0616,0.1072,0.1920,0.3496,0.5952"); + index_2("0.0080,0.0288,0.0616,0.1072,0.1920,0.3496,0.5952"); + values ("-0.6982,-0.6787,-0.6533,-0.6104,-0.5293,-0.3838,-0.1611",\ +"-0.7063,-0.6867,-0.6613,-0.6184,-0.5373,-0.3918,-0.1692",\ +"-0.7153,-0.6957,-0.6704,-0.6274,-0.5463,-0.4008,-0.1782",\ +"-0.7284,-0.7089,-0.6835,-0.6405,-0.5595,-0.4140,-0.1913",\ +"-0.7527,-0.7332,-0.7078,-0.6648,-0.5838,-0.4383,-0.2156",\ +"-0.7832,-0.7637,-0.7383,-0.6953,-0.6143,-0.4688,-0.2461",\ +"-0.8647,-0.8451,-0.8198,-0.7768,-0.6957,-0.5502,-0.3276"); + } + + fall_constraint("SIG2SRAM_constraint_template") { + index_1("0.0080,0.0288,0.0616,0.1072,0.1920,0.3496,0.5952"); + index_2("0.0080,0.0288,0.0616,0.1072,0.1920,0.3496,0.5952"); + values ("-0.6357,-0.6182,-0.5908,-0.5518,-0.4688,-0.3330,-0.1211",\ +"-0.6438,-0.6262,-0.5988,-0.5598,-0.4768,-0.3410,-0.1291",\ +"-0.6528,-0.6352,-0.6079,-0.5688,-0.4858,-0.3500,-0.1381",\ +"-0.6659,-0.6484,-0.6210,-0.5819,-0.4989,-0.3632,-0.1513",\ +"-0.6902,-0.6726,-0.6453,-0.6062,-0.5232,-0.3875,-0.1756",\ +"-0.7207,-0.7032,-0.6758,-0.6367,-0.5537,-0.4180,-0.2061",\ +"-0.8022,-0.7846,-0.7573,-0.7182,-0.6352,-0.4994,-0.2875"); + } + } + + timing() { + timing_type : hold_rising; + related_pin : "A_CLK"; + when : "(A_WEN & A_MEN)"; + sdf_cond : "A_W_ACCESS"; + + rise_constraint("SIG2SRAM_constraint_template") { + index_1("0.0080,0.0288,0.0616,0.1072,0.1920,0.3496,0.5952"); + index_2("0.0080,0.0288,0.0616,0.1072,0.1920,0.3496,0.5952"); + values ("0.8139,0.7924,0.7680,0.7250,0.6449,0.4984,0.2758",\ +"0.8219,0.8004,0.7760,0.7330,0.6529,0.5065,0.2838",\ +"0.8309,0.8094,0.7850,0.7420,0.6619,0.5155,0.2928",\ +"0.8440,0.8226,0.7982,0.7552,0.6751,0.5286,0.3060",\ +"0.8683,0.8468,0.8224,0.7795,0.6994,0.5529,0.3302",\ +"0.8988,0.8773,0.8529,0.8100,0.7299,0.5834,0.3607",\ +"0.9803,0.9588,0.9344,0.8914,0.8113,0.6649,0.4422"); + } + + fall_constraint("SIG2SRAM_constraint_template") { + index_1("0.0080,0.0288,0.0616,0.1072,0.1920,0.3496,0.5952"); + index_2("0.0080,0.0288,0.0616,0.1072,0.1920,0.3496,0.5952"); + values ("0.7396,0.7221,0.6947,0.6557,0.5726,0.4359,0.2250",\ +"0.7477,0.7301,0.7027,0.6637,0.5807,0.4440,0.2330",\ +"0.7567,0.7391,0.7117,0.6727,0.5897,0.4530,0.2420",\ +"0.7698,0.7522,0.7249,0.6858,0.6028,0.4661,0.2552",\ +"0.7941,0.7765,0.7492,0.7101,0.6271,0.4904,0.2795",\ +"0.8246,0.8070,0.7797,0.7406,0.6576,0.5209,0.3100",\ +"0.9061,0.8885,0.8611,0.8221,0.7391,0.6024,0.3914"); + } + } + } + + pin(A_BIST_EN) { + direction : input ; + capacitance : 0.00387999 ; + max_transition : "1" ; + related_power_pin : VDD; + related_ground_pin : VSS; + internal_power() { + rise_power("scalar") { + values (0); + } + fall_power("scalar") { + values (0); + } + } + } + +bus(A_BIST_ADDR) { + bus_type : A_9_0; + direction : input ; + capacitance : 0.0129586 ; + pin(A_BIST_ADDR[0]) { + capacitance : 0.0058687 ; + } + pin(A_BIST_ADDR[1]) { + capacitance : 0.00807137 ; + } + pin(A_BIST_ADDR[2]) { + capacitance : 0.0112051 ; + } + pin(A_BIST_ADDR[3]) { + capacitance : 0.00709524 ; + } + pin(A_BIST_ADDR[4]) { + capacitance : 0.00648778 ; + } + pin(A_BIST_ADDR[5]) { + capacitance : 0.011209 ; + } + pin(A_BIST_ADDR[6]) { + capacitance : 0.0140441 ; + } + pin(A_BIST_ADDR[7]) { + capacitance : 0.0111199 ; + } + pin(A_BIST_ADDR[8]) { + capacitance : 0.00957807 ; + } + max_transition : "0.5952" ; + pin(A_BIST_ADDR[9:0]) { + related_power_pin : VDD; + related_ground_pin : VSS; + internal_power() { + when : "A_BIST_MEN"; + rise_power("scalar"){ + values (0.0011); + } + fall_power("scalar"){ + values (0.0188); + } + } + internal_power() { + when : "!A_BIST_MEN"; + rise_power("scalar"){ + values (0.0058); + } + fall_power("scalar"){ + values (0.0107); + } + } + } + timing() { + timing_type : setup_rising; + related_pin : "A_BIST_CLK"; + when : "((A_BIST_WEN | A_BIST_REN)& A_BIST_MEN)" + sdf_cond : "A_BIST_RW_ACCESS" + + rise_constraint("SIG2SRAM_constraint_template") { + index_1("0.0080,0.0288,0.0616,0.1072,0.1920,0.3496,0.5952"); + index_2("0.0080,0.0288,0.0616,0.1072,0.1920,0.3496,0.5952"); + values ("-0.7371,-0.7176,-0.6863,-0.6434,-0.5652,-0.4168,-0.1980",\ +"-0.7566,-0.7371,-0.7059,-0.6629,-0.5848,-0.4363,-0.2137",\ +"-0.7879,-0.7645,-0.7332,-0.6902,-0.6121,-0.4637,-0.2449",\ +"-0.8309,-0.8074,-0.7762,-0.7332,-0.6551,-0.5066,-0.2879",\ +"-0.9051,-0.8895,-0.8543,-0.8113,-0.7332,-0.5887,-0.3660",\ +"-1.0418,-1.0262,-0.9949,-0.9480,-0.8699,-0.7293,-0.5027",\ +"-1.2684,-1.2449,-1.2176,-1.1707,-1.0965,-0.9480,-0.7293"); + } + + fall_constraint("SIG2SRAM_constraint_template") { + index_1("0.0080,0.0288,0.0616,0.1072,0.1920,0.3496,0.5952"); + index_2("0.0080,0.0288,0.0616,0.1072,0.1920,0.3496,0.5952"); + values ("-0.5926,-0.5730,-0.5418,-0.4988,-0.4246,-0.2879,-0.0730",\ +"-0.6121,-0.5926,-0.5613,-0.5223,-0.4441,-0.3074,-0.0887",\ +"-0.6395,-0.6199,-0.5926,-0.5496,-0.4715,-0.3348,-0.1160",\ +"-0.6863,-0.6668,-0.6355,-0.5965,-0.5184,-0.3777,-0.1590",\ +"-0.7605,-0.7410,-0.7137,-0.6746,-0.5926,-0.4559,-0.2410",\ +"-0.9012,-0.8816,-0.8504,-0.8113,-0.7332,-0.5926,-0.3895",\ +"-1.1238,-1.1043,-1.0769,-1.0379,-0.9559,-0.8191,-0.6004"); + } + } + + + timing() { + timing_type : hold_rising; + related_pin : "A_BIST_CLK"; + when : "((A_BIST_WEN | A_BIST_REN)& A_BIST_MEN)" + sdf_cond : "A_BIST_RW_ACCESS" + + rise_constraint("SIG2SRAM_constraint_template") { + index_1("0.0080,0.0288,0.0616,0.1072,0.1920,0.3496,0.5952"); + index_2("0.0080,0.0288,0.0616,0.1072,0.1920,0.3496,0.5952"); + values ("0.8488,0.8293,0.7980,0.7551,0.6730,0.5285,0.3098",\ +"0.8684,0.8488,0.8176,0.7746,0.6926,0.5480,0.3254",\ +"0.8996,0.8801,0.8449,0.8020,0.7238,0.5754,0.3527",\ +"0.9426,0.9191,0.8918,0.8488,0.7668,0.6223,0.3996",\ +"1.0168,1.0012,0.9699,0.9230,0.8449,0.7004,0.4777",\ +"1.1574,1.1379,1.1105,1.0598,0.9816,0.8371,0.6184",\ +"1.3801,1.3605,1.3254,1.2980,1.2043,1.0637,0.8371"); + } + + fall_constraint("SIG2SRAM_constraint_template") { + index_1("0.0080,0.0288,0.0616,0.1072,0.1920,0.3496,0.5952"); + index_2("0.0080,0.0288,0.0616,0.1072,0.1920,0.3496,0.5952"); + values ("0.6965,0.6770,0.6496,0.6066,0.5246,0.3918,0.1730",\ +"0.7160,0.6965,0.6652,0.6262,0.5441,0.4113,0.1965",\ +"0.7473,0.7277,0.6965,0.6535,0.5754,0.4426,0.2238",\ +"0.7863,0.7707,0.7395,0.7004,0.6223,0.4855,0.2629",\ +"0.8684,0.8449,0.8176,0.7785,0.7004,0.5637,0.3449",\ +"1.0051,0.9855,0.9855,0.9113,0.8332,0.7004,0.4895",\ +"1.2277,1.2082,1.1809,1.1379,1.0598,0.9230,0.7004"); + } + } +} +pin(A_BIST_WEN) { + direction : input ; + capacitance : 0.00313551 ; + max_transition : "0.5952" ; + related_power_pin : VDD; + related_ground_pin : VSS; + internal_power() { + when : "A_BIST_MEN"; + rise_power("scalar"){ + values (0.0065); + } + fall_power("scalar"){ + values (0.0066); + } + } + internal_power() { + when : "!A_BIST_MEN"; + rise_power("scalar"){ + values (0.0128); + } + fall_power("scalar"){ + values (0.0293); + } + } + timing() { + timing_type : setup_rising; + related_pin : "A_BIST_CLK"; + when : "A_BIST_MEN" + sdf_cond : "A_BIST_MEN" + + rise_constraint("SIG2SRAM_constraint_template") { + index_1("0.0080,0.0288,0.0616,0.1072,0.1920,0.3496,0.5952"); + index_2("0.0080,0.0288,0.0616,0.1072,0.1920,0.3496,0.5952"); + values ("0.3137,0.3332,0.3605,0.4035,0.4816,0.6223,0.8488",\ +"0.2980,0.3176,0.3410,0.3840,0.4660,0.6027,0.8293",\ +"0.2629,0.2824,0.3098,0.3527,0.4348,0.5754,0.7980",\ +"0.2199,0.2395,0.2668,0.3098,0.3918,0.5324,0.7590",\ +"0.1418,0.1613,0.1887,0.2316,0.3137,0.4348,0.6730",\ +"0.0012,0.0207,0.0520,0.0910,0.1730,0.3098,0.5285",\ +"-0.2215,-0.2020,-0.1746,-0.1277,-0.0496,0.0910,0.3098"); + } + + fall_constraint("SIG2SRAM_constraint_template") { + index_1("0.0080,0.0288,0.0616,0.1072,0.1920,0.3496,0.5952"); + index_2("0.0080,0.0288,0.0616,0.1072,0.1920,0.3496,0.5952"); + values ("0.4504,0.4699,0.4973,0.5324,0.6027,0.7355,0.9699",\ +"0.4309,0.4504,0.4777,0.5129,0.5910,0.7160,0.9504",\ +"0.3996,0.4191,0.4465,0.4816,0.5520,0.6848,0.9191",\ +"0.3605,0.3762,0.4035,0.4387,0.5168,0.6418,0.8723",\ +"0.2785,0.2980,0.3215,0.3605,0.4348,0.5637,0.7980",\ +"0.1379,0.1574,0.1809,0.2199,0.2980,0.4309,0.6457",\ +"-0.0809,-0.0613,-0.0340,0.0051,0.0832,0.2160,0.4191"); + } + } + + + timing() { + timing_type : hold_rising; + related_pin : "A_BIST_CLK"; + when : "A_BIST_MEN" + sdf_cond : "A_BIST_MEN" + + rise_constraint("SIG2SRAM_constraint_template") { + index_1("0.0080,0.0288,0.0616,0.1072,0.1920,0.3496,0.5952"); + index_2("0.0080,0.0288,0.0616,0.1072,0.1920,0.3496,0.5952"); + values ("0.3723,0.3527,0.3215,0.2785,0.1965,0.0559,-0.1668",\ +"0.3918,0.3723,0.3449,0.2980,0.2160,0.0754,-0.1473",\ +"0.4152,0.3996,0.3684,0.3254,0.2434,0.1066,-0.1199",\ +"0.4621,0.4465,0.4152,0.3723,0.2863,0.1496,-0.0730",\ +"0.5324,0.5207,0.4895,0.4465,0.3645,0.2199,0.0051",\ +"0.6770,0.6535,0.6301,0.5832,0.5090,0.3605,0.1418",\ +"0.9035,0.8879,0.8566,0.8137,0.7316,0.5871,0.3684"); + } + + fall_constraint("SIG2SRAM_constraint_template") { + index_1("0.0080,0.0288,0.0616,0.1072,0.1920,0.3496,0.5952"); + index_2("0.0080,0.0288,0.0616,0.1072,0.1920,0.3496,0.5952"); + values ("0.3762,0.3566,0.3293,0.2863,0.2043,0.0676,-0.1434",\ +"0.3957,0.3762,0.3488,0.3059,0.2238,0.0871,-0.1199",\ +"0.4230,0.4035,0.3723,0.3332,0.2512,0.1184,-0.0965",\ +"0.4660,0.4465,0.4191,0.3762,0.2941,0.1613,-0.0496",\ +"0.5324,0.5168,0.4973,0.4543,0.3723,0.2316,0.0285",\ +"0.6809,0.6613,0.6340,0.5910,0.5129,0.3645,0.1652",\ +"0.9113,0.8918,0.8605,0.8176,0.7395,0.5988,0.3879"); + } + } + } +pin(A_BIST_REN) { + direction : input ; + capacitance : 0.00381144 ; + max_transition : "0.5952" ; + related_power_pin : VDD; + related_ground_pin : VSS; + internal_power() { + when : "A_BIST_MEN"; + rise_power("scalar"){ + values (0.0060); + } + fall_power("scalar"){ + values (0.0027); + } + } + internal_power() { + when : "!A_BIST_MEN"; + rise_power("scalar"){ + values (0.0013); + } + fall_power("scalar"){ + values (0.0021); + } + } + timing() { + timing_type : setup_rising; + related_pin : "A_BIST_CLK"; + when : "A_BIST_MEN" + sdf_cond : "A_BIST_MEN" + + rise_constraint("SIG2SRAM_constraint_template") { + index_1("0.0080,0.0288,0.0616,0.1072,0.1920,0.3496,0.5952"); + index_2("0.0080,0.0288,0.0616,0.1072,0.1920,0.3496,0.5952"); + values ("-0.0770,-0.0574,-0.0262,0.0168,0.0949,0.2355,0.4582",\ +"-0.0965,-0.0770,-0.0457,-0.0027,0.0754,0.2160,0.4387",\ +"-0.1199,-0.1004,-0.0730,-0.0262,0.0520,0.1887,0.4113",\ +"-0.1590,-0.1434,-0.1160,-0.0730,0.0051,0.1457,0.3645",\ +"-0.2449,-0.2254,-0.1941,-0.1473,-0.0770,0.0676,0.2863",\ +"-0.3816,-0.3699,-0.3387,-0.2801,-0.2215,-0.0770,0.1457",\ +"-0.6121,-0.5926,-0.5613,-0.5145,-0.4363,-0.2996,-0.0730"); + } + + fall_constraint("SIG2SRAM_constraint_template") { + index_1("0.0080,0.0288,0.0616,0.1072,0.1920,0.3496,0.5952"); + index_2("0.0080,0.0288,0.0616,0.1072,0.1920,0.3496,0.5952"); + values ("0.1262,0.1457,0.1691,0.2121,0.2824,0.4191,0.6457",\ +"0.1105,0.1262,0.1496,0.1887,0.2629,0.3996,0.6262",\ +"0.0793,0.0949,0.1223,0.1652,0.2395,0.3684,0.5949",\ +"0.0363,0.0559,0.0793,0.1223,0.2004,0.3410,0.5520",\ +"-0.0457,-0.0262,0.0012,0.0441,0.1301,0.2629,0.4738",\ +"-0.1902,-0.1746,-0.1434,-0.1043,-0.0184,0.1223,0.3332",\ +"-0.4129,-0.3934,-0.3660,-0.3230,-0.2449,-0.1043,0.1105"); + } + } + + + timing() { + timing_type : hold_rising; + related_pin : "A_BIST_CLK"; + when : "A_BIST_MEN" + sdf_cond : "A_BIST_MEN" + + rise_constraint("SIG2SRAM_constraint_template") { + index_1("0.0080,0.0288,0.0616,0.1072,0.1920,0.3496,0.5952"); + index_2("0.0080,0.0288,0.0616,0.1072,0.1920,0.3496,0.5952"); + values ("0.4113,0.3918,0.3645,0.3176,0.2395,0.0988,-0.1238",\ +"0.4309,0.4113,0.3840,0.3371,0.2590,0.1184,-0.1043",\ +"0.4582,0.4387,0.4113,0.3645,0.2824,0.1457,-0.0770",\ +"0.5051,0.4816,0.4543,0.4074,0.3293,0.1887,-0.0340",\ +"0.5715,0.5598,0.5324,0.4895,0.4035,0.2512,0.0441",\ +"0.7043,0.7004,0.6730,0.6262,0.5402,0.3957,0.1809",\ +"0.9387,0.9270,0.8957,0.8527,0.7746,0.6262,0.4074"); + } + + fall_constraint("SIG2SRAM_constraint_template") { + index_1("0.0080,0.0288,0.0616,0.1072,0.1920,0.3496,0.5952"); + index_2("0.0080,0.0288,0.0616,0.1072,0.1920,0.3496,0.5952"); + values ("0.4152,0.3918,0.3645,0.3215,0.2395,0.1027,-0.1082",\ +"0.4309,0.4113,0.3801,0.3410,0.2590,0.1223,-0.0926",\ +"0.4582,0.4387,0.4074,0.3684,0.2863,0.1496,-0.0613",\ +"0.5012,0.4816,0.4504,0.4074,0.3293,0.1887,-0.0145",\ +"0.5715,0.5559,0.5285,0.4816,0.3996,0.2512,0.0598",\ +"0.7160,0.7004,0.6691,0.6262,0.5520,0.4035,0.2004",\ +"0.9387,0.9191,0.8957,0.8488,0.7707,0.6262,0.4113"); + } + } + } +pin(A_BIST_MEN) { + direction : input ; + capacitance : 0.00300347 ; + max_transition : "0.5952" ; + related_power_pin : VDD; + related_ground_pin : VSS; + internal_power() { + rise_power("scalar"){ + values (0.0060); + } + fall_power("scalar"){ + values (0.0099); + } + } + timing() { + timing_type : setup_rising; + related_pin : "A_BIST_CLK"; + + rise_constraint("SIG2SRAM_constraint_template") { + index_1("0.0080,0.0288,0.0616,0.1072,0.1920,0.3496,0.5952"); + index_2("0.0080,0.0288,0.0616,0.1072,0.1920,0.3496,0.5952"); + values ("0.3215,0.3449,0.3684,0.4113,0.4895,0.6301,0.8527",\ +"0.3059,0.3254,0.3527,0.3957,0.4738,0.6145,0.8371",\ +"0.2746,0.2941,0.3215,0.3645,0.4426,0.5871,0.8059",\ +"0.2316,0.2512,0.2785,0.3215,0.3996,0.5402,0.7629",\ +"0.1496,0.1730,0.1965,0.2395,0.3215,0.4660,0.6848",\ +"0.0090,0.0285,0.0598,0.1027,0.1809,0.3176,0.5402",\ +"-0.2098,-0.1902,-0.1668,-0.1199,-0.0418,0.0988,0.3137"); + } + + fall_constraint("SIG2SRAM_constraint_template") { + index_1("0.0080,0.0288,0.0616,0.1072,0.1920,0.3496,0.5952"); + index_2("0.0080,0.0288,0.0616,0.1072,0.1920,0.3496,0.5952"); + values ("0.4582,0.4738,0.5012,0.5363,0.6145,0.7395,0.9738",\ +"0.4387,0.4543,0.4816,0.5207,0.5910,0.7199,0.9582",\ +"0.4035,0.4230,0.4504,0.4855,0.5637,0.6887,0.9230",\ +"0.3645,0.3840,0.4074,0.4465,0.5285,0.6496,0.8840",\ +"0.2824,0.3020,0.3254,0.3645,0.4465,0.5715,0.7980",\ +"0.1418,0.1613,0.1887,0.2238,0.3020,0.4309,0.6496",\ +"-0.0770,-0.0574,-0.0301,0.0090,0.0910,0.2238,0.4191"); + } + } + + + timing() { + timing_type : hold_rising; + related_pin : "A_BIST_CLK"; + + rise_constraint("SIG2SRAM_constraint_template") { + index_1("0.0080,0.0288,0.0616,0.1072,0.1920,0.3496,0.5952"); + index_2("0.0080,0.0288,0.0616,0.1072,0.1920,0.3496,0.5952"); + values ("0.3762,0.3605,0.3293,0.2863,0.2043,0.0637,-0.1629",\ +"0.3996,0.3801,0.3488,0.3020,0.2238,0.0832,-0.1395",\ +"0.4230,0.4074,0.3723,0.3293,0.2473,0.1105,-0.1121",\ +"0.4621,0.4465,0.4152,0.3762,0.2941,0.1535,-0.0691",\ +"0.5441,0.5285,0.4973,0.4465,0.3684,0.2316,0.0090",\ +"0.6848,0.6652,0.6301,0.5910,0.5129,0.3605,0.1496",\ +"0.9074,0.8918,0.8566,0.8215,0.7395,0.5910,0.3723"); + } + + fall_constraint("SIG2SRAM_constraint_template") { + index_1("0.0080,0.0288,0.0616,0.1072,0.1920,0.3496,0.5952"); + index_2("0.0080,0.0288,0.0616,0.1072,0.1920,0.3496,0.5952"); + values ("0.3762,0.3605,0.3332,0.2863,0.2043,0.0715,-0.1395",\ +"0.3996,0.3762,0.3488,0.3059,0.2238,0.0910,-0.1199",\ +"0.4270,0.4035,0.3762,0.3332,0.2512,0.1184,-0.0965",\ +"0.4699,0.4504,0.4191,0.3762,0.2941,0.1613,-0.0496",\ +"0.5441,0.5285,0.4973,0.4543,0.3762,0.2355,0.0324",\ +"0.6770,0.6613,0.6340,0.5949,0.5207,0.3762,0.1652",\ +"0.9074,0.8918,0.8605,0.8176,0.7395,0.6027,0.3918"); + } + } + } +bus(A_BIST_BM) { + bus_type : D_15_0; + direction : input ; + capacitance : 0.00347781 ; + max_transition : "0.5952" ; + pin(A_BIST_BM[15:0]) { + related_power_pin : VDD; + related_ground_pin : VSS; + internal_power() { + when : "A_BIST_MEN"; + rise_power("scalar"){ + values (0.0368); + } + fall_power("scalar"){ + values (0.0200); + } + } + internal_power() { + when : "!A_BIST_MEN"; + rise_power("scalar"){ + values (0.0452); + } + fall_power("scalar"){ + values (0.0145); + } + } + } + timing() { + timing_type : setup_rising; + related_pin : "A_BIST_CLK"; + when : "(A_BIST_WEN & A_BIST_MEN)" + sdf_cond : "A_BIST_RW_ACCESS" + + rise_constraint("SIG2SRAM_constraint_template") { + index_1("0.0080,0.0288,0.0616,0.1072,0.1920,0.3496,0.5952"); + index_2("0.0080,0.0288,0.0616,0.1072,0.1920,0.3496,0.5952"); + values ("-0.6982,-0.6787,-0.6533,-0.6104,-0.5293,-0.3838,-0.1611",\ +"-0.7063,-0.6867,-0.6613,-0.6184,-0.5373,-0.3918,-0.1692",\ +"-0.7153,-0.6957,-0.6704,-0.6274,-0.5463,-0.4008,-0.1782",\ +"-0.7284,-0.7089,-0.6835,-0.6405,-0.5595,-0.4140,-0.1913",\ +"-0.7527,-0.7332,-0.7078,-0.6648,-0.5838,-0.4383,-0.2156",\ +"-0.7832,-0.7637,-0.7383,-0.6953,-0.6143,-0.4688,-0.2461",\ +"-0.8647,-0.8451,-0.8198,-0.7768,-0.6957,-0.5502,-0.3276"); + } + + fall_constraint("SIG2SRAM_constraint_template") { + index_1("0.0080,0.0288,0.0616,0.1072,0.1920,0.3496,0.5952"); + index_2("0.0080,0.0288,0.0616,0.1072,0.1920,0.3496,0.5952"); + values ("-0.6357,-0.6182,-0.5908,-0.5518,-0.4688,-0.3330,-0.1211",\ +"-0.6438,-0.6262,-0.5988,-0.5598,-0.4768,-0.3410,-0.1291",\ +"-0.6528,-0.6352,-0.6079,-0.5688,-0.4858,-0.3500,-0.1381",\ +"-0.6659,-0.6484,-0.6210,-0.5819,-0.4989,-0.3632,-0.1513",\ +"-0.6902,-0.6726,-0.6453,-0.6062,-0.5232,-0.3875,-0.1756",\ +"-0.7207,-0.7032,-0.6758,-0.6367,-0.5537,-0.4180,-0.2061",\ +"-0.8022,-0.7846,-0.7573,-0.7182,-0.6352,-0.4994,-0.2875"); + } + } + + + timing() { + timing_type : hold_rising; + related_pin : "A_BIST_CLK"; + when : "(A_BIST_WEN & A_BIST_MEN)" + sdf_cond : "A_BIST_RW_ACCESS" + + rise_constraint("SIG2SRAM_constraint_template") { + index_1("0.0080,0.0288,0.0616,0.1072,0.1920,0.3496,0.5952"); + index_2("0.0080,0.0288,0.0616,0.1072,0.1920,0.3496,0.5952"); + values ("0.8139,0.7924,0.7680,0.7250,0.6449,0.4984,0.2758",\ +"0.8219,0.8004,0.7760,0.7330,0.6529,0.5065,0.2838",\ +"0.8309,0.8094,0.7850,0.7420,0.6619,0.5155,0.2928",\ +"0.8440,0.8226,0.7982,0.7552,0.6751,0.5286,0.3060",\ +"0.8683,0.8468,0.8224,0.7795,0.6994,0.5529,0.3302",\ +"0.8988,0.8773,0.8529,0.8100,0.7299,0.5834,0.3607",\ +"0.9803,0.9588,0.9344,0.8914,0.8113,0.6649,0.4422"); + } + + fall_constraint("SIG2SRAM_constraint_template") { + index_1("0.0080,0.0288,0.0616,0.1072,0.1920,0.3496,0.5952"); + index_2("0.0080,0.0288,0.0616,0.1072,0.1920,0.3496,0.5952"); + values ("0.7396,0.7221,0.6947,0.6557,0.5726,0.4359,0.2250",\ +"0.7477,0.7301,0.7027,0.6637,0.5807,0.4440,0.2330",\ +"0.7567,0.7391,0.7117,0.6727,0.5897,0.4530,0.2420",\ +"0.7698,0.7522,0.7249,0.6858,0.6028,0.4661,0.2552",\ +"0.7941,0.7765,0.7492,0.7101,0.6271,0.4904,0.2795",\ +"0.8246,0.8070,0.7797,0.7406,0.6576,0.5209,0.3100",\ +"0.9061,0.8885,0.8611,0.8221,0.7391,0.6024,0.3914"); + } + } +} + pin(A_BIST_CLK) { + direction : input; + capacitance : 0.00378957; + max_transition : "0.5952"; + clock : "true" ; + pin_func_type : active_rising ; + + timing () { + timing_type : "min_pulse_width"; + related_pin : "A_BIST_CLK"; + rise_constraint("CLKTRAN_constraint_template") { + index_1("0.008,0.5952"); + values("0.4,0.4"); + } + } + + related_power_pin : VDD; + related_ground_pin : VSS; + + internal_power() { + when : "!A_BIST_MEN & !A_BIST_WEN & !A_BIST_REN"; + rise_power("scalar"){ + values (0); + } + fall_power("scalar"){ + values (0); + } + } + internal_power() { + when : "!A_BIST_MEN & A_BIST_WEN & !A_BIST_REN"; + rise_power("scalar"){ + values (0.5660); + } + fall_power("scalar"){ + values (0); + } + } + internal_power() { + when : "A_BIST_MEN & A_BIST_WEN & !A_BIST_REN"; + rise_power("scalar"){ + values (25.9369); + } + fall_power("scalar"){ + values (0); + } + } + internal_power() { + when : "A_BIST_MEN & A_BIST_WEN & A_BIST_REN"; + rise_power("scalar"){ + values (26.9678); + } + fall_power("scalar"){ + values (0); + } + } + internal_power() { + when : "A_BIST_MEN & !A_BIST_WEN & A_BIST_REN"; + rise_power("scalar"){ + values (20.0971); + } + fall_power("scalar"){ + values (0); + } + } + internal_power() { + when : "!A_BIST_MEN & !A_BIST_WEN & A_BIST_REN"; + rise_power("scalar"){ + values (0.3586); + } + fall_power("scalar"){ + values (0); + } + } + internal_power() { + when : "!A_BIST_MEN & A_BIST_WEN & A_BIST_REN"; + rise_power("scalar"){ + values (0.7302); + } + fall_power("scalar"){ + values (0); + } + } + internal_power() { + when : "A_BIST_MEN & !A_BIST_WEN & !A_BIST_REN"; + rise_power("scalar"){ + values (0); + } + fall_power("scalar"){ + values (0); + } + } + } + bus(A_BIST_DIN) { + bus_type : D_15_0; + direction : input ; + capacitance : 0.00396073 ; + memory_write() { + address : A_BIST_ADDR ; + clocked_on : A_BIST_CLK; + } + + max_transition : "0.5952" ; + pin(A_BIST_DIN[15:0]) { + related_power_pin : VDD; + related_ground_pin : VSS; + internal_power() { + when : "A_BIST_MEN"; + rise_power("scalar"){ + values (0.0368); + } + fall_power("scalar"){ + values (0.0200); + } + } + internal_power() { + when : "!A_BIST_MEN"; + rise_power("scalar"){ + values (0.0452); + } + fall_power("scalar"){ + values (0.0145); + } + } + } + timing() { + timing_type : setup_rising; + related_pin : "A_BIST_CLK"; + when : "(A_BIST_WEN & A_BIST_MEN)"; + sdf_cond : "A_BIST_W_ACCESS"; + + rise_constraint("SIG2SRAM_constraint_template") { + index_1("0.0080,0.0288,0.0616,0.1072,0.1920,0.3496,0.5952"); + index_2("0.0080,0.0288,0.0616,0.1072,0.1920,0.3496,0.5952"); + values ("-0.6982,-0.6787,-0.6533,-0.6104,-0.5293,-0.3838,-0.1611",\ +"-0.7063,-0.6867,-0.6613,-0.6184,-0.5373,-0.3918,-0.1692",\ +"-0.7153,-0.6957,-0.6704,-0.6274,-0.5463,-0.4008,-0.1782",\ +"-0.7284,-0.7089,-0.6835,-0.6405,-0.5595,-0.4140,-0.1913",\ +"-0.7527,-0.7332,-0.7078,-0.6648,-0.5838,-0.4383,-0.2156",\ +"-0.7832,-0.7637,-0.7383,-0.6953,-0.6143,-0.4688,-0.2461",\ +"-0.8647,-0.8451,-0.8198,-0.7768,-0.6957,-0.5502,-0.3276"); + } + + fall_constraint("SIG2SRAM_constraint_template") { + index_1("0.0080,0.0288,0.0616,0.1072,0.1920,0.3496,0.5952"); + index_2("0.0080,0.0288,0.0616,0.1072,0.1920,0.3496,0.5952"); + values ("-0.6357,-0.6182,-0.5908,-0.5518,-0.4688,-0.3330,-0.1211",\ +"-0.6438,-0.6262,-0.5988,-0.5598,-0.4768,-0.3410,-0.1291",\ +"-0.6528,-0.6352,-0.6079,-0.5688,-0.4858,-0.3500,-0.1381",\ +"-0.6659,-0.6484,-0.6210,-0.5819,-0.4989,-0.3632,-0.1513",\ +"-0.6902,-0.6726,-0.6453,-0.6062,-0.5232,-0.3875,-0.1756",\ +"-0.7207,-0.7032,-0.6758,-0.6367,-0.5537,-0.4180,-0.2061",\ +"-0.8022,-0.7846,-0.7573,-0.7182,-0.6352,-0.4994,-0.2875"); + } + } + + timing() { + timing_type : hold_rising; + related_pin : "A_BIST_CLK"; + when : "(A_BIST_WEN & A_BIST_MEN)"; + sdf_cond : "A_BIST_W_ACCESS"; + + rise_constraint("SIG2SRAM_constraint_template") { + index_1("0.0080,0.0288,0.0616,0.1072,0.1920,0.3496,0.5952"); + index_2("0.0080,0.0288,0.0616,0.1072,0.1920,0.3496,0.5952"); + values ("0.8139,0.7924,0.7680,0.7250,0.6449,0.4984,0.2758",\ +"0.8219,0.8004,0.7760,0.7330,0.6529,0.5065,0.2838",\ +"0.8309,0.8094,0.7850,0.7420,0.6619,0.5155,0.2928",\ +"0.8440,0.8226,0.7982,0.7552,0.6751,0.5286,0.3060",\ +"0.8683,0.8468,0.8224,0.7795,0.6994,0.5529,0.3302",\ +"0.8988,0.8773,0.8529,0.8100,0.7299,0.5834,0.3607",\ +"0.9803,0.9588,0.9344,0.8914,0.8113,0.6649,0.4422"); + } + + fall_constraint("SIG2SRAM_constraint_template") { + index_1("0.0080,0.0288,0.0616,0.1072,0.1920,0.3496,0.5952"); + index_2("0.0080,0.0288,0.0616,0.1072,0.1920,0.3496,0.5952"); + values ("0.7396,0.7221,0.6947,0.6557,0.5726,0.4359,0.2250",\ +"0.7477,0.7301,0.7027,0.6637,0.5807,0.4440,0.2330",\ +"0.7567,0.7391,0.7117,0.6727,0.5897,0.4530,0.2420",\ +"0.7698,0.7522,0.7249,0.6858,0.6028,0.4661,0.2552",\ +"0.7941,0.7765,0.7492,0.7101,0.6271,0.4904,0.2795",\ +"0.8246,0.8070,0.7797,0.7406,0.6576,0.5209,0.3100",\ +"0.9061,0.8885,0.8611,0.8221,0.7391,0.6024,0.3914"); + } + } + } + +bus(A_DOUT) { + + bus_type : D_15_0; + direction : output ; + capacitance : 0 ; + max_capacitance : 0.064 ; + memory_read() { + address : A_ADDR ; + } + pin(A_DOUT[15:0]) { + related_power_pin : VDD; + related_ground_pin : VSS; + internal_power() { + rise_power("scalar") { + values (0); + } + fall_power("scalar") { + values (0); + } + } + } + timing() { + related_pin : "A_CLK"; + timing_type : rising_edge ; + timing_sense : non_unate ; + + cell_rise(SIG2SRAM_delay_template) { + index_1("0.0080,0.0288,0.0616,0.1072,0.1920,0.3496,0.5952"); + index_2("0.0008,0.0014,0.0051,0.0100,0.0339,0.0640"); + values ("7.2051,7.2084,7.2206,7.2346,7.2871,7.3450",\ +"7.2205,7.2239,7.2360,7.2500,7.3025,7.3604",\ +"7.2268,7.2302,7.2424,7.2563,7.3089,7.3667",\ +"7.2475,7.2509,7.2630,7.2770,7.3296,7.3874",\ +"7.2650,7.2683,7.2805,7.2944,7.3470,7.4048",\ +"7.3007,7.3041,7.3163,7.3302,7.3828,7.4406",\ +"7.3711,7.3745,7.3866,7.4006,7.4531,7.5110"); + } + cell_fall(SIG2SRAM_delay_template) { + index_1("0.0080,0.0288,0.0616,0.1072,0.1920,0.3496,0.5952"); + index_2("0.0008,0.0014,0.0051,0.0100,0.0339,0.0640"); + values ("7.0953,7.0975,7.1076,7.1192,7.1626,7.2064",\ +"7.1108,7.1129,7.1230,7.1347,7.1780,7.2218",\ +"7.1171,7.1193,7.1293,7.1410,7.1843,7.2282",\ +"7.1378,7.1400,7.1500,7.1617,7.2050,7.2489",\ +"7.1552,7.1574,7.1674,7.1791,7.2225,7.2663",\ +"7.1910,7.1932,7.2032,7.2149,7.2582,7.3021",\ +"7.2614,7.2635,7.2736,7.2853,7.3286,7.3724"); + } + + rise_transition(SRAM_load_template) { + index_1("0.0008,0.0014,0.0051,0.0100,0.0339,0.0640"); + values ("0.0560,0.0583,0.0696,0.0816,0.1519,0.2335"); + } + fall_transition(SRAM_load_template) { + index_1("0.0008,0.0014,0.0051,0.0100,0.0339,0.0640"); + values ("0.0428,0.0445,0.0538,0.0658,0.1181,0.1751"); + } + } +} + pin(B_DLY) { + direction : input ; + capacitance : 0.00387999 ; + max_transition : "1" ; + related_power_pin : VDD; + related_ground_pin : VSS; + internal_power() { + rise_power("scalar") { + values (0); + } + fall_power("scalar") { + values (0); + } + } + } + +bus(B_ADDR) { + bus_type : A_9_0; + direction : input ; + capacitance : 0.0129586 ; + pin(B_ADDR[0]) { + capacitance : 0.00588404 ; + } + pin(B_ADDR[1]) { + capacitance : 0.0080425 ; + } + pin(B_ADDR[2]) { + capacitance : 0.0112051 ; + } + pin(B_ADDR[3]) { + capacitance : 0.00706428 ; + } + pin(B_ADDR[4]) { + capacitance : 0.00656149 ; + } + pin(B_ADDR[5]) { + capacitance : 0.0111839 ; + } + pin(B_ADDR[6]) { + capacitance : 0.0140236 ; + } + pin(B_ADDR[7]) { + capacitance : 0.0111118 ; + } + pin(B_ADDR[8]) { + capacitance : 0.00954392 ; + } + max_transition : "0.5952" ; + pin(B_ADDR[9:0]) { + related_power_pin : VDD; + related_ground_pin : VSS; + internal_power() { + when : "B_MEN"; + rise_power("scalar"){ + values (0.0011); + } + fall_power("scalar"){ + values (0.0188); + } + } + internal_power() { + when : "!B_MEN"; + rise_power("scalar"){ + values (0.0058); + } + fall_power("scalar"){ + values (0.0107); + } + } + } + timing() { + timing_type : setup_rising; + related_pin : "B_CLK"; + when : "((B_WEN | B_REN)& B_MEN)" + sdf_cond : "B_RW_ACCESS" + + rise_constraint("SIG2SRAM_constraint_template") { + index_1("0.0080,0.0288,0.0616,0.1072,0.1920,0.3496,0.5952"); + index_2("0.0080,0.0288,0.0616,0.1072,0.1920,0.3496,0.5952"); + values ("-0.7371,-0.7176,-0.6863,-0.6434,-0.5652,-0.4168,-0.1980",\ +"-0.7566,-0.7371,-0.7059,-0.6629,-0.5848,-0.4363,-0.2137",\ +"-0.7879,-0.7645,-0.7332,-0.6902,-0.6121,-0.4637,-0.2449",\ +"-0.8309,-0.8074,-0.7762,-0.7332,-0.6551,-0.5066,-0.2879",\ +"-0.9051,-0.8895,-0.8543,-0.8113,-0.7332,-0.5887,-0.3660",\ +"-1.0418,-1.0262,-0.9949,-0.9480,-0.8699,-0.7293,-0.5027",\ +"-1.2684,-1.2449,-1.2176,-1.1707,-1.0965,-0.9480,-0.7293"); + } + + fall_constraint("SIG2SRAM_constraint_template") { + index_1("0.0080,0.0288,0.0616,0.1072,0.1920,0.3496,0.5952"); + index_2("0.0080,0.0288,0.0616,0.1072,0.1920,0.3496,0.5952"); + values ("-0.5926,-0.5730,-0.5418,-0.4988,-0.4246,-0.2879,-0.0730",\ +"-0.6121,-0.5926,-0.5613,-0.5223,-0.4441,-0.3074,-0.0887",\ +"-0.6395,-0.6199,-0.5926,-0.5496,-0.4715,-0.3348,-0.1160",\ +"-0.6863,-0.6668,-0.6355,-0.5965,-0.5184,-0.3777,-0.1590",\ +"-0.7605,-0.7410,-0.7137,-0.6746,-0.5926,-0.4559,-0.2410",\ +"-0.9012,-0.8816,-0.8504,-0.8113,-0.7332,-0.5926,-0.3895",\ +"-1.1238,-1.1043,-1.0769,-1.0379,-0.9559,-0.8191,-0.6004"); + } + } + + + timing() { + timing_type : hold_rising; + related_pin : "B_CLK"; + when : "((B_WEN | B_REN)& B_MEN)" + sdf_cond : "B_RW_ACCESS" + + rise_constraint("SIG2SRAM_constraint_template") { + index_1("0.0080,0.0288,0.0616,0.1072,0.1920,0.3496,0.5952"); + index_2("0.0080,0.0288,0.0616,0.1072,0.1920,0.3496,0.5952"); + values ("0.8488,0.8293,0.7980,0.7551,0.6730,0.5285,0.3098",\ +"0.8684,0.8488,0.8176,0.7746,0.6926,0.5480,0.3254",\ +"0.8996,0.8801,0.8449,0.8020,0.7238,0.5754,0.3527",\ +"0.9426,0.9191,0.8918,0.8488,0.7668,0.6223,0.3996",\ +"1.0168,1.0012,0.9699,0.9230,0.8449,0.7004,0.4777",\ +"1.1574,1.1379,1.1105,1.0598,0.9816,0.8371,0.6184",\ +"1.3801,1.3605,1.3254,1.2980,1.2043,1.0637,0.8371"); + } + + fall_constraint("SIG2SRAM_constraint_template") { + index_1("0.0080,0.0288,0.0616,0.1072,0.1920,0.3496,0.5952"); + index_2("0.0080,0.0288,0.0616,0.1072,0.1920,0.3496,0.5952"); + values ("0.6965,0.6770,0.6496,0.6066,0.5246,0.3918,0.1730",\ +"0.7160,0.6965,0.6652,0.6262,0.5441,0.4113,0.1965",\ +"0.7473,0.7277,0.6965,0.6535,0.5754,0.4426,0.2238",\ +"0.7863,0.7707,0.7395,0.7004,0.6223,0.4855,0.2629",\ +"0.8684,0.8449,0.8176,0.7785,0.7004,0.5637,0.3449",\ +"1.0051,0.9855,0.9855,0.9113,0.8332,0.7004,0.4895",\ +"1.2277,1.2082,1.1809,1.1379,1.0598,0.9230,0.7004"); + } + } +} +pin(B_WEN) { + direction : input ; + capacitance : 0.00313551 ; + max_transition : "0.5952" ; + related_power_pin : VDD; + related_ground_pin : VSS; + internal_power() { + when : "B_MEN"; + rise_power("scalar"){ + values (0.0065); + } + fall_power("scalar"){ + values (0.0066); + } + } + internal_power() { + when : "!B_MEN"; + rise_power("scalar"){ + values (0.0128); + } + fall_power("scalar"){ + values (0.0293); + } + } + timing() { + timing_type : setup_rising; + related_pin : "B_CLK"; + when : "B_MEN" + sdf_cond : "B_MEN" + + rise_constraint("SIG2SRAM_constraint_template") { + index_1("0.0080,0.0288,0.0616,0.1072,0.1920,0.3496,0.5952"); + index_2("0.0080,0.0288,0.0616,0.1072,0.1920,0.3496,0.5952"); + values ("0.3137,0.3332,0.3605,0.4035,0.4816,0.6223,0.8488",\ +"0.2980,0.3176,0.3410,0.3840,0.4660,0.6027,0.8293",\ +"0.2629,0.2824,0.3098,0.3527,0.4348,0.5754,0.7980",\ +"0.2199,0.2395,0.2668,0.3098,0.3918,0.5324,0.7590",\ +"0.1418,0.1613,0.1887,0.2316,0.3137,0.4348,0.6730",\ +"0.0012,0.0207,0.0520,0.0910,0.1730,0.3098,0.5285",\ +"-0.2215,-0.2020,-0.1746,-0.1277,-0.0496,0.0910,0.3098"); + } + + fall_constraint("SIG2SRAM_constraint_template") { + index_1("0.0080,0.0288,0.0616,0.1072,0.1920,0.3496,0.5952"); + index_2("0.0080,0.0288,0.0616,0.1072,0.1920,0.3496,0.5952"); + values ("0.4504,0.4699,0.4973,0.5324,0.6027,0.7355,0.9699",\ +"0.4309,0.4504,0.4777,0.5129,0.5910,0.7160,0.9504",\ +"0.3996,0.4191,0.4465,0.4816,0.5520,0.6848,0.9191",\ +"0.3605,0.3762,0.4035,0.4387,0.5168,0.6418,0.8723",\ +"0.2785,0.2980,0.3215,0.3605,0.4348,0.5637,0.7980",\ +"0.1379,0.1574,0.1809,0.2199,0.2980,0.4309,0.6457",\ +"-0.0809,-0.0613,-0.0340,0.0051,0.0832,0.2160,0.4191"); + } + } + + + timing() { + timing_type : hold_rising; + related_pin : "B_CLK"; + when : "B_MEN" + sdf_cond : "B_MEN" + + rise_constraint("SIG2SRAM_constraint_template") { + index_1("0.0080,0.0288,0.0616,0.1072,0.1920,0.3496,0.5952"); + index_2("0.0080,0.0288,0.0616,0.1072,0.1920,0.3496,0.5952"); + values ("0.3723,0.3527,0.3215,0.2785,0.1965,0.0559,-0.1668",\ +"0.3918,0.3723,0.3449,0.2980,0.2160,0.0754,-0.1473",\ +"0.4152,0.3996,0.3684,0.3254,0.2434,0.1066,-0.1199",\ +"0.4621,0.4465,0.4152,0.3723,0.2863,0.1496,-0.0730",\ +"0.5324,0.5207,0.4895,0.4465,0.3645,0.2199,0.0051",\ +"0.6770,0.6535,0.6301,0.5832,0.5090,0.3605,0.1418",\ +"0.9035,0.8879,0.8566,0.8137,0.7316,0.5871,0.3684"); + } + + fall_constraint("SIG2SRAM_constraint_template") { + index_1("0.0080,0.0288,0.0616,0.1072,0.1920,0.3496,0.5952"); + index_2("0.0080,0.0288,0.0616,0.1072,0.1920,0.3496,0.5952"); + values ("0.3762,0.3566,0.3293,0.2863,0.2043,0.0676,-0.1434",\ +"0.3957,0.3762,0.3488,0.3059,0.2238,0.0871,-0.1199",\ +"0.4230,0.4035,0.3723,0.3332,0.2512,0.1184,-0.0965",\ +"0.4660,0.4465,0.4191,0.3762,0.2941,0.1613,-0.0496",\ +"0.5324,0.5168,0.4973,0.4543,0.3723,0.2316,0.0285",\ +"0.6809,0.6613,0.6340,0.5910,0.5129,0.3645,0.1652",\ +"0.9113,0.8918,0.8605,0.8176,0.7395,0.5988,0.3879"); + } + } + } +pin(B_REN) { + direction : input ; + capacitance : 0.00381144 ; + max_transition : "0.5952" ; + related_power_pin : VDD; + related_ground_pin : VSS; + internal_power() { + when : "B_MEN"; + rise_power("scalar"){ + values (0.0060); + } + fall_power("scalar"){ + values (0.0027); + } + } + internal_power() { + when : "!B_MEN"; + rise_power("scalar"){ + values (0.0013); + } + fall_power("scalar"){ + values (0.0021); + } + } + timing() { + timing_type : setup_rising; + related_pin : "B_CLK"; + when : "B_MEN" + sdf_cond : "B_MEN" + + rise_constraint("SIG2SRAM_constraint_template") { + index_1("0.0080,0.0288,0.0616,0.1072,0.1920,0.3496,0.5952"); + index_2("0.0080,0.0288,0.0616,0.1072,0.1920,0.3496,0.5952"); + values ("-0.0770,-0.0574,-0.0262,0.0168,0.0949,0.2355,0.4582",\ +"-0.0965,-0.0770,-0.0457,-0.0027,0.0754,0.2160,0.4387",\ +"-0.1199,-0.1004,-0.0730,-0.0262,0.0520,0.1887,0.4113",\ +"-0.1590,-0.1434,-0.1160,-0.0730,0.0051,0.1457,0.3645",\ +"-0.2449,-0.2254,-0.1941,-0.1473,-0.0770,0.0676,0.2863",\ +"-0.3816,-0.3699,-0.3387,-0.2801,-0.2215,-0.0770,0.1457",\ +"-0.6121,-0.5926,-0.5613,-0.5145,-0.4363,-0.2996,-0.0730"); + } + + fall_constraint("SIG2SRAM_constraint_template") { + index_1("0.0080,0.0288,0.0616,0.1072,0.1920,0.3496,0.5952"); + index_2("0.0080,0.0288,0.0616,0.1072,0.1920,0.3496,0.5952"); + values ("0.1262,0.1457,0.1691,0.2121,0.2824,0.4191,0.6457",\ +"0.1105,0.1262,0.1496,0.1887,0.2629,0.3996,0.6262",\ +"0.0793,0.0949,0.1223,0.1652,0.2395,0.3684,0.5949",\ +"0.0363,0.0559,0.0793,0.1223,0.2004,0.3410,0.5520",\ +"-0.0457,-0.0262,0.0012,0.0441,0.1301,0.2629,0.4738",\ +"-0.1902,-0.1746,-0.1434,-0.1043,-0.0184,0.1223,0.3332",\ +"-0.4129,-0.3934,-0.3660,-0.3230,-0.2449,-0.1043,0.1105"); + } + } + + + timing() { + timing_type : hold_rising; + related_pin : "B_CLK"; + when : "B_MEN" + sdf_cond : "B_MEN" + + rise_constraint("SIG2SRAM_constraint_template") { + index_1("0.0080,0.0288,0.0616,0.1072,0.1920,0.3496,0.5952"); + index_2("0.0080,0.0288,0.0616,0.1072,0.1920,0.3496,0.5952"); + values ("0.4113,0.3918,0.3645,0.3176,0.2395,0.0988,-0.1238",\ +"0.4309,0.4113,0.3840,0.3371,0.2590,0.1184,-0.1043",\ +"0.4582,0.4387,0.4113,0.3645,0.2824,0.1457,-0.0770",\ +"0.5051,0.4816,0.4543,0.4074,0.3293,0.1887,-0.0340",\ +"0.5715,0.5598,0.5324,0.4895,0.4035,0.2512,0.0441",\ +"0.7043,0.7004,0.6730,0.6262,0.5402,0.3957,0.1809",\ +"0.9387,0.9270,0.8957,0.8527,0.7746,0.6262,0.4074"); + } + + fall_constraint("SIG2SRAM_constraint_template") { + index_1("0.0080,0.0288,0.0616,0.1072,0.1920,0.3496,0.5952"); + index_2("0.0080,0.0288,0.0616,0.1072,0.1920,0.3496,0.5952"); + values ("0.4152,0.3918,0.3645,0.3215,0.2395,0.1027,-0.1082",\ +"0.4309,0.4113,0.3801,0.3410,0.2590,0.1223,-0.0926",\ +"0.4582,0.4387,0.4074,0.3684,0.2863,0.1496,-0.0613",\ +"0.5012,0.4816,0.4504,0.4074,0.3293,0.1887,-0.0145",\ +"0.5715,0.5559,0.5285,0.4816,0.3996,0.2512,0.0598",\ +"0.7160,0.7004,0.6691,0.6262,0.5520,0.4035,0.2004",\ +"0.9387,0.9191,0.8957,0.8488,0.7707,0.6262,0.4113"); + } + } + } +pin(B_MEN) { + direction : input ; + capacitance : 0.00300347 ; + max_transition : "0.5952" ; + related_power_pin : VDD; + related_ground_pin : VSS; + internal_power() { + rise_power("scalar"){ + values (0.0060); + } + fall_power("scalar"){ + values (0.0099); + } + } + timing() { + timing_type : setup_rising; + related_pin : "B_CLK"; + + rise_constraint("SIG2SRAM_constraint_template") { + index_1("0.0080,0.0288,0.0616,0.1072,0.1920,0.3496,0.5952"); + index_2("0.0080,0.0288,0.0616,0.1072,0.1920,0.3496,0.5952"); + values ("0.3215,0.3449,0.3684,0.4113,0.4895,0.6301,0.8527",\ +"0.3059,0.3254,0.3527,0.3957,0.4738,0.6145,0.8371",\ +"0.2746,0.2941,0.3215,0.3645,0.4426,0.5871,0.8059",\ +"0.2316,0.2512,0.2785,0.3215,0.3996,0.5402,0.7629",\ +"0.1496,0.1730,0.1965,0.2395,0.3215,0.4660,0.6848",\ +"0.0090,0.0285,0.0598,0.1027,0.1809,0.3176,0.5402",\ +"-0.2098,-0.1902,-0.1668,-0.1199,-0.0418,0.0988,0.3137"); + } + + fall_constraint("SIG2SRAM_constraint_template") { + index_1("0.0080,0.0288,0.0616,0.1072,0.1920,0.3496,0.5952"); + index_2("0.0080,0.0288,0.0616,0.1072,0.1920,0.3496,0.5952"); + values ("0.4582,0.4738,0.5012,0.5363,0.6145,0.7395,0.9738",\ +"0.4387,0.4543,0.4816,0.5207,0.5910,0.7199,0.9582",\ +"0.4035,0.4230,0.4504,0.4855,0.5637,0.6887,0.9230",\ +"0.3645,0.3840,0.4074,0.4465,0.5285,0.6496,0.8840",\ +"0.2824,0.3020,0.3254,0.3645,0.4465,0.5715,0.7980",\ +"0.1418,0.1613,0.1887,0.2238,0.3020,0.4309,0.6496",\ +"-0.0770,-0.0574,-0.0301,0.0090,0.0910,0.2238,0.4191"); + } + } + + + timing() { + timing_type : hold_rising; + related_pin : "B_CLK"; + + rise_constraint("SIG2SRAM_constraint_template") { + index_1("0.0080,0.0288,0.0616,0.1072,0.1920,0.3496,0.5952"); + index_2("0.0080,0.0288,0.0616,0.1072,0.1920,0.3496,0.5952"); + values ("0.3762,0.3605,0.3293,0.2863,0.2043,0.0637,-0.1629",\ +"0.3996,0.3801,0.3488,0.3020,0.2238,0.0832,-0.1395",\ +"0.4230,0.4074,0.3723,0.3293,0.2473,0.1105,-0.1121",\ +"0.4621,0.4465,0.4152,0.3762,0.2941,0.1535,-0.0691",\ +"0.5441,0.5285,0.4973,0.4465,0.3684,0.2316,0.0090",\ +"0.6848,0.6652,0.6301,0.5910,0.5129,0.3605,0.1496",\ +"0.9074,0.8918,0.8566,0.8215,0.7395,0.5910,0.3723"); + } + + fall_constraint("SIG2SRAM_constraint_template") { + index_1("0.0080,0.0288,0.0616,0.1072,0.1920,0.3496,0.5952"); + index_2("0.0080,0.0288,0.0616,0.1072,0.1920,0.3496,0.5952"); + values ("0.3762,0.3605,0.3332,0.2863,0.2043,0.0715,-0.1395",\ +"0.3996,0.3762,0.3488,0.3059,0.2238,0.0910,-0.1199",\ +"0.4270,0.4035,0.3762,0.3332,0.2512,0.1184,-0.0965",\ +"0.4699,0.4504,0.4191,0.3762,0.2941,0.1613,-0.0496",\ +"0.5441,0.5285,0.4973,0.4543,0.3762,0.2355,0.0324",\ +"0.6770,0.6613,0.6340,0.5949,0.5207,0.3762,0.1652",\ +"0.9074,0.8918,0.8605,0.8176,0.7395,0.6027,0.3918"); + } + } + } +bus(B_BM) { + bus_type : D_15_0; + direction : input ; + capacitance : 0.00293202 ; + max_transition : "0.5952" ; + pin(B_BM[15:0]) { + related_power_pin : VDD; + related_ground_pin : VSS; + internal_power() { + when : "B_MEN"; + rise_power("scalar"){ + values (0.0368); + } + fall_power("scalar"){ + values (0.0200); + } + } + internal_power() { + when : "!B_MEN"; + rise_power("scalar"){ + values (0.0452); + } + fall_power("scalar"){ + values (0.0145); + } + } + } + timing() { + timing_type : setup_rising; + related_pin : "B_CLK"; + when : "(B_WEN & B_MEN)" + sdf_cond : "B_RW_ACCESS" + + rise_constraint("SIG2SRAM_constraint_template") { + index_1("0.0080,0.0288,0.0616,0.1072,0.1920,0.3496,0.5952"); + index_2("0.0080,0.0288,0.0616,0.1072,0.1920,0.3496,0.5952"); + values ("-0.6982,-0.6787,-0.6533,-0.6104,-0.5293,-0.3838,-0.1611",\ +"-0.7063,-0.6867,-0.6613,-0.6184,-0.5373,-0.3918,-0.1692",\ +"-0.7153,-0.6957,-0.6704,-0.6274,-0.5463,-0.4008,-0.1782",\ +"-0.7284,-0.7089,-0.6835,-0.6405,-0.5595,-0.4140,-0.1913",\ +"-0.7527,-0.7332,-0.7078,-0.6648,-0.5838,-0.4383,-0.2156",\ +"-0.7832,-0.7637,-0.7383,-0.6953,-0.6143,-0.4688,-0.2461",\ +"-0.8647,-0.8451,-0.8198,-0.7768,-0.6957,-0.5502,-0.3276"); + } + + fall_constraint("SIG2SRAM_constraint_template") { + index_1("0.0080,0.0288,0.0616,0.1072,0.1920,0.3496,0.5952"); + index_2("0.0080,0.0288,0.0616,0.1072,0.1920,0.3496,0.5952"); + values ("-0.6357,-0.6182,-0.5908,-0.5518,-0.4688,-0.3330,-0.1211",\ +"-0.6438,-0.6262,-0.5988,-0.5598,-0.4768,-0.3410,-0.1291",\ +"-0.6528,-0.6352,-0.6079,-0.5688,-0.4858,-0.3500,-0.1381",\ +"-0.6659,-0.6484,-0.6210,-0.5819,-0.4989,-0.3632,-0.1513",\ +"-0.6902,-0.6726,-0.6453,-0.6062,-0.5232,-0.3875,-0.1756",\ +"-0.7207,-0.7032,-0.6758,-0.6367,-0.5537,-0.4180,-0.2061",\ +"-0.8022,-0.7846,-0.7573,-0.7182,-0.6352,-0.4994,-0.2875"); + } + } + + + timing() { + timing_type : hold_rising; + related_pin : "B_CLK"; + when : "(B_WEN & B_MEN)" + sdf_cond : "B_RW_ACCESS" + + rise_constraint("SIG2SRAM_constraint_template") { + index_1("0.0080,0.0288,0.0616,0.1072,0.1920,0.3496,0.5952"); + index_2("0.0080,0.0288,0.0616,0.1072,0.1920,0.3496,0.5952"); + values ("0.8139,0.7924,0.7680,0.7250,0.6449,0.4984,0.2758",\ +"0.8219,0.8004,0.7760,0.7330,0.6529,0.5065,0.2838",\ +"0.8309,0.8094,0.7850,0.7420,0.6619,0.5155,0.2928",\ +"0.8440,0.8226,0.7982,0.7552,0.6751,0.5286,0.3060",\ +"0.8683,0.8468,0.8224,0.7795,0.6994,0.5529,0.3302",\ +"0.8988,0.8773,0.8529,0.8100,0.7299,0.5834,0.3607",\ +"0.9803,0.9588,0.9344,0.8914,0.8113,0.6649,0.4422"); + } + + fall_constraint("SIG2SRAM_constraint_template") { + index_1("0.0080,0.0288,0.0616,0.1072,0.1920,0.3496,0.5952"); + index_2("0.0080,0.0288,0.0616,0.1072,0.1920,0.3496,0.5952"); + values ("0.7396,0.7221,0.6947,0.6557,0.5726,0.4359,0.2250",\ +"0.7477,0.7301,0.7027,0.6637,0.5807,0.4440,0.2330",\ +"0.7567,0.7391,0.7117,0.6727,0.5897,0.4530,0.2420",\ +"0.7698,0.7522,0.7249,0.6858,0.6028,0.4661,0.2552",\ +"0.7941,0.7765,0.7492,0.7101,0.6271,0.4904,0.2795",\ +"0.8246,0.8070,0.7797,0.7406,0.6576,0.5209,0.3100",\ +"0.9061,0.8885,0.8611,0.8221,0.7391,0.6024,0.3914"); + } + } +} + pin(B_CLK) { + direction : input; + capacitance : 0.00378957; + max_transition : "0.5952"; + clock : "true" ; + pin_func_type : active_rising ; + + timing () { + timing_type : "min_pulse_width"; + related_pin : "B_CLK"; + rise_constraint("CLKTRAN_constraint_template") { + index_1("0.008,0.5952"); + values("0.4,0.4"); + } + } + + related_power_pin : VDD; + related_ground_pin : VSS; + + internal_power() { + when : "!B_MEN & !B_WEN & !B_REN"; + rise_power("scalar"){ + values (0); + } + fall_power("scalar"){ + values (0); + } + } + internal_power() { + when : "!B_MEN & B_WEN & !B_REN"; + rise_power("scalar"){ + values (0.5660); + } + fall_power("scalar"){ + values (0); + } + } + internal_power() { + when : "B_MEN & B_WEN & !B_REN"; + rise_power("scalar"){ + values (25.9369); + } + fall_power("scalar"){ + values (0); + } + } + internal_power() { + when : "B_MEN & B_WEN & B_REN"; + rise_power("scalar"){ + values (26.9678); + } + fall_power("scalar"){ + values (0); + } + } + internal_power() { + when : "B_MEN & !B_WEN & B_REN"; + rise_power("scalar"){ + values (20.0971); + } + fall_power("scalar"){ + values (0); + } + } + internal_power() { + when : "!B_MEN & !B_WEN & B_REN"; + rise_power("scalar"){ + values (0.3586); + } + fall_power("scalar"){ + values (0); + } + } + internal_power() { + when : "!B_MEN & B_WEN & B_REN"; + rise_power("scalar"){ + values (0.7302); + } + fall_power("scalar"){ + values (0); + } + } + internal_power() { + when : "B_MEN & !B_WEN & !B_REN"; + rise_power("scalar"){ + values (0); + } + fall_power("scalar"){ + values (0); + } + } + } + bus(B_DIN) { + bus_type : D_15_0; + direction : input ; + capacitance : 0.00460366 ; + memory_write() { + address : B_ADDR ; + clocked_on : B_CLK; + } + + max_transition : "0.5952" ; + pin(B_DIN[15:0]) { + related_power_pin : VDD; + related_ground_pin : VSS; + internal_power() { + when : "B_MEN"; + rise_power("scalar"){ + values (0.0368); + } + fall_power("scalar"){ + values (0.0200); + } + } + internal_power() { + when : "!B_MEN"; + rise_power("scalar"){ + values (0.0452); + } + fall_power("scalar"){ + values (0.0145); + } + } + } + timing() { + timing_type : setup_rising; + related_pin : "B_CLK"; + when : "(B_WEN & B_MEN)"; + sdf_cond : "B_W_ACCESS"; + + rise_constraint("SIG2SRAM_constraint_template") { + index_1("0.0080,0.0288,0.0616,0.1072,0.1920,0.3496,0.5952"); + index_2("0.0080,0.0288,0.0616,0.1072,0.1920,0.3496,0.5952"); + values ("-0.6982,-0.6787,-0.6533,-0.6104,-0.5293,-0.3838,-0.1611",\ +"-0.7063,-0.6867,-0.6613,-0.6184,-0.5373,-0.3918,-0.1692",\ +"-0.7153,-0.6957,-0.6704,-0.6274,-0.5463,-0.4008,-0.1782",\ +"-0.7284,-0.7089,-0.6835,-0.6405,-0.5595,-0.4140,-0.1913",\ +"-0.7527,-0.7332,-0.7078,-0.6648,-0.5838,-0.4383,-0.2156",\ +"-0.7832,-0.7637,-0.7383,-0.6953,-0.6143,-0.4688,-0.2461",\ +"-0.8647,-0.8451,-0.8198,-0.7768,-0.6957,-0.5502,-0.3276"); + } + + fall_constraint("SIG2SRAM_constraint_template") { + index_1("0.0080,0.0288,0.0616,0.1072,0.1920,0.3496,0.5952"); + index_2("0.0080,0.0288,0.0616,0.1072,0.1920,0.3496,0.5952"); + values ("-0.6357,-0.6182,-0.5908,-0.5518,-0.4688,-0.3330,-0.1211",\ +"-0.6438,-0.6262,-0.5988,-0.5598,-0.4768,-0.3410,-0.1291",\ +"-0.6528,-0.6352,-0.6079,-0.5688,-0.4858,-0.3500,-0.1381",\ +"-0.6659,-0.6484,-0.6210,-0.5819,-0.4989,-0.3632,-0.1513",\ +"-0.6902,-0.6726,-0.6453,-0.6062,-0.5232,-0.3875,-0.1756",\ +"-0.7207,-0.7032,-0.6758,-0.6367,-0.5537,-0.4180,-0.2061",\ +"-0.8022,-0.7846,-0.7573,-0.7182,-0.6352,-0.4994,-0.2875"); + } + } + + timing() { + timing_type : hold_rising; + related_pin : "B_CLK"; + when : "(B_WEN & B_MEN)"; + sdf_cond : "B_W_ACCESS"; + + rise_constraint("SIG2SRAM_constraint_template") { + index_1("0.0080,0.0288,0.0616,0.1072,0.1920,0.3496,0.5952"); + index_2("0.0080,0.0288,0.0616,0.1072,0.1920,0.3496,0.5952"); + values ("0.8139,0.7924,0.7680,0.7250,0.6449,0.4984,0.2758",\ +"0.8219,0.8004,0.7760,0.7330,0.6529,0.5065,0.2838",\ +"0.8309,0.8094,0.7850,0.7420,0.6619,0.5155,0.2928",\ +"0.8440,0.8226,0.7982,0.7552,0.6751,0.5286,0.3060",\ +"0.8683,0.8468,0.8224,0.7795,0.6994,0.5529,0.3302",\ +"0.8988,0.8773,0.8529,0.8100,0.7299,0.5834,0.3607",\ +"0.9803,0.9588,0.9344,0.8914,0.8113,0.6649,0.4422"); + } + + fall_constraint("SIG2SRAM_constraint_template") { + index_1("0.0080,0.0288,0.0616,0.1072,0.1920,0.3496,0.5952"); + index_2("0.0080,0.0288,0.0616,0.1072,0.1920,0.3496,0.5952"); + values ("0.7396,0.7221,0.6947,0.6557,0.5726,0.4359,0.2250",\ +"0.7477,0.7301,0.7027,0.6637,0.5807,0.4440,0.2330",\ +"0.7567,0.7391,0.7117,0.6727,0.5897,0.4530,0.2420",\ +"0.7698,0.7522,0.7249,0.6858,0.6028,0.4661,0.2552",\ +"0.7941,0.7765,0.7492,0.7101,0.6271,0.4904,0.2795",\ +"0.8246,0.8070,0.7797,0.7406,0.6576,0.5209,0.3100",\ +"0.9061,0.8885,0.8611,0.8221,0.7391,0.6024,0.3914"); + } + } + } + + pin(B_BIST_EN) { + direction : input ; + capacitance : 0.00387999 ; + max_transition : "1" ; + related_power_pin : VDD; + related_ground_pin : VSS; + internal_power() { + rise_power("scalar") { + values (0); + } + fall_power("scalar") { + values (0); + } + } + } + +bus(B_BIST_ADDR) { + bus_type : A_9_0; + direction : input ; + capacitance : 0.0129586 ; + pin(B_BIST_ADDR[0]) { + capacitance : 0.00588404 ; + } + pin(B_BIST_ADDR[1]) { + capacitance : 0.0080425 ; + } + pin(B_BIST_ADDR[2]) { + capacitance : 0.0112051 ; + } + pin(B_BIST_ADDR[3]) { + capacitance : 0.00706428 ; + } + pin(B_BIST_ADDR[4]) { + capacitance : 0.00656149 ; + } + pin(B_BIST_ADDR[5]) { + capacitance : 0.0111839 ; + } + pin(B_BIST_ADDR[6]) { + capacitance : 0.0140236 ; + } + pin(B_BIST_ADDR[7]) { + capacitance : 0.0111118 ; + } + pin(B_BIST_ADDR[8]) { + capacitance : 0.00954392 ; + } + max_transition : "0.5952" ; + pin(B_BIST_ADDR[9:0]) { + related_power_pin : VDD; + related_ground_pin : VSS; + internal_power() { + when : "B_BIST_MEN"; + rise_power("scalar"){ + values (0.0011); + } + fall_power("scalar"){ + values (0.0188); + } + } + internal_power() { + when : "!B_BIST_MEN"; + rise_power("scalar"){ + values (0.0058); + } + fall_power("scalar"){ + values (0.0107); + } + } + } + timing() { + timing_type : setup_rising; + related_pin : "B_BIST_CLK"; + when : "((B_BIST_WEN | B_BIST_REN)& B_BIST_MEN)" + sdf_cond : "B_BIST_RW_ACCESS" + + rise_constraint("SIG2SRAM_constraint_template") { + index_1("0.0080,0.0288,0.0616,0.1072,0.1920,0.3496,0.5952"); + index_2("0.0080,0.0288,0.0616,0.1072,0.1920,0.3496,0.5952"); + values ("-0.7371,-0.7176,-0.6863,-0.6434,-0.5652,-0.4168,-0.1980",\ +"-0.7566,-0.7371,-0.7059,-0.6629,-0.5848,-0.4363,-0.2137",\ +"-0.7879,-0.7645,-0.7332,-0.6902,-0.6121,-0.4637,-0.2449",\ +"-0.8309,-0.8074,-0.7762,-0.7332,-0.6551,-0.5066,-0.2879",\ +"-0.9051,-0.8895,-0.8543,-0.8113,-0.7332,-0.5887,-0.3660",\ +"-1.0418,-1.0262,-0.9949,-0.9480,-0.8699,-0.7293,-0.5027",\ +"-1.2684,-1.2449,-1.2176,-1.1707,-1.0965,-0.9480,-0.7293"); + } + + fall_constraint("SIG2SRAM_constraint_template") { + index_1("0.0080,0.0288,0.0616,0.1072,0.1920,0.3496,0.5952"); + index_2("0.0080,0.0288,0.0616,0.1072,0.1920,0.3496,0.5952"); + values ("-0.5926,-0.5730,-0.5418,-0.4988,-0.4246,-0.2879,-0.0730",\ +"-0.6121,-0.5926,-0.5613,-0.5223,-0.4441,-0.3074,-0.0887",\ +"-0.6395,-0.6199,-0.5926,-0.5496,-0.4715,-0.3348,-0.1160",\ +"-0.6863,-0.6668,-0.6355,-0.5965,-0.5184,-0.3777,-0.1590",\ +"-0.7605,-0.7410,-0.7137,-0.6746,-0.5926,-0.4559,-0.2410",\ +"-0.9012,-0.8816,-0.8504,-0.8113,-0.7332,-0.5926,-0.3895",\ +"-1.1238,-1.1043,-1.0769,-1.0379,-0.9559,-0.8191,-0.6004"); + } + } + + + timing() { + timing_type : hold_rising; + related_pin : "B_BIST_CLK"; + when : "((B_BIST_WEN | B_BIST_REN)& B_BIST_MEN)" + sdf_cond : "B_BIST_RW_ACCESS" + + rise_constraint("SIG2SRAM_constraint_template") { + index_1("0.0080,0.0288,0.0616,0.1072,0.1920,0.3496,0.5952"); + index_2("0.0080,0.0288,0.0616,0.1072,0.1920,0.3496,0.5952"); + values ("0.8488,0.8293,0.7980,0.7551,0.6730,0.5285,0.3098",\ +"0.8684,0.8488,0.8176,0.7746,0.6926,0.5480,0.3254",\ +"0.8996,0.8801,0.8449,0.8020,0.7238,0.5754,0.3527",\ +"0.9426,0.9191,0.8918,0.8488,0.7668,0.6223,0.3996",\ +"1.0168,1.0012,0.9699,0.9230,0.8449,0.7004,0.4777",\ +"1.1574,1.1379,1.1105,1.0598,0.9816,0.8371,0.6184",\ +"1.3801,1.3605,1.3254,1.2980,1.2043,1.0637,0.8371"); + } + + fall_constraint("SIG2SRAM_constraint_template") { + index_1("0.0080,0.0288,0.0616,0.1072,0.1920,0.3496,0.5952"); + index_2("0.0080,0.0288,0.0616,0.1072,0.1920,0.3496,0.5952"); + values ("0.6965,0.6770,0.6496,0.6066,0.5246,0.3918,0.1730",\ +"0.7160,0.6965,0.6652,0.6262,0.5441,0.4113,0.1965",\ +"0.7473,0.7277,0.6965,0.6535,0.5754,0.4426,0.2238",\ +"0.7863,0.7707,0.7395,0.7004,0.6223,0.4855,0.2629",\ +"0.8684,0.8449,0.8176,0.7785,0.7004,0.5637,0.3449",\ +"1.0051,0.9855,0.9855,0.9113,0.8332,0.7004,0.4895",\ +"1.2277,1.2082,1.1809,1.1379,1.0598,0.9230,0.7004"); + } + } +} +pin(B_BIST_WEN) { + direction : input ; + capacitance : 0.00313551 ; + max_transition : "0.5952" ; + related_power_pin : VDD; + related_ground_pin : VSS; + internal_power() { + when : "B_BIST_MEN"; + rise_power("scalar"){ + values (0.0065); + } + fall_power("scalar"){ + values (0.0066); + } + } + internal_power() { + when : "!B_BIST_MEN"; + rise_power("scalar"){ + values (0.0128); + } + fall_power("scalar"){ + values (0.0293); + } + } + timing() { + timing_type : setup_rising; + related_pin : "B_BIST_CLK"; + when : "B_BIST_MEN" + sdf_cond : "B_BIST_MEN" + + rise_constraint("SIG2SRAM_constraint_template") { + index_1("0.0080,0.0288,0.0616,0.1072,0.1920,0.3496,0.5952"); + index_2("0.0080,0.0288,0.0616,0.1072,0.1920,0.3496,0.5952"); + values ("0.3137,0.3332,0.3605,0.4035,0.4816,0.6223,0.8488",\ +"0.2980,0.3176,0.3410,0.3840,0.4660,0.6027,0.8293",\ +"0.2629,0.2824,0.3098,0.3527,0.4348,0.5754,0.7980",\ +"0.2199,0.2395,0.2668,0.3098,0.3918,0.5324,0.7590",\ +"0.1418,0.1613,0.1887,0.2316,0.3137,0.4348,0.6730",\ +"0.0012,0.0207,0.0520,0.0910,0.1730,0.3098,0.5285",\ +"-0.2215,-0.2020,-0.1746,-0.1277,-0.0496,0.0910,0.3098"); + } + + fall_constraint("SIG2SRAM_constraint_template") { + index_1("0.0080,0.0288,0.0616,0.1072,0.1920,0.3496,0.5952"); + index_2("0.0080,0.0288,0.0616,0.1072,0.1920,0.3496,0.5952"); + values ("0.4504,0.4699,0.4973,0.5324,0.6027,0.7355,0.9699",\ +"0.4309,0.4504,0.4777,0.5129,0.5910,0.7160,0.9504",\ +"0.3996,0.4191,0.4465,0.4816,0.5520,0.6848,0.9191",\ +"0.3605,0.3762,0.4035,0.4387,0.5168,0.6418,0.8723",\ +"0.2785,0.2980,0.3215,0.3605,0.4348,0.5637,0.7980",\ +"0.1379,0.1574,0.1809,0.2199,0.2980,0.4309,0.6457",\ +"-0.0809,-0.0613,-0.0340,0.0051,0.0832,0.2160,0.4191"); + } + } + + + timing() { + timing_type : hold_rising; + related_pin : "B_BIST_CLK"; + when : "B_BIST_MEN" + sdf_cond : "B_BIST_MEN" + + rise_constraint("SIG2SRAM_constraint_template") { + index_1("0.0080,0.0288,0.0616,0.1072,0.1920,0.3496,0.5952"); + index_2("0.0080,0.0288,0.0616,0.1072,0.1920,0.3496,0.5952"); + values ("0.3723,0.3527,0.3215,0.2785,0.1965,0.0559,-0.1668",\ +"0.3918,0.3723,0.3449,0.2980,0.2160,0.0754,-0.1473",\ +"0.4152,0.3996,0.3684,0.3254,0.2434,0.1066,-0.1199",\ +"0.4621,0.4465,0.4152,0.3723,0.2863,0.1496,-0.0730",\ +"0.5324,0.5207,0.4895,0.4465,0.3645,0.2199,0.0051",\ +"0.6770,0.6535,0.6301,0.5832,0.5090,0.3605,0.1418",\ +"0.9035,0.8879,0.8566,0.8137,0.7316,0.5871,0.3684"); + } + + fall_constraint("SIG2SRAM_constraint_template") { + index_1("0.0080,0.0288,0.0616,0.1072,0.1920,0.3496,0.5952"); + index_2("0.0080,0.0288,0.0616,0.1072,0.1920,0.3496,0.5952"); + values ("0.3762,0.3566,0.3293,0.2863,0.2043,0.0676,-0.1434",\ +"0.3957,0.3762,0.3488,0.3059,0.2238,0.0871,-0.1199",\ +"0.4230,0.4035,0.3723,0.3332,0.2512,0.1184,-0.0965",\ +"0.4660,0.4465,0.4191,0.3762,0.2941,0.1613,-0.0496",\ +"0.5324,0.5168,0.4973,0.4543,0.3723,0.2316,0.0285",\ +"0.6809,0.6613,0.6340,0.5910,0.5129,0.3645,0.1652",\ +"0.9113,0.8918,0.8605,0.8176,0.7395,0.5988,0.3879"); + } + } + } +pin(B_BIST_REN) { + direction : input ; + capacitance : 0.00381144 ; + max_transition : "0.5952" ; + related_power_pin : VDD; + related_ground_pin : VSS; + internal_power() { + when : "B_BIST_MEN"; + rise_power("scalar"){ + values (0.0060); + } + fall_power("scalar"){ + values (0.0027); + } + } + internal_power() { + when : "!B_BIST_MEN"; + rise_power("scalar"){ + values (0.0013); + } + fall_power("scalar"){ + values (0.0021); + } + } + timing() { + timing_type : setup_rising; + related_pin : "B_BIST_CLK"; + when : "B_BIST_MEN" + sdf_cond : "B_BIST_MEN" + + rise_constraint("SIG2SRAM_constraint_template") { + index_1("0.0080,0.0288,0.0616,0.1072,0.1920,0.3496,0.5952"); + index_2("0.0080,0.0288,0.0616,0.1072,0.1920,0.3496,0.5952"); + values ("-0.0770,-0.0574,-0.0262,0.0168,0.0949,0.2355,0.4582",\ +"-0.0965,-0.0770,-0.0457,-0.0027,0.0754,0.2160,0.4387",\ +"-0.1199,-0.1004,-0.0730,-0.0262,0.0520,0.1887,0.4113",\ +"-0.1590,-0.1434,-0.1160,-0.0730,0.0051,0.1457,0.3645",\ +"-0.2449,-0.2254,-0.1941,-0.1473,-0.0770,0.0676,0.2863",\ +"-0.3816,-0.3699,-0.3387,-0.2801,-0.2215,-0.0770,0.1457",\ +"-0.6121,-0.5926,-0.5613,-0.5145,-0.4363,-0.2996,-0.0730"); + } + + fall_constraint("SIG2SRAM_constraint_template") { + index_1("0.0080,0.0288,0.0616,0.1072,0.1920,0.3496,0.5952"); + index_2("0.0080,0.0288,0.0616,0.1072,0.1920,0.3496,0.5952"); + values ("0.1262,0.1457,0.1691,0.2121,0.2824,0.4191,0.6457",\ +"0.1105,0.1262,0.1496,0.1887,0.2629,0.3996,0.6262",\ +"0.0793,0.0949,0.1223,0.1652,0.2395,0.3684,0.5949",\ +"0.0363,0.0559,0.0793,0.1223,0.2004,0.3410,0.5520",\ +"-0.0457,-0.0262,0.0012,0.0441,0.1301,0.2629,0.4738",\ +"-0.1902,-0.1746,-0.1434,-0.1043,-0.0184,0.1223,0.3332",\ +"-0.4129,-0.3934,-0.3660,-0.3230,-0.2449,-0.1043,0.1105"); + } + } + + + timing() { + timing_type : hold_rising; + related_pin : "B_BIST_CLK"; + when : "B_BIST_MEN" + sdf_cond : "B_BIST_MEN" + + rise_constraint("SIG2SRAM_constraint_template") { + index_1("0.0080,0.0288,0.0616,0.1072,0.1920,0.3496,0.5952"); + index_2("0.0080,0.0288,0.0616,0.1072,0.1920,0.3496,0.5952"); + values ("0.4113,0.3918,0.3645,0.3176,0.2395,0.0988,-0.1238",\ +"0.4309,0.4113,0.3840,0.3371,0.2590,0.1184,-0.1043",\ +"0.4582,0.4387,0.4113,0.3645,0.2824,0.1457,-0.0770",\ +"0.5051,0.4816,0.4543,0.4074,0.3293,0.1887,-0.0340",\ +"0.5715,0.5598,0.5324,0.4895,0.4035,0.2512,0.0441",\ +"0.7043,0.7004,0.6730,0.6262,0.5402,0.3957,0.1809",\ +"0.9387,0.9270,0.8957,0.8527,0.7746,0.6262,0.4074"); + } + + fall_constraint("SIG2SRAM_constraint_template") { + index_1("0.0080,0.0288,0.0616,0.1072,0.1920,0.3496,0.5952"); + index_2("0.0080,0.0288,0.0616,0.1072,0.1920,0.3496,0.5952"); + values ("0.4152,0.3918,0.3645,0.3215,0.2395,0.1027,-0.1082",\ +"0.4309,0.4113,0.3801,0.3410,0.2590,0.1223,-0.0926",\ +"0.4582,0.4387,0.4074,0.3684,0.2863,0.1496,-0.0613",\ +"0.5012,0.4816,0.4504,0.4074,0.3293,0.1887,-0.0145",\ +"0.5715,0.5559,0.5285,0.4816,0.3996,0.2512,0.0598",\ +"0.7160,0.7004,0.6691,0.6262,0.5520,0.4035,0.2004",\ +"0.9387,0.9191,0.8957,0.8488,0.7707,0.6262,0.4113"); + } + } + } +pin(B_BIST_MEN) { + direction : input ; + capacitance : 0.00300347 ; + max_transition : "0.5952" ; + related_power_pin : VDD; + related_ground_pin : VSS; + internal_power() { + rise_power("scalar"){ + values (0.0060); + } + fall_power("scalar"){ + values (0.0099); + } + } + timing() { + timing_type : setup_rising; + related_pin : "B_BIST_CLK"; + + rise_constraint("SIG2SRAM_constraint_template") { + index_1("0.0080,0.0288,0.0616,0.1072,0.1920,0.3496,0.5952"); + index_2("0.0080,0.0288,0.0616,0.1072,0.1920,0.3496,0.5952"); + values ("0.3215,0.3449,0.3684,0.4113,0.4895,0.6301,0.8527",\ +"0.3059,0.3254,0.3527,0.3957,0.4738,0.6145,0.8371",\ +"0.2746,0.2941,0.3215,0.3645,0.4426,0.5871,0.8059",\ +"0.2316,0.2512,0.2785,0.3215,0.3996,0.5402,0.7629",\ +"0.1496,0.1730,0.1965,0.2395,0.3215,0.4660,0.6848",\ +"0.0090,0.0285,0.0598,0.1027,0.1809,0.3176,0.5402",\ +"-0.2098,-0.1902,-0.1668,-0.1199,-0.0418,0.0988,0.3137"); + } + + fall_constraint("SIG2SRAM_constraint_template") { + index_1("0.0080,0.0288,0.0616,0.1072,0.1920,0.3496,0.5952"); + index_2("0.0080,0.0288,0.0616,0.1072,0.1920,0.3496,0.5952"); + values ("0.4582,0.4738,0.5012,0.5363,0.6145,0.7395,0.9738",\ +"0.4387,0.4543,0.4816,0.5207,0.5910,0.7199,0.9582",\ +"0.4035,0.4230,0.4504,0.4855,0.5637,0.6887,0.9230",\ +"0.3645,0.3840,0.4074,0.4465,0.5285,0.6496,0.8840",\ +"0.2824,0.3020,0.3254,0.3645,0.4465,0.5715,0.7980",\ +"0.1418,0.1613,0.1887,0.2238,0.3020,0.4309,0.6496",\ +"-0.0770,-0.0574,-0.0301,0.0090,0.0910,0.2238,0.4191"); + } + } + + + timing() { + timing_type : hold_rising; + related_pin : "B_BIST_CLK"; + + rise_constraint("SIG2SRAM_constraint_template") { + index_1("0.0080,0.0288,0.0616,0.1072,0.1920,0.3496,0.5952"); + index_2("0.0080,0.0288,0.0616,0.1072,0.1920,0.3496,0.5952"); + values ("0.3762,0.3605,0.3293,0.2863,0.2043,0.0637,-0.1629",\ +"0.3996,0.3801,0.3488,0.3020,0.2238,0.0832,-0.1395",\ +"0.4230,0.4074,0.3723,0.3293,0.2473,0.1105,-0.1121",\ +"0.4621,0.4465,0.4152,0.3762,0.2941,0.1535,-0.0691",\ +"0.5441,0.5285,0.4973,0.4465,0.3684,0.2316,0.0090",\ +"0.6848,0.6652,0.6301,0.5910,0.5129,0.3605,0.1496",\ +"0.9074,0.8918,0.8566,0.8215,0.7395,0.5910,0.3723"); + } + + fall_constraint("SIG2SRAM_constraint_template") { + index_1("0.0080,0.0288,0.0616,0.1072,0.1920,0.3496,0.5952"); + index_2("0.0080,0.0288,0.0616,0.1072,0.1920,0.3496,0.5952"); + values ("0.3762,0.3605,0.3332,0.2863,0.2043,0.0715,-0.1395",\ +"0.3996,0.3762,0.3488,0.3059,0.2238,0.0910,-0.1199",\ +"0.4270,0.4035,0.3762,0.3332,0.2512,0.1184,-0.0965",\ +"0.4699,0.4504,0.4191,0.3762,0.2941,0.1613,-0.0496",\ +"0.5441,0.5285,0.4973,0.4543,0.3762,0.2355,0.0324",\ +"0.6770,0.6613,0.6340,0.5949,0.5207,0.3762,0.1652",\ +"0.9074,0.8918,0.8605,0.8176,0.7395,0.6027,0.3918"); + } + } + } +bus(B_BIST_BM) { + bus_type : D_15_0; + direction : input ; + capacitance : 0.00261869 ; + max_transition : "0.5952" ; + pin(B_BIST_BM[15:0]) { + related_power_pin : VDD; + related_ground_pin : VSS; + internal_power() { + when : "B_BIST_MEN"; + rise_power("scalar"){ + values (0.0368); + } + fall_power("scalar"){ + values (0.0200); + } + } + internal_power() { + when : "!B_BIST_MEN"; + rise_power("scalar"){ + values (0.0452); + } + fall_power("scalar"){ + values (0.0145); + } + } + } + timing() { + timing_type : setup_rising; + related_pin : "B_BIST_CLK"; + when : "(B_BIST_WEN & B_BIST_MEN)" + sdf_cond : "B_BIST_RW_ACCESS" + + rise_constraint("SIG2SRAM_constraint_template") { + index_1("0.0080,0.0288,0.0616,0.1072,0.1920,0.3496,0.5952"); + index_2("0.0080,0.0288,0.0616,0.1072,0.1920,0.3496,0.5952"); + values ("-0.6982,-0.6787,-0.6533,-0.6104,-0.5293,-0.3838,-0.1611",\ +"-0.7063,-0.6867,-0.6613,-0.6184,-0.5373,-0.3918,-0.1692",\ +"-0.7153,-0.6957,-0.6704,-0.6274,-0.5463,-0.4008,-0.1782",\ +"-0.7284,-0.7089,-0.6835,-0.6405,-0.5595,-0.4140,-0.1913",\ +"-0.7527,-0.7332,-0.7078,-0.6648,-0.5838,-0.4383,-0.2156",\ +"-0.7832,-0.7637,-0.7383,-0.6953,-0.6143,-0.4688,-0.2461",\ +"-0.8647,-0.8451,-0.8198,-0.7768,-0.6957,-0.5502,-0.3276"); + } + + fall_constraint("SIG2SRAM_constraint_template") { + index_1("0.0080,0.0288,0.0616,0.1072,0.1920,0.3496,0.5952"); + index_2("0.0080,0.0288,0.0616,0.1072,0.1920,0.3496,0.5952"); + values ("-0.6357,-0.6182,-0.5908,-0.5518,-0.4688,-0.3330,-0.1211",\ +"-0.6438,-0.6262,-0.5988,-0.5598,-0.4768,-0.3410,-0.1291",\ +"-0.6528,-0.6352,-0.6079,-0.5688,-0.4858,-0.3500,-0.1381",\ +"-0.6659,-0.6484,-0.6210,-0.5819,-0.4989,-0.3632,-0.1513",\ +"-0.6902,-0.6726,-0.6453,-0.6062,-0.5232,-0.3875,-0.1756",\ +"-0.7207,-0.7032,-0.6758,-0.6367,-0.5537,-0.4180,-0.2061",\ +"-0.8022,-0.7846,-0.7573,-0.7182,-0.6352,-0.4994,-0.2875"); + } + } + + + timing() { + timing_type : hold_rising; + related_pin : "B_BIST_CLK"; + when : "(B_BIST_WEN & B_BIST_MEN)" + sdf_cond : "B_BIST_RW_ACCESS" + + rise_constraint("SIG2SRAM_constraint_template") { + index_1("0.0080,0.0288,0.0616,0.1072,0.1920,0.3496,0.5952"); + index_2("0.0080,0.0288,0.0616,0.1072,0.1920,0.3496,0.5952"); + values ("0.8139,0.7924,0.7680,0.7250,0.6449,0.4984,0.2758",\ +"0.8219,0.8004,0.7760,0.7330,0.6529,0.5065,0.2838",\ +"0.8309,0.8094,0.7850,0.7420,0.6619,0.5155,0.2928",\ +"0.8440,0.8226,0.7982,0.7552,0.6751,0.5286,0.3060",\ +"0.8683,0.8468,0.8224,0.7795,0.6994,0.5529,0.3302",\ +"0.8988,0.8773,0.8529,0.8100,0.7299,0.5834,0.3607",\ +"0.9803,0.9588,0.9344,0.8914,0.8113,0.6649,0.4422"); + } + + fall_constraint("SIG2SRAM_constraint_template") { + index_1("0.0080,0.0288,0.0616,0.1072,0.1920,0.3496,0.5952"); + index_2("0.0080,0.0288,0.0616,0.1072,0.1920,0.3496,0.5952"); + values ("0.7396,0.7221,0.6947,0.6557,0.5726,0.4359,0.2250",\ +"0.7477,0.7301,0.7027,0.6637,0.5807,0.4440,0.2330",\ +"0.7567,0.7391,0.7117,0.6727,0.5897,0.4530,0.2420",\ +"0.7698,0.7522,0.7249,0.6858,0.6028,0.4661,0.2552",\ +"0.7941,0.7765,0.7492,0.7101,0.6271,0.4904,0.2795",\ +"0.8246,0.8070,0.7797,0.7406,0.6576,0.5209,0.3100",\ +"0.9061,0.8885,0.8611,0.8221,0.7391,0.6024,0.3914"); + } + } +} + pin(B_BIST_CLK) { + direction : input; + capacitance : 0.00378957; + max_transition : "0.5952"; + clock : "true" ; + pin_func_type : active_rising ; + + timing () { + timing_type : "min_pulse_width"; + related_pin : "B_BIST_CLK"; + rise_constraint("CLKTRAN_constraint_template") { + index_1("0.008,0.5952"); + values("0.4,0.4"); + } + } + + related_power_pin : VDD; + related_ground_pin : VSS; + + internal_power() { + when : "!B_BIST_MEN & !B_BIST_WEN & !B_BIST_REN"; + rise_power("scalar"){ + values (0); + } + fall_power("scalar"){ + values (0); + } + } + internal_power() { + when : "!B_BIST_MEN & B_BIST_WEN & !B_BIST_REN"; + rise_power("scalar"){ + values (0.5660); + } + fall_power("scalar"){ + values (0); + } + } + internal_power() { + when : "B_BIST_MEN & B_BIST_WEN & !B_BIST_REN"; + rise_power("scalar"){ + values (25.9369); + } + fall_power("scalar"){ + values (0); + } + } + internal_power() { + when : "B_BIST_MEN & B_BIST_WEN & B_BIST_REN"; + rise_power("scalar"){ + values (26.9678); + } + fall_power("scalar"){ + values (0); + } + } + internal_power() { + when : "B_BIST_MEN & !B_BIST_WEN & B_BIST_REN"; + rise_power("scalar"){ + values (20.0971); + } + fall_power("scalar"){ + values (0); + } + } + internal_power() { + when : "!B_BIST_MEN & !B_BIST_WEN & B_BIST_REN"; + rise_power("scalar"){ + values (0.3586); + } + fall_power("scalar"){ + values (0); + } + } + internal_power() { + when : "!B_BIST_MEN & B_BIST_WEN & B_BIST_REN"; + rise_power("scalar"){ + values (0.7302); + } + fall_power("scalar"){ + values (0); + } + } + internal_power() { + when : "B_BIST_MEN & !B_BIST_WEN & !B_BIST_REN"; + rise_power("scalar"){ + values (0); + } + fall_power("scalar"){ + values (0); + } + } + } + bus(B_BIST_DIN) { + bus_type : D_15_0; + direction : input ; + capacitance : 0.00416317 ; + memory_write() { + address : B_BIST_ADDR ; + clocked_on : B_BIST_CLK; + } + + max_transition : "0.5952" ; + pin(B_BIST_DIN[15:0]) { + related_power_pin : VDD; + related_ground_pin : VSS; + internal_power() { + when : "B_BIST_MEN"; + rise_power("scalar"){ + values (0.0368); + } + fall_power("scalar"){ + values (0.0200); + } + } + internal_power() { + when : "!B_BIST_MEN"; + rise_power("scalar"){ + values (0.0452); + } + fall_power("scalar"){ + values (0.0145); + } + } + } + timing() { + timing_type : setup_rising; + related_pin : "B_BIST_CLK"; + when : "(B_BIST_WEN & B_BIST_MEN)"; + sdf_cond : "B_BIST_W_ACCESS"; + + rise_constraint("SIG2SRAM_constraint_template") { + index_1("0.0080,0.0288,0.0616,0.1072,0.1920,0.3496,0.5952"); + index_2("0.0080,0.0288,0.0616,0.1072,0.1920,0.3496,0.5952"); + values ("-0.6982,-0.6787,-0.6533,-0.6104,-0.5293,-0.3838,-0.1611",\ +"-0.7063,-0.6867,-0.6613,-0.6184,-0.5373,-0.3918,-0.1692",\ +"-0.7153,-0.6957,-0.6704,-0.6274,-0.5463,-0.4008,-0.1782",\ +"-0.7284,-0.7089,-0.6835,-0.6405,-0.5595,-0.4140,-0.1913",\ +"-0.7527,-0.7332,-0.7078,-0.6648,-0.5838,-0.4383,-0.2156",\ +"-0.7832,-0.7637,-0.7383,-0.6953,-0.6143,-0.4688,-0.2461",\ +"-0.8647,-0.8451,-0.8198,-0.7768,-0.6957,-0.5502,-0.3276"); + } + + fall_constraint("SIG2SRAM_constraint_template") { + index_1("0.0080,0.0288,0.0616,0.1072,0.1920,0.3496,0.5952"); + index_2("0.0080,0.0288,0.0616,0.1072,0.1920,0.3496,0.5952"); + values ("-0.6357,-0.6182,-0.5908,-0.5518,-0.4688,-0.3330,-0.1211",\ +"-0.6438,-0.6262,-0.5988,-0.5598,-0.4768,-0.3410,-0.1291",\ +"-0.6528,-0.6352,-0.6079,-0.5688,-0.4858,-0.3500,-0.1381",\ +"-0.6659,-0.6484,-0.6210,-0.5819,-0.4989,-0.3632,-0.1513",\ +"-0.6902,-0.6726,-0.6453,-0.6062,-0.5232,-0.3875,-0.1756",\ +"-0.7207,-0.7032,-0.6758,-0.6367,-0.5537,-0.4180,-0.2061",\ +"-0.8022,-0.7846,-0.7573,-0.7182,-0.6352,-0.4994,-0.2875"); + } + } + + timing() { + timing_type : hold_rising; + related_pin : "B_BIST_CLK"; + when : "(B_BIST_WEN & B_BIST_MEN)"; + sdf_cond : "B_BIST_W_ACCESS"; + + rise_constraint("SIG2SRAM_constraint_template") { + index_1("0.0080,0.0288,0.0616,0.1072,0.1920,0.3496,0.5952"); + index_2("0.0080,0.0288,0.0616,0.1072,0.1920,0.3496,0.5952"); + values ("0.8139,0.7924,0.7680,0.7250,0.6449,0.4984,0.2758",\ +"0.8219,0.8004,0.7760,0.7330,0.6529,0.5065,0.2838",\ +"0.8309,0.8094,0.7850,0.7420,0.6619,0.5155,0.2928",\ +"0.8440,0.8226,0.7982,0.7552,0.6751,0.5286,0.3060",\ +"0.8683,0.8468,0.8224,0.7795,0.6994,0.5529,0.3302",\ +"0.8988,0.8773,0.8529,0.8100,0.7299,0.5834,0.3607",\ +"0.9803,0.9588,0.9344,0.8914,0.8113,0.6649,0.4422"); + } + + fall_constraint("SIG2SRAM_constraint_template") { + index_1("0.0080,0.0288,0.0616,0.1072,0.1920,0.3496,0.5952"); + index_2("0.0080,0.0288,0.0616,0.1072,0.1920,0.3496,0.5952"); + values ("0.7396,0.7221,0.6947,0.6557,0.5726,0.4359,0.2250",\ +"0.7477,0.7301,0.7027,0.6637,0.5807,0.4440,0.2330",\ +"0.7567,0.7391,0.7117,0.6727,0.5897,0.4530,0.2420",\ +"0.7698,0.7522,0.7249,0.6858,0.6028,0.4661,0.2552",\ +"0.7941,0.7765,0.7492,0.7101,0.6271,0.4904,0.2795",\ +"0.8246,0.8070,0.7797,0.7406,0.6576,0.5209,0.3100",\ +"0.9061,0.8885,0.8611,0.8221,0.7391,0.6024,0.3914"); + } + } + } + +bus(B_DOUT) { + + bus_type : D_15_0; + direction : output ; + capacitance : 0 ; + max_capacitance : 0.064 ; + memory_read() { + address : B_ADDR ; + } + pin(B_DOUT[15:0]) { + related_power_pin : VDD; + related_ground_pin : VSS; + internal_power() { + rise_power("scalar") { + values (0); + } + fall_power("scalar") { + values (0); + } + } + } + timing() { + related_pin : "B_CLK"; + timing_type : rising_edge ; + timing_sense : non_unate ; + + cell_rise(SIG2SRAM_delay_template) { + index_1("0.0080,0.0288,0.0616,0.1072,0.1920,0.3496,0.5952"); + index_2("0.0008,0.0014,0.0051,0.0100,0.0339,0.0640"); + values ("7.2051,7.2084,7.2206,7.2346,7.2871,7.3450",\ +"7.2205,7.2239,7.2360,7.2500,7.3025,7.3604",\ +"7.2268,7.2302,7.2424,7.2563,7.3089,7.3667",\ +"7.2475,7.2509,7.2630,7.2770,7.3296,7.3874",\ +"7.2650,7.2683,7.2805,7.2944,7.3470,7.4048",\ +"7.3007,7.3041,7.3163,7.3302,7.3828,7.4406",\ +"7.3711,7.3745,7.3866,7.4006,7.4531,7.5110"); + } + cell_fall(SIG2SRAM_delay_template) { + index_1("0.0080,0.0288,0.0616,0.1072,0.1920,0.3496,0.5952"); + index_2("0.0008,0.0014,0.0051,0.0100,0.0339,0.0640"); + values ("7.0953,7.0975,7.1076,7.1192,7.1626,7.2064",\ +"7.1108,7.1129,7.1230,7.1347,7.1780,7.2218",\ +"7.1171,7.1193,7.1293,7.1410,7.1843,7.2282",\ +"7.1378,7.1400,7.1500,7.1617,7.2050,7.2489",\ +"7.1552,7.1574,7.1674,7.1791,7.2225,7.2663",\ +"7.1910,7.1932,7.2032,7.2149,7.2582,7.3021",\ +"7.2614,7.2635,7.2736,7.2853,7.3286,7.3724"); + } + + rise_transition(SRAM_load_template) { + index_1("0.0008,0.0014,0.0051,0.0100,0.0339,0.0640"); + values ("0.0560,0.0583,0.0696,0.0816,0.1519,0.2335"); + } + fall_transition(SRAM_load_template) { + index_1("0.0008,0.0014,0.0051,0.0100,0.0339,0.0640"); + values ("0.0428,0.0445,0.0538,0.0658,0.1181,0.1751"); + } + } +} +cell_leakage_power : 1906.3142; +} +} diff --git a/flow/platforms/ihp-sg13g2/lib/RM_IHPSG13_2P_1024x16_c2_bm_bist_typ_1p20V_25C.lib b/flow/platforms/ihp-sg13g2/lib/RM_IHPSG13_2P_1024x16_c2_bm_bist_typ_1p20V_25C.lib new file mode 100644 index 0000000000..ec81cd0c55 --- /dev/null +++ b/flow/platforms/ihp-sg13g2/lib/RM_IHPSG13_2P_1024x16_c2_bm_bist_typ_1p20V_25C.lib @@ -0,0 +1,2898 @@ +/* ------------------------------------------------------*/ +/**/ +/* Copyright 2025 IHP PDK Authors*/ +/**/ +/* Licensed under the Apache License, Version 2.0 (the "License");*/ +/* you may not use this file except in compliance with the License.*/ +/* You may obtain a copy of the License at*/ +/* */ +/* https://www.apache.org/licenses/LICENSE-2.0*/ +/* */ +/* Unless required by applicable law or agreed to in writing, software*/ +/* distributed under the License is distributed on an "AS IS" BASIS,*/ +/* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.*/ +/* See the License for the specific language governing permissions and*/ +/* limitations under the License.*/ +/* */ +/* Generated on Tue Sep 9 10:49:18 2025 */ +/* */ +/* ------------------------------------------------------ */ +library(RM_IHPSG13_2P_1024x16_c2_bm_bist_typ_1p20V_25C) { + technology (cmos) ; + delay_model : table_lookup ; + define ("add_pg_pin_to_lib", "library", "boolean"); + add_pg_pin_to_lib : true; + voltage_map ( VDD, 1.20); + voltage_map ( VDDARRAY, 1.20); + voltage_map ( VSS, 0.000000 ); + + date : "Tue Sep 9 10:49:15 2025" ; + comment : "IHP Microelectronics GmbH, 2023" ; + revision : 1.0.0 ; + simulation : true ; + nom_process : 1 ; + nom_temperature : 25 ; + nom_voltage : 1.20 ; + + operating_conditions("typ_1p20V_25C"){ + process : 1 ; + temperature : 25 ; + voltage : 1.20 ; + tree_type : "balanced_tree" ; + } + + default_operating_conditions : typ_1p20V_25C ; + default_max_transition : 1.0 ; + default_fanout_load : 1.0 ; + default_inout_pin_cap : 0.0 ; + default_input_pin_cap : 0.0 ; + default_output_pin_cap : 0.0 ; + default_cell_leakage_power : 0.0 ; + default_leakage_power_density : 0.0 ; + + slew_lower_threshold_pct_rise : 30 ; + slew_upper_threshold_pct_rise : 70 ; + input_threshold_pct_fall : 50 ; + output_threshold_pct_fall : 50 ; + input_threshold_pct_rise : 50 ; + output_threshold_pct_rise : 50 ; + slew_lower_threshold_pct_fall : 30 ; + slew_upper_threshold_pct_fall : 70 ; + slew_derate_from_library : 0.5; + k_volt_cell_leakage_power : 0.0 ; + k_temp_cell_leakage_power : 0.0 ; + k_process_cell_leakage_power : 0.0 ; + k_volt_internal_power : 0.0 ; + k_temp_internal_power : 0.0 ; + k_process_internal_power : 0.0 ; + + capacitive_load_unit (1,pf) ; + voltage_unit : "1V" ; + current_unit : "1uA" ; + time_unit : "1ns" ; + leakage_power_unit : "1nW" ; + pulling_resistance_unit : "1kohm"; + /* + ------------------------------------------------------------------------------------------ + implicit units overview: + cell_area unit : "um" + internal_power unit : "1e-12 * J/toggle = 1 * uW/MHz" + (capacitive_load_unit * voltage_unit^2) per toggle event + ------------------------------------------------------------------------------------------ + */ + library_features(report_delay_calculation); + define_cell_area (pad_drivers,pad_driver_sites) ; + + lu_table_template(CLKTRAN_constraint_template) { + variable_1 : constrained_pin_transition; + index_1 ( "0.010, 0.050, 0.200, 0.400, 1.000" ); + } + lu_table_template(SRAM_load_template) { + variable_1 : total_output_net_capacitance; + index_1 ( "0.0008,0.0014,0.0051,0.0100,0.0339,0.0640" ); + } + lu_table_template(SIG2SRAM_constraint_template) { + variable_1 : related_pin_transition; + variable_2 : constrained_pin_transition; + index_1 ( "0.0056,0.0232,0.0400,0.0728,0.1280,0.2440,0.4760" ); + index_2 ( "0.0056,0.0232,0.0400,0.0728,0.1280,0.2440,0.4760" ); + } + + lu_table_template(SIG2SRAM_delay_template) { + variable_1 : input_net_transition; + variable_2 : total_output_net_capacitance; + index_1 ( "0.0056,0.0232,0.0400,0.0728,0.1280,0.2440,0.4760" ); + index_2 ( "0.0008,0.0014,0.0051,0.0100,0.0339,0.0640" ); + } + + type (D_15_0) { + base_type : array; + data_type : bit; + bit_width : 16; + bit_from : 15; + bit_to : 0; + downto : true; + } + + type (A_9_0) { + base_type : array; + data_type : bit; + bit_width : 10; + bit_from : 9; + bit_to : 0; + downto : true; + } + +cell(RM_IHPSG13_2P_1024x16_c2_bm_bist) { +pg_pin (VDD) { + pg_type : primary_power; + voltage_name : VDD; +} +pg_pin (VDDARRAY) { + pg_type : primary_power; + voltage_name : VDDARRAY; +} +pg_pin (VSS) { + pg_type : primary_ground; + voltage_name : VSS; +} + +memory() { + type : ram; + address_width : 10; + word_width : 16; +} + +interface_timing : false; +bus_naming_style : "%s[%d]" ; +area : 155153.8157 ; + + pin(A_DLY) { + direction : input ; + capacitance : 0.00401111 ; + max_transition : "1" ; + related_power_pin : VDD; + related_ground_pin : VSS; + internal_power() { + rise_power("scalar") { + values (0); + } + fall_power("scalar") { + values (0); + } + } + } + +bus(A_ADDR) { + bus_type : A_9_0; + direction : input ; + capacitance : 0.0121077 ; + pin(A_ADDR[0]) { + capacitance : 0.00568653 ; + } + pin(A_ADDR[1]) { + capacitance : 0.00767263 ; + } + pin(A_ADDR[2]) { + capacitance : 0.0105079 ; + } + pin(A_ADDR[3]) { + capacitance : 0.0068178 ; + } + pin(A_ADDR[4]) { + capacitance : 0.00624497 ; + } + pin(A_ADDR[5]) { + capacitance : 0.0105871 ; + } + pin(A_ADDR[6]) { + capacitance : 0.0130817 ; + } + pin(A_ADDR[7]) { + capacitance : 0.0104931 ; + } + pin(A_ADDR[8]) { + capacitance : 0.00913384 ; + } + max_transition : "0.476" ; + pin(A_ADDR[9:0]) { + related_power_pin : VDD; + related_ground_pin : VSS; + internal_power() { + when : "A_MEN"; + rise_power("scalar"){ + values (0.0120); + } + fall_power("scalar"){ + values (0.0063); + } + } + internal_power() { + when : "!A_MEN"; + rise_power("scalar"){ + values (0.0204); + } + fall_power("scalar"){ + values (0.0012); + } + } + } + timing() { + timing_type : setup_rising; + related_pin : "A_CLK"; + when : "((A_WEN | A_REN)& A_MEN)" + sdf_cond : "A_RW_ACCESS" + + rise_constraint("SIG2SRAM_constraint_template") { + index_1("0.0056,0.0232,0.0400,0.0728,0.1280,0.2440,0.4760"); + index_2("0.0056,0.0232,0.0400,0.0728,0.1280,0.2440,0.4760"); + values ("-0.4168,-0.3973,-0.3855,-0.3543,-0.3074,-0.2020,-0.0027",\ +"-0.4324,-0.4129,-0.4012,-0.3699,-0.3191,-0.2176,-0.0184",\ +"-0.4441,-0.4285,-0.4129,-0.3816,-0.3309,-0.2293,-0.0301",\ +"-0.4793,-0.4598,-0.4441,-0.4129,-0.3660,-0.2645,-0.0652",\ +"-0.5223,-0.5066,-0.4910,-0.4598,-0.4129,-0.3074,-0.1121",\ +"-0.6199,-0.6082,-0.5926,-0.5613,-0.5145,-0.4129,-0.2137",\ +"-0.8191,-0.8074,-0.7840,-0.7566,-0.7098,-0.6082,-0.4051"); + } + + fall_constraint("SIG2SRAM_constraint_template") { + index_1("0.0056,0.0232,0.0400,0.0728,0.1280,0.2440,0.4760"); + index_2("0.0056,0.0232,0.0400,0.0728,0.1280,0.2440,0.4760"); + values ("-0.3309,-0.3113,-0.2996,-0.2684,-0.2176,-0.1238,0.0637",\ +"-0.3465,-0.3309,-0.3152,-0.2840,-0.2332,-0.1395,0.0480",\ +"-0.3582,-0.3426,-0.3270,-0.2996,-0.2488,-0.1512,0.0324",\ +"-0.3895,-0.3738,-0.3582,-0.3309,-0.2801,-0.1863,0.0051",\ +"-0.4363,-0.4207,-0.4051,-0.3777,-0.3230,-0.2293,-0.0379",\ +"-0.5379,-0.5223,-0.5066,-0.4793,-0.4285,-0.3309,-0.1434",\ +"-0.7332,-0.7176,-0.7020,-0.6746,-0.6238,-0.5262,-0.3387"); + } + } + + + timing() { + timing_type : hold_rising; + related_pin : "A_CLK"; + when : "((A_WEN | A_REN)& A_MEN)" + sdf_cond : "A_RW_ACCESS" + + rise_constraint("SIG2SRAM_constraint_template") { + index_1("0.0056,0.0232,0.0400,0.0728,0.1280,0.2440,0.4760"); + index_2("0.0056,0.0232,0.0400,0.0728,0.1280,0.2440,0.4760"); + values ("0.5246,0.5051,0.4895,0.4582,0.4113,0.3059,0.1066",\ +"0.5402,0.5207,0.5051,0.4777,0.4270,0.3215,0.1223",\ +"0.5520,0.5324,0.5168,0.4895,0.4387,0.3371,0.1340",\ +"0.5832,0.5676,0.5520,0.5207,0.4738,0.3684,0.1691",\ +"0.6301,0.6105,0.5949,0.5676,0.5168,0.4113,0.2160",\ +"0.7316,0.7121,0.7004,0.6691,0.6223,0.5168,0.3176",\ +"0.9270,0.9230,0.8957,0.8645,0.8137,0.7121,0.5168"); + } + + fall_constraint("SIG2SRAM_constraint_template") { + index_1("0.0056,0.0232,0.0400,0.0728,0.1280,0.2440,0.4760"); + index_2("0.0056,0.0232,0.0400,0.0728,0.1280,0.2440,0.4760"); + values ("0.4309,0.4152,0.4035,0.3684,0.3215,0.2277,0.0363",\ +"0.4465,0.4309,0.4152,0.3879,0.3371,0.2395,0.0559",\ +"0.4582,0.4426,0.4309,0.3996,0.3488,0.2551,0.0715",\ +"0.4934,0.4777,0.4621,0.4348,0.3840,0.2863,0.0988",\ +"0.5363,0.5207,0.5051,0.4777,0.4270,0.3332,0.1418",\ +"0.6379,0.6262,0.6105,0.5793,0.5324,0.4348,0.2434",\ +"0.8332,0.8215,0.8059,0.7707,0.7238,0.6301,0.4387"); + } + } +} +pin(A_WEN) { + direction : input ; + capacitance : 0.00324098 ; + max_transition : "0.476" ; + related_power_pin : VDD; + related_ground_pin : VSS; + internal_power() { + when : "A_MEN"; + rise_power("scalar"){ + values (0.0046); + } + fall_power("scalar"){ + values (0.0039); + } + } + internal_power() { + when : "!A_MEN"; + rise_power("scalar"){ + values (0.0043); + } + fall_power("scalar"){ + values (0.0040); + } + } + timing() { + timing_type : setup_rising; + related_pin : "A_CLK"; + when : "A_MEN" + sdf_cond : "A_MEN" + + rise_constraint("SIG2SRAM_constraint_template") { + index_1("0.0056,0.0232,0.0400,0.0728,0.1280,0.2440,0.4760"); + index_2("0.0056,0.0232,0.0400,0.0728,0.1280,0.2440,0.4760"); + values ("0.2043,0.2199,0.2316,0.2629,0.3059,0.4113,0.6066",\ +"0.1887,0.2043,0.2160,0.2473,0.2941,0.3957,0.5949",\ +"0.1691,0.1848,0.2004,0.2316,0.2785,0.3801,0.5754",\ +"0.1379,0.1574,0.1691,0.2004,0.2473,0.3527,0.5480",\ +"0.0910,0.1066,0.1223,0.1535,0.2004,0.2980,0.4973",\ +"-0.0105,0.0051,0.0207,0.0520,0.0949,0.2004,0.3957",\ +"-0.2059,-0.1902,-0.1746,-0.1473,-0.1004,0.0051,0.2004"); + } + + fall_constraint("SIG2SRAM_constraint_template") { + index_1("0.0056,0.0232,0.0400,0.0728,0.1280,0.2440,0.4760"); + index_2("0.0056,0.0232,0.0400,0.0728,0.1280,0.2440,0.4760"); + values ("0.2941,0.3098,0.3215,0.3488,0.4035,0.4973,0.6887",\ +"0.2785,0.2941,0.3059,0.3332,0.3840,0.4816,0.6691",\ +"0.2629,0.2785,0.2902,0.3176,0.3684,0.4660,0.6535",\ +"0.2316,0.2473,0.2590,0.2863,0.3410,0.4348,0.6262",\ +"0.1848,0.2004,0.2121,0.2395,0.2902,0.3879,0.5754",\ +"0.0832,0.0988,0.1105,0.1379,0.1809,0.2746,0.4699",\ +"-0.1121,-0.0965,-0.0848,-0.0535,-0.0066,0.0910,0.2824"); + } + } + + + timing() { + timing_type : hold_rising; + related_pin : "A_CLK"; + when : "A_MEN" + sdf_cond : "A_MEN" + + rise_constraint("SIG2SRAM_constraint_template") { + index_1("0.0056,0.0232,0.0400,0.0728,0.1280,0.2440,0.4760"); + index_2("0.0056,0.0232,0.0400,0.0728,0.1280,0.2440,0.4760"); + values ("0.2473,0.2316,0.2160,0.1887,0.1379,0.0363,-0.1629",\ +"0.2629,0.2473,0.2316,0.2043,0.1535,0.0520,-0.1473",\ +"0.2785,0.2590,0.2434,0.2160,0.1652,0.0676,-0.1355",\ +"0.3098,0.2941,0.2785,0.2473,0.1965,0.0910,-0.1043",\ +"0.3527,0.3371,0.3215,0.2941,0.2434,0.1418,-0.0574",\ +"0.4582,0.4426,0.4270,0.3957,0.3488,0.2434,0.0480",\ +"0.6535,0.6379,0.6184,0.5910,0.5402,0.4426,0.2434"); + } + + fall_constraint("SIG2SRAM_constraint_template") { + index_1("0.0056,0.0232,0.0400,0.0728,0.1280,0.2440,0.4760"); + index_2("0.0056,0.0232,0.0400,0.0728,0.1280,0.2440,0.4760"); + values ("0.2395,0.2238,0.2121,0.1809,0.1301,0.0324,-0.1551",\ +"0.2551,0.2395,0.2277,0.1965,0.1457,0.0480,-0.1395",\ +"0.2668,0.2551,0.2395,0.2082,0.1574,0.0637,-0.1277",\ +"0.3020,0.2863,0.2707,0.2395,0.1887,0.0910,-0.0965",\ +"0.3449,0.3293,0.3176,0.2863,0.2355,0.1379,-0.0496",\ +"0.4504,0.4348,0.4191,0.3879,0.3371,0.2395,0.0559",\ +"0.6457,0.6301,0.6145,0.5871,0.5324,0.4309,0.2512"); + } + } + } +pin(A_REN) { + direction : input ; + capacitance : 0.00381634 ; + max_transition : "0.476" ; + related_power_pin : VDD; + related_ground_pin : VSS; + internal_power() { + when : "A_MEN"; + rise_power("scalar"){ + values (0.0061); + } + fall_power("scalar"){ + values (0.0021); + } + } + internal_power() { + when : "!A_MEN"; + rise_power("scalar"){ + values (0.0062); + } + fall_power("scalar"){ + values (0.0025); + } + } + timing() { + timing_type : setup_rising; + related_pin : "A_CLK"; + when : "A_MEN" + sdf_cond : "A_MEN" + + rise_constraint("SIG2SRAM_constraint_template") { + index_1("0.0056,0.0232,0.0400,0.0728,0.1280,0.2440,0.4760"); + index_2("0.0056,0.0232,0.0400,0.0728,0.1280,0.2440,0.4760"); + values ("-0.0301,-0.0145,0.0012,0.0324,0.0793,0.1809,0.3762",\ +"-0.0457,-0.0301,-0.0145,0.0168,0.0637,0.1613,0.3605",\ +"-0.0574,-0.0418,-0.0262,0.0051,0.0520,0.1496,0.3449",\ +"-0.0926,-0.0730,-0.0574,-0.0262,0.0207,0.1184,0.3137",\ +"-0.1395,-0.1238,-0.1082,-0.0770,-0.0301,0.0715,0.2707",\ +"-0.2410,-0.2254,-0.2098,-0.1746,-0.1355,-0.0340,0.1652",\ +"-0.4402,-0.4207,-0.4051,-0.3738,-0.3270,-0.2293,-0.0340"); + } + + fall_constraint("SIG2SRAM_constraint_template") { + index_1("0.0056,0.0232,0.0400,0.0728,0.1280,0.2440,0.4760"); + index_2("0.0056,0.0232,0.0400,0.0728,0.1280,0.2440,0.4760"); + values ("0.0988,0.1145,0.1262,0.1535,0.2043,0.3020,0.4855",\ +"0.0832,0.0988,0.1105,0.1418,0.1848,0.2824,0.4738",\ +"0.0676,0.0832,0.0949,0.1262,0.1730,0.2668,0.4621",\ +"0.0402,0.0559,0.0676,0.0988,0.1457,0.2434,0.4191",\ +"-0.0105,0.0012,0.0168,0.0480,0.0988,0.1965,0.3840",\ +"-0.1160,-0.0965,-0.0848,-0.0535,-0.0066,0.0988,0.2824",\ +"-0.3113,-0.2957,-0.2801,-0.2527,-0.2059,-0.1043,0.0832"); + } + } + + + timing() { + timing_type : hold_rising; + related_pin : "A_CLK"; + when : "A_MEN" + sdf_cond : "A_MEN" + + rise_constraint("SIG2SRAM_constraint_template") { + index_1("0.0056,0.0232,0.0400,0.0728,0.1280,0.2440,0.4760"); + index_2("0.0056,0.0232,0.0400,0.0728,0.1280,0.2440,0.4760"); + values ("0.2707,0.2551,0.2395,0.2121,0.1613,0.0598,-0.1395",\ +"0.2863,0.2707,0.2551,0.2238,0.1730,0.0715,-0.1238",\ +"0.2980,0.2824,0.2668,0.2395,0.1887,0.0871,-0.1121",\ +"0.3332,0.3176,0.3020,0.2707,0.2199,0.1184,-0.0809",\ +"0.3762,0.3605,0.3449,0.3176,0.2668,0.1613,-0.0340",\ +"0.4816,0.4621,0.4504,0.4191,0.3723,0.2629,0.0715",\ +"0.6770,0.6613,0.6418,0.6184,0.5637,0.4699,0.2629"); + } + + fall_constraint("SIG2SRAM_constraint_template") { + index_1("0.0056,0.0232,0.0400,0.0728,0.1280,0.2440,0.4760"); + index_2("0.0056,0.0232,0.0400,0.0728,0.1280,0.2440,0.4760"); + values ("0.2590,0.2434,0.2316,0.2004,0.1457,0.0520,-0.1355",\ +"0.2746,0.2590,0.2434,0.2160,0.1613,0.0676,-0.1199",\ +"0.2863,0.2707,0.2590,0.2277,0.1730,0.0832,-0.1082",\ +"0.3215,0.3059,0.2902,0.2590,0.2082,0.1105,-0.0770",\ +"0.3645,0.3488,0.3332,0.3059,0.2551,0.1535,-0.0340",\ +"0.4699,0.4543,0.4387,0.4074,0.3605,0.2551,0.0715",\ +"0.6652,0.6496,0.6340,0.6027,0.5520,0.4621,0.2707"); + } + } + } +pin(A_MEN) { + direction : input ; + capacitance : 0.00309605 ; + max_transition : "0.476" ; + related_power_pin : VDD; + related_ground_pin : VSS; + internal_power() { + rise_power("scalar"){ + values (0.0448); + } + fall_power("scalar"){ + values (0.0052); + } + } + timing() { + timing_type : setup_rising; + related_pin : "A_CLK"; + + rise_constraint("SIG2SRAM_constraint_template") { + index_1("0.0056,0.0232,0.0400,0.0728,0.1280,0.2440,0.4760"); + index_2("0.0056,0.0232,0.0400,0.0728,0.1280,0.2440,0.4760"); + values ("0.2043,0.2199,0.2316,0.2668,0.3098,0.4152,0.6066",\ +"0.1887,0.2043,0.2199,0.2512,0.2941,0.3996,0.5949",\ +"0.1730,0.1887,0.2043,0.2355,0.2824,0.3840,0.5793",\ +"0.1418,0.1574,0.1730,0.2043,0.2512,0.3566,0.5480",\ +"0.0949,0.1105,0.1262,0.1574,0.2043,0.3020,0.5051",\ +"-0.0066,0.0090,0.0246,0.0520,0.0988,0.2043,0.3996",\ +"-0.2020,-0.1863,-0.1746,-0.1434,-0.0965,0.0090,0.2082"); + } + + fall_constraint("SIG2SRAM_constraint_template") { + index_1("0.0056,0.0232,0.0400,0.0728,0.1280,0.2440,0.4760"); + index_2("0.0056,0.0232,0.0400,0.0728,0.1280,0.2440,0.4760"); + values ("0.2980,0.3137,0.3254,0.3527,0.4035,0.5012,0.6887",\ +"0.2824,0.2980,0.3098,0.3371,0.3879,0.4855,0.6730",\ +"0.2668,0.2824,0.2941,0.3215,0.3723,0.4699,0.6574",\ +"0.2355,0.2473,0.2629,0.2902,0.3410,0.4387,0.6262",\ +"0.1887,0.2004,0.2160,0.2395,0.2941,0.3918,0.5793",\ +"0.0871,0.1027,0.1145,0.1418,0.1848,0.2746,0.4816",\ +"-0.1082,-0.0965,-0.0809,-0.0496,-0.0027,0.0949,0.2863"); + } + } + + + timing() { + timing_type : hold_rising; + related_pin : "A_CLK"; + + rise_constraint("SIG2SRAM_constraint_template") { + index_1("0.0056,0.0232,0.0400,0.0728,0.1280,0.2440,0.4760"); + index_2("0.0056,0.0232,0.0400,0.0728,0.1280,0.2440,0.4760"); + values ("0.2512,0.2355,0.2199,0.1926,0.1418,0.0402,-0.1590",\ +"0.2668,0.2512,0.2355,0.2082,0.1574,0.0559,-0.1434",\ +"0.2824,0.2629,0.2512,0.2199,0.1691,0.0715,-0.1316",\ +"0.3137,0.2980,0.2824,0.2512,0.2004,0.0988,-0.0965",\ +"0.3566,0.3410,0.3254,0.2980,0.2473,0.1418,-0.0535",\ +"0.4621,0.4426,0.4309,0.3996,0.3527,0.2473,0.0520",\ +"0.6574,0.6418,0.6262,0.5949,0.5441,0.4465,0.2473"); + } + + fall_constraint("SIG2SRAM_constraint_template") { + index_1("0.0056,0.0232,0.0400,0.0728,0.1280,0.2440,0.4760"); + index_2("0.0056,0.0232,0.0400,0.0728,0.1280,0.2440,0.4760"); + values ("0.2395,0.2238,0.2121,0.1809,0.1301,0.0324,-0.1551",\ +"0.2551,0.2434,0.2277,0.1965,0.1457,0.0480,-0.1395",\ +"0.2707,0.2551,0.2395,0.2082,0.1574,0.0637,-0.1277",\ +"0.3020,0.2863,0.2707,0.2434,0.1926,0.0910,-0.0965",\ +"0.3449,0.3332,0.3176,0.2863,0.2355,0.1379,-0.0496",\ +"0.4504,0.4348,0.4230,0.3918,0.3410,0.2434,0.0559",\ +"0.6457,0.6301,0.6145,0.5910,0.5324,0.4387,0.2512"); + } + } + } +bus(A_BM) { + bus_type : D_15_0; + direction : input ; + capacitance : 0.00372627 ; + max_transition : "0.476" ; + pin(A_BM[15:0]) { + related_power_pin : VDD; + related_ground_pin : VSS; + internal_power() { + when : "A_MEN"; + rise_power("scalar"){ + values (0.0592); + } + fall_power("scalar"){ + values (0.0247); + } + } + internal_power() { + when : "!A_MEN"; + rise_power("scalar"){ + values (0.0603); + } + fall_power("scalar"){ + values (0.0245); + } + } + } + timing() { + timing_type : setup_rising; + related_pin : "A_CLK"; + when : "(A_WEN & A_MEN)" + sdf_cond : "A_RW_ACCESS" + + rise_constraint("SIG2SRAM_constraint_template") { + index_1("0.0056,0.0232,0.0400,0.0728,0.1280,0.2440,0.4760"); + index_2("0.0056,0.0232,0.0400,0.0728,0.1280,0.2440,0.4760"); + values ("-0.3858,-0.3702,-0.3565,-0.3243,-0.2774,-0.1729,0.0185",\ +"-0.3908,-0.3752,-0.3615,-0.3293,-0.2824,-0.1779,0.0135",\ +"-0.3953,-0.3796,-0.3660,-0.3337,-0.2869,-0.1824,0.0090",\ +"-0.4051,-0.3895,-0.3758,-0.3436,-0.2967,-0.1922,-0.0008",\ +"-0.4114,-0.3958,-0.3821,-0.3499,-0.3030,-0.1985,-0.0071",\ +"-0.4479,-0.4323,-0.4186,-0.3864,-0.3395,-0.2351,-0.0436",\ +"-0.4988,-0.4832,-0.4695,-0.4373,-0.3904,-0.2859,-0.0945"); + } + + fall_constraint("SIG2SRAM_constraint_template") { + index_1("0.0056,0.0232,0.0400,0.0728,0.1280,0.2440,0.4760"); + index_2("0.0056,0.0232,0.0400,0.0728,0.1280,0.2440,0.4760"); + values ("-0.3477,-0.3331,-0.3194,-0.2911,-0.2403,-0.1426,0.0400",\ +"-0.3527,-0.3381,-0.3244,-0.2961,-0.2453,-0.1477,0.0350",\ +"-0.3572,-0.3425,-0.3288,-0.3005,-0.2497,-0.1521,0.0305",\ +"-0.3670,-0.3524,-0.3387,-0.3104,-0.2596,-0.1619,0.0207",\ +"-0.3734,-0.3587,-0.3450,-0.3167,-0.2659,-0.1683,0.0143",\ +"-0.4098,-0.3952,-0.3815,-0.3532,-0.3024,-0.2048,-0.0222",\ +"-0.4607,-0.4461,-0.4324,-0.4041,-0.3533,-0.2556,-0.0730"); + } + } + + + timing() { + timing_type : hold_rising; + related_pin : "A_CLK"; + when : "(A_WEN & A_MEN)" + sdf_cond : "A_RW_ACCESS" + + rise_constraint("SIG2SRAM_constraint_template") { + index_1("0.0056,0.0232,0.0400,0.0728,0.1280,0.2440,0.4760"); + index_2("0.0056,0.0232,0.0400,0.0728,0.1280,0.2440,0.4760"); + values ("0.4953,0.4787,0.4660,0.4338,0.3859,0.2824,0.0900",\ +"0.5003,0.4837,0.4710,0.4388,0.3909,0.2874,0.0950",\ +"0.5048,0.4881,0.4754,0.4432,0.3954,0.2919,0.0995",\ +"0.5146,0.4980,0.4853,0.4531,0.4052,0.3017,0.1093",\ +"0.5209,0.5043,0.4916,0.4594,0.4116,0.3080,0.1157",\ +"0.5574,0.5408,0.5281,0.4959,0.4481,0.3445,0.1522",\ +"0.6083,0.5917,0.5790,0.5468,0.4989,0.3954,0.2030"); + } + + fall_constraint("SIG2SRAM_constraint_template") { + index_1("0.0056,0.0232,0.0400,0.0728,0.1280,0.2440,0.4760"); + index_2("0.0056,0.0232,0.0400,0.0728,0.1280,0.2440,0.4760"); + values ("0.4494,0.4348,0.4211,0.3928,0.3430,0.2502,0.0656",\ +"0.4544,0.4398,0.4261,0.3978,0.3480,0.2552,0.0706",\ +"0.4588,0.4442,0.4305,0.4022,0.3524,0.2596,0.0751",\ +"0.4687,0.4540,0.4404,0.4121,0.3622,0.2695,0.0849",\ +"0.4750,0.4604,0.4467,0.4184,0.3686,0.2758,0.0912",\ +"0.5115,0.4969,0.4832,0.4549,0.4051,0.3123,0.1277",\ +"0.5624,0.5477,0.5341,0.5058,0.4559,0.3632,0.1786"); + } + } +} + pin(A_CLK) { + direction : input; + capacitance : 0.00380014; + max_transition : "0.476"; + clock : "true" ; + pin_func_type : active_rising ; + + timing () { + timing_type : "min_pulse_width"; + related_pin : "A_CLK"; + rise_constraint("CLKTRAN_constraint_template") { + index_1("0.0056,0.476"); + values("0.21,0.21"); + } + } + + related_power_pin : VDD; + related_ground_pin : VSS; + + internal_power() { + when : "!A_MEN & !A_WEN & !A_REN"; + rise_power("scalar"){ + values (0); + } + fall_power("scalar"){ + values (0); + } + } + internal_power() { + when : "!A_MEN & A_WEN & !A_REN"; + rise_power("scalar"){ + values (0.5466); + } + fall_power("scalar"){ + values (0); + } + } + internal_power() { + when : "A_MEN & A_WEN & !A_REN"; + rise_power("scalar"){ + values (32.9180); + } + fall_power("scalar"){ + values (0); + } + } + internal_power() { + when : "A_MEN & A_WEN & A_REN"; + rise_power("scalar"){ + values (33.7600); + } + fall_power("scalar"){ + values (0); + } + } + internal_power() { + when : "A_MEN & !A_WEN & A_REN"; + rise_power("scalar"){ + values (26.4863); + } + fall_power("scalar"){ + values (0); + } + } + internal_power() { + when : "!A_MEN & !A_WEN & A_REN"; + rise_power("scalar"){ + values (0.3253); + } + fall_power("scalar"){ + values (0); + } + } + internal_power() { + when : "!A_MEN & A_WEN & A_REN"; + rise_power("scalar"){ + values (0.7651); + } + fall_power("scalar"){ + values (0); + } + } + internal_power() { + when : "A_MEN & !A_WEN & !A_REN"; + rise_power("scalar"){ + values (0); + } + fall_power("scalar"){ + values (0); + } + } + } + bus(A_DIN) { + bus_type : D_15_0; + direction : input ; + capacitance : 0.00500744 ; + memory_write() { + address : A_ADDR ; + clocked_on : A_CLK; + } + + max_transition : "0.476" ; + pin(A_DIN[15:0]) { + related_power_pin : VDD; + related_ground_pin : VSS; + internal_power() { + when : "A_MEN"; + rise_power("scalar"){ + values (0.0592); + } + fall_power("scalar"){ + values (0.0247); + } + } + internal_power() { + when : "!A_MEN"; + rise_power("scalar"){ + values (0.0603); + } + fall_power("scalar"){ + values (0.0245); + } + } + } + timing() { + timing_type : setup_rising; + related_pin : "A_CLK"; + when : "(A_WEN & A_MEN)"; + sdf_cond : "A_W_ACCESS"; + + rise_constraint("SIG2SRAM_constraint_template") { + index_1("0.0056,0.0232,0.0400,0.0728,0.1280,0.2440,0.4760"); + index_2("0.0056,0.0232,0.0400,0.0728,0.1280,0.2440,0.4760"); + values ("-0.3858,-0.3702,-0.3565,-0.3243,-0.2774,-0.1729,0.0185",\ +"-0.3908,-0.3752,-0.3615,-0.3293,-0.2824,-0.1779,0.0135",\ +"-0.3953,-0.3796,-0.3660,-0.3337,-0.2869,-0.1824,0.0090",\ +"-0.4051,-0.3895,-0.3758,-0.3436,-0.2967,-0.1922,-0.0008",\ +"-0.4114,-0.3958,-0.3821,-0.3499,-0.3030,-0.1985,-0.0071",\ +"-0.4479,-0.4323,-0.4186,-0.3864,-0.3395,-0.2351,-0.0436",\ +"-0.4988,-0.4832,-0.4695,-0.4373,-0.3904,-0.2859,-0.0945"); + } + + fall_constraint("SIG2SRAM_constraint_template") { + index_1("0.0056,0.0232,0.0400,0.0728,0.1280,0.2440,0.4760"); + index_2("0.0056,0.0232,0.0400,0.0728,0.1280,0.2440,0.4760"); + values ("-0.3477,-0.3331,-0.3194,-0.2911,-0.2403,-0.1426,0.0400",\ +"-0.3527,-0.3381,-0.3244,-0.2961,-0.2453,-0.1477,0.0350",\ +"-0.3572,-0.3425,-0.3288,-0.3005,-0.2497,-0.1521,0.0305",\ +"-0.3670,-0.3524,-0.3387,-0.3104,-0.2596,-0.1619,0.0207",\ +"-0.3734,-0.3587,-0.3450,-0.3167,-0.2659,-0.1683,0.0143",\ +"-0.4098,-0.3952,-0.3815,-0.3532,-0.3024,-0.2048,-0.0222",\ +"-0.4607,-0.4461,-0.4324,-0.4041,-0.3533,-0.2556,-0.0730"); + } + } + + timing() { + timing_type : hold_rising; + related_pin : "A_CLK"; + when : "(A_WEN & A_MEN)"; + sdf_cond : "A_W_ACCESS"; + + rise_constraint("SIG2SRAM_constraint_template") { + index_1("0.0056,0.0232,0.0400,0.0728,0.1280,0.2440,0.4760"); + index_2("0.0056,0.0232,0.0400,0.0728,0.1280,0.2440,0.4760"); + values ("0.4953,0.4787,0.4660,0.4338,0.3859,0.2824,0.0900",\ +"0.5003,0.4837,0.4710,0.4388,0.3909,0.2874,0.0950",\ +"0.5048,0.4881,0.4754,0.4432,0.3954,0.2919,0.0995",\ +"0.5146,0.4980,0.4853,0.4531,0.4052,0.3017,0.1093",\ +"0.5209,0.5043,0.4916,0.4594,0.4116,0.3080,0.1157",\ +"0.5574,0.5408,0.5281,0.4959,0.4481,0.3445,0.1522",\ +"0.6083,0.5917,0.5790,0.5468,0.4989,0.3954,0.2030"); + } + + fall_constraint("SIG2SRAM_constraint_template") { + index_1("0.0056,0.0232,0.0400,0.0728,0.1280,0.2440,0.4760"); + index_2("0.0056,0.0232,0.0400,0.0728,0.1280,0.2440,0.4760"); + values ("0.4494,0.4348,0.4211,0.3928,0.3430,0.2502,0.0656",\ +"0.4544,0.4398,0.4261,0.3978,0.3480,0.2552,0.0706",\ +"0.4588,0.4442,0.4305,0.4022,0.3524,0.2596,0.0751",\ +"0.4687,0.4540,0.4404,0.4121,0.3622,0.2695,0.0849",\ +"0.4750,0.4604,0.4467,0.4184,0.3686,0.2758,0.0912",\ +"0.5115,0.4969,0.4832,0.4549,0.4051,0.3123,0.1277",\ +"0.5624,0.5477,0.5341,0.5058,0.4559,0.3632,0.1786"); + } + } + } + + pin(A_BIST_EN) { + direction : input ; + capacitance : 0.00401111 ; + max_transition : "1" ; + related_power_pin : VDD; + related_ground_pin : VSS; + internal_power() { + rise_power("scalar") { + values (0); + } + fall_power("scalar") { + values (0); + } + } + } + +bus(A_BIST_ADDR) { + bus_type : A_9_0; + direction : input ; + capacitance : 0.0121077 ; + pin(A_BIST_ADDR[0]) { + capacitance : 0.00568653 ; + } + pin(A_BIST_ADDR[1]) { + capacitance : 0.00767263 ; + } + pin(A_BIST_ADDR[2]) { + capacitance : 0.0105079 ; + } + pin(A_BIST_ADDR[3]) { + capacitance : 0.0068178 ; + } + pin(A_BIST_ADDR[4]) { + capacitance : 0.00624497 ; + } + pin(A_BIST_ADDR[5]) { + capacitance : 0.0105871 ; + } + pin(A_BIST_ADDR[6]) { + capacitance : 0.0130817 ; + } + pin(A_BIST_ADDR[7]) { + capacitance : 0.0104931 ; + } + pin(A_BIST_ADDR[8]) { + capacitance : 0.00913384 ; + } + max_transition : "0.476" ; + pin(A_BIST_ADDR[9:0]) { + related_power_pin : VDD; + related_ground_pin : VSS; + internal_power() { + when : "A_BIST_MEN"; + rise_power("scalar"){ + values (0.0120); + } + fall_power("scalar"){ + values (0.0063); + } + } + internal_power() { + when : "!A_BIST_MEN"; + rise_power("scalar"){ + values (0.0204); + } + fall_power("scalar"){ + values (0.0012); + } + } + } + timing() { + timing_type : setup_rising; + related_pin : "A_BIST_CLK"; + when : "((A_BIST_WEN | A_BIST_REN)& A_BIST_MEN)" + sdf_cond : "A_BIST_RW_ACCESS" + + rise_constraint("SIG2SRAM_constraint_template") { + index_1("0.0056,0.0232,0.0400,0.0728,0.1280,0.2440,0.4760"); + index_2("0.0056,0.0232,0.0400,0.0728,0.1280,0.2440,0.4760"); + values ("-0.4168,-0.3973,-0.3855,-0.3543,-0.3074,-0.2020,-0.0027",\ +"-0.4324,-0.4129,-0.4012,-0.3699,-0.3191,-0.2176,-0.0184",\ +"-0.4441,-0.4285,-0.4129,-0.3816,-0.3309,-0.2293,-0.0301",\ +"-0.4793,-0.4598,-0.4441,-0.4129,-0.3660,-0.2645,-0.0652",\ +"-0.5223,-0.5066,-0.4910,-0.4598,-0.4129,-0.3074,-0.1121",\ +"-0.6199,-0.6082,-0.5926,-0.5613,-0.5145,-0.4129,-0.2137",\ +"-0.8191,-0.8074,-0.7840,-0.7566,-0.7098,-0.6082,-0.4051"); + } + + fall_constraint("SIG2SRAM_constraint_template") { + index_1("0.0056,0.0232,0.0400,0.0728,0.1280,0.2440,0.4760"); + index_2("0.0056,0.0232,0.0400,0.0728,0.1280,0.2440,0.4760"); + values ("-0.3309,-0.3113,-0.2996,-0.2684,-0.2176,-0.1238,0.0637",\ +"-0.3465,-0.3309,-0.3152,-0.2840,-0.2332,-0.1395,0.0480",\ +"-0.3582,-0.3426,-0.3270,-0.2996,-0.2488,-0.1512,0.0324",\ +"-0.3895,-0.3738,-0.3582,-0.3309,-0.2801,-0.1863,0.0051",\ +"-0.4363,-0.4207,-0.4051,-0.3777,-0.3230,-0.2293,-0.0379",\ +"-0.5379,-0.5223,-0.5066,-0.4793,-0.4285,-0.3309,-0.1434",\ +"-0.7332,-0.7176,-0.7020,-0.6746,-0.6238,-0.5262,-0.3387"); + } + } + + + timing() { + timing_type : hold_rising; + related_pin : "A_BIST_CLK"; + when : "((A_BIST_WEN | A_BIST_REN)& A_BIST_MEN)" + sdf_cond : "A_BIST_RW_ACCESS" + + rise_constraint("SIG2SRAM_constraint_template") { + index_1("0.0056,0.0232,0.0400,0.0728,0.1280,0.2440,0.4760"); + index_2("0.0056,0.0232,0.0400,0.0728,0.1280,0.2440,0.4760"); + values ("0.5246,0.5051,0.4895,0.4582,0.4113,0.3059,0.1066",\ +"0.5402,0.5207,0.5051,0.4777,0.4270,0.3215,0.1223",\ +"0.5520,0.5324,0.5168,0.4895,0.4387,0.3371,0.1340",\ +"0.5832,0.5676,0.5520,0.5207,0.4738,0.3684,0.1691",\ +"0.6301,0.6105,0.5949,0.5676,0.5168,0.4113,0.2160",\ +"0.7316,0.7121,0.7004,0.6691,0.6223,0.5168,0.3176",\ +"0.9270,0.9230,0.8957,0.8645,0.8137,0.7121,0.5168"); + } + + fall_constraint("SIG2SRAM_constraint_template") { + index_1("0.0056,0.0232,0.0400,0.0728,0.1280,0.2440,0.4760"); + index_2("0.0056,0.0232,0.0400,0.0728,0.1280,0.2440,0.4760"); + values ("0.4309,0.4152,0.4035,0.3684,0.3215,0.2277,0.0363",\ +"0.4465,0.4309,0.4152,0.3879,0.3371,0.2395,0.0559",\ +"0.4582,0.4426,0.4309,0.3996,0.3488,0.2551,0.0715",\ +"0.4934,0.4777,0.4621,0.4348,0.3840,0.2863,0.0988",\ +"0.5363,0.5207,0.5051,0.4777,0.4270,0.3332,0.1418",\ +"0.6379,0.6262,0.6105,0.5793,0.5324,0.4348,0.2434",\ +"0.8332,0.8215,0.8059,0.7707,0.7238,0.6301,0.4387"); + } + } +} +pin(A_BIST_WEN) { + direction : input ; + capacitance : 0.00324098 ; + max_transition : "0.476" ; + related_power_pin : VDD; + related_ground_pin : VSS; + internal_power() { + when : "A_BIST_MEN"; + rise_power("scalar"){ + values (0.0046); + } + fall_power("scalar"){ + values (0.0039); + } + } + internal_power() { + when : "!A_BIST_MEN"; + rise_power("scalar"){ + values (0.0043); + } + fall_power("scalar"){ + values (0.0040); + } + } + timing() { + timing_type : setup_rising; + related_pin : "A_BIST_CLK"; + when : "A_BIST_MEN" + sdf_cond : "A_BIST_MEN" + + rise_constraint("SIG2SRAM_constraint_template") { + index_1("0.0056,0.0232,0.0400,0.0728,0.1280,0.2440,0.4760"); + index_2("0.0056,0.0232,0.0400,0.0728,0.1280,0.2440,0.4760"); + values ("0.2043,0.2199,0.2316,0.2629,0.3059,0.4113,0.6066",\ +"0.1887,0.2043,0.2160,0.2473,0.2941,0.3957,0.5949",\ +"0.1691,0.1848,0.2004,0.2316,0.2785,0.3801,0.5754",\ +"0.1379,0.1574,0.1691,0.2004,0.2473,0.3527,0.5480",\ +"0.0910,0.1066,0.1223,0.1535,0.2004,0.2980,0.4973",\ +"-0.0105,0.0051,0.0207,0.0520,0.0949,0.2004,0.3957",\ +"-0.2059,-0.1902,-0.1746,-0.1473,-0.1004,0.0051,0.2004"); + } + + fall_constraint("SIG2SRAM_constraint_template") { + index_1("0.0056,0.0232,0.0400,0.0728,0.1280,0.2440,0.4760"); + index_2("0.0056,0.0232,0.0400,0.0728,0.1280,0.2440,0.4760"); + values ("0.2941,0.3098,0.3215,0.3488,0.4035,0.4973,0.6887",\ +"0.2785,0.2941,0.3059,0.3332,0.3840,0.4816,0.6691",\ +"0.2629,0.2785,0.2902,0.3176,0.3684,0.4660,0.6535",\ +"0.2316,0.2473,0.2590,0.2863,0.3410,0.4348,0.6262",\ +"0.1848,0.2004,0.2121,0.2395,0.2902,0.3879,0.5754",\ +"0.0832,0.0988,0.1105,0.1379,0.1809,0.2746,0.4699",\ +"-0.1121,-0.0965,-0.0848,-0.0535,-0.0066,0.0910,0.2824"); + } + } + + + timing() { + timing_type : hold_rising; + related_pin : "A_BIST_CLK"; + when : "A_BIST_MEN" + sdf_cond : "A_BIST_MEN" + + rise_constraint("SIG2SRAM_constraint_template") { + index_1("0.0056,0.0232,0.0400,0.0728,0.1280,0.2440,0.4760"); + index_2("0.0056,0.0232,0.0400,0.0728,0.1280,0.2440,0.4760"); + values ("0.2473,0.2316,0.2160,0.1887,0.1379,0.0363,-0.1629",\ +"0.2629,0.2473,0.2316,0.2043,0.1535,0.0520,-0.1473",\ +"0.2785,0.2590,0.2434,0.2160,0.1652,0.0676,-0.1355",\ +"0.3098,0.2941,0.2785,0.2473,0.1965,0.0910,-0.1043",\ +"0.3527,0.3371,0.3215,0.2941,0.2434,0.1418,-0.0574",\ +"0.4582,0.4426,0.4270,0.3957,0.3488,0.2434,0.0480",\ +"0.6535,0.6379,0.6184,0.5910,0.5402,0.4426,0.2434"); + } + + fall_constraint("SIG2SRAM_constraint_template") { + index_1("0.0056,0.0232,0.0400,0.0728,0.1280,0.2440,0.4760"); + index_2("0.0056,0.0232,0.0400,0.0728,0.1280,0.2440,0.4760"); + values ("0.2395,0.2238,0.2121,0.1809,0.1301,0.0324,-0.1551",\ +"0.2551,0.2395,0.2277,0.1965,0.1457,0.0480,-0.1395",\ +"0.2668,0.2551,0.2395,0.2082,0.1574,0.0637,-0.1277",\ +"0.3020,0.2863,0.2707,0.2395,0.1887,0.0910,-0.0965",\ +"0.3449,0.3293,0.3176,0.2863,0.2355,0.1379,-0.0496",\ +"0.4504,0.4348,0.4191,0.3879,0.3371,0.2395,0.0559",\ +"0.6457,0.6301,0.6145,0.5871,0.5324,0.4309,0.2512"); + } + } + } +pin(A_BIST_REN) { + direction : input ; + capacitance : 0.00381634 ; + max_transition : "0.476" ; + related_power_pin : VDD; + related_ground_pin : VSS; + internal_power() { + when : "A_BIST_MEN"; + rise_power("scalar"){ + values (0.0061); + } + fall_power("scalar"){ + values (0.0021); + } + } + internal_power() { + when : "!A_BIST_MEN"; + rise_power("scalar"){ + values (0.0062); + } + fall_power("scalar"){ + values (0.0025); + } + } + timing() { + timing_type : setup_rising; + related_pin : "A_BIST_CLK"; + when : "A_BIST_MEN" + sdf_cond : "A_BIST_MEN" + + rise_constraint("SIG2SRAM_constraint_template") { + index_1("0.0056,0.0232,0.0400,0.0728,0.1280,0.2440,0.4760"); + index_2("0.0056,0.0232,0.0400,0.0728,0.1280,0.2440,0.4760"); + values ("-0.0301,-0.0145,0.0012,0.0324,0.0793,0.1809,0.3762",\ +"-0.0457,-0.0301,-0.0145,0.0168,0.0637,0.1613,0.3605",\ +"-0.0574,-0.0418,-0.0262,0.0051,0.0520,0.1496,0.3449",\ +"-0.0926,-0.0730,-0.0574,-0.0262,0.0207,0.1184,0.3137",\ +"-0.1395,-0.1238,-0.1082,-0.0770,-0.0301,0.0715,0.2707",\ +"-0.2410,-0.2254,-0.2098,-0.1746,-0.1355,-0.0340,0.1652",\ +"-0.4402,-0.4207,-0.4051,-0.3738,-0.3270,-0.2293,-0.0340"); + } + + fall_constraint("SIG2SRAM_constraint_template") { + index_1("0.0056,0.0232,0.0400,0.0728,0.1280,0.2440,0.4760"); + index_2("0.0056,0.0232,0.0400,0.0728,0.1280,0.2440,0.4760"); + values ("0.0988,0.1145,0.1262,0.1535,0.2043,0.3020,0.4855",\ +"0.0832,0.0988,0.1105,0.1418,0.1848,0.2824,0.4738",\ +"0.0676,0.0832,0.0949,0.1262,0.1730,0.2668,0.4621",\ +"0.0402,0.0559,0.0676,0.0988,0.1457,0.2434,0.4191",\ +"-0.0105,0.0012,0.0168,0.0480,0.0988,0.1965,0.3840",\ +"-0.1160,-0.0965,-0.0848,-0.0535,-0.0066,0.0988,0.2824",\ +"-0.3113,-0.2957,-0.2801,-0.2527,-0.2059,-0.1043,0.0832"); + } + } + + + timing() { + timing_type : hold_rising; + related_pin : "A_BIST_CLK"; + when : "A_BIST_MEN" + sdf_cond : "A_BIST_MEN" + + rise_constraint("SIG2SRAM_constraint_template") { + index_1("0.0056,0.0232,0.0400,0.0728,0.1280,0.2440,0.4760"); + index_2("0.0056,0.0232,0.0400,0.0728,0.1280,0.2440,0.4760"); + values ("0.2707,0.2551,0.2395,0.2121,0.1613,0.0598,-0.1395",\ +"0.2863,0.2707,0.2551,0.2238,0.1730,0.0715,-0.1238",\ +"0.2980,0.2824,0.2668,0.2395,0.1887,0.0871,-0.1121",\ +"0.3332,0.3176,0.3020,0.2707,0.2199,0.1184,-0.0809",\ +"0.3762,0.3605,0.3449,0.3176,0.2668,0.1613,-0.0340",\ +"0.4816,0.4621,0.4504,0.4191,0.3723,0.2629,0.0715",\ +"0.6770,0.6613,0.6418,0.6184,0.5637,0.4699,0.2629"); + } + + fall_constraint("SIG2SRAM_constraint_template") { + index_1("0.0056,0.0232,0.0400,0.0728,0.1280,0.2440,0.4760"); + index_2("0.0056,0.0232,0.0400,0.0728,0.1280,0.2440,0.4760"); + values ("0.2590,0.2434,0.2316,0.2004,0.1457,0.0520,-0.1355",\ +"0.2746,0.2590,0.2434,0.2160,0.1613,0.0676,-0.1199",\ +"0.2863,0.2707,0.2590,0.2277,0.1730,0.0832,-0.1082",\ +"0.3215,0.3059,0.2902,0.2590,0.2082,0.1105,-0.0770",\ +"0.3645,0.3488,0.3332,0.3059,0.2551,0.1535,-0.0340",\ +"0.4699,0.4543,0.4387,0.4074,0.3605,0.2551,0.0715",\ +"0.6652,0.6496,0.6340,0.6027,0.5520,0.4621,0.2707"); + } + } + } +pin(A_BIST_MEN) { + direction : input ; + capacitance : 0.00309605 ; + max_transition : "0.476" ; + related_power_pin : VDD; + related_ground_pin : VSS; + internal_power() { + rise_power("scalar"){ + values (0.0448); + } + fall_power("scalar"){ + values (0.0052); + } + } + timing() { + timing_type : setup_rising; + related_pin : "A_BIST_CLK"; + + rise_constraint("SIG2SRAM_constraint_template") { + index_1("0.0056,0.0232,0.0400,0.0728,0.1280,0.2440,0.4760"); + index_2("0.0056,0.0232,0.0400,0.0728,0.1280,0.2440,0.4760"); + values ("0.2043,0.2199,0.2316,0.2668,0.3098,0.4152,0.6066",\ +"0.1887,0.2043,0.2199,0.2512,0.2941,0.3996,0.5949",\ +"0.1730,0.1887,0.2043,0.2355,0.2824,0.3840,0.5793",\ +"0.1418,0.1574,0.1730,0.2043,0.2512,0.3566,0.5480",\ +"0.0949,0.1105,0.1262,0.1574,0.2043,0.3020,0.5051",\ +"-0.0066,0.0090,0.0246,0.0520,0.0988,0.2043,0.3996",\ +"-0.2020,-0.1863,-0.1746,-0.1434,-0.0965,0.0090,0.2082"); + } + + fall_constraint("SIG2SRAM_constraint_template") { + index_1("0.0056,0.0232,0.0400,0.0728,0.1280,0.2440,0.4760"); + index_2("0.0056,0.0232,0.0400,0.0728,0.1280,0.2440,0.4760"); + values ("0.2980,0.3137,0.3254,0.3527,0.4035,0.5012,0.6887",\ +"0.2824,0.2980,0.3098,0.3371,0.3879,0.4855,0.6730",\ +"0.2668,0.2824,0.2941,0.3215,0.3723,0.4699,0.6574",\ +"0.2355,0.2473,0.2629,0.2902,0.3410,0.4387,0.6262",\ +"0.1887,0.2004,0.2160,0.2395,0.2941,0.3918,0.5793",\ +"0.0871,0.1027,0.1145,0.1418,0.1848,0.2746,0.4816",\ +"-0.1082,-0.0965,-0.0809,-0.0496,-0.0027,0.0949,0.2863"); + } + } + + + timing() { + timing_type : hold_rising; + related_pin : "A_BIST_CLK"; + + rise_constraint("SIG2SRAM_constraint_template") { + index_1("0.0056,0.0232,0.0400,0.0728,0.1280,0.2440,0.4760"); + index_2("0.0056,0.0232,0.0400,0.0728,0.1280,0.2440,0.4760"); + values ("0.2512,0.2355,0.2199,0.1926,0.1418,0.0402,-0.1590",\ +"0.2668,0.2512,0.2355,0.2082,0.1574,0.0559,-0.1434",\ +"0.2824,0.2629,0.2512,0.2199,0.1691,0.0715,-0.1316",\ +"0.3137,0.2980,0.2824,0.2512,0.2004,0.0988,-0.0965",\ +"0.3566,0.3410,0.3254,0.2980,0.2473,0.1418,-0.0535",\ +"0.4621,0.4426,0.4309,0.3996,0.3527,0.2473,0.0520",\ +"0.6574,0.6418,0.6262,0.5949,0.5441,0.4465,0.2473"); + } + + fall_constraint("SIG2SRAM_constraint_template") { + index_1("0.0056,0.0232,0.0400,0.0728,0.1280,0.2440,0.4760"); + index_2("0.0056,0.0232,0.0400,0.0728,0.1280,0.2440,0.4760"); + values ("0.2395,0.2238,0.2121,0.1809,0.1301,0.0324,-0.1551",\ +"0.2551,0.2434,0.2277,0.1965,0.1457,0.0480,-0.1395",\ +"0.2707,0.2551,0.2395,0.2082,0.1574,0.0637,-0.1277",\ +"0.3020,0.2863,0.2707,0.2434,0.1926,0.0910,-0.0965",\ +"0.3449,0.3332,0.3176,0.2863,0.2355,0.1379,-0.0496",\ +"0.4504,0.4348,0.4230,0.3918,0.3410,0.2434,0.0559",\ +"0.6457,0.6301,0.6145,0.5910,0.5324,0.4387,0.2512"); + } + } + } +bus(A_BIST_BM) { + bus_type : D_15_0; + direction : input ; + capacitance : 0.00349377 ; + max_transition : "0.476" ; + pin(A_BIST_BM[15:0]) { + related_power_pin : VDD; + related_ground_pin : VSS; + internal_power() { + when : "A_BIST_MEN"; + rise_power("scalar"){ + values (0.0592); + } + fall_power("scalar"){ + values (0.0247); + } + } + internal_power() { + when : "!A_BIST_MEN"; + rise_power("scalar"){ + values (0.0603); + } + fall_power("scalar"){ + values (0.0245); + } + } + } + timing() { + timing_type : setup_rising; + related_pin : "A_BIST_CLK"; + when : "(A_BIST_WEN & A_BIST_MEN)" + sdf_cond : "A_BIST_RW_ACCESS" + + rise_constraint("SIG2SRAM_constraint_template") { + index_1("0.0056,0.0232,0.0400,0.0728,0.1280,0.2440,0.4760"); + index_2("0.0056,0.0232,0.0400,0.0728,0.1280,0.2440,0.4760"); + values ("-0.3858,-0.3702,-0.3565,-0.3243,-0.2774,-0.1729,0.0185",\ +"-0.3908,-0.3752,-0.3615,-0.3293,-0.2824,-0.1779,0.0135",\ +"-0.3953,-0.3796,-0.3660,-0.3337,-0.2869,-0.1824,0.0090",\ +"-0.4051,-0.3895,-0.3758,-0.3436,-0.2967,-0.1922,-0.0008",\ +"-0.4114,-0.3958,-0.3821,-0.3499,-0.3030,-0.1985,-0.0071",\ +"-0.4479,-0.4323,-0.4186,-0.3864,-0.3395,-0.2351,-0.0436",\ +"-0.4988,-0.4832,-0.4695,-0.4373,-0.3904,-0.2859,-0.0945"); + } + + fall_constraint("SIG2SRAM_constraint_template") { + index_1("0.0056,0.0232,0.0400,0.0728,0.1280,0.2440,0.4760"); + index_2("0.0056,0.0232,0.0400,0.0728,0.1280,0.2440,0.4760"); + values ("-0.3477,-0.3331,-0.3194,-0.2911,-0.2403,-0.1426,0.0400",\ +"-0.3527,-0.3381,-0.3244,-0.2961,-0.2453,-0.1477,0.0350",\ +"-0.3572,-0.3425,-0.3288,-0.3005,-0.2497,-0.1521,0.0305",\ +"-0.3670,-0.3524,-0.3387,-0.3104,-0.2596,-0.1619,0.0207",\ +"-0.3734,-0.3587,-0.3450,-0.3167,-0.2659,-0.1683,0.0143",\ +"-0.4098,-0.3952,-0.3815,-0.3532,-0.3024,-0.2048,-0.0222",\ +"-0.4607,-0.4461,-0.4324,-0.4041,-0.3533,-0.2556,-0.0730"); + } + } + + + timing() { + timing_type : hold_rising; + related_pin : "A_BIST_CLK"; + when : "(A_BIST_WEN & A_BIST_MEN)" + sdf_cond : "A_BIST_RW_ACCESS" + + rise_constraint("SIG2SRAM_constraint_template") { + index_1("0.0056,0.0232,0.0400,0.0728,0.1280,0.2440,0.4760"); + index_2("0.0056,0.0232,0.0400,0.0728,0.1280,0.2440,0.4760"); + values ("0.4953,0.4787,0.4660,0.4338,0.3859,0.2824,0.0900",\ +"0.5003,0.4837,0.4710,0.4388,0.3909,0.2874,0.0950",\ +"0.5048,0.4881,0.4754,0.4432,0.3954,0.2919,0.0995",\ +"0.5146,0.4980,0.4853,0.4531,0.4052,0.3017,0.1093",\ +"0.5209,0.5043,0.4916,0.4594,0.4116,0.3080,0.1157",\ +"0.5574,0.5408,0.5281,0.4959,0.4481,0.3445,0.1522",\ +"0.6083,0.5917,0.5790,0.5468,0.4989,0.3954,0.2030"); + } + + fall_constraint("SIG2SRAM_constraint_template") { + index_1("0.0056,0.0232,0.0400,0.0728,0.1280,0.2440,0.4760"); + index_2("0.0056,0.0232,0.0400,0.0728,0.1280,0.2440,0.4760"); + values ("0.4494,0.4348,0.4211,0.3928,0.3430,0.2502,0.0656",\ +"0.4544,0.4398,0.4261,0.3978,0.3480,0.2552,0.0706",\ +"0.4588,0.4442,0.4305,0.4022,0.3524,0.2596,0.0751",\ +"0.4687,0.4540,0.4404,0.4121,0.3622,0.2695,0.0849",\ +"0.4750,0.4604,0.4467,0.4184,0.3686,0.2758,0.0912",\ +"0.5115,0.4969,0.4832,0.4549,0.4051,0.3123,0.1277",\ +"0.5624,0.5477,0.5341,0.5058,0.4559,0.3632,0.1786"); + } + } +} + pin(A_BIST_CLK) { + direction : input; + capacitance : 0.00380014; + max_transition : "0.476"; + clock : "true" ; + pin_func_type : active_rising ; + + timing () { + timing_type : "min_pulse_width"; + related_pin : "A_BIST_CLK"; + rise_constraint("CLKTRAN_constraint_template") { + index_1("0.0056,0.476"); + values("0.21,0.21"); + } + } + + related_power_pin : VDD; + related_ground_pin : VSS; + + internal_power() { + when : "!A_BIST_MEN & !A_BIST_WEN & !A_BIST_REN"; + rise_power("scalar"){ + values (0); + } + fall_power("scalar"){ + values (0); + } + } + internal_power() { + when : "!A_BIST_MEN & A_BIST_WEN & !A_BIST_REN"; + rise_power("scalar"){ + values (0.5466); + } + fall_power("scalar"){ + values (0); + } + } + internal_power() { + when : "A_BIST_MEN & A_BIST_WEN & !A_BIST_REN"; + rise_power("scalar"){ + values (32.9180); + } + fall_power("scalar"){ + values (0); + } + } + internal_power() { + when : "A_BIST_MEN & A_BIST_WEN & A_BIST_REN"; + rise_power("scalar"){ + values (33.7600); + } + fall_power("scalar"){ + values (0); + } + } + internal_power() { + when : "A_BIST_MEN & !A_BIST_WEN & A_BIST_REN"; + rise_power("scalar"){ + values (26.4863); + } + fall_power("scalar"){ + values (0); + } + } + internal_power() { + when : "!A_BIST_MEN & !A_BIST_WEN & A_BIST_REN"; + rise_power("scalar"){ + values (0.3253); + } + fall_power("scalar"){ + values (0); + } + } + internal_power() { + when : "!A_BIST_MEN & A_BIST_WEN & A_BIST_REN"; + rise_power("scalar"){ + values (0.7651); + } + fall_power("scalar"){ + values (0); + } + } + internal_power() { + when : "A_BIST_MEN & !A_BIST_WEN & !A_BIST_REN"; + rise_power("scalar"){ + values (0); + } + fall_power("scalar"){ + values (0); + } + } + } + bus(A_BIST_DIN) { + bus_type : D_15_0; + direction : input ; + capacitance : 0.00393889 ; + memory_write() { + address : A_BIST_ADDR ; + clocked_on : A_BIST_CLK; + } + + max_transition : "0.476" ; + pin(A_BIST_DIN[15:0]) { + related_power_pin : VDD; + related_ground_pin : VSS; + internal_power() { + when : "A_BIST_MEN"; + rise_power("scalar"){ + values (0.0592); + } + fall_power("scalar"){ + values (0.0247); + } + } + internal_power() { + when : "!A_BIST_MEN"; + rise_power("scalar"){ + values (0.0603); + } + fall_power("scalar"){ + values (0.0245); + } + } + } + timing() { + timing_type : setup_rising; + related_pin : "A_BIST_CLK"; + when : "(A_BIST_WEN & A_BIST_MEN)"; + sdf_cond : "A_BIST_W_ACCESS"; + + rise_constraint("SIG2SRAM_constraint_template") { + index_1("0.0056,0.0232,0.0400,0.0728,0.1280,0.2440,0.4760"); + index_2("0.0056,0.0232,0.0400,0.0728,0.1280,0.2440,0.4760"); + values ("-0.3858,-0.3702,-0.3565,-0.3243,-0.2774,-0.1729,0.0185",\ +"-0.3908,-0.3752,-0.3615,-0.3293,-0.2824,-0.1779,0.0135",\ +"-0.3953,-0.3796,-0.3660,-0.3337,-0.2869,-0.1824,0.0090",\ +"-0.4051,-0.3895,-0.3758,-0.3436,-0.2967,-0.1922,-0.0008",\ +"-0.4114,-0.3958,-0.3821,-0.3499,-0.3030,-0.1985,-0.0071",\ +"-0.4479,-0.4323,-0.4186,-0.3864,-0.3395,-0.2351,-0.0436",\ +"-0.4988,-0.4832,-0.4695,-0.4373,-0.3904,-0.2859,-0.0945"); + } + + fall_constraint("SIG2SRAM_constraint_template") { + index_1("0.0056,0.0232,0.0400,0.0728,0.1280,0.2440,0.4760"); + index_2("0.0056,0.0232,0.0400,0.0728,0.1280,0.2440,0.4760"); + values ("-0.3477,-0.3331,-0.3194,-0.2911,-0.2403,-0.1426,0.0400",\ +"-0.3527,-0.3381,-0.3244,-0.2961,-0.2453,-0.1477,0.0350",\ +"-0.3572,-0.3425,-0.3288,-0.3005,-0.2497,-0.1521,0.0305",\ +"-0.3670,-0.3524,-0.3387,-0.3104,-0.2596,-0.1619,0.0207",\ +"-0.3734,-0.3587,-0.3450,-0.3167,-0.2659,-0.1683,0.0143",\ +"-0.4098,-0.3952,-0.3815,-0.3532,-0.3024,-0.2048,-0.0222",\ +"-0.4607,-0.4461,-0.4324,-0.4041,-0.3533,-0.2556,-0.0730"); + } + } + + timing() { + timing_type : hold_rising; + related_pin : "A_BIST_CLK"; + when : "(A_BIST_WEN & A_BIST_MEN)"; + sdf_cond : "A_BIST_W_ACCESS"; + + rise_constraint("SIG2SRAM_constraint_template") { + index_1("0.0056,0.0232,0.0400,0.0728,0.1280,0.2440,0.4760"); + index_2("0.0056,0.0232,0.0400,0.0728,0.1280,0.2440,0.4760"); + values ("0.4953,0.4787,0.4660,0.4338,0.3859,0.2824,0.0900",\ +"0.5003,0.4837,0.4710,0.4388,0.3909,0.2874,0.0950",\ +"0.5048,0.4881,0.4754,0.4432,0.3954,0.2919,0.0995",\ +"0.5146,0.4980,0.4853,0.4531,0.4052,0.3017,0.1093",\ +"0.5209,0.5043,0.4916,0.4594,0.4116,0.3080,0.1157",\ +"0.5574,0.5408,0.5281,0.4959,0.4481,0.3445,0.1522",\ +"0.6083,0.5917,0.5790,0.5468,0.4989,0.3954,0.2030"); + } + + fall_constraint("SIG2SRAM_constraint_template") { + index_1("0.0056,0.0232,0.0400,0.0728,0.1280,0.2440,0.4760"); + index_2("0.0056,0.0232,0.0400,0.0728,0.1280,0.2440,0.4760"); + values ("0.4494,0.4348,0.4211,0.3928,0.3430,0.2502,0.0656",\ +"0.4544,0.4398,0.4261,0.3978,0.3480,0.2552,0.0706",\ +"0.4588,0.4442,0.4305,0.4022,0.3524,0.2596,0.0751",\ +"0.4687,0.4540,0.4404,0.4121,0.3622,0.2695,0.0849",\ +"0.4750,0.4604,0.4467,0.4184,0.3686,0.2758,0.0912",\ +"0.5115,0.4969,0.4832,0.4549,0.4051,0.3123,0.1277",\ +"0.5624,0.5477,0.5341,0.5058,0.4559,0.3632,0.1786"); + } + } + } + +bus(A_DOUT) { + + bus_type : D_15_0; + direction : output ; + capacitance : 0 ; + max_capacitance : 0.064 ; + memory_read() { + address : A_ADDR ; + } + pin(A_DOUT[15:0]) { + related_power_pin : VDD; + related_ground_pin : VSS; + internal_power() { + rise_power("scalar") { + values (0); + } + fall_power("scalar") { + values (0); + } + } + } + timing() { + related_pin : "A_CLK"; + timing_type : rising_edge ; + timing_sense : non_unate ; + + cell_rise(SIG2SRAM_delay_template) { + index_1("0.0056,0.0232,0.0400,0.0728,0.1280,0.2440,0.4760"); + index_2("0.0008,0.0014,0.0051,0.0100,0.0339,0.0640"); + values ("4.3139,4.3155,4.3232,4.3319,4.3643,4.4004",\ +"4.3240,4.3257,4.3333,4.3420,4.3744,4.4105",\ +"4.3287,4.3303,4.3379,4.3466,4.3790,4.4152",\ +"4.3365,4.3381,4.3457,4.3544,4.3868,4.4230",\ +"4.3440,4.3456,4.3532,4.3620,4.3943,4.4305",\ +"4.3791,4.3807,4.3883,4.3970,4.4294,4.4656",\ +"4.4324,4.4340,4.4417,4.4504,4.4828,4.5189"); + } + cell_fall(SIG2SRAM_delay_template) { + index_1("0.0056,0.0232,0.0400,0.0728,0.1280,0.2440,0.4760"); + index_2("0.0008,0.0014,0.0051,0.0100,0.0339,0.0640"); + values ("4.2536,4.2550,4.2611,4.2682,4.2947,4.3209",\ +"4.2638,4.2651,4.2712,4.2783,4.3048,4.3310",\ +"4.2684,4.2697,4.2758,4.2829,4.3094,4.3357",\ +"4.2762,4.2775,4.2836,4.2907,4.3172,4.3435",\ +"4.2837,4.2851,4.2911,4.2983,4.3248,4.3510",\ +"4.3188,4.3201,4.3262,4.3333,4.3598,4.3861",\ +"4.3721,4.3735,4.3796,4.3867,4.4132,4.4394"); + } + + rise_transition(SRAM_load_template) { + index_1("0.0008,0.0014,0.0051,0.0100,0.0339,0.0640"); + values ("0.0326,0.0341,0.0428,0.0518,0.0923,0.1492"); + } + fall_transition(SRAM_load_template) { + index_1("0.0008,0.0014,0.0051,0.0100,0.0339,0.0640"); + values ("0.0254,0.0265,0.0335,0.0402,0.0707,0.1039"); + } + } +} + pin(B_DLY) { + direction : input ; + capacitance : 0.00401111 ; + max_transition : "1" ; + related_power_pin : VDD; + related_ground_pin : VSS; + internal_power() { + rise_power("scalar") { + values (0); + } + fall_power("scalar") { + values (0); + } + } + } + +bus(B_ADDR) { + bus_type : A_9_0; + direction : input ; + capacitance : 0.0121077 ; + pin(B_ADDR[0]) { + capacitance : 0.00570093 ; + } + pin(B_ADDR[1]) { + capacitance : 0.00764555 ; + } + pin(B_ADDR[2]) { + capacitance : 0.0105375 ; + } + pin(B_ADDR[3]) { + capacitance : 0.0067894 ; + } + pin(B_ADDR[4]) { + capacitance : 0.00630967 ; + } + pin(B_ADDR[5]) { + capacitance : 0.0104132 ; + } + pin(B_ADDR[6]) { + capacitance : 0.0131402 ; + } + pin(B_ADDR[7]) { + capacitance : 0.0105203 ; + } + pin(B_ADDR[8]) { + capacitance : 0.00910078 ; + } + max_transition : "0.476" ; + pin(B_ADDR[9:0]) { + related_power_pin : VDD; + related_ground_pin : VSS; + internal_power() { + when : "B_MEN"; + rise_power("scalar"){ + values (0.0120); + } + fall_power("scalar"){ + values (0.0063); + } + } + internal_power() { + when : "!B_MEN"; + rise_power("scalar"){ + values (0.0204); + } + fall_power("scalar"){ + values (0.0012); + } + } + } + timing() { + timing_type : setup_rising; + related_pin : "B_CLK"; + when : "((B_WEN | B_REN)& B_MEN)" + sdf_cond : "B_RW_ACCESS" + + rise_constraint("SIG2SRAM_constraint_template") { + index_1("0.0056,0.0232,0.0400,0.0728,0.1280,0.2440,0.4760"); + index_2("0.0056,0.0232,0.0400,0.0728,0.1280,0.2440,0.4760"); + values ("-0.4168,-0.3973,-0.3855,-0.3543,-0.3074,-0.2020,-0.0027",\ +"-0.4324,-0.4129,-0.4012,-0.3699,-0.3191,-0.2176,-0.0184",\ +"-0.4441,-0.4285,-0.4129,-0.3816,-0.3309,-0.2293,-0.0301",\ +"-0.4793,-0.4598,-0.4441,-0.4129,-0.3660,-0.2645,-0.0652",\ +"-0.5223,-0.5066,-0.4910,-0.4598,-0.4129,-0.3074,-0.1121",\ +"-0.6199,-0.6082,-0.5926,-0.5613,-0.5145,-0.4129,-0.2137",\ +"-0.8191,-0.8074,-0.7840,-0.7566,-0.7098,-0.6082,-0.4051"); + } + + fall_constraint("SIG2SRAM_constraint_template") { + index_1("0.0056,0.0232,0.0400,0.0728,0.1280,0.2440,0.4760"); + index_2("0.0056,0.0232,0.0400,0.0728,0.1280,0.2440,0.4760"); + values ("-0.3309,-0.3113,-0.2996,-0.2684,-0.2176,-0.1238,0.0637",\ +"-0.3465,-0.3309,-0.3152,-0.2840,-0.2332,-0.1395,0.0480",\ +"-0.3582,-0.3426,-0.3270,-0.2996,-0.2488,-0.1512,0.0324",\ +"-0.3895,-0.3738,-0.3582,-0.3309,-0.2801,-0.1863,0.0051",\ +"-0.4363,-0.4207,-0.4051,-0.3777,-0.3230,-0.2293,-0.0379",\ +"-0.5379,-0.5223,-0.5066,-0.4793,-0.4285,-0.3309,-0.1434",\ +"-0.7332,-0.7176,-0.7020,-0.6746,-0.6238,-0.5262,-0.3387"); + } + } + + + timing() { + timing_type : hold_rising; + related_pin : "B_CLK"; + when : "((B_WEN | B_REN)& B_MEN)" + sdf_cond : "B_RW_ACCESS" + + rise_constraint("SIG2SRAM_constraint_template") { + index_1("0.0056,0.0232,0.0400,0.0728,0.1280,0.2440,0.4760"); + index_2("0.0056,0.0232,0.0400,0.0728,0.1280,0.2440,0.4760"); + values ("0.5246,0.5051,0.4895,0.4582,0.4113,0.3059,0.1066",\ +"0.5402,0.5207,0.5051,0.4777,0.4270,0.3215,0.1223",\ +"0.5520,0.5324,0.5168,0.4895,0.4387,0.3371,0.1340",\ +"0.5832,0.5676,0.5520,0.5207,0.4738,0.3684,0.1691",\ +"0.6301,0.6105,0.5949,0.5676,0.5168,0.4113,0.2160",\ +"0.7316,0.7121,0.7004,0.6691,0.6223,0.5168,0.3176",\ +"0.9270,0.9230,0.8957,0.8645,0.8137,0.7121,0.5168"); + } + + fall_constraint("SIG2SRAM_constraint_template") { + index_1("0.0056,0.0232,0.0400,0.0728,0.1280,0.2440,0.4760"); + index_2("0.0056,0.0232,0.0400,0.0728,0.1280,0.2440,0.4760"); + values ("0.4309,0.4152,0.4035,0.3684,0.3215,0.2277,0.0363",\ +"0.4465,0.4309,0.4152,0.3879,0.3371,0.2395,0.0559",\ +"0.4582,0.4426,0.4309,0.3996,0.3488,0.2551,0.0715",\ +"0.4934,0.4777,0.4621,0.4348,0.3840,0.2863,0.0988",\ +"0.5363,0.5207,0.5051,0.4777,0.4270,0.3332,0.1418",\ +"0.6379,0.6262,0.6105,0.5793,0.5324,0.4348,0.2434",\ +"0.8332,0.8215,0.8059,0.7707,0.7238,0.6301,0.4387"); + } + } +} +pin(B_WEN) { + direction : input ; + capacitance : 0.00324098 ; + max_transition : "0.476" ; + related_power_pin : VDD; + related_ground_pin : VSS; + internal_power() { + when : "B_MEN"; + rise_power("scalar"){ + values (0.0046); + } + fall_power("scalar"){ + values (0.0039); + } + } + internal_power() { + when : "!B_MEN"; + rise_power("scalar"){ + values (0.0043); + } + fall_power("scalar"){ + values (0.0040); + } + } + timing() { + timing_type : setup_rising; + related_pin : "B_CLK"; + when : "B_MEN" + sdf_cond : "B_MEN" + + rise_constraint("SIG2SRAM_constraint_template") { + index_1("0.0056,0.0232,0.0400,0.0728,0.1280,0.2440,0.4760"); + index_2("0.0056,0.0232,0.0400,0.0728,0.1280,0.2440,0.4760"); + values ("0.2043,0.2199,0.2316,0.2629,0.3059,0.4113,0.6066",\ +"0.1887,0.2043,0.2160,0.2473,0.2941,0.3957,0.5949",\ +"0.1691,0.1848,0.2004,0.2316,0.2785,0.3801,0.5754",\ +"0.1379,0.1574,0.1691,0.2004,0.2473,0.3527,0.5480",\ +"0.0910,0.1066,0.1223,0.1535,0.2004,0.2980,0.4973",\ +"-0.0105,0.0051,0.0207,0.0520,0.0949,0.2004,0.3957",\ +"-0.2059,-0.1902,-0.1746,-0.1473,-0.1004,0.0051,0.2004"); + } + + fall_constraint("SIG2SRAM_constraint_template") { + index_1("0.0056,0.0232,0.0400,0.0728,0.1280,0.2440,0.4760"); + index_2("0.0056,0.0232,0.0400,0.0728,0.1280,0.2440,0.4760"); + values ("0.2941,0.3098,0.3215,0.3488,0.4035,0.4973,0.6887",\ +"0.2785,0.2941,0.3059,0.3332,0.3840,0.4816,0.6691",\ +"0.2629,0.2785,0.2902,0.3176,0.3684,0.4660,0.6535",\ +"0.2316,0.2473,0.2590,0.2863,0.3410,0.4348,0.6262",\ +"0.1848,0.2004,0.2121,0.2395,0.2902,0.3879,0.5754",\ +"0.0832,0.0988,0.1105,0.1379,0.1809,0.2746,0.4699",\ +"-0.1121,-0.0965,-0.0848,-0.0535,-0.0066,0.0910,0.2824"); + } + } + + + timing() { + timing_type : hold_rising; + related_pin : "B_CLK"; + when : "B_MEN" + sdf_cond : "B_MEN" + + rise_constraint("SIG2SRAM_constraint_template") { + index_1("0.0056,0.0232,0.0400,0.0728,0.1280,0.2440,0.4760"); + index_2("0.0056,0.0232,0.0400,0.0728,0.1280,0.2440,0.4760"); + values ("0.2473,0.2316,0.2160,0.1887,0.1379,0.0363,-0.1629",\ +"0.2629,0.2473,0.2316,0.2043,0.1535,0.0520,-0.1473",\ +"0.2785,0.2590,0.2434,0.2160,0.1652,0.0676,-0.1355",\ +"0.3098,0.2941,0.2785,0.2473,0.1965,0.0910,-0.1043",\ +"0.3527,0.3371,0.3215,0.2941,0.2434,0.1418,-0.0574",\ +"0.4582,0.4426,0.4270,0.3957,0.3488,0.2434,0.0480",\ +"0.6535,0.6379,0.6184,0.5910,0.5402,0.4426,0.2434"); + } + + fall_constraint("SIG2SRAM_constraint_template") { + index_1("0.0056,0.0232,0.0400,0.0728,0.1280,0.2440,0.4760"); + index_2("0.0056,0.0232,0.0400,0.0728,0.1280,0.2440,0.4760"); + values ("0.2395,0.2238,0.2121,0.1809,0.1301,0.0324,-0.1551",\ +"0.2551,0.2395,0.2277,0.1965,0.1457,0.0480,-0.1395",\ +"0.2668,0.2551,0.2395,0.2082,0.1574,0.0637,-0.1277",\ +"0.3020,0.2863,0.2707,0.2395,0.1887,0.0910,-0.0965",\ +"0.3449,0.3293,0.3176,0.2863,0.2355,0.1379,-0.0496",\ +"0.4504,0.4348,0.4191,0.3879,0.3371,0.2395,0.0559",\ +"0.6457,0.6301,0.6145,0.5871,0.5324,0.4309,0.2512"); + } + } + } +pin(B_REN) { + direction : input ; + capacitance : 0.00381634 ; + max_transition : "0.476" ; + related_power_pin : VDD; + related_ground_pin : VSS; + internal_power() { + when : "B_MEN"; + rise_power("scalar"){ + values (0.0061); + } + fall_power("scalar"){ + values (0.0021); + } + } + internal_power() { + when : "!B_MEN"; + rise_power("scalar"){ + values (0.0062); + } + fall_power("scalar"){ + values (0.0025); + } + } + timing() { + timing_type : setup_rising; + related_pin : "B_CLK"; + when : "B_MEN" + sdf_cond : "B_MEN" + + rise_constraint("SIG2SRAM_constraint_template") { + index_1("0.0056,0.0232,0.0400,0.0728,0.1280,0.2440,0.4760"); + index_2("0.0056,0.0232,0.0400,0.0728,0.1280,0.2440,0.4760"); + values ("-0.0301,-0.0145,0.0012,0.0324,0.0793,0.1809,0.3762",\ +"-0.0457,-0.0301,-0.0145,0.0168,0.0637,0.1613,0.3605",\ +"-0.0574,-0.0418,-0.0262,0.0051,0.0520,0.1496,0.3449",\ +"-0.0926,-0.0730,-0.0574,-0.0262,0.0207,0.1184,0.3137",\ +"-0.1395,-0.1238,-0.1082,-0.0770,-0.0301,0.0715,0.2707",\ +"-0.2410,-0.2254,-0.2098,-0.1746,-0.1355,-0.0340,0.1652",\ +"-0.4402,-0.4207,-0.4051,-0.3738,-0.3270,-0.2293,-0.0340"); + } + + fall_constraint("SIG2SRAM_constraint_template") { + index_1("0.0056,0.0232,0.0400,0.0728,0.1280,0.2440,0.4760"); + index_2("0.0056,0.0232,0.0400,0.0728,0.1280,0.2440,0.4760"); + values ("0.0988,0.1145,0.1262,0.1535,0.2043,0.3020,0.4855",\ +"0.0832,0.0988,0.1105,0.1418,0.1848,0.2824,0.4738",\ +"0.0676,0.0832,0.0949,0.1262,0.1730,0.2668,0.4621",\ +"0.0402,0.0559,0.0676,0.0988,0.1457,0.2434,0.4191",\ +"-0.0105,0.0012,0.0168,0.0480,0.0988,0.1965,0.3840",\ +"-0.1160,-0.0965,-0.0848,-0.0535,-0.0066,0.0988,0.2824",\ +"-0.3113,-0.2957,-0.2801,-0.2527,-0.2059,-0.1043,0.0832"); + } + } + + + timing() { + timing_type : hold_rising; + related_pin : "B_CLK"; + when : "B_MEN" + sdf_cond : "B_MEN" + + rise_constraint("SIG2SRAM_constraint_template") { + index_1("0.0056,0.0232,0.0400,0.0728,0.1280,0.2440,0.4760"); + index_2("0.0056,0.0232,0.0400,0.0728,0.1280,0.2440,0.4760"); + values ("0.2707,0.2551,0.2395,0.2121,0.1613,0.0598,-0.1395",\ +"0.2863,0.2707,0.2551,0.2238,0.1730,0.0715,-0.1238",\ +"0.2980,0.2824,0.2668,0.2395,0.1887,0.0871,-0.1121",\ +"0.3332,0.3176,0.3020,0.2707,0.2199,0.1184,-0.0809",\ +"0.3762,0.3605,0.3449,0.3176,0.2668,0.1613,-0.0340",\ +"0.4816,0.4621,0.4504,0.4191,0.3723,0.2629,0.0715",\ +"0.6770,0.6613,0.6418,0.6184,0.5637,0.4699,0.2629"); + } + + fall_constraint("SIG2SRAM_constraint_template") { + index_1("0.0056,0.0232,0.0400,0.0728,0.1280,0.2440,0.4760"); + index_2("0.0056,0.0232,0.0400,0.0728,0.1280,0.2440,0.4760"); + values ("0.2590,0.2434,0.2316,0.2004,0.1457,0.0520,-0.1355",\ +"0.2746,0.2590,0.2434,0.2160,0.1613,0.0676,-0.1199",\ +"0.2863,0.2707,0.2590,0.2277,0.1730,0.0832,-0.1082",\ +"0.3215,0.3059,0.2902,0.2590,0.2082,0.1105,-0.0770",\ +"0.3645,0.3488,0.3332,0.3059,0.2551,0.1535,-0.0340",\ +"0.4699,0.4543,0.4387,0.4074,0.3605,0.2551,0.0715",\ +"0.6652,0.6496,0.6340,0.6027,0.5520,0.4621,0.2707"); + } + } + } +pin(B_MEN) { + direction : input ; + capacitance : 0.00309605 ; + max_transition : "0.476" ; + related_power_pin : VDD; + related_ground_pin : VSS; + internal_power() { + rise_power("scalar"){ + values (0.0448); + } + fall_power("scalar"){ + values (0.0052); + } + } + timing() { + timing_type : setup_rising; + related_pin : "B_CLK"; + + rise_constraint("SIG2SRAM_constraint_template") { + index_1("0.0056,0.0232,0.0400,0.0728,0.1280,0.2440,0.4760"); + index_2("0.0056,0.0232,0.0400,0.0728,0.1280,0.2440,0.4760"); + values ("0.2043,0.2199,0.2316,0.2668,0.3098,0.4152,0.6066",\ +"0.1887,0.2043,0.2199,0.2512,0.2941,0.3996,0.5949",\ +"0.1730,0.1887,0.2043,0.2355,0.2824,0.3840,0.5793",\ +"0.1418,0.1574,0.1730,0.2043,0.2512,0.3566,0.5480",\ +"0.0949,0.1105,0.1262,0.1574,0.2043,0.3020,0.5051",\ +"-0.0066,0.0090,0.0246,0.0520,0.0988,0.2043,0.3996",\ +"-0.2020,-0.1863,-0.1746,-0.1434,-0.0965,0.0090,0.2082"); + } + + fall_constraint("SIG2SRAM_constraint_template") { + index_1("0.0056,0.0232,0.0400,0.0728,0.1280,0.2440,0.4760"); + index_2("0.0056,0.0232,0.0400,0.0728,0.1280,0.2440,0.4760"); + values ("0.2980,0.3137,0.3254,0.3527,0.4035,0.5012,0.6887",\ +"0.2824,0.2980,0.3098,0.3371,0.3879,0.4855,0.6730",\ +"0.2668,0.2824,0.2941,0.3215,0.3723,0.4699,0.6574",\ +"0.2355,0.2473,0.2629,0.2902,0.3410,0.4387,0.6262",\ +"0.1887,0.2004,0.2160,0.2395,0.2941,0.3918,0.5793",\ +"0.0871,0.1027,0.1145,0.1418,0.1848,0.2746,0.4816",\ +"-0.1082,-0.0965,-0.0809,-0.0496,-0.0027,0.0949,0.2863"); + } + } + + + timing() { + timing_type : hold_rising; + related_pin : "B_CLK"; + + rise_constraint("SIG2SRAM_constraint_template") { + index_1("0.0056,0.0232,0.0400,0.0728,0.1280,0.2440,0.4760"); + index_2("0.0056,0.0232,0.0400,0.0728,0.1280,0.2440,0.4760"); + values ("0.2512,0.2355,0.2199,0.1926,0.1418,0.0402,-0.1590",\ +"0.2668,0.2512,0.2355,0.2082,0.1574,0.0559,-0.1434",\ +"0.2824,0.2629,0.2512,0.2199,0.1691,0.0715,-0.1316",\ +"0.3137,0.2980,0.2824,0.2512,0.2004,0.0988,-0.0965",\ +"0.3566,0.3410,0.3254,0.2980,0.2473,0.1418,-0.0535",\ +"0.4621,0.4426,0.4309,0.3996,0.3527,0.2473,0.0520",\ +"0.6574,0.6418,0.6262,0.5949,0.5441,0.4465,0.2473"); + } + + fall_constraint("SIG2SRAM_constraint_template") { + index_1("0.0056,0.0232,0.0400,0.0728,0.1280,0.2440,0.4760"); + index_2("0.0056,0.0232,0.0400,0.0728,0.1280,0.2440,0.4760"); + values ("0.2395,0.2238,0.2121,0.1809,0.1301,0.0324,-0.1551",\ +"0.2551,0.2434,0.2277,0.1965,0.1457,0.0480,-0.1395",\ +"0.2707,0.2551,0.2395,0.2082,0.1574,0.0637,-0.1277",\ +"0.3020,0.2863,0.2707,0.2434,0.1926,0.0910,-0.0965",\ +"0.3449,0.3332,0.3176,0.2863,0.2355,0.1379,-0.0496",\ +"0.4504,0.4348,0.4230,0.3918,0.3410,0.2434,0.0559",\ +"0.6457,0.6301,0.6145,0.5910,0.5324,0.4387,0.2512"); + } + } + } +bus(B_BM) { + bus_type : D_15_0; + direction : input ; + capacitance : 0.00312518 ; + max_transition : "0.476" ; + pin(B_BM[15:0]) { + related_power_pin : VDD; + related_ground_pin : VSS; + internal_power() { + when : "B_MEN"; + rise_power("scalar"){ + values (0.0592); + } + fall_power("scalar"){ + values (0.0247); + } + } + internal_power() { + when : "!B_MEN"; + rise_power("scalar"){ + values (0.0603); + } + fall_power("scalar"){ + values (0.0245); + } + } + } + timing() { + timing_type : setup_rising; + related_pin : "B_CLK"; + when : "(B_WEN & B_MEN)" + sdf_cond : "B_RW_ACCESS" + + rise_constraint("SIG2SRAM_constraint_template") { + index_1("0.0056,0.0232,0.0400,0.0728,0.1280,0.2440,0.4760"); + index_2("0.0056,0.0232,0.0400,0.0728,0.1280,0.2440,0.4760"); + values ("-0.3858,-0.3702,-0.3565,-0.3243,-0.2774,-0.1729,0.0185",\ +"-0.3908,-0.3752,-0.3615,-0.3293,-0.2824,-0.1779,0.0135",\ +"-0.3953,-0.3796,-0.3660,-0.3337,-0.2869,-0.1824,0.0090",\ +"-0.4051,-0.3895,-0.3758,-0.3436,-0.2967,-0.1922,-0.0008",\ +"-0.4114,-0.3958,-0.3821,-0.3499,-0.3030,-0.1985,-0.0071",\ +"-0.4479,-0.4323,-0.4186,-0.3864,-0.3395,-0.2351,-0.0436",\ +"-0.4988,-0.4832,-0.4695,-0.4373,-0.3904,-0.2859,-0.0945"); + } + + fall_constraint("SIG2SRAM_constraint_template") { + index_1("0.0056,0.0232,0.0400,0.0728,0.1280,0.2440,0.4760"); + index_2("0.0056,0.0232,0.0400,0.0728,0.1280,0.2440,0.4760"); + values ("-0.3477,-0.3331,-0.3194,-0.2911,-0.2403,-0.1426,0.0400",\ +"-0.3527,-0.3381,-0.3244,-0.2961,-0.2453,-0.1477,0.0350",\ +"-0.3572,-0.3425,-0.3288,-0.3005,-0.2497,-0.1521,0.0305",\ +"-0.3670,-0.3524,-0.3387,-0.3104,-0.2596,-0.1619,0.0207",\ +"-0.3734,-0.3587,-0.3450,-0.3167,-0.2659,-0.1683,0.0143",\ +"-0.4098,-0.3952,-0.3815,-0.3532,-0.3024,-0.2048,-0.0222",\ +"-0.4607,-0.4461,-0.4324,-0.4041,-0.3533,-0.2556,-0.0730"); + } + } + + + timing() { + timing_type : hold_rising; + related_pin : "B_CLK"; + when : "(B_WEN & B_MEN)" + sdf_cond : "B_RW_ACCESS" + + rise_constraint("SIG2SRAM_constraint_template") { + index_1("0.0056,0.0232,0.0400,0.0728,0.1280,0.2440,0.4760"); + index_2("0.0056,0.0232,0.0400,0.0728,0.1280,0.2440,0.4760"); + values ("0.4953,0.4787,0.4660,0.4338,0.3859,0.2824,0.0900",\ +"0.5003,0.4837,0.4710,0.4388,0.3909,0.2874,0.0950",\ +"0.5048,0.4881,0.4754,0.4432,0.3954,0.2919,0.0995",\ +"0.5146,0.4980,0.4853,0.4531,0.4052,0.3017,0.1093",\ +"0.5209,0.5043,0.4916,0.4594,0.4116,0.3080,0.1157",\ +"0.5574,0.5408,0.5281,0.4959,0.4481,0.3445,0.1522",\ +"0.6083,0.5917,0.5790,0.5468,0.4989,0.3954,0.2030"); + } + + fall_constraint("SIG2SRAM_constraint_template") { + index_1("0.0056,0.0232,0.0400,0.0728,0.1280,0.2440,0.4760"); + index_2("0.0056,0.0232,0.0400,0.0728,0.1280,0.2440,0.4760"); + values ("0.4494,0.4348,0.4211,0.3928,0.3430,0.2502,0.0656",\ +"0.4544,0.4398,0.4261,0.3978,0.3480,0.2552,0.0706",\ +"0.4588,0.4442,0.4305,0.4022,0.3524,0.2596,0.0751",\ +"0.4687,0.4540,0.4404,0.4121,0.3622,0.2695,0.0849",\ +"0.4750,0.4604,0.4467,0.4184,0.3686,0.2758,0.0912",\ +"0.5115,0.4969,0.4832,0.4549,0.4051,0.3123,0.1277",\ +"0.5624,0.5477,0.5341,0.5058,0.4559,0.3632,0.1786"); + } + } +} + pin(B_CLK) { + direction : input; + capacitance : 0.00380014; + max_transition : "0.476"; + clock : "true" ; + pin_func_type : active_rising ; + + timing () { + timing_type : "min_pulse_width"; + related_pin : "B_CLK"; + rise_constraint("CLKTRAN_constraint_template") { + index_1("0.0056,0.476"); + values("0.21,0.21"); + } + } + + related_power_pin : VDD; + related_ground_pin : VSS; + + internal_power() { + when : "!B_MEN & !B_WEN & !B_REN"; + rise_power("scalar"){ + values (0); + } + fall_power("scalar"){ + values (0); + } + } + internal_power() { + when : "!B_MEN & B_WEN & !B_REN"; + rise_power("scalar"){ + values (0.5466); + } + fall_power("scalar"){ + values (0); + } + } + internal_power() { + when : "B_MEN & B_WEN & !B_REN"; + rise_power("scalar"){ + values (32.9180); + } + fall_power("scalar"){ + values (0); + } + } + internal_power() { + when : "B_MEN & B_WEN & B_REN"; + rise_power("scalar"){ + values (33.7600); + } + fall_power("scalar"){ + values (0); + } + } + internal_power() { + when : "B_MEN & !B_WEN & B_REN"; + rise_power("scalar"){ + values (26.4863); + } + fall_power("scalar"){ + values (0); + } + } + internal_power() { + when : "!B_MEN & !B_WEN & B_REN"; + rise_power("scalar"){ + values (0.3253); + } + fall_power("scalar"){ + values (0); + } + } + internal_power() { + when : "!B_MEN & B_WEN & B_REN"; + rise_power("scalar"){ + values (0.7651); + } + fall_power("scalar"){ + values (0); + } + } + internal_power() { + when : "B_MEN & !B_WEN & !B_REN"; + rise_power("scalar"){ + values (0); + } + fall_power("scalar"){ + values (0); + } + } + } + bus(B_DIN) { + bus_type : D_15_0; + direction : input ; + capacitance : 0.00461776 ; + memory_write() { + address : B_ADDR ; + clocked_on : B_CLK; + } + + max_transition : "0.476" ; + pin(B_DIN[15:0]) { + related_power_pin : VDD; + related_ground_pin : VSS; + internal_power() { + when : "B_MEN"; + rise_power("scalar"){ + values (0.0592); + } + fall_power("scalar"){ + values (0.0247); + } + } + internal_power() { + when : "!B_MEN"; + rise_power("scalar"){ + values (0.0603); + } + fall_power("scalar"){ + values (0.0245); + } + } + } + timing() { + timing_type : setup_rising; + related_pin : "B_CLK"; + when : "(B_WEN & B_MEN)"; + sdf_cond : "B_W_ACCESS"; + + rise_constraint("SIG2SRAM_constraint_template") { + index_1("0.0056,0.0232,0.0400,0.0728,0.1280,0.2440,0.4760"); + index_2("0.0056,0.0232,0.0400,0.0728,0.1280,0.2440,0.4760"); + values ("-0.3858,-0.3702,-0.3565,-0.3243,-0.2774,-0.1729,0.0185",\ +"-0.3908,-0.3752,-0.3615,-0.3293,-0.2824,-0.1779,0.0135",\ +"-0.3953,-0.3796,-0.3660,-0.3337,-0.2869,-0.1824,0.0090",\ +"-0.4051,-0.3895,-0.3758,-0.3436,-0.2967,-0.1922,-0.0008",\ +"-0.4114,-0.3958,-0.3821,-0.3499,-0.3030,-0.1985,-0.0071",\ +"-0.4479,-0.4323,-0.4186,-0.3864,-0.3395,-0.2351,-0.0436",\ +"-0.4988,-0.4832,-0.4695,-0.4373,-0.3904,-0.2859,-0.0945"); + } + + fall_constraint("SIG2SRAM_constraint_template") { + index_1("0.0056,0.0232,0.0400,0.0728,0.1280,0.2440,0.4760"); + index_2("0.0056,0.0232,0.0400,0.0728,0.1280,0.2440,0.4760"); + values ("-0.3477,-0.3331,-0.3194,-0.2911,-0.2403,-0.1426,0.0400",\ +"-0.3527,-0.3381,-0.3244,-0.2961,-0.2453,-0.1477,0.0350",\ +"-0.3572,-0.3425,-0.3288,-0.3005,-0.2497,-0.1521,0.0305",\ +"-0.3670,-0.3524,-0.3387,-0.3104,-0.2596,-0.1619,0.0207",\ +"-0.3734,-0.3587,-0.3450,-0.3167,-0.2659,-0.1683,0.0143",\ +"-0.4098,-0.3952,-0.3815,-0.3532,-0.3024,-0.2048,-0.0222",\ +"-0.4607,-0.4461,-0.4324,-0.4041,-0.3533,-0.2556,-0.0730"); + } + } + + timing() { + timing_type : hold_rising; + related_pin : "B_CLK"; + when : "(B_WEN & B_MEN)"; + sdf_cond : "B_W_ACCESS"; + + rise_constraint("SIG2SRAM_constraint_template") { + index_1("0.0056,0.0232,0.0400,0.0728,0.1280,0.2440,0.4760"); + index_2("0.0056,0.0232,0.0400,0.0728,0.1280,0.2440,0.4760"); + values ("0.4953,0.4787,0.4660,0.4338,0.3859,0.2824,0.0900",\ +"0.5003,0.4837,0.4710,0.4388,0.3909,0.2874,0.0950",\ +"0.5048,0.4881,0.4754,0.4432,0.3954,0.2919,0.0995",\ +"0.5146,0.4980,0.4853,0.4531,0.4052,0.3017,0.1093",\ +"0.5209,0.5043,0.4916,0.4594,0.4116,0.3080,0.1157",\ +"0.5574,0.5408,0.5281,0.4959,0.4481,0.3445,0.1522",\ +"0.6083,0.5917,0.5790,0.5468,0.4989,0.3954,0.2030"); + } + + fall_constraint("SIG2SRAM_constraint_template") { + index_1("0.0056,0.0232,0.0400,0.0728,0.1280,0.2440,0.4760"); + index_2("0.0056,0.0232,0.0400,0.0728,0.1280,0.2440,0.4760"); + values ("0.4494,0.4348,0.4211,0.3928,0.3430,0.2502,0.0656",\ +"0.4544,0.4398,0.4261,0.3978,0.3480,0.2552,0.0706",\ +"0.4588,0.4442,0.4305,0.4022,0.3524,0.2596,0.0751",\ +"0.4687,0.4540,0.4404,0.4121,0.3622,0.2695,0.0849",\ +"0.4750,0.4604,0.4467,0.4184,0.3686,0.2758,0.0912",\ +"0.5115,0.4969,0.4832,0.4549,0.4051,0.3123,0.1277",\ +"0.5624,0.5477,0.5341,0.5058,0.4559,0.3632,0.1786"); + } + } + } + + pin(B_BIST_EN) { + direction : input ; + capacitance : 0.00401111 ; + max_transition : "1" ; + related_power_pin : VDD; + related_ground_pin : VSS; + internal_power() { + rise_power("scalar") { + values (0); + } + fall_power("scalar") { + values (0); + } + } + } + +bus(B_BIST_ADDR) { + bus_type : A_9_0; + direction : input ; + capacitance : 0.0121077 ; + pin(B_BIST_ADDR[0]) { + capacitance : 0.00570093 ; + } + pin(B_BIST_ADDR[1]) { + capacitance : 0.00764555 ; + } + pin(B_BIST_ADDR[2]) { + capacitance : 0.0105375 ; + } + pin(B_BIST_ADDR[3]) { + capacitance : 0.0067894 ; + } + pin(B_BIST_ADDR[4]) { + capacitance : 0.00630967 ; + } + pin(B_BIST_ADDR[5]) { + capacitance : 0.0104132 ; + } + pin(B_BIST_ADDR[6]) { + capacitance : 0.0131402 ; + } + pin(B_BIST_ADDR[7]) { + capacitance : 0.0105203 ; + } + pin(B_BIST_ADDR[8]) { + capacitance : 0.00910078 ; + } + max_transition : "0.476" ; + pin(B_BIST_ADDR[9:0]) { + related_power_pin : VDD; + related_ground_pin : VSS; + internal_power() { + when : "B_BIST_MEN"; + rise_power("scalar"){ + values (0.0120); + } + fall_power("scalar"){ + values (0.0063); + } + } + internal_power() { + when : "!B_BIST_MEN"; + rise_power("scalar"){ + values (0.0204); + } + fall_power("scalar"){ + values (0.0012); + } + } + } + timing() { + timing_type : setup_rising; + related_pin : "B_BIST_CLK"; + when : "((B_BIST_WEN | B_BIST_REN)& B_BIST_MEN)" + sdf_cond : "B_BIST_RW_ACCESS" + + rise_constraint("SIG2SRAM_constraint_template") { + index_1("0.0056,0.0232,0.0400,0.0728,0.1280,0.2440,0.4760"); + index_2("0.0056,0.0232,0.0400,0.0728,0.1280,0.2440,0.4760"); + values ("-0.4168,-0.3973,-0.3855,-0.3543,-0.3074,-0.2020,-0.0027",\ +"-0.4324,-0.4129,-0.4012,-0.3699,-0.3191,-0.2176,-0.0184",\ +"-0.4441,-0.4285,-0.4129,-0.3816,-0.3309,-0.2293,-0.0301",\ +"-0.4793,-0.4598,-0.4441,-0.4129,-0.3660,-0.2645,-0.0652",\ +"-0.5223,-0.5066,-0.4910,-0.4598,-0.4129,-0.3074,-0.1121",\ +"-0.6199,-0.6082,-0.5926,-0.5613,-0.5145,-0.4129,-0.2137",\ +"-0.8191,-0.8074,-0.7840,-0.7566,-0.7098,-0.6082,-0.4051"); + } + + fall_constraint("SIG2SRAM_constraint_template") { + index_1("0.0056,0.0232,0.0400,0.0728,0.1280,0.2440,0.4760"); + index_2("0.0056,0.0232,0.0400,0.0728,0.1280,0.2440,0.4760"); + values ("-0.3309,-0.3113,-0.2996,-0.2684,-0.2176,-0.1238,0.0637",\ +"-0.3465,-0.3309,-0.3152,-0.2840,-0.2332,-0.1395,0.0480",\ +"-0.3582,-0.3426,-0.3270,-0.2996,-0.2488,-0.1512,0.0324",\ +"-0.3895,-0.3738,-0.3582,-0.3309,-0.2801,-0.1863,0.0051",\ +"-0.4363,-0.4207,-0.4051,-0.3777,-0.3230,-0.2293,-0.0379",\ +"-0.5379,-0.5223,-0.5066,-0.4793,-0.4285,-0.3309,-0.1434",\ +"-0.7332,-0.7176,-0.7020,-0.6746,-0.6238,-0.5262,-0.3387"); + } + } + + + timing() { + timing_type : hold_rising; + related_pin : "B_BIST_CLK"; + when : "((B_BIST_WEN | B_BIST_REN)& B_BIST_MEN)" + sdf_cond : "B_BIST_RW_ACCESS" + + rise_constraint("SIG2SRAM_constraint_template") { + index_1("0.0056,0.0232,0.0400,0.0728,0.1280,0.2440,0.4760"); + index_2("0.0056,0.0232,0.0400,0.0728,0.1280,0.2440,0.4760"); + values ("0.5246,0.5051,0.4895,0.4582,0.4113,0.3059,0.1066",\ +"0.5402,0.5207,0.5051,0.4777,0.4270,0.3215,0.1223",\ +"0.5520,0.5324,0.5168,0.4895,0.4387,0.3371,0.1340",\ +"0.5832,0.5676,0.5520,0.5207,0.4738,0.3684,0.1691",\ +"0.6301,0.6105,0.5949,0.5676,0.5168,0.4113,0.2160",\ +"0.7316,0.7121,0.7004,0.6691,0.6223,0.5168,0.3176",\ +"0.9270,0.9230,0.8957,0.8645,0.8137,0.7121,0.5168"); + } + + fall_constraint("SIG2SRAM_constraint_template") { + index_1("0.0056,0.0232,0.0400,0.0728,0.1280,0.2440,0.4760"); + index_2("0.0056,0.0232,0.0400,0.0728,0.1280,0.2440,0.4760"); + values ("0.4309,0.4152,0.4035,0.3684,0.3215,0.2277,0.0363",\ +"0.4465,0.4309,0.4152,0.3879,0.3371,0.2395,0.0559",\ +"0.4582,0.4426,0.4309,0.3996,0.3488,0.2551,0.0715",\ +"0.4934,0.4777,0.4621,0.4348,0.3840,0.2863,0.0988",\ +"0.5363,0.5207,0.5051,0.4777,0.4270,0.3332,0.1418",\ +"0.6379,0.6262,0.6105,0.5793,0.5324,0.4348,0.2434",\ +"0.8332,0.8215,0.8059,0.7707,0.7238,0.6301,0.4387"); + } + } +} +pin(B_BIST_WEN) { + direction : input ; + capacitance : 0.00324098 ; + max_transition : "0.476" ; + related_power_pin : VDD; + related_ground_pin : VSS; + internal_power() { + when : "B_BIST_MEN"; + rise_power("scalar"){ + values (0.0046); + } + fall_power("scalar"){ + values (0.0039); + } + } + internal_power() { + when : "!B_BIST_MEN"; + rise_power("scalar"){ + values (0.0043); + } + fall_power("scalar"){ + values (0.0040); + } + } + timing() { + timing_type : setup_rising; + related_pin : "B_BIST_CLK"; + when : "B_BIST_MEN" + sdf_cond : "B_BIST_MEN" + + rise_constraint("SIG2SRAM_constraint_template") { + index_1("0.0056,0.0232,0.0400,0.0728,0.1280,0.2440,0.4760"); + index_2("0.0056,0.0232,0.0400,0.0728,0.1280,0.2440,0.4760"); + values ("0.2043,0.2199,0.2316,0.2629,0.3059,0.4113,0.6066",\ +"0.1887,0.2043,0.2160,0.2473,0.2941,0.3957,0.5949",\ +"0.1691,0.1848,0.2004,0.2316,0.2785,0.3801,0.5754",\ +"0.1379,0.1574,0.1691,0.2004,0.2473,0.3527,0.5480",\ +"0.0910,0.1066,0.1223,0.1535,0.2004,0.2980,0.4973",\ +"-0.0105,0.0051,0.0207,0.0520,0.0949,0.2004,0.3957",\ +"-0.2059,-0.1902,-0.1746,-0.1473,-0.1004,0.0051,0.2004"); + } + + fall_constraint("SIG2SRAM_constraint_template") { + index_1("0.0056,0.0232,0.0400,0.0728,0.1280,0.2440,0.4760"); + index_2("0.0056,0.0232,0.0400,0.0728,0.1280,0.2440,0.4760"); + values ("0.2941,0.3098,0.3215,0.3488,0.4035,0.4973,0.6887",\ +"0.2785,0.2941,0.3059,0.3332,0.3840,0.4816,0.6691",\ +"0.2629,0.2785,0.2902,0.3176,0.3684,0.4660,0.6535",\ +"0.2316,0.2473,0.2590,0.2863,0.3410,0.4348,0.6262",\ +"0.1848,0.2004,0.2121,0.2395,0.2902,0.3879,0.5754",\ +"0.0832,0.0988,0.1105,0.1379,0.1809,0.2746,0.4699",\ +"-0.1121,-0.0965,-0.0848,-0.0535,-0.0066,0.0910,0.2824"); + } + } + + + timing() { + timing_type : hold_rising; + related_pin : "B_BIST_CLK"; + when : "B_BIST_MEN" + sdf_cond : "B_BIST_MEN" + + rise_constraint("SIG2SRAM_constraint_template") { + index_1("0.0056,0.0232,0.0400,0.0728,0.1280,0.2440,0.4760"); + index_2("0.0056,0.0232,0.0400,0.0728,0.1280,0.2440,0.4760"); + values ("0.2473,0.2316,0.2160,0.1887,0.1379,0.0363,-0.1629",\ +"0.2629,0.2473,0.2316,0.2043,0.1535,0.0520,-0.1473",\ +"0.2785,0.2590,0.2434,0.2160,0.1652,0.0676,-0.1355",\ +"0.3098,0.2941,0.2785,0.2473,0.1965,0.0910,-0.1043",\ +"0.3527,0.3371,0.3215,0.2941,0.2434,0.1418,-0.0574",\ +"0.4582,0.4426,0.4270,0.3957,0.3488,0.2434,0.0480",\ +"0.6535,0.6379,0.6184,0.5910,0.5402,0.4426,0.2434"); + } + + fall_constraint("SIG2SRAM_constraint_template") { + index_1("0.0056,0.0232,0.0400,0.0728,0.1280,0.2440,0.4760"); + index_2("0.0056,0.0232,0.0400,0.0728,0.1280,0.2440,0.4760"); + values ("0.2395,0.2238,0.2121,0.1809,0.1301,0.0324,-0.1551",\ +"0.2551,0.2395,0.2277,0.1965,0.1457,0.0480,-0.1395",\ +"0.2668,0.2551,0.2395,0.2082,0.1574,0.0637,-0.1277",\ +"0.3020,0.2863,0.2707,0.2395,0.1887,0.0910,-0.0965",\ +"0.3449,0.3293,0.3176,0.2863,0.2355,0.1379,-0.0496",\ +"0.4504,0.4348,0.4191,0.3879,0.3371,0.2395,0.0559",\ +"0.6457,0.6301,0.6145,0.5871,0.5324,0.4309,0.2512"); + } + } + } +pin(B_BIST_REN) { + direction : input ; + capacitance : 0.00381634 ; + max_transition : "0.476" ; + related_power_pin : VDD; + related_ground_pin : VSS; + internal_power() { + when : "B_BIST_MEN"; + rise_power("scalar"){ + values (0.0061); + } + fall_power("scalar"){ + values (0.0021); + } + } + internal_power() { + when : "!B_BIST_MEN"; + rise_power("scalar"){ + values (0.0062); + } + fall_power("scalar"){ + values (0.0025); + } + } + timing() { + timing_type : setup_rising; + related_pin : "B_BIST_CLK"; + when : "B_BIST_MEN" + sdf_cond : "B_BIST_MEN" + + rise_constraint("SIG2SRAM_constraint_template") { + index_1("0.0056,0.0232,0.0400,0.0728,0.1280,0.2440,0.4760"); + index_2("0.0056,0.0232,0.0400,0.0728,0.1280,0.2440,0.4760"); + values ("-0.0301,-0.0145,0.0012,0.0324,0.0793,0.1809,0.3762",\ +"-0.0457,-0.0301,-0.0145,0.0168,0.0637,0.1613,0.3605",\ +"-0.0574,-0.0418,-0.0262,0.0051,0.0520,0.1496,0.3449",\ +"-0.0926,-0.0730,-0.0574,-0.0262,0.0207,0.1184,0.3137",\ +"-0.1395,-0.1238,-0.1082,-0.0770,-0.0301,0.0715,0.2707",\ +"-0.2410,-0.2254,-0.2098,-0.1746,-0.1355,-0.0340,0.1652",\ +"-0.4402,-0.4207,-0.4051,-0.3738,-0.3270,-0.2293,-0.0340"); + } + + fall_constraint("SIG2SRAM_constraint_template") { + index_1("0.0056,0.0232,0.0400,0.0728,0.1280,0.2440,0.4760"); + index_2("0.0056,0.0232,0.0400,0.0728,0.1280,0.2440,0.4760"); + values ("0.0988,0.1145,0.1262,0.1535,0.2043,0.3020,0.4855",\ +"0.0832,0.0988,0.1105,0.1418,0.1848,0.2824,0.4738",\ +"0.0676,0.0832,0.0949,0.1262,0.1730,0.2668,0.4621",\ +"0.0402,0.0559,0.0676,0.0988,0.1457,0.2434,0.4191",\ +"-0.0105,0.0012,0.0168,0.0480,0.0988,0.1965,0.3840",\ +"-0.1160,-0.0965,-0.0848,-0.0535,-0.0066,0.0988,0.2824",\ +"-0.3113,-0.2957,-0.2801,-0.2527,-0.2059,-0.1043,0.0832"); + } + } + + + timing() { + timing_type : hold_rising; + related_pin : "B_BIST_CLK"; + when : "B_BIST_MEN" + sdf_cond : "B_BIST_MEN" + + rise_constraint("SIG2SRAM_constraint_template") { + index_1("0.0056,0.0232,0.0400,0.0728,0.1280,0.2440,0.4760"); + index_2("0.0056,0.0232,0.0400,0.0728,0.1280,0.2440,0.4760"); + values ("0.2707,0.2551,0.2395,0.2121,0.1613,0.0598,-0.1395",\ +"0.2863,0.2707,0.2551,0.2238,0.1730,0.0715,-0.1238",\ +"0.2980,0.2824,0.2668,0.2395,0.1887,0.0871,-0.1121",\ +"0.3332,0.3176,0.3020,0.2707,0.2199,0.1184,-0.0809",\ +"0.3762,0.3605,0.3449,0.3176,0.2668,0.1613,-0.0340",\ +"0.4816,0.4621,0.4504,0.4191,0.3723,0.2629,0.0715",\ +"0.6770,0.6613,0.6418,0.6184,0.5637,0.4699,0.2629"); + } + + fall_constraint("SIG2SRAM_constraint_template") { + index_1("0.0056,0.0232,0.0400,0.0728,0.1280,0.2440,0.4760"); + index_2("0.0056,0.0232,0.0400,0.0728,0.1280,0.2440,0.4760"); + values ("0.2590,0.2434,0.2316,0.2004,0.1457,0.0520,-0.1355",\ +"0.2746,0.2590,0.2434,0.2160,0.1613,0.0676,-0.1199",\ +"0.2863,0.2707,0.2590,0.2277,0.1730,0.0832,-0.1082",\ +"0.3215,0.3059,0.2902,0.2590,0.2082,0.1105,-0.0770",\ +"0.3645,0.3488,0.3332,0.3059,0.2551,0.1535,-0.0340",\ +"0.4699,0.4543,0.4387,0.4074,0.3605,0.2551,0.0715",\ +"0.6652,0.6496,0.6340,0.6027,0.5520,0.4621,0.2707"); + } + } + } +pin(B_BIST_MEN) { + direction : input ; + capacitance : 0.00309605 ; + max_transition : "0.476" ; + related_power_pin : VDD; + related_ground_pin : VSS; + internal_power() { + rise_power("scalar"){ + values (0.0448); + } + fall_power("scalar"){ + values (0.0052); + } + } + timing() { + timing_type : setup_rising; + related_pin : "B_BIST_CLK"; + + rise_constraint("SIG2SRAM_constraint_template") { + index_1("0.0056,0.0232,0.0400,0.0728,0.1280,0.2440,0.4760"); + index_2("0.0056,0.0232,0.0400,0.0728,0.1280,0.2440,0.4760"); + values ("0.2043,0.2199,0.2316,0.2668,0.3098,0.4152,0.6066",\ +"0.1887,0.2043,0.2199,0.2512,0.2941,0.3996,0.5949",\ +"0.1730,0.1887,0.2043,0.2355,0.2824,0.3840,0.5793",\ +"0.1418,0.1574,0.1730,0.2043,0.2512,0.3566,0.5480",\ +"0.0949,0.1105,0.1262,0.1574,0.2043,0.3020,0.5051",\ +"-0.0066,0.0090,0.0246,0.0520,0.0988,0.2043,0.3996",\ +"-0.2020,-0.1863,-0.1746,-0.1434,-0.0965,0.0090,0.2082"); + } + + fall_constraint("SIG2SRAM_constraint_template") { + index_1("0.0056,0.0232,0.0400,0.0728,0.1280,0.2440,0.4760"); + index_2("0.0056,0.0232,0.0400,0.0728,0.1280,0.2440,0.4760"); + values ("0.2980,0.3137,0.3254,0.3527,0.4035,0.5012,0.6887",\ +"0.2824,0.2980,0.3098,0.3371,0.3879,0.4855,0.6730",\ +"0.2668,0.2824,0.2941,0.3215,0.3723,0.4699,0.6574",\ +"0.2355,0.2473,0.2629,0.2902,0.3410,0.4387,0.6262",\ +"0.1887,0.2004,0.2160,0.2395,0.2941,0.3918,0.5793",\ +"0.0871,0.1027,0.1145,0.1418,0.1848,0.2746,0.4816",\ +"-0.1082,-0.0965,-0.0809,-0.0496,-0.0027,0.0949,0.2863"); + } + } + + + timing() { + timing_type : hold_rising; + related_pin : "B_BIST_CLK"; + + rise_constraint("SIG2SRAM_constraint_template") { + index_1("0.0056,0.0232,0.0400,0.0728,0.1280,0.2440,0.4760"); + index_2("0.0056,0.0232,0.0400,0.0728,0.1280,0.2440,0.4760"); + values ("0.2512,0.2355,0.2199,0.1926,0.1418,0.0402,-0.1590",\ +"0.2668,0.2512,0.2355,0.2082,0.1574,0.0559,-0.1434",\ +"0.2824,0.2629,0.2512,0.2199,0.1691,0.0715,-0.1316",\ +"0.3137,0.2980,0.2824,0.2512,0.2004,0.0988,-0.0965",\ +"0.3566,0.3410,0.3254,0.2980,0.2473,0.1418,-0.0535",\ +"0.4621,0.4426,0.4309,0.3996,0.3527,0.2473,0.0520",\ +"0.6574,0.6418,0.6262,0.5949,0.5441,0.4465,0.2473"); + } + + fall_constraint("SIG2SRAM_constraint_template") { + index_1("0.0056,0.0232,0.0400,0.0728,0.1280,0.2440,0.4760"); + index_2("0.0056,0.0232,0.0400,0.0728,0.1280,0.2440,0.4760"); + values ("0.2395,0.2238,0.2121,0.1809,0.1301,0.0324,-0.1551",\ +"0.2551,0.2434,0.2277,0.1965,0.1457,0.0480,-0.1395",\ +"0.2707,0.2551,0.2395,0.2082,0.1574,0.0637,-0.1277",\ +"0.3020,0.2863,0.2707,0.2434,0.1926,0.0910,-0.0965",\ +"0.3449,0.3332,0.3176,0.2863,0.2355,0.1379,-0.0496",\ +"0.4504,0.4348,0.4230,0.3918,0.3410,0.2434,0.0559",\ +"0.6457,0.6301,0.6145,0.5910,0.5324,0.4387,0.2512"); + } + } + } +bus(B_BIST_BM) { + bus_type : D_15_0; + direction : input ; + capacitance : 0.00275526 ; + max_transition : "0.476" ; + pin(B_BIST_BM[15:0]) { + related_power_pin : VDD; + related_ground_pin : VSS; + internal_power() { + when : "B_BIST_MEN"; + rise_power("scalar"){ + values (0.0592); + } + fall_power("scalar"){ + values (0.0247); + } + } + internal_power() { + when : "!B_BIST_MEN"; + rise_power("scalar"){ + values (0.0603); + } + fall_power("scalar"){ + values (0.0245); + } + } + } + timing() { + timing_type : setup_rising; + related_pin : "B_BIST_CLK"; + when : "(B_BIST_WEN & B_BIST_MEN)" + sdf_cond : "B_BIST_RW_ACCESS" + + rise_constraint("SIG2SRAM_constraint_template") { + index_1("0.0056,0.0232,0.0400,0.0728,0.1280,0.2440,0.4760"); + index_2("0.0056,0.0232,0.0400,0.0728,0.1280,0.2440,0.4760"); + values ("-0.3858,-0.3702,-0.3565,-0.3243,-0.2774,-0.1729,0.0185",\ +"-0.3908,-0.3752,-0.3615,-0.3293,-0.2824,-0.1779,0.0135",\ +"-0.3953,-0.3796,-0.3660,-0.3337,-0.2869,-0.1824,0.0090",\ +"-0.4051,-0.3895,-0.3758,-0.3436,-0.2967,-0.1922,-0.0008",\ +"-0.4114,-0.3958,-0.3821,-0.3499,-0.3030,-0.1985,-0.0071",\ +"-0.4479,-0.4323,-0.4186,-0.3864,-0.3395,-0.2351,-0.0436",\ +"-0.4988,-0.4832,-0.4695,-0.4373,-0.3904,-0.2859,-0.0945"); + } + + fall_constraint("SIG2SRAM_constraint_template") { + index_1("0.0056,0.0232,0.0400,0.0728,0.1280,0.2440,0.4760"); + index_2("0.0056,0.0232,0.0400,0.0728,0.1280,0.2440,0.4760"); + values ("-0.3477,-0.3331,-0.3194,-0.2911,-0.2403,-0.1426,0.0400",\ +"-0.3527,-0.3381,-0.3244,-0.2961,-0.2453,-0.1477,0.0350",\ +"-0.3572,-0.3425,-0.3288,-0.3005,-0.2497,-0.1521,0.0305",\ +"-0.3670,-0.3524,-0.3387,-0.3104,-0.2596,-0.1619,0.0207",\ +"-0.3734,-0.3587,-0.3450,-0.3167,-0.2659,-0.1683,0.0143",\ +"-0.4098,-0.3952,-0.3815,-0.3532,-0.3024,-0.2048,-0.0222",\ +"-0.4607,-0.4461,-0.4324,-0.4041,-0.3533,-0.2556,-0.0730"); + } + } + + + timing() { + timing_type : hold_rising; + related_pin : "B_BIST_CLK"; + when : "(B_BIST_WEN & B_BIST_MEN)" + sdf_cond : "B_BIST_RW_ACCESS" + + rise_constraint("SIG2SRAM_constraint_template") { + index_1("0.0056,0.0232,0.0400,0.0728,0.1280,0.2440,0.4760"); + index_2("0.0056,0.0232,0.0400,0.0728,0.1280,0.2440,0.4760"); + values ("0.4953,0.4787,0.4660,0.4338,0.3859,0.2824,0.0900",\ +"0.5003,0.4837,0.4710,0.4388,0.3909,0.2874,0.0950",\ +"0.5048,0.4881,0.4754,0.4432,0.3954,0.2919,0.0995",\ +"0.5146,0.4980,0.4853,0.4531,0.4052,0.3017,0.1093",\ +"0.5209,0.5043,0.4916,0.4594,0.4116,0.3080,0.1157",\ +"0.5574,0.5408,0.5281,0.4959,0.4481,0.3445,0.1522",\ +"0.6083,0.5917,0.5790,0.5468,0.4989,0.3954,0.2030"); + } + + fall_constraint("SIG2SRAM_constraint_template") { + index_1("0.0056,0.0232,0.0400,0.0728,0.1280,0.2440,0.4760"); + index_2("0.0056,0.0232,0.0400,0.0728,0.1280,0.2440,0.4760"); + values ("0.4494,0.4348,0.4211,0.3928,0.3430,0.2502,0.0656",\ +"0.4544,0.4398,0.4261,0.3978,0.3480,0.2552,0.0706",\ +"0.4588,0.4442,0.4305,0.4022,0.3524,0.2596,0.0751",\ +"0.4687,0.4540,0.4404,0.4121,0.3622,0.2695,0.0849",\ +"0.4750,0.4604,0.4467,0.4184,0.3686,0.2758,0.0912",\ +"0.5115,0.4969,0.4832,0.4549,0.4051,0.3123,0.1277",\ +"0.5624,0.5477,0.5341,0.5058,0.4559,0.3632,0.1786"); + } + } +} + pin(B_BIST_CLK) { + direction : input; + capacitance : 0.00380014; + max_transition : "0.476"; + clock : "true" ; + pin_func_type : active_rising ; + + timing () { + timing_type : "min_pulse_width"; + related_pin : "B_BIST_CLK"; + rise_constraint("CLKTRAN_constraint_template") { + index_1("0.0056,0.476"); + values("0.21,0.21"); + } + } + + related_power_pin : VDD; + related_ground_pin : VSS; + + internal_power() { + when : "!B_BIST_MEN & !B_BIST_WEN & !B_BIST_REN"; + rise_power("scalar"){ + values (0); + } + fall_power("scalar"){ + values (0); + } + } + internal_power() { + when : "!B_BIST_MEN & B_BIST_WEN & !B_BIST_REN"; + rise_power("scalar"){ + values (0.5466); + } + fall_power("scalar"){ + values (0); + } + } + internal_power() { + when : "B_BIST_MEN & B_BIST_WEN & !B_BIST_REN"; + rise_power("scalar"){ + values (32.9180); + } + fall_power("scalar"){ + values (0); + } + } + internal_power() { + when : "B_BIST_MEN & B_BIST_WEN & B_BIST_REN"; + rise_power("scalar"){ + values (33.7600); + } + fall_power("scalar"){ + values (0); + } + } + internal_power() { + when : "B_BIST_MEN & !B_BIST_WEN & B_BIST_REN"; + rise_power("scalar"){ + values (26.4863); + } + fall_power("scalar"){ + values (0); + } + } + internal_power() { + when : "!B_BIST_MEN & !B_BIST_WEN & B_BIST_REN"; + rise_power("scalar"){ + values (0.3253); + } + fall_power("scalar"){ + values (0); + } + } + internal_power() { + when : "!B_BIST_MEN & B_BIST_WEN & B_BIST_REN"; + rise_power("scalar"){ + values (0.7651); + } + fall_power("scalar"){ + values (0); + } + } + internal_power() { + when : "B_BIST_MEN & !B_BIST_WEN & !B_BIST_REN"; + rise_power("scalar"){ + values (0); + } + fall_power("scalar"){ + values (0); + } + } + } + bus(B_BIST_DIN) { + bus_type : D_15_0; + direction : input ; + capacitance : 0.00414348 ; + memory_write() { + address : B_BIST_ADDR ; + clocked_on : B_BIST_CLK; + } + + max_transition : "0.476" ; + pin(B_BIST_DIN[15:0]) { + related_power_pin : VDD; + related_ground_pin : VSS; + internal_power() { + when : "B_BIST_MEN"; + rise_power("scalar"){ + values (0.0592); + } + fall_power("scalar"){ + values (0.0247); + } + } + internal_power() { + when : "!B_BIST_MEN"; + rise_power("scalar"){ + values (0.0603); + } + fall_power("scalar"){ + values (0.0245); + } + } + } + timing() { + timing_type : setup_rising; + related_pin : "B_BIST_CLK"; + when : "(B_BIST_WEN & B_BIST_MEN)"; + sdf_cond : "B_BIST_W_ACCESS"; + + rise_constraint("SIG2SRAM_constraint_template") { + index_1("0.0056,0.0232,0.0400,0.0728,0.1280,0.2440,0.4760"); + index_2("0.0056,0.0232,0.0400,0.0728,0.1280,0.2440,0.4760"); + values ("-0.3858,-0.3702,-0.3565,-0.3243,-0.2774,-0.1729,0.0185",\ +"-0.3908,-0.3752,-0.3615,-0.3293,-0.2824,-0.1779,0.0135",\ +"-0.3953,-0.3796,-0.3660,-0.3337,-0.2869,-0.1824,0.0090",\ +"-0.4051,-0.3895,-0.3758,-0.3436,-0.2967,-0.1922,-0.0008",\ +"-0.4114,-0.3958,-0.3821,-0.3499,-0.3030,-0.1985,-0.0071",\ +"-0.4479,-0.4323,-0.4186,-0.3864,-0.3395,-0.2351,-0.0436",\ +"-0.4988,-0.4832,-0.4695,-0.4373,-0.3904,-0.2859,-0.0945"); + } + + fall_constraint("SIG2SRAM_constraint_template") { + index_1("0.0056,0.0232,0.0400,0.0728,0.1280,0.2440,0.4760"); + index_2("0.0056,0.0232,0.0400,0.0728,0.1280,0.2440,0.4760"); + values ("-0.3477,-0.3331,-0.3194,-0.2911,-0.2403,-0.1426,0.0400",\ +"-0.3527,-0.3381,-0.3244,-0.2961,-0.2453,-0.1477,0.0350",\ +"-0.3572,-0.3425,-0.3288,-0.3005,-0.2497,-0.1521,0.0305",\ +"-0.3670,-0.3524,-0.3387,-0.3104,-0.2596,-0.1619,0.0207",\ +"-0.3734,-0.3587,-0.3450,-0.3167,-0.2659,-0.1683,0.0143",\ +"-0.4098,-0.3952,-0.3815,-0.3532,-0.3024,-0.2048,-0.0222",\ +"-0.4607,-0.4461,-0.4324,-0.4041,-0.3533,-0.2556,-0.0730"); + } + } + + timing() { + timing_type : hold_rising; + related_pin : "B_BIST_CLK"; + when : "(B_BIST_WEN & B_BIST_MEN)"; + sdf_cond : "B_BIST_W_ACCESS"; + + rise_constraint("SIG2SRAM_constraint_template") { + index_1("0.0056,0.0232,0.0400,0.0728,0.1280,0.2440,0.4760"); + index_2("0.0056,0.0232,0.0400,0.0728,0.1280,0.2440,0.4760"); + values ("0.4953,0.4787,0.4660,0.4338,0.3859,0.2824,0.0900",\ +"0.5003,0.4837,0.4710,0.4388,0.3909,0.2874,0.0950",\ +"0.5048,0.4881,0.4754,0.4432,0.3954,0.2919,0.0995",\ +"0.5146,0.4980,0.4853,0.4531,0.4052,0.3017,0.1093",\ +"0.5209,0.5043,0.4916,0.4594,0.4116,0.3080,0.1157",\ +"0.5574,0.5408,0.5281,0.4959,0.4481,0.3445,0.1522",\ +"0.6083,0.5917,0.5790,0.5468,0.4989,0.3954,0.2030"); + } + + fall_constraint("SIG2SRAM_constraint_template") { + index_1("0.0056,0.0232,0.0400,0.0728,0.1280,0.2440,0.4760"); + index_2("0.0056,0.0232,0.0400,0.0728,0.1280,0.2440,0.4760"); + values ("0.4494,0.4348,0.4211,0.3928,0.3430,0.2502,0.0656",\ +"0.4544,0.4398,0.4261,0.3978,0.3480,0.2552,0.0706",\ +"0.4588,0.4442,0.4305,0.4022,0.3524,0.2596,0.0751",\ +"0.4687,0.4540,0.4404,0.4121,0.3622,0.2695,0.0849",\ +"0.4750,0.4604,0.4467,0.4184,0.3686,0.2758,0.0912",\ +"0.5115,0.4969,0.4832,0.4549,0.4051,0.3123,0.1277",\ +"0.5624,0.5477,0.5341,0.5058,0.4559,0.3632,0.1786"); + } + } + } + +bus(B_DOUT) { + + bus_type : D_15_0; + direction : output ; + capacitance : 0 ; + max_capacitance : 0.064 ; + memory_read() { + address : B_ADDR ; + } + pin(B_DOUT[15:0]) { + related_power_pin : VDD; + related_ground_pin : VSS; + internal_power() { + rise_power("scalar") { + values (0); + } + fall_power("scalar") { + values (0); + } + } + } + timing() { + related_pin : "B_CLK"; + timing_type : rising_edge ; + timing_sense : non_unate ; + + cell_rise(SIG2SRAM_delay_template) { + index_1("0.0056,0.0232,0.0400,0.0728,0.1280,0.2440,0.4760"); + index_2("0.0008,0.0014,0.0051,0.0100,0.0339,0.0640"); + values ("4.3139,4.3155,4.3232,4.3319,4.3643,4.4004",\ +"4.3240,4.3257,4.3333,4.3420,4.3744,4.4105",\ +"4.3287,4.3303,4.3379,4.3466,4.3790,4.4152",\ +"4.3365,4.3381,4.3457,4.3544,4.3868,4.4230",\ +"4.3440,4.3456,4.3532,4.3620,4.3943,4.4305",\ +"4.3791,4.3807,4.3883,4.3970,4.4294,4.4656",\ +"4.4324,4.4340,4.4417,4.4504,4.4828,4.5189"); + } + cell_fall(SIG2SRAM_delay_template) { + index_1("0.0056,0.0232,0.0400,0.0728,0.1280,0.2440,0.4760"); + index_2("0.0008,0.0014,0.0051,0.0100,0.0339,0.0640"); + values ("4.2536,4.2550,4.2611,4.2682,4.2947,4.3209",\ +"4.2638,4.2651,4.2712,4.2783,4.3048,4.3310",\ +"4.2684,4.2697,4.2758,4.2829,4.3094,4.3357",\ +"4.2762,4.2775,4.2836,4.2907,4.3172,4.3435",\ +"4.2837,4.2851,4.2911,4.2983,4.3248,4.3510",\ +"4.3188,4.3201,4.3262,4.3333,4.3598,4.3861",\ +"4.3721,4.3735,4.3796,4.3867,4.4132,4.4394"); + } + + rise_transition(SRAM_load_template) { + index_1("0.0008,0.0014,0.0051,0.0100,0.0339,0.0640"); + values ("0.0326,0.0341,0.0428,0.0518,0.0923,0.1492"); + } + fall_transition(SRAM_load_template) { + index_1("0.0008,0.0014,0.0051,0.0100,0.0339,0.0640"); + values ("0.0254,0.0265,0.0335,0.0402,0.0707,0.1039"); + } + } +} +cell_leakage_power : 318.9007; +} +} diff --git a/flow/platforms/ihp-sg13g2/lib/RM_IHPSG13_2P_1024x32_c2_bm_bist_fast_1p32V_m55C.lib b/flow/platforms/ihp-sg13g2/lib/RM_IHPSG13_2P_1024x32_c2_bm_bist_fast_1p32V_m55C.lib new file mode 100644 index 0000000000..c0e5411d59 --- /dev/null +++ b/flow/platforms/ihp-sg13g2/lib/RM_IHPSG13_2P_1024x32_c2_bm_bist_fast_1p32V_m55C.lib @@ -0,0 +1,2898 @@ +/* ------------------------------------------------------*/ +/**/ +/* Copyright 2025 IHP PDK Authors*/ +/**/ +/* Licensed under the Apache License, Version 2.0 (the "License");*/ +/* you may not use this file except in compliance with the License.*/ +/* You may obtain a copy of the License at*/ +/* */ +/* https://www.apache.org/licenses/LICENSE-2.0*/ +/* */ +/* Unless required by applicable law or agreed to in writing, software*/ +/* distributed under the License is distributed on an "AS IS" BASIS,*/ +/* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.*/ +/* See the License for the specific language governing permissions and*/ +/* limitations under the License.*/ +/* */ +/* Generated on Wed Aug 27 13:08:55 2025 */ +/* */ +/* ------------------------------------------------------ */ +library(RM_IHPSG13_2P_1024x32_c2_bm_bist_fast_1p32V_m55C) { + technology (cmos) ; + delay_model : table_lookup ; + define ("add_pg_pin_to_lib", "library", "boolean"); + add_pg_pin_to_lib : true; + voltage_map ( VDD, 1.32); + voltage_map ( VDDARRAY, 1.32); + voltage_map ( VSS, 0.000000 ); + + date : "Wed Aug 27 13:08:53 2025" ; + comment : "IHP Microelectronics GmbH, 2023" ; + revision : 1.0.0 ; + simulation : true ; + nom_process : 1 ; + nom_temperature : -55 ; + nom_voltage : 1.32 ; + + operating_conditions("fast_1p32V_m55C"){ + process : 1 ; + temperature : -55 ; + voltage : 1.32 ; + tree_type : "balanced_tree" ; + } + + default_operating_conditions : fast_1p32V_m55C ; + default_max_transition : 1.0 ; + default_fanout_load : 1.0 ; + default_inout_pin_cap : 0.0 ; + default_input_pin_cap : 0.0 ; + default_output_pin_cap : 0.0 ; + default_cell_leakage_power : 0.0 ; + default_leakage_power_density : 0.0 ; + + slew_lower_threshold_pct_rise : 30 ; + slew_upper_threshold_pct_rise : 70 ; + input_threshold_pct_fall : 50 ; + output_threshold_pct_fall : 50 ; + input_threshold_pct_rise : 50 ; + output_threshold_pct_rise : 50 ; + slew_lower_threshold_pct_fall : 30 ; + slew_upper_threshold_pct_fall : 70 ; + slew_derate_from_library : 0.5; + k_volt_cell_leakage_power : 0.0 ; + k_temp_cell_leakage_power : 0.0 ; + k_process_cell_leakage_power : 0.0 ; + k_volt_internal_power : 0.0 ; + k_temp_internal_power : 0.0 ; + k_process_internal_power : 0.0 ; + + capacitive_load_unit (1,pf) ; + voltage_unit : "1V" ; + current_unit : "1uA" ; + time_unit : "1ns" ; + leakage_power_unit : "1nW" ; + pulling_resistance_unit : "1kohm"; + /* + ------------------------------------------------------------------------------------------ + implicit units overview: + cell_area unit : "um" + internal_power unit : "1e-12 * J/toggle = 1 * uW/MHz" + (capacitive_load_unit * voltage_unit^2) per toggle event + ------------------------------------------------------------------------------------------ + */ + library_features(report_delay_calculation); + define_cell_area (pad_drivers,pad_driver_sites) ; + + lu_table_template(CLKTRAN_constraint_template) { + variable_1 : constrained_pin_transition; + index_1 ( "0.010, 0.050, 0.200, 0.400, 1.000" ); + } + lu_table_template(SRAM_load_template) { + variable_1 : total_output_net_capacitance; + index_1 ( "0.0008,0.0014,0.0051,0.0100,0.0339,0.0640" ); + } + lu_table_template(SIG2SRAM_constraint_template) { + variable_1 : related_pin_transition; + variable_2 : constrained_pin_transition; + index_1 ( "0.0040,0.0176,0.0344,0.0656,0.1120,0.2016,0.3800" ); + index_2 ( "0.0040,0.0176,0.0344,0.0656,0.1120,0.2016,0.3800" ); + } + + lu_table_template(SIG2SRAM_delay_template) { + variable_1 : input_net_transition; + variable_2 : total_output_net_capacitance; + index_1 ( "0.0040,0.0176,0.0344,0.0656,0.1120,0.2016,0.3800" ); + index_2 ( "0.0008,0.0014,0.0051,0.0100,0.0339,0.0640" ); + } + + type (D_31_0) { + base_type : array; + data_type : bit; + bit_width : 32; + bit_from : 31; + bit_to : 0; + downto : true; + } + + type (A_9_0) { + base_type : array; + data_type : bit; + bit_width : 10; + bit_from : 9; + bit_to : 0; + downto : true; + } + +cell(RM_IHPSG13_2P_1024x32_c2_bm_bist) { +pg_pin (VDD) { + pg_type : primary_power; + voltage_name : VDD; +} +pg_pin (VDDARRAY) { + pg_type : primary_power; + voltage_name : VDDARRAY; +} +pg_pin (VSS) { + pg_type : primary_ground; + voltage_name : VSS; +} + +memory() { + type : ram; + address_width : 10; + word_width : 32; +} + +interface_timing : false; +bus_naming_style : "%s[%d]" ; +area : 264167.2813 ; + + pin(A_DLY) { + direction : input ; + capacitance : 0.00421562 ; + max_transition : "1" ; + related_power_pin : VDD; + related_ground_pin : VSS; + internal_power() { + rise_power("scalar") { + values (0); + } + fall_power("scalar") { + values (0); + } + } + } + +bus(A_ADDR) { + bus_type : A_9_0; + direction : input ; + capacitance : 0.0115194 ; + pin(A_ADDR[0]) { + capacitance : 0.00563454 ; + } + pin(A_ADDR[1]) { + capacitance : 0.00744185 ; + } + pin(A_ADDR[2]) { + capacitance : 0.0100611 ; + } + pin(A_ADDR[3]) { + capacitance : 0.00669965 ; + } + pin(A_ADDR[4]) { + capacitance : 0.00614331 ; + } + pin(A_ADDR[5]) { + capacitance : 0.0102172 ; + } + pin(A_ADDR[6]) { + capacitance : 0.0124225 ; + } + pin(A_ADDR[7]) { + capacitance : 0.010114 ; + } + pin(A_ADDR[8]) { + capacitance : 0.0089001 ; + } + max_transition : "0.38" ; + pin(A_ADDR[9:0]) { + related_power_pin : VDD; + related_ground_pin : VSS; + internal_power() { + when : "A_MEN"; + rise_power("scalar"){ + values (0.4735); + } + fall_power("scalar"){ + values (0.6259); + } + } + internal_power() { + when : "!A_MEN"; + rise_power("scalar"){ + values (0.0322); + } + fall_power("scalar"){ + values (0.0023); + } + } + } + timing() { + timing_type : setup_rising; + related_pin : "A_CLK"; + when : "((A_WEN | A_REN)& A_MEN)" + sdf_cond : "A_RW_ACCESS" + + rise_constraint("SIG2SRAM_constraint_template") { + index_1("0.0040,0.0176,0.0344,0.0656,0.1120,0.2016,0.3800"); + index_2("0.0040,0.0176,0.0344,0.0656,0.1120,0.2016,0.3800"); + values ("-0.2371,-0.2215,-0.2098,-0.1824,-0.1434,-0.0691,0.0676",\ +"-0.2449,-0.2332,-0.2176,-0.1902,-0.1551,-0.0770,0.0559",\ +"-0.2605,-0.2488,-0.2332,-0.2059,-0.1707,-0.0965,0.0441",\ +"-0.2879,-0.2723,-0.2605,-0.2332,-0.1941,-0.1199,0.0168",\ +"-0.3230,-0.3113,-0.2996,-0.2723,-0.2332,-0.1590,-0.0184",\ +"-0.4012,-0.3895,-0.3738,-0.3465,-0.3074,-0.2332,-0.0965",\ +"-0.5379,-0.5262,-0.5105,-0.4832,-0.4480,-0.3699,-0.2332"); + } + + fall_constraint("SIG2SRAM_constraint_template") { + index_1("0.0040,0.0176,0.0344,0.0656,0.1120,0.2016,0.3800"); + index_2("0.0040,0.0176,0.0344,0.0656,0.1120,0.2016,0.3800"); + values ("-0.1785,-0.1707,-0.1551,-0.1277,-0.0887,-0.0184,0.1145",\ +"-0.1902,-0.1785,-0.1629,-0.1355,-0.1004,-0.0262,0.1027",\ +"-0.2059,-0.1941,-0.1785,-0.1512,-0.1160,-0.0418,0.0871",\ +"-0.2293,-0.2176,-0.2059,-0.1785,-0.1434,-0.0691,0.0598",\ +"-0.2684,-0.2566,-0.2449,-0.2176,-0.1824,-0.1082,0.0207",\ +"-0.3465,-0.3348,-0.3191,-0.2918,-0.2566,-0.1824,-0.0535",\ +"-0.4832,-0.4715,-0.4559,-0.4324,-0.3934,-0.3191,-0.1902"); + } + } + + + timing() { + timing_type : hold_rising; + related_pin : "A_CLK"; + when : "((A_WEN | A_REN)& A_MEN)" + sdf_cond : "A_RW_ACCESS" + + rise_constraint("SIG2SRAM_constraint_template") { + index_1("0.0040,0.0176,0.0344,0.0656,0.1120,0.2016,0.3800"); + index_2("0.0040,0.0176,0.0344,0.0656,0.1120,0.2016,0.3800"); + values ("0.3410,0.3293,0.3137,0.2863,0.2473,0.1730,0.0324",\ +"0.3488,0.3371,0.3215,0.2941,0.2590,0.1809,0.0480",\ +"0.3684,0.3527,0.3371,0.3098,0.2746,0.1965,0.0598",\ +"0.3918,0.3762,0.3645,0.3371,0.2980,0.2238,0.0871",\ +"0.4309,0.4152,0.4035,0.3762,0.3371,0.2629,0.1223",\ +"0.5051,0.4934,0.4777,0.4504,0.4113,0.3371,0.1965",\ +"0.6418,0.6262,0.6145,0.5871,0.5520,0.4738,0.3332"); + } + + fall_constraint("SIG2SRAM_constraint_template") { + index_1("0.0040,0.0176,0.0344,0.0656,0.1120,0.2016,0.3800"); + index_2("0.0040,0.0176,0.0344,0.0656,0.1120,0.2016,0.3800"); + values ("0.2824,0.2707,0.2551,0.2277,0.1926,0.1184,-0.0105",\ +"0.2902,0.2785,0.2668,0.2395,0.2043,0.1301,0.0012",\ +"0.3059,0.2941,0.2824,0.2551,0.2199,0.1457,0.0168",\ +"0.3332,0.3215,0.3059,0.2785,0.2434,0.1691,0.0402",\ +"0.3723,0.3605,0.3449,0.3176,0.2824,0.2121,0.0793",\ +"0.4465,0.4348,0.4230,0.3918,0.3566,0.2824,0.1535",\ +"0.5832,0.5715,0.5598,0.5324,0.4934,0.4191,0.2902"); + } + } +} +pin(A_WEN) { + direction : input ; + capacitance : 0.00341384 ; + max_transition : "0.38" ; + related_power_pin : VDD; + related_ground_pin : VSS; + internal_power() { + when : "A_MEN"; + rise_power("scalar"){ + values (0.9384); + } + fall_power("scalar"){ + values (0.0212); + } + } + internal_power() { + when : "!A_MEN"; + rise_power("scalar"){ + values (0.0069); + } + fall_power("scalar"){ + values (0.0124); + } + } + timing() { + timing_type : setup_rising; + related_pin : "A_CLK"; + when : "A_MEN" + sdf_cond : "A_MEN" + + rise_constraint("SIG2SRAM_constraint_template") { + index_1("0.0040,0.0176,0.0344,0.0656,0.1120,0.2016,0.3800"); + index_2("0.0040,0.0176,0.0344,0.0656,0.1120,0.2016,0.3800"); + values ("0.1418,0.1496,0.1652,0.1887,0.2316,0.3059,0.4465",\ +"0.1301,0.1379,0.1535,0.1809,0.2199,0.2941,0.4348",\ +"0.1145,0.1262,0.1379,0.1652,0.2043,0.2785,0.4191",\ +"0.0871,0.0949,0.1105,0.1379,0.1770,0.2512,0.3879",\ +"0.0480,0.0598,0.0754,0.0988,0.1379,0.2082,0.3527",\ +"-0.0262,-0.0145,0.0012,0.0246,0.0676,0.1379,0.2785",\ +"-0.1668,-0.1551,-0.1395,-0.1121,-0.0730,0.0012,0.1418"); + } + + fall_constraint("SIG2SRAM_constraint_template") { + index_1("0.0040,0.0176,0.0344,0.0656,0.1120,0.2016,0.3800"); + index_2("0.0040,0.0176,0.0344,0.0656,0.1120,0.2016,0.3800"); + values ("0.2082,0.2160,0.2316,0.2590,0.2941,0.3684,0.5012",\ +"0.1926,0.2043,0.2199,0.2473,0.2824,0.3566,0.4895",\ +"0.1770,0.1887,0.2043,0.2316,0.2668,0.3410,0.4777",\ +"0.1535,0.1652,0.1770,0.2043,0.2395,0.3137,0.4504",\ +"0.1145,0.1262,0.1379,0.1652,0.2043,0.2746,0.4113",\ +"0.0402,0.0520,0.0676,0.0910,0.1262,0.2004,0.3332",\ +"-0.0965,-0.0848,-0.0730,-0.0457,-0.0066,0.0637,0.2004"); + } + } + + + timing() { + timing_type : hold_rising; + related_pin : "A_CLK"; + when : "A_MEN" + sdf_cond : "A_MEN" + + rise_constraint("SIG2SRAM_constraint_template") { + index_1("0.0040,0.0176,0.0344,0.0656,0.1120,0.2016,0.3800"); + index_2("0.0040,0.0176,0.0344,0.0656,0.1120,0.2016,0.3800"); + values ("0.1770,0.1652,0.1496,0.1223,0.0793,0.0090,-0.1316",\ +"0.1848,0.1730,0.1574,0.1301,0.0910,0.0168,-0.1199",\ +"0.2004,0.1887,0.1770,0.1496,0.1066,0.0363,-0.1043",\ +"0.2277,0.2160,0.2004,0.1730,0.1340,0.0598,-0.0809",\ +"0.2668,0.2551,0.2395,0.2121,0.1730,0.0988,-0.0418",\ +"0.3410,0.3293,0.3137,0.2863,0.2434,0.1730,0.0324",\ +"0.4816,0.4699,0.4543,0.4230,0.3801,0.3098,0.1730"); + } + + fall_constraint("SIG2SRAM_constraint_template") { + index_1("0.0040,0.0176,0.0344,0.0656,0.1120,0.2016,0.3800"); + index_2("0.0040,0.0176,0.0344,0.0656,0.1120,0.2016,0.3800"); + values ("0.1613,0.1496,0.1379,0.1066,0.0715,0.0012,-0.1355",\ +"0.1730,0.1613,0.1457,0.1184,0.0832,0.0129,-0.1238",\ +"0.1887,0.1770,0.1613,0.1340,0.0988,0.0246,-0.1121",\ +"0.2121,0.2043,0.1887,0.1613,0.1223,0.0520,-0.0848",\ +"0.2512,0.2434,0.2277,0.2004,0.1613,0.0910,-0.0457",\ +"0.3254,0.3176,0.3020,0.2746,0.2355,0.1652,0.0324",\ +"0.4660,0.4543,0.4387,0.4113,0.3723,0.3020,0.1691"); + } + } + } +pin(A_REN) { + direction : input ; + capacitance : 0.00390661 ; + max_transition : "0.38" ; + related_power_pin : VDD; + related_ground_pin : VSS; + internal_power() { + when : "A_MEN"; + rise_power("scalar"){ + values (0.0154); + } + fall_power("scalar"){ + values (0.0113); + } + } + internal_power() { + when : "!A_MEN"; + rise_power("scalar"){ + values (0.0276); + } + fall_power("scalar"){ + values (0.0235); + } + } + timing() { + timing_type : setup_rising; + related_pin : "A_CLK"; + when : "A_MEN" + sdf_cond : "A_MEN" + + rise_constraint("SIG2SRAM_constraint_template") { + index_1("0.0040,0.0176,0.0344,0.0656,0.1120,0.2016,0.3800"); + index_2("0.0040,0.0176,0.0344,0.0656,0.1120,0.2016,0.3800"); + values ("-0.0027,0.0090,0.0246,0.0520,0.0910,0.1613,0.3020",\ +"-0.0105,0.0012,0.0129,0.0363,0.0793,0.1535,0.2902",\ +"-0.0262,-0.0145,-0.0027,0.0246,0.0637,0.1379,0.2785",\ +"-0.0535,-0.0418,-0.0262,0.0012,0.0363,0.1105,0.2512",\ +"-0.0926,-0.0809,-0.0652,-0.0418,-0.0027,0.0715,0.2121",\ +"-0.1668,-0.1551,-0.1395,-0.1082,-0.0770,-0.0027,0.1379",\ +"-0.3035,-0.2918,-0.2762,-0.2488,-0.2137,-0.1434,-0.0027"); + } + + fall_constraint("SIG2SRAM_constraint_template") { + index_1("0.0040,0.0176,0.0344,0.0656,0.1120,0.2016,0.3800"); + index_2("0.0040,0.0176,0.0344,0.0656,0.1120,0.2016,0.3800"); + values ("0.0832,0.0949,0.1105,0.1379,0.1730,0.2473,0.3801",\ +"0.0754,0.0832,0.0988,0.1223,0.1613,0.2355,0.3684",\ +"0.0598,0.0676,0.0832,0.1066,0.1457,0.2121,0.3527",\ +"0.0324,0.0441,0.0598,0.0871,0.1223,0.1926,0.3293",\ +"-0.0066,0.0051,0.0168,0.0480,0.0832,0.1535,0.2902",\ +"-0.0809,-0.0691,-0.0574,-0.0301,0.0090,0.0832,0.2121",\ +"-0.2176,-0.2059,-0.1941,-0.1668,-0.1277,-0.0574,0.0793"); + } + } + + + timing() { + timing_type : hold_rising; + related_pin : "A_CLK"; + when : "A_MEN" + sdf_cond : "A_MEN" + + rise_constraint("SIG2SRAM_constraint_template") { + index_1("0.0040,0.0176,0.0344,0.0656,0.1120,0.2016,0.3800"); + index_2("0.0040,0.0176,0.0344,0.0656,0.1120,0.2016,0.3800"); + values ("0.1887,0.1770,0.1613,0.1340,0.0949,0.0207,-0.1160",\ +"0.1965,0.1848,0.1730,0.1457,0.1027,0.0324,-0.1082",\ +"0.2160,0.2004,0.1887,0.1613,0.1184,0.0480,-0.0926",\ +"0.2395,0.2277,0.2121,0.1848,0.1457,0.0715,-0.0652",\ +"0.2785,0.2668,0.2512,0.2238,0.1848,0.1105,-0.0262",\ +"0.3527,0.3410,0.3254,0.2980,0.2551,0.1848,0.0480",\ +"0.4934,0.4816,0.4660,0.4387,0.3957,0.3254,0.1887"); + } + + fall_constraint("SIG2SRAM_constraint_template") { + index_1("0.0040,0.0176,0.0344,0.0656,0.1120,0.2016,0.3800"); + index_2("0.0040,0.0176,0.0344,0.0656,0.1120,0.2016,0.3800"); + values ("0.1730,0.1613,0.1496,0.1184,0.0793,0.0129,-0.1238",\ +"0.1848,0.1730,0.1574,0.1301,0.0910,0.0207,-0.1121",\ +"0.2004,0.1887,0.1730,0.1457,0.1066,0.0363,-0.1004",\ +"0.2238,0.2121,0.2004,0.1691,0.1340,0.0598,-0.0730",\ +"0.2629,0.2512,0.2395,0.2121,0.1691,0.0988,-0.0340",\ +"0.3371,0.3254,0.3137,0.2863,0.2434,0.1730,0.0402",\ +"0.4777,0.4660,0.4504,0.4230,0.3840,0.3137,0.1809"); + } + } + } +pin(A_MEN) { + direction : input ; + capacitance : 0.00326046 ; + max_transition : "0.38" ; + related_power_pin : VDD; + related_ground_pin : VSS; + internal_power() { + rise_power("scalar"){ + values (0.2886); + } + fall_power("scalar"){ + values (0.4759); + } + } + timing() { + timing_type : setup_rising; + related_pin : "A_CLK"; + + rise_constraint("SIG2SRAM_constraint_template") { + index_1("0.0040,0.0176,0.0344,0.0656,0.1120,0.2016,0.3800"); + index_2("0.0040,0.0176,0.0344,0.0656,0.1120,0.2016,0.3800"); + values ("0.1418,0.1496,0.1652,0.1926,0.2316,0.3059,0.4465",\ +"0.1301,0.1379,0.1535,0.1809,0.2199,0.2941,0.4348",\ +"0.1145,0.1262,0.1418,0.1652,0.2043,0.2785,0.4191",\ +"0.0871,0.0949,0.1105,0.1379,0.1770,0.2512,0.3879",\ +"0.0480,0.0598,0.0754,0.0988,0.1379,0.2082,0.3488",\ +"-0.0262,-0.0145,0.0012,0.0285,0.0676,0.1379,0.2785",\ +"-0.1668,-0.1551,-0.1395,-0.1121,-0.0730,0.0012,0.1379"); + } + + fall_constraint("SIG2SRAM_constraint_template") { + index_1("0.0040,0.0176,0.0344,0.0656,0.1120,0.2016,0.3800"); + index_2("0.0040,0.0176,0.0344,0.0656,0.1120,0.2016,0.3800"); + values ("0.2082,0.2199,0.2316,0.2590,0.2980,0.3723,0.5051",\ +"0.1965,0.2082,0.2199,0.2473,0.2863,0.3605,0.4934",\ +"0.1809,0.1926,0.2043,0.2316,0.2707,0.3449,0.4777",\ +"0.1574,0.1691,0.1809,0.2082,0.2434,0.3176,0.4543",\ +"0.1145,0.1262,0.1418,0.1691,0.2043,0.2785,0.4113",\ +"0.0441,0.0559,0.0676,0.0949,0.1301,0.2004,0.3332",\ +"-0.0965,-0.0848,-0.0691,-0.0418,-0.0066,0.0676,0.2004"); + } + } + + + timing() { + timing_type : hold_rising; + related_pin : "A_CLK"; + + rise_constraint("SIG2SRAM_constraint_template") { + index_1("0.0040,0.0176,0.0344,0.0656,0.1120,0.2016,0.3800"); + index_2("0.0040,0.0176,0.0344,0.0656,0.1120,0.2016,0.3800"); + values ("0.1770,0.1652,0.1535,0.1262,0.0832,0.0129,-0.1277",\ +"0.1887,0.1770,0.1613,0.1340,0.0949,0.0207,-0.1199",\ +"0.2043,0.1926,0.1770,0.1496,0.1105,0.0363,-0.1043",\ +"0.2277,0.2160,0.2043,0.1770,0.1379,0.0598,-0.0770",\ +"0.2668,0.2551,0.2434,0.2160,0.1730,0.0988,-0.0379",\ +"0.3449,0.3332,0.3176,0.2902,0.2473,0.1730,0.0363",\ +"0.4816,0.4699,0.4543,0.4270,0.3840,0.3098,0.1770"); + } + + fall_constraint("SIG2SRAM_constraint_template") { + index_1("0.0040,0.0176,0.0344,0.0656,0.1120,0.2016,0.3800"); + index_2("0.0040,0.0176,0.0344,0.0656,0.1120,0.2016,0.3800"); + values ("0.1613,0.1496,0.1379,0.1105,0.0715,0.0012,-0.1355",\ +"0.1730,0.1613,0.1496,0.1184,0.0832,0.0129,-0.1238",\ +"0.1887,0.1770,0.1652,0.1340,0.0988,0.0285,-0.1121",\ +"0.2121,0.2043,0.1887,0.1613,0.1223,0.0520,-0.0848",\ +"0.2551,0.2434,0.2277,0.2004,0.1613,0.0910,-0.0418",\ +"0.3293,0.3176,0.3020,0.2746,0.2395,0.1652,0.0324",\ +"0.4660,0.4543,0.4426,0.4113,0.3762,0.3020,0.1691"); + } + } + } +bus(A_BM) { + bus_type : D_31_0; + direction : input ; + capacitance : 0.00388883 ; + max_transition : "0.38" ; + pin(A_BM[31:0]) { + related_power_pin : VDD; + related_ground_pin : VSS; + internal_power() { + when : "A_MEN"; + rise_power("scalar"){ + values (0.1512); + } + fall_power("scalar"){ + values (0.1660); + } + } + internal_power() { + when : "!A_MEN"; + rise_power("scalar"){ + values (0.1918); + } + fall_power("scalar"){ + values (0.1601); + } + } + } + timing() { + timing_type : setup_rising; + related_pin : "A_CLK"; + when : "(A_WEN & A_MEN)" + sdf_cond : "A_RW_ACCESS" + + rise_constraint("SIG2SRAM_constraint_template") { + index_1("0.0040,0.0176,0.0344,0.0656,0.1120,0.2016,0.3800"); + index_2("0.0040,0.0176,0.0344,0.0656,0.1120,0.2016,0.3800"); + values ("-0.2899,-0.2791,-0.2635,-0.2381,-0.1971,-0.1238,0.0109",\ +"-0.2937,-0.2830,-0.2674,-0.2420,-0.2010,-0.1277,0.0070",\ +"-0.2975,-0.2868,-0.2712,-0.2458,-0.2048,-0.1315,0.0032",\ +"-0.3008,-0.2901,-0.2744,-0.2490,-0.2080,-0.1348,-0.0000",\ +"-0.3132,-0.3025,-0.2869,-0.2615,-0.2205,-0.1472,-0.0125",\ +"-0.3307,-0.3200,-0.3043,-0.2789,-0.2379,-0.1647,-0.0299",\ +"-0.3584,-0.3476,-0.3320,-0.3066,-0.2656,-0.1923,-0.0576"); + } + + fall_constraint("SIG2SRAM_constraint_template") { + index_1("0.0040,0.0176,0.0344,0.0656,0.1120,0.2016,0.3800"); + index_2("0.0040,0.0176,0.0344,0.0656,0.1120,0.2016,0.3800"); + values ("-0.2664,-0.2547,-0.2420,-0.2147,-0.1776,-0.1043,0.0236",\ +"-0.2703,-0.2586,-0.2459,-0.2185,-0.1814,-0.1082,0.0197",\ +"-0.2741,-0.2624,-0.2497,-0.2223,-0.1852,-0.1120,0.0159",\ +"-0.2774,-0.2656,-0.2529,-0.2256,-0.1885,-0.1152,0.0127",\ +"-0.2898,-0.2781,-0.2654,-0.2380,-0.2009,-0.1277,0.0002",\ +"-0.3073,-0.2955,-0.2828,-0.2555,-0.2184,-0.1452,-0.0172",\ +"-0.3349,-0.3232,-0.3105,-0.2832,-0.2461,-0.1728,-0.0449"); + } + } + + + timing() { + timing_type : hold_rising; + related_pin : "A_CLK"; + when : "(A_WEN & A_MEN)" + sdf_cond : "A_RW_ACCESS" + + rise_constraint("SIG2SRAM_constraint_template") { + index_1("0.0040,0.0176,0.0344,0.0656,0.1120,0.2016,0.3800"); + index_2("0.0040,0.0176,0.0344,0.0656,0.1120,0.2016,0.3800"); + values ("0.3958,0.3861,0.3705,0.3441,0.3070,0.2328,0.0980",\ +"0.3997,0.3900,0.3743,0.3480,0.3109,0.2366,0.1019",\ +"0.4035,0.3938,0.3781,0.3518,0.3147,0.2404,0.1057",\ +"0.4068,0.3970,0.3814,0.3550,0.3179,0.2437,0.1089",\ +"0.4192,0.4095,0.3938,0.3675,0.3304,0.2561,0.1214",\ +"0.4367,0.4269,0.4113,0.3849,0.3478,0.2736,0.1388",\ +"0.4643,0.4546,0.4389,0.4126,0.3755,0.3013,0.1665"); + } + + fall_constraint("SIG2SRAM_constraint_template") { + index_1("0.0040,0.0176,0.0344,0.0656,0.1120,0.2016,0.3800"); + index_2("0.0040,0.0176,0.0344,0.0656,0.1120,0.2016,0.3800"); + values ("0.3675,0.3568,0.3431,0.3158,0.2796,0.2074,0.0775",\ +"0.3714,0.3607,0.3470,0.3196,0.2835,0.2113,0.0814",\ +"0.3752,0.3645,0.3508,0.3234,0.2873,0.2150,0.0852",\ +"0.3785,0.3677,0.3540,0.3267,0.2906,0.2183,0.0884",\ +"0.3909,0.3802,0.3665,0.3391,0.3030,0.2307,0.1009",\ +"0.4084,0.3976,0.3839,0.3566,0.3205,0.2482,0.1183",\ +"0.4360,0.4253,0.4116,0.3843,0.3481,0.2759,0.1460"); + } + } +} + pin(A_CLK) { + direction : input; + capacitance : 0.00389386; + max_transition : "0.38"; + clock : "true" ; + pin_func_type : active_rising ; + + timing () { + timing_type : "min_pulse_width"; + related_pin : "A_CLK"; + rise_constraint("CLKTRAN_constraint_template") { + index_1("0.004,0.38"); + values("0.12,0.12"); + } + } + + related_power_pin : VDD; + related_ground_pin : VSS; + + internal_power() { + when : "!A_MEN & !A_WEN & !A_REN"; + rise_power("scalar"){ + values (0); + } + fall_power("scalar"){ + values (0); + } + } + internal_power() { + when : "!A_MEN & A_WEN & !A_REN"; + rise_power("scalar"){ + values (0.7228); + } + fall_power("scalar"){ + values (0); + } + } + internal_power() { + when : "A_MEN & A_WEN & !A_REN"; + rise_power("scalar"){ + values (73.7434); + } + fall_power("scalar"){ + values (0); + } + } + internal_power() { + when : "A_MEN & A_WEN & A_REN"; + rise_power("scalar"){ + values (76.2622); + } + fall_power("scalar"){ + values (0); + } + } + internal_power() { + when : "A_MEN & !A_WEN & A_REN"; + rise_power("scalar"){ + values (61.9692); + } + fall_power("scalar"){ + values (0); + } + } + internal_power() { + when : "!A_MEN & !A_WEN & A_REN"; + rise_power("scalar"){ + values (0.4287); + } + fall_power("scalar"){ + values (0); + } + } + internal_power() { + when : "!A_MEN & A_WEN & A_REN"; + rise_power("scalar"){ + values (1.4323); + } + fall_power("scalar"){ + values (0); + } + } + internal_power() { + when : "A_MEN & !A_WEN & !A_REN"; + rise_power("scalar"){ + values (0); + } + fall_power("scalar"){ + values (0); + } + } + } + bus(A_DIN) { + bus_type : D_31_0; + direction : input ; + capacitance : 0.00505326 ; + memory_write() { + address : A_ADDR ; + clocked_on : A_CLK; + } + + max_transition : "0.38" ; + pin(A_DIN[31:0]) { + related_power_pin : VDD; + related_ground_pin : VSS; + internal_power() { + when : "A_MEN"; + rise_power("scalar"){ + values (0.1512); + } + fall_power("scalar"){ + values (0.1660); + } + } + internal_power() { + when : "!A_MEN"; + rise_power("scalar"){ + values (0.1918); + } + fall_power("scalar"){ + values (0.1601); + } + } + } + timing() { + timing_type : setup_rising; + related_pin : "A_CLK"; + when : "(A_WEN & A_MEN)"; + sdf_cond : "A_W_ACCESS"; + + rise_constraint("SIG2SRAM_constraint_template") { + index_1("0.0040,0.0176,0.0344,0.0656,0.1120,0.2016,0.3800"); + index_2("0.0040,0.0176,0.0344,0.0656,0.1120,0.2016,0.3800"); + values ("-0.2899,-0.2791,-0.2635,-0.2381,-0.1971,-0.1238,0.0109",\ +"-0.2937,-0.2830,-0.2674,-0.2420,-0.2010,-0.1277,0.0070",\ +"-0.2975,-0.2868,-0.2712,-0.2458,-0.2048,-0.1315,0.0032",\ +"-0.3008,-0.2901,-0.2744,-0.2490,-0.2080,-0.1348,-0.0000",\ +"-0.3132,-0.3025,-0.2869,-0.2615,-0.2205,-0.1472,-0.0125",\ +"-0.3307,-0.3200,-0.3043,-0.2789,-0.2379,-0.1647,-0.0299",\ +"-0.3584,-0.3476,-0.3320,-0.3066,-0.2656,-0.1923,-0.0576"); + } + + fall_constraint("SIG2SRAM_constraint_template") { + index_1("0.0040,0.0176,0.0344,0.0656,0.1120,0.2016,0.3800"); + index_2("0.0040,0.0176,0.0344,0.0656,0.1120,0.2016,0.3800"); + values ("-0.2664,-0.2547,-0.2420,-0.2147,-0.1776,-0.1043,0.0236",\ +"-0.2703,-0.2586,-0.2459,-0.2185,-0.1814,-0.1082,0.0197",\ +"-0.2741,-0.2624,-0.2497,-0.2223,-0.1852,-0.1120,0.0159",\ +"-0.2774,-0.2656,-0.2529,-0.2256,-0.1885,-0.1152,0.0127",\ +"-0.2898,-0.2781,-0.2654,-0.2380,-0.2009,-0.1277,0.0002",\ +"-0.3073,-0.2955,-0.2828,-0.2555,-0.2184,-0.1452,-0.0172",\ +"-0.3349,-0.3232,-0.3105,-0.2832,-0.2461,-0.1728,-0.0449"); + } + } + + timing() { + timing_type : hold_rising; + related_pin : "A_CLK"; + when : "(A_WEN & A_MEN)"; + sdf_cond : "A_W_ACCESS"; + + rise_constraint("SIG2SRAM_constraint_template") { + index_1("0.0040,0.0176,0.0344,0.0656,0.1120,0.2016,0.3800"); + index_2("0.0040,0.0176,0.0344,0.0656,0.1120,0.2016,0.3800"); + values ("0.3958,0.3861,0.3705,0.3441,0.3070,0.2328,0.0980",\ +"0.3997,0.3900,0.3743,0.3480,0.3109,0.2366,0.1019",\ +"0.4035,0.3938,0.3781,0.3518,0.3147,0.2404,0.1057",\ +"0.4068,0.3970,0.3814,0.3550,0.3179,0.2437,0.1089",\ +"0.4192,0.4095,0.3938,0.3675,0.3304,0.2561,0.1214",\ +"0.4367,0.4269,0.4113,0.3849,0.3478,0.2736,0.1388",\ +"0.4643,0.4546,0.4389,0.4126,0.3755,0.3013,0.1665"); + } + + fall_constraint("SIG2SRAM_constraint_template") { + index_1("0.0040,0.0176,0.0344,0.0656,0.1120,0.2016,0.3800"); + index_2("0.0040,0.0176,0.0344,0.0656,0.1120,0.2016,0.3800"); + values ("0.3675,0.3568,0.3431,0.3158,0.2796,0.2074,0.0775",\ +"0.3714,0.3607,0.3470,0.3196,0.2835,0.2113,0.0814",\ +"0.3752,0.3645,0.3508,0.3234,0.2873,0.2150,0.0852",\ +"0.3785,0.3677,0.3540,0.3267,0.2906,0.2183,0.0884",\ +"0.3909,0.3802,0.3665,0.3391,0.3030,0.2307,0.1009",\ +"0.4084,0.3976,0.3839,0.3566,0.3205,0.2482,0.1183",\ +"0.4360,0.4253,0.4116,0.3843,0.3481,0.2759,0.1460"); + } + } + } + + pin(A_BIST_EN) { + direction : input ; + capacitance : 0.00421562 ; + max_transition : "1" ; + related_power_pin : VDD; + related_ground_pin : VSS; + internal_power() { + rise_power("scalar") { + values (0); + } + fall_power("scalar") { + values (0); + } + } + } + +bus(A_BIST_ADDR) { + bus_type : A_9_0; + direction : input ; + capacitance : 0.0115194 ; + pin(A_BIST_ADDR[0]) { + capacitance : 0.00563454 ; + } + pin(A_BIST_ADDR[1]) { + capacitance : 0.00744185 ; + } + pin(A_BIST_ADDR[2]) { + capacitance : 0.0100611 ; + } + pin(A_BIST_ADDR[3]) { + capacitance : 0.00669965 ; + } + pin(A_BIST_ADDR[4]) { + capacitance : 0.00614331 ; + } + pin(A_BIST_ADDR[5]) { + capacitance : 0.0102172 ; + } + pin(A_BIST_ADDR[6]) { + capacitance : 0.0124225 ; + } + pin(A_BIST_ADDR[7]) { + capacitance : 0.010114 ; + } + pin(A_BIST_ADDR[8]) { + capacitance : 0.0089001 ; + } + max_transition : "0.38" ; + pin(A_BIST_ADDR[9:0]) { + related_power_pin : VDD; + related_ground_pin : VSS; + internal_power() { + when : "A_BIST_MEN"; + rise_power("scalar"){ + values (0.4735); + } + fall_power("scalar"){ + values (0.6259); + } + } + internal_power() { + when : "!A_BIST_MEN"; + rise_power("scalar"){ + values (0.0322); + } + fall_power("scalar"){ + values (0.0023); + } + } + } + timing() { + timing_type : setup_rising; + related_pin : "A_BIST_CLK"; + when : "((A_BIST_WEN | A_BIST_REN)& A_BIST_MEN)" + sdf_cond : "A_BIST_RW_ACCESS" + + rise_constraint("SIG2SRAM_constraint_template") { + index_1("0.0040,0.0176,0.0344,0.0656,0.1120,0.2016,0.3800"); + index_2("0.0040,0.0176,0.0344,0.0656,0.1120,0.2016,0.3800"); + values ("-0.2371,-0.2215,-0.2098,-0.1824,-0.1434,-0.0691,0.0676",\ +"-0.2449,-0.2332,-0.2176,-0.1902,-0.1551,-0.0770,0.0559",\ +"-0.2605,-0.2488,-0.2332,-0.2059,-0.1707,-0.0965,0.0441",\ +"-0.2879,-0.2723,-0.2605,-0.2332,-0.1941,-0.1199,0.0168",\ +"-0.3230,-0.3113,-0.2996,-0.2723,-0.2332,-0.1590,-0.0184",\ +"-0.4012,-0.3895,-0.3738,-0.3465,-0.3074,-0.2332,-0.0965",\ +"-0.5379,-0.5262,-0.5105,-0.4832,-0.4480,-0.3699,-0.2332"); + } + + fall_constraint("SIG2SRAM_constraint_template") { + index_1("0.0040,0.0176,0.0344,0.0656,0.1120,0.2016,0.3800"); + index_2("0.0040,0.0176,0.0344,0.0656,0.1120,0.2016,0.3800"); + values ("-0.1785,-0.1707,-0.1551,-0.1277,-0.0887,-0.0184,0.1145",\ +"-0.1902,-0.1785,-0.1629,-0.1355,-0.1004,-0.0262,0.1027",\ +"-0.2059,-0.1941,-0.1785,-0.1512,-0.1160,-0.0418,0.0871",\ +"-0.2293,-0.2176,-0.2059,-0.1785,-0.1434,-0.0691,0.0598",\ +"-0.2684,-0.2566,-0.2449,-0.2176,-0.1824,-0.1082,0.0207",\ +"-0.3465,-0.3348,-0.3191,-0.2918,-0.2566,-0.1824,-0.0535",\ +"-0.4832,-0.4715,-0.4559,-0.4324,-0.3934,-0.3191,-0.1902"); + } + } + + + timing() { + timing_type : hold_rising; + related_pin : "A_BIST_CLK"; + when : "((A_BIST_WEN | A_BIST_REN)& A_BIST_MEN)" + sdf_cond : "A_BIST_RW_ACCESS" + + rise_constraint("SIG2SRAM_constraint_template") { + index_1("0.0040,0.0176,0.0344,0.0656,0.1120,0.2016,0.3800"); + index_2("0.0040,0.0176,0.0344,0.0656,0.1120,0.2016,0.3800"); + values ("0.3410,0.3293,0.3137,0.2863,0.2473,0.1730,0.0324",\ +"0.3488,0.3371,0.3215,0.2941,0.2590,0.1809,0.0480",\ +"0.3684,0.3527,0.3371,0.3098,0.2746,0.1965,0.0598",\ +"0.3918,0.3762,0.3645,0.3371,0.2980,0.2238,0.0871",\ +"0.4309,0.4152,0.4035,0.3762,0.3371,0.2629,0.1223",\ +"0.5051,0.4934,0.4777,0.4504,0.4113,0.3371,0.1965",\ +"0.6418,0.6262,0.6145,0.5871,0.5520,0.4738,0.3332"); + } + + fall_constraint("SIG2SRAM_constraint_template") { + index_1("0.0040,0.0176,0.0344,0.0656,0.1120,0.2016,0.3800"); + index_2("0.0040,0.0176,0.0344,0.0656,0.1120,0.2016,0.3800"); + values ("0.2824,0.2707,0.2551,0.2277,0.1926,0.1184,-0.0105",\ +"0.2902,0.2785,0.2668,0.2395,0.2043,0.1301,0.0012",\ +"0.3059,0.2941,0.2824,0.2551,0.2199,0.1457,0.0168",\ +"0.3332,0.3215,0.3059,0.2785,0.2434,0.1691,0.0402",\ +"0.3723,0.3605,0.3449,0.3176,0.2824,0.2121,0.0793",\ +"0.4465,0.4348,0.4230,0.3918,0.3566,0.2824,0.1535",\ +"0.5832,0.5715,0.5598,0.5324,0.4934,0.4191,0.2902"); + } + } +} +pin(A_BIST_WEN) { + direction : input ; + capacitance : 0.00341384 ; + max_transition : "0.38" ; + related_power_pin : VDD; + related_ground_pin : VSS; + internal_power() { + when : "A_BIST_MEN"; + rise_power("scalar"){ + values (0.9384); + } + fall_power("scalar"){ + values (0.0212); + } + } + internal_power() { + when : "!A_BIST_MEN"; + rise_power("scalar"){ + values (0.0069); + } + fall_power("scalar"){ + values (0.0124); + } + } + timing() { + timing_type : setup_rising; + related_pin : "A_BIST_CLK"; + when : "A_BIST_MEN" + sdf_cond : "A_BIST_MEN" + + rise_constraint("SIG2SRAM_constraint_template") { + index_1("0.0040,0.0176,0.0344,0.0656,0.1120,0.2016,0.3800"); + index_2("0.0040,0.0176,0.0344,0.0656,0.1120,0.2016,0.3800"); + values ("0.1418,0.1496,0.1652,0.1887,0.2316,0.3059,0.4465",\ +"0.1301,0.1379,0.1535,0.1809,0.2199,0.2941,0.4348",\ +"0.1145,0.1262,0.1379,0.1652,0.2043,0.2785,0.4191",\ +"0.0871,0.0949,0.1105,0.1379,0.1770,0.2512,0.3879",\ +"0.0480,0.0598,0.0754,0.0988,0.1379,0.2082,0.3527",\ +"-0.0262,-0.0145,0.0012,0.0246,0.0676,0.1379,0.2785",\ +"-0.1668,-0.1551,-0.1395,-0.1121,-0.0730,0.0012,0.1418"); + } + + fall_constraint("SIG2SRAM_constraint_template") { + index_1("0.0040,0.0176,0.0344,0.0656,0.1120,0.2016,0.3800"); + index_2("0.0040,0.0176,0.0344,0.0656,0.1120,0.2016,0.3800"); + values ("0.2082,0.2160,0.2316,0.2590,0.2941,0.3684,0.5012",\ +"0.1926,0.2043,0.2199,0.2473,0.2824,0.3566,0.4895",\ +"0.1770,0.1887,0.2043,0.2316,0.2668,0.3410,0.4777",\ +"0.1535,0.1652,0.1770,0.2043,0.2395,0.3137,0.4504",\ +"0.1145,0.1262,0.1379,0.1652,0.2043,0.2746,0.4113",\ +"0.0402,0.0520,0.0676,0.0910,0.1262,0.2004,0.3332",\ +"-0.0965,-0.0848,-0.0730,-0.0457,-0.0066,0.0637,0.2004"); + } + } + + + timing() { + timing_type : hold_rising; + related_pin : "A_BIST_CLK"; + when : "A_BIST_MEN" + sdf_cond : "A_BIST_MEN" + + rise_constraint("SIG2SRAM_constraint_template") { + index_1("0.0040,0.0176,0.0344,0.0656,0.1120,0.2016,0.3800"); + index_2("0.0040,0.0176,0.0344,0.0656,0.1120,0.2016,0.3800"); + values ("0.1770,0.1652,0.1496,0.1223,0.0793,0.0090,-0.1316",\ +"0.1848,0.1730,0.1574,0.1301,0.0910,0.0168,-0.1199",\ +"0.2004,0.1887,0.1770,0.1496,0.1066,0.0363,-0.1043",\ +"0.2277,0.2160,0.2004,0.1730,0.1340,0.0598,-0.0809",\ +"0.2668,0.2551,0.2395,0.2121,0.1730,0.0988,-0.0418",\ +"0.3410,0.3293,0.3137,0.2863,0.2434,0.1730,0.0324",\ +"0.4816,0.4699,0.4543,0.4230,0.3801,0.3098,0.1730"); + } + + fall_constraint("SIG2SRAM_constraint_template") { + index_1("0.0040,0.0176,0.0344,0.0656,0.1120,0.2016,0.3800"); + index_2("0.0040,0.0176,0.0344,0.0656,0.1120,0.2016,0.3800"); + values ("0.1613,0.1496,0.1379,0.1066,0.0715,0.0012,-0.1355",\ +"0.1730,0.1613,0.1457,0.1184,0.0832,0.0129,-0.1238",\ +"0.1887,0.1770,0.1613,0.1340,0.0988,0.0246,-0.1121",\ +"0.2121,0.2043,0.1887,0.1613,0.1223,0.0520,-0.0848",\ +"0.2512,0.2434,0.2277,0.2004,0.1613,0.0910,-0.0457",\ +"0.3254,0.3176,0.3020,0.2746,0.2355,0.1652,0.0324",\ +"0.4660,0.4543,0.4387,0.4113,0.3723,0.3020,0.1691"); + } + } + } +pin(A_BIST_REN) { + direction : input ; + capacitance : 0.00390661 ; + max_transition : "0.38" ; + related_power_pin : VDD; + related_ground_pin : VSS; + internal_power() { + when : "A_BIST_MEN"; + rise_power("scalar"){ + values (0.0154); + } + fall_power("scalar"){ + values (0.0113); + } + } + internal_power() { + when : "!A_BIST_MEN"; + rise_power("scalar"){ + values (0.0276); + } + fall_power("scalar"){ + values (0.0235); + } + } + timing() { + timing_type : setup_rising; + related_pin : "A_BIST_CLK"; + when : "A_BIST_MEN" + sdf_cond : "A_BIST_MEN" + + rise_constraint("SIG2SRAM_constraint_template") { + index_1("0.0040,0.0176,0.0344,0.0656,0.1120,0.2016,0.3800"); + index_2("0.0040,0.0176,0.0344,0.0656,0.1120,0.2016,0.3800"); + values ("-0.0027,0.0090,0.0246,0.0520,0.0910,0.1613,0.3020",\ +"-0.0105,0.0012,0.0129,0.0363,0.0793,0.1535,0.2902",\ +"-0.0262,-0.0145,-0.0027,0.0246,0.0637,0.1379,0.2785",\ +"-0.0535,-0.0418,-0.0262,0.0012,0.0363,0.1105,0.2512",\ +"-0.0926,-0.0809,-0.0652,-0.0418,-0.0027,0.0715,0.2121",\ +"-0.1668,-0.1551,-0.1395,-0.1082,-0.0770,-0.0027,0.1379",\ +"-0.3035,-0.2918,-0.2762,-0.2488,-0.2137,-0.1434,-0.0027"); + } + + fall_constraint("SIG2SRAM_constraint_template") { + index_1("0.0040,0.0176,0.0344,0.0656,0.1120,0.2016,0.3800"); + index_2("0.0040,0.0176,0.0344,0.0656,0.1120,0.2016,0.3800"); + values ("0.0832,0.0949,0.1105,0.1379,0.1730,0.2473,0.3801",\ +"0.0754,0.0832,0.0988,0.1223,0.1613,0.2355,0.3684",\ +"0.0598,0.0676,0.0832,0.1066,0.1457,0.2121,0.3527",\ +"0.0324,0.0441,0.0598,0.0871,0.1223,0.1926,0.3293",\ +"-0.0066,0.0051,0.0168,0.0480,0.0832,0.1535,0.2902",\ +"-0.0809,-0.0691,-0.0574,-0.0301,0.0090,0.0832,0.2121",\ +"-0.2176,-0.2059,-0.1941,-0.1668,-0.1277,-0.0574,0.0793"); + } + } + + + timing() { + timing_type : hold_rising; + related_pin : "A_BIST_CLK"; + when : "A_BIST_MEN" + sdf_cond : "A_BIST_MEN" + + rise_constraint("SIG2SRAM_constraint_template") { + index_1("0.0040,0.0176,0.0344,0.0656,0.1120,0.2016,0.3800"); + index_2("0.0040,0.0176,0.0344,0.0656,0.1120,0.2016,0.3800"); + values ("0.1887,0.1770,0.1613,0.1340,0.0949,0.0207,-0.1160",\ +"0.1965,0.1848,0.1730,0.1457,0.1027,0.0324,-0.1082",\ +"0.2160,0.2004,0.1887,0.1613,0.1184,0.0480,-0.0926",\ +"0.2395,0.2277,0.2121,0.1848,0.1457,0.0715,-0.0652",\ +"0.2785,0.2668,0.2512,0.2238,0.1848,0.1105,-0.0262",\ +"0.3527,0.3410,0.3254,0.2980,0.2551,0.1848,0.0480",\ +"0.4934,0.4816,0.4660,0.4387,0.3957,0.3254,0.1887"); + } + + fall_constraint("SIG2SRAM_constraint_template") { + index_1("0.0040,0.0176,0.0344,0.0656,0.1120,0.2016,0.3800"); + index_2("0.0040,0.0176,0.0344,0.0656,0.1120,0.2016,0.3800"); + values ("0.1730,0.1613,0.1496,0.1184,0.0793,0.0129,-0.1238",\ +"0.1848,0.1730,0.1574,0.1301,0.0910,0.0207,-0.1121",\ +"0.2004,0.1887,0.1730,0.1457,0.1066,0.0363,-0.1004",\ +"0.2238,0.2121,0.2004,0.1691,0.1340,0.0598,-0.0730",\ +"0.2629,0.2512,0.2395,0.2121,0.1691,0.0988,-0.0340",\ +"0.3371,0.3254,0.3137,0.2863,0.2434,0.1730,0.0402",\ +"0.4777,0.4660,0.4504,0.4230,0.3840,0.3137,0.1809"); + } + } + } +pin(A_BIST_MEN) { + direction : input ; + capacitance : 0.00326046 ; + max_transition : "0.38" ; + related_power_pin : VDD; + related_ground_pin : VSS; + internal_power() { + rise_power("scalar"){ + values (0.2886); + } + fall_power("scalar"){ + values (0.4759); + } + } + timing() { + timing_type : setup_rising; + related_pin : "A_BIST_CLK"; + + rise_constraint("SIG2SRAM_constraint_template") { + index_1("0.0040,0.0176,0.0344,0.0656,0.1120,0.2016,0.3800"); + index_2("0.0040,0.0176,0.0344,0.0656,0.1120,0.2016,0.3800"); + values ("0.1418,0.1496,0.1652,0.1926,0.2316,0.3059,0.4465",\ +"0.1301,0.1379,0.1535,0.1809,0.2199,0.2941,0.4348",\ +"0.1145,0.1262,0.1418,0.1652,0.2043,0.2785,0.4191",\ +"0.0871,0.0949,0.1105,0.1379,0.1770,0.2512,0.3879",\ +"0.0480,0.0598,0.0754,0.0988,0.1379,0.2082,0.3488",\ +"-0.0262,-0.0145,0.0012,0.0285,0.0676,0.1379,0.2785",\ +"-0.1668,-0.1551,-0.1395,-0.1121,-0.0730,0.0012,0.1379"); + } + + fall_constraint("SIG2SRAM_constraint_template") { + index_1("0.0040,0.0176,0.0344,0.0656,0.1120,0.2016,0.3800"); + index_2("0.0040,0.0176,0.0344,0.0656,0.1120,0.2016,0.3800"); + values ("0.2082,0.2199,0.2316,0.2590,0.2980,0.3723,0.5051",\ +"0.1965,0.2082,0.2199,0.2473,0.2863,0.3605,0.4934",\ +"0.1809,0.1926,0.2043,0.2316,0.2707,0.3449,0.4777",\ +"0.1574,0.1691,0.1809,0.2082,0.2434,0.3176,0.4543",\ +"0.1145,0.1262,0.1418,0.1691,0.2043,0.2785,0.4113",\ +"0.0441,0.0559,0.0676,0.0949,0.1301,0.2004,0.3332",\ +"-0.0965,-0.0848,-0.0691,-0.0418,-0.0066,0.0676,0.2004"); + } + } + + + timing() { + timing_type : hold_rising; + related_pin : "A_BIST_CLK"; + + rise_constraint("SIG2SRAM_constraint_template") { + index_1("0.0040,0.0176,0.0344,0.0656,0.1120,0.2016,0.3800"); + index_2("0.0040,0.0176,0.0344,0.0656,0.1120,0.2016,0.3800"); + values ("0.1770,0.1652,0.1535,0.1262,0.0832,0.0129,-0.1277",\ +"0.1887,0.1770,0.1613,0.1340,0.0949,0.0207,-0.1199",\ +"0.2043,0.1926,0.1770,0.1496,0.1105,0.0363,-0.1043",\ +"0.2277,0.2160,0.2043,0.1770,0.1379,0.0598,-0.0770",\ +"0.2668,0.2551,0.2434,0.2160,0.1730,0.0988,-0.0379",\ +"0.3449,0.3332,0.3176,0.2902,0.2473,0.1730,0.0363",\ +"0.4816,0.4699,0.4543,0.4270,0.3840,0.3098,0.1770"); + } + + fall_constraint("SIG2SRAM_constraint_template") { + index_1("0.0040,0.0176,0.0344,0.0656,0.1120,0.2016,0.3800"); + index_2("0.0040,0.0176,0.0344,0.0656,0.1120,0.2016,0.3800"); + values ("0.1613,0.1496,0.1379,0.1105,0.0715,0.0012,-0.1355",\ +"0.1730,0.1613,0.1496,0.1184,0.0832,0.0129,-0.1238",\ +"0.1887,0.1770,0.1652,0.1340,0.0988,0.0285,-0.1121",\ +"0.2121,0.2043,0.1887,0.1613,0.1223,0.0520,-0.0848",\ +"0.2551,0.2434,0.2277,0.2004,0.1613,0.0910,-0.0418",\ +"0.3293,0.3176,0.3020,0.2746,0.2395,0.1652,0.0324",\ +"0.4660,0.4543,0.4426,0.4113,0.3762,0.3020,0.1691"); + } + } + } +bus(A_BIST_BM) { + bus_type : D_31_0; + direction : input ; + capacitance : 0.00353394 ; + max_transition : "0.38" ; + pin(A_BIST_BM[31:0]) { + related_power_pin : VDD; + related_ground_pin : VSS; + internal_power() { + when : "A_BIST_MEN"; + rise_power("scalar"){ + values (0.1512); + } + fall_power("scalar"){ + values (0.1660); + } + } + internal_power() { + when : "!A_BIST_MEN"; + rise_power("scalar"){ + values (0.1918); + } + fall_power("scalar"){ + values (0.1601); + } + } + } + timing() { + timing_type : setup_rising; + related_pin : "A_BIST_CLK"; + when : "(A_BIST_WEN & A_BIST_MEN)" + sdf_cond : "A_BIST_RW_ACCESS" + + rise_constraint("SIG2SRAM_constraint_template") { + index_1("0.0040,0.0176,0.0344,0.0656,0.1120,0.2016,0.3800"); + index_2("0.0040,0.0176,0.0344,0.0656,0.1120,0.2016,0.3800"); + values ("-0.2899,-0.2791,-0.2635,-0.2381,-0.1971,-0.1238,0.0109",\ +"-0.2937,-0.2830,-0.2674,-0.2420,-0.2010,-0.1277,0.0070",\ +"-0.2975,-0.2868,-0.2712,-0.2458,-0.2048,-0.1315,0.0032",\ +"-0.3008,-0.2901,-0.2744,-0.2490,-0.2080,-0.1348,-0.0000",\ +"-0.3132,-0.3025,-0.2869,-0.2615,-0.2205,-0.1472,-0.0125",\ +"-0.3307,-0.3200,-0.3043,-0.2789,-0.2379,-0.1647,-0.0299",\ +"-0.3584,-0.3476,-0.3320,-0.3066,-0.2656,-0.1923,-0.0576"); + } + + fall_constraint("SIG2SRAM_constraint_template") { + index_1("0.0040,0.0176,0.0344,0.0656,0.1120,0.2016,0.3800"); + index_2("0.0040,0.0176,0.0344,0.0656,0.1120,0.2016,0.3800"); + values ("-0.2664,-0.2547,-0.2420,-0.2147,-0.1776,-0.1043,0.0236",\ +"-0.2703,-0.2586,-0.2459,-0.2185,-0.1814,-0.1082,0.0197",\ +"-0.2741,-0.2624,-0.2497,-0.2223,-0.1852,-0.1120,0.0159",\ +"-0.2774,-0.2656,-0.2529,-0.2256,-0.1885,-0.1152,0.0127",\ +"-0.2898,-0.2781,-0.2654,-0.2380,-0.2009,-0.1277,0.0002",\ +"-0.3073,-0.2955,-0.2828,-0.2555,-0.2184,-0.1452,-0.0172",\ +"-0.3349,-0.3232,-0.3105,-0.2832,-0.2461,-0.1728,-0.0449"); + } + } + + + timing() { + timing_type : hold_rising; + related_pin : "A_BIST_CLK"; + when : "(A_BIST_WEN & A_BIST_MEN)" + sdf_cond : "A_BIST_RW_ACCESS" + + rise_constraint("SIG2SRAM_constraint_template") { + index_1("0.0040,0.0176,0.0344,0.0656,0.1120,0.2016,0.3800"); + index_2("0.0040,0.0176,0.0344,0.0656,0.1120,0.2016,0.3800"); + values ("0.3958,0.3861,0.3705,0.3441,0.3070,0.2328,0.0980",\ +"0.3997,0.3900,0.3743,0.3480,0.3109,0.2366,0.1019",\ +"0.4035,0.3938,0.3781,0.3518,0.3147,0.2404,0.1057",\ +"0.4068,0.3970,0.3814,0.3550,0.3179,0.2437,0.1089",\ +"0.4192,0.4095,0.3938,0.3675,0.3304,0.2561,0.1214",\ +"0.4367,0.4269,0.4113,0.3849,0.3478,0.2736,0.1388",\ +"0.4643,0.4546,0.4389,0.4126,0.3755,0.3013,0.1665"); + } + + fall_constraint("SIG2SRAM_constraint_template") { + index_1("0.0040,0.0176,0.0344,0.0656,0.1120,0.2016,0.3800"); + index_2("0.0040,0.0176,0.0344,0.0656,0.1120,0.2016,0.3800"); + values ("0.3675,0.3568,0.3431,0.3158,0.2796,0.2074,0.0775",\ +"0.3714,0.3607,0.3470,0.3196,0.2835,0.2113,0.0814",\ +"0.3752,0.3645,0.3508,0.3234,0.2873,0.2150,0.0852",\ +"0.3785,0.3677,0.3540,0.3267,0.2906,0.2183,0.0884",\ +"0.3909,0.3802,0.3665,0.3391,0.3030,0.2307,0.1009",\ +"0.4084,0.3976,0.3839,0.3566,0.3205,0.2482,0.1183",\ +"0.4360,0.4253,0.4116,0.3843,0.3481,0.2759,0.1460"); + } + } +} + pin(A_BIST_CLK) { + direction : input; + capacitance : 0.00389386; + max_transition : "0.38"; + clock : "true" ; + pin_func_type : active_rising ; + + timing () { + timing_type : "min_pulse_width"; + related_pin : "A_BIST_CLK"; + rise_constraint("CLKTRAN_constraint_template") { + index_1("0.004,0.38"); + values("0.12,0.12"); + } + } + + related_power_pin : VDD; + related_ground_pin : VSS; + + internal_power() { + when : "!A_BIST_MEN & !A_BIST_WEN & !A_BIST_REN"; + rise_power("scalar"){ + values (0); + } + fall_power("scalar"){ + values (0); + } + } + internal_power() { + when : "!A_BIST_MEN & A_BIST_WEN & !A_BIST_REN"; + rise_power("scalar"){ + values (0.7228); + } + fall_power("scalar"){ + values (0); + } + } + internal_power() { + when : "A_BIST_MEN & A_BIST_WEN & !A_BIST_REN"; + rise_power("scalar"){ + values (73.7434); + } + fall_power("scalar"){ + values (0); + } + } + internal_power() { + when : "A_BIST_MEN & A_BIST_WEN & A_BIST_REN"; + rise_power("scalar"){ + values (76.2622); + } + fall_power("scalar"){ + values (0); + } + } + internal_power() { + when : "A_BIST_MEN & !A_BIST_WEN & A_BIST_REN"; + rise_power("scalar"){ + values (61.9692); + } + fall_power("scalar"){ + values (0); + } + } + internal_power() { + when : "!A_BIST_MEN & !A_BIST_WEN & A_BIST_REN"; + rise_power("scalar"){ + values (0.4287); + } + fall_power("scalar"){ + values (0); + } + } + internal_power() { + when : "!A_BIST_MEN & A_BIST_WEN & A_BIST_REN"; + rise_power("scalar"){ + values (1.4323); + } + fall_power("scalar"){ + values (0); + } + } + internal_power() { + when : "A_BIST_MEN & !A_BIST_WEN & !A_BIST_REN"; + rise_power("scalar"){ + values (0); + } + fall_power("scalar"){ + values (0); + } + } + } + bus(A_BIST_DIN) { + bus_type : D_31_0; + direction : input ; + capacitance : 0.00397186 ; + memory_write() { + address : A_BIST_ADDR ; + clocked_on : A_BIST_CLK; + } + + max_transition : "0.38" ; + pin(A_BIST_DIN[31:0]) { + related_power_pin : VDD; + related_ground_pin : VSS; + internal_power() { + when : "A_BIST_MEN"; + rise_power("scalar"){ + values (0.1512); + } + fall_power("scalar"){ + values (0.1660); + } + } + internal_power() { + when : "!A_BIST_MEN"; + rise_power("scalar"){ + values (0.1918); + } + fall_power("scalar"){ + values (0.1601); + } + } + } + timing() { + timing_type : setup_rising; + related_pin : "A_BIST_CLK"; + when : "(A_BIST_WEN & A_BIST_MEN)"; + sdf_cond : "A_BIST_W_ACCESS"; + + rise_constraint("SIG2SRAM_constraint_template") { + index_1("0.0040,0.0176,0.0344,0.0656,0.1120,0.2016,0.3800"); + index_2("0.0040,0.0176,0.0344,0.0656,0.1120,0.2016,0.3800"); + values ("-0.2899,-0.2791,-0.2635,-0.2381,-0.1971,-0.1238,0.0109",\ +"-0.2937,-0.2830,-0.2674,-0.2420,-0.2010,-0.1277,0.0070",\ +"-0.2975,-0.2868,-0.2712,-0.2458,-0.2048,-0.1315,0.0032",\ +"-0.3008,-0.2901,-0.2744,-0.2490,-0.2080,-0.1348,-0.0000",\ +"-0.3132,-0.3025,-0.2869,-0.2615,-0.2205,-0.1472,-0.0125",\ +"-0.3307,-0.3200,-0.3043,-0.2789,-0.2379,-0.1647,-0.0299",\ +"-0.3584,-0.3476,-0.3320,-0.3066,-0.2656,-0.1923,-0.0576"); + } + + fall_constraint("SIG2SRAM_constraint_template") { + index_1("0.0040,0.0176,0.0344,0.0656,0.1120,0.2016,0.3800"); + index_2("0.0040,0.0176,0.0344,0.0656,0.1120,0.2016,0.3800"); + values ("-0.2664,-0.2547,-0.2420,-0.2147,-0.1776,-0.1043,0.0236",\ +"-0.2703,-0.2586,-0.2459,-0.2185,-0.1814,-0.1082,0.0197",\ +"-0.2741,-0.2624,-0.2497,-0.2223,-0.1852,-0.1120,0.0159",\ +"-0.2774,-0.2656,-0.2529,-0.2256,-0.1885,-0.1152,0.0127",\ +"-0.2898,-0.2781,-0.2654,-0.2380,-0.2009,-0.1277,0.0002",\ +"-0.3073,-0.2955,-0.2828,-0.2555,-0.2184,-0.1452,-0.0172",\ +"-0.3349,-0.3232,-0.3105,-0.2832,-0.2461,-0.1728,-0.0449"); + } + } + + timing() { + timing_type : hold_rising; + related_pin : "A_BIST_CLK"; + when : "(A_BIST_WEN & A_BIST_MEN)"; + sdf_cond : "A_BIST_W_ACCESS"; + + rise_constraint("SIG2SRAM_constraint_template") { + index_1("0.0040,0.0176,0.0344,0.0656,0.1120,0.2016,0.3800"); + index_2("0.0040,0.0176,0.0344,0.0656,0.1120,0.2016,0.3800"); + values ("0.3958,0.3861,0.3705,0.3441,0.3070,0.2328,0.0980",\ +"0.3997,0.3900,0.3743,0.3480,0.3109,0.2366,0.1019",\ +"0.4035,0.3938,0.3781,0.3518,0.3147,0.2404,0.1057",\ +"0.4068,0.3970,0.3814,0.3550,0.3179,0.2437,0.1089",\ +"0.4192,0.4095,0.3938,0.3675,0.3304,0.2561,0.1214",\ +"0.4367,0.4269,0.4113,0.3849,0.3478,0.2736,0.1388",\ +"0.4643,0.4546,0.4389,0.4126,0.3755,0.3013,0.1665"); + } + + fall_constraint("SIG2SRAM_constraint_template") { + index_1("0.0040,0.0176,0.0344,0.0656,0.1120,0.2016,0.3800"); + index_2("0.0040,0.0176,0.0344,0.0656,0.1120,0.2016,0.3800"); + values ("0.3675,0.3568,0.3431,0.3158,0.2796,0.2074,0.0775",\ +"0.3714,0.3607,0.3470,0.3196,0.2835,0.2113,0.0814",\ +"0.3752,0.3645,0.3508,0.3234,0.2873,0.2150,0.0852",\ +"0.3785,0.3677,0.3540,0.3267,0.2906,0.2183,0.0884",\ +"0.3909,0.3802,0.3665,0.3391,0.3030,0.2307,0.1009",\ +"0.4084,0.3976,0.3839,0.3566,0.3205,0.2482,0.1183",\ +"0.4360,0.4253,0.4116,0.3843,0.3481,0.2759,0.1460"); + } + } + } + +bus(A_DOUT) { + + bus_type : D_31_0; + direction : output ; + capacitance : 0 ; + max_capacitance : 0.064 ; + memory_read() { + address : A_ADDR ; + } + pin(A_DOUT[31:0]) { + related_power_pin : VDD; + related_ground_pin : VSS; + internal_power() { + rise_power("scalar") { + values (0); + } + fall_power("scalar") { + values (0); + } + } + } + timing() { + related_pin : "A_CLK"; + timing_type : rising_edge ; + timing_sense : non_unate ; + + cell_rise(SIG2SRAM_delay_template) { + index_1("0.0040,0.0176,0.0344,0.0656,0.1120,0.2016,0.3800"); + index_2("0.0008,0.0014,0.0051,0.0100,0.0339,0.0640"); + values ("2.7179,2.7189,2.7237,2.7292,2.7502,2.7737",\ +"2.7251,2.7261,2.7309,2.7365,2.7574,2.7809",\ +"2.7266,2.7276,2.7324,2.7379,2.7588,2.7823",\ +"2.7299,2.7309,2.7358,2.7413,2.7622,2.7857",\ +"2.7428,2.7438,2.7486,2.7541,2.7750,2.7985",\ +"2.7605,2.7615,2.7663,2.7719,2.7928,2.8163",\ +"2.7859,2.7869,2.7917,2.7972,2.8182,2.8417"); + } + cell_fall(SIG2SRAM_delay_template) { + index_1("0.0040,0.0176,0.0344,0.0656,0.1120,0.2016,0.3800"); + index_2("0.0008,0.0014,0.0051,0.0100,0.0339,0.0640"); + values ("2.6836,2.6845,2.6885,2.6931,2.7101,2.7269",\ +"2.6908,2.6917,2.6957,2.7003,2.7174,2.7341",\ +"2.6923,2.6932,2.6972,2.7017,2.7188,2.7356",\ +"2.6956,2.6965,2.7005,2.7051,2.7222,2.7389",\ +"2.7085,2.7093,2.7134,2.7179,2.7350,2.7517",\ +"2.7262,2.7271,2.7311,2.7357,2.7528,2.7695",\ +"2.7516,2.7525,2.7565,2.7611,2.7781,2.7949"); + } + + rise_transition(SRAM_load_template) { + index_1("0.0008,0.0014,0.0051,0.0100,0.0339,0.0640"); + values ("0.0206,0.0210,0.0265,0.0323,0.0606,0.0955"); + } + fall_transition(SRAM_load_template) { + index_1("0.0008,0.0014,0.0051,0.0100,0.0339,0.0640"); + values ("0.0170,0.0177,0.0222,0.0270,0.0451,0.0644"); + } + } +} + pin(B_DLY) { + direction : input ; + capacitance : 0.00421562 ; + max_transition : "1" ; + related_power_pin : VDD; + related_ground_pin : VSS; + internal_power() { + rise_power("scalar") { + values (0); + } + fall_power("scalar") { + values (0); + } + } + } + +bus(B_ADDR) { + bus_type : A_9_0; + direction : input ; + capacitance : 0.0115194 ; + pin(B_ADDR[0]) { + capacitance : 0.0056487 ; + } + pin(B_ADDR[1]) { + capacitance : 0.00741688 ; + } + pin(B_ADDR[2]) { + capacitance : 0.0100613 ; + } + pin(B_ADDR[3]) { + capacitance : 0.00667339 ; + } + pin(B_ADDR[4]) { + capacitance : 0.00620204 ; + } + pin(B_ADDR[5]) { + capacitance : 0.0101975 ; + } + pin(B_ADDR[6]) { + capacitance : 0.0124055 ; + } + pin(B_ADDR[7]) { + capacitance : 0.0101065 ; + } + pin(B_ADDR[8]) { + capacitance : 0.00887215 ; + } + max_transition : "0.38" ; + pin(B_ADDR[9:0]) { + related_power_pin : VDD; + related_ground_pin : VSS; + internal_power() { + when : "B_MEN"; + rise_power("scalar"){ + values (0.4735); + } + fall_power("scalar"){ + values (0.6259); + } + } + internal_power() { + when : "!B_MEN"; + rise_power("scalar"){ + values (0.0322); + } + fall_power("scalar"){ + values (0.0023); + } + } + } + timing() { + timing_type : setup_rising; + related_pin : "B_CLK"; + when : "((B_WEN | B_REN)& B_MEN)" + sdf_cond : "B_RW_ACCESS" + + rise_constraint("SIG2SRAM_constraint_template") { + index_1("0.0040,0.0176,0.0344,0.0656,0.1120,0.2016,0.3800"); + index_2("0.0040,0.0176,0.0344,0.0656,0.1120,0.2016,0.3800"); + values ("-0.2371,-0.2215,-0.2098,-0.1824,-0.1434,-0.0691,0.0676",\ +"-0.2449,-0.2332,-0.2176,-0.1902,-0.1551,-0.0770,0.0559",\ +"-0.2605,-0.2488,-0.2332,-0.2059,-0.1707,-0.0965,0.0441",\ +"-0.2879,-0.2723,-0.2605,-0.2332,-0.1941,-0.1199,0.0168",\ +"-0.3230,-0.3113,-0.2996,-0.2723,-0.2332,-0.1590,-0.0184",\ +"-0.4012,-0.3895,-0.3738,-0.3465,-0.3074,-0.2332,-0.0965",\ +"-0.5379,-0.5262,-0.5105,-0.4832,-0.4480,-0.3699,-0.2332"); + } + + fall_constraint("SIG2SRAM_constraint_template") { + index_1("0.0040,0.0176,0.0344,0.0656,0.1120,0.2016,0.3800"); + index_2("0.0040,0.0176,0.0344,0.0656,0.1120,0.2016,0.3800"); + values ("-0.1785,-0.1707,-0.1551,-0.1277,-0.0887,-0.0184,0.1145",\ +"-0.1902,-0.1785,-0.1629,-0.1355,-0.1004,-0.0262,0.1027",\ +"-0.2059,-0.1941,-0.1785,-0.1512,-0.1160,-0.0418,0.0871",\ +"-0.2293,-0.2176,-0.2059,-0.1785,-0.1434,-0.0691,0.0598",\ +"-0.2684,-0.2566,-0.2449,-0.2176,-0.1824,-0.1082,0.0207",\ +"-0.3465,-0.3348,-0.3191,-0.2918,-0.2566,-0.1824,-0.0535",\ +"-0.4832,-0.4715,-0.4559,-0.4324,-0.3934,-0.3191,-0.1902"); + } + } + + + timing() { + timing_type : hold_rising; + related_pin : "B_CLK"; + when : "((B_WEN | B_REN)& B_MEN)" + sdf_cond : "B_RW_ACCESS" + + rise_constraint("SIG2SRAM_constraint_template") { + index_1("0.0040,0.0176,0.0344,0.0656,0.1120,0.2016,0.3800"); + index_2("0.0040,0.0176,0.0344,0.0656,0.1120,0.2016,0.3800"); + values ("0.3410,0.3293,0.3137,0.2863,0.2473,0.1730,0.0324",\ +"0.3488,0.3371,0.3215,0.2941,0.2590,0.1809,0.0480",\ +"0.3684,0.3527,0.3371,0.3098,0.2746,0.1965,0.0598",\ +"0.3918,0.3762,0.3645,0.3371,0.2980,0.2238,0.0871",\ +"0.4309,0.4152,0.4035,0.3762,0.3371,0.2629,0.1223",\ +"0.5051,0.4934,0.4777,0.4504,0.4113,0.3371,0.1965",\ +"0.6418,0.6262,0.6145,0.5871,0.5520,0.4738,0.3332"); + } + + fall_constraint("SIG2SRAM_constraint_template") { + index_1("0.0040,0.0176,0.0344,0.0656,0.1120,0.2016,0.3800"); + index_2("0.0040,0.0176,0.0344,0.0656,0.1120,0.2016,0.3800"); + values ("0.2824,0.2707,0.2551,0.2277,0.1926,0.1184,-0.0105",\ +"0.2902,0.2785,0.2668,0.2395,0.2043,0.1301,0.0012",\ +"0.3059,0.2941,0.2824,0.2551,0.2199,0.1457,0.0168",\ +"0.3332,0.3215,0.3059,0.2785,0.2434,0.1691,0.0402",\ +"0.3723,0.3605,0.3449,0.3176,0.2824,0.2121,0.0793",\ +"0.4465,0.4348,0.4230,0.3918,0.3566,0.2824,0.1535",\ +"0.5832,0.5715,0.5598,0.5324,0.4934,0.4191,0.2902"); + } + } +} +pin(B_WEN) { + direction : input ; + capacitance : 0.00341384 ; + max_transition : "0.38" ; + related_power_pin : VDD; + related_ground_pin : VSS; + internal_power() { + when : "B_MEN"; + rise_power("scalar"){ + values (0.9384); + } + fall_power("scalar"){ + values (0.0212); + } + } + internal_power() { + when : "!B_MEN"; + rise_power("scalar"){ + values (0.0069); + } + fall_power("scalar"){ + values (0.0124); + } + } + timing() { + timing_type : setup_rising; + related_pin : "B_CLK"; + when : "B_MEN" + sdf_cond : "B_MEN" + + rise_constraint("SIG2SRAM_constraint_template") { + index_1("0.0040,0.0176,0.0344,0.0656,0.1120,0.2016,0.3800"); + index_2("0.0040,0.0176,0.0344,0.0656,0.1120,0.2016,0.3800"); + values ("0.1418,0.1496,0.1652,0.1887,0.2316,0.3059,0.4465",\ +"0.1301,0.1379,0.1535,0.1809,0.2199,0.2941,0.4348",\ +"0.1145,0.1262,0.1379,0.1652,0.2043,0.2785,0.4191",\ +"0.0871,0.0949,0.1105,0.1379,0.1770,0.2512,0.3879",\ +"0.0480,0.0598,0.0754,0.0988,0.1379,0.2082,0.3527",\ +"-0.0262,-0.0145,0.0012,0.0246,0.0676,0.1379,0.2785",\ +"-0.1668,-0.1551,-0.1395,-0.1121,-0.0730,0.0012,0.1418"); + } + + fall_constraint("SIG2SRAM_constraint_template") { + index_1("0.0040,0.0176,0.0344,0.0656,0.1120,0.2016,0.3800"); + index_2("0.0040,0.0176,0.0344,0.0656,0.1120,0.2016,0.3800"); + values ("0.2082,0.2160,0.2316,0.2590,0.2941,0.3684,0.5012",\ +"0.1926,0.2043,0.2199,0.2473,0.2824,0.3566,0.4895",\ +"0.1770,0.1887,0.2043,0.2316,0.2668,0.3410,0.4777",\ +"0.1535,0.1652,0.1770,0.2043,0.2395,0.3137,0.4504",\ +"0.1145,0.1262,0.1379,0.1652,0.2043,0.2746,0.4113",\ +"0.0402,0.0520,0.0676,0.0910,0.1262,0.2004,0.3332",\ +"-0.0965,-0.0848,-0.0730,-0.0457,-0.0066,0.0637,0.2004"); + } + } + + + timing() { + timing_type : hold_rising; + related_pin : "B_CLK"; + when : "B_MEN" + sdf_cond : "B_MEN" + + rise_constraint("SIG2SRAM_constraint_template") { + index_1("0.0040,0.0176,0.0344,0.0656,0.1120,0.2016,0.3800"); + index_2("0.0040,0.0176,0.0344,0.0656,0.1120,0.2016,0.3800"); + values ("0.1770,0.1652,0.1496,0.1223,0.0793,0.0090,-0.1316",\ +"0.1848,0.1730,0.1574,0.1301,0.0910,0.0168,-0.1199",\ +"0.2004,0.1887,0.1770,0.1496,0.1066,0.0363,-0.1043",\ +"0.2277,0.2160,0.2004,0.1730,0.1340,0.0598,-0.0809",\ +"0.2668,0.2551,0.2395,0.2121,0.1730,0.0988,-0.0418",\ +"0.3410,0.3293,0.3137,0.2863,0.2434,0.1730,0.0324",\ +"0.4816,0.4699,0.4543,0.4230,0.3801,0.3098,0.1730"); + } + + fall_constraint("SIG2SRAM_constraint_template") { + index_1("0.0040,0.0176,0.0344,0.0656,0.1120,0.2016,0.3800"); + index_2("0.0040,0.0176,0.0344,0.0656,0.1120,0.2016,0.3800"); + values ("0.1613,0.1496,0.1379,0.1066,0.0715,0.0012,-0.1355",\ +"0.1730,0.1613,0.1457,0.1184,0.0832,0.0129,-0.1238",\ +"0.1887,0.1770,0.1613,0.1340,0.0988,0.0246,-0.1121",\ +"0.2121,0.2043,0.1887,0.1613,0.1223,0.0520,-0.0848",\ +"0.2512,0.2434,0.2277,0.2004,0.1613,0.0910,-0.0457",\ +"0.3254,0.3176,0.3020,0.2746,0.2355,0.1652,0.0324",\ +"0.4660,0.4543,0.4387,0.4113,0.3723,0.3020,0.1691"); + } + } + } +pin(B_REN) { + direction : input ; + capacitance : 0.00390661 ; + max_transition : "0.38" ; + related_power_pin : VDD; + related_ground_pin : VSS; + internal_power() { + when : "B_MEN"; + rise_power("scalar"){ + values (0.0154); + } + fall_power("scalar"){ + values (0.0113); + } + } + internal_power() { + when : "!B_MEN"; + rise_power("scalar"){ + values (0.0276); + } + fall_power("scalar"){ + values (0.0235); + } + } + timing() { + timing_type : setup_rising; + related_pin : "B_CLK"; + when : "B_MEN" + sdf_cond : "B_MEN" + + rise_constraint("SIG2SRAM_constraint_template") { + index_1("0.0040,0.0176,0.0344,0.0656,0.1120,0.2016,0.3800"); + index_2("0.0040,0.0176,0.0344,0.0656,0.1120,0.2016,0.3800"); + values ("-0.0027,0.0090,0.0246,0.0520,0.0910,0.1613,0.3020",\ +"-0.0105,0.0012,0.0129,0.0363,0.0793,0.1535,0.2902",\ +"-0.0262,-0.0145,-0.0027,0.0246,0.0637,0.1379,0.2785",\ +"-0.0535,-0.0418,-0.0262,0.0012,0.0363,0.1105,0.2512",\ +"-0.0926,-0.0809,-0.0652,-0.0418,-0.0027,0.0715,0.2121",\ +"-0.1668,-0.1551,-0.1395,-0.1082,-0.0770,-0.0027,0.1379",\ +"-0.3035,-0.2918,-0.2762,-0.2488,-0.2137,-0.1434,-0.0027"); + } + + fall_constraint("SIG2SRAM_constraint_template") { + index_1("0.0040,0.0176,0.0344,0.0656,0.1120,0.2016,0.3800"); + index_2("0.0040,0.0176,0.0344,0.0656,0.1120,0.2016,0.3800"); + values ("0.0832,0.0949,0.1105,0.1379,0.1730,0.2473,0.3801",\ +"0.0754,0.0832,0.0988,0.1223,0.1613,0.2355,0.3684",\ +"0.0598,0.0676,0.0832,0.1066,0.1457,0.2121,0.3527",\ +"0.0324,0.0441,0.0598,0.0871,0.1223,0.1926,0.3293",\ +"-0.0066,0.0051,0.0168,0.0480,0.0832,0.1535,0.2902",\ +"-0.0809,-0.0691,-0.0574,-0.0301,0.0090,0.0832,0.2121",\ +"-0.2176,-0.2059,-0.1941,-0.1668,-0.1277,-0.0574,0.0793"); + } + } + + + timing() { + timing_type : hold_rising; + related_pin : "B_CLK"; + when : "B_MEN" + sdf_cond : "B_MEN" + + rise_constraint("SIG2SRAM_constraint_template") { + index_1("0.0040,0.0176,0.0344,0.0656,0.1120,0.2016,0.3800"); + index_2("0.0040,0.0176,0.0344,0.0656,0.1120,0.2016,0.3800"); + values ("0.1887,0.1770,0.1613,0.1340,0.0949,0.0207,-0.1160",\ +"0.1965,0.1848,0.1730,0.1457,0.1027,0.0324,-0.1082",\ +"0.2160,0.2004,0.1887,0.1613,0.1184,0.0480,-0.0926",\ +"0.2395,0.2277,0.2121,0.1848,0.1457,0.0715,-0.0652",\ +"0.2785,0.2668,0.2512,0.2238,0.1848,0.1105,-0.0262",\ +"0.3527,0.3410,0.3254,0.2980,0.2551,0.1848,0.0480",\ +"0.4934,0.4816,0.4660,0.4387,0.3957,0.3254,0.1887"); + } + + fall_constraint("SIG2SRAM_constraint_template") { + index_1("0.0040,0.0176,0.0344,0.0656,0.1120,0.2016,0.3800"); + index_2("0.0040,0.0176,0.0344,0.0656,0.1120,0.2016,0.3800"); + values ("0.1730,0.1613,0.1496,0.1184,0.0793,0.0129,-0.1238",\ +"0.1848,0.1730,0.1574,0.1301,0.0910,0.0207,-0.1121",\ +"0.2004,0.1887,0.1730,0.1457,0.1066,0.0363,-0.1004",\ +"0.2238,0.2121,0.2004,0.1691,0.1340,0.0598,-0.0730",\ +"0.2629,0.2512,0.2395,0.2121,0.1691,0.0988,-0.0340",\ +"0.3371,0.3254,0.3137,0.2863,0.2434,0.1730,0.0402",\ +"0.4777,0.4660,0.4504,0.4230,0.3840,0.3137,0.1809"); + } + } + } +pin(B_MEN) { + direction : input ; + capacitance : 0.00326046 ; + max_transition : "0.38" ; + related_power_pin : VDD; + related_ground_pin : VSS; + internal_power() { + rise_power("scalar"){ + values (0.2886); + } + fall_power("scalar"){ + values (0.4759); + } + } + timing() { + timing_type : setup_rising; + related_pin : "B_CLK"; + + rise_constraint("SIG2SRAM_constraint_template") { + index_1("0.0040,0.0176,0.0344,0.0656,0.1120,0.2016,0.3800"); + index_2("0.0040,0.0176,0.0344,0.0656,0.1120,0.2016,0.3800"); + values ("0.1418,0.1496,0.1652,0.1926,0.2316,0.3059,0.4465",\ +"0.1301,0.1379,0.1535,0.1809,0.2199,0.2941,0.4348",\ +"0.1145,0.1262,0.1418,0.1652,0.2043,0.2785,0.4191",\ +"0.0871,0.0949,0.1105,0.1379,0.1770,0.2512,0.3879",\ +"0.0480,0.0598,0.0754,0.0988,0.1379,0.2082,0.3488",\ +"-0.0262,-0.0145,0.0012,0.0285,0.0676,0.1379,0.2785",\ +"-0.1668,-0.1551,-0.1395,-0.1121,-0.0730,0.0012,0.1379"); + } + + fall_constraint("SIG2SRAM_constraint_template") { + index_1("0.0040,0.0176,0.0344,0.0656,0.1120,0.2016,0.3800"); + index_2("0.0040,0.0176,0.0344,0.0656,0.1120,0.2016,0.3800"); + values ("0.2082,0.2199,0.2316,0.2590,0.2980,0.3723,0.5051",\ +"0.1965,0.2082,0.2199,0.2473,0.2863,0.3605,0.4934",\ +"0.1809,0.1926,0.2043,0.2316,0.2707,0.3449,0.4777",\ +"0.1574,0.1691,0.1809,0.2082,0.2434,0.3176,0.4543",\ +"0.1145,0.1262,0.1418,0.1691,0.2043,0.2785,0.4113",\ +"0.0441,0.0559,0.0676,0.0949,0.1301,0.2004,0.3332",\ +"-0.0965,-0.0848,-0.0691,-0.0418,-0.0066,0.0676,0.2004"); + } + } + + + timing() { + timing_type : hold_rising; + related_pin : "B_CLK"; + + rise_constraint("SIG2SRAM_constraint_template") { + index_1("0.0040,0.0176,0.0344,0.0656,0.1120,0.2016,0.3800"); + index_2("0.0040,0.0176,0.0344,0.0656,0.1120,0.2016,0.3800"); + values ("0.1770,0.1652,0.1535,0.1262,0.0832,0.0129,-0.1277",\ +"0.1887,0.1770,0.1613,0.1340,0.0949,0.0207,-0.1199",\ +"0.2043,0.1926,0.1770,0.1496,0.1105,0.0363,-0.1043",\ +"0.2277,0.2160,0.2043,0.1770,0.1379,0.0598,-0.0770",\ +"0.2668,0.2551,0.2434,0.2160,0.1730,0.0988,-0.0379",\ +"0.3449,0.3332,0.3176,0.2902,0.2473,0.1730,0.0363",\ +"0.4816,0.4699,0.4543,0.4270,0.3840,0.3098,0.1770"); + } + + fall_constraint("SIG2SRAM_constraint_template") { + index_1("0.0040,0.0176,0.0344,0.0656,0.1120,0.2016,0.3800"); + index_2("0.0040,0.0176,0.0344,0.0656,0.1120,0.2016,0.3800"); + values ("0.1613,0.1496,0.1379,0.1105,0.0715,0.0012,-0.1355",\ +"0.1730,0.1613,0.1496,0.1184,0.0832,0.0129,-0.1238",\ +"0.1887,0.1770,0.1652,0.1340,0.0988,0.0285,-0.1121",\ +"0.2121,0.2043,0.1887,0.1613,0.1223,0.0520,-0.0848",\ +"0.2551,0.2434,0.2277,0.2004,0.1613,0.0910,-0.0418",\ +"0.3293,0.3176,0.3020,0.2746,0.2395,0.1652,0.0324",\ +"0.4660,0.4543,0.4426,0.4113,0.3762,0.3020,0.1691"); + } + } + } +bus(B_BM) { + bus_type : D_31_0; + direction : input ; + capacitance : 0.00334781 ; + max_transition : "0.38" ; + pin(B_BM[31:0]) { + related_power_pin : VDD; + related_ground_pin : VSS; + internal_power() { + when : "B_MEN"; + rise_power("scalar"){ + values (0.1512); + } + fall_power("scalar"){ + values (0.1660); + } + } + internal_power() { + when : "!B_MEN"; + rise_power("scalar"){ + values (0.1918); + } + fall_power("scalar"){ + values (0.1601); + } + } + } + timing() { + timing_type : setup_rising; + related_pin : "B_CLK"; + when : "(B_WEN & B_MEN)" + sdf_cond : "B_RW_ACCESS" + + rise_constraint("SIG2SRAM_constraint_template") { + index_1("0.0040,0.0176,0.0344,0.0656,0.1120,0.2016,0.3800"); + index_2("0.0040,0.0176,0.0344,0.0656,0.1120,0.2016,0.3800"); + values ("-0.2899,-0.2791,-0.2635,-0.2381,-0.1971,-0.1238,0.0109",\ +"-0.2937,-0.2830,-0.2674,-0.2420,-0.2010,-0.1277,0.0070",\ +"-0.2975,-0.2868,-0.2712,-0.2458,-0.2048,-0.1315,0.0032",\ +"-0.3008,-0.2901,-0.2744,-0.2490,-0.2080,-0.1348,-0.0000",\ +"-0.3132,-0.3025,-0.2869,-0.2615,-0.2205,-0.1472,-0.0125",\ +"-0.3307,-0.3200,-0.3043,-0.2789,-0.2379,-0.1647,-0.0299",\ +"-0.3584,-0.3476,-0.3320,-0.3066,-0.2656,-0.1923,-0.0576"); + } + + fall_constraint("SIG2SRAM_constraint_template") { + index_1("0.0040,0.0176,0.0344,0.0656,0.1120,0.2016,0.3800"); + index_2("0.0040,0.0176,0.0344,0.0656,0.1120,0.2016,0.3800"); + values ("-0.2664,-0.2547,-0.2420,-0.2147,-0.1776,-0.1043,0.0236",\ +"-0.2703,-0.2586,-0.2459,-0.2185,-0.1814,-0.1082,0.0197",\ +"-0.2741,-0.2624,-0.2497,-0.2223,-0.1852,-0.1120,0.0159",\ +"-0.2774,-0.2656,-0.2529,-0.2256,-0.1885,-0.1152,0.0127",\ +"-0.2898,-0.2781,-0.2654,-0.2380,-0.2009,-0.1277,0.0002",\ +"-0.3073,-0.2955,-0.2828,-0.2555,-0.2184,-0.1452,-0.0172",\ +"-0.3349,-0.3232,-0.3105,-0.2832,-0.2461,-0.1728,-0.0449"); + } + } + + + timing() { + timing_type : hold_rising; + related_pin : "B_CLK"; + when : "(B_WEN & B_MEN)" + sdf_cond : "B_RW_ACCESS" + + rise_constraint("SIG2SRAM_constraint_template") { + index_1("0.0040,0.0176,0.0344,0.0656,0.1120,0.2016,0.3800"); + index_2("0.0040,0.0176,0.0344,0.0656,0.1120,0.2016,0.3800"); + values ("0.3958,0.3861,0.3705,0.3441,0.3070,0.2328,0.0980",\ +"0.3997,0.3900,0.3743,0.3480,0.3109,0.2366,0.1019",\ +"0.4035,0.3938,0.3781,0.3518,0.3147,0.2404,0.1057",\ +"0.4068,0.3970,0.3814,0.3550,0.3179,0.2437,0.1089",\ +"0.4192,0.4095,0.3938,0.3675,0.3304,0.2561,0.1214",\ +"0.4367,0.4269,0.4113,0.3849,0.3478,0.2736,0.1388",\ +"0.4643,0.4546,0.4389,0.4126,0.3755,0.3013,0.1665"); + } + + fall_constraint("SIG2SRAM_constraint_template") { + index_1("0.0040,0.0176,0.0344,0.0656,0.1120,0.2016,0.3800"); + index_2("0.0040,0.0176,0.0344,0.0656,0.1120,0.2016,0.3800"); + values ("0.3675,0.3568,0.3431,0.3158,0.2796,0.2074,0.0775",\ +"0.3714,0.3607,0.3470,0.3196,0.2835,0.2113,0.0814",\ +"0.3752,0.3645,0.3508,0.3234,0.2873,0.2150,0.0852",\ +"0.3785,0.3677,0.3540,0.3267,0.2906,0.2183,0.0884",\ +"0.3909,0.3802,0.3665,0.3391,0.3030,0.2307,0.1009",\ +"0.4084,0.3976,0.3839,0.3566,0.3205,0.2482,0.1183",\ +"0.4360,0.4253,0.4116,0.3843,0.3481,0.2759,0.1460"); + } + } +} + pin(B_CLK) { + direction : input; + capacitance : 0.00389386; + max_transition : "0.38"; + clock : "true" ; + pin_func_type : active_rising ; + + timing () { + timing_type : "min_pulse_width"; + related_pin : "B_CLK"; + rise_constraint("CLKTRAN_constraint_template") { + index_1("0.004,0.38"); + values("0.12,0.12"); + } + } + + related_power_pin : VDD; + related_ground_pin : VSS; + + internal_power() { + when : "!B_MEN & !B_WEN & !B_REN"; + rise_power("scalar"){ + values (0); + } + fall_power("scalar"){ + values (0); + } + } + internal_power() { + when : "!B_MEN & B_WEN & !B_REN"; + rise_power("scalar"){ + values (0.7228); + } + fall_power("scalar"){ + values (0); + } + } + internal_power() { + when : "B_MEN & B_WEN & !B_REN"; + rise_power("scalar"){ + values (73.7434); + } + fall_power("scalar"){ + values (0); + } + } + internal_power() { + when : "B_MEN & B_WEN & B_REN"; + rise_power("scalar"){ + values (76.2622); + } + fall_power("scalar"){ + values (0); + } + } + internal_power() { + when : "B_MEN & !B_WEN & B_REN"; + rise_power("scalar"){ + values (61.9692); + } + fall_power("scalar"){ + values (0); + } + } + internal_power() { + when : "!B_MEN & !B_WEN & B_REN"; + rise_power("scalar"){ + values (0.4287); + } + fall_power("scalar"){ + values (0); + } + } + internal_power() { + when : "!B_MEN & B_WEN & B_REN"; + rise_power("scalar"){ + values (1.4323); + } + fall_power("scalar"){ + values (0); + } + } + internal_power() { + when : "B_MEN & !B_WEN & !B_REN"; + rise_power("scalar"){ + values (0); + } + fall_power("scalar"){ + values (0); + } + } + } + bus(B_DIN) { + bus_type : D_31_0; + direction : input ; + capacitance : 0.00468868 ; + memory_write() { + address : B_ADDR ; + clocked_on : B_CLK; + } + + max_transition : "0.38" ; + pin(B_DIN[31:0]) { + related_power_pin : VDD; + related_ground_pin : VSS; + internal_power() { + when : "B_MEN"; + rise_power("scalar"){ + values (0.1512); + } + fall_power("scalar"){ + values (0.1660); + } + } + internal_power() { + when : "!B_MEN"; + rise_power("scalar"){ + values (0.1918); + } + fall_power("scalar"){ + values (0.1601); + } + } + } + timing() { + timing_type : setup_rising; + related_pin : "B_CLK"; + when : "(B_WEN & B_MEN)"; + sdf_cond : "B_W_ACCESS"; + + rise_constraint("SIG2SRAM_constraint_template") { + index_1("0.0040,0.0176,0.0344,0.0656,0.1120,0.2016,0.3800"); + index_2("0.0040,0.0176,0.0344,0.0656,0.1120,0.2016,0.3800"); + values ("-0.2899,-0.2791,-0.2635,-0.2381,-0.1971,-0.1238,0.0109",\ +"-0.2937,-0.2830,-0.2674,-0.2420,-0.2010,-0.1277,0.0070",\ +"-0.2975,-0.2868,-0.2712,-0.2458,-0.2048,-0.1315,0.0032",\ +"-0.3008,-0.2901,-0.2744,-0.2490,-0.2080,-0.1348,-0.0000",\ +"-0.3132,-0.3025,-0.2869,-0.2615,-0.2205,-0.1472,-0.0125",\ +"-0.3307,-0.3200,-0.3043,-0.2789,-0.2379,-0.1647,-0.0299",\ +"-0.3584,-0.3476,-0.3320,-0.3066,-0.2656,-0.1923,-0.0576"); + } + + fall_constraint("SIG2SRAM_constraint_template") { + index_1("0.0040,0.0176,0.0344,0.0656,0.1120,0.2016,0.3800"); + index_2("0.0040,0.0176,0.0344,0.0656,0.1120,0.2016,0.3800"); + values ("-0.2664,-0.2547,-0.2420,-0.2147,-0.1776,-0.1043,0.0236",\ +"-0.2703,-0.2586,-0.2459,-0.2185,-0.1814,-0.1082,0.0197",\ +"-0.2741,-0.2624,-0.2497,-0.2223,-0.1852,-0.1120,0.0159",\ +"-0.2774,-0.2656,-0.2529,-0.2256,-0.1885,-0.1152,0.0127",\ +"-0.2898,-0.2781,-0.2654,-0.2380,-0.2009,-0.1277,0.0002",\ +"-0.3073,-0.2955,-0.2828,-0.2555,-0.2184,-0.1452,-0.0172",\ +"-0.3349,-0.3232,-0.3105,-0.2832,-0.2461,-0.1728,-0.0449"); + } + } + + timing() { + timing_type : hold_rising; + related_pin : "B_CLK"; + when : "(B_WEN & B_MEN)"; + sdf_cond : "B_W_ACCESS"; + + rise_constraint("SIG2SRAM_constraint_template") { + index_1("0.0040,0.0176,0.0344,0.0656,0.1120,0.2016,0.3800"); + index_2("0.0040,0.0176,0.0344,0.0656,0.1120,0.2016,0.3800"); + values ("0.3958,0.3861,0.3705,0.3441,0.3070,0.2328,0.0980",\ +"0.3997,0.3900,0.3743,0.3480,0.3109,0.2366,0.1019",\ +"0.4035,0.3938,0.3781,0.3518,0.3147,0.2404,0.1057",\ +"0.4068,0.3970,0.3814,0.3550,0.3179,0.2437,0.1089",\ +"0.4192,0.4095,0.3938,0.3675,0.3304,0.2561,0.1214",\ +"0.4367,0.4269,0.4113,0.3849,0.3478,0.2736,0.1388",\ +"0.4643,0.4546,0.4389,0.4126,0.3755,0.3013,0.1665"); + } + + fall_constraint("SIG2SRAM_constraint_template") { + index_1("0.0040,0.0176,0.0344,0.0656,0.1120,0.2016,0.3800"); + index_2("0.0040,0.0176,0.0344,0.0656,0.1120,0.2016,0.3800"); + values ("0.3675,0.3568,0.3431,0.3158,0.2796,0.2074,0.0775",\ +"0.3714,0.3607,0.3470,0.3196,0.2835,0.2113,0.0814",\ +"0.3752,0.3645,0.3508,0.3234,0.2873,0.2150,0.0852",\ +"0.3785,0.3677,0.3540,0.3267,0.2906,0.2183,0.0884",\ +"0.3909,0.3802,0.3665,0.3391,0.3030,0.2307,0.1009",\ +"0.4084,0.3976,0.3839,0.3566,0.3205,0.2482,0.1183",\ +"0.4360,0.4253,0.4116,0.3843,0.3481,0.2759,0.1460"); + } + } + } + + pin(B_BIST_EN) { + direction : input ; + capacitance : 0.00421562 ; + max_transition : "1" ; + related_power_pin : VDD; + related_ground_pin : VSS; + internal_power() { + rise_power("scalar") { + values (0); + } + fall_power("scalar") { + values (0); + } + } + } + +bus(B_BIST_ADDR) { + bus_type : A_9_0; + direction : input ; + capacitance : 0.0115194 ; + pin(B_BIST_ADDR[0]) { + capacitance : 0.0056487 ; + } + pin(B_BIST_ADDR[1]) { + capacitance : 0.00741688 ; + } + pin(B_BIST_ADDR[2]) { + capacitance : 0.0100613 ; + } + pin(B_BIST_ADDR[3]) { + capacitance : 0.00667339 ; + } + pin(B_BIST_ADDR[4]) { + capacitance : 0.00620204 ; + } + pin(B_BIST_ADDR[5]) { + capacitance : 0.0101975 ; + } + pin(B_BIST_ADDR[6]) { + capacitance : 0.0124055 ; + } + pin(B_BIST_ADDR[7]) { + capacitance : 0.0101065 ; + } + pin(B_BIST_ADDR[8]) { + capacitance : 0.00887215 ; + } + max_transition : "0.38" ; + pin(B_BIST_ADDR[9:0]) { + related_power_pin : VDD; + related_ground_pin : VSS; + internal_power() { + when : "B_BIST_MEN"; + rise_power("scalar"){ + values (0.4735); + } + fall_power("scalar"){ + values (0.6259); + } + } + internal_power() { + when : "!B_BIST_MEN"; + rise_power("scalar"){ + values (0.0322); + } + fall_power("scalar"){ + values (0.0023); + } + } + } + timing() { + timing_type : setup_rising; + related_pin : "B_BIST_CLK"; + when : "((B_BIST_WEN | B_BIST_REN)& B_BIST_MEN)" + sdf_cond : "B_BIST_RW_ACCESS" + + rise_constraint("SIG2SRAM_constraint_template") { + index_1("0.0040,0.0176,0.0344,0.0656,0.1120,0.2016,0.3800"); + index_2("0.0040,0.0176,0.0344,0.0656,0.1120,0.2016,0.3800"); + values ("-0.2371,-0.2215,-0.2098,-0.1824,-0.1434,-0.0691,0.0676",\ +"-0.2449,-0.2332,-0.2176,-0.1902,-0.1551,-0.0770,0.0559",\ +"-0.2605,-0.2488,-0.2332,-0.2059,-0.1707,-0.0965,0.0441",\ +"-0.2879,-0.2723,-0.2605,-0.2332,-0.1941,-0.1199,0.0168",\ +"-0.3230,-0.3113,-0.2996,-0.2723,-0.2332,-0.1590,-0.0184",\ +"-0.4012,-0.3895,-0.3738,-0.3465,-0.3074,-0.2332,-0.0965",\ +"-0.5379,-0.5262,-0.5105,-0.4832,-0.4480,-0.3699,-0.2332"); + } + + fall_constraint("SIG2SRAM_constraint_template") { + index_1("0.0040,0.0176,0.0344,0.0656,0.1120,0.2016,0.3800"); + index_2("0.0040,0.0176,0.0344,0.0656,0.1120,0.2016,0.3800"); + values ("-0.1785,-0.1707,-0.1551,-0.1277,-0.0887,-0.0184,0.1145",\ +"-0.1902,-0.1785,-0.1629,-0.1355,-0.1004,-0.0262,0.1027",\ +"-0.2059,-0.1941,-0.1785,-0.1512,-0.1160,-0.0418,0.0871",\ +"-0.2293,-0.2176,-0.2059,-0.1785,-0.1434,-0.0691,0.0598",\ +"-0.2684,-0.2566,-0.2449,-0.2176,-0.1824,-0.1082,0.0207",\ +"-0.3465,-0.3348,-0.3191,-0.2918,-0.2566,-0.1824,-0.0535",\ +"-0.4832,-0.4715,-0.4559,-0.4324,-0.3934,-0.3191,-0.1902"); + } + } + + + timing() { + timing_type : hold_rising; + related_pin : "B_BIST_CLK"; + when : "((B_BIST_WEN | B_BIST_REN)& B_BIST_MEN)" + sdf_cond : "B_BIST_RW_ACCESS" + + rise_constraint("SIG2SRAM_constraint_template") { + index_1("0.0040,0.0176,0.0344,0.0656,0.1120,0.2016,0.3800"); + index_2("0.0040,0.0176,0.0344,0.0656,0.1120,0.2016,0.3800"); + values ("0.3410,0.3293,0.3137,0.2863,0.2473,0.1730,0.0324",\ +"0.3488,0.3371,0.3215,0.2941,0.2590,0.1809,0.0480",\ +"0.3684,0.3527,0.3371,0.3098,0.2746,0.1965,0.0598",\ +"0.3918,0.3762,0.3645,0.3371,0.2980,0.2238,0.0871",\ +"0.4309,0.4152,0.4035,0.3762,0.3371,0.2629,0.1223",\ +"0.5051,0.4934,0.4777,0.4504,0.4113,0.3371,0.1965",\ +"0.6418,0.6262,0.6145,0.5871,0.5520,0.4738,0.3332"); + } + + fall_constraint("SIG2SRAM_constraint_template") { + index_1("0.0040,0.0176,0.0344,0.0656,0.1120,0.2016,0.3800"); + index_2("0.0040,0.0176,0.0344,0.0656,0.1120,0.2016,0.3800"); + values ("0.2824,0.2707,0.2551,0.2277,0.1926,0.1184,-0.0105",\ +"0.2902,0.2785,0.2668,0.2395,0.2043,0.1301,0.0012",\ +"0.3059,0.2941,0.2824,0.2551,0.2199,0.1457,0.0168",\ +"0.3332,0.3215,0.3059,0.2785,0.2434,0.1691,0.0402",\ +"0.3723,0.3605,0.3449,0.3176,0.2824,0.2121,0.0793",\ +"0.4465,0.4348,0.4230,0.3918,0.3566,0.2824,0.1535",\ +"0.5832,0.5715,0.5598,0.5324,0.4934,0.4191,0.2902"); + } + } +} +pin(B_BIST_WEN) { + direction : input ; + capacitance : 0.00341384 ; + max_transition : "0.38" ; + related_power_pin : VDD; + related_ground_pin : VSS; + internal_power() { + when : "B_BIST_MEN"; + rise_power("scalar"){ + values (0.9384); + } + fall_power("scalar"){ + values (0.0212); + } + } + internal_power() { + when : "!B_BIST_MEN"; + rise_power("scalar"){ + values (0.0069); + } + fall_power("scalar"){ + values (0.0124); + } + } + timing() { + timing_type : setup_rising; + related_pin : "B_BIST_CLK"; + when : "B_BIST_MEN" + sdf_cond : "B_BIST_MEN" + + rise_constraint("SIG2SRAM_constraint_template") { + index_1("0.0040,0.0176,0.0344,0.0656,0.1120,0.2016,0.3800"); + index_2("0.0040,0.0176,0.0344,0.0656,0.1120,0.2016,0.3800"); + values ("0.1418,0.1496,0.1652,0.1887,0.2316,0.3059,0.4465",\ +"0.1301,0.1379,0.1535,0.1809,0.2199,0.2941,0.4348",\ +"0.1145,0.1262,0.1379,0.1652,0.2043,0.2785,0.4191",\ +"0.0871,0.0949,0.1105,0.1379,0.1770,0.2512,0.3879",\ +"0.0480,0.0598,0.0754,0.0988,0.1379,0.2082,0.3527",\ +"-0.0262,-0.0145,0.0012,0.0246,0.0676,0.1379,0.2785",\ +"-0.1668,-0.1551,-0.1395,-0.1121,-0.0730,0.0012,0.1418"); + } + + fall_constraint("SIG2SRAM_constraint_template") { + index_1("0.0040,0.0176,0.0344,0.0656,0.1120,0.2016,0.3800"); + index_2("0.0040,0.0176,0.0344,0.0656,0.1120,0.2016,0.3800"); + values ("0.2082,0.2160,0.2316,0.2590,0.2941,0.3684,0.5012",\ +"0.1926,0.2043,0.2199,0.2473,0.2824,0.3566,0.4895",\ +"0.1770,0.1887,0.2043,0.2316,0.2668,0.3410,0.4777",\ +"0.1535,0.1652,0.1770,0.2043,0.2395,0.3137,0.4504",\ +"0.1145,0.1262,0.1379,0.1652,0.2043,0.2746,0.4113",\ +"0.0402,0.0520,0.0676,0.0910,0.1262,0.2004,0.3332",\ +"-0.0965,-0.0848,-0.0730,-0.0457,-0.0066,0.0637,0.2004"); + } + } + + + timing() { + timing_type : hold_rising; + related_pin : "B_BIST_CLK"; + when : "B_BIST_MEN" + sdf_cond : "B_BIST_MEN" + + rise_constraint("SIG2SRAM_constraint_template") { + index_1("0.0040,0.0176,0.0344,0.0656,0.1120,0.2016,0.3800"); + index_2("0.0040,0.0176,0.0344,0.0656,0.1120,0.2016,0.3800"); + values ("0.1770,0.1652,0.1496,0.1223,0.0793,0.0090,-0.1316",\ +"0.1848,0.1730,0.1574,0.1301,0.0910,0.0168,-0.1199",\ +"0.2004,0.1887,0.1770,0.1496,0.1066,0.0363,-0.1043",\ +"0.2277,0.2160,0.2004,0.1730,0.1340,0.0598,-0.0809",\ +"0.2668,0.2551,0.2395,0.2121,0.1730,0.0988,-0.0418",\ +"0.3410,0.3293,0.3137,0.2863,0.2434,0.1730,0.0324",\ +"0.4816,0.4699,0.4543,0.4230,0.3801,0.3098,0.1730"); + } + + fall_constraint("SIG2SRAM_constraint_template") { + index_1("0.0040,0.0176,0.0344,0.0656,0.1120,0.2016,0.3800"); + index_2("0.0040,0.0176,0.0344,0.0656,0.1120,0.2016,0.3800"); + values ("0.1613,0.1496,0.1379,0.1066,0.0715,0.0012,-0.1355",\ +"0.1730,0.1613,0.1457,0.1184,0.0832,0.0129,-0.1238",\ +"0.1887,0.1770,0.1613,0.1340,0.0988,0.0246,-0.1121",\ +"0.2121,0.2043,0.1887,0.1613,0.1223,0.0520,-0.0848",\ +"0.2512,0.2434,0.2277,0.2004,0.1613,0.0910,-0.0457",\ +"0.3254,0.3176,0.3020,0.2746,0.2355,0.1652,0.0324",\ +"0.4660,0.4543,0.4387,0.4113,0.3723,0.3020,0.1691"); + } + } + } +pin(B_BIST_REN) { + direction : input ; + capacitance : 0.00390661 ; + max_transition : "0.38" ; + related_power_pin : VDD; + related_ground_pin : VSS; + internal_power() { + when : "B_BIST_MEN"; + rise_power("scalar"){ + values (0.0154); + } + fall_power("scalar"){ + values (0.0113); + } + } + internal_power() { + when : "!B_BIST_MEN"; + rise_power("scalar"){ + values (0.0276); + } + fall_power("scalar"){ + values (0.0235); + } + } + timing() { + timing_type : setup_rising; + related_pin : "B_BIST_CLK"; + when : "B_BIST_MEN" + sdf_cond : "B_BIST_MEN" + + rise_constraint("SIG2SRAM_constraint_template") { + index_1("0.0040,0.0176,0.0344,0.0656,0.1120,0.2016,0.3800"); + index_2("0.0040,0.0176,0.0344,0.0656,0.1120,0.2016,0.3800"); + values ("-0.0027,0.0090,0.0246,0.0520,0.0910,0.1613,0.3020",\ +"-0.0105,0.0012,0.0129,0.0363,0.0793,0.1535,0.2902",\ +"-0.0262,-0.0145,-0.0027,0.0246,0.0637,0.1379,0.2785",\ +"-0.0535,-0.0418,-0.0262,0.0012,0.0363,0.1105,0.2512",\ +"-0.0926,-0.0809,-0.0652,-0.0418,-0.0027,0.0715,0.2121",\ +"-0.1668,-0.1551,-0.1395,-0.1082,-0.0770,-0.0027,0.1379",\ +"-0.3035,-0.2918,-0.2762,-0.2488,-0.2137,-0.1434,-0.0027"); + } + + fall_constraint("SIG2SRAM_constraint_template") { + index_1("0.0040,0.0176,0.0344,0.0656,0.1120,0.2016,0.3800"); + index_2("0.0040,0.0176,0.0344,0.0656,0.1120,0.2016,0.3800"); + values ("0.0832,0.0949,0.1105,0.1379,0.1730,0.2473,0.3801",\ +"0.0754,0.0832,0.0988,0.1223,0.1613,0.2355,0.3684",\ +"0.0598,0.0676,0.0832,0.1066,0.1457,0.2121,0.3527",\ +"0.0324,0.0441,0.0598,0.0871,0.1223,0.1926,0.3293",\ +"-0.0066,0.0051,0.0168,0.0480,0.0832,0.1535,0.2902",\ +"-0.0809,-0.0691,-0.0574,-0.0301,0.0090,0.0832,0.2121",\ +"-0.2176,-0.2059,-0.1941,-0.1668,-0.1277,-0.0574,0.0793"); + } + } + + + timing() { + timing_type : hold_rising; + related_pin : "B_BIST_CLK"; + when : "B_BIST_MEN" + sdf_cond : "B_BIST_MEN" + + rise_constraint("SIG2SRAM_constraint_template") { + index_1("0.0040,0.0176,0.0344,0.0656,0.1120,0.2016,0.3800"); + index_2("0.0040,0.0176,0.0344,0.0656,0.1120,0.2016,0.3800"); + values ("0.1887,0.1770,0.1613,0.1340,0.0949,0.0207,-0.1160",\ +"0.1965,0.1848,0.1730,0.1457,0.1027,0.0324,-0.1082",\ +"0.2160,0.2004,0.1887,0.1613,0.1184,0.0480,-0.0926",\ +"0.2395,0.2277,0.2121,0.1848,0.1457,0.0715,-0.0652",\ +"0.2785,0.2668,0.2512,0.2238,0.1848,0.1105,-0.0262",\ +"0.3527,0.3410,0.3254,0.2980,0.2551,0.1848,0.0480",\ +"0.4934,0.4816,0.4660,0.4387,0.3957,0.3254,0.1887"); + } + + fall_constraint("SIG2SRAM_constraint_template") { + index_1("0.0040,0.0176,0.0344,0.0656,0.1120,0.2016,0.3800"); + index_2("0.0040,0.0176,0.0344,0.0656,0.1120,0.2016,0.3800"); + values ("0.1730,0.1613,0.1496,0.1184,0.0793,0.0129,-0.1238",\ +"0.1848,0.1730,0.1574,0.1301,0.0910,0.0207,-0.1121",\ +"0.2004,0.1887,0.1730,0.1457,0.1066,0.0363,-0.1004",\ +"0.2238,0.2121,0.2004,0.1691,0.1340,0.0598,-0.0730",\ +"0.2629,0.2512,0.2395,0.2121,0.1691,0.0988,-0.0340",\ +"0.3371,0.3254,0.3137,0.2863,0.2434,0.1730,0.0402",\ +"0.4777,0.4660,0.4504,0.4230,0.3840,0.3137,0.1809"); + } + } + } +pin(B_BIST_MEN) { + direction : input ; + capacitance : 0.00326046 ; + max_transition : "0.38" ; + related_power_pin : VDD; + related_ground_pin : VSS; + internal_power() { + rise_power("scalar"){ + values (0.2886); + } + fall_power("scalar"){ + values (0.4759); + } + } + timing() { + timing_type : setup_rising; + related_pin : "B_BIST_CLK"; + + rise_constraint("SIG2SRAM_constraint_template") { + index_1("0.0040,0.0176,0.0344,0.0656,0.1120,0.2016,0.3800"); + index_2("0.0040,0.0176,0.0344,0.0656,0.1120,0.2016,0.3800"); + values ("0.1418,0.1496,0.1652,0.1926,0.2316,0.3059,0.4465",\ +"0.1301,0.1379,0.1535,0.1809,0.2199,0.2941,0.4348",\ +"0.1145,0.1262,0.1418,0.1652,0.2043,0.2785,0.4191",\ +"0.0871,0.0949,0.1105,0.1379,0.1770,0.2512,0.3879",\ +"0.0480,0.0598,0.0754,0.0988,0.1379,0.2082,0.3488",\ +"-0.0262,-0.0145,0.0012,0.0285,0.0676,0.1379,0.2785",\ +"-0.1668,-0.1551,-0.1395,-0.1121,-0.0730,0.0012,0.1379"); + } + + fall_constraint("SIG2SRAM_constraint_template") { + index_1("0.0040,0.0176,0.0344,0.0656,0.1120,0.2016,0.3800"); + index_2("0.0040,0.0176,0.0344,0.0656,0.1120,0.2016,0.3800"); + values ("0.2082,0.2199,0.2316,0.2590,0.2980,0.3723,0.5051",\ +"0.1965,0.2082,0.2199,0.2473,0.2863,0.3605,0.4934",\ +"0.1809,0.1926,0.2043,0.2316,0.2707,0.3449,0.4777",\ +"0.1574,0.1691,0.1809,0.2082,0.2434,0.3176,0.4543",\ +"0.1145,0.1262,0.1418,0.1691,0.2043,0.2785,0.4113",\ +"0.0441,0.0559,0.0676,0.0949,0.1301,0.2004,0.3332",\ +"-0.0965,-0.0848,-0.0691,-0.0418,-0.0066,0.0676,0.2004"); + } + } + + + timing() { + timing_type : hold_rising; + related_pin : "B_BIST_CLK"; + + rise_constraint("SIG2SRAM_constraint_template") { + index_1("0.0040,0.0176,0.0344,0.0656,0.1120,0.2016,0.3800"); + index_2("0.0040,0.0176,0.0344,0.0656,0.1120,0.2016,0.3800"); + values ("0.1770,0.1652,0.1535,0.1262,0.0832,0.0129,-0.1277",\ +"0.1887,0.1770,0.1613,0.1340,0.0949,0.0207,-0.1199",\ +"0.2043,0.1926,0.1770,0.1496,0.1105,0.0363,-0.1043",\ +"0.2277,0.2160,0.2043,0.1770,0.1379,0.0598,-0.0770",\ +"0.2668,0.2551,0.2434,0.2160,0.1730,0.0988,-0.0379",\ +"0.3449,0.3332,0.3176,0.2902,0.2473,0.1730,0.0363",\ +"0.4816,0.4699,0.4543,0.4270,0.3840,0.3098,0.1770"); + } + + fall_constraint("SIG2SRAM_constraint_template") { + index_1("0.0040,0.0176,0.0344,0.0656,0.1120,0.2016,0.3800"); + index_2("0.0040,0.0176,0.0344,0.0656,0.1120,0.2016,0.3800"); + values ("0.1613,0.1496,0.1379,0.1105,0.0715,0.0012,-0.1355",\ +"0.1730,0.1613,0.1496,0.1184,0.0832,0.0129,-0.1238",\ +"0.1887,0.1770,0.1652,0.1340,0.0988,0.0285,-0.1121",\ +"0.2121,0.2043,0.1887,0.1613,0.1223,0.0520,-0.0848",\ +"0.2551,0.2434,0.2277,0.2004,0.1613,0.0910,-0.0418",\ +"0.3293,0.3176,0.3020,0.2746,0.2395,0.1652,0.0324",\ +"0.4660,0.4543,0.4426,0.4113,0.3762,0.3020,0.1691"); + } + } + } +bus(B_BIST_BM) { + bus_type : D_31_0; + direction : input ; + capacitance : 0.00290564 ; + max_transition : "0.38" ; + pin(B_BIST_BM[31:0]) { + related_power_pin : VDD; + related_ground_pin : VSS; + internal_power() { + when : "B_BIST_MEN"; + rise_power("scalar"){ + values (0.1512); + } + fall_power("scalar"){ + values (0.1660); + } + } + internal_power() { + when : "!B_BIST_MEN"; + rise_power("scalar"){ + values (0.1918); + } + fall_power("scalar"){ + values (0.1601); + } + } + } + timing() { + timing_type : setup_rising; + related_pin : "B_BIST_CLK"; + when : "(B_BIST_WEN & B_BIST_MEN)" + sdf_cond : "B_BIST_RW_ACCESS" + + rise_constraint("SIG2SRAM_constraint_template") { + index_1("0.0040,0.0176,0.0344,0.0656,0.1120,0.2016,0.3800"); + index_2("0.0040,0.0176,0.0344,0.0656,0.1120,0.2016,0.3800"); + values ("-0.2899,-0.2791,-0.2635,-0.2381,-0.1971,-0.1238,0.0109",\ +"-0.2937,-0.2830,-0.2674,-0.2420,-0.2010,-0.1277,0.0070",\ +"-0.2975,-0.2868,-0.2712,-0.2458,-0.2048,-0.1315,0.0032",\ +"-0.3008,-0.2901,-0.2744,-0.2490,-0.2080,-0.1348,-0.0000",\ +"-0.3132,-0.3025,-0.2869,-0.2615,-0.2205,-0.1472,-0.0125",\ +"-0.3307,-0.3200,-0.3043,-0.2789,-0.2379,-0.1647,-0.0299",\ +"-0.3584,-0.3476,-0.3320,-0.3066,-0.2656,-0.1923,-0.0576"); + } + + fall_constraint("SIG2SRAM_constraint_template") { + index_1("0.0040,0.0176,0.0344,0.0656,0.1120,0.2016,0.3800"); + index_2("0.0040,0.0176,0.0344,0.0656,0.1120,0.2016,0.3800"); + values ("-0.2664,-0.2547,-0.2420,-0.2147,-0.1776,-0.1043,0.0236",\ +"-0.2703,-0.2586,-0.2459,-0.2185,-0.1814,-0.1082,0.0197",\ +"-0.2741,-0.2624,-0.2497,-0.2223,-0.1852,-0.1120,0.0159",\ +"-0.2774,-0.2656,-0.2529,-0.2256,-0.1885,-0.1152,0.0127",\ +"-0.2898,-0.2781,-0.2654,-0.2380,-0.2009,-0.1277,0.0002",\ +"-0.3073,-0.2955,-0.2828,-0.2555,-0.2184,-0.1452,-0.0172",\ +"-0.3349,-0.3232,-0.3105,-0.2832,-0.2461,-0.1728,-0.0449"); + } + } + + + timing() { + timing_type : hold_rising; + related_pin : "B_BIST_CLK"; + when : "(B_BIST_WEN & B_BIST_MEN)" + sdf_cond : "B_BIST_RW_ACCESS" + + rise_constraint("SIG2SRAM_constraint_template") { + index_1("0.0040,0.0176,0.0344,0.0656,0.1120,0.2016,0.3800"); + index_2("0.0040,0.0176,0.0344,0.0656,0.1120,0.2016,0.3800"); + values ("0.3958,0.3861,0.3705,0.3441,0.3070,0.2328,0.0980",\ +"0.3997,0.3900,0.3743,0.3480,0.3109,0.2366,0.1019",\ +"0.4035,0.3938,0.3781,0.3518,0.3147,0.2404,0.1057",\ +"0.4068,0.3970,0.3814,0.3550,0.3179,0.2437,0.1089",\ +"0.4192,0.4095,0.3938,0.3675,0.3304,0.2561,0.1214",\ +"0.4367,0.4269,0.4113,0.3849,0.3478,0.2736,0.1388",\ +"0.4643,0.4546,0.4389,0.4126,0.3755,0.3013,0.1665"); + } + + fall_constraint("SIG2SRAM_constraint_template") { + index_1("0.0040,0.0176,0.0344,0.0656,0.1120,0.2016,0.3800"); + index_2("0.0040,0.0176,0.0344,0.0656,0.1120,0.2016,0.3800"); + values ("0.3675,0.3568,0.3431,0.3158,0.2796,0.2074,0.0775",\ +"0.3714,0.3607,0.3470,0.3196,0.2835,0.2113,0.0814",\ +"0.3752,0.3645,0.3508,0.3234,0.2873,0.2150,0.0852",\ +"0.3785,0.3677,0.3540,0.3267,0.2906,0.2183,0.0884",\ +"0.3909,0.3802,0.3665,0.3391,0.3030,0.2307,0.1009",\ +"0.4084,0.3976,0.3839,0.3566,0.3205,0.2482,0.1183",\ +"0.4360,0.4253,0.4116,0.3843,0.3481,0.2759,0.1460"); + } + } +} + pin(B_BIST_CLK) { + direction : input; + capacitance : 0.00389386; + max_transition : "0.38"; + clock : "true" ; + pin_func_type : active_rising ; + + timing () { + timing_type : "min_pulse_width"; + related_pin : "B_BIST_CLK"; + rise_constraint("CLKTRAN_constraint_template") { + index_1("0.004,0.38"); + values("0.12,0.12"); + } + } + + related_power_pin : VDD; + related_ground_pin : VSS; + + internal_power() { + when : "!B_BIST_MEN & !B_BIST_WEN & !B_BIST_REN"; + rise_power("scalar"){ + values (0); + } + fall_power("scalar"){ + values (0); + } + } + internal_power() { + when : "!B_BIST_MEN & B_BIST_WEN & !B_BIST_REN"; + rise_power("scalar"){ + values (0.7228); + } + fall_power("scalar"){ + values (0); + } + } + internal_power() { + when : "B_BIST_MEN & B_BIST_WEN & !B_BIST_REN"; + rise_power("scalar"){ + values (73.7434); + } + fall_power("scalar"){ + values (0); + } + } + internal_power() { + when : "B_BIST_MEN & B_BIST_WEN & B_BIST_REN"; + rise_power("scalar"){ + values (76.2622); + } + fall_power("scalar"){ + values (0); + } + } + internal_power() { + when : "B_BIST_MEN & !B_BIST_WEN & B_BIST_REN"; + rise_power("scalar"){ + values (61.9692); + } + fall_power("scalar"){ + values (0); + } + } + internal_power() { + when : "!B_BIST_MEN & !B_BIST_WEN & B_BIST_REN"; + rise_power("scalar"){ + values (0.4287); + } + fall_power("scalar"){ + values (0); + } + } + internal_power() { + when : "!B_BIST_MEN & B_BIST_WEN & B_BIST_REN"; + rise_power("scalar"){ + values (1.4323); + } + fall_power("scalar"){ + values (0); + } + } + internal_power() { + when : "B_BIST_MEN & !B_BIST_WEN & !B_BIST_REN"; + rise_power("scalar"){ + values (0); + } + fall_power("scalar"){ + values (0); + } + } + } + bus(B_BIST_DIN) { + bus_type : D_31_0; + direction : input ; + capacitance : 0.00417898 ; + memory_write() { + address : B_BIST_ADDR ; + clocked_on : B_BIST_CLK; + } + + max_transition : "0.38" ; + pin(B_BIST_DIN[31:0]) { + related_power_pin : VDD; + related_ground_pin : VSS; + internal_power() { + when : "B_BIST_MEN"; + rise_power("scalar"){ + values (0.1512); + } + fall_power("scalar"){ + values (0.1660); + } + } + internal_power() { + when : "!B_BIST_MEN"; + rise_power("scalar"){ + values (0.1918); + } + fall_power("scalar"){ + values (0.1601); + } + } + } + timing() { + timing_type : setup_rising; + related_pin : "B_BIST_CLK"; + when : "(B_BIST_WEN & B_BIST_MEN)"; + sdf_cond : "B_BIST_W_ACCESS"; + + rise_constraint("SIG2SRAM_constraint_template") { + index_1("0.0040,0.0176,0.0344,0.0656,0.1120,0.2016,0.3800"); + index_2("0.0040,0.0176,0.0344,0.0656,0.1120,0.2016,0.3800"); + values ("-0.2899,-0.2791,-0.2635,-0.2381,-0.1971,-0.1238,0.0109",\ +"-0.2937,-0.2830,-0.2674,-0.2420,-0.2010,-0.1277,0.0070",\ +"-0.2975,-0.2868,-0.2712,-0.2458,-0.2048,-0.1315,0.0032",\ +"-0.3008,-0.2901,-0.2744,-0.2490,-0.2080,-0.1348,-0.0000",\ +"-0.3132,-0.3025,-0.2869,-0.2615,-0.2205,-0.1472,-0.0125",\ +"-0.3307,-0.3200,-0.3043,-0.2789,-0.2379,-0.1647,-0.0299",\ +"-0.3584,-0.3476,-0.3320,-0.3066,-0.2656,-0.1923,-0.0576"); + } + + fall_constraint("SIG2SRAM_constraint_template") { + index_1("0.0040,0.0176,0.0344,0.0656,0.1120,0.2016,0.3800"); + index_2("0.0040,0.0176,0.0344,0.0656,0.1120,0.2016,0.3800"); + values ("-0.2664,-0.2547,-0.2420,-0.2147,-0.1776,-0.1043,0.0236",\ +"-0.2703,-0.2586,-0.2459,-0.2185,-0.1814,-0.1082,0.0197",\ +"-0.2741,-0.2624,-0.2497,-0.2223,-0.1852,-0.1120,0.0159",\ +"-0.2774,-0.2656,-0.2529,-0.2256,-0.1885,-0.1152,0.0127",\ +"-0.2898,-0.2781,-0.2654,-0.2380,-0.2009,-0.1277,0.0002",\ +"-0.3073,-0.2955,-0.2828,-0.2555,-0.2184,-0.1452,-0.0172",\ +"-0.3349,-0.3232,-0.3105,-0.2832,-0.2461,-0.1728,-0.0449"); + } + } + + timing() { + timing_type : hold_rising; + related_pin : "B_BIST_CLK"; + when : "(B_BIST_WEN & B_BIST_MEN)"; + sdf_cond : "B_BIST_W_ACCESS"; + + rise_constraint("SIG2SRAM_constraint_template") { + index_1("0.0040,0.0176,0.0344,0.0656,0.1120,0.2016,0.3800"); + index_2("0.0040,0.0176,0.0344,0.0656,0.1120,0.2016,0.3800"); + values ("0.3958,0.3861,0.3705,0.3441,0.3070,0.2328,0.0980",\ +"0.3997,0.3900,0.3743,0.3480,0.3109,0.2366,0.1019",\ +"0.4035,0.3938,0.3781,0.3518,0.3147,0.2404,0.1057",\ +"0.4068,0.3970,0.3814,0.3550,0.3179,0.2437,0.1089",\ +"0.4192,0.4095,0.3938,0.3675,0.3304,0.2561,0.1214",\ +"0.4367,0.4269,0.4113,0.3849,0.3478,0.2736,0.1388",\ +"0.4643,0.4546,0.4389,0.4126,0.3755,0.3013,0.1665"); + } + + fall_constraint("SIG2SRAM_constraint_template") { + index_1("0.0040,0.0176,0.0344,0.0656,0.1120,0.2016,0.3800"); + index_2("0.0040,0.0176,0.0344,0.0656,0.1120,0.2016,0.3800"); + values ("0.3675,0.3568,0.3431,0.3158,0.2796,0.2074,0.0775",\ +"0.3714,0.3607,0.3470,0.3196,0.2835,0.2113,0.0814",\ +"0.3752,0.3645,0.3508,0.3234,0.2873,0.2150,0.0852",\ +"0.3785,0.3677,0.3540,0.3267,0.2906,0.2183,0.0884",\ +"0.3909,0.3802,0.3665,0.3391,0.3030,0.2307,0.1009",\ +"0.4084,0.3976,0.3839,0.3566,0.3205,0.2482,0.1183",\ +"0.4360,0.4253,0.4116,0.3843,0.3481,0.2759,0.1460"); + } + } + } + +bus(B_DOUT) { + + bus_type : D_31_0; + direction : output ; + capacitance : 0 ; + max_capacitance : 0.064 ; + memory_read() { + address : B_ADDR ; + } + pin(B_DOUT[31:0]) { + related_power_pin : VDD; + related_ground_pin : VSS; + internal_power() { + rise_power("scalar") { + values (0); + } + fall_power("scalar") { + values (0); + } + } + } + timing() { + related_pin : "B_CLK"; + timing_type : rising_edge ; + timing_sense : non_unate ; + + cell_rise(SIG2SRAM_delay_template) { + index_1("0.0040,0.0176,0.0344,0.0656,0.1120,0.2016,0.3800"); + index_2("0.0008,0.0014,0.0051,0.0100,0.0339,0.0640"); + values ("2.7179,2.7189,2.7237,2.7292,2.7502,2.7737",\ +"2.7251,2.7261,2.7309,2.7365,2.7574,2.7809",\ +"2.7266,2.7276,2.7324,2.7379,2.7588,2.7823",\ +"2.7299,2.7309,2.7358,2.7413,2.7622,2.7857",\ +"2.7428,2.7438,2.7486,2.7541,2.7750,2.7985",\ +"2.7605,2.7615,2.7663,2.7719,2.7928,2.8163",\ +"2.7859,2.7869,2.7917,2.7972,2.8182,2.8417"); + } + cell_fall(SIG2SRAM_delay_template) { + index_1("0.0040,0.0176,0.0344,0.0656,0.1120,0.2016,0.3800"); + index_2("0.0008,0.0014,0.0051,0.0100,0.0339,0.0640"); + values ("2.6836,2.6845,2.6885,2.6931,2.7101,2.7269",\ +"2.6908,2.6917,2.6957,2.7003,2.7174,2.7341",\ +"2.6923,2.6932,2.6972,2.7017,2.7188,2.7356",\ +"2.6956,2.6965,2.7005,2.7051,2.7222,2.7389",\ +"2.7085,2.7093,2.7134,2.7179,2.7350,2.7517",\ +"2.7262,2.7271,2.7311,2.7357,2.7528,2.7695",\ +"2.7516,2.7525,2.7565,2.7611,2.7781,2.7949"); + } + + rise_transition(SRAM_load_template) { + index_1("0.0008,0.0014,0.0051,0.0100,0.0339,0.0640"); + values ("0.0206,0.0210,0.0265,0.0323,0.0606,0.0955"); + } + fall_transition(SRAM_load_template) { + index_1("0.0008,0.0014,0.0051,0.0100,0.0339,0.0640"); + values ("0.0170,0.0177,0.0222,0.0270,0.0451,0.0644"); + } + } +} +cell_leakage_power : 1806.8275; +} +} diff --git a/flow/platforms/ihp-sg13g2/lib/RM_IHPSG13_2P_1024x32_c2_bm_bist_slow_1p08V_125C.lib b/flow/platforms/ihp-sg13g2/lib/RM_IHPSG13_2P_1024x32_c2_bm_bist_slow_1p08V_125C.lib new file mode 100644 index 0000000000..88af471446 --- /dev/null +++ b/flow/platforms/ihp-sg13g2/lib/RM_IHPSG13_2P_1024x32_c2_bm_bist_slow_1p08V_125C.lib @@ -0,0 +1,2898 @@ +/* ------------------------------------------------------*/ +/**/ +/* Copyright 2025 IHP PDK Authors*/ +/**/ +/* Licensed under the Apache License, Version 2.0 (the "License");*/ +/* you may not use this file except in compliance with the License.*/ +/* You may obtain a copy of the License at*/ +/* */ +/* https://www.apache.org/licenses/LICENSE-2.0*/ +/* */ +/* Unless required by applicable law or agreed to in writing, software*/ +/* distributed under the License is distributed on an "AS IS" BASIS,*/ +/* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.*/ +/* See the License for the specific language governing permissions and*/ +/* limitations under the License.*/ +/* */ +/* Generated on Wed Aug 27 13:08:54 2025 */ +/* */ +/* ------------------------------------------------------ */ +library(RM_IHPSG13_2P_1024x32_c2_bm_bist_slow_1p08V_125C) { + technology (cmos) ; + delay_model : table_lookup ; + define ("add_pg_pin_to_lib", "library", "boolean"); + add_pg_pin_to_lib : true; + voltage_map ( VDD, 1.08); + voltage_map ( VDDARRAY, 1.08); + voltage_map ( VSS, 0.000000 ); + + date : "Wed Aug 27 13:08:53 2025" ; + comment : "IHP Microelectronics GmbH, 2023" ; + revision : 1.0.0 ; + simulation : true ; + nom_process : 1 ; + nom_temperature : 125 ; + nom_voltage : 1.08 ; + + operating_conditions("slow_1p08V_125C"){ + process : 1 ; + temperature : 125 ; + voltage : 1.08 ; + tree_type : "balanced_tree" ; + } + + default_operating_conditions : slow_1p08V_125C ; + default_max_transition : 1.0 ; + default_fanout_load : 1.0 ; + default_inout_pin_cap : 0.0 ; + default_input_pin_cap : 0.0 ; + default_output_pin_cap : 0.0 ; + default_cell_leakage_power : 0.0 ; + default_leakage_power_density : 0.0 ; + + slew_lower_threshold_pct_rise : 30 ; + slew_upper_threshold_pct_rise : 70 ; + input_threshold_pct_fall : 50 ; + output_threshold_pct_fall : 50 ; + input_threshold_pct_rise : 50 ; + output_threshold_pct_rise : 50 ; + slew_lower_threshold_pct_fall : 30 ; + slew_upper_threshold_pct_fall : 70 ; + slew_derate_from_library : 0.5; + k_volt_cell_leakage_power : 0.0 ; + k_temp_cell_leakage_power : 0.0 ; + k_process_cell_leakage_power : 0.0 ; + k_volt_internal_power : 0.0 ; + k_temp_internal_power : 0.0 ; + k_process_internal_power : 0.0 ; + + capacitive_load_unit (1,pf) ; + voltage_unit : "1V" ; + current_unit : "1uA" ; + time_unit : "1ns" ; + leakage_power_unit : "1nW" ; + pulling_resistance_unit : "1kohm"; + /* + ------------------------------------------------------------------------------------------ + implicit units overview: + cell_area unit : "um" + internal_power unit : "1e-12 * J/toggle = 1 * uW/MHz" + (capacitive_load_unit * voltage_unit^2) per toggle event + ------------------------------------------------------------------------------------------ + */ + library_features(report_delay_calculation); + define_cell_area (pad_drivers,pad_driver_sites) ; + + lu_table_template(CLKTRAN_constraint_template) { + variable_1 : constrained_pin_transition; + index_1 ( "0.010, 0.050, 0.200, 0.400, 1.000" ); + } + lu_table_template(SRAM_load_template) { + variable_1 : total_output_net_capacitance; + index_1 ( "0.0008,0.0014,0.0051,0.0100,0.0339,0.0640" ); + } + lu_table_template(SIG2SRAM_constraint_template) { + variable_1 : related_pin_transition; + variable_2 : constrained_pin_transition; + index_1 ( "0.0080,0.0288,0.0616,0.1072,0.1920,0.3496,0.5952" ); + index_2 ( "0.0080,0.0288,0.0616,0.1072,0.1920,0.3496,0.5952" ); + } + + lu_table_template(SIG2SRAM_delay_template) { + variable_1 : input_net_transition; + variable_2 : total_output_net_capacitance; + index_1 ( "0.0080,0.0288,0.0616,0.1072,0.1920,0.3496,0.5952" ); + index_2 ( "0.0008,0.0014,0.0051,0.0100,0.0339,0.0640" ); + } + + type (D_31_0) { + base_type : array; + data_type : bit; + bit_width : 32; + bit_from : 31; + bit_to : 0; + downto : true; + } + + type (A_9_0) { + base_type : array; + data_type : bit; + bit_width : 10; + bit_from : 9; + bit_to : 0; + downto : true; + } + +cell(RM_IHPSG13_2P_1024x32_c2_bm_bist) { +pg_pin (VDD) { + pg_type : primary_power; + voltage_name : VDD; +} +pg_pin (VDDARRAY) { + pg_type : primary_power; + voltage_name : VDDARRAY; +} +pg_pin (VSS) { + pg_type : primary_ground; + voltage_name : VSS; +} + +memory() { + type : ram; + address_width : 10; + word_width : 32; +} + +interface_timing : false; +bus_naming_style : "%s[%d]" ; +area : 264167.2813 ; + + pin(A_DLY) { + direction : input ; + capacitance : 0.00387999 ; + max_transition : "1" ; + related_power_pin : VDD; + related_ground_pin : VSS; + internal_power() { + rise_power("scalar") { + values (0); + } + fall_power("scalar") { + values (0); + } + } + } + +bus(A_ADDR) { + bus_type : A_9_0; + direction : input ; + capacitance : 0.0129586 ; + pin(A_ADDR[0]) { + capacitance : 0.0058687 ; + } + pin(A_ADDR[1]) { + capacitance : 0.00807137 ; + } + pin(A_ADDR[2]) { + capacitance : 0.0112051 ; + } + pin(A_ADDR[3]) { + capacitance : 0.00709524 ; + } + pin(A_ADDR[4]) { + capacitance : 0.00648778 ; + } + pin(A_ADDR[5]) { + capacitance : 0.011209 ; + } + pin(A_ADDR[6]) { + capacitance : 0.0140441 ; + } + pin(A_ADDR[7]) { + capacitance : 0.0111199 ; + } + pin(A_ADDR[8]) { + capacitance : 0.00957807 ; + } + max_transition : "0.5952" ; + pin(A_ADDR[9:0]) { + related_power_pin : VDD; + related_ground_pin : VSS; + internal_power() { + when : "A_MEN"; + rise_power("scalar"){ + values (0.0195); + } + fall_power("scalar"){ + values (0.0388); + } + } + internal_power() { + when : "!A_MEN"; + rise_power("scalar"){ + values (0.0129); + } + fall_power("scalar"){ + values (0.0238); + } + } + } + timing() { + timing_type : setup_rising; + related_pin : "A_CLK"; + when : "((A_WEN | A_REN)& A_MEN)" + sdf_cond : "A_RW_ACCESS" + + rise_constraint("SIG2SRAM_constraint_template") { + index_1("0.0080,0.0288,0.0616,0.1072,0.1920,0.3496,0.5952"); + index_2("0.0080,0.0288,0.0616,0.1072,0.1920,0.3496,0.5952"); + values ("-0.7371,-0.7176,-0.6863,-0.6434,-0.5652,-0.4168,-0.1980",\ +"-0.7566,-0.7371,-0.7059,-0.6629,-0.5848,-0.4363,-0.2137",\ +"-0.7879,-0.7645,-0.7332,-0.6902,-0.6121,-0.4637,-0.2449",\ +"-0.8309,-0.8074,-0.7762,-0.7332,-0.6551,-0.5066,-0.2879",\ +"-0.9051,-0.8895,-0.8543,-0.8113,-0.7332,-0.5887,-0.3660",\ +"-1.0418,-1.0262,-0.9949,-0.9480,-0.8699,-0.7293,-0.5027",\ +"-1.2684,-1.2449,-1.2176,-1.1707,-1.0965,-0.9480,-0.7293"); + } + + fall_constraint("SIG2SRAM_constraint_template") { + index_1("0.0080,0.0288,0.0616,0.1072,0.1920,0.3496,0.5952"); + index_2("0.0080,0.0288,0.0616,0.1072,0.1920,0.3496,0.5952"); + values ("-0.5926,-0.5730,-0.5418,-0.4988,-0.4246,-0.2879,-0.0730",\ +"-0.6121,-0.5926,-0.5613,-0.5223,-0.4441,-0.3074,-0.0887",\ +"-0.6395,-0.6199,-0.5926,-0.5496,-0.4715,-0.3348,-0.1160",\ +"-0.6863,-0.6668,-0.6355,-0.5965,-0.5184,-0.3777,-0.1590",\ +"-0.7605,-0.7410,-0.7137,-0.6746,-0.5926,-0.4559,-0.2410",\ +"-0.9012,-0.8816,-0.8504,-0.8113,-0.7332,-0.5926,-0.3895",\ +"-1.1238,-1.1043,-1.0769,-1.0379,-0.9559,-0.8191,-0.6004"); + } + } + + + timing() { + timing_type : hold_rising; + related_pin : "A_CLK"; + when : "((A_WEN | A_REN)& A_MEN)" + sdf_cond : "A_RW_ACCESS" + + rise_constraint("SIG2SRAM_constraint_template") { + index_1("0.0080,0.0288,0.0616,0.1072,0.1920,0.3496,0.5952"); + index_2("0.0080,0.0288,0.0616,0.1072,0.1920,0.3496,0.5952"); + values ("0.8488,0.8293,0.7980,0.7551,0.6730,0.5285,0.3098",\ +"0.8684,0.8488,0.8176,0.7746,0.6926,0.5480,0.3254",\ +"0.8996,0.8801,0.8449,0.8020,0.7238,0.5754,0.3527",\ +"0.9426,0.9191,0.8918,0.8488,0.7668,0.6223,0.3996",\ +"1.0168,1.0012,0.9699,0.9230,0.8449,0.7004,0.4777",\ +"1.1574,1.1379,1.1105,1.0598,0.9816,0.8371,0.6184",\ +"1.3801,1.3605,1.3254,1.2980,1.2043,1.0637,0.8371"); + } + + fall_constraint("SIG2SRAM_constraint_template") { + index_1("0.0080,0.0288,0.0616,0.1072,0.1920,0.3496,0.5952"); + index_2("0.0080,0.0288,0.0616,0.1072,0.1920,0.3496,0.5952"); + values ("0.6965,0.6770,0.6496,0.6066,0.5246,0.3918,0.1730",\ +"0.7160,0.6965,0.6652,0.6262,0.5441,0.4113,0.1965",\ +"0.7473,0.7277,0.6965,0.6535,0.5754,0.4426,0.2238",\ +"0.7863,0.7707,0.7395,0.7004,0.6223,0.4855,0.2629",\ +"0.8684,0.8449,0.8176,0.7785,0.7004,0.5637,0.3449",\ +"1.0051,0.9855,0.9855,0.9113,0.8332,0.7004,0.4895",\ +"1.2277,1.2082,1.1809,1.1379,1.0598,0.9230,0.7004"); + } + } +} +pin(A_WEN) { + direction : input ; + capacitance : 0.00313551 ; + max_transition : "0.5952" ; + related_power_pin : VDD; + related_ground_pin : VSS; + internal_power() { + when : "A_MEN"; + rise_power("scalar"){ + values (0.0268); + } + fall_power("scalar"){ + values (0.0213); + } + } + internal_power() { + when : "!A_MEN"; + rise_power("scalar"){ + values (0.0484); + } + fall_power("scalar"){ + values (0.0885); + } + } + timing() { + timing_type : setup_rising; + related_pin : "A_CLK"; + when : "A_MEN" + sdf_cond : "A_MEN" + + rise_constraint("SIG2SRAM_constraint_template") { + index_1("0.0080,0.0288,0.0616,0.1072,0.1920,0.3496,0.5952"); + index_2("0.0080,0.0288,0.0616,0.1072,0.1920,0.3496,0.5952"); + values ("0.3137,0.3332,0.3605,0.4035,0.4816,0.6223,0.8488",\ +"0.2980,0.3176,0.3410,0.3840,0.4660,0.6027,0.8293",\ +"0.2629,0.2824,0.3098,0.3527,0.4348,0.5754,0.7980",\ +"0.2199,0.2395,0.2668,0.3098,0.3918,0.5324,0.7590",\ +"0.1418,0.1613,0.1887,0.2316,0.3137,0.4348,0.6730",\ +"0.0012,0.0207,0.0520,0.0910,0.1730,0.3098,0.5285",\ +"-0.2215,-0.2020,-0.1746,-0.1277,-0.0496,0.0910,0.3098"); + } + + fall_constraint("SIG2SRAM_constraint_template") { + index_1("0.0080,0.0288,0.0616,0.1072,0.1920,0.3496,0.5952"); + index_2("0.0080,0.0288,0.0616,0.1072,0.1920,0.3496,0.5952"); + values ("0.4504,0.4699,0.4973,0.5324,0.6027,0.7355,0.9699",\ +"0.4309,0.4504,0.4777,0.5129,0.5910,0.7160,0.9504",\ +"0.3996,0.4191,0.4465,0.4816,0.5520,0.6848,0.9191",\ +"0.3605,0.3762,0.4035,0.4387,0.5168,0.6418,0.8723",\ +"0.2785,0.2980,0.3215,0.3605,0.4348,0.5637,0.7980",\ +"0.1379,0.1574,0.1809,0.2199,0.2980,0.4309,0.6457",\ +"-0.0809,-0.0613,-0.0340,0.0051,0.0832,0.2160,0.4191"); + } + } + + + timing() { + timing_type : hold_rising; + related_pin : "A_CLK"; + when : "A_MEN" + sdf_cond : "A_MEN" + + rise_constraint("SIG2SRAM_constraint_template") { + index_1("0.0080,0.0288,0.0616,0.1072,0.1920,0.3496,0.5952"); + index_2("0.0080,0.0288,0.0616,0.1072,0.1920,0.3496,0.5952"); + values ("0.3723,0.3527,0.3215,0.2785,0.1965,0.0559,-0.1668",\ +"0.3918,0.3723,0.3449,0.2980,0.2160,0.0754,-0.1473",\ +"0.4152,0.3996,0.3684,0.3254,0.2434,0.1066,-0.1199",\ +"0.4621,0.4465,0.4152,0.3723,0.2863,0.1496,-0.0730",\ +"0.5324,0.5207,0.4895,0.4465,0.3645,0.2199,0.0051",\ +"0.6770,0.6535,0.6301,0.5832,0.5090,0.3605,0.1418",\ +"0.9035,0.8879,0.8566,0.8137,0.7316,0.5871,0.3684"); + } + + fall_constraint("SIG2SRAM_constraint_template") { + index_1("0.0080,0.0288,0.0616,0.1072,0.1920,0.3496,0.5952"); + index_2("0.0080,0.0288,0.0616,0.1072,0.1920,0.3496,0.5952"); + values ("0.3762,0.3566,0.3293,0.2863,0.2043,0.0676,-0.1434",\ +"0.3957,0.3762,0.3488,0.3059,0.2238,0.0871,-0.1199",\ +"0.4230,0.4035,0.3723,0.3332,0.2512,0.1184,-0.0965",\ +"0.4660,0.4465,0.4191,0.3762,0.2941,0.1613,-0.0496",\ +"0.5324,0.5168,0.4973,0.4543,0.3723,0.2316,0.0285",\ +"0.6809,0.6613,0.6340,0.5910,0.5129,0.3645,0.1652",\ +"0.9113,0.8918,0.8605,0.8176,0.7395,0.5988,0.3879"); + } + } + } +pin(A_REN) { + direction : input ; + capacitance : 0.00381144 ; + max_transition : "0.5952" ; + related_power_pin : VDD; + related_ground_pin : VSS; + internal_power() { + when : "A_MEN"; + rise_power("scalar"){ + values (0.0263); + } + fall_power("scalar"){ + values (0.0112); + } + } + internal_power() { + when : "!A_MEN"; + rise_power("scalar"){ + values (0.0042); + } + fall_power("scalar"){ + values (0.0039); + } + } + timing() { + timing_type : setup_rising; + related_pin : "A_CLK"; + when : "A_MEN" + sdf_cond : "A_MEN" + + rise_constraint("SIG2SRAM_constraint_template") { + index_1("0.0080,0.0288,0.0616,0.1072,0.1920,0.3496,0.5952"); + index_2("0.0080,0.0288,0.0616,0.1072,0.1920,0.3496,0.5952"); + values ("-0.0770,-0.0574,-0.0262,0.0168,0.0949,0.2355,0.4582",\ +"-0.0965,-0.0770,-0.0457,-0.0027,0.0754,0.2160,0.4387",\ +"-0.1199,-0.1004,-0.0730,-0.0262,0.0520,0.1887,0.4113",\ +"-0.1590,-0.1434,-0.1160,-0.0730,0.0051,0.1457,0.3645",\ +"-0.2449,-0.2254,-0.1941,-0.1473,-0.0770,0.0676,0.2863",\ +"-0.3816,-0.3699,-0.3387,-0.2801,-0.2215,-0.0770,0.1457",\ +"-0.6121,-0.5926,-0.5613,-0.5145,-0.4363,-0.2996,-0.0730"); + } + + fall_constraint("SIG2SRAM_constraint_template") { + index_1("0.0080,0.0288,0.0616,0.1072,0.1920,0.3496,0.5952"); + index_2("0.0080,0.0288,0.0616,0.1072,0.1920,0.3496,0.5952"); + values ("0.1262,0.1457,0.1691,0.2121,0.2824,0.4191,0.6457",\ +"0.1105,0.1262,0.1496,0.1887,0.2629,0.3996,0.6262",\ +"0.0793,0.0949,0.1223,0.1652,0.2395,0.3684,0.5949",\ +"0.0363,0.0559,0.0793,0.1223,0.2004,0.3410,0.5520",\ +"-0.0457,-0.0262,0.0012,0.0441,0.1301,0.2629,0.4738",\ +"-0.1902,-0.1746,-0.1434,-0.1043,-0.0184,0.1223,0.3332",\ +"-0.4129,-0.3934,-0.3660,-0.3230,-0.2449,-0.1043,0.1105"); + } + } + + + timing() { + timing_type : hold_rising; + related_pin : "A_CLK"; + when : "A_MEN" + sdf_cond : "A_MEN" + + rise_constraint("SIG2SRAM_constraint_template") { + index_1("0.0080,0.0288,0.0616,0.1072,0.1920,0.3496,0.5952"); + index_2("0.0080,0.0288,0.0616,0.1072,0.1920,0.3496,0.5952"); + values ("0.4113,0.3918,0.3645,0.3176,0.2395,0.0988,-0.1238",\ +"0.4309,0.4113,0.3840,0.3371,0.2590,0.1184,-0.1043",\ +"0.4582,0.4387,0.4113,0.3645,0.2824,0.1457,-0.0770",\ +"0.5051,0.4816,0.4543,0.4074,0.3293,0.1887,-0.0340",\ +"0.5715,0.5598,0.5324,0.4895,0.4035,0.2512,0.0441",\ +"0.7043,0.7004,0.6730,0.6262,0.5402,0.3957,0.1809",\ +"0.9387,0.9270,0.8957,0.8527,0.7746,0.6262,0.4074"); + } + + fall_constraint("SIG2SRAM_constraint_template") { + index_1("0.0080,0.0288,0.0616,0.1072,0.1920,0.3496,0.5952"); + index_2("0.0080,0.0288,0.0616,0.1072,0.1920,0.3496,0.5952"); + values ("0.4152,0.3918,0.3645,0.3215,0.2395,0.1027,-0.1082",\ +"0.4309,0.4113,0.3801,0.3410,0.2590,0.1223,-0.0926",\ +"0.4582,0.4387,0.4074,0.3684,0.2863,0.1496,-0.0613",\ +"0.5012,0.4816,0.4504,0.4074,0.3293,0.1887,-0.0145",\ +"0.5715,0.5559,0.5285,0.4816,0.3996,0.2512,0.0598",\ +"0.7160,0.7004,0.6691,0.6262,0.5520,0.4035,0.2004",\ +"0.9387,0.9191,0.8957,0.8488,0.7707,0.6262,0.4113"); + } + } + } +pin(A_MEN) { + direction : input ; + capacitance : 0.00300347 ; + max_transition : "0.5952" ; + related_power_pin : VDD; + related_ground_pin : VSS; + internal_power() { + rise_power("scalar"){ + values (0.0005); + } + fall_power("scalar"){ + values (0.0301); + } + } + timing() { + timing_type : setup_rising; + related_pin : "A_CLK"; + + rise_constraint("SIG2SRAM_constraint_template") { + index_1("0.0080,0.0288,0.0616,0.1072,0.1920,0.3496,0.5952"); + index_2("0.0080,0.0288,0.0616,0.1072,0.1920,0.3496,0.5952"); + values ("0.3215,0.3449,0.3684,0.4113,0.4895,0.6301,0.8527",\ +"0.3059,0.3254,0.3527,0.3957,0.4738,0.6145,0.8371",\ +"0.2746,0.2941,0.3215,0.3645,0.4426,0.5871,0.8059",\ +"0.2316,0.2512,0.2785,0.3215,0.3996,0.5402,0.7629",\ +"0.1496,0.1730,0.1965,0.2395,0.3215,0.4660,0.6848",\ +"0.0090,0.0285,0.0598,0.1027,0.1809,0.3176,0.5402",\ +"-0.2098,-0.1902,-0.1668,-0.1199,-0.0418,0.0988,0.3137"); + } + + fall_constraint("SIG2SRAM_constraint_template") { + index_1("0.0080,0.0288,0.0616,0.1072,0.1920,0.3496,0.5952"); + index_2("0.0080,0.0288,0.0616,0.1072,0.1920,0.3496,0.5952"); + values ("0.4582,0.4738,0.5012,0.5363,0.6145,0.7395,0.9738",\ +"0.4387,0.4543,0.4816,0.5207,0.5910,0.7199,0.9582",\ +"0.4035,0.4230,0.4504,0.4855,0.5637,0.6887,0.9230",\ +"0.3645,0.3840,0.4074,0.4465,0.5285,0.6496,0.8840",\ +"0.2824,0.3020,0.3254,0.3645,0.4465,0.5715,0.7980",\ +"0.1418,0.1613,0.1887,0.2238,0.3020,0.4309,0.6496",\ +"-0.0770,-0.0574,-0.0301,0.0090,0.0910,0.2238,0.4191"); + } + } + + + timing() { + timing_type : hold_rising; + related_pin : "A_CLK"; + + rise_constraint("SIG2SRAM_constraint_template") { + index_1("0.0080,0.0288,0.0616,0.1072,0.1920,0.3496,0.5952"); + index_2("0.0080,0.0288,0.0616,0.1072,0.1920,0.3496,0.5952"); + values ("0.3762,0.3605,0.3293,0.2863,0.2043,0.0637,-0.1629",\ +"0.3996,0.3801,0.3488,0.3020,0.2238,0.0832,-0.1395",\ +"0.4230,0.4074,0.3723,0.3293,0.2473,0.1105,-0.1121",\ +"0.4621,0.4465,0.4152,0.3762,0.2941,0.1535,-0.0691",\ +"0.5441,0.5285,0.4973,0.4465,0.3684,0.2316,0.0090",\ +"0.6848,0.6652,0.6301,0.5910,0.5129,0.3605,0.1496",\ +"0.9074,0.8918,0.8566,0.8215,0.7395,0.5910,0.3723"); + } + + fall_constraint("SIG2SRAM_constraint_template") { + index_1("0.0080,0.0288,0.0616,0.1072,0.1920,0.3496,0.5952"); + index_2("0.0080,0.0288,0.0616,0.1072,0.1920,0.3496,0.5952"); + values ("0.3762,0.3605,0.3332,0.2863,0.2043,0.0715,-0.1395",\ +"0.3996,0.3762,0.3488,0.3059,0.2238,0.0910,-0.1199",\ +"0.4270,0.4035,0.3762,0.3332,0.2512,0.1184,-0.0965",\ +"0.4699,0.4504,0.4191,0.3762,0.2941,0.1613,-0.0496",\ +"0.5441,0.5285,0.4973,0.4543,0.3762,0.2355,0.0324",\ +"0.6770,0.6613,0.6340,0.5949,0.5207,0.3762,0.1652",\ +"0.9074,0.8918,0.8605,0.8176,0.7395,0.6027,0.3918"); + } + } + } +bus(A_BM) { + bus_type : D_31_0; + direction : input ; + capacitance : 0.00359979 ; + max_transition : "0.5952" ; + pin(A_BM[31:0]) { + related_power_pin : VDD; + related_ground_pin : VSS; + internal_power() { + when : "A_MEN"; + rise_power("scalar"){ + values (0.0632); + } + fall_power("scalar"){ + values (0.0448); + } + } + internal_power() { + when : "!A_MEN"; + rise_power("scalar"){ + values (0.0895); + } + fall_power("scalar"){ + values (0.0291); + } + } + } + timing() { + timing_type : setup_rising; + related_pin : "A_CLK"; + when : "(A_WEN & A_MEN)" + sdf_cond : "A_RW_ACCESS" + + rise_constraint("SIG2SRAM_constraint_template") { + index_1("0.0080,0.0288,0.0616,0.1072,0.1920,0.3496,0.5952"); + index_2("0.0080,0.0288,0.0616,0.1072,0.1920,0.3496,0.5952"); + values ("-0.9175,-0.8980,-0.8726,-0.8296,-0.7486,-0.6031,-0.3804",\ +"-0.9255,-0.9060,-0.8806,-0.8376,-0.7566,-0.6111,-0.3884",\ +"-0.9345,-0.9150,-0.8896,-0.8467,-0.7656,-0.6201,-0.3974",\ +"-0.9477,-0.9282,-0.9028,-0.8598,-0.7788,-0.6332,-0.4106",\ +"-0.9720,-0.9524,-0.9271,-0.8841,-0.8030,-0.6575,-0.4349",\ +"-1.0025,-0.9830,-0.9576,-0.9146,-0.8336,-0.6880,-0.4654",\ +"-1.0839,-1.0644,-1.0390,-0.9961,-0.9150,-0.7695,-0.5468"); + } + + fall_constraint("SIG2SRAM_constraint_template") { + index_1("0.0080,0.0288,0.0616,0.1072,0.1920,0.3496,0.5952"); + index_2("0.0080,0.0288,0.0616,0.1072,0.1920,0.3496,0.5952"); + values ("-0.8550,-0.8374,-0.8101,-0.7710,-0.6880,-0.5523,-0.3404",\ +"-0.8630,-0.8455,-0.8181,-0.7791,-0.6960,-0.5603,-0.3484",\ +"-0.8720,-0.8545,-0.8271,-0.7881,-0.7051,-0.5693,-0.3574",\ +"-0.8852,-0.8676,-0.8403,-0.8012,-0.7182,-0.5825,-0.3706",\ +"-0.9095,-0.8919,-0.8646,-0.8255,-0.7425,-0.6067,-0.3948",\ +"-0.9400,-0.9224,-0.8951,-0.8560,-0.7730,-0.6373,-0.4253",\ +"-1.0214,-1.0039,-0.9765,-0.9375,-0.8544,-0.7187,-0.5068"); + } + } + + + timing() { + timing_type : hold_rising; + related_pin : "A_CLK"; + when : "(A_WEN & A_MEN)" + sdf_cond : "A_RW_ACCESS" + + rise_constraint("SIG2SRAM_constraint_template") { + index_1("0.0080,0.0288,0.0616,0.1072,0.1920,0.3496,0.5952"); + index_2("0.0080,0.0288,0.0616,0.1072,0.1920,0.3496,0.5952"); + values ("1.0343,1.0128,0.9884,0.9454,0.8654,0.7189,0.4962",\ +"1.0423,1.0209,0.9964,0.9535,0.8734,0.7269,0.5042",\ +"1.0513,1.0299,1.0054,0.9625,0.8824,0.7359,0.5133",\ +"1.0645,1.0430,1.0186,0.9756,0.8956,0.7491,0.5264",\ +"1.0888,1.0673,1.0429,0.9999,0.9198,0.7733,0.5507",\ +"1.1193,1.0978,1.0734,1.0304,0.9503,0.8039,0.5812",\ +"1.2007,1.1793,1.1548,1.1119,1.0318,0.8853,0.6627"); + } + + fall_constraint("SIG2SRAM_constraint_template") { + index_1("0.0080,0.0288,0.0616,0.1072,0.1920,0.3496,0.5952"); + index_2("0.0080,0.0288,0.0616,0.1072,0.1920,0.3496,0.5952"); + values ("0.9601,0.9425,0.9152,0.8761,0.7931,0.6564,0.4454",\ +"0.9681,0.9505,0.9232,0.8841,0.8011,0.6644,0.4535",\ +"0.9771,0.9595,0.9322,0.8931,0.8101,0.6734,0.4625",\ +"0.9903,0.9727,0.9454,0.9063,0.8233,0.6866,0.4756",\ +"1.0146,0.9970,0.9696,0.9306,0.8476,0.7108,0.4999",\ +"1.0451,1.0275,1.0002,0.9611,0.8781,0.7414,0.5304",\ +"1.1265,1.1089,1.0816,1.0425,0.9595,0.8228,0.6119"); + } + } +} + pin(A_CLK) { + direction : input; + capacitance : 0.00378957; + max_transition : "0.5952"; + clock : "true" ; + pin_func_type : active_rising ; + + timing () { + timing_type : "min_pulse_width"; + related_pin : "A_CLK"; + rise_constraint("CLKTRAN_constraint_template") { + index_1("0.008,0.5952"); + values("0.4,0.4"); + } + } + + related_power_pin : VDD; + related_ground_pin : VSS; + + internal_power() { + when : "!A_MEN & !A_WEN & !A_REN"; + rise_power("scalar"){ + values (0); + } + fall_power("scalar"){ + values (0); + } + } + internal_power() { + when : "!A_MEN & A_WEN & !A_REN"; + rise_power("scalar"){ + values (0.6568); + } + fall_power("scalar"){ + values (0); + } + } + internal_power() { + when : "A_MEN & A_WEN & !A_REN"; + rise_power("scalar"){ + values (46.0330); + } + fall_power("scalar"){ + values (0); + } + } + internal_power() { + when : "A_MEN & A_WEN & A_REN"; + rise_power("scalar"){ + values (49.3119); + } + fall_power("scalar"){ + values (0); + } + } + internal_power() { + when : "A_MEN & !A_WEN & A_REN"; + rise_power("scalar"){ + values (36.0779); + } + fall_power("scalar"){ + values (0); + } + } + internal_power() { + when : "!A_MEN & !A_WEN & A_REN"; + rise_power("scalar"){ + values (0.4418); + } + fall_power("scalar"){ + values (0); + } + } + internal_power() { + when : "!A_MEN & A_WEN & A_REN"; + rise_power("scalar"){ + values (1.1609); + } + fall_power("scalar"){ + values (0); + } + } + internal_power() { + when : "A_MEN & !A_WEN & !A_REN"; + rise_power("scalar"){ + values (0); + } + fall_power("scalar"){ + values (0); + } + } + } + bus(A_DIN) { + bus_type : D_31_0; + direction : input ; + capacitance : 0.00502163 ; + memory_write() { + address : A_ADDR ; + clocked_on : A_CLK; + } + + max_transition : "0.5952" ; + pin(A_DIN[31:0]) { + related_power_pin : VDD; + related_ground_pin : VSS; + internal_power() { + when : "A_MEN"; + rise_power("scalar"){ + values (0.0632); + } + fall_power("scalar"){ + values (0.0448); + } + } + internal_power() { + when : "!A_MEN"; + rise_power("scalar"){ + values (0.0895); + } + fall_power("scalar"){ + values (0.0291); + } + } + } + timing() { + timing_type : setup_rising; + related_pin : "A_CLK"; + when : "(A_WEN & A_MEN)"; + sdf_cond : "A_W_ACCESS"; + + rise_constraint("SIG2SRAM_constraint_template") { + index_1("0.0080,0.0288,0.0616,0.1072,0.1920,0.3496,0.5952"); + index_2("0.0080,0.0288,0.0616,0.1072,0.1920,0.3496,0.5952"); + values ("-0.9175,-0.8980,-0.8726,-0.8296,-0.7486,-0.6031,-0.3804",\ +"-0.9255,-0.9060,-0.8806,-0.8376,-0.7566,-0.6111,-0.3884",\ +"-0.9345,-0.9150,-0.8896,-0.8467,-0.7656,-0.6201,-0.3974",\ +"-0.9477,-0.9282,-0.9028,-0.8598,-0.7788,-0.6332,-0.4106",\ +"-0.9720,-0.9524,-0.9271,-0.8841,-0.8030,-0.6575,-0.4349",\ +"-1.0025,-0.9830,-0.9576,-0.9146,-0.8336,-0.6880,-0.4654",\ +"-1.0839,-1.0644,-1.0390,-0.9961,-0.9150,-0.7695,-0.5468"); + } + + fall_constraint("SIG2SRAM_constraint_template") { + index_1("0.0080,0.0288,0.0616,0.1072,0.1920,0.3496,0.5952"); + index_2("0.0080,0.0288,0.0616,0.1072,0.1920,0.3496,0.5952"); + values ("-0.8550,-0.8374,-0.8101,-0.7710,-0.6880,-0.5523,-0.3404",\ +"-0.8630,-0.8455,-0.8181,-0.7791,-0.6960,-0.5603,-0.3484",\ +"-0.8720,-0.8545,-0.8271,-0.7881,-0.7051,-0.5693,-0.3574",\ +"-0.8852,-0.8676,-0.8403,-0.8012,-0.7182,-0.5825,-0.3706",\ +"-0.9095,-0.8919,-0.8646,-0.8255,-0.7425,-0.6067,-0.3948",\ +"-0.9400,-0.9224,-0.8951,-0.8560,-0.7730,-0.6373,-0.4253",\ +"-1.0214,-1.0039,-0.9765,-0.9375,-0.8544,-0.7187,-0.5068"); + } + } + + timing() { + timing_type : hold_rising; + related_pin : "A_CLK"; + when : "(A_WEN & A_MEN)"; + sdf_cond : "A_W_ACCESS"; + + rise_constraint("SIG2SRAM_constraint_template") { + index_1("0.0080,0.0288,0.0616,0.1072,0.1920,0.3496,0.5952"); + index_2("0.0080,0.0288,0.0616,0.1072,0.1920,0.3496,0.5952"); + values ("1.0343,1.0128,0.9884,0.9454,0.8654,0.7189,0.4962",\ +"1.0423,1.0209,0.9964,0.9535,0.8734,0.7269,0.5042",\ +"1.0513,1.0299,1.0054,0.9625,0.8824,0.7359,0.5133",\ +"1.0645,1.0430,1.0186,0.9756,0.8956,0.7491,0.5264",\ +"1.0888,1.0673,1.0429,0.9999,0.9198,0.7733,0.5507",\ +"1.1193,1.0978,1.0734,1.0304,0.9503,0.8039,0.5812",\ +"1.2007,1.1793,1.1548,1.1119,1.0318,0.8853,0.6627"); + } + + fall_constraint("SIG2SRAM_constraint_template") { + index_1("0.0080,0.0288,0.0616,0.1072,0.1920,0.3496,0.5952"); + index_2("0.0080,0.0288,0.0616,0.1072,0.1920,0.3496,0.5952"); + values ("0.9601,0.9425,0.9152,0.8761,0.7931,0.6564,0.4454",\ +"0.9681,0.9505,0.9232,0.8841,0.8011,0.6644,0.4535",\ +"0.9771,0.9595,0.9322,0.8931,0.8101,0.6734,0.4625",\ +"0.9903,0.9727,0.9454,0.9063,0.8233,0.6866,0.4756",\ +"1.0146,0.9970,0.9696,0.9306,0.8476,0.7108,0.4999",\ +"1.0451,1.0275,1.0002,0.9611,0.8781,0.7414,0.5304",\ +"1.1265,1.1089,1.0816,1.0425,0.9595,0.8228,0.6119"); + } + } + } + + pin(A_BIST_EN) { + direction : input ; + capacitance : 0.00387999 ; + max_transition : "1" ; + related_power_pin : VDD; + related_ground_pin : VSS; + internal_power() { + rise_power("scalar") { + values (0); + } + fall_power("scalar") { + values (0); + } + } + } + +bus(A_BIST_ADDR) { + bus_type : A_9_0; + direction : input ; + capacitance : 0.0129586 ; + pin(A_BIST_ADDR[0]) { + capacitance : 0.0058687 ; + } + pin(A_BIST_ADDR[1]) { + capacitance : 0.00807137 ; + } + pin(A_BIST_ADDR[2]) { + capacitance : 0.0112051 ; + } + pin(A_BIST_ADDR[3]) { + capacitance : 0.00709524 ; + } + pin(A_BIST_ADDR[4]) { + capacitance : 0.00648778 ; + } + pin(A_BIST_ADDR[5]) { + capacitance : 0.011209 ; + } + pin(A_BIST_ADDR[6]) { + capacitance : 0.0140441 ; + } + pin(A_BIST_ADDR[7]) { + capacitance : 0.0111199 ; + } + pin(A_BIST_ADDR[8]) { + capacitance : 0.00957807 ; + } + max_transition : "0.5952" ; + pin(A_BIST_ADDR[9:0]) { + related_power_pin : VDD; + related_ground_pin : VSS; + internal_power() { + when : "A_BIST_MEN"; + rise_power("scalar"){ + values (0.0195); + } + fall_power("scalar"){ + values (0.0388); + } + } + internal_power() { + when : "!A_BIST_MEN"; + rise_power("scalar"){ + values (0.0129); + } + fall_power("scalar"){ + values (0.0238); + } + } + } + timing() { + timing_type : setup_rising; + related_pin : "A_BIST_CLK"; + when : "((A_BIST_WEN | A_BIST_REN)& A_BIST_MEN)" + sdf_cond : "A_BIST_RW_ACCESS" + + rise_constraint("SIG2SRAM_constraint_template") { + index_1("0.0080,0.0288,0.0616,0.1072,0.1920,0.3496,0.5952"); + index_2("0.0080,0.0288,0.0616,0.1072,0.1920,0.3496,0.5952"); + values ("-0.7371,-0.7176,-0.6863,-0.6434,-0.5652,-0.4168,-0.1980",\ +"-0.7566,-0.7371,-0.7059,-0.6629,-0.5848,-0.4363,-0.2137",\ +"-0.7879,-0.7645,-0.7332,-0.6902,-0.6121,-0.4637,-0.2449",\ +"-0.8309,-0.8074,-0.7762,-0.7332,-0.6551,-0.5066,-0.2879",\ +"-0.9051,-0.8895,-0.8543,-0.8113,-0.7332,-0.5887,-0.3660",\ +"-1.0418,-1.0262,-0.9949,-0.9480,-0.8699,-0.7293,-0.5027",\ +"-1.2684,-1.2449,-1.2176,-1.1707,-1.0965,-0.9480,-0.7293"); + } + + fall_constraint("SIG2SRAM_constraint_template") { + index_1("0.0080,0.0288,0.0616,0.1072,0.1920,0.3496,0.5952"); + index_2("0.0080,0.0288,0.0616,0.1072,0.1920,0.3496,0.5952"); + values ("-0.5926,-0.5730,-0.5418,-0.4988,-0.4246,-0.2879,-0.0730",\ +"-0.6121,-0.5926,-0.5613,-0.5223,-0.4441,-0.3074,-0.0887",\ +"-0.6395,-0.6199,-0.5926,-0.5496,-0.4715,-0.3348,-0.1160",\ +"-0.6863,-0.6668,-0.6355,-0.5965,-0.5184,-0.3777,-0.1590",\ +"-0.7605,-0.7410,-0.7137,-0.6746,-0.5926,-0.4559,-0.2410",\ +"-0.9012,-0.8816,-0.8504,-0.8113,-0.7332,-0.5926,-0.3895",\ +"-1.1238,-1.1043,-1.0769,-1.0379,-0.9559,-0.8191,-0.6004"); + } + } + + + timing() { + timing_type : hold_rising; + related_pin : "A_BIST_CLK"; + when : "((A_BIST_WEN | A_BIST_REN)& A_BIST_MEN)" + sdf_cond : "A_BIST_RW_ACCESS" + + rise_constraint("SIG2SRAM_constraint_template") { + index_1("0.0080,0.0288,0.0616,0.1072,0.1920,0.3496,0.5952"); + index_2("0.0080,0.0288,0.0616,0.1072,0.1920,0.3496,0.5952"); + values ("0.8488,0.8293,0.7980,0.7551,0.6730,0.5285,0.3098",\ +"0.8684,0.8488,0.8176,0.7746,0.6926,0.5480,0.3254",\ +"0.8996,0.8801,0.8449,0.8020,0.7238,0.5754,0.3527",\ +"0.9426,0.9191,0.8918,0.8488,0.7668,0.6223,0.3996",\ +"1.0168,1.0012,0.9699,0.9230,0.8449,0.7004,0.4777",\ +"1.1574,1.1379,1.1105,1.0598,0.9816,0.8371,0.6184",\ +"1.3801,1.3605,1.3254,1.2980,1.2043,1.0637,0.8371"); + } + + fall_constraint("SIG2SRAM_constraint_template") { + index_1("0.0080,0.0288,0.0616,0.1072,0.1920,0.3496,0.5952"); + index_2("0.0080,0.0288,0.0616,0.1072,0.1920,0.3496,0.5952"); + values ("0.6965,0.6770,0.6496,0.6066,0.5246,0.3918,0.1730",\ +"0.7160,0.6965,0.6652,0.6262,0.5441,0.4113,0.1965",\ +"0.7473,0.7277,0.6965,0.6535,0.5754,0.4426,0.2238",\ +"0.7863,0.7707,0.7395,0.7004,0.6223,0.4855,0.2629",\ +"0.8684,0.8449,0.8176,0.7785,0.7004,0.5637,0.3449",\ +"1.0051,0.9855,0.9855,0.9113,0.8332,0.7004,0.4895",\ +"1.2277,1.2082,1.1809,1.1379,1.0598,0.9230,0.7004"); + } + } +} +pin(A_BIST_WEN) { + direction : input ; + capacitance : 0.00313551 ; + max_transition : "0.5952" ; + related_power_pin : VDD; + related_ground_pin : VSS; + internal_power() { + when : "A_BIST_MEN"; + rise_power("scalar"){ + values (0.0268); + } + fall_power("scalar"){ + values (0.0213); + } + } + internal_power() { + when : "!A_BIST_MEN"; + rise_power("scalar"){ + values (0.0484); + } + fall_power("scalar"){ + values (0.0885); + } + } + timing() { + timing_type : setup_rising; + related_pin : "A_BIST_CLK"; + when : "A_BIST_MEN" + sdf_cond : "A_BIST_MEN" + + rise_constraint("SIG2SRAM_constraint_template") { + index_1("0.0080,0.0288,0.0616,0.1072,0.1920,0.3496,0.5952"); + index_2("0.0080,0.0288,0.0616,0.1072,0.1920,0.3496,0.5952"); + values ("0.3137,0.3332,0.3605,0.4035,0.4816,0.6223,0.8488",\ +"0.2980,0.3176,0.3410,0.3840,0.4660,0.6027,0.8293",\ +"0.2629,0.2824,0.3098,0.3527,0.4348,0.5754,0.7980",\ +"0.2199,0.2395,0.2668,0.3098,0.3918,0.5324,0.7590",\ +"0.1418,0.1613,0.1887,0.2316,0.3137,0.4348,0.6730",\ +"0.0012,0.0207,0.0520,0.0910,0.1730,0.3098,0.5285",\ +"-0.2215,-0.2020,-0.1746,-0.1277,-0.0496,0.0910,0.3098"); + } + + fall_constraint("SIG2SRAM_constraint_template") { + index_1("0.0080,0.0288,0.0616,0.1072,0.1920,0.3496,0.5952"); + index_2("0.0080,0.0288,0.0616,0.1072,0.1920,0.3496,0.5952"); + values ("0.4504,0.4699,0.4973,0.5324,0.6027,0.7355,0.9699",\ +"0.4309,0.4504,0.4777,0.5129,0.5910,0.7160,0.9504",\ +"0.3996,0.4191,0.4465,0.4816,0.5520,0.6848,0.9191",\ +"0.3605,0.3762,0.4035,0.4387,0.5168,0.6418,0.8723",\ +"0.2785,0.2980,0.3215,0.3605,0.4348,0.5637,0.7980",\ +"0.1379,0.1574,0.1809,0.2199,0.2980,0.4309,0.6457",\ +"-0.0809,-0.0613,-0.0340,0.0051,0.0832,0.2160,0.4191"); + } + } + + + timing() { + timing_type : hold_rising; + related_pin : "A_BIST_CLK"; + when : "A_BIST_MEN" + sdf_cond : "A_BIST_MEN" + + rise_constraint("SIG2SRAM_constraint_template") { + index_1("0.0080,0.0288,0.0616,0.1072,0.1920,0.3496,0.5952"); + index_2("0.0080,0.0288,0.0616,0.1072,0.1920,0.3496,0.5952"); + values ("0.3723,0.3527,0.3215,0.2785,0.1965,0.0559,-0.1668",\ +"0.3918,0.3723,0.3449,0.2980,0.2160,0.0754,-0.1473",\ +"0.4152,0.3996,0.3684,0.3254,0.2434,0.1066,-0.1199",\ +"0.4621,0.4465,0.4152,0.3723,0.2863,0.1496,-0.0730",\ +"0.5324,0.5207,0.4895,0.4465,0.3645,0.2199,0.0051",\ +"0.6770,0.6535,0.6301,0.5832,0.5090,0.3605,0.1418",\ +"0.9035,0.8879,0.8566,0.8137,0.7316,0.5871,0.3684"); + } + + fall_constraint("SIG2SRAM_constraint_template") { + index_1("0.0080,0.0288,0.0616,0.1072,0.1920,0.3496,0.5952"); + index_2("0.0080,0.0288,0.0616,0.1072,0.1920,0.3496,0.5952"); + values ("0.3762,0.3566,0.3293,0.2863,0.2043,0.0676,-0.1434",\ +"0.3957,0.3762,0.3488,0.3059,0.2238,0.0871,-0.1199",\ +"0.4230,0.4035,0.3723,0.3332,0.2512,0.1184,-0.0965",\ +"0.4660,0.4465,0.4191,0.3762,0.2941,0.1613,-0.0496",\ +"0.5324,0.5168,0.4973,0.4543,0.3723,0.2316,0.0285",\ +"0.6809,0.6613,0.6340,0.5910,0.5129,0.3645,0.1652",\ +"0.9113,0.8918,0.8605,0.8176,0.7395,0.5988,0.3879"); + } + } + } +pin(A_BIST_REN) { + direction : input ; + capacitance : 0.00381144 ; + max_transition : "0.5952" ; + related_power_pin : VDD; + related_ground_pin : VSS; + internal_power() { + when : "A_BIST_MEN"; + rise_power("scalar"){ + values (0.0263); + } + fall_power("scalar"){ + values (0.0112); + } + } + internal_power() { + when : "!A_BIST_MEN"; + rise_power("scalar"){ + values (0.0042); + } + fall_power("scalar"){ + values (0.0039); + } + } + timing() { + timing_type : setup_rising; + related_pin : "A_BIST_CLK"; + when : "A_BIST_MEN" + sdf_cond : "A_BIST_MEN" + + rise_constraint("SIG2SRAM_constraint_template") { + index_1("0.0080,0.0288,0.0616,0.1072,0.1920,0.3496,0.5952"); + index_2("0.0080,0.0288,0.0616,0.1072,0.1920,0.3496,0.5952"); + values ("-0.0770,-0.0574,-0.0262,0.0168,0.0949,0.2355,0.4582",\ +"-0.0965,-0.0770,-0.0457,-0.0027,0.0754,0.2160,0.4387",\ +"-0.1199,-0.1004,-0.0730,-0.0262,0.0520,0.1887,0.4113",\ +"-0.1590,-0.1434,-0.1160,-0.0730,0.0051,0.1457,0.3645",\ +"-0.2449,-0.2254,-0.1941,-0.1473,-0.0770,0.0676,0.2863",\ +"-0.3816,-0.3699,-0.3387,-0.2801,-0.2215,-0.0770,0.1457",\ +"-0.6121,-0.5926,-0.5613,-0.5145,-0.4363,-0.2996,-0.0730"); + } + + fall_constraint("SIG2SRAM_constraint_template") { + index_1("0.0080,0.0288,0.0616,0.1072,0.1920,0.3496,0.5952"); + index_2("0.0080,0.0288,0.0616,0.1072,0.1920,0.3496,0.5952"); + values ("0.1262,0.1457,0.1691,0.2121,0.2824,0.4191,0.6457",\ +"0.1105,0.1262,0.1496,0.1887,0.2629,0.3996,0.6262",\ +"0.0793,0.0949,0.1223,0.1652,0.2395,0.3684,0.5949",\ +"0.0363,0.0559,0.0793,0.1223,0.2004,0.3410,0.5520",\ +"-0.0457,-0.0262,0.0012,0.0441,0.1301,0.2629,0.4738",\ +"-0.1902,-0.1746,-0.1434,-0.1043,-0.0184,0.1223,0.3332",\ +"-0.4129,-0.3934,-0.3660,-0.3230,-0.2449,-0.1043,0.1105"); + } + } + + + timing() { + timing_type : hold_rising; + related_pin : "A_BIST_CLK"; + when : "A_BIST_MEN" + sdf_cond : "A_BIST_MEN" + + rise_constraint("SIG2SRAM_constraint_template") { + index_1("0.0080,0.0288,0.0616,0.1072,0.1920,0.3496,0.5952"); + index_2("0.0080,0.0288,0.0616,0.1072,0.1920,0.3496,0.5952"); + values ("0.4113,0.3918,0.3645,0.3176,0.2395,0.0988,-0.1238",\ +"0.4309,0.4113,0.3840,0.3371,0.2590,0.1184,-0.1043",\ +"0.4582,0.4387,0.4113,0.3645,0.2824,0.1457,-0.0770",\ +"0.5051,0.4816,0.4543,0.4074,0.3293,0.1887,-0.0340",\ +"0.5715,0.5598,0.5324,0.4895,0.4035,0.2512,0.0441",\ +"0.7043,0.7004,0.6730,0.6262,0.5402,0.3957,0.1809",\ +"0.9387,0.9270,0.8957,0.8527,0.7746,0.6262,0.4074"); + } + + fall_constraint("SIG2SRAM_constraint_template") { + index_1("0.0080,0.0288,0.0616,0.1072,0.1920,0.3496,0.5952"); + index_2("0.0080,0.0288,0.0616,0.1072,0.1920,0.3496,0.5952"); + values ("0.4152,0.3918,0.3645,0.3215,0.2395,0.1027,-0.1082",\ +"0.4309,0.4113,0.3801,0.3410,0.2590,0.1223,-0.0926",\ +"0.4582,0.4387,0.4074,0.3684,0.2863,0.1496,-0.0613",\ +"0.5012,0.4816,0.4504,0.4074,0.3293,0.1887,-0.0145",\ +"0.5715,0.5559,0.5285,0.4816,0.3996,0.2512,0.0598",\ +"0.7160,0.7004,0.6691,0.6262,0.5520,0.4035,0.2004",\ +"0.9387,0.9191,0.8957,0.8488,0.7707,0.6262,0.4113"); + } + } + } +pin(A_BIST_MEN) { + direction : input ; + capacitance : 0.00300347 ; + max_transition : "0.5952" ; + related_power_pin : VDD; + related_ground_pin : VSS; + internal_power() { + rise_power("scalar"){ + values (0.0005); + } + fall_power("scalar"){ + values (0.0301); + } + } + timing() { + timing_type : setup_rising; + related_pin : "A_BIST_CLK"; + + rise_constraint("SIG2SRAM_constraint_template") { + index_1("0.0080,0.0288,0.0616,0.1072,0.1920,0.3496,0.5952"); + index_2("0.0080,0.0288,0.0616,0.1072,0.1920,0.3496,0.5952"); + values ("0.3215,0.3449,0.3684,0.4113,0.4895,0.6301,0.8527",\ +"0.3059,0.3254,0.3527,0.3957,0.4738,0.6145,0.8371",\ +"0.2746,0.2941,0.3215,0.3645,0.4426,0.5871,0.8059",\ +"0.2316,0.2512,0.2785,0.3215,0.3996,0.5402,0.7629",\ +"0.1496,0.1730,0.1965,0.2395,0.3215,0.4660,0.6848",\ +"0.0090,0.0285,0.0598,0.1027,0.1809,0.3176,0.5402",\ +"-0.2098,-0.1902,-0.1668,-0.1199,-0.0418,0.0988,0.3137"); + } + + fall_constraint("SIG2SRAM_constraint_template") { + index_1("0.0080,0.0288,0.0616,0.1072,0.1920,0.3496,0.5952"); + index_2("0.0080,0.0288,0.0616,0.1072,0.1920,0.3496,0.5952"); + values ("0.4582,0.4738,0.5012,0.5363,0.6145,0.7395,0.9738",\ +"0.4387,0.4543,0.4816,0.5207,0.5910,0.7199,0.9582",\ +"0.4035,0.4230,0.4504,0.4855,0.5637,0.6887,0.9230",\ +"0.3645,0.3840,0.4074,0.4465,0.5285,0.6496,0.8840",\ +"0.2824,0.3020,0.3254,0.3645,0.4465,0.5715,0.7980",\ +"0.1418,0.1613,0.1887,0.2238,0.3020,0.4309,0.6496",\ +"-0.0770,-0.0574,-0.0301,0.0090,0.0910,0.2238,0.4191"); + } + } + + + timing() { + timing_type : hold_rising; + related_pin : "A_BIST_CLK"; + + rise_constraint("SIG2SRAM_constraint_template") { + index_1("0.0080,0.0288,0.0616,0.1072,0.1920,0.3496,0.5952"); + index_2("0.0080,0.0288,0.0616,0.1072,0.1920,0.3496,0.5952"); + values ("0.3762,0.3605,0.3293,0.2863,0.2043,0.0637,-0.1629",\ +"0.3996,0.3801,0.3488,0.3020,0.2238,0.0832,-0.1395",\ +"0.4230,0.4074,0.3723,0.3293,0.2473,0.1105,-0.1121",\ +"0.4621,0.4465,0.4152,0.3762,0.2941,0.1535,-0.0691",\ +"0.5441,0.5285,0.4973,0.4465,0.3684,0.2316,0.0090",\ +"0.6848,0.6652,0.6301,0.5910,0.5129,0.3605,0.1496",\ +"0.9074,0.8918,0.8566,0.8215,0.7395,0.5910,0.3723"); + } + + fall_constraint("SIG2SRAM_constraint_template") { + index_1("0.0080,0.0288,0.0616,0.1072,0.1920,0.3496,0.5952"); + index_2("0.0080,0.0288,0.0616,0.1072,0.1920,0.3496,0.5952"); + values ("0.3762,0.3605,0.3332,0.2863,0.2043,0.0715,-0.1395",\ +"0.3996,0.3762,0.3488,0.3059,0.2238,0.0910,-0.1199",\ +"0.4270,0.4035,0.3762,0.3332,0.2512,0.1184,-0.0965",\ +"0.4699,0.4504,0.4191,0.3762,0.2941,0.1613,-0.0496",\ +"0.5441,0.5285,0.4973,0.4543,0.3762,0.2355,0.0324",\ +"0.6770,0.6613,0.6340,0.5949,0.5207,0.3762,0.1652",\ +"0.9074,0.8918,0.8605,0.8176,0.7395,0.6027,0.3918"); + } + } + } +bus(A_BIST_BM) { + bus_type : D_31_0; + direction : input ; + capacitance : 0.00347781 ; + max_transition : "0.5952" ; + pin(A_BIST_BM[31:0]) { + related_power_pin : VDD; + related_ground_pin : VSS; + internal_power() { + when : "A_BIST_MEN"; + rise_power("scalar"){ + values (0.0632); + } + fall_power("scalar"){ + values (0.0448); + } + } + internal_power() { + when : "!A_BIST_MEN"; + rise_power("scalar"){ + values (0.0895); + } + fall_power("scalar"){ + values (0.0291); + } + } + } + timing() { + timing_type : setup_rising; + related_pin : "A_BIST_CLK"; + when : "(A_BIST_WEN & A_BIST_MEN)" + sdf_cond : "A_BIST_RW_ACCESS" + + rise_constraint("SIG2SRAM_constraint_template") { + index_1("0.0080,0.0288,0.0616,0.1072,0.1920,0.3496,0.5952"); + index_2("0.0080,0.0288,0.0616,0.1072,0.1920,0.3496,0.5952"); + values ("-0.9175,-0.8980,-0.8726,-0.8296,-0.7486,-0.6031,-0.3804",\ +"-0.9255,-0.9060,-0.8806,-0.8376,-0.7566,-0.6111,-0.3884",\ +"-0.9345,-0.9150,-0.8896,-0.8467,-0.7656,-0.6201,-0.3974",\ +"-0.9477,-0.9282,-0.9028,-0.8598,-0.7788,-0.6332,-0.4106",\ +"-0.9720,-0.9524,-0.9271,-0.8841,-0.8030,-0.6575,-0.4349",\ +"-1.0025,-0.9830,-0.9576,-0.9146,-0.8336,-0.6880,-0.4654",\ +"-1.0839,-1.0644,-1.0390,-0.9961,-0.9150,-0.7695,-0.5468"); + } + + fall_constraint("SIG2SRAM_constraint_template") { + index_1("0.0080,0.0288,0.0616,0.1072,0.1920,0.3496,0.5952"); + index_2("0.0080,0.0288,0.0616,0.1072,0.1920,0.3496,0.5952"); + values ("-0.8550,-0.8374,-0.8101,-0.7710,-0.6880,-0.5523,-0.3404",\ +"-0.8630,-0.8455,-0.8181,-0.7791,-0.6960,-0.5603,-0.3484",\ +"-0.8720,-0.8545,-0.8271,-0.7881,-0.7051,-0.5693,-0.3574",\ +"-0.8852,-0.8676,-0.8403,-0.8012,-0.7182,-0.5825,-0.3706",\ +"-0.9095,-0.8919,-0.8646,-0.8255,-0.7425,-0.6067,-0.3948",\ +"-0.9400,-0.9224,-0.8951,-0.8560,-0.7730,-0.6373,-0.4253",\ +"-1.0214,-1.0039,-0.9765,-0.9375,-0.8544,-0.7187,-0.5068"); + } + } + + + timing() { + timing_type : hold_rising; + related_pin : "A_BIST_CLK"; + when : "(A_BIST_WEN & A_BIST_MEN)" + sdf_cond : "A_BIST_RW_ACCESS" + + rise_constraint("SIG2SRAM_constraint_template") { + index_1("0.0080,0.0288,0.0616,0.1072,0.1920,0.3496,0.5952"); + index_2("0.0080,0.0288,0.0616,0.1072,0.1920,0.3496,0.5952"); + values ("1.0343,1.0128,0.9884,0.9454,0.8654,0.7189,0.4962",\ +"1.0423,1.0209,0.9964,0.9535,0.8734,0.7269,0.5042",\ +"1.0513,1.0299,1.0054,0.9625,0.8824,0.7359,0.5133",\ +"1.0645,1.0430,1.0186,0.9756,0.8956,0.7491,0.5264",\ +"1.0888,1.0673,1.0429,0.9999,0.9198,0.7733,0.5507",\ +"1.1193,1.0978,1.0734,1.0304,0.9503,0.8039,0.5812",\ +"1.2007,1.1793,1.1548,1.1119,1.0318,0.8853,0.6627"); + } + + fall_constraint("SIG2SRAM_constraint_template") { + index_1("0.0080,0.0288,0.0616,0.1072,0.1920,0.3496,0.5952"); + index_2("0.0080,0.0288,0.0616,0.1072,0.1920,0.3496,0.5952"); + values ("0.9601,0.9425,0.9152,0.8761,0.7931,0.6564,0.4454",\ +"0.9681,0.9505,0.9232,0.8841,0.8011,0.6644,0.4535",\ +"0.9771,0.9595,0.9322,0.8931,0.8101,0.6734,0.4625",\ +"0.9903,0.9727,0.9454,0.9063,0.8233,0.6866,0.4756",\ +"1.0146,0.9970,0.9696,0.9306,0.8476,0.7108,0.4999",\ +"1.0451,1.0275,1.0002,0.9611,0.8781,0.7414,0.5304",\ +"1.1265,1.1089,1.0816,1.0425,0.9595,0.8228,0.6119"); + } + } +} + pin(A_BIST_CLK) { + direction : input; + capacitance : 0.00378957; + max_transition : "0.5952"; + clock : "true" ; + pin_func_type : active_rising ; + + timing () { + timing_type : "min_pulse_width"; + related_pin : "A_BIST_CLK"; + rise_constraint("CLKTRAN_constraint_template") { + index_1("0.008,0.5952"); + values("0.4,0.4"); + } + } + + related_power_pin : VDD; + related_ground_pin : VSS; + + internal_power() { + when : "!A_BIST_MEN & !A_BIST_WEN & !A_BIST_REN"; + rise_power("scalar"){ + values (0); + } + fall_power("scalar"){ + values (0); + } + } + internal_power() { + when : "!A_BIST_MEN & A_BIST_WEN & !A_BIST_REN"; + rise_power("scalar"){ + values (0.6568); + } + fall_power("scalar"){ + values (0); + } + } + internal_power() { + when : "A_BIST_MEN & A_BIST_WEN & !A_BIST_REN"; + rise_power("scalar"){ + values (46.0330); + } + fall_power("scalar"){ + values (0); + } + } + internal_power() { + when : "A_BIST_MEN & A_BIST_WEN & A_BIST_REN"; + rise_power("scalar"){ + values (49.3119); + } + fall_power("scalar"){ + values (0); + } + } + internal_power() { + when : "A_BIST_MEN & !A_BIST_WEN & A_BIST_REN"; + rise_power("scalar"){ + values (36.0779); + } + fall_power("scalar"){ + values (0); + } + } + internal_power() { + when : "!A_BIST_MEN & !A_BIST_WEN & A_BIST_REN"; + rise_power("scalar"){ + values (0.4418); + } + fall_power("scalar"){ + values (0); + } + } + internal_power() { + when : "!A_BIST_MEN & A_BIST_WEN & A_BIST_REN"; + rise_power("scalar"){ + values (1.1609); + } + fall_power("scalar"){ + values (0); + } + } + internal_power() { + when : "A_BIST_MEN & !A_BIST_WEN & !A_BIST_REN"; + rise_power("scalar"){ + values (0); + } + fall_power("scalar"){ + values (0); + } + } + } + bus(A_BIST_DIN) { + bus_type : D_31_0; + direction : input ; + capacitance : 0.00396073 ; + memory_write() { + address : A_BIST_ADDR ; + clocked_on : A_BIST_CLK; + } + + max_transition : "0.5952" ; + pin(A_BIST_DIN[31:0]) { + related_power_pin : VDD; + related_ground_pin : VSS; + internal_power() { + when : "A_BIST_MEN"; + rise_power("scalar"){ + values (0.0632); + } + fall_power("scalar"){ + values (0.0448); + } + } + internal_power() { + when : "!A_BIST_MEN"; + rise_power("scalar"){ + values (0.0895); + } + fall_power("scalar"){ + values (0.0291); + } + } + } + timing() { + timing_type : setup_rising; + related_pin : "A_BIST_CLK"; + when : "(A_BIST_WEN & A_BIST_MEN)"; + sdf_cond : "A_BIST_W_ACCESS"; + + rise_constraint("SIG2SRAM_constraint_template") { + index_1("0.0080,0.0288,0.0616,0.1072,0.1920,0.3496,0.5952"); + index_2("0.0080,0.0288,0.0616,0.1072,0.1920,0.3496,0.5952"); + values ("-0.9175,-0.8980,-0.8726,-0.8296,-0.7486,-0.6031,-0.3804",\ +"-0.9255,-0.9060,-0.8806,-0.8376,-0.7566,-0.6111,-0.3884",\ +"-0.9345,-0.9150,-0.8896,-0.8467,-0.7656,-0.6201,-0.3974",\ +"-0.9477,-0.9282,-0.9028,-0.8598,-0.7788,-0.6332,-0.4106",\ +"-0.9720,-0.9524,-0.9271,-0.8841,-0.8030,-0.6575,-0.4349",\ +"-1.0025,-0.9830,-0.9576,-0.9146,-0.8336,-0.6880,-0.4654",\ +"-1.0839,-1.0644,-1.0390,-0.9961,-0.9150,-0.7695,-0.5468"); + } + + fall_constraint("SIG2SRAM_constraint_template") { + index_1("0.0080,0.0288,0.0616,0.1072,0.1920,0.3496,0.5952"); + index_2("0.0080,0.0288,0.0616,0.1072,0.1920,0.3496,0.5952"); + values ("-0.8550,-0.8374,-0.8101,-0.7710,-0.6880,-0.5523,-0.3404",\ +"-0.8630,-0.8455,-0.8181,-0.7791,-0.6960,-0.5603,-0.3484",\ +"-0.8720,-0.8545,-0.8271,-0.7881,-0.7051,-0.5693,-0.3574",\ +"-0.8852,-0.8676,-0.8403,-0.8012,-0.7182,-0.5825,-0.3706",\ +"-0.9095,-0.8919,-0.8646,-0.8255,-0.7425,-0.6067,-0.3948",\ +"-0.9400,-0.9224,-0.8951,-0.8560,-0.7730,-0.6373,-0.4253",\ +"-1.0214,-1.0039,-0.9765,-0.9375,-0.8544,-0.7187,-0.5068"); + } + } + + timing() { + timing_type : hold_rising; + related_pin : "A_BIST_CLK"; + when : "(A_BIST_WEN & A_BIST_MEN)"; + sdf_cond : "A_BIST_W_ACCESS"; + + rise_constraint("SIG2SRAM_constraint_template") { + index_1("0.0080,0.0288,0.0616,0.1072,0.1920,0.3496,0.5952"); + index_2("0.0080,0.0288,0.0616,0.1072,0.1920,0.3496,0.5952"); + values ("1.0343,1.0128,0.9884,0.9454,0.8654,0.7189,0.4962",\ +"1.0423,1.0209,0.9964,0.9535,0.8734,0.7269,0.5042",\ +"1.0513,1.0299,1.0054,0.9625,0.8824,0.7359,0.5133",\ +"1.0645,1.0430,1.0186,0.9756,0.8956,0.7491,0.5264",\ +"1.0888,1.0673,1.0429,0.9999,0.9198,0.7733,0.5507",\ +"1.1193,1.0978,1.0734,1.0304,0.9503,0.8039,0.5812",\ +"1.2007,1.1793,1.1548,1.1119,1.0318,0.8853,0.6627"); + } + + fall_constraint("SIG2SRAM_constraint_template") { + index_1("0.0080,0.0288,0.0616,0.1072,0.1920,0.3496,0.5952"); + index_2("0.0080,0.0288,0.0616,0.1072,0.1920,0.3496,0.5952"); + values ("0.9601,0.9425,0.9152,0.8761,0.7931,0.6564,0.4454",\ +"0.9681,0.9505,0.9232,0.8841,0.8011,0.6644,0.4535",\ +"0.9771,0.9595,0.9322,0.8931,0.8101,0.6734,0.4625",\ +"0.9903,0.9727,0.9454,0.9063,0.8233,0.6866,0.4756",\ +"1.0146,0.9970,0.9696,0.9306,0.8476,0.7108,0.4999",\ +"1.0451,1.0275,1.0002,0.9611,0.8781,0.7414,0.5304",\ +"1.1265,1.1089,1.0816,1.0425,0.9595,0.8228,0.6119"); + } + } + } + +bus(A_DOUT) { + + bus_type : D_31_0; + direction : output ; + capacitance : 0 ; + max_capacitance : 0.064 ; + memory_read() { + address : A_ADDR ; + } + pin(A_DOUT[31:0]) { + related_power_pin : VDD; + related_ground_pin : VSS; + internal_power() { + rise_power("scalar") { + values (0); + } + fall_power("scalar") { + values (0); + } + } + } + timing() { + related_pin : "A_CLK"; + timing_type : rising_edge ; + timing_sense : non_unate ; + + cell_rise(SIG2SRAM_delay_template) { + index_1("0.0080,0.0288,0.0616,0.1072,0.1920,0.3496,0.5952"); + index_2("0.0008,0.0014,0.0051,0.0100,0.0339,0.0640"); + values ("7.4080,7.4114,7.4235,7.4375,7.4901,7.5479",\ +"7.4234,7.4268,7.4390,7.4529,7.5055,7.5633",\ +"7.4298,7.4331,7.4453,7.4592,7.5118,7.5697",\ +"7.4504,7.4538,7.4660,7.4799,7.5325,7.5903",\ +"7.4679,7.4713,7.4834,7.4974,7.5499,7.6078",\ +"7.5037,7.5070,7.5192,7.5331,7.5857,7.6435",\ +"7.5740,7.5774,7.5896,7.6035,7.6561,7.7139"); + } + cell_fall(SIG2SRAM_delay_template) { + index_1("0.0080,0.0288,0.0616,0.1072,0.1920,0.3496,0.5952"); + index_2("0.0008,0.0014,0.0051,0.0100,0.0339,0.0640"); + values ("7.2983,7.3004,7.3105,7.3222,7.3655,7.4093",\ +"7.3137,7.3159,7.3259,7.3376,7.3809,7.4248",\ +"7.3200,7.3222,7.3322,7.3439,7.3873,7.4311",\ +"7.3407,7.3429,7.3529,7.3646,7.4080,7.4518",\ +"7.3582,7.3603,7.3704,7.3821,7.4254,7.4692",\ +"7.3939,7.3961,7.4061,7.4178,7.4612,7.5050",\ +"7.4643,7.4665,7.4765,7.4882,7.5315,7.5754"); + } + + rise_transition(SRAM_load_template) { + index_1("0.0008,0.0014,0.0051,0.0100,0.0339,0.0640"); + values ("0.0560,0.0583,0.0696,0.0816,0.1519,0.2335"); + } + fall_transition(SRAM_load_template) { + index_1("0.0008,0.0014,0.0051,0.0100,0.0339,0.0640"); + values ("0.0428,0.0445,0.0538,0.0658,0.1181,0.1751"); + } + } +} + pin(B_DLY) { + direction : input ; + capacitance : 0.00387999 ; + max_transition : "1" ; + related_power_pin : VDD; + related_ground_pin : VSS; + internal_power() { + rise_power("scalar") { + values (0); + } + fall_power("scalar") { + values (0); + } + } + } + +bus(B_ADDR) { + bus_type : A_9_0; + direction : input ; + capacitance : 0.0129586 ; + pin(B_ADDR[0]) { + capacitance : 0.00588404 ; + } + pin(B_ADDR[1]) { + capacitance : 0.0080425 ; + } + pin(B_ADDR[2]) { + capacitance : 0.0112051 ; + } + pin(B_ADDR[3]) { + capacitance : 0.00706428 ; + } + pin(B_ADDR[4]) { + capacitance : 0.00656149 ; + } + pin(B_ADDR[5]) { + capacitance : 0.0111839 ; + } + pin(B_ADDR[6]) { + capacitance : 0.0140236 ; + } + pin(B_ADDR[7]) { + capacitance : 0.0111118 ; + } + pin(B_ADDR[8]) { + capacitance : 0.00954392 ; + } + max_transition : "0.5952" ; + pin(B_ADDR[9:0]) { + related_power_pin : VDD; + related_ground_pin : VSS; + internal_power() { + when : "B_MEN"; + rise_power("scalar"){ + values (0.0195); + } + fall_power("scalar"){ + values (0.0388); + } + } + internal_power() { + when : "!B_MEN"; + rise_power("scalar"){ + values (0.0129); + } + fall_power("scalar"){ + values (0.0238); + } + } + } + timing() { + timing_type : setup_rising; + related_pin : "B_CLK"; + when : "((B_WEN | B_REN)& B_MEN)" + sdf_cond : "B_RW_ACCESS" + + rise_constraint("SIG2SRAM_constraint_template") { + index_1("0.0080,0.0288,0.0616,0.1072,0.1920,0.3496,0.5952"); + index_2("0.0080,0.0288,0.0616,0.1072,0.1920,0.3496,0.5952"); + values ("-0.7371,-0.7176,-0.6863,-0.6434,-0.5652,-0.4168,-0.1980",\ +"-0.7566,-0.7371,-0.7059,-0.6629,-0.5848,-0.4363,-0.2137",\ +"-0.7879,-0.7645,-0.7332,-0.6902,-0.6121,-0.4637,-0.2449",\ +"-0.8309,-0.8074,-0.7762,-0.7332,-0.6551,-0.5066,-0.2879",\ +"-0.9051,-0.8895,-0.8543,-0.8113,-0.7332,-0.5887,-0.3660",\ +"-1.0418,-1.0262,-0.9949,-0.9480,-0.8699,-0.7293,-0.5027",\ +"-1.2684,-1.2449,-1.2176,-1.1707,-1.0965,-0.9480,-0.7293"); + } + + fall_constraint("SIG2SRAM_constraint_template") { + index_1("0.0080,0.0288,0.0616,0.1072,0.1920,0.3496,0.5952"); + index_2("0.0080,0.0288,0.0616,0.1072,0.1920,0.3496,0.5952"); + values ("-0.5926,-0.5730,-0.5418,-0.4988,-0.4246,-0.2879,-0.0730",\ +"-0.6121,-0.5926,-0.5613,-0.5223,-0.4441,-0.3074,-0.0887",\ +"-0.6395,-0.6199,-0.5926,-0.5496,-0.4715,-0.3348,-0.1160",\ +"-0.6863,-0.6668,-0.6355,-0.5965,-0.5184,-0.3777,-0.1590",\ +"-0.7605,-0.7410,-0.7137,-0.6746,-0.5926,-0.4559,-0.2410",\ +"-0.9012,-0.8816,-0.8504,-0.8113,-0.7332,-0.5926,-0.3895",\ +"-1.1238,-1.1043,-1.0769,-1.0379,-0.9559,-0.8191,-0.6004"); + } + } + + + timing() { + timing_type : hold_rising; + related_pin : "B_CLK"; + when : "((B_WEN | B_REN)& B_MEN)" + sdf_cond : "B_RW_ACCESS" + + rise_constraint("SIG2SRAM_constraint_template") { + index_1("0.0080,0.0288,0.0616,0.1072,0.1920,0.3496,0.5952"); + index_2("0.0080,0.0288,0.0616,0.1072,0.1920,0.3496,0.5952"); + values ("0.8488,0.8293,0.7980,0.7551,0.6730,0.5285,0.3098",\ +"0.8684,0.8488,0.8176,0.7746,0.6926,0.5480,0.3254",\ +"0.8996,0.8801,0.8449,0.8020,0.7238,0.5754,0.3527",\ +"0.9426,0.9191,0.8918,0.8488,0.7668,0.6223,0.3996",\ +"1.0168,1.0012,0.9699,0.9230,0.8449,0.7004,0.4777",\ +"1.1574,1.1379,1.1105,1.0598,0.9816,0.8371,0.6184",\ +"1.3801,1.3605,1.3254,1.2980,1.2043,1.0637,0.8371"); + } + + fall_constraint("SIG2SRAM_constraint_template") { + index_1("0.0080,0.0288,0.0616,0.1072,0.1920,0.3496,0.5952"); + index_2("0.0080,0.0288,0.0616,0.1072,0.1920,0.3496,0.5952"); + values ("0.6965,0.6770,0.6496,0.6066,0.5246,0.3918,0.1730",\ +"0.7160,0.6965,0.6652,0.6262,0.5441,0.4113,0.1965",\ +"0.7473,0.7277,0.6965,0.6535,0.5754,0.4426,0.2238",\ +"0.7863,0.7707,0.7395,0.7004,0.6223,0.4855,0.2629",\ +"0.8684,0.8449,0.8176,0.7785,0.7004,0.5637,0.3449",\ +"1.0051,0.9855,0.9855,0.9113,0.8332,0.7004,0.4895",\ +"1.2277,1.2082,1.1809,1.1379,1.0598,0.9230,0.7004"); + } + } +} +pin(B_WEN) { + direction : input ; + capacitance : 0.00313551 ; + max_transition : "0.5952" ; + related_power_pin : VDD; + related_ground_pin : VSS; + internal_power() { + when : "B_MEN"; + rise_power("scalar"){ + values (0.0268); + } + fall_power("scalar"){ + values (0.0213); + } + } + internal_power() { + when : "!B_MEN"; + rise_power("scalar"){ + values (0.0484); + } + fall_power("scalar"){ + values (0.0885); + } + } + timing() { + timing_type : setup_rising; + related_pin : "B_CLK"; + when : "B_MEN" + sdf_cond : "B_MEN" + + rise_constraint("SIG2SRAM_constraint_template") { + index_1("0.0080,0.0288,0.0616,0.1072,0.1920,0.3496,0.5952"); + index_2("0.0080,0.0288,0.0616,0.1072,0.1920,0.3496,0.5952"); + values ("0.3137,0.3332,0.3605,0.4035,0.4816,0.6223,0.8488",\ +"0.2980,0.3176,0.3410,0.3840,0.4660,0.6027,0.8293",\ +"0.2629,0.2824,0.3098,0.3527,0.4348,0.5754,0.7980",\ +"0.2199,0.2395,0.2668,0.3098,0.3918,0.5324,0.7590",\ +"0.1418,0.1613,0.1887,0.2316,0.3137,0.4348,0.6730",\ +"0.0012,0.0207,0.0520,0.0910,0.1730,0.3098,0.5285",\ +"-0.2215,-0.2020,-0.1746,-0.1277,-0.0496,0.0910,0.3098"); + } + + fall_constraint("SIG2SRAM_constraint_template") { + index_1("0.0080,0.0288,0.0616,0.1072,0.1920,0.3496,0.5952"); + index_2("0.0080,0.0288,0.0616,0.1072,0.1920,0.3496,0.5952"); + values ("0.4504,0.4699,0.4973,0.5324,0.6027,0.7355,0.9699",\ +"0.4309,0.4504,0.4777,0.5129,0.5910,0.7160,0.9504",\ +"0.3996,0.4191,0.4465,0.4816,0.5520,0.6848,0.9191",\ +"0.3605,0.3762,0.4035,0.4387,0.5168,0.6418,0.8723",\ +"0.2785,0.2980,0.3215,0.3605,0.4348,0.5637,0.7980",\ +"0.1379,0.1574,0.1809,0.2199,0.2980,0.4309,0.6457",\ +"-0.0809,-0.0613,-0.0340,0.0051,0.0832,0.2160,0.4191"); + } + } + + + timing() { + timing_type : hold_rising; + related_pin : "B_CLK"; + when : "B_MEN" + sdf_cond : "B_MEN" + + rise_constraint("SIG2SRAM_constraint_template") { + index_1("0.0080,0.0288,0.0616,0.1072,0.1920,0.3496,0.5952"); + index_2("0.0080,0.0288,0.0616,0.1072,0.1920,0.3496,0.5952"); + values ("0.3723,0.3527,0.3215,0.2785,0.1965,0.0559,-0.1668",\ +"0.3918,0.3723,0.3449,0.2980,0.2160,0.0754,-0.1473",\ +"0.4152,0.3996,0.3684,0.3254,0.2434,0.1066,-0.1199",\ +"0.4621,0.4465,0.4152,0.3723,0.2863,0.1496,-0.0730",\ +"0.5324,0.5207,0.4895,0.4465,0.3645,0.2199,0.0051",\ +"0.6770,0.6535,0.6301,0.5832,0.5090,0.3605,0.1418",\ +"0.9035,0.8879,0.8566,0.8137,0.7316,0.5871,0.3684"); + } + + fall_constraint("SIG2SRAM_constraint_template") { + index_1("0.0080,0.0288,0.0616,0.1072,0.1920,0.3496,0.5952"); + index_2("0.0080,0.0288,0.0616,0.1072,0.1920,0.3496,0.5952"); + values ("0.3762,0.3566,0.3293,0.2863,0.2043,0.0676,-0.1434",\ +"0.3957,0.3762,0.3488,0.3059,0.2238,0.0871,-0.1199",\ +"0.4230,0.4035,0.3723,0.3332,0.2512,0.1184,-0.0965",\ +"0.4660,0.4465,0.4191,0.3762,0.2941,0.1613,-0.0496",\ +"0.5324,0.5168,0.4973,0.4543,0.3723,0.2316,0.0285",\ +"0.6809,0.6613,0.6340,0.5910,0.5129,0.3645,0.1652",\ +"0.9113,0.8918,0.8605,0.8176,0.7395,0.5988,0.3879"); + } + } + } +pin(B_REN) { + direction : input ; + capacitance : 0.00381144 ; + max_transition : "0.5952" ; + related_power_pin : VDD; + related_ground_pin : VSS; + internal_power() { + when : "B_MEN"; + rise_power("scalar"){ + values (0.0263); + } + fall_power("scalar"){ + values (0.0112); + } + } + internal_power() { + when : "!B_MEN"; + rise_power("scalar"){ + values (0.0042); + } + fall_power("scalar"){ + values (0.0039); + } + } + timing() { + timing_type : setup_rising; + related_pin : "B_CLK"; + when : "B_MEN" + sdf_cond : "B_MEN" + + rise_constraint("SIG2SRAM_constraint_template") { + index_1("0.0080,0.0288,0.0616,0.1072,0.1920,0.3496,0.5952"); + index_2("0.0080,0.0288,0.0616,0.1072,0.1920,0.3496,0.5952"); + values ("-0.0770,-0.0574,-0.0262,0.0168,0.0949,0.2355,0.4582",\ +"-0.0965,-0.0770,-0.0457,-0.0027,0.0754,0.2160,0.4387",\ +"-0.1199,-0.1004,-0.0730,-0.0262,0.0520,0.1887,0.4113",\ +"-0.1590,-0.1434,-0.1160,-0.0730,0.0051,0.1457,0.3645",\ +"-0.2449,-0.2254,-0.1941,-0.1473,-0.0770,0.0676,0.2863",\ +"-0.3816,-0.3699,-0.3387,-0.2801,-0.2215,-0.0770,0.1457",\ +"-0.6121,-0.5926,-0.5613,-0.5145,-0.4363,-0.2996,-0.0730"); + } + + fall_constraint("SIG2SRAM_constraint_template") { + index_1("0.0080,0.0288,0.0616,0.1072,0.1920,0.3496,0.5952"); + index_2("0.0080,0.0288,0.0616,0.1072,0.1920,0.3496,0.5952"); + values ("0.1262,0.1457,0.1691,0.2121,0.2824,0.4191,0.6457",\ +"0.1105,0.1262,0.1496,0.1887,0.2629,0.3996,0.6262",\ +"0.0793,0.0949,0.1223,0.1652,0.2395,0.3684,0.5949",\ +"0.0363,0.0559,0.0793,0.1223,0.2004,0.3410,0.5520",\ +"-0.0457,-0.0262,0.0012,0.0441,0.1301,0.2629,0.4738",\ +"-0.1902,-0.1746,-0.1434,-0.1043,-0.0184,0.1223,0.3332",\ +"-0.4129,-0.3934,-0.3660,-0.3230,-0.2449,-0.1043,0.1105"); + } + } + + + timing() { + timing_type : hold_rising; + related_pin : "B_CLK"; + when : "B_MEN" + sdf_cond : "B_MEN" + + rise_constraint("SIG2SRAM_constraint_template") { + index_1("0.0080,0.0288,0.0616,0.1072,0.1920,0.3496,0.5952"); + index_2("0.0080,0.0288,0.0616,0.1072,0.1920,0.3496,0.5952"); + values ("0.4113,0.3918,0.3645,0.3176,0.2395,0.0988,-0.1238",\ +"0.4309,0.4113,0.3840,0.3371,0.2590,0.1184,-0.1043",\ +"0.4582,0.4387,0.4113,0.3645,0.2824,0.1457,-0.0770",\ +"0.5051,0.4816,0.4543,0.4074,0.3293,0.1887,-0.0340",\ +"0.5715,0.5598,0.5324,0.4895,0.4035,0.2512,0.0441",\ +"0.7043,0.7004,0.6730,0.6262,0.5402,0.3957,0.1809",\ +"0.9387,0.9270,0.8957,0.8527,0.7746,0.6262,0.4074"); + } + + fall_constraint("SIG2SRAM_constraint_template") { + index_1("0.0080,0.0288,0.0616,0.1072,0.1920,0.3496,0.5952"); + index_2("0.0080,0.0288,0.0616,0.1072,0.1920,0.3496,0.5952"); + values ("0.4152,0.3918,0.3645,0.3215,0.2395,0.1027,-0.1082",\ +"0.4309,0.4113,0.3801,0.3410,0.2590,0.1223,-0.0926",\ +"0.4582,0.4387,0.4074,0.3684,0.2863,0.1496,-0.0613",\ +"0.5012,0.4816,0.4504,0.4074,0.3293,0.1887,-0.0145",\ +"0.5715,0.5559,0.5285,0.4816,0.3996,0.2512,0.0598",\ +"0.7160,0.7004,0.6691,0.6262,0.5520,0.4035,0.2004",\ +"0.9387,0.9191,0.8957,0.8488,0.7707,0.6262,0.4113"); + } + } + } +pin(B_MEN) { + direction : input ; + capacitance : 0.00300347 ; + max_transition : "0.5952" ; + related_power_pin : VDD; + related_ground_pin : VSS; + internal_power() { + rise_power("scalar"){ + values (0.0005); + } + fall_power("scalar"){ + values (0.0301); + } + } + timing() { + timing_type : setup_rising; + related_pin : "B_CLK"; + + rise_constraint("SIG2SRAM_constraint_template") { + index_1("0.0080,0.0288,0.0616,0.1072,0.1920,0.3496,0.5952"); + index_2("0.0080,0.0288,0.0616,0.1072,0.1920,0.3496,0.5952"); + values ("0.3215,0.3449,0.3684,0.4113,0.4895,0.6301,0.8527",\ +"0.3059,0.3254,0.3527,0.3957,0.4738,0.6145,0.8371",\ +"0.2746,0.2941,0.3215,0.3645,0.4426,0.5871,0.8059",\ +"0.2316,0.2512,0.2785,0.3215,0.3996,0.5402,0.7629",\ +"0.1496,0.1730,0.1965,0.2395,0.3215,0.4660,0.6848",\ +"0.0090,0.0285,0.0598,0.1027,0.1809,0.3176,0.5402",\ +"-0.2098,-0.1902,-0.1668,-0.1199,-0.0418,0.0988,0.3137"); + } + + fall_constraint("SIG2SRAM_constraint_template") { + index_1("0.0080,0.0288,0.0616,0.1072,0.1920,0.3496,0.5952"); + index_2("0.0080,0.0288,0.0616,0.1072,0.1920,0.3496,0.5952"); + values ("0.4582,0.4738,0.5012,0.5363,0.6145,0.7395,0.9738",\ +"0.4387,0.4543,0.4816,0.5207,0.5910,0.7199,0.9582",\ +"0.4035,0.4230,0.4504,0.4855,0.5637,0.6887,0.9230",\ +"0.3645,0.3840,0.4074,0.4465,0.5285,0.6496,0.8840",\ +"0.2824,0.3020,0.3254,0.3645,0.4465,0.5715,0.7980",\ +"0.1418,0.1613,0.1887,0.2238,0.3020,0.4309,0.6496",\ +"-0.0770,-0.0574,-0.0301,0.0090,0.0910,0.2238,0.4191"); + } + } + + + timing() { + timing_type : hold_rising; + related_pin : "B_CLK"; + + rise_constraint("SIG2SRAM_constraint_template") { + index_1("0.0080,0.0288,0.0616,0.1072,0.1920,0.3496,0.5952"); + index_2("0.0080,0.0288,0.0616,0.1072,0.1920,0.3496,0.5952"); + values ("0.3762,0.3605,0.3293,0.2863,0.2043,0.0637,-0.1629",\ +"0.3996,0.3801,0.3488,0.3020,0.2238,0.0832,-0.1395",\ +"0.4230,0.4074,0.3723,0.3293,0.2473,0.1105,-0.1121",\ +"0.4621,0.4465,0.4152,0.3762,0.2941,0.1535,-0.0691",\ +"0.5441,0.5285,0.4973,0.4465,0.3684,0.2316,0.0090",\ +"0.6848,0.6652,0.6301,0.5910,0.5129,0.3605,0.1496",\ +"0.9074,0.8918,0.8566,0.8215,0.7395,0.5910,0.3723"); + } + + fall_constraint("SIG2SRAM_constraint_template") { + index_1("0.0080,0.0288,0.0616,0.1072,0.1920,0.3496,0.5952"); + index_2("0.0080,0.0288,0.0616,0.1072,0.1920,0.3496,0.5952"); + values ("0.3762,0.3605,0.3332,0.2863,0.2043,0.0715,-0.1395",\ +"0.3996,0.3762,0.3488,0.3059,0.2238,0.0910,-0.1199",\ +"0.4270,0.4035,0.3762,0.3332,0.2512,0.1184,-0.0965",\ +"0.4699,0.4504,0.4191,0.3762,0.2941,0.1613,-0.0496",\ +"0.5441,0.5285,0.4973,0.4543,0.3762,0.2355,0.0324",\ +"0.6770,0.6613,0.6340,0.5949,0.5207,0.3762,0.1652",\ +"0.9074,0.8918,0.8605,0.8176,0.7395,0.6027,0.3918"); + } + } + } +bus(B_BM) { + bus_type : D_31_0; + direction : input ; + capacitance : 0.00293202 ; + max_transition : "0.5952" ; + pin(B_BM[31:0]) { + related_power_pin : VDD; + related_ground_pin : VSS; + internal_power() { + when : "B_MEN"; + rise_power("scalar"){ + values (0.0632); + } + fall_power("scalar"){ + values (0.0448); + } + } + internal_power() { + when : "!B_MEN"; + rise_power("scalar"){ + values (0.0895); + } + fall_power("scalar"){ + values (0.0291); + } + } + } + timing() { + timing_type : setup_rising; + related_pin : "B_CLK"; + when : "(B_WEN & B_MEN)" + sdf_cond : "B_RW_ACCESS" + + rise_constraint("SIG2SRAM_constraint_template") { + index_1("0.0080,0.0288,0.0616,0.1072,0.1920,0.3496,0.5952"); + index_2("0.0080,0.0288,0.0616,0.1072,0.1920,0.3496,0.5952"); + values ("-0.9175,-0.8980,-0.8726,-0.8296,-0.7486,-0.6031,-0.3804",\ +"-0.9255,-0.9060,-0.8806,-0.8376,-0.7566,-0.6111,-0.3884",\ +"-0.9345,-0.9150,-0.8896,-0.8467,-0.7656,-0.6201,-0.3974",\ +"-0.9477,-0.9282,-0.9028,-0.8598,-0.7788,-0.6332,-0.4106",\ +"-0.9720,-0.9524,-0.9271,-0.8841,-0.8030,-0.6575,-0.4349",\ +"-1.0025,-0.9830,-0.9576,-0.9146,-0.8336,-0.6880,-0.4654",\ +"-1.0839,-1.0644,-1.0390,-0.9961,-0.9150,-0.7695,-0.5468"); + } + + fall_constraint("SIG2SRAM_constraint_template") { + index_1("0.0080,0.0288,0.0616,0.1072,0.1920,0.3496,0.5952"); + index_2("0.0080,0.0288,0.0616,0.1072,0.1920,0.3496,0.5952"); + values ("-0.8550,-0.8374,-0.8101,-0.7710,-0.6880,-0.5523,-0.3404",\ +"-0.8630,-0.8455,-0.8181,-0.7791,-0.6960,-0.5603,-0.3484",\ +"-0.8720,-0.8545,-0.8271,-0.7881,-0.7051,-0.5693,-0.3574",\ +"-0.8852,-0.8676,-0.8403,-0.8012,-0.7182,-0.5825,-0.3706",\ +"-0.9095,-0.8919,-0.8646,-0.8255,-0.7425,-0.6067,-0.3948",\ +"-0.9400,-0.9224,-0.8951,-0.8560,-0.7730,-0.6373,-0.4253",\ +"-1.0214,-1.0039,-0.9765,-0.9375,-0.8544,-0.7187,-0.5068"); + } + } + + + timing() { + timing_type : hold_rising; + related_pin : "B_CLK"; + when : "(B_WEN & B_MEN)" + sdf_cond : "B_RW_ACCESS" + + rise_constraint("SIG2SRAM_constraint_template") { + index_1("0.0080,0.0288,0.0616,0.1072,0.1920,0.3496,0.5952"); + index_2("0.0080,0.0288,0.0616,0.1072,0.1920,0.3496,0.5952"); + values ("1.0343,1.0128,0.9884,0.9454,0.8654,0.7189,0.4962",\ +"1.0423,1.0209,0.9964,0.9535,0.8734,0.7269,0.5042",\ +"1.0513,1.0299,1.0054,0.9625,0.8824,0.7359,0.5133",\ +"1.0645,1.0430,1.0186,0.9756,0.8956,0.7491,0.5264",\ +"1.0888,1.0673,1.0429,0.9999,0.9198,0.7733,0.5507",\ +"1.1193,1.0978,1.0734,1.0304,0.9503,0.8039,0.5812",\ +"1.2007,1.1793,1.1548,1.1119,1.0318,0.8853,0.6627"); + } + + fall_constraint("SIG2SRAM_constraint_template") { + index_1("0.0080,0.0288,0.0616,0.1072,0.1920,0.3496,0.5952"); + index_2("0.0080,0.0288,0.0616,0.1072,0.1920,0.3496,0.5952"); + values ("0.9601,0.9425,0.9152,0.8761,0.7931,0.6564,0.4454",\ +"0.9681,0.9505,0.9232,0.8841,0.8011,0.6644,0.4535",\ +"0.9771,0.9595,0.9322,0.8931,0.8101,0.6734,0.4625",\ +"0.9903,0.9727,0.9454,0.9063,0.8233,0.6866,0.4756",\ +"1.0146,0.9970,0.9696,0.9306,0.8476,0.7108,0.4999",\ +"1.0451,1.0275,1.0002,0.9611,0.8781,0.7414,0.5304",\ +"1.1265,1.1089,1.0816,1.0425,0.9595,0.8228,0.6119"); + } + } +} + pin(B_CLK) { + direction : input; + capacitance : 0.00378957; + max_transition : "0.5952"; + clock : "true" ; + pin_func_type : active_rising ; + + timing () { + timing_type : "min_pulse_width"; + related_pin : "B_CLK"; + rise_constraint("CLKTRAN_constraint_template") { + index_1("0.008,0.5952"); + values("0.4,0.4"); + } + } + + related_power_pin : VDD; + related_ground_pin : VSS; + + internal_power() { + when : "!B_MEN & !B_WEN & !B_REN"; + rise_power("scalar"){ + values (0); + } + fall_power("scalar"){ + values (0); + } + } + internal_power() { + when : "!B_MEN & B_WEN & !B_REN"; + rise_power("scalar"){ + values (0.6568); + } + fall_power("scalar"){ + values (0); + } + } + internal_power() { + when : "B_MEN & B_WEN & !B_REN"; + rise_power("scalar"){ + values (46.0330); + } + fall_power("scalar"){ + values (0); + } + } + internal_power() { + when : "B_MEN & B_WEN & B_REN"; + rise_power("scalar"){ + values (49.3119); + } + fall_power("scalar"){ + values (0); + } + } + internal_power() { + when : "B_MEN & !B_WEN & B_REN"; + rise_power("scalar"){ + values (36.0779); + } + fall_power("scalar"){ + values (0); + } + } + internal_power() { + when : "!B_MEN & !B_WEN & B_REN"; + rise_power("scalar"){ + values (0.4418); + } + fall_power("scalar"){ + values (0); + } + } + internal_power() { + when : "!B_MEN & B_WEN & B_REN"; + rise_power("scalar"){ + values (1.1609); + } + fall_power("scalar"){ + values (0); + } + } + internal_power() { + when : "B_MEN & !B_WEN & !B_REN"; + rise_power("scalar"){ + values (0); + } + fall_power("scalar"){ + values (0); + } + } + } + bus(B_DIN) { + bus_type : D_31_0; + direction : input ; + capacitance : 0.00460366 ; + memory_write() { + address : B_ADDR ; + clocked_on : B_CLK; + } + + max_transition : "0.5952" ; + pin(B_DIN[31:0]) { + related_power_pin : VDD; + related_ground_pin : VSS; + internal_power() { + when : "B_MEN"; + rise_power("scalar"){ + values (0.0632); + } + fall_power("scalar"){ + values (0.0448); + } + } + internal_power() { + when : "!B_MEN"; + rise_power("scalar"){ + values (0.0895); + } + fall_power("scalar"){ + values (0.0291); + } + } + } + timing() { + timing_type : setup_rising; + related_pin : "B_CLK"; + when : "(B_WEN & B_MEN)"; + sdf_cond : "B_W_ACCESS"; + + rise_constraint("SIG2SRAM_constraint_template") { + index_1("0.0080,0.0288,0.0616,0.1072,0.1920,0.3496,0.5952"); + index_2("0.0080,0.0288,0.0616,0.1072,0.1920,0.3496,0.5952"); + values ("-0.9175,-0.8980,-0.8726,-0.8296,-0.7486,-0.6031,-0.3804",\ +"-0.9255,-0.9060,-0.8806,-0.8376,-0.7566,-0.6111,-0.3884",\ +"-0.9345,-0.9150,-0.8896,-0.8467,-0.7656,-0.6201,-0.3974",\ +"-0.9477,-0.9282,-0.9028,-0.8598,-0.7788,-0.6332,-0.4106",\ +"-0.9720,-0.9524,-0.9271,-0.8841,-0.8030,-0.6575,-0.4349",\ +"-1.0025,-0.9830,-0.9576,-0.9146,-0.8336,-0.6880,-0.4654",\ +"-1.0839,-1.0644,-1.0390,-0.9961,-0.9150,-0.7695,-0.5468"); + } + + fall_constraint("SIG2SRAM_constraint_template") { + index_1("0.0080,0.0288,0.0616,0.1072,0.1920,0.3496,0.5952"); + index_2("0.0080,0.0288,0.0616,0.1072,0.1920,0.3496,0.5952"); + values ("-0.8550,-0.8374,-0.8101,-0.7710,-0.6880,-0.5523,-0.3404",\ +"-0.8630,-0.8455,-0.8181,-0.7791,-0.6960,-0.5603,-0.3484",\ +"-0.8720,-0.8545,-0.8271,-0.7881,-0.7051,-0.5693,-0.3574",\ +"-0.8852,-0.8676,-0.8403,-0.8012,-0.7182,-0.5825,-0.3706",\ +"-0.9095,-0.8919,-0.8646,-0.8255,-0.7425,-0.6067,-0.3948",\ +"-0.9400,-0.9224,-0.8951,-0.8560,-0.7730,-0.6373,-0.4253",\ +"-1.0214,-1.0039,-0.9765,-0.9375,-0.8544,-0.7187,-0.5068"); + } + } + + timing() { + timing_type : hold_rising; + related_pin : "B_CLK"; + when : "(B_WEN & B_MEN)"; + sdf_cond : "B_W_ACCESS"; + + rise_constraint("SIG2SRAM_constraint_template") { + index_1("0.0080,0.0288,0.0616,0.1072,0.1920,0.3496,0.5952"); + index_2("0.0080,0.0288,0.0616,0.1072,0.1920,0.3496,0.5952"); + values ("1.0343,1.0128,0.9884,0.9454,0.8654,0.7189,0.4962",\ +"1.0423,1.0209,0.9964,0.9535,0.8734,0.7269,0.5042",\ +"1.0513,1.0299,1.0054,0.9625,0.8824,0.7359,0.5133",\ +"1.0645,1.0430,1.0186,0.9756,0.8956,0.7491,0.5264",\ +"1.0888,1.0673,1.0429,0.9999,0.9198,0.7733,0.5507",\ +"1.1193,1.0978,1.0734,1.0304,0.9503,0.8039,0.5812",\ +"1.2007,1.1793,1.1548,1.1119,1.0318,0.8853,0.6627"); + } + + fall_constraint("SIG2SRAM_constraint_template") { + index_1("0.0080,0.0288,0.0616,0.1072,0.1920,0.3496,0.5952"); + index_2("0.0080,0.0288,0.0616,0.1072,0.1920,0.3496,0.5952"); + values ("0.9601,0.9425,0.9152,0.8761,0.7931,0.6564,0.4454",\ +"0.9681,0.9505,0.9232,0.8841,0.8011,0.6644,0.4535",\ +"0.9771,0.9595,0.9322,0.8931,0.8101,0.6734,0.4625",\ +"0.9903,0.9727,0.9454,0.9063,0.8233,0.6866,0.4756",\ +"1.0146,0.9970,0.9696,0.9306,0.8476,0.7108,0.4999",\ +"1.0451,1.0275,1.0002,0.9611,0.8781,0.7414,0.5304",\ +"1.1265,1.1089,1.0816,1.0425,0.9595,0.8228,0.6119"); + } + } + } + + pin(B_BIST_EN) { + direction : input ; + capacitance : 0.00387999 ; + max_transition : "1" ; + related_power_pin : VDD; + related_ground_pin : VSS; + internal_power() { + rise_power("scalar") { + values (0); + } + fall_power("scalar") { + values (0); + } + } + } + +bus(B_BIST_ADDR) { + bus_type : A_9_0; + direction : input ; + capacitance : 0.0129586 ; + pin(B_BIST_ADDR[0]) { + capacitance : 0.00588404 ; + } + pin(B_BIST_ADDR[1]) { + capacitance : 0.0080425 ; + } + pin(B_BIST_ADDR[2]) { + capacitance : 0.0112051 ; + } + pin(B_BIST_ADDR[3]) { + capacitance : 0.00706428 ; + } + pin(B_BIST_ADDR[4]) { + capacitance : 0.00656149 ; + } + pin(B_BIST_ADDR[5]) { + capacitance : 0.0111839 ; + } + pin(B_BIST_ADDR[6]) { + capacitance : 0.0140236 ; + } + pin(B_BIST_ADDR[7]) { + capacitance : 0.0111118 ; + } + pin(B_BIST_ADDR[8]) { + capacitance : 0.00954392 ; + } + max_transition : "0.5952" ; + pin(B_BIST_ADDR[9:0]) { + related_power_pin : VDD; + related_ground_pin : VSS; + internal_power() { + when : "B_BIST_MEN"; + rise_power("scalar"){ + values (0.0195); + } + fall_power("scalar"){ + values (0.0388); + } + } + internal_power() { + when : "!B_BIST_MEN"; + rise_power("scalar"){ + values (0.0129); + } + fall_power("scalar"){ + values (0.0238); + } + } + } + timing() { + timing_type : setup_rising; + related_pin : "B_BIST_CLK"; + when : "((B_BIST_WEN | B_BIST_REN)& B_BIST_MEN)" + sdf_cond : "B_BIST_RW_ACCESS" + + rise_constraint("SIG2SRAM_constraint_template") { + index_1("0.0080,0.0288,0.0616,0.1072,0.1920,0.3496,0.5952"); + index_2("0.0080,0.0288,0.0616,0.1072,0.1920,0.3496,0.5952"); + values ("-0.7371,-0.7176,-0.6863,-0.6434,-0.5652,-0.4168,-0.1980",\ +"-0.7566,-0.7371,-0.7059,-0.6629,-0.5848,-0.4363,-0.2137",\ +"-0.7879,-0.7645,-0.7332,-0.6902,-0.6121,-0.4637,-0.2449",\ +"-0.8309,-0.8074,-0.7762,-0.7332,-0.6551,-0.5066,-0.2879",\ +"-0.9051,-0.8895,-0.8543,-0.8113,-0.7332,-0.5887,-0.3660",\ +"-1.0418,-1.0262,-0.9949,-0.9480,-0.8699,-0.7293,-0.5027",\ +"-1.2684,-1.2449,-1.2176,-1.1707,-1.0965,-0.9480,-0.7293"); + } + + fall_constraint("SIG2SRAM_constraint_template") { + index_1("0.0080,0.0288,0.0616,0.1072,0.1920,0.3496,0.5952"); + index_2("0.0080,0.0288,0.0616,0.1072,0.1920,0.3496,0.5952"); + values ("-0.5926,-0.5730,-0.5418,-0.4988,-0.4246,-0.2879,-0.0730",\ +"-0.6121,-0.5926,-0.5613,-0.5223,-0.4441,-0.3074,-0.0887",\ +"-0.6395,-0.6199,-0.5926,-0.5496,-0.4715,-0.3348,-0.1160",\ +"-0.6863,-0.6668,-0.6355,-0.5965,-0.5184,-0.3777,-0.1590",\ +"-0.7605,-0.7410,-0.7137,-0.6746,-0.5926,-0.4559,-0.2410",\ +"-0.9012,-0.8816,-0.8504,-0.8113,-0.7332,-0.5926,-0.3895",\ +"-1.1238,-1.1043,-1.0769,-1.0379,-0.9559,-0.8191,-0.6004"); + } + } + + + timing() { + timing_type : hold_rising; + related_pin : "B_BIST_CLK"; + when : "((B_BIST_WEN | B_BIST_REN)& B_BIST_MEN)" + sdf_cond : "B_BIST_RW_ACCESS" + + rise_constraint("SIG2SRAM_constraint_template") { + index_1("0.0080,0.0288,0.0616,0.1072,0.1920,0.3496,0.5952"); + index_2("0.0080,0.0288,0.0616,0.1072,0.1920,0.3496,0.5952"); + values ("0.8488,0.8293,0.7980,0.7551,0.6730,0.5285,0.3098",\ +"0.8684,0.8488,0.8176,0.7746,0.6926,0.5480,0.3254",\ +"0.8996,0.8801,0.8449,0.8020,0.7238,0.5754,0.3527",\ +"0.9426,0.9191,0.8918,0.8488,0.7668,0.6223,0.3996",\ +"1.0168,1.0012,0.9699,0.9230,0.8449,0.7004,0.4777",\ +"1.1574,1.1379,1.1105,1.0598,0.9816,0.8371,0.6184",\ +"1.3801,1.3605,1.3254,1.2980,1.2043,1.0637,0.8371"); + } + + fall_constraint("SIG2SRAM_constraint_template") { + index_1("0.0080,0.0288,0.0616,0.1072,0.1920,0.3496,0.5952"); + index_2("0.0080,0.0288,0.0616,0.1072,0.1920,0.3496,0.5952"); + values ("0.6965,0.6770,0.6496,0.6066,0.5246,0.3918,0.1730",\ +"0.7160,0.6965,0.6652,0.6262,0.5441,0.4113,0.1965",\ +"0.7473,0.7277,0.6965,0.6535,0.5754,0.4426,0.2238",\ +"0.7863,0.7707,0.7395,0.7004,0.6223,0.4855,0.2629",\ +"0.8684,0.8449,0.8176,0.7785,0.7004,0.5637,0.3449",\ +"1.0051,0.9855,0.9855,0.9113,0.8332,0.7004,0.4895",\ +"1.2277,1.2082,1.1809,1.1379,1.0598,0.9230,0.7004"); + } + } +} +pin(B_BIST_WEN) { + direction : input ; + capacitance : 0.00313551 ; + max_transition : "0.5952" ; + related_power_pin : VDD; + related_ground_pin : VSS; + internal_power() { + when : "B_BIST_MEN"; + rise_power("scalar"){ + values (0.0268); + } + fall_power("scalar"){ + values (0.0213); + } + } + internal_power() { + when : "!B_BIST_MEN"; + rise_power("scalar"){ + values (0.0484); + } + fall_power("scalar"){ + values (0.0885); + } + } + timing() { + timing_type : setup_rising; + related_pin : "B_BIST_CLK"; + when : "B_BIST_MEN" + sdf_cond : "B_BIST_MEN" + + rise_constraint("SIG2SRAM_constraint_template") { + index_1("0.0080,0.0288,0.0616,0.1072,0.1920,0.3496,0.5952"); + index_2("0.0080,0.0288,0.0616,0.1072,0.1920,0.3496,0.5952"); + values ("0.3137,0.3332,0.3605,0.4035,0.4816,0.6223,0.8488",\ +"0.2980,0.3176,0.3410,0.3840,0.4660,0.6027,0.8293",\ +"0.2629,0.2824,0.3098,0.3527,0.4348,0.5754,0.7980",\ +"0.2199,0.2395,0.2668,0.3098,0.3918,0.5324,0.7590",\ +"0.1418,0.1613,0.1887,0.2316,0.3137,0.4348,0.6730",\ +"0.0012,0.0207,0.0520,0.0910,0.1730,0.3098,0.5285",\ +"-0.2215,-0.2020,-0.1746,-0.1277,-0.0496,0.0910,0.3098"); + } + + fall_constraint("SIG2SRAM_constraint_template") { + index_1("0.0080,0.0288,0.0616,0.1072,0.1920,0.3496,0.5952"); + index_2("0.0080,0.0288,0.0616,0.1072,0.1920,0.3496,0.5952"); + values ("0.4504,0.4699,0.4973,0.5324,0.6027,0.7355,0.9699",\ +"0.4309,0.4504,0.4777,0.5129,0.5910,0.7160,0.9504",\ +"0.3996,0.4191,0.4465,0.4816,0.5520,0.6848,0.9191",\ +"0.3605,0.3762,0.4035,0.4387,0.5168,0.6418,0.8723",\ +"0.2785,0.2980,0.3215,0.3605,0.4348,0.5637,0.7980",\ +"0.1379,0.1574,0.1809,0.2199,0.2980,0.4309,0.6457",\ +"-0.0809,-0.0613,-0.0340,0.0051,0.0832,0.2160,0.4191"); + } + } + + + timing() { + timing_type : hold_rising; + related_pin : "B_BIST_CLK"; + when : "B_BIST_MEN" + sdf_cond : "B_BIST_MEN" + + rise_constraint("SIG2SRAM_constraint_template") { + index_1("0.0080,0.0288,0.0616,0.1072,0.1920,0.3496,0.5952"); + index_2("0.0080,0.0288,0.0616,0.1072,0.1920,0.3496,0.5952"); + values ("0.3723,0.3527,0.3215,0.2785,0.1965,0.0559,-0.1668",\ +"0.3918,0.3723,0.3449,0.2980,0.2160,0.0754,-0.1473",\ +"0.4152,0.3996,0.3684,0.3254,0.2434,0.1066,-0.1199",\ +"0.4621,0.4465,0.4152,0.3723,0.2863,0.1496,-0.0730",\ +"0.5324,0.5207,0.4895,0.4465,0.3645,0.2199,0.0051",\ +"0.6770,0.6535,0.6301,0.5832,0.5090,0.3605,0.1418",\ +"0.9035,0.8879,0.8566,0.8137,0.7316,0.5871,0.3684"); + } + + fall_constraint("SIG2SRAM_constraint_template") { + index_1("0.0080,0.0288,0.0616,0.1072,0.1920,0.3496,0.5952"); + index_2("0.0080,0.0288,0.0616,0.1072,0.1920,0.3496,0.5952"); + values ("0.3762,0.3566,0.3293,0.2863,0.2043,0.0676,-0.1434",\ +"0.3957,0.3762,0.3488,0.3059,0.2238,0.0871,-0.1199",\ +"0.4230,0.4035,0.3723,0.3332,0.2512,0.1184,-0.0965",\ +"0.4660,0.4465,0.4191,0.3762,0.2941,0.1613,-0.0496",\ +"0.5324,0.5168,0.4973,0.4543,0.3723,0.2316,0.0285",\ +"0.6809,0.6613,0.6340,0.5910,0.5129,0.3645,0.1652",\ +"0.9113,0.8918,0.8605,0.8176,0.7395,0.5988,0.3879"); + } + } + } +pin(B_BIST_REN) { + direction : input ; + capacitance : 0.00381144 ; + max_transition : "0.5952" ; + related_power_pin : VDD; + related_ground_pin : VSS; + internal_power() { + when : "B_BIST_MEN"; + rise_power("scalar"){ + values (0.0263); + } + fall_power("scalar"){ + values (0.0112); + } + } + internal_power() { + when : "!B_BIST_MEN"; + rise_power("scalar"){ + values (0.0042); + } + fall_power("scalar"){ + values (0.0039); + } + } + timing() { + timing_type : setup_rising; + related_pin : "B_BIST_CLK"; + when : "B_BIST_MEN" + sdf_cond : "B_BIST_MEN" + + rise_constraint("SIG2SRAM_constraint_template") { + index_1("0.0080,0.0288,0.0616,0.1072,0.1920,0.3496,0.5952"); + index_2("0.0080,0.0288,0.0616,0.1072,0.1920,0.3496,0.5952"); + values ("-0.0770,-0.0574,-0.0262,0.0168,0.0949,0.2355,0.4582",\ +"-0.0965,-0.0770,-0.0457,-0.0027,0.0754,0.2160,0.4387",\ +"-0.1199,-0.1004,-0.0730,-0.0262,0.0520,0.1887,0.4113",\ +"-0.1590,-0.1434,-0.1160,-0.0730,0.0051,0.1457,0.3645",\ +"-0.2449,-0.2254,-0.1941,-0.1473,-0.0770,0.0676,0.2863",\ +"-0.3816,-0.3699,-0.3387,-0.2801,-0.2215,-0.0770,0.1457",\ +"-0.6121,-0.5926,-0.5613,-0.5145,-0.4363,-0.2996,-0.0730"); + } + + fall_constraint("SIG2SRAM_constraint_template") { + index_1("0.0080,0.0288,0.0616,0.1072,0.1920,0.3496,0.5952"); + index_2("0.0080,0.0288,0.0616,0.1072,0.1920,0.3496,0.5952"); + values ("0.1262,0.1457,0.1691,0.2121,0.2824,0.4191,0.6457",\ +"0.1105,0.1262,0.1496,0.1887,0.2629,0.3996,0.6262",\ +"0.0793,0.0949,0.1223,0.1652,0.2395,0.3684,0.5949",\ +"0.0363,0.0559,0.0793,0.1223,0.2004,0.3410,0.5520",\ +"-0.0457,-0.0262,0.0012,0.0441,0.1301,0.2629,0.4738",\ +"-0.1902,-0.1746,-0.1434,-0.1043,-0.0184,0.1223,0.3332",\ +"-0.4129,-0.3934,-0.3660,-0.3230,-0.2449,-0.1043,0.1105"); + } + } + + + timing() { + timing_type : hold_rising; + related_pin : "B_BIST_CLK"; + when : "B_BIST_MEN" + sdf_cond : "B_BIST_MEN" + + rise_constraint("SIG2SRAM_constraint_template") { + index_1("0.0080,0.0288,0.0616,0.1072,0.1920,0.3496,0.5952"); + index_2("0.0080,0.0288,0.0616,0.1072,0.1920,0.3496,0.5952"); + values ("0.4113,0.3918,0.3645,0.3176,0.2395,0.0988,-0.1238",\ +"0.4309,0.4113,0.3840,0.3371,0.2590,0.1184,-0.1043",\ +"0.4582,0.4387,0.4113,0.3645,0.2824,0.1457,-0.0770",\ +"0.5051,0.4816,0.4543,0.4074,0.3293,0.1887,-0.0340",\ +"0.5715,0.5598,0.5324,0.4895,0.4035,0.2512,0.0441",\ +"0.7043,0.7004,0.6730,0.6262,0.5402,0.3957,0.1809",\ +"0.9387,0.9270,0.8957,0.8527,0.7746,0.6262,0.4074"); + } + + fall_constraint("SIG2SRAM_constraint_template") { + index_1("0.0080,0.0288,0.0616,0.1072,0.1920,0.3496,0.5952"); + index_2("0.0080,0.0288,0.0616,0.1072,0.1920,0.3496,0.5952"); + values ("0.4152,0.3918,0.3645,0.3215,0.2395,0.1027,-0.1082",\ +"0.4309,0.4113,0.3801,0.3410,0.2590,0.1223,-0.0926",\ +"0.4582,0.4387,0.4074,0.3684,0.2863,0.1496,-0.0613",\ +"0.5012,0.4816,0.4504,0.4074,0.3293,0.1887,-0.0145",\ +"0.5715,0.5559,0.5285,0.4816,0.3996,0.2512,0.0598",\ +"0.7160,0.7004,0.6691,0.6262,0.5520,0.4035,0.2004",\ +"0.9387,0.9191,0.8957,0.8488,0.7707,0.6262,0.4113"); + } + } + } +pin(B_BIST_MEN) { + direction : input ; + capacitance : 0.00300347 ; + max_transition : "0.5952" ; + related_power_pin : VDD; + related_ground_pin : VSS; + internal_power() { + rise_power("scalar"){ + values (0.0005); + } + fall_power("scalar"){ + values (0.0301); + } + } + timing() { + timing_type : setup_rising; + related_pin : "B_BIST_CLK"; + + rise_constraint("SIG2SRAM_constraint_template") { + index_1("0.0080,0.0288,0.0616,0.1072,0.1920,0.3496,0.5952"); + index_2("0.0080,0.0288,0.0616,0.1072,0.1920,0.3496,0.5952"); + values ("0.3215,0.3449,0.3684,0.4113,0.4895,0.6301,0.8527",\ +"0.3059,0.3254,0.3527,0.3957,0.4738,0.6145,0.8371",\ +"0.2746,0.2941,0.3215,0.3645,0.4426,0.5871,0.8059",\ +"0.2316,0.2512,0.2785,0.3215,0.3996,0.5402,0.7629",\ +"0.1496,0.1730,0.1965,0.2395,0.3215,0.4660,0.6848",\ +"0.0090,0.0285,0.0598,0.1027,0.1809,0.3176,0.5402",\ +"-0.2098,-0.1902,-0.1668,-0.1199,-0.0418,0.0988,0.3137"); + } + + fall_constraint("SIG2SRAM_constraint_template") { + index_1("0.0080,0.0288,0.0616,0.1072,0.1920,0.3496,0.5952"); + index_2("0.0080,0.0288,0.0616,0.1072,0.1920,0.3496,0.5952"); + values ("0.4582,0.4738,0.5012,0.5363,0.6145,0.7395,0.9738",\ +"0.4387,0.4543,0.4816,0.5207,0.5910,0.7199,0.9582",\ +"0.4035,0.4230,0.4504,0.4855,0.5637,0.6887,0.9230",\ +"0.3645,0.3840,0.4074,0.4465,0.5285,0.6496,0.8840",\ +"0.2824,0.3020,0.3254,0.3645,0.4465,0.5715,0.7980",\ +"0.1418,0.1613,0.1887,0.2238,0.3020,0.4309,0.6496",\ +"-0.0770,-0.0574,-0.0301,0.0090,0.0910,0.2238,0.4191"); + } + } + + + timing() { + timing_type : hold_rising; + related_pin : "B_BIST_CLK"; + + rise_constraint("SIG2SRAM_constraint_template") { + index_1("0.0080,0.0288,0.0616,0.1072,0.1920,0.3496,0.5952"); + index_2("0.0080,0.0288,0.0616,0.1072,0.1920,0.3496,0.5952"); + values ("0.3762,0.3605,0.3293,0.2863,0.2043,0.0637,-0.1629",\ +"0.3996,0.3801,0.3488,0.3020,0.2238,0.0832,-0.1395",\ +"0.4230,0.4074,0.3723,0.3293,0.2473,0.1105,-0.1121",\ +"0.4621,0.4465,0.4152,0.3762,0.2941,0.1535,-0.0691",\ +"0.5441,0.5285,0.4973,0.4465,0.3684,0.2316,0.0090",\ +"0.6848,0.6652,0.6301,0.5910,0.5129,0.3605,0.1496",\ +"0.9074,0.8918,0.8566,0.8215,0.7395,0.5910,0.3723"); + } + + fall_constraint("SIG2SRAM_constraint_template") { + index_1("0.0080,0.0288,0.0616,0.1072,0.1920,0.3496,0.5952"); + index_2("0.0080,0.0288,0.0616,0.1072,0.1920,0.3496,0.5952"); + values ("0.3762,0.3605,0.3332,0.2863,0.2043,0.0715,-0.1395",\ +"0.3996,0.3762,0.3488,0.3059,0.2238,0.0910,-0.1199",\ +"0.4270,0.4035,0.3762,0.3332,0.2512,0.1184,-0.0965",\ +"0.4699,0.4504,0.4191,0.3762,0.2941,0.1613,-0.0496",\ +"0.5441,0.5285,0.4973,0.4543,0.3762,0.2355,0.0324",\ +"0.6770,0.6613,0.6340,0.5949,0.5207,0.3762,0.1652",\ +"0.9074,0.8918,0.8605,0.8176,0.7395,0.6027,0.3918"); + } + } + } +bus(B_BIST_BM) { + bus_type : D_31_0; + direction : input ; + capacitance : 0.00261869 ; + max_transition : "0.5952" ; + pin(B_BIST_BM[31:0]) { + related_power_pin : VDD; + related_ground_pin : VSS; + internal_power() { + when : "B_BIST_MEN"; + rise_power("scalar"){ + values (0.0632); + } + fall_power("scalar"){ + values (0.0448); + } + } + internal_power() { + when : "!B_BIST_MEN"; + rise_power("scalar"){ + values (0.0895); + } + fall_power("scalar"){ + values (0.0291); + } + } + } + timing() { + timing_type : setup_rising; + related_pin : "B_BIST_CLK"; + when : "(B_BIST_WEN & B_BIST_MEN)" + sdf_cond : "B_BIST_RW_ACCESS" + + rise_constraint("SIG2SRAM_constraint_template") { + index_1("0.0080,0.0288,0.0616,0.1072,0.1920,0.3496,0.5952"); + index_2("0.0080,0.0288,0.0616,0.1072,0.1920,0.3496,0.5952"); + values ("-0.9175,-0.8980,-0.8726,-0.8296,-0.7486,-0.6031,-0.3804",\ +"-0.9255,-0.9060,-0.8806,-0.8376,-0.7566,-0.6111,-0.3884",\ +"-0.9345,-0.9150,-0.8896,-0.8467,-0.7656,-0.6201,-0.3974",\ +"-0.9477,-0.9282,-0.9028,-0.8598,-0.7788,-0.6332,-0.4106",\ +"-0.9720,-0.9524,-0.9271,-0.8841,-0.8030,-0.6575,-0.4349",\ +"-1.0025,-0.9830,-0.9576,-0.9146,-0.8336,-0.6880,-0.4654",\ +"-1.0839,-1.0644,-1.0390,-0.9961,-0.9150,-0.7695,-0.5468"); + } + + fall_constraint("SIG2SRAM_constraint_template") { + index_1("0.0080,0.0288,0.0616,0.1072,0.1920,0.3496,0.5952"); + index_2("0.0080,0.0288,0.0616,0.1072,0.1920,0.3496,0.5952"); + values ("-0.8550,-0.8374,-0.8101,-0.7710,-0.6880,-0.5523,-0.3404",\ +"-0.8630,-0.8455,-0.8181,-0.7791,-0.6960,-0.5603,-0.3484",\ +"-0.8720,-0.8545,-0.8271,-0.7881,-0.7051,-0.5693,-0.3574",\ +"-0.8852,-0.8676,-0.8403,-0.8012,-0.7182,-0.5825,-0.3706",\ +"-0.9095,-0.8919,-0.8646,-0.8255,-0.7425,-0.6067,-0.3948",\ +"-0.9400,-0.9224,-0.8951,-0.8560,-0.7730,-0.6373,-0.4253",\ +"-1.0214,-1.0039,-0.9765,-0.9375,-0.8544,-0.7187,-0.5068"); + } + } + + + timing() { + timing_type : hold_rising; + related_pin : "B_BIST_CLK"; + when : "(B_BIST_WEN & B_BIST_MEN)" + sdf_cond : "B_BIST_RW_ACCESS" + + rise_constraint("SIG2SRAM_constraint_template") { + index_1("0.0080,0.0288,0.0616,0.1072,0.1920,0.3496,0.5952"); + index_2("0.0080,0.0288,0.0616,0.1072,0.1920,0.3496,0.5952"); + values ("1.0343,1.0128,0.9884,0.9454,0.8654,0.7189,0.4962",\ +"1.0423,1.0209,0.9964,0.9535,0.8734,0.7269,0.5042",\ +"1.0513,1.0299,1.0054,0.9625,0.8824,0.7359,0.5133",\ +"1.0645,1.0430,1.0186,0.9756,0.8956,0.7491,0.5264",\ +"1.0888,1.0673,1.0429,0.9999,0.9198,0.7733,0.5507",\ +"1.1193,1.0978,1.0734,1.0304,0.9503,0.8039,0.5812",\ +"1.2007,1.1793,1.1548,1.1119,1.0318,0.8853,0.6627"); + } + + fall_constraint("SIG2SRAM_constraint_template") { + index_1("0.0080,0.0288,0.0616,0.1072,0.1920,0.3496,0.5952"); + index_2("0.0080,0.0288,0.0616,0.1072,0.1920,0.3496,0.5952"); + values ("0.9601,0.9425,0.9152,0.8761,0.7931,0.6564,0.4454",\ +"0.9681,0.9505,0.9232,0.8841,0.8011,0.6644,0.4535",\ +"0.9771,0.9595,0.9322,0.8931,0.8101,0.6734,0.4625",\ +"0.9903,0.9727,0.9454,0.9063,0.8233,0.6866,0.4756",\ +"1.0146,0.9970,0.9696,0.9306,0.8476,0.7108,0.4999",\ +"1.0451,1.0275,1.0002,0.9611,0.8781,0.7414,0.5304",\ +"1.1265,1.1089,1.0816,1.0425,0.9595,0.8228,0.6119"); + } + } +} + pin(B_BIST_CLK) { + direction : input; + capacitance : 0.00378957; + max_transition : "0.5952"; + clock : "true" ; + pin_func_type : active_rising ; + + timing () { + timing_type : "min_pulse_width"; + related_pin : "B_BIST_CLK"; + rise_constraint("CLKTRAN_constraint_template") { + index_1("0.008,0.5952"); + values("0.4,0.4"); + } + } + + related_power_pin : VDD; + related_ground_pin : VSS; + + internal_power() { + when : "!B_BIST_MEN & !B_BIST_WEN & !B_BIST_REN"; + rise_power("scalar"){ + values (0); + } + fall_power("scalar"){ + values (0); + } + } + internal_power() { + when : "!B_BIST_MEN & B_BIST_WEN & !B_BIST_REN"; + rise_power("scalar"){ + values (0.6568); + } + fall_power("scalar"){ + values (0); + } + } + internal_power() { + when : "B_BIST_MEN & B_BIST_WEN & !B_BIST_REN"; + rise_power("scalar"){ + values (46.0330); + } + fall_power("scalar"){ + values (0); + } + } + internal_power() { + when : "B_BIST_MEN & B_BIST_WEN & B_BIST_REN"; + rise_power("scalar"){ + values (49.3119); + } + fall_power("scalar"){ + values (0); + } + } + internal_power() { + when : "B_BIST_MEN & !B_BIST_WEN & B_BIST_REN"; + rise_power("scalar"){ + values (36.0779); + } + fall_power("scalar"){ + values (0); + } + } + internal_power() { + when : "!B_BIST_MEN & !B_BIST_WEN & B_BIST_REN"; + rise_power("scalar"){ + values (0.4418); + } + fall_power("scalar"){ + values (0); + } + } + internal_power() { + when : "!B_BIST_MEN & B_BIST_WEN & B_BIST_REN"; + rise_power("scalar"){ + values (1.1609); + } + fall_power("scalar"){ + values (0); + } + } + internal_power() { + when : "B_BIST_MEN & !B_BIST_WEN & !B_BIST_REN"; + rise_power("scalar"){ + values (0); + } + fall_power("scalar"){ + values (0); + } + } + } + bus(B_BIST_DIN) { + bus_type : D_31_0; + direction : input ; + capacitance : 0.00416317 ; + memory_write() { + address : B_BIST_ADDR ; + clocked_on : B_BIST_CLK; + } + + max_transition : "0.5952" ; + pin(B_BIST_DIN[31:0]) { + related_power_pin : VDD; + related_ground_pin : VSS; + internal_power() { + when : "B_BIST_MEN"; + rise_power("scalar"){ + values (0.0632); + } + fall_power("scalar"){ + values (0.0448); + } + } + internal_power() { + when : "!B_BIST_MEN"; + rise_power("scalar"){ + values (0.0895); + } + fall_power("scalar"){ + values (0.0291); + } + } + } + timing() { + timing_type : setup_rising; + related_pin : "B_BIST_CLK"; + when : "(B_BIST_WEN & B_BIST_MEN)"; + sdf_cond : "B_BIST_W_ACCESS"; + + rise_constraint("SIG2SRAM_constraint_template") { + index_1("0.0080,0.0288,0.0616,0.1072,0.1920,0.3496,0.5952"); + index_2("0.0080,0.0288,0.0616,0.1072,0.1920,0.3496,0.5952"); + values ("-0.9175,-0.8980,-0.8726,-0.8296,-0.7486,-0.6031,-0.3804",\ +"-0.9255,-0.9060,-0.8806,-0.8376,-0.7566,-0.6111,-0.3884",\ +"-0.9345,-0.9150,-0.8896,-0.8467,-0.7656,-0.6201,-0.3974",\ +"-0.9477,-0.9282,-0.9028,-0.8598,-0.7788,-0.6332,-0.4106",\ +"-0.9720,-0.9524,-0.9271,-0.8841,-0.8030,-0.6575,-0.4349",\ +"-1.0025,-0.9830,-0.9576,-0.9146,-0.8336,-0.6880,-0.4654",\ +"-1.0839,-1.0644,-1.0390,-0.9961,-0.9150,-0.7695,-0.5468"); + } + + fall_constraint("SIG2SRAM_constraint_template") { + index_1("0.0080,0.0288,0.0616,0.1072,0.1920,0.3496,0.5952"); + index_2("0.0080,0.0288,0.0616,0.1072,0.1920,0.3496,0.5952"); + values ("-0.8550,-0.8374,-0.8101,-0.7710,-0.6880,-0.5523,-0.3404",\ +"-0.8630,-0.8455,-0.8181,-0.7791,-0.6960,-0.5603,-0.3484",\ +"-0.8720,-0.8545,-0.8271,-0.7881,-0.7051,-0.5693,-0.3574",\ +"-0.8852,-0.8676,-0.8403,-0.8012,-0.7182,-0.5825,-0.3706",\ +"-0.9095,-0.8919,-0.8646,-0.8255,-0.7425,-0.6067,-0.3948",\ +"-0.9400,-0.9224,-0.8951,-0.8560,-0.7730,-0.6373,-0.4253",\ +"-1.0214,-1.0039,-0.9765,-0.9375,-0.8544,-0.7187,-0.5068"); + } + } + + timing() { + timing_type : hold_rising; + related_pin : "B_BIST_CLK"; + when : "(B_BIST_WEN & B_BIST_MEN)"; + sdf_cond : "B_BIST_W_ACCESS"; + + rise_constraint("SIG2SRAM_constraint_template") { + index_1("0.0080,0.0288,0.0616,0.1072,0.1920,0.3496,0.5952"); + index_2("0.0080,0.0288,0.0616,0.1072,0.1920,0.3496,0.5952"); + values ("1.0343,1.0128,0.9884,0.9454,0.8654,0.7189,0.4962",\ +"1.0423,1.0209,0.9964,0.9535,0.8734,0.7269,0.5042",\ +"1.0513,1.0299,1.0054,0.9625,0.8824,0.7359,0.5133",\ +"1.0645,1.0430,1.0186,0.9756,0.8956,0.7491,0.5264",\ +"1.0888,1.0673,1.0429,0.9999,0.9198,0.7733,0.5507",\ +"1.1193,1.0978,1.0734,1.0304,0.9503,0.8039,0.5812",\ +"1.2007,1.1793,1.1548,1.1119,1.0318,0.8853,0.6627"); + } + + fall_constraint("SIG2SRAM_constraint_template") { + index_1("0.0080,0.0288,0.0616,0.1072,0.1920,0.3496,0.5952"); + index_2("0.0080,0.0288,0.0616,0.1072,0.1920,0.3496,0.5952"); + values ("0.9601,0.9425,0.9152,0.8761,0.7931,0.6564,0.4454",\ +"0.9681,0.9505,0.9232,0.8841,0.8011,0.6644,0.4535",\ +"0.9771,0.9595,0.9322,0.8931,0.8101,0.6734,0.4625",\ +"0.9903,0.9727,0.9454,0.9063,0.8233,0.6866,0.4756",\ +"1.0146,0.9970,0.9696,0.9306,0.8476,0.7108,0.4999",\ +"1.0451,1.0275,1.0002,0.9611,0.8781,0.7414,0.5304",\ +"1.1265,1.1089,1.0816,1.0425,0.9595,0.8228,0.6119"); + } + } + } + +bus(B_DOUT) { + + bus_type : D_31_0; + direction : output ; + capacitance : 0 ; + max_capacitance : 0.064 ; + memory_read() { + address : B_ADDR ; + } + pin(B_DOUT[31:0]) { + related_power_pin : VDD; + related_ground_pin : VSS; + internal_power() { + rise_power("scalar") { + values (0); + } + fall_power("scalar") { + values (0); + } + } + } + timing() { + related_pin : "B_CLK"; + timing_type : rising_edge ; + timing_sense : non_unate ; + + cell_rise(SIG2SRAM_delay_template) { + index_1("0.0080,0.0288,0.0616,0.1072,0.1920,0.3496,0.5952"); + index_2("0.0008,0.0014,0.0051,0.0100,0.0339,0.0640"); + values ("7.4080,7.4114,7.4235,7.4375,7.4901,7.5479",\ +"7.4234,7.4268,7.4390,7.4529,7.5055,7.5633",\ +"7.4298,7.4331,7.4453,7.4592,7.5118,7.5697",\ +"7.4504,7.4538,7.4660,7.4799,7.5325,7.5903",\ +"7.4679,7.4713,7.4834,7.4974,7.5499,7.6078",\ +"7.5037,7.5070,7.5192,7.5331,7.5857,7.6435",\ +"7.5740,7.5774,7.5896,7.6035,7.6561,7.7139"); + } + cell_fall(SIG2SRAM_delay_template) { + index_1("0.0080,0.0288,0.0616,0.1072,0.1920,0.3496,0.5952"); + index_2("0.0008,0.0014,0.0051,0.0100,0.0339,0.0640"); + values ("7.2983,7.3004,7.3105,7.3222,7.3655,7.4093",\ +"7.3137,7.3159,7.3259,7.3376,7.3809,7.4248",\ +"7.3200,7.3222,7.3322,7.3439,7.3873,7.4311",\ +"7.3407,7.3429,7.3529,7.3646,7.4080,7.4518",\ +"7.3582,7.3603,7.3704,7.3821,7.4254,7.4692",\ +"7.3939,7.3961,7.4061,7.4178,7.4612,7.5050",\ +"7.4643,7.4665,7.4765,7.4882,7.5315,7.5754"); + } + + rise_transition(SRAM_load_template) { + index_1("0.0008,0.0014,0.0051,0.0100,0.0339,0.0640"); + values ("0.0560,0.0583,0.0696,0.0816,0.1519,0.2335"); + } + fall_transition(SRAM_load_template) { + index_1("0.0008,0.0014,0.0051,0.0100,0.0339,0.0640"); + values ("0.0428,0.0445,0.0538,0.0658,0.1181,0.1751"); + } + } +} +cell_leakage_power : 3812.6285; +} +} diff --git a/flow/platforms/ihp-sg13g2/lib/RM_IHPSG13_2P_1024x32_c2_bm_bist_typ_1p20V_25C.lib b/flow/platforms/ihp-sg13g2/lib/RM_IHPSG13_2P_1024x32_c2_bm_bist_typ_1p20V_25C.lib new file mode 100644 index 0000000000..541d09d8b8 --- /dev/null +++ b/flow/platforms/ihp-sg13g2/lib/RM_IHPSG13_2P_1024x32_c2_bm_bist_typ_1p20V_25C.lib @@ -0,0 +1,2898 @@ +/* ------------------------------------------------------*/ +/**/ +/* Copyright 2025 IHP PDK Authors*/ +/**/ +/* Licensed under the Apache License, Version 2.0 (the "License");*/ +/* you may not use this file except in compliance with the License.*/ +/* You may obtain a copy of the License at*/ +/* */ +/* https://www.apache.org/licenses/LICENSE-2.0*/ +/* */ +/* Unless required by applicable law or agreed to in writing, software*/ +/* distributed under the License is distributed on an "AS IS" BASIS,*/ +/* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.*/ +/* See the License for the specific language governing permissions and*/ +/* limitations under the License.*/ +/* */ +/* Generated on Wed Aug 27 13:08:56 2025 */ +/* */ +/* ------------------------------------------------------ */ +library(RM_IHPSG13_2P_1024x32_c2_bm_bist_typ_1p20V_25C) { + technology (cmos) ; + delay_model : table_lookup ; + define ("add_pg_pin_to_lib", "library", "boolean"); + add_pg_pin_to_lib : true; + voltage_map ( VDD, 1.20); + voltage_map ( VDDARRAY, 1.20); + voltage_map ( VSS, 0.000000 ); + + date : "Wed Aug 27 13:08:53 2025" ; + comment : "IHP Microelectronics GmbH, 2023" ; + revision : 1.0.0 ; + simulation : true ; + nom_process : 1 ; + nom_temperature : 25 ; + nom_voltage : 1.20 ; + + operating_conditions("typ_1p20V_25C"){ + process : 1 ; + temperature : 25 ; + voltage : 1.20 ; + tree_type : "balanced_tree" ; + } + + default_operating_conditions : typ_1p20V_25C ; + default_max_transition : 1.0 ; + default_fanout_load : 1.0 ; + default_inout_pin_cap : 0.0 ; + default_input_pin_cap : 0.0 ; + default_output_pin_cap : 0.0 ; + default_cell_leakage_power : 0.0 ; + default_leakage_power_density : 0.0 ; + + slew_lower_threshold_pct_rise : 30 ; + slew_upper_threshold_pct_rise : 70 ; + input_threshold_pct_fall : 50 ; + output_threshold_pct_fall : 50 ; + input_threshold_pct_rise : 50 ; + output_threshold_pct_rise : 50 ; + slew_lower_threshold_pct_fall : 30 ; + slew_upper_threshold_pct_fall : 70 ; + slew_derate_from_library : 0.5; + k_volt_cell_leakage_power : 0.0 ; + k_temp_cell_leakage_power : 0.0 ; + k_process_cell_leakage_power : 0.0 ; + k_volt_internal_power : 0.0 ; + k_temp_internal_power : 0.0 ; + k_process_internal_power : 0.0 ; + + capacitive_load_unit (1,pf) ; + voltage_unit : "1V" ; + current_unit : "1uA" ; + time_unit : "1ns" ; + leakage_power_unit : "1nW" ; + pulling_resistance_unit : "1kohm"; + /* + ------------------------------------------------------------------------------------------ + implicit units overview: + cell_area unit : "um" + internal_power unit : "1e-12 * J/toggle = 1 * uW/MHz" + (capacitive_load_unit * voltage_unit^2) per toggle event + ------------------------------------------------------------------------------------------ + */ + library_features(report_delay_calculation); + define_cell_area (pad_drivers,pad_driver_sites) ; + + lu_table_template(CLKTRAN_constraint_template) { + variable_1 : constrained_pin_transition; + index_1 ( "0.010, 0.050, 0.200, 0.400, 1.000" ); + } + lu_table_template(SRAM_load_template) { + variable_1 : total_output_net_capacitance; + index_1 ( "0.0008,0.0014,0.0051,0.0100,0.0339,0.0640" ); + } + lu_table_template(SIG2SRAM_constraint_template) { + variable_1 : related_pin_transition; + variable_2 : constrained_pin_transition; + index_1 ( "0.0056,0.0232,0.0400,0.0728,0.1280,0.2440,0.4760" ); + index_2 ( "0.0056,0.0232,0.0400,0.0728,0.1280,0.2440,0.4760" ); + } + + lu_table_template(SIG2SRAM_delay_template) { + variable_1 : input_net_transition; + variable_2 : total_output_net_capacitance; + index_1 ( "0.0056,0.0232,0.0400,0.0728,0.1280,0.2440,0.4760" ); + index_2 ( "0.0008,0.0014,0.0051,0.0100,0.0339,0.0640" ); + } + + type (D_31_0) { + base_type : array; + data_type : bit; + bit_width : 32; + bit_from : 31; + bit_to : 0; + downto : true; + } + + type (A_9_0) { + base_type : array; + data_type : bit; + bit_width : 10; + bit_from : 9; + bit_to : 0; + downto : true; + } + +cell(RM_IHPSG13_2P_1024x32_c2_bm_bist) { +pg_pin (VDD) { + pg_type : primary_power; + voltage_name : VDD; +} +pg_pin (VDDARRAY) { + pg_type : primary_power; + voltage_name : VDDARRAY; +} +pg_pin (VSS) { + pg_type : primary_ground; + voltage_name : VSS; +} + +memory() { + type : ram; + address_width : 10; + word_width : 32; +} + +interface_timing : false; +bus_naming_style : "%s[%d]" ; +area : 264167.2813 ; + + pin(A_DLY) { + direction : input ; + capacitance : 0.00401111 ; + max_transition : "1" ; + related_power_pin : VDD; + related_ground_pin : VSS; + internal_power() { + rise_power("scalar") { + values (0); + } + fall_power("scalar") { + values (0); + } + } + } + +bus(A_ADDR) { + bus_type : A_9_0; + direction : input ; + capacitance : 0.0121077 ; + pin(A_ADDR[0]) { + capacitance : 0.00568653 ; + } + pin(A_ADDR[1]) { + capacitance : 0.00767263 ; + } + pin(A_ADDR[2]) { + capacitance : 0.0105079 ; + } + pin(A_ADDR[3]) { + capacitance : 0.0068178 ; + } + pin(A_ADDR[4]) { + capacitance : 0.00624497 ; + } + pin(A_ADDR[5]) { + capacitance : 0.0105871 ; + } + pin(A_ADDR[6]) { + capacitance : 0.0130817 ; + } + pin(A_ADDR[7]) { + capacitance : 0.0104931 ; + } + pin(A_ADDR[8]) { + capacitance : 0.00913384 ; + } + max_transition : "0.476" ; + pin(A_ADDR[9:0]) { + related_power_pin : VDD; + related_ground_pin : VSS; + internal_power() { + when : "A_MEN"; + rise_power("scalar"){ + values (0.0115); + } + fall_power("scalar"){ + values (0.0061); + } + } + internal_power() { + when : "!A_MEN"; + rise_power("scalar"){ + values (0.0201); + } + fall_power("scalar"){ + values (0.0005); + } + } + } + timing() { + timing_type : setup_rising; + related_pin : "A_CLK"; + when : "((A_WEN | A_REN)& A_MEN)" + sdf_cond : "A_RW_ACCESS" + + rise_constraint("SIG2SRAM_constraint_template") { + index_1("0.0056,0.0232,0.0400,0.0728,0.1280,0.2440,0.4760"); + index_2("0.0056,0.0232,0.0400,0.0728,0.1280,0.2440,0.4760"); + values ("-0.4168,-0.3973,-0.3855,-0.3543,-0.3074,-0.2020,-0.0027",\ +"-0.4324,-0.4129,-0.4012,-0.3699,-0.3191,-0.2176,-0.0184",\ +"-0.4441,-0.4285,-0.4129,-0.3816,-0.3309,-0.2293,-0.0301",\ +"-0.4793,-0.4598,-0.4441,-0.4129,-0.3660,-0.2645,-0.0652",\ +"-0.5223,-0.5066,-0.4910,-0.4598,-0.4129,-0.3074,-0.1121",\ +"-0.6199,-0.6082,-0.5926,-0.5613,-0.5145,-0.4129,-0.2137",\ +"-0.8191,-0.8074,-0.7840,-0.7566,-0.7098,-0.6082,-0.4051"); + } + + fall_constraint("SIG2SRAM_constraint_template") { + index_1("0.0056,0.0232,0.0400,0.0728,0.1280,0.2440,0.4760"); + index_2("0.0056,0.0232,0.0400,0.0728,0.1280,0.2440,0.4760"); + values ("-0.3309,-0.3113,-0.2996,-0.2684,-0.2176,-0.1238,0.0637",\ +"-0.3465,-0.3309,-0.3152,-0.2840,-0.2332,-0.1395,0.0480",\ +"-0.3582,-0.3426,-0.3270,-0.2996,-0.2488,-0.1512,0.0324",\ +"-0.3895,-0.3738,-0.3582,-0.3309,-0.2801,-0.1863,0.0051",\ +"-0.4363,-0.4207,-0.4051,-0.3777,-0.3230,-0.2293,-0.0379",\ +"-0.5379,-0.5223,-0.5066,-0.4793,-0.4285,-0.3309,-0.1434",\ +"-0.7332,-0.7176,-0.7020,-0.6746,-0.6238,-0.5262,-0.3387"); + } + } + + + timing() { + timing_type : hold_rising; + related_pin : "A_CLK"; + when : "((A_WEN | A_REN)& A_MEN)" + sdf_cond : "A_RW_ACCESS" + + rise_constraint("SIG2SRAM_constraint_template") { + index_1("0.0056,0.0232,0.0400,0.0728,0.1280,0.2440,0.4760"); + index_2("0.0056,0.0232,0.0400,0.0728,0.1280,0.2440,0.4760"); + values ("0.5246,0.5051,0.4895,0.4582,0.4113,0.3059,0.1066",\ +"0.5402,0.5207,0.5051,0.4777,0.4270,0.3215,0.1223",\ +"0.5520,0.5324,0.5168,0.4895,0.4387,0.3371,0.1340",\ +"0.5832,0.5676,0.5520,0.5207,0.4738,0.3684,0.1691",\ +"0.6301,0.6105,0.5949,0.5676,0.5168,0.4113,0.2160",\ +"0.7316,0.7121,0.7004,0.6691,0.6223,0.5168,0.3176",\ +"0.9270,0.9230,0.8957,0.8645,0.8137,0.7121,0.5168"); + } + + fall_constraint("SIG2SRAM_constraint_template") { + index_1("0.0056,0.0232,0.0400,0.0728,0.1280,0.2440,0.4760"); + index_2("0.0056,0.0232,0.0400,0.0728,0.1280,0.2440,0.4760"); + values ("0.4309,0.4152,0.4035,0.3684,0.3215,0.2277,0.0363",\ +"0.4465,0.4309,0.4152,0.3879,0.3371,0.2395,0.0559",\ +"0.4582,0.4426,0.4309,0.3996,0.3488,0.2551,0.0715",\ +"0.4934,0.4777,0.4621,0.4348,0.3840,0.2863,0.0988",\ +"0.5363,0.5207,0.5051,0.4777,0.4270,0.3332,0.1418",\ +"0.6379,0.6262,0.6105,0.5793,0.5324,0.4348,0.2434",\ +"0.8332,0.8215,0.8059,0.7707,0.7238,0.6301,0.4387"); + } + } +} +pin(A_WEN) { + direction : input ; + capacitance : 0.00324098 ; + max_transition : "0.476" ; + related_power_pin : VDD; + related_ground_pin : VSS; + internal_power() { + when : "A_MEN"; + rise_power("scalar"){ + values (0.0046); + } + fall_power("scalar"){ + values (0.0040); + } + } + internal_power() { + when : "!A_MEN"; + rise_power("scalar"){ + values (0.0045); + } + fall_power("scalar"){ + values (0.0043); + } + } + timing() { + timing_type : setup_rising; + related_pin : "A_CLK"; + when : "A_MEN" + sdf_cond : "A_MEN" + + rise_constraint("SIG2SRAM_constraint_template") { + index_1("0.0056,0.0232,0.0400,0.0728,0.1280,0.2440,0.4760"); + index_2("0.0056,0.0232,0.0400,0.0728,0.1280,0.2440,0.4760"); + values ("0.2043,0.2199,0.2316,0.2629,0.3059,0.4113,0.6066",\ +"0.1887,0.2043,0.2160,0.2473,0.2941,0.3957,0.5949",\ +"0.1691,0.1848,0.2004,0.2316,0.2785,0.3801,0.5754",\ +"0.1379,0.1574,0.1691,0.2004,0.2473,0.3527,0.5480",\ +"0.0910,0.1066,0.1223,0.1535,0.2004,0.2980,0.4973",\ +"-0.0105,0.0051,0.0207,0.0520,0.0949,0.2004,0.3957",\ +"-0.2059,-0.1902,-0.1746,-0.1473,-0.1004,0.0051,0.2004"); + } + + fall_constraint("SIG2SRAM_constraint_template") { + index_1("0.0056,0.0232,0.0400,0.0728,0.1280,0.2440,0.4760"); + index_2("0.0056,0.0232,0.0400,0.0728,0.1280,0.2440,0.4760"); + values ("0.2941,0.3098,0.3215,0.3488,0.4035,0.4973,0.6887",\ +"0.2785,0.2941,0.3059,0.3332,0.3840,0.4816,0.6691",\ +"0.2629,0.2785,0.2902,0.3176,0.3684,0.4660,0.6535",\ +"0.2316,0.2473,0.2590,0.2863,0.3410,0.4348,0.6262",\ +"0.1848,0.2004,0.2121,0.2395,0.2902,0.3879,0.5754",\ +"0.0832,0.0988,0.1105,0.1379,0.1809,0.2746,0.4699",\ +"-0.1121,-0.0965,-0.0848,-0.0535,-0.0066,0.0910,0.2824"); + } + } + + + timing() { + timing_type : hold_rising; + related_pin : "A_CLK"; + when : "A_MEN" + sdf_cond : "A_MEN" + + rise_constraint("SIG2SRAM_constraint_template") { + index_1("0.0056,0.0232,0.0400,0.0728,0.1280,0.2440,0.4760"); + index_2("0.0056,0.0232,0.0400,0.0728,0.1280,0.2440,0.4760"); + values ("0.2473,0.2316,0.2160,0.1887,0.1379,0.0363,-0.1629",\ +"0.2629,0.2473,0.2316,0.2043,0.1535,0.0520,-0.1473",\ +"0.2785,0.2590,0.2434,0.2160,0.1652,0.0676,-0.1355",\ +"0.3098,0.2941,0.2785,0.2473,0.1965,0.0910,-0.1043",\ +"0.3527,0.3371,0.3215,0.2941,0.2434,0.1418,-0.0574",\ +"0.4582,0.4426,0.4270,0.3957,0.3488,0.2434,0.0480",\ +"0.6535,0.6379,0.6184,0.5910,0.5402,0.4426,0.2434"); + } + + fall_constraint("SIG2SRAM_constraint_template") { + index_1("0.0056,0.0232,0.0400,0.0728,0.1280,0.2440,0.4760"); + index_2("0.0056,0.0232,0.0400,0.0728,0.1280,0.2440,0.4760"); + values ("0.2395,0.2238,0.2121,0.1809,0.1301,0.0324,-0.1551",\ +"0.2551,0.2395,0.2277,0.1965,0.1457,0.0480,-0.1395",\ +"0.2668,0.2551,0.2395,0.2082,0.1574,0.0637,-0.1277",\ +"0.3020,0.2863,0.2707,0.2395,0.1887,0.0910,-0.0965",\ +"0.3449,0.3293,0.3176,0.2863,0.2355,0.1379,-0.0496",\ +"0.4504,0.4348,0.4191,0.3879,0.3371,0.2395,0.0559",\ +"0.6457,0.6301,0.6145,0.5871,0.5324,0.4309,0.2512"); + } + } + } +pin(A_REN) { + direction : input ; + capacitance : 0.00381634 ; + max_transition : "0.476" ; + related_power_pin : VDD; + related_ground_pin : VSS; + internal_power() { + when : "A_MEN"; + rise_power("scalar"){ + values (0.0061); + } + fall_power("scalar"){ + values (0.0022); + } + } + internal_power() { + when : "!A_MEN"; + rise_power("scalar"){ + values (0.0064); + } + fall_power("scalar"){ + values (0.0027); + } + } + timing() { + timing_type : setup_rising; + related_pin : "A_CLK"; + when : "A_MEN" + sdf_cond : "A_MEN" + + rise_constraint("SIG2SRAM_constraint_template") { + index_1("0.0056,0.0232,0.0400,0.0728,0.1280,0.2440,0.4760"); + index_2("0.0056,0.0232,0.0400,0.0728,0.1280,0.2440,0.4760"); + values ("-0.0301,-0.0145,0.0012,0.0324,0.0793,0.1809,0.3762",\ +"-0.0457,-0.0301,-0.0145,0.0168,0.0637,0.1613,0.3605",\ +"-0.0574,-0.0418,-0.0262,0.0051,0.0520,0.1496,0.3449",\ +"-0.0926,-0.0730,-0.0574,-0.0262,0.0207,0.1184,0.3137",\ +"-0.1395,-0.1238,-0.1082,-0.0770,-0.0301,0.0715,0.2707",\ +"-0.2410,-0.2254,-0.2098,-0.1746,-0.1355,-0.0340,0.1652",\ +"-0.4402,-0.4207,-0.4051,-0.3738,-0.3270,-0.2293,-0.0340"); + } + + fall_constraint("SIG2SRAM_constraint_template") { + index_1("0.0056,0.0232,0.0400,0.0728,0.1280,0.2440,0.4760"); + index_2("0.0056,0.0232,0.0400,0.0728,0.1280,0.2440,0.4760"); + values ("0.0988,0.1145,0.1262,0.1535,0.2043,0.3020,0.4855",\ +"0.0832,0.0988,0.1105,0.1418,0.1848,0.2824,0.4738",\ +"0.0676,0.0832,0.0949,0.1262,0.1730,0.2668,0.4621",\ +"0.0402,0.0559,0.0676,0.0988,0.1457,0.2434,0.4191",\ +"-0.0105,0.0012,0.0168,0.0480,0.0988,0.1965,0.3840",\ +"-0.1160,-0.0965,-0.0848,-0.0535,-0.0066,0.0988,0.2824",\ +"-0.3113,-0.2957,-0.2801,-0.2527,-0.2059,-0.1043,0.0832"); + } + } + + + timing() { + timing_type : hold_rising; + related_pin : "A_CLK"; + when : "A_MEN" + sdf_cond : "A_MEN" + + rise_constraint("SIG2SRAM_constraint_template") { + index_1("0.0056,0.0232,0.0400,0.0728,0.1280,0.2440,0.4760"); + index_2("0.0056,0.0232,0.0400,0.0728,0.1280,0.2440,0.4760"); + values ("0.2707,0.2551,0.2395,0.2121,0.1613,0.0598,-0.1395",\ +"0.2863,0.2707,0.2551,0.2238,0.1730,0.0715,-0.1238",\ +"0.2980,0.2824,0.2668,0.2395,0.1887,0.0871,-0.1121",\ +"0.3332,0.3176,0.3020,0.2707,0.2199,0.1184,-0.0809",\ +"0.3762,0.3605,0.3449,0.3176,0.2668,0.1613,-0.0340",\ +"0.4816,0.4621,0.4504,0.4191,0.3723,0.2629,0.0715",\ +"0.6770,0.6613,0.6418,0.6184,0.5637,0.4699,0.2629"); + } + + fall_constraint("SIG2SRAM_constraint_template") { + index_1("0.0056,0.0232,0.0400,0.0728,0.1280,0.2440,0.4760"); + index_2("0.0056,0.0232,0.0400,0.0728,0.1280,0.2440,0.4760"); + values ("0.2590,0.2434,0.2316,0.2004,0.1457,0.0520,-0.1355",\ +"0.2746,0.2590,0.2434,0.2160,0.1613,0.0676,-0.1199",\ +"0.2863,0.2707,0.2590,0.2277,0.1730,0.0832,-0.1082",\ +"0.3215,0.3059,0.2902,0.2590,0.2082,0.1105,-0.0770",\ +"0.3645,0.3488,0.3332,0.3059,0.2551,0.1535,-0.0340",\ +"0.4699,0.4543,0.4387,0.4074,0.3605,0.2551,0.0715",\ +"0.6652,0.6496,0.6340,0.6027,0.5520,0.4621,0.2707"); + } + } + } +pin(A_MEN) { + direction : input ; + capacitance : 0.00309605 ; + max_transition : "0.476" ; + related_power_pin : VDD; + related_ground_pin : VSS; + internal_power() { + rise_power("scalar"){ + values (0.0870); + } + fall_power("scalar"){ + values (0.0053); + } + } + timing() { + timing_type : setup_rising; + related_pin : "A_CLK"; + + rise_constraint("SIG2SRAM_constraint_template") { + index_1("0.0056,0.0232,0.0400,0.0728,0.1280,0.2440,0.4760"); + index_2("0.0056,0.0232,0.0400,0.0728,0.1280,0.2440,0.4760"); + values ("0.2043,0.2199,0.2316,0.2668,0.3098,0.4152,0.6066",\ +"0.1887,0.2043,0.2199,0.2512,0.2941,0.3996,0.5949",\ +"0.1730,0.1887,0.2043,0.2355,0.2824,0.3840,0.5793",\ +"0.1418,0.1574,0.1730,0.2043,0.2512,0.3566,0.5480",\ +"0.0949,0.1105,0.1262,0.1574,0.2043,0.3020,0.5051",\ +"-0.0066,0.0090,0.0246,0.0520,0.0988,0.2043,0.3996",\ +"-0.2020,-0.1863,-0.1746,-0.1434,-0.0965,0.0090,0.2082"); + } + + fall_constraint("SIG2SRAM_constraint_template") { + index_1("0.0056,0.0232,0.0400,0.0728,0.1280,0.2440,0.4760"); + index_2("0.0056,0.0232,0.0400,0.0728,0.1280,0.2440,0.4760"); + values ("0.2980,0.3137,0.3254,0.3527,0.4035,0.5012,0.6887",\ +"0.2824,0.2980,0.3098,0.3371,0.3879,0.4855,0.6730",\ +"0.2668,0.2824,0.2941,0.3215,0.3723,0.4699,0.6574",\ +"0.2355,0.2473,0.2629,0.2902,0.3410,0.4387,0.6262",\ +"0.1887,0.2004,0.2160,0.2395,0.2941,0.3918,0.5793",\ +"0.0871,0.1027,0.1145,0.1418,0.1848,0.2746,0.4816",\ +"-0.1082,-0.0965,-0.0809,-0.0496,-0.0027,0.0949,0.2863"); + } + } + + + timing() { + timing_type : hold_rising; + related_pin : "A_CLK"; + + rise_constraint("SIG2SRAM_constraint_template") { + index_1("0.0056,0.0232,0.0400,0.0728,0.1280,0.2440,0.4760"); + index_2("0.0056,0.0232,0.0400,0.0728,0.1280,0.2440,0.4760"); + values ("0.2512,0.2355,0.2199,0.1926,0.1418,0.0402,-0.1590",\ +"0.2668,0.2512,0.2355,0.2082,0.1574,0.0559,-0.1434",\ +"0.2824,0.2629,0.2512,0.2199,0.1691,0.0715,-0.1316",\ +"0.3137,0.2980,0.2824,0.2512,0.2004,0.0988,-0.0965",\ +"0.3566,0.3410,0.3254,0.2980,0.2473,0.1418,-0.0535",\ +"0.4621,0.4426,0.4309,0.3996,0.3527,0.2473,0.0520",\ +"0.6574,0.6418,0.6262,0.5949,0.5441,0.4465,0.2473"); + } + + fall_constraint("SIG2SRAM_constraint_template") { + index_1("0.0056,0.0232,0.0400,0.0728,0.1280,0.2440,0.4760"); + index_2("0.0056,0.0232,0.0400,0.0728,0.1280,0.2440,0.4760"); + values ("0.2395,0.2238,0.2121,0.1809,0.1301,0.0324,-0.1551",\ +"0.2551,0.2434,0.2277,0.1965,0.1457,0.0480,-0.1395",\ +"0.2707,0.2551,0.2395,0.2082,0.1574,0.0637,-0.1277",\ +"0.3020,0.2863,0.2707,0.2434,0.1926,0.0910,-0.0965",\ +"0.3449,0.3332,0.3176,0.2863,0.2355,0.1379,-0.0496",\ +"0.4504,0.4348,0.4230,0.3918,0.3410,0.2434,0.0559",\ +"0.6457,0.6301,0.6145,0.5910,0.5324,0.4387,0.2512"); + } + } + } +bus(A_BM) { + bus_type : D_31_0; + direction : input ; + capacitance : 0.00372627 ; + max_transition : "0.476" ; + pin(A_BM[31:0]) { + related_power_pin : VDD; + related_ground_pin : VSS; + internal_power() { + when : "A_MEN"; + rise_power("scalar"){ + values (0.1177); + } + fall_power("scalar"){ + values (0.0495); + } + } + internal_power() { + when : "!A_MEN"; + rise_power("scalar"){ + values (0.1175); + } + fall_power("scalar"){ + values (0.0489); + } + } + } + timing() { + timing_type : setup_rising; + related_pin : "A_CLK"; + when : "(A_WEN & A_MEN)" + sdf_cond : "A_RW_ACCESS" + + rise_constraint("SIG2SRAM_constraint_template") { + index_1("0.0056,0.0232,0.0400,0.0728,0.1280,0.2440,0.4760"); + index_2("0.0056,0.0232,0.0400,0.0728,0.1280,0.2440,0.4760"); + values ("-0.5145,-0.4989,-0.4852,-0.4530,-0.4061,-0.3016,-0.1102",\ +"-0.5195,-0.5039,-0.4902,-0.4580,-0.4111,-0.3067,-0.1152",\ +"-0.5240,-0.5083,-0.4947,-0.4624,-0.4156,-0.3111,-0.1197",\ +"-0.5338,-0.5182,-0.5045,-0.4723,-0.4254,-0.3209,-0.1295",\ +"-0.5402,-0.5245,-0.5109,-0.4786,-0.4318,-0.3273,-0.1359",\ +"-0.5767,-0.5610,-0.5474,-0.5151,-0.4683,-0.3638,-0.1724",\ +"-0.6275,-0.6119,-0.5982,-0.5660,-0.5191,-0.4146,-0.2232"); + } + + fall_constraint("SIG2SRAM_constraint_template") { + index_1("0.0056,0.0232,0.0400,0.0728,0.1280,0.2440,0.4760"); + index_2("0.0056,0.0232,0.0400,0.0728,0.1280,0.2440,0.4760"); + values ("-0.4764,-0.4618,-0.4481,-0.4198,-0.3690,-0.2714,-0.0887",\ +"-0.4815,-0.4668,-0.4531,-0.4248,-0.3740,-0.2764,-0.0938",\ +"-0.4859,-0.4712,-0.4576,-0.4292,-0.3785,-0.2808,-0.0982",\ +"-0.4957,-0.4811,-0.4674,-0.4391,-0.3883,-0.2907,-0.1080",\ +"-0.5021,-0.4874,-0.4738,-0.4454,-0.3947,-0.2970,-0.1144",\ +"-0.5386,-0.5239,-0.5102,-0.4819,-0.4311,-0.3335,-0.1509",\ +"-0.5894,-0.5748,-0.5611,-0.5328,-0.4820,-0.3844,-0.2017"); + } + } + + + timing() { + timing_type : hold_rising; + related_pin : "A_CLK"; + when : "(A_WEN & A_MEN)" + sdf_cond : "A_RW_ACCESS" + + rise_constraint("SIG2SRAM_constraint_template") { + index_1("0.0056,0.0232,0.0400,0.0728,0.1280,0.2440,0.4760"); + index_2("0.0056,0.0232,0.0400,0.0728,0.1280,0.2440,0.4760"); + values ("0.6249,0.6083,0.5956,0.5634,0.5155,0.4120,0.2196",\ +"0.6299,0.6133,0.6006,0.5684,0.5205,0.4170,0.2246",\ +"0.6343,0.6177,0.6050,0.5728,0.5250,0.4214,0.2291",\ +"0.6442,0.6276,0.6149,0.5827,0.5348,0.4313,0.2389",\ +"0.6505,0.6339,0.6212,0.5890,0.5412,0.4376,0.2453",\ +"0.6870,0.6704,0.6577,0.6255,0.5776,0.4741,0.2817",\ +"0.7379,0.7213,0.7086,0.6764,0.6285,0.5250,0.3326"); + } + + fall_constraint("SIG2SRAM_constraint_template") { + index_1("0.0056,0.0232,0.0400,0.0728,0.1280,0.2440,0.4760"); + index_2("0.0056,0.0232,0.0400,0.0728,0.1280,0.2440,0.4760"); + values ("0.5790,0.5643,0.5507,0.5224,0.4726,0.3798,0.1952",\ +"0.5840,0.5694,0.5557,0.5274,0.4776,0.3848,0.2002",\ +"0.5884,0.5738,0.5601,0.5318,0.4820,0.3892,0.2046",\ +"0.5983,0.5836,0.5700,0.5416,0.4918,0.3991,0.2145",\ +"0.6046,0.5900,0.5763,0.5480,0.4982,0.4054,0.2208",\ +"0.6411,0.6265,0.6128,0.5845,0.5347,0.4419,0.2573",\ +"0.6920,0.6773,0.6637,0.6353,0.5855,0.4928,0.3082"); + } + } +} + pin(A_CLK) { + direction : input; + capacitance : 0.00380014; + max_transition : "0.476"; + clock : "true" ; + pin_func_type : active_rising ; + + timing () { + timing_type : "min_pulse_width"; + related_pin : "A_CLK"; + rise_constraint("CLKTRAN_constraint_template") { + index_1("0.0056,0.476"); + values("0.21,0.21"); + } + } + + related_power_pin : VDD; + related_ground_pin : VSS; + + internal_power() { + when : "!A_MEN & !A_WEN & !A_REN"; + rise_power("scalar"){ + values (0); + } + fall_power("scalar"){ + values (0); + } + } + internal_power() { + when : "!A_MEN & A_WEN & !A_REN"; + rise_power("scalar"){ + values (0.5298); + } + fall_power("scalar"){ + values (0); + } + } + internal_power() { + when : "A_MEN & A_WEN & !A_REN"; + rise_power("scalar"){ + values (58.9183); + } + fall_power("scalar"){ + values (0); + } + } + internal_power() { + when : "A_MEN & A_WEN & A_REN"; + rise_power("scalar"){ + values (61.8765); + } + fall_power("scalar"){ + values (0); + } + } + internal_power() { + when : "A_MEN & !A_WEN & A_REN"; + rise_power("scalar"){ + values (48.2666); + } + fall_power("scalar"){ + values (0); + } + } + internal_power() { + when : "!A_MEN & !A_WEN & A_REN"; + rise_power("scalar"){ + values (0.3622); + } + fall_power("scalar"){ + values (0); + } + } + internal_power() { + when : "!A_MEN & A_WEN & A_REN"; + rise_power("scalar"){ + values (1.2134); + } + fall_power("scalar"){ + values (0); + } + } + internal_power() { + when : "A_MEN & !A_WEN & !A_REN"; + rise_power("scalar"){ + values (0); + } + fall_power("scalar"){ + values (0); + } + } + } + bus(A_DIN) { + bus_type : D_31_0; + direction : input ; + capacitance : 0.00500744 ; + memory_write() { + address : A_ADDR ; + clocked_on : A_CLK; + } + + max_transition : "0.476" ; + pin(A_DIN[31:0]) { + related_power_pin : VDD; + related_ground_pin : VSS; + internal_power() { + when : "A_MEN"; + rise_power("scalar"){ + values (0.1177); + } + fall_power("scalar"){ + values (0.0495); + } + } + internal_power() { + when : "!A_MEN"; + rise_power("scalar"){ + values (0.1175); + } + fall_power("scalar"){ + values (0.0489); + } + } + } + timing() { + timing_type : setup_rising; + related_pin : "A_CLK"; + when : "(A_WEN & A_MEN)"; + sdf_cond : "A_W_ACCESS"; + + rise_constraint("SIG2SRAM_constraint_template") { + index_1("0.0056,0.0232,0.0400,0.0728,0.1280,0.2440,0.4760"); + index_2("0.0056,0.0232,0.0400,0.0728,0.1280,0.2440,0.4760"); + values ("-0.5145,-0.4989,-0.4852,-0.4530,-0.4061,-0.3016,-0.1102",\ +"-0.5195,-0.5039,-0.4902,-0.4580,-0.4111,-0.3067,-0.1152",\ +"-0.5240,-0.5083,-0.4947,-0.4624,-0.4156,-0.3111,-0.1197",\ +"-0.5338,-0.5182,-0.5045,-0.4723,-0.4254,-0.3209,-0.1295",\ +"-0.5402,-0.5245,-0.5109,-0.4786,-0.4318,-0.3273,-0.1359",\ +"-0.5767,-0.5610,-0.5474,-0.5151,-0.4683,-0.3638,-0.1724",\ +"-0.6275,-0.6119,-0.5982,-0.5660,-0.5191,-0.4146,-0.2232"); + } + + fall_constraint("SIG2SRAM_constraint_template") { + index_1("0.0056,0.0232,0.0400,0.0728,0.1280,0.2440,0.4760"); + index_2("0.0056,0.0232,0.0400,0.0728,0.1280,0.2440,0.4760"); + values ("-0.4764,-0.4618,-0.4481,-0.4198,-0.3690,-0.2714,-0.0887",\ +"-0.4815,-0.4668,-0.4531,-0.4248,-0.3740,-0.2764,-0.0938",\ +"-0.4859,-0.4712,-0.4576,-0.4292,-0.3785,-0.2808,-0.0982",\ +"-0.4957,-0.4811,-0.4674,-0.4391,-0.3883,-0.2907,-0.1080",\ +"-0.5021,-0.4874,-0.4738,-0.4454,-0.3947,-0.2970,-0.1144",\ +"-0.5386,-0.5239,-0.5102,-0.4819,-0.4311,-0.3335,-0.1509",\ +"-0.5894,-0.5748,-0.5611,-0.5328,-0.4820,-0.3844,-0.2017"); + } + } + + timing() { + timing_type : hold_rising; + related_pin : "A_CLK"; + when : "(A_WEN & A_MEN)"; + sdf_cond : "A_W_ACCESS"; + + rise_constraint("SIG2SRAM_constraint_template") { + index_1("0.0056,0.0232,0.0400,0.0728,0.1280,0.2440,0.4760"); + index_2("0.0056,0.0232,0.0400,0.0728,0.1280,0.2440,0.4760"); + values ("0.6249,0.6083,0.5956,0.5634,0.5155,0.4120,0.2196",\ +"0.6299,0.6133,0.6006,0.5684,0.5205,0.4170,0.2246",\ +"0.6343,0.6177,0.6050,0.5728,0.5250,0.4214,0.2291",\ +"0.6442,0.6276,0.6149,0.5827,0.5348,0.4313,0.2389",\ +"0.6505,0.6339,0.6212,0.5890,0.5412,0.4376,0.2453",\ +"0.6870,0.6704,0.6577,0.6255,0.5776,0.4741,0.2817",\ +"0.7379,0.7213,0.7086,0.6764,0.6285,0.5250,0.3326"); + } + + fall_constraint("SIG2SRAM_constraint_template") { + index_1("0.0056,0.0232,0.0400,0.0728,0.1280,0.2440,0.4760"); + index_2("0.0056,0.0232,0.0400,0.0728,0.1280,0.2440,0.4760"); + values ("0.5790,0.5643,0.5507,0.5224,0.4726,0.3798,0.1952",\ +"0.5840,0.5694,0.5557,0.5274,0.4776,0.3848,0.2002",\ +"0.5884,0.5738,0.5601,0.5318,0.4820,0.3892,0.2046",\ +"0.5983,0.5836,0.5700,0.5416,0.4918,0.3991,0.2145",\ +"0.6046,0.5900,0.5763,0.5480,0.4982,0.4054,0.2208",\ +"0.6411,0.6265,0.6128,0.5845,0.5347,0.4419,0.2573",\ +"0.6920,0.6773,0.6637,0.6353,0.5855,0.4928,0.3082"); + } + } + } + + pin(A_BIST_EN) { + direction : input ; + capacitance : 0.00401111 ; + max_transition : "1" ; + related_power_pin : VDD; + related_ground_pin : VSS; + internal_power() { + rise_power("scalar") { + values (0); + } + fall_power("scalar") { + values (0); + } + } + } + +bus(A_BIST_ADDR) { + bus_type : A_9_0; + direction : input ; + capacitance : 0.0121077 ; + pin(A_BIST_ADDR[0]) { + capacitance : 0.00568653 ; + } + pin(A_BIST_ADDR[1]) { + capacitance : 0.00767263 ; + } + pin(A_BIST_ADDR[2]) { + capacitance : 0.0105079 ; + } + pin(A_BIST_ADDR[3]) { + capacitance : 0.0068178 ; + } + pin(A_BIST_ADDR[4]) { + capacitance : 0.00624497 ; + } + pin(A_BIST_ADDR[5]) { + capacitance : 0.0105871 ; + } + pin(A_BIST_ADDR[6]) { + capacitance : 0.0130817 ; + } + pin(A_BIST_ADDR[7]) { + capacitance : 0.0104931 ; + } + pin(A_BIST_ADDR[8]) { + capacitance : 0.00913384 ; + } + max_transition : "0.476" ; + pin(A_BIST_ADDR[9:0]) { + related_power_pin : VDD; + related_ground_pin : VSS; + internal_power() { + when : "A_BIST_MEN"; + rise_power("scalar"){ + values (0.0115); + } + fall_power("scalar"){ + values (0.0061); + } + } + internal_power() { + when : "!A_BIST_MEN"; + rise_power("scalar"){ + values (0.0201); + } + fall_power("scalar"){ + values (0.0005); + } + } + } + timing() { + timing_type : setup_rising; + related_pin : "A_BIST_CLK"; + when : "((A_BIST_WEN | A_BIST_REN)& A_BIST_MEN)" + sdf_cond : "A_BIST_RW_ACCESS" + + rise_constraint("SIG2SRAM_constraint_template") { + index_1("0.0056,0.0232,0.0400,0.0728,0.1280,0.2440,0.4760"); + index_2("0.0056,0.0232,0.0400,0.0728,0.1280,0.2440,0.4760"); + values ("-0.4168,-0.3973,-0.3855,-0.3543,-0.3074,-0.2020,-0.0027",\ +"-0.4324,-0.4129,-0.4012,-0.3699,-0.3191,-0.2176,-0.0184",\ +"-0.4441,-0.4285,-0.4129,-0.3816,-0.3309,-0.2293,-0.0301",\ +"-0.4793,-0.4598,-0.4441,-0.4129,-0.3660,-0.2645,-0.0652",\ +"-0.5223,-0.5066,-0.4910,-0.4598,-0.4129,-0.3074,-0.1121",\ +"-0.6199,-0.6082,-0.5926,-0.5613,-0.5145,-0.4129,-0.2137",\ +"-0.8191,-0.8074,-0.7840,-0.7566,-0.7098,-0.6082,-0.4051"); + } + + fall_constraint("SIG2SRAM_constraint_template") { + index_1("0.0056,0.0232,0.0400,0.0728,0.1280,0.2440,0.4760"); + index_2("0.0056,0.0232,0.0400,0.0728,0.1280,0.2440,0.4760"); + values ("-0.3309,-0.3113,-0.2996,-0.2684,-0.2176,-0.1238,0.0637",\ +"-0.3465,-0.3309,-0.3152,-0.2840,-0.2332,-0.1395,0.0480",\ +"-0.3582,-0.3426,-0.3270,-0.2996,-0.2488,-0.1512,0.0324",\ +"-0.3895,-0.3738,-0.3582,-0.3309,-0.2801,-0.1863,0.0051",\ +"-0.4363,-0.4207,-0.4051,-0.3777,-0.3230,-0.2293,-0.0379",\ +"-0.5379,-0.5223,-0.5066,-0.4793,-0.4285,-0.3309,-0.1434",\ +"-0.7332,-0.7176,-0.7020,-0.6746,-0.6238,-0.5262,-0.3387"); + } + } + + + timing() { + timing_type : hold_rising; + related_pin : "A_BIST_CLK"; + when : "((A_BIST_WEN | A_BIST_REN)& A_BIST_MEN)" + sdf_cond : "A_BIST_RW_ACCESS" + + rise_constraint("SIG2SRAM_constraint_template") { + index_1("0.0056,0.0232,0.0400,0.0728,0.1280,0.2440,0.4760"); + index_2("0.0056,0.0232,0.0400,0.0728,0.1280,0.2440,0.4760"); + values ("0.5246,0.5051,0.4895,0.4582,0.4113,0.3059,0.1066",\ +"0.5402,0.5207,0.5051,0.4777,0.4270,0.3215,0.1223",\ +"0.5520,0.5324,0.5168,0.4895,0.4387,0.3371,0.1340",\ +"0.5832,0.5676,0.5520,0.5207,0.4738,0.3684,0.1691",\ +"0.6301,0.6105,0.5949,0.5676,0.5168,0.4113,0.2160",\ +"0.7316,0.7121,0.7004,0.6691,0.6223,0.5168,0.3176",\ +"0.9270,0.9230,0.8957,0.8645,0.8137,0.7121,0.5168"); + } + + fall_constraint("SIG2SRAM_constraint_template") { + index_1("0.0056,0.0232,0.0400,0.0728,0.1280,0.2440,0.4760"); + index_2("0.0056,0.0232,0.0400,0.0728,0.1280,0.2440,0.4760"); + values ("0.4309,0.4152,0.4035,0.3684,0.3215,0.2277,0.0363",\ +"0.4465,0.4309,0.4152,0.3879,0.3371,0.2395,0.0559",\ +"0.4582,0.4426,0.4309,0.3996,0.3488,0.2551,0.0715",\ +"0.4934,0.4777,0.4621,0.4348,0.3840,0.2863,0.0988",\ +"0.5363,0.5207,0.5051,0.4777,0.4270,0.3332,0.1418",\ +"0.6379,0.6262,0.6105,0.5793,0.5324,0.4348,0.2434",\ +"0.8332,0.8215,0.8059,0.7707,0.7238,0.6301,0.4387"); + } + } +} +pin(A_BIST_WEN) { + direction : input ; + capacitance : 0.00324098 ; + max_transition : "0.476" ; + related_power_pin : VDD; + related_ground_pin : VSS; + internal_power() { + when : "A_BIST_MEN"; + rise_power("scalar"){ + values (0.0046); + } + fall_power("scalar"){ + values (0.0040); + } + } + internal_power() { + when : "!A_BIST_MEN"; + rise_power("scalar"){ + values (0.0045); + } + fall_power("scalar"){ + values (0.0043); + } + } + timing() { + timing_type : setup_rising; + related_pin : "A_BIST_CLK"; + when : "A_BIST_MEN" + sdf_cond : "A_BIST_MEN" + + rise_constraint("SIG2SRAM_constraint_template") { + index_1("0.0056,0.0232,0.0400,0.0728,0.1280,0.2440,0.4760"); + index_2("0.0056,0.0232,0.0400,0.0728,0.1280,0.2440,0.4760"); + values ("0.2043,0.2199,0.2316,0.2629,0.3059,0.4113,0.6066",\ +"0.1887,0.2043,0.2160,0.2473,0.2941,0.3957,0.5949",\ +"0.1691,0.1848,0.2004,0.2316,0.2785,0.3801,0.5754",\ +"0.1379,0.1574,0.1691,0.2004,0.2473,0.3527,0.5480",\ +"0.0910,0.1066,0.1223,0.1535,0.2004,0.2980,0.4973",\ +"-0.0105,0.0051,0.0207,0.0520,0.0949,0.2004,0.3957",\ +"-0.2059,-0.1902,-0.1746,-0.1473,-0.1004,0.0051,0.2004"); + } + + fall_constraint("SIG2SRAM_constraint_template") { + index_1("0.0056,0.0232,0.0400,0.0728,0.1280,0.2440,0.4760"); + index_2("0.0056,0.0232,0.0400,0.0728,0.1280,0.2440,0.4760"); + values ("0.2941,0.3098,0.3215,0.3488,0.4035,0.4973,0.6887",\ +"0.2785,0.2941,0.3059,0.3332,0.3840,0.4816,0.6691",\ +"0.2629,0.2785,0.2902,0.3176,0.3684,0.4660,0.6535",\ +"0.2316,0.2473,0.2590,0.2863,0.3410,0.4348,0.6262",\ +"0.1848,0.2004,0.2121,0.2395,0.2902,0.3879,0.5754",\ +"0.0832,0.0988,0.1105,0.1379,0.1809,0.2746,0.4699",\ +"-0.1121,-0.0965,-0.0848,-0.0535,-0.0066,0.0910,0.2824"); + } + } + + + timing() { + timing_type : hold_rising; + related_pin : "A_BIST_CLK"; + when : "A_BIST_MEN" + sdf_cond : "A_BIST_MEN" + + rise_constraint("SIG2SRAM_constraint_template") { + index_1("0.0056,0.0232,0.0400,0.0728,0.1280,0.2440,0.4760"); + index_2("0.0056,0.0232,0.0400,0.0728,0.1280,0.2440,0.4760"); + values ("0.2473,0.2316,0.2160,0.1887,0.1379,0.0363,-0.1629",\ +"0.2629,0.2473,0.2316,0.2043,0.1535,0.0520,-0.1473",\ +"0.2785,0.2590,0.2434,0.2160,0.1652,0.0676,-0.1355",\ +"0.3098,0.2941,0.2785,0.2473,0.1965,0.0910,-0.1043",\ +"0.3527,0.3371,0.3215,0.2941,0.2434,0.1418,-0.0574",\ +"0.4582,0.4426,0.4270,0.3957,0.3488,0.2434,0.0480",\ +"0.6535,0.6379,0.6184,0.5910,0.5402,0.4426,0.2434"); + } + + fall_constraint("SIG2SRAM_constraint_template") { + index_1("0.0056,0.0232,0.0400,0.0728,0.1280,0.2440,0.4760"); + index_2("0.0056,0.0232,0.0400,0.0728,0.1280,0.2440,0.4760"); + values ("0.2395,0.2238,0.2121,0.1809,0.1301,0.0324,-0.1551",\ +"0.2551,0.2395,0.2277,0.1965,0.1457,0.0480,-0.1395",\ +"0.2668,0.2551,0.2395,0.2082,0.1574,0.0637,-0.1277",\ +"0.3020,0.2863,0.2707,0.2395,0.1887,0.0910,-0.0965",\ +"0.3449,0.3293,0.3176,0.2863,0.2355,0.1379,-0.0496",\ +"0.4504,0.4348,0.4191,0.3879,0.3371,0.2395,0.0559",\ +"0.6457,0.6301,0.6145,0.5871,0.5324,0.4309,0.2512"); + } + } + } +pin(A_BIST_REN) { + direction : input ; + capacitance : 0.00381634 ; + max_transition : "0.476" ; + related_power_pin : VDD; + related_ground_pin : VSS; + internal_power() { + when : "A_BIST_MEN"; + rise_power("scalar"){ + values (0.0061); + } + fall_power("scalar"){ + values (0.0022); + } + } + internal_power() { + when : "!A_BIST_MEN"; + rise_power("scalar"){ + values (0.0064); + } + fall_power("scalar"){ + values (0.0027); + } + } + timing() { + timing_type : setup_rising; + related_pin : "A_BIST_CLK"; + when : "A_BIST_MEN" + sdf_cond : "A_BIST_MEN" + + rise_constraint("SIG2SRAM_constraint_template") { + index_1("0.0056,0.0232,0.0400,0.0728,0.1280,0.2440,0.4760"); + index_2("0.0056,0.0232,0.0400,0.0728,0.1280,0.2440,0.4760"); + values ("-0.0301,-0.0145,0.0012,0.0324,0.0793,0.1809,0.3762",\ +"-0.0457,-0.0301,-0.0145,0.0168,0.0637,0.1613,0.3605",\ +"-0.0574,-0.0418,-0.0262,0.0051,0.0520,0.1496,0.3449",\ +"-0.0926,-0.0730,-0.0574,-0.0262,0.0207,0.1184,0.3137",\ +"-0.1395,-0.1238,-0.1082,-0.0770,-0.0301,0.0715,0.2707",\ +"-0.2410,-0.2254,-0.2098,-0.1746,-0.1355,-0.0340,0.1652",\ +"-0.4402,-0.4207,-0.4051,-0.3738,-0.3270,-0.2293,-0.0340"); + } + + fall_constraint("SIG2SRAM_constraint_template") { + index_1("0.0056,0.0232,0.0400,0.0728,0.1280,0.2440,0.4760"); + index_2("0.0056,0.0232,0.0400,0.0728,0.1280,0.2440,0.4760"); + values ("0.0988,0.1145,0.1262,0.1535,0.2043,0.3020,0.4855",\ +"0.0832,0.0988,0.1105,0.1418,0.1848,0.2824,0.4738",\ +"0.0676,0.0832,0.0949,0.1262,0.1730,0.2668,0.4621",\ +"0.0402,0.0559,0.0676,0.0988,0.1457,0.2434,0.4191",\ +"-0.0105,0.0012,0.0168,0.0480,0.0988,0.1965,0.3840",\ +"-0.1160,-0.0965,-0.0848,-0.0535,-0.0066,0.0988,0.2824",\ +"-0.3113,-0.2957,-0.2801,-0.2527,-0.2059,-0.1043,0.0832"); + } + } + + + timing() { + timing_type : hold_rising; + related_pin : "A_BIST_CLK"; + when : "A_BIST_MEN" + sdf_cond : "A_BIST_MEN" + + rise_constraint("SIG2SRAM_constraint_template") { + index_1("0.0056,0.0232,0.0400,0.0728,0.1280,0.2440,0.4760"); + index_2("0.0056,0.0232,0.0400,0.0728,0.1280,0.2440,0.4760"); + values ("0.2707,0.2551,0.2395,0.2121,0.1613,0.0598,-0.1395",\ +"0.2863,0.2707,0.2551,0.2238,0.1730,0.0715,-0.1238",\ +"0.2980,0.2824,0.2668,0.2395,0.1887,0.0871,-0.1121",\ +"0.3332,0.3176,0.3020,0.2707,0.2199,0.1184,-0.0809",\ +"0.3762,0.3605,0.3449,0.3176,0.2668,0.1613,-0.0340",\ +"0.4816,0.4621,0.4504,0.4191,0.3723,0.2629,0.0715",\ +"0.6770,0.6613,0.6418,0.6184,0.5637,0.4699,0.2629"); + } + + fall_constraint("SIG2SRAM_constraint_template") { + index_1("0.0056,0.0232,0.0400,0.0728,0.1280,0.2440,0.4760"); + index_2("0.0056,0.0232,0.0400,0.0728,0.1280,0.2440,0.4760"); + values ("0.2590,0.2434,0.2316,0.2004,0.1457,0.0520,-0.1355",\ +"0.2746,0.2590,0.2434,0.2160,0.1613,0.0676,-0.1199",\ +"0.2863,0.2707,0.2590,0.2277,0.1730,0.0832,-0.1082",\ +"0.3215,0.3059,0.2902,0.2590,0.2082,0.1105,-0.0770",\ +"0.3645,0.3488,0.3332,0.3059,0.2551,0.1535,-0.0340",\ +"0.4699,0.4543,0.4387,0.4074,0.3605,0.2551,0.0715",\ +"0.6652,0.6496,0.6340,0.6027,0.5520,0.4621,0.2707"); + } + } + } +pin(A_BIST_MEN) { + direction : input ; + capacitance : 0.00309605 ; + max_transition : "0.476" ; + related_power_pin : VDD; + related_ground_pin : VSS; + internal_power() { + rise_power("scalar"){ + values (0.0870); + } + fall_power("scalar"){ + values (0.0053); + } + } + timing() { + timing_type : setup_rising; + related_pin : "A_BIST_CLK"; + + rise_constraint("SIG2SRAM_constraint_template") { + index_1("0.0056,0.0232,0.0400,0.0728,0.1280,0.2440,0.4760"); + index_2("0.0056,0.0232,0.0400,0.0728,0.1280,0.2440,0.4760"); + values ("0.2043,0.2199,0.2316,0.2668,0.3098,0.4152,0.6066",\ +"0.1887,0.2043,0.2199,0.2512,0.2941,0.3996,0.5949",\ +"0.1730,0.1887,0.2043,0.2355,0.2824,0.3840,0.5793",\ +"0.1418,0.1574,0.1730,0.2043,0.2512,0.3566,0.5480",\ +"0.0949,0.1105,0.1262,0.1574,0.2043,0.3020,0.5051",\ +"-0.0066,0.0090,0.0246,0.0520,0.0988,0.2043,0.3996",\ +"-0.2020,-0.1863,-0.1746,-0.1434,-0.0965,0.0090,0.2082"); + } + + fall_constraint("SIG2SRAM_constraint_template") { + index_1("0.0056,0.0232,0.0400,0.0728,0.1280,0.2440,0.4760"); + index_2("0.0056,0.0232,0.0400,0.0728,0.1280,0.2440,0.4760"); + values ("0.2980,0.3137,0.3254,0.3527,0.4035,0.5012,0.6887",\ +"0.2824,0.2980,0.3098,0.3371,0.3879,0.4855,0.6730",\ +"0.2668,0.2824,0.2941,0.3215,0.3723,0.4699,0.6574",\ +"0.2355,0.2473,0.2629,0.2902,0.3410,0.4387,0.6262",\ +"0.1887,0.2004,0.2160,0.2395,0.2941,0.3918,0.5793",\ +"0.0871,0.1027,0.1145,0.1418,0.1848,0.2746,0.4816",\ +"-0.1082,-0.0965,-0.0809,-0.0496,-0.0027,0.0949,0.2863"); + } + } + + + timing() { + timing_type : hold_rising; + related_pin : "A_BIST_CLK"; + + rise_constraint("SIG2SRAM_constraint_template") { + index_1("0.0056,0.0232,0.0400,0.0728,0.1280,0.2440,0.4760"); + index_2("0.0056,0.0232,0.0400,0.0728,0.1280,0.2440,0.4760"); + values ("0.2512,0.2355,0.2199,0.1926,0.1418,0.0402,-0.1590",\ +"0.2668,0.2512,0.2355,0.2082,0.1574,0.0559,-0.1434",\ +"0.2824,0.2629,0.2512,0.2199,0.1691,0.0715,-0.1316",\ +"0.3137,0.2980,0.2824,0.2512,0.2004,0.0988,-0.0965",\ +"0.3566,0.3410,0.3254,0.2980,0.2473,0.1418,-0.0535",\ +"0.4621,0.4426,0.4309,0.3996,0.3527,0.2473,0.0520",\ +"0.6574,0.6418,0.6262,0.5949,0.5441,0.4465,0.2473"); + } + + fall_constraint("SIG2SRAM_constraint_template") { + index_1("0.0056,0.0232,0.0400,0.0728,0.1280,0.2440,0.4760"); + index_2("0.0056,0.0232,0.0400,0.0728,0.1280,0.2440,0.4760"); + values ("0.2395,0.2238,0.2121,0.1809,0.1301,0.0324,-0.1551",\ +"0.2551,0.2434,0.2277,0.1965,0.1457,0.0480,-0.1395",\ +"0.2707,0.2551,0.2395,0.2082,0.1574,0.0637,-0.1277",\ +"0.3020,0.2863,0.2707,0.2434,0.1926,0.0910,-0.0965",\ +"0.3449,0.3332,0.3176,0.2863,0.2355,0.1379,-0.0496",\ +"0.4504,0.4348,0.4230,0.3918,0.3410,0.2434,0.0559",\ +"0.6457,0.6301,0.6145,0.5910,0.5324,0.4387,0.2512"); + } + } + } +bus(A_BIST_BM) { + bus_type : D_31_0; + direction : input ; + capacitance : 0.00349377 ; + max_transition : "0.476" ; + pin(A_BIST_BM[31:0]) { + related_power_pin : VDD; + related_ground_pin : VSS; + internal_power() { + when : "A_BIST_MEN"; + rise_power("scalar"){ + values (0.1177); + } + fall_power("scalar"){ + values (0.0495); + } + } + internal_power() { + when : "!A_BIST_MEN"; + rise_power("scalar"){ + values (0.1175); + } + fall_power("scalar"){ + values (0.0489); + } + } + } + timing() { + timing_type : setup_rising; + related_pin : "A_BIST_CLK"; + when : "(A_BIST_WEN & A_BIST_MEN)" + sdf_cond : "A_BIST_RW_ACCESS" + + rise_constraint("SIG2SRAM_constraint_template") { + index_1("0.0056,0.0232,0.0400,0.0728,0.1280,0.2440,0.4760"); + index_2("0.0056,0.0232,0.0400,0.0728,0.1280,0.2440,0.4760"); + values ("-0.5145,-0.4989,-0.4852,-0.4530,-0.4061,-0.3016,-0.1102",\ +"-0.5195,-0.5039,-0.4902,-0.4580,-0.4111,-0.3067,-0.1152",\ +"-0.5240,-0.5083,-0.4947,-0.4624,-0.4156,-0.3111,-0.1197",\ +"-0.5338,-0.5182,-0.5045,-0.4723,-0.4254,-0.3209,-0.1295",\ +"-0.5402,-0.5245,-0.5109,-0.4786,-0.4318,-0.3273,-0.1359",\ +"-0.5767,-0.5610,-0.5474,-0.5151,-0.4683,-0.3638,-0.1724",\ +"-0.6275,-0.6119,-0.5982,-0.5660,-0.5191,-0.4146,-0.2232"); + } + + fall_constraint("SIG2SRAM_constraint_template") { + index_1("0.0056,0.0232,0.0400,0.0728,0.1280,0.2440,0.4760"); + index_2("0.0056,0.0232,0.0400,0.0728,0.1280,0.2440,0.4760"); + values ("-0.4764,-0.4618,-0.4481,-0.4198,-0.3690,-0.2714,-0.0887",\ +"-0.4815,-0.4668,-0.4531,-0.4248,-0.3740,-0.2764,-0.0938",\ +"-0.4859,-0.4712,-0.4576,-0.4292,-0.3785,-0.2808,-0.0982",\ +"-0.4957,-0.4811,-0.4674,-0.4391,-0.3883,-0.2907,-0.1080",\ +"-0.5021,-0.4874,-0.4738,-0.4454,-0.3947,-0.2970,-0.1144",\ +"-0.5386,-0.5239,-0.5102,-0.4819,-0.4311,-0.3335,-0.1509",\ +"-0.5894,-0.5748,-0.5611,-0.5328,-0.4820,-0.3844,-0.2017"); + } + } + + + timing() { + timing_type : hold_rising; + related_pin : "A_BIST_CLK"; + when : "(A_BIST_WEN & A_BIST_MEN)" + sdf_cond : "A_BIST_RW_ACCESS" + + rise_constraint("SIG2SRAM_constraint_template") { + index_1("0.0056,0.0232,0.0400,0.0728,0.1280,0.2440,0.4760"); + index_2("0.0056,0.0232,0.0400,0.0728,0.1280,0.2440,0.4760"); + values ("0.6249,0.6083,0.5956,0.5634,0.5155,0.4120,0.2196",\ +"0.6299,0.6133,0.6006,0.5684,0.5205,0.4170,0.2246",\ +"0.6343,0.6177,0.6050,0.5728,0.5250,0.4214,0.2291",\ +"0.6442,0.6276,0.6149,0.5827,0.5348,0.4313,0.2389",\ +"0.6505,0.6339,0.6212,0.5890,0.5412,0.4376,0.2453",\ +"0.6870,0.6704,0.6577,0.6255,0.5776,0.4741,0.2817",\ +"0.7379,0.7213,0.7086,0.6764,0.6285,0.5250,0.3326"); + } + + fall_constraint("SIG2SRAM_constraint_template") { + index_1("0.0056,0.0232,0.0400,0.0728,0.1280,0.2440,0.4760"); + index_2("0.0056,0.0232,0.0400,0.0728,0.1280,0.2440,0.4760"); + values ("0.5790,0.5643,0.5507,0.5224,0.4726,0.3798,0.1952",\ +"0.5840,0.5694,0.5557,0.5274,0.4776,0.3848,0.2002",\ +"0.5884,0.5738,0.5601,0.5318,0.4820,0.3892,0.2046",\ +"0.5983,0.5836,0.5700,0.5416,0.4918,0.3991,0.2145",\ +"0.6046,0.5900,0.5763,0.5480,0.4982,0.4054,0.2208",\ +"0.6411,0.6265,0.6128,0.5845,0.5347,0.4419,0.2573",\ +"0.6920,0.6773,0.6637,0.6353,0.5855,0.4928,0.3082"); + } + } +} + pin(A_BIST_CLK) { + direction : input; + capacitance : 0.00380014; + max_transition : "0.476"; + clock : "true" ; + pin_func_type : active_rising ; + + timing () { + timing_type : "min_pulse_width"; + related_pin : "A_BIST_CLK"; + rise_constraint("CLKTRAN_constraint_template") { + index_1("0.0056,0.476"); + values("0.21,0.21"); + } + } + + related_power_pin : VDD; + related_ground_pin : VSS; + + internal_power() { + when : "!A_BIST_MEN & !A_BIST_WEN & !A_BIST_REN"; + rise_power("scalar"){ + values (0); + } + fall_power("scalar"){ + values (0); + } + } + internal_power() { + when : "!A_BIST_MEN & A_BIST_WEN & !A_BIST_REN"; + rise_power("scalar"){ + values (0.5298); + } + fall_power("scalar"){ + values (0); + } + } + internal_power() { + when : "A_BIST_MEN & A_BIST_WEN & !A_BIST_REN"; + rise_power("scalar"){ + values (58.9183); + } + fall_power("scalar"){ + values (0); + } + } + internal_power() { + when : "A_BIST_MEN & A_BIST_WEN & A_BIST_REN"; + rise_power("scalar"){ + values (61.8765); + } + fall_power("scalar"){ + values (0); + } + } + internal_power() { + when : "A_BIST_MEN & !A_BIST_WEN & A_BIST_REN"; + rise_power("scalar"){ + values (48.2666); + } + fall_power("scalar"){ + values (0); + } + } + internal_power() { + when : "!A_BIST_MEN & !A_BIST_WEN & A_BIST_REN"; + rise_power("scalar"){ + values (0.3622); + } + fall_power("scalar"){ + values (0); + } + } + internal_power() { + when : "!A_BIST_MEN & A_BIST_WEN & A_BIST_REN"; + rise_power("scalar"){ + values (1.2134); + } + fall_power("scalar"){ + values (0); + } + } + internal_power() { + when : "A_BIST_MEN & !A_BIST_WEN & !A_BIST_REN"; + rise_power("scalar"){ + values (0); + } + fall_power("scalar"){ + values (0); + } + } + } + bus(A_BIST_DIN) { + bus_type : D_31_0; + direction : input ; + capacitance : 0.00393889 ; + memory_write() { + address : A_BIST_ADDR ; + clocked_on : A_BIST_CLK; + } + + max_transition : "0.476" ; + pin(A_BIST_DIN[31:0]) { + related_power_pin : VDD; + related_ground_pin : VSS; + internal_power() { + when : "A_BIST_MEN"; + rise_power("scalar"){ + values (0.1177); + } + fall_power("scalar"){ + values (0.0495); + } + } + internal_power() { + when : "!A_BIST_MEN"; + rise_power("scalar"){ + values (0.1175); + } + fall_power("scalar"){ + values (0.0489); + } + } + } + timing() { + timing_type : setup_rising; + related_pin : "A_BIST_CLK"; + when : "(A_BIST_WEN & A_BIST_MEN)"; + sdf_cond : "A_BIST_W_ACCESS"; + + rise_constraint("SIG2SRAM_constraint_template") { + index_1("0.0056,0.0232,0.0400,0.0728,0.1280,0.2440,0.4760"); + index_2("0.0056,0.0232,0.0400,0.0728,0.1280,0.2440,0.4760"); + values ("-0.5145,-0.4989,-0.4852,-0.4530,-0.4061,-0.3016,-0.1102",\ +"-0.5195,-0.5039,-0.4902,-0.4580,-0.4111,-0.3067,-0.1152",\ +"-0.5240,-0.5083,-0.4947,-0.4624,-0.4156,-0.3111,-0.1197",\ +"-0.5338,-0.5182,-0.5045,-0.4723,-0.4254,-0.3209,-0.1295",\ +"-0.5402,-0.5245,-0.5109,-0.4786,-0.4318,-0.3273,-0.1359",\ +"-0.5767,-0.5610,-0.5474,-0.5151,-0.4683,-0.3638,-0.1724",\ +"-0.6275,-0.6119,-0.5982,-0.5660,-0.5191,-0.4146,-0.2232"); + } + + fall_constraint("SIG2SRAM_constraint_template") { + index_1("0.0056,0.0232,0.0400,0.0728,0.1280,0.2440,0.4760"); + index_2("0.0056,0.0232,0.0400,0.0728,0.1280,0.2440,0.4760"); + values ("-0.4764,-0.4618,-0.4481,-0.4198,-0.3690,-0.2714,-0.0887",\ +"-0.4815,-0.4668,-0.4531,-0.4248,-0.3740,-0.2764,-0.0938",\ +"-0.4859,-0.4712,-0.4576,-0.4292,-0.3785,-0.2808,-0.0982",\ +"-0.4957,-0.4811,-0.4674,-0.4391,-0.3883,-0.2907,-0.1080",\ +"-0.5021,-0.4874,-0.4738,-0.4454,-0.3947,-0.2970,-0.1144",\ +"-0.5386,-0.5239,-0.5102,-0.4819,-0.4311,-0.3335,-0.1509",\ +"-0.5894,-0.5748,-0.5611,-0.5328,-0.4820,-0.3844,-0.2017"); + } + } + + timing() { + timing_type : hold_rising; + related_pin : "A_BIST_CLK"; + when : "(A_BIST_WEN & A_BIST_MEN)"; + sdf_cond : "A_BIST_W_ACCESS"; + + rise_constraint("SIG2SRAM_constraint_template") { + index_1("0.0056,0.0232,0.0400,0.0728,0.1280,0.2440,0.4760"); + index_2("0.0056,0.0232,0.0400,0.0728,0.1280,0.2440,0.4760"); + values ("0.6249,0.6083,0.5956,0.5634,0.5155,0.4120,0.2196",\ +"0.6299,0.6133,0.6006,0.5684,0.5205,0.4170,0.2246",\ +"0.6343,0.6177,0.6050,0.5728,0.5250,0.4214,0.2291",\ +"0.6442,0.6276,0.6149,0.5827,0.5348,0.4313,0.2389",\ +"0.6505,0.6339,0.6212,0.5890,0.5412,0.4376,0.2453",\ +"0.6870,0.6704,0.6577,0.6255,0.5776,0.4741,0.2817",\ +"0.7379,0.7213,0.7086,0.6764,0.6285,0.5250,0.3326"); + } + + fall_constraint("SIG2SRAM_constraint_template") { + index_1("0.0056,0.0232,0.0400,0.0728,0.1280,0.2440,0.4760"); + index_2("0.0056,0.0232,0.0400,0.0728,0.1280,0.2440,0.4760"); + values ("0.5790,0.5643,0.5507,0.5224,0.4726,0.3798,0.1952",\ +"0.5840,0.5694,0.5557,0.5274,0.4776,0.3848,0.2002",\ +"0.5884,0.5738,0.5601,0.5318,0.4820,0.3892,0.2046",\ +"0.5983,0.5836,0.5700,0.5416,0.4918,0.3991,0.2145",\ +"0.6046,0.5900,0.5763,0.5480,0.4982,0.4054,0.2208",\ +"0.6411,0.6265,0.6128,0.5845,0.5347,0.4419,0.2573",\ +"0.6920,0.6773,0.6637,0.6353,0.5855,0.4928,0.3082"); + } + } + } + +bus(A_DOUT) { + + bus_type : D_31_0; + direction : output ; + capacitance : 0 ; + max_capacitance : 0.064 ; + memory_read() { + address : A_ADDR ; + } + pin(A_DOUT[31:0]) { + related_power_pin : VDD; + related_ground_pin : VSS; + internal_power() { + rise_power("scalar") { + values (0); + } + fall_power("scalar") { + values (0); + } + } + } + timing() { + related_pin : "A_CLK"; + timing_type : rising_edge ; + timing_sense : non_unate ; + + cell_rise(SIG2SRAM_delay_template) { + index_1("0.0056,0.0232,0.0400,0.0728,0.1280,0.2440,0.4760"); + index_2("0.0008,0.0014,0.0051,0.0100,0.0339,0.0640"); + values ("4.4248,4.4264,4.4340,4.4427,4.4751,4.5113",\ +"4.4349,4.4365,4.4441,4.4529,4.4852,4.5214",\ +"4.4395,4.4411,4.4488,4.4575,4.4899,4.5260",\ +"4.4473,4.4489,4.4566,4.4653,4.4977,4.5338",\ +"4.4549,4.4565,4.4641,4.4728,4.5052,4.5413",\ +"4.4899,4.4916,4.4992,4.5079,4.5403,4.5764",\ +"4.5433,4.5449,4.5525,4.5612,4.5936,4.6298"); + } + cell_fall(SIG2SRAM_delay_template) { + index_1("0.0056,0.0232,0.0400,0.0728,0.1280,0.2440,0.4760"); + index_2("0.0008,0.0014,0.0051,0.0100,0.0339,0.0640"); + values ("4.3645,4.3658,4.3719,4.3790,4.4055,4.4318",\ +"4.3746,4.3759,4.3820,4.3892,4.4157,4.4419",\ +"4.3792,4.3806,4.3867,4.3938,4.4203,4.4465",\ +"4.3870,4.3884,4.3945,4.4016,4.4281,4.4543",\ +"4.3946,4.3959,4.4020,4.4091,4.4356,4.4618",\ +"4.4297,4.4310,4.4371,4.4442,4.4707,4.4969",\ +"4.4830,4.4843,4.4904,4.4975,4.5240,4.5503"); + } + + rise_transition(SRAM_load_template) { + index_1("0.0008,0.0014,0.0051,0.0100,0.0339,0.0640"); + values ("0.0326,0.0341,0.0428,0.0518,0.0923,0.1492"); + } + fall_transition(SRAM_load_template) { + index_1("0.0008,0.0014,0.0051,0.0100,0.0339,0.0640"); + values ("0.0254,0.0265,0.0335,0.0402,0.0707,0.1039"); + } + } +} + pin(B_DLY) { + direction : input ; + capacitance : 0.00401111 ; + max_transition : "1" ; + related_power_pin : VDD; + related_ground_pin : VSS; + internal_power() { + rise_power("scalar") { + values (0); + } + fall_power("scalar") { + values (0); + } + } + } + +bus(B_ADDR) { + bus_type : A_9_0; + direction : input ; + capacitance : 0.0121077 ; + pin(B_ADDR[0]) { + capacitance : 0.00570093 ; + } + pin(B_ADDR[1]) { + capacitance : 0.00764555 ; + } + pin(B_ADDR[2]) { + capacitance : 0.0105375 ; + } + pin(B_ADDR[3]) { + capacitance : 0.0067894 ; + } + pin(B_ADDR[4]) { + capacitance : 0.00630967 ; + } + pin(B_ADDR[5]) { + capacitance : 0.0104132 ; + } + pin(B_ADDR[6]) { + capacitance : 0.0131402 ; + } + pin(B_ADDR[7]) { + capacitance : 0.0105203 ; + } + pin(B_ADDR[8]) { + capacitance : 0.00910078 ; + } + max_transition : "0.476" ; + pin(B_ADDR[9:0]) { + related_power_pin : VDD; + related_ground_pin : VSS; + internal_power() { + when : "B_MEN"; + rise_power("scalar"){ + values (0.0115); + } + fall_power("scalar"){ + values (0.0061); + } + } + internal_power() { + when : "!B_MEN"; + rise_power("scalar"){ + values (0.0201); + } + fall_power("scalar"){ + values (0.0005); + } + } + } + timing() { + timing_type : setup_rising; + related_pin : "B_CLK"; + when : "((B_WEN | B_REN)& B_MEN)" + sdf_cond : "B_RW_ACCESS" + + rise_constraint("SIG2SRAM_constraint_template") { + index_1("0.0056,0.0232,0.0400,0.0728,0.1280,0.2440,0.4760"); + index_2("0.0056,0.0232,0.0400,0.0728,0.1280,0.2440,0.4760"); + values ("-0.4168,-0.3973,-0.3855,-0.3543,-0.3074,-0.2020,-0.0027",\ +"-0.4324,-0.4129,-0.4012,-0.3699,-0.3191,-0.2176,-0.0184",\ +"-0.4441,-0.4285,-0.4129,-0.3816,-0.3309,-0.2293,-0.0301",\ +"-0.4793,-0.4598,-0.4441,-0.4129,-0.3660,-0.2645,-0.0652",\ +"-0.5223,-0.5066,-0.4910,-0.4598,-0.4129,-0.3074,-0.1121",\ +"-0.6199,-0.6082,-0.5926,-0.5613,-0.5145,-0.4129,-0.2137",\ +"-0.8191,-0.8074,-0.7840,-0.7566,-0.7098,-0.6082,-0.4051"); + } + + fall_constraint("SIG2SRAM_constraint_template") { + index_1("0.0056,0.0232,0.0400,0.0728,0.1280,0.2440,0.4760"); + index_2("0.0056,0.0232,0.0400,0.0728,0.1280,0.2440,0.4760"); + values ("-0.3309,-0.3113,-0.2996,-0.2684,-0.2176,-0.1238,0.0637",\ +"-0.3465,-0.3309,-0.3152,-0.2840,-0.2332,-0.1395,0.0480",\ +"-0.3582,-0.3426,-0.3270,-0.2996,-0.2488,-0.1512,0.0324",\ +"-0.3895,-0.3738,-0.3582,-0.3309,-0.2801,-0.1863,0.0051",\ +"-0.4363,-0.4207,-0.4051,-0.3777,-0.3230,-0.2293,-0.0379",\ +"-0.5379,-0.5223,-0.5066,-0.4793,-0.4285,-0.3309,-0.1434",\ +"-0.7332,-0.7176,-0.7020,-0.6746,-0.6238,-0.5262,-0.3387"); + } + } + + + timing() { + timing_type : hold_rising; + related_pin : "B_CLK"; + when : "((B_WEN | B_REN)& B_MEN)" + sdf_cond : "B_RW_ACCESS" + + rise_constraint("SIG2SRAM_constraint_template") { + index_1("0.0056,0.0232,0.0400,0.0728,0.1280,0.2440,0.4760"); + index_2("0.0056,0.0232,0.0400,0.0728,0.1280,0.2440,0.4760"); + values ("0.5246,0.5051,0.4895,0.4582,0.4113,0.3059,0.1066",\ +"0.5402,0.5207,0.5051,0.4777,0.4270,0.3215,0.1223",\ +"0.5520,0.5324,0.5168,0.4895,0.4387,0.3371,0.1340",\ +"0.5832,0.5676,0.5520,0.5207,0.4738,0.3684,0.1691",\ +"0.6301,0.6105,0.5949,0.5676,0.5168,0.4113,0.2160",\ +"0.7316,0.7121,0.7004,0.6691,0.6223,0.5168,0.3176",\ +"0.9270,0.9230,0.8957,0.8645,0.8137,0.7121,0.5168"); + } + + fall_constraint("SIG2SRAM_constraint_template") { + index_1("0.0056,0.0232,0.0400,0.0728,0.1280,0.2440,0.4760"); + index_2("0.0056,0.0232,0.0400,0.0728,0.1280,0.2440,0.4760"); + values ("0.4309,0.4152,0.4035,0.3684,0.3215,0.2277,0.0363",\ +"0.4465,0.4309,0.4152,0.3879,0.3371,0.2395,0.0559",\ +"0.4582,0.4426,0.4309,0.3996,0.3488,0.2551,0.0715",\ +"0.4934,0.4777,0.4621,0.4348,0.3840,0.2863,0.0988",\ +"0.5363,0.5207,0.5051,0.4777,0.4270,0.3332,0.1418",\ +"0.6379,0.6262,0.6105,0.5793,0.5324,0.4348,0.2434",\ +"0.8332,0.8215,0.8059,0.7707,0.7238,0.6301,0.4387"); + } + } +} +pin(B_WEN) { + direction : input ; + capacitance : 0.00324098 ; + max_transition : "0.476" ; + related_power_pin : VDD; + related_ground_pin : VSS; + internal_power() { + when : "B_MEN"; + rise_power("scalar"){ + values (0.0046); + } + fall_power("scalar"){ + values (0.0040); + } + } + internal_power() { + when : "!B_MEN"; + rise_power("scalar"){ + values (0.0045); + } + fall_power("scalar"){ + values (0.0043); + } + } + timing() { + timing_type : setup_rising; + related_pin : "B_CLK"; + when : "B_MEN" + sdf_cond : "B_MEN" + + rise_constraint("SIG2SRAM_constraint_template") { + index_1("0.0056,0.0232,0.0400,0.0728,0.1280,0.2440,0.4760"); + index_2("0.0056,0.0232,0.0400,0.0728,0.1280,0.2440,0.4760"); + values ("0.2043,0.2199,0.2316,0.2629,0.3059,0.4113,0.6066",\ +"0.1887,0.2043,0.2160,0.2473,0.2941,0.3957,0.5949",\ +"0.1691,0.1848,0.2004,0.2316,0.2785,0.3801,0.5754",\ +"0.1379,0.1574,0.1691,0.2004,0.2473,0.3527,0.5480",\ +"0.0910,0.1066,0.1223,0.1535,0.2004,0.2980,0.4973",\ +"-0.0105,0.0051,0.0207,0.0520,0.0949,0.2004,0.3957",\ +"-0.2059,-0.1902,-0.1746,-0.1473,-0.1004,0.0051,0.2004"); + } + + fall_constraint("SIG2SRAM_constraint_template") { + index_1("0.0056,0.0232,0.0400,0.0728,0.1280,0.2440,0.4760"); + index_2("0.0056,0.0232,0.0400,0.0728,0.1280,0.2440,0.4760"); + values ("0.2941,0.3098,0.3215,0.3488,0.4035,0.4973,0.6887",\ +"0.2785,0.2941,0.3059,0.3332,0.3840,0.4816,0.6691",\ +"0.2629,0.2785,0.2902,0.3176,0.3684,0.4660,0.6535",\ +"0.2316,0.2473,0.2590,0.2863,0.3410,0.4348,0.6262",\ +"0.1848,0.2004,0.2121,0.2395,0.2902,0.3879,0.5754",\ +"0.0832,0.0988,0.1105,0.1379,0.1809,0.2746,0.4699",\ +"-0.1121,-0.0965,-0.0848,-0.0535,-0.0066,0.0910,0.2824"); + } + } + + + timing() { + timing_type : hold_rising; + related_pin : "B_CLK"; + when : "B_MEN" + sdf_cond : "B_MEN" + + rise_constraint("SIG2SRAM_constraint_template") { + index_1("0.0056,0.0232,0.0400,0.0728,0.1280,0.2440,0.4760"); + index_2("0.0056,0.0232,0.0400,0.0728,0.1280,0.2440,0.4760"); + values ("0.2473,0.2316,0.2160,0.1887,0.1379,0.0363,-0.1629",\ +"0.2629,0.2473,0.2316,0.2043,0.1535,0.0520,-0.1473",\ +"0.2785,0.2590,0.2434,0.2160,0.1652,0.0676,-0.1355",\ +"0.3098,0.2941,0.2785,0.2473,0.1965,0.0910,-0.1043",\ +"0.3527,0.3371,0.3215,0.2941,0.2434,0.1418,-0.0574",\ +"0.4582,0.4426,0.4270,0.3957,0.3488,0.2434,0.0480",\ +"0.6535,0.6379,0.6184,0.5910,0.5402,0.4426,0.2434"); + } + + fall_constraint("SIG2SRAM_constraint_template") { + index_1("0.0056,0.0232,0.0400,0.0728,0.1280,0.2440,0.4760"); + index_2("0.0056,0.0232,0.0400,0.0728,0.1280,0.2440,0.4760"); + values ("0.2395,0.2238,0.2121,0.1809,0.1301,0.0324,-0.1551",\ +"0.2551,0.2395,0.2277,0.1965,0.1457,0.0480,-0.1395",\ +"0.2668,0.2551,0.2395,0.2082,0.1574,0.0637,-0.1277",\ +"0.3020,0.2863,0.2707,0.2395,0.1887,0.0910,-0.0965",\ +"0.3449,0.3293,0.3176,0.2863,0.2355,0.1379,-0.0496",\ +"0.4504,0.4348,0.4191,0.3879,0.3371,0.2395,0.0559",\ +"0.6457,0.6301,0.6145,0.5871,0.5324,0.4309,0.2512"); + } + } + } +pin(B_REN) { + direction : input ; + capacitance : 0.00381634 ; + max_transition : "0.476" ; + related_power_pin : VDD; + related_ground_pin : VSS; + internal_power() { + when : "B_MEN"; + rise_power("scalar"){ + values (0.0061); + } + fall_power("scalar"){ + values (0.0022); + } + } + internal_power() { + when : "!B_MEN"; + rise_power("scalar"){ + values (0.0064); + } + fall_power("scalar"){ + values (0.0027); + } + } + timing() { + timing_type : setup_rising; + related_pin : "B_CLK"; + when : "B_MEN" + sdf_cond : "B_MEN" + + rise_constraint("SIG2SRAM_constraint_template") { + index_1("0.0056,0.0232,0.0400,0.0728,0.1280,0.2440,0.4760"); + index_2("0.0056,0.0232,0.0400,0.0728,0.1280,0.2440,0.4760"); + values ("-0.0301,-0.0145,0.0012,0.0324,0.0793,0.1809,0.3762",\ +"-0.0457,-0.0301,-0.0145,0.0168,0.0637,0.1613,0.3605",\ +"-0.0574,-0.0418,-0.0262,0.0051,0.0520,0.1496,0.3449",\ +"-0.0926,-0.0730,-0.0574,-0.0262,0.0207,0.1184,0.3137",\ +"-0.1395,-0.1238,-0.1082,-0.0770,-0.0301,0.0715,0.2707",\ +"-0.2410,-0.2254,-0.2098,-0.1746,-0.1355,-0.0340,0.1652",\ +"-0.4402,-0.4207,-0.4051,-0.3738,-0.3270,-0.2293,-0.0340"); + } + + fall_constraint("SIG2SRAM_constraint_template") { + index_1("0.0056,0.0232,0.0400,0.0728,0.1280,0.2440,0.4760"); + index_2("0.0056,0.0232,0.0400,0.0728,0.1280,0.2440,0.4760"); + values ("0.0988,0.1145,0.1262,0.1535,0.2043,0.3020,0.4855",\ +"0.0832,0.0988,0.1105,0.1418,0.1848,0.2824,0.4738",\ +"0.0676,0.0832,0.0949,0.1262,0.1730,0.2668,0.4621",\ +"0.0402,0.0559,0.0676,0.0988,0.1457,0.2434,0.4191",\ +"-0.0105,0.0012,0.0168,0.0480,0.0988,0.1965,0.3840",\ +"-0.1160,-0.0965,-0.0848,-0.0535,-0.0066,0.0988,0.2824",\ +"-0.3113,-0.2957,-0.2801,-0.2527,-0.2059,-0.1043,0.0832"); + } + } + + + timing() { + timing_type : hold_rising; + related_pin : "B_CLK"; + when : "B_MEN" + sdf_cond : "B_MEN" + + rise_constraint("SIG2SRAM_constraint_template") { + index_1("0.0056,0.0232,0.0400,0.0728,0.1280,0.2440,0.4760"); + index_2("0.0056,0.0232,0.0400,0.0728,0.1280,0.2440,0.4760"); + values ("0.2707,0.2551,0.2395,0.2121,0.1613,0.0598,-0.1395",\ +"0.2863,0.2707,0.2551,0.2238,0.1730,0.0715,-0.1238",\ +"0.2980,0.2824,0.2668,0.2395,0.1887,0.0871,-0.1121",\ +"0.3332,0.3176,0.3020,0.2707,0.2199,0.1184,-0.0809",\ +"0.3762,0.3605,0.3449,0.3176,0.2668,0.1613,-0.0340",\ +"0.4816,0.4621,0.4504,0.4191,0.3723,0.2629,0.0715",\ +"0.6770,0.6613,0.6418,0.6184,0.5637,0.4699,0.2629"); + } + + fall_constraint("SIG2SRAM_constraint_template") { + index_1("0.0056,0.0232,0.0400,0.0728,0.1280,0.2440,0.4760"); + index_2("0.0056,0.0232,0.0400,0.0728,0.1280,0.2440,0.4760"); + values ("0.2590,0.2434,0.2316,0.2004,0.1457,0.0520,-0.1355",\ +"0.2746,0.2590,0.2434,0.2160,0.1613,0.0676,-0.1199",\ +"0.2863,0.2707,0.2590,0.2277,0.1730,0.0832,-0.1082",\ +"0.3215,0.3059,0.2902,0.2590,0.2082,0.1105,-0.0770",\ +"0.3645,0.3488,0.3332,0.3059,0.2551,0.1535,-0.0340",\ +"0.4699,0.4543,0.4387,0.4074,0.3605,0.2551,0.0715",\ +"0.6652,0.6496,0.6340,0.6027,0.5520,0.4621,0.2707"); + } + } + } +pin(B_MEN) { + direction : input ; + capacitance : 0.00309605 ; + max_transition : "0.476" ; + related_power_pin : VDD; + related_ground_pin : VSS; + internal_power() { + rise_power("scalar"){ + values (0.0870); + } + fall_power("scalar"){ + values (0.0053); + } + } + timing() { + timing_type : setup_rising; + related_pin : "B_CLK"; + + rise_constraint("SIG2SRAM_constraint_template") { + index_1("0.0056,0.0232,0.0400,0.0728,0.1280,0.2440,0.4760"); + index_2("0.0056,0.0232,0.0400,0.0728,0.1280,0.2440,0.4760"); + values ("0.2043,0.2199,0.2316,0.2668,0.3098,0.4152,0.6066",\ +"0.1887,0.2043,0.2199,0.2512,0.2941,0.3996,0.5949",\ +"0.1730,0.1887,0.2043,0.2355,0.2824,0.3840,0.5793",\ +"0.1418,0.1574,0.1730,0.2043,0.2512,0.3566,0.5480",\ +"0.0949,0.1105,0.1262,0.1574,0.2043,0.3020,0.5051",\ +"-0.0066,0.0090,0.0246,0.0520,0.0988,0.2043,0.3996",\ +"-0.2020,-0.1863,-0.1746,-0.1434,-0.0965,0.0090,0.2082"); + } + + fall_constraint("SIG2SRAM_constraint_template") { + index_1("0.0056,0.0232,0.0400,0.0728,0.1280,0.2440,0.4760"); + index_2("0.0056,0.0232,0.0400,0.0728,0.1280,0.2440,0.4760"); + values ("0.2980,0.3137,0.3254,0.3527,0.4035,0.5012,0.6887",\ +"0.2824,0.2980,0.3098,0.3371,0.3879,0.4855,0.6730",\ +"0.2668,0.2824,0.2941,0.3215,0.3723,0.4699,0.6574",\ +"0.2355,0.2473,0.2629,0.2902,0.3410,0.4387,0.6262",\ +"0.1887,0.2004,0.2160,0.2395,0.2941,0.3918,0.5793",\ +"0.0871,0.1027,0.1145,0.1418,0.1848,0.2746,0.4816",\ +"-0.1082,-0.0965,-0.0809,-0.0496,-0.0027,0.0949,0.2863"); + } + } + + + timing() { + timing_type : hold_rising; + related_pin : "B_CLK"; + + rise_constraint("SIG2SRAM_constraint_template") { + index_1("0.0056,0.0232,0.0400,0.0728,0.1280,0.2440,0.4760"); + index_2("0.0056,0.0232,0.0400,0.0728,0.1280,0.2440,0.4760"); + values ("0.2512,0.2355,0.2199,0.1926,0.1418,0.0402,-0.1590",\ +"0.2668,0.2512,0.2355,0.2082,0.1574,0.0559,-0.1434",\ +"0.2824,0.2629,0.2512,0.2199,0.1691,0.0715,-0.1316",\ +"0.3137,0.2980,0.2824,0.2512,0.2004,0.0988,-0.0965",\ +"0.3566,0.3410,0.3254,0.2980,0.2473,0.1418,-0.0535",\ +"0.4621,0.4426,0.4309,0.3996,0.3527,0.2473,0.0520",\ +"0.6574,0.6418,0.6262,0.5949,0.5441,0.4465,0.2473"); + } + + fall_constraint("SIG2SRAM_constraint_template") { + index_1("0.0056,0.0232,0.0400,0.0728,0.1280,0.2440,0.4760"); + index_2("0.0056,0.0232,0.0400,0.0728,0.1280,0.2440,0.4760"); + values ("0.2395,0.2238,0.2121,0.1809,0.1301,0.0324,-0.1551",\ +"0.2551,0.2434,0.2277,0.1965,0.1457,0.0480,-0.1395",\ +"0.2707,0.2551,0.2395,0.2082,0.1574,0.0637,-0.1277",\ +"0.3020,0.2863,0.2707,0.2434,0.1926,0.0910,-0.0965",\ +"0.3449,0.3332,0.3176,0.2863,0.2355,0.1379,-0.0496",\ +"0.4504,0.4348,0.4230,0.3918,0.3410,0.2434,0.0559",\ +"0.6457,0.6301,0.6145,0.5910,0.5324,0.4387,0.2512"); + } + } + } +bus(B_BM) { + bus_type : D_31_0; + direction : input ; + capacitance : 0.00312518 ; + max_transition : "0.476" ; + pin(B_BM[31:0]) { + related_power_pin : VDD; + related_ground_pin : VSS; + internal_power() { + when : "B_MEN"; + rise_power("scalar"){ + values (0.1177); + } + fall_power("scalar"){ + values (0.0495); + } + } + internal_power() { + when : "!B_MEN"; + rise_power("scalar"){ + values (0.1175); + } + fall_power("scalar"){ + values (0.0489); + } + } + } + timing() { + timing_type : setup_rising; + related_pin : "B_CLK"; + when : "(B_WEN & B_MEN)" + sdf_cond : "B_RW_ACCESS" + + rise_constraint("SIG2SRAM_constraint_template") { + index_1("0.0056,0.0232,0.0400,0.0728,0.1280,0.2440,0.4760"); + index_2("0.0056,0.0232,0.0400,0.0728,0.1280,0.2440,0.4760"); + values ("-0.5145,-0.4989,-0.4852,-0.4530,-0.4061,-0.3016,-0.1102",\ +"-0.5195,-0.5039,-0.4902,-0.4580,-0.4111,-0.3067,-0.1152",\ +"-0.5240,-0.5083,-0.4947,-0.4624,-0.4156,-0.3111,-0.1197",\ +"-0.5338,-0.5182,-0.5045,-0.4723,-0.4254,-0.3209,-0.1295",\ +"-0.5402,-0.5245,-0.5109,-0.4786,-0.4318,-0.3273,-0.1359",\ +"-0.5767,-0.5610,-0.5474,-0.5151,-0.4683,-0.3638,-0.1724",\ +"-0.6275,-0.6119,-0.5982,-0.5660,-0.5191,-0.4146,-0.2232"); + } + + fall_constraint("SIG2SRAM_constraint_template") { + index_1("0.0056,0.0232,0.0400,0.0728,0.1280,0.2440,0.4760"); + index_2("0.0056,0.0232,0.0400,0.0728,0.1280,0.2440,0.4760"); + values ("-0.4764,-0.4618,-0.4481,-0.4198,-0.3690,-0.2714,-0.0887",\ +"-0.4815,-0.4668,-0.4531,-0.4248,-0.3740,-0.2764,-0.0938",\ +"-0.4859,-0.4712,-0.4576,-0.4292,-0.3785,-0.2808,-0.0982",\ +"-0.4957,-0.4811,-0.4674,-0.4391,-0.3883,-0.2907,-0.1080",\ +"-0.5021,-0.4874,-0.4738,-0.4454,-0.3947,-0.2970,-0.1144",\ +"-0.5386,-0.5239,-0.5102,-0.4819,-0.4311,-0.3335,-0.1509",\ +"-0.5894,-0.5748,-0.5611,-0.5328,-0.4820,-0.3844,-0.2017"); + } + } + + + timing() { + timing_type : hold_rising; + related_pin : "B_CLK"; + when : "(B_WEN & B_MEN)" + sdf_cond : "B_RW_ACCESS" + + rise_constraint("SIG2SRAM_constraint_template") { + index_1("0.0056,0.0232,0.0400,0.0728,0.1280,0.2440,0.4760"); + index_2("0.0056,0.0232,0.0400,0.0728,0.1280,0.2440,0.4760"); + values ("0.6249,0.6083,0.5956,0.5634,0.5155,0.4120,0.2196",\ +"0.6299,0.6133,0.6006,0.5684,0.5205,0.4170,0.2246",\ +"0.6343,0.6177,0.6050,0.5728,0.5250,0.4214,0.2291",\ +"0.6442,0.6276,0.6149,0.5827,0.5348,0.4313,0.2389",\ +"0.6505,0.6339,0.6212,0.5890,0.5412,0.4376,0.2453",\ +"0.6870,0.6704,0.6577,0.6255,0.5776,0.4741,0.2817",\ +"0.7379,0.7213,0.7086,0.6764,0.6285,0.5250,0.3326"); + } + + fall_constraint("SIG2SRAM_constraint_template") { + index_1("0.0056,0.0232,0.0400,0.0728,0.1280,0.2440,0.4760"); + index_2("0.0056,0.0232,0.0400,0.0728,0.1280,0.2440,0.4760"); + values ("0.5790,0.5643,0.5507,0.5224,0.4726,0.3798,0.1952",\ +"0.5840,0.5694,0.5557,0.5274,0.4776,0.3848,0.2002",\ +"0.5884,0.5738,0.5601,0.5318,0.4820,0.3892,0.2046",\ +"0.5983,0.5836,0.5700,0.5416,0.4918,0.3991,0.2145",\ +"0.6046,0.5900,0.5763,0.5480,0.4982,0.4054,0.2208",\ +"0.6411,0.6265,0.6128,0.5845,0.5347,0.4419,0.2573",\ +"0.6920,0.6773,0.6637,0.6353,0.5855,0.4928,0.3082"); + } + } +} + pin(B_CLK) { + direction : input; + capacitance : 0.00380014; + max_transition : "0.476"; + clock : "true" ; + pin_func_type : active_rising ; + + timing () { + timing_type : "min_pulse_width"; + related_pin : "B_CLK"; + rise_constraint("CLKTRAN_constraint_template") { + index_1("0.0056,0.476"); + values("0.21,0.21"); + } + } + + related_power_pin : VDD; + related_ground_pin : VSS; + + internal_power() { + when : "!B_MEN & !B_WEN & !B_REN"; + rise_power("scalar"){ + values (0); + } + fall_power("scalar"){ + values (0); + } + } + internal_power() { + when : "!B_MEN & B_WEN & !B_REN"; + rise_power("scalar"){ + values (0.5298); + } + fall_power("scalar"){ + values (0); + } + } + internal_power() { + when : "B_MEN & B_WEN & !B_REN"; + rise_power("scalar"){ + values (58.9183); + } + fall_power("scalar"){ + values (0); + } + } + internal_power() { + when : "B_MEN & B_WEN & B_REN"; + rise_power("scalar"){ + values (61.8765); + } + fall_power("scalar"){ + values (0); + } + } + internal_power() { + when : "B_MEN & !B_WEN & B_REN"; + rise_power("scalar"){ + values (48.2666); + } + fall_power("scalar"){ + values (0); + } + } + internal_power() { + when : "!B_MEN & !B_WEN & B_REN"; + rise_power("scalar"){ + values (0.3622); + } + fall_power("scalar"){ + values (0); + } + } + internal_power() { + when : "!B_MEN & B_WEN & B_REN"; + rise_power("scalar"){ + values (1.2134); + } + fall_power("scalar"){ + values (0); + } + } + internal_power() { + when : "B_MEN & !B_WEN & !B_REN"; + rise_power("scalar"){ + values (0); + } + fall_power("scalar"){ + values (0); + } + } + } + bus(B_DIN) { + bus_type : D_31_0; + direction : input ; + capacitance : 0.00461776 ; + memory_write() { + address : B_ADDR ; + clocked_on : B_CLK; + } + + max_transition : "0.476" ; + pin(B_DIN[31:0]) { + related_power_pin : VDD; + related_ground_pin : VSS; + internal_power() { + when : "B_MEN"; + rise_power("scalar"){ + values (0.1177); + } + fall_power("scalar"){ + values (0.0495); + } + } + internal_power() { + when : "!B_MEN"; + rise_power("scalar"){ + values (0.1175); + } + fall_power("scalar"){ + values (0.0489); + } + } + } + timing() { + timing_type : setup_rising; + related_pin : "B_CLK"; + when : "(B_WEN & B_MEN)"; + sdf_cond : "B_W_ACCESS"; + + rise_constraint("SIG2SRAM_constraint_template") { + index_1("0.0056,0.0232,0.0400,0.0728,0.1280,0.2440,0.4760"); + index_2("0.0056,0.0232,0.0400,0.0728,0.1280,0.2440,0.4760"); + values ("-0.5145,-0.4989,-0.4852,-0.4530,-0.4061,-0.3016,-0.1102",\ +"-0.5195,-0.5039,-0.4902,-0.4580,-0.4111,-0.3067,-0.1152",\ +"-0.5240,-0.5083,-0.4947,-0.4624,-0.4156,-0.3111,-0.1197",\ +"-0.5338,-0.5182,-0.5045,-0.4723,-0.4254,-0.3209,-0.1295",\ +"-0.5402,-0.5245,-0.5109,-0.4786,-0.4318,-0.3273,-0.1359",\ +"-0.5767,-0.5610,-0.5474,-0.5151,-0.4683,-0.3638,-0.1724",\ +"-0.6275,-0.6119,-0.5982,-0.5660,-0.5191,-0.4146,-0.2232"); + } + + fall_constraint("SIG2SRAM_constraint_template") { + index_1("0.0056,0.0232,0.0400,0.0728,0.1280,0.2440,0.4760"); + index_2("0.0056,0.0232,0.0400,0.0728,0.1280,0.2440,0.4760"); + values ("-0.4764,-0.4618,-0.4481,-0.4198,-0.3690,-0.2714,-0.0887",\ +"-0.4815,-0.4668,-0.4531,-0.4248,-0.3740,-0.2764,-0.0938",\ +"-0.4859,-0.4712,-0.4576,-0.4292,-0.3785,-0.2808,-0.0982",\ +"-0.4957,-0.4811,-0.4674,-0.4391,-0.3883,-0.2907,-0.1080",\ +"-0.5021,-0.4874,-0.4738,-0.4454,-0.3947,-0.2970,-0.1144",\ +"-0.5386,-0.5239,-0.5102,-0.4819,-0.4311,-0.3335,-0.1509",\ +"-0.5894,-0.5748,-0.5611,-0.5328,-0.4820,-0.3844,-0.2017"); + } + } + + timing() { + timing_type : hold_rising; + related_pin : "B_CLK"; + when : "(B_WEN & B_MEN)"; + sdf_cond : "B_W_ACCESS"; + + rise_constraint("SIG2SRAM_constraint_template") { + index_1("0.0056,0.0232,0.0400,0.0728,0.1280,0.2440,0.4760"); + index_2("0.0056,0.0232,0.0400,0.0728,0.1280,0.2440,0.4760"); + values ("0.6249,0.6083,0.5956,0.5634,0.5155,0.4120,0.2196",\ +"0.6299,0.6133,0.6006,0.5684,0.5205,0.4170,0.2246",\ +"0.6343,0.6177,0.6050,0.5728,0.5250,0.4214,0.2291",\ +"0.6442,0.6276,0.6149,0.5827,0.5348,0.4313,0.2389",\ +"0.6505,0.6339,0.6212,0.5890,0.5412,0.4376,0.2453",\ +"0.6870,0.6704,0.6577,0.6255,0.5776,0.4741,0.2817",\ +"0.7379,0.7213,0.7086,0.6764,0.6285,0.5250,0.3326"); + } + + fall_constraint("SIG2SRAM_constraint_template") { + index_1("0.0056,0.0232,0.0400,0.0728,0.1280,0.2440,0.4760"); + index_2("0.0056,0.0232,0.0400,0.0728,0.1280,0.2440,0.4760"); + values ("0.5790,0.5643,0.5507,0.5224,0.4726,0.3798,0.1952",\ +"0.5840,0.5694,0.5557,0.5274,0.4776,0.3848,0.2002",\ +"0.5884,0.5738,0.5601,0.5318,0.4820,0.3892,0.2046",\ +"0.5983,0.5836,0.5700,0.5416,0.4918,0.3991,0.2145",\ +"0.6046,0.5900,0.5763,0.5480,0.4982,0.4054,0.2208",\ +"0.6411,0.6265,0.6128,0.5845,0.5347,0.4419,0.2573",\ +"0.6920,0.6773,0.6637,0.6353,0.5855,0.4928,0.3082"); + } + } + } + + pin(B_BIST_EN) { + direction : input ; + capacitance : 0.00401111 ; + max_transition : "1" ; + related_power_pin : VDD; + related_ground_pin : VSS; + internal_power() { + rise_power("scalar") { + values (0); + } + fall_power("scalar") { + values (0); + } + } + } + +bus(B_BIST_ADDR) { + bus_type : A_9_0; + direction : input ; + capacitance : 0.0121077 ; + pin(B_BIST_ADDR[0]) { + capacitance : 0.00570093 ; + } + pin(B_BIST_ADDR[1]) { + capacitance : 0.00764555 ; + } + pin(B_BIST_ADDR[2]) { + capacitance : 0.0105375 ; + } + pin(B_BIST_ADDR[3]) { + capacitance : 0.0067894 ; + } + pin(B_BIST_ADDR[4]) { + capacitance : 0.00630967 ; + } + pin(B_BIST_ADDR[5]) { + capacitance : 0.0104132 ; + } + pin(B_BIST_ADDR[6]) { + capacitance : 0.0131402 ; + } + pin(B_BIST_ADDR[7]) { + capacitance : 0.0105203 ; + } + pin(B_BIST_ADDR[8]) { + capacitance : 0.00910078 ; + } + max_transition : "0.476" ; + pin(B_BIST_ADDR[9:0]) { + related_power_pin : VDD; + related_ground_pin : VSS; + internal_power() { + when : "B_BIST_MEN"; + rise_power("scalar"){ + values (0.0115); + } + fall_power("scalar"){ + values (0.0061); + } + } + internal_power() { + when : "!B_BIST_MEN"; + rise_power("scalar"){ + values (0.0201); + } + fall_power("scalar"){ + values (0.0005); + } + } + } + timing() { + timing_type : setup_rising; + related_pin : "B_BIST_CLK"; + when : "((B_BIST_WEN | B_BIST_REN)& B_BIST_MEN)" + sdf_cond : "B_BIST_RW_ACCESS" + + rise_constraint("SIG2SRAM_constraint_template") { + index_1("0.0056,0.0232,0.0400,0.0728,0.1280,0.2440,0.4760"); + index_2("0.0056,0.0232,0.0400,0.0728,0.1280,0.2440,0.4760"); + values ("-0.4168,-0.3973,-0.3855,-0.3543,-0.3074,-0.2020,-0.0027",\ +"-0.4324,-0.4129,-0.4012,-0.3699,-0.3191,-0.2176,-0.0184",\ +"-0.4441,-0.4285,-0.4129,-0.3816,-0.3309,-0.2293,-0.0301",\ +"-0.4793,-0.4598,-0.4441,-0.4129,-0.3660,-0.2645,-0.0652",\ +"-0.5223,-0.5066,-0.4910,-0.4598,-0.4129,-0.3074,-0.1121",\ +"-0.6199,-0.6082,-0.5926,-0.5613,-0.5145,-0.4129,-0.2137",\ +"-0.8191,-0.8074,-0.7840,-0.7566,-0.7098,-0.6082,-0.4051"); + } + + fall_constraint("SIG2SRAM_constraint_template") { + index_1("0.0056,0.0232,0.0400,0.0728,0.1280,0.2440,0.4760"); + index_2("0.0056,0.0232,0.0400,0.0728,0.1280,0.2440,0.4760"); + values ("-0.3309,-0.3113,-0.2996,-0.2684,-0.2176,-0.1238,0.0637",\ +"-0.3465,-0.3309,-0.3152,-0.2840,-0.2332,-0.1395,0.0480",\ +"-0.3582,-0.3426,-0.3270,-0.2996,-0.2488,-0.1512,0.0324",\ +"-0.3895,-0.3738,-0.3582,-0.3309,-0.2801,-0.1863,0.0051",\ +"-0.4363,-0.4207,-0.4051,-0.3777,-0.3230,-0.2293,-0.0379",\ +"-0.5379,-0.5223,-0.5066,-0.4793,-0.4285,-0.3309,-0.1434",\ +"-0.7332,-0.7176,-0.7020,-0.6746,-0.6238,-0.5262,-0.3387"); + } + } + + + timing() { + timing_type : hold_rising; + related_pin : "B_BIST_CLK"; + when : "((B_BIST_WEN | B_BIST_REN)& B_BIST_MEN)" + sdf_cond : "B_BIST_RW_ACCESS" + + rise_constraint("SIG2SRAM_constraint_template") { + index_1("0.0056,0.0232,0.0400,0.0728,0.1280,0.2440,0.4760"); + index_2("0.0056,0.0232,0.0400,0.0728,0.1280,0.2440,0.4760"); + values ("0.5246,0.5051,0.4895,0.4582,0.4113,0.3059,0.1066",\ +"0.5402,0.5207,0.5051,0.4777,0.4270,0.3215,0.1223",\ +"0.5520,0.5324,0.5168,0.4895,0.4387,0.3371,0.1340",\ +"0.5832,0.5676,0.5520,0.5207,0.4738,0.3684,0.1691",\ +"0.6301,0.6105,0.5949,0.5676,0.5168,0.4113,0.2160",\ +"0.7316,0.7121,0.7004,0.6691,0.6223,0.5168,0.3176",\ +"0.9270,0.9230,0.8957,0.8645,0.8137,0.7121,0.5168"); + } + + fall_constraint("SIG2SRAM_constraint_template") { + index_1("0.0056,0.0232,0.0400,0.0728,0.1280,0.2440,0.4760"); + index_2("0.0056,0.0232,0.0400,0.0728,0.1280,0.2440,0.4760"); + values ("0.4309,0.4152,0.4035,0.3684,0.3215,0.2277,0.0363",\ +"0.4465,0.4309,0.4152,0.3879,0.3371,0.2395,0.0559",\ +"0.4582,0.4426,0.4309,0.3996,0.3488,0.2551,0.0715",\ +"0.4934,0.4777,0.4621,0.4348,0.3840,0.2863,0.0988",\ +"0.5363,0.5207,0.5051,0.4777,0.4270,0.3332,0.1418",\ +"0.6379,0.6262,0.6105,0.5793,0.5324,0.4348,0.2434",\ +"0.8332,0.8215,0.8059,0.7707,0.7238,0.6301,0.4387"); + } + } +} +pin(B_BIST_WEN) { + direction : input ; + capacitance : 0.00324098 ; + max_transition : "0.476" ; + related_power_pin : VDD; + related_ground_pin : VSS; + internal_power() { + when : "B_BIST_MEN"; + rise_power("scalar"){ + values (0.0046); + } + fall_power("scalar"){ + values (0.0040); + } + } + internal_power() { + when : "!B_BIST_MEN"; + rise_power("scalar"){ + values (0.0045); + } + fall_power("scalar"){ + values (0.0043); + } + } + timing() { + timing_type : setup_rising; + related_pin : "B_BIST_CLK"; + when : "B_BIST_MEN" + sdf_cond : "B_BIST_MEN" + + rise_constraint("SIG2SRAM_constraint_template") { + index_1("0.0056,0.0232,0.0400,0.0728,0.1280,0.2440,0.4760"); + index_2("0.0056,0.0232,0.0400,0.0728,0.1280,0.2440,0.4760"); + values ("0.2043,0.2199,0.2316,0.2629,0.3059,0.4113,0.6066",\ +"0.1887,0.2043,0.2160,0.2473,0.2941,0.3957,0.5949",\ +"0.1691,0.1848,0.2004,0.2316,0.2785,0.3801,0.5754",\ +"0.1379,0.1574,0.1691,0.2004,0.2473,0.3527,0.5480",\ +"0.0910,0.1066,0.1223,0.1535,0.2004,0.2980,0.4973",\ +"-0.0105,0.0051,0.0207,0.0520,0.0949,0.2004,0.3957",\ +"-0.2059,-0.1902,-0.1746,-0.1473,-0.1004,0.0051,0.2004"); + } + + fall_constraint("SIG2SRAM_constraint_template") { + index_1("0.0056,0.0232,0.0400,0.0728,0.1280,0.2440,0.4760"); + index_2("0.0056,0.0232,0.0400,0.0728,0.1280,0.2440,0.4760"); + values ("0.2941,0.3098,0.3215,0.3488,0.4035,0.4973,0.6887",\ +"0.2785,0.2941,0.3059,0.3332,0.3840,0.4816,0.6691",\ +"0.2629,0.2785,0.2902,0.3176,0.3684,0.4660,0.6535",\ +"0.2316,0.2473,0.2590,0.2863,0.3410,0.4348,0.6262",\ +"0.1848,0.2004,0.2121,0.2395,0.2902,0.3879,0.5754",\ +"0.0832,0.0988,0.1105,0.1379,0.1809,0.2746,0.4699",\ +"-0.1121,-0.0965,-0.0848,-0.0535,-0.0066,0.0910,0.2824"); + } + } + + + timing() { + timing_type : hold_rising; + related_pin : "B_BIST_CLK"; + when : "B_BIST_MEN" + sdf_cond : "B_BIST_MEN" + + rise_constraint("SIG2SRAM_constraint_template") { + index_1("0.0056,0.0232,0.0400,0.0728,0.1280,0.2440,0.4760"); + index_2("0.0056,0.0232,0.0400,0.0728,0.1280,0.2440,0.4760"); + values ("0.2473,0.2316,0.2160,0.1887,0.1379,0.0363,-0.1629",\ +"0.2629,0.2473,0.2316,0.2043,0.1535,0.0520,-0.1473",\ +"0.2785,0.2590,0.2434,0.2160,0.1652,0.0676,-0.1355",\ +"0.3098,0.2941,0.2785,0.2473,0.1965,0.0910,-0.1043",\ +"0.3527,0.3371,0.3215,0.2941,0.2434,0.1418,-0.0574",\ +"0.4582,0.4426,0.4270,0.3957,0.3488,0.2434,0.0480",\ +"0.6535,0.6379,0.6184,0.5910,0.5402,0.4426,0.2434"); + } + + fall_constraint("SIG2SRAM_constraint_template") { + index_1("0.0056,0.0232,0.0400,0.0728,0.1280,0.2440,0.4760"); + index_2("0.0056,0.0232,0.0400,0.0728,0.1280,0.2440,0.4760"); + values ("0.2395,0.2238,0.2121,0.1809,0.1301,0.0324,-0.1551",\ +"0.2551,0.2395,0.2277,0.1965,0.1457,0.0480,-0.1395",\ +"0.2668,0.2551,0.2395,0.2082,0.1574,0.0637,-0.1277",\ +"0.3020,0.2863,0.2707,0.2395,0.1887,0.0910,-0.0965",\ +"0.3449,0.3293,0.3176,0.2863,0.2355,0.1379,-0.0496",\ +"0.4504,0.4348,0.4191,0.3879,0.3371,0.2395,0.0559",\ +"0.6457,0.6301,0.6145,0.5871,0.5324,0.4309,0.2512"); + } + } + } +pin(B_BIST_REN) { + direction : input ; + capacitance : 0.00381634 ; + max_transition : "0.476" ; + related_power_pin : VDD; + related_ground_pin : VSS; + internal_power() { + when : "B_BIST_MEN"; + rise_power("scalar"){ + values (0.0061); + } + fall_power("scalar"){ + values (0.0022); + } + } + internal_power() { + when : "!B_BIST_MEN"; + rise_power("scalar"){ + values (0.0064); + } + fall_power("scalar"){ + values (0.0027); + } + } + timing() { + timing_type : setup_rising; + related_pin : "B_BIST_CLK"; + when : "B_BIST_MEN" + sdf_cond : "B_BIST_MEN" + + rise_constraint("SIG2SRAM_constraint_template") { + index_1("0.0056,0.0232,0.0400,0.0728,0.1280,0.2440,0.4760"); + index_2("0.0056,0.0232,0.0400,0.0728,0.1280,0.2440,0.4760"); + values ("-0.0301,-0.0145,0.0012,0.0324,0.0793,0.1809,0.3762",\ +"-0.0457,-0.0301,-0.0145,0.0168,0.0637,0.1613,0.3605",\ +"-0.0574,-0.0418,-0.0262,0.0051,0.0520,0.1496,0.3449",\ +"-0.0926,-0.0730,-0.0574,-0.0262,0.0207,0.1184,0.3137",\ +"-0.1395,-0.1238,-0.1082,-0.0770,-0.0301,0.0715,0.2707",\ +"-0.2410,-0.2254,-0.2098,-0.1746,-0.1355,-0.0340,0.1652",\ +"-0.4402,-0.4207,-0.4051,-0.3738,-0.3270,-0.2293,-0.0340"); + } + + fall_constraint("SIG2SRAM_constraint_template") { + index_1("0.0056,0.0232,0.0400,0.0728,0.1280,0.2440,0.4760"); + index_2("0.0056,0.0232,0.0400,0.0728,0.1280,0.2440,0.4760"); + values ("0.0988,0.1145,0.1262,0.1535,0.2043,0.3020,0.4855",\ +"0.0832,0.0988,0.1105,0.1418,0.1848,0.2824,0.4738",\ +"0.0676,0.0832,0.0949,0.1262,0.1730,0.2668,0.4621",\ +"0.0402,0.0559,0.0676,0.0988,0.1457,0.2434,0.4191",\ +"-0.0105,0.0012,0.0168,0.0480,0.0988,0.1965,0.3840",\ +"-0.1160,-0.0965,-0.0848,-0.0535,-0.0066,0.0988,0.2824",\ +"-0.3113,-0.2957,-0.2801,-0.2527,-0.2059,-0.1043,0.0832"); + } + } + + + timing() { + timing_type : hold_rising; + related_pin : "B_BIST_CLK"; + when : "B_BIST_MEN" + sdf_cond : "B_BIST_MEN" + + rise_constraint("SIG2SRAM_constraint_template") { + index_1("0.0056,0.0232,0.0400,0.0728,0.1280,0.2440,0.4760"); + index_2("0.0056,0.0232,0.0400,0.0728,0.1280,0.2440,0.4760"); + values ("0.2707,0.2551,0.2395,0.2121,0.1613,0.0598,-0.1395",\ +"0.2863,0.2707,0.2551,0.2238,0.1730,0.0715,-0.1238",\ +"0.2980,0.2824,0.2668,0.2395,0.1887,0.0871,-0.1121",\ +"0.3332,0.3176,0.3020,0.2707,0.2199,0.1184,-0.0809",\ +"0.3762,0.3605,0.3449,0.3176,0.2668,0.1613,-0.0340",\ +"0.4816,0.4621,0.4504,0.4191,0.3723,0.2629,0.0715",\ +"0.6770,0.6613,0.6418,0.6184,0.5637,0.4699,0.2629"); + } + + fall_constraint("SIG2SRAM_constraint_template") { + index_1("0.0056,0.0232,0.0400,0.0728,0.1280,0.2440,0.4760"); + index_2("0.0056,0.0232,0.0400,0.0728,0.1280,0.2440,0.4760"); + values ("0.2590,0.2434,0.2316,0.2004,0.1457,0.0520,-0.1355",\ +"0.2746,0.2590,0.2434,0.2160,0.1613,0.0676,-0.1199",\ +"0.2863,0.2707,0.2590,0.2277,0.1730,0.0832,-0.1082",\ +"0.3215,0.3059,0.2902,0.2590,0.2082,0.1105,-0.0770",\ +"0.3645,0.3488,0.3332,0.3059,0.2551,0.1535,-0.0340",\ +"0.4699,0.4543,0.4387,0.4074,0.3605,0.2551,0.0715",\ +"0.6652,0.6496,0.6340,0.6027,0.5520,0.4621,0.2707"); + } + } + } +pin(B_BIST_MEN) { + direction : input ; + capacitance : 0.00309605 ; + max_transition : "0.476" ; + related_power_pin : VDD; + related_ground_pin : VSS; + internal_power() { + rise_power("scalar"){ + values (0.0870); + } + fall_power("scalar"){ + values (0.0053); + } + } + timing() { + timing_type : setup_rising; + related_pin : "B_BIST_CLK"; + + rise_constraint("SIG2SRAM_constraint_template") { + index_1("0.0056,0.0232,0.0400,0.0728,0.1280,0.2440,0.4760"); + index_2("0.0056,0.0232,0.0400,0.0728,0.1280,0.2440,0.4760"); + values ("0.2043,0.2199,0.2316,0.2668,0.3098,0.4152,0.6066",\ +"0.1887,0.2043,0.2199,0.2512,0.2941,0.3996,0.5949",\ +"0.1730,0.1887,0.2043,0.2355,0.2824,0.3840,0.5793",\ +"0.1418,0.1574,0.1730,0.2043,0.2512,0.3566,0.5480",\ +"0.0949,0.1105,0.1262,0.1574,0.2043,0.3020,0.5051",\ +"-0.0066,0.0090,0.0246,0.0520,0.0988,0.2043,0.3996",\ +"-0.2020,-0.1863,-0.1746,-0.1434,-0.0965,0.0090,0.2082"); + } + + fall_constraint("SIG2SRAM_constraint_template") { + index_1("0.0056,0.0232,0.0400,0.0728,0.1280,0.2440,0.4760"); + index_2("0.0056,0.0232,0.0400,0.0728,0.1280,0.2440,0.4760"); + values ("0.2980,0.3137,0.3254,0.3527,0.4035,0.5012,0.6887",\ +"0.2824,0.2980,0.3098,0.3371,0.3879,0.4855,0.6730",\ +"0.2668,0.2824,0.2941,0.3215,0.3723,0.4699,0.6574",\ +"0.2355,0.2473,0.2629,0.2902,0.3410,0.4387,0.6262",\ +"0.1887,0.2004,0.2160,0.2395,0.2941,0.3918,0.5793",\ +"0.0871,0.1027,0.1145,0.1418,0.1848,0.2746,0.4816",\ +"-0.1082,-0.0965,-0.0809,-0.0496,-0.0027,0.0949,0.2863"); + } + } + + + timing() { + timing_type : hold_rising; + related_pin : "B_BIST_CLK"; + + rise_constraint("SIG2SRAM_constraint_template") { + index_1("0.0056,0.0232,0.0400,0.0728,0.1280,0.2440,0.4760"); + index_2("0.0056,0.0232,0.0400,0.0728,0.1280,0.2440,0.4760"); + values ("0.2512,0.2355,0.2199,0.1926,0.1418,0.0402,-0.1590",\ +"0.2668,0.2512,0.2355,0.2082,0.1574,0.0559,-0.1434",\ +"0.2824,0.2629,0.2512,0.2199,0.1691,0.0715,-0.1316",\ +"0.3137,0.2980,0.2824,0.2512,0.2004,0.0988,-0.0965",\ +"0.3566,0.3410,0.3254,0.2980,0.2473,0.1418,-0.0535",\ +"0.4621,0.4426,0.4309,0.3996,0.3527,0.2473,0.0520",\ +"0.6574,0.6418,0.6262,0.5949,0.5441,0.4465,0.2473"); + } + + fall_constraint("SIG2SRAM_constraint_template") { + index_1("0.0056,0.0232,0.0400,0.0728,0.1280,0.2440,0.4760"); + index_2("0.0056,0.0232,0.0400,0.0728,0.1280,0.2440,0.4760"); + values ("0.2395,0.2238,0.2121,0.1809,0.1301,0.0324,-0.1551",\ +"0.2551,0.2434,0.2277,0.1965,0.1457,0.0480,-0.1395",\ +"0.2707,0.2551,0.2395,0.2082,0.1574,0.0637,-0.1277",\ +"0.3020,0.2863,0.2707,0.2434,0.1926,0.0910,-0.0965",\ +"0.3449,0.3332,0.3176,0.2863,0.2355,0.1379,-0.0496",\ +"0.4504,0.4348,0.4230,0.3918,0.3410,0.2434,0.0559",\ +"0.6457,0.6301,0.6145,0.5910,0.5324,0.4387,0.2512"); + } + } + } +bus(B_BIST_BM) { + bus_type : D_31_0; + direction : input ; + capacitance : 0.00275526 ; + max_transition : "0.476" ; + pin(B_BIST_BM[31:0]) { + related_power_pin : VDD; + related_ground_pin : VSS; + internal_power() { + when : "B_BIST_MEN"; + rise_power("scalar"){ + values (0.1177); + } + fall_power("scalar"){ + values (0.0495); + } + } + internal_power() { + when : "!B_BIST_MEN"; + rise_power("scalar"){ + values (0.1175); + } + fall_power("scalar"){ + values (0.0489); + } + } + } + timing() { + timing_type : setup_rising; + related_pin : "B_BIST_CLK"; + when : "(B_BIST_WEN & B_BIST_MEN)" + sdf_cond : "B_BIST_RW_ACCESS" + + rise_constraint("SIG2SRAM_constraint_template") { + index_1("0.0056,0.0232,0.0400,0.0728,0.1280,0.2440,0.4760"); + index_2("0.0056,0.0232,0.0400,0.0728,0.1280,0.2440,0.4760"); + values ("-0.5145,-0.4989,-0.4852,-0.4530,-0.4061,-0.3016,-0.1102",\ +"-0.5195,-0.5039,-0.4902,-0.4580,-0.4111,-0.3067,-0.1152",\ +"-0.5240,-0.5083,-0.4947,-0.4624,-0.4156,-0.3111,-0.1197",\ +"-0.5338,-0.5182,-0.5045,-0.4723,-0.4254,-0.3209,-0.1295",\ +"-0.5402,-0.5245,-0.5109,-0.4786,-0.4318,-0.3273,-0.1359",\ +"-0.5767,-0.5610,-0.5474,-0.5151,-0.4683,-0.3638,-0.1724",\ +"-0.6275,-0.6119,-0.5982,-0.5660,-0.5191,-0.4146,-0.2232"); + } + + fall_constraint("SIG2SRAM_constraint_template") { + index_1("0.0056,0.0232,0.0400,0.0728,0.1280,0.2440,0.4760"); + index_2("0.0056,0.0232,0.0400,0.0728,0.1280,0.2440,0.4760"); + values ("-0.4764,-0.4618,-0.4481,-0.4198,-0.3690,-0.2714,-0.0887",\ +"-0.4815,-0.4668,-0.4531,-0.4248,-0.3740,-0.2764,-0.0938",\ +"-0.4859,-0.4712,-0.4576,-0.4292,-0.3785,-0.2808,-0.0982",\ +"-0.4957,-0.4811,-0.4674,-0.4391,-0.3883,-0.2907,-0.1080",\ +"-0.5021,-0.4874,-0.4738,-0.4454,-0.3947,-0.2970,-0.1144",\ +"-0.5386,-0.5239,-0.5102,-0.4819,-0.4311,-0.3335,-0.1509",\ +"-0.5894,-0.5748,-0.5611,-0.5328,-0.4820,-0.3844,-0.2017"); + } + } + + + timing() { + timing_type : hold_rising; + related_pin : "B_BIST_CLK"; + when : "(B_BIST_WEN & B_BIST_MEN)" + sdf_cond : "B_BIST_RW_ACCESS" + + rise_constraint("SIG2SRAM_constraint_template") { + index_1("0.0056,0.0232,0.0400,0.0728,0.1280,0.2440,0.4760"); + index_2("0.0056,0.0232,0.0400,0.0728,0.1280,0.2440,0.4760"); + values ("0.6249,0.6083,0.5956,0.5634,0.5155,0.4120,0.2196",\ +"0.6299,0.6133,0.6006,0.5684,0.5205,0.4170,0.2246",\ +"0.6343,0.6177,0.6050,0.5728,0.5250,0.4214,0.2291",\ +"0.6442,0.6276,0.6149,0.5827,0.5348,0.4313,0.2389",\ +"0.6505,0.6339,0.6212,0.5890,0.5412,0.4376,0.2453",\ +"0.6870,0.6704,0.6577,0.6255,0.5776,0.4741,0.2817",\ +"0.7379,0.7213,0.7086,0.6764,0.6285,0.5250,0.3326"); + } + + fall_constraint("SIG2SRAM_constraint_template") { + index_1("0.0056,0.0232,0.0400,0.0728,0.1280,0.2440,0.4760"); + index_2("0.0056,0.0232,0.0400,0.0728,0.1280,0.2440,0.4760"); + values ("0.5790,0.5643,0.5507,0.5224,0.4726,0.3798,0.1952",\ +"0.5840,0.5694,0.5557,0.5274,0.4776,0.3848,0.2002",\ +"0.5884,0.5738,0.5601,0.5318,0.4820,0.3892,0.2046",\ +"0.5983,0.5836,0.5700,0.5416,0.4918,0.3991,0.2145",\ +"0.6046,0.5900,0.5763,0.5480,0.4982,0.4054,0.2208",\ +"0.6411,0.6265,0.6128,0.5845,0.5347,0.4419,0.2573",\ +"0.6920,0.6773,0.6637,0.6353,0.5855,0.4928,0.3082"); + } + } +} + pin(B_BIST_CLK) { + direction : input; + capacitance : 0.00380014; + max_transition : "0.476"; + clock : "true" ; + pin_func_type : active_rising ; + + timing () { + timing_type : "min_pulse_width"; + related_pin : "B_BIST_CLK"; + rise_constraint("CLKTRAN_constraint_template") { + index_1("0.0056,0.476"); + values("0.21,0.21"); + } + } + + related_power_pin : VDD; + related_ground_pin : VSS; + + internal_power() { + when : "!B_BIST_MEN & !B_BIST_WEN & !B_BIST_REN"; + rise_power("scalar"){ + values (0); + } + fall_power("scalar"){ + values (0); + } + } + internal_power() { + when : "!B_BIST_MEN & B_BIST_WEN & !B_BIST_REN"; + rise_power("scalar"){ + values (0.5298); + } + fall_power("scalar"){ + values (0); + } + } + internal_power() { + when : "B_BIST_MEN & B_BIST_WEN & !B_BIST_REN"; + rise_power("scalar"){ + values (58.9183); + } + fall_power("scalar"){ + values (0); + } + } + internal_power() { + when : "B_BIST_MEN & B_BIST_WEN & B_BIST_REN"; + rise_power("scalar"){ + values (61.8765); + } + fall_power("scalar"){ + values (0); + } + } + internal_power() { + when : "B_BIST_MEN & !B_BIST_WEN & B_BIST_REN"; + rise_power("scalar"){ + values (48.2666); + } + fall_power("scalar"){ + values (0); + } + } + internal_power() { + when : "!B_BIST_MEN & !B_BIST_WEN & B_BIST_REN"; + rise_power("scalar"){ + values (0.3622); + } + fall_power("scalar"){ + values (0); + } + } + internal_power() { + when : "!B_BIST_MEN & B_BIST_WEN & B_BIST_REN"; + rise_power("scalar"){ + values (1.2134); + } + fall_power("scalar"){ + values (0); + } + } + internal_power() { + when : "B_BIST_MEN & !B_BIST_WEN & !B_BIST_REN"; + rise_power("scalar"){ + values (0); + } + fall_power("scalar"){ + values (0); + } + } + } + bus(B_BIST_DIN) { + bus_type : D_31_0; + direction : input ; + capacitance : 0.00414348 ; + memory_write() { + address : B_BIST_ADDR ; + clocked_on : B_BIST_CLK; + } + + max_transition : "0.476" ; + pin(B_BIST_DIN[31:0]) { + related_power_pin : VDD; + related_ground_pin : VSS; + internal_power() { + when : "B_BIST_MEN"; + rise_power("scalar"){ + values (0.1177); + } + fall_power("scalar"){ + values (0.0495); + } + } + internal_power() { + when : "!B_BIST_MEN"; + rise_power("scalar"){ + values (0.1175); + } + fall_power("scalar"){ + values (0.0489); + } + } + } + timing() { + timing_type : setup_rising; + related_pin : "B_BIST_CLK"; + when : "(B_BIST_WEN & B_BIST_MEN)"; + sdf_cond : "B_BIST_W_ACCESS"; + + rise_constraint("SIG2SRAM_constraint_template") { + index_1("0.0056,0.0232,0.0400,0.0728,0.1280,0.2440,0.4760"); + index_2("0.0056,0.0232,0.0400,0.0728,0.1280,0.2440,0.4760"); + values ("-0.5145,-0.4989,-0.4852,-0.4530,-0.4061,-0.3016,-0.1102",\ +"-0.5195,-0.5039,-0.4902,-0.4580,-0.4111,-0.3067,-0.1152",\ +"-0.5240,-0.5083,-0.4947,-0.4624,-0.4156,-0.3111,-0.1197",\ +"-0.5338,-0.5182,-0.5045,-0.4723,-0.4254,-0.3209,-0.1295",\ +"-0.5402,-0.5245,-0.5109,-0.4786,-0.4318,-0.3273,-0.1359",\ +"-0.5767,-0.5610,-0.5474,-0.5151,-0.4683,-0.3638,-0.1724",\ +"-0.6275,-0.6119,-0.5982,-0.5660,-0.5191,-0.4146,-0.2232"); + } + + fall_constraint("SIG2SRAM_constraint_template") { + index_1("0.0056,0.0232,0.0400,0.0728,0.1280,0.2440,0.4760"); + index_2("0.0056,0.0232,0.0400,0.0728,0.1280,0.2440,0.4760"); + values ("-0.4764,-0.4618,-0.4481,-0.4198,-0.3690,-0.2714,-0.0887",\ +"-0.4815,-0.4668,-0.4531,-0.4248,-0.3740,-0.2764,-0.0938",\ +"-0.4859,-0.4712,-0.4576,-0.4292,-0.3785,-0.2808,-0.0982",\ +"-0.4957,-0.4811,-0.4674,-0.4391,-0.3883,-0.2907,-0.1080",\ +"-0.5021,-0.4874,-0.4738,-0.4454,-0.3947,-0.2970,-0.1144",\ +"-0.5386,-0.5239,-0.5102,-0.4819,-0.4311,-0.3335,-0.1509",\ +"-0.5894,-0.5748,-0.5611,-0.5328,-0.4820,-0.3844,-0.2017"); + } + } + + timing() { + timing_type : hold_rising; + related_pin : "B_BIST_CLK"; + when : "(B_BIST_WEN & B_BIST_MEN)"; + sdf_cond : "B_BIST_W_ACCESS"; + + rise_constraint("SIG2SRAM_constraint_template") { + index_1("0.0056,0.0232,0.0400,0.0728,0.1280,0.2440,0.4760"); + index_2("0.0056,0.0232,0.0400,0.0728,0.1280,0.2440,0.4760"); + values ("0.6249,0.6083,0.5956,0.5634,0.5155,0.4120,0.2196",\ +"0.6299,0.6133,0.6006,0.5684,0.5205,0.4170,0.2246",\ +"0.6343,0.6177,0.6050,0.5728,0.5250,0.4214,0.2291",\ +"0.6442,0.6276,0.6149,0.5827,0.5348,0.4313,0.2389",\ +"0.6505,0.6339,0.6212,0.5890,0.5412,0.4376,0.2453",\ +"0.6870,0.6704,0.6577,0.6255,0.5776,0.4741,0.2817",\ +"0.7379,0.7213,0.7086,0.6764,0.6285,0.5250,0.3326"); + } + + fall_constraint("SIG2SRAM_constraint_template") { + index_1("0.0056,0.0232,0.0400,0.0728,0.1280,0.2440,0.4760"); + index_2("0.0056,0.0232,0.0400,0.0728,0.1280,0.2440,0.4760"); + values ("0.5790,0.5643,0.5507,0.5224,0.4726,0.3798,0.1952",\ +"0.5840,0.5694,0.5557,0.5274,0.4776,0.3848,0.2002",\ +"0.5884,0.5738,0.5601,0.5318,0.4820,0.3892,0.2046",\ +"0.5983,0.5836,0.5700,0.5416,0.4918,0.3991,0.2145",\ +"0.6046,0.5900,0.5763,0.5480,0.4982,0.4054,0.2208",\ +"0.6411,0.6265,0.6128,0.5845,0.5347,0.4419,0.2573",\ +"0.6920,0.6773,0.6637,0.6353,0.5855,0.4928,0.3082"); + } + } + } + +bus(B_DOUT) { + + bus_type : D_31_0; + direction : output ; + capacitance : 0 ; + max_capacitance : 0.064 ; + memory_read() { + address : B_ADDR ; + } + pin(B_DOUT[31:0]) { + related_power_pin : VDD; + related_ground_pin : VSS; + internal_power() { + rise_power("scalar") { + values (0); + } + fall_power("scalar") { + values (0); + } + } + } + timing() { + related_pin : "B_CLK"; + timing_type : rising_edge ; + timing_sense : non_unate ; + + cell_rise(SIG2SRAM_delay_template) { + index_1("0.0056,0.0232,0.0400,0.0728,0.1280,0.2440,0.4760"); + index_2("0.0008,0.0014,0.0051,0.0100,0.0339,0.0640"); + values ("4.4248,4.4264,4.4340,4.4427,4.4751,4.5113",\ +"4.4349,4.4365,4.4441,4.4529,4.4852,4.5214",\ +"4.4395,4.4411,4.4488,4.4575,4.4899,4.5260",\ +"4.4473,4.4489,4.4566,4.4653,4.4977,4.5338",\ +"4.4549,4.4565,4.4641,4.4728,4.5052,4.5413",\ +"4.4899,4.4916,4.4992,4.5079,4.5403,4.5764",\ +"4.5433,4.5449,4.5525,4.5612,4.5936,4.6298"); + } + cell_fall(SIG2SRAM_delay_template) { + index_1("0.0056,0.0232,0.0400,0.0728,0.1280,0.2440,0.4760"); + index_2("0.0008,0.0014,0.0051,0.0100,0.0339,0.0640"); + values ("4.3645,4.3658,4.3719,4.3790,4.4055,4.4318",\ +"4.3746,4.3759,4.3820,4.3892,4.4157,4.4419",\ +"4.3792,4.3806,4.3867,4.3938,4.4203,4.4465",\ +"4.3870,4.3884,4.3945,4.4016,4.4281,4.4543",\ +"4.3946,4.3959,4.4020,4.4091,4.4356,4.4618",\ +"4.4297,4.4310,4.4371,4.4442,4.4707,4.4969",\ +"4.4830,4.4843,4.4904,4.4975,4.5240,4.5503"); + } + + rise_transition(SRAM_load_template) { + index_1("0.0008,0.0014,0.0051,0.0100,0.0339,0.0640"); + values ("0.0326,0.0341,0.0428,0.0518,0.0923,0.1492"); + } + fall_transition(SRAM_load_template) { + index_1("0.0008,0.0014,0.0051,0.0100,0.0339,0.0640"); + values ("0.0254,0.0265,0.0335,0.0402,0.0707,0.1039"); + } + } +} +cell_leakage_power : 637.8015; +} +} diff --git a/flow/platforms/ihp-sg13g2/lib/RM_IHPSG13_2P_256x16_c2_bm_bist_fast_1p32V_m55C.lib b/flow/platforms/ihp-sg13g2/lib/RM_IHPSG13_2P_256x16_c2_bm_bist_fast_1p32V_m55C.lib new file mode 100644 index 0000000000..a114d3636f --- /dev/null +++ b/flow/platforms/ihp-sg13g2/lib/RM_IHPSG13_2P_256x16_c2_bm_bist_fast_1p32V_m55C.lib @@ -0,0 +1,2874 @@ +/* ------------------------------------------------------*/ +/**/ +/* Copyright 2025 IHP PDK Authors*/ +/**/ +/* Licensed under the Apache License, Version 2.0 (the "License");*/ +/* you may not use this file except in compliance with the License.*/ +/* You may obtain a copy of the License at*/ +/* */ +/* https://www.apache.org/licenses/LICENSE-2.0*/ +/* */ +/* Unless required by applicable law or agreed to in writing, software*/ +/* distributed under the License is distributed on an "AS IS" BASIS,*/ +/* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.*/ +/* See the License for the specific language governing permissions and*/ +/* limitations under the License.*/ +/* */ +/* Generated on Wed Aug 27 13:19:41 2025 */ +/* */ +/* ------------------------------------------------------ */ +library(RM_IHPSG13_2P_256x16_c2_bm_bist_fast_1p32V_m55C) { + technology (cmos) ; + delay_model : table_lookup ; + define ("add_pg_pin_to_lib", "library", "boolean"); + add_pg_pin_to_lib : true; + voltage_map ( VDD, 1.32); + voltage_map ( VDDARRAY, 1.32); + voltage_map ( VSS, 0.000000 ); + + date : "Wed Aug 27 13:19:39 2025" ; + comment : "IHP Microelectronics GmbH, 2023" ; + revision : 1.0.0 ; + simulation : true ; + nom_process : 1 ; + nom_temperature : -55 ; + nom_voltage : 1.32 ; + + operating_conditions("fast_1p32V_m55C"){ + process : 1 ; + temperature : -55 ; + voltage : 1.32 ; + tree_type : "balanced_tree" ; + } + + default_operating_conditions : fast_1p32V_m55C ; + default_max_transition : 1.0 ; + default_fanout_load : 1.0 ; + default_inout_pin_cap : 0.0 ; + default_input_pin_cap : 0.0 ; + default_output_pin_cap : 0.0 ; + default_cell_leakage_power : 0.0 ; + default_leakage_power_density : 0.0 ; + + slew_lower_threshold_pct_rise : 30 ; + slew_upper_threshold_pct_rise : 70 ; + input_threshold_pct_fall : 50 ; + output_threshold_pct_fall : 50 ; + input_threshold_pct_rise : 50 ; + output_threshold_pct_rise : 50 ; + slew_lower_threshold_pct_fall : 30 ; + slew_upper_threshold_pct_fall : 70 ; + slew_derate_from_library : 0.5; + k_volt_cell_leakage_power : 0.0 ; + k_temp_cell_leakage_power : 0.0 ; + k_process_cell_leakage_power : 0.0 ; + k_volt_internal_power : 0.0 ; + k_temp_internal_power : 0.0 ; + k_process_internal_power : 0.0 ; + + capacitive_load_unit (1,pf) ; + voltage_unit : "1V" ; + current_unit : "1uA" ; + time_unit : "1ns" ; + leakage_power_unit : "1nW" ; + pulling_resistance_unit : "1kohm"; + /* + ------------------------------------------------------------------------------------------ + implicit units overview: + cell_area unit : "um" + internal_power unit : "1e-12 * J/toggle = 1 * uW/MHz" + (capacitive_load_unit * voltage_unit^2) per toggle event + ------------------------------------------------------------------------------------------ + */ + library_features(report_delay_calculation); + define_cell_area (pad_drivers,pad_driver_sites) ; + + lu_table_template(CLKTRAN_constraint_template) { + variable_1 : constrained_pin_transition; + index_1 ( "0.010, 0.050, 0.200, 0.400, 1.000" ); + } + lu_table_template(SRAM_load_template) { + variable_1 : total_output_net_capacitance; + index_1 ( "0.0008,0.0014,0.0051,0.0100,0.0339,0.0640" ); + } + lu_table_template(SIG2SRAM_constraint_template) { + variable_1 : related_pin_transition; + variable_2 : constrained_pin_transition; + index_1 ( "0.0040,0.0176,0.0344,0.0656,0.1120,0.2016,0.3800" ); + index_2 ( "0.0040,0.0176,0.0344,0.0656,0.1120,0.2016,0.3800" ); + } + + lu_table_template(SIG2SRAM_delay_template) { + variable_1 : input_net_transition; + variable_2 : total_output_net_capacitance; + index_1 ( "0.0040,0.0176,0.0344,0.0656,0.1120,0.2016,0.3800" ); + index_2 ( "0.0008,0.0014,0.0051,0.0100,0.0339,0.0640" ); + } + + type (D_15_0) { + base_type : array; + data_type : bit; + bit_width : 16; + bit_from : 15; + bit_to : 0; + downto : true; + } + + type (A_7_0) { + base_type : array; + data_type : bit; + bit_width : 8; + bit_from : 7; + bit_to : 0; + downto : true; + } + +cell(RM_IHPSG13_2P_256x16_c2_bm_bist) { +pg_pin (VDD) { + pg_type : primary_power; + voltage_name : VDD; +} +pg_pin (VDDARRAY) { + pg_type : primary_power; + voltage_name : VDDARRAY; +} +pg_pin (VSS) { + pg_type : primary_ground; + voltage_name : VSS; +} + +memory() { + type : ram; + address_width : 8; + word_width : 16; +} + +interface_timing : false; +bus_naming_style : "%s[%d]" ; +area : 57520.5515 ; + + pin(A_DLY) { + direction : input ; + capacitance : 0.00421562 ; + max_transition : "1" ; + related_power_pin : VDD; + related_ground_pin : VSS; + internal_power() { + rise_power("scalar") { + values (0); + } + fall_power("scalar") { + values (0); + } + } + } + +bus(A_ADDR) { + bus_type : A_7_0; + direction : input ; + capacitance : 0.0115194 ; + pin(A_ADDR[0]) { + capacitance : 0.00563454 ; + } + pin(A_ADDR[1]) { + capacitance : 0.00744185 ; + } + pin(A_ADDR[2]) { + capacitance : 0.0100611 ; + } + pin(A_ADDR[3]) { + capacitance : 0.00669965 ; + } + pin(A_ADDR[4]) { + capacitance : 0.00614331 ; + } + pin(A_ADDR[5]) { + capacitance : 0.0102172 ; + } + pin(A_ADDR[6]) { + capacitance : 0.0124225 ; + } + max_transition : "0.38" ; + pin(A_ADDR[7:0]) { + related_power_pin : VDD; + related_ground_pin : VSS; + internal_power() { + when : "A_MEN"; + rise_power("scalar"){ + values (0.0119); + } + fall_power("scalar"){ + values (0.0026); + } + } + internal_power() { + when : "!A_MEN"; + rise_power("scalar"){ + values (0.0264); + } + fall_power("scalar"){ + values (0.0021); + } + } + } + timing() { + timing_type : setup_rising; + related_pin : "A_CLK"; + when : "((A_WEN | A_REN)& A_MEN)" + sdf_cond : "A_RW_ACCESS" + + rise_constraint("SIG2SRAM_constraint_template") { + index_1("0.0040,0.0176,0.0344,0.0656,0.1120,0.2016,0.3800"); + index_2("0.0040,0.0176,0.0344,0.0656,0.1120,0.2016,0.3800"); + values ("-0.2371,-0.2215,-0.2098,-0.1824,-0.1434,-0.0691,0.0676",\ +"-0.2449,-0.2332,-0.2176,-0.1902,-0.1551,-0.0770,0.0559",\ +"-0.2605,-0.2488,-0.2332,-0.2059,-0.1707,-0.0965,0.0441",\ +"-0.2879,-0.2723,-0.2605,-0.2332,-0.1941,-0.1199,0.0168",\ +"-0.3230,-0.3113,-0.2996,-0.2723,-0.2332,-0.1590,-0.0184",\ +"-0.4012,-0.3895,-0.3738,-0.3465,-0.3074,-0.2332,-0.0965",\ +"-0.5379,-0.5262,-0.5105,-0.4832,-0.4480,-0.3699,-0.2332"); + } + + fall_constraint("SIG2SRAM_constraint_template") { + index_1("0.0040,0.0176,0.0344,0.0656,0.1120,0.2016,0.3800"); + index_2("0.0040,0.0176,0.0344,0.0656,0.1120,0.2016,0.3800"); + values ("-0.1785,-0.1707,-0.1551,-0.1277,-0.0887,-0.0184,0.1145",\ +"-0.1902,-0.1785,-0.1629,-0.1355,-0.1004,-0.0262,0.1027",\ +"-0.2059,-0.1941,-0.1785,-0.1512,-0.1160,-0.0418,0.0871",\ +"-0.2293,-0.2176,-0.2059,-0.1785,-0.1434,-0.0691,0.0598",\ +"-0.2684,-0.2566,-0.2449,-0.2176,-0.1824,-0.1082,0.0207",\ +"-0.3465,-0.3348,-0.3191,-0.2918,-0.2566,-0.1824,-0.0535",\ +"-0.4832,-0.4715,-0.4559,-0.4324,-0.3934,-0.3191,-0.1902"); + } + } + + + timing() { + timing_type : hold_rising; + related_pin : "A_CLK"; + when : "((A_WEN | A_REN)& A_MEN)" + sdf_cond : "A_RW_ACCESS" + + rise_constraint("SIG2SRAM_constraint_template") { + index_1("0.0040,0.0176,0.0344,0.0656,0.1120,0.2016,0.3800"); + index_2("0.0040,0.0176,0.0344,0.0656,0.1120,0.2016,0.3800"); + values ("0.3410,0.3293,0.3137,0.2863,0.2473,0.1730,0.0324",\ +"0.3488,0.3371,0.3215,0.2941,0.2590,0.1809,0.0480",\ +"0.3684,0.3527,0.3371,0.3098,0.2746,0.1965,0.0598",\ +"0.3918,0.3762,0.3645,0.3371,0.2980,0.2238,0.0871",\ +"0.4309,0.4152,0.4035,0.3762,0.3371,0.2629,0.1223",\ +"0.5051,0.4934,0.4777,0.4504,0.4113,0.3371,0.1965",\ +"0.6418,0.6262,0.6145,0.5871,0.5520,0.4738,0.3332"); + } + + fall_constraint("SIG2SRAM_constraint_template") { + index_1("0.0040,0.0176,0.0344,0.0656,0.1120,0.2016,0.3800"); + index_2("0.0040,0.0176,0.0344,0.0656,0.1120,0.2016,0.3800"); + values ("0.2824,0.2707,0.2551,0.2277,0.1926,0.1184,-0.0105",\ +"0.2902,0.2785,0.2668,0.2395,0.2043,0.1301,0.0012",\ +"0.3059,0.2941,0.2824,0.2551,0.2199,0.1457,0.0168",\ +"0.3332,0.3215,0.3059,0.2785,0.2434,0.1691,0.0402",\ +"0.3723,0.3605,0.3449,0.3176,0.2824,0.2121,0.0793",\ +"0.4465,0.4348,0.4230,0.3918,0.3566,0.2824,0.1535",\ +"0.5832,0.5715,0.5598,0.5324,0.4934,0.4191,0.2902"); + } + } +} +pin(A_WEN) { + direction : input ; + capacitance : 0.00341384 ; + max_transition : "0.38" ; + related_power_pin : VDD; + related_ground_pin : VSS; + internal_power() { + when : "A_MEN"; + rise_power("scalar"){ + values (0.0061); + } + fall_power("scalar"){ + values (0.0158); + } + } + internal_power() { + when : "!A_MEN"; + rise_power("scalar"){ + values (0.0054); + } + fall_power("scalar"){ + values (0.0210); + } + } + timing() { + timing_type : setup_rising; + related_pin : "A_CLK"; + when : "A_MEN" + sdf_cond : "A_MEN" + + rise_constraint("SIG2SRAM_constraint_template") { + index_1("0.0040,0.0176,0.0344,0.0656,0.1120,0.2016,0.3800"); + index_2("0.0040,0.0176,0.0344,0.0656,0.1120,0.2016,0.3800"); + values ("0.1418,0.1496,0.1652,0.1887,0.2316,0.3059,0.4465",\ +"0.1301,0.1379,0.1535,0.1809,0.2199,0.2941,0.4348",\ +"0.1145,0.1262,0.1379,0.1652,0.2043,0.2785,0.4191",\ +"0.0871,0.0949,0.1105,0.1379,0.1770,0.2512,0.3879",\ +"0.0480,0.0598,0.0754,0.0988,0.1379,0.2082,0.3527",\ +"-0.0262,-0.0145,0.0012,0.0246,0.0676,0.1379,0.2785",\ +"-0.1668,-0.1551,-0.1395,-0.1121,-0.0730,0.0012,0.1418"); + } + + fall_constraint("SIG2SRAM_constraint_template") { + index_1("0.0040,0.0176,0.0344,0.0656,0.1120,0.2016,0.3800"); + index_2("0.0040,0.0176,0.0344,0.0656,0.1120,0.2016,0.3800"); + values ("0.2082,0.2160,0.2316,0.2590,0.2941,0.3684,0.5012",\ +"0.1926,0.2043,0.2199,0.2473,0.2824,0.3566,0.4895",\ +"0.1770,0.1887,0.2043,0.2316,0.2668,0.3410,0.4777",\ +"0.1535,0.1652,0.1770,0.2043,0.2395,0.3137,0.4504",\ +"0.1145,0.1262,0.1379,0.1652,0.2043,0.2746,0.4113",\ +"0.0402,0.0520,0.0676,0.0910,0.1262,0.2004,0.3332",\ +"-0.0965,-0.0848,-0.0730,-0.0457,-0.0066,0.0637,0.2004"); + } + } + + + timing() { + timing_type : hold_rising; + related_pin : "A_CLK"; + when : "A_MEN" + sdf_cond : "A_MEN" + + rise_constraint("SIG2SRAM_constraint_template") { + index_1("0.0040,0.0176,0.0344,0.0656,0.1120,0.2016,0.3800"); + index_2("0.0040,0.0176,0.0344,0.0656,0.1120,0.2016,0.3800"); + values ("0.1770,0.1652,0.1496,0.1223,0.0793,0.0090,-0.1316",\ +"0.1848,0.1730,0.1574,0.1301,0.0910,0.0168,-0.1199",\ +"0.2004,0.1887,0.1770,0.1496,0.1066,0.0363,-0.1043",\ +"0.2277,0.2160,0.2004,0.1730,0.1340,0.0598,-0.0809",\ +"0.2668,0.2551,0.2395,0.2121,0.1730,0.0988,-0.0418",\ +"0.3410,0.3293,0.3137,0.2863,0.2434,0.1730,0.0324",\ +"0.4816,0.4699,0.4543,0.4230,0.3801,0.3098,0.1730"); + } + + fall_constraint("SIG2SRAM_constraint_template") { + index_1("0.0040,0.0176,0.0344,0.0656,0.1120,0.2016,0.3800"); + index_2("0.0040,0.0176,0.0344,0.0656,0.1120,0.2016,0.3800"); + values ("0.1613,0.1496,0.1379,0.1066,0.0715,0.0012,-0.1355",\ +"0.1730,0.1613,0.1457,0.1184,0.0832,0.0129,-0.1238",\ +"0.1887,0.1770,0.1613,0.1340,0.0988,0.0246,-0.1121",\ +"0.2121,0.2043,0.1887,0.1613,0.1223,0.0520,-0.0848",\ +"0.2512,0.2434,0.2277,0.2004,0.1613,0.0910,-0.0457",\ +"0.3254,0.3176,0.3020,0.2746,0.2355,0.1652,0.0324",\ +"0.4660,0.4543,0.4387,0.4113,0.3723,0.3020,0.1691"); + } + } + } +pin(A_REN) { + direction : input ; + capacitance : 0.00390661 ; + max_transition : "0.38" ; + related_power_pin : VDD; + related_ground_pin : VSS; + internal_power() { + when : "A_MEN"; + rise_power("scalar"){ + values (0.0108); + } + fall_power("scalar"){ + values (0.0104); + } + } + internal_power() { + when : "!A_MEN"; + rise_power("scalar"){ + values (0.0222); + } + fall_power("scalar"){ + values (0.0197); + } + } + timing() { + timing_type : setup_rising; + related_pin : "A_CLK"; + when : "A_MEN" + sdf_cond : "A_MEN" + + rise_constraint("SIG2SRAM_constraint_template") { + index_1("0.0040,0.0176,0.0344,0.0656,0.1120,0.2016,0.3800"); + index_2("0.0040,0.0176,0.0344,0.0656,0.1120,0.2016,0.3800"); + values ("-0.0027,0.0090,0.0246,0.0520,0.0910,0.1613,0.3020",\ +"-0.0105,0.0012,0.0129,0.0363,0.0793,0.1535,0.2902",\ +"-0.0262,-0.0145,-0.0027,0.0246,0.0637,0.1379,0.2785",\ +"-0.0535,-0.0418,-0.0262,0.0012,0.0363,0.1105,0.2512",\ +"-0.0926,-0.0809,-0.0652,-0.0418,-0.0027,0.0715,0.2121",\ +"-0.1668,-0.1551,-0.1395,-0.1082,-0.0770,-0.0027,0.1379",\ +"-0.3035,-0.2918,-0.2762,-0.2488,-0.2137,-0.1434,-0.0027"); + } + + fall_constraint("SIG2SRAM_constraint_template") { + index_1("0.0040,0.0176,0.0344,0.0656,0.1120,0.2016,0.3800"); + index_2("0.0040,0.0176,0.0344,0.0656,0.1120,0.2016,0.3800"); + values ("0.0832,0.0949,0.1105,0.1379,0.1730,0.2473,0.3801",\ +"0.0754,0.0832,0.0988,0.1223,0.1613,0.2355,0.3684",\ +"0.0598,0.0676,0.0832,0.1066,0.1457,0.2121,0.3527",\ +"0.0324,0.0441,0.0598,0.0871,0.1223,0.1926,0.3293",\ +"-0.0066,0.0051,0.0168,0.0480,0.0832,0.1535,0.2902",\ +"-0.0809,-0.0691,-0.0574,-0.0301,0.0090,0.0832,0.2121",\ +"-0.2176,-0.2059,-0.1941,-0.1668,-0.1277,-0.0574,0.0793"); + } + } + + + timing() { + timing_type : hold_rising; + related_pin : "A_CLK"; + when : "A_MEN" + sdf_cond : "A_MEN" + + rise_constraint("SIG2SRAM_constraint_template") { + index_1("0.0040,0.0176,0.0344,0.0656,0.1120,0.2016,0.3800"); + index_2("0.0040,0.0176,0.0344,0.0656,0.1120,0.2016,0.3800"); + values ("0.1887,0.1770,0.1613,0.1340,0.0949,0.0207,-0.1160",\ +"0.1965,0.1848,0.1730,0.1457,0.1027,0.0324,-0.1082",\ +"0.2160,0.2004,0.1887,0.1613,0.1184,0.0480,-0.0926",\ +"0.2395,0.2277,0.2121,0.1848,0.1457,0.0715,-0.0652",\ +"0.2785,0.2668,0.2512,0.2238,0.1848,0.1105,-0.0262",\ +"0.3527,0.3410,0.3254,0.2980,0.2551,0.1848,0.0480",\ +"0.4934,0.4816,0.4660,0.4387,0.3957,0.3254,0.1887"); + } + + fall_constraint("SIG2SRAM_constraint_template") { + index_1("0.0040,0.0176,0.0344,0.0656,0.1120,0.2016,0.3800"); + index_2("0.0040,0.0176,0.0344,0.0656,0.1120,0.2016,0.3800"); + values ("0.1730,0.1613,0.1496,0.1184,0.0793,0.0129,-0.1238",\ +"0.1848,0.1730,0.1574,0.1301,0.0910,0.0207,-0.1121",\ +"0.2004,0.1887,0.1730,0.1457,0.1066,0.0363,-0.1004",\ +"0.2238,0.2121,0.2004,0.1691,0.1340,0.0598,-0.0730",\ +"0.2629,0.2512,0.2395,0.2121,0.1691,0.0988,-0.0340",\ +"0.3371,0.3254,0.3137,0.2863,0.2434,0.1730,0.0402",\ +"0.4777,0.4660,0.4504,0.4230,0.3840,0.3137,0.1809"); + } + } + } +pin(A_MEN) { + direction : input ; + capacitance : 0.00326046 ; + max_transition : "0.38" ; + related_power_pin : VDD; + related_ground_pin : VSS; + internal_power() { + rise_power("scalar"){ + values (0.1424); + } + fall_power("scalar"){ + values (0.0108); + } + } + timing() { + timing_type : setup_rising; + related_pin : "A_CLK"; + + rise_constraint("SIG2SRAM_constraint_template") { + index_1("0.0040,0.0176,0.0344,0.0656,0.1120,0.2016,0.3800"); + index_2("0.0040,0.0176,0.0344,0.0656,0.1120,0.2016,0.3800"); + values ("0.1418,0.1496,0.1652,0.1926,0.2316,0.3059,0.4465",\ +"0.1301,0.1379,0.1535,0.1809,0.2199,0.2941,0.4348",\ +"0.1145,0.1262,0.1418,0.1652,0.2043,0.2785,0.4191",\ +"0.0871,0.0949,0.1105,0.1379,0.1770,0.2512,0.3879",\ +"0.0480,0.0598,0.0754,0.0988,0.1379,0.2082,0.3488",\ +"-0.0262,-0.0145,0.0012,0.0285,0.0676,0.1379,0.2785",\ +"-0.1668,-0.1551,-0.1395,-0.1121,-0.0730,0.0012,0.1379"); + } + + fall_constraint("SIG2SRAM_constraint_template") { + index_1("0.0040,0.0176,0.0344,0.0656,0.1120,0.2016,0.3800"); + index_2("0.0040,0.0176,0.0344,0.0656,0.1120,0.2016,0.3800"); + values ("0.2082,0.2199,0.2316,0.2590,0.2980,0.3723,0.5051",\ +"0.1965,0.2082,0.2199,0.2473,0.2863,0.3605,0.4934",\ +"0.1809,0.1926,0.2043,0.2316,0.2707,0.3449,0.4777",\ +"0.1574,0.1691,0.1809,0.2082,0.2434,0.3176,0.4543",\ +"0.1145,0.1262,0.1418,0.1691,0.2043,0.2785,0.4113",\ +"0.0441,0.0559,0.0676,0.0949,0.1301,0.2004,0.3332",\ +"-0.0965,-0.0848,-0.0691,-0.0418,-0.0066,0.0676,0.2004"); + } + } + + + timing() { + timing_type : hold_rising; + related_pin : "A_CLK"; + + rise_constraint("SIG2SRAM_constraint_template") { + index_1("0.0040,0.0176,0.0344,0.0656,0.1120,0.2016,0.3800"); + index_2("0.0040,0.0176,0.0344,0.0656,0.1120,0.2016,0.3800"); + values ("0.1770,0.1652,0.1535,0.1262,0.0832,0.0129,-0.1277",\ +"0.1887,0.1770,0.1613,0.1340,0.0949,0.0207,-0.1199",\ +"0.2043,0.1926,0.1770,0.1496,0.1105,0.0363,-0.1043",\ +"0.2277,0.2160,0.2043,0.1770,0.1379,0.0598,-0.0770",\ +"0.2668,0.2551,0.2434,0.2160,0.1730,0.0988,-0.0379",\ +"0.3449,0.3332,0.3176,0.2902,0.2473,0.1730,0.0363",\ +"0.4816,0.4699,0.4543,0.4270,0.3840,0.3098,0.1770"); + } + + fall_constraint("SIG2SRAM_constraint_template") { + index_1("0.0040,0.0176,0.0344,0.0656,0.1120,0.2016,0.3800"); + index_2("0.0040,0.0176,0.0344,0.0656,0.1120,0.2016,0.3800"); + values ("0.1613,0.1496,0.1379,0.1105,0.0715,0.0012,-0.1355",\ +"0.1730,0.1613,0.1496,0.1184,0.0832,0.0129,-0.1238",\ +"0.1887,0.1770,0.1652,0.1340,0.0988,0.0285,-0.1121",\ +"0.2121,0.2043,0.1887,0.1613,0.1223,0.0520,-0.0848",\ +"0.2551,0.2434,0.2277,0.2004,0.1613,0.0910,-0.0418",\ +"0.3293,0.3176,0.3020,0.2746,0.2395,0.1652,0.0324",\ +"0.4660,0.4543,0.4426,0.4113,0.3762,0.3020,0.1691"); + } + } + } +bus(A_BM) { + bus_type : D_15_0; + direction : input ; + capacitance : 0.00388883 ; + max_transition : "0.38" ; + pin(A_BM[15:0]) { + related_power_pin : VDD; + related_ground_pin : VSS; + internal_power() { + when : "A_MEN"; + rise_power("scalar"){ + values (0.0914); + } + fall_power("scalar"){ + values (0.0775); + } + } + internal_power() { + when : "!A_MEN"; + rise_power("scalar"){ + values (0.0871); + } + fall_power("scalar"){ + values (0.0796); + } + } + } + timing() { + timing_type : setup_rising; + related_pin : "A_CLK"; + when : "(A_WEN & A_MEN)" + sdf_cond : "A_RW_ACCESS" + + rise_constraint("SIG2SRAM_constraint_template") { + index_1("0.0040,0.0176,0.0344,0.0656,0.1120,0.2016,0.3800"); + index_2("0.0040,0.0176,0.0344,0.0656,0.1120,0.2016,0.3800"); + values ("-0.2116,-0.2009,-0.1853,-0.1599,-0.1189,-0.0456,0.0891",\ +"-0.2155,-0.2048,-0.1891,-0.1638,-0.1227,-0.0495,0.0853",\ +"-0.2192,-0.2085,-0.1928,-0.1674,-0.1264,-0.0532,0.0816",\ +"-0.2224,-0.2116,-0.1960,-0.1706,-0.1296,-0.0564,0.0784",\ +"-0.2350,-0.2243,-0.2086,-0.1833,-0.1422,-0.0690,0.0658",\ +"-0.2526,-0.2419,-0.2263,-0.2009,-0.1598,-0.0866,0.0482",\ +"-0.2801,-0.2694,-0.2538,-0.2284,-0.1874,-0.1141,0.0207"); + } + + fall_constraint("SIG2SRAM_constraint_template") { + index_1("0.0040,0.0176,0.0344,0.0656,0.1120,0.2016,0.3800"); + index_2("0.0040,0.0176,0.0344,0.0656,0.1120,0.2016,0.3800"); + values ("-0.1882,-0.1765,-0.1638,-0.1364,-0.0993,-0.0261,0.1018",\ +"-0.1921,-0.1804,-0.1677,-0.1403,-0.1032,-0.0300,0.0980",\ +"-0.1958,-0.1840,-0.1713,-0.1440,-0.1069,-0.0337,0.0943",\ +"-0.1990,-0.1872,-0.1745,-0.1472,-0.1101,-0.0368,0.0911",\ +"-0.2116,-0.1999,-0.1872,-0.1598,-0.1227,-0.0495,0.0785",\ +"-0.2292,-0.2175,-0.2048,-0.1774,-0.1403,-0.0671,0.0609",\ +"-0.2567,-0.2450,-0.2323,-0.2049,-0.1678,-0.0946,0.0333"); + } + } + + + timing() { + timing_type : hold_rising; + related_pin : "A_CLK"; + when : "(A_WEN & A_MEN)" + sdf_cond : "A_RW_ACCESS" + + rise_constraint("SIG2SRAM_constraint_template") { + index_1("0.0040,0.0176,0.0344,0.0656,0.1120,0.2016,0.3800"); + index_2("0.0040,0.0176,0.0344,0.0656,0.1120,0.2016,0.3800"); + values ("0.3170,0.3072,0.2916,0.2652,0.2281,0.1539,0.0192",\ +"0.3209,0.3111,0.2955,0.2691,0.2320,0.1578,0.0230",\ +"0.3246,0.3148,0.2992,0.2728,0.2357,0.1615,0.0267",\ +"0.3278,0.3180,0.3024,0.2760,0.2389,0.1647,0.0299",\ +"0.3404,0.3306,0.3150,0.2886,0.2515,0.1773,0.0425",\ +"0.3580,0.3482,0.3326,0.3062,0.2691,0.1949,0.0601",\ +"0.3855,0.3757,0.3601,0.3337,0.2966,0.2224,0.0877"); + } + + fall_constraint("SIG2SRAM_constraint_template") { + index_1("0.0040,0.0176,0.0344,0.0656,0.1120,0.2016,0.3800"); + index_2("0.0040,0.0176,0.0344,0.0656,0.1120,0.2016,0.3800"); + values ("0.2887,0.2779,0.2643,0.2369,0.2008,0.1285,-0.0013",\ +"0.2926,0.2818,0.2682,0.2408,0.2047,0.1324,0.0025",\ +"0.2962,0.2855,0.2718,0.2445,0.2084,0.1361,0.0062",\ +"0.2994,0.2887,0.2750,0.2477,0.2116,0.1393,0.0094",\ +"0.3121,0.3013,0.2877,0.2603,0.2242,0.1519,0.0220",\ +"0.3297,0.3189,0.3053,0.2779,0.2418,0.1695,0.0396",\ +"0.3572,0.3464,0.3328,0.3054,0.2693,0.1970,0.0671"); + } + } +} + pin(A_CLK) { + direction : input; + capacitance : 0.00389386; + max_transition : "0.38"; + clock : "true" ; + pin_func_type : active_rising ; + + timing () { + timing_type : "min_pulse_width"; + related_pin : "A_CLK"; + rise_constraint("CLKTRAN_constraint_template") { + index_1("0.004,0.38"); + values("0.12,0.12"); + } + } + + related_power_pin : VDD; + related_ground_pin : VSS; + + internal_power() { + when : "!A_MEN & !A_WEN & !A_REN"; + rise_power("scalar"){ + values (0); + } + fall_power("scalar"){ + values (0); + } + } + internal_power() { + when : "!A_MEN & A_WEN & !A_REN"; + rise_power("scalar"){ + values (0.6406); + } + fall_power("scalar"){ + values (0); + } + } + internal_power() { + when : "A_MEN & A_WEN & !A_REN"; + rise_power("scalar"){ + values (22.6954); + } + fall_power("scalar"){ + values (0); + } + } + internal_power() { + when : "A_MEN & A_WEN & A_REN"; + rise_power("scalar"){ + values (24.9897); + } + fall_power("scalar"){ + values (0); + } + } + internal_power() { + when : "A_MEN & !A_WEN & A_REN"; + rise_power("scalar"){ + values (18.3238); + } + fall_power("scalar"){ + values (0); + } + } + internal_power() { + when : "!A_MEN & !A_WEN & A_REN"; + rise_power("scalar"){ + values (0.3904); + } + fall_power("scalar"){ + values (0); + } + } + internal_power() { + when : "!A_MEN & A_WEN & A_REN"; + rise_power("scalar"){ + values (0.8744); + } + fall_power("scalar"){ + values (0); + } + } + internal_power() { + when : "A_MEN & !A_WEN & !A_REN"; + rise_power("scalar"){ + values (0); + } + fall_power("scalar"){ + values (0); + } + } + } + bus(A_DIN) { + bus_type : D_15_0; + direction : input ; + capacitance : 0.00505326 ; + memory_write() { + address : A_ADDR ; + clocked_on : A_CLK; + } + + max_transition : "0.38" ; + pin(A_DIN[15:0]) { + related_power_pin : VDD; + related_ground_pin : VSS; + internal_power() { + when : "A_MEN"; + rise_power("scalar"){ + values (0.0914); + } + fall_power("scalar"){ + values (0.0775); + } + } + internal_power() { + when : "!A_MEN"; + rise_power("scalar"){ + values (0.0871); + } + fall_power("scalar"){ + values (0.0796); + } + } + } + timing() { + timing_type : setup_rising; + related_pin : "A_CLK"; + when : "(A_WEN & A_MEN)"; + sdf_cond : "A_W_ACCESS"; + + rise_constraint("SIG2SRAM_constraint_template") { + index_1("0.0040,0.0176,0.0344,0.0656,0.1120,0.2016,0.3800"); + index_2("0.0040,0.0176,0.0344,0.0656,0.1120,0.2016,0.3800"); + values ("-0.2116,-0.2009,-0.1853,-0.1599,-0.1189,-0.0456,0.0891",\ +"-0.2155,-0.2048,-0.1891,-0.1638,-0.1227,-0.0495,0.0853",\ +"-0.2192,-0.2085,-0.1928,-0.1674,-0.1264,-0.0532,0.0816",\ +"-0.2224,-0.2116,-0.1960,-0.1706,-0.1296,-0.0564,0.0784",\ +"-0.2350,-0.2243,-0.2086,-0.1833,-0.1422,-0.0690,0.0658",\ +"-0.2526,-0.2419,-0.2263,-0.2009,-0.1598,-0.0866,0.0482",\ +"-0.2801,-0.2694,-0.2538,-0.2284,-0.1874,-0.1141,0.0207"); + } + + fall_constraint("SIG2SRAM_constraint_template") { + index_1("0.0040,0.0176,0.0344,0.0656,0.1120,0.2016,0.3800"); + index_2("0.0040,0.0176,0.0344,0.0656,0.1120,0.2016,0.3800"); + values ("-0.1882,-0.1765,-0.1638,-0.1364,-0.0993,-0.0261,0.1018",\ +"-0.1921,-0.1804,-0.1677,-0.1403,-0.1032,-0.0300,0.0980",\ +"-0.1958,-0.1840,-0.1713,-0.1440,-0.1069,-0.0337,0.0943",\ +"-0.1990,-0.1872,-0.1745,-0.1472,-0.1101,-0.0368,0.0911",\ +"-0.2116,-0.1999,-0.1872,-0.1598,-0.1227,-0.0495,0.0785",\ +"-0.2292,-0.2175,-0.2048,-0.1774,-0.1403,-0.0671,0.0609",\ +"-0.2567,-0.2450,-0.2323,-0.2049,-0.1678,-0.0946,0.0333"); + } + } + + timing() { + timing_type : hold_rising; + related_pin : "A_CLK"; + when : "(A_WEN & A_MEN)"; + sdf_cond : "A_W_ACCESS"; + + rise_constraint("SIG2SRAM_constraint_template") { + index_1("0.0040,0.0176,0.0344,0.0656,0.1120,0.2016,0.3800"); + index_2("0.0040,0.0176,0.0344,0.0656,0.1120,0.2016,0.3800"); + values ("0.3170,0.3072,0.2916,0.2652,0.2281,0.1539,0.0192",\ +"0.3209,0.3111,0.2955,0.2691,0.2320,0.1578,0.0230",\ +"0.3246,0.3148,0.2992,0.2728,0.2357,0.1615,0.0267",\ +"0.3278,0.3180,0.3024,0.2760,0.2389,0.1647,0.0299",\ +"0.3404,0.3306,0.3150,0.2886,0.2515,0.1773,0.0425",\ +"0.3580,0.3482,0.3326,0.3062,0.2691,0.1949,0.0601",\ +"0.3855,0.3757,0.3601,0.3337,0.2966,0.2224,0.0877"); + } + + fall_constraint("SIG2SRAM_constraint_template") { + index_1("0.0040,0.0176,0.0344,0.0656,0.1120,0.2016,0.3800"); + index_2("0.0040,0.0176,0.0344,0.0656,0.1120,0.2016,0.3800"); + values ("0.2887,0.2779,0.2643,0.2369,0.2008,0.1285,-0.0013",\ +"0.2926,0.2818,0.2682,0.2408,0.2047,0.1324,0.0025",\ +"0.2962,0.2855,0.2718,0.2445,0.2084,0.1361,0.0062",\ +"0.2994,0.2887,0.2750,0.2477,0.2116,0.1393,0.0094",\ +"0.3121,0.3013,0.2877,0.2603,0.2242,0.1519,0.0220",\ +"0.3297,0.3189,0.3053,0.2779,0.2418,0.1695,0.0396",\ +"0.3572,0.3464,0.3328,0.3054,0.2693,0.1970,0.0671"); + } + } + } + + pin(A_BIST_EN) { + direction : input ; + capacitance : 0.00421562 ; + max_transition : "1" ; + related_power_pin : VDD; + related_ground_pin : VSS; + internal_power() { + rise_power("scalar") { + values (0); + } + fall_power("scalar") { + values (0); + } + } + } + +bus(A_BIST_ADDR) { + bus_type : A_7_0; + direction : input ; + capacitance : 0.0115194 ; + pin(A_BIST_ADDR[0]) { + capacitance : 0.00563454 ; + } + pin(A_BIST_ADDR[1]) { + capacitance : 0.00744185 ; + } + pin(A_BIST_ADDR[2]) { + capacitance : 0.0100611 ; + } + pin(A_BIST_ADDR[3]) { + capacitance : 0.00669965 ; + } + pin(A_BIST_ADDR[4]) { + capacitance : 0.00614331 ; + } + pin(A_BIST_ADDR[5]) { + capacitance : 0.0102172 ; + } + pin(A_BIST_ADDR[6]) { + capacitance : 0.0124225 ; + } + max_transition : "0.38" ; + pin(A_BIST_ADDR[7:0]) { + related_power_pin : VDD; + related_ground_pin : VSS; + internal_power() { + when : "A_BIST_MEN"; + rise_power("scalar"){ + values (0.0119); + } + fall_power("scalar"){ + values (0.0026); + } + } + internal_power() { + when : "!A_BIST_MEN"; + rise_power("scalar"){ + values (0.0264); + } + fall_power("scalar"){ + values (0.0021); + } + } + } + timing() { + timing_type : setup_rising; + related_pin : "A_BIST_CLK"; + when : "((A_BIST_WEN | A_BIST_REN)& A_BIST_MEN)" + sdf_cond : "A_BIST_RW_ACCESS" + + rise_constraint("SIG2SRAM_constraint_template") { + index_1("0.0040,0.0176,0.0344,0.0656,0.1120,0.2016,0.3800"); + index_2("0.0040,0.0176,0.0344,0.0656,0.1120,0.2016,0.3800"); + values ("-0.2371,-0.2215,-0.2098,-0.1824,-0.1434,-0.0691,0.0676",\ +"-0.2449,-0.2332,-0.2176,-0.1902,-0.1551,-0.0770,0.0559",\ +"-0.2605,-0.2488,-0.2332,-0.2059,-0.1707,-0.0965,0.0441",\ +"-0.2879,-0.2723,-0.2605,-0.2332,-0.1941,-0.1199,0.0168",\ +"-0.3230,-0.3113,-0.2996,-0.2723,-0.2332,-0.1590,-0.0184",\ +"-0.4012,-0.3895,-0.3738,-0.3465,-0.3074,-0.2332,-0.0965",\ +"-0.5379,-0.5262,-0.5105,-0.4832,-0.4480,-0.3699,-0.2332"); + } + + fall_constraint("SIG2SRAM_constraint_template") { + index_1("0.0040,0.0176,0.0344,0.0656,0.1120,0.2016,0.3800"); + index_2("0.0040,0.0176,0.0344,0.0656,0.1120,0.2016,0.3800"); + values ("-0.1785,-0.1707,-0.1551,-0.1277,-0.0887,-0.0184,0.1145",\ +"-0.1902,-0.1785,-0.1629,-0.1355,-0.1004,-0.0262,0.1027",\ +"-0.2059,-0.1941,-0.1785,-0.1512,-0.1160,-0.0418,0.0871",\ +"-0.2293,-0.2176,-0.2059,-0.1785,-0.1434,-0.0691,0.0598",\ +"-0.2684,-0.2566,-0.2449,-0.2176,-0.1824,-0.1082,0.0207",\ +"-0.3465,-0.3348,-0.3191,-0.2918,-0.2566,-0.1824,-0.0535",\ +"-0.4832,-0.4715,-0.4559,-0.4324,-0.3934,-0.3191,-0.1902"); + } + } + + + timing() { + timing_type : hold_rising; + related_pin : "A_BIST_CLK"; + when : "((A_BIST_WEN | A_BIST_REN)& A_BIST_MEN)" + sdf_cond : "A_BIST_RW_ACCESS" + + rise_constraint("SIG2SRAM_constraint_template") { + index_1("0.0040,0.0176,0.0344,0.0656,0.1120,0.2016,0.3800"); + index_2("0.0040,0.0176,0.0344,0.0656,0.1120,0.2016,0.3800"); + values ("0.3410,0.3293,0.3137,0.2863,0.2473,0.1730,0.0324",\ +"0.3488,0.3371,0.3215,0.2941,0.2590,0.1809,0.0480",\ +"0.3684,0.3527,0.3371,0.3098,0.2746,0.1965,0.0598",\ +"0.3918,0.3762,0.3645,0.3371,0.2980,0.2238,0.0871",\ +"0.4309,0.4152,0.4035,0.3762,0.3371,0.2629,0.1223",\ +"0.5051,0.4934,0.4777,0.4504,0.4113,0.3371,0.1965",\ +"0.6418,0.6262,0.6145,0.5871,0.5520,0.4738,0.3332"); + } + + fall_constraint("SIG2SRAM_constraint_template") { + index_1("0.0040,0.0176,0.0344,0.0656,0.1120,0.2016,0.3800"); + index_2("0.0040,0.0176,0.0344,0.0656,0.1120,0.2016,0.3800"); + values ("0.2824,0.2707,0.2551,0.2277,0.1926,0.1184,-0.0105",\ +"0.2902,0.2785,0.2668,0.2395,0.2043,0.1301,0.0012",\ +"0.3059,0.2941,0.2824,0.2551,0.2199,0.1457,0.0168",\ +"0.3332,0.3215,0.3059,0.2785,0.2434,0.1691,0.0402",\ +"0.3723,0.3605,0.3449,0.3176,0.2824,0.2121,0.0793",\ +"0.4465,0.4348,0.4230,0.3918,0.3566,0.2824,0.1535",\ +"0.5832,0.5715,0.5598,0.5324,0.4934,0.4191,0.2902"); + } + } +} +pin(A_BIST_WEN) { + direction : input ; + capacitance : 0.00341384 ; + max_transition : "0.38" ; + related_power_pin : VDD; + related_ground_pin : VSS; + internal_power() { + when : "A_BIST_MEN"; + rise_power("scalar"){ + values (0.0061); + } + fall_power("scalar"){ + values (0.0158); + } + } + internal_power() { + when : "!A_BIST_MEN"; + rise_power("scalar"){ + values (0.0054); + } + fall_power("scalar"){ + values (0.0210); + } + } + timing() { + timing_type : setup_rising; + related_pin : "A_BIST_CLK"; + when : "A_BIST_MEN" + sdf_cond : "A_BIST_MEN" + + rise_constraint("SIG2SRAM_constraint_template") { + index_1("0.0040,0.0176,0.0344,0.0656,0.1120,0.2016,0.3800"); + index_2("0.0040,0.0176,0.0344,0.0656,0.1120,0.2016,0.3800"); + values ("0.1418,0.1496,0.1652,0.1887,0.2316,0.3059,0.4465",\ +"0.1301,0.1379,0.1535,0.1809,0.2199,0.2941,0.4348",\ +"0.1145,0.1262,0.1379,0.1652,0.2043,0.2785,0.4191",\ +"0.0871,0.0949,0.1105,0.1379,0.1770,0.2512,0.3879",\ +"0.0480,0.0598,0.0754,0.0988,0.1379,0.2082,0.3527",\ +"-0.0262,-0.0145,0.0012,0.0246,0.0676,0.1379,0.2785",\ +"-0.1668,-0.1551,-0.1395,-0.1121,-0.0730,0.0012,0.1418"); + } + + fall_constraint("SIG2SRAM_constraint_template") { + index_1("0.0040,0.0176,0.0344,0.0656,0.1120,0.2016,0.3800"); + index_2("0.0040,0.0176,0.0344,0.0656,0.1120,0.2016,0.3800"); + values ("0.2082,0.2160,0.2316,0.2590,0.2941,0.3684,0.5012",\ +"0.1926,0.2043,0.2199,0.2473,0.2824,0.3566,0.4895",\ +"0.1770,0.1887,0.2043,0.2316,0.2668,0.3410,0.4777",\ +"0.1535,0.1652,0.1770,0.2043,0.2395,0.3137,0.4504",\ +"0.1145,0.1262,0.1379,0.1652,0.2043,0.2746,0.4113",\ +"0.0402,0.0520,0.0676,0.0910,0.1262,0.2004,0.3332",\ +"-0.0965,-0.0848,-0.0730,-0.0457,-0.0066,0.0637,0.2004"); + } + } + + + timing() { + timing_type : hold_rising; + related_pin : "A_BIST_CLK"; + when : "A_BIST_MEN" + sdf_cond : "A_BIST_MEN" + + rise_constraint("SIG2SRAM_constraint_template") { + index_1("0.0040,0.0176,0.0344,0.0656,0.1120,0.2016,0.3800"); + index_2("0.0040,0.0176,0.0344,0.0656,0.1120,0.2016,0.3800"); + values ("0.1770,0.1652,0.1496,0.1223,0.0793,0.0090,-0.1316",\ +"0.1848,0.1730,0.1574,0.1301,0.0910,0.0168,-0.1199",\ +"0.2004,0.1887,0.1770,0.1496,0.1066,0.0363,-0.1043",\ +"0.2277,0.2160,0.2004,0.1730,0.1340,0.0598,-0.0809",\ +"0.2668,0.2551,0.2395,0.2121,0.1730,0.0988,-0.0418",\ +"0.3410,0.3293,0.3137,0.2863,0.2434,0.1730,0.0324",\ +"0.4816,0.4699,0.4543,0.4230,0.3801,0.3098,0.1730"); + } + + fall_constraint("SIG2SRAM_constraint_template") { + index_1("0.0040,0.0176,0.0344,0.0656,0.1120,0.2016,0.3800"); + index_2("0.0040,0.0176,0.0344,0.0656,0.1120,0.2016,0.3800"); + values ("0.1613,0.1496,0.1379,0.1066,0.0715,0.0012,-0.1355",\ +"0.1730,0.1613,0.1457,0.1184,0.0832,0.0129,-0.1238",\ +"0.1887,0.1770,0.1613,0.1340,0.0988,0.0246,-0.1121",\ +"0.2121,0.2043,0.1887,0.1613,0.1223,0.0520,-0.0848",\ +"0.2512,0.2434,0.2277,0.2004,0.1613,0.0910,-0.0457",\ +"0.3254,0.3176,0.3020,0.2746,0.2355,0.1652,0.0324",\ +"0.4660,0.4543,0.4387,0.4113,0.3723,0.3020,0.1691"); + } + } + } +pin(A_BIST_REN) { + direction : input ; + capacitance : 0.00390661 ; + max_transition : "0.38" ; + related_power_pin : VDD; + related_ground_pin : VSS; + internal_power() { + when : "A_BIST_MEN"; + rise_power("scalar"){ + values (0.0108); + } + fall_power("scalar"){ + values (0.0104); + } + } + internal_power() { + when : "!A_BIST_MEN"; + rise_power("scalar"){ + values (0.0222); + } + fall_power("scalar"){ + values (0.0197); + } + } + timing() { + timing_type : setup_rising; + related_pin : "A_BIST_CLK"; + when : "A_BIST_MEN" + sdf_cond : "A_BIST_MEN" + + rise_constraint("SIG2SRAM_constraint_template") { + index_1("0.0040,0.0176,0.0344,0.0656,0.1120,0.2016,0.3800"); + index_2("0.0040,0.0176,0.0344,0.0656,0.1120,0.2016,0.3800"); + values ("-0.0027,0.0090,0.0246,0.0520,0.0910,0.1613,0.3020",\ +"-0.0105,0.0012,0.0129,0.0363,0.0793,0.1535,0.2902",\ +"-0.0262,-0.0145,-0.0027,0.0246,0.0637,0.1379,0.2785",\ +"-0.0535,-0.0418,-0.0262,0.0012,0.0363,0.1105,0.2512",\ +"-0.0926,-0.0809,-0.0652,-0.0418,-0.0027,0.0715,0.2121",\ +"-0.1668,-0.1551,-0.1395,-0.1082,-0.0770,-0.0027,0.1379",\ +"-0.3035,-0.2918,-0.2762,-0.2488,-0.2137,-0.1434,-0.0027"); + } + + fall_constraint("SIG2SRAM_constraint_template") { + index_1("0.0040,0.0176,0.0344,0.0656,0.1120,0.2016,0.3800"); + index_2("0.0040,0.0176,0.0344,0.0656,0.1120,0.2016,0.3800"); + values ("0.0832,0.0949,0.1105,0.1379,0.1730,0.2473,0.3801",\ +"0.0754,0.0832,0.0988,0.1223,0.1613,0.2355,0.3684",\ +"0.0598,0.0676,0.0832,0.1066,0.1457,0.2121,0.3527",\ +"0.0324,0.0441,0.0598,0.0871,0.1223,0.1926,0.3293",\ +"-0.0066,0.0051,0.0168,0.0480,0.0832,0.1535,0.2902",\ +"-0.0809,-0.0691,-0.0574,-0.0301,0.0090,0.0832,0.2121",\ +"-0.2176,-0.2059,-0.1941,-0.1668,-0.1277,-0.0574,0.0793"); + } + } + + + timing() { + timing_type : hold_rising; + related_pin : "A_BIST_CLK"; + when : "A_BIST_MEN" + sdf_cond : "A_BIST_MEN" + + rise_constraint("SIG2SRAM_constraint_template") { + index_1("0.0040,0.0176,0.0344,0.0656,0.1120,0.2016,0.3800"); + index_2("0.0040,0.0176,0.0344,0.0656,0.1120,0.2016,0.3800"); + values ("0.1887,0.1770,0.1613,0.1340,0.0949,0.0207,-0.1160",\ +"0.1965,0.1848,0.1730,0.1457,0.1027,0.0324,-0.1082",\ +"0.2160,0.2004,0.1887,0.1613,0.1184,0.0480,-0.0926",\ +"0.2395,0.2277,0.2121,0.1848,0.1457,0.0715,-0.0652",\ +"0.2785,0.2668,0.2512,0.2238,0.1848,0.1105,-0.0262",\ +"0.3527,0.3410,0.3254,0.2980,0.2551,0.1848,0.0480",\ +"0.4934,0.4816,0.4660,0.4387,0.3957,0.3254,0.1887"); + } + + fall_constraint("SIG2SRAM_constraint_template") { + index_1("0.0040,0.0176,0.0344,0.0656,0.1120,0.2016,0.3800"); + index_2("0.0040,0.0176,0.0344,0.0656,0.1120,0.2016,0.3800"); + values ("0.1730,0.1613,0.1496,0.1184,0.0793,0.0129,-0.1238",\ +"0.1848,0.1730,0.1574,0.1301,0.0910,0.0207,-0.1121",\ +"0.2004,0.1887,0.1730,0.1457,0.1066,0.0363,-0.1004",\ +"0.2238,0.2121,0.2004,0.1691,0.1340,0.0598,-0.0730",\ +"0.2629,0.2512,0.2395,0.2121,0.1691,0.0988,-0.0340",\ +"0.3371,0.3254,0.3137,0.2863,0.2434,0.1730,0.0402",\ +"0.4777,0.4660,0.4504,0.4230,0.3840,0.3137,0.1809"); + } + } + } +pin(A_BIST_MEN) { + direction : input ; + capacitance : 0.00326046 ; + max_transition : "0.38" ; + related_power_pin : VDD; + related_ground_pin : VSS; + internal_power() { + rise_power("scalar"){ + values (0.1424); + } + fall_power("scalar"){ + values (0.0108); + } + } + timing() { + timing_type : setup_rising; + related_pin : "A_BIST_CLK"; + + rise_constraint("SIG2SRAM_constraint_template") { + index_1("0.0040,0.0176,0.0344,0.0656,0.1120,0.2016,0.3800"); + index_2("0.0040,0.0176,0.0344,0.0656,0.1120,0.2016,0.3800"); + values ("0.1418,0.1496,0.1652,0.1926,0.2316,0.3059,0.4465",\ +"0.1301,0.1379,0.1535,0.1809,0.2199,0.2941,0.4348",\ +"0.1145,0.1262,0.1418,0.1652,0.2043,0.2785,0.4191",\ +"0.0871,0.0949,0.1105,0.1379,0.1770,0.2512,0.3879",\ +"0.0480,0.0598,0.0754,0.0988,0.1379,0.2082,0.3488",\ +"-0.0262,-0.0145,0.0012,0.0285,0.0676,0.1379,0.2785",\ +"-0.1668,-0.1551,-0.1395,-0.1121,-0.0730,0.0012,0.1379"); + } + + fall_constraint("SIG2SRAM_constraint_template") { + index_1("0.0040,0.0176,0.0344,0.0656,0.1120,0.2016,0.3800"); + index_2("0.0040,0.0176,0.0344,0.0656,0.1120,0.2016,0.3800"); + values ("0.2082,0.2199,0.2316,0.2590,0.2980,0.3723,0.5051",\ +"0.1965,0.2082,0.2199,0.2473,0.2863,0.3605,0.4934",\ +"0.1809,0.1926,0.2043,0.2316,0.2707,0.3449,0.4777",\ +"0.1574,0.1691,0.1809,0.2082,0.2434,0.3176,0.4543",\ +"0.1145,0.1262,0.1418,0.1691,0.2043,0.2785,0.4113",\ +"0.0441,0.0559,0.0676,0.0949,0.1301,0.2004,0.3332",\ +"-0.0965,-0.0848,-0.0691,-0.0418,-0.0066,0.0676,0.2004"); + } + } + + + timing() { + timing_type : hold_rising; + related_pin : "A_BIST_CLK"; + + rise_constraint("SIG2SRAM_constraint_template") { + index_1("0.0040,0.0176,0.0344,0.0656,0.1120,0.2016,0.3800"); + index_2("0.0040,0.0176,0.0344,0.0656,0.1120,0.2016,0.3800"); + values ("0.1770,0.1652,0.1535,0.1262,0.0832,0.0129,-0.1277",\ +"0.1887,0.1770,0.1613,0.1340,0.0949,0.0207,-0.1199",\ +"0.2043,0.1926,0.1770,0.1496,0.1105,0.0363,-0.1043",\ +"0.2277,0.2160,0.2043,0.1770,0.1379,0.0598,-0.0770",\ +"0.2668,0.2551,0.2434,0.2160,0.1730,0.0988,-0.0379",\ +"0.3449,0.3332,0.3176,0.2902,0.2473,0.1730,0.0363",\ +"0.4816,0.4699,0.4543,0.4270,0.3840,0.3098,0.1770"); + } + + fall_constraint("SIG2SRAM_constraint_template") { + index_1("0.0040,0.0176,0.0344,0.0656,0.1120,0.2016,0.3800"); + index_2("0.0040,0.0176,0.0344,0.0656,0.1120,0.2016,0.3800"); + values ("0.1613,0.1496,0.1379,0.1105,0.0715,0.0012,-0.1355",\ +"0.1730,0.1613,0.1496,0.1184,0.0832,0.0129,-0.1238",\ +"0.1887,0.1770,0.1652,0.1340,0.0988,0.0285,-0.1121",\ +"0.2121,0.2043,0.1887,0.1613,0.1223,0.0520,-0.0848",\ +"0.2551,0.2434,0.2277,0.2004,0.1613,0.0910,-0.0418",\ +"0.3293,0.3176,0.3020,0.2746,0.2395,0.1652,0.0324",\ +"0.4660,0.4543,0.4426,0.4113,0.3762,0.3020,0.1691"); + } + } + } +bus(A_BIST_BM) { + bus_type : D_15_0; + direction : input ; + capacitance : 0.00353394 ; + max_transition : "0.38" ; + pin(A_BIST_BM[15:0]) { + related_power_pin : VDD; + related_ground_pin : VSS; + internal_power() { + when : "A_BIST_MEN"; + rise_power("scalar"){ + values (0.0914); + } + fall_power("scalar"){ + values (0.0775); + } + } + internal_power() { + when : "!A_BIST_MEN"; + rise_power("scalar"){ + values (0.0871); + } + fall_power("scalar"){ + values (0.0796); + } + } + } + timing() { + timing_type : setup_rising; + related_pin : "A_BIST_CLK"; + when : "(A_BIST_WEN & A_BIST_MEN)" + sdf_cond : "A_BIST_RW_ACCESS" + + rise_constraint("SIG2SRAM_constraint_template") { + index_1("0.0040,0.0176,0.0344,0.0656,0.1120,0.2016,0.3800"); + index_2("0.0040,0.0176,0.0344,0.0656,0.1120,0.2016,0.3800"); + values ("-0.2116,-0.2009,-0.1853,-0.1599,-0.1189,-0.0456,0.0891",\ +"-0.2155,-0.2048,-0.1891,-0.1638,-0.1227,-0.0495,0.0853",\ +"-0.2192,-0.2085,-0.1928,-0.1674,-0.1264,-0.0532,0.0816",\ +"-0.2224,-0.2116,-0.1960,-0.1706,-0.1296,-0.0564,0.0784",\ +"-0.2350,-0.2243,-0.2086,-0.1833,-0.1422,-0.0690,0.0658",\ +"-0.2526,-0.2419,-0.2263,-0.2009,-0.1598,-0.0866,0.0482",\ +"-0.2801,-0.2694,-0.2538,-0.2284,-0.1874,-0.1141,0.0207"); + } + + fall_constraint("SIG2SRAM_constraint_template") { + index_1("0.0040,0.0176,0.0344,0.0656,0.1120,0.2016,0.3800"); + index_2("0.0040,0.0176,0.0344,0.0656,0.1120,0.2016,0.3800"); + values ("-0.1882,-0.1765,-0.1638,-0.1364,-0.0993,-0.0261,0.1018",\ +"-0.1921,-0.1804,-0.1677,-0.1403,-0.1032,-0.0300,0.0980",\ +"-0.1958,-0.1840,-0.1713,-0.1440,-0.1069,-0.0337,0.0943",\ +"-0.1990,-0.1872,-0.1745,-0.1472,-0.1101,-0.0368,0.0911",\ +"-0.2116,-0.1999,-0.1872,-0.1598,-0.1227,-0.0495,0.0785",\ +"-0.2292,-0.2175,-0.2048,-0.1774,-0.1403,-0.0671,0.0609",\ +"-0.2567,-0.2450,-0.2323,-0.2049,-0.1678,-0.0946,0.0333"); + } + } + + + timing() { + timing_type : hold_rising; + related_pin : "A_BIST_CLK"; + when : "(A_BIST_WEN & A_BIST_MEN)" + sdf_cond : "A_BIST_RW_ACCESS" + + rise_constraint("SIG2SRAM_constraint_template") { + index_1("0.0040,0.0176,0.0344,0.0656,0.1120,0.2016,0.3800"); + index_2("0.0040,0.0176,0.0344,0.0656,0.1120,0.2016,0.3800"); + values ("0.3170,0.3072,0.2916,0.2652,0.2281,0.1539,0.0192",\ +"0.3209,0.3111,0.2955,0.2691,0.2320,0.1578,0.0230",\ +"0.3246,0.3148,0.2992,0.2728,0.2357,0.1615,0.0267",\ +"0.3278,0.3180,0.3024,0.2760,0.2389,0.1647,0.0299",\ +"0.3404,0.3306,0.3150,0.2886,0.2515,0.1773,0.0425",\ +"0.3580,0.3482,0.3326,0.3062,0.2691,0.1949,0.0601",\ +"0.3855,0.3757,0.3601,0.3337,0.2966,0.2224,0.0877"); + } + + fall_constraint("SIG2SRAM_constraint_template") { + index_1("0.0040,0.0176,0.0344,0.0656,0.1120,0.2016,0.3800"); + index_2("0.0040,0.0176,0.0344,0.0656,0.1120,0.2016,0.3800"); + values ("0.2887,0.2779,0.2643,0.2369,0.2008,0.1285,-0.0013",\ +"0.2926,0.2818,0.2682,0.2408,0.2047,0.1324,0.0025",\ +"0.2962,0.2855,0.2718,0.2445,0.2084,0.1361,0.0062",\ +"0.2994,0.2887,0.2750,0.2477,0.2116,0.1393,0.0094",\ +"0.3121,0.3013,0.2877,0.2603,0.2242,0.1519,0.0220",\ +"0.3297,0.3189,0.3053,0.2779,0.2418,0.1695,0.0396",\ +"0.3572,0.3464,0.3328,0.3054,0.2693,0.1970,0.0671"); + } + } +} + pin(A_BIST_CLK) { + direction : input; + capacitance : 0.00389386; + max_transition : "0.38"; + clock : "true" ; + pin_func_type : active_rising ; + + timing () { + timing_type : "min_pulse_width"; + related_pin : "A_BIST_CLK"; + rise_constraint("CLKTRAN_constraint_template") { + index_1("0.004,0.38"); + values("0.12,0.12"); + } + } + + related_power_pin : VDD; + related_ground_pin : VSS; + + internal_power() { + when : "!A_BIST_MEN & !A_BIST_WEN & !A_BIST_REN"; + rise_power("scalar"){ + values (0); + } + fall_power("scalar"){ + values (0); + } + } + internal_power() { + when : "!A_BIST_MEN & A_BIST_WEN & !A_BIST_REN"; + rise_power("scalar"){ + values (0.6406); + } + fall_power("scalar"){ + values (0); + } + } + internal_power() { + when : "A_BIST_MEN & A_BIST_WEN & !A_BIST_REN"; + rise_power("scalar"){ + values (22.6954); + } + fall_power("scalar"){ + values (0); + } + } + internal_power() { + when : "A_BIST_MEN & A_BIST_WEN & A_BIST_REN"; + rise_power("scalar"){ + values (24.9897); + } + fall_power("scalar"){ + values (0); + } + } + internal_power() { + when : "A_BIST_MEN & !A_BIST_WEN & A_BIST_REN"; + rise_power("scalar"){ + values (18.3238); + } + fall_power("scalar"){ + values (0); + } + } + internal_power() { + when : "!A_BIST_MEN & !A_BIST_WEN & A_BIST_REN"; + rise_power("scalar"){ + values (0.3904); + } + fall_power("scalar"){ + values (0); + } + } + internal_power() { + when : "!A_BIST_MEN & A_BIST_WEN & A_BIST_REN"; + rise_power("scalar"){ + values (0.8744); + } + fall_power("scalar"){ + values (0); + } + } + internal_power() { + when : "A_BIST_MEN & !A_BIST_WEN & !A_BIST_REN"; + rise_power("scalar"){ + values (0); + } + fall_power("scalar"){ + values (0); + } + } + } + bus(A_BIST_DIN) { + bus_type : D_15_0; + direction : input ; + capacitance : 0.00397186 ; + memory_write() { + address : A_BIST_ADDR ; + clocked_on : A_BIST_CLK; + } + + max_transition : "0.38" ; + pin(A_BIST_DIN[15:0]) { + related_power_pin : VDD; + related_ground_pin : VSS; + internal_power() { + when : "A_BIST_MEN"; + rise_power("scalar"){ + values (0.0914); + } + fall_power("scalar"){ + values (0.0775); + } + } + internal_power() { + when : "!A_BIST_MEN"; + rise_power("scalar"){ + values (0.0871); + } + fall_power("scalar"){ + values (0.0796); + } + } + } + timing() { + timing_type : setup_rising; + related_pin : "A_BIST_CLK"; + when : "(A_BIST_WEN & A_BIST_MEN)"; + sdf_cond : "A_BIST_W_ACCESS"; + + rise_constraint("SIG2SRAM_constraint_template") { + index_1("0.0040,0.0176,0.0344,0.0656,0.1120,0.2016,0.3800"); + index_2("0.0040,0.0176,0.0344,0.0656,0.1120,0.2016,0.3800"); + values ("-0.2116,-0.2009,-0.1853,-0.1599,-0.1189,-0.0456,0.0891",\ +"-0.2155,-0.2048,-0.1891,-0.1638,-0.1227,-0.0495,0.0853",\ +"-0.2192,-0.2085,-0.1928,-0.1674,-0.1264,-0.0532,0.0816",\ +"-0.2224,-0.2116,-0.1960,-0.1706,-0.1296,-0.0564,0.0784",\ +"-0.2350,-0.2243,-0.2086,-0.1833,-0.1422,-0.0690,0.0658",\ +"-0.2526,-0.2419,-0.2263,-0.2009,-0.1598,-0.0866,0.0482",\ +"-0.2801,-0.2694,-0.2538,-0.2284,-0.1874,-0.1141,0.0207"); + } + + fall_constraint("SIG2SRAM_constraint_template") { + index_1("0.0040,0.0176,0.0344,0.0656,0.1120,0.2016,0.3800"); + index_2("0.0040,0.0176,0.0344,0.0656,0.1120,0.2016,0.3800"); + values ("-0.1882,-0.1765,-0.1638,-0.1364,-0.0993,-0.0261,0.1018",\ +"-0.1921,-0.1804,-0.1677,-0.1403,-0.1032,-0.0300,0.0980",\ +"-0.1958,-0.1840,-0.1713,-0.1440,-0.1069,-0.0337,0.0943",\ +"-0.1990,-0.1872,-0.1745,-0.1472,-0.1101,-0.0368,0.0911",\ +"-0.2116,-0.1999,-0.1872,-0.1598,-0.1227,-0.0495,0.0785",\ +"-0.2292,-0.2175,-0.2048,-0.1774,-0.1403,-0.0671,0.0609",\ +"-0.2567,-0.2450,-0.2323,-0.2049,-0.1678,-0.0946,0.0333"); + } + } + + timing() { + timing_type : hold_rising; + related_pin : "A_BIST_CLK"; + when : "(A_BIST_WEN & A_BIST_MEN)"; + sdf_cond : "A_BIST_W_ACCESS"; + + rise_constraint("SIG2SRAM_constraint_template") { + index_1("0.0040,0.0176,0.0344,0.0656,0.1120,0.2016,0.3800"); + index_2("0.0040,0.0176,0.0344,0.0656,0.1120,0.2016,0.3800"); + values ("0.3170,0.3072,0.2916,0.2652,0.2281,0.1539,0.0192",\ +"0.3209,0.3111,0.2955,0.2691,0.2320,0.1578,0.0230",\ +"0.3246,0.3148,0.2992,0.2728,0.2357,0.1615,0.0267",\ +"0.3278,0.3180,0.3024,0.2760,0.2389,0.1647,0.0299",\ +"0.3404,0.3306,0.3150,0.2886,0.2515,0.1773,0.0425",\ +"0.3580,0.3482,0.3326,0.3062,0.2691,0.1949,0.0601",\ +"0.3855,0.3757,0.3601,0.3337,0.2966,0.2224,0.0877"); + } + + fall_constraint("SIG2SRAM_constraint_template") { + index_1("0.0040,0.0176,0.0344,0.0656,0.1120,0.2016,0.3800"); + index_2("0.0040,0.0176,0.0344,0.0656,0.1120,0.2016,0.3800"); + values ("0.2887,0.2779,0.2643,0.2369,0.2008,0.1285,-0.0013",\ +"0.2926,0.2818,0.2682,0.2408,0.2047,0.1324,0.0025",\ +"0.2962,0.2855,0.2718,0.2445,0.2084,0.1361,0.0062",\ +"0.2994,0.2887,0.2750,0.2477,0.2116,0.1393,0.0094",\ +"0.3121,0.3013,0.2877,0.2603,0.2242,0.1519,0.0220",\ +"0.3297,0.3189,0.3053,0.2779,0.2418,0.1695,0.0396",\ +"0.3572,0.3464,0.3328,0.3054,0.2693,0.1970,0.0671"); + } + } + } + +bus(A_DOUT) { + + bus_type : D_15_0; + direction : output ; + capacitance : 0 ; + max_capacitance : 0.064 ; + memory_read() { + address : A_ADDR ; + } + pin(A_DOUT[15:0]) { + related_power_pin : VDD; + related_ground_pin : VSS; + internal_power() { + rise_power("scalar") { + values (0); + } + fall_power("scalar") { + values (0); + } + } + } + timing() { + related_pin : "A_CLK"; + timing_type : rising_edge ; + timing_sense : non_unate ; + + cell_rise(SIG2SRAM_delay_template) { + index_1("0.0040,0.0176,0.0344,0.0656,0.1120,0.2016,0.3800"); + index_2("0.0008,0.0014,0.0051,0.0100,0.0339,0.0640"); + values ("1.8529,1.8539,1.8587,1.8642,1.8851,1.9086",\ +"1.8588,1.8598,1.8646,1.8701,1.8911,1.9146",\ +"1.8616,1.8626,1.8674,1.8729,1.8938,1.9173",\ +"1.8658,1.8668,1.8716,1.8771,1.8980,1.9215",\ +"1.8774,1.8784,1.8832,1.8887,1.9096,1.9331",\ +"1.8965,1.8975,1.9023,1.9078,1.9287,1.9522",\ +"1.9229,1.9239,1.9287,1.9342,1.9551,1.9786"); + } + cell_fall(SIG2SRAM_delay_template) { + index_1("0.0040,0.0176,0.0344,0.0656,0.1120,0.2016,0.3800"); + index_2("0.0008,0.0014,0.0051,0.0100,0.0339,0.0640"); + values ("1.8186,1.8194,1.8235,1.8280,1.8451,1.8618",\ +"1.8245,1.8254,1.8294,1.8340,1.8510,1.8678",\ +"1.8273,1.8281,1.8322,1.8367,1.8538,1.8705",\ +"1.8315,1.8323,1.8364,1.8409,1.8580,1.8747",\ +"1.8431,1.8439,1.8480,1.8525,1.8696,1.8863",\ +"1.8622,1.8631,1.8671,1.8716,1.8887,1.9055",\ +"1.8886,1.8894,1.8935,1.8980,1.9151,1.9318"); + } + + rise_transition(SRAM_load_template) { + index_1("0.0008,0.0014,0.0051,0.0100,0.0339,0.0640"); + values ("0.0206,0.0210,0.0265,0.0323,0.0606,0.0955"); + } + fall_transition(SRAM_load_template) { + index_1("0.0008,0.0014,0.0051,0.0100,0.0339,0.0640"); + values ("0.0170,0.0177,0.0222,0.0270,0.0451,0.0644"); + } + } +} + pin(B_DLY) { + direction : input ; + capacitance : 0.00421562 ; + max_transition : "1" ; + related_power_pin : VDD; + related_ground_pin : VSS; + internal_power() { + rise_power("scalar") { + values (0); + } + fall_power("scalar") { + values (0); + } + } + } + +bus(B_ADDR) { + bus_type : A_7_0; + direction : input ; + capacitance : 0.0115194 ; + pin(B_ADDR[0]) { + capacitance : 0.0056487 ; + } + pin(B_ADDR[1]) { + capacitance : 0.00741688 ; + } + pin(B_ADDR[2]) { + capacitance : 0.0100613 ; + } + pin(B_ADDR[3]) { + capacitance : 0.00667339 ; + } + pin(B_ADDR[4]) { + capacitance : 0.00620204 ; + } + pin(B_ADDR[5]) { + capacitance : 0.0101975 ; + } + pin(B_ADDR[6]) { + capacitance : 0.0124055 ; + } + max_transition : "0.38" ; + pin(B_ADDR[7:0]) { + related_power_pin : VDD; + related_ground_pin : VSS; + internal_power() { + when : "B_MEN"; + rise_power("scalar"){ + values (0.0119); + } + fall_power("scalar"){ + values (0.0026); + } + } + internal_power() { + when : "!B_MEN"; + rise_power("scalar"){ + values (0.0264); + } + fall_power("scalar"){ + values (0.0021); + } + } + } + timing() { + timing_type : setup_rising; + related_pin : "B_CLK"; + when : "((B_WEN | B_REN)& B_MEN)" + sdf_cond : "B_RW_ACCESS" + + rise_constraint("SIG2SRAM_constraint_template") { + index_1("0.0040,0.0176,0.0344,0.0656,0.1120,0.2016,0.3800"); + index_2("0.0040,0.0176,0.0344,0.0656,0.1120,0.2016,0.3800"); + values ("-0.2371,-0.2215,-0.2098,-0.1824,-0.1434,-0.0691,0.0676",\ +"-0.2449,-0.2332,-0.2176,-0.1902,-0.1551,-0.0770,0.0559",\ +"-0.2605,-0.2488,-0.2332,-0.2059,-0.1707,-0.0965,0.0441",\ +"-0.2879,-0.2723,-0.2605,-0.2332,-0.1941,-0.1199,0.0168",\ +"-0.3230,-0.3113,-0.2996,-0.2723,-0.2332,-0.1590,-0.0184",\ +"-0.4012,-0.3895,-0.3738,-0.3465,-0.3074,-0.2332,-0.0965",\ +"-0.5379,-0.5262,-0.5105,-0.4832,-0.4480,-0.3699,-0.2332"); + } + + fall_constraint("SIG2SRAM_constraint_template") { + index_1("0.0040,0.0176,0.0344,0.0656,0.1120,0.2016,0.3800"); + index_2("0.0040,0.0176,0.0344,0.0656,0.1120,0.2016,0.3800"); + values ("-0.1785,-0.1707,-0.1551,-0.1277,-0.0887,-0.0184,0.1145",\ +"-0.1902,-0.1785,-0.1629,-0.1355,-0.1004,-0.0262,0.1027",\ +"-0.2059,-0.1941,-0.1785,-0.1512,-0.1160,-0.0418,0.0871",\ +"-0.2293,-0.2176,-0.2059,-0.1785,-0.1434,-0.0691,0.0598",\ +"-0.2684,-0.2566,-0.2449,-0.2176,-0.1824,-0.1082,0.0207",\ +"-0.3465,-0.3348,-0.3191,-0.2918,-0.2566,-0.1824,-0.0535",\ +"-0.4832,-0.4715,-0.4559,-0.4324,-0.3934,-0.3191,-0.1902"); + } + } + + + timing() { + timing_type : hold_rising; + related_pin : "B_CLK"; + when : "((B_WEN | B_REN)& B_MEN)" + sdf_cond : "B_RW_ACCESS" + + rise_constraint("SIG2SRAM_constraint_template") { + index_1("0.0040,0.0176,0.0344,0.0656,0.1120,0.2016,0.3800"); + index_2("0.0040,0.0176,0.0344,0.0656,0.1120,0.2016,0.3800"); + values ("0.3410,0.3293,0.3137,0.2863,0.2473,0.1730,0.0324",\ +"0.3488,0.3371,0.3215,0.2941,0.2590,0.1809,0.0480",\ +"0.3684,0.3527,0.3371,0.3098,0.2746,0.1965,0.0598",\ +"0.3918,0.3762,0.3645,0.3371,0.2980,0.2238,0.0871",\ +"0.4309,0.4152,0.4035,0.3762,0.3371,0.2629,0.1223",\ +"0.5051,0.4934,0.4777,0.4504,0.4113,0.3371,0.1965",\ +"0.6418,0.6262,0.6145,0.5871,0.5520,0.4738,0.3332"); + } + + fall_constraint("SIG2SRAM_constraint_template") { + index_1("0.0040,0.0176,0.0344,0.0656,0.1120,0.2016,0.3800"); + index_2("0.0040,0.0176,0.0344,0.0656,0.1120,0.2016,0.3800"); + values ("0.2824,0.2707,0.2551,0.2277,0.1926,0.1184,-0.0105",\ +"0.2902,0.2785,0.2668,0.2395,0.2043,0.1301,0.0012",\ +"0.3059,0.2941,0.2824,0.2551,0.2199,0.1457,0.0168",\ +"0.3332,0.3215,0.3059,0.2785,0.2434,0.1691,0.0402",\ +"0.3723,0.3605,0.3449,0.3176,0.2824,0.2121,0.0793",\ +"0.4465,0.4348,0.4230,0.3918,0.3566,0.2824,0.1535",\ +"0.5832,0.5715,0.5598,0.5324,0.4934,0.4191,0.2902"); + } + } +} +pin(B_WEN) { + direction : input ; + capacitance : 0.00341384 ; + max_transition : "0.38" ; + related_power_pin : VDD; + related_ground_pin : VSS; + internal_power() { + when : "B_MEN"; + rise_power("scalar"){ + values (0.0061); + } + fall_power("scalar"){ + values (0.0158); + } + } + internal_power() { + when : "!B_MEN"; + rise_power("scalar"){ + values (0.0054); + } + fall_power("scalar"){ + values (0.0210); + } + } + timing() { + timing_type : setup_rising; + related_pin : "B_CLK"; + when : "B_MEN" + sdf_cond : "B_MEN" + + rise_constraint("SIG2SRAM_constraint_template") { + index_1("0.0040,0.0176,0.0344,0.0656,0.1120,0.2016,0.3800"); + index_2("0.0040,0.0176,0.0344,0.0656,0.1120,0.2016,0.3800"); + values ("0.1418,0.1496,0.1652,0.1887,0.2316,0.3059,0.4465",\ +"0.1301,0.1379,0.1535,0.1809,0.2199,0.2941,0.4348",\ +"0.1145,0.1262,0.1379,0.1652,0.2043,0.2785,0.4191",\ +"0.0871,0.0949,0.1105,0.1379,0.1770,0.2512,0.3879",\ +"0.0480,0.0598,0.0754,0.0988,0.1379,0.2082,0.3527",\ +"-0.0262,-0.0145,0.0012,0.0246,0.0676,0.1379,0.2785",\ +"-0.1668,-0.1551,-0.1395,-0.1121,-0.0730,0.0012,0.1418"); + } + + fall_constraint("SIG2SRAM_constraint_template") { + index_1("0.0040,0.0176,0.0344,0.0656,0.1120,0.2016,0.3800"); + index_2("0.0040,0.0176,0.0344,0.0656,0.1120,0.2016,0.3800"); + values ("0.2082,0.2160,0.2316,0.2590,0.2941,0.3684,0.5012",\ +"0.1926,0.2043,0.2199,0.2473,0.2824,0.3566,0.4895",\ +"0.1770,0.1887,0.2043,0.2316,0.2668,0.3410,0.4777",\ +"0.1535,0.1652,0.1770,0.2043,0.2395,0.3137,0.4504",\ +"0.1145,0.1262,0.1379,0.1652,0.2043,0.2746,0.4113",\ +"0.0402,0.0520,0.0676,0.0910,0.1262,0.2004,0.3332",\ +"-0.0965,-0.0848,-0.0730,-0.0457,-0.0066,0.0637,0.2004"); + } + } + + + timing() { + timing_type : hold_rising; + related_pin : "B_CLK"; + when : "B_MEN" + sdf_cond : "B_MEN" + + rise_constraint("SIG2SRAM_constraint_template") { + index_1("0.0040,0.0176,0.0344,0.0656,0.1120,0.2016,0.3800"); + index_2("0.0040,0.0176,0.0344,0.0656,0.1120,0.2016,0.3800"); + values ("0.1770,0.1652,0.1496,0.1223,0.0793,0.0090,-0.1316",\ +"0.1848,0.1730,0.1574,0.1301,0.0910,0.0168,-0.1199",\ +"0.2004,0.1887,0.1770,0.1496,0.1066,0.0363,-0.1043",\ +"0.2277,0.2160,0.2004,0.1730,0.1340,0.0598,-0.0809",\ +"0.2668,0.2551,0.2395,0.2121,0.1730,0.0988,-0.0418",\ +"0.3410,0.3293,0.3137,0.2863,0.2434,0.1730,0.0324",\ +"0.4816,0.4699,0.4543,0.4230,0.3801,0.3098,0.1730"); + } + + fall_constraint("SIG2SRAM_constraint_template") { + index_1("0.0040,0.0176,0.0344,0.0656,0.1120,0.2016,0.3800"); + index_2("0.0040,0.0176,0.0344,0.0656,0.1120,0.2016,0.3800"); + values ("0.1613,0.1496,0.1379,0.1066,0.0715,0.0012,-0.1355",\ +"0.1730,0.1613,0.1457,0.1184,0.0832,0.0129,-0.1238",\ +"0.1887,0.1770,0.1613,0.1340,0.0988,0.0246,-0.1121",\ +"0.2121,0.2043,0.1887,0.1613,0.1223,0.0520,-0.0848",\ +"0.2512,0.2434,0.2277,0.2004,0.1613,0.0910,-0.0457",\ +"0.3254,0.3176,0.3020,0.2746,0.2355,0.1652,0.0324",\ +"0.4660,0.4543,0.4387,0.4113,0.3723,0.3020,0.1691"); + } + } + } +pin(B_REN) { + direction : input ; + capacitance : 0.00390661 ; + max_transition : "0.38" ; + related_power_pin : VDD; + related_ground_pin : VSS; + internal_power() { + when : "B_MEN"; + rise_power("scalar"){ + values (0.0108); + } + fall_power("scalar"){ + values (0.0104); + } + } + internal_power() { + when : "!B_MEN"; + rise_power("scalar"){ + values (0.0222); + } + fall_power("scalar"){ + values (0.0197); + } + } + timing() { + timing_type : setup_rising; + related_pin : "B_CLK"; + when : "B_MEN" + sdf_cond : "B_MEN" + + rise_constraint("SIG2SRAM_constraint_template") { + index_1("0.0040,0.0176,0.0344,0.0656,0.1120,0.2016,0.3800"); + index_2("0.0040,0.0176,0.0344,0.0656,0.1120,0.2016,0.3800"); + values ("-0.0027,0.0090,0.0246,0.0520,0.0910,0.1613,0.3020",\ +"-0.0105,0.0012,0.0129,0.0363,0.0793,0.1535,0.2902",\ +"-0.0262,-0.0145,-0.0027,0.0246,0.0637,0.1379,0.2785",\ +"-0.0535,-0.0418,-0.0262,0.0012,0.0363,0.1105,0.2512",\ +"-0.0926,-0.0809,-0.0652,-0.0418,-0.0027,0.0715,0.2121",\ +"-0.1668,-0.1551,-0.1395,-0.1082,-0.0770,-0.0027,0.1379",\ +"-0.3035,-0.2918,-0.2762,-0.2488,-0.2137,-0.1434,-0.0027"); + } + + fall_constraint("SIG2SRAM_constraint_template") { + index_1("0.0040,0.0176,0.0344,0.0656,0.1120,0.2016,0.3800"); + index_2("0.0040,0.0176,0.0344,0.0656,0.1120,0.2016,0.3800"); + values ("0.0832,0.0949,0.1105,0.1379,0.1730,0.2473,0.3801",\ +"0.0754,0.0832,0.0988,0.1223,0.1613,0.2355,0.3684",\ +"0.0598,0.0676,0.0832,0.1066,0.1457,0.2121,0.3527",\ +"0.0324,0.0441,0.0598,0.0871,0.1223,0.1926,0.3293",\ +"-0.0066,0.0051,0.0168,0.0480,0.0832,0.1535,0.2902",\ +"-0.0809,-0.0691,-0.0574,-0.0301,0.0090,0.0832,0.2121",\ +"-0.2176,-0.2059,-0.1941,-0.1668,-0.1277,-0.0574,0.0793"); + } + } + + + timing() { + timing_type : hold_rising; + related_pin : "B_CLK"; + when : "B_MEN" + sdf_cond : "B_MEN" + + rise_constraint("SIG2SRAM_constraint_template") { + index_1("0.0040,0.0176,0.0344,0.0656,0.1120,0.2016,0.3800"); + index_2("0.0040,0.0176,0.0344,0.0656,0.1120,0.2016,0.3800"); + values ("0.1887,0.1770,0.1613,0.1340,0.0949,0.0207,-0.1160",\ +"0.1965,0.1848,0.1730,0.1457,0.1027,0.0324,-0.1082",\ +"0.2160,0.2004,0.1887,0.1613,0.1184,0.0480,-0.0926",\ +"0.2395,0.2277,0.2121,0.1848,0.1457,0.0715,-0.0652",\ +"0.2785,0.2668,0.2512,0.2238,0.1848,0.1105,-0.0262",\ +"0.3527,0.3410,0.3254,0.2980,0.2551,0.1848,0.0480",\ +"0.4934,0.4816,0.4660,0.4387,0.3957,0.3254,0.1887"); + } + + fall_constraint("SIG2SRAM_constraint_template") { + index_1("0.0040,0.0176,0.0344,0.0656,0.1120,0.2016,0.3800"); + index_2("0.0040,0.0176,0.0344,0.0656,0.1120,0.2016,0.3800"); + values ("0.1730,0.1613,0.1496,0.1184,0.0793,0.0129,-0.1238",\ +"0.1848,0.1730,0.1574,0.1301,0.0910,0.0207,-0.1121",\ +"0.2004,0.1887,0.1730,0.1457,0.1066,0.0363,-0.1004",\ +"0.2238,0.2121,0.2004,0.1691,0.1340,0.0598,-0.0730",\ +"0.2629,0.2512,0.2395,0.2121,0.1691,0.0988,-0.0340",\ +"0.3371,0.3254,0.3137,0.2863,0.2434,0.1730,0.0402",\ +"0.4777,0.4660,0.4504,0.4230,0.3840,0.3137,0.1809"); + } + } + } +pin(B_MEN) { + direction : input ; + capacitance : 0.00326046 ; + max_transition : "0.38" ; + related_power_pin : VDD; + related_ground_pin : VSS; + internal_power() { + rise_power("scalar"){ + values (0.1424); + } + fall_power("scalar"){ + values (0.0108); + } + } + timing() { + timing_type : setup_rising; + related_pin : "B_CLK"; + + rise_constraint("SIG2SRAM_constraint_template") { + index_1("0.0040,0.0176,0.0344,0.0656,0.1120,0.2016,0.3800"); + index_2("0.0040,0.0176,0.0344,0.0656,0.1120,0.2016,0.3800"); + values ("0.1418,0.1496,0.1652,0.1926,0.2316,0.3059,0.4465",\ +"0.1301,0.1379,0.1535,0.1809,0.2199,0.2941,0.4348",\ +"0.1145,0.1262,0.1418,0.1652,0.2043,0.2785,0.4191",\ +"0.0871,0.0949,0.1105,0.1379,0.1770,0.2512,0.3879",\ +"0.0480,0.0598,0.0754,0.0988,0.1379,0.2082,0.3488",\ +"-0.0262,-0.0145,0.0012,0.0285,0.0676,0.1379,0.2785",\ +"-0.1668,-0.1551,-0.1395,-0.1121,-0.0730,0.0012,0.1379"); + } + + fall_constraint("SIG2SRAM_constraint_template") { + index_1("0.0040,0.0176,0.0344,0.0656,0.1120,0.2016,0.3800"); + index_2("0.0040,0.0176,0.0344,0.0656,0.1120,0.2016,0.3800"); + values ("0.2082,0.2199,0.2316,0.2590,0.2980,0.3723,0.5051",\ +"0.1965,0.2082,0.2199,0.2473,0.2863,0.3605,0.4934",\ +"0.1809,0.1926,0.2043,0.2316,0.2707,0.3449,0.4777",\ +"0.1574,0.1691,0.1809,0.2082,0.2434,0.3176,0.4543",\ +"0.1145,0.1262,0.1418,0.1691,0.2043,0.2785,0.4113",\ +"0.0441,0.0559,0.0676,0.0949,0.1301,0.2004,0.3332",\ +"-0.0965,-0.0848,-0.0691,-0.0418,-0.0066,0.0676,0.2004"); + } + } + + + timing() { + timing_type : hold_rising; + related_pin : "B_CLK"; + + rise_constraint("SIG2SRAM_constraint_template") { + index_1("0.0040,0.0176,0.0344,0.0656,0.1120,0.2016,0.3800"); + index_2("0.0040,0.0176,0.0344,0.0656,0.1120,0.2016,0.3800"); + values ("0.1770,0.1652,0.1535,0.1262,0.0832,0.0129,-0.1277",\ +"0.1887,0.1770,0.1613,0.1340,0.0949,0.0207,-0.1199",\ +"0.2043,0.1926,0.1770,0.1496,0.1105,0.0363,-0.1043",\ +"0.2277,0.2160,0.2043,0.1770,0.1379,0.0598,-0.0770",\ +"0.2668,0.2551,0.2434,0.2160,0.1730,0.0988,-0.0379",\ +"0.3449,0.3332,0.3176,0.2902,0.2473,0.1730,0.0363",\ +"0.4816,0.4699,0.4543,0.4270,0.3840,0.3098,0.1770"); + } + + fall_constraint("SIG2SRAM_constraint_template") { + index_1("0.0040,0.0176,0.0344,0.0656,0.1120,0.2016,0.3800"); + index_2("0.0040,0.0176,0.0344,0.0656,0.1120,0.2016,0.3800"); + values ("0.1613,0.1496,0.1379,0.1105,0.0715,0.0012,-0.1355",\ +"0.1730,0.1613,0.1496,0.1184,0.0832,0.0129,-0.1238",\ +"0.1887,0.1770,0.1652,0.1340,0.0988,0.0285,-0.1121",\ +"0.2121,0.2043,0.1887,0.1613,0.1223,0.0520,-0.0848",\ +"0.2551,0.2434,0.2277,0.2004,0.1613,0.0910,-0.0418",\ +"0.3293,0.3176,0.3020,0.2746,0.2395,0.1652,0.0324",\ +"0.4660,0.4543,0.4426,0.4113,0.3762,0.3020,0.1691"); + } + } + } +bus(B_BM) { + bus_type : D_15_0; + direction : input ; + capacitance : 0.00334781 ; + max_transition : "0.38" ; + pin(B_BM[15:0]) { + related_power_pin : VDD; + related_ground_pin : VSS; + internal_power() { + when : "B_MEN"; + rise_power("scalar"){ + values (0.0914); + } + fall_power("scalar"){ + values (0.0775); + } + } + internal_power() { + when : "!B_MEN"; + rise_power("scalar"){ + values (0.0871); + } + fall_power("scalar"){ + values (0.0796); + } + } + } + timing() { + timing_type : setup_rising; + related_pin : "B_CLK"; + when : "(B_WEN & B_MEN)" + sdf_cond : "B_RW_ACCESS" + + rise_constraint("SIG2SRAM_constraint_template") { + index_1("0.0040,0.0176,0.0344,0.0656,0.1120,0.2016,0.3800"); + index_2("0.0040,0.0176,0.0344,0.0656,0.1120,0.2016,0.3800"); + values ("-0.2116,-0.2009,-0.1853,-0.1599,-0.1189,-0.0456,0.0891",\ +"-0.2155,-0.2048,-0.1891,-0.1638,-0.1227,-0.0495,0.0853",\ +"-0.2192,-0.2085,-0.1928,-0.1674,-0.1264,-0.0532,0.0816",\ +"-0.2224,-0.2116,-0.1960,-0.1706,-0.1296,-0.0564,0.0784",\ +"-0.2350,-0.2243,-0.2086,-0.1833,-0.1422,-0.0690,0.0658",\ +"-0.2526,-0.2419,-0.2263,-0.2009,-0.1598,-0.0866,0.0482",\ +"-0.2801,-0.2694,-0.2538,-0.2284,-0.1874,-0.1141,0.0207"); + } + + fall_constraint("SIG2SRAM_constraint_template") { + index_1("0.0040,0.0176,0.0344,0.0656,0.1120,0.2016,0.3800"); + index_2("0.0040,0.0176,0.0344,0.0656,0.1120,0.2016,0.3800"); + values ("-0.1882,-0.1765,-0.1638,-0.1364,-0.0993,-0.0261,0.1018",\ +"-0.1921,-0.1804,-0.1677,-0.1403,-0.1032,-0.0300,0.0980",\ +"-0.1958,-0.1840,-0.1713,-0.1440,-0.1069,-0.0337,0.0943",\ +"-0.1990,-0.1872,-0.1745,-0.1472,-0.1101,-0.0368,0.0911",\ +"-0.2116,-0.1999,-0.1872,-0.1598,-0.1227,-0.0495,0.0785",\ +"-0.2292,-0.2175,-0.2048,-0.1774,-0.1403,-0.0671,0.0609",\ +"-0.2567,-0.2450,-0.2323,-0.2049,-0.1678,-0.0946,0.0333"); + } + } + + + timing() { + timing_type : hold_rising; + related_pin : "B_CLK"; + when : "(B_WEN & B_MEN)" + sdf_cond : "B_RW_ACCESS" + + rise_constraint("SIG2SRAM_constraint_template") { + index_1("0.0040,0.0176,0.0344,0.0656,0.1120,0.2016,0.3800"); + index_2("0.0040,0.0176,0.0344,0.0656,0.1120,0.2016,0.3800"); + values ("0.3170,0.3072,0.2916,0.2652,0.2281,0.1539,0.0192",\ +"0.3209,0.3111,0.2955,0.2691,0.2320,0.1578,0.0230",\ +"0.3246,0.3148,0.2992,0.2728,0.2357,0.1615,0.0267",\ +"0.3278,0.3180,0.3024,0.2760,0.2389,0.1647,0.0299",\ +"0.3404,0.3306,0.3150,0.2886,0.2515,0.1773,0.0425",\ +"0.3580,0.3482,0.3326,0.3062,0.2691,0.1949,0.0601",\ +"0.3855,0.3757,0.3601,0.3337,0.2966,0.2224,0.0877"); + } + + fall_constraint("SIG2SRAM_constraint_template") { + index_1("0.0040,0.0176,0.0344,0.0656,0.1120,0.2016,0.3800"); + index_2("0.0040,0.0176,0.0344,0.0656,0.1120,0.2016,0.3800"); + values ("0.2887,0.2779,0.2643,0.2369,0.2008,0.1285,-0.0013",\ +"0.2926,0.2818,0.2682,0.2408,0.2047,0.1324,0.0025",\ +"0.2962,0.2855,0.2718,0.2445,0.2084,0.1361,0.0062",\ +"0.2994,0.2887,0.2750,0.2477,0.2116,0.1393,0.0094",\ +"0.3121,0.3013,0.2877,0.2603,0.2242,0.1519,0.0220",\ +"0.3297,0.3189,0.3053,0.2779,0.2418,0.1695,0.0396",\ +"0.3572,0.3464,0.3328,0.3054,0.2693,0.1970,0.0671"); + } + } +} + pin(B_CLK) { + direction : input; + capacitance : 0.00389386; + max_transition : "0.38"; + clock : "true" ; + pin_func_type : active_rising ; + + timing () { + timing_type : "min_pulse_width"; + related_pin : "B_CLK"; + rise_constraint("CLKTRAN_constraint_template") { + index_1("0.004,0.38"); + values("0.12,0.12"); + } + } + + related_power_pin : VDD; + related_ground_pin : VSS; + + internal_power() { + when : "!B_MEN & !B_WEN & !B_REN"; + rise_power("scalar"){ + values (0); + } + fall_power("scalar"){ + values (0); + } + } + internal_power() { + when : "!B_MEN & B_WEN & !B_REN"; + rise_power("scalar"){ + values (0.6406); + } + fall_power("scalar"){ + values (0); + } + } + internal_power() { + when : "B_MEN & B_WEN & !B_REN"; + rise_power("scalar"){ + values (22.6954); + } + fall_power("scalar"){ + values (0); + } + } + internal_power() { + when : "B_MEN & B_WEN & B_REN"; + rise_power("scalar"){ + values (24.9897); + } + fall_power("scalar"){ + values (0); + } + } + internal_power() { + when : "B_MEN & !B_WEN & B_REN"; + rise_power("scalar"){ + values (18.3238); + } + fall_power("scalar"){ + values (0); + } + } + internal_power() { + when : "!B_MEN & !B_WEN & B_REN"; + rise_power("scalar"){ + values (0.3904); + } + fall_power("scalar"){ + values (0); + } + } + internal_power() { + when : "!B_MEN & B_WEN & B_REN"; + rise_power("scalar"){ + values (0.8744); + } + fall_power("scalar"){ + values (0); + } + } + internal_power() { + when : "B_MEN & !B_WEN & !B_REN"; + rise_power("scalar"){ + values (0); + } + fall_power("scalar"){ + values (0); + } + } + } + bus(B_DIN) { + bus_type : D_15_0; + direction : input ; + capacitance : 0.00468868 ; + memory_write() { + address : B_ADDR ; + clocked_on : B_CLK; + } + + max_transition : "0.38" ; + pin(B_DIN[15:0]) { + related_power_pin : VDD; + related_ground_pin : VSS; + internal_power() { + when : "B_MEN"; + rise_power("scalar"){ + values (0.0914); + } + fall_power("scalar"){ + values (0.0775); + } + } + internal_power() { + when : "!B_MEN"; + rise_power("scalar"){ + values (0.0871); + } + fall_power("scalar"){ + values (0.0796); + } + } + } + timing() { + timing_type : setup_rising; + related_pin : "B_CLK"; + when : "(B_WEN & B_MEN)"; + sdf_cond : "B_W_ACCESS"; + + rise_constraint("SIG2SRAM_constraint_template") { + index_1("0.0040,0.0176,0.0344,0.0656,0.1120,0.2016,0.3800"); + index_2("0.0040,0.0176,0.0344,0.0656,0.1120,0.2016,0.3800"); + values ("-0.2116,-0.2009,-0.1853,-0.1599,-0.1189,-0.0456,0.0891",\ +"-0.2155,-0.2048,-0.1891,-0.1638,-0.1227,-0.0495,0.0853",\ +"-0.2192,-0.2085,-0.1928,-0.1674,-0.1264,-0.0532,0.0816",\ +"-0.2224,-0.2116,-0.1960,-0.1706,-0.1296,-0.0564,0.0784",\ +"-0.2350,-0.2243,-0.2086,-0.1833,-0.1422,-0.0690,0.0658",\ +"-0.2526,-0.2419,-0.2263,-0.2009,-0.1598,-0.0866,0.0482",\ +"-0.2801,-0.2694,-0.2538,-0.2284,-0.1874,-0.1141,0.0207"); + } + + fall_constraint("SIG2SRAM_constraint_template") { + index_1("0.0040,0.0176,0.0344,0.0656,0.1120,0.2016,0.3800"); + index_2("0.0040,0.0176,0.0344,0.0656,0.1120,0.2016,0.3800"); + values ("-0.1882,-0.1765,-0.1638,-0.1364,-0.0993,-0.0261,0.1018",\ +"-0.1921,-0.1804,-0.1677,-0.1403,-0.1032,-0.0300,0.0980",\ +"-0.1958,-0.1840,-0.1713,-0.1440,-0.1069,-0.0337,0.0943",\ +"-0.1990,-0.1872,-0.1745,-0.1472,-0.1101,-0.0368,0.0911",\ +"-0.2116,-0.1999,-0.1872,-0.1598,-0.1227,-0.0495,0.0785",\ +"-0.2292,-0.2175,-0.2048,-0.1774,-0.1403,-0.0671,0.0609",\ +"-0.2567,-0.2450,-0.2323,-0.2049,-0.1678,-0.0946,0.0333"); + } + } + + timing() { + timing_type : hold_rising; + related_pin : "B_CLK"; + when : "(B_WEN & B_MEN)"; + sdf_cond : "B_W_ACCESS"; + + rise_constraint("SIG2SRAM_constraint_template") { + index_1("0.0040,0.0176,0.0344,0.0656,0.1120,0.2016,0.3800"); + index_2("0.0040,0.0176,0.0344,0.0656,0.1120,0.2016,0.3800"); + values ("0.3170,0.3072,0.2916,0.2652,0.2281,0.1539,0.0192",\ +"0.3209,0.3111,0.2955,0.2691,0.2320,0.1578,0.0230",\ +"0.3246,0.3148,0.2992,0.2728,0.2357,0.1615,0.0267",\ +"0.3278,0.3180,0.3024,0.2760,0.2389,0.1647,0.0299",\ +"0.3404,0.3306,0.3150,0.2886,0.2515,0.1773,0.0425",\ +"0.3580,0.3482,0.3326,0.3062,0.2691,0.1949,0.0601",\ +"0.3855,0.3757,0.3601,0.3337,0.2966,0.2224,0.0877"); + } + + fall_constraint("SIG2SRAM_constraint_template") { + index_1("0.0040,0.0176,0.0344,0.0656,0.1120,0.2016,0.3800"); + index_2("0.0040,0.0176,0.0344,0.0656,0.1120,0.2016,0.3800"); + values ("0.2887,0.2779,0.2643,0.2369,0.2008,0.1285,-0.0013",\ +"0.2926,0.2818,0.2682,0.2408,0.2047,0.1324,0.0025",\ +"0.2962,0.2855,0.2718,0.2445,0.2084,0.1361,0.0062",\ +"0.2994,0.2887,0.2750,0.2477,0.2116,0.1393,0.0094",\ +"0.3121,0.3013,0.2877,0.2603,0.2242,0.1519,0.0220",\ +"0.3297,0.3189,0.3053,0.2779,0.2418,0.1695,0.0396",\ +"0.3572,0.3464,0.3328,0.3054,0.2693,0.1970,0.0671"); + } + } + } + + pin(B_BIST_EN) { + direction : input ; + capacitance : 0.00421562 ; + max_transition : "1" ; + related_power_pin : VDD; + related_ground_pin : VSS; + internal_power() { + rise_power("scalar") { + values (0); + } + fall_power("scalar") { + values (0); + } + } + } + +bus(B_BIST_ADDR) { + bus_type : A_7_0; + direction : input ; + capacitance : 0.0115194 ; + pin(B_BIST_ADDR[0]) { + capacitance : 0.0056487 ; + } + pin(B_BIST_ADDR[1]) { + capacitance : 0.00741688 ; + } + pin(B_BIST_ADDR[2]) { + capacitance : 0.0100613 ; + } + pin(B_BIST_ADDR[3]) { + capacitance : 0.00667339 ; + } + pin(B_BIST_ADDR[4]) { + capacitance : 0.00620204 ; + } + pin(B_BIST_ADDR[5]) { + capacitance : 0.0101975 ; + } + pin(B_BIST_ADDR[6]) { + capacitance : 0.0124055 ; + } + max_transition : "0.38" ; + pin(B_BIST_ADDR[7:0]) { + related_power_pin : VDD; + related_ground_pin : VSS; + internal_power() { + when : "B_BIST_MEN"; + rise_power("scalar"){ + values (0.0119); + } + fall_power("scalar"){ + values (0.0026); + } + } + internal_power() { + when : "!B_BIST_MEN"; + rise_power("scalar"){ + values (0.0264); + } + fall_power("scalar"){ + values (0.0021); + } + } + } + timing() { + timing_type : setup_rising; + related_pin : "B_BIST_CLK"; + when : "((B_BIST_WEN | B_BIST_REN)& B_BIST_MEN)" + sdf_cond : "B_BIST_RW_ACCESS" + + rise_constraint("SIG2SRAM_constraint_template") { + index_1("0.0040,0.0176,0.0344,0.0656,0.1120,0.2016,0.3800"); + index_2("0.0040,0.0176,0.0344,0.0656,0.1120,0.2016,0.3800"); + values ("-0.2371,-0.2215,-0.2098,-0.1824,-0.1434,-0.0691,0.0676",\ +"-0.2449,-0.2332,-0.2176,-0.1902,-0.1551,-0.0770,0.0559",\ +"-0.2605,-0.2488,-0.2332,-0.2059,-0.1707,-0.0965,0.0441",\ +"-0.2879,-0.2723,-0.2605,-0.2332,-0.1941,-0.1199,0.0168",\ +"-0.3230,-0.3113,-0.2996,-0.2723,-0.2332,-0.1590,-0.0184",\ +"-0.4012,-0.3895,-0.3738,-0.3465,-0.3074,-0.2332,-0.0965",\ +"-0.5379,-0.5262,-0.5105,-0.4832,-0.4480,-0.3699,-0.2332"); + } + + fall_constraint("SIG2SRAM_constraint_template") { + index_1("0.0040,0.0176,0.0344,0.0656,0.1120,0.2016,0.3800"); + index_2("0.0040,0.0176,0.0344,0.0656,0.1120,0.2016,0.3800"); + values ("-0.1785,-0.1707,-0.1551,-0.1277,-0.0887,-0.0184,0.1145",\ +"-0.1902,-0.1785,-0.1629,-0.1355,-0.1004,-0.0262,0.1027",\ +"-0.2059,-0.1941,-0.1785,-0.1512,-0.1160,-0.0418,0.0871",\ +"-0.2293,-0.2176,-0.2059,-0.1785,-0.1434,-0.0691,0.0598",\ +"-0.2684,-0.2566,-0.2449,-0.2176,-0.1824,-0.1082,0.0207",\ +"-0.3465,-0.3348,-0.3191,-0.2918,-0.2566,-0.1824,-0.0535",\ +"-0.4832,-0.4715,-0.4559,-0.4324,-0.3934,-0.3191,-0.1902"); + } + } + + + timing() { + timing_type : hold_rising; + related_pin : "B_BIST_CLK"; + when : "((B_BIST_WEN | B_BIST_REN)& B_BIST_MEN)" + sdf_cond : "B_BIST_RW_ACCESS" + + rise_constraint("SIG2SRAM_constraint_template") { + index_1("0.0040,0.0176,0.0344,0.0656,0.1120,0.2016,0.3800"); + index_2("0.0040,0.0176,0.0344,0.0656,0.1120,0.2016,0.3800"); + values ("0.3410,0.3293,0.3137,0.2863,0.2473,0.1730,0.0324",\ +"0.3488,0.3371,0.3215,0.2941,0.2590,0.1809,0.0480",\ +"0.3684,0.3527,0.3371,0.3098,0.2746,0.1965,0.0598",\ +"0.3918,0.3762,0.3645,0.3371,0.2980,0.2238,0.0871",\ +"0.4309,0.4152,0.4035,0.3762,0.3371,0.2629,0.1223",\ +"0.5051,0.4934,0.4777,0.4504,0.4113,0.3371,0.1965",\ +"0.6418,0.6262,0.6145,0.5871,0.5520,0.4738,0.3332"); + } + + fall_constraint("SIG2SRAM_constraint_template") { + index_1("0.0040,0.0176,0.0344,0.0656,0.1120,0.2016,0.3800"); + index_2("0.0040,0.0176,0.0344,0.0656,0.1120,0.2016,0.3800"); + values ("0.2824,0.2707,0.2551,0.2277,0.1926,0.1184,-0.0105",\ +"0.2902,0.2785,0.2668,0.2395,0.2043,0.1301,0.0012",\ +"0.3059,0.2941,0.2824,0.2551,0.2199,0.1457,0.0168",\ +"0.3332,0.3215,0.3059,0.2785,0.2434,0.1691,0.0402",\ +"0.3723,0.3605,0.3449,0.3176,0.2824,0.2121,0.0793",\ +"0.4465,0.4348,0.4230,0.3918,0.3566,0.2824,0.1535",\ +"0.5832,0.5715,0.5598,0.5324,0.4934,0.4191,0.2902"); + } + } +} +pin(B_BIST_WEN) { + direction : input ; + capacitance : 0.00341384 ; + max_transition : "0.38" ; + related_power_pin : VDD; + related_ground_pin : VSS; + internal_power() { + when : "B_BIST_MEN"; + rise_power("scalar"){ + values (0.0061); + } + fall_power("scalar"){ + values (0.0158); + } + } + internal_power() { + when : "!B_BIST_MEN"; + rise_power("scalar"){ + values (0.0054); + } + fall_power("scalar"){ + values (0.0210); + } + } + timing() { + timing_type : setup_rising; + related_pin : "B_BIST_CLK"; + when : "B_BIST_MEN" + sdf_cond : "B_BIST_MEN" + + rise_constraint("SIG2SRAM_constraint_template") { + index_1("0.0040,0.0176,0.0344,0.0656,0.1120,0.2016,0.3800"); + index_2("0.0040,0.0176,0.0344,0.0656,0.1120,0.2016,0.3800"); + values ("0.1418,0.1496,0.1652,0.1887,0.2316,0.3059,0.4465",\ +"0.1301,0.1379,0.1535,0.1809,0.2199,0.2941,0.4348",\ +"0.1145,0.1262,0.1379,0.1652,0.2043,0.2785,0.4191",\ +"0.0871,0.0949,0.1105,0.1379,0.1770,0.2512,0.3879",\ +"0.0480,0.0598,0.0754,0.0988,0.1379,0.2082,0.3527",\ +"-0.0262,-0.0145,0.0012,0.0246,0.0676,0.1379,0.2785",\ +"-0.1668,-0.1551,-0.1395,-0.1121,-0.0730,0.0012,0.1418"); + } + + fall_constraint("SIG2SRAM_constraint_template") { + index_1("0.0040,0.0176,0.0344,0.0656,0.1120,0.2016,0.3800"); + index_2("0.0040,0.0176,0.0344,0.0656,0.1120,0.2016,0.3800"); + values ("0.2082,0.2160,0.2316,0.2590,0.2941,0.3684,0.5012",\ +"0.1926,0.2043,0.2199,0.2473,0.2824,0.3566,0.4895",\ +"0.1770,0.1887,0.2043,0.2316,0.2668,0.3410,0.4777",\ +"0.1535,0.1652,0.1770,0.2043,0.2395,0.3137,0.4504",\ +"0.1145,0.1262,0.1379,0.1652,0.2043,0.2746,0.4113",\ +"0.0402,0.0520,0.0676,0.0910,0.1262,0.2004,0.3332",\ +"-0.0965,-0.0848,-0.0730,-0.0457,-0.0066,0.0637,0.2004"); + } + } + + + timing() { + timing_type : hold_rising; + related_pin : "B_BIST_CLK"; + when : "B_BIST_MEN" + sdf_cond : "B_BIST_MEN" + + rise_constraint("SIG2SRAM_constraint_template") { + index_1("0.0040,0.0176,0.0344,0.0656,0.1120,0.2016,0.3800"); + index_2("0.0040,0.0176,0.0344,0.0656,0.1120,0.2016,0.3800"); + values ("0.1770,0.1652,0.1496,0.1223,0.0793,0.0090,-0.1316",\ +"0.1848,0.1730,0.1574,0.1301,0.0910,0.0168,-0.1199",\ +"0.2004,0.1887,0.1770,0.1496,0.1066,0.0363,-0.1043",\ +"0.2277,0.2160,0.2004,0.1730,0.1340,0.0598,-0.0809",\ +"0.2668,0.2551,0.2395,0.2121,0.1730,0.0988,-0.0418",\ +"0.3410,0.3293,0.3137,0.2863,0.2434,0.1730,0.0324",\ +"0.4816,0.4699,0.4543,0.4230,0.3801,0.3098,0.1730"); + } + + fall_constraint("SIG2SRAM_constraint_template") { + index_1("0.0040,0.0176,0.0344,0.0656,0.1120,0.2016,0.3800"); + index_2("0.0040,0.0176,0.0344,0.0656,0.1120,0.2016,0.3800"); + values ("0.1613,0.1496,0.1379,0.1066,0.0715,0.0012,-0.1355",\ +"0.1730,0.1613,0.1457,0.1184,0.0832,0.0129,-0.1238",\ +"0.1887,0.1770,0.1613,0.1340,0.0988,0.0246,-0.1121",\ +"0.2121,0.2043,0.1887,0.1613,0.1223,0.0520,-0.0848",\ +"0.2512,0.2434,0.2277,0.2004,0.1613,0.0910,-0.0457",\ +"0.3254,0.3176,0.3020,0.2746,0.2355,0.1652,0.0324",\ +"0.4660,0.4543,0.4387,0.4113,0.3723,0.3020,0.1691"); + } + } + } +pin(B_BIST_REN) { + direction : input ; + capacitance : 0.00390661 ; + max_transition : "0.38" ; + related_power_pin : VDD; + related_ground_pin : VSS; + internal_power() { + when : "B_BIST_MEN"; + rise_power("scalar"){ + values (0.0108); + } + fall_power("scalar"){ + values (0.0104); + } + } + internal_power() { + when : "!B_BIST_MEN"; + rise_power("scalar"){ + values (0.0222); + } + fall_power("scalar"){ + values (0.0197); + } + } + timing() { + timing_type : setup_rising; + related_pin : "B_BIST_CLK"; + when : "B_BIST_MEN" + sdf_cond : "B_BIST_MEN" + + rise_constraint("SIG2SRAM_constraint_template") { + index_1("0.0040,0.0176,0.0344,0.0656,0.1120,0.2016,0.3800"); + index_2("0.0040,0.0176,0.0344,0.0656,0.1120,0.2016,0.3800"); + values ("-0.0027,0.0090,0.0246,0.0520,0.0910,0.1613,0.3020",\ +"-0.0105,0.0012,0.0129,0.0363,0.0793,0.1535,0.2902",\ +"-0.0262,-0.0145,-0.0027,0.0246,0.0637,0.1379,0.2785",\ +"-0.0535,-0.0418,-0.0262,0.0012,0.0363,0.1105,0.2512",\ +"-0.0926,-0.0809,-0.0652,-0.0418,-0.0027,0.0715,0.2121",\ +"-0.1668,-0.1551,-0.1395,-0.1082,-0.0770,-0.0027,0.1379",\ +"-0.3035,-0.2918,-0.2762,-0.2488,-0.2137,-0.1434,-0.0027"); + } + + fall_constraint("SIG2SRAM_constraint_template") { + index_1("0.0040,0.0176,0.0344,0.0656,0.1120,0.2016,0.3800"); + index_2("0.0040,0.0176,0.0344,0.0656,0.1120,0.2016,0.3800"); + values ("0.0832,0.0949,0.1105,0.1379,0.1730,0.2473,0.3801",\ +"0.0754,0.0832,0.0988,0.1223,0.1613,0.2355,0.3684",\ +"0.0598,0.0676,0.0832,0.1066,0.1457,0.2121,0.3527",\ +"0.0324,0.0441,0.0598,0.0871,0.1223,0.1926,0.3293",\ +"-0.0066,0.0051,0.0168,0.0480,0.0832,0.1535,0.2902",\ +"-0.0809,-0.0691,-0.0574,-0.0301,0.0090,0.0832,0.2121",\ +"-0.2176,-0.2059,-0.1941,-0.1668,-0.1277,-0.0574,0.0793"); + } + } + + + timing() { + timing_type : hold_rising; + related_pin : "B_BIST_CLK"; + when : "B_BIST_MEN" + sdf_cond : "B_BIST_MEN" + + rise_constraint("SIG2SRAM_constraint_template") { + index_1("0.0040,0.0176,0.0344,0.0656,0.1120,0.2016,0.3800"); + index_2("0.0040,0.0176,0.0344,0.0656,0.1120,0.2016,0.3800"); + values ("0.1887,0.1770,0.1613,0.1340,0.0949,0.0207,-0.1160",\ +"0.1965,0.1848,0.1730,0.1457,0.1027,0.0324,-0.1082",\ +"0.2160,0.2004,0.1887,0.1613,0.1184,0.0480,-0.0926",\ +"0.2395,0.2277,0.2121,0.1848,0.1457,0.0715,-0.0652",\ +"0.2785,0.2668,0.2512,0.2238,0.1848,0.1105,-0.0262",\ +"0.3527,0.3410,0.3254,0.2980,0.2551,0.1848,0.0480",\ +"0.4934,0.4816,0.4660,0.4387,0.3957,0.3254,0.1887"); + } + + fall_constraint("SIG2SRAM_constraint_template") { + index_1("0.0040,0.0176,0.0344,0.0656,0.1120,0.2016,0.3800"); + index_2("0.0040,0.0176,0.0344,0.0656,0.1120,0.2016,0.3800"); + values ("0.1730,0.1613,0.1496,0.1184,0.0793,0.0129,-0.1238",\ +"0.1848,0.1730,0.1574,0.1301,0.0910,0.0207,-0.1121",\ +"0.2004,0.1887,0.1730,0.1457,0.1066,0.0363,-0.1004",\ +"0.2238,0.2121,0.2004,0.1691,0.1340,0.0598,-0.0730",\ +"0.2629,0.2512,0.2395,0.2121,0.1691,0.0988,-0.0340",\ +"0.3371,0.3254,0.3137,0.2863,0.2434,0.1730,0.0402",\ +"0.4777,0.4660,0.4504,0.4230,0.3840,0.3137,0.1809"); + } + } + } +pin(B_BIST_MEN) { + direction : input ; + capacitance : 0.00326046 ; + max_transition : "0.38" ; + related_power_pin : VDD; + related_ground_pin : VSS; + internal_power() { + rise_power("scalar"){ + values (0.1424); + } + fall_power("scalar"){ + values (0.0108); + } + } + timing() { + timing_type : setup_rising; + related_pin : "B_BIST_CLK"; + + rise_constraint("SIG2SRAM_constraint_template") { + index_1("0.0040,0.0176,0.0344,0.0656,0.1120,0.2016,0.3800"); + index_2("0.0040,0.0176,0.0344,0.0656,0.1120,0.2016,0.3800"); + values ("0.1418,0.1496,0.1652,0.1926,0.2316,0.3059,0.4465",\ +"0.1301,0.1379,0.1535,0.1809,0.2199,0.2941,0.4348",\ +"0.1145,0.1262,0.1418,0.1652,0.2043,0.2785,0.4191",\ +"0.0871,0.0949,0.1105,0.1379,0.1770,0.2512,0.3879",\ +"0.0480,0.0598,0.0754,0.0988,0.1379,0.2082,0.3488",\ +"-0.0262,-0.0145,0.0012,0.0285,0.0676,0.1379,0.2785",\ +"-0.1668,-0.1551,-0.1395,-0.1121,-0.0730,0.0012,0.1379"); + } + + fall_constraint("SIG2SRAM_constraint_template") { + index_1("0.0040,0.0176,0.0344,0.0656,0.1120,0.2016,0.3800"); + index_2("0.0040,0.0176,0.0344,0.0656,0.1120,0.2016,0.3800"); + values ("0.2082,0.2199,0.2316,0.2590,0.2980,0.3723,0.5051",\ +"0.1965,0.2082,0.2199,0.2473,0.2863,0.3605,0.4934",\ +"0.1809,0.1926,0.2043,0.2316,0.2707,0.3449,0.4777",\ +"0.1574,0.1691,0.1809,0.2082,0.2434,0.3176,0.4543",\ +"0.1145,0.1262,0.1418,0.1691,0.2043,0.2785,0.4113",\ +"0.0441,0.0559,0.0676,0.0949,0.1301,0.2004,0.3332",\ +"-0.0965,-0.0848,-0.0691,-0.0418,-0.0066,0.0676,0.2004"); + } + } + + + timing() { + timing_type : hold_rising; + related_pin : "B_BIST_CLK"; + + rise_constraint("SIG2SRAM_constraint_template") { + index_1("0.0040,0.0176,0.0344,0.0656,0.1120,0.2016,0.3800"); + index_2("0.0040,0.0176,0.0344,0.0656,0.1120,0.2016,0.3800"); + values ("0.1770,0.1652,0.1535,0.1262,0.0832,0.0129,-0.1277",\ +"0.1887,0.1770,0.1613,0.1340,0.0949,0.0207,-0.1199",\ +"0.2043,0.1926,0.1770,0.1496,0.1105,0.0363,-0.1043",\ +"0.2277,0.2160,0.2043,0.1770,0.1379,0.0598,-0.0770",\ +"0.2668,0.2551,0.2434,0.2160,0.1730,0.0988,-0.0379",\ +"0.3449,0.3332,0.3176,0.2902,0.2473,0.1730,0.0363",\ +"0.4816,0.4699,0.4543,0.4270,0.3840,0.3098,0.1770"); + } + + fall_constraint("SIG2SRAM_constraint_template") { + index_1("0.0040,0.0176,0.0344,0.0656,0.1120,0.2016,0.3800"); + index_2("0.0040,0.0176,0.0344,0.0656,0.1120,0.2016,0.3800"); + values ("0.1613,0.1496,0.1379,0.1105,0.0715,0.0012,-0.1355",\ +"0.1730,0.1613,0.1496,0.1184,0.0832,0.0129,-0.1238",\ +"0.1887,0.1770,0.1652,0.1340,0.0988,0.0285,-0.1121",\ +"0.2121,0.2043,0.1887,0.1613,0.1223,0.0520,-0.0848",\ +"0.2551,0.2434,0.2277,0.2004,0.1613,0.0910,-0.0418",\ +"0.3293,0.3176,0.3020,0.2746,0.2395,0.1652,0.0324",\ +"0.4660,0.4543,0.4426,0.4113,0.3762,0.3020,0.1691"); + } + } + } +bus(B_BIST_BM) { + bus_type : D_15_0; + direction : input ; + capacitance : 0.00290564 ; + max_transition : "0.38" ; + pin(B_BIST_BM[15:0]) { + related_power_pin : VDD; + related_ground_pin : VSS; + internal_power() { + when : "B_BIST_MEN"; + rise_power("scalar"){ + values (0.0914); + } + fall_power("scalar"){ + values (0.0775); + } + } + internal_power() { + when : "!B_BIST_MEN"; + rise_power("scalar"){ + values (0.0871); + } + fall_power("scalar"){ + values (0.0796); + } + } + } + timing() { + timing_type : setup_rising; + related_pin : "B_BIST_CLK"; + when : "(B_BIST_WEN & B_BIST_MEN)" + sdf_cond : "B_BIST_RW_ACCESS" + + rise_constraint("SIG2SRAM_constraint_template") { + index_1("0.0040,0.0176,0.0344,0.0656,0.1120,0.2016,0.3800"); + index_2("0.0040,0.0176,0.0344,0.0656,0.1120,0.2016,0.3800"); + values ("-0.2116,-0.2009,-0.1853,-0.1599,-0.1189,-0.0456,0.0891",\ +"-0.2155,-0.2048,-0.1891,-0.1638,-0.1227,-0.0495,0.0853",\ +"-0.2192,-0.2085,-0.1928,-0.1674,-0.1264,-0.0532,0.0816",\ +"-0.2224,-0.2116,-0.1960,-0.1706,-0.1296,-0.0564,0.0784",\ +"-0.2350,-0.2243,-0.2086,-0.1833,-0.1422,-0.0690,0.0658",\ +"-0.2526,-0.2419,-0.2263,-0.2009,-0.1598,-0.0866,0.0482",\ +"-0.2801,-0.2694,-0.2538,-0.2284,-0.1874,-0.1141,0.0207"); + } + + fall_constraint("SIG2SRAM_constraint_template") { + index_1("0.0040,0.0176,0.0344,0.0656,0.1120,0.2016,0.3800"); + index_2("0.0040,0.0176,0.0344,0.0656,0.1120,0.2016,0.3800"); + values ("-0.1882,-0.1765,-0.1638,-0.1364,-0.0993,-0.0261,0.1018",\ +"-0.1921,-0.1804,-0.1677,-0.1403,-0.1032,-0.0300,0.0980",\ +"-0.1958,-0.1840,-0.1713,-0.1440,-0.1069,-0.0337,0.0943",\ +"-0.1990,-0.1872,-0.1745,-0.1472,-0.1101,-0.0368,0.0911",\ +"-0.2116,-0.1999,-0.1872,-0.1598,-0.1227,-0.0495,0.0785",\ +"-0.2292,-0.2175,-0.2048,-0.1774,-0.1403,-0.0671,0.0609",\ +"-0.2567,-0.2450,-0.2323,-0.2049,-0.1678,-0.0946,0.0333"); + } + } + + + timing() { + timing_type : hold_rising; + related_pin : "B_BIST_CLK"; + when : "(B_BIST_WEN & B_BIST_MEN)" + sdf_cond : "B_BIST_RW_ACCESS" + + rise_constraint("SIG2SRAM_constraint_template") { + index_1("0.0040,0.0176,0.0344,0.0656,0.1120,0.2016,0.3800"); + index_2("0.0040,0.0176,0.0344,0.0656,0.1120,0.2016,0.3800"); + values ("0.3170,0.3072,0.2916,0.2652,0.2281,0.1539,0.0192",\ +"0.3209,0.3111,0.2955,0.2691,0.2320,0.1578,0.0230",\ +"0.3246,0.3148,0.2992,0.2728,0.2357,0.1615,0.0267",\ +"0.3278,0.3180,0.3024,0.2760,0.2389,0.1647,0.0299",\ +"0.3404,0.3306,0.3150,0.2886,0.2515,0.1773,0.0425",\ +"0.3580,0.3482,0.3326,0.3062,0.2691,0.1949,0.0601",\ +"0.3855,0.3757,0.3601,0.3337,0.2966,0.2224,0.0877"); + } + + fall_constraint("SIG2SRAM_constraint_template") { + index_1("0.0040,0.0176,0.0344,0.0656,0.1120,0.2016,0.3800"); + index_2("0.0040,0.0176,0.0344,0.0656,0.1120,0.2016,0.3800"); + values ("0.2887,0.2779,0.2643,0.2369,0.2008,0.1285,-0.0013",\ +"0.2926,0.2818,0.2682,0.2408,0.2047,0.1324,0.0025",\ +"0.2962,0.2855,0.2718,0.2445,0.2084,0.1361,0.0062",\ +"0.2994,0.2887,0.2750,0.2477,0.2116,0.1393,0.0094",\ +"0.3121,0.3013,0.2877,0.2603,0.2242,0.1519,0.0220",\ +"0.3297,0.3189,0.3053,0.2779,0.2418,0.1695,0.0396",\ +"0.3572,0.3464,0.3328,0.3054,0.2693,0.1970,0.0671"); + } + } +} + pin(B_BIST_CLK) { + direction : input; + capacitance : 0.00389386; + max_transition : "0.38"; + clock : "true" ; + pin_func_type : active_rising ; + + timing () { + timing_type : "min_pulse_width"; + related_pin : "B_BIST_CLK"; + rise_constraint("CLKTRAN_constraint_template") { + index_1("0.004,0.38"); + values("0.12,0.12"); + } + } + + related_power_pin : VDD; + related_ground_pin : VSS; + + internal_power() { + when : "!B_BIST_MEN & !B_BIST_WEN & !B_BIST_REN"; + rise_power("scalar"){ + values (0); + } + fall_power("scalar"){ + values (0); + } + } + internal_power() { + when : "!B_BIST_MEN & B_BIST_WEN & !B_BIST_REN"; + rise_power("scalar"){ + values (0.6406); + } + fall_power("scalar"){ + values (0); + } + } + internal_power() { + when : "B_BIST_MEN & B_BIST_WEN & !B_BIST_REN"; + rise_power("scalar"){ + values (22.6954); + } + fall_power("scalar"){ + values (0); + } + } + internal_power() { + when : "B_BIST_MEN & B_BIST_WEN & B_BIST_REN"; + rise_power("scalar"){ + values (24.9897); + } + fall_power("scalar"){ + values (0); + } + } + internal_power() { + when : "B_BIST_MEN & !B_BIST_WEN & B_BIST_REN"; + rise_power("scalar"){ + values (18.3238); + } + fall_power("scalar"){ + values (0); + } + } + internal_power() { + when : "!B_BIST_MEN & !B_BIST_WEN & B_BIST_REN"; + rise_power("scalar"){ + values (0.3904); + } + fall_power("scalar"){ + values (0); + } + } + internal_power() { + when : "!B_BIST_MEN & B_BIST_WEN & B_BIST_REN"; + rise_power("scalar"){ + values (0.8744); + } + fall_power("scalar"){ + values (0); + } + } + internal_power() { + when : "B_BIST_MEN & !B_BIST_WEN & !B_BIST_REN"; + rise_power("scalar"){ + values (0); + } + fall_power("scalar"){ + values (0); + } + } + } + bus(B_BIST_DIN) { + bus_type : D_15_0; + direction : input ; + capacitance : 0.00417898 ; + memory_write() { + address : B_BIST_ADDR ; + clocked_on : B_BIST_CLK; + } + + max_transition : "0.38" ; + pin(B_BIST_DIN[15:0]) { + related_power_pin : VDD; + related_ground_pin : VSS; + internal_power() { + when : "B_BIST_MEN"; + rise_power("scalar"){ + values (0.0914); + } + fall_power("scalar"){ + values (0.0775); + } + } + internal_power() { + when : "!B_BIST_MEN"; + rise_power("scalar"){ + values (0.0871); + } + fall_power("scalar"){ + values (0.0796); + } + } + } + timing() { + timing_type : setup_rising; + related_pin : "B_BIST_CLK"; + when : "(B_BIST_WEN & B_BIST_MEN)"; + sdf_cond : "B_BIST_W_ACCESS"; + + rise_constraint("SIG2SRAM_constraint_template") { + index_1("0.0040,0.0176,0.0344,0.0656,0.1120,0.2016,0.3800"); + index_2("0.0040,0.0176,0.0344,0.0656,0.1120,0.2016,0.3800"); + values ("-0.2116,-0.2009,-0.1853,-0.1599,-0.1189,-0.0456,0.0891",\ +"-0.2155,-0.2048,-0.1891,-0.1638,-0.1227,-0.0495,0.0853",\ +"-0.2192,-0.2085,-0.1928,-0.1674,-0.1264,-0.0532,0.0816",\ +"-0.2224,-0.2116,-0.1960,-0.1706,-0.1296,-0.0564,0.0784",\ +"-0.2350,-0.2243,-0.2086,-0.1833,-0.1422,-0.0690,0.0658",\ +"-0.2526,-0.2419,-0.2263,-0.2009,-0.1598,-0.0866,0.0482",\ +"-0.2801,-0.2694,-0.2538,-0.2284,-0.1874,-0.1141,0.0207"); + } + + fall_constraint("SIG2SRAM_constraint_template") { + index_1("0.0040,0.0176,0.0344,0.0656,0.1120,0.2016,0.3800"); + index_2("0.0040,0.0176,0.0344,0.0656,0.1120,0.2016,0.3800"); + values ("-0.1882,-0.1765,-0.1638,-0.1364,-0.0993,-0.0261,0.1018",\ +"-0.1921,-0.1804,-0.1677,-0.1403,-0.1032,-0.0300,0.0980",\ +"-0.1958,-0.1840,-0.1713,-0.1440,-0.1069,-0.0337,0.0943",\ +"-0.1990,-0.1872,-0.1745,-0.1472,-0.1101,-0.0368,0.0911",\ +"-0.2116,-0.1999,-0.1872,-0.1598,-0.1227,-0.0495,0.0785",\ +"-0.2292,-0.2175,-0.2048,-0.1774,-0.1403,-0.0671,0.0609",\ +"-0.2567,-0.2450,-0.2323,-0.2049,-0.1678,-0.0946,0.0333"); + } + } + + timing() { + timing_type : hold_rising; + related_pin : "B_BIST_CLK"; + when : "(B_BIST_WEN & B_BIST_MEN)"; + sdf_cond : "B_BIST_W_ACCESS"; + + rise_constraint("SIG2SRAM_constraint_template") { + index_1("0.0040,0.0176,0.0344,0.0656,0.1120,0.2016,0.3800"); + index_2("0.0040,0.0176,0.0344,0.0656,0.1120,0.2016,0.3800"); + values ("0.3170,0.3072,0.2916,0.2652,0.2281,0.1539,0.0192",\ +"0.3209,0.3111,0.2955,0.2691,0.2320,0.1578,0.0230",\ +"0.3246,0.3148,0.2992,0.2728,0.2357,0.1615,0.0267",\ +"0.3278,0.3180,0.3024,0.2760,0.2389,0.1647,0.0299",\ +"0.3404,0.3306,0.3150,0.2886,0.2515,0.1773,0.0425",\ +"0.3580,0.3482,0.3326,0.3062,0.2691,0.1949,0.0601",\ +"0.3855,0.3757,0.3601,0.3337,0.2966,0.2224,0.0877"); + } + + fall_constraint("SIG2SRAM_constraint_template") { + index_1("0.0040,0.0176,0.0344,0.0656,0.1120,0.2016,0.3800"); + index_2("0.0040,0.0176,0.0344,0.0656,0.1120,0.2016,0.3800"); + values ("0.2887,0.2779,0.2643,0.2369,0.2008,0.1285,-0.0013",\ +"0.2926,0.2818,0.2682,0.2408,0.2047,0.1324,0.0025",\ +"0.2962,0.2855,0.2718,0.2445,0.2084,0.1361,0.0062",\ +"0.2994,0.2887,0.2750,0.2477,0.2116,0.1393,0.0094",\ +"0.3121,0.3013,0.2877,0.2603,0.2242,0.1519,0.0220",\ +"0.3297,0.3189,0.3053,0.2779,0.2418,0.1695,0.0396",\ +"0.3572,0.3464,0.3328,0.3054,0.2693,0.1970,0.0671"); + } + } + } + +bus(B_DOUT) { + + bus_type : D_15_0; + direction : output ; + capacitance : 0 ; + max_capacitance : 0.064 ; + memory_read() { + address : B_ADDR ; + } + pin(B_DOUT[15:0]) { + related_power_pin : VDD; + related_ground_pin : VSS; + internal_power() { + rise_power("scalar") { + values (0); + } + fall_power("scalar") { + values (0); + } + } + } + timing() { + related_pin : "B_CLK"; + timing_type : rising_edge ; + timing_sense : non_unate ; + + cell_rise(SIG2SRAM_delay_template) { + index_1("0.0040,0.0176,0.0344,0.0656,0.1120,0.2016,0.3800"); + index_2("0.0008,0.0014,0.0051,0.0100,0.0339,0.0640"); + values ("1.8529,1.8539,1.8587,1.8642,1.8851,1.9086",\ +"1.8588,1.8598,1.8646,1.8701,1.8911,1.9146",\ +"1.8616,1.8626,1.8674,1.8729,1.8938,1.9173",\ +"1.8658,1.8668,1.8716,1.8771,1.8980,1.9215",\ +"1.8774,1.8784,1.8832,1.8887,1.9096,1.9331",\ +"1.8965,1.8975,1.9023,1.9078,1.9287,1.9522",\ +"1.9229,1.9239,1.9287,1.9342,1.9551,1.9786"); + } + cell_fall(SIG2SRAM_delay_template) { + index_1("0.0040,0.0176,0.0344,0.0656,0.1120,0.2016,0.3800"); + index_2("0.0008,0.0014,0.0051,0.0100,0.0339,0.0640"); + values ("1.8186,1.8194,1.8235,1.8280,1.8451,1.8618",\ +"1.8245,1.8254,1.8294,1.8340,1.8510,1.8678",\ +"1.8273,1.8281,1.8322,1.8367,1.8538,1.8705",\ +"1.8315,1.8323,1.8364,1.8409,1.8580,1.8747",\ +"1.8431,1.8439,1.8480,1.8525,1.8696,1.8863",\ +"1.8622,1.8631,1.8671,1.8716,1.8887,1.9055",\ +"1.8886,1.8894,1.8935,1.8980,1.9151,1.9318"); + } + + rise_transition(SRAM_load_template) { + index_1("0.0008,0.0014,0.0051,0.0100,0.0339,0.0640"); + values ("0.0206,0.0210,0.0265,0.0323,0.0606,0.0955"); + } + fall_transition(SRAM_load_template) { + index_1("0.0008,0.0014,0.0051,0.0100,0.0339,0.0640"); + values ("0.0170,0.0177,0.0222,0.0270,0.0451,0.0644"); + } + } +} +cell_leakage_power : 225.8534; +} +} diff --git a/flow/platforms/ihp-sg13g2/lib/RM_IHPSG13_2P_256x16_c2_bm_bist_slow_1p08V_125C.lib b/flow/platforms/ihp-sg13g2/lib/RM_IHPSG13_2P_256x16_c2_bm_bist_slow_1p08V_125C.lib new file mode 100644 index 0000000000..90bc7fe9bf --- /dev/null +++ b/flow/platforms/ihp-sg13g2/lib/RM_IHPSG13_2P_256x16_c2_bm_bist_slow_1p08V_125C.lib @@ -0,0 +1,2874 @@ +/* ------------------------------------------------------*/ +/**/ +/* Copyright 2025 IHP PDK Authors*/ +/**/ +/* Licensed under the Apache License, Version 2.0 (the "License");*/ +/* you may not use this file except in compliance with the License.*/ +/* You may obtain a copy of the License at*/ +/* */ +/* https://www.apache.org/licenses/LICENSE-2.0*/ +/* */ +/* Unless required by applicable law or agreed to in writing, software*/ +/* distributed under the License is distributed on an "AS IS" BASIS,*/ +/* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.*/ +/* See the License for the specific language governing permissions and*/ +/* limitations under the License.*/ +/* */ +/* Generated on Wed Aug 27 13:19:40 2025 */ +/* */ +/* ------------------------------------------------------ */ +library(RM_IHPSG13_2P_256x16_c2_bm_bist_slow_1p08V_125C) { + technology (cmos) ; + delay_model : table_lookup ; + define ("add_pg_pin_to_lib", "library", "boolean"); + add_pg_pin_to_lib : true; + voltage_map ( VDD, 1.08); + voltage_map ( VDDARRAY, 1.08); + voltage_map ( VSS, 0.000000 ); + + date : "Wed Aug 27 13:19:39 2025" ; + comment : "IHP Microelectronics GmbH, 2023" ; + revision : 1.0.0 ; + simulation : true ; + nom_process : 1 ; + nom_temperature : 125 ; + nom_voltage : 1.08 ; + + operating_conditions("slow_1p08V_125C"){ + process : 1 ; + temperature : 125 ; + voltage : 1.08 ; + tree_type : "balanced_tree" ; + } + + default_operating_conditions : slow_1p08V_125C ; + default_max_transition : 1.0 ; + default_fanout_load : 1.0 ; + default_inout_pin_cap : 0.0 ; + default_input_pin_cap : 0.0 ; + default_output_pin_cap : 0.0 ; + default_cell_leakage_power : 0.0 ; + default_leakage_power_density : 0.0 ; + + slew_lower_threshold_pct_rise : 30 ; + slew_upper_threshold_pct_rise : 70 ; + input_threshold_pct_fall : 50 ; + output_threshold_pct_fall : 50 ; + input_threshold_pct_rise : 50 ; + output_threshold_pct_rise : 50 ; + slew_lower_threshold_pct_fall : 30 ; + slew_upper_threshold_pct_fall : 70 ; + slew_derate_from_library : 0.5; + k_volt_cell_leakage_power : 0.0 ; + k_temp_cell_leakage_power : 0.0 ; + k_process_cell_leakage_power : 0.0 ; + k_volt_internal_power : 0.0 ; + k_temp_internal_power : 0.0 ; + k_process_internal_power : 0.0 ; + + capacitive_load_unit (1,pf) ; + voltage_unit : "1V" ; + current_unit : "1uA" ; + time_unit : "1ns" ; + leakage_power_unit : "1nW" ; + pulling_resistance_unit : "1kohm"; + /* + ------------------------------------------------------------------------------------------ + implicit units overview: + cell_area unit : "um" + internal_power unit : "1e-12 * J/toggle = 1 * uW/MHz" + (capacitive_load_unit * voltage_unit^2) per toggle event + ------------------------------------------------------------------------------------------ + */ + library_features(report_delay_calculation); + define_cell_area (pad_drivers,pad_driver_sites) ; + + lu_table_template(CLKTRAN_constraint_template) { + variable_1 : constrained_pin_transition; + index_1 ( "0.010, 0.050, 0.200, 0.400, 1.000" ); + } + lu_table_template(SRAM_load_template) { + variable_1 : total_output_net_capacitance; + index_1 ( "0.0008,0.0014,0.0051,0.0100,0.0339,0.0640" ); + } + lu_table_template(SIG2SRAM_constraint_template) { + variable_1 : related_pin_transition; + variable_2 : constrained_pin_transition; + index_1 ( "0.0080,0.0288,0.0616,0.1072,0.1920,0.3496,0.5952" ); + index_2 ( "0.0080,0.0288,0.0616,0.1072,0.1920,0.3496,0.5952" ); + } + + lu_table_template(SIG2SRAM_delay_template) { + variable_1 : input_net_transition; + variable_2 : total_output_net_capacitance; + index_1 ( "0.0080,0.0288,0.0616,0.1072,0.1920,0.3496,0.5952" ); + index_2 ( "0.0008,0.0014,0.0051,0.0100,0.0339,0.0640" ); + } + + type (D_15_0) { + base_type : array; + data_type : bit; + bit_width : 16; + bit_from : 15; + bit_to : 0; + downto : true; + } + + type (A_7_0) { + base_type : array; + data_type : bit; + bit_width : 8; + bit_from : 7; + bit_to : 0; + downto : true; + } + +cell(RM_IHPSG13_2P_256x16_c2_bm_bist) { +pg_pin (VDD) { + pg_type : primary_power; + voltage_name : VDD; +} +pg_pin (VDDARRAY) { + pg_type : primary_power; + voltage_name : VDDARRAY; +} +pg_pin (VSS) { + pg_type : primary_ground; + voltage_name : VSS; +} + +memory() { + type : ram; + address_width : 8; + word_width : 16; +} + +interface_timing : false; +bus_naming_style : "%s[%d]" ; +area : 57520.5515 ; + + pin(A_DLY) { + direction : input ; + capacitance : 0.00387999 ; + max_transition : "1" ; + related_power_pin : VDD; + related_ground_pin : VSS; + internal_power() { + rise_power("scalar") { + values (0); + } + fall_power("scalar") { + values (0); + } + } + } + +bus(A_ADDR) { + bus_type : A_7_0; + direction : input ; + capacitance : 0.0129586 ; + pin(A_ADDR[0]) { + capacitance : 0.0058687 ; + } + pin(A_ADDR[1]) { + capacitance : 0.00807137 ; + } + pin(A_ADDR[2]) { + capacitance : 0.0112051 ; + } + pin(A_ADDR[3]) { + capacitance : 0.00709524 ; + } + pin(A_ADDR[4]) { + capacitance : 0.00648778 ; + } + pin(A_ADDR[5]) { + capacitance : 0.011209 ; + } + pin(A_ADDR[6]) { + capacitance : 0.0140441 ; + } + max_transition : "0.5952" ; + pin(A_ADDR[7:0]) { + related_power_pin : VDD; + related_ground_pin : VSS; + internal_power() { + when : "A_MEN"; + rise_power("scalar"){ + values (0.0102); + } + fall_power("scalar"){ + values (0.0077); + } + } + internal_power() { + when : "!A_MEN"; + rise_power("scalar"){ + values (0.0150); + } + fall_power("scalar"){ + values (0.0029); + } + } + } + timing() { + timing_type : setup_rising; + related_pin : "A_CLK"; + when : "((A_WEN | A_REN)& A_MEN)" + sdf_cond : "A_RW_ACCESS" + + rise_constraint("SIG2SRAM_constraint_template") { + index_1("0.0080,0.0288,0.0616,0.1072,0.1920,0.3496,0.5952"); + index_2("0.0080,0.0288,0.0616,0.1072,0.1920,0.3496,0.5952"); + values ("-0.7371,-0.7176,-0.6863,-0.6434,-0.5652,-0.4168,-0.1980",\ +"-0.7566,-0.7371,-0.7059,-0.6629,-0.5848,-0.4363,-0.2137",\ +"-0.7879,-0.7645,-0.7332,-0.6902,-0.6121,-0.4637,-0.2449",\ +"-0.8309,-0.8074,-0.7762,-0.7332,-0.6551,-0.5066,-0.2879",\ +"-0.9051,-0.8895,-0.8543,-0.8113,-0.7332,-0.5887,-0.3660",\ +"-1.0418,-1.0262,-0.9949,-0.9480,-0.8699,-0.7293,-0.5027",\ +"-1.2684,-1.2449,-1.2176,-1.1707,-1.0965,-0.9480,-0.7293"); + } + + fall_constraint("SIG2SRAM_constraint_template") { + index_1("0.0080,0.0288,0.0616,0.1072,0.1920,0.3496,0.5952"); + index_2("0.0080,0.0288,0.0616,0.1072,0.1920,0.3496,0.5952"); + values ("-0.5926,-0.5730,-0.5418,-0.4988,-0.4246,-0.2879,-0.0730",\ +"-0.6121,-0.5926,-0.5613,-0.5223,-0.4441,-0.3074,-0.0887",\ +"-0.6395,-0.6199,-0.5926,-0.5496,-0.4715,-0.3348,-0.1160",\ +"-0.6863,-0.6668,-0.6355,-0.5965,-0.5184,-0.3777,-0.1590",\ +"-0.7605,-0.7410,-0.7137,-0.6746,-0.5926,-0.4559,-0.2410",\ +"-0.9012,-0.8816,-0.8504,-0.8113,-0.7332,-0.5926,-0.3895",\ +"-1.1238,-1.1043,-1.0769,-1.0379,-0.9559,-0.8191,-0.6004"); + } + } + + + timing() { + timing_type : hold_rising; + related_pin : "A_CLK"; + when : "((A_WEN | A_REN)& A_MEN)" + sdf_cond : "A_RW_ACCESS" + + rise_constraint("SIG2SRAM_constraint_template") { + index_1("0.0080,0.0288,0.0616,0.1072,0.1920,0.3496,0.5952"); + index_2("0.0080,0.0288,0.0616,0.1072,0.1920,0.3496,0.5952"); + values ("0.8488,0.8293,0.7980,0.7551,0.6730,0.5285,0.3059",\ +"0.8684,0.8488,0.8176,0.7746,0.6926,0.5480,0.3254",\ +"0.8996,0.8801,0.8449,0.8020,0.7238,0.5754,0.3527",\ +"0.9426,0.9191,0.8918,0.8488,0.7668,0.6223,0.3996",\ +"1.0168,1.0012,0.9699,0.9230,0.8449,0.7004,0.4777",\ +"1.1574,1.1379,1.1105,1.0598,0.9816,0.8371,0.6184",\ +"1.3801,1.3605,1.3254,1.2980,1.2043,1.0637,0.8371"); + } + + fall_constraint("SIG2SRAM_constraint_template") { + index_1("0.0080,0.0288,0.0616,0.1072,0.1920,0.3496,0.5952"); + index_2("0.0080,0.0288,0.0616,0.1072,0.1920,0.3496,0.5952"); + values ("0.6965,0.6770,0.6496,0.6066,0.5246,0.3918,0.1730",\ +"0.7160,0.6965,0.6652,0.6262,0.5441,0.4113,0.1965",\ +"0.7473,0.7277,0.6965,0.6535,0.5754,0.4426,0.2238",\ +"0.7863,0.7707,0.7395,0.7004,0.6223,0.4855,0.2629",\ +"0.8684,0.8449,0.8176,0.7785,0.7004,0.5637,0.3449",\ +"1.0051,0.9855,0.9855,0.9113,0.8332,0.7004,0.4895",\ +"1.2277,1.2082,1.1809,1.1379,1.0598,0.9230,0.7004"); + } + } +} +pin(A_WEN) { + direction : input ; + capacitance : 0.00313551 ; + max_transition : "0.5952" ; + related_power_pin : VDD; + related_ground_pin : VSS; + internal_power() { + when : "A_MEN"; + rise_power("scalar"){ + values (0.0036); + } + fall_power("scalar"){ + values (0.0007); + } + } + internal_power() { + when : "!A_MEN"; + rise_power("scalar"){ + values (0.0050); + } + fall_power("scalar"){ + values (0.0002); + } + } + timing() { + timing_type : setup_rising; + related_pin : "A_CLK"; + when : "A_MEN" + sdf_cond : "A_MEN" + + rise_constraint("SIG2SRAM_constraint_template") { + index_1("0.0080,0.0288,0.0616,0.1072,0.1920,0.3496,0.5952"); + index_2("0.0080,0.0288,0.0616,0.1072,0.1920,0.3496,0.5952"); + values ("0.3137,0.3332,0.3605,0.4035,0.4816,0.6223,0.8488",\ +"0.2980,0.3176,0.3410,0.3840,0.4660,0.6027,0.8293",\ +"0.2629,0.2824,0.3098,0.3527,0.4348,0.5754,0.7980",\ +"0.2199,0.2395,0.2668,0.3098,0.3918,0.5324,0.7590",\ +"0.1418,0.1613,0.1887,0.2316,0.3137,0.4348,0.6730",\ +"0.0012,0.0207,0.0520,0.0910,0.1730,0.3098,0.5285",\ +"-0.2215,-0.2020,-0.1746,-0.1277,-0.0496,0.0910,0.3098"); + } + + fall_constraint("SIG2SRAM_constraint_template") { + index_1("0.0080,0.0288,0.0616,0.1072,0.1920,0.3496,0.5952"); + index_2("0.0080,0.0288,0.0616,0.1072,0.1920,0.3496,0.5952"); + values ("0.4504,0.4699,0.4973,0.5324,0.6027,0.7355,0.9699",\ +"0.4309,0.4504,0.4777,0.5129,0.5910,0.7160,0.9504",\ +"0.3996,0.4191,0.4465,0.4816,0.5520,0.6848,0.9191",\ +"0.3605,0.3762,0.4035,0.4387,0.5168,0.6418,0.8723",\ +"0.2785,0.2980,0.3215,0.3605,0.4348,0.5637,0.7980",\ +"0.1379,0.1574,0.1809,0.2199,0.2980,0.4309,0.6457",\ +"-0.0809,-0.0613,-0.0340,0.0051,0.0832,0.2160,0.4191"); + } + } + + + timing() { + timing_type : hold_rising; + related_pin : "A_CLK"; + when : "A_MEN" + sdf_cond : "A_MEN" + + rise_constraint("SIG2SRAM_constraint_template") { + index_1("0.0080,0.0288,0.0616,0.1072,0.1920,0.3496,0.5952"); + index_2("0.0080,0.0288,0.0616,0.1072,0.1920,0.3496,0.5952"); + values ("0.3723,0.3527,0.3215,0.2785,0.1965,0.0559,-0.1668",\ +"0.3918,0.3723,0.3449,0.2980,0.2160,0.0754,-0.1473",\ +"0.4152,0.3996,0.3684,0.3254,0.2434,0.1066,-0.1199",\ +"0.4621,0.4465,0.4152,0.3723,0.2863,0.1496,-0.0730",\ +"0.5324,0.5207,0.4895,0.4465,0.3645,0.2199,0.0051",\ +"0.6770,0.6535,0.6301,0.5832,0.5090,0.3605,0.1418",\ +"0.9035,0.8879,0.8566,0.8137,0.7316,0.5871,0.3684"); + } + + fall_constraint("SIG2SRAM_constraint_template") { + index_1("0.0080,0.0288,0.0616,0.1072,0.1920,0.3496,0.5952"); + index_2("0.0080,0.0288,0.0616,0.1072,0.1920,0.3496,0.5952"); + values ("0.3762,0.3566,0.3293,0.2863,0.2043,0.0676,-0.1434",\ +"0.3957,0.3762,0.3488,0.3059,0.2238,0.0871,-0.1199",\ +"0.4230,0.4035,0.3723,0.3332,0.2512,0.1184,-0.0965",\ +"0.4660,0.4465,0.4191,0.3762,0.2941,0.1613,-0.0496",\ +"0.5324,0.5168,0.4973,0.4543,0.3723,0.2316,0.0285",\ +"0.6809,0.6613,0.6340,0.5910,0.5129,0.3645,0.1652",\ +"0.9113,0.8918,0.8605,0.8176,0.7395,0.5988,0.3879"); + } + } + } +pin(A_REN) { + direction : input ; + capacitance : 0.00381144 ; + max_transition : "0.5952" ; + related_power_pin : VDD; + related_ground_pin : VSS; + internal_power() { + when : "A_MEN"; + rise_power("scalar"){ + values (0.0040); + } + fall_power("scalar"){ + values (0.0015); + } + } + internal_power() { + when : "!A_MEN"; + rise_power("scalar"){ + values (0.0040); + } + fall_power("scalar"){ + values (0.0013); + } + } + timing() { + timing_type : setup_rising; + related_pin : "A_CLK"; + when : "A_MEN" + sdf_cond : "A_MEN" + + rise_constraint("SIG2SRAM_constraint_template") { + index_1("0.0080,0.0288,0.0616,0.1072,0.1920,0.3496,0.5952"); + index_2("0.0080,0.0288,0.0616,0.1072,0.1920,0.3496,0.5952"); + values ("-0.0770,-0.0574,-0.0262,0.0168,0.0949,0.2355,0.4582",\ +"-0.0965,-0.0770,-0.0457,-0.0027,0.0754,0.2160,0.4387",\ +"-0.1199,-0.1004,-0.0730,-0.0262,0.0520,0.1887,0.4113",\ +"-0.1590,-0.1434,-0.1160,-0.0730,0.0051,0.1457,0.3645",\ +"-0.2449,-0.2254,-0.1941,-0.1473,-0.0770,0.0676,0.2863",\ +"-0.3816,-0.3699,-0.3387,-0.2801,-0.2215,-0.0770,0.1457",\ +"-0.6121,-0.5926,-0.5613,-0.5145,-0.4363,-0.2996,-0.0730"); + } + + fall_constraint("SIG2SRAM_constraint_template") { + index_1("0.0080,0.0288,0.0616,0.1072,0.1920,0.3496,0.5952"); + index_2("0.0080,0.0288,0.0616,0.1072,0.1920,0.3496,0.5952"); + values ("0.1262,0.1457,0.1691,0.2121,0.2824,0.4191,0.6457",\ +"0.1105,0.1262,0.1496,0.1887,0.2629,0.3996,0.6262",\ +"0.0793,0.0949,0.1223,0.1652,0.2395,0.3684,0.5949",\ +"0.0363,0.0559,0.0793,0.1223,0.2004,0.3410,0.5520",\ +"-0.0457,-0.0262,0.0012,0.0441,0.1301,0.2629,0.4738",\ +"-0.1902,-0.1746,-0.1434,-0.1043,-0.0184,0.1223,0.3332",\ +"-0.4129,-0.3934,-0.3660,-0.3230,-0.2449,-0.1043,0.1105"); + } + } + + + timing() { + timing_type : hold_rising; + related_pin : "A_CLK"; + when : "A_MEN" + sdf_cond : "A_MEN" + + rise_constraint("SIG2SRAM_constraint_template") { + index_1("0.0080,0.0288,0.0616,0.1072,0.1920,0.3496,0.5952"); + index_2("0.0080,0.0288,0.0616,0.1072,0.1920,0.3496,0.5952"); + values ("0.4113,0.3918,0.3645,0.3176,0.2395,0.0988,-0.1238",\ +"0.4309,0.4113,0.3840,0.3371,0.2590,0.1184,-0.1043",\ +"0.4582,0.4387,0.4113,0.3645,0.2824,0.1457,-0.0770",\ +"0.5051,0.4816,0.4543,0.4074,0.3293,0.1887,-0.0340",\ +"0.5715,0.5598,0.5324,0.4895,0.4035,0.2512,0.0441",\ +"0.7043,0.7004,0.6730,0.6262,0.5402,0.3957,0.1809",\ +"0.9387,0.9270,0.8957,0.8527,0.7746,0.6262,0.4074"); + } + + fall_constraint("SIG2SRAM_constraint_template") { + index_1("0.0080,0.0288,0.0616,0.1072,0.1920,0.3496,0.5952"); + index_2("0.0080,0.0288,0.0616,0.1072,0.1920,0.3496,0.5952"); + values ("0.4152,0.3918,0.3645,0.3215,0.2395,0.1027,-0.1082",\ +"0.4309,0.4113,0.3801,0.3410,0.2590,0.1223,-0.0926",\ +"0.4582,0.4387,0.4074,0.3684,0.2863,0.1496,-0.0613",\ +"0.5012,0.4816,0.4504,0.4074,0.3293,0.1887,-0.0145",\ +"0.5715,0.5559,0.5285,0.4816,0.3996,0.2512,0.0598",\ +"0.7160,0.7004,0.6691,0.6262,0.5520,0.4035,0.2004",\ +"0.9387,0.9191,0.8957,0.8488,0.7707,0.6262,0.4113"); + } + } + } +pin(A_MEN) { + direction : input ; + capacitance : 0.00300347 ; + max_transition : "0.5952" ; + related_power_pin : VDD; + related_ground_pin : VSS; + internal_power() { + rise_power("scalar"){ + values (0.0161); + } + fall_power("scalar"){ + values (0.0002); + } + } + timing() { + timing_type : setup_rising; + related_pin : "A_CLK"; + + rise_constraint("SIG2SRAM_constraint_template") { + index_1("0.0080,0.0288,0.0616,0.1072,0.1920,0.3496,0.5952"); + index_2("0.0080,0.0288,0.0616,0.1072,0.1920,0.3496,0.5952"); + values ("0.3215,0.3449,0.3684,0.4113,0.4895,0.6301,0.8527",\ +"0.3059,0.3254,0.3527,0.3957,0.4738,0.6145,0.8371",\ +"0.2746,0.2941,0.3215,0.3645,0.4426,0.5871,0.8059",\ +"0.2316,0.2512,0.2785,0.3215,0.3996,0.5402,0.7629",\ +"0.1496,0.1730,0.1965,0.2395,0.3215,0.4660,0.6848",\ +"0.0090,0.0285,0.0598,0.1027,0.1809,0.3176,0.5402",\ +"-0.2098,-0.1902,-0.1668,-0.1199,-0.0418,0.0988,0.3137"); + } + + fall_constraint("SIG2SRAM_constraint_template") { + index_1("0.0080,0.0288,0.0616,0.1072,0.1920,0.3496,0.5952"); + index_2("0.0080,0.0288,0.0616,0.1072,0.1920,0.3496,0.5952"); + values ("0.4582,0.4738,0.5012,0.5363,0.6145,0.7395,0.9738",\ +"0.4387,0.4543,0.4816,0.5207,0.5910,0.7199,0.9582",\ +"0.4035,0.4230,0.4504,0.4855,0.5637,0.6887,0.9230",\ +"0.3645,0.3840,0.4074,0.4465,0.5285,0.6496,0.8840",\ +"0.2824,0.3020,0.3254,0.3645,0.4465,0.5715,0.7980",\ +"0.1418,0.1613,0.1887,0.2238,0.3020,0.4309,0.6496",\ +"-0.0770,-0.0574,-0.0301,0.0090,0.0910,0.2238,0.4191"); + } + } + + + timing() { + timing_type : hold_rising; + related_pin : "A_CLK"; + + rise_constraint("SIG2SRAM_constraint_template") { + index_1("0.0080,0.0288,0.0616,0.1072,0.1920,0.3496,0.5952"); + index_2("0.0080,0.0288,0.0616,0.1072,0.1920,0.3496,0.5952"); + values ("0.3762,0.3605,0.3293,0.2863,0.2043,0.0637,-0.1629",\ +"0.3996,0.3801,0.3488,0.3020,0.2238,0.0832,-0.1395",\ +"0.4230,0.4074,0.3723,0.3293,0.2473,0.1105,-0.1121",\ +"0.4621,0.4465,0.4152,0.3762,0.2941,0.1535,-0.0691",\ +"0.5441,0.5285,0.4973,0.4465,0.3684,0.2316,0.0090",\ +"0.6848,0.6652,0.6301,0.5910,0.5129,0.3605,0.1496",\ +"0.9074,0.8918,0.8566,0.8215,0.7395,0.5910,0.3723"); + } + + fall_constraint("SIG2SRAM_constraint_template") { + index_1("0.0080,0.0288,0.0616,0.1072,0.1920,0.3496,0.5952"); + index_2("0.0080,0.0288,0.0616,0.1072,0.1920,0.3496,0.5952"); + values ("0.3762,0.3605,0.3332,0.2863,0.2043,0.0715,-0.1395",\ +"0.3996,0.3762,0.3488,0.3059,0.2238,0.0910,-0.1199",\ +"0.4270,0.4035,0.3762,0.3332,0.2512,0.1184,-0.0965",\ +"0.4699,0.4504,0.4191,0.3762,0.2941,0.1613,-0.0496",\ +"0.5441,0.5285,0.4973,0.4543,0.3762,0.2355,0.0324",\ +"0.6770,0.6613,0.6340,0.5949,0.5207,0.3762,0.1652",\ +"0.9074,0.8918,0.8605,0.8176,0.7395,0.6027,0.3918"); + } + } + } +bus(A_BM) { + bus_type : D_15_0; + direction : input ; + capacitance : 0.00359979 ; + max_transition : "0.5952" ; + pin(A_BM[15:0]) { + related_power_pin : VDD; + related_ground_pin : VSS; + internal_power() { + when : "A_MEN"; + rise_power("scalar"){ + values (0.0469); + } + fall_power("scalar"){ + values (0.0152); + } + } + internal_power() { + when : "!A_MEN"; + rise_power("scalar"){ + values (0.0453); + } + fall_power("scalar"){ + values (0.0145); + } + } + } + timing() { + timing_type : setup_rising; + related_pin : "A_CLK"; + when : "(A_WEN & A_MEN)" + sdf_cond : "A_RW_ACCESS" + + rise_constraint("SIG2SRAM_constraint_template") { + index_1("0.0080,0.0288,0.0616,0.1072,0.1920,0.3496,0.5952"); + index_2("0.0080,0.0288,0.0616,0.1072,0.1920,0.3496,0.5952"); + values ("-0.6982,-0.6787,-0.6533,-0.6103,-0.5293,-0.3838,-0.1611",\ +"-0.7062,-0.6866,-0.6612,-0.6183,-0.5372,-0.3917,-0.1690",\ +"-0.7153,-0.6958,-0.6704,-0.6274,-0.5464,-0.4008,-0.1782",\ +"-0.7303,-0.7107,-0.6853,-0.6424,-0.5613,-0.4158,-0.1932",\ +"-0.7527,-0.7331,-0.7077,-0.6648,-0.5837,-0.4382,-0.2155",\ +"-0.7962,-0.7767,-0.7513,-0.7084,-0.6273,-0.4818,-0.2591",\ +"-0.8654,-0.8459,-0.8205,-0.7775,-0.6965,-0.5510,-0.3283"); + } + + fall_constraint("SIG2SRAM_constraint_template") { + index_1("0.0080,0.0288,0.0616,0.1072,0.1920,0.3496,0.5952"); + index_2("0.0080,0.0288,0.0616,0.1072,0.1920,0.3496,0.5952"); + values ("-0.6357,-0.6181,-0.5908,-0.5518,-0.4687,-0.3330,-0.1211",\ +"-0.6436,-0.6261,-0.5987,-0.5597,-0.4767,-0.3409,-0.1290",\ +"-0.6528,-0.6352,-0.6079,-0.5688,-0.4858,-0.3501,-0.1381",\ +"-0.6678,-0.6502,-0.6228,-0.5838,-0.5008,-0.3650,-0.1531",\ +"-0.6901,-0.6726,-0.6452,-0.6062,-0.5232,-0.3874,-0.1755",\ +"-0.7338,-0.7162,-0.6888,-0.6498,-0.5668,-0.4310,-0.2191",\ +"-0.8029,-0.7854,-0.7580,-0.7189,-0.6359,-0.5002,-0.2883"); + } + } + + + timing() { + timing_type : hold_rising; + related_pin : "A_CLK"; + when : "(A_WEN & A_MEN)" + sdf_cond : "A_RW_ACCESS" + + rise_constraint("SIG2SRAM_constraint_template") { + index_1("0.0080,0.0288,0.0616,0.1072,0.1920,0.3496,0.5952"); + index_2("0.0080,0.0288,0.0616,0.1072,0.1920,0.3496,0.5952"); + values ("0.8138,0.7924,0.7679,0.7250,0.6449,0.4984,0.2758",\ +"0.8218,0.8003,0.7759,0.7329,0.6528,0.5063,0.2837",\ +"0.8309,0.8094,0.7850,0.7420,0.6620,0.5155,0.2928",\ +"0.8459,0.8244,0.8000,0.7570,0.6769,0.5304,0.3078",\ +"0.8683,0.8468,0.8224,0.7794,0.6993,0.5528,0.3302",\ +"0.9119,0.8904,0.8660,0.8230,0.7429,0.5964,0.3738",\ +"0.9810,0.9596,0.9351,0.8922,0.8121,0.6656,0.4430"); + } + + fall_constraint("SIG2SRAM_constraint_template") { + index_1("0.0080,0.0288,0.0616,0.1072,0.1920,0.3496,0.5952"); + index_2("0.0080,0.0288,0.0616,0.1072,0.1920,0.3496,0.5952"); + values ("0.7396,0.7220,0.6947,0.6556,0.5726,0.4359,0.2250",\ +"0.7475,0.7300,0.7026,0.6636,0.5806,0.4438,0.2329",\ +"0.7567,0.7391,0.7118,0.6727,0.5897,0.4530,0.2420",\ +"0.7717,0.7541,0.7267,0.6877,0.6047,0.4679,0.2570",\ +"0.7940,0.7765,0.7491,0.7101,0.6271,0.4903,0.2794",\ +"0.8376,0.8201,0.7927,0.7537,0.6706,0.5339,0.3230",\ +"0.9068,0.8892,0.8619,0.8228,0.7398,0.6031,0.3922"); + } + } +} + pin(A_CLK) { + direction : input; + capacitance : 0.00378957; + max_transition : "0.5952"; + clock : "true" ; + pin_func_type : active_rising ; + + timing () { + timing_type : "min_pulse_width"; + related_pin : "A_CLK"; + rise_constraint("CLKTRAN_constraint_template") { + index_1("0.008,0.5952"); + values("0.4,0.4"); + } + } + + related_power_pin : VDD; + related_ground_pin : VSS; + + internal_power() { + when : "!A_MEN & !A_WEN & !A_REN"; + rise_power("scalar"){ + values (0); + } + fall_power("scalar"){ + values (0); + } + } + internal_power() { + when : "!A_MEN & A_WEN & !A_REN"; + rise_power("scalar"){ + values (0.4498); + } + fall_power("scalar"){ + values (0); + } + } + internal_power() { + when : "A_MEN & A_WEN & !A_REN"; + rise_power("scalar"){ + values (15.3644); + } + fall_power("scalar"){ + values (0); + } + } + internal_power() { + when : "A_MEN & A_WEN & A_REN"; + rise_power("scalar"){ + values (16.3884); + } + fall_power("scalar"){ + values (0); + } + } + internal_power() { + when : "A_MEN & !A_WEN & A_REN"; + rise_power("scalar"){ + values (11.8557); + } + fall_power("scalar"){ + values (0); + } + } + internal_power() { + when : "!A_MEN & !A_WEN & A_REN"; + rise_power("scalar"){ + values (0.2837); + } + fall_power("scalar"){ + values (0); + } + } + internal_power() { + when : "!A_MEN & A_WEN & A_REN"; + rise_power("scalar"){ + values (0.6730); + } + fall_power("scalar"){ + values (0); + } + } + internal_power() { + when : "A_MEN & !A_WEN & !A_REN"; + rise_power("scalar"){ + values (0); + } + fall_power("scalar"){ + values (0); + } + } + } + bus(A_DIN) { + bus_type : D_15_0; + direction : input ; + capacitance : 0.00502163 ; + memory_write() { + address : A_ADDR ; + clocked_on : A_CLK; + } + + max_transition : "0.5952" ; + pin(A_DIN[15:0]) { + related_power_pin : VDD; + related_ground_pin : VSS; + internal_power() { + when : "A_MEN"; + rise_power("scalar"){ + values (0.0469); + } + fall_power("scalar"){ + values (0.0152); + } + } + internal_power() { + when : "!A_MEN"; + rise_power("scalar"){ + values (0.0453); + } + fall_power("scalar"){ + values (0.0145); + } + } + } + timing() { + timing_type : setup_rising; + related_pin : "A_CLK"; + when : "(A_WEN & A_MEN)"; + sdf_cond : "A_W_ACCESS"; + + rise_constraint("SIG2SRAM_constraint_template") { + index_1("0.0080,0.0288,0.0616,0.1072,0.1920,0.3496,0.5952"); + index_2("0.0080,0.0288,0.0616,0.1072,0.1920,0.3496,0.5952"); + values ("-0.6982,-0.6787,-0.6533,-0.6103,-0.5293,-0.3838,-0.1611",\ +"-0.7062,-0.6866,-0.6612,-0.6183,-0.5372,-0.3917,-0.1690",\ +"-0.7153,-0.6958,-0.6704,-0.6274,-0.5464,-0.4008,-0.1782",\ +"-0.7303,-0.7107,-0.6853,-0.6424,-0.5613,-0.4158,-0.1932",\ +"-0.7527,-0.7331,-0.7077,-0.6648,-0.5837,-0.4382,-0.2155",\ +"-0.7962,-0.7767,-0.7513,-0.7084,-0.6273,-0.4818,-0.2591",\ +"-0.8654,-0.8459,-0.8205,-0.7775,-0.6965,-0.5510,-0.3283"); + } + + fall_constraint("SIG2SRAM_constraint_template") { + index_1("0.0080,0.0288,0.0616,0.1072,0.1920,0.3496,0.5952"); + index_2("0.0080,0.0288,0.0616,0.1072,0.1920,0.3496,0.5952"); + values ("-0.6357,-0.6181,-0.5908,-0.5518,-0.4687,-0.3330,-0.1211",\ +"-0.6436,-0.6261,-0.5987,-0.5597,-0.4767,-0.3409,-0.1290",\ +"-0.6528,-0.6352,-0.6079,-0.5688,-0.4858,-0.3501,-0.1381",\ +"-0.6678,-0.6502,-0.6228,-0.5838,-0.5008,-0.3650,-0.1531",\ +"-0.6901,-0.6726,-0.6452,-0.6062,-0.5232,-0.3874,-0.1755",\ +"-0.7338,-0.7162,-0.6888,-0.6498,-0.5668,-0.4310,-0.2191",\ +"-0.8029,-0.7854,-0.7580,-0.7189,-0.6359,-0.5002,-0.2883"); + } + } + + timing() { + timing_type : hold_rising; + related_pin : "A_CLK"; + when : "(A_WEN & A_MEN)"; + sdf_cond : "A_W_ACCESS"; + + rise_constraint("SIG2SRAM_constraint_template") { + index_1("0.0080,0.0288,0.0616,0.1072,0.1920,0.3496,0.5952"); + index_2("0.0080,0.0288,0.0616,0.1072,0.1920,0.3496,0.5952"); + values ("0.8138,0.7924,0.7679,0.7250,0.6449,0.4984,0.2758",\ +"0.8218,0.8003,0.7759,0.7329,0.6528,0.5063,0.2837",\ +"0.8309,0.8094,0.7850,0.7420,0.6620,0.5155,0.2928",\ +"0.8459,0.8244,0.8000,0.7570,0.6769,0.5304,0.3078",\ +"0.8683,0.8468,0.8224,0.7794,0.6993,0.5528,0.3302",\ +"0.9119,0.8904,0.8660,0.8230,0.7429,0.5964,0.3738",\ +"0.9810,0.9596,0.9351,0.8922,0.8121,0.6656,0.4430"); + } + + fall_constraint("SIG2SRAM_constraint_template") { + index_1("0.0080,0.0288,0.0616,0.1072,0.1920,0.3496,0.5952"); + index_2("0.0080,0.0288,0.0616,0.1072,0.1920,0.3496,0.5952"); + values ("0.7396,0.7220,0.6947,0.6556,0.5726,0.4359,0.2250",\ +"0.7475,0.7300,0.7026,0.6636,0.5806,0.4438,0.2329",\ +"0.7567,0.7391,0.7118,0.6727,0.5897,0.4530,0.2420",\ +"0.7717,0.7541,0.7267,0.6877,0.6047,0.4679,0.2570",\ +"0.7940,0.7765,0.7491,0.7101,0.6271,0.4903,0.2794",\ +"0.8376,0.8201,0.7927,0.7537,0.6706,0.5339,0.3230",\ +"0.9068,0.8892,0.8619,0.8228,0.7398,0.6031,0.3922"); + } + } + } + + pin(A_BIST_EN) { + direction : input ; + capacitance : 0.00387999 ; + max_transition : "1" ; + related_power_pin : VDD; + related_ground_pin : VSS; + internal_power() { + rise_power("scalar") { + values (0); + } + fall_power("scalar") { + values (0); + } + } + } + +bus(A_BIST_ADDR) { + bus_type : A_7_0; + direction : input ; + capacitance : 0.0129586 ; + pin(A_BIST_ADDR[0]) { + capacitance : 0.0058687 ; + } + pin(A_BIST_ADDR[1]) { + capacitance : 0.00807137 ; + } + pin(A_BIST_ADDR[2]) { + capacitance : 0.0112051 ; + } + pin(A_BIST_ADDR[3]) { + capacitance : 0.00709524 ; + } + pin(A_BIST_ADDR[4]) { + capacitance : 0.00648778 ; + } + pin(A_BIST_ADDR[5]) { + capacitance : 0.011209 ; + } + pin(A_BIST_ADDR[6]) { + capacitance : 0.0140441 ; + } + max_transition : "0.5952" ; + pin(A_BIST_ADDR[7:0]) { + related_power_pin : VDD; + related_ground_pin : VSS; + internal_power() { + when : "A_BIST_MEN"; + rise_power("scalar"){ + values (0.0102); + } + fall_power("scalar"){ + values (0.0077); + } + } + internal_power() { + when : "!A_BIST_MEN"; + rise_power("scalar"){ + values (0.0150); + } + fall_power("scalar"){ + values (0.0029); + } + } + } + timing() { + timing_type : setup_rising; + related_pin : "A_BIST_CLK"; + when : "((A_BIST_WEN | A_BIST_REN)& A_BIST_MEN)" + sdf_cond : "A_BIST_RW_ACCESS" + + rise_constraint("SIG2SRAM_constraint_template") { + index_1("0.0080,0.0288,0.0616,0.1072,0.1920,0.3496,0.5952"); + index_2("0.0080,0.0288,0.0616,0.1072,0.1920,0.3496,0.5952"); + values ("-0.7371,-0.7176,-0.6863,-0.6434,-0.5652,-0.4168,-0.1980",\ +"-0.7566,-0.7371,-0.7059,-0.6629,-0.5848,-0.4363,-0.2137",\ +"-0.7879,-0.7645,-0.7332,-0.6902,-0.6121,-0.4637,-0.2449",\ +"-0.8309,-0.8074,-0.7762,-0.7332,-0.6551,-0.5066,-0.2879",\ +"-0.9051,-0.8895,-0.8543,-0.8113,-0.7332,-0.5887,-0.3660",\ +"-1.0418,-1.0262,-0.9949,-0.9480,-0.8699,-0.7293,-0.5027",\ +"-1.2684,-1.2449,-1.2176,-1.1707,-1.0965,-0.9480,-0.7293"); + } + + fall_constraint("SIG2SRAM_constraint_template") { + index_1("0.0080,0.0288,0.0616,0.1072,0.1920,0.3496,0.5952"); + index_2("0.0080,0.0288,0.0616,0.1072,0.1920,0.3496,0.5952"); + values ("-0.5926,-0.5730,-0.5418,-0.4988,-0.4246,-0.2879,-0.0730",\ +"-0.6121,-0.5926,-0.5613,-0.5223,-0.4441,-0.3074,-0.0887",\ +"-0.6395,-0.6199,-0.5926,-0.5496,-0.4715,-0.3348,-0.1160",\ +"-0.6863,-0.6668,-0.6355,-0.5965,-0.5184,-0.3777,-0.1590",\ +"-0.7605,-0.7410,-0.7137,-0.6746,-0.5926,-0.4559,-0.2410",\ +"-0.9012,-0.8816,-0.8504,-0.8113,-0.7332,-0.5926,-0.3895",\ +"-1.1238,-1.1043,-1.0769,-1.0379,-0.9559,-0.8191,-0.6004"); + } + } + + + timing() { + timing_type : hold_rising; + related_pin : "A_BIST_CLK"; + when : "((A_BIST_WEN | A_BIST_REN)& A_BIST_MEN)" + sdf_cond : "A_BIST_RW_ACCESS" + + rise_constraint("SIG2SRAM_constraint_template") { + index_1("0.0080,0.0288,0.0616,0.1072,0.1920,0.3496,0.5952"); + index_2("0.0080,0.0288,0.0616,0.1072,0.1920,0.3496,0.5952"); + values ("0.8488,0.8293,0.7980,0.7551,0.6730,0.5285,0.3059",\ +"0.8684,0.8488,0.8176,0.7746,0.6926,0.5480,0.3254",\ +"0.8996,0.8801,0.8449,0.8020,0.7238,0.5754,0.3527",\ +"0.9426,0.9191,0.8918,0.8488,0.7668,0.6223,0.3996",\ +"1.0168,1.0012,0.9699,0.9230,0.8449,0.7004,0.4777",\ +"1.1574,1.1379,1.1105,1.0598,0.9816,0.8371,0.6184",\ +"1.3801,1.3605,1.3254,1.2980,1.2043,1.0637,0.8371"); + } + + fall_constraint("SIG2SRAM_constraint_template") { + index_1("0.0080,0.0288,0.0616,0.1072,0.1920,0.3496,0.5952"); + index_2("0.0080,0.0288,0.0616,0.1072,0.1920,0.3496,0.5952"); + values ("0.6965,0.6770,0.6496,0.6066,0.5246,0.3918,0.1730",\ +"0.7160,0.6965,0.6652,0.6262,0.5441,0.4113,0.1965",\ +"0.7473,0.7277,0.6965,0.6535,0.5754,0.4426,0.2238",\ +"0.7863,0.7707,0.7395,0.7004,0.6223,0.4855,0.2629",\ +"0.8684,0.8449,0.8176,0.7785,0.7004,0.5637,0.3449",\ +"1.0051,0.9855,0.9855,0.9113,0.8332,0.7004,0.4895",\ +"1.2277,1.2082,1.1809,1.1379,1.0598,0.9230,0.7004"); + } + } +} +pin(A_BIST_WEN) { + direction : input ; + capacitance : 0.00313551 ; + max_transition : "0.5952" ; + related_power_pin : VDD; + related_ground_pin : VSS; + internal_power() { + when : "A_BIST_MEN"; + rise_power("scalar"){ + values (0.0036); + } + fall_power("scalar"){ + values (0.0007); + } + } + internal_power() { + when : "!A_BIST_MEN"; + rise_power("scalar"){ + values (0.0050); + } + fall_power("scalar"){ + values (0.0002); + } + } + timing() { + timing_type : setup_rising; + related_pin : "A_BIST_CLK"; + when : "A_BIST_MEN" + sdf_cond : "A_BIST_MEN" + + rise_constraint("SIG2SRAM_constraint_template") { + index_1("0.0080,0.0288,0.0616,0.1072,0.1920,0.3496,0.5952"); + index_2("0.0080,0.0288,0.0616,0.1072,0.1920,0.3496,0.5952"); + values ("0.3137,0.3332,0.3605,0.4035,0.4816,0.6223,0.8488",\ +"0.2980,0.3176,0.3410,0.3840,0.4660,0.6027,0.8293",\ +"0.2629,0.2824,0.3098,0.3527,0.4348,0.5754,0.7980",\ +"0.2199,0.2395,0.2668,0.3098,0.3918,0.5324,0.7590",\ +"0.1418,0.1613,0.1887,0.2316,0.3137,0.4348,0.6730",\ +"0.0012,0.0207,0.0520,0.0910,0.1730,0.3098,0.5285",\ +"-0.2215,-0.2020,-0.1746,-0.1277,-0.0496,0.0910,0.3098"); + } + + fall_constraint("SIG2SRAM_constraint_template") { + index_1("0.0080,0.0288,0.0616,0.1072,0.1920,0.3496,0.5952"); + index_2("0.0080,0.0288,0.0616,0.1072,0.1920,0.3496,0.5952"); + values ("0.4504,0.4699,0.4973,0.5324,0.6027,0.7355,0.9699",\ +"0.4309,0.4504,0.4777,0.5129,0.5910,0.7160,0.9504",\ +"0.3996,0.4191,0.4465,0.4816,0.5520,0.6848,0.9191",\ +"0.3605,0.3762,0.4035,0.4387,0.5168,0.6418,0.8723",\ +"0.2785,0.2980,0.3215,0.3605,0.4348,0.5637,0.7980",\ +"0.1379,0.1574,0.1809,0.2199,0.2980,0.4309,0.6457",\ +"-0.0809,-0.0613,-0.0340,0.0051,0.0832,0.2160,0.4191"); + } + } + + + timing() { + timing_type : hold_rising; + related_pin : "A_BIST_CLK"; + when : "A_BIST_MEN" + sdf_cond : "A_BIST_MEN" + + rise_constraint("SIG2SRAM_constraint_template") { + index_1("0.0080,0.0288,0.0616,0.1072,0.1920,0.3496,0.5952"); + index_2("0.0080,0.0288,0.0616,0.1072,0.1920,0.3496,0.5952"); + values ("0.3723,0.3527,0.3215,0.2785,0.1965,0.0559,-0.1668",\ +"0.3918,0.3723,0.3449,0.2980,0.2160,0.0754,-0.1473",\ +"0.4152,0.3996,0.3684,0.3254,0.2434,0.1066,-0.1199",\ +"0.4621,0.4465,0.4152,0.3723,0.2863,0.1496,-0.0730",\ +"0.5324,0.5207,0.4895,0.4465,0.3645,0.2199,0.0051",\ +"0.6770,0.6535,0.6301,0.5832,0.5090,0.3605,0.1418",\ +"0.9035,0.8879,0.8566,0.8137,0.7316,0.5871,0.3684"); + } + + fall_constraint("SIG2SRAM_constraint_template") { + index_1("0.0080,0.0288,0.0616,0.1072,0.1920,0.3496,0.5952"); + index_2("0.0080,0.0288,0.0616,0.1072,0.1920,0.3496,0.5952"); + values ("0.3762,0.3566,0.3293,0.2863,0.2043,0.0676,-0.1434",\ +"0.3957,0.3762,0.3488,0.3059,0.2238,0.0871,-0.1199",\ +"0.4230,0.4035,0.3723,0.3332,0.2512,0.1184,-0.0965",\ +"0.4660,0.4465,0.4191,0.3762,0.2941,0.1613,-0.0496",\ +"0.5324,0.5168,0.4973,0.4543,0.3723,0.2316,0.0285",\ +"0.6809,0.6613,0.6340,0.5910,0.5129,0.3645,0.1652",\ +"0.9113,0.8918,0.8605,0.8176,0.7395,0.5988,0.3879"); + } + } + } +pin(A_BIST_REN) { + direction : input ; + capacitance : 0.00381144 ; + max_transition : "0.5952" ; + related_power_pin : VDD; + related_ground_pin : VSS; + internal_power() { + when : "A_BIST_MEN"; + rise_power("scalar"){ + values (0.0040); + } + fall_power("scalar"){ + values (0.0015); + } + } + internal_power() { + when : "!A_BIST_MEN"; + rise_power("scalar"){ + values (0.0040); + } + fall_power("scalar"){ + values (0.0013); + } + } + timing() { + timing_type : setup_rising; + related_pin : "A_BIST_CLK"; + when : "A_BIST_MEN" + sdf_cond : "A_BIST_MEN" + + rise_constraint("SIG2SRAM_constraint_template") { + index_1("0.0080,0.0288,0.0616,0.1072,0.1920,0.3496,0.5952"); + index_2("0.0080,0.0288,0.0616,0.1072,0.1920,0.3496,0.5952"); + values ("-0.0770,-0.0574,-0.0262,0.0168,0.0949,0.2355,0.4582",\ +"-0.0965,-0.0770,-0.0457,-0.0027,0.0754,0.2160,0.4387",\ +"-0.1199,-0.1004,-0.0730,-0.0262,0.0520,0.1887,0.4113",\ +"-0.1590,-0.1434,-0.1160,-0.0730,0.0051,0.1457,0.3645",\ +"-0.2449,-0.2254,-0.1941,-0.1473,-0.0770,0.0676,0.2863",\ +"-0.3816,-0.3699,-0.3387,-0.2801,-0.2215,-0.0770,0.1457",\ +"-0.6121,-0.5926,-0.5613,-0.5145,-0.4363,-0.2996,-0.0730"); + } + + fall_constraint("SIG2SRAM_constraint_template") { + index_1("0.0080,0.0288,0.0616,0.1072,0.1920,0.3496,0.5952"); + index_2("0.0080,0.0288,0.0616,0.1072,0.1920,0.3496,0.5952"); + values ("0.1262,0.1457,0.1691,0.2121,0.2824,0.4191,0.6457",\ +"0.1105,0.1262,0.1496,0.1887,0.2629,0.3996,0.6262",\ +"0.0793,0.0949,0.1223,0.1652,0.2395,0.3684,0.5949",\ +"0.0363,0.0559,0.0793,0.1223,0.2004,0.3410,0.5520",\ +"-0.0457,-0.0262,0.0012,0.0441,0.1301,0.2629,0.4738",\ +"-0.1902,-0.1746,-0.1434,-0.1043,-0.0184,0.1223,0.3332",\ +"-0.4129,-0.3934,-0.3660,-0.3230,-0.2449,-0.1043,0.1105"); + } + } + + + timing() { + timing_type : hold_rising; + related_pin : "A_BIST_CLK"; + when : "A_BIST_MEN" + sdf_cond : "A_BIST_MEN" + + rise_constraint("SIG2SRAM_constraint_template") { + index_1("0.0080,0.0288,0.0616,0.1072,0.1920,0.3496,0.5952"); + index_2("0.0080,0.0288,0.0616,0.1072,0.1920,0.3496,0.5952"); + values ("0.4113,0.3918,0.3645,0.3176,0.2395,0.0988,-0.1238",\ +"0.4309,0.4113,0.3840,0.3371,0.2590,0.1184,-0.1043",\ +"0.4582,0.4387,0.4113,0.3645,0.2824,0.1457,-0.0770",\ +"0.5051,0.4816,0.4543,0.4074,0.3293,0.1887,-0.0340",\ +"0.5715,0.5598,0.5324,0.4895,0.4035,0.2512,0.0441",\ +"0.7043,0.7004,0.6730,0.6262,0.5402,0.3957,0.1809",\ +"0.9387,0.9270,0.8957,0.8527,0.7746,0.6262,0.4074"); + } + + fall_constraint("SIG2SRAM_constraint_template") { + index_1("0.0080,0.0288,0.0616,0.1072,0.1920,0.3496,0.5952"); + index_2("0.0080,0.0288,0.0616,0.1072,0.1920,0.3496,0.5952"); + values ("0.4152,0.3918,0.3645,0.3215,0.2395,0.1027,-0.1082",\ +"0.4309,0.4113,0.3801,0.3410,0.2590,0.1223,-0.0926",\ +"0.4582,0.4387,0.4074,0.3684,0.2863,0.1496,-0.0613",\ +"0.5012,0.4816,0.4504,0.4074,0.3293,0.1887,-0.0145",\ +"0.5715,0.5559,0.5285,0.4816,0.3996,0.2512,0.0598",\ +"0.7160,0.7004,0.6691,0.6262,0.5520,0.4035,0.2004",\ +"0.9387,0.9191,0.8957,0.8488,0.7707,0.6262,0.4113"); + } + } + } +pin(A_BIST_MEN) { + direction : input ; + capacitance : 0.00300347 ; + max_transition : "0.5952" ; + related_power_pin : VDD; + related_ground_pin : VSS; + internal_power() { + rise_power("scalar"){ + values (0.0161); + } + fall_power("scalar"){ + values (0.0002); + } + } + timing() { + timing_type : setup_rising; + related_pin : "A_BIST_CLK"; + + rise_constraint("SIG2SRAM_constraint_template") { + index_1("0.0080,0.0288,0.0616,0.1072,0.1920,0.3496,0.5952"); + index_2("0.0080,0.0288,0.0616,0.1072,0.1920,0.3496,0.5952"); + values ("0.3215,0.3449,0.3684,0.4113,0.4895,0.6301,0.8527",\ +"0.3059,0.3254,0.3527,0.3957,0.4738,0.6145,0.8371",\ +"0.2746,0.2941,0.3215,0.3645,0.4426,0.5871,0.8059",\ +"0.2316,0.2512,0.2785,0.3215,0.3996,0.5402,0.7629",\ +"0.1496,0.1730,0.1965,0.2395,0.3215,0.4660,0.6848",\ +"0.0090,0.0285,0.0598,0.1027,0.1809,0.3176,0.5402",\ +"-0.2098,-0.1902,-0.1668,-0.1199,-0.0418,0.0988,0.3137"); + } + + fall_constraint("SIG2SRAM_constraint_template") { + index_1("0.0080,0.0288,0.0616,0.1072,0.1920,0.3496,0.5952"); + index_2("0.0080,0.0288,0.0616,0.1072,0.1920,0.3496,0.5952"); + values ("0.4582,0.4738,0.5012,0.5363,0.6145,0.7395,0.9738",\ +"0.4387,0.4543,0.4816,0.5207,0.5910,0.7199,0.9582",\ +"0.4035,0.4230,0.4504,0.4855,0.5637,0.6887,0.9230",\ +"0.3645,0.3840,0.4074,0.4465,0.5285,0.6496,0.8840",\ +"0.2824,0.3020,0.3254,0.3645,0.4465,0.5715,0.7980",\ +"0.1418,0.1613,0.1887,0.2238,0.3020,0.4309,0.6496",\ +"-0.0770,-0.0574,-0.0301,0.0090,0.0910,0.2238,0.4191"); + } + } + + + timing() { + timing_type : hold_rising; + related_pin : "A_BIST_CLK"; + + rise_constraint("SIG2SRAM_constraint_template") { + index_1("0.0080,0.0288,0.0616,0.1072,0.1920,0.3496,0.5952"); + index_2("0.0080,0.0288,0.0616,0.1072,0.1920,0.3496,0.5952"); + values ("0.3762,0.3605,0.3293,0.2863,0.2043,0.0637,-0.1629",\ +"0.3996,0.3801,0.3488,0.3020,0.2238,0.0832,-0.1395",\ +"0.4230,0.4074,0.3723,0.3293,0.2473,0.1105,-0.1121",\ +"0.4621,0.4465,0.4152,0.3762,0.2941,0.1535,-0.0691",\ +"0.5441,0.5285,0.4973,0.4465,0.3684,0.2316,0.0090",\ +"0.6848,0.6652,0.6301,0.5910,0.5129,0.3605,0.1496",\ +"0.9074,0.8918,0.8566,0.8215,0.7395,0.5910,0.3723"); + } + + fall_constraint("SIG2SRAM_constraint_template") { + index_1("0.0080,0.0288,0.0616,0.1072,0.1920,0.3496,0.5952"); + index_2("0.0080,0.0288,0.0616,0.1072,0.1920,0.3496,0.5952"); + values ("0.3762,0.3605,0.3332,0.2863,0.2043,0.0715,-0.1395",\ +"0.3996,0.3762,0.3488,0.3059,0.2238,0.0910,-0.1199",\ +"0.4270,0.4035,0.3762,0.3332,0.2512,0.1184,-0.0965",\ +"0.4699,0.4504,0.4191,0.3762,0.2941,0.1613,-0.0496",\ +"0.5441,0.5285,0.4973,0.4543,0.3762,0.2355,0.0324",\ +"0.6770,0.6613,0.6340,0.5949,0.5207,0.3762,0.1652",\ +"0.9074,0.8918,0.8605,0.8176,0.7395,0.6027,0.3918"); + } + } + } +bus(A_BIST_BM) { + bus_type : D_15_0; + direction : input ; + capacitance : 0.00347781 ; + max_transition : "0.5952" ; + pin(A_BIST_BM[15:0]) { + related_power_pin : VDD; + related_ground_pin : VSS; + internal_power() { + when : "A_BIST_MEN"; + rise_power("scalar"){ + values (0.0469); + } + fall_power("scalar"){ + values (0.0152); + } + } + internal_power() { + when : "!A_BIST_MEN"; + rise_power("scalar"){ + values (0.0453); + } + fall_power("scalar"){ + values (0.0145); + } + } + } + timing() { + timing_type : setup_rising; + related_pin : "A_BIST_CLK"; + when : "(A_BIST_WEN & A_BIST_MEN)" + sdf_cond : "A_BIST_RW_ACCESS" + + rise_constraint("SIG2SRAM_constraint_template") { + index_1("0.0080,0.0288,0.0616,0.1072,0.1920,0.3496,0.5952"); + index_2("0.0080,0.0288,0.0616,0.1072,0.1920,0.3496,0.5952"); + values ("-0.6982,-0.6787,-0.6533,-0.6103,-0.5293,-0.3838,-0.1611",\ +"-0.7062,-0.6866,-0.6612,-0.6183,-0.5372,-0.3917,-0.1690",\ +"-0.7153,-0.6958,-0.6704,-0.6274,-0.5464,-0.4008,-0.1782",\ +"-0.7303,-0.7107,-0.6853,-0.6424,-0.5613,-0.4158,-0.1932",\ +"-0.7527,-0.7331,-0.7077,-0.6648,-0.5837,-0.4382,-0.2155",\ +"-0.7962,-0.7767,-0.7513,-0.7084,-0.6273,-0.4818,-0.2591",\ +"-0.8654,-0.8459,-0.8205,-0.7775,-0.6965,-0.5510,-0.3283"); + } + + fall_constraint("SIG2SRAM_constraint_template") { + index_1("0.0080,0.0288,0.0616,0.1072,0.1920,0.3496,0.5952"); + index_2("0.0080,0.0288,0.0616,0.1072,0.1920,0.3496,0.5952"); + values ("-0.6357,-0.6181,-0.5908,-0.5518,-0.4687,-0.3330,-0.1211",\ +"-0.6436,-0.6261,-0.5987,-0.5597,-0.4767,-0.3409,-0.1290",\ +"-0.6528,-0.6352,-0.6079,-0.5688,-0.4858,-0.3501,-0.1381",\ +"-0.6678,-0.6502,-0.6228,-0.5838,-0.5008,-0.3650,-0.1531",\ +"-0.6901,-0.6726,-0.6452,-0.6062,-0.5232,-0.3874,-0.1755",\ +"-0.7338,-0.7162,-0.6888,-0.6498,-0.5668,-0.4310,-0.2191",\ +"-0.8029,-0.7854,-0.7580,-0.7189,-0.6359,-0.5002,-0.2883"); + } + } + + + timing() { + timing_type : hold_rising; + related_pin : "A_BIST_CLK"; + when : "(A_BIST_WEN & A_BIST_MEN)" + sdf_cond : "A_BIST_RW_ACCESS" + + rise_constraint("SIG2SRAM_constraint_template") { + index_1("0.0080,0.0288,0.0616,0.1072,0.1920,0.3496,0.5952"); + index_2("0.0080,0.0288,0.0616,0.1072,0.1920,0.3496,0.5952"); + values ("0.8138,0.7924,0.7679,0.7250,0.6449,0.4984,0.2758",\ +"0.8218,0.8003,0.7759,0.7329,0.6528,0.5063,0.2837",\ +"0.8309,0.8094,0.7850,0.7420,0.6620,0.5155,0.2928",\ +"0.8459,0.8244,0.8000,0.7570,0.6769,0.5304,0.3078",\ +"0.8683,0.8468,0.8224,0.7794,0.6993,0.5528,0.3302",\ +"0.9119,0.8904,0.8660,0.8230,0.7429,0.5964,0.3738",\ +"0.9810,0.9596,0.9351,0.8922,0.8121,0.6656,0.4430"); + } + + fall_constraint("SIG2SRAM_constraint_template") { + index_1("0.0080,0.0288,0.0616,0.1072,0.1920,0.3496,0.5952"); + index_2("0.0080,0.0288,0.0616,0.1072,0.1920,0.3496,0.5952"); + values ("0.7396,0.7220,0.6947,0.6556,0.5726,0.4359,0.2250",\ +"0.7475,0.7300,0.7026,0.6636,0.5806,0.4438,0.2329",\ +"0.7567,0.7391,0.7118,0.6727,0.5897,0.4530,0.2420",\ +"0.7717,0.7541,0.7267,0.6877,0.6047,0.4679,0.2570",\ +"0.7940,0.7765,0.7491,0.7101,0.6271,0.4903,0.2794",\ +"0.8376,0.8201,0.7927,0.7537,0.6706,0.5339,0.3230",\ +"0.9068,0.8892,0.8619,0.8228,0.7398,0.6031,0.3922"); + } + } +} + pin(A_BIST_CLK) { + direction : input; + capacitance : 0.00378957; + max_transition : "0.5952"; + clock : "true" ; + pin_func_type : active_rising ; + + timing () { + timing_type : "min_pulse_width"; + related_pin : "A_BIST_CLK"; + rise_constraint("CLKTRAN_constraint_template") { + index_1("0.008,0.5952"); + values("0.4,0.4"); + } + } + + related_power_pin : VDD; + related_ground_pin : VSS; + + internal_power() { + when : "!A_BIST_MEN & !A_BIST_WEN & !A_BIST_REN"; + rise_power("scalar"){ + values (0); + } + fall_power("scalar"){ + values (0); + } + } + internal_power() { + when : "!A_BIST_MEN & A_BIST_WEN & !A_BIST_REN"; + rise_power("scalar"){ + values (0.4498); + } + fall_power("scalar"){ + values (0); + } + } + internal_power() { + when : "A_BIST_MEN & A_BIST_WEN & !A_BIST_REN"; + rise_power("scalar"){ + values (15.3644); + } + fall_power("scalar"){ + values (0); + } + } + internal_power() { + when : "A_BIST_MEN & A_BIST_WEN & A_BIST_REN"; + rise_power("scalar"){ + values (16.3884); + } + fall_power("scalar"){ + values (0); + } + } + internal_power() { + when : "A_BIST_MEN & !A_BIST_WEN & A_BIST_REN"; + rise_power("scalar"){ + values (11.8557); + } + fall_power("scalar"){ + values (0); + } + } + internal_power() { + when : "!A_BIST_MEN & !A_BIST_WEN & A_BIST_REN"; + rise_power("scalar"){ + values (0.2837); + } + fall_power("scalar"){ + values (0); + } + } + internal_power() { + when : "!A_BIST_MEN & A_BIST_WEN & A_BIST_REN"; + rise_power("scalar"){ + values (0.6730); + } + fall_power("scalar"){ + values (0); + } + } + internal_power() { + when : "A_BIST_MEN & !A_BIST_WEN & !A_BIST_REN"; + rise_power("scalar"){ + values (0); + } + fall_power("scalar"){ + values (0); + } + } + } + bus(A_BIST_DIN) { + bus_type : D_15_0; + direction : input ; + capacitance : 0.00396073 ; + memory_write() { + address : A_BIST_ADDR ; + clocked_on : A_BIST_CLK; + } + + max_transition : "0.5952" ; + pin(A_BIST_DIN[15:0]) { + related_power_pin : VDD; + related_ground_pin : VSS; + internal_power() { + when : "A_BIST_MEN"; + rise_power("scalar"){ + values (0.0469); + } + fall_power("scalar"){ + values (0.0152); + } + } + internal_power() { + when : "!A_BIST_MEN"; + rise_power("scalar"){ + values (0.0453); + } + fall_power("scalar"){ + values (0.0145); + } + } + } + timing() { + timing_type : setup_rising; + related_pin : "A_BIST_CLK"; + when : "(A_BIST_WEN & A_BIST_MEN)"; + sdf_cond : "A_BIST_W_ACCESS"; + + rise_constraint("SIG2SRAM_constraint_template") { + index_1("0.0080,0.0288,0.0616,0.1072,0.1920,0.3496,0.5952"); + index_2("0.0080,0.0288,0.0616,0.1072,0.1920,0.3496,0.5952"); + values ("-0.6982,-0.6787,-0.6533,-0.6103,-0.5293,-0.3838,-0.1611",\ +"-0.7062,-0.6866,-0.6612,-0.6183,-0.5372,-0.3917,-0.1690",\ +"-0.7153,-0.6958,-0.6704,-0.6274,-0.5464,-0.4008,-0.1782",\ +"-0.7303,-0.7107,-0.6853,-0.6424,-0.5613,-0.4158,-0.1932",\ +"-0.7527,-0.7331,-0.7077,-0.6648,-0.5837,-0.4382,-0.2155",\ +"-0.7962,-0.7767,-0.7513,-0.7084,-0.6273,-0.4818,-0.2591",\ +"-0.8654,-0.8459,-0.8205,-0.7775,-0.6965,-0.5510,-0.3283"); + } + + fall_constraint("SIG2SRAM_constraint_template") { + index_1("0.0080,0.0288,0.0616,0.1072,0.1920,0.3496,0.5952"); + index_2("0.0080,0.0288,0.0616,0.1072,0.1920,0.3496,0.5952"); + values ("-0.6357,-0.6181,-0.5908,-0.5518,-0.4687,-0.3330,-0.1211",\ +"-0.6436,-0.6261,-0.5987,-0.5597,-0.4767,-0.3409,-0.1290",\ +"-0.6528,-0.6352,-0.6079,-0.5688,-0.4858,-0.3501,-0.1381",\ +"-0.6678,-0.6502,-0.6228,-0.5838,-0.5008,-0.3650,-0.1531",\ +"-0.6901,-0.6726,-0.6452,-0.6062,-0.5232,-0.3874,-0.1755",\ +"-0.7338,-0.7162,-0.6888,-0.6498,-0.5668,-0.4310,-0.2191",\ +"-0.8029,-0.7854,-0.7580,-0.7189,-0.6359,-0.5002,-0.2883"); + } + } + + timing() { + timing_type : hold_rising; + related_pin : "A_BIST_CLK"; + when : "(A_BIST_WEN & A_BIST_MEN)"; + sdf_cond : "A_BIST_W_ACCESS"; + + rise_constraint("SIG2SRAM_constraint_template") { + index_1("0.0080,0.0288,0.0616,0.1072,0.1920,0.3496,0.5952"); + index_2("0.0080,0.0288,0.0616,0.1072,0.1920,0.3496,0.5952"); + values ("0.8138,0.7924,0.7679,0.7250,0.6449,0.4984,0.2758",\ +"0.8218,0.8003,0.7759,0.7329,0.6528,0.5063,0.2837",\ +"0.8309,0.8094,0.7850,0.7420,0.6620,0.5155,0.2928",\ +"0.8459,0.8244,0.8000,0.7570,0.6769,0.5304,0.3078",\ +"0.8683,0.8468,0.8224,0.7794,0.6993,0.5528,0.3302",\ +"0.9119,0.8904,0.8660,0.8230,0.7429,0.5964,0.3738",\ +"0.9810,0.9596,0.9351,0.8922,0.8121,0.6656,0.4430"); + } + + fall_constraint("SIG2SRAM_constraint_template") { + index_1("0.0080,0.0288,0.0616,0.1072,0.1920,0.3496,0.5952"); + index_2("0.0080,0.0288,0.0616,0.1072,0.1920,0.3496,0.5952"); + values ("0.7396,0.7220,0.6947,0.6556,0.5726,0.4359,0.2250",\ +"0.7475,0.7300,0.7026,0.6636,0.5806,0.4438,0.2329",\ +"0.7567,0.7391,0.7118,0.6727,0.5897,0.4530,0.2420",\ +"0.7717,0.7541,0.7267,0.6877,0.6047,0.4679,0.2570",\ +"0.7940,0.7765,0.7491,0.7101,0.6271,0.4903,0.2794",\ +"0.8376,0.8201,0.7927,0.7537,0.6706,0.5339,0.3230",\ +"0.9068,0.8892,0.8619,0.8228,0.7398,0.6031,0.3922"); + } + } + } + +bus(A_DOUT) { + + bus_type : D_15_0; + direction : output ; + capacitance : 0 ; + max_capacitance : 0.064 ; + memory_read() { + address : A_ADDR ; + } + pin(A_DOUT[15:0]) { + related_power_pin : VDD; + related_ground_pin : VSS; + internal_power() { + rise_power("scalar") { + values (0); + } + fall_power("scalar") { + values (0); + } + } + } + timing() { + related_pin : "A_CLK"; + timing_type : rising_edge ; + timing_sense : non_unate ; + + cell_rise(SIG2SRAM_delay_template) { + index_1("0.0080,0.0288,0.0616,0.1072,0.1920,0.3496,0.5952"); + index_2("0.0008,0.0014,0.0051,0.0100,0.0339,0.0640"); + values ("5.0746,5.0780,5.0902,5.1041,5.1567,5.2145",\ +"5.0885,5.0919,5.1041,5.1180,5.1706,5.2284",\ +"5.0984,5.1017,5.1139,5.1279,5.1804,5.2383",\ +"5.1117,5.1150,5.1272,5.1412,5.1937,5.2516",\ +"5.1349,5.1383,5.1505,5.1644,5.2170,5.2748",\ +"5.1797,5.1831,5.1952,5.2092,5.2617,5.3196",\ +"5.2469,5.2503,5.2625,5.2764,5.3290,5.3868"); + } + cell_fall(SIG2SRAM_delay_template) { + index_1("0.0080,0.0288,0.0616,0.1072,0.1920,0.3496,0.5952"); + index_2("0.0008,0.0014,0.0051,0.0100,0.0339,0.0640"); + values ("4.9649,4.9671,4.9771,4.9888,5.0321,5.0760",\ +"4.9788,4.9810,4.9910,5.0027,5.0460,5.0899",\ +"4.9887,4.9908,5.0009,5.0125,5.0559,5.0997",\ +"5.0019,5.0041,5.0142,5.0258,5.0692,5.1130",\ +"5.0252,5.0274,5.0374,5.0491,5.0924,5.1363",\ +"5.0700,5.0721,5.0822,5.0939,5.1372,5.1810",\ +"5.1372,5.1394,5.1494,5.1611,5.2045,5.2483"); + } + + rise_transition(SRAM_load_template) { + index_1("0.0008,0.0014,0.0051,0.0100,0.0339,0.0640"); + values ("0.0560,0.0583,0.0696,0.0816,0.1519,0.2335"); + } + fall_transition(SRAM_load_template) { + index_1("0.0008,0.0014,0.0051,0.0100,0.0339,0.0640"); + values ("0.0428,0.0445,0.0538,0.0658,0.1181,0.1751"); + } + } +} + pin(B_DLY) { + direction : input ; + capacitance : 0.00387999 ; + max_transition : "1" ; + related_power_pin : VDD; + related_ground_pin : VSS; + internal_power() { + rise_power("scalar") { + values (0); + } + fall_power("scalar") { + values (0); + } + } + } + +bus(B_ADDR) { + bus_type : A_7_0; + direction : input ; + capacitance : 0.0129586 ; + pin(B_ADDR[0]) { + capacitance : 0.00588404 ; + } + pin(B_ADDR[1]) { + capacitance : 0.0080425 ; + } + pin(B_ADDR[2]) { + capacitance : 0.0112051 ; + } + pin(B_ADDR[3]) { + capacitance : 0.00706428 ; + } + pin(B_ADDR[4]) { + capacitance : 0.00656149 ; + } + pin(B_ADDR[5]) { + capacitance : 0.0111839 ; + } + pin(B_ADDR[6]) { + capacitance : 0.0140236 ; + } + max_transition : "0.5952" ; + pin(B_ADDR[7:0]) { + related_power_pin : VDD; + related_ground_pin : VSS; + internal_power() { + when : "B_MEN"; + rise_power("scalar"){ + values (0.0102); + } + fall_power("scalar"){ + values (0.0077); + } + } + internal_power() { + when : "!B_MEN"; + rise_power("scalar"){ + values (0.0150); + } + fall_power("scalar"){ + values (0.0029); + } + } + } + timing() { + timing_type : setup_rising; + related_pin : "B_CLK"; + when : "((B_WEN | B_REN)& B_MEN)" + sdf_cond : "B_RW_ACCESS" + + rise_constraint("SIG2SRAM_constraint_template") { + index_1("0.0080,0.0288,0.0616,0.1072,0.1920,0.3496,0.5952"); + index_2("0.0080,0.0288,0.0616,0.1072,0.1920,0.3496,0.5952"); + values ("-0.7371,-0.7176,-0.6863,-0.6434,-0.5652,-0.4168,-0.1980",\ +"-0.7566,-0.7371,-0.7059,-0.6629,-0.5848,-0.4363,-0.2137",\ +"-0.7879,-0.7645,-0.7332,-0.6902,-0.6121,-0.4637,-0.2449",\ +"-0.8309,-0.8074,-0.7762,-0.7332,-0.6551,-0.5066,-0.2879",\ +"-0.9051,-0.8895,-0.8543,-0.8113,-0.7332,-0.5887,-0.3660",\ +"-1.0418,-1.0262,-0.9949,-0.9480,-0.8699,-0.7293,-0.5027",\ +"-1.2684,-1.2449,-1.2176,-1.1707,-1.0965,-0.9480,-0.7293"); + } + + fall_constraint("SIG2SRAM_constraint_template") { + index_1("0.0080,0.0288,0.0616,0.1072,0.1920,0.3496,0.5952"); + index_2("0.0080,0.0288,0.0616,0.1072,0.1920,0.3496,0.5952"); + values ("-0.5926,-0.5730,-0.5418,-0.4988,-0.4246,-0.2879,-0.0730",\ +"-0.6121,-0.5926,-0.5613,-0.5223,-0.4441,-0.3074,-0.0887",\ +"-0.6395,-0.6199,-0.5926,-0.5496,-0.4715,-0.3348,-0.1160",\ +"-0.6863,-0.6668,-0.6355,-0.5965,-0.5184,-0.3777,-0.1590",\ +"-0.7605,-0.7410,-0.7137,-0.6746,-0.5926,-0.4559,-0.2410",\ +"-0.9012,-0.8816,-0.8504,-0.8113,-0.7332,-0.5926,-0.3895",\ +"-1.1238,-1.1043,-1.0769,-1.0379,-0.9559,-0.8191,-0.6004"); + } + } + + + timing() { + timing_type : hold_rising; + related_pin : "B_CLK"; + when : "((B_WEN | B_REN)& B_MEN)" + sdf_cond : "B_RW_ACCESS" + + rise_constraint("SIG2SRAM_constraint_template") { + index_1("0.0080,0.0288,0.0616,0.1072,0.1920,0.3496,0.5952"); + index_2("0.0080,0.0288,0.0616,0.1072,0.1920,0.3496,0.5952"); + values ("0.8488,0.8293,0.7980,0.7551,0.6730,0.5285,0.3059",\ +"0.8684,0.8488,0.8176,0.7746,0.6926,0.5480,0.3254",\ +"0.8996,0.8801,0.8449,0.8020,0.7238,0.5754,0.3527",\ +"0.9426,0.9191,0.8918,0.8488,0.7668,0.6223,0.3996",\ +"1.0168,1.0012,0.9699,0.9230,0.8449,0.7004,0.4777",\ +"1.1574,1.1379,1.1105,1.0598,0.9816,0.8371,0.6184",\ +"1.3801,1.3605,1.3254,1.2980,1.2043,1.0637,0.8371"); + } + + fall_constraint("SIG2SRAM_constraint_template") { + index_1("0.0080,0.0288,0.0616,0.1072,0.1920,0.3496,0.5952"); + index_2("0.0080,0.0288,0.0616,0.1072,0.1920,0.3496,0.5952"); + values ("0.6965,0.6770,0.6496,0.6066,0.5246,0.3918,0.1730",\ +"0.7160,0.6965,0.6652,0.6262,0.5441,0.4113,0.1965",\ +"0.7473,0.7277,0.6965,0.6535,0.5754,0.4426,0.2238",\ +"0.7863,0.7707,0.7395,0.7004,0.6223,0.4855,0.2629",\ +"0.8684,0.8449,0.8176,0.7785,0.7004,0.5637,0.3449",\ +"1.0051,0.9855,0.9855,0.9113,0.8332,0.7004,0.4895",\ +"1.2277,1.2082,1.1809,1.1379,1.0598,0.9230,0.7004"); + } + } +} +pin(B_WEN) { + direction : input ; + capacitance : 0.00313551 ; + max_transition : "0.5952" ; + related_power_pin : VDD; + related_ground_pin : VSS; + internal_power() { + when : "B_MEN"; + rise_power("scalar"){ + values (0.0036); + } + fall_power("scalar"){ + values (0.0007); + } + } + internal_power() { + when : "!B_MEN"; + rise_power("scalar"){ + values (0.0050); + } + fall_power("scalar"){ + values (0.0002); + } + } + timing() { + timing_type : setup_rising; + related_pin : "B_CLK"; + when : "B_MEN" + sdf_cond : "B_MEN" + + rise_constraint("SIG2SRAM_constraint_template") { + index_1("0.0080,0.0288,0.0616,0.1072,0.1920,0.3496,0.5952"); + index_2("0.0080,0.0288,0.0616,0.1072,0.1920,0.3496,0.5952"); + values ("0.3137,0.3332,0.3605,0.4035,0.4816,0.6223,0.8488",\ +"0.2980,0.3176,0.3410,0.3840,0.4660,0.6027,0.8293",\ +"0.2629,0.2824,0.3098,0.3527,0.4348,0.5754,0.7980",\ +"0.2199,0.2395,0.2668,0.3098,0.3918,0.5324,0.7590",\ +"0.1418,0.1613,0.1887,0.2316,0.3137,0.4348,0.6730",\ +"0.0012,0.0207,0.0520,0.0910,0.1730,0.3098,0.5285",\ +"-0.2215,-0.2020,-0.1746,-0.1277,-0.0496,0.0910,0.3098"); + } + + fall_constraint("SIG2SRAM_constraint_template") { + index_1("0.0080,0.0288,0.0616,0.1072,0.1920,0.3496,0.5952"); + index_2("0.0080,0.0288,0.0616,0.1072,0.1920,0.3496,0.5952"); + values ("0.4504,0.4699,0.4973,0.5324,0.6027,0.7355,0.9699",\ +"0.4309,0.4504,0.4777,0.5129,0.5910,0.7160,0.9504",\ +"0.3996,0.4191,0.4465,0.4816,0.5520,0.6848,0.9191",\ +"0.3605,0.3762,0.4035,0.4387,0.5168,0.6418,0.8723",\ +"0.2785,0.2980,0.3215,0.3605,0.4348,0.5637,0.7980",\ +"0.1379,0.1574,0.1809,0.2199,0.2980,0.4309,0.6457",\ +"-0.0809,-0.0613,-0.0340,0.0051,0.0832,0.2160,0.4191"); + } + } + + + timing() { + timing_type : hold_rising; + related_pin : "B_CLK"; + when : "B_MEN" + sdf_cond : "B_MEN" + + rise_constraint("SIG2SRAM_constraint_template") { + index_1("0.0080,0.0288,0.0616,0.1072,0.1920,0.3496,0.5952"); + index_2("0.0080,0.0288,0.0616,0.1072,0.1920,0.3496,0.5952"); + values ("0.3723,0.3527,0.3215,0.2785,0.1965,0.0559,-0.1668",\ +"0.3918,0.3723,0.3449,0.2980,0.2160,0.0754,-0.1473",\ +"0.4152,0.3996,0.3684,0.3254,0.2434,0.1066,-0.1199",\ +"0.4621,0.4465,0.4152,0.3723,0.2863,0.1496,-0.0730",\ +"0.5324,0.5207,0.4895,0.4465,0.3645,0.2199,0.0051",\ +"0.6770,0.6535,0.6301,0.5832,0.5090,0.3605,0.1418",\ +"0.9035,0.8879,0.8566,0.8137,0.7316,0.5871,0.3684"); + } + + fall_constraint("SIG2SRAM_constraint_template") { + index_1("0.0080,0.0288,0.0616,0.1072,0.1920,0.3496,0.5952"); + index_2("0.0080,0.0288,0.0616,0.1072,0.1920,0.3496,0.5952"); + values ("0.3762,0.3566,0.3293,0.2863,0.2043,0.0676,-0.1434",\ +"0.3957,0.3762,0.3488,0.3059,0.2238,0.0871,-0.1199",\ +"0.4230,0.4035,0.3723,0.3332,0.2512,0.1184,-0.0965",\ +"0.4660,0.4465,0.4191,0.3762,0.2941,0.1613,-0.0496",\ +"0.5324,0.5168,0.4973,0.4543,0.3723,0.2316,0.0285",\ +"0.6809,0.6613,0.6340,0.5910,0.5129,0.3645,0.1652",\ +"0.9113,0.8918,0.8605,0.8176,0.7395,0.5988,0.3879"); + } + } + } +pin(B_REN) { + direction : input ; + capacitance : 0.00381144 ; + max_transition : "0.5952" ; + related_power_pin : VDD; + related_ground_pin : VSS; + internal_power() { + when : "B_MEN"; + rise_power("scalar"){ + values (0.0040); + } + fall_power("scalar"){ + values (0.0015); + } + } + internal_power() { + when : "!B_MEN"; + rise_power("scalar"){ + values (0.0040); + } + fall_power("scalar"){ + values (0.0013); + } + } + timing() { + timing_type : setup_rising; + related_pin : "B_CLK"; + when : "B_MEN" + sdf_cond : "B_MEN" + + rise_constraint("SIG2SRAM_constraint_template") { + index_1("0.0080,0.0288,0.0616,0.1072,0.1920,0.3496,0.5952"); + index_2("0.0080,0.0288,0.0616,0.1072,0.1920,0.3496,0.5952"); + values ("-0.0770,-0.0574,-0.0262,0.0168,0.0949,0.2355,0.4582",\ +"-0.0965,-0.0770,-0.0457,-0.0027,0.0754,0.2160,0.4387",\ +"-0.1199,-0.1004,-0.0730,-0.0262,0.0520,0.1887,0.4113",\ +"-0.1590,-0.1434,-0.1160,-0.0730,0.0051,0.1457,0.3645",\ +"-0.2449,-0.2254,-0.1941,-0.1473,-0.0770,0.0676,0.2863",\ +"-0.3816,-0.3699,-0.3387,-0.2801,-0.2215,-0.0770,0.1457",\ +"-0.6121,-0.5926,-0.5613,-0.5145,-0.4363,-0.2996,-0.0730"); + } + + fall_constraint("SIG2SRAM_constraint_template") { + index_1("0.0080,0.0288,0.0616,0.1072,0.1920,0.3496,0.5952"); + index_2("0.0080,0.0288,0.0616,0.1072,0.1920,0.3496,0.5952"); + values ("0.1262,0.1457,0.1691,0.2121,0.2824,0.4191,0.6457",\ +"0.1105,0.1262,0.1496,0.1887,0.2629,0.3996,0.6262",\ +"0.0793,0.0949,0.1223,0.1652,0.2395,0.3684,0.5949",\ +"0.0363,0.0559,0.0793,0.1223,0.2004,0.3410,0.5520",\ +"-0.0457,-0.0262,0.0012,0.0441,0.1301,0.2629,0.4738",\ +"-0.1902,-0.1746,-0.1434,-0.1043,-0.0184,0.1223,0.3332",\ +"-0.4129,-0.3934,-0.3660,-0.3230,-0.2449,-0.1043,0.1105"); + } + } + + + timing() { + timing_type : hold_rising; + related_pin : "B_CLK"; + when : "B_MEN" + sdf_cond : "B_MEN" + + rise_constraint("SIG2SRAM_constraint_template") { + index_1("0.0080,0.0288,0.0616,0.1072,0.1920,0.3496,0.5952"); + index_2("0.0080,0.0288,0.0616,0.1072,0.1920,0.3496,0.5952"); + values ("0.4113,0.3918,0.3645,0.3176,0.2395,0.0988,-0.1238",\ +"0.4309,0.4113,0.3840,0.3371,0.2590,0.1184,-0.1043",\ +"0.4582,0.4387,0.4113,0.3645,0.2824,0.1457,-0.0770",\ +"0.5051,0.4816,0.4543,0.4074,0.3293,0.1887,-0.0340",\ +"0.5715,0.5598,0.5324,0.4895,0.4035,0.2512,0.0441",\ +"0.7043,0.7004,0.6730,0.6262,0.5402,0.3957,0.1809",\ +"0.9387,0.9270,0.8957,0.8527,0.7746,0.6262,0.4074"); + } + + fall_constraint("SIG2SRAM_constraint_template") { + index_1("0.0080,0.0288,0.0616,0.1072,0.1920,0.3496,0.5952"); + index_2("0.0080,0.0288,0.0616,0.1072,0.1920,0.3496,0.5952"); + values ("0.4152,0.3918,0.3645,0.3215,0.2395,0.1027,-0.1082",\ +"0.4309,0.4113,0.3801,0.3410,0.2590,0.1223,-0.0926",\ +"0.4582,0.4387,0.4074,0.3684,0.2863,0.1496,-0.0613",\ +"0.5012,0.4816,0.4504,0.4074,0.3293,0.1887,-0.0145",\ +"0.5715,0.5559,0.5285,0.4816,0.3996,0.2512,0.0598",\ +"0.7160,0.7004,0.6691,0.6262,0.5520,0.4035,0.2004",\ +"0.9387,0.9191,0.8957,0.8488,0.7707,0.6262,0.4113"); + } + } + } +pin(B_MEN) { + direction : input ; + capacitance : 0.00300347 ; + max_transition : "0.5952" ; + related_power_pin : VDD; + related_ground_pin : VSS; + internal_power() { + rise_power("scalar"){ + values (0.0161); + } + fall_power("scalar"){ + values (0.0002); + } + } + timing() { + timing_type : setup_rising; + related_pin : "B_CLK"; + + rise_constraint("SIG2SRAM_constraint_template") { + index_1("0.0080,0.0288,0.0616,0.1072,0.1920,0.3496,0.5952"); + index_2("0.0080,0.0288,0.0616,0.1072,0.1920,0.3496,0.5952"); + values ("0.3215,0.3449,0.3684,0.4113,0.4895,0.6301,0.8527",\ +"0.3059,0.3254,0.3527,0.3957,0.4738,0.6145,0.8371",\ +"0.2746,0.2941,0.3215,0.3645,0.4426,0.5871,0.8059",\ +"0.2316,0.2512,0.2785,0.3215,0.3996,0.5402,0.7629",\ +"0.1496,0.1730,0.1965,0.2395,0.3215,0.4660,0.6848",\ +"0.0090,0.0285,0.0598,0.1027,0.1809,0.3176,0.5402",\ +"-0.2098,-0.1902,-0.1668,-0.1199,-0.0418,0.0988,0.3137"); + } + + fall_constraint("SIG2SRAM_constraint_template") { + index_1("0.0080,0.0288,0.0616,0.1072,0.1920,0.3496,0.5952"); + index_2("0.0080,0.0288,0.0616,0.1072,0.1920,0.3496,0.5952"); + values ("0.4582,0.4738,0.5012,0.5363,0.6145,0.7395,0.9738",\ +"0.4387,0.4543,0.4816,0.5207,0.5910,0.7199,0.9582",\ +"0.4035,0.4230,0.4504,0.4855,0.5637,0.6887,0.9230",\ +"0.3645,0.3840,0.4074,0.4465,0.5285,0.6496,0.8840",\ +"0.2824,0.3020,0.3254,0.3645,0.4465,0.5715,0.7980",\ +"0.1418,0.1613,0.1887,0.2238,0.3020,0.4309,0.6496",\ +"-0.0770,-0.0574,-0.0301,0.0090,0.0910,0.2238,0.4191"); + } + } + + + timing() { + timing_type : hold_rising; + related_pin : "B_CLK"; + + rise_constraint("SIG2SRAM_constraint_template") { + index_1("0.0080,0.0288,0.0616,0.1072,0.1920,0.3496,0.5952"); + index_2("0.0080,0.0288,0.0616,0.1072,0.1920,0.3496,0.5952"); + values ("0.3762,0.3605,0.3293,0.2863,0.2043,0.0637,-0.1629",\ +"0.3996,0.3801,0.3488,0.3020,0.2238,0.0832,-0.1395",\ +"0.4230,0.4074,0.3723,0.3293,0.2473,0.1105,-0.1121",\ +"0.4621,0.4465,0.4152,0.3762,0.2941,0.1535,-0.0691",\ +"0.5441,0.5285,0.4973,0.4465,0.3684,0.2316,0.0090",\ +"0.6848,0.6652,0.6301,0.5910,0.5129,0.3605,0.1496",\ +"0.9074,0.8918,0.8566,0.8215,0.7395,0.5910,0.3723"); + } + + fall_constraint("SIG2SRAM_constraint_template") { + index_1("0.0080,0.0288,0.0616,0.1072,0.1920,0.3496,0.5952"); + index_2("0.0080,0.0288,0.0616,0.1072,0.1920,0.3496,0.5952"); + values ("0.3762,0.3605,0.3332,0.2863,0.2043,0.0715,-0.1395",\ +"0.3996,0.3762,0.3488,0.3059,0.2238,0.0910,-0.1199",\ +"0.4270,0.4035,0.3762,0.3332,0.2512,0.1184,-0.0965",\ +"0.4699,0.4504,0.4191,0.3762,0.2941,0.1613,-0.0496",\ +"0.5441,0.5285,0.4973,0.4543,0.3762,0.2355,0.0324",\ +"0.6770,0.6613,0.6340,0.5949,0.5207,0.3762,0.1652",\ +"0.9074,0.8918,0.8605,0.8176,0.7395,0.6027,0.3918"); + } + } + } +bus(B_BM) { + bus_type : D_15_0; + direction : input ; + capacitance : 0.00293202 ; + max_transition : "0.5952" ; + pin(B_BM[15:0]) { + related_power_pin : VDD; + related_ground_pin : VSS; + internal_power() { + when : "B_MEN"; + rise_power("scalar"){ + values (0.0469); + } + fall_power("scalar"){ + values (0.0152); + } + } + internal_power() { + when : "!B_MEN"; + rise_power("scalar"){ + values (0.0453); + } + fall_power("scalar"){ + values (0.0145); + } + } + } + timing() { + timing_type : setup_rising; + related_pin : "B_CLK"; + when : "(B_WEN & B_MEN)" + sdf_cond : "B_RW_ACCESS" + + rise_constraint("SIG2SRAM_constraint_template") { + index_1("0.0080,0.0288,0.0616,0.1072,0.1920,0.3496,0.5952"); + index_2("0.0080,0.0288,0.0616,0.1072,0.1920,0.3496,0.5952"); + values ("-0.6982,-0.6787,-0.6533,-0.6103,-0.5293,-0.3838,-0.1611",\ +"-0.7062,-0.6866,-0.6612,-0.6183,-0.5372,-0.3917,-0.1690",\ +"-0.7153,-0.6958,-0.6704,-0.6274,-0.5464,-0.4008,-0.1782",\ +"-0.7303,-0.7107,-0.6853,-0.6424,-0.5613,-0.4158,-0.1932",\ +"-0.7527,-0.7331,-0.7077,-0.6648,-0.5837,-0.4382,-0.2155",\ +"-0.7962,-0.7767,-0.7513,-0.7084,-0.6273,-0.4818,-0.2591",\ +"-0.8654,-0.8459,-0.8205,-0.7775,-0.6965,-0.5510,-0.3283"); + } + + fall_constraint("SIG2SRAM_constraint_template") { + index_1("0.0080,0.0288,0.0616,0.1072,0.1920,0.3496,0.5952"); + index_2("0.0080,0.0288,0.0616,0.1072,0.1920,0.3496,0.5952"); + values ("-0.6357,-0.6181,-0.5908,-0.5518,-0.4687,-0.3330,-0.1211",\ +"-0.6436,-0.6261,-0.5987,-0.5597,-0.4767,-0.3409,-0.1290",\ +"-0.6528,-0.6352,-0.6079,-0.5688,-0.4858,-0.3501,-0.1381",\ +"-0.6678,-0.6502,-0.6228,-0.5838,-0.5008,-0.3650,-0.1531",\ +"-0.6901,-0.6726,-0.6452,-0.6062,-0.5232,-0.3874,-0.1755",\ +"-0.7338,-0.7162,-0.6888,-0.6498,-0.5668,-0.4310,-0.2191",\ +"-0.8029,-0.7854,-0.7580,-0.7189,-0.6359,-0.5002,-0.2883"); + } + } + + + timing() { + timing_type : hold_rising; + related_pin : "B_CLK"; + when : "(B_WEN & B_MEN)" + sdf_cond : "B_RW_ACCESS" + + rise_constraint("SIG2SRAM_constraint_template") { + index_1("0.0080,0.0288,0.0616,0.1072,0.1920,0.3496,0.5952"); + index_2("0.0080,0.0288,0.0616,0.1072,0.1920,0.3496,0.5952"); + values ("0.8138,0.7924,0.7679,0.7250,0.6449,0.4984,0.2758",\ +"0.8218,0.8003,0.7759,0.7329,0.6528,0.5063,0.2837",\ +"0.8309,0.8094,0.7850,0.7420,0.6620,0.5155,0.2928",\ +"0.8459,0.8244,0.8000,0.7570,0.6769,0.5304,0.3078",\ +"0.8683,0.8468,0.8224,0.7794,0.6993,0.5528,0.3302",\ +"0.9119,0.8904,0.8660,0.8230,0.7429,0.5964,0.3738",\ +"0.9810,0.9596,0.9351,0.8922,0.8121,0.6656,0.4430"); + } + + fall_constraint("SIG2SRAM_constraint_template") { + index_1("0.0080,0.0288,0.0616,0.1072,0.1920,0.3496,0.5952"); + index_2("0.0080,0.0288,0.0616,0.1072,0.1920,0.3496,0.5952"); + values ("0.7396,0.7220,0.6947,0.6556,0.5726,0.4359,0.2250",\ +"0.7475,0.7300,0.7026,0.6636,0.5806,0.4438,0.2329",\ +"0.7567,0.7391,0.7118,0.6727,0.5897,0.4530,0.2420",\ +"0.7717,0.7541,0.7267,0.6877,0.6047,0.4679,0.2570",\ +"0.7940,0.7765,0.7491,0.7101,0.6271,0.4903,0.2794",\ +"0.8376,0.8201,0.7927,0.7537,0.6706,0.5339,0.3230",\ +"0.9068,0.8892,0.8619,0.8228,0.7398,0.6031,0.3922"); + } + } +} + pin(B_CLK) { + direction : input; + capacitance : 0.00378957; + max_transition : "0.5952"; + clock : "true" ; + pin_func_type : active_rising ; + + timing () { + timing_type : "min_pulse_width"; + related_pin : "B_CLK"; + rise_constraint("CLKTRAN_constraint_template") { + index_1("0.008,0.5952"); + values("0.4,0.4"); + } + } + + related_power_pin : VDD; + related_ground_pin : VSS; + + internal_power() { + when : "!B_MEN & !B_WEN & !B_REN"; + rise_power("scalar"){ + values (0); + } + fall_power("scalar"){ + values (0); + } + } + internal_power() { + when : "!B_MEN & B_WEN & !B_REN"; + rise_power("scalar"){ + values (0.4498); + } + fall_power("scalar"){ + values (0); + } + } + internal_power() { + when : "B_MEN & B_WEN & !B_REN"; + rise_power("scalar"){ + values (15.3644); + } + fall_power("scalar"){ + values (0); + } + } + internal_power() { + when : "B_MEN & B_WEN & B_REN"; + rise_power("scalar"){ + values (16.3884); + } + fall_power("scalar"){ + values (0); + } + } + internal_power() { + when : "B_MEN & !B_WEN & B_REN"; + rise_power("scalar"){ + values (11.8557); + } + fall_power("scalar"){ + values (0); + } + } + internal_power() { + when : "!B_MEN & !B_WEN & B_REN"; + rise_power("scalar"){ + values (0.2837); + } + fall_power("scalar"){ + values (0); + } + } + internal_power() { + when : "!B_MEN & B_WEN & B_REN"; + rise_power("scalar"){ + values (0.6730); + } + fall_power("scalar"){ + values (0); + } + } + internal_power() { + when : "B_MEN & !B_WEN & !B_REN"; + rise_power("scalar"){ + values (0); + } + fall_power("scalar"){ + values (0); + } + } + } + bus(B_DIN) { + bus_type : D_15_0; + direction : input ; + capacitance : 0.00460366 ; + memory_write() { + address : B_ADDR ; + clocked_on : B_CLK; + } + + max_transition : "0.5952" ; + pin(B_DIN[15:0]) { + related_power_pin : VDD; + related_ground_pin : VSS; + internal_power() { + when : "B_MEN"; + rise_power("scalar"){ + values (0.0469); + } + fall_power("scalar"){ + values (0.0152); + } + } + internal_power() { + when : "!B_MEN"; + rise_power("scalar"){ + values (0.0453); + } + fall_power("scalar"){ + values (0.0145); + } + } + } + timing() { + timing_type : setup_rising; + related_pin : "B_CLK"; + when : "(B_WEN & B_MEN)"; + sdf_cond : "B_W_ACCESS"; + + rise_constraint("SIG2SRAM_constraint_template") { + index_1("0.0080,0.0288,0.0616,0.1072,0.1920,0.3496,0.5952"); + index_2("0.0080,0.0288,0.0616,0.1072,0.1920,0.3496,0.5952"); + values ("-0.6982,-0.6787,-0.6533,-0.6103,-0.5293,-0.3838,-0.1611",\ +"-0.7062,-0.6866,-0.6612,-0.6183,-0.5372,-0.3917,-0.1690",\ +"-0.7153,-0.6958,-0.6704,-0.6274,-0.5464,-0.4008,-0.1782",\ +"-0.7303,-0.7107,-0.6853,-0.6424,-0.5613,-0.4158,-0.1932",\ +"-0.7527,-0.7331,-0.7077,-0.6648,-0.5837,-0.4382,-0.2155",\ +"-0.7962,-0.7767,-0.7513,-0.7084,-0.6273,-0.4818,-0.2591",\ +"-0.8654,-0.8459,-0.8205,-0.7775,-0.6965,-0.5510,-0.3283"); + } + + fall_constraint("SIG2SRAM_constraint_template") { + index_1("0.0080,0.0288,0.0616,0.1072,0.1920,0.3496,0.5952"); + index_2("0.0080,0.0288,0.0616,0.1072,0.1920,0.3496,0.5952"); + values ("-0.6357,-0.6181,-0.5908,-0.5518,-0.4687,-0.3330,-0.1211",\ +"-0.6436,-0.6261,-0.5987,-0.5597,-0.4767,-0.3409,-0.1290",\ +"-0.6528,-0.6352,-0.6079,-0.5688,-0.4858,-0.3501,-0.1381",\ +"-0.6678,-0.6502,-0.6228,-0.5838,-0.5008,-0.3650,-0.1531",\ +"-0.6901,-0.6726,-0.6452,-0.6062,-0.5232,-0.3874,-0.1755",\ +"-0.7338,-0.7162,-0.6888,-0.6498,-0.5668,-0.4310,-0.2191",\ +"-0.8029,-0.7854,-0.7580,-0.7189,-0.6359,-0.5002,-0.2883"); + } + } + + timing() { + timing_type : hold_rising; + related_pin : "B_CLK"; + when : "(B_WEN & B_MEN)"; + sdf_cond : "B_W_ACCESS"; + + rise_constraint("SIG2SRAM_constraint_template") { + index_1("0.0080,0.0288,0.0616,0.1072,0.1920,0.3496,0.5952"); + index_2("0.0080,0.0288,0.0616,0.1072,0.1920,0.3496,0.5952"); + values ("0.8138,0.7924,0.7679,0.7250,0.6449,0.4984,0.2758",\ +"0.8218,0.8003,0.7759,0.7329,0.6528,0.5063,0.2837",\ +"0.8309,0.8094,0.7850,0.7420,0.6620,0.5155,0.2928",\ +"0.8459,0.8244,0.8000,0.7570,0.6769,0.5304,0.3078",\ +"0.8683,0.8468,0.8224,0.7794,0.6993,0.5528,0.3302",\ +"0.9119,0.8904,0.8660,0.8230,0.7429,0.5964,0.3738",\ +"0.9810,0.9596,0.9351,0.8922,0.8121,0.6656,0.4430"); + } + + fall_constraint("SIG2SRAM_constraint_template") { + index_1("0.0080,0.0288,0.0616,0.1072,0.1920,0.3496,0.5952"); + index_2("0.0080,0.0288,0.0616,0.1072,0.1920,0.3496,0.5952"); + values ("0.7396,0.7220,0.6947,0.6556,0.5726,0.4359,0.2250",\ +"0.7475,0.7300,0.7026,0.6636,0.5806,0.4438,0.2329",\ +"0.7567,0.7391,0.7118,0.6727,0.5897,0.4530,0.2420",\ +"0.7717,0.7541,0.7267,0.6877,0.6047,0.4679,0.2570",\ +"0.7940,0.7765,0.7491,0.7101,0.6271,0.4903,0.2794",\ +"0.8376,0.8201,0.7927,0.7537,0.6706,0.5339,0.3230",\ +"0.9068,0.8892,0.8619,0.8228,0.7398,0.6031,0.3922"); + } + } + } + + pin(B_BIST_EN) { + direction : input ; + capacitance : 0.00387999 ; + max_transition : "1" ; + related_power_pin : VDD; + related_ground_pin : VSS; + internal_power() { + rise_power("scalar") { + values (0); + } + fall_power("scalar") { + values (0); + } + } + } + +bus(B_BIST_ADDR) { + bus_type : A_7_0; + direction : input ; + capacitance : 0.0129586 ; + pin(B_BIST_ADDR[0]) { + capacitance : 0.00588404 ; + } + pin(B_BIST_ADDR[1]) { + capacitance : 0.0080425 ; + } + pin(B_BIST_ADDR[2]) { + capacitance : 0.0112051 ; + } + pin(B_BIST_ADDR[3]) { + capacitance : 0.00706428 ; + } + pin(B_BIST_ADDR[4]) { + capacitance : 0.00656149 ; + } + pin(B_BIST_ADDR[5]) { + capacitance : 0.0111839 ; + } + pin(B_BIST_ADDR[6]) { + capacitance : 0.0140236 ; + } + max_transition : "0.5952" ; + pin(B_BIST_ADDR[7:0]) { + related_power_pin : VDD; + related_ground_pin : VSS; + internal_power() { + when : "B_BIST_MEN"; + rise_power("scalar"){ + values (0.0102); + } + fall_power("scalar"){ + values (0.0077); + } + } + internal_power() { + when : "!B_BIST_MEN"; + rise_power("scalar"){ + values (0.0150); + } + fall_power("scalar"){ + values (0.0029); + } + } + } + timing() { + timing_type : setup_rising; + related_pin : "B_BIST_CLK"; + when : "((B_BIST_WEN | B_BIST_REN)& B_BIST_MEN)" + sdf_cond : "B_BIST_RW_ACCESS" + + rise_constraint("SIG2SRAM_constraint_template") { + index_1("0.0080,0.0288,0.0616,0.1072,0.1920,0.3496,0.5952"); + index_2("0.0080,0.0288,0.0616,0.1072,0.1920,0.3496,0.5952"); + values ("-0.7371,-0.7176,-0.6863,-0.6434,-0.5652,-0.4168,-0.1980",\ +"-0.7566,-0.7371,-0.7059,-0.6629,-0.5848,-0.4363,-0.2137",\ +"-0.7879,-0.7645,-0.7332,-0.6902,-0.6121,-0.4637,-0.2449",\ +"-0.8309,-0.8074,-0.7762,-0.7332,-0.6551,-0.5066,-0.2879",\ +"-0.9051,-0.8895,-0.8543,-0.8113,-0.7332,-0.5887,-0.3660",\ +"-1.0418,-1.0262,-0.9949,-0.9480,-0.8699,-0.7293,-0.5027",\ +"-1.2684,-1.2449,-1.2176,-1.1707,-1.0965,-0.9480,-0.7293"); + } + + fall_constraint("SIG2SRAM_constraint_template") { + index_1("0.0080,0.0288,0.0616,0.1072,0.1920,0.3496,0.5952"); + index_2("0.0080,0.0288,0.0616,0.1072,0.1920,0.3496,0.5952"); + values ("-0.5926,-0.5730,-0.5418,-0.4988,-0.4246,-0.2879,-0.0730",\ +"-0.6121,-0.5926,-0.5613,-0.5223,-0.4441,-0.3074,-0.0887",\ +"-0.6395,-0.6199,-0.5926,-0.5496,-0.4715,-0.3348,-0.1160",\ +"-0.6863,-0.6668,-0.6355,-0.5965,-0.5184,-0.3777,-0.1590",\ +"-0.7605,-0.7410,-0.7137,-0.6746,-0.5926,-0.4559,-0.2410",\ +"-0.9012,-0.8816,-0.8504,-0.8113,-0.7332,-0.5926,-0.3895",\ +"-1.1238,-1.1043,-1.0769,-1.0379,-0.9559,-0.8191,-0.6004"); + } + } + + + timing() { + timing_type : hold_rising; + related_pin : "B_BIST_CLK"; + when : "((B_BIST_WEN | B_BIST_REN)& B_BIST_MEN)" + sdf_cond : "B_BIST_RW_ACCESS" + + rise_constraint("SIG2SRAM_constraint_template") { + index_1("0.0080,0.0288,0.0616,0.1072,0.1920,0.3496,0.5952"); + index_2("0.0080,0.0288,0.0616,0.1072,0.1920,0.3496,0.5952"); + values ("0.8488,0.8293,0.7980,0.7551,0.6730,0.5285,0.3059",\ +"0.8684,0.8488,0.8176,0.7746,0.6926,0.5480,0.3254",\ +"0.8996,0.8801,0.8449,0.8020,0.7238,0.5754,0.3527",\ +"0.9426,0.9191,0.8918,0.8488,0.7668,0.6223,0.3996",\ +"1.0168,1.0012,0.9699,0.9230,0.8449,0.7004,0.4777",\ +"1.1574,1.1379,1.1105,1.0598,0.9816,0.8371,0.6184",\ +"1.3801,1.3605,1.3254,1.2980,1.2043,1.0637,0.8371"); + } + + fall_constraint("SIG2SRAM_constraint_template") { + index_1("0.0080,0.0288,0.0616,0.1072,0.1920,0.3496,0.5952"); + index_2("0.0080,0.0288,0.0616,0.1072,0.1920,0.3496,0.5952"); + values ("0.6965,0.6770,0.6496,0.6066,0.5246,0.3918,0.1730",\ +"0.7160,0.6965,0.6652,0.6262,0.5441,0.4113,0.1965",\ +"0.7473,0.7277,0.6965,0.6535,0.5754,0.4426,0.2238",\ +"0.7863,0.7707,0.7395,0.7004,0.6223,0.4855,0.2629",\ +"0.8684,0.8449,0.8176,0.7785,0.7004,0.5637,0.3449",\ +"1.0051,0.9855,0.9855,0.9113,0.8332,0.7004,0.4895",\ +"1.2277,1.2082,1.1809,1.1379,1.0598,0.9230,0.7004"); + } + } +} +pin(B_BIST_WEN) { + direction : input ; + capacitance : 0.00313551 ; + max_transition : "0.5952" ; + related_power_pin : VDD; + related_ground_pin : VSS; + internal_power() { + when : "B_BIST_MEN"; + rise_power("scalar"){ + values (0.0036); + } + fall_power("scalar"){ + values (0.0007); + } + } + internal_power() { + when : "!B_BIST_MEN"; + rise_power("scalar"){ + values (0.0050); + } + fall_power("scalar"){ + values (0.0002); + } + } + timing() { + timing_type : setup_rising; + related_pin : "B_BIST_CLK"; + when : "B_BIST_MEN" + sdf_cond : "B_BIST_MEN" + + rise_constraint("SIG2SRAM_constraint_template") { + index_1("0.0080,0.0288,0.0616,0.1072,0.1920,0.3496,0.5952"); + index_2("0.0080,0.0288,0.0616,0.1072,0.1920,0.3496,0.5952"); + values ("0.3137,0.3332,0.3605,0.4035,0.4816,0.6223,0.8488",\ +"0.2980,0.3176,0.3410,0.3840,0.4660,0.6027,0.8293",\ +"0.2629,0.2824,0.3098,0.3527,0.4348,0.5754,0.7980",\ +"0.2199,0.2395,0.2668,0.3098,0.3918,0.5324,0.7590",\ +"0.1418,0.1613,0.1887,0.2316,0.3137,0.4348,0.6730",\ +"0.0012,0.0207,0.0520,0.0910,0.1730,0.3098,0.5285",\ +"-0.2215,-0.2020,-0.1746,-0.1277,-0.0496,0.0910,0.3098"); + } + + fall_constraint("SIG2SRAM_constraint_template") { + index_1("0.0080,0.0288,0.0616,0.1072,0.1920,0.3496,0.5952"); + index_2("0.0080,0.0288,0.0616,0.1072,0.1920,0.3496,0.5952"); + values ("0.4504,0.4699,0.4973,0.5324,0.6027,0.7355,0.9699",\ +"0.4309,0.4504,0.4777,0.5129,0.5910,0.7160,0.9504",\ +"0.3996,0.4191,0.4465,0.4816,0.5520,0.6848,0.9191",\ +"0.3605,0.3762,0.4035,0.4387,0.5168,0.6418,0.8723",\ +"0.2785,0.2980,0.3215,0.3605,0.4348,0.5637,0.7980",\ +"0.1379,0.1574,0.1809,0.2199,0.2980,0.4309,0.6457",\ +"-0.0809,-0.0613,-0.0340,0.0051,0.0832,0.2160,0.4191"); + } + } + + + timing() { + timing_type : hold_rising; + related_pin : "B_BIST_CLK"; + when : "B_BIST_MEN" + sdf_cond : "B_BIST_MEN" + + rise_constraint("SIG2SRAM_constraint_template") { + index_1("0.0080,0.0288,0.0616,0.1072,0.1920,0.3496,0.5952"); + index_2("0.0080,0.0288,0.0616,0.1072,0.1920,0.3496,0.5952"); + values ("0.3723,0.3527,0.3215,0.2785,0.1965,0.0559,-0.1668",\ +"0.3918,0.3723,0.3449,0.2980,0.2160,0.0754,-0.1473",\ +"0.4152,0.3996,0.3684,0.3254,0.2434,0.1066,-0.1199",\ +"0.4621,0.4465,0.4152,0.3723,0.2863,0.1496,-0.0730",\ +"0.5324,0.5207,0.4895,0.4465,0.3645,0.2199,0.0051",\ +"0.6770,0.6535,0.6301,0.5832,0.5090,0.3605,0.1418",\ +"0.9035,0.8879,0.8566,0.8137,0.7316,0.5871,0.3684"); + } + + fall_constraint("SIG2SRAM_constraint_template") { + index_1("0.0080,0.0288,0.0616,0.1072,0.1920,0.3496,0.5952"); + index_2("0.0080,0.0288,0.0616,0.1072,0.1920,0.3496,0.5952"); + values ("0.3762,0.3566,0.3293,0.2863,0.2043,0.0676,-0.1434",\ +"0.3957,0.3762,0.3488,0.3059,0.2238,0.0871,-0.1199",\ +"0.4230,0.4035,0.3723,0.3332,0.2512,0.1184,-0.0965",\ +"0.4660,0.4465,0.4191,0.3762,0.2941,0.1613,-0.0496",\ +"0.5324,0.5168,0.4973,0.4543,0.3723,0.2316,0.0285",\ +"0.6809,0.6613,0.6340,0.5910,0.5129,0.3645,0.1652",\ +"0.9113,0.8918,0.8605,0.8176,0.7395,0.5988,0.3879"); + } + } + } +pin(B_BIST_REN) { + direction : input ; + capacitance : 0.00381144 ; + max_transition : "0.5952" ; + related_power_pin : VDD; + related_ground_pin : VSS; + internal_power() { + when : "B_BIST_MEN"; + rise_power("scalar"){ + values (0.0040); + } + fall_power("scalar"){ + values (0.0015); + } + } + internal_power() { + when : "!B_BIST_MEN"; + rise_power("scalar"){ + values (0.0040); + } + fall_power("scalar"){ + values (0.0013); + } + } + timing() { + timing_type : setup_rising; + related_pin : "B_BIST_CLK"; + when : "B_BIST_MEN" + sdf_cond : "B_BIST_MEN" + + rise_constraint("SIG2SRAM_constraint_template") { + index_1("0.0080,0.0288,0.0616,0.1072,0.1920,0.3496,0.5952"); + index_2("0.0080,0.0288,0.0616,0.1072,0.1920,0.3496,0.5952"); + values ("-0.0770,-0.0574,-0.0262,0.0168,0.0949,0.2355,0.4582",\ +"-0.0965,-0.0770,-0.0457,-0.0027,0.0754,0.2160,0.4387",\ +"-0.1199,-0.1004,-0.0730,-0.0262,0.0520,0.1887,0.4113",\ +"-0.1590,-0.1434,-0.1160,-0.0730,0.0051,0.1457,0.3645",\ +"-0.2449,-0.2254,-0.1941,-0.1473,-0.0770,0.0676,0.2863",\ +"-0.3816,-0.3699,-0.3387,-0.2801,-0.2215,-0.0770,0.1457",\ +"-0.6121,-0.5926,-0.5613,-0.5145,-0.4363,-0.2996,-0.0730"); + } + + fall_constraint("SIG2SRAM_constraint_template") { + index_1("0.0080,0.0288,0.0616,0.1072,0.1920,0.3496,0.5952"); + index_2("0.0080,0.0288,0.0616,0.1072,0.1920,0.3496,0.5952"); + values ("0.1262,0.1457,0.1691,0.2121,0.2824,0.4191,0.6457",\ +"0.1105,0.1262,0.1496,0.1887,0.2629,0.3996,0.6262",\ +"0.0793,0.0949,0.1223,0.1652,0.2395,0.3684,0.5949",\ +"0.0363,0.0559,0.0793,0.1223,0.2004,0.3410,0.5520",\ +"-0.0457,-0.0262,0.0012,0.0441,0.1301,0.2629,0.4738",\ +"-0.1902,-0.1746,-0.1434,-0.1043,-0.0184,0.1223,0.3332",\ +"-0.4129,-0.3934,-0.3660,-0.3230,-0.2449,-0.1043,0.1105"); + } + } + + + timing() { + timing_type : hold_rising; + related_pin : "B_BIST_CLK"; + when : "B_BIST_MEN" + sdf_cond : "B_BIST_MEN" + + rise_constraint("SIG2SRAM_constraint_template") { + index_1("0.0080,0.0288,0.0616,0.1072,0.1920,0.3496,0.5952"); + index_2("0.0080,0.0288,0.0616,0.1072,0.1920,0.3496,0.5952"); + values ("0.4113,0.3918,0.3645,0.3176,0.2395,0.0988,-0.1238",\ +"0.4309,0.4113,0.3840,0.3371,0.2590,0.1184,-0.1043",\ +"0.4582,0.4387,0.4113,0.3645,0.2824,0.1457,-0.0770",\ +"0.5051,0.4816,0.4543,0.4074,0.3293,0.1887,-0.0340",\ +"0.5715,0.5598,0.5324,0.4895,0.4035,0.2512,0.0441",\ +"0.7043,0.7004,0.6730,0.6262,0.5402,0.3957,0.1809",\ +"0.9387,0.9270,0.8957,0.8527,0.7746,0.6262,0.4074"); + } + + fall_constraint("SIG2SRAM_constraint_template") { + index_1("0.0080,0.0288,0.0616,0.1072,0.1920,0.3496,0.5952"); + index_2("0.0080,0.0288,0.0616,0.1072,0.1920,0.3496,0.5952"); + values ("0.4152,0.3918,0.3645,0.3215,0.2395,0.1027,-0.1082",\ +"0.4309,0.4113,0.3801,0.3410,0.2590,0.1223,-0.0926",\ +"0.4582,0.4387,0.4074,0.3684,0.2863,0.1496,-0.0613",\ +"0.5012,0.4816,0.4504,0.4074,0.3293,0.1887,-0.0145",\ +"0.5715,0.5559,0.5285,0.4816,0.3996,0.2512,0.0598",\ +"0.7160,0.7004,0.6691,0.6262,0.5520,0.4035,0.2004",\ +"0.9387,0.9191,0.8957,0.8488,0.7707,0.6262,0.4113"); + } + } + } +pin(B_BIST_MEN) { + direction : input ; + capacitance : 0.00300347 ; + max_transition : "0.5952" ; + related_power_pin : VDD; + related_ground_pin : VSS; + internal_power() { + rise_power("scalar"){ + values (0.0161); + } + fall_power("scalar"){ + values (0.0002); + } + } + timing() { + timing_type : setup_rising; + related_pin : "B_BIST_CLK"; + + rise_constraint("SIG2SRAM_constraint_template") { + index_1("0.0080,0.0288,0.0616,0.1072,0.1920,0.3496,0.5952"); + index_2("0.0080,0.0288,0.0616,0.1072,0.1920,0.3496,0.5952"); + values ("0.3215,0.3449,0.3684,0.4113,0.4895,0.6301,0.8527",\ +"0.3059,0.3254,0.3527,0.3957,0.4738,0.6145,0.8371",\ +"0.2746,0.2941,0.3215,0.3645,0.4426,0.5871,0.8059",\ +"0.2316,0.2512,0.2785,0.3215,0.3996,0.5402,0.7629",\ +"0.1496,0.1730,0.1965,0.2395,0.3215,0.4660,0.6848",\ +"0.0090,0.0285,0.0598,0.1027,0.1809,0.3176,0.5402",\ +"-0.2098,-0.1902,-0.1668,-0.1199,-0.0418,0.0988,0.3137"); + } + + fall_constraint("SIG2SRAM_constraint_template") { + index_1("0.0080,0.0288,0.0616,0.1072,0.1920,0.3496,0.5952"); + index_2("0.0080,0.0288,0.0616,0.1072,0.1920,0.3496,0.5952"); + values ("0.4582,0.4738,0.5012,0.5363,0.6145,0.7395,0.9738",\ +"0.4387,0.4543,0.4816,0.5207,0.5910,0.7199,0.9582",\ +"0.4035,0.4230,0.4504,0.4855,0.5637,0.6887,0.9230",\ +"0.3645,0.3840,0.4074,0.4465,0.5285,0.6496,0.8840",\ +"0.2824,0.3020,0.3254,0.3645,0.4465,0.5715,0.7980",\ +"0.1418,0.1613,0.1887,0.2238,0.3020,0.4309,0.6496",\ +"-0.0770,-0.0574,-0.0301,0.0090,0.0910,0.2238,0.4191"); + } + } + + + timing() { + timing_type : hold_rising; + related_pin : "B_BIST_CLK"; + + rise_constraint("SIG2SRAM_constraint_template") { + index_1("0.0080,0.0288,0.0616,0.1072,0.1920,0.3496,0.5952"); + index_2("0.0080,0.0288,0.0616,0.1072,0.1920,0.3496,0.5952"); + values ("0.3762,0.3605,0.3293,0.2863,0.2043,0.0637,-0.1629",\ +"0.3996,0.3801,0.3488,0.3020,0.2238,0.0832,-0.1395",\ +"0.4230,0.4074,0.3723,0.3293,0.2473,0.1105,-0.1121",\ +"0.4621,0.4465,0.4152,0.3762,0.2941,0.1535,-0.0691",\ +"0.5441,0.5285,0.4973,0.4465,0.3684,0.2316,0.0090",\ +"0.6848,0.6652,0.6301,0.5910,0.5129,0.3605,0.1496",\ +"0.9074,0.8918,0.8566,0.8215,0.7395,0.5910,0.3723"); + } + + fall_constraint("SIG2SRAM_constraint_template") { + index_1("0.0080,0.0288,0.0616,0.1072,0.1920,0.3496,0.5952"); + index_2("0.0080,0.0288,0.0616,0.1072,0.1920,0.3496,0.5952"); + values ("0.3762,0.3605,0.3332,0.2863,0.2043,0.0715,-0.1395",\ +"0.3996,0.3762,0.3488,0.3059,0.2238,0.0910,-0.1199",\ +"0.4270,0.4035,0.3762,0.3332,0.2512,0.1184,-0.0965",\ +"0.4699,0.4504,0.4191,0.3762,0.2941,0.1613,-0.0496",\ +"0.5441,0.5285,0.4973,0.4543,0.3762,0.2355,0.0324",\ +"0.6770,0.6613,0.6340,0.5949,0.5207,0.3762,0.1652",\ +"0.9074,0.8918,0.8605,0.8176,0.7395,0.6027,0.3918"); + } + } + } +bus(B_BIST_BM) { + bus_type : D_15_0; + direction : input ; + capacitance : 0.00261869 ; + max_transition : "0.5952" ; + pin(B_BIST_BM[15:0]) { + related_power_pin : VDD; + related_ground_pin : VSS; + internal_power() { + when : "B_BIST_MEN"; + rise_power("scalar"){ + values (0.0469); + } + fall_power("scalar"){ + values (0.0152); + } + } + internal_power() { + when : "!B_BIST_MEN"; + rise_power("scalar"){ + values (0.0453); + } + fall_power("scalar"){ + values (0.0145); + } + } + } + timing() { + timing_type : setup_rising; + related_pin : "B_BIST_CLK"; + when : "(B_BIST_WEN & B_BIST_MEN)" + sdf_cond : "B_BIST_RW_ACCESS" + + rise_constraint("SIG2SRAM_constraint_template") { + index_1("0.0080,0.0288,0.0616,0.1072,0.1920,0.3496,0.5952"); + index_2("0.0080,0.0288,0.0616,0.1072,0.1920,0.3496,0.5952"); + values ("-0.6982,-0.6787,-0.6533,-0.6103,-0.5293,-0.3838,-0.1611",\ +"-0.7062,-0.6866,-0.6612,-0.6183,-0.5372,-0.3917,-0.1690",\ +"-0.7153,-0.6958,-0.6704,-0.6274,-0.5464,-0.4008,-0.1782",\ +"-0.7303,-0.7107,-0.6853,-0.6424,-0.5613,-0.4158,-0.1932",\ +"-0.7527,-0.7331,-0.7077,-0.6648,-0.5837,-0.4382,-0.2155",\ +"-0.7962,-0.7767,-0.7513,-0.7084,-0.6273,-0.4818,-0.2591",\ +"-0.8654,-0.8459,-0.8205,-0.7775,-0.6965,-0.5510,-0.3283"); + } + + fall_constraint("SIG2SRAM_constraint_template") { + index_1("0.0080,0.0288,0.0616,0.1072,0.1920,0.3496,0.5952"); + index_2("0.0080,0.0288,0.0616,0.1072,0.1920,0.3496,0.5952"); + values ("-0.6357,-0.6181,-0.5908,-0.5518,-0.4687,-0.3330,-0.1211",\ +"-0.6436,-0.6261,-0.5987,-0.5597,-0.4767,-0.3409,-0.1290",\ +"-0.6528,-0.6352,-0.6079,-0.5688,-0.4858,-0.3501,-0.1381",\ +"-0.6678,-0.6502,-0.6228,-0.5838,-0.5008,-0.3650,-0.1531",\ +"-0.6901,-0.6726,-0.6452,-0.6062,-0.5232,-0.3874,-0.1755",\ +"-0.7338,-0.7162,-0.6888,-0.6498,-0.5668,-0.4310,-0.2191",\ +"-0.8029,-0.7854,-0.7580,-0.7189,-0.6359,-0.5002,-0.2883"); + } + } + + + timing() { + timing_type : hold_rising; + related_pin : "B_BIST_CLK"; + when : "(B_BIST_WEN & B_BIST_MEN)" + sdf_cond : "B_BIST_RW_ACCESS" + + rise_constraint("SIG2SRAM_constraint_template") { + index_1("0.0080,0.0288,0.0616,0.1072,0.1920,0.3496,0.5952"); + index_2("0.0080,0.0288,0.0616,0.1072,0.1920,0.3496,0.5952"); + values ("0.8138,0.7924,0.7679,0.7250,0.6449,0.4984,0.2758",\ +"0.8218,0.8003,0.7759,0.7329,0.6528,0.5063,0.2837",\ +"0.8309,0.8094,0.7850,0.7420,0.6620,0.5155,0.2928",\ +"0.8459,0.8244,0.8000,0.7570,0.6769,0.5304,0.3078",\ +"0.8683,0.8468,0.8224,0.7794,0.6993,0.5528,0.3302",\ +"0.9119,0.8904,0.8660,0.8230,0.7429,0.5964,0.3738",\ +"0.9810,0.9596,0.9351,0.8922,0.8121,0.6656,0.4430"); + } + + fall_constraint("SIG2SRAM_constraint_template") { + index_1("0.0080,0.0288,0.0616,0.1072,0.1920,0.3496,0.5952"); + index_2("0.0080,0.0288,0.0616,0.1072,0.1920,0.3496,0.5952"); + values ("0.7396,0.7220,0.6947,0.6556,0.5726,0.4359,0.2250",\ +"0.7475,0.7300,0.7026,0.6636,0.5806,0.4438,0.2329",\ +"0.7567,0.7391,0.7118,0.6727,0.5897,0.4530,0.2420",\ +"0.7717,0.7541,0.7267,0.6877,0.6047,0.4679,0.2570",\ +"0.7940,0.7765,0.7491,0.7101,0.6271,0.4903,0.2794",\ +"0.8376,0.8201,0.7927,0.7537,0.6706,0.5339,0.3230",\ +"0.9068,0.8892,0.8619,0.8228,0.7398,0.6031,0.3922"); + } + } +} + pin(B_BIST_CLK) { + direction : input; + capacitance : 0.00378957; + max_transition : "0.5952"; + clock : "true" ; + pin_func_type : active_rising ; + + timing () { + timing_type : "min_pulse_width"; + related_pin : "B_BIST_CLK"; + rise_constraint("CLKTRAN_constraint_template") { + index_1("0.008,0.5952"); + values("0.4,0.4"); + } + } + + related_power_pin : VDD; + related_ground_pin : VSS; + + internal_power() { + when : "!B_BIST_MEN & !B_BIST_WEN & !B_BIST_REN"; + rise_power("scalar"){ + values (0); + } + fall_power("scalar"){ + values (0); + } + } + internal_power() { + when : "!B_BIST_MEN & B_BIST_WEN & !B_BIST_REN"; + rise_power("scalar"){ + values (0.4498); + } + fall_power("scalar"){ + values (0); + } + } + internal_power() { + when : "B_BIST_MEN & B_BIST_WEN & !B_BIST_REN"; + rise_power("scalar"){ + values (15.3644); + } + fall_power("scalar"){ + values (0); + } + } + internal_power() { + when : "B_BIST_MEN & B_BIST_WEN & B_BIST_REN"; + rise_power("scalar"){ + values (16.3884); + } + fall_power("scalar"){ + values (0); + } + } + internal_power() { + when : "B_BIST_MEN & !B_BIST_WEN & B_BIST_REN"; + rise_power("scalar"){ + values (11.8557); + } + fall_power("scalar"){ + values (0); + } + } + internal_power() { + when : "!B_BIST_MEN & !B_BIST_WEN & B_BIST_REN"; + rise_power("scalar"){ + values (0.2837); + } + fall_power("scalar"){ + values (0); + } + } + internal_power() { + when : "!B_BIST_MEN & B_BIST_WEN & B_BIST_REN"; + rise_power("scalar"){ + values (0.6730); + } + fall_power("scalar"){ + values (0); + } + } + internal_power() { + when : "B_BIST_MEN & !B_BIST_WEN & !B_BIST_REN"; + rise_power("scalar"){ + values (0); + } + fall_power("scalar"){ + values (0); + } + } + } + bus(B_BIST_DIN) { + bus_type : D_15_0; + direction : input ; + capacitance : 0.00416317 ; + memory_write() { + address : B_BIST_ADDR ; + clocked_on : B_BIST_CLK; + } + + max_transition : "0.5952" ; + pin(B_BIST_DIN[15:0]) { + related_power_pin : VDD; + related_ground_pin : VSS; + internal_power() { + when : "B_BIST_MEN"; + rise_power("scalar"){ + values (0.0469); + } + fall_power("scalar"){ + values (0.0152); + } + } + internal_power() { + when : "!B_BIST_MEN"; + rise_power("scalar"){ + values (0.0453); + } + fall_power("scalar"){ + values (0.0145); + } + } + } + timing() { + timing_type : setup_rising; + related_pin : "B_BIST_CLK"; + when : "(B_BIST_WEN & B_BIST_MEN)"; + sdf_cond : "B_BIST_W_ACCESS"; + + rise_constraint("SIG2SRAM_constraint_template") { + index_1("0.0080,0.0288,0.0616,0.1072,0.1920,0.3496,0.5952"); + index_2("0.0080,0.0288,0.0616,0.1072,0.1920,0.3496,0.5952"); + values ("-0.6982,-0.6787,-0.6533,-0.6103,-0.5293,-0.3838,-0.1611",\ +"-0.7062,-0.6866,-0.6612,-0.6183,-0.5372,-0.3917,-0.1690",\ +"-0.7153,-0.6958,-0.6704,-0.6274,-0.5464,-0.4008,-0.1782",\ +"-0.7303,-0.7107,-0.6853,-0.6424,-0.5613,-0.4158,-0.1932",\ +"-0.7527,-0.7331,-0.7077,-0.6648,-0.5837,-0.4382,-0.2155",\ +"-0.7962,-0.7767,-0.7513,-0.7084,-0.6273,-0.4818,-0.2591",\ +"-0.8654,-0.8459,-0.8205,-0.7775,-0.6965,-0.5510,-0.3283"); + } + + fall_constraint("SIG2SRAM_constraint_template") { + index_1("0.0080,0.0288,0.0616,0.1072,0.1920,0.3496,0.5952"); + index_2("0.0080,0.0288,0.0616,0.1072,0.1920,0.3496,0.5952"); + values ("-0.6357,-0.6181,-0.5908,-0.5518,-0.4687,-0.3330,-0.1211",\ +"-0.6436,-0.6261,-0.5987,-0.5597,-0.4767,-0.3409,-0.1290",\ +"-0.6528,-0.6352,-0.6079,-0.5688,-0.4858,-0.3501,-0.1381",\ +"-0.6678,-0.6502,-0.6228,-0.5838,-0.5008,-0.3650,-0.1531",\ +"-0.6901,-0.6726,-0.6452,-0.6062,-0.5232,-0.3874,-0.1755",\ +"-0.7338,-0.7162,-0.6888,-0.6498,-0.5668,-0.4310,-0.2191",\ +"-0.8029,-0.7854,-0.7580,-0.7189,-0.6359,-0.5002,-0.2883"); + } + } + + timing() { + timing_type : hold_rising; + related_pin : "B_BIST_CLK"; + when : "(B_BIST_WEN & B_BIST_MEN)"; + sdf_cond : "B_BIST_W_ACCESS"; + + rise_constraint("SIG2SRAM_constraint_template") { + index_1("0.0080,0.0288,0.0616,0.1072,0.1920,0.3496,0.5952"); + index_2("0.0080,0.0288,0.0616,0.1072,0.1920,0.3496,0.5952"); + values ("0.8138,0.7924,0.7679,0.7250,0.6449,0.4984,0.2758",\ +"0.8218,0.8003,0.7759,0.7329,0.6528,0.5063,0.2837",\ +"0.8309,0.8094,0.7850,0.7420,0.6620,0.5155,0.2928",\ +"0.8459,0.8244,0.8000,0.7570,0.6769,0.5304,0.3078",\ +"0.8683,0.8468,0.8224,0.7794,0.6993,0.5528,0.3302",\ +"0.9119,0.8904,0.8660,0.8230,0.7429,0.5964,0.3738",\ +"0.9810,0.9596,0.9351,0.8922,0.8121,0.6656,0.4430"); + } + + fall_constraint("SIG2SRAM_constraint_template") { + index_1("0.0080,0.0288,0.0616,0.1072,0.1920,0.3496,0.5952"); + index_2("0.0080,0.0288,0.0616,0.1072,0.1920,0.3496,0.5952"); + values ("0.7396,0.7220,0.6947,0.6556,0.5726,0.4359,0.2250",\ +"0.7475,0.7300,0.7026,0.6636,0.5806,0.4438,0.2329",\ +"0.7567,0.7391,0.7118,0.6727,0.5897,0.4530,0.2420",\ +"0.7717,0.7541,0.7267,0.6877,0.6047,0.4679,0.2570",\ +"0.7940,0.7765,0.7491,0.7101,0.6271,0.4903,0.2794",\ +"0.8376,0.8201,0.7927,0.7537,0.6706,0.5339,0.3230",\ +"0.9068,0.8892,0.8619,0.8228,0.7398,0.6031,0.3922"); + } + } + } + +bus(B_DOUT) { + + bus_type : D_15_0; + direction : output ; + capacitance : 0 ; + max_capacitance : 0.064 ; + memory_read() { + address : B_ADDR ; + } + pin(B_DOUT[15:0]) { + related_power_pin : VDD; + related_ground_pin : VSS; + internal_power() { + rise_power("scalar") { + values (0); + } + fall_power("scalar") { + values (0); + } + } + } + timing() { + related_pin : "B_CLK"; + timing_type : rising_edge ; + timing_sense : non_unate ; + + cell_rise(SIG2SRAM_delay_template) { + index_1("0.0080,0.0288,0.0616,0.1072,0.1920,0.3496,0.5952"); + index_2("0.0008,0.0014,0.0051,0.0100,0.0339,0.0640"); + values ("5.0746,5.0780,5.0902,5.1041,5.1567,5.2145",\ +"5.0885,5.0919,5.1041,5.1180,5.1706,5.2284",\ +"5.0984,5.1017,5.1139,5.1279,5.1804,5.2383",\ +"5.1117,5.1150,5.1272,5.1412,5.1937,5.2516",\ +"5.1349,5.1383,5.1505,5.1644,5.2170,5.2748",\ +"5.1797,5.1831,5.1952,5.2092,5.2617,5.3196",\ +"5.2469,5.2503,5.2625,5.2764,5.3290,5.3868"); + } + cell_fall(SIG2SRAM_delay_template) { + index_1("0.0080,0.0288,0.0616,0.1072,0.1920,0.3496,0.5952"); + index_2("0.0008,0.0014,0.0051,0.0100,0.0339,0.0640"); + values ("4.9649,4.9671,4.9771,4.9888,5.0321,5.0760",\ +"4.9788,4.9810,4.9910,5.0027,5.0460,5.0899",\ +"4.9887,4.9908,5.0009,5.0125,5.0559,5.0997",\ +"5.0019,5.0041,5.0142,5.0258,5.0692,5.1130",\ +"5.0252,5.0274,5.0374,5.0491,5.0924,5.1363",\ +"5.0700,5.0721,5.0822,5.0939,5.1372,5.1810",\ +"5.1372,5.1394,5.1494,5.1611,5.2045,5.2483"); + } + + rise_transition(SRAM_load_template) { + index_1("0.0008,0.0014,0.0051,0.0100,0.0339,0.0640"); + values ("0.0560,0.0583,0.0696,0.0816,0.1519,0.2335"); + } + fall_transition(SRAM_load_template) { + index_1("0.0008,0.0014,0.0051,0.0100,0.0339,0.0640"); + values ("0.0428,0.0445,0.0538,0.0658,0.1181,0.1751"); + } + } +} +cell_leakage_power : 476.5786; +} +} diff --git a/flow/platforms/ihp-sg13g2/lib/RM_IHPSG13_2P_256x16_c2_bm_bist_typ_1p20V_25C.lib b/flow/platforms/ihp-sg13g2/lib/RM_IHPSG13_2P_256x16_c2_bm_bist_typ_1p20V_25C.lib new file mode 100644 index 0000000000..7720acce70 --- /dev/null +++ b/flow/platforms/ihp-sg13g2/lib/RM_IHPSG13_2P_256x16_c2_bm_bist_typ_1p20V_25C.lib @@ -0,0 +1,2874 @@ +/* ------------------------------------------------------*/ +/**/ +/* Copyright 2025 IHP PDK Authors*/ +/**/ +/* Licensed under the Apache License, Version 2.0 (the "License");*/ +/* you may not use this file except in compliance with the License.*/ +/* You may obtain a copy of the License at*/ +/* */ +/* https://www.apache.org/licenses/LICENSE-2.0*/ +/* */ +/* Unless required by applicable law or agreed to in writing, software*/ +/* distributed under the License is distributed on an "AS IS" BASIS,*/ +/* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.*/ +/* See the License for the specific language governing permissions and*/ +/* limitations under the License.*/ +/* */ +/* Generated on Wed Aug 27 13:19:42 2025 */ +/* */ +/* ------------------------------------------------------ */ +library(RM_IHPSG13_2P_256x16_c2_bm_bist_typ_1p20V_25C) { + technology (cmos) ; + delay_model : table_lookup ; + define ("add_pg_pin_to_lib", "library", "boolean"); + add_pg_pin_to_lib : true; + voltage_map ( VDD, 1.20); + voltage_map ( VDDARRAY, 1.20); + voltage_map ( VSS, 0.000000 ); + + date : "Wed Aug 27 13:19:39 2025" ; + comment : "IHP Microelectronics GmbH, 2023" ; + revision : 1.0.0 ; + simulation : true ; + nom_process : 1 ; + nom_temperature : 25 ; + nom_voltage : 1.20 ; + + operating_conditions("typ_1p20V_25C"){ + process : 1 ; + temperature : 25 ; + voltage : 1.20 ; + tree_type : "balanced_tree" ; + } + + default_operating_conditions : typ_1p20V_25C ; + default_max_transition : 1.0 ; + default_fanout_load : 1.0 ; + default_inout_pin_cap : 0.0 ; + default_input_pin_cap : 0.0 ; + default_output_pin_cap : 0.0 ; + default_cell_leakage_power : 0.0 ; + default_leakage_power_density : 0.0 ; + + slew_lower_threshold_pct_rise : 30 ; + slew_upper_threshold_pct_rise : 70 ; + input_threshold_pct_fall : 50 ; + output_threshold_pct_fall : 50 ; + input_threshold_pct_rise : 50 ; + output_threshold_pct_rise : 50 ; + slew_lower_threshold_pct_fall : 30 ; + slew_upper_threshold_pct_fall : 70 ; + slew_derate_from_library : 0.5; + k_volt_cell_leakage_power : 0.0 ; + k_temp_cell_leakage_power : 0.0 ; + k_process_cell_leakage_power : 0.0 ; + k_volt_internal_power : 0.0 ; + k_temp_internal_power : 0.0 ; + k_process_internal_power : 0.0 ; + + capacitive_load_unit (1,pf) ; + voltage_unit : "1V" ; + current_unit : "1uA" ; + time_unit : "1ns" ; + leakage_power_unit : "1nW" ; + pulling_resistance_unit : "1kohm"; + /* + ------------------------------------------------------------------------------------------ + implicit units overview: + cell_area unit : "um" + internal_power unit : "1e-12 * J/toggle = 1 * uW/MHz" + (capacitive_load_unit * voltage_unit^2) per toggle event + ------------------------------------------------------------------------------------------ + */ + library_features(report_delay_calculation); + define_cell_area (pad_drivers,pad_driver_sites) ; + + lu_table_template(CLKTRAN_constraint_template) { + variable_1 : constrained_pin_transition; + index_1 ( "0.010, 0.050, 0.200, 0.400, 1.000" ); + } + lu_table_template(SRAM_load_template) { + variable_1 : total_output_net_capacitance; + index_1 ( "0.0008,0.0014,0.0051,0.0100,0.0339,0.0640" ); + } + lu_table_template(SIG2SRAM_constraint_template) { + variable_1 : related_pin_transition; + variable_2 : constrained_pin_transition; + index_1 ( "0.0056,0.0232,0.0400,0.0728,0.1280,0.2440,0.4760" ); + index_2 ( "0.0056,0.0232,0.0400,0.0728,0.1280,0.2440,0.4760" ); + } + + lu_table_template(SIG2SRAM_delay_template) { + variable_1 : input_net_transition; + variable_2 : total_output_net_capacitance; + index_1 ( "0.0056,0.0232,0.0400,0.0728,0.1280,0.2440,0.4760" ); + index_2 ( "0.0008,0.0014,0.0051,0.0100,0.0339,0.0640" ); + } + + type (D_15_0) { + base_type : array; + data_type : bit; + bit_width : 16; + bit_from : 15; + bit_to : 0; + downto : true; + } + + type (A_7_0) { + base_type : array; + data_type : bit; + bit_width : 8; + bit_from : 7; + bit_to : 0; + downto : true; + } + +cell(RM_IHPSG13_2P_256x16_c2_bm_bist) { +pg_pin (VDD) { + pg_type : primary_power; + voltage_name : VDD; +} +pg_pin (VDDARRAY) { + pg_type : primary_power; + voltage_name : VDDARRAY; +} +pg_pin (VSS) { + pg_type : primary_ground; + voltage_name : VSS; +} + +memory() { + type : ram; + address_width : 8; + word_width : 16; +} + +interface_timing : false; +bus_naming_style : "%s[%d]" ; +area : 57520.5515 ; + + pin(A_DLY) { + direction : input ; + capacitance : 0.00401111 ; + max_transition : "1" ; + related_power_pin : VDD; + related_ground_pin : VSS; + internal_power() { + rise_power("scalar") { + values (0); + } + fall_power("scalar") { + values (0); + } + } + } + +bus(A_ADDR) { + bus_type : A_7_0; + direction : input ; + capacitance : 0.0121077 ; + pin(A_ADDR[0]) { + capacitance : 0.00568653 ; + } + pin(A_ADDR[1]) { + capacitance : 0.00767263 ; + } + pin(A_ADDR[2]) { + capacitance : 0.0105079 ; + } + pin(A_ADDR[3]) { + capacitance : 0.0068178 ; + } + pin(A_ADDR[4]) { + capacitance : 0.00624497 ; + } + pin(A_ADDR[5]) { + capacitance : 0.0105871 ; + } + pin(A_ADDR[6]) { + capacitance : 0.0130817 ; + } + max_transition : "0.476" ; + pin(A_ADDR[7:0]) { + related_power_pin : VDD; + related_ground_pin : VSS; + internal_power() { + when : "A_MEN"; + rise_power("scalar"){ + values (0.0109); + } + fall_power("scalar"){ + values (0.0051); + } + } + internal_power() { + when : "!A_MEN"; + rise_power("scalar"){ + values (0.0190); + } + fall_power("scalar"){ + values (0.0000); + } + } + } + timing() { + timing_type : setup_rising; + related_pin : "A_CLK"; + when : "((A_WEN | A_REN)& A_MEN)" + sdf_cond : "A_RW_ACCESS" + + rise_constraint("SIG2SRAM_constraint_template") { + index_1("0.0056,0.0232,0.0400,0.0728,0.1280,0.2440,0.4760"); + index_2("0.0056,0.0232,0.0400,0.0728,0.1280,0.2440,0.4760"); + values ("-0.4168,-0.3973,-0.3855,-0.3543,-0.3074,-0.2020,-0.0027",\ +"-0.4324,-0.4129,-0.4012,-0.3699,-0.3191,-0.2176,-0.0184",\ +"-0.4441,-0.4285,-0.4129,-0.3816,-0.3309,-0.2293,-0.0301",\ +"-0.4793,-0.4598,-0.4441,-0.4129,-0.3660,-0.2645,-0.0652",\ +"-0.5223,-0.5066,-0.4910,-0.4598,-0.4129,-0.3074,-0.1121",\ +"-0.6199,-0.6082,-0.5926,-0.5613,-0.5145,-0.4129,-0.2137",\ +"-0.8191,-0.8074,-0.7840,-0.7566,-0.7098,-0.6082,-0.4051"); + } + + fall_constraint("SIG2SRAM_constraint_template") { + index_1("0.0056,0.0232,0.0400,0.0728,0.1280,0.2440,0.4760"); + index_2("0.0056,0.0232,0.0400,0.0728,0.1280,0.2440,0.4760"); + values ("-0.3309,-0.3113,-0.2996,-0.2684,-0.2176,-0.1238,0.0637",\ +"-0.3465,-0.3309,-0.3152,-0.2840,-0.2332,-0.1395,0.0480",\ +"-0.3582,-0.3426,-0.3270,-0.2996,-0.2488,-0.1512,0.0324",\ +"-0.3895,-0.3738,-0.3582,-0.3309,-0.2801,-0.1863,0.0051",\ +"-0.4363,-0.4207,-0.4051,-0.3777,-0.3230,-0.2293,-0.0379",\ +"-0.5379,-0.5223,-0.5066,-0.4793,-0.4285,-0.3309,-0.1434",\ +"-0.7332,-0.7176,-0.7020,-0.6746,-0.6238,-0.5262,-0.3387"); + } + } + + + timing() { + timing_type : hold_rising; + related_pin : "A_CLK"; + when : "((A_WEN | A_REN)& A_MEN)" + sdf_cond : "A_RW_ACCESS" + + rise_constraint("SIG2SRAM_constraint_template") { + index_1("0.0056,0.0232,0.0400,0.0728,0.1280,0.2440,0.4760"); + index_2("0.0056,0.0232,0.0400,0.0728,0.1280,0.2440,0.4760"); + values ("0.5246,0.5051,0.4895,0.4582,0.4113,0.3059,0.1066",\ +"0.5402,0.5207,0.5051,0.4777,0.4270,0.3215,0.1223",\ +"0.5520,0.5324,0.5168,0.4895,0.4387,0.3371,0.1340",\ +"0.5832,0.5676,0.5520,0.5207,0.4738,0.3684,0.1691",\ +"0.6301,0.6105,0.5949,0.5676,0.5168,0.4113,0.2160",\ +"0.7316,0.7121,0.7004,0.6691,0.6223,0.5168,0.3176",\ +"0.9270,0.9230,0.8957,0.8645,0.8137,0.7121,0.5168"); + } + + fall_constraint("SIG2SRAM_constraint_template") { + index_1("0.0056,0.0232,0.0400,0.0728,0.1280,0.2440,0.4760"); + index_2("0.0056,0.0232,0.0400,0.0728,0.1280,0.2440,0.4760"); + values ("0.4309,0.4152,0.4035,0.3684,0.3215,0.2277,0.0363",\ +"0.4465,0.4309,0.4152,0.3879,0.3371,0.2395,0.0559",\ +"0.4582,0.4426,0.4309,0.3996,0.3488,0.2551,0.0715",\ +"0.4934,0.4777,0.4621,0.4348,0.3840,0.2863,0.0988",\ +"0.5363,0.5207,0.5051,0.4777,0.4270,0.3332,0.1418",\ +"0.6379,0.6262,0.6105,0.5793,0.5324,0.4348,0.2434",\ +"0.8332,0.8215,0.8059,0.7707,0.7238,0.6301,0.4387"); + } + } +} +pin(A_WEN) { + direction : input ; + capacitance : 0.00324098 ; + max_transition : "0.476" ; + related_power_pin : VDD; + related_ground_pin : VSS; + internal_power() { + when : "A_MEN"; + rise_power("scalar"){ + values (0.0046); + } + fall_power("scalar"){ + values (0.0038); + } + } + internal_power() { + when : "!A_MEN"; + rise_power("scalar"){ + values (0.0042); + } + fall_power("scalar"){ + values (0.0039); + } + } + timing() { + timing_type : setup_rising; + related_pin : "A_CLK"; + when : "A_MEN" + sdf_cond : "A_MEN" + + rise_constraint("SIG2SRAM_constraint_template") { + index_1("0.0056,0.0232,0.0400,0.0728,0.1280,0.2440,0.4760"); + index_2("0.0056,0.0232,0.0400,0.0728,0.1280,0.2440,0.4760"); + values ("0.2043,0.2199,0.2316,0.2629,0.3059,0.4113,0.6066",\ +"0.1887,0.2043,0.2160,0.2473,0.2941,0.3957,0.5949",\ +"0.1691,0.1848,0.2004,0.2316,0.2785,0.3801,0.5754",\ +"0.1379,0.1574,0.1691,0.2004,0.2473,0.3527,0.5480",\ +"0.0910,0.1066,0.1223,0.1535,0.2004,0.2980,0.4973",\ +"-0.0105,0.0051,0.0207,0.0520,0.0949,0.2004,0.3957",\ +"-0.2059,-0.1902,-0.1746,-0.1473,-0.1004,0.0051,0.2004"); + } + + fall_constraint("SIG2SRAM_constraint_template") { + index_1("0.0056,0.0232,0.0400,0.0728,0.1280,0.2440,0.4760"); + index_2("0.0056,0.0232,0.0400,0.0728,0.1280,0.2440,0.4760"); + values ("0.2941,0.3098,0.3215,0.3488,0.4035,0.4973,0.6887",\ +"0.2785,0.2941,0.3059,0.3332,0.3840,0.4816,0.6691",\ +"0.2629,0.2785,0.2902,0.3176,0.3684,0.4660,0.6535",\ +"0.2316,0.2473,0.2590,0.2863,0.3410,0.4348,0.6262",\ +"0.1848,0.2004,0.2121,0.2395,0.2902,0.3879,0.5754",\ +"0.0832,0.0988,0.1105,0.1379,0.1809,0.2746,0.4699",\ +"-0.1121,-0.0965,-0.0848,-0.0535,-0.0066,0.0910,0.2824"); + } + } + + + timing() { + timing_type : hold_rising; + related_pin : "A_CLK"; + when : "A_MEN" + sdf_cond : "A_MEN" + + rise_constraint("SIG2SRAM_constraint_template") { + index_1("0.0056,0.0232,0.0400,0.0728,0.1280,0.2440,0.4760"); + index_2("0.0056,0.0232,0.0400,0.0728,0.1280,0.2440,0.4760"); + values ("0.2473,0.2316,0.2160,0.1887,0.1379,0.0363,-0.1629",\ +"0.2629,0.2473,0.2316,0.2043,0.1535,0.0520,-0.1473",\ +"0.2785,0.2590,0.2434,0.2160,0.1652,0.0676,-0.1355",\ +"0.3098,0.2941,0.2785,0.2473,0.1965,0.0910,-0.1043",\ +"0.3527,0.3371,0.3215,0.2941,0.2434,0.1418,-0.0574",\ +"0.4582,0.4426,0.4270,0.3957,0.3488,0.2434,0.0480",\ +"0.6535,0.6379,0.6184,0.5910,0.5402,0.4426,0.2434"); + } + + fall_constraint("SIG2SRAM_constraint_template") { + index_1("0.0056,0.0232,0.0400,0.0728,0.1280,0.2440,0.4760"); + index_2("0.0056,0.0232,0.0400,0.0728,0.1280,0.2440,0.4760"); + values ("0.2395,0.2238,0.2121,0.1809,0.1301,0.0324,-0.1551",\ +"0.2551,0.2395,0.2277,0.1965,0.1457,0.0480,-0.1395",\ +"0.2668,0.2551,0.2395,0.2082,0.1574,0.0637,-0.1277",\ +"0.3020,0.2863,0.2707,0.2395,0.1887,0.0910,-0.0965",\ +"0.3449,0.3293,0.3176,0.2863,0.2355,0.1379,-0.0496",\ +"0.4504,0.4348,0.4191,0.3879,0.3371,0.2395,0.0559",\ +"0.6457,0.6301,0.6145,0.5871,0.5324,0.4309,0.2512"); + } + } + } +pin(A_REN) { + direction : input ; + capacitance : 0.00381634 ; + max_transition : "0.476" ; + related_power_pin : VDD; + related_ground_pin : VSS; + internal_power() { + when : "A_MEN"; + rise_power("scalar"){ + values (0.0061); + } + fall_power("scalar"){ + values (0.0020); + } + } + internal_power() { + when : "!A_MEN"; + rise_power("scalar"){ + values (0.0062); + } + fall_power("scalar"){ + values (0.0025); + } + } + timing() { + timing_type : setup_rising; + related_pin : "A_CLK"; + when : "A_MEN" + sdf_cond : "A_MEN" + + rise_constraint("SIG2SRAM_constraint_template") { + index_1("0.0056,0.0232,0.0400,0.0728,0.1280,0.2440,0.4760"); + index_2("0.0056,0.0232,0.0400,0.0728,0.1280,0.2440,0.4760"); + values ("-0.0301,-0.0145,0.0012,0.0324,0.0793,0.1809,0.3762",\ +"-0.0457,-0.0301,-0.0145,0.0168,0.0637,0.1613,0.3605",\ +"-0.0574,-0.0418,-0.0262,0.0051,0.0520,0.1496,0.3449",\ +"-0.0926,-0.0730,-0.0574,-0.0262,0.0207,0.1184,0.3137",\ +"-0.1395,-0.1238,-0.1082,-0.0770,-0.0301,0.0715,0.2707",\ +"-0.2410,-0.2254,-0.2098,-0.1746,-0.1355,-0.0340,0.1652",\ +"-0.4402,-0.4207,-0.4051,-0.3738,-0.3270,-0.2293,-0.0340"); + } + + fall_constraint("SIG2SRAM_constraint_template") { + index_1("0.0056,0.0232,0.0400,0.0728,0.1280,0.2440,0.4760"); + index_2("0.0056,0.0232,0.0400,0.0728,0.1280,0.2440,0.4760"); + values ("0.0988,0.1145,0.1262,0.1535,0.2043,0.3020,0.4855",\ +"0.0832,0.0988,0.1105,0.1418,0.1848,0.2824,0.4738",\ +"0.0676,0.0832,0.0949,0.1262,0.1730,0.2668,0.4621",\ +"0.0402,0.0559,0.0676,0.0988,0.1457,0.2434,0.4191",\ +"-0.0105,0.0012,0.0168,0.0480,0.0988,0.1965,0.3840",\ +"-0.1160,-0.0965,-0.0848,-0.0535,-0.0066,0.0988,0.2824",\ +"-0.3113,-0.2957,-0.2801,-0.2527,-0.2059,-0.1043,0.0832"); + } + } + + + timing() { + timing_type : hold_rising; + related_pin : "A_CLK"; + when : "A_MEN" + sdf_cond : "A_MEN" + + rise_constraint("SIG2SRAM_constraint_template") { + index_1("0.0056,0.0232,0.0400,0.0728,0.1280,0.2440,0.4760"); + index_2("0.0056,0.0232,0.0400,0.0728,0.1280,0.2440,0.4760"); + values ("0.2707,0.2551,0.2395,0.2121,0.1613,0.0598,-0.1395",\ +"0.2863,0.2707,0.2551,0.2238,0.1730,0.0715,-0.1238",\ +"0.2980,0.2824,0.2668,0.2395,0.1887,0.0871,-0.1121",\ +"0.3332,0.3176,0.3020,0.2707,0.2199,0.1184,-0.0809",\ +"0.3762,0.3605,0.3449,0.3176,0.2668,0.1613,-0.0340",\ +"0.4816,0.4621,0.4504,0.4191,0.3723,0.2629,0.0715",\ +"0.6770,0.6613,0.6418,0.6184,0.5637,0.4699,0.2629"); + } + + fall_constraint("SIG2SRAM_constraint_template") { + index_1("0.0056,0.0232,0.0400,0.0728,0.1280,0.2440,0.4760"); + index_2("0.0056,0.0232,0.0400,0.0728,0.1280,0.2440,0.4760"); + values ("0.2590,0.2434,0.2316,0.2004,0.1457,0.0520,-0.1355",\ +"0.2746,0.2590,0.2434,0.2160,0.1613,0.0676,-0.1199",\ +"0.2863,0.2707,0.2590,0.2277,0.1730,0.0832,-0.1082",\ +"0.3215,0.3059,0.2902,0.2590,0.2082,0.1105,-0.0770",\ +"0.3645,0.3488,0.3332,0.3059,0.2551,0.1535,-0.0340",\ +"0.4699,0.4543,0.4387,0.4074,0.3605,0.2551,0.0715",\ +"0.6652,0.6496,0.6340,0.6027,0.5520,0.4621,0.2707"); + } + } + } +pin(A_MEN) { + direction : input ; + capacitance : 0.00309605 ; + max_transition : "0.476" ; + related_power_pin : VDD; + related_ground_pin : VSS; + internal_power() { + rise_power("scalar"){ + values (0.0447); + } + fall_power("scalar"){ + values (0.0052); + } + } + timing() { + timing_type : setup_rising; + related_pin : "A_CLK"; + + rise_constraint("SIG2SRAM_constraint_template") { + index_1("0.0056,0.0232,0.0400,0.0728,0.1280,0.2440,0.4760"); + index_2("0.0056,0.0232,0.0400,0.0728,0.1280,0.2440,0.4760"); + values ("0.2043,0.2199,0.2316,0.2668,0.3098,0.4152,0.6066",\ +"0.1887,0.2043,0.2199,0.2512,0.2941,0.3996,0.5949",\ +"0.1730,0.1887,0.2043,0.2355,0.2824,0.3840,0.5793",\ +"0.1418,0.1574,0.1730,0.2043,0.2512,0.3566,0.5480",\ +"0.0949,0.1105,0.1262,0.1574,0.2043,0.3020,0.5051",\ +"-0.0066,0.0090,0.0246,0.0520,0.0988,0.2043,0.3996",\ +"-0.2020,-0.1863,-0.1746,-0.1434,-0.0965,0.0090,0.2082"); + } + + fall_constraint("SIG2SRAM_constraint_template") { + index_1("0.0056,0.0232,0.0400,0.0728,0.1280,0.2440,0.4760"); + index_2("0.0056,0.0232,0.0400,0.0728,0.1280,0.2440,0.4760"); + values ("0.2980,0.3137,0.3254,0.3527,0.4035,0.5012,0.6887",\ +"0.2824,0.2980,0.3098,0.3371,0.3879,0.4855,0.6730",\ +"0.2668,0.2824,0.2941,0.3215,0.3723,0.4699,0.6574",\ +"0.2355,0.2473,0.2629,0.2902,0.3410,0.4387,0.6262",\ +"0.1887,0.2004,0.2160,0.2395,0.2941,0.3918,0.5793",\ +"0.0871,0.1027,0.1145,0.1418,0.1848,0.2746,0.4816",\ +"-0.1082,-0.0965,-0.0809,-0.0496,-0.0027,0.0949,0.2863"); + } + } + + + timing() { + timing_type : hold_rising; + related_pin : "A_CLK"; + + rise_constraint("SIG2SRAM_constraint_template") { + index_1("0.0056,0.0232,0.0400,0.0728,0.1280,0.2440,0.4760"); + index_2("0.0056,0.0232,0.0400,0.0728,0.1280,0.2440,0.4760"); + values ("0.2512,0.2355,0.2199,0.1926,0.1418,0.0402,-0.1590",\ +"0.2668,0.2512,0.2355,0.2082,0.1574,0.0559,-0.1434",\ +"0.2824,0.2629,0.2512,0.2199,0.1691,0.0715,-0.1316",\ +"0.3137,0.2980,0.2824,0.2512,0.2004,0.0988,-0.0965",\ +"0.3566,0.3410,0.3254,0.2980,0.2473,0.1418,-0.0535",\ +"0.4621,0.4426,0.4309,0.3996,0.3527,0.2473,0.0520",\ +"0.6574,0.6418,0.6262,0.5949,0.5441,0.4465,0.2473"); + } + + fall_constraint("SIG2SRAM_constraint_template") { + index_1("0.0056,0.0232,0.0400,0.0728,0.1280,0.2440,0.4760"); + index_2("0.0056,0.0232,0.0400,0.0728,0.1280,0.2440,0.4760"); + values ("0.2395,0.2238,0.2121,0.1809,0.1301,0.0324,-0.1551",\ +"0.2551,0.2434,0.2277,0.1965,0.1457,0.0480,-0.1395",\ +"0.2707,0.2551,0.2395,0.2082,0.1574,0.0637,-0.1277",\ +"0.3020,0.2863,0.2707,0.2434,0.1926,0.0910,-0.0965",\ +"0.3449,0.3332,0.3176,0.2863,0.2355,0.1379,-0.0496",\ +"0.4504,0.4348,0.4230,0.3918,0.3410,0.2434,0.0559",\ +"0.6457,0.6301,0.6145,0.5910,0.5324,0.4387,0.2512"); + } + } + } +bus(A_BM) { + bus_type : D_15_0; + direction : input ; + capacitance : 0.00372627 ; + max_transition : "0.476" ; + pin(A_BM[15:0]) { + related_power_pin : VDD; + related_ground_pin : VSS; + internal_power() { + when : "A_MEN"; + rise_power("scalar"){ + values (0.0591); + } + fall_power("scalar"){ + values (0.0246); + } + } + internal_power() { + when : "!A_MEN"; + rise_power("scalar"){ + values (0.0602); + } + fall_power("scalar"){ + values (0.0244); + } + } + } + timing() { + timing_type : setup_rising; + related_pin : "A_CLK"; + when : "(A_WEN & A_MEN)" + sdf_cond : "A_RW_ACCESS" + + rise_constraint("SIG2SRAM_constraint_template") { + index_1("0.0056,0.0232,0.0400,0.0728,0.1280,0.2440,0.4760"); + index_2("0.0056,0.0232,0.0400,0.0728,0.1280,0.2440,0.4760"); + values ("-0.3235,-0.3079,-0.2952,-0.2620,-0.2132,-0.1145,0.0788",\ +"-0.3285,-0.3129,-0.3002,-0.2670,-0.2182,-0.1195,0.0738",\ +"-0.3330,-0.3174,-0.3047,-0.2715,-0.2226,-0.1240,0.0693",\ +"-0.3421,-0.3265,-0.3138,-0.2806,-0.2318,-0.1331,0.0602",\ +"-0.3493,-0.3337,-0.3210,-0.2878,-0.2390,-0.1403,0.0530",\ +"-0.3790,-0.3634,-0.3507,-0.3175,-0.2686,-0.1700,0.0234",\ +"-0.4370,-0.4214,-0.4087,-0.3755,-0.3267,-0.2281,-0.0347"); + } + + fall_constraint("SIG2SRAM_constraint_template") { + index_1("0.0056,0.0232,0.0400,0.0728,0.1280,0.2440,0.4760"); + index_2("0.0056,0.0232,0.0400,0.0728,0.1280,0.2440,0.4760"); + values ("-0.2893,-0.2747,-0.2610,-0.2327,-0.1829,-0.0843,0.0954",\ +"-0.2943,-0.2797,-0.2660,-0.2377,-0.1879,-0.0893,0.0904",\ +"-0.2988,-0.2842,-0.2705,-0.2422,-0.1924,-0.0937,0.0859",\ +"-0.3079,-0.2933,-0.2796,-0.2513,-0.2015,-0.1029,0.0768",\ +"-0.3151,-0.3005,-0.2868,-0.2585,-0.2087,-0.1101,0.0696",\ +"-0.3448,-0.3301,-0.3165,-0.2882,-0.2384,-0.1397,0.0400",\ +"-0.4029,-0.3882,-0.3745,-0.3462,-0.2964,-0.1978,-0.0181"); + } + } + + + timing() { + timing_type : hold_rising; + related_pin : "A_CLK"; + when : "(A_WEN & A_MEN)" + sdf_cond : "A_RW_ACCESS" + + rise_constraint("SIG2SRAM_constraint_template") { + index_1("0.0056,0.0232,0.0400,0.0728,0.1280,0.2440,0.4760"); + index_2("0.0056,0.0232,0.0400,0.0728,0.1280,0.2440,0.4760"); + values ("0.4331,0.4175,0.4048,0.3716,0.3237,0.2241,0.0298",\ +"0.4381,0.4225,0.4098,0.3766,0.3287,0.2291,0.0348",\ +"0.4426,0.4270,0.4143,0.3811,0.3332,0.2336,0.0393",\ +"0.4517,0.4361,0.4234,0.3902,0.3423,0.2427,0.0484",\ +"0.4589,0.4433,0.4306,0.3974,0.3495,0.2499,0.0556",\ +"0.4886,0.4729,0.4602,0.4270,0.3792,0.2796,0.0853",\ +"0.5466,0.5310,0.5183,0.4851,0.4373,0.3376,0.1433"); + } + + fall_constraint("SIG2SRAM_constraint_template") { + index_1("0.0056,0.0232,0.0400,0.0728,0.1280,0.2440,0.4760"); + index_2("0.0056,0.0232,0.0400,0.0728,0.1280,0.2440,0.4760"); + values ("0.3921,0.3774,0.3628,0.3345,0.2837,0.1919,0.0073",\ +"0.3971,0.3824,0.3678,0.3395,0.2887,0.1969,0.0123",\ +"0.4016,0.3869,0.3723,0.3440,0.2932,0.2014,0.0168",\ +"0.4107,0.3960,0.3814,0.3531,0.3023,0.2105,0.0259",\ +"0.4179,0.4032,0.3886,0.3603,0.3095,0.2177,0.0331",\ +"0.4476,0.4329,0.4183,0.3899,0.3392,0.2474,0.0628",\ +"0.5056,0.4910,0.4763,0.4480,0.3972,0.3054,0.1209"); + } + } +} + pin(A_CLK) { + direction : input; + capacitance : 0.00380014; + max_transition : "0.476"; + clock : "true" ; + pin_func_type : active_rising ; + + timing () { + timing_type : "min_pulse_width"; + related_pin : "A_CLK"; + rise_constraint("CLKTRAN_constraint_template") { + index_1("0.0056,0.476"); + values("0.21,0.21"); + } + } + + related_power_pin : VDD; + related_ground_pin : VSS; + + internal_power() { + when : "!A_MEN & !A_WEN & !A_REN"; + rise_power("scalar"){ + values (0); + } + fall_power("scalar"){ + values (0); + } + } + internal_power() { + when : "!A_MEN & A_WEN & !A_REN"; + rise_power("scalar"){ + values (0.4920); + } + fall_power("scalar"){ + values (0); + } + } + internal_power() { + when : "A_MEN & A_WEN & !A_REN"; + rise_power("scalar"){ + values (18.4562); + } + fall_power("scalar"){ + values (0); + } + } + internal_power() { + when : "A_MEN & A_WEN & A_REN"; + rise_power("scalar"){ + values (20.3138); + } + fall_power("scalar"){ + values (0); + } + } + internal_power() { + when : "A_MEN & !A_WEN & A_REN"; + rise_power("scalar"){ + values (14.1920); + } + fall_power("scalar"){ + values (0); + } + } + internal_power() { + when : "!A_MEN & !A_WEN & A_REN"; + rise_power("scalar"){ + values (0.2984); + } + fall_power("scalar"){ + values (0); + } + } + internal_power() { + when : "!A_MEN & A_WEN & A_REN"; + rise_power("scalar"){ + values (0.7334); + } + fall_power("scalar"){ + values (0); + } + } + internal_power() { + when : "A_MEN & !A_WEN & !A_REN"; + rise_power("scalar"){ + values (0); + } + fall_power("scalar"){ + values (0); + } + } + } + bus(A_DIN) { + bus_type : D_15_0; + direction : input ; + capacitance : 0.00500744 ; + memory_write() { + address : A_ADDR ; + clocked_on : A_CLK; + } + + max_transition : "0.476" ; + pin(A_DIN[15:0]) { + related_power_pin : VDD; + related_ground_pin : VSS; + internal_power() { + when : "A_MEN"; + rise_power("scalar"){ + values (0.0591); + } + fall_power("scalar"){ + values (0.0246); + } + } + internal_power() { + when : "!A_MEN"; + rise_power("scalar"){ + values (0.0602); + } + fall_power("scalar"){ + values (0.0244); + } + } + } + timing() { + timing_type : setup_rising; + related_pin : "A_CLK"; + when : "(A_WEN & A_MEN)"; + sdf_cond : "A_W_ACCESS"; + + rise_constraint("SIG2SRAM_constraint_template") { + index_1("0.0056,0.0232,0.0400,0.0728,0.1280,0.2440,0.4760"); + index_2("0.0056,0.0232,0.0400,0.0728,0.1280,0.2440,0.4760"); + values ("-0.3235,-0.3079,-0.2952,-0.2620,-0.2132,-0.1145,0.0788",\ +"-0.3285,-0.3129,-0.3002,-0.2670,-0.2182,-0.1195,0.0738",\ +"-0.3330,-0.3174,-0.3047,-0.2715,-0.2226,-0.1240,0.0693",\ +"-0.3421,-0.3265,-0.3138,-0.2806,-0.2318,-0.1331,0.0602",\ +"-0.3493,-0.3337,-0.3210,-0.2878,-0.2390,-0.1403,0.0530",\ +"-0.3790,-0.3634,-0.3507,-0.3175,-0.2686,-0.1700,0.0234",\ +"-0.4370,-0.4214,-0.4087,-0.3755,-0.3267,-0.2281,-0.0347"); + } + + fall_constraint("SIG2SRAM_constraint_template") { + index_1("0.0056,0.0232,0.0400,0.0728,0.1280,0.2440,0.4760"); + index_2("0.0056,0.0232,0.0400,0.0728,0.1280,0.2440,0.4760"); + values ("-0.2893,-0.2747,-0.2610,-0.2327,-0.1829,-0.0843,0.0954",\ +"-0.2943,-0.2797,-0.2660,-0.2377,-0.1879,-0.0893,0.0904",\ +"-0.2988,-0.2842,-0.2705,-0.2422,-0.1924,-0.0937,0.0859",\ +"-0.3079,-0.2933,-0.2796,-0.2513,-0.2015,-0.1029,0.0768",\ +"-0.3151,-0.3005,-0.2868,-0.2585,-0.2087,-0.1101,0.0696",\ +"-0.3448,-0.3301,-0.3165,-0.2882,-0.2384,-0.1397,0.0400",\ +"-0.4029,-0.3882,-0.3745,-0.3462,-0.2964,-0.1978,-0.0181"); + } + } + + timing() { + timing_type : hold_rising; + related_pin : "A_CLK"; + when : "(A_WEN & A_MEN)"; + sdf_cond : "A_W_ACCESS"; + + rise_constraint("SIG2SRAM_constraint_template") { + index_1("0.0056,0.0232,0.0400,0.0728,0.1280,0.2440,0.4760"); + index_2("0.0056,0.0232,0.0400,0.0728,0.1280,0.2440,0.4760"); + values ("0.4331,0.4175,0.4048,0.3716,0.3237,0.2241,0.0298",\ +"0.4381,0.4225,0.4098,0.3766,0.3287,0.2291,0.0348",\ +"0.4426,0.4270,0.4143,0.3811,0.3332,0.2336,0.0393",\ +"0.4517,0.4361,0.4234,0.3902,0.3423,0.2427,0.0484",\ +"0.4589,0.4433,0.4306,0.3974,0.3495,0.2499,0.0556",\ +"0.4886,0.4729,0.4602,0.4270,0.3792,0.2796,0.0853",\ +"0.5466,0.5310,0.5183,0.4851,0.4373,0.3376,0.1433"); + } + + fall_constraint("SIG2SRAM_constraint_template") { + index_1("0.0056,0.0232,0.0400,0.0728,0.1280,0.2440,0.4760"); + index_2("0.0056,0.0232,0.0400,0.0728,0.1280,0.2440,0.4760"); + values ("0.3921,0.3774,0.3628,0.3345,0.2837,0.1919,0.0073",\ +"0.3971,0.3824,0.3678,0.3395,0.2887,0.1969,0.0123",\ +"0.4016,0.3869,0.3723,0.3440,0.2932,0.2014,0.0168",\ +"0.4107,0.3960,0.3814,0.3531,0.3023,0.2105,0.0259",\ +"0.4179,0.4032,0.3886,0.3603,0.3095,0.2177,0.0331",\ +"0.4476,0.4329,0.4183,0.3899,0.3392,0.2474,0.0628",\ +"0.5056,0.4910,0.4763,0.4480,0.3972,0.3054,0.1209"); + } + } + } + + pin(A_BIST_EN) { + direction : input ; + capacitance : 0.00401111 ; + max_transition : "1" ; + related_power_pin : VDD; + related_ground_pin : VSS; + internal_power() { + rise_power("scalar") { + values (0); + } + fall_power("scalar") { + values (0); + } + } + } + +bus(A_BIST_ADDR) { + bus_type : A_7_0; + direction : input ; + capacitance : 0.0121077 ; + pin(A_BIST_ADDR[0]) { + capacitance : 0.00568653 ; + } + pin(A_BIST_ADDR[1]) { + capacitance : 0.00767263 ; + } + pin(A_BIST_ADDR[2]) { + capacitance : 0.0105079 ; + } + pin(A_BIST_ADDR[3]) { + capacitance : 0.0068178 ; + } + pin(A_BIST_ADDR[4]) { + capacitance : 0.00624497 ; + } + pin(A_BIST_ADDR[5]) { + capacitance : 0.0105871 ; + } + pin(A_BIST_ADDR[6]) { + capacitance : 0.0130817 ; + } + max_transition : "0.476" ; + pin(A_BIST_ADDR[7:0]) { + related_power_pin : VDD; + related_ground_pin : VSS; + internal_power() { + when : "A_BIST_MEN"; + rise_power("scalar"){ + values (0.0109); + } + fall_power("scalar"){ + values (0.0051); + } + } + internal_power() { + when : "!A_BIST_MEN"; + rise_power("scalar"){ + values (0.0190); + } + fall_power("scalar"){ + values (0.0000); + } + } + } + timing() { + timing_type : setup_rising; + related_pin : "A_BIST_CLK"; + when : "((A_BIST_WEN | A_BIST_REN)& A_BIST_MEN)" + sdf_cond : "A_BIST_RW_ACCESS" + + rise_constraint("SIG2SRAM_constraint_template") { + index_1("0.0056,0.0232,0.0400,0.0728,0.1280,0.2440,0.4760"); + index_2("0.0056,0.0232,0.0400,0.0728,0.1280,0.2440,0.4760"); + values ("-0.4168,-0.3973,-0.3855,-0.3543,-0.3074,-0.2020,-0.0027",\ +"-0.4324,-0.4129,-0.4012,-0.3699,-0.3191,-0.2176,-0.0184",\ +"-0.4441,-0.4285,-0.4129,-0.3816,-0.3309,-0.2293,-0.0301",\ +"-0.4793,-0.4598,-0.4441,-0.4129,-0.3660,-0.2645,-0.0652",\ +"-0.5223,-0.5066,-0.4910,-0.4598,-0.4129,-0.3074,-0.1121",\ +"-0.6199,-0.6082,-0.5926,-0.5613,-0.5145,-0.4129,-0.2137",\ +"-0.8191,-0.8074,-0.7840,-0.7566,-0.7098,-0.6082,-0.4051"); + } + + fall_constraint("SIG2SRAM_constraint_template") { + index_1("0.0056,0.0232,0.0400,0.0728,0.1280,0.2440,0.4760"); + index_2("0.0056,0.0232,0.0400,0.0728,0.1280,0.2440,0.4760"); + values ("-0.3309,-0.3113,-0.2996,-0.2684,-0.2176,-0.1238,0.0637",\ +"-0.3465,-0.3309,-0.3152,-0.2840,-0.2332,-0.1395,0.0480",\ +"-0.3582,-0.3426,-0.3270,-0.2996,-0.2488,-0.1512,0.0324",\ +"-0.3895,-0.3738,-0.3582,-0.3309,-0.2801,-0.1863,0.0051",\ +"-0.4363,-0.4207,-0.4051,-0.3777,-0.3230,-0.2293,-0.0379",\ +"-0.5379,-0.5223,-0.5066,-0.4793,-0.4285,-0.3309,-0.1434",\ +"-0.7332,-0.7176,-0.7020,-0.6746,-0.6238,-0.5262,-0.3387"); + } + } + + + timing() { + timing_type : hold_rising; + related_pin : "A_BIST_CLK"; + when : "((A_BIST_WEN | A_BIST_REN)& A_BIST_MEN)" + sdf_cond : "A_BIST_RW_ACCESS" + + rise_constraint("SIG2SRAM_constraint_template") { + index_1("0.0056,0.0232,0.0400,0.0728,0.1280,0.2440,0.4760"); + index_2("0.0056,0.0232,0.0400,0.0728,0.1280,0.2440,0.4760"); + values ("0.5246,0.5051,0.4895,0.4582,0.4113,0.3059,0.1066",\ +"0.5402,0.5207,0.5051,0.4777,0.4270,0.3215,0.1223",\ +"0.5520,0.5324,0.5168,0.4895,0.4387,0.3371,0.1340",\ +"0.5832,0.5676,0.5520,0.5207,0.4738,0.3684,0.1691",\ +"0.6301,0.6105,0.5949,0.5676,0.5168,0.4113,0.2160",\ +"0.7316,0.7121,0.7004,0.6691,0.6223,0.5168,0.3176",\ +"0.9270,0.9230,0.8957,0.8645,0.8137,0.7121,0.5168"); + } + + fall_constraint("SIG2SRAM_constraint_template") { + index_1("0.0056,0.0232,0.0400,0.0728,0.1280,0.2440,0.4760"); + index_2("0.0056,0.0232,0.0400,0.0728,0.1280,0.2440,0.4760"); + values ("0.4309,0.4152,0.4035,0.3684,0.3215,0.2277,0.0363",\ +"0.4465,0.4309,0.4152,0.3879,0.3371,0.2395,0.0559",\ +"0.4582,0.4426,0.4309,0.3996,0.3488,0.2551,0.0715",\ +"0.4934,0.4777,0.4621,0.4348,0.3840,0.2863,0.0988",\ +"0.5363,0.5207,0.5051,0.4777,0.4270,0.3332,0.1418",\ +"0.6379,0.6262,0.6105,0.5793,0.5324,0.4348,0.2434",\ +"0.8332,0.8215,0.8059,0.7707,0.7238,0.6301,0.4387"); + } + } +} +pin(A_BIST_WEN) { + direction : input ; + capacitance : 0.00324098 ; + max_transition : "0.476" ; + related_power_pin : VDD; + related_ground_pin : VSS; + internal_power() { + when : "A_BIST_MEN"; + rise_power("scalar"){ + values (0.0046); + } + fall_power("scalar"){ + values (0.0038); + } + } + internal_power() { + when : "!A_BIST_MEN"; + rise_power("scalar"){ + values (0.0042); + } + fall_power("scalar"){ + values (0.0039); + } + } + timing() { + timing_type : setup_rising; + related_pin : "A_BIST_CLK"; + when : "A_BIST_MEN" + sdf_cond : "A_BIST_MEN" + + rise_constraint("SIG2SRAM_constraint_template") { + index_1("0.0056,0.0232,0.0400,0.0728,0.1280,0.2440,0.4760"); + index_2("0.0056,0.0232,0.0400,0.0728,0.1280,0.2440,0.4760"); + values ("0.2043,0.2199,0.2316,0.2629,0.3059,0.4113,0.6066",\ +"0.1887,0.2043,0.2160,0.2473,0.2941,0.3957,0.5949",\ +"0.1691,0.1848,0.2004,0.2316,0.2785,0.3801,0.5754",\ +"0.1379,0.1574,0.1691,0.2004,0.2473,0.3527,0.5480",\ +"0.0910,0.1066,0.1223,0.1535,0.2004,0.2980,0.4973",\ +"-0.0105,0.0051,0.0207,0.0520,0.0949,0.2004,0.3957",\ +"-0.2059,-0.1902,-0.1746,-0.1473,-0.1004,0.0051,0.2004"); + } + + fall_constraint("SIG2SRAM_constraint_template") { + index_1("0.0056,0.0232,0.0400,0.0728,0.1280,0.2440,0.4760"); + index_2("0.0056,0.0232,0.0400,0.0728,0.1280,0.2440,0.4760"); + values ("0.2941,0.3098,0.3215,0.3488,0.4035,0.4973,0.6887",\ +"0.2785,0.2941,0.3059,0.3332,0.3840,0.4816,0.6691",\ +"0.2629,0.2785,0.2902,0.3176,0.3684,0.4660,0.6535",\ +"0.2316,0.2473,0.2590,0.2863,0.3410,0.4348,0.6262",\ +"0.1848,0.2004,0.2121,0.2395,0.2902,0.3879,0.5754",\ +"0.0832,0.0988,0.1105,0.1379,0.1809,0.2746,0.4699",\ +"-0.1121,-0.0965,-0.0848,-0.0535,-0.0066,0.0910,0.2824"); + } + } + + + timing() { + timing_type : hold_rising; + related_pin : "A_BIST_CLK"; + when : "A_BIST_MEN" + sdf_cond : "A_BIST_MEN" + + rise_constraint("SIG2SRAM_constraint_template") { + index_1("0.0056,0.0232,0.0400,0.0728,0.1280,0.2440,0.4760"); + index_2("0.0056,0.0232,0.0400,0.0728,0.1280,0.2440,0.4760"); + values ("0.2473,0.2316,0.2160,0.1887,0.1379,0.0363,-0.1629",\ +"0.2629,0.2473,0.2316,0.2043,0.1535,0.0520,-0.1473",\ +"0.2785,0.2590,0.2434,0.2160,0.1652,0.0676,-0.1355",\ +"0.3098,0.2941,0.2785,0.2473,0.1965,0.0910,-0.1043",\ +"0.3527,0.3371,0.3215,0.2941,0.2434,0.1418,-0.0574",\ +"0.4582,0.4426,0.4270,0.3957,0.3488,0.2434,0.0480",\ +"0.6535,0.6379,0.6184,0.5910,0.5402,0.4426,0.2434"); + } + + fall_constraint("SIG2SRAM_constraint_template") { + index_1("0.0056,0.0232,0.0400,0.0728,0.1280,0.2440,0.4760"); + index_2("0.0056,0.0232,0.0400,0.0728,0.1280,0.2440,0.4760"); + values ("0.2395,0.2238,0.2121,0.1809,0.1301,0.0324,-0.1551",\ +"0.2551,0.2395,0.2277,0.1965,0.1457,0.0480,-0.1395",\ +"0.2668,0.2551,0.2395,0.2082,0.1574,0.0637,-0.1277",\ +"0.3020,0.2863,0.2707,0.2395,0.1887,0.0910,-0.0965",\ +"0.3449,0.3293,0.3176,0.2863,0.2355,0.1379,-0.0496",\ +"0.4504,0.4348,0.4191,0.3879,0.3371,0.2395,0.0559",\ +"0.6457,0.6301,0.6145,0.5871,0.5324,0.4309,0.2512"); + } + } + } +pin(A_BIST_REN) { + direction : input ; + capacitance : 0.00381634 ; + max_transition : "0.476" ; + related_power_pin : VDD; + related_ground_pin : VSS; + internal_power() { + when : "A_BIST_MEN"; + rise_power("scalar"){ + values (0.0061); + } + fall_power("scalar"){ + values (0.0020); + } + } + internal_power() { + when : "!A_BIST_MEN"; + rise_power("scalar"){ + values (0.0062); + } + fall_power("scalar"){ + values (0.0025); + } + } + timing() { + timing_type : setup_rising; + related_pin : "A_BIST_CLK"; + when : "A_BIST_MEN" + sdf_cond : "A_BIST_MEN" + + rise_constraint("SIG2SRAM_constraint_template") { + index_1("0.0056,0.0232,0.0400,0.0728,0.1280,0.2440,0.4760"); + index_2("0.0056,0.0232,0.0400,0.0728,0.1280,0.2440,0.4760"); + values ("-0.0301,-0.0145,0.0012,0.0324,0.0793,0.1809,0.3762",\ +"-0.0457,-0.0301,-0.0145,0.0168,0.0637,0.1613,0.3605",\ +"-0.0574,-0.0418,-0.0262,0.0051,0.0520,0.1496,0.3449",\ +"-0.0926,-0.0730,-0.0574,-0.0262,0.0207,0.1184,0.3137",\ +"-0.1395,-0.1238,-0.1082,-0.0770,-0.0301,0.0715,0.2707",\ +"-0.2410,-0.2254,-0.2098,-0.1746,-0.1355,-0.0340,0.1652",\ +"-0.4402,-0.4207,-0.4051,-0.3738,-0.3270,-0.2293,-0.0340"); + } + + fall_constraint("SIG2SRAM_constraint_template") { + index_1("0.0056,0.0232,0.0400,0.0728,0.1280,0.2440,0.4760"); + index_2("0.0056,0.0232,0.0400,0.0728,0.1280,0.2440,0.4760"); + values ("0.0988,0.1145,0.1262,0.1535,0.2043,0.3020,0.4855",\ +"0.0832,0.0988,0.1105,0.1418,0.1848,0.2824,0.4738",\ +"0.0676,0.0832,0.0949,0.1262,0.1730,0.2668,0.4621",\ +"0.0402,0.0559,0.0676,0.0988,0.1457,0.2434,0.4191",\ +"-0.0105,0.0012,0.0168,0.0480,0.0988,0.1965,0.3840",\ +"-0.1160,-0.0965,-0.0848,-0.0535,-0.0066,0.0988,0.2824",\ +"-0.3113,-0.2957,-0.2801,-0.2527,-0.2059,-0.1043,0.0832"); + } + } + + + timing() { + timing_type : hold_rising; + related_pin : "A_BIST_CLK"; + when : "A_BIST_MEN" + sdf_cond : "A_BIST_MEN" + + rise_constraint("SIG2SRAM_constraint_template") { + index_1("0.0056,0.0232,0.0400,0.0728,0.1280,0.2440,0.4760"); + index_2("0.0056,0.0232,0.0400,0.0728,0.1280,0.2440,0.4760"); + values ("0.2707,0.2551,0.2395,0.2121,0.1613,0.0598,-0.1395",\ +"0.2863,0.2707,0.2551,0.2238,0.1730,0.0715,-0.1238",\ +"0.2980,0.2824,0.2668,0.2395,0.1887,0.0871,-0.1121",\ +"0.3332,0.3176,0.3020,0.2707,0.2199,0.1184,-0.0809",\ +"0.3762,0.3605,0.3449,0.3176,0.2668,0.1613,-0.0340",\ +"0.4816,0.4621,0.4504,0.4191,0.3723,0.2629,0.0715",\ +"0.6770,0.6613,0.6418,0.6184,0.5637,0.4699,0.2629"); + } + + fall_constraint("SIG2SRAM_constraint_template") { + index_1("0.0056,0.0232,0.0400,0.0728,0.1280,0.2440,0.4760"); + index_2("0.0056,0.0232,0.0400,0.0728,0.1280,0.2440,0.4760"); + values ("0.2590,0.2434,0.2316,0.2004,0.1457,0.0520,-0.1355",\ +"0.2746,0.2590,0.2434,0.2160,0.1613,0.0676,-0.1199",\ +"0.2863,0.2707,0.2590,0.2277,0.1730,0.0832,-0.1082",\ +"0.3215,0.3059,0.2902,0.2590,0.2082,0.1105,-0.0770",\ +"0.3645,0.3488,0.3332,0.3059,0.2551,0.1535,-0.0340",\ +"0.4699,0.4543,0.4387,0.4074,0.3605,0.2551,0.0715",\ +"0.6652,0.6496,0.6340,0.6027,0.5520,0.4621,0.2707"); + } + } + } +pin(A_BIST_MEN) { + direction : input ; + capacitance : 0.00309605 ; + max_transition : "0.476" ; + related_power_pin : VDD; + related_ground_pin : VSS; + internal_power() { + rise_power("scalar"){ + values (0.0447); + } + fall_power("scalar"){ + values (0.0052); + } + } + timing() { + timing_type : setup_rising; + related_pin : "A_BIST_CLK"; + + rise_constraint("SIG2SRAM_constraint_template") { + index_1("0.0056,0.0232,0.0400,0.0728,0.1280,0.2440,0.4760"); + index_2("0.0056,0.0232,0.0400,0.0728,0.1280,0.2440,0.4760"); + values ("0.2043,0.2199,0.2316,0.2668,0.3098,0.4152,0.6066",\ +"0.1887,0.2043,0.2199,0.2512,0.2941,0.3996,0.5949",\ +"0.1730,0.1887,0.2043,0.2355,0.2824,0.3840,0.5793",\ +"0.1418,0.1574,0.1730,0.2043,0.2512,0.3566,0.5480",\ +"0.0949,0.1105,0.1262,0.1574,0.2043,0.3020,0.5051",\ +"-0.0066,0.0090,0.0246,0.0520,0.0988,0.2043,0.3996",\ +"-0.2020,-0.1863,-0.1746,-0.1434,-0.0965,0.0090,0.2082"); + } + + fall_constraint("SIG2SRAM_constraint_template") { + index_1("0.0056,0.0232,0.0400,0.0728,0.1280,0.2440,0.4760"); + index_2("0.0056,0.0232,0.0400,0.0728,0.1280,0.2440,0.4760"); + values ("0.2980,0.3137,0.3254,0.3527,0.4035,0.5012,0.6887",\ +"0.2824,0.2980,0.3098,0.3371,0.3879,0.4855,0.6730",\ +"0.2668,0.2824,0.2941,0.3215,0.3723,0.4699,0.6574",\ +"0.2355,0.2473,0.2629,0.2902,0.3410,0.4387,0.6262",\ +"0.1887,0.2004,0.2160,0.2395,0.2941,0.3918,0.5793",\ +"0.0871,0.1027,0.1145,0.1418,0.1848,0.2746,0.4816",\ +"-0.1082,-0.0965,-0.0809,-0.0496,-0.0027,0.0949,0.2863"); + } + } + + + timing() { + timing_type : hold_rising; + related_pin : "A_BIST_CLK"; + + rise_constraint("SIG2SRAM_constraint_template") { + index_1("0.0056,0.0232,0.0400,0.0728,0.1280,0.2440,0.4760"); + index_2("0.0056,0.0232,0.0400,0.0728,0.1280,0.2440,0.4760"); + values ("0.2512,0.2355,0.2199,0.1926,0.1418,0.0402,-0.1590",\ +"0.2668,0.2512,0.2355,0.2082,0.1574,0.0559,-0.1434",\ +"0.2824,0.2629,0.2512,0.2199,0.1691,0.0715,-0.1316",\ +"0.3137,0.2980,0.2824,0.2512,0.2004,0.0988,-0.0965",\ +"0.3566,0.3410,0.3254,0.2980,0.2473,0.1418,-0.0535",\ +"0.4621,0.4426,0.4309,0.3996,0.3527,0.2473,0.0520",\ +"0.6574,0.6418,0.6262,0.5949,0.5441,0.4465,0.2473"); + } + + fall_constraint("SIG2SRAM_constraint_template") { + index_1("0.0056,0.0232,0.0400,0.0728,0.1280,0.2440,0.4760"); + index_2("0.0056,0.0232,0.0400,0.0728,0.1280,0.2440,0.4760"); + values ("0.2395,0.2238,0.2121,0.1809,0.1301,0.0324,-0.1551",\ +"0.2551,0.2434,0.2277,0.1965,0.1457,0.0480,-0.1395",\ +"0.2707,0.2551,0.2395,0.2082,0.1574,0.0637,-0.1277",\ +"0.3020,0.2863,0.2707,0.2434,0.1926,0.0910,-0.0965",\ +"0.3449,0.3332,0.3176,0.2863,0.2355,0.1379,-0.0496",\ +"0.4504,0.4348,0.4230,0.3918,0.3410,0.2434,0.0559",\ +"0.6457,0.6301,0.6145,0.5910,0.5324,0.4387,0.2512"); + } + } + } +bus(A_BIST_BM) { + bus_type : D_15_0; + direction : input ; + capacitance : 0.00349377 ; + max_transition : "0.476" ; + pin(A_BIST_BM[15:0]) { + related_power_pin : VDD; + related_ground_pin : VSS; + internal_power() { + when : "A_BIST_MEN"; + rise_power("scalar"){ + values (0.0591); + } + fall_power("scalar"){ + values (0.0246); + } + } + internal_power() { + when : "!A_BIST_MEN"; + rise_power("scalar"){ + values (0.0602); + } + fall_power("scalar"){ + values (0.0244); + } + } + } + timing() { + timing_type : setup_rising; + related_pin : "A_BIST_CLK"; + when : "(A_BIST_WEN & A_BIST_MEN)" + sdf_cond : "A_BIST_RW_ACCESS" + + rise_constraint("SIG2SRAM_constraint_template") { + index_1("0.0056,0.0232,0.0400,0.0728,0.1280,0.2440,0.4760"); + index_2("0.0056,0.0232,0.0400,0.0728,0.1280,0.2440,0.4760"); + values ("-0.3235,-0.3079,-0.2952,-0.2620,-0.2132,-0.1145,0.0788",\ +"-0.3285,-0.3129,-0.3002,-0.2670,-0.2182,-0.1195,0.0738",\ +"-0.3330,-0.3174,-0.3047,-0.2715,-0.2226,-0.1240,0.0693",\ +"-0.3421,-0.3265,-0.3138,-0.2806,-0.2318,-0.1331,0.0602",\ +"-0.3493,-0.3337,-0.3210,-0.2878,-0.2390,-0.1403,0.0530",\ +"-0.3790,-0.3634,-0.3507,-0.3175,-0.2686,-0.1700,0.0234",\ +"-0.4370,-0.4214,-0.4087,-0.3755,-0.3267,-0.2281,-0.0347"); + } + + fall_constraint("SIG2SRAM_constraint_template") { + index_1("0.0056,0.0232,0.0400,0.0728,0.1280,0.2440,0.4760"); + index_2("0.0056,0.0232,0.0400,0.0728,0.1280,0.2440,0.4760"); + values ("-0.2893,-0.2747,-0.2610,-0.2327,-0.1829,-0.0843,0.0954",\ +"-0.2943,-0.2797,-0.2660,-0.2377,-0.1879,-0.0893,0.0904",\ +"-0.2988,-0.2842,-0.2705,-0.2422,-0.1924,-0.0937,0.0859",\ +"-0.3079,-0.2933,-0.2796,-0.2513,-0.2015,-0.1029,0.0768",\ +"-0.3151,-0.3005,-0.2868,-0.2585,-0.2087,-0.1101,0.0696",\ +"-0.3448,-0.3301,-0.3165,-0.2882,-0.2384,-0.1397,0.0400",\ +"-0.4029,-0.3882,-0.3745,-0.3462,-0.2964,-0.1978,-0.0181"); + } + } + + + timing() { + timing_type : hold_rising; + related_pin : "A_BIST_CLK"; + when : "(A_BIST_WEN & A_BIST_MEN)" + sdf_cond : "A_BIST_RW_ACCESS" + + rise_constraint("SIG2SRAM_constraint_template") { + index_1("0.0056,0.0232,0.0400,0.0728,0.1280,0.2440,0.4760"); + index_2("0.0056,0.0232,0.0400,0.0728,0.1280,0.2440,0.4760"); + values ("0.4331,0.4175,0.4048,0.3716,0.3237,0.2241,0.0298",\ +"0.4381,0.4225,0.4098,0.3766,0.3287,0.2291,0.0348",\ +"0.4426,0.4270,0.4143,0.3811,0.3332,0.2336,0.0393",\ +"0.4517,0.4361,0.4234,0.3902,0.3423,0.2427,0.0484",\ +"0.4589,0.4433,0.4306,0.3974,0.3495,0.2499,0.0556",\ +"0.4886,0.4729,0.4602,0.4270,0.3792,0.2796,0.0853",\ +"0.5466,0.5310,0.5183,0.4851,0.4373,0.3376,0.1433"); + } + + fall_constraint("SIG2SRAM_constraint_template") { + index_1("0.0056,0.0232,0.0400,0.0728,0.1280,0.2440,0.4760"); + index_2("0.0056,0.0232,0.0400,0.0728,0.1280,0.2440,0.4760"); + values ("0.3921,0.3774,0.3628,0.3345,0.2837,0.1919,0.0073",\ +"0.3971,0.3824,0.3678,0.3395,0.2887,0.1969,0.0123",\ +"0.4016,0.3869,0.3723,0.3440,0.2932,0.2014,0.0168",\ +"0.4107,0.3960,0.3814,0.3531,0.3023,0.2105,0.0259",\ +"0.4179,0.4032,0.3886,0.3603,0.3095,0.2177,0.0331",\ +"0.4476,0.4329,0.4183,0.3899,0.3392,0.2474,0.0628",\ +"0.5056,0.4910,0.4763,0.4480,0.3972,0.3054,0.1209"); + } + } +} + pin(A_BIST_CLK) { + direction : input; + capacitance : 0.00380014; + max_transition : "0.476"; + clock : "true" ; + pin_func_type : active_rising ; + + timing () { + timing_type : "min_pulse_width"; + related_pin : "A_BIST_CLK"; + rise_constraint("CLKTRAN_constraint_template") { + index_1("0.0056,0.476"); + values("0.21,0.21"); + } + } + + related_power_pin : VDD; + related_ground_pin : VSS; + + internal_power() { + when : "!A_BIST_MEN & !A_BIST_WEN & !A_BIST_REN"; + rise_power("scalar"){ + values (0); + } + fall_power("scalar"){ + values (0); + } + } + internal_power() { + when : "!A_BIST_MEN & A_BIST_WEN & !A_BIST_REN"; + rise_power("scalar"){ + values (0.4920); + } + fall_power("scalar"){ + values (0); + } + } + internal_power() { + when : "A_BIST_MEN & A_BIST_WEN & !A_BIST_REN"; + rise_power("scalar"){ + values (18.4562); + } + fall_power("scalar"){ + values (0); + } + } + internal_power() { + when : "A_BIST_MEN & A_BIST_WEN & A_BIST_REN"; + rise_power("scalar"){ + values (20.3138); + } + fall_power("scalar"){ + values (0); + } + } + internal_power() { + when : "A_BIST_MEN & !A_BIST_WEN & A_BIST_REN"; + rise_power("scalar"){ + values (14.1920); + } + fall_power("scalar"){ + values (0); + } + } + internal_power() { + when : "!A_BIST_MEN & !A_BIST_WEN & A_BIST_REN"; + rise_power("scalar"){ + values (0.2984); + } + fall_power("scalar"){ + values (0); + } + } + internal_power() { + when : "!A_BIST_MEN & A_BIST_WEN & A_BIST_REN"; + rise_power("scalar"){ + values (0.7334); + } + fall_power("scalar"){ + values (0); + } + } + internal_power() { + when : "A_BIST_MEN & !A_BIST_WEN & !A_BIST_REN"; + rise_power("scalar"){ + values (0); + } + fall_power("scalar"){ + values (0); + } + } + } + bus(A_BIST_DIN) { + bus_type : D_15_0; + direction : input ; + capacitance : 0.00393889 ; + memory_write() { + address : A_BIST_ADDR ; + clocked_on : A_BIST_CLK; + } + + max_transition : "0.476" ; + pin(A_BIST_DIN[15:0]) { + related_power_pin : VDD; + related_ground_pin : VSS; + internal_power() { + when : "A_BIST_MEN"; + rise_power("scalar"){ + values (0.0591); + } + fall_power("scalar"){ + values (0.0246); + } + } + internal_power() { + when : "!A_BIST_MEN"; + rise_power("scalar"){ + values (0.0602); + } + fall_power("scalar"){ + values (0.0244); + } + } + } + timing() { + timing_type : setup_rising; + related_pin : "A_BIST_CLK"; + when : "(A_BIST_WEN & A_BIST_MEN)"; + sdf_cond : "A_BIST_W_ACCESS"; + + rise_constraint("SIG2SRAM_constraint_template") { + index_1("0.0056,0.0232,0.0400,0.0728,0.1280,0.2440,0.4760"); + index_2("0.0056,0.0232,0.0400,0.0728,0.1280,0.2440,0.4760"); + values ("-0.3235,-0.3079,-0.2952,-0.2620,-0.2132,-0.1145,0.0788",\ +"-0.3285,-0.3129,-0.3002,-0.2670,-0.2182,-0.1195,0.0738",\ +"-0.3330,-0.3174,-0.3047,-0.2715,-0.2226,-0.1240,0.0693",\ +"-0.3421,-0.3265,-0.3138,-0.2806,-0.2318,-0.1331,0.0602",\ +"-0.3493,-0.3337,-0.3210,-0.2878,-0.2390,-0.1403,0.0530",\ +"-0.3790,-0.3634,-0.3507,-0.3175,-0.2686,-0.1700,0.0234",\ +"-0.4370,-0.4214,-0.4087,-0.3755,-0.3267,-0.2281,-0.0347"); + } + + fall_constraint("SIG2SRAM_constraint_template") { + index_1("0.0056,0.0232,0.0400,0.0728,0.1280,0.2440,0.4760"); + index_2("0.0056,0.0232,0.0400,0.0728,0.1280,0.2440,0.4760"); + values ("-0.2893,-0.2747,-0.2610,-0.2327,-0.1829,-0.0843,0.0954",\ +"-0.2943,-0.2797,-0.2660,-0.2377,-0.1879,-0.0893,0.0904",\ +"-0.2988,-0.2842,-0.2705,-0.2422,-0.1924,-0.0937,0.0859",\ +"-0.3079,-0.2933,-0.2796,-0.2513,-0.2015,-0.1029,0.0768",\ +"-0.3151,-0.3005,-0.2868,-0.2585,-0.2087,-0.1101,0.0696",\ +"-0.3448,-0.3301,-0.3165,-0.2882,-0.2384,-0.1397,0.0400",\ +"-0.4029,-0.3882,-0.3745,-0.3462,-0.2964,-0.1978,-0.0181"); + } + } + + timing() { + timing_type : hold_rising; + related_pin : "A_BIST_CLK"; + when : "(A_BIST_WEN & A_BIST_MEN)"; + sdf_cond : "A_BIST_W_ACCESS"; + + rise_constraint("SIG2SRAM_constraint_template") { + index_1("0.0056,0.0232,0.0400,0.0728,0.1280,0.2440,0.4760"); + index_2("0.0056,0.0232,0.0400,0.0728,0.1280,0.2440,0.4760"); + values ("0.4331,0.4175,0.4048,0.3716,0.3237,0.2241,0.0298",\ +"0.4381,0.4225,0.4098,0.3766,0.3287,0.2291,0.0348",\ +"0.4426,0.4270,0.4143,0.3811,0.3332,0.2336,0.0393",\ +"0.4517,0.4361,0.4234,0.3902,0.3423,0.2427,0.0484",\ +"0.4589,0.4433,0.4306,0.3974,0.3495,0.2499,0.0556",\ +"0.4886,0.4729,0.4602,0.4270,0.3792,0.2796,0.0853",\ +"0.5466,0.5310,0.5183,0.4851,0.4373,0.3376,0.1433"); + } + + fall_constraint("SIG2SRAM_constraint_template") { + index_1("0.0056,0.0232,0.0400,0.0728,0.1280,0.2440,0.4760"); + index_2("0.0056,0.0232,0.0400,0.0728,0.1280,0.2440,0.4760"); + values ("0.3921,0.3774,0.3628,0.3345,0.2837,0.1919,0.0073",\ +"0.3971,0.3824,0.3678,0.3395,0.2887,0.1969,0.0123",\ +"0.4016,0.3869,0.3723,0.3440,0.2932,0.2014,0.0168",\ +"0.4107,0.3960,0.3814,0.3531,0.3023,0.2105,0.0259",\ +"0.4179,0.4032,0.3886,0.3603,0.3095,0.2177,0.0331",\ +"0.4476,0.4329,0.4183,0.3899,0.3392,0.2474,0.0628",\ +"0.5056,0.4910,0.4763,0.4480,0.3972,0.3054,0.1209"); + } + } + } + +bus(A_DOUT) { + + bus_type : D_15_0; + direction : output ; + capacitance : 0 ; + max_capacitance : 0.064 ; + memory_read() { + address : A_ADDR ; + } + pin(A_DOUT[15:0]) { + related_power_pin : VDD; + related_ground_pin : VSS; + internal_power() { + rise_power("scalar") { + values (0); + } + fall_power("scalar") { + values (0); + } + } + } + timing() { + related_pin : "A_CLK"; + timing_type : rising_edge ; + timing_sense : non_unate ; + + cell_rise(SIG2SRAM_delay_template) { + index_1("0.0056,0.0232,0.0400,0.0728,0.1280,0.2440,0.4760"); + index_2("0.0008,0.0014,0.0051,0.0100,0.0339,0.0640"); + values ("2.9823,2.9839,2.9915,3.0002,3.0326,3.0688",\ +"2.9886,2.9902,2.9979,3.0066,3.0390,3.0751",\ +"2.9907,2.9923,3.0000,3.0087,3.0411,3.0772",\ +"3.0038,3.0054,3.0130,3.0217,3.0541,3.0903",\ +"3.0100,3.0116,3.0192,3.0279,3.0603,3.0965",\ +"3.0414,3.0431,3.0507,3.0594,3.0918,3.1279",\ +"3.0960,3.0976,3.1052,3.1139,3.1463,3.1824"); + } + cell_fall(SIG2SRAM_delay_template) { + index_1("0.0056,0.0232,0.0400,0.0728,0.1280,0.2440,0.4760"); + index_2("0.0008,0.0014,0.0051,0.0100,0.0339,0.0640"); + values ("2.9220,2.9233,2.9294,2.9365,2.9630,2.9893",\ +"2.9284,2.9297,2.9358,2.9429,2.9694,2.9956",\ +"2.9305,2.9318,2.9379,2.9450,2.9715,2.9977",\ +"2.9435,2.9448,2.9509,2.9580,2.9845,3.0108",\ +"2.9497,2.9510,2.9571,2.9642,2.9907,3.0170",\ +"2.9812,2.9825,2.9886,2.9957,3.0222,3.0484",\ +"3.0357,3.0370,3.0431,3.0502,3.0767,3.1029"); + } + + rise_transition(SRAM_load_template) { + index_1("0.0008,0.0014,0.0051,0.0100,0.0339,0.0640"); + values ("0.0326,0.0341,0.0428,0.0518,0.0923,0.1492"); + } + fall_transition(SRAM_load_template) { + index_1("0.0008,0.0014,0.0051,0.0100,0.0339,0.0640"); + values ("0.0254,0.0265,0.0335,0.0402,0.0707,0.1039"); + } + } +} + pin(B_DLY) { + direction : input ; + capacitance : 0.00401111 ; + max_transition : "1" ; + related_power_pin : VDD; + related_ground_pin : VSS; + internal_power() { + rise_power("scalar") { + values (0); + } + fall_power("scalar") { + values (0); + } + } + } + +bus(B_ADDR) { + bus_type : A_7_0; + direction : input ; + capacitance : 0.0121077 ; + pin(B_ADDR[0]) { + capacitance : 0.00570093 ; + } + pin(B_ADDR[1]) { + capacitance : 0.00764555 ; + } + pin(B_ADDR[2]) { + capacitance : 0.0105375 ; + } + pin(B_ADDR[3]) { + capacitance : 0.0067894 ; + } + pin(B_ADDR[4]) { + capacitance : 0.00630967 ; + } + pin(B_ADDR[5]) { + capacitance : 0.0104132 ; + } + pin(B_ADDR[6]) { + capacitance : 0.0131402 ; + } + max_transition : "0.476" ; + pin(B_ADDR[7:0]) { + related_power_pin : VDD; + related_ground_pin : VSS; + internal_power() { + when : "B_MEN"; + rise_power("scalar"){ + values (0.0109); + } + fall_power("scalar"){ + values (0.0051); + } + } + internal_power() { + when : "!B_MEN"; + rise_power("scalar"){ + values (0.0190); + } + fall_power("scalar"){ + values (0.0000); + } + } + } + timing() { + timing_type : setup_rising; + related_pin : "B_CLK"; + when : "((B_WEN | B_REN)& B_MEN)" + sdf_cond : "B_RW_ACCESS" + + rise_constraint("SIG2SRAM_constraint_template") { + index_1("0.0056,0.0232,0.0400,0.0728,0.1280,0.2440,0.4760"); + index_2("0.0056,0.0232,0.0400,0.0728,0.1280,0.2440,0.4760"); + values ("-0.4168,-0.3973,-0.3855,-0.3543,-0.3074,-0.2020,-0.0027",\ +"-0.4324,-0.4129,-0.4012,-0.3699,-0.3191,-0.2176,-0.0184",\ +"-0.4441,-0.4285,-0.4129,-0.3816,-0.3309,-0.2293,-0.0301",\ +"-0.4793,-0.4598,-0.4441,-0.4129,-0.3660,-0.2645,-0.0652",\ +"-0.5223,-0.5066,-0.4910,-0.4598,-0.4129,-0.3074,-0.1121",\ +"-0.6199,-0.6082,-0.5926,-0.5613,-0.5145,-0.4129,-0.2137",\ +"-0.8191,-0.8074,-0.7840,-0.7566,-0.7098,-0.6082,-0.4051"); + } + + fall_constraint("SIG2SRAM_constraint_template") { + index_1("0.0056,0.0232,0.0400,0.0728,0.1280,0.2440,0.4760"); + index_2("0.0056,0.0232,0.0400,0.0728,0.1280,0.2440,0.4760"); + values ("-0.3309,-0.3113,-0.2996,-0.2684,-0.2176,-0.1238,0.0637",\ +"-0.3465,-0.3309,-0.3152,-0.2840,-0.2332,-0.1395,0.0480",\ +"-0.3582,-0.3426,-0.3270,-0.2996,-0.2488,-0.1512,0.0324",\ +"-0.3895,-0.3738,-0.3582,-0.3309,-0.2801,-0.1863,0.0051",\ +"-0.4363,-0.4207,-0.4051,-0.3777,-0.3230,-0.2293,-0.0379",\ +"-0.5379,-0.5223,-0.5066,-0.4793,-0.4285,-0.3309,-0.1434",\ +"-0.7332,-0.7176,-0.7020,-0.6746,-0.6238,-0.5262,-0.3387"); + } + } + + + timing() { + timing_type : hold_rising; + related_pin : "B_CLK"; + when : "((B_WEN | B_REN)& B_MEN)" + sdf_cond : "B_RW_ACCESS" + + rise_constraint("SIG2SRAM_constraint_template") { + index_1("0.0056,0.0232,0.0400,0.0728,0.1280,0.2440,0.4760"); + index_2("0.0056,0.0232,0.0400,0.0728,0.1280,0.2440,0.4760"); + values ("0.5246,0.5051,0.4895,0.4582,0.4113,0.3059,0.1066",\ +"0.5402,0.5207,0.5051,0.4777,0.4270,0.3215,0.1223",\ +"0.5520,0.5324,0.5168,0.4895,0.4387,0.3371,0.1340",\ +"0.5832,0.5676,0.5520,0.5207,0.4738,0.3684,0.1691",\ +"0.6301,0.6105,0.5949,0.5676,0.5168,0.4113,0.2160",\ +"0.7316,0.7121,0.7004,0.6691,0.6223,0.5168,0.3176",\ +"0.9270,0.9230,0.8957,0.8645,0.8137,0.7121,0.5168"); + } + + fall_constraint("SIG2SRAM_constraint_template") { + index_1("0.0056,0.0232,0.0400,0.0728,0.1280,0.2440,0.4760"); + index_2("0.0056,0.0232,0.0400,0.0728,0.1280,0.2440,0.4760"); + values ("0.4309,0.4152,0.4035,0.3684,0.3215,0.2277,0.0363",\ +"0.4465,0.4309,0.4152,0.3879,0.3371,0.2395,0.0559",\ +"0.4582,0.4426,0.4309,0.3996,0.3488,0.2551,0.0715",\ +"0.4934,0.4777,0.4621,0.4348,0.3840,0.2863,0.0988",\ +"0.5363,0.5207,0.5051,0.4777,0.4270,0.3332,0.1418",\ +"0.6379,0.6262,0.6105,0.5793,0.5324,0.4348,0.2434",\ +"0.8332,0.8215,0.8059,0.7707,0.7238,0.6301,0.4387"); + } + } +} +pin(B_WEN) { + direction : input ; + capacitance : 0.00324098 ; + max_transition : "0.476" ; + related_power_pin : VDD; + related_ground_pin : VSS; + internal_power() { + when : "B_MEN"; + rise_power("scalar"){ + values (0.0046); + } + fall_power("scalar"){ + values (0.0038); + } + } + internal_power() { + when : "!B_MEN"; + rise_power("scalar"){ + values (0.0042); + } + fall_power("scalar"){ + values (0.0039); + } + } + timing() { + timing_type : setup_rising; + related_pin : "B_CLK"; + when : "B_MEN" + sdf_cond : "B_MEN" + + rise_constraint("SIG2SRAM_constraint_template") { + index_1("0.0056,0.0232,0.0400,0.0728,0.1280,0.2440,0.4760"); + index_2("0.0056,0.0232,0.0400,0.0728,0.1280,0.2440,0.4760"); + values ("0.2043,0.2199,0.2316,0.2629,0.3059,0.4113,0.6066",\ +"0.1887,0.2043,0.2160,0.2473,0.2941,0.3957,0.5949",\ +"0.1691,0.1848,0.2004,0.2316,0.2785,0.3801,0.5754",\ +"0.1379,0.1574,0.1691,0.2004,0.2473,0.3527,0.5480",\ +"0.0910,0.1066,0.1223,0.1535,0.2004,0.2980,0.4973",\ +"-0.0105,0.0051,0.0207,0.0520,0.0949,0.2004,0.3957",\ +"-0.2059,-0.1902,-0.1746,-0.1473,-0.1004,0.0051,0.2004"); + } + + fall_constraint("SIG2SRAM_constraint_template") { + index_1("0.0056,0.0232,0.0400,0.0728,0.1280,0.2440,0.4760"); + index_2("0.0056,0.0232,0.0400,0.0728,0.1280,0.2440,0.4760"); + values ("0.2941,0.3098,0.3215,0.3488,0.4035,0.4973,0.6887",\ +"0.2785,0.2941,0.3059,0.3332,0.3840,0.4816,0.6691",\ +"0.2629,0.2785,0.2902,0.3176,0.3684,0.4660,0.6535",\ +"0.2316,0.2473,0.2590,0.2863,0.3410,0.4348,0.6262",\ +"0.1848,0.2004,0.2121,0.2395,0.2902,0.3879,0.5754",\ +"0.0832,0.0988,0.1105,0.1379,0.1809,0.2746,0.4699",\ +"-0.1121,-0.0965,-0.0848,-0.0535,-0.0066,0.0910,0.2824"); + } + } + + + timing() { + timing_type : hold_rising; + related_pin : "B_CLK"; + when : "B_MEN" + sdf_cond : "B_MEN" + + rise_constraint("SIG2SRAM_constraint_template") { + index_1("0.0056,0.0232,0.0400,0.0728,0.1280,0.2440,0.4760"); + index_2("0.0056,0.0232,0.0400,0.0728,0.1280,0.2440,0.4760"); + values ("0.2473,0.2316,0.2160,0.1887,0.1379,0.0363,-0.1629",\ +"0.2629,0.2473,0.2316,0.2043,0.1535,0.0520,-0.1473",\ +"0.2785,0.2590,0.2434,0.2160,0.1652,0.0676,-0.1355",\ +"0.3098,0.2941,0.2785,0.2473,0.1965,0.0910,-0.1043",\ +"0.3527,0.3371,0.3215,0.2941,0.2434,0.1418,-0.0574",\ +"0.4582,0.4426,0.4270,0.3957,0.3488,0.2434,0.0480",\ +"0.6535,0.6379,0.6184,0.5910,0.5402,0.4426,0.2434"); + } + + fall_constraint("SIG2SRAM_constraint_template") { + index_1("0.0056,0.0232,0.0400,0.0728,0.1280,0.2440,0.4760"); + index_2("0.0056,0.0232,0.0400,0.0728,0.1280,0.2440,0.4760"); + values ("0.2395,0.2238,0.2121,0.1809,0.1301,0.0324,-0.1551",\ +"0.2551,0.2395,0.2277,0.1965,0.1457,0.0480,-0.1395",\ +"0.2668,0.2551,0.2395,0.2082,0.1574,0.0637,-0.1277",\ +"0.3020,0.2863,0.2707,0.2395,0.1887,0.0910,-0.0965",\ +"0.3449,0.3293,0.3176,0.2863,0.2355,0.1379,-0.0496",\ +"0.4504,0.4348,0.4191,0.3879,0.3371,0.2395,0.0559",\ +"0.6457,0.6301,0.6145,0.5871,0.5324,0.4309,0.2512"); + } + } + } +pin(B_REN) { + direction : input ; + capacitance : 0.00381634 ; + max_transition : "0.476" ; + related_power_pin : VDD; + related_ground_pin : VSS; + internal_power() { + when : "B_MEN"; + rise_power("scalar"){ + values (0.0061); + } + fall_power("scalar"){ + values (0.0020); + } + } + internal_power() { + when : "!B_MEN"; + rise_power("scalar"){ + values (0.0062); + } + fall_power("scalar"){ + values (0.0025); + } + } + timing() { + timing_type : setup_rising; + related_pin : "B_CLK"; + when : "B_MEN" + sdf_cond : "B_MEN" + + rise_constraint("SIG2SRAM_constraint_template") { + index_1("0.0056,0.0232,0.0400,0.0728,0.1280,0.2440,0.4760"); + index_2("0.0056,0.0232,0.0400,0.0728,0.1280,0.2440,0.4760"); + values ("-0.0301,-0.0145,0.0012,0.0324,0.0793,0.1809,0.3762",\ +"-0.0457,-0.0301,-0.0145,0.0168,0.0637,0.1613,0.3605",\ +"-0.0574,-0.0418,-0.0262,0.0051,0.0520,0.1496,0.3449",\ +"-0.0926,-0.0730,-0.0574,-0.0262,0.0207,0.1184,0.3137",\ +"-0.1395,-0.1238,-0.1082,-0.0770,-0.0301,0.0715,0.2707",\ +"-0.2410,-0.2254,-0.2098,-0.1746,-0.1355,-0.0340,0.1652",\ +"-0.4402,-0.4207,-0.4051,-0.3738,-0.3270,-0.2293,-0.0340"); + } + + fall_constraint("SIG2SRAM_constraint_template") { + index_1("0.0056,0.0232,0.0400,0.0728,0.1280,0.2440,0.4760"); + index_2("0.0056,0.0232,0.0400,0.0728,0.1280,0.2440,0.4760"); + values ("0.0988,0.1145,0.1262,0.1535,0.2043,0.3020,0.4855",\ +"0.0832,0.0988,0.1105,0.1418,0.1848,0.2824,0.4738",\ +"0.0676,0.0832,0.0949,0.1262,0.1730,0.2668,0.4621",\ +"0.0402,0.0559,0.0676,0.0988,0.1457,0.2434,0.4191",\ +"-0.0105,0.0012,0.0168,0.0480,0.0988,0.1965,0.3840",\ +"-0.1160,-0.0965,-0.0848,-0.0535,-0.0066,0.0988,0.2824",\ +"-0.3113,-0.2957,-0.2801,-0.2527,-0.2059,-0.1043,0.0832"); + } + } + + + timing() { + timing_type : hold_rising; + related_pin : "B_CLK"; + when : "B_MEN" + sdf_cond : "B_MEN" + + rise_constraint("SIG2SRAM_constraint_template") { + index_1("0.0056,0.0232,0.0400,0.0728,0.1280,0.2440,0.4760"); + index_2("0.0056,0.0232,0.0400,0.0728,0.1280,0.2440,0.4760"); + values ("0.2707,0.2551,0.2395,0.2121,0.1613,0.0598,-0.1395",\ +"0.2863,0.2707,0.2551,0.2238,0.1730,0.0715,-0.1238",\ +"0.2980,0.2824,0.2668,0.2395,0.1887,0.0871,-0.1121",\ +"0.3332,0.3176,0.3020,0.2707,0.2199,0.1184,-0.0809",\ +"0.3762,0.3605,0.3449,0.3176,0.2668,0.1613,-0.0340",\ +"0.4816,0.4621,0.4504,0.4191,0.3723,0.2629,0.0715",\ +"0.6770,0.6613,0.6418,0.6184,0.5637,0.4699,0.2629"); + } + + fall_constraint("SIG2SRAM_constraint_template") { + index_1("0.0056,0.0232,0.0400,0.0728,0.1280,0.2440,0.4760"); + index_2("0.0056,0.0232,0.0400,0.0728,0.1280,0.2440,0.4760"); + values ("0.2590,0.2434,0.2316,0.2004,0.1457,0.0520,-0.1355",\ +"0.2746,0.2590,0.2434,0.2160,0.1613,0.0676,-0.1199",\ +"0.2863,0.2707,0.2590,0.2277,0.1730,0.0832,-0.1082",\ +"0.3215,0.3059,0.2902,0.2590,0.2082,0.1105,-0.0770",\ +"0.3645,0.3488,0.3332,0.3059,0.2551,0.1535,-0.0340",\ +"0.4699,0.4543,0.4387,0.4074,0.3605,0.2551,0.0715",\ +"0.6652,0.6496,0.6340,0.6027,0.5520,0.4621,0.2707"); + } + } + } +pin(B_MEN) { + direction : input ; + capacitance : 0.00309605 ; + max_transition : "0.476" ; + related_power_pin : VDD; + related_ground_pin : VSS; + internal_power() { + rise_power("scalar"){ + values (0.0447); + } + fall_power("scalar"){ + values (0.0052); + } + } + timing() { + timing_type : setup_rising; + related_pin : "B_CLK"; + + rise_constraint("SIG2SRAM_constraint_template") { + index_1("0.0056,0.0232,0.0400,0.0728,0.1280,0.2440,0.4760"); + index_2("0.0056,0.0232,0.0400,0.0728,0.1280,0.2440,0.4760"); + values ("0.2043,0.2199,0.2316,0.2668,0.3098,0.4152,0.6066",\ +"0.1887,0.2043,0.2199,0.2512,0.2941,0.3996,0.5949",\ +"0.1730,0.1887,0.2043,0.2355,0.2824,0.3840,0.5793",\ +"0.1418,0.1574,0.1730,0.2043,0.2512,0.3566,0.5480",\ +"0.0949,0.1105,0.1262,0.1574,0.2043,0.3020,0.5051",\ +"-0.0066,0.0090,0.0246,0.0520,0.0988,0.2043,0.3996",\ +"-0.2020,-0.1863,-0.1746,-0.1434,-0.0965,0.0090,0.2082"); + } + + fall_constraint("SIG2SRAM_constraint_template") { + index_1("0.0056,0.0232,0.0400,0.0728,0.1280,0.2440,0.4760"); + index_2("0.0056,0.0232,0.0400,0.0728,0.1280,0.2440,0.4760"); + values ("0.2980,0.3137,0.3254,0.3527,0.4035,0.5012,0.6887",\ +"0.2824,0.2980,0.3098,0.3371,0.3879,0.4855,0.6730",\ +"0.2668,0.2824,0.2941,0.3215,0.3723,0.4699,0.6574",\ +"0.2355,0.2473,0.2629,0.2902,0.3410,0.4387,0.6262",\ +"0.1887,0.2004,0.2160,0.2395,0.2941,0.3918,0.5793",\ +"0.0871,0.1027,0.1145,0.1418,0.1848,0.2746,0.4816",\ +"-0.1082,-0.0965,-0.0809,-0.0496,-0.0027,0.0949,0.2863"); + } + } + + + timing() { + timing_type : hold_rising; + related_pin : "B_CLK"; + + rise_constraint("SIG2SRAM_constraint_template") { + index_1("0.0056,0.0232,0.0400,0.0728,0.1280,0.2440,0.4760"); + index_2("0.0056,0.0232,0.0400,0.0728,0.1280,0.2440,0.4760"); + values ("0.2512,0.2355,0.2199,0.1926,0.1418,0.0402,-0.1590",\ +"0.2668,0.2512,0.2355,0.2082,0.1574,0.0559,-0.1434",\ +"0.2824,0.2629,0.2512,0.2199,0.1691,0.0715,-0.1316",\ +"0.3137,0.2980,0.2824,0.2512,0.2004,0.0988,-0.0965",\ +"0.3566,0.3410,0.3254,0.2980,0.2473,0.1418,-0.0535",\ +"0.4621,0.4426,0.4309,0.3996,0.3527,0.2473,0.0520",\ +"0.6574,0.6418,0.6262,0.5949,0.5441,0.4465,0.2473"); + } + + fall_constraint("SIG2SRAM_constraint_template") { + index_1("0.0056,0.0232,0.0400,0.0728,0.1280,0.2440,0.4760"); + index_2("0.0056,0.0232,0.0400,0.0728,0.1280,0.2440,0.4760"); + values ("0.2395,0.2238,0.2121,0.1809,0.1301,0.0324,-0.1551",\ +"0.2551,0.2434,0.2277,0.1965,0.1457,0.0480,-0.1395",\ +"0.2707,0.2551,0.2395,0.2082,0.1574,0.0637,-0.1277",\ +"0.3020,0.2863,0.2707,0.2434,0.1926,0.0910,-0.0965",\ +"0.3449,0.3332,0.3176,0.2863,0.2355,0.1379,-0.0496",\ +"0.4504,0.4348,0.4230,0.3918,0.3410,0.2434,0.0559",\ +"0.6457,0.6301,0.6145,0.5910,0.5324,0.4387,0.2512"); + } + } + } +bus(B_BM) { + bus_type : D_15_0; + direction : input ; + capacitance : 0.00312518 ; + max_transition : "0.476" ; + pin(B_BM[15:0]) { + related_power_pin : VDD; + related_ground_pin : VSS; + internal_power() { + when : "B_MEN"; + rise_power("scalar"){ + values (0.0591); + } + fall_power("scalar"){ + values (0.0246); + } + } + internal_power() { + when : "!B_MEN"; + rise_power("scalar"){ + values (0.0602); + } + fall_power("scalar"){ + values (0.0244); + } + } + } + timing() { + timing_type : setup_rising; + related_pin : "B_CLK"; + when : "(B_WEN & B_MEN)" + sdf_cond : "B_RW_ACCESS" + + rise_constraint("SIG2SRAM_constraint_template") { + index_1("0.0056,0.0232,0.0400,0.0728,0.1280,0.2440,0.4760"); + index_2("0.0056,0.0232,0.0400,0.0728,0.1280,0.2440,0.4760"); + values ("-0.3235,-0.3079,-0.2952,-0.2620,-0.2132,-0.1145,0.0788",\ +"-0.3285,-0.3129,-0.3002,-0.2670,-0.2182,-0.1195,0.0738",\ +"-0.3330,-0.3174,-0.3047,-0.2715,-0.2226,-0.1240,0.0693",\ +"-0.3421,-0.3265,-0.3138,-0.2806,-0.2318,-0.1331,0.0602",\ +"-0.3493,-0.3337,-0.3210,-0.2878,-0.2390,-0.1403,0.0530",\ +"-0.3790,-0.3634,-0.3507,-0.3175,-0.2686,-0.1700,0.0234",\ +"-0.4370,-0.4214,-0.4087,-0.3755,-0.3267,-0.2281,-0.0347"); + } + + fall_constraint("SIG2SRAM_constraint_template") { + index_1("0.0056,0.0232,0.0400,0.0728,0.1280,0.2440,0.4760"); + index_2("0.0056,0.0232,0.0400,0.0728,0.1280,0.2440,0.4760"); + values ("-0.2893,-0.2747,-0.2610,-0.2327,-0.1829,-0.0843,0.0954",\ +"-0.2943,-0.2797,-0.2660,-0.2377,-0.1879,-0.0893,0.0904",\ +"-0.2988,-0.2842,-0.2705,-0.2422,-0.1924,-0.0937,0.0859",\ +"-0.3079,-0.2933,-0.2796,-0.2513,-0.2015,-0.1029,0.0768",\ +"-0.3151,-0.3005,-0.2868,-0.2585,-0.2087,-0.1101,0.0696",\ +"-0.3448,-0.3301,-0.3165,-0.2882,-0.2384,-0.1397,0.0400",\ +"-0.4029,-0.3882,-0.3745,-0.3462,-0.2964,-0.1978,-0.0181"); + } + } + + + timing() { + timing_type : hold_rising; + related_pin : "B_CLK"; + when : "(B_WEN & B_MEN)" + sdf_cond : "B_RW_ACCESS" + + rise_constraint("SIG2SRAM_constraint_template") { + index_1("0.0056,0.0232,0.0400,0.0728,0.1280,0.2440,0.4760"); + index_2("0.0056,0.0232,0.0400,0.0728,0.1280,0.2440,0.4760"); + values ("0.4331,0.4175,0.4048,0.3716,0.3237,0.2241,0.0298",\ +"0.4381,0.4225,0.4098,0.3766,0.3287,0.2291,0.0348",\ +"0.4426,0.4270,0.4143,0.3811,0.3332,0.2336,0.0393",\ +"0.4517,0.4361,0.4234,0.3902,0.3423,0.2427,0.0484",\ +"0.4589,0.4433,0.4306,0.3974,0.3495,0.2499,0.0556",\ +"0.4886,0.4729,0.4602,0.4270,0.3792,0.2796,0.0853",\ +"0.5466,0.5310,0.5183,0.4851,0.4373,0.3376,0.1433"); + } + + fall_constraint("SIG2SRAM_constraint_template") { + index_1("0.0056,0.0232,0.0400,0.0728,0.1280,0.2440,0.4760"); + index_2("0.0056,0.0232,0.0400,0.0728,0.1280,0.2440,0.4760"); + values ("0.3921,0.3774,0.3628,0.3345,0.2837,0.1919,0.0073",\ +"0.3971,0.3824,0.3678,0.3395,0.2887,0.1969,0.0123",\ +"0.4016,0.3869,0.3723,0.3440,0.2932,0.2014,0.0168",\ +"0.4107,0.3960,0.3814,0.3531,0.3023,0.2105,0.0259",\ +"0.4179,0.4032,0.3886,0.3603,0.3095,0.2177,0.0331",\ +"0.4476,0.4329,0.4183,0.3899,0.3392,0.2474,0.0628",\ +"0.5056,0.4910,0.4763,0.4480,0.3972,0.3054,0.1209"); + } + } +} + pin(B_CLK) { + direction : input; + capacitance : 0.00380014; + max_transition : "0.476"; + clock : "true" ; + pin_func_type : active_rising ; + + timing () { + timing_type : "min_pulse_width"; + related_pin : "B_CLK"; + rise_constraint("CLKTRAN_constraint_template") { + index_1("0.0056,0.476"); + values("0.21,0.21"); + } + } + + related_power_pin : VDD; + related_ground_pin : VSS; + + internal_power() { + when : "!B_MEN & !B_WEN & !B_REN"; + rise_power("scalar"){ + values (0); + } + fall_power("scalar"){ + values (0); + } + } + internal_power() { + when : "!B_MEN & B_WEN & !B_REN"; + rise_power("scalar"){ + values (0.4920); + } + fall_power("scalar"){ + values (0); + } + } + internal_power() { + when : "B_MEN & B_WEN & !B_REN"; + rise_power("scalar"){ + values (18.4562); + } + fall_power("scalar"){ + values (0); + } + } + internal_power() { + when : "B_MEN & B_WEN & B_REN"; + rise_power("scalar"){ + values (20.3138); + } + fall_power("scalar"){ + values (0); + } + } + internal_power() { + when : "B_MEN & !B_WEN & B_REN"; + rise_power("scalar"){ + values (14.1920); + } + fall_power("scalar"){ + values (0); + } + } + internal_power() { + when : "!B_MEN & !B_WEN & B_REN"; + rise_power("scalar"){ + values (0.2984); + } + fall_power("scalar"){ + values (0); + } + } + internal_power() { + when : "!B_MEN & B_WEN & B_REN"; + rise_power("scalar"){ + values (0.7334); + } + fall_power("scalar"){ + values (0); + } + } + internal_power() { + when : "B_MEN & !B_WEN & !B_REN"; + rise_power("scalar"){ + values (0); + } + fall_power("scalar"){ + values (0); + } + } + } + bus(B_DIN) { + bus_type : D_15_0; + direction : input ; + capacitance : 0.00461776 ; + memory_write() { + address : B_ADDR ; + clocked_on : B_CLK; + } + + max_transition : "0.476" ; + pin(B_DIN[15:0]) { + related_power_pin : VDD; + related_ground_pin : VSS; + internal_power() { + when : "B_MEN"; + rise_power("scalar"){ + values (0.0591); + } + fall_power("scalar"){ + values (0.0246); + } + } + internal_power() { + when : "!B_MEN"; + rise_power("scalar"){ + values (0.0602); + } + fall_power("scalar"){ + values (0.0244); + } + } + } + timing() { + timing_type : setup_rising; + related_pin : "B_CLK"; + when : "(B_WEN & B_MEN)"; + sdf_cond : "B_W_ACCESS"; + + rise_constraint("SIG2SRAM_constraint_template") { + index_1("0.0056,0.0232,0.0400,0.0728,0.1280,0.2440,0.4760"); + index_2("0.0056,0.0232,0.0400,0.0728,0.1280,0.2440,0.4760"); + values ("-0.3235,-0.3079,-0.2952,-0.2620,-0.2132,-0.1145,0.0788",\ +"-0.3285,-0.3129,-0.3002,-0.2670,-0.2182,-0.1195,0.0738",\ +"-0.3330,-0.3174,-0.3047,-0.2715,-0.2226,-0.1240,0.0693",\ +"-0.3421,-0.3265,-0.3138,-0.2806,-0.2318,-0.1331,0.0602",\ +"-0.3493,-0.3337,-0.3210,-0.2878,-0.2390,-0.1403,0.0530",\ +"-0.3790,-0.3634,-0.3507,-0.3175,-0.2686,-0.1700,0.0234",\ +"-0.4370,-0.4214,-0.4087,-0.3755,-0.3267,-0.2281,-0.0347"); + } + + fall_constraint("SIG2SRAM_constraint_template") { + index_1("0.0056,0.0232,0.0400,0.0728,0.1280,0.2440,0.4760"); + index_2("0.0056,0.0232,0.0400,0.0728,0.1280,0.2440,0.4760"); + values ("-0.2893,-0.2747,-0.2610,-0.2327,-0.1829,-0.0843,0.0954",\ +"-0.2943,-0.2797,-0.2660,-0.2377,-0.1879,-0.0893,0.0904",\ +"-0.2988,-0.2842,-0.2705,-0.2422,-0.1924,-0.0937,0.0859",\ +"-0.3079,-0.2933,-0.2796,-0.2513,-0.2015,-0.1029,0.0768",\ +"-0.3151,-0.3005,-0.2868,-0.2585,-0.2087,-0.1101,0.0696",\ +"-0.3448,-0.3301,-0.3165,-0.2882,-0.2384,-0.1397,0.0400",\ +"-0.4029,-0.3882,-0.3745,-0.3462,-0.2964,-0.1978,-0.0181"); + } + } + + timing() { + timing_type : hold_rising; + related_pin : "B_CLK"; + when : "(B_WEN & B_MEN)"; + sdf_cond : "B_W_ACCESS"; + + rise_constraint("SIG2SRAM_constraint_template") { + index_1("0.0056,0.0232,0.0400,0.0728,0.1280,0.2440,0.4760"); + index_2("0.0056,0.0232,0.0400,0.0728,0.1280,0.2440,0.4760"); + values ("0.4331,0.4175,0.4048,0.3716,0.3237,0.2241,0.0298",\ +"0.4381,0.4225,0.4098,0.3766,0.3287,0.2291,0.0348",\ +"0.4426,0.4270,0.4143,0.3811,0.3332,0.2336,0.0393",\ +"0.4517,0.4361,0.4234,0.3902,0.3423,0.2427,0.0484",\ +"0.4589,0.4433,0.4306,0.3974,0.3495,0.2499,0.0556",\ +"0.4886,0.4729,0.4602,0.4270,0.3792,0.2796,0.0853",\ +"0.5466,0.5310,0.5183,0.4851,0.4373,0.3376,0.1433"); + } + + fall_constraint("SIG2SRAM_constraint_template") { + index_1("0.0056,0.0232,0.0400,0.0728,0.1280,0.2440,0.4760"); + index_2("0.0056,0.0232,0.0400,0.0728,0.1280,0.2440,0.4760"); + values ("0.3921,0.3774,0.3628,0.3345,0.2837,0.1919,0.0073",\ +"0.3971,0.3824,0.3678,0.3395,0.2887,0.1969,0.0123",\ +"0.4016,0.3869,0.3723,0.3440,0.2932,0.2014,0.0168",\ +"0.4107,0.3960,0.3814,0.3531,0.3023,0.2105,0.0259",\ +"0.4179,0.4032,0.3886,0.3603,0.3095,0.2177,0.0331",\ +"0.4476,0.4329,0.4183,0.3899,0.3392,0.2474,0.0628",\ +"0.5056,0.4910,0.4763,0.4480,0.3972,0.3054,0.1209"); + } + } + } + + pin(B_BIST_EN) { + direction : input ; + capacitance : 0.00401111 ; + max_transition : "1" ; + related_power_pin : VDD; + related_ground_pin : VSS; + internal_power() { + rise_power("scalar") { + values (0); + } + fall_power("scalar") { + values (0); + } + } + } + +bus(B_BIST_ADDR) { + bus_type : A_7_0; + direction : input ; + capacitance : 0.0121077 ; + pin(B_BIST_ADDR[0]) { + capacitance : 0.00570093 ; + } + pin(B_BIST_ADDR[1]) { + capacitance : 0.00764555 ; + } + pin(B_BIST_ADDR[2]) { + capacitance : 0.0105375 ; + } + pin(B_BIST_ADDR[3]) { + capacitance : 0.0067894 ; + } + pin(B_BIST_ADDR[4]) { + capacitance : 0.00630967 ; + } + pin(B_BIST_ADDR[5]) { + capacitance : 0.0104132 ; + } + pin(B_BIST_ADDR[6]) { + capacitance : 0.0131402 ; + } + max_transition : "0.476" ; + pin(B_BIST_ADDR[7:0]) { + related_power_pin : VDD; + related_ground_pin : VSS; + internal_power() { + when : "B_BIST_MEN"; + rise_power("scalar"){ + values (0.0109); + } + fall_power("scalar"){ + values (0.0051); + } + } + internal_power() { + when : "!B_BIST_MEN"; + rise_power("scalar"){ + values (0.0190); + } + fall_power("scalar"){ + values (0.0000); + } + } + } + timing() { + timing_type : setup_rising; + related_pin : "B_BIST_CLK"; + when : "((B_BIST_WEN | B_BIST_REN)& B_BIST_MEN)" + sdf_cond : "B_BIST_RW_ACCESS" + + rise_constraint("SIG2SRAM_constraint_template") { + index_1("0.0056,0.0232,0.0400,0.0728,0.1280,0.2440,0.4760"); + index_2("0.0056,0.0232,0.0400,0.0728,0.1280,0.2440,0.4760"); + values ("-0.4168,-0.3973,-0.3855,-0.3543,-0.3074,-0.2020,-0.0027",\ +"-0.4324,-0.4129,-0.4012,-0.3699,-0.3191,-0.2176,-0.0184",\ +"-0.4441,-0.4285,-0.4129,-0.3816,-0.3309,-0.2293,-0.0301",\ +"-0.4793,-0.4598,-0.4441,-0.4129,-0.3660,-0.2645,-0.0652",\ +"-0.5223,-0.5066,-0.4910,-0.4598,-0.4129,-0.3074,-0.1121",\ +"-0.6199,-0.6082,-0.5926,-0.5613,-0.5145,-0.4129,-0.2137",\ +"-0.8191,-0.8074,-0.7840,-0.7566,-0.7098,-0.6082,-0.4051"); + } + + fall_constraint("SIG2SRAM_constraint_template") { + index_1("0.0056,0.0232,0.0400,0.0728,0.1280,0.2440,0.4760"); + index_2("0.0056,0.0232,0.0400,0.0728,0.1280,0.2440,0.4760"); + values ("-0.3309,-0.3113,-0.2996,-0.2684,-0.2176,-0.1238,0.0637",\ +"-0.3465,-0.3309,-0.3152,-0.2840,-0.2332,-0.1395,0.0480",\ +"-0.3582,-0.3426,-0.3270,-0.2996,-0.2488,-0.1512,0.0324",\ +"-0.3895,-0.3738,-0.3582,-0.3309,-0.2801,-0.1863,0.0051",\ +"-0.4363,-0.4207,-0.4051,-0.3777,-0.3230,-0.2293,-0.0379",\ +"-0.5379,-0.5223,-0.5066,-0.4793,-0.4285,-0.3309,-0.1434",\ +"-0.7332,-0.7176,-0.7020,-0.6746,-0.6238,-0.5262,-0.3387"); + } + } + + + timing() { + timing_type : hold_rising; + related_pin : "B_BIST_CLK"; + when : "((B_BIST_WEN | B_BIST_REN)& B_BIST_MEN)" + sdf_cond : "B_BIST_RW_ACCESS" + + rise_constraint("SIG2SRAM_constraint_template") { + index_1("0.0056,0.0232,0.0400,0.0728,0.1280,0.2440,0.4760"); + index_2("0.0056,0.0232,0.0400,0.0728,0.1280,0.2440,0.4760"); + values ("0.5246,0.5051,0.4895,0.4582,0.4113,0.3059,0.1066",\ +"0.5402,0.5207,0.5051,0.4777,0.4270,0.3215,0.1223",\ +"0.5520,0.5324,0.5168,0.4895,0.4387,0.3371,0.1340",\ +"0.5832,0.5676,0.5520,0.5207,0.4738,0.3684,0.1691",\ +"0.6301,0.6105,0.5949,0.5676,0.5168,0.4113,0.2160",\ +"0.7316,0.7121,0.7004,0.6691,0.6223,0.5168,0.3176",\ +"0.9270,0.9230,0.8957,0.8645,0.8137,0.7121,0.5168"); + } + + fall_constraint("SIG2SRAM_constraint_template") { + index_1("0.0056,0.0232,0.0400,0.0728,0.1280,0.2440,0.4760"); + index_2("0.0056,0.0232,0.0400,0.0728,0.1280,0.2440,0.4760"); + values ("0.4309,0.4152,0.4035,0.3684,0.3215,0.2277,0.0363",\ +"0.4465,0.4309,0.4152,0.3879,0.3371,0.2395,0.0559",\ +"0.4582,0.4426,0.4309,0.3996,0.3488,0.2551,0.0715",\ +"0.4934,0.4777,0.4621,0.4348,0.3840,0.2863,0.0988",\ +"0.5363,0.5207,0.5051,0.4777,0.4270,0.3332,0.1418",\ +"0.6379,0.6262,0.6105,0.5793,0.5324,0.4348,0.2434",\ +"0.8332,0.8215,0.8059,0.7707,0.7238,0.6301,0.4387"); + } + } +} +pin(B_BIST_WEN) { + direction : input ; + capacitance : 0.00324098 ; + max_transition : "0.476" ; + related_power_pin : VDD; + related_ground_pin : VSS; + internal_power() { + when : "B_BIST_MEN"; + rise_power("scalar"){ + values (0.0046); + } + fall_power("scalar"){ + values (0.0038); + } + } + internal_power() { + when : "!B_BIST_MEN"; + rise_power("scalar"){ + values (0.0042); + } + fall_power("scalar"){ + values (0.0039); + } + } + timing() { + timing_type : setup_rising; + related_pin : "B_BIST_CLK"; + when : "B_BIST_MEN" + sdf_cond : "B_BIST_MEN" + + rise_constraint("SIG2SRAM_constraint_template") { + index_1("0.0056,0.0232,0.0400,0.0728,0.1280,0.2440,0.4760"); + index_2("0.0056,0.0232,0.0400,0.0728,0.1280,0.2440,0.4760"); + values ("0.2043,0.2199,0.2316,0.2629,0.3059,0.4113,0.6066",\ +"0.1887,0.2043,0.2160,0.2473,0.2941,0.3957,0.5949",\ +"0.1691,0.1848,0.2004,0.2316,0.2785,0.3801,0.5754",\ +"0.1379,0.1574,0.1691,0.2004,0.2473,0.3527,0.5480",\ +"0.0910,0.1066,0.1223,0.1535,0.2004,0.2980,0.4973",\ +"-0.0105,0.0051,0.0207,0.0520,0.0949,0.2004,0.3957",\ +"-0.2059,-0.1902,-0.1746,-0.1473,-0.1004,0.0051,0.2004"); + } + + fall_constraint("SIG2SRAM_constraint_template") { + index_1("0.0056,0.0232,0.0400,0.0728,0.1280,0.2440,0.4760"); + index_2("0.0056,0.0232,0.0400,0.0728,0.1280,0.2440,0.4760"); + values ("0.2941,0.3098,0.3215,0.3488,0.4035,0.4973,0.6887",\ +"0.2785,0.2941,0.3059,0.3332,0.3840,0.4816,0.6691",\ +"0.2629,0.2785,0.2902,0.3176,0.3684,0.4660,0.6535",\ +"0.2316,0.2473,0.2590,0.2863,0.3410,0.4348,0.6262",\ +"0.1848,0.2004,0.2121,0.2395,0.2902,0.3879,0.5754",\ +"0.0832,0.0988,0.1105,0.1379,0.1809,0.2746,0.4699",\ +"-0.1121,-0.0965,-0.0848,-0.0535,-0.0066,0.0910,0.2824"); + } + } + + + timing() { + timing_type : hold_rising; + related_pin : "B_BIST_CLK"; + when : "B_BIST_MEN" + sdf_cond : "B_BIST_MEN" + + rise_constraint("SIG2SRAM_constraint_template") { + index_1("0.0056,0.0232,0.0400,0.0728,0.1280,0.2440,0.4760"); + index_2("0.0056,0.0232,0.0400,0.0728,0.1280,0.2440,0.4760"); + values ("0.2473,0.2316,0.2160,0.1887,0.1379,0.0363,-0.1629",\ +"0.2629,0.2473,0.2316,0.2043,0.1535,0.0520,-0.1473",\ +"0.2785,0.2590,0.2434,0.2160,0.1652,0.0676,-0.1355",\ +"0.3098,0.2941,0.2785,0.2473,0.1965,0.0910,-0.1043",\ +"0.3527,0.3371,0.3215,0.2941,0.2434,0.1418,-0.0574",\ +"0.4582,0.4426,0.4270,0.3957,0.3488,0.2434,0.0480",\ +"0.6535,0.6379,0.6184,0.5910,0.5402,0.4426,0.2434"); + } + + fall_constraint("SIG2SRAM_constraint_template") { + index_1("0.0056,0.0232,0.0400,0.0728,0.1280,0.2440,0.4760"); + index_2("0.0056,0.0232,0.0400,0.0728,0.1280,0.2440,0.4760"); + values ("0.2395,0.2238,0.2121,0.1809,0.1301,0.0324,-0.1551",\ +"0.2551,0.2395,0.2277,0.1965,0.1457,0.0480,-0.1395",\ +"0.2668,0.2551,0.2395,0.2082,0.1574,0.0637,-0.1277",\ +"0.3020,0.2863,0.2707,0.2395,0.1887,0.0910,-0.0965",\ +"0.3449,0.3293,0.3176,0.2863,0.2355,0.1379,-0.0496",\ +"0.4504,0.4348,0.4191,0.3879,0.3371,0.2395,0.0559",\ +"0.6457,0.6301,0.6145,0.5871,0.5324,0.4309,0.2512"); + } + } + } +pin(B_BIST_REN) { + direction : input ; + capacitance : 0.00381634 ; + max_transition : "0.476" ; + related_power_pin : VDD; + related_ground_pin : VSS; + internal_power() { + when : "B_BIST_MEN"; + rise_power("scalar"){ + values (0.0061); + } + fall_power("scalar"){ + values (0.0020); + } + } + internal_power() { + when : "!B_BIST_MEN"; + rise_power("scalar"){ + values (0.0062); + } + fall_power("scalar"){ + values (0.0025); + } + } + timing() { + timing_type : setup_rising; + related_pin : "B_BIST_CLK"; + when : "B_BIST_MEN" + sdf_cond : "B_BIST_MEN" + + rise_constraint("SIG2SRAM_constraint_template") { + index_1("0.0056,0.0232,0.0400,0.0728,0.1280,0.2440,0.4760"); + index_2("0.0056,0.0232,0.0400,0.0728,0.1280,0.2440,0.4760"); + values ("-0.0301,-0.0145,0.0012,0.0324,0.0793,0.1809,0.3762",\ +"-0.0457,-0.0301,-0.0145,0.0168,0.0637,0.1613,0.3605",\ +"-0.0574,-0.0418,-0.0262,0.0051,0.0520,0.1496,0.3449",\ +"-0.0926,-0.0730,-0.0574,-0.0262,0.0207,0.1184,0.3137",\ +"-0.1395,-0.1238,-0.1082,-0.0770,-0.0301,0.0715,0.2707",\ +"-0.2410,-0.2254,-0.2098,-0.1746,-0.1355,-0.0340,0.1652",\ +"-0.4402,-0.4207,-0.4051,-0.3738,-0.3270,-0.2293,-0.0340"); + } + + fall_constraint("SIG2SRAM_constraint_template") { + index_1("0.0056,0.0232,0.0400,0.0728,0.1280,0.2440,0.4760"); + index_2("0.0056,0.0232,0.0400,0.0728,0.1280,0.2440,0.4760"); + values ("0.0988,0.1145,0.1262,0.1535,0.2043,0.3020,0.4855",\ +"0.0832,0.0988,0.1105,0.1418,0.1848,0.2824,0.4738",\ +"0.0676,0.0832,0.0949,0.1262,0.1730,0.2668,0.4621",\ +"0.0402,0.0559,0.0676,0.0988,0.1457,0.2434,0.4191",\ +"-0.0105,0.0012,0.0168,0.0480,0.0988,0.1965,0.3840",\ +"-0.1160,-0.0965,-0.0848,-0.0535,-0.0066,0.0988,0.2824",\ +"-0.3113,-0.2957,-0.2801,-0.2527,-0.2059,-0.1043,0.0832"); + } + } + + + timing() { + timing_type : hold_rising; + related_pin : "B_BIST_CLK"; + when : "B_BIST_MEN" + sdf_cond : "B_BIST_MEN" + + rise_constraint("SIG2SRAM_constraint_template") { + index_1("0.0056,0.0232,0.0400,0.0728,0.1280,0.2440,0.4760"); + index_2("0.0056,0.0232,0.0400,0.0728,0.1280,0.2440,0.4760"); + values ("0.2707,0.2551,0.2395,0.2121,0.1613,0.0598,-0.1395",\ +"0.2863,0.2707,0.2551,0.2238,0.1730,0.0715,-0.1238",\ +"0.2980,0.2824,0.2668,0.2395,0.1887,0.0871,-0.1121",\ +"0.3332,0.3176,0.3020,0.2707,0.2199,0.1184,-0.0809",\ +"0.3762,0.3605,0.3449,0.3176,0.2668,0.1613,-0.0340",\ +"0.4816,0.4621,0.4504,0.4191,0.3723,0.2629,0.0715",\ +"0.6770,0.6613,0.6418,0.6184,0.5637,0.4699,0.2629"); + } + + fall_constraint("SIG2SRAM_constraint_template") { + index_1("0.0056,0.0232,0.0400,0.0728,0.1280,0.2440,0.4760"); + index_2("0.0056,0.0232,0.0400,0.0728,0.1280,0.2440,0.4760"); + values ("0.2590,0.2434,0.2316,0.2004,0.1457,0.0520,-0.1355",\ +"0.2746,0.2590,0.2434,0.2160,0.1613,0.0676,-0.1199",\ +"0.2863,0.2707,0.2590,0.2277,0.1730,0.0832,-0.1082",\ +"0.3215,0.3059,0.2902,0.2590,0.2082,0.1105,-0.0770",\ +"0.3645,0.3488,0.3332,0.3059,0.2551,0.1535,-0.0340",\ +"0.4699,0.4543,0.4387,0.4074,0.3605,0.2551,0.0715",\ +"0.6652,0.6496,0.6340,0.6027,0.5520,0.4621,0.2707"); + } + } + } +pin(B_BIST_MEN) { + direction : input ; + capacitance : 0.00309605 ; + max_transition : "0.476" ; + related_power_pin : VDD; + related_ground_pin : VSS; + internal_power() { + rise_power("scalar"){ + values (0.0447); + } + fall_power("scalar"){ + values (0.0052); + } + } + timing() { + timing_type : setup_rising; + related_pin : "B_BIST_CLK"; + + rise_constraint("SIG2SRAM_constraint_template") { + index_1("0.0056,0.0232,0.0400,0.0728,0.1280,0.2440,0.4760"); + index_2("0.0056,0.0232,0.0400,0.0728,0.1280,0.2440,0.4760"); + values ("0.2043,0.2199,0.2316,0.2668,0.3098,0.4152,0.6066",\ +"0.1887,0.2043,0.2199,0.2512,0.2941,0.3996,0.5949",\ +"0.1730,0.1887,0.2043,0.2355,0.2824,0.3840,0.5793",\ +"0.1418,0.1574,0.1730,0.2043,0.2512,0.3566,0.5480",\ +"0.0949,0.1105,0.1262,0.1574,0.2043,0.3020,0.5051",\ +"-0.0066,0.0090,0.0246,0.0520,0.0988,0.2043,0.3996",\ +"-0.2020,-0.1863,-0.1746,-0.1434,-0.0965,0.0090,0.2082"); + } + + fall_constraint("SIG2SRAM_constraint_template") { + index_1("0.0056,0.0232,0.0400,0.0728,0.1280,0.2440,0.4760"); + index_2("0.0056,0.0232,0.0400,0.0728,0.1280,0.2440,0.4760"); + values ("0.2980,0.3137,0.3254,0.3527,0.4035,0.5012,0.6887",\ +"0.2824,0.2980,0.3098,0.3371,0.3879,0.4855,0.6730",\ +"0.2668,0.2824,0.2941,0.3215,0.3723,0.4699,0.6574",\ +"0.2355,0.2473,0.2629,0.2902,0.3410,0.4387,0.6262",\ +"0.1887,0.2004,0.2160,0.2395,0.2941,0.3918,0.5793",\ +"0.0871,0.1027,0.1145,0.1418,0.1848,0.2746,0.4816",\ +"-0.1082,-0.0965,-0.0809,-0.0496,-0.0027,0.0949,0.2863"); + } + } + + + timing() { + timing_type : hold_rising; + related_pin : "B_BIST_CLK"; + + rise_constraint("SIG2SRAM_constraint_template") { + index_1("0.0056,0.0232,0.0400,0.0728,0.1280,0.2440,0.4760"); + index_2("0.0056,0.0232,0.0400,0.0728,0.1280,0.2440,0.4760"); + values ("0.2512,0.2355,0.2199,0.1926,0.1418,0.0402,-0.1590",\ +"0.2668,0.2512,0.2355,0.2082,0.1574,0.0559,-0.1434",\ +"0.2824,0.2629,0.2512,0.2199,0.1691,0.0715,-0.1316",\ +"0.3137,0.2980,0.2824,0.2512,0.2004,0.0988,-0.0965",\ +"0.3566,0.3410,0.3254,0.2980,0.2473,0.1418,-0.0535",\ +"0.4621,0.4426,0.4309,0.3996,0.3527,0.2473,0.0520",\ +"0.6574,0.6418,0.6262,0.5949,0.5441,0.4465,0.2473"); + } + + fall_constraint("SIG2SRAM_constraint_template") { + index_1("0.0056,0.0232,0.0400,0.0728,0.1280,0.2440,0.4760"); + index_2("0.0056,0.0232,0.0400,0.0728,0.1280,0.2440,0.4760"); + values ("0.2395,0.2238,0.2121,0.1809,0.1301,0.0324,-0.1551",\ +"0.2551,0.2434,0.2277,0.1965,0.1457,0.0480,-0.1395",\ +"0.2707,0.2551,0.2395,0.2082,0.1574,0.0637,-0.1277",\ +"0.3020,0.2863,0.2707,0.2434,0.1926,0.0910,-0.0965",\ +"0.3449,0.3332,0.3176,0.2863,0.2355,0.1379,-0.0496",\ +"0.4504,0.4348,0.4230,0.3918,0.3410,0.2434,0.0559",\ +"0.6457,0.6301,0.6145,0.5910,0.5324,0.4387,0.2512"); + } + } + } +bus(B_BIST_BM) { + bus_type : D_15_0; + direction : input ; + capacitance : 0.00275526 ; + max_transition : "0.476" ; + pin(B_BIST_BM[15:0]) { + related_power_pin : VDD; + related_ground_pin : VSS; + internal_power() { + when : "B_BIST_MEN"; + rise_power("scalar"){ + values (0.0591); + } + fall_power("scalar"){ + values (0.0246); + } + } + internal_power() { + when : "!B_BIST_MEN"; + rise_power("scalar"){ + values (0.0602); + } + fall_power("scalar"){ + values (0.0244); + } + } + } + timing() { + timing_type : setup_rising; + related_pin : "B_BIST_CLK"; + when : "(B_BIST_WEN & B_BIST_MEN)" + sdf_cond : "B_BIST_RW_ACCESS" + + rise_constraint("SIG2SRAM_constraint_template") { + index_1("0.0056,0.0232,0.0400,0.0728,0.1280,0.2440,0.4760"); + index_2("0.0056,0.0232,0.0400,0.0728,0.1280,0.2440,0.4760"); + values ("-0.3235,-0.3079,-0.2952,-0.2620,-0.2132,-0.1145,0.0788",\ +"-0.3285,-0.3129,-0.3002,-0.2670,-0.2182,-0.1195,0.0738",\ +"-0.3330,-0.3174,-0.3047,-0.2715,-0.2226,-0.1240,0.0693",\ +"-0.3421,-0.3265,-0.3138,-0.2806,-0.2318,-0.1331,0.0602",\ +"-0.3493,-0.3337,-0.3210,-0.2878,-0.2390,-0.1403,0.0530",\ +"-0.3790,-0.3634,-0.3507,-0.3175,-0.2686,-0.1700,0.0234",\ +"-0.4370,-0.4214,-0.4087,-0.3755,-0.3267,-0.2281,-0.0347"); + } + + fall_constraint("SIG2SRAM_constraint_template") { + index_1("0.0056,0.0232,0.0400,0.0728,0.1280,0.2440,0.4760"); + index_2("0.0056,0.0232,0.0400,0.0728,0.1280,0.2440,0.4760"); + values ("-0.2893,-0.2747,-0.2610,-0.2327,-0.1829,-0.0843,0.0954",\ +"-0.2943,-0.2797,-0.2660,-0.2377,-0.1879,-0.0893,0.0904",\ +"-0.2988,-0.2842,-0.2705,-0.2422,-0.1924,-0.0937,0.0859",\ +"-0.3079,-0.2933,-0.2796,-0.2513,-0.2015,-0.1029,0.0768",\ +"-0.3151,-0.3005,-0.2868,-0.2585,-0.2087,-0.1101,0.0696",\ +"-0.3448,-0.3301,-0.3165,-0.2882,-0.2384,-0.1397,0.0400",\ +"-0.4029,-0.3882,-0.3745,-0.3462,-0.2964,-0.1978,-0.0181"); + } + } + + + timing() { + timing_type : hold_rising; + related_pin : "B_BIST_CLK"; + when : "(B_BIST_WEN & B_BIST_MEN)" + sdf_cond : "B_BIST_RW_ACCESS" + + rise_constraint("SIG2SRAM_constraint_template") { + index_1("0.0056,0.0232,0.0400,0.0728,0.1280,0.2440,0.4760"); + index_2("0.0056,0.0232,0.0400,0.0728,0.1280,0.2440,0.4760"); + values ("0.4331,0.4175,0.4048,0.3716,0.3237,0.2241,0.0298",\ +"0.4381,0.4225,0.4098,0.3766,0.3287,0.2291,0.0348",\ +"0.4426,0.4270,0.4143,0.3811,0.3332,0.2336,0.0393",\ +"0.4517,0.4361,0.4234,0.3902,0.3423,0.2427,0.0484",\ +"0.4589,0.4433,0.4306,0.3974,0.3495,0.2499,0.0556",\ +"0.4886,0.4729,0.4602,0.4270,0.3792,0.2796,0.0853",\ +"0.5466,0.5310,0.5183,0.4851,0.4373,0.3376,0.1433"); + } + + fall_constraint("SIG2SRAM_constraint_template") { + index_1("0.0056,0.0232,0.0400,0.0728,0.1280,0.2440,0.4760"); + index_2("0.0056,0.0232,0.0400,0.0728,0.1280,0.2440,0.4760"); + values ("0.3921,0.3774,0.3628,0.3345,0.2837,0.1919,0.0073",\ +"0.3971,0.3824,0.3678,0.3395,0.2887,0.1969,0.0123",\ +"0.4016,0.3869,0.3723,0.3440,0.2932,0.2014,0.0168",\ +"0.4107,0.3960,0.3814,0.3531,0.3023,0.2105,0.0259",\ +"0.4179,0.4032,0.3886,0.3603,0.3095,0.2177,0.0331",\ +"0.4476,0.4329,0.4183,0.3899,0.3392,0.2474,0.0628",\ +"0.5056,0.4910,0.4763,0.4480,0.3972,0.3054,0.1209"); + } + } +} + pin(B_BIST_CLK) { + direction : input; + capacitance : 0.00380014; + max_transition : "0.476"; + clock : "true" ; + pin_func_type : active_rising ; + + timing () { + timing_type : "min_pulse_width"; + related_pin : "B_BIST_CLK"; + rise_constraint("CLKTRAN_constraint_template") { + index_1("0.0056,0.476"); + values("0.21,0.21"); + } + } + + related_power_pin : VDD; + related_ground_pin : VSS; + + internal_power() { + when : "!B_BIST_MEN & !B_BIST_WEN & !B_BIST_REN"; + rise_power("scalar"){ + values (0); + } + fall_power("scalar"){ + values (0); + } + } + internal_power() { + when : "!B_BIST_MEN & B_BIST_WEN & !B_BIST_REN"; + rise_power("scalar"){ + values (0.4920); + } + fall_power("scalar"){ + values (0); + } + } + internal_power() { + when : "B_BIST_MEN & B_BIST_WEN & !B_BIST_REN"; + rise_power("scalar"){ + values (18.4562); + } + fall_power("scalar"){ + values (0); + } + } + internal_power() { + when : "B_BIST_MEN & B_BIST_WEN & B_BIST_REN"; + rise_power("scalar"){ + values (20.3138); + } + fall_power("scalar"){ + values (0); + } + } + internal_power() { + when : "B_BIST_MEN & !B_BIST_WEN & B_BIST_REN"; + rise_power("scalar"){ + values (14.1920); + } + fall_power("scalar"){ + values (0); + } + } + internal_power() { + when : "!B_BIST_MEN & !B_BIST_WEN & B_BIST_REN"; + rise_power("scalar"){ + values (0.2984); + } + fall_power("scalar"){ + values (0); + } + } + internal_power() { + when : "!B_BIST_MEN & B_BIST_WEN & B_BIST_REN"; + rise_power("scalar"){ + values (0.7334); + } + fall_power("scalar"){ + values (0); + } + } + internal_power() { + when : "B_BIST_MEN & !B_BIST_WEN & !B_BIST_REN"; + rise_power("scalar"){ + values (0); + } + fall_power("scalar"){ + values (0); + } + } + } + bus(B_BIST_DIN) { + bus_type : D_15_0; + direction : input ; + capacitance : 0.00414348 ; + memory_write() { + address : B_BIST_ADDR ; + clocked_on : B_BIST_CLK; + } + + max_transition : "0.476" ; + pin(B_BIST_DIN[15:0]) { + related_power_pin : VDD; + related_ground_pin : VSS; + internal_power() { + when : "B_BIST_MEN"; + rise_power("scalar"){ + values (0.0591); + } + fall_power("scalar"){ + values (0.0246); + } + } + internal_power() { + when : "!B_BIST_MEN"; + rise_power("scalar"){ + values (0.0602); + } + fall_power("scalar"){ + values (0.0244); + } + } + } + timing() { + timing_type : setup_rising; + related_pin : "B_BIST_CLK"; + when : "(B_BIST_WEN & B_BIST_MEN)"; + sdf_cond : "B_BIST_W_ACCESS"; + + rise_constraint("SIG2SRAM_constraint_template") { + index_1("0.0056,0.0232,0.0400,0.0728,0.1280,0.2440,0.4760"); + index_2("0.0056,0.0232,0.0400,0.0728,0.1280,0.2440,0.4760"); + values ("-0.3235,-0.3079,-0.2952,-0.2620,-0.2132,-0.1145,0.0788",\ +"-0.3285,-0.3129,-0.3002,-0.2670,-0.2182,-0.1195,0.0738",\ +"-0.3330,-0.3174,-0.3047,-0.2715,-0.2226,-0.1240,0.0693",\ +"-0.3421,-0.3265,-0.3138,-0.2806,-0.2318,-0.1331,0.0602",\ +"-0.3493,-0.3337,-0.3210,-0.2878,-0.2390,-0.1403,0.0530",\ +"-0.3790,-0.3634,-0.3507,-0.3175,-0.2686,-0.1700,0.0234",\ +"-0.4370,-0.4214,-0.4087,-0.3755,-0.3267,-0.2281,-0.0347"); + } + + fall_constraint("SIG2SRAM_constraint_template") { + index_1("0.0056,0.0232,0.0400,0.0728,0.1280,0.2440,0.4760"); + index_2("0.0056,0.0232,0.0400,0.0728,0.1280,0.2440,0.4760"); + values ("-0.2893,-0.2747,-0.2610,-0.2327,-0.1829,-0.0843,0.0954",\ +"-0.2943,-0.2797,-0.2660,-0.2377,-0.1879,-0.0893,0.0904",\ +"-0.2988,-0.2842,-0.2705,-0.2422,-0.1924,-0.0937,0.0859",\ +"-0.3079,-0.2933,-0.2796,-0.2513,-0.2015,-0.1029,0.0768",\ +"-0.3151,-0.3005,-0.2868,-0.2585,-0.2087,-0.1101,0.0696",\ +"-0.3448,-0.3301,-0.3165,-0.2882,-0.2384,-0.1397,0.0400",\ +"-0.4029,-0.3882,-0.3745,-0.3462,-0.2964,-0.1978,-0.0181"); + } + } + + timing() { + timing_type : hold_rising; + related_pin : "B_BIST_CLK"; + when : "(B_BIST_WEN & B_BIST_MEN)"; + sdf_cond : "B_BIST_W_ACCESS"; + + rise_constraint("SIG2SRAM_constraint_template") { + index_1("0.0056,0.0232,0.0400,0.0728,0.1280,0.2440,0.4760"); + index_2("0.0056,0.0232,0.0400,0.0728,0.1280,0.2440,0.4760"); + values ("0.4331,0.4175,0.4048,0.3716,0.3237,0.2241,0.0298",\ +"0.4381,0.4225,0.4098,0.3766,0.3287,0.2291,0.0348",\ +"0.4426,0.4270,0.4143,0.3811,0.3332,0.2336,0.0393",\ +"0.4517,0.4361,0.4234,0.3902,0.3423,0.2427,0.0484",\ +"0.4589,0.4433,0.4306,0.3974,0.3495,0.2499,0.0556",\ +"0.4886,0.4729,0.4602,0.4270,0.3792,0.2796,0.0853",\ +"0.5466,0.5310,0.5183,0.4851,0.4373,0.3376,0.1433"); + } + + fall_constraint("SIG2SRAM_constraint_template") { + index_1("0.0056,0.0232,0.0400,0.0728,0.1280,0.2440,0.4760"); + index_2("0.0056,0.0232,0.0400,0.0728,0.1280,0.2440,0.4760"); + values ("0.3921,0.3774,0.3628,0.3345,0.2837,0.1919,0.0073",\ +"0.3971,0.3824,0.3678,0.3395,0.2887,0.1969,0.0123",\ +"0.4016,0.3869,0.3723,0.3440,0.2932,0.2014,0.0168",\ +"0.4107,0.3960,0.3814,0.3531,0.3023,0.2105,0.0259",\ +"0.4179,0.4032,0.3886,0.3603,0.3095,0.2177,0.0331",\ +"0.4476,0.4329,0.4183,0.3899,0.3392,0.2474,0.0628",\ +"0.5056,0.4910,0.4763,0.4480,0.3972,0.3054,0.1209"); + } + } + } + +bus(B_DOUT) { + + bus_type : D_15_0; + direction : output ; + capacitance : 0 ; + max_capacitance : 0.064 ; + memory_read() { + address : B_ADDR ; + } + pin(B_DOUT[15:0]) { + related_power_pin : VDD; + related_ground_pin : VSS; + internal_power() { + rise_power("scalar") { + values (0); + } + fall_power("scalar") { + values (0); + } + } + } + timing() { + related_pin : "B_CLK"; + timing_type : rising_edge ; + timing_sense : non_unate ; + + cell_rise(SIG2SRAM_delay_template) { + index_1("0.0056,0.0232,0.0400,0.0728,0.1280,0.2440,0.4760"); + index_2("0.0008,0.0014,0.0051,0.0100,0.0339,0.0640"); + values ("2.9823,2.9839,2.9915,3.0002,3.0326,3.0688",\ +"2.9886,2.9902,2.9979,3.0066,3.0390,3.0751",\ +"2.9907,2.9923,3.0000,3.0087,3.0411,3.0772",\ +"3.0038,3.0054,3.0130,3.0217,3.0541,3.0903",\ +"3.0100,3.0116,3.0192,3.0279,3.0603,3.0965",\ +"3.0414,3.0431,3.0507,3.0594,3.0918,3.1279",\ +"3.0960,3.0976,3.1052,3.1139,3.1463,3.1824"); + } + cell_fall(SIG2SRAM_delay_template) { + index_1("0.0056,0.0232,0.0400,0.0728,0.1280,0.2440,0.4760"); + index_2("0.0008,0.0014,0.0051,0.0100,0.0339,0.0640"); + values ("2.9220,2.9233,2.9294,2.9365,2.9630,2.9893",\ +"2.9284,2.9297,2.9358,2.9429,2.9694,2.9956",\ +"2.9305,2.9318,2.9379,2.9450,2.9715,2.9977",\ +"2.9435,2.9448,2.9509,2.9580,2.9845,3.0108",\ +"2.9497,2.9510,2.9571,2.9642,2.9907,3.0170",\ +"2.9812,2.9825,2.9886,2.9957,3.0222,3.0484",\ +"3.0357,3.0370,3.0431,3.0502,3.0767,3.1029"); + } + + rise_transition(SRAM_load_template) { + index_1("0.0008,0.0014,0.0051,0.0100,0.0339,0.0640"); + values ("0.0326,0.0341,0.0428,0.0518,0.0923,0.1492"); + } + fall_transition(SRAM_load_template) { + index_1("0.0008,0.0014,0.0051,0.0100,0.0339,0.0640"); + values ("0.0254,0.0265,0.0335,0.0402,0.0707,0.1039"); + } + } +} +cell_leakage_power : 79.7252; +} +} diff --git a/flow/platforms/ihp-sg13g2/lib/RM_IHPSG13_2P_256x32_c2_bm_bist_fast_1p32V_m55C.lib b/flow/platforms/ihp-sg13g2/lib/RM_IHPSG13_2P_256x32_c2_bm_bist_fast_1p32V_m55C.lib new file mode 100644 index 0000000000..38cfe08fb0 --- /dev/null +++ b/flow/platforms/ihp-sg13g2/lib/RM_IHPSG13_2P_256x32_c2_bm_bist_fast_1p32V_m55C.lib @@ -0,0 +1,2874 @@ +/* ------------------------------------------------------*/ +/**/ +/* Copyright 2025 IHP PDK Authors*/ +/**/ +/* Licensed under the Apache License, Version 2.0 (the "License");*/ +/* you may not use this file except in compliance with the License.*/ +/* You may obtain a copy of the License at*/ +/* */ +/* https://www.apache.org/licenses/LICENSE-2.0*/ +/* */ +/* Unless required by applicable law or agreed to in writing, software*/ +/* distributed under the License is distributed on an "AS IS" BASIS,*/ +/* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.*/ +/* See the License for the specific language governing permissions and*/ +/* limitations under the License.*/ +/* */ +/* Generated on Wed Aug 27 13:14:36 2025 */ +/* */ +/* ------------------------------------------------------ */ +library(RM_IHPSG13_2P_256x32_c2_bm_bist_fast_1p32V_m55C) { + technology (cmos) ; + delay_model : table_lookup ; + define ("add_pg_pin_to_lib", "library", "boolean"); + add_pg_pin_to_lib : true; + voltage_map ( VDD, 1.32); + voltage_map ( VDDARRAY, 1.32); + voltage_map ( VSS, 0.000000 ); + + date : "Wed Aug 27 13:14:35 2025" ; + comment : "IHP Microelectronics GmbH, 2023" ; + revision : 1.0.0 ; + simulation : true ; + nom_process : 1 ; + nom_temperature : -55 ; + nom_voltage : 1.32 ; + + operating_conditions("fast_1p32V_m55C"){ + process : 1 ; + temperature : -55 ; + voltage : 1.32 ; + tree_type : "balanced_tree" ; + } + + default_operating_conditions : fast_1p32V_m55C ; + default_max_transition : 1.0 ; + default_fanout_load : 1.0 ; + default_inout_pin_cap : 0.0 ; + default_input_pin_cap : 0.0 ; + default_output_pin_cap : 0.0 ; + default_cell_leakage_power : 0.0 ; + default_leakage_power_density : 0.0 ; + + slew_lower_threshold_pct_rise : 30 ; + slew_upper_threshold_pct_rise : 70 ; + input_threshold_pct_fall : 50 ; + output_threshold_pct_fall : 50 ; + input_threshold_pct_rise : 50 ; + output_threshold_pct_rise : 50 ; + slew_lower_threshold_pct_fall : 30 ; + slew_upper_threshold_pct_fall : 70 ; + slew_derate_from_library : 0.5; + k_volt_cell_leakage_power : 0.0 ; + k_temp_cell_leakage_power : 0.0 ; + k_process_cell_leakage_power : 0.0 ; + k_volt_internal_power : 0.0 ; + k_temp_internal_power : 0.0 ; + k_process_internal_power : 0.0 ; + + capacitive_load_unit (1,pf) ; + voltage_unit : "1V" ; + current_unit : "1uA" ; + time_unit : "1ns" ; + leakage_power_unit : "1nW" ; + pulling_resistance_unit : "1kohm"; + /* + ------------------------------------------------------------------------------------------ + implicit units overview: + cell_area unit : "um" + internal_power unit : "1e-12 * J/toggle = 1 * uW/MHz" + (capacitive_load_unit * voltage_unit^2) per toggle event + ------------------------------------------------------------------------------------------ + */ + library_features(report_delay_calculation); + define_cell_area (pad_drivers,pad_driver_sites) ; + + lu_table_template(CLKTRAN_constraint_template) { + variable_1 : constrained_pin_transition; + index_1 ( "0.010, 0.050, 0.200, 0.400, 1.000" ); + } + lu_table_template(SRAM_load_template) { + variable_1 : total_output_net_capacitance; + index_1 ( "0.0008,0.0014,0.0051,0.0100,0.0339,0.0640" ); + } + lu_table_template(SIG2SRAM_constraint_template) { + variable_1 : related_pin_transition; + variable_2 : constrained_pin_transition; + index_1 ( "0.0040,0.0176,0.0344,0.0656,0.1120,0.2016,0.3800" ); + index_2 ( "0.0040,0.0176,0.0344,0.0656,0.1120,0.2016,0.3800" ); + } + + lu_table_template(SIG2SRAM_delay_template) { + variable_1 : input_net_transition; + variable_2 : total_output_net_capacitance; + index_1 ( "0.0040,0.0176,0.0344,0.0656,0.1120,0.2016,0.3800" ); + index_2 ( "0.0008,0.0014,0.0051,0.0100,0.0339,0.0640" ); + } + + type (D_31_0) { + base_type : array; + data_type : bit; + bit_width : 32; + bit_from : 31; + bit_to : 0; + downto : true; + } + + type (A_7_0) { + base_type : array; + data_type : bit; + bit_width : 8; + bit_from : 7; + bit_to : 0; + downto : true; + } + +cell(RM_IHPSG13_2P_256x32_c2_bm_bist) { +pg_pin (VDD) { + pg_type : primary_power; + voltage_name : VDD; +} +pg_pin (VDDARRAY) { + pg_type : primary_power; + voltage_name : VDDARRAY; +} +pg_pin (VSS) { + pg_type : primary_ground; + voltage_name : VSS; +} + +memory() { + type : ram; + address_width : 8; + word_width : 32; +} + +interface_timing : false; +bus_naming_style : "%s[%d]" ; +area : 96266.6251 ; + + pin(A_DLY) { + direction : input ; + capacitance : 0.00421562 ; + max_transition : "1" ; + related_power_pin : VDD; + related_ground_pin : VSS; + internal_power() { + rise_power("scalar") { + values (0); + } + fall_power("scalar") { + values (0); + } + } + } + +bus(A_ADDR) { + bus_type : A_7_0; + direction : input ; + capacitance : 0.0115194 ; + pin(A_ADDR[0]) { + capacitance : 0.00563454 ; + } + pin(A_ADDR[1]) { + capacitance : 0.00744185 ; + } + pin(A_ADDR[2]) { + capacitance : 0.0100611 ; + } + pin(A_ADDR[3]) { + capacitance : 0.00669965 ; + } + pin(A_ADDR[4]) { + capacitance : 0.00614331 ; + } + pin(A_ADDR[5]) { + capacitance : 0.0102172 ; + } + pin(A_ADDR[6]) { + capacitance : 0.0124225 ; + } + max_transition : "0.38" ; + pin(A_ADDR[7:0]) { + related_power_pin : VDD; + related_ground_pin : VSS; + internal_power() { + when : "A_MEN"; + rise_power("scalar"){ + values (0.0108); + } + fall_power("scalar"){ + values (0.0034); + } + } + internal_power() { + when : "!A_MEN"; + rise_power("scalar"){ + values (0.0264); + } + fall_power("scalar"){ + values (0.0033); + } + } + } + timing() { + timing_type : setup_rising; + related_pin : "A_CLK"; + when : "((A_WEN | A_REN)& A_MEN)" + sdf_cond : "A_RW_ACCESS" + + rise_constraint("SIG2SRAM_constraint_template") { + index_1("0.0040,0.0176,0.0344,0.0656,0.1120,0.2016,0.3800"); + index_2("0.0040,0.0176,0.0344,0.0656,0.1120,0.2016,0.3800"); + values ("-0.2371,-0.2215,-0.2098,-0.1824,-0.1434,-0.0691,0.0676",\ +"-0.2449,-0.2332,-0.2176,-0.1902,-0.1551,-0.0770,0.0559",\ +"-0.2605,-0.2488,-0.2332,-0.2059,-0.1707,-0.0965,0.0441",\ +"-0.2879,-0.2723,-0.2605,-0.2332,-0.1941,-0.1199,0.0168",\ +"-0.3230,-0.3113,-0.2996,-0.2723,-0.2332,-0.1590,-0.0184",\ +"-0.4012,-0.3895,-0.3738,-0.3465,-0.3074,-0.2332,-0.0965",\ +"-0.5379,-0.5262,-0.5105,-0.4832,-0.4480,-0.3699,-0.2332"); + } + + fall_constraint("SIG2SRAM_constraint_template") { + index_1("0.0040,0.0176,0.0344,0.0656,0.1120,0.2016,0.3800"); + index_2("0.0040,0.0176,0.0344,0.0656,0.1120,0.2016,0.3800"); + values ("-0.1785,-0.1707,-0.1551,-0.1277,-0.0887,-0.0184,0.1145",\ +"-0.1902,-0.1785,-0.1629,-0.1355,-0.1004,-0.0262,0.1027",\ +"-0.2059,-0.1941,-0.1785,-0.1512,-0.1160,-0.0418,0.0871",\ +"-0.2293,-0.2176,-0.2059,-0.1785,-0.1434,-0.0691,0.0598",\ +"-0.2684,-0.2566,-0.2449,-0.2176,-0.1824,-0.1082,0.0207",\ +"-0.3465,-0.3348,-0.3191,-0.2918,-0.2566,-0.1824,-0.0535",\ +"-0.4832,-0.4715,-0.4559,-0.4324,-0.3934,-0.3191,-0.1902"); + } + } + + + timing() { + timing_type : hold_rising; + related_pin : "A_CLK"; + when : "((A_WEN | A_REN)& A_MEN)" + sdf_cond : "A_RW_ACCESS" + + rise_constraint("SIG2SRAM_constraint_template") { + index_1("0.0040,0.0176,0.0344,0.0656,0.1120,0.2016,0.3800"); + index_2("0.0040,0.0176,0.0344,0.0656,0.1120,0.2016,0.3800"); + values ("0.3410,0.3293,0.3137,0.2863,0.2473,0.1730,0.0324",\ +"0.3488,0.3371,0.3215,0.2941,0.2590,0.1809,0.0480",\ +"0.3684,0.3527,0.3371,0.3098,0.2746,0.1965,0.0598",\ +"0.3918,0.3762,0.3645,0.3371,0.2980,0.2238,0.0871",\ +"0.4309,0.4152,0.4035,0.3762,0.3371,0.2629,0.1223",\ +"0.5051,0.4934,0.4777,0.4504,0.4113,0.3371,0.1965",\ +"0.6418,0.6262,0.6145,0.5871,0.5520,0.4738,0.3332"); + } + + fall_constraint("SIG2SRAM_constraint_template") { + index_1("0.0040,0.0176,0.0344,0.0656,0.1120,0.2016,0.3800"); + index_2("0.0040,0.0176,0.0344,0.0656,0.1120,0.2016,0.3800"); + values ("0.2824,0.2707,0.2551,0.2277,0.1926,0.1184,-0.0105",\ +"0.2902,0.2785,0.2668,0.2395,0.2043,0.1301,0.0012",\ +"0.3059,0.2941,0.2824,0.2551,0.2199,0.1457,0.0168",\ +"0.3332,0.3215,0.3059,0.2785,0.2434,0.1691,0.0402",\ +"0.3723,0.3605,0.3449,0.3176,0.2824,0.2121,0.0793",\ +"0.4465,0.4348,0.4230,0.3918,0.3566,0.2824,0.1535",\ +"0.5832,0.5715,0.5598,0.5324,0.4934,0.4191,0.2902"); + } + } +} +pin(A_WEN) { + direction : input ; + capacitance : 0.00341384 ; + max_transition : "0.38" ; + related_power_pin : VDD; + related_ground_pin : VSS; + internal_power() { + when : "A_MEN"; + rise_power("scalar"){ + values (0.0040); + } + fall_power("scalar"){ + values (0.0171); + } + } + internal_power() { + when : "!A_MEN"; + rise_power("scalar"){ + values (0.0050); + } + fall_power("scalar"){ + values (0.0218); + } + } + timing() { + timing_type : setup_rising; + related_pin : "A_CLK"; + when : "A_MEN" + sdf_cond : "A_MEN" + + rise_constraint("SIG2SRAM_constraint_template") { + index_1("0.0040,0.0176,0.0344,0.0656,0.1120,0.2016,0.3800"); + index_2("0.0040,0.0176,0.0344,0.0656,0.1120,0.2016,0.3800"); + values ("0.1418,0.1496,0.1652,0.1887,0.2316,0.3059,0.4465",\ +"0.1301,0.1379,0.1535,0.1809,0.2199,0.2941,0.4348",\ +"0.1145,0.1262,0.1379,0.1652,0.2043,0.2785,0.4191",\ +"0.0871,0.0949,0.1105,0.1379,0.1770,0.2512,0.3879",\ +"0.0480,0.0598,0.0754,0.0988,0.1379,0.2082,0.3527",\ +"-0.0262,-0.0145,0.0012,0.0246,0.0676,0.1379,0.2785",\ +"-0.1668,-0.1551,-0.1395,-0.1121,-0.0730,0.0012,0.1418"); + } + + fall_constraint("SIG2SRAM_constraint_template") { + index_1("0.0040,0.0176,0.0344,0.0656,0.1120,0.2016,0.3800"); + index_2("0.0040,0.0176,0.0344,0.0656,0.1120,0.2016,0.3800"); + values ("0.2082,0.2160,0.2316,0.2590,0.2941,0.3684,0.5012",\ +"0.1926,0.2043,0.2199,0.2473,0.2824,0.3566,0.4895",\ +"0.1770,0.1887,0.2043,0.2316,0.2668,0.3410,0.4777",\ +"0.1535,0.1652,0.1770,0.2043,0.2395,0.3137,0.4504",\ +"0.1145,0.1262,0.1379,0.1652,0.2043,0.2746,0.4113",\ +"0.0402,0.0520,0.0676,0.0910,0.1262,0.2004,0.3332",\ +"-0.0965,-0.0848,-0.0730,-0.0457,-0.0066,0.0637,0.2004"); + } + } + + + timing() { + timing_type : hold_rising; + related_pin : "A_CLK"; + when : "A_MEN" + sdf_cond : "A_MEN" + + rise_constraint("SIG2SRAM_constraint_template") { + index_1("0.0040,0.0176,0.0344,0.0656,0.1120,0.2016,0.3800"); + index_2("0.0040,0.0176,0.0344,0.0656,0.1120,0.2016,0.3800"); + values ("0.1770,0.1652,0.1496,0.1223,0.0793,0.0090,-0.1316",\ +"0.1848,0.1730,0.1574,0.1301,0.0910,0.0168,-0.1199",\ +"0.2004,0.1887,0.1770,0.1496,0.1066,0.0363,-0.1043",\ +"0.2277,0.2160,0.2004,0.1730,0.1340,0.0598,-0.0809",\ +"0.2668,0.2551,0.2395,0.2121,0.1730,0.0988,-0.0418",\ +"0.3410,0.3293,0.3137,0.2863,0.2434,0.1730,0.0324",\ +"0.4816,0.4699,0.4543,0.4230,0.3801,0.3098,0.1730"); + } + + fall_constraint("SIG2SRAM_constraint_template") { + index_1("0.0040,0.0176,0.0344,0.0656,0.1120,0.2016,0.3800"); + index_2("0.0040,0.0176,0.0344,0.0656,0.1120,0.2016,0.3800"); + values ("0.1613,0.1496,0.1379,0.1066,0.0715,0.0012,-0.1355",\ +"0.1730,0.1613,0.1457,0.1184,0.0832,0.0129,-0.1238",\ +"0.1887,0.1770,0.1613,0.1340,0.0988,0.0246,-0.1121",\ +"0.2121,0.2043,0.1887,0.1613,0.1223,0.0520,-0.0848",\ +"0.2512,0.2434,0.2277,0.2004,0.1613,0.0910,-0.0457",\ +"0.3254,0.3176,0.3020,0.2746,0.2355,0.1652,0.0324",\ +"0.4660,0.4543,0.4387,0.4113,0.3723,0.3020,0.1691"); + } + } + } +pin(A_REN) { + direction : input ; + capacitance : 0.00390661 ; + max_transition : "0.38" ; + related_power_pin : VDD; + related_ground_pin : VSS; + internal_power() { + when : "A_MEN"; + rise_power("scalar"){ + values (0.0122); + } + fall_power("scalar"){ + values (0.0105); + } + } + internal_power() { + when : "!A_MEN"; + rise_power("scalar"){ + values (0.0181); + } + fall_power("scalar"){ + values (0.0202); + } + } + timing() { + timing_type : setup_rising; + related_pin : "A_CLK"; + when : "A_MEN" + sdf_cond : "A_MEN" + + rise_constraint("SIG2SRAM_constraint_template") { + index_1("0.0040,0.0176,0.0344,0.0656,0.1120,0.2016,0.3800"); + index_2("0.0040,0.0176,0.0344,0.0656,0.1120,0.2016,0.3800"); + values ("-0.0027,0.0090,0.0246,0.0520,0.0910,0.1613,0.3020",\ +"-0.0105,0.0012,0.0129,0.0363,0.0793,0.1535,0.2902",\ +"-0.0262,-0.0145,-0.0027,0.0246,0.0637,0.1379,0.2785",\ +"-0.0535,-0.0418,-0.0262,0.0012,0.0363,0.1105,0.2512",\ +"-0.0926,-0.0809,-0.0652,-0.0418,-0.0027,0.0715,0.2121",\ +"-0.1668,-0.1551,-0.1395,-0.1082,-0.0770,-0.0027,0.1379",\ +"-0.3035,-0.2918,-0.2762,-0.2488,-0.2137,-0.1434,-0.0027"); + } + + fall_constraint("SIG2SRAM_constraint_template") { + index_1("0.0040,0.0176,0.0344,0.0656,0.1120,0.2016,0.3800"); + index_2("0.0040,0.0176,0.0344,0.0656,0.1120,0.2016,0.3800"); + values ("0.0832,0.0949,0.1105,0.1379,0.1730,0.2473,0.3801",\ +"0.0754,0.0832,0.0988,0.1223,0.1613,0.2355,0.3684",\ +"0.0598,0.0676,0.0832,0.1066,0.1457,0.2121,0.3527",\ +"0.0324,0.0441,0.0598,0.0871,0.1223,0.1926,0.3293",\ +"-0.0066,0.0051,0.0168,0.0480,0.0832,0.1535,0.2902",\ +"-0.0809,-0.0691,-0.0574,-0.0301,0.0090,0.0832,0.2121",\ +"-0.2176,-0.2059,-0.1941,-0.1668,-0.1277,-0.0574,0.0793"); + } + } + + + timing() { + timing_type : hold_rising; + related_pin : "A_CLK"; + when : "A_MEN" + sdf_cond : "A_MEN" + + rise_constraint("SIG2SRAM_constraint_template") { + index_1("0.0040,0.0176,0.0344,0.0656,0.1120,0.2016,0.3800"); + index_2("0.0040,0.0176,0.0344,0.0656,0.1120,0.2016,0.3800"); + values ("0.1887,0.1770,0.1613,0.1340,0.0949,0.0207,-0.1160",\ +"0.1965,0.1848,0.1730,0.1457,0.1027,0.0324,-0.1082",\ +"0.2160,0.2004,0.1887,0.1613,0.1184,0.0480,-0.0926",\ +"0.2395,0.2277,0.2121,0.1848,0.1457,0.0715,-0.0652",\ +"0.2785,0.2668,0.2512,0.2238,0.1848,0.1105,-0.0262",\ +"0.3527,0.3410,0.3254,0.2980,0.2551,0.1848,0.0480",\ +"0.4934,0.4816,0.4660,0.4387,0.3957,0.3254,0.1887"); + } + + fall_constraint("SIG2SRAM_constraint_template") { + index_1("0.0040,0.0176,0.0344,0.0656,0.1120,0.2016,0.3800"); + index_2("0.0040,0.0176,0.0344,0.0656,0.1120,0.2016,0.3800"); + values ("0.1730,0.1613,0.1496,0.1184,0.0793,0.0129,-0.1238",\ +"0.1848,0.1730,0.1574,0.1301,0.0910,0.0207,-0.1121",\ +"0.2004,0.1887,0.1730,0.1457,0.1066,0.0363,-0.1004",\ +"0.2238,0.2121,0.2004,0.1691,0.1340,0.0598,-0.0730",\ +"0.2629,0.2512,0.2395,0.2121,0.1691,0.0988,-0.0340",\ +"0.3371,0.3254,0.3137,0.2863,0.2434,0.1730,0.0402",\ +"0.4777,0.4660,0.4504,0.4230,0.3840,0.3137,0.1809"); + } + } + } +pin(A_MEN) { + direction : input ; + capacitance : 0.00326046 ; + max_transition : "0.38" ; + related_power_pin : VDD; + related_ground_pin : VSS; + internal_power() { + rise_power("scalar"){ + values (0.2714); + } + fall_power("scalar"){ + values (0.0108); + } + } + timing() { + timing_type : setup_rising; + related_pin : "A_CLK"; + + rise_constraint("SIG2SRAM_constraint_template") { + index_1("0.0040,0.0176,0.0344,0.0656,0.1120,0.2016,0.3800"); + index_2("0.0040,0.0176,0.0344,0.0656,0.1120,0.2016,0.3800"); + values ("0.1418,0.1496,0.1652,0.1926,0.2316,0.3059,0.4465",\ +"0.1301,0.1379,0.1535,0.1809,0.2199,0.2941,0.4348",\ +"0.1145,0.1262,0.1418,0.1652,0.2043,0.2785,0.4191",\ +"0.0871,0.0949,0.1105,0.1379,0.1770,0.2512,0.3879",\ +"0.0480,0.0598,0.0754,0.0988,0.1379,0.2082,0.3488",\ +"-0.0262,-0.0145,0.0012,0.0285,0.0676,0.1379,0.2785",\ +"-0.1668,-0.1551,-0.1395,-0.1121,-0.0730,0.0012,0.1379"); + } + + fall_constraint("SIG2SRAM_constraint_template") { + index_1("0.0040,0.0176,0.0344,0.0656,0.1120,0.2016,0.3800"); + index_2("0.0040,0.0176,0.0344,0.0656,0.1120,0.2016,0.3800"); + values ("0.2082,0.2199,0.2316,0.2590,0.2980,0.3723,0.5051",\ +"0.1965,0.2082,0.2199,0.2473,0.2863,0.3605,0.4934",\ +"0.1809,0.1926,0.2043,0.2316,0.2707,0.3449,0.4777",\ +"0.1574,0.1691,0.1809,0.2082,0.2434,0.3176,0.4543",\ +"0.1145,0.1262,0.1418,0.1691,0.2043,0.2785,0.4113",\ +"0.0441,0.0559,0.0676,0.0949,0.1301,0.2004,0.3332",\ +"-0.0965,-0.0848,-0.0691,-0.0418,-0.0066,0.0676,0.2004"); + } + } + + + timing() { + timing_type : hold_rising; + related_pin : "A_CLK"; + + rise_constraint("SIG2SRAM_constraint_template") { + index_1("0.0040,0.0176,0.0344,0.0656,0.1120,0.2016,0.3800"); + index_2("0.0040,0.0176,0.0344,0.0656,0.1120,0.2016,0.3800"); + values ("0.1770,0.1652,0.1535,0.1262,0.0832,0.0129,-0.1277",\ +"0.1887,0.1770,0.1613,0.1340,0.0949,0.0207,-0.1199",\ +"0.2043,0.1926,0.1770,0.1496,0.1105,0.0363,-0.1043",\ +"0.2277,0.2160,0.2043,0.1770,0.1379,0.0598,-0.0770",\ +"0.2668,0.2551,0.2434,0.2160,0.1730,0.0988,-0.0379",\ +"0.3449,0.3332,0.3176,0.2902,0.2473,0.1730,0.0363",\ +"0.4816,0.4699,0.4543,0.4270,0.3840,0.3098,0.1770"); + } + + fall_constraint("SIG2SRAM_constraint_template") { + index_1("0.0040,0.0176,0.0344,0.0656,0.1120,0.2016,0.3800"); + index_2("0.0040,0.0176,0.0344,0.0656,0.1120,0.2016,0.3800"); + values ("0.1613,0.1496,0.1379,0.1105,0.0715,0.0012,-0.1355",\ +"0.1730,0.1613,0.1496,0.1184,0.0832,0.0129,-0.1238",\ +"0.1887,0.1770,0.1652,0.1340,0.0988,0.0285,-0.1121",\ +"0.2121,0.2043,0.1887,0.1613,0.1223,0.0520,-0.0848",\ +"0.2551,0.2434,0.2277,0.2004,0.1613,0.0910,-0.0418",\ +"0.3293,0.3176,0.3020,0.2746,0.2395,0.1652,0.0324",\ +"0.4660,0.4543,0.4426,0.4113,0.3762,0.3020,0.1691"); + } + } + } +bus(A_BM) { + bus_type : D_31_0; + direction : input ; + capacitance : 0.00388883 ; + max_transition : "0.38" ; + pin(A_BM[31:0]) { + related_power_pin : VDD; + related_ground_pin : VSS; + internal_power() { + when : "A_MEN"; + rise_power("scalar"){ + values (0.1809); + } + fall_power("scalar"){ + values (0.1563); + } + } + internal_power() { + when : "!A_MEN"; + rise_power("scalar"){ + values (0.1509); + } + fall_power("scalar"){ + values (0.1509); + } + } + } + timing() { + timing_type : setup_rising; + related_pin : "A_CLK"; + when : "(A_WEN & A_MEN)" + sdf_cond : "A_RW_ACCESS" + + rise_constraint("SIG2SRAM_constraint_template") { + index_1("0.0040,0.0176,0.0344,0.0656,0.1120,0.2016,0.3800"); + index_2("0.0040,0.0176,0.0344,0.0656,0.1120,0.2016,0.3800"); + values ("-0.2898,-0.2791,-0.2634,-0.2380,-0.1970,-0.1238,0.0110",\ +"-0.2937,-0.2829,-0.2673,-0.2419,-0.2009,-0.1277,0.0071",\ +"-0.2974,-0.2866,-0.2710,-0.2456,-0.2046,-0.1313,0.0034",\ +"-0.3006,-0.2898,-0.2742,-0.2488,-0.2078,-0.1346,0.0002",\ +"-0.3132,-0.3024,-0.2868,-0.2614,-0.2204,-0.1472,-0.0124",\ +"-0.3308,-0.3200,-0.3044,-0.2790,-0.2380,-0.1648,-0.0300",\ +"-0.3583,-0.3475,-0.3319,-0.3065,-0.2655,-0.1923,-0.0575"); + } + + fall_constraint("SIG2SRAM_constraint_template") { + index_1("0.0040,0.0176,0.0344,0.0656,0.1120,0.2016,0.3800"); + index_2("0.0040,0.0176,0.0344,0.0656,0.1120,0.2016,0.3800"); + values ("-0.2664,-0.2546,-0.2419,-0.2146,-0.1775,-0.1042,0.0237",\ +"-0.2702,-0.2585,-0.2458,-0.2185,-0.1814,-0.1081,0.0198",\ +"-0.2739,-0.2622,-0.2495,-0.2222,-0.1851,-0.1118,0.0161",\ +"-0.2771,-0.2654,-0.2527,-0.2254,-0.1883,-0.1150,0.0129",\ +"-0.2897,-0.2780,-0.2653,-0.2380,-0.2009,-0.1276,0.0003",\ +"-0.3073,-0.2956,-0.2829,-0.2556,-0.2185,-0.1452,-0.0173",\ +"-0.3349,-0.3231,-0.3104,-0.2831,-0.2460,-0.1727,-0.0448"); + } + } + + + timing() { + timing_type : hold_rising; + related_pin : "A_CLK"; + when : "(A_WEN & A_MEN)" + sdf_cond : "A_RW_ACCESS" + + rise_constraint("SIG2SRAM_constraint_template") { + index_1("0.0040,0.0176,0.0344,0.0656,0.1120,0.2016,0.3800"); + index_2("0.0040,0.0176,0.0344,0.0656,0.1120,0.2016,0.3800"); + values ("0.3958,0.3860,0.3704,0.3440,0.3069,0.2327,0.0979",\ +"0.3997,0.3899,0.3743,0.3479,0.3108,0.2366,0.1018",\ +"0.4033,0.3936,0.3780,0.3516,0.3145,0.2403,0.1055",\ +"0.4065,0.3968,0.3811,0.3548,0.3177,0.2435,0.1087",\ +"0.4192,0.4094,0.3938,0.3674,0.3303,0.2561,0.1213",\ +"0.4368,0.4270,0.4114,0.3850,0.3479,0.2737,0.1389",\ +"0.4643,0.4545,0.4389,0.4125,0.3754,0.3012,0.1664"); + } + + fall_constraint("SIG2SRAM_constraint_template") { + index_1("0.0040,0.0176,0.0344,0.0656,0.1120,0.2016,0.3800"); + index_2("0.0040,0.0176,0.0344,0.0656,0.1120,0.2016,0.3800"); + values ("0.3675,0.3567,0.3430,0.3157,0.2796,0.2073,0.0774",\ +"0.3713,0.3606,0.3469,0.3196,0.2834,0.2112,0.0813",\ +"0.3750,0.3643,0.3506,0.3233,0.2871,0.2149,0.0850",\ +"0.3782,0.3675,0.3538,0.3265,0.2903,0.2181,0.0882",\ +"0.3908,0.3801,0.3664,0.3391,0.3029,0.2307,0.1008",\ +"0.4084,0.3977,0.3840,0.3567,0.3206,0.2483,0.1184",\ +"0.4360,0.4252,0.4115,0.3842,0.3481,0.2758,0.1459"); + } + } +} + pin(A_CLK) { + direction : input; + capacitance : 0.00389386; + max_transition : "0.38"; + clock : "true" ; + pin_func_type : active_rising ; + + timing () { + timing_type : "min_pulse_width"; + related_pin : "A_CLK"; + rise_constraint("CLKTRAN_constraint_template") { + index_1("0.004,0.38"); + values("0.12,0.12"); + } + } + + related_power_pin : VDD; + related_ground_pin : VSS; + + internal_power() { + when : "!A_MEN & !A_WEN & !A_REN"; + rise_power("scalar"){ + values (0); + } + fall_power("scalar"){ + values (0); + } + } + internal_power() { + when : "!A_MEN & A_WEN & !A_REN"; + rise_power("scalar"){ + values (0.6783); + } + fall_power("scalar"){ + values (0); + } + } + internal_power() { + when : "A_MEN & A_WEN & !A_REN"; + rise_power("scalar"){ + values (41.2558); + } + fall_power("scalar"){ + values (0); + } + } + internal_power() { + when : "A_MEN & A_WEN & A_REN"; + rise_power("scalar"){ + values (46.5325); + } + fall_power("scalar"){ + values (0); + } + } + internal_power() { + when : "A_MEN & !A_WEN & A_REN"; + rise_power("scalar"){ + values (34.0312); + } + fall_power("scalar"){ + values (0); + } + } + internal_power() { + when : "!A_MEN & !A_WEN & A_REN"; + rise_power("scalar"){ + values (0.4087); + } + fall_power("scalar"){ + values (0); + } + } + internal_power() { + when : "!A_MEN & A_WEN & A_REN"; + rise_power("scalar"){ + values (1.3353); + } + fall_power("scalar"){ + values (0); + } + } + internal_power() { + when : "A_MEN & !A_WEN & !A_REN"; + rise_power("scalar"){ + values (0); + } + fall_power("scalar"){ + values (0); + } + } + } + bus(A_DIN) { + bus_type : D_31_0; + direction : input ; + capacitance : 0.00505326 ; + memory_write() { + address : A_ADDR ; + clocked_on : A_CLK; + } + + max_transition : "0.38" ; + pin(A_DIN[31:0]) { + related_power_pin : VDD; + related_ground_pin : VSS; + internal_power() { + when : "A_MEN"; + rise_power("scalar"){ + values (0.1809); + } + fall_power("scalar"){ + values (0.1563); + } + } + internal_power() { + when : "!A_MEN"; + rise_power("scalar"){ + values (0.1509); + } + fall_power("scalar"){ + values (0.1509); + } + } + } + timing() { + timing_type : setup_rising; + related_pin : "A_CLK"; + when : "(A_WEN & A_MEN)"; + sdf_cond : "A_W_ACCESS"; + + rise_constraint("SIG2SRAM_constraint_template") { + index_1("0.0040,0.0176,0.0344,0.0656,0.1120,0.2016,0.3800"); + index_2("0.0040,0.0176,0.0344,0.0656,0.1120,0.2016,0.3800"); + values ("-0.2898,-0.2791,-0.2634,-0.2380,-0.1970,-0.1238,0.0110",\ +"-0.2937,-0.2829,-0.2673,-0.2419,-0.2009,-0.1277,0.0071",\ +"-0.2974,-0.2866,-0.2710,-0.2456,-0.2046,-0.1313,0.0034",\ +"-0.3006,-0.2898,-0.2742,-0.2488,-0.2078,-0.1346,0.0002",\ +"-0.3132,-0.3024,-0.2868,-0.2614,-0.2204,-0.1472,-0.0124",\ +"-0.3308,-0.3200,-0.3044,-0.2790,-0.2380,-0.1648,-0.0300",\ +"-0.3583,-0.3475,-0.3319,-0.3065,-0.2655,-0.1923,-0.0575"); + } + + fall_constraint("SIG2SRAM_constraint_template") { + index_1("0.0040,0.0176,0.0344,0.0656,0.1120,0.2016,0.3800"); + index_2("0.0040,0.0176,0.0344,0.0656,0.1120,0.2016,0.3800"); + values ("-0.2664,-0.2546,-0.2419,-0.2146,-0.1775,-0.1042,0.0237",\ +"-0.2702,-0.2585,-0.2458,-0.2185,-0.1814,-0.1081,0.0198",\ +"-0.2739,-0.2622,-0.2495,-0.2222,-0.1851,-0.1118,0.0161",\ +"-0.2771,-0.2654,-0.2527,-0.2254,-0.1883,-0.1150,0.0129",\ +"-0.2897,-0.2780,-0.2653,-0.2380,-0.2009,-0.1276,0.0003",\ +"-0.3073,-0.2956,-0.2829,-0.2556,-0.2185,-0.1452,-0.0173",\ +"-0.3349,-0.3231,-0.3104,-0.2831,-0.2460,-0.1727,-0.0448"); + } + } + + timing() { + timing_type : hold_rising; + related_pin : "A_CLK"; + when : "(A_WEN & A_MEN)"; + sdf_cond : "A_W_ACCESS"; + + rise_constraint("SIG2SRAM_constraint_template") { + index_1("0.0040,0.0176,0.0344,0.0656,0.1120,0.2016,0.3800"); + index_2("0.0040,0.0176,0.0344,0.0656,0.1120,0.2016,0.3800"); + values ("0.3958,0.3860,0.3704,0.3440,0.3069,0.2327,0.0979",\ +"0.3997,0.3899,0.3743,0.3479,0.3108,0.2366,0.1018",\ +"0.4033,0.3936,0.3780,0.3516,0.3145,0.2403,0.1055",\ +"0.4065,0.3968,0.3811,0.3548,0.3177,0.2435,0.1087",\ +"0.4192,0.4094,0.3938,0.3674,0.3303,0.2561,0.1213",\ +"0.4368,0.4270,0.4114,0.3850,0.3479,0.2737,0.1389",\ +"0.4643,0.4545,0.4389,0.4125,0.3754,0.3012,0.1664"); + } + + fall_constraint("SIG2SRAM_constraint_template") { + index_1("0.0040,0.0176,0.0344,0.0656,0.1120,0.2016,0.3800"); + index_2("0.0040,0.0176,0.0344,0.0656,0.1120,0.2016,0.3800"); + values ("0.3675,0.3567,0.3430,0.3157,0.2796,0.2073,0.0774",\ +"0.3713,0.3606,0.3469,0.3196,0.2834,0.2112,0.0813",\ +"0.3750,0.3643,0.3506,0.3233,0.2871,0.2149,0.0850",\ +"0.3782,0.3675,0.3538,0.3265,0.2903,0.2181,0.0882",\ +"0.3908,0.3801,0.3664,0.3391,0.3029,0.2307,0.1008",\ +"0.4084,0.3977,0.3840,0.3567,0.3206,0.2483,0.1184",\ +"0.4360,0.4252,0.4115,0.3842,0.3481,0.2758,0.1459"); + } + } + } + + pin(A_BIST_EN) { + direction : input ; + capacitance : 0.00421562 ; + max_transition : "1" ; + related_power_pin : VDD; + related_ground_pin : VSS; + internal_power() { + rise_power("scalar") { + values (0); + } + fall_power("scalar") { + values (0); + } + } + } + +bus(A_BIST_ADDR) { + bus_type : A_7_0; + direction : input ; + capacitance : 0.0115194 ; + pin(A_BIST_ADDR[0]) { + capacitance : 0.00563454 ; + } + pin(A_BIST_ADDR[1]) { + capacitance : 0.00744185 ; + } + pin(A_BIST_ADDR[2]) { + capacitance : 0.0100611 ; + } + pin(A_BIST_ADDR[3]) { + capacitance : 0.00669965 ; + } + pin(A_BIST_ADDR[4]) { + capacitance : 0.00614331 ; + } + pin(A_BIST_ADDR[5]) { + capacitance : 0.0102172 ; + } + pin(A_BIST_ADDR[6]) { + capacitance : 0.0124225 ; + } + max_transition : "0.38" ; + pin(A_BIST_ADDR[7:0]) { + related_power_pin : VDD; + related_ground_pin : VSS; + internal_power() { + when : "A_BIST_MEN"; + rise_power("scalar"){ + values (0.0108); + } + fall_power("scalar"){ + values (0.0034); + } + } + internal_power() { + when : "!A_BIST_MEN"; + rise_power("scalar"){ + values (0.0264); + } + fall_power("scalar"){ + values (0.0033); + } + } + } + timing() { + timing_type : setup_rising; + related_pin : "A_BIST_CLK"; + when : "((A_BIST_WEN | A_BIST_REN)& A_BIST_MEN)" + sdf_cond : "A_BIST_RW_ACCESS" + + rise_constraint("SIG2SRAM_constraint_template") { + index_1("0.0040,0.0176,0.0344,0.0656,0.1120,0.2016,0.3800"); + index_2("0.0040,0.0176,0.0344,0.0656,0.1120,0.2016,0.3800"); + values ("-0.2371,-0.2215,-0.2098,-0.1824,-0.1434,-0.0691,0.0676",\ +"-0.2449,-0.2332,-0.2176,-0.1902,-0.1551,-0.0770,0.0559",\ +"-0.2605,-0.2488,-0.2332,-0.2059,-0.1707,-0.0965,0.0441",\ +"-0.2879,-0.2723,-0.2605,-0.2332,-0.1941,-0.1199,0.0168",\ +"-0.3230,-0.3113,-0.2996,-0.2723,-0.2332,-0.1590,-0.0184",\ +"-0.4012,-0.3895,-0.3738,-0.3465,-0.3074,-0.2332,-0.0965",\ +"-0.5379,-0.5262,-0.5105,-0.4832,-0.4480,-0.3699,-0.2332"); + } + + fall_constraint("SIG2SRAM_constraint_template") { + index_1("0.0040,0.0176,0.0344,0.0656,0.1120,0.2016,0.3800"); + index_2("0.0040,0.0176,0.0344,0.0656,0.1120,0.2016,0.3800"); + values ("-0.1785,-0.1707,-0.1551,-0.1277,-0.0887,-0.0184,0.1145",\ +"-0.1902,-0.1785,-0.1629,-0.1355,-0.1004,-0.0262,0.1027",\ +"-0.2059,-0.1941,-0.1785,-0.1512,-0.1160,-0.0418,0.0871",\ +"-0.2293,-0.2176,-0.2059,-0.1785,-0.1434,-0.0691,0.0598",\ +"-0.2684,-0.2566,-0.2449,-0.2176,-0.1824,-0.1082,0.0207",\ +"-0.3465,-0.3348,-0.3191,-0.2918,-0.2566,-0.1824,-0.0535",\ +"-0.4832,-0.4715,-0.4559,-0.4324,-0.3934,-0.3191,-0.1902"); + } + } + + + timing() { + timing_type : hold_rising; + related_pin : "A_BIST_CLK"; + when : "((A_BIST_WEN | A_BIST_REN)& A_BIST_MEN)" + sdf_cond : "A_BIST_RW_ACCESS" + + rise_constraint("SIG2SRAM_constraint_template") { + index_1("0.0040,0.0176,0.0344,0.0656,0.1120,0.2016,0.3800"); + index_2("0.0040,0.0176,0.0344,0.0656,0.1120,0.2016,0.3800"); + values ("0.3410,0.3293,0.3137,0.2863,0.2473,0.1730,0.0324",\ +"0.3488,0.3371,0.3215,0.2941,0.2590,0.1809,0.0480",\ +"0.3684,0.3527,0.3371,0.3098,0.2746,0.1965,0.0598",\ +"0.3918,0.3762,0.3645,0.3371,0.2980,0.2238,0.0871",\ +"0.4309,0.4152,0.4035,0.3762,0.3371,0.2629,0.1223",\ +"0.5051,0.4934,0.4777,0.4504,0.4113,0.3371,0.1965",\ +"0.6418,0.6262,0.6145,0.5871,0.5520,0.4738,0.3332"); + } + + fall_constraint("SIG2SRAM_constraint_template") { + index_1("0.0040,0.0176,0.0344,0.0656,0.1120,0.2016,0.3800"); + index_2("0.0040,0.0176,0.0344,0.0656,0.1120,0.2016,0.3800"); + values ("0.2824,0.2707,0.2551,0.2277,0.1926,0.1184,-0.0105",\ +"0.2902,0.2785,0.2668,0.2395,0.2043,0.1301,0.0012",\ +"0.3059,0.2941,0.2824,0.2551,0.2199,0.1457,0.0168",\ +"0.3332,0.3215,0.3059,0.2785,0.2434,0.1691,0.0402",\ +"0.3723,0.3605,0.3449,0.3176,0.2824,0.2121,0.0793",\ +"0.4465,0.4348,0.4230,0.3918,0.3566,0.2824,0.1535",\ +"0.5832,0.5715,0.5598,0.5324,0.4934,0.4191,0.2902"); + } + } +} +pin(A_BIST_WEN) { + direction : input ; + capacitance : 0.00341384 ; + max_transition : "0.38" ; + related_power_pin : VDD; + related_ground_pin : VSS; + internal_power() { + when : "A_BIST_MEN"; + rise_power("scalar"){ + values (0.0040); + } + fall_power("scalar"){ + values (0.0171); + } + } + internal_power() { + when : "!A_BIST_MEN"; + rise_power("scalar"){ + values (0.0050); + } + fall_power("scalar"){ + values (0.0218); + } + } + timing() { + timing_type : setup_rising; + related_pin : "A_BIST_CLK"; + when : "A_BIST_MEN" + sdf_cond : "A_BIST_MEN" + + rise_constraint("SIG2SRAM_constraint_template") { + index_1("0.0040,0.0176,0.0344,0.0656,0.1120,0.2016,0.3800"); + index_2("0.0040,0.0176,0.0344,0.0656,0.1120,0.2016,0.3800"); + values ("0.1418,0.1496,0.1652,0.1887,0.2316,0.3059,0.4465",\ +"0.1301,0.1379,0.1535,0.1809,0.2199,0.2941,0.4348",\ +"0.1145,0.1262,0.1379,0.1652,0.2043,0.2785,0.4191",\ +"0.0871,0.0949,0.1105,0.1379,0.1770,0.2512,0.3879",\ +"0.0480,0.0598,0.0754,0.0988,0.1379,0.2082,0.3527",\ +"-0.0262,-0.0145,0.0012,0.0246,0.0676,0.1379,0.2785",\ +"-0.1668,-0.1551,-0.1395,-0.1121,-0.0730,0.0012,0.1418"); + } + + fall_constraint("SIG2SRAM_constraint_template") { + index_1("0.0040,0.0176,0.0344,0.0656,0.1120,0.2016,0.3800"); + index_2("0.0040,0.0176,0.0344,0.0656,0.1120,0.2016,0.3800"); + values ("0.2082,0.2160,0.2316,0.2590,0.2941,0.3684,0.5012",\ +"0.1926,0.2043,0.2199,0.2473,0.2824,0.3566,0.4895",\ +"0.1770,0.1887,0.2043,0.2316,0.2668,0.3410,0.4777",\ +"0.1535,0.1652,0.1770,0.2043,0.2395,0.3137,0.4504",\ +"0.1145,0.1262,0.1379,0.1652,0.2043,0.2746,0.4113",\ +"0.0402,0.0520,0.0676,0.0910,0.1262,0.2004,0.3332",\ +"-0.0965,-0.0848,-0.0730,-0.0457,-0.0066,0.0637,0.2004"); + } + } + + + timing() { + timing_type : hold_rising; + related_pin : "A_BIST_CLK"; + when : "A_BIST_MEN" + sdf_cond : "A_BIST_MEN" + + rise_constraint("SIG2SRAM_constraint_template") { + index_1("0.0040,0.0176,0.0344,0.0656,0.1120,0.2016,0.3800"); + index_2("0.0040,0.0176,0.0344,0.0656,0.1120,0.2016,0.3800"); + values ("0.1770,0.1652,0.1496,0.1223,0.0793,0.0090,-0.1316",\ +"0.1848,0.1730,0.1574,0.1301,0.0910,0.0168,-0.1199",\ +"0.2004,0.1887,0.1770,0.1496,0.1066,0.0363,-0.1043",\ +"0.2277,0.2160,0.2004,0.1730,0.1340,0.0598,-0.0809",\ +"0.2668,0.2551,0.2395,0.2121,0.1730,0.0988,-0.0418",\ +"0.3410,0.3293,0.3137,0.2863,0.2434,0.1730,0.0324",\ +"0.4816,0.4699,0.4543,0.4230,0.3801,0.3098,0.1730"); + } + + fall_constraint("SIG2SRAM_constraint_template") { + index_1("0.0040,0.0176,0.0344,0.0656,0.1120,0.2016,0.3800"); + index_2("0.0040,0.0176,0.0344,0.0656,0.1120,0.2016,0.3800"); + values ("0.1613,0.1496,0.1379,0.1066,0.0715,0.0012,-0.1355",\ +"0.1730,0.1613,0.1457,0.1184,0.0832,0.0129,-0.1238",\ +"0.1887,0.1770,0.1613,0.1340,0.0988,0.0246,-0.1121",\ +"0.2121,0.2043,0.1887,0.1613,0.1223,0.0520,-0.0848",\ +"0.2512,0.2434,0.2277,0.2004,0.1613,0.0910,-0.0457",\ +"0.3254,0.3176,0.3020,0.2746,0.2355,0.1652,0.0324",\ +"0.4660,0.4543,0.4387,0.4113,0.3723,0.3020,0.1691"); + } + } + } +pin(A_BIST_REN) { + direction : input ; + capacitance : 0.00390661 ; + max_transition : "0.38" ; + related_power_pin : VDD; + related_ground_pin : VSS; + internal_power() { + when : "A_BIST_MEN"; + rise_power("scalar"){ + values (0.0122); + } + fall_power("scalar"){ + values (0.0105); + } + } + internal_power() { + when : "!A_BIST_MEN"; + rise_power("scalar"){ + values (0.0181); + } + fall_power("scalar"){ + values (0.0202); + } + } + timing() { + timing_type : setup_rising; + related_pin : "A_BIST_CLK"; + when : "A_BIST_MEN" + sdf_cond : "A_BIST_MEN" + + rise_constraint("SIG2SRAM_constraint_template") { + index_1("0.0040,0.0176,0.0344,0.0656,0.1120,0.2016,0.3800"); + index_2("0.0040,0.0176,0.0344,0.0656,0.1120,0.2016,0.3800"); + values ("-0.0027,0.0090,0.0246,0.0520,0.0910,0.1613,0.3020",\ +"-0.0105,0.0012,0.0129,0.0363,0.0793,0.1535,0.2902",\ +"-0.0262,-0.0145,-0.0027,0.0246,0.0637,0.1379,0.2785",\ +"-0.0535,-0.0418,-0.0262,0.0012,0.0363,0.1105,0.2512",\ +"-0.0926,-0.0809,-0.0652,-0.0418,-0.0027,0.0715,0.2121",\ +"-0.1668,-0.1551,-0.1395,-0.1082,-0.0770,-0.0027,0.1379",\ +"-0.3035,-0.2918,-0.2762,-0.2488,-0.2137,-0.1434,-0.0027"); + } + + fall_constraint("SIG2SRAM_constraint_template") { + index_1("0.0040,0.0176,0.0344,0.0656,0.1120,0.2016,0.3800"); + index_2("0.0040,0.0176,0.0344,0.0656,0.1120,0.2016,0.3800"); + values ("0.0832,0.0949,0.1105,0.1379,0.1730,0.2473,0.3801",\ +"0.0754,0.0832,0.0988,0.1223,0.1613,0.2355,0.3684",\ +"0.0598,0.0676,0.0832,0.1066,0.1457,0.2121,0.3527",\ +"0.0324,0.0441,0.0598,0.0871,0.1223,0.1926,0.3293",\ +"-0.0066,0.0051,0.0168,0.0480,0.0832,0.1535,0.2902",\ +"-0.0809,-0.0691,-0.0574,-0.0301,0.0090,0.0832,0.2121",\ +"-0.2176,-0.2059,-0.1941,-0.1668,-0.1277,-0.0574,0.0793"); + } + } + + + timing() { + timing_type : hold_rising; + related_pin : "A_BIST_CLK"; + when : "A_BIST_MEN" + sdf_cond : "A_BIST_MEN" + + rise_constraint("SIG2SRAM_constraint_template") { + index_1("0.0040,0.0176,0.0344,0.0656,0.1120,0.2016,0.3800"); + index_2("0.0040,0.0176,0.0344,0.0656,0.1120,0.2016,0.3800"); + values ("0.1887,0.1770,0.1613,0.1340,0.0949,0.0207,-0.1160",\ +"0.1965,0.1848,0.1730,0.1457,0.1027,0.0324,-0.1082",\ +"0.2160,0.2004,0.1887,0.1613,0.1184,0.0480,-0.0926",\ +"0.2395,0.2277,0.2121,0.1848,0.1457,0.0715,-0.0652",\ +"0.2785,0.2668,0.2512,0.2238,0.1848,0.1105,-0.0262",\ +"0.3527,0.3410,0.3254,0.2980,0.2551,0.1848,0.0480",\ +"0.4934,0.4816,0.4660,0.4387,0.3957,0.3254,0.1887"); + } + + fall_constraint("SIG2SRAM_constraint_template") { + index_1("0.0040,0.0176,0.0344,0.0656,0.1120,0.2016,0.3800"); + index_2("0.0040,0.0176,0.0344,0.0656,0.1120,0.2016,0.3800"); + values ("0.1730,0.1613,0.1496,0.1184,0.0793,0.0129,-0.1238",\ +"0.1848,0.1730,0.1574,0.1301,0.0910,0.0207,-0.1121",\ +"0.2004,0.1887,0.1730,0.1457,0.1066,0.0363,-0.1004",\ +"0.2238,0.2121,0.2004,0.1691,0.1340,0.0598,-0.0730",\ +"0.2629,0.2512,0.2395,0.2121,0.1691,0.0988,-0.0340",\ +"0.3371,0.3254,0.3137,0.2863,0.2434,0.1730,0.0402",\ +"0.4777,0.4660,0.4504,0.4230,0.3840,0.3137,0.1809"); + } + } + } +pin(A_BIST_MEN) { + direction : input ; + capacitance : 0.00326046 ; + max_transition : "0.38" ; + related_power_pin : VDD; + related_ground_pin : VSS; + internal_power() { + rise_power("scalar"){ + values (0.2714); + } + fall_power("scalar"){ + values (0.0108); + } + } + timing() { + timing_type : setup_rising; + related_pin : "A_BIST_CLK"; + + rise_constraint("SIG2SRAM_constraint_template") { + index_1("0.0040,0.0176,0.0344,0.0656,0.1120,0.2016,0.3800"); + index_2("0.0040,0.0176,0.0344,0.0656,0.1120,0.2016,0.3800"); + values ("0.1418,0.1496,0.1652,0.1926,0.2316,0.3059,0.4465",\ +"0.1301,0.1379,0.1535,0.1809,0.2199,0.2941,0.4348",\ +"0.1145,0.1262,0.1418,0.1652,0.2043,0.2785,0.4191",\ +"0.0871,0.0949,0.1105,0.1379,0.1770,0.2512,0.3879",\ +"0.0480,0.0598,0.0754,0.0988,0.1379,0.2082,0.3488",\ +"-0.0262,-0.0145,0.0012,0.0285,0.0676,0.1379,0.2785",\ +"-0.1668,-0.1551,-0.1395,-0.1121,-0.0730,0.0012,0.1379"); + } + + fall_constraint("SIG2SRAM_constraint_template") { + index_1("0.0040,0.0176,0.0344,0.0656,0.1120,0.2016,0.3800"); + index_2("0.0040,0.0176,0.0344,0.0656,0.1120,0.2016,0.3800"); + values ("0.2082,0.2199,0.2316,0.2590,0.2980,0.3723,0.5051",\ +"0.1965,0.2082,0.2199,0.2473,0.2863,0.3605,0.4934",\ +"0.1809,0.1926,0.2043,0.2316,0.2707,0.3449,0.4777",\ +"0.1574,0.1691,0.1809,0.2082,0.2434,0.3176,0.4543",\ +"0.1145,0.1262,0.1418,0.1691,0.2043,0.2785,0.4113",\ +"0.0441,0.0559,0.0676,0.0949,0.1301,0.2004,0.3332",\ +"-0.0965,-0.0848,-0.0691,-0.0418,-0.0066,0.0676,0.2004"); + } + } + + + timing() { + timing_type : hold_rising; + related_pin : "A_BIST_CLK"; + + rise_constraint("SIG2SRAM_constraint_template") { + index_1("0.0040,0.0176,0.0344,0.0656,0.1120,0.2016,0.3800"); + index_2("0.0040,0.0176,0.0344,0.0656,0.1120,0.2016,0.3800"); + values ("0.1770,0.1652,0.1535,0.1262,0.0832,0.0129,-0.1277",\ +"0.1887,0.1770,0.1613,0.1340,0.0949,0.0207,-0.1199",\ +"0.2043,0.1926,0.1770,0.1496,0.1105,0.0363,-0.1043",\ +"0.2277,0.2160,0.2043,0.1770,0.1379,0.0598,-0.0770",\ +"0.2668,0.2551,0.2434,0.2160,0.1730,0.0988,-0.0379",\ +"0.3449,0.3332,0.3176,0.2902,0.2473,0.1730,0.0363",\ +"0.4816,0.4699,0.4543,0.4270,0.3840,0.3098,0.1770"); + } + + fall_constraint("SIG2SRAM_constraint_template") { + index_1("0.0040,0.0176,0.0344,0.0656,0.1120,0.2016,0.3800"); + index_2("0.0040,0.0176,0.0344,0.0656,0.1120,0.2016,0.3800"); + values ("0.1613,0.1496,0.1379,0.1105,0.0715,0.0012,-0.1355",\ +"0.1730,0.1613,0.1496,0.1184,0.0832,0.0129,-0.1238",\ +"0.1887,0.1770,0.1652,0.1340,0.0988,0.0285,-0.1121",\ +"0.2121,0.2043,0.1887,0.1613,0.1223,0.0520,-0.0848",\ +"0.2551,0.2434,0.2277,0.2004,0.1613,0.0910,-0.0418",\ +"0.3293,0.3176,0.3020,0.2746,0.2395,0.1652,0.0324",\ +"0.4660,0.4543,0.4426,0.4113,0.3762,0.3020,0.1691"); + } + } + } +bus(A_BIST_BM) { + bus_type : D_31_0; + direction : input ; + capacitance : 0.00353394 ; + max_transition : "0.38" ; + pin(A_BIST_BM[31:0]) { + related_power_pin : VDD; + related_ground_pin : VSS; + internal_power() { + when : "A_BIST_MEN"; + rise_power("scalar"){ + values (0.1809); + } + fall_power("scalar"){ + values (0.1563); + } + } + internal_power() { + when : "!A_BIST_MEN"; + rise_power("scalar"){ + values (0.1509); + } + fall_power("scalar"){ + values (0.1509); + } + } + } + timing() { + timing_type : setup_rising; + related_pin : "A_BIST_CLK"; + when : "(A_BIST_WEN & A_BIST_MEN)" + sdf_cond : "A_BIST_RW_ACCESS" + + rise_constraint("SIG2SRAM_constraint_template") { + index_1("0.0040,0.0176,0.0344,0.0656,0.1120,0.2016,0.3800"); + index_2("0.0040,0.0176,0.0344,0.0656,0.1120,0.2016,0.3800"); + values ("-0.2898,-0.2791,-0.2634,-0.2380,-0.1970,-0.1238,0.0110",\ +"-0.2937,-0.2829,-0.2673,-0.2419,-0.2009,-0.1277,0.0071",\ +"-0.2974,-0.2866,-0.2710,-0.2456,-0.2046,-0.1313,0.0034",\ +"-0.3006,-0.2898,-0.2742,-0.2488,-0.2078,-0.1346,0.0002",\ +"-0.3132,-0.3024,-0.2868,-0.2614,-0.2204,-0.1472,-0.0124",\ +"-0.3308,-0.3200,-0.3044,-0.2790,-0.2380,-0.1648,-0.0300",\ +"-0.3583,-0.3475,-0.3319,-0.3065,-0.2655,-0.1923,-0.0575"); + } + + fall_constraint("SIG2SRAM_constraint_template") { + index_1("0.0040,0.0176,0.0344,0.0656,0.1120,0.2016,0.3800"); + index_2("0.0040,0.0176,0.0344,0.0656,0.1120,0.2016,0.3800"); + values ("-0.2664,-0.2546,-0.2419,-0.2146,-0.1775,-0.1042,0.0237",\ +"-0.2702,-0.2585,-0.2458,-0.2185,-0.1814,-0.1081,0.0198",\ +"-0.2739,-0.2622,-0.2495,-0.2222,-0.1851,-0.1118,0.0161",\ +"-0.2771,-0.2654,-0.2527,-0.2254,-0.1883,-0.1150,0.0129",\ +"-0.2897,-0.2780,-0.2653,-0.2380,-0.2009,-0.1276,0.0003",\ +"-0.3073,-0.2956,-0.2829,-0.2556,-0.2185,-0.1452,-0.0173",\ +"-0.3349,-0.3231,-0.3104,-0.2831,-0.2460,-0.1727,-0.0448"); + } + } + + + timing() { + timing_type : hold_rising; + related_pin : "A_BIST_CLK"; + when : "(A_BIST_WEN & A_BIST_MEN)" + sdf_cond : "A_BIST_RW_ACCESS" + + rise_constraint("SIG2SRAM_constraint_template") { + index_1("0.0040,0.0176,0.0344,0.0656,0.1120,0.2016,0.3800"); + index_2("0.0040,0.0176,0.0344,0.0656,0.1120,0.2016,0.3800"); + values ("0.3958,0.3860,0.3704,0.3440,0.3069,0.2327,0.0979",\ +"0.3997,0.3899,0.3743,0.3479,0.3108,0.2366,0.1018",\ +"0.4033,0.3936,0.3780,0.3516,0.3145,0.2403,0.1055",\ +"0.4065,0.3968,0.3811,0.3548,0.3177,0.2435,0.1087",\ +"0.4192,0.4094,0.3938,0.3674,0.3303,0.2561,0.1213",\ +"0.4368,0.4270,0.4114,0.3850,0.3479,0.2737,0.1389",\ +"0.4643,0.4545,0.4389,0.4125,0.3754,0.3012,0.1664"); + } + + fall_constraint("SIG2SRAM_constraint_template") { + index_1("0.0040,0.0176,0.0344,0.0656,0.1120,0.2016,0.3800"); + index_2("0.0040,0.0176,0.0344,0.0656,0.1120,0.2016,0.3800"); + values ("0.3675,0.3567,0.3430,0.3157,0.2796,0.2073,0.0774",\ +"0.3713,0.3606,0.3469,0.3196,0.2834,0.2112,0.0813",\ +"0.3750,0.3643,0.3506,0.3233,0.2871,0.2149,0.0850",\ +"0.3782,0.3675,0.3538,0.3265,0.2903,0.2181,0.0882",\ +"0.3908,0.3801,0.3664,0.3391,0.3029,0.2307,0.1008",\ +"0.4084,0.3977,0.3840,0.3567,0.3206,0.2483,0.1184",\ +"0.4360,0.4252,0.4115,0.3842,0.3481,0.2758,0.1459"); + } + } +} + pin(A_BIST_CLK) { + direction : input; + capacitance : 0.00389386; + max_transition : "0.38"; + clock : "true" ; + pin_func_type : active_rising ; + + timing () { + timing_type : "min_pulse_width"; + related_pin : "A_BIST_CLK"; + rise_constraint("CLKTRAN_constraint_template") { + index_1("0.004,0.38"); + values("0.12,0.12"); + } + } + + related_power_pin : VDD; + related_ground_pin : VSS; + + internal_power() { + when : "!A_BIST_MEN & !A_BIST_WEN & !A_BIST_REN"; + rise_power("scalar"){ + values (0); + } + fall_power("scalar"){ + values (0); + } + } + internal_power() { + when : "!A_BIST_MEN & A_BIST_WEN & !A_BIST_REN"; + rise_power("scalar"){ + values (0.6783); + } + fall_power("scalar"){ + values (0); + } + } + internal_power() { + when : "A_BIST_MEN & A_BIST_WEN & !A_BIST_REN"; + rise_power("scalar"){ + values (41.2558); + } + fall_power("scalar"){ + values (0); + } + } + internal_power() { + when : "A_BIST_MEN & A_BIST_WEN & A_BIST_REN"; + rise_power("scalar"){ + values (46.5325); + } + fall_power("scalar"){ + values (0); + } + } + internal_power() { + when : "A_BIST_MEN & !A_BIST_WEN & A_BIST_REN"; + rise_power("scalar"){ + values (34.0312); + } + fall_power("scalar"){ + values (0); + } + } + internal_power() { + when : "!A_BIST_MEN & !A_BIST_WEN & A_BIST_REN"; + rise_power("scalar"){ + values (0.4087); + } + fall_power("scalar"){ + values (0); + } + } + internal_power() { + when : "!A_BIST_MEN & A_BIST_WEN & A_BIST_REN"; + rise_power("scalar"){ + values (1.3353); + } + fall_power("scalar"){ + values (0); + } + } + internal_power() { + when : "A_BIST_MEN & !A_BIST_WEN & !A_BIST_REN"; + rise_power("scalar"){ + values (0); + } + fall_power("scalar"){ + values (0); + } + } + } + bus(A_BIST_DIN) { + bus_type : D_31_0; + direction : input ; + capacitance : 0.00397186 ; + memory_write() { + address : A_BIST_ADDR ; + clocked_on : A_BIST_CLK; + } + + max_transition : "0.38" ; + pin(A_BIST_DIN[31:0]) { + related_power_pin : VDD; + related_ground_pin : VSS; + internal_power() { + when : "A_BIST_MEN"; + rise_power("scalar"){ + values (0.1809); + } + fall_power("scalar"){ + values (0.1563); + } + } + internal_power() { + when : "!A_BIST_MEN"; + rise_power("scalar"){ + values (0.1509); + } + fall_power("scalar"){ + values (0.1509); + } + } + } + timing() { + timing_type : setup_rising; + related_pin : "A_BIST_CLK"; + when : "(A_BIST_WEN & A_BIST_MEN)"; + sdf_cond : "A_BIST_W_ACCESS"; + + rise_constraint("SIG2SRAM_constraint_template") { + index_1("0.0040,0.0176,0.0344,0.0656,0.1120,0.2016,0.3800"); + index_2("0.0040,0.0176,0.0344,0.0656,0.1120,0.2016,0.3800"); + values ("-0.2898,-0.2791,-0.2634,-0.2380,-0.1970,-0.1238,0.0110",\ +"-0.2937,-0.2829,-0.2673,-0.2419,-0.2009,-0.1277,0.0071",\ +"-0.2974,-0.2866,-0.2710,-0.2456,-0.2046,-0.1313,0.0034",\ +"-0.3006,-0.2898,-0.2742,-0.2488,-0.2078,-0.1346,0.0002",\ +"-0.3132,-0.3024,-0.2868,-0.2614,-0.2204,-0.1472,-0.0124",\ +"-0.3308,-0.3200,-0.3044,-0.2790,-0.2380,-0.1648,-0.0300",\ +"-0.3583,-0.3475,-0.3319,-0.3065,-0.2655,-0.1923,-0.0575"); + } + + fall_constraint("SIG2SRAM_constraint_template") { + index_1("0.0040,0.0176,0.0344,0.0656,0.1120,0.2016,0.3800"); + index_2("0.0040,0.0176,0.0344,0.0656,0.1120,0.2016,0.3800"); + values ("-0.2664,-0.2546,-0.2419,-0.2146,-0.1775,-0.1042,0.0237",\ +"-0.2702,-0.2585,-0.2458,-0.2185,-0.1814,-0.1081,0.0198",\ +"-0.2739,-0.2622,-0.2495,-0.2222,-0.1851,-0.1118,0.0161",\ +"-0.2771,-0.2654,-0.2527,-0.2254,-0.1883,-0.1150,0.0129",\ +"-0.2897,-0.2780,-0.2653,-0.2380,-0.2009,-0.1276,0.0003",\ +"-0.3073,-0.2956,-0.2829,-0.2556,-0.2185,-0.1452,-0.0173",\ +"-0.3349,-0.3231,-0.3104,-0.2831,-0.2460,-0.1727,-0.0448"); + } + } + + timing() { + timing_type : hold_rising; + related_pin : "A_BIST_CLK"; + when : "(A_BIST_WEN & A_BIST_MEN)"; + sdf_cond : "A_BIST_W_ACCESS"; + + rise_constraint("SIG2SRAM_constraint_template") { + index_1("0.0040,0.0176,0.0344,0.0656,0.1120,0.2016,0.3800"); + index_2("0.0040,0.0176,0.0344,0.0656,0.1120,0.2016,0.3800"); + values ("0.3958,0.3860,0.3704,0.3440,0.3069,0.2327,0.0979",\ +"0.3997,0.3899,0.3743,0.3479,0.3108,0.2366,0.1018",\ +"0.4033,0.3936,0.3780,0.3516,0.3145,0.2403,0.1055",\ +"0.4065,0.3968,0.3811,0.3548,0.3177,0.2435,0.1087",\ +"0.4192,0.4094,0.3938,0.3674,0.3303,0.2561,0.1213",\ +"0.4368,0.4270,0.4114,0.3850,0.3479,0.2737,0.1389",\ +"0.4643,0.4545,0.4389,0.4125,0.3754,0.3012,0.1664"); + } + + fall_constraint("SIG2SRAM_constraint_template") { + index_1("0.0040,0.0176,0.0344,0.0656,0.1120,0.2016,0.3800"); + index_2("0.0040,0.0176,0.0344,0.0656,0.1120,0.2016,0.3800"); + values ("0.3675,0.3567,0.3430,0.3157,0.2796,0.2073,0.0774",\ +"0.3713,0.3606,0.3469,0.3196,0.2834,0.2112,0.0813",\ +"0.3750,0.3643,0.3506,0.3233,0.2871,0.2149,0.0850",\ +"0.3782,0.3675,0.3538,0.3265,0.2903,0.2181,0.0882",\ +"0.3908,0.3801,0.3664,0.3391,0.3029,0.2307,0.1008",\ +"0.4084,0.3977,0.3840,0.3567,0.3206,0.2483,0.1184",\ +"0.4360,0.4252,0.4115,0.3842,0.3481,0.2758,0.1459"); + } + } + } + +bus(A_DOUT) { + + bus_type : D_31_0; + direction : output ; + capacitance : 0 ; + max_capacitance : 0.064 ; + memory_read() { + address : A_ADDR ; + } + pin(A_DOUT[31:0]) { + related_power_pin : VDD; + related_ground_pin : VSS; + internal_power() { + rise_power("scalar") { + values (0); + } + fall_power("scalar") { + values (0); + } + } + } + timing() { + related_pin : "A_CLK"; + timing_type : rising_edge ; + timing_sense : non_unate ; + + cell_rise(SIG2SRAM_delay_template) { + index_1("0.0040,0.0176,0.0344,0.0656,0.1120,0.2016,0.3800"); + index_2("0.0008,0.0014,0.0051,0.0100,0.0339,0.0640"); + values ("1.9084,1.9094,1.9142,1.9197,1.9406,1.9641",\ +"1.9143,1.9153,1.9202,1.9257,1.9466,1.9701",\ +"1.9171,1.9181,1.9229,1.9284,1.9493,1.9728",\ +"1.9213,1.9223,1.9271,1.9326,1.9535,1.9770",\ +"1.9329,1.9339,1.9387,1.9442,1.9652,1.9887",\ +"1.9520,1.9530,1.9578,1.9634,1.9843,2.0078",\ +"1.9784,1.9794,1.9842,1.9897,2.0107,2.0342"); + } + cell_fall(SIG2SRAM_delay_template) { + index_1("0.0040,0.0176,0.0344,0.0656,0.1120,0.2016,0.3800"); + index_2("0.0008,0.0014,0.0051,0.0100,0.0339,0.0640"); + values ("1.8741,1.8749,1.8790,1.8835,1.9006,1.9173",\ +"1.8800,1.8809,1.8849,1.8895,1.9066,1.9233",\ +"1.8828,1.8836,1.8877,1.8922,1.9093,1.9260",\ +"1.8870,1.8879,1.8919,1.8964,1.9135,1.9303",\ +"1.8986,1.8995,1.9035,1.9081,1.9251,1.9419",\ +"1.9177,1.9186,1.9226,1.9272,1.9443,1.9610",\ +"1.9441,1.9450,1.9490,1.9536,1.9706,1.9874"); + } + + rise_transition(SRAM_load_template) { + index_1("0.0008,0.0014,0.0051,0.0100,0.0339,0.0640"); + values ("0.0206,0.0210,0.0265,0.0323,0.0606,0.0955"); + } + fall_transition(SRAM_load_template) { + index_1("0.0008,0.0014,0.0051,0.0100,0.0339,0.0640"); + values ("0.0170,0.0177,0.0222,0.0270,0.0451,0.0644"); + } + } +} + pin(B_DLY) { + direction : input ; + capacitance : 0.00421562 ; + max_transition : "1" ; + related_power_pin : VDD; + related_ground_pin : VSS; + internal_power() { + rise_power("scalar") { + values (0); + } + fall_power("scalar") { + values (0); + } + } + } + +bus(B_ADDR) { + bus_type : A_7_0; + direction : input ; + capacitance : 0.0115194 ; + pin(B_ADDR[0]) { + capacitance : 0.0056487 ; + } + pin(B_ADDR[1]) { + capacitance : 0.00741688 ; + } + pin(B_ADDR[2]) { + capacitance : 0.0100613 ; + } + pin(B_ADDR[3]) { + capacitance : 0.00667339 ; + } + pin(B_ADDR[4]) { + capacitance : 0.00620204 ; + } + pin(B_ADDR[5]) { + capacitance : 0.0101975 ; + } + pin(B_ADDR[6]) { + capacitance : 0.0124055 ; + } + max_transition : "0.38" ; + pin(B_ADDR[7:0]) { + related_power_pin : VDD; + related_ground_pin : VSS; + internal_power() { + when : "B_MEN"; + rise_power("scalar"){ + values (0.0108); + } + fall_power("scalar"){ + values (0.0034); + } + } + internal_power() { + when : "!B_MEN"; + rise_power("scalar"){ + values (0.0264); + } + fall_power("scalar"){ + values (0.0033); + } + } + } + timing() { + timing_type : setup_rising; + related_pin : "B_CLK"; + when : "((B_WEN | B_REN)& B_MEN)" + sdf_cond : "B_RW_ACCESS" + + rise_constraint("SIG2SRAM_constraint_template") { + index_1("0.0040,0.0176,0.0344,0.0656,0.1120,0.2016,0.3800"); + index_2("0.0040,0.0176,0.0344,0.0656,0.1120,0.2016,0.3800"); + values ("-0.2371,-0.2215,-0.2098,-0.1824,-0.1434,-0.0691,0.0676",\ +"-0.2449,-0.2332,-0.2176,-0.1902,-0.1551,-0.0770,0.0559",\ +"-0.2605,-0.2488,-0.2332,-0.2059,-0.1707,-0.0965,0.0441",\ +"-0.2879,-0.2723,-0.2605,-0.2332,-0.1941,-0.1199,0.0168",\ +"-0.3230,-0.3113,-0.2996,-0.2723,-0.2332,-0.1590,-0.0184",\ +"-0.4012,-0.3895,-0.3738,-0.3465,-0.3074,-0.2332,-0.0965",\ +"-0.5379,-0.5262,-0.5105,-0.4832,-0.4480,-0.3699,-0.2332"); + } + + fall_constraint("SIG2SRAM_constraint_template") { + index_1("0.0040,0.0176,0.0344,0.0656,0.1120,0.2016,0.3800"); + index_2("0.0040,0.0176,0.0344,0.0656,0.1120,0.2016,0.3800"); + values ("-0.1785,-0.1707,-0.1551,-0.1277,-0.0887,-0.0184,0.1145",\ +"-0.1902,-0.1785,-0.1629,-0.1355,-0.1004,-0.0262,0.1027",\ +"-0.2059,-0.1941,-0.1785,-0.1512,-0.1160,-0.0418,0.0871",\ +"-0.2293,-0.2176,-0.2059,-0.1785,-0.1434,-0.0691,0.0598",\ +"-0.2684,-0.2566,-0.2449,-0.2176,-0.1824,-0.1082,0.0207",\ +"-0.3465,-0.3348,-0.3191,-0.2918,-0.2566,-0.1824,-0.0535",\ +"-0.4832,-0.4715,-0.4559,-0.4324,-0.3934,-0.3191,-0.1902"); + } + } + + + timing() { + timing_type : hold_rising; + related_pin : "B_CLK"; + when : "((B_WEN | B_REN)& B_MEN)" + sdf_cond : "B_RW_ACCESS" + + rise_constraint("SIG2SRAM_constraint_template") { + index_1("0.0040,0.0176,0.0344,0.0656,0.1120,0.2016,0.3800"); + index_2("0.0040,0.0176,0.0344,0.0656,0.1120,0.2016,0.3800"); + values ("0.3410,0.3293,0.3137,0.2863,0.2473,0.1730,0.0324",\ +"0.3488,0.3371,0.3215,0.2941,0.2590,0.1809,0.0480",\ +"0.3684,0.3527,0.3371,0.3098,0.2746,0.1965,0.0598",\ +"0.3918,0.3762,0.3645,0.3371,0.2980,0.2238,0.0871",\ +"0.4309,0.4152,0.4035,0.3762,0.3371,0.2629,0.1223",\ +"0.5051,0.4934,0.4777,0.4504,0.4113,0.3371,0.1965",\ +"0.6418,0.6262,0.6145,0.5871,0.5520,0.4738,0.3332"); + } + + fall_constraint("SIG2SRAM_constraint_template") { + index_1("0.0040,0.0176,0.0344,0.0656,0.1120,0.2016,0.3800"); + index_2("0.0040,0.0176,0.0344,0.0656,0.1120,0.2016,0.3800"); + values ("0.2824,0.2707,0.2551,0.2277,0.1926,0.1184,-0.0105",\ +"0.2902,0.2785,0.2668,0.2395,0.2043,0.1301,0.0012",\ +"0.3059,0.2941,0.2824,0.2551,0.2199,0.1457,0.0168",\ +"0.3332,0.3215,0.3059,0.2785,0.2434,0.1691,0.0402",\ +"0.3723,0.3605,0.3449,0.3176,0.2824,0.2121,0.0793",\ +"0.4465,0.4348,0.4230,0.3918,0.3566,0.2824,0.1535",\ +"0.5832,0.5715,0.5598,0.5324,0.4934,0.4191,0.2902"); + } + } +} +pin(B_WEN) { + direction : input ; + capacitance : 0.00341384 ; + max_transition : "0.38" ; + related_power_pin : VDD; + related_ground_pin : VSS; + internal_power() { + when : "B_MEN"; + rise_power("scalar"){ + values (0.0040); + } + fall_power("scalar"){ + values (0.0171); + } + } + internal_power() { + when : "!B_MEN"; + rise_power("scalar"){ + values (0.0050); + } + fall_power("scalar"){ + values (0.0218); + } + } + timing() { + timing_type : setup_rising; + related_pin : "B_CLK"; + when : "B_MEN" + sdf_cond : "B_MEN" + + rise_constraint("SIG2SRAM_constraint_template") { + index_1("0.0040,0.0176,0.0344,0.0656,0.1120,0.2016,0.3800"); + index_2("0.0040,0.0176,0.0344,0.0656,0.1120,0.2016,0.3800"); + values ("0.1418,0.1496,0.1652,0.1887,0.2316,0.3059,0.4465",\ +"0.1301,0.1379,0.1535,0.1809,0.2199,0.2941,0.4348",\ +"0.1145,0.1262,0.1379,0.1652,0.2043,0.2785,0.4191",\ +"0.0871,0.0949,0.1105,0.1379,0.1770,0.2512,0.3879",\ +"0.0480,0.0598,0.0754,0.0988,0.1379,0.2082,0.3527",\ +"-0.0262,-0.0145,0.0012,0.0246,0.0676,0.1379,0.2785",\ +"-0.1668,-0.1551,-0.1395,-0.1121,-0.0730,0.0012,0.1418"); + } + + fall_constraint("SIG2SRAM_constraint_template") { + index_1("0.0040,0.0176,0.0344,0.0656,0.1120,0.2016,0.3800"); + index_2("0.0040,0.0176,0.0344,0.0656,0.1120,0.2016,0.3800"); + values ("0.2082,0.2160,0.2316,0.2590,0.2941,0.3684,0.5012",\ +"0.1926,0.2043,0.2199,0.2473,0.2824,0.3566,0.4895",\ +"0.1770,0.1887,0.2043,0.2316,0.2668,0.3410,0.4777",\ +"0.1535,0.1652,0.1770,0.2043,0.2395,0.3137,0.4504",\ +"0.1145,0.1262,0.1379,0.1652,0.2043,0.2746,0.4113",\ +"0.0402,0.0520,0.0676,0.0910,0.1262,0.2004,0.3332",\ +"-0.0965,-0.0848,-0.0730,-0.0457,-0.0066,0.0637,0.2004"); + } + } + + + timing() { + timing_type : hold_rising; + related_pin : "B_CLK"; + when : "B_MEN" + sdf_cond : "B_MEN" + + rise_constraint("SIG2SRAM_constraint_template") { + index_1("0.0040,0.0176,0.0344,0.0656,0.1120,0.2016,0.3800"); + index_2("0.0040,0.0176,0.0344,0.0656,0.1120,0.2016,0.3800"); + values ("0.1770,0.1652,0.1496,0.1223,0.0793,0.0090,-0.1316",\ +"0.1848,0.1730,0.1574,0.1301,0.0910,0.0168,-0.1199",\ +"0.2004,0.1887,0.1770,0.1496,0.1066,0.0363,-0.1043",\ +"0.2277,0.2160,0.2004,0.1730,0.1340,0.0598,-0.0809",\ +"0.2668,0.2551,0.2395,0.2121,0.1730,0.0988,-0.0418",\ +"0.3410,0.3293,0.3137,0.2863,0.2434,0.1730,0.0324",\ +"0.4816,0.4699,0.4543,0.4230,0.3801,0.3098,0.1730"); + } + + fall_constraint("SIG2SRAM_constraint_template") { + index_1("0.0040,0.0176,0.0344,0.0656,0.1120,0.2016,0.3800"); + index_2("0.0040,0.0176,0.0344,0.0656,0.1120,0.2016,0.3800"); + values ("0.1613,0.1496,0.1379,0.1066,0.0715,0.0012,-0.1355",\ +"0.1730,0.1613,0.1457,0.1184,0.0832,0.0129,-0.1238",\ +"0.1887,0.1770,0.1613,0.1340,0.0988,0.0246,-0.1121",\ +"0.2121,0.2043,0.1887,0.1613,0.1223,0.0520,-0.0848",\ +"0.2512,0.2434,0.2277,0.2004,0.1613,0.0910,-0.0457",\ +"0.3254,0.3176,0.3020,0.2746,0.2355,0.1652,0.0324",\ +"0.4660,0.4543,0.4387,0.4113,0.3723,0.3020,0.1691"); + } + } + } +pin(B_REN) { + direction : input ; + capacitance : 0.00390661 ; + max_transition : "0.38" ; + related_power_pin : VDD; + related_ground_pin : VSS; + internal_power() { + when : "B_MEN"; + rise_power("scalar"){ + values (0.0122); + } + fall_power("scalar"){ + values (0.0105); + } + } + internal_power() { + when : "!B_MEN"; + rise_power("scalar"){ + values (0.0181); + } + fall_power("scalar"){ + values (0.0202); + } + } + timing() { + timing_type : setup_rising; + related_pin : "B_CLK"; + when : "B_MEN" + sdf_cond : "B_MEN" + + rise_constraint("SIG2SRAM_constraint_template") { + index_1("0.0040,0.0176,0.0344,0.0656,0.1120,0.2016,0.3800"); + index_2("0.0040,0.0176,0.0344,0.0656,0.1120,0.2016,0.3800"); + values ("-0.0027,0.0090,0.0246,0.0520,0.0910,0.1613,0.3020",\ +"-0.0105,0.0012,0.0129,0.0363,0.0793,0.1535,0.2902",\ +"-0.0262,-0.0145,-0.0027,0.0246,0.0637,0.1379,0.2785",\ +"-0.0535,-0.0418,-0.0262,0.0012,0.0363,0.1105,0.2512",\ +"-0.0926,-0.0809,-0.0652,-0.0418,-0.0027,0.0715,0.2121",\ +"-0.1668,-0.1551,-0.1395,-0.1082,-0.0770,-0.0027,0.1379",\ +"-0.3035,-0.2918,-0.2762,-0.2488,-0.2137,-0.1434,-0.0027"); + } + + fall_constraint("SIG2SRAM_constraint_template") { + index_1("0.0040,0.0176,0.0344,0.0656,0.1120,0.2016,0.3800"); + index_2("0.0040,0.0176,0.0344,0.0656,0.1120,0.2016,0.3800"); + values ("0.0832,0.0949,0.1105,0.1379,0.1730,0.2473,0.3801",\ +"0.0754,0.0832,0.0988,0.1223,0.1613,0.2355,0.3684",\ +"0.0598,0.0676,0.0832,0.1066,0.1457,0.2121,0.3527",\ +"0.0324,0.0441,0.0598,0.0871,0.1223,0.1926,0.3293",\ +"-0.0066,0.0051,0.0168,0.0480,0.0832,0.1535,0.2902",\ +"-0.0809,-0.0691,-0.0574,-0.0301,0.0090,0.0832,0.2121",\ +"-0.2176,-0.2059,-0.1941,-0.1668,-0.1277,-0.0574,0.0793"); + } + } + + + timing() { + timing_type : hold_rising; + related_pin : "B_CLK"; + when : "B_MEN" + sdf_cond : "B_MEN" + + rise_constraint("SIG2SRAM_constraint_template") { + index_1("0.0040,0.0176,0.0344,0.0656,0.1120,0.2016,0.3800"); + index_2("0.0040,0.0176,0.0344,0.0656,0.1120,0.2016,0.3800"); + values ("0.1887,0.1770,0.1613,0.1340,0.0949,0.0207,-0.1160",\ +"0.1965,0.1848,0.1730,0.1457,0.1027,0.0324,-0.1082",\ +"0.2160,0.2004,0.1887,0.1613,0.1184,0.0480,-0.0926",\ +"0.2395,0.2277,0.2121,0.1848,0.1457,0.0715,-0.0652",\ +"0.2785,0.2668,0.2512,0.2238,0.1848,0.1105,-0.0262",\ +"0.3527,0.3410,0.3254,0.2980,0.2551,0.1848,0.0480",\ +"0.4934,0.4816,0.4660,0.4387,0.3957,0.3254,0.1887"); + } + + fall_constraint("SIG2SRAM_constraint_template") { + index_1("0.0040,0.0176,0.0344,0.0656,0.1120,0.2016,0.3800"); + index_2("0.0040,0.0176,0.0344,0.0656,0.1120,0.2016,0.3800"); + values ("0.1730,0.1613,0.1496,0.1184,0.0793,0.0129,-0.1238",\ +"0.1848,0.1730,0.1574,0.1301,0.0910,0.0207,-0.1121",\ +"0.2004,0.1887,0.1730,0.1457,0.1066,0.0363,-0.1004",\ +"0.2238,0.2121,0.2004,0.1691,0.1340,0.0598,-0.0730",\ +"0.2629,0.2512,0.2395,0.2121,0.1691,0.0988,-0.0340",\ +"0.3371,0.3254,0.3137,0.2863,0.2434,0.1730,0.0402",\ +"0.4777,0.4660,0.4504,0.4230,0.3840,0.3137,0.1809"); + } + } + } +pin(B_MEN) { + direction : input ; + capacitance : 0.00326046 ; + max_transition : "0.38" ; + related_power_pin : VDD; + related_ground_pin : VSS; + internal_power() { + rise_power("scalar"){ + values (0.2714); + } + fall_power("scalar"){ + values (0.0108); + } + } + timing() { + timing_type : setup_rising; + related_pin : "B_CLK"; + + rise_constraint("SIG2SRAM_constraint_template") { + index_1("0.0040,0.0176,0.0344,0.0656,0.1120,0.2016,0.3800"); + index_2("0.0040,0.0176,0.0344,0.0656,0.1120,0.2016,0.3800"); + values ("0.1418,0.1496,0.1652,0.1926,0.2316,0.3059,0.4465",\ +"0.1301,0.1379,0.1535,0.1809,0.2199,0.2941,0.4348",\ +"0.1145,0.1262,0.1418,0.1652,0.2043,0.2785,0.4191",\ +"0.0871,0.0949,0.1105,0.1379,0.1770,0.2512,0.3879",\ +"0.0480,0.0598,0.0754,0.0988,0.1379,0.2082,0.3488",\ +"-0.0262,-0.0145,0.0012,0.0285,0.0676,0.1379,0.2785",\ +"-0.1668,-0.1551,-0.1395,-0.1121,-0.0730,0.0012,0.1379"); + } + + fall_constraint("SIG2SRAM_constraint_template") { + index_1("0.0040,0.0176,0.0344,0.0656,0.1120,0.2016,0.3800"); + index_2("0.0040,0.0176,0.0344,0.0656,0.1120,0.2016,0.3800"); + values ("0.2082,0.2199,0.2316,0.2590,0.2980,0.3723,0.5051",\ +"0.1965,0.2082,0.2199,0.2473,0.2863,0.3605,0.4934",\ +"0.1809,0.1926,0.2043,0.2316,0.2707,0.3449,0.4777",\ +"0.1574,0.1691,0.1809,0.2082,0.2434,0.3176,0.4543",\ +"0.1145,0.1262,0.1418,0.1691,0.2043,0.2785,0.4113",\ +"0.0441,0.0559,0.0676,0.0949,0.1301,0.2004,0.3332",\ +"-0.0965,-0.0848,-0.0691,-0.0418,-0.0066,0.0676,0.2004"); + } + } + + + timing() { + timing_type : hold_rising; + related_pin : "B_CLK"; + + rise_constraint("SIG2SRAM_constraint_template") { + index_1("0.0040,0.0176,0.0344,0.0656,0.1120,0.2016,0.3800"); + index_2("0.0040,0.0176,0.0344,0.0656,0.1120,0.2016,0.3800"); + values ("0.1770,0.1652,0.1535,0.1262,0.0832,0.0129,-0.1277",\ +"0.1887,0.1770,0.1613,0.1340,0.0949,0.0207,-0.1199",\ +"0.2043,0.1926,0.1770,0.1496,0.1105,0.0363,-0.1043",\ +"0.2277,0.2160,0.2043,0.1770,0.1379,0.0598,-0.0770",\ +"0.2668,0.2551,0.2434,0.2160,0.1730,0.0988,-0.0379",\ +"0.3449,0.3332,0.3176,0.2902,0.2473,0.1730,0.0363",\ +"0.4816,0.4699,0.4543,0.4270,0.3840,0.3098,0.1770"); + } + + fall_constraint("SIG2SRAM_constraint_template") { + index_1("0.0040,0.0176,0.0344,0.0656,0.1120,0.2016,0.3800"); + index_2("0.0040,0.0176,0.0344,0.0656,0.1120,0.2016,0.3800"); + values ("0.1613,0.1496,0.1379,0.1105,0.0715,0.0012,-0.1355",\ +"0.1730,0.1613,0.1496,0.1184,0.0832,0.0129,-0.1238",\ +"0.1887,0.1770,0.1652,0.1340,0.0988,0.0285,-0.1121",\ +"0.2121,0.2043,0.1887,0.1613,0.1223,0.0520,-0.0848",\ +"0.2551,0.2434,0.2277,0.2004,0.1613,0.0910,-0.0418",\ +"0.3293,0.3176,0.3020,0.2746,0.2395,0.1652,0.0324",\ +"0.4660,0.4543,0.4426,0.4113,0.3762,0.3020,0.1691"); + } + } + } +bus(B_BM) { + bus_type : D_31_0; + direction : input ; + capacitance : 0.00334781 ; + max_transition : "0.38" ; + pin(B_BM[31:0]) { + related_power_pin : VDD; + related_ground_pin : VSS; + internal_power() { + when : "B_MEN"; + rise_power("scalar"){ + values (0.1809); + } + fall_power("scalar"){ + values (0.1563); + } + } + internal_power() { + when : "!B_MEN"; + rise_power("scalar"){ + values (0.1509); + } + fall_power("scalar"){ + values (0.1509); + } + } + } + timing() { + timing_type : setup_rising; + related_pin : "B_CLK"; + when : "(B_WEN & B_MEN)" + sdf_cond : "B_RW_ACCESS" + + rise_constraint("SIG2SRAM_constraint_template") { + index_1("0.0040,0.0176,0.0344,0.0656,0.1120,0.2016,0.3800"); + index_2("0.0040,0.0176,0.0344,0.0656,0.1120,0.2016,0.3800"); + values ("-0.2898,-0.2791,-0.2634,-0.2380,-0.1970,-0.1238,0.0110",\ +"-0.2937,-0.2829,-0.2673,-0.2419,-0.2009,-0.1277,0.0071",\ +"-0.2974,-0.2866,-0.2710,-0.2456,-0.2046,-0.1313,0.0034",\ +"-0.3006,-0.2898,-0.2742,-0.2488,-0.2078,-0.1346,0.0002",\ +"-0.3132,-0.3024,-0.2868,-0.2614,-0.2204,-0.1472,-0.0124",\ +"-0.3308,-0.3200,-0.3044,-0.2790,-0.2380,-0.1648,-0.0300",\ +"-0.3583,-0.3475,-0.3319,-0.3065,-0.2655,-0.1923,-0.0575"); + } + + fall_constraint("SIG2SRAM_constraint_template") { + index_1("0.0040,0.0176,0.0344,0.0656,0.1120,0.2016,0.3800"); + index_2("0.0040,0.0176,0.0344,0.0656,0.1120,0.2016,0.3800"); + values ("-0.2664,-0.2546,-0.2419,-0.2146,-0.1775,-0.1042,0.0237",\ +"-0.2702,-0.2585,-0.2458,-0.2185,-0.1814,-0.1081,0.0198",\ +"-0.2739,-0.2622,-0.2495,-0.2222,-0.1851,-0.1118,0.0161",\ +"-0.2771,-0.2654,-0.2527,-0.2254,-0.1883,-0.1150,0.0129",\ +"-0.2897,-0.2780,-0.2653,-0.2380,-0.2009,-0.1276,0.0003",\ +"-0.3073,-0.2956,-0.2829,-0.2556,-0.2185,-0.1452,-0.0173",\ +"-0.3349,-0.3231,-0.3104,-0.2831,-0.2460,-0.1727,-0.0448"); + } + } + + + timing() { + timing_type : hold_rising; + related_pin : "B_CLK"; + when : "(B_WEN & B_MEN)" + sdf_cond : "B_RW_ACCESS" + + rise_constraint("SIG2SRAM_constraint_template") { + index_1("0.0040,0.0176,0.0344,0.0656,0.1120,0.2016,0.3800"); + index_2("0.0040,0.0176,0.0344,0.0656,0.1120,0.2016,0.3800"); + values ("0.3958,0.3860,0.3704,0.3440,0.3069,0.2327,0.0979",\ +"0.3997,0.3899,0.3743,0.3479,0.3108,0.2366,0.1018",\ +"0.4033,0.3936,0.3780,0.3516,0.3145,0.2403,0.1055",\ +"0.4065,0.3968,0.3811,0.3548,0.3177,0.2435,0.1087",\ +"0.4192,0.4094,0.3938,0.3674,0.3303,0.2561,0.1213",\ +"0.4368,0.4270,0.4114,0.3850,0.3479,0.2737,0.1389",\ +"0.4643,0.4545,0.4389,0.4125,0.3754,0.3012,0.1664"); + } + + fall_constraint("SIG2SRAM_constraint_template") { + index_1("0.0040,0.0176,0.0344,0.0656,0.1120,0.2016,0.3800"); + index_2("0.0040,0.0176,0.0344,0.0656,0.1120,0.2016,0.3800"); + values ("0.3675,0.3567,0.3430,0.3157,0.2796,0.2073,0.0774",\ +"0.3713,0.3606,0.3469,0.3196,0.2834,0.2112,0.0813",\ +"0.3750,0.3643,0.3506,0.3233,0.2871,0.2149,0.0850",\ +"0.3782,0.3675,0.3538,0.3265,0.2903,0.2181,0.0882",\ +"0.3908,0.3801,0.3664,0.3391,0.3029,0.2307,0.1008",\ +"0.4084,0.3977,0.3840,0.3567,0.3206,0.2483,0.1184",\ +"0.4360,0.4252,0.4115,0.3842,0.3481,0.2758,0.1459"); + } + } +} + pin(B_CLK) { + direction : input; + capacitance : 0.00389386; + max_transition : "0.38"; + clock : "true" ; + pin_func_type : active_rising ; + + timing () { + timing_type : "min_pulse_width"; + related_pin : "B_CLK"; + rise_constraint("CLKTRAN_constraint_template") { + index_1("0.004,0.38"); + values("0.12,0.12"); + } + } + + related_power_pin : VDD; + related_ground_pin : VSS; + + internal_power() { + when : "!B_MEN & !B_WEN & !B_REN"; + rise_power("scalar"){ + values (0); + } + fall_power("scalar"){ + values (0); + } + } + internal_power() { + when : "!B_MEN & B_WEN & !B_REN"; + rise_power("scalar"){ + values (0.6783); + } + fall_power("scalar"){ + values (0); + } + } + internal_power() { + when : "B_MEN & B_WEN & !B_REN"; + rise_power("scalar"){ + values (41.2558); + } + fall_power("scalar"){ + values (0); + } + } + internal_power() { + when : "B_MEN & B_WEN & B_REN"; + rise_power("scalar"){ + values (46.5325); + } + fall_power("scalar"){ + values (0); + } + } + internal_power() { + when : "B_MEN & !B_WEN & B_REN"; + rise_power("scalar"){ + values (34.0312); + } + fall_power("scalar"){ + values (0); + } + } + internal_power() { + when : "!B_MEN & !B_WEN & B_REN"; + rise_power("scalar"){ + values (0.4087); + } + fall_power("scalar"){ + values (0); + } + } + internal_power() { + when : "!B_MEN & B_WEN & B_REN"; + rise_power("scalar"){ + values (1.3353); + } + fall_power("scalar"){ + values (0); + } + } + internal_power() { + when : "B_MEN & !B_WEN & !B_REN"; + rise_power("scalar"){ + values (0); + } + fall_power("scalar"){ + values (0); + } + } + } + bus(B_DIN) { + bus_type : D_31_0; + direction : input ; + capacitance : 0.00468868 ; + memory_write() { + address : B_ADDR ; + clocked_on : B_CLK; + } + + max_transition : "0.38" ; + pin(B_DIN[31:0]) { + related_power_pin : VDD; + related_ground_pin : VSS; + internal_power() { + when : "B_MEN"; + rise_power("scalar"){ + values (0.1809); + } + fall_power("scalar"){ + values (0.1563); + } + } + internal_power() { + when : "!B_MEN"; + rise_power("scalar"){ + values (0.1509); + } + fall_power("scalar"){ + values (0.1509); + } + } + } + timing() { + timing_type : setup_rising; + related_pin : "B_CLK"; + when : "(B_WEN & B_MEN)"; + sdf_cond : "B_W_ACCESS"; + + rise_constraint("SIG2SRAM_constraint_template") { + index_1("0.0040,0.0176,0.0344,0.0656,0.1120,0.2016,0.3800"); + index_2("0.0040,0.0176,0.0344,0.0656,0.1120,0.2016,0.3800"); + values ("-0.2898,-0.2791,-0.2634,-0.2380,-0.1970,-0.1238,0.0110",\ +"-0.2937,-0.2829,-0.2673,-0.2419,-0.2009,-0.1277,0.0071",\ +"-0.2974,-0.2866,-0.2710,-0.2456,-0.2046,-0.1313,0.0034",\ +"-0.3006,-0.2898,-0.2742,-0.2488,-0.2078,-0.1346,0.0002",\ +"-0.3132,-0.3024,-0.2868,-0.2614,-0.2204,-0.1472,-0.0124",\ +"-0.3308,-0.3200,-0.3044,-0.2790,-0.2380,-0.1648,-0.0300",\ +"-0.3583,-0.3475,-0.3319,-0.3065,-0.2655,-0.1923,-0.0575"); + } + + fall_constraint("SIG2SRAM_constraint_template") { + index_1("0.0040,0.0176,0.0344,0.0656,0.1120,0.2016,0.3800"); + index_2("0.0040,0.0176,0.0344,0.0656,0.1120,0.2016,0.3800"); + values ("-0.2664,-0.2546,-0.2419,-0.2146,-0.1775,-0.1042,0.0237",\ +"-0.2702,-0.2585,-0.2458,-0.2185,-0.1814,-0.1081,0.0198",\ +"-0.2739,-0.2622,-0.2495,-0.2222,-0.1851,-0.1118,0.0161",\ +"-0.2771,-0.2654,-0.2527,-0.2254,-0.1883,-0.1150,0.0129",\ +"-0.2897,-0.2780,-0.2653,-0.2380,-0.2009,-0.1276,0.0003",\ +"-0.3073,-0.2956,-0.2829,-0.2556,-0.2185,-0.1452,-0.0173",\ +"-0.3349,-0.3231,-0.3104,-0.2831,-0.2460,-0.1727,-0.0448"); + } + } + + timing() { + timing_type : hold_rising; + related_pin : "B_CLK"; + when : "(B_WEN & B_MEN)"; + sdf_cond : "B_W_ACCESS"; + + rise_constraint("SIG2SRAM_constraint_template") { + index_1("0.0040,0.0176,0.0344,0.0656,0.1120,0.2016,0.3800"); + index_2("0.0040,0.0176,0.0344,0.0656,0.1120,0.2016,0.3800"); + values ("0.3958,0.3860,0.3704,0.3440,0.3069,0.2327,0.0979",\ +"0.3997,0.3899,0.3743,0.3479,0.3108,0.2366,0.1018",\ +"0.4033,0.3936,0.3780,0.3516,0.3145,0.2403,0.1055",\ +"0.4065,0.3968,0.3811,0.3548,0.3177,0.2435,0.1087",\ +"0.4192,0.4094,0.3938,0.3674,0.3303,0.2561,0.1213",\ +"0.4368,0.4270,0.4114,0.3850,0.3479,0.2737,0.1389",\ +"0.4643,0.4545,0.4389,0.4125,0.3754,0.3012,0.1664"); + } + + fall_constraint("SIG2SRAM_constraint_template") { + index_1("0.0040,0.0176,0.0344,0.0656,0.1120,0.2016,0.3800"); + index_2("0.0040,0.0176,0.0344,0.0656,0.1120,0.2016,0.3800"); + values ("0.3675,0.3567,0.3430,0.3157,0.2796,0.2073,0.0774",\ +"0.3713,0.3606,0.3469,0.3196,0.2834,0.2112,0.0813",\ +"0.3750,0.3643,0.3506,0.3233,0.2871,0.2149,0.0850",\ +"0.3782,0.3675,0.3538,0.3265,0.2903,0.2181,0.0882",\ +"0.3908,0.3801,0.3664,0.3391,0.3029,0.2307,0.1008",\ +"0.4084,0.3977,0.3840,0.3567,0.3206,0.2483,0.1184",\ +"0.4360,0.4252,0.4115,0.3842,0.3481,0.2758,0.1459"); + } + } + } + + pin(B_BIST_EN) { + direction : input ; + capacitance : 0.00421562 ; + max_transition : "1" ; + related_power_pin : VDD; + related_ground_pin : VSS; + internal_power() { + rise_power("scalar") { + values (0); + } + fall_power("scalar") { + values (0); + } + } + } + +bus(B_BIST_ADDR) { + bus_type : A_7_0; + direction : input ; + capacitance : 0.0115194 ; + pin(B_BIST_ADDR[0]) { + capacitance : 0.0056487 ; + } + pin(B_BIST_ADDR[1]) { + capacitance : 0.00741688 ; + } + pin(B_BIST_ADDR[2]) { + capacitance : 0.0100613 ; + } + pin(B_BIST_ADDR[3]) { + capacitance : 0.00667339 ; + } + pin(B_BIST_ADDR[4]) { + capacitance : 0.00620204 ; + } + pin(B_BIST_ADDR[5]) { + capacitance : 0.0101975 ; + } + pin(B_BIST_ADDR[6]) { + capacitance : 0.0124055 ; + } + max_transition : "0.38" ; + pin(B_BIST_ADDR[7:0]) { + related_power_pin : VDD; + related_ground_pin : VSS; + internal_power() { + when : "B_BIST_MEN"; + rise_power("scalar"){ + values (0.0108); + } + fall_power("scalar"){ + values (0.0034); + } + } + internal_power() { + when : "!B_BIST_MEN"; + rise_power("scalar"){ + values (0.0264); + } + fall_power("scalar"){ + values (0.0033); + } + } + } + timing() { + timing_type : setup_rising; + related_pin : "B_BIST_CLK"; + when : "((B_BIST_WEN | B_BIST_REN)& B_BIST_MEN)" + sdf_cond : "B_BIST_RW_ACCESS" + + rise_constraint("SIG2SRAM_constraint_template") { + index_1("0.0040,0.0176,0.0344,0.0656,0.1120,0.2016,0.3800"); + index_2("0.0040,0.0176,0.0344,0.0656,0.1120,0.2016,0.3800"); + values ("-0.2371,-0.2215,-0.2098,-0.1824,-0.1434,-0.0691,0.0676",\ +"-0.2449,-0.2332,-0.2176,-0.1902,-0.1551,-0.0770,0.0559",\ +"-0.2605,-0.2488,-0.2332,-0.2059,-0.1707,-0.0965,0.0441",\ +"-0.2879,-0.2723,-0.2605,-0.2332,-0.1941,-0.1199,0.0168",\ +"-0.3230,-0.3113,-0.2996,-0.2723,-0.2332,-0.1590,-0.0184",\ +"-0.4012,-0.3895,-0.3738,-0.3465,-0.3074,-0.2332,-0.0965",\ +"-0.5379,-0.5262,-0.5105,-0.4832,-0.4480,-0.3699,-0.2332"); + } + + fall_constraint("SIG2SRAM_constraint_template") { + index_1("0.0040,0.0176,0.0344,0.0656,0.1120,0.2016,0.3800"); + index_2("0.0040,0.0176,0.0344,0.0656,0.1120,0.2016,0.3800"); + values ("-0.1785,-0.1707,-0.1551,-0.1277,-0.0887,-0.0184,0.1145",\ +"-0.1902,-0.1785,-0.1629,-0.1355,-0.1004,-0.0262,0.1027",\ +"-0.2059,-0.1941,-0.1785,-0.1512,-0.1160,-0.0418,0.0871",\ +"-0.2293,-0.2176,-0.2059,-0.1785,-0.1434,-0.0691,0.0598",\ +"-0.2684,-0.2566,-0.2449,-0.2176,-0.1824,-0.1082,0.0207",\ +"-0.3465,-0.3348,-0.3191,-0.2918,-0.2566,-0.1824,-0.0535",\ +"-0.4832,-0.4715,-0.4559,-0.4324,-0.3934,-0.3191,-0.1902"); + } + } + + + timing() { + timing_type : hold_rising; + related_pin : "B_BIST_CLK"; + when : "((B_BIST_WEN | B_BIST_REN)& B_BIST_MEN)" + sdf_cond : "B_BIST_RW_ACCESS" + + rise_constraint("SIG2SRAM_constraint_template") { + index_1("0.0040,0.0176,0.0344,0.0656,0.1120,0.2016,0.3800"); + index_2("0.0040,0.0176,0.0344,0.0656,0.1120,0.2016,0.3800"); + values ("0.3410,0.3293,0.3137,0.2863,0.2473,0.1730,0.0324",\ +"0.3488,0.3371,0.3215,0.2941,0.2590,0.1809,0.0480",\ +"0.3684,0.3527,0.3371,0.3098,0.2746,0.1965,0.0598",\ +"0.3918,0.3762,0.3645,0.3371,0.2980,0.2238,0.0871",\ +"0.4309,0.4152,0.4035,0.3762,0.3371,0.2629,0.1223",\ +"0.5051,0.4934,0.4777,0.4504,0.4113,0.3371,0.1965",\ +"0.6418,0.6262,0.6145,0.5871,0.5520,0.4738,0.3332"); + } + + fall_constraint("SIG2SRAM_constraint_template") { + index_1("0.0040,0.0176,0.0344,0.0656,0.1120,0.2016,0.3800"); + index_2("0.0040,0.0176,0.0344,0.0656,0.1120,0.2016,0.3800"); + values ("0.2824,0.2707,0.2551,0.2277,0.1926,0.1184,-0.0105",\ +"0.2902,0.2785,0.2668,0.2395,0.2043,0.1301,0.0012",\ +"0.3059,0.2941,0.2824,0.2551,0.2199,0.1457,0.0168",\ +"0.3332,0.3215,0.3059,0.2785,0.2434,0.1691,0.0402",\ +"0.3723,0.3605,0.3449,0.3176,0.2824,0.2121,0.0793",\ +"0.4465,0.4348,0.4230,0.3918,0.3566,0.2824,0.1535",\ +"0.5832,0.5715,0.5598,0.5324,0.4934,0.4191,0.2902"); + } + } +} +pin(B_BIST_WEN) { + direction : input ; + capacitance : 0.00341384 ; + max_transition : "0.38" ; + related_power_pin : VDD; + related_ground_pin : VSS; + internal_power() { + when : "B_BIST_MEN"; + rise_power("scalar"){ + values (0.0040); + } + fall_power("scalar"){ + values (0.0171); + } + } + internal_power() { + when : "!B_BIST_MEN"; + rise_power("scalar"){ + values (0.0050); + } + fall_power("scalar"){ + values (0.0218); + } + } + timing() { + timing_type : setup_rising; + related_pin : "B_BIST_CLK"; + when : "B_BIST_MEN" + sdf_cond : "B_BIST_MEN" + + rise_constraint("SIG2SRAM_constraint_template") { + index_1("0.0040,0.0176,0.0344,0.0656,0.1120,0.2016,0.3800"); + index_2("0.0040,0.0176,0.0344,0.0656,0.1120,0.2016,0.3800"); + values ("0.1418,0.1496,0.1652,0.1887,0.2316,0.3059,0.4465",\ +"0.1301,0.1379,0.1535,0.1809,0.2199,0.2941,0.4348",\ +"0.1145,0.1262,0.1379,0.1652,0.2043,0.2785,0.4191",\ +"0.0871,0.0949,0.1105,0.1379,0.1770,0.2512,0.3879",\ +"0.0480,0.0598,0.0754,0.0988,0.1379,0.2082,0.3527",\ +"-0.0262,-0.0145,0.0012,0.0246,0.0676,0.1379,0.2785",\ +"-0.1668,-0.1551,-0.1395,-0.1121,-0.0730,0.0012,0.1418"); + } + + fall_constraint("SIG2SRAM_constraint_template") { + index_1("0.0040,0.0176,0.0344,0.0656,0.1120,0.2016,0.3800"); + index_2("0.0040,0.0176,0.0344,0.0656,0.1120,0.2016,0.3800"); + values ("0.2082,0.2160,0.2316,0.2590,0.2941,0.3684,0.5012",\ +"0.1926,0.2043,0.2199,0.2473,0.2824,0.3566,0.4895",\ +"0.1770,0.1887,0.2043,0.2316,0.2668,0.3410,0.4777",\ +"0.1535,0.1652,0.1770,0.2043,0.2395,0.3137,0.4504",\ +"0.1145,0.1262,0.1379,0.1652,0.2043,0.2746,0.4113",\ +"0.0402,0.0520,0.0676,0.0910,0.1262,0.2004,0.3332",\ +"-0.0965,-0.0848,-0.0730,-0.0457,-0.0066,0.0637,0.2004"); + } + } + + + timing() { + timing_type : hold_rising; + related_pin : "B_BIST_CLK"; + when : "B_BIST_MEN" + sdf_cond : "B_BIST_MEN" + + rise_constraint("SIG2SRAM_constraint_template") { + index_1("0.0040,0.0176,0.0344,0.0656,0.1120,0.2016,0.3800"); + index_2("0.0040,0.0176,0.0344,0.0656,0.1120,0.2016,0.3800"); + values ("0.1770,0.1652,0.1496,0.1223,0.0793,0.0090,-0.1316",\ +"0.1848,0.1730,0.1574,0.1301,0.0910,0.0168,-0.1199",\ +"0.2004,0.1887,0.1770,0.1496,0.1066,0.0363,-0.1043",\ +"0.2277,0.2160,0.2004,0.1730,0.1340,0.0598,-0.0809",\ +"0.2668,0.2551,0.2395,0.2121,0.1730,0.0988,-0.0418",\ +"0.3410,0.3293,0.3137,0.2863,0.2434,0.1730,0.0324",\ +"0.4816,0.4699,0.4543,0.4230,0.3801,0.3098,0.1730"); + } + + fall_constraint("SIG2SRAM_constraint_template") { + index_1("0.0040,0.0176,0.0344,0.0656,0.1120,0.2016,0.3800"); + index_2("0.0040,0.0176,0.0344,0.0656,0.1120,0.2016,0.3800"); + values ("0.1613,0.1496,0.1379,0.1066,0.0715,0.0012,-0.1355",\ +"0.1730,0.1613,0.1457,0.1184,0.0832,0.0129,-0.1238",\ +"0.1887,0.1770,0.1613,0.1340,0.0988,0.0246,-0.1121",\ +"0.2121,0.2043,0.1887,0.1613,0.1223,0.0520,-0.0848",\ +"0.2512,0.2434,0.2277,0.2004,0.1613,0.0910,-0.0457",\ +"0.3254,0.3176,0.3020,0.2746,0.2355,0.1652,0.0324",\ +"0.4660,0.4543,0.4387,0.4113,0.3723,0.3020,0.1691"); + } + } + } +pin(B_BIST_REN) { + direction : input ; + capacitance : 0.00390661 ; + max_transition : "0.38" ; + related_power_pin : VDD; + related_ground_pin : VSS; + internal_power() { + when : "B_BIST_MEN"; + rise_power("scalar"){ + values (0.0122); + } + fall_power("scalar"){ + values (0.0105); + } + } + internal_power() { + when : "!B_BIST_MEN"; + rise_power("scalar"){ + values (0.0181); + } + fall_power("scalar"){ + values (0.0202); + } + } + timing() { + timing_type : setup_rising; + related_pin : "B_BIST_CLK"; + when : "B_BIST_MEN" + sdf_cond : "B_BIST_MEN" + + rise_constraint("SIG2SRAM_constraint_template") { + index_1("0.0040,0.0176,0.0344,0.0656,0.1120,0.2016,0.3800"); + index_2("0.0040,0.0176,0.0344,0.0656,0.1120,0.2016,0.3800"); + values ("-0.0027,0.0090,0.0246,0.0520,0.0910,0.1613,0.3020",\ +"-0.0105,0.0012,0.0129,0.0363,0.0793,0.1535,0.2902",\ +"-0.0262,-0.0145,-0.0027,0.0246,0.0637,0.1379,0.2785",\ +"-0.0535,-0.0418,-0.0262,0.0012,0.0363,0.1105,0.2512",\ +"-0.0926,-0.0809,-0.0652,-0.0418,-0.0027,0.0715,0.2121",\ +"-0.1668,-0.1551,-0.1395,-0.1082,-0.0770,-0.0027,0.1379",\ +"-0.3035,-0.2918,-0.2762,-0.2488,-0.2137,-0.1434,-0.0027"); + } + + fall_constraint("SIG2SRAM_constraint_template") { + index_1("0.0040,0.0176,0.0344,0.0656,0.1120,0.2016,0.3800"); + index_2("0.0040,0.0176,0.0344,0.0656,0.1120,0.2016,0.3800"); + values ("0.0832,0.0949,0.1105,0.1379,0.1730,0.2473,0.3801",\ +"0.0754,0.0832,0.0988,0.1223,0.1613,0.2355,0.3684",\ +"0.0598,0.0676,0.0832,0.1066,0.1457,0.2121,0.3527",\ +"0.0324,0.0441,0.0598,0.0871,0.1223,0.1926,0.3293",\ +"-0.0066,0.0051,0.0168,0.0480,0.0832,0.1535,0.2902",\ +"-0.0809,-0.0691,-0.0574,-0.0301,0.0090,0.0832,0.2121",\ +"-0.2176,-0.2059,-0.1941,-0.1668,-0.1277,-0.0574,0.0793"); + } + } + + + timing() { + timing_type : hold_rising; + related_pin : "B_BIST_CLK"; + when : "B_BIST_MEN" + sdf_cond : "B_BIST_MEN" + + rise_constraint("SIG2SRAM_constraint_template") { + index_1("0.0040,0.0176,0.0344,0.0656,0.1120,0.2016,0.3800"); + index_2("0.0040,0.0176,0.0344,0.0656,0.1120,0.2016,0.3800"); + values ("0.1887,0.1770,0.1613,0.1340,0.0949,0.0207,-0.1160",\ +"0.1965,0.1848,0.1730,0.1457,0.1027,0.0324,-0.1082",\ +"0.2160,0.2004,0.1887,0.1613,0.1184,0.0480,-0.0926",\ +"0.2395,0.2277,0.2121,0.1848,0.1457,0.0715,-0.0652",\ +"0.2785,0.2668,0.2512,0.2238,0.1848,0.1105,-0.0262",\ +"0.3527,0.3410,0.3254,0.2980,0.2551,0.1848,0.0480",\ +"0.4934,0.4816,0.4660,0.4387,0.3957,0.3254,0.1887"); + } + + fall_constraint("SIG2SRAM_constraint_template") { + index_1("0.0040,0.0176,0.0344,0.0656,0.1120,0.2016,0.3800"); + index_2("0.0040,0.0176,0.0344,0.0656,0.1120,0.2016,0.3800"); + values ("0.1730,0.1613,0.1496,0.1184,0.0793,0.0129,-0.1238",\ +"0.1848,0.1730,0.1574,0.1301,0.0910,0.0207,-0.1121",\ +"0.2004,0.1887,0.1730,0.1457,0.1066,0.0363,-0.1004",\ +"0.2238,0.2121,0.2004,0.1691,0.1340,0.0598,-0.0730",\ +"0.2629,0.2512,0.2395,0.2121,0.1691,0.0988,-0.0340",\ +"0.3371,0.3254,0.3137,0.2863,0.2434,0.1730,0.0402",\ +"0.4777,0.4660,0.4504,0.4230,0.3840,0.3137,0.1809"); + } + } + } +pin(B_BIST_MEN) { + direction : input ; + capacitance : 0.00326046 ; + max_transition : "0.38" ; + related_power_pin : VDD; + related_ground_pin : VSS; + internal_power() { + rise_power("scalar"){ + values (0.2714); + } + fall_power("scalar"){ + values (0.0108); + } + } + timing() { + timing_type : setup_rising; + related_pin : "B_BIST_CLK"; + + rise_constraint("SIG2SRAM_constraint_template") { + index_1("0.0040,0.0176,0.0344,0.0656,0.1120,0.2016,0.3800"); + index_2("0.0040,0.0176,0.0344,0.0656,0.1120,0.2016,0.3800"); + values ("0.1418,0.1496,0.1652,0.1926,0.2316,0.3059,0.4465",\ +"0.1301,0.1379,0.1535,0.1809,0.2199,0.2941,0.4348",\ +"0.1145,0.1262,0.1418,0.1652,0.2043,0.2785,0.4191",\ +"0.0871,0.0949,0.1105,0.1379,0.1770,0.2512,0.3879",\ +"0.0480,0.0598,0.0754,0.0988,0.1379,0.2082,0.3488",\ +"-0.0262,-0.0145,0.0012,0.0285,0.0676,0.1379,0.2785",\ +"-0.1668,-0.1551,-0.1395,-0.1121,-0.0730,0.0012,0.1379"); + } + + fall_constraint("SIG2SRAM_constraint_template") { + index_1("0.0040,0.0176,0.0344,0.0656,0.1120,0.2016,0.3800"); + index_2("0.0040,0.0176,0.0344,0.0656,0.1120,0.2016,0.3800"); + values ("0.2082,0.2199,0.2316,0.2590,0.2980,0.3723,0.5051",\ +"0.1965,0.2082,0.2199,0.2473,0.2863,0.3605,0.4934",\ +"0.1809,0.1926,0.2043,0.2316,0.2707,0.3449,0.4777",\ +"0.1574,0.1691,0.1809,0.2082,0.2434,0.3176,0.4543",\ +"0.1145,0.1262,0.1418,0.1691,0.2043,0.2785,0.4113",\ +"0.0441,0.0559,0.0676,0.0949,0.1301,0.2004,0.3332",\ +"-0.0965,-0.0848,-0.0691,-0.0418,-0.0066,0.0676,0.2004"); + } + } + + + timing() { + timing_type : hold_rising; + related_pin : "B_BIST_CLK"; + + rise_constraint("SIG2SRAM_constraint_template") { + index_1("0.0040,0.0176,0.0344,0.0656,0.1120,0.2016,0.3800"); + index_2("0.0040,0.0176,0.0344,0.0656,0.1120,0.2016,0.3800"); + values ("0.1770,0.1652,0.1535,0.1262,0.0832,0.0129,-0.1277",\ +"0.1887,0.1770,0.1613,0.1340,0.0949,0.0207,-0.1199",\ +"0.2043,0.1926,0.1770,0.1496,0.1105,0.0363,-0.1043",\ +"0.2277,0.2160,0.2043,0.1770,0.1379,0.0598,-0.0770",\ +"0.2668,0.2551,0.2434,0.2160,0.1730,0.0988,-0.0379",\ +"0.3449,0.3332,0.3176,0.2902,0.2473,0.1730,0.0363",\ +"0.4816,0.4699,0.4543,0.4270,0.3840,0.3098,0.1770"); + } + + fall_constraint("SIG2SRAM_constraint_template") { + index_1("0.0040,0.0176,0.0344,0.0656,0.1120,0.2016,0.3800"); + index_2("0.0040,0.0176,0.0344,0.0656,0.1120,0.2016,0.3800"); + values ("0.1613,0.1496,0.1379,0.1105,0.0715,0.0012,-0.1355",\ +"0.1730,0.1613,0.1496,0.1184,0.0832,0.0129,-0.1238",\ +"0.1887,0.1770,0.1652,0.1340,0.0988,0.0285,-0.1121",\ +"0.2121,0.2043,0.1887,0.1613,0.1223,0.0520,-0.0848",\ +"0.2551,0.2434,0.2277,0.2004,0.1613,0.0910,-0.0418",\ +"0.3293,0.3176,0.3020,0.2746,0.2395,0.1652,0.0324",\ +"0.4660,0.4543,0.4426,0.4113,0.3762,0.3020,0.1691"); + } + } + } +bus(B_BIST_BM) { + bus_type : D_31_0; + direction : input ; + capacitance : 0.00290564 ; + max_transition : "0.38" ; + pin(B_BIST_BM[31:0]) { + related_power_pin : VDD; + related_ground_pin : VSS; + internal_power() { + when : "B_BIST_MEN"; + rise_power("scalar"){ + values (0.1809); + } + fall_power("scalar"){ + values (0.1563); + } + } + internal_power() { + when : "!B_BIST_MEN"; + rise_power("scalar"){ + values (0.1509); + } + fall_power("scalar"){ + values (0.1509); + } + } + } + timing() { + timing_type : setup_rising; + related_pin : "B_BIST_CLK"; + when : "(B_BIST_WEN & B_BIST_MEN)" + sdf_cond : "B_BIST_RW_ACCESS" + + rise_constraint("SIG2SRAM_constraint_template") { + index_1("0.0040,0.0176,0.0344,0.0656,0.1120,0.2016,0.3800"); + index_2("0.0040,0.0176,0.0344,0.0656,0.1120,0.2016,0.3800"); + values ("-0.2898,-0.2791,-0.2634,-0.2380,-0.1970,-0.1238,0.0110",\ +"-0.2937,-0.2829,-0.2673,-0.2419,-0.2009,-0.1277,0.0071",\ +"-0.2974,-0.2866,-0.2710,-0.2456,-0.2046,-0.1313,0.0034",\ +"-0.3006,-0.2898,-0.2742,-0.2488,-0.2078,-0.1346,0.0002",\ +"-0.3132,-0.3024,-0.2868,-0.2614,-0.2204,-0.1472,-0.0124",\ +"-0.3308,-0.3200,-0.3044,-0.2790,-0.2380,-0.1648,-0.0300",\ +"-0.3583,-0.3475,-0.3319,-0.3065,-0.2655,-0.1923,-0.0575"); + } + + fall_constraint("SIG2SRAM_constraint_template") { + index_1("0.0040,0.0176,0.0344,0.0656,0.1120,0.2016,0.3800"); + index_2("0.0040,0.0176,0.0344,0.0656,0.1120,0.2016,0.3800"); + values ("-0.2664,-0.2546,-0.2419,-0.2146,-0.1775,-0.1042,0.0237",\ +"-0.2702,-0.2585,-0.2458,-0.2185,-0.1814,-0.1081,0.0198",\ +"-0.2739,-0.2622,-0.2495,-0.2222,-0.1851,-0.1118,0.0161",\ +"-0.2771,-0.2654,-0.2527,-0.2254,-0.1883,-0.1150,0.0129",\ +"-0.2897,-0.2780,-0.2653,-0.2380,-0.2009,-0.1276,0.0003",\ +"-0.3073,-0.2956,-0.2829,-0.2556,-0.2185,-0.1452,-0.0173",\ +"-0.3349,-0.3231,-0.3104,-0.2831,-0.2460,-0.1727,-0.0448"); + } + } + + + timing() { + timing_type : hold_rising; + related_pin : "B_BIST_CLK"; + when : "(B_BIST_WEN & B_BIST_MEN)" + sdf_cond : "B_BIST_RW_ACCESS" + + rise_constraint("SIG2SRAM_constraint_template") { + index_1("0.0040,0.0176,0.0344,0.0656,0.1120,0.2016,0.3800"); + index_2("0.0040,0.0176,0.0344,0.0656,0.1120,0.2016,0.3800"); + values ("0.3958,0.3860,0.3704,0.3440,0.3069,0.2327,0.0979",\ +"0.3997,0.3899,0.3743,0.3479,0.3108,0.2366,0.1018",\ +"0.4033,0.3936,0.3780,0.3516,0.3145,0.2403,0.1055",\ +"0.4065,0.3968,0.3811,0.3548,0.3177,0.2435,0.1087",\ +"0.4192,0.4094,0.3938,0.3674,0.3303,0.2561,0.1213",\ +"0.4368,0.4270,0.4114,0.3850,0.3479,0.2737,0.1389",\ +"0.4643,0.4545,0.4389,0.4125,0.3754,0.3012,0.1664"); + } + + fall_constraint("SIG2SRAM_constraint_template") { + index_1("0.0040,0.0176,0.0344,0.0656,0.1120,0.2016,0.3800"); + index_2("0.0040,0.0176,0.0344,0.0656,0.1120,0.2016,0.3800"); + values ("0.3675,0.3567,0.3430,0.3157,0.2796,0.2073,0.0774",\ +"0.3713,0.3606,0.3469,0.3196,0.2834,0.2112,0.0813",\ +"0.3750,0.3643,0.3506,0.3233,0.2871,0.2149,0.0850",\ +"0.3782,0.3675,0.3538,0.3265,0.2903,0.2181,0.0882",\ +"0.3908,0.3801,0.3664,0.3391,0.3029,0.2307,0.1008",\ +"0.4084,0.3977,0.3840,0.3567,0.3206,0.2483,0.1184",\ +"0.4360,0.4252,0.4115,0.3842,0.3481,0.2758,0.1459"); + } + } +} + pin(B_BIST_CLK) { + direction : input; + capacitance : 0.00389386; + max_transition : "0.38"; + clock : "true" ; + pin_func_type : active_rising ; + + timing () { + timing_type : "min_pulse_width"; + related_pin : "B_BIST_CLK"; + rise_constraint("CLKTRAN_constraint_template") { + index_1("0.004,0.38"); + values("0.12,0.12"); + } + } + + related_power_pin : VDD; + related_ground_pin : VSS; + + internal_power() { + when : "!B_BIST_MEN & !B_BIST_WEN & !B_BIST_REN"; + rise_power("scalar"){ + values (0); + } + fall_power("scalar"){ + values (0); + } + } + internal_power() { + when : "!B_BIST_MEN & B_BIST_WEN & !B_BIST_REN"; + rise_power("scalar"){ + values (0.6783); + } + fall_power("scalar"){ + values (0); + } + } + internal_power() { + when : "B_BIST_MEN & B_BIST_WEN & !B_BIST_REN"; + rise_power("scalar"){ + values (41.2558); + } + fall_power("scalar"){ + values (0); + } + } + internal_power() { + when : "B_BIST_MEN & B_BIST_WEN & B_BIST_REN"; + rise_power("scalar"){ + values (46.5325); + } + fall_power("scalar"){ + values (0); + } + } + internal_power() { + when : "B_BIST_MEN & !B_BIST_WEN & B_BIST_REN"; + rise_power("scalar"){ + values (34.0312); + } + fall_power("scalar"){ + values (0); + } + } + internal_power() { + when : "!B_BIST_MEN & !B_BIST_WEN & B_BIST_REN"; + rise_power("scalar"){ + values (0.4087); + } + fall_power("scalar"){ + values (0); + } + } + internal_power() { + when : "!B_BIST_MEN & B_BIST_WEN & B_BIST_REN"; + rise_power("scalar"){ + values (1.3353); + } + fall_power("scalar"){ + values (0); + } + } + internal_power() { + when : "B_BIST_MEN & !B_BIST_WEN & !B_BIST_REN"; + rise_power("scalar"){ + values (0); + } + fall_power("scalar"){ + values (0); + } + } + } + bus(B_BIST_DIN) { + bus_type : D_31_0; + direction : input ; + capacitance : 0.00417898 ; + memory_write() { + address : B_BIST_ADDR ; + clocked_on : B_BIST_CLK; + } + + max_transition : "0.38" ; + pin(B_BIST_DIN[31:0]) { + related_power_pin : VDD; + related_ground_pin : VSS; + internal_power() { + when : "B_BIST_MEN"; + rise_power("scalar"){ + values (0.1809); + } + fall_power("scalar"){ + values (0.1563); + } + } + internal_power() { + when : "!B_BIST_MEN"; + rise_power("scalar"){ + values (0.1509); + } + fall_power("scalar"){ + values (0.1509); + } + } + } + timing() { + timing_type : setup_rising; + related_pin : "B_BIST_CLK"; + when : "(B_BIST_WEN & B_BIST_MEN)"; + sdf_cond : "B_BIST_W_ACCESS"; + + rise_constraint("SIG2SRAM_constraint_template") { + index_1("0.0040,0.0176,0.0344,0.0656,0.1120,0.2016,0.3800"); + index_2("0.0040,0.0176,0.0344,0.0656,0.1120,0.2016,0.3800"); + values ("-0.2898,-0.2791,-0.2634,-0.2380,-0.1970,-0.1238,0.0110",\ +"-0.2937,-0.2829,-0.2673,-0.2419,-0.2009,-0.1277,0.0071",\ +"-0.2974,-0.2866,-0.2710,-0.2456,-0.2046,-0.1313,0.0034",\ +"-0.3006,-0.2898,-0.2742,-0.2488,-0.2078,-0.1346,0.0002",\ +"-0.3132,-0.3024,-0.2868,-0.2614,-0.2204,-0.1472,-0.0124",\ +"-0.3308,-0.3200,-0.3044,-0.2790,-0.2380,-0.1648,-0.0300",\ +"-0.3583,-0.3475,-0.3319,-0.3065,-0.2655,-0.1923,-0.0575"); + } + + fall_constraint("SIG2SRAM_constraint_template") { + index_1("0.0040,0.0176,0.0344,0.0656,0.1120,0.2016,0.3800"); + index_2("0.0040,0.0176,0.0344,0.0656,0.1120,0.2016,0.3800"); + values ("-0.2664,-0.2546,-0.2419,-0.2146,-0.1775,-0.1042,0.0237",\ +"-0.2702,-0.2585,-0.2458,-0.2185,-0.1814,-0.1081,0.0198",\ +"-0.2739,-0.2622,-0.2495,-0.2222,-0.1851,-0.1118,0.0161",\ +"-0.2771,-0.2654,-0.2527,-0.2254,-0.1883,-0.1150,0.0129",\ +"-0.2897,-0.2780,-0.2653,-0.2380,-0.2009,-0.1276,0.0003",\ +"-0.3073,-0.2956,-0.2829,-0.2556,-0.2185,-0.1452,-0.0173",\ +"-0.3349,-0.3231,-0.3104,-0.2831,-0.2460,-0.1727,-0.0448"); + } + } + + timing() { + timing_type : hold_rising; + related_pin : "B_BIST_CLK"; + when : "(B_BIST_WEN & B_BIST_MEN)"; + sdf_cond : "B_BIST_W_ACCESS"; + + rise_constraint("SIG2SRAM_constraint_template") { + index_1("0.0040,0.0176,0.0344,0.0656,0.1120,0.2016,0.3800"); + index_2("0.0040,0.0176,0.0344,0.0656,0.1120,0.2016,0.3800"); + values ("0.3958,0.3860,0.3704,0.3440,0.3069,0.2327,0.0979",\ +"0.3997,0.3899,0.3743,0.3479,0.3108,0.2366,0.1018",\ +"0.4033,0.3936,0.3780,0.3516,0.3145,0.2403,0.1055",\ +"0.4065,0.3968,0.3811,0.3548,0.3177,0.2435,0.1087",\ +"0.4192,0.4094,0.3938,0.3674,0.3303,0.2561,0.1213",\ +"0.4368,0.4270,0.4114,0.3850,0.3479,0.2737,0.1389",\ +"0.4643,0.4545,0.4389,0.4125,0.3754,0.3012,0.1664"); + } + + fall_constraint("SIG2SRAM_constraint_template") { + index_1("0.0040,0.0176,0.0344,0.0656,0.1120,0.2016,0.3800"); + index_2("0.0040,0.0176,0.0344,0.0656,0.1120,0.2016,0.3800"); + values ("0.3675,0.3567,0.3430,0.3157,0.2796,0.2073,0.0774",\ +"0.3713,0.3606,0.3469,0.3196,0.2834,0.2112,0.0813",\ +"0.3750,0.3643,0.3506,0.3233,0.2871,0.2149,0.0850",\ +"0.3782,0.3675,0.3538,0.3265,0.2903,0.2181,0.0882",\ +"0.3908,0.3801,0.3664,0.3391,0.3029,0.2307,0.1008",\ +"0.4084,0.3977,0.3840,0.3567,0.3206,0.2483,0.1184",\ +"0.4360,0.4252,0.4115,0.3842,0.3481,0.2758,0.1459"); + } + } + } + +bus(B_DOUT) { + + bus_type : D_31_0; + direction : output ; + capacitance : 0 ; + max_capacitance : 0.064 ; + memory_read() { + address : B_ADDR ; + } + pin(B_DOUT[31:0]) { + related_power_pin : VDD; + related_ground_pin : VSS; + internal_power() { + rise_power("scalar") { + values (0); + } + fall_power("scalar") { + values (0); + } + } + } + timing() { + related_pin : "B_CLK"; + timing_type : rising_edge ; + timing_sense : non_unate ; + + cell_rise(SIG2SRAM_delay_template) { + index_1("0.0040,0.0176,0.0344,0.0656,0.1120,0.2016,0.3800"); + index_2("0.0008,0.0014,0.0051,0.0100,0.0339,0.0640"); + values ("1.9084,1.9094,1.9142,1.9197,1.9406,1.9641",\ +"1.9143,1.9153,1.9202,1.9257,1.9466,1.9701",\ +"1.9171,1.9181,1.9229,1.9284,1.9493,1.9728",\ +"1.9213,1.9223,1.9271,1.9326,1.9535,1.9770",\ +"1.9329,1.9339,1.9387,1.9442,1.9652,1.9887",\ +"1.9520,1.9530,1.9578,1.9634,1.9843,2.0078",\ +"1.9784,1.9794,1.9842,1.9897,2.0107,2.0342"); + } + cell_fall(SIG2SRAM_delay_template) { + index_1("0.0040,0.0176,0.0344,0.0656,0.1120,0.2016,0.3800"); + index_2("0.0008,0.0014,0.0051,0.0100,0.0339,0.0640"); + values ("1.8741,1.8749,1.8790,1.8835,1.9006,1.9173",\ +"1.8800,1.8809,1.8849,1.8895,1.9066,1.9233",\ +"1.8828,1.8836,1.8877,1.8922,1.9093,1.9260",\ +"1.8870,1.8879,1.8919,1.8964,1.9135,1.9303",\ +"1.8986,1.8995,1.9035,1.9081,1.9251,1.9419",\ +"1.9177,1.9186,1.9226,1.9272,1.9443,1.9610",\ +"1.9441,1.9450,1.9490,1.9536,1.9706,1.9874"); + } + + rise_transition(SRAM_load_template) { + index_1("0.0008,0.0014,0.0051,0.0100,0.0339,0.0640"); + values ("0.0206,0.0210,0.0265,0.0323,0.0606,0.0955"); + } + fall_transition(SRAM_load_template) { + index_1("0.0008,0.0014,0.0051,0.0100,0.0339,0.0640"); + values ("0.0170,0.0177,0.0222,0.0270,0.0451,0.0644"); + } + } +} +cell_leakage_power : 451.7069; +} +} diff --git a/flow/platforms/ihp-sg13g2/lib/RM_IHPSG13_2P_256x32_c2_bm_bist_slow_1p08V_125C.lib b/flow/platforms/ihp-sg13g2/lib/RM_IHPSG13_2P_256x32_c2_bm_bist_slow_1p08V_125C.lib new file mode 100644 index 0000000000..819459cad5 --- /dev/null +++ b/flow/platforms/ihp-sg13g2/lib/RM_IHPSG13_2P_256x32_c2_bm_bist_slow_1p08V_125C.lib @@ -0,0 +1,2874 @@ +/* ------------------------------------------------------*/ +/**/ +/* Copyright 2025 IHP PDK Authors*/ +/**/ +/* Licensed under the Apache License, Version 2.0 (the "License");*/ +/* you may not use this file except in compliance with the License.*/ +/* You may obtain a copy of the License at*/ +/* */ +/* https://www.apache.org/licenses/LICENSE-2.0*/ +/* */ +/* Unless required by applicable law or agreed to in writing, software*/ +/* distributed under the License is distributed on an "AS IS" BASIS,*/ +/* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.*/ +/* See the License for the specific language governing permissions and*/ +/* limitations under the License.*/ +/* */ +/* Generated on Wed Aug 27 13:14:35 2025 */ +/* */ +/* ------------------------------------------------------ */ +library(RM_IHPSG13_2P_256x32_c2_bm_bist_slow_1p08V_125C) { + technology (cmos) ; + delay_model : table_lookup ; + define ("add_pg_pin_to_lib", "library", "boolean"); + add_pg_pin_to_lib : true; + voltage_map ( VDD, 1.08); + voltage_map ( VDDARRAY, 1.08); + voltage_map ( VSS, 0.000000 ); + + date : "Wed Aug 27 13:14:35 2025" ; + comment : "IHP Microelectronics GmbH, 2023" ; + revision : 1.0.0 ; + simulation : true ; + nom_process : 1 ; + nom_temperature : 125 ; + nom_voltage : 1.08 ; + + operating_conditions("slow_1p08V_125C"){ + process : 1 ; + temperature : 125 ; + voltage : 1.08 ; + tree_type : "balanced_tree" ; + } + + default_operating_conditions : slow_1p08V_125C ; + default_max_transition : 1.0 ; + default_fanout_load : 1.0 ; + default_inout_pin_cap : 0.0 ; + default_input_pin_cap : 0.0 ; + default_output_pin_cap : 0.0 ; + default_cell_leakage_power : 0.0 ; + default_leakage_power_density : 0.0 ; + + slew_lower_threshold_pct_rise : 30 ; + slew_upper_threshold_pct_rise : 70 ; + input_threshold_pct_fall : 50 ; + output_threshold_pct_fall : 50 ; + input_threshold_pct_rise : 50 ; + output_threshold_pct_rise : 50 ; + slew_lower_threshold_pct_fall : 30 ; + slew_upper_threshold_pct_fall : 70 ; + slew_derate_from_library : 0.5; + k_volt_cell_leakage_power : 0.0 ; + k_temp_cell_leakage_power : 0.0 ; + k_process_cell_leakage_power : 0.0 ; + k_volt_internal_power : 0.0 ; + k_temp_internal_power : 0.0 ; + k_process_internal_power : 0.0 ; + + capacitive_load_unit (1,pf) ; + voltage_unit : "1V" ; + current_unit : "1uA" ; + time_unit : "1ns" ; + leakage_power_unit : "1nW" ; + pulling_resistance_unit : "1kohm"; + /* + ------------------------------------------------------------------------------------------ + implicit units overview: + cell_area unit : "um" + internal_power unit : "1e-12 * J/toggle = 1 * uW/MHz" + (capacitive_load_unit * voltage_unit^2) per toggle event + ------------------------------------------------------------------------------------------ + */ + library_features(report_delay_calculation); + define_cell_area (pad_drivers,pad_driver_sites) ; + + lu_table_template(CLKTRAN_constraint_template) { + variable_1 : constrained_pin_transition; + index_1 ( "0.010, 0.050, 0.200, 0.400, 1.000" ); + } + lu_table_template(SRAM_load_template) { + variable_1 : total_output_net_capacitance; + index_1 ( "0.0008,0.0014,0.0051,0.0100,0.0339,0.0640" ); + } + lu_table_template(SIG2SRAM_constraint_template) { + variable_1 : related_pin_transition; + variable_2 : constrained_pin_transition; + index_1 ( "0.0080,0.0288,0.0616,0.1072,0.1920,0.3496,0.5952" ); + index_2 ( "0.0080,0.0288,0.0616,0.1072,0.1920,0.3496,0.5952" ); + } + + lu_table_template(SIG2SRAM_delay_template) { + variable_1 : input_net_transition; + variable_2 : total_output_net_capacitance; + index_1 ( "0.0080,0.0288,0.0616,0.1072,0.1920,0.3496,0.5952" ); + index_2 ( "0.0008,0.0014,0.0051,0.0100,0.0339,0.0640" ); + } + + type (D_31_0) { + base_type : array; + data_type : bit; + bit_width : 32; + bit_from : 31; + bit_to : 0; + downto : true; + } + + type (A_7_0) { + base_type : array; + data_type : bit; + bit_width : 8; + bit_from : 7; + bit_to : 0; + downto : true; + } + +cell(RM_IHPSG13_2P_256x32_c2_bm_bist) { +pg_pin (VDD) { + pg_type : primary_power; + voltage_name : VDD; +} +pg_pin (VDDARRAY) { + pg_type : primary_power; + voltage_name : VDDARRAY; +} +pg_pin (VSS) { + pg_type : primary_ground; + voltage_name : VSS; +} + +memory() { + type : ram; + address_width : 8; + word_width : 32; +} + +interface_timing : false; +bus_naming_style : "%s[%d]" ; +area : 96266.6251 ; + + pin(A_DLY) { + direction : input ; + capacitance : 0.00387999 ; + max_transition : "1" ; + related_power_pin : VDD; + related_ground_pin : VSS; + internal_power() { + rise_power("scalar") { + values (0); + } + fall_power("scalar") { + values (0); + } + } + } + +bus(A_ADDR) { + bus_type : A_7_0; + direction : input ; + capacitance : 0.0129586 ; + pin(A_ADDR[0]) { + capacitance : 0.0058687 ; + } + pin(A_ADDR[1]) { + capacitance : 0.00807137 ; + } + pin(A_ADDR[2]) { + capacitance : 0.0112051 ; + } + pin(A_ADDR[3]) { + capacitance : 0.00709524 ; + } + pin(A_ADDR[4]) { + capacitance : 0.00648778 ; + } + pin(A_ADDR[5]) { + capacitance : 0.011209 ; + } + pin(A_ADDR[6]) { + capacitance : 0.0140441 ; + } + max_transition : "0.5952" ; + pin(A_ADDR[7:0]) { + related_power_pin : VDD; + related_ground_pin : VSS; + internal_power() { + when : "A_MEN"; + rise_power("scalar"){ + values (0.0097); + } + fall_power("scalar"){ + values (0.0074); + } + } + internal_power() { + when : "!A_MEN"; + rise_power("scalar"){ + values (0.0163); + } + fall_power("scalar"){ + values (0.0021); + } + } + } + timing() { + timing_type : setup_rising; + related_pin : "A_CLK"; + when : "((A_WEN | A_REN)& A_MEN)" + sdf_cond : "A_RW_ACCESS" + + rise_constraint("SIG2SRAM_constraint_template") { + index_1("0.0080,0.0288,0.0616,0.1072,0.1920,0.3496,0.5952"); + index_2("0.0080,0.0288,0.0616,0.1072,0.1920,0.3496,0.5952"); + values ("-0.7371,-0.7176,-0.6863,-0.6434,-0.5652,-0.4168,-0.1980",\ +"-0.7566,-0.7371,-0.7059,-0.6629,-0.5848,-0.4363,-0.2137",\ +"-0.7879,-0.7645,-0.7332,-0.6902,-0.6121,-0.4637,-0.2449",\ +"-0.8309,-0.8074,-0.7762,-0.7332,-0.6551,-0.5066,-0.2879",\ +"-0.9051,-0.8895,-0.8543,-0.8113,-0.7332,-0.5887,-0.3660",\ +"-1.0418,-1.0262,-0.9949,-0.9480,-0.8699,-0.7293,-0.5027",\ +"-1.2684,-1.2449,-1.2176,-1.1707,-1.0965,-0.9480,-0.7293"); + } + + fall_constraint("SIG2SRAM_constraint_template") { + index_1("0.0080,0.0288,0.0616,0.1072,0.1920,0.3496,0.5952"); + index_2("0.0080,0.0288,0.0616,0.1072,0.1920,0.3496,0.5952"); + values ("-0.5926,-0.5730,-0.5418,-0.4988,-0.4246,-0.2879,-0.0730",\ +"-0.6121,-0.5926,-0.5613,-0.5223,-0.4441,-0.3074,-0.0887",\ +"-0.6395,-0.6199,-0.5926,-0.5496,-0.4715,-0.3348,-0.1160",\ +"-0.6863,-0.6668,-0.6355,-0.5965,-0.5184,-0.3777,-0.1590",\ +"-0.7605,-0.7410,-0.7137,-0.6746,-0.5926,-0.4559,-0.2410",\ +"-0.9012,-0.8816,-0.8504,-0.8113,-0.7332,-0.5926,-0.3895",\ +"-1.1238,-1.1043,-1.0769,-1.0379,-0.9559,-0.8191,-0.6004"); + } + } + + + timing() { + timing_type : hold_rising; + related_pin : "A_CLK"; + when : "((A_WEN | A_REN)& A_MEN)" + sdf_cond : "A_RW_ACCESS" + + rise_constraint("SIG2SRAM_constraint_template") { + index_1("0.0080,0.0288,0.0616,0.1072,0.1920,0.3496,0.5952"); + index_2("0.0080,0.0288,0.0616,0.1072,0.1920,0.3496,0.5952"); + values ("0.8488,0.8293,0.7980,0.7551,0.6730,0.5285,0.3059",\ +"0.8684,0.8488,0.8176,0.7746,0.6926,0.5480,0.3254",\ +"0.8996,0.8801,0.8449,0.8020,0.7238,0.5754,0.3527",\ +"0.9426,0.9191,0.8918,0.8488,0.7668,0.6223,0.3996",\ +"1.0168,1.0012,0.9699,0.9230,0.8449,0.7004,0.4777",\ +"1.1574,1.1379,1.1105,1.0598,0.9816,0.8371,0.6184",\ +"1.3801,1.3605,1.3254,1.2980,1.2043,1.0637,0.8371"); + } + + fall_constraint("SIG2SRAM_constraint_template") { + index_1("0.0080,0.0288,0.0616,0.1072,0.1920,0.3496,0.5952"); + index_2("0.0080,0.0288,0.0616,0.1072,0.1920,0.3496,0.5952"); + values ("0.6965,0.6770,0.6496,0.6066,0.5246,0.3918,0.1730",\ +"0.7160,0.6965,0.6652,0.6262,0.5441,0.4113,0.1965",\ +"0.7473,0.7277,0.6965,0.6535,0.5754,0.4426,0.2238",\ +"0.7863,0.7707,0.7395,0.7004,0.6223,0.4855,0.2629",\ +"0.8684,0.8449,0.8176,0.7785,0.7004,0.5637,0.3449",\ +"1.0051,0.9855,0.9855,0.9113,0.8332,0.7004,0.4895",\ +"1.2277,1.2082,1.1809,1.1379,1.0598,0.9230,0.7004"); + } + } +} +pin(A_WEN) { + direction : input ; + capacitance : 0.00313551 ; + max_transition : "0.5952" ; + related_power_pin : VDD; + related_ground_pin : VSS; + internal_power() { + when : "A_MEN"; + rise_power("scalar"){ + values (0.0036); + } + fall_power("scalar"){ + values (0.0005); + } + } + internal_power() { + when : "!A_MEN"; + rise_power("scalar"){ + values (0.0052); + } + fall_power("scalar"){ + values (0.0001); + } + } + timing() { + timing_type : setup_rising; + related_pin : "A_CLK"; + when : "A_MEN" + sdf_cond : "A_MEN" + + rise_constraint("SIG2SRAM_constraint_template") { + index_1("0.0080,0.0288,0.0616,0.1072,0.1920,0.3496,0.5952"); + index_2("0.0080,0.0288,0.0616,0.1072,0.1920,0.3496,0.5952"); + values ("0.3137,0.3332,0.3605,0.4035,0.4816,0.6223,0.8488",\ +"0.2980,0.3176,0.3410,0.3840,0.4660,0.6027,0.8293",\ +"0.2629,0.2824,0.3098,0.3527,0.4348,0.5754,0.7980",\ +"0.2199,0.2395,0.2668,0.3098,0.3918,0.5324,0.7590",\ +"0.1418,0.1613,0.1887,0.2316,0.3137,0.4348,0.6730",\ +"0.0012,0.0207,0.0520,0.0910,0.1730,0.3098,0.5285",\ +"-0.2215,-0.2020,-0.1746,-0.1277,-0.0496,0.0910,0.3098"); + } + + fall_constraint("SIG2SRAM_constraint_template") { + index_1("0.0080,0.0288,0.0616,0.1072,0.1920,0.3496,0.5952"); + index_2("0.0080,0.0288,0.0616,0.1072,0.1920,0.3496,0.5952"); + values ("0.4504,0.4699,0.4973,0.5324,0.6027,0.7355,0.9699",\ +"0.4309,0.4504,0.4777,0.5129,0.5910,0.7160,0.9504",\ +"0.3996,0.4191,0.4465,0.4816,0.5520,0.6848,0.9191",\ +"0.3605,0.3762,0.4035,0.4387,0.5168,0.6418,0.8723",\ +"0.2785,0.2980,0.3215,0.3605,0.4348,0.5637,0.7980",\ +"0.1379,0.1574,0.1809,0.2199,0.2980,0.4309,0.6457",\ +"-0.0809,-0.0613,-0.0340,0.0051,0.0832,0.2160,0.4191"); + } + } + + + timing() { + timing_type : hold_rising; + related_pin : "A_CLK"; + when : "A_MEN" + sdf_cond : "A_MEN" + + rise_constraint("SIG2SRAM_constraint_template") { + index_1("0.0080,0.0288,0.0616,0.1072,0.1920,0.3496,0.5952"); + index_2("0.0080,0.0288,0.0616,0.1072,0.1920,0.3496,0.5952"); + values ("0.3723,0.3527,0.3215,0.2785,0.1965,0.0559,-0.1668",\ +"0.3918,0.3723,0.3449,0.2980,0.2160,0.0754,-0.1473",\ +"0.4152,0.3996,0.3684,0.3254,0.2434,0.1066,-0.1199",\ +"0.4621,0.4465,0.4152,0.3723,0.2863,0.1496,-0.0730",\ +"0.5324,0.5207,0.4895,0.4465,0.3645,0.2199,0.0051",\ +"0.6770,0.6535,0.6301,0.5832,0.5090,0.3605,0.1418",\ +"0.9035,0.8879,0.8566,0.8137,0.7316,0.5871,0.3684"); + } + + fall_constraint("SIG2SRAM_constraint_template") { + index_1("0.0080,0.0288,0.0616,0.1072,0.1920,0.3496,0.5952"); + index_2("0.0080,0.0288,0.0616,0.1072,0.1920,0.3496,0.5952"); + values ("0.3762,0.3566,0.3293,0.2863,0.2043,0.0676,-0.1434",\ +"0.3957,0.3762,0.3488,0.3059,0.2238,0.0871,-0.1199",\ +"0.4230,0.4035,0.3723,0.3332,0.2512,0.1184,-0.0965",\ +"0.4660,0.4465,0.4191,0.3762,0.2941,0.1613,-0.0496",\ +"0.5324,0.5168,0.4973,0.4543,0.3723,0.2316,0.0285",\ +"0.6809,0.6613,0.6340,0.5910,0.5129,0.3645,0.1652",\ +"0.9113,0.8918,0.8605,0.8176,0.7395,0.5988,0.3879"); + } + } + } +pin(A_REN) { + direction : input ; + capacitance : 0.00381144 ; + max_transition : "0.5952" ; + related_power_pin : VDD; + related_ground_pin : VSS; + internal_power() { + when : "A_MEN"; + rise_power("scalar"){ + values (0.0041); + } + fall_power("scalar"){ + values (0.0013); + } + } + internal_power() { + when : "!A_MEN"; + rise_power("scalar"){ + values (0.0042); + } + fall_power("scalar"){ + values (0.0010); + } + } + timing() { + timing_type : setup_rising; + related_pin : "A_CLK"; + when : "A_MEN" + sdf_cond : "A_MEN" + + rise_constraint("SIG2SRAM_constraint_template") { + index_1("0.0080,0.0288,0.0616,0.1072,0.1920,0.3496,0.5952"); + index_2("0.0080,0.0288,0.0616,0.1072,0.1920,0.3496,0.5952"); + values ("-0.0770,-0.0574,-0.0262,0.0168,0.0949,0.2355,0.4582",\ +"-0.0965,-0.0770,-0.0457,-0.0027,0.0754,0.2160,0.4387",\ +"-0.1199,-0.1004,-0.0730,-0.0262,0.0520,0.1887,0.4113",\ +"-0.1590,-0.1434,-0.1160,-0.0730,0.0051,0.1457,0.3645",\ +"-0.2449,-0.2254,-0.1941,-0.1473,-0.0770,0.0676,0.2863",\ +"-0.3816,-0.3699,-0.3387,-0.2801,-0.2215,-0.0770,0.1457",\ +"-0.6121,-0.5926,-0.5613,-0.5145,-0.4363,-0.2996,-0.0730"); + } + + fall_constraint("SIG2SRAM_constraint_template") { + index_1("0.0080,0.0288,0.0616,0.1072,0.1920,0.3496,0.5952"); + index_2("0.0080,0.0288,0.0616,0.1072,0.1920,0.3496,0.5952"); + values ("0.1262,0.1457,0.1691,0.2121,0.2824,0.4191,0.6457",\ +"0.1105,0.1262,0.1496,0.1887,0.2629,0.3996,0.6262",\ +"0.0793,0.0949,0.1223,0.1652,0.2395,0.3684,0.5949",\ +"0.0363,0.0559,0.0793,0.1223,0.2004,0.3410,0.5520",\ +"-0.0457,-0.0262,0.0012,0.0441,0.1301,0.2629,0.4738",\ +"-0.1902,-0.1746,-0.1434,-0.1043,-0.0184,0.1223,0.3332",\ +"-0.4129,-0.3934,-0.3660,-0.3230,-0.2449,-0.1043,0.1105"); + } + } + + + timing() { + timing_type : hold_rising; + related_pin : "A_CLK"; + when : "A_MEN" + sdf_cond : "A_MEN" + + rise_constraint("SIG2SRAM_constraint_template") { + index_1("0.0080,0.0288,0.0616,0.1072,0.1920,0.3496,0.5952"); + index_2("0.0080,0.0288,0.0616,0.1072,0.1920,0.3496,0.5952"); + values ("0.4113,0.3918,0.3645,0.3176,0.2395,0.0988,-0.1238",\ +"0.4309,0.4113,0.3840,0.3371,0.2590,0.1184,-0.1043",\ +"0.4582,0.4387,0.4113,0.3645,0.2824,0.1457,-0.0770",\ +"0.5051,0.4816,0.4543,0.4074,0.3293,0.1887,-0.0340",\ +"0.5715,0.5598,0.5324,0.4895,0.4035,0.2512,0.0441",\ +"0.7043,0.7004,0.6730,0.6262,0.5402,0.3957,0.1809",\ +"0.9387,0.9270,0.8957,0.8527,0.7746,0.6262,0.4074"); + } + + fall_constraint("SIG2SRAM_constraint_template") { + index_1("0.0080,0.0288,0.0616,0.1072,0.1920,0.3496,0.5952"); + index_2("0.0080,0.0288,0.0616,0.1072,0.1920,0.3496,0.5952"); + values ("0.4152,0.3918,0.3645,0.3215,0.2395,0.1027,-0.1082",\ +"0.4309,0.4113,0.3801,0.3410,0.2590,0.1223,-0.0926",\ +"0.4582,0.4387,0.4074,0.3684,0.2863,0.1496,-0.0613",\ +"0.5012,0.4816,0.4504,0.4074,0.3293,0.1887,-0.0145",\ +"0.5715,0.5559,0.5285,0.4816,0.3996,0.2512,0.0598",\ +"0.7160,0.7004,0.6691,0.6262,0.5520,0.4035,0.2004",\ +"0.9387,0.9191,0.8957,0.8488,0.7707,0.6262,0.4113"); + } + } + } +pin(A_MEN) { + direction : input ; + capacitance : 0.00300347 ; + max_transition : "0.5952" ; + related_power_pin : VDD; + related_ground_pin : VSS; + internal_power() { + rise_power("scalar"){ + values (0.0300); + } + fall_power("scalar"){ + values (0.0003); + } + } + timing() { + timing_type : setup_rising; + related_pin : "A_CLK"; + + rise_constraint("SIG2SRAM_constraint_template") { + index_1("0.0080,0.0288,0.0616,0.1072,0.1920,0.3496,0.5952"); + index_2("0.0080,0.0288,0.0616,0.1072,0.1920,0.3496,0.5952"); + values ("0.3215,0.3449,0.3684,0.4113,0.4895,0.6301,0.8527",\ +"0.3059,0.3254,0.3527,0.3957,0.4738,0.6145,0.8371",\ +"0.2746,0.2941,0.3215,0.3645,0.4426,0.5871,0.8059",\ +"0.2316,0.2512,0.2785,0.3215,0.3996,0.5402,0.7629",\ +"0.1496,0.1730,0.1965,0.2395,0.3215,0.4660,0.6848",\ +"0.0090,0.0285,0.0598,0.1027,0.1809,0.3176,0.5402",\ +"-0.2098,-0.1902,-0.1668,-0.1199,-0.0418,0.0988,0.3137"); + } + + fall_constraint("SIG2SRAM_constraint_template") { + index_1("0.0080,0.0288,0.0616,0.1072,0.1920,0.3496,0.5952"); + index_2("0.0080,0.0288,0.0616,0.1072,0.1920,0.3496,0.5952"); + values ("0.4582,0.4738,0.5012,0.5363,0.6145,0.7395,0.9738",\ +"0.4387,0.4543,0.4816,0.5207,0.5910,0.7199,0.9582",\ +"0.4035,0.4230,0.4504,0.4855,0.5637,0.6887,0.9230",\ +"0.3645,0.3840,0.4074,0.4465,0.5285,0.6496,0.8840",\ +"0.2824,0.3020,0.3254,0.3645,0.4465,0.5715,0.7980",\ +"0.1418,0.1613,0.1887,0.2238,0.3020,0.4309,0.6496",\ +"-0.0770,-0.0574,-0.0301,0.0090,0.0910,0.2238,0.4191"); + } + } + + + timing() { + timing_type : hold_rising; + related_pin : "A_CLK"; + + rise_constraint("SIG2SRAM_constraint_template") { + index_1("0.0080,0.0288,0.0616,0.1072,0.1920,0.3496,0.5952"); + index_2("0.0080,0.0288,0.0616,0.1072,0.1920,0.3496,0.5952"); + values ("0.3762,0.3605,0.3293,0.2863,0.2043,0.0637,-0.1629",\ +"0.3996,0.3801,0.3488,0.3020,0.2238,0.0832,-0.1395",\ +"0.4230,0.4074,0.3723,0.3293,0.2473,0.1105,-0.1121",\ +"0.4621,0.4465,0.4152,0.3762,0.2941,0.1535,-0.0691",\ +"0.5441,0.5285,0.4973,0.4465,0.3684,0.2316,0.0090",\ +"0.6848,0.6652,0.6301,0.5910,0.5129,0.3605,0.1496",\ +"0.9074,0.8918,0.8566,0.8215,0.7395,0.5910,0.3723"); + } + + fall_constraint("SIG2SRAM_constraint_template") { + index_1("0.0080,0.0288,0.0616,0.1072,0.1920,0.3496,0.5952"); + index_2("0.0080,0.0288,0.0616,0.1072,0.1920,0.3496,0.5952"); + values ("0.3762,0.3605,0.3332,0.2863,0.2043,0.0715,-0.1395",\ +"0.3996,0.3762,0.3488,0.3059,0.2238,0.0910,-0.1199",\ +"0.4270,0.4035,0.3762,0.3332,0.2512,0.1184,-0.0965",\ +"0.4699,0.4504,0.4191,0.3762,0.2941,0.1613,-0.0496",\ +"0.5441,0.5285,0.4973,0.4543,0.3762,0.2355,0.0324",\ +"0.6770,0.6613,0.6340,0.5949,0.5207,0.3762,0.1652",\ +"0.9074,0.8918,0.8605,0.8176,0.7395,0.6027,0.3918"); + } + } + } +bus(A_BM) { + bus_type : D_31_0; + direction : input ; + capacitance : 0.00359979 ; + max_transition : "0.5952" ; + pin(A_BM[31:0]) { + related_power_pin : VDD; + related_ground_pin : VSS; + internal_power() { + when : "A_MEN"; + rise_power("scalar"){ + values (0.0936); + } + fall_power("scalar"){ + values (0.0304); + } + } + internal_power() { + when : "!A_MEN"; + rise_power("scalar"){ + values (0.0900); + } + fall_power("scalar"){ + values (0.0290); + } + } + } + timing() { + timing_type : setup_rising; + related_pin : "A_CLK"; + when : "(A_WEN & A_MEN)" + sdf_cond : "A_RW_ACCESS" + + rise_constraint("SIG2SRAM_constraint_template") { + index_1("0.0080,0.0288,0.0616,0.1072,0.1920,0.3496,0.5952"); + index_2("0.0080,0.0288,0.0616,0.1072,0.1920,0.3496,0.5952"); + values ("-0.9175,-0.8980,-0.8726,-0.8296,-0.7485,-0.6030,-0.3804",\ +"-0.9254,-0.9059,-0.8805,-0.8375,-0.7565,-0.6109,-0.3883",\ +"-0.9345,-0.9150,-0.8896,-0.8467,-0.7656,-0.6201,-0.3974",\ +"-0.9495,-0.9300,-0.9046,-0.8616,-0.7806,-0.6351,-0.4124",\ +"-0.9719,-0.9524,-0.9270,-0.8840,-0.8030,-0.6575,-0.4348",\ +"-1.0155,-0.9960,-0.9706,-0.9276,-0.8466,-0.7010,-0.4784",\ +"-1.0847,-1.0652,-1.0398,-0.9968,-0.9157,-0.7702,-0.5476"); + } + + fall_constraint("SIG2SRAM_constraint_template") { + index_1("0.0080,0.0288,0.0616,0.1072,0.1920,0.3496,0.5952"); + index_2("0.0080,0.0288,0.0616,0.1072,0.1920,0.3496,0.5952"); + values ("-0.8550,-0.8374,-0.8101,-0.7710,-0.6880,-0.5523,-0.3403",\ +"-0.8629,-0.8453,-0.8180,-0.7789,-0.6959,-0.5602,-0.3483",\ +"-0.8720,-0.8545,-0.8271,-0.7881,-0.7051,-0.5693,-0.3574",\ +"-0.8870,-0.8694,-0.8421,-0.8030,-0.7200,-0.5843,-0.3724",\ +"-0.9094,-0.8918,-0.8645,-0.8254,-0.7424,-0.6067,-0.3948",\ +"-0.9530,-0.9354,-0.9081,-0.8690,-0.7860,-0.6503,-0.4384",\ +"-1.0222,-1.0046,-0.9773,-0.9382,-0.8552,-0.7194,-0.5075"); + } + } + + + timing() { + timing_type : hold_rising; + related_pin : "A_CLK"; + when : "(A_WEN & A_MEN)" + sdf_cond : "A_RW_ACCESS" + + rise_constraint("SIG2SRAM_constraint_template") { + index_1("0.0080,0.0288,0.0616,0.1072,0.1920,0.3496,0.5952"); + index_2("0.0080,0.0288,0.0616,0.1072,0.1920,0.3496,0.5952"); + values ("1.0343,1.0128,0.9884,0.9454,0.8653,0.7188,0.4962",\ +"1.0422,1.0207,0.9963,0.9533,0.8733,0.7268,0.5041",\ +"1.0513,1.0299,1.0054,0.9625,0.8824,0.7359,0.5133",\ +"1.0663,1.0448,1.0204,0.9775,0.8974,0.7509,0.5282",\ +"1.0887,1.0672,1.0428,0.9998,0.9198,0.7733,0.5506",\ +"1.1323,1.1108,1.0864,1.0434,0.9634,0.8169,0.5942",\ +"1.2015,1.1800,1.1556,1.1126,1.0325,0.8861,0.6634"); + } + + fall_constraint("SIG2SRAM_constraint_template") { + index_1("0.0080,0.0288,0.0616,0.1072,0.1920,0.3496,0.5952"); + index_2("0.0080,0.0288,0.0616,0.1072,0.1920,0.3496,0.5952"); + values ("0.9601,0.9425,0.9151,0.8761,0.7931,0.6563,0.4454",\ +"0.9680,0.9504,0.9231,0.8840,0.8010,0.6643,0.4533",\ +"0.9771,0.9595,0.9322,0.8931,0.8101,0.6734,0.4625",\ +"0.9921,0.9745,0.9472,0.9081,0.8251,0.6884,0.4775",\ +"1.0145,0.9969,0.9696,0.9305,0.8475,0.7108,0.4998",\ +"1.0581,1.0405,1.0132,0.9741,0.8911,0.7544,0.5434",\ +"1.1273,1.1097,1.0823,1.0433,0.9603,0.8236,0.6126"); + } + } +} + pin(A_CLK) { + direction : input; + capacitance : 0.00378957; + max_transition : "0.5952"; + clock : "true" ; + pin_func_type : active_rising ; + + timing () { + timing_type : "min_pulse_width"; + related_pin : "A_CLK"; + rise_constraint("CLKTRAN_constraint_template") { + index_1("0.008,0.5952"); + values("0.4,0.4"); + } + } + + related_power_pin : VDD; + related_ground_pin : VSS; + + internal_power() { + when : "!A_MEN & !A_WEN & !A_REN"; + rise_power("scalar"){ + values (0); + } + fall_power("scalar"){ + values (0); + } + } + internal_power() { + when : "!A_MEN & A_WEN & !A_REN"; + rise_power("scalar"){ + values (0.4981); + } + fall_power("scalar"){ + values (0); + } + } + internal_power() { + when : "A_MEN & A_WEN & !A_REN"; + rise_power("scalar"){ + values (28.0075); + } + fall_power("scalar"){ + values (0); + } + } + internal_power() { + when : "A_MEN & A_WEN & A_REN"; + rise_power("scalar"){ + values (30.3621); + } + fall_power("scalar"){ + values (0); + } + } + internal_power() { + when : "A_MEN & !A_WEN & A_REN"; + rise_power("scalar"){ + values (21.9513); + } + fall_power("scalar"){ + values (0); + } + } + internal_power() { + when : "!A_MEN & !A_WEN & A_REN"; + rise_power("scalar"){ + values (0.3219); + } + fall_power("scalar"){ + values (0); + } + } + internal_power() { + when : "!A_MEN & A_WEN & A_REN"; + rise_power("scalar"){ + values (1.0771); + } + fall_power("scalar"){ + values (0); + } + } + internal_power() { + when : "A_MEN & !A_WEN & !A_REN"; + rise_power("scalar"){ + values (0); + } + fall_power("scalar"){ + values (0); + } + } + } + bus(A_DIN) { + bus_type : D_31_0; + direction : input ; + capacitance : 0.00502163 ; + memory_write() { + address : A_ADDR ; + clocked_on : A_CLK; + } + + max_transition : "0.5952" ; + pin(A_DIN[31:0]) { + related_power_pin : VDD; + related_ground_pin : VSS; + internal_power() { + when : "A_MEN"; + rise_power("scalar"){ + values (0.0936); + } + fall_power("scalar"){ + values (0.0304); + } + } + internal_power() { + when : "!A_MEN"; + rise_power("scalar"){ + values (0.0900); + } + fall_power("scalar"){ + values (0.0290); + } + } + } + timing() { + timing_type : setup_rising; + related_pin : "A_CLK"; + when : "(A_WEN & A_MEN)"; + sdf_cond : "A_W_ACCESS"; + + rise_constraint("SIG2SRAM_constraint_template") { + index_1("0.0080,0.0288,0.0616,0.1072,0.1920,0.3496,0.5952"); + index_2("0.0080,0.0288,0.0616,0.1072,0.1920,0.3496,0.5952"); + values ("-0.9175,-0.8980,-0.8726,-0.8296,-0.7485,-0.6030,-0.3804",\ +"-0.9254,-0.9059,-0.8805,-0.8375,-0.7565,-0.6109,-0.3883",\ +"-0.9345,-0.9150,-0.8896,-0.8467,-0.7656,-0.6201,-0.3974",\ +"-0.9495,-0.9300,-0.9046,-0.8616,-0.7806,-0.6351,-0.4124",\ +"-0.9719,-0.9524,-0.9270,-0.8840,-0.8030,-0.6575,-0.4348",\ +"-1.0155,-0.9960,-0.9706,-0.9276,-0.8466,-0.7010,-0.4784",\ +"-1.0847,-1.0652,-1.0398,-0.9968,-0.9157,-0.7702,-0.5476"); + } + + fall_constraint("SIG2SRAM_constraint_template") { + index_1("0.0080,0.0288,0.0616,0.1072,0.1920,0.3496,0.5952"); + index_2("0.0080,0.0288,0.0616,0.1072,0.1920,0.3496,0.5952"); + values ("-0.8550,-0.8374,-0.8101,-0.7710,-0.6880,-0.5523,-0.3403",\ +"-0.8629,-0.8453,-0.8180,-0.7789,-0.6959,-0.5602,-0.3483",\ +"-0.8720,-0.8545,-0.8271,-0.7881,-0.7051,-0.5693,-0.3574",\ +"-0.8870,-0.8694,-0.8421,-0.8030,-0.7200,-0.5843,-0.3724",\ +"-0.9094,-0.8918,-0.8645,-0.8254,-0.7424,-0.6067,-0.3948",\ +"-0.9530,-0.9354,-0.9081,-0.8690,-0.7860,-0.6503,-0.4384",\ +"-1.0222,-1.0046,-0.9773,-0.9382,-0.8552,-0.7194,-0.5075"); + } + } + + timing() { + timing_type : hold_rising; + related_pin : "A_CLK"; + when : "(A_WEN & A_MEN)"; + sdf_cond : "A_W_ACCESS"; + + rise_constraint("SIG2SRAM_constraint_template") { + index_1("0.0080,0.0288,0.0616,0.1072,0.1920,0.3496,0.5952"); + index_2("0.0080,0.0288,0.0616,0.1072,0.1920,0.3496,0.5952"); + values ("1.0343,1.0128,0.9884,0.9454,0.8653,0.7188,0.4962",\ +"1.0422,1.0207,0.9963,0.9533,0.8733,0.7268,0.5041",\ +"1.0513,1.0299,1.0054,0.9625,0.8824,0.7359,0.5133",\ +"1.0663,1.0448,1.0204,0.9775,0.8974,0.7509,0.5282",\ +"1.0887,1.0672,1.0428,0.9998,0.9198,0.7733,0.5506",\ +"1.1323,1.1108,1.0864,1.0434,0.9634,0.8169,0.5942",\ +"1.2015,1.1800,1.1556,1.1126,1.0325,0.8861,0.6634"); + } + + fall_constraint("SIG2SRAM_constraint_template") { + index_1("0.0080,0.0288,0.0616,0.1072,0.1920,0.3496,0.5952"); + index_2("0.0080,0.0288,0.0616,0.1072,0.1920,0.3496,0.5952"); + values ("0.9601,0.9425,0.9151,0.8761,0.7931,0.6563,0.4454",\ +"0.9680,0.9504,0.9231,0.8840,0.8010,0.6643,0.4533",\ +"0.9771,0.9595,0.9322,0.8931,0.8101,0.6734,0.4625",\ +"0.9921,0.9745,0.9472,0.9081,0.8251,0.6884,0.4775",\ +"1.0145,0.9969,0.9696,0.9305,0.8475,0.7108,0.4998",\ +"1.0581,1.0405,1.0132,0.9741,0.8911,0.7544,0.5434",\ +"1.1273,1.1097,1.0823,1.0433,0.9603,0.8236,0.6126"); + } + } + } + + pin(A_BIST_EN) { + direction : input ; + capacitance : 0.00387999 ; + max_transition : "1" ; + related_power_pin : VDD; + related_ground_pin : VSS; + internal_power() { + rise_power("scalar") { + values (0); + } + fall_power("scalar") { + values (0); + } + } + } + +bus(A_BIST_ADDR) { + bus_type : A_7_0; + direction : input ; + capacitance : 0.0129586 ; + pin(A_BIST_ADDR[0]) { + capacitance : 0.0058687 ; + } + pin(A_BIST_ADDR[1]) { + capacitance : 0.00807137 ; + } + pin(A_BIST_ADDR[2]) { + capacitance : 0.0112051 ; + } + pin(A_BIST_ADDR[3]) { + capacitance : 0.00709524 ; + } + pin(A_BIST_ADDR[4]) { + capacitance : 0.00648778 ; + } + pin(A_BIST_ADDR[5]) { + capacitance : 0.011209 ; + } + pin(A_BIST_ADDR[6]) { + capacitance : 0.0140441 ; + } + max_transition : "0.5952" ; + pin(A_BIST_ADDR[7:0]) { + related_power_pin : VDD; + related_ground_pin : VSS; + internal_power() { + when : "A_BIST_MEN"; + rise_power("scalar"){ + values (0.0097); + } + fall_power("scalar"){ + values (0.0074); + } + } + internal_power() { + when : "!A_BIST_MEN"; + rise_power("scalar"){ + values (0.0163); + } + fall_power("scalar"){ + values (0.0021); + } + } + } + timing() { + timing_type : setup_rising; + related_pin : "A_BIST_CLK"; + when : "((A_BIST_WEN | A_BIST_REN)& A_BIST_MEN)" + sdf_cond : "A_BIST_RW_ACCESS" + + rise_constraint("SIG2SRAM_constraint_template") { + index_1("0.0080,0.0288,0.0616,0.1072,0.1920,0.3496,0.5952"); + index_2("0.0080,0.0288,0.0616,0.1072,0.1920,0.3496,0.5952"); + values ("-0.7371,-0.7176,-0.6863,-0.6434,-0.5652,-0.4168,-0.1980",\ +"-0.7566,-0.7371,-0.7059,-0.6629,-0.5848,-0.4363,-0.2137",\ +"-0.7879,-0.7645,-0.7332,-0.6902,-0.6121,-0.4637,-0.2449",\ +"-0.8309,-0.8074,-0.7762,-0.7332,-0.6551,-0.5066,-0.2879",\ +"-0.9051,-0.8895,-0.8543,-0.8113,-0.7332,-0.5887,-0.3660",\ +"-1.0418,-1.0262,-0.9949,-0.9480,-0.8699,-0.7293,-0.5027",\ +"-1.2684,-1.2449,-1.2176,-1.1707,-1.0965,-0.9480,-0.7293"); + } + + fall_constraint("SIG2SRAM_constraint_template") { + index_1("0.0080,0.0288,0.0616,0.1072,0.1920,0.3496,0.5952"); + index_2("0.0080,0.0288,0.0616,0.1072,0.1920,0.3496,0.5952"); + values ("-0.5926,-0.5730,-0.5418,-0.4988,-0.4246,-0.2879,-0.0730",\ +"-0.6121,-0.5926,-0.5613,-0.5223,-0.4441,-0.3074,-0.0887",\ +"-0.6395,-0.6199,-0.5926,-0.5496,-0.4715,-0.3348,-0.1160",\ +"-0.6863,-0.6668,-0.6355,-0.5965,-0.5184,-0.3777,-0.1590",\ +"-0.7605,-0.7410,-0.7137,-0.6746,-0.5926,-0.4559,-0.2410",\ +"-0.9012,-0.8816,-0.8504,-0.8113,-0.7332,-0.5926,-0.3895",\ +"-1.1238,-1.1043,-1.0769,-1.0379,-0.9559,-0.8191,-0.6004"); + } + } + + + timing() { + timing_type : hold_rising; + related_pin : "A_BIST_CLK"; + when : "((A_BIST_WEN | A_BIST_REN)& A_BIST_MEN)" + sdf_cond : "A_BIST_RW_ACCESS" + + rise_constraint("SIG2SRAM_constraint_template") { + index_1("0.0080,0.0288,0.0616,0.1072,0.1920,0.3496,0.5952"); + index_2("0.0080,0.0288,0.0616,0.1072,0.1920,0.3496,0.5952"); + values ("0.8488,0.8293,0.7980,0.7551,0.6730,0.5285,0.3059",\ +"0.8684,0.8488,0.8176,0.7746,0.6926,0.5480,0.3254",\ +"0.8996,0.8801,0.8449,0.8020,0.7238,0.5754,0.3527",\ +"0.9426,0.9191,0.8918,0.8488,0.7668,0.6223,0.3996",\ +"1.0168,1.0012,0.9699,0.9230,0.8449,0.7004,0.4777",\ +"1.1574,1.1379,1.1105,1.0598,0.9816,0.8371,0.6184",\ +"1.3801,1.3605,1.3254,1.2980,1.2043,1.0637,0.8371"); + } + + fall_constraint("SIG2SRAM_constraint_template") { + index_1("0.0080,0.0288,0.0616,0.1072,0.1920,0.3496,0.5952"); + index_2("0.0080,0.0288,0.0616,0.1072,0.1920,0.3496,0.5952"); + values ("0.6965,0.6770,0.6496,0.6066,0.5246,0.3918,0.1730",\ +"0.7160,0.6965,0.6652,0.6262,0.5441,0.4113,0.1965",\ +"0.7473,0.7277,0.6965,0.6535,0.5754,0.4426,0.2238",\ +"0.7863,0.7707,0.7395,0.7004,0.6223,0.4855,0.2629",\ +"0.8684,0.8449,0.8176,0.7785,0.7004,0.5637,0.3449",\ +"1.0051,0.9855,0.9855,0.9113,0.8332,0.7004,0.4895",\ +"1.2277,1.2082,1.1809,1.1379,1.0598,0.9230,0.7004"); + } + } +} +pin(A_BIST_WEN) { + direction : input ; + capacitance : 0.00313551 ; + max_transition : "0.5952" ; + related_power_pin : VDD; + related_ground_pin : VSS; + internal_power() { + when : "A_BIST_MEN"; + rise_power("scalar"){ + values (0.0036); + } + fall_power("scalar"){ + values (0.0005); + } + } + internal_power() { + when : "!A_BIST_MEN"; + rise_power("scalar"){ + values (0.0052); + } + fall_power("scalar"){ + values (0.0001); + } + } + timing() { + timing_type : setup_rising; + related_pin : "A_BIST_CLK"; + when : "A_BIST_MEN" + sdf_cond : "A_BIST_MEN" + + rise_constraint("SIG2SRAM_constraint_template") { + index_1("0.0080,0.0288,0.0616,0.1072,0.1920,0.3496,0.5952"); + index_2("0.0080,0.0288,0.0616,0.1072,0.1920,0.3496,0.5952"); + values ("0.3137,0.3332,0.3605,0.4035,0.4816,0.6223,0.8488",\ +"0.2980,0.3176,0.3410,0.3840,0.4660,0.6027,0.8293",\ +"0.2629,0.2824,0.3098,0.3527,0.4348,0.5754,0.7980",\ +"0.2199,0.2395,0.2668,0.3098,0.3918,0.5324,0.7590",\ +"0.1418,0.1613,0.1887,0.2316,0.3137,0.4348,0.6730",\ +"0.0012,0.0207,0.0520,0.0910,0.1730,0.3098,0.5285",\ +"-0.2215,-0.2020,-0.1746,-0.1277,-0.0496,0.0910,0.3098"); + } + + fall_constraint("SIG2SRAM_constraint_template") { + index_1("0.0080,0.0288,0.0616,0.1072,0.1920,0.3496,0.5952"); + index_2("0.0080,0.0288,0.0616,0.1072,0.1920,0.3496,0.5952"); + values ("0.4504,0.4699,0.4973,0.5324,0.6027,0.7355,0.9699",\ +"0.4309,0.4504,0.4777,0.5129,0.5910,0.7160,0.9504",\ +"0.3996,0.4191,0.4465,0.4816,0.5520,0.6848,0.9191",\ +"0.3605,0.3762,0.4035,0.4387,0.5168,0.6418,0.8723",\ +"0.2785,0.2980,0.3215,0.3605,0.4348,0.5637,0.7980",\ +"0.1379,0.1574,0.1809,0.2199,0.2980,0.4309,0.6457",\ +"-0.0809,-0.0613,-0.0340,0.0051,0.0832,0.2160,0.4191"); + } + } + + + timing() { + timing_type : hold_rising; + related_pin : "A_BIST_CLK"; + when : "A_BIST_MEN" + sdf_cond : "A_BIST_MEN" + + rise_constraint("SIG2SRAM_constraint_template") { + index_1("0.0080,0.0288,0.0616,0.1072,0.1920,0.3496,0.5952"); + index_2("0.0080,0.0288,0.0616,0.1072,0.1920,0.3496,0.5952"); + values ("0.3723,0.3527,0.3215,0.2785,0.1965,0.0559,-0.1668",\ +"0.3918,0.3723,0.3449,0.2980,0.2160,0.0754,-0.1473",\ +"0.4152,0.3996,0.3684,0.3254,0.2434,0.1066,-0.1199",\ +"0.4621,0.4465,0.4152,0.3723,0.2863,0.1496,-0.0730",\ +"0.5324,0.5207,0.4895,0.4465,0.3645,0.2199,0.0051",\ +"0.6770,0.6535,0.6301,0.5832,0.5090,0.3605,0.1418",\ +"0.9035,0.8879,0.8566,0.8137,0.7316,0.5871,0.3684"); + } + + fall_constraint("SIG2SRAM_constraint_template") { + index_1("0.0080,0.0288,0.0616,0.1072,0.1920,0.3496,0.5952"); + index_2("0.0080,0.0288,0.0616,0.1072,0.1920,0.3496,0.5952"); + values ("0.3762,0.3566,0.3293,0.2863,0.2043,0.0676,-0.1434",\ +"0.3957,0.3762,0.3488,0.3059,0.2238,0.0871,-0.1199",\ +"0.4230,0.4035,0.3723,0.3332,0.2512,0.1184,-0.0965",\ +"0.4660,0.4465,0.4191,0.3762,0.2941,0.1613,-0.0496",\ +"0.5324,0.5168,0.4973,0.4543,0.3723,0.2316,0.0285",\ +"0.6809,0.6613,0.6340,0.5910,0.5129,0.3645,0.1652",\ +"0.9113,0.8918,0.8605,0.8176,0.7395,0.5988,0.3879"); + } + } + } +pin(A_BIST_REN) { + direction : input ; + capacitance : 0.00381144 ; + max_transition : "0.5952" ; + related_power_pin : VDD; + related_ground_pin : VSS; + internal_power() { + when : "A_BIST_MEN"; + rise_power("scalar"){ + values (0.0041); + } + fall_power("scalar"){ + values (0.0013); + } + } + internal_power() { + when : "!A_BIST_MEN"; + rise_power("scalar"){ + values (0.0042); + } + fall_power("scalar"){ + values (0.0010); + } + } + timing() { + timing_type : setup_rising; + related_pin : "A_BIST_CLK"; + when : "A_BIST_MEN" + sdf_cond : "A_BIST_MEN" + + rise_constraint("SIG2SRAM_constraint_template") { + index_1("0.0080,0.0288,0.0616,0.1072,0.1920,0.3496,0.5952"); + index_2("0.0080,0.0288,0.0616,0.1072,0.1920,0.3496,0.5952"); + values ("-0.0770,-0.0574,-0.0262,0.0168,0.0949,0.2355,0.4582",\ +"-0.0965,-0.0770,-0.0457,-0.0027,0.0754,0.2160,0.4387",\ +"-0.1199,-0.1004,-0.0730,-0.0262,0.0520,0.1887,0.4113",\ +"-0.1590,-0.1434,-0.1160,-0.0730,0.0051,0.1457,0.3645",\ +"-0.2449,-0.2254,-0.1941,-0.1473,-0.0770,0.0676,0.2863",\ +"-0.3816,-0.3699,-0.3387,-0.2801,-0.2215,-0.0770,0.1457",\ +"-0.6121,-0.5926,-0.5613,-0.5145,-0.4363,-0.2996,-0.0730"); + } + + fall_constraint("SIG2SRAM_constraint_template") { + index_1("0.0080,0.0288,0.0616,0.1072,0.1920,0.3496,0.5952"); + index_2("0.0080,0.0288,0.0616,0.1072,0.1920,0.3496,0.5952"); + values ("0.1262,0.1457,0.1691,0.2121,0.2824,0.4191,0.6457",\ +"0.1105,0.1262,0.1496,0.1887,0.2629,0.3996,0.6262",\ +"0.0793,0.0949,0.1223,0.1652,0.2395,0.3684,0.5949",\ +"0.0363,0.0559,0.0793,0.1223,0.2004,0.3410,0.5520",\ +"-0.0457,-0.0262,0.0012,0.0441,0.1301,0.2629,0.4738",\ +"-0.1902,-0.1746,-0.1434,-0.1043,-0.0184,0.1223,0.3332",\ +"-0.4129,-0.3934,-0.3660,-0.3230,-0.2449,-0.1043,0.1105"); + } + } + + + timing() { + timing_type : hold_rising; + related_pin : "A_BIST_CLK"; + when : "A_BIST_MEN" + sdf_cond : "A_BIST_MEN" + + rise_constraint("SIG2SRAM_constraint_template") { + index_1("0.0080,0.0288,0.0616,0.1072,0.1920,0.3496,0.5952"); + index_2("0.0080,0.0288,0.0616,0.1072,0.1920,0.3496,0.5952"); + values ("0.4113,0.3918,0.3645,0.3176,0.2395,0.0988,-0.1238",\ +"0.4309,0.4113,0.3840,0.3371,0.2590,0.1184,-0.1043",\ +"0.4582,0.4387,0.4113,0.3645,0.2824,0.1457,-0.0770",\ +"0.5051,0.4816,0.4543,0.4074,0.3293,0.1887,-0.0340",\ +"0.5715,0.5598,0.5324,0.4895,0.4035,0.2512,0.0441",\ +"0.7043,0.7004,0.6730,0.6262,0.5402,0.3957,0.1809",\ +"0.9387,0.9270,0.8957,0.8527,0.7746,0.6262,0.4074"); + } + + fall_constraint("SIG2SRAM_constraint_template") { + index_1("0.0080,0.0288,0.0616,0.1072,0.1920,0.3496,0.5952"); + index_2("0.0080,0.0288,0.0616,0.1072,0.1920,0.3496,0.5952"); + values ("0.4152,0.3918,0.3645,0.3215,0.2395,0.1027,-0.1082",\ +"0.4309,0.4113,0.3801,0.3410,0.2590,0.1223,-0.0926",\ +"0.4582,0.4387,0.4074,0.3684,0.2863,0.1496,-0.0613",\ +"0.5012,0.4816,0.4504,0.4074,0.3293,0.1887,-0.0145",\ +"0.5715,0.5559,0.5285,0.4816,0.3996,0.2512,0.0598",\ +"0.7160,0.7004,0.6691,0.6262,0.5520,0.4035,0.2004",\ +"0.9387,0.9191,0.8957,0.8488,0.7707,0.6262,0.4113"); + } + } + } +pin(A_BIST_MEN) { + direction : input ; + capacitance : 0.00300347 ; + max_transition : "0.5952" ; + related_power_pin : VDD; + related_ground_pin : VSS; + internal_power() { + rise_power("scalar"){ + values (0.0300); + } + fall_power("scalar"){ + values (0.0003); + } + } + timing() { + timing_type : setup_rising; + related_pin : "A_BIST_CLK"; + + rise_constraint("SIG2SRAM_constraint_template") { + index_1("0.0080,0.0288,0.0616,0.1072,0.1920,0.3496,0.5952"); + index_2("0.0080,0.0288,0.0616,0.1072,0.1920,0.3496,0.5952"); + values ("0.3215,0.3449,0.3684,0.4113,0.4895,0.6301,0.8527",\ +"0.3059,0.3254,0.3527,0.3957,0.4738,0.6145,0.8371",\ +"0.2746,0.2941,0.3215,0.3645,0.4426,0.5871,0.8059",\ +"0.2316,0.2512,0.2785,0.3215,0.3996,0.5402,0.7629",\ +"0.1496,0.1730,0.1965,0.2395,0.3215,0.4660,0.6848",\ +"0.0090,0.0285,0.0598,0.1027,0.1809,0.3176,0.5402",\ +"-0.2098,-0.1902,-0.1668,-0.1199,-0.0418,0.0988,0.3137"); + } + + fall_constraint("SIG2SRAM_constraint_template") { + index_1("0.0080,0.0288,0.0616,0.1072,0.1920,0.3496,0.5952"); + index_2("0.0080,0.0288,0.0616,0.1072,0.1920,0.3496,0.5952"); + values ("0.4582,0.4738,0.5012,0.5363,0.6145,0.7395,0.9738",\ +"0.4387,0.4543,0.4816,0.5207,0.5910,0.7199,0.9582",\ +"0.4035,0.4230,0.4504,0.4855,0.5637,0.6887,0.9230",\ +"0.3645,0.3840,0.4074,0.4465,0.5285,0.6496,0.8840",\ +"0.2824,0.3020,0.3254,0.3645,0.4465,0.5715,0.7980",\ +"0.1418,0.1613,0.1887,0.2238,0.3020,0.4309,0.6496",\ +"-0.0770,-0.0574,-0.0301,0.0090,0.0910,0.2238,0.4191"); + } + } + + + timing() { + timing_type : hold_rising; + related_pin : "A_BIST_CLK"; + + rise_constraint("SIG2SRAM_constraint_template") { + index_1("0.0080,0.0288,0.0616,0.1072,0.1920,0.3496,0.5952"); + index_2("0.0080,0.0288,0.0616,0.1072,0.1920,0.3496,0.5952"); + values ("0.3762,0.3605,0.3293,0.2863,0.2043,0.0637,-0.1629",\ +"0.3996,0.3801,0.3488,0.3020,0.2238,0.0832,-0.1395",\ +"0.4230,0.4074,0.3723,0.3293,0.2473,0.1105,-0.1121",\ +"0.4621,0.4465,0.4152,0.3762,0.2941,0.1535,-0.0691",\ +"0.5441,0.5285,0.4973,0.4465,0.3684,0.2316,0.0090",\ +"0.6848,0.6652,0.6301,0.5910,0.5129,0.3605,0.1496",\ +"0.9074,0.8918,0.8566,0.8215,0.7395,0.5910,0.3723"); + } + + fall_constraint("SIG2SRAM_constraint_template") { + index_1("0.0080,0.0288,0.0616,0.1072,0.1920,0.3496,0.5952"); + index_2("0.0080,0.0288,0.0616,0.1072,0.1920,0.3496,0.5952"); + values ("0.3762,0.3605,0.3332,0.2863,0.2043,0.0715,-0.1395",\ +"0.3996,0.3762,0.3488,0.3059,0.2238,0.0910,-0.1199",\ +"0.4270,0.4035,0.3762,0.3332,0.2512,0.1184,-0.0965",\ +"0.4699,0.4504,0.4191,0.3762,0.2941,0.1613,-0.0496",\ +"0.5441,0.5285,0.4973,0.4543,0.3762,0.2355,0.0324",\ +"0.6770,0.6613,0.6340,0.5949,0.5207,0.3762,0.1652",\ +"0.9074,0.8918,0.8605,0.8176,0.7395,0.6027,0.3918"); + } + } + } +bus(A_BIST_BM) { + bus_type : D_31_0; + direction : input ; + capacitance : 0.00347781 ; + max_transition : "0.5952" ; + pin(A_BIST_BM[31:0]) { + related_power_pin : VDD; + related_ground_pin : VSS; + internal_power() { + when : "A_BIST_MEN"; + rise_power("scalar"){ + values (0.0936); + } + fall_power("scalar"){ + values (0.0304); + } + } + internal_power() { + when : "!A_BIST_MEN"; + rise_power("scalar"){ + values (0.0900); + } + fall_power("scalar"){ + values (0.0290); + } + } + } + timing() { + timing_type : setup_rising; + related_pin : "A_BIST_CLK"; + when : "(A_BIST_WEN & A_BIST_MEN)" + sdf_cond : "A_BIST_RW_ACCESS" + + rise_constraint("SIG2SRAM_constraint_template") { + index_1("0.0080,0.0288,0.0616,0.1072,0.1920,0.3496,0.5952"); + index_2("0.0080,0.0288,0.0616,0.1072,0.1920,0.3496,0.5952"); + values ("-0.9175,-0.8980,-0.8726,-0.8296,-0.7485,-0.6030,-0.3804",\ +"-0.9254,-0.9059,-0.8805,-0.8375,-0.7565,-0.6109,-0.3883",\ +"-0.9345,-0.9150,-0.8896,-0.8467,-0.7656,-0.6201,-0.3974",\ +"-0.9495,-0.9300,-0.9046,-0.8616,-0.7806,-0.6351,-0.4124",\ +"-0.9719,-0.9524,-0.9270,-0.8840,-0.8030,-0.6575,-0.4348",\ +"-1.0155,-0.9960,-0.9706,-0.9276,-0.8466,-0.7010,-0.4784",\ +"-1.0847,-1.0652,-1.0398,-0.9968,-0.9157,-0.7702,-0.5476"); + } + + fall_constraint("SIG2SRAM_constraint_template") { + index_1("0.0080,0.0288,0.0616,0.1072,0.1920,0.3496,0.5952"); + index_2("0.0080,0.0288,0.0616,0.1072,0.1920,0.3496,0.5952"); + values ("-0.8550,-0.8374,-0.8101,-0.7710,-0.6880,-0.5523,-0.3403",\ +"-0.8629,-0.8453,-0.8180,-0.7789,-0.6959,-0.5602,-0.3483",\ +"-0.8720,-0.8545,-0.8271,-0.7881,-0.7051,-0.5693,-0.3574",\ +"-0.8870,-0.8694,-0.8421,-0.8030,-0.7200,-0.5843,-0.3724",\ +"-0.9094,-0.8918,-0.8645,-0.8254,-0.7424,-0.6067,-0.3948",\ +"-0.9530,-0.9354,-0.9081,-0.8690,-0.7860,-0.6503,-0.4384",\ +"-1.0222,-1.0046,-0.9773,-0.9382,-0.8552,-0.7194,-0.5075"); + } + } + + + timing() { + timing_type : hold_rising; + related_pin : "A_BIST_CLK"; + when : "(A_BIST_WEN & A_BIST_MEN)" + sdf_cond : "A_BIST_RW_ACCESS" + + rise_constraint("SIG2SRAM_constraint_template") { + index_1("0.0080,0.0288,0.0616,0.1072,0.1920,0.3496,0.5952"); + index_2("0.0080,0.0288,0.0616,0.1072,0.1920,0.3496,0.5952"); + values ("1.0343,1.0128,0.9884,0.9454,0.8653,0.7188,0.4962",\ +"1.0422,1.0207,0.9963,0.9533,0.8733,0.7268,0.5041",\ +"1.0513,1.0299,1.0054,0.9625,0.8824,0.7359,0.5133",\ +"1.0663,1.0448,1.0204,0.9775,0.8974,0.7509,0.5282",\ +"1.0887,1.0672,1.0428,0.9998,0.9198,0.7733,0.5506",\ +"1.1323,1.1108,1.0864,1.0434,0.9634,0.8169,0.5942",\ +"1.2015,1.1800,1.1556,1.1126,1.0325,0.8861,0.6634"); + } + + fall_constraint("SIG2SRAM_constraint_template") { + index_1("0.0080,0.0288,0.0616,0.1072,0.1920,0.3496,0.5952"); + index_2("0.0080,0.0288,0.0616,0.1072,0.1920,0.3496,0.5952"); + values ("0.9601,0.9425,0.9151,0.8761,0.7931,0.6563,0.4454",\ +"0.9680,0.9504,0.9231,0.8840,0.8010,0.6643,0.4533",\ +"0.9771,0.9595,0.9322,0.8931,0.8101,0.6734,0.4625",\ +"0.9921,0.9745,0.9472,0.9081,0.8251,0.6884,0.4775",\ +"1.0145,0.9969,0.9696,0.9305,0.8475,0.7108,0.4998",\ +"1.0581,1.0405,1.0132,0.9741,0.8911,0.7544,0.5434",\ +"1.1273,1.1097,1.0823,1.0433,0.9603,0.8236,0.6126"); + } + } +} + pin(A_BIST_CLK) { + direction : input; + capacitance : 0.00378957; + max_transition : "0.5952"; + clock : "true" ; + pin_func_type : active_rising ; + + timing () { + timing_type : "min_pulse_width"; + related_pin : "A_BIST_CLK"; + rise_constraint("CLKTRAN_constraint_template") { + index_1("0.008,0.5952"); + values("0.4,0.4"); + } + } + + related_power_pin : VDD; + related_ground_pin : VSS; + + internal_power() { + when : "!A_BIST_MEN & !A_BIST_WEN & !A_BIST_REN"; + rise_power("scalar"){ + values (0); + } + fall_power("scalar"){ + values (0); + } + } + internal_power() { + when : "!A_BIST_MEN & A_BIST_WEN & !A_BIST_REN"; + rise_power("scalar"){ + values (0.4981); + } + fall_power("scalar"){ + values (0); + } + } + internal_power() { + when : "A_BIST_MEN & A_BIST_WEN & !A_BIST_REN"; + rise_power("scalar"){ + values (28.0075); + } + fall_power("scalar"){ + values (0); + } + } + internal_power() { + when : "A_BIST_MEN & A_BIST_WEN & A_BIST_REN"; + rise_power("scalar"){ + values (30.3621); + } + fall_power("scalar"){ + values (0); + } + } + internal_power() { + when : "A_BIST_MEN & !A_BIST_WEN & A_BIST_REN"; + rise_power("scalar"){ + values (21.9513); + } + fall_power("scalar"){ + values (0); + } + } + internal_power() { + when : "!A_BIST_MEN & !A_BIST_WEN & A_BIST_REN"; + rise_power("scalar"){ + values (0.3219); + } + fall_power("scalar"){ + values (0); + } + } + internal_power() { + when : "!A_BIST_MEN & A_BIST_WEN & A_BIST_REN"; + rise_power("scalar"){ + values (1.0771); + } + fall_power("scalar"){ + values (0); + } + } + internal_power() { + when : "A_BIST_MEN & !A_BIST_WEN & !A_BIST_REN"; + rise_power("scalar"){ + values (0); + } + fall_power("scalar"){ + values (0); + } + } + } + bus(A_BIST_DIN) { + bus_type : D_31_0; + direction : input ; + capacitance : 0.00396073 ; + memory_write() { + address : A_BIST_ADDR ; + clocked_on : A_BIST_CLK; + } + + max_transition : "0.5952" ; + pin(A_BIST_DIN[31:0]) { + related_power_pin : VDD; + related_ground_pin : VSS; + internal_power() { + when : "A_BIST_MEN"; + rise_power("scalar"){ + values (0.0936); + } + fall_power("scalar"){ + values (0.0304); + } + } + internal_power() { + when : "!A_BIST_MEN"; + rise_power("scalar"){ + values (0.0900); + } + fall_power("scalar"){ + values (0.0290); + } + } + } + timing() { + timing_type : setup_rising; + related_pin : "A_BIST_CLK"; + when : "(A_BIST_WEN & A_BIST_MEN)"; + sdf_cond : "A_BIST_W_ACCESS"; + + rise_constraint("SIG2SRAM_constraint_template") { + index_1("0.0080,0.0288,0.0616,0.1072,0.1920,0.3496,0.5952"); + index_2("0.0080,0.0288,0.0616,0.1072,0.1920,0.3496,0.5952"); + values ("-0.9175,-0.8980,-0.8726,-0.8296,-0.7485,-0.6030,-0.3804",\ +"-0.9254,-0.9059,-0.8805,-0.8375,-0.7565,-0.6109,-0.3883",\ +"-0.9345,-0.9150,-0.8896,-0.8467,-0.7656,-0.6201,-0.3974",\ +"-0.9495,-0.9300,-0.9046,-0.8616,-0.7806,-0.6351,-0.4124",\ +"-0.9719,-0.9524,-0.9270,-0.8840,-0.8030,-0.6575,-0.4348",\ +"-1.0155,-0.9960,-0.9706,-0.9276,-0.8466,-0.7010,-0.4784",\ +"-1.0847,-1.0652,-1.0398,-0.9968,-0.9157,-0.7702,-0.5476"); + } + + fall_constraint("SIG2SRAM_constraint_template") { + index_1("0.0080,0.0288,0.0616,0.1072,0.1920,0.3496,0.5952"); + index_2("0.0080,0.0288,0.0616,0.1072,0.1920,0.3496,0.5952"); + values ("-0.8550,-0.8374,-0.8101,-0.7710,-0.6880,-0.5523,-0.3403",\ +"-0.8629,-0.8453,-0.8180,-0.7789,-0.6959,-0.5602,-0.3483",\ +"-0.8720,-0.8545,-0.8271,-0.7881,-0.7051,-0.5693,-0.3574",\ +"-0.8870,-0.8694,-0.8421,-0.8030,-0.7200,-0.5843,-0.3724",\ +"-0.9094,-0.8918,-0.8645,-0.8254,-0.7424,-0.6067,-0.3948",\ +"-0.9530,-0.9354,-0.9081,-0.8690,-0.7860,-0.6503,-0.4384",\ +"-1.0222,-1.0046,-0.9773,-0.9382,-0.8552,-0.7194,-0.5075"); + } + } + + timing() { + timing_type : hold_rising; + related_pin : "A_BIST_CLK"; + when : "(A_BIST_WEN & A_BIST_MEN)"; + sdf_cond : "A_BIST_W_ACCESS"; + + rise_constraint("SIG2SRAM_constraint_template") { + index_1("0.0080,0.0288,0.0616,0.1072,0.1920,0.3496,0.5952"); + index_2("0.0080,0.0288,0.0616,0.1072,0.1920,0.3496,0.5952"); + values ("1.0343,1.0128,0.9884,0.9454,0.8653,0.7188,0.4962",\ +"1.0422,1.0207,0.9963,0.9533,0.8733,0.7268,0.5041",\ +"1.0513,1.0299,1.0054,0.9625,0.8824,0.7359,0.5133",\ +"1.0663,1.0448,1.0204,0.9775,0.8974,0.7509,0.5282",\ +"1.0887,1.0672,1.0428,0.9998,0.9198,0.7733,0.5506",\ +"1.1323,1.1108,1.0864,1.0434,0.9634,0.8169,0.5942",\ +"1.2015,1.1800,1.1556,1.1126,1.0325,0.8861,0.6634"); + } + + fall_constraint("SIG2SRAM_constraint_template") { + index_1("0.0080,0.0288,0.0616,0.1072,0.1920,0.3496,0.5952"); + index_2("0.0080,0.0288,0.0616,0.1072,0.1920,0.3496,0.5952"); + values ("0.9601,0.9425,0.9151,0.8761,0.7931,0.6563,0.4454",\ +"0.9680,0.9504,0.9231,0.8840,0.8010,0.6643,0.4533",\ +"0.9771,0.9595,0.9322,0.8931,0.8101,0.6734,0.4625",\ +"0.9921,0.9745,0.9472,0.9081,0.8251,0.6884,0.4775",\ +"1.0145,0.9969,0.9696,0.9305,0.8475,0.7108,0.4998",\ +"1.0581,1.0405,1.0132,0.9741,0.8911,0.7544,0.5434",\ +"1.1273,1.1097,1.0823,1.0433,0.9603,0.8236,0.6126"); + } + } + } + +bus(A_DOUT) { + + bus_type : D_31_0; + direction : output ; + capacitance : 0 ; + max_capacitance : 0.064 ; + memory_read() { + address : A_ADDR ; + } + pin(A_DOUT[31:0]) { + related_power_pin : VDD; + related_ground_pin : VSS; + internal_power() { + rise_power("scalar") { + values (0); + } + fall_power("scalar") { + values (0); + } + } + } + timing() { + related_pin : "A_CLK"; + timing_type : rising_edge ; + timing_sense : non_unate ; + + cell_rise(SIG2SRAM_delay_template) { + index_1("0.0080,0.0288,0.0616,0.1072,0.1920,0.3496,0.5952"); + index_2("0.0008,0.0014,0.0051,0.0100,0.0339,0.0640"); + values ("5.2549,5.2582,5.2704,5.2844,5.3369,5.3948",\ +"5.2688,5.2721,5.2843,5.2983,5.3508,5.4087",\ +"5.2786,5.2820,5.2942,5.3081,5.3607,5.4185",\ +"5.2919,5.2953,5.3075,5.3214,5.3740,5.4318",\ +"5.3152,5.3185,5.3307,5.3447,5.3972,5.4551",\ +"5.3599,5.3633,5.3755,5.3894,5.4420,5.4998",\ +"5.4272,5.4306,5.4427,5.4567,5.5092,5.5671"); + } + cell_fall(SIG2SRAM_delay_template) { + index_1("0.0080,0.0288,0.0616,0.1072,0.1920,0.3496,0.5952"); + index_2("0.0008,0.0014,0.0051,0.0100,0.0339,0.0640"); + values ("5.1451,5.1473,5.1574,5.1690,5.2124,5.2562",\ +"5.1590,5.1612,5.1713,5.1829,5.2263,5.2701",\ +"5.1689,5.1711,5.1811,5.1928,5.2361,5.2800",\ +"5.1822,5.1844,5.1944,5.2061,5.2494,5.2933",\ +"5.2055,5.2076,5.2177,5.2294,5.2727,5.3165",\ +"5.2502,5.2524,5.2624,5.2741,5.3174,5.3613",\ +"5.3175,5.3196,5.3297,5.3414,5.3847,5.4285"); + } + + rise_transition(SRAM_load_template) { + index_1("0.0008,0.0014,0.0051,0.0100,0.0339,0.0640"); + values ("0.0560,0.0583,0.0696,0.0816,0.1519,0.2335"); + } + fall_transition(SRAM_load_template) { + index_1("0.0008,0.0014,0.0051,0.0100,0.0339,0.0640"); + values ("0.0428,0.0445,0.0538,0.0658,0.1181,0.1751"); + } + } +} + pin(B_DLY) { + direction : input ; + capacitance : 0.00387999 ; + max_transition : "1" ; + related_power_pin : VDD; + related_ground_pin : VSS; + internal_power() { + rise_power("scalar") { + values (0); + } + fall_power("scalar") { + values (0); + } + } + } + +bus(B_ADDR) { + bus_type : A_7_0; + direction : input ; + capacitance : 0.0129586 ; + pin(B_ADDR[0]) { + capacitance : 0.00588404 ; + } + pin(B_ADDR[1]) { + capacitance : 0.0080425 ; + } + pin(B_ADDR[2]) { + capacitance : 0.0112051 ; + } + pin(B_ADDR[3]) { + capacitance : 0.00706428 ; + } + pin(B_ADDR[4]) { + capacitance : 0.00656149 ; + } + pin(B_ADDR[5]) { + capacitance : 0.0111839 ; + } + pin(B_ADDR[6]) { + capacitance : 0.0140236 ; + } + max_transition : "0.5952" ; + pin(B_ADDR[7:0]) { + related_power_pin : VDD; + related_ground_pin : VSS; + internal_power() { + when : "B_MEN"; + rise_power("scalar"){ + values (0.0097); + } + fall_power("scalar"){ + values (0.0074); + } + } + internal_power() { + when : "!B_MEN"; + rise_power("scalar"){ + values (0.0163); + } + fall_power("scalar"){ + values (0.0021); + } + } + } + timing() { + timing_type : setup_rising; + related_pin : "B_CLK"; + when : "((B_WEN | B_REN)& B_MEN)" + sdf_cond : "B_RW_ACCESS" + + rise_constraint("SIG2SRAM_constraint_template") { + index_1("0.0080,0.0288,0.0616,0.1072,0.1920,0.3496,0.5952"); + index_2("0.0080,0.0288,0.0616,0.1072,0.1920,0.3496,0.5952"); + values ("-0.7371,-0.7176,-0.6863,-0.6434,-0.5652,-0.4168,-0.1980",\ +"-0.7566,-0.7371,-0.7059,-0.6629,-0.5848,-0.4363,-0.2137",\ +"-0.7879,-0.7645,-0.7332,-0.6902,-0.6121,-0.4637,-0.2449",\ +"-0.8309,-0.8074,-0.7762,-0.7332,-0.6551,-0.5066,-0.2879",\ +"-0.9051,-0.8895,-0.8543,-0.8113,-0.7332,-0.5887,-0.3660",\ +"-1.0418,-1.0262,-0.9949,-0.9480,-0.8699,-0.7293,-0.5027",\ +"-1.2684,-1.2449,-1.2176,-1.1707,-1.0965,-0.9480,-0.7293"); + } + + fall_constraint("SIG2SRAM_constraint_template") { + index_1("0.0080,0.0288,0.0616,0.1072,0.1920,0.3496,0.5952"); + index_2("0.0080,0.0288,0.0616,0.1072,0.1920,0.3496,0.5952"); + values ("-0.5926,-0.5730,-0.5418,-0.4988,-0.4246,-0.2879,-0.0730",\ +"-0.6121,-0.5926,-0.5613,-0.5223,-0.4441,-0.3074,-0.0887",\ +"-0.6395,-0.6199,-0.5926,-0.5496,-0.4715,-0.3348,-0.1160",\ +"-0.6863,-0.6668,-0.6355,-0.5965,-0.5184,-0.3777,-0.1590",\ +"-0.7605,-0.7410,-0.7137,-0.6746,-0.5926,-0.4559,-0.2410",\ +"-0.9012,-0.8816,-0.8504,-0.8113,-0.7332,-0.5926,-0.3895",\ +"-1.1238,-1.1043,-1.0769,-1.0379,-0.9559,-0.8191,-0.6004"); + } + } + + + timing() { + timing_type : hold_rising; + related_pin : "B_CLK"; + when : "((B_WEN | B_REN)& B_MEN)" + sdf_cond : "B_RW_ACCESS" + + rise_constraint("SIG2SRAM_constraint_template") { + index_1("0.0080,0.0288,0.0616,0.1072,0.1920,0.3496,0.5952"); + index_2("0.0080,0.0288,0.0616,0.1072,0.1920,0.3496,0.5952"); + values ("0.8488,0.8293,0.7980,0.7551,0.6730,0.5285,0.3059",\ +"0.8684,0.8488,0.8176,0.7746,0.6926,0.5480,0.3254",\ +"0.8996,0.8801,0.8449,0.8020,0.7238,0.5754,0.3527",\ +"0.9426,0.9191,0.8918,0.8488,0.7668,0.6223,0.3996",\ +"1.0168,1.0012,0.9699,0.9230,0.8449,0.7004,0.4777",\ +"1.1574,1.1379,1.1105,1.0598,0.9816,0.8371,0.6184",\ +"1.3801,1.3605,1.3254,1.2980,1.2043,1.0637,0.8371"); + } + + fall_constraint("SIG2SRAM_constraint_template") { + index_1("0.0080,0.0288,0.0616,0.1072,0.1920,0.3496,0.5952"); + index_2("0.0080,0.0288,0.0616,0.1072,0.1920,0.3496,0.5952"); + values ("0.6965,0.6770,0.6496,0.6066,0.5246,0.3918,0.1730",\ +"0.7160,0.6965,0.6652,0.6262,0.5441,0.4113,0.1965",\ +"0.7473,0.7277,0.6965,0.6535,0.5754,0.4426,0.2238",\ +"0.7863,0.7707,0.7395,0.7004,0.6223,0.4855,0.2629",\ +"0.8684,0.8449,0.8176,0.7785,0.7004,0.5637,0.3449",\ +"1.0051,0.9855,0.9855,0.9113,0.8332,0.7004,0.4895",\ +"1.2277,1.2082,1.1809,1.1379,1.0598,0.9230,0.7004"); + } + } +} +pin(B_WEN) { + direction : input ; + capacitance : 0.00313551 ; + max_transition : "0.5952" ; + related_power_pin : VDD; + related_ground_pin : VSS; + internal_power() { + when : "B_MEN"; + rise_power("scalar"){ + values (0.0036); + } + fall_power("scalar"){ + values (0.0005); + } + } + internal_power() { + when : "!B_MEN"; + rise_power("scalar"){ + values (0.0052); + } + fall_power("scalar"){ + values (0.0001); + } + } + timing() { + timing_type : setup_rising; + related_pin : "B_CLK"; + when : "B_MEN" + sdf_cond : "B_MEN" + + rise_constraint("SIG2SRAM_constraint_template") { + index_1("0.0080,0.0288,0.0616,0.1072,0.1920,0.3496,0.5952"); + index_2("0.0080,0.0288,0.0616,0.1072,0.1920,0.3496,0.5952"); + values ("0.3137,0.3332,0.3605,0.4035,0.4816,0.6223,0.8488",\ +"0.2980,0.3176,0.3410,0.3840,0.4660,0.6027,0.8293",\ +"0.2629,0.2824,0.3098,0.3527,0.4348,0.5754,0.7980",\ +"0.2199,0.2395,0.2668,0.3098,0.3918,0.5324,0.7590",\ +"0.1418,0.1613,0.1887,0.2316,0.3137,0.4348,0.6730",\ +"0.0012,0.0207,0.0520,0.0910,0.1730,0.3098,0.5285",\ +"-0.2215,-0.2020,-0.1746,-0.1277,-0.0496,0.0910,0.3098"); + } + + fall_constraint("SIG2SRAM_constraint_template") { + index_1("0.0080,0.0288,0.0616,0.1072,0.1920,0.3496,0.5952"); + index_2("0.0080,0.0288,0.0616,0.1072,0.1920,0.3496,0.5952"); + values ("0.4504,0.4699,0.4973,0.5324,0.6027,0.7355,0.9699",\ +"0.4309,0.4504,0.4777,0.5129,0.5910,0.7160,0.9504",\ +"0.3996,0.4191,0.4465,0.4816,0.5520,0.6848,0.9191",\ +"0.3605,0.3762,0.4035,0.4387,0.5168,0.6418,0.8723",\ +"0.2785,0.2980,0.3215,0.3605,0.4348,0.5637,0.7980",\ +"0.1379,0.1574,0.1809,0.2199,0.2980,0.4309,0.6457",\ +"-0.0809,-0.0613,-0.0340,0.0051,0.0832,0.2160,0.4191"); + } + } + + + timing() { + timing_type : hold_rising; + related_pin : "B_CLK"; + when : "B_MEN" + sdf_cond : "B_MEN" + + rise_constraint("SIG2SRAM_constraint_template") { + index_1("0.0080,0.0288,0.0616,0.1072,0.1920,0.3496,0.5952"); + index_2("0.0080,0.0288,0.0616,0.1072,0.1920,0.3496,0.5952"); + values ("0.3723,0.3527,0.3215,0.2785,0.1965,0.0559,-0.1668",\ +"0.3918,0.3723,0.3449,0.2980,0.2160,0.0754,-0.1473",\ +"0.4152,0.3996,0.3684,0.3254,0.2434,0.1066,-0.1199",\ +"0.4621,0.4465,0.4152,0.3723,0.2863,0.1496,-0.0730",\ +"0.5324,0.5207,0.4895,0.4465,0.3645,0.2199,0.0051",\ +"0.6770,0.6535,0.6301,0.5832,0.5090,0.3605,0.1418",\ +"0.9035,0.8879,0.8566,0.8137,0.7316,0.5871,0.3684"); + } + + fall_constraint("SIG2SRAM_constraint_template") { + index_1("0.0080,0.0288,0.0616,0.1072,0.1920,0.3496,0.5952"); + index_2("0.0080,0.0288,0.0616,0.1072,0.1920,0.3496,0.5952"); + values ("0.3762,0.3566,0.3293,0.2863,0.2043,0.0676,-0.1434",\ +"0.3957,0.3762,0.3488,0.3059,0.2238,0.0871,-0.1199",\ +"0.4230,0.4035,0.3723,0.3332,0.2512,0.1184,-0.0965",\ +"0.4660,0.4465,0.4191,0.3762,0.2941,0.1613,-0.0496",\ +"0.5324,0.5168,0.4973,0.4543,0.3723,0.2316,0.0285",\ +"0.6809,0.6613,0.6340,0.5910,0.5129,0.3645,0.1652",\ +"0.9113,0.8918,0.8605,0.8176,0.7395,0.5988,0.3879"); + } + } + } +pin(B_REN) { + direction : input ; + capacitance : 0.00381144 ; + max_transition : "0.5952" ; + related_power_pin : VDD; + related_ground_pin : VSS; + internal_power() { + when : "B_MEN"; + rise_power("scalar"){ + values (0.0041); + } + fall_power("scalar"){ + values (0.0013); + } + } + internal_power() { + when : "!B_MEN"; + rise_power("scalar"){ + values (0.0042); + } + fall_power("scalar"){ + values (0.0010); + } + } + timing() { + timing_type : setup_rising; + related_pin : "B_CLK"; + when : "B_MEN" + sdf_cond : "B_MEN" + + rise_constraint("SIG2SRAM_constraint_template") { + index_1("0.0080,0.0288,0.0616,0.1072,0.1920,0.3496,0.5952"); + index_2("0.0080,0.0288,0.0616,0.1072,0.1920,0.3496,0.5952"); + values ("-0.0770,-0.0574,-0.0262,0.0168,0.0949,0.2355,0.4582",\ +"-0.0965,-0.0770,-0.0457,-0.0027,0.0754,0.2160,0.4387",\ +"-0.1199,-0.1004,-0.0730,-0.0262,0.0520,0.1887,0.4113",\ +"-0.1590,-0.1434,-0.1160,-0.0730,0.0051,0.1457,0.3645",\ +"-0.2449,-0.2254,-0.1941,-0.1473,-0.0770,0.0676,0.2863",\ +"-0.3816,-0.3699,-0.3387,-0.2801,-0.2215,-0.0770,0.1457",\ +"-0.6121,-0.5926,-0.5613,-0.5145,-0.4363,-0.2996,-0.0730"); + } + + fall_constraint("SIG2SRAM_constraint_template") { + index_1("0.0080,0.0288,0.0616,0.1072,0.1920,0.3496,0.5952"); + index_2("0.0080,0.0288,0.0616,0.1072,0.1920,0.3496,0.5952"); + values ("0.1262,0.1457,0.1691,0.2121,0.2824,0.4191,0.6457",\ +"0.1105,0.1262,0.1496,0.1887,0.2629,0.3996,0.6262",\ +"0.0793,0.0949,0.1223,0.1652,0.2395,0.3684,0.5949",\ +"0.0363,0.0559,0.0793,0.1223,0.2004,0.3410,0.5520",\ +"-0.0457,-0.0262,0.0012,0.0441,0.1301,0.2629,0.4738",\ +"-0.1902,-0.1746,-0.1434,-0.1043,-0.0184,0.1223,0.3332",\ +"-0.4129,-0.3934,-0.3660,-0.3230,-0.2449,-0.1043,0.1105"); + } + } + + + timing() { + timing_type : hold_rising; + related_pin : "B_CLK"; + when : "B_MEN" + sdf_cond : "B_MEN" + + rise_constraint("SIG2SRAM_constraint_template") { + index_1("0.0080,0.0288,0.0616,0.1072,0.1920,0.3496,0.5952"); + index_2("0.0080,0.0288,0.0616,0.1072,0.1920,0.3496,0.5952"); + values ("0.4113,0.3918,0.3645,0.3176,0.2395,0.0988,-0.1238",\ +"0.4309,0.4113,0.3840,0.3371,0.2590,0.1184,-0.1043",\ +"0.4582,0.4387,0.4113,0.3645,0.2824,0.1457,-0.0770",\ +"0.5051,0.4816,0.4543,0.4074,0.3293,0.1887,-0.0340",\ +"0.5715,0.5598,0.5324,0.4895,0.4035,0.2512,0.0441",\ +"0.7043,0.7004,0.6730,0.6262,0.5402,0.3957,0.1809",\ +"0.9387,0.9270,0.8957,0.8527,0.7746,0.6262,0.4074"); + } + + fall_constraint("SIG2SRAM_constraint_template") { + index_1("0.0080,0.0288,0.0616,0.1072,0.1920,0.3496,0.5952"); + index_2("0.0080,0.0288,0.0616,0.1072,0.1920,0.3496,0.5952"); + values ("0.4152,0.3918,0.3645,0.3215,0.2395,0.1027,-0.1082",\ +"0.4309,0.4113,0.3801,0.3410,0.2590,0.1223,-0.0926",\ +"0.4582,0.4387,0.4074,0.3684,0.2863,0.1496,-0.0613",\ +"0.5012,0.4816,0.4504,0.4074,0.3293,0.1887,-0.0145",\ +"0.5715,0.5559,0.5285,0.4816,0.3996,0.2512,0.0598",\ +"0.7160,0.7004,0.6691,0.6262,0.5520,0.4035,0.2004",\ +"0.9387,0.9191,0.8957,0.8488,0.7707,0.6262,0.4113"); + } + } + } +pin(B_MEN) { + direction : input ; + capacitance : 0.00300347 ; + max_transition : "0.5952" ; + related_power_pin : VDD; + related_ground_pin : VSS; + internal_power() { + rise_power("scalar"){ + values (0.0300); + } + fall_power("scalar"){ + values (0.0003); + } + } + timing() { + timing_type : setup_rising; + related_pin : "B_CLK"; + + rise_constraint("SIG2SRAM_constraint_template") { + index_1("0.0080,0.0288,0.0616,0.1072,0.1920,0.3496,0.5952"); + index_2("0.0080,0.0288,0.0616,0.1072,0.1920,0.3496,0.5952"); + values ("0.3215,0.3449,0.3684,0.4113,0.4895,0.6301,0.8527",\ +"0.3059,0.3254,0.3527,0.3957,0.4738,0.6145,0.8371",\ +"0.2746,0.2941,0.3215,0.3645,0.4426,0.5871,0.8059",\ +"0.2316,0.2512,0.2785,0.3215,0.3996,0.5402,0.7629",\ +"0.1496,0.1730,0.1965,0.2395,0.3215,0.4660,0.6848",\ +"0.0090,0.0285,0.0598,0.1027,0.1809,0.3176,0.5402",\ +"-0.2098,-0.1902,-0.1668,-0.1199,-0.0418,0.0988,0.3137"); + } + + fall_constraint("SIG2SRAM_constraint_template") { + index_1("0.0080,0.0288,0.0616,0.1072,0.1920,0.3496,0.5952"); + index_2("0.0080,0.0288,0.0616,0.1072,0.1920,0.3496,0.5952"); + values ("0.4582,0.4738,0.5012,0.5363,0.6145,0.7395,0.9738",\ +"0.4387,0.4543,0.4816,0.5207,0.5910,0.7199,0.9582",\ +"0.4035,0.4230,0.4504,0.4855,0.5637,0.6887,0.9230",\ +"0.3645,0.3840,0.4074,0.4465,0.5285,0.6496,0.8840",\ +"0.2824,0.3020,0.3254,0.3645,0.4465,0.5715,0.7980",\ +"0.1418,0.1613,0.1887,0.2238,0.3020,0.4309,0.6496",\ +"-0.0770,-0.0574,-0.0301,0.0090,0.0910,0.2238,0.4191"); + } + } + + + timing() { + timing_type : hold_rising; + related_pin : "B_CLK"; + + rise_constraint("SIG2SRAM_constraint_template") { + index_1("0.0080,0.0288,0.0616,0.1072,0.1920,0.3496,0.5952"); + index_2("0.0080,0.0288,0.0616,0.1072,0.1920,0.3496,0.5952"); + values ("0.3762,0.3605,0.3293,0.2863,0.2043,0.0637,-0.1629",\ +"0.3996,0.3801,0.3488,0.3020,0.2238,0.0832,-0.1395",\ +"0.4230,0.4074,0.3723,0.3293,0.2473,0.1105,-0.1121",\ +"0.4621,0.4465,0.4152,0.3762,0.2941,0.1535,-0.0691",\ +"0.5441,0.5285,0.4973,0.4465,0.3684,0.2316,0.0090",\ +"0.6848,0.6652,0.6301,0.5910,0.5129,0.3605,0.1496",\ +"0.9074,0.8918,0.8566,0.8215,0.7395,0.5910,0.3723"); + } + + fall_constraint("SIG2SRAM_constraint_template") { + index_1("0.0080,0.0288,0.0616,0.1072,0.1920,0.3496,0.5952"); + index_2("0.0080,0.0288,0.0616,0.1072,0.1920,0.3496,0.5952"); + values ("0.3762,0.3605,0.3332,0.2863,0.2043,0.0715,-0.1395",\ +"0.3996,0.3762,0.3488,0.3059,0.2238,0.0910,-0.1199",\ +"0.4270,0.4035,0.3762,0.3332,0.2512,0.1184,-0.0965",\ +"0.4699,0.4504,0.4191,0.3762,0.2941,0.1613,-0.0496",\ +"0.5441,0.5285,0.4973,0.4543,0.3762,0.2355,0.0324",\ +"0.6770,0.6613,0.6340,0.5949,0.5207,0.3762,0.1652",\ +"0.9074,0.8918,0.8605,0.8176,0.7395,0.6027,0.3918"); + } + } + } +bus(B_BM) { + bus_type : D_31_0; + direction : input ; + capacitance : 0.00293202 ; + max_transition : "0.5952" ; + pin(B_BM[31:0]) { + related_power_pin : VDD; + related_ground_pin : VSS; + internal_power() { + when : "B_MEN"; + rise_power("scalar"){ + values (0.0936); + } + fall_power("scalar"){ + values (0.0304); + } + } + internal_power() { + when : "!B_MEN"; + rise_power("scalar"){ + values (0.0900); + } + fall_power("scalar"){ + values (0.0290); + } + } + } + timing() { + timing_type : setup_rising; + related_pin : "B_CLK"; + when : "(B_WEN & B_MEN)" + sdf_cond : "B_RW_ACCESS" + + rise_constraint("SIG2SRAM_constraint_template") { + index_1("0.0080,0.0288,0.0616,0.1072,0.1920,0.3496,0.5952"); + index_2("0.0080,0.0288,0.0616,0.1072,0.1920,0.3496,0.5952"); + values ("-0.9175,-0.8980,-0.8726,-0.8296,-0.7485,-0.6030,-0.3804",\ +"-0.9254,-0.9059,-0.8805,-0.8375,-0.7565,-0.6109,-0.3883",\ +"-0.9345,-0.9150,-0.8896,-0.8467,-0.7656,-0.6201,-0.3974",\ +"-0.9495,-0.9300,-0.9046,-0.8616,-0.7806,-0.6351,-0.4124",\ +"-0.9719,-0.9524,-0.9270,-0.8840,-0.8030,-0.6575,-0.4348",\ +"-1.0155,-0.9960,-0.9706,-0.9276,-0.8466,-0.7010,-0.4784",\ +"-1.0847,-1.0652,-1.0398,-0.9968,-0.9157,-0.7702,-0.5476"); + } + + fall_constraint("SIG2SRAM_constraint_template") { + index_1("0.0080,0.0288,0.0616,0.1072,0.1920,0.3496,0.5952"); + index_2("0.0080,0.0288,0.0616,0.1072,0.1920,0.3496,0.5952"); + values ("-0.8550,-0.8374,-0.8101,-0.7710,-0.6880,-0.5523,-0.3403",\ +"-0.8629,-0.8453,-0.8180,-0.7789,-0.6959,-0.5602,-0.3483",\ +"-0.8720,-0.8545,-0.8271,-0.7881,-0.7051,-0.5693,-0.3574",\ +"-0.8870,-0.8694,-0.8421,-0.8030,-0.7200,-0.5843,-0.3724",\ +"-0.9094,-0.8918,-0.8645,-0.8254,-0.7424,-0.6067,-0.3948",\ +"-0.9530,-0.9354,-0.9081,-0.8690,-0.7860,-0.6503,-0.4384",\ +"-1.0222,-1.0046,-0.9773,-0.9382,-0.8552,-0.7194,-0.5075"); + } + } + + + timing() { + timing_type : hold_rising; + related_pin : "B_CLK"; + when : "(B_WEN & B_MEN)" + sdf_cond : "B_RW_ACCESS" + + rise_constraint("SIG2SRAM_constraint_template") { + index_1("0.0080,0.0288,0.0616,0.1072,0.1920,0.3496,0.5952"); + index_2("0.0080,0.0288,0.0616,0.1072,0.1920,0.3496,0.5952"); + values ("1.0343,1.0128,0.9884,0.9454,0.8653,0.7188,0.4962",\ +"1.0422,1.0207,0.9963,0.9533,0.8733,0.7268,0.5041",\ +"1.0513,1.0299,1.0054,0.9625,0.8824,0.7359,0.5133",\ +"1.0663,1.0448,1.0204,0.9775,0.8974,0.7509,0.5282",\ +"1.0887,1.0672,1.0428,0.9998,0.9198,0.7733,0.5506",\ +"1.1323,1.1108,1.0864,1.0434,0.9634,0.8169,0.5942",\ +"1.2015,1.1800,1.1556,1.1126,1.0325,0.8861,0.6634"); + } + + fall_constraint("SIG2SRAM_constraint_template") { + index_1("0.0080,0.0288,0.0616,0.1072,0.1920,0.3496,0.5952"); + index_2("0.0080,0.0288,0.0616,0.1072,0.1920,0.3496,0.5952"); + values ("0.9601,0.9425,0.9151,0.8761,0.7931,0.6563,0.4454",\ +"0.9680,0.9504,0.9231,0.8840,0.8010,0.6643,0.4533",\ +"0.9771,0.9595,0.9322,0.8931,0.8101,0.6734,0.4625",\ +"0.9921,0.9745,0.9472,0.9081,0.8251,0.6884,0.4775",\ +"1.0145,0.9969,0.9696,0.9305,0.8475,0.7108,0.4998",\ +"1.0581,1.0405,1.0132,0.9741,0.8911,0.7544,0.5434",\ +"1.1273,1.1097,1.0823,1.0433,0.9603,0.8236,0.6126"); + } + } +} + pin(B_CLK) { + direction : input; + capacitance : 0.00378957; + max_transition : "0.5952"; + clock : "true" ; + pin_func_type : active_rising ; + + timing () { + timing_type : "min_pulse_width"; + related_pin : "B_CLK"; + rise_constraint("CLKTRAN_constraint_template") { + index_1("0.008,0.5952"); + values("0.4,0.4"); + } + } + + related_power_pin : VDD; + related_ground_pin : VSS; + + internal_power() { + when : "!B_MEN & !B_WEN & !B_REN"; + rise_power("scalar"){ + values (0); + } + fall_power("scalar"){ + values (0); + } + } + internal_power() { + when : "!B_MEN & B_WEN & !B_REN"; + rise_power("scalar"){ + values (0.4981); + } + fall_power("scalar"){ + values (0); + } + } + internal_power() { + when : "B_MEN & B_WEN & !B_REN"; + rise_power("scalar"){ + values (28.0075); + } + fall_power("scalar"){ + values (0); + } + } + internal_power() { + when : "B_MEN & B_WEN & B_REN"; + rise_power("scalar"){ + values (30.3621); + } + fall_power("scalar"){ + values (0); + } + } + internal_power() { + when : "B_MEN & !B_WEN & B_REN"; + rise_power("scalar"){ + values (21.9513); + } + fall_power("scalar"){ + values (0); + } + } + internal_power() { + when : "!B_MEN & !B_WEN & B_REN"; + rise_power("scalar"){ + values (0.3219); + } + fall_power("scalar"){ + values (0); + } + } + internal_power() { + when : "!B_MEN & B_WEN & B_REN"; + rise_power("scalar"){ + values (1.0771); + } + fall_power("scalar"){ + values (0); + } + } + internal_power() { + when : "B_MEN & !B_WEN & !B_REN"; + rise_power("scalar"){ + values (0); + } + fall_power("scalar"){ + values (0); + } + } + } + bus(B_DIN) { + bus_type : D_31_0; + direction : input ; + capacitance : 0.00460366 ; + memory_write() { + address : B_ADDR ; + clocked_on : B_CLK; + } + + max_transition : "0.5952" ; + pin(B_DIN[31:0]) { + related_power_pin : VDD; + related_ground_pin : VSS; + internal_power() { + when : "B_MEN"; + rise_power("scalar"){ + values (0.0936); + } + fall_power("scalar"){ + values (0.0304); + } + } + internal_power() { + when : "!B_MEN"; + rise_power("scalar"){ + values (0.0900); + } + fall_power("scalar"){ + values (0.0290); + } + } + } + timing() { + timing_type : setup_rising; + related_pin : "B_CLK"; + when : "(B_WEN & B_MEN)"; + sdf_cond : "B_W_ACCESS"; + + rise_constraint("SIG2SRAM_constraint_template") { + index_1("0.0080,0.0288,0.0616,0.1072,0.1920,0.3496,0.5952"); + index_2("0.0080,0.0288,0.0616,0.1072,0.1920,0.3496,0.5952"); + values ("-0.9175,-0.8980,-0.8726,-0.8296,-0.7485,-0.6030,-0.3804",\ +"-0.9254,-0.9059,-0.8805,-0.8375,-0.7565,-0.6109,-0.3883",\ +"-0.9345,-0.9150,-0.8896,-0.8467,-0.7656,-0.6201,-0.3974",\ +"-0.9495,-0.9300,-0.9046,-0.8616,-0.7806,-0.6351,-0.4124",\ +"-0.9719,-0.9524,-0.9270,-0.8840,-0.8030,-0.6575,-0.4348",\ +"-1.0155,-0.9960,-0.9706,-0.9276,-0.8466,-0.7010,-0.4784",\ +"-1.0847,-1.0652,-1.0398,-0.9968,-0.9157,-0.7702,-0.5476"); + } + + fall_constraint("SIG2SRAM_constraint_template") { + index_1("0.0080,0.0288,0.0616,0.1072,0.1920,0.3496,0.5952"); + index_2("0.0080,0.0288,0.0616,0.1072,0.1920,0.3496,0.5952"); + values ("-0.8550,-0.8374,-0.8101,-0.7710,-0.6880,-0.5523,-0.3403",\ +"-0.8629,-0.8453,-0.8180,-0.7789,-0.6959,-0.5602,-0.3483",\ +"-0.8720,-0.8545,-0.8271,-0.7881,-0.7051,-0.5693,-0.3574",\ +"-0.8870,-0.8694,-0.8421,-0.8030,-0.7200,-0.5843,-0.3724",\ +"-0.9094,-0.8918,-0.8645,-0.8254,-0.7424,-0.6067,-0.3948",\ +"-0.9530,-0.9354,-0.9081,-0.8690,-0.7860,-0.6503,-0.4384",\ +"-1.0222,-1.0046,-0.9773,-0.9382,-0.8552,-0.7194,-0.5075"); + } + } + + timing() { + timing_type : hold_rising; + related_pin : "B_CLK"; + when : "(B_WEN & B_MEN)"; + sdf_cond : "B_W_ACCESS"; + + rise_constraint("SIG2SRAM_constraint_template") { + index_1("0.0080,0.0288,0.0616,0.1072,0.1920,0.3496,0.5952"); + index_2("0.0080,0.0288,0.0616,0.1072,0.1920,0.3496,0.5952"); + values ("1.0343,1.0128,0.9884,0.9454,0.8653,0.7188,0.4962",\ +"1.0422,1.0207,0.9963,0.9533,0.8733,0.7268,0.5041",\ +"1.0513,1.0299,1.0054,0.9625,0.8824,0.7359,0.5133",\ +"1.0663,1.0448,1.0204,0.9775,0.8974,0.7509,0.5282",\ +"1.0887,1.0672,1.0428,0.9998,0.9198,0.7733,0.5506",\ +"1.1323,1.1108,1.0864,1.0434,0.9634,0.8169,0.5942",\ +"1.2015,1.1800,1.1556,1.1126,1.0325,0.8861,0.6634"); + } + + fall_constraint("SIG2SRAM_constraint_template") { + index_1("0.0080,0.0288,0.0616,0.1072,0.1920,0.3496,0.5952"); + index_2("0.0080,0.0288,0.0616,0.1072,0.1920,0.3496,0.5952"); + values ("0.9601,0.9425,0.9151,0.8761,0.7931,0.6563,0.4454",\ +"0.9680,0.9504,0.9231,0.8840,0.8010,0.6643,0.4533",\ +"0.9771,0.9595,0.9322,0.8931,0.8101,0.6734,0.4625",\ +"0.9921,0.9745,0.9472,0.9081,0.8251,0.6884,0.4775",\ +"1.0145,0.9969,0.9696,0.9305,0.8475,0.7108,0.4998",\ +"1.0581,1.0405,1.0132,0.9741,0.8911,0.7544,0.5434",\ +"1.1273,1.1097,1.0823,1.0433,0.9603,0.8236,0.6126"); + } + } + } + + pin(B_BIST_EN) { + direction : input ; + capacitance : 0.00387999 ; + max_transition : "1" ; + related_power_pin : VDD; + related_ground_pin : VSS; + internal_power() { + rise_power("scalar") { + values (0); + } + fall_power("scalar") { + values (0); + } + } + } + +bus(B_BIST_ADDR) { + bus_type : A_7_0; + direction : input ; + capacitance : 0.0129586 ; + pin(B_BIST_ADDR[0]) { + capacitance : 0.00588404 ; + } + pin(B_BIST_ADDR[1]) { + capacitance : 0.0080425 ; + } + pin(B_BIST_ADDR[2]) { + capacitance : 0.0112051 ; + } + pin(B_BIST_ADDR[3]) { + capacitance : 0.00706428 ; + } + pin(B_BIST_ADDR[4]) { + capacitance : 0.00656149 ; + } + pin(B_BIST_ADDR[5]) { + capacitance : 0.0111839 ; + } + pin(B_BIST_ADDR[6]) { + capacitance : 0.0140236 ; + } + max_transition : "0.5952" ; + pin(B_BIST_ADDR[7:0]) { + related_power_pin : VDD; + related_ground_pin : VSS; + internal_power() { + when : "B_BIST_MEN"; + rise_power("scalar"){ + values (0.0097); + } + fall_power("scalar"){ + values (0.0074); + } + } + internal_power() { + when : "!B_BIST_MEN"; + rise_power("scalar"){ + values (0.0163); + } + fall_power("scalar"){ + values (0.0021); + } + } + } + timing() { + timing_type : setup_rising; + related_pin : "B_BIST_CLK"; + when : "((B_BIST_WEN | B_BIST_REN)& B_BIST_MEN)" + sdf_cond : "B_BIST_RW_ACCESS" + + rise_constraint("SIG2SRAM_constraint_template") { + index_1("0.0080,0.0288,0.0616,0.1072,0.1920,0.3496,0.5952"); + index_2("0.0080,0.0288,0.0616,0.1072,0.1920,0.3496,0.5952"); + values ("-0.7371,-0.7176,-0.6863,-0.6434,-0.5652,-0.4168,-0.1980",\ +"-0.7566,-0.7371,-0.7059,-0.6629,-0.5848,-0.4363,-0.2137",\ +"-0.7879,-0.7645,-0.7332,-0.6902,-0.6121,-0.4637,-0.2449",\ +"-0.8309,-0.8074,-0.7762,-0.7332,-0.6551,-0.5066,-0.2879",\ +"-0.9051,-0.8895,-0.8543,-0.8113,-0.7332,-0.5887,-0.3660",\ +"-1.0418,-1.0262,-0.9949,-0.9480,-0.8699,-0.7293,-0.5027",\ +"-1.2684,-1.2449,-1.2176,-1.1707,-1.0965,-0.9480,-0.7293"); + } + + fall_constraint("SIG2SRAM_constraint_template") { + index_1("0.0080,0.0288,0.0616,0.1072,0.1920,0.3496,0.5952"); + index_2("0.0080,0.0288,0.0616,0.1072,0.1920,0.3496,0.5952"); + values ("-0.5926,-0.5730,-0.5418,-0.4988,-0.4246,-0.2879,-0.0730",\ +"-0.6121,-0.5926,-0.5613,-0.5223,-0.4441,-0.3074,-0.0887",\ +"-0.6395,-0.6199,-0.5926,-0.5496,-0.4715,-0.3348,-0.1160",\ +"-0.6863,-0.6668,-0.6355,-0.5965,-0.5184,-0.3777,-0.1590",\ +"-0.7605,-0.7410,-0.7137,-0.6746,-0.5926,-0.4559,-0.2410",\ +"-0.9012,-0.8816,-0.8504,-0.8113,-0.7332,-0.5926,-0.3895",\ +"-1.1238,-1.1043,-1.0769,-1.0379,-0.9559,-0.8191,-0.6004"); + } + } + + + timing() { + timing_type : hold_rising; + related_pin : "B_BIST_CLK"; + when : "((B_BIST_WEN | B_BIST_REN)& B_BIST_MEN)" + sdf_cond : "B_BIST_RW_ACCESS" + + rise_constraint("SIG2SRAM_constraint_template") { + index_1("0.0080,0.0288,0.0616,0.1072,0.1920,0.3496,0.5952"); + index_2("0.0080,0.0288,0.0616,0.1072,0.1920,0.3496,0.5952"); + values ("0.8488,0.8293,0.7980,0.7551,0.6730,0.5285,0.3059",\ +"0.8684,0.8488,0.8176,0.7746,0.6926,0.5480,0.3254",\ +"0.8996,0.8801,0.8449,0.8020,0.7238,0.5754,0.3527",\ +"0.9426,0.9191,0.8918,0.8488,0.7668,0.6223,0.3996",\ +"1.0168,1.0012,0.9699,0.9230,0.8449,0.7004,0.4777",\ +"1.1574,1.1379,1.1105,1.0598,0.9816,0.8371,0.6184",\ +"1.3801,1.3605,1.3254,1.2980,1.2043,1.0637,0.8371"); + } + + fall_constraint("SIG2SRAM_constraint_template") { + index_1("0.0080,0.0288,0.0616,0.1072,0.1920,0.3496,0.5952"); + index_2("0.0080,0.0288,0.0616,0.1072,0.1920,0.3496,0.5952"); + values ("0.6965,0.6770,0.6496,0.6066,0.5246,0.3918,0.1730",\ +"0.7160,0.6965,0.6652,0.6262,0.5441,0.4113,0.1965",\ +"0.7473,0.7277,0.6965,0.6535,0.5754,0.4426,0.2238",\ +"0.7863,0.7707,0.7395,0.7004,0.6223,0.4855,0.2629",\ +"0.8684,0.8449,0.8176,0.7785,0.7004,0.5637,0.3449",\ +"1.0051,0.9855,0.9855,0.9113,0.8332,0.7004,0.4895",\ +"1.2277,1.2082,1.1809,1.1379,1.0598,0.9230,0.7004"); + } + } +} +pin(B_BIST_WEN) { + direction : input ; + capacitance : 0.00313551 ; + max_transition : "0.5952" ; + related_power_pin : VDD; + related_ground_pin : VSS; + internal_power() { + when : "B_BIST_MEN"; + rise_power("scalar"){ + values (0.0036); + } + fall_power("scalar"){ + values (0.0005); + } + } + internal_power() { + when : "!B_BIST_MEN"; + rise_power("scalar"){ + values (0.0052); + } + fall_power("scalar"){ + values (0.0001); + } + } + timing() { + timing_type : setup_rising; + related_pin : "B_BIST_CLK"; + when : "B_BIST_MEN" + sdf_cond : "B_BIST_MEN" + + rise_constraint("SIG2SRAM_constraint_template") { + index_1("0.0080,0.0288,0.0616,0.1072,0.1920,0.3496,0.5952"); + index_2("0.0080,0.0288,0.0616,0.1072,0.1920,0.3496,0.5952"); + values ("0.3137,0.3332,0.3605,0.4035,0.4816,0.6223,0.8488",\ +"0.2980,0.3176,0.3410,0.3840,0.4660,0.6027,0.8293",\ +"0.2629,0.2824,0.3098,0.3527,0.4348,0.5754,0.7980",\ +"0.2199,0.2395,0.2668,0.3098,0.3918,0.5324,0.7590",\ +"0.1418,0.1613,0.1887,0.2316,0.3137,0.4348,0.6730",\ +"0.0012,0.0207,0.0520,0.0910,0.1730,0.3098,0.5285",\ +"-0.2215,-0.2020,-0.1746,-0.1277,-0.0496,0.0910,0.3098"); + } + + fall_constraint("SIG2SRAM_constraint_template") { + index_1("0.0080,0.0288,0.0616,0.1072,0.1920,0.3496,0.5952"); + index_2("0.0080,0.0288,0.0616,0.1072,0.1920,0.3496,0.5952"); + values ("0.4504,0.4699,0.4973,0.5324,0.6027,0.7355,0.9699",\ +"0.4309,0.4504,0.4777,0.5129,0.5910,0.7160,0.9504",\ +"0.3996,0.4191,0.4465,0.4816,0.5520,0.6848,0.9191",\ +"0.3605,0.3762,0.4035,0.4387,0.5168,0.6418,0.8723",\ +"0.2785,0.2980,0.3215,0.3605,0.4348,0.5637,0.7980",\ +"0.1379,0.1574,0.1809,0.2199,0.2980,0.4309,0.6457",\ +"-0.0809,-0.0613,-0.0340,0.0051,0.0832,0.2160,0.4191"); + } + } + + + timing() { + timing_type : hold_rising; + related_pin : "B_BIST_CLK"; + when : "B_BIST_MEN" + sdf_cond : "B_BIST_MEN" + + rise_constraint("SIG2SRAM_constraint_template") { + index_1("0.0080,0.0288,0.0616,0.1072,0.1920,0.3496,0.5952"); + index_2("0.0080,0.0288,0.0616,0.1072,0.1920,0.3496,0.5952"); + values ("0.3723,0.3527,0.3215,0.2785,0.1965,0.0559,-0.1668",\ +"0.3918,0.3723,0.3449,0.2980,0.2160,0.0754,-0.1473",\ +"0.4152,0.3996,0.3684,0.3254,0.2434,0.1066,-0.1199",\ +"0.4621,0.4465,0.4152,0.3723,0.2863,0.1496,-0.0730",\ +"0.5324,0.5207,0.4895,0.4465,0.3645,0.2199,0.0051",\ +"0.6770,0.6535,0.6301,0.5832,0.5090,0.3605,0.1418",\ +"0.9035,0.8879,0.8566,0.8137,0.7316,0.5871,0.3684"); + } + + fall_constraint("SIG2SRAM_constraint_template") { + index_1("0.0080,0.0288,0.0616,0.1072,0.1920,0.3496,0.5952"); + index_2("0.0080,0.0288,0.0616,0.1072,0.1920,0.3496,0.5952"); + values ("0.3762,0.3566,0.3293,0.2863,0.2043,0.0676,-0.1434",\ +"0.3957,0.3762,0.3488,0.3059,0.2238,0.0871,-0.1199",\ +"0.4230,0.4035,0.3723,0.3332,0.2512,0.1184,-0.0965",\ +"0.4660,0.4465,0.4191,0.3762,0.2941,0.1613,-0.0496",\ +"0.5324,0.5168,0.4973,0.4543,0.3723,0.2316,0.0285",\ +"0.6809,0.6613,0.6340,0.5910,0.5129,0.3645,0.1652",\ +"0.9113,0.8918,0.8605,0.8176,0.7395,0.5988,0.3879"); + } + } + } +pin(B_BIST_REN) { + direction : input ; + capacitance : 0.00381144 ; + max_transition : "0.5952" ; + related_power_pin : VDD; + related_ground_pin : VSS; + internal_power() { + when : "B_BIST_MEN"; + rise_power("scalar"){ + values (0.0041); + } + fall_power("scalar"){ + values (0.0013); + } + } + internal_power() { + when : "!B_BIST_MEN"; + rise_power("scalar"){ + values (0.0042); + } + fall_power("scalar"){ + values (0.0010); + } + } + timing() { + timing_type : setup_rising; + related_pin : "B_BIST_CLK"; + when : "B_BIST_MEN" + sdf_cond : "B_BIST_MEN" + + rise_constraint("SIG2SRAM_constraint_template") { + index_1("0.0080,0.0288,0.0616,0.1072,0.1920,0.3496,0.5952"); + index_2("0.0080,0.0288,0.0616,0.1072,0.1920,0.3496,0.5952"); + values ("-0.0770,-0.0574,-0.0262,0.0168,0.0949,0.2355,0.4582",\ +"-0.0965,-0.0770,-0.0457,-0.0027,0.0754,0.2160,0.4387",\ +"-0.1199,-0.1004,-0.0730,-0.0262,0.0520,0.1887,0.4113",\ +"-0.1590,-0.1434,-0.1160,-0.0730,0.0051,0.1457,0.3645",\ +"-0.2449,-0.2254,-0.1941,-0.1473,-0.0770,0.0676,0.2863",\ +"-0.3816,-0.3699,-0.3387,-0.2801,-0.2215,-0.0770,0.1457",\ +"-0.6121,-0.5926,-0.5613,-0.5145,-0.4363,-0.2996,-0.0730"); + } + + fall_constraint("SIG2SRAM_constraint_template") { + index_1("0.0080,0.0288,0.0616,0.1072,0.1920,0.3496,0.5952"); + index_2("0.0080,0.0288,0.0616,0.1072,0.1920,0.3496,0.5952"); + values ("0.1262,0.1457,0.1691,0.2121,0.2824,0.4191,0.6457",\ +"0.1105,0.1262,0.1496,0.1887,0.2629,0.3996,0.6262",\ +"0.0793,0.0949,0.1223,0.1652,0.2395,0.3684,0.5949",\ +"0.0363,0.0559,0.0793,0.1223,0.2004,0.3410,0.5520",\ +"-0.0457,-0.0262,0.0012,0.0441,0.1301,0.2629,0.4738",\ +"-0.1902,-0.1746,-0.1434,-0.1043,-0.0184,0.1223,0.3332",\ +"-0.4129,-0.3934,-0.3660,-0.3230,-0.2449,-0.1043,0.1105"); + } + } + + + timing() { + timing_type : hold_rising; + related_pin : "B_BIST_CLK"; + when : "B_BIST_MEN" + sdf_cond : "B_BIST_MEN" + + rise_constraint("SIG2SRAM_constraint_template") { + index_1("0.0080,0.0288,0.0616,0.1072,0.1920,0.3496,0.5952"); + index_2("0.0080,0.0288,0.0616,0.1072,0.1920,0.3496,0.5952"); + values ("0.4113,0.3918,0.3645,0.3176,0.2395,0.0988,-0.1238",\ +"0.4309,0.4113,0.3840,0.3371,0.2590,0.1184,-0.1043",\ +"0.4582,0.4387,0.4113,0.3645,0.2824,0.1457,-0.0770",\ +"0.5051,0.4816,0.4543,0.4074,0.3293,0.1887,-0.0340",\ +"0.5715,0.5598,0.5324,0.4895,0.4035,0.2512,0.0441",\ +"0.7043,0.7004,0.6730,0.6262,0.5402,0.3957,0.1809",\ +"0.9387,0.9270,0.8957,0.8527,0.7746,0.6262,0.4074"); + } + + fall_constraint("SIG2SRAM_constraint_template") { + index_1("0.0080,0.0288,0.0616,0.1072,0.1920,0.3496,0.5952"); + index_2("0.0080,0.0288,0.0616,0.1072,0.1920,0.3496,0.5952"); + values ("0.4152,0.3918,0.3645,0.3215,0.2395,0.1027,-0.1082",\ +"0.4309,0.4113,0.3801,0.3410,0.2590,0.1223,-0.0926",\ +"0.4582,0.4387,0.4074,0.3684,0.2863,0.1496,-0.0613",\ +"0.5012,0.4816,0.4504,0.4074,0.3293,0.1887,-0.0145",\ +"0.5715,0.5559,0.5285,0.4816,0.3996,0.2512,0.0598",\ +"0.7160,0.7004,0.6691,0.6262,0.5520,0.4035,0.2004",\ +"0.9387,0.9191,0.8957,0.8488,0.7707,0.6262,0.4113"); + } + } + } +pin(B_BIST_MEN) { + direction : input ; + capacitance : 0.00300347 ; + max_transition : "0.5952" ; + related_power_pin : VDD; + related_ground_pin : VSS; + internal_power() { + rise_power("scalar"){ + values (0.0300); + } + fall_power("scalar"){ + values (0.0003); + } + } + timing() { + timing_type : setup_rising; + related_pin : "B_BIST_CLK"; + + rise_constraint("SIG2SRAM_constraint_template") { + index_1("0.0080,0.0288,0.0616,0.1072,0.1920,0.3496,0.5952"); + index_2("0.0080,0.0288,0.0616,0.1072,0.1920,0.3496,0.5952"); + values ("0.3215,0.3449,0.3684,0.4113,0.4895,0.6301,0.8527",\ +"0.3059,0.3254,0.3527,0.3957,0.4738,0.6145,0.8371",\ +"0.2746,0.2941,0.3215,0.3645,0.4426,0.5871,0.8059",\ +"0.2316,0.2512,0.2785,0.3215,0.3996,0.5402,0.7629",\ +"0.1496,0.1730,0.1965,0.2395,0.3215,0.4660,0.6848",\ +"0.0090,0.0285,0.0598,0.1027,0.1809,0.3176,0.5402",\ +"-0.2098,-0.1902,-0.1668,-0.1199,-0.0418,0.0988,0.3137"); + } + + fall_constraint("SIG2SRAM_constraint_template") { + index_1("0.0080,0.0288,0.0616,0.1072,0.1920,0.3496,0.5952"); + index_2("0.0080,0.0288,0.0616,0.1072,0.1920,0.3496,0.5952"); + values ("0.4582,0.4738,0.5012,0.5363,0.6145,0.7395,0.9738",\ +"0.4387,0.4543,0.4816,0.5207,0.5910,0.7199,0.9582",\ +"0.4035,0.4230,0.4504,0.4855,0.5637,0.6887,0.9230",\ +"0.3645,0.3840,0.4074,0.4465,0.5285,0.6496,0.8840",\ +"0.2824,0.3020,0.3254,0.3645,0.4465,0.5715,0.7980",\ +"0.1418,0.1613,0.1887,0.2238,0.3020,0.4309,0.6496",\ +"-0.0770,-0.0574,-0.0301,0.0090,0.0910,0.2238,0.4191"); + } + } + + + timing() { + timing_type : hold_rising; + related_pin : "B_BIST_CLK"; + + rise_constraint("SIG2SRAM_constraint_template") { + index_1("0.0080,0.0288,0.0616,0.1072,0.1920,0.3496,0.5952"); + index_2("0.0080,0.0288,0.0616,0.1072,0.1920,0.3496,0.5952"); + values ("0.3762,0.3605,0.3293,0.2863,0.2043,0.0637,-0.1629",\ +"0.3996,0.3801,0.3488,0.3020,0.2238,0.0832,-0.1395",\ +"0.4230,0.4074,0.3723,0.3293,0.2473,0.1105,-0.1121",\ +"0.4621,0.4465,0.4152,0.3762,0.2941,0.1535,-0.0691",\ +"0.5441,0.5285,0.4973,0.4465,0.3684,0.2316,0.0090",\ +"0.6848,0.6652,0.6301,0.5910,0.5129,0.3605,0.1496",\ +"0.9074,0.8918,0.8566,0.8215,0.7395,0.5910,0.3723"); + } + + fall_constraint("SIG2SRAM_constraint_template") { + index_1("0.0080,0.0288,0.0616,0.1072,0.1920,0.3496,0.5952"); + index_2("0.0080,0.0288,0.0616,0.1072,0.1920,0.3496,0.5952"); + values ("0.3762,0.3605,0.3332,0.2863,0.2043,0.0715,-0.1395",\ +"0.3996,0.3762,0.3488,0.3059,0.2238,0.0910,-0.1199",\ +"0.4270,0.4035,0.3762,0.3332,0.2512,0.1184,-0.0965",\ +"0.4699,0.4504,0.4191,0.3762,0.2941,0.1613,-0.0496",\ +"0.5441,0.5285,0.4973,0.4543,0.3762,0.2355,0.0324",\ +"0.6770,0.6613,0.6340,0.5949,0.5207,0.3762,0.1652",\ +"0.9074,0.8918,0.8605,0.8176,0.7395,0.6027,0.3918"); + } + } + } +bus(B_BIST_BM) { + bus_type : D_31_0; + direction : input ; + capacitance : 0.00261869 ; + max_transition : "0.5952" ; + pin(B_BIST_BM[31:0]) { + related_power_pin : VDD; + related_ground_pin : VSS; + internal_power() { + when : "B_BIST_MEN"; + rise_power("scalar"){ + values (0.0936); + } + fall_power("scalar"){ + values (0.0304); + } + } + internal_power() { + when : "!B_BIST_MEN"; + rise_power("scalar"){ + values (0.0900); + } + fall_power("scalar"){ + values (0.0290); + } + } + } + timing() { + timing_type : setup_rising; + related_pin : "B_BIST_CLK"; + when : "(B_BIST_WEN & B_BIST_MEN)" + sdf_cond : "B_BIST_RW_ACCESS" + + rise_constraint("SIG2SRAM_constraint_template") { + index_1("0.0080,0.0288,0.0616,0.1072,0.1920,0.3496,0.5952"); + index_2("0.0080,0.0288,0.0616,0.1072,0.1920,0.3496,0.5952"); + values ("-0.9175,-0.8980,-0.8726,-0.8296,-0.7485,-0.6030,-0.3804",\ +"-0.9254,-0.9059,-0.8805,-0.8375,-0.7565,-0.6109,-0.3883",\ +"-0.9345,-0.9150,-0.8896,-0.8467,-0.7656,-0.6201,-0.3974",\ +"-0.9495,-0.9300,-0.9046,-0.8616,-0.7806,-0.6351,-0.4124",\ +"-0.9719,-0.9524,-0.9270,-0.8840,-0.8030,-0.6575,-0.4348",\ +"-1.0155,-0.9960,-0.9706,-0.9276,-0.8466,-0.7010,-0.4784",\ +"-1.0847,-1.0652,-1.0398,-0.9968,-0.9157,-0.7702,-0.5476"); + } + + fall_constraint("SIG2SRAM_constraint_template") { + index_1("0.0080,0.0288,0.0616,0.1072,0.1920,0.3496,0.5952"); + index_2("0.0080,0.0288,0.0616,0.1072,0.1920,0.3496,0.5952"); + values ("-0.8550,-0.8374,-0.8101,-0.7710,-0.6880,-0.5523,-0.3403",\ +"-0.8629,-0.8453,-0.8180,-0.7789,-0.6959,-0.5602,-0.3483",\ +"-0.8720,-0.8545,-0.8271,-0.7881,-0.7051,-0.5693,-0.3574",\ +"-0.8870,-0.8694,-0.8421,-0.8030,-0.7200,-0.5843,-0.3724",\ +"-0.9094,-0.8918,-0.8645,-0.8254,-0.7424,-0.6067,-0.3948",\ +"-0.9530,-0.9354,-0.9081,-0.8690,-0.7860,-0.6503,-0.4384",\ +"-1.0222,-1.0046,-0.9773,-0.9382,-0.8552,-0.7194,-0.5075"); + } + } + + + timing() { + timing_type : hold_rising; + related_pin : "B_BIST_CLK"; + when : "(B_BIST_WEN & B_BIST_MEN)" + sdf_cond : "B_BIST_RW_ACCESS" + + rise_constraint("SIG2SRAM_constraint_template") { + index_1("0.0080,0.0288,0.0616,0.1072,0.1920,0.3496,0.5952"); + index_2("0.0080,0.0288,0.0616,0.1072,0.1920,0.3496,0.5952"); + values ("1.0343,1.0128,0.9884,0.9454,0.8653,0.7188,0.4962",\ +"1.0422,1.0207,0.9963,0.9533,0.8733,0.7268,0.5041",\ +"1.0513,1.0299,1.0054,0.9625,0.8824,0.7359,0.5133",\ +"1.0663,1.0448,1.0204,0.9775,0.8974,0.7509,0.5282",\ +"1.0887,1.0672,1.0428,0.9998,0.9198,0.7733,0.5506",\ +"1.1323,1.1108,1.0864,1.0434,0.9634,0.8169,0.5942",\ +"1.2015,1.1800,1.1556,1.1126,1.0325,0.8861,0.6634"); + } + + fall_constraint("SIG2SRAM_constraint_template") { + index_1("0.0080,0.0288,0.0616,0.1072,0.1920,0.3496,0.5952"); + index_2("0.0080,0.0288,0.0616,0.1072,0.1920,0.3496,0.5952"); + values ("0.9601,0.9425,0.9151,0.8761,0.7931,0.6563,0.4454",\ +"0.9680,0.9504,0.9231,0.8840,0.8010,0.6643,0.4533",\ +"0.9771,0.9595,0.9322,0.8931,0.8101,0.6734,0.4625",\ +"0.9921,0.9745,0.9472,0.9081,0.8251,0.6884,0.4775",\ +"1.0145,0.9969,0.9696,0.9305,0.8475,0.7108,0.4998",\ +"1.0581,1.0405,1.0132,0.9741,0.8911,0.7544,0.5434",\ +"1.1273,1.1097,1.0823,1.0433,0.9603,0.8236,0.6126"); + } + } +} + pin(B_BIST_CLK) { + direction : input; + capacitance : 0.00378957; + max_transition : "0.5952"; + clock : "true" ; + pin_func_type : active_rising ; + + timing () { + timing_type : "min_pulse_width"; + related_pin : "B_BIST_CLK"; + rise_constraint("CLKTRAN_constraint_template") { + index_1("0.008,0.5952"); + values("0.4,0.4"); + } + } + + related_power_pin : VDD; + related_ground_pin : VSS; + + internal_power() { + when : "!B_BIST_MEN & !B_BIST_WEN & !B_BIST_REN"; + rise_power("scalar"){ + values (0); + } + fall_power("scalar"){ + values (0); + } + } + internal_power() { + when : "!B_BIST_MEN & B_BIST_WEN & !B_BIST_REN"; + rise_power("scalar"){ + values (0.4981); + } + fall_power("scalar"){ + values (0); + } + } + internal_power() { + when : "B_BIST_MEN & B_BIST_WEN & !B_BIST_REN"; + rise_power("scalar"){ + values (28.0075); + } + fall_power("scalar"){ + values (0); + } + } + internal_power() { + when : "B_BIST_MEN & B_BIST_WEN & B_BIST_REN"; + rise_power("scalar"){ + values (30.3621); + } + fall_power("scalar"){ + values (0); + } + } + internal_power() { + when : "B_BIST_MEN & !B_BIST_WEN & B_BIST_REN"; + rise_power("scalar"){ + values (21.9513); + } + fall_power("scalar"){ + values (0); + } + } + internal_power() { + when : "!B_BIST_MEN & !B_BIST_WEN & B_BIST_REN"; + rise_power("scalar"){ + values (0.3219); + } + fall_power("scalar"){ + values (0); + } + } + internal_power() { + when : "!B_BIST_MEN & B_BIST_WEN & B_BIST_REN"; + rise_power("scalar"){ + values (1.0771); + } + fall_power("scalar"){ + values (0); + } + } + internal_power() { + when : "B_BIST_MEN & !B_BIST_WEN & !B_BIST_REN"; + rise_power("scalar"){ + values (0); + } + fall_power("scalar"){ + values (0); + } + } + } + bus(B_BIST_DIN) { + bus_type : D_31_0; + direction : input ; + capacitance : 0.00416317 ; + memory_write() { + address : B_BIST_ADDR ; + clocked_on : B_BIST_CLK; + } + + max_transition : "0.5952" ; + pin(B_BIST_DIN[31:0]) { + related_power_pin : VDD; + related_ground_pin : VSS; + internal_power() { + when : "B_BIST_MEN"; + rise_power("scalar"){ + values (0.0936); + } + fall_power("scalar"){ + values (0.0304); + } + } + internal_power() { + when : "!B_BIST_MEN"; + rise_power("scalar"){ + values (0.0900); + } + fall_power("scalar"){ + values (0.0290); + } + } + } + timing() { + timing_type : setup_rising; + related_pin : "B_BIST_CLK"; + when : "(B_BIST_WEN & B_BIST_MEN)"; + sdf_cond : "B_BIST_W_ACCESS"; + + rise_constraint("SIG2SRAM_constraint_template") { + index_1("0.0080,0.0288,0.0616,0.1072,0.1920,0.3496,0.5952"); + index_2("0.0080,0.0288,0.0616,0.1072,0.1920,0.3496,0.5952"); + values ("-0.9175,-0.8980,-0.8726,-0.8296,-0.7485,-0.6030,-0.3804",\ +"-0.9254,-0.9059,-0.8805,-0.8375,-0.7565,-0.6109,-0.3883",\ +"-0.9345,-0.9150,-0.8896,-0.8467,-0.7656,-0.6201,-0.3974",\ +"-0.9495,-0.9300,-0.9046,-0.8616,-0.7806,-0.6351,-0.4124",\ +"-0.9719,-0.9524,-0.9270,-0.8840,-0.8030,-0.6575,-0.4348",\ +"-1.0155,-0.9960,-0.9706,-0.9276,-0.8466,-0.7010,-0.4784",\ +"-1.0847,-1.0652,-1.0398,-0.9968,-0.9157,-0.7702,-0.5476"); + } + + fall_constraint("SIG2SRAM_constraint_template") { + index_1("0.0080,0.0288,0.0616,0.1072,0.1920,0.3496,0.5952"); + index_2("0.0080,0.0288,0.0616,0.1072,0.1920,0.3496,0.5952"); + values ("-0.8550,-0.8374,-0.8101,-0.7710,-0.6880,-0.5523,-0.3403",\ +"-0.8629,-0.8453,-0.8180,-0.7789,-0.6959,-0.5602,-0.3483",\ +"-0.8720,-0.8545,-0.8271,-0.7881,-0.7051,-0.5693,-0.3574",\ +"-0.8870,-0.8694,-0.8421,-0.8030,-0.7200,-0.5843,-0.3724",\ +"-0.9094,-0.8918,-0.8645,-0.8254,-0.7424,-0.6067,-0.3948",\ +"-0.9530,-0.9354,-0.9081,-0.8690,-0.7860,-0.6503,-0.4384",\ +"-1.0222,-1.0046,-0.9773,-0.9382,-0.8552,-0.7194,-0.5075"); + } + } + + timing() { + timing_type : hold_rising; + related_pin : "B_BIST_CLK"; + when : "(B_BIST_WEN & B_BIST_MEN)"; + sdf_cond : "B_BIST_W_ACCESS"; + + rise_constraint("SIG2SRAM_constraint_template") { + index_1("0.0080,0.0288,0.0616,0.1072,0.1920,0.3496,0.5952"); + index_2("0.0080,0.0288,0.0616,0.1072,0.1920,0.3496,0.5952"); + values ("1.0343,1.0128,0.9884,0.9454,0.8653,0.7188,0.4962",\ +"1.0422,1.0207,0.9963,0.9533,0.8733,0.7268,0.5041",\ +"1.0513,1.0299,1.0054,0.9625,0.8824,0.7359,0.5133",\ +"1.0663,1.0448,1.0204,0.9775,0.8974,0.7509,0.5282",\ +"1.0887,1.0672,1.0428,0.9998,0.9198,0.7733,0.5506",\ +"1.1323,1.1108,1.0864,1.0434,0.9634,0.8169,0.5942",\ +"1.2015,1.1800,1.1556,1.1126,1.0325,0.8861,0.6634"); + } + + fall_constraint("SIG2SRAM_constraint_template") { + index_1("0.0080,0.0288,0.0616,0.1072,0.1920,0.3496,0.5952"); + index_2("0.0080,0.0288,0.0616,0.1072,0.1920,0.3496,0.5952"); + values ("0.9601,0.9425,0.9151,0.8761,0.7931,0.6563,0.4454",\ +"0.9680,0.9504,0.9231,0.8840,0.8010,0.6643,0.4533",\ +"0.9771,0.9595,0.9322,0.8931,0.8101,0.6734,0.4625",\ +"0.9921,0.9745,0.9472,0.9081,0.8251,0.6884,0.4775",\ +"1.0145,0.9969,0.9696,0.9305,0.8475,0.7108,0.4998",\ +"1.0581,1.0405,1.0132,0.9741,0.8911,0.7544,0.5434",\ +"1.1273,1.1097,1.0823,1.0433,0.9603,0.8236,0.6126"); + } + } + } + +bus(B_DOUT) { + + bus_type : D_31_0; + direction : output ; + capacitance : 0 ; + max_capacitance : 0.064 ; + memory_read() { + address : B_ADDR ; + } + pin(B_DOUT[31:0]) { + related_power_pin : VDD; + related_ground_pin : VSS; + internal_power() { + rise_power("scalar") { + values (0); + } + fall_power("scalar") { + values (0); + } + } + } + timing() { + related_pin : "B_CLK"; + timing_type : rising_edge ; + timing_sense : non_unate ; + + cell_rise(SIG2SRAM_delay_template) { + index_1("0.0080,0.0288,0.0616,0.1072,0.1920,0.3496,0.5952"); + index_2("0.0008,0.0014,0.0051,0.0100,0.0339,0.0640"); + values ("5.2549,5.2582,5.2704,5.2844,5.3369,5.3948",\ +"5.2688,5.2721,5.2843,5.2983,5.3508,5.4087",\ +"5.2786,5.2820,5.2942,5.3081,5.3607,5.4185",\ +"5.2919,5.2953,5.3075,5.3214,5.3740,5.4318",\ +"5.3152,5.3185,5.3307,5.3447,5.3972,5.4551",\ +"5.3599,5.3633,5.3755,5.3894,5.4420,5.4998",\ +"5.4272,5.4306,5.4427,5.4567,5.5092,5.5671"); + } + cell_fall(SIG2SRAM_delay_template) { + index_1("0.0080,0.0288,0.0616,0.1072,0.1920,0.3496,0.5952"); + index_2("0.0008,0.0014,0.0051,0.0100,0.0339,0.0640"); + values ("5.1451,5.1473,5.1574,5.1690,5.2124,5.2562",\ +"5.1590,5.1612,5.1713,5.1829,5.2263,5.2701",\ +"5.1689,5.1711,5.1811,5.1928,5.2361,5.2800",\ +"5.1822,5.1844,5.1944,5.2061,5.2494,5.2933",\ +"5.2055,5.2076,5.2177,5.2294,5.2727,5.3165",\ +"5.2502,5.2524,5.2624,5.2741,5.3174,5.3613",\ +"5.3175,5.3196,5.3297,5.3414,5.3847,5.4285"); + } + + rise_transition(SRAM_load_template) { + index_1("0.0008,0.0014,0.0051,0.0100,0.0339,0.0640"); + values ("0.0560,0.0583,0.0696,0.0816,0.1519,0.2335"); + } + fall_transition(SRAM_load_template) { + index_1("0.0008,0.0014,0.0051,0.0100,0.0339,0.0640"); + values ("0.0428,0.0445,0.0538,0.0658,0.1181,0.1751"); + } + } +} +cell_leakage_power : 953.1571; +} +} diff --git a/flow/platforms/ihp-sg13g2/lib/RM_IHPSG13_2P_256x32_c2_bm_bist_typ_1p20V_25C.lib b/flow/platforms/ihp-sg13g2/lib/RM_IHPSG13_2P_256x32_c2_bm_bist_typ_1p20V_25C.lib new file mode 100644 index 0000000000..aa1df71ebe --- /dev/null +++ b/flow/platforms/ihp-sg13g2/lib/RM_IHPSG13_2P_256x32_c2_bm_bist_typ_1p20V_25C.lib @@ -0,0 +1,2874 @@ +/* ------------------------------------------------------*/ +/**/ +/* Copyright 2025 IHP PDK Authors*/ +/**/ +/* Licensed under the Apache License, Version 2.0 (the "License");*/ +/* you may not use this file except in compliance with the License.*/ +/* You may obtain a copy of the License at*/ +/* */ +/* https://www.apache.org/licenses/LICENSE-2.0*/ +/* */ +/* Unless required by applicable law or agreed to in writing, software*/ +/* distributed under the License is distributed on an "AS IS" BASIS,*/ +/* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.*/ +/* See the License for the specific language governing permissions and*/ +/* limitations under the License.*/ +/* */ +/* Generated on Wed Aug 27 13:14:37 2025 */ +/* */ +/* ------------------------------------------------------ */ +library(RM_IHPSG13_2P_256x32_c2_bm_bist_typ_1p20V_25C) { + technology (cmos) ; + delay_model : table_lookup ; + define ("add_pg_pin_to_lib", "library", "boolean"); + add_pg_pin_to_lib : true; + voltage_map ( VDD, 1.20); + voltage_map ( VDDARRAY, 1.20); + voltage_map ( VSS, 0.000000 ); + + date : "Wed Aug 27 13:14:35 2025" ; + comment : "IHP Microelectronics GmbH, 2023" ; + revision : 1.0.0 ; + simulation : true ; + nom_process : 1 ; + nom_temperature : 25 ; + nom_voltage : 1.20 ; + + operating_conditions("typ_1p20V_25C"){ + process : 1 ; + temperature : 25 ; + voltage : 1.20 ; + tree_type : "balanced_tree" ; + } + + default_operating_conditions : typ_1p20V_25C ; + default_max_transition : 1.0 ; + default_fanout_load : 1.0 ; + default_inout_pin_cap : 0.0 ; + default_input_pin_cap : 0.0 ; + default_output_pin_cap : 0.0 ; + default_cell_leakage_power : 0.0 ; + default_leakage_power_density : 0.0 ; + + slew_lower_threshold_pct_rise : 30 ; + slew_upper_threshold_pct_rise : 70 ; + input_threshold_pct_fall : 50 ; + output_threshold_pct_fall : 50 ; + input_threshold_pct_rise : 50 ; + output_threshold_pct_rise : 50 ; + slew_lower_threshold_pct_fall : 30 ; + slew_upper_threshold_pct_fall : 70 ; + slew_derate_from_library : 0.5; + k_volt_cell_leakage_power : 0.0 ; + k_temp_cell_leakage_power : 0.0 ; + k_process_cell_leakage_power : 0.0 ; + k_volt_internal_power : 0.0 ; + k_temp_internal_power : 0.0 ; + k_process_internal_power : 0.0 ; + + capacitive_load_unit (1,pf) ; + voltage_unit : "1V" ; + current_unit : "1uA" ; + time_unit : "1ns" ; + leakage_power_unit : "1nW" ; + pulling_resistance_unit : "1kohm"; + /* + ------------------------------------------------------------------------------------------ + implicit units overview: + cell_area unit : "um" + internal_power unit : "1e-12 * J/toggle = 1 * uW/MHz" + (capacitive_load_unit * voltage_unit^2) per toggle event + ------------------------------------------------------------------------------------------ + */ + library_features(report_delay_calculation); + define_cell_area (pad_drivers,pad_driver_sites) ; + + lu_table_template(CLKTRAN_constraint_template) { + variable_1 : constrained_pin_transition; + index_1 ( "0.010, 0.050, 0.200, 0.400, 1.000" ); + } + lu_table_template(SRAM_load_template) { + variable_1 : total_output_net_capacitance; + index_1 ( "0.0008,0.0014,0.0051,0.0100,0.0339,0.0640" ); + } + lu_table_template(SIG2SRAM_constraint_template) { + variable_1 : related_pin_transition; + variable_2 : constrained_pin_transition; + index_1 ( "0.0056,0.0232,0.0400,0.0728,0.1280,0.2440,0.4760" ); + index_2 ( "0.0056,0.0232,0.0400,0.0728,0.1280,0.2440,0.4760" ); + } + + lu_table_template(SIG2SRAM_delay_template) { + variable_1 : input_net_transition; + variable_2 : total_output_net_capacitance; + index_1 ( "0.0056,0.0232,0.0400,0.0728,0.1280,0.2440,0.4760" ); + index_2 ( "0.0008,0.0014,0.0051,0.0100,0.0339,0.0640" ); + } + + type (D_31_0) { + base_type : array; + data_type : bit; + bit_width : 32; + bit_from : 31; + bit_to : 0; + downto : true; + } + + type (A_7_0) { + base_type : array; + data_type : bit; + bit_width : 8; + bit_from : 7; + bit_to : 0; + downto : true; + } + +cell(RM_IHPSG13_2P_256x32_c2_bm_bist) { +pg_pin (VDD) { + pg_type : primary_power; + voltage_name : VDD; +} +pg_pin (VDDARRAY) { + pg_type : primary_power; + voltage_name : VDDARRAY; +} +pg_pin (VSS) { + pg_type : primary_ground; + voltage_name : VSS; +} + +memory() { + type : ram; + address_width : 8; + word_width : 32; +} + +interface_timing : false; +bus_naming_style : "%s[%d]" ; +area : 96266.6251 ; + + pin(A_DLY) { + direction : input ; + capacitance : 0.00401111 ; + max_transition : "1" ; + related_power_pin : VDD; + related_ground_pin : VSS; + internal_power() { + rise_power("scalar") { + values (0); + } + fall_power("scalar") { + values (0); + } + } + } + +bus(A_ADDR) { + bus_type : A_7_0; + direction : input ; + capacitance : 0.0121077 ; + pin(A_ADDR[0]) { + capacitance : 0.00568653 ; + } + pin(A_ADDR[1]) { + capacitance : 0.00767263 ; + } + pin(A_ADDR[2]) { + capacitance : 0.0105079 ; + } + pin(A_ADDR[3]) { + capacitance : 0.0068178 ; + } + pin(A_ADDR[4]) { + capacitance : 0.00624497 ; + } + pin(A_ADDR[5]) { + capacitance : 0.0105871 ; + } + pin(A_ADDR[6]) { + capacitance : 0.0130817 ; + } + max_transition : "0.476" ; + pin(A_ADDR[7:0]) { + related_power_pin : VDD; + related_ground_pin : VSS; + internal_power() { + when : "A_MEN"; + rise_power("scalar"){ + values (0.0100); + } + fall_power("scalar"){ + values (0.0047); + } + } + internal_power() { + when : "!A_MEN"; + rise_power("scalar"){ + values (0.0183); + } + fall_power("scalar"){ + values (0.0010); + } + } + } + timing() { + timing_type : setup_rising; + related_pin : "A_CLK"; + when : "((A_WEN | A_REN)& A_MEN)" + sdf_cond : "A_RW_ACCESS" + + rise_constraint("SIG2SRAM_constraint_template") { + index_1("0.0056,0.0232,0.0400,0.0728,0.1280,0.2440,0.4760"); + index_2("0.0056,0.0232,0.0400,0.0728,0.1280,0.2440,0.4760"); + values ("-0.4168,-0.3973,-0.3855,-0.3543,-0.3074,-0.2020,-0.0027",\ +"-0.4324,-0.4129,-0.4012,-0.3699,-0.3191,-0.2176,-0.0184",\ +"-0.4441,-0.4285,-0.4129,-0.3816,-0.3309,-0.2293,-0.0301",\ +"-0.4793,-0.4598,-0.4441,-0.4129,-0.3660,-0.2645,-0.0652",\ +"-0.5223,-0.5066,-0.4910,-0.4598,-0.4129,-0.3074,-0.1121",\ +"-0.6199,-0.6082,-0.5926,-0.5613,-0.5145,-0.4129,-0.2137",\ +"-0.8191,-0.8074,-0.7840,-0.7566,-0.7098,-0.6082,-0.4051"); + } + + fall_constraint("SIG2SRAM_constraint_template") { + index_1("0.0056,0.0232,0.0400,0.0728,0.1280,0.2440,0.4760"); + index_2("0.0056,0.0232,0.0400,0.0728,0.1280,0.2440,0.4760"); + values ("-0.3309,-0.3113,-0.2996,-0.2684,-0.2176,-0.1238,0.0637",\ +"-0.3465,-0.3309,-0.3152,-0.2840,-0.2332,-0.1395,0.0480",\ +"-0.3582,-0.3426,-0.3270,-0.2996,-0.2488,-0.1512,0.0324",\ +"-0.3895,-0.3738,-0.3582,-0.3309,-0.2801,-0.1863,0.0051",\ +"-0.4363,-0.4207,-0.4051,-0.3777,-0.3230,-0.2293,-0.0379",\ +"-0.5379,-0.5223,-0.5066,-0.4793,-0.4285,-0.3309,-0.1434",\ +"-0.7332,-0.7176,-0.7020,-0.6746,-0.6238,-0.5262,-0.3387"); + } + } + + + timing() { + timing_type : hold_rising; + related_pin : "A_CLK"; + when : "((A_WEN | A_REN)& A_MEN)" + sdf_cond : "A_RW_ACCESS" + + rise_constraint("SIG2SRAM_constraint_template") { + index_1("0.0056,0.0232,0.0400,0.0728,0.1280,0.2440,0.4760"); + index_2("0.0056,0.0232,0.0400,0.0728,0.1280,0.2440,0.4760"); + values ("0.5246,0.5051,0.4895,0.4582,0.4113,0.3059,0.1066",\ +"0.5402,0.5207,0.5051,0.4777,0.4270,0.3215,0.1223",\ +"0.5520,0.5324,0.5168,0.4895,0.4387,0.3371,0.1340",\ +"0.5832,0.5676,0.5520,0.5207,0.4738,0.3684,0.1691",\ +"0.6301,0.6105,0.5949,0.5676,0.5168,0.4113,0.2160",\ +"0.7316,0.7121,0.7004,0.6691,0.6223,0.5168,0.3176",\ +"0.9270,0.9230,0.8957,0.8645,0.8137,0.7121,0.5168"); + } + + fall_constraint("SIG2SRAM_constraint_template") { + index_1("0.0056,0.0232,0.0400,0.0728,0.1280,0.2440,0.4760"); + index_2("0.0056,0.0232,0.0400,0.0728,0.1280,0.2440,0.4760"); + values ("0.4309,0.4152,0.4035,0.3684,0.3215,0.2277,0.0363",\ +"0.4465,0.4309,0.4152,0.3879,0.3371,0.2395,0.0559",\ +"0.4582,0.4426,0.4309,0.3996,0.3488,0.2551,0.0715",\ +"0.4934,0.4777,0.4621,0.4348,0.3840,0.2863,0.0988",\ +"0.5363,0.5207,0.5051,0.4777,0.4270,0.3332,0.1418",\ +"0.6379,0.6262,0.6105,0.5793,0.5324,0.4348,0.2434",\ +"0.8332,0.8215,0.8059,0.7707,0.7238,0.6301,0.4387"); + } + } +} +pin(A_WEN) { + direction : input ; + capacitance : 0.00324098 ; + max_transition : "0.476" ; + related_power_pin : VDD; + related_ground_pin : VSS; + internal_power() { + when : "A_MEN"; + rise_power("scalar"){ + values (0.0047); + } + fall_power("scalar"){ + values (0.0041); + } + } + internal_power() { + when : "!A_MEN"; + rise_power("scalar"){ + values (0.0045); + } + fall_power("scalar"){ + values (0.0043); + } + } + timing() { + timing_type : setup_rising; + related_pin : "A_CLK"; + when : "A_MEN" + sdf_cond : "A_MEN" + + rise_constraint("SIG2SRAM_constraint_template") { + index_1("0.0056,0.0232,0.0400,0.0728,0.1280,0.2440,0.4760"); + index_2("0.0056,0.0232,0.0400,0.0728,0.1280,0.2440,0.4760"); + values ("0.2043,0.2199,0.2316,0.2629,0.3059,0.4113,0.6066",\ +"0.1887,0.2043,0.2160,0.2473,0.2941,0.3957,0.5949",\ +"0.1691,0.1848,0.2004,0.2316,0.2785,0.3801,0.5754",\ +"0.1379,0.1574,0.1691,0.2004,0.2473,0.3527,0.5480",\ +"0.0910,0.1066,0.1223,0.1535,0.2004,0.2980,0.4973",\ +"-0.0105,0.0051,0.0207,0.0520,0.0949,0.2004,0.3957",\ +"-0.2059,-0.1902,-0.1746,-0.1473,-0.1004,0.0051,0.2004"); + } + + fall_constraint("SIG2SRAM_constraint_template") { + index_1("0.0056,0.0232,0.0400,0.0728,0.1280,0.2440,0.4760"); + index_2("0.0056,0.0232,0.0400,0.0728,0.1280,0.2440,0.4760"); + values ("0.2941,0.3098,0.3215,0.3488,0.4035,0.4973,0.6887",\ +"0.2785,0.2941,0.3059,0.3332,0.3840,0.4816,0.6691",\ +"0.2629,0.2785,0.2902,0.3176,0.3684,0.4660,0.6535",\ +"0.2316,0.2473,0.2590,0.2863,0.3410,0.4348,0.6262",\ +"0.1848,0.2004,0.2121,0.2395,0.2902,0.3879,0.5754",\ +"0.0832,0.0988,0.1105,0.1379,0.1809,0.2746,0.4699",\ +"-0.1121,-0.0965,-0.0848,-0.0535,-0.0066,0.0910,0.2824"); + } + } + + + timing() { + timing_type : hold_rising; + related_pin : "A_CLK"; + when : "A_MEN" + sdf_cond : "A_MEN" + + rise_constraint("SIG2SRAM_constraint_template") { + index_1("0.0056,0.0232,0.0400,0.0728,0.1280,0.2440,0.4760"); + index_2("0.0056,0.0232,0.0400,0.0728,0.1280,0.2440,0.4760"); + values ("0.2473,0.2316,0.2160,0.1887,0.1379,0.0363,-0.1629",\ +"0.2629,0.2473,0.2316,0.2043,0.1535,0.0520,-0.1473",\ +"0.2785,0.2590,0.2434,0.2160,0.1652,0.0676,-0.1355",\ +"0.3098,0.2941,0.2785,0.2473,0.1965,0.0910,-0.1043",\ +"0.3527,0.3371,0.3215,0.2941,0.2434,0.1418,-0.0574",\ +"0.4582,0.4426,0.4270,0.3957,0.3488,0.2434,0.0480",\ +"0.6535,0.6379,0.6184,0.5910,0.5402,0.4426,0.2434"); + } + + fall_constraint("SIG2SRAM_constraint_template") { + index_1("0.0056,0.0232,0.0400,0.0728,0.1280,0.2440,0.4760"); + index_2("0.0056,0.0232,0.0400,0.0728,0.1280,0.2440,0.4760"); + values ("0.2395,0.2238,0.2121,0.1809,0.1301,0.0324,-0.1551",\ +"0.2551,0.2395,0.2277,0.1965,0.1457,0.0480,-0.1395",\ +"0.2668,0.2551,0.2395,0.2082,0.1574,0.0637,-0.1277",\ +"0.3020,0.2863,0.2707,0.2395,0.1887,0.0910,-0.0965",\ +"0.3449,0.3293,0.3176,0.2863,0.2355,0.1379,-0.0496",\ +"0.4504,0.4348,0.4191,0.3879,0.3371,0.2395,0.0559",\ +"0.6457,0.6301,0.6145,0.5871,0.5324,0.4309,0.2512"); + } + } + } +pin(A_REN) { + direction : input ; + capacitance : 0.00381634 ; + max_transition : "0.476" ; + related_power_pin : VDD; + related_ground_pin : VSS; + internal_power() { + when : "A_MEN"; + rise_power("scalar"){ + values (0.0061); + } + fall_power("scalar"){ + values (0.0022); + } + } + internal_power() { + when : "!A_MEN"; + rise_power("scalar"){ + values (0.0063); + } + fall_power("scalar"){ + values (0.0027); + } + } + timing() { + timing_type : setup_rising; + related_pin : "A_CLK"; + when : "A_MEN" + sdf_cond : "A_MEN" + + rise_constraint("SIG2SRAM_constraint_template") { + index_1("0.0056,0.0232,0.0400,0.0728,0.1280,0.2440,0.4760"); + index_2("0.0056,0.0232,0.0400,0.0728,0.1280,0.2440,0.4760"); + values ("-0.0301,-0.0145,0.0012,0.0324,0.0793,0.1809,0.3762",\ +"-0.0457,-0.0301,-0.0145,0.0168,0.0637,0.1613,0.3605",\ +"-0.0574,-0.0418,-0.0262,0.0051,0.0520,0.1496,0.3449",\ +"-0.0926,-0.0730,-0.0574,-0.0262,0.0207,0.1184,0.3137",\ +"-0.1395,-0.1238,-0.1082,-0.0770,-0.0301,0.0715,0.2707",\ +"-0.2410,-0.2254,-0.2098,-0.1746,-0.1355,-0.0340,0.1652",\ +"-0.4402,-0.4207,-0.4051,-0.3738,-0.3270,-0.2293,-0.0340"); + } + + fall_constraint("SIG2SRAM_constraint_template") { + index_1("0.0056,0.0232,0.0400,0.0728,0.1280,0.2440,0.4760"); + index_2("0.0056,0.0232,0.0400,0.0728,0.1280,0.2440,0.4760"); + values ("0.0988,0.1145,0.1262,0.1535,0.2043,0.3020,0.4855",\ +"0.0832,0.0988,0.1105,0.1418,0.1848,0.2824,0.4738",\ +"0.0676,0.0832,0.0949,0.1262,0.1730,0.2668,0.4621",\ +"0.0402,0.0559,0.0676,0.0988,0.1457,0.2434,0.4191",\ +"-0.0105,0.0012,0.0168,0.0480,0.0988,0.1965,0.3840",\ +"-0.1160,-0.0965,-0.0848,-0.0535,-0.0066,0.0988,0.2824",\ +"-0.3113,-0.2957,-0.2801,-0.2527,-0.2059,-0.1043,0.0832"); + } + } + + + timing() { + timing_type : hold_rising; + related_pin : "A_CLK"; + when : "A_MEN" + sdf_cond : "A_MEN" + + rise_constraint("SIG2SRAM_constraint_template") { + index_1("0.0056,0.0232,0.0400,0.0728,0.1280,0.2440,0.4760"); + index_2("0.0056,0.0232,0.0400,0.0728,0.1280,0.2440,0.4760"); + values ("0.2707,0.2551,0.2395,0.2121,0.1613,0.0598,-0.1395",\ +"0.2863,0.2707,0.2551,0.2238,0.1730,0.0715,-0.1238",\ +"0.2980,0.2824,0.2668,0.2395,0.1887,0.0871,-0.1121",\ +"0.3332,0.3176,0.3020,0.2707,0.2199,0.1184,-0.0809",\ +"0.3762,0.3605,0.3449,0.3176,0.2668,0.1613,-0.0340",\ +"0.4816,0.4621,0.4504,0.4191,0.3723,0.2629,0.0715",\ +"0.6770,0.6613,0.6418,0.6184,0.5637,0.4699,0.2629"); + } + + fall_constraint("SIG2SRAM_constraint_template") { + index_1("0.0056,0.0232,0.0400,0.0728,0.1280,0.2440,0.4760"); + index_2("0.0056,0.0232,0.0400,0.0728,0.1280,0.2440,0.4760"); + values ("0.2590,0.2434,0.2316,0.2004,0.1457,0.0520,-0.1355",\ +"0.2746,0.2590,0.2434,0.2160,0.1613,0.0676,-0.1199",\ +"0.2863,0.2707,0.2590,0.2277,0.1730,0.0832,-0.1082",\ +"0.3215,0.3059,0.2902,0.2590,0.2082,0.1105,-0.0770",\ +"0.3645,0.3488,0.3332,0.3059,0.2551,0.1535,-0.0340",\ +"0.4699,0.4543,0.4387,0.4074,0.3605,0.2551,0.0715",\ +"0.6652,0.6496,0.6340,0.6027,0.5520,0.4621,0.2707"); + } + } + } +pin(A_MEN) { + direction : input ; + capacitance : 0.00309605 ; + max_transition : "0.476" ; + related_power_pin : VDD; + related_ground_pin : VSS; + internal_power() { + rise_power("scalar"){ + values (0.0870); + } + fall_power("scalar"){ + values (0.0053); + } + } + timing() { + timing_type : setup_rising; + related_pin : "A_CLK"; + + rise_constraint("SIG2SRAM_constraint_template") { + index_1("0.0056,0.0232,0.0400,0.0728,0.1280,0.2440,0.4760"); + index_2("0.0056,0.0232,0.0400,0.0728,0.1280,0.2440,0.4760"); + values ("0.2043,0.2199,0.2316,0.2668,0.3098,0.4152,0.6066",\ +"0.1887,0.2043,0.2199,0.2512,0.2941,0.3996,0.5949",\ +"0.1730,0.1887,0.2043,0.2355,0.2824,0.3840,0.5793",\ +"0.1418,0.1574,0.1730,0.2043,0.2512,0.3566,0.5480",\ +"0.0949,0.1105,0.1262,0.1574,0.2043,0.3020,0.5051",\ +"-0.0066,0.0090,0.0246,0.0520,0.0988,0.2043,0.3996",\ +"-0.2020,-0.1863,-0.1746,-0.1434,-0.0965,0.0090,0.2082"); + } + + fall_constraint("SIG2SRAM_constraint_template") { + index_1("0.0056,0.0232,0.0400,0.0728,0.1280,0.2440,0.4760"); + index_2("0.0056,0.0232,0.0400,0.0728,0.1280,0.2440,0.4760"); + values ("0.2980,0.3137,0.3254,0.3527,0.4035,0.5012,0.6887",\ +"0.2824,0.2980,0.3098,0.3371,0.3879,0.4855,0.6730",\ +"0.2668,0.2824,0.2941,0.3215,0.3723,0.4699,0.6574",\ +"0.2355,0.2473,0.2629,0.2902,0.3410,0.4387,0.6262",\ +"0.1887,0.2004,0.2160,0.2395,0.2941,0.3918,0.5793",\ +"0.0871,0.1027,0.1145,0.1418,0.1848,0.2746,0.4816",\ +"-0.1082,-0.0965,-0.0809,-0.0496,-0.0027,0.0949,0.2863"); + } + } + + + timing() { + timing_type : hold_rising; + related_pin : "A_CLK"; + + rise_constraint("SIG2SRAM_constraint_template") { + index_1("0.0056,0.0232,0.0400,0.0728,0.1280,0.2440,0.4760"); + index_2("0.0056,0.0232,0.0400,0.0728,0.1280,0.2440,0.4760"); + values ("0.2512,0.2355,0.2199,0.1926,0.1418,0.0402,-0.1590",\ +"0.2668,0.2512,0.2355,0.2082,0.1574,0.0559,-0.1434",\ +"0.2824,0.2629,0.2512,0.2199,0.1691,0.0715,-0.1316",\ +"0.3137,0.2980,0.2824,0.2512,0.2004,0.0988,-0.0965",\ +"0.3566,0.3410,0.3254,0.2980,0.2473,0.1418,-0.0535",\ +"0.4621,0.4426,0.4309,0.3996,0.3527,0.2473,0.0520",\ +"0.6574,0.6418,0.6262,0.5949,0.5441,0.4465,0.2473"); + } + + fall_constraint("SIG2SRAM_constraint_template") { + index_1("0.0056,0.0232,0.0400,0.0728,0.1280,0.2440,0.4760"); + index_2("0.0056,0.0232,0.0400,0.0728,0.1280,0.2440,0.4760"); + values ("0.2395,0.2238,0.2121,0.1809,0.1301,0.0324,-0.1551",\ +"0.2551,0.2434,0.2277,0.1965,0.1457,0.0480,-0.1395",\ +"0.2707,0.2551,0.2395,0.2082,0.1574,0.0637,-0.1277",\ +"0.3020,0.2863,0.2707,0.2434,0.1926,0.0910,-0.0965",\ +"0.3449,0.3332,0.3176,0.2863,0.2355,0.1379,-0.0496",\ +"0.4504,0.4348,0.4230,0.3918,0.3410,0.2434,0.0559",\ +"0.6457,0.6301,0.6145,0.5910,0.5324,0.4387,0.2512"); + } + } + } +bus(A_BM) { + bus_type : D_31_0; + direction : input ; + capacitance : 0.00372627 ; + max_transition : "0.476" ; + pin(A_BM[31:0]) { + related_power_pin : VDD; + related_ground_pin : VSS; + internal_power() { + when : "A_MEN"; + rise_power("scalar"){ + values (0.1176); + } + fall_power("scalar"){ + values (0.0493); + } + } + internal_power() { + when : "!A_MEN"; + rise_power("scalar"){ + values (0.1174); + } + fall_power("scalar"){ + values (0.0488); + } + } + } + timing() { + timing_type : setup_rising; + related_pin : "A_CLK"; + when : "(A_WEN & A_MEN)" + sdf_cond : "A_RW_ACCESS" + + rise_constraint("SIG2SRAM_constraint_template") { + index_1("0.0056,0.0232,0.0400,0.0728,0.1280,0.2440,0.4760"); + index_2("0.0056,0.0232,0.0400,0.0728,0.1280,0.2440,0.4760"); + values ("-0.3935,-0.3779,-0.3652,-0.3320,-0.2832,-0.1845,0.0088",\ +"-0.3985,-0.3829,-0.3702,-0.3370,-0.2882,-0.1895,0.0038",\ +"-0.4030,-0.3874,-0.3747,-0.3415,-0.2926,-0.1940,-0.0007",\ +"-0.4121,-0.3965,-0.3838,-0.3506,-0.3018,-0.2031,-0.0098",\ +"-0.4193,-0.4037,-0.3910,-0.3578,-0.3090,-0.2103,-0.0170",\ +"-0.4490,-0.4334,-0.4207,-0.3875,-0.3386,-0.2400,-0.0466",\ +"-0.5071,-0.4914,-0.4787,-0.4455,-0.3967,-0.2981,-0.1047"); + } + + fall_constraint("SIG2SRAM_constraint_template") { + index_1("0.0056,0.0232,0.0400,0.0728,0.1280,0.2440,0.4760"); + index_2("0.0056,0.0232,0.0400,0.0728,0.1280,0.2440,0.4760"); + values ("-0.3593,-0.3447,-0.3310,-0.3027,-0.2529,-0.1543,0.0254",\ +"-0.3643,-0.3497,-0.3360,-0.3077,-0.2579,-0.1593,0.0204",\ +"-0.3688,-0.3542,-0.3405,-0.3122,-0.2624,-0.1637,0.0159",\ +"-0.3779,-0.3633,-0.3496,-0.3213,-0.2715,-0.1729,0.0068",\ +"-0.3851,-0.3705,-0.3568,-0.3285,-0.2787,-0.1801,-0.0004",\ +"-0.4148,-0.4002,-0.3865,-0.3582,-0.3084,-0.2097,-0.0300",\ +"-0.4729,-0.4582,-0.4446,-0.4162,-0.3664,-0.2678,-0.0881"); + } + } + + + timing() { + timing_type : hold_rising; + related_pin : "A_CLK"; + when : "(A_WEN & A_MEN)" + sdf_cond : "A_RW_ACCESS" + + rise_constraint("SIG2SRAM_constraint_template") { + index_1("0.0056,0.0232,0.0400,0.0728,0.1280,0.2440,0.4760"); + index_2("0.0056,0.0232,0.0400,0.0728,0.1280,0.2440,0.4760"); + values ("0.5041,0.4885,0.4758,0.4426,0.3947,0.2951,0.1008",\ +"0.5091,0.4935,0.4808,0.4476,0.3997,0.3001,0.1058",\ +"0.5136,0.4980,0.4853,0.4521,0.4042,0.3046,0.1103",\ +"0.5227,0.5071,0.4944,0.4612,0.4133,0.3137,0.1194",\ +"0.5299,0.5143,0.5016,0.4684,0.4205,0.3209,0.1266",\ +"0.5596,0.5440,0.5313,0.4980,0.4502,0.3506,0.1563",\ +"0.6176,0.6020,0.5893,0.5561,0.5083,0.4087,0.2143"); + } + + fall_constraint("SIG2SRAM_constraint_template") { + index_1("0.0056,0.0232,0.0400,0.0728,0.1280,0.2440,0.4760"); + index_2("0.0056,0.0232,0.0400,0.0728,0.1280,0.2440,0.4760"); + values ("0.4631,0.4484,0.4338,0.4055,0.3547,0.2629,0.0783",\ +"0.4681,0.4534,0.4388,0.4105,0.3597,0.2679,0.0833",\ +"0.4726,0.4579,0.4433,0.4150,0.3642,0.2724,0.0878",\ +"0.4817,0.4671,0.4524,0.4241,0.3733,0.2815,0.0969",\ +"0.4889,0.4742,0.4596,0.4313,0.3805,0.2887,0.1041",\ +"0.5186,0.5039,0.4893,0.4609,0.4102,0.3184,0.1338",\ +"0.5766,0.5620,0.5473,0.5190,0.4682,0.3764,0.1919"); + } + } +} + pin(A_CLK) { + direction : input; + capacitance : 0.00380014; + max_transition : "0.476"; + clock : "true" ; + pin_func_type : active_rising ; + + timing () { + timing_type : "min_pulse_width"; + related_pin : "A_CLK"; + rise_constraint("CLKTRAN_constraint_template") { + index_1("0.0056,0.476"); + values("0.21,0.21"); + } + } + + related_power_pin : VDD; + related_ground_pin : VSS; + + internal_power() { + when : "!A_MEN & !A_WEN & !A_REN"; + rise_power("scalar"){ + values (0); + } + fall_power("scalar"){ + values (0); + } + } + internal_power() { + when : "!A_MEN & A_WEN & !A_REN"; + rise_power("scalar"){ + values (0.5036); + } + fall_power("scalar"){ + values (0); + } + } + internal_power() { + when : "A_MEN & A_WEN & !A_REN"; + rise_power("scalar"){ + values (33.4496); + } + fall_power("scalar"){ + values (0); + } + } + internal_power() { + when : "A_MEN & A_WEN & A_REN"; + rise_power("scalar"){ + values (37.7280); + } + fall_power("scalar"){ + values (0); + } + } + internal_power() { + when : "A_MEN & !A_WEN & A_REN"; + rise_power("scalar"){ + values (26.0060); + } + fall_power("scalar"){ + values (0); + } + } + internal_power() { + when : "!A_MEN & !A_WEN & A_REN"; + rise_power("scalar"){ + values (0.3024); + } + fall_power("scalar"){ + values (0); + } + } + internal_power() { + when : "!A_MEN & A_WEN & A_REN"; + rise_power("scalar"){ + values (1.1356); + } + fall_power("scalar"){ + values (0); + } + } + internal_power() { + when : "A_MEN & !A_WEN & !A_REN"; + rise_power("scalar"){ + values (0); + } + fall_power("scalar"){ + values (0); + } + } + } + bus(A_DIN) { + bus_type : D_31_0; + direction : input ; + capacitance : 0.00500744 ; + memory_write() { + address : A_ADDR ; + clocked_on : A_CLK; + } + + max_transition : "0.476" ; + pin(A_DIN[31:0]) { + related_power_pin : VDD; + related_ground_pin : VSS; + internal_power() { + when : "A_MEN"; + rise_power("scalar"){ + values (0.1176); + } + fall_power("scalar"){ + values (0.0493); + } + } + internal_power() { + when : "!A_MEN"; + rise_power("scalar"){ + values (0.1174); + } + fall_power("scalar"){ + values (0.0488); + } + } + } + timing() { + timing_type : setup_rising; + related_pin : "A_CLK"; + when : "(A_WEN & A_MEN)"; + sdf_cond : "A_W_ACCESS"; + + rise_constraint("SIG2SRAM_constraint_template") { + index_1("0.0056,0.0232,0.0400,0.0728,0.1280,0.2440,0.4760"); + index_2("0.0056,0.0232,0.0400,0.0728,0.1280,0.2440,0.4760"); + values ("-0.3935,-0.3779,-0.3652,-0.3320,-0.2832,-0.1845,0.0088",\ +"-0.3985,-0.3829,-0.3702,-0.3370,-0.2882,-0.1895,0.0038",\ +"-0.4030,-0.3874,-0.3747,-0.3415,-0.2926,-0.1940,-0.0007",\ +"-0.4121,-0.3965,-0.3838,-0.3506,-0.3018,-0.2031,-0.0098",\ +"-0.4193,-0.4037,-0.3910,-0.3578,-0.3090,-0.2103,-0.0170",\ +"-0.4490,-0.4334,-0.4207,-0.3875,-0.3386,-0.2400,-0.0466",\ +"-0.5071,-0.4914,-0.4787,-0.4455,-0.3967,-0.2981,-0.1047"); + } + + fall_constraint("SIG2SRAM_constraint_template") { + index_1("0.0056,0.0232,0.0400,0.0728,0.1280,0.2440,0.4760"); + index_2("0.0056,0.0232,0.0400,0.0728,0.1280,0.2440,0.4760"); + values ("-0.3593,-0.3447,-0.3310,-0.3027,-0.2529,-0.1543,0.0254",\ +"-0.3643,-0.3497,-0.3360,-0.3077,-0.2579,-0.1593,0.0204",\ +"-0.3688,-0.3542,-0.3405,-0.3122,-0.2624,-0.1637,0.0159",\ +"-0.3779,-0.3633,-0.3496,-0.3213,-0.2715,-0.1729,0.0068",\ +"-0.3851,-0.3705,-0.3568,-0.3285,-0.2787,-0.1801,-0.0004",\ +"-0.4148,-0.4002,-0.3865,-0.3582,-0.3084,-0.2097,-0.0300",\ +"-0.4729,-0.4582,-0.4446,-0.4162,-0.3664,-0.2678,-0.0881"); + } + } + + timing() { + timing_type : hold_rising; + related_pin : "A_CLK"; + when : "(A_WEN & A_MEN)"; + sdf_cond : "A_W_ACCESS"; + + rise_constraint("SIG2SRAM_constraint_template") { + index_1("0.0056,0.0232,0.0400,0.0728,0.1280,0.2440,0.4760"); + index_2("0.0056,0.0232,0.0400,0.0728,0.1280,0.2440,0.4760"); + values ("0.5041,0.4885,0.4758,0.4426,0.3947,0.2951,0.1008",\ +"0.5091,0.4935,0.4808,0.4476,0.3997,0.3001,0.1058",\ +"0.5136,0.4980,0.4853,0.4521,0.4042,0.3046,0.1103",\ +"0.5227,0.5071,0.4944,0.4612,0.4133,0.3137,0.1194",\ +"0.5299,0.5143,0.5016,0.4684,0.4205,0.3209,0.1266",\ +"0.5596,0.5440,0.5313,0.4980,0.4502,0.3506,0.1563",\ +"0.6176,0.6020,0.5893,0.5561,0.5083,0.4087,0.2143"); + } + + fall_constraint("SIG2SRAM_constraint_template") { + index_1("0.0056,0.0232,0.0400,0.0728,0.1280,0.2440,0.4760"); + index_2("0.0056,0.0232,0.0400,0.0728,0.1280,0.2440,0.4760"); + values ("0.4631,0.4484,0.4338,0.4055,0.3547,0.2629,0.0783",\ +"0.4681,0.4534,0.4388,0.4105,0.3597,0.2679,0.0833",\ +"0.4726,0.4579,0.4433,0.4150,0.3642,0.2724,0.0878",\ +"0.4817,0.4671,0.4524,0.4241,0.3733,0.2815,0.0969",\ +"0.4889,0.4742,0.4596,0.4313,0.3805,0.2887,0.1041",\ +"0.5186,0.5039,0.4893,0.4609,0.4102,0.3184,0.1338",\ +"0.5766,0.5620,0.5473,0.5190,0.4682,0.3764,0.1919"); + } + } + } + + pin(A_BIST_EN) { + direction : input ; + capacitance : 0.00401111 ; + max_transition : "1" ; + related_power_pin : VDD; + related_ground_pin : VSS; + internal_power() { + rise_power("scalar") { + values (0); + } + fall_power("scalar") { + values (0); + } + } + } + +bus(A_BIST_ADDR) { + bus_type : A_7_0; + direction : input ; + capacitance : 0.0121077 ; + pin(A_BIST_ADDR[0]) { + capacitance : 0.00568653 ; + } + pin(A_BIST_ADDR[1]) { + capacitance : 0.00767263 ; + } + pin(A_BIST_ADDR[2]) { + capacitance : 0.0105079 ; + } + pin(A_BIST_ADDR[3]) { + capacitance : 0.0068178 ; + } + pin(A_BIST_ADDR[4]) { + capacitance : 0.00624497 ; + } + pin(A_BIST_ADDR[5]) { + capacitance : 0.0105871 ; + } + pin(A_BIST_ADDR[6]) { + capacitance : 0.0130817 ; + } + max_transition : "0.476" ; + pin(A_BIST_ADDR[7:0]) { + related_power_pin : VDD; + related_ground_pin : VSS; + internal_power() { + when : "A_BIST_MEN"; + rise_power("scalar"){ + values (0.0100); + } + fall_power("scalar"){ + values (0.0047); + } + } + internal_power() { + when : "!A_BIST_MEN"; + rise_power("scalar"){ + values (0.0183); + } + fall_power("scalar"){ + values (0.0010); + } + } + } + timing() { + timing_type : setup_rising; + related_pin : "A_BIST_CLK"; + when : "((A_BIST_WEN | A_BIST_REN)& A_BIST_MEN)" + sdf_cond : "A_BIST_RW_ACCESS" + + rise_constraint("SIG2SRAM_constraint_template") { + index_1("0.0056,0.0232,0.0400,0.0728,0.1280,0.2440,0.4760"); + index_2("0.0056,0.0232,0.0400,0.0728,0.1280,0.2440,0.4760"); + values ("-0.4168,-0.3973,-0.3855,-0.3543,-0.3074,-0.2020,-0.0027",\ +"-0.4324,-0.4129,-0.4012,-0.3699,-0.3191,-0.2176,-0.0184",\ +"-0.4441,-0.4285,-0.4129,-0.3816,-0.3309,-0.2293,-0.0301",\ +"-0.4793,-0.4598,-0.4441,-0.4129,-0.3660,-0.2645,-0.0652",\ +"-0.5223,-0.5066,-0.4910,-0.4598,-0.4129,-0.3074,-0.1121",\ +"-0.6199,-0.6082,-0.5926,-0.5613,-0.5145,-0.4129,-0.2137",\ +"-0.8191,-0.8074,-0.7840,-0.7566,-0.7098,-0.6082,-0.4051"); + } + + fall_constraint("SIG2SRAM_constraint_template") { + index_1("0.0056,0.0232,0.0400,0.0728,0.1280,0.2440,0.4760"); + index_2("0.0056,0.0232,0.0400,0.0728,0.1280,0.2440,0.4760"); + values ("-0.3309,-0.3113,-0.2996,-0.2684,-0.2176,-0.1238,0.0637",\ +"-0.3465,-0.3309,-0.3152,-0.2840,-0.2332,-0.1395,0.0480",\ +"-0.3582,-0.3426,-0.3270,-0.2996,-0.2488,-0.1512,0.0324",\ +"-0.3895,-0.3738,-0.3582,-0.3309,-0.2801,-0.1863,0.0051",\ +"-0.4363,-0.4207,-0.4051,-0.3777,-0.3230,-0.2293,-0.0379",\ +"-0.5379,-0.5223,-0.5066,-0.4793,-0.4285,-0.3309,-0.1434",\ +"-0.7332,-0.7176,-0.7020,-0.6746,-0.6238,-0.5262,-0.3387"); + } + } + + + timing() { + timing_type : hold_rising; + related_pin : "A_BIST_CLK"; + when : "((A_BIST_WEN | A_BIST_REN)& A_BIST_MEN)" + sdf_cond : "A_BIST_RW_ACCESS" + + rise_constraint("SIG2SRAM_constraint_template") { + index_1("0.0056,0.0232,0.0400,0.0728,0.1280,0.2440,0.4760"); + index_2("0.0056,0.0232,0.0400,0.0728,0.1280,0.2440,0.4760"); + values ("0.5246,0.5051,0.4895,0.4582,0.4113,0.3059,0.1066",\ +"0.5402,0.5207,0.5051,0.4777,0.4270,0.3215,0.1223",\ +"0.5520,0.5324,0.5168,0.4895,0.4387,0.3371,0.1340",\ +"0.5832,0.5676,0.5520,0.5207,0.4738,0.3684,0.1691",\ +"0.6301,0.6105,0.5949,0.5676,0.5168,0.4113,0.2160",\ +"0.7316,0.7121,0.7004,0.6691,0.6223,0.5168,0.3176",\ +"0.9270,0.9230,0.8957,0.8645,0.8137,0.7121,0.5168"); + } + + fall_constraint("SIG2SRAM_constraint_template") { + index_1("0.0056,0.0232,0.0400,0.0728,0.1280,0.2440,0.4760"); + index_2("0.0056,0.0232,0.0400,0.0728,0.1280,0.2440,0.4760"); + values ("0.4309,0.4152,0.4035,0.3684,0.3215,0.2277,0.0363",\ +"0.4465,0.4309,0.4152,0.3879,0.3371,0.2395,0.0559",\ +"0.4582,0.4426,0.4309,0.3996,0.3488,0.2551,0.0715",\ +"0.4934,0.4777,0.4621,0.4348,0.3840,0.2863,0.0988",\ +"0.5363,0.5207,0.5051,0.4777,0.4270,0.3332,0.1418",\ +"0.6379,0.6262,0.6105,0.5793,0.5324,0.4348,0.2434",\ +"0.8332,0.8215,0.8059,0.7707,0.7238,0.6301,0.4387"); + } + } +} +pin(A_BIST_WEN) { + direction : input ; + capacitance : 0.00324098 ; + max_transition : "0.476" ; + related_power_pin : VDD; + related_ground_pin : VSS; + internal_power() { + when : "A_BIST_MEN"; + rise_power("scalar"){ + values (0.0047); + } + fall_power("scalar"){ + values (0.0041); + } + } + internal_power() { + when : "!A_BIST_MEN"; + rise_power("scalar"){ + values (0.0045); + } + fall_power("scalar"){ + values (0.0043); + } + } + timing() { + timing_type : setup_rising; + related_pin : "A_BIST_CLK"; + when : "A_BIST_MEN" + sdf_cond : "A_BIST_MEN" + + rise_constraint("SIG2SRAM_constraint_template") { + index_1("0.0056,0.0232,0.0400,0.0728,0.1280,0.2440,0.4760"); + index_2("0.0056,0.0232,0.0400,0.0728,0.1280,0.2440,0.4760"); + values ("0.2043,0.2199,0.2316,0.2629,0.3059,0.4113,0.6066",\ +"0.1887,0.2043,0.2160,0.2473,0.2941,0.3957,0.5949",\ +"0.1691,0.1848,0.2004,0.2316,0.2785,0.3801,0.5754",\ +"0.1379,0.1574,0.1691,0.2004,0.2473,0.3527,0.5480",\ +"0.0910,0.1066,0.1223,0.1535,0.2004,0.2980,0.4973",\ +"-0.0105,0.0051,0.0207,0.0520,0.0949,0.2004,0.3957",\ +"-0.2059,-0.1902,-0.1746,-0.1473,-0.1004,0.0051,0.2004"); + } + + fall_constraint("SIG2SRAM_constraint_template") { + index_1("0.0056,0.0232,0.0400,0.0728,0.1280,0.2440,0.4760"); + index_2("0.0056,0.0232,0.0400,0.0728,0.1280,0.2440,0.4760"); + values ("0.2941,0.3098,0.3215,0.3488,0.4035,0.4973,0.6887",\ +"0.2785,0.2941,0.3059,0.3332,0.3840,0.4816,0.6691",\ +"0.2629,0.2785,0.2902,0.3176,0.3684,0.4660,0.6535",\ +"0.2316,0.2473,0.2590,0.2863,0.3410,0.4348,0.6262",\ +"0.1848,0.2004,0.2121,0.2395,0.2902,0.3879,0.5754",\ +"0.0832,0.0988,0.1105,0.1379,0.1809,0.2746,0.4699",\ +"-0.1121,-0.0965,-0.0848,-0.0535,-0.0066,0.0910,0.2824"); + } + } + + + timing() { + timing_type : hold_rising; + related_pin : "A_BIST_CLK"; + when : "A_BIST_MEN" + sdf_cond : "A_BIST_MEN" + + rise_constraint("SIG2SRAM_constraint_template") { + index_1("0.0056,0.0232,0.0400,0.0728,0.1280,0.2440,0.4760"); + index_2("0.0056,0.0232,0.0400,0.0728,0.1280,0.2440,0.4760"); + values ("0.2473,0.2316,0.2160,0.1887,0.1379,0.0363,-0.1629",\ +"0.2629,0.2473,0.2316,0.2043,0.1535,0.0520,-0.1473",\ +"0.2785,0.2590,0.2434,0.2160,0.1652,0.0676,-0.1355",\ +"0.3098,0.2941,0.2785,0.2473,0.1965,0.0910,-0.1043",\ +"0.3527,0.3371,0.3215,0.2941,0.2434,0.1418,-0.0574",\ +"0.4582,0.4426,0.4270,0.3957,0.3488,0.2434,0.0480",\ +"0.6535,0.6379,0.6184,0.5910,0.5402,0.4426,0.2434"); + } + + fall_constraint("SIG2SRAM_constraint_template") { + index_1("0.0056,0.0232,0.0400,0.0728,0.1280,0.2440,0.4760"); + index_2("0.0056,0.0232,0.0400,0.0728,0.1280,0.2440,0.4760"); + values ("0.2395,0.2238,0.2121,0.1809,0.1301,0.0324,-0.1551",\ +"0.2551,0.2395,0.2277,0.1965,0.1457,0.0480,-0.1395",\ +"0.2668,0.2551,0.2395,0.2082,0.1574,0.0637,-0.1277",\ +"0.3020,0.2863,0.2707,0.2395,0.1887,0.0910,-0.0965",\ +"0.3449,0.3293,0.3176,0.2863,0.2355,0.1379,-0.0496",\ +"0.4504,0.4348,0.4191,0.3879,0.3371,0.2395,0.0559",\ +"0.6457,0.6301,0.6145,0.5871,0.5324,0.4309,0.2512"); + } + } + } +pin(A_BIST_REN) { + direction : input ; + capacitance : 0.00381634 ; + max_transition : "0.476" ; + related_power_pin : VDD; + related_ground_pin : VSS; + internal_power() { + when : "A_BIST_MEN"; + rise_power("scalar"){ + values (0.0061); + } + fall_power("scalar"){ + values (0.0022); + } + } + internal_power() { + when : "!A_BIST_MEN"; + rise_power("scalar"){ + values (0.0063); + } + fall_power("scalar"){ + values (0.0027); + } + } + timing() { + timing_type : setup_rising; + related_pin : "A_BIST_CLK"; + when : "A_BIST_MEN" + sdf_cond : "A_BIST_MEN" + + rise_constraint("SIG2SRAM_constraint_template") { + index_1("0.0056,0.0232,0.0400,0.0728,0.1280,0.2440,0.4760"); + index_2("0.0056,0.0232,0.0400,0.0728,0.1280,0.2440,0.4760"); + values ("-0.0301,-0.0145,0.0012,0.0324,0.0793,0.1809,0.3762",\ +"-0.0457,-0.0301,-0.0145,0.0168,0.0637,0.1613,0.3605",\ +"-0.0574,-0.0418,-0.0262,0.0051,0.0520,0.1496,0.3449",\ +"-0.0926,-0.0730,-0.0574,-0.0262,0.0207,0.1184,0.3137",\ +"-0.1395,-0.1238,-0.1082,-0.0770,-0.0301,0.0715,0.2707",\ +"-0.2410,-0.2254,-0.2098,-0.1746,-0.1355,-0.0340,0.1652",\ +"-0.4402,-0.4207,-0.4051,-0.3738,-0.3270,-0.2293,-0.0340"); + } + + fall_constraint("SIG2SRAM_constraint_template") { + index_1("0.0056,0.0232,0.0400,0.0728,0.1280,0.2440,0.4760"); + index_2("0.0056,0.0232,0.0400,0.0728,0.1280,0.2440,0.4760"); + values ("0.0988,0.1145,0.1262,0.1535,0.2043,0.3020,0.4855",\ +"0.0832,0.0988,0.1105,0.1418,0.1848,0.2824,0.4738",\ +"0.0676,0.0832,0.0949,0.1262,0.1730,0.2668,0.4621",\ +"0.0402,0.0559,0.0676,0.0988,0.1457,0.2434,0.4191",\ +"-0.0105,0.0012,0.0168,0.0480,0.0988,0.1965,0.3840",\ +"-0.1160,-0.0965,-0.0848,-0.0535,-0.0066,0.0988,0.2824",\ +"-0.3113,-0.2957,-0.2801,-0.2527,-0.2059,-0.1043,0.0832"); + } + } + + + timing() { + timing_type : hold_rising; + related_pin : "A_BIST_CLK"; + when : "A_BIST_MEN" + sdf_cond : "A_BIST_MEN" + + rise_constraint("SIG2SRAM_constraint_template") { + index_1("0.0056,0.0232,0.0400,0.0728,0.1280,0.2440,0.4760"); + index_2("0.0056,0.0232,0.0400,0.0728,0.1280,0.2440,0.4760"); + values ("0.2707,0.2551,0.2395,0.2121,0.1613,0.0598,-0.1395",\ +"0.2863,0.2707,0.2551,0.2238,0.1730,0.0715,-0.1238",\ +"0.2980,0.2824,0.2668,0.2395,0.1887,0.0871,-0.1121",\ +"0.3332,0.3176,0.3020,0.2707,0.2199,0.1184,-0.0809",\ +"0.3762,0.3605,0.3449,0.3176,0.2668,0.1613,-0.0340",\ +"0.4816,0.4621,0.4504,0.4191,0.3723,0.2629,0.0715",\ +"0.6770,0.6613,0.6418,0.6184,0.5637,0.4699,0.2629"); + } + + fall_constraint("SIG2SRAM_constraint_template") { + index_1("0.0056,0.0232,0.0400,0.0728,0.1280,0.2440,0.4760"); + index_2("0.0056,0.0232,0.0400,0.0728,0.1280,0.2440,0.4760"); + values ("0.2590,0.2434,0.2316,0.2004,0.1457,0.0520,-0.1355",\ +"0.2746,0.2590,0.2434,0.2160,0.1613,0.0676,-0.1199",\ +"0.2863,0.2707,0.2590,0.2277,0.1730,0.0832,-0.1082",\ +"0.3215,0.3059,0.2902,0.2590,0.2082,0.1105,-0.0770",\ +"0.3645,0.3488,0.3332,0.3059,0.2551,0.1535,-0.0340",\ +"0.4699,0.4543,0.4387,0.4074,0.3605,0.2551,0.0715",\ +"0.6652,0.6496,0.6340,0.6027,0.5520,0.4621,0.2707"); + } + } + } +pin(A_BIST_MEN) { + direction : input ; + capacitance : 0.00309605 ; + max_transition : "0.476" ; + related_power_pin : VDD; + related_ground_pin : VSS; + internal_power() { + rise_power("scalar"){ + values (0.0870); + } + fall_power("scalar"){ + values (0.0053); + } + } + timing() { + timing_type : setup_rising; + related_pin : "A_BIST_CLK"; + + rise_constraint("SIG2SRAM_constraint_template") { + index_1("0.0056,0.0232,0.0400,0.0728,0.1280,0.2440,0.4760"); + index_2("0.0056,0.0232,0.0400,0.0728,0.1280,0.2440,0.4760"); + values ("0.2043,0.2199,0.2316,0.2668,0.3098,0.4152,0.6066",\ +"0.1887,0.2043,0.2199,0.2512,0.2941,0.3996,0.5949",\ +"0.1730,0.1887,0.2043,0.2355,0.2824,0.3840,0.5793",\ +"0.1418,0.1574,0.1730,0.2043,0.2512,0.3566,0.5480",\ +"0.0949,0.1105,0.1262,0.1574,0.2043,0.3020,0.5051",\ +"-0.0066,0.0090,0.0246,0.0520,0.0988,0.2043,0.3996",\ +"-0.2020,-0.1863,-0.1746,-0.1434,-0.0965,0.0090,0.2082"); + } + + fall_constraint("SIG2SRAM_constraint_template") { + index_1("0.0056,0.0232,0.0400,0.0728,0.1280,0.2440,0.4760"); + index_2("0.0056,0.0232,0.0400,0.0728,0.1280,0.2440,0.4760"); + values ("0.2980,0.3137,0.3254,0.3527,0.4035,0.5012,0.6887",\ +"0.2824,0.2980,0.3098,0.3371,0.3879,0.4855,0.6730",\ +"0.2668,0.2824,0.2941,0.3215,0.3723,0.4699,0.6574",\ +"0.2355,0.2473,0.2629,0.2902,0.3410,0.4387,0.6262",\ +"0.1887,0.2004,0.2160,0.2395,0.2941,0.3918,0.5793",\ +"0.0871,0.1027,0.1145,0.1418,0.1848,0.2746,0.4816",\ +"-0.1082,-0.0965,-0.0809,-0.0496,-0.0027,0.0949,0.2863"); + } + } + + + timing() { + timing_type : hold_rising; + related_pin : "A_BIST_CLK"; + + rise_constraint("SIG2SRAM_constraint_template") { + index_1("0.0056,0.0232,0.0400,0.0728,0.1280,0.2440,0.4760"); + index_2("0.0056,0.0232,0.0400,0.0728,0.1280,0.2440,0.4760"); + values ("0.2512,0.2355,0.2199,0.1926,0.1418,0.0402,-0.1590",\ +"0.2668,0.2512,0.2355,0.2082,0.1574,0.0559,-0.1434",\ +"0.2824,0.2629,0.2512,0.2199,0.1691,0.0715,-0.1316",\ +"0.3137,0.2980,0.2824,0.2512,0.2004,0.0988,-0.0965",\ +"0.3566,0.3410,0.3254,0.2980,0.2473,0.1418,-0.0535",\ +"0.4621,0.4426,0.4309,0.3996,0.3527,0.2473,0.0520",\ +"0.6574,0.6418,0.6262,0.5949,0.5441,0.4465,0.2473"); + } + + fall_constraint("SIG2SRAM_constraint_template") { + index_1("0.0056,0.0232,0.0400,0.0728,0.1280,0.2440,0.4760"); + index_2("0.0056,0.0232,0.0400,0.0728,0.1280,0.2440,0.4760"); + values ("0.2395,0.2238,0.2121,0.1809,0.1301,0.0324,-0.1551",\ +"0.2551,0.2434,0.2277,0.1965,0.1457,0.0480,-0.1395",\ +"0.2707,0.2551,0.2395,0.2082,0.1574,0.0637,-0.1277",\ +"0.3020,0.2863,0.2707,0.2434,0.1926,0.0910,-0.0965",\ +"0.3449,0.3332,0.3176,0.2863,0.2355,0.1379,-0.0496",\ +"0.4504,0.4348,0.4230,0.3918,0.3410,0.2434,0.0559",\ +"0.6457,0.6301,0.6145,0.5910,0.5324,0.4387,0.2512"); + } + } + } +bus(A_BIST_BM) { + bus_type : D_31_0; + direction : input ; + capacitance : 0.00349377 ; + max_transition : "0.476" ; + pin(A_BIST_BM[31:0]) { + related_power_pin : VDD; + related_ground_pin : VSS; + internal_power() { + when : "A_BIST_MEN"; + rise_power("scalar"){ + values (0.1176); + } + fall_power("scalar"){ + values (0.0493); + } + } + internal_power() { + when : "!A_BIST_MEN"; + rise_power("scalar"){ + values (0.1174); + } + fall_power("scalar"){ + values (0.0488); + } + } + } + timing() { + timing_type : setup_rising; + related_pin : "A_BIST_CLK"; + when : "(A_BIST_WEN & A_BIST_MEN)" + sdf_cond : "A_BIST_RW_ACCESS" + + rise_constraint("SIG2SRAM_constraint_template") { + index_1("0.0056,0.0232,0.0400,0.0728,0.1280,0.2440,0.4760"); + index_2("0.0056,0.0232,0.0400,0.0728,0.1280,0.2440,0.4760"); + values ("-0.3935,-0.3779,-0.3652,-0.3320,-0.2832,-0.1845,0.0088",\ +"-0.3985,-0.3829,-0.3702,-0.3370,-0.2882,-0.1895,0.0038",\ +"-0.4030,-0.3874,-0.3747,-0.3415,-0.2926,-0.1940,-0.0007",\ +"-0.4121,-0.3965,-0.3838,-0.3506,-0.3018,-0.2031,-0.0098",\ +"-0.4193,-0.4037,-0.3910,-0.3578,-0.3090,-0.2103,-0.0170",\ +"-0.4490,-0.4334,-0.4207,-0.3875,-0.3386,-0.2400,-0.0466",\ +"-0.5071,-0.4914,-0.4787,-0.4455,-0.3967,-0.2981,-0.1047"); + } + + fall_constraint("SIG2SRAM_constraint_template") { + index_1("0.0056,0.0232,0.0400,0.0728,0.1280,0.2440,0.4760"); + index_2("0.0056,0.0232,0.0400,0.0728,0.1280,0.2440,0.4760"); + values ("-0.3593,-0.3447,-0.3310,-0.3027,-0.2529,-0.1543,0.0254",\ +"-0.3643,-0.3497,-0.3360,-0.3077,-0.2579,-0.1593,0.0204",\ +"-0.3688,-0.3542,-0.3405,-0.3122,-0.2624,-0.1637,0.0159",\ +"-0.3779,-0.3633,-0.3496,-0.3213,-0.2715,-0.1729,0.0068",\ +"-0.3851,-0.3705,-0.3568,-0.3285,-0.2787,-0.1801,-0.0004",\ +"-0.4148,-0.4002,-0.3865,-0.3582,-0.3084,-0.2097,-0.0300",\ +"-0.4729,-0.4582,-0.4446,-0.4162,-0.3664,-0.2678,-0.0881"); + } + } + + + timing() { + timing_type : hold_rising; + related_pin : "A_BIST_CLK"; + when : "(A_BIST_WEN & A_BIST_MEN)" + sdf_cond : "A_BIST_RW_ACCESS" + + rise_constraint("SIG2SRAM_constraint_template") { + index_1("0.0056,0.0232,0.0400,0.0728,0.1280,0.2440,0.4760"); + index_2("0.0056,0.0232,0.0400,0.0728,0.1280,0.2440,0.4760"); + values ("0.5041,0.4885,0.4758,0.4426,0.3947,0.2951,0.1008",\ +"0.5091,0.4935,0.4808,0.4476,0.3997,0.3001,0.1058",\ +"0.5136,0.4980,0.4853,0.4521,0.4042,0.3046,0.1103",\ +"0.5227,0.5071,0.4944,0.4612,0.4133,0.3137,0.1194",\ +"0.5299,0.5143,0.5016,0.4684,0.4205,0.3209,0.1266",\ +"0.5596,0.5440,0.5313,0.4980,0.4502,0.3506,0.1563",\ +"0.6176,0.6020,0.5893,0.5561,0.5083,0.4087,0.2143"); + } + + fall_constraint("SIG2SRAM_constraint_template") { + index_1("0.0056,0.0232,0.0400,0.0728,0.1280,0.2440,0.4760"); + index_2("0.0056,0.0232,0.0400,0.0728,0.1280,0.2440,0.4760"); + values ("0.4631,0.4484,0.4338,0.4055,0.3547,0.2629,0.0783",\ +"0.4681,0.4534,0.4388,0.4105,0.3597,0.2679,0.0833",\ +"0.4726,0.4579,0.4433,0.4150,0.3642,0.2724,0.0878",\ +"0.4817,0.4671,0.4524,0.4241,0.3733,0.2815,0.0969",\ +"0.4889,0.4742,0.4596,0.4313,0.3805,0.2887,0.1041",\ +"0.5186,0.5039,0.4893,0.4609,0.4102,0.3184,0.1338",\ +"0.5766,0.5620,0.5473,0.5190,0.4682,0.3764,0.1919"); + } + } +} + pin(A_BIST_CLK) { + direction : input; + capacitance : 0.00380014; + max_transition : "0.476"; + clock : "true" ; + pin_func_type : active_rising ; + + timing () { + timing_type : "min_pulse_width"; + related_pin : "A_BIST_CLK"; + rise_constraint("CLKTRAN_constraint_template") { + index_1("0.0056,0.476"); + values("0.21,0.21"); + } + } + + related_power_pin : VDD; + related_ground_pin : VSS; + + internal_power() { + when : "!A_BIST_MEN & !A_BIST_WEN & !A_BIST_REN"; + rise_power("scalar"){ + values (0); + } + fall_power("scalar"){ + values (0); + } + } + internal_power() { + when : "!A_BIST_MEN & A_BIST_WEN & !A_BIST_REN"; + rise_power("scalar"){ + values (0.5036); + } + fall_power("scalar"){ + values (0); + } + } + internal_power() { + when : "A_BIST_MEN & A_BIST_WEN & !A_BIST_REN"; + rise_power("scalar"){ + values (33.4496); + } + fall_power("scalar"){ + values (0); + } + } + internal_power() { + when : "A_BIST_MEN & A_BIST_WEN & A_BIST_REN"; + rise_power("scalar"){ + values (37.7280); + } + fall_power("scalar"){ + values (0); + } + } + internal_power() { + when : "A_BIST_MEN & !A_BIST_WEN & A_BIST_REN"; + rise_power("scalar"){ + values (26.0060); + } + fall_power("scalar"){ + values (0); + } + } + internal_power() { + when : "!A_BIST_MEN & !A_BIST_WEN & A_BIST_REN"; + rise_power("scalar"){ + values (0.3024); + } + fall_power("scalar"){ + values (0); + } + } + internal_power() { + when : "!A_BIST_MEN & A_BIST_WEN & A_BIST_REN"; + rise_power("scalar"){ + values (1.1356); + } + fall_power("scalar"){ + values (0); + } + } + internal_power() { + when : "A_BIST_MEN & !A_BIST_WEN & !A_BIST_REN"; + rise_power("scalar"){ + values (0); + } + fall_power("scalar"){ + values (0); + } + } + } + bus(A_BIST_DIN) { + bus_type : D_31_0; + direction : input ; + capacitance : 0.00393889 ; + memory_write() { + address : A_BIST_ADDR ; + clocked_on : A_BIST_CLK; + } + + max_transition : "0.476" ; + pin(A_BIST_DIN[31:0]) { + related_power_pin : VDD; + related_ground_pin : VSS; + internal_power() { + when : "A_BIST_MEN"; + rise_power("scalar"){ + values (0.1176); + } + fall_power("scalar"){ + values (0.0493); + } + } + internal_power() { + when : "!A_BIST_MEN"; + rise_power("scalar"){ + values (0.1174); + } + fall_power("scalar"){ + values (0.0488); + } + } + } + timing() { + timing_type : setup_rising; + related_pin : "A_BIST_CLK"; + when : "(A_BIST_WEN & A_BIST_MEN)"; + sdf_cond : "A_BIST_W_ACCESS"; + + rise_constraint("SIG2SRAM_constraint_template") { + index_1("0.0056,0.0232,0.0400,0.0728,0.1280,0.2440,0.4760"); + index_2("0.0056,0.0232,0.0400,0.0728,0.1280,0.2440,0.4760"); + values ("-0.3935,-0.3779,-0.3652,-0.3320,-0.2832,-0.1845,0.0088",\ +"-0.3985,-0.3829,-0.3702,-0.3370,-0.2882,-0.1895,0.0038",\ +"-0.4030,-0.3874,-0.3747,-0.3415,-0.2926,-0.1940,-0.0007",\ +"-0.4121,-0.3965,-0.3838,-0.3506,-0.3018,-0.2031,-0.0098",\ +"-0.4193,-0.4037,-0.3910,-0.3578,-0.3090,-0.2103,-0.0170",\ +"-0.4490,-0.4334,-0.4207,-0.3875,-0.3386,-0.2400,-0.0466",\ +"-0.5071,-0.4914,-0.4787,-0.4455,-0.3967,-0.2981,-0.1047"); + } + + fall_constraint("SIG2SRAM_constraint_template") { + index_1("0.0056,0.0232,0.0400,0.0728,0.1280,0.2440,0.4760"); + index_2("0.0056,0.0232,0.0400,0.0728,0.1280,0.2440,0.4760"); + values ("-0.3593,-0.3447,-0.3310,-0.3027,-0.2529,-0.1543,0.0254",\ +"-0.3643,-0.3497,-0.3360,-0.3077,-0.2579,-0.1593,0.0204",\ +"-0.3688,-0.3542,-0.3405,-0.3122,-0.2624,-0.1637,0.0159",\ +"-0.3779,-0.3633,-0.3496,-0.3213,-0.2715,-0.1729,0.0068",\ +"-0.3851,-0.3705,-0.3568,-0.3285,-0.2787,-0.1801,-0.0004",\ +"-0.4148,-0.4002,-0.3865,-0.3582,-0.3084,-0.2097,-0.0300",\ +"-0.4729,-0.4582,-0.4446,-0.4162,-0.3664,-0.2678,-0.0881"); + } + } + + timing() { + timing_type : hold_rising; + related_pin : "A_BIST_CLK"; + when : "(A_BIST_WEN & A_BIST_MEN)"; + sdf_cond : "A_BIST_W_ACCESS"; + + rise_constraint("SIG2SRAM_constraint_template") { + index_1("0.0056,0.0232,0.0400,0.0728,0.1280,0.2440,0.4760"); + index_2("0.0056,0.0232,0.0400,0.0728,0.1280,0.2440,0.4760"); + values ("0.5041,0.4885,0.4758,0.4426,0.3947,0.2951,0.1008",\ +"0.5091,0.4935,0.4808,0.4476,0.3997,0.3001,0.1058",\ +"0.5136,0.4980,0.4853,0.4521,0.4042,0.3046,0.1103",\ +"0.5227,0.5071,0.4944,0.4612,0.4133,0.3137,0.1194",\ +"0.5299,0.5143,0.5016,0.4684,0.4205,0.3209,0.1266",\ +"0.5596,0.5440,0.5313,0.4980,0.4502,0.3506,0.1563",\ +"0.6176,0.6020,0.5893,0.5561,0.5083,0.4087,0.2143"); + } + + fall_constraint("SIG2SRAM_constraint_template") { + index_1("0.0056,0.0232,0.0400,0.0728,0.1280,0.2440,0.4760"); + index_2("0.0056,0.0232,0.0400,0.0728,0.1280,0.2440,0.4760"); + values ("0.4631,0.4484,0.4338,0.4055,0.3547,0.2629,0.0783",\ +"0.4681,0.4534,0.4388,0.4105,0.3597,0.2679,0.0833",\ +"0.4726,0.4579,0.4433,0.4150,0.3642,0.2724,0.0878",\ +"0.4817,0.4671,0.4524,0.4241,0.3733,0.2815,0.0969",\ +"0.4889,0.4742,0.4596,0.4313,0.3805,0.2887,0.1041",\ +"0.5186,0.5039,0.4893,0.4609,0.4102,0.3184,0.1338",\ +"0.5766,0.5620,0.5473,0.5190,0.4682,0.3764,0.1919"); + } + } + } + +bus(A_DOUT) { + + bus_type : D_31_0; + direction : output ; + capacitance : 0 ; + max_capacitance : 0.064 ; + memory_read() { + address : A_ADDR ; + } + pin(A_DOUT[31:0]) { + related_power_pin : VDD; + related_ground_pin : VSS; + internal_power() { + rise_power("scalar") { + values (0); + } + fall_power("scalar") { + values (0); + } + } + } + timing() { + related_pin : "A_CLK"; + timing_type : rising_edge ; + timing_sense : non_unate ; + + cell_rise(SIG2SRAM_delay_template) { + index_1("0.0056,0.0232,0.0400,0.0728,0.1280,0.2440,0.4760"); + index_2("0.0008,0.0014,0.0051,0.0100,0.0339,0.0640"); + values ("3.0433,3.0449,3.0525,3.0613,3.0937,3.1298",\ +"3.0496,3.0513,3.0589,3.0676,3.1000,3.1361",\ +"3.0517,3.0534,3.0610,3.0697,3.1021,3.1382",\ +"3.0648,3.0664,3.0740,3.0828,3.1151,3.1513",\ +"3.0710,3.0726,3.0802,3.0890,3.1213,3.1575",\ +"3.1025,3.1041,3.1117,3.1204,3.1528,3.1890",\ +"3.1570,3.1586,3.1662,3.1749,3.2073,3.2435"); + } + cell_fall(SIG2SRAM_delay_template) { + index_1("0.0056,0.0232,0.0400,0.0728,0.1280,0.2440,0.4760"); + index_2("0.0008,0.0014,0.0051,0.0100,0.0339,0.0640"); + values ("2.9830,2.9844,2.9905,2.9976,3.0241,3.0503",\ +"2.9894,2.9907,2.9968,3.0039,3.0304,3.0566",\ +"2.9915,2.9928,2.9989,3.0060,3.0325,3.0587",\ +"3.0045,3.0059,3.0119,3.0191,3.0456,3.0718",\ +"3.0107,3.0121,3.0181,3.0253,3.0518,3.0780",\ +"3.0422,3.0435,3.0496,3.0567,3.0832,3.1095",\ +"3.0967,3.0980,3.1041,3.1112,3.1377,3.1640"); + } + + rise_transition(SRAM_load_template) { + index_1("0.0008,0.0014,0.0051,0.0100,0.0339,0.0640"); + values ("0.0326,0.0341,0.0428,0.0518,0.0923,0.1492"); + } + fall_transition(SRAM_load_template) { + index_1("0.0008,0.0014,0.0051,0.0100,0.0339,0.0640"); + values ("0.0254,0.0265,0.0335,0.0402,0.0707,0.1039"); + } + } +} + pin(B_DLY) { + direction : input ; + capacitance : 0.00401111 ; + max_transition : "1" ; + related_power_pin : VDD; + related_ground_pin : VSS; + internal_power() { + rise_power("scalar") { + values (0); + } + fall_power("scalar") { + values (0); + } + } + } + +bus(B_ADDR) { + bus_type : A_7_0; + direction : input ; + capacitance : 0.0121077 ; + pin(B_ADDR[0]) { + capacitance : 0.00570093 ; + } + pin(B_ADDR[1]) { + capacitance : 0.00764555 ; + } + pin(B_ADDR[2]) { + capacitance : 0.0105375 ; + } + pin(B_ADDR[3]) { + capacitance : 0.0067894 ; + } + pin(B_ADDR[4]) { + capacitance : 0.00630967 ; + } + pin(B_ADDR[5]) { + capacitance : 0.0104132 ; + } + pin(B_ADDR[6]) { + capacitance : 0.0131402 ; + } + max_transition : "0.476" ; + pin(B_ADDR[7:0]) { + related_power_pin : VDD; + related_ground_pin : VSS; + internal_power() { + when : "B_MEN"; + rise_power("scalar"){ + values (0.0100); + } + fall_power("scalar"){ + values (0.0047); + } + } + internal_power() { + when : "!B_MEN"; + rise_power("scalar"){ + values (0.0183); + } + fall_power("scalar"){ + values (0.0010); + } + } + } + timing() { + timing_type : setup_rising; + related_pin : "B_CLK"; + when : "((B_WEN | B_REN)& B_MEN)" + sdf_cond : "B_RW_ACCESS" + + rise_constraint("SIG2SRAM_constraint_template") { + index_1("0.0056,0.0232,0.0400,0.0728,0.1280,0.2440,0.4760"); + index_2("0.0056,0.0232,0.0400,0.0728,0.1280,0.2440,0.4760"); + values ("-0.4168,-0.3973,-0.3855,-0.3543,-0.3074,-0.2020,-0.0027",\ +"-0.4324,-0.4129,-0.4012,-0.3699,-0.3191,-0.2176,-0.0184",\ +"-0.4441,-0.4285,-0.4129,-0.3816,-0.3309,-0.2293,-0.0301",\ +"-0.4793,-0.4598,-0.4441,-0.4129,-0.3660,-0.2645,-0.0652",\ +"-0.5223,-0.5066,-0.4910,-0.4598,-0.4129,-0.3074,-0.1121",\ +"-0.6199,-0.6082,-0.5926,-0.5613,-0.5145,-0.4129,-0.2137",\ +"-0.8191,-0.8074,-0.7840,-0.7566,-0.7098,-0.6082,-0.4051"); + } + + fall_constraint("SIG2SRAM_constraint_template") { + index_1("0.0056,0.0232,0.0400,0.0728,0.1280,0.2440,0.4760"); + index_2("0.0056,0.0232,0.0400,0.0728,0.1280,0.2440,0.4760"); + values ("-0.3309,-0.3113,-0.2996,-0.2684,-0.2176,-0.1238,0.0637",\ +"-0.3465,-0.3309,-0.3152,-0.2840,-0.2332,-0.1395,0.0480",\ +"-0.3582,-0.3426,-0.3270,-0.2996,-0.2488,-0.1512,0.0324",\ +"-0.3895,-0.3738,-0.3582,-0.3309,-0.2801,-0.1863,0.0051",\ +"-0.4363,-0.4207,-0.4051,-0.3777,-0.3230,-0.2293,-0.0379",\ +"-0.5379,-0.5223,-0.5066,-0.4793,-0.4285,-0.3309,-0.1434",\ +"-0.7332,-0.7176,-0.7020,-0.6746,-0.6238,-0.5262,-0.3387"); + } + } + + + timing() { + timing_type : hold_rising; + related_pin : "B_CLK"; + when : "((B_WEN | B_REN)& B_MEN)" + sdf_cond : "B_RW_ACCESS" + + rise_constraint("SIG2SRAM_constraint_template") { + index_1("0.0056,0.0232,0.0400,0.0728,0.1280,0.2440,0.4760"); + index_2("0.0056,0.0232,0.0400,0.0728,0.1280,0.2440,0.4760"); + values ("0.5246,0.5051,0.4895,0.4582,0.4113,0.3059,0.1066",\ +"0.5402,0.5207,0.5051,0.4777,0.4270,0.3215,0.1223",\ +"0.5520,0.5324,0.5168,0.4895,0.4387,0.3371,0.1340",\ +"0.5832,0.5676,0.5520,0.5207,0.4738,0.3684,0.1691",\ +"0.6301,0.6105,0.5949,0.5676,0.5168,0.4113,0.2160",\ +"0.7316,0.7121,0.7004,0.6691,0.6223,0.5168,0.3176",\ +"0.9270,0.9230,0.8957,0.8645,0.8137,0.7121,0.5168"); + } + + fall_constraint("SIG2SRAM_constraint_template") { + index_1("0.0056,0.0232,0.0400,0.0728,0.1280,0.2440,0.4760"); + index_2("0.0056,0.0232,0.0400,0.0728,0.1280,0.2440,0.4760"); + values ("0.4309,0.4152,0.4035,0.3684,0.3215,0.2277,0.0363",\ +"0.4465,0.4309,0.4152,0.3879,0.3371,0.2395,0.0559",\ +"0.4582,0.4426,0.4309,0.3996,0.3488,0.2551,0.0715",\ +"0.4934,0.4777,0.4621,0.4348,0.3840,0.2863,0.0988",\ +"0.5363,0.5207,0.5051,0.4777,0.4270,0.3332,0.1418",\ +"0.6379,0.6262,0.6105,0.5793,0.5324,0.4348,0.2434",\ +"0.8332,0.8215,0.8059,0.7707,0.7238,0.6301,0.4387"); + } + } +} +pin(B_WEN) { + direction : input ; + capacitance : 0.00324098 ; + max_transition : "0.476" ; + related_power_pin : VDD; + related_ground_pin : VSS; + internal_power() { + when : "B_MEN"; + rise_power("scalar"){ + values (0.0047); + } + fall_power("scalar"){ + values (0.0041); + } + } + internal_power() { + when : "!B_MEN"; + rise_power("scalar"){ + values (0.0045); + } + fall_power("scalar"){ + values (0.0043); + } + } + timing() { + timing_type : setup_rising; + related_pin : "B_CLK"; + when : "B_MEN" + sdf_cond : "B_MEN" + + rise_constraint("SIG2SRAM_constraint_template") { + index_1("0.0056,0.0232,0.0400,0.0728,0.1280,0.2440,0.4760"); + index_2("0.0056,0.0232,0.0400,0.0728,0.1280,0.2440,0.4760"); + values ("0.2043,0.2199,0.2316,0.2629,0.3059,0.4113,0.6066",\ +"0.1887,0.2043,0.2160,0.2473,0.2941,0.3957,0.5949",\ +"0.1691,0.1848,0.2004,0.2316,0.2785,0.3801,0.5754",\ +"0.1379,0.1574,0.1691,0.2004,0.2473,0.3527,0.5480",\ +"0.0910,0.1066,0.1223,0.1535,0.2004,0.2980,0.4973",\ +"-0.0105,0.0051,0.0207,0.0520,0.0949,0.2004,0.3957",\ +"-0.2059,-0.1902,-0.1746,-0.1473,-0.1004,0.0051,0.2004"); + } + + fall_constraint("SIG2SRAM_constraint_template") { + index_1("0.0056,0.0232,0.0400,0.0728,0.1280,0.2440,0.4760"); + index_2("0.0056,0.0232,0.0400,0.0728,0.1280,0.2440,0.4760"); + values ("0.2941,0.3098,0.3215,0.3488,0.4035,0.4973,0.6887",\ +"0.2785,0.2941,0.3059,0.3332,0.3840,0.4816,0.6691",\ +"0.2629,0.2785,0.2902,0.3176,0.3684,0.4660,0.6535",\ +"0.2316,0.2473,0.2590,0.2863,0.3410,0.4348,0.6262",\ +"0.1848,0.2004,0.2121,0.2395,0.2902,0.3879,0.5754",\ +"0.0832,0.0988,0.1105,0.1379,0.1809,0.2746,0.4699",\ +"-0.1121,-0.0965,-0.0848,-0.0535,-0.0066,0.0910,0.2824"); + } + } + + + timing() { + timing_type : hold_rising; + related_pin : "B_CLK"; + when : "B_MEN" + sdf_cond : "B_MEN" + + rise_constraint("SIG2SRAM_constraint_template") { + index_1("0.0056,0.0232,0.0400,0.0728,0.1280,0.2440,0.4760"); + index_2("0.0056,0.0232,0.0400,0.0728,0.1280,0.2440,0.4760"); + values ("0.2473,0.2316,0.2160,0.1887,0.1379,0.0363,-0.1629",\ +"0.2629,0.2473,0.2316,0.2043,0.1535,0.0520,-0.1473",\ +"0.2785,0.2590,0.2434,0.2160,0.1652,0.0676,-0.1355",\ +"0.3098,0.2941,0.2785,0.2473,0.1965,0.0910,-0.1043",\ +"0.3527,0.3371,0.3215,0.2941,0.2434,0.1418,-0.0574",\ +"0.4582,0.4426,0.4270,0.3957,0.3488,0.2434,0.0480",\ +"0.6535,0.6379,0.6184,0.5910,0.5402,0.4426,0.2434"); + } + + fall_constraint("SIG2SRAM_constraint_template") { + index_1("0.0056,0.0232,0.0400,0.0728,0.1280,0.2440,0.4760"); + index_2("0.0056,0.0232,0.0400,0.0728,0.1280,0.2440,0.4760"); + values ("0.2395,0.2238,0.2121,0.1809,0.1301,0.0324,-0.1551",\ +"0.2551,0.2395,0.2277,0.1965,0.1457,0.0480,-0.1395",\ +"0.2668,0.2551,0.2395,0.2082,0.1574,0.0637,-0.1277",\ +"0.3020,0.2863,0.2707,0.2395,0.1887,0.0910,-0.0965",\ +"0.3449,0.3293,0.3176,0.2863,0.2355,0.1379,-0.0496",\ +"0.4504,0.4348,0.4191,0.3879,0.3371,0.2395,0.0559",\ +"0.6457,0.6301,0.6145,0.5871,0.5324,0.4309,0.2512"); + } + } + } +pin(B_REN) { + direction : input ; + capacitance : 0.00381634 ; + max_transition : "0.476" ; + related_power_pin : VDD; + related_ground_pin : VSS; + internal_power() { + when : "B_MEN"; + rise_power("scalar"){ + values (0.0061); + } + fall_power("scalar"){ + values (0.0022); + } + } + internal_power() { + when : "!B_MEN"; + rise_power("scalar"){ + values (0.0063); + } + fall_power("scalar"){ + values (0.0027); + } + } + timing() { + timing_type : setup_rising; + related_pin : "B_CLK"; + when : "B_MEN" + sdf_cond : "B_MEN" + + rise_constraint("SIG2SRAM_constraint_template") { + index_1("0.0056,0.0232,0.0400,0.0728,0.1280,0.2440,0.4760"); + index_2("0.0056,0.0232,0.0400,0.0728,0.1280,0.2440,0.4760"); + values ("-0.0301,-0.0145,0.0012,0.0324,0.0793,0.1809,0.3762",\ +"-0.0457,-0.0301,-0.0145,0.0168,0.0637,0.1613,0.3605",\ +"-0.0574,-0.0418,-0.0262,0.0051,0.0520,0.1496,0.3449",\ +"-0.0926,-0.0730,-0.0574,-0.0262,0.0207,0.1184,0.3137",\ +"-0.1395,-0.1238,-0.1082,-0.0770,-0.0301,0.0715,0.2707",\ +"-0.2410,-0.2254,-0.2098,-0.1746,-0.1355,-0.0340,0.1652",\ +"-0.4402,-0.4207,-0.4051,-0.3738,-0.3270,-0.2293,-0.0340"); + } + + fall_constraint("SIG2SRAM_constraint_template") { + index_1("0.0056,0.0232,0.0400,0.0728,0.1280,0.2440,0.4760"); + index_2("0.0056,0.0232,0.0400,0.0728,0.1280,0.2440,0.4760"); + values ("0.0988,0.1145,0.1262,0.1535,0.2043,0.3020,0.4855",\ +"0.0832,0.0988,0.1105,0.1418,0.1848,0.2824,0.4738",\ +"0.0676,0.0832,0.0949,0.1262,0.1730,0.2668,0.4621",\ +"0.0402,0.0559,0.0676,0.0988,0.1457,0.2434,0.4191",\ +"-0.0105,0.0012,0.0168,0.0480,0.0988,0.1965,0.3840",\ +"-0.1160,-0.0965,-0.0848,-0.0535,-0.0066,0.0988,0.2824",\ +"-0.3113,-0.2957,-0.2801,-0.2527,-0.2059,-0.1043,0.0832"); + } + } + + + timing() { + timing_type : hold_rising; + related_pin : "B_CLK"; + when : "B_MEN" + sdf_cond : "B_MEN" + + rise_constraint("SIG2SRAM_constraint_template") { + index_1("0.0056,0.0232,0.0400,0.0728,0.1280,0.2440,0.4760"); + index_2("0.0056,0.0232,0.0400,0.0728,0.1280,0.2440,0.4760"); + values ("0.2707,0.2551,0.2395,0.2121,0.1613,0.0598,-0.1395",\ +"0.2863,0.2707,0.2551,0.2238,0.1730,0.0715,-0.1238",\ +"0.2980,0.2824,0.2668,0.2395,0.1887,0.0871,-0.1121",\ +"0.3332,0.3176,0.3020,0.2707,0.2199,0.1184,-0.0809",\ +"0.3762,0.3605,0.3449,0.3176,0.2668,0.1613,-0.0340",\ +"0.4816,0.4621,0.4504,0.4191,0.3723,0.2629,0.0715",\ +"0.6770,0.6613,0.6418,0.6184,0.5637,0.4699,0.2629"); + } + + fall_constraint("SIG2SRAM_constraint_template") { + index_1("0.0056,0.0232,0.0400,0.0728,0.1280,0.2440,0.4760"); + index_2("0.0056,0.0232,0.0400,0.0728,0.1280,0.2440,0.4760"); + values ("0.2590,0.2434,0.2316,0.2004,0.1457,0.0520,-0.1355",\ +"0.2746,0.2590,0.2434,0.2160,0.1613,0.0676,-0.1199",\ +"0.2863,0.2707,0.2590,0.2277,0.1730,0.0832,-0.1082",\ +"0.3215,0.3059,0.2902,0.2590,0.2082,0.1105,-0.0770",\ +"0.3645,0.3488,0.3332,0.3059,0.2551,0.1535,-0.0340",\ +"0.4699,0.4543,0.4387,0.4074,0.3605,0.2551,0.0715",\ +"0.6652,0.6496,0.6340,0.6027,0.5520,0.4621,0.2707"); + } + } + } +pin(B_MEN) { + direction : input ; + capacitance : 0.00309605 ; + max_transition : "0.476" ; + related_power_pin : VDD; + related_ground_pin : VSS; + internal_power() { + rise_power("scalar"){ + values (0.0870); + } + fall_power("scalar"){ + values (0.0053); + } + } + timing() { + timing_type : setup_rising; + related_pin : "B_CLK"; + + rise_constraint("SIG2SRAM_constraint_template") { + index_1("0.0056,0.0232,0.0400,0.0728,0.1280,0.2440,0.4760"); + index_2("0.0056,0.0232,0.0400,0.0728,0.1280,0.2440,0.4760"); + values ("0.2043,0.2199,0.2316,0.2668,0.3098,0.4152,0.6066",\ +"0.1887,0.2043,0.2199,0.2512,0.2941,0.3996,0.5949",\ +"0.1730,0.1887,0.2043,0.2355,0.2824,0.3840,0.5793",\ +"0.1418,0.1574,0.1730,0.2043,0.2512,0.3566,0.5480",\ +"0.0949,0.1105,0.1262,0.1574,0.2043,0.3020,0.5051",\ +"-0.0066,0.0090,0.0246,0.0520,0.0988,0.2043,0.3996",\ +"-0.2020,-0.1863,-0.1746,-0.1434,-0.0965,0.0090,0.2082"); + } + + fall_constraint("SIG2SRAM_constraint_template") { + index_1("0.0056,0.0232,0.0400,0.0728,0.1280,0.2440,0.4760"); + index_2("0.0056,0.0232,0.0400,0.0728,0.1280,0.2440,0.4760"); + values ("0.2980,0.3137,0.3254,0.3527,0.4035,0.5012,0.6887",\ +"0.2824,0.2980,0.3098,0.3371,0.3879,0.4855,0.6730",\ +"0.2668,0.2824,0.2941,0.3215,0.3723,0.4699,0.6574",\ +"0.2355,0.2473,0.2629,0.2902,0.3410,0.4387,0.6262",\ +"0.1887,0.2004,0.2160,0.2395,0.2941,0.3918,0.5793",\ +"0.0871,0.1027,0.1145,0.1418,0.1848,0.2746,0.4816",\ +"-0.1082,-0.0965,-0.0809,-0.0496,-0.0027,0.0949,0.2863"); + } + } + + + timing() { + timing_type : hold_rising; + related_pin : "B_CLK"; + + rise_constraint("SIG2SRAM_constraint_template") { + index_1("0.0056,0.0232,0.0400,0.0728,0.1280,0.2440,0.4760"); + index_2("0.0056,0.0232,0.0400,0.0728,0.1280,0.2440,0.4760"); + values ("0.2512,0.2355,0.2199,0.1926,0.1418,0.0402,-0.1590",\ +"0.2668,0.2512,0.2355,0.2082,0.1574,0.0559,-0.1434",\ +"0.2824,0.2629,0.2512,0.2199,0.1691,0.0715,-0.1316",\ +"0.3137,0.2980,0.2824,0.2512,0.2004,0.0988,-0.0965",\ +"0.3566,0.3410,0.3254,0.2980,0.2473,0.1418,-0.0535",\ +"0.4621,0.4426,0.4309,0.3996,0.3527,0.2473,0.0520",\ +"0.6574,0.6418,0.6262,0.5949,0.5441,0.4465,0.2473"); + } + + fall_constraint("SIG2SRAM_constraint_template") { + index_1("0.0056,0.0232,0.0400,0.0728,0.1280,0.2440,0.4760"); + index_2("0.0056,0.0232,0.0400,0.0728,0.1280,0.2440,0.4760"); + values ("0.2395,0.2238,0.2121,0.1809,0.1301,0.0324,-0.1551",\ +"0.2551,0.2434,0.2277,0.1965,0.1457,0.0480,-0.1395",\ +"0.2707,0.2551,0.2395,0.2082,0.1574,0.0637,-0.1277",\ +"0.3020,0.2863,0.2707,0.2434,0.1926,0.0910,-0.0965",\ +"0.3449,0.3332,0.3176,0.2863,0.2355,0.1379,-0.0496",\ +"0.4504,0.4348,0.4230,0.3918,0.3410,0.2434,0.0559",\ +"0.6457,0.6301,0.6145,0.5910,0.5324,0.4387,0.2512"); + } + } + } +bus(B_BM) { + bus_type : D_31_0; + direction : input ; + capacitance : 0.00312518 ; + max_transition : "0.476" ; + pin(B_BM[31:0]) { + related_power_pin : VDD; + related_ground_pin : VSS; + internal_power() { + when : "B_MEN"; + rise_power("scalar"){ + values (0.1176); + } + fall_power("scalar"){ + values (0.0493); + } + } + internal_power() { + when : "!B_MEN"; + rise_power("scalar"){ + values (0.1174); + } + fall_power("scalar"){ + values (0.0488); + } + } + } + timing() { + timing_type : setup_rising; + related_pin : "B_CLK"; + when : "(B_WEN & B_MEN)" + sdf_cond : "B_RW_ACCESS" + + rise_constraint("SIG2SRAM_constraint_template") { + index_1("0.0056,0.0232,0.0400,0.0728,0.1280,0.2440,0.4760"); + index_2("0.0056,0.0232,0.0400,0.0728,0.1280,0.2440,0.4760"); + values ("-0.3935,-0.3779,-0.3652,-0.3320,-0.2832,-0.1845,0.0088",\ +"-0.3985,-0.3829,-0.3702,-0.3370,-0.2882,-0.1895,0.0038",\ +"-0.4030,-0.3874,-0.3747,-0.3415,-0.2926,-0.1940,-0.0007",\ +"-0.4121,-0.3965,-0.3838,-0.3506,-0.3018,-0.2031,-0.0098",\ +"-0.4193,-0.4037,-0.3910,-0.3578,-0.3090,-0.2103,-0.0170",\ +"-0.4490,-0.4334,-0.4207,-0.3875,-0.3386,-0.2400,-0.0466",\ +"-0.5071,-0.4914,-0.4787,-0.4455,-0.3967,-0.2981,-0.1047"); + } + + fall_constraint("SIG2SRAM_constraint_template") { + index_1("0.0056,0.0232,0.0400,0.0728,0.1280,0.2440,0.4760"); + index_2("0.0056,0.0232,0.0400,0.0728,0.1280,0.2440,0.4760"); + values ("-0.3593,-0.3447,-0.3310,-0.3027,-0.2529,-0.1543,0.0254",\ +"-0.3643,-0.3497,-0.3360,-0.3077,-0.2579,-0.1593,0.0204",\ +"-0.3688,-0.3542,-0.3405,-0.3122,-0.2624,-0.1637,0.0159",\ +"-0.3779,-0.3633,-0.3496,-0.3213,-0.2715,-0.1729,0.0068",\ +"-0.3851,-0.3705,-0.3568,-0.3285,-0.2787,-0.1801,-0.0004",\ +"-0.4148,-0.4002,-0.3865,-0.3582,-0.3084,-0.2097,-0.0300",\ +"-0.4729,-0.4582,-0.4446,-0.4162,-0.3664,-0.2678,-0.0881"); + } + } + + + timing() { + timing_type : hold_rising; + related_pin : "B_CLK"; + when : "(B_WEN & B_MEN)" + sdf_cond : "B_RW_ACCESS" + + rise_constraint("SIG2SRAM_constraint_template") { + index_1("0.0056,0.0232,0.0400,0.0728,0.1280,0.2440,0.4760"); + index_2("0.0056,0.0232,0.0400,0.0728,0.1280,0.2440,0.4760"); + values ("0.5041,0.4885,0.4758,0.4426,0.3947,0.2951,0.1008",\ +"0.5091,0.4935,0.4808,0.4476,0.3997,0.3001,0.1058",\ +"0.5136,0.4980,0.4853,0.4521,0.4042,0.3046,0.1103",\ +"0.5227,0.5071,0.4944,0.4612,0.4133,0.3137,0.1194",\ +"0.5299,0.5143,0.5016,0.4684,0.4205,0.3209,0.1266",\ +"0.5596,0.5440,0.5313,0.4980,0.4502,0.3506,0.1563",\ +"0.6176,0.6020,0.5893,0.5561,0.5083,0.4087,0.2143"); + } + + fall_constraint("SIG2SRAM_constraint_template") { + index_1("0.0056,0.0232,0.0400,0.0728,0.1280,0.2440,0.4760"); + index_2("0.0056,0.0232,0.0400,0.0728,0.1280,0.2440,0.4760"); + values ("0.4631,0.4484,0.4338,0.4055,0.3547,0.2629,0.0783",\ +"0.4681,0.4534,0.4388,0.4105,0.3597,0.2679,0.0833",\ +"0.4726,0.4579,0.4433,0.4150,0.3642,0.2724,0.0878",\ +"0.4817,0.4671,0.4524,0.4241,0.3733,0.2815,0.0969",\ +"0.4889,0.4742,0.4596,0.4313,0.3805,0.2887,0.1041",\ +"0.5186,0.5039,0.4893,0.4609,0.4102,0.3184,0.1338",\ +"0.5766,0.5620,0.5473,0.5190,0.4682,0.3764,0.1919"); + } + } +} + pin(B_CLK) { + direction : input; + capacitance : 0.00380014; + max_transition : "0.476"; + clock : "true" ; + pin_func_type : active_rising ; + + timing () { + timing_type : "min_pulse_width"; + related_pin : "B_CLK"; + rise_constraint("CLKTRAN_constraint_template") { + index_1("0.0056,0.476"); + values("0.21,0.21"); + } + } + + related_power_pin : VDD; + related_ground_pin : VSS; + + internal_power() { + when : "!B_MEN & !B_WEN & !B_REN"; + rise_power("scalar"){ + values (0); + } + fall_power("scalar"){ + values (0); + } + } + internal_power() { + when : "!B_MEN & B_WEN & !B_REN"; + rise_power("scalar"){ + values (0.5036); + } + fall_power("scalar"){ + values (0); + } + } + internal_power() { + when : "B_MEN & B_WEN & !B_REN"; + rise_power("scalar"){ + values (33.4496); + } + fall_power("scalar"){ + values (0); + } + } + internal_power() { + when : "B_MEN & B_WEN & B_REN"; + rise_power("scalar"){ + values (37.7280); + } + fall_power("scalar"){ + values (0); + } + } + internal_power() { + when : "B_MEN & !B_WEN & B_REN"; + rise_power("scalar"){ + values (26.0060); + } + fall_power("scalar"){ + values (0); + } + } + internal_power() { + when : "!B_MEN & !B_WEN & B_REN"; + rise_power("scalar"){ + values (0.3024); + } + fall_power("scalar"){ + values (0); + } + } + internal_power() { + when : "!B_MEN & B_WEN & B_REN"; + rise_power("scalar"){ + values (1.1356); + } + fall_power("scalar"){ + values (0); + } + } + internal_power() { + when : "B_MEN & !B_WEN & !B_REN"; + rise_power("scalar"){ + values (0); + } + fall_power("scalar"){ + values (0); + } + } + } + bus(B_DIN) { + bus_type : D_31_0; + direction : input ; + capacitance : 0.00461776 ; + memory_write() { + address : B_ADDR ; + clocked_on : B_CLK; + } + + max_transition : "0.476" ; + pin(B_DIN[31:0]) { + related_power_pin : VDD; + related_ground_pin : VSS; + internal_power() { + when : "B_MEN"; + rise_power("scalar"){ + values (0.1176); + } + fall_power("scalar"){ + values (0.0493); + } + } + internal_power() { + when : "!B_MEN"; + rise_power("scalar"){ + values (0.1174); + } + fall_power("scalar"){ + values (0.0488); + } + } + } + timing() { + timing_type : setup_rising; + related_pin : "B_CLK"; + when : "(B_WEN & B_MEN)"; + sdf_cond : "B_W_ACCESS"; + + rise_constraint("SIG2SRAM_constraint_template") { + index_1("0.0056,0.0232,0.0400,0.0728,0.1280,0.2440,0.4760"); + index_2("0.0056,0.0232,0.0400,0.0728,0.1280,0.2440,0.4760"); + values ("-0.3935,-0.3779,-0.3652,-0.3320,-0.2832,-0.1845,0.0088",\ +"-0.3985,-0.3829,-0.3702,-0.3370,-0.2882,-0.1895,0.0038",\ +"-0.4030,-0.3874,-0.3747,-0.3415,-0.2926,-0.1940,-0.0007",\ +"-0.4121,-0.3965,-0.3838,-0.3506,-0.3018,-0.2031,-0.0098",\ +"-0.4193,-0.4037,-0.3910,-0.3578,-0.3090,-0.2103,-0.0170",\ +"-0.4490,-0.4334,-0.4207,-0.3875,-0.3386,-0.2400,-0.0466",\ +"-0.5071,-0.4914,-0.4787,-0.4455,-0.3967,-0.2981,-0.1047"); + } + + fall_constraint("SIG2SRAM_constraint_template") { + index_1("0.0056,0.0232,0.0400,0.0728,0.1280,0.2440,0.4760"); + index_2("0.0056,0.0232,0.0400,0.0728,0.1280,0.2440,0.4760"); + values ("-0.3593,-0.3447,-0.3310,-0.3027,-0.2529,-0.1543,0.0254",\ +"-0.3643,-0.3497,-0.3360,-0.3077,-0.2579,-0.1593,0.0204",\ +"-0.3688,-0.3542,-0.3405,-0.3122,-0.2624,-0.1637,0.0159",\ +"-0.3779,-0.3633,-0.3496,-0.3213,-0.2715,-0.1729,0.0068",\ +"-0.3851,-0.3705,-0.3568,-0.3285,-0.2787,-0.1801,-0.0004",\ +"-0.4148,-0.4002,-0.3865,-0.3582,-0.3084,-0.2097,-0.0300",\ +"-0.4729,-0.4582,-0.4446,-0.4162,-0.3664,-0.2678,-0.0881"); + } + } + + timing() { + timing_type : hold_rising; + related_pin : "B_CLK"; + when : "(B_WEN & B_MEN)"; + sdf_cond : "B_W_ACCESS"; + + rise_constraint("SIG2SRAM_constraint_template") { + index_1("0.0056,0.0232,0.0400,0.0728,0.1280,0.2440,0.4760"); + index_2("0.0056,0.0232,0.0400,0.0728,0.1280,0.2440,0.4760"); + values ("0.5041,0.4885,0.4758,0.4426,0.3947,0.2951,0.1008",\ +"0.5091,0.4935,0.4808,0.4476,0.3997,0.3001,0.1058",\ +"0.5136,0.4980,0.4853,0.4521,0.4042,0.3046,0.1103",\ +"0.5227,0.5071,0.4944,0.4612,0.4133,0.3137,0.1194",\ +"0.5299,0.5143,0.5016,0.4684,0.4205,0.3209,0.1266",\ +"0.5596,0.5440,0.5313,0.4980,0.4502,0.3506,0.1563",\ +"0.6176,0.6020,0.5893,0.5561,0.5083,0.4087,0.2143"); + } + + fall_constraint("SIG2SRAM_constraint_template") { + index_1("0.0056,0.0232,0.0400,0.0728,0.1280,0.2440,0.4760"); + index_2("0.0056,0.0232,0.0400,0.0728,0.1280,0.2440,0.4760"); + values ("0.4631,0.4484,0.4338,0.4055,0.3547,0.2629,0.0783",\ +"0.4681,0.4534,0.4388,0.4105,0.3597,0.2679,0.0833",\ +"0.4726,0.4579,0.4433,0.4150,0.3642,0.2724,0.0878",\ +"0.4817,0.4671,0.4524,0.4241,0.3733,0.2815,0.0969",\ +"0.4889,0.4742,0.4596,0.4313,0.3805,0.2887,0.1041",\ +"0.5186,0.5039,0.4893,0.4609,0.4102,0.3184,0.1338",\ +"0.5766,0.5620,0.5473,0.5190,0.4682,0.3764,0.1919"); + } + } + } + + pin(B_BIST_EN) { + direction : input ; + capacitance : 0.00401111 ; + max_transition : "1" ; + related_power_pin : VDD; + related_ground_pin : VSS; + internal_power() { + rise_power("scalar") { + values (0); + } + fall_power("scalar") { + values (0); + } + } + } + +bus(B_BIST_ADDR) { + bus_type : A_7_0; + direction : input ; + capacitance : 0.0121077 ; + pin(B_BIST_ADDR[0]) { + capacitance : 0.00570093 ; + } + pin(B_BIST_ADDR[1]) { + capacitance : 0.00764555 ; + } + pin(B_BIST_ADDR[2]) { + capacitance : 0.0105375 ; + } + pin(B_BIST_ADDR[3]) { + capacitance : 0.0067894 ; + } + pin(B_BIST_ADDR[4]) { + capacitance : 0.00630967 ; + } + pin(B_BIST_ADDR[5]) { + capacitance : 0.0104132 ; + } + pin(B_BIST_ADDR[6]) { + capacitance : 0.0131402 ; + } + max_transition : "0.476" ; + pin(B_BIST_ADDR[7:0]) { + related_power_pin : VDD; + related_ground_pin : VSS; + internal_power() { + when : "B_BIST_MEN"; + rise_power("scalar"){ + values (0.0100); + } + fall_power("scalar"){ + values (0.0047); + } + } + internal_power() { + when : "!B_BIST_MEN"; + rise_power("scalar"){ + values (0.0183); + } + fall_power("scalar"){ + values (0.0010); + } + } + } + timing() { + timing_type : setup_rising; + related_pin : "B_BIST_CLK"; + when : "((B_BIST_WEN | B_BIST_REN)& B_BIST_MEN)" + sdf_cond : "B_BIST_RW_ACCESS" + + rise_constraint("SIG2SRAM_constraint_template") { + index_1("0.0056,0.0232,0.0400,0.0728,0.1280,0.2440,0.4760"); + index_2("0.0056,0.0232,0.0400,0.0728,0.1280,0.2440,0.4760"); + values ("-0.4168,-0.3973,-0.3855,-0.3543,-0.3074,-0.2020,-0.0027",\ +"-0.4324,-0.4129,-0.4012,-0.3699,-0.3191,-0.2176,-0.0184",\ +"-0.4441,-0.4285,-0.4129,-0.3816,-0.3309,-0.2293,-0.0301",\ +"-0.4793,-0.4598,-0.4441,-0.4129,-0.3660,-0.2645,-0.0652",\ +"-0.5223,-0.5066,-0.4910,-0.4598,-0.4129,-0.3074,-0.1121",\ +"-0.6199,-0.6082,-0.5926,-0.5613,-0.5145,-0.4129,-0.2137",\ +"-0.8191,-0.8074,-0.7840,-0.7566,-0.7098,-0.6082,-0.4051"); + } + + fall_constraint("SIG2SRAM_constraint_template") { + index_1("0.0056,0.0232,0.0400,0.0728,0.1280,0.2440,0.4760"); + index_2("0.0056,0.0232,0.0400,0.0728,0.1280,0.2440,0.4760"); + values ("-0.3309,-0.3113,-0.2996,-0.2684,-0.2176,-0.1238,0.0637",\ +"-0.3465,-0.3309,-0.3152,-0.2840,-0.2332,-0.1395,0.0480",\ +"-0.3582,-0.3426,-0.3270,-0.2996,-0.2488,-0.1512,0.0324",\ +"-0.3895,-0.3738,-0.3582,-0.3309,-0.2801,-0.1863,0.0051",\ +"-0.4363,-0.4207,-0.4051,-0.3777,-0.3230,-0.2293,-0.0379",\ +"-0.5379,-0.5223,-0.5066,-0.4793,-0.4285,-0.3309,-0.1434",\ +"-0.7332,-0.7176,-0.7020,-0.6746,-0.6238,-0.5262,-0.3387"); + } + } + + + timing() { + timing_type : hold_rising; + related_pin : "B_BIST_CLK"; + when : "((B_BIST_WEN | B_BIST_REN)& B_BIST_MEN)" + sdf_cond : "B_BIST_RW_ACCESS" + + rise_constraint("SIG2SRAM_constraint_template") { + index_1("0.0056,0.0232,0.0400,0.0728,0.1280,0.2440,0.4760"); + index_2("0.0056,0.0232,0.0400,0.0728,0.1280,0.2440,0.4760"); + values ("0.5246,0.5051,0.4895,0.4582,0.4113,0.3059,0.1066",\ +"0.5402,0.5207,0.5051,0.4777,0.4270,0.3215,0.1223",\ +"0.5520,0.5324,0.5168,0.4895,0.4387,0.3371,0.1340",\ +"0.5832,0.5676,0.5520,0.5207,0.4738,0.3684,0.1691",\ +"0.6301,0.6105,0.5949,0.5676,0.5168,0.4113,0.2160",\ +"0.7316,0.7121,0.7004,0.6691,0.6223,0.5168,0.3176",\ +"0.9270,0.9230,0.8957,0.8645,0.8137,0.7121,0.5168"); + } + + fall_constraint("SIG2SRAM_constraint_template") { + index_1("0.0056,0.0232,0.0400,0.0728,0.1280,0.2440,0.4760"); + index_2("0.0056,0.0232,0.0400,0.0728,0.1280,0.2440,0.4760"); + values ("0.4309,0.4152,0.4035,0.3684,0.3215,0.2277,0.0363",\ +"0.4465,0.4309,0.4152,0.3879,0.3371,0.2395,0.0559",\ +"0.4582,0.4426,0.4309,0.3996,0.3488,0.2551,0.0715",\ +"0.4934,0.4777,0.4621,0.4348,0.3840,0.2863,0.0988",\ +"0.5363,0.5207,0.5051,0.4777,0.4270,0.3332,0.1418",\ +"0.6379,0.6262,0.6105,0.5793,0.5324,0.4348,0.2434",\ +"0.8332,0.8215,0.8059,0.7707,0.7238,0.6301,0.4387"); + } + } +} +pin(B_BIST_WEN) { + direction : input ; + capacitance : 0.00324098 ; + max_transition : "0.476" ; + related_power_pin : VDD; + related_ground_pin : VSS; + internal_power() { + when : "B_BIST_MEN"; + rise_power("scalar"){ + values (0.0047); + } + fall_power("scalar"){ + values (0.0041); + } + } + internal_power() { + when : "!B_BIST_MEN"; + rise_power("scalar"){ + values (0.0045); + } + fall_power("scalar"){ + values (0.0043); + } + } + timing() { + timing_type : setup_rising; + related_pin : "B_BIST_CLK"; + when : "B_BIST_MEN" + sdf_cond : "B_BIST_MEN" + + rise_constraint("SIG2SRAM_constraint_template") { + index_1("0.0056,0.0232,0.0400,0.0728,0.1280,0.2440,0.4760"); + index_2("0.0056,0.0232,0.0400,0.0728,0.1280,0.2440,0.4760"); + values ("0.2043,0.2199,0.2316,0.2629,0.3059,0.4113,0.6066",\ +"0.1887,0.2043,0.2160,0.2473,0.2941,0.3957,0.5949",\ +"0.1691,0.1848,0.2004,0.2316,0.2785,0.3801,0.5754",\ +"0.1379,0.1574,0.1691,0.2004,0.2473,0.3527,0.5480",\ +"0.0910,0.1066,0.1223,0.1535,0.2004,0.2980,0.4973",\ +"-0.0105,0.0051,0.0207,0.0520,0.0949,0.2004,0.3957",\ +"-0.2059,-0.1902,-0.1746,-0.1473,-0.1004,0.0051,0.2004"); + } + + fall_constraint("SIG2SRAM_constraint_template") { + index_1("0.0056,0.0232,0.0400,0.0728,0.1280,0.2440,0.4760"); + index_2("0.0056,0.0232,0.0400,0.0728,0.1280,0.2440,0.4760"); + values ("0.2941,0.3098,0.3215,0.3488,0.4035,0.4973,0.6887",\ +"0.2785,0.2941,0.3059,0.3332,0.3840,0.4816,0.6691",\ +"0.2629,0.2785,0.2902,0.3176,0.3684,0.4660,0.6535",\ +"0.2316,0.2473,0.2590,0.2863,0.3410,0.4348,0.6262",\ +"0.1848,0.2004,0.2121,0.2395,0.2902,0.3879,0.5754",\ +"0.0832,0.0988,0.1105,0.1379,0.1809,0.2746,0.4699",\ +"-0.1121,-0.0965,-0.0848,-0.0535,-0.0066,0.0910,0.2824"); + } + } + + + timing() { + timing_type : hold_rising; + related_pin : "B_BIST_CLK"; + when : "B_BIST_MEN" + sdf_cond : "B_BIST_MEN" + + rise_constraint("SIG2SRAM_constraint_template") { + index_1("0.0056,0.0232,0.0400,0.0728,0.1280,0.2440,0.4760"); + index_2("0.0056,0.0232,0.0400,0.0728,0.1280,0.2440,0.4760"); + values ("0.2473,0.2316,0.2160,0.1887,0.1379,0.0363,-0.1629",\ +"0.2629,0.2473,0.2316,0.2043,0.1535,0.0520,-0.1473",\ +"0.2785,0.2590,0.2434,0.2160,0.1652,0.0676,-0.1355",\ +"0.3098,0.2941,0.2785,0.2473,0.1965,0.0910,-0.1043",\ +"0.3527,0.3371,0.3215,0.2941,0.2434,0.1418,-0.0574",\ +"0.4582,0.4426,0.4270,0.3957,0.3488,0.2434,0.0480",\ +"0.6535,0.6379,0.6184,0.5910,0.5402,0.4426,0.2434"); + } + + fall_constraint("SIG2SRAM_constraint_template") { + index_1("0.0056,0.0232,0.0400,0.0728,0.1280,0.2440,0.4760"); + index_2("0.0056,0.0232,0.0400,0.0728,0.1280,0.2440,0.4760"); + values ("0.2395,0.2238,0.2121,0.1809,0.1301,0.0324,-0.1551",\ +"0.2551,0.2395,0.2277,0.1965,0.1457,0.0480,-0.1395",\ +"0.2668,0.2551,0.2395,0.2082,0.1574,0.0637,-0.1277",\ +"0.3020,0.2863,0.2707,0.2395,0.1887,0.0910,-0.0965",\ +"0.3449,0.3293,0.3176,0.2863,0.2355,0.1379,-0.0496",\ +"0.4504,0.4348,0.4191,0.3879,0.3371,0.2395,0.0559",\ +"0.6457,0.6301,0.6145,0.5871,0.5324,0.4309,0.2512"); + } + } + } +pin(B_BIST_REN) { + direction : input ; + capacitance : 0.00381634 ; + max_transition : "0.476" ; + related_power_pin : VDD; + related_ground_pin : VSS; + internal_power() { + when : "B_BIST_MEN"; + rise_power("scalar"){ + values (0.0061); + } + fall_power("scalar"){ + values (0.0022); + } + } + internal_power() { + when : "!B_BIST_MEN"; + rise_power("scalar"){ + values (0.0063); + } + fall_power("scalar"){ + values (0.0027); + } + } + timing() { + timing_type : setup_rising; + related_pin : "B_BIST_CLK"; + when : "B_BIST_MEN" + sdf_cond : "B_BIST_MEN" + + rise_constraint("SIG2SRAM_constraint_template") { + index_1("0.0056,0.0232,0.0400,0.0728,0.1280,0.2440,0.4760"); + index_2("0.0056,0.0232,0.0400,0.0728,0.1280,0.2440,0.4760"); + values ("-0.0301,-0.0145,0.0012,0.0324,0.0793,0.1809,0.3762",\ +"-0.0457,-0.0301,-0.0145,0.0168,0.0637,0.1613,0.3605",\ +"-0.0574,-0.0418,-0.0262,0.0051,0.0520,0.1496,0.3449",\ +"-0.0926,-0.0730,-0.0574,-0.0262,0.0207,0.1184,0.3137",\ +"-0.1395,-0.1238,-0.1082,-0.0770,-0.0301,0.0715,0.2707",\ +"-0.2410,-0.2254,-0.2098,-0.1746,-0.1355,-0.0340,0.1652",\ +"-0.4402,-0.4207,-0.4051,-0.3738,-0.3270,-0.2293,-0.0340"); + } + + fall_constraint("SIG2SRAM_constraint_template") { + index_1("0.0056,0.0232,0.0400,0.0728,0.1280,0.2440,0.4760"); + index_2("0.0056,0.0232,0.0400,0.0728,0.1280,0.2440,0.4760"); + values ("0.0988,0.1145,0.1262,0.1535,0.2043,0.3020,0.4855",\ +"0.0832,0.0988,0.1105,0.1418,0.1848,0.2824,0.4738",\ +"0.0676,0.0832,0.0949,0.1262,0.1730,0.2668,0.4621",\ +"0.0402,0.0559,0.0676,0.0988,0.1457,0.2434,0.4191",\ +"-0.0105,0.0012,0.0168,0.0480,0.0988,0.1965,0.3840",\ +"-0.1160,-0.0965,-0.0848,-0.0535,-0.0066,0.0988,0.2824",\ +"-0.3113,-0.2957,-0.2801,-0.2527,-0.2059,-0.1043,0.0832"); + } + } + + + timing() { + timing_type : hold_rising; + related_pin : "B_BIST_CLK"; + when : "B_BIST_MEN" + sdf_cond : "B_BIST_MEN" + + rise_constraint("SIG2SRAM_constraint_template") { + index_1("0.0056,0.0232,0.0400,0.0728,0.1280,0.2440,0.4760"); + index_2("0.0056,0.0232,0.0400,0.0728,0.1280,0.2440,0.4760"); + values ("0.2707,0.2551,0.2395,0.2121,0.1613,0.0598,-0.1395",\ +"0.2863,0.2707,0.2551,0.2238,0.1730,0.0715,-0.1238",\ +"0.2980,0.2824,0.2668,0.2395,0.1887,0.0871,-0.1121",\ +"0.3332,0.3176,0.3020,0.2707,0.2199,0.1184,-0.0809",\ +"0.3762,0.3605,0.3449,0.3176,0.2668,0.1613,-0.0340",\ +"0.4816,0.4621,0.4504,0.4191,0.3723,0.2629,0.0715",\ +"0.6770,0.6613,0.6418,0.6184,0.5637,0.4699,0.2629"); + } + + fall_constraint("SIG2SRAM_constraint_template") { + index_1("0.0056,0.0232,0.0400,0.0728,0.1280,0.2440,0.4760"); + index_2("0.0056,0.0232,0.0400,0.0728,0.1280,0.2440,0.4760"); + values ("0.2590,0.2434,0.2316,0.2004,0.1457,0.0520,-0.1355",\ +"0.2746,0.2590,0.2434,0.2160,0.1613,0.0676,-0.1199",\ +"0.2863,0.2707,0.2590,0.2277,0.1730,0.0832,-0.1082",\ +"0.3215,0.3059,0.2902,0.2590,0.2082,0.1105,-0.0770",\ +"0.3645,0.3488,0.3332,0.3059,0.2551,0.1535,-0.0340",\ +"0.4699,0.4543,0.4387,0.4074,0.3605,0.2551,0.0715",\ +"0.6652,0.6496,0.6340,0.6027,0.5520,0.4621,0.2707"); + } + } + } +pin(B_BIST_MEN) { + direction : input ; + capacitance : 0.00309605 ; + max_transition : "0.476" ; + related_power_pin : VDD; + related_ground_pin : VSS; + internal_power() { + rise_power("scalar"){ + values (0.0870); + } + fall_power("scalar"){ + values (0.0053); + } + } + timing() { + timing_type : setup_rising; + related_pin : "B_BIST_CLK"; + + rise_constraint("SIG2SRAM_constraint_template") { + index_1("0.0056,0.0232,0.0400,0.0728,0.1280,0.2440,0.4760"); + index_2("0.0056,0.0232,0.0400,0.0728,0.1280,0.2440,0.4760"); + values ("0.2043,0.2199,0.2316,0.2668,0.3098,0.4152,0.6066",\ +"0.1887,0.2043,0.2199,0.2512,0.2941,0.3996,0.5949",\ +"0.1730,0.1887,0.2043,0.2355,0.2824,0.3840,0.5793",\ +"0.1418,0.1574,0.1730,0.2043,0.2512,0.3566,0.5480",\ +"0.0949,0.1105,0.1262,0.1574,0.2043,0.3020,0.5051",\ +"-0.0066,0.0090,0.0246,0.0520,0.0988,0.2043,0.3996",\ +"-0.2020,-0.1863,-0.1746,-0.1434,-0.0965,0.0090,0.2082"); + } + + fall_constraint("SIG2SRAM_constraint_template") { + index_1("0.0056,0.0232,0.0400,0.0728,0.1280,0.2440,0.4760"); + index_2("0.0056,0.0232,0.0400,0.0728,0.1280,0.2440,0.4760"); + values ("0.2980,0.3137,0.3254,0.3527,0.4035,0.5012,0.6887",\ +"0.2824,0.2980,0.3098,0.3371,0.3879,0.4855,0.6730",\ +"0.2668,0.2824,0.2941,0.3215,0.3723,0.4699,0.6574",\ +"0.2355,0.2473,0.2629,0.2902,0.3410,0.4387,0.6262",\ +"0.1887,0.2004,0.2160,0.2395,0.2941,0.3918,0.5793",\ +"0.0871,0.1027,0.1145,0.1418,0.1848,0.2746,0.4816",\ +"-0.1082,-0.0965,-0.0809,-0.0496,-0.0027,0.0949,0.2863"); + } + } + + + timing() { + timing_type : hold_rising; + related_pin : "B_BIST_CLK"; + + rise_constraint("SIG2SRAM_constraint_template") { + index_1("0.0056,0.0232,0.0400,0.0728,0.1280,0.2440,0.4760"); + index_2("0.0056,0.0232,0.0400,0.0728,0.1280,0.2440,0.4760"); + values ("0.2512,0.2355,0.2199,0.1926,0.1418,0.0402,-0.1590",\ +"0.2668,0.2512,0.2355,0.2082,0.1574,0.0559,-0.1434",\ +"0.2824,0.2629,0.2512,0.2199,0.1691,0.0715,-0.1316",\ +"0.3137,0.2980,0.2824,0.2512,0.2004,0.0988,-0.0965",\ +"0.3566,0.3410,0.3254,0.2980,0.2473,0.1418,-0.0535",\ +"0.4621,0.4426,0.4309,0.3996,0.3527,0.2473,0.0520",\ +"0.6574,0.6418,0.6262,0.5949,0.5441,0.4465,0.2473"); + } + + fall_constraint("SIG2SRAM_constraint_template") { + index_1("0.0056,0.0232,0.0400,0.0728,0.1280,0.2440,0.4760"); + index_2("0.0056,0.0232,0.0400,0.0728,0.1280,0.2440,0.4760"); + values ("0.2395,0.2238,0.2121,0.1809,0.1301,0.0324,-0.1551",\ +"0.2551,0.2434,0.2277,0.1965,0.1457,0.0480,-0.1395",\ +"0.2707,0.2551,0.2395,0.2082,0.1574,0.0637,-0.1277",\ +"0.3020,0.2863,0.2707,0.2434,0.1926,0.0910,-0.0965",\ +"0.3449,0.3332,0.3176,0.2863,0.2355,0.1379,-0.0496",\ +"0.4504,0.4348,0.4230,0.3918,0.3410,0.2434,0.0559",\ +"0.6457,0.6301,0.6145,0.5910,0.5324,0.4387,0.2512"); + } + } + } +bus(B_BIST_BM) { + bus_type : D_31_0; + direction : input ; + capacitance : 0.00275526 ; + max_transition : "0.476" ; + pin(B_BIST_BM[31:0]) { + related_power_pin : VDD; + related_ground_pin : VSS; + internal_power() { + when : "B_BIST_MEN"; + rise_power("scalar"){ + values (0.1176); + } + fall_power("scalar"){ + values (0.0493); + } + } + internal_power() { + when : "!B_BIST_MEN"; + rise_power("scalar"){ + values (0.1174); + } + fall_power("scalar"){ + values (0.0488); + } + } + } + timing() { + timing_type : setup_rising; + related_pin : "B_BIST_CLK"; + when : "(B_BIST_WEN & B_BIST_MEN)" + sdf_cond : "B_BIST_RW_ACCESS" + + rise_constraint("SIG2SRAM_constraint_template") { + index_1("0.0056,0.0232,0.0400,0.0728,0.1280,0.2440,0.4760"); + index_2("0.0056,0.0232,0.0400,0.0728,0.1280,0.2440,0.4760"); + values ("-0.3935,-0.3779,-0.3652,-0.3320,-0.2832,-0.1845,0.0088",\ +"-0.3985,-0.3829,-0.3702,-0.3370,-0.2882,-0.1895,0.0038",\ +"-0.4030,-0.3874,-0.3747,-0.3415,-0.2926,-0.1940,-0.0007",\ +"-0.4121,-0.3965,-0.3838,-0.3506,-0.3018,-0.2031,-0.0098",\ +"-0.4193,-0.4037,-0.3910,-0.3578,-0.3090,-0.2103,-0.0170",\ +"-0.4490,-0.4334,-0.4207,-0.3875,-0.3386,-0.2400,-0.0466",\ +"-0.5071,-0.4914,-0.4787,-0.4455,-0.3967,-0.2981,-0.1047"); + } + + fall_constraint("SIG2SRAM_constraint_template") { + index_1("0.0056,0.0232,0.0400,0.0728,0.1280,0.2440,0.4760"); + index_2("0.0056,0.0232,0.0400,0.0728,0.1280,0.2440,0.4760"); + values ("-0.3593,-0.3447,-0.3310,-0.3027,-0.2529,-0.1543,0.0254",\ +"-0.3643,-0.3497,-0.3360,-0.3077,-0.2579,-0.1593,0.0204",\ +"-0.3688,-0.3542,-0.3405,-0.3122,-0.2624,-0.1637,0.0159",\ +"-0.3779,-0.3633,-0.3496,-0.3213,-0.2715,-0.1729,0.0068",\ +"-0.3851,-0.3705,-0.3568,-0.3285,-0.2787,-0.1801,-0.0004",\ +"-0.4148,-0.4002,-0.3865,-0.3582,-0.3084,-0.2097,-0.0300",\ +"-0.4729,-0.4582,-0.4446,-0.4162,-0.3664,-0.2678,-0.0881"); + } + } + + + timing() { + timing_type : hold_rising; + related_pin : "B_BIST_CLK"; + when : "(B_BIST_WEN & B_BIST_MEN)" + sdf_cond : "B_BIST_RW_ACCESS" + + rise_constraint("SIG2SRAM_constraint_template") { + index_1("0.0056,0.0232,0.0400,0.0728,0.1280,0.2440,0.4760"); + index_2("0.0056,0.0232,0.0400,0.0728,0.1280,0.2440,0.4760"); + values ("0.5041,0.4885,0.4758,0.4426,0.3947,0.2951,0.1008",\ +"0.5091,0.4935,0.4808,0.4476,0.3997,0.3001,0.1058",\ +"0.5136,0.4980,0.4853,0.4521,0.4042,0.3046,0.1103",\ +"0.5227,0.5071,0.4944,0.4612,0.4133,0.3137,0.1194",\ +"0.5299,0.5143,0.5016,0.4684,0.4205,0.3209,0.1266",\ +"0.5596,0.5440,0.5313,0.4980,0.4502,0.3506,0.1563",\ +"0.6176,0.6020,0.5893,0.5561,0.5083,0.4087,0.2143"); + } + + fall_constraint("SIG2SRAM_constraint_template") { + index_1("0.0056,0.0232,0.0400,0.0728,0.1280,0.2440,0.4760"); + index_2("0.0056,0.0232,0.0400,0.0728,0.1280,0.2440,0.4760"); + values ("0.4631,0.4484,0.4338,0.4055,0.3547,0.2629,0.0783",\ +"0.4681,0.4534,0.4388,0.4105,0.3597,0.2679,0.0833",\ +"0.4726,0.4579,0.4433,0.4150,0.3642,0.2724,0.0878",\ +"0.4817,0.4671,0.4524,0.4241,0.3733,0.2815,0.0969",\ +"0.4889,0.4742,0.4596,0.4313,0.3805,0.2887,0.1041",\ +"0.5186,0.5039,0.4893,0.4609,0.4102,0.3184,0.1338",\ +"0.5766,0.5620,0.5473,0.5190,0.4682,0.3764,0.1919"); + } + } +} + pin(B_BIST_CLK) { + direction : input; + capacitance : 0.00380014; + max_transition : "0.476"; + clock : "true" ; + pin_func_type : active_rising ; + + timing () { + timing_type : "min_pulse_width"; + related_pin : "B_BIST_CLK"; + rise_constraint("CLKTRAN_constraint_template") { + index_1("0.0056,0.476"); + values("0.21,0.21"); + } + } + + related_power_pin : VDD; + related_ground_pin : VSS; + + internal_power() { + when : "!B_BIST_MEN & !B_BIST_WEN & !B_BIST_REN"; + rise_power("scalar"){ + values (0); + } + fall_power("scalar"){ + values (0); + } + } + internal_power() { + when : "!B_BIST_MEN & B_BIST_WEN & !B_BIST_REN"; + rise_power("scalar"){ + values (0.5036); + } + fall_power("scalar"){ + values (0); + } + } + internal_power() { + when : "B_BIST_MEN & B_BIST_WEN & !B_BIST_REN"; + rise_power("scalar"){ + values (33.4496); + } + fall_power("scalar"){ + values (0); + } + } + internal_power() { + when : "B_BIST_MEN & B_BIST_WEN & B_BIST_REN"; + rise_power("scalar"){ + values (37.7280); + } + fall_power("scalar"){ + values (0); + } + } + internal_power() { + when : "B_BIST_MEN & !B_BIST_WEN & B_BIST_REN"; + rise_power("scalar"){ + values (26.0060); + } + fall_power("scalar"){ + values (0); + } + } + internal_power() { + when : "!B_BIST_MEN & !B_BIST_WEN & B_BIST_REN"; + rise_power("scalar"){ + values (0.3024); + } + fall_power("scalar"){ + values (0); + } + } + internal_power() { + when : "!B_BIST_MEN & B_BIST_WEN & B_BIST_REN"; + rise_power("scalar"){ + values (1.1356); + } + fall_power("scalar"){ + values (0); + } + } + internal_power() { + when : "B_BIST_MEN & !B_BIST_WEN & !B_BIST_REN"; + rise_power("scalar"){ + values (0); + } + fall_power("scalar"){ + values (0); + } + } + } + bus(B_BIST_DIN) { + bus_type : D_31_0; + direction : input ; + capacitance : 0.00414348 ; + memory_write() { + address : B_BIST_ADDR ; + clocked_on : B_BIST_CLK; + } + + max_transition : "0.476" ; + pin(B_BIST_DIN[31:0]) { + related_power_pin : VDD; + related_ground_pin : VSS; + internal_power() { + when : "B_BIST_MEN"; + rise_power("scalar"){ + values (0.1176); + } + fall_power("scalar"){ + values (0.0493); + } + } + internal_power() { + when : "!B_BIST_MEN"; + rise_power("scalar"){ + values (0.1174); + } + fall_power("scalar"){ + values (0.0488); + } + } + } + timing() { + timing_type : setup_rising; + related_pin : "B_BIST_CLK"; + when : "(B_BIST_WEN & B_BIST_MEN)"; + sdf_cond : "B_BIST_W_ACCESS"; + + rise_constraint("SIG2SRAM_constraint_template") { + index_1("0.0056,0.0232,0.0400,0.0728,0.1280,0.2440,0.4760"); + index_2("0.0056,0.0232,0.0400,0.0728,0.1280,0.2440,0.4760"); + values ("-0.3935,-0.3779,-0.3652,-0.3320,-0.2832,-0.1845,0.0088",\ +"-0.3985,-0.3829,-0.3702,-0.3370,-0.2882,-0.1895,0.0038",\ +"-0.4030,-0.3874,-0.3747,-0.3415,-0.2926,-0.1940,-0.0007",\ +"-0.4121,-0.3965,-0.3838,-0.3506,-0.3018,-0.2031,-0.0098",\ +"-0.4193,-0.4037,-0.3910,-0.3578,-0.3090,-0.2103,-0.0170",\ +"-0.4490,-0.4334,-0.4207,-0.3875,-0.3386,-0.2400,-0.0466",\ +"-0.5071,-0.4914,-0.4787,-0.4455,-0.3967,-0.2981,-0.1047"); + } + + fall_constraint("SIG2SRAM_constraint_template") { + index_1("0.0056,0.0232,0.0400,0.0728,0.1280,0.2440,0.4760"); + index_2("0.0056,0.0232,0.0400,0.0728,0.1280,0.2440,0.4760"); + values ("-0.3593,-0.3447,-0.3310,-0.3027,-0.2529,-0.1543,0.0254",\ +"-0.3643,-0.3497,-0.3360,-0.3077,-0.2579,-0.1593,0.0204",\ +"-0.3688,-0.3542,-0.3405,-0.3122,-0.2624,-0.1637,0.0159",\ +"-0.3779,-0.3633,-0.3496,-0.3213,-0.2715,-0.1729,0.0068",\ +"-0.3851,-0.3705,-0.3568,-0.3285,-0.2787,-0.1801,-0.0004",\ +"-0.4148,-0.4002,-0.3865,-0.3582,-0.3084,-0.2097,-0.0300",\ +"-0.4729,-0.4582,-0.4446,-0.4162,-0.3664,-0.2678,-0.0881"); + } + } + + timing() { + timing_type : hold_rising; + related_pin : "B_BIST_CLK"; + when : "(B_BIST_WEN & B_BIST_MEN)"; + sdf_cond : "B_BIST_W_ACCESS"; + + rise_constraint("SIG2SRAM_constraint_template") { + index_1("0.0056,0.0232,0.0400,0.0728,0.1280,0.2440,0.4760"); + index_2("0.0056,0.0232,0.0400,0.0728,0.1280,0.2440,0.4760"); + values ("0.5041,0.4885,0.4758,0.4426,0.3947,0.2951,0.1008",\ +"0.5091,0.4935,0.4808,0.4476,0.3997,0.3001,0.1058",\ +"0.5136,0.4980,0.4853,0.4521,0.4042,0.3046,0.1103",\ +"0.5227,0.5071,0.4944,0.4612,0.4133,0.3137,0.1194",\ +"0.5299,0.5143,0.5016,0.4684,0.4205,0.3209,0.1266",\ +"0.5596,0.5440,0.5313,0.4980,0.4502,0.3506,0.1563",\ +"0.6176,0.6020,0.5893,0.5561,0.5083,0.4087,0.2143"); + } + + fall_constraint("SIG2SRAM_constraint_template") { + index_1("0.0056,0.0232,0.0400,0.0728,0.1280,0.2440,0.4760"); + index_2("0.0056,0.0232,0.0400,0.0728,0.1280,0.2440,0.4760"); + values ("0.4631,0.4484,0.4338,0.4055,0.3547,0.2629,0.0783",\ +"0.4681,0.4534,0.4388,0.4105,0.3597,0.2679,0.0833",\ +"0.4726,0.4579,0.4433,0.4150,0.3642,0.2724,0.0878",\ +"0.4817,0.4671,0.4524,0.4241,0.3733,0.2815,0.0969",\ +"0.4889,0.4742,0.4596,0.4313,0.3805,0.2887,0.1041",\ +"0.5186,0.5039,0.4893,0.4609,0.4102,0.3184,0.1338",\ +"0.5766,0.5620,0.5473,0.5190,0.4682,0.3764,0.1919"); + } + } + } + +bus(B_DOUT) { + + bus_type : D_31_0; + direction : output ; + capacitance : 0 ; + max_capacitance : 0.064 ; + memory_read() { + address : B_ADDR ; + } + pin(B_DOUT[31:0]) { + related_power_pin : VDD; + related_ground_pin : VSS; + internal_power() { + rise_power("scalar") { + values (0); + } + fall_power("scalar") { + values (0); + } + } + } + timing() { + related_pin : "B_CLK"; + timing_type : rising_edge ; + timing_sense : non_unate ; + + cell_rise(SIG2SRAM_delay_template) { + index_1("0.0056,0.0232,0.0400,0.0728,0.1280,0.2440,0.4760"); + index_2("0.0008,0.0014,0.0051,0.0100,0.0339,0.0640"); + values ("3.0433,3.0449,3.0525,3.0613,3.0937,3.1298",\ +"3.0496,3.0513,3.0589,3.0676,3.1000,3.1361",\ +"3.0517,3.0534,3.0610,3.0697,3.1021,3.1382",\ +"3.0648,3.0664,3.0740,3.0828,3.1151,3.1513",\ +"3.0710,3.0726,3.0802,3.0890,3.1213,3.1575",\ +"3.1025,3.1041,3.1117,3.1204,3.1528,3.1890",\ +"3.1570,3.1586,3.1662,3.1749,3.2073,3.2435"); + } + cell_fall(SIG2SRAM_delay_template) { + index_1("0.0056,0.0232,0.0400,0.0728,0.1280,0.2440,0.4760"); + index_2("0.0008,0.0014,0.0051,0.0100,0.0339,0.0640"); + values ("2.9830,2.9844,2.9905,2.9976,3.0241,3.0503",\ +"2.9894,2.9907,2.9968,3.0039,3.0304,3.0566",\ +"2.9915,2.9928,2.9989,3.0060,3.0325,3.0587",\ +"3.0045,3.0059,3.0119,3.0191,3.0456,3.0718",\ +"3.0107,3.0121,3.0181,3.0253,3.0518,3.0780",\ +"3.0422,3.0435,3.0496,3.0567,3.0832,3.1095",\ +"3.0967,3.0980,3.1041,3.1112,3.1377,3.1640"); + } + + rise_transition(SRAM_load_template) { + index_1("0.0008,0.0014,0.0051,0.0100,0.0339,0.0640"); + values ("0.0326,0.0341,0.0428,0.0518,0.0923,0.1492"); + } + fall_transition(SRAM_load_template) { + index_1("0.0008,0.0014,0.0051,0.0100,0.0339,0.0640"); + values ("0.0254,0.0265,0.0335,0.0402,0.0707,0.1039"); + } + } +} +cell_leakage_power : 159.4504; +} +} diff --git a/flow/platforms/ihp-sg13g2/lib/RM_IHPSG13_2P_256x8_c2_bm_bist_fast_1p32V_m55C.lib b/flow/platforms/ihp-sg13g2/lib/RM_IHPSG13_2P_256x8_c2_bm_bist_fast_1p32V_m55C.lib new file mode 100644 index 0000000000..e14f7e2439 --- /dev/null +++ b/flow/platforms/ihp-sg13g2/lib/RM_IHPSG13_2P_256x8_c2_bm_bist_fast_1p32V_m55C.lib @@ -0,0 +1,2874 @@ +/* ------------------------------------------------------*/ +/**/ +/* Copyright 2025 IHP PDK Authors*/ +/**/ +/* Licensed under the Apache License, Version 2.0 (the "License");*/ +/* you may not use this file except in compliance with the License.*/ +/* You may obtain a copy of the License at*/ +/* */ +/* https://www.apache.org/licenses/LICENSE-2.0*/ +/* */ +/* Unless required by applicable law or agreed to in writing, software*/ +/* distributed under the License is distributed on an "AS IS" BASIS,*/ +/* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.*/ +/* See the License for the specific language governing permissions and*/ +/* limitations under the License.*/ +/* */ +/* Generated on Wed Aug 27 13:36:30 2025 */ +/* */ +/* ------------------------------------------------------ */ +library(RM_IHPSG13_2P_256x8_c2_bm_bist_fast_1p32V_m55C) { + technology (cmos) ; + delay_model : table_lookup ; + define ("add_pg_pin_to_lib", "library", "boolean"); + add_pg_pin_to_lib : true; + voltage_map ( VDD, 1.32); + voltage_map ( VDDARRAY, 1.32); + voltage_map ( VSS, 0.000000 ); + + date : "Wed Aug 27 13:36:28 2025" ; + comment : "IHP Microelectronics GmbH, 2023" ; + revision : 1.0.0 ; + simulation : true ; + nom_process : 1 ; + nom_temperature : -55 ; + nom_voltage : 1.32 ; + + operating_conditions("fast_1p32V_m55C"){ + process : 1 ; + temperature : -55 ; + voltage : 1.32 ; + tree_type : "balanced_tree" ; + } + + default_operating_conditions : fast_1p32V_m55C ; + default_max_transition : 1.0 ; + default_fanout_load : 1.0 ; + default_inout_pin_cap : 0.0 ; + default_input_pin_cap : 0.0 ; + default_output_pin_cap : 0.0 ; + default_cell_leakage_power : 0.0 ; + default_leakage_power_density : 0.0 ; + + slew_lower_threshold_pct_rise : 30 ; + slew_upper_threshold_pct_rise : 70 ; + input_threshold_pct_fall : 50 ; + output_threshold_pct_fall : 50 ; + input_threshold_pct_rise : 50 ; + output_threshold_pct_rise : 50 ; + slew_lower_threshold_pct_fall : 30 ; + slew_upper_threshold_pct_fall : 70 ; + slew_derate_from_library : 0.5; + k_volt_cell_leakage_power : 0.0 ; + k_temp_cell_leakage_power : 0.0 ; + k_process_cell_leakage_power : 0.0 ; + k_volt_internal_power : 0.0 ; + k_temp_internal_power : 0.0 ; + k_process_internal_power : 0.0 ; + + capacitive_load_unit (1,pf) ; + voltage_unit : "1V" ; + current_unit : "1uA" ; + time_unit : "1ns" ; + leakage_power_unit : "1nW" ; + pulling_resistance_unit : "1kohm"; + /* + ------------------------------------------------------------------------------------------ + implicit units overview: + cell_area unit : "um" + internal_power unit : "1e-12 * J/toggle = 1 * uW/MHz" + (capacitive_load_unit * voltage_unit^2) per toggle event + ------------------------------------------------------------------------------------------ + */ + library_features(report_delay_calculation); + define_cell_area (pad_drivers,pad_driver_sites) ; + + lu_table_template(CLKTRAN_constraint_template) { + variable_1 : constrained_pin_transition; + index_1 ( "0.010, 0.050, 0.200, 0.400, 1.000" ); + } + lu_table_template(SRAM_load_template) { + variable_1 : total_output_net_capacitance; + index_1 ( "0.0008,0.0014,0.0051,0.0100,0.0339,0.0640" ); + } + lu_table_template(SIG2SRAM_constraint_template) { + variable_1 : related_pin_transition; + variable_2 : constrained_pin_transition; + index_1 ( "0.0040,0.0176,0.0344,0.0656,0.1120,0.2016,0.3800" ); + index_2 ( "0.0040,0.0176,0.0344,0.0656,0.1120,0.2016,0.3800" ); + } + + lu_table_template(SIG2SRAM_delay_template) { + variable_1 : input_net_transition; + variable_2 : total_output_net_capacitance; + index_1 ( "0.0040,0.0176,0.0344,0.0656,0.1120,0.2016,0.3800" ); + index_2 ( "0.0008,0.0014,0.0051,0.0100,0.0339,0.0640" ); + } + + type (D_7_0) { + base_type : array; + data_type : bit; + bit_width : 8; + bit_from : 7; + bit_to : 0; + downto : true; + } + + type (A_7_0) { + base_type : array; + data_type : bit; + bit_width : 8; + bit_from : 7; + bit_to : 0; + downto : true; + } + +cell(RM_IHPSG13_2P_256x8_c2_bm_bist) { +pg_pin (VDD) { + pg_type : primary_power; + voltage_name : VDD; +} +pg_pin (VDDARRAY) { + pg_type : primary_power; + voltage_name : VDDARRAY; +} +pg_pin (VSS) { + pg_type : primary_ground; + voltage_name : VSS; +} + +memory() { + type : ram; + address_width : 8; + word_width : 8; +} + +interface_timing : false; +bus_naming_style : "%s[%d]" ; +area : 38147.5147 ; + + pin(A_DLY) { + direction : input ; + capacitance : 0.00421562 ; + max_transition : "1" ; + related_power_pin : VDD; + related_ground_pin : VSS; + internal_power() { + rise_power("scalar") { + values (0); + } + fall_power("scalar") { + values (0); + } + } + } + +bus(A_ADDR) { + bus_type : A_7_0; + direction : input ; + capacitance : 0.0115194 ; + pin(A_ADDR[0]) { + capacitance : 0.00563454 ; + } + pin(A_ADDR[1]) { + capacitance : 0.00744185 ; + } + pin(A_ADDR[2]) { + capacitance : 0.0100611 ; + } + pin(A_ADDR[3]) { + capacitance : 0.00669965 ; + } + pin(A_ADDR[4]) { + capacitance : 0.00614331 ; + } + pin(A_ADDR[5]) { + capacitance : 0.0102172 ; + } + pin(A_ADDR[6]) { + capacitance : 0.0124225 ; + } + max_transition : "0.38" ; + pin(A_ADDR[7:0]) { + related_power_pin : VDD; + related_ground_pin : VSS; + internal_power() { + when : "A_MEN"; + rise_power("scalar"){ + values (0.0125); + } + fall_power("scalar"){ + values (0.0021); + } + } + internal_power() { + when : "!A_MEN"; + rise_power("scalar"){ + values (0.0265); + } + fall_power("scalar"){ + values (0.0015); + } + } + } + timing() { + timing_type : setup_rising; + related_pin : "A_CLK"; + when : "((A_WEN | A_REN)& A_MEN)" + sdf_cond : "A_RW_ACCESS" + + rise_constraint("SIG2SRAM_constraint_template") { + index_1("0.0040,0.0176,0.0344,0.0656,0.1120,0.2016,0.3800"); + index_2("0.0040,0.0176,0.0344,0.0656,0.1120,0.2016,0.3800"); + values ("-0.2371,-0.2215,-0.2098,-0.1824,-0.1434,-0.0691,0.0676",\ +"-0.2449,-0.2332,-0.2176,-0.1902,-0.1551,-0.0770,0.0559",\ +"-0.2605,-0.2488,-0.2332,-0.2059,-0.1707,-0.0965,0.0441",\ +"-0.2879,-0.2723,-0.2605,-0.2332,-0.1941,-0.1199,0.0168",\ +"-0.3230,-0.3113,-0.2996,-0.2723,-0.2332,-0.1590,-0.0184",\ +"-0.4012,-0.3895,-0.3738,-0.3465,-0.3074,-0.2332,-0.0965",\ +"-0.5379,-0.5262,-0.5105,-0.4832,-0.4480,-0.3699,-0.2332"); + } + + fall_constraint("SIG2SRAM_constraint_template") { + index_1("0.0040,0.0176,0.0344,0.0656,0.1120,0.2016,0.3800"); + index_2("0.0040,0.0176,0.0344,0.0656,0.1120,0.2016,0.3800"); + values ("-0.1785,-0.1707,-0.1551,-0.1277,-0.0887,-0.0184,0.1145",\ +"-0.1902,-0.1785,-0.1629,-0.1355,-0.1004,-0.0262,0.1027",\ +"-0.2059,-0.1941,-0.1785,-0.1512,-0.1160,-0.0418,0.0871",\ +"-0.2293,-0.2176,-0.2059,-0.1785,-0.1434,-0.0691,0.0598",\ +"-0.2684,-0.2566,-0.2449,-0.2176,-0.1824,-0.1082,0.0207",\ +"-0.3465,-0.3348,-0.3191,-0.2918,-0.2566,-0.1824,-0.0535",\ +"-0.4832,-0.4715,-0.4559,-0.4324,-0.3934,-0.3191,-0.1902"); + } + } + + + timing() { + timing_type : hold_rising; + related_pin : "A_CLK"; + when : "((A_WEN | A_REN)& A_MEN)" + sdf_cond : "A_RW_ACCESS" + + rise_constraint("SIG2SRAM_constraint_template") { + index_1("0.0040,0.0176,0.0344,0.0656,0.1120,0.2016,0.3800"); + index_2("0.0040,0.0176,0.0344,0.0656,0.1120,0.2016,0.3800"); + values ("0.3410,0.3293,0.3137,0.2863,0.2473,0.1730,0.0324",\ +"0.3488,0.3371,0.3215,0.2941,0.2590,0.1809,0.0480",\ +"0.3684,0.3527,0.3371,0.3098,0.2746,0.1965,0.0598",\ +"0.3918,0.3762,0.3645,0.3371,0.2980,0.2238,0.0871",\ +"0.4309,0.4152,0.4035,0.3762,0.3371,0.2629,0.1223",\ +"0.5051,0.4934,0.4777,0.4504,0.4113,0.3371,0.1965",\ +"0.6418,0.6262,0.6145,0.5871,0.5520,0.4738,0.3332"); + } + + fall_constraint("SIG2SRAM_constraint_template") { + index_1("0.0040,0.0176,0.0344,0.0656,0.1120,0.2016,0.3800"); + index_2("0.0040,0.0176,0.0344,0.0656,0.1120,0.2016,0.3800"); + values ("0.2824,0.2707,0.2551,0.2277,0.1926,0.1184,-0.0105",\ +"0.2902,0.2785,0.2668,0.2395,0.2043,0.1301,0.0012",\ +"0.3059,0.2941,0.2824,0.2551,0.2199,0.1457,0.0168",\ +"0.3332,0.3215,0.3059,0.2785,0.2434,0.1691,0.0402",\ +"0.3723,0.3605,0.3449,0.3176,0.2824,0.2121,0.0793",\ +"0.4465,0.4348,0.4230,0.3918,0.3566,0.2824,0.1535",\ +"0.5832,0.5715,0.5598,0.5324,0.4934,0.4191,0.2902"); + } + } +} +pin(A_WEN) { + direction : input ; + capacitance : 0.00341384 ; + max_transition : "0.38" ; + related_power_pin : VDD; + related_ground_pin : VSS; + internal_power() { + when : "A_MEN"; + rise_power("scalar"){ + values (0.0072); + } + fall_power("scalar"){ + values (0.0151); + } + } + internal_power() { + when : "!A_MEN"; + rise_power("scalar"){ + values (0.0057); + } + fall_power("scalar"){ + values (0.0206); + } + } + timing() { + timing_type : setup_rising; + related_pin : "A_CLK"; + when : "A_MEN" + sdf_cond : "A_MEN" + + rise_constraint("SIG2SRAM_constraint_template") { + index_1("0.0040,0.0176,0.0344,0.0656,0.1120,0.2016,0.3800"); + index_2("0.0040,0.0176,0.0344,0.0656,0.1120,0.2016,0.3800"); + values ("0.1418,0.1496,0.1652,0.1887,0.2316,0.3059,0.4465",\ +"0.1301,0.1379,0.1535,0.1809,0.2199,0.2941,0.4348",\ +"0.1145,0.1262,0.1379,0.1652,0.2043,0.2785,0.4191",\ +"0.0871,0.0949,0.1105,0.1379,0.1770,0.2512,0.3879",\ +"0.0480,0.0598,0.0754,0.0988,0.1379,0.2082,0.3527",\ +"-0.0262,-0.0145,0.0012,0.0246,0.0676,0.1379,0.2785",\ +"-0.1668,-0.1551,-0.1395,-0.1121,-0.0730,0.0012,0.1418"); + } + + fall_constraint("SIG2SRAM_constraint_template") { + index_1("0.0040,0.0176,0.0344,0.0656,0.1120,0.2016,0.3800"); + index_2("0.0040,0.0176,0.0344,0.0656,0.1120,0.2016,0.3800"); + values ("0.2082,0.2160,0.2316,0.2590,0.2941,0.3684,0.5012",\ +"0.1926,0.2043,0.2199,0.2473,0.2824,0.3566,0.4895",\ +"0.1770,0.1887,0.2043,0.2316,0.2668,0.3410,0.4777",\ +"0.1535,0.1652,0.1770,0.2043,0.2395,0.3137,0.4504",\ +"0.1145,0.1262,0.1379,0.1652,0.2043,0.2746,0.4113",\ +"0.0402,0.0520,0.0676,0.0910,0.1262,0.2004,0.3332",\ +"-0.0965,-0.0848,-0.0730,-0.0457,-0.0066,0.0637,0.2004"); + } + } + + + timing() { + timing_type : hold_rising; + related_pin : "A_CLK"; + when : "A_MEN" + sdf_cond : "A_MEN" + + rise_constraint("SIG2SRAM_constraint_template") { + index_1("0.0040,0.0176,0.0344,0.0656,0.1120,0.2016,0.3800"); + index_2("0.0040,0.0176,0.0344,0.0656,0.1120,0.2016,0.3800"); + values ("0.1770,0.1652,0.1496,0.1223,0.0793,0.0090,-0.1316",\ +"0.1848,0.1730,0.1574,0.1301,0.0910,0.0168,-0.1199",\ +"0.2004,0.1887,0.1770,0.1496,0.1066,0.0363,-0.1043",\ +"0.2277,0.2160,0.2004,0.1730,0.1340,0.0598,-0.0809",\ +"0.2668,0.2551,0.2395,0.2121,0.1730,0.0988,-0.0418",\ +"0.3410,0.3293,0.3137,0.2863,0.2434,0.1730,0.0324",\ +"0.4816,0.4699,0.4543,0.4230,0.3801,0.3098,0.1730"); + } + + fall_constraint("SIG2SRAM_constraint_template") { + index_1("0.0040,0.0176,0.0344,0.0656,0.1120,0.2016,0.3800"); + index_2("0.0040,0.0176,0.0344,0.0656,0.1120,0.2016,0.3800"); + values ("0.1613,0.1496,0.1379,0.1066,0.0715,0.0012,-0.1355",\ +"0.1730,0.1613,0.1457,0.1184,0.0832,0.0129,-0.1238",\ +"0.1887,0.1770,0.1613,0.1340,0.0988,0.0246,-0.1121",\ +"0.2121,0.2043,0.1887,0.1613,0.1223,0.0520,-0.0848",\ +"0.2512,0.2434,0.2277,0.2004,0.1613,0.0910,-0.0457",\ +"0.3254,0.3176,0.3020,0.2746,0.2355,0.1652,0.0324",\ +"0.4660,0.4543,0.4387,0.4113,0.3723,0.3020,0.1691"); + } + } + } +pin(A_REN) { + direction : input ; + capacitance : 0.00390661 ; + max_transition : "0.38" ; + related_power_pin : VDD; + related_ground_pin : VSS; + internal_power() { + when : "A_MEN"; + rise_power("scalar"){ + values (0.0101); + } + fall_power("scalar"){ + values (0.0103); + } + } + internal_power() { + when : "!A_MEN"; + rise_power("scalar"){ + values (0.0242); + } + fall_power("scalar"){ + values (0.0195); + } + } + timing() { + timing_type : setup_rising; + related_pin : "A_CLK"; + when : "A_MEN" + sdf_cond : "A_MEN" + + rise_constraint("SIG2SRAM_constraint_template") { + index_1("0.0040,0.0176,0.0344,0.0656,0.1120,0.2016,0.3800"); + index_2("0.0040,0.0176,0.0344,0.0656,0.1120,0.2016,0.3800"); + values ("-0.0027,0.0090,0.0246,0.0520,0.0910,0.1613,0.3020",\ +"-0.0105,0.0012,0.0129,0.0363,0.0793,0.1535,0.2902",\ +"-0.0262,-0.0145,-0.0027,0.0246,0.0637,0.1379,0.2785",\ +"-0.0535,-0.0418,-0.0262,0.0012,0.0363,0.1105,0.2512",\ +"-0.0926,-0.0809,-0.0652,-0.0418,-0.0027,0.0715,0.2121",\ +"-0.1668,-0.1551,-0.1395,-0.1082,-0.0770,-0.0027,0.1379",\ +"-0.3035,-0.2918,-0.2762,-0.2488,-0.2137,-0.1434,-0.0027"); + } + + fall_constraint("SIG2SRAM_constraint_template") { + index_1("0.0040,0.0176,0.0344,0.0656,0.1120,0.2016,0.3800"); + index_2("0.0040,0.0176,0.0344,0.0656,0.1120,0.2016,0.3800"); + values ("0.0832,0.0949,0.1105,0.1379,0.1730,0.2473,0.3801",\ +"0.0754,0.0832,0.0988,0.1223,0.1613,0.2355,0.3684",\ +"0.0598,0.0676,0.0832,0.1066,0.1457,0.2121,0.3527",\ +"0.0324,0.0441,0.0598,0.0871,0.1223,0.1926,0.3293",\ +"-0.0066,0.0051,0.0168,0.0480,0.0832,0.1535,0.2902",\ +"-0.0809,-0.0691,-0.0574,-0.0301,0.0090,0.0832,0.2121",\ +"-0.2176,-0.2059,-0.1941,-0.1668,-0.1277,-0.0574,0.0793"); + } + } + + + timing() { + timing_type : hold_rising; + related_pin : "A_CLK"; + when : "A_MEN" + sdf_cond : "A_MEN" + + rise_constraint("SIG2SRAM_constraint_template") { + index_1("0.0040,0.0176,0.0344,0.0656,0.1120,0.2016,0.3800"); + index_2("0.0040,0.0176,0.0344,0.0656,0.1120,0.2016,0.3800"); + values ("0.1887,0.1770,0.1613,0.1340,0.0949,0.0207,-0.1160",\ +"0.1965,0.1848,0.1730,0.1457,0.1027,0.0324,-0.1082",\ +"0.2160,0.2004,0.1887,0.1613,0.1184,0.0480,-0.0926",\ +"0.2395,0.2277,0.2121,0.1848,0.1457,0.0715,-0.0652",\ +"0.2785,0.2668,0.2512,0.2238,0.1848,0.1105,-0.0262",\ +"0.3527,0.3410,0.3254,0.2980,0.2551,0.1848,0.0480",\ +"0.4934,0.4816,0.4660,0.4387,0.3957,0.3254,0.1887"); + } + + fall_constraint("SIG2SRAM_constraint_template") { + index_1("0.0040,0.0176,0.0344,0.0656,0.1120,0.2016,0.3800"); + index_2("0.0040,0.0176,0.0344,0.0656,0.1120,0.2016,0.3800"); + values ("0.1730,0.1613,0.1496,0.1184,0.0793,0.0129,-0.1238",\ +"0.1848,0.1730,0.1574,0.1301,0.0910,0.0207,-0.1121",\ +"0.2004,0.1887,0.1730,0.1457,0.1066,0.0363,-0.1004",\ +"0.2238,0.2121,0.2004,0.1691,0.1340,0.0598,-0.0730",\ +"0.2629,0.2512,0.2395,0.2121,0.1691,0.0988,-0.0340",\ +"0.3371,0.3254,0.3137,0.2863,0.2434,0.1730,0.0402",\ +"0.4777,0.4660,0.4504,0.4230,0.3840,0.3137,0.1809"); + } + } + } +pin(A_MEN) { + direction : input ; + capacitance : 0.00326046 ; + max_transition : "0.38" ; + related_power_pin : VDD; + related_ground_pin : VSS; + internal_power() { + rise_power("scalar"){ + values (0.0779); + } + fall_power("scalar"){ + values (0.0107); + } + } + timing() { + timing_type : setup_rising; + related_pin : "A_CLK"; + + rise_constraint("SIG2SRAM_constraint_template") { + index_1("0.0040,0.0176,0.0344,0.0656,0.1120,0.2016,0.3800"); + index_2("0.0040,0.0176,0.0344,0.0656,0.1120,0.2016,0.3800"); + values ("0.1418,0.1496,0.1652,0.1926,0.2316,0.3059,0.4465",\ +"0.1301,0.1379,0.1535,0.1809,0.2199,0.2941,0.4348",\ +"0.1145,0.1262,0.1418,0.1652,0.2043,0.2785,0.4191",\ +"0.0871,0.0949,0.1105,0.1379,0.1770,0.2512,0.3879",\ +"0.0480,0.0598,0.0754,0.0988,0.1379,0.2082,0.3488",\ +"-0.0262,-0.0145,0.0012,0.0285,0.0676,0.1379,0.2785",\ +"-0.1668,-0.1551,-0.1395,-0.1121,-0.0730,0.0012,0.1379"); + } + + fall_constraint("SIG2SRAM_constraint_template") { + index_1("0.0040,0.0176,0.0344,0.0656,0.1120,0.2016,0.3800"); + index_2("0.0040,0.0176,0.0344,0.0656,0.1120,0.2016,0.3800"); + values ("0.2082,0.2199,0.2316,0.2590,0.2980,0.3723,0.5051",\ +"0.1965,0.2082,0.2199,0.2473,0.2863,0.3605,0.4934",\ +"0.1809,0.1926,0.2043,0.2316,0.2707,0.3449,0.4777",\ +"0.1574,0.1691,0.1809,0.2082,0.2434,0.3176,0.4543",\ +"0.1145,0.1262,0.1418,0.1691,0.2043,0.2785,0.4113",\ +"0.0441,0.0559,0.0676,0.0949,0.1301,0.2004,0.3332",\ +"-0.0965,-0.0848,-0.0691,-0.0418,-0.0066,0.0676,0.2004"); + } + } + + + timing() { + timing_type : hold_rising; + related_pin : "A_CLK"; + + rise_constraint("SIG2SRAM_constraint_template") { + index_1("0.0040,0.0176,0.0344,0.0656,0.1120,0.2016,0.3800"); + index_2("0.0040,0.0176,0.0344,0.0656,0.1120,0.2016,0.3800"); + values ("0.1770,0.1652,0.1535,0.1262,0.0832,0.0129,-0.1277",\ +"0.1887,0.1770,0.1613,0.1340,0.0949,0.0207,-0.1199",\ +"0.2043,0.1926,0.1770,0.1496,0.1105,0.0363,-0.1043",\ +"0.2277,0.2160,0.2043,0.1770,0.1379,0.0598,-0.0770",\ +"0.2668,0.2551,0.2434,0.2160,0.1730,0.0988,-0.0379",\ +"0.3449,0.3332,0.3176,0.2902,0.2473,0.1730,0.0363",\ +"0.4816,0.4699,0.4543,0.4270,0.3840,0.3098,0.1770"); + } + + fall_constraint("SIG2SRAM_constraint_template") { + index_1("0.0040,0.0176,0.0344,0.0656,0.1120,0.2016,0.3800"); + index_2("0.0040,0.0176,0.0344,0.0656,0.1120,0.2016,0.3800"); + values ("0.1613,0.1496,0.1379,0.1105,0.0715,0.0012,-0.1355",\ +"0.1730,0.1613,0.1496,0.1184,0.0832,0.0129,-0.1238",\ +"0.1887,0.1770,0.1652,0.1340,0.0988,0.0285,-0.1121",\ +"0.2121,0.2043,0.1887,0.1613,0.1223,0.0520,-0.0848",\ +"0.2551,0.2434,0.2277,0.2004,0.1613,0.0910,-0.0418",\ +"0.3293,0.3176,0.3020,0.2746,0.2395,0.1652,0.0324",\ +"0.4660,0.4543,0.4426,0.4113,0.3762,0.3020,0.1691"); + } + } + } +bus(A_BM) { + bus_type : D_7_0; + direction : input ; + capacitance : 0.00388883 ; + max_transition : "0.38" ; + pin(A_BM[7:0]) { + related_power_pin : VDD; + related_ground_pin : VSS; + internal_power() { + when : "A_MEN"; + rise_power("scalar"){ + values (0.0466); + } + fall_power("scalar"){ + values (0.0382); + } + } + internal_power() { + when : "!A_MEN"; + rise_power("scalar"){ + values (0.0552); + } + fall_power("scalar"){ + values (0.0440); + } + } + } + timing() { + timing_type : setup_rising; + related_pin : "A_CLK"; + when : "(A_WEN & A_MEN)" + sdf_cond : "A_RW_ACCESS" + + rise_constraint("SIG2SRAM_constraint_template") { + index_1("0.0040,0.0176,0.0344,0.0656,0.1120,0.2016,0.3800"); + index_2("0.0040,0.0176,0.0344,0.0656,0.1120,0.2016,0.3800"); + values ("-0.1725,-0.1618,-0.1462,-0.1208,-0.0798,-0.0065,0.1282",\ +"-0.1764,-0.1657,-0.1501,-0.1247,-0.0837,-0.0104,0.1243",\ +"-0.1801,-0.1694,-0.1537,-0.1284,-0.0873,-0.0141,0.1207",\ +"-0.1833,-0.1726,-0.1570,-0.1315,-0.0905,-0.0173,0.1175",\ +"-0.1959,-0.1852,-0.1696,-0.1442,-0.1032,-0.0299,0.1048",\ +"-0.2135,-0.2028,-0.1872,-0.1618,-0.1208,-0.0475,0.0872",\ +"-0.2410,-0.2303,-0.2147,-0.1893,-0.1483,-0.0750,0.0597"); + } + + fall_constraint("SIG2SRAM_constraint_template") { + index_1("0.0040,0.0176,0.0344,0.0656,0.1120,0.2016,0.3800"); + index_2("0.0040,0.0176,0.0344,0.0656,0.1120,0.2016,0.3800"); + values ("-0.1491,-0.1374,-0.1247,-0.0974,-0.0602,0.0130,0.1409",\ +"-0.1530,-0.1413,-0.1286,-0.1012,-0.0641,0.0091,0.1370",\ +"-0.1567,-0.1450,-0.1323,-0.1049,-0.0678,0.0054,0.1334",\ +"-0.1599,-0.1482,-0.1355,-0.1081,-0.0710,0.0022,0.1302",\ +"-0.1725,-0.1608,-0.1481,-0.1207,-0.0836,-0.0104,0.1175",\ +"-0.1901,-0.1784,-0.1657,-0.1383,-0.1012,-0.0280,0.0999",\ +"-0.2176,-0.2059,-0.1932,-0.1658,-0.1287,-0.0555,0.0724"); + } + } + + + timing() { + timing_type : hold_rising; + related_pin : "A_CLK"; + when : "(A_WEN & A_MEN)" + sdf_cond : "A_RW_ACCESS" + + rise_constraint("SIG2SRAM_constraint_template") { + index_1("0.0040,0.0176,0.0344,0.0656,0.1120,0.2016,0.3800"); + index_2("0.0040,0.0176,0.0344,0.0656,0.1120,0.2016,0.3800"); + values ("0.2776,0.2679,0.2522,0.2259,0.1887,0.1145,-0.0202",\ +"0.2815,0.2717,0.2561,0.2297,0.1926,0.1184,-0.0163",\ +"0.2852,0.2754,0.2598,0.2334,0.1963,0.1221,-0.0127",\ +"0.2884,0.2786,0.2630,0.2366,0.1995,0.1253,-0.0095",\ +"0.3010,0.2912,0.2756,0.2492,0.2121,0.1379,0.0032",\ +"0.3186,0.3088,0.2932,0.2668,0.2297,0.1555,0.0208",\ +"0.3461,0.3363,0.3207,0.2944,0.2572,0.1830,0.0483"); + } + + fall_constraint("SIG2SRAM_constraint_template") { + index_1("0.0040,0.0176,0.0344,0.0656,0.1120,0.2016,0.3800"); + index_2("0.0040,0.0176,0.0344,0.0656,0.1120,0.2016,0.3800"); + values ("0.2493,0.2386,0.2249,0.1975,0.1614,0.0891,-0.0407",\ +"0.2532,0.2424,0.2288,0.2014,0.1653,0.0930,-0.0369",\ +"0.2569,0.2461,0.2324,0.2051,0.1690,0.0967,-0.0332",\ +"0.2601,0.2493,0.2356,0.2083,0.1722,0.0999,-0.0300",\ +"0.2727,0.2619,0.2483,0.2209,0.1848,0.1125,-0.0174",\ +"0.2903,0.2796,0.2659,0.2385,0.2024,0.1301,0.0003",\ +"0.3178,0.3070,0.2934,0.2660,0.2299,0.1576,0.0278"); + } + } +} + pin(A_CLK) { + direction : input; + capacitance : 0.00389386; + max_transition : "0.38"; + clock : "true" ; + pin_func_type : active_rising ; + + timing () { + timing_type : "min_pulse_width"; + related_pin : "A_CLK"; + rise_constraint("CLKTRAN_constraint_template") { + index_1("0.004,0.38"); + values("0.12,0.12"); + } + } + + related_power_pin : VDD; + related_ground_pin : VSS; + + internal_power() { + when : "!A_MEN & !A_WEN & !A_REN"; + rise_power("scalar"){ + values (0); + } + fall_power("scalar"){ + values (0); + } + } + internal_power() { + when : "!A_MEN & A_WEN & !A_REN"; + rise_power("scalar"){ + values (0.6217); + } + fall_power("scalar"){ + values (0); + } + } + internal_power() { + when : "A_MEN & A_WEN & !A_REN"; + rise_power("scalar"){ + values (13.4151); + } + fall_power("scalar"){ + values (0); + } + } + internal_power() { + when : "A_MEN & A_WEN & A_REN"; + rise_power("scalar"){ + values (14.2183); + } + fall_power("scalar"){ + values (0); + } + } + internal_power() { + when : "A_MEN & !A_WEN & A_REN"; + rise_power("scalar"){ + values (10.4701); + } + fall_power("scalar"){ + values (0); + } + } + internal_power() { + when : "!A_MEN & !A_WEN & A_REN"; + rise_power("scalar"){ + values (0.3812); + } + fall_power("scalar"){ + values (0); + } + } + internal_power() { + when : "!A_MEN & A_WEN & A_REN"; + rise_power("scalar"){ + values (0.6439); + } + fall_power("scalar"){ + values (0); + } + } + internal_power() { + when : "A_MEN & !A_WEN & !A_REN"; + rise_power("scalar"){ + values (0); + } + fall_power("scalar"){ + values (0); + } + } + } + bus(A_DIN) { + bus_type : D_7_0; + direction : input ; + capacitance : 0.00505326 ; + memory_write() { + address : A_ADDR ; + clocked_on : A_CLK; + } + + max_transition : "0.38" ; + pin(A_DIN[7:0]) { + related_power_pin : VDD; + related_ground_pin : VSS; + internal_power() { + when : "A_MEN"; + rise_power("scalar"){ + values (0.0466); + } + fall_power("scalar"){ + values (0.0382); + } + } + internal_power() { + when : "!A_MEN"; + rise_power("scalar"){ + values (0.0552); + } + fall_power("scalar"){ + values (0.0440); + } + } + } + timing() { + timing_type : setup_rising; + related_pin : "A_CLK"; + when : "(A_WEN & A_MEN)"; + sdf_cond : "A_W_ACCESS"; + + rise_constraint("SIG2SRAM_constraint_template") { + index_1("0.0040,0.0176,0.0344,0.0656,0.1120,0.2016,0.3800"); + index_2("0.0040,0.0176,0.0344,0.0656,0.1120,0.2016,0.3800"); + values ("-0.1725,-0.1618,-0.1462,-0.1208,-0.0798,-0.0065,0.1282",\ +"-0.1764,-0.1657,-0.1501,-0.1247,-0.0837,-0.0104,0.1243",\ +"-0.1801,-0.1694,-0.1537,-0.1284,-0.0873,-0.0141,0.1207",\ +"-0.1833,-0.1726,-0.1570,-0.1315,-0.0905,-0.0173,0.1175",\ +"-0.1959,-0.1852,-0.1696,-0.1442,-0.1032,-0.0299,0.1048",\ +"-0.2135,-0.2028,-0.1872,-0.1618,-0.1208,-0.0475,0.0872",\ +"-0.2410,-0.2303,-0.2147,-0.1893,-0.1483,-0.0750,0.0597"); + } + + fall_constraint("SIG2SRAM_constraint_template") { + index_1("0.0040,0.0176,0.0344,0.0656,0.1120,0.2016,0.3800"); + index_2("0.0040,0.0176,0.0344,0.0656,0.1120,0.2016,0.3800"); + values ("-0.1491,-0.1374,-0.1247,-0.0974,-0.0602,0.0130,0.1409",\ +"-0.1530,-0.1413,-0.1286,-0.1012,-0.0641,0.0091,0.1370",\ +"-0.1567,-0.1450,-0.1323,-0.1049,-0.0678,0.0054,0.1334",\ +"-0.1599,-0.1482,-0.1355,-0.1081,-0.0710,0.0022,0.1302",\ +"-0.1725,-0.1608,-0.1481,-0.1207,-0.0836,-0.0104,0.1175",\ +"-0.1901,-0.1784,-0.1657,-0.1383,-0.1012,-0.0280,0.0999",\ +"-0.2176,-0.2059,-0.1932,-0.1658,-0.1287,-0.0555,0.0724"); + } + } + + timing() { + timing_type : hold_rising; + related_pin : "A_CLK"; + when : "(A_WEN & A_MEN)"; + sdf_cond : "A_W_ACCESS"; + + rise_constraint("SIG2SRAM_constraint_template") { + index_1("0.0040,0.0176,0.0344,0.0656,0.1120,0.2016,0.3800"); + index_2("0.0040,0.0176,0.0344,0.0656,0.1120,0.2016,0.3800"); + values ("0.2776,0.2679,0.2522,0.2259,0.1887,0.1145,-0.0202",\ +"0.2815,0.2717,0.2561,0.2297,0.1926,0.1184,-0.0163",\ +"0.2852,0.2754,0.2598,0.2334,0.1963,0.1221,-0.0127",\ +"0.2884,0.2786,0.2630,0.2366,0.1995,0.1253,-0.0095",\ +"0.3010,0.2912,0.2756,0.2492,0.2121,0.1379,0.0032",\ +"0.3186,0.3088,0.2932,0.2668,0.2297,0.1555,0.0208",\ +"0.3461,0.3363,0.3207,0.2944,0.2572,0.1830,0.0483"); + } + + fall_constraint("SIG2SRAM_constraint_template") { + index_1("0.0040,0.0176,0.0344,0.0656,0.1120,0.2016,0.3800"); + index_2("0.0040,0.0176,0.0344,0.0656,0.1120,0.2016,0.3800"); + values ("0.2493,0.2386,0.2249,0.1975,0.1614,0.0891,-0.0407",\ +"0.2532,0.2424,0.2288,0.2014,0.1653,0.0930,-0.0369",\ +"0.2569,0.2461,0.2324,0.2051,0.1690,0.0967,-0.0332",\ +"0.2601,0.2493,0.2356,0.2083,0.1722,0.0999,-0.0300",\ +"0.2727,0.2619,0.2483,0.2209,0.1848,0.1125,-0.0174",\ +"0.2903,0.2796,0.2659,0.2385,0.2024,0.1301,0.0003",\ +"0.3178,0.3070,0.2934,0.2660,0.2299,0.1576,0.0278"); + } + } + } + + pin(A_BIST_EN) { + direction : input ; + capacitance : 0.00421562 ; + max_transition : "1" ; + related_power_pin : VDD; + related_ground_pin : VSS; + internal_power() { + rise_power("scalar") { + values (0); + } + fall_power("scalar") { + values (0); + } + } + } + +bus(A_BIST_ADDR) { + bus_type : A_7_0; + direction : input ; + capacitance : 0.0115194 ; + pin(A_BIST_ADDR[0]) { + capacitance : 0.00563454 ; + } + pin(A_BIST_ADDR[1]) { + capacitance : 0.00744185 ; + } + pin(A_BIST_ADDR[2]) { + capacitance : 0.0100611 ; + } + pin(A_BIST_ADDR[3]) { + capacitance : 0.00669965 ; + } + pin(A_BIST_ADDR[4]) { + capacitance : 0.00614331 ; + } + pin(A_BIST_ADDR[5]) { + capacitance : 0.0102172 ; + } + pin(A_BIST_ADDR[6]) { + capacitance : 0.0124225 ; + } + max_transition : "0.38" ; + pin(A_BIST_ADDR[7:0]) { + related_power_pin : VDD; + related_ground_pin : VSS; + internal_power() { + when : "A_BIST_MEN"; + rise_power("scalar"){ + values (0.0125); + } + fall_power("scalar"){ + values (0.0021); + } + } + internal_power() { + when : "!A_BIST_MEN"; + rise_power("scalar"){ + values (0.0265); + } + fall_power("scalar"){ + values (0.0015); + } + } + } + timing() { + timing_type : setup_rising; + related_pin : "A_BIST_CLK"; + when : "((A_BIST_WEN | A_BIST_REN)& A_BIST_MEN)" + sdf_cond : "A_BIST_RW_ACCESS" + + rise_constraint("SIG2SRAM_constraint_template") { + index_1("0.0040,0.0176,0.0344,0.0656,0.1120,0.2016,0.3800"); + index_2("0.0040,0.0176,0.0344,0.0656,0.1120,0.2016,0.3800"); + values ("-0.2371,-0.2215,-0.2098,-0.1824,-0.1434,-0.0691,0.0676",\ +"-0.2449,-0.2332,-0.2176,-0.1902,-0.1551,-0.0770,0.0559",\ +"-0.2605,-0.2488,-0.2332,-0.2059,-0.1707,-0.0965,0.0441",\ +"-0.2879,-0.2723,-0.2605,-0.2332,-0.1941,-0.1199,0.0168",\ +"-0.3230,-0.3113,-0.2996,-0.2723,-0.2332,-0.1590,-0.0184",\ +"-0.4012,-0.3895,-0.3738,-0.3465,-0.3074,-0.2332,-0.0965",\ +"-0.5379,-0.5262,-0.5105,-0.4832,-0.4480,-0.3699,-0.2332"); + } + + fall_constraint("SIG2SRAM_constraint_template") { + index_1("0.0040,0.0176,0.0344,0.0656,0.1120,0.2016,0.3800"); + index_2("0.0040,0.0176,0.0344,0.0656,0.1120,0.2016,0.3800"); + values ("-0.1785,-0.1707,-0.1551,-0.1277,-0.0887,-0.0184,0.1145",\ +"-0.1902,-0.1785,-0.1629,-0.1355,-0.1004,-0.0262,0.1027",\ +"-0.2059,-0.1941,-0.1785,-0.1512,-0.1160,-0.0418,0.0871",\ +"-0.2293,-0.2176,-0.2059,-0.1785,-0.1434,-0.0691,0.0598",\ +"-0.2684,-0.2566,-0.2449,-0.2176,-0.1824,-0.1082,0.0207",\ +"-0.3465,-0.3348,-0.3191,-0.2918,-0.2566,-0.1824,-0.0535",\ +"-0.4832,-0.4715,-0.4559,-0.4324,-0.3934,-0.3191,-0.1902"); + } + } + + + timing() { + timing_type : hold_rising; + related_pin : "A_BIST_CLK"; + when : "((A_BIST_WEN | A_BIST_REN)& A_BIST_MEN)" + sdf_cond : "A_BIST_RW_ACCESS" + + rise_constraint("SIG2SRAM_constraint_template") { + index_1("0.0040,0.0176,0.0344,0.0656,0.1120,0.2016,0.3800"); + index_2("0.0040,0.0176,0.0344,0.0656,0.1120,0.2016,0.3800"); + values ("0.3410,0.3293,0.3137,0.2863,0.2473,0.1730,0.0324",\ +"0.3488,0.3371,0.3215,0.2941,0.2590,0.1809,0.0480",\ +"0.3684,0.3527,0.3371,0.3098,0.2746,0.1965,0.0598",\ +"0.3918,0.3762,0.3645,0.3371,0.2980,0.2238,0.0871",\ +"0.4309,0.4152,0.4035,0.3762,0.3371,0.2629,0.1223",\ +"0.5051,0.4934,0.4777,0.4504,0.4113,0.3371,0.1965",\ +"0.6418,0.6262,0.6145,0.5871,0.5520,0.4738,0.3332"); + } + + fall_constraint("SIG2SRAM_constraint_template") { + index_1("0.0040,0.0176,0.0344,0.0656,0.1120,0.2016,0.3800"); + index_2("0.0040,0.0176,0.0344,0.0656,0.1120,0.2016,0.3800"); + values ("0.2824,0.2707,0.2551,0.2277,0.1926,0.1184,-0.0105",\ +"0.2902,0.2785,0.2668,0.2395,0.2043,0.1301,0.0012",\ +"0.3059,0.2941,0.2824,0.2551,0.2199,0.1457,0.0168",\ +"0.3332,0.3215,0.3059,0.2785,0.2434,0.1691,0.0402",\ +"0.3723,0.3605,0.3449,0.3176,0.2824,0.2121,0.0793",\ +"0.4465,0.4348,0.4230,0.3918,0.3566,0.2824,0.1535",\ +"0.5832,0.5715,0.5598,0.5324,0.4934,0.4191,0.2902"); + } + } +} +pin(A_BIST_WEN) { + direction : input ; + capacitance : 0.00341384 ; + max_transition : "0.38" ; + related_power_pin : VDD; + related_ground_pin : VSS; + internal_power() { + when : "A_BIST_MEN"; + rise_power("scalar"){ + values (0.0072); + } + fall_power("scalar"){ + values (0.0151); + } + } + internal_power() { + when : "!A_BIST_MEN"; + rise_power("scalar"){ + values (0.0057); + } + fall_power("scalar"){ + values (0.0206); + } + } + timing() { + timing_type : setup_rising; + related_pin : "A_BIST_CLK"; + when : "A_BIST_MEN" + sdf_cond : "A_BIST_MEN" + + rise_constraint("SIG2SRAM_constraint_template") { + index_1("0.0040,0.0176,0.0344,0.0656,0.1120,0.2016,0.3800"); + index_2("0.0040,0.0176,0.0344,0.0656,0.1120,0.2016,0.3800"); + values ("0.1418,0.1496,0.1652,0.1887,0.2316,0.3059,0.4465",\ +"0.1301,0.1379,0.1535,0.1809,0.2199,0.2941,0.4348",\ +"0.1145,0.1262,0.1379,0.1652,0.2043,0.2785,0.4191",\ +"0.0871,0.0949,0.1105,0.1379,0.1770,0.2512,0.3879",\ +"0.0480,0.0598,0.0754,0.0988,0.1379,0.2082,0.3527",\ +"-0.0262,-0.0145,0.0012,0.0246,0.0676,0.1379,0.2785",\ +"-0.1668,-0.1551,-0.1395,-0.1121,-0.0730,0.0012,0.1418"); + } + + fall_constraint("SIG2SRAM_constraint_template") { + index_1("0.0040,0.0176,0.0344,0.0656,0.1120,0.2016,0.3800"); + index_2("0.0040,0.0176,0.0344,0.0656,0.1120,0.2016,0.3800"); + values ("0.2082,0.2160,0.2316,0.2590,0.2941,0.3684,0.5012",\ +"0.1926,0.2043,0.2199,0.2473,0.2824,0.3566,0.4895",\ +"0.1770,0.1887,0.2043,0.2316,0.2668,0.3410,0.4777",\ +"0.1535,0.1652,0.1770,0.2043,0.2395,0.3137,0.4504",\ +"0.1145,0.1262,0.1379,0.1652,0.2043,0.2746,0.4113",\ +"0.0402,0.0520,0.0676,0.0910,0.1262,0.2004,0.3332",\ +"-0.0965,-0.0848,-0.0730,-0.0457,-0.0066,0.0637,0.2004"); + } + } + + + timing() { + timing_type : hold_rising; + related_pin : "A_BIST_CLK"; + when : "A_BIST_MEN" + sdf_cond : "A_BIST_MEN" + + rise_constraint("SIG2SRAM_constraint_template") { + index_1("0.0040,0.0176,0.0344,0.0656,0.1120,0.2016,0.3800"); + index_2("0.0040,0.0176,0.0344,0.0656,0.1120,0.2016,0.3800"); + values ("0.1770,0.1652,0.1496,0.1223,0.0793,0.0090,-0.1316",\ +"0.1848,0.1730,0.1574,0.1301,0.0910,0.0168,-0.1199",\ +"0.2004,0.1887,0.1770,0.1496,0.1066,0.0363,-0.1043",\ +"0.2277,0.2160,0.2004,0.1730,0.1340,0.0598,-0.0809",\ +"0.2668,0.2551,0.2395,0.2121,0.1730,0.0988,-0.0418",\ +"0.3410,0.3293,0.3137,0.2863,0.2434,0.1730,0.0324",\ +"0.4816,0.4699,0.4543,0.4230,0.3801,0.3098,0.1730"); + } + + fall_constraint("SIG2SRAM_constraint_template") { + index_1("0.0040,0.0176,0.0344,0.0656,0.1120,0.2016,0.3800"); + index_2("0.0040,0.0176,0.0344,0.0656,0.1120,0.2016,0.3800"); + values ("0.1613,0.1496,0.1379,0.1066,0.0715,0.0012,-0.1355",\ +"0.1730,0.1613,0.1457,0.1184,0.0832,0.0129,-0.1238",\ +"0.1887,0.1770,0.1613,0.1340,0.0988,0.0246,-0.1121",\ +"0.2121,0.2043,0.1887,0.1613,0.1223,0.0520,-0.0848",\ +"0.2512,0.2434,0.2277,0.2004,0.1613,0.0910,-0.0457",\ +"0.3254,0.3176,0.3020,0.2746,0.2355,0.1652,0.0324",\ +"0.4660,0.4543,0.4387,0.4113,0.3723,0.3020,0.1691"); + } + } + } +pin(A_BIST_REN) { + direction : input ; + capacitance : 0.00390661 ; + max_transition : "0.38" ; + related_power_pin : VDD; + related_ground_pin : VSS; + internal_power() { + when : "A_BIST_MEN"; + rise_power("scalar"){ + values (0.0101); + } + fall_power("scalar"){ + values (0.0103); + } + } + internal_power() { + when : "!A_BIST_MEN"; + rise_power("scalar"){ + values (0.0242); + } + fall_power("scalar"){ + values (0.0195); + } + } + timing() { + timing_type : setup_rising; + related_pin : "A_BIST_CLK"; + when : "A_BIST_MEN" + sdf_cond : "A_BIST_MEN" + + rise_constraint("SIG2SRAM_constraint_template") { + index_1("0.0040,0.0176,0.0344,0.0656,0.1120,0.2016,0.3800"); + index_2("0.0040,0.0176,0.0344,0.0656,0.1120,0.2016,0.3800"); + values ("-0.0027,0.0090,0.0246,0.0520,0.0910,0.1613,0.3020",\ +"-0.0105,0.0012,0.0129,0.0363,0.0793,0.1535,0.2902",\ +"-0.0262,-0.0145,-0.0027,0.0246,0.0637,0.1379,0.2785",\ +"-0.0535,-0.0418,-0.0262,0.0012,0.0363,0.1105,0.2512",\ +"-0.0926,-0.0809,-0.0652,-0.0418,-0.0027,0.0715,0.2121",\ +"-0.1668,-0.1551,-0.1395,-0.1082,-0.0770,-0.0027,0.1379",\ +"-0.3035,-0.2918,-0.2762,-0.2488,-0.2137,-0.1434,-0.0027"); + } + + fall_constraint("SIG2SRAM_constraint_template") { + index_1("0.0040,0.0176,0.0344,0.0656,0.1120,0.2016,0.3800"); + index_2("0.0040,0.0176,0.0344,0.0656,0.1120,0.2016,0.3800"); + values ("0.0832,0.0949,0.1105,0.1379,0.1730,0.2473,0.3801",\ +"0.0754,0.0832,0.0988,0.1223,0.1613,0.2355,0.3684",\ +"0.0598,0.0676,0.0832,0.1066,0.1457,0.2121,0.3527",\ +"0.0324,0.0441,0.0598,0.0871,0.1223,0.1926,0.3293",\ +"-0.0066,0.0051,0.0168,0.0480,0.0832,0.1535,0.2902",\ +"-0.0809,-0.0691,-0.0574,-0.0301,0.0090,0.0832,0.2121",\ +"-0.2176,-0.2059,-0.1941,-0.1668,-0.1277,-0.0574,0.0793"); + } + } + + + timing() { + timing_type : hold_rising; + related_pin : "A_BIST_CLK"; + when : "A_BIST_MEN" + sdf_cond : "A_BIST_MEN" + + rise_constraint("SIG2SRAM_constraint_template") { + index_1("0.0040,0.0176,0.0344,0.0656,0.1120,0.2016,0.3800"); + index_2("0.0040,0.0176,0.0344,0.0656,0.1120,0.2016,0.3800"); + values ("0.1887,0.1770,0.1613,0.1340,0.0949,0.0207,-0.1160",\ +"0.1965,0.1848,0.1730,0.1457,0.1027,0.0324,-0.1082",\ +"0.2160,0.2004,0.1887,0.1613,0.1184,0.0480,-0.0926",\ +"0.2395,0.2277,0.2121,0.1848,0.1457,0.0715,-0.0652",\ +"0.2785,0.2668,0.2512,0.2238,0.1848,0.1105,-0.0262",\ +"0.3527,0.3410,0.3254,0.2980,0.2551,0.1848,0.0480",\ +"0.4934,0.4816,0.4660,0.4387,0.3957,0.3254,0.1887"); + } + + fall_constraint("SIG2SRAM_constraint_template") { + index_1("0.0040,0.0176,0.0344,0.0656,0.1120,0.2016,0.3800"); + index_2("0.0040,0.0176,0.0344,0.0656,0.1120,0.2016,0.3800"); + values ("0.1730,0.1613,0.1496,0.1184,0.0793,0.0129,-0.1238",\ +"0.1848,0.1730,0.1574,0.1301,0.0910,0.0207,-0.1121",\ +"0.2004,0.1887,0.1730,0.1457,0.1066,0.0363,-0.1004",\ +"0.2238,0.2121,0.2004,0.1691,0.1340,0.0598,-0.0730",\ +"0.2629,0.2512,0.2395,0.2121,0.1691,0.0988,-0.0340",\ +"0.3371,0.3254,0.3137,0.2863,0.2434,0.1730,0.0402",\ +"0.4777,0.4660,0.4504,0.4230,0.3840,0.3137,0.1809"); + } + } + } +pin(A_BIST_MEN) { + direction : input ; + capacitance : 0.00326046 ; + max_transition : "0.38" ; + related_power_pin : VDD; + related_ground_pin : VSS; + internal_power() { + rise_power("scalar"){ + values (0.0779); + } + fall_power("scalar"){ + values (0.0107); + } + } + timing() { + timing_type : setup_rising; + related_pin : "A_BIST_CLK"; + + rise_constraint("SIG2SRAM_constraint_template") { + index_1("0.0040,0.0176,0.0344,0.0656,0.1120,0.2016,0.3800"); + index_2("0.0040,0.0176,0.0344,0.0656,0.1120,0.2016,0.3800"); + values ("0.1418,0.1496,0.1652,0.1926,0.2316,0.3059,0.4465",\ +"0.1301,0.1379,0.1535,0.1809,0.2199,0.2941,0.4348",\ +"0.1145,0.1262,0.1418,0.1652,0.2043,0.2785,0.4191",\ +"0.0871,0.0949,0.1105,0.1379,0.1770,0.2512,0.3879",\ +"0.0480,0.0598,0.0754,0.0988,0.1379,0.2082,0.3488",\ +"-0.0262,-0.0145,0.0012,0.0285,0.0676,0.1379,0.2785",\ +"-0.1668,-0.1551,-0.1395,-0.1121,-0.0730,0.0012,0.1379"); + } + + fall_constraint("SIG2SRAM_constraint_template") { + index_1("0.0040,0.0176,0.0344,0.0656,0.1120,0.2016,0.3800"); + index_2("0.0040,0.0176,0.0344,0.0656,0.1120,0.2016,0.3800"); + values ("0.2082,0.2199,0.2316,0.2590,0.2980,0.3723,0.5051",\ +"0.1965,0.2082,0.2199,0.2473,0.2863,0.3605,0.4934",\ +"0.1809,0.1926,0.2043,0.2316,0.2707,0.3449,0.4777",\ +"0.1574,0.1691,0.1809,0.2082,0.2434,0.3176,0.4543",\ +"0.1145,0.1262,0.1418,0.1691,0.2043,0.2785,0.4113",\ +"0.0441,0.0559,0.0676,0.0949,0.1301,0.2004,0.3332",\ +"-0.0965,-0.0848,-0.0691,-0.0418,-0.0066,0.0676,0.2004"); + } + } + + + timing() { + timing_type : hold_rising; + related_pin : "A_BIST_CLK"; + + rise_constraint("SIG2SRAM_constraint_template") { + index_1("0.0040,0.0176,0.0344,0.0656,0.1120,0.2016,0.3800"); + index_2("0.0040,0.0176,0.0344,0.0656,0.1120,0.2016,0.3800"); + values ("0.1770,0.1652,0.1535,0.1262,0.0832,0.0129,-0.1277",\ +"0.1887,0.1770,0.1613,0.1340,0.0949,0.0207,-0.1199",\ +"0.2043,0.1926,0.1770,0.1496,0.1105,0.0363,-0.1043",\ +"0.2277,0.2160,0.2043,0.1770,0.1379,0.0598,-0.0770",\ +"0.2668,0.2551,0.2434,0.2160,0.1730,0.0988,-0.0379",\ +"0.3449,0.3332,0.3176,0.2902,0.2473,0.1730,0.0363",\ +"0.4816,0.4699,0.4543,0.4270,0.3840,0.3098,0.1770"); + } + + fall_constraint("SIG2SRAM_constraint_template") { + index_1("0.0040,0.0176,0.0344,0.0656,0.1120,0.2016,0.3800"); + index_2("0.0040,0.0176,0.0344,0.0656,0.1120,0.2016,0.3800"); + values ("0.1613,0.1496,0.1379,0.1105,0.0715,0.0012,-0.1355",\ +"0.1730,0.1613,0.1496,0.1184,0.0832,0.0129,-0.1238",\ +"0.1887,0.1770,0.1652,0.1340,0.0988,0.0285,-0.1121",\ +"0.2121,0.2043,0.1887,0.1613,0.1223,0.0520,-0.0848",\ +"0.2551,0.2434,0.2277,0.2004,0.1613,0.0910,-0.0418",\ +"0.3293,0.3176,0.3020,0.2746,0.2395,0.1652,0.0324",\ +"0.4660,0.4543,0.4426,0.4113,0.3762,0.3020,0.1691"); + } + } + } +bus(A_BIST_BM) { + bus_type : D_7_0; + direction : input ; + capacitance : 0.00353394 ; + max_transition : "0.38" ; + pin(A_BIST_BM[7:0]) { + related_power_pin : VDD; + related_ground_pin : VSS; + internal_power() { + when : "A_BIST_MEN"; + rise_power("scalar"){ + values (0.0466); + } + fall_power("scalar"){ + values (0.0382); + } + } + internal_power() { + when : "!A_BIST_MEN"; + rise_power("scalar"){ + values (0.0552); + } + fall_power("scalar"){ + values (0.0440); + } + } + } + timing() { + timing_type : setup_rising; + related_pin : "A_BIST_CLK"; + when : "(A_BIST_WEN & A_BIST_MEN)" + sdf_cond : "A_BIST_RW_ACCESS" + + rise_constraint("SIG2SRAM_constraint_template") { + index_1("0.0040,0.0176,0.0344,0.0656,0.1120,0.2016,0.3800"); + index_2("0.0040,0.0176,0.0344,0.0656,0.1120,0.2016,0.3800"); + values ("-0.1725,-0.1618,-0.1462,-0.1208,-0.0798,-0.0065,0.1282",\ +"-0.1764,-0.1657,-0.1501,-0.1247,-0.0837,-0.0104,0.1243",\ +"-0.1801,-0.1694,-0.1537,-0.1284,-0.0873,-0.0141,0.1207",\ +"-0.1833,-0.1726,-0.1570,-0.1315,-0.0905,-0.0173,0.1175",\ +"-0.1959,-0.1852,-0.1696,-0.1442,-0.1032,-0.0299,0.1048",\ +"-0.2135,-0.2028,-0.1872,-0.1618,-0.1208,-0.0475,0.0872",\ +"-0.2410,-0.2303,-0.2147,-0.1893,-0.1483,-0.0750,0.0597"); + } + + fall_constraint("SIG2SRAM_constraint_template") { + index_1("0.0040,0.0176,0.0344,0.0656,0.1120,0.2016,0.3800"); + index_2("0.0040,0.0176,0.0344,0.0656,0.1120,0.2016,0.3800"); + values ("-0.1491,-0.1374,-0.1247,-0.0974,-0.0602,0.0130,0.1409",\ +"-0.1530,-0.1413,-0.1286,-0.1012,-0.0641,0.0091,0.1370",\ +"-0.1567,-0.1450,-0.1323,-0.1049,-0.0678,0.0054,0.1334",\ +"-0.1599,-0.1482,-0.1355,-0.1081,-0.0710,0.0022,0.1302",\ +"-0.1725,-0.1608,-0.1481,-0.1207,-0.0836,-0.0104,0.1175",\ +"-0.1901,-0.1784,-0.1657,-0.1383,-0.1012,-0.0280,0.0999",\ +"-0.2176,-0.2059,-0.1932,-0.1658,-0.1287,-0.0555,0.0724"); + } + } + + + timing() { + timing_type : hold_rising; + related_pin : "A_BIST_CLK"; + when : "(A_BIST_WEN & A_BIST_MEN)" + sdf_cond : "A_BIST_RW_ACCESS" + + rise_constraint("SIG2SRAM_constraint_template") { + index_1("0.0040,0.0176,0.0344,0.0656,0.1120,0.2016,0.3800"); + index_2("0.0040,0.0176,0.0344,0.0656,0.1120,0.2016,0.3800"); + values ("0.2776,0.2679,0.2522,0.2259,0.1887,0.1145,-0.0202",\ +"0.2815,0.2717,0.2561,0.2297,0.1926,0.1184,-0.0163",\ +"0.2852,0.2754,0.2598,0.2334,0.1963,0.1221,-0.0127",\ +"0.2884,0.2786,0.2630,0.2366,0.1995,0.1253,-0.0095",\ +"0.3010,0.2912,0.2756,0.2492,0.2121,0.1379,0.0032",\ +"0.3186,0.3088,0.2932,0.2668,0.2297,0.1555,0.0208",\ +"0.3461,0.3363,0.3207,0.2944,0.2572,0.1830,0.0483"); + } + + fall_constraint("SIG2SRAM_constraint_template") { + index_1("0.0040,0.0176,0.0344,0.0656,0.1120,0.2016,0.3800"); + index_2("0.0040,0.0176,0.0344,0.0656,0.1120,0.2016,0.3800"); + values ("0.2493,0.2386,0.2249,0.1975,0.1614,0.0891,-0.0407",\ +"0.2532,0.2424,0.2288,0.2014,0.1653,0.0930,-0.0369",\ +"0.2569,0.2461,0.2324,0.2051,0.1690,0.0967,-0.0332",\ +"0.2601,0.2493,0.2356,0.2083,0.1722,0.0999,-0.0300",\ +"0.2727,0.2619,0.2483,0.2209,0.1848,0.1125,-0.0174",\ +"0.2903,0.2796,0.2659,0.2385,0.2024,0.1301,0.0003",\ +"0.3178,0.3070,0.2934,0.2660,0.2299,0.1576,0.0278"); + } + } +} + pin(A_BIST_CLK) { + direction : input; + capacitance : 0.00389386; + max_transition : "0.38"; + clock : "true" ; + pin_func_type : active_rising ; + + timing () { + timing_type : "min_pulse_width"; + related_pin : "A_BIST_CLK"; + rise_constraint("CLKTRAN_constraint_template") { + index_1("0.004,0.38"); + values("0.12,0.12"); + } + } + + related_power_pin : VDD; + related_ground_pin : VSS; + + internal_power() { + when : "!A_BIST_MEN & !A_BIST_WEN & !A_BIST_REN"; + rise_power("scalar"){ + values (0); + } + fall_power("scalar"){ + values (0); + } + } + internal_power() { + when : "!A_BIST_MEN & A_BIST_WEN & !A_BIST_REN"; + rise_power("scalar"){ + values (0.6217); + } + fall_power("scalar"){ + values (0); + } + } + internal_power() { + when : "A_BIST_MEN & A_BIST_WEN & !A_BIST_REN"; + rise_power("scalar"){ + values (13.4151); + } + fall_power("scalar"){ + values (0); + } + } + internal_power() { + when : "A_BIST_MEN & A_BIST_WEN & A_BIST_REN"; + rise_power("scalar"){ + values (14.2183); + } + fall_power("scalar"){ + values (0); + } + } + internal_power() { + when : "A_BIST_MEN & !A_BIST_WEN & A_BIST_REN"; + rise_power("scalar"){ + values (10.4701); + } + fall_power("scalar"){ + values (0); + } + } + internal_power() { + when : "!A_BIST_MEN & !A_BIST_WEN & A_BIST_REN"; + rise_power("scalar"){ + values (0.3812); + } + fall_power("scalar"){ + values (0); + } + } + internal_power() { + when : "!A_BIST_MEN & A_BIST_WEN & A_BIST_REN"; + rise_power("scalar"){ + values (0.6439); + } + fall_power("scalar"){ + values (0); + } + } + internal_power() { + when : "A_BIST_MEN & !A_BIST_WEN & !A_BIST_REN"; + rise_power("scalar"){ + values (0); + } + fall_power("scalar"){ + values (0); + } + } + } + bus(A_BIST_DIN) { + bus_type : D_7_0; + direction : input ; + capacitance : 0.00397186 ; + memory_write() { + address : A_BIST_ADDR ; + clocked_on : A_BIST_CLK; + } + + max_transition : "0.38" ; + pin(A_BIST_DIN[7:0]) { + related_power_pin : VDD; + related_ground_pin : VSS; + internal_power() { + when : "A_BIST_MEN"; + rise_power("scalar"){ + values (0.0466); + } + fall_power("scalar"){ + values (0.0382); + } + } + internal_power() { + when : "!A_BIST_MEN"; + rise_power("scalar"){ + values (0.0552); + } + fall_power("scalar"){ + values (0.0440); + } + } + } + timing() { + timing_type : setup_rising; + related_pin : "A_BIST_CLK"; + when : "(A_BIST_WEN & A_BIST_MEN)"; + sdf_cond : "A_BIST_W_ACCESS"; + + rise_constraint("SIG2SRAM_constraint_template") { + index_1("0.0040,0.0176,0.0344,0.0656,0.1120,0.2016,0.3800"); + index_2("0.0040,0.0176,0.0344,0.0656,0.1120,0.2016,0.3800"); + values ("-0.1725,-0.1618,-0.1462,-0.1208,-0.0798,-0.0065,0.1282",\ +"-0.1764,-0.1657,-0.1501,-0.1247,-0.0837,-0.0104,0.1243",\ +"-0.1801,-0.1694,-0.1537,-0.1284,-0.0873,-0.0141,0.1207",\ +"-0.1833,-0.1726,-0.1570,-0.1315,-0.0905,-0.0173,0.1175",\ +"-0.1959,-0.1852,-0.1696,-0.1442,-0.1032,-0.0299,0.1048",\ +"-0.2135,-0.2028,-0.1872,-0.1618,-0.1208,-0.0475,0.0872",\ +"-0.2410,-0.2303,-0.2147,-0.1893,-0.1483,-0.0750,0.0597"); + } + + fall_constraint("SIG2SRAM_constraint_template") { + index_1("0.0040,0.0176,0.0344,0.0656,0.1120,0.2016,0.3800"); + index_2("0.0040,0.0176,0.0344,0.0656,0.1120,0.2016,0.3800"); + values ("-0.1491,-0.1374,-0.1247,-0.0974,-0.0602,0.0130,0.1409",\ +"-0.1530,-0.1413,-0.1286,-0.1012,-0.0641,0.0091,0.1370",\ +"-0.1567,-0.1450,-0.1323,-0.1049,-0.0678,0.0054,0.1334",\ +"-0.1599,-0.1482,-0.1355,-0.1081,-0.0710,0.0022,0.1302",\ +"-0.1725,-0.1608,-0.1481,-0.1207,-0.0836,-0.0104,0.1175",\ +"-0.1901,-0.1784,-0.1657,-0.1383,-0.1012,-0.0280,0.0999",\ +"-0.2176,-0.2059,-0.1932,-0.1658,-0.1287,-0.0555,0.0724"); + } + } + + timing() { + timing_type : hold_rising; + related_pin : "A_BIST_CLK"; + when : "(A_BIST_WEN & A_BIST_MEN)"; + sdf_cond : "A_BIST_W_ACCESS"; + + rise_constraint("SIG2SRAM_constraint_template") { + index_1("0.0040,0.0176,0.0344,0.0656,0.1120,0.2016,0.3800"); + index_2("0.0040,0.0176,0.0344,0.0656,0.1120,0.2016,0.3800"); + values ("0.2776,0.2679,0.2522,0.2259,0.1887,0.1145,-0.0202",\ +"0.2815,0.2717,0.2561,0.2297,0.1926,0.1184,-0.0163",\ +"0.2852,0.2754,0.2598,0.2334,0.1963,0.1221,-0.0127",\ +"0.2884,0.2786,0.2630,0.2366,0.1995,0.1253,-0.0095",\ +"0.3010,0.2912,0.2756,0.2492,0.2121,0.1379,0.0032",\ +"0.3186,0.3088,0.2932,0.2668,0.2297,0.1555,0.0208",\ +"0.3461,0.3363,0.3207,0.2944,0.2572,0.1830,0.0483"); + } + + fall_constraint("SIG2SRAM_constraint_template") { + index_1("0.0040,0.0176,0.0344,0.0656,0.1120,0.2016,0.3800"); + index_2("0.0040,0.0176,0.0344,0.0656,0.1120,0.2016,0.3800"); + values ("0.2493,0.2386,0.2249,0.1975,0.1614,0.0891,-0.0407",\ +"0.2532,0.2424,0.2288,0.2014,0.1653,0.0930,-0.0369",\ +"0.2569,0.2461,0.2324,0.2051,0.1690,0.0967,-0.0332",\ +"0.2601,0.2493,0.2356,0.2083,0.1722,0.0999,-0.0300",\ +"0.2727,0.2619,0.2483,0.2209,0.1848,0.1125,-0.0174",\ +"0.2903,0.2796,0.2659,0.2385,0.2024,0.1301,0.0003",\ +"0.3178,0.3070,0.2934,0.2660,0.2299,0.1576,0.0278"); + } + } + } + +bus(A_DOUT) { + + bus_type : D_7_0; + direction : output ; + capacitance : 0 ; + max_capacitance : 0.064 ; + memory_read() { + address : A_ADDR ; + } + pin(A_DOUT[7:0]) { + related_power_pin : VDD; + related_ground_pin : VSS; + internal_power() { + rise_power("scalar") { + values (0); + } + fall_power("scalar") { + values (0); + } + } + } + timing() { + related_pin : "A_CLK"; + timing_type : rising_edge ; + timing_sense : non_unate ; + + cell_rise(SIG2SRAM_delay_template) { + index_1("0.0040,0.0176,0.0344,0.0656,0.1120,0.2016,0.3800"); + index_2("0.0008,0.0014,0.0051,0.0100,0.0339,0.0640"); + values ("1.8251,1.8261,1.8309,1.8364,1.8573,1.8808",\ +"1.8310,1.8320,1.8369,1.8424,1.8633,1.8868",\ +"1.8338,1.8348,1.8396,1.8451,1.8660,1.8895",\ +"1.8380,1.8390,1.8438,1.8493,1.8702,1.8937",\ +"1.8496,1.8506,1.8554,1.8609,1.8819,1.9054",\ +"1.8687,1.8697,1.8746,1.8801,1.9010,1.9245",\ +"1.8951,1.8961,1.9009,1.9064,1.9274,1.9509"); + } + cell_fall(SIG2SRAM_delay_template) { + index_1("0.0040,0.0176,0.0344,0.0656,0.1120,0.2016,0.3800"); + index_2("0.0008,0.0014,0.0051,0.0100,0.0339,0.0640"); + values ("1.7908,1.7917,1.7957,1.8002,1.8173,1.8341",\ +"1.7968,1.7976,1.8016,1.8062,1.8233,1.8400",\ +"1.7995,1.8004,1.8044,1.8089,1.8260,1.8428",\ +"1.8037,1.8046,1.8086,1.8132,1.8302,1.8470",\ +"1.8153,1.8162,1.8202,1.8248,1.8419,1.8586",\ +"1.8344,1.8353,1.8393,1.8439,1.8610,1.8777",\ +"1.8608,1.8617,1.8657,1.8703,1.8874,1.9041"); + } + + rise_transition(SRAM_load_template) { + index_1("0.0008,0.0014,0.0051,0.0100,0.0339,0.0640"); + values ("0.0206,0.0210,0.0265,0.0323,0.0606,0.0955"); + } + fall_transition(SRAM_load_template) { + index_1("0.0008,0.0014,0.0051,0.0100,0.0339,0.0640"); + values ("0.0170,0.0177,0.0222,0.0270,0.0451,0.0644"); + } + } +} + pin(B_DLY) { + direction : input ; + capacitance : 0.00421562 ; + max_transition : "1" ; + related_power_pin : VDD; + related_ground_pin : VSS; + internal_power() { + rise_power("scalar") { + values (0); + } + fall_power("scalar") { + values (0); + } + } + } + +bus(B_ADDR) { + bus_type : A_7_0; + direction : input ; + capacitance : 0.0115194 ; + pin(B_ADDR[0]) { + capacitance : 0.0056487 ; + } + pin(B_ADDR[1]) { + capacitance : 0.00741688 ; + } + pin(B_ADDR[2]) { + capacitance : 0.0100613 ; + } + pin(B_ADDR[3]) { + capacitance : 0.00667339 ; + } + pin(B_ADDR[4]) { + capacitance : 0.00620204 ; + } + pin(B_ADDR[5]) { + capacitance : 0.0101975 ; + } + pin(B_ADDR[6]) { + capacitance : 0.0124055 ; + } + max_transition : "0.38" ; + pin(B_ADDR[7:0]) { + related_power_pin : VDD; + related_ground_pin : VSS; + internal_power() { + when : "B_MEN"; + rise_power("scalar"){ + values (0.0125); + } + fall_power("scalar"){ + values (0.0021); + } + } + internal_power() { + when : "!B_MEN"; + rise_power("scalar"){ + values (0.0265); + } + fall_power("scalar"){ + values (0.0015); + } + } + } + timing() { + timing_type : setup_rising; + related_pin : "B_CLK"; + when : "((B_WEN | B_REN)& B_MEN)" + sdf_cond : "B_RW_ACCESS" + + rise_constraint("SIG2SRAM_constraint_template") { + index_1("0.0040,0.0176,0.0344,0.0656,0.1120,0.2016,0.3800"); + index_2("0.0040,0.0176,0.0344,0.0656,0.1120,0.2016,0.3800"); + values ("-0.2371,-0.2215,-0.2098,-0.1824,-0.1434,-0.0691,0.0676",\ +"-0.2449,-0.2332,-0.2176,-0.1902,-0.1551,-0.0770,0.0559",\ +"-0.2605,-0.2488,-0.2332,-0.2059,-0.1707,-0.0965,0.0441",\ +"-0.2879,-0.2723,-0.2605,-0.2332,-0.1941,-0.1199,0.0168",\ +"-0.3230,-0.3113,-0.2996,-0.2723,-0.2332,-0.1590,-0.0184",\ +"-0.4012,-0.3895,-0.3738,-0.3465,-0.3074,-0.2332,-0.0965",\ +"-0.5379,-0.5262,-0.5105,-0.4832,-0.4480,-0.3699,-0.2332"); + } + + fall_constraint("SIG2SRAM_constraint_template") { + index_1("0.0040,0.0176,0.0344,0.0656,0.1120,0.2016,0.3800"); + index_2("0.0040,0.0176,0.0344,0.0656,0.1120,0.2016,0.3800"); + values ("-0.1785,-0.1707,-0.1551,-0.1277,-0.0887,-0.0184,0.1145",\ +"-0.1902,-0.1785,-0.1629,-0.1355,-0.1004,-0.0262,0.1027",\ +"-0.2059,-0.1941,-0.1785,-0.1512,-0.1160,-0.0418,0.0871",\ +"-0.2293,-0.2176,-0.2059,-0.1785,-0.1434,-0.0691,0.0598",\ +"-0.2684,-0.2566,-0.2449,-0.2176,-0.1824,-0.1082,0.0207",\ +"-0.3465,-0.3348,-0.3191,-0.2918,-0.2566,-0.1824,-0.0535",\ +"-0.4832,-0.4715,-0.4559,-0.4324,-0.3934,-0.3191,-0.1902"); + } + } + + + timing() { + timing_type : hold_rising; + related_pin : "B_CLK"; + when : "((B_WEN | B_REN)& B_MEN)" + sdf_cond : "B_RW_ACCESS" + + rise_constraint("SIG2SRAM_constraint_template") { + index_1("0.0040,0.0176,0.0344,0.0656,0.1120,0.2016,0.3800"); + index_2("0.0040,0.0176,0.0344,0.0656,0.1120,0.2016,0.3800"); + values ("0.3410,0.3293,0.3137,0.2863,0.2473,0.1730,0.0324",\ +"0.3488,0.3371,0.3215,0.2941,0.2590,0.1809,0.0480",\ +"0.3684,0.3527,0.3371,0.3098,0.2746,0.1965,0.0598",\ +"0.3918,0.3762,0.3645,0.3371,0.2980,0.2238,0.0871",\ +"0.4309,0.4152,0.4035,0.3762,0.3371,0.2629,0.1223",\ +"0.5051,0.4934,0.4777,0.4504,0.4113,0.3371,0.1965",\ +"0.6418,0.6262,0.6145,0.5871,0.5520,0.4738,0.3332"); + } + + fall_constraint("SIG2SRAM_constraint_template") { + index_1("0.0040,0.0176,0.0344,0.0656,0.1120,0.2016,0.3800"); + index_2("0.0040,0.0176,0.0344,0.0656,0.1120,0.2016,0.3800"); + values ("0.2824,0.2707,0.2551,0.2277,0.1926,0.1184,-0.0105",\ +"0.2902,0.2785,0.2668,0.2395,0.2043,0.1301,0.0012",\ +"0.3059,0.2941,0.2824,0.2551,0.2199,0.1457,0.0168",\ +"0.3332,0.3215,0.3059,0.2785,0.2434,0.1691,0.0402",\ +"0.3723,0.3605,0.3449,0.3176,0.2824,0.2121,0.0793",\ +"0.4465,0.4348,0.4230,0.3918,0.3566,0.2824,0.1535",\ +"0.5832,0.5715,0.5598,0.5324,0.4934,0.4191,0.2902"); + } + } +} +pin(B_WEN) { + direction : input ; + capacitance : 0.00341384 ; + max_transition : "0.38" ; + related_power_pin : VDD; + related_ground_pin : VSS; + internal_power() { + when : "B_MEN"; + rise_power("scalar"){ + values (0.0072); + } + fall_power("scalar"){ + values (0.0151); + } + } + internal_power() { + when : "!B_MEN"; + rise_power("scalar"){ + values (0.0057); + } + fall_power("scalar"){ + values (0.0206); + } + } + timing() { + timing_type : setup_rising; + related_pin : "B_CLK"; + when : "B_MEN" + sdf_cond : "B_MEN" + + rise_constraint("SIG2SRAM_constraint_template") { + index_1("0.0040,0.0176,0.0344,0.0656,0.1120,0.2016,0.3800"); + index_2("0.0040,0.0176,0.0344,0.0656,0.1120,0.2016,0.3800"); + values ("0.1418,0.1496,0.1652,0.1887,0.2316,0.3059,0.4465",\ +"0.1301,0.1379,0.1535,0.1809,0.2199,0.2941,0.4348",\ +"0.1145,0.1262,0.1379,0.1652,0.2043,0.2785,0.4191",\ +"0.0871,0.0949,0.1105,0.1379,0.1770,0.2512,0.3879",\ +"0.0480,0.0598,0.0754,0.0988,0.1379,0.2082,0.3527",\ +"-0.0262,-0.0145,0.0012,0.0246,0.0676,0.1379,0.2785",\ +"-0.1668,-0.1551,-0.1395,-0.1121,-0.0730,0.0012,0.1418"); + } + + fall_constraint("SIG2SRAM_constraint_template") { + index_1("0.0040,0.0176,0.0344,0.0656,0.1120,0.2016,0.3800"); + index_2("0.0040,0.0176,0.0344,0.0656,0.1120,0.2016,0.3800"); + values ("0.2082,0.2160,0.2316,0.2590,0.2941,0.3684,0.5012",\ +"0.1926,0.2043,0.2199,0.2473,0.2824,0.3566,0.4895",\ +"0.1770,0.1887,0.2043,0.2316,0.2668,0.3410,0.4777",\ +"0.1535,0.1652,0.1770,0.2043,0.2395,0.3137,0.4504",\ +"0.1145,0.1262,0.1379,0.1652,0.2043,0.2746,0.4113",\ +"0.0402,0.0520,0.0676,0.0910,0.1262,0.2004,0.3332",\ +"-0.0965,-0.0848,-0.0730,-0.0457,-0.0066,0.0637,0.2004"); + } + } + + + timing() { + timing_type : hold_rising; + related_pin : "B_CLK"; + when : "B_MEN" + sdf_cond : "B_MEN" + + rise_constraint("SIG2SRAM_constraint_template") { + index_1("0.0040,0.0176,0.0344,0.0656,0.1120,0.2016,0.3800"); + index_2("0.0040,0.0176,0.0344,0.0656,0.1120,0.2016,0.3800"); + values ("0.1770,0.1652,0.1496,0.1223,0.0793,0.0090,-0.1316",\ +"0.1848,0.1730,0.1574,0.1301,0.0910,0.0168,-0.1199",\ +"0.2004,0.1887,0.1770,0.1496,0.1066,0.0363,-0.1043",\ +"0.2277,0.2160,0.2004,0.1730,0.1340,0.0598,-0.0809",\ +"0.2668,0.2551,0.2395,0.2121,0.1730,0.0988,-0.0418",\ +"0.3410,0.3293,0.3137,0.2863,0.2434,0.1730,0.0324",\ +"0.4816,0.4699,0.4543,0.4230,0.3801,0.3098,0.1730"); + } + + fall_constraint("SIG2SRAM_constraint_template") { + index_1("0.0040,0.0176,0.0344,0.0656,0.1120,0.2016,0.3800"); + index_2("0.0040,0.0176,0.0344,0.0656,0.1120,0.2016,0.3800"); + values ("0.1613,0.1496,0.1379,0.1066,0.0715,0.0012,-0.1355",\ +"0.1730,0.1613,0.1457,0.1184,0.0832,0.0129,-0.1238",\ +"0.1887,0.1770,0.1613,0.1340,0.0988,0.0246,-0.1121",\ +"0.2121,0.2043,0.1887,0.1613,0.1223,0.0520,-0.0848",\ +"0.2512,0.2434,0.2277,0.2004,0.1613,0.0910,-0.0457",\ +"0.3254,0.3176,0.3020,0.2746,0.2355,0.1652,0.0324",\ +"0.4660,0.4543,0.4387,0.4113,0.3723,0.3020,0.1691"); + } + } + } +pin(B_REN) { + direction : input ; + capacitance : 0.00390661 ; + max_transition : "0.38" ; + related_power_pin : VDD; + related_ground_pin : VSS; + internal_power() { + when : "B_MEN"; + rise_power("scalar"){ + values (0.0101); + } + fall_power("scalar"){ + values (0.0103); + } + } + internal_power() { + when : "!B_MEN"; + rise_power("scalar"){ + values (0.0242); + } + fall_power("scalar"){ + values (0.0195); + } + } + timing() { + timing_type : setup_rising; + related_pin : "B_CLK"; + when : "B_MEN" + sdf_cond : "B_MEN" + + rise_constraint("SIG2SRAM_constraint_template") { + index_1("0.0040,0.0176,0.0344,0.0656,0.1120,0.2016,0.3800"); + index_2("0.0040,0.0176,0.0344,0.0656,0.1120,0.2016,0.3800"); + values ("-0.0027,0.0090,0.0246,0.0520,0.0910,0.1613,0.3020",\ +"-0.0105,0.0012,0.0129,0.0363,0.0793,0.1535,0.2902",\ +"-0.0262,-0.0145,-0.0027,0.0246,0.0637,0.1379,0.2785",\ +"-0.0535,-0.0418,-0.0262,0.0012,0.0363,0.1105,0.2512",\ +"-0.0926,-0.0809,-0.0652,-0.0418,-0.0027,0.0715,0.2121",\ +"-0.1668,-0.1551,-0.1395,-0.1082,-0.0770,-0.0027,0.1379",\ +"-0.3035,-0.2918,-0.2762,-0.2488,-0.2137,-0.1434,-0.0027"); + } + + fall_constraint("SIG2SRAM_constraint_template") { + index_1("0.0040,0.0176,0.0344,0.0656,0.1120,0.2016,0.3800"); + index_2("0.0040,0.0176,0.0344,0.0656,0.1120,0.2016,0.3800"); + values ("0.0832,0.0949,0.1105,0.1379,0.1730,0.2473,0.3801",\ +"0.0754,0.0832,0.0988,0.1223,0.1613,0.2355,0.3684",\ +"0.0598,0.0676,0.0832,0.1066,0.1457,0.2121,0.3527",\ +"0.0324,0.0441,0.0598,0.0871,0.1223,0.1926,0.3293",\ +"-0.0066,0.0051,0.0168,0.0480,0.0832,0.1535,0.2902",\ +"-0.0809,-0.0691,-0.0574,-0.0301,0.0090,0.0832,0.2121",\ +"-0.2176,-0.2059,-0.1941,-0.1668,-0.1277,-0.0574,0.0793"); + } + } + + + timing() { + timing_type : hold_rising; + related_pin : "B_CLK"; + when : "B_MEN" + sdf_cond : "B_MEN" + + rise_constraint("SIG2SRAM_constraint_template") { + index_1("0.0040,0.0176,0.0344,0.0656,0.1120,0.2016,0.3800"); + index_2("0.0040,0.0176,0.0344,0.0656,0.1120,0.2016,0.3800"); + values ("0.1887,0.1770,0.1613,0.1340,0.0949,0.0207,-0.1160",\ +"0.1965,0.1848,0.1730,0.1457,0.1027,0.0324,-0.1082",\ +"0.2160,0.2004,0.1887,0.1613,0.1184,0.0480,-0.0926",\ +"0.2395,0.2277,0.2121,0.1848,0.1457,0.0715,-0.0652",\ +"0.2785,0.2668,0.2512,0.2238,0.1848,0.1105,-0.0262",\ +"0.3527,0.3410,0.3254,0.2980,0.2551,0.1848,0.0480",\ +"0.4934,0.4816,0.4660,0.4387,0.3957,0.3254,0.1887"); + } + + fall_constraint("SIG2SRAM_constraint_template") { + index_1("0.0040,0.0176,0.0344,0.0656,0.1120,0.2016,0.3800"); + index_2("0.0040,0.0176,0.0344,0.0656,0.1120,0.2016,0.3800"); + values ("0.1730,0.1613,0.1496,0.1184,0.0793,0.0129,-0.1238",\ +"0.1848,0.1730,0.1574,0.1301,0.0910,0.0207,-0.1121",\ +"0.2004,0.1887,0.1730,0.1457,0.1066,0.0363,-0.1004",\ +"0.2238,0.2121,0.2004,0.1691,0.1340,0.0598,-0.0730",\ +"0.2629,0.2512,0.2395,0.2121,0.1691,0.0988,-0.0340",\ +"0.3371,0.3254,0.3137,0.2863,0.2434,0.1730,0.0402",\ +"0.4777,0.4660,0.4504,0.4230,0.3840,0.3137,0.1809"); + } + } + } +pin(B_MEN) { + direction : input ; + capacitance : 0.00326046 ; + max_transition : "0.38" ; + related_power_pin : VDD; + related_ground_pin : VSS; + internal_power() { + rise_power("scalar"){ + values (0.0779); + } + fall_power("scalar"){ + values (0.0107); + } + } + timing() { + timing_type : setup_rising; + related_pin : "B_CLK"; + + rise_constraint("SIG2SRAM_constraint_template") { + index_1("0.0040,0.0176,0.0344,0.0656,0.1120,0.2016,0.3800"); + index_2("0.0040,0.0176,0.0344,0.0656,0.1120,0.2016,0.3800"); + values ("0.1418,0.1496,0.1652,0.1926,0.2316,0.3059,0.4465",\ +"0.1301,0.1379,0.1535,0.1809,0.2199,0.2941,0.4348",\ +"0.1145,0.1262,0.1418,0.1652,0.2043,0.2785,0.4191",\ +"0.0871,0.0949,0.1105,0.1379,0.1770,0.2512,0.3879",\ +"0.0480,0.0598,0.0754,0.0988,0.1379,0.2082,0.3488",\ +"-0.0262,-0.0145,0.0012,0.0285,0.0676,0.1379,0.2785",\ +"-0.1668,-0.1551,-0.1395,-0.1121,-0.0730,0.0012,0.1379"); + } + + fall_constraint("SIG2SRAM_constraint_template") { + index_1("0.0040,0.0176,0.0344,0.0656,0.1120,0.2016,0.3800"); + index_2("0.0040,0.0176,0.0344,0.0656,0.1120,0.2016,0.3800"); + values ("0.2082,0.2199,0.2316,0.2590,0.2980,0.3723,0.5051",\ +"0.1965,0.2082,0.2199,0.2473,0.2863,0.3605,0.4934",\ +"0.1809,0.1926,0.2043,0.2316,0.2707,0.3449,0.4777",\ +"0.1574,0.1691,0.1809,0.2082,0.2434,0.3176,0.4543",\ +"0.1145,0.1262,0.1418,0.1691,0.2043,0.2785,0.4113",\ +"0.0441,0.0559,0.0676,0.0949,0.1301,0.2004,0.3332",\ +"-0.0965,-0.0848,-0.0691,-0.0418,-0.0066,0.0676,0.2004"); + } + } + + + timing() { + timing_type : hold_rising; + related_pin : "B_CLK"; + + rise_constraint("SIG2SRAM_constraint_template") { + index_1("0.0040,0.0176,0.0344,0.0656,0.1120,0.2016,0.3800"); + index_2("0.0040,0.0176,0.0344,0.0656,0.1120,0.2016,0.3800"); + values ("0.1770,0.1652,0.1535,0.1262,0.0832,0.0129,-0.1277",\ +"0.1887,0.1770,0.1613,0.1340,0.0949,0.0207,-0.1199",\ +"0.2043,0.1926,0.1770,0.1496,0.1105,0.0363,-0.1043",\ +"0.2277,0.2160,0.2043,0.1770,0.1379,0.0598,-0.0770",\ +"0.2668,0.2551,0.2434,0.2160,0.1730,0.0988,-0.0379",\ +"0.3449,0.3332,0.3176,0.2902,0.2473,0.1730,0.0363",\ +"0.4816,0.4699,0.4543,0.4270,0.3840,0.3098,0.1770"); + } + + fall_constraint("SIG2SRAM_constraint_template") { + index_1("0.0040,0.0176,0.0344,0.0656,0.1120,0.2016,0.3800"); + index_2("0.0040,0.0176,0.0344,0.0656,0.1120,0.2016,0.3800"); + values ("0.1613,0.1496,0.1379,0.1105,0.0715,0.0012,-0.1355",\ +"0.1730,0.1613,0.1496,0.1184,0.0832,0.0129,-0.1238",\ +"0.1887,0.1770,0.1652,0.1340,0.0988,0.0285,-0.1121",\ +"0.2121,0.2043,0.1887,0.1613,0.1223,0.0520,-0.0848",\ +"0.2551,0.2434,0.2277,0.2004,0.1613,0.0910,-0.0418",\ +"0.3293,0.3176,0.3020,0.2746,0.2395,0.1652,0.0324",\ +"0.4660,0.4543,0.4426,0.4113,0.3762,0.3020,0.1691"); + } + } + } +bus(B_BM) { + bus_type : D_7_0; + direction : input ; + capacitance : 0.00334781 ; + max_transition : "0.38" ; + pin(B_BM[7:0]) { + related_power_pin : VDD; + related_ground_pin : VSS; + internal_power() { + when : "B_MEN"; + rise_power("scalar"){ + values (0.0466); + } + fall_power("scalar"){ + values (0.0382); + } + } + internal_power() { + when : "!B_MEN"; + rise_power("scalar"){ + values (0.0552); + } + fall_power("scalar"){ + values (0.0440); + } + } + } + timing() { + timing_type : setup_rising; + related_pin : "B_CLK"; + when : "(B_WEN & B_MEN)" + sdf_cond : "B_RW_ACCESS" + + rise_constraint("SIG2SRAM_constraint_template") { + index_1("0.0040,0.0176,0.0344,0.0656,0.1120,0.2016,0.3800"); + index_2("0.0040,0.0176,0.0344,0.0656,0.1120,0.2016,0.3800"); + values ("-0.1725,-0.1618,-0.1462,-0.1208,-0.0798,-0.0065,0.1282",\ +"-0.1764,-0.1657,-0.1501,-0.1247,-0.0837,-0.0104,0.1243",\ +"-0.1801,-0.1694,-0.1537,-0.1284,-0.0873,-0.0141,0.1207",\ +"-0.1833,-0.1726,-0.1570,-0.1315,-0.0905,-0.0173,0.1175",\ +"-0.1959,-0.1852,-0.1696,-0.1442,-0.1032,-0.0299,0.1048",\ +"-0.2135,-0.2028,-0.1872,-0.1618,-0.1208,-0.0475,0.0872",\ +"-0.2410,-0.2303,-0.2147,-0.1893,-0.1483,-0.0750,0.0597"); + } + + fall_constraint("SIG2SRAM_constraint_template") { + index_1("0.0040,0.0176,0.0344,0.0656,0.1120,0.2016,0.3800"); + index_2("0.0040,0.0176,0.0344,0.0656,0.1120,0.2016,0.3800"); + values ("-0.1491,-0.1374,-0.1247,-0.0974,-0.0602,0.0130,0.1409",\ +"-0.1530,-0.1413,-0.1286,-0.1012,-0.0641,0.0091,0.1370",\ +"-0.1567,-0.1450,-0.1323,-0.1049,-0.0678,0.0054,0.1334",\ +"-0.1599,-0.1482,-0.1355,-0.1081,-0.0710,0.0022,0.1302",\ +"-0.1725,-0.1608,-0.1481,-0.1207,-0.0836,-0.0104,0.1175",\ +"-0.1901,-0.1784,-0.1657,-0.1383,-0.1012,-0.0280,0.0999",\ +"-0.2176,-0.2059,-0.1932,-0.1658,-0.1287,-0.0555,0.0724"); + } + } + + + timing() { + timing_type : hold_rising; + related_pin : "B_CLK"; + when : "(B_WEN & B_MEN)" + sdf_cond : "B_RW_ACCESS" + + rise_constraint("SIG2SRAM_constraint_template") { + index_1("0.0040,0.0176,0.0344,0.0656,0.1120,0.2016,0.3800"); + index_2("0.0040,0.0176,0.0344,0.0656,0.1120,0.2016,0.3800"); + values ("0.2776,0.2679,0.2522,0.2259,0.1887,0.1145,-0.0202",\ +"0.2815,0.2717,0.2561,0.2297,0.1926,0.1184,-0.0163",\ +"0.2852,0.2754,0.2598,0.2334,0.1963,0.1221,-0.0127",\ +"0.2884,0.2786,0.2630,0.2366,0.1995,0.1253,-0.0095",\ +"0.3010,0.2912,0.2756,0.2492,0.2121,0.1379,0.0032",\ +"0.3186,0.3088,0.2932,0.2668,0.2297,0.1555,0.0208",\ +"0.3461,0.3363,0.3207,0.2944,0.2572,0.1830,0.0483"); + } + + fall_constraint("SIG2SRAM_constraint_template") { + index_1("0.0040,0.0176,0.0344,0.0656,0.1120,0.2016,0.3800"); + index_2("0.0040,0.0176,0.0344,0.0656,0.1120,0.2016,0.3800"); + values ("0.2493,0.2386,0.2249,0.1975,0.1614,0.0891,-0.0407",\ +"0.2532,0.2424,0.2288,0.2014,0.1653,0.0930,-0.0369",\ +"0.2569,0.2461,0.2324,0.2051,0.1690,0.0967,-0.0332",\ +"0.2601,0.2493,0.2356,0.2083,0.1722,0.0999,-0.0300",\ +"0.2727,0.2619,0.2483,0.2209,0.1848,0.1125,-0.0174",\ +"0.2903,0.2796,0.2659,0.2385,0.2024,0.1301,0.0003",\ +"0.3178,0.3070,0.2934,0.2660,0.2299,0.1576,0.0278"); + } + } +} + pin(B_CLK) { + direction : input; + capacitance : 0.00389386; + max_transition : "0.38"; + clock : "true" ; + pin_func_type : active_rising ; + + timing () { + timing_type : "min_pulse_width"; + related_pin : "B_CLK"; + rise_constraint("CLKTRAN_constraint_template") { + index_1("0.004,0.38"); + values("0.12,0.12"); + } + } + + related_power_pin : VDD; + related_ground_pin : VSS; + + internal_power() { + when : "!B_MEN & !B_WEN & !B_REN"; + rise_power("scalar"){ + values (0); + } + fall_power("scalar"){ + values (0); + } + } + internal_power() { + when : "!B_MEN & B_WEN & !B_REN"; + rise_power("scalar"){ + values (0.6217); + } + fall_power("scalar"){ + values (0); + } + } + internal_power() { + when : "B_MEN & B_WEN & !B_REN"; + rise_power("scalar"){ + values (13.4151); + } + fall_power("scalar"){ + values (0); + } + } + internal_power() { + when : "B_MEN & B_WEN & B_REN"; + rise_power("scalar"){ + values (14.2183); + } + fall_power("scalar"){ + values (0); + } + } + internal_power() { + when : "B_MEN & !B_WEN & B_REN"; + rise_power("scalar"){ + values (10.4701); + } + fall_power("scalar"){ + values (0); + } + } + internal_power() { + when : "!B_MEN & !B_WEN & B_REN"; + rise_power("scalar"){ + values (0.3812); + } + fall_power("scalar"){ + values (0); + } + } + internal_power() { + when : "!B_MEN & B_WEN & B_REN"; + rise_power("scalar"){ + values (0.6439); + } + fall_power("scalar"){ + values (0); + } + } + internal_power() { + when : "B_MEN & !B_WEN & !B_REN"; + rise_power("scalar"){ + values (0); + } + fall_power("scalar"){ + values (0); + } + } + } + bus(B_DIN) { + bus_type : D_7_0; + direction : input ; + capacitance : 0.00468868 ; + memory_write() { + address : B_ADDR ; + clocked_on : B_CLK; + } + + max_transition : "0.38" ; + pin(B_DIN[7:0]) { + related_power_pin : VDD; + related_ground_pin : VSS; + internal_power() { + when : "B_MEN"; + rise_power("scalar"){ + values (0.0466); + } + fall_power("scalar"){ + values (0.0382); + } + } + internal_power() { + when : "!B_MEN"; + rise_power("scalar"){ + values (0.0552); + } + fall_power("scalar"){ + values (0.0440); + } + } + } + timing() { + timing_type : setup_rising; + related_pin : "B_CLK"; + when : "(B_WEN & B_MEN)"; + sdf_cond : "B_W_ACCESS"; + + rise_constraint("SIG2SRAM_constraint_template") { + index_1("0.0040,0.0176,0.0344,0.0656,0.1120,0.2016,0.3800"); + index_2("0.0040,0.0176,0.0344,0.0656,0.1120,0.2016,0.3800"); + values ("-0.1725,-0.1618,-0.1462,-0.1208,-0.0798,-0.0065,0.1282",\ +"-0.1764,-0.1657,-0.1501,-0.1247,-0.0837,-0.0104,0.1243",\ +"-0.1801,-0.1694,-0.1537,-0.1284,-0.0873,-0.0141,0.1207",\ +"-0.1833,-0.1726,-0.1570,-0.1315,-0.0905,-0.0173,0.1175",\ +"-0.1959,-0.1852,-0.1696,-0.1442,-0.1032,-0.0299,0.1048",\ +"-0.2135,-0.2028,-0.1872,-0.1618,-0.1208,-0.0475,0.0872",\ +"-0.2410,-0.2303,-0.2147,-0.1893,-0.1483,-0.0750,0.0597"); + } + + fall_constraint("SIG2SRAM_constraint_template") { + index_1("0.0040,0.0176,0.0344,0.0656,0.1120,0.2016,0.3800"); + index_2("0.0040,0.0176,0.0344,0.0656,0.1120,0.2016,0.3800"); + values ("-0.1491,-0.1374,-0.1247,-0.0974,-0.0602,0.0130,0.1409",\ +"-0.1530,-0.1413,-0.1286,-0.1012,-0.0641,0.0091,0.1370",\ +"-0.1567,-0.1450,-0.1323,-0.1049,-0.0678,0.0054,0.1334",\ +"-0.1599,-0.1482,-0.1355,-0.1081,-0.0710,0.0022,0.1302",\ +"-0.1725,-0.1608,-0.1481,-0.1207,-0.0836,-0.0104,0.1175",\ +"-0.1901,-0.1784,-0.1657,-0.1383,-0.1012,-0.0280,0.0999",\ +"-0.2176,-0.2059,-0.1932,-0.1658,-0.1287,-0.0555,0.0724"); + } + } + + timing() { + timing_type : hold_rising; + related_pin : "B_CLK"; + when : "(B_WEN & B_MEN)"; + sdf_cond : "B_W_ACCESS"; + + rise_constraint("SIG2SRAM_constraint_template") { + index_1("0.0040,0.0176,0.0344,0.0656,0.1120,0.2016,0.3800"); + index_2("0.0040,0.0176,0.0344,0.0656,0.1120,0.2016,0.3800"); + values ("0.2776,0.2679,0.2522,0.2259,0.1887,0.1145,-0.0202",\ +"0.2815,0.2717,0.2561,0.2297,0.1926,0.1184,-0.0163",\ +"0.2852,0.2754,0.2598,0.2334,0.1963,0.1221,-0.0127",\ +"0.2884,0.2786,0.2630,0.2366,0.1995,0.1253,-0.0095",\ +"0.3010,0.2912,0.2756,0.2492,0.2121,0.1379,0.0032",\ +"0.3186,0.3088,0.2932,0.2668,0.2297,0.1555,0.0208",\ +"0.3461,0.3363,0.3207,0.2944,0.2572,0.1830,0.0483"); + } + + fall_constraint("SIG2SRAM_constraint_template") { + index_1("0.0040,0.0176,0.0344,0.0656,0.1120,0.2016,0.3800"); + index_2("0.0040,0.0176,0.0344,0.0656,0.1120,0.2016,0.3800"); + values ("0.2493,0.2386,0.2249,0.1975,0.1614,0.0891,-0.0407",\ +"0.2532,0.2424,0.2288,0.2014,0.1653,0.0930,-0.0369",\ +"0.2569,0.2461,0.2324,0.2051,0.1690,0.0967,-0.0332",\ +"0.2601,0.2493,0.2356,0.2083,0.1722,0.0999,-0.0300",\ +"0.2727,0.2619,0.2483,0.2209,0.1848,0.1125,-0.0174",\ +"0.2903,0.2796,0.2659,0.2385,0.2024,0.1301,0.0003",\ +"0.3178,0.3070,0.2934,0.2660,0.2299,0.1576,0.0278"); + } + } + } + + pin(B_BIST_EN) { + direction : input ; + capacitance : 0.00421562 ; + max_transition : "1" ; + related_power_pin : VDD; + related_ground_pin : VSS; + internal_power() { + rise_power("scalar") { + values (0); + } + fall_power("scalar") { + values (0); + } + } + } + +bus(B_BIST_ADDR) { + bus_type : A_7_0; + direction : input ; + capacitance : 0.0115194 ; + pin(B_BIST_ADDR[0]) { + capacitance : 0.0056487 ; + } + pin(B_BIST_ADDR[1]) { + capacitance : 0.00741688 ; + } + pin(B_BIST_ADDR[2]) { + capacitance : 0.0100613 ; + } + pin(B_BIST_ADDR[3]) { + capacitance : 0.00667339 ; + } + pin(B_BIST_ADDR[4]) { + capacitance : 0.00620204 ; + } + pin(B_BIST_ADDR[5]) { + capacitance : 0.0101975 ; + } + pin(B_BIST_ADDR[6]) { + capacitance : 0.0124055 ; + } + max_transition : "0.38" ; + pin(B_BIST_ADDR[7:0]) { + related_power_pin : VDD; + related_ground_pin : VSS; + internal_power() { + when : "B_BIST_MEN"; + rise_power("scalar"){ + values (0.0125); + } + fall_power("scalar"){ + values (0.0021); + } + } + internal_power() { + when : "!B_BIST_MEN"; + rise_power("scalar"){ + values (0.0265); + } + fall_power("scalar"){ + values (0.0015); + } + } + } + timing() { + timing_type : setup_rising; + related_pin : "B_BIST_CLK"; + when : "((B_BIST_WEN | B_BIST_REN)& B_BIST_MEN)" + sdf_cond : "B_BIST_RW_ACCESS" + + rise_constraint("SIG2SRAM_constraint_template") { + index_1("0.0040,0.0176,0.0344,0.0656,0.1120,0.2016,0.3800"); + index_2("0.0040,0.0176,0.0344,0.0656,0.1120,0.2016,0.3800"); + values ("-0.2371,-0.2215,-0.2098,-0.1824,-0.1434,-0.0691,0.0676",\ +"-0.2449,-0.2332,-0.2176,-0.1902,-0.1551,-0.0770,0.0559",\ +"-0.2605,-0.2488,-0.2332,-0.2059,-0.1707,-0.0965,0.0441",\ +"-0.2879,-0.2723,-0.2605,-0.2332,-0.1941,-0.1199,0.0168",\ +"-0.3230,-0.3113,-0.2996,-0.2723,-0.2332,-0.1590,-0.0184",\ +"-0.4012,-0.3895,-0.3738,-0.3465,-0.3074,-0.2332,-0.0965",\ +"-0.5379,-0.5262,-0.5105,-0.4832,-0.4480,-0.3699,-0.2332"); + } + + fall_constraint("SIG2SRAM_constraint_template") { + index_1("0.0040,0.0176,0.0344,0.0656,0.1120,0.2016,0.3800"); + index_2("0.0040,0.0176,0.0344,0.0656,0.1120,0.2016,0.3800"); + values ("-0.1785,-0.1707,-0.1551,-0.1277,-0.0887,-0.0184,0.1145",\ +"-0.1902,-0.1785,-0.1629,-0.1355,-0.1004,-0.0262,0.1027",\ +"-0.2059,-0.1941,-0.1785,-0.1512,-0.1160,-0.0418,0.0871",\ +"-0.2293,-0.2176,-0.2059,-0.1785,-0.1434,-0.0691,0.0598",\ +"-0.2684,-0.2566,-0.2449,-0.2176,-0.1824,-0.1082,0.0207",\ +"-0.3465,-0.3348,-0.3191,-0.2918,-0.2566,-0.1824,-0.0535",\ +"-0.4832,-0.4715,-0.4559,-0.4324,-0.3934,-0.3191,-0.1902"); + } + } + + + timing() { + timing_type : hold_rising; + related_pin : "B_BIST_CLK"; + when : "((B_BIST_WEN | B_BIST_REN)& B_BIST_MEN)" + sdf_cond : "B_BIST_RW_ACCESS" + + rise_constraint("SIG2SRAM_constraint_template") { + index_1("0.0040,0.0176,0.0344,0.0656,0.1120,0.2016,0.3800"); + index_2("0.0040,0.0176,0.0344,0.0656,0.1120,0.2016,0.3800"); + values ("0.3410,0.3293,0.3137,0.2863,0.2473,0.1730,0.0324",\ +"0.3488,0.3371,0.3215,0.2941,0.2590,0.1809,0.0480",\ +"0.3684,0.3527,0.3371,0.3098,0.2746,0.1965,0.0598",\ +"0.3918,0.3762,0.3645,0.3371,0.2980,0.2238,0.0871",\ +"0.4309,0.4152,0.4035,0.3762,0.3371,0.2629,0.1223",\ +"0.5051,0.4934,0.4777,0.4504,0.4113,0.3371,0.1965",\ +"0.6418,0.6262,0.6145,0.5871,0.5520,0.4738,0.3332"); + } + + fall_constraint("SIG2SRAM_constraint_template") { + index_1("0.0040,0.0176,0.0344,0.0656,0.1120,0.2016,0.3800"); + index_2("0.0040,0.0176,0.0344,0.0656,0.1120,0.2016,0.3800"); + values ("0.2824,0.2707,0.2551,0.2277,0.1926,0.1184,-0.0105",\ +"0.2902,0.2785,0.2668,0.2395,0.2043,0.1301,0.0012",\ +"0.3059,0.2941,0.2824,0.2551,0.2199,0.1457,0.0168",\ +"0.3332,0.3215,0.3059,0.2785,0.2434,0.1691,0.0402",\ +"0.3723,0.3605,0.3449,0.3176,0.2824,0.2121,0.0793",\ +"0.4465,0.4348,0.4230,0.3918,0.3566,0.2824,0.1535",\ +"0.5832,0.5715,0.5598,0.5324,0.4934,0.4191,0.2902"); + } + } +} +pin(B_BIST_WEN) { + direction : input ; + capacitance : 0.00341384 ; + max_transition : "0.38" ; + related_power_pin : VDD; + related_ground_pin : VSS; + internal_power() { + when : "B_BIST_MEN"; + rise_power("scalar"){ + values (0.0072); + } + fall_power("scalar"){ + values (0.0151); + } + } + internal_power() { + when : "!B_BIST_MEN"; + rise_power("scalar"){ + values (0.0057); + } + fall_power("scalar"){ + values (0.0206); + } + } + timing() { + timing_type : setup_rising; + related_pin : "B_BIST_CLK"; + when : "B_BIST_MEN" + sdf_cond : "B_BIST_MEN" + + rise_constraint("SIG2SRAM_constraint_template") { + index_1("0.0040,0.0176,0.0344,0.0656,0.1120,0.2016,0.3800"); + index_2("0.0040,0.0176,0.0344,0.0656,0.1120,0.2016,0.3800"); + values ("0.1418,0.1496,0.1652,0.1887,0.2316,0.3059,0.4465",\ +"0.1301,0.1379,0.1535,0.1809,0.2199,0.2941,0.4348",\ +"0.1145,0.1262,0.1379,0.1652,0.2043,0.2785,0.4191",\ +"0.0871,0.0949,0.1105,0.1379,0.1770,0.2512,0.3879",\ +"0.0480,0.0598,0.0754,0.0988,0.1379,0.2082,0.3527",\ +"-0.0262,-0.0145,0.0012,0.0246,0.0676,0.1379,0.2785",\ +"-0.1668,-0.1551,-0.1395,-0.1121,-0.0730,0.0012,0.1418"); + } + + fall_constraint("SIG2SRAM_constraint_template") { + index_1("0.0040,0.0176,0.0344,0.0656,0.1120,0.2016,0.3800"); + index_2("0.0040,0.0176,0.0344,0.0656,0.1120,0.2016,0.3800"); + values ("0.2082,0.2160,0.2316,0.2590,0.2941,0.3684,0.5012",\ +"0.1926,0.2043,0.2199,0.2473,0.2824,0.3566,0.4895",\ +"0.1770,0.1887,0.2043,0.2316,0.2668,0.3410,0.4777",\ +"0.1535,0.1652,0.1770,0.2043,0.2395,0.3137,0.4504",\ +"0.1145,0.1262,0.1379,0.1652,0.2043,0.2746,0.4113",\ +"0.0402,0.0520,0.0676,0.0910,0.1262,0.2004,0.3332",\ +"-0.0965,-0.0848,-0.0730,-0.0457,-0.0066,0.0637,0.2004"); + } + } + + + timing() { + timing_type : hold_rising; + related_pin : "B_BIST_CLK"; + when : "B_BIST_MEN" + sdf_cond : "B_BIST_MEN" + + rise_constraint("SIG2SRAM_constraint_template") { + index_1("0.0040,0.0176,0.0344,0.0656,0.1120,0.2016,0.3800"); + index_2("0.0040,0.0176,0.0344,0.0656,0.1120,0.2016,0.3800"); + values ("0.1770,0.1652,0.1496,0.1223,0.0793,0.0090,-0.1316",\ +"0.1848,0.1730,0.1574,0.1301,0.0910,0.0168,-0.1199",\ +"0.2004,0.1887,0.1770,0.1496,0.1066,0.0363,-0.1043",\ +"0.2277,0.2160,0.2004,0.1730,0.1340,0.0598,-0.0809",\ +"0.2668,0.2551,0.2395,0.2121,0.1730,0.0988,-0.0418",\ +"0.3410,0.3293,0.3137,0.2863,0.2434,0.1730,0.0324",\ +"0.4816,0.4699,0.4543,0.4230,0.3801,0.3098,0.1730"); + } + + fall_constraint("SIG2SRAM_constraint_template") { + index_1("0.0040,0.0176,0.0344,0.0656,0.1120,0.2016,0.3800"); + index_2("0.0040,0.0176,0.0344,0.0656,0.1120,0.2016,0.3800"); + values ("0.1613,0.1496,0.1379,0.1066,0.0715,0.0012,-0.1355",\ +"0.1730,0.1613,0.1457,0.1184,0.0832,0.0129,-0.1238",\ +"0.1887,0.1770,0.1613,0.1340,0.0988,0.0246,-0.1121",\ +"0.2121,0.2043,0.1887,0.1613,0.1223,0.0520,-0.0848",\ +"0.2512,0.2434,0.2277,0.2004,0.1613,0.0910,-0.0457",\ +"0.3254,0.3176,0.3020,0.2746,0.2355,0.1652,0.0324",\ +"0.4660,0.4543,0.4387,0.4113,0.3723,0.3020,0.1691"); + } + } + } +pin(B_BIST_REN) { + direction : input ; + capacitance : 0.00390661 ; + max_transition : "0.38" ; + related_power_pin : VDD; + related_ground_pin : VSS; + internal_power() { + when : "B_BIST_MEN"; + rise_power("scalar"){ + values (0.0101); + } + fall_power("scalar"){ + values (0.0103); + } + } + internal_power() { + when : "!B_BIST_MEN"; + rise_power("scalar"){ + values (0.0242); + } + fall_power("scalar"){ + values (0.0195); + } + } + timing() { + timing_type : setup_rising; + related_pin : "B_BIST_CLK"; + when : "B_BIST_MEN" + sdf_cond : "B_BIST_MEN" + + rise_constraint("SIG2SRAM_constraint_template") { + index_1("0.0040,0.0176,0.0344,0.0656,0.1120,0.2016,0.3800"); + index_2("0.0040,0.0176,0.0344,0.0656,0.1120,0.2016,0.3800"); + values ("-0.0027,0.0090,0.0246,0.0520,0.0910,0.1613,0.3020",\ +"-0.0105,0.0012,0.0129,0.0363,0.0793,0.1535,0.2902",\ +"-0.0262,-0.0145,-0.0027,0.0246,0.0637,0.1379,0.2785",\ +"-0.0535,-0.0418,-0.0262,0.0012,0.0363,0.1105,0.2512",\ +"-0.0926,-0.0809,-0.0652,-0.0418,-0.0027,0.0715,0.2121",\ +"-0.1668,-0.1551,-0.1395,-0.1082,-0.0770,-0.0027,0.1379",\ +"-0.3035,-0.2918,-0.2762,-0.2488,-0.2137,-0.1434,-0.0027"); + } + + fall_constraint("SIG2SRAM_constraint_template") { + index_1("0.0040,0.0176,0.0344,0.0656,0.1120,0.2016,0.3800"); + index_2("0.0040,0.0176,0.0344,0.0656,0.1120,0.2016,0.3800"); + values ("0.0832,0.0949,0.1105,0.1379,0.1730,0.2473,0.3801",\ +"0.0754,0.0832,0.0988,0.1223,0.1613,0.2355,0.3684",\ +"0.0598,0.0676,0.0832,0.1066,0.1457,0.2121,0.3527",\ +"0.0324,0.0441,0.0598,0.0871,0.1223,0.1926,0.3293",\ +"-0.0066,0.0051,0.0168,0.0480,0.0832,0.1535,0.2902",\ +"-0.0809,-0.0691,-0.0574,-0.0301,0.0090,0.0832,0.2121",\ +"-0.2176,-0.2059,-0.1941,-0.1668,-0.1277,-0.0574,0.0793"); + } + } + + + timing() { + timing_type : hold_rising; + related_pin : "B_BIST_CLK"; + when : "B_BIST_MEN" + sdf_cond : "B_BIST_MEN" + + rise_constraint("SIG2SRAM_constraint_template") { + index_1("0.0040,0.0176,0.0344,0.0656,0.1120,0.2016,0.3800"); + index_2("0.0040,0.0176,0.0344,0.0656,0.1120,0.2016,0.3800"); + values ("0.1887,0.1770,0.1613,0.1340,0.0949,0.0207,-0.1160",\ +"0.1965,0.1848,0.1730,0.1457,0.1027,0.0324,-0.1082",\ +"0.2160,0.2004,0.1887,0.1613,0.1184,0.0480,-0.0926",\ +"0.2395,0.2277,0.2121,0.1848,0.1457,0.0715,-0.0652",\ +"0.2785,0.2668,0.2512,0.2238,0.1848,0.1105,-0.0262",\ +"0.3527,0.3410,0.3254,0.2980,0.2551,0.1848,0.0480",\ +"0.4934,0.4816,0.4660,0.4387,0.3957,0.3254,0.1887"); + } + + fall_constraint("SIG2SRAM_constraint_template") { + index_1("0.0040,0.0176,0.0344,0.0656,0.1120,0.2016,0.3800"); + index_2("0.0040,0.0176,0.0344,0.0656,0.1120,0.2016,0.3800"); + values ("0.1730,0.1613,0.1496,0.1184,0.0793,0.0129,-0.1238",\ +"0.1848,0.1730,0.1574,0.1301,0.0910,0.0207,-0.1121",\ +"0.2004,0.1887,0.1730,0.1457,0.1066,0.0363,-0.1004",\ +"0.2238,0.2121,0.2004,0.1691,0.1340,0.0598,-0.0730",\ +"0.2629,0.2512,0.2395,0.2121,0.1691,0.0988,-0.0340",\ +"0.3371,0.3254,0.3137,0.2863,0.2434,0.1730,0.0402",\ +"0.4777,0.4660,0.4504,0.4230,0.3840,0.3137,0.1809"); + } + } + } +pin(B_BIST_MEN) { + direction : input ; + capacitance : 0.00326046 ; + max_transition : "0.38" ; + related_power_pin : VDD; + related_ground_pin : VSS; + internal_power() { + rise_power("scalar"){ + values (0.0779); + } + fall_power("scalar"){ + values (0.0107); + } + } + timing() { + timing_type : setup_rising; + related_pin : "B_BIST_CLK"; + + rise_constraint("SIG2SRAM_constraint_template") { + index_1("0.0040,0.0176,0.0344,0.0656,0.1120,0.2016,0.3800"); + index_2("0.0040,0.0176,0.0344,0.0656,0.1120,0.2016,0.3800"); + values ("0.1418,0.1496,0.1652,0.1926,0.2316,0.3059,0.4465",\ +"0.1301,0.1379,0.1535,0.1809,0.2199,0.2941,0.4348",\ +"0.1145,0.1262,0.1418,0.1652,0.2043,0.2785,0.4191",\ +"0.0871,0.0949,0.1105,0.1379,0.1770,0.2512,0.3879",\ +"0.0480,0.0598,0.0754,0.0988,0.1379,0.2082,0.3488",\ +"-0.0262,-0.0145,0.0012,0.0285,0.0676,0.1379,0.2785",\ +"-0.1668,-0.1551,-0.1395,-0.1121,-0.0730,0.0012,0.1379"); + } + + fall_constraint("SIG2SRAM_constraint_template") { + index_1("0.0040,0.0176,0.0344,0.0656,0.1120,0.2016,0.3800"); + index_2("0.0040,0.0176,0.0344,0.0656,0.1120,0.2016,0.3800"); + values ("0.2082,0.2199,0.2316,0.2590,0.2980,0.3723,0.5051",\ +"0.1965,0.2082,0.2199,0.2473,0.2863,0.3605,0.4934",\ +"0.1809,0.1926,0.2043,0.2316,0.2707,0.3449,0.4777",\ +"0.1574,0.1691,0.1809,0.2082,0.2434,0.3176,0.4543",\ +"0.1145,0.1262,0.1418,0.1691,0.2043,0.2785,0.4113",\ +"0.0441,0.0559,0.0676,0.0949,0.1301,0.2004,0.3332",\ +"-0.0965,-0.0848,-0.0691,-0.0418,-0.0066,0.0676,0.2004"); + } + } + + + timing() { + timing_type : hold_rising; + related_pin : "B_BIST_CLK"; + + rise_constraint("SIG2SRAM_constraint_template") { + index_1("0.0040,0.0176,0.0344,0.0656,0.1120,0.2016,0.3800"); + index_2("0.0040,0.0176,0.0344,0.0656,0.1120,0.2016,0.3800"); + values ("0.1770,0.1652,0.1535,0.1262,0.0832,0.0129,-0.1277",\ +"0.1887,0.1770,0.1613,0.1340,0.0949,0.0207,-0.1199",\ +"0.2043,0.1926,0.1770,0.1496,0.1105,0.0363,-0.1043",\ +"0.2277,0.2160,0.2043,0.1770,0.1379,0.0598,-0.0770",\ +"0.2668,0.2551,0.2434,0.2160,0.1730,0.0988,-0.0379",\ +"0.3449,0.3332,0.3176,0.2902,0.2473,0.1730,0.0363",\ +"0.4816,0.4699,0.4543,0.4270,0.3840,0.3098,0.1770"); + } + + fall_constraint("SIG2SRAM_constraint_template") { + index_1("0.0040,0.0176,0.0344,0.0656,0.1120,0.2016,0.3800"); + index_2("0.0040,0.0176,0.0344,0.0656,0.1120,0.2016,0.3800"); + values ("0.1613,0.1496,0.1379,0.1105,0.0715,0.0012,-0.1355",\ +"0.1730,0.1613,0.1496,0.1184,0.0832,0.0129,-0.1238",\ +"0.1887,0.1770,0.1652,0.1340,0.0988,0.0285,-0.1121",\ +"0.2121,0.2043,0.1887,0.1613,0.1223,0.0520,-0.0848",\ +"0.2551,0.2434,0.2277,0.2004,0.1613,0.0910,-0.0418",\ +"0.3293,0.3176,0.3020,0.2746,0.2395,0.1652,0.0324",\ +"0.4660,0.4543,0.4426,0.4113,0.3762,0.3020,0.1691"); + } + } + } +bus(B_BIST_BM) { + bus_type : D_7_0; + direction : input ; + capacitance : 0.00290564 ; + max_transition : "0.38" ; + pin(B_BIST_BM[7:0]) { + related_power_pin : VDD; + related_ground_pin : VSS; + internal_power() { + when : "B_BIST_MEN"; + rise_power("scalar"){ + values (0.0466); + } + fall_power("scalar"){ + values (0.0382); + } + } + internal_power() { + when : "!B_BIST_MEN"; + rise_power("scalar"){ + values (0.0552); + } + fall_power("scalar"){ + values (0.0440); + } + } + } + timing() { + timing_type : setup_rising; + related_pin : "B_BIST_CLK"; + when : "(B_BIST_WEN & B_BIST_MEN)" + sdf_cond : "B_BIST_RW_ACCESS" + + rise_constraint("SIG2SRAM_constraint_template") { + index_1("0.0040,0.0176,0.0344,0.0656,0.1120,0.2016,0.3800"); + index_2("0.0040,0.0176,0.0344,0.0656,0.1120,0.2016,0.3800"); + values ("-0.1725,-0.1618,-0.1462,-0.1208,-0.0798,-0.0065,0.1282",\ +"-0.1764,-0.1657,-0.1501,-0.1247,-0.0837,-0.0104,0.1243",\ +"-0.1801,-0.1694,-0.1537,-0.1284,-0.0873,-0.0141,0.1207",\ +"-0.1833,-0.1726,-0.1570,-0.1315,-0.0905,-0.0173,0.1175",\ +"-0.1959,-0.1852,-0.1696,-0.1442,-0.1032,-0.0299,0.1048",\ +"-0.2135,-0.2028,-0.1872,-0.1618,-0.1208,-0.0475,0.0872",\ +"-0.2410,-0.2303,-0.2147,-0.1893,-0.1483,-0.0750,0.0597"); + } + + fall_constraint("SIG2SRAM_constraint_template") { + index_1("0.0040,0.0176,0.0344,0.0656,0.1120,0.2016,0.3800"); + index_2("0.0040,0.0176,0.0344,0.0656,0.1120,0.2016,0.3800"); + values ("-0.1491,-0.1374,-0.1247,-0.0974,-0.0602,0.0130,0.1409",\ +"-0.1530,-0.1413,-0.1286,-0.1012,-0.0641,0.0091,0.1370",\ +"-0.1567,-0.1450,-0.1323,-0.1049,-0.0678,0.0054,0.1334",\ +"-0.1599,-0.1482,-0.1355,-0.1081,-0.0710,0.0022,0.1302",\ +"-0.1725,-0.1608,-0.1481,-0.1207,-0.0836,-0.0104,0.1175",\ +"-0.1901,-0.1784,-0.1657,-0.1383,-0.1012,-0.0280,0.0999",\ +"-0.2176,-0.2059,-0.1932,-0.1658,-0.1287,-0.0555,0.0724"); + } + } + + + timing() { + timing_type : hold_rising; + related_pin : "B_BIST_CLK"; + when : "(B_BIST_WEN & B_BIST_MEN)" + sdf_cond : "B_BIST_RW_ACCESS" + + rise_constraint("SIG2SRAM_constraint_template") { + index_1("0.0040,0.0176,0.0344,0.0656,0.1120,0.2016,0.3800"); + index_2("0.0040,0.0176,0.0344,0.0656,0.1120,0.2016,0.3800"); + values ("0.2776,0.2679,0.2522,0.2259,0.1887,0.1145,-0.0202",\ +"0.2815,0.2717,0.2561,0.2297,0.1926,0.1184,-0.0163",\ +"0.2852,0.2754,0.2598,0.2334,0.1963,0.1221,-0.0127",\ +"0.2884,0.2786,0.2630,0.2366,0.1995,0.1253,-0.0095",\ +"0.3010,0.2912,0.2756,0.2492,0.2121,0.1379,0.0032",\ +"0.3186,0.3088,0.2932,0.2668,0.2297,0.1555,0.0208",\ +"0.3461,0.3363,0.3207,0.2944,0.2572,0.1830,0.0483"); + } + + fall_constraint("SIG2SRAM_constraint_template") { + index_1("0.0040,0.0176,0.0344,0.0656,0.1120,0.2016,0.3800"); + index_2("0.0040,0.0176,0.0344,0.0656,0.1120,0.2016,0.3800"); + values ("0.2493,0.2386,0.2249,0.1975,0.1614,0.0891,-0.0407",\ +"0.2532,0.2424,0.2288,0.2014,0.1653,0.0930,-0.0369",\ +"0.2569,0.2461,0.2324,0.2051,0.1690,0.0967,-0.0332",\ +"0.2601,0.2493,0.2356,0.2083,0.1722,0.0999,-0.0300",\ +"0.2727,0.2619,0.2483,0.2209,0.1848,0.1125,-0.0174",\ +"0.2903,0.2796,0.2659,0.2385,0.2024,0.1301,0.0003",\ +"0.3178,0.3070,0.2934,0.2660,0.2299,0.1576,0.0278"); + } + } +} + pin(B_BIST_CLK) { + direction : input; + capacitance : 0.00389386; + max_transition : "0.38"; + clock : "true" ; + pin_func_type : active_rising ; + + timing () { + timing_type : "min_pulse_width"; + related_pin : "B_BIST_CLK"; + rise_constraint("CLKTRAN_constraint_template") { + index_1("0.004,0.38"); + values("0.12,0.12"); + } + } + + related_power_pin : VDD; + related_ground_pin : VSS; + + internal_power() { + when : "!B_BIST_MEN & !B_BIST_WEN & !B_BIST_REN"; + rise_power("scalar"){ + values (0); + } + fall_power("scalar"){ + values (0); + } + } + internal_power() { + when : "!B_BIST_MEN & B_BIST_WEN & !B_BIST_REN"; + rise_power("scalar"){ + values (0.6217); + } + fall_power("scalar"){ + values (0); + } + } + internal_power() { + when : "B_BIST_MEN & B_BIST_WEN & !B_BIST_REN"; + rise_power("scalar"){ + values (13.4151); + } + fall_power("scalar"){ + values (0); + } + } + internal_power() { + when : "B_BIST_MEN & B_BIST_WEN & B_BIST_REN"; + rise_power("scalar"){ + values (14.2183); + } + fall_power("scalar"){ + values (0); + } + } + internal_power() { + when : "B_BIST_MEN & !B_BIST_WEN & B_BIST_REN"; + rise_power("scalar"){ + values (10.4701); + } + fall_power("scalar"){ + values (0); + } + } + internal_power() { + when : "!B_BIST_MEN & !B_BIST_WEN & B_BIST_REN"; + rise_power("scalar"){ + values (0.3812); + } + fall_power("scalar"){ + values (0); + } + } + internal_power() { + when : "!B_BIST_MEN & B_BIST_WEN & B_BIST_REN"; + rise_power("scalar"){ + values (0.6439); + } + fall_power("scalar"){ + values (0); + } + } + internal_power() { + when : "B_BIST_MEN & !B_BIST_WEN & !B_BIST_REN"; + rise_power("scalar"){ + values (0); + } + fall_power("scalar"){ + values (0); + } + } + } + bus(B_BIST_DIN) { + bus_type : D_7_0; + direction : input ; + capacitance : 0.00417898 ; + memory_write() { + address : B_BIST_ADDR ; + clocked_on : B_BIST_CLK; + } + + max_transition : "0.38" ; + pin(B_BIST_DIN[7:0]) { + related_power_pin : VDD; + related_ground_pin : VSS; + internal_power() { + when : "B_BIST_MEN"; + rise_power("scalar"){ + values (0.0466); + } + fall_power("scalar"){ + values (0.0382); + } + } + internal_power() { + when : "!B_BIST_MEN"; + rise_power("scalar"){ + values (0.0552); + } + fall_power("scalar"){ + values (0.0440); + } + } + } + timing() { + timing_type : setup_rising; + related_pin : "B_BIST_CLK"; + when : "(B_BIST_WEN & B_BIST_MEN)"; + sdf_cond : "B_BIST_W_ACCESS"; + + rise_constraint("SIG2SRAM_constraint_template") { + index_1("0.0040,0.0176,0.0344,0.0656,0.1120,0.2016,0.3800"); + index_2("0.0040,0.0176,0.0344,0.0656,0.1120,0.2016,0.3800"); + values ("-0.1725,-0.1618,-0.1462,-0.1208,-0.0798,-0.0065,0.1282",\ +"-0.1764,-0.1657,-0.1501,-0.1247,-0.0837,-0.0104,0.1243",\ +"-0.1801,-0.1694,-0.1537,-0.1284,-0.0873,-0.0141,0.1207",\ +"-0.1833,-0.1726,-0.1570,-0.1315,-0.0905,-0.0173,0.1175",\ +"-0.1959,-0.1852,-0.1696,-0.1442,-0.1032,-0.0299,0.1048",\ +"-0.2135,-0.2028,-0.1872,-0.1618,-0.1208,-0.0475,0.0872",\ +"-0.2410,-0.2303,-0.2147,-0.1893,-0.1483,-0.0750,0.0597"); + } + + fall_constraint("SIG2SRAM_constraint_template") { + index_1("0.0040,0.0176,0.0344,0.0656,0.1120,0.2016,0.3800"); + index_2("0.0040,0.0176,0.0344,0.0656,0.1120,0.2016,0.3800"); + values ("-0.1491,-0.1374,-0.1247,-0.0974,-0.0602,0.0130,0.1409",\ +"-0.1530,-0.1413,-0.1286,-0.1012,-0.0641,0.0091,0.1370",\ +"-0.1567,-0.1450,-0.1323,-0.1049,-0.0678,0.0054,0.1334",\ +"-0.1599,-0.1482,-0.1355,-0.1081,-0.0710,0.0022,0.1302",\ +"-0.1725,-0.1608,-0.1481,-0.1207,-0.0836,-0.0104,0.1175",\ +"-0.1901,-0.1784,-0.1657,-0.1383,-0.1012,-0.0280,0.0999",\ +"-0.2176,-0.2059,-0.1932,-0.1658,-0.1287,-0.0555,0.0724"); + } + } + + timing() { + timing_type : hold_rising; + related_pin : "B_BIST_CLK"; + when : "(B_BIST_WEN & B_BIST_MEN)"; + sdf_cond : "B_BIST_W_ACCESS"; + + rise_constraint("SIG2SRAM_constraint_template") { + index_1("0.0040,0.0176,0.0344,0.0656,0.1120,0.2016,0.3800"); + index_2("0.0040,0.0176,0.0344,0.0656,0.1120,0.2016,0.3800"); + values ("0.2776,0.2679,0.2522,0.2259,0.1887,0.1145,-0.0202",\ +"0.2815,0.2717,0.2561,0.2297,0.1926,0.1184,-0.0163",\ +"0.2852,0.2754,0.2598,0.2334,0.1963,0.1221,-0.0127",\ +"0.2884,0.2786,0.2630,0.2366,0.1995,0.1253,-0.0095",\ +"0.3010,0.2912,0.2756,0.2492,0.2121,0.1379,0.0032",\ +"0.3186,0.3088,0.2932,0.2668,0.2297,0.1555,0.0208",\ +"0.3461,0.3363,0.3207,0.2944,0.2572,0.1830,0.0483"); + } + + fall_constraint("SIG2SRAM_constraint_template") { + index_1("0.0040,0.0176,0.0344,0.0656,0.1120,0.2016,0.3800"); + index_2("0.0040,0.0176,0.0344,0.0656,0.1120,0.2016,0.3800"); + values ("0.2493,0.2386,0.2249,0.1975,0.1614,0.0891,-0.0407",\ +"0.2532,0.2424,0.2288,0.2014,0.1653,0.0930,-0.0369",\ +"0.2569,0.2461,0.2324,0.2051,0.1690,0.0967,-0.0332",\ +"0.2601,0.2493,0.2356,0.2083,0.1722,0.0999,-0.0300",\ +"0.2727,0.2619,0.2483,0.2209,0.1848,0.1125,-0.0174",\ +"0.2903,0.2796,0.2659,0.2385,0.2024,0.1301,0.0003",\ +"0.3178,0.3070,0.2934,0.2660,0.2299,0.1576,0.0278"); + } + } + } + +bus(B_DOUT) { + + bus_type : D_7_0; + direction : output ; + capacitance : 0 ; + max_capacitance : 0.064 ; + memory_read() { + address : B_ADDR ; + } + pin(B_DOUT[7:0]) { + related_power_pin : VDD; + related_ground_pin : VSS; + internal_power() { + rise_power("scalar") { + values (0); + } + fall_power("scalar") { + values (0); + } + } + } + timing() { + related_pin : "B_CLK"; + timing_type : rising_edge ; + timing_sense : non_unate ; + + cell_rise(SIG2SRAM_delay_template) { + index_1("0.0040,0.0176,0.0344,0.0656,0.1120,0.2016,0.3800"); + index_2("0.0008,0.0014,0.0051,0.0100,0.0339,0.0640"); + values ("1.8251,1.8261,1.8309,1.8364,1.8573,1.8808",\ +"1.8310,1.8320,1.8369,1.8424,1.8633,1.8868",\ +"1.8338,1.8348,1.8396,1.8451,1.8660,1.8895",\ +"1.8380,1.8390,1.8438,1.8493,1.8702,1.8937",\ +"1.8496,1.8506,1.8554,1.8609,1.8819,1.9054",\ +"1.8687,1.8697,1.8746,1.8801,1.9010,1.9245",\ +"1.8951,1.8961,1.9009,1.9064,1.9274,1.9509"); + } + cell_fall(SIG2SRAM_delay_template) { + index_1("0.0040,0.0176,0.0344,0.0656,0.1120,0.2016,0.3800"); + index_2("0.0008,0.0014,0.0051,0.0100,0.0339,0.0640"); + values ("1.7908,1.7917,1.7957,1.8002,1.8173,1.8341",\ +"1.7968,1.7976,1.8016,1.8062,1.8233,1.8400",\ +"1.7995,1.8004,1.8044,1.8089,1.8260,1.8428",\ +"1.8037,1.8046,1.8086,1.8132,1.8302,1.8470",\ +"1.8153,1.8162,1.8202,1.8248,1.8419,1.8586",\ +"1.8344,1.8353,1.8393,1.8439,1.8610,1.8777",\ +"1.8608,1.8617,1.8657,1.8703,1.8874,1.9041"); + } + + rise_transition(SRAM_load_template) { + index_1("0.0008,0.0014,0.0051,0.0100,0.0339,0.0640"); + values ("0.0206,0.0210,0.0265,0.0323,0.0606,0.0955"); + } + fall_transition(SRAM_load_template) { + index_1("0.0008,0.0014,0.0051,0.0100,0.0339,0.0640"); + values ("0.0170,0.0177,0.0222,0.0270,0.0451,0.0644"); + } + } +} +cell_leakage_power : 112.9267; +} +} diff --git a/flow/platforms/ihp-sg13g2/lib/RM_IHPSG13_2P_256x8_c2_bm_bist_slow_1p08V_125C.lib b/flow/platforms/ihp-sg13g2/lib/RM_IHPSG13_2P_256x8_c2_bm_bist_slow_1p08V_125C.lib new file mode 100644 index 0000000000..df2fc1e2b8 --- /dev/null +++ b/flow/platforms/ihp-sg13g2/lib/RM_IHPSG13_2P_256x8_c2_bm_bist_slow_1p08V_125C.lib @@ -0,0 +1,2874 @@ +/* ------------------------------------------------------*/ +/**/ +/* Copyright 2025 IHP PDK Authors*/ +/**/ +/* Licensed under the Apache License, Version 2.0 (the "License");*/ +/* you may not use this file except in compliance with the License.*/ +/* You may obtain a copy of the License at*/ +/* */ +/* https://www.apache.org/licenses/LICENSE-2.0*/ +/* */ +/* Unless required by applicable law or agreed to in writing, software*/ +/* distributed under the License is distributed on an "AS IS" BASIS,*/ +/* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.*/ +/* See the License for the specific language governing permissions and*/ +/* limitations under the License.*/ +/* */ +/* Generated on Wed Aug 27 13:36:29 2025 */ +/* */ +/* ------------------------------------------------------ */ +library(RM_IHPSG13_2P_256x8_c2_bm_bist_slow_1p08V_125C) { + technology (cmos) ; + delay_model : table_lookup ; + define ("add_pg_pin_to_lib", "library", "boolean"); + add_pg_pin_to_lib : true; + voltage_map ( VDD, 1.08); + voltage_map ( VDDARRAY, 1.08); + voltage_map ( VSS, 0.000000 ); + + date : "Wed Aug 27 13:36:28 2025" ; + comment : "IHP Microelectronics GmbH, 2023" ; + revision : 1.0.0 ; + simulation : true ; + nom_process : 1 ; + nom_temperature : 125 ; + nom_voltage : 1.08 ; + + operating_conditions("slow_1p08V_125C"){ + process : 1 ; + temperature : 125 ; + voltage : 1.08 ; + tree_type : "balanced_tree" ; + } + + default_operating_conditions : slow_1p08V_125C ; + default_max_transition : 1.0 ; + default_fanout_load : 1.0 ; + default_inout_pin_cap : 0.0 ; + default_input_pin_cap : 0.0 ; + default_output_pin_cap : 0.0 ; + default_cell_leakage_power : 0.0 ; + default_leakage_power_density : 0.0 ; + + slew_lower_threshold_pct_rise : 30 ; + slew_upper_threshold_pct_rise : 70 ; + input_threshold_pct_fall : 50 ; + output_threshold_pct_fall : 50 ; + input_threshold_pct_rise : 50 ; + output_threshold_pct_rise : 50 ; + slew_lower_threshold_pct_fall : 30 ; + slew_upper_threshold_pct_fall : 70 ; + slew_derate_from_library : 0.5; + k_volt_cell_leakage_power : 0.0 ; + k_temp_cell_leakage_power : 0.0 ; + k_process_cell_leakage_power : 0.0 ; + k_volt_internal_power : 0.0 ; + k_temp_internal_power : 0.0 ; + k_process_internal_power : 0.0 ; + + capacitive_load_unit (1,pf) ; + voltage_unit : "1V" ; + current_unit : "1uA" ; + time_unit : "1ns" ; + leakage_power_unit : "1nW" ; + pulling_resistance_unit : "1kohm"; + /* + ------------------------------------------------------------------------------------------ + implicit units overview: + cell_area unit : "um" + internal_power unit : "1e-12 * J/toggle = 1 * uW/MHz" + (capacitive_load_unit * voltage_unit^2) per toggle event + ------------------------------------------------------------------------------------------ + */ + library_features(report_delay_calculation); + define_cell_area (pad_drivers,pad_driver_sites) ; + + lu_table_template(CLKTRAN_constraint_template) { + variable_1 : constrained_pin_transition; + index_1 ( "0.010, 0.050, 0.200, 0.400, 1.000" ); + } + lu_table_template(SRAM_load_template) { + variable_1 : total_output_net_capacitance; + index_1 ( "0.0008,0.0014,0.0051,0.0100,0.0339,0.0640" ); + } + lu_table_template(SIG2SRAM_constraint_template) { + variable_1 : related_pin_transition; + variable_2 : constrained_pin_transition; + index_1 ( "0.0080,0.0288,0.0616,0.1072,0.1920,0.3496,0.5952" ); + index_2 ( "0.0080,0.0288,0.0616,0.1072,0.1920,0.3496,0.5952" ); + } + + lu_table_template(SIG2SRAM_delay_template) { + variable_1 : input_net_transition; + variable_2 : total_output_net_capacitance; + index_1 ( "0.0080,0.0288,0.0616,0.1072,0.1920,0.3496,0.5952" ); + index_2 ( "0.0008,0.0014,0.0051,0.0100,0.0339,0.0640" ); + } + + type (D_7_0) { + base_type : array; + data_type : bit; + bit_width : 8; + bit_from : 7; + bit_to : 0; + downto : true; + } + + type (A_7_0) { + base_type : array; + data_type : bit; + bit_width : 8; + bit_from : 7; + bit_to : 0; + downto : true; + } + +cell(RM_IHPSG13_2P_256x8_c2_bm_bist) { +pg_pin (VDD) { + pg_type : primary_power; + voltage_name : VDD; +} +pg_pin (VDDARRAY) { + pg_type : primary_power; + voltage_name : VDDARRAY; +} +pg_pin (VSS) { + pg_type : primary_ground; + voltage_name : VSS; +} + +memory() { + type : ram; + address_width : 8; + word_width : 8; +} + +interface_timing : false; +bus_naming_style : "%s[%d]" ; +area : 38147.5147 ; + + pin(A_DLY) { + direction : input ; + capacitance : 0.00387999 ; + max_transition : "1" ; + related_power_pin : VDD; + related_ground_pin : VSS; + internal_power() { + rise_power("scalar") { + values (0); + } + fall_power("scalar") { + values (0); + } + } + } + +bus(A_ADDR) { + bus_type : A_7_0; + direction : input ; + capacitance : 0.0129586 ; + pin(A_ADDR[0]) { + capacitance : 0.0058687 ; + } + pin(A_ADDR[1]) { + capacitance : 0.00807137 ; + } + pin(A_ADDR[2]) { + capacitance : 0.0112051 ; + } + pin(A_ADDR[3]) { + capacitance : 0.00709524 ; + } + pin(A_ADDR[4]) { + capacitance : 0.00648778 ; + } + pin(A_ADDR[5]) { + capacitance : 0.011209 ; + } + pin(A_ADDR[6]) { + capacitance : 0.0140441 ; + } + max_transition : "0.5952" ; + pin(A_ADDR[7:0]) { + related_power_pin : VDD; + related_ground_pin : VSS; + internal_power() { + when : "A_MEN"; + rise_power("scalar"){ + values (0.0105); + } + fall_power("scalar"){ + values (0.0079); + } + } + internal_power() { + when : "!A_MEN"; + rise_power("scalar"){ + values (0.0144); + } + fall_power("scalar"){ + values (0.0033); + } + } + } + timing() { + timing_type : setup_rising; + related_pin : "A_CLK"; + when : "((A_WEN | A_REN)& A_MEN)" + sdf_cond : "A_RW_ACCESS" + + rise_constraint("SIG2SRAM_constraint_template") { + index_1("0.0080,0.0288,0.0616,0.1072,0.1920,0.3496,0.5952"); + index_2("0.0080,0.0288,0.0616,0.1072,0.1920,0.3496,0.5952"); + values ("-0.7371,-0.7176,-0.6863,-0.6434,-0.5652,-0.4168,-0.1980",\ +"-0.7566,-0.7371,-0.7059,-0.6629,-0.5848,-0.4363,-0.2137",\ +"-0.7879,-0.7645,-0.7332,-0.6902,-0.6121,-0.4637,-0.2449",\ +"-0.8309,-0.8074,-0.7762,-0.7332,-0.6551,-0.5066,-0.2879",\ +"-0.9051,-0.8895,-0.8543,-0.8113,-0.7332,-0.5887,-0.3660",\ +"-1.0418,-1.0262,-0.9949,-0.9480,-0.8699,-0.7293,-0.5027",\ +"-1.2684,-1.2449,-1.2176,-1.1707,-1.0965,-0.9480,-0.7293"); + } + + fall_constraint("SIG2SRAM_constraint_template") { + index_1("0.0080,0.0288,0.0616,0.1072,0.1920,0.3496,0.5952"); + index_2("0.0080,0.0288,0.0616,0.1072,0.1920,0.3496,0.5952"); + values ("-0.5926,-0.5730,-0.5418,-0.4988,-0.4246,-0.2879,-0.0730",\ +"-0.6121,-0.5926,-0.5613,-0.5223,-0.4441,-0.3074,-0.0887",\ +"-0.6395,-0.6199,-0.5926,-0.5496,-0.4715,-0.3348,-0.1160",\ +"-0.6863,-0.6668,-0.6355,-0.5965,-0.5184,-0.3777,-0.1590",\ +"-0.7605,-0.7410,-0.7137,-0.6746,-0.5926,-0.4559,-0.2410",\ +"-0.9012,-0.8816,-0.8504,-0.8113,-0.7332,-0.5926,-0.3895",\ +"-1.1238,-1.1043,-1.0769,-1.0379,-0.9559,-0.8191,-0.6004"); + } + } + + + timing() { + timing_type : hold_rising; + related_pin : "A_CLK"; + when : "((A_WEN | A_REN)& A_MEN)" + sdf_cond : "A_RW_ACCESS" + + rise_constraint("SIG2SRAM_constraint_template") { + index_1("0.0080,0.0288,0.0616,0.1072,0.1920,0.3496,0.5952"); + index_2("0.0080,0.0288,0.0616,0.1072,0.1920,0.3496,0.5952"); + values ("0.8488,0.8293,0.7980,0.7551,0.6730,0.5285,0.3059",\ +"0.8684,0.8488,0.8176,0.7746,0.6926,0.5480,0.3254",\ +"0.8996,0.8801,0.8449,0.8020,0.7238,0.5754,0.3527",\ +"0.9426,0.9191,0.8918,0.8488,0.7668,0.6223,0.3996",\ +"1.0168,1.0012,0.9699,0.9230,0.8449,0.7004,0.4777",\ +"1.1574,1.1379,1.1105,1.0598,0.9816,0.8371,0.6184",\ +"1.3801,1.3605,1.3254,1.2980,1.2043,1.0637,0.8371"); + } + + fall_constraint("SIG2SRAM_constraint_template") { + index_1("0.0080,0.0288,0.0616,0.1072,0.1920,0.3496,0.5952"); + index_2("0.0080,0.0288,0.0616,0.1072,0.1920,0.3496,0.5952"); + values ("0.6965,0.6770,0.6496,0.6066,0.5246,0.3918,0.1730",\ +"0.7160,0.6965,0.6652,0.6262,0.5441,0.4113,0.1965",\ +"0.7473,0.7277,0.6965,0.6535,0.5754,0.4426,0.2238",\ +"0.7863,0.7707,0.7395,0.7004,0.6223,0.4855,0.2629",\ +"0.8684,0.8449,0.8176,0.7785,0.7004,0.5637,0.3449",\ +"1.0051,0.9855,0.9855,0.9113,0.8332,0.7004,0.4895",\ +"1.2277,1.2082,1.1809,1.1379,1.0598,0.9230,0.7004"); + } + } +} +pin(A_WEN) { + direction : input ; + capacitance : 0.00313551 ; + max_transition : "0.5952" ; + related_power_pin : VDD; + related_ground_pin : VSS; + internal_power() { + when : "A_MEN"; + rise_power("scalar"){ + values (0.0036); + } + fall_power("scalar"){ + values (0.0008); + } + } + internal_power() { + when : "!A_MEN"; + rise_power("scalar"){ + values (0.0049); + } + fall_power("scalar"){ + values (0.0004); + } + } + timing() { + timing_type : setup_rising; + related_pin : "A_CLK"; + when : "A_MEN" + sdf_cond : "A_MEN" + + rise_constraint("SIG2SRAM_constraint_template") { + index_1("0.0080,0.0288,0.0616,0.1072,0.1920,0.3496,0.5952"); + index_2("0.0080,0.0288,0.0616,0.1072,0.1920,0.3496,0.5952"); + values ("0.3137,0.3332,0.3605,0.4035,0.4816,0.6223,0.8488",\ +"0.2980,0.3176,0.3410,0.3840,0.4660,0.6027,0.8293",\ +"0.2629,0.2824,0.3098,0.3527,0.4348,0.5754,0.7980",\ +"0.2199,0.2395,0.2668,0.3098,0.3918,0.5324,0.7590",\ +"0.1418,0.1613,0.1887,0.2316,0.3137,0.4348,0.6730",\ +"0.0012,0.0207,0.0520,0.0910,0.1730,0.3098,0.5285",\ +"-0.2215,-0.2020,-0.1746,-0.1277,-0.0496,0.0910,0.3098"); + } + + fall_constraint("SIG2SRAM_constraint_template") { + index_1("0.0080,0.0288,0.0616,0.1072,0.1920,0.3496,0.5952"); + index_2("0.0080,0.0288,0.0616,0.1072,0.1920,0.3496,0.5952"); + values ("0.4504,0.4699,0.4973,0.5324,0.6027,0.7355,0.9699",\ +"0.4309,0.4504,0.4777,0.5129,0.5910,0.7160,0.9504",\ +"0.3996,0.4191,0.4465,0.4816,0.5520,0.6848,0.9191",\ +"0.3605,0.3762,0.4035,0.4387,0.5168,0.6418,0.8723",\ +"0.2785,0.2980,0.3215,0.3605,0.4348,0.5637,0.7980",\ +"0.1379,0.1574,0.1809,0.2199,0.2980,0.4309,0.6457",\ +"-0.0809,-0.0613,-0.0340,0.0051,0.0832,0.2160,0.4191"); + } + } + + + timing() { + timing_type : hold_rising; + related_pin : "A_CLK"; + when : "A_MEN" + sdf_cond : "A_MEN" + + rise_constraint("SIG2SRAM_constraint_template") { + index_1("0.0080,0.0288,0.0616,0.1072,0.1920,0.3496,0.5952"); + index_2("0.0080,0.0288,0.0616,0.1072,0.1920,0.3496,0.5952"); + values ("0.3723,0.3527,0.3215,0.2785,0.1965,0.0559,-0.1668",\ +"0.3918,0.3723,0.3449,0.2980,0.2160,0.0754,-0.1473",\ +"0.4152,0.3996,0.3684,0.3254,0.2434,0.1066,-0.1199",\ +"0.4621,0.4465,0.4152,0.3723,0.2863,0.1496,-0.0730",\ +"0.5324,0.5207,0.4895,0.4465,0.3645,0.2199,0.0051",\ +"0.6770,0.6535,0.6301,0.5832,0.5090,0.3605,0.1418",\ +"0.9035,0.8879,0.8566,0.8137,0.7316,0.5871,0.3684"); + } + + fall_constraint("SIG2SRAM_constraint_template") { + index_1("0.0080,0.0288,0.0616,0.1072,0.1920,0.3496,0.5952"); + index_2("0.0080,0.0288,0.0616,0.1072,0.1920,0.3496,0.5952"); + values ("0.3762,0.3566,0.3293,0.2863,0.2043,0.0676,-0.1434",\ +"0.3957,0.3762,0.3488,0.3059,0.2238,0.0871,-0.1199",\ +"0.4230,0.4035,0.3723,0.3332,0.2512,0.1184,-0.0965",\ +"0.4660,0.4465,0.4191,0.3762,0.2941,0.1613,-0.0496",\ +"0.5324,0.5168,0.4973,0.4543,0.3723,0.2316,0.0285",\ +"0.6809,0.6613,0.6340,0.5910,0.5129,0.3645,0.1652",\ +"0.9113,0.8918,0.8605,0.8176,0.7395,0.5988,0.3879"); + } + } + } +pin(A_REN) { + direction : input ; + capacitance : 0.00381144 ; + max_transition : "0.5952" ; + related_power_pin : VDD; + related_ground_pin : VSS; + internal_power() { + when : "A_MEN"; + rise_power("scalar"){ + values (0.0040); + } + fall_power("scalar"){ + values (0.0016); + } + } + internal_power() { + when : "!A_MEN"; + rise_power("scalar"){ + values (0.0040); + } + fall_power("scalar"){ + values (0.0014); + } + } + timing() { + timing_type : setup_rising; + related_pin : "A_CLK"; + when : "A_MEN" + sdf_cond : "A_MEN" + + rise_constraint("SIG2SRAM_constraint_template") { + index_1("0.0080,0.0288,0.0616,0.1072,0.1920,0.3496,0.5952"); + index_2("0.0080,0.0288,0.0616,0.1072,0.1920,0.3496,0.5952"); + values ("-0.0770,-0.0574,-0.0262,0.0168,0.0949,0.2355,0.4582",\ +"-0.0965,-0.0770,-0.0457,-0.0027,0.0754,0.2160,0.4387",\ +"-0.1199,-0.1004,-0.0730,-0.0262,0.0520,0.1887,0.4113",\ +"-0.1590,-0.1434,-0.1160,-0.0730,0.0051,0.1457,0.3645",\ +"-0.2449,-0.2254,-0.1941,-0.1473,-0.0770,0.0676,0.2863",\ +"-0.3816,-0.3699,-0.3387,-0.2801,-0.2215,-0.0770,0.1457",\ +"-0.6121,-0.5926,-0.5613,-0.5145,-0.4363,-0.2996,-0.0730"); + } + + fall_constraint("SIG2SRAM_constraint_template") { + index_1("0.0080,0.0288,0.0616,0.1072,0.1920,0.3496,0.5952"); + index_2("0.0080,0.0288,0.0616,0.1072,0.1920,0.3496,0.5952"); + values ("0.1262,0.1457,0.1691,0.2121,0.2824,0.4191,0.6457",\ +"0.1105,0.1262,0.1496,0.1887,0.2629,0.3996,0.6262",\ +"0.0793,0.0949,0.1223,0.1652,0.2395,0.3684,0.5949",\ +"0.0363,0.0559,0.0793,0.1223,0.2004,0.3410,0.5520",\ +"-0.0457,-0.0262,0.0012,0.0441,0.1301,0.2629,0.4738",\ +"-0.1902,-0.1746,-0.1434,-0.1043,-0.0184,0.1223,0.3332",\ +"-0.4129,-0.3934,-0.3660,-0.3230,-0.2449,-0.1043,0.1105"); + } + } + + + timing() { + timing_type : hold_rising; + related_pin : "A_CLK"; + when : "A_MEN" + sdf_cond : "A_MEN" + + rise_constraint("SIG2SRAM_constraint_template") { + index_1("0.0080,0.0288,0.0616,0.1072,0.1920,0.3496,0.5952"); + index_2("0.0080,0.0288,0.0616,0.1072,0.1920,0.3496,0.5952"); + values ("0.4113,0.3918,0.3645,0.3176,0.2395,0.0988,-0.1238",\ +"0.4309,0.4113,0.3840,0.3371,0.2590,0.1184,-0.1043",\ +"0.4582,0.4387,0.4113,0.3645,0.2824,0.1457,-0.0770",\ +"0.5051,0.4816,0.4543,0.4074,0.3293,0.1887,-0.0340",\ +"0.5715,0.5598,0.5324,0.4895,0.4035,0.2512,0.0441",\ +"0.7043,0.7004,0.6730,0.6262,0.5402,0.3957,0.1809",\ +"0.9387,0.9270,0.8957,0.8527,0.7746,0.6262,0.4074"); + } + + fall_constraint("SIG2SRAM_constraint_template") { + index_1("0.0080,0.0288,0.0616,0.1072,0.1920,0.3496,0.5952"); + index_2("0.0080,0.0288,0.0616,0.1072,0.1920,0.3496,0.5952"); + values ("0.4152,0.3918,0.3645,0.3215,0.2395,0.1027,-0.1082",\ +"0.4309,0.4113,0.3801,0.3410,0.2590,0.1223,-0.0926",\ +"0.4582,0.4387,0.4074,0.3684,0.2863,0.1496,-0.0613",\ +"0.5012,0.4816,0.4504,0.4074,0.3293,0.1887,-0.0145",\ +"0.5715,0.5559,0.5285,0.4816,0.3996,0.2512,0.0598",\ +"0.7160,0.7004,0.6691,0.6262,0.5520,0.4035,0.2004",\ +"0.9387,0.9191,0.8957,0.8488,0.7707,0.6262,0.4113"); + } + } + } +pin(A_MEN) { + direction : input ; + capacitance : 0.00300347 ; + max_transition : "0.5952" ; + related_power_pin : VDD; + related_ground_pin : VSS; + internal_power() { + rise_power("scalar"){ + values (0.0091); + } + fall_power("scalar"){ + values (0.0001); + } + } + timing() { + timing_type : setup_rising; + related_pin : "A_CLK"; + + rise_constraint("SIG2SRAM_constraint_template") { + index_1("0.0080,0.0288,0.0616,0.1072,0.1920,0.3496,0.5952"); + index_2("0.0080,0.0288,0.0616,0.1072,0.1920,0.3496,0.5952"); + values ("0.3215,0.3449,0.3684,0.4113,0.4895,0.6301,0.8527",\ +"0.3059,0.3254,0.3527,0.3957,0.4738,0.6145,0.8371",\ +"0.2746,0.2941,0.3215,0.3645,0.4426,0.5871,0.8059",\ +"0.2316,0.2512,0.2785,0.3215,0.3996,0.5402,0.7629",\ +"0.1496,0.1730,0.1965,0.2395,0.3215,0.4660,0.6848",\ +"0.0090,0.0285,0.0598,0.1027,0.1809,0.3176,0.5402",\ +"-0.2098,-0.1902,-0.1668,-0.1199,-0.0418,0.0988,0.3137"); + } + + fall_constraint("SIG2SRAM_constraint_template") { + index_1("0.0080,0.0288,0.0616,0.1072,0.1920,0.3496,0.5952"); + index_2("0.0080,0.0288,0.0616,0.1072,0.1920,0.3496,0.5952"); + values ("0.4582,0.4738,0.5012,0.5363,0.6145,0.7395,0.9738",\ +"0.4387,0.4543,0.4816,0.5207,0.5910,0.7199,0.9582",\ +"0.4035,0.4230,0.4504,0.4855,0.5637,0.6887,0.9230",\ +"0.3645,0.3840,0.4074,0.4465,0.5285,0.6496,0.8840",\ +"0.2824,0.3020,0.3254,0.3645,0.4465,0.5715,0.7980",\ +"0.1418,0.1613,0.1887,0.2238,0.3020,0.4309,0.6496",\ +"-0.0770,-0.0574,-0.0301,0.0090,0.0910,0.2238,0.4191"); + } + } + + + timing() { + timing_type : hold_rising; + related_pin : "A_CLK"; + + rise_constraint("SIG2SRAM_constraint_template") { + index_1("0.0080,0.0288,0.0616,0.1072,0.1920,0.3496,0.5952"); + index_2("0.0080,0.0288,0.0616,0.1072,0.1920,0.3496,0.5952"); + values ("0.3762,0.3605,0.3293,0.2863,0.2043,0.0637,-0.1629",\ +"0.3996,0.3801,0.3488,0.3020,0.2238,0.0832,-0.1395",\ +"0.4230,0.4074,0.3723,0.3293,0.2473,0.1105,-0.1121",\ +"0.4621,0.4465,0.4152,0.3762,0.2941,0.1535,-0.0691",\ +"0.5441,0.5285,0.4973,0.4465,0.3684,0.2316,0.0090",\ +"0.6848,0.6652,0.6301,0.5910,0.5129,0.3605,0.1496",\ +"0.9074,0.8918,0.8566,0.8215,0.7395,0.5910,0.3723"); + } + + fall_constraint("SIG2SRAM_constraint_template") { + index_1("0.0080,0.0288,0.0616,0.1072,0.1920,0.3496,0.5952"); + index_2("0.0080,0.0288,0.0616,0.1072,0.1920,0.3496,0.5952"); + values ("0.3762,0.3605,0.3332,0.2863,0.2043,0.0715,-0.1395",\ +"0.3996,0.3762,0.3488,0.3059,0.2238,0.0910,-0.1199",\ +"0.4270,0.4035,0.3762,0.3332,0.2512,0.1184,-0.0965",\ +"0.4699,0.4504,0.4191,0.3762,0.2941,0.1613,-0.0496",\ +"0.5441,0.5285,0.4973,0.4543,0.3762,0.2355,0.0324",\ +"0.6770,0.6613,0.6340,0.5949,0.5207,0.3762,0.1652",\ +"0.9074,0.8918,0.8605,0.8176,0.7395,0.6027,0.3918"); + } + } + } +bus(A_BM) { + bus_type : D_7_0; + direction : input ; + capacitance : 0.00359979 ; + max_transition : "0.5952" ; + pin(A_BM[7:0]) { + related_power_pin : VDD; + related_ground_pin : VSS; + internal_power() { + when : "A_MEN"; + rise_power("scalar"){ + values (0.0236); + } + fall_power("scalar"){ + values (0.0076); + } + } + internal_power() { + when : "!A_MEN"; + rise_power("scalar"){ + values (0.0229); + } + fall_power("scalar"){ + values (0.0073); + } + } + } + timing() { + timing_type : setup_rising; + related_pin : "A_CLK"; + when : "(A_WEN & A_MEN)" + sdf_cond : "A_RW_ACCESS" + + rise_constraint("SIG2SRAM_constraint_template") { + index_1("0.0080,0.0288,0.0616,0.1072,0.1920,0.3496,0.5952"); + index_2("0.0080,0.0288,0.0616,0.1072,0.1920,0.3496,0.5952"); + values ("-0.5886,-0.5691,-0.5437,-0.5007,-0.4197,-0.2742,-0.0515",\ +"-0.5965,-0.5770,-0.5516,-0.5086,-0.4276,-0.2821,-0.0594",\ +"-0.6057,-0.5861,-0.5607,-0.5178,-0.4367,-0.2912,-0.0686",\ +"-0.6206,-0.6011,-0.5757,-0.5327,-0.4517,-0.3062,-0.0835",\ +"-0.6430,-0.6235,-0.5981,-0.5551,-0.4741,-0.3286,-0.1059",\ +"-0.6866,-0.6671,-0.6417,-0.5987,-0.5177,-0.3722,-0.1495",\ +"-0.7558,-0.7363,-0.7109,-0.6679,-0.5869,-0.4413,-0.2187"); + } + + fall_constraint("SIG2SRAM_constraint_template") { + index_1("0.0080,0.0288,0.0616,0.1072,0.1920,0.3496,0.5952"); + index_2("0.0080,0.0288,0.0616,0.1072,0.1920,0.3496,0.5952"); + values ("-0.5261,-0.5085,-0.4812,-0.4421,-0.3591,-0.2234,-0.0115",\ +"-0.5340,-0.5164,-0.4891,-0.4500,-0.3670,-0.2313,-0.0194",\ +"-0.5432,-0.5256,-0.4982,-0.4592,-0.3762,-0.2404,-0.0285",\ +"-0.5581,-0.5406,-0.5132,-0.4742,-0.3911,-0.2554,-0.0435",\ +"-0.5805,-0.5629,-0.5356,-0.4965,-0.4135,-0.2778,-0.0659",\ +"-0.6241,-0.6065,-0.5792,-0.5401,-0.4571,-0.3214,-0.1095",\ +"-0.6933,-0.6757,-0.6484,-0.6093,-0.5263,-0.3906,-0.1787"); + } + } + + + timing() { + timing_type : hold_rising; + related_pin : "A_CLK"; + when : "(A_WEN & A_MEN)" + sdf_cond : "A_RW_ACCESS" + + rise_constraint("SIG2SRAM_constraint_template") { + index_1("0.0080,0.0288,0.0616,0.1072,0.1920,0.3496,0.5952"); + index_2("0.0080,0.0288,0.0616,0.1072,0.1920,0.3496,0.5952"); + values ("0.7036,0.6821,0.6577,0.6148,0.5347,0.3882,0.1655",\ +"0.7115,0.6901,0.6656,0.6227,0.5426,0.3961,0.1735",\ +"0.7207,0.6992,0.6748,0.6318,0.5517,0.4053,0.1826",\ +"0.7357,0.7142,0.6898,0.6468,0.5667,0.4202,0.1976",\ +"0.7581,0.7366,0.7121,0.6692,0.5891,0.4426,0.2200",\ +"0.8016,0.7802,0.7558,0.7128,0.6327,0.4862,0.2636",\ +"0.8708,0.8493,0.8249,0.7820,0.7019,0.5554,0.3327"); + } + + fall_constraint("SIG2SRAM_constraint_template") { + index_1("0.0080,0.0288,0.0616,0.1072,0.1920,0.3496,0.5952"); + index_2("0.0080,0.0288,0.0616,0.1072,0.1920,0.3496,0.5952"); + values ("0.6294,0.6118,0.5845,0.5454,0.4624,0.3257,0.1148",\ +"0.6373,0.6197,0.5924,0.5533,0.4703,0.3336,0.1227",\ +"0.6465,0.6289,0.6015,0.5625,0.4795,0.3428,0.1318",\ +"0.6614,0.6439,0.6165,0.5775,0.4944,0.3577,0.1468",\ +"0.6838,0.6663,0.6389,0.5998,0.5168,0.3801,0.1692",\ +"0.7274,0.7098,0.6825,0.6434,0.5604,0.4237,0.2128",\ +"0.7966,0.7790,0.7517,0.7126,0.6296,0.4929,0.2820"); + } + } +} + pin(A_CLK) { + direction : input; + capacitance : 0.00378957; + max_transition : "0.5952"; + clock : "true" ; + pin_func_type : active_rising ; + + timing () { + timing_type : "min_pulse_width"; + related_pin : "A_CLK"; + rise_constraint("CLKTRAN_constraint_template") { + index_1("0.008,0.5952"); + values("0.4,0.4"); + } + } + + related_power_pin : VDD; + related_ground_pin : VSS; + + internal_power() { + when : "!A_MEN & !A_WEN & !A_REN"; + rise_power("scalar"){ + values (0); + } + fall_power("scalar"){ + values (0); + } + } + internal_power() { + when : "!A_MEN & A_WEN & !A_REN"; + rise_power("scalar"){ + values (0.4257); + } + fall_power("scalar"){ + values (0); + } + } + internal_power() { + when : "A_MEN & A_WEN & !A_REN"; + rise_power("scalar"){ + values (9.0428); + } + fall_power("scalar"){ + values (0); + } + } + internal_power() { + when : "A_MEN & A_WEN & A_REN"; + rise_power("scalar"){ + values (9.4016); + } + fall_power("scalar"){ + values (0); + } + } + internal_power() { + when : "A_MEN & !A_WEN & A_REN"; + rise_power("scalar"){ + values (6.8079); + } + fall_power("scalar"){ + values (0); + } + } + internal_power() { + when : "!A_MEN & !A_WEN & A_REN"; + rise_power("scalar"){ + values (0.2646); + } + fall_power("scalar"){ + values (0); + } + } + internal_power() { + when : "!A_MEN & A_WEN & A_REN"; + rise_power("scalar"){ + values (0.4709); + } + fall_power("scalar"){ + values (0); + } + } + internal_power() { + when : "A_MEN & !A_WEN & !A_REN"; + rise_power("scalar"){ + values (0); + } + fall_power("scalar"){ + values (0); + } + } + } + bus(A_DIN) { + bus_type : D_7_0; + direction : input ; + capacitance : 0.00502163 ; + memory_write() { + address : A_ADDR ; + clocked_on : A_CLK; + } + + max_transition : "0.5952" ; + pin(A_DIN[7:0]) { + related_power_pin : VDD; + related_ground_pin : VSS; + internal_power() { + when : "A_MEN"; + rise_power("scalar"){ + values (0.0236); + } + fall_power("scalar"){ + values (0.0076); + } + } + internal_power() { + when : "!A_MEN"; + rise_power("scalar"){ + values (0.0229); + } + fall_power("scalar"){ + values (0.0073); + } + } + } + timing() { + timing_type : setup_rising; + related_pin : "A_CLK"; + when : "(A_WEN & A_MEN)"; + sdf_cond : "A_W_ACCESS"; + + rise_constraint("SIG2SRAM_constraint_template") { + index_1("0.0080,0.0288,0.0616,0.1072,0.1920,0.3496,0.5952"); + index_2("0.0080,0.0288,0.0616,0.1072,0.1920,0.3496,0.5952"); + values ("-0.5886,-0.5691,-0.5437,-0.5007,-0.4197,-0.2742,-0.0515",\ +"-0.5965,-0.5770,-0.5516,-0.5086,-0.4276,-0.2821,-0.0594",\ +"-0.6057,-0.5861,-0.5607,-0.5178,-0.4367,-0.2912,-0.0686",\ +"-0.6206,-0.6011,-0.5757,-0.5327,-0.4517,-0.3062,-0.0835",\ +"-0.6430,-0.6235,-0.5981,-0.5551,-0.4741,-0.3286,-0.1059",\ +"-0.6866,-0.6671,-0.6417,-0.5987,-0.5177,-0.3722,-0.1495",\ +"-0.7558,-0.7363,-0.7109,-0.6679,-0.5869,-0.4413,-0.2187"); + } + + fall_constraint("SIG2SRAM_constraint_template") { + index_1("0.0080,0.0288,0.0616,0.1072,0.1920,0.3496,0.5952"); + index_2("0.0080,0.0288,0.0616,0.1072,0.1920,0.3496,0.5952"); + values ("-0.5261,-0.5085,-0.4812,-0.4421,-0.3591,-0.2234,-0.0115",\ +"-0.5340,-0.5164,-0.4891,-0.4500,-0.3670,-0.2313,-0.0194",\ +"-0.5432,-0.5256,-0.4982,-0.4592,-0.3762,-0.2404,-0.0285",\ +"-0.5581,-0.5406,-0.5132,-0.4742,-0.3911,-0.2554,-0.0435",\ +"-0.5805,-0.5629,-0.5356,-0.4965,-0.4135,-0.2778,-0.0659",\ +"-0.6241,-0.6065,-0.5792,-0.5401,-0.4571,-0.3214,-0.1095",\ +"-0.6933,-0.6757,-0.6484,-0.6093,-0.5263,-0.3906,-0.1787"); + } + } + + timing() { + timing_type : hold_rising; + related_pin : "A_CLK"; + when : "(A_WEN & A_MEN)"; + sdf_cond : "A_W_ACCESS"; + + rise_constraint("SIG2SRAM_constraint_template") { + index_1("0.0080,0.0288,0.0616,0.1072,0.1920,0.3496,0.5952"); + index_2("0.0080,0.0288,0.0616,0.1072,0.1920,0.3496,0.5952"); + values ("0.7036,0.6821,0.6577,0.6148,0.5347,0.3882,0.1655",\ +"0.7115,0.6901,0.6656,0.6227,0.5426,0.3961,0.1735",\ +"0.7207,0.6992,0.6748,0.6318,0.5517,0.4053,0.1826",\ +"0.7357,0.7142,0.6898,0.6468,0.5667,0.4202,0.1976",\ +"0.7581,0.7366,0.7121,0.6692,0.5891,0.4426,0.2200",\ +"0.8016,0.7802,0.7558,0.7128,0.6327,0.4862,0.2636",\ +"0.8708,0.8493,0.8249,0.7820,0.7019,0.5554,0.3327"); + } + + fall_constraint("SIG2SRAM_constraint_template") { + index_1("0.0080,0.0288,0.0616,0.1072,0.1920,0.3496,0.5952"); + index_2("0.0080,0.0288,0.0616,0.1072,0.1920,0.3496,0.5952"); + values ("0.6294,0.6118,0.5845,0.5454,0.4624,0.3257,0.1148",\ +"0.6373,0.6197,0.5924,0.5533,0.4703,0.3336,0.1227",\ +"0.6465,0.6289,0.6015,0.5625,0.4795,0.3428,0.1318",\ +"0.6614,0.6439,0.6165,0.5775,0.4944,0.3577,0.1468",\ +"0.6838,0.6663,0.6389,0.5998,0.5168,0.3801,0.1692",\ +"0.7274,0.7098,0.6825,0.6434,0.5604,0.4237,0.2128",\ +"0.7966,0.7790,0.7517,0.7126,0.6296,0.4929,0.2820"); + } + } + } + + pin(A_BIST_EN) { + direction : input ; + capacitance : 0.00387999 ; + max_transition : "1" ; + related_power_pin : VDD; + related_ground_pin : VSS; + internal_power() { + rise_power("scalar") { + values (0); + } + fall_power("scalar") { + values (0); + } + } + } + +bus(A_BIST_ADDR) { + bus_type : A_7_0; + direction : input ; + capacitance : 0.0129586 ; + pin(A_BIST_ADDR[0]) { + capacitance : 0.0058687 ; + } + pin(A_BIST_ADDR[1]) { + capacitance : 0.00807137 ; + } + pin(A_BIST_ADDR[2]) { + capacitance : 0.0112051 ; + } + pin(A_BIST_ADDR[3]) { + capacitance : 0.00709524 ; + } + pin(A_BIST_ADDR[4]) { + capacitance : 0.00648778 ; + } + pin(A_BIST_ADDR[5]) { + capacitance : 0.011209 ; + } + pin(A_BIST_ADDR[6]) { + capacitance : 0.0140441 ; + } + max_transition : "0.5952" ; + pin(A_BIST_ADDR[7:0]) { + related_power_pin : VDD; + related_ground_pin : VSS; + internal_power() { + when : "A_BIST_MEN"; + rise_power("scalar"){ + values (0.0105); + } + fall_power("scalar"){ + values (0.0079); + } + } + internal_power() { + when : "!A_BIST_MEN"; + rise_power("scalar"){ + values (0.0144); + } + fall_power("scalar"){ + values (0.0033); + } + } + } + timing() { + timing_type : setup_rising; + related_pin : "A_BIST_CLK"; + when : "((A_BIST_WEN | A_BIST_REN)& A_BIST_MEN)" + sdf_cond : "A_BIST_RW_ACCESS" + + rise_constraint("SIG2SRAM_constraint_template") { + index_1("0.0080,0.0288,0.0616,0.1072,0.1920,0.3496,0.5952"); + index_2("0.0080,0.0288,0.0616,0.1072,0.1920,0.3496,0.5952"); + values ("-0.7371,-0.7176,-0.6863,-0.6434,-0.5652,-0.4168,-0.1980",\ +"-0.7566,-0.7371,-0.7059,-0.6629,-0.5848,-0.4363,-0.2137",\ +"-0.7879,-0.7645,-0.7332,-0.6902,-0.6121,-0.4637,-0.2449",\ +"-0.8309,-0.8074,-0.7762,-0.7332,-0.6551,-0.5066,-0.2879",\ +"-0.9051,-0.8895,-0.8543,-0.8113,-0.7332,-0.5887,-0.3660",\ +"-1.0418,-1.0262,-0.9949,-0.9480,-0.8699,-0.7293,-0.5027",\ +"-1.2684,-1.2449,-1.2176,-1.1707,-1.0965,-0.9480,-0.7293"); + } + + fall_constraint("SIG2SRAM_constraint_template") { + index_1("0.0080,0.0288,0.0616,0.1072,0.1920,0.3496,0.5952"); + index_2("0.0080,0.0288,0.0616,0.1072,0.1920,0.3496,0.5952"); + values ("-0.5926,-0.5730,-0.5418,-0.4988,-0.4246,-0.2879,-0.0730",\ +"-0.6121,-0.5926,-0.5613,-0.5223,-0.4441,-0.3074,-0.0887",\ +"-0.6395,-0.6199,-0.5926,-0.5496,-0.4715,-0.3348,-0.1160",\ +"-0.6863,-0.6668,-0.6355,-0.5965,-0.5184,-0.3777,-0.1590",\ +"-0.7605,-0.7410,-0.7137,-0.6746,-0.5926,-0.4559,-0.2410",\ +"-0.9012,-0.8816,-0.8504,-0.8113,-0.7332,-0.5926,-0.3895",\ +"-1.1238,-1.1043,-1.0769,-1.0379,-0.9559,-0.8191,-0.6004"); + } + } + + + timing() { + timing_type : hold_rising; + related_pin : "A_BIST_CLK"; + when : "((A_BIST_WEN | A_BIST_REN)& A_BIST_MEN)" + sdf_cond : "A_BIST_RW_ACCESS" + + rise_constraint("SIG2SRAM_constraint_template") { + index_1("0.0080,0.0288,0.0616,0.1072,0.1920,0.3496,0.5952"); + index_2("0.0080,0.0288,0.0616,0.1072,0.1920,0.3496,0.5952"); + values ("0.8488,0.8293,0.7980,0.7551,0.6730,0.5285,0.3059",\ +"0.8684,0.8488,0.8176,0.7746,0.6926,0.5480,0.3254",\ +"0.8996,0.8801,0.8449,0.8020,0.7238,0.5754,0.3527",\ +"0.9426,0.9191,0.8918,0.8488,0.7668,0.6223,0.3996",\ +"1.0168,1.0012,0.9699,0.9230,0.8449,0.7004,0.4777",\ +"1.1574,1.1379,1.1105,1.0598,0.9816,0.8371,0.6184",\ +"1.3801,1.3605,1.3254,1.2980,1.2043,1.0637,0.8371"); + } + + fall_constraint("SIG2SRAM_constraint_template") { + index_1("0.0080,0.0288,0.0616,0.1072,0.1920,0.3496,0.5952"); + index_2("0.0080,0.0288,0.0616,0.1072,0.1920,0.3496,0.5952"); + values ("0.6965,0.6770,0.6496,0.6066,0.5246,0.3918,0.1730",\ +"0.7160,0.6965,0.6652,0.6262,0.5441,0.4113,0.1965",\ +"0.7473,0.7277,0.6965,0.6535,0.5754,0.4426,0.2238",\ +"0.7863,0.7707,0.7395,0.7004,0.6223,0.4855,0.2629",\ +"0.8684,0.8449,0.8176,0.7785,0.7004,0.5637,0.3449",\ +"1.0051,0.9855,0.9855,0.9113,0.8332,0.7004,0.4895",\ +"1.2277,1.2082,1.1809,1.1379,1.0598,0.9230,0.7004"); + } + } +} +pin(A_BIST_WEN) { + direction : input ; + capacitance : 0.00313551 ; + max_transition : "0.5952" ; + related_power_pin : VDD; + related_ground_pin : VSS; + internal_power() { + when : "A_BIST_MEN"; + rise_power("scalar"){ + values (0.0036); + } + fall_power("scalar"){ + values (0.0008); + } + } + internal_power() { + when : "!A_BIST_MEN"; + rise_power("scalar"){ + values (0.0049); + } + fall_power("scalar"){ + values (0.0004); + } + } + timing() { + timing_type : setup_rising; + related_pin : "A_BIST_CLK"; + when : "A_BIST_MEN" + sdf_cond : "A_BIST_MEN" + + rise_constraint("SIG2SRAM_constraint_template") { + index_1("0.0080,0.0288,0.0616,0.1072,0.1920,0.3496,0.5952"); + index_2("0.0080,0.0288,0.0616,0.1072,0.1920,0.3496,0.5952"); + values ("0.3137,0.3332,0.3605,0.4035,0.4816,0.6223,0.8488",\ +"0.2980,0.3176,0.3410,0.3840,0.4660,0.6027,0.8293",\ +"0.2629,0.2824,0.3098,0.3527,0.4348,0.5754,0.7980",\ +"0.2199,0.2395,0.2668,0.3098,0.3918,0.5324,0.7590",\ +"0.1418,0.1613,0.1887,0.2316,0.3137,0.4348,0.6730",\ +"0.0012,0.0207,0.0520,0.0910,0.1730,0.3098,0.5285",\ +"-0.2215,-0.2020,-0.1746,-0.1277,-0.0496,0.0910,0.3098"); + } + + fall_constraint("SIG2SRAM_constraint_template") { + index_1("0.0080,0.0288,0.0616,0.1072,0.1920,0.3496,0.5952"); + index_2("0.0080,0.0288,0.0616,0.1072,0.1920,0.3496,0.5952"); + values ("0.4504,0.4699,0.4973,0.5324,0.6027,0.7355,0.9699",\ +"0.4309,0.4504,0.4777,0.5129,0.5910,0.7160,0.9504",\ +"0.3996,0.4191,0.4465,0.4816,0.5520,0.6848,0.9191",\ +"0.3605,0.3762,0.4035,0.4387,0.5168,0.6418,0.8723",\ +"0.2785,0.2980,0.3215,0.3605,0.4348,0.5637,0.7980",\ +"0.1379,0.1574,0.1809,0.2199,0.2980,0.4309,0.6457",\ +"-0.0809,-0.0613,-0.0340,0.0051,0.0832,0.2160,0.4191"); + } + } + + + timing() { + timing_type : hold_rising; + related_pin : "A_BIST_CLK"; + when : "A_BIST_MEN" + sdf_cond : "A_BIST_MEN" + + rise_constraint("SIG2SRAM_constraint_template") { + index_1("0.0080,0.0288,0.0616,0.1072,0.1920,0.3496,0.5952"); + index_2("0.0080,0.0288,0.0616,0.1072,0.1920,0.3496,0.5952"); + values ("0.3723,0.3527,0.3215,0.2785,0.1965,0.0559,-0.1668",\ +"0.3918,0.3723,0.3449,0.2980,0.2160,0.0754,-0.1473",\ +"0.4152,0.3996,0.3684,0.3254,0.2434,0.1066,-0.1199",\ +"0.4621,0.4465,0.4152,0.3723,0.2863,0.1496,-0.0730",\ +"0.5324,0.5207,0.4895,0.4465,0.3645,0.2199,0.0051",\ +"0.6770,0.6535,0.6301,0.5832,0.5090,0.3605,0.1418",\ +"0.9035,0.8879,0.8566,0.8137,0.7316,0.5871,0.3684"); + } + + fall_constraint("SIG2SRAM_constraint_template") { + index_1("0.0080,0.0288,0.0616,0.1072,0.1920,0.3496,0.5952"); + index_2("0.0080,0.0288,0.0616,0.1072,0.1920,0.3496,0.5952"); + values ("0.3762,0.3566,0.3293,0.2863,0.2043,0.0676,-0.1434",\ +"0.3957,0.3762,0.3488,0.3059,0.2238,0.0871,-0.1199",\ +"0.4230,0.4035,0.3723,0.3332,0.2512,0.1184,-0.0965",\ +"0.4660,0.4465,0.4191,0.3762,0.2941,0.1613,-0.0496",\ +"0.5324,0.5168,0.4973,0.4543,0.3723,0.2316,0.0285",\ +"0.6809,0.6613,0.6340,0.5910,0.5129,0.3645,0.1652",\ +"0.9113,0.8918,0.8605,0.8176,0.7395,0.5988,0.3879"); + } + } + } +pin(A_BIST_REN) { + direction : input ; + capacitance : 0.00381144 ; + max_transition : "0.5952" ; + related_power_pin : VDD; + related_ground_pin : VSS; + internal_power() { + when : "A_BIST_MEN"; + rise_power("scalar"){ + values (0.0040); + } + fall_power("scalar"){ + values (0.0016); + } + } + internal_power() { + when : "!A_BIST_MEN"; + rise_power("scalar"){ + values (0.0040); + } + fall_power("scalar"){ + values (0.0014); + } + } + timing() { + timing_type : setup_rising; + related_pin : "A_BIST_CLK"; + when : "A_BIST_MEN" + sdf_cond : "A_BIST_MEN" + + rise_constraint("SIG2SRAM_constraint_template") { + index_1("0.0080,0.0288,0.0616,0.1072,0.1920,0.3496,0.5952"); + index_2("0.0080,0.0288,0.0616,0.1072,0.1920,0.3496,0.5952"); + values ("-0.0770,-0.0574,-0.0262,0.0168,0.0949,0.2355,0.4582",\ +"-0.0965,-0.0770,-0.0457,-0.0027,0.0754,0.2160,0.4387",\ +"-0.1199,-0.1004,-0.0730,-0.0262,0.0520,0.1887,0.4113",\ +"-0.1590,-0.1434,-0.1160,-0.0730,0.0051,0.1457,0.3645",\ +"-0.2449,-0.2254,-0.1941,-0.1473,-0.0770,0.0676,0.2863",\ +"-0.3816,-0.3699,-0.3387,-0.2801,-0.2215,-0.0770,0.1457",\ +"-0.6121,-0.5926,-0.5613,-0.5145,-0.4363,-0.2996,-0.0730"); + } + + fall_constraint("SIG2SRAM_constraint_template") { + index_1("0.0080,0.0288,0.0616,0.1072,0.1920,0.3496,0.5952"); + index_2("0.0080,0.0288,0.0616,0.1072,0.1920,0.3496,0.5952"); + values ("0.1262,0.1457,0.1691,0.2121,0.2824,0.4191,0.6457",\ +"0.1105,0.1262,0.1496,0.1887,0.2629,0.3996,0.6262",\ +"0.0793,0.0949,0.1223,0.1652,0.2395,0.3684,0.5949",\ +"0.0363,0.0559,0.0793,0.1223,0.2004,0.3410,0.5520",\ +"-0.0457,-0.0262,0.0012,0.0441,0.1301,0.2629,0.4738",\ +"-0.1902,-0.1746,-0.1434,-0.1043,-0.0184,0.1223,0.3332",\ +"-0.4129,-0.3934,-0.3660,-0.3230,-0.2449,-0.1043,0.1105"); + } + } + + + timing() { + timing_type : hold_rising; + related_pin : "A_BIST_CLK"; + when : "A_BIST_MEN" + sdf_cond : "A_BIST_MEN" + + rise_constraint("SIG2SRAM_constraint_template") { + index_1("0.0080,0.0288,0.0616,0.1072,0.1920,0.3496,0.5952"); + index_2("0.0080,0.0288,0.0616,0.1072,0.1920,0.3496,0.5952"); + values ("0.4113,0.3918,0.3645,0.3176,0.2395,0.0988,-0.1238",\ +"0.4309,0.4113,0.3840,0.3371,0.2590,0.1184,-0.1043",\ +"0.4582,0.4387,0.4113,0.3645,0.2824,0.1457,-0.0770",\ +"0.5051,0.4816,0.4543,0.4074,0.3293,0.1887,-0.0340",\ +"0.5715,0.5598,0.5324,0.4895,0.4035,0.2512,0.0441",\ +"0.7043,0.7004,0.6730,0.6262,0.5402,0.3957,0.1809",\ +"0.9387,0.9270,0.8957,0.8527,0.7746,0.6262,0.4074"); + } + + fall_constraint("SIG2SRAM_constraint_template") { + index_1("0.0080,0.0288,0.0616,0.1072,0.1920,0.3496,0.5952"); + index_2("0.0080,0.0288,0.0616,0.1072,0.1920,0.3496,0.5952"); + values ("0.4152,0.3918,0.3645,0.3215,0.2395,0.1027,-0.1082",\ +"0.4309,0.4113,0.3801,0.3410,0.2590,0.1223,-0.0926",\ +"0.4582,0.4387,0.4074,0.3684,0.2863,0.1496,-0.0613",\ +"0.5012,0.4816,0.4504,0.4074,0.3293,0.1887,-0.0145",\ +"0.5715,0.5559,0.5285,0.4816,0.3996,0.2512,0.0598",\ +"0.7160,0.7004,0.6691,0.6262,0.5520,0.4035,0.2004",\ +"0.9387,0.9191,0.8957,0.8488,0.7707,0.6262,0.4113"); + } + } + } +pin(A_BIST_MEN) { + direction : input ; + capacitance : 0.00300347 ; + max_transition : "0.5952" ; + related_power_pin : VDD; + related_ground_pin : VSS; + internal_power() { + rise_power("scalar"){ + values (0.0091); + } + fall_power("scalar"){ + values (0.0001); + } + } + timing() { + timing_type : setup_rising; + related_pin : "A_BIST_CLK"; + + rise_constraint("SIG2SRAM_constraint_template") { + index_1("0.0080,0.0288,0.0616,0.1072,0.1920,0.3496,0.5952"); + index_2("0.0080,0.0288,0.0616,0.1072,0.1920,0.3496,0.5952"); + values ("0.3215,0.3449,0.3684,0.4113,0.4895,0.6301,0.8527",\ +"0.3059,0.3254,0.3527,0.3957,0.4738,0.6145,0.8371",\ +"0.2746,0.2941,0.3215,0.3645,0.4426,0.5871,0.8059",\ +"0.2316,0.2512,0.2785,0.3215,0.3996,0.5402,0.7629",\ +"0.1496,0.1730,0.1965,0.2395,0.3215,0.4660,0.6848",\ +"0.0090,0.0285,0.0598,0.1027,0.1809,0.3176,0.5402",\ +"-0.2098,-0.1902,-0.1668,-0.1199,-0.0418,0.0988,0.3137"); + } + + fall_constraint("SIG2SRAM_constraint_template") { + index_1("0.0080,0.0288,0.0616,0.1072,0.1920,0.3496,0.5952"); + index_2("0.0080,0.0288,0.0616,0.1072,0.1920,0.3496,0.5952"); + values ("0.4582,0.4738,0.5012,0.5363,0.6145,0.7395,0.9738",\ +"0.4387,0.4543,0.4816,0.5207,0.5910,0.7199,0.9582",\ +"0.4035,0.4230,0.4504,0.4855,0.5637,0.6887,0.9230",\ +"0.3645,0.3840,0.4074,0.4465,0.5285,0.6496,0.8840",\ +"0.2824,0.3020,0.3254,0.3645,0.4465,0.5715,0.7980",\ +"0.1418,0.1613,0.1887,0.2238,0.3020,0.4309,0.6496",\ +"-0.0770,-0.0574,-0.0301,0.0090,0.0910,0.2238,0.4191"); + } + } + + + timing() { + timing_type : hold_rising; + related_pin : "A_BIST_CLK"; + + rise_constraint("SIG2SRAM_constraint_template") { + index_1("0.0080,0.0288,0.0616,0.1072,0.1920,0.3496,0.5952"); + index_2("0.0080,0.0288,0.0616,0.1072,0.1920,0.3496,0.5952"); + values ("0.3762,0.3605,0.3293,0.2863,0.2043,0.0637,-0.1629",\ +"0.3996,0.3801,0.3488,0.3020,0.2238,0.0832,-0.1395",\ +"0.4230,0.4074,0.3723,0.3293,0.2473,0.1105,-0.1121",\ +"0.4621,0.4465,0.4152,0.3762,0.2941,0.1535,-0.0691",\ +"0.5441,0.5285,0.4973,0.4465,0.3684,0.2316,0.0090",\ +"0.6848,0.6652,0.6301,0.5910,0.5129,0.3605,0.1496",\ +"0.9074,0.8918,0.8566,0.8215,0.7395,0.5910,0.3723"); + } + + fall_constraint("SIG2SRAM_constraint_template") { + index_1("0.0080,0.0288,0.0616,0.1072,0.1920,0.3496,0.5952"); + index_2("0.0080,0.0288,0.0616,0.1072,0.1920,0.3496,0.5952"); + values ("0.3762,0.3605,0.3332,0.2863,0.2043,0.0715,-0.1395",\ +"0.3996,0.3762,0.3488,0.3059,0.2238,0.0910,-0.1199",\ +"0.4270,0.4035,0.3762,0.3332,0.2512,0.1184,-0.0965",\ +"0.4699,0.4504,0.4191,0.3762,0.2941,0.1613,-0.0496",\ +"0.5441,0.5285,0.4973,0.4543,0.3762,0.2355,0.0324",\ +"0.6770,0.6613,0.6340,0.5949,0.5207,0.3762,0.1652",\ +"0.9074,0.8918,0.8605,0.8176,0.7395,0.6027,0.3918"); + } + } + } +bus(A_BIST_BM) { + bus_type : D_7_0; + direction : input ; + capacitance : 0.00347781 ; + max_transition : "0.5952" ; + pin(A_BIST_BM[7:0]) { + related_power_pin : VDD; + related_ground_pin : VSS; + internal_power() { + when : "A_BIST_MEN"; + rise_power("scalar"){ + values (0.0236); + } + fall_power("scalar"){ + values (0.0076); + } + } + internal_power() { + when : "!A_BIST_MEN"; + rise_power("scalar"){ + values (0.0229); + } + fall_power("scalar"){ + values (0.0073); + } + } + } + timing() { + timing_type : setup_rising; + related_pin : "A_BIST_CLK"; + when : "(A_BIST_WEN & A_BIST_MEN)" + sdf_cond : "A_BIST_RW_ACCESS" + + rise_constraint("SIG2SRAM_constraint_template") { + index_1("0.0080,0.0288,0.0616,0.1072,0.1920,0.3496,0.5952"); + index_2("0.0080,0.0288,0.0616,0.1072,0.1920,0.3496,0.5952"); + values ("-0.5886,-0.5691,-0.5437,-0.5007,-0.4197,-0.2742,-0.0515",\ +"-0.5965,-0.5770,-0.5516,-0.5086,-0.4276,-0.2821,-0.0594",\ +"-0.6057,-0.5861,-0.5607,-0.5178,-0.4367,-0.2912,-0.0686",\ +"-0.6206,-0.6011,-0.5757,-0.5327,-0.4517,-0.3062,-0.0835",\ +"-0.6430,-0.6235,-0.5981,-0.5551,-0.4741,-0.3286,-0.1059",\ +"-0.6866,-0.6671,-0.6417,-0.5987,-0.5177,-0.3722,-0.1495",\ +"-0.7558,-0.7363,-0.7109,-0.6679,-0.5869,-0.4413,-0.2187"); + } + + fall_constraint("SIG2SRAM_constraint_template") { + index_1("0.0080,0.0288,0.0616,0.1072,0.1920,0.3496,0.5952"); + index_2("0.0080,0.0288,0.0616,0.1072,0.1920,0.3496,0.5952"); + values ("-0.5261,-0.5085,-0.4812,-0.4421,-0.3591,-0.2234,-0.0115",\ +"-0.5340,-0.5164,-0.4891,-0.4500,-0.3670,-0.2313,-0.0194",\ +"-0.5432,-0.5256,-0.4982,-0.4592,-0.3762,-0.2404,-0.0285",\ +"-0.5581,-0.5406,-0.5132,-0.4742,-0.3911,-0.2554,-0.0435",\ +"-0.5805,-0.5629,-0.5356,-0.4965,-0.4135,-0.2778,-0.0659",\ +"-0.6241,-0.6065,-0.5792,-0.5401,-0.4571,-0.3214,-0.1095",\ +"-0.6933,-0.6757,-0.6484,-0.6093,-0.5263,-0.3906,-0.1787"); + } + } + + + timing() { + timing_type : hold_rising; + related_pin : "A_BIST_CLK"; + when : "(A_BIST_WEN & A_BIST_MEN)" + sdf_cond : "A_BIST_RW_ACCESS" + + rise_constraint("SIG2SRAM_constraint_template") { + index_1("0.0080,0.0288,0.0616,0.1072,0.1920,0.3496,0.5952"); + index_2("0.0080,0.0288,0.0616,0.1072,0.1920,0.3496,0.5952"); + values ("0.7036,0.6821,0.6577,0.6148,0.5347,0.3882,0.1655",\ +"0.7115,0.6901,0.6656,0.6227,0.5426,0.3961,0.1735",\ +"0.7207,0.6992,0.6748,0.6318,0.5517,0.4053,0.1826",\ +"0.7357,0.7142,0.6898,0.6468,0.5667,0.4202,0.1976",\ +"0.7581,0.7366,0.7121,0.6692,0.5891,0.4426,0.2200",\ +"0.8016,0.7802,0.7558,0.7128,0.6327,0.4862,0.2636",\ +"0.8708,0.8493,0.8249,0.7820,0.7019,0.5554,0.3327"); + } + + fall_constraint("SIG2SRAM_constraint_template") { + index_1("0.0080,0.0288,0.0616,0.1072,0.1920,0.3496,0.5952"); + index_2("0.0080,0.0288,0.0616,0.1072,0.1920,0.3496,0.5952"); + values ("0.6294,0.6118,0.5845,0.5454,0.4624,0.3257,0.1148",\ +"0.6373,0.6197,0.5924,0.5533,0.4703,0.3336,0.1227",\ +"0.6465,0.6289,0.6015,0.5625,0.4795,0.3428,0.1318",\ +"0.6614,0.6439,0.6165,0.5775,0.4944,0.3577,0.1468",\ +"0.6838,0.6663,0.6389,0.5998,0.5168,0.3801,0.1692",\ +"0.7274,0.7098,0.6825,0.6434,0.5604,0.4237,0.2128",\ +"0.7966,0.7790,0.7517,0.7126,0.6296,0.4929,0.2820"); + } + } +} + pin(A_BIST_CLK) { + direction : input; + capacitance : 0.00378957; + max_transition : "0.5952"; + clock : "true" ; + pin_func_type : active_rising ; + + timing () { + timing_type : "min_pulse_width"; + related_pin : "A_BIST_CLK"; + rise_constraint("CLKTRAN_constraint_template") { + index_1("0.008,0.5952"); + values("0.4,0.4"); + } + } + + related_power_pin : VDD; + related_ground_pin : VSS; + + internal_power() { + when : "!A_BIST_MEN & !A_BIST_WEN & !A_BIST_REN"; + rise_power("scalar"){ + values (0); + } + fall_power("scalar"){ + values (0); + } + } + internal_power() { + when : "!A_BIST_MEN & A_BIST_WEN & !A_BIST_REN"; + rise_power("scalar"){ + values (0.4257); + } + fall_power("scalar"){ + values (0); + } + } + internal_power() { + when : "A_BIST_MEN & A_BIST_WEN & !A_BIST_REN"; + rise_power("scalar"){ + values (9.0428); + } + fall_power("scalar"){ + values (0); + } + } + internal_power() { + when : "A_BIST_MEN & A_BIST_WEN & A_BIST_REN"; + rise_power("scalar"){ + values (9.4016); + } + fall_power("scalar"){ + values (0); + } + } + internal_power() { + when : "A_BIST_MEN & !A_BIST_WEN & A_BIST_REN"; + rise_power("scalar"){ + values (6.8079); + } + fall_power("scalar"){ + values (0); + } + } + internal_power() { + when : "!A_BIST_MEN & !A_BIST_WEN & A_BIST_REN"; + rise_power("scalar"){ + values (0.2646); + } + fall_power("scalar"){ + values (0); + } + } + internal_power() { + when : "!A_BIST_MEN & A_BIST_WEN & A_BIST_REN"; + rise_power("scalar"){ + values (0.4709); + } + fall_power("scalar"){ + values (0); + } + } + internal_power() { + when : "A_BIST_MEN & !A_BIST_WEN & !A_BIST_REN"; + rise_power("scalar"){ + values (0); + } + fall_power("scalar"){ + values (0); + } + } + } + bus(A_BIST_DIN) { + bus_type : D_7_0; + direction : input ; + capacitance : 0.00396073 ; + memory_write() { + address : A_BIST_ADDR ; + clocked_on : A_BIST_CLK; + } + + max_transition : "0.5952" ; + pin(A_BIST_DIN[7:0]) { + related_power_pin : VDD; + related_ground_pin : VSS; + internal_power() { + when : "A_BIST_MEN"; + rise_power("scalar"){ + values (0.0236); + } + fall_power("scalar"){ + values (0.0076); + } + } + internal_power() { + when : "!A_BIST_MEN"; + rise_power("scalar"){ + values (0.0229); + } + fall_power("scalar"){ + values (0.0073); + } + } + } + timing() { + timing_type : setup_rising; + related_pin : "A_BIST_CLK"; + when : "(A_BIST_WEN & A_BIST_MEN)"; + sdf_cond : "A_BIST_W_ACCESS"; + + rise_constraint("SIG2SRAM_constraint_template") { + index_1("0.0080,0.0288,0.0616,0.1072,0.1920,0.3496,0.5952"); + index_2("0.0080,0.0288,0.0616,0.1072,0.1920,0.3496,0.5952"); + values ("-0.5886,-0.5691,-0.5437,-0.5007,-0.4197,-0.2742,-0.0515",\ +"-0.5965,-0.5770,-0.5516,-0.5086,-0.4276,-0.2821,-0.0594",\ +"-0.6057,-0.5861,-0.5607,-0.5178,-0.4367,-0.2912,-0.0686",\ +"-0.6206,-0.6011,-0.5757,-0.5327,-0.4517,-0.3062,-0.0835",\ +"-0.6430,-0.6235,-0.5981,-0.5551,-0.4741,-0.3286,-0.1059",\ +"-0.6866,-0.6671,-0.6417,-0.5987,-0.5177,-0.3722,-0.1495",\ +"-0.7558,-0.7363,-0.7109,-0.6679,-0.5869,-0.4413,-0.2187"); + } + + fall_constraint("SIG2SRAM_constraint_template") { + index_1("0.0080,0.0288,0.0616,0.1072,0.1920,0.3496,0.5952"); + index_2("0.0080,0.0288,0.0616,0.1072,0.1920,0.3496,0.5952"); + values ("-0.5261,-0.5085,-0.4812,-0.4421,-0.3591,-0.2234,-0.0115",\ +"-0.5340,-0.5164,-0.4891,-0.4500,-0.3670,-0.2313,-0.0194",\ +"-0.5432,-0.5256,-0.4982,-0.4592,-0.3762,-0.2404,-0.0285",\ +"-0.5581,-0.5406,-0.5132,-0.4742,-0.3911,-0.2554,-0.0435",\ +"-0.5805,-0.5629,-0.5356,-0.4965,-0.4135,-0.2778,-0.0659",\ +"-0.6241,-0.6065,-0.5792,-0.5401,-0.4571,-0.3214,-0.1095",\ +"-0.6933,-0.6757,-0.6484,-0.6093,-0.5263,-0.3906,-0.1787"); + } + } + + timing() { + timing_type : hold_rising; + related_pin : "A_BIST_CLK"; + when : "(A_BIST_WEN & A_BIST_MEN)"; + sdf_cond : "A_BIST_W_ACCESS"; + + rise_constraint("SIG2SRAM_constraint_template") { + index_1("0.0080,0.0288,0.0616,0.1072,0.1920,0.3496,0.5952"); + index_2("0.0080,0.0288,0.0616,0.1072,0.1920,0.3496,0.5952"); + values ("0.7036,0.6821,0.6577,0.6148,0.5347,0.3882,0.1655",\ +"0.7115,0.6901,0.6656,0.6227,0.5426,0.3961,0.1735",\ +"0.7207,0.6992,0.6748,0.6318,0.5517,0.4053,0.1826",\ +"0.7357,0.7142,0.6898,0.6468,0.5667,0.4202,0.1976",\ +"0.7581,0.7366,0.7121,0.6692,0.5891,0.4426,0.2200",\ +"0.8016,0.7802,0.7558,0.7128,0.6327,0.4862,0.2636",\ +"0.8708,0.8493,0.8249,0.7820,0.7019,0.5554,0.3327"); + } + + fall_constraint("SIG2SRAM_constraint_template") { + index_1("0.0080,0.0288,0.0616,0.1072,0.1920,0.3496,0.5952"); + index_2("0.0080,0.0288,0.0616,0.1072,0.1920,0.3496,0.5952"); + values ("0.6294,0.6118,0.5845,0.5454,0.4624,0.3257,0.1148",\ +"0.6373,0.6197,0.5924,0.5533,0.4703,0.3336,0.1227",\ +"0.6465,0.6289,0.6015,0.5625,0.4795,0.3428,0.1318",\ +"0.6614,0.6439,0.6165,0.5775,0.4944,0.3577,0.1468",\ +"0.6838,0.6663,0.6389,0.5998,0.5168,0.3801,0.1692",\ +"0.7274,0.7098,0.6825,0.6434,0.5604,0.4237,0.2128",\ +"0.7966,0.7790,0.7517,0.7126,0.6296,0.4929,0.2820"); + } + } + } + +bus(A_DOUT) { + + bus_type : D_7_0; + direction : output ; + capacitance : 0 ; + max_capacitance : 0.064 ; + memory_read() { + address : A_ADDR ; + } + pin(A_DOUT[7:0]) { + related_power_pin : VDD; + related_ground_pin : VSS; + internal_power() { + rise_power("scalar") { + values (0); + } + fall_power("scalar") { + values (0); + } + } + } + timing() { + related_pin : "A_CLK"; + timing_type : rising_edge ; + timing_sense : non_unate ; + + cell_rise(SIG2SRAM_delay_template) { + index_1("0.0080,0.0288,0.0616,0.1072,0.1920,0.3496,0.5952"); + index_2("0.0008,0.0014,0.0051,0.0100,0.0339,0.0640"); + values ("4.9845,4.9879,5.0000,5.0140,5.0665,5.1244",\ +"4.9984,5.0018,5.0139,5.0279,5.0805,5.1383",\ +"5.0083,5.0116,5.0238,5.0377,5.0903,5.1481",\ +"5.0215,5.0249,5.0371,5.0510,5.1036,5.1614",\ +"5.0448,5.0482,5.0604,5.0743,5.1269,5.1847",\ +"5.0896,5.0929,5.1051,5.1191,5.1716,5.2295",\ +"5.1568,5.1602,5.1724,5.1863,5.2389,5.2967"); + } + cell_fall(SIG2SRAM_delay_template) { + index_1("0.0080,0.0288,0.0616,0.1072,0.1920,0.3496,0.5952"); + index_2("0.0008,0.0014,0.0051,0.0100,0.0339,0.0640"); + values ("4.8748,4.8769,4.8870,4.8987,4.9420,4.9858",\ +"4.8887,4.8909,4.9009,4.9126,4.9559,4.9998",\ +"4.8985,4.9007,4.9107,4.9224,4.9658,5.0096",\ +"4.9118,4.9140,4.9240,4.9357,4.9791,5.0229",\ +"4.9351,4.9373,4.9473,4.9590,5.0023,5.0462",\ +"4.9798,4.9820,4.9921,5.0037,5.0471,5.0909",\ +"5.0471,5.0493,5.0593,5.0710,5.1143,5.1582"); + } + + rise_transition(SRAM_load_template) { + index_1("0.0008,0.0014,0.0051,0.0100,0.0339,0.0640"); + values ("0.0560,0.0583,0.0696,0.0816,0.1519,0.2335"); + } + fall_transition(SRAM_load_template) { + index_1("0.0008,0.0014,0.0051,0.0100,0.0339,0.0640"); + values ("0.0428,0.0445,0.0538,0.0658,0.1181,0.1751"); + } + } +} + pin(B_DLY) { + direction : input ; + capacitance : 0.00387999 ; + max_transition : "1" ; + related_power_pin : VDD; + related_ground_pin : VSS; + internal_power() { + rise_power("scalar") { + values (0); + } + fall_power("scalar") { + values (0); + } + } + } + +bus(B_ADDR) { + bus_type : A_7_0; + direction : input ; + capacitance : 0.0129586 ; + pin(B_ADDR[0]) { + capacitance : 0.00588404 ; + } + pin(B_ADDR[1]) { + capacitance : 0.0080425 ; + } + pin(B_ADDR[2]) { + capacitance : 0.0112051 ; + } + pin(B_ADDR[3]) { + capacitance : 0.00706428 ; + } + pin(B_ADDR[4]) { + capacitance : 0.00656149 ; + } + pin(B_ADDR[5]) { + capacitance : 0.0111839 ; + } + pin(B_ADDR[6]) { + capacitance : 0.0140236 ; + } + max_transition : "0.5952" ; + pin(B_ADDR[7:0]) { + related_power_pin : VDD; + related_ground_pin : VSS; + internal_power() { + when : "B_MEN"; + rise_power("scalar"){ + values (0.0105); + } + fall_power("scalar"){ + values (0.0079); + } + } + internal_power() { + when : "!B_MEN"; + rise_power("scalar"){ + values (0.0144); + } + fall_power("scalar"){ + values (0.0033); + } + } + } + timing() { + timing_type : setup_rising; + related_pin : "B_CLK"; + when : "((B_WEN | B_REN)& B_MEN)" + sdf_cond : "B_RW_ACCESS" + + rise_constraint("SIG2SRAM_constraint_template") { + index_1("0.0080,0.0288,0.0616,0.1072,0.1920,0.3496,0.5952"); + index_2("0.0080,0.0288,0.0616,0.1072,0.1920,0.3496,0.5952"); + values ("-0.7371,-0.7176,-0.6863,-0.6434,-0.5652,-0.4168,-0.1980",\ +"-0.7566,-0.7371,-0.7059,-0.6629,-0.5848,-0.4363,-0.2137",\ +"-0.7879,-0.7645,-0.7332,-0.6902,-0.6121,-0.4637,-0.2449",\ +"-0.8309,-0.8074,-0.7762,-0.7332,-0.6551,-0.5066,-0.2879",\ +"-0.9051,-0.8895,-0.8543,-0.8113,-0.7332,-0.5887,-0.3660",\ +"-1.0418,-1.0262,-0.9949,-0.9480,-0.8699,-0.7293,-0.5027",\ +"-1.2684,-1.2449,-1.2176,-1.1707,-1.0965,-0.9480,-0.7293"); + } + + fall_constraint("SIG2SRAM_constraint_template") { + index_1("0.0080,0.0288,0.0616,0.1072,0.1920,0.3496,0.5952"); + index_2("0.0080,0.0288,0.0616,0.1072,0.1920,0.3496,0.5952"); + values ("-0.5926,-0.5730,-0.5418,-0.4988,-0.4246,-0.2879,-0.0730",\ +"-0.6121,-0.5926,-0.5613,-0.5223,-0.4441,-0.3074,-0.0887",\ +"-0.6395,-0.6199,-0.5926,-0.5496,-0.4715,-0.3348,-0.1160",\ +"-0.6863,-0.6668,-0.6355,-0.5965,-0.5184,-0.3777,-0.1590",\ +"-0.7605,-0.7410,-0.7137,-0.6746,-0.5926,-0.4559,-0.2410",\ +"-0.9012,-0.8816,-0.8504,-0.8113,-0.7332,-0.5926,-0.3895",\ +"-1.1238,-1.1043,-1.0769,-1.0379,-0.9559,-0.8191,-0.6004"); + } + } + + + timing() { + timing_type : hold_rising; + related_pin : "B_CLK"; + when : "((B_WEN | B_REN)& B_MEN)" + sdf_cond : "B_RW_ACCESS" + + rise_constraint("SIG2SRAM_constraint_template") { + index_1("0.0080,0.0288,0.0616,0.1072,0.1920,0.3496,0.5952"); + index_2("0.0080,0.0288,0.0616,0.1072,0.1920,0.3496,0.5952"); + values ("0.8488,0.8293,0.7980,0.7551,0.6730,0.5285,0.3059",\ +"0.8684,0.8488,0.8176,0.7746,0.6926,0.5480,0.3254",\ +"0.8996,0.8801,0.8449,0.8020,0.7238,0.5754,0.3527",\ +"0.9426,0.9191,0.8918,0.8488,0.7668,0.6223,0.3996",\ +"1.0168,1.0012,0.9699,0.9230,0.8449,0.7004,0.4777",\ +"1.1574,1.1379,1.1105,1.0598,0.9816,0.8371,0.6184",\ +"1.3801,1.3605,1.3254,1.2980,1.2043,1.0637,0.8371"); + } + + fall_constraint("SIG2SRAM_constraint_template") { + index_1("0.0080,0.0288,0.0616,0.1072,0.1920,0.3496,0.5952"); + index_2("0.0080,0.0288,0.0616,0.1072,0.1920,0.3496,0.5952"); + values ("0.6965,0.6770,0.6496,0.6066,0.5246,0.3918,0.1730",\ +"0.7160,0.6965,0.6652,0.6262,0.5441,0.4113,0.1965",\ +"0.7473,0.7277,0.6965,0.6535,0.5754,0.4426,0.2238",\ +"0.7863,0.7707,0.7395,0.7004,0.6223,0.4855,0.2629",\ +"0.8684,0.8449,0.8176,0.7785,0.7004,0.5637,0.3449",\ +"1.0051,0.9855,0.9855,0.9113,0.8332,0.7004,0.4895",\ +"1.2277,1.2082,1.1809,1.1379,1.0598,0.9230,0.7004"); + } + } +} +pin(B_WEN) { + direction : input ; + capacitance : 0.00313551 ; + max_transition : "0.5952" ; + related_power_pin : VDD; + related_ground_pin : VSS; + internal_power() { + when : "B_MEN"; + rise_power("scalar"){ + values (0.0036); + } + fall_power("scalar"){ + values (0.0008); + } + } + internal_power() { + when : "!B_MEN"; + rise_power("scalar"){ + values (0.0049); + } + fall_power("scalar"){ + values (0.0004); + } + } + timing() { + timing_type : setup_rising; + related_pin : "B_CLK"; + when : "B_MEN" + sdf_cond : "B_MEN" + + rise_constraint("SIG2SRAM_constraint_template") { + index_1("0.0080,0.0288,0.0616,0.1072,0.1920,0.3496,0.5952"); + index_2("0.0080,0.0288,0.0616,0.1072,0.1920,0.3496,0.5952"); + values ("0.3137,0.3332,0.3605,0.4035,0.4816,0.6223,0.8488",\ +"0.2980,0.3176,0.3410,0.3840,0.4660,0.6027,0.8293",\ +"0.2629,0.2824,0.3098,0.3527,0.4348,0.5754,0.7980",\ +"0.2199,0.2395,0.2668,0.3098,0.3918,0.5324,0.7590",\ +"0.1418,0.1613,0.1887,0.2316,0.3137,0.4348,0.6730",\ +"0.0012,0.0207,0.0520,0.0910,0.1730,0.3098,0.5285",\ +"-0.2215,-0.2020,-0.1746,-0.1277,-0.0496,0.0910,0.3098"); + } + + fall_constraint("SIG2SRAM_constraint_template") { + index_1("0.0080,0.0288,0.0616,0.1072,0.1920,0.3496,0.5952"); + index_2("0.0080,0.0288,0.0616,0.1072,0.1920,0.3496,0.5952"); + values ("0.4504,0.4699,0.4973,0.5324,0.6027,0.7355,0.9699",\ +"0.4309,0.4504,0.4777,0.5129,0.5910,0.7160,0.9504",\ +"0.3996,0.4191,0.4465,0.4816,0.5520,0.6848,0.9191",\ +"0.3605,0.3762,0.4035,0.4387,0.5168,0.6418,0.8723",\ +"0.2785,0.2980,0.3215,0.3605,0.4348,0.5637,0.7980",\ +"0.1379,0.1574,0.1809,0.2199,0.2980,0.4309,0.6457",\ +"-0.0809,-0.0613,-0.0340,0.0051,0.0832,0.2160,0.4191"); + } + } + + + timing() { + timing_type : hold_rising; + related_pin : "B_CLK"; + when : "B_MEN" + sdf_cond : "B_MEN" + + rise_constraint("SIG2SRAM_constraint_template") { + index_1("0.0080,0.0288,0.0616,0.1072,0.1920,0.3496,0.5952"); + index_2("0.0080,0.0288,0.0616,0.1072,0.1920,0.3496,0.5952"); + values ("0.3723,0.3527,0.3215,0.2785,0.1965,0.0559,-0.1668",\ +"0.3918,0.3723,0.3449,0.2980,0.2160,0.0754,-0.1473",\ +"0.4152,0.3996,0.3684,0.3254,0.2434,0.1066,-0.1199",\ +"0.4621,0.4465,0.4152,0.3723,0.2863,0.1496,-0.0730",\ +"0.5324,0.5207,0.4895,0.4465,0.3645,0.2199,0.0051",\ +"0.6770,0.6535,0.6301,0.5832,0.5090,0.3605,0.1418",\ +"0.9035,0.8879,0.8566,0.8137,0.7316,0.5871,0.3684"); + } + + fall_constraint("SIG2SRAM_constraint_template") { + index_1("0.0080,0.0288,0.0616,0.1072,0.1920,0.3496,0.5952"); + index_2("0.0080,0.0288,0.0616,0.1072,0.1920,0.3496,0.5952"); + values ("0.3762,0.3566,0.3293,0.2863,0.2043,0.0676,-0.1434",\ +"0.3957,0.3762,0.3488,0.3059,0.2238,0.0871,-0.1199",\ +"0.4230,0.4035,0.3723,0.3332,0.2512,0.1184,-0.0965",\ +"0.4660,0.4465,0.4191,0.3762,0.2941,0.1613,-0.0496",\ +"0.5324,0.5168,0.4973,0.4543,0.3723,0.2316,0.0285",\ +"0.6809,0.6613,0.6340,0.5910,0.5129,0.3645,0.1652",\ +"0.9113,0.8918,0.8605,0.8176,0.7395,0.5988,0.3879"); + } + } + } +pin(B_REN) { + direction : input ; + capacitance : 0.00381144 ; + max_transition : "0.5952" ; + related_power_pin : VDD; + related_ground_pin : VSS; + internal_power() { + when : "B_MEN"; + rise_power("scalar"){ + values (0.0040); + } + fall_power("scalar"){ + values (0.0016); + } + } + internal_power() { + when : "!B_MEN"; + rise_power("scalar"){ + values (0.0040); + } + fall_power("scalar"){ + values (0.0014); + } + } + timing() { + timing_type : setup_rising; + related_pin : "B_CLK"; + when : "B_MEN" + sdf_cond : "B_MEN" + + rise_constraint("SIG2SRAM_constraint_template") { + index_1("0.0080,0.0288,0.0616,0.1072,0.1920,0.3496,0.5952"); + index_2("0.0080,0.0288,0.0616,0.1072,0.1920,0.3496,0.5952"); + values ("-0.0770,-0.0574,-0.0262,0.0168,0.0949,0.2355,0.4582",\ +"-0.0965,-0.0770,-0.0457,-0.0027,0.0754,0.2160,0.4387",\ +"-0.1199,-0.1004,-0.0730,-0.0262,0.0520,0.1887,0.4113",\ +"-0.1590,-0.1434,-0.1160,-0.0730,0.0051,0.1457,0.3645",\ +"-0.2449,-0.2254,-0.1941,-0.1473,-0.0770,0.0676,0.2863",\ +"-0.3816,-0.3699,-0.3387,-0.2801,-0.2215,-0.0770,0.1457",\ +"-0.6121,-0.5926,-0.5613,-0.5145,-0.4363,-0.2996,-0.0730"); + } + + fall_constraint("SIG2SRAM_constraint_template") { + index_1("0.0080,0.0288,0.0616,0.1072,0.1920,0.3496,0.5952"); + index_2("0.0080,0.0288,0.0616,0.1072,0.1920,0.3496,0.5952"); + values ("0.1262,0.1457,0.1691,0.2121,0.2824,0.4191,0.6457",\ +"0.1105,0.1262,0.1496,0.1887,0.2629,0.3996,0.6262",\ +"0.0793,0.0949,0.1223,0.1652,0.2395,0.3684,0.5949",\ +"0.0363,0.0559,0.0793,0.1223,0.2004,0.3410,0.5520",\ +"-0.0457,-0.0262,0.0012,0.0441,0.1301,0.2629,0.4738",\ +"-0.1902,-0.1746,-0.1434,-0.1043,-0.0184,0.1223,0.3332",\ +"-0.4129,-0.3934,-0.3660,-0.3230,-0.2449,-0.1043,0.1105"); + } + } + + + timing() { + timing_type : hold_rising; + related_pin : "B_CLK"; + when : "B_MEN" + sdf_cond : "B_MEN" + + rise_constraint("SIG2SRAM_constraint_template") { + index_1("0.0080,0.0288,0.0616,0.1072,0.1920,0.3496,0.5952"); + index_2("0.0080,0.0288,0.0616,0.1072,0.1920,0.3496,0.5952"); + values ("0.4113,0.3918,0.3645,0.3176,0.2395,0.0988,-0.1238",\ +"0.4309,0.4113,0.3840,0.3371,0.2590,0.1184,-0.1043",\ +"0.4582,0.4387,0.4113,0.3645,0.2824,0.1457,-0.0770",\ +"0.5051,0.4816,0.4543,0.4074,0.3293,0.1887,-0.0340",\ +"0.5715,0.5598,0.5324,0.4895,0.4035,0.2512,0.0441",\ +"0.7043,0.7004,0.6730,0.6262,0.5402,0.3957,0.1809",\ +"0.9387,0.9270,0.8957,0.8527,0.7746,0.6262,0.4074"); + } + + fall_constraint("SIG2SRAM_constraint_template") { + index_1("0.0080,0.0288,0.0616,0.1072,0.1920,0.3496,0.5952"); + index_2("0.0080,0.0288,0.0616,0.1072,0.1920,0.3496,0.5952"); + values ("0.4152,0.3918,0.3645,0.3215,0.2395,0.1027,-0.1082",\ +"0.4309,0.4113,0.3801,0.3410,0.2590,0.1223,-0.0926",\ +"0.4582,0.4387,0.4074,0.3684,0.2863,0.1496,-0.0613",\ +"0.5012,0.4816,0.4504,0.4074,0.3293,0.1887,-0.0145",\ +"0.5715,0.5559,0.5285,0.4816,0.3996,0.2512,0.0598",\ +"0.7160,0.7004,0.6691,0.6262,0.5520,0.4035,0.2004",\ +"0.9387,0.9191,0.8957,0.8488,0.7707,0.6262,0.4113"); + } + } + } +pin(B_MEN) { + direction : input ; + capacitance : 0.00300347 ; + max_transition : "0.5952" ; + related_power_pin : VDD; + related_ground_pin : VSS; + internal_power() { + rise_power("scalar"){ + values (0.0091); + } + fall_power("scalar"){ + values (0.0001); + } + } + timing() { + timing_type : setup_rising; + related_pin : "B_CLK"; + + rise_constraint("SIG2SRAM_constraint_template") { + index_1("0.0080,0.0288,0.0616,0.1072,0.1920,0.3496,0.5952"); + index_2("0.0080,0.0288,0.0616,0.1072,0.1920,0.3496,0.5952"); + values ("0.3215,0.3449,0.3684,0.4113,0.4895,0.6301,0.8527",\ +"0.3059,0.3254,0.3527,0.3957,0.4738,0.6145,0.8371",\ +"0.2746,0.2941,0.3215,0.3645,0.4426,0.5871,0.8059",\ +"0.2316,0.2512,0.2785,0.3215,0.3996,0.5402,0.7629",\ +"0.1496,0.1730,0.1965,0.2395,0.3215,0.4660,0.6848",\ +"0.0090,0.0285,0.0598,0.1027,0.1809,0.3176,0.5402",\ +"-0.2098,-0.1902,-0.1668,-0.1199,-0.0418,0.0988,0.3137"); + } + + fall_constraint("SIG2SRAM_constraint_template") { + index_1("0.0080,0.0288,0.0616,0.1072,0.1920,0.3496,0.5952"); + index_2("0.0080,0.0288,0.0616,0.1072,0.1920,0.3496,0.5952"); + values ("0.4582,0.4738,0.5012,0.5363,0.6145,0.7395,0.9738",\ +"0.4387,0.4543,0.4816,0.5207,0.5910,0.7199,0.9582",\ +"0.4035,0.4230,0.4504,0.4855,0.5637,0.6887,0.9230",\ +"0.3645,0.3840,0.4074,0.4465,0.5285,0.6496,0.8840",\ +"0.2824,0.3020,0.3254,0.3645,0.4465,0.5715,0.7980",\ +"0.1418,0.1613,0.1887,0.2238,0.3020,0.4309,0.6496",\ +"-0.0770,-0.0574,-0.0301,0.0090,0.0910,0.2238,0.4191"); + } + } + + + timing() { + timing_type : hold_rising; + related_pin : "B_CLK"; + + rise_constraint("SIG2SRAM_constraint_template") { + index_1("0.0080,0.0288,0.0616,0.1072,0.1920,0.3496,0.5952"); + index_2("0.0080,0.0288,0.0616,0.1072,0.1920,0.3496,0.5952"); + values ("0.3762,0.3605,0.3293,0.2863,0.2043,0.0637,-0.1629",\ +"0.3996,0.3801,0.3488,0.3020,0.2238,0.0832,-0.1395",\ +"0.4230,0.4074,0.3723,0.3293,0.2473,0.1105,-0.1121",\ +"0.4621,0.4465,0.4152,0.3762,0.2941,0.1535,-0.0691",\ +"0.5441,0.5285,0.4973,0.4465,0.3684,0.2316,0.0090",\ +"0.6848,0.6652,0.6301,0.5910,0.5129,0.3605,0.1496",\ +"0.9074,0.8918,0.8566,0.8215,0.7395,0.5910,0.3723"); + } + + fall_constraint("SIG2SRAM_constraint_template") { + index_1("0.0080,0.0288,0.0616,0.1072,0.1920,0.3496,0.5952"); + index_2("0.0080,0.0288,0.0616,0.1072,0.1920,0.3496,0.5952"); + values ("0.3762,0.3605,0.3332,0.2863,0.2043,0.0715,-0.1395",\ +"0.3996,0.3762,0.3488,0.3059,0.2238,0.0910,-0.1199",\ +"0.4270,0.4035,0.3762,0.3332,0.2512,0.1184,-0.0965",\ +"0.4699,0.4504,0.4191,0.3762,0.2941,0.1613,-0.0496",\ +"0.5441,0.5285,0.4973,0.4543,0.3762,0.2355,0.0324",\ +"0.6770,0.6613,0.6340,0.5949,0.5207,0.3762,0.1652",\ +"0.9074,0.8918,0.8605,0.8176,0.7395,0.6027,0.3918"); + } + } + } +bus(B_BM) { + bus_type : D_7_0; + direction : input ; + capacitance : 0.00293202 ; + max_transition : "0.5952" ; + pin(B_BM[7:0]) { + related_power_pin : VDD; + related_ground_pin : VSS; + internal_power() { + when : "B_MEN"; + rise_power("scalar"){ + values (0.0236); + } + fall_power("scalar"){ + values (0.0076); + } + } + internal_power() { + when : "!B_MEN"; + rise_power("scalar"){ + values (0.0229); + } + fall_power("scalar"){ + values (0.0073); + } + } + } + timing() { + timing_type : setup_rising; + related_pin : "B_CLK"; + when : "(B_WEN & B_MEN)" + sdf_cond : "B_RW_ACCESS" + + rise_constraint("SIG2SRAM_constraint_template") { + index_1("0.0080,0.0288,0.0616,0.1072,0.1920,0.3496,0.5952"); + index_2("0.0080,0.0288,0.0616,0.1072,0.1920,0.3496,0.5952"); + values ("-0.5886,-0.5691,-0.5437,-0.5007,-0.4197,-0.2742,-0.0515",\ +"-0.5965,-0.5770,-0.5516,-0.5086,-0.4276,-0.2821,-0.0594",\ +"-0.6057,-0.5861,-0.5607,-0.5178,-0.4367,-0.2912,-0.0686",\ +"-0.6206,-0.6011,-0.5757,-0.5327,-0.4517,-0.3062,-0.0835",\ +"-0.6430,-0.6235,-0.5981,-0.5551,-0.4741,-0.3286,-0.1059",\ +"-0.6866,-0.6671,-0.6417,-0.5987,-0.5177,-0.3722,-0.1495",\ +"-0.7558,-0.7363,-0.7109,-0.6679,-0.5869,-0.4413,-0.2187"); + } + + fall_constraint("SIG2SRAM_constraint_template") { + index_1("0.0080,0.0288,0.0616,0.1072,0.1920,0.3496,0.5952"); + index_2("0.0080,0.0288,0.0616,0.1072,0.1920,0.3496,0.5952"); + values ("-0.5261,-0.5085,-0.4812,-0.4421,-0.3591,-0.2234,-0.0115",\ +"-0.5340,-0.5164,-0.4891,-0.4500,-0.3670,-0.2313,-0.0194",\ +"-0.5432,-0.5256,-0.4982,-0.4592,-0.3762,-0.2404,-0.0285",\ +"-0.5581,-0.5406,-0.5132,-0.4742,-0.3911,-0.2554,-0.0435",\ +"-0.5805,-0.5629,-0.5356,-0.4965,-0.4135,-0.2778,-0.0659",\ +"-0.6241,-0.6065,-0.5792,-0.5401,-0.4571,-0.3214,-0.1095",\ +"-0.6933,-0.6757,-0.6484,-0.6093,-0.5263,-0.3906,-0.1787"); + } + } + + + timing() { + timing_type : hold_rising; + related_pin : "B_CLK"; + when : "(B_WEN & B_MEN)" + sdf_cond : "B_RW_ACCESS" + + rise_constraint("SIG2SRAM_constraint_template") { + index_1("0.0080,0.0288,0.0616,0.1072,0.1920,0.3496,0.5952"); + index_2("0.0080,0.0288,0.0616,0.1072,0.1920,0.3496,0.5952"); + values ("0.7036,0.6821,0.6577,0.6148,0.5347,0.3882,0.1655",\ +"0.7115,0.6901,0.6656,0.6227,0.5426,0.3961,0.1735",\ +"0.7207,0.6992,0.6748,0.6318,0.5517,0.4053,0.1826",\ +"0.7357,0.7142,0.6898,0.6468,0.5667,0.4202,0.1976",\ +"0.7581,0.7366,0.7121,0.6692,0.5891,0.4426,0.2200",\ +"0.8016,0.7802,0.7558,0.7128,0.6327,0.4862,0.2636",\ +"0.8708,0.8493,0.8249,0.7820,0.7019,0.5554,0.3327"); + } + + fall_constraint("SIG2SRAM_constraint_template") { + index_1("0.0080,0.0288,0.0616,0.1072,0.1920,0.3496,0.5952"); + index_2("0.0080,0.0288,0.0616,0.1072,0.1920,0.3496,0.5952"); + values ("0.6294,0.6118,0.5845,0.5454,0.4624,0.3257,0.1148",\ +"0.6373,0.6197,0.5924,0.5533,0.4703,0.3336,0.1227",\ +"0.6465,0.6289,0.6015,0.5625,0.4795,0.3428,0.1318",\ +"0.6614,0.6439,0.6165,0.5775,0.4944,0.3577,0.1468",\ +"0.6838,0.6663,0.6389,0.5998,0.5168,0.3801,0.1692",\ +"0.7274,0.7098,0.6825,0.6434,0.5604,0.4237,0.2128",\ +"0.7966,0.7790,0.7517,0.7126,0.6296,0.4929,0.2820"); + } + } +} + pin(B_CLK) { + direction : input; + capacitance : 0.00378957; + max_transition : "0.5952"; + clock : "true" ; + pin_func_type : active_rising ; + + timing () { + timing_type : "min_pulse_width"; + related_pin : "B_CLK"; + rise_constraint("CLKTRAN_constraint_template") { + index_1("0.008,0.5952"); + values("0.4,0.4"); + } + } + + related_power_pin : VDD; + related_ground_pin : VSS; + + internal_power() { + when : "!B_MEN & !B_WEN & !B_REN"; + rise_power("scalar"){ + values (0); + } + fall_power("scalar"){ + values (0); + } + } + internal_power() { + when : "!B_MEN & B_WEN & !B_REN"; + rise_power("scalar"){ + values (0.4257); + } + fall_power("scalar"){ + values (0); + } + } + internal_power() { + when : "B_MEN & B_WEN & !B_REN"; + rise_power("scalar"){ + values (9.0428); + } + fall_power("scalar"){ + values (0); + } + } + internal_power() { + when : "B_MEN & B_WEN & B_REN"; + rise_power("scalar"){ + values (9.4016); + } + fall_power("scalar"){ + values (0); + } + } + internal_power() { + when : "B_MEN & !B_WEN & B_REN"; + rise_power("scalar"){ + values (6.8079); + } + fall_power("scalar"){ + values (0); + } + } + internal_power() { + when : "!B_MEN & !B_WEN & B_REN"; + rise_power("scalar"){ + values (0.2646); + } + fall_power("scalar"){ + values (0); + } + } + internal_power() { + when : "!B_MEN & B_WEN & B_REN"; + rise_power("scalar"){ + values (0.4709); + } + fall_power("scalar"){ + values (0); + } + } + internal_power() { + when : "B_MEN & !B_WEN & !B_REN"; + rise_power("scalar"){ + values (0); + } + fall_power("scalar"){ + values (0); + } + } + } + bus(B_DIN) { + bus_type : D_7_0; + direction : input ; + capacitance : 0.00460366 ; + memory_write() { + address : B_ADDR ; + clocked_on : B_CLK; + } + + max_transition : "0.5952" ; + pin(B_DIN[7:0]) { + related_power_pin : VDD; + related_ground_pin : VSS; + internal_power() { + when : "B_MEN"; + rise_power("scalar"){ + values (0.0236); + } + fall_power("scalar"){ + values (0.0076); + } + } + internal_power() { + when : "!B_MEN"; + rise_power("scalar"){ + values (0.0229); + } + fall_power("scalar"){ + values (0.0073); + } + } + } + timing() { + timing_type : setup_rising; + related_pin : "B_CLK"; + when : "(B_WEN & B_MEN)"; + sdf_cond : "B_W_ACCESS"; + + rise_constraint("SIG2SRAM_constraint_template") { + index_1("0.0080,0.0288,0.0616,0.1072,0.1920,0.3496,0.5952"); + index_2("0.0080,0.0288,0.0616,0.1072,0.1920,0.3496,0.5952"); + values ("-0.5886,-0.5691,-0.5437,-0.5007,-0.4197,-0.2742,-0.0515",\ +"-0.5965,-0.5770,-0.5516,-0.5086,-0.4276,-0.2821,-0.0594",\ +"-0.6057,-0.5861,-0.5607,-0.5178,-0.4367,-0.2912,-0.0686",\ +"-0.6206,-0.6011,-0.5757,-0.5327,-0.4517,-0.3062,-0.0835",\ +"-0.6430,-0.6235,-0.5981,-0.5551,-0.4741,-0.3286,-0.1059",\ +"-0.6866,-0.6671,-0.6417,-0.5987,-0.5177,-0.3722,-0.1495",\ +"-0.7558,-0.7363,-0.7109,-0.6679,-0.5869,-0.4413,-0.2187"); + } + + fall_constraint("SIG2SRAM_constraint_template") { + index_1("0.0080,0.0288,0.0616,0.1072,0.1920,0.3496,0.5952"); + index_2("0.0080,0.0288,0.0616,0.1072,0.1920,0.3496,0.5952"); + values ("-0.5261,-0.5085,-0.4812,-0.4421,-0.3591,-0.2234,-0.0115",\ +"-0.5340,-0.5164,-0.4891,-0.4500,-0.3670,-0.2313,-0.0194",\ +"-0.5432,-0.5256,-0.4982,-0.4592,-0.3762,-0.2404,-0.0285",\ +"-0.5581,-0.5406,-0.5132,-0.4742,-0.3911,-0.2554,-0.0435",\ +"-0.5805,-0.5629,-0.5356,-0.4965,-0.4135,-0.2778,-0.0659",\ +"-0.6241,-0.6065,-0.5792,-0.5401,-0.4571,-0.3214,-0.1095",\ +"-0.6933,-0.6757,-0.6484,-0.6093,-0.5263,-0.3906,-0.1787"); + } + } + + timing() { + timing_type : hold_rising; + related_pin : "B_CLK"; + when : "(B_WEN & B_MEN)"; + sdf_cond : "B_W_ACCESS"; + + rise_constraint("SIG2SRAM_constraint_template") { + index_1("0.0080,0.0288,0.0616,0.1072,0.1920,0.3496,0.5952"); + index_2("0.0080,0.0288,0.0616,0.1072,0.1920,0.3496,0.5952"); + values ("0.7036,0.6821,0.6577,0.6148,0.5347,0.3882,0.1655",\ +"0.7115,0.6901,0.6656,0.6227,0.5426,0.3961,0.1735",\ +"0.7207,0.6992,0.6748,0.6318,0.5517,0.4053,0.1826",\ +"0.7357,0.7142,0.6898,0.6468,0.5667,0.4202,0.1976",\ +"0.7581,0.7366,0.7121,0.6692,0.5891,0.4426,0.2200",\ +"0.8016,0.7802,0.7558,0.7128,0.6327,0.4862,0.2636",\ +"0.8708,0.8493,0.8249,0.7820,0.7019,0.5554,0.3327"); + } + + fall_constraint("SIG2SRAM_constraint_template") { + index_1("0.0080,0.0288,0.0616,0.1072,0.1920,0.3496,0.5952"); + index_2("0.0080,0.0288,0.0616,0.1072,0.1920,0.3496,0.5952"); + values ("0.6294,0.6118,0.5845,0.5454,0.4624,0.3257,0.1148",\ +"0.6373,0.6197,0.5924,0.5533,0.4703,0.3336,0.1227",\ +"0.6465,0.6289,0.6015,0.5625,0.4795,0.3428,0.1318",\ +"0.6614,0.6439,0.6165,0.5775,0.4944,0.3577,0.1468",\ +"0.6838,0.6663,0.6389,0.5998,0.5168,0.3801,0.1692",\ +"0.7274,0.7098,0.6825,0.6434,0.5604,0.4237,0.2128",\ +"0.7966,0.7790,0.7517,0.7126,0.6296,0.4929,0.2820"); + } + } + } + + pin(B_BIST_EN) { + direction : input ; + capacitance : 0.00387999 ; + max_transition : "1" ; + related_power_pin : VDD; + related_ground_pin : VSS; + internal_power() { + rise_power("scalar") { + values (0); + } + fall_power("scalar") { + values (0); + } + } + } + +bus(B_BIST_ADDR) { + bus_type : A_7_0; + direction : input ; + capacitance : 0.0129586 ; + pin(B_BIST_ADDR[0]) { + capacitance : 0.00588404 ; + } + pin(B_BIST_ADDR[1]) { + capacitance : 0.0080425 ; + } + pin(B_BIST_ADDR[2]) { + capacitance : 0.0112051 ; + } + pin(B_BIST_ADDR[3]) { + capacitance : 0.00706428 ; + } + pin(B_BIST_ADDR[4]) { + capacitance : 0.00656149 ; + } + pin(B_BIST_ADDR[5]) { + capacitance : 0.0111839 ; + } + pin(B_BIST_ADDR[6]) { + capacitance : 0.0140236 ; + } + max_transition : "0.5952" ; + pin(B_BIST_ADDR[7:0]) { + related_power_pin : VDD; + related_ground_pin : VSS; + internal_power() { + when : "B_BIST_MEN"; + rise_power("scalar"){ + values (0.0105); + } + fall_power("scalar"){ + values (0.0079); + } + } + internal_power() { + when : "!B_BIST_MEN"; + rise_power("scalar"){ + values (0.0144); + } + fall_power("scalar"){ + values (0.0033); + } + } + } + timing() { + timing_type : setup_rising; + related_pin : "B_BIST_CLK"; + when : "((B_BIST_WEN | B_BIST_REN)& B_BIST_MEN)" + sdf_cond : "B_BIST_RW_ACCESS" + + rise_constraint("SIG2SRAM_constraint_template") { + index_1("0.0080,0.0288,0.0616,0.1072,0.1920,0.3496,0.5952"); + index_2("0.0080,0.0288,0.0616,0.1072,0.1920,0.3496,0.5952"); + values ("-0.7371,-0.7176,-0.6863,-0.6434,-0.5652,-0.4168,-0.1980",\ +"-0.7566,-0.7371,-0.7059,-0.6629,-0.5848,-0.4363,-0.2137",\ +"-0.7879,-0.7645,-0.7332,-0.6902,-0.6121,-0.4637,-0.2449",\ +"-0.8309,-0.8074,-0.7762,-0.7332,-0.6551,-0.5066,-0.2879",\ +"-0.9051,-0.8895,-0.8543,-0.8113,-0.7332,-0.5887,-0.3660",\ +"-1.0418,-1.0262,-0.9949,-0.9480,-0.8699,-0.7293,-0.5027",\ +"-1.2684,-1.2449,-1.2176,-1.1707,-1.0965,-0.9480,-0.7293"); + } + + fall_constraint("SIG2SRAM_constraint_template") { + index_1("0.0080,0.0288,0.0616,0.1072,0.1920,0.3496,0.5952"); + index_2("0.0080,0.0288,0.0616,0.1072,0.1920,0.3496,0.5952"); + values ("-0.5926,-0.5730,-0.5418,-0.4988,-0.4246,-0.2879,-0.0730",\ +"-0.6121,-0.5926,-0.5613,-0.5223,-0.4441,-0.3074,-0.0887",\ +"-0.6395,-0.6199,-0.5926,-0.5496,-0.4715,-0.3348,-0.1160",\ +"-0.6863,-0.6668,-0.6355,-0.5965,-0.5184,-0.3777,-0.1590",\ +"-0.7605,-0.7410,-0.7137,-0.6746,-0.5926,-0.4559,-0.2410",\ +"-0.9012,-0.8816,-0.8504,-0.8113,-0.7332,-0.5926,-0.3895",\ +"-1.1238,-1.1043,-1.0769,-1.0379,-0.9559,-0.8191,-0.6004"); + } + } + + + timing() { + timing_type : hold_rising; + related_pin : "B_BIST_CLK"; + when : "((B_BIST_WEN | B_BIST_REN)& B_BIST_MEN)" + sdf_cond : "B_BIST_RW_ACCESS" + + rise_constraint("SIG2SRAM_constraint_template") { + index_1("0.0080,0.0288,0.0616,0.1072,0.1920,0.3496,0.5952"); + index_2("0.0080,0.0288,0.0616,0.1072,0.1920,0.3496,0.5952"); + values ("0.8488,0.8293,0.7980,0.7551,0.6730,0.5285,0.3059",\ +"0.8684,0.8488,0.8176,0.7746,0.6926,0.5480,0.3254",\ +"0.8996,0.8801,0.8449,0.8020,0.7238,0.5754,0.3527",\ +"0.9426,0.9191,0.8918,0.8488,0.7668,0.6223,0.3996",\ +"1.0168,1.0012,0.9699,0.9230,0.8449,0.7004,0.4777",\ +"1.1574,1.1379,1.1105,1.0598,0.9816,0.8371,0.6184",\ +"1.3801,1.3605,1.3254,1.2980,1.2043,1.0637,0.8371"); + } + + fall_constraint("SIG2SRAM_constraint_template") { + index_1("0.0080,0.0288,0.0616,0.1072,0.1920,0.3496,0.5952"); + index_2("0.0080,0.0288,0.0616,0.1072,0.1920,0.3496,0.5952"); + values ("0.6965,0.6770,0.6496,0.6066,0.5246,0.3918,0.1730",\ +"0.7160,0.6965,0.6652,0.6262,0.5441,0.4113,0.1965",\ +"0.7473,0.7277,0.6965,0.6535,0.5754,0.4426,0.2238",\ +"0.7863,0.7707,0.7395,0.7004,0.6223,0.4855,0.2629",\ +"0.8684,0.8449,0.8176,0.7785,0.7004,0.5637,0.3449",\ +"1.0051,0.9855,0.9855,0.9113,0.8332,0.7004,0.4895",\ +"1.2277,1.2082,1.1809,1.1379,1.0598,0.9230,0.7004"); + } + } +} +pin(B_BIST_WEN) { + direction : input ; + capacitance : 0.00313551 ; + max_transition : "0.5952" ; + related_power_pin : VDD; + related_ground_pin : VSS; + internal_power() { + when : "B_BIST_MEN"; + rise_power("scalar"){ + values (0.0036); + } + fall_power("scalar"){ + values (0.0008); + } + } + internal_power() { + when : "!B_BIST_MEN"; + rise_power("scalar"){ + values (0.0049); + } + fall_power("scalar"){ + values (0.0004); + } + } + timing() { + timing_type : setup_rising; + related_pin : "B_BIST_CLK"; + when : "B_BIST_MEN" + sdf_cond : "B_BIST_MEN" + + rise_constraint("SIG2SRAM_constraint_template") { + index_1("0.0080,0.0288,0.0616,0.1072,0.1920,0.3496,0.5952"); + index_2("0.0080,0.0288,0.0616,0.1072,0.1920,0.3496,0.5952"); + values ("0.3137,0.3332,0.3605,0.4035,0.4816,0.6223,0.8488",\ +"0.2980,0.3176,0.3410,0.3840,0.4660,0.6027,0.8293",\ +"0.2629,0.2824,0.3098,0.3527,0.4348,0.5754,0.7980",\ +"0.2199,0.2395,0.2668,0.3098,0.3918,0.5324,0.7590",\ +"0.1418,0.1613,0.1887,0.2316,0.3137,0.4348,0.6730",\ +"0.0012,0.0207,0.0520,0.0910,0.1730,0.3098,0.5285",\ +"-0.2215,-0.2020,-0.1746,-0.1277,-0.0496,0.0910,0.3098"); + } + + fall_constraint("SIG2SRAM_constraint_template") { + index_1("0.0080,0.0288,0.0616,0.1072,0.1920,0.3496,0.5952"); + index_2("0.0080,0.0288,0.0616,0.1072,0.1920,0.3496,0.5952"); + values ("0.4504,0.4699,0.4973,0.5324,0.6027,0.7355,0.9699",\ +"0.4309,0.4504,0.4777,0.5129,0.5910,0.7160,0.9504",\ +"0.3996,0.4191,0.4465,0.4816,0.5520,0.6848,0.9191",\ +"0.3605,0.3762,0.4035,0.4387,0.5168,0.6418,0.8723",\ +"0.2785,0.2980,0.3215,0.3605,0.4348,0.5637,0.7980",\ +"0.1379,0.1574,0.1809,0.2199,0.2980,0.4309,0.6457",\ +"-0.0809,-0.0613,-0.0340,0.0051,0.0832,0.2160,0.4191"); + } + } + + + timing() { + timing_type : hold_rising; + related_pin : "B_BIST_CLK"; + when : "B_BIST_MEN" + sdf_cond : "B_BIST_MEN" + + rise_constraint("SIG2SRAM_constraint_template") { + index_1("0.0080,0.0288,0.0616,0.1072,0.1920,0.3496,0.5952"); + index_2("0.0080,0.0288,0.0616,0.1072,0.1920,0.3496,0.5952"); + values ("0.3723,0.3527,0.3215,0.2785,0.1965,0.0559,-0.1668",\ +"0.3918,0.3723,0.3449,0.2980,0.2160,0.0754,-0.1473",\ +"0.4152,0.3996,0.3684,0.3254,0.2434,0.1066,-0.1199",\ +"0.4621,0.4465,0.4152,0.3723,0.2863,0.1496,-0.0730",\ +"0.5324,0.5207,0.4895,0.4465,0.3645,0.2199,0.0051",\ +"0.6770,0.6535,0.6301,0.5832,0.5090,0.3605,0.1418",\ +"0.9035,0.8879,0.8566,0.8137,0.7316,0.5871,0.3684"); + } + + fall_constraint("SIG2SRAM_constraint_template") { + index_1("0.0080,0.0288,0.0616,0.1072,0.1920,0.3496,0.5952"); + index_2("0.0080,0.0288,0.0616,0.1072,0.1920,0.3496,0.5952"); + values ("0.3762,0.3566,0.3293,0.2863,0.2043,0.0676,-0.1434",\ +"0.3957,0.3762,0.3488,0.3059,0.2238,0.0871,-0.1199",\ +"0.4230,0.4035,0.3723,0.3332,0.2512,0.1184,-0.0965",\ +"0.4660,0.4465,0.4191,0.3762,0.2941,0.1613,-0.0496",\ +"0.5324,0.5168,0.4973,0.4543,0.3723,0.2316,0.0285",\ +"0.6809,0.6613,0.6340,0.5910,0.5129,0.3645,0.1652",\ +"0.9113,0.8918,0.8605,0.8176,0.7395,0.5988,0.3879"); + } + } + } +pin(B_BIST_REN) { + direction : input ; + capacitance : 0.00381144 ; + max_transition : "0.5952" ; + related_power_pin : VDD; + related_ground_pin : VSS; + internal_power() { + when : "B_BIST_MEN"; + rise_power("scalar"){ + values (0.0040); + } + fall_power("scalar"){ + values (0.0016); + } + } + internal_power() { + when : "!B_BIST_MEN"; + rise_power("scalar"){ + values (0.0040); + } + fall_power("scalar"){ + values (0.0014); + } + } + timing() { + timing_type : setup_rising; + related_pin : "B_BIST_CLK"; + when : "B_BIST_MEN" + sdf_cond : "B_BIST_MEN" + + rise_constraint("SIG2SRAM_constraint_template") { + index_1("0.0080,0.0288,0.0616,0.1072,0.1920,0.3496,0.5952"); + index_2("0.0080,0.0288,0.0616,0.1072,0.1920,0.3496,0.5952"); + values ("-0.0770,-0.0574,-0.0262,0.0168,0.0949,0.2355,0.4582",\ +"-0.0965,-0.0770,-0.0457,-0.0027,0.0754,0.2160,0.4387",\ +"-0.1199,-0.1004,-0.0730,-0.0262,0.0520,0.1887,0.4113",\ +"-0.1590,-0.1434,-0.1160,-0.0730,0.0051,0.1457,0.3645",\ +"-0.2449,-0.2254,-0.1941,-0.1473,-0.0770,0.0676,0.2863",\ +"-0.3816,-0.3699,-0.3387,-0.2801,-0.2215,-0.0770,0.1457",\ +"-0.6121,-0.5926,-0.5613,-0.5145,-0.4363,-0.2996,-0.0730"); + } + + fall_constraint("SIG2SRAM_constraint_template") { + index_1("0.0080,0.0288,0.0616,0.1072,0.1920,0.3496,0.5952"); + index_2("0.0080,0.0288,0.0616,0.1072,0.1920,0.3496,0.5952"); + values ("0.1262,0.1457,0.1691,0.2121,0.2824,0.4191,0.6457",\ +"0.1105,0.1262,0.1496,0.1887,0.2629,0.3996,0.6262",\ +"0.0793,0.0949,0.1223,0.1652,0.2395,0.3684,0.5949",\ +"0.0363,0.0559,0.0793,0.1223,0.2004,0.3410,0.5520",\ +"-0.0457,-0.0262,0.0012,0.0441,0.1301,0.2629,0.4738",\ +"-0.1902,-0.1746,-0.1434,-0.1043,-0.0184,0.1223,0.3332",\ +"-0.4129,-0.3934,-0.3660,-0.3230,-0.2449,-0.1043,0.1105"); + } + } + + + timing() { + timing_type : hold_rising; + related_pin : "B_BIST_CLK"; + when : "B_BIST_MEN" + sdf_cond : "B_BIST_MEN" + + rise_constraint("SIG2SRAM_constraint_template") { + index_1("0.0080,0.0288,0.0616,0.1072,0.1920,0.3496,0.5952"); + index_2("0.0080,0.0288,0.0616,0.1072,0.1920,0.3496,0.5952"); + values ("0.4113,0.3918,0.3645,0.3176,0.2395,0.0988,-0.1238",\ +"0.4309,0.4113,0.3840,0.3371,0.2590,0.1184,-0.1043",\ +"0.4582,0.4387,0.4113,0.3645,0.2824,0.1457,-0.0770",\ +"0.5051,0.4816,0.4543,0.4074,0.3293,0.1887,-0.0340",\ +"0.5715,0.5598,0.5324,0.4895,0.4035,0.2512,0.0441",\ +"0.7043,0.7004,0.6730,0.6262,0.5402,0.3957,0.1809",\ +"0.9387,0.9270,0.8957,0.8527,0.7746,0.6262,0.4074"); + } + + fall_constraint("SIG2SRAM_constraint_template") { + index_1("0.0080,0.0288,0.0616,0.1072,0.1920,0.3496,0.5952"); + index_2("0.0080,0.0288,0.0616,0.1072,0.1920,0.3496,0.5952"); + values ("0.4152,0.3918,0.3645,0.3215,0.2395,0.1027,-0.1082",\ +"0.4309,0.4113,0.3801,0.3410,0.2590,0.1223,-0.0926",\ +"0.4582,0.4387,0.4074,0.3684,0.2863,0.1496,-0.0613",\ +"0.5012,0.4816,0.4504,0.4074,0.3293,0.1887,-0.0145",\ +"0.5715,0.5559,0.5285,0.4816,0.3996,0.2512,0.0598",\ +"0.7160,0.7004,0.6691,0.6262,0.5520,0.4035,0.2004",\ +"0.9387,0.9191,0.8957,0.8488,0.7707,0.6262,0.4113"); + } + } + } +pin(B_BIST_MEN) { + direction : input ; + capacitance : 0.00300347 ; + max_transition : "0.5952" ; + related_power_pin : VDD; + related_ground_pin : VSS; + internal_power() { + rise_power("scalar"){ + values (0.0091); + } + fall_power("scalar"){ + values (0.0001); + } + } + timing() { + timing_type : setup_rising; + related_pin : "B_BIST_CLK"; + + rise_constraint("SIG2SRAM_constraint_template") { + index_1("0.0080,0.0288,0.0616,0.1072,0.1920,0.3496,0.5952"); + index_2("0.0080,0.0288,0.0616,0.1072,0.1920,0.3496,0.5952"); + values ("0.3215,0.3449,0.3684,0.4113,0.4895,0.6301,0.8527",\ +"0.3059,0.3254,0.3527,0.3957,0.4738,0.6145,0.8371",\ +"0.2746,0.2941,0.3215,0.3645,0.4426,0.5871,0.8059",\ +"0.2316,0.2512,0.2785,0.3215,0.3996,0.5402,0.7629",\ +"0.1496,0.1730,0.1965,0.2395,0.3215,0.4660,0.6848",\ +"0.0090,0.0285,0.0598,0.1027,0.1809,0.3176,0.5402",\ +"-0.2098,-0.1902,-0.1668,-0.1199,-0.0418,0.0988,0.3137"); + } + + fall_constraint("SIG2SRAM_constraint_template") { + index_1("0.0080,0.0288,0.0616,0.1072,0.1920,0.3496,0.5952"); + index_2("0.0080,0.0288,0.0616,0.1072,0.1920,0.3496,0.5952"); + values ("0.4582,0.4738,0.5012,0.5363,0.6145,0.7395,0.9738",\ +"0.4387,0.4543,0.4816,0.5207,0.5910,0.7199,0.9582",\ +"0.4035,0.4230,0.4504,0.4855,0.5637,0.6887,0.9230",\ +"0.3645,0.3840,0.4074,0.4465,0.5285,0.6496,0.8840",\ +"0.2824,0.3020,0.3254,0.3645,0.4465,0.5715,0.7980",\ +"0.1418,0.1613,0.1887,0.2238,0.3020,0.4309,0.6496",\ +"-0.0770,-0.0574,-0.0301,0.0090,0.0910,0.2238,0.4191"); + } + } + + + timing() { + timing_type : hold_rising; + related_pin : "B_BIST_CLK"; + + rise_constraint("SIG2SRAM_constraint_template") { + index_1("0.0080,0.0288,0.0616,0.1072,0.1920,0.3496,0.5952"); + index_2("0.0080,0.0288,0.0616,0.1072,0.1920,0.3496,0.5952"); + values ("0.3762,0.3605,0.3293,0.2863,0.2043,0.0637,-0.1629",\ +"0.3996,0.3801,0.3488,0.3020,0.2238,0.0832,-0.1395",\ +"0.4230,0.4074,0.3723,0.3293,0.2473,0.1105,-0.1121",\ +"0.4621,0.4465,0.4152,0.3762,0.2941,0.1535,-0.0691",\ +"0.5441,0.5285,0.4973,0.4465,0.3684,0.2316,0.0090",\ +"0.6848,0.6652,0.6301,0.5910,0.5129,0.3605,0.1496",\ +"0.9074,0.8918,0.8566,0.8215,0.7395,0.5910,0.3723"); + } + + fall_constraint("SIG2SRAM_constraint_template") { + index_1("0.0080,0.0288,0.0616,0.1072,0.1920,0.3496,0.5952"); + index_2("0.0080,0.0288,0.0616,0.1072,0.1920,0.3496,0.5952"); + values ("0.3762,0.3605,0.3332,0.2863,0.2043,0.0715,-0.1395",\ +"0.3996,0.3762,0.3488,0.3059,0.2238,0.0910,-0.1199",\ +"0.4270,0.4035,0.3762,0.3332,0.2512,0.1184,-0.0965",\ +"0.4699,0.4504,0.4191,0.3762,0.2941,0.1613,-0.0496",\ +"0.5441,0.5285,0.4973,0.4543,0.3762,0.2355,0.0324",\ +"0.6770,0.6613,0.6340,0.5949,0.5207,0.3762,0.1652",\ +"0.9074,0.8918,0.8605,0.8176,0.7395,0.6027,0.3918"); + } + } + } +bus(B_BIST_BM) { + bus_type : D_7_0; + direction : input ; + capacitance : 0.00261869 ; + max_transition : "0.5952" ; + pin(B_BIST_BM[7:0]) { + related_power_pin : VDD; + related_ground_pin : VSS; + internal_power() { + when : "B_BIST_MEN"; + rise_power("scalar"){ + values (0.0236); + } + fall_power("scalar"){ + values (0.0076); + } + } + internal_power() { + when : "!B_BIST_MEN"; + rise_power("scalar"){ + values (0.0229); + } + fall_power("scalar"){ + values (0.0073); + } + } + } + timing() { + timing_type : setup_rising; + related_pin : "B_BIST_CLK"; + when : "(B_BIST_WEN & B_BIST_MEN)" + sdf_cond : "B_BIST_RW_ACCESS" + + rise_constraint("SIG2SRAM_constraint_template") { + index_1("0.0080,0.0288,0.0616,0.1072,0.1920,0.3496,0.5952"); + index_2("0.0080,0.0288,0.0616,0.1072,0.1920,0.3496,0.5952"); + values ("-0.5886,-0.5691,-0.5437,-0.5007,-0.4197,-0.2742,-0.0515",\ +"-0.5965,-0.5770,-0.5516,-0.5086,-0.4276,-0.2821,-0.0594",\ +"-0.6057,-0.5861,-0.5607,-0.5178,-0.4367,-0.2912,-0.0686",\ +"-0.6206,-0.6011,-0.5757,-0.5327,-0.4517,-0.3062,-0.0835",\ +"-0.6430,-0.6235,-0.5981,-0.5551,-0.4741,-0.3286,-0.1059",\ +"-0.6866,-0.6671,-0.6417,-0.5987,-0.5177,-0.3722,-0.1495",\ +"-0.7558,-0.7363,-0.7109,-0.6679,-0.5869,-0.4413,-0.2187"); + } + + fall_constraint("SIG2SRAM_constraint_template") { + index_1("0.0080,0.0288,0.0616,0.1072,0.1920,0.3496,0.5952"); + index_2("0.0080,0.0288,0.0616,0.1072,0.1920,0.3496,0.5952"); + values ("-0.5261,-0.5085,-0.4812,-0.4421,-0.3591,-0.2234,-0.0115",\ +"-0.5340,-0.5164,-0.4891,-0.4500,-0.3670,-0.2313,-0.0194",\ +"-0.5432,-0.5256,-0.4982,-0.4592,-0.3762,-0.2404,-0.0285",\ +"-0.5581,-0.5406,-0.5132,-0.4742,-0.3911,-0.2554,-0.0435",\ +"-0.5805,-0.5629,-0.5356,-0.4965,-0.4135,-0.2778,-0.0659",\ +"-0.6241,-0.6065,-0.5792,-0.5401,-0.4571,-0.3214,-0.1095",\ +"-0.6933,-0.6757,-0.6484,-0.6093,-0.5263,-0.3906,-0.1787"); + } + } + + + timing() { + timing_type : hold_rising; + related_pin : "B_BIST_CLK"; + when : "(B_BIST_WEN & B_BIST_MEN)" + sdf_cond : "B_BIST_RW_ACCESS" + + rise_constraint("SIG2SRAM_constraint_template") { + index_1("0.0080,0.0288,0.0616,0.1072,0.1920,0.3496,0.5952"); + index_2("0.0080,0.0288,0.0616,0.1072,0.1920,0.3496,0.5952"); + values ("0.7036,0.6821,0.6577,0.6148,0.5347,0.3882,0.1655",\ +"0.7115,0.6901,0.6656,0.6227,0.5426,0.3961,0.1735",\ +"0.7207,0.6992,0.6748,0.6318,0.5517,0.4053,0.1826",\ +"0.7357,0.7142,0.6898,0.6468,0.5667,0.4202,0.1976",\ +"0.7581,0.7366,0.7121,0.6692,0.5891,0.4426,0.2200",\ +"0.8016,0.7802,0.7558,0.7128,0.6327,0.4862,0.2636",\ +"0.8708,0.8493,0.8249,0.7820,0.7019,0.5554,0.3327"); + } + + fall_constraint("SIG2SRAM_constraint_template") { + index_1("0.0080,0.0288,0.0616,0.1072,0.1920,0.3496,0.5952"); + index_2("0.0080,0.0288,0.0616,0.1072,0.1920,0.3496,0.5952"); + values ("0.6294,0.6118,0.5845,0.5454,0.4624,0.3257,0.1148",\ +"0.6373,0.6197,0.5924,0.5533,0.4703,0.3336,0.1227",\ +"0.6465,0.6289,0.6015,0.5625,0.4795,0.3428,0.1318",\ +"0.6614,0.6439,0.6165,0.5775,0.4944,0.3577,0.1468",\ +"0.6838,0.6663,0.6389,0.5998,0.5168,0.3801,0.1692",\ +"0.7274,0.7098,0.6825,0.6434,0.5604,0.4237,0.2128",\ +"0.7966,0.7790,0.7517,0.7126,0.6296,0.4929,0.2820"); + } + } +} + pin(B_BIST_CLK) { + direction : input; + capacitance : 0.00378957; + max_transition : "0.5952"; + clock : "true" ; + pin_func_type : active_rising ; + + timing () { + timing_type : "min_pulse_width"; + related_pin : "B_BIST_CLK"; + rise_constraint("CLKTRAN_constraint_template") { + index_1("0.008,0.5952"); + values("0.4,0.4"); + } + } + + related_power_pin : VDD; + related_ground_pin : VSS; + + internal_power() { + when : "!B_BIST_MEN & !B_BIST_WEN & !B_BIST_REN"; + rise_power("scalar"){ + values (0); + } + fall_power("scalar"){ + values (0); + } + } + internal_power() { + when : "!B_BIST_MEN & B_BIST_WEN & !B_BIST_REN"; + rise_power("scalar"){ + values (0.4257); + } + fall_power("scalar"){ + values (0); + } + } + internal_power() { + when : "B_BIST_MEN & B_BIST_WEN & !B_BIST_REN"; + rise_power("scalar"){ + values (9.0428); + } + fall_power("scalar"){ + values (0); + } + } + internal_power() { + when : "B_BIST_MEN & B_BIST_WEN & B_BIST_REN"; + rise_power("scalar"){ + values (9.4016); + } + fall_power("scalar"){ + values (0); + } + } + internal_power() { + when : "B_BIST_MEN & !B_BIST_WEN & B_BIST_REN"; + rise_power("scalar"){ + values (6.8079); + } + fall_power("scalar"){ + values (0); + } + } + internal_power() { + when : "!B_BIST_MEN & !B_BIST_WEN & B_BIST_REN"; + rise_power("scalar"){ + values (0.2646); + } + fall_power("scalar"){ + values (0); + } + } + internal_power() { + when : "!B_BIST_MEN & B_BIST_WEN & B_BIST_REN"; + rise_power("scalar"){ + values (0.4709); + } + fall_power("scalar"){ + values (0); + } + } + internal_power() { + when : "B_BIST_MEN & !B_BIST_WEN & !B_BIST_REN"; + rise_power("scalar"){ + values (0); + } + fall_power("scalar"){ + values (0); + } + } + } + bus(B_BIST_DIN) { + bus_type : D_7_0; + direction : input ; + capacitance : 0.00416317 ; + memory_write() { + address : B_BIST_ADDR ; + clocked_on : B_BIST_CLK; + } + + max_transition : "0.5952" ; + pin(B_BIST_DIN[7:0]) { + related_power_pin : VDD; + related_ground_pin : VSS; + internal_power() { + when : "B_BIST_MEN"; + rise_power("scalar"){ + values (0.0236); + } + fall_power("scalar"){ + values (0.0076); + } + } + internal_power() { + when : "!B_BIST_MEN"; + rise_power("scalar"){ + values (0.0229); + } + fall_power("scalar"){ + values (0.0073); + } + } + } + timing() { + timing_type : setup_rising; + related_pin : "B_BIST_CLK"; + when : "(B_BIST_WEN & B_BIST_MEN)"; + sdf_cond : "B_BIST_W_ACCESS"; + + rise_constraint("SIG2SRAM_constraint_template") { + index_1("0.0080,0.0288,0.0616,0.1072,0.1920,0.3496,0.5952"); + index_2("0.0080,0.0288,0.0616,0.1072,0.1920,0.3496,0.5952"); + values ("-0.5886,-0.5691,-0.5437,-0.5007,-0.4197,-0.2742,-0.0515",\ +"-0.5965,-0.5770,-0.5516,-0.5086,-0.4276,-0.2821,-0.0594",\ +"-0.6057,-0.5861,-0.5607,-0.5178,-0.4367,-0.2912,-0.0686",\ +"-0.6206,-0.6011,-0.5757,-0.5327,-0.4517,-0.3062,-0.0835",\ +"-0.6430,-0.6235,-0.5981,-0.5551,-0.4741,-0.3286,-0.1059",\ +"-0.6866,-0.6671,-0.6417,-0.5987,-0.5177,-0.3722,-0.1495",\ +"-0.7558,-0.7363,-0.7109,-0.6679,-0.5869,-0.4413,-0.2187"); + } + + fall_constraint("SIG2SRAM_constraint_template") { + index_1("0.0080,0.0288,0.0616,0.1072,0.1920,0.3496,0.5952"); + index_2("0.0080,0.0288,0.0616,0.1072,0.1920,0.3496,0.5952"); + values ("-0.5261,-0.5085,-0.4812,-0.4421,-0.3591,-0.2234,-0.0115",\ +"-0.5340,-0.5164,-0.4891,-0.4500,-0.3670,-0.2313,-0.0194",\ +"-0.5432,-0.5256,-0.4982,-0.4592,-0.3762,-0.2404,-0.0285",\ +"-0.5581,-0.5406,-0.5132,-0.4742,-0.3911,-0.2554,-0.0435",\ +"-0.5805,-0.5629,-0.5356,-0.4965,-0.4135,-0.2778,-0.0659",\ +"-0.6241,-0.6065,-0.5792,-0.5401,-0.4571,-0.3214,-0.1095",\ +"-0.6933,-0.6757,-0.6484,-0.6093,-0.5263,-0.3906,-0.1787"); + } + } + + timing() { + timing_type : hold_rising; + related_pin : "B_BIST_CLK"; + when : "(B_BIST_WEN & B_BIST_MEN)"; + sdf_cond : "B_BIST_W_ACCESS"; + + rise_constraint("SIG2SRAM_constraint_template") { + index_1("0.0080,0.0288,0.0616,0.1072,0.1920,0.3496,0.5952"); + index_2("0.0080,0.0288,0.0616,0.1072,0.1920,0.3496,0.5952"); + values ("0.7036,0.6821,0.6577,0.6148,0.5347,0.3882,0.1655",\ +"0.7115,0.6901,0.6656,0.6227,0.5426,0.3961,0.1735",\ +"0.7207,0.6992,0.6748,0.6318,0.5517,0.4053,0.1826",\ +"0.7357,0.7142,0.6898,0.6468,0.5667,0.4202,0.1976",\ +"0.7581,0.7366,0.7121,0.6692,0.5891,0.4426,0.2200",\ +"0.8016,0.7802,0.7558,0.7128,0.6327,0.4862,0.2636",\ +"0.8708,0.8493,0.8249,0.7820,0.7019,0.5554,0.3327"); + } + + fall_constraint("SIG2SRAM_constraint_template") { + index_1("0.0080,0.0288,0.0616,0.1072,0.1920,0.3496,0.5952"); + index_2("0.0080,0.0288,0.0616,0.1072,0.1920,0.3496,0.5952"); + values ("0.6294,0.6118,0.5845,0.5454,0.4624,0.3257,0.1148",\ +"0.6373,0.6197,0.5924,0.5533,0.4703,0.3336,0.1227",\ +"0.6465,0.6289,0.6015,0.5625,0.4795,0.3428,0.1318",\ +"0.6614,0.6439,0.6165,0.5775,0.4944,0.3577,0.1468",\ +"0.6838,0.6663,0.6389,0.5998,0.5168,0.3801,0.1692",\ +"0.7274,0.7098,0.6825,0.6434,0.5604,0.4237,0.2128",\ +"0.7966,0.7790,0.7517,0.7126,0.6296,0.4929,0.2820"); + } + } + } + +bus(B_DOUT) { + + bus_type : D_7_0; + direction : output ; + capacitance : 0 ; + max_capacitance : 0.064 ; + memory_read() { + address : B_ADDR ; + } + pin(B_DOUT[7:0]) { + related_power_pin : VDD; + related_ground_pin : VSS; + internal_power() { + rise_power("scalar") { + values (0); + } + fall_power("scalar") { + values (0); + } + } + } + timing() { + related_pin : "B_CLK"; + timing_type : rising_edge ; + timing_sense : non_unate ; + + cell_rise(SIG2SRAM_delay_template) { + index_1("0.0080,0.0288,0.0616,0.1072,0.1920,0.3496,0.5952"); + index_2("0.0008,0.0014,0.0051,0.0100,0.0339,0.0640"); + values ("4.9845,4.9879,5.0000,5.0140,5.0665,5.1244",\ +"4.9984,5.0018,5.0139,5.0279,5.0805,5.1383",\ +"5.0083,5.0116,5.0238,5.0377,5.0903,5.1481",\ +"5.0215,5.0249,5.0371,5.0510,5.1036,5.1614",\ +"5.0448,5.0482,5.0604,5.0743,5.1269,5.1847",\ +"5.0896,5.0929,5.1051,5.1191,5.1716,5.2295",\ +"5.1568,5.1602,5.1724,5.1863,5.2389,5.2967"); + } + cell_fall(SIG2SRAM_delay_template) { + index_1("0.0080,0.0288,0.0616,0.1072,0.1920,0.3496,0.5952"); + index_2("0.0008,0.0014,0.0051,0.0100,0.0339,0.0640"); + values ("4.8748,4.8769,4.8870,4.8987,4.9420,4.9858",\ +"4.8887,4.8909,4.9009,4.9126,4.9559,4.9998",\ +"4.8985,4.9007,4.9107,4.9224,4.9658,5.0096",\ +"4.9118,4.9140,4.9240,4.9357,4.9791,5.0229",\ +"4.9351,4.9373,4.9473,4.9590,5.0023,5.0462",\ +"4.9798,4.9820,4.9921,5.0037,5.0471,5.0909",\ +"5.0471,5.0493,5.0593,5.0710,5.1143,5.1582"); + } + + rise_transition(SRAM_load_template) { + index_1("0.0008,0.0014,0.0051,0.0100,0.0339,0.0640"); + values ("0.0560,0.0583,0.0696,0.0816,0.1519,0.2335"); + } + fall_transition(SRAM_load_template) { + index_1("0.0008,0.0014,0.0051,0.0100,0.0339,0.0640"); + values ("0.0428,0.0445,0.0538,0.0658,0.1181,0.1751"); + } + } +} +cell_leakage_power : 238.2893; +} +} diff --git a/flow/platforms/ihp-sg13g2/lib/RM_IHPSG13_2P_256x8_c2_bm_bist_typ_1p20V_25C.lib b/flow/platforms/ihp-sg13g2/lib/RM_IHPSG13_2P_256x8_c2_bm_bist_typ_1p20V_25C.lib new file mode 100644 index 0000000000..7089f55bde --- /dev/null +++ b/flow/platforms/ihp-sg13g2/lib/RM_IHPSG13_2P_256x8_c2_bm_bist_typ_1p20V_25C.lib @@ -0,0 +1,2874 @@ +/* ------------------------------------------------------*/ +/**/ +/* Copyright 2025 IHP PDK Authors*/ +/**/ +/* Licensed under the Apache License, Version 2.0 (the "License");*/ +/* you may not use this file except in compliance with the License.*/ +/* You may obtain a copy of the License at*/ +/* */ +/* https://www.apache.org/licenses/LICENSE-2.0*/ +/* */ +/* Unless required by applicable law or agreed to in writing, software*/ +/* distributed under the License is distributed on an "AS IS" BASIS,*/ +/* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.*/ +/* See the License for the specific language governing permissions and*/ +/* limitations under the License.*/ +/* */ +/* Generated on Wed Aug 27 13:36:31 2025 */ +/* */ +/* ------------------------------------------------------ */ +library(RM_IHPSG13_2P_256x8_c2_bm_bist_typ_1p20V_25C) { + technology (cmos) ; + delay_model : table_lookup ; + define ("add_pg_pin_to_lib", "library", "boolean"); + add_pg_pin_to_lib : true; + voltage_map ( VDD, 1.20); + voltage_map ( VDDARRAY, 1.20); + voltage_map ( VSS, 0.000000 ); + + date : "Wed Aug 27 13:36:28 2025" ; + comment : "IHP Microelectronics GmbH, 2023" ; + revision : 1.0.0 ; + simulation : true ; + nom_process : 1 ; + nom_temperature : 25 ; + nom_voltage : 1.20 ; + + operating_conditions("typ_1p20V_25C"){ + process : 1 ; + temperature : 25 ; + voltage : 1.20 ; + tree_type : "balanced_tree" ; + } + + default_operating_conditions : typ_1p20V_25C ; + default_max_transition : 1.0 ; + default_fanout_load : 1.0 ; + default_inout_pin_cap : 0.0 ; + default_input_pin_cap : 0.0 ; + default_output_pin_cap : 0.0 ; + default_cell_leakage_power : 0.0 ; + default_leakage_power_density : 0.0 ; + + slew_lower_threshold_pct_rise : 30 ; + slew_upper_threshold_pct_rise : 70 ; + input_threshold_pct_fall : 50 ; + output_threshold_pct_fall : 50 ; + input_threshold_pct_rise : 50 ; + output_threshold_pct_rise : 50 ; + slew_lower_threshold_pct_fall : 30 ; + slew_upper_threshold_pct_fall : 70 ; + slew_derate_from_library : 0.5; + k_volt_cell_leakage_power : 0.0 ; + k_temp_cell_leakage_power : 0.0 ; + k_process_cell_leakage_power : 0.0 ; + k_volt_internal_power : 0.0 ; + k_temp_internal_power : 0.0 ; + k_process_internal_power : 0.0 ; + + capacitive_load_unit (1,pf) ; + voltage_unit : "1V" ; + current_unit : "1uA" ; + time_unit : "1ns" ; + leakage_power_unit : "1nW" ; + pulling_resistance_unit : "1kohm"; + /* + ------------------------------------------------------------------------------------------ + implicit units overview: + cell_area unit : "um" + internal_power unit : "1e-12 * J/toggle = 1 * uW/MHz" + (capacitive_load_unit * voltage_unit^2) per toggle event + ------------------------------------------------------------------------------------------ + */ + library_features(report_delay_calculation); + define_cell_area (pad_drivers,pad_driver_sites) ; + + lu_table_template(CLKTRAN_constraint_template) { + variable_1 : constrained_pin_transition; + index_1 ( "0.010, 0.050, 0.200, 0.400, 1.000" ); + } + lu_table_template(SRAM_load_template) { + variable_1 : total_output_net_capacitance; + index_1 ( "0.0008,0.0014,0.0051,0.0100,0.0339,0.0640" ); + } + lu_table_template(SIG2SRAM_constraint_template) { + variable_1 : related_pin_transition; + variable_2 : constrained_pin_transition; + index_1 ( "0.0056,0.0232,0.0400,0.0728,0.1280,0.2440,0.4760" ); + index_2 ( "0.0056,0.0232,0.0400,0.0728,0.1280,0.2440,0.4760" ); + } + + lu_table_template(SIG2SRAM_delay_template) { + variable_1 : input_net_transition; + variable_2 : total_output_net_capacitance; + index_1 ( "0.0056,0.0232,0.0400,0.0728,0.1280,0.2440,0.4760" ); + index_2 ( "0.0008,0.0014,0.0051,0.0100,0.0339,0.0640" ); + } + + type (D_7_0) { + base_type : array; + data_type : bit; + bit_width : 8; + bit_from : 7; + bit_to : 0; + downto : true; + } + + type (A_7_0) { + base_type : array; + data_type : bit; + bit_width : 8; + bit_from : 7; + bit_to : 0; + downto : true; + } + +cell(RM_IHPSG13_2P_256x8_c2_bm_bist) { +pg_pin (VDD) { + pg_type : primary_power; + voltage_name : VDD; +} +pg_pin (VDDARRAY) { + pg_type : primary_power; + voltage_name : VDDARRAY; +} +pg_pin (VSS) { + pg_type : primary_ground; + voltage_name : VSS; +} + +memory() { + type : ram; + address_width : 8; + word_width : 8; +} + +interface_timing : false; +bus_naming_style : "%s[%d]" ; +area : 38147.5147 ; + + pin(A_DLY) { + direction : input ; + capacitance : 0.00401111 ; + max_transition : "1" ; + related_power_pin : VDD; + related_ground_pin : VSS; + internal_power() { + rise_power("scalar") { + values (0); + } + fall_power("scalar") { + values (0); + } + } + } + +bus(A_ADDR) { + bus_type : A_7_0; + direction : input ; + capacitance : 0.0121077 ; + pin(A_ADDR[0]) { + capacitance : 0.00568653 ; + } + pin(A_ADDR[1]) { + capacitance : 0.00767263 ; + } + pin(A_ADDR[2]) { + capacitance : 0.0105079 ; + } + pin(A_ADDR[3]) { + capacitance : 0.0068178 ; + } + pin(A_ADDR[4]) { + capacitance : 0.00624497 ; + } + pin(A_ADDR[5]) { + capacitance : 0.0105871 ; + } + pin(A_ADDR[6]) { + capacitance : 0.0130817 ; + } + max_transition : "0.476" ; + pin(A_ADDR[7:0]) { + related_power_pin : VDD; + related_ground_pin : VSS; + internal_power() { + when : "A_MEN"; + rise_power("scalar"){ + values (0.0113); + } + fall_power("scalar"){ + values (0.0053); + } + } + internal_power() { + when : "!A_MEN"; + rise_power("scalar"){ + values (0.0194); + } + fall_power("scalar"){ + values (0.0005); + } + } + } + timing() { + timing_type : setup_rising; + related_pin : "A_CLK"; + when : "((A_WEN | A_REN)& A_MEN)" + sdf_cond : "A_RW_ACCESS" + + rise_constraint("SIG2SRAM_constraint_template") { + index_1("0.0056,0.0232,0.0400,0.0728,0.1280,0.2440,0.4760"); + index_2("0.0056,0.0232,0.0400,0.0728,0.1280,0.2440,0.4760"); + values ("-0.4168,-0.3973,-0.3855,-0.3543,-0.3074,-0.2020,-0.0027",\ +"-0.4324,-0.4129,-0.4012,-0.3699,-0.3191,-0.2176,-0.0184",\ +"-0.4441,-0.4285,-0.4129,-0.3816,-0.3309,-0.2293,-0.0301",\ +"-0.4793,-0.4598,-0.4441,-0.4129,-0.3660,-0.2645,-0.0652",\ +"-0.5223,-0.5066,-0.4910,-0.4598,-0.4129,-0.3074,-0.1121",\ +"-0.6199,-0.6082,-0.5926,-0.5613,-0.5145,-0.4129,-0.2137",\ +"-0.8191,-0.8074,-0.7840,-0.7566,-0.7098,-0.6082,-0.4051"); + } + + fall_constraint("SIG2SRAM_constraint_template") { + index_1("0.0056,0.0232,0.0400,0.0728,0.1280,0.2440,0.4760"); + index_2("0.0056,0.0232,0.0400,0.0728,0.1280,0.2440,0.4760"); + values ("-0.3309,-0.3113,-0.2996,-0.2684,-0.2176,-0.1238,0.0637",\ +"-0.3465,-0.3309,-0.3152,-0.2840,-0.2332,-0.1395,0.0480",\ +"-0.3582,-0.3426,-0.3270,-0.2996,-0.2488,-0.1512,0.0324",\ +"-0.3895,-0.3738,-0.3582,-0.3309,-0.2801,-0.1863,0.0051",\ +"-0.4363,-0.4207,-0.4051,-0.3777,-0.3230,-0.2293,-0.0379",\ +"-0.5379,-0.5223,-0.5066,-0.4793,-0.4285,-0.3309,-0.1434",\ +"-0.7332,-0.7176,-0.7020,-0.6746,-0.6238,-0.5262,-0.3387"); + } + } + + + timing() { + timing_type : hold_rising; + related_pin : "A_CLK"; + when : "((A_WEN | A_REN)& A_MEN)" + sdf_cond : "A_RW_ACCESS" + + rise_constraint("SIG2SRAM_constraint_template") { + index_1("0.0056,0.0232,0.0400,0.0728,0.1280,0.2440,0.4760"); + index_2("0.0056,0.0232,0.0400,0.0728,0.1280,0.2440,0.4760"); + values ("0.5246,0.5051,0.4895,0.4582,0.4113,0.3059,0.1066",\ +"0.5402,0.5207,0.5051,0.4777,0.4270,0.3215,0.1223",\ +"0.5520,0.5324,0.5168,0.4895,0.4387,0.3371,0.1340",\ +"0.5832,0.5676,0.5520,0.5207,0.4738,0.3684,0.1691",\ +"0.6301,0.6105,0.5949,0.5676,0.5168,0.4113,0.2160",\ +"0.7316,0.7121,0.7004,0.6691,0.6223,0.5168,0.3176",\ +"0.9270,0.9230,0.8957,0.8645,0.8137,0.7121,0.5168"); + } + + fall_constraint("SIG2SRAM_constraint_template") { + index_1("0.0056,0.0232,0.0400,0.0728,0.1280,0.2440,0.4760"); + index_2("0.0056,0.0232,0.0400,0.0728,0.1280,0.2440,0.4760"); + values ("0.4309,0.4152,0.4035,0.3684,0.3215,0.2277,0.0363",\ +"0.4465,0.4309,0.4152,0.3879,0.3371,0.2395,0.0559",\ +"0.4582,0.4426,0.4309,0.3996,0.3488,0.2551,0.0715",\ +"0.4934,0.4777,0.4621,0.4348,0.3840,0.2863,0.0988",\ +"0.5363,0.5207,0.5051,0.4777,0.4270,0.3332,0.1418",\ +"0.6379,0.6262,0.6105,0.5793,0.5324,0.4348,0.2434",\ +"0.8332,0.8215,0.8059,0.7707,0.7238,0.6301,0.4387"); + } + } +} +pin(A_WEN) { + direction : input ; + capacitance : 0.00324098 ; + max_transition : "0.476" ; + related_power_pin : VDD; + related_ground_pin : VSS; + internal_power() { + when : "A_MEN"; + rise_power("scalar"){ + values (0.0046); + } + fall_power("scalar"){ + values (0.0037); + } + } + internal_power() { + when : "!A_MEN"; + rise_power("scalar"){ + values (0.0041); + } + fall_power("scalar"){ + values (0.0037); + } + } + timing() { + timing_type : setup_rising; + related_pin : "A_CLK"; + when : "A_MEN" + sdf_cond : "A_MEN" + + rise_constraint("SIG2SRAM_constraint_template") { + index_1("0.0056,0.0232,0.0400,0.0728,0.1280,0.2440,0.4760"); + index_2("0.0056,0.0232,0.0400,0.0728,0.1280,0.2440,0.4760"); + values ("0.2043,0.2199,0.2316,0.2629,0.3059,0.4113,0.6066",\ +"0.1887,0.2043,0.2160,0.2473,0.2941,0.3957,0.5949",\ +"0.1691,0.1848,0.2004,0.2316,0.2785,0.3801,0.5754",\ +"0.1379,0.1574,0.1691,0.2004,0.2473,0.3527,0.5480",\ +"0.0910,0.1066,0.1223,0.1535,0.2004,0.2980,0.4973",\ +"-0.0105,0.0051,0.0207,0.0520,0.0949,0.2004,0.3957",\ +"-0.2059,-0.1902,-0.1746,-0.1473,-0.1004,0.0051,0.2004"); + } + + fall_constraint("SIG2SRAM_constraint_template") { + index_1("0.0056,0.0232,0.0400,0.0728,0.1280,0.2440,0.4760"); + index_2("0.0056,0.0232,0.0400,0.0728,0.1280,0.2440,0.4760"); + values ("0.2941,0.3098,0.3215,0.3488,0.4035,0.4973,0.6887",\ +"0.2785,0.2941,0.3059,0.3332,0.3840,0.4816,0.6691",\ +"0.2629,0.2785,0.2902,0.3176,0.3684,0.4660,0.6535",\ +"0.2316,0.2473,0.2590,0.2863,0.3410,0.4348,0.6262",\ +"0.1848,0.2004,0.2121,0.2395,0.2902,0.3879,0.5754",\ +"0.0832,0.0988,0.1105,0.1379,0.1809,0.2746,0.4699",\ +"-0.1121,-0.0965,-0.0848,-0.0535,-0.0066,0.0910,0.2824"); + } + } + + + timing() { + timing_type : hold_rising; + related_pin : "A_CLK"; + when : "A_MEN" + sdf_cond : "A_MEN" + + rise_constraint("SIG2SRAM_constraint_template") { + index_1("0.0056,0.0232,0.0400,0.0728,0.1280,0.2440,0.4760"); + index_2("0.0056,0.0232,0.0400,0.0728,0.1280,0.2440,0.4760"); + values ("0.2473,0.2316,0.2160,0.1887,0.1379,0.0363,-0.1629",\ +"0.2629,0.2473,0.2316,0.2043,0.1535,0.0520,-0.1473",\ +"0.2785,0.2590,0.2434,0.2160,0.1652,0.0676,-0.1355",\ +"0.3098,0.2941,0.2785,0.2473,0.1965,0.0910,-0.1043",\ +"0.3527,0.3371,0.3215,0.2941,0.2434,0.1418,-0.0574",\ +"0.4582,0.4426,0.4270,0.3957,0.3488,0.2434,0.0480",\ +"0.6535,0.6379,0.6184,0.5910,0.5402,0.4426,0.2434"); + } + + fall_constraint("SIG2SRAM_constraint_template") { + index_1("0.0056,0.0232,0.0400,0.0728,0.1280,0.2440,0.4760"); + index_2("0.0056,0.0232,0.0400,0.0728,0.1280,0.2440,0.4760"); + values ("0.2395,0.2238,0.2121,0.1809,0.1301,0.0324,-0.1551",\ +"0.2551,0.2395,0.2277,0.1965,0.1457,0.0480,-0.1395",\ +"0.2668,0.2551,0.2395,0.2082,0.1574,0.0637,-0.1277",\ +"0.3020,0.2863,0.2707,0.2395,0.1887,0.0910,-0.0965",\ +"0.3449,0.3293,0.3176,0.2863,0.2355,0.1379,-0.0496",\ +"0.4504,0.4348,0.4191,0.3879,0.3371,0.2395,0.0559",\ +"0.6457,0.6301,0.6145,0.5871,0.5324,0.4309,0.2512"); + } + } + } +pin(A_REN) { + direction : input ; + capacitance : 0.00381634 ; + max_transition : "0.476" ; + related_power_pin : VDD; + related_ground_pin : VSS; + internal_power() { + when : "A_MEN"; + rise_power("scalar"){ + values (0.0060); + } + fall_power("scalar"){ + values (0.0020); + } + } + internal_power() { + when : "!A_MEN"; + rise_power("scalar"){ + values (0.0061); + } + fall_power("scalar"){ + values (0.0023); + } + } + timing() { + timing_type : setup_rising; + related_pin : "A_CLK"; + when : "A_MEN" + sdf_cond : "A_MEN" + + rise_constraint("SIG2SRAM_constraint_template") { + index_1("0.0056,0.0232,0.0400,0.0728,0.1280,0.2440,0.4760"); + index_2("0.0056,0.0232,0.0400,0.0728,0.1280,0.2440,0.4760"); + values ("-0.0301,-0.0145,0.0012,0.0324,0.0793,0.1809,0.3762",\ +"-0.0457,-0.0301,-0.0145,0.0168,0.0637,0.1613,0.3605",\ +"-0.0574,-0.0418,-0.0262,0.0051,0.0520,0.1496,0.3449",\ +"-0.0926,-0.0730,-0.0574,-0.0262,0.0207,0.1184,0.3137",\ +"-0.1395,-0.1238,-0.1082,-0.0770,-0.0301,0.0715,0.2707",\ +"-0.2410,-0.2254,-0.2098,-0.1746,-0.1355,-0.0340,0.1652",\ +"-0.4402,-0.4207,-0.4051,-0.3738,-0.3270,-0.2293,-0.0340"); + } + + fall_constraint("SIG2SRAM_constraint_template") { + index_1("0.0056,0.0232,0.0400,0.0728,0.1280,0.2440,0.4760"); + index_2("0.0056,0.0232,0.0400,0.0728,0.1280,0.2440,0.4760"); + values ("0.0988,0.1145,0.1262,0.1535,0.2043,0.3020,0.4855",\ +"0.0832,0.0988,0.1105,0.1418,0.1848,0.2824,0.4738",\ +"0.0676,0.0832,0.0949,0.1262,0.1730,0.2668,0.4621",\ +"0.0402,0.0559,0.0676,0.0988,0.1457,0.2434,0.4191",\ +"-0.0105,0.0012,0.0168,0.0480,0.0988,0.1965,0.3840",\ +"-0.1160,-0.0965,-0.0848,-0.0535,-0.0066,0.0988,0.2824",\ +"-0.3113,-0.2957,-0.2801,-0.2527,-0.2059,-0.1043,0.0832"); + } + } + + + timing() { + timing_type : hold_rising; + related_pin : "A_CLK"; + when : "A_MEN" + sdf_cond : "A_MEN" + + rise_constraint("SIG2SRAM_constraint_template") { + index_1("0.0056,0.0232,0.0400,0.0728,0.1280,0.2440,0.4760"); + index_2("0.0056,0.0232,0.0400,0.0728,0.1280,0.2440,0.4760"); + values ("0.2707,0.2551,0.2395,0.2121,0.1613,0.0598,-0.1395",\ +"0.2863,0.2707,0.2551,0.2238,0.1730,0.0715,-0.1238",\ +"0.2980,0.2824,0.2668,0.2395,0.1887,0.0871,-0.1121",\ +"0.3332,0.3176,0.3020,0.2707,0.2199,0.1184,-0.0809",\ +"0.3762,0.3605,0.3449,0.3176,0.2668,0.1613,-0.0340",\ +"0.4816,0.4621,0.4504,0.4191,0.3723,0.2629,0.0715",\ +"0.6770,0.6613,0.6418,0.6184,0.5637,0.4699,0.2629"); + } + + fall_constraint("SIG2SRAM_constraint_template") { + index_1("0.0056,0.0232,0.0400,0.0728,0.1280,0.2440,0.4760"); + index_2("0.0056,0.0232,0.0400,0.0728,0.1280,0.2440,0.4760"); + values ("0.2590,0.2434,0.2316,0.2004,0.1457,0.0520,-0.1355",\ +"0.2746,0.2590,0.2434,0.2160,0.1613,0.0676,-0.1199",\ +"0.2863,0.2707,0.2590,0.2277,0.1730,0.0832,-0.1082",\ +"0.3215,0.3059,0.2902,0.2590,0.2082,0.1105,-0.0770",\ +"0.3645,0.3488,0.3332,0.3059,0.2551,0.1535,-0.0340",\ +"0.4699,0.4543,0.4387,0.4074,0.3605,0.2551,0.0715",\ +"0.6652,0.6496,0.6340,0.6027,0.5520,0.4621,0.2707"); + } + } + } +pin(A_MEN) { + direction : input ; + capacitance : 0.00309605 ; + max_transition : "0.476" ; + related_power_pin : VDD; + related_ground_pin : VSS; + internal_power() { + rise_power("scalar"){ + values (0.0236); + } + fall_power("scalar"){ + values (0.0052); + } + } + timing() { + timing_type : setup_rising; + related_pin : "A_CLK"; + + rise_constraint("SIG2SRAM_constraint_template") { + index_1("0.0056,0.0232,0.0400,0.0728,0.1280,0.2440,0.4760"); + index_2("0.0056,0.0232,0.0400,0.0728,0.1280,0.2440,0.4760"); + values ("0.2043,0.2199,0.2316,0.2668,0.3098,0.4152,0.6066",\ +"0.1887,0.2043,0.2199,0.2512,0.2941,0.3996,0.5949",\ +"0.1730,0.1887,0.2043,0.2355,0.2824,0.3840,0.5793",\ +"0.1418,0.1574,0.1730,0.2043,0.2512,0.3566,0.5480",\ +"0.0949,0.1105,0.1262,0.1574,0.2043,0.3020,0.5051",\ +"-0.0066,0.0090,0.0246,0.0520,0.0988,0.2043,0.3996",\ +"-0.2020,-0.1863,-0.1746,-0.1434,-0.0965,0.0090,0.2082"); + } + + fall_constraint("SIG2SRAM_constraint_template") { + index_1("0.0056,0.0232,0.0400,0.0728,0.1280,0.2440,0.4760"); + index_2("0.0056,0.0232,0.0400,0.0728,0.1280,0.2440,0.4760"); + values ("0.2980,0.3137,0.3254,0.3527,0.4035,0.5012,0.6887",\ +"0.2824,0.2980,0.3098,0.3371,0.3879,0.4855,0.6730",\ +"0.2668,0.2824,0.2941,0.3215,0.3723,0.4699,0.6574",\ +"0.2355,0.2473,0.2629,0.2902,0.3410,0.4387,0.6262",\ +"0.1887,0.2004,0.2160,0.2395,0.2941,0.3918,0.5793",\ +"0.0871,0.1027,0.1145,0.1418,0.1848,0.2746,0.4816",\ +"-0.1082,-0.0965,-0.0809,-0.0496,-0.0027,0.0949,0.2863"); + } + } + + + timing() { + timing_type : hold_rising; + related_pin : "A_CLK"; + + rise_constraint("SIG2SRAM_constraint_template") { + index_1("0.0056,0.0232,0.0400,0.0728,0.1280,0.2440,0.4760"); + index_2("0.0056,0.0232,0.0400,0.0728,0.1280,0.2440,0.4760"); + values ("0.2512,0.2355,0.2199,0.1926,0.1418,0.0402,-0.1590",\ +"0.2668,0.2512,0.2355,0.2082,0.1574,0.0559,-0.1434",\ +"0.2824,0.2629,0.2512,0.2199,0.1691,0.0715,-0.1316",\ +"0.3137,0.2980,0.2824,0.2512,0.2004,0.0988,-0.0965",\ +"0.3566,0.3410,0.3254,0.2980,0.2473,0.1418,-0.0535",\ +"0.4621,0.4426,0.4309,0.3996,0.3527,0.2473,0.0520",\ +"0.6574,0.6418,0.6262,0.5949,0.5441,0.4465,0.2473"); + } + + fall_constraint("SIG2SRAM_constraint_template") { + index_1("0.0056,0.0232,0.0400,0.0728,0.1280,0.2440,0.4760"); + index_2("0.0056,0.0232,0.0400,0.0728,0.1280,0.2440,0.4760"); + values ("0.2395,0.2238,0.2121,0.1809,0.1301,0.0324,-0.1551",\ +"0.2551,0.2434,0.2277,0.1965,0.1457,0.0480,-0.1395",\ +"0.2707,0.2551,0.2395,0.2082,0.1574,0.0637,-0.1277",\ +"0.3020,0.2863,0.2707,0.2434,0.1926,0.0910,-0.0965",\ +"0.3449,0.3332,0.3176,0.2863,0.2355,0.1379,-0.0496",\ +"0.4504,0.4348,0.4230,0.3918,0.3410,0.2434,0.0559",\ +"0.6457,0.6301,0.6145,0.5910,0.5324,0.4387,0.2512"); + } + } + } +bus(A_BM) { + bus_type : D_7_0; + direction : input ; + capacitance : 0.00372627 ; + max_transition : "0.476" ; + pin(A_BM[7:0]) { + related_power_pin : VDD; + related_ground_pin : VSS; + internal_power() { + when : "A_MEN"; + rise_power("scalar"){ + values (0.0299); + } + fall_power("scalar"){ + values (0.0123); + } + } + internal_power() { + when : "!A_MEN"; + rise_power("scalar"){ + values (0.0316); + } + fall_power("scalar"){ + values (0.0122); + } + } + } + timing() { + timing_type : setup_rising; + related_pin : "A_CLK"; + when : "(A_WEN & A_MEN)" + sdf_cond : "A_RW_ACCESS" + + rise_constraint("SIG2SRAM_constraint_template") { + index_1("0.0056,0.0232,0.0400,0.0728,0.1280,0.2440,0.4760"); + index_2("0.0056,0.0232,0.0400,0.0728,0.1280,0.2440,0.4760"); + values ("-0.2885,-0.2729,-0.2602,-0.2270,-0.1782,-0.0795,0.1138",\ +"-0.2935,-0.2779,-0.2652,-0.2320,-0.1832,-0.0845,0.1088",\ +"-0.2980,-0.2824,-0.2697,-0.2365,-0.1876,-0.0890,0.1043",\ +"-0.3071,-0.2915,-0.2788,-0.2456,-0.1968,-0.0981,0.0952",\ +"-0.3143,-0.2987,-0.2860,-0.2528,-0.2040,-0.1053,0.0880",\ +"-0.3440,-0.3283,-0.3157,-0.2825,-0.2336,-0.1350,0.0584",\ +"-0.4020,-0.3864,-0.3737,-0.3405,-0.2917,-0.1931,0.0003"); + } + + fall_constraint("SIG2SRAM_constraint_template") { + index_1("0.0056,0.0232,0.0400,0.0728,0.1280,0.2440,0.4760"); + index_2("0.0056,0.0232,0.0400,0.0728,0.1280,0.2440,0.4760"); + values ("-0.2543,-0.2397,-0.2260,-0.1977,-0.1479,-0.0493,0.1304",\ +"-0.2593,-0.2447,-0.2310,-0.2027,-0.1529,-0.0543,0.1254",\ +"-0.2638,-0.2492,-0.2355,-0.2072,-0.1574,-0.0587,0.1209",\ +"-0.2729,-0.2583,-0.2446,-0.2163,-0.1665,-0.0679,0.1118",\ +"-0.2801,-0.2655,-0.2518,-0.2235,-0.1737,-0.0751,0.1046",\ +"-0.3098,-0.2951,-0.2815,-0.2532,-0.2033,-0.1047,0.0750",\ +"-0.3679,-0.3532,-0.3395,-0.3112,-0.2614,-0.1628,0.0169"); + } + } + + + timing() { + timing_type : hold_rising; + related_pin : "A_CLK"; + when : "(A_WEN & A_MEN)" + sdf_cond : "A_RW_ACCESS" + + rise_constraint("SIG2SRAM_constraint_template") { + index_1("0.0056,0.0232,0.0400,0.0728,0.1280,0.2440,0.4760"); + index_2("0.0056,0.0232,0.0400,0.0728,0.1280,0.2440,0.4760"); + values ("0.3976,0.3820,0.3693,0.3361,0.2882,0.1886,-0.0057",\ +"0.4026,0.3870,0.3743,0.3411,0.2932,0.1936,-0.0007",\ +"0.4071,0.3915,0.3788,0.3456,0.2977,0.1981,0.0038",\ +"0.4162,0.4006,0.3879,0.3547,0.3068,0.2072,0.0129",\ +"0.4234,0.4078,0.3951,0.3619,0.3140,0.2144,0.0201",\ +"0.4531,0.4374,0.4247,0.3915,0.3437,0.2441,0.0497",\ +"0.5111,0.4955,0.4828,0.4496,0.4018,0.3021,0.1078"); + } + + fall_constraint("SIG2SRAM_constraint_template") { + index_1("0.0056,0.0232,0.0400,0.0728,0.1280,0.2440,0.4760"); + index_2("0.0056,0.0232,0.0400,0.0728,0.1280,0.2440,0.4760"); + values ("0.3566,0.3419,0.3273,0.2990,0.2482,0.1564,-0.0282",\ +"0.3616,0.3469,0.3323,0.3040,0.2532,0.1614,-0.0232",\ +"0.3661,0.3514,0.3368,0.3084,0.2577,0.1659,-0.0187",\ +"0.3752,0.3605,0.3459,0.3176,0.2668,0.1750,-0.0096",\ +"0.3824,0.3677,0.3531,0.3248,0.2740,0.1822,-0.0024",\ +"0.4120,0.3974,0.3828,0.3544,0.3037,0.2119,0.0273",\ +"0.4701,0.4555,0.4408,0.4125,0.3617,0.2699,0.0854"); + } + } +} + pin(A_CLK) { + direction : input; + capacitance : 0.00380014; + max_transition : "0.476"; + clock : "true" ; + pin_func_type : active_rising ; + + timing () { + timing_type : "min_pulse_width"; + related_pin : "A_CLK"; + rise_constraint("CLKTRAN_constraint_template") { + index_1("0.0056,0.476"); + values("0.21,0.21"); + } + } + + related_power_pin : VDD; + related_ground_pin : VSS; + + internal_power() { + when : "!A_MEN & !A_WEN & !A_REN"; + rise_power("scalar"){ + values (0); + } + fall_power("scalar"){ + values (0); + } + } + internal_power() { + when : "!A_MEN & A_WEN & !A_REN"; + rise_power("scalar"){ + values (0.4861); + } + fall_power("scalar"){ + values (0); + } + } + internal_power() { + when : "A_MEN & A_WEN & !A_REN"; + rise_power("scalar"){ + values (10.9594); + } + fall_power("scalar"){ + values (0); + } + } + internal_power() { + when : "A_MEN & A_WEN & A_REN"; + rise_power("scalar"){ + values (11.6067); + } + fall_power("scalar"){ + values (0); + } + } + internal_power() { + when : "A_MEN & !A_WEN & A_REN"; + rise_power("scalar"){ + values (8.2850); + } + fall_power("scalar"){ + values (0); + } + } + internal_power() { + when : "!A_MEN & !A_WEN & A_REN"; + rise_power("scalar"){ + values (0.2964); + } + fall_power("scalar"){ + values (0); + } + } + internal_power() { + when : "!A_MEN & A_WEN & A_REN"; + rise_power("scalar"){ + values (0.5323); + } + fall_power("scalar"){ + values (0); + } + } + internal_power() { + when : "A_MEN & !A_WEN & !A_REN"; + rise_power("scalar"){ + values (0); + } + fall_power("scalar"){ + values (0); + } + } + } + bus(A_DIN) { + bus_type : D_7_0; + direction : input ; + capacitance : 0.00500744 ; + memory_write() { + address : A_ADDR ; + clocked_on : A_CLK; + } + + max_transition : "0.476" ; + pin(A_DIN[7:0]) { + related_power_pin : VDD; + related_ground_pin : VSS; + internal_power() { + when : "A_MEN"; + rise_power("scalar"){ + values (0.0299); + } + fall_power("scalar"){ + values (0.0123); + } + } + internal_power() { + when : "!A_MEN"; + rise_power("scalar"){ + values (0.0316); + } + fall_power("scalar"){ + values (0.0122); + } + } + } + timing() { + timing_type : setup_rising; + related_pin : "A_CLK"; + when : "(A_WEN & A_MEN)"; + sdf_cond : "A_W_ACCESS"; + + rise_constraint("SIG2SRAM_constraint_template") { + index_1("0.0056,0.0232,0.0400,0.0728,0.1280,0.2440,0.4760"); + index_2("0.0056,0.0232,0.0400,0.0728,0.1280,0.2440,0.4760"); + values ("-0.2885,-0.2729,-0.2602,-0.2270,-0.1782,-0.0795,0.1138",\ +"-0.2935,-0.2779,-0.2652,-0.2320,-0.1832,-0.0845,0.1088",\ +"-0.2980,-0.2824,-0.2697,-0.2365,-0.1876,-0.0890,0.1043",\ +"-0.3071,-0.2915,-0.2788,-0.2456,-0.1968,-0.0981,0.0952",\ +"-0.3143,-0.2987,-0.2860,-0.2528,-0.2040,-0.1053,0.0880",\ +"-0.3440,-0.3283,-0.3157,-0.2825,-0.2336,-0.1350,0.0584",\ +"-0.4020,-0.3864,-0.3737,-0.3405,-0.2917,-0.1931,0.0003"); + } + + fall_constraint("SIG2SRAM_constraint_template") { + index_1("0.0056,0.0232,0.0400,0.0728,0.1280,0.2440,0.4760"); + index_2("0.0056,0.0232,0.0400,0.0728,0.1280,0.2440,0.4760"); + values ("-0.2543,-0.2397,-0.2260,-0.1977,-0.1479,-0.0493,0.1304",\ +"-0.2593,-0.2447,-0.2310,-0.2027,-0.1529,-0.0543,0.1254",\ +"-0.2638,-0.2492,-0.2355,-0.2072,-0.1574,-0.0587,0.1209",\ +"-0.2729,-0.2583,-0.2446,-0.2163,-0.1665,-0.0679,0.1118",\ +"-0.2801,-0.2655,-0.2518,-0.2235,-0.1737,-0.0751,0.1046",\ +"-0.3098,-0.2951,-0.2815,-0.2532,-0.2033,-0.1047,0.0750",\ +"-0.3679,-0.3532,-0.3395,-0.3112,-0.2614,-0.1628,0.0169"); + } + } + + timing() { + timing_type : hold_rising; + related_pin : "A_CLK"; + when : "(A_WEN & A_MEN)"; + sdf_cond : "A_W_ACCESS"; + + rise_constraint("SIG2SRAM_constraint_template") { + index_1("0.0056,0.0232,0.0400,0.0728,0.1280,0.2440,0.4760"); + index_2("0.0056,0.0232,0.0400,0.0728,0.1280,0.2440,0.4760"); + values ("0.3976,0.3820,0.3693,0.3361,0.2882,0.1886,-0.0057",\ +"0.4026,0.3870,0.3743,0.3411,0.2932,0.1936,-0.0007",\ +"0.4071,0.3915,0.3788,0.3456,0.2977,0.1981,0.0038",\ +"0.4162,0.4006,0.3879,0.3547,0.3068,0.2072,0.0129",\ +"0.4234,0.4078,0.3951,0.3619,0.3140,0.2144,0.0201",\ +"0.4531,0.4374,0.4247,0.3915,0.3437,0.2441,0.0497",\ +"0.5111,0.4955,0.4828,0.4496,0.4018,0.3021,0.1078"); + } + + fall_constraint("SIG2SRAM_constraint_template") { + index_1("0.0056,0.0232,0.0400,0.0728,0.1280,0.2440,0.4760"); + index_2("0.0056,0.0232,0.0400,0.0728,0.1280,0.2440,0.4760"); + values ("0.3566,0.3419,0.3273,0.2990,0.2482,0.1564,-0.0282",\ +"0.3616,0.3469,0.3323,0.3040,0.2532,0.1614,-0.0232",\ +"0.3661,0.3514,0.3368,0.3084,0.2577,0.1659,-0.0187",\ +"0.3752,0.3605,0.3459,0.3176,0.2668,0.1750,-0.0096",\ +"0.3824,0.3677,0.3531,0.3248,0.2740,0.1822,-0.0024",\ +"0.4120,0.3974,0.3828,0.3544,0.3037,0.2119,0.0273",\ +"0.4701,0.4555,0.4408,0.4125,0.3617,0.2699,0.0854"); + } + } + } + + pin(A_BIST_EN) { + direction : input ; + capacitance : 0.00401111 ; + max_transition : "1" ; + related_power_pin : VDD; + related_ground_pin : VSS; + internal_power() { + rise_power("scalar") { + values (0); + } + fall_power("scalar") { + values (0); + } + } + } + +bus(A_BIST_ADDR) { + bus_type : A_7_0; + direction : input ; + capacitance : 0.0121077 ; + pin(A_BIST_ADDR[0]) { + capacitance : 0.00568653 ; + } + pin(A_BIST_ADDR[1]) { + capacitance : 0.00767263 ; + } + pin(A_BIST_ADDR[2]) { + capacitance : 0.0105079 ; + } + pin(A_BIST_ADDR[3]) { + capacitance : 0.0068178 ; + } + pin(A_BIST_ADDR[4]) { + capacitance : 0.00624497 ; + } + pin(A_BIST_ADDR[5]) { + capacitance : 0.0105871 ; + } + pin(A_BIST_ADDR[6]) { + capacitance : 0.0130817 ; + } + max_transition : "0.476" ; + pin(A_BIST_ADDR[7:0]) { + related_power_pin : VDD; + related_ground_pin : VSS; + internal_power() { + when : "A_BIST_MEN"; + rise_power("scalar"){ + values (0.0113); + } + fall_power("scalar"){ + values (0.0053); + } + } + internal_power() { + when : "!A_BIST_MEN"; + rise_power("scalar"){ + values (0.0194); + } + fall_power("scalar"){ + values (0.0005); + } + } + } + timing() { + timing_type : setup_rising; + related_pin : "A_BIST_CLK"; + when : "((A_BIST_WEN | A_BIST_REN)& A_BIST_MEN)" + sdf_cond : "A_BIST_RW_ACCESS" + + rise_constraint("SIG2SRAM_constraint_template") { + index_1("0.0056,0.0232,0.0400,0.0728,0.1280,0.2440,0.4760"); + index_2("0.0056,0.0232,0.0400,0.0728,0.1280,0.2440,0.4760"); + values ("-0.4168,-0.3973,-0.3855,-0.3543,-0.3074,-0.2020,-0.0027",\ +"-0.4324,-0.4129,-0.4012,-0.3699,-0.3191,-0.2176,-0.0184",\ +"-0.4441,-0.4285,-0.4129,-0.3816,-0.3309,-0.2293,-0.0301",\ +"-0.4793,-0.4598,-0.4441,-0.4129,-0.3660,-0.2645,-0.0652",\ +"-0.5223,-0.5066,-0.4910,-0.4598,-0.4129,-0.3074,-0.1121",\ +"-0.6199,-0.6082,-0.5926,-0.5613,-0.5145,-0.4129,-0.2137",\ +"-0.8191,-0.8074,-0.7840,-0.7566,-0.7098,-0.6082,-0.4051"); + } + + fall_constraint("SIG2SRAM_constraint_template") { + index_1("0.0056,0.0232,0.0400,0.0728,0.1280,0.2440,0.4760"); + index_2("0.0056,0.0232,0.0400,0.0728,0.1280,0.2440,0.4760"); + values ("-0.3309,-0.3113,-0.2996,-0.2684,-0.2176,-0.1238,0.0637",\ +"-0.3465,-0.3309,-0.3152,-0.2840,-0.2332,-0.1395,0.0480",\ +"-0.3582,-0.3426,-0.3270,-0.2996,-0.2488,-0.1512,0.0324",\ +"-0.3895,-0.3738,-0.3582,-0.3309,-0.2801,-0.1863,0.0051",\ +"-0.4363,-0.4207,-0.4051,-0.3777,-0.3230,-0.2293,-0.0379",\ +"-0.5379,-0.5223,-0.5066,-0.4793,-0.4285,-0.3309,-0.1434",\ +"-0.7332,-0.7176,-0.7020,-0.6746,-0.6238,-0.5262,-0.3387"); + } + } + + + timing() { + timing_type : hold_rising; + related_pin : "A_BIST_CLK"; + when : "((A_BIST_WEN | A_BIST_REN)& A_BIST_MEN)" + sdf_cond : "A_BIST_RW_ACCESS" + + rise_constraint("SIG2SRAM_constraint_template") { + index_1("0.0056,0.0232,0.0400,0.0728,0.1280,0.2440,0.4760"); + index_2("0.0056,0.0232,0.0400,0.0728,0.1280,0.2440,0.4760"); + values ("0.5246,0.5051,0.4895,0.4582,0.4113,0.3059,0.1066",\ +"0.5402,0.5207,0.5051,0.4777,0.4270,0.3215,0.1223",\ +"0.5520,0.5324,0.5168,0.4895,0.4387,0.3371,0.1340",\ +"0.5832,0.5676,0.5520,0.5207,0.4738,0.3684,0.1691",\ +"0.6301,0.6105,0.5949,0.5676,0.5168,0.4113,0.2160",\ +"0.7316,0.7121,0.7004,0.6691,0.6223,0.5168,0.3176",\ +"0.9270,0.9230,0.8957,0.8645,0.8137,0.7121,0.5168"); + } + + fall_constraint("SIG2SRAM_constraint_template") { + index_1("0.0056,0.0232,0.0400,0.0728,0.1280,0.2440,0.4760"); + index_2("0.0056,0.0232,0.0400,0.0728,0.1280,0.2440,0.4760"); + values ("0.4309,0.4152,0.4035,0.3684,0.3215,0.2277,0.0363",\ +"0.4465,0.4309,0.4152,0.3879,0.3371,0.2395,0.0559",\ +"0.4582,0.4426,0.4309,0.3996,0.3488,0.2551,0.0715",\ +"0.4934,0.4777,0.4621,0.4348,0.3840,0.2863,0.0988",\ +"0.5363,0.5207,0.5051,0.4777,0.4270,0.3332,0.1418",\ +"0.6379,0.6262,0.6105,0.5793,0.5324,0.4348,0.2434",\ +"0.8332,0.8215,0.8059,0.7707,0.7238,0.6301,0.4387"); + } + } +} +pin(A_BIST_WEN) { + direction : input ; + capacitance : 0.00324098 ; + max_transition : "0.476" ; + related_power_pin : VDD; + related_ground_pin : VSS; + internal_power() { + when : "A_BIST_MEN"; + rise_power("scalar"){ + values (0.0046); + } + fall_power("scalar"){ + values (0.0037); + } + } + internal_power() { + when : "!A_BIST_MEN"; + rise_power("scalar"){ + values (0.0041); + } + fall_power("scalar"){ + values (0.0037); + } + } + timing() { + timing_type : setup_rising; + related_pin : "A_BIST_CLK"; + when : "A_BIST_MEN" + sdf_cond : "A_BIST_MEN" + + rise_constraint("SIG2SRAM_constraint_template") { + index_1("0.0056,0.0232,0.0400,0.0728,0.1280,0.2440,0.4760"); + index_2("0.0056,0.0232,0.0400,0.0728,0.1280,0.2440,0.4760"); + values ("0.2043,0.2199,0.2316,0.2629,0.3059,0.4113,0.6066",\ +"0.1887,0.2043,0.2160,0.2473,0.2941,0.3957,0.5949",\ +"0.1691,0.1848,0.2004,0.2316,0.2785,0.3801,0.5754",\ +"0.1379,0.1574,0.1691,0.2004,0.2473,0.3527,0.5480",\ +"0.0910,0.1066,0.1223,0.1535,0.2004,0.2980,0.4973",\ +"-0.0105,0.0051,0.0207,0.0520,0.0949,0.2004,0.3957",\ +"-0.2059,-0.1902,-0.1746,-0.1473,-0.1004,0.0051,0.2004"); + } + + fall_constraint("SIG2SRAM_constraint_template") { + index_1("0.0056,0.0232,0.0400,0.0728,0.1280,0.2440,0.4760"); + index_2("0.0056,0.0232,0.0400,0.0728,0.1280,0.2440,0.4760"); + values ("0.2941,0.3098,0.3215,0.3488,0.4035,0.4973,0.6887",\ +"0.2785,0.2941,0.3059,0.3332,0.3840,0.4816,0.6691",\ +"0.2629,0.2785,0.2902,0.3176,0.3684,0.4660,0.6535",\ +"0.2316,0.2473,0.2590,0.2863,0.3410,0.4348,0.6262",\ +"0.1848,0.2004,0.2121,0.2395,0.2902,0.3879,0.5754",\ +"0.0832,0.0988,0.1105,0.1379,0.1809,0.2746,0.4699",\ +"-0.1121,-0.0965,-0.0848,-0.0535,-0.0066,0.0910,0.2824"); + } + } + + + timing() { + timing_type : hold_rising; + related_pin : "A_BIST_CLK"; + when : "A_BIST_MEN" + sdf_cond : "A_BIST_MEN" + + rise_constraint("SIG2SRAM_constraint_template") { + index_1("0.0056,0.0232,0.0400,0.0728,0.1280,0.2440,0.4760"); + index_2("0.0056,0.0232,0.0400,0.0728,0.1280,0.2440,0.4760"); + values ("0.2473,0.2316,0.2160,0.1887,0.1379,0.0363,-0.1629",\ +"0.2629,0.2473,0.2316,0.2043,0.1535,0.0520,-0.1473",\ +"0.2785,0.2590,0.2434,0.2160,0.1652,0.0676,-0.1355",\ +"0.3098,0.2941,0.2785,0.2473,0.1965,0.0910,-0.1043",\ +"0.3527,0.3371,0.3215,0.2941,0.2434,0.1418,-0.0574",\ +"0.4582,0.4426,0.4270,0.3957,0.3488,0.2434,0.0480",\ +"0.6535,0.6379,0.6184,0.5910,0.5402,0.4426,0.2434"); + } + + fall_constraint("SIG2SRAM_constraint_template") { + index_1("0.0056,0.0232,0.0400,0.0728,0.1280,0.2440,0.4760"); + index_2("0.0056,0.0232,0.0400,0.0728,0.1280,0.2440,0.4760"); + values ("0.2395,0.2238,0.2121,0.1809,0.1301,0.0324,-0.1551",\ +"0.2551,0.2395,0.2277,0.1965,0.1457,0.0480,-0.1395",\ +"0.2668,0.2551,0.2395,0.2082,0.1574,0.0637,-0.1277",\ +"0.3020,0.2863,0.2707,0.2395,0.1887,0.0910,-0.0965",\ +"0.3449,0.3293,0.3176,0.2863,0.2355,0.1379,-0.0496",\ +"0.4504,0.4348,0.4191,0.3879,0.3371,0.2395,0.0559",\ +"0.6457,0.6301,0.6145,0.5871,0.5324,0.4309,0.2512"); + } + } + } +pin(A_BIST_REN) { + direction : input ; + capacitance : 0.00381634 ; + max_transition : "0.476" ; + related_power_pin : VDD; + related_ground_pin : VSS; + internal_power() { + when : "A_BIST_MEN"; + rise_power("scalar"){ + values (0.0060); + } + fall_power("scalar"){ + values (0.0020); + } + } + internal_power() { + when : "!A_BIST_MEN"; + rise_power("scalar"){ + values (0.0061); + } + fall_power("scalar"){ + values (0.0023); + } + } + timing() { + timing_type : setup_rising; + related_pin : "A_BIST_CLK"; + when : "A_BIST_MEN" + sdf_cond : "A_BIST_MEN" + + rise_constraint("SIG2SRAM_constraint_template") { + index_1("0.0056,0.0232,0.0400,0.0728,0.1280,0.2440,0.4760"); + index_2("0.0056,0.0232,0.0400,0.0728,0.1280,0.2440,0.4760"); + values ("-0.0301,-0.0145,0.0012,0.0324,0.0793,0.1809,0.3762",\ +"-0.0457,-0.0301,-0.0145,0.0168,0.0637,0.1613,0.3605",\ +"-0.0574,-0.0418,-0.0262,0.0051,0.0520,0.1496,0.3449",\ +"-0.0926,-0.0730,-0.0574,-0.0262,0.0207,0.1184,0.3137",\ +"-0.1395,-0.1238,-0.1082,-0.0770,-0.0301,0.0715,0.2707",\ +"-0.2410,-0.2254,-0.2098,-0.1746,-0.1355,-0.0340,0.1652",\ +"-0.4402,-0.4207,-0.4051,-0.3738,-0.3270,-0.2293,-0.0340"); + } + + fall_constraint("SIG2SRAM_constraint_template") { + index_1("0.0056,0.0232,0.0400,0.0728,0.1280,0.2440,0.4760"); + index_2("0.0056,0.0232,0.0400,0.0728,0.1280,0.2440,0.4760"); + values ("0.0988,0.1145,0.1262,0.1535,0.2043,0.3020,0.4855",\ +"0.0832,0.0988,0.1105,0.1418,0.1848,0.2824,0.4738",\ +"0.0676,0.0832,0.0949,0.1262,0.1730,0.2668,0.4621",\ +"0.0402,0.0559,0.0676,0.0988,0.1457,0.2434,0.4191",\ +"-0.0105,0.0012,0.0168,0.0480,0.0988,0.1965,0.3840",\ +"-0.1160,-0.0965,-0.0848,-0.0535,-0.0066,0.0988,0.2824",\ +"-0.3113,-0.2957,-0.2801,-0.2527,-0.2059,-0.1043,0.0832"); + } + } + + + timing() { + timing_type : hold_rising; + related_pin : "A_BIST_CLK"; + when : "A_BIST_MEN" + sdf_cond : "A_BIST_MEN" + + rise_constraint("SIG2SRAM_constraint_template") { + index_1("0.0056,0.0232,0.0400,0.0728,0.1280,0.2440,0.4760"); + index_2("0.0056,0.0232,0.0400,0.0728,0.1280,0.2440,0.4760"); + values ("0.2707,0.2551,0.2395,0.2121,0.1613,0.0598,-0.1395",\ +"0.2863,0.2707,0.2551,0.2238,0.1730,0.0715,-0.1238",\ +"0.2980,0.2824,0.2668,0.2395,0.1887,0.0871,-0.1121",\ +"0.3332,0.3176,0.3020,0.2707,0.2199,0.1184,-0.0809",\ +"0.3762,0.3605,0.3449,0.3176,0.2668,0.1613,-0.0340",\ +"0.4816,0.4621,0.4504,0.4191,0.3723,0.2629,0.0715",\ +"0.6770,0.6613,0.6418,0.6184,0.5637,0.4699,0.2629"); + } + + fall_constraint("SIG2SRAM_constraint_template") { + index_1("0.0056,0.0232,0.0400,0.0728,0.1280,0.2440,0.4760"); + index_2("0.0056,0.0232,0.0400,0.0728,0.1280,0.2440,0.4760"); + values ("0.2590,0.2434,0.2316,0.2004,0.1457,0.0520,-0.1355",\ +"0.2746,0.2590,0.2434,0.2160,0.1613,0.0676,-0.1199",\ +"0.2863,0.2707,0.2590,0.2277,0.1730,0.0832,-0.1082",\ +"0.3215,0.3059,0.2902,0.2590,0.2082,0.1105,-0.0770",\ +"0.3645,0.3488,0.3332,0.3059,0.2551,0.1535,-0.0340",\ +"0.4699,0.4543,0.4387,0.4074,0.3605,0.2551,0.0715",\ +"0.6652,0.6496,0.6340,0.6027,0.5520,0.4621,0.2707"); + } + } + } +pin(A_BIST_MEN) { + direction : input ; + capacitance : 0.00309605 ; + max_transition : "0.476" ; + related_power_pin : VDD; + related_ground_pin : VSS; + internal_power() { + rise_power("scalar"){ + values (0.0236); + } + fall_power("scalar"){ + values (0.0052); + } + } + timing() { + timing_type : setup_rising; + related_pin : "A_BIST_CLK"; + + rise_constraint("SIG2SRAM_constraint_template") { + index_1("0.0056,0.0232,0.0400,0.0728,0.1280,0.2440,0.4760"); + index_2("0.0056,0.0232,0.0400,0.0728,0.1280,0.2440,0.4760"); + values ("0.2043,0.2199,0.2316,0.2668,0.3098,0.4152,0.6066",\ +"0.1887,0.2043,0.2199,0.2512,0.2941,0.3996,0.5949",\ +"0.1730,0.1887,0.2043,0.2355,0.2824,0.3840,0.5793",\ +"0.1418,0.1574,0.1730,0.2043,0.2512,0.3566,0.5480",\ +"0.0949,0.1105,0.1262,0.1574,0.2043,0.3020,0.5051",\ +"-0.0066,0.0090,0.0246,0.0520,0.0988,0.2043,0.3996",\ +"-0.2020,-0.1863,-0.1746,-0.1434,-0.0965,0.0090,0.2082"); + } + + fall_constraint("SIG2SRAM_constraint_template") { + index_1("0.0056,0.0232,0.0400,0.0728,0.1280,0.2440,0.4760"); + index_2("0.0056,0.0232,0.0400,0.0728,0.1280,0.2440,0.4760"); + values ("0.2980,0.3137,0.3254,0.3527,0.4035,0.5012,0.6887",\ +"0.2824,0.2980,0.3098,0.3371,0.3879,0.4855,0.6730",\ +"0.2668,0.2824,0.2941,0.3215,0.3723,0.4699,0.6574",\ +"0.2355,0.2473,0.2629,0.2902,0.3410,0.4387,0.6262",\ +"0.1887,0.2004,0.2160,0.2395,0.2941,0.3918,0.5793",\ +"0.0871,0.1027,0.1145,0.1418,0.1848,0.2746,0.4816",\ +"-0.1082,-0.0965,-0.0809,-0.0496,-0.0027,0.0949,0.2863"); + } + } + + + timing() { + timing_type : hold_rising; + related_pin : "A_BIST_CLK"; + + rise_constraint("SIG2SRAM_constraint_template") { + index_1("0.0056,0.0232,0.0400,0.0728,0.1280,0.2440,0.4760"); + index_2("0.0056,0.0232,0.0400,0.0728,0.1280,0.2440,0.4760"); + values ("0.2512,0.2355,0.2199,0.1926,0.1418,0.0402,-0.1590",\ +"0.2668,0.2512,0.2355,0.2082,0.1574,0.0559,-0.1434",\ +"0.2824,0.2629,0.2512,0.2199,0.1691,0.0715,-0.1316",\ +"0.3137,0.2980,0.2824,0.2512,0.2004,0.0988,-0.0965",\ +"0.3566,0.3410,0.3254,0.2980,0.2473,0.1418,-0.0535",\ +"0.4621,0.4426,0.4309,0.3996,0.3527,0.2473,0.0520",\ +"0.6574,0.6418,0.6262,0.5949,0.5441,0.4465,0.2473"); + } + + fall_constraint("SIG2SRAM_constraint_template") { + index_1("0.0056,0.0232,0.0400,0.0728,0.1280,0.2440,0.4760"); + index_2("0.0056,0.0232,0.0400,0.0728,0.1280,0.2440,0.4760"); + values ("0.2395,0.2238,0.2121,0.1809,0.1301,0.0324,-0.1551",\ +"0.2551,0.2434,0.2277,0.1965,0.1457,0.0480,-0.1395",\ +"0.2707,0.2551,0.2395,0.2082,0.1574,0.0637,-0.1277",\ +"0.3020,0.2863,0.2707,0.2434,0.1926,0.0910,-0.0965",\ +"0.3449,0.3332,0.3176,0.2863,0.2355,0.1379,-0.0496",\ +"0.4504,0.4348,0.4230,0.3918,0.3410,0.2434,0.0559",\ +"0.6457,0.6301,0.6145,0.5910,0.5324,0.4387,0.2512"); + } + } + } +bus(A_BIST_BM) { + bus_type : D_7_0; + direction : input ; + capacitance : 0.00349377 ; + max_transition : "0.476" ; + pin(A_BIST_BM[7:0]) { + related_power_pin : VDD; + related_ground_pin : VSS; + internal_power() { + when : "A_BIST_MEN"; + rise_power("scalar"){ + values (0.0299); + } + fall_power("scalar"){ + values (0.0123); + } + } + internal_power() { + when : "!A_BIST_MEN"; + rise_power("scalar"){ + values (0.0316); + } + fall_power("scalar"){ + values (0.0122); + } + } + } + timing() { + timing_type : setup_rising; + related_pin : "A_BIST_CLK"; + when : "(A_BIST_WEN & A_BIST_MEN)" + sdf_cond : "A_BIST_RW_ACCESS" + + rise_constraint("SIG2SRAM_constraint_template") { + index_1("0.0056,0.0232,0.0400,0.0728,0.1280,0.2440,0.4760"); + index_2("0.0056,0.0232,0.0400,0.0728,0.1280,0.2440,0.4760"); + values ("-0.2885,-0.2729,-0.2602,-0.2270,-0.1782,-0.0795,0.1138",\ +"-0.2935,-0.2779,-0.2652,-0.2320,-0.1832,-0.0845,0.1088",\ +"-0.2980,-0.2824,-0.2697,-0.2365,-0.1876,-0.0890,0.1043",\ +"-0.3071,-0.2915,-0.2788,-0.2456,-0.1968,-0.0981,0.0952",\ +"-0.3143,-0.2987,-0.2860,-0.2528,-0.2040,-0.1053,0.0880",\ +"-0.3440,-0.3283,-0.3157,-0.2825,-0.2336,-0.1350,0.0584",\ +"-0.4020,-0.3864,-0.3737,-0.3405,-0.2917,-0.1931,0.0003"); + } + + fall_constraint("SIG2SRAM_constraint_template") { + index_1("0.0056,0.0232,0.0400,0.0728,0.1280,0.2440,0.4760"); + index_2("0.0056,0.0232,0.0400,0.0728,0.1280,0.2440,0.4760"); + values ("-0.2543,-0.2397,-0.2260,-0.1977,-0.1479,-0.0493,0.1304",\ +"-0.2593,-0.2447,-0.2310,-0.2027,-0.1529,-0.0543,0.1254",\ +"-0.2638,-0.2492,-0.2355,-0.2072,-0.1574,-0.0587,0.1209",\ +"-0.2729,-0.2583,-0.2446,-0.2163,-0.1665,-0.0679,0.1118",\ +"-0.2801,-0.2655,-0.2518,-0.2235,-0.1737,-0.0751,0.1046",\ +"-0.3098,-0.2951,-0.2815,-0.2532,-0.2033,-0.1047,0.0750",\ +"-0.3679,-0.3532,-0.3395,-0.3112,-0.2614,-0.1628,0.0169"); + } + } + + + timing() { + timing_type : hold_rising; + related_pin : "A_BIST_CLK"; + when : "(A_BIST_WEN & A_BIST_MEN)" + sdf_cond : "A_BIST_RW_ACCESS" + + rise_constraint("SIG2SRAM_constraint_template") { + index_1("0.0056,0.0232,0.0400,0.0728,0.1280,0.2440,0.4760"); + index_2("0.0056,0.0232,0.0400,0.0728,0.1280,0.2440,0.4760"); + values ("0.3976,0.3820,0.3693,0.3361,0.2882,0.1886,-0.0057",\ +"0.4026,0.3870,0.3743,0.3411,0.2932,0.1936,-0.0007",\ +"0.4071,0.3915,0.3788,0.3456,0.2977,0.1981,0.0038",\ +"0.4162,0.4006,0.3879,0.3547,0.3068,0.2072,0.0129",\ +"0.4234,0.4078,0.3951,0.3619,0.3140,0.2144,0.0201",\ +"0.4531,0.4374,0.4247,0.3915,0.3437,0.2441,0.0497",\ +"0.5111,0.4955,0.4828,0.4496,0.4018,0.3021,0.1078"); + } + + fall_constraint("SIG2SRAM_constraint_template") { + index_1("0.0056,0.0232,0.0400,0.0728,0.1280,0.2440,0.4760"); + index_2("0.0056,0.0232,0.0400,0.0728,0.1280,0.2440,0.4760"); + values ("0.3566,0.3419,0.3273,0.2990,0.2482,0.1564,-0.0282",\ +"0.3616,0.3469,0.3323,0.3040,0.2532,0.1614,-0.0232",\ +"0.3661,0.3514,0.3368,0.3084,0.2577,0.1659,-0.0187",\ +"0.3752,0.3605,0.3459,0.3176,0.2668,0.1750,-0.0096",\ +"0.3824,0.3677,0.3531,0.3248,0.2740,0.1822,-0.0024",\ +"0.4120,0.3974,0.3828,0.3544,0.3037,0.2119,0.0273",\ +"0.4701,0.4555,0.4408,0.4125,0.3617,0.2699,0.0854"); + } + } +} + pin(A_BIST_CLK) { + direction : input; + capacitance : 0.00380014; + max_transition : "0.476"; + clock : "true" ; + pin_func_type : active_rising ; + + timing () { + timing_type : "min_pulse_width"; + related_pin : "A_BIST_CLK"; + rise_constraint("CLKTRAN_constraint_template") { + index_1("0.0056,0.476"); + values("0.21,0.21"); + } + } + + related_power_pin : VDD; + related_ground_pin : VSS; + + internal_power() { + when : "!A_BIST_MEN & !A_BIST_WEN & !A_BIST_REN"; + rise_power("scalar"){ + values (0); + } + fall_power("scalar"){ + values (0); + } + } + internal_power() { + when : "!A_BIST_MEN & A_BIST_WEN & !A_BIST_REN"; + rise_power("scalar"){ + values (0.4861); + } + fall_power("scalar"){ + values (0); + } + } + internal_power() { + when : "A_BIST_MEN & A_BIST_WEN & !A_BIST_REN"; + rise_power("scalar"){ + values (10.9594); + } + fall_power("scalar"){ + values (0); + } + } + internal_power() { + when : "A_BIST_MEN & A_BIST_WEN & A_BIST_REN"; + rise_power("scalar"){ + values (11.6067); + } + fall_power("scalar"){ + values (0); + } + } + internal_power() { + when : "A_BIST_MEN & !A_BIST_WEN & A_BIST_REN"; + rise_power("scalar"){ + values (8.2850); + } + fall_power("scalar"){ + values (0); + } + } + internal_power() { + when : "!A_BIST_MEN & !A_BIST_WEN & A_BIST_REN"; + rise_power("scalar"){ + values (0.2964); + } + fall_power("scalar"){ + values (0); + } + } + internal_power() { + when : "!A_BIST_MEN & A_BIST_WEN & A_BIST_REN"; + rise_power("scalar"){ + values (0.5323); + } + fall_power("scalar"){ + values (0); + } + } + internal_power() { + when : "A_BIST_MEN & !A_BIST_WEN & !A_BIST_REN"; + rise_power("scalar"){ + values (0); + } + fall_power("scalar"){ + values (0); + } + } + } + bus(A_BIST_DIN) { + bus_type : D_7_0; + direction : input ; + capacitance : 0.00393889 ; + memory_write() { + address : A_BIST_ADDR ; + clocked_on : A_BIST_CLK; + } + + max_transition : "0.476" ; + pin(A_BIST_DIN[7:0]) { + related_power_pin : VDD; + related_ground_pin : VSS; + internal_power() { + when : "A_BIST_MEN"; + rise_power("scalar"){ + values (0.0299); + } + fall_power("scalar"){ + values (0.0123); + } + } + internal_power() { + when : "!A_BIST_MEN"; + rise_power("scalar"){ + values (0.0316); + } + fall_power("scalar"){ + values (0.0122); + } + } + } + timing() { + timing_type : setup_rising; + related_pin : "A_BIST_CLK"; + when : "(A_BIST_WEN & A_BIST_MEN)"; + sdf_cond : "A_BIST_W_ACCESS"; + + rise_constraint("SIG2SRAM_constraint_template") { + index_1("0.0056,0.0232,0.0400,0.0728,0.1280,0.2440,0.4760"); + index_2("0.0056,0.0232,0.0400,0.0728,0.1280,0.2440,0.4760"); + values ("-0.2885,-0.2729,-0.2602,-0.2270,-0.1782,-0.0795,0.1138",\ +"-0.2935,-0.2779,-0.2652,-0.2320,-0.1832,-0.0845,0.1088",\ +"-0.2980,-0.2824,-0.2697,-0.2365,-0.1876,-0.0890,0.1043",\ +"-0.3071,-0.2915,-0.2788,-0.2456,-0.1968,-0.0981,0.0952",\ +"-0.3143,-0.2987,-0.2860,-0.2528,-0.2040,-0.1053,0.0880",\ +"-0.3440,-0.3283,-0.3157,-0.2825,-0.2336,-0.1350,0.0584",\ +"-0.4020,-0.3864,-0.3737,-0.3405,-0.2917,-0.1931,0.0003"); + } + + fall_constraint("SIG2SRAM_constraint_template") { + index_1("0.0056,0.0232,0.0400,0.0728,0.1280,0.2440,0.4760"); + index_2("0.0056,0.0232,0.0400,0.0728,0.1280,0.2440,0.4760"); + values ("-0.2543,-0.2397,-0.2260,-0.1977,-0.1479,-0.0493,0.1304",\ +"-0.2593,-0.2447,-0.2310,-0.2027,-0.1529,-0.0543,0.1254",\ +"-0.2638,-0.2492,-0.2355,-0.2072,-0.1574,-0.0587,0.1209",\ +"-0.2729,-0.2583,-0.2446,-0.2163,-0.1665,-0.0679,0.1118",\ +"-0.2801,-0.2655,-0.2518,-0.2235,-0.1737,-0.0751,0.1046",\ +"-0.3098,-0.2951,-0.2815,-0.2532,-0.2033,-0.1047,0.0750",\ +"-0.3679,-0.3532,-0.3395,-0.3112,-0.2614,-0.1628,0.0169"); + } + } + + timing() { + timing_type : hold_rising; + related_pin : "A_BIST_CLK"; + when : "(A_BIST_WEN & A_BIST_MEN)"; + sdf_cond : "A_BIST_W_ACCESS"; + + rise_constraint("SIG2SRAM_constraint_template") { + index_1("0.0056,0.0232,0.0400,0.0728,0.1280,0.2440,0.4760"); + index_2("0.0056,0.0232,0.0400,0.0728,0.1280,0.2440,0.4760"); + values ("0.3976,0.3820,0.3693,0.3361,0.2882,0.1886,-0.0057",\ +"0.4026,0.3870,0.3743,0.3411,0.2932,0.1936,-0.0007",\ +"0.4071,0.3915,0.3788,0.3456,0.2977,0.1981,0.0038",\ +"0.4162,0.4006,0.3879,0.3547,0.3068,0.2072,0.0129",\ +"0.4234,0.4078,0.3951,0.3619,0.3140,0.2144,0.0201",\ +"0.4531,0.4374,0.4247,0.3915,0.3437,0.2441,0.0497",\ +"0.5111,0.4955,0.4828,0.4496,0.4018,0.3021,0.1078"); + } + + fall_constraint("SIG2SRAM_constraint_template") { + index_1("0.0056,0.0232,0.0400,0.0728,0.1280,0.2440,0.4760"); + index_2("0.0056,0.0232,0.0400,0.0728,0.1280,0.2440,0.4760"); + values ("0.3566,0.3419,0.3273,0.2990,0.2482,0.1564,-0.0282",\ +"0.3616,0.3469,0.3323,0.3040,0.2532,0.1614,-0.0232",\ +"0.3661,0.3514,0.3368,0.3084,0.2577,0.1659,-0.0187",\ +"0.3752,0.3605,0.3459,0.3176,0.2668,0.1750,-0.0096",\ +"0.3824,0.3677,0.3531,0.3248,0.2740,0.1822,-0.0024",\ +"0.4120,0.3974,0.3828,0.3544,0.3037,0.2119,0.0273",\ +"0.4701,0.4555,0.4408,0.4125,0.3617,0.2699,0.0854"); + } + } + } + +bus(A_DOUT) { + + bus_type : D_7_0; + direction : output ; + capacitance : 0 ; + max_capacitance : 0.064 ; + memory_read() { + address : A_ADDR ; + } + pin(A_DOUT[7:0]) { + related_power_pin : VDD; + related_ground_pin : VSS; + internal_power() { + rise_power("scalar") { + values (0); + } + fall_power("scalar") { + values (0); + } + } + } + timing() { + related_pin : "A_CLK"; + timing_type : rising_edge ; + timing_sense : non_unate ; + + cell_rise(SIG2SRAM_delay_template) { + index_1("0.0056,0.0232,0.0400,0.0728,0.1280,0.2440,0.4760"); + index_2("0.0008,0.0014,0.0051,0.0100,0.0339,0.0640"); + values ("2.9518,2.9534,2.9610,2.9697,3.0021,3.0383",\ +"2.9581,2.9597,2.9673,2.9761,3.0085,3.0446",\ +"2.9602,2.9618,2.9694,2.9782,3.0106,3.0467",\ +"2.9733,2.9749,2.9825,2.9912,3.0236,3.0598",\ +"2.9795,2.9811,2.9887,2.9974,3.0298,3.0660",\ +"3.0109,3.0125,3.0202,3.0289,3.0613,3.0974",\ +"3.0654,3.0671,3.0747,3.0834,3.1158,3.1519"); + } + cell_fall(SIG2SRAM_delay_template) { + index_1("0.0056,0.0232,0.0400,0.0728,0.1280,0.2440,0.4760"); + index_2("0.0008,0.0014,0.0051,0.0100,0.0339,0.0640"); + values ("2.8915,2.8928,2.8989,2.9060,2.9325,2.9588",\ +"2.8978,2.8992,2.9052,2.9124,2.9389,2.9651",\ +"2.8999,2.9013,2.9073,2.9145,2.9410,2.9672",\ +"2.9130,2.9143,2.9204,2.9275,2.9540,2.9803",\ +"2.9192,2.9205,2.9266,2.9337,2.9602,2.9865",\ +"2.9506,2.9520,2.9581,2.9652,2.9917,3.0179",\ +"3.0052,3.0065,3.0126,3.0197,3.0462,3.0724"); + } + + rise_transition(SRAM_load_template) { + index_1("0.0008,0.0014,0.0051,0.0100,0.0339,0.0640"); + values ("0.0326,0.0341,0.0428,0.0518,0.0923,0.1492"); + } + fall_transition(SRAM_load_template) { + index_1("0.0008,0.0014,0.0051,0.0100,0.0339,0.0640"); + values ("0.0254,0.0265,0.0335,0.0402,0.0707,0.1039"); + } + } +} + pin(B_DLY) { + direction : input ; + capacitance : 0.00401111 ; + max_transition : "1" ; + related_power_pin : VDD; + related_ground_pin : VSS; + internal_power() { + rise_power("scalar") { + values (0); + } + fall_power("scalar") { + values (0); + } + } + } + +bus(B_ADDR) { + bus_type : A_7_0; + direction : input ; + capacitance : 0.0121077 ; + pin(B_ADDR[0]) { + capacitance : 0.00570093 ; + } + pin(B_ADDR[1]) { + capacitance : 0.00764555 ; + } + pin(B_ADDR[2]) { + capacitance : 0.0105375 ; + } + pin(B_ADDR[3]) { + capacitance : 0.0067894 ; + } + pin(B_ADDR[4]) { + capacitance : 0.00630967 ; + } + pin(B_ADDR[5]) { + capacitance : 0.0104132 ; + } + pin(B_ADDR[6]) { + capacitance : 0.0131402 ; + } + max_transition : "0.476" ; + pin(B_ADDR[7:0]) { + related_power_pin : VDD; + related_ground_pin : VSS; + internal_power() { + when : "B_MEN"; + rise_power("scalar"){ + values (0.0113); + } + fall_power("scalar"){ + values (0.0053); + } + } + internal_power() { + when : "!B_MEN"; + rise_power("scalar"){ + values (0.0194); + } + fall_power("scalar"){ + values (0.0005); + } + } + } + timing() { + timing_type : setup_rising; + related_pin : "B_CLK"; + when : "((B_WEN | B_REN)& B_MEN)" + sdf_cond : "B_RW_ACCESS" + + rise_constraint("SIG2SRAM_constraint_template") { + index_1("0.0056,0.0232,0.0400,0.0728,0.1280,0.2440,0.4760"); + index_2("0.0056,0.0232,0.0400,0.0728,0.1280,0.2440,0.4760"); + values ("-0.4168,-0.3973,-0.3855,-0.3543,-0.3074,-0.2020,-0.0027",\ +"-0.4324,-0.4129,-0.4012,-0.3699,-0.3191,-0.2176,-0.0184",\ +"-0.4441,-0.4285,-0.4129,-0.3816,-0.3309,-0.2293,-0.0301",\ +"-0.4793,-0.4598,-0.4441,-0.4129,-0.3660,-0.2645,-0.0652",\ +"-0.5223,-0.5066,-0.4910,-0.4598,-0.4129,-0.3074,-0.1121",\ +"-0.6199,-0.6082,-0.5926,-0.5613,-0.5145,-0.4129,-0.2137",\ +"-0.8191,-0.8074,-0.7840,-0.7566,-0.7098,-0.6082,-0.4051"); + } + + fall_constraint("SIG2SRAM_constraint_template") { + index_1("0.0056,0.0232,0.0400,0.0728,0.1280,0.2440,0.4760"); + index_2("0.0056,0.0232,0.0400,0.0728,0.1280,0.2440,0.4760"); + values ("-0.3309,-0.3113,-0.2996,-0.2684,-0.2176,-0.1238,0.0637",\ +"-0.3465,-0.3309,-0.3152,-0.2840,-0.2332,-0.1395,0.0480",\ +"-0.3582,-0.3426,-0.3270,-0.2996,-0.2488,-0.1512,0.0324",\ +"-0.3895,-0.3738,-0.3582,-0.3309,-0.2801,-0.1863,0.0051",\ +"-0.4363,-0.4207,-0.4051,-0.3777,-0.3230,-0.2293,-0.0379",\ +"-0.5379,-0.5223,-0.5066,-0.4793,-0.4285,-0.3309,-0.1434",\ +"-0.7332,-0.7176,-0.7020,-0.6746,-0.6238,-0.5262,-0.3387"); + } + } + + + timing() { + timing_type : hold_rising; + related_pin : "B_CLK"; + when : "((B_WEN | B_REN)& B_MEN)" + sdf_cond : "B_RW_ACCESS" + + rise_constraint("SIG2SRAM_constraint_template") { + index_1("0.0056,0.0232,0.0400,0.0728,0.1280,0.2440,0.4760"); + index_2("0.0056,0.0232,0.0400,0.0728,0.1280,0.2440,0.4760"); + values ("0.5246,0.5051,0.4895,0.4582,0.4113,0.3059,0.1066",\ +"0.5402,0.5207,0.5051,0.4777,0.4270,0.3215,0.1223",\ +"0.5520,0.5324,0.5168,0.4895,0.4387,0.3371,0.1340",\ +"0.5832,0.5676,0.5520,0.5207,0.4738,0.3684,0.1691",\ +"0.6301,0.6105,0.5949,0.5676,0.5168,0.4113,0.2160",\ +"0.7316,0.7121,0.7004,0.6691,0.6223,0.5168,0.3176",\ +"0.9270,0.9230,0.8957,0.8645,0.8137,0.7121,0.5168"); + } + + fall_constraint("SIG2SRAM_constraint_template") { + index_1("0.0056,0.0232,0.0400,0.0728,0.1280,0.2440,0.4760"); + index_2("0.0056,0.0232,0.0400,0.0728,0.1280,0.2440,0.4760"); + values ("0.4309,0.4152,0.4035,0.3684,0.3215,0.2277,0.0363",\ +"0.4465,0.4309,0.4152,0.3879,0.3371,0.2395,0.0559",\ +"0.4582,0.4426,0.4309,0.3996,0.3488,0.2551,0.0715",\ +"0.4934,0.4777,0.4621,0.4348,0.3840,0.2863,0.0988",\ +"0.5363,0.5207,0.5051,0.4777,0.4270,0.3332,0.1418",\ +"0.6379,0.6262,0.6105,0.5793,0.5324,0.4348,0.2434",\ +"0.8332,0.8215,0.8059,0.7707,0.7238,0.6301,0.4387"); + } + } +} +pin(B_WEN) { + direction : input ; + capacitance : 0.00324098 ; + max_transition : "0.476" ; + related_power_pin : VDD; + related_ground_pin : VSS; + internal_power() { + when : "B_MEN"; + rise_power("scalar"){ + values (0.0046); + } + fall_power("scalar"){ + values (0.0037); + } + } + internal_power() { + when : "!B_MEN"; + rise_power("scalar"){ + values (0.0041); + } + fall_power("scalar"){ + values (0.0037); + } + } + timing() { + timing_type : setup_rising; + related_pin : "B_CLK"; + when : "B_MEN" + sdf_cond : "B_MEN" + + rise_constraint("SIG2SRAM_constraint_template") { + index_1("0.0056,0.0232,0.0400,0.0728,0.1280,0.2440,0.4760"); + index_2("0.0056,0.0232,0.0400,0.0728,0.1280,0.2440,0.4760"); + values ("0.2043,0.2199,0.2316,0.2629,0.3059,0.4113,0.6066",\ +"0.1887,0.2043,0.2160,0.2473,0.2941,0.3957,0.5949",\ +"0.1691,0.1848,0.2004,0.2316,0.2785,0.3801,0.5754",\ +"0.1379,0.1574,0.1691,0.2004,0.2473,0.3527,0.5480",\ +"0.0910,0.1066,0.1223,0.1535,0.2004,0.2980,0.4973",\ +"-0.0105,0.0051,0.0207,0.0520,0.0949,0.2004,0.3957",\ +"-0.2059,-0.1902,-0.1746,-0.1473,-0.1004,0.0051,0.2004"); + } + + fall_constraint("SIG2SRAM_constraint_template") { + index_1("0.0056,0.0232,0.0400,0.0728,0.1280,0.2440,0.4760"); + index_2("0.0056,0.0232,0.0400,0.0728,0.1280,0.2440,0.4760"); + values ("0.2941,0.3098,0.3215,0.3488,0.4035,0.4973,0.6887",\ +"0.2785,0.2941,0.3059,0.3332,0.3840,0.4816,0.6691",\ +"0.2629,0.2785,0.2902,0.3176,0.3684,0.4660,0.6535",\ +"0.2316,0.2473,0.2590,0.2863,0.3410,0.4348,0.6262",\ +"0.1848,0.2004,0.2121,0.2395,0.2902,0.3879,0.5754",\ +"0.0832,0.0988,0.1105,0.1379,0.1809,0.2746,0.4699",\ +"-0.1121,-0.0965,-0.0848,-0.0535,-0.0066,0.0910,0.2824"); + } + } + + + timing() { + timing_type : hold_rising; + related_pin : "B_CLK"; + when : "B_MEN" + sdf_cond : "B_MEN" + + rise_constraint("SIG2SRAM_constraint_template") { + index_1("0.0056,0.0232,0.0400,0.0728,0.1280,0.2440,0.4760"); + index_2("0.0056,0.0232,0.0400,0.0728,0.1280,0.2440,0.4760"); + values ("0.2473,0.2316,0.2160,0.1887,0.1379,0.0363,-0.1629",\ +"0.2629,0.2473,0.2316,0.2043,0.1535,0.0520,-0.1473",\ +"0.2785,0.2590,0.2434,0.2160,0.1652,0.0676,-0.1355",\ +"0.3098,0.2941,0.2785,0.2473,0.1965,0.0910,-0.1043",\ +"0.3527,0.3371,0.3215,0.2941,0.2434,0.1418,-0.0574",\ +"0.4582,0.4426,0.4270,0.3957,0.3488,0.2434,0.0480",\ +"0.6535,0.6379,0.6184,0.5910,0.5402,0.4426,0.2434"); + } + + fall_constraint("SIG2SRAM_constraint_template") { + index_1("0.0056,0.0232,0.0400,0.0728,0.1280,0.2440,0.4760"); + index_2("0.0056,0.0232,0.0400,0.0728,0.1280,0.2440,0.4760"); + values ("0.2395,0.2238,0.2121,0.1809,0.1301,0.0324,-0.1551",\ +"0.2551,0.2395,0.2277,0.1965,0.1457,0.0480,-0.1395",\ +"0.2668,0.2551,0.2395,0.2082,0.1574,0.0637,-0.1277",\ +"0.3020,0.2863,0.2707,0.2395,0.1887,0.0910,-0.0965",\ +"0.3449,0.3293,0.3176,0.2863,0.2355,0.1379,-0.0496",\ +"0.4504,0.4348,0.4191,0.3879,0.3371,0.2395,0.0559",\ +"0.6457,0.6301,0.6145,0.5871,0.5324,0.4309,0.2512"); + } + } + } +pin(B_REN) { + direction : input ; + capacitance : 0.00381634 ; + max_transition : "0.476" ; + related_power_pin : VDD; + related_ground_pin : VSS; + internal_power() { + when : "B_MEN"; + rise_power("scalar"){ + values (0.0060); + } + fall_power("scalar"){ + values (0.0020); + } + } + internal_power() { + when : "!B_MEN"; + rise_power("scalar"){ + values (0.0061); + } + fall_power("scalar"){ + values (0.0023); + } + } + timing() { + timing_type : setup_rising; + related_pin : "B_CLK"; + when : "B_MEN" + sdf_cond : "B_MEN" + + rise_constraint("SIG2SRAM_constraint_template") { + index_1("0.0056,0.0232,0.0400,0.0728,0.1280,0.2440,0.4760"); + index_2("0.0056,0.0232,0.0400,0.0728,0.1280,0.2440,0.4760"); + values ("-0.0301,-0.0145,0.0012,0.0324,0.0793,0.1809,0.3762",\ +"-0.0457,-0.0301,-0.0145,0.0168,0.0637,0.1613,0.3605",\ +"-0.0574,-0.0418,-0.0262,0.0051,0.0520,0.1496,0.3449",\ +"-0.0926,-0.0730,-0.0574,-0.0262,0.0207,0.1184,0.3137",\ +"-0.1395,-0.1238,-0.1082,-0.0770,-0.0301,0.0715,0.2707",\ +"-0.2410,-0.2254,-0.2098,-0.1746,-0.1355,-0.0340,0.1652",\ +"-0.4402,-0.4207,-0.4051,-0.3738,-0.3270,-0.2293,-0.0340"); + } + + fall_constraint("SIG2SRAM_constraint_template") { + index_1("0.0056,0.0232,0.0400,0.0728,0.1280,0.2440,0.4760"); + index_2("0.0056,0.0232,0.0400,0.0728,0.1280,0.2440,0.4760"); + values ("0.0988,0.1145,0.1262,0.1535,0.2043,0.3020,0.4855",\ +"0.0832,0.0988,0.1105,0.1418,0.1848,0.2824,0.4738",\ +"0.0676,0.0832,0.0949,0.1262,0.1730,0.2668,0.4621",\ +"0.0402,0.0559,0.0676,0.0988,0.1457,0.2434,0.4191",\ +"-0.0105,0.0012,0.0168,0.0480,0.0988,0.1965,0.3840",\ +"-0.1160,-0.0965,-0.0848,-0.0535,-0.0066,0.0988,0.2824",\ +"-0.3113,-0.2957,-0.2801,-0.2527,-0.2059,-0.1043,0.0832"); + } + } + + + timing() { + timing_type : hold_rising; + related_pin : "B_CLK"; + when : "B_MEN" + sdf_cond : "B_MEN" + + rise_constraint("SIG2SRAM_constraint_template") { + index_1("0.0056,0.0232,0.0400,0.0728,0.1280,0.2440,0.4760"); + index_2("0.0056,0.0232,0.0400,0.0728,0.1280,0.2440,0.4760"); + values ("0.2707,0.2551,0.2395,0.2121,0.1613,0.0598,-0.1395",\ +"0.2863,0.2707,0.2551,0.2238,0.1730,0.0715,-0.1238",\ +"0.2980,0.2824,0.2668,0.2395,0.1887,0.0871,-0.1121",\ +"0.3332,0.3176,0.3020,0.2707,0.2199,0.1184,-0.0809",\ +"0.3762,0.3605,0.3449,0.3176,0.2668,0.1613,-0.0340",\ +"0.4816,0.4621,0.4504,0.4191,0.3723,0.2629,0.0715",\ +"0.6770,0.6613,0.6418,0.6184,0.5637,0.4699,0.2629"); + } + + fall_constraint("SIG2SRAM_constraint_template") { + index_1("0.0056,0.0232,0.0400,0.0728,0.1280,0.2440,0.4760"); + index_2("0.0056,0.0232,0.0400,0.0728,0.1280,0.2440,0.4760"); + values ("0.2590,0.2434,0.2316,0.2004,0.1457,0.0520,-0.1355",\ +"0.2746,0.2590,0.2434,0.2160,0.1613,0.0676,-0.1199",\ +"0.2863,0.2707,0.2590,0.2277,0.1730,0.0832,-0.1082",\ +"0.3215,0.3059,0.2902,0.2590,0.2082,0.1105,-0.0770",\ +"0.3645,0.3488,0.3332,0.3059,0.2551,0.1535,-0.0340",\ +"0.4699,0.4543,0.4387,0.4074,0.3605,0.2551,0.0715",\ +"0.6652,0.6496,0.6340,0.6027,0.5520,0.4621,0.2707"); + } + } + } +pin(B_MEN) { + direction : input ; + capacitance : 0.00309605 ; + max_transition : "0.476" ; + related_power_pin : VDD; + related_ground_pin : VSS; + internal_power() { + rise_power("scalar"){ + values (0.0236); + } + fall_power("scalar"){ + values (0.0052); + } + } + timing() { + timing_type : setup_rising; + related_pin : "B_CLK"; + + rise_constraint("SIG2SRAM_constraint_template") { + index_1("0.0056,0.0232,0.0400,0.0728,0.1280,0.2440,0.4760"); + index_2("0.0056,0.0232,0.0400,0.0728,0.1280,0.2440,0.4760"); + values ("0.2043,0.2199,0.2316,0.2668,0.3098,0.4152,0.6066",\ +"0.1887,0.2043,0.2199,0.2512,0.2941,0.3996,0.5949",\ +"0.1730,0.1887,0.2043,0.2355,0.2824,0.3840,0.5793",\ +"0.1418,0.1574,0.1730,0.2043,0.2512,0.3566,0.5480",\ +"0.0949,0.1105,0.1262,0.1574,0.2043,0.3020,0.5051",\ +"-0.0066,0.0090,0.0246,0.0520,0.0988,0.2043,0.3996",\ +"-0.2020,-0.1863,-0.1746,-0.1434,-0.0965,0.0090,0.2082"); + } + + fall_constraint("SIG2SRAM_constraint_template") { + index_1("0.0056,0.0232,0.0400,0.0728,0.1280,0.2440,0.4760"); + index_2("0.0056,0.0232,0.0400,0.0728,0.1280,0.2440,0.4760"); + values ("0.2980,0.3137,0.3254,0.3527,0.4035,0.5012,0.6887",\ +"0.2824,0.2980,0.3098,0.3371,0.3879,0.4855,0.6730",\ +"0.2668,0.2824,0.2941,0.3215,0.3723,0.4699,0.6574",\ +"0.2355,0.2473,0.2629,0.2902,0.3410,0.4387,0.6262",\ +"0.1887,0.2004,0.2160,0.2395,0.2941,0.3918,0.5793",\ +"0.0871,0.1027,0.1145,0.1418,0.1848,0.2746,0.4816",\ +"-0.1082,-0.0965,-0.0809,-0.0496,-0.0027,0.0949,0.2863"); + } + } + + + timing() { + timing_type : hold_rising; + related_pin : "B_CLK"; + + rise_constraint("SIG2SRAM_constraint_template") { + index_1("0.0056,0.0232,0.0400,0.0728,0.1280,0.2440,0.4760"); + index_2("0.0056,0.0232,0.0400,0.0728,0.1280,0.2440,0.4760"); + values ("0.2512,0.2355,0.2199,0.1926,0.1418,0.0402,-0.1590",\ +"0.2668,0.2512,0.2355,0.2082,0.1574,0.0559,-0.1434",\ +"0.2824,0.2629,0.2512,0.2199,0.1691,0.0715,-0.1316",\ +"0.3137,0.2980,0.2824,0.2512,0.2004,0.0988,-0.0965",\ +"0.3566,0.3410,0.3254,0.2980,0.2473,0.1418,-0.0535",\ +"0.4621,0.4426,0.4309,0.3996,0.3527,0.2473,0.0520",\ +"0.6574,0.6418,0.6262,0.5949,0.5441,0.4465,0.2473"); + } + + fall_constraint("SIG2SRAM_constraint_template") { + index_1("0.0056,0.0232,0.0400,0.0728,0.1280,0.2440,0.4760"); + index_2("0.0056,0.0232,0.0400,0.0728,0.1280,0.2440,0.4760"); + values ("0.2395,0.2238,0.2121,0.1809,0.1301,0.0324,-0.1551",\ +"0.2551,0.2434,0.2277,0.1965,0.1457,0.0480,-0.1395",\ +"0.2707,0.2551,0.2395,0.2082,0.1574,0.0637,-0.1277",\ +"0.3020,0.2863,0.2707,0.2434,0.1926,0.0910,-0.0965",\ +"0.3449,0.3332,0.3176,0.2863,0.2355,0.1379,-0.0496",\ +"0.4504,0.4348,0.4230,0.3918,0.3410,0.2434,0.0559",\ +"0.6457,0.6301,0.6145,0.5910,0.5324,0.4387,0.2512"); + } + } + } +bus(B_BM) { + bus_type : D_7_0; + direction : input ; + capacitance : 0.00312518 ; + max_transition : "0.476" ; + pin(B_BM[7:0]) { + related_power_pin : VDD; + related_ground_pin : VSS; + internal_power() { + when : "B_MEN"; + rise_power("scalar"){ + values (0.0299); + } + fall_power("scalar"){ + values (0.0123); + } + } + internal_power() { + when : "!B_MEN"; + rise_power("scalar"){ + values (0.0316); + } + fall_power("scalar"){ + values (0.0122); + } + } + } + timing() { + timing_type : setup_rising; + related_pin : "B_CLK"; + when : "(B_WEN & B_MEN)" + sdf_cond : "B_RW_ACCESS" + + rise_constraint("SIG2SRAM_constraint_template") { + index_1("0.0056,0.0232,0.0400,0.0728,0.1280,0.2440,0.4760"); + index_2("0.0056,0.0232,0.0400,0.0728,0.1280,0.2440,0.4760"); + values ("-0.2885,-0.2729,-0.2602,-0.2270,-0.1782,-0.0795,0.1138",\ +"-0.2935,-0.2779,-0.2652,-0.2320,-0.1832,-0.0845,0.1088",\ +"-0.2980,-0.2824,-0.2697,-0.2365,-0.1876,-0.0890,0.1043",\ +"-0.3071,-0.2915,-0.2788,-0.2456,-0.1968,-0.0981,0.0952",\ +"-0.3143,-0.2987,-0.2860,-0.2528,-0.2040,-0.1053,0.0880",\ +"-0.3440,-0.3283,-0.3157,-0.2825,-0.2336,-0.1350,0.0584",\ +"-0.4020,-0.3864,-0.3737,-0.3405,-0.2917,-0.1931,0.0003"); + } + + fall_constraint("SIG2SRAM_constraint_template") { + index_1("0.0056,0.0232,0.0400,0.0728,0.1280,0.2440,0.4760"); + index_2("0.0056,0.0232,0.0400,0.0728,0.1280,0.2440,0.4760"); + values ("-0.2543,-0.2397,-0.2260,-0.1977,-0.1479,-0.0493,0.1304",\ +"-0.2593,-0.2447,-0.2310,-0.2027,-0.1529,-0.0543,0.1254",\ +"-0.2638,-0.2492,-0.2355,-0.2072,-0.1574,-0.0587,0.1209",\ +"-0.2729,-0.2583,-0.2446,-0.2163,-0.1665,-0.0679,0.1118",\ +"-0.2801,-0.2655,-0.2518,-0.2235,-0.1737,-0.0751,0.1046",\ +"-0.3098,-0.2951,-0.2815,-0.2532,-0.2033,-0.1047,0.0750",\ +"-0.3679,-0.3532,-0.3395,-0.3112,-0.2614,-0.1628,0.0169"); + } + } + + + timing() { + timing_type : hold_rising; + related_pin : "B_CLK"; + when : "(B_WEN & B_MEN)" + sdf_cond : "B_RW_ACCESS" + + rise_constraint("SIG2SRAM_constraint_template") { + index_1("0.0056,0.0232,0.0400,0.0728,0.1280,0.2440,0.4760"); + index_2("0.0056,0.0232,0.0400,0.0728,0.1280,0.2440,0.4760"); + values ("0.3976,0.3820,0.3693,0.3361,0.2882,0.1886,-0.0057",\ +"0.4026,0.3870,0.3743,0.3411,0.2932,0.1936,-0.0007",\ +"0.4071,0.3915,0.3788,0.3456,0.2977,0.1981,0.0038",\ +"0.4162,0.4006,0.3879,0.3547,0.3068,0.2072,0.0129",\ +"0.4234,0.4078,0.3951,0.3619,0.3140,0.2144,0.0201",\ +"0.4531,0.4374,0.4247,0.3915,0.3437,0.2441,0.0497",\ +"0.5111,0.4955,0.4828,0.4496,0.4018,0.3021,0.1078"); + } + + fall_constraint("SIG2SRAM_constraint_template") { + index_1("0.0056,0.0232,0.0400,0.0728,0.1280,0.2440,0.4760"); + index_2("0.0056,0.0232,0.0400,0.0728,0.1280,0.2440,0.4760"); + values ("0.3566,0.3419,0.3273,0.2990,0.2482,0.1564,-0.0282",\ +"0.3616,0.3469,0.3323,0.3040,0.2532,0.1614,-0.0232",\ +"0.3661,0.3514,0.3368,0.3084,0.2577,0.1659,-0.0187",\ +"0.3752,0.3605,0.3459,0.3176,0.2668,0.1750,-0.0096",\ +"0.3824,0.3677,0.3531,0.3248,0.2740,0.1822,-0.0024",\ +"0.4120,0.3974,0.3828,0.3544,0.3037,0.2119,0.0273",\ +"0.4701,0.4555,0.4408,0.4125,0.3617,0.2699,0.0854"); + } + } +} + pin(B_CLK) { + direction : input; + capacitance : 0.00380014; + max_transition : "0.476"; + clock : "true" ; + pin_func_type : active_rising ; + + timing () { + timing_type : "min_pulse_width"; + related_pin : "B_CLK"; + rise_constraint("CLKTRAN_constraint_template") { + index_1("0.0056,0.476"); + values("0.21,0.21"); + } + } + + related_power_pin : VDD; + related_ground_pin : VSS; + + internal_power() { + when : "!B_MEN & !B_WEN & !B_REN"; + rise_power("scalar"){ + values (0); + } + fall_power("scalar"){ + values (0); + } + } + internal_power() { + when : "!B_MEN & B_WEN & !B_REN"; + rise_power("scalar"){ + values (0.4861); + } + fall_power("scalar"){ + values (0); + } + } + internal_power() { + when : "B_MEN & B_WEN & !B_REN"; + rise_power("scalar"){ + values (10.9594); + } + fall_power("scalar"){ + values (0); + } + } + internal_power() { + when : "B_MEN & B_WEN & B_REN"; + rise_power("scalar"){ + values (11.6067); + } + fall_power("scalar"){ + values (0); + } + } + internal_power() { + when : "B_MEN & !B_WEN & B_REN"; + rise_power("scalar"){ + values (8.2850); + } + fall_power("scalar"){ + values (0); + } + } + internal_power() { + when : "!B_MEN & !B_WEN & B_REN"; + rise_power("scalar"){ + values (0.2964); + } + fall_power("scalar"){ + values (0); + } + } + internal_power() { + when : "!B_MEN & B_WEN & B_REN"; + rise_power("scalar"){ + values (0.5323); + } + fall_power("scalar"){ + values (0); + } + } + internal_power() { + when : "B_MEN & !B_WEN & !B_REN"; + rise_power("scalar"){ + values (0); + } + fall_power("scalar"){ + values (0); + } + } + } + bus(B_DIN) { + bus_type : D_7_0; + direction : input ; + capacitance : 0.00461776 ; + memory_write() { + address : B_ADDR ; + clocked_on : B_CLK; + } + + max_transition : "0.476" ; + pin(B_DIN[7:0]) { + related_power_pin : VDD; + related_ground_pin : VSS; + internal_power() { + when : "B_MEN"; + rise_power("scalar"){ + values (0.0299); + } + fall_power("scalar"){ + values (0.0123); + } + } + internal_power() { + when : "!B_MEN"; + rise_power("scalar"){ + values (0.0316); + } + fall_power("scalar"){ + values (0.0122); + } + } + } + timing() { + timing_type : setup_rising; + related_pin : "B_CLK"; + when : "(B_WEN & B_MEN)"; + sdf_cond : "B_W_ACCESS"; + + rise_constraint("SIG2SRAM_constraint_template") { + index_1("0.0056,0.0232,0.0400,0.0728,0.1280,0.2440,0.4760"); + index_2("0.0056,0.0232,0.0400,0.0728,0.1280,0.2440,0.4760"); + values ("-0.2885,-0.2729,-0.2602,-0.2270,-0.1782,-0.0795,0.1138",\ +"-0.2935,-0.2779,-0.2652,-0.2320,-0.1832,-0.0845,0.1088",\ +"-0.2980,-0.2824,-0.2697,-0.2365,-0.1876,-0.0890,0.1043",\ +"-0.3071,-0.2915,-0.2788,-0.2456,-0.1968,-0.0981,0.0952",\ +"-0.3143,-0.2987,-0.2860,-0.2528,-0.2040,-0.1053,0.0880",\ +"-0.3440,-0.3283,-0.3157,-0.2825,-0.2336,-0.1350,0.0584",\ +"-0.4020,-0.3864,-0.3737,-0.3405,-0.2917,-0.1931,0.0003"); + } + + fall_constraint("SIG2SRAM_constraint_template") { + index_1("0.0056,0.0232,0.0400,0.0728,0.1280,0.2440,0.4760"); + index_2("0.0056,0.0232,0.0400,0.0728,0.1280,0.2440,0.4760"); + values ("-0.2543,-0.2397,-0.2260,-0.1977,-0.1479,-0.0493,0.1304",\ +"-0.2593,-0.2447,-0.2310,-0.2027,-0.1529,-0.0543,0.1254",\ +"-0.2638,-0.2492,-0.2355,-0.2072,-0.1574,-0.0587,0.1209",\ +"-0.2729,-0.2583,-0.2446,-0.2163,-0.1665,-0.0679,0.1118",\ +"-0.2801,-0.2655,-0.2518,-0.2235,-0.1737,-0.0751,0.1046",\ +"-0.3098,-0.2951,-0.2815,-0.2532,-0.2033,-0.1047,0.0750",\ +"-0.3679,-0.3532,-0.3395,-0.3112,-0.2614,-0.1628,0.0169"); + } + } + + timing() { + timing_type : hold_rising; + related_pin : "B_CLK"; + when : "(B_WEN & B_MEN)"; + sdf_cond : "B_W_ACCESS"; + + rise_constraint("SIG2SRAM_constraint_template") { + index_1("0.0056,0.0232,0.0400,0.0728,0.1280,0.2440,0.4760"); + index_2("0.0056,0.0232,0.0400,0.0728,0.1280,0.2440,0.4760"); + values ("0.3976,0.3820,0.3693,0.3361,0.2882,0.1886,-0.0057",\ +"0.4026,0.3870,0.3743,0.3411,0.2932,0.1936,-0.0007",\ +"0.4071,0.3915,0.3788,0.3456,0.2977,0.1981,0.0038",\ +"0.4162,0.4006,0.3879,0.3547,0.3068,0.2072,0.0129",\ +"0.4234,0.4078,0.3951,0.3619,0.3140,0.2144,0.0201",\ +"0.4531,0.4374,0.4247,0.3915,0.3437,0.2441,0.0497",\ +"0.5111,0.4955,0.4828,0.4496,0.4018,0.3021,0.1078"); + } + + fall_constraint("SIG2SRAM_constraint_template") { + index_1("0.0056,0.0232,0.0400,0.0728,0.1280,0.2440,0.4760"); + index_2("0.0056,0.0232,0.0400,0.0728,0.1280,0.2440,0.4760"); + values ("0.3566,0.3419,0.3273,0.2990,0.2482,0.1564,-0.0282",\ +"0.3616,0.3469,0.3323,0.3040,0.2532,0.1614,-0.0232",\ +"0.3661,0.3514,0.3368,0.3084,0.2577,0.1659,-0.0187",\ +"0.3752,0.3605,0.3459,0.3176,0.2668,0.1750,-0.0096",\ +"0.3824,0.3677,0.3531,0.3248,0.2740,0.1822,-0.0024",\ +"0.4120,0.3974,0.3828,0.3544,0.3037,0.2119,0.0273",\ +"0.4701,0.4555,0.4408,0.4125,0.3617,0.2699,0.0854"); + } + } + } + + pin(B_BIST_EN) { + direction : input ; + capacitance : 0.00401111 ; + max_transition : "1" ; + related_power_pin : VDD; + related_ground_pin : VSS; + internal_power() { + rise_power("scalar") { + values (0); + } + fall_power("scalar") { + values (0); + } + } + } + +bus(B_BIST_ADDR) { + bus_type : A_7_0; + direction : input ; + capacitance : 0.0121077 ; + pin(B_BIST_ADDR[0]) { + capacitance : 0.00570093 ; + } + pin(B_BIST_ADDR[1]) { + capacitance : 0.00764555 ; + } + pin(B_BIST_ADDR[2]) { + capacitance : 0.0105375 ; + } + pin(B_BIST_ADDR[3]) { + capacitance : 0.0067894 ; + } + pin(B_BIST_ADDR[4]) { + capacitance : 0.00630967 ; + } + pin(B_BIST_ADDR[5]) { + capacitance : 0.0104132 ; + } + pin(B_BIST_ADDR[6]) { + capacitance : 0.0131402 ; + } + max_transition : "0.476" ; + pin(B_BIST_ADDR[7:0]) { + related_power_pin : VDD; + related_ground_pin : VSS; + internal_power() { + when : "B_BIST_MEN"; + rise_power("scalar"){ + values (0.0113); + } + fall_power("scalar"){ + values (0.0053); + } + } + internal_power() { + when : "!B_BIST_MEN"; + rise_power("scalar"){ + values (0.0194); + } + fall_power("scalar"){ + values (0.0005); + } + } + } + timing() { + timing_type : setup_rising; + related_pin : "B_BIST_CLK"; + when : "((B_BIST_WEN | B_BIST_REN)& B_BIST_MEN)" + sdf_cond : "B_BIST_RW_ACCESS" + + rise_constraint("SIG2SRAM_constraint_template") { + index_1("0.0056,0.0232,0.0400,0.0728,0.1280,0.2440,0.4760"); + index_2("0.0056,0.0232,0.0400,0.0728,0.1280,0.2440,0.4760"); + values ("-0.4168,-0.3973,-0.3855,-0.3543,-0.3074,-0.2020,-0.0027",\ +"-0.4324,-0.4129,-0.4012,-0.3699,-0.3191,-0.2176,-0.0184",\ +"-0.4441,-0.4285,-0.4129,-0.3816,-0.3309,-0.2293,-0.0301",\ +"-0.4793,-0.4598,-0.4441,-0.4129,-0.3660,-0.2645,-0.0652",\ +"-0.5223,-0.5066,-0.4910,-0.4598,-0.4129,-0.3074,-0.1121",\ +"-0.6199,-0.6082,-0.5926,-0.5613,-0.5145,-0.4129,-0.2137",\ +"-0.8191,-0.8074,-0.7840,-0.7566,-0.7098,-0.6082,-0.4051"); + } + + fall_constraint("SIG2SRAM_constraint_template") { + index_1("0.0056,0.0232,0.0400,0.0728,0.1280,0.2440,0.4760"); + index_2("0.0056,0.0232,0.0400,0.0728,0.1280,0.2440,0.4760"); + values ("-0.3309,-0.3113,-0.2996,-0.2684,-0.2176,-0.1238,0.0637",\ +"-0.3465,-0.3309,-0.3152,-0.2840,-0.2332,-0.1395,0.0480",\ +"-0.3582,-0.3426,-0.3270,-0.2996,-0.2488,-0.1512,0.0324",\ +"-0.3895,-0.3738,-0.3582,-0.3309,-0.2801,-0.1863,0.0051",\ +"-0.4363,-0.4207,-0.4051,-0.3777,-0.3230,-0.2293,-0.0379",\ +"-0.5379,-0.5223,-0.5066,-0.4793,-0.4285,-0.3309,-0.1434",\ +"-0.7332,-0.7176,-0.7020,-0.6746,-0.6238,-0.5262,-0.3387"); + } + } + + + timing() { + timing_type : hold_rising; + related_pin : "B_BIST_CLK"; + when : "((B_BIST_WEN | B_BIST_REN)& B_BIST_MEN)" + sdf_cond : "B_BIST_RW_ACCESS" + + rise_constraint("SIG2SRAM_constraint_template") { + index_1("0.0056,0.0232,0.0400,0.0728,0.1280,0.2440,0.4760"); + index_2("0.0056,0.0232,0.0400,0.0728,0.1280,0.2440,0.4760"); + values ("0.5246,0.5051,0.4895,0.4582,0.4113,0.3059,0.1066",\ +"0.5402,0.5207,0.5051,0.4777,0.4270,0.3215,0.1223",\ +"0.5520,0.5324,0.5168,0.4895,0.4387,0.3371,0.1340",\ +"0.5832,0.5676,0.5520,0.5207,0.4738,0.3684,0.1691",\ +"0.6301,0.6105,0.5949,0.5676,0.5168,0.4113,0.2160",\ +"0.7316,0.7121,0.7004,0.6691,0.6223,0.5168,0.3176",\ +"0.9270,0.9230,0.8957,0.8645,0.8137,0.7121,0.5168"); + } + + fall_constraint("SIG2SRAM_constraint_template") { + index_1("0.0056,0.0232,0.0400,0.0728,0.1280,0.2440,0.4760"); + index_2("0.0056,0.0232,0.0400,0.0728,0.1280,0.2440,0.4760"); + values ("0.4309,0.4152,0.4035,0.3684,0.3215,0.2277,0.0363",\ +"0.4465,0.4309,0.4152,0.3879,0.3371,0.2395,0.0559",\ +"0.4582,0.4426,0.4309,0.3996,0.3488,0.2551,0.0715",\ +"0.4934,0.4777,0.4621,0.4348,0.3840,0.2863,0.0988",\ +"0.5363,0.5207,0.5051,0.4777,0.4270,0.3332,0.1418",\ +"0.6379,0.6262,0.6105,0.5793,0.5324,0.4348,0.2434",\ +"0.8332,0.8215,0.8059,0.7707,0.7238,0.6301,0.4387"); + } + } +} +pin(B_BIST_WEN) { + direction : input ; + capacitance : 0.00324098 ; + max_transition : "0.476" ; + related_power_pin : VDD; + related_ground_pin : VSS; + internal_power() { + when : "B_BIST_MEN"; + rise_power("scalar"){ + values (0.0046); + } + fall_power("scalar"){ + values (0.0037); + } + } + internal_power() { + when : "!B_BIST_MEN"; + rise_power("scalar"){ + values (0.0041); + } + fall_power("scalar"){ + values (0.0037); + } + } + timing() { + timing_type : setup_rising; + related_pin : "B_BIST_CLK"; + when : "B_BIST_MEN" + sdf_cond : "B_BIST_MEN" + + rise_constraint("SIG2SRAM_constraint_template") { + index_1("0.0056,0.0232,0.0400,0.0728,0.1280,0.2440,0.4760"); + index_2("0.0056,0.0232,0.0400,0.0728,0.1280,0.2440,0.4760"); + values ("0.2043,0.2199,0.2316,0.2629,0.3059,0.4113,0.6066",\ +"0.1887,0.2043,0.2160,0.2473,0.2941,0.3957,0.5949",\ +"0.1691,0.1848,0.2004,0.2316,0.2785,0.3801,0.5754",\ +"0.1379,0.1574,0.1691,0.2004,0.2473,0.3527,0.5480",\ +"0.0910,0.1066,0.1223,0.1535,0.2004,0.2980,0.4973",\ +"-0.0105,0.0051,0.0207,0.0520,0.0949,0.2004,0.3957",\ +"-0.2059,-0.1902,-0.1746,-0.1473,-0.1004,0.0051,0.2004"); + } + + fall_constraint("SIG2SRAM_constraint_template") { + index_1("0.0056,0.0232,0.0400,0.0728,0.1280,0.2440,0.4760"); + index_2("0.0056,0.0232,0.0400,0.0728,0.1280,0.2440,0.4760"); + values ("0.2941,0.3098,0.3215,0.3488,0.4035,0.4973,0.6887",\ +"0.2785,0.2941,0.3059,0.3332,0.3840,0.4816,0.6691",\ +"0.2629,0.2785,0.2902,0.3176,0.3684,0.4660,0.6535",\ +"0.2316,0.2473,0.2590,0.2863,0.3410,0.4348,0.6262",\ +"0.1848,0.2004,0.2121,0.2395,0.2902,0.3879,0.5754",\ +"0.0832,0.0988,0.1105,0.1379,0.1809,0.2746,0.4699",\ +"-0.1121,-0.0965,-0.0848,-0.0535,-0.0066,0.0910,0.2824"); + } + } + + + timing() { + timing_type : hold_rising; + related_pin : "B_BIST_CLK"; + when : "B_BIST_MEN" + sdf_cond : "B_BIST_MEN" + + rise_constraint("SIG2SRAM_constraint_template") { + index_1("0.0056,0.0232,0.0400,0.0728,0.1280,0.2440,0.4760"); + index_2("0.0056,0.0232,0.0400,0.0728,0.1280,0.2440,0.4760"); + values ("0.2473,0.2316,0.2160,0.1887,0.1379,0.0363,-0.1629",\ +"0.2629,0.2473,0.2316,0.2043,0.1535,0.0520,-0.1473",\ +"0.2785,0.2590,0.2434,0.2160,0.1652,0.0676,-0.1355",\ +"0.3098,0.2941,0.2785,0.2473,0.1965,0.0910,-0.1043",\ +"0.3527,0.3371,0.3215,0.2941,0.2434,0.1418,-0.0574",\ +"0.4582,0.4426,0.4270,0.3957,0.3488,0.2434,0.0480",\ +"0.6535,0.6379,0.6184,0.5910,0.5402,0.4426,0.2434"); + } + + fall_constraint("SIG2SRAM_constraint_template") { + index_1("0.0056,0.0232,0.0400,0.0728,0.1280,0.2440,0.4760"); + index_2("0.0056,0.0232,0.0400,0.0728,0.1280,0.2440,0.4760"); + values ("0.2395,0.2238,0.2121,0.1809,0.1301,0.0324,-0.1551",\ +"0.2551,0.2395,0.2277,0.1965,0.1457,0.0480,-0.1395",\ +"0.2668,0.2551,0.2395,0.2082,0.1574,0.0637,-0.1277",\ +"0.3020,0.2863,0.2707,0.2395,0.1887,0.0910,-0.0965",\ +"0.3449,0.3293,0.3176,0.2863,0.2355,0.1379,-0.0496",\ +"0.4504,0.4348,0.4191,0.3879,0.3371,0.2395,0.0559",\ +"0.6457,0.6301,0.6145,0.5871,0.5324,0.4309,0.2512"); + } + } + } +pin(B_BIST_REN) { + direction : input ; + capacitance : 0.00381634 ; + max_transition : "0.476" ; + related_power_pin : VDD; + related_ground_pin : VSS; + internal_power() { + when : "B_BIST_MEN"; + rise_power("scalar"){ + values (0.0060); + } + fall_power("scalar"){ + values (0.0020); + } + } + internal_power() { + when : "!B_BIST_MEN"; + rise_power("scalar"){ + values (0.0061); + } + fall_power("scalar"){ + values (0.0023); + } + } + timing() { + timing_type : setup_rising; + related_pin : "B_BIST_CLK"; + when : "B_BIST_MEN" + sdf_cond : "B_BIST_MEN" + + rise_constraint("SIG2SRAM_constraint_template") { + index_1("0.0056,0.0232,0.0400,0.0728,0.1280,0.2440,0.4760"); + index_2("0.0056,0.0232,0.0400,0.0728,0.1280,0.2440,0.4760"); + values ("-0.0301,-0.0145,0.0012,0.0324,0.0793,0.1809,0.3762",\ +"-0.0457,-0.0301,-0.0145,0.0168,0.0637,0.1613,0.3605",\ +"-0.0574,-0.0418,-0.0262,0.0051,0.0520,0.1496,0.3449",\ +"-0.0926,-0.0730,-0.0574,-0.0262,0.0207,0.1184,0.3137",\ +"-0.1395,-0.1238,-0.1082,-0.0770,-0.0301,0.0715,0.2707",\ +"-0.2410,-0.2254,-0.2098,-0.1746,-0.1355,-0.0340,0.1652",\ +"-0.4402,-0.4207,-0.4051,-0.3738,-0.3270,-0.2293,-0.0340"); + } + + fall_constraint("SIG2SRAM_constraint_template") { + index_1("0.0056,0.0232,0.0400,0.0728,0.1280,0.2440,0.4760"); + index_2("0.0056,0.0232,0.0400,0.0728,0.1280,0.2440,0.4760"); + values ("0.0988,0.1145,0.1262,0.1535,0.2043,0.3020,0.4855",\ +"0.0832,0.0988,0.1105,0.1418,0.1848,0.2824,0.4738",\ +"0.0676,0.0832,0.0949,0.1262,0.1730,0.2668,0.4621",\ +"0.0402,0.0559,0.0676,0.0988,0.1457,0.2434,0.4191",\ +"-0.0105,0.0012,0.0168,0.0480,0.0988,0.1965,0.3840",\ +"-0.1160,-0.0965,-0.0848,-0.0535,-0.0066,0.0988,0.2824",\ +"-0.3113,-0.2957,-0.2801,-0.2527,-0.2059,-0.1043,0.0832"); + } + } + + + timing() { + timing_type : hold_rising; + related_pin : "B_BIST_CLK"; + when : "B_BIST_MEN" + sdf_cond : "B_BIST_MEN" + + rise_constraint("SIG2SRAM_constraint_template") { + index_1("0.0056,0.0232,0.0400,0.0728,0.1280,0.2440,0.4760"); + index_2("0.0056,0.0232,0.0400,0.0728,0.1280,0.2440,0.4760"); + values ("0.2707,0.2551,0.2395,0.2121,0.1613,0.0598,-0.1395",\ +"0.2863,0.2707,0.2551,0.2238,0.1730,0.0715,-0.1238",\ +"0.2980,0.2824,0.2668,0.2395,0.1887,0.0871,-0.1121",\ +"0.3332,0.3176,0.3020,0.2707,0.2199,0.1184,-0.0809",\ +"0.3762,0.3605,0.3449,0.3176,0.2668,0.1613,-0.0340",\ +"0.4816,0.4621,0.4504,0.4191,0.3723,0.2629,0.0715",\ +"0.6770,0.6613,0.6418,0.6184,0.5637,0.4699,0.2629"); + } + + fall_constraint("SIG2SRAM_constraint_template") { + index_1("0.0056,0.0232,0.0400,0.0728,0.1280,0.2440,0.4760"); + index_2("0.0056,0.0232,0.0400,0.0728,0.1280,0.2440,0.4760"); + values ("0.2590,0.2434,0.2316,0.2004,0.1457,0.0520,-0.1355",\ +"0.2746,0.2590,0.2434,0.2160,0.1613,0.0676,-0.1199",\ +"0.2863,0.2707,0.2590,0.2277,0.1730,0.0832,-0.1082",\ +"0.3215,0.3059,0.2902,0.2590,0.2082,0.1105,-0.0770",\ +"0.3645,0.3488,0.3332,0.3059,0.2551,0.1535,-0.0340",\ +"0.4699,0.4543,0.4387,0.4074,0.3605,0.2551,0.0715",\ +"0.6652,0.6496,0.6340,0.6027,0.5520,0.4621,0.2707"); + } + } + } +pin(B_BIST_MEN) { + direction : input ; + capacitance : 0.00309605 ; + max_transition : "0.476" ; + related_power_pin : VDD; + related_ground_pin : VSS; + internal_power() { + rise_power("scalar"){ + values (0.0236); + } + fall_power("scalar"){ + values (0.0052); + } + } + timing() { + timing_type : setup_rising; + related_pin : "B_BIST_CLK"; + + rise_constraint("SIG2SRAM_constraint_template") { + index_1("0.0056,0.0232,0.0400,0.0728,0.1280,0.2440,0.4760"); + index_2("0.0056,0.0232,0.0400,0.0728,0.1280,0.2440,0.4760"); + values ("0.2043,0.2199,0.2316,0.2668,0.3098,0.4152,0.6066",\ +"0.1887,0.2043,0.2199,0.2512,0.2941,0.3996,0.5949",\ +"0.1730,0.1887,0.2043,0.2355,0.2824,0.3840,0.5793",\ +"0.1418,0.1574,0.1730,0.2043,0.2512,0.3566,0.5480",\ +"0.0949,0.1105,0.1262,0.1574,0.2043,0.3020,0.5051",\ +"-0.0066,0.0090,0.0246,0.0520,0.0988,0.2043,0.3996",\ +"-0.2020,-0.1863,-0.1746,-0.1434,-0.0965,0.0090,0.2082"); + } + + fall_constraint("SIG2SRAM_constraint_template") { + index_1("0.0056,0.0232,0.0400,0.0728,0.1280,0.2440,0.4760"); + index_2("0.0056,0.0232,0.0400,0.0728,0.1280,0.2440,0.4760"); + values ("0.2980,0.3137,0.3254,0.3527,0.4035,0.5012,0.6887",\ +"0.2824,0.2980,0.3098,0.3371,0.3879,0.4855,0.6730",\ +"0.2668,0.2824,0.2941,0.3215,0.3723,0.4699,0.6574",\ +"0.2355,0.2473,0.2629,0.2902,0.3410,0.4387,0.6262",\ +"0.1887,0.2004,0.2160,0.2395,0.2941,0.3918,0.5793",\ +"0.0871,0.1027,0.1145,0.1418,0.1848,0.2746,0.4816",\ +"-0.1082,-0.0965,-0.0809,-0.0496,-0.0027,0.0949,0.2863"); + } + } + + + timing() { + timing_type : hold_rising; + related_pin : "B_BIST_CLK"; + + rise_constraint("SIG2SRAM_constraint_template") { + index_1("0.0056,0.0232,0.0400,0.0728,0.1280,0.2440,0.4760"); + index_2("0.0056,0.0232,0.0400,0.0728,0.1280,0.2440,0.4760"); + values ("0.2512,0.2355,0.2199,0.1926,0.1418,0.0402,-0.1590",\ +"0.2668,0.2512,0.2355,0.2082,0.1574,0.0559,-0.1434",\ +"0.2824,0.2629,0.2512,0.2199,0.1691,0.0715,-0.1316",\ +"0.3137,0.2980,0.2824,0.2512,0.2004,0.0988,-0.0965",\ +"0.3566,0.3410,0.3254,0.2980,0.2473,0.1418,-0.0535",\ +"0.4621,0.4426,0.4309,0.3996,0.3527,0.2473,0.0520",\ +"0.6574,0.6418,0.6262,0.5949,0.5441,0.4465,0.2473"); + } + + fall_constraint("SIG2SRAM_constraint_template") { + index_1("0.0056,0.0232,0.0400,0.0728,0.1280,0.2440,0.4760"); + index_2("0.0056,0.0232,0.0400,0.0728,0.1280,0.2440,0.4760"); + values ("0.2395,0.2238,0.2121,0.1809,0.1301,0.0324,-0.1551",\ +"0.2551,0.2434,0.2277,0.1965,0.1457,0.0480,-0.1395",\ +"0.2707,0.2551,0.2395,0.2082,0.1574,0.0637,-0.1277",\ +"0.3020,0.2863,0.2707,0.2434,0.1926,0.0910,-0.0965",\ +"0.3449,0.3332,0.3176,0.2863,0.2355,0.1379,-0.0496",\ +"0.4504,0.4348,0.4230,0.3918,0.3410,0.2434,0.0559",\ +"0.6457,0.6301,0.6145,0.5910,0.5324,0.4387,0.2512"); + } + } + } +bus(B_BIST_BM) { + bus_type : D_7_0; + direction : input ; + capacitance : 0.00275526 ; + max_transition : "0.476" ; + pin(B_BIST_BM[7:0]) { + related_power_pin : VDD; + related_ground_pin : VSS; + internal_power() { + when : "B_BIST_MEN"; + rise_power("scalar"){ + values (0.0299); + } + fall_power("scalar"){ + values (0.0123); + } + } + internal_power() { + when : "!B_BIST_MEN"; + rise_power("scalar"){ + values (0.0316); + } + fall_power("scalar"){ + values (0.0122); + } + } + } + timing() { + timing_type : setup_rising; + related_pin : "B_BIST_CLK"; + when : "(B_BIST_WEN & B_BIST_MEN)" + sdf_cond : "B_BIST_RW_ACCESS" + + rise_constraint("SIG2SRAM_constraint_template") { + index_1("0.0056,0.0232,0.0400,0.0728,0.1280,0.2440,0.4760"); + index_2("0.0056,0.0232,0.0400,0.0728,0.1280,0.2440,0.4760"); + values ("-0.2885,-0.2729,-0.2602,-0.2270,-0.1782,-0.0795,0.1138",\ +"-0.2935,-0.2779,-0.2652,-0.2320,-0.1832,-0.0845,0.1088",\ +"-0.2980,-0.2824,-0.2697,-0.2365,-0.1876,-0.0890,0.1043",\ +"-0.3071,-0.2915,-0.2788,-0.2456,-0.1968,-0.0981,0.0952",\ +"-0.3143,-0.2987,-0.2860,-0.2528,-0.2040,-0.1053,0.0880",\ +"-0.3440,-0.3283,-0.3157,-0.2825,-0.2336,-0.1350,0.0584",\ +"-0.4020,-0.3864,-0.3737,-0.3405,-0.2917,-0.1931,0.0003"); + } + + fall_constraint("SIG2SRAM_constraint_template") { + index_1("0.0056,0.0232,0.0400,0.0728,0.1280,0.2440,0.4760"); + index_2("0.0056,0.0232,0.0400,0.0728,0.1280,0.2440,0.4760"); + values ("-0.2543,-0.2397,-0.2260,-0.1977,-0.1479,-0.0493,0.1304",\ +"-0.2593,-0.2447,-0.2310,-0.2027,-0.1529,-0.0543,0.1254",\ +"-0.2638,-0.2492,-0.2355,-0.2072,-0.1574,-0.0587,0.1209",\ +"-0.2729,-0.2583,-0.2446,-0.2163,-0.1665,-0.0679,0.1118",\ +"-0.2801,-0.2655,-0.2518,-0.2235,-0.1737,-0.0751,0.1046",\ +"-0.3098,-0.2951,-0.2815,-0.2532,-0.2033,-0.1047,0.0750",\ +"-0.3679,-0.3532,-0.3395,-0.3112,-0.2614,-0.1628,0.0169"); + } + } + + + timing() { + timing_type : hold_rising; + related_pin : "B_BIST_CLK"; + when : "(B_BIST_WEN & B_BIST_MEN)" + sdf_cond : "B_BIST_RW_ACCESS" + + rise_constraint("SIG2SRAM_constraint_template") { + index_1("0.0056,0.0232,0.0400,0.0728,0.1280,0.2440,0.4760"); + index_2("0.0056,0.0232,0.0400,0.0728,0.1280,0.2440,0.4760"); + values ("0.3976,0.3820,0.3693,0.3361,0.2882,0.1886,-0.0057",\ +"0.4026,0.3870,0.3743,0.3411,0.2932,0.1936,-0.0007",\ +"0.4071,0.3915,0.3788,0.3456,0.2977,0.1981,0.0038",\ +"0.4162,0.4006,0.3879,0.3547,0.3068,0.2072,0.0129",\ +"0.4234,0.4078,0.3951,0.3619,0.3140,0.2144,0.0201",\ +"0.4531,0.4374,0.4247,0.3915,0.3437,0.2441,0.0497",\ +"0.5111,0.4955,0.4828,0.4496,0.4018,0.3021,0.1078"); + } + + fall_constraint("SIG2SRAM_constraint_template") { + index_1("0.0056,0.0232,0.0400,0.0728,0.1280,0.2440,0.4760"); + index_2("0.0056,0.0232,0.0400,0.0728,0.1280,0.2440,0.4760"); + values ("0.3566,0.3419,0.3273,0.2990,0.2482,0.1564,-0.0282",\ +"0.3616,0.3469,0.3323,0.3040,0.2532,0.1614,-0.0232",\ +"0.3661,0.3514,0.3368,0.3084,0.2577,0.1659,-0.0187",\ +"0.3752,0.3605,0.3459,0.3176,0.2668,0.1750,-0.0096",\ +"0.3824,0.3677,0.3531,0.3248,0.2740,0.1822,-0.0024",\ +"0.4120,0.3974,0.3828,0.3544,0.3037,0.2119,0.0273",\ +"0.4701,0.4555,0.4408,0.4125,0.3617,0.2699,0.0854"); + } + } +} + pin(B_BIST_CLK) { + direction : input; + capacitance : 0.00380014; + max_transition : "0.476"; + clock : "true" ; + pin_func_type : active_rising ; + + timing () { + timing_type : "min_pulse_width"; + related_pin : "B_BIST_CLK"; + rise_constraint("CLKTRAN_constraint_template") { + index_1("0.0056,0.476"); + values("0.21,0.21"); + } + } + + related_power_pin : VDD; + related_ground_pin : VSS; + + internal_power() { + when : "!B_BIST_MEN & !B_BIST_WEN & !B_BIST_REN"; + rise_power("scalar"){ + values (0); + } + fall_power("scalar"){ + values (0); + } + } + internal_power() { + when : "!B_BIST_MEN & B_BIST_WEN & !B_BIST_REN"; + rise_power("scalar"){ + values (0.4861); + } + fall_power("scalar"){ + values (0); + } + } + internal_power() { + when : "B_BIST_MEN & B_BIST_WEN & !B_BIST_REN"; + rise_power("scalar"){ + values (10.9594); + } + fall_power("scalar"){ + values (0); + } + } + internal_power() { + when : "B_BIST_MEN & B_BIST_WEN & B_BIST_REN"; + rise_power("scalar"){ + values (11.6067); + } + fall_power("scalar"){ + values (0); + } + } + internal_power() { + when : "B_BIST_MEN & !B_BIST_WEN & B_BIST_REN"; + rise_power("scalar"){ + values (8.2850); + } + fall_power("scalar"){ + values (0); + } + } + internal_power() { + when : "!B_BIST_MEN & !B_BIST_WEN & B_BIST_REN"; + rise_power("scalar"){ + values (0.2964); + } + fall_power("scalar"){ + values (0); + } + } + internal_power() { + when : "!B_BIST_MEN & B_BIST_WEN & B_BIST_REN"; + rise_power("scalar"){ + values (0.5323); + } + fall_power("scalar"){ + values (0); + } + } + internal_power() { + when : "B_BIST_MEN & !B_BIST_WEN & !B_BIST_REN"; + rise_power("scalar"){ + values (0); + } + fall_power("scalar"){ + values (0); + } + } + } + bus(B_BIST_DIN) { + bus_type : D_7_0; + direction : input ; + capacitance : 0.00414348 ; + memory_write() { + address : B_BIST_ADDR ; + clocked_on : B_BIST_CLK; + } + + max_transition : "0.476" ; + pin(B_BIST_DIN[7:0]) { + related_power_pin : VDD; + related_ground_pin : VSS; + internal_power() { + when : "B_BIST_MEN"; + rise_power("scalar"){ + values (0.0299); + } + fall_power("scalar"){ + values (0.0123); + } + } + internal_power() { + when : "!B_BIST_MEN"; + rise_power("scalar"){ + values (0.0316); + } + fall_power("scalar"){ + values (0.0122); + } + } + } + timing() { + timing_type : setup_rising; + related_pin : "B_BIST_CLK"; + when : "(B_BIST_WEN & B_BIST_MEN)"; + sdf_cond : "B_BIST_W_ACCESS"; + + rise_constraint("SIG2SRAM_constraint_template") { + index_1("0.0056,0.0232,0.0400,0.0728,0.1280,0.2440,0.4760"); + index_2("0.0056,0.0232,0.0400,0.0728,0.1280,0.2440,0.4760"); + values ("-0.2885,-0.2729,-0.2602,-0.2270,-0.1782,-0.0795,0.1138",\ +"-0.2935,-0.2779,-0.2652,-0.2320,-0.1832,-0.0845,0.1088",\ +"-0.2980,-0.2824,-0.2697,-0.2365,-0.1876,-0.0890,0.1043",\ +"-0.3071,-0.2915,-0.2788,-0.2456,-0.1968,-0.0981,0.0952",\ +"-0.3143,-0.2987,-0.2860,-0.2528,-0.2040,-0.1053,0.0880",\ +"-0.3440,-0.3283,-0.3157,-0.2825,-0.2336,-0.1350,0.0584",\ +"-0.4020,-0.3864,-0.3737,-0.3405,-0.2917,-0.1931,0.0003"); + } + + fall_constraint("SIG2SRAM_constraint_template") { + index_1("0.0056,0.0232,0.0400,0.0728,0.1280,0.2440,0.4760"); + index_2("0.0056,0.0232,0.0400,0.0728,0.1280,0.2440,0.4760"); + values ("-0.2543,-0.2397,-0.2260,-0.1977,-0.1479,-0.0493,0.1304",\ +"-0.2593,-0.2447,-0.2310,-0.2027,-0.1529,-0.0543,0.1254",\ +"-0.2638,-0.2492,-0.2355,-0.2072,-0.1574,-0.0587,0.1209",\ +"-0.2729,-0.2583,-0.2446,-0.2163,-0.1665,-0.0679,0.1118",\ +"-0.2801,-0.2655,-0.2518,-0.2235,-0.1737,-0.0751,0.1046",\ +"-0.3098,-0.2951,-0.2815,-0.2532,-0.2033,-0.1047,0.0750",\ +"-0.3679,-0.3532,-0.3395,-0.3112,-0.2614,-0.1628,0.0169"); + } + } + + timing() { + timing_type : hold_rising; + related_pin : "B_BIST_CLK"; + when : "(B_BIST_WEN & B_BIST_MEN)"; + sdf_cond : "B_BIST_W_ACCESS"; + + rise_constraint("SIG2SRAM_constraint_template") { + index_1("0.0056,0.0232,0.0400,0.0728,0.1280,0.2440,0.4760"); + index_2("0.0056,0.0232,0.0400,0.0728,0.1280,0.2440,0.4760"); + values ("0.3976,0.3820,0.3693,0.3361,0.2882,0.1886,-0.0057",\ +"0.4026,0.3870,0.3743,0.3411,0.2932,0.1936,-0.0007",\ +"0.4071,0.3915,0.3788,0.3456,0.2977,0.1981,0.0038",\ +"0.4162,0.4006,0.3879,0.3547,0.3068,0.2072,0.0129",\ +"0.4234,0.4078,0.3951,0.3619,0.3140,0.2144,0.0201",\ +"0.4531,0.4374,0.4247,0.3915,0.3437,0.2441,0.0497",\ +"0.5111,0.4955,0.4828,0.4496,0.4018,0.3021,0.1078"); + } + + fall_constraint("SIG2SRAM_constraint_template") { + index_1("0.0056,0.0232,0.0400,0.0728,0.1280,0.2440,0.4760"); + index_2("0.0056,0.0232,0.0400,0.0728,0.1280,0.2440,0.4760"); + values ("0.3566,0.3419,0.3273,0.2990,0.2482,0.1564,-0.0282",\ +"0.3616,0.3469,0.3323,0.3040,0.2532,0.1614,-0.0232",\ +"0.3661,0.3514,0.3368,0.3084,0.2577,0.1659,-0.0187",\ +"0.3752,0.3605,0.3459,0.3176,0.2668,0.1750,-0.0096",\ +"0.3824,0.3677,0.3531,0.3248,0.2740,0.1822,-0.0024",\ +"0.4120,0.3974,0.3828,0.3544,0.3037,0.2119,0.0273",\ +"0.4701,0.4555,0.4408,0.4125,0.3617,0.2699,0.0854"); + } + } + } + +bus(B_DOUT) { + + bus_type : D_7_0; + direction : output ; + capacitance : 0 ; + max_capacitance : 0.064 ; + memory_read() { + address : B_ADDR ; + } + pin(B_DOUT[7:0]) { + related_power_pin : VDD; + related_ground_pin : VSS; + internal_power() { + rise_power("scalar") { + values (0); + } + fall_power("scalar") { + values (0); + } + } + } + timing() { + related_pin : "B_CLK"; + timing_type : rising_edge ; + timing_sense : non_unate ; + + cell_rise(SIG2SRAM_delay_template) { + index_1("0.0056,0.0232,0.0400,0.0728,0.1280,0.2440,0.4760"); + index_2("0.0008,0.0014,0.0051,0.0100,0.0339,0.0640"); + values ("2.9518,2.9534,2.9610,2.9697,3.0021,3.0383",\ +"2.9581,2.9597,2.9673,2.9761,3.0085,3.0446",\ +"2.9602,2.9618,2.9694,2.9782,3.0106,3.0467",\ +"2.9733,2.9749,2.9825,2.9912,3.0236,3.0598",\ +"2.9795,2.9811,2.9887,2.9974,3.0298,3.0660",\ +"3.0109,3.0125,3.0202,3.0289,3.0613,3.0974",\ +"3.0654,3.0671,3.0747,3.0834,3.1158,3.1519"); + } + cell_fall(SIG2SRAM_delay_template) { + index_1("0.0056,0.0232,0.0400,0.0728,0.1280,0.2440,0.4760"); + index_2("0.0008,0.0014,0.0051,0.0100,0.0339,0.0640"); + values ("2.8915,2.8928,2.8989,2.9060,2.9325,2.9588",\ +"2.8978,2.8992,2.9052,2.9124,2.9389,2.9651",\ +"2.8999,2.9013,2.9073,2.9145,2.9410,2.9672",\ +"2.9130,2.9143,2.9204,2.9275,2.9540,2.9803",\ +"2.9192,2.9205,2.9266,2.9337,2.9602,2.9865",\ +"2.9506,2.9520,2.9581,2.9652,2.9917,3.0179",\ +"3.0052,3.0065,3.0126,3.0197,3.0462,3.0724"); + } + + rise_transition(SRAM_load_template) { + index_1("0.0008,0.0014,0.0051,0.0100,0.0339,0.0640"); + values ("0.0326,0.0341,0.0428,0.0518,0.0923,0.1492"); + } + fall_transition(SRAM_load_template) { + index_1("0.0008,0.0014,0.0051,0.0100,0.0339,0.0640"); + values ("0.0254,0.0265,0.0335,0.0402,0.0707,0.1039"); + } + } +} +cell_leakage_power : 39.8626; +} +} diff --git a/flow/platforms/ihp-sg13g2/lib/RM_IHPSG13_2P_512x16_c2_bm_bist_fast_1p32V_m55C.lib b/flow/platforms/ihp-sg13g2/lib/RM_IHPSG13_2P_512x16_c2_bm_bist_fast_1p32V_m55C.lib new file mode 100644 index 0000000000..bb400b27f8 --- /dev/null +++ b/flow/platforms/ihp-sg13g2/lib/RM_IHPSG13_2P_512x16_c2_bm_bist_fast_1p32V_m55C.lib @@ -0,0 +1,2886 @@ +/* ------------------------------------------------------*/ +/**/ +/* Copyright 2025 IHP PDK Authors*/ +/**/ +/* Licensed under the Apache License, Version 2.0 (the "License");*/ +/* you may not use this file except in compliance with the License.*/ +/* You may obtain a copy of the License at*/ +/* */ +/* https://www.apache.org/licenses/LICENSE-2.0*/ +/* */ +/* Unless required by applicable law or agreed to in writing, software*/ +/* distributed under the License is distributed on an "AS IS" BASIS,*/ +/* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.*/ +/* See the License for the specific language governing permissions and*/ +/* limitations under the License.*/ +/* */ +/* Generated on Wed Aug 27 13:18:09 2025 */ +/* */ +/* ------------------------------------------------------ */ +library(RM_IHPSG13_2P_512x16_c2_bm_bist_fast_1p32V_m55C) { + technology (cmos) ; + delay_model : table_lookup ; + define ("add_pg_pin_to_lib", "library", "boolean"); + add_pg_pin_to_lib : true; + voltage_map ( VDD, 1.32); + voltage_map ( VDDARRAY, 1.32); + voltage_map ( VSS, 0.000000 ); + + date : "Wed Aug 27 13:18:07 2025" ; + comment : "IHP Microelectronics GmbH, 2023" ; + revision : 1.0.0 ; + simulation : true ; + nom_process : 1 ; + nom_temperature : -55 ; + nom_voltage : 1.32 ; + + operating_conditions("fast_1p32V_m55C"){ + process : 1 ; + temperature : -55 ; + voltage : 1.32 ; + tree_type : "balanced_tree" ; + } + + default_operating_conditions : fast_1p32V_m55C ; + default_max_transition : 1.0 ; + default_fanout_load : 1.0 ; + default_inout_pin_cap : 0.0 ; + default_input_pin_cap : 0.0 ; + default_output_pin_cap : 0.0 ; + default_cell_leakage_power : 0.0 ; + default_leakage_power_density : 0.0 ; + + slew_lower_threshold_pct_rise : 30 ; + slew_upper_threshold_pct_rise : 70 ; + input_threshold_pct_fall : 50 ; + output_threshold_pct_fall : 50 ; + input_threshold_pct_rise : 50 ; + output_threshold_pct_rise : 50 ; + slew_lower_threshold_pct_fall : 30 ; + slew_upper_threshold_pct_fall : 70 ; + slew_derate_from_library : 0.5; + k_volt_cell_leakage_power : 0.0 ; + k_temp_cell_leakage_power : 0.0 ; + k_process_cell_leakage_power : 0.0 ; + k_volt_internal_power : 0.0 ; + k_temp_internal_power : 0.0 ; + k_process_internal_power : 0.0 ; + + capacitive_load_unit (1,pf) ; + voltage_unit : "1V" ; + current_unit : "1uA" ; + time_unit : "1ns" ; + leakage_power_unit : "1nW" ; + pulling_resistance_unit : "1kohm"; + /* + ------------------------------------------------------------------------------------------ + implicit units overview: + cell_area unit : "um" + internal_power unit : "1e-12 * J/toggle = 1 * uW/MHz" + (capacitive_load_unit * voltage_unit^2) per toggle event + ------------------------------------------------------------------------------------------ + */ + library_features(report_delay_calculation); + define_cell_area (pad_drivers,pad_driver_sites) ; + + lu_table_template(CLKTRAN_constraint_template) { + variable_1 : constrained_pin_transition; + index_1 ( "0.010, 0.050, 0.200, 0.400, 1.000" ); + } + lu_table_template(SRAM_load_template) { + variable_1 : total_output_net_capacitance; + index_1 ( "0.0008,0.0014,0.0051,0.0100,0.0339,0.0640" ); + } + lu_table_template(SIG2SRAM_constraint_template) { + variable_1 : related_pin_transition; + variable_2 : constrained_pin_transition; + index_1 ( "0.0040,0.0176,0.0344,0.0656,0.1120,0.2016,0.3800" ); + index_2 ( "0.0040,0.0176,0.0344,0.0656,0.1120,0.2016,0.3800" ); + } + + lu_table_template(SIG2SRAM_delay_template) { + variable_1 : input_net_transition; + variable_2 : total_output_net_capacitance; + index_1 ( "0.0040,0.0176,0.0344,0.0656,0.1120,0.2016,0.3800" ); + index_2 ( "0.0008,0.0014,0.0051,0.0100,0.0339,0.0640" ); + } + + type (D_15_0) { + base_type : array; + data_type : bit; + bit_width : 16; + bit_from : 15; + bit_to : 0; + downto : true; + } + + type (A_8_0) { + base_type : array; + data_type : bit; + bit_width : 9; + bit_from : 8; + bit_to : 0; + downto : true; + } + +cell(RM_IHPSG13_2P_512x16_c2_bm_bist) { +pg_pin (VDD) { + pg_type : primary_power; + voltage_name : VDD; +} +pg_pin (VDDARRAY) { + pg_type : primary_power; + voltage_name : VDDARRAY; +} +pg_pin (VSS) { + pg_type : primary_ground; + voltage_name : VSS; +} + +memory() { + type : ram; + address_width : 9; + word_width : 16; +} + +interface_timing : false; +bus_naming_style : "%s[%d]" ; +area : 88481.5997 ; + + pin(A_DLY) { + direction : input ; + capacitance : 0.00421562 ; + max_transition : "1" ; + related_power_pin : VDD; + related_ground_pin : VSS; + internal_power() { + rise_power("scalar") { + values (0); + } + fall_power("scalar") { + values (0); + } + } + } + +bus(A_ADDR) { + bus_type : A_8_0; + direction : input ; + capacitance : 0.0115194 ; + pin(A_ADDR[0]) { + capacitance : 0.00563454 ; + } + pin(A_ADDR[1]) { + capacitance : 0.00744185 ; + } + pin(A_ADDR[2]) { + capacitance : 0.0100611 ; + } + pin(A_ADDR[3]) { + capacitance : 0.00669965 ; + } + pin(A_ADDR[4]) { + capacitance : 0.00614331 ; + } + pin(A_ADDR[5]) { + capacitance : 0.0102172 ; + } + pin(A_ADDR[6]) { + capacitance : 0.0124225 ; + } + pin(A_ADDR[7]) { + capacitance : 0.010114 ; + } + max_transition : "0.38" ; + pin(A_ADDR[8:0]) { + related_power_pin : VDD; + related_ground_pin : VSS; + internal_power() { + when : "A_MEN"; + rise_power("scalar"){ + values (0.0125); + } + fall_power("scalar"){ + values (0.0025); + } + } + internal_power() { + when : "!A_MEN"; + rise_power("scalar"){ + values (0.0288); + } + fall_power("scalar"){ + values (0.0013); + } + } + } + timing() { + timing_type : setup_rising; + related_pin : "A_CLK"; + when : "((A_WEN | A_REN)& A_MEN)" + sdf_cond : "A_RW_ACCESS" + + rise_constraint("SIG2SRAM_constraint_template") { + index_1("0.0040,0.0176,0.0344,0.0656,0.1120,0.2016,0.3800"); + index_2("0.0040,0.0176,0.0344,0.0656,0.1120,0.2016,0.3800"); + values ("-0.2371,-0.2215,-0.2098,-0.1824,-0.1434,-0.0691,0.0676",\ +"-0.2449,-0.2332,-0.2176,-0.1902,-0.1551,-0.0770,0.0559",\ +"-0.2605,-0.2488,-0.2332,-0.2059,-0.1707,-0.0965,0.0441",\ +"-0.2879,-0.2723,-0.2605,-0.2332,-0.1941,-0.1199,0.0168",\ +"-0.3230,-0.3113,-0.2996,-0.2723,-0.2332,-0.1590,-0.0184",\ +"-0.4012,-0.3895,-0.3738,-0.3465,-0.3074,-0.2332,-0.0965",\ +"-0.5379,-0.5262,-0.5105,-0.4832,-0.4480,-0.3699,-0.2332"); + } + + fall_constraint("SIG2SRAM_constraint_template") { + index_1("0.0040,0.0176,0.0344,0.0656,0.1120,0.2016,0.3800"); + index_2("0.0040,0.0176,0.0344,0.0656,0.1120,0.2016,0.3800"); + values ("-0.1785,-0.1707,-0.1551,-0.1277,-0.0887,-0.0184,0.1145",\ +"-0.1902,-0.1785,-0.1629,-0.1355,-0.1004,-0.0262,0.1027",\ +"-0.2059,-0.1941,-0.1785,-0.1512,-0.1160,-0.0418,0.0871",\ +"-0.2293,-0.2176,-0.2059,-0.1785,-0.1434,-0.0691,0.0598",\ +"-0.2684,-0.2566,-0.2449,-0.2176,-0.1824,-0.1082,0.0207",\ +"-0.3465,-0.3348,-0.3191,-0.2918,-0.2566,-0.1824,-0.0535",\ +"-0.4832,-0.4715,-0.4559,-0.4324,-0.3934,-0.3191,-0.1902"); + } + } + + + timing() { + timing_type : hold_rising; + related_pin : "A_CLK"; + when : "((A_WEN | A_REN)& A_MEN)" + sdf_cond : "A_RW_ACCESS" + + rise_constraint("SIG2SRAM_constraint_template") { + index_1("0.0040,0.0176,0.0344,0.0656,0.1120,0.2016,0.3800"); + index_2("0.0040,0.0176,0.0344,0.0656,0.1120,0.2016,0.3800"); + values ("0.3410,0.3293,0.3137,0.2863,0.2473,0.1730,0.0324",\ +"0.3488,0.3371,0.3215,0.2941,0.2590,0.1809,0.0480",\ +"0.3684,0.3527,0.3371,0.3098,0.2746,0.1965,0.0598",\ +"0.3918,0.3762,0.3645,0.3371,0.2980,0.2238,0.0871",\ +"0.4309,0.4152,0.4035,0.3762,0.3371,0.2629,0.1223",\ +"0.5051,0.4934,0.4777,0.4504,0.4113,0.3371,0.1965",\ +"0.6418,0.6262,0.6145,0.5871,0.5520,0.4738,0.3332"); + } + + fall_constraint("SIG2SRAM_constraint_template") { + index_1("0.0040,0.0176,0.0344,0.0656,0.1120,0.2016,0.3800"); + index_2("0.0040,0.0176,0.0344,0.0656,0.1120,0.2016,0.3800"); + values ("0.2824,0.2707,0.2551,0.2277,0.1926,0.1184,-0.0105",\ +"0.2902,0.2785,0.2668,0.2395,0.2043,0.1301,0.0012",\ +"0.3059,0.2941,0.2824,0.2551,0.2199,0.1457,0.0168",\ +"0.3332,0.3215,0.3059,0.2785,0.2434,0.1691,0.0402",\ +"0.3723,0.3605,0.3449,0.3176,0.2824,0.2121,0.0793",\ +"0.4465,0.4348,0.4230,0.3918,0.3566,0.2824,0.1535",\ +"0.5832,0.5715,0.5598,0.5324,0.4934,0.4191,0.2902"); + } + } +} +pin(A_WEN) { + direction : input ; + capacitance : 0.00341384 ; + max_transition : "0.38" ; + related_power_pin : VDD; + related_ground_pin : VSS; + internal_power() { + when : "A_MEN"; + rise_power("scalar"){ + values (0.0076); + } + fall_power("scalar"){ + values (0.0137); + } + } + internal_power() { + when : "!A_MEN"; + rise_power("scalar"){ + values (0.0073); + } + fall_power("scalar"){ + values (0.0261); + } + } + timing() { + timing_type : setup_rising; + related_pin : "A_CLK"; + when : "A_MEN" + sdf_cond : "A_MEN" + + rise_constraint("SIG2SRAM_constraint_template") { + index_1("0.0040,0.0176,0.0344,0.0656,0.1120,0.2016,0.3800"); + index_2("0.0040,0.0176,0.0344,0.0656,0.1120,0.2016,0.3800"); + values ("0.1418,0.1496,0.1652,0.1887,0.2316,0.3059,0.4465",\ +"0.1301,0.1379,0.1535,0.1809,0.2199,0.2941,0.4348",\ +"0.1145,0.1262,0.1379,0.1652,0.2043,0.2785,0.4191",\ +"0.0871,0.0949,0.1105,0.1379,0.1770,0.2512,0.3879",\ +"0.0480,0.0598,0.0754,0.0988,0.1379,0.2082,0.3527",\ +"-0.0262,-0.0145,0.0012,0.0246,0.0676,0.1379,0.2785",\ +"-0.1668,-0.1551,-0.1395,-0.1121,-0.0730,0.0012,0.1418"); + } + + fall_constraint("SIG2SRAM_constraint_template") { + index_1("0.0040,0.0176,0.0344,0.0656,0.1120,0.2016,0.3800"); + index_2("0.0040,0.0176,0.0344,0.0656,0.1120,0.2016,0.3800"); + values ("0.2082,0.2160,0.2316,0.2590,0.2941,0.3684,0.5012",\ +"0.1926,0.2043,0.2199,0.2473,0.2824,0.3566,0.4895",\ +"0.1770,0.1887,0.2043,0.2316,0.2668,0.3410,0.4777",\ +"0.1535,0.1652,0.1770,0.2043,0.2395,0.3137,0.4504",\ +"0.1145,0.1262,0.1379,0.1652,0.2043,0.2746,0.4113",\ +"0.0402,0.0520,0.0676,0.0910,0.1262,0.2004,0.3332",\ +"-0.0965,-0.0848,-0.0730,-0.0457,-0.0066,0.0637,0.2004"); + } + } + + + timing() { + timing_type : hold_rising; + related_pin : "A_CLK"; + when : "A_MEN" + sdf_cond : "A_MEN" + + rise_constraint("SIG2SRAM_constraint_template") { + index_1("0.0040,0.0176,0.0344,0.0656,0.1120,0.2016,0.3800"); + index_2("0.0040,0.0176,0.0344,0.0656,0.1120,0.2016,0.3800"); + values ("0.1770,0.1652,0.1496,0.1223,0.0793,0.0090,-0.1316",\ +"0.1848,0.1730,0.1574,0.1301,0.0910,0.0168,-0.1199",\ +"0.2004,0.1887,0.1770,0.1496,0.1066,0.0363,-0.1043",\ +"0.2277,0.2160,0.2004,0.1730,0.1340,0.0598,-0.0809",\ +"0.2668,0.2551,0.2395,0.2121,0.1730,0.0988,-0.0418",\ +"0.3410,0.3293,0.3137,0.2863,0.2434,0.1730,0.0324",\ +"0.4816,0.4699,0.4543,0.4230,0.3801,0.3098,0.1730"); + } + + fall_constraint("SIG2SRAM_constraint_template") { + index_1("0.0040,0.0176,0.0344,0.0656,0.1120,0.2016,0.3800"); + index_2("0.0040,0.0176,0.0344,0.0656,0.1120,0.2016,0.3800"); + values ("0.1613,0.1496,0.1379,0.1066,0.0715,0.0012,-0.1355",\ +"0.1730,0.1613,0.1457,0.1184,0.0832,0.0129,-0.1238",\ +"0.1887,0.1770,0.1613,0.1340,0.0988,0.0246,-0.1121",\ +"0.2121,0.2043,0.1887,0.1613,0.1223,0.0520,-0.0848",\ +"0.2512,0.2434,0.2277,0.2004,0.1613,0.0910,-0.0457",\ +"0.3254,0.3176,0.3020,0.2746,0.2355,0.1652,0.0324",\ +"0.4660,0.4543,0.4387,0.4113,0.3723,0.3020,0.1691"); + } + } + } +pin(A_REN) { + direction : input ; + capacitance : 0.00390661 ; + max_transition : "0.38" ; + related_power_pin : VDD; + related_ground_pin : VSS; + internal_power() { + when : "A_MEN"; + rise_power("scalar"){ + values (0.0069); + } + fall_power("scalar"){ + values (0.0122); + } + } + internal_power() { + when : "!A_MEN"; + rise_power("scalar"){ + values (0.0243); + } + fall_power("scalar"){ + values (0.0202); + } + } + timing() { + timing_type : setup_rising; + related_pin : "A_CLK"; + when : "A_MEN" + sdf_cond : "A_MEN" + + rise_constraint("SIG2SRAM_constraint_template") { + index_1("0.0040,0.0176,0.0344,0.0656,0.1120,0.2016,0.3800"); + index_2("0.0040,0.0176,0.0344,0.0656,0.1120,0.2016,0.3800"); + values ("-0.0027,0.0090,0.0246,0.0520,0.0910,0.1613,0.3020",\ +"-0.0105,0.0012,0.0129,0.0363,0.0793,0.1535,0.2902",\ +"-0.0262,-0.0145,-0.0027,0.0246,0.0637,0.1379,0.2785",\ +"-0.0535,-0.0418,-0.0262,0.0012,0.0363,0.1105,0.2512",\ +"-0.0926,-0.0809,-0.0652,-0.0418,-0.0027,0.0715,0.2121",\ +"-0.1668,-0.1551,-0.1395,-0.1082,-0.0770,-0.0027,0.1379",\ +"-0.3035,-0.2918,-0.2762,-0.2488,-0.2137,-0.1434,-0.0027"); + } + + fall_constraint("SIG2SRAM_constraint_template") { + index_1("0.0040,0.0176,0.0344,0.0656,0.1120,0.2016,0.3800"); + index_2("0.0040,0.0176,0.0344,0.0656,0.1120,0.2016,0.3800"); + values ("0.0832,0.0949,0.1105,0.1379,0.1730,0.2473,0.3801",\ +"0.0754,0.0832,0.0988,0.1223,0.1613,0.2355,0.3684",\ +"0.0598,0.0676,0.0832,0.1066,0.1457,0.2121,0.3527",\ +"0.0324,0.0441,0.0598,0.0871,0.1223,0.1926,0.3293",\ +"-0.0066,0.0051,0.0168,0.0480,0.0832,0.1535,0.2902",\ +"-0.0809,-0.0691,-0.0574,-0.0301,0.0090,0.0832,0.2121",\ +"-0.2176,-0.2059,-0.1941,-0.1668,-0.1277,-0.0574,0.0793"); + } + } + + + timing() { + timing_type : hold_rising; + related_pin : "A_CLK"; + when : "A_MEN" + sdf_cond : "A_MEN" + + rise_constraint("SIG2SRAM_constraint_template") { + index_1("0.0040,0.0176,0.0344,0.0656,0.1120,0.2016,0.3800"); + index_2("0.0040,0.0176,0.0344,0.0656,0.1120,0.2016,0.3800"); + values ("0.1887,0.1770,0.1613,0.1340,0.0949,0.0207,-0.1160",\ +"0.1965,0.1848,0.1730,0.1457,0.1027,0.0324,-0.1082",\ +"0.2160,0.2004,0.1887,0.1613,0.1184,0.0480,-0.0926",\ +"0.2395,0.2277,0.2121,0.1848,0.1457,0.0715,-0.0652",\ +"0.2785,0.2668,0.2512,0.2238,0.1848,0.1105,-0.0262",\ +"0.3527,0.3410,0.3254,0.2980,0.2551,0.1848,0.0480",\ +"0.4934,0.4816,0.4660,0.4387,0.3957,0.3254,0.1887"); + } + + fall_constraint("SIG2SRAM_constraint_template") { + index_1("0.0040,0.0176,0.0344,0.0656,0.1120,0.2016,0.3800"); + index_2("0.0040,0.0176,0.0344,0.0656,0.1120,0.2016,0.3800"); + values ("0.1730,0.1613,0.1496,0.1184,0.0793,0.0129,-0.1238",\ +"0.1848,0.1730,0.1574,0.1301,0.0910,0.0207,-0.1121",\ +"0.2004,0.1887,0.1730,0.1457,0.1066,0.0363,-0.1004",\ +"0.2238,0.2121,0.2004,0.1691,0.1340,0.0598,-0.0730",\ +"0.2629,0.2512,0.2395,0.2121,0.1691,0.0988,-0.0340",\ +"0.3371,0.3254,0.3137,0.2863,0.2434,0.1730,0.0402",\ +"0.4777,0.4660,0.4504,0.4230,0.3840,0.3137,0.1809"); + } + } + } +pin(A_MEN) { + direction : input ; + capacitance : 0.00326046 ; + max_transition : "0.38" ; + related_power_pin : VDD; + related_ground_pin : VSS; + internal_power() { + rise_power("scalar"){ + values (0.1674); + } + fall_power("scalar"){ + values (0.0108); + } + } + timing() { + timing_type : setup_rising; + related_pin : "A_CLK"; + + rise_constraint("SIG2SRAM_constraint_template") { + index_1("0.0040,0.0176,0.0344,0.0656,0.1120,0.2016,0.3800"); + index_2("0.0040,0.0176,0.0344,0.0656,0.1120,0.2016,0.3800"); + values ("0.1418,0.1496,0.1652,0.1926,0.2316,0.3059,0.4465",\ +"0.1301,0.1379,0.1535,0.1809,0.2199,0.2941,0.4348",\ +"0.1145,0.1262,0.1418,0.1652,0.2043,0.2785,0.4191",\ +"0.0871,0.0949,0.1105,0.1379,0.1770,0.2512,0.3879",\ +"0.0480,0.0598,0.0754,0.0988,0.1379,0.2082,0.3488",\ +"-0.0262,-0.0145,0.0012,0.0285,0.0676,0.1379,0.2785",\ +"-0.1668,-0.1551,-0.1395,-0.1121,-0.0730,0.0012,0.1379"); + } + + fall_constraint("SIG2SRAM_constraint_template") { + index_1("0.0040,0.0176,0.0344,0.0656,0.1120,0.2016,0.3800"); + index_2("0.0040,0.0176,0.0344,0.0656,0.1120,0.2016,0.3800"); + values ("0.2082,0.2199,0.2316,0.2590,0.2980,0.3723,0.5051",\ +"0.1965,0.2082,0.2199,0.2473,0.2863,0.3605,0.4934",\ +"0.1809,0.1926,0.2043,0.2316,0.2707,0.3449,0.4777",\ +"0.1574,0.1691,0.1809,0.2082,0.2434,0.3176,0.4543",\ +"0.1145,0.1262,0.1418,0.1691,0.2043,0.2785,0.4113",\ +"0.0441,0.0559,0.0676,0.0949,0.1301,0.2004,0.3332",\ +"-0.0965,-0.0848,-0.0691,-0.0418,-0.0066,0.0676,0.2004"); + } + } + + + timing() { + timing_type : hold_rising; + related_pin : "A_CLK"; + + rise_constraint("SIG2SRAM_constraint_template") { + index_1("0.0040,0.0176,0.0344,0.0656,0.1120,0.2016,0.3800"); + index_2("0.0040,0.0176,0.0344,0.0656,0.1120,0.2016,0.3800"); + values ("0.1770,0.1652,0.1535,0.1262,0.0832,0.0129,-0.1277",\ +"0.1887,0.1770,0.1613,0.1340,0.0949,0.0207,-0.1199",\ +"0.2043,0.1926,0.1770,0.1496,0.1105,0.0363,-0.1043",\ +"0.2277,0.2160,0.2043,0.1770,0.1379,0.0598,-0.0770",\ +"0.2668,0.2551,0.2434,0.2160,0.1730,0.0988,-0.0379",\ +"0.3449,0.3332,0.3176,0.2902,0.2473,0.1730,0.0363",\ +"0.4816,0.4699,0.4543,0.4270,0.3840,0.3098,0.1770"); + } + + fall_constraint("SIG2SRAM_constraint_template") { + index_1("0.0040,0.0176,0.0344,0.0656,0.1120,0.2016,0.3800"); + index_2("0.0040,0.0176,0.0344,0.0656,0.1120,0.2016,0.3800"); + values ("0.1613,0.1496,0.1379,0.1105,0.0715,0.0012,-0.1355",\ +"0.1730,0.1613,0.1496,0.1184,0.0832,0.0129,-0.1238",\ +"0.1887,0.1770,0.1652,0.1340,0.0988,0.0285,-0.1121",\ +"0.2121,0.2043,0.1887,0.1613,0.1223,0.0520,-0.0848",\ +"0.2551,0.2434,0.2277,0.2004,0.1613,0.0910,-0.0418",\ +"0.3293,0.3176,0.3020,0.2746,0.2395,0.1652,0.0324",\ +"0.4660,0.4543,0.4426,0.4113,0.3762,0.3020,0.1691"); + } + } + } +bus(A_BM) { + bus_type : D_15_0; + direction : input ; + capacitance : 0.00388883 ; + max_transition : "0.38" ; + pin(A_BM[15:0]) { + related_power_pin : VDD; + related_ground_pin : VSS; + internal_power() { + when : "A_MEN"; + rise_power("scalar"){ + values (0.0757); + } + fall_power("scalar"){ + values (0.0696); + } + } + internal_power() { + when : "!A_MEN"; + rise_power("scalar"){ + values (0.0977); + } + fall_power("scalar"){ + values (0.0801); + } + } + } + timing() { + timing_type : setup_rising; + related_pin : "A_CLK"; + when : "(A_WEN & A_MEN)" + sdf_cond : "A_RW_ACCESS" + + rise_constraint("SIG2SRAM_constraint_template") { + index_1("0.0040,0.0176,0.0344,0.0656,0.1120,0.2016,0.3800"); + index_2("0.0040,0.0176,0.0344,0.0656,0.1120,0.2016,0.3800"); + values ("-0.2116,-0.2009,-0.1853,-0.1599,-0.1189,-0.0456,0.0891",\ +"-0.2155,-0.2048,-0.1892,-0.1638,-0.1228,-0.0495,0.0852",\ +"-0.2193,-0.2086,-0.1930,-0.1676,-0.1266,-0.0533,0.0815",\ +"-0.2226,-0.2118,-0.1962,-0.1708,-0.1298,-0.0566,0.0782",\ +"-0.2350,-0.2243,-0.2087,-0.1833,-0.1422,-0.0690,0.0658",\ +"-0.2526,-0.2419,-0.2263,-0.2009,-0.1599,-0.0866,0.0481",\ +"-0.2801,-0.2694,-0.2538,-0.2284,-0.1874,-0.1141,0.0206"); + } + + fall_constraint("SIG2SRAM_constraint_template") { + index_1("0.0040,0.0176,0.0344,0.0656,0.1120,0.2016,0.3800"); + index_2("0.0040,0.0176,0.0344,0.0656,0.1120,0.2016,0.3800"); + values ("-0.1882,-0.1765,-0.1638,-0.1365,-0.0993,-0.0261,0.1018",\ +"-0.1921,-0.1804,-0.1677,-0.1403,-0.1032,-0.0300,0.0979",\ +"-0.1959,-0.1842,-0.1715,-0.1441,-0.1070,-0.0338,0.0941",\ +"-0.1991,-0.1874,-0.1747,-0.1474,-0.1103,-0.0370,0.0909",\ +"-0.2116,-0.1999,-0.1872,-0.1598,-0.1227,-0.0495,0.0784",\ +"-0.2292,-0.2175,-0.2048,-0.1774,-0.1403,-0.0671,0.0608",\ +"-0.2567,-0.2450,-0.2323,-0.2049,-0.1678,-0.0946,0.0333"); + } + } + + + timing() { + timing_type : hold_rising; + related_pin : "A_CLK"; + when : "(A_WEN & A_MEN)" + sdf_cond : "A_RW_ACCESS" + + rise_constraint("SIG2SRAM_constraint_template") { + index_1("0.0040,0.0176,0.0344,0.0656,0.1120,0.2016,0.3800"); + index_2("0.0040,0.0176,0.0344,0.0656,0.1120,0.2016,0.3800"); + values ("0.3170,0.3073,0.2916,0.2653,0.2282,0.1539,0.0192",\ +"0.3209,0.3111,0.2955,0.2691,0.2320,0.1578,0.0231",\ +"0.3247,0.3149,0.2993,0.2729,0.2358,0.1616,0.0269",\ +"0.3280,0.3182,0.3026,0.2762,0.2391,0.1649,0.0301",\ +"0.3404,0.3306,0.3150,0.2886,0.2515,0.1773,0.0426",\ +"0.3580,0.3482,0.3326,0.3063,0.2691,0.1949,0.0602",\ +"0.3855,0.3758,0.3601,0.3338,0.2966,0.2224,0.0877"); + } + + fall_constraint("SIG2SRAM_constraint_template") { + index_1("0.0040,0.0176,0.0344,0.0656,0.1120,0.2016,0.3800"); + index_2("0.0040,0.0176,0.0344,0.0656,0.1120,0.2016,0.3800"); + values ("0.2887,0.2780,0.2643,0.2369,0.2008,0.1285,-0.0013",\ +"0.2926,0.2818,0.2682,0.2408,0.2047,0.1324,0.0025",\ +"0.2964,0.2856,0.2720,0.2446,0.2085,0.1362,0.0063",\ +"0.2996,0.2889,0.2752,0.2479,0.2117,0.1395,0.0096",\ +"0.3121,0.3013,0.2877,0.2603,0.2242,0.1519,0.0220",\ +"0.3297,0.3189,0.3053,0.2779,0.2418,0.1695,0.0397",\ +"0.3572,0.3465,0.3328,0.3054,0.2693,0.1970,0.0672"); + } + } +} + pin(A_CLK) { + direction : input; + capacitance : 0.00389386; + max_transition : "0.38"; + clock : "true" ; + pin_func_type : active_rising ; + + timing () { + timing_type : "min_pulse_width"; + related_pin : "A_CLK"; + rise_constraint("CLKTRAN_constraint_template") { + index_1("0.004,0.38"); + values("0.12,0.12"); + } + } + + related_power_pin : VDD; + related_ground_pin : VSS; + + internal_power() { + when : "!A_MEN & !A_WEN & !A_REN"; + rise_power("scalar"){ + values (0); + } + fall_power("scalar"){ + values (0); + } + } + internal_power() { + when : "!A_MEN & A_WEN & !A_REN"; + rise_power("scalar"){ + values (0.6697); + } + fall_power("scalar"){ + values (0); + } + } + internal_power() { + when : "A_MEN & A_WEN & !A_REN"; + rise_power("scalar"){ + values (29.9728); + } + fall_power("scalar"){ + values (0); + } + } + internal_power() { + when : "A_MEN & A_WEN & A_REN"; + rise_power("scalar"){ + values (30.7463); + } + fall_power("scalar"){ + values (0); + } + } + internal_power() { + when : "A_MEN & !A_WEN & A_REN"; + rise_power("scalar"){ + values (24.5331); + } + fall_power("scalar"){ + values (0); + } + } + internal_power() { + when : "!A_MEN & !A_WEN & A_REN"; + rise_power("scalar"){ + values (0.4084); + } + fall_power("scalar"){ + values (0); + } + } + internal_power() { + when : "!A_MEN & A_WEN & A_REN"; + rise_power("scalar"){ + values (1.0137); + } + fall_power("scalar"){ + values (0); + } + } + internal_power() { + when : "A_MEN & !A_WEN & !A_REN"; + rise_power("scalar"){ + values (0); + } + fall_power("scalar"){ + values (0); + } + } + } + bus(A_DIN) { + bus_type : D_15_0; + direction : input ; + capacitance : 0.00505326 ; + memory_write() { + address : A_ADDR ; + clocked_on : A_CLK; + } + + max_transition : "0.38" ; + pin(A_DIN[15:0]) { + related_power_pin : VDD; + related_ground_pin : VSS; + internal_power() { + when : "A_MEN"; + rise_power("scalar"){ + values (0.0757); + } + fall_power("scalar"){ + values (0.0696); + } + } + internal_power() { + when : "!A_MEN"; + rise_power("scalar"){ + values (0.0977); + } + fall_power("scalar"){ + values (0.0801); + } + } + } + timing() { + timing_type : setup_rising; + related_pin : "A_CLK"; + when : "(A_WEN & A_MEN)"; + sdf_cond : "A_W_ACCESS"; + + rise_constraint("SIG2SRAM_constraint_template") { + index_1("0.0040,0.0176,0.0344,0.0656,0.1120,0.2016,0.3800"); + index_2("0.0040,0.0176,0.0344,0.0656,0.1120,0.2016,0.3800"); + values ("-0.2116,-0.2009,-0.1853,-0.1599,-0.1189,-0.0456,0.0891",\ +"-0.2155,-0.2048,-0.1892,-0.1638,-0.1228,-0.0495,0.0852",\ +"-0.2193,-0.2086,-0.1930,-0.1676,-0.1266,-0.0533,0.0815",\ +"-0.2226,-0.2118,-0.1962,-0.1708,-0.1298,-0.0566,0.0782",\ +"-0.2350,-0.2243,-0.2087,-0.1833,-0.1422,-0.0690,0.0658",\ +"-0.2526,-0.2419,-0.2263,-0.2009,-0.1599,-0.0866,0.0481",\ +"-0.2801,-0.2694,-0.2538,-0.2284,-0.1874,-0.1141,0.0206"); + } + + fall_constraint("SIG2SRAM_constraint_template") { + index_1("0.0040,0.0176,0.0344,0.0656,0.1120,0.2016,0.3800"); + index_2("0.0040,0.0176,0.0344,0.0656,0.1120,0.2016,0.3800"); + values ("-0.1882,-0.1765,-0.1638,-0.1365,-0.0993,-0.0261,0.1018",\ +"-0.1921,-0.1804,-0.1677,-0.1403,-0.1032,-0.0300,0.0979",\ +"-0.1959,-0.1842,-0.1715,-0.1441,-0.1070,-0.0338,0.0941",\ +"-0.1991,-0.1874,-0.1747,-0.1474,-0.1103,-0.0370,0.0909",\ +"-0.2116,-0.1999,-0.1872,-0.1598,-0.1227,-0.0495,0.0784",\ +"-0.2292,-0.2175,-0.2048,-0.1774,-0.1403,-0.0671,0.0608",\ +"-0.2567,-0.2450,-0.2323,-0.2049,-0.1678,-0.0946,0.0333"); + } + } + + timing() { + timing_type : hold_rising; + related_pin : "A_CLK"; + when : "(A_WEN & A_MEN)"; + sdf_cond : "A_W_ACCESS"; + + rise_constraint("SIG2SRAM_constraint_template") { + index_1("0.0040,0.0176,0.0344,0.0656,0.1120,0.2016,0.3800"); + index_2("0.0040,0.0176,0.0344,0.0656,0.1120,0.2016,0.3800"); + values ("0.3170,0.3073,0.2916,0.2653,0.2282,0.1539,0.0192",\ +"0.3209,0.3111,0.2955,0.2691,0.2320,0.1578,0.0231",\ +"0.3247,0.3149,0.2993,0.2729,0.2358,0.1616,0.0269",\ +"0.3280,0.3182,0.3026,0.2762,0.2391,0.1649,0.0301",\ +"0.3404,0.3306,0.3150,0.2886,0.2515,0.1773,0.0426",\ +"0.3580,0.3482,0.3326,0.3063,0.2691,0.1949,0.0602",\ +"0.3855,0.3758,0.3601,0.3338,0.2966,0.2224,0.0877"); + } + + fall_constraint("SIG2SRAM_constraint_template") { + index_1("0.0040,0.0176,0.0344,0.0656,0.1120,0.2016,0.3800"); + index_2("0.0040,0.0176,0.0344,0.0656,0.1120,0.2016,0.3800"); + values ("0.2887,0.2780,0.2643,0.2369,0.2008,0.1285,-0.0013",\ +"0.2926,0.2818,0.2682,0.2408,0.2047,0.1324,0.0025",\ +"0.2964,0.2856,0.2720,0.2446,0.2085,0.1362,0.0063",\ +"0.2996,0.2889,0.2752,0.2479,0.2117,0.1395,0.0096",\ +"0.3121,0.3013,0.2877,0.2603,0.2242,0.1519,0.0220",\ +"0.3297,0.3189,0.3053,0.2779,0.2418,0.1695,0.0397",\ +"0.3572,0.3465,0.3328,0.3054,0.2693,0.1970,0.0672"); + } + } + } + + pin(A_BIST_EN) { + direction : input ; + capacitance : 0.00421562 ; + max_transition : "1" ; + related_power_pin : VDD; + related_ground_pin : VSS; + internal_power() { + rise_power("scalar") { + values (0); + } + fall_power("scalar") { + values (0); + } + } + } + +bus(A_BIST_ADDR) { + bus_type : A_8_0; + direction : input ; + capacitance : 0.0115194 ; + pin(A_BIST_ADDR[0]) { + capacitance : 0.00563454 ; + } + pin(A_BIST_ADDR[1]) { + capacitance : 0.00744185 ; + } + pin(A_BIST_ADDR[2]) { + capacitance : 0.0100611 ; + } + pin(A_BIST_ADDR[3]) { + capacitance : 0.00669965 ; + } + pin(A_BIST_ADDR[4]) { + capacitance : 0.00614331 ; + } + pin(A_BIST_ADDR[5]) { + capacitance : 0.0102172 ; + } + pin(A_BIST_ADDR[6]) { + capacitance : 0.0124225 ; + } + pin(A_BIST_ADDR[7]) { + capacitance : 0.010114 ; + } + max_transition : "0.38" ; + pin(A_BIST_ADDR[8:0]) { + related_power_pin : VDD; + related_ground_pin : VSS; + internal_power() { + when : "A_BIST_MEN"; + rise_power("scalar"){ + values (0.0125); + } + fall_power("scalar"){ + values (0.0025); + } + } + internal_power() { + when : "!A_BIST_MEN"; + rise_power("scalar"){ + values (0.0288); + } + fall_power("scalar"){ + values (0.0013); + } + } + } + timing() { + timing_type : setup_rising; + related_pin : "A_BIST_CLK"; + when : "((A_BIST_WEN | A_BIST_REN)& A_BIST_MEN)" + sdf_cond : "A_BIST_RW_ACCESS" + + rise_constraint("SIG2SRAM_constraint_template") { + index_1("0.0040,0.0176,0.0344,0.0656,0.1120,0.2016,0.3800"); + index_2("0.0040,0.0176,0.0344,0.0656,0.1120,0.2016,0.3800"); + values ("-0.2371,-0.2215,-0.2098,-0.1824,-0.1434,-0.0691,0.0676",\ +"-0.2449,-0.2332,-0.2176,-0.1902,-0.1551,-0.0770,0.0559",\ +"-0.2605,-0.2488,-0.2332,-0.2059,-0.1707,-0.0965,0.0441",\ +"-0.2879,-0.2723,-0.2605,-0.2332,-0.1941,-0.1199,0.0168",\ +"-0.3230,-0.3113,-0.2996,-0.2723,-0.2332,-0.1590,-0.0184",\ +"-0.4012,-0.3895,-0.3738,-0.3465,-0.3074,-0.2332,-0.0965",\ +"-0.5379,-0.5262,-0.5105,-0.4832,-0.4480,-0.3699,-0.2332"); + } + + fall_constraint("SIG2SRAM_constraint_template") { + index_1("0.0040,0.0176,0.0344,0.0656,0.1120,0.2016,0.3800"); + index_2("0.0040,0.0176,0.0344,0.0656,0.1120,0.2016,0.3800"); + values ("-0.1785,-0.1707,-0.1551,-0.1277,-0.0887,-0.0184,0.1145",\ +"-0.1902,-0.1785,-0.1629,-0.1355,-0.1004,-0.0262,0.1027",\ +"-0.2059,-0.1941,-0.1785,-0.1512,-0.1160,-0.0418,0.0871",\ +"-0.2293,-0.2176,-0.2059,-0.1785,-0.1434,-0.0691,0.0598",\ +"-0.2684,-0.2566,-0.2449,-0.2176,-0.1824,-0.1082,0.0207",\ +"-0.3465,-0.3348,-0.3191,-0.2918,-0.2566,-0.1824,-0.0535",\ +"-0.4832,-0.4715,-0.4559,-0.4324,-0.3934,-0.3191,-0.1902"); + } + } + + + timing() { + timing_type : hold_rising; + related_pin : "A_BIST_CLK"; + when : "((A_BIST_WEN | A_BIST_REN)& A_BIST_MEN)" + sdf_cond : "A_BIST_RW_ACCESS" + + rise_constraint("SIG2SRAM_constraint_template") { + index_1("0.0040,0.0176,0.0344,0.0656,0.1120,0.2016,0.3800"); + index_2("0.0040,0.0176,0.0344,0.0656,0.1120,0.2016,0.3800"); + values ("0.3410,0.3293,0.3137,0.2863,0.2473,0.1730,0.0324",\ +"0.3488,0.3371,0.3215,0.2941,0.2590,0.1809,0.0480",\ +"0.3684,0.3527,0.3371,0.3098,0.2746,0.1965,0.0598",\ +"0.3918,0.3762,0.3645,0.3371,0.2980,0.2238,0.0871",\ +"0.4309,0.4152,0.4035,0.3762,0.3371,0.2629,0.1223",\ +"0.5051,0.4934,0.4777,0.4504,0.4113,0.3371,0.1965",\ +"0.6418,0.6262,0.6145,0.5871,0.5520,0.4738,0.3332"); + } + + fall_constraint("SIG2SRAM_constraint_template") { + index_1("0.0040,0.0176,0.0344,0.0656,0.1120,0.2016,0.3800"); + index_2("0.0040,0.0176,0.0344,0.0656,0.1120,0.2016,0.3800"); + values ("0.2824,0.2707,0.2551,0.2277,0.1926,0.1184,-0.0105",\ +"0.2902,0.2785,0.2668,0.2395,0.2043,0.1301,0.0012",\ +"0.3059,0.2941,0.2824,0.2551,0.2199,0.1457,0.0168",\ +"0.3332,0.3215,0.3059,0.2785,0.2434,0.1691,0.0402",\ +"0.3723,0.3605,0.3449,0.3176,0.2824,0.2121,0.0793",\ +"0.4465,0.4348,0.4230,0.3918,0.3566,0.2824,0.1535",\ +"0.5832,0.5715,0.5598,0.5324,0.4934,0.4191,0.2902"); + } + } +} +pin(A_BIST_WEN) { + direction : input ; + capacitance : 0.00341384 ; + max_transition : "0.38" ; + related_power_pin : VDD; + related_ground_pin : VSS; + internal_power() { + when : "A_BIST_MEN"; + rise_power("scalar"){ + values (0.0076); + } + fall_power("scalar"){ + values (0.0137); + } + } + internal_power() { + when : "!A_BIST_MEN"; + rise_power("scalar"){ + values (0.0073); + } + fall_power("scalar"){ + values (0.0261); + } + } + timing() { + timing_type : setup_rising; + related_pin : "A_BIST_CLK"; + when : "A_BIST_MEN" + sdf_cond : "A_BIST_MEN" + + rise_constraint("SIG2SRAM_constraint_template") { + index_1("0.0040,0.0176,0.0344,0.0656,0.1120,0.2016,0.3800"); + index_2("0.0040,0.0176,0.0344,0.0656,0.1120,0.2016,0.3800"); + values ("0.1418,0.1496,0.1652,0.1887,0.2316,0.3059,0.4465",\ +"0.1301,0.1379,0.1535,0.1809,0.2199,0.2941,0.4348",\ +"0.1145,0.1262,0.1379,0.1652,0.2043,0.2785,0.4191",\ +"0.0871,0.0949,0.1105,0.1379,0.1770,0.2512,0.3879",\ +"0.0480,0.0598,0.0754,0.0988,0.1379,0.2082,0.3527",\ +"-0.0262,-0.0145,0.0012,0.0246,0.0676,0.1379,0.2785",\ +"-0.1668,-0.1551,-0.1395,-0.1121,-0.0730,0.0012,0.1418"); + } + + fall_constraint("SIG2SRAM_constraint_template") { + index_1("0.0040,0.0176,0.0344,0.0656,0.1120,0.2016,0.3800"); + index_2("0.0040,0.0176,0.0344,0.0656,0.1120,0.2016,0.3800"); + values ("0.2082,0.2160,0.2316,0.2590,0.2941,0.3684,0.5012",\ +"0.1926,0.2043,0.2199,0.2473,0.2824,0.3566,0.4895",\ +"0.1770,0.1887,0.2043,0.2316,0.2668,0.3410,0.4777",\ +"0.1535,0.1652,0.1770,0.2043,0.2395,0.3137,0.4504",\ +"0.1145,0.1262,0.1379,0.1652,0.2043,0.2746,0.4113",\ +"0.0402,0.0520,0.0676,0.0910,0.1262,0.2004,0.3332",\ +"-0.0965,-0.0848,-0.0730,-0.0457,-0.0066,0.0637,0.2004"); + } + } + + + timing() { + timing_type : hold_rising; + related_pin : "A_BIST_CLK"; + when : "A_BIST_MEN" + sdf_cond : "A_BIST_MEN" + + rise_constraint("SIG2SRAM_constraint_template") { + index_1("0.0040,0.0176,0.0344,0.0656,0.1120,0.2016,0.3800"); + index_2("0.0040,0.0176,0.0344,0.0656,0.1120,0.2016,0.3800"); + values ("0.1770,0.1652,0.1496,0.1223,0.0793,0.0090,-0.1316",\ +"0.1848,0.1730,0.1574,0.1301,0.0910,0.0168,-0.1199",\ +"0.2004,0.1887,0.1770,0.1496,0.1066,0.0363,-0.1043",\ +"0.2277,0.2160,0.2004,0.1730,0.1340,0.0598,-0.0809",\ +"0.2668,0.2551,0.2395,0.2121,0.1730,0.0988,-0.0418",\ +"0.3410,0.3293,0.3137,0.2863,0.2434,0.1730,0.0324",\ +"0.4816,0.4699,0.4543,0.4230,0.3801,0.3098,0.1730"); + } + + fall_constraint("SIG2SRAM_constraint_template") { + index_1("0.0040,0.0176,0.0344,0.0656,0.1120,0.2016,0.3800"); + index_2("0.0040,0.0176,0.0344,0.0656,0.1120,0.2016,0.3800"); + values ("0.1613,0.1496,0.1379,0.1066,0.0715,0.0012,-0.1355",\ +"0.1730,0.1613,0.1457,0.1184,0.0832,0.0129,-0.1238",\ +"0.1887,0.1770,0.1613,0.1340,0.0988,0.0246,-0.1121",\ +"0.2121,0.2043,0.1887,0.1613,0.1223,0.0520,-0.0848",\ +"0.2512,0.2434,0.2277,0.2004,0.1613,0.0910,-0.0457",\ +"0.3254,0.3176,0.3020,0.2746,0.2355,0.1652,0.0324",\ +"0.4660,0.4543,0.4387,0.4113,0.3723,0.3020,0.1691"); + } + } + } +pin(A_BIST_REN) { + direction : input ; + capacitance : 0.00390661 ; + max_transition : "0.38" ; + related_power_pin : VDD; + related_ground_pin : VSS; + internal_power() { + when : "A_BIST_MEN"; + rise_power("scalar"){ + values (0.0069); + } + fall_power("scalar"){ + values (0.0122); + } + } + internal_power() { + when : "!A_BIST_MEN"; + rise_power("scalar"){ + values (0.0243); + } + fall_power("scalar"){ + values (0.0202); + } + } + timing() { + timing_type : setup_rising; + related_pin : "A_BIST_CLK"; + when : "A_BIST_MEN" + sdf_cond : "A_BIST_MEN" + + rise_constraint("SIG2SRAM_constraint_template") { + index_1("0.0040,0.0176,0.0344,0.0656,0.1120,0.2016,0.3800"); + index_2("0.0040,0.0176,0.0344,0.0656,0.1120,0.2016,0.3800"); + values ("-0.0027,0.0090,0.0246,0.0520,0.0910,0.1613,0.3020",\ +"-0.0105,0.0012,0.0129,0.0363,0.0793,0.1535,0.2902",\ +"-0.0262,-0.0145,-0.0027,0.0246,0.0637,0.1379,0.2785",\ +"-0.0535,-0.0418,-0.0262,0.0012,0.0363,0.1105,0.2512",\ +"-0.0926,-0.0809,-0.0652,-0.0418,-0.0027,0.0715,0.2121",\ +"-0.1668,-0.1551,-0.1395,-0.1082,-0.0770,-0.0027,0.1379",\ +"-0.3035,-0.2918,-0.2762,-0.2488,-0.2137,-0.1434,-0.0027"); + } + + fall_constraint("SIG2SRAM_constraint_template") { + index_1("0.0040,0.0176,0.0344,0.0656,0.1120,0.2016,0.3800"); + index_2("0.0040,0.0176,0.0344,0.0656,0.1120,0.2016,0.3800"); + values ("0.0832,0.0949,0.1105,0.1379,0.1730,0.2473,0.3801",\ +"0.0754,0.0832,0.0988,0.1223,0.1613,0.2355,0.3684",\ +"0.0598,0.0676,0.0832,0.1066,0.1457,0.2121,0.3527",\ +"0.0324,0.0441,0.0598,0.0871,0.1223,0.1926,0.3293",\ +"-0.0066,0.0051,0.0168,0.0480,0.0832,0.1535,0.2902",\ +"-0.0809,-0.0691,-0.0574,-0.0301,0.0090,0.0832,0.2121",\ +"-0.2176,-0.2059,-0.1941,-0.1668,-0.1277,-0.0574,0.0793"); + } + } + + + timing() { + timing_type : hold_rising; + related_pin : "A_BIST_CLK"; + when : "A_BIST_MEN" + sdf_cond : "A_BIST_MEN" + + rise_constraint("SIG2SRAM_constraint_template") { + index_1("0.0040,0.0176,0.0344,0.0656,0.1120,0.2016,0.3800"); + index_2("0.0040,0.0176,0.0344,0.0656,0.1120,0.2016,0.3800"); + values ("0.1887,0.1770,0.1613,0.1340,0.0949,0.0207,-0.1160",\ +"0.1965,0.1848,0.1730,0.1457,0.1027,0.0324,-0.1082",\ +"0.2160,0.2004,0.1887,0.1613,0.1184,0.0480,-0.0926",\ +"0.2395,0.2277,0.2121,0.1848,0.1457,0.0715,-0.0652",\ +"0.2785,0.2668,0.2512,0.2238,0.1848,0.1105,-0.0262",\ +"0.3527,0.3410,0.3254,0.2980,0.2551,0.1848,0.0480",\ +"0.4934,0.4816,0.4660,0.4387,0.3957,0.3254,0.1887"); + } + + fall_constraint("SIG2SRAM_constraint_template") { + index_1("0.0040,0.0176,0.0344,0.0656,0.1120,0.2016,0.3800"); + index_2("0.0040,0.0176,0.0344,0.0656,0.1120,0.2016,0.3800"); + values ("0.1730,0.1613,0.1496,0.1184,0.0793,0.0129,-0.1238",\ +"0.1848,0.1730,0.1574,0.1301,0.0910,0.0207,-0.1121",\ +"0.2004,0.1887,0.1730,0.1457,0.1066,0.0363,-0.1004",\ +"0.2238,0.2121,0.2004,0.1691,0.1340,0.0598,-0.0730",\ +"0.2629,0.2512,0.2395,0.2121,0.1691,0.0988,-0.0340",\ +"0.3371,0.3254,0.3137,0.2863,0.2434,0.1730,0.0402",\ +"0.4777,0.4660,0.4504,0.4230,0.3840,0.3137,0.1809"); + } + } + } +pin(A_BIST_MEN) { + direction : input ; + capacitance : 0.00326046 ; + max_transition : "0.38" ; + related_power_pin : VDD; + related_ground_pin : VSS; + internal_power() { + rise_power("scalar"){ + values (0.1674); + } + fall_power("scalar"){ + values (0.0108); + } + } + timing() { + timing_type : setup_rising; + related_pin : "A_BIST_CLK"; + + rise_constraint("SIG2SRAM_constraint_template") { + index_1("0.0040,0.0176,0.0344,0.0656,0.1120,0.2016,0.3800"); + index_2("0.0040,0.0176,0.0344,0.0656,0.1120,0.2016,0.3800"); + values ("0.1418,0.1496,0.1652,0.1926,0.2316,0.3059,0.4465",\ +"0.1301,0.1379,0.1535,0.1809,0.2199,0.2941,0.4348",\ +"0.1145,0.1262,0.1418,0.1652,0.2043,0.2785,0.4191",\ +"0.0871,0.0949,0.1105,0.1379,0.1770,0.2512,0.3879",\ +"0.0480,0.0598,0.0754,0.0988,0.1379,0.2082,0.3488",\ +"-0.0262,-0.0145,0.0012,0.0285,0.0676,0.1379,0.2785",\ +"-0.1668,-0.1551,-0.1395,-0.1121,-0.0730,0.0012,0.1379"); + } + + fall_constraint("SIG2SRAM_constraint_template") { + index_1("0.0040,0.0176,0.0344,0.0656,0.1120,0.2016,0.3800"); + index_2("0.0040,0.0176,0.0344,0.0656,0.1120,0.2016,0.3800"); + values ("0.2082,0.2199,0.2316,0.2590,0.2980,0.3723,0.5051",\ +"0.1965,0.2082,0.2199,0.2473,0.2863,0.3605,0.4934",\ +"0.1809,0.1926,0.2043,0.2316,0.2707,0.3449,0.4777",\ +"0.1574,0.1691,0.1809,0.2082,0.2434,0.3176,0.4543",\ +"0.1145,0.1262,0.1418,0.1691,0.2043,0.2785,0.4113",\ +"0.0441,0.0559,0.0676,0.0949,0.1301,0.2004,0.3332",\ +"-0.0965,-0.0848,-0.0691,-0.0418,-0.0066,0.0676,0.2004"); + } + } + + + timing() { + timing_type : hold_rising; + related_pin : "A_BIST_CLK"; + + rise_constraint("SIG2SRAM_constraint_template") { + index_1("0.0040,0.0176,0.0344,0.0656,0.1120,0.2016,0.3800"); + index_2("0.0040,0.0176,0.0344,0.0656,0.1120,0.2016,0.3800"); + values ("0.1770,0.1652,0.1535,0.1262,0.0832,0.0129,-0.1277",\ +"0.1887,0.1770,0.1613,0.1340,0.0949,0.0207,-0.1199",\ +"0.2043,0.1926,0.1770,0.1496,0.1105,0.0363,-0.1043",\ +"0.2277,0.2160,0.2043,0.1770,0.1379,0.0598,-0.0770",\ +"0.2668,0.2551,0.2434,0.2160,0.1730,0.0988,-0.0379",\ +"0.3449,0.3332,0.3176,0.2902,0.2473,0.1730,0.0363",\ +"0.4816,0.4699,0.4543,0.4270,0.3840,0.3098,0.1770"); + } + + fall_constraint("SIG2SRAM_constraint_template") { + index_1("0.0040,0.0176,0.0344,0.0656,0.1120,0.2016,0.3800"); + index_2("0.0040,0.0176,0.0344,0.0656,0.1120,0.2016,0.3800"); + values ("0.1613,0.1496,0.1379,0.1105,0.0715,0.0012,-0.1355",\ +"0.1730,0.1613,0.1496,0.1184,0.0832,0.0129,-0.1238",\ +"0.1887,0.1770,0.1652,0.1340,0.0988,0.0285,-0.1121",\ +"0.2121,0.2043,0.1887,0.1613,0.1223,0.0520,-0.0848",\ +"0.2551,0.2434,0.2277,0.2004,0.1613,0.0910,-0.0418",\ +"0.3293,0.3176,0.3020,0.2746,0.2395,0.1652,0.0324",\ +"0.4660,0.4543,0.4426,0.4113,0.3762,0.3020,0.1691"); + } + } + } +bus(A_BIST_BM) { + bus_type : D_15_0; + direction : input ; + capacitance : 0.00353394 ; + max_transition : "0.38" ; + pin(A_BIST_BM[15:0]) { + related_power_pin : VDD; + related_ground_pin : VSS; + internal_power() { + when : "A_BIST_MEN"; + rise_power("scalar"){ + values (0.0757); + } + fall_power("scalar"){ + values (0.0696); + } + } + internal_power() { + when : "!A_BIST_MEN"; + rise_power("scalar"){ + values (0.0977); + } + fall_power("scalar"){ + values (0.0801); + } + } + } + timing() { + timing_type : setup_rising; + related_pin : "A_BIST_CLK"; + when : "(A_BIST_WEN & A_BIST_MEN)" + sdf_cond : "A_BIST_RW_ACCESS" + + rise_constraint("SIG2SRAM_constraint_template") { + index_1("0.0040,0.0176,0.0344,0.0656,0.1120,0.2016,0.3800"); + index_2("0.0040,0.0176,0.0344,0.0656,0.1120,0.2016,0.3800"); + values ("-0.2116,-0.2009,-0.1853,-0.1599,-0.1189,-0.0456,0.0891",\ +"-0.2155,-0.2048,-0.1892,-0.1638,-0.1228,-0.0495,0.0852",\ +"-0.2193,-0.2086,-0.1930,-0.1676,-0.1266,-0.0533,0.0815",\ +"-0.2226,-0.2118,-0.1962,-0.1708,-0.1298,-0.0566,0.0782",\ +"-0.2350,-0.2243,-0.2087,-0.1833,-0.1422,-0.0690,0.0658",\ +"-0.2526,-0.2419,-0.2263,-0.2009,-0.1599,-0.0866,0.0481",\ +"-0.2801,-0.2694,-0.2538,-0.2284,-0.1874,-0.1141,0.0206"); + } + + fall_constraint("SIG2SRAM_constraint_template") { + index_1("0.0040,0.0176,0.0344,0.0656,0.1120,0.2016,0.3800"); + index_2("0.0040,0.0176,0.0344,0.0656,0.1120,0.2016,0.3800"); + values ("-0.1882,-0.1765,-0.1638,-0.1365,-0.0993,-0.0261,0.1018",\ +"-0.1921,-0.1804,-0.1677,-0.1403,-0.1032,-0.0300,0.0979",\ +"-0.1959,-0.1842,-0.1715,-0.1441,-0.1070,-0.0338,0.0941",\ +"-0.1991,-0.1874,-0.1747,-0.1474,-0.1103,-0.0370,0.0909",\ +"-0.2116,-0.1999,-0.1872,-0.1598,-0.1227,-0.0495,0.0784",\ +"-0.2292,-0.2175,-0.2048,-0.1774,-0.1403,-0.0671,0.0608",\ +"-0.2567,-0.2450,-0.2323,-0.2049,-0.1678,-0.0946,0.0333"); + } + } + + + timing() { + timing_type : hold_rising; + related_pin : "A_BIST_CLK"; + when : "(A_BIST_WEN & A_BIST_MEN)" + sdf_cond : "A_BIST_RW_ACCESS" + + rise_constraint("SIG2SRAM_constraint_template") { + index_1("0.0040,0.0176,0.0344,0.0656,0.1120,0.2016,0.3800"); + index_2("0.0040,0.0176,0.0344,0.0656,0.1120,0.2016,0.3800"); + values ("0.3170,0.3073,0.2916,0.2653,0.2282,0.1539,0.0192",\ +"0.3209,0.3111,0.2955,0.2691,0.2320,0.1578,0.0231",\ +"0.3247,0.3149,0.2993,0.2729,0.2358,0.1616,0.0269",\ +"0.3280,0.3182,0.3026,0.2762,0.2391,0.1649,0.0301",\ +"0.3404,0.3306,0.3150,0.2886,0.2515,0.1773,0.0426",\ +"0.3580,0.3482,0.3326,0.3063,0.2691,0.1949,0.0602",\ +"0.3855,0.3758,0.3601,0.3338,0.2966,0.2224,0.0877"); + } + + fall_constraint("SIG2SRAM_constraint_template") { + index_1("0.0040,0.0176,0.0344,0.0656,0.1120,0.2016,0.3800"); + index_2("0.0040,0.0176,0.0344,0.0656,0.1120,0.2016,0.3800"); + values ("0.2887,0.2780,0.2643,0.2369,0.2008,0.1285,-0.0013",\ +"0.2926,0.2818,0.2682,0.2408,0.2047,0.1324,0.0025",\ +"0.2964,0.2856,0.2720,0.2446,0.2085,0.1362,0.0063",\ +"0.2996,0.2889,0.2752,0.2479,0.2117,0.1395,0.0096",\ +"0.3121,0.3013,0.2877,0.2603,0.2242,0.1519,0.0220",\ +"0.3297,0.3189,0.3053,0.2779,0.2418,0.1695,0.0397",\ +"0.3572,0.3465,0.3328,0.3054,0.2693,0.1970,0.0672"); + } + } +} + pin(A_BIST_CLK) { + direction : input; + capacitance : 0.00389386; + max_transition : "0.38"; + clock : "true" ; + pin_func_type : active_rising ; + + timing () { + timing_type : "min_pulse_width"; + related_pin : "A_BIST_CLK"; + rise_constraint("CLKTRAN_constraint_template") { + index_1("0.004,0.38"); + values("0.12,0.12"); + } + } + + related_power_pin : VDD; + related_ground_pin : VSS; + + internal_power() { + when : "!A_BIST_MEN & !A_BIST_WEN & !A_BIST_REN"; + rise_power("scalar"){ + values (0); + } + fall_power("scalar"){ + values (0); + } + } + internal_power() { + when : "!A_BIST_MEN & A_BIST_WEN & !A_BIST_REN"; + rise_power("scalar"){ + values (0.6697); + } + fall_power("scalar"){ + values (0); + } + } + internal_power() { + when : "A_BIST_MEN & A_BIST_WEN & !A_BIST_REN"; + rise_power("scalar"){ + values (29.9728); + } + fall_power("scalar"){ + values (0); + } + } + internal_power() { + when : "A_BIST_MEN & A_BIST_WEN & A_BIST_REN"; + rise_power("scalar"){ + values (30.7463); + } + fall_power("scalar"){ + values (0); + } + } + internal_power() { + when : "A_BIST_MEN & !A_BIST_WEN & A_BIST_REN"; + rise_power("scalar"){ + values (24.5331); + } + fall_power("scalar"){ + values (0); + } + } + internal_power() { + when : "!A_BIST_MEN & !A_BIST_WEN & A_BIST_REN"; + rise_power("scalar"){ + values (0.4084); + } + fall_power("scalar"){ + values (0); + } + } + internal_power() { + when : "!A_BIST_MEN & A_BIST_WEN & A_BIST_REN"; + rise_power("scalar"){ + values (1.0137); + } + fall_power("scalar"){ + values (0); + } + } + internal_power() { + when : "A_BIST_MEN & !A_BIST_WEN & !A_BIST_REN"; + rise_power("scalar"){ + values (0); + } + fall_power("scalar"){ + values (0); + } + } + } + bus(A_BIST_DIN) { + bus_type : D_15_0; + direction : input ; + capacitance : 0.00397186 ; + memory_write() { + address : A_BIST_ADDR ; + clocked_on : A_BIST_CLK; + } + + max_transition : "0.38" ; + pin(A_BIST_DIN[15:0]) { + related_power_pin : VDD; + related_ground_pin : VSS; + internal_power() { + when : "A_BIST_MEN"; + rise_power("scalar"){ + values (0.0757); + } + fall_power("scalar"){ + values (0.0696); + } + } + internal_power() { + when : "!A_BIST_MEN"; + rise_power("scalar"){ + values (0.0977); + } + fall_power("scalar"){ + values (0.0801); + } + } + } + timing() { + timing_type : setup_rising; + related_pin : "A_BIST_CLK"; + when : "(A_BIST_WEN & A_BIST_MEN)"; + sdf_cond : "A_BIST_W_ACCESS"; + + rise_constraint("SIG2SRAM_constraint_template") { + index_1("0.0040,0.0176,0.0344,0.0656,0.1120,0.2016,0.3800"); + index_2("0.0040,0.0176,0.0344,0.0656,0.1120,0.2016,0.3800"); + values ("-0.2116,-0.2009,-0.1853,-0.1599,-0.1189,-0.0456,0.0891",\ +"-0.2155,-0.2048,-0.1892,-0.1638,-0.1228,-0.0495,0.0852",\ +"-0.2193,-0.2086,-0.1930,-0.1676,-0.1266,-0.0533,0.0815",\ +"-0.2226,-0.2118,-0.1962,-0.1708,-0.1298,-0.0566,0.0782",\ +"-0.2350,-0.2243,-0.2087,-0.1833,-0.1422,-0.0690,0.0658",\ +"-0.2526,-0.2419,-0.2263,-0.2009,-0.1599,-0.0866,0.0481",\ +"-0.2801,-0.2694,-0.2538,-0.2284,-0.1874,-0.1141,0.0206"); + } + + fall_constraint("SIG2SRAM_constraint_template") { + index_1("0.0040,0.0176,0.0344,0.0656,0.1120,0.2016,0.3800"); + index_2("0.0040,0.0176,0.0344,0.0656,0.1120,0.2016,0.3800"); + values ("-0.1882,-0.1765,-0.1638,-0.1365,-0.0993,-0.0261,0.1018",\ +"-0.1921,-0.1804,-0.1677,-0.1403,-0.1032,-0.0300,0.0979",\ +"-0.1959,-0.1842,-0.1715,-0.1441,-0.1070,-0.0338,0.0941",\ +"-0.1991,-0.1874,-0.1747,-0.1474,-0.1103,-0.0370,0.0909",\ +"-0.2116,-0.1999,-0.1872,-0.1598,-0.1227,-0.0495,0.0784",\ +"-0.2292,-0.2175,-0.2048,-0.1774,-0.1403,-0.0671,0.0608",\ +"-0.2567,-0.2450,-0.2323,-0.2049,-0.1678,-0.0946,0.0333"); + } + } + + timing() { + timing_type : hold_rising; + related_pin : "A_BIST_CLK"; + when : "(A_BIST_WEN & A_BIST_MEN)"; + sdf_cond : "A_BIST_W_ACCESS"; + + rise_constraint("SIG2SRAM_constraint_template") { + index_1("0.0040,0.0176,0.0344,0.0656,0.1120,0.2016,0.3800"); + index_2("0.0040,0.0176,0.0344,0.0656,0.1120,0.2016,0.3800"); + values ("0.3170,0.3073,0.2916,0.2653,0.2282,0.1539,0.0192",\ +"0.3209,0.3111,0.2955,0.2691,0.2320,0.1578,0.0231",\ +"0.3247,0.3149,0.2993,0.2729,0.2358,0.1616,0.0269",\ +"0.3280,0.3182,0.3026,0.2762,0.2391,0.1649,0.0301",\ +"0.3404,0.3306,0.3150,0.2886,0.2515,0.1773,0.0426",\ +"0.3580,0.3482,0.3326,0.3063,0.2691,0.1949,0.0602",\ +"0.3855,0.3758,0.3601,0.3338,0.2966,0.2224,0.0877"); + } + + fall_constraint("SIG2SRAM_constraint_template") { + index_1("0.0040,0.0176,0.0344,0.0656,0.1120,0.2016,0.3800"); + index_2("0.0040,0.0176,0.0344,0.0656,0.1120,0.2016,0.3800"); + values ("0.2887,0.2780,0.2643,0.2369,0.2008,0.1285,-0.0013",\ +"0.2926,0.2818,0.2682,0.2408,0.2047,0.1324,0.0025",\ +"0.2964,0.2856,0.2720,0.2446,0.2085,0.1362,0.0063",\ +"0.2996,0.2889,0.2752,0.2479,0.2117,0.1395,0.0096",\ +"0.3121,0.3013,0.2877,0.2603,0.2242,0.1519,0.0220",\ +"0.3297,0.3189,0.3053,0.2779,0.2418,0.1695,0.0397",\ +"0.3572,0.3465,0.3328,0.3054,0.2693,0.1970,0.0672"); + } + } + } + +bus(A_DOUT) { + + bus_type : D_15_0; + direction : output ; + capacitance : 0 ; + max_capacitance : 0.064 ; + memory_read() { + address : A_ADDR ; + } + pin(A_DOUT[15:0]) { + related_power_pin : VDD; + related_ground_pin : VSS; + internal_power() { + rise_power("scalar") { + values (0); + } + fall_power("scalar") { + values (0); + } + } + } + timing() { + related_pin : "A_CLK"; + timing_type : rising_edge ; + timing_sense : non_unate ; + + cell_rise(SIG2SRAM_delay_template) { + index_1("0.0040,0.0176,0.0344,0.0656,0.1120,0.2016,0.3800"); + index_2("0.0008,0.0014,0.0051,0.0100,0.0339,0.0640"); + values ("2.3227,2.3237,2.3285,2.3340,2.3549,2.3784",\ +"2.3291,2.3301,2.3349,2.3404,2.3613,2.3848",\ +"2.3307,2.3317,2.3365,2.3420,2.3629,2.3864",\ +"2.3350,2.3360,2.3408,2.3463,2.3672,2.3907",\ +"2.3482,2.3492,2.3540,2.3595,2.3804,2.4039",\ +"2.3667,2.3677,2.3725,2.3780,2.3989,2.4224",\ +"2.3932,2.3942,2.3990,2.4046,2.4255,2.4490"); + } + cell_fall(SIG2SRAM_delay_template) { + index_1("0.0040,0.0176,0.0344,0.0656,0.1120,0.2016,0.3800"); + index_2("0.0008,0.0014,0.0051,0.0100,0.0339,0.0640"); + values ("2.2884,2.2892,2.2933,2.2978,2.3149,2.3316",\ +"2.2948,2.2956,2.2997,2.3042,2.3213,2.3380",\ +"2.2964,2.2972,2.3013,2.3058,2.3229,2.3396",\ +"2.3007,2.3015,2.3056,2.3101,2.3272,2.3439",\ +"2.3139,2.3147,2.3188,2.3233,2.3404,2.3571",\ +"2.3324,2.3333,2.3373,2.3419,2.3589,2.3757",\ +"2.3589,2.3598,2.3638,2.3684,2.3855,2.4022"); + } + + rise_transition(SRAM_load_template) { + index_1("0.0008,0.0014,0.0051,0.0100,0.0339,0.0640"); + values ("0.0206,0.0210,0.0265,0.0323,0.0606,0.0955"); + } + fall_transition(SRAM_load_template) { + index_1("0.0008,0.0014,0.0051,0.0100,0.0339,0.0640"); + values ("0.0170,0.0177,0.0222,0.0270,0.0451,0.0644"); + } + } +} + pin(B_DLY) { + direction : input ; + capacitance : 0.00421562 ; + max_transition : "1" ; + related_power_pin : VDD; + related_ground_pin : VSS; + internal_power() { + rise_power("scalar") { + values (0); + } + fall_power("scalar") { + values (0); + } + } + } + +bus(B_ADDR) { + bus_type : A_8_0; + direction : input ; + capacitance : 0.0115194 ; + pin(B_ADDR[0]) { + capacitance : 0.0056487 ; + } + pin(B_ADDR[1]) { + capacitance : 0.00741688 ; + } + pin(B_ADDR[2]) { + capacitance : 0.0100613 ; + } + pin(B_ADDR[3]) { + capacitance : 0.00667339 ; + } + pin(B_ADDR[4]) { + capacitance : 0.00620204 ; + } + pin(B_ADDR[5]) { + capacitance : 0.0101975 ; + } + pin(B_ADDR[6]) { + capacitance : 0.0124055 ; + } + pin(B_ADDR[7]) { + capacitance : 0.0101065 ; + } + max_transition : "0.38" ; + pin(B_ADDR[8:0]) { + related_power_pin : VDD; + related_ground_pin : VSS; + internal_power() { + when : "B_MEN"; + rise_power("scalar"){ + values (0.0125); + } + fall_power("scalar"){ + values (0.0025); + } + } + internal_power() { + when : "!B_MEN"; + rise_power("scalar"){ + values (0.0288); + } + fall_power("scalar"){ + values (0.0013); + } + } + } + timing() { + timing_type : setup_rising; + related_pin : "B_CLK"; + when : "((B_WEN | B_REN)& B_MEN)" + sdf_cond : "B_RW_ACCESS" + + rise_constraint("SIG2SRAM_constraint_template") { + index_1("0.0040,0.0176,0.0344,0.0656,0.1120,0.2016,0.3800"); + index_2("0.0040,0.0176,0.0344,0.0656,0.1120,0.2016,0.3800"); + values ("-0.2371,-0.2215,-0.2098,-0.1824,-0.1434,-0.0691,0.0676",\ +"-0.2449,-0.2332,-0.2176,-0.1902,-0.1551,-0.0770,0.0559",\ +"-0.2605,-0.2488,-0.2332,-0.2059,-0.1707,-0.0965,0.0441",\ +"-0.2879,-0.2723,-0.2605,-0.2332,-0.1941,-0.1199,0.0168",\ +"-0.3230,-0.3113,-0.2996,-0.2723,-0.2332,-0.1590,-0.0184",\ +"-0.4012,-0.3895,-0.3738,-0.3465,-0.3074,-0.2332,-0.0965",\ +"-0.5379,-0.5262,-0.5105,-0.4832,-0.4480,-0.3699,-0.2332"); + } + + fall_constraint("SIG2SRAM_constraint_template") { + index_1("0.0040,0.0176,0.0344,0.0656,0.1120,0.2016,0.3800"); + index_2("0.0040,0.0176,0.0344,0.0656,0.1120,0.2016,0.3800"); + values ("-0.1785,-0.1707,-0.1551,-0.1277,-0.0887,-0.0184,0.1145",\ +"-0.1902,-0.1785,-0.1629,-0.1355,-0.1004,-0.0262,0.1027",\ +"-0.2059,-0.1941,-0.1785,-0.1512,-0.1160,-0.0418,0.0871",\ +"-0.2293,-0.2176,-0.2059,-0.1785,-0.1434,-0.0691,0.0598",\ +"-0.2684,-0.2566,-0.2449,-0.2176,-0.1824,-0.1082,0.0207",\ +"-0.3465,-0.3348,-0.3191,-0.2918,-0.2566,-0.1824,-0.0535",\ +"-0.4832,-0.4715,-0.4559,-0.4324,-0.3934,-0.3191,-0.1902"); + } + } + + + timing() { + timing_type : hold_rising; + related_pin : "B_CLK"; + when : "((B_WEN | B_REN)& B_MEN)" + sdf_cond : "B_RW_ACCESS" + + rise_constraint("SIG2SRAM_constraint_template") { + index_1("0.0040,0.0176,0.0344,0.0656,0.1120,0.2016,0.3800"); + index_2("0.0040,0.0176,0.0344,0.0656,0.1120,0.2016,0.3800"); + values ("0.3410,0.3293,0.3137,0.2863,0.2473,0.1730,0.0324",\ +"0.3488,0.3371,0.3215,0.2941,0.2590,0.1809,0.0480",\ +"0.3684,0.3527,0.3371,0.3098,0.2746,0.1965,0.0598",\ +"0.3918,0.3762,0.3645,0.3371,0.2980,0.2238,0.0871",\ +"0.4309,0.4152,0.4035,0.3762,0.3371,0.2629,0.1223",\ +"0.5051,0.4934,0.4777,0.4504,0.4113,0.3371,0.1965",\ +"0.6418,0.6262,0.6145,0.5871,0.5520,0.4738,0.3332"); + } + + fall_constraint("SIG2SRAM_constraint_template") { + index_1("0.0040,0.0176,0.0344,0.0656,0.1120,0.2016,0.3800"); + index_2("0.0040,0.0176,0.0344,0.0656,0.1120,0.2016,0.3800"); + values ("0.2824,0.2707,0.2551,0.2277,0.1926,0.1184,-0.0105",\ +"0.2902,0.2785,0.2668,0.2395,0.2043,0.1301,0.0012",\ +"0.3059,0.2941,0.2824,0.2551,0.2199,0.1457,0.0168",\ +"0.3332,0.3215,0.3059,0.2785,0.2434,0.1691,0.0402",\ +"0.3723,0.3605,0.3449,0.3176,0.2824,0.2121,0.0793",\ +"0.4465,0.4348,0.4230,0.3918,0.3566,0.2824,0.1535",\ +"0.5832,0.5715,0.5598,0.5324,0.4934,0.4191,0.2902"); + } + } +} +pin(B_WEN) { + direction : input ; + capacitance : 0.00341384 ; + max_transition : "0.38" ; + related_power_pin : VDD; + related_ground_pin : VSS; + internal_power() { + when : "B_MEN"; + rise_power("scalar"){ + values (0.0076); + } + fall_power("scalar"){ + values (0.0137); + } + } + internal_power() { + when : "!B_MEN"; + rise_power("scalar"){ + values (0.0073); + } + fall_power("scalar"){ + values (0.0261); + } + } + timing() { + timing_type : setup_rising; + related_pin : "B_CLK"; + when : "B_MEN" + sdf_cond : "B_MEN" + + rise_constraint("SIG2SRAM_constraint_template") { + index_1("0.0040,0.0176,0.0344,0.0656,0.1120,0.2016,0.3800"); + index_2("0.0040,0.0176,0.0344,0.0656,0.1120,0.2016,0.3800"); + values ("0.1418,0.1496,0.1652,0.1887,0.2316,0.3059,0.4465",\ +"0.1301,0.1379,0.1535,0.1809,0.2199,0.2941,0.4348",\ +"0.1145,0.1262,0.1379,0.1652,0.2043,0.2785,0.4191",\ +"0.0871,0.0949,0.1105,0.1379,0.1770,0.2512,0.3879",\ +"0.0480,0.0598,0.0754,0.0988,0.1379,0.2082,0.3527",\ +"-0.0262,-0.0145,0.0012,0.0246,0.0676,0.1379,0.2785",\ +"-0.1668,-0.1551,-0.1395,-0.1121,-0.0730,0.0012,0.1418"); + } + + fall_constraint("SIG2SRAM_constraint_template") { + index_1("0.0040,0.0176,0.0344,0.0656,0.1120,0.2016,0.3800"); + index_2("0.0040,0.0176,0.0344,0.0656,0.1120,0.2016,0.3800"); + values ("0.2082,0.2160,0.2316,0.2590,0.2941,0.3684,0.5012",\ +"0.1926,0.2043,0.2199,0.2473,0.2824,0.3566,0.4895",\ +"0.1770,0.1887,0.2043,0.2316,0.2668,0.3410,0.4777",\ +"0.1535,0.1652,0.1770,0.2043,0.2395,0.3137,0.4504",\ +"0.1145,0.1262,0.1379,0.1652,0.2043,0.2746,0.4113",\ +"0.0402,0.0520,0.0676,0.0910,0.1262,0.2004,0.3332",\ +"-0.0965,-0.0848,-0.0730,-0.0457,-0.0066,0.0637,0.2004"); + } + } + + + timing() { + timing_type : hold_rising; + related_pin : "B_CLK"; + when : "B_MEN" + sdf_cond : "B_MEN" + + rise_constraint("SIG2SRAM_constraint_template") { + index_1("0.0040,0.0176,0.0344,0.0656,0.1120,0.2016,0.3800"); + index_2("0.0040,0.0176,0.0344,0.0656,0.1120,0.2016,0.3800"); + values ("0.1770,0.1652,0.1496,0.1223,0.0793,0.0090,-0.1316",\ +"0.1848,0.1730,0.1574,0.1301,0.0910,0.0168,-0.1199",\ +"0.2004,0.1887,0.1770,0.1496,0.1066,0.0363,-0.1043",\ +"0.2277,0.2160,0.2004,0.1730,0.1340,0.0598,-0.0809",\ +"0.2668,0.2551,0.2395,0.2121,0.1730,0.0988,-0.0418",\ +"0.3410,0.3293,0.3137,0.2863,0.2434,0.1730,0.0324",\ +"0.4816,0.4699,0.4543,0.4230,0.3801,0.3098,0.1730"); + } + + fall_constraint("SIG2SRAM_constraint_template") { + index_1("0.0040,0.0176,0.0344,0.0656,0.1120,0.2016,0.3800"); + index_2("0.0040,0.0176,0.0344,0.0656,0.1120,0.2016,0.3800"); + values ("0.1613,0.1496,0.1379,0.1066,0.0715,0.0012,-0.1355",\ +"0.1730,0.1613,0.1457,0.1184,0.0832,0.0129,-0.1238",\ +"0.1887,0.1770,0.1613,0.1340,0.0988,0.0246,-0.1121",\ +"0.2121,0.2043,0.1887,0.1613,0.1223,0.0520,-0.0848",\ +"0.2512,0.2434,0.2277,0.2004,0.1613,0.0910,-0.0457",\ +"0.3254,0.3176,0.3020,0.2746,0.2355,0.1652,0.0324",\ +"0.4660,0.4543,0.4387,0.4113,0.3723,0.3020,0.1691"); + } + } + } +pin(B_REN) { + direction : input ; + capacitance : 0.00390661 ; + max_transition : "0.38" ; + related_power_pin : VDD; + related_ground_pin : VSS; + internal_power() { + when : "B_MEN"; + rise_power("scalar"){ + values (0.0069); + } + fall_power("scalar"){ + values (0.0122); + } + } + internal_power() { + when : "!B_MEN"; + rise_power("scalar"){ + values (0.0243); + } + fall_power("scalar"){ + values (0.0202); + } + } + timing() { + timing_type : setup_rising; + related_pin : "B_CLK"; + when : "B_MEN" + sdf_cond : "B_MEN" + + rise_constraint("SIG2SRAM_constraint_template") { + index_1("0.0040,0.0176,0.0344,0.0656,0.1120,0.2016,0.3800"); + index_2("0.0040,0.0176,0.0344,0.0656,0.1120,0.2016,0.3800"); + values ("-0.0027,0.0090,0.0246,0.0520,0.0910,0.1613,0.3020",\ +"-0.0105,0.0012,0.0129,0.0363,0.0793,0.1535,0.2902",\ +"-0.0262,-0.0145,-0.0027,0.0246,0.0637,0.1379,0.2785",\ +"-0.0535,-0.0418,-0.0262,0.0012,0.0363,0.1105,0.2512",\ +"-0.0926,-0.0809,-0.0652,-0.0418,-0.0027,0.0715,0.2121",\ +"-0.1668,-0.1551,-0.1395,-0.1082,-0.0770,-0.0027,0.1379",\ +"-0.3035,-0.2918,-0.2762,-0.2488,-0.2137,-0.1434,-0.0027"); + } + + fall_constraint("SIG2SRAM_constraint_template") { + index_1("0.0040,0.0176,0.0344,0.0656,0.1120,0.2016,0.3800"); + index_2("0.0040,0.0176,0.0344,0.0656,0.1120,0.2016,0.3800"); + values ("0.0832,0.0949,0.1105,0.1379,0.1730,0.2473,0.3801",\ +"0.0754,0.0832,0.0988,0.1223,0.1613,0.2355,0.3684",\ +"0.0598,0.0676,0.0832,0.1066,0.1457,0.2121,0.3527",\ +"0.0324,0.0441,0.0598,0.0871,0.1223,0.1926,0.3293",\ +"-0.0066,0.0051,0.0168,0.0480,0.0832,0.1535,0.2902",\ +"-0.0809,-0.0691,-0.0574,-0.0301,0.0090,0.0832,0.2121",\ +"-0.2176,-0.2059,-0.1941,-0.1668,-0.1277,-0.0574,0.0793"); + } + } + + + timing() { + timing_type : hold_rising; + related_pin : "B_CLK"; + when : "B_MEN" + sdf_cond : "B_MEN" + + rise_constraint("SIG2SRAM_constraint_template") { + index_1("0.0040,0.0176,0.0344,0.0656,0.1120,0.2016,0.3800"); + index_2("0.0040,0.0176,0.0344,0.0656,0.1120,0.2016,0.3800"); + values ("0.1887,0.1770,0.1613,0.1340,0.0949,0.0207,-0.1160",\ +"0.1965,0.1848,0.1730,0.1457,0.1027,0.0324,-0.1082",\ +"0.2160,0.2004,0.1887,0.1613,0.1184,0.0480,-0.0926",\ +"0.2395,0.2277,0.2121,0.1848,0.1457,0.0715,-0.0652",\ +"0.2785,0.2668,0.2512,0.2238,0.1848,0.1105,-0.0262",\ +"0.3527,0.3410,0.3254,0.2980,0.2551,0.1848,0.0480",\ +"0.4934,0.4816,0.4660,0.4387,0.3957,0.3254,0.1887"); + } + + fall_constraint("SIG2SRAM_constraint_template") { + index_1("0.0040,0.0176,0.0344,0.0656,0.1120,0.2016,0.3800"); + index_2("0.0040,0.0176,0.0344,0.0656,0.1120,0.2016,0.3800"); + values ("0.1730,0.1613,0.1496,0.1184,0.0793,0.0129,-0.1238",\ +"0.1848,0.1730,0.1574,0.1301,0.0910,0.0207,-0.1121",\ +"0.2004,0.1887,0.1730,0.1457,0.1066,0.0363,-0.1004",\ +"0.2238,0.2121,0.2004,0.1691,0.1340,0.0598,-0.0730",\ +"0.2629,0.2512,0.2395,0.2121,0.1691,0.0988,-0.0340",\ +"0.3371,0.3254,0.3137,0.2863,0.2434,0.1730,0.0402",\ +"0.4777,0.4660,0.4504,0.4230,0.3840,0.3137,0.1809"); + } + } + } +pin(B_MEN) { + direction : input ; + capacitance : 0.00326046 ; + max_transition : "0.38" ; + related_power_pin : VDD; + related_ground_pin : VSS; + internal_power() { + rise_power("scalar"){ + values (0.1674); + } + fall_power("scalar"){ + values (0.0108); + } + } + timing() { + timing_type : setup_rising; + related_pin : "B_CLK"; + + rise_constraint("SIG2SRAM_constraint_template") { + index_1("0.0040,0.0176,0.0344,0.0656,0.1120,0.2016,0.3800"); + index_2("0.0040,0.0176,0.0344,0.0656,0.1120,0.2016,0.3800"); + values ("0.1418,0.1496,0.1652,0.1926,0.2316,0.3059,0.4465",\ +"0.1301,0.1379,0.1535,0.1809,0.2199,0.2941,0.4348",\ +"0.1145,0.1262,0.1418,0.1652,0.2043,0.2785,0.4191",\ +"0.0871,0.0949,0.1105,0.1379,0.1770,0.2512,0.3879",\ +"0.0480,0.0598,0.0754,0.0988,0.1379,0.2082,0.3488",\ +"-0.0262,-0.0145,0.0012,0.0285,0.0676,0.1379,0.2785",\ +"-0.1668,-0.1551,-0.1395,-0.1121,-0.0730,0.0012,0.1379"); + } + + fall_constraint("SIG2SRAM_constraint_template") { + index_1("0.0040,0.0176,0.0344,0.0656,0.1120,0.2016,0.3800"); + index_2("0.0040,0.0176,0.0344,0.0656,0.1120,0.2016,0.3800"); + values ("0.2082,0.2199,0.2316,0.2590,0.2980,0.3723,0.5051",\ +"0.1965,0.2082,0.2199,0.2473,0.2863,0.3605,0.4934",\ +"0.1809,0.1926,0.2043,0.2316,0.2707,0.3449,0.4777",\ +"0.1574,0.1691,0.1809,0.2082,0.2434,0.3176,0.4543",\ +"0.1145,0.1262,0.1418,0.1691,0.2043,0.2785,0.4113",\ +"0.0441,0.0559,0.0676,0.0949,0.1301,0.2004,0.3332",\ +"-0.0965,-0.0848,-0.0691,-0.0418,-0.0066,0.0676,0.2004"); + } + } + + + timing() { + timing_type : hold_rising; + related_pin : "B_CLK"; + + rise_constraint("SIG2SRAM_constraint_template") { + index_1("0.0040,0.0176,0.0344,0.0656,0.1120,0.2016,0.3800"); + index_2("0.0040,0.0176,0.0344,0.0656,0.1120,0.2016,0.3800"); + values ("0.1770,0.1652,0.1535,0.1262,0.0832,0.0129,-0.1277",\ +"0.1887,0.1770,0.1613,0.1340,0.0949,0.0207,-0.1199",\ +"0.2043,0.1926,0.1770,0.1496,0.1105,0.0363,-0.1043",\ +"0.2277,0.2160,0.2043,0.1770,0.1379,0.0598,-0.0770",\ +"0.2668,0.2551,0.2434,0.2160,0.1730,0.0988,-0.0379",\ +"0.3449,0.3332,0.3176,0.2902,0.2473,0.1730,0.0363",\ +"0.4816,0.4699,0.4543,0.4270,0.3840,0.3098,0.1770"); + } + + fall_constraint("SIG2SRAM_constraint_template") { + index_1("0.0040,0.0176,0.0344,0.0656,0.1120,0.2016,0.3800"); + index_2("0.0040,0.0176,0.0344,0.0656,0.1120,0.2016,0.3800"); + values ("0.1613,0.1496,0.1379,0.1105,0.0715,0.0012,-0.1355",\ +"0.1730,0.1613,0.1496,0.1184,0.0832,0.0129,-0.1238",\ +"0.1887,0.1770,0.1652,0.1340,0.0988,0.0285,-0.1121",\ +"0.2121,0.2043,0.1887,0.1613,0.1223,0.0520,-0.0848",\ +"0.2551,0.2434,0.2277,0.2004,0.1613,0.0910,-0.0418",\ +"0.3293,0.3176,0.3020,0.2746,0.2395,0.1652,0.0324",\ +"0.4660,0.4543,0.4426,0.4113,0.3762,0.3020,0.1691"); + } + } + } +bus(B_BM) { + bus_type : D_15_0; + direction : input ; + capacitance : 0.00334781 ; + max_transition : "0.38" ; + pin(B_BM[15:0]) { + related_power_pin : VDD; + related_ground_pin : VSS; + internal_power() { + when : "B_MEN"; + rise_power("scalar"){ + values (0.0757); + } + fall_power("scalar"){ + values (0.0696); + } + } + internal_power() { + when : "!B_MEN"; + rise_power("scalar"){ + values (0.0977); + } + fall_power("scalar"){ + values (0.0801); + } + } + } + timing() { + timing_type : setup_rising; + related_pin : "B_CLK"; + when : "(B_WEN & B_MEN)" + sdf_cond : "B_RW_ACCESS" + + rise_constraint("SIG2SRAM_constraint_template") { + index_1("0.0040,0.0176,0.0344,0.0656,0.1120,0.2016,0.3800"); + index_2("0.0040,0.0176,0.0344,0.0656,0.1120,0.2016,0.3800"); + values ("-0.2116,-0.2009,-0.1853,-0.1599,-0.1189,-0.0456,0.0891",\ +"-0.2155,-0.2048,-0.1892,-0.1638,-0.1228,-0.0495,0.0852",\ +"-0.2193,-0.2086,-0.1930,-0.1676,-0.1266,-0.0533,0.0815",\ +"-0.2226,-0.2118,-0.1962,-0.1708,-0.1298,-0.0566,0.0782",\ +"-0.2350,-0.2243,-0.2087,-0.1833,-0.1422,-0.0690,0.0658",\ +"-0.2526,-0.2419,-0.2263,-0.2009,-0.1599,-0.0866,0.0481",\ +"-0.2801,-0.2694,-0.2538,-0.2284,-0.1874,-0.1141,0.0206"); + } + + fall_constraint("SIG2SRAM_constraint_template") { + index_1("0.0040,0.0176,0.0344,0.0656,0.1120,0.2016,0.3800"); + index_2("0.0040,0.0176,0.0344,0.0656,0.1120,0.2016,0.3800"); + values ("-0.1882,-0.1765,-0.1638,-0.1365,-0.0993,-0.0261,0.1018",\ +"-0.1921,-0.1804,-0.1677,-0.1403,-0.1032,-0.0300,0.0979",\ +"-0.1959,-0.1842,-0.1715,-0.1441,-0.1070,-0.0338,0.0941",\ +"-0.1991,-0.1874,-0.1747,-0.1474,-0.1103,-0.0370,0.0909",\ +"-0.2116,-0.1999,-0.1872,-0.1598,-0.1227,-0.0495,0.0784",\ +"-0.2292,-0.2175,-0.2048,-0.1774,-0.1403,-0.0671,0.0608",\ +"-0.2567,-0.2450,-0.2323,-0.2049,-0.1678,-0.0946,0.0333"); + } + } + + + timing() { + timing_type : hold_rising; + related_pin : "B_CLK"; + when : "(B_WEN & B_MEN)" + sdf_cond : "B_RW_ACCESS" + + rise_constraint("SIG2SRAM_constraint_template") { + index_1("0.0040,0.0176,0.0344,0.0656,0.1120,0.2016,0.3800"); + index_2("0.0040,0.0176,0.0344,0.0656,0.1120,0.2016,0.3800"); + values ("0.3170,0.3073,0.2916,0.2653,0.2282,0.1539,0.0192",\ +"0.3209,0.3111,0.2955,0.2691,0.2320,0.1578,0.0231",\ +"0.3247,0.3149,0.2993,0.2729,0.2358,0.1616,0.0269",\ +"0.3280,0.3182,0.3026,0.2762,0.2391,0.1649,0.0301",\ +"0.3404,0.3306,0.3150,0.2886,0.2515,0.1773,0.0426",\ +"0.3580,0.3482,0.3326,0.3063,0.2691,0.1949,0.0602",\ +"0.3855,0.3758,0.3601,0.3338,0.2966,0.2224,0.0877"); + } + + fall_constraint("SIG2SRAM_constraint_template") { + index_1("0.0040,0.0176,0.0344,0.0656,0.1120,0.2016,0.3800"); + index_2("0.0040,0.0176,0.0344,0.0656,0.1120,0.2016,0.3800"); + values ("0.2887,0.2780,0.2643,0.2369,0.2008,0.1285,-0.0013",\ +"0.2926,0.2818,0.2682,0.2408,0.2047,0.1324,0.0025",\ +"0.2964,0.2856,0.2720,0.2446,0.2085,0.1362,0.0063",\ +"0.2996,0.2889,0.2752,0.2479,0.2117,0.1395,0.0096",\ +"0.3121,0.3013,0.2877,0.2603,0.2242,0.1519,0.0220",\ +"0.3297,0.3189,0.3053,0.2779,0.2418,0.1695,0.0397",\ +"0.3572,0.3465,0.3328,0.3054,0.2693,0.1970,0.0672"); + } + } +} + pin(B_CLK) { + direction : input; + capacitance : 0.00389386; + max_transition : "0.38"; + clock : "true" ; + pin_func_type : active_rising ; + + timing () { + timing_type : "min_pulse_width"; + related_pin : "B_CLK"; + rise_constraint("CLKTRAN_constraint_template") { + index_1("0.004,0.38"); + values("0.12,0.12"); + } + } + + related_power_pin : VDD; + related_ground_pin : VSS; + + internal_power() { + when : "!B_MEN & !B_WEN & !B_REN"; + rise_power("scalar"){ + values (0); + } + fall_power("scalar"){ + values (0); + } + } + internal_power() { + when : "!B_MEN & B_WEN & !B_REN"; + rise_power("scalar"){ + values (0.6697); + } + fall_power("scalar"){ + values (0); + } + } + internal_power() { + when : "B_MEN & B_WEN & !B_REN"; + rise_power("scalar"){ + values (29.9728); + } + fall_power("scalar"){ + values (0); + } + } + internal_power() { + when : "B_MEN & B_WEN & B_REN"; + rise_power("scalar"){ + values (30.7463); + } + fall_power("scalar"){ + values (0); + } + } + internal_power() { + when : "B_MEN & !B_WEN & B_REN"; + rise_power("scalar"){ + values (24.5331); + } + fall_power("scalar"){ + values (0); + } + } + internal_power() { + when : "!B_MEN & !B_WEN & B_REN"; + rise_power("scalar"){ + values (0.4084); + } + fall_power("scalar"){ + values (0); + } + } + internal_power() { + when : "!B_MEN & B_WEN & B_REN"; + rise_power("scalar"){ + values (1.0137); + } + fall_power("scalar"){ + values (0); + } + } + internal_power() { + when : "B_MEN & !B_WEN & !B_REN"; + rise_power("scalar"){ + values (0); + } + fall_power("scalar"){ + values (0); + } + } + } + bus(B_DIN) { + bus_type : D_15_0; + direction : input ; + capacitance : 0.00468868 ; + memory_write() { + address : B_ADDR ; + clocked_on : B_CLK; + } + + max_transition : "0.38" ; + pin(B_DIN[15:0]) { + related_power_pin : VDD; + related_ground_pin : VSS; + internal_power() { + when : "B_MEN"; + rise_power("scalar"){ + values (0.0757); + } + fall_power("scalar"){ + values (0.0696); + } + } + internal_power() { + when : "!B_MEN"; + rise_power("scalar"){ + values (0.0977); + } + fall_power("scalar"){ + values (0.0801); + } + } + } + timing() { + timing_type : setup_rising; + related_pin : "B_CLK"; + when : "(B_WEN & B_MEN)"; + sdf_cond : "B_W_ACCESS"; + + rise_constraint("SIG2SRAM_constraint_template") { + index_1("0.0040,0.0176,0.0344,0.0656,0.1120,0.2016,0.3800"); + index_2("0.0040,0.0176,0.0344,0.0656,0.1120,0.2016,0.3800"); + values ("-0.2116,-0.2009,-0.1853,-0.1599,-0.1189,-0.0456,0.0891",\ +"-0.2155,-0.2048,-0.1892,-0.1638,-0.1228,-0.0495,0.0852",\ +"-0.2193,-0.2086,-0.1930,-0.1676,-0.1266,-0.0533,0.0815",\ +"-0.2226,-0.2118,-0.1962,-0.1708,-0.1298,-0.0566,0.0782",\ +"-0.2350,-0.2243,-0.2087,-0.1833,-0.1422,-0.0690,0.0658",\ +"-0.2526,-0.2419,-0.2263,-0.2009,-0.1599,-0.0866,0.0481",\ +"-0.2801,-0.2694,-0.2538,-0.2284,-0.1874,-0.1141,0.0206"); + } + + fall_constraint("SIG2SRAM_constraint_template") { + index_1("0.0040,0.0176,0.0344,0.0656,0.1120,0.2016,0.3800"); + index_2("0.0040,0.0176,0.0344,0.0656,0.1120,0.2016,0.3800"); + values ("-0.1882,-0.1765,-0.1638,-0.1365,-0.0993,-0.0261,0.1018",\ +"-0.1921,-0.1804,-0.1677,-0.1403,-0.1032,-0.0300,0.0979",\ +"-0.1959,-0.1842,-0.1715,-0.1441,-0.1070,-0.0338,0.0941",\ +"-0.1991,-0.1874,-0.1747,-0.1474,-0.1103,-0.0370,0.0909",\ +"-0.2116,-0.1999,-0.1872,-0.1598,-0.1227,-0.0495,0.0784",\ +"-0.2292,-0.2175,-0.2048,-0.1774,-0.1403,-0.0671,0.0608",\ +"-0.2567,-0.2450,-0.2323,-0.2049,-0.1678,-0.0946,0.0333"); + } + } + + timing() { + timing_type : hold_rising; + related_pin : "B_CLK"; + when : "(B_WEN & B_MEN)"; + sdf_cond : "B_W_ACCESS"; + + rise_constraint("SIG2SRAM_constraint_template") { + index_1("0.0040,0.0176,0.0344,0.0656,0.1120,0.2016,0.3800"); + index_2("0.0040,0.0176,0.0344,0.0656,0.1120,0.2016,0.3800"); + values ("0.3170,0.3073,0.2916,0.2653,0.2282,0.1539,0.0192",\ +"0.3209,0.3111,0.2955,0.2691,0.2320,0.1578,0.0231",\ +"0.3247,0.3149,0.2993,0.2729,0.2358,0.1616,0.0269",\ +"0.3280,0.3182,0.3026,0.2762,0.2391,0.1649,0.0301",\ +"0.3404,0.3306,0.3150,0.2886,0.2515,0.1773,0.0426",\ +"0.3580,0.3482,0.3326,0.3063,0.2691,0.1949,0.0602",\ +"0.3855,0.3758,0.3601,0.3338,0.2966,0.2224,0.0877"); + } + + fall_constraint("SIG2SRAM_constraint_template") { + index_1("0.0040,0.0176,0.0344,0.0656,0.1120,0.2016,0.3800"); + index_2("0.0040,0.0176,0.0344,0.0656,0.1120,0.2016,0.3800"); + values ("0.2887,0.2780,0.2643,0.2369,0.2008,0.1285,-0.0013",\ +"0.2926,0.2818,0.2682,0.2408,0.2047,0.1324,0.0025",\ +"0.2964,0.2856,0.2720,0.2446,0.2085,0.1362,0.0063",\ +"0.2996,0.2889,0.2752,0.2479,0.2117,0.1395,0.0096",\ +"0.3121,0.3013,0.2877,0.2603,0.2242,0.1519,0.0220",\ +"0.3297,0.3189,0.3053,0.2779,0.2418,0.1695,0.0397",\ +"0.3572,0.3465,0.3328,0.3054,0.2693,0.1970,0.0672"); + } + } + } + + pin(B_BIST_EN) { + direction : input ; + capacitance : 0.00421562 ; + max_transition : "1" ; + related_power_pin : VDD; + related_ground_pin : VSS; + internal_power() { + rise_power("scalar") { + values (0); + } + fall_power("scalar") { + values (0); + } + } + } + +bus(B_BIST_ADDR) { + bus_type : A_8_0; + direction : input ; + capacitance : 0.0115194 ; + pin(B_BIST_ADDR[0]) { + capacitance : 0.0056487 ; + } + pin(B_BIST_ADDR[1]) { + capacitance : 0.00741688 ; + } + pin(B_BIST_ADDR[2]) { + capacitance : 0.0100613 ; + } + pin(B_BIST_ADDR[3]) { + capacitance : 0.00667339 ; + } + pin(B_BIST_ADDR[4]) { + capacitance : 0.00620204 ; + } + pin(B_BIST_ADDR[5]) { + capacitance : 0.0101975 ; + } + pin(B_BIST_ADDR[6]) { + capacitance : 0.0124055 ; + } + pin(B_BIST_ADDR[7]) { + capacitance : 0.0101065 ; + } + max_transition : "0.38" ; + pin(B_BIST_ADDR[8:0]) { + related_power_pin : VDD; + related_ground_pin : VSS; + internal_power() { + when : "B_BIST_MEN"; + rise_power("scalar"){ + values (0.0125); + } + fall_power("scalar"){ + values (0.0025); + } + } + internal_power() { + when : "!B_BIST_MEN"; + rise_power("scalar"){ + values (0.0288); + } + fall_power("scalar"){ + values (0.0013); + } + } + } + timing() { + timing_type : setup_rising; + related_pin : "B_BIST_CLK"; + when : "((B_BIST_WEN | B_BIST_REN)& B_BIST_MEN)" + sdf_cond : "B_BIST_RW_ACCESS" + + rise_constraint("SIG2SRAM_constraint_template") { + index_1("0.0040,0.0176,0.0344,0.0656,0.1120,0.2016,0.3800"); + index_2("0.0040,0.0176,0.0344,0.0656,0.1120,0.2016,0.3800"); + values ("-0.2371,-0.2215,-0.2098,-0.1824,-0.1434,-0.0691,0.0676",\ +"-0.2449,-0.2332,-0.2176,-0.1902,-0.1551,-0.0770,0.0559",\ +"-0.2605,-0.2488,-0.2332,-0.2059,-0.1707,-0.0965,0.0441",\ +"-0.2879,-0.2723,-0.2605,-0.2332,-0.1941,-0.1199,0.0168",\ +"-0.3230,-0.3113,-0.2996,-0.2723,-0.2332,-0.1590,-0.0184",\ +"-0.4012,-0.3895,-0.3738,-0.3465,-0.3074,-0.2332,-0.0965",\ +"-0.5379,-0.5262,-0.5105,-0.4832,-0.4480,-0.3699,-0.2332"); + } + + fall_constraint("SIG2SRAM_constraint_template") { + index_1("0.0040,0.0176,0.0344,0.0656,0.1120,0.2016,0.3800"); + index_2("0.0040,0.0176,0.0344,0.0656,0.1120,0.2016,0.3800"); + values ("-0.1785,-0.1707,-0.1551,-0.1277,-0.0887,-0.0184,0.1145",\ +"-0.1902,-0.1785,-0.1629,-0.1355,-0.1004,-0.0262,0.1027",\ +"-0.2059,-0.1941,-0.1785,-0.1512,-0.1160,-0.0418,0.0871",\ +"-0.2293,-0.2176,-0.2059,-0.1785,-0.1434,-0.0691,0.0598",\ +"-0.2684,-0.2566,-0.2449,-0.2176,-0.1824,-0.1082,0.0207",\ +"-0.3465,-0.3348,-0.3191,-0.2918,-0.2566,-0.1824,-0.0535",\ +"-0.4832,-0.4715,-0.4559,-0.4324,-0.3934,-0.3191,-0.1902"); + } + } + + + timing() { + timing_type : hold_rising; + related_pin : "B_BIST_CLK"; + when : "((B_BIST_WEN | B_BIST_REN)& B_BIST_MEN)" + sdf_cond : "B_BIST_RW_ACCESS" + + rise_constraint("SIG2SRAM_constraint_template") { + index_1("0.0040,0.0176,0.0344,0.0656,0.1120,0.2016,0.3800"); + index_2("0.0040,0.0176,0.0344,0.0656,0.1120,0.2016,0.3800"); + values ("0.3410,0.3293,0.3137,0.2863,0.2473,0.1730,0.0324",\ +"0.3488,0.3371,0.3215,0.2941,0.2590,0.1809,0.0480",\ +"0.3684,0.3527,0.3371,0.3098,0.2746,0.1965,0.0598",\ +"0.3918,0.3762,0.3645,0.3371,0.2980,0.2238,0.0871",\ +"0.4309,0.4152,0.4035,0.3762,0.3371,0.2629,0.1223",\ +"0.5051,0.4934,0.4777,0.4504,0.4113,0.3371,0.1965",\ +"0.6418,0.6262,0.6145,0.5871,0.5520,0.4738,0.3332"); + } + + fall_constraint("SIG2SRAM_constraint_template") { + index_1("0.0040,0.0176,0.0344,0.0656,0.1120,0.2016,0.3800"); + index_2("0.0040,0.0176,0.0344,0.0656,0.1120,0.2016,0.3800"); + values ("0.2824,0.2707,0.2551,0.2277,0.1926,0.1184,-0.0105",\ +"0.2902,0.2785,0.2668,0.2395,0.2043,0.1301,0.0012",\ +"0.3059,0.2941,0.2824,0.2551,0.2199,0.1457,0.0168",\ +"0.3332,0.3215,0.3059,0.2785,0.2434,0.1691,0.0402",\ +"0.3723,0.3605,0.3449,0.3176,0.2824,0.2121,0.0793",\ +"0.4465,0.4348,0.4230,0.3918,0.3566,0.2824,0.1535",\ +"0.5832,0.5715,0.5598,0.5324,0.4934,0.4191,0.2902"); + } + } +} +pin(B_BIST_WEN) { + direction : input ; + capacitance : 0.00341384 ; + max_transition : "0.38" ; + related_power_pin : VDD; + related_ground_pin : VSS; + internal_power() { + when : "B_BIST_MEN"; + rise_power("scalar"){ + values (0.0076); + } + fall_power("scalar"){ + values (0.0137); + } + } + internal_power() { + when : "!B_BIST_MEN"; + rise_power("scalar"){ + values (0.0073); + } + fall_power("scalar"){ + values (0.0261); + } + } + timing() { + timing_type : setup_rising; + related_pin : "B_BIST_CLK"; + when : "B_BIST_MEN" + sdf_cond : "B_BIST_MEN" + + rise_constraint("SIG2SRAM_constraint_template") { + index_1("0.0040,0.0176,0.0344,0.0656,0.1120,0.2016,0.3800"); + index_2("0.0040,0.0176,0.0344,0.0656,0.1120,0.2016,0.3800"); + values ("0.1418,0.1496,0.1652,0.1887,0.2316,0.3059,0.4465",\ +"0.1301,0.1379,0.1535,0.1809,0.2199,0.2941,0.4348",\ +"0.1145,0.1262,0.1379,0.1652,0.2043,0.2785,0.4191",\ +"0.0871,0.0949,0.1105,0.1379,0.1770,0.2512,0.3879",\ +"0.0480,0.0598,0.0754,0.0988,0.1379,0.2082,0.3527",\ +"-0.0262,-0.0145,0.0012,0.0246,0.0676,0.1379,0.2785",\ +"-0.1668,-0.1551,-0.1395,-0.1121,-0.0730,0.0012,0.1418"); + } + + fall_constraint("SIG2SRAM_constraint_template") { + index_1("0.0040,0.0176,0.0344,0.0656,0.1120,0.2016,0.3800"); + index_2("0.0040,0.0176,0.0344,0.0656,0.1120,0.2016,0.3800"); + values ("0.2082,0.2160,0.2316,0.2590,0.2941,0.3684,0.5012",\ +"0.1926,0.2043,0.2199,0.2473,0.2824,0.3566,0.4895",\ +"0.1770,0.1887,0.2043,0.2316,0.2668,0.3410,0.4777",\ +"0.1535,0.1652,0.1770,0.2043,0.2395,0.3137,0.4504",\ +"0.1145,0.1262,0.1379,0.1652,0.2043,0.2746,0.4113",\ +"0.0402,0.0520,0.0676,0.0910,0.1262,0.2004,0.3332",\ +"-0.0965,-0.0848,-0.0730,-0.0457,-0.0066,0.0637,0.2004"); + } + } + + + timing() { + timing_type : hold_rising; + related_pin : "B_BIST_CLK"; + when : "B_BIST_MEN" + sdf_cond : "B_BIST_MEN" + + rise_constraint("SIG2SRAM_constraint_template") { + index_1("0.0040,0.0176,0.0344,0.0656,0.1120,0.2016,0.3800"); + index_2("0.0040,0.0176,0.0344,0.0656,0.1120,0.2016,0.3800"); + values ("0.1770,0.1652,0.1496,0.1223,0.0793,0.0090,-0.1316",\ +"0.1848,0.1730,0.1574,0.1301,0.0910,0.0168,-0.1199",\ +"0.2004,0.1887,0.1770,0.1496,0.1066,0.0363,-0.1043",\ +"0.2277,0.2160,0.2004,0.1730,0.1340,0.0598,-0.0809",\ +"0.2668,0.2551,0.2395,0.2121,0.1730,0.0988,-0.0418",\ +"0.3410,0.3293,0.3137,0.2863,0.2434,0.1730,0.0324",\ +"0.4816,0.4699,0.4543,0.4230,0.3801,0.3098,0.1730"); + } + + fall_constraint("SIG2SRAM_constraint_template") { + index_1("0.0040,0.0176,0.0344,0.0656,0.1120,0.2016,0.3800"); + index_2("0.0040,0.0176,0.0344,0.0656,0.1120,0.2016,0.3800"); + values ("0.1613,0.1496,0.1379,0.1066,0.0715,0.0012,-0.1355",\ +"0.1730,0.1613,0.1457,0.1184,0.0832,0.0129,-0.1238",\ +"0.1887,0.1770,0.1613,0.1340,0.0988,0.0246,-0.1121",\ +"0.2121,0.2043,0.1887,0.1613,0.1223,0.0520,-0.0848",\ +"0.2512,0.2434,0.2277,0.2004,0.1613,0.0910,-0.0457",\ +"0.3254,0.3176,0.3020,0.2746,0.2355,0.1652,0.0324",\ +"0.4660,0.4543,0.4387,0.4113,0.3723,0.3020,0.1691"); + } + } + } +pin(B_BIST_REN) { + direction : input ; + capacitance : 0.00390661 ; + max_transition : "0.38" ; + related_power_pin : VDD; + related_ground_pin : VSS; + internal_power() { + when : "B_BIST_MEN"; + rise_power("scalar"){ + values (0.0069); + } + fall_power("scalar"){ + values (0.0122); + } + } + internal_power() { + when : "!B_BIST_MEN"; + rise_power("scalar"){ + values (0.0243); + } + fall_power("scalar"){ + values (0.0202); + } + } + timing() { + timing_type : setup_rising; + related_pin : "B_BIST_CLK"; + when : "B_BIST_MEN" + sdf_cond : "B_BIST_MEN" + + rise_constraint("SIG2SRAM_constraint_template") { + index_1("0.0040,0.0176,0.0344,0.0656,0.1120,0.2016,0.3800"); + index_2("0.0040,0.0176,0.0344,0.0656,0.1120,0.2016,0.3800"); + values ("-0.0027,0.0090,0.0246,0.0520,0.0910,0.1613,0.3020",\ +"-0.0105,0.0012,0.0129,0.0363,0.0793,0.1535,0.2902",\ +"-0.0262,-0.0145,-0.0027,0.0246,0.0637,0.1379,0.2785",\ +"-0.0535,-0.0418,-0.0262,0.0012,0.0363,0.1105,0.2512",\ +"-0.0926,-0.0809,-0.0652,-0.0418,-0.0027,0.0715,0.2121",\ +"-0.1668,-0.1551,-0.1395,-0.1082,-0.0770,-0.0027,0.1379",\ +"-0.3035,-0.2918,-0.2762,-0.2488,-0.2137,-0.1434,-0.0027"); + } + + fall_constraint("SIG2SRAM_constraint_template") { + index_1("0.0040,0.0176,0.0344,0.0656,0.1120,0.2016,0.3800"); + index_2("0.0040,0.0176,0.0344,0.0656,0.1120,0.2016,0.3800"); + values ("0.0832,0.0949,0.1105,0.1379,0.1730,0.2473,0.3801",\ +"0.0754,0.0832,0.0988,0.1223,0.1613,0.2355,0.3684",\ +"0.0598,0.0676,0.0832,0.1066,0.1457,0.2121,0.3527",\ +"0.0324,0.0441,0.0598,0.0871,0.1223,0.1926,0.3293",\ +"-0.0066,0.0051,0.0168,0.0480,0.0832,0.1535,0.2902",\ +"-0.0809,-0.0691,-0.0574,-0.0301,0.0090,0.0832,0.2121",\ +"-0.2176,-0.2059,-0.1941,-0.1668,-0.1277,-0.0574,0.0793"); + } + } + + + timing() { + timing_type : hold_rising; + related_pin : "B_BIST_CLK"; + when : "B_BIST_MEN" + sdf_cond : "B_BIST_MEN" + + rise_constraint("SIG2SRAM_constraint_template") { + index_1("0.0040,0.0176,0.0344,0.0656,0.1120,0.2016,0.3800"); + index_2("0.0040,0.0176,0.0344,0.0656,0.1120,0.2016,0.3800"); + values ("0.1887,0.1770,0.1613,0.1340,0.0949,0.0207,-0.1160",\ +"0.1965,0.1848,0.1730,0.1457,0.1027,0.0324,-0.1082",\ +"0.2160,0.2004,0.1887,0.1613,0.1184,0.0480,-0.0926",\ +"0.2395,0.2277,0.2121,0.1848,0.1457,0.0715,-0.0652",\ +"0.2785,0.2668,0.2512,0.2238,0.1848,0.1105,-0.0262",\ +"0.3527,0.3410,0.3254,0.2980,0.2551,0.1848,0.0480",\ +"0.4934,0.4816,0.4660,0.4387,0.3957,0.3254,0.1887"); + } + + fall_constraint("SIG2SRAM_constraint_template") { + index_1("0.0040,0.0176,0.0344,0.0656,0.1120,0.2016,0.3800"); + index_2("0.0040,0.0176,0.0344,0.0656,0.1120,0.2016,0.3800"); + values ("0.1730,0.1613,0.1496,0.1184,0.0793,0.0129,-0.1238",\ +"0.1848,0.1730,0.1574,0.1301,0.0910,0.0207,-0.1121",\ +"0.2004,0.1887,0.1730,0.1457,0.1066,0.0363,-0.1004",\ +"0.2238,0.2121,0.2004,0.1691,0.1340,0.0598,-0.0730",\ +"0.2629,0.2512,0.2395,0.2121,0.1691,0.0988,-0.0340",\ +"0.3371,0.3254,0.3137,0.2863,0.2434,0.1730,0.0402",\ +"0.4777,0.4660,0.4504,0.4230,0.3840,0.3137,0.1809"); + } + } + } +pin(B_BIST_MEN) { + direction : input ; + capacitance : 0.00326046 ; + max_transition : "0.38" ; + related_power_pin : VDD; + related_ground_pin : VSS; + internal_power() { + rise_power("scalar"){ + values (0.1674); + } + fall_power("scalar"){ + values (0.0108); + } + } + timing() { + timing_type : setup_rising; + related_pin : "B_BIST_CLK"; + + rise_constraint("SIG2SRAM_constraint_template") { + index_1("0.0040,0.0176,0.0344,0.0656,0.1120,0.2016,0.3800"); + index_2("0.0040,0.0176,0.0344,0.0656,0.1120,0.2016,0.3800"); + values ("0.1418,0.1496,0.1652,0.1926,0.2316,0.3059,0.4465",\ +"0.1301,0.1379,0.1535,0.1809,0.2199,0.2941,0.4348",\ +"0.1145,0.1262,0.1418,0.1652,0.2043,0.2785,0.4191",\ +"0.0871,0.0949,0.1105,0.1379,0.1770,0.2512,0.3879",\ +"0.0480,0.0598,0.0754,0.0988,0.1379,0.2082,0.3488",\ +"-0.0262,-0.0145,0.0012,0.0285,0.0676,0.1379,0.2785",\ +"-0.1668,-0.1551,-0.1395,-0.1121,-0.0730,0.0012,0.1379"); + } + + fall_constraint("SIG2SRAM_constraint_template") { + index_1("0.0040,0.0176,0.0344,0.0656,0.1120,0.2016,0.3800"); + index_2("0.0040,0.0176,0.0344,0.0656,0.1120,0.2016,0.3800"); + values ("0.2082,0.2199,0.2316,0.2590,0.2980,0.3723,0.5051",\ +"0.1965,0.2082,0.2199,0.2473,0.2863,0.3605,0.4934",\ +"0.1809,0.1926,0.2043,0.2316,0.2707,0.3449,0.4777",\ +"0.1574,0.1691,0.1809,0.2082,0.2434,0.3176,0.4543",\ +"0.1145,0.1262,0.1418,0.1691,0.2043,0.2785,0.4113",\ +"0.0441,0.0559,0.0676,0.0949,0.1301,0.2004,0.3332",\ +"-0.0965,-0.0848,-0.0691,-0.0418,-0.0066,0.0676,0.2004"); + } + } + + + timing() { + timing_type : hold_rising; + related_pin : "B_BIST_CLK"; + + rise_constraint("SIG2SRAM_constraint_template") { + index_1("0.0040,0.0176,0.0344,0.0656,0.1120,0.2016,0.3800"); + index_2("0.0040,0.0176,0.0344,0.0656,0.1120,0.2016,0.3800"); + values ("0.1770,0.1652,0.1535,0.1262,0.0832,0.0129,-0.1277",\ +"0.1887,0.1770,0.1613,0.1340,0.0949,0.0207,-0.1199",\ +"0.2043,0.1926,0.1770,0.1496,0.1105,0.0363,-0.1043",\ +"0.2277,0.2160,0.2043,0.1770,0.1379,0.0598,-0.0770",\ +"0.2668,0.2551,0.2434,0.2160,0.1730,0.0988,-0.0379",\ +"0.3449,0.3332,0.3176,0.2902,0.2473,0.1730,0.0363",\ +"0.4816,0.4699,0.4543,0.4270,0.3840,0.3098,0.1770"); + } + + fall_constraint("SIG2SRAM_constraint_template") { + index_1("0.0040,0.0176,0.0344,0.0656,0.1120,0.2016,0.3800"); + index_2("0.0040,0.0176,0.0344,0.0656,0.1120,0.2016,0.3800"); + values ("0.1613,0.1496,0.1379,0.1105,0.0715,0.0012,-0.1355",\ +"0.1730,0.1613,0.1496,0.1184,0.0832,0.0129,-0.1238",\ +"0.1887,0.1770,0.1652,0.1340,0.0988,0.0285,-0.1121",\ +"0.2121,0.2043,0.1887,0.1613,0.1223,0.0520,-0.0848",\ +"0.2551,0.2434,0.2277,0.2004,0.1613,0.0910,-0.0418",\ +"0.3293,0.3176,0.3020,0.2746,0.2395,0.1652,0.0324",\ +"0.4660,0.4543,0.4426,0.4113,0.3762,0.3020,0.1691"); + } + } + } +bus(B_BIST_BM) { + bus_type : D_15_0; + direction : input ; + capacitance : 0.00290564 ; + max_transition : "0.38" ; + pin(B_BIST_BM[15:0]) { + related_power_pin : VDD; + related_ground_pin : VSS; + internal_power() { + when : "B_BIST_MEN"; + rise_power("scalar"){ + values (0.0757); + } + fall_power("scalar"){ + values (0.0696); + } + } + internal_power() { + when : "!B_BIST_MEN"; + rise_power("scalar"){ + values (0.0977); + } + fall_power("scalar"){ + values (0.0801); + } + } + } + timing() { + timing_type : setup_rising; + related_pin : "B_BIST_CLK"; + when : "(B_BIST_WEN & B_BIST_MEN)" + sdf_cond : "B_BIST_RW_ACCESS" + + rise_constraint("SIG2SRAM_constraint_template") { + index_1("0.0040,0.0176,0.0344,0.0656,0.1120,0.2016,0.3800"); + index_2("0.0040,0.0176,0.0344,0.0656,0.1120,0.2016,0.3800"); + values ("-0.2116,-0.2009,-0.1853,-0.1599,-0.1189,-0.0456,0.0891",\ +"-0.2155,-0.2048,-0.1892,-0.1638,-0.1228,-0.0495,0.0852",\ +"-0.2193,-0.2086,-0.1930,-0.1676,-0.1266,-0.0533,0.0815",\ +"-0.2226,-0.2118,-0.1962,-0.1708,-0.1298,-0.0566,0.0782",\ +"-0.2350,-0.2243,-0.2087,-0.1833,-0.1422,-0.0690,0.0658",\ +"-0.2526,-0.2419,-0.2263,-0.2009,-0.1599,-0.0866,0.0481",\ +"-0.2801,-0.2694,-0.2538,-0.2284,-0.1874,-0.1141,0.0206"); + } + + fall_constraint("SIG2SRAM_constraint_template") { + index_1("0.0040,0.0176,0.0344,0.0656,0.1120,0.2016,0.3800"); + index_2("0.0040,0.0176,0.0344,0.0656,0.1120,0.2016,0.3800"); + values ("-0.1882,-0.1765,-0.1638,-0.1365,-0.0993,-0.0261,0.1018",\ +"-0.1921,-0.1804,-0.1677,-0.1403,-0.1032,-0.0300,0.0979",\ +"-0.1959,-0.1842,-0.1715,-0.1441,-0.1070,-0.0338,0.0941",\ +"-0.1991,-0.1874,-0.1747,-0.1474,-0.1103,-0.0370,0.0909",\ +"-0.2116,-0.1999,-0.1872,-0.1598,-0.1227,-0.0495,0.0784",\ +"-0.2292,-0.2175,-0.2048,-0.1774,-0.1403,-0.0671,0.0608",\ +"-0.2567,-0.2450,-0.2323,-0.2049,-0.1678,-0.0946,0.0333"); + } + } + + + timing() { + timing_type : hold_rising; + related_pin : "B_BIST_CLK"; + when : "(B_BIST_WEN & B_BIST_MEN)" + sdf_cond : "B_BIST_RW_ACCESS" + + rise_constraint("SIG2SRAM_constraint_template") { + index_1("0.0040,0.0176,0.0344,0.0656,0.1120,0.2016,0.3800"); + index_2("0.0040,0.0176,0.0344,0.0656,0.1120,0.2016,0.3800"); + values ("0.3170,0.3073,0.2916,0.2653,0.2282,0.1539,0.0192",\ +"0.3209,0.3111,0.2955,0.2691,0.2320,0.1578,0.0231",\ +"0.3247,0.3149,0.2993,0.2729,0.2358,0.1616,0.0269",\ +"0.3280,0.3182,0.3026,0.2762,0.2391,0.1649,0.0301",\ +"0.3404,0.3306,0.3150,0.2886,0.2515,0.1773,0.0426",\ +"0.3580,0.3482,0.3326,0.3063,0.2691,0.1949,0.0602",\ +"0.3855,0.3758,0.3601,0.3338,0.2966,0.2224,0.0877"); + } + + fall_constraint("SIG2SRAM_constraint_template") { + index_1("0.0040,0.0176,0.0344,0.0656,0.1120,0.2016,0.3800"); + index_2("0.0040,0.0176,0.0344,0.0656,0.1120,0.2016,0.3800"); + values ("0.2887,0.2780,0.2643,0.2369,0.2008,0.1285,-0.0013",\ +"0.2926,0.2818,0.2682,0.2408,0.2047,0.1324,0.0025",\ +"0.2964,0.2856,0.2720,0.2446,0.2085,0.1362,0.0063",\ +"0.2996,0.2889,0.2752,0.2479,0.2117,0.1395,0.0096",\ +"0.3121,0.3013,0.2877,0.2603,0.2242,0.1519,0.0220",\ +"0.3297,0.3189,0.3053,0.2779,0.2418,0.1695,0.0397",\ +"0.3572,0.3465,0.3328,0.3054,0.2693,0.1970,0.0672"); + } + } +} + pin(B_BIST_CLK) { + direction : input; + capacitance : 0.00389386; + max_transition : "0.38"; + clock : "true" ; + pin_func_type : active_rising ; + + timing () { + timing_type : "min_pulse_width"; + related_pin : "B_BIST_CLK"; + rise_constraint("CLKTRAN_constraint_template") { + index_1("0.004,0.38"); + values("0.12,0.12"); + } + } + + related_power_pin : VDD; + related_ground_pin : VSS; + + internal_power() { + when : "!B_BIST_MEN & !B_BIST_WEN & !B_BIST_REN"; + rise_power("scalar"){ + values (0); + } + fall_power("scalar"){ + values (0); + } + } + internal_power() { + when : "!B_BIST_MEN & B_BIST_WEN & !B_BIST_REN"; + rise_power("scalar"){ + values (0.6697); + } + fall_power("scalar"){ + values (0); + } + } + internal_power() { + when : "B_BIST_MEN & B_BIST_WEN & !B_BIST_REN"; + rise_power("scalar"){ + values (29.9728); + } + fall_power("scalar"){ + values (0); + } + } + internal_power() { + when : "B_BIST_MEN & B_BIST_WEN & B_BIST_REN"; + rise_power("scalar"){ + values (30.7463); + } + fall_power("scalar"){ + values (0); + } + } + internal_power() { + when : "B_BIST_MEN & !B_BIST_WEN & B_BIST_REN"; + rise_power("scalar"){ + values (24.5331); + } + fall_power("scalar"){ + values (0); + } + } + internal_power() { + when : "!B_BIST_MEN & !B_BIST_WEN & B_BIST_REN"; + rise_power("scalar"){ + values (0.4084); + } + fall_power("scalar"){ + values (0); + } + } + internal_power() { + when : "!B_BIST_MEN & B_BIST_WEN & B_BIST_REN"; + rise_power("scalar"){ + values (1.0137); + } + fall_power("scalar"){ + values (0); + } + } + internal_power() { + when : "B_BIST_MEN & !B_BIST_WEN & !B_BIST_REN"; + rise_power("scalar"){ + values (0); + } + fall_power("scalar"){ + values (0); + } + } + } + bus(B_BIST_DIN) { + bus_type : D_15_0; + direction : input ; + capacitance : 0.00417898 ; + memory_write() { + address : B_BIST_ADDR ; + clocked_on : B_BIST_CLK; + } + + max_transition : "0.38" ; + pin(B_BIST_DIN[15:0]) { + related_power_pin : VDD; + related_ground_pin : VSS; + internal_power() { + when : "B_BIST_MEN"; + rise_power("scalar"){ + values (0.0757); + } + fall_power("scalar"){ + values (0.0696); + } + } + internal_power() { + when : "!B_BIST_MEN"; + rise_power("scalar"){ + values (0.0977); + } + fall_power("scalar"){ + values (0.0801); + } + } + } + timing() { + timing_type : setup_rising; + related_pin : "B_BIST_CLK"; + when : "(B_BIST_WEN & B_BIST_MEN)"; + sdf_cond : "B_BIST_W_ACCESS"; + + rise_constraint("SIG2SRAM_constraint_template") { + index_1("0.0040,0.0176,0.0344,0.0656,0.1120,0.2016,0.3800"); + index_2("0.0040,0.0176,0.0344,0.0656,0.1120,0.2016,0.3800"); + values ("-0.2116,-0.2009,-0.1853,-0.1599,-0.1189,-0.0456,0.0891",\ +"-0.2155,-0.2048,-0.1892,-0.1638,-0.1228,-0.0495,0.0852",\ +"-0.2193,-0.2086,-0.1930,-0.1676,-0.1266,-0.0533,0.0815",\ +"-0.2226,-0.2118,-0.1962,-0.1708,-0.1298,-0.0566,0.0782",\ +"-0.2350,-0.2243,-0.2087,-0.1833,-0.1422,-0.0690,0.0658",\ +"-0.2526,-0.2419,-0.2263,-0.2009,-0.1599,-0.0866,0.0481",\ +"-0.2801,-0.2694,-0.2538,-0.2284,-0.1874,-0.1141,0.0206"); + } + + fall_constraint("SIG2SRAM_constraint_template") { + index_1("0.0040,0.0176,0.0344,0.0656,0.1120,0.2016,0.3800"); + index_2("0.0040,0.0176,0.0344,0.0656,0.1120,0.2016,0.3800"); + values ("-0.1882,-0.1765,-0.1638,-0.1365,-0.0993,-0.0261,0.1018",\ +"-0.1921,-0.1804,-0.1677,-0.1403,-0.1032,-0.0300,0.0979",\ +"-0.1959,-0.1842,-0.1715,-0.1441,-0.1070,-0.0338,0.0941",\ +"-0.1991,-0.1874,-0.1747,-0.1474,-0.1103,-0.0370,0.0909",\ +"-0.2116,-0.1999,-0.1872,-0.1598,-0.1227,-0.0495,0.0784",\ +"-0.2292,-0.2175,-0.2048,-0.1774,-0.1403,-0.0671,0.0608",\ +"-0.2567,-0.2450,-0.2323,-0.2049,-0.1678,-0.0946,0.0333"); + } + } + + timing() { + timing_type : hold_rising; + related_pin : "B_BIST_CLK"; + when : "(B_BIST_WEN & B_BIST_MEN)"; + sdf_cond : "B_BIST_W_ACCESS"; + + rise_constraint("SIG2SRAM_constraint_template") { + index_1("0.0040,0.0176,0.0344,0.0656,0.1120,0.2016,0.3800"); + index_2("0.0040,0.0176,0.0344,0.0656,0.1120,0.2016,0.3800"); + values ("0.3170,0.3073,0.2916,0.2653,0.2282,0.1539,0.0192",\ +"0.3209,0.3111,0.2955,0.2691,0.2320,0.1578,0.0231",\ +"0.3247,0.3149,0.2993,0.2729,0.2358,0.1616,0.0269",\ +"0.3280,0.3182,0.3026,0.2762,0.2391,0.1649,0.0301",\ +"0.3404,0.3306,0.3150,0.2886,0.2515,0.1773,0.0426",\ +"0.3580,0.3482,0.3326,0.3063,0.2691,0.1949,0.0602",\ +"0.3855,0.3758,0.3601,0.3338,0.2966,0.2224,0.0877"); + } + + fall_constraint("SIG2SRAM_constraint_template") { + index_1("0.0040,0.0176,0.0344,0.0656,0.1120,0.2016,0.3800"); + index_2("0.0040,0.0176,0.0344,0.0656,0.1120,0.2016,0.3800"); + values ("0.2887,0.2780,0.2643,0.2369,0.2008,0.1285,-0.0013",\ +"0.2926,0.2818,0.2682,0.2408,0.2047,0.1324,0.0025",\ +"0.2964,0.2856,0.2720,0.2446,0.2085,0.1362,0.0063",\ +"0.2996,0.2889,0.2752,0.2479,0.2117,0.1395,0.0096",\ +"0.3121,0.3013,0.2877,0.2603,0.2242,0.1519,0.0220",\ +"0.3297,0.3189,0.3053,0.2779,0.2418,0.1695,0.0397",\ +"0.3572,0.3465,0.3328,0.3054,0.2693,0.1970,0.0672"); + } + } + } + +bus(B_DOUT) { + + bus_type : D_15_0; + direction : output ; + capacitance : 0 ; + max_capacitance : 0.064 ; + memory_read() { + address : B_ADDR ; + } + pin(B_DOUT[15:0]) { + related_power_pin : VDD; + related_ground_pin : VSS; + internal_power() { + rise_power("scalar") { + values (0); + } + fall_power("scalar") { + values (0); + } + } + } + timing() { + related_pin : "B_CLK"; + timing_type : rising_edge ; + timing_sense : non_unate ; + + cell_rise(SIG2SRAM_delay_template) { + index_1("0.0040,0.0176,0.0344,0.0656,0.1120,0.2016,0.3800"); + index_2("0.0008,0.0014,0.0051,0.0100,0.0339,0.0640"); + values ("2.3227,2.3237,2.3285,2.3340,2.3549,2.3784",\ +"2.3291,2.3301,2.3349,2.3404,2.3613,2.3848",\ +"2.3307,2.3317,2.3365,2.3420,2.3629,2.3864",\ +"2.3350,2.3360,2.3408,2.3463,2.3672,2.3907",\ +"2.3482,2.3492,2.3540,2.3595,2.3804,2.4039",\ +"2.3667,2.3677,2.3725,2.3780,2.3989,2.4224",\ +"2.3932,2.3942,2.3990,2.4046,2.4255,2.4490"); + } + cell_fall(SIG2SRAM_delay_template) { + index_1("0.0040,0.0176,0.0344,0.0656,0.1120,0.2016,0.3800"); + index_2("0.0008,0.0014,0.0051,0.0100,0.0339,0.0640"); + values ("2.2884,2.2892,2.2933,2.2978,2.3149,2.3316",\ +"2.2948,2.2956,2.2997,2.3042,2.3213,2.3380",\ +"2.2964,2.2972,2.3013,2.3058,2.3229,2.3396",\ +"2.3007,2.3015,2.3056,2.3101,2.3272,2.3439",\ +"2.3139,2.3147,2.3188,2.3233,2.3404,2.3571",\ +"2.3324,2.3333,2.3373,2.3419,2.3589,2.3757",\ +"2.3589,2.3598,2.3638,2.3684,2.3855,2.4022"); + } + + rise_transition(SRAM_load_template) { + index_1("0.0008,0.0014,0.0051,0.0100,0.0339,0.0640"); + values ("0.0206,0.0210,0.0265,0.0323,0.0606,0.0955"); + } + fall_transition(SRAM_load_template) { + index_1("0.0008,0.0014,0.0051,0.0100,0.0339,0.0640"); + values ("0.0170,0.0177,0.0222,0.0270,0.0451,0.0644"); + } + } +} +cell_leakage_power : 451.7069; +} +} diff --git a/flow/platforms/ihp-sg13g2/lib/RM_IHPSG13_2P_512x16_c2_bm_bist_slow_1p08V_125C.lib b/flow/platforms/ihp-sg13g2/lib/RM_IHPSG13_2P_512x16_c2_bm_bist_slow_1p08V_125C.lib new file mode 100644 index 0000000000..8954cb0343 --- /dev/null +++ b/flow/platforms/ihp-sg13g2/lib/RM_IHPSG13_2P_512x16_c2_bm_bist_slow_1p08V_125C.lib @@ -0,0 +1,2886 @@ +/* ------------------------------------------------------*/ +/**/ +/* Copyright 2025 IHP PDK Authors*/ +/**/ +/* Licensed under the Apache License, Version 2.0 (the "License");*/ +/* you may not use this file except in compliance with the License.*/ +/* You may obtain a copy of the License at*/ +/* */ +/* https://www.apache.org/licenses/LICENSE-2.0*/ +/* */ +/* Unless required by applicable law or agreed to in writing, software*/ +/* distributed under the License is distributed on an "AS IS" BASIS,*/ +/* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.*/ +/* See the License for the specific language governing permissions and*/ +/* limitations under the License.*/ +/* */ +/* Generated on Wed Aug 27 13:18:08 2025 */ +/* */ +/* ------------------------------------------------------ */ +library(RM_IHPSG13_2P_512x16_c2_bm_bist_slow_1p08V_125C) { + technology (cmos) ; + delay_model : table_lookup ; + define ("add_pg_pin_to_lib", "library", "boolean"); + add_pg_pin_to_lib : true; + voltage_map ( VDD, 1.08); + voltage_map ( VDDARRAY, 1.08); + voltage_map ( VSS, 0.000000 ); + + date : "Wed Aug 27 13:18:07 2025" ; + comment : "IHP Microelectronics GmbH, 2023" ; + revision : 1.0.0 ; + simulation : true ; + nom_process : 1 ; + nom_temperature : 125 ; + nom_voltage : 1.08 ; + + operating_conditions("slow_1p08V_125C"){ + process : 1 ; + temperature : 125 ; + voltage : 1.08 ; + tree_type : "balanced_tree" ; + } + + default_operating_conditions : slow_1p08V_125C ; + default_max_transition : 1.0 ; + default_fanout_load : 1.0 ; + default_inout_pin_cap : 0.0 ; + default_input_pin_cap : 0.0 ; + default_output_pin_cap : 0.0 ; + default_cell_leakage_power : 0.0 ; + default_leakage_power_density : 0.0 ; + + slew_lower_threshold_pct_rise : 30 ; + slew_upper_threshold_pct_rise : 70 ; + input_threshold_pct_fall : 50 ; + output_threshold_pct_fall : 50 ; + input_threshold_pct_rise : 50 ; + output_threshold_pct_rise : 50 ; + slew_lower_threshold_pct_fall : 30 ; + slew_upper_threshold_pct_fall : 70 ; + slew_derate_from_library : 0.5; + k_volt_cell_leakage_power : 0.0 ; + k_temp_cell_leakage_power : 0.0 ; + k_process_cell_leakage_power : 0.0 ; + k_volt_internal_power : 0.0 ; + k_temp_internal_power : 0.0 ; + k_process_internal_power : 0.0 ; + + capacitive_load_unit (1,pf) ; + voltage_unit : "1V" ; + current_unit : "1uA" ; + time_unit : "1ns" ; + leakage_power_unit : "1nW" ; + pulling_resistance_unit : "1kohm"; + /* + ------------------------------------------------------------------------------------------ + implicit units overview: + cell_area unit : "um" + internal_power unit : "1e-12 * J/toggle = 1 * uW/MHz" + (capacitive_load_unit * voltage_unit^2) per toggle event + ------------------------------------------------------------------------------------------ + */ + library_features(report_delay_calculation); + define_cell_area (pad_drivers,pad_driver_sites) ; + + lu_table_template(CLKTRAN_constraint_template) { + variable_1 : constrained_pin_transition; + index_1 ( "0.010, 0.050, 0.200, 0.400, 1.000" ); + } + lu_table_template(SRAM_load_template) { + variable_1 : total_output_net_capacitance; + index_1 ( "0.0008,0.0014,0.0051,0.0100,0.0339,0.0640" ); + } + lu_table_template(SIG2SRAM_constraint_template) { + variable_1 : related_pin_transition; + variable_2 : constrained_pin_transition; + index_1 ( "0.0080,0.0288,0.0616,0.1072,0.1920,0.3496,0.5952" ); + index_2 ( "0.0080,0.0288,0.0616,0.1072,0.1920,0.3496,0.5952" ); + } + + lu_table_template(SIG2SRAM_delay_template) { + variable_1 : input_net_transition; + variable_2 : total_output_net_capacitance; + index_1 ( "0.0080,0.0288,0.0616,0.1072,0.1920,0.3496,0.5952" ); + index_2 ( "0.0008,0.0014,0.0051,0.0100,0.0339,0.0640" ); + } + + type (D_15_0) { + base_type : array; + data_type : bit; + bit_width : 16; + bit_from : 15; + bit_to : 0; + downto : true; + } + + type (A_8_0) { + base_type : array; + data_type : bit; + bit_width : 9; + bit_from : 8; + bit_to : 0; + downto : true; + } + +cell(RM_IHPSG13_2P_512x16_c2_bm_bist) { +pg_pin (VDD) { + pg_type : primary_power; + voltage_name : VDD; +} +pg_pin (VDDARRAY) { + pg_type : primary_power; + voltage_name : VDDARRAY; +} +pg_pin (VSS) { + pg_type : primary_ground; + voltage_name : VSS; +} + +memory() { + type : ram; + address_width : 9; + word_width : 16; +} + +interface_timing : false; +bus_naming_style : "%s[%d]" ; +area : 88481.5997 ; + + pin(A_DLY) { + direction : input ; + capacitance : 0.00387999 ; + max_transition : "1" ; + related_power_pin : VDD; + related_ground_pin : VSS; + internal_power() { + rise_power("scalar") { + values (0); + } + fall_power("scalar") { + values (0); + } + } + } + +bus(A_ADDR) { + bus_type : A_8_0; + direction : input ; + capacitance : 0.0129586 ; + pin(A_ADDR[0]) { + capacitance : 0.0058687 ; + } + pin(A_ADDR[1]) { + capacitance : 0.00807137 ; + } + pin(A_ADDR[2]) { + capacitance : 0.0112051 ; + } + pin(A_ADDR[3]) { + capacitance : 0.00709524 ; + } + pin(A_ADDR[4]) { + capacitance : 0.00648778 ; + } + pin(A_ADDR[5]) { + capacitance : 0.011209 ; + } + pin(A_ADDR[6]) { + capacitance : 0.0140441 ; + } + pin(A_ADDR[7]) { + capacitance : 0.0111199 ; + } + max_transition : "0.5952" ; + pin(A_ADDR[8:0]) { + related_power_pin : VDD; + related_ground_pin : VSS; + internal_power() { + when : "A_MEN"; + rise_power("scalar"){ + values (0.0102); + } + fall_power("scalar"){ + values (0.0078); + } + } + internal_power() { + when : "!A_MEN"; + rise_power("scalar"){ + values (0.0149); + } + fall_power("scalar"){ + values (0.0029); + } + } + } + timing() { + timing_type : setup_rising; + related_pin : "A_CLK"; + when : "((A_WEN | A_REN)& A_MEN)" + sdf_cond : "A_RW_ACCESS" + + rise_constraint("SIG2SRAM_constraint_template") { + index_1("0.0080,0.0288,0.0616,0.1072,0.1920,0.3496,0.5952"); + index_2("0.0080,0.0288,0.0616,0.1072,0.1920,0.3496,0.5952"); + values ("-0.7371,-0.7176,-0.6863,-0.6434,-0.5652,-0.4168,-0.1980",\ +"-0.7566,-0.7371,-0.7059,-0.6629,-0.5848,-0.4363,-0.2137",\ +"-0.7879,-0.7645,-0.7332,-0.6902,-0.6121,-0.4637,-0.2449",\ +"-0.8309,-0.8074,-0.7762,-0.7332,-0.6551,-0.5066,-0.2879",\ +"-0.9051,-0.8895,-0.8543,-0.8113,-0.7332,-0.5887,-0.3660",\ +"-1.0418,-1.0262,-0.9949,-0.9480,-0.8699,-0.7293,-0.5027",\ +"-1.2684,-1.2449,-1.2176,-1.1707,-1.0965,-0.9480,-0.7293"); + } + + fall_constraint("SIG2SRAM_constraint_template") { + index_1("0.0080,0.0288,0.0616,0.1072,0.1920,0.3496,0.5952"); + index_2("0.0080,0.0288,0.0616,0.1072,0.1920,0.3496,0.5952"); + values ("-0.5926,-0.5730,-0.5418,-0.4988,-0.4246,-0.2879,-0.0730",\ +"-0.6121,-0.5926,-0.5613,-0.5223,-0.4441,-0.3074,-0.0887",\ +"-0.6395,-0.6199,-0.5926,-0.5496,-0.4715,-0.3348,-0.1160",\ +"-0.6863,-0.6668,-0.6355,-0.5965,-0.5184,-0.3777,-0.1590",\ +"-0.7605,-0.7410,-0.7137,-0.6746,-0.5926,-0.4559,-0.2410",\ +"-0.9012,-0.8816,-0.8504,-0.8113,-0.7332,-0.5926,-0.3895",\ +"-1.1238,-1.1043,-1.0769,-1.0379,-0.9559,-0.8191,-0.6004"); + } + } + + + timing() { + timing_type : hold_rising; + related_pin : "A_CLK"; + when : "((A_WEN | A_REN)& A_MEN)" + sdf_cond : "A_RW_ACCESS" + + rise_constraint("SIG2SRAM_constraint_template") { + index_1("0.0080,0.0288,0.0616,0.1072,0.1920,0.3496,0.5952"); + index_2("0.0080,0.0288,0.0616,0.1072,0.1920,0.3496,0.5952"); + values ("0.8488,0.8293,0.7980,0.7551,0.6730,0.5285,0.3059",\ +"0.8684,0.8488,0.8176,0.7746,0.6926,0.5480,0.3254",\ +"0.8996,0.8801,0.8449,0.8020,0.7238,0.5754,0.3527",\ +"0.9426,0.9191,0.8918,0.8488,0.7668,0.6223,0.3996",\ +"1.0168,1.0012,0.9699,0.9230,0.8449,0.7004,0.4777",\ +"1.1574,1.1379,1.1105,1.0598,0.9816,0.8371,0.6184",\ +"1.3801,1.3605,1.3254,1.2980,1.2043,1.0637,0.8371"); + } + + fall_constraint("SIG2SRAM_constraint_template") { + index_1("0.0080,0.0288,0.0616,0.1072,0.1920,0.3496,0.5952"); + index_2("0.0080,0.0288,0.0616,0.1072,0.1920,0.3496,0.5952"); + values ("0.6965,0.6770,0.6496,0.6066,0.5246,0.3918,0.1730",\ +"0.7160,0.6965,0.6652,0.6262,0.5441,0.4113,0.1965",\ +"0.7473,0.7277,0.6965,0.6535,0.5754,0.4426,0.2238",\ +"0.7863,0.7707,0.7395,0.7004,0.6223,0.4855,0.2629",\ +"0.8684,0.8449,0.8176,0.7785,0.7004,0.5637,0.3449",\ +"1.0051,0.9855,0.9855,0.9113,0.8332,0.7004,0.4895",\ +"1.2277,1.2082,1.1809,1.1379,1.0598,0.9230,0.7004"); + } + } +} +pin(A_WEN) { + direction : input ; + capacitance : 0.00313551 ; + max_transition : "0.5952" ; + related_power_pin : VDD; + related_ground_pin : VSS; + internal_power() { + when : "A_MEN"; + rise_power("scalar"){ + values (0.0036); + } + fall_power("scalar"){ + values (0.0006); + } + } + internal_power() { + when : "!A_MEN"; + rise_power("scalar"){ + values (0.0050); + } + fall_power("scalar"){ + values (0.0002); + } + } + timing() { + timing_type : setup_rising; + related_pin : "A_CLK"; + when : "A_MEN" + sdf_cond : "A_MEN" + + rise_constraint("SIG2SRAM_constraint_template") { + index_1("0.0080,0.0288,0.0616,0.1072,0.1920,0.3496,0.5952"); + index_2("0.0080,0.0288,0.0616,0.1072,0.1920,0.3496,0.5952"); + values ("0.3137,0.3332,0.3605,0.4035,0.4816,0.6223,0.8488",\ +"0.2980,0.3176,0.3410,0.3840,0.4660,0.6027,0.8293",\ +"0.2629,0.2824,0.3098,0.3527,0.4348,0.5754,0.7980",\ +"0.2199,0.2395,0.2668,0.3098,0.3918,0.5324,0.7590",\ +"0.1418,0.1613,0.1887,0.2316,0.3137,0.4348,0.6730",\ +"0.0012,0.0207,0.0520,0.0910,0.1730,0.3098,0.5285",\ +"-0.2215,-0.2020,-0.1746,-0.1277,-0.0496,0.0910,0.3098"); + } + + fall_constraint("SIG2SRAM_constraint_template") { + index_1("0.0080,0.0288,0.0616,0.1072,0.1920,0.3496,0.5952"); + index_2("0.0080,0.0288,0.0616,0.1072,0.1920,0.3496,0.5952"); + values ("0.4504,0.4699,0.4973,0.5324,0.6027,0.7355,0.9699",\ +"0.4309,0.4504,0.4777,0.5129,0.5910,0.7160,0.9504",\ +"0.3996,0.4191,0.4465,0.4816,0.5520,0.6848,0.9191",\ +"0.3605,0.3762,0.4035,0.4387,0.5168,0.6418,0.8723",\ +"0.2785,0.2980,0.3215,0.3605,0.4348,0.5637,0.7980",\ +"0.1379,0.1574,0.1809,0.2199,0.2980,0.4309,0.6457",\ +"-0.0809,-0.0613,-0.0340,0.0051,0.0832,0.2160,0.4191"); + } + } + + + timing() { + timing_type : hold_rising; + related_pin : "A_CLK"; + when : "A_MEN" + sdf_cond : "A_MEN" + + rise_constraint("SIG2SRAM_constraint_template") { + index_1("0.0080,0.0288,0.0616,0.1072,0.1920,0.3496,0.5952"); + index_2("0.0080,0.0288,0.0616,0.1072,0.1920,0.3496,0.5952"); + values ("0.3723,0.3527,0.3215,0.2785,0.1965,0.0559,-0.1668",\ +"0.3918,0.3723,0.3449,0.2980,0.2160,0.0754,-0.1473",\ +"0.4152,0.3996,0.3684,0.3254,0.2434,0.1066,-0.1199",\ +"0.4621,0.4465,0.4152,0.3723,0.2863,0.1496,-0.0730",\ +"0.5324,0.5207,0.4895,0.4465,0.3645,0.2199,0.0051",\ +"0.6770,0.6535,0.6301,0.5832,0.5090,0.3605,0.1418",\ +"0.9035,0.8879,0.8566,0.8137,0.7316,0.5871,0.3684"); + } + + fall_constraint("SIG2SRAM_constraint_template") { + index_1("0.0080,0.0288,0.0616,0.1072,0.1920,0.3496,0.5952"); + index_2("0.0080,0.0288,0.0616,0.1072,0.1920,0.3496,0.5952"); + values ("0.3762,0.3566,0.3293,0.2863,0.2043,0.0676,-0.1434",\ +"0.3957,0.3762,0.3488,0.3059,0.2238,0.0871,-0.1199",\ +"0.4230,0.4035,0.3723,0.3332,0.2512,0.1184,-0.0965",\ +"0.4660,0.4465,0.4191,0.3762,0.2941,0.1613,-0.0496",\ +"0.5324,0.5168,0.4973,0.4543,0.3723,0.2316,0.0285",\ +"0.6809,0.6613,0.6340,0.5910,0.5129,0.3645,0.1652",\ +"0.9113,0.8918,0.8605,0.8176,0.7395,0.5988,0.3879"); + } + } + } +pin(A_REN) { + direction : input ; + capacitance : 0.00381144 ; + max_transition : "0.5952" ; + related_power_pin : VDD; + related_ground_pin : VSS; + internal_power() { + when : "A_MEN"; + rise_power("scalar"){ + values (0.0041); + } + fall_power("scalar"){ + values (0.0014); + } + } + internal_power() { + when : "!A_MEN"; + rise_power("scalar"){ + values (0.0041); + } + fall_power("scalar"){ + values (0.0012); + } + } + timing() { + timing_type : setup_rising; + related_pin : "A_CLK"; + when : "A_MEN" + sdf_cond : "A_MEN" + + rise_constraint("SIG2SRAM_constraint_template") { + index_1("0.0080,0.0288,0.0616,0.1072,0.1920,0.3496,0.5952"); + index_2("0.0080,0.0288,0.0616,0.1072,0.1920,0.3496,0.5952"); + values ("-0.0770,-0.0574,-0.0262,0.0168,0.0949,0.2355,0.4582",\ +"-0.0965,-0.0770,-0.0457,-0.0027,0.0754,0.2160,0.4387",\ +"-0.1199,-0.1004,-0.0730,-0.0262,0.0520,0.1887,0.4113",\ +"-0.1590,-0.1434,-0.1160,-0.0730,0.0051,0.1457,0.3645",\ +"-0.2449,-0.2254,-0.1941,-0.1473,-0.0770,0.0676,0.2863",\ +"-0.3816,-0.3699,-0.3387,-0.2801,-0.2215,-0.0770,0.1457",\ +"-0.6121,-0.5926,-0.5613,-0.5145,-0.4363,-0.2996,-0.0730"); + } + + fall_constraint("SIG2SRAM_constraint_template") { + index_1("0.0080,0.0288,0.0616,0.1072,0.1920,0.3496,0.5952"); + index_2("0.0080,0.0288,0.0616,0.1072,0.1920,0.3496,0.5952"); + values ("0.1262,0.1457,0.1691,0.2121,0.2824,0.4191,0.6457",\ +"0.1105,0.1262,0.1496,0.1887,0.2629,0.3996,0.6262",\ +"0.0793,0.0949,0.1223,0.1652,0.2395,0.3684,0.5949",\ +"0.0363,0.0559,0.0793,0.1223,0.2004,0.3410,0.5520",\ +"-0.0457,-0.0262,0.0012,0.0441,0.1301,0.2629,0.4738",\ +"-0.1902,-0.1746,-0.1434,-0.1043,-0.0184,0.1223,0.3332",\ +"-0.4129,-0.3934,-0.3660,-0.3230,-0.2449,-0.1043,0.1105"); + } + } + + + timing() { + timing_type : hold_rising; + related_pin : "A_CLK"; + when : "A_MEN" + sdf_cond : "A_MEN" + + rise_constraint("SIG2SRAM_constraint_template") { + index_1("0.0080,0.0288,0.0616,0.1072,0.1920,0.3496,0.5952"); + index_2("0.0080,0.0288,0.0616,0.1072,0.1920,0.3496,0.5952"); + values ("0.4113,0.3918,0.3645,0.3176,0.2395,0.0988,-0.1238",\ +"0.4309,0.4113,0.3840,0.3371,0.2590,0.1184,-0.1043",\ +"0.4582,0.4387,0.4113,0.3645,0.2824,0.1457,-0.0770",\ +"0.5051,0.4816,0.4543,0.4074,0.3293,0.1887,-0.0340",\ +"0.5715,0.5598,0.5324,0.4895,0.4035,0.2512,0.0441",\ +"0.7043,0.7004,0.6730,0.6262,0.5402,0.3957,0.1809",\ +"0.9387,0.9270,0.8957,0.8527,0.7746,0.6262,0.4074"); + } + + fall_constraint("SIG2SRAM_constraint_template") { + index_1("0.0080,0.0288,0.0616,0.1072,0.1920,0.3496,0.5952"); + index_2("0.0080,0.0288,0.0616,0.1072,0.1920,0.3496,0.5952"); + values ("0.4152,0.3918,0.3645,0.3215,0.2395,0.1027,-0.1082",\ +"0.4309,0.4113,0.3801,0.3410,0.2590,0.1223,-0.0926",\ +"0.4582,0.4387,0.4074,0.3684,0.2863,0.1496,-0.0613",\ +"0.5012,0.4816,0.4504,0.4074,0.3293,0.1887,-0.0145",\ +"0.5715,0.5559,0.5285,0.4816,0.3996,0.2512,0.0598",\ +"0.7160,0.7004,0.6691,0.6262,0.5520,0.4035,0.2004",\ +"0.9387,0.9191,0.8957,0.8488,0.7707,0.6262,0.4113"); + } + } + } +pin(A_MEN) { + direction : input ; + capacitance : 0.00300347 ; + max_transition : "0.5952" ; + related_power_pin : VDD; + related_ground_pin : VSS; + internal_power() { + rise_power("scalar"){ + values (0.0161); + } + fall_power("scalar"){ + values (0.0002); + } + } + timing() { + timing_type : setup_rising; + related_pin : "A_CLK"; + + rise_constraint("SIG2SRAM_constraint_template") { + index_1("0.0080,0.0288,0.0616,0.1072,0.1920,0.3496,0.5952"); + index_2("0.0080,0.0288,0.0616,0.1072,0.1920,0.3496,0.5952"); + values ("0.3215,0.3449,0.3684,0.4113,0.4895,0.6301,0.8527",\ +"0.3059,0.3254,0.3527,0.3957,0.4738,0.6145,0.8371",\ +"0.2746,0.2941,0.3215,0.3645,0.4426,0.5871,0.8059",\ +"0.2316,0.2512,0.2785,0.3215,0.3996,0.5402,0.7629",\ +"0.1496,0.1730,0.1965,0.2395,0.3215,0.4660,0.6848",\ +"0.0090,0.0285,0.0598,0.1027,0.1809,0.3176,0.5402",\ +"-0.2098,-0.1902,-0.1668,-0.1199,-0.0418,0.0988,0.3137"); + } + + fall_constraint("SIG2SRAM_constraint_template") { + index_1("0.0080,0.0288,0.0616,0.1072,0.1920,0.3496,0.5952"); + index_2("0.0080,0.0288,0.0616,0.1072,0.1920,0.3496,0.5952"); + values ("0.4582,0.4738,0.5012,0.5363,0.6145,0.7395,0.9738",\ +"0.4387,0.4543,0.4816,0.5207,0.5910,0.7199,0.9582",\ +"0.4035,0.4230,0.4504,0.4855,0.5637,0.6887,0.9230",\ +"0.3645,0.3840,0.4074,0.4465,0.5285,0.6496,0.8840",\ +"0.2824,0.3020,0.3254,0.3645,0.4465,0.5715,0.7980",\ +"0.1418,0.1613,0.1887,0.2238,0.3020,0.4309,0.6496",\ +"-0.0770,-0.0574,-0.0301,0.0090,0.0910,0.2238,0.4191"); + } + } + + + timing() { + timing_type : hold_rising; + related_pin : "A_CLK"; + + rise_constraint("SIG2SRAM_constraint_template") { + index_1("0.0080,0.0288,0.0616,0.1072,0.1920,0.3496,0.5952"); + index_2("0.0080,0.0288,0.0616,0.1072,0.1920,0.3496,0.5952"); + values ("0.3762,0.3605,0.3293,0.2863,0.2043,0.0637,-0.1629",\ +"0.3996,0.3801,0.3488,0.3020,0.2238,0.0832,-0.1395",\ +"0.4230,0.4074,0.3723,0.3293,0.2473,0.1105,-0.1121",\ +"0.4621,0.4465,0.4152,0.3762,0.2941,0.1535,-0.0691",\ +"0.5441,0.5285,0.4973,0.4465,0.3684,0.2316,0.0090",\ +"0.6848,0.6652,0.6301,0.5910,0.5129,0.3605,0.1496",\ +"0.9074,0.8918,0.8566,0.8215,0.7395,0.5910,0.3723"); + } + + fall_constraint("SIG2SRAM_constraint_template") { + index_1("0.0080,0.0288,0.0616,0.1072,0.1920,0.3496,0.5952"); + index_2("0.0080,0.0288,0.0616,0.1072,0.1920,0.3496,0.5952"); + values ("0.3762,0.3605,0.3332,0.2863,0.2043,0.0715,-0.1395",\ +"0.3996,0.3762,0.3488,0.3059,0.2238,0.0910,-0.1199",\ +"0.4270,0.4035,0.3762,0.3332,0.2512,0.1184,-0.0965",\ +"0.4699,0.4504,0.4191,0.3762,0.2941,0.1613,-0.0496",\ +"0.5441,0.5285,0.4973,0.4543,0.3762,0.2355,0.0324",\ +"0.6770,0.6613,0.6340,0.5949,0.5207,0.3762,0.1652",\ +"0.9074,0.8918,0.8605,0.8176,0.7395,0.6027,0.3918"); + } + } + } +bus(A_BM) { + bus_type : D_15_0; + direction : input ; + capacitance : 0.00359979 ; + max_transition : "0.5952" ; + pin(A_BM[15:0]) { + related_power_pin : VDD; + related_ground_pin : VSS; + internal_power() { + when : "A_MEN"; + rise_power("scalar"){ + values (0.0469); + } + fall_power("scalar"){ + values (0.0152); + } + } + internal_power() { + when : "!A_MEN"; + rise_power("scalar"){ + values (0.0453); + } + fall_power("scalar"){ + values (0.0145); + } + } + } + timing() { + timing_type : setup_rising; + related_pin : "A_CLK"; + when : "(A_WEN & A_MEN)" + sdf_cond : "A_RW_ACCESS" + + rise_constraint("SIG2SRAM_constraint_template") { + index_1("0.0080,0.0288,0.0616,0.1072,0.1920,0.3496,0.5952"); + index_2("0.0080,0.0288,0.0616,0.1072,0.1920,0.3496,0.5952"); + values ("-0.6982,-0.6787,-0.6533,-0.6103,-0.5293,-0.3838,-0.1611",\ +"-0.7057,-0.6861,-0.6608,-0.6178,-0.5367,-0.3912,-0.1686",\ +"-0.7153,-0.6957,-0.6703,-0.6274,-0.5463,-0.4008,-0.1782",\ +"-0.7284,-0.7089,-0.6835,-0.6405,-0.5595,-0.4140,-0.1913",\ +"-0.7527,-0.7331,-0.7077,-0.6648,-0.5837,-0.4382,-0.2156",\ +"-0.7831,-0.7636,-0.7382,-0.6952,-0.6142,-0.4686,-0.2460",\ +"-0.8647,-0.8452,-0.8198,-0.7768,-0.6958,-0.5503,-0.3276"); + } + + fall_constraint("SIG2SRAM_constraint_template") { + index_1("0.0080,0.0288,0.0616,0.1072,0.1920,0.3496,0.5952"); + index_2("0.0080,0.0288,0.0616,0.1072,0.1920,0.3496,0.5952"); + values ("-0.6357,-0.6181,-0.5908,-0.5517,-0.4687,-0.3330,-0.1211",\ +"-0.6432,-0.6256,-0.5983,-0.5592,-0.4762,-0.3404,-0.1285",\ +"-0.6528,-0.6352,-0.6078,-0.5688,-0.4858,-0.3500,-0.1381",\ +"-0.6659,-0.6483,-0.6210,-0.5819,-0.4989,-0.3632,-0.1513",\ +"-0.6902,-0.6726,-0.6452,-0.6062,-0.5232,-0.3874,-0.1755",\ +"-0.7206,-0.7030,-0.6757,-0.6366,-0.5536,-0.4179,-0.2059",\ +"-0.8022,-0.7846,-0.7573,-0.7182,-0.6352,-0.4995,-0.2876"); + } + } + + + timing() { + timing_type : hold_rising; + related_pin : "A_CLK"; + when : "(A_WEN & A_MEN)" + sdf_cond : "A_RW_ACCESS" + + rise_constraint("SIG2SRAM_constraint_template") { + index_1("0.0080,0.0288,0.0616,0.1072,0.1920,0.3496,0.5952"); + index_2("0.0080,0.0288,0.0616,0.1072,0.1920,0.3496,0.5952"); + values ("0.8138,0.7923,0.7679,0.7250,0.6449,0.4984,0.2757",\ +"0.8213,0.7998,0.7754,0.7324,0.6523,0.5059,0.2832",\ +"0.8309,0.8094,0.7850,0.7420,0.6619,0.5154,0.2928",\ +"0.8440,0.8225,0.7981,0.7552,0.6751,0.5286,0.3059",\ +"0.8683,0.8468,0.8224,0.7794,0.6993,0.5528,0.3302",\ +"0.8987,0.8772,0.8528,0.8098,0.7298,0.5833,0.3606",\ +"0.9803,0.9588,0.9344,0.8915,0.8114,0.6649,0.4422"); + } + + fall_constraint("SIG2SRAM_constraint_template") { + index_1("0.0080,0.0288,0.0616,0.1072,0.1920,0.3496,0.5952"); + index_2("0.0080,0.0288,0.0616,0.1072,0.1920,0.3496,0.5952"); + values ("0.7396,0.7220,0.6947,0.6556,0.5726,0.4359,0.2250",\ +"0.7471,0.7295,0.7022,0.6631,0.5801,0.4434,0.2324",\ +"0.7567,0.7391,0.7117,0.6727,0.5897,0.4529,0.2420",\ +"0.7698,0.7522,0.7249,0.6858,0.6028,0.4661,0.2552",\ +"0.7941,0.7765,0.7491,0.7101,0.6271,0.4904,0.2794",\ +"0.8245,0.8069,0.7796,0.7405,0.6575,0.5208,0.3098",\ +"0.9061,0.8885,0.8612,0.8221,0.7391,0.6024,0.3915"); + } + } +} + pin(A_CLK) { + direction : input; + capacitance : 0.00378957; + max_transition : "0.5952"; + clock : "true" ; + pin_func_type : active_rising ; + + timing () { + timing_type : "min_pulse_width"; + related_pin : "A_CLK"; + rise_constraint("CLKTRAN_constraint_template") { + index_1("0.008,0.5952"); + values("0.4,0.4"); + } + } + + related_power_pin : VDD; + related_ground_pin : VSS; + + internal_power() { + when : "!A_MEN & !A_WEN & !A_REN"; + rise_power("scalar"){ + values (0); + } + fall_power("scalar"){ + values (0); + } + } + internal_power() { + when : "!A_MEN & A_WEN & !A_REN"; + rise_power("scalar"){ + values (0.5014); + } + fall_power("scalar"){ + values (0); + } + } + internal_power() { + when : "A_MEN & A_WEN & !A_REN"; + rise_power("scalar"){ + values (19.4302); + } + fall_power("scalar"){ + values (0); + } + } + internal_power() { + when : "A_MEN & A_WEN & A_REN"; + rise_power("scalar"){ + values (20.3865); + } + fall_power("scalar"){ + values (0); + } + } + internal_power() { + when : "A_MEN & !A_WEN & A_REN"; + rise_power("scalar"){ + values (15.8142); + } + fall_power("scalar"){ + values (0); + } + } + internal_power() { + when : "!A_MEN & !A_WEN & A_REN"; + rise_power("scalar"){ + values (0.3165); + } + fall_power("scalar"){ + values (0); + } + } + internal_power() { + when : "!A_MEN & A_WEN & A_REN"; + rise_power("scalar"){ + values (0.6909); + } + fall_power("scalar"){ + values (0); + } + } + internal_power() { + when : "A_MEN & !A_WEN & !A_REN"; + rise_power("scalar"){ + values (0); + } + fall_power("scalar"){ + values (0); + } + } + } + bus(A_DIN) { + bus_type : D_15_0; + direction : input ; + capacitance : 0.00502163 ; + memory_write() { + address : A_ADDR ; + clocked_on : A_CLK; + } + + max_transition : "0.5952" ; + pin(A_DIN[15:0]) { + related_power_pin : VDD; + related_ground_pin : VSS; + internal_power() { + when : "A_MEN"; + rise_power("scalar"){ + values (0.0469); + } + fall_power("scalar"){ + values (0.0152); + } + } + internal_power() { + when : "!A_MEN"; + rise_power("scalar"){ + values (0.0453); + } + fall_power("scalar"){ + values (0.0145); + } + } + } + timing() { + timing_type : setup_rising; + related_pin : "A_CLK"; + when : "(A_WEN & A_MEN)"; + sdf_cond : "A_W_ACCESS"; + + rise_constraint("SIG2SRAM_constraint_template") { + index_1("0.0080,0.0288,0.0616,0.1072,0.1920,0.3496,0.5952"); + index_2("0.0080,0.0288,0.0616,0.1072,0.1920,0.3496,0.5952"); + values ("-0.6982,-0.6787,-0.6533,-0.6103,-0.5293,-0.3838,-0.1611",\ +"-0.7057,-0.6861,-0.6608,-0.6178,-0.5367,-0.3912,-0.1686",\ +"-0.7153,-0.6957,-0.6703,-0.6274,-0.5463,-0.4008,-0.1782",\ +"-0.7284,-0.7089,-0.6835,-0.6405,-0.5595,-0.4140,-0.1913",\ +"-0.7527,-0.7331,-0.7077,-0.6648,-0.5837,-0.4382,-0.2156",\ +"-0.7831,-0.7636,-0.7382,-0.6952,-0.6142,-0.4686,-0.2460",\ +"-0.8647,-0.8452,-0.8198,-0.7768,-0.6958,-0.5503,-0.3276"); + } + + fall_constraint("SIG2SRAM_constraint_template") { + index_1("0.0080,0.0288,0.0616,0.1072,0.1920,0.3496,0.5952"); + index_2("0.0080,0.0288,0.0616,0.1072,0.1920,0.3496,0.5952"); + values ("-0.6357,-0.6181,-0.5908,-0.5517,-0.4687,-0.3330,-0.1211",\ +"-0.6432,-0.6256,-0.5983,-0.5592,-0.4762,-0.3404,-0.1285",\ +"-0.6528,-0.6352,-0.6078,-0.5688,-0.4858,-0.3500,-0.1381",\ +"-0.6659,-0.6483,-0.6210,-0.5819,-0.4989,-0.3632,-0.1513",\ +"-0.6902,-0.6726,-0.6452,-0.6062,-0.5232,-0.3874,-0.1755",\ +"-0.7206,-0.7030,-0.6757,-0.6366,-0.5536,-0.4179,-0.2059",\ +"-0.8022,-0.7846,-0.7573,-0.7182,-0.6352,-0.4995,-0.2876"); + } + } + + timing() { + timing_type : hold_rising; + related_pin : "A_CLK"; + when : "(A_WEN & A_MEN)"; + sdf_cond : "A_W_ACCESS"; + + rise_constraint("SIG2SRAM_constraint_template") { + index_1("0.0080,0.0288,0.0616,0.1072,0.1920,0.3496,0.5952"); + index_2("0.0080,0.0288,0.0616,0.1072,0.1920,0.3496,0.5952"); + values ("0.8138,0.7923,0.7679,0.7250,0.6449,0.4984,0.2757",\ +"0.8213,0.7998,0.7754,0.7324,0.6523,0.5059,0.2832",\ +"0.8309,0.8094,0.7850,0.7420,0.6619,0.5154,0.2928",\ +"0.8440,0.8225,0.7981,0.7552,0.6751,0.5286,0.3059",\ +"0.8683,0.8468,0.8224,0.7794,0.6993,0.5528,0.3302",\ +"0.8987,0.8772,0.8528,0.8098,0.7298,0.5833,0.3606",\ +"0.9803,0.9588,0.9344,0.8915,0.8114,0.6649,0.4422"); + } + + fall_constraint("SIG2SRAM_constraint_template") { + index_1("0.0080,0.0288,0.0616,0.1072,0.1920,0.3496,0.5952"); + index_2("0.0080,0.0288,0.0616,0.1072,0.1920,0.3496,0.5952"); + values ("0.7396,0.7220,0.6947,0.6556,0.5726,0.4359,0.2250",\ +"0.7471,0.7295,0.7022,0.6631,0.5801,0.4434,0.2324",\ +"0.7567,0.7391,0.7117,0.6727,0.5897,0.4529,0.2420",\ +"0.7698,0.7522,0.7249,0.6858,0.6028,0.4661,0.2552",\ +"0.7941,0.7765,0.7491,0.7101,0.6271,0.4904,0.2794",\ +"0.8245,0.8069,0.7796,0.7405,0.6575,0.5208,0.3098",\ +"0.9061,0.8885,0.8612,0.8221,0.7391,0.6024,0.3915"); + } + } + } + + pin(A_BIST_EN) { + direction : input ; + capacitance : 0.00387999 ; + max_transition : "1" ; + related_power_pin : VDD; + related_ground_pin : VSS; + internal_power() { + rise_power("scalar") { + values (0); + } + fall_power("scalar") { + values (0); + } + } + } + +bus(A_BIST_ADDR) { + bus_type : A_8_0; + direction : input ; + capacitance : 0.0129586 ; + pin(A_BIST_ADDR[0]) { + capacitance : 0.0058687 ; + } + pin(A_BIST_ADDR[1]) { + capacitance : 0.00807137 ; + } + pin(A_BIST_ADDR[2]) { + capacitance : 0.0112051 ; + } + pin(A_BIST_ADDR[3]) { + capacitance : 0.00709524 ; + } + pin(A_BIST_ADDR[4]) { + capacitance : 0.00648778 ; + } + pin(A_BIST_ADDR[5]) { + capacitance : 0.011209 ; + } + pin(A_BIST_ADDR[6]) { + capacitance : 0.0140441 ; + } + pin(A_BIST_ADDR[7]) { + capacitance : 0.0111199 ; + } + max_transition : "0.5952" ; + pin(A_BIST_ADDR[8:0]) { + related_power_pin : VDD; + related_ground_pin : VSS; + internal_power() { + when : "A_BIST_MEN"; + rise_power("scalar"){ + values (0.0102); + } + fall_power("scalar"){ + values (0.0078); + } + } + internal_power() { + when : "!A_BIST_MEN"; + rise_power("scalar"){ + values (0.0149); + } + fall_power("scalar"){ + values (0.0029); + } + } + } + timing() { + timing_type : setup_rising; + related_pin : "A_BIST_CLK"; + when : "((A_BIST_WEN | A_BIST_REN)& A_BIST_MEN)" + sdf_cond : "A_BIST_RW_ACCESS" + + rise_constraint("SIG2SRAM_constraint_template") { + index_1("0.0080,0.0288,0.0616,0.1072,0.1920,0.3496,0.5952"); + index_2("0.0080,0.0288,0.0616,0.1072,0.1920,0.3496,0.5952"); + values ("-0.7371,-0.7176,-0.6863,-0.6434,-0.5652,-0.4168,-0.1980",\ +"-0.7566,-0.7371,-0.7059,-0.6629,-0.5848,-0.4363,-0.2137",\ +"-0.7879,-0.7645,-0.7332,-0.6902,-0.6121,-0.4637,-0.2449",\ +"-0.8309,-0.8074,-0.7762,-0.7332,-0.6551,-0.5066,-0.2879",\ +"-0.9051,-0.8895,-0.8543,-0.8113,-0.7332,-0.5887,-0.3660",\ +"-1.0418,-1.0262,-0.9949,-0.9480,-0.8699,-0.7293,-0.5027",\ +"-1.2684,-1.2449,-1.2176,-1.1707,-1.0965,-0.9480,-0.7293"); + } + + fall_constraint("SIG2SRAM_constraint_template") { + index_1("0.0080,0.0288,0.0616,0.1072,0.1920,0.3496,0.5952"); + index_2("0.0080,0.0288,0.0616,0.1072,0.1920,0.3496,0.5952"); + values ("-0.5926,-0.5730,-0.5418,-0.4988,-0.4246,-0.2879,-0.0730",\ +"-0.6121,-0.5926,-0.5613,-0.5223,-0.4441,-0.3074,-0.0887",\ +"-0.6395,-0.6199,-0.5926,-0.5496,-0.4715,-0.3348,-0.1160",\ +"-0.6863,-0.6668,-0.6355,-0.5965,-0.5184,-0.3777,-0.1590",\ +"-0.7605,-0.7410,-0.7137,-0.6746,-0.5926,-0.4559,-0.2410",\ +"-0.9012,-0.8816,-0.8504,-0.8113,-0.7332,-0.5926,-0.3895",\ +"-1.1238,-1.1043,-1.0769,-1.0379,-0.9559,-0.8191,-0.6004"); + } + } + + + timing() { + timing_type : hold_rising; + related_pin : "A_BIST_CLK"; + when : "((A_BIST_WEN | A_BIST_REN)& A_BIST_MEN)" + sdf_cond : "A_BIST_RW_ACCESS" + + rise_constraint("SIG2SRAM_constraint_template") { + index_1("0.0080,0.0288,0.0616,0.1072,0.1920,0.3496,0.5952"); + index_2("0.0080,0.0288,0.0616,0.1072,0.1920,0.3496,0.5952"); + values ("0.8488,0.8293,0.7980,0.7551,0.6730,0.5285,0.3059",\ +"0.8684,0.8488,0.8176,0.7746,0.6926,0.5480,0.3254",\ +"0.8996,0.8801,0.8449,0.8020,0.7238,0.5754,0.3527",\ +"0.9426,0.9191,0.8918,0.8488,0.7668,0.6223,0.3996",\ +"1.0168,1.0012,0.9699,0.9230,0.8449,0.7004,0.4777",\ +"1.1574,1.1379,1.1105,1.0598,0.9816,0.8371,0.6184",\ +"1.3801,1.3605,1.3254,1.2980,1.2043,1.0637,0.8371"); + } + + fall_constraint("SIG2SRAM_constraint_template") { + index_1("0.0080,0.0288,0.0616,0.1072,0.1920,0.3496,0.5952"); + index_2("0.0080,0.0288,0.0616,0.1072,0.1920,0.3496,0.5952"); + values ("0.6965,0.6770,0.6496,0.6066,0.5246,0.3918,0.1730",\ +"0.7160,0.6965,0.6652,0.6262,0.5441,0.4113,0.1965",\ +"0.7473,0.7277,0.6965,0.6535,0.5754,0.4426,0.2238",\ +"0.7863,0.7707,0.7395,0.7004,0.6223,0.4855,0.2629",\ +"0.8684,0.8449,0.8176,0.7785,0.7004,0.5637,0.3449",\ +"1.0051,0.9855,0.9855,0.9113,0.8332,0.7004,0.4895",\ +"1.2277,1.2082,1.1809,1.1379,1.0598,0.9230,0.7004"); + } + } +} +pin(A_BIST_WEN) { + direction : input ; + capacitance : 0.00313551 ; + max_transition : "0.5952" ; + related_power_pin : VDD; + related_ground_pin : VSS; + internal_power() { + when : "A_BIST_MEN"; + rise_power("scalar"){ + values (0.0036); + } + fall_power("scalar"){ + values (0.0006); + } + } + internal_power() { + when : "!A_BIST_MEN"; + rise_power("scalar"){ + values (0.0050); + } + fall_power("scalar"){ + values (0.0002); + } + } + timing() { + timing_type : setup_rising; + related_pin : "A_BIST_CLK"; + when : "A_BIST_MEN" + sdf_cond : "A_BIST_MEN" + + rise_constraint("SIG2SRAM_constraint_template") { + index_1("0.0080,0.0288,0.0616,0.1072,0.1920,0.3496,0.5952"); + index_2("0.0080,0.0288,0.0616,0.1072,0.1920,0.3496,0.5952"); + values ("0.3137,0.3332,0.3605,0.4035,0.4816,0.6223,0.8488",\ +"0.2980,0.3176,0.3410,0.3840,0.4660,0.6027,0.8293",\ +"0.2629,0.2824,0.3098,0.3527,0.4348,0.5754,0.7980",\ +"0.2199,0.2395,0.2668,0.3098,0.3918,0.5324,0.7590",\ +"0.1418,0.1613,0.1887,0.2316,0.3137,0.4348,0.6730",\ +"0.0012,0.0207,0.0520,0.0910,0.1730,0.3098,0.5285",\ +"-0.2215,-0.2020,-0.1746,-0.1277,-0.0496,0.0910,0.3098"); + } + + fall_constraint("SIG2SRAM_constraint_template") { + index_1("0.0080,0.0288,0.0616,0.1072,0.1920,0.3496,0.5952"); + index_2("0.0080,0.0288,0.0616,0.1072,0.1920,0.3496,0.5952"); + values ("0.4504,0.4699,0.4973,0.5324,0.6027,0.7355,0.9699",\ +"0.4309,0.4504,0.4777,0.5129,0.5910,0.7160,0.9504",\ +"0.3996,0.4191,0.4465,0.4816,0.5520,0.6848,0.9191",\ +"0.3605,0.3762,0.4035,0.4387,0.5168,0.6418,0.8723",\ +"0.2785,0.2980,0.3215,0.3605,0.4348,0.5637,0.7980",\ +"0.1379,0.1574,0.1809,0.2199,0.2980,0.4309,0.6457",\ +"-0.0809,-0.0613,-0.0340,0.0051,0.0832,0.2160,0.4191"); + } + } + + + timing() { + timing_type : hold_rising; + related_pin : "A_BIST_CLK"; + when : "A_BIST_MEN" + sdf_cond : "A_BIST_MEN" + + rise_constraint("SIG2SRAM_constraint_template") { + index_1("0.0080,0.0288,0.0616,0.1072,0.1920,0.3496,0.5952"); + index_2("0.0080,0.0288,0.0616,0.1072,0.1920,0.3496,0.5952"); + values ("0.3723,0.3527,0.3215,0.2785,0.1965,0.0559,-0.1668",\ +"0.3918,0.3723,0.3449,0.2980,0.2160,0.0754,-0.1473",\ +"0.4152,0.3996,0.3684,0.3254,0.2434,0.1066,-0.1199",\ +"0.4621,0.4465,0.4152,0.3723,0.2863,0.1496,-0.0730",\ +"0.5324,0.5207,0.4895,0.4465,0.3645,0.2199,0.0051",\ +"0.6770,0.6535,0.6301,0.5832,0.5090,0.3605,0.1418",\ +"0.9035,0.8879,0.8566,0.8137,0.7316,0.5871,0.3684"); + } + + fall_constraint("SIG2SRAM_constraint_template") { + index_1("0.0080,0.0288,0.0616,0.1072,0.1920,0.3496,0.5952"); + index_2("0.0080,0.0288,0.0616,0.1072,0.1920,0.3496,0.5952"); + values ("0.3762,0.3566,0.3293,0.2863,0.2043,0.0676,-0.1434",\ +"0.3957,0.3762,0.3488,0.3059,0.2238,0.0871,-0.1199",\ +"0.4230,0.4035,0.3723,0.3332,0.2512,0.1184,-0.0965",\ +"0.4660,0.4465,0.4191,0.3762,0.2941,0.1613,-0.0496",\ +"0.5324,0.5168,0.4973,0.4543,0.3723,0.2316,0.0285",\ +"0.6809,0.6613,0.6340,0.5910,0.5129,0.3645,0.1652",\ +"0.9113,0.8918,0.8605,0.8176,0.7395,0.5988,0.3879"); + } + } + } +pin(A_BIST_REN) { + direction : input ; + capacitance : 0.00381144 ; + max_transition : "0.5952" ; + related_power_pin : VDD; + related_ground_pin : VSS; + internal_power() { + when : "A_BIST_MEN"; + rise_power("scalar"){ + values (0.0041); + } + fall_power("scalar"){ + values (0.0014); + } + } + internal_power() { + when : "!A_BIST_MEN"; + rise_power("scalar"){ + values (0.0041); + } + fall_power("scalar"){ + values (0.0012); + } + } + timing() { + timing_type : setup_rising; + related_pin : "A_BIST_CLK"; + when : "A_BIST_MEN" + sdf_cond : "A_BIST_MEN" + + rise_constraint("SIG2SRAM_constraint_template") { + index_1("0.0080,0.0288,0.0616,0.1072,0.1920,0.3496,0.5952"); + index_2("0.0080,0.0288,0.0616,0.1072,0.1920,0.3496,0.5952"); + values ("-0.0770,-0.0574,-0.0262,0.0168,0.0949,0.2355,0.4582",\ +"-0.0965,-0.0770,-0.0457,-0.0027,0.0754,0.2160,0.4387",\ +"-0.1199,-0.1004,-0.0730,-0.0262,0.0520,0.1887,0.4113",\ +"-0.1590,-0.1434,-0.1160,-0.0730,0.0051,0.1457,0.3645",\ +"-0.2449,-0.2254,-0.1941,-0.1473,-0.0770,0.0676,0.2863",\ +"-0.3816,-0.3699,-0.3387,-0.2801,-0.2215,-0.0770,0.1457",\ +"-0.6121,-0.5926,-0.5613,-0.5145,-0.4363,-0.2996,-0.0730"); + } + + fall_constraint("SIG2SRAM_constraint_template") { + index_1("0.0080,0.0288,0.0616,0.1072,0.1920,0.3496,0.5952"); + index_2("0.0080,0.0288,0.0616,0.1072,0.1920,0.3496,0.5952"); + values ("0.1262,0.1457,0.1691,0.2121,0.2824,0.4191,0.6457",\ +"0.1105,0.1262,0.1496,0.1887,0.2629,0.3996,0.6262",\ +"0.0793,0.0949,0.1223,0.1652,0.2395,0.3684,0.5949",\ +"0.0363,0.0559,0.0793,0.1223,0.2004,0.3410,0.5520",\ +"-0.0457,-0.0262,0.0012,0.0441,0.1301,0.2629,0.4738",\ +"-0.1902,-0.1746,-0.1434,-0.1043,-0.0184,0.1223,0.3332",\ +"-0.4129,-0.3934,-0.3660,-0.3230,-0.2449,-0.1043,0.1105"); + } + } + + + timing() { + timing_type : hold_rising; + related_pin : "A_BIST_CLK"; + when : "A_BIST_MEN" + sdf_cond : "A_BIST_MEN" + + rise_constraint("SIG2SRAM_constraint_template") { + index_1("0.0080,0.0288,0.0616,0.1072,0.1920,0.3496,0.5952"); + index_2("0.0080,0.0288,0.0616,0.1072,0.1920,0.3496,0.5952"); + values ("0.4113,0.3918,0.3645,0.3176,0.2395,0.0988,-0.1238",\ +"0.4309,0.4113,0.3840,0.3371,0.2590,0.1184,-0.1043",\ +"0.4582,0.4387,0.4113,0.3645,0.2824,0.1457,-0.0770",\ +"0.5051,0.4816,0.4543,0.4074,0.3293,0.1887,-0.0340",\ +"0.5715,0.5598,0.5324,0.4895,0.4035,0.2512,0.0441",\ +"0.7043,0.7004,0.6730,0.6262,0.5402,0.3957,0.1809",\ +"0.9387,0.9270,0.8957,0.8527,0.7746,0.6262,0.4074"); + } + + fall_constraint("SIG2SRAM_constraint_template") { + index_1("0.0080,0.0288,0.0616,0.1072,0.1920,0.3496,0.5952"); + index_2("0.0080,0.0288,0.0616,0.1072,0.1920,0.3496,0.5952"); + values ("0.4152,0.3918,0.3645,0.3215,0.2395,0.1027,-0.1082",\ +"0.4309,0.4113,0.3801,0.3410,0.2590,0.1223,-0.0926",\ +"0.4582,0.4387,0.4074,0.3684,0.2863,0.1496,-0.0613",\ +"0.5012,0.4816,0.4504,0.4074,0.3293,0.1887,-0.0145",\ +"0.5715,0.5559,0.5285,0.4816,0.3996,0.2512,0.0598",\ +"0.7160,0.7004,0.6691,0.6262,0.5520,0.4035,0.2004",\ +"0.9387,0.9191,0.8957,0.8488,0.7707,0.6262,0.4113"); + } + } + } +pin(A_BIST_MEN) { + direction : input ; + capacitance : 0.00300347 ; + max_transition : "0.5952" ; + related_power_pin : VDD; + related_ground_pin : VSS; + internal_power() { + rise_power("scalar"){ + values (0.0161); + } + fall_power("scalar"){ + values (0.0002); + } + } + timing() { + timing_type : setup_rising; + related_pin : "A_BIST_CLK"; + + rise_constraint("SIG2SRAM_constraint_template") { + index_1("0.0080,0.0288,0.0616,0.1072,0.1920,0.3496,0.5952"); + index_2("0.0080,0.0288,0.0616,0.1072,0.1920,0.3496,0.5952"); + values ("0.3215,0.3449,0.3684,0.4113,0.4895,0.6301,0.8527",\ +"0.3059,0.3254,0.3527,0.3957,0.4738,0.6145,0.8371",\ +"0.2746,0.2941,0.3215,0.3645,0.4426,0.5871,0.8059",\ +"0.2316,0.2512,0.2785,0.3215,0.3996,0.5402,0.7629",\ +"0.1496,0.1730,0.1965,0.2395,0.3215,0.4660,0.6848",\ +"0.0090,0.0285,0.0598,0.1027,0.1809,0.3176,0.5402",\ +"-0.2098,-0.1902,-0.1668,-0.1199,-0.0418,0.0988,0.3137"); + } + + fall_constraint("SIG2SRAM_constraint_template") { + index_1("0.0080,0.0288,0.0616,0.1072,0.1920,0.3496,0.5952"); + index_2("0.0080,0.0288,0.0616,0.1072,0.1920,0.3496,0.5952"); + values ("0.4582,0.4738,0.5012,0.5363,0.6145,0.7395,0.9738",\ +"0.4387,0.4543,0.4816,0.5207,0.5910,0.7199,0.9582",\ +"0.4035,0.4230,0.4504,0.4855,0.5637,0.6887,0.9230",\ +"0.3645,0.3840,0.4074,0.4465,0.5285,0.6496,0.8840",\ +"0.2824,0.3020,0.3254,0.3645,0.4465,0.5715,0.7980",\ +"0.1418,0.1613,0.1887,0.2238,0.3020,0.4309,0.6496",\ +"-0.0770,-0.0574,-0.0301,0.0090,0.0910,0.2238,0.4191"); + } + } + + + timing() { + timing_type : hold_rising; + related_pin : "A_BIST_CLK"; + + rise_constraint("SIG2SRAM_constraint_template") { + index_1("0.0080,0.0288,0.0616,0.1072,0.1920,0.3496,0.5952"); + index_2("0.0080,0.0288,0.0616,0.1072,0.1920,0.3496,0.5952"); + values ("0.3762,0.3605,0.3293,0.2863,0.2043,0.0637,-0.1629",\ +"0.3996,0.3801,0.3488,0.3020,0.2238,0.0832,-0.1395",\ +"0.4230,0.4074,0.3723,0.3293,0.2473,0.1105,-0.1121",\ +"0.4621,0.4465,0.4152,0.3762,0.2941,0.1535,-0.0691",\ +"0.5441,0.5285,0.4973,0.4465,0.3684,0.2316,0.0090",\ +"0.6848,0.6652,0.6301,0.5910,0.5129,0.3605,0.1496",\ +"0.9074,0.8918,0.8566,0.8215,0.7395,0.5910,0.3723"); + } + + fall_constraint("SIG2SRAM_constraint_template") { + index_1("0.0080,0.0288,0.0616,0.1072,0.1920,0.3496,0.5952"); + index_2("0.0080,0.0288,0.0616,0.1072,0.1920,0.3496,0.5952"); + values ("0.3762,0.3605,0.3332,0.2863,0.2043,0.0715,-0.1395",\ +"0.3996,0.3762,0.3488,0.3059,0.2238,0.0910,-0.1199",\ +"0.4270,0.4035,0.3762,0.3332,0.2512,0.1184,-0.0965",\ +"0.4699,0.4504,0.4191,0.3762,0.2941,0.1613,-0.0496",\ +"0.5441,0.5285,0.4973,0.4543,0.3762,0.2355,0.0324",\ +"0.6770,0.6613,0.6340,0.5949,0.5207,0.3762,0.1652",\ +"0.9074,0.8918,0.8605,0.8176,0.7395,0.6027,0.3918"); + } + } + } +bus(A_BIST_BM) { + bus_type : D_15_0; + direction : input ; + capacitance : 0.00347781 ; + max_transition : "0.5952" ; + pin(A_BIST_BM[15:0]) { + related_power_pin : VDD; + related_ground_pin : VSS; + internal_power() { + when : "A_BIST_MEN"; + rise_power("scalar"){ + values (0.0469); + } + fall_power("scalar"){ + values (0.0152); + } + } + internal_power() { + when : "!A_BIST_MEN"; + rise_power("scalar"){ + values (0.0453); + } + fall_power("scalar"){ + values (0.0145); + } + } + } + timing() { + timing_type : setup_rising; + related_pin : "A_BIST_CLK"; + when : "(A_BIST_WEN & A_BIST_MEN)" + sdf_cond : "A_BIST_RW_ACCESS" + + rise_constraint("SIG2SRAM_constraint_template") { + index_1("0.0080,0.0288,0.0616,0.1072,0.1920,0.3496,0.5952"); + index_2("0.0080,0.0288,0.0616,0.1072,0.1920,0.3496,0.5952"); + values ("-0.6982,-0.6787,-0.6533,-0.6103,-0.5293,-0.3838,-0.1611",\ +"-0.7057,-0.6861,-0.6608,-0.6178,-0.5367,-0.3912,-0.1686",\ +"-0.7153,-0.6957,-0.6703,-0.6274,-0.5463,-0.4008,-0.1782",\ +"-0.7284,-0.7089,-0.6835,-0.6405,-0.5595,-0.4140,-0.1913",\ +"-0.7527,-0.7331,-0.7077,-0.6648,-0.5837,-0.4382,-0.2156",\ +"-0.7831,-0.7636,-0.7382,-0.6952,-0.6142,-0.4686,-0.2460",\ +"-0.8647,-0.8452,-0.8198,-0.7768,-0.6958,-0.5503,-0.3276"); + } + + fall_constraint("SIG2SRAM_constraint_template") { + index_1("0.0080,0.0288,0.0616,0.1072,0.1920,0.3496,0.5952"); + index_2("0.0080,0.0288,0.0616,0.1072,0.1920,0.3496,0.5952"); + values ("-0.6357,-0.6181,-0.5908,-0.5517,-0.4687,-0.3330,-0.1211",\ +"-0.6432,-0.6256,-0.5983,-0.5592,-0.4762,-0.3404,-0.1285",\ +"-0.6528,-0.6352,-0.6078,-0.5688,-0.4858,-0.3500,-0.1381",\ +"-0.6659,-0.6483,-0.6210,-0.5819,-0.4989,-0.3632,-0.1513",\ +"-0.6902,-0.6726,-0.6452,-0.6062,-0.5232,-0.3874,-0.1755",\ +"-0.7206,-0.7030,-0.6757,-0.6366,-0.5536,-0.4179,-0.2059",\ +"-0.8022,-0.7846,-0.7573,-0.7182,-0.6352,-0.4995,-0.2876"); + } + } + + + timing() { + timing_type : hold_rising; + related_pin : "A_BIST_CLK"; + when : "(A_BIST_WEN & A_BIST_MEN)" + sdf_cond : "A_BIST_RW_ACCESS" + + rise_constraint("SIG2SRAM_constraint_template") { + index_1("0.0080,0.0288,0.0616,0.1072,0.1920,0.3496,0.5952"); + index_2("0.0080,0.0288,0.0616,0.1072,0.1920,0.3496,0.5952"); + values ("0.8138,0.7923,0.7679,0.7250,0.6449,0.4984,0.2757",\ +"0.8213,0.7998,0.7754,0.7324,0.6523,0.5059,0.2832",\ +"0.8309,0.8094,0.7850,0.7420,0.6619,0.5154,0.2928",\ +"0.8440,0.8225,0.7981,0.7552,0.6751,0.5286,0.3059",\ +"0.8683,0.8468,0.8224,0.7794,0.6993,0.5528,0.3302",\ +"0.8987,0.8772,0.8528,0.8098,0.7298,0.5833,0.3606",\ +"0.9803,0.9588,0.9344,0.8915,0.8114,0.6649,0.4422"); + } + + fall_constraint("SIG2SRAM_constraint_template") { + index_1("0.0080,0.0288,0.0616,0.1072,0.1920,0.3496,0.5952"); + index_2("0.0080,0.0288,0.0616,0.1072,0.1920,0.3496,0.5952"); + values ("0.7396,0.7220,0.6947,0.6556,0.5726,0.4359,0.2250",\ +"0.7471,0.7295,0.7022,0.6631,0.5801,0.4434,0.2324",\ +"0.7567,0.7391,0.7117,0.6727,0.5897,0.4529,0.2420",\ +"0.7698,0.7522,0.7249,0.6858,0.6028,0.4661,0.2552",\ +"0.7941,0.7765,0.7491,0.7101,0.6271,0.4904,0.2794",\ +"0.8245,0.8069,0.7796,0.7405,0.6575,0.5208,0.3098",\ +"0.9061,0.8885,0.8612,0.8221,0.7391,0.6024,0.3915"); + } + } +} + pin(A_BIST_CLK) { + direction : input; + capacitance : 0.00378957; + max_transition : "0.5952"; + clock : "true" ; + pin_func_type : active_rising ; + + timing () { + timing_type : "min_pulse_width"; + related_pin : "A_BIST_CLK"; + rise_constraint("CLKTRAN_constraint_template") { + index_1("0.008,0.5952"); + values("0.4,0.4"); + } + } + + related_power_pin : VDD; + related_ground_pin : VSS; + + internal_power() { + when : "!A_BIST_MEN & !A_BIST_WEN & !A_BIST_REN"; + rise_power("scalar"){ + values (0); + } + fall_power("scalar"){ + values (0); + } + } + internal_power() { + when : "!A_BIST_MEN & A_BIST_WEN & !A_BIST_REN"; + rise_power("scalar"){ + values (0.5014); + } + fall_power("scalar"){ + values (0); + } + } + internal_power() { + when : "A_BIST_MEN & A_BIST_WEN & !A_BIST_REN"; + rise_power("scalar"){ + values (19.4302); + } + fall_power("scalar"){ + values (0); + } + } + internal_power() { + when : "A_BIST_MEN & A_BIST_WEN & A_BIST_REN"; + rise_power("scalar"){ + values (20.3865); + } + fall_power("scalar"){ + values (0); + } + } + internal_power() { + when : "A_BIST_MEN & !A_BIST_WEN & A_BIST_REN"; + rise_power("scalar"){ + values (15.8142); + } + fall_power("scalar"){ + values (0); + } + } + internal_power() { + when : "!A_BIST_MEN & !A_BIST_WEN & A_BIST_REN"; + rise_power("scalar"){ + values (0.3165); + } + fall_power("scalar"){ + values (0); + } + } + internal_power() { + when : "!A_BIST_MEN & A_BIST_WEN & A_BIST_REN"; + rise_power("scalar"){ + values (0.6909); + } + fall_power("scalar"){ + values (0); + } + } + internal_power() { + when : "A_BIST_MEN & !A_BIST_WEN & !A_BIST_REN"; + rise_power("scalar"){ + values (0); + } + fall_power("scalar"){ + values (0); + } + } + } + bus(A_BIST_DIN) { + bus_type : D_15_0; + direction : input ; + capacitance : 0.00396073 ; + memory_write() { + address : A_BIST_ADDR ; + clocked_on : A_BIST_CLK; + } + + max_transition : "0.5952" ; + pin(A_BIST_DIN[15:0]) { + related_power_pin : VDD; + related_ground_pin : VSS; + internal_power() { + when : "A_BIST_MEN"; + rise_power("scalar"){ + values (0.0469); + } + fall_power("scalar"){ + values (0.0152); + } + } + internal_power() { + when : "!A_BIST_MEN"; + rise_power("scalar"){ + values (0.0453); + } + fall_power("scalar"){ + values (0.0145); + } + } + } + timing() { + timing_type : setup_rising; + related_pin : "A_BIST_CLK"; + when : "(A_BIST_WEN & A_BIST_MEN)"; + sdf_cond : "A_BIST_W_ACCESS"; + + rise_constraint("SIG2SRAM_constraint_template") { + index_1("0.0080,0.0288,0.0616,0.1072,0.1920,0.3496,0.5952"); + index_2("0.0080,0.0288,0.0616,0.1072,0.1920,0.3496,0.5952"); + values ("-0.6982,-0.6787,-0.6533,-0.6103,-0.5293,-0.3838,-0.1611",\ +"-0.7057,-0.6861,-0.6608,-0.6178,-0.5367,-0.3912,-0.1686",\ +"-0.7153,-0.6957,-0.6703,-0.6274,-0.5463,-0.4008,-0.1782",\ +"-0.7284,-0.7089,-0.6835,-0.6405,-0.5595,-0.4140,-0.1913",\ +"-0.7527,-0.7331,-0.7077,-0.6648,-0.5837,-0.4382,-0.2156",\ +"-0.7831,-0.7636,-0.7382,-0.6952,-0.6142,-0.4686,-0.2460",\ +"-0.8647,-0.8452,-0.8198,-0.7768,-0.6958,-0.5503,-0.3276"); + } + + fall_constraint("SIG2SRAM_constraint_template") { + index_1("0.0080,0.0288,0.0616,0.1072,0.1920,0.3496,0.5952"); + index_2("0.0080,0.0288,0.0616,0.1072,0.1920,0.3496,0.5952"); + values ("-0.6357,-0.6181,-0.5908,-0.5517,-0.4687,-0.3330,-0.1211",\ +"-0.6432,-0.6256,-0.5983,-0.5592,-0.4762,-0.3404,-0.1285",\ +"-0.6528,-0.6352,-0.6078,-0.5688,-0.4858,-0.3500,-0.1381",\ +"-0.6659,-0.6483,-0.6210,-0.5819,-0.4989,-0.3632,-0.1513",\ +"-0.6902,-0.6726,-0.6452,-0.6062,-0.5232,-0.3874,-0.1755",\ +"-0.7206,-0.7030,-0.6757,-0.6366,-0.5536,-0.4179,-0.2059",\ +"-0.8022,-0.7846,-0.7573,-0.7182,-0.6352,-0.4995,-0.2876"); + } + } + + timing() { + timing_type : hold_rising; + related_pin : "A_BIST_CLK"; + when : "(A_BIST_WEN & A_BIST_MEN)"; + sdf_cond : "A_BIST_W_ACCESS"; + + rise_constraint("SIG2SRAM_constraint_template") { + index_1("0.0080,0.0288,0.0616,0.1072,0.1920,0.3496,0.5952"); + index_2("0.0080,0.0288,0.0616,0.1072,0.1920,0.3496,0.5952"); + values ("0.8138,0.7923,0.7679,0.7250,0.6449,0.4984,0.2757",\ +"0.8213,0.7998,0.7754,0.7324,0.6523,0.5059,0.2832",\ +"0.8309,0.8094,0.7850,0.7420,0.6619,0.5154,0.2928",\ +"0.8440,0.8225,0.7981,0.7552,0.6751,0.5286,0.3059",\ +"0.8683,0.8468,0.8224,0.7794,0.6993,0.5528,0.3302",\ +"0.8987,0.8772,0.8528,0.8098,0.7298,0.5833,0.3606",\ +"0.9803,0.9588,0.9344,0.8915,0.8114,0.6649,0.4422"); + } + + fall_constraint("SIG2SRAM_constraint_template") { + index_1("0.0080,0.0288,0.0616,0.1072,0.1920,0.3496,0.5952"); + index_2("0.0080,0.0288,0.0616,0.1072,0.1920,0.3496,0.5952"); + values ("0.7396,0.7220,0.6947,0.6556,0.5726,0.4359,0.2250",\ +"0.7471,0.7295,0.7022,0.6631,0.5801,0.4434,0.2324",\ +"0.7567,0.7391,0.7117,0.6727,0.5897,0.4529,0.2420",\ +"0.7698,0.7522,0.7249,0.6858,0.6028,0.4661,0.2552",\ +"0.7941,0.7765,0.7491,0.7101,0.6271,0.4904,0.2794",\ +"0.8245,0.8069,0.7796,0.7405,0.6575,0.5208,0.3098",\ +"0.9061,0.8885,0.8612,0.8221,0.7391,0.6024,0.3915"); + } + } + } + +bus(A_DOUT) { + + bus_type : D_15_0; + direction : output ; + capacitance : 0 ; + max_capacitance : 0.064 ; + memory_read() { + address : A_ADDR ; + } + pin(A_DOUT[15:0]) { + related_power_pin : VDD; + related_ground_pin : VSS; + internal_power() { + rise_power("scalar") { + values (0); + } + fall_power("scalar") { + values (0); + } + } + } + timing() { + related_pin : "A_CLK"; + timing_type : rising_edge ; + timing_sense : non_unate ; + + cell_rise(SIG2SRAM_delay_template) { + index_1("0.0080,0.0288,0.0616,0.1072,0.1920,0.3496,0.5952"); + index_2("0.0008,0.0014,0.0051,0.0100,0.0339,0.0640"); + values ("6.3579,6.3612,6.3734,6.3874,6.4399,6.4978",\ +"6.3622,6.3656,6.3778,6.3917,6.4443,6.5021",\ +"6.3727,6.3760,6.3882,6.4022,6.4547,6.5126",\ +"6.3933,6.3967,6.4089,6.4228,6.4754,6.5332",\ +"6.4076,6.4109,6.4231,6.4371,6.4896,6.5475",\ +"6.4410,6.4444,6.4566,6.4705,6.5231,6.5809",\ +"6.5267,6.5301,6.5423,6.5562,6.6088,6.6666"); + } + cell_fall(SIG2SRAM_delay_template) { + index_1("0.0080,0.0288,0.0616,0.1072,0.1920,0.3496,0.5952"); + index_2("0.0008,0.0014,0.0051,0.0100,0.0339,0.0640"); + values ("6.2481,6.2503,6.2604,6.2720,6.3154,6.3592",\ +"6.2525,6.2547,6.2647,6.2764,6.3197,6.3636",\ +"6.2629,6.2651,6.2752,6.2868,6.3302,6.3740",\ +"6.2836,6.2858,6.2958,6.3075,6.3508,6.3947",\ +"6.2979,6.3000,6.3101,6.3218,6.3651,6.4089",\ +"6.3313,6.3335,6.3435,6.3552,6.3985,6.4424",\ +"6.4170,6.4192,6.4292,6.4409,6.4842,6.5281"); + } + + rise_transition(SRAM_load_template) { + index_1("0.0008,0.0014,0.0051,0.0100,0.0339,0.0640"); + values ("0.0560,0.0583,0.0696,0.0816,0.1519,0.2335"); + } + fall_transition(SRAM_load_template) { + index_1("0.0008,0.0014,0.0051,0.0100,0.0339,0.0640"); + values ("0.0428,0.0445,0.0538,0.0658,0.1181,0.1751"); + } + } +} + pin(B_DLY) { + direction : input ; + capacitance : 0.00387999 ; + max_transition : "1" ; + related_power_pin : VDD; + related_ground_pin : VSS; + internal_power() { + rise_power("scalar") { + values (0); + } + fall_power("scalar") { + values (0); + } + } + } + +bus(B_ADDR) { + bus_type : A_8_0; + direction : input ; + capacitance : 0.0129586 ; + pin(B_ADDR[0]) { + capacitance : 0.00588404 ; + } + pin(B_ADDR[1]) { + capacitance : 0.0080425 ; + } + pin(B_ADDR[2]) { + capacitance : 0.0112051 ; + } + pin(B_ADDR[3]) { + capacitance : 0.00706428 ; + } + pin(B_ADDR[4]) { + capacitance : 0.00656149 ; + } + pin(B_ADDR[5]) { + capacitance : 0.0111839 ; + } + pin(B_ADDR[6]) { + capacitance : 0.0140236 ; + } + pin(B_ADDR[7]) { + capacitance : 0.0111118 ; + } + max_transition : "0.5952" ; + pin(B_ADDR[8:0]) { + related_power_pin : VDD; + related_ground_pin : VSS; + internal_power() { + when : "B_MEN"; + rise_power("scalar"){ + values (0.0102); + } + fall_power("scalar"){ + values (0.0078); + } + } + internal_power() { + when : "!B_MEN"; + rise_power("scalar"){ + values (0.0149); + } + fall_power("scalar"){ + values (0.0029); + } + } + } + timing() { + timing_type : setup_rising; + related_pin : "B_CLK"; + when : "((B_WEN | B_REN)& B_MEN)" + sdf_cond : "B_RW_ACCESS" + + rise_constraint("SIG2SRAM_constraint_template") { + index_1("0.0080,0.0288,0.0616,0.1072,0.1920,0.3496,0.5952"); + index_2("0.0080,0.0288,0.0616,0.1072,0.1920,0.3496,0.5952"); + values ("-0.7371,-0.7176,-0.6863,-0.6434,-0.5652,-0.4168,-0.1980",\ +"-0.7566,-0.7371,-0.7059,-0.6629,-0.5848,-0.4363,-0.2137",\ +"-0.7879,-0.7645,-0.7332,-0.6902,-0.6121,-0.4637,-0.2449",\ +"-0.8309,-0.8074,-0.7762,-0.7332,-0.6551,-0.5066,-0.2879",\ +"-0.9051,-0.8895,-0.8543,-0.8113,-0.7332,-0.5887,-0.3660",\ +"-1.0418,-1.0262,-0.9949,-0.9480,-0.8699,-0.7293,-0.5027",\ +"-1.2684,-1.2449,-1.2176,-1.1707,-1.0965,-0.9480,-0.7293"); + } + + fall_constraint("SIG2SRAM_constraint_template") { + index_1("0.0080,0.0288,0.0616,0.1072,0.1920,0.3496,0.5952"); + index_2("0.0080,0.0288,0.0616,0.1072,0.1920,0.3496,0.5952"); + values ("-0.5926,-0.5730,-0.5418,-0.4988,-0.4246,-0.2879,-0.0730",\ +"-0.6121,-0.5926,-0.5613,-0.5223,-0.4441,-0.3074,-0.0887",\ +"-0.6395,-0.6199,-0.5926,-0.5496,-0.4715,-0.3348,-0.1160",\ +"-0.6863,-0.6668,-0.6355,-0.5965,-0.5184,-0.3777,-0.1590",\ +"-0.7605,-0.7410,-0.7137,-0.6746,-0.5926,-0.4559,-0.2410",\ +"-0.9012,-0.8816,-0.8504,-0.8113,-0.7332,-0.5926,-0.3895",\ +"-1.1238,-1.1043,-1.0769,-1.0379,-0.9559,-0.8191,-0.6004"); + } + } + + + timing() { + timing_type : hold_rising; + related_pin : "B_CLK"; + when : "((B_WEN | B_REN)& B_MEN)" + sdf_cond : "B_RW_ACCESS" + + rise_constraint("SIG2SRAM_constraint_template") { + index_1("0.0080,0.0288,0.0616,0.1072,0.1920,0.3496,0.5952"); + index_2("0.0080,0.0288,0.0616,0.1072,0.1920,0.3496,0.5952"); + values ("0.8488,0.8293,0.7980,0.7551,0.6730,0.5285,0.3059",\ +"0.8684,0.8488,0.8176,0.7746,0.6926,0.5480,0.3254",\ +"0.8996,0.8801,0.8449,0.8020,0.7238,0.5754,0.3527",\ +"0.9426,0.9191,0.8918,0.8488,0.7668,0.6223,0.3996",\ +"1.0168,1.0012,0.9699,0.9230,0.8449,0.7004,0.4777",\ +"1.1574,1.1379,1.1105,1.0598,0.9816,0.8371,0.6184",\ +"1.3801,1.3605,1.3254,1.2980,1.2043,1.0637,0.8371"); + } + + fall_constraint("SIG2SRAM_constraint_template") { + index_1("0.0080,0.0288,0.0616,0.1072,0.1920,0.3496,0.5952"); + index_2("0.0080,0.0288,0.0616,0.1072,0.1920,0.3496,0.5952"); + values ("0.6965,0.6770,0.6496,0.6066,0.5246,0.3918,0.1730",\ +"0.7160,0.6965,0.6652,0.6262,0.5441,0.4113,0.1965",\ +"0.7473,0.7277,0.6965,0.6535,0.5754,0.4426,0.2238",\ +"0.7863,0.7707,0.7395,0.7004,0.6223,0.4855,0.2629",\ +"0.8684,0.8449,0.8176,0.7785,0.7004,0.5637,0.3449",\ +"1.0051,0.9855,0.9855,0.9113,0.8332,0.7004,0.4895",\ +"1.2277,1.2082,1.1809,1.1379,1.0598,0.9230,0.7004"); + } + } +} +pin(B_WEN) { + direction : input ; + capacitance : 0.00313551 ; + max_transition : "0.5952" ; + related_power_pin : VDD; + related_ground_pin : VSS; + internal_power() { + when : "B_MEN"; + rise_power("scalar"){ + values (0.0036); + } + fall_power("scalar"){ + values (0.0006); + } + } + internal_power() { + when : "!B_MEN"; + rise_power("scalar"){ + values (0.0050); + } + fall_power("scalar"){ + values (0.0002); + } + } + timing() { + timing_type : setup_rising; + related_pin : "B_CLK"; + when : "B_MEN" + sdf_cond : "B_MEN" + + rise_constraint("SIG2SRAM_constraint_template") { + index_1("0.0080,0.0288,0.0616,0.1072,0.1920,0.3496,0.5952"); + index_2("0.0080,0.0288,0.0616,0.1072,0.1920,0.3496,0.5952"); + values ("0.3137,0.3332,0.3605,0.4035,0.4816,0.6223,0.8488",\ +"0.2980,0.3176,0.3410,0.3840,0.4660,0.6027,0.8293",\ +"0.2629,0.2824,0.3098,0.3527,0.4348,0.5754,0.7980",\ +"0.2199,0.2395,0.2668,0.3098,0.3918,0.5324,0.7590",\ +"0.1418,0.1613,0.1887,0.2316,0.3137,0.4348,0.6730",\ +"0.0012,0.0207,0.0520,0.0910,0.1730,0.3098,0.5285",\ +"-0.2215,-0.2020,-0.1746,-0.1277,-0.0496,0.0910,0.3098"); + } + + fall_constraint("SIG2SRAM_constraint_template") { + index_1("0.0080,0.0288,0.0616,0.1072,0.1920,0.3496,0.5952"); + index_2("0.0080,0.0288,0.0616,0.1072,0.1920,0.3496,0.5952"); + values ("0.4504,0.4699,0.4973,0.5324,0.6027,0.7355,0.9699",\ +"0.4309,0.4504,0.4777,0.5129,0.5910,0.7160,0.9504",\ +"0.3996,0.4191,0.4465,0.4816,0.5520,0.6848,0.9191",\ +"0.3605,0.3762,0.4035,0.4387,0.5168,0.6418,0.8723",\ +"0.2785,0.2980,0.3215,0.3605,0.4348,0.5637,0.7980",\ +"0.1379,0.1574,0.1809,0.2199,0.2980,0.4309,0.6457",\ +"-0.0809,-0.0613,-0.0340,0.0051,0.0832,0.2160,0.4191"); + } + } + + + timing() { + timing_type : hold_rising; + related_pin : "B_CLK"; + when : "B_MEN" + sdf_cond : "B_MEN" + + rise_constraint("SIG2SRAM_constraint_template") { + index_1("0.0080,0.0288,0.0616,0.1072,0.1920,0.3496,0.5952"); + index_2("0.0080,0.0288,0.0616,0.1072,0.1920,0.3496,0.5952"); + values ("0.3723,0.3527,0.3215,0.2785,0.1965,0.0559,-0.1668",\ +"0.3918,0.3723,0.3449,0.2980,0.2160,0.0754,-0.1473",\ +"0.4152,0.3996,0.3684,0.3254,0.2434,0.1066,-0.1199",\ +"0.4621,0.4465,0.4152,0.3723,0.2863,0.1496,-0.0730",\ +"0.5324,0.5207,0.4895,0.4465,0.3645,0.2199,0.0051",\ +"0.6770,0.6535,0.6301,0.5832,0.5090,0.3605,0.1418",\ +"0.9035,0.8879,0.8566,0.8137,0.7316,0.5871,0.3684"); + } + + fall_constraint("SIG2SRAM_constraint_template") { + index_1("0.0080,0.0288,0.0616,0.1072,0.1920,0.3496,0.5952"); + index_2("0.0080,0.0288,0.0616,0.1072,0.1920,0.3496,0.5952"); + values ("0.3762,0.3566,0.3293,0.2863,0.2043,0.0676,-0.1434",\ +"0.3957,0.3762,0.3488,0.3059,0.2238,0.0871,-0.1199",\ +"0.4230,0.4035,0.3723,0.3332,0.2512,0.1184,-0.0965",\ +"0.4660,0.4465,0.4191,0.3762,0.2941,0.1613,-0.0496",\ +"0.5324,0.5168,0.4973,0.4543,0.3723,0.2316,0.0285",\ +"0.6809,0.6613,0.6340,0.5910,0.5129,0.3645,0.1652",\ +"0.9113,0.8918,0.8605,0.8176,0.7395,0.5988,0.3879"); + } + } + } +pin(B_REN) { + direction : input ; + capacitance : 0.00381144 ; + max_transition : "0.5952" ; + related_power_pin : VDD; + related_ground_pin : VSS; + internal_power() { + when : "B_MEN"; + rise_power("scalar"){ + values (0.0041); + } + fall_power("scalar"){ + values (0.0014); + } + } + internal_power() { + when : "!B_MEN"; + rise_power("scalar"){ + values (0.0041); + } + fall_power("scalar"){ + values (0.0012); + } + } + timing() { + timing_type : setup_rising; + related_pin : "B_CLK"; + when : "B_MEN" + sdf_cond : "B_MEN" + + rise_constraint("SIG2SRAM_constraint_template") { + index_1("0.0080,0.0288,0.0616,0.1072,0.1920,0.3496,0.5952"); + index_2("0.0080,0.0288,0.0616,0.1072,0.1920,0.3496,0.5952"); + values ("-0.0770,-0.0574,-0.0262,0.0168,0.0949,0.2355,0.4582",\ +"-0.0965,-0.0770,-0.0457,-0.0027,0.0754,0.2160,0.4387",\ +"-0.1199,-0.1004,-0.0730,-0.0262,0.0520,0.1887,0.4113",\ +"-0.1590,-0.1434,-0.1160,-0.0730,0.0051,0.1457,0.3645",\ +"-0.2449,-0.2254,-0.1941,-0.1473,-0.0770,0.0676,0.2863",\ +"-0.3816,-0.3699,-0.3387,-0.2801,-0.2215,-0.0770,0.1457",\ +"-0.6121,-0.5926,-0.5613,-0.5145,-0.4363,-0.2996,-0.0730"); + } + + fall_constraint("SIG2SRAM_constraint_template") { + index_1("0.0080,0.0288,0.0616,0.1072,0.1920,0.3496,0.5952"); + index_2("0.0080,0.0288,0.0616,0.1072,0.1920,0.3496,0.5952"); + values ("0.1262,0.1457,0.1691,0.2121,0.2824,0.4191,0.6457",\ +"0.1105,0.1262,0.1496,0.1887,0.2629,0.3996,0.6262",\ +"0.0793,0.0949,0.1223,0.1652,0.2395,0.3684,0.5949",\ +"0.0363,0.0559,0.0793,0.1223,0.2004,0.3410,0.5520",\ +"-0.0457,-0.0262,0.0012,0.0441,0.1301,0.2629,0.4738",\ +"-0.1902,-0.1746,-0.1434,-0.1043,-0.0184,0.1223,0.3332",\ +"-0.4129,-0.3934,-0.3660,-0.3230,-0.2449,-0.1043,0.1105"); + } + } + + + timing() { + timing_type : hold_rising; + related_pin : "B_CLK"; + when : "B_MEN" + sdf_cond : "B_MEN" + + rise_constraint("SIG2SRAM_constraint_template") { + index_1("0.0080,0.0288,0.0616,0.1072,0.1920,0.3496,0.5952"); + index_2("0.0080,0.0288,0.0616,0.1072,0.1920,0.3496,0.5952"); + values ("0.4113,0.3918,0.3645,0.3176,0.2395,0.0988,-0.1238",\ +"0.4309,0.4113,0.3840,0.3371,0.2590,0.1184,-0.1043",\ +"0.4582,0.4387,0.4113,0.3645,0.2824,0.1457,-0.0770",\ +"0.5051,0.4816,0.4543,0.4074,0.3293,0.1887,-0.0340",\ +"0.5715,0.5598,0.5324,0.4895,0.4035,0.2512,0.0441",\ +"0.7043,0.7004,0.6730,0.6262,0.5402,0.3957,0.1809",\ +"0.9387,0.9270,0.8957,0.8527,0.7746,0.6262,0.4074"); + } + + fall_constraint("SIG2SRAM_constraint_template") { + index_1("0.0080,0.0288,0.0616,0.1072,0.1920,0.3496,0.5952"); + index_2("0.0080,0.0288,0.0616,0.1072,0.1920,0.3496,0.5952"); + values ("0.4152,0.3918,0.3645,0.3215,0.2395,0.1027,-0.1082",\ +"0.4309,0.4113,0.3801,0.3410,0.2590,0.1223,-0.0926",\ +"0.4582,0.4387,0.4074,0.3684,0.2863,0.1496,-0.0613",\ +"0.5012,0.4816,0.4504,0.4074,0.3293,0.1887,-0.0145",\ +"0.5715,0.5559,0.5285,0.4816,0.3996,0.2512,0.0598",\ +"0.7160,0.7004,0.6691,0.6262,0.5520,0.4035,0.2004",\ +"0.9387,0.9191,0.8957,0.8488,0.7707,0.6262,0.4113"); + } + } + } +pin(B_MEN) { + direction : input ; + capacitance : 0.00300347 ; + max_transition : "0.5952" ; + related_power_pin : VDD; + related_ground_pin : VSS; + internal_power() { + rise_power("scalar"){ + values (0.0161); + } + fall_power("scalar"){ + values (0.0002); + } + } + timing() { + timing_type : setup_rising; + related_pin : "B_CLK"; + + rise_constraint("SIG2SRAM_constraint_template") { + index_1("0.0080,0.0288,0.0616,0.1072,0.1920,0.3496,0.5952"); + index_2("0.0080,0.0288,0.0616,0.1072,0.1920,0.3496,0.5952"); + values ("0.3215,0.3449,0.3684,0.4113,0.4895,0.6301,0.8527",\ +"0.3059,0.3254,0.3527,0.3957,0.4738,0.6145,0.8371",\ +"0.2746,0.2941,0.3215,0.3645,0.4426,0.5871,0.8059",\ +"0.2316,0.2512,0.2785,0.3215,0.3996,0.5402,0.7629",\ +"0.1496,0.1730,0.1965,0.2395,0.3215,0.4660,0.6848",\ +"0.0090,0.0285,0.0598,0.1027,0.1809,0.3176,0.5402",\ +"-0.2098,-0.1902,-0.1668,-0.1199,-0.0418,0.0988,0.3137"); + } + + fall_constraint("SIG2SRAM_constraint_template") { + index_1("0.0080,0.0288,0.0616,0.1072,0.1920,0.3496,0.5952"); + index_2("0.0080,0.0288,0.0616,0.1072,0.1920,0.3496,0.5952"); + values ("0.4582,0.4738,0.5012,0.5363,0.6145,0.7395,0.9738",\ +"0.4387,0.4543,0.4816,0.5207,0.5910,0.7199,0.9582",\ +"0.4035,0.4230,0.4504,0.4855,0.5637,0.6887,0.9230",\ +"0.3645,0.3840,0.4074,0.4465,0.5285,0.6496,0.8840",\ +"0.2824,0.3020,0.3254,0.3645,0.4465,0.5715,0.7980",\ +"0.1418,0.1613,0.1887,0.2238,0.3020,0.4309,0.6496",\ +"-0.0770,-0.0574,-0.0301,0.0090,0.0910,0.2238,0.4191"); + } + } + + + timing() { + timing_type : hold_rising; + related_pin : "B_CLK"; + + rise_constraint("SIG2SRAM_constraint_template") { + index_1("0.0080,0.0288,0.0616,0.1072,0.1920,0.3496,0.5952"); + index_2("0.0080,0.0288,0.0616,0.1072,0.1920,0.3496,0.5952"); + values ("0.3762,0.3605,0.3293,0.2863,0.2043,0.0637,-0.1629",\ +"0.3996,0.3801,0.3488,0.3020,0.2238,0.0832,-0.1395",\ +"0.4230,0.4074,0.3723,0.3293,0.2473,0.1105,-0.1121",\ +"0.4621,0.4465,0.4152,0.3762,0.2941,0.1535,-0.0691",\ +"0.5441,0.5285,0.4973,0.4465,0.3684,0.2316,0.0090",\ +"0.6848,0.6652,0.6301,0.5910,0.5129,0.3605,0.1496",\ +"0.9074,0.8918,0.8566,0.8215,0.7395,0.5910,0.3723"); + } + + fall_constraint("SIG2SRAM_constraint_template") { + index_1("0.0080,0.0288,0.0616,0.1072,0.1920,0.3496,0.5952"); + index_2("0.0080,0.0288,0.0616,0.1072,0.1920,0.3496,0.5952"); + values ("0.3762,0.3605,0.3332,0.2863,0.2043,0.0715,-0.1395",\ +"0.3996,0.3762,0.3488,0.3059,0.2238,0.0910,-0.1199",\ +"0.4270,0.4035,0.3762,0.3332,0.2512,0.1184,-0.0965",\ +"0.4699,0.4504,0.4191,0.3762,0.2941,0.1613,-0.0496",\ +"0.5441,0.5285,0.4973,0.4543,0.3762,0.2355,0.0324",\ +"0.6770,0.6613,0.6340,0.5949,0.5207,0.3762,0.1652",\ +"0.9074,0.8918,0.8605,0.8176,0.7395,0.6027,0.3918"); + } + } + } +bus(B_BM) { + bus_type : D_15_0; + direction : input ; + capacitance : 0.00293202 ; + max_transition : "0.5952" ; + pin(B_BM[15:0]) { + related_power_pin : VDD; + related_ground_pin : VSS; + internal_power() { + when : "B_MEN"; + rise_power("scalar"){ + values (0.0469); + } + fall_power("scalar"){ + values (0.0152); + } + } + internal_power() { + when : "!B_MEN"; + rise_power("scalar"){ + values (0.0453); + } + fall_power("scalar"){ + values (0.0145); + } + } + } + timing() { + timing_type : setup_rising; + related_pin : "B_CLK"; + when : "(B_WEN & B_MEN)" + sdf_cond : "B_RW_ACCESS" + + rise_constraint("SIG2SRAM_constraint_template") { + index_1("0.0080,0.0288,0.0616,0.1072,0.1920,0.3496,0.5952"); + index_2("0.0080,0.0288,0.0616,0.1072,0.1920,0.3496,0.5952"); + values ("-0.6982,-0.6787,-0.6533,-0.6103,-0.5293,-0.3838,-0.1611",\ +"-0.7057,-0.6861,-0.6608,-0.6178,-0.5367,-0.3912,-0.1686",\ +"-0.7153,-0.6957,-0.6703,-0.6274,-0.5463,-0.4008,-0.1782",\ +"-0.7284,-0.7089,-0.6835,-0.6405,-0.5595,-0.4140,-0.1913",\ +"-0.7527,-0.7331,-0.7077,-0.6648,-0.5837,-0.4382,-0.2156",\ +"-0.7831,-0.7636,-0.7382,-0.6952,-0.6142,-0.4686,-0.2460",\ +"-0.8647,-0.8452,-0.8198,-0.7768,-0.6958,-0.5503,-0.3276"); + } + + fall_constraint("SIG2SRAM_constraint_template") { + index_1("0.0080,0.0288,0.0616,0.1072,0.1920,0.3496,0.5952"); + index_2("0.0080,0.0288,0.0616,0.1072,0.1920,0.3496,0.5952"); + values ("-0.6357,-0.6181,-0.5908,-0.5517,-0.4687,-0.3330,-0.1211",\ +"-0.6432,-0.6256,-0.5983,-0.5592,-0.4762,-0.3404,-0.1285",\ +"-0.6528,-0.6352,-0.6078,-0.5688,-0.4858,-0.3500,-0.1381",\ +"-0.6659,-0.6483,-0.6210,-0.5819,-0.4989,-0.3632,-0.1513",\ +"-0.6902,-0.6726,-0.6452,-0.6062,-0.5232,-0.3874,-0.1755",\ +"-0.7206,-0.7030,-0.6757,-0.6366,-0.5536,-0.4179,-0.2059",\ +"-0.8022,-0.7846,-0.7573,-0.7182,-0.6352,-0.4995,-0.2876"); + } + } + + + timing() { + timing_type : hold_rising; + related_pin : "B_CLK"; + when : "(B_WEN & B_MEN)" + sdf_cond : "B_RW_ACCESS" + + rise_constraint("SIG2SRAM_constraint_template") { + index_1("0.0080,0.0288,0.0616,0.1072,0.1920,0.3496,0.5952"); + index_2("0.0080,0.0288,0.0616,0.1072,0.1920,0.3496,0.5952"); + values ("0.8138,0.7923,0.7679,0.7250,0.6449,0.4984,0.2757",\ +"0.8213,0.7998,0.7754,0.7324,0.6523,0.5059,0.2832",\ +"0.8309,0.8094,0.7850,0.7420,0.6619,0.5154,0.2928",\ +"0.8440,0.8225,0.7981,0.7552,0.6751,0.5286,0.3059",\ +"0.8683,0.8468,0.8224,0.7794,0.6993,0.5528,0.3302",\ +"0.8987,0.8772,0.8528,0.8098,0.7298,0.5833,0.3606",\ +"0.9803,0.9588,0.9344,0.8915,0.8114,0.6649,0.4422"); + } + + fall_constraint("SIG2SRAM_constraint_template") { + index_1("0.0080,0.0288,0.0616,0.1072,0.1920,0.3496,0.5952"); + index_2("0.0080,0.0288,0.0616,0.1072,0.1920,0.3496,0.5952"); + values ("0.7396,0.7220,0.6947,0.6556,0.5726,0.4359,0.2250",\ +"0.7471,0.7295,0.7022,0.6631,0.5801,0.4434,0.2324",\ +"0.7567,0.7391,0.7117,0.6727,0.5897,0.4529,0.2420",\ +"0.7698,0.7522,0.7249,0.6858,0.6028,0.4661,0.2552",\ +"0.7941,0.7765,0.7491,0.7101,0.6271,0.4904,0.2794",\ +"0.8245,0.8069,0.7796,0.7405,0.6575,0.5208,0.3098",\ +"0.9061,0.8885,0.8612,0.8221,0.7391,0.6024,0.3915"); + } + } +} + pin(B_CLK) { + direction : input; + capacitance : 0.00378957; + max_transition : "0.5952"; + clock : "true" ; + pin_func_type : active_rising ; + + timing () { + timing_type : "min_pulse_width"; + related_pin : "B_CLK"; + rise_constraint("CLKTRAN_constraint_template") { + index_1("0.008,0.5952"); + values("0.4,0.4"); + } + } + + related_power_pin : VDD; + related_ground_pin : VSS; + + internal_power() { + when : "!B_MEN & !B_WEN & !B_REN"; + rise_power("scalar"){ + values (0); + } + fall_power("scalar"){ + values (0); + } + } + internal_power() { + when : "!B_MEN & B_WEN & !B_REN"; + rise_power("scalar"){ + values (0.5014); + } + fall_power("scalar"){ + values (0); + } + } + internal_power() { + when : "B_MEN & B_WEN & !B_REN"; + rise_power("scalar"){ + values (19.4302); + } + fall_power("scalar"){ + values (0); + } + } + internal_power() { + when : "B_MEN & B_WEN & B_REN"; + rise_power("scalar"){ + values (20.3865); + } + fall_power("scalar"){ + values (0); + } + } + internal_power() { + when : "B_MEN & !B_WEN & B_REN"; + rise_power("scalar"){ + values (15.8142); + } + fall_power("scalar"){ + values (0); + } + } + internal_power() { + when : "!B_MEN & !B_WEN & B_REN"; + rise_power("scalar"){ + values (0.3165); + } + fall_power("scalar"){ + values (0); + } + } + internal_power() { + when : "!B_MEN & B_WEN & B_REN"; + rise_power("scalar"){ + values (0.6909); + } + fall_power("scalar"){ + values (0); + } + } + internal_power() { + when : "B_MEN & !B_WEN & !B_REN"; + rise_power("scalar"){ + values (0); + } + fall_power("scalar"){ + values (0); + } + } + } + bus(B_DIN) { + bus_type : D_15_0; + direction : input ; + capacitance : 0.00460366 ; + memory_write() { + address : B_ADDR ; + clocked_on : B_CLK; + } + + max_transition : "0.5952" ; + pin(B_DIN[15:0]) { + related_power_pin : VDD; + related_ground_pin : VSS; + internal_power() { + when : "B_MEN"; + rise_power("scalar"){ + values (0.0469); + } + fall_power("scalar"){ + values (0.0152); + } + } + internal_power() { + when : "!B_MEN"; + rise_power("scalar"){ + values (0.0453); + } + fall_power("scalar"){ + values (0.0145); + } + } + } + timing() { + timing_type : setup_rising; + related_pin : "B_CLK"; + when : "(B_WEN & B_MEN)"; + sdf_cond : "B_W_ACCESS"; + + rise_constraint("SIG2SRAM_constraint_template") { + index_1("0.0080,0.0288,0.0616,0.1072,0.1920,0.3496,0.5952"); + index_2("0.0080,0.0288,0.0616,0.1072,0.1920,0.3496,0.5952"); + values ("-0.6982,-0.6787,-0.6533,-0.6103,-0.5293,-0.3838,-0.1611",\ +"-0.7057,-0.6861,-0.6608,-0.6178,-0.5367,-0.3912,-0.1686",\ +"-0.7153,-0.6957,-0.6703,-0.6274,-0.5463,-0.4008,-0.1782",\ +"-0.7284,-0.7089,-0.6835,-0.6405,-0.5595,-0.4140,-0.1913",\ +"-0.7527,-0.7331,-0.7077,-0.6648,-0.5837,-0.4382,-0.2156",\ +"-0.7831,-0.7636,-0.7382,-0.6952,-0.6142,-0.4686,-0.2460",\ +"-0.8647,-0.8452,-0.8198,-0.7768,-0.6958,-0.5503,-0.3276"); + } + + fall_constraint("SIG2SRAM_constraint_template") { + index_1("0.0080,0.0288,0.0616,0.1072,0.1920,0.3496,0.5952"); + index_2("0.0080,0.0288,0.0616,0.1072,0.1920,0.3496,0.5952"); + values ("-0.6357,-0.6181,-0.5908,-0.5517,-0.4687,-0.3330,-0.1211",\ +"-0.6432,-0.6256,-0.5983,-0.5592,-0.4762,-0.3404,-0.1285",\ +"-0.6528,-0.6352,-0.6078,-0.5688,-0.4858,-0.3500,-0.1381",\ +"-0.6659,-0.6483,-0.6210,-0.5819,-0.4989,-0.3632,-0.1513",\ +"-0.6902,-0.6726,-0.6452,-0.6062,-0.5232,-0.3874,-0.1755",\ +"-0.7206,-0.7030,-0.6757,-0.6366,-0.5536,-0.4179,-0.2059",\ +"-0.8022,-0.7846,-0.7573,-0.7182,-0.6352,-0.4995,-0.2876"); + } + } + + timing() { + timing_type : hold_rising; + related_pin : "B_CLK"; + when : "(B_WEN & B_MEN)"; + sdf_cond : "B_W_ACCESS"; + + rise_constraint("SIG2SRAM_constraint_template") { + index_1("0.0080,0.0288,0.0616,0.1072,0.1920,0.3496,0.5952"); + index_2("0.0080,0.0288,0.0616,0.1072,0.1920,0.3496,0.5952"); + values ("0.8138,0.7923,0.7679,0.7250,0.6449,0.4984,0.2757",\ +"0.8213,0.7998,0.7754,0.7324,0.6523,0.5059,0.2832",\ +"0.8309,0.8094,0.7850,0.7420,0.6619,0.5154,0.2928",\ +"0.8440,0.8225,0.7981,0.7552,0.6751,0.5286,0.3059",\ +"0.8683,0.8468,0.8224,0.7794,0.6993,0.5528,0.3302",\ +"0.8987,0.8772,0.8528,0.8098,0.7298,0.5833,0.3606",\ +"0.9803,0.9588,0.9344,0.8915,0.8114,0.6649,0.4422"); + } + + fall_constraint("SIG2SRAM_constraint_template") { + index_1("0.0080,0.0288,0.0616,0.1072,0.1920,0.3496,0.5952"); + index_2("0.0080,0.0288,0.0616,0.1072,0.1920,0.3496,0.5952"); + values ("0.7396,0.7220,0.6947,0.6556,0.5726,0.4359,0.2250",\ +"0.7471,0.7295,0.7022,0.6631,0.5801,0.4434,0.2324",\ +"0.7567,0.7391,0.7117,0.6727,0.5897,0.4529,0.2420",\ +"0.7698,0.7522,0.7249,0.6858,0.6028,0.4661,0.2552",\ +"0.7941,0.7765,0.7491,0.7101,0.6271,0.4904,0.2794",\ +"0.8245,0.8069,0.7796,0.7405,0.6575,0.5208,0.3098",\ +"0.9061,0.8885,0.8612,0.8221,0.7391,0.6024,0.3915"); + } + } + } + + pin(B_BIST_EN) { + direction : input ; + capacitance : 0.00387999 ; + max_transition : "1" ; + related_power_pin : VDD; + related_ground_pin : VSS; + internal_power() { + rise_power("scalar") { + values (0); + } + fall_power("scalar") { + values (0); + } + } + } + +bus(B_BIST_ADDR) { + bus_type : A_8_0; + direction : input ; + capacitance : 0.0129586 ; + pin(B_BIST_ADDR[0]) { + capacitance : 0.00588404 ; + } + pin(B_BIST_ADDR[1]) { + capacitance : 0.0080425 ; + } + pin(B_BIST_ADDR[2]) { + capacitance : 0.0112051 ; + } + pin(B_BIST_ADDR[3]) { + capacitance : 0.00706428 ; + } + pin(B_BIST_ADDR[4]) { + capacitance : 0.00656149 ; + } + pin(B_BIST_ADDR[5]) { + capacitance : 0.0111839 ; + } + pin(B_BIST_ADDR[6]) { + capacitance : 0.0140236 ; + } + pin(B_BIST_ADDR[7]) { + capacitance : 0.0111118 ; + } + max_transition : "0.5952" ; + pin(B_BIST_ADDR[8:0]) { + related_power_pin : VDD; + related_ground_pin : VSS; + internal_power() { + when : "B_BIST_MEN"; + rise_power("scalar"){ + values (0.0102); + } + fall_power("scalar"){ + values (0.0078); + } + } + internal_power() { + when : "!B_BIST_MEN"; + rise_power("scalar"){ + values (0.0149); + } + fall_power("scalar"){ + values (0.0029); + } + } + } + timing() { + timing_type : setup_rising; + related_pin : "B_BIST_CLK"; + when : "((B_BIST_WEN | B_BIST_REN)& B_BIST_MEN)" + sdf_cond : "B_BIST_RW_ACCESS" + + rise_constraint("SIG2SRAM_constraint_template") { + index_1("0.0080,0.0288,0.0616,0.1072,0.1920,0.3496,0.5952"); + index_2("0.0080,0.0288,0.0616,0.1072,0.1920,0.3496,0.5952"); + values ("-0.7371,-0.7176,-0.6863,-0.6434,-0.5652,-0.4168,-0.1980",\ +"-0.7566,-0.7371,-0.7059,-0.6629,-0.5848,-0.4363,-0.2137",\ +"-0.7879,-0.7645,-0.7332,-0.6902,-0.6121,-0.4637,-0.2449",\ +"-0.8309,-0.8074,-0.7762,-0.7332,-0.6551,-0.5066,-0.2879",\ +"-0.9051,-0.8895,-0.8543,-0.8113,-0.7332,-0.5887,-0.3660",\ +"-1.0418,-1.0262,-0.9949,-0.9480,-0.8699,-0.7293,-0.5027",\ +"-1.2684,-1.2449,-1.2176,-1.1707,-1.0965,-0.9480,-0.7293"); + } + + fall_constraint("SIG2SRAM_constraint_template") { + index_1("0.0080,0.0288,0.0616,0.1072,0.1920,0.3496,0.5952"); + index_2("0.0080,0.0288,0.0616,0.1072,0.1920,0.3496,0.5952"); + values ("-0.5926,-0.5730,-0.5418,-0.4988,-0.4246,-0.2879,-0.0730",\ +"-0.6121,-0.5926,-0.5613,-0.5223,-0.4441,-0.3074,-0.0887",\ +"-0.6395,-0.6199,-0.5926,-0.5496,-0.4715,-0.3348,-0.1160",\ +"-0.6863,-0.6668,-0.6355,-0.5965,-0.5184,-0.3777,-0.1590",\ +"-0.7605,-0.7410,-0.7137,-0.6746,-0.5926,-0.4559,-0.2410",\ +"-0.9012,-0.8816,-0.8504,-0.8113,-0.7332,-0.5926,-0.3895",\ +"-1.1238,-1.1043,-1.0769,-1.0379,-0.9559,-0.8191,-0.6004"); + } + } + + + timing() { + timing_type : hold_rising; + related_pin : "B_BIST_CLK"; + when : "((B_BIST_WEN | B_BIST_REN)& B_BIST_MEN)" + sdf_cond : "B_BIST_RW_ACCESS" + + rise_constraint("SIG2SRAM_constraint_template") { + index_1("0.0080,0.0288,0.0616,0.1072,0.1920,0.3496,0.5952"); + index_2("0.0080,0.0288,0.0616,0.1072,0.1920,0.3496,0.5952"); + values ("0.8488,0.8293,0.7980,0.7551,0.6730,0.5285,0.3059",\ +"0.8684,0.8488,0.8176,0.7746,0.6926,0.5480,0.3254",\ +"0.8996,0.8801,0.8449,0.8020,0.7238,0.5754,0.3527",\ +"0.9426,0.9191,0.8918,0.8488,0.7668,0.6223,0.3996",\ +"1.0168,1.0012,0.9699,0.9230,0.8449,0.7004,0.4777",\ +"1.1574,1.1379,1.1105,1.0598,0.9816,0.8371,0.6184",\ +"1.3801,1.3605,1.3254,1.2980,1.2043,1.0637,0.8371"); + } + + fall_constraint("SIG2SRAM_constraint_template") { + index_1("0.0080,0.0288,0.0616,0.1072,0.1920,0.3496,0.5952"); + index_2("0.0080,0.0288,0.0616,0.1072,0.1920,0.3496,0.5952"); + values ("0.6965,0.6770,0.6496,0.6066,0.5246,0.3918,0.1730",\ +"0.7160,0.6965,0.6652,0.6262,0.5441,0.4113,0.1965",\ +"0.7473,0.7277,0.6965,0.6535,0.5754,0.4426,0.2238",\ +"0.7863,0.7707,0.7395,0.7004,0.6223,0.4855,0.2629",\ +"0.8684,0.8449,0.8176,0.7785,0.7004,0.5637,0.3449",\ +"1.0051,0.9855,0.9855,0.9113,0.8332,0.7004,0.4895",\ +"1.2277,1.2082,1.1809,1.1379,1.0598,0.9230,0.7004"); + } + } +} +pin(B_BIST_WEN) { + direction : input ; + capacitance : 0.00313551 ; + max_transition : "0.5952" ; + related_power_pin : VDD; + related_ground_pin : VSS; + internal_power() { + when : "B_BIST_MEN"; + rise_power("scalar"){ + values (0.0036); + } + fall_power("scalar"){ + values (0.0006); + } + } + internal_power() { + when : "!B_BIST_MEN"; + rise_power("scalar"){ + values (0.0050); + } + fall_power("scalar"){ + values (0.0002); + } + } + timing() { + timing_type : setup_rising; + related_pin : "B_BIST_CLK"; + when : "B_BIST_MEN" + sdf_cond : "B_BIST_MEN" + + rise_constraint("SIG2SRAM_constraint_template") { + index_1("0.0080,0.0288,0.0616,0.1072,0.1920,0.3496,0.5952"); + index_2("0.0080,0.0288,0.0616,0.1072,0.1920,0.3496,0.5952"); + values ("0.3137,0.3332,0.3605,0.4035,0.4816,0.6223,0.8488",\ +"0.2980,0.3176,0.3410,0.3840,0.4660,0.6027,0.8293",\ +"0.2629,0.2824,0.3098,0.3527,0.4348,0.5754,0.7980",\ +"0.2199,0.2395,0.2668,0.3098,0.3918,0.5324,0.7590",\ +"0.1418,0.1613,0.1887,0.2316,0.3137,0.4348,0.6730",\ +"0.0012,0.0207,0.0520,0.0910,0.1730,0.3098,0.5285",\ +"-0.2215,-0.2020,-0.1746,-0.1277,-0.0496,0.0910,0.3098"); + } + + fall_constraint("SIG2SRAM_constraint_template") { + index_1("0.0080,0.0288,0.0616,0.1072,0.1920,0.3496,0.5952"); + index_2("0.0080,0.0288,0.0616,0.1072,0.1920,0.3496,0.5952"); + values ("0.4504,0.4699,0.4973,0.5324,0.6027,0.7355,0.9699",\ +"0.4309,0.4504,0.4777,0.5129,0.5910,0.7160,0.9504",\ +"0.3996,0.4191,0.4465,0.4816,0.5520,0.6848,0.9191",\ +"0.3605,0.3762,0.4035,0.4387,0.5168,0.6418,0.8723",\ +"0.2785,0.2980,0.3215,0.3605,0.4348,0.5637,0.7980",\ +"0.1379,0.1574,0.1809,0.2199,0.2980,0.4309,0.6457",\ +"-0.0809,-0.0613,-0.0340,0.0051,0.0832,0.2160,0.4191"); + } + } + + + timing() { + timing_type : hold_rising; + related_pin : "B_BIST_CLK"; + when : "B_BIST_MEN" + sdf_cond : "B_BIST_MEN" + + rise_constraint("SIG2SRAM_constraint_template") { + index_1("0.0080,0.0288,0.0616,0.1072,0.1920,0.3496,0.5952"); + index_2("0.0080,0.0288,0.0616,0.1072,0.1920,0.3496,0.5952"); + values ("0.3723,0.3527,0.3215,0.2785,0.1965,0.0559,-0.1668",\ +"0.3918,0.3723,0.3449,0.2980,0.2160,0.0754,-0.1473",\ +"0.4152,0.3996,0.3684,0.3254,0.2434,0.1066,-0.1199",\ +"0.4621,0.4465,0.4152,0.3723,0.2863,0.1496,-0.0730",\ +"0.5324,0.5207,0.4895,0.4465,0.3645,0.2199,0.0051",\ +"0.6770,0.6535,0.6301,0.5832,0.5090,0.3605,0.1418",\ +"0.9035,0.8879,0.8566,0.8137,0.7316,0.5871,0.3684"); + } + + fall_constraint("SIG2SRAM_constraint_template") { + index_1("0.0080,0.0288,0.0616,0.1072,0.1920,0.3496,0.5952"); + index_2("0.0080,0.0288,0.0616,0.1072,0.1920,0.3496,0.5952"); + values ("0.3762,0.3566,0.3293,0.2863,0.2043,0.0676,-0.1434",\ +"0.3957,0.3762,0.3488,0.3059,0.2238,0.0871,-0.1199",\ +"0.4230,0.4035,0.3723,0.3332,0.2512,0.1184,-0.0965",\ +"0.4660,0.4465,0.4191,0.3762,0.2941,0.1613,-0.0496",\ +"0.5324,0.5168,0.4973,0.4543,0.3723,0.2316,0.0285",\ +"0.6809,0.6613,0.6340,0.5910,0.5129,0.3645,0.1652",\ +"0.9113,0.8918,0.8605,0.8176,0.7395,0.5988,0.3879"); + } + } + } +pin(B_BIST_REN) { + direction : input ; + capacitance : 0.00381144 ; + max_transition : "0.5952" ; + related_power_pin : VDD; + related_ground_pin : VSS; + internal_power() { + when : "B_BIST_MEN"; + rise_power("scalar"){ + values (0.0041); + } + fall_power("scalar"){ + values (0.0014); + } + } + internal_power() { + when : "!B_BIST_MEN"; + rise_power("scalar"){ + values (0.0041); + } + fall_power("scalar"){ + values (0.0012); + } + } + timing() { + timing_type : setup_rising; + related_pin : "B_BIST_CLK"; + when : "B_BIST_MEN" + sdf_cond : "B_BIST_MEN" + + rise_constraint("SIG2SRAM_constraint_template") { + index_1("0.0080,0.0288,0.0616,0.1072,0.1920,0.3496,0.5952"); + index_2("0.0080,0.0288,0.0616,0.1072,0.1920,0.3496,0.5952"); + values ("-0.0770,-0.0574,-0.0262,0.0168,0.0949,0.2355,0.4582",\ +"-0.0965,-0.0770,-0.0457,-0.0027,0.0754,0.2160,0.4387",\ +"-0.1199,-0.1004,-0.0730,-0.0262,0.0520,0.1887,0.4113",\ +"-0.1590,-0.1434,-0.1160,-0.0730,0.0051,0.1457,0.3645",\ +"-0.2449,-0.2254,-0.1941,-0.1473,-0.0770,0.0676,0.2863",\ +"-0.3816,-0.3699,-0.3387,-0.2801,-0.2215,-0.0770,0.1457",\ +"-0.6121,-0.5926,-0.5613,-0.5145,-0.4363,-0.2996,-0.0730"); + } + + fall_constraint("SIG2SRAM_constraint_template") { + index_1("0.0080,0.0288,0.0616,0.1072,0.1920,0.3496,0.5952"); + index_2("0.0080,0.0288,0.0616,0.1072,0.1920,0.3496,0.5952"); + values ("0.1262,0.1457,0.1691,0.2121,0.2824,0.4191,0.6457",\ +"0.1105,0.1262,0.1496,0.1887,0.2629,0.3996,0.6262",\ +"0.0793,0.0949,0.1223,0.1652,0.2395,0.3684,0.5949",\ +"0.0363,0.0559,0.0793,0.1223,0.2004,0.3410,0.5520",\ +"-0.0457,-0.0262,0.0012,0.0441,0.1301,0.2629,0.4738",\ +"-0.1902,-0.1746,-0.1434,-0.1043,-0.0184,0.1223,0.3332",\ +"-0.4129,-0.3934,-0.3660,-0.3230,-0.2449,-0.1043,0.1105"); + } + } + + + timing() { + timing_type : hold_rising; + related_pin : "B_BIST_CLK"; + when : "B_BIST_MEN" + sdf_cond : "B_BIST_MEN" + + rise_constraint("SIG2SRAM_constraint_template") { + index_1("0.0080,0.0288,0.0616,0.1072,0.1920,0.3496,0.5952"); + index_2("0.0080,0.0288,0.0616,0.1072,0.1920,0.3496,0.5952"); + values ("0.4113,0.3918,0.3645,0.3176,0.2395,0.0988,-0.1238",\ +"0.4309,0.4113,0.3840,0.3371,0.2590,0.1184,-0.1043",\ +"0.4582,0.4387,0.4113,0.3645,0.2824,0.1457,-0.0770",\ +"0.5051,0.4816,0.4543,0.4074,0.3293,0.1887,-0.0340",\ +"0.5715,0.5598,0.5324,0.4895,0.4035,0.2512,0.0441",\ +"0.7043,0.7004,0.6730,0.6262,0.5402,0.3957,0.1809",\ +"0.9387,0.9270,0.8957,0.8527,0.7746,0.6262,0.4074"); + } + + fall_constraint("SIG2SRAM_constraint_template") { + index_1("0.0080,0.0288,0.0616,0.1072,0.1920,0.3496,0.5952"); + index_2("0.0080,0.0288,0.0616,0.1072,0.1920,0.3496,0.5952"); + values ("0.4152,0.3918,0.3645,0.3215,0.2395,0.1027,-0.1082",\ +"0.4309,0.4113,0.3801,0.3410,0.2590,0.1223,-0.0926",\ +"0.4582,0.4387,0.4074,0.3684,0.2863,0.1496,-0.0613",\ +"0.5012,0.4816,0.4504,0.4074,0.3293,0.1887,-0.0145",\ +"0.5715,0.5559,0.5285,0.4816,0.3996,0.2512,0.0598",\ +"0.7160,0.7004,0.6691,0.6262,0.5520,0.4035,0.2004",\ +"0.9387,0.9191,0.8957,0.8488,0.7707,0.6262,0.4113"); + } + } + } +pin(B_BIST_MEN) { + direction : input ; + capacitance : 0.00300347 ; + max_transition : "0.5952" ; + related_power_pin : VDD; + related_ground_pin : VSS; + internal_power() { + rise_power("scalar"){ + values (0.0161); + } + fall_power("scalar"){ + values (0.0002); + } + } + timing() { + timing_type : setup_rising; + related_pin : "B_BIST_CLK"; + + rise_constraint("SIG2SRAM_constraint_template") { + index_1("0.0080,0.0288,0.0616,0.1072,0.1920,0.3496,0.5952"); + index_2("0.0080,0.0288,0.0616,0.1072,0.1920,0.3496,0.5952"); + values ("0.3215,0.3449,0.3684,0.4113,0.4895,0.6301,0.8527",\ +"0.3059,0.3254,0.3527,0.3957,0.4738,0.6145,0.8371",\ +"0.2746,0.2941,0.3215,0.3645,0.4426,0.5871,0.8059",\ +"0.2316,0.2512,0.2785,0.3215,0.3996,0.5402,0.7629",\ +"0.1496,0.1730,0.1965,0.2395,0.3215,0.4660,0.6848",\ +"0.0090,0.0285,0.0598,0.1027,0.1809,0.3176,0.5402",\ +"-0.2098,-0.1902,-0.1668,-0.1199,-0.0418,0.0988,0.3137"); + } + + fall_constraint("SIG2SRAM_constraint_template") { + index_1("0.0080,0.0288,0.0616,0.1072,0.1920,0.3496,0.5952"); + index_2("0.0080,0.0288,0.0616,0.1072,0.1920,0.3496,0.5952"); + values ("0.4582,0.4738,0.5012,0.5363,0.6145,0.7395,0.9738",\ +"0.4387,0.4543,0.4816,0.5207,0.5910,0.7199,0.9582",\ +"0.4035,0.4230,0.4504,0.4855,0.5637,0.6887,0.9230",\ +"0.3645,0.3840,0.4074,0.4465,0.5285,0.6496,0.8840",\ +"0.2824,0.3020,0.3254,0.3645,0.4465,0.5715,0.7980",\ +"0.1418,0.1613,0.1887,0.2238,0.3020,0.4309,0.6496",\ +"-0.0770,-0.0574,-0.0301,0.0090,0.0910,0.2238,0.4191"); + } + } + + + timing() { + timing_type : hold_rising; + related_pin : "B_BIST_CLK"; + + rise_constraint("SIG2SRAM_constraint_template") { + index_1("0.0080,0.0288,0.0616,0.1072,0.1920,0.3496,0.5952"); + index_2("0.0080,0.0288,0.0616,0.1072,0.1920,0.3496,0.5952"); + values ("0.3762,0.3605,0.3293,0.2863,0.2043,0.0637,-0.1629",\ +"0.3996,0.3801,0.3488,0.3020,0.2238,0.0832,-0.1395",\ +"0.4230,0.4074,0.3723,0.3293,0.2473,0.1105,-0.1121",\ +"0.4621,0.4465,0.4152,0.3762,0.2941,0.1535,-0.0691",\ +"0.5441,0.5285,0.4973,0.4465,0.3684,0.2316,0.0090",\ +"0.6848,0.6652,0.6301,0.5910,0.5129,0.3605,0.1496",\ +"0.9074,0.8918,0.8566,0.8215,0.7395,0.5910,0.3723"); + } + + fall_constraint("SIG2SRAM_constraint_template") { + index_1("0.0080,0.0288,0.0616,0.1072,0.1920,0.3496,0.5952"); + index_2("0.0080,0.0288,0.0616,0.1072,0.1920,0.3496,0.5952"); + values ("0.3762,0.3605,0.3332,0.2863,0.2043,0.0715,-0.1395",\ +"0.3996,0.3762,0.3488,0.3059,0.2238,0.0910,-0.1199",\ +"0.4270,0.4035,0.3762,0.3332,0.2512,0.1184,-0.0965",\ +"0.4699,0.4504,0.4191,0.3762,0.2941,0.1613,-0.0496",\ +"0.5441,0.5285,0.4973,0.4543,0.3762,0.2355,0.0324",\ +"0.6770,0.6613,0.6340,0.5949,0.5207,0.3762,0.1652",\ +"0.9074,0.8918,0.8605,0.8176,0.7395,0.6027,0.3918"); + } + } + } +bus(B_BIST_BM) { + bus_type : D_15_0; + direction : input ; + capacitance : 0.00261869 ; + max_transition : "0.5952" ; + pin(B_BIST_BM[15:0]) { + related_power_pin : VDD; + related_ground_pin : VSS; + internal_power() { + when : "B_BIST_MEN"; + rise_power("scalar"){ + values (0.0469); + } + fall_power("scalar"){ + values (0.0152); + } + } + internal_power() { + when : "!B_BIST_MEN"; + rise_power("scalar"){ + values (0.0453); + } + fall_power("scalar"){ + values (0.0145); + } + } + } + timing() { + timing_type : setup_rising; + related_pin : "B_BIST_CLK"; + when : "(B_BIST_WEN & B_BIST_MEN)" + sdf_cond : "B_BIST_RW_ACCESS" + + rise_constraint("SIG2SRAM_constraint_template") { + index_1("0.0080,0.0288,0.0616,0.1072,0.1920,0.3496,0.5952"); + index_2("0.0080,0.0288,0.0616,0.1072,0.1920,0.3496,0.5952"); + values ("-0.6982,-0.6787,-0.6533,-0.6103,-0.5293,-0.3838,-0.1611",\ +"-0.7057,-0.6861,-0.6608,-0.6178,-0.5367,-0.3912,-0.1686",\ +"-0.7153,-0.6957,-0.6703,-0.6274,-0.5463,-0.4008,-0.1782",\ +"-0.7284,-0.7089,-0.6835,-0.6405,-0.5595,-0.4140,-0.1913",\ +"-0.7527,-0.7331,-0.7077,-0.6648,-0.5837,-0.4382,-0.2156",\ +"-0.7831,-0.7636,-0.7382,-0.6952,-0.6142,-0.4686,-0.2460",\ +"-0.8647,-0.8452,-0.8198,-0.7768,-0.6958,-0.5503,-0.3276"); + } + + fall_constraint("SIG2SRAM_constraint_template") { + index_1("0.0080,0.0288,0.0616,0.1072,0.1920,0.3496,0.5952"); + index_2("0.0080,0.0288,0.0616,0.1072,0.1920,0.3496,0.5952"); + values ("-0.6357,-0.6181,-0.5908,-0.5517,-0.4687,-0.3330,-0.1211",\ +"-0.6432,-0.6256,-0.5983,-0.5592,-0.4762,-0.3404,-0.1285",\ +"-0.6528,-0.6352,-0.6078,-0.5688,-0.4858,-0.3500,-0.1381",\ +"-0.6659,-0.6483,-0.6210,-0.5819,-0.4989,-0.3632,-0.1513",\ +"-0.6902,-0.6726,-0.6452,-0.6062,-0.5232,-0.3874,-0.1755",\ +"-0.7206,-0.7030,-0.6757,-0.6366,-0.5536,-0.4179,-0.2059",\ +"-0.8022,-0.7846,-0.7573,-0.7182,-0.6352,-0.4995,-0.2876"); + } + } + + + timing() { + timing_type : hold_rising; + related_pin : "B_BIST_CLK"; + when : "(B_BIST_WEN & B_BIST_MEN)" + sdf_cond : "B_BIST_RW_ACCESS" + + rise_constraint("SIG2SRAM_constraint_template") { + index_1("0.0080,0.0288,0.0616,0.1072,0.1920,0.3496,0.5952"); + index_2("0.0080,0.0288,0.0616,0.1072,0.1920,0.3496,0.5952"); + values ("0.8138,0.7923,0.7679,0.7250,0.6449,0.4984,0.2757",\ +"0.8213,0.7998,0.7754,0.7324,0.6523,0.5059,0.2832",\ +"0.8309,0.8094,0.7850,0.7420,0.6619,0.5154,0.2928",\ +"0.8440,0.8225,0.7981,0.7552,0.6751,0.5286,0.3059",\ +"0.8683,0.8468,0.8224,0.7794,0.6993,0.5528,0.3302",\ +"0.8987,0.8772,0.8528,0.8098,0.7298,0.5833,0.3606",\ +"0.9803,0.9588,0.9344,0.8915,0.8114,0.6649,0.4422"); + } + + fall_constraint("SIG2SRAM_constraint_template") { + index_1("0.0080,0.0288,0.0616,0.1072,0.1920,0.3496,0.5952"); + index_2("0.0080,0.0288,0.0616,0.1072,0.1920,0.3496,0.5952"); + values ("0.7396,0.7220,0.6947,0.6556,0.5726,0.4359,0.2250",\ +"0.7471,0.7295,0.7022,0.6631,0.5801,0.4434,0.2324",\ +"0.7567,0.7391,0.7117,0.6727,0.5897,0.4529,0.2420",\ +"0.7698,0.7522,0.7249,0.6858,0.6028,0.4661,0.2552",\ +"0.7941,0.7765,0.7491,0.7101,0.6271,0.4904,0.2794",\ +"0.8245,0.8069,0.7796,0.7405,0.6575,0.5208,0.3098",\ +"0.9061,0.8885,0.8612,0.8221,0.7391,0.6024,0.3915"); + } + } +} + pin(B_BIST_CLK) { + direction : input; + capacitance : 0.00378957; + max_transition : "0.5952"; + clock : "true" ; + pin_func_type : active_rising ; + + timing () { + timing_type : "min_pulse_width"; + related_pin : "B_BIST_CLK"; + rise_constraint("CLKTRAN_constraint_template") { + index_1("0.008,0.5952"); + values("0.4,0.4"); + } + } + + related_power_pin : VDD; + related_ground_pin : VSS; + + internal_power() { + when : "!B_BIST_MEN & !B_BIST_WEN & !B_BIST_REN"; + rise_power("scalar"){ + values (0); + } + fall_power("scalar"){ + values (0); + } + } + internal_power() { + when : "!B_BIST_MEN & B_BIST_WEN & !B_BIST_REN"; + rise_power("scalar"){ + values (0.5014); + } + fall_power("scalar"){ + values (0); + } + } + internal_power() { + when : "B_BIST_MEN & B_BIST_WEN & !B_BIST_REN"; + rise_power("scalar"){ + values (19.4302); + } + fall_power("scalar"){ + values (0); + } + } + internal_power() { + when : "B_BIST_MEN & B_BIST_WEN & B_BIST_REN"; + rise_power("scalar"){ + values (20.3865); + } + fall_power("scalar"){ + values (0); + } + } + internal_power() { + when : "B_BIST_MEN & !B_BIST_WEN & B_BIST_REN"; + rise_power("scalar"){ + values (15.8142); + } + fall_power("scalar"){ + values (0); + } + } + internal_power() { + when : "!B_BIST_MEN & !B_BIST_WEN & B_BIST_REN"; + rise_power("scalar"){ + values (0.3165); + } + fall_power("scalar"){ + values (0); + } + } + internal_power() { + when : "!B_BIST_MEN & B_BIST_WEN & B_BIST_REN"; + rise_power("scalar"){ + values (0.6909); + } + fall_power("scalar"){ + values (0); + } + } + internal_power() { + when : "B_BIST_MEN & !B_BIST_WEN & !B_BIST_REN"; + rise_power("scalar"){ + values (0); + } + fall_power("scalar"){ + values (0); + } + } + } + bus(B_BIST_DIN) { + bus_type : D_15_0; + direction : input ; + capacitance : 0.00416317 ; + memory_write() { + address : B_BIST_ADDR ; + clocked_on : B_BIST_CLK; + } + + max_transition : "0.5952" ; + pin(B_BIST_DIN[15:0]) { + related_power_pin : VDD; + related_ground_pin : VSS; + internal_power() { + when : "B_BIST_MEN"; + rise_power("scalar"){ + values (0.0469); + } + fall_power("scalar"){ + values (0.0152); + } + } + internal_power() { + when : "!B_BIST_MEN"; + rise_power("scalar"){ + values (0.0453); + } + fall_power("scalar"){ + values (0.0145); + } + } + } + timing() { + timing_type : setup_rising; + related_pin : "B_BIST_CLK"; + when : "(B_BIST_WEN & B_BIST_MEN)"; + sdf_cond : "B_BIST_W_ACCESS"; + + rise_constraint("SIG2SRAM_constraint_template") { + index_1("0.0080,0.0288,0.0616,0.1072,0.1920,0.3496,0.5952"); + index_2("0.0080,0.0288,0.0616,0.1072,0.1920,0.3496,0.5952"); + values ("-0.6982,-0.6787,-0.6533,-0.6103,-0.5293,-0.3838,-0.1611",\ +"-0.7057,-0.6861,-0.6608,-0.6178,-0.5367,-0.3912,-0.1686",\ +"-0.7153,-0.6957,-0.6703,-0.6274,-0.5463,-0.4008,-0.1782",\ +"-0.7284,-0.7089,-0.6835,-0.6405,-0.5595,-0.4140,-0.1913",\ +"-0.7527,-0.7331,-0.7077,-0.6648,-0.5837,-0.4382,-0.2156",\ +"-0.7831,-0.7636,-0.7382,-0.6952,-0.6142,-0.4686,-0.2460",\ +"-0.8647,-0.8452,-0.8198,-0.7768,-0.6958,-0.5503,-0.3276"); + } + + fall_constraint("SIG2SRAM_constraint_template") { + index_1("0.0080,0.0288,0.0616,0.1072,0.1920,0.3496,0.5952"); + index_2("0.0080,0.0288,0.0616,0.1072,0.1920,0.3496,0.5952"); + values ("-0.6357,-0.6181,-0.5908,-0.5517,-0.4687,-0.3330,-0.1211",\ +"-0.6432,-0.6256,-0.5983,-0.5592,-0.4762,-0.3404,-0.1285",\ +"-0.6528,-0.6352,-0.6078,-0.5688,-0.4858,-0.3500,-0.1381",\ +"-0.6659,-0.6483,-0.6210,-0.5819,-0.4989,-0.3632,-0.1513",\ +"-0.6902,-0.6726,-0.6452,-0.6062,-0.5232,-0.3874,-0.1755",\ +"-0.7206,-0.7030,-0.6757,-0.6366,-0.5536,-0.4179,-0.2059",\ +"-0.8022,-0.7846,-0.7573,-0.7182,-0.6352,-0.4995,-0.2876"); + } + } + + timing() { + timing_type : hold_rising; + related_pin : "B_BIST_CLK"; + when : "(B_BIST_WEN & B_BIST_MEN)"; + sdf_cond : "B_BIST_W_ACCESS"; + + rise_constraint("SIG2SRAM_constraint_template") { + index_1("0.0080,0.0288,0.0616,0.1072,0.1920,0.3496,0.5952"); + index_2("0.0080,0.0288,0.0616,0.1072,0.1920,0.3496,0.5952"); + values ("0.8138,0.7923,0.7679,0.7250,0.6449,0.4984,0.2757",\ +"0.8213,0.7998,0.7754,0.7324,0.6523,0.5059,0.2832",\ +"0.8309,0.8094,0.7850,0.7420,0.6619,0.5154,0.2928",\ +"0.8440,0.8225,0.7981,0.7552,0.6751,0.5286,0.3059",\ +"0.8683,0.8468,0.8224,0.7794,0.6993,0.5528,0.3302",\ +"0.8987,0.8772,0.8528,0.8098,0.7298,0.5833,0.3606",\ +"0.9803,0.9588,0.9344,0.8915,0.8114,0.6649,0.4422"); + } + + fall_constraint("SIG2SRAM_constraint_template") { + index_1("0.0080,0.0288,0.0616,0.1072,0.1920,0.3496,0.5952"); + index_2("0.0080,0.0288,0.0616,0.1072,0.1920,0.3496,0.5952"); + values ("0.7396,0.7220,0.6947,0.6556,0.5726,0.4359,0.2250",\ +"0.7471,0.7295,0.7022,0.6631,0.5801,0.4434,0.2324",\ +"0.7567,0.7391,0.7117,0.6727,0.5897,0.4529,0.2420",\ +"0.7698,0.7522,0.7249,0.6858,0.6028,0.4661,0.2552",\ +"0.7941,0.7765,0.7491,0.7101,0.6271,0.4904,0.2794",\ +"0.8245,0.8069,0.7796,0.7405,0.6575,0.5208,0.3098",\ +"0.9061,0.8885,0.8612,0.8221,0.7391,0.6024,0.3915"); + } + } + } + +bus(B_DOUT) { + + bus_type : D_15_0; + direction : output ; + capacitance : 0 ; + max_capacitance : 0.064 ; + memory_read() { + address : B_ADDR ; + } + pin(B_DOUT[15:0]) { + related_power_pin : VDD; + related_ground_pin : VSS; + internal_power() { + rise_power("scalar") { + values (0); + } + fall_power("scalar") { + values (0); + } + } + } + timing() { + related_pin : "B_CLK"; + timing_type : rising_edge ; + timing_sense : non_unate ; + + cell_rise(SIG2SRAM_delay_template) { + index_1("0.0080,0.0288,0.0616,0.1072,0.1920,0.3496,0.5952"); + index_2("0.0008,0.0014,0.0051,0.0100,0.0339,0.0640"); + values ("6.3579,6.3612,6.3734,6.3874,6.4399,6.4978",\ +"6.3622,6.3656,6.3778,6.3917,6.4443,6.5021",\ +"6.3727,6.3760,6.3882,6.4022,6.4547,6.5126",\ +"6.3933,6.3967,6.4089,6.4228,6.4754,6.5332",\ +"6.4076,6.4109,6.4231,6.4371,6.4896,6.5475",\ +"6.4410,6.4444,6.4566,6.4705,6.5231,6.5809",\ +"6.5267,6.5301,6.5423,6.5562,6.6088,6.6666"); + } + cell_fall(SIG2SRAM_delay_template) { + index_1("0.0080,0.0288,0.0616,0.1072,0.1920,0.3496,0.5952"); + index_2("0.0008,0.0014,0.0051,0.0100,0.0339,0.0640"); + values ("6.2481,6.2503,6.2604,6.2720,6.3154,6.3592",\ +"6.2525,6.2547,6.2647,6.2764,6.3197,6.3636",\ +"6.2629,6.2651,6.2752,6.2868,6.3302,6.3740",\ +"6.2836,6.2858,6.2958,6.3075,6.3508,6.3947",\ +"6.2979,6.3000,6.3101,6.3218,6.3651,6.4089",\ +"6.3313,6.3335,6.3435,6.3552,6.3985,6.4424",\ +"6.4170,6.4192,6.4292,6.4409,6.4842,6.5281"); + } + + rise_transition(SRAM_load_template) { + index_1("0.0008,0.0014,0.0051,0.0100,0.0339,0.0640"); + values ("0.0560,0.0583,0.0696,0.0816,0.1519,0.2335"); + } + fall_transition(SRAM_load_template) { + index_1("0.0008,0.0014,0.0051,0.0100,0.0339,0.0640"); + values ("0.0428,0.0445,0.0538,0.0658,0.1181,0.1751"); + } + } +} +cell_leakage_power : 953.1571; +} +} diff --git a/flow/platforms/ihp-sg13g2/lib/RM_IHPSG13_2P_512x16_c2_bm_bist_typ_1p20V_25C.lib b/flow/platforms/ihp-sg13g2/lib/RM_IHPSG13_2P_512x16_c2_bm_bist_typ_1p20V_25C.lib new file mode 100644 index 0000000000..a478be7609 --- /dev/null +++ b/flow/platforms/ihp-sg13g2/lib/RM_IHPSG13_2P_512x16_c2_bm_bist_typ_1p20V_25C.lib @@ -0,0 +1,2886 @@ +/* ------------------------------------------------------*/ +/**/ +/* Copyright 2025 IHP PDK Authors*/ +/**/ +/* Licensed under the Apache License, Version 2.0 (the "License");*/ +/* you may not use this file except in compliance with the License.*/ +/* You may obtain a copy of the License at*/ +/* */ +/* https://www.apache.org/licenses/LICENSE-2.0*/ +/* */ +/* Unless required by applicable law or agreed to in writing, software*/ +/* distributed under the License is distributed on an "AS IS" BASIS,*/ +/* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.*/ +/* See the License for the specific language governing permissions and*/ +/* limitations under the License.*/ +/* */ +/* Generated on Wed Aug 27 13:18:10 2025 */ +/* */ +/* ------------------------------------------------------ */ +library(RM_IHPSG13_2P_512x16_c2_bm_bist_typ_1p20V_25C) { + technology (cmos) ; + delay_model : table_lookup ; + define ("add_pg_pin_to_lib", "library", "boolean"); + add_pg_pin_to_lib : true; + voltage_map ( VDD, 1.20); + voltage_map ( VDDARRAY, 1.20); + voltage_map ( VSS, 0.000000 ); + + date : "Wed Aug 27 13:18:07 2025" ; + comment : "IHP Microelectronics GmbH, 2023" ; + revision : 1.0.0 ; + simulation : true ; + nom_process : 1 ; + nom_temperature : 25 ; + nom_voltage : 1.20 ; + + operating_conditions("typ_1p20V_25C"){ + process : 1 ; + temperature : 25 ; + voltage : 1.20 ; + tree_type : "balanced_tree" ; + } + + default_operating_conditions : typ_1p20V_25C ; + default_max_transition : 1.0 ; + default_fanout_load : 1.0 ; + default_inout_pin_cap : 0.0 ; + default_input_pin_cap : 0.0 ; + default_output_pin_cap : 0.0 ; + default_cell_leakage_power : 0.0 ; + default_leakage_power_density : 0.0 ; + + slew_lower_threshold_pct_rise : 30 ; + slew_upper_threshold_pct_rise : 70 ; + input_threshold_pct_fall : 50 ; + output_threshold_pct_fall : 50 ; + input_threshold_pct_rise : 50 ; + output_threshold_pct_rise : 50 ; + slew_lower_threshold_pct_fall : 30 ; + slew_upper_threshold_pct_fall : 70 ; + slew_derate_from_library : 0.5; + k_volt_cell_leakage_power : 0.0 ; + k_temp_cell_leakage_power : 0.0 ; + k_process_cell_leakage_power : 0.0 ; + k_volt_internal_power : 0.0 ; + k_temp_internal_power : 0.0 ; + k_process_internal_power : 0.0 ; + + capacitive_load_unit (1,pf) ; + voltage_unit : "1V" ; + current_unit : "1uA" ; + time_unit : "1ns" ; + leakage_power_unit : "1nW" ; + pulling_resistance_unit : "1kohm"; + /* + ------------------------------------------------------------------------------------------ + implicit units overview: + cell_area unit : "um" + internal_power unit : "1e-12 * J/toggle = 1 * uW/MHz" + (capacitive_load_unit * voltage_unit^2) per toggle event + ------------------------------------------------------------------------------------------ + */ + library_features(report_delay_calculation); + define_cell_area (pad_drivers,pad_driver_sites) ; + + lu_table_template(CLKTRAN_constraint_template) { + variable_1 : constrained_pin_transition; + index_1 ( "0.010, 0.050, 0.200, 0.400, 1.000" ); + } + lu_table_template(SRAM_load_template) { + variable_1 : total_output_net_capacitance; + index_1 ( "0.0008,0.0014,0.0051,0.0100,0.0339,0.0640" ); + } + lu_table_template(SIG2SRAM_constraint_template) { + variable_1 : related_pin_transition; + variable_2 : constrained_pin_transition; + index_1 ( "0.0056,0.0232,0.0400,0.0728,0.1280,0.2440,0.4760" ); + index_2 ( "0.0056,0.0232,0.0400,0.0728,0.1280,0.2440,0.4760" ); + } + + lu_table_template(SIG2SRAM_delay_template) { + variable_1 : input_net_transition; + variable_2 : total_output_net_capacitance; + index_1 ( "0.0056,0.0232,0.0400,0.0728,0.1280,0.2440,0.4760" ); + index_2 ( "0.0008,0.0014,0.0051,0.0100,0.0339,0.0640" ); + } + + type (D_15_0) { + base_type : array; + data_type : bit; + bit_width : 16; + bit_from : 15; + bit_to : 0; + downto : true; + } + + type (A_8_0) { + base_type : array; + data_type : bit; + bit_width : 9; + bit_from : 8; + bit_to : 0; + downto : true; + } + +cell(RM_IHPSG13_2P_512x16_c2_bm_bist) { +pg_pin (VDD) { + pg_type : primary_power; + voltage_name : VDD; +} +pg_pin (VDDARRAY) { + pg_type : primary_power; + voltage_name : VDDARRAY; +} +pg_pin (VSS) { + pg_type : primary_ground; + voltage_name : VSS; +} + +memory() { + type : ram; + address_width : 9; + word_width : 16; +} + +interface_timing : false; +bus_naming_style : "%s[%d]" ; +area : 88481.5997 ; + + pin(A_DLY) { + direction : input ; + capacitance : 0.00401111 ; + max_transition : "1" ; + related_power_pin : VDD; + related_ground_pin : VSS; + internal_power() { + rise_power("scalar") { + values (0); + } + fall_power("scalar") { + values (0); + } + } + } + +bus(A_ADDR) { + bus_type : A_8_0; + direction : input ; + capacitance : 0.0121077 ; + pin(A_ADDR[0]) { + capacitance : 0.00568653 ; + } + pin(A_ADDR[1]) { + capacitance : 0.00767263 ; + } + pin(A_ADDR[2]) { + capacitance : 0.0105079 ; + } + pin(A_ADDR[3]) { + capacitance : 0.0068178 ; + } + pin(A_ADDR[4]) { + capacitance : 0.00624497 ; + } + pin(A_ADDR[5]) { + capacitance : 0.0105871 ; + } + pin(A_ADDR[6]) { + capacitance : 0.0130817 ; + } + pin(A_ADDR[7]) { + capacitance : 0.0104931 ; + } + max_transition : "0.476" ; + pin(A_ADDR[8:0]) { + related_power_pin : VDD; + related_ground_pin : VSS; + internal_power() { + when : "A_MEN"; + rise_power("scalar"){ + values (0.0110); + } + fall_power("scalar"){ + values (0.0056); + } + } + internal_power() { + when : "!A_MEN"; + rise_power("scalar"){ + values (0.0168); + } + fall_power("scalar"){ + values (0.0004); + } + } + } + timing() { + timing_type : setup_rising; + related_pin : "A_CLK"; + when : "((A_WEN | A_REN)& A_MEN)" + sdf_cond : "A_RW_ACCESS" + + rise_constraint("SIG2SRAM_constraint_template") { + index_1("0.0056,0.0232,0.0400,0.0728,0.1280,0.2440,0.4760"); + index_2("0.0056,0.0232,0.0400,0.0728,0.1280,0.2440,0.4760"); + values ("-0.4168,-0.3973,-0.3855,-0.3543,-0.3074,-0.2020,-0.0027",\ +"-0.4324,-0.4129,-0.4012,-0.3699,-0.3191,-0.2176,-0.0184",\ +"-0.4441,-0.4285,-0.4129,-0.3816,-0.3309,-0.2293,-0.0301",\ +"-0.4793,-0.4598,-0.4441,-0.4129,-0.3660,-0.2645,-0.0652",\ +"-0.5223,-0.5066,-0.4910,-0.4598,-0.4129,-0.3074,-0.1121",\ +"-0.6199,-0.6082,-0.5926,-0.5613,-0.5145,-0.4129,-0.2137",\ +"-0.8191,-0.8074,-0.7840,-0.7566,-0.7098,-0.6082,-0.4051"); + } + + fall_constraint("SIG2SRAM_constraint_template") { + index_1("0.0056,0.0232,0.0400,0.0728,0.1280,0.2440,0.4760"); + index_2("0.0056,0.0232,0.0400,0.0728,0.1280,0.2440,0.4760"); + values ("-0.3309,-0.3113,-0.2996,-0.2684,-0.2176,-0.1238,0.0637",\ +"-0.3465,-0.3309,-0.3152,-0.2840,-0.2332,-0.1395,0.0480",\ +"-0.3582,-0.3426,-0.3270,-0.2996,-0.2488,-0.1512,0.0324",\ +"-0.3895,-0.3738,-0.3582,-0.3309,-0.2801,-0.1863,0.0051",\ +"-0.4363,-0.4207,-0.4051,-0.3777,-0.3230,-0.2293,-0.0379",\ +"-0.5379,-0.5223,-0.5066,-0.4793,-0.4285,-0.3309,-0.1434",\ +"-0.7332,-0.7176,-0.7020,-0.6746,-0.6238,-0.5262,-0.3387"); + } + } + + + timing() { + timing_type : hold_rising; + related_pin : "A_CLK"; + when : "((A_WEN | A_REN)& A_MEN)" + sdf_cond : "A_RW_ACCESS" + + rise_constraint("SIG2SRAM_constraint_template") { + index_1("0.0056,0.0232,0.0400,0.0728,0.1280,0.2440,0.4760"); + index_2("0.0056,0.0232,0.0400,0.0728,0.1280,0.2440,0.4760"); + values ("0.5246,0.5051,0.4895,0.4582,0.4113,0.3059,0.1066",\ +"0.5402,0.5207,0.5051,0.4777,0.4270,0.3215,0.1223",\ +"0.5520,0.5324,0.5168,0.4895,0.4387,0.3371,0.1340",\ +"0.5832,0.5676,0.5520,0.5207,0.4738,0.3684,0.1691",\ +"0.6301,0.6105,0.5949,0.5676,0.5168,0.4113,0.2160",\ +"0.7316,0.7121,0.7004,0.6691,0.6223,0.5168,0.3176",\ +"0.9270,0.9230,0.8957,0.8645,0.8137,0.7121,0.5168"); + } + + fall_constraint("SIG2SRAM_constraint_template") { + index_1("0.0056,0.0232,0.0400,0.0728,0.1280,0.2440,0.4760"); + index_2("0.0056,0.0232,0.0400,0.0728,0.1280,0.2440,0.4760"); + values ("0.4309,0.4152,0.4035,0.3684,0.3215,0.2277,0.0363",\ +"0.4465,0.4309,0.4152,0.3879,0.3371,0.2395,0.0559",\ +"0.4582,0.4426,0.4309,0.3996,0.3488,0.2551,0.0715",\ +"0.4934,0.4777,0.4621,0.4348,0.3840,0.2863,0.0988",\ +"0.5363,0.5207,0.5051,0.4777,0.4270,0.3332,0.1418",\ +"0.6379,0.6262,0.6105,0.5793,0.5324,0.4348,0.2434",\ +"0.8332,0.8215,0.8059,0.7707,0.7238,0.6301,0.4387"); + } + } +} +pin(A_WEN) { + direction : input ; + capacitance : 0.00324098 ; + max_transition : "0.476" ; + related_power_pin : VDD; + related_ground_pin : VSS; + internal_power() { + when : "A_MEN"; + rise_power("scalar"){ + values (0.0046); + } + fall_power("scalar"){ + values (0.0039); + } + } + internal_power() { + when : "!A_MEN"; + rise_power("scalar"){ + values (0.0043); + } + fall_power("scalar"){ + values (0.0040); + } + } + timing() { + timing_type : setup_rising; + related_pin : "A_CLK"; + when : "A_MEN" + sdf_cond : "A_MEN" + + rise_constraint("SIG2SRAM_constraint_template") { + index_1("0.0056,0.0232,0.0400,0.0728,0.1280,0.2440,0.4760"); + index_2("0.0056,0.0232,0.0400,0.0728,0.1280,0.2440,0.4760"); + values ("0.2043,0.2199,0.2316,0.2629,0.3059,0.4113,0.6066",\ +"0.1887,0.2043,0.2160,0.2473,0.2941,0.3957,0.5949",\ +"0.1691,0.1848,0.2004,0.2316,0.2785,0.3801,0.5754",\ +"0.1379,0.1574,0.1691,0.2004,0.2473,0.3527,0.5480",\ +"0.0910,0.1066,0.1223,0.1535,0.2004,0.2980,0.4973",\ +"-0.0105,0.0051,0.0207,0.0520,0.0949,0.2004,0.3957",\ +"-0.2059,-0.1902,-0.1746,-0.1473,-0.1004,0.0051,0.2004"); + } + + fall_constraint("SIG2SRAM_constraint_template") { + index_1("0.0056,0.0232,0.0400,0.0728,0.1280,0.2440,0.4760"); + index_2("0.0056,0.0232,0.0400,0.0728,0.1280,0.2440,0.4760"); + values ("0.2941,0.3098,0.3215,0.3488,0.4035,0.4973,0.6887",\ +"0.2785,0.2941,0.3059,0.3332,0.3840,0.4816,0.6691",\ +"0.2629,0.2785,0.2902,0.3176,0.3684,0.4660,0.6535",\ +"0.2316,0.2473,0.2590,0.2863,0.3410,0.4348,0.6262",\ +"0.1848,0.2004,0.2121,0.2395,0.2902,0.3879,0.5754",\ +"0.0832,0.0988,0.1105,0.1379,0.1809,0.2746,0.4699",\ +"-0.1121,-0.0965,-0.0848,-0.0535,-0.0066,0.0910,0.2824"); + } + } + + + timing() { + timing_type : hold_rising; + related_pin : "A_CLK"; + when : "A_MEN" + sdf_cond : "A_MEN" + + rise_constraint("SIG2SRAM_constraint_template") { + index_1("0.0056,0.0232,0.0400,0.0728,0.1280,0.2440,0.4760"); + index_2("0.0056,0.0232,0.0400,0.0728,0.1280,0.2440,0.4760"); + values ("0.2473,0.2316,0.2160,0.1887,0.1379,0.0363,-0.1629",\ +"0.2629,0.2473,0.2316,0.2043,0.1535,0.0520,-0.1473",\ +"0.2785,0.2590,0.2434,0.2160,0.1652,0.0676,-0.1355",\ +"0.3098,0.2941,0.2785,0.2473,0.1965,0.0910,-0.1043",\ +"0.3527,0.3371,0.3215,0.2941,0.2434,0.1418,-0.0574",\ +"0.4582,0.4426,0.4270,0.3957,0.3488,0.2434,0.0480",\ +"0.6535,0.6379,0.6184,0.5910,0.5402,0.4426,0.2434"); + } + + fall_constraint("SIG2SRAM_constraint_template") { + index_1("0.0056,0.0232,0.0400,0.0728,0.1280,0.2440,0.4760"); + index_2("0.0056,0.0232,0.0400,0.0728,0.1280,0.2440,0.4760"); + values ("0.2395,0.2238,0.2121,0.1809,0.1301,0.0324,-0.1551",\ +"0.2551,0.2395,0.2277,0.1965,0.1457,0.0480,-0.1395",\ +"0.2668,0.2551,0.2395,0.2082,0.1574,0.0637,-0.1277",\ +"0.3020,0.2863,0.2707,0.2395,0.1887,0.0910,-0.0965",\ +"0.3449,0.3293,0.3176,0.2863,0.2355,0.1379,-0.0496",\ +"0.4504,0.4348,0.4191,0.3879,0.3371,0.2395,0.0559",\ +"0.6457,0.6301,0.6145,0.5871,0.5324,0.4309,0.2512"); + } + } + } +pin(A_REN) { + direction : input ; + capacitance : 0.00381634 ; + max_transition : "0.476" ; + related_power_pin : VDD; + related_ground_pin : VSS; + internal_power() { + when : "A_MEN"; + rise_power("scalar"){ + values (0.0061); + } + fall_power("scalar"){ + values (0.0021); + } + } + internal_power() { + when : "!A_MEN"; + rise_power("scalar"){ + values (0.0062); + } + fall_power("scalar"){ + values (0.0025); + } + } + timing() { + timing_type : setup_rising; + related_pin : "A_CLK"; + when : "A_MEN" + sdf_cond : "A_MEN" + + rise_constraint("SIG2SRAM_constraint_template") { + index_1("0.0056,0.0232,0.0400,0.0728,0.1280,0.2440,0.4760"); + index_2("0.0056,0.0232,0.0400,0.0728,0.1280,0.2440,0.4760"); + values ("-0.0301,-0.0145,0.0012,0.0324,0.0793,0.1809,0.3762",\ +"-0.0457,-0.0301,-0.0145,0.0168,0.0637,0.1613,0.3605",\ +"-0.0574,-0.0418,-0.0262,0.0051,0.0520,0.1496,0.3449",\ +"-0.0926,-0.0730,-0.0574,-0.0262,0.0207,0.1184,0.3137",\ +"-0.1395,-0.1238,-0.1082,-0.0770,-0.0301,0.0715,0.2707",\ +"-0.2410,-0.2254,-0.2098,-0.1746,-0.1355,-0.0340,0.1652",\ +"-0.4402,-0.4207,-0.4051,-0.3738,-0.3270,-0.2293,-0.0340"); + } + + fall_constraint("SIG2SRAM_constraint_template") { + index_1("0.0056,0.0232,0.0400,0.0728,0.1280,0.2440,0.4760"); + index_2("0.0056,0.0232,0.0400,0.0728,0.1280,0.2440,0.4760"); + values ("0.0988,0.1145,0.1262,0.1535,0.2043,0.3020,0.4855",\ +"0.0832,0.0988,0.1105,0.1418,0.1848,0.2824,0.4738",\ +"0.0676,0.0832,0.0949,0.1262,0.1730,0.2668,0.4621",\ +"0.0402,0.0559,0.0676,0.0988,0.1457,0.2434,0.4191",\ +"-0.0105,0.0012,0.0168,0.0480,0.0988,0.1965,0.3840",\ +"-0.1160,-0.0965,-0.0848,-0.0535,-0.0066,0.0988,0.2824",\ +"-0.3113,-0.2957,-0.2801,-0.2527,-0.2059,-0.1043,0.0832"); + } + } + + + timing() { + timing_type : hold_rising; + related_pin : "A_CLK"; + when : "A_MEN" + sdf_cond : "A_MEN" + + rise_constraint("SIG2SRAM_constraint_template") { + index_1("0.0056,0.0232,0.0400,0.0728,0.1280,0.2440,0.4760"); + index_2("0.0056,0.0232,0.0400,0.0728,0.1280,0.2440,0.4760"); + values ("0.2707,0.2551,0.2395,0.2121,0.1613,0.0598,-0.1395",\ +"0.2863,0.2707,0.2551,0.2238,0.1730,0.0715,-0.1238",\ +"0.2980,0.2824,0.2668,0.2395,0.1887,0.0871,-0.1121",\ +"0.3332,0.3176,0.3020,0.2707,0.2199,0.1184,-0.0809",\ +"0.3762,0.3605,0.3449,0.3176,0.2668,0.1613,-0.0340",\ +"0.4816,0.4621,0.4504,0.4191,0.3723,0.2629,0.0715",\ +"0.6770,0.6613,0.6418,0.6184,0.5637,0.4699,0.2629"); + } + + fall_constraint("SIG2SRAM_constraint_template") { + index_1("0.0056,0.0232,0.0400,0.0728,0.1280,0.2440,0.4760"); + index_2("0.0056,0.0232,0.0400,0.0728,0.1280,0.2440,0.4760"); + values ("0.2590,0.2434,0.2316,0.2004,0.1457,0.0520,-0.1355",\ +"0.2746,0.2590,0.2434,0.2160,0.1613,0.0676,-0.1199",\ +"0.2863,0.2707,0.2590,0.2277,0.1730,0.0832,-0.1082",\ +"0.3215,0.3059,0.2902,0.2590,0.2082,0.1105,-0.0770",\ +"0.3645,0.3488,0.3332,0.3059,0.2551,0.1535,-0.0340",\ +"0.4699,0.4543,0.4387,0.4074,0.3605,0.2551,0.0715",\ +"0.6652,0.6496,0.6340,0.6027,0.5520,0.4621,0.2707"); + } + } + } +pin(A_MEN) { + direction : input ; + capacitance : 0.00309605 ; + max_transition : "0.476" ; + related_power_pin : VDD; + related_ground_pin : VSS; + internal_power() { + rise_power("scalar"){ + values (0.0449); + } + fall_power("scalar"){ + values (0.0052); + } + } + timing() { + timing_type : setup_rising; + related_pin : "A_CLK"; + + rise_constraint("SIG2SRAM_constraint_template") { + index_1("0.0056,0.0232,0.0400,0.0728,0.1280,0.2440,0.4760"); + index_2("0.0056,0.0232,0.0400,0.0728,0.1280,0.2440,0.4760"); + values ("0.2043,0.2199,0.2316,0.2668,0.3098,0.4152,0.6066",\ +"0.1887,0.2043,0.2199,0.2512,0.2941,0.3996,0.5949",\ +"0.1730,0.1887,0.2043,0.2355,0.2824,0.3840,0.5793",\ +"0.1418,0.1574,0.1730,0.2043,0.2512,0.3566,0.5480",\ +"0.0949,0.1105,0.1262,0.1574,0.2043,0.3020,0.5051",\ +"-0.0066,0.0090,0.0246,0.0520,0.0988,0.2043,0.3996",\ +"-0.2020,-0.1863,-0.1746,-0.1434,-0.0965,0.0090,0.2082"); + } + + fall_constraint("SIG2SRAM_constraint_template") { + index_1("0.0056,0.0232,0.0400,0.0728,0.1280,0.2440,0.4760"); + index_2("0.0056,0.0232,0.0400,0.0728,0.1280,0.2440,0.4760"); + values ("0.2980,0.3137,0.3254,0.3527,0.4035,0.5012,0.6887",\ +"0.2824,0.2980,0.3098,0.3371,0.3879,0.4855,0.6730",\ +"0.2668,0.2824,0.2941,0.3215,0.3723,0.4699,0.6574",\ +"0.2355,0.2473,0.2629,0.2902,0.3410,0.4387,0.6262",\ +"0.1887,0.2004,0.2160,0.2395,0.2941,0.3918,0.5793",\ +"0.0871,0.1027,0.1145,0.1418,0.1848,0.2746,0.4816",\ +"-0.1082,-0.0965,-0.0809,-0.0496,-0.0027,0.0949,0.2863"); + } + } + + + timing() { + timing_type : hold_rising; + related_pin : "A_CLK"; + + rise_constraint("SIG2SRAM_constraint_template") { + index_1("0.0056,0.0232,0.0400,0.0728,0.1280,0.2440,0.4760"); + index_2("0.0056,0.0232,0.0400,0.0728,0.1280,0.2440,0.4760"); + values ("0.2512,0.2355,0.2199,0.1926,0.1418,0.0402,-0.1590",\ +"0.2668,0.2512,0.2355,0.2082,0.1574,0.0559,-0.1434",\ +"0.2824,0.2629,0.2512,0.2199,0.1691,0.0715,-0.1316",\ +"0.3137,0.2980,0.2824,0.2512,0.2004,0.0988,-0.0965",\ +"0.3566,0.3410,0.3254,0.2980,0.2473,0.1418,-0.0535",\ +"0.4621,0.4426,0.4309,0.3996,0.3527,0.2473,0.0520",\ +"0.6574,0.6418,0.6262,0.5949,0.5441,0.4465,0.2473"); + } + + fall_constraint("SIG2SRAM_constraint_template") { + index_1("0.0056,0.0232,0.0400,0.0728,0.1280,0.2440,0.4760"); + index_2("0.0056,0.0232,0.0400,0.0728,0.1280,0.2440,0.4760"); + values ("0.2395,0.2238,0.2121,0.1809,0.1301,0.0324,-0.1551",\ +"0.2551,0.2434,0.2277,0.1965,0.1457,0.0480,-0.1395",\ +"0.2707,0.2551,0.2395,0.2082,0.1574,0.0637,-0.1277",\ +"0.3020,0.2863,0.2707,0.2434,0.1926,0.0910,-0.0965",\ +"0.3449,0.3332,0.3176,0.2863,0.2355,0.1379,-0.0496",\ +"0.4504,0.4348,0.4230,0.3918,0.3410,0.2434,0.0559",\ +"0.6457,0.6301,0.6145,0.5910,0.5324,0.4387,0.2512"); + } + } + } +bus(A_BM) { + bus_type : D_15_0; + direction : input ; + capacitance : 0.00372627 ; + max_transition : "0.476" ; + pin(A_BM[15:0]) { + related_power_pin : VDD; + related_ground_pin : VSS; + internal_power() { + when : "A_MEN"; + rise_power("scalar"){ + values (0.0570); + } + fall_power("scalar"){ + values (0.0255); + } + } + internal_power() { + when : "!A_MEN"; + rise_power("scalar"){ + values (0.0603); + } + fall_power("scalar"){ + values (0.0244); + } + } + } + timing() { + timing_type : setup_rising; + related_pin : "A_CLK"; + when : "(A_WEN & A_MEN)" + sdf_cond : "A_RW_ACCESS" + + rise_constraint("SIG2SRAM_constraint_template") { + index_1("0.0056,0.0232,0.0400,0.0728,0.1280,0.2440,0.4760"); + index_2("0.0056,0.0232,0.0400,0.0728,0.1280,0.2440,0.4760"); + values ("-0.3858,-0.3702,-0.3565,-0.3243,-0.2774,-0.1729,0.0185",\ +"-0.3908,-0.3752,-0.3615,-0.3293,-0.2824,-0.1779,0.0135",\ +"-0.3953,-0.3796,-0.3660,-0.3337,-0.2869,-0.1824,0.0090",\ +"-0.4044,-0.3887,-0.3751,-0.3428,-0.2960,-0.1915,-0.0001",\ +"-0.4116,-0.3960,-0.3823,-0.3501,-0.3032,-0.1987,-0.0073",\ +"-0.4417,-0.4261,-0.4124,-0.3802,-0.3333,-0.2288,-0.0374",\ +"-0.4993,-0.4837,-0.4700,-0.4378,-0.3909,-0.2864,-0.0950"); + } + + fall_constraint("SIG2SRAM_constraint_template") { + index_1("0.0056,0.0232,0.0400,0.0728,0.1280,0.2440,0.4760"); + index_2("0.0056,0.0232,0.0400,0.0728,0.1280,0.2440,0.4760"); + values ("-0.3477,-0.3330,-0.3194,-0.2910,-0.2403,-0.1426,0.0400",\ +"-0.3527,-0.3380,-0.3244,-0.2961,-0.2453,-0.1476,0.0350",\ +"-0.3572,-0.3425,-0.3288,-0.3005,-0.2497,-0.1521,0.0305",\ +"-0.3663,-0.3516,-0.3379,-0.3096,-0.2588,-0.1612,0.0214",\ +"-0.3735,-0.3589,-0.3452,-0.3169,-0.2661,-0.1685,0.0142",\ +"-0.4036,-0.3890,-0.3753,-0.3470,-0.2962,-0.1985,-0.0159",\ +"-0.4612,-0.4466,-0.4329,-0.4046,-0.3538,-0.2561,-0.0735"); + } + } + + + timing() { + timing_type : hold_rising; + related_pin : "A_CLK"; + when : "(A_WEN & A_MEN)" + sdf_cond : "A_RW_ACCESS" + + rise_constraint("SIG2SRAM_constraint_template") { + index_1("0.0056,0.0232,0.0400,0.0728,0.1280,0.2440,0.4760"); + index_2("0.0056,0.0232,0.0400,0.0728,0.1280,0.2440,0.4760"); + values ("0.4953,0.4787,0.4660,0.4337,0.3859,0.2824,0.0900",\ +"0.5003,0.4837,0.4710,0.4387,0.3909,0.2874,0.0950",\ +"0.5048,0.4881,0.4755,0.4432,0.3954,0.2919,0.0995",\ +"0.5139,0.4972,0.4846,0.4523,0.4045,0.3010,0.1086",\ +"0.5211,0.5045,0.4918,0.4596,0.4117,0.3082,0.1158",\ +"0.5512,0.5346,0.5219,0.4897,0.4418,0.3383,0.1459",\ +"0.6088,0.5922,0.5795,0.5473,0.4994,0.3959,0.2035"); + } + + fall_constraint("SIG2SRAM_constraint_template") { + index_1("0.0056,0.0232,0.0400,0.0728,0.1280,0.2440,0.4760"); + index_2("0.0056,0.0232,0.0400,0.0728,0.1280,0.2440,0.4760"); + values ("0.4494,0.4347,0.4210,0.3927,0.3429,0.2502,0.0656",\ +"0.4544,0.4397,0.4261,0.3977,0.3479,0.2552,0.0706",\ +"0.4589,0.4442,0.4305,0.4022,0.3524,0.2596,0.0751",\ +"0.4679,0.4533,0.4396,0.4113,0.3615,0.2687,0.0842",\ +"0.4752,0.4606,0.4469,0.4186,0.3688,0.2760,0.0914",\ +"0.5053,0.4906,0.4770,0.4487,0.3989,0.3061,0.1215",\ +"0.5629,0.5483,0.5346,0.5063,0.4565,0.3637,0.1791"); + } + } +} + pin(A_CLK) { + direction : input; + capacitance : 0.00380014; + max_transition : "0.476"; + clock : "true" ; + pin_func_type : active_rising ; + + timing () { + timing_type : "min_pulse_width"; + related_pin : "A_CLK"; + rise_constraint("CLKTRAN_constraint_template") { + index_1("0.0056,0.476"); + values("0.21,0.21"); + } + } + + related_power_pin : VDD; + related_ground_pin : VSS; + + internal_power() { + when : "!A_MEN & !A_WEN & !A_REN"; + rise_power("scalar"){ + values (0); + } + fall_power("scalar"){ + values (0); + } + } + internal_power() { + when : "!A_MEN & A_WEN & !A_REN"; + rise_power("scalar"){ + values (0.5315); + } + fall_power("scalar"){ + values (0); + } + } + internal_power() { + when : "A_MEN & A_WEN & !A_REN"; + rise_power("scalar"){ + values (23.4667); + } + fall_power("scalar"){ + values (0); + } + } + internal_power() { + when : "A_MEN & A_WEN & A_REN"; + rise_power("scalar"){ + values (25.7036); + } + fall_power("scalar"){ + values (0); + } + } + internal_power() { + when : "A_MEN & !A_WEN & A_REN"; + rise_power("scalar"){ + values (19.5664); + } + fall_power("scalar"){ + values (0); + } + } + internal_power() { + when : "!A_MEN & !A_WEN & A_REN"; + rise_power("scalar"){ + values (0.3077); + } + fall_power("scalar"){ + values (0); + } + } + internal_power() { + when : "!A_MEN & A_WEN & A_REN"; + rise_power("scalar"){ + values (0.7640); + } + fall_power("scalar"){ + values (0); + } + } + internal_power() { + when : "A_MEN & !A_WEN & !A_REN"; + rise_power("scalar"){ + values (0); + } + fall_power("scalar"){ + values (0); + } + } + } + bus(A_DIN) { + bus_type : D_15_0; + direction : input ; + capacitance : 0.00500744 ; + memory_write() { + address : A_ADDR ; + clocked_on : A_CLK; + } + + max_transition : "0.476" ; + pin(A_DIN[15:0]) { + related_power_pin : VDD; + related_ground_pin : VSS; + internal_power() { + when : "A_MEN"; + rise_power("scalar"){ + values (0.0570); + } + fall_power("scalar"){ + values (0.0255); + } + } + internal_power() { + when : "!A_MEN"; + rise_power("scalar"){ + values (0.0603); + } + fall_power("scalar"){ + values (0.0244); + } + } + } + timing() { + timing_type : setup_rising; + related_pin : "A_CLK"; + when : "(A_WEN & A_MEN)"; + sdf_cond : "A_W_ACCESS"; + + rise_constraint("SIG2SRAM_constraint_template") { + index_1("0.0056,0.0232,0.0400,0.0728,0.1280,0.2440,0.4760"); + index_2("0.0056,0.0232,0.0400,0.0728,0.1280,0.2440,0.4760"); + values ("-0.3858,-0.3702,-0.3565,-0.3243,-0.2774,-0.1729,0.0185",\ +"-0.3908,-0.3752,-0.3615,-0.3293,-0.2824,-0.1779,0.0135",\ +"-0.3953,-0.3796,-0.3660,-0.3337,-0.2869,-0.1824,0.0090",\ +"-0.4044,-0.3887,-0.3751,-0.3428,-0.2960,-0.1915,-0.0001",\ +"-0.4116,-0.3960,-0.3823,-0.3501,-0.3032,-0.1987,-0.0073",\ +"-0.4417,-0.4261,-0.4124,-0.3802,-0.3333,-0.2288,-0.0374",\ +"-0.4993,-0.4837,-0.4700,-0.4378,-0.3909,-0.2864,-0.0950"); + } + + fall_constraint("SIG2SRAM_constraint_template") { + index_1("0.0056,0.0232,0.0400,0.0728,0.1280,0.2440,0.4760"); + index_2("0.0056,0.0232,0.0400,0.0728,0.1280,0.2440,0.4760"); + values ("-0.3477,-0.3330,-0.3194,-0.2910,-0.2403,-0.1426,0.0400",\ +"-0.3527,-0.3380,-0.3244,-0.2961,-0.2453,-0.1476,0.0350",\ +"-0.3572,-0.3425,-0.3288,-0.3005,-0.2497,-0.1521,0.0305",\ +"-0.3663,-0.3516,-0.3379,-0.3096,-0.2588,-0.1612,0.0214",\ +"-0.3735,-0.3589,-0.3452,-0.3169,-0.2661,-0.1685,0.0142",\ +"-0.4036,-0.3890,-0.3753,-0.3470,-0.2962,-0.1985,-0.0159",\ +"-0.4612,-0.4466,-0.4329,-0.4046,-0.3538,-0.2561,-0.0735"); + } + } + + timing() { + timing_type : hold_rising; + related_pin : "A_CLK"; + when : "(A_WEN & A_MEN)"; + sdf_cond : "A_W_ACCESS"; + + rise_constraint("SIG2SRAM_constraint_template") { + index_1("0.0056,0.0232,0.0400,0.0728,0.1280,0.2440,0.4760"); + index_2("0.0056,0.0232,0.0400,0.0728,0.1280,0.2440,0.4760"); + values ("0.4953,0.4787,0.4660,0.4337,0.3859,0.2824,0.0900",\ +"0.5003,0.4837,0.4710,0.4387,0.3909,0.2874,0.0950",\ +"0.5048,0.4881,0.4755,0.4432,0.3954,0.2919,0.0995",\ +"0.5139,0.4972,0.4846,0.4523,0.4045,0.3010,0.1086",\ +"0.5211,0.5045,0.4918,0.4596,0.4117,0.3082,0.1158",\ +"0.5512,0.5346,0.5219,0.4897,0.4418,0.3383,0.1459",\ +"0.6088,0.5922,0.5795,0.5473,0.4994,0.3959,0.2035"); + } + + fall_constraint("SIG2SRAM_constraint_template") { + index_1("0.0056,0.0232,0.0400,0.0728,0.1280,0.2440,0.4760"); + index_2("0.0056,0.0232,0.0400,0.0728,0.1280,0.2440,0.4760"); + values ("0.4494,0.4347,0.4210,0.3927,0.3429,0.2502,0.0656",\ +"0.4544,0.4397,0.4261,0.3977,0.3479,0.2552,0.0706",\ +"0.4589,0.4442,0.4305,0.4022,0.3524,0.2596,0.0751",\ +"0.4679,0.4533,0.4396,0.4113,0.3615,0.2687,0.0842",\ +"0.4752,0.4606,0.4469,0.4186,0.3688,0.2760,0.0914",\ +"0.5053,0.4906,0.4770,0.4487,0.3989,0.3061,0.1215",\ +"0.5629,0.5483,0.5346,0.5063,0.4565,0.3637,0.1791"); + } + } + } + + pin(A_BIST_EN) { + direction : input ; + capacitance : 0.00401111 ; + max_transition : "1" ; + related_power_pin : VDD; + related_ground_pin : VSS; + internal_power() { + rise_power("scalar") { + values (0); + } + fall_power("scalar") { + values (0); + } + } + } + +bus(A_BIST_ADDR) { + bus_type : A_8_0; + direction : input ; + capacitance : 0.0121077 ; + pin(A_BIST_ADDR[0]) { + capacitance : 0.00568653 ; + } + pin(A_BIST_ADDR[1]) { + capacitance : 0.00767263 ; + } + pin(A_BIST_ADDR[2]) { + capacitance : 0.0105079 ; + } + pin(A_BIST_ADDR[3]) { + capacitance : 0.0068178 ; + } + pin(A_BIST_ADDR[4]) { + capacitance : 0.00624497 ; + } + pin(A_BIST_ADDR[5]) { + capacitance : 0.0105871 ; + } + pin(A_BIST_ADDR[6]) { + capacitance : 0.0130817 ; + } + pin(A_BIST_ADDR[7]) { + capacitance : 0.0104931 ; + } + max_transition : "0.476" ; + pin(A_BIST_ADDR[8:0]) { + related_power_pin : VDD; + related_ground_pin : VSS; + internal_power() { + when : "A_BIST_MEN"; + rise_power("scalar"){ + values (0.0110); + } + fall_power("scalar"){ + values (0.0056); + } + } + internal_power() { + when : "!A_BIST_MEN"; + rise_power("scalar"){ + values (0.0168); + } + fall_power("scalar"){ + values (0.0004); + } + } + } + timing() { + timing_type : setup_rising; + related_pin : "A_BIST_CLK"; + when : "((A_BIST_WEN | A_BIST_REN)& A_BIST_MEN)" + sdf_cond : "A_BIST_RW_ACCESS" + + rise_constraint("SIG2SRAM_constraint_template") { + index_1("0.0056,0.0232,0.0400,0.0728,0.1280,0.2440,0.4760"); + index_2("0.0056,0.0232,0.0400,0.0728,0.1280,0.2440,0.4760"); + values ("-0.4168,-0.3973,-0.3855,-0.3543,-0.3074,-0.2020,-0.0027",\ +"-0.4324,-0.4129,-0.4012,-0.3699,-0.3191,-0.2176,-0.0184",\ +"-0.4441,-0.4285,-0.4129,-0.3816,-0.3309,-0.2293,-0.0301",\ +"-0.4793,-0.4598,-0.4441,-0.4129,-0.3660,-0.2645,-0.0652",\ +"-0.5223,-0.5066,-0.4910,-0.4598,-0.4129,-0.3074,-0.1121",\ +"-0.6199,-0.6082,-0.5926,-0.5613,-0.5145,-0.4129,-0.2137",\ +"-0.8191,-0.8074,-0.7840,-0.7566,-0.7098,-0.6082,-0.4051"); + } + + fall_constraint("SIG2SRAM_constraint_template") { + index_1("0.0056,0.0232,0.0400,0.0728,0.1280,0.2440,0.4760"); + index_2("0.0056,0.0232,0.0400,0.0728,0.1280,0.2440,0.4760"); + values ("-0.3309,-0.3113,-0.2996,-0.2684,-0.2176,-0.1238,0.0637",\ +"-0.3465,-0.3309,-0.3152,-0.2840,-0.2332,-0.1395,0.0480",\ +"-0.3582,-0.3426,-0.3270,-0.2996,-0.2488,-0.1512,0.0324",\ +"-0.3895,-0.3738,-0.3582,-0.3309,-0.2801,-0.1863,0.0051",\ +"-0.4363,-0.4207,-0.4051,-0.3777,-0.3230,-0.2293,-0.0379",\ +"-0.5379,-0.5223,-0.5066,-0.4793,-0.4285,-0.3309,-0.1434",\ +"-0.7332,-0.7176,-0.7020,-0.6746,-0.6238,-0.5262,-0.3387"); + } + } + + + timing() { + timing_type : hold_rising; + related_pin : "A_BIST_CLK"; + when : "((A_BIST_WEN | A_BIST_REN)& A_BIST_MEN)" + sdf_cond : "A_BIST_RW_ACCESS" + + rise_constraint("SIG2SRAM_constraint_template") { + index_1("0.0056,0.0232,0.0400,0.0728,0.1280,0.2440,0.4760"); + index_2("0.0056,0.0232,0.0400,0.0728,0.1280,0.2440,0.4760"); + values ("0.5246,0.5051,0.4895,0.4582,0.4113,0.3059,0.1066",\ +"0.5402,0.5207,0.5051,0.4777,0.4270,0.3215,0.1223",\ +"0.5520,0.5324,0.5168,0.4895,0.4387,0.3371,0.1340",\ +"0.5832,0.5676,0.5520,0.5207,0.4738,0.3684,0.1691",\ +"0.6301,0.6105,0.5949,0.5676,0.5168,0.4113,0.2160",\ +"0.7316,0.7121,0.7004,0.6691,0.6223,0.5168,0.3176",\ +"0.9270,0.9230,0.8957,0.8645,0.8137,0.7121,0.5168"); + } + + fall_constraint("SIG2SRAM_constraint_template") { + index_1("0.0056,0.0232,0.0400,0.0728,0.1280,0.2440,0.4760"); + index_2("0.0056,0.0232,0.0400,0.0728,0.1280,0.2440,0.4760"); + values ("0.4309,0.4152,0.4035,0.3684,0.3215,0.2277,0.0363",\ +"0.4465,0.4309,0.4152,0.3879,0.3371,0.2395,0.0559",\ +"0.4582,0.4426,0.4309,0.3996,0.3488,0.2551,0.0715",\ +"0.4934,0.4777,0.4621,0.4348,0.3840,0.2863,0.0988",\ +"0.5363,0.5207,0.5051,0.4777,0.4270,0.3332,0.1418",\ +"0.6379,0.6262,0.6105,0.5793,0.5324,0.4348,0.2434",\ +"0.8332,0.8215,0.8059,0.7707,0.7238,0.6301,0.4387"); + } + } +} +pin(A_BIST_WEN) { + direction : input ; + capacitance : 0.00324098 ; + max_transition : "0.476" ; + related_power_pin : VDD; + related_ground_pin : VSS; + internal_power() { + when : "A_BIST_MEN"; + rise_power("scalar"){ + values (0.0046); + } + fall_power("scalar"){ + values (0.0039); + } + } + internal_power() { + when : "!A_BIST_MEN"; + rise_power("scalar"){ + values (0.0043); + } + fall_power("scalar"){ + values (0.0040); + } + } + timing() { + timing_type : setup_rising; + related_pin : "A_BIST_CLK"; + when : "A_BIST_MEN" + sdf_cond : "A_BIST_MEN" + + rise_constraint("SIG2SRAM_constraint_template") { + index_1("0.0056,0.0232,0.0400,0.0728,0.1280,0.2440,0.4760"); + index_2("0.0056,0.0232,0.0400,0.0728,0.1280,0.2440,0.4760"); + values ("0.2043,0.2199,0.2316,0.2629,0.3059,0.4113,0.6066",\ +"0.1887,0.2043,0.2160,0.2473,0.2941,0.3957,0.5949",\ +"0.1691,0.1848,0.2004,0.2316,0.2785,0.3801,0.5754",\ +"0.1379,0.1574,0.1691,0.2004,0.2473,0.3527,0.5480",\ +"0.0910,0.1066,0.1223,0.1535,0.2004,0.2980,0.4973",\ +"-0.0105,0.0051,0.0207,0.0520,0.0949,0.2004,0.3957",\ +"-0.2059,-0.1902,-0.1746,-0.1473,-0.1004,0.0051,0.2004"); + } + + fall_constraint("SIG2SRAM_constraint_template") { + index_1("0.0056,0.0232,0.0400,0.0728,0.1280,0.2440,0.4760"); + index_2("0.0056,0.0232,0.0400,0.0728,0.1280,0.2440,0.4760"); + values ("0.2941,0.3098,0.3215,0.3488,0.4035,0.4973,0.6887",\ +"0.2785,0.2941,0.3059,0.3332,0.3840,0.4816,0.6691",\ +"0.2629,0.2785,0.2902,0.3176,0.3684,0.4660,0.6535",\ +"0.2316,0.2473,0.2590,0.2863,0.3410,0.4348,0.6262",\ +"0.1848,0.2004,0.2121,0.2395,0.2902,0.3879,0.5754",\ +"0.0832,0.0988,0.1105,0.1379,0.1809,0.2746,0.4699",\ +"-0.1121,-0.0965,-0.0848,-0.0535,-0.0066,0.0910,0.2824"); + } + } + + + timing() { + timing_type : hold_rising; + related_pin : "A_BIST_CLK"; + when : "A_BIST_MEN" + sdf_cond : "A_BIST_MEN" + + rise_constraint("SIG2SRAM_constraint_template") { + index_1("0.0056,0.0232,0.0400,0.0728,0.1280,0.2440,0.4760"); + index_2("0.0056,0.0232,0.0400,0.0728,0.1280,0.2440,0.4760"); + values ("0.2473,0.2316,0.2160,0.1887,0.1379,0.0363,-0.1629",\ +"0.2629,0.2473,0.2316,0.2043,0.1535,0.0520,-0.1473",\ +"0.2785,0.2590,0.2434,0.2160,0.1652,0.0676,-0.1355",\ +"0.3098,0.2941,0.2785,0.2473,0.1965,0.0910,-0.1043",\ +"0.3527,0.3371,0.3215,0.2941,0.2434,0.1418,-0.0574",\ +"0.4582,0.4426,0.4270,0.3957,0.3488,0.2434,0.0480",\ +"0.6535,0.6379,0.6184,0.5910,0.5402,0.4426,0.2434"); + } + + fall_constraint("SIG2SRAM_constraint_template") { + index_1("0.0056,0.0232,0.0400,0.0728,0.1280,0.2440,0.4760"); + index_2("0.0056,0.0232,0.0400,0.0728,0.1280,0.2440,0.4760"); + values ("0.2395,0.2238,0.2121,0.1809,0.1301,0.0324,-0.1551",\ +"0.2551,0.2395,0.2277,0.1965,0.1457,0.0480,-0.1395",\ +"0.2668,0.2551,0.2395,0.2082,0.1574,0.0637,-0.1277",\ +"0.3020,0.2863,0.2707,0.2395,0.1887,0.0910,-0.0965",\ +"0.3449,0.3293,0.3176,0.2863,0.2355,0.1379,-0.0496",\ +"0.4504,0.4348,0.4191,0.3879,0.3371,0.2395,0.0559",\ +"0.6457,0.6301,0.6145,0.5871,0.5324,0.4309,0.2512"); + } + } + } +pin(A_BIST_REN) { + direction : input ; + capacitance : 0.00381634 ; + max_transition : "0.476" ; + related_power_pin : VDD; + related_ground_pin : VSS; + internal_power() { + when : "A_BIST_MEN"; + rise_power("scalar"){ + values (0.0061); + } + fall_power("scalar"){ + values (0.0021); + } + } + internal_power() { + when : "!A_BIST_MEN"; + rise_power("scalar"){ + values (0.0062); + } + fall_power("scalar"){ + values (0.0025); + } + } + timing() { + timing_type : setup_rising; + related_pin : "A_BIST_CLK"; + when : "A_BIST_MEN" + sdf_cond : "A_BIST_MEN" + + rise_constraint("SIG2SRAM_constraint_template") { + index_1("0.0056,0.0232,0.0400,0.0728,0.1280,0.2440,0.4760"); + index_2("0.0056,0.0232,0.0400,0.0728,0.1280,0.2440,0.4760"); + values ("-0.0301,-0.0145,0.0012,0.0324,0.0793,0.1809,0.3762",\ +"-0.0457,-0.0301,-0.0145,0.0168,0.0637,0.1613,0.3605",\ +"-0.0574,-0.0418,-0.0262,0.0051,0.0520,0.1496,0.3449",\ +"-0.0926,-0.0730,-0.0574,-0.0262,0.0207,0.1184,0.3137",\ +"-0.1395,-0.1238,-0.1082,-0.0770,-0.0301,0.0715,0.2707",\ +"-0.2410,-0.2254,-0.2098,-0.1746,-0.1355,-0.0340,0.1652",\ +"-0.4402,-0.4207,-0.4051,-0.3738,-0.3270,-0.2293,-0.0340"); + } + + fall_constraint("SIG2SRAM_constraint_template") { + index_1("0.0056,0.0232,0.0400,0.0728,0.1280,0.2440,0.4760"); + index_2("0.0056,0.0232,0.0400,0.0728,0.1280,0.2440,0.4760"); + values ("0.0988,0.1145,0.1262,0.1535,0.2043,0.3020,0.4855",\ +"0.0832,0.0988,0.1105,0.1418,0.1848,0.2824,0.4738",\ +"0.0676,0.0832,0.0949,0.1262,0.1730,0.2668,0.4621",\ +"0.0402,0.0559,0.0676,0.0988,0.1457,0.2434,0.4191",\ +"-0.0105,0.0012,0.0168,0.0480,0.0988,0.1965,0.3840",\ +"-0.1160,-0.0965,-0.0848,-0.0535,-0.0066,0.0988,0.2824",\ +"-0.3113,-0.2957,-0.2801,-0.2527,-0.2059,-0.1043,0.0832"); + } + } + + + timing() { + timing_type : hold_rising; + related_pin : "A_BIST_CLK"; + when : "A_BIST_MEN" + sdf_cond : "A_BIST_MEN" + + rise_constraint("SIG2SRAM_constraint_template") { + index_1("0.0056,0.0232,0.0400,0.0728,0.1280,0.2440,0.4760"); + index_2("0.0056,0.0232,0.0400,0.0728,0.1280,0.2440,0.4760"); + values ("0.2707,0.2551,0.2395,0.2121,0.1613,0.0598,-0.1395",\ +"0.2863,0.2707,0.2551,0.2238,0.1730,0.0715,-0.1238",\ +"0.2980,0.2824,0.2668,0.2395,0.1887,0.0871,-0.1121",\ +"0.3332,0.3176,0.3020,0.2707,0.2199,0.1184,-0.0809",\ +"0.3762,0.3605,0.3449,0.3176,0.2668,0.1613,-0.0340",\ +"0.4816,0.4621,0.4504,0.4191,0.3723,0.2629,0.0715",\ +"0.6770,0.6613,0.6418,0.6184,0.5637,0.4699,0.2629"); + } + + fall_constraint("SIG2SRAM_constraint_template") { + index_1("0.0056,0.0232,0.0400,0.0728,0.1280,0.2440,0.4760"); + index_2("0.0056,0.0232,0.0400,0.0728,0.1280,0.2440,0.4760"); + values ("0.2590,0.2434,0.2316,0.2004,0.1457,0.0520,-0.1355",\ +"0.2746,0.2590,0.2434,0.2160,0.1613,0.0676,-0.1199",\ +"0.2863,0.2707,0.2590,0.2277,0.1730,0.0832,-0.1082",\ +"0.3215,0.3059,0.2902,0.2590,0.2082,0.1105,-0.0770",\ +"0.3645,0.3488,0.3332,0.3059,0.2551,0.1535,-0.0340",\ +"0.4699,0.4543,0.4387,0.4074,0.3605,0.2551,0.0715",\ +"0.6652,0.6496,0.6340,0.6027,0.5520,0.4621,0.2707"); + } + } + } +pin(A_BIST_MEN) { + direction : input ; + capacitance : 0.00309605 ; + max_transition : "0.476" ; + related_power_pin : VDD; + related_ground_pin : VSS; + internal_power() { + rise_power("scalar"){ + values (0.0449); + } + fall_power("scalar"){ + values (0.0052); + } + } + timing() { + timing_type : setup_rising; + related_pin : "A_BIST_CLK"; + + rise_constraint("SIG2SRAM_constraint_template") { + index_1("0.0056,0.0232,0.0400,0.0728,0.1280,0.2440,0.4760"); + index_2("0.0056,0.0232,0.0400,0.0728,0.1280,0.2440,0.4760"); + values ("0.2043,0.2199,0.2316,0.2668,0.3098,0.4152,0.6066",\ +"0.1887,0.2043,0.2199,0.2512,0.2941,0.3996,0.5949",\ +"0.1730,0.1887,0.2043,0.2355,0.2824,0.3840,0.5793",\ +"0.1418,0.1574,0.1730,0.2043,0.2512,0.3566,0.5480",\ +"0.0949,0.1105,0.1262,0.1574,0.2043,0.3020,0.5051",\ +"-0.0066,0.0090,0.0246,0.0520,0.0988,0.2043,0.3996",\ +"-0.2020,-0.1863,-0.1746,-0.1434,-0.0965,0.0090,0.2082"); + } + + fall_constraint("SIG2SRAM_constraint_template") { + index_1("0.0056,0.0232,0.0400,0.0728,0.1280,0.2440,0.4760"); + index_2("0.0056,0.0232,0.0400,0.0728,0.1280,0.2440,0.4760"); + values ("0.2980,0.3137,0.3254,0.3527,0.4035,0.5012,0.6887",\ +"0.2824,0.2980,0.3098,0.3371,0.3879,0.4855,0.6730",\ +"0.2668,0.2824,0.2941,0.3215,0.3723,0.4699,0.6574",\ +"0.2355,0.2473,0.2629,0.2902,0.3410,0.4387,0.6262",\ +"0.1887,0.2004,0.2160,0.2395,0.2941,0.3918,0.5793",\ +"0.0871,0.1027,0.1145,0.1418,0.1848,0.2746,0.4816",\ +"-0.1082,-0.0965,-0.0809,-0.0496,-0.0027,0.0949,0.2863"); + } + } + + + timing() { + timing_type : hold_rising; + related_pin : "A_BIST_CLK"; + + rise_constraint("SIG2SRAM_constraint_template") { + index_1("0.0056,0.0232,0.0400,0.0728,0.1280,0.2440,0.4760"); + index_2("0.0056,0.0232,0.0400,0.0728,0.1280,0.2440,0.4760"); + values ("0.2512,0.2355,0.2199,0.1926,0.1418,0.0402,-0.1590",\ +"0.2668,0.2512,0.2355,0.2082,0.1574,0.0559,-0.1434",\ +"0.2824,0.2629,0.2512,0.2199,0.1691,0.0715,-0.1316",\ +"0.3137,0.2980,0.2824,0.2512,0.2004,0.0988,-0.0965",\ +"0.3566,0.3410,0.3254,0.2980,0.2473,0.1418,-0.0535",\ +"0.4621,0.4426,0.4309,0.3996,0.3527,0.2473,0.0520",\ +"0.6574,0.6418,0.6262,0.5949,0.5441,0.4465,0.2473"); + } + + fall_constraint("SIG2SRAM_constraint_template") { + index_1("0.0056,0.0232,0.0400,0.0728,0.1280,0.2440,0.4760"); + index_2("0.0056,0.0232,0.0400,0.0728,0.1280,0.2440,0.4760"); + values ("0.2395,0.2238,0.2121,0.1809,0.1301,0.0324,-0.1551",\ +"0.2551,0.2434,0.2277,0.1965,0.1457,0.0480,-0.1395",\ +"0.2707,0.2551,0.2395,0.2082,0.1574,0.0637,-0.1277",\ +"0.3020,0.2863,0.2707,0.2434,0.1926,0.0910,-0.0965",\ +"0.3449,0.3332,0.3176,0.2863,0.2355,0.1379,-0.0496",\ +"0.4504,0.4348,0.4230,0.3918,0.3410,0.2434,0.0559",\ +"0.6457,0.6301,0.6145,0.5910,0.5324,0.4387,0.2512"); + } + } + } +bus(A_BIST_BM) { + bus_type : D_15_0; + direction : input ; + capacitance : 0.00349377 ; + max_transition : "0.476" ; + pin(A_BIST_BM[15:0]) { + related_power_pin : VDD; + related_ground_pin : VSS; + internal_power() { + when : "A_BIST_MEN"; + rise_power("scalar"){ + values (0.0570); + } + fall_power("scalar"){ + values (0.0255); + } + } + internal_power() { + when : "!A_BIST_MEN"; + rise_power("scalar"){ + values (0.0603); + } + fall_power("scalar"){ + values (0.0244); + } + } + } + timing() { + timing_type : setup_rising; + related_pin : "A_BIST_CLK"; + when : "(A_BIST_WEN & A_BIST_MEN)" + sdf_cond : "A_BIST_RW_ACCESS" + + rise_constraint("SIG2SRAM_constraint_template") { + index_1("0.0056,0.0232,0.0400,0.0728,0.1280,0.2440,0.4760"); + index_2("0.0056,0.0232,0.0400,0.0728,0.1280,0.2440,0.4760"); + values ("-0.3858,-0.3702,-0.3565,-0.3243,-0.2774,-0.1729,0.0185",\ +"-0.3908,-0.3752,-0.3615,-0.3293,-0.2824,-0.1779,0.0135",\ +"-0.3953,-0.3796,-0.3660,-0.3337,-0.2869,-0.1824,0.0090",\ +"-0.4044,-0.3887,-0.3751,-0.3428,-0.2960,-0.1915,-0.0001",\ +"-0.4116,-0.3960,-0.3823,-0.3501,-0.3032,-0.1987,-0.0073",\ +"-0.4417,-0.4261,-0.4124,-0.3802,-0.3333,-0.2288,-0.0374",\ +"-0.4993,-0.4837,-0.4700,-0.4378,-0.3909,-0.2864,-0.0950"); + } + + fall_constraint("SIG2SRAM_constraint_template") { + index_1("0.0056,0.0232,0.0400,0.0728,0.1280,0.2440,0.4760"); + index_2("0.0056,0.0232,0.0400,0.0728,0.1280,0.2440,0.4760"); + values ("-0.3477,-0.3330,-0.3194,-0.2910,-0.2403,-0.1426,0.0400",\ +"-0.3527,-0.3380,-0.3244,-0.2961,-0.2453,-0.1476,0.0350",\ +"-0.3572,-0.3425,-0.3288,-0.3005,-0.2497,-0.1521,0.0305",\ +"-0.3663,-0.3516,-0.3379,-0.3096,-0.2588,-0.1612,0.0214",\ +"-0.3735,-0.3589,-0.3452,-0.3169,-0.2661,-0.1685,0.0142",\ +"-0.4036,-0.3890,-0.3753,-0.3470,-0.2962,-0.1985,-0.0159",\ +"-0.4612,-0.4466,-0.4329,-0.4046,-0.3538,-0.2561,-0.0735"); + } + } + + + timing() { + timing_type : hold_rising; + related_pin : "A_BIST_CLK"; + when : "(A_BIST_WEN & A_BIST_MEN)" + sdf_cond : "A_BIST_RW_ACCESS" + + rise_constraint("SIG2SRAM_constraint_template") { + index_1("0.0056,0.0232,0.0400,0.0728,0.1280,0.2440,0.4760"); + index_2("0.0056,0.0232,0.0400,0.0728,0.1280,0.2440,0.4760"); + values ("0.4953,0.4787,0.4660,0.4337,0.3859,0.2824,0.0900",\ +"0.5003,0.4837,0.4710,0.4387,0.3909,0.2874,0.0950",\ +"0.5048,0.4881,0.4755,0.4432,0.3954,0.2919,0.0995",\ +"0.5139,0.4972,0.4846,0.4523,0.4045,0.3010,0.1086",\ +"0.5211,0.5045,0.4918,0.4596,0.4117,0.3082,0.1158",\ +"0.5512,0.5346,0.5219,0.4897,0.4418,0.3383,0.1459",\ +"0.6088,0.5922,0.5795,0.5473,0.4994,0.3959,0.2035"); + } + + fall_constraint("SIG2SRAM_constraint_template") { + index_1("0.0056,0.0232,0.0400,0.0728,0.1280,0.2440,0.4760"); + index_2("0.0056,0.0232,0.0400,0.0728,0.1280,0.2440,0.4760"); + values ("0.4494,0.4347,0.4210,0.3927,0.3429,0.2502,0.0656",\ +"0.4544,0.4397,0.4261,0.3977,0.3479,0.2552,0.0706",\ +"0.4589,0.4442,0.4305,0.4022,0.3524,0.2596,0.0751",\ +"0.4679,0.4533,0.4396,0.4113,0.3615,0.2687,0.0842",\ +"0.4752,0.4606,0.4469,0.4186,0.3688,0.2760,0.0914",\ +"0.5053,0.4906,0.4770,0.4487,0.3989,0.3061,0.1215",\ +"0.5629,0.5483,0.5346,0.5063,0.4565,0.3637,0.1791"); + } + } +} + pin(A_BIST_CLK) { + direction : input; + capacitance : 0.00380014; + max_transition : "0.476"; + clock : "true" ; + pin_func_type : active_rising ; + + timing () { + timing_type : "min_pulse_width"; + related_pin : "A_BIST_CLK"; + rise_constraint("CLKTRAN_constraint_template") { + index_1("0.0056,0.476"); + values("0.21,0.21"); + } + } + + related_power_pin : VDD; + related_ground_pin : VSS; + + internal_power() { + when : "!A_BIST_MEN & !A_BIST_WEN & !A_BIST_REN"; + rise_power("scalar"){ + values (0); + } + fall_power("scalar"){ + values (0); + } + } + internal_power() { + when : "!A_BIST_MEN & A_BIST_WEN & !A_BIST_REN"; + rise_power("scalar"){ + values (0.5315); + } + fall_power("scalar"){ + values (0); + } + } + internal_power() { + when : "A_BIST_MEN & A_BIST_WEN & !A_BIST_REN"; + rise_power("scalar"){ + values (23.4667); + } + fall_power("scalar"){ + values (0); + } + } + internal_power() { + when : "A_BIST_MEN & A_BIST_WEN & A_BIST_REN"; + rise_power("scalar"){ + values (25.7036); + } + fall_power("scalar"){ + values (0); + } + } + internal_power() { + when : "A_BIST_MEN & !A_BIST_WEN & A_BIST_REN"; + rise_power("scalar"){ + values (19.5664); + } + fall_power("scalar"){ + values (0); + } + } + internal_power() { + when : "!A_BIST_MEN & !A_BIST_WEN & A_BIST_REN"; + rise_power("scalar"){ + values (0.3077); + } + fall_power("scalar"){ + values (0); + } + } + internal_power() { + when : "!A_BIST_MEN & A_BIST_WEN & A_BIST_REN"; + rise_power("scalar"){ + values (0.7640); + } + fall_power("scalar"){ + values (0); + } + } + internal_power() { + when : "A_BIST_MEN & !A_BIST_WEN & !A_BIST_REN"; + rise_power("scalar"){ + values (0); + } + fall_power("scalar"){ + values (0); + } + } + } + bus(A_BIST_DIN) { + bus_type : D_15_0; + direction : input ; + capacitance : 0.00393889 ; + memory_write() { + address : A_BIST_ADDR ; + clocked_on : A_BIST_CLK; + } + + max_transition : "0.476" ; + pin(A_BIST_DIN[15:0]) { + related_power_pin : VDD; + related_ground_pin : VSS; + internal_power() { + when : "A_BIST_MEN"; + rise_power("scalar"){ + values (0.0570); + } + fall_power("scalar"){ + values (0.0255); + } + } + internal_power() { + when : "!A_BIST_MEN"; + rise_power("scalar"){ + values (0.0603); + } + fall_power("scalar"){ + values (0.0244); + } + } + } + timing() { + timing_type : setup_rising; + related_pin : "A_BIST_CLK"; + when : "(A_BIST_WEN & A_BIST_MEN)"; + sdf_cond : "A_BIST_W_ACCESS"; + + rise_constraint("SIG2SRAM_constraint_template") { + index_1("0.0056,0.0232,0.0400,0.0728,0.1280,0.2440,0.4760"); + index_2("0.0056,0.0232,0.0400,0.0728,0.1280,0.2440,0.4760"); + values ("-0.3858,-0.3702,-0.3565,-0.3243,-0.2774,-0.1729,0.0185",\ +"-0.3908,-0.3752,-0.3615,-0.3293,-0.2824,-0.1779,0.0135",\ +"-0.3953,-0.3796,-0.3660,-0.3337,-0.2869,-0.1824,0.0090",\ +"-0.4044,-0.3887,-0.3751,-0.3428,-0.2960,-0.1915,-0.0001",\ +"-0.4116,-0.3960,-0.3823,-0.3501,-0.3032,-0.1987,-0.0073",\ +"-0.4417,-0.4261,-0.4124,-0.3802,-0.3333,-0.2288,-0.0374",\ +"-0.4993,-0.4837,-0.4700,-0.4378,-0.3909,-0.2864,-0.0950"); + } + + fall_constraint("SIG2SRAM_constraint_template") { + index_1("0.0056,0.0232,0.0400,0.0728,0.1280,0.2440,0.4760"); + index_2("0.0056,0.0232,0.0400,0.0728,0.1280,0.2440,0.4760"); + values ("-0.3477,-0.3330,-0.3194,-0.2910,-0.2403,-0.1426,0.0400",\ +"-0.3527,-0.3380,-0.3244,-0.2961,-0.2453,-0.1476,0.0350",\ +"-0.3572,-0.3425,-0.3288,-0.3005,-0.2497,-0.1521,0.0305",\ +"-0.3663,-0.3516,-0.3379,-0.3096,-0.2588,-0.1612,0.0214",\ +"-0.3735,-0.3589,-0.3452,-0.3169,-0.2661,-0.1685,0.0142",\ +"-0.4036,-0.3890,-0.3753,-0.3470,-0.2962,-0.1985,-0.0159",\ +"-0.4612,-0.4466,-0.4329,-0.4046,-0.3538,-0.2561,-0.0735"); + } + } + + timing() { + timing_type : hold_rising; + related_pin : "A_BIST_CLK"; + when : "(A_BIST_WEN & A_BIST_MEN)"; + sdf_cond : "A_BIST_W_ACCESS"; + + rise_constraint("SIG2SRAM_constraint_template") { + index_1("0.0056,0.0232,0.0400,0.0728,0.1280,0.2440,0.4760"); + index_2("0.0056,0.0232,0.0400,0.0728,0.1280,0.2440,0.4760"); + values ("0.4953,0.4787,0.4660,0.4337,0.3859,0.2824,0.0900",\ +"0.5003,0.4837,0.4710,0.4387,0.3909,0.2874,0.0950",\ +"0.5048,0.4881,0.4755,0.4432,0.3954,0.2919,0.0995",\ +"0.5139,0.4972,0.4846,0.4523,0.4045,0.3010,0.1086",\ +"0.5211,0.5045,0.4918,0.4596,0.4117,0.3082,0.1158",\ +"0.5512,0.5346,0.5219,0.4897,0.4418,0.3383,0.1459",\ +"0.6088,0.5922,0.5795,0.5473,0.4994,0.3959,0.2035"); + } + + fall_constraint("SIG2SRAM_constraint_template") { + index_1("0.0056,0.0232,0.0400,0.0728,0.1280,0.2440,0.4760"); + index_2("0.0056,0.0232,0.0400,0.0728,0.1280,0.2440,0.4760"); + values ("0.4494,0.4347,0.4210,0.3927,0.3429,0.2502,0.0656",\ +"0.4544,0.4397,0.4261,0.3977,0.3479,0.2552,0.0706",\ +"0.4589,0.4442,0.4305,0.4022,0.3524,0.2596,0.0751",\ +"0.4679,0.4533,0.4396,0.4113,0.3615,0.2687,0.0842",\ +"0.4752,0.4606,0.4469,0.4186,0.3688,0.2760,0.0914",\ +"0.5053,0.4906,0.4770,0.4487,0.3989,0.3061,0.1215",\ +"0.5629,0.5483,0.5346,0.5063,0.4565,0.3637,0.1791"); + } + } + } + +bus(A_DOUT) { + + bus_type : D_15_0; + direction : output ; + capacitance : 0 ; + max_capacitance : 0.064 ; + memory_read() { + address : A_ADDR ; + } + pin(A_DOUT[15:0]) { + related_power_pin : VDD; + related_ground_pin : VSS; + internal_power() { + rise_power("scalar") { + values (0); + } + fall_power("scalar") { + values (0); + } + } + } + timing() { + related_pin : "A_CLK"; + timing_type : rising_edge ; + timing_sense : non_unate ; + + cell_rise(SIG2SRAM_delay_template) { + index_1("0.0056,0.0232,0.0400,0.0728,0.1280,0.2440,0.4760"); + index_2("0.0008,0.0014,0.0051,0.0100,0.0339,0.0640"); + values ("3.7906,3.7922,3.7999,3.8086,3.8410,3.8771",\ +"3.7958,3.7974,3.8050,3.8137,3.8461,3.8823",\ +"3.7990,3.8006,3.8082,3.8169,3.8493,3.8855",\ +"3.8114,3.8131,3.8207,3.8294,3.8618,3.8979",\ +"3.8173,3.8189,3.8265,3.8352,3.8676,3.9038",\ +"3.8482,3.8499,3.8575,3.8662,3.8986,3.9347",\ +"3.9039,3.9056,3.9132,3.9219,3.9543,3.9904"); + } + cell_fall(SIG2SRAM_delay_template) { + index_1("0.0056,0.0232,0.0400,0.0728,0.1280,0.2440,0.4760"); + index_2("0.0008,0.0014,0.0051,0.0100,0.0339,0.0640"); + values ("3.7303,3.7317,3.7378,3.7449,3.7714,3.7976",\ +"3.7355,3.7368,3.7429,3.7500,3.7765,3.8028",\ +"3.7387,3.7400,3.7461,3.7532,3.7797,3.8060",\ +"3.7512,3.7525,3.7586,3.7657,3.7922,3.8184",\ +"3.7570,3.7583,3.7644,3.7715,3.7980,3.8243",\ +"3.7880,3.7893,3.7954,3.8025,3.8290,3.8552",\ +"3.8437,3.8450,3.8511,3.8582,3.8847,3.9109"); + } + + rise_transition(SRAM_load_template) { + index_1("0.0008,0.0014,0.0051,0.0100,0.0339,0.0640"); + values ("0.0326,0.0341,0.0428,0.0518,0.0923,0.1492"); + } + fall_transition(SRAM_load_template) { + index_1("0.0008,0.0014,0.0051,0.0100,0.0339,0.0640"); + values ("0.0254,0.0265,0.0335,0.0402,0.0707,0.1039"); + } + } +} + pin(B_DLY) { + direction : input ; + capacitance : 0.00401111 ; + max_transition : "1" ; + related_power_pin : VDD; + related_ground_pin : VSS; + internal_power() { + rise_power("scalar") { + values (0); + } + fall_power("scalar") { + values (0); + } + } + } + +bus(B_ADDR) { + bus_type : A_8_0; + direction : input ; + capacitance : 0.0121077 ; + pin(B_ADDR[0]) { + capacitance : 0.00570093 ; + } + pin(B_ADDR[1]) { + capacitance : 0.00764555 ; + } + pin(B_ADDR[2]) { + capacitance : 0.0105375 ; + } + pin(B_ADDR[3]) { + capacitance : 0.0067894 ; + } + pin(B_ADDR[4]) { + capacitance : 0.00630967 ; + } + pin(B_ADDR[5]) { + capacitance : 0.0104132 ; + } + pin(B_ADDR[6]) { + capacitance : 0.0131402 ; + } + pin(B_ADDR[7]) { + capacitance : 0.0105203 ; + } + max_transition : "0.476" ; + pin(B_ADDR[8:0]) { + related_power_pin : VDD; + related_ground_pin : VSS; + internal_power() { + when : "B_MEN"; + rise_power("scalar"){ + values (0.0110); + } + fall_power("scalar"){ + values (0.0056); + } + } + internal_power() { + when : "!B_MEN"; + rise_power("scalar"){ + values (0.0168); + } + fall_power("scalar"){ + values (0.0004); + } + } + } + timing() { + timing_type : setup_rising; + related_pin : "B_CLK"; + when : "((B_WEN | B_REN)& B_MEN)" + sdf_cond : "B_RW_ACCESS" + + rise_constraint("SIG2SRAM_constraint_template") { + index_1("0.0056,0.0232,0.0400,0.0728,0.1280,0.2440,0.4760"); + index_2("0.0056,0.0232,0.0400,0.0728,0.1280,0.2440,0.4760"); + values ("-0.4168,-0.3973,-0.3855,-0.3543,-0.3074,-0.2020,-0.0027",\ +"-0.4324,-0.4129,-0.4012,-0.3699,-0.3191,-0.2176,-0.0184",\ +"-0.4441,-0.4285,-0.4129,-0.3816,-0.3309,-0.2293,-0.0301",\ +"-0.4793,-0.4598,-0.4441,-0.4129,-0.3660,-0.2645,-0.0652",\ +"-0.5223,-0.5066,-0.4910,-0.4598,-0.4129,-0.3074,-0.1121",\ +"-0.6199,-0.6082,-0.5926,-0.5613,-0.5145,-0.4129,-0.2137",\ +"-0.8191,-0.8074,-0.7840,-0.7566,-0.7098,-0.6082,-0.4051"); + } + + fall_constraint("SIG2SRAM_constraint_template") { + index_1("0.0056,0.0232,0.0400,0.0728,0.1280,0.2440,0.4760"); + index_2("0.0056,0.0232,0.0400,0.0728,0.1280,0.2440,0.4760"); + values ("-0.3309,-0.3113,-0.2996,-0.2684,-0.2176,-0.1238,0.0637",\ +"-0.3465,-0.3309,-0.3152,-0.2840,-0.2332,-0.1395,0.0480",\ +"-0.3582,-0.3426,-0.3270,-0.2996,-0.2488,-0.1512,0.0324",\ +"-0.3895,-0.3738,-0.3582,-0.3309,-0.2801,-0.1863,0.0051",\ +"-0.4363,-0.4207,-0.4051,-0.3777,-0.3230,-0.2293,-0.0379",\ +"-0.5379,-0.5223,-0.5066,-0.4793,-0.4285,-0.3309,-0.1434",\ +"-0.7332,-0.7176,-0.7020,-0.6746,-0.6238,-0.5262,-0.3387"); + } + } + + + timing() { + timing_type : hold_rising; + related_pin : "B_CLK"; + when : "((B_WEN | B_REN)& B_MEN)" + sdf_cond : "B_RW_ACCESS" + + rise_constraint("SIG2SRAM_constraint_template") { + index_1("0.0056,0.0232,0.0400,0.0728,0.1280,0.2440,0.4760"); + index_2("0.0056,0.0232,0.0400,0.0728,0.1280,0.2440,0.4760"); + values ("0.5246,0.5051,0.4895,0.4582,0.4113,0.3059,0.1066",\ +"0.5402,0.5207,0.5051,0.4777,0.4270,0.3215,0.1223",\ +"0.5520,0.5324,0.5168,0.4895,0.4387,0.3371,0.1340",\ +"0.5832,0.5676,0.5520,0.5207,0.4738,0.3684,0.1691",\ +"0.6301,0.6105,0.5949,0.5676,0.5168,0.4113,0.2160",\ +"0.7316,0.7121,0.7004,0.6691,0.6223,0.5168,0.3176",\ +"0.9270,0.9230,0.8957,0.8645,0.8137,0.7121,0.5168"); + } + + fall_constraint("SIG2SRAM_constraint_template") { + index_1("0.0056,0.0232,0.0400,0.0728,0.1280,0.2440,0.4760"); + index_2("0.0056,0.0232,0.0400,0.0728,0.1280,0.2440,0.4760"); + values ("0.4309,0.4152,0.4035,0.3684,0.3215,0.2277,0.0363",\ +"0.4465,0.4309,0.4152,0.3879,0.3371,0.2395,0.0559",\ +"0.4582,0.4426,0.4309,0.3996,0.3488,0.2551,0.0715",\ +"0.4934,0.4777,0.4621,0.4348,0.3840,0.2863,0.0988",\ +"0.5363,0.5207,0.5051,0.4777,0.4270,0.3332,0.1418",\ +"0.6379,0.6262,0.6105,0.5793,0.5324,0.4348,0.2434",\ +"0.8332,0.8215,0.8059,0.7707,0.7238,0.6301,0.4387"); + } + } +} +pin(B_WEN) { + direction : input ; + capacitance : 0.00324098 ; + max_transition : "0.476" ; + related_power_pin : VDD; + related_ground_pin : VSS; + internal_power() { + when : "B_MEN"; + rise_power("scalar"){ + values (0.0046); + } + fall_power("scalar"){ + values (0.0039); + } + } + internal_power() { + when : "!B_MEN"; + rise_power("scalar"){ + values (0.0043); + } + fall_power("scalar"){ + values (0.0040); + } + } + timing() { + timing_type : setup_rising; + related_pin : "B_CLK"; + when : "B_MEN" + sdf_cond : "B_MEN" + + rise_constraint("SIG2SRAM_constraint_template") { + index_1("0.0056,0.0232,0.0400,0.0728,0.1280,0.2440,0.4760"); + index_2("0.0056,0.0232,0.0400,0.0728,0.1280,0.2440,0.4760"); + values ("0.2043,0.2199,0.2316,0.2629,0.3059,0.4113,0.6066",\ +"0.1887,0.2043,0.2160,0.2473,0.2941,0.3957,0.5949",\ +"0.1691,0.1848,0.2004,0.2316,0.2785,0.3801,0.5754",\ +"0.1379,0.1574,0.1691,0.2004,0.2473,0.3527,0.5480",\ +"0.0910,0.1066,0.1223,0.1535,0.2004,0.2980,0.4973",\ +"-0.0105,0.0051,0.0207,0.0520,0.0949,0.2004,0.3957",\ +"-0.2059,-0.1902,-0.1746,-0.1473,-0.1004,0.0051,0.2004"); + } + + fall_constraint("SIG2SRAM_constraint_template") { + index_1("0.0056,0.0232,0.0400,0.0728,0.1280,0.2440,0.4760"); + index_2("0.0056,0.0232,0.0400,0.0728,0.1280,0.2440,0.4760"); + values ("0.2941,0.3098,0.3215,0.3488,0.4035,0.4973,0.6887",\ +"0.2785,0.2941,0.3059,0.3332,0.3840,0.4816,0.6691",\ +"0.2629,0.2785,0.2902,0.3176,0.3684,0.4660,0.6535",\ +"0.2316,0.2473,0.2590,0.2863,0.3410,0.4348,0.6262",\ +"0.1848,0.2004,0.2121,0.2395,0.2902,0.3879,0.5754",\ +"0.0832,0.0988,0.1105,0.1379,0.1809,0.2746,0.4699",\ +"-0.1121,-0.0965,-0.0848,-0.0535,-0.0066,0.0910,0.2824"); + } + } + + + timing() { + timing_type : hold_rising; + related_pin : "B_CLK"; + when : "B_MEN" + sdf_cond : "B_MEN" + + rise_constraint("SIG2SRAM_constraint_template") { + index_1("0.0056,0.0232,0.0400,0.0728,0.1280,0.2440,0.4760"); + index_2("0.0056,0.0232,0.0400,0.0728,0.1280,0.2440,0.4760"); + values ("0.2473,0.2316,0.2160,0.1887,0.1379,0.0363,-0.1629",\ +"0.2629,0.2473,0.2316,0.2043,0.1535,0.0520,-0.1473",\ +"0.2785,0.2590,0.2434,0.2160,0.1652,0.0676,-0.1355",\ +"0.3098,0.2941,0.2785,0.2473,0.1965,0.0910,-0.1043",\ +"0.3527,0.3371,0.3215,0.2941,0.2434,0.1418,-0.0574",\ +"0.4582,0.4426,0.4270,0.3957,0.3488,0.2434,0.0480",\ +"0.6535,0.6379,0.6184,0.5910,0.5402,0.4426,0.2434"); + } + + fall_constraint("SIG2SRAM_constraint_template") { + index_1("0.0056,0.0232,0.0400,0.0728,0.1280,0.2440,0.4760"); + index_2("0.0056,0.0232,0.0400,0.0728,0.1280,0.2440,0.4760"); + values ("0.2395,0.2238,0.2121,0.1809,0.1301,0.0324,-0.1551",\ +"0.2551,0.2395,0.2277,0.1965,0.1457,0.0480,-0.1395",\ +"0.2668,0.2551,0.2395,0.2082,0.1574,0.0637,-0.1277",\ +"0.3020,0.2863,0.2707,0.2395,0.1887,0.0910,-0.0965",\ +"0.3449,0.3293,0.3176,0.2863,0.2355,0.1379,-0.0496",\ +"0.4504,0.4348,0.4191,0.3879,0.3371,0.2395,0.0559",\ +"0.6457,0.6301,0.6145,0.5871,0.5324,0.4309,0.2512"); + } + } + } +pin(B_REN) { + direction : input ; + capacitance : 0.00381634 ; + max_transition : "0.476" ; + related_power_pin : VDD; + related_ground_pin : VSS; + internal_power() { + when : "B_MEN"; + rise_power("scalar"){ + values (0.0061); + } + fall_power("scalar"){ + values (0.0021); + } + } + internal_power() { + when : "!B_MEN"; + rise_power("scalar"){ + values (0.0062); + } + fall_power("scalar"){ + values (0.0025); + } + } + timing() { + timing_type : setup_rising; + related_pin : "B_CLK"; + when : "B_MEN" + sdf_cond : "B_MEN" + + rise_constraint("SIG2SRAM_constraint_template") { + index_1("0.0056,0.0232,0.0400,0.0728,0.1280,0.2440,0.4760"); + index_2("0.0056,0.0232,0.0400,0.0728,0.1280,0.2440,0.4760"); + values ("-0.0301,-0.0145,0.0012,0.0324,0.0793,0.1809,0.3762",\ +"-0.0457,-0.0301,-0.0145,0.0168,0.0637,0.1613,0.3605",\ +"-0.0574,-0.0418,-0.0262,0.0051,0.0520,0.1496,0.3449",\ +"-0.0926,-0.0730,-0.0574,-0.0262,0.0207,0.1184,0.3137",\ +"-0.1395,-0.1238,-0.1082,-0.0770,-0.0301,0.0715,0.2707",\ +"-0.2410,-0.2254,-0.2098,-0.1746,-0.1355,-0.0340,0.1652",\ +"-0.4402,-0.4207,-0.4051,-0.3738,-0.3270,-0.2293,-0.0340"); + } + + fall_constraint("SIG2SRAM_constraint_template") { + index_1("0.0056,0.0232,0.0400,0.0728,0.1280,0.2440,0.4760"); + index_2("0.0056,0.0232,0.0400,0.0728,0.1280,0.2440,0.4760"); + values ("0.0988,0.1145,0.1262,0.1535,0.2043,0.3020,0.4855",\ +"0.0832,0.0988,0.1105,0.1418,0.1848,0.2824,0.4738",\ +"0.0676,0.0832,0.0949,0.1262,0.1730,0.2668,0.4621",\ +"0.0402,0.0559,0.0676,0.0988,0.1457,0.2434,0.4191",\ +"-0.0105,0.0012,0.0168,0.0480,0.0988,0.1965,0.3840",\ +"-0.1160,-0.0965,-0.0848,-0.0535,-0.0066,0.0988,0.2824",\ +"-0.3113,-0.2957,-0.2801,-0.2527,-0.2059,-0.1043,0.0832"); + } + } + + + timing() { + timing_type : hold_rising; + related_pin : "B_CLK"; + when : "B_MEN" + sdf_cond : "B_MEN" + + rise_constraint("SIG2SRAM_constraint_template") { + index_1("0.0056,0.0232,0.0400,0.0728,0.1280,0.2440,0.4760"); + index_2("0.0056,0.0232,0.0400,0.0728,0.1280,0.2440,0.4760"); + values ("0.2707,0.2551,0.2395,0.2121,0.1613,0.0598,-0.1395",\ +"0.2863,0.2707,0.2551,0.2238,0.1730,0.0715,-0.1238",\ +"0.2980,0.2824,0.2668,0.2395,0.1887,0.0871,-0.1121",\ +"0.3332,0.3176,0.3020,0.2707,0.2199,0.1184,-0.0809",\ +"0.3762,0.3605,0.3449,0.3176,0.2668,0.1613,-0.0340",\ +"0.4816,0.4621,0.4504,0.4191,0.3723,0.2629,0.0715",\ +"0.6770,0.6613,0.6418,0.6184,0.5637,0.4699,0.2629"); + } + + fall_constraint("SIG2SRAM_constraint_template") { + index_1("0.0056,0.0232,0.0400,0.0728,0.1280,0.2440,0.4760"); + index_2("0.0056,0.0232,0.0400,0.0728,0.1280,0.2440,0.4760"); + values ("0.2590,0.2434,0.2316,0.2004,0.1457,0.0520,-0.1355",\ +"0.2746,0.2590,0.2434,0.2160,0.1613,0.0676,-0.1199",\ +"0.2863,0.2707,0.2590,0.2277,0.1730,0.0832,-0.1082",\ +"0.3215,0.3059,0.2902,0.2590,0.2082,0.1105,-0.0770",\ +"0.3645,0.3488,0.3332,0.3059,0.2551,0.1535,-0.0340",\ +"0.4699,0.4543,0.4387,0.4074,0.3605,0.2551,0.0715",\ +"0.6652,0.6496,0.6340,0.6027,0.5520,0.4621,0.2707"); + } + } + } +pin(B_MEN) { + direction : input ; + capacitance : 0.00309605 ; + max_transition : "0.476" ; + related_power_pin : VDD; + related_ground_pin : VSS; + internal_power() { + rise_power("scalar"){ + values (0.0449); + } + fall_power("scalar"){ + values (0.0052); + } + } + timing() { + timing_type : setup_rising; + related_pin : "B_CLK"; + + rise_constraint("SIG2SRAM_constraint_template") { + index_1("0.0056,0.0232,0.0400,0.0728,0.1280,0.2440,0.4760"); + index_2("0.0056,0.0232,0.0400,0.0728,0.1280,0.2440,0.4760"); + values ("0.2043,0.2199,0.2316,0.2668,0.3098,0.4152,0.6066",\ +"0.1887,0.2043,0.2199,0.2512,0.2941,0.3996,0.5949",\ +"0.1730,0.1887,0.2043,0.2355,0.2824,0.3840,0.5793",\ +"0.1418,0.1574,0.1730,0.2043,0.2512,0.3566,0.5480",\ +"0.0949,0.1105,0.1262,0.1574,0.2043,0.3020,0.5051",\ +"-0.0066,0.0090,0.0246,0.0520,0.0988,0.2043,0.3996",\ +"-0.2020,-0.1863,-0.1746,-0.1434,-0.0965,0.0090,0.2082"); + } + + fall_constraint("SIG2SRAM_constraint_template") { + index_1("0.0056,0.0232,0.0400,0.0728,0.1280,0.2440,0.4760"); + index_2("0.0056,0.0232,0.0400,0.0728,0.1280,0.2440,0.4760"); + values ("0.2980,0.3137,0.3254,0.3527,0.4035,0.5012,0.6887",\ +"0.2824,0.2980,0.3098,0.3371,0.3879,0.4855,0.6730",\ +"0.2668,0.2824,0.2941,0.3215,0.3723,0.4699,0.6574",\ +"0.2355,0.2473,0.2629,0.2902,0.3410,0.4387,0.6262",\ +"0.1887,0.2004,0.2160,0.2395,0.2941,0.3918,0.5793",\ +"0.0871,0.1027,0.1145,0.1418,0.1848,0.2746,0.4816",\ +"-0.1082,-0.0965,-0.0809,-0.0496,-0.0027,0.0949,0.2863"); + } + } + + + timing() { + timing_type : hold_rising; + related_pin : "B_CLK"; + + rise_constraint("SIG2SRAM_constraint_template") { + index_1("0.0056,0.0232,0.0400,0.0728,0.1280,0.2440,0.4760"); + index_2("0.0056,0.0232,0.0400,0.0728,0.1280,0.2440,0.4760"); + values ("0.2512,0.2355,0.2199,0.1926,0.1418,0.0402,-0.1590",\ +"0.2668,0.2512,0.2355,0.2082,0.1574,0.0559,-0.1434",\ +"0.2824,0.2629,0.2512,0.2199,0.1691,0.0715,-0.1316",\ +"0.3137,0.2980,0.2824,0.2512,0.2004,0.0988,-0.0965",\ +"0.3566,0.3410,0.3254,0.2980,0.2473,0.1418,-0.0535",\ +"0.4621,0.4426,0.4309,0.3996,0.3527,0.2473,0.0520",\ +"0.6574,0.6418,0.6262,0.5949,0.5441,0.4465,0.2473"); + } + + fall_constraint("SIG2SRAM_constraint_template") { + index_1("0.0056,0.0232,0.0400,0.0728,0.1280,0.2440,0.4760"); + index_2("0.0056,0.0232,0.0400,0.0728,0.1280,0.2440,0.4760"); + values ("0.2395,0.2238,0.2121,0.1809,0.1301,0.0324,-0.1551",\ +"0.2551,0.2434,0.2277,0.1965,0.1457,0.0480,-0.1395",\ +"0.2707,0.2551,0.2395,0.2082,0.1574,0.0637,-0.1277",\ +"0.3020,0.2863,0.2707,0.2434,0.1926,0.0910,-0.0965",\ +"0.3449,0.3332,0.3176,0.2863,0.2355,0.1379,-0.0496",\ +"0.4504,0.4348,0.4230,0.3918,0.3410,0.2434,0.0559",\ +"0.6457,0.6301,0.6145,0.5910,0.5324,0.4387,0.2512"); + } + } + } +bus(B_BM) { + bus_type : D_15_0; + direction : input ; + capacitance : 0.00312518 ; + max_transition : "0.476" ; + pin(B_BM[15:0]) { + related_power_pin : VDD; + related_ground_pin : VSS; + internal_power() { + when : "B_MEN"; + rise_power("scalar"){ + values (0.0570); + } + fall_power("scalar"){ + values (0.0255); + } + } + internal_power() { + when : "!B_MEN"; + rise_power("scalar"){ + values (0.0603); + } + fall_power("scalar"){ + values (0.0244); + } + } + } + timing() { + timing_type : setup_rising; + related_pin : "B_CLK"; + when : "(B_WEN & B_MEN)" + sdf_cond : "B_RW_ACCESS" + + rise_constraint("SIG2SRAM_constraint_template") { + index_1("0.0056,0.0232,0.0400,0.0728,0.1280,0.2440,0.4760"); + index_2("0.0056,0.0232,0.0400,0.0728,0.1280,0.2440,0.4760"); + values ("-0.3858,-0.3702,-0.3565,-0.3243,-0.2774,-0.1729,0.0185",\ +"-0.3908,-0.3752,-0.3615,-0.3293,-0.2824,-0.1779,0.0135",\ +"-0.3953,-0.3796,-0.3660,-0.3337,-0.2869,-0.1824,0.0090",\ +"-0.4044,-0.3887,-0.3751,-0.3428,-0.2960,-0.1915,-0.0001",\ +"-0.4116,-0.3960,-0.3823,-0.3501,-0.3032,-0.1987,-0.0073",\ +"-0.4417,-0.4261,-0.4124,-0.3802,-0.3333,-0.2288,-0.0374",\ +"-0.4993,-0.4837,-0.4700,-0.4378,-0.3909,-0.2864,-0.0950"); + } + + fall_constraint("SIG2SRAM_constraint_template") { + index_1("0.0056,0.0232,0.0400,0.0728,0.1280,0.2440,0.4760"); + index_2("0.0056,0.0232,0.0400,0.0728,0.1280,0.2440,0.4760"); + values ("-0.3477,-0.3330,-0.3194,-0.2910,-0.2403,-0.1426,0.0400",\ +"-0.3527,-0.3380,-0.3244,-0.2961,-0.2453,-0.1476,0.0350",\ +"-0.3572,-0.3425,-0.3288,-0.3005,-0.2497,-0.1521,0.0305",\ +"-0.3663,-0.3516,-0.3379,-0.3096,-0.2588,-0.1612,0.0214",\ +"-0.3735,-0.3589,-0.3452,-0.3169,-0.2661,-0.1685,0.0142",\ +"-0.4036,-0.3890,-0.3753,-0.3470,-0.2962,-0.1985,-0.0159",\ +"-0.4612,-0.4466,-0.4329,-0.4046,-0.3538,-0.2561,-0.0735"); + } + } + + + timing() { + timing_type : hold_rising; + related_pin : "B_CLK"; + when : "(B_WEN & B_MEN)" + sdf_cond : "B_RW_ACCESS" + + rise_constraint("SIG2SRAM_constraint_template") { + index_1("0.0056,0.0232,0.0400,0.0728,0.1280,0.2440,0.4760"); + index_2("0.0056,0.0232,0.0400,0.0728,0.1280,0.2440,0.4760"); + values ("0.4953,0.4787,0.4660,0.4337,0.3859,0.2824,0.0900",\ +"0.5003,0.4837,0.4710,0.4387,0.3909,0.2874,0.0950",\ +"0.5048,0.4881,0.4755,0.4432,0.3954,0.2919,0.0995",\ +"0.5139,0.4972,0.4846,0.4523,0.4045,0.3010,0.1086",\ +"0.5211,0.5045,0.4918,0.4596,0.4117,0.3082,0.1158",\ +"0.5512,0.5346,0.5219,0.4897,0.4418,0.3383,0.1459",\ +"0.6088,0.5922,0.5795,0.5473,0.4994,0.3959,0.2035"); + } + + fall_constraint("SIG2SRAM_constraint_template") { + index_1("0.0056,0.0232,0.0400,0.0728,0.1280,0.2440,0.4760"); + index_2("0.0056,0.0232,0.0400,0.0728,0.1280,0.2440,0.4760"); + values ("0.4494,0.4347,0.4210,0.3927,0.3429,0.2502,0.0656",\ +"0.4544,0.4397,0.4261,0.3977,0.3479,0.2552,0.0706",\ +"0.4589,0.4442,0.4305,0.4022,0.3524,0.2596,0.0751",\ +"0.4679,0.4533,0.4396,0.4113,0.3615,0.2687,0.0842",\ +"0.4752,0.4606,0.4469,0.4186,0.3688,0.2760,0.0914",\ +"0.5053,0.4906,0.4770,0.4487,0.3989,0.3061,0.1215",\ +"0.5629,0.5483,0.5346,0.5063,0.4565,0.3637,0.1791"); + } + } +} + pin(B_CLK) { + direction : input; + capacitance : 0.00380014; + max_transition : "0.476"; + clock : "true" ; + pin_func_type : active_rising ; + + timing () { + timing_type : "min_pulse_width"; + related_pin : "B_CLK"; + rise_constraint("CLKTRAN_constraint_template") { + index_1("0.0056,0.476"); + values("0.21,0.21"); + } + } + + related_power_pin : VDD; + related_ground_pin : VSS; + + internal_power() { + when : "!B_MEN & !B_WEN & !B_REN"; + rise_power("scalar"){ + values (0); + } + fall_power("scalar"){ + values (0); + } + } + internal_power() { + when : "!B_MEN & B_WEN & !B_REN"; + rise_power("scalar"){ + values (0.5315); + } + fall_power("scalar"){ + values (0); + } + } + internal_power() { + when : "B_MEN & B_WEN & !B_REN"; + rise_power("scalar"){ + values (23.4667); + } + fall_power("scalar"){ + values (0); + } + } + internal_power() { + when : "B_MEN & B_WEN & B_REN"; + rise_power("scalar"){ + values (25.7036); + } + fall_power("scalar"){ + values (0); + } + } + internal_power() { + when : "B_MEN & !B_WEN & B_REN"; + rise_power("scalar"){ + values (19.5664); + } + fall_power("scalar"){ + values (0); + } + } + internal_power() { + when : "!B_MEN & !B_WEN & B_REN"; + rise_power("scalar"){ + values (0.3077); + } + fall_power("scalar"){ + values (0); + } + } + internal_power() { + when : "!B_MEN & B_WEN & B_REN"; + rise_power("scalar"){ + values (0.7640); + } + fall_power("scalar"){ + values (0); + } + } + internal_power() { + when : "B_MEN & !B_WEN & !B_REN"; + rise_power("scalar"){ + values (0); + } + fall_power("scalar"){ + values (0); + } + } + } + bus(B_DIN) { + bus_type : D_15_0; + direction : input ; + capacitance : 0.00461776 ; + memory_write() { + address : B_ADDR ; + clocked_on : B_CLK; + } + + max_transition : "0.476" ; + pin(B_DIN[15:0]) { + related_power_pin : VDD; + related_ground_pin : VSS; + internal_power() { + when : "B_MEN"; + rise_power("scalar"){ + values (0.0570); + } + fall_power("scalar"){ + values (0.0255); + } + } + internal_power() { + when : "!B_MEN"; + rise_power("scalar"){ + values (0.0603); + } + fall_power("scalar"){ + values (0.0244); + } + } + } + timing() { + timing_type : setup_rising; + related_pin : "B_CLK"; + when : "(B_WEN & B_MEN)"; + sdf_cond : "B_W_ACCESS"; + + rise_constraint("SIG2SRAM_constraint_template") { + index_1("0.0056,0.0232,0.0400,0.0728,0.1280,0.2440,0.4760"); + index_2("0.0056,0.0232,0.0400,0.0728,0.1280,0.2440,0.4760"); + values ("-0.3858,-0.3702,-0.3565,-0.3243,-0.2774,-0.1729,0.0185",\ +"-0.3908,-0.3752,-0.3615,-0.3293,-0.2824,-0.1779,0.0135",\ +"-0.3953,-0.3796,-0.3660,-0.3337,-0.2869,-0.1824,0.0090",\ +"-0.4044,-0.3887,-0.3751,-0.3428,-0.2960,-0.1915,-0.0001",\ +"-0.4116,-0.3960,-0.3823,-0.3501,-0.3032,-0.1987,-0.0073",\ +"-0.4417,-0.4261,-0.4124,-0.3802,-0.3333,-0.2288,-0.0374",\ +"-0.4993,-0.4837,-0.4700,-0.4378,-0.3909,-0.2864,-0.0950"); + } + + fall_constraint("SIG2SRAM_constraint_template") { + index_1("0.0056,0.0232,0.0400,0.0728,0.1280,0.2440,0.4760"); + index_2("0.0056,0.0232,0.0400,0.0728,0.1280,0.2440,0.4760"); + values ("-0.3477,-0.3330,-0.3194,-0.2910,-0.2403,-0.1426,0.0400",\ +"-0.3527,-0.3380,-0.3244,-0.2961,-0.2453,-0.1476,0.0350",\ +"-0.3572,-0.3425,-0.3288,-0.3005,-0.2497,-0.1521,0.0305",\ +"-0.3663,-0.3516,-0.3379,-0.3096,-0.2588,-0.1612,0.0214",\ +"-0.3735,-0.3589,-0.3452,-0.3169,-0.2661,-0.1685,0.0142",\ +"-0.4036,-0.3890,-0.3753,-0.3470,-0.2962,-0.1985,-0.0159",\ +"-0.4612,-0.4466,-0.4329,-0.4046,-0.3538,-0.2561,-0.0735"); + } + } + + timing() { + timing_type : hold_rising; + related_pin : "B_CLK"; + when : "(B_WEN & B_MEN)"; + sdf_cond : "B_W_ACCESS"; + + rise_constraint("SIG2SRAM_constraint_template") { + index_1("0.0056,0.0232,0.0400,0.0728,0.1280,0.2440,0.4760"); + index_2("0.0056,0.0232,0.0400,0.0728,0.1280,0.2440,0.4760"); + values ("0.4953,0.4787,0.4660,0.4337,0.3859,0.2824,0.0900",\ +"0.5003,0.4837,0.4710,0.4387,0.3909,0.2874,0.0950",\ +"0.5048,0.4881,0.4755,0.4432,0.3954,0.2919,0.0995",\ +"0.5139,0.4972,0.4846,0.4523,0.4045,0.3010,0.1086",\ +"0.5211,0.5045,0.4918,0.4596,0.4117,0.3082,0.1158",\ +"0.5512,0.5346,0.5219,0.4897,0.4418,0.3383,0.1459",\ +"0.6088,0.5922,0.5795,0.5473,0.4994,0.3959,0.2035"); + } + + fall_constraint("SIG2SRAM_constraint_template") { + index_1("0.0056,0.0232,0.0400,0.0728,0.1280,0.2440,0.4760"); + index_2("0.0056,0.0232,0.0400,0.0728,0.1280,0.2440,0.4760"); + values ("0.4494,0.4347,0.4210,0.3927,0.3429,0.2502,0.0656",\ +"0.4544,0.4397,0.4261,0.3977,0.3479,0.2552,0.0706",\ +"0.4589,0.4442,0.4305,0.4022,0.3524,0.2596,0.0751",\ +"0.4679,0.4533,0.4396,0.4113,0.3615,0.2687,0.0842",\ +"0.4752,0.4606,0.4469,0.4186,0.3688,0.2760,0.0914",\ +"0.5053,0.4906,0.4770,0.4487,0.3989,0.3061,0.1215",\ +"0.5629,0.5483,0.5346,0.5063,0.4565,0.3637,0.1791"); + } + } + } + + pin(B_BIST_EN) { + direction : input ; + capacitance : 0.00401111 ; + max_transition : "1" ; + related_power_pin : VDD; + related_ground_pin : VSS; + internal_power() { + rise_power("scalar") { + values (0); + } + fall_power("scalar") { + values (0); + } + } + } + +bus(B_BIST_ADDR) { + bus_type : A_8_0; + direction : input ; + capacitance : 0.0121077 ; + pin(B_BIST_ADDR[0]) { + capacitance : 0.00570093 ; + } + pin(B_BIST_ADDR[1]) { + capacitance : 0.00764555 ; + } + pin(B_BIST_ADDR[2]) { + capacitance : 0.0105375 ; + } + pin(B_BIST_ADDR[3]) { + capacitance : 0.0067894 ; + } + pin(B_BIST_ADDR[4]) { + capacitance : 0.00630967 ; + } + pin(B_BIST_ADDR[5]) { + capacitance : 0.0104132 ; + } + pin(B_BIST_ADDR[6]) { + capacitance : 0.0131402 ; + } + pin(B_BIST_ADDR[7]) { + capacitance : 0.0105203 ; + } + max_transition : "0.476" ; + pin(B_BIST_ADDR[8:0]) { + related_power_pin : VDD; + related_ground_pin : VSS; + internal_power() { + when : "B_BIST_MEN"; + rise_power("scalar"){ + values (0.0110); + } + fall_power("scalar"){ + values (0.0056); + } + } + internal_power() { + when : "!B_BIST_MEN"; + rise_power("scalar"){ + values (0.0168); + } + fall_power("scalar"){ + values (0.0004); + } + } + } + timing() { + timing_type : setup_rising; + related_pin : "B_BIST_CLK"; + when : "((B_BIST_WEN | B_BIST_REN)& B_BIST_MEN)" + sdf_cond : "B_BIST_RW_ACCESS" + + rise_constraint("SIG2SRAM_constraint_template") { + index_1("0.0056,0.0232,0.0400,0.0728,0.1280,0.2440,0.4760"); + index_2("0.0056,0.0232,0.0400,0.0728,0.1280,0.2440,0.4760"); + values ("-0.4168,-0.3973,-0.3855,-0.3543,-0.3074,-0.2020,-0.0027",\ +"-0.4324,-0.4129,-0.4012,-0.3699,-0.3191,-0.2176,-0.0184",\ +"-0.4441,-0.4285,-0.4129,-0.3816,-0.3309,-0.2293,-0.0301",\ +"-0.4793,-0.4598,-0.4441,-0.4129,-0.3660,-0.2645,-0.0652",\ +"-0.5223,-0.5066,-0.4910,-0.4598,-0.4129,-0.3074,-0.1121",\ +"-0.6199,-0.6082,-0.5926,-0.5613,-0.5145,-0.4129,-0.2137",\ +"-0.8191,-0.8074,-0.7840,-0.7566,-0.7098,-0.6082,-0.4051"); + } + + fall_constraint("SIG2SRAM_constraint_template") { + index_1("0.0056,0.0232,0.0400,0.0728,0.1280,0.2440,0.4760"); + index_2("0.0056,0.0232,0.0400,0.0728,0.1280,0.2440,0.4760"); + values ("-0.3309,-0.3113,-0.2996,-0.2684,-0.2176,-0.1238,0.0637",\ +"-0.3465,-0.3309,-0.3152,-0.2840,-0.2332,-0.1395,0.0480",\ +"-0.3582,-0.3426,-0.3270,-0.2996,-0.2488,-0.1512,0.0324",\ +"-0.3895,-0.3738,-0.3582,-0.3309,-0.2801,-0.1863,0.0051",\ +"-0.4363,-0.4207,-0.4051,-0.3777,-0.3230,-0.2293,-0.0379",\ +"-0.5379,-0.5223,-0.5066,-0.4793,-0.4285,-0.3309,-0.1434",\ +"-0.7332,-0.7176,-0.7020,-0.6746,-0.6238,-0.5262,-0.3387"); + } + } + + + timing() { + timing_type : hold_rising; + related_pin : "B_BIST_CLK"; + when : "((B_BIST_WEN | B_BIST_REN)& B_BIST_MEN)" + sdf_cond : "B_BIST_RW_ACCESS" + + rise_constraint("SIG2SRAM_constraint_template") { + index_1("0.0056,0.0232,0.0400,0.0728,0.1280,0.2440,0.4760"); + index_2("0.0056,0.0232,0.0400,0.0728,0.1280,0.2440,0.4760"); + values ("0.5246,0.5051,0.4895,0.4582,0.4113,0.3059,0.1066",\ +"0.5402,0.5207,0.5051,0.4777,0.4270,0.3215,0.1223",\ +"0.5520,0.5324,0.5168,0.4895,0.4387,0.3371,0.1340",\ +"0.5832,0.5676,0.5520,0.5207,0.4738,0.3684,0.1691",\ +"0.6301,0.6105,0.5949,0.5676,0.5168,0.4113,0.2160",\ +"0.7316,0.7121,0.7004,0.6691,0.6223,0.5168,0.3176",\ +"0.9270,0.9230,0.8957,0.8645,0.8137,0.7121,0.5168"); + } + + fall_constraint("SIG2SRAM_constraint_template") { + index_1("0.0056,0.0232,0.0400,0.0728,0.1280,0.2440,0.4760"); + index_2("0.0056,0.0232,0.0400,0.0728,0.1280,0.2440,0.4760"); + values ("0.4309,0.4152,0.4035,0.3684,0.3215,0.2277,0.0363",\ +"0.4465,0.4309,0.4152,0.3879,0.3371,0.2395,0.0559",\ +"0.4582,0.4426,0.4309,0.3996,0.3488,0.2551,0.0715",\ +"0.4934,0.4777,0.4621,0.4348,0.3840,0.2863,0.0988",\ +"0.5363,0.5207,0.5051,0.4777,0.4270,0.3332,0.1418",\ +"0.6379,0.6262,0.6105,0.5793,0.5324,0.4348,0.2434",\ +"0.8332,0.8215,0.8059,0.7707,0.7238,0.6301,0.4387"); + } + } +} +pin(B_BIST_WEN) { + direction : input ; + capacitance : 0.00324098 ; + max_transition : "0.476" ; + related_power_pin : VDD; + related_ground_pin : VSS; + internal_power() { + when : "B_BIST_MEN"; + rise_power("scalar"){ + values (0.0046); + } + fall_power("scalar"){ + values (0.0039); + } + } + internal_power() { + when : "!B_BIST_MEN"; + rise_power("scalar"){ + values (0.0043); + } + fall_power("scalar"){ + values (0.0040); + } + } + timing() { + timing_type : setup_rising; + related_pin : "B_BIST_CLK"; + when : "B_BIST_MEN" + sdf_cond : "B_BIST_MEN" + + rise_constraint("SIG2SRAM_constraint_template") { + index_1("0.0056,0.0232,0.0400,0.0728,0.1280,0.2440,0.4760"); + index_2("0.0056,0.0232,0.0400,0.0728,0.1280,0.2440,0.4760"); + values ("0.2043,0.2199,0.2316,0.2629,0.3059,0.4113,0.6066",\ +"0.1887,0.2043,0.2160,0.2473,0.2941,0.3957,0.5949",\ +"0.1691,0.1848,0.2004,0.2316,0.2785,0.3801,0.5754",\ +"0.1379,0.1574,0.1691,0.2004,0.2473,0.3527,0.5480",\ +"0.0910,0.1066,0.1223,0.1535,0.2004,0.2980,0.4973",\ +"-0.0105,0.0051,0.0207,0.0520,0.0949,0.2004,0.3957",\ +"-0.2059,-0.1902,-0.1746,-0.1473,-0.1004,0.0051,0.2004"); + } + + fall_constraint("SIG2SRAM_constraint_template") { + index_1("0.0056,0.0232,0.0400,0.0728,0.1280,0.2440,0.4760"); + index_2("0.0056,0.0232,0.0400,0.0728,0.1280,0.2440,0.4760"); + values ("0.2941,0.3098,0.3215,0.3488,0.4035,0.4973,0.6887",\ +"0.2785,0.2941,0.3059,0.3332,0.3840,0.4816,0.6691",\ +"0.2629,0.2785,0.2902,0.3176,0.3684,0.4660,0.6535",\ +"0.2316,0.2473,0.2590,0.2863,0.3410,0.4348,0.6262",\ +"0.1848,0.2004,0.2121,0.2395,0.2902,0.3879,0.5754",\ +"0.0832,0.0988,0.1105,0.1379,0.1809,0.2746,0.4699",\ +"-0.1121,-0.0965,-0.0848,-0.0535,-0.0066,0.0910,0.2824"); + } + } + + + timing() { + timing_type : hold_rising; + related_pin : "B_BIST_CLK"; + when : "B_BIST_MEN" + sdf_cond : "B_BIST_MEN" + + rise_constraint("SIG2SRAM_constraint_template") { + index_1("0.0056,0.0232,0.0400,0.0728,0.1280,0.2440,0.4760"); + index_2("0.0056,0.0232,0.0400,0.0728,0.1280,0.2440,0.4760"); + values ("0.2473,0.2316,0.2160,0.1887,0.1379,0.0363,-0.1629",\ +"0.2629,0.2473,0.2316,0.2043,0.1535,0.0520,-0.1473",\ +"0.2785,0.2590,0.2434,0.2160,0.1652,0.0676,-0.1355",\ +"0.3098,0.2941,0.2785,0.2473,0.1965,0.0910,-0.1043",\ +"0.3527,0.3371,0.3215,0.2941,0.2434,0.1418,-0.0574",\ +"0.4582,0.4426,0.4270,0.3957,0.3488,0.2434,0.0480",\ +"0.6535,0.6379,0.6184,0.5910,0.5402,0.4426,0.2434"); + } + + fall_constraint("SIG2SRAM_constraint_template") { + index_1("0.0056,0.0232,0.0400,0.0728,0.1280,0.2440,0.4760"); + index_2("0.0056,0.0232,0.0400,0.0728,0.1280,0.2440,0.4760"); + values ("0.2395,0.2238,0.2121,0.1809,0.1301,0.0324,-0.1551",\ +"0.2551,0.2395,0.2277,0.1965,0.1457,0.0480,-0.1395",\ +"0.2668,0.2551,0.2395,0.2082,0.1574,0.0637,-0.1277",\ +"0.3020,0.2863,0.2707,0.2395,0.1887,0.0910,-0.0965",\ +"0.3449,0.3293,0.3176,0.2863,0.2355,0.1379,-0.0496",\ +"0.4504,0.4348,0.4191,0.3879,0.3371,0.2395,0.0559",\ +"0.6457,0.6301,0.6145,0.5871,0.5324,0.4309,0.2512"); + } + } + } +pin(B_BIST_REN) { + direction : input ; + capacitance : 0.00381634 ; + max_transition : "0.476" ; + related_power_pin : VDD; + related_ground_pin : VSS; + internal_power() { + when : "B_BIST_MEN"; + rise_power("scalar"){ + values (0.0061); + } + fall_power("scalar"){ + values (0.0021); + } + } + internal_power() { + when : "!B_BIST_MEN"; + rise_power("scalar"){ + values (0.0062); + } + fall_power("scalar"){ + values (0.0025); + } + } + timing() { + timing_type : setup_rising; + related_pin : "B_BIST_CLK"; + when : "B_BIST_MEN" + sdf_cond : "B_BIST_MEN" + + rise_constraint("SIG2SRAM_constraint_template") { + index_1("0.0056,0.0232,0.0400,0.0728,0.1280,0.2440,0.4760"); + index_2("0.0056,0.0232,0.0400,0.0728,0.1280,0.2440,0.4760"); + values ("-0.0301,-0.0145,0.0012,0.0324,0.0793,0.1809,0.3762",\ +"-0.0457,-0.0301,-0.0145,0.0168,0.0637,0.1613,0.3605",\ +"-0.0574,-0.0418,-0.0262,0.0051,0.0520,0.1496,0.3449",\ +"-0.0926,-0.0730,-0.0574,-0.0262,0.0207,0.1184,0.3137",\ +"-0.1395,-0.1238,-0.1082,-0.0770,-0.0301,0.0715,0.2707",\ +"-0.2410,-0.2254,-0.2098,-0.1746,-0.1355,-0.0340,0.1652",\ +"-0.4402,-0.4207,-0.4051,-0.3738,-0.3270,-0.2293,-0.0340"); + } + + fall_constraint("SIG2SRAM_constraint_template") { + index_1("0.0056,0.0232,0.0400,0.0728,0.1280,0.2440,0.4760"); + index_2("0.0056,0.0232,0.0400,0.0728,0.1280,0.2440,0.4760"); + values ("0.0988,0.1145,0.1262,0.1535,0.2043,0.3020,0.4855",\ +"0.0832,0.0988,0.1105,0.1418,0.1848,0.2824,0.4738",\ +"0.0676,0.0832,0.0949,0.1262,0.1730,0.2668,0.4621",\ +"0.0402,0.0559,0.0676,0.0988,0.1457,0.2434,0.4191",\ +"-0.0105,0.0012,0.0168,0.0480,0.0988,0.1965,0.3840",\ +"-0.1160,-0.0965,-0.0848,-0.0535,-0.0066,0.0988,0.2824",\ +"-0.3113,-0.2957,-0.2801,-0.2527,-0.2059,-0.1043,0.0832"); + } + } + + + timing() { + timing_type : hold_rising; + related_pin : "B_BIST_CLK"; + when : "B_BIST_MEN" + sdf_cond : "B_BIST_MEN" + + rise_constraint("SIG2SRAM_constraint_template") { + index_1("0.0056,0.0232,0.0400,0.0728,0.1280,0.2440,0.4760"); + index_2("0.0056,0.0232,0.0400,0.0728,0.1280,0.2440,0.4760"); + values ("0.2707,0.2551,0.2395,0.2121,0.1613,0.0598,-0.1395",\ +"0.2863,0.2707,0.2551,0.2238,0.1730,0.0715,-0.1238",\ +"0.2980,0.2824,0.2668,0.2395,0.1887,0.0871,-0.1121",\ +"0.3332,0.3176,0.3020,0.2707,0.2199,0.1184,-0.0809",\ +"0.3762,0.3605,0.3449,0.3176,0.2668,0.1613,-0.0340",\ +"0.4816,0.4621,0.4504,0.4191,0.3723,0.2629,0.0715",\ +"0.6770,0.6613,0.6418,0.6184,0.5637,0.4699,0.2629"); + } + + fall_constraint("SIG2SRAM_constraint_template") { + index_1("0.0056,0.0232,0.0400,0.0728,0.1280,0.2440,0.4760"); + index_2("0.0056,0.0232,0.0400,0.0728,0.1280,0.2440,0.4760"); + values ("0.2590,0.2434,0.2316,0.2004,0.1457,0.0520,-0.1355",\ +"0.2746,0.2590,0.2434,0.2160,0.1613,0.0676,-0.1199",\ +"0.2863,0.2707,0.2590,0.2277,0.1730,0.0832,-0.1082",\ +"0.3215,0.3059,0.2902,0.2590,0.2082,0.1105,-0.0770",\ +"0.3645,0.3488,0.3332,0.3059,0.2551,0.1535,-0.0340",\ +"0.4699,0.4543,0.4387,0.4074,0.3605,0.2551,0.0715",\ +"0.6652,0.6496,0.6340,0.6027,0.5520,0.4621,0.2707"); + } + } + } +pin(B_BIST_MEN) { + direction : input ; + capacitance : 0.00309605 ; + max_transition : "0.476" ; + related_power_pin : VDD; + related_ground_pin : VSS; + internal_power() { + rise_power("scalar"){ + values (0.0449); + } + fall_power("scalar"){ + values (0.0052); + } + } + timing() { + timing_type : setup_rising; + related_pin : "B_BIST_CLK"; + + rise_constraint("SIG2SRAM_constraint_template") { + index_1("0.0056,0.0232,0.0400,0.0728,0.1280,0.2440,0.4760"); + index_2("0.0056,0.0232,0.0400,0.0728,0.1280,0.2440,0.4760"); + values ("0.2043,0.2199,0.2316,0.2668,0.3098,0.4152,0.6066",\ +"0.1887,0.2043,0.2199,0.2512,0.2941,0.3996,0.5949",\ +"0.1730,0.1887,0.2043,0.2355,0.2824,0.3840,0.5793",\ +"0.1418,0.1574,0.1730,0.2043,0.2512,0.3566,0.5480",\ +"0.0949,0.1105,0.1262,0.1574,0.2043,0.3020,0.5051",\ +"-0.0066,0.0090,0.0246,0.0520,0.0988,0.2043,0.3996",\ +"-0.2020,-0.1863,-0.1746,-0.1434,-0.0965,0.0090,0.2082"); + } + + fall_constraint("SIG2SRAM_constraint_template") { + index_1("0.0056,0.0232,0.0400,0.0728,0.1280,0.2440,0.4760"); + index_2("0.0056,0.0232,0.0400,0.0728,0.1280,0.2440,0.4760"); + values ("0.2980,0.3137,0.3254,0.3527,0.4035,0.5012,0.6887",\ +"0.2824,0.2980,0.3098,0.3371,0.3879,0.4855,0.6730",\ +"0.2668,0.2824,0.2941,0.3215,0.3723,0.4699,0.6574",\ +"0.2355,0.2473,0.2629,0.2902,0.3410,0.4387,0.6262",\ +"0.1887,0.2004,0.2160,0.2395,0.2941,0.3918,0.5793",\ +"0.0871,0.1027,0.1145,0.1418,0.1848,0.2746,0.4816",\ +"-0.1082,-0.0965,-0.0809,-0.0496,-0.0027,0.0949,0.2863"); + } + } + + + timing() { + timing_type : hold_rising; + related_pin : "B_BIST_CLK"; + + rise_constraint("SIG2SRAM_constraint_template") { + index_1("0.0056,0.0232,0.0400,0.0728,0.1280,0.2440,0.4760"); + index_2("0.0056,0.0232,0.0400,0.0728,0.1280,0.2440,0.4760"); + values ("0.2512,0.2355,0.2199,0.1926,0.1418,0.0402,-0.1590",\ +"0.2668,0.2512,0.2355,0.2082,0.1574,0.0559,-0.1434",\ +"0.2824,0.2629,0.2512,0.2199,0.1691,0.0715,-0.1316",\ +"0.3137,0.2980,0.2824,0.2512,0.2004,0.0988,-0.0965",\ +"0.3566,0.3410,0.3254,0.2980,0.2473,0.1418,-0.0535",\ +"0.4621,0.4426,0.4309,0.3996,0.3527,0.2473,0.0520",\ +"0.6574,0.6418,0.6262,0.5949,0.5441,0.4465,0.2473"); + } + + fall_constraint("SIG2SRAM_constraint_template") { + index_1("0.0056,0.0232,0.0400,0.0728,0.1280,0.2440,0.4760"); + index_2("0.0056,0.0232,0.0400,0.0728,0.1280,0.2440,0.4760"); + values ("0.2395,0.2238,0.2121,0.1809,0.1301,0.0324,-0.1551",\ +"0.2551,0.2434,0.2277,0.1965,0.1457,0.0480,-0.1395",\ +"0.2707,0.2551,0.2395,0.2082,0.1574,0.0637,-0.1277",\ +"0.3020,0.2863,0.2707,0.2434,0.1926,0.0910,-0.0965",\ +"0.3449,0.3332,0.3176,0.2863,0.2355,0.1379,-0.0496",\ +"0.4504,0.4348,0.4230,0.3918,0.3410,0.2434,0.0559",\ +"0.6457,0.6301,0.6145,0.5910,0.5324,0.4387,0.2512"); + } + } + } +bus(B_BIST_BM) { + bus_type : D_15_0; + direction : input ; + capacitance : 0.00275526 ; + max_transition : "0.476" ; + pin(B_BIST_BM[15:0]) { + related_power_pin : VDD; + related_ground_pin : VSS; + internal_power() { + when : "B_BIST_MEN"; + rise_power("scalar"){ + values (0.0570); + } + fall_power("scalar"){ + values (0.0255); + } + } + internal_power() { + when : "!B_BIST_MEN"; + rise_power("scalar"){ + values (0.0603); + } + fall_power("scalar"){ + values (0.0244); + } + } + } + timing() { + timing_type : setup_rising; + related_pin : "B_BIST_CLK"; + when : "(B_BIST_WEN & B_BIST_MEN)" + sdf_cond : "B_BIST_RW_ACCESS" + + rise_constraint("SIG2SRAM_constraint_template") { + index_1("0.0056,0.0232,0.0400,0.0728,0.1280,0.2440,0.4760"); + index_2("0.0056,0.0232,0.0400,0.0728,0.1280,0.2440,0.4760"); + values ("-0.3858,-0.3702,-0.3565,-0.3243,-0.2774,-0.1729,0.0185",\ +"-0.3908,-0.3752,-0.3615,-0.3293,-0.2824,-0.1779,0.0135",\ +"-0.3953,-0.3796,-0.3660,-0.3337,-0.2869,-0.1824,0.0090",\ +"-0.4044,-0.3887,-0.3751,-0.3428,-0.2960,-0.1915,-0.0001",\ +"-0.4116,-0.3960,-0.3823,-0.3501,-0.3032,-0.1987,-0.0073",\ +"-0.4417,-0.4261,-0.4124,-0.3802,-0.3333,-0.2288,-0.0374",\ +"-0.4993,-0.4837,-0.4700,-0.4378,-0.3909,-0.2864,-0.0950"); + } + + fall_constraint("SIG2SRAM_constraint_template") { + index_1("0.0056,0.0232,0.0400,0.0728,0.1280,0.2440,0.4760"); + index_2("0.0056,0.0232,0.0400,0.0728,0.1280,0.2440,0.4760"); + values ("-0.3477,-0.3330,-0.3194,-0.2910,-0.2403,-0.1426,0.0400",\ +"-0.3527,-0.3380,-0.3244,-0.2961,-0.2453,-0.1476,0.0350",\ +"-0.3572,-0.3425,-0.3288,-0.3005,-0.2497,-0.1521,0.0305",\ +"-0.3663,-0.3516,-0.3379,-0.3096,-0.2588,-0.1612,0.0214",\ +"-0.3735,-0.3589,-0.3452,-0.3169,-0.2661,-0.1685,0.0142",\ +"-0.4036,-0.3890,-0.3753,-0.3470,-0.2962,-0.1985,-0.0159",\ +"-0.4612,-0.4466,-0.4329,-0.4046,-0.3538,-0.2561,-0.0735"); + } + } + + + timing() { + timing_type : hold_rising; + related_pin : "B_BIST_CLK"; + when : "(B_BIST_WEN & B_BIST_MEN)" + sdf_cond : "B_BIST_RW_ACCESS" + + rise_constraint("SIG2SRAM_constraint_template") { + index_1("0.0056,0.0232,0.0400,0.0728,0.1280,0.2440,0.4760"); + index_2("0.0056,0.0232,0.0400,0.0728,0.1280,0.2440,0.4760"); + values ("0.4953,0.4787,0.4660,0.4337,0.3859,0.2824,0.0900",\ +"0.5003,0.4837,0.4710,0.4387,0.3909,0.2874,0.0950",\ +"0.5048,0.4881,0.4755,0.4432,0.3954,0.2919,0.0995",\ +"0.5139,0.4972,0.4846,0.4523,0.4045,0.3010,0.1086",\ +"0.5211,0.5045,0.4918,0.4596,0.4117,0.3082,0.1158",\ +"0.5512,0.5346,0.5219,0.4897,0.4418,0.3383,0.1459",\ +"0.6088,0.5922,0.5795,0.5473,0.4994,0.3959,0.2035"); + } + + fall_constraint("SIG2SRAM_constraint_template") { + index_1("0.0056,0.0232,0.0400,0.0728,0.1280,0.2440,0.4760"); + index_2("0.0056,0.0232,0.0400,0.0728,0.1280,0.2440,0.4760"); + values ("0.4494,0.4347,0.4210,0.3927,0.3429,0.2502,0.0656",\ +"0.4544,0.4397,0.4261,0.3977,0.3479,0.2552,0.0706",\ +"0.4589,0.4442,0.4305,0.4022,0.3524,0.2596,0.0751",\ +"0.4679,0.4533,0.4396,0.4113,0.3615,0.2687,0.0842",\ +"0.4752,0.4606,0.4469,0.4186,0.3688,0.2760,0.0914",\ +"0.5053,0.4906,0.4770,0.4487,0.3989,0.3061,0.1215",\ +"0.5629,0.5483,0.5346,0.5063,0.4565,0.3637,0.1791"); + } + } +} + pin(B_BIST_CLK) { + direction : input; + capacitance : 0.00380014; + max_transition : "0.476"; + clock : "true" ; + pin_func_type : active_rising ; + + timing () { + timing_type : "min_pulse_width"; + related_pin : "B_BIST_CLK"; + rise_constraint("CLKTRAN_constraint_template") { + index_1("0.0056,0.476"); + values("0.21,0.21"); + } + } + + related_power_pin : VDD; + related_ground_pin : VSS; + + internal_power() { + when : "!B_BIST_MEN & !B_BIST_WEN & !B_BIST_REN"; + rise_power("scalar"){ + values (0); + } + fall_power("scalar"){ + values (0); + } + } + internal_power() { + when : "!B_BIST_MEN & B_BIST_WEN & !B_BIST_REN"; + rise_power("scalar"){ + values (0.5315); + } + fall_power("scalar"){ + values (0); + } + } + internal_power() { + when : "B_BIST_MEN & B_BIST_WEN & !B_BIST_REN"; + rise_power("scalar"){ + values (23.4667); + } + fall_power("scalar"){ + values (0); + } + } + internal_power() { + when : "B_BIST_MEN & B_BIST_WEN & B_BIST_REN"; + rise_power("scalar"){ + values (25.7036); + } + fall_power("scalar"){ + values (0); + } + } + internal_power() { + when : "B_BIST_MEN & !B_BIST_WEN & B_BIST_REN"; + rise_power("scalar"){ + values (19.5664); + } + fall_power("scalar"){ + values (0); + } + } + internal_power() { + when : "!B_BIST_MEN & !B_BIST_WEN & B_BIST_REN"; + rise_power("scalar"){ + values (0.3077); + } + fall_power("scalar"){ + values (0); + } + } + internal_power() { + when : "!B_BIST_MEN & B_BIST_WEN & B_BIST_REN"; + rise_power("scalar"){ + values (0.7640); + } + fall_power("scalar"){ + values (0); + } + } + internal_power() { + when : "B_BIST_MEN & !B_BIST_WEN & !B_BIST_REN"; + rise_power("scalar"){ + values (0); + } + fall_power("scalar"){ + values (0); + } + } + } + bus(B_BIST_DIN) { + bus_type : D_15_0; + direction : input ; + capacitance : 0.00414348 ; + memory_write() { + address : B_BIST_ADDR ; + clocked_on : B_BIST_CLK; + } + + max_transition : "0.476" ; + pin(B_BIST_DIN[15:0]) { + related_power_pin : VDD; + related_ground_pin : VSS; + internal_power() { + when : "B_BIST_MEN"; + rise_power("scalar"){ + values (0.0570); + } + fall_power("scalar"){ + values (0.0255); + } + } + internal_power() { + when : "!B_BIST_MEN"; + rise_power("scalar"){ + values (0.0603); + } + fall_power("scalar"){ + values (0.0244); + } + } + } + timing() { + timing_type : setup_rising; + related_pin : "B_BIST_CLK"; + when : "(B_BIST_WEN & B_BIST_MEN)"; + sdf_cond : "B_BIST_W_ACCESS"; + + rise_constraint("SIG2SRAM_constraint_template") { + index_1("0.0056,0.0232,0.0400,0.0728,0.1280,0.2440,0.4760"); + index_2("0.0056,0.0232,0.0400,0.0728,0.1280,0.2440,0.4760"); + values ("-0.3858,-0.3702,-0.3565,-0.3243,-0.2774,-0.1729,0.0185",\ +"-0.3908,-0.3752,-0.3615,-0.3293,-0.2824,-0.1779,0.0135",\ +"-0.3953,-0.3796,-0.3660,-0.3337,-0.2869,-0.1824,0.0090",\ +"-0.4044,-0.3887,-0.3751,-0.3428,-0.2960,-0.1915,-0.0001",\ +"-0.4116,-0.3960,-0.3823,-0.3501,-0.3032,-0.1987,-0.0073",\ +"-0.4417,-0.4261,-0.4124,-0.3802,-0.3333,-0.2288,-0.0374",\ +"-0.4993,-0.4837,-0.4700,-0.4378,-0.3909,-0.2864,-0.0950"); + } + + fall_constraint("SIG2SRAM_constraint_template") { + index_1("0.0056,0.0232,0.0400,0.0728,0.1280,0.2440,0.4760"); + index_2("0.0056,0.0232,0.0400,0.0728,0.1280,0.2440,0.4760"); + values ("-0.3477,-0.3330,-0.3194,-0.2910,-0.2403,-0.1426,0.0400",\ +"-0.3527,-0.3380,-0.3244,-0.2961,-0.2453,-0.1476,0.0350",\ +"-0.3572,-0.3425,-0.3288,-0.3005,-0.2497,-0.1521,0.0305",\ +"-0.3663,-0.3516,-0.3379,-0.3096,-0.2588,-0.1612,0.0214",\ +"-0.3735,-0.3589,-0.3452,-0.3169,-0.2661,-0.1685,0.0142",\ +"-0.4036,-0.3890,-0.3753,-0.3470,-0.2962,-0.1985,-0.0159",\ +"-0.4612,-0.4466,-0.4329,-0.4046,-0.3538,-0.2561,-0.0735"); + } + } + + timing() { + timing_type : hold_rising; + related_pin : "B_BIST_CLK"; + when : "(B_BIST_WEN & B_BIST_MEN)"; + sdf_cond : "B_BIST_W_ACCESS"; + + rise_constraint("SIG2SRAM_constraint_template") { + index_1("0.0056,0.0232,0.0400,0.0728,0.1280,0.2440,0.4760"); + index_2("0.0056,0.0232,0.0400,0.0728,0.1280,0.2440,0.4760"); + values ("0.4953,0.4787,0.4660,0.4337,0.3859,0.2824,0.0900",\ +"0.5003,0.4837,0.4710,0.4387,0.3909,0.2874,0.0950",\ +"0.5048,0.4881,0.4755,0.4432,0.3954,0.2919,0.0995",\ +"0.5139,0.4972,0.4846,0.4523,0.4045,0.3010,0.1086",\ +"0.5211,0.5045,0.4918,0.4596,0.4117,0.3082,0.1158",\ +"0.5512,0.5346,0.5219,0.4897,0.4418,0.3383,0.1459",\ +"0.6088,0.5922,0.5795,0.5473,0.4994,0.3959,0.2035"); + } + + fall_constraint("SIG2SRAM_constraint_template") { + index_1("0.0056,0.0232,0.0400,0.0728,0.1280,0.2440,0.4760"); + index_2("0.0056,0.0232,0.0400,0.0728,0.1280,0.2440,0.4760"); + values ("0.4494,0.4347,0.4210,0.3927,0.3429,0.2502,0.0656",\ +"0.4544,0.4397,0.4261,0.3977,0.3479,0.2552,0.0706",\ +"0.4589,0.4442,0.4305,0.4022,0.3524,0.2596,0.0751",\ +"0.4679,0.4533,0.4396,0.4113,0.3615,0.2687,0.0842",\ +"0.4752,0.4606,0.4469,0.4186,0.3688,0.2760,0.0914",\ +"0.5053,0.4906,0.4770,0.4487,0.3989,0.3061,0.1215",\ +"0.5629,0.5483,0.5346,0.5063,0.4565,0.3637,0.1791"); + } + } + } + +bus(B_DOUT) { + + bus_type : D_15_0; + direction : output ; + capacitance : 0 ; + max_capacitance : 0.064 ; + memory_read() { + address : B_ADDR ; + } + pin(B_DOUT[15:0]) { + related_power_pin : VDD; + related_ground_pin : VSS; + internal_power() { + rise_power("scalar") { + values (0); + } + fall_power("scalar") { + values (0); + } + } + } + timing() { + related_pin : "B_CLK"; + timing_type : rising_edge ; + timing_sense : non_unate ; + + cell_rise(SIG2SRAM_delay_template) { + index_1("0.0056,0.0232,0.0400,0.0728,0.1280,0.2440,0.4760"); + index_2("0.0008,0.0014,0.0051,0.0100,0.0339,0.0640"); + values ("3.7906,3.7922,3.7999,3.8086,3.8410,3.8771",\ +"3.7958,3.7974,3.8050,3.8137,3.8461,3.8823",\ +"3.7990,3.8006,3.8082,3.8169,3.8493,3.8855",\ +"3.8114,3.8131,3.8207,3.8294,3.8618,3.8979",\ +"3.8173,3.8189,3.8265,3.8352,3.8676,3.9038",\ +"3.8482,3.8499,3.8575,3.8662,3.8986,3.9347",\ +"3.9039,3.9056,3.9132,3.9219,3.9543,3.9904"); + } + cell_fall(SIG2SRAM_delay_template) { + index_1("0.0056,0.0232,0.0400,0.0728,0.1280,0.2440,0.4760"); + index_2("0.0008,0.0014,0.0051,0.0100,0.0339,0.0640"); + values ("3.7303,3.7317,3.7378,3.7449,3.7714,3.7976",\ +"3.7355,3.7368,3.7429,3.7500,3.7765,3.8028",\ +"3.7387,3.7400,3.7461,3.7532,3.7797,3.8060",\ +"3.7512,3.7525,3.7586,3.7657,3.7922,3.8184",\ +"3.7570,3.7583,3.7644,3.7715,3.7980,3.8243",\ +"3.7880,3.7893,3.7954,3.8025,3.8290,3.8552",\ +"3.8437,3.8450,3.8511,3.8582,3.8847,3.9109"); + } + + rise_transition(SRAM_load_template) { + index_1("0.0008,0.0014,0.0051,0.0100,0.0339,0.0640"); + values ("0.0326,0.0341,0.0428,0.0518,0.0923,0.1492"); + } + fall_transition(SRAM_load_template) { + index_1("0.0008,0.0014,0.0051,0.0100,0.0339,0.0640"); + values ("0.0254,0.0265,0.0335,0.0402,0.0707,0.1039"); + } + } +} +cell_leakage_power : 159.4504; +} +} diff --git a/flow/platforms/ihp-sg13g2/lib/RM_IHPSG13_2P_512x32_c2_bm_bist_fast_1p32V_m55C.lib b/flow/platforms/ihp-sg13g2/lib/RM_IHPSG13_2P_512x32_c2_bm_bist_fast_1p32V_m55C.lib new file mode 100644 index 0000000000..313f61729d --- /dev/null +++ b/flow/platforms/ihp-sg13g2/lib/RM_IHPSG13_2P_512x32_c2_bm_bist_fast_1p32V_m55C.lib @@ -0,0 +1,2886 @@ +/* ------------------------------------------------------*/ +/**/ +/* Copyright 2025 IHP PDK Authors*/ +/**/ +/* Licensed under the Apache License, Version 2.0 (the "License");*/ +/* you may not use this file except in compliance with the License.*/ +/* You may obtain a copy of the License at*/ +/* */ +/* https://www.apache.org/licenses/LICENSE-2.0*/ +/* */ +/* Unless required by applicable law or agreed to in writing, software*/ +/* distributed under the License is distributed on an "AS IS" BASIS,*/ +/* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.*/ +/* See the License for the specific language governing permissions and*/ +/* limitations under the License.*/ +/* */ +/* Generated on Wed Aug 27 13:11:28 2025 */ +/* */ +/* ------------------------------------------------------ */ +library(RM_IHPSG13_2P_512x32_c2_bm_bist_fast_1p32V_m55C) { + technology (cmos) ; + delay_model : table_lookup ; + define ("add_pg_pin_to_lib", "library", "boolean"); + add_pg_pin_to_lib : true; + voltage_map ( VDD, 1.32); + voltage_map ( VDDARRAY, 1.32); + voltage_map ( VSS, 0.000000 ); + + date : "Wed Aug 27 13:11:26 2025" ; + comment : "IHP Microelectronics GmbH, 2023" ; + revision : 1.0.0 ; + simulation : true ; + nom_process : 1 ; + nom_temperature : -55 ; + nom_voltage : 1.32 ; + + operating_conditions("fast_1p32V_m55C"){ + process : 1 ; + temperature : -55 ; + voltage : 1.32 ; + tree_type : "balanced_tree" ; + } + + default_operating_conditions : fast_1p32V_m55C ; + default_max_transition : 1.0 ; + default_fanout_load : 1.0 ; + default_inout_pin_cap : 0.0 ; + default_input_pin_cap : 0.0 ; + default_output_pin_cap : 0.0 ; + default_cell_leakage_power : 0.0 ; + default_leakage_power_density : 0.0 ; + + slew_lower_threshold_pct_rise : 30 ; + slew_upper_threshold_pct_rise : 70 ; + input_threshold_pct_fall : 50 ; + output_threshold_pct_fall : 50 ; + input_threshold_pct_rise : 50 ; + output_threshold_pct_rise : 50 ; + slew_lower_threshold_pct_fall : 30 ; + slew_upper_threshold_pct_fall : 70 ; + slew_derate_from_library : 0.5; + k_volt_cell_leakage_power : 0.0 ; + k_temp_cell_leakage_power : 0.0 ; + k_process_cell_leakage_power : 0.0 ; + k_volt_internal_power : 0.0 ; + k_temp_internal_power : 0.0 ; + k_process_internal_power : 0.0 ; + + capacitive_load_unit (1,pf) ; + voltage_unit : "1V" ; + current_unit : "1uA" ; + time_unit : "1ns" ; + leakage_power_unit : "1nW" ; + pulling_resistance_unit : "1kohm"; + /* + ------------------------------------------------------------------------------------------ + implicit units overview: + cell_area unit : "um" + internal_power unit : "1e-12 * J/toggle = 1 * uW/MHz" + (capacitive_load_unit * voltage_unit^2) per toggle event + ------------------------------------------------------------------------------------------ + */ + library_features(report_delay_calculation); + define_cell_area (pad_drivers,pad_driver_sites) ; + + lu_table_template(CLKTRAN_constraint_template) { + variable_1 : constrained_pin_transition; + index_1 ( "0.010, 0.050, 0.200, 0.400, 1.000" ); + } + lu_table_template(SRAM_load_template) { + variable_1 : total_output_net_capacitance; + index_1 ( "0.0008,0.0014,0.0051,0.0100,0.0339,0.0640" ); + } + lu_table_template(SIG2SRAM_constraint_template) { + variable_1 : related_pin_transition; + variable_2 : constrained_pin_transition; + index_1 ( "0.0040,0.0176,0.0344,0.0656,0.1120,0.2016,0.3800" ); + index_2 ( "0.0040,0.0176,0.0344,0.0656,0.1120,0.2016,0.3800" ); + } + + lu_table_template(SIG2SRAM_delay_template) { + variable_1 : input_net_transition; + variable_2 : total_output_net_capacitance; + index_1 ( "0.0040,0.0176,0.0344,0.0656,0.1120,0.2016,0.3800" ); + index_2 ( "0.0008,0.0014,0.0051,0.0100,0.0339,0.0640" ); + } + + type (D_31_0) { + base_type : array; + data_type : bit; + bit_width : 32; + bit_from : 31; + bit_to : 0; + downto : true; + } + + type (A_8_0) { + base_type : array; + data_type : bit; + bit_width : 9; + bit_from : 8; + bit_to : 0; + downto : true; + } + +cell(RM_IHPSG13_2P_512x32_c2_bm_bist) { +pg_pin (VDD) { + pg_type : primary_power; + voltage_name : VDD; +} +pg_pin (VDDARRAY) { + pg_type : primary_power; + voltage_name : VDDARRAY; +} +pg_pin (VSS) { + pg_type : primary_ground; + voltage_name : VSS; +} + +memory() { + type : ram; + address_width : 9; + word_width : 32; +} + +interface_timing : false; +bus_naming_style : "%s[%d]" ; +area : 150650.1373 ; + + pin(A_DLY) { + direction : input ; + capacitance : 0.00421562 ; + max_transition : "1" ; + related_power_pin : VDD; + related_ground_pin : VSS; + internal_power() { + rise_power("scalar") { + values (0); + } + fall_power("scalar") { + values (0); + } + } + } + +bus(A_ADDR) { + bus_type : A_8_0; + direction : input ; + capacitance : 0.0115194 ; + pin(A_ADDR[0]) { + capacitance : 0.00563454 ; + } + pin(A_ADDR[1]) { + capacitance : 0.00744185 ; + } + pin(A_ADDR[2]) { + capacitance : 0.0100611 ; + } + pin(A_ADDR[3]) { + capacitance : 0.00669965 ; + } + pin(A_ADDR[4]) { + capacitance : 0.00614331 ; + } + pin(A_ADDR[5]) { + capacitance : 0.0102172 ; + } + pin(A_ADDR[6]) { + capacitance : 0.0124225 ; + } + pin(A_ADDR[7]) { + capacitance : 0.010114 ; + } + max_transition : "0.38" ; + pin(A_ADDR[8:0]) { + related_power_pin : VDD; + related_ground_pin : VSS; + internal_power() { + when : "A_MEN"; + rise_power("scalar"){ + values (0.0115); + } + fall_power("scalar"){ + values (0.0021); + } + } + internal_power() { + when : "!A_MEN"; + rise_power("scalar"){ + values (0.0343); + } + fall_power("scalar"){ + values (0.0003); + } + } + } + timing() { + timing_type : setup_rising; + related_pin : "A_CLK"; + when : "((A_WEN | A_REN)& A_MEN)" + sdf_cond : "A_RW_ACCESS" + + rise_constraint("SIG2SRAM_constraint_template") { + index_1("0.0040,0.0176,0.0344,0.0656,0.1120,0.2016,0.3800"); + index_2("0.0040,0.0176,0.0344,0.0656,0.1120,0.2016,0.3800"); + values ("-0.2371,-0.2215,-0.2098,-0.1824,-0.1434,-0.0691,0.0676",\ +"-0.2449,-0.2332,-0.2176,-0.1902,-0.1551,-0.0770,0.0559",\ +"-0.2605,-0.2488,-0.2332,-0.2059,-0.1707,-0.0965,0.0441",\ +"-0.2879,-0.2723,-0.2605,-0.2332,-0.1941,-0.1199,0.0168",\ +"-0.3230,-0.3113,-0.2996,-0.2723,-0.2332,-0.1590,-0.0184",\ +"-0.4012,-0.3895,-0.3738,-0.3465,-0.3074,-0.2332,-0.0965",\ +"-0.5379,-0.5262,-0.5105,-0.4832,-0.4480,-0.3699,-0.2332"); + } + + fall_constraint("SIG2SRAM_constraint_template") { + index_1("0.0040,0.0176,0.0344,0.0656,0.1120,0.2016,0.3800"); + index_2("0.0040,0.0176,0.0344,0.0656,0.1120,0.2016,0.3800"); + values ("-0.1785,-0.1707,-0.1551,-0.1277,-0.0887,-0.0184,0.1145",\ +"-0.1902,-0.1785,-0.1629,-0.1355,-0.1004,-0.0262,0.1027",\ +"-0.2059,-0.1941,-0.1785,-0.1512,-0.1160,-0.0418,0.0871",\ +"-0.2293,-0.2176,-0.2059,-0.1785,-0.1434,-0.0691,0.0598",\ +"-0.2684,-0.2566,-0.2449,-0.2176,-0.1824,-0.1082,0.0207",\ +"-0.3465,-0.3348,-0.3191,-0.2918,-0.2566,-0.1824,-0.0535",\ +"-0.4832,-0.4715,-0.4559,-0.4324,-0.3934,-0.3191,-0.1902"); + } + } + + + timing() { + timing_type : hold_rising; + related_pin : "A_CLK"; + when : "((A_WEN | A_REN)& A_MEN)" + sdf_cond : "A_RW_ACCESS" + + rise_constraint("SIG2SRAM_constraint_template") { + index_1("0.0040,0.0176,0.0344,0.0656,0.1120,0.2016,0.3800"); + index_2("0.0040,0.0176,0.0344,0.0656,0.1120,0.2016,0.3800"); + values ("0.3410,0.3293,0.3137,0.2863,0.2473,0.1730,0.0324",\ +"0.3488,0.3371,0.3215,0.2941,0.2590,0.1809,0.0480",\ +"0.3684,0.3527,0.3371,0.3098,0.2746,0.1965,0.0598",\ +"0.3918,0.3762,0.3645,0.3371,0.2980,0.2238,0.0871",\ +"0.4309,0.4152,0.4035,0.3762,0.3371,0.2629,0.1223",\ +"0.5051,0.4934,0.4777,0.4504,0.4113,0.3371,0.1965",\ +"0.6418,0.6262,0.6145,0.5871,0.5520,0.4738,0.3332"); + } + + fall_constraint("SIG2SRAM_constraint_template") { + index_1("0.0040,0.0176,0.0344,0.0656,0.1120,0.2016,0.3800"); + index_2("0.0040,0.0176,0.0344,0.0656,0.1120,0.2016,0.3800"); + values ("0.2824,0.2707,0.2551,0.2277,0.1926,0.1184,-0.0105",\ +"0.2902,0.2785,0.2668,0.2395,0.2043,0.1301,0.0012",\ +"0.3059,0.2941,0.2824,0.2551,0.2199,0.1457,0.0168",\ +"0.3332,0.3215,0.3059,0.2785,0.2434,0.1691,0.0402",\ +"0.3723,0.3605,0.3449,0.3176,0.2824,0.2121,0.0793",\ +"0.4465,0.4348,0.4230,0.3918,0.3566,0.2824,0.1535",\ +"0.5832,0.5715,0.5598,0.5324,0.4934,0.4191,0.2902"); + } + } +} +pin(A_WEN) { + direction : input ; + capacitance : 0.00341384 ; + max_transition : "0.38" ; + related_power_pin : VDD; + related_ground_pin : VSS; + internal_power() { + when : "A_MEN"; + rise_power("scalar"){ + values (0.0083); + } + fall_power("scalar"){ + values (0.0107); + } + } + internal_power() { + when : "!A_MEN"; + rise_power("scalar"){ + values (0.0099); + } + fall_power("scalar"){ + values (0.0320); + } + } + timing() { + timing_type : setup_rising; + related_pin : "A_CLK"; + when : "A_MEN" + sdf_cond : "A_MEN" + + rise_constraint("SIG2SRAM_constraint_template") { + index_1("0.0040,0.0176,0.0344,0.0656,0.1120,0.2016,0.3800"); + index_2("0.0040,0.0176,0.0344,0.0656,0.1120,0.2016,0.3800"); + values ("0.1418,0.1496,0.1652,0.1887,0.2316,0.3059,0.4465",\ +"0.1301,0.1379,0.1535,0.1809,0.2199,0.2941,0.4348",\ +"0.1145,0.1262,0.1379,0.1652,0.2043,0.2785,0.4191",\ +"0.0871,0.0949,0.1105,0.1379,0.1770,0.2512,0.3879",\ +"0.0480,0.0598,0.0754,0.0988,0.1379,0.2082,0.3527",\ +"-0.0262,-0.0145,0.0012,0.0246,0.0676,0.1379,0.2785",\ +"-0.1668,-0.1551,-0.1395,-0.1121,-0.0730,0.0012,0.1418"); + } + + fall_constraint("SIG2SRAM_constraint_template") { + index_1("0.0040,0.0176,0.0344,0.0656,0.1120,0.2016,0.3800"); + index_2("0.0040,0.0176,0.0344,0.0656,0.1120,0.2016,0.3800"); + values ("0.2082,0.2160,0.2316,0.2590,0.2941,0.3684,0.5012",\ +"0.1926,0.2043,0.2199,0.2473,0.2824,0.3566,0.4895",\ +"0.1770,0.1887,0.2043,0.2316,0.2668,0.3410,0.4777",\ +"0.1535,0.1652,0.1770,0.2043,0.2395,0.3137,0.4504",\ +"0.1145,0.1262,0.1379,0.1652,0.2043,0.2746,0.4113",\ +"0.0402,0.0520,0.0676,0.0910,0.1262,0.2004,0.3332",\ +"-0.0965,-0.0848,-0.0730,-0.0457,-0.0066,0.0637,0.2004"); + } + } + + + timing() { + timing_type : hold_rising; + related_pin : "A_CLK"; + when : "A_MEN" + sdf_cond : "A_MEN" + + rise_constraint("SIG2SRAM_constraint_template") { + index_1("0.0040,0.0176,0.0344,0.0656,0.1120,0.2016,0.3800"); + index_2("0.0040,0.0176,0.0344,0.0656,0.1120,0.2016,0.3800"); + values ("0.1770,0.1652,0.1496,0.1223,0.0793,0.0090,-0.1316",\ +"0.1848,0.1730,0.1574,0.1301,0.0910,0.0168,-0.1199",\ +"0.2004,0.1887,0.1770,0.1496,0.1066,0.0363,-0.1043",\ +"0.2277,0.2160,0.2004,0.1730,0.1340,0.0598,-0.0809",\ +"0.2668,0.2551,0.2395,0.2121,0.1730,0.0988,-0.0418",\ +"0.3410,0.3293,0.3137,0.2863,0.2434,0.1730,0.0324",\ +"0.4816,0.4699,0.4543,0.4230,0.3801,0.3098,0.1730"); + } + + fall_constraint("SIG2SRAM_constraint_template") { + index_1("0.0040,0.0176,0.0344,0.0656,0.1120,0.2016,0.3800"); + index_2("0.0040,0.0176,0.0344,0.0656,0.1120,0.2016,0.3800"); + values ("0.1613,0.1496,0.1379,0.1066,0.0715,0.0012,-0.1355",\ +"0.1730,0.1613,0.1457,0.1184,0.0832,0.0129,-0.1238",\ +"0.1887,0.1770,0.1613,0.1340,0.0988,0.0246,-0.1121",\ +"0.2121,0.2043,0.1887,0.1613,0.1223,0.0520,-0.0848",\ +"0.2512,0.2434,0.2277,0.2004,0.1613,0.0910,-0.0457",\ +"0.3254,0.3176,0.3020,0.2746,0.2355,0.1652,0.0324",\ +"0.4660,0.4543,0.4387,0.4113,0.3723,0.3020,0.1691"); + } + } + } +pin(A_REN) { + direction : input ; + capacitance : 0.00390661 ; + max_transition : "0.38" ; + related_power_pin : VDD; + related_ground_pin : VSS; + internal_power() { + when : "A_MEN"; + rise_power("scalar"){ + values (0.0014); + } + fall_power("scalar"){ + values (0.0139); + } + } + internal_power() { + when : "!A_MEN"; + rise_power("scalar"){ + values (0.0211); + } + fall_power("scalar"){ + values (0.0216); + } + } + timing() { + timing_type : setup_rising; + related_pin : "A_CLK"; + when : "A_MEN" + sdf_cond : "A_MEN" + + rise_constraint("SIG2SRAM_constraint_template") { + index_1("0.0040,0.0176,0.0344,0.0656,0.1120,0.2016,0.3800"); + index_2("0.0040,0.0176,0.0344,0.0656,0.1120,0.2016,0.3800"); + values ("-0.0027,0.0090,0.0246,0.0520,0.0910,0.1613,0.3020",\ +"-0.0105,0.0012,0.0129,0.0363,0.0793,0.1535,0.2902",\ +"-0.0262,-0.0145,-0.0027,0.0246,0.0637,0.1379,0.2785",\ +"-0.0535,-0.0418,-0.0262,0.0012,0.0363,0.1105,0.2512",\ +"-0.0926,-0.0809,-0.0652,-0.0418,-0.0027,0.0715,0.2121",\ +"-0.1668,-0.1551,-0.1395,-0.1082,-0.0770,-0.0027,0.1379",\ +"-0.3035,-0.2918,-0.2762,-0.2488,-0.2137,-0.1434,-0.0027"); + } + + fall_constraint("SIG2SRAM_constraint_template") { + index_1("0.0040,0.0176,0.0344,0.0656,0.1120,0.2016,0.3800"); + index_2("0.0040,0.0176,0.0344,0.0656,0.1120,0.2016,0.3800"); + values ("0.0832,0.0949,0.1105,0.1379,0.1730,0.2473,0.3801",\ +"0.0754,0.0832,0.0988,0.1223,0.1613,0.2355,0.3684",\ +"0.0598,0.0676,0.0832,0.1066,0.1457,0.2121,0.3527",\ +"0.0324,0.0441,0.0598,0.0871,0.1223,0.1926,0.3293",\ +"-0.0066,0.0051,0.0168,0.0480,0.0832,0.1535,0.2902",\ +"-0.0809,-0.0691,-0.0574,-0.0301,0.0090,0.0832,0.2121",\ +"-0.2176,-0.2059,-0.1941,-0.1668,-0.1277,-0.0574,0.0793"); + } + } + + + timing() { + timing_type : hold_rising; + related_pin : "A_CLK"; + when : "A_MEN" + sdf_cond : "A_MEN" + + rise_constraint("SIG2SRAM_constraint_template") { + index_1("0.0040,0.0176,0.0344,0.0656,0.1120,0.2016,0.3800"); + index_2("0.0040,0.0176,0.0344,0.0656,0.1120,0.2016,0.3800"); + values ("0.1887,0.1770,0.1613,0.1340,0.0949,0.0207,-0.1160",\ +"0.1965,0.1848,0.1730,0.1457,0.1027,0.0324,-0.1082",\ +"0.2160,0.2004,0.1887,0.1613,0.1184,0.0480,-0.0926",\ +"0.2395,0.2277,0.2121,0.1848,0.1457,0.0715,-0.0652",\ +"0.2785,0.2668,0.2512,0.2238,0.1848,0.1105,-0.0262",\ +"0.3527,0.3410,0.3254,0.2980,0.2551,0.1848,0.0480",\ +"0.4934,0.4816,0.4660,0.4387,0.3957,0.3254,0.1887"); + } + + fall_constraint("SIG2SRAM_constraint_template") { + index_1("0.0040,0.0176,0.0344,0.0656,0.1120,0.2016,0.3800"); + index_2("0.0040,0.0176,0.0344,0.0656,0.1120,0.2016,0.3800"); + values ("0.1730,0.1613,0.1496,0.1184,0.0793,0.0129,-0.1238",\ +"0.1848,0.1730,0.1574,0.1301,0.0910,0.0207,-0.1121",\ +"0.2004,0.1887,0.1730,0.1457,0.1066,0.0363,-0.1004",\ +"0.2238,0.2121,0.2004,0.1691,0.1340,0.0598,-0.0730",\ +"0.2629,0.2512,0.2395,0.2121,0.1691,0.0988,-0.0340",\ +"0.3371,0.3254,0.3137,0.2863,0.2434,0.1730,0.0402",\ +"0.4777,0.4660,0.4504,0.4230,0.3840,0.3137,0.1809"); + } + } + } +pin(A_MEN) { + direction : input ; + capacitance : 0.00326046 ; + max_transition : "0.38" ; + related_power_pin : VDD; + related_ground_pin : VSS; + internal_power() { + rise_power("scalar"){ + values (0.3360); + } + fall_power("scalar"){ + values (0.0108); + } + } + timing() { + timing_type : setup_rising; + related_pin : "A_CLK"; + + rise_constraint("SIG2SRAM_constraint_template") { + index_1("0.0040,0.0176,0.0344,0.0656,0.1120,0.2016,0.3800"); + index_2("0.0040,0.0176,0.0344,0.0656,0.1120,0.2016,0.3800"); + values ("0.1418,0.1496,0.1652,0.1926,0.2316,0.3059,0.4465",\ +"0.1301,0.1379,0.1535,0.1809,0.2199,0.2941,0.4348",\ +"0.1145,0.1262,0.1418,0.1652,0.2043,0.2785,0.4191",\ +"0.0871,0.0949,0.1105,0.1379,0.1770,0.2512,0.3879",\ +"0.0480,0.0598,0.0754,0.0988,0.1379,0.2082,0.3488",\ +"-0.0262,-0.0145,0.0012,0.0285,0.0676,0.1379,0.2785",\ +"-0.1668,-0.1551,-0.1395,-0.1121,-0.0730,0.0012,0.1379"); + } + + fall_constraint("SIG2SRAM_constraint_template") { + index_1("0.0040,0.0176,0.0344,0.0656,0.1120,0.2016,0.3800"); + index_2("0.0040,0.0176,0.0344,0.0656,0.1120,0.2016,0.3800"); + values ("0.2082,0.2199,0.2316,0.2590,0.2980,0.3723,0.5051",\ +"0.1965,0.2082,0.2199,0.2473,0.2863,0.3605,0.4934",\ +"0.1809,0.1926,0.2043,0.2316,0.2707,0.3449,0.4777",\ +"0.1574,0.1691,0.1809,0.2082,0.2434,0.3176,0.4543",\ +"0.1145,0.1262,0.1418,0.1691,0.2043,0.2785,0.4113",\ +"0.0441,0.0559,0.0676,0.0949,0.1301,0.2004,0.3332",\ +"-0.0965,-0.0848,-0.0691,-0.0418,-0.0066,0.0676,0.2004"); + } + } + + + timing() { + timing_type : hold_rising; + related_pin : "A_CLK"; + + rise_constraint("SIG2SRAM_constraint_template") { + index_1("0.0040,0.0176,0.0344,0.0656,0.1120,0.2016,0.3800"); + index_2("0.0040,0.0176,0.0344,0.0656,0.1120,0.2016,0.3800"); + values ("0.1770,0.1652,0.1535,0.1262,0.0832,0.0129,-0.1277",\ +"0.1887,0.1770,0.1613,0.1340,0.0949,0.0207,-0.1199",\ +"0.2043,0.1926,0.1770,0.1496,0.1105,0.0363,-0.1043",\ +"0.2277,0.2160,0.2043,0.1770,0.1379,0.0598,-0.0770",\ +"0.2668,0.2551,0.2434,0.2160,0.1730,0.0988,-0.0379",\ +"0.3449,0.3332,0.3176,0.2902,0.2473,0.1730,0.0363",\ +"0.4816,0.4699,0.4543,0.4270,0.3840,0.3098,0.1770"); + } + + fall_constraint("SIG2SRAM_constraint_template") { + index_1("0.0040,0.0176,0.0344,0.0656,0.1120,0.2016,0.3800"); + index_2("0.0040,0.0176,0.0344,0.0656,0.1120,0.2016,0.3800"); + values ("0.1613,0.1496,0.1379,0.1105,0.0715,0.0012,-0.1355",\ +"0.1730,0.1613,0.1496,0.1184,0.0832,0.0129,-0.1238",\ +"0.1887,0.1770,0.1652,0.1340,0.0988,0.0285,-0.1121",\ +"0.2121,0.2043,0.1887,0.1613,0.1223,0.0520,-0.0848",\ +"0.2551,0.2434,0.2277,0.2004,0.1613,0.0910,-0.0418",\ +"0.3293,0.3176,0.3020,0.2746,0.2395,0.1652,0.0324",\ +"0.4660,0.4543,0.4426,0.4113,0.3762,0.3020,0.1691"); + } + } + } +bus(A_BM) { + bus_type : D_31_0; + direction : input ; + capacitance : 0.00388883 ; + max_transition : "0.38" ; + pin(A_BM[31:0]) { + related_power_pin : VDD; + related_ground_pin : VSS; + internal_power() { + when : "A_MEN"; + rise_power("scalar"){ + values (0.1471); + } + fall_power("scalar"){ + values (0.1374); + } + } + internal_power() { + when : "!A_MEN"; + rise_power("scalar"){ + values (0.1745); + } + fall_power("scalar"){ + values (0.1522); + } + } + } + timing() { + timing_type : setup_rising; + related_pin : "A_CLK"; + when : "(A_WEN & A_MEN)" + sdf_cond : "A_RW_ACCESS" + + rise_constraint("SIG2SRAM_constraint_template") { + index_1("0.0040,0.0176,0.0344,0.0656,0.1120,0.2016,0.3800"); + index_2("0.0040,0.0176,0.0344,0.0656,0.1120,0.2016,0.3800"); + values ("-0.2899,-0.2791,-0.2635,-0.2381,-0.1971,-0.1238,0.0109",\ +"-0.2937,-0.2830,-0.2674,-0.2420,-0.2010,-0.1277,0.0070",\ +"-0.2975,-0.2868,-0.2712,-0.2458,-0.2048,-0.1315,0.0032",\ +"-0.3008,-0.2900,-0.2744,-0.2490,-0.2080,-0.1348,-0.0000",\ +"-0.3132,-0.3025,-0.2869,-0.2615,-0.2205,-0.1472,-0.0125",\ +"-0.3308,-0.3201,-0.3045,-0.2791,-0.2381,-0.1648,-0.0301",\ +"-0.3584,-0.3476,-0.3320,-0.3066,-0.2656,-0.1923,-0.0576"); + } + + fall_constraint("SIG2SRAM_constraint_template") { + index_1("0.0040,0.0176,0.0344,0.0656,0.1120,0.2016,0.3800"); + index_2("0.0040,0.0176,0.0344,0.0656,0.1120,0.2016,0.3800"); + values ("-0.2664,-0.2547,-0.2420,-0.2147,-0.1776,-0.1043,0.0236",\ +"-0.2703,-0.2586,-0.2459,-0.2185,-0.1814,-0.1082,0.0197",\ +"-0.2741,-0.2624,-0.2497,-0.2223,-0.1852,-0.1120,0.0159",\ +"-0.2774,-0.2656,-0.2529,-0.2256,-0.1885,-0.1152,0.0127",\ +"-0.2898,-0.2781,-0.2654,-0.2380,-0.2009,-0.1277,0.0002",\ +"-0.3074,-0.2957,-0.2830,-0.2556,-0.2185,-0.1453,-0.0174",\ +"-0.3349,-0.3232,-0.3105,-0.2832,-0.2460,-0.1728,-0.0449"); + } + } + + + timing() { + timing_type : hold_rising; + related_pin : "A_CLK"; + when : "(A_WEN & A_MEN)" + sdf_cond : "A_RW_ACCESS" + + rise_constraint("SIG2SRAM_constraint_template") { + index_1("0.0040,0.0176,0.0344,0.0656,0.1120,0.2016,0.3800"); + index_2("0.0040,0.0176,0.0344,0.0656,0.1120,0.2016,0.3800"); + values ("0.3958,0.3861,0.3704,0.3441,0.3070,0.2328,0.0980",\ +"0.3997,0.3900,0.3743,0.3480,0.3109,0.2366,0.1019",\ +"0.4035,0.3938,0.3781,0.3518,0.3147,0.2404,0.1057",\ +"0.4068,0.3970,0.3814,0.3550,0.3179,0.2437,0.1089",\ +"0.4192,0.4095,0.3938,0.3675,0.3303,0.2561,0.1214",\ +"0.4368,0.4271,0.4114,0.3851,0.3480,0.2737,0.1390",\ +"0.4643,0.4546,0.4389,0.4126,0.3755,0.3013,0.1665"); + } + + fall_constraint("SIG2SRAM_constraint_template") { + index_1("0.0040,0.0176,0.0344,0.0656,0.1120,0.2016,0.3800"); + index_2("0.0040,0.0176,0.0344,0.0656,0.1120,0.2016,0.3800"); + values ("0.3675,0.3568,0.3431,0.3158,0.2796,0.2074,0.0775",\ +"0.3714,0.3607,0.3470,0.3196,0.2835,0.2112,0.0814",\ +"0.3752,0.3645,0.3508,0.3234,0.2873,0.2150,0.0852",\ +"0.3785,0.3677,0.3540,0.3267,0.2906,0.2183,0.0884",\ +"0.3909,0.3802,0.3665,0.3391,0.3030,0.2307,0.1009",\ +"0.4085,0.3978,0.3841,0.3567,0.3206,0.2484,0.1185",\ +"0.4360,0.4253,0.4116,0.3843,0.3481,0.2759,0.1460"); + } + } +} + pin(A_CLK) { + direction : input; + capacitance : 0.00389386; + max_transition : "0.38"; + clock : "true" ; + pin_func_type : active_rising ; + + timing () { + timing_type : "min_pulse_width"; + related_pin : "A_CLK"; + rise_constraint("CLKTRAN_constraint_template") { + index_1("0.004,0.38"); + values("0.12,0.12"); + } + } + + related_power_pin : VDD; + related_ground_pin : VSS; + + internal_power() { + when : "!A_MEN & !A_WEN & !A_REN"; + rise_power("scalar"){ + values (0); + } + fall_power("scalar"){ + values (0); + } + } + internal_power() { + when : "!A_MEN & A_WEN & !A_REN"; + rise_power("scalar"){ + values (0.6735); + } + fall_power("scalar"){ + values (0); + } + } + internal_power() { + when : "A_MEN & A_WEN & !A_REN"; + rise_power("scalar"){ + values (54.8620); + } + fall_power("scalar"){ + values (0); + } + } + internal_power() { + when : "A_MEN & A_WEN & A_REN"; + rise_power("scalar"){ + values (56.6091); + } + fall_power("scalar"){ + values (0); + } + } + internal_power() { + when : "A_MEN & !A_WEN & A_REN"; + rise_power("scalar"){ + values (45.3648); + } + fall_power("scalar"){ + values (0); + } + } + internal_power() { + when : "!A_MEN & !A_WEN & A_REN"; + rise_power("scalar"){ + values (0.4386); + } + fall_power("scalar"){ + values (0); + } + } + internal_power() { + when : "!A_MEN & A_WEN & A_REN"; + rise_power("scalar"){ + values (1.6639); + } + fall_power("scalar"){ + values (0); + } + } + internal_power() { + when : "A_MEN & !A_WEN & !A_REN"; + rise_power("scalar"){ + values (0); + } + fall_power("scalar"){ + values (0); + } + } + } + bus(A_DIN) { + bus_type : D_31_0; + direction : input ; + capacitance : 0.00505326 ; + memory_write() { + address : A_ADDR ; + clocked_on : A_CLK; + } + + max_transition : "0.38" ; + pin(A_DIN[31:0]) { + related_power_pin : VDD; + related_ground_pin : VSS; + internal_power() { + when : "A_MEN"; + rise_power("scalar"){ + values (0.1471); + } + fall_power("scalar"){ + values (0.1374); + } + } + internal_power() { + when : "!A_MEN"; + rise_power("scalar"){ + values (0.1745); + } + fall_power("scalar"){ + values (0.1522); + } + } + } + timing() { + timing_type : setup_rising; + related_pin : "A_CLK"; + when : "(A_WEN & A_MEN)"; + sdf_cond : "A_W_ACCESS"; + + rise_constraint("SIG2SRAM_constraint_template") { + index_1("0.0040,0.0176,0.0344,0.0656,0.1120,0.2016,0.3800"); + index_2("0.0040,0.0176,0.0344,0.0656,0.1120,0.2016,0.3800"); + values ("-0.2899,-0.2791,-0.2635,-0.2381,-0.1971,-0.1238,0.0109",\ +"-0.2937,-0.2830,-0.2674,-0.2420,-0.2010,-0.1277,0.0070",\ +"-0.2975,-0.2868,-0.2712,-0.2458,-0.2048,-0.1315,0.0032",\ +"-0.3008,-0.2900,-0.2744,-0.2490,-0.2080,-0.1348,-0.0000",\ +"-0.3132,-0.3025,-0.2869,-0.2615,-0.2205,-0.1472,-0.0125",\ +"-0.3308,-0.3201,-0.3045,-0.2791,-0.2381,-0.1648,-0.0301",\ +"-0.3584,-0.3476,-0.3320,-0.3066,-0.2656,-0.1923,-0.0576"); + } + + fall_constraint("SIG2SRAM_constraint_template") { + index_1("0.0040,0.0176,0.0344,0.0656,0.1120,0.2016,0.3800"); + index_2("0.0040,0.0176,0.0344,0.0656,0.1120,0.2016,0.3800"); + values ("-0.2664,-0.2547,-0.2420,-0.2147,-0.1776,-0.1043,0.0236",\ +"-0.2703,-0.2586,-0.2459,-0.2185,-0.1814,-0.1082,0.0197",\ +"-0.2741,-0.2624,-0.2497,-0.2223,-0.1852,-0.1120,0.0159",\ +"-0.2774,-0.2656,-0.2529,-0.2256,-0.1885,-0.1152,0.0127",\ +"-0.2898,-0.2781,-0.2654,-0.2380,-0.2009,-0.1277,0.0002",\ +"-0.3074,-0.2957,-0.2830,-0.2556,-0.2185,-0.1453,-0.0174",\ +"-0.3349,-0.3232,-0.3105,-0.2832,-0.2460,-0.1728,-0.0449"); + } + } + + timing() { + timing_type : hold_rising; + related_pin : "A_CLK"; + when : "(A_WEN & A_MEN)"; + sdf_cond : "A_W_ACCESS"; + + rise_constraint("SIG2SRAM_constraint_template") { + index_1("0.0040,0.0176,0.0344,0.0656,0.1120,0.2016,0.3800"); + index_2("0.0040,0.0176,0.0344,0.0656,0.1120,0.2016,0.3800"); + values ("0.3958,0.3861,0.3704,0.3441,0.3070,0.2328,0.0980",\ +"0.3997,0.3900,0.3743,0.3480,0.3109,0.2366,0.1019",\ +"0.4035,0.3938,0.3781,0.3518,0.3147,0.2404,0.1057",\ +"0.4068,0.3970,0.3814,0.3550,0.3179,0.2437,0.1089",\ +"0.4192,0.4095,0.3938,0.3675,0.3303,0.2561,0.1214",\ +"0.4368,0.4271,0.4114,0.3851,0.3480,0.2737,0.1390",\ +"0.4643,0.4546,0.4389,0.4126,0.3755,0.3013,0.1665"); + } + + fall_constraint("SIG2SRAM_constraint_template") { + index_1("0.0040,0.0176,0.0344,0.0656,0.1120,0.2016,0.3800"); + index_2("0.0040,0.0176,0.0344,0.0656,0.1120,0.2016,0.3800"); + values ("0.3675,0.3568,0.3431,0.3158,0.2796,0.2074,0.0775",\ +"0.3714,0.3607,0.3470,0.3196,0.2835,0.2112,0.0814",\ +"0.3752,0.3645,0.3508,0.3234,0.2873,0.2150,0.0852",\ +"0.3785,0.3677,0.3540,0.3267,0.2906,0.2183,0.0884",\ +"0.3909,0.3802,0.3665,0.3391,0.3030,0.2307,0.1009",\ +"0.4085,0.3978,0.3841,0.3567,0.3206,0.2484,0.1185",\ +"0.4360,0.4253,0.4116,0.3843,0.3481,0.2759,0.1460"); + } + } + } + + pin(A_BIST_EN) { + direction : input ; + capacitance : 0.00421562 ; + max_transition : "1" ; + related_power_pin : VDD; + related_ground_pin : VSS; + internal_power() { + rise_power("scalar") { + values (0); + } + fall_power("scalar") { + values (0); + } + } + } + +bus(A_BIST_ADDR) { + bus_type : A_8_0; + direction : input ; + capacitance : 0.0115194 ; + pin(A_BIST_ADDR[0]) { + capacitance : 0.00563454 ; + } + pin(A_BIST_ADDR[1]) { + capacitance : 0.00744185 ; + } + pin(A_BIST_ADDR[2]) { + capacitance : 0.0100611 ; + } + pin(A_BIST_ADDR[3]) { + capacitance : 0.00669965 ; + } + pin(A_BIST_ADDR[4]) { + capacitance : 0.00614331 ; + } + pin(A_BIST_ADDR[5]) { + capacitance : 0.0102172 ; + } + pin(A_BIST_ADDR[6]) { + capacitance : 0.0124225 ; + } + pin(A_BIST_ADDR[7]) { + capacitance : 0.010114 ; + } + max_transition : "0.38" ; + pin(A_BIST_ADDR[8:0]) { + related_power_pin : VDD; + related_ground_pin : VSS; + internal_power() { + when : "A_BIST_MEN"; + rise_power("scalar"){ + values (0.0115); + } + fall_power("scalar"){ + values (0.0021); + } + } + internal_power() { + when : "!A_BIST_MEN"; + rise_power("scalar"){ + values (0.0343); + } + fall_power("scalar"){ + values (0.0003); + } + } + } + timing() { + timing_type : setup_rising; + related_pin : "A_BIST_CLK"; + when : "((A_BIST_WEN | A_BIST_REN)& A_BIST_MEN)" + sdf_cond : "A_BIST_RW_ACCESS" + + rise_constraint("SIG2SRAM_constraint_template") { + index_1("0.0040,0.0176,0.0344,0.0656,0.1120,0.2016,0.3800"); + index_2("0.0040,0.0176,0.0344,0.0656,0.1120,0.2016,0.3800"); + values ("-0.2371,-0.2215,-0.2098,-0.1824,-0.1434,-0.0691,0.0676",\ +"-0.2449,-0.2332,-0.2176,-0.1902,-0.1551,-0.0770,0.0559",\ +"-0.2605,-0.2488,-0.2332,-0.2059,-0.1707,-0.0965,0.0441",\ +"-0.2879,-0.2723,-0.2605,-0.2332,-0.1941,-0.1199,0.0168",\ +"-0.3230,-0.3113,-0.2996,-0.2723,-0.2332,-0.1590,-0.0184",\ +"-0.4012,-0.3895,-0.3738,-0.3465,-0.3074,-0.2332,-0.0965",\ +"-0.5379,-0.5262,-0.5105,-0.4832,-0.4480,-0.3699,-0.2332"); + } + + fall_constraint("SIG2SRAM_constraint_template") { + index_1("0.0040,0.0176,0.0344,0.0656,0.1120,0.2016,0.3800"); + index_2("0.0040,0.0176,0.0344,0.0656,0.1120,0.2016,0.3800"); + values ("-0.1785,-0.1707,-0.1551,-0.1277,-0.0887,-0.0184,0.1145",\ +"-0.1902,-0.1785,-0.1629,-0.1355,-0.1004,-0.0262,0.1027",\ +"-0.2059,-0.1941,-0.1785,-0.1512,-0.1160,-0.0418,0.0871",\ +"-0.2293,-0.2176,-0.2059,-0.1785,-0.1434,-0.0691,0.0598",\ +"-0.2684,-0.2566,-0.2449,-0.2176,-0.1824,-0.1082,0.0207",\ +"-0.3465,-0.3348,-0.3191,-0.2918,-0.2566,-0.1824,-0.0535",\ +"-0.4832,-0.4715,-0.4559,-0.4324,-0.3934,-0.3191,-0.1902"); + } + } + + + timing() { + timing_type : hold_rising; + related_pin : "A_BIST_CLK"; + when : "((A_BIST_WEN | A_BIST_REN)& A_BIST_MEN)" + sdf_cond : "A_BIST_RW_ACCESS" + + rise_constraint("SIG2SRAM_constraint_template") { + index_1("0.0040,0.0176,0.0344,0.0656,0.1120,0.2016,0.3800"); + index_2("0.0040,0.0176,0.0344,0.0656,0.1120,0.2016,0.3800"); + values ("0.3410,0.3293,0.3137,0.2863,0.2473,0.1730,0.0324",\ +"0.3488,0.3371,0.3215,0.2941,0.2590,0.1809,0.0480",\ +"0.3684,0.3527,0.3371,0.3098,0.2746,0.1965,0.0598",\ +"0.3918,0.3762,0.3645,0.3371,0.2980,0.2238,0.0871",\ +"0.4309,0.4152,0.4035,0.3762,0.3371,0.2629,0.1223",\ +"0.5051,0.4934,0.4777,0.4504,0.4113,0.3371,0.1965",\ +"0.6418,0.6262,0.6145,0.5871,0.5520,0.4738,0.3332"); + } + + fall_constraint("SIG2SRAM_constraint_template") { + index_1("0.0040,0.0176,0.0344,0.0656,0.1120,0.2016,0.3800"); + index_2("0.0040,0.0176,0.0344,0.0656,0.1120,0.2016,0.3800"); + values ("0.2824,0.2707,0.2551,0.2277,0.1926,0.1184,-0.0105",\ +"0.2902,0.2785,0.2668,0.2395,0.2043,0.1301,0.0012",\ +"0.3059,0.2941,0.2824,0.2551,0.2199,0.1457,0.0168",\ +"0.3332,0.3215,0.3059,0.2785,0.2434,0.1691,0.0402",\ +"0.3723,0.3605,0.3449,0.3176,0.2824,0.2121,0.0793",\ +"0.4465,0.4348,0.4230,0.3918,0.3566,0.2824,0.1535",\ +"0.5832,0.5715,0.5598,0.5324,0.4934,0.4191,0.2902"); + } + } +} +pin(A_BIST_WEN) { + direction : input ; + capacitance : 0.00341384 ; + max_transition : "0.38" ; + related_power_pin : VDD; + related_ground_pin : VSS; + internal_power() { + when : "A_BIST_MEN"; + rise_power("scalar"){ + values (0.0083); + } + fall_power("scalar"){ + values (0.0107); + } + } + internal_power() { + when : "!A_BIST_MEN"; + rise_power("scalar"){ + values (0.0099); + } + fall_power("scalar"){ + values (0.0320); + } + } + timing() { + timing_type : setup_rising; + related_pin : "A_BIST_CLK"; + when : "A_BIST_MEN" + sdf_cond : "A_BIST_MEN" + + rise_constraint("SIG2SRAM_constraint_template") { + index_1("0.0040,0.0176,0.0344,0.0656,0.1120,0.2016,0.3800"); + index_2("0.0040,0.0176,0.0344,0.0656,0.1120,0.2016,0.3800"); + values ("0.1418,0.1496,0.1652,0.1887,0.2316,0.3059,0.4465",\ +"0.1301,0.1379,0.1535,0.1809,0.2199,0.2941,0.4348",\ +"0.1145,0.1262,0.1379,0.1652,0.2043,0.2785,0.4191",\ +"0.0871,0.0949,0.1105,0.1379,0.1770,0.2512,0.3879",\ +"0.0480,0.0598,0.0754,0.0988,0.1379,0.2082,0.3527",\ +"-0.0262,-0.0145,0.0012,0.0246,0.0676,0.1379,0.2785",\ +"-0.1668,-0.1551,-0.1395,-0.1121,-0.0730,0.0012,0.1418"); + } + + fall_constraint("SIG2SRAM_constraint_template") { + index_1("0.0040,0.0176,0.0344,0.0656,0.1120,0.2016,0.3800"); + index_2("0.0040,0.0176,0.0344,0.0656,0.1120,0.2016,0.3800"); + values ("0.2082,0.2160,0.2316,0.2590,0.2941,0.3684,0.5012",\ +"0.1926,0.2043,0.2199,0.2473,0.2824,0.3566,0.4895",\ +"0.1770,0.1887,0.2043,0.2316,0.2668,0.3410,0.4777",\ +"0.1535,0.1652,0.1770,0.2043,0.2395,0.3137,0.4504",\ +"0.1145,0.1262,0.1379,0.1652,0.2043,0.2746,0.4113",\ +"0.0402,0.0520,0.0676,0.0910,0.1262,0.2004,0.3332",\ +"-0.0965,-0.0848,-0.0730,-0.0457,-0.0066,0.0637,0.2004"); + } + } + + + timing() { + timing_type : hold_rising; + related_pin : "A_BIST_CLK"; + when : "A_BIST_MEN" + sdf_cond : "A_BIST_MEN" + + rise_constraint("SIG2SRAM_constraint_template") { + index_1("0.0040,0.0176,0.0344,0.0656,0.1120,0.2016,0.3800"); + index_2("0.0040,0.0176,0.0344,0.0656,0.1120,0.2016,0.3800"); + values ("0.1770,0.1652,0.1496,0.1223,0.0793,0.0090,-0.1316",\ +"0.1848,0.1730,0.1574,0.1301,0.0910,0.0168,-0.1199",\ +"0.2004,0.1887,0.1770,0.1496,0.1066,0.0363,-0.1043",\ +"0.2277,0.2160,0.2004,0.1730,0.1340,0.0598,-0.0809",\ +"0.2668,0.2551,0.2395,0.2121,0.1730,0.0988,-0.0418",\ +"0.3410,0.3293,0.3137,0.2863,0.2434,0.1730,0.0324",\ +"0.4816,0.4699,0.4543,0.4230,0.3801,0.3098,0.1730"); + } + + fall_constraint("SIG2SRAM_constraint_template") { + index_1("0.0040,0.0176,0.0344,0.0656,0.1120,0.2016,0.3800"); + index_2("0.0040,0.0176,0.0344,0.0656,0.1120,0.2016,0.3800"); + values ("0.1613,0.1496,0.1379,0.1066,0.0715,0.0012,-0.1355",\ +"0.1730,0.1613,0.1457,0.1184,0.0832,0.0129,-0.1238",\ +"0.1887,0.1770,0.1613,0.1340,0.0988,0.0246,-0.1121",\ +"0.2121,0.2043,0.1887,0.1613,0.1223,0.0520,-0.0848",\ +"0.2512,0.2434,0.2277,0.2004,0.1613,0.0910,-0.0457",\ +"0.3254,0.3176,0.3020,0.2746,0.2355,0.1652,0.0324",\ +"0.4660,0.4543,0.4387,0.4113,0.3723,0.3020,0.1691"); + } + } + } +pin(A_BIST_REN) { + direction : input ; + capacitance : 0.00390661 ; + max_transition : "0.38" ; + related_power_pin : VDD; + related_ground_pin : VSS; + internal_power() { + when : "A_BIST_MEN"; + rise_power("scalar"){ + values (0.0014); + } + fall_power("scalar"){ + values (0.0139); + } + } + internal_power() { + when : "!A_BIST_MEN"; + rise_power("scalar"){ + values (0.0211); + } + fall_power("scalar"){ + values (0.0216); + } + } + timing() { + timing_type : setup_rising; + related_pin : "A_BIST_CLK"; + when : "A_BIST_MEN" + sdf_cond : "A_BIST_MEN" + + rise_constraint("SIG2SRAM_constraint_template") { + index_1("0.0040,0.0176,0.0344,0.0656,0.1120,0.2016,0.3800"); + index_2("0.0040,0.0176,0.0344,0.0656,0.1120,0.2016,0.3800"); + values ("-0.0027,0.0090,0.0246,0.0520,0.0910,0.1613,0.3020",\ +"-0.0105,0.0012,0.0129,0.0363,0.0793,0.1535,0.2902",\ +"-0.0262,-0.0145,-0.0027,0.0246,0.0637,0.1379,0.2785",\ +"-0.0535,-0.0418,-0.0262,0.0012,0.0363,0.1105,0.2512",\ +"-0.0926,-0.0809,-0.0652,-0.0418,-0.0027,0.0715,0.2121",\ +"-0.1668,-0.1551,-0.1395,-0.1082,-0.0770,-0.0027,0.1379",\ +"-0.3035,-0.2918,-0.2762,-0.2488,-0.2137,-0.1434,-0.0027"); + } + + fall_constraint("SIG2SRAM_constraint_template") { + index_1("0.0040,0.0176,0.0344,0.0656,0.1120,0.2016,0.3800"); + index_2("0.0040,0.0176,0.0344,0.0656,0.1120,0.2016,0.3800"); + values ("0.0832,0.0949,0.1105,0.1379,0.1730,0.2473,0.3801",\ +"0.0754,0.0832,0.0988,0.1223,0.1613,0.2355,0.3684",\ +"0.0598,0.0676,0.0832,0.1066,0.1457,0.2121,0.3527",\ +"0.0324,0.0441,0.0598,0.0871,0.1223,0.1926,0.3293",\ +"-0.0066,0.0051,0.0168,0.0480,0.0832,0.1535,0.2902",\ +"-0.0809,-0.0691,-0.0574,-0.0301,0.0090,0.0832,0.2121",\ +"-0.2176,-0.2059,-0.1941,-0.1668,-0.1277,-0.0574,0.0793"); + } + } + + + timing() { + timing_type : hold_rising; + related_pin : "A_BIST_CLK"; + when : "A_BIST_MEN" + sdf_cond : "A_BIST_MEN" + + rise_constraint("SIG2SRAM_constraint_template") { + index_1("0.0040,0.0176,0.0344,0.0656,0.1120,0.2016,0.3800"); + index_2("0.0040,0.0176,0.0344,0.0656,0.1120,0.2016,0.3800"); + values ("0.1887,0.1770,0.1613,0.1340,0.0949,0.0207,-0.1160",\ +"0.1965,0.1848,0.1730,0.1457,0.1027,0.0324,-0.1082",\ +"0.2160,0.2004,0.1887,0.1613,0.1184,0.0480,-0.0926",\ +"0.2395,0.2277,0.2121,0.1848,0.1457,0.0715,-0.0652",\ +"0.2785,0.2668,0.2512,0.2238,0.1848,0.1105,-0.0262",\ +"0.3527,0.3410,0.3254,0.2980,0.2551,0.1848,0.0480",\ +"0.4934,0.4816,0.4660,0.4387,0.3957,0.3254,0.1887"); + } + + fall_constraint("SIG2SRAM_constraint_template") { + index_1("0.0040,0.0176,0.0344,0.0656,0.1120,0.2016,0.3800"); + index_2("0.0040,0.0176,0.0344,0.0656,0.1120,0.2016,0.3800"); + values ("0.1730,0.1613,0.1496,0.1184,0.0793,0.0129,-0.1238",\ +"0.1848,0.1730,0.1574,0.1301,0.0910,0.0207,-0.1121",\ +"0.2004,0.1887,0.1730,0.1457,0.1066,0.0363,-0.1004",\ +"0.2238,0.2121,0.2004,0.1691,0.1340,0.0598,-0.0730",\ +"0.2629,0.2512,0.2395,0.2121,0.1691,0.0988,-0.0340",\ +"0.3371,0.3254,0.3137,0.2863,0.2434,0.1730,0.0402",\ +"0.4777,0.4660,0.4504,0.4230,0.3840,0.3137,0.1809"); + } + } + } +pin(A_BIST_MEN) { + direction : input ; + capacitance : 0.00326046 ; + max_transition : "0.38" ; + related_power_pin : VDD; + related_ground_pin : VSS; + internal_power() { + rise_power("scalar"){ + values (0.3360); + } + fall_power("scalar"){ + values (0.0108); + } + } + timing() { + timing_type : setup_rising; + related_pin : "A_BIST_CLK"; + + rise_constraint("SIG2SRAM_constraint_template") { + index_1("0.0040,0.0176,0.0344,0.0656,0.1120,0.2016,0.3800"); + index_2("0.0040,0.0176,0.0344,0.0656,0.1120,0.2016,0.3800"); + values ("0.1418,0.1496,0.1652,0.1926,0.2316,0.3059,0.4465",\ +"0.1301,0.1379,0.1535,0.1809,0.2199,0.2941,0.4348",\ +"0.1145,0.1262,0.1418,0.1652,0.2043,0.2785,0.4191",\ +"0.0871,0.0949,0.1105,0.1379,0.1770,0.2512,0.3879",\ +"0.0480,0.0598,0.0754,0.0988,0.1379,0.2082,0.3488",\ +"-0.0262,-0.0145,0.0012,0.0285,0.0676,0.1379,0.2785",\ +"-0.1668,-0.1551,-0.1395,-0.1121,-0.0730,0.0012,0.1379"); + } + + fall_constraint("SIG2SRAM_constraint_template") { + index_1("0.0040,0.0176,0.0344,0.0656,0.1120,0.2016,0.3800"); + index_2("0.0040,0.0176,0.0344,0.0656,0.1120,0.2016,0.3800"); + values ("0.2082,0.2199,0.2316,0.2590,0.2980,0.3723,0.5051",\ +"0.1965,0.2082,0.2199,0.2473,0.2863,0.3605,0.4934",\ +"0.1809,0.1926,0.2043,0.2316,0.2707,0.3449,0.4777",\ +"0.1574,0.1691,0.1809,0.2082,0.2434,0.3176,0.4543",\ +"0.1145,0.1262,0.1418,0.1691,0.2043,0.2785,0.4113",\ +"0.0441,0.0559,0.0676,0.0949,0.1301,0.2004,0.3332",\ +"-0.0965,-0.0848,-0.0691,-0.0418,-0.0066,0.0676,0.2004"); + } + } + + + timing() { + timing_type : hold_rising; + related_pin : "A_BIST_CLK"; + + rise_constraint("SIG2SRAM_constraint_template") { + index_1("0.0040,0.0176,0.0344,0.0656,0.1120,0.2016,0.3800"); + index_2("0.0040,0.0176,0.0344,0.0656,0.1120,0.2016,0.3800"); + values ("0.1770,0.1652,0.1535,0.1262,0.0832,0.0129,-0.1277",\ +"0.1887,0.1770,0.1613,0.1340,0.0949,0.0207,-0.1199",\ +"0.2043,0.1926,0.1770,0.1496,0.1105,0.0363,-0.1043",\ +"0.2277,0.2160,0.2043,0.1770,0.1379,0.0598,-0.0770",\ +"0.2668,0.2551,0.2434,0.2160,0.1730,0.0988,-0.0379",\ +"0.3449,0.3332,0.3176,0.2902,0.2473,0.1730,0.0363",\ +"0.4816,0.4699,0.4543,0.4270,0.3840,0.3098,0.1770"); + } + + fall_constraint("SIG2SRAM_constraint_template") { + index_1("0.0040,0.0176,0.0344,0.0656,0.1120,0.2016,0.3800"); + index_2("0.0040,0.0176,0.0344,0.0656,0.1120,0.2016,0.3800"); + values ("0.1613,0.1496,0.1379,0.1105,0.0715,0.0012,-0.1355",\ +"0.1730,0.1613,0.1496,0.1184,0.0832,0.0129,-0.1238",\ +"0.1887,0.1770,0.1652,0.1340,0.0988,0.0285,-0.1121",\ +"0.2121,0.2043,0.1887,0.1613,0.1223,0.0520,-0.0848",\ +"0.2551,0.2434,0.2277,0.2004,0.1613,0.0910,-0.0418",\ +"0.3293,0.3176,0.3020,0.2746,0.2395,0.1652,0.0324",\ +"0.4660,0.4543,0.4426,0.4113,0.3762,0.3020,0.1691"); + } + } + } +bus(A_BIST_BM) { + bus_type : D_31_0; + direction : input ; + capacitance : 0.00353394 ; + max_transition : "0.38" ; + pin(A_BIST_BM[31:0]) { + related_power_pin : VDD; + related_ground_pin : VSS; + internal_power() { + when : "A_BIST_MEN"; + rise_power("scalar"){ + values (0.1471); + } + fall_power("scalar"){ + values (0.1374); + } + } + internal_power() { + when : "!A_BIST_MEN"; + rise_power("scalar"){ + values (0.1745); + } + fall_power("scalar"){ + values (0.1522); + } + } + } + timing() { + timing_type : setup_rising; + related_pin : "A_BIST_CLK"; + when : "(A_BIST_WEN & A_BIST_MEN)" + sdf_cond : "A_BIST_RW_ACCESS" + + rise_constraint("SIG2SRAM_constraint_template") { + index_1("0.0040,0.0176,0.0344,0.0656,0.1120,0.2016,0.3800"); + index_2("0.0040,0.0176,0.0344,0.0656,0.1120,0.2016,0.3800"); + values ("-0.2899,-0.2791,-0.2635,-0.2381,-0.1971,-0.1238,0.0109",\ +"-0.2937,-0.2830,-0.2674,-0.2420,-0.2010,-0.1277,0.0070",\ +"-0.2975,-0.2868,-0.2712,-0.2458,-0.2048,-0.1315,0.0032",\ +"-0.3008,-0.2900,-0.2744,-0.2490,-0.2080,-0.1348,-0.0000",\ +"-0.3132,-0.3025,-0.2869,-0.2615,-0.2205,-0.1472,-0.0125",\ +"-0.3308,-0.3201,-0.3045,-0.2791,-0.2381,-0.1648,-0.0301",\ +"-0.3584,-0.3476,-0.3320,-0.3066,-0.2656,-0.1923,-0.0576"); + } + + fall_constraint("SIG2SRAM_constraint_template") { + index_1("0.0040,0.0176,0.0344,0.0656,0.1120,0.2016,0.3800"); + index_2("0.0040,0.0176,0.0344,0.0656,0.1120,0.2016,0.3800"); + values ("-0.2664,-0.2547,-0.2420,-0.2147,-0.1776,-0.1043,0.0236",\ +"-0.2703,-0.2586,-0.2459,-0.2185,-0.1814,-0.1082,0.0197",\ +"-0.2741,-0.2624,-0.2497,-0.2223,-0.1852,-0.1120,0.0159",\ +"-0.2774,-0.2656,-0.2529,-0.2256,-0.1885,-0.1152,0.0127",\ +"-0.2898,-0.2781,-0.2654,-0.2380,-0.2009,-0.1277,0.0002",\ +"-0.3074,-0.2957,-0.2830,-0.2556,-0.2185,-0.1453,-0.0174",\ +"-0.3349,-0.3232,-0.3105,-0.2832,-0.2460,-0.1728,-0.0449"); + } + } + + + timing() { + timing_type : hold_rising; + related_pin : "A_BIST_CLK"; + when : "(A_BIST_WEN & A_BIST_MEN)" + sdf_cond : "A_BIST_RW_ACCESS" + + rise_constraint("SIG2SRAM_constraint_template") { + index_1("0.0040,0.0176,0.0344,0.0656,0.1120,0.2016,0.3800"); + index_2("0.0040,0.0176,0.0344,0.0656,0.1120,0.2016,0.3800"); + values ("0.3958,0.3861,0.3704,0.3441,0.3070,0.2328,0.0980",\ +"0.3997,0.3900,0.3743,0.3480,0.3109,0.2366,0.1019",\ +"0.4035,0.3938,0.3781,0.3518,0.3147,0.2404,0.1057",\ +"0.4068,0.3970,0.3814,0.3550,0.3179,0.2437,0.1089",\ +"0.4192,0.4095,0.3938,0.3675,0.3303,0.2561,0.1214",\ +"0.4368,0.4271,0.4114,0.3851,0.3480,0.2737,0.1390",\ +"0.4643,0.4546,0.4389,0.4126,0.3755,0.3013,0.1665"); + } + + fall_constraint("SIG2SRAM_constraint_template") { + index_1("0.0040,0.0176,0.0344,0.0656,0.1120,0.2016,0.3800"); + index_2("0.0040,0.0176,0.0344,0.0656,0.1120,0.2016,0.3800"); + values ("0.3675,0.3568,0.3431,0.3158,0.2796,0.2074,0.0775",\ +"0.3714,0.3607,0.3470,0.3196,0.2835,0.2112,0.0814",\ +"0.3752,0.3645,0.3508,0.3234,0.2873,0.2150,0.0852",\ +"0.3785,0.3677,0.3540,0.3267,0.2906,0.2183,0.0884",\ +"0.3909,0.3802,0.3665,0.3391,0.3030,0.2307,0.1009",\ +"0.4085,0.3978,0.3841,0.3567,0.3206,0.2484,0.1185",\ +"0.4360,0.4253,0.4116,0.3843,0.3481,0.2759,0.1460"); + } + } +} + pin(A_BIST_CLK) { + direction : input; + capacitance : 0.00389386; + max_transition : "0.38"; + clock : "true" ; + pin_func_type : active_rising ; + + timing () { + timing_type : "min_pulse_width"; + related_pin : "A_BIST_CLK"; + rise_constraint("CLKTRAN_constraint_template") { + index_1("0.004,0.38"); + values("0.12,0.12"); + } + } + + related_power_pin : VDD; + related_ground_pin : VSS; + + internal_power() { + when : "!A_BIST_MEN & !A_BIST_WEN & !A_BIST_REN"; + rise_power("scalar"){ + values (0); + } + fall_power("scalar"){ + values (0); + } + } + internal_power() { + when : "!A_BIST_MEN & A_BIST_WEN & !A_BIST_REN"; + rise_power("scalar"){ + values (0.6735); + } + fall_power("scalar"){ + values (0); + } + } + internal_power() { + when : "A_BIST_MEN & A_BIST_WEN & !A_BIST_REN"; + rise_power("scalar"){ + values (54.8620); + } + fall_power("scalar"){ + values (0); + } + } + internal_power() { + when : "A_BIST_MEN & A_BIST_WEN & A_BIST_REN"; + rise_power("scalar"){ + values (56.6091); + } + fall_power("scalar"){ + values (0); + } + } + internal_power() { + when : "A_BIST_MEN & !A_BIST_WEN & A_BIST_REN"; + rise_power("scalar"){ + values (45.3648); + } + fall_power("scalar"){ + values (0); + } + } + internal_power() { + when : "!A_BIST_MEN & !A_BIST_WEN & A_BIST_REN"; + rise_power("scalar"){ + values (0.4386); + } + fall_power("scalar"){ + values (0); + } + } + internal_power() { + when : "!A_BIST_MEN & A_BIST_WEN & A_BIST_REN"; + rise_power("scalar"){ + values (1.6639); + } + fall_power("scalar"){ + values (0); + } + } + internal_power() { + when : "A_BIST_MEN & !A_BIST_WEN & !A_BIST_REN"; + rise_power("scalar"){ + values (0); + } + fall_power("scalar"){ + values (0); + } + } + } + bus(A_BIST_DIN) { + bus_type : D_31_0; + direction : input ; + capacitance : 0.00397186 ; + memory_write() { + address : A_BIST_ADDR ; + clocked_on : A_BIST_CLK; + } + + max_transition : "0.38" ; + pin(A_BIST_DIN[31:0]) { + related_power_pin : VDD; + related_ground_pin : VSS; + internal_power() { + when : "A_BIST_MEN"; + rise_power("scalar"){ + values (0.1471); + } + fall_power("scalar"){ + values (0.1374); + } + } + internal_power() { + when : "!A_BIST_MEN"; + rise_power("scalar"){ + values (0.1745); + } + fall_power("scalar"){ + values (0.1522); + } + } + } + timing() { + timing_type : setup_rising; + related_pin : "A_BIST_CLK"; + when : "(A_BIST_WEN & A_BIST_MEN)"; + sdf_cond : "A_BIST_W_ACCESS"; + + rise_constraint("SIG2SRAM_constraint_template") { + index_1("0.0040,0.0176,0.0344,0.0656,0.1120,0.2016,0.3800"); + index_2("0.0040,0.0176,0.0344,0.0656,0.1120,0.2016,0.3800"); + values ("-0.2899,-0.2791,-0.2635,-0.2381,-0.1971,-0.1238,0.0109",\ +"-0.2937,-0.2830,-0.2674,-0.2420,-0.2010,-0.1277,0.0070",\ +"-0.2975,-0.2868,-0.2712,-0.2458,-0.2048,-0.1315,0.0032",\ +"-0.3008,-0.2900,-0.2744,-0.2490,-0.2080,-0.1348,-0.0000",\ +"-0.3132,-0.3025,-0.2869,-0.2615,-0.2205,-0.1472,-0.0125",\ +"-0.3308,-0.3201,-0.3045,-0.2791,-0.2381,-0.1648,-0.0301",\ +"-0.3584,-0.3476,-0.3320,-0.3066,-0.2656,-0.1923,-0.0576"); + } + + fall_constraint("SIG2SRAM_constraint_template") { + index_1("0.0040,0.0176,0.0344,0.0656,0.1120,0.2016,0.3800"); + index_2("0.0040,0.0176,0.0344,0.0656,0.1120,0.2016,0.3800"); + values ("-0.2664,-0.2547,-0.2420,-0.2147,-0.1776,-0.1043,0.0236",\ +"-0.2703,-0.2586,-0.2459,-0.2185,-0.1814,-0.1082,0.0197",\ +"-0.2741,-0.2624,-0.2497,-0.2223,-0.1852,-0.1120,0.0159",\ +"-0.2774,-0.2656,-0.2529,-0.2256,-0.1885,-0.1152,0.0127",\ +"-0.2898,-0.2781,-0.2654,-0.2380,-0.2009,-0.1277,0.0002",\ +"-0.3074,-0.2957,-0.2830,-0.2556,-0.2185,-0.1453,-0.0174",\ +"-0.3349,-0.3232,-0.3105,-0.2832,-0.2460,-0.1728,-0.0449"); + } + } + + timing() { + timing_type : hold_rising; + related_pin : "A_BIST_CLK"; + when : "(A_BIST_WEN & A_BIST_MEN)"; + sdf_cond : "A_BIST_W_ACCESS"; + + rise_constraint("SIG2SRAM_constraint_template") { + index_1("0.0040,0.0176,0.0344,0.0656,0.1120,0.2016,0.3800"); + index_2("0.0040,0.0176,0.0344,0.0656,0.1120,0.2016,0.3800"); + values ("0.3958,0.3861,0.3704,0.3441,0.3070,0.2328,0.0980",\ +"0.3997,0.3900,0.3743,0.3480,0.3109,0.2366,0.1019",\ +"0.4035,0.3938,0.3781,0.3518,0.3147,0.2404,0.1057",\ +"0.4068,0.3970,0.3814,0.3550,0.3179,0.2437,0.1089",\ +"0.4192,0.4095,0.3938,0.3675,0.3303,0.2561,0.1214",\ +"0.4368,0.4271,0.4114,0.3851,0.3480,0.2737,0.1390",\ +"0.4643,0.4546,0.4389,0.4126,0.3755,0.3013,0.1665"); + } + + fall_constraint("SIG2SRAM_constraint_template") { + index_1("0.0040,0.0176,0.0344,0.0656,0.1120,0.2016,0.3800"); + index_2("0.0040,0.0176,0.0344,0.0656,0.1120,0.2016,0.3800"); + values ("0.3675,0.3568,0.3431,0.3158,0.2796,0.2074,0.0775",\ +"0.3714,0.3607,0.3470,0.3196,0.2835,0.2112,0.0814",\ +"0.3752,0.3645,0.3508,0.3234,0.2873,0.2150,0.0852",\ +"0.3785,0.3677,0.3540,0.3267,0.2906,0.2183,0.0884",\ +"0.3909,0.3802,0.3665,0.3391,0.3030,0.2307,0.1009",\ +"0.4085,0.3978,0.3841,0.3567,0.3206,0.2484,0.1185",\ +"0.4360,0.4253,0.4116,0.3843,0.3481,0.2759,0.1460"); + } + } + } + +bus(A_DOUT) { + + bus_type : D_31_0; + direction : output ; + capacitance : 0 ; + max_capacitance : 0.064 ; + memory_read() { + address : A_ADDR ; + } + pin(A_DOUT[31:0]) { + related_power_pin : VDD; + related_ground_pin : VSS; + internal_power() { + rise_power("scalar") { + values (0); + } + fall_power("scalar") { + values (0); + } + } + } + timing() { + related_pin : "A_CLK"; + timing_type : rising_edge ; + timing_sense : non_unate ; + + cell_rise(SIG2SRAM_delay_template) { + index_1("0.0040,0.0176,0.0344,0.0656,0.1120,0.2016,0.3800"); + index_2("0.0008,0.0014,0.0051,0.0100,0.0339,0.0640"); + values ("2.3870,2.3880,2.3928,2.3984,2.4193,2.4428",\ +"2.3934,2.3944,2.3992,2.4047,2.4257,2.4492",\ +"2.3950,2.3960,2.4008,2.4063,2.4273,2.4508",\ +"2.3993,2.4003,2.4052,2.4107,2.4316,2.4551",\ +"2.4125,2.4135,2.4183,2.4238,2.4447,2.4682",\ +"2.4311,2.4321,2.4369,2.4424,2.4633,2.4868",\ +"2.4576,2.4586,2.4634,2.4689,2.4898,2.5133"); + } + cell_fall(SIG2SRAM_delay_template) { + index_1("0.0040,0.0176,0.0344,0.0656,0.1120,0.2016,0.3800"); + index_2("0.0008,0.0014,0.0051,0.0100,0.0339,0.0640"); + values ("2.3527,2.3536,2.3576,2.3622,2.3793,2.3960",\ +"2.3591,2.3600,2.3640,2.3686,2.3857,2.4024",\ +"2.3607,2.3616,2.3656,2.3702,2.3873,2.4040",\ +"2.3650,2.3659,2.3699,2.3745,2.3916,2.4083",\ +"2.3782,2.3791,2.3831,2.3877,2.4047,2.4215",\ +"2.3968,2.3976,2.4017,2.4062,2.4233,2.4400",\ +"2.4233,2.4241,2.4282,2.4327,2.4498,2.4665"); + } + + rise_transition(SRAM_load_template) { + index_1("0.0008,0.0014,0.0051,0.0100,0.0339,0.0640"); + values ("0.0206,0.0210,0.0265,0.0323,0.0606,0.0955"); + } + fall_transition(SRAM_load_template) { + index_1("0.0008,0.0014,0.0051,0.0100,0.0339,0.0640"); + values ("0.0170,0.0177,0.0222,0.0270,0.0451,0.0644"); + } + } +} + pin(B_DLY) { + direction : input ; + capacitance : 0.00421562 ; + max_transition : "1" ; + related_power_pin : VDD; + related_ground_pin : VSS; + internal_power() { + rise_power("scalar") { + values (0); + } + fall_power("scalar") { + values (0); + } + } + } + +bus(B_ADDR) { + bus_type : A_8_0; + direction : input ; + capacitance : 0.0115194 ; + pin(B_ADDR[0]) { + capacitance : 0.0056487 ; + } + pin(B_ADDR[1]) { + capacitance : 0.00741688 ; + } + pin(B_ADDR[2]) { + capacitance : 0.0100613 ; + } + pin(B_ADDR[3]) { + capacitance : 0.00667339 ; + } + pin(B_ADDR[4]) { + capacitance : 0.00620204 ; + } + pin(B_ADDR[5]) { + capacitance : 0.0101975 ; + } + pin(B_ADDR[6]) { + capacitance : 0.0124055 ; + } + pin(B_ADDR[7]) { + capacitance : 0.0101065 ; + } + max_transition : "0.38" ; + pin(B_ADDR[8:0]) { + related_power_pin : VDD; + related_ground_pin : VSS; + internal_power() { + when : "B_MEN"; + rise_power("scalar"){ + values (0.0115); + } + fall_power("scalar"){ + values (0.0021); + } + } + internal_power() { + when : "!B_MEN"; + rise_power("scalar"){ + values (0.0343); + } + fall_power("scalar"){ + values (0.0003); + } + } + } + timing() { + timing_type : setup_rising; + related_pin : "B_CLK"; + when : "((B_WEN | B_REN)& B_MEN)" + sdf_cond : "B_RW_ACCESS" + + rise_constraint("SIG2SRAM_constraint_template") { + index_1("0.0040,0.0176,0.0344,0.0656,0.1120,0.2016,0.3800"); + index_2("0.0040,0.0176,0.0344,0.0656,0.1120,0.2016,0.3800"); + values ("-0.2371,-0.2215,-0.2098,-0.1824,-0.1434,-0.0691,0.0676",\ +"-0.2449,-0.2332,-0.2176,-0.1902,-0.1551,-0.0770,0.0559",\ +"-0.2605,-0.2488,-0.2332,-0.2059,-0.1707,-0.0965,0.0441",\ +"-0.2879,-0.2723,-0.2605,-0.2332,-0.1941,-0.1199,0.0168",\ +"-0.3230,-0.3113,-0.2996,-0.2723,-0.2332,-0.1590,-0.0184",\ +"-0.4012,-0.3895,-0.3738,-0.3465,-0.3074,-0.2332,-0.0965",\ +"-0.5379,-0.5262,-0.5105,-0.4832,-0.4480,-0.3699,-0.2332"); + } + + fall_constraint("SIG2SRAM_constraint_template") { + index_1("0.0040,0.0176,0.0344,0.0656,0.1120,0.2016,0.3800"); + index_2("0.0040,0.0176,0.0344,0.0656,0.1120,0.2016,0.3800"); + values ("-0.1785,-0.1707,-0.1551,-0.1277,-0.0887,-0.0184,0.1145",\ +"-0.1902,-0.1785,-0.1629,-0.1355,-0.1004,-0.0262,0.1027",\ +"-0.2059,-0.1941,-0.1785,-0.1512,-0.1160,-0.0418,0.0871",\ +"-0.2293,-0.2176,-0.2059,-0.1785,-0.1434,-0.0691,0.0598",\ +"-0.2684,-0.2566,-0.2449,-0.2176,-0.1824,-0.1082,0.0207",\ +"-0.3465,-0.3348,-0.3191,-0.2918,-0.2566,-0.1824,-0.0535",\ +"-0.4832,-0.4715,-0.4559,-0.4324,-0.3934,-0.3191,-0.1902"); + } + } + + + timing() { + timing_type : hold_rising; + related_pin : "B_CLK"; + when : "((B_WEN | B_REN)& B_MEN)" + sdf_cond : "B_RW_ACCESS" + + rise_constraint("SIG2SRAM_constraint_template") { + index_1("0.0040,0.0176,0.0344,0.0656,0.1120,0.2016,0.3800"); + index_2("0.0040,0.0176,0.0344,0.0656,0.1120,0.2016,0.3800"); + values ("0.3410,0.3293,0.3137,0.2863,0.2473,0.1730,0.0324",\ +"0.3488,0.3371,0.3215,0.2941,0.2590,0.1809,0.0480",\ +"0.3684,0.3527,0.3371,0.3098,0.2746,0.1965,0.0598",\ +"0.3918,0.3762,0.3645,0.3371,0.2980,0.2238,0.0871",\ +"0.4309,0.4152,0.4035,0.3762,0.3371,0.2629,0.1223",\ +"0.5051,0.4934,0.4777,0.4504,0.4113,0.3371,0.1965",\ +"0.6418,0.6262,0.6145,0.5871,0.5520,0.4738,0.3332"); + } + + fall_constraint("SIG2SRAM_constraint_template") { + index_1("0.0040,0.0176,0.0344,0.0656,0.1120,0.2016,0.3800"); + index_2("0.0040,0.0176,0.0344,0.0656,0.1120,0.2016,0.3800"); + values ("0.2824,0.2707,0.2551,0.2277,0.1926,0.1184,-0.0105",\ +"0.2902,0.2785,0.2668,0.2395,0.2043,0.1301,0.0012",\ +"0.3059,0.2941,0.2824,0.2551,0.2199,0.1457,0.0168",\ +"0.3332,0.3215,0.3059,0.2785,0.2434,0.1691,0.0402",\ +"0.3723,0.3605,0.3449,0.3176,0.2824,0.2121,0.0793",\ +"0.4465,0.4348,0.4230,0.3918,0.3566,0.2824,0.1535",\ +"0.5832,0.5715,0.5598,0.5324,0.4934,0.4191,0.2902"); + } + } +} +pin(B_WEN) { + direction : input ; + capacitance : 0.00341384 ; + max_transition : "0.38" ; + related_power_pin : VDD; + related_ground_pin : VSS; + internal_power() { + when : "B_MEN"; + rise_power("scalar"){ + values (0.0083); + } + fall_power("scalar"){ + values (0.0107); + } + } + internal_power() { + when : "!B_MEN"; + rise_power("scalar"){ + values (0.0099); + } + fall_power("scalar"){ + values (0.0320); + } + } + timing() { + timing_type : setup_rising; + related_pin : "B_CLK"; + when : "B_MEN" + sdf_cond : "B_MEN" + + rise_constraint("SIG2SRAM_constraint_template") { + index_1("0.0040,0.0176,0.0344,0.0656,0.1120,0.2016,0.3800"); + index_2("0.0040,0.0176,0.0344,0.0656,0.1120,0.2016,0.3800"); + values ("0.1418,0.1496,0.1652,0.1887,0.2316,0.3059,0.4465",\ +"0.1301,0.1379,0.1535,0.1809,0.2199,0.2941,0.4348",\ +"0.1145,0.1262,0.1379,0.1652,0.2043,0.2785,0.4191",\ +"0.0871,0.0949,0.1105,0.1379,0.1770,0.2512,0.3879",\ +"0.0480,0.0598,0.0754,0.0988,0.1379,0.2082,0.3527",\ +"-0.0262,-0.0145,0.0012,0.0246,0.0676,0.1379,0.2785",\ +"-0.1668,-0.1551,-0.1395,-0.1121,-0.0730,0.0012,0.1418"); + } + + fall_constraint("SIG2SRAM_constraint_template") { + index_1("0.0040,0.0176,0.0344,0.0656,0.1120,0.2016,0.3800"); + index_2("0.0040,0.0176,0.0344,0.0656,0.1120,0.2016,0.3800"); + values ("0.2082,0.2160,0.2316,0.2590,0.2941,0.3684,0.5012",\ +"0.1926,0.2043,0.2199,0.2473,0.2824,0.3566,0.4895",\ +"0.1770,0.1887,0.2043,0.2316,0.2668,0.3410,0.4777",\ +"0.1535,0.1652,0.1770,0.2043,0.2395,0.3137,0.4504",\ +"0.1145,0.1262,0.1379,0.1652,0.2043,0.2746,0.4113",\ +"0.0402,0.0520,0.0676,0.0910,0.1262,0.2004,0.3332",\ +"-0.0965,-0.0848,-0.0730,-0.0457,-0.0066,0.0637,0.2004"); + } + } + + + timing() { + timing_type : hold_rising; + related_pin : "B_CLK"; + when : "B_MEN" + sdf_cond : "B_MEN" + + rise_constraint("SIG2SRAM_constraint_template") { + index_1("0.0040,0.0176,0.0344,0.0656,0.1120,0.2016,0.3800"); + index_2("0.0040,0.0176,0.0344,0.0656,0.1120,0.2016,0.3800"); + values ("0.1770,0.1652,0.1496,0.1223,0.0793,0.0090,-0.1316",\ +"0.1848,0.1730,0.1574,0.1301,0.0910,0.0168,-0.1199",\ +"0.2004,0.1887,0.1770,0.1496,0.1066,0.0363,-0.1043",\ +"0.2277,0.2160,0.2004,0.1730,0.1340,0.0598,-0.0809",\ +"0.2668,0.2551,0.2395,0.2121,0.1730,0.0988,-0.0418",\ +"0.3410,0.3293,0.3137,0.2863,0.2434,0.1730,0.0324",\ +"0.4816,0.4699,0.4543,0.4230,0.3801,0.3098,0.1730"); + } + + fall_constraint("SIG2SRAM_constraint_template") { + index_1("0.0040,0.0176,0.0344,0.0656,0.1120,0.2016,0.3800"); + index_2("0.0040,0.0176,0.0344,0.0656,0.1120,0.2016,0.3800"); + values ("0.1613,0.1496,0.1379,0.1066,0.0715,0.0012,-0.1355",\ +"0.1730,0.1613,0.1457,0.1184,0.0832,0.0129,-0.1238",\ +"0.1887,0.1770,0.1613,0.1340,0.0988,0.0246,-0.1121",\ +"0.2121,0.2043,0.1887,0.1613,0.1223,0.0520,-0.0848",\ +"0.2512,0.2434,0.2277,0.2004,0.1613,0.0910,-0.0457",\ +"0.3254,0.3176,0.3020,0.2746,0.2355,0.1652,0.0324",\ +"0.4660,0.4543,0.4387,0.4113,0.3723,0.3020,0.1691"); + } + } + } +pin(B_REN) { + direction : input ; + capacitance : 0.00390661 ; + max_transition : "0.38" ; + related_power_pin : VDD; + related_ground_pin : VSS; + internal_power() { + when : "B_MEN"; + rise_power("scalar"){ + values (0.0014); + } + fall_power("scalar"){ + values (0.0139); + } + } + internal_power() { + when : "!B_MEN"; + rise_power("scalar"){ + values (0.0211); + } + fall_power("scalar"){ + values (0.0216); + } + } + timing() { + timing_type : setup_rising; + related_pin : "B_CLK"; + when : "B_MEN" + sdf_cond : "B_MEN" + + rise_constraint("SIG2SRAM_constraint_template") { + index_1("0.0040,0.0176,0.0344,0.0656,0.1120,0.2016,0.3800"); + index_2("0.0040,0.0176,0.0344,0.0656,0.1120,0.2016,0.3800"); + values ("-0.0027,0.0090,0.0246,0.0520,0.0910,0.1613,0.3020",\ +"-0.0105,0.0012,0.0129,0.0363,0.0793,0.1535,0.2902",\ +"-0.0262,-0.0145,-0.0027,0.0246,0.0637,0.1379,0.2785",\ +"-0.0535,-0.0418,-0.0262,0.0012,0.0363,0.1105,0.2512",\ +"-0.0926,-0.0809,-0.0652,-0.0418,-0.0027,0.0715,0.2121",\ +"-0.1668,-0.1551,-0.1395,-0.1082,-0.0770,-0.0027,0.1379",\ +"-0.3035,-0.2918,-0.2762,-0.2488,-0.2137,-0.1434,-0.0027"); + } + + fall_constraint("SIG2SRAM_constraint_template") { + index_1("0.0040,0.0176,0.0344,0.0656,0.1120,0.2016,0.3800"); + index_2("0.0040,0.0176,0.0344,0.0656,0.1120,0.2016,0.3800"); + values ("0.0832,0.0949,0.1105,0.1379,0.1730,0.2473,0.3801",\ +"0.0754,0.0832,0.0988,0.1223,0.1613,0.2355,0.3684",\ +"0.0598,0.0676,0.0832,0.1066,0.1457,0.2121,0.3527",\ +"0.0324,0.0441,0.0598,0.0871,0.1223,0.1926,0.3293",\ +"-0.0066,0.0051,0.0168,0.0480,0.0832,0.1535,0.2902",\ +"-0.0809,-0.0691,-0.0574,-0.0301,0.0090,0.0832,0.2121",\ +"-0.2176,-0.2059,-0.1941,-0.1668,-0.1277,-0.0574,0.0793"); + } + } + + + timing() { + timing_type : hold_rising; + related_pin : "B_CLK"; + when : "B_MEN" + sdf_cond : "B_MEN" + + rise_constraint("SIG2SRAM_constraint_template") { + index_1("0.0040,0.0176,0.0344,0.0656,0.1120,0.2016,0.3800"); + index_2("0.0040,0.0176,0.0344,0.0656,0.1120,0.2016,0.3800"); + values ("0.1887,0.1770,0.1613,0.1340,0.0949,0.0207,-0.1160",\ +"0.1965,0.1848,0.1730,0.1457,0.1027,0.0324,-0.1082",\ +"0.2160,0.2004,0.1887,0.1613,0.1184,0.0480,-0.0926",\ +"0.2395,0.2277,0.2121,0.1848,0.1457,0.0715,-0.0652",\ +"0.2785,0.2668,0.2512,0.2238,0.1848,0.1105,-0.0262",\ +"0.3527,0.3410,0.3254,0.2980,0.2551,0.1848,0.0480",\ +"0.4934,0.4816,0.4660,0.4387,0.3957,0.3254,0.1887"); + } + + fall_constraint("SIG2SRAM_constraint_template") { + index_1("0.0040,0.0176,0.0344,0.0656,0.1120,0.2016,0.3800"); + index_2("0.0040,0.0176,0.0344,0.0656,0.1120,0.2016,0.3800"); + values ("0.1730,0.1613,0.1496,0.1184,0.0793,0.0129,-0.1238",\ +"0.1848,0.1730,0.1574,0.1301,0.0910,0.0207,-0.1121",\ +"0.2004,0.1887,0.1730,0.1457,0.1066,0.0363,-0.1004",\ +"0.2238,0.2121,0.2004,0.1691,0.1340,0.0598,-0.0730",\ +"0.2629,0.2512,0.2395,0.2121,0.1691,0.0988,-0.0340",\ +"0.3371,0.3254,0.3137,0.2863,0.2434,0.1730,0.0402",\ +"0.4777,0.4660,0.4504,0.4230,0.3840,0.3137,0.1809"); + } + } + } +pin(B_MEN) { + direction : input ; + capacitance : 0.00326046 ; + max_transition : "0.38" ; + related_power_pin : VDD; + related_ground_pin : VSS; + internal_power() { + rise_power("scalar"){ + values (0.3360); + } + fall_power("scalar"){ + values (0.0108); + } + } + timing() { + timing_type : setup_rising; + related_pin : "B_CLK"; + + rise_constraint("SIG2SRAM_constraint_template") { + index_1("0.0040,0.0176,0.0344,0.0656,0.1120,0.2016,0.3800"); + index_2("0.0040,0.0176,0.0344,0.0656,0.1120,0.2016,0.3800"); + values ("0.1418,0.1496,0.1652,0.1926,0.2316,0.3059,0.4465",\ +"0.1301,0.1379,0.1535,0.1809,0.2199,0.2941,0.4348",\ +"0.1145,0.1262,0.1418,0.1652,0.2043,0.2785,0.4191",\ +"0.0871,0.0949,0.1105,0.1379,0.1770,0.2512,0.3879",\ +"0.0480,0.0598,0.0754,0.0988,0.1379,0.2082,0.3488",\ +"-0.0262,-0.0145,0.0012,0.0285,0.0676,0.1379,0.2785",\ +"-0.1668,-0.1551,-0.1395,-0.1121,-0.0730,0.0012,0.1379"); + } + + fall_constraint("SIG2SRAM_constraint_template") { + index_1("0.0040,0.0176,0.0344,0.0656,0.1120,0.2016,0.3800"); + index_2("0.0040,0.0176,0.0344,0.0656,0.1120,0.2016,0.3800"); + values ("0.2082,0.2199,0.2316,0.2590,0.2980,0.3723,0.5051",\ +"0.1965,0.2082,0.2199,0.2473,0.2863,0.3605,0.4934",\ +"0.1809,0.1926,0.2043,0.2316,0.2707,0.3449,0.4777",\ +"0.1574,0.1691,0.1809,0.2082,0.2434,0.3176,0.4543",\ +"0.1145,0.1262,0.1418,0.1691,0.2043,0.2785,0.4113",\ +"0.0441,0.0559,0.0676,0.0949,0.1301,0.2004,0.3332",\ +"-0.0965,-0.0848,-0.0691,-0.0418,-0.0066,0.0676,0.2004"); + } + } + + + timing() { + timing_type : hold_rising; + related_pin : "B_CLK"; + + rise_constraint("SIG2SRAM_constraint_template") { + index_1("0.0040,0.0176,0.0344,0.0656,0.1120,0.2016,0.3800"); + index_2("0.0040,0.0176,0.0344,0.0656,0.1120,0.2016,0.3800"); + values ("0.1770,0.1652,0.1535,0.1262,0.0832,0.0129,-0.1277",\ +"0.1887,0.1770,0.1613,0.1340,0.0949,0.0207,-0.1199",\ +"0.2043,0.1926,0.1770,0.1496,0.1105,0.0363,-0.1043",\ +"0.2277,0.2160,0.2043,0.1770,0.1379,0.0598,-0.0770",\ +"0.2668,0.2551,0.2434,0.2160,0.1730,0.0988,-0.0379",\ +"0.3449,0.3332,0.3176,0.2902,0.2473,0.1730,0.0363",\ +"0.4816,0.4699,0.4543,0.4270,0.3840,0.3098,0.1770"); + } + + fall_constraint("SIG2SRAM_constraint_template") { + index_1("0.0040,0.0176,0.0344,0.0656,0.1120,0.2016,0.3800"); + index_2("0.0040,0.0176,0.0344,0.0656,0.1120,0.2016,0.3800"); + values ("0.1613,0.1496,0.1379,0.1105,0.0715,0.0012,-0.1355",\ +"0.1730,0.1613,0.1496,0.1184,0.0832,0.0129,-0.1238",\ +"0.1887,0.1770,0.1652,0.1340,0.0988,0.0285,-0.1121",\ +"0.2121,0.2043,0.1887,0.1613,0.1223,0.0520,-0.0848",\ +"0.2551,0.2434,0.2277,0.2004,0.1613,0.0910,-0.0418",\ +"0.3293,0.3176,0.3020,0.2746,0.2395,0.1652,0.0324",\ +"0.4660,0.4543,0.4426,0.4113,0.3762,0.3020,0.1691"); + } + } + } +bus(B_BM) { + bus_type : D_31_0; + direction : input ; + capacitance : 0.00334781 ; + max_transition : "0.38" ; + pin(B_BM[31:0]) { + related_power_pin : VDD; + related_ground_pin : VSS; + internal_power() { + when : "B_MEN"; + rise_power("scalar"){ + values (0.1471); + } + fall_power("scalar"){ + values (0.1374); + } + } + internal_power() { + when : "!B_MEN"; + rise_power("scalar"){ + values (0.1745); + } + fall_power("scalar"){ + values (0.1522); + } + } + } + timing() { + timing_type : setup_rising; + related_pin : "B_CLK"; + when : "(B_WEN & B_MEN)" + sdf_cond : "B_RW_ACCESS" + + rise_constraint("SIG2SRAM_constraint_template") { + index_1("0.0040,0.0176,0.0344,0.0656,0.1120,0.2016,0.3800"); + index_2("0.0040,0.0176,0.0344,0.0656,0.1120,0.2016,0.3800"); + values ("-0.2899,-0.2791,-0.2635,-0.2381,-0.1971,-0.1238,0.0109",\ +"-0.2937,-0.2830,-0.2674,-0.2420,-0.2010,-0.1277,0.0070",\ +"-0.2975,-0.2868,-0.2712,-0.2458,-0.2048,-0.1315,0.0032",\ +"-0.3008,-0.2900,-0.2744,-0.2490,-0.2080,-0.1348,-0.0000",\ +"-0.3132,-0.3025,-0.2869,-0.2615,-0.2205,-0.1472,-0.0125",\ +"-0.3308,-0.3201,-0.3045,-0.2791,-0.2381,-0.1648,-0.0301",\ +"-0.3584,-0.3476,-0.3320,-0.3066,-0.2656,-0.1923,-0.0576"); + } + + fall_constraint("SIG2SRAM_constraint_template") { + index_1("0.0040,0.0176,0.0344,0.0656,0.1120,0.2016,0.3800"); + index_2("0.0040,0.0176,0.0344,0.0656,0.1120,0.2016,0.3800"); + values ("-0.2664,-0.2547,-0.2420,-0.2147,-0.1776,-0.1043,0.0236",\ +"-0.2703,-0.2586,-0.2459,-0.2185,-0.1814,-0.1082,0.0197",\ +"-0.2741,-0.2624,-0.2497,-0.2223,-0.1852,-0.1120,0.0159",\ +"-0.2774,-0.2656,-0.2529,-0.2256,-0.1885,-0.1152,0.0127",\ +"-0.2898,-0.2781,-0.2654,-0.2380,-0.2009,-0.1277,0.0002",\ +"-0.3074,-0.2957,-0.2830,-0.2556,-0.2185,-0.1453,-0.0174",\ +"-0.3349,-0.3232,-0.3105,-0.2832,-0.2460,-0.1728,-0.0449"); + } + } + + + timing() { + timing_type : hold_rising; + related_pin : "B_CLK"; + when : "(B_WEN & B_MEN)" + sdf_cond : "B_RW_ACCESS" + + rise_constraint("SIG2SRAM_constraint_template") { + index_1("0.0040,0.0176,0.0344,0.0656,0.1120,0.2016,0.3800"); + index_2("0.0040,0.0176,0.0344,0.0656,0.1120,0.2016,0.3800"); + values ("0.3958,0.3861,0.3704,0.3441,0.3070,0.2328,0.0980",\ +"0.3997,0.3900,0.3743,0.3480,0.3109,0.2366,0.1019",\ +"0.4035,0.3938,0.3781,0.3518,0.3147,0.2404,0.1057",\ +"0.4068,0.3970,0.3814,0.3550,0.3179,0.2437,0.1089",\ +"0.4192,0.4095,0.3938,0.3675,0.3303,0.2561,0.1214",\ +"0.4368,0.4271,0.4114,0.3851,0.3480,0.2737,0.1390",\ +"0.4643,0.4546,0.4389,0.4126,0.3755,0.3013,0.1665"); + } + + fall_constraint("SIG2SRAM_constraint_template") { + index_1("0.0040,0.0176,0.0344,0.0656,0.1120,0.2016,0.3800"); + index_2("0.0040,0.0176,0.0344,0.0656,0.1120,0.2016,0.3800"); + values ("0.3675,0.3568,0.3431,0.3158,0.2796,0.2074,0.0775",\ +"0.3714,0.3607,0.3470,0.3196,0.2835,0.2112,0.0814",\ +"0.3752,0.3645,0.3508,0.3234,0.2873,0.2150,0.0852",\ +"0.3785,0.3677,0.3540,0.3267,0.2906,0.2183,0.0884",\ +"0.3909,0.3802,0.3665,0.3391,0.3030,0.2307,0.1009",\ +"0.4085,0.3978,0.3841,0.3567,0.3206,0.2484,0.1185",\ +"0.4360,0.4253,0.4116,0.3843,0.3481,0.2759,0.1460"); + } + } +} + pin(B_CLK) { + direction : input; + capacitance : 0.00389386; + max_transition : "0.38"; + clock : "true" ; + pin_func_type : active_rising ; + + timing () { + timing_type : "min_pulse_width"; + related_pin : "B_CLK"; + rise_constraint("CLKTRAN_constraint_template") { + index_1("0.004,0.38"); + values("0.12,0.12"); + } + } + + related_power_pin : VDD; + related_ground_pin : VSS; + + internal_power() { + when : "!B_MEN & !B_WEN & !B_REN"; + rise_power("scalar"){ + values (0); + } + fall_power("scalar"){ + values (0); + } + } + internal_power() { + when : "!B_MEN & B_WEN & !B_REN"; + rise_power("scalar"){ + values (0.6735); + } + fall_power("scalar"){ + values (0); + } + } + internal_power() { + when : "B_MEN & B_WEN & !B_REN"; + rise_power("scalar"){ + values (54.8620); + } + fall_power("scalar"){ + values (0); + } + } + internal_power() { + when : "B_MEN & B_WEN & B_REN"; + rise_power("scalar"){ + values (56.6091); + } + fall_power("scalar"){ + values (0); + } + } + internal_power() { + when : "B_MEN & !B_WEN & B_REN"; + rise_power("scalar"){ + values (45.3648); + } + fall_power("scalar"){ + values (0); + } + } + internal_power() { + when : "!B_MEN & !B_WEN & B_REN"; + rise_power("scalar"){ + values (0.4386); + } + fall_power("scalar"){ + values (0); + } + } + internal_power() { + when : "!B_MEN & B_WEN & B_REN"; + rise_power("scalar"){ + values (1.6639); + } + fall_power("scalar"){ + values (0); + } + } + internal_power() { + when : "B_MEN & !B_WEN & !B_REN"; + rise_power("scalar"){ + values (0); + } + fall_power("scalar"){ + values (0); + } + } + } + bus(B_DIN) { + bus_type : D_31_0; + direction : input ; + capacitance : 0.00468868 ; + memory_write() { + address : B_ADDR ; + clocked_on : B_CLK; + } + + max_transition : "0.38" ; + pin(B_DIN[31:0]) { + related_power_pin : VDD; + related_ground_pin : VSS; + internal_power() { + when : "B_MEN"; + rise_power("scalar"){ + values (0.1471); + } + fall_power("scalar"){ + values (0.1374); + } + } + internal_power() { + when : "!B_MEN"; + rise_power("scalar"){ + values (0.1745); + } + fall_power("scalar"){ + values (0.1522); + } + } + } + timing() { + timing_type : setup_rising; + related_pin : "B_CLK"; + when : "(B_WEN & B_MEN)"; + sdf_cond : "B_W_ACCESS"; + + rise_constraint("SIG2SRAM_constraint_template") { + index_1("0.0040,0.0176,0.0344,0.0656,0.1120,0.2016,0.3800"); + index_2("0.0040,0.0176,0.0344,0.0656,0.1120,0.2016,0.3800"); + values ("-0.2899,-0.2791,-0.2635,-0.2381,-0.1971,-0.1238,0.0109",\ +"-0.2937,-0.2830,-0.2674,-0.2420,-0.2010,-0.1277,0.0070",\ +"-0.2975,-0.2868,-0.2712,-0.2458,-0.2048,-0.1315,0.0032",\ +"-0.3008,-0.2900,-0.2744,-0.2490,-0.2080,-0.1348,-0.0000",\ +"-0.3132,-0.3025,-0.2869,-0.2615,-0.2205,-0.1472,-0.0125",\ +"-0.3308,-0.3201,-0.3045,-0.2791,-0.2381,-0.1648,-0.0301",\ +"-0.3584,-0.3476,-0.3320,-0.3066,-0.2656,-0.1923,-0.0576"); + } + + fall_constraint("SIG2SRAM_constraint_template") { + index_1("0.0040,0.0176,0.0344,0.0656,0.1120,0.2016,0.3800"); + index_2("0.0040,0.0176,0.0344,0.0656,0.1120,0.2016,0.3800"); + values ("-0.2664,-0.2547,-0.2420,-0.2147,-0.1776,-0.1043,0.0236",\ +"-0.2703,-0.2586,-0.2459,-0.2185,-0.1814,-0.1082,0.0197",\ +"-0.2741,-0.2624,-0.2497,-0.2223,-0.1852,-0.1120,0.0159",\ +"-0.2774,-0.2656,-0.2529,-0.2256,-0.1885,-0.1152,0.0127",\ +"-0.2898,-0.2781,-0.2654,-0.2380,-0.2009,-0.1277,0.0002",\ +"-0.3074,-0.2957,-0.2830,-0.2556,-0.2185,-0.1453,-0.0174",\ +"-0.3349,-0.3232,-0.3105,-0.2832,-0.2460,-0.1728,-0.0449"); + } + } + + timing() { + timing_type : hold_rising; + related_pin : "B_CLK"; + when : "(B_WEN & B_MEN)"; + sdf_cond : "B_W_ACCESS"; + + rise_constraint("SIG2SRAM_constraint_template") { + index_1("0.0040,0.0176,0.0344,0.0656,0.1120,0.2016,0.3800"); + index_2("0.0040,0.0176,0.0344,0.0656,0.1120,0.2016,0.3800"); + values ("0.3958,0.3861,0.3704,0.3441,0.3070,0.2328,0.0980",\ +"0.3997,0.3900,0.3743,0.3480,0.3109,0.2366,0.1019",\ +"0.4035,0.3938,0.3781,0.3518,0.3147,0.2404,0.1057",\ +"0.4068,0.3970,0.3814,0.3550,0.3179,0.2437,0.1089",\ +"0.4192,0.4095,0.3938,0.3675,0.3303,0.2561,0.1214",\ +"0.4368,0.4271,0.4114,0.3851,0.3480,0.2737,0.1390",\ +"0.4643,0.4546,0.4389,0.4126,0.3755,0.3013,0.1665"); + } + + fall_constraint("SIG2SRAM_constraint_template") { + index_1("0.0040,0.0176,0.0344,0.0656,0.1120,0.2016,0.3800"); + index_2("0.0040,0.0176,0.0344,0.0656,0.1120,0.2016,0.3800"); + values ("0.3675,0.3568,0.3431,0.3158,0.2796,0.2074,0.0775",\ +"0.3714,0.3607,0.3470,0.3196,0.2835,0.2112,0.0814",\ +"0.3752,0.3645,0.3508,0.3234,0.2873,0.2150,0.0852",\ +"0.3785,0.3677,0.3540,0.3267,0.2906,0.2183,0.0884",\ +"0.3909,0.3802,0.3665,0.3391,0.3030,0.2307,0.1009",\ +"0.4085,0.3978,0.3841,0.3567,0.3206,0.2484,0.1185",\ +"0.4360,0.4253,0.4116,0.3843,0.3481,0.2759,0.1460"); + } + } + } + + pin(B_BIST_EN) { + direction : input ; + capacitance : 0.00421562 ; + max_transition : "1" ; + related_power_pin : VDD; + related_ground_pin : VSS; + internal_power() { + rise_power("scalar") { + values (0); + } + fall_power("scalar") { + values (0); + } + } + } + +bus(B_BIST_ADDR) { + bus_type : A_8_0; + direction : input ; + capacitance : 0.0115194 ; + pin(B_BIST_ADDR[0]) { + capacitance : 0.0056487 ; + } + pin(B_BIST_ADDR[1]) { + capacitance : 0.00741688 ; + } + pin(B_BIST_ADDR[2]) { + capacitance : 0.0100613 ; + } + pin(B_BIST_ADDR[3]) { + capacitance : 0.00667339 ; + } + pin(B_BIST_ADDR[4]) { + capacitance : 0.00620204 ; + } + pin(B_BIST_ADDR[5]) { + capacitance : 0.0101975 ; + } + pin(B_BIST_ADDR[6]) { + capacitance : 0.0124055 ; + } + pin(B_BIST_ADDR[7]) { + capacitance : 0.0101065 ; + } + max_transition : "0.38" ; + pin(B_BIST_ADDR[8:0]) { + related_power_pin : VDD; + related_ground_pin : VSS; + internal_power() { + when : "B_BIST_MEN"; + rise_power("scalar"){ + values (0.0115); + } + fall_power("scalar"){ + values (0.0021); + } + } + internal_power() { + when : "!B_BIST_MEN"; + rise_power("scalar"){ + values (0.0343); + } + fall_power("scalar"){ + values (0.0003); + } + } + } + timing() { + timing_type : setup_rising; + related_pin : "B_BIST_CLK"; + when : "((B_BIST_WEN | B_BIST_REN)& B_BIST_MEN)" + sdf_cond : "B_BIST_RW_ACCESS" + + rise_constraint("SIG2SRAM_constraint_template") { + index_1("0.0040,0.0176,0.0344,0.0656,0.1120,0.2016,0.3800"); + index_2("0.0040,0.0176,0.0344,0.0656,0.1120,0.2016,0.3800"); + values ("-0.2371,-0.2215,-0.2098,-0.1824,-0.1434,-0.0691,0.0676",\ +"-0.2449,-0.2332,-0.2176,-0.1902,-0.1551,-0.0770,0.0559",\ +"-0.2605,-0.2488,-0.2332,-0.2059,-0.1707,-0.0965,0.0441",\ +"-0.2879,-0.2723,-0.2605,-0.2332,-0.1941,-0.1199,0.0168",\ +"-0.3230,-0.3113,-0.2996,-0.2723,-0.2332,-0.1590,-0.0184",\ +"-0.4012,-0.3895,-0.3738,-0.3465,-0.3074,-0.2332,-0.0965",\ +"-0.5379,-0.5262,-0.5105,-0.4832,-0.4480,-0.3699,-0.2332"); + } + + fall_constraint("SIG2SRAM_constraint_template") { + index_1("0.0040,0.0176,0.0344,0.0656,0.1120,0.2016,0.3800"); + index_2("0.0040,0.0176,0.0344,0.0656,0.1120,0.2016,0.3800"); + values ("-0.1785,-0.1707,-0.1551,-0.1277,-0.0887,-0.0184,0.1145",\ +"-0.1902,-0.1785,-0.1629,-0.1355,-0.1004,-0.0262,0.1027",\ +"-0.2059,-0.1941,-0.1785,-0.1512,-0.1160,-0.0418,0.0871",\ +"-0.2293,-0.2176,-0.2059,-0.1785,-0.1434,-0.0691,0.0598",\ +"-0.2684,-0.2566,-0.2449,-0.2176,-0.1824,-0.1082,0.0207",\ +"-0.3465,-0.3348,-0.3191,-0.2918,-0.2566,-0.1824,-0.0535",\ +"-0.4832,-0.4715,-0.4559,-0.4324,-0.3934,-0.3191,-0.1902"); + } + } + + + timing() { + timing_type : hold_rising; + related_pin : "B_BIST_CLK"; + when : "((B_BIST_WEN | B_BIST_REN)& B_BIST_MEN)" + sdf_cond : "B_BIST_RW_ACCESS" + + rise_constraint("SIG2SRAM_constraint_template") { + index_1("0.0040,0.0176,0.0344,0.0656,0.1120,0.2016,0.3800"); + index_2("0.0040,0.0176,0.0344,0.0656,0.1120,0.2016,0.3800"); + values ("0.3410,0.3293,0.3137,0.2863,0.2473,0.1730,0.0324",\ +"0.3488,0.3371,0.3215,0.2941,0.2590,0.1809,0.0480",\ +"0.3684,0.3527,0.3371,0.3098,0.2746,0.1965,0.0598",\ +"0.3918,0.3762,0.3645,0.3371,0.2980,0.2238,0.0871",\ +"0.4309,0.4152,0.4035,0.3762,0.3371,0.2629,0.1223",\ +"0.5051,0.4934,0.4777,0.4504,0.4113,0.3371,0.1965",\ +"0.6418,0.6262,0.6145,0.5871,0.5520,0.4738,0.3332"); + } + + fall_constraint("SIG2SRAM_constraint_template") { + index_1("0.0040,0.0176,0.0344,0.0656,0.1120,0.2016,0.3800"); + index_2("0.0040,0.0176,0.0344,0.0656,0.1120,0.2016,0.3800"); + values ("0.2824,0.2707,0.2551,0.2277,0.1926,0.1184,-0.0105",\ +"0.2902,0.2785,0.2668,0.2395,0.2043,0.1301,0.0012",\ +"0.3059,0.2941,0.2824,0.2551,0.2199,0.1457,0.0168",\ +"0.3332,0.3215,0.3059,0.2785,0.2434,0.1691,0.0402",\ +"0.3723,0.3605,0.3449,0.3176,0.2824,0.2121,0.0793",\ +"0.4465,0.4348,0.4230,0.3918,0.3566,0.2824,0.1535",\ +"0.5832,0.5715,0.5598,0.5324,0.4934,0.4191,0.2902"); + } + } +} +pin(B_BIST_WEN) { + direction : input ; + capacitance : 0.00341384 ; + max_transition : "0.38" ; + related_power_pin : VDD; + related_ground_pin : VSS; + internal_power() { + when : "B_BIST_MEN"; + rise_power("scalar"){ + values (0.0083); + } + fall_power("scalar"){ + values (0.0107); + } + } + internal_power() { + when : "!B_BIST_MEN"; + rise_power("scalar"){ + values (0.0099); + } + fall_power("scalar"){ + values (0.0320); + } + } + timing() { + timing_type : setup_rising; + related_pin : "B_BIST_CLK"; + when : "B_BIST_MEN" + sdf_cond : "B_BIST_MEN" + + rise_constraint("SIG2SRAM_constraint_template") { + index_1("0.0040,0.0176,0.0344,0.0656,0.1120,0.2016,0.3800"); + index_2("0.0040,0.0176,0.0344,0.0656,0.1120,0.2016,0.3800"); + values ("0.1418,0.1496,0.1652,0.1887,0.2316,0.3059,0.4465",\ +"0.1301,0.1379,0.1535,0.1809,0.2199,0.2941,0.4348",\ +"0.1145,0.1262,0.1379,0.1652,0.2043,0.2785,0.4191",\ +"0.0871,0.0949,0.1105,0.1379,0.1770,0.2512,0.3879",\ +"0.0480,0.0598,0.0754,0.0988,0.1379,0.2082,0.3527",\ +"-0.0262,-0.0145,0.0012,0.0246,0.0676,0.1379,0.2785",\ +"-0.1668,-0.1551,-0.1395,-0.1121,-0.0730,0.0012,0.1418"); + } + + fall_constraint("SIG2SRAM_constraint_template") { + index_1("0.0040,0.0176,0.0344,0.0656,0.1120,0.2016,0.3800"); + index_2("0.0040,0.0176,0.0344,0.0656,0.1120,0.2016,0.3800"); + values ("0.2082,0.2160,0.2316,0.2590,0.2941,0.3684,0.5012",\ +"0.1926,0.2043,0.2199,0.2473,0.2824,0.3566,0.4895",\ +"0.1770,0.1887,0.2043,0.2316,0.2668,0.3410,0.4777",\ +"0.1535,0.1652,0.1770,0.2043,0.2395,0.3137,0.4504",\ +"0.1145,0.1262,0.1379,0.1652,0.2043,0.2746,0.4113",\ +"0.0402,0.0520,0.0676,0.0910,0.1262,0.2004,0.3332",\ +"-0.0965,-0.0848,-0.0730,-0.0457,-0.0066,0.0637,0.2004"); + } + } + + + timing() { + timing_type : hold_rising; + related_pin : "B_BIST_CLK"; + when : "B_BIST_MEN" + sdf_cond : "B_BIST_MEN" + + rise_constraint("SIG2SRAM_constraint_template") { + index_1("0.0040,0.0176,0.0344,0.0656,0.1120,0.2016,0.3800"); + index_2("0.0040,0.0176,0.0344,0.0656,0.1120,0.2016,0.3800"); + values ("0.1770,0.1652,0.1496,0.1223,0.0793,0.0090,-0.1316",\ +"0.1848,0.1730,0.1574,0.1301,0.0910,0.0168,-0.1199",\ +"0.2004,0.1887,0.1770,0.1496,0.1066,0.0363,-0.1043",\ +"0.2277,0.2160,0.2004,0.1730,0.1340,0.0598,-0.0809",\ +"0.2668,0.2551,0.2395,0.2121,0.1730,0.0988,-0.0418",\ +"0.3410,0.3293,0.3137,0.2863,0.2434,0.1730,0.0324",\ +"0.4816,0.4699,0.4543,0.4230,0.3801,0.3098,0.1730"); + } + + fall_constraint("SIG2SRAM_constraint_template") { + index_1("0.0040,0.0176,0.0344,0.0656,0.1120,0.2016,0.3800"); + index_2("0.0040,0.0176,0.0344,0.0656,0.1120,0.2016,0.3800"); + values ("0.1613,0.1496,0.1379,0.1066,0.0715,0.0012,-0.1355",\ +"0.1730,0.1613,0.1457,0.1184,0.0832,0.0129,-0.1238",\ +"0.1887,0.1770,0.1613,0.1340,0.0988,0.0246,-0.1121",\ +"0.2121,0.2043,0.1887,0.1613,0.1223,0.0520,-0.0848",\ +"0.2512,0.2434,0.2277,0.2004,0.1613,0.0910,-0.0457",\ +"0.3254,0.3176,0.3020,0.2746,0.2355,0.1652,0.0324",\ +"0.4660,0.4543,0.4387,0.4113,0.3723,0.3020,0.1691"); + } + } + } +pin(B_BIST_REN) { + direction : input ; + capacitance : 0.00390661 ; + max_transition : "0.38" ; + related_power_pin : VDD; + related_ground_pin : VSS; + internal_power() { + when : "B_BIST_MEN"; + rise_power("scalar"){ + values (0.0014); + } + fall_power("scalar"){ + values (0.0139); + } + } + internal_power() { + when : "!B_BIST_MEN"; + rise_power("scalar"){ + values (0.0211); + } + fall_power("scalar"){ + values (0.0216); + } + } + timing() { + timing_type : setup_rising; + related_pin : "B_BIST_CLK"; + when : "B_BIST_MEN" + sdf_cond : "B_BIST_MEN" + + rise_constraint("SIG2SRAM_constraint_template") { + index_1("0.0040,0.0176,0.0344,0.0656,0.1120,0.2016,0.3800"); + index_2("0.0040,0.0176,0.0344,0.0656,0.1120,0.2016,0.3800"); + values ("-0.0027,0.0090,0.0246,0.0520,0.0910,0.1613,0.3020",\ +"-0.0105,0.0012,0.0129,0.0363,0.0793,0.1535,0.2902",\ +"-0.0262,-0.0145,-0.0027,0.0246,0.0637,0.1379,0.2785",\ +"-0.0535,-0.0418,-0.0262,0.0012,0.0363,0.1105,0.2512",\ +"-0.0926,-0.0809,-0.0652,-0.0418,-0.0027,0.0715,0.2121",\ +"-0.1668,-0.1551,-0.1395,-0.1082,-0.0770,-0.0027,0.1379",\ +"-0.3035,-0.2918,-0.2762,-0.2488,-0.2137,-0.1434,-0.0027"); + } + + fall_constraint("SIG2SRAM_constraint_template") { + index_1("0.0040,0.0176,0.0344,0.0656,0.1120,0.2016,0.3800"); + index_2("0.0040,0.0176,0.0344,0.0656,0.1120,0.2016,0.3800"); + values ("0.0832,0.0949,0.1105,0.1379,0.1730,0.2473,0.3801",\ +"0.0754,0.0832,0.0988,0.1223,0.1613,0.2355,0.3684",\ +"0.0598,0.0676,0.0832,0.1066,0.1457,0.2121,0.3527",\ +"0.0324,0.0441,0.0598,0.0871,0.1223,0.1926,0.3293",\ +"-0.0066,0.0051,0.0168,0.0480,0.0832,0.1535,0.2902",\ +"-0.0809,-0.0691,-0.0574,-0.0301,0.0090,0.0832,0.2121",\ +"-0.2176,-0.2059,-0.1941,-0.1668,-0.1277,-0.0574,0.0793"); + } + } + + + timing() { + timing_type : hold_rising; + related_pin : "B_BIST_CLK"; + when : "B_BIST_MEN" + sdf_cond : "B_BIST_MEN" + + rise_constraint("SIG2SRAM_constraint_template") { + index_1("0.0040,0.0176,0.0344,0.0656,0.1120,0.2016,0.3800"); + index_2("0.0040,0.0176,0.0344,0.0656,0.1120,0.2016,0.3800"); + values ("0.1887,0.1770,0.1613,0.1340,0.0949,0.0207,-0.1160",\ +"0.1965,0.1848,0.1730,0.1457,0.1027,0.0324,-0.1082",\ +"0.2160,0.2004,0.1887,0.1613,0.1184,0.0480,-0.0926",\ +"0.2395,0.2277,0.2121,0.1848,0.1457,0.0715,-0.0652",\ +"0.2785,0.2668,0.2512,0.2238,0.1848,0.1105,-0.0262",\ +"0.3527,0.3410,0.3254,0.2980,0.2551,0.1848,0.0480",\ +"0.4934,0.4816,0.4660,0.4387,0.3957,0.3254,0.1887"); + } + + fall_constraint("SIG2SRAM_constraint_template") { + index_1("0.0040,0.0176,0.0344,0.0656,0.1120,0.2016,0.3800"); + index_2("0.0040,0.0176,0.0344,0.0656,0.1120,0.2016,0.3800"); + values ("0.1730,0.1613,0.1496,0.1184,0.0793,0.0129,-0.1238",\ +"0.1848,0.1730,0.1574,0.1301,0.0910,0.0207,-0.1121",\ +"0.2004,0.1887,0.1730,0.1457,0.1066,0.0363,-0.1004",\ +"0.2238,0.2121,0.2004,0.1691,0.1340,0.0598,-0.0730",\ +"0.2629,0.2512,0.2395,0.2121,0.1691,0.0988,-0.0340",\ +"0.3371,0.3254,0.3137,0.2863,0.2434,0.1730,0.0402",\ +"0.4777,0.4660,0.4504,0.4230,0.3840,0.3137,0.1809"); + } + } + } +pin(B_BIST_MEN) { + direction : input ; + capacitance : 0.00326046 ; + max_transition : "0.38" ; + related_power_pin : VDD; + related_ground_pin : VSS; + internal_power() { + rise_power("scalar"){ + values (0.3360); + } + fall_power("scalar"){ + values (0.0108); + } + } + timing() { + timing_type : setup_rising; + related_pin : "B_BIST_CLK"; + + rise_constraint("SIG2SRAM_constraint_template") { + index_1("0.0040,0.0176,0.0344,0.0656,0.1120,0.2016,0.3800"); + index_2("0.0040,0.0176,0.0344,0.0656,0.1120,0.2016,0.3800"); + values ("0.1418,0.1496,0.1652,0.1926,0.2316,0.3059,0.4465",\ +"0.1301,0.1379,0.1535,0.1809,0.2199,0.2941,0.4348",\ +"0.1145,0.1262,0.1418,0.1652,0.2043,0.2785,0.4191",\ +"0.0871,0.0949,0.1105,0.1379,0.1770,0.2512,0.3879",\ +"0.0480,0.0598,0.0754,0.0988,0.1379,0.2082,0.3488",\ +"-0.0262,-0.0145,0.0012,0.0285,0.0676,0.1379,0.2785",\ +"-0.1668,-0.1551,-0.1395,-0.1121,-0.0730,0.0012,0.1379"); + } + + fall_constraint("SIG2SRAM_constraint_template") { + index_1("0.0040,0.0176,0.0344,0.0656,0.1120,0.2016,0.3800"); + index_2("0.0040,0.0176,0.0344,0.0656,0.1120,0.2016,0.3800"); + values ("0.2082,0.2199,0.2316,0.2590,0.2980,0.3723,0.5051",\ +"0.1965,0.2082,0.2199,0.2473,0.2863,0.3605,0.4934",\ +"0.1809,0.1926,0.2043,0.2316,0.2707,0.3449,0.4777",\ +"0.1574,0.1691,0.1809,0.2082,0.2434,0.3176,0.4543",\ +"0.1145,0.1262,0.1418,0.1691,0.2043,0.2785,0.4113",\ +"0.0441,0.0559,0.0676,0.0949,0.1301,0.2004,0.3332",\ +"-0.0965,-0.0848,-0.0691,-0.0418,-0.0066,0.0676,0.2004"); + } + } + + + timing() { + timing_type : hold_rising; + related_pin : "B_BIST_CLK"; + + rise_constraint("SIG2SRAM_constraint_template") { + index_1("0.0040,0.0176,0.0344,0.0656,0.1120,0.2016,0.3800"); + index_2("0.0040,0.0176,0.0344,0.0656,0.1120,0.2016,0.3800"); + values ("0.1770,0.1652,0.1535,0.1262,0.0832,0.0129,-0.1277",\ +"0.1887,0.1770,0.1613,0.1340,0.0949,0.0207,-0.1199",\ +"0.2043,0.1926,0.1770,0.1496,0.1105,0.0363,-0.1043",\ +"0.2277,0.2160,0.2043,0.1770,0.1379,0.0598,-0.0770",\ +"0.2668,0.2551,0.2434,0.2160,0.1730,0.0988,-0.0379",\ +"0.3449,0.3332,0.3176,0.2902,0.2473,0.1730,0.0363",\ +"0.4816,0.4699,0.4543,0.4270,0.3840,0.3098,0.1770"); + } + + fall_constraint("SIG2SRAM_constraint_template") { + index_1("0.0040,0.0176,0.0344,0.0656,0.1120,0.2016,0.3800"); + index_2("0.0040,0.0176,0.0344,0.0656,0.1120,0.2016,0.3800"); + values ("0.1613,0.1496,0.1379,0.1105,0.0715,0.0012,-0.1355",\ +"0.1730,0.1613,0.1496,0.1184,0.0832,0.0129,-0.1238",\ +"0.1887,0.1770,0.1652,0.1340,0.0988,0.0285,-0.1121",\ +"0.2121,0.2043,0.1887,0.1613,0.1223,0.0520,-0.0848",\ +"0.2551,0.2434,0.2277,0.2004,0.1613,0.0910,-0.0418",\ +"0.3293,0.3176,0.3020,0.2746,0.2395,0.1652,0.0324",\ +"0.4660,0.4543,0.4426,0.4113,0.3762,0.3020,0.1691"); + } + } + } +bus(B_BIST_BM) { + bus_type : D_31_0; + direction : input ; + capacitance : 0.00290564 ; + max_transition : "0.38" ; + pin(B_BIST_BM[31:0]) { + related_power_pin : VDD; + related_ground_pin : VSS; + internal_power() { + when : "B_BIST_MEN"; + rise_power("scalar"){ + values (0.1471); + } + fall_power("scalar"){ + values (0.1374); + } + } + internal_power() { + when : "!B_BIST_MEN"; + rise_power("scalar"){ + values (0.1745); + } + fall_power("scalar"){ + values (0.1522); + } + } + } + timing() { + timing_type : setup_rising; + related_pin : "B_BIST_CLK"; + when : "(B_BIST_WEN & B_BIST_MEN)" + sdf_cond : "B_BIST_RW_ACCESS" + + rise_constraint("SIG2SRAM_constraint_template") { + index_1("0.0040,0.0176,0.0344,0.0656,0.1120,0.2016,0.3800"); + index_2("0.0040,0.0176,0.0344,0.0656,0.1120,0.2016,0.3800"); + values ("-0.2899,-0.2791,-0.2635,-0.2381,-0.1971,-0.1238,0.0109",\ +"-0.2937,-0.2830,-0.2674,-0.2420,-0.2010,-0.1277,0.0070",\ +"-0.2975,-0.2868,-0.2712,-0.2458,-0.2048,-0.1315,0.0032",\ +"-0.3008,-0.2900,-0.2744,-0.2490,-0.2080,-0.1348,-0.0000",\ +"-0.3132,-0.3025,-0.2869,-0.2615,-0.2205,-0.1472,-0.0125",\ +"-0.3308,-0.3201,-0.3045,-0.2791,-0.2381,-0.1648,-0.0301",\ +"-0.3584,-0.3476,-0.3320,-0.3066,-0.2656,-0.1923,-0.0576"); + } + + fall_constraint("SIG2SRAM_constraint_template") { + index_1("0.0040,0.0176,0.0344,0.0656,0.1120,0.2016,0.3800"); + index_2("0.0040,0.0176,0.0344,0.0656,0.1120,0.2016,0.3800"); + values ("-0.2664,-0.2547,-0.2420,-0.2147,-0.1776,-0.1043,0.0236",\ +"-0.2703,-0.2586,-0.2459,-0.2185,-0.1814,-0.1082,0.0197",\ +"-0.2741,-0.2624,-0.2497,-0.2223,-0.1852,-0.1120,0.0159",\ +"-0.2774,-0.2656,-0.2529,-0.2256,-0.1885,-0.1152,0.0127",\ +"-0.2898,-0.2781,-0.2654,-0.2380,-0.2009,-0.1277,0.0002",\ +"-0.3074,-0.2957,-0.2830,-0.2556,-0.2185,-0.1453,-0.0174",\ +"-0.3349,-0.3232,-0.3105,-0.2832,-0.2460,-0.1728,-0.0449"); + } + } + + + timing() { + timing_type : hold_rising; + related_pin : "B_BIST_CLK"; + when : "(B_BIST_WEN & B_BIST_MEN)" + sdf_cond : "B_BIST_RW_ACCESS" + + rise_constraint("SIG2SRAM_constraint_template") { + index_1("0.0040,0.0176,0.0344,0.0656,0.1120,0.2016,0.3800"); + index_2("0.0040,0.0176,0.0344,0.0656,0.1120,0.2016,0.3800"); + values ("0.3958,0.3861,0.3704,0.3441,0.3070,0.2328,0.0980",\ +"0.3997,0.3900,0.3743,0.3480,0.3109,0.2366,0.1019",\ +"0.4035,0.3938,0.3781,0.3518,0.3147,0.2404,0.1057",\ +"0.4068,0.3970,0.3814,0.3550,0.3179,0.2437,0.1089",\ +"0.4192,0.4095,0.3938,0.3675,0.3303,0.2561,0.1214",\ +"0.4368,0.4271,0.4114,0.3851,0.3480,0.2737,0.1390",\ +"0.4643,0.4546,0.4389,0.4126,0.3755,0.3013,0.1665"); + } + + fall_constraint("SIG2SRAM_constraint_template") { + index_1("0.0040,0.0176,0.0344,0.0656,0.1120,0.2016,0.3800"); + index_2("0.0040,0.0176,0.0344,0.0656,0.1120,0.2016,0.3800"); + values ("0.3675,0.3568,0.3431,0.3158,0.2796,0.2074,0.0775",\ +"0.3714,0.3607,0.3470,0.3196,0.2835,0.2112,0.0814",\ +"0.3752,0.3645,0.3508,0.3234,0.2873,0.2150,0.0852",\ +"0.3785,0.3677,0.3540,0.3267,0.2906,0.2183,0.0884",\ +"0.3909,0.3802,0.3665,0.3391,0.3030,0.2307,0.1009",\ +"0.4085,0.3978,0.3841,0.3567,0.3206,0.2484,0.1185",\ +"0.4360,0.4253,0.4116,0.3843,0.3481,0.2759,0.1460"); + } + } +} + pin(B_BIST_CLK) { + direction : input; + capacitance : 0.00389386; + max_transition : "0.38"; + clock : "true" ; + pin_func_type : active_rising ; + + timing () { + timing_type : "min_pulse_width"; + related_pin : "B_BIST_CLK"; + rise_constraint("CLKTRAN_constraint_template") { + index_1("0.004,0.38"); + values("0.12,0.12"); + } + } + + related_power_pin : VDD; + related_ground_pin : VSS; + + internal_power() { + when : "!B_BIST_MEN & !B_BIST_WEN & !B_BIST_REN"; + rise_power("scalar"){ + values (0); + } + fall_power("scalar"){ + values (0); + } + } + internal_power() { + when : "!B_BIST_MEN & B_BIST_WEN & !B_BIST_REN"; + rise_power("scalar"){ + values (0.6735); + } + fall_power("scalar"){ + values (0); + } + } + internal_power() { + when : "B_BIST_MEN & B_BIST_WEN & !B_BIST_REN"; + rise_power("scalar"){ + values (54.8620); + } + fall_power("scalar"){ + values (0); + } + } + internal_power() { + when : "B_BIST_MEN & B_BIST_WEN & B_BIST_REN"; + rise_power("scalar"){ + values (56.6091); + } + fall_power("scalar"){ + values (0); + } + } + internal_power() { + when : "B_BIST_MEN & !B_BIST_WEN & B_BIST_REN"; + rise_power("scalar"){ + values (45.3648); + } + fall_power("scalar"){ + values (0); + } + } + internal_power() { + when : "!B_BIST_MEN & !B_BIST_WEN & B_BIST_REN"; + rise_power("scalar"){ + values (0.4386); + } + fall_power("scalar"){ + values (0); + } + } + internal_power() { + when : "!B_BIST_MEN & B_BIST_WEN & B_BIST_REN"; + rise_power("scalar"){ + values (1.6639); + } + fall_power("scalar"){ + values (0); + } + } + internal_power() { + when : "B_BIST_MEN & !B_BIST_WEN & !B_BIST_REN"; + rise_power("scalar"){ + values (0); + } + fall_power("scalar"){ + values (0); + } + } + } + bus(B_BIST_DIN) { + bus_type : D_31_0; + direction : input ; + capacitance : 0.00417898 ; + memory_write() { + address : B_BIST_ADDR ; + clocked_on : B_BIST_CLK; + } + + max_transition : "0.38" ; + pin(B_BIST_DIN[31:0]) { + related_power_pin : VDD; + related_ground_pin : VSS; + internal_power() { + when : "B_BIST_MEN"; + rise_power("scalar"){ + values (0.1471); + } + fall_power("scalar"){ + values (0.1374); + } + } + internal_power() { + when : "!B_BIST_MEN"; + rise_power("scalar"){ + values (0.1745); + } + fall_power("scalar"){ + values (0.1522); + } + } + } + timing() { + timing_type : setup_rising; + related_pin : "B_BIST_CLK"; + when : "(B_BIST_WEN & B_BIST_MEN)"; + sdf_cond : "B_BIST_W_ACCESS"; + + rise_constraint("SIG2SRAM_constraint_template") { + index_1("0.0040,0.0176,0.0344,0.0656,0.1120,0.2016,0.3800"); + index_2("0.0040,0.0176,0.0344,0.0656,0.1120,0.2016,0.3800"); + values ("-0.2899,-0.2791,-0.2635,-0.2381,-0.1971,-0.1238,0.0109",\ +"-0.2937,-0.2830,-0.2674,-0.2420,-0.2010,-0.1277,0.0070",\ +"-0.2975,-0.2868,-0.2712,-0.2458,-0.2048,-0.1315,0.0032",\ +"-0.3008,-0.2900,-0.2744,-0.2490,-0.2080,-0.1348,-0.0000",\ +"-0.3132,-0.3025,-0.2869,-0.2615,-0.2205,-0.1472,-0.0125",\ +"-0.3308,-0.3201,-0.3045,-0.2791,-0.2381,-0.1648,-0.0301",\ +"-0.3584,-0.3476,-0.3320,-0.3066,-0.2656,-0.1923,-0.0576"); + } + + fall_constraint("SIG2SRAM_constraint_template") { + index_1("0.0040,0.0176,0.0344,0.0656,0.1120,0.2016,0.3800"); + index_2("0.0040,0.0176,0.0344,0.0656,0.1120,0.2016,0.3800"); + values ("-0.2664,-0.2547,-0.2420,-0.2147,-0.1776,-0.1043,0.0236",\ +"-0.2703,-0.2586,-0.2459,-0.2185,-0.1814,-0.1082,0.0197",\ +"-0.2741,-0.2624,-0.2497,-0.2223,-0.1852,-0.1120,0.0159",\ +"-0.2774,-0.2656,-0.2529,-0.2256,-0.1885,-0.1152,0.0127",\ +"-0.2898,-0.2781,-0.2654,-0.2380,-0.2009,-0.1277,0.0002",\ +"-0.3074,-0.2957,-0.2830,-0.2556,-0.2185,-0.1453,-0.0174",\ +"-0.3349,-0.3232,-0.3105,-0.2832,-0.2460,-0.1728,-0.0449"); + } + } + + timing() { + timing_type : hold_rising; + related_pin : "B_BIST_CLK"; + when : "(B_BIST_WEN & B_BIST_MEN)"; + sdf_cond : "B_BIST_W_ACCESS"; + + rise_constraint("SIG2SRAM_constraint_template") { + index_1("0.0040,0.0176,0.0344,0.0656,0.1120,0.2016,0.3800"); + index_2("0.0040,0.0176,0.0344,0.0656,0.1120,0.2016,0.3800"); + values ("0.3958,0.3861,0.3704,0.3441,0.3070,0.2328,0.0980",\ +"0.3997,0.3900,0.3743,0.3480,0.3109,0.2366,0.1019",\ +"0.4035,0.3938,0.3781,0.3518,0.3147,0.2404,0.1057",\ +"0.4068,0.3970,0.3814,0.3550,0.3179,0.2437,0.1089",\ +"0.4192,0.4095,0.3938,0.3675,0.3303,0.2561,0.1214",\ +"0.4368,0.4271,0.4114,0.3851,0.3480,0.2737,0.1390",\ +"0.4643,0.4546,0.4389,0.4126,0.3755,0.3013,0.1665"); + } + + fall_constraint("SIG2SRAM_constraint_template") { + index_1("0.0040,0.0176,0.0344,0.0656,0.1120,0.2016,0.3800"); + index_2("0.0040,0.0176,0.0344,0.0656,0.1120,0.2016,0.3800"); + values ("0.3675,0.3568,0.3431,0.3158,0.2796,0.2074,0.0775",\ +"0.3714,0.3607,0.3470,0.3196,0.2835,0.2112,0.0814",\ +"0.3752,0.3645,0.3508,0.3234,0.2873,0.2150,0.0852",\ +"0.3785,0.3677,0.3540,0.3267,0.2906,0.2183,0.0884",\ +"0.3909,0.3802,0.3665,0.3391,0.3030,0.2307,0.1009",\ +"0.4085,0.3978,0.3841,0.3567,0.3206,0.2484,0.1185",\ +"0.4360,0.4253,0.4116,0.3843,0.3481,0.2759,0.1460"); + } + } + } + +bus(B_DOUT) { + + bus_type : D_31_0; + direction : output ; + capacitance : 0 ; + max_capacitance : 0.064 ; + memory_read() { + address : B_ADDR ; + } + pin(B_DOUT[31:0]) { + related_power_pin : VDD; + related_ground_pin : VSS; + internal_power() { + rise_power("scalar") { + values (0); + } + fall_power("scalar") { + values (0); + } + } + } + timing() { + related_pin : "B_CLK"; + timing_type : rising_edge ; + timing_sense : non_unate ; + + cell_rise(SIG2SRAM_delay_template) { + index_1("0.0040,0.0176,0.0344,0.0656,0.1120,0.2016,0.3800"); + index_2("0.0008,0.0014,0.0051,0.0100,0.0339,0.0640"); + values ("2.3870,2.3880,2.3928,2.3984,2.4193,2.4428",\ +"2.3934,2.3944,2.3992,2.4047,2.4257,2.4492",\ +"2.3950,2.3960,2.4008,2.4063,2.4273,2.4508",\ +"2.3993,2.4003,2.4052,2.4107,2.4316,2.4551",\ +"2.4125,2.4135,2.4183,2.4238,2.4447,2.4682",\ +"2.4311,2.4321,2.4369,2.4424,2.4633,2.4868",\ +"2.4576,2.4586,2.4634,2.4689,2.4898,2.5133"); + } + cell_fall(SIG2SRAM_delay_template) { + index_1("0.0040,0.0176,0.0344,0.0656,0.1120,0.2016,0.3800"); + index_2("0.0008,0.0014,0.0051,0.0100,0.0339,0.0640"); + values ("2.3527,2.3536,2.3576,2.3622,2.3793,2.3960",\ +"2.3591,2.3600,2.3640,2.3686,2.3857,2.4024",\ +"2.3607,2.3616,2.3656,2.3702,2.3873,2.4040",\ +"2.3650,2.3659,2.3699,2.3745,2.3916,2.4083",\ +"2.3782,2.3791,2.3831,2.3877,2.4047,2.4215",\ +"2.3968,2.3976,2.4017,2.4062,2.4233,2.4400",\ +"2.4233,2.4241,2.4282,2.4327,2.4498,2.4665"); + } + + rise_transition(SRAM_load_template) { + index_1("0.0008,0.0014,0.0051,0.0100,0.0339,0.0640"); + values ("0.0206,0.0210,0.0265,0.0323,0.0606,0.0955"); + } + fall_transition(SRAM_load_template) { + index_1("0.0008,0.0014,0.0051,0.0100,0.0339,0.0640"); + values ("0.0170,0.0177,0.0222,0.0270,0.0451,0.0644"); + } + } +} +cell_leakage_power : 903.4138; +} +} diff --git a/flow/platforms/ihp-sg13g2/lib/RM_IHPSG13_2P_512x32_c2_bm_bist_slow_1p08V_125C.lib b/flow/platforms/ihp-sg13g2/lib/RM_IHPSG13_2P_512x32_c2_bm_bist_slow_1p08V_125C.lib new file mode 100644 index 0000000000..6424e7e79c --- /dev/null +++ b/flow/platforms/ihp-sg13g2/lib/RM_IHPSG13_2P_512x32_c2_bm_bist_slow_1p08V_125C.lib @@ -0,0 +1,2886 @@ +/* ------------------------------------------------------*/ +/**/ +/* Copyright 2025 IHP PDK Authors*/ +/**/ +/* Licensed under the Apache License, Version 2.0 (the "License");*/ +/* you may not use this file except in compliance with the License.*/ +/* You may obtain a copy of the License at*/ +/* */ +/* https://www.apache.org/licenses/LICENSE-2.0*/ +/* */ +/* Unless required by applicable law or agreed to in writing, software*/ +/* distributed under the License is distributed on an "AS IS" BASIS,*/ +/* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.*/ +/* See the License for the specific language governing permissions and*/ +/* limitations under the License.*/ +/* */ +/* Generated on Wed Aug 27 13:11:27 2025 */ +/* */ +/* ------------------------------------------------------ */ +library(RM_IHPSG13_2P_512x32_c2_bm_bist_slow_1p08V_125C) { + technology (cmos) ; + delay_model : table_lookup ; + define ("add_pg_pin_to_lib", "library", "boolean"); + add_pg_pin_to_lib : true; + voltage_map ( VDD, 1.08); + voltage_map ( VDDARRAY, 1.08); + voltage_map ( VSS, 0.000000 ); + + date : "Wed Aug 27 13:11:26 2025" ; + comment : "IHP Microelectronics GmbH, 2023" ; + revision : 1.0.0 ; + simulation : true ; + nom_process : 1 ; + nom_temperature : 125 ; + nom_voltage : 1.08 ; + + operating_conditions("slow_1p08V_125C"){ + process : 1 ; + temperature : 125 ; + voltage : 1.08 ; + tree_type : "balanced_tree" ; + } + + default_operating_conditions : slow_1p08V_125C ; + default_max_transition : 1.0 ; + default_fanout_load : 1.0 ; + default_inout_pin_cap : 0.0 ; + default_input_pin_cap : 0.0 ; + default_output_pin_cap : 0.0 ; + default_cell_leakage_power : 0.0 ; + default_leakage_power_density : 0.0 ; + + slew_lower_threshold_pct_rise : 30 ; + slew_upper_threshold_pct_rise : 70 ; + input_threshold_pct_fall : 50 ; + output_threshold_pct_fall : 50 ; + input_threshold_pct_rise : 50 ; + output_threshold_pct_rise : 50 ; + slew_lower_threshold_pct_fall : 30 ; + slew_upper_threshold_pct_fall : 70 ; + slew_derate_from_library : 0.5; + k_volt_cell_leakage_power : 0.0 ; + k_temp_cell_leakage_power : 0.0 ; + k_process_cell_leakage_power : 0.0 ; + k_volt_internal_power : 0.0 ; + k_temp_internal_power : 0.0 ; + k_process_internal_power : 0.0 ; + + capacitive_load_unit (1,pf) ; + voltage_unit : "1V" ; + current_unit : "1uA" ; + time_unit : "1ns" ; + leakage_power_unit : "1nW" ; + pulling_resistance_unit : "1kohm"; + /* + ------------------------------------------------------------------------------------------ + implicit units overview: + cell_area unit : "um" + internal_power unit : "1e-12 * J/toggle = 1 * uW/MHz" + (capacitive_load_unit * voltage_unit^2) per toggle event + ------------------------------------------------------------------------------------------ + */ + library_features(report_delay_calculation); + define_cell_area (pad_drivers,pad_driver_sites) ; + + lu_table_template(CLKTRAN_constraint_template) { + variable_1 : constrained_pin_transition; + index_1 ( "0.010, 0.050, 0.200, 0.400, 1.000" ); + } + lu_table_template(SRAM_load_template) { + variable_1 : total_output_net_capacitance; + index_1 ( "0.0008,0.0014,0.0051,0.0100,0.0339,0.0640" ); + } + lu_table_template(SIG2SRAM_constraint_template) { + variable_1 : related_pin_transition; + variable_2 : constrained_pin_transition; + index_1 ( "0.0080,0.0288,0.0616,0.1072,0.1920,0.3496,0.5952" ); + index_2 ( "0.0080,0.0288,0.0616,0.1072,0.1920,0.3496,0.5952" ); + } + + lu_table_template(SIG2SRAM_delay_template) { + variable_1 : input_net_transition; + variable_2 : total_output_net_capacitance; + index_1 ( "0.0080,0.0288,0.0616,0.1072,0.1920,0.3496,0.5952" ); + index_2 ( "0.0008,0.0014,0.0051,0.0100,0.0339,0.0640" ); + } + + type (D_31_0) { + base_type : array; + data_type : bit; + bit_width : 32; + bit_from : 31; + bit_to : 0; + downto : true; + } + + type (A_8_0) { + base_type : array; + data_type : bit; + bit_width : 9; + bit_from : 8; + bit_to : 0; + downto : true; + } + +cell(RM_IHPSG13_2P_512x32_c2_bm_bist) { +pg_pin (VDD) { + pg_type : primary_power; + voltage_name : VDD; +} +pg_pin (VDDARRAY) { + pg_type : primary_power; + voltage_name : VDDARRAY; +} +pg_pin (VSS) { + pg_type : primary_ground; + voltage_name : VSS; +} + +memory() { + type : ram; + address_width : 9; + word_width : 32; +} + +interface_timing : false; +bus_naming_style : "%s[%d]" ; +area : 150650.1373 ; + + pin(A_DLY) { + direction : input ; + capacitance : 0.00387999 ; + max_transition : "1" ; + related_power_pin : VDD; + related_ground_pin : VSS; + internal_power() { + rise_power("scalar") { + values (0); + } + fall_power("scalar") { + values (0); + } + } + } + +bus(A_ADDR) { + bus_type : A_8_0; + direction : input ; + capacitance : 0.0129586 ; + pin(A_ADDR[0]) { + capacitance : 0.0058687 ; + } + pin(A_ADDR[1]) { + capacitance : 0.00807137 ; + } + pin(A_ADDR[2]) { + capacitance : 0.0112051 ; + } + pin(A_ADDR[3]) { + capacitance : 0.00709524 ; + } + pin(A_ADDR[4]) { + capacitance : 0.00648778 ; + } + pin(A_ADDR[5]) { + capacitance : 0.011209 ; + } + pin(A_ADDR[6]) { + capacitance : 0.0140441 ; + } + pin(A_ADDR[7]) { + capacitance : 0.0111199 ; + } + max_transition : "0.5952" ; + pin(A_ADDR[8:0]) { + related_power_pin : VDD; + related_ground_pin : VSS; + internal_power() { + when : "A_MEN"; + rise_power("scalar"){ + values (0.0100); + } + fall_power("scalar"){ + values (0.0075); + } + } + internal_power() { + when : "!A_MEN"; + rise_power("scalar"){ + values (0.0165); + } + fall_power("scalar"){ + values (0.0022); + } + } + } + timing() { + timing_type : setup_rising; + related_pin : "A_CLK"; + when : "((A_WEN | A_REN)& A_MEN)" + sdf_cond : "A_RW_ACCESS" + + rise_constraint("SIG2SRAM_constraint_template") { + index_1("0.0080,0.0288,0.0616,0.1072,0.1920,0.3496,0.5952"); + index_2("0.0080,0.0288,0.0616,0.1072,0.1920,0.3496,0.5952"); + values ("-0.7371,-0.7176,-0.6863,-0.6434,-0.5652,-0.4168,-0.1980",\ +"-0.7566,-0.7371,-0.7059,-0.6629,-0.5848,-0.4363,-0.2137",\ +"-0.7879,-0.7645,-0.7332,-0.6902,-0.6121,-0.4637,-0.2449",\ +"-0.8309,-0.8074,-0.7762,-0.7332,-0.6551,-0.5066,-0.2879",\ +"-0.9051,-0.8895,-0.8543,-0.8113,-0.7332,-0.5887,-0.3660",\ +"-1.0418,-1.0262,-0.9949,-0.9480,-0.8699,-0.7293,-0.5027",\ +"-1.2684,-1.2449,-1.2176,-1.1707,-1.0965,-0.9480,-0.7293"); + } + + fall_constraint("SIG2SRAM_constraint_template") { + index_1("0.0080,0.0288,0.0616,0.1072,0.1920,0.3496,0.5952"); + index_2("0.0080,0.0288,0.0616,0.1072,0.1920,0.3496,0.5952"); + values ("-0.5926,-0.5730,-0.5418,-0.4988,-0.4246,-0.2879,-0.0730",\ +"-0.6121,-0.5926,-0.5613,-0.5223,-0.4441,-0.3074,-0.0887",\ +"-0.6395,-0.6199,-0.5926,-0.5496,-0.4715,-0.3348,-0.1160",\ +"-0.6863,-0.6668,-0.6355,-0.5965,-0.5184,-0.3777,-0.1590",\ +"-0.7605,-0.7410,-0.7137,-0.6746,-0.5926,-0.4559,-0.2410",\ +"-0.9012,-0.8816,-0.8504,-0.8113,-0.7332,-0.5926,-0.3895",\ +"-1.1238,-1.1043,-1.0769,-1.0379,-0.9559,-0.8191,-0.6004"); + } + } + + + timing() { + timing_type : hold_rising; + related_pin : "A_CLK"; + when : "((A_WEN | A_REN)& A_MEN)" + sdf_cond : "A_RW_ACCESS" + + rise_constraint("SIG2SRAM_constraint_template") { + index_1("0.0080,0.0288,0.0616,0.1072,0.1920,0.3496,0.5952"); + index_2("0.0080,0.0288,0.0616,0.1072,0.1920,0.3496,0.5952"); + values ("0.8488,0.8293,0.7980,0.7551,0.6730,0.5285,0.3059",\ +"0.8684,0.8488,0.8176,0.7746,0.6926,0.5480,0.3254",\ +"0.8996,0.8801,0.8449,0.8020,0.7238,0.5754,0.3527",\ +"0.9426,0.9191,0.8918,0.8488,0.7668,0.6223,0.3996",\ +"1.0168,1.0012,0.9699,0.9230,0.8449,0.7004,0.4777",\ +"1.1574,1.1379,1.1105,1.0598,0.9816,0.8371,0.6184",\ +"1.3801,1.3605,1.3254,1.2980,1.2043,1.0637,0.8371"); + } + + fall_constraint("SIG2SRAM_constraint_template") { + index_1("0.0080,0.0288,0.0616,0.1072,0.1920,0.3496,0.5952"); + index_2("0.0080,0.0288,0.0616,0.1072,0.1920,0.3496,0.5952"); + values ("0.6965,0.6770,0.6496,0.6066,0.5246,0.3918,0.1730",\ +"0.7160,0.6965,0.6652,0.6262,0.5441,0.4113,0.1965",\ +"0.7473,0.7277,0.6965,0.6535,0.5754,0.4426,0.2238",\ +"0.7863,0.7707,0.7395,0.7004,0.6223,0.4855,0.2629",\ +"0.8684,0.8449,0.8176,0.7785,0.7004,0.5637,0.3449",\ +"1.0051,0.9855,0.9855,0.9113,0.8332,0.7004,0.4895",\ +"1.2277,1.2082,1.1809,1.1379,1.0598,0.9230,0.7004"); + } + } +} +pin(A_WEN) { + direction : input ; + capacitance : 0.00313551 ; + max_transition : "0.5952" ; + related_power_pin : VDD; + related_ground_pin : VSS; + internal_power() { + when : "A_MEN"; + rise_power("scalar"){ + values (0.0036); + } + fall_power("scalar"){ + values (0.0004); + } + } + internal_power() { + when : "!A_MEN"; + rise_power("scalar"){ + values (0.0051); + } + fall_power("scalar"){ + values (0.0001); + } + } + timing() { + timing_type : setup_rising; + related_pin : "A_CLK"; + when : "A_MEN" + sdf_cond : "A_MEN" + + rise_constraint("SIG2SRAM_constraint_template") { + index_1("0.0080,0.0288,0.0616,0.1072,0.1920,0.3496,0.5952"); + index_2("0.0080,0.0288,0.0616,0.1072,0.1920,0.3496,0.5952"); + values ("0.3137,0.3332,0.3605,0.4035,0.4816,0.6223,0.8488",\ +"0.2980,0.3176,0.3410,0.3840,0.4660,0.6027,0.8293",\ +"0.2629,0.2824,0.3098,0.3527,0.4348,0.5754,0.7980",\ +"0.2199,0.2395,0.2668,0.3098,0.3918,0.5324,0.7590",\ +"0.1418,0.1613,0.1887,0.2316,0.3137,0.4348,0.6730",\ +"0.0012,0.0207,0.0520,0.0910,0.1730,0.3098,0.5285",\ +"-0.2215,-0.2020,-0.1746,-0.1277,-0.0496,0.0910,0.3098"); + } + + fall_constraint("SIG2SRAM_constraint_template") { + index_1("0.0080,0.0288,0.0616,0.1072,0.1920,0.3496,0.5952"); + index_2("0.0080,0.0288,0.0616,0.1072,0.1920,0.3496,0.5952"); + values ("0.4504,0.4699,0.4973,0.5324,0.6027,0.7355,0.9699",\ +"0.4309,0.4504,0.4777,0.5129,0.5910,0.7160,0.9504",\ +"0.3996,0.4191,0.4465,0.4816,0.5520,0.6848,0.9191",\ +"0.3605,0.3762,0.4035,0.4387,0.5168,0.6418,0.8723",\ +"0.2785,0.2980,0.3215,0.3605,0.4348,0.5637,0.7980",\ +"0.1379,0.1574,0.1809,0.2199,0.2980,0.4309,0.6457",\ +"-0.0809,-0.0613,-0.0340,0.0051,0.0832,0.2160,0.4191"); + } + } + + + timing() { + timing_type : hold_rising; + related_pin : "A_CLK"; + when : "A_MEN" + sdf_cond : "A_MEN" + + rise_constraint("SIG2SRAM_constraint_template") { + index_1("0.0080,0.0288,0.0616,0.1072,0.1920,0.3496,0.5952"); + index_2("0.0080,0.0288,0.0616,0.1072,0.1920,0.3496,0.5952"); + values ("0.3723,0.3527,0.3215,0.2785,0.1965,0.0559,-0.1668",\ +"0.3918,0.3723,0.3449,0.2980,0.2160,0.0754,-0.1473",\ +"0.4152,0.3996,0.3684,0.3254,0.2434,0.1066,-0.1199",\ +"0.4621,0.4465,0.4152,0.3723,0.2863,0.1496,-0.0730",\ +"0.5324,0.5207,0.4895,0.4465,0.3645,0.2199,0.0051",\ +"0.6770,0.6535,0.6301,0.5832,0.5090,0.3605,0.1418",\ +"0.9035,0.8879,0.8566,0.8137,0.7316,0.5871,0.3684"); + } + + fall_constraint("SIG2SRAM_constraint_template") { + index_1("0.0080,0.0288,0.0616,0.1072,0.1920,0.3496,0.5952"); + index_2("0.0080,0.0288,0.0616,0.1072,0.1920,0.3496,0.5952"); + values ("0.3762,0.3566,0.3293,0.2863,0.2043,0.0676,-0.1434",\ +"0.3957,0.3762,0.3488,0.3059,0.2238,0.0871,-0.1199",\ +"0.4230,0.4035,0.3723,0.3332,0.2512,0.1184,-0.0965",\ +"0.4660,0.4465,0.4191,0.3762,0.2941,0.1613,-0.0496",\ +"0.5324,0.5168,0.4973,0.4543,0.3723,0.2316,0.0285",\ +"0.6809,0.6613,0.6340,0.5910,0.5129,0.3645,0.1652",\ +"0.9113,0.8918,0.8605,0.8176,0.7395,0.5988,0.3879"); + } + } + } +pin(A_REN) { + direction : input ; + capacitance : 0.00381144 ; + max_transition : "0.5952" ; + related_power_pin : VDD; + related_ground_pin : VSS; + internal_power() { + when : "A_MEN"; + rise_power("scalar"){ + values (0.0041); + } + fall_power("scalar"){ + values (0.0013); + } + } + internal_power() { + when : "!A_MEN"; + rise_power("scalar"){ + values (0.0043); + } + fall_power("scalar"){ + values (0.0010); + } + } + timing() { + timing_type : setup_rising; + related_pin : "A_CLK"; + when : "A_MEN" + sdf_cond : "A_MEN" + + rise_constraint("SIG2SRAM_constraint_template") { + index_1("0.0080,0.0288,0.0616,0.1072,0.1920,0.3496,0.5952"); + index_2("0.0080,0.0288,0.0616,0.1072,0.1920,0.3496,0.5952"); + values ("-0.0770,-0.0574,-0.0262,0.0168,0.0949,0.2355,0.4582",\ +"-0.0965,-0.0770,-0.0457,-0.0027,0.0754,0.2160,0.4387",\ +"-0.1199,-0.1004,-0.0730,-0.0262,0.0520,0.1887,0.4113",\ +"-0.1590,-0.1434,-0.1160,-0.0730,0.0051,0.1457,0.3645",\ +"-0.2449,-0.2254,-0.1941,-0.1473,-0.0770,0.0676,0.2863",\ +"-0.3816,-0.3699,-0.3387,-0.2801,-0.2215,-0.0770,0.1457",\ +"-0.6121,-0.5926,-0.5613,-0.5145,-0.4363,-0.2996,-0.0730"); + } + + fall_constraint("SIG2SRAM_constraint_template") { + index_1("0.0080,0.0288,0.0616,0.1072,0.1920,0.3496,0.5952"); + index_2("0.0080,0.0288,0.0616,0.1072,0.1920,0.3496,0.5952"); + values ("0.1262,0.1457,0.1691,0.2121,0.2824,0.4191,0.6457",\ +"0.1105,0.1262,0.1496,0.1887,0.2629,0.3996,0.6262",\ +"0.0793,0.0949,0.1223,0.1652,0.2395,0.3684,0.5949",\ +"0.0363,0.0559,0.0793,0.1223,0.2004,0.3410,0.5520",\ +"-0.0457,-0.0262,0.0012,0.0441,0.1301,0.2629,0.4738",\ +"-0.1902,-0.1746,-0.1434,-0.1043,-0.0184,0.1223,0.3332",\ +"-0.4129,-0.3934,-0.3660,-0.3230,-0.2449,-0.1043,0.1105"); + } + } + + + timing() { + timing_type : hold_rising; + related_pin : "A_CLK"; + when : "A_MEN" + sdf_cond : "A_MEN" + + rise_constraint("SIG2SRAM_constraint_template") { + index_1("0.0080,0.0288,0.0616,0.1072,0.1920,0.3496,0.5952"); + index_2("0.0080,0.0288,0.0616,0.1072,0.1920,0.3496,0.5952"); + values ("0.4113,0.3918,0.3645,0.3176,0.2395,0.0988,-0.1238",\ +"0.4309,0.4113,0.3840,0.3371,0.2590,0.1184,-0.1043",\ +"0.4582,0.4387,0.4113,0.3645,0.2824,0.1457,-0.0770",\ +"0.5051,0.4816,0.4543,0.4074,0.3293,0.1887,-0.0340",\ +"0.5715,0.5598,0.5324,0.4895,0.4035,0.2512,0.0441",\ +"0.7043,0.7004,0.6730,0.6262,0.5402,0.3957,0.1809",\ +"0.9387,0.9270,0.8957,0.8527,0.7746,0.6262,0.4074"); + } + + fall_constraint("SIG2SRAM_constraint_template") { + index_1("0.0080,0.0288,0.0616,0.1072,0.1920,0.3496,0.5952"); + index_2("0.0080,0.0288,0.0616,0.1072,0.1920,0.3496,0.5952"); + values ("0.4152,0.3918,0.3645,0.3215,0.2395,0.1027,-0.1082",\ +"0.4309,0.4113,0.3801,0.3410,0.2590,0.1223,-0.0926",\ +"0.4582,0.4387,0.4074,0.3684,0.2863,0.1496,-0.0613",\ +"0.5012,0.4816,0.4504,0.4074,0.3293,0.1887,-0.0145",\ +"0.5715,0.5559,0.5285,0.4816,0.3996,0.2512,0.0598",\ +"0.7160,0.7004,0.6691,0.6262,0.5520,0.4035,0.2004",\ +"0.9387,0.9191,0.8957,0.8488,0.7707,0.6262,0.4113"); + } + } + } +pin(A_MEN) { + direction : input ; + capacitance : 0.00300347 ; + max_transition : "0.5952" ; + related_power_pin : VDD; + related_ground_pin : VSS; + internal_power() { + rise_power("scalar"){ + values (0.0300); + } + fall_power("scalar"){ + values (0.0003); + } + } + timing() { + timing_type : setup_rising; + related_pin : "A_CLK"; + + rise_constraint("SIG2SRAM_constraint_template") { + index_1("0.0080,0.0288,0.0616,0.1072,0.1920,0.3496,0.5952"); + index_2("0.0080,0.0288,0.0616,0.1072,0.1920,0.3496,0.5952"); + values ("0.3215,0.3449,0.3684,0.4113,0.4895,0.6301,0.8527",\ +"0.3059,0.3254,0.3527,0.3957,0.4738,0.6145,0.8371",\ +"0.2746,0.2941,0.3215,0.3645,0.4426,0.5871,0.8059",\ +"0.2316,0.2512,0.2785,0.3215,0.3996,0.5402,0.7629",\ +"0.1496,0.1730,0.1965,0.2395,0.3215,0.4660,0.6848",\ +"0.0090,0.0285,0.0598,0.1027,0.1809,0.3176,0.5402",\ +"-0.2098,-0.1902,-0.1668,-0.1199,-0.0418,0.0988,0.3137"); + } + + fall_constraint("SIG2SRAM_constraint_template") { + index_1("0.0080,0.0288,0.0616,0.1072,0.1920,0.3496,0.5952"); + index_2("0.0080,0.0288,0.0616,0.1072,0.1920,0.3496,0.5952"); + values ("0.4582,0.4738,0.5012,0.5363,0.6145,0.7395,0.9738",\ +"0.4387,0.4543,0.4816,0.5207,0.5910,0.7199,0.9582",\ +"0.4035,0.4230,0.4504,0.4855,0.5637,0.6887,0.9230",\ +"0.3645,0.3840,0.4074,0.4465,0.5285,0.6496,0.8840",\ +"0.2824,0.3020,0.3254,0.3645,0.4465,0.5715,0.7980",\ +"0.1418,0.1613,0.1887,0.2238,0.3020,0.4309,0.6496",\ +"-0.0770,-0.0574,-0.0301,0.0090,0.0910,0.2238,0.4191"); + } + } + + + timing() { + timing_type : hold_rising; + related_pin : "A_CLK"; + + rise_constraint("SIG2SRAM_constraint_template") { + index_1("0.0080,0.0288,0.0616,0.1072,0.1920,0.3496,0.5952"); + index_2("0.0080,0.0288,0.0616,0.1072,0.1920,0.3496,0.5952"); + values ("0.3762,0.3605,0.3293,0.2863,0.2043,0.0637,-0.1629",\ +"0.3996,0.3801,0.3488,0.3020,0.2238,0.0832,-0.1395",\ +"0.4230,0.4074,0.3723,0.3293,0.2473,0.1105,-0.1121",\ +"0.4621,0.4465,0.4152,0.3762,0.2941,0.1535,-0.0691",\ +"0.5441,0.5285,0.4973,0.4465,0.3684,0.2316,0.0090",\ +"0.6848,0.6652,0.6301,0.5910,0.5129,0.3605,0.1496",\ +"0.9074,0.8918,0.8566,0.8215,0.7395,0.5910,0.3723"); + } + + fall_constraint("SIG2SRAM_constraint_template") { + index_1("0.0080,0.0288,0.0616,0.1072,0.1920,0.3496,0.5952"); + index_2("0.0080,0.0288,0.0616,0.1072,0.1920,0.3496,0.5952"); + values ("0.3762,0.3605,0.3332,0.2863,0.2043,0.0715,-0.1395",\ +"0.3996,0.3762,0.3488,0.3059,0.2238,0.0910,-0.1199",\ +"0.4270,0.4035,0.3762,0.3332,0.2512,0.1184,-0.0965",\ +"0.4699,0.4504,0.4191,0.3762,0.2941,0.1613,-0.0496",\ +"0.5441,0.5285,0.4973,0.4543,0.3762,0.2355,0.0324",\ +"0.6770,0.6613,0.6340,0.5949,0.5207,0.3762,0.1652",\ +"0.9074,0.8918,0.8605,0.8176,0.7395,0.6027,0.3918"); + } + } + } +bus(A_BM) { + bus_type : D_31_0; + direction : input ; + capacitance : 0.00359979 ; + max_transition : "0.5952" ; + pin(A_BM[31:0]) { + related_power_pin : VDD; + related_ground_pin : VSS; + internal_power() { + when : "A_MEN"; + rise_power("scalar"){ + values (0.0936); + } + fall_power("scalar"){ + values (0.0303); + } + } + internal_power() { + when : "!A_MEN"; + rise_power("scalar"){ + values (0.0900); + } + fall_power("scalar"){ + values (0.0290); + } + } + } + timing() { + timing_type : setup_rising; + related_pin : "A_CLK"; + when : "(A_WEN & A_MEN)" + sdf_cond : "A_RW_ACCESS" + + rise_constraint("SIG2SRAM_constraint_template") { + index_1("0.0080,0.0288,0.0616,0.1072,0.1920,0.3496,0.5952"); + index_2("0.0080,0.0288,0.0616,0.1072,0.1920,0.3496,0.5952"); + values ("-0.9175,-0.8980,-0.8726,-0.8296,-0.7485,-0.6030,-0.3804",\ +"-0.9250,-0.9054,-0.8800,-0.8371,-0.7560,-0.6105,-0.3878",\ +"-0.9345,-0.9150,-0.8896,-0.8467,-0.7656,-0.6201,-0.3974",\ +"-0.9477,-0.9282,-0.9028,-0.8598,-0.7787,-0.6332,-0.4106",\ +"-0.9719,-0.9524,-0.9270,-0.8841,-0.8030,-0.6575,-0.4348",\ +"-1.0024,-0.9828,-0.9575,-0.9145,-0.8334,-0.6879,-0.4653",\ +"-1.0840,-1.0645,-1.0391,-0.9961,-0.9150,-0.7695,-0.5469"); + } + + fall_constraint("SIG2SRAM_constraint_template") { + index_1("0.0080,0.0288,0.0616,0.1072,0.1920,0.3496,0.5952"); + index_2("0.0080,0.0288,0.0616,0.1072,0.1920,0.3496,0.5952"); + values ("-0.8550,-0.8374,-0.8101,-0.7710,-0.6880,-0.5523,-0.3403",\ +"-0.8625,-0.8449,-0.8175,-0.7785,-0.6955,-0.5597,-0.3478",\ +"-0.8720,-0.8545,-0.8271,-0.7881,-0.7050,-0.5693,-0.3574",\ +"-0.8852,-0.8676,-0.8403,-0.8012,-0.7182,-0.5825,-0.3705",\ +"-0.9094,-0.8919,-0.8645,-0.8255,-0.7424,-0.6067,-0.3948",\ +"-0.9399,-0.9223,-0.8950,-0.8559,-0.7729,-0.6371,-0.4252",\ +"-1.0215,-1.0039,-0.9766,-0.9375,-0.8545,-0.7188,-0.5069"); + } + } + + + timing() { + timing_type : hold_rising; + related_pin : "A_CLK"; + when : "(A_WEN & A_MEN)" + sdf_cond : "A_RW_ACCESS" + + rise_constraint("SIG2SRAM_constraint_template") { + index_1("0.0080,0.0288,0.0616,0.1072,0.1920,0.3496,0.5952"); + index_2("0.0080,0.0288,0.0616,0.1072,0.1920,0.3496,0.5952"); + values ("1.0343,1.0128,0.9884,0.9454,0.8653,0.7189,0.4962",\ +"1.0418,1.0203,0.9959,0.9529,0.8728,0.7263,0.5037",\ +"1.0513,1.0298,1.0054,0.9625,0.8824,0.7359,0.5132",\ +"1.0645,1.0430,1.0186,0.9756,0.8955,0.7491,0.5264",\ +"1.0887,1.0673,1.0428,0.9999,0.9198,0.7733,0.5507",\ +"1.1192,1.0977,1.0733,1.0303,0.9502,0.8037,0.5811",\ +"1.2008,1.1793,1.1549,1.1119,1.0318,0.8854,0.6627"); + } + + fall_constraint("SIG2SRAM_constraint_template") { + index_1("0.0080,0.0288,0.0616,0.1072,0.1920,0.3496,0.5952"); + index_2("0.0080,0.0288,0.0616,0.1072,0.1920,0.3496,0.5952"); + values ("0.9601,0.9425,0.9151,0.8761,0.7931,0.6564,0.4454",\ +"0.9675,0.9500,0.9226,0.8836,0.8005,0.6638,0.4529",\ +"0.9771,0.9595,0.9322,0.8931,0.8101,0.6734,0.4625",\ +"0.9903,0.9727,0.9453,0.9063,0.8233,0.6866,0.4756",\ +"1.0145,0.9969,0.9696,0.9305,0.8475,0.7108,0.4999",\ +"1.0450,1.0274,1.0000,0.9610,0.8780,0.7412,0.5303",\ +"1.1266,1.1090,1.0817,1.0426,0.9596,0.8229,0.6119"); + } + } +} + pin(A_CLK) { + direction : input; + capacitance : 0.00378957; + max_transition : "0.5952"; + clock : "true" ; + pin_func_type : active_rising ; + + timing () { + timing_type : "min_pulse_width"; + related_pin : "A_CLK"; + rise_constraint("CLKTRAN_constraint_template") { + index_1("0.008,0.5952"); + values("0.4,0.4"); + } + } + + related_power_pin : VDD; + related_ground_pin : VSS; + + internal_power() { + when : "!A_MEN & !A_WEN & !A_REN"; + rise_power("scalar"){ + values (0); + } + fall_power("scalar"){ + values (0); + } + } + internal_power() { + when : "!A_MEN & A_WEN & !A_REN"; + rise_power("scalar"){ + values (0.5614); + } + fall_power("scalar"){ + values (0); + } + } + internal_power() { + when : "A_MEN & A_WEN & !A_REN"; + rise_power("scalar"){ + values (35.0454); + } + fall_power("scalar"){ + values (0); + } + } + internal_power() { + when : "A_MEN & A_WEN & A_REN"; + rise_power("scalar"){ + values (37.3908); + } + fall_power("scalar"){ + values (0); + } + } + internal_power() { + when : "A_MEN & !A_WEN & A_REN"; + rise_power("scalar"){ + values (29.1692); + } + fall_power("scalar"){ + values (0); + } + } + internal_power() { + when : "!A_MEN & !A_WEN & A_REN"; + rise_power("scalar"){ + values (0.3780); + } + fall_power("scalar"){ + values (0); + } + } + internal_power() { + when : "!A_MEN & A_WEN & A_REN"; + rise_power("scalar"){ + values (1.1082); + } + fall_power("scalar"){ + values (0); + } + } + internal_power() { + when : "A_MEN & !A_WEN & !A_REN"; + rise_power("scalar"){ + values (0); + } + fall_power("scalar"){ + values (0); + } + } + } + bus(A_DIN) { + bus_type : D_31_0; + direction : input ; + capacitance : 0.00502163 ; + memory_write() { + address : A_ADDR ; + clocked_on : A_CLK; + } + + max_transition : "0.5952" ; + pin(A_DIN[31:0]) { + related_power_pin : VDD; + related_ground_pin : VSS; + internal_power() { + when : "A_MEN"; + rise_power("scalar"){ + values (0.0936); + } + fall_power("scalar"){ + values (0.0303); + } + } + internal_power() { + when : "!A_MEN"; + rise_power("scalar"){ + values (0.0900); + } + fall_power("scalar"){ + values (0.0290); + } + } + } + timing() { + timing_type : setup_rising; + related_pin : "A_CLK"; + when : "(A_WEN & A_MEN)"; + sdf_cond : "A_W_ACCESS"; + + rise_constraint("SIG2SRAM_constraint_template") { + index_1("0.0080,0.0288,0.0616,0.1072,0.1920,0.3496,0.5952"); + index_2("0.0080,0.0288,0.0616,0.1072,0.1920,0.3496,0.5952"); + values ("-0.9175,-0.8980,-0.8726,-0.8296,-0.7485,-0.6030,-0.3804",\ +"-0.9250,-0.9054,-0.8800,-0.8371,-0.7560,-0.6105,-0.3878",\ +"-0.9345,-0.9150,-0.8896,-0.8467,-0.7656,-0.6201,-0.3974",\ +"-0.9477,-0.9282,-0.9028,-0.8598,-0.7787,-0.6332,-0.4106",\ +"-0.9719,-0.9524,-0.9270,-0.8841,-0.8030,-0.6575,-0.4348",\ +"-1.0024,-0.9828,-0.9575,-0.9145,-0.8334,-0.6879,-0.4653",\ +"-1.0840,-1.0645,-1.0391,-0.9961,-0.9150,-0.7695,-0.5469"); + } + + fall_constraint("SIG2SRAM_constraint_template") { + index_1("0.0080,0.0288,0.0616,0.1072,0.1920,0.3496,0.5952"); + index_2("0.0080,0.0288,0.0616,0.1072,0.1920,0.3496,0.5952"); + values ("-0.8550,-0.8374,-0.8101,-0.7710,-0.6880,-0.5523,-0.3403",\ +"-0.8625,-0.8449,-0.8175,-0.7785,-0.6955,-0.5597,-0.3478",\ +"-0.8720,-0.8545,-0.8271,-0.7881,-0.7050,-0.5693,-0.3574",\ +"-0.8852,-0.8676,-0.8403,-0.8012,-0.7182,-0.5825,-0.3705",\ +"-0.9094,-0.8919,-0.8645,-0.8255,-0.7424,-0.6067,-0.3948",\ +"-0.9399,-0.9223,-0.8950,-0.8559,-0.7729,-0.6371,-0.4252",\ +"-1.0215,-1.0039,-0.9766,-0.9375,-0.8545,-0.7188,-0.5069"); + } + } + + timing() { + timing_type : hold_rising; + related_pin : "A_CLK"; + when : "(A_WEN & A_MEN)"; + sdf_cond : "A_W_ACCESS"; + + rise_constraint("SIG2SRAM_constraint_template") { + index_1("0.0080,0.0288,0.0616,0.1072,0.1920,0.3496,0.5952"); + index_2("0.0080,0.0288,0.0616,0.1072,0.1920,0.3496,0.5952"); + values ("1.0343,1.0128,0.9884,0.9454,0.8653,0.7189,0.4962",\ +"1.0418,1.0203,0.9959,0.9529,0.8728,0.7263,0.5037",\ +"1.0513,1.0298,1.0054,0.9625,0.8824,0.7359,0.5132",\ +"1.0645,1.0430,1.0186,0.9756,0.8955,0.7491,0.5264",\ +"1.0887,1.0673,1.0428,0.9999,0.9198,0.7733,0.5507",\ +"1.1192,1.0977,1.0733,1.0303,0.9502,0.8037,0.5811",\ +"1.2008,1.1793,1.1549,1.1119,1.0318,0.8854,0.6627"); + } + + fall_constraint("SIG2SRAM_constraint_template") { + index_1("0.0080,0.0288,0.0616,0.1072,0.1920,0.3496,0.5952"); + index_2("0.0080,0.0288,0.0616,0.1072,0.1920,0.3496,0.5952"); + values ("0.9601,0.9425,0.9151,0.8761,0.7931,0.6564,0.4454",\ +"0.9675,0.9500,0.9226,0.8836,0.8005,0.6638,0.4529",\ +"0.9771,0.9595,0.9322,0.8931,0.8101,0.6734,0.4625",\ +"0.9903,0.9727,0.9453,0.9063,0.8233,0.6866,0.4756",\ +"1.0145,0.9969,0.9696,0.9305,0.8475,0.7108,0.4999",\ +"1.0450,1.0274,1.0000,0.9610,0.8780,0.7412,0.5303",\ +"1.1266,1.1090,1.0817,1.0426,0.9596,0.8229,0.6119"); + } + } + } + + pin(A_BIST_EN) { + direction : input ; + capacitance : 0.00387999 ; + max_transition : "1" ; + related_power_pin : VDD; + related_ground_pin : VSS; + internal_power() { + rise_power("scalar") { + values (0); + } + fall_power("scalar") { + values (0); + } + } + } + +bus(A_BIST_ADDR) { + bus_type : A_8_0; + direction : input ; + capacitance : 0.0129586 ; + pin(A_BIST_ADDR[0]) { + capacitance : 0.0058687 ; + } + pin(A_BIST_ADDR[1]) { + capacitance : 0.00807137 ; + } + pin(A_BIST_ADDR[2]) { + capacitance : 0.0112051 ; + } + pin(A_BIST_ADDR[3]) { + capacitance : 0.00709524 ; + } + pin(A_BIST_ADDR[4]) { + capacitance : 0.00648778 ; + } + pin(A_BIST_ADDR[5]) { + capacitance : 0.011209 ; + } + pin(A_BIST_ADDR[6]) { + capacitance : 0.0140441 ; + } + pin(A_BIST_ADDR[7]) { + capacitance : 0.0111199 ; + } + max_transition : "0.5952" ; + pin(A_BIST_ADDR[8:0]) { + related_power_pin : VDD; + related_ground_pin : VSS; + internal_power() { + when : "A_BIST_MEN"; + rise_power("scalar"){ + values (0.0100); + } + fall_power("scalar"){ + values (0.0075); + } + } + internal_power() { + when : "!A_BIST_MEN"; + rise_power("scalar"){ + values (0.0165); + } + fall_power("scalar"){ + values (0.0022); + } + } + } + timing() { + timing_type : setup_rising; + related_pin : "A_BIST_CLK"; + when : "((A_BIST_WEN | A_BIST_REN)& A_BIST_MEN)" + sdf_cond : "A_BIST_RW_ACCESS" + + rise_constraint("SIG2SRAM_constraint_template") { + index_1("0.0080,0.0288,0.0616,0.1072,0.1920,0.3496,0.5952"); + index_2("0.0080,0.0288,0.0616,0.1072,0.1920,0.3496,0.5952"); + values ("-0.7371,-0.7176,-0.6863,-0.6434,-0.5652,-0.4168,-0.1980",\ +"-0.7566,-0.7371,-0.7059,-0.6629,-0.5848,-0.4363,-0.2137",\ +"-0.7879,-0.7645,-0.7332,-0.6902,-0.6121,-0.4637,-0.2449",\ +"-0.8309,-0.8074,-0.7762,-0.7332,-0.6551,-0.5066,-0.2879",\ +"-0.9051,-0.8895,-0.8543,-0.8113,-0.7332,-0.5887,-0.3660",\ +"-1.0418,-1.0262,-0.9949,-0.9480,-0.8699,-0.7293,-0.5027",\ +"-1.2684,-1.2449,-1.2176,-1.1707,-1.0965,-0.9480,-0.7293"); + } + + fall_constraint("SIG2SRAM_constraint_template") { + index_1("0.0080,0.0288,0.0616,0.1072,0.1920,0.3496,0.5952"); + index_2("0.0080,0.0288,0.0616,0.1072,0.1920,0.3496,0.5952"); + values ("-0.5926,-0.5730,-0.5418,-0.4988,-0.4246,-0.2879,-0.0730",\ +"-0.6121,-0.5926,-0.5613,-0.5223,-0.4441,-0.3074,-0.0887",\ +"-0.6395,-0.6199,-0.5926,-0.5496,-0.4715,-0.3348,-0.1160",\ +"-0.6863,-0.6668,-0.6355,-0.5965,-0.5184,-0.3777,-0.1590",\ +"-0.7605,-0.7410,-0.7137,-0.6746,-0.5926,-0.4559,-0.2410",\ +"-0.9012,-0.8816,-0.8504,-0.8113,-0.7332,-0.5926,-0.3895",\ +"-1.1238,-1.1043,-1.0769,-1.0379,-0.9559,-0.8191,-0.6004"); + } + } + + + timing() { + timing_type : hold_rising; + related_pin : "A_BIST_CLK"; + when : "((A_BIST_WEN | A_BIST_REN)& A_BIST_MEN)" + sdf_cond : "A_BIST_RW_ACCESS" + + rise_constraint("SIG2SRAM_constraint_template") { + index_1("0.0080,0.0288,0.0616,0.1072,0.1920,0.3496,0.5952"); + index_2("0.0080,0.0288,0.0616,0.1072,0.1920,0.3496,0.5952"); + values ("0.8488,0.8293,0.7980,0.7551,0.6730,0.5285,0.3059",\ +"0.8684,0.8488,0.8176,0.7746,0.6926,0.5480,0.3254",\ +"0.8996,0.8801,0.8449,0.8020,0.7238,0.5754,0.3527",\ +"0.9426,0.9191,0.8918,0.8488,0.7668,0.6223,0.3996",\ +"1.0168,1.0012,0.9699,0.9230,0.8449,0.7004,0.4777",\ +"1.1574,1.1379,1.1105,1.0598,0.9816,0.8371,0.6184",\ +"1.3801,1.3605,1.3254,1.2980,1.2043,1.0637,0.8371"); + } + + fall_constraint("SIG2SRAM_constraint_template") { + index_1("0.0080,0.0288,0.0616,0.1072,0.1920,0.3496,0.5952"); + index_2("0.0080,0.0288,0.0616,0.1072,0.1920,0.3496,0.5952"); + values ("0.6965,0.6770,0.6496,0.6066,0.5246,0.3918,0.1730",\ +"0.7160,0.6965,0.6652,0.6262,0.5441,0.4113,0.1965",\ +"0.7473,0.7277,0.6965,0.6535,0.5754,0.4426,0.2238",\ +"0.7863,0.7707,0.7395,0.7004,0.6223,0.4855,0.2629",\ +"0.8684,0.8449,0.8176,0.7785,0.7004,0.5637,0.3449",\ +"1.0051,0.9855,0.9855,0.9113,0.8332,0.7004,0.4895",\ +"1.2277,1.2082,1.1809,1.1379,1.0598,0.9230,0.7004"); + } + } +} +pin(A_BIST_WEN) { + direction : input ; + capacitance : 0.00313551 ; + max_transition : "0.5952" ; + related_power_pin : VDD; + related_ground_pin : VSS; + internal_power() { + when : "A_BIST_MEN"; + rise_power("scalar"){ + values (0.0036); + } + fall_power("scalar"){ + values (0.0004); + } + } + internal_power() { + when : "!A_BIST_MEN"; + rise_power("scalar"){ + values (0.0051); + } + fall_power("scalar"){ + values (0.0001); + } + } + timing() { + timing_type : setup_rising; + related_pin : "A_BIST_CLK"; + when : "A_BIST_MEN" + sdf_cond : "A_BIST_MEN" + + rise_constraint("SIG2SRAM_constraint_template") { + index_1("0.0080,0.0288,0.0616,0.1072,0.1920,0.3496,0.5952"); + index_2("0.0080,0.0288,0.0616,0.1072,0.1920,0.3496,0.5952"); + values ("0.3137,0.3332,0.3605,0.4035,0.4816,0.6223,0.8488",\ +"0.2980,0.3176,0.3410,0.3840,0.4660,0.6027,0.8293",\ +"0.2629,0.2824,0.3098,0.3527,0.4348,0.5754,0.7980",\ +"0.2199,0.2395,0.2668,0.3098,0.3918,0.5324,0.7590",\ +"0.1418,0.1613,0.1887,0.2316,0.3137,0.4348,0.6730",\ +"0.0012,0.0207,0.0520,0.0910,0.1730,0.3098,0.5285",\ +"-0.2215,-0.2020,-0.1746,-0.1277,-0.0496,0.0910,0.3098"); + } + + fall_constraint("SIG2SRAM_constraint_template") { + index_1("0.0080,0.0288,0.0616,0.1072,0.1920,0.3496,0.5952"); + index_2("0.0080,0.0288,0.0616,0.1072,0.1920,0.3496,0.5952"); + values ("0.4504,0.4699,0.4973,0.5324,0.6027,0.7355,0.9699",\ +"0.4309,0.4504,0.4777,0.5129,0.5910,0.7160,0.9504",\ +"0.3996,0.4191,0.4465,0.4816,0.5520,0.6848,0.9191",\ +"0.3605,0.3762,0.4035,0.4387,0.5168,0.6418,0.8723",\ +"0.2785,0.2980,0.3215,0.3605,0.4348,0.5637,0.7980",\ +"0.1379,0.1574,0.1809,0.2199,0.2980,0.4309,0.6457",\ +"-0.0809,-0.0613,-0.0340,0.0051,0.0832,0.2160,0.4191"); + } + } + + + timing() { + timing_type : hold_rising; + related_pin : "A_BIST_CLK"; + when : "A_BIST_MEN" + sdf_cond : "A_BIST_MEN" + + rise_constraint("SIG2SRAM_constraint_template") { + index_1("0.0080,0.0288,0.0616,0.1072,0.1920,0.3496,0.5952"); + index_2("0.0080,0.0288,0.0616,0.1072,0.1920,0.3496,0.5952"); + values ("0.3723,0.3527,0.3215,0.2785,0.1965,0.0559,-0.1668",\ +"0.3918,0.3723,0.3449,0.2980,0.2160,0.0754,-0.1473",\ +"0.4152,0.3996,0.3684,0.3254,0.2434,0.1066,-0.1199",\ +"0.4621,0.4465,0.4152,0.3723,0.2863,0.1496,-0.0730",\ +"0.5324,0.5207,0.4895,0.4465,0.3645,0.2199,0.0051",\ +"0.6770,0.6535,0.6301,0.5832,0.5090,0.3605,0.1418",\ +"0.9035,0.8879,0.8566,0.8137,0.7316,0.5871,0.3684"); + } + + fall_constraint("SIG2SRAM_constraint_template") { + index_1("0.0080,0.0288,0.0616,0.1072,0.1920,0.3496,0.5952"); + index_2("0.0080,0.0288,0.0616,0.1072,0.1920,0.3496,0.5952"); + values ("0.3762,0.3566,0.3293,0.2863,0.2043,0.0676,-0.1434",\ +"0.3957,0.3762,0.3488,0.3059,0.2238,0.0871,-0.1199",\ +"0.4230,0.4035,0.3723,0.3332,0.2512,0.1184,-0.0965",\ +"0.4660,0.4465,0.4191,0.3762,0.2941,0.1613,-0.0496",\ +"0.5324,0.5168,0.4973,0.4543,0.3723,0.2316,0.0285",\ +"0.6809,0.6613,0.6340,0.5910,0.5129,0.3645,0.1652",\ +"0.9113,0.8918,0.8605,0.8176,0.7395,0.5988,0.3879"); + } + } + } +pin(A_BIST_REN) { + direction : input ; + capacitance : 0.00381144 ; + max_transition : "0.5952" ; + related_power_pin : VDD; + related_ground_pin : VSS; + internal_power() { + when : "A_BIST_MEN"; + rise_power("scalar"){ + values (0.0041); + } + fall_power("scalar"){ + values (0.0013); + } + } + internal_power() { + when : "!A_BIST_MEN"; + rise_power("scalar"){ + values (0.0043); + } + fall_power("scalar"){ + values (0.0010); + } + } + timing() { + timing_type : setup_rising; + related_pin : "A_BIST_CLK"; + when : "A_BIST_MEN" + sdf_cond : "A_BIST_MEN" + + rise_constraint("SIG2SRAM_constraint_template") { + index_1("0.0080,0.0288,0.0616,0.1072,0.1920,0.3496,0.5952"); + index_2("0.0080,0.0288,0.0616,0.1072,0.1920,0.3496,0.5952"); + values ("-0.0770,-0.0574,-0.0262,0.0168,0.0949,0.2355,0.4582",\ +"-0.0965,-0.0770,-0.0457,-0.0027,0.0754,0.2160,0.4387",\ +"-0.1199,-0.1004,-0.0730,-0.0262,0.0520,0.1887,0.4113",\ +"-0.1590,-0.1434,-0.1160,-0.0730,0.0051,0.1457,0.3645",\ +"-0.2449,-0.2254,-0.1941,-0.1473,-0.0770,0.0676,0.2863",\ +"-0.3816,-0.3699,-0.3387,-0.2801,-0.2215,-0.0770,0.1457",\ +"-0.6121,-0.5926,-0.5613,-0.5145,-0.4363,-0.2996,-0.0730"); + } + + fall_constraint("SIG2SRAM_constraint_template") { + index_1("0.0080,0.0288,0.0616,0.1072,0.1920,0.3496,0.5952"); + index_2("0.0080,0.0288,0.0616,0.1072,0.1920,0.3496,0.5952"); + values ("0.1262,0.1457,0.1691,0.2121,0.2824,0.4191,0.6457",\ +"0.1105,0.1262,0.1496,0.1887,0.2629,0.3996,0.6262",\ +"0.0793,0.0949,0.1223,0.1652,0.2395,0.3684,0.5949",\ +"0.0363,0.0559,0.0793,0.1223,0.2004,0.3410,0.5520",\ +"-0.0457,-0.0262,0.0012,0.0441,0.1301,0.2629,0.4738",\ +"-0.1902,-0.1746,-0.1434,-0.1043,-0.0184,0.1223,0.3332",\ +"-0.4129,-0.3934,-0.3660,-0.3230,-0.2449,-0.1043,0.1105"); + } + } + + + timing() { + timing_type : hold_rising; + related_pin : "A_BIST_CLK"; + when : "A_BIST_MEN" + sdf_cond : "A_BIST_MEN" + + rise_constraint("SIG2SRAM_constraint_template") { + index_1("0.0080,0.0288,0.0616,0.1072,0.1920,0.3496,0.5952"); + index_2("0.0080,0.0288,0.0616,0.1072,0.1920,0.3496,0.5952"); + values ("0.4113,0.3918,0.3645,0.3176,0.2395,0.0988,-0.1238",\ +"0.4309,0.4113,0.3840,0.3371,0.2590,0.1184,-0.1043",\ +"0.4582,0.4387,0.4113,0.3645,0.2824,0.1457,-0.0770",\ +"0.5051,0.4816,0.4543,0.4074,0.3293,0.1887,-0.0340",\ +"0.5715,0.5598,0.5324,0.4895,0.4035,0.2512,0.0441",\ +"0.7043,0.7004,0.6730,0.6262,0.5402,0.3957,0.1809",\ +"0.9387,0.9270,0.8957,0.8527,0.7746,0.6262,0.4074"); + } + + fall_constraint("SIG2SRAM_constraint_template") { + index_1("0.0080,0.0288,0.0616,0.1072,0.1920,0.3496,0.5952"); + index_2("0.0080,0.0288,0.0616,0.1072,0.1920,0.3496,0.5952"); + values ("0.4152,0.3918,0.3645,0.3215,0.2395,0.1027,-0.1082",\ +"0.4309,0.4113,0.3801,0.3410,0.2590,0.1223,-0.0926",\ +"0.4582,0.4387,0.4074,0.3684,0.2863,0.1496,-0.0613",\ +"0.5012,0.4816,0.4504,0.4074,0.3293,0.1887,-0.0145",\ +"0.5715,0.5559,0.5285,0.4816,0.3996,0.2512,0.0598",\ +"0.7160,0.7004,0.6691,0.6262,0.5520,0.4035,0.2004",\ +"0.9387,0.9191,0.8957,0.8488,0.7707,0.6262,0.4113"); + } + } + } +pin(A_BIST_MEN) { + direction : input ; + capacitance : 0.00300347 ; + max_transition : "0.5952" ; + related_power_pin : VDD; + related_ground_pin : VSS; + internal_power() { + rise_power("scalar"){ + values (0.0300); + } + fall_power("scalar"){ + values (0.0003); + } + } + timing() { + timing_type : setup_rising; + related_pin : "A_BIST_CLK"; + + rise_constraint("SIG2SRAM_constraint_template") { + index_1("0.0080,0.0288,0.0616,0.1072,0.1920,0.3496,0.5952"); + index_2("0.0080,0.0288,0.0616,0.1072,0.1920,0.3496,0.5952"); + values ("0.3215,0.3449,0.3684,0.4113,0.4895,0.6301,0.8527",\ +"0.3059,0.3254,0.3527,0.3957,0.4738,0.6145,0.8371",\ +"0.2746,0.2941,0.3215,0.3645,0.4426,0.5871,0.8059",\ +"0.2316,0.2512,0.2785,0.3215,0.3996,0.5402,0.7629",\ +"0.1496,0.1730,0.1965,0.2395,0.3215,0.4660,0.6848",\ +"0.0090,0.0285,0.0598,0.1027,0.1809,0.3176,0.5402",\ +"-0.2098,-0.1902,-0.1668,-0.1199,-0.0418,0.0988,0.3137"); + } + + fall_constraint("SIG2SRAM_constraint_template") { + index_1("0.0080,0.0288,0.0616,0.1072,0.1920,0.3496,0.5952"); + index_2("0.0080,0.0288,0.0616,0.1072,0.1920,0.3496,0.5952"); + values ("0.4582,0.4738,0.5012,0.5363,0.6145,0.7395,0.9738",\ +"0.4387,0.4543,0.4816,0.5207,0.5910,0.7199,0.9582",\ +"0.4035,0.4230,0.4504,0.4855,0.5637,0.6887,0.9230",\ +"0.3645,0.3840,0.4074,0.4465,0.5285,0.6496,0.8840",\ +"0.2824,0.3020,0.3254,0.3645,0.4465,0.5715,0.7980",\ +"0.1418,0.1613,0.1887,0.2238,0.3020,0.4309,0.6496",\ +"-0.0770,-0.0574,-0.0301,0.0090,0.0910,0.2238,0.4191"); + } + } + + + timing() { + timing_type : hold_rising; + related_pin : "A_BIST_CLK"; + + rise_constraint("SIG2SRAM_constraint_template") { + index_1("0.0080,0.0288,0.0616,0.1072,0.1920,0.3496,0.5952"); + index_2("0.0080,0.0288,0.0616,0.1072,0.1920,0.3496,0.5952"); + values ("0.3762,0.3605,0.3293,0.2863,0.2043,0.0637,-0.1629",\ +"0.3996,0.3801,0.3488,0.3020,0.2238,0.0832,-0.1395",\ +"0.4230,0.4074,0.3723,0.3293,0.2473,0.1105,-0.1121",\ +"0.4621,0.4465,0.4152,0.3762,0.2941,0.1535,-0.0691",\ +"0.5441,0.5285,0.4973,0.4465,0.3684,0.2316,0.0090",\ +"0.6848,0.6652,0.6301,0.5910,0.5129,0.3605,0.1496",\ +"0.9074,0.8918,0.8566,0.8215,0.7395,0.5910,0.3723"); + } + + fall_constraint("SIG2SRAM_constraint_template") { + index_1("0.0080,0.0288,0.0616,0.1072,0.1920,0.3496,0.5952"); + index_2("0.0080,0.0288,0.0616,0.1072,0.1920,0.3496,0.5952"); + values ("0.3762,0.3605,0.3332,0.2863,0.2043,0.0715,-0.1395",\ +"0.3996,0.3762,0.3488,0.3059,0.2238,0.0910,-0.1199",\ +"0.4270,0.4035,0.3762,0.3332,0.2512,0.1184,-0.0965",\ +"0.4699,0.4504,0.4191,0.3762,0.2941,0.1613,-0.0496",\ +"0.5441,0.5285,0.4973,0.4543,0.3762,0.2355,0.0324",\ +"0.6770,0.6613,0.6340,0.5949,0.5207,0.3762,0.1652",\ +"0.9074,0.8918,0.8605,0.8176,0.7395,0.6027,0.3918"); + } + } + } +bus(A_BIST_BM) { + bus_type : D_31_0; + direction : input ; + capacitance : 0.00347781 ; + max_transition : "0.5952" ; + pin(A_BIST_BM[31:0]) { + related_power_pin : VDD; + related_ground_pin : VSS; + internal_power() { + when : "A_BIST_MEN"; + rise_power("scalar"){ + values (0.0936); + } + fall_power("scalar"){ + values (0.0303); + } + } + internal_power() { + when : "!A_BIST_MEN"; + rise_power("scalar"){ + values (0.0900); + } + fall_power("scalar"){ + values (0.0290); + } + } + } + timing() { + timing_type : setup_rising; + related_pin : "A_BIST_CLK"; + when : "(A_BIST_WEN & A_BIST_MEN)" + sdf_cond : "A_BIST_RW_ACCESS" + + rise_constraint("SIG2SRAM_constraint_template") { + index_1("0.0080,0.0288,0.0616,0.1072,0.1920,0.3496,0.5952"); + index_2("0.0080,0.0288,0.0616,0.1072,0.1920,0.3496,0.5952"); + values ("-0.9175,-0.8980,-0.8726,-0.8296,-0.7485,-0.6030,-0.3804",\ +"-0.9250,-0.9054,-0.8800,-0.8371,-0.7560,-0.6105,-0.3878",\ +"-0.9345,-0.9150,-0.8896,-0.8467,-0.7656,-0.6201,-0.3974",\ +"-0.9477,-0.9282,-0.9028,-0.8598,-0.7787,-0.6332,-0.4106",\ +"-0.9719,-0.9524,-0.9270,-0.8841,-0.8030,-0.6575,-0.4348",\ +"-1.0024,-0.9828,-0.9575,-0.9145,-0.8334,-0.6879,-0.4653",\ +"-1.0840,-1.0645,-1.0391,-0.9961,-0.9150,-0.7695,-0.5469"); + } + + fall_constraint("SIG2SRAM_constraint_template") { + index_1("0.0080,0.0288,0.0616,0.1072,0.1920,0.3496,0.5952"); + index_2("0.0080,0.0288,0.0616,0.1072,0.1920,0.3496,0.5952"); + values ("-0.8550,-0.8374,-0.8101,-0.7710,-0.6880,-0.5523,-0.3403",\ +"-0.8625,-0.8449,-0.8175,-0.7785,-0.6955,-0.5597,-0.3478",\ +"-0.8720,-0.8545,-0.8271,-0.7881,-0.7050,-0.5693,-0.3574",\ +"-0.8852,-0.8676,-0.8403,-0.8012,-0.7182,-0.5825,-0.3705",\ +"-0.9094,-0.8919,-0.8645,-0.8255,-0.7424,-0.6067,-0.3948",\ +"-0.9399,-0.9223,-0.8950,-0.8559,-0.7729,-0.6371,-0.4252",\ +"-1.0215,-1.0039,-0.9766,-0.9375,-0.8545,-0.7188,-0.5069"); + } + } + + + timing() { + timing_type : hold_rising; + related_pin : "A_BIST_CLK"; + when : "(A_BIST_WEN & A_BIST_MEN)" + sdf_cond : "A_BIST_RW_ACCESS" + + rise_constraint("SIG2SRAM_constraint_template") { + index_1("0.0080,0.0288,0.0616,0.1072,0.1920,0.3496,0.5952"); + index_2("0.0080,0.0288,0.0616,0.1072,0.1920,0.3496,0.5952"); + values ("1.0343,1.0128,0.9884,0.9454,0.8653,0.7189,0.4962",\ +"1.0418,1.0203,0.9959,0.9529,0.8728,0.7263,0.5037",\ +"1.0513,1.0298,1.0054,0.9625,0.8824,0.7359,0.5132",\ +"1.0645,1.0430,1.0186,0.9756,0.8955,0.7491,0.5264",\ +"1.0887,1.0673,1.0428,0.9999,0.9198,0.7733,0.5507",\ +"1.1192,1.0977,1.0733,1.0303,0.9502,0.8037,0.5811",\ +"1.2008,1.1793,1.1549,1.1119,1.0318,0.8854,0.6627"); + } + + fall_constraint("SIG2SRAM_constraint_template") { + index_1("0.0080,0.0288,0.0616,0.1072,0.1920,0.3496,0.5952"); + index_2("0.0080,0.0288,0.0616,0.1072,0.1920,0.3496,0.5952"); + values ("0.9601,0.9425,0.9151,0.8761,0.7931,0.6564,0.4454",\ +"0.9675,0.9500,0.9226,0.8836,0.8005,0.6638,0.4529",\ +"0.9771,0.9595,0.9322,0.8931,0.8101,0.6734,0.4625",\ +"0.9903,0.9727,0.9453,0.9063,0.8233,0.6866,0.4756",\ +"1.0145,0.9969,0.9696,0.9305,0.8475,0.7108,0.4999",\ +"1.0450,1.0274,1.0000,0.9610,0.8780,0.7412,0.5303",\ +"1.1266,1.1090,1.0817,1.0426,0.9596,0.8229,0.6119"); + } + } +} + pin(A_BIST_CLK) { + direction : input; + capacitance : 0.00378957; + max_transition : "0.5952"; + clock : "true" ; + pin_func_type : active_rising ; + + timing () { + timing_type : "min_pulse_width"; + related_pin : "A_BIST_CLK"; + rise_constraint("CLKTRAN_constraint_template") { + index_1("0.008,0.5952"); + values("0.4,0.4"); + } + } + + related_power_pin : VDD; + related_ground_pin : VSS; + + internal_power() { + when : "!A_BIST_MEN & !A_BIST_WEN & !A_BIST_REN"; + rise_power("scalar"){ + values (0); + } + fall_power("scalar"){ + values (0); + } + } + internal_power() { + when : "!A_BIST_MEN & A_BIST_WEN & !A_BIST_REN"; + rise_power("scalar"){ + values (0.5614); + } + fall_power("scalar"){ + values (0); + } + } + internal_power() { + when : "A_BIST_MEN & A_BIST_WEN & !A_BIST_REN"; + rise_power("scalar"){ + values (35.0454); + } + fall_power("scalar"){ + values (0); + } + } + internal_power() { + when : "A_BIST_MEN & A_BIST_WEN & A_BIST_REN"; + rise_power("scalar"){ + values (37.3908); + } + fall_power("scalar"){ + values (0); + } + } + internal_power() { + when : "A_BIST_MEN & !A_BIST_WEN & A_BIST_REN"; + rise_power("scalar"){ + values (29.1692); + } + fall_power("scalar"){ + values (0); + } + } + internal_power() { + when : "!A_BIST_MEN & !A_BIST_WEN & A_BIST_REN"; + rise_power("scalar"){ + values (0.3780); + } + fall_power("scalar"){ + values (0); + } + } + internal_power() { + when : "!A_BIST_MEN & A_BIST_WEN & A_BIST_REN"; + rise_power("scalar"){ + values (1.1082); + } + fall_power("scalar"){ + values (0); + } + } + internal_power() { + when : "A_BIST_MEN & !A_BIST_WEN & !A_BIST_REN"; + rise_power("scalar"){ + values (0); + } + fall_power("scalar"){ + values (0); + } + } + } + bus(A_BIST_DIN) { + bus_type : D_31_0; + direction : input ; + capacitance : 0.00396073 ; + memory_write() { + address : A_BIST_ADDR ; + clocked_on : A_BIST_CLK; + } + + max_transition : "0.5952" ; + pin(A_BIST_DIN[31:0]) { + related_power_pin : VDD; + related_ground_pin : VSS; + internal_power() { + when : "A_BIST_MEN"; + rise_power("scalar"){ + values (0.0936); + } + fall_power("scalar"){ + values (0.0303); + } + } + internal_power() { + when : "!A_BIST_MEN"; + rise_power("scalar"){ + values (0.0900); + } + fall_power("scalar"){ + values (0.0290); + } + } + } + timing() { + timing_type : setup_rising; + related_pin : "A_BIST_CLK"; + when : "(A_BIST_WEN & A_BIST_MEN)"; + sdf_cond : "A_BIST_W_ACCESS"; + + rise_constraint("SIG2SRAM_constraint_template") { + index_1("0.0080,0.0288,0.0616,0.1072,0.1920,0.3496,0.5952"); + index_2("0.0080,0.0288,0.0616,0.1072,0.1920,0.3496,0.5952"); + values ("-0.9175,-0.8980,-0.8726,-0.8296,-0.7485,-0.6030,-0.3804",\ +"-0.9250,-0.9054,-0.8800,-0.8371,-0.7560,-0.6105,-0.3878",\ +"-0.9345,-0.9150,-0.8896,-0.8467,-0.7656,-0.6201,-0.3974",\ +"-0.9477,-0.9282,-0.9028,-0.8598,-0.7787,-0.6332,-0.4106",\ +"-0.9719,-0.9524,-0.9270,-0.8841,-0.8030,-0.6575,-0.4348",\ +"-1.0024,-0.9828,-0.9575,-0.9145,-0.8334,-0.6879,-0.4653",\ +"-1.0840,-1.0645,-1.0391,-0.9961,-0.9150,-0.7695,-0.5469"); + } + + fall_constraint("SIG2SRAM_constraint_template") { + index_1("0.0080,0.0288,0.0616,0.1072,0.1920,0.3496,0.5952"); + index_2("0.0080,0.0288,0.0616,0.1072,0.1920,0.3496,0.5952"); + values ("-0.8550,-0.8374,-0.8101,-0.7710,-0.6880,-0.5523,-0.3403",\ +"-0.8625,-0.8449,-0.8175,-0.7785,-0.6955,-0.5597,-0.3478",\ +"-0.8720,-0.8545,-0.8271,-0.7881,-0.7050,-0.5693,-0.3574",\ +"-0.8852,-0.8676,-0.8403,-0.8012,-0.7182,-0.5825,-0.3705",\ +"-0.9094,-0.8919,-0.8645,-0.8255,-0.7424,-0.6067,-0.3948",\ +"-0.9399,-0.9223,-0.8950,-0.8559,-0.7729,-0.6371,-0.4252",\ +"-1.0215,-1.0039,-0.9766,-0.9375,-0.8545,-0.7188,-0.5069"); + } + } + + timing() { + timing_type : hold_rising; + related_pin : "A_BIST_CLK"; + when : "(A_BIST_WEN & A_BIST_MEN)"; + sdf_cond : "A_BIST_W_ACCESS"; + + rise_constraint("SIG2SRAM_constraint_template") { + index_1("0.0080,0.0288,0.0616,0.1072,0.1920,0.3496,0.5952"); + index_2("0.0080,0.0288,0.0616,0.1072,0.1920,0.3496,0.5952"); + values ("1.0343,1.0128,0.9884,0.9454,0.8653,0.7189,0.4962",\ +"1.0418,1.0203,0.9959,0.9529,0.8728,0.7263,0.5037",\ +"1.0513,1.0298,1.0054,0.9625,0.8824,0.7359,0.5132",\ +"1.0645,1.0430,1.0186,0.9756,0.8955,0.7491,0.5264",\ +"1.0887,1.0673,1.0428,0.9999,0.9198,0.7733,0.5507",\ +"1.1192,1.0977,1.0733,1.0303,0.9502,0.8037,0.5811",\ +"1.2008,1.1793,1.1549,1.1119,1.0318,0.8854,0.6627"); + } + + fall_constraint("SIG2SRAM_constraint_template") { + index_1("0.0080,0.0288,0.0616,0.1072,0.1920,0.3496,0.5952"); + index_2("0.0080,0.0288,0.0616,0.1072,0.1920,0.3496,0.5952"); + values ("0.9601,0.9425,0.9151,0.8761,0.7931,0.6564,0.4454",\ +"0.9675,0.9500,0.9226,0.8836,0.8005,0.6638,0.4529",\ +"0.9771,0.9595,0.9322,0.8931,0.8101,0.6734,0.4625",\ +"0.9903,0.9727,0.9453,0.9063,0.8233,0.6866,0.4756",\ +"1.0145,0.9969,0.9696,0.9305,0.8475,0.7108,0.4999",\ +"1.0450,1.0274,1.0000,0.9610,0.8780,0.7412,0.5303",\ +"1.1266,1.1090,1.0817,1.0426,0.9596,0.8229,0.6119"); + } + } + } + +bus(A_DOUT) { + + bus_type : D_31_0; + direction : output ; + capacitance : 0 ; + max_capacitance : 0.064 ; + memory_read() { + address : A_ADDR ; + } + pin(A_DOUT[31:0]) { + related_power_pin : VDD; + related_ground_pin : VSS; + internal_power() { + rise_power("scalar") { + values (0); + } + fall_power("scalar") { + values (0); + } + } + } + timing() { + related_pin : "A_CLK"; + timing_type : rising_edge ; + timing_sense : non_unate ; + + cell_rise(SIG2SRAM_delay_template) { + index_1("0.0080,0.0288,0.0616,0.1072,0.1920,0.3496,0.5952"); + index_2("0.0008,0.0014,0.0051,0.0100,0.0339,0.0640"); + values ("6.5553,6.5586,6.5708,6.5847,6.6373,6.6952",\ +"6.5596,6.5630,6.5752,6.5891,6.6417,6.6995",\ +"6.5701,6.5734,6.5856,6.5995,6.6521,6.7100",\ +"6.5907,6.5941,6.6063,6.6202,6.6728,6.7306",\ +"6.6050,6.6083,6.6205,6.6345,6.6870,6.7449",\ +"6.6384,6.6418,6.6540,6.6679,6.7205,6.7783",\ +"6.7241,6.7275,6.7397,6.7536,6.8062,6.8640"); + } + cell_fall(SIG2SRAM_delay_template) { + index_1("0.0080,0.0288,0.0616,0.1072,0.1920,0.3496,0.5952"); + index_2("0.0008,0.0014,0.0051,0.0100,0.0339,0.0640"); + values ("6.4455,6.4477,6.4577,6.4694,6.5128,6.5566",\ +"6.4499,6.4521,6.4621,6.4738,6.5171,6.5610",\ +"6.4603,6.4625,6.4725,6.4842,6.5276,6.5714",\ +"6.4810,6.4832,6.4932,6.5049,6.5482,6.5921",\ +"6.4953,6.4974,6.5075,6.5191,6.5625,6.6063",\ +"6.5287,6.5309,6.5409,6.5526,6.5959,6.6398",\ +"6.6144,6.6166,6.6266,6.6383,6.6816,6.7255"); + } + + rise_transition(SRAM_load_template) { + index_1("0.0008,0.0014,0.0051,0.0100,0.0339,0.0640"); + values ("0.0560,0.0583,0.0696,0.0816,0.1519,0.2335"); + } + fall_transition(SRAM_load_template) { + index_1("0.0008,0.0014,0.0051,0.0100,0.0339,0.0640"); + values ("0.0428,0.0445,0.0538,0.0658,0.1181,0.1751"); + } + } +} + pin(B_DLY) { + direction : input ; + capacitance : 0.00387999 ; + max_transition : "1" ; + related_power_pin : VDD; + related_ground_pin : VSS; + internal_power() { + rise_power("scalar") { + values (0); + } + fall_power("scalar") { + values (0); + } + } + } + +bus(B_ADDR) { + bus_type : A_8_0; + direction : input ; + capacitance : 0.0129586 ; + pin(B_ADDR[0]) { + capacitance : 0.00588404 ; + } + pin(B_ADDR[1]) { + capacitance : 0.0080425 ; + } + pin(B_ADDR[2]) { + capacitance : 0.0112051 ; + } + pin(B_ADDR[3]) { + capacitance : 0.00706428 ; + } + pin(B_ADDR[4]) { + capacitance : 0.00656149 ; + } + pin(B_ADDR[5]) { + capacitance : 0.0111839 ; + } + pin(B_ADDR[6]) { + capacitance : 0.0140236 ; + } + pin(B_ADDR[7]) { + capacitance : 0.0111118 ; + } + max_transition : "0.5952" ; + pin(B_ADDR[8:0]) { + related_power_pin : VDD; + related_ground_pin : VSS; + internal_power() { + when : "B_MEN"; + rise_power("scalar"){ + values (0.0100); + } + fall_power("scalar"){ + values (0.0075); + } + } + internal_power() { + when : "!B_MEN"; + rise_power("scalar"){ + values (0.0165); + } + fall_power("scalar"){ + values (0.0022); + } + } + } + timing() { + timing_type : setup_rising; + related_pin : "B_CLK"; + when : "((B_WEN | B_REN)& B_MEN)" + sdf_cond : "B_RW_ACCESS" + + rise_constraint("SIG2SRAM_constraint_template") { + index_1("0.0080,0.0288,0.0616,0.1072,0.1920,0.3496,0.5952"); + index_2("0.0080,0.0288,0.0616,0.1072,0.1920,0.3496,0.5952"); + values ("-0.7371,-0.7176,-0.6863,-0.6434,-0.5652,-0.4168,-0.1980",\ +"-0.7566,-0.7371,-0.7059,-0.6629,-0.5848,-0.4363,-0.2137",\ +"-0.7879,-0.7645,-0.7332,-0.6902,-0.6121,-0.4637,-0.2449",\ +"-0.8309,-0.8074,-0.7762,-0.7332,-0.6551,-0.5066,-0.2879",\ +"-0.9051,-0.8895,-0.8543,-0.8113,-0.7332,-0.5887,-0.3660",\ +"-1.0418,-1.0262,-0.9949,-0.9480,-0.8699,-0.7293,-0.5027",\ +"-1.2684,-1.2449,-1.2176,-1.1707,-1.0965,-0.9480,-0.7293"); + } + + fall_constraint("SIG2SRAM_constraint_template") { + index_1("0.0080,0.0288,0.0616,0.1072,0.1920,0.3496,0.5952"); + index_2("0.0080,0.0288,0.0616,0.1072,0.1920,0.3496,0.5952"); + values ("-0.5926,-0.5730,-0.5418,-0.4988,-0.4246,-0.2879,-0.0730",\ +"-0.6121,-0.5926,-0.5613,-0.5223,-0.4441,-0.3074,-0.0887",\ +"-0.6395,-0.6199,-0.5926,-0.5496,-0.4715,-0.3348,-0.1160",\ +"-0.6863,-0.6668,-0.6355,-0.5965,-0.5184,-0.3777,-0.1590",\ +"-0.7605,-0.7410,-0.7137,-0.6746,-0.5926,-0.4559,-0.2410",\ +"-0.9012,-0.8816,-0.8504,-0.8113,-0.7332,-0.5926,-0.3895",\ +"-1.1238,-1.1043,-1.0769,-1.0379,-0.9559,-0.8191,-0.6004"); + } + } + + + timing() { + timing_type : hold_rising; + related_pin : "B_CLK"; + when : "((B_WEN | B_REN)& B_MEN)" + sdf_cond : "B_RW_ACCESS" + + rise_constraint("SIG2SRAM_constraint_template") { + index_1("0.0080,0.0288,0.0616,0.1072,0.1920,0.3496,0.5952"); + index_2("0.0080,0.0288,0.0616,0.1072,0.1920,0.3496,0.5952"); + values ("0.8488,0.8293,0.7980,0.7551,0.6730,0.5285,0.3059",\ +"0.8684,0.8488,0.8176,0.7746,0.6926,0.5480,0.3254",\ +"0.8996,0.8801,0.8449,0.8020,0.7238,0.5754,0.3527",\ +"0.9426,0.9191,0.8918,0.8488,0.7668,0.6223,0.3996",\ +"1.0168,1.0012,0.9699,0.9230,0.8449,0.7004,0.4777",\ +"1.1574,1.1379,1.1105,1.0598,0.9816,0.8371,0.6184",\ +"1.3801,1.3605,1.3254,1.2980,1.2043,1.0637,0.8371"); + } + + fall_constraint("SIG2SRAM_constraint_template") { + index_1("0.0080,0.0288,0.0616,0.1072,0.1920,0.3496,0.5952"); + index_2("0.0080,0.0288,0.0616,0.1072,0.1920,0.3496,0.5952"); + values ("0.6965,0.6770,0.6496,0.6066,0.5246,0.3918,0.1730",\ +"0.7160,0.6965,0.6652,0.6262,0.5441,0.4113,0.1965",\ +"0.7473,0.7277,0.6965,0.6535,0.5754,0.4426,0.2238",\ +"0.7863,0.7707,0.7395,0.7004,0.6223,0.4855,0.2629",\ +"0.8684,0.8449,0.8176,0.7785,0.7004,0.5637,0.3449",\ +"1.0051,0.9855,0.9855,0.9113,0.8332,0.7004,0.4895",\ +"1.2277,1.2082,1.1809,1.1379,1.0598,0.9230,0.7004"); + } + } +} +pin(B_WEN) { + direction : input ; + capacitance : 0.00313551 ; + max_transition : "0.5952" ; + related_power_pin : VDD; + related_ground_pin : VSS; + internal_power() { + when : "B_MEN"; + rise_power("scalar"){ + values (0.0036); + } + fall_power("scalar"){ + values (0.0004); + } + } + internal_power() { + when : "!B_MEN"; + rise_power("scalar"){ + values (0.0051); + } + fall_power("scalar"){ + values (0.0001); + } + } + timing() { + timing_type : setup_rising; + related_pin : "B_CLK"; + when : "B_MEN" + sdf_cond : "B_MEN" + + rise_constraint("SIG2SRAM_constraint_template") { + index_1("0.0080,0.0288,0.0616,0.1072,0.1920,0.3496,0.5952"); + index_2("0.0080,0.0288,0.0616,0.1072,0.1920,0.3496,0.5952"); + values ("0.3137,0.3332,0.3605,0.4035,0.4816,0.6223,0.8488",\ +"0.2980,0.3176,0.3410,0.3840,0.4660,0.6027,0.8293",\ +"0.2629,0.2824,0.3098,0.3527,0.4348,0.5754,0.7980",\ +"0.2199,0.2395,0.2668,0.3098,0.3918,0.5324,0.7590",\ +"0.1418,0.1613,0.1887,0.2316,0.3137,0.4348,0.6730",\ +"0.0012,0.0207,0.0520,0.0910,0.1730,0.3098,0.5285",\ +"-0.2215,-0.2020,-0.1746,-0.1277,-0.0496,0.0910,0.3098"); + } + + fall_constraint("SIG2SRAM_constraint_template") { + index_1("0.0080,0.0288,0.0616,0.1072,0.1920,0.3496,0.5952"); + index_2("0.0080,0.0288,0.0616,0.1072,0.1920,0.3496,0.5952"); + values ("0.4504,0.4699,0.4973,0.5324,0.6027,0.7355,0.9699",\ +"0.4309,0.4504,0.4777,0.5129,0.5910,0.7160,0.9504",\ +"0.3996,0.4191,0.4465,0.4816,0.5520,0.6848,0.9191",\ +"0.3605,0.3762,0.4035,0.4387,0.5168,0.6418,0.8723",\ +"0.2785,0.2980,0.3215,0.3605,0.4348,0.5637,0.7980",\ +"0.1379,0.1574,0.1809,0.2199,0.2980,0.4309,0.6457",\ +"-0.0809,-0.0613,-0.0340,0.0051,0.0832,0.2160,0.4191"); + } + } + + + timing() { + timing_type : hold_rising; + related_pin : "B_CLK"; + when : "B_MEN" + sdf_cond : "B_MEN" + + rise_constraint("SIG2SRAM_constraint_template") { + index_1("0.0080,0.0288,0.0616,0.1072,0.1920,0.3496,0.5952"); + index_2("0.0080,0.0288,0.0616,0.1072,0.1920,0.3496,0.5952"); + values ("0.3723,0.3527,0.3215,0.2785,0.1965,0.0559,-0.1668",\ +"0.3918,0.3723,0.3449,0.2980,0.2160,0.0754,-0.1473",\ +"0.4152,0.3996,0.3684,0.3254,0.2434,0.1066,-0.1199",\ +"0.4621,0.4465,0.4152,0.3723,0.2863,0.1496,-0.0730",\ +"0.5324,0.5207,0.4895,0.4465,0.3645,0.2199,0.0051",\ +"0.6770,0.6535,0.6301,0.5832,0.5090,0.3605,0.1418",\ +"0.9035,0.8879,0.8566,0.8137,0.7316,0.5871,0.3684"); + } + + fall_constraint("SIG2SRAM_constraint_template") { + index_1("0.0080,0.0288,0.0616,0.1072,0.1920,0.3496,0.5952"); + index_2("0.0080,0.0288,0.0616,0.1072,0.1920,0.3496,0.5952"); + values ("0.3762,0.3566,0.3293,0.2863,0.2043,0.0676,-0.1434",\ +"0.3957,0.3762,0.3488,0.3059,0.2238,0.0871,-0.1199",\ +"0.4230,0.4035,0.3723,0.3332,0.2512,0.1184,-0.0965",\ +"0.4660,0.4465,0.4191,0.3762,0.2941,0.1613,-0.0496",\ +"0.5324,0.5168,0.4973,0.4543,0.3723,0.2316,0.0285",\ +"0.6809,0.6613,0.6340,0.5910,0.5129,0.3645,0.1652",\ +"0.9113,0.8918,0.8605,0.8176,0.7395,0.5988,0.3879"); + } + } + } +pin(B_REN) { + direction : input ; + capacitance : 0.00381144 ; + max_transition : "0.5952" ; + related_power_pin : VDD; + related_ground_pin : VSS; + internal_power() { + when : "B_MEN"; + rise_power("scalar"){ + values (0.0041); + } + fall_power("scalar"){ + values (0.0013); + } + } + internal_power() { + when : "!B_MEN"; + rise_power("scalar"){ + values (0.0043); + } + fall_power("scalar"){ + values (0.0010); + } + } + timing() { + timing_type : setup_rising; + related_pin : "B_CLK"; + when : "B_MEN" + sdf_cond : "B_MEN" + + rise_constraint("SIG2SRAM_constraint_template") { + index_1("0.0080,0.0288,0.0616,0.1072,0.1920,0.3496,0.5952"); + index_2("0.0080,0.0288,0.0616,0.1072,0.1920,0.3496,0.5952"); + values ("-0.0770,-0.0574,-0.0262,0.0168,0.0949,0.2355,0.4582",\ +"-0.0965,-0.0770,-0.0457,-0.0027,0.0754,0.2160,0.4387",\ +"-0.1199,-0.1004,-0.0730,-0.0262,0.0520,0.1887,0.4113",\ +"-0.1590,-0.1434,-0.1160,-0.0730,0.0051,0.1457,0.3645",\ +"-0.2449,-0.2254,-0.1941,-0.1473,-0.0770,0.0676,0.2863",\ +"-0.3816,-0.3699,-0.3387,-0.2801,-0.2215,-0.0770,0.1457",\ +"-0.6121,-0.5926,-0.5613,-0.5145,-0.4363,-0.2996,-0.0730"); + } + + fall_constraint("SIG2SRAM_constraint_template") { + index_1("0.0080,0.0288,0.0616,0.1072,0.1920,0.3496,0.5952"); + index_2("0.0080,0.0288,0.0616,0.1072,0.1920,0.3496,0.5952"); + values ("0.1262,0.1457,0.1691,0.2121,0.2824,0.4191,0.6457",\ +"0.1105,0.1262,0.1496,0.1887,0.2629,0.3996,0.6262",\ +"0.0793,0.0949,0.1223,0.1652,0.2395,0.3684,0.5949",\ +"0.0363,0.0559,0.0793,0.1223,0.2004,0.3410,0.5520",\ +"-0.0457,-0.0262,0.0012,0.0441,0.1301,0.2629,0.4738",\ +"-0.1902,-0.1746,-0.1434,-0.1043,-0.0184,0.1223,0.3332",\ +"-0.4129,-0.3934,-0.3660,-0.3230,-0.2449,-0.1043,0.1105"); + } + } + + + timing() { + timing_type : hold_rising; + related_pin : "B_CLK"; + when : "B_MEN" + sdf_cond : "B_MEN" + + rise_constraint("SIG2SRAM_constraint_template") { + index_1("0.0080,0.0288,0.0616,0.1072,0.1920,0.3496,0.5952"); + index_2("0.0080,0.0288,0.0616,0.1072,0.1920,0.3496,0.5952"); + values ("0.4113,0.3918,0.3645,0.3176,0.2395,0.0988,-0.1238",\ +"0.4309,0.4113,0.3840,0.3371,0.2590,0.1184,-0.1043",\ +"0.4582,0.4387,0.4113,0.3645,0.2824,0.1457,-0.0770",\ +"0.5051,0.4816,0.4543,0.4074,0.3293,0.1887,-0.0340",\ +"0.5715,0.5598,0.5324,0.4895,0.4035,0.2512,0.0441",\ +"0.7043,0.7004,0.6730,0.6262,0.5402,0.3957,0.1809",\ +"0.9387,0.9270,0.8957,0.8527,0.7746,0.6262,0.4074"); + } + + fall_constraint("SIG2SRAM_constraint_template") { + index_1("0.0080,0.0288,0.0616,0.1072,0.1920,0.3496,0.5952"); + index_2("0.0080,0.0288,0.0616,0.1072,0.1920,0.3496,0.5952"); + values ("0.4152,0.3918,0.3645,0.3215,0.2395,0.1027,-0.1082",\ +"0.4309,0.4113,0.3801,0.3410,0.2590,0.1223,-0.0926",\ +"0.4582,0.4387,0.4074,0.3684,0.2863,0.1496,-0.0613",\ +"0.5012,0.4816,0.4504,0.4074,0.3293,0.1887,-0.0145",\ +"0.5715,0.5559,0.5285,0.4816,0.3996,0.2512,0.0598",\ +"0.7160,0.7004,0.6691,0.6262,0.5520,0.4035,0.2004",\ +"0.9387,0.9191,0.8957,0.8488,0.7707,0.6262,0.4113"); + } + } + } +pin(B_MEN) { + direction : input ; + capacitance : 0.00300347 ; + max_transition : "0.5952" ; + related_power_pin : VDD; + related_ground_pin : VSS; + internal_power() { + rise_power("scalar"){ + values (0.0300); + } + fall_power("scalar"){ + values (0.0003); + } + } + timing() { + timing_type : setup_rising; + related_pin : "B_CLK"; + + rise_constraint("SIG2SRAM_constraint_template") { + index_1("0.0080,0.0288,0.0616,0.1072,0.1920,0.3496,0.5952"); + index_2("0.0080,0.0288,0.0616,0.1072,0.1920,0.3496,0.5952"); + values ("0.3215,0.3449,0.3684,0.4113,0.4895,0.6301,0.8527",\ +"0.3059,0.3254,0.3527,0.3957,0.4738,0.6145,0.8371",\ +"0.2746,0.2941,0.3215,0.3645,0.4426,0.5871,0.8059",\ +"0.2316,0.2512,0.2785,0.3215,0.3996,0.5402,0.7629",\ +"0.1496,0.1730,0.1965,0.2395,0.3215,0.4660,0.6848",\ +"0.0090,0.0285,0.0598,0.1027,0.1809,0.3176,0.5402",\ +"-0.2098,-0.1902,-0.1668,-0.1199,-0.0418,0.0988,0.3137"); + } + + fall_constraint("SIG2SRAM_constraint_template") { + index_1("0.0080,0.0288,0.0616,0.1072,0.1920,0.3496,0.5952"); + index_2("0.0080,0.0288,0.0616,0.1072,0.1920,0.3496,0.5952"); + values ("0.4582,0.4738,0.5012,0.5363,0.6145,0.7395,0.9738",\ +"0.4387,0.4543,0.4816,0.5207,0.5910,0.7199,0.9582",\ +"0.4035,0.4230,0.4504,0.4855,0.5637,0.6887,0.9230",\ +"0.3645,0.3840,0.4074,0.4465,0.5285,0.6496,0.8840",\ +"0.2824,0.3020,0.3254,0.3645,0.4465,0.5715,0.7980",\ +"0.1418,0.1613,0.1887,0.2238,0.3020,0.4309,0.6496",\ +"-0.0770,-0.0574,-0.0301,0.0090,0.0910,0.2238,0.4191"); + } + } + + + timing() { + timing_type : hold_rising; + related_pin : "B_CLK"; + + rise_constraint("SIG2SRAM_constraint_template") { + index_1("0.0080,0.0288,0.0616,0.1072,0.1920,0.3496,0.5952"); + index_2("0.0080,0.0288,0.0616,0.1072,0.1920,0.3496,0.5952"); + values ("0.3762,0.3605,0.3293,0.2863,0.2043,0.0637,-0.1629",\ +"0.3996,0.3801,0.3488,0.3020,0.2238,0.0832,-0.1395",\ +"0.4230,0.4074,0.3723,0.3293,0.2473,0.1105,-0.1121",\ +"0.4621,0.4465,0.4152,0.3762,0.2941,0.1535,-0.0691",\ +"0.5441,0.5285,0.4973,0.4465,0.3684,0.2316,0.0090",\ +"0.6848,0.6652,0.6301,0.5910,0.5129,0.3605,0.1496",\ +"0.9074,0.8918,0.8566,0.8215,0.7395,0.5910,0.3723"); + } + + fall_constraint("SIG2SRAM_constraint_template") { + index_1("0.0080,0.0288,0.0616,0.1072,0.1920,0.3496,0.5952"); + index_2("0.0080,0.0288,0.0616,0.1072,0.1920,0.3496,0.5952"); + values ("0.3762,0.3605,0.3332,0.2863,0.2043,0.0715,-0.1395",\ +"0.3996,0.3762,0.3488,0.3059,0.2238,0.0910,-0.1199",\ +"0.4270,0.4035,0.3762,0.3332,0.2512,0.1184,-0.0965",\ +"0.4699,0.4504,0.4191,0.3762,0.2941,0.1613,-0.0496",\ +"0.5441,0.5285,0.4973,0.4543,0.3762,0.2355,0.0324",\ +"0.6770,0.6613,0.6340,0.5949,0.5207,0.3762,0.1652",\ +"0.9074,0.8918,0.8605,0.8176,0.7395,0.6027,0.3918"); + } + } + } +bus(B_BM) { + bus_type : D_31_0; + direction : input ; + capacitance : 0.00293202 ; + max_transition : "0.5952" ; + pin(B_BM[31:0]) { + related_power_pin : VDD; + related_ground_pin : VSS; + internal_power() { + when : "B_MEN"; + rise_power("scalar"){ + values (0.0936); + } + fall_power("scalar"){ + values (0.0303); + } + } + internal_power() { + when : "!B_MEN"; + rise_power("scalar"){ + values (0.0900); + } + fall_power("scalar"){ + values (0.0290); + } + } + } + timing() { + timing_type : setup_rising; + related_pin : "B_CLK"; + when : "(B_WEN & B_MEN)" + sdf_cond : "B_RW_ACCESS" + + rise_constraint("SIG2SRAM_constraint_template") { + index_1("0.0080,0.0288,0.0616,0.1072,0.1920,0.3496,0.5952"); + index_2("0.0080,0.0288,0.0616,0.1072,0.1920,0.3496,0.5952"); + values ("-0.9175,-0.8980,-0.8726,-0.8296,-0.7485,-0.6030,-0.3804",\ +"-0.9250,-0.9054,-0.8800,-0.8371,-0.7560,-0.6105,-0.3878",\ +"-0.9345,-0.9150,-0.8896,-0.8467,-0.7656,-0.6201,-0.3974",\ +"-0.9477,-0.9282,-0.9028,-0.8598,-0.7787,-0.6332,-0.4106",\ +"-0.9719,-0.9524,-0.9270,-0.8841,-0.8030,-0.6575,-0.4348",\ +"-1.0024,-0.9828,-0.9575,-0.9145,-0.8334,-0.6879,-0.4653",\ +"-1.0840,-1.0645,-1.0391,-0.9961,-0.9150,-0.7695,-0.5469"); + } + + fall_constraint("SIG2SRAM_constraint_template") { + index_1("0.0080,0.0288,0.0616,0.1072,0.1920,0.3496,0.5952"); + index_2("0.0080,0.0288,0.0616,0.1072,0.1920,0.3496,0.5952"); + values ("-0.8550,-0.8374,-0.8101,-0.7710,-0.6880,-0.5523,-0.3403",\ +"-0.8625,-0.8449,-0.8175,-0.7785,-0.6955,-0.5597,-0.3478",\ +"-0.8720,-0.8545,-0.8271,-0.7881,-0.7050,-0.5693,-0.3574",\ +"-0.8852,-0.8676,-0.8403,-0.8012,-0.7182,-0.5825,-0.3705",\ +"-0.9094,-0.8919,-0.8645,-0.8255,-0.7424,-0.6067,-0.3948",\ +"-0.9399,-0.9223,-0.8950,-0.8559,-0.7729,-0.6371,-0.4252",\ +"-1.0215,-1.0039,-0.9766,-0.9375,-0.8545,-0.7188,-0.5069"); + } + } + + + timing() { + timing_type : hold_rising; + related_pin : "B_CLK"; + when : "(B_WEN & B_MEN)" + sdf_cond : "B_RW_ACCESS" + + rise_constraint("SIG2SRAM_constraint_template") { + index_1("0.0080,0.0288,0.0616,0.1072,0.1920,0.3496,0.5952"); + index_2("0.0080,0.0288,0.0616,0.1072,0.1920,0.3496,0.5952"); + values ("1.0343,1.0128,0.9884,0.9454,0.8653,0.7189,0.4962",\ +"1.0418,1.0203,0.9959,0.9529,0.8728,0.7263,0.5037",\ +"1.0513,1.0298,1.0054,0.9625,0.8824,0.7359,0.5132",\ +"1.0645,1.0430,1.0186,0.9756,0.8955,0.7491,0.5264",\ +"1.0887,1.0673,1.0428,0.9999,0.9198,0.7733,0.5507",\ +"1.1192,1.0977,1.0733,1.0303,0.9502,0.8037,0.5811",\ +"1.2008,1.1793,1.1549,1.1119,1.0318,0.8854,0.6627"); + } + + fall_constraint("SIG2SRAM_constraint_template") { + index_1("0.0080,0.0288,0.0616,0.1072,0.1920,0.3496,0.5952"); + index_2("0.0080,0.0288,0.0616,0.1072,0.1920,0.3496,0.5952"); + values ("0.9601,0.9425,0.9151,0.8761,0.7931,0.6564,0.4454",\ +"0.9675,0.9500,0.9226,0.8836,0.8005,0.6638,0.4529",\ +"0.9771,0.9595,0.9322,0.8931,0.8101,0.6734,0.4625",\ +"0.9903,0.9727,0.9453,0.9063,0.8233,0.6866,0.4756",\ +"1.0145,0.9969,0.9696,0.9305,0.8475,0.7108,0.4999",\ +"1.0450,1.0274,1.0000,0.9610,0.8780,0.7412,0.5303",\ +"1.1266,1.1090,1.0817,1.0426,0.9596,0.8229,0.6119"); + } + } +} + pin(B_CLK) { + direction : input; + capacitance : 0.00378957; + max_transition : "0.5952"; + clock : "true" ; + pin_func_type : active_rising ; + + timing () { + timing_type : "min_pulse_width"; + related_pin : "B_CLK"; + rise_constraint("CLKTRAN_constraint_template") { + index_1("0.008,0.5952"); + values("0.4,0.4"); + } + } + + related_power_pin : VDD; + related_ground_pin : VSS; + + internal_power() { + when : "!B_MEN & !B_WEN & !B_REN"; + rise_power("scalar"){ + values (0); + } + fall_power("scalar"){ + values (0); + } + } + internal_power() { + when : "!B_MEN & B_WEN & !B_REN"; + rise_power("scalar"){ + values (0.5614); + } + fall_power("scalar"){ + values (0); + } + } + internal_power() { + when : "B_MEN & B_WEN & !B_REN"; + rise_power("scalar"){ + values (35.0454); + } + fall_power("scalar"){ + values (0); + } + } + internal_power() { + when : "B_MEN & B_WEN & B_REN"; + rise_power("scalar"){ + values (37.3908); + } + fall_power("scalar"){ + values (0); + } + } + internal_power() { + when : "B_MEN & !B_WEN & B_REN"; + rise_power("scalar"){ + values (29.1692); + } + fall_power("scalar"){ + values (0); + } + } + internal_power() { + when : "!B_MEN & !B_WEN & B_REN"; + rise_power("scalar"){ + values (0.3780); + } + fall_power("scalar"){ + values (0); + } + } + internal_power() { + when : "!B_MEN & B_WEN & B_REN"; + rise_power("scalar"){ + values (1.1082); + } + fall_power("scalar"){ + values (0); + } + } + internal_power() { + when : "B_MEN & !B_WEN & !B_REN"; + rise_power("scalar"){ + values (0); + } + fall_power("scalar"){ + values (0); + } + } + } + bus(B_DIN) { + bus_type : D_31_0; + direction : input ; + capacitance : 0.00460366 ; + memory_write() { + address : B_ADDR ; + clocked_on : B_CLK; + } + + max_transition : "0.5952" ; + pin(B_DIN[31:0]) { + related_power_pin : VDD; + related_ground_pin : VSS; + internal_power() { + when : "B_MEN"; + rise_power("scalar"){ + values (0.0936); + } + fall_power("scalar"){ + values (0.0303); + } + } + internal_power() { + when : "!B_MEN"; + rise_power("scalar"){ + values (0.0900); + } + fall_power("scalar"){ + values (0.0290); + } + } + } + timing() { + timing_type : setup_rising; + related_pin : "B_CLK"; + when : "(B_WEN & B_MEN)"; + sdf_cond : "B_W_ACCESS"; + + rise_constraint("SIG2SRAM_constraint_template") { + index_1("0.0080,0.0288,0.0616,0.1072,0.1920,0.3496,0.5952"); + index_2("0.0080,0.0288,0.0616,0.1072,0.1920,0.3496,0.5952"); + values ("-0.9175,-0.8980,-0.8726,-0.8296,-0.7485,-0.6030,-0.3804",\ +"-0.9250,-0.9054,-0.8800,-0.8371,-0.7560,-0.6105,-0.3878",\ +"-0.9345,-0.9150,-0.8896,-0.8467,-0.7656,-0.6201,-0.3974",\ +"-0.9477,-0.9282,-0.9028,-0.8598,-0.7787,-0.6332,-0.4106",\ +"-0.9719,-0.9524,-0.9270,-0.8841,-0.8030,-0.6575,-0.4348",\ +"-1.0024,-0.9828,-0.9575,-0.9145,-0.8334,-0.6879,-0.4653",\ +"-1.0840,-1.0645,-1.0391,-0.9961,-0.9150,-0.7695,-0.5469"); + } + + fall_constraint("SIG2SRAM_constraint_template") { + index_1("0.0080,0.0288,0.0616,0.1072,0.1920,0.3496,0.5952"); + index_2("0.0080,0.0288,0.0616,0.1072,0.1920,0.3496,0.5952"); + values ("-0.8550,-0.8374,-0.8101,-0.7710,-0.6880,-0.5523,-0.3403",\ +"-0.8625,-0.8449,-0.8175,-0.7785,-0.6955,-0.5597,-0.3478",\ +"-0.8720,-0.8545,-0.8271,-0.7881,-0.7050,-0.5693,-0.3574",\ +"-0.8852,-0.8676,-0.8403,-0.8012,-0.7182,-0.5825,-0.3705",\ +"-0.9094,-0.8919,-0.8645,-0.8255,-0.7424,-0.6067,-0.3948",\ +"-0.9399,-0.9223,-0.8950,-0.8559,-0.7729,-0.6371,-0.4252",\ +"-1.0215,-1.0039,-0.9766,-0.9375,-0.8545,-0.7188,-0.5069"); + } + } + + timing() { + timing_type : hold_rising; + related_pin : "B_CLK"; + when : "(B_WEN & B_MEN)"; + sdf_cond : "B_W_ACCESS"; + + rise_constraint("SIG2SRAM_constraint_template") { + index_1("0.0080,0.0288,0.0616,0.1072,0.1920,0.3496,0.5952"); + index_2("0.0080,0.0288,0.0616,0.1072,0.1920,0.3496,0.5952"); + values ("1.0343,1.0128,0.9884,0.9454,0.8653,0.7189,0.4962",\ +"1.0418,1.0203,0.9959,0.9529,0.8728,0.7263,0.5037",\ +"1.0513,1.0298,1.0054,0.9625,0.8824,0.7359,0.5132",\ +"1.0645,1.0430,1.0186,0.9756,0.8955,0.7491,0.5264",\ +"1.0887,1.0673,1.0428,0.9999,0.9198,0.7733,0.5507",\ +"1.1192,1.0977,1.0733,1.0303,0.9502,0.8037,0.5811",\ +"1.2008,1.1793,1.1549,1.1119,1.0318,0.8854,0.6627"); + } + + fall_constraint("SIG2SRAM_constraint_template") { + index_1("0.0080,0.0288,0.0616,0.1072,0.1920,0.3496,0.5952"); + index_2("0.0080,0.0288,0.0616,0.1072,0.1920,0.3496,0.5952"); + values ("0.9601,0.9425,0.9151,0.8761,0.7931,0.6564,0.4454",\ +"0.9675,0.9500,0.9226,0.8836,0.8005,0.6638,0.4529",\ +"0.9771,0.9595,0.9322,0.8931,0.8101,0.6734,0.4625",\ +"0.9903,0.9727,0.9453,0.9063,0.8233,0.6866,0.4756",\ +"1.0145,0.9969,0.9696,0.9305,0.8475,0.7108,0.4999",\ +"1.0450,1.0274,1.0000,0.9610,0.8780,0.7412,0.5303",\ +"1.1266,1.1090,1.0817,1.0426,0.9596,0.8229,0.6119"); + } + } + } + + pin(B_BIST_EN) { + direction : input ; + capacitance : 0.00387999 ; + max_transition : "1" ; + related_power_pin : VDD; + related_ground_pin : VSS; + internal_power() { + rise_power("scalar") { + values (0); + } + fall_power("scalar") { + values (0); + } + } + } + +bus(B_BIST_ADDR) { + bus_type : A_8_0; + direction : input ; + capacitance : 0.0129586 ; + pin(B_BIST_ADDR[0]) { + capacitance : 0.00588404 ; + } + pin(B_BIST_ADDR[1]) { + capacitance : 0.0080425 ; + } + pin(B_BIST_ADDR[2]) { + capacitance : 0.0112051 ; + } + pin(B_BIST_ADDR[3]) { + capacitance : 0.00706428 ; + } + pin(B_BIST_ADDR[4]) { + capacitance : 0.00656149 ; + } + pin(B_BIST_ADDR[5]) { + capacitance : 0.0111839 ; + } + pin(B_BIST_ADDR[6]) { + capacitance : 0.0140236 ; + } + pin(B_BIST_ADDR[7]) { + capacitance : 0.0111118 ; + } + max_transition : "0.5952" ; + pin(B_BIST_ADDR[8:0]) { + related_power_pin : VDD; + related_ground_pin : VSS; + internal_power() { + when : "B_BIST_MEN"; + rise_power("scalar"){ + values (0.0100); + } + fall_power("scalar"){ + values (0.0075); + } + } + internal_power() { + when : "!B_BIST_MEN"; + rise_power("scalar"){ + values (0.0165); + } + fall_power("scalar"){ + values (0.0022); + } + } + } + timing() { + timing_type : setup_rising; + related_pin : "B_BIST_CLK"; + when : "((B_BIST_WEN | B_BIST_REN)& B_BIST_MEN)" + sdf_cond : "B_BIST_RW_ACCESS" + + rise_constraint("SIG2SRAM_constraint_template") { + index_1("0.0080,0.0288,0.0616,0.1072,0.1920,0.3496,0.5952"); + index_2("0.0080,0.0288,0.0616,0.1072,0.1920,0.3496,0.5952"); + values ("-0.7371,-0.7176,-0.6863,-0.6434,-0.5652,-0.4168,-0.1980",\ +"-0.7566,-0.7371,-0.7059,-0.6629,-0.5848,-0.4363,-0.2137",\ +"-0.7879,-0.7645,-0.7332,-0.6902,-0.6121,-0.4637,-0.2449",\ +"-0.8309,-0.8074,-0.7762,-0.7332,-0.6551,-0.5066,-0.2879",\ +"-0.9051,-0.8895,-0.8543,-0.8113,-0.7332,-0.5887,-0.3660",\ +"-1.0418,-1.0262,-0.9949,-0.9480,-0.8699,-0.7293,-0.5027",\ +"-1.2684,-1.2449,-1.2176,-1.1707,-1.0965,-0.9480,-0.7293"); + } + + fall_constraint("SIG2SRAM_constraint_template") { + index_1("0.0080,0.0288,0.0616,0.1072,0.1920,0.3496,0.5952"); + index_2("0.0080,0.0288,0.0616,0.1072,0.1920,0.3496,0.5952"); + values ("-0.5926,-0.5730,-0.5418,-0.4988,-0.4246,-0.2879,-0.0730",\ +"-0.6121,-0.5926,-0.5613,-0.5223,-0.4441,-0.3074,-0.0887",\ +"-0.6395,-0.6199,-0.5926,-0.5496,-0.4715,-0.3348,-0.1160",\ +"-0.6863,-0.6668,-0.6355,-0.5965,-0.5184,-0.3777,-0.1590",\ +"-0.7605,-0.7410,-0.7137,-0.6746,-0.5926,-0.4559,-0.2410",\ +"-0.9012,-0.8816,-0.8504,-0.8113,-0.7332,-0.5926,-0.3895",\ +"-1.1238,-1.1043,-1.0769,-1.0379,-0.9559,-0.8191,-0.6004"); + } + } + + + timing() { + timing_type : hold_rising; + related_pin : "B_BIST_CLK"; + when : "((B_BIST_WEN | B_BIST_REN)& B_BIST_MEN)" + sdf_cond : "B_BIST_RW_ACCESS" + + rise_constraint("SIG2SRAM_constraint_template") { + index_1("0.0080,0.0288,0.0616,0.1072,0.1920,0.3496,0.5952"); + index_2("0.0080,0.0288,0.0616,0.1072,0.1920,0.3496,0.5952"); + values ("0.8488,0.8293,0.7980,0.7551,0.6730,0.5285,0.3059",\ +"0.8684,0.8488,0.8176,0.7746,0.6926,0.5480,0.3254",\ +"0.8996,0.8801,0.8449,0.8020,0.7238,0.5754,0.3527",\ +"0.9426,0.9191,0.8918,0.8488,0.7668,0.6223,0.3996",\ +"1.0168,1.0012,0.9699,0.9230,0.8449,0.7004,0.4777",\ +"1.1574,1.1379,1.1105,1.0598,0.9816,0.8371,0.6184",\ +"1.3801,1.3605,1.3254,1.2980,1.2043,1.0637,0.8371"); + } + + fall_constraint("SIG2SRAM_constraint_template") { + index_1("0.0080,0.0288,0.0616,0.1072,0.1920,0.3496,0.5952"); + index_2("0.0080,0.0288,0.0616,0.1072,0.1920,0.3496,0.5952"); + values ("0.6965,0.6770,0.6496,0.6066,0.5246,0.3918,0.1730",\ +"0.7160,0.6965,0.6652,0.6262,0.5441,0.4113,0.1965",\ +"0.7473,0.7277,0.6965,0.6535,0.5754,0.4426,0.2238",\ +"0.7863,0.7707,0.7395,0.7004,0.6223,0.4855,0.2629",\ +"0.8684,0.8449,0.8176,0.7785,0.7004,0.5637,0.3449",\ +"1.0051,0.9855,0.9855,0.9113,0.8332,0.7004,0.4895",\ +"1.2277,1.2082,1.1809,1.1379,1.0598,0.9230,0.7004"); + } + } +} +pin(B_BIST_WEN) { + direction : input ; + capacitance : 0.00313551 ; + max_transition : "0.5952" ; + related_power_pin : VDD; + related_ground_pin : VSS; + internal_power() { + when : "B_BIST_MEN"; + rise_power("scalar"){ + values (0.0036); + } + fall_power("scalar"){ + values (0.0004); + } + } + internal_power() { + when : "!B_BIST_MEN"; + rise_power("scalar"){ + values (0.0051); + } + fall_power("scalar"){ + values (0.0001); + } + } + timing() { + timing_type : setup_rising; + related_pin : "B_BIST_CLK"; + when : "B_BIST_MEN" + sdf_cond : "B_BIST_MEN" + + rise_constraint("SIG2SRAM_constraint_template") { + index_1("0.0080,0.0288,0.0616,0.1072,0.1920,0.3496,0.5952"); + index_2("0.0080,0.0288,0.0616,0.1072,0.1920,0.3496,0.5952"); + values ("0.3137,0.3332,0.3605,0.4035,0.4816,0.6223,0.8488",\ +"0.2980,0.3176,0.3410,0.3840,0.4660,0.6027,0.8293",\ +"0.2629,0.2824,0.3098,0.3527,0.4348,0.5754,0.7980",\ +"0.2199,0.2395,0.2668,0.3098,0.3918,0.5324,0.7590",\ +"0.1418,0.1613,0.1887,0.2316,0.3137,0.4348,0.6730",\ +"0.0012,0.0207,0.0520,0.0910,0.1730,0.3098,0.5285",\ +"-0.2215,-0.2020,-0.1746,-0.1277,-0.0496,0.0910,0.3098"); + } + + fall_constraint("SIG2SRAM_constraint_template") { + index_1("0.0080,0.0288,0.0616,0.1072,0.1920,0.3496,0.5952"); + index_2("0.0080,0.0288,0.0616,0.1072,0.1920,0.3496,0.5952"); + values ("0.4504,0.4699,0.4973,0.5324,0.6027,0.7355,0.9699",\ +"0.4309,0.4504,0.4777,0.5129,0.5910,0.7160,0.9504",\ +"0.3996,0.4191,0.4465,0.4816,0.5520,0.6848,0.9191",\ +"0.3605,0.3762,0.4035,0.4387,0.5168,0.6418,0.8723",\ +"0.2785,0.2980,0.3215,0.3605,0.4348,0.5637,0.7980",\ +"0.1379,0.1574,0.1809,0.2199,0.2980,0.4309,0.6457",\ +"-0.0809,-0.0613,-0.0340,0.0051,0.0832,0.2160,0.4191"); + } + } + + + timing() { + timing_type : hold_rising; + related_pin : "B_BIST_CLK"; + when : "B_BIST_MEN" + sdf_cond : "B_BIST_MEN" + + rise_constraint("SIG2SRAM_constraint_template") { + index_1("0.0080,0.0288,0.0616,0.1072,0.1920,0.3496,0.5952"); + index_2("0.0080,0.0288,0.0616,0.1072,0.1920,0.3496,0.5952"); + values ("0.3723,0.3527,0.3215,0.2785,0.1965,0.0559,-0.1668",\ +"0.3918,0.3723,0.3449,0.2980,0.2160,0.0754,-0.1473",\ +"0.4152,0.3996,0.3684,0.3254,0.2434,0.1066,-0.1199",\ +"0.4621,0.4465,0.4152,0.3723,0.2863,0.1496,-0.0730",\ +"0.5324,0.5207,0.4895,0.4465,0.3645,0.2199,0.0051",\ +"0.6770,0.6535,0.6301,0.5832,0.5090,0.3605,0.1418",\ +"0.9035,0.8879,0.8566,0.8137,0.7316,0.5871,0.3684"); + } + + fall_constraint("SIG2SRAM_constraint_template") { + index_1("0.0080,0.0288,0.0616,0.1072,0.1920,0.3496,0.5952"); + index_2("0.0080,0.0288,0.0616,0.1072,0.1920,0.3496,0.5952"); + values ("0.3762,0.3566,0.3293,0.2863,0.2043,0.0676,-0.1434",\ +"0.3957,0.3762,0.3488,0.3059,0.2238,0.0871,-0.1199",\ +"0.4230,0.4035,0.3723,0.3332,0.2512,0.1184,-0.0965",\ +"0.4660,0.4465,0.4191,0.3762,0.2941,0.1613,-0.0496",\ +"0.5324,0.5168,0.4973,0.4543,0.3723,0.2316,0.0285",\ +"0.6809,0.6613,0.6340,0.5910,0.5129,0.3645,0.1652",\ +"0.9113,0.8918,0.8605,0.8176,0.7395,0.5988,0.3879"); + } + } + } +pin(B_BIST_REN) { + direction : input ; + capacitance : 0.00381144 ; + max_transition : "0.5952" ; + related_power_pin : VDD; + related_ground_pin : VSS; + internal_power() { + when : "B_BIST_MEN"; + rise_power("scalar"){ + values (0.0041); + } + fall_power("scalar"){ + values (0.0013); + } + } + internal_power() { + when : "!B_BIST_MEN"; + rise_power("scalar"){ + values (0.0043); + } + fall_power("scalar"){ + values (0.0010); + } + } + timing() { + timing_type : setup_rising; + related_pin : "B_BIST_CLK"; + when : "B_BIST_MEN" + sdf_cond : "B_BIST_MEN" + + rise_constraint("SIG2SRAM_constraint_template") { + index_1("0.0080,0.0288,0.0616,0.1072,0.1920,0.3496,0.5952"); + index_2("0.0080,0.0288,0.0616,0.1072,0.1920,0.3496,0.5952"); + values ("-0.0770,-0.0574,-0.0262,0.0168,0.0949,0.2355,0.4582",\ +"-0.0965,-0.0770,-0.0457,-0.0027,0.0754,0.2160,0.4387",\ +"-0.1199,-0.1004,-0.0730,-0.0262,0.0520,0.1887,0.4113",\ +"-0.1590,-0.1434,-0.1160,-0.0730,0.0051,0.1457,0.3645",\ +"-0.2449,-0.2254,-0.1941,-0.1473,-0.0770,0.0676,0.2863",\ +"-0.3816,-0.3699,-0.3387,-0.2801,-0.2215,-0.0770,0.1457",\ +"-0.6121,-0.5926,-0.5613,-0.5145,-0.4363,-0.2996,-0.0730"); + } + + fall_constraint("SIG2SRAM_constraint_template") { + index_1("0.0080,0.0288,0.0616,0.1072,0.1920,0.3496,0.5952"); + index_2("0.0080,0.0288,0.0616,0.1072,0.1920,0.3496,0.5952"); + values ("0.1262,0.1457,0.1691,0.2121,0.2824,0.4191,0.6457",\ +"0.1105,0.1262,0.1496,0.1887,0.2629,0.3996,0.6262",\ +"0.0793,0.0949,0.1223,0.1652,0.2395,0.3684,0.5949",\ +"0.0363,0.0559,0.0793,0.1223,0.2004,0.3410,0.5520",\ +"-0.0457,-0.0262,0.0012,0.0441,0.1301,0.2629,0.4738",\ +"-0.1902,-0.1746,-0.1434,-0.1043,-0.0184,0.1223,0.3332",\ +"-0.4129,-0.3934,-0.3660,-0.3230,-0.2449,-0.1043,0.1105"); + } + } + + + timing() { + timing_type : hold_rising; + related_pin : "B_BIST_CLK"; + when : "B_BIST_MEN" + sdf_cond : "B_BIST_MEN" + + rise_constraint("SIG2SRAM_constraint_template") { + index_1("0.0080,0.0288,0.0616,0.1072,0.1920,0.3496,0.5952"); + index_2("0.0080,0.0288,0.0616,0.1072,0.1920,0.3496,0.5952"); + values ("0.4113,0.3918,0.3645,0.3176,0.2395,0.0988,-0.1238",\ +"0.4309,0.4113,0.3840,0.3371,0.2590,0.1184,-0.1043",\ +"0.4582,0.4387,0.4113,0.3645,0.2824,0.1457,-0.0770",\ +"0.5051,0.4816,0.4543,0.4074,0.3293,0.1887,-0.0340",\ +"0.5715,0.5598,0.5324,0.4895,0.4035,0.2512,0.0441",\ +"0.7043,0.7004,0.6730,0.6262,0.5402,0.3957,0.1809",\ +"0.9387,0.9270,0.8957,0.8527,0.7746,0.6262,0.4074"); + } + + fall_constraint("SIG2SRAM_constraint_template") { + index_1("0.0080,0.0288,0.0616,0.1072,0.1920,0.3496,0.5952"); + index_2("0.0080,0.0288,0.0616,0.1072,0.1920,0.3496,0.5952"); + values ("0.4152,0.3918,0.3645,0.3215,0.2395,0.1027,-0.1082",\ +"0.4309,0.4113,0.3801,0.3410,0.2590,0.1223,-0.0926",\ +"0.4582,0.4387,0.4074,0.3684,0.2863,0.1496,-0.0613",\ +"0.5012,0.4816,0.4504,0.4074,0.3293,0.1887,-0.0145",\ +"0.5715,0.5559,0.5285,0.4816,0.3996,0.2512,0.0598",\ +"0.7160,0.7004,0.6691,0.6262,0.5520,0.4035,0.2004",\ +"0.9387,0.9191,0.8957,0.8488,0.7707,0.6262,0.4113"); + } + } + } +pin(B_BIST_MEN) { + direction : input ; + capacitance : 0.00300347 ; + max_transition : "0.5952" ; + related_power_pin : VDD; + related_ground_pin : VSS; + internal_power() { + rise_power("scalar"){ + values (0.0300); + } + fall_power("scalar"){ + values (0.0003); + } + } + timing() { + timing_type : setup_rising; + related_pin : "B_BIST_CLK"; + + rise_constraint("SIG2SRAM_constraint_template") { + index_1("0.0080,0.0288,0.0616,0.1072,0.1920,0.3496,0.5952"); + index_2("0.0080,0.0288,0.0616,0.1072,0.1920,0.3496,0.5952"); + values ("0.3215,0.3449,0.3684,0.4113,0.4895,0.6301,0.8527",\ +"0.3059,0.3254,0.3527,0.3957,0.4738,0.6145,0.8371",\ +"0.2746,0.2941,0.3215,0.3645,0.4426,0.5871,0.8059",\ +"0.2316,0.2512,0.2785,0.3215,0.3996,0.5402,0.7629",\ +"0.1496,0.1730,0.1965,0.2395,0.3215,0.4660,0.6848",\ +"0.0090,0.0285,0.0598,0.1027,0.1809,0.3176,0.5402",\ +"-0.2098,-0.1902,-0.1668,-0.1199,-0.0418,0.0988,0.3137"); + } + + fall_constraint("SIG2SRAM_constraint_template") { + index_1("0.0080,0.0288,0.0616,0.1072,0.1920,0.3496,0.5952"); + index_2("0.0080,0.0288,0.0616,0.1072,0.1920,0.3496,0.5952"); + values ("0.4582,0.4738,0.5012,0.5363,0.6145,0.7395,0.9738",\ +"0.4387,0.4543,0.4816,0.5207,0.5910,0.7199,0.9582",\ +"0.4035,0.4230,0.4504,0.4855,0.5637,0.6887,0.9230",\ +"0.3645,0.3840,0.4074,0.4465,0.5285,0.6496,0.8840",\ +"0.2824,0.3020,0.3254,0.3645,0.4465,0.5715,0.7980",\ +"0.1418,0.1613,0.1887,0.2238,0.3020,0.4309,0.6496",\ +"-0.0770,-0.0574,-0.0301,0.0090,0.0910,0.2238,0.4191"); + } + } + + + timing() { + timing_type : hold_rising; + related_pin : "B_BIST_CLK"; + + rise_constraint("SIG2SRAM_constraint_template") { + index_1("0.0080,0.0288,0.0616,0.1072,0.1920,0.3496,0.5952"); + index_2("0.0080,0.0288,0.0616,0.1072,0.1920,0.3496,0.5952"); + values ("0.3762,0.3605,0.3293,0.2863,0.2043,0.0637,-0.1629",\ +"0.3996,0.3801,0.3488,0.3020,0.2238,0.0832,-0.1395",\ +"0.4230,0.4074,0.3723,0.3293,0.2473,0.1105,-0.1121",\ +"0.4621,0.4465,0.4152,0.3762,0.2941,0.1535,-0.0691",\ +"0.5441,0.5285,0.4973,0.4465,0.3684,0.2316,0.0090",\ +"0.6848,0.6652,0.6301,0.5910,0.5129,0.3605,0.1496",\ +"0.9074,0.8918,0.8566,0.8215,0.7395,0.5910,0.3723"); + } + + fall_constraint("SIG2SRAM_constraint_template") { + index_1("0.0080,0.0288,0.0616,0.1072,0.1920,0.3496,0.5952"); + index_2("0.0080,0.0288,0.0616,0.1072,0.1920,0.3496,0.5952"); + values ("0.3762,0.3605,0.3332,0.2863,0.2043,0.0715,-0.1395",\ +"0.3996,0.3762,0.3488,0.3059,0.2238,0.0910,-0.1199",\ +"0.4270,0.4035,0.3762,0.3332,0.2512,0.1184,-0.0965",\ +"0.4699,0.4504,0.4191,0.3762,0.2941,0.1613,-0.0496",\ +"0.5441,0.5285,0.4973,0.4543,0.3762,0.2355,0.0324",\ +"0.6770,0.6613,0.6340,0.5949,0.5207,0.3762,0.1652",\ +"0.9074,0.8918,0.8605,0.8176,0.7395,0.6027,0.3918"); + } + } + } +bus(B_BIST_BM) { + bus_type : D_31_0; + direction : input ; + capacitance : 0.00261869 ; + max_transition : "0.5952" ; + pin(B_BIST_BM[31:0]) { + related_power_pin : VDD; + related_ground_pin : VSS; + internal_power() { + when : "B_BIST_MEN"; + rise_power("scalar"){ + values (0.0936); + } + fall_power("scalar"){ + values (0.0303); + } + } + internal_power() { + when : "!B_BIST_MEN"; + rise_power("scalar"){ + values (0.0900); + } + fall_power("scalar"){ + values (0.0290); + } + } + } + timing() { + timing_type : setup_rising; + related_pin : "B_BIST_CLK"; + when : "(B_BIST_WEN & B_BIST_MEN)" + sdf_cond : "B_BIST_RW_ACCESS" + + rise_constraint("SIG2SRAM_constraint_template") { + index_1("0.0080,0.0288,0.0616,0.1072,0.1920,0.3496,0.5952"); + index_2("0.0080,0.0288,0.0616,0.1072,0.1920,0.3496,0.5952"); + values ("-0.9175,-0.8980,-0.8726,-0.8296,-0.7485,-0.6030,-0.3804",\ +"-0.9250,-0.9054,-0.8800,-0.8371,-0.7560,-0.6105,-0.3878",\ +"-0.9345,-0.9150,-0.8896,-0.8467,-0.7656,-0.6201,-0.3974",\ +"-0.9477,-0.9282,-0.9028,-0.8598,-0.7787,-0.6332,-0.4106",\ +"-0.9719,-0.9524,-0.9270,-0.8841,-0.8030,-0.6575,-0.4348",\ +"-1.0024,-0.9828,-0.9575,-0.9145,-0.8334,-0.6879,-0.4653",\ +"-1.0840,-1.0645,-1.0391,-0.9961,-0.9150,-0.7695,-0.5469"); + } + + fall_constraint("SIG2SRAM_constraint_template") { + index_1("0.0080,0.0288,0.0616,0.1072,0.1920,0.3496,0.5952"); + index_2("0.0080,0.0288,0.0616,0.1072,0.1920,0.3496,0.5952"); + values ("-0.8550,-0.8374,-0.8101,-0.7710,-0.6880,-0.5523,-0.3403",\ +"-0.8625,-0.8449,-0.8175,-0.7785,-0.6955,-0.5597,-0.3478",\ +"-0.8720,-0.8545,-0.8271,-0.7881,-0.7050,-0.5693,-0.3574",\ +"-0.8852,-0.8676,-0.8403,-0.8012,-0.7182,-0.5825,-0.3705",\ +"-0.9094,-0.8919,-0.8645,-0.8255,-0.7424,-0.6067,-0.3948",\ +"-0.9399,-0.9223,-0.8950,-0.8559,-0.7729,-0.6371,-0.4252",\ +"-1.0215,-1.0039,-0.9766,-0.9375,-0.8545,-0.7188,-0.5069"); + } + } + + + timing() { + timing_type : hold_rising; + related_pin : "B_BIST_CLK"; + when : "(B_BIST_WEN & B_BIST_MEN)" + sdf_cond : "B_BIST_RW_ACCESS" + + rise_constraint("SIG2SRAM_constraint_template") { + index_1("0.0080,0.0288,0.0616,0.1072,0.1920,0.3496,0.5952"); + index_2("0.0080,0.0288,0.0616,0.1072,0.1920,0.3496,0.5952"); + values ("1.0343,1.0128,0.9884,0.9454,0.8653,0.7189,0.4962",\ +"1.0418,1.0203,0.9959,0.9529,0.8728,0.7263,0.5037",\ +"1.0513,1.0298,1.0054,0.9625,0.8824,0.7359,0.5132",\ +"1.0645,1.0430,1.0186,0.9756,0.8955,0.7491,0.5264",\ +"1.0887,1.0673,1.0428,0.9999,0.9198,0.7733,0.5507",\ +"1.1192,1.0977,1.0733,1.0303,0.9502,0.8037,0.5811",\ +"1.2008,1.1793,1.1549,1.1119,1.0318,0.8854,0.6627"); + } + + fall_constraint("SIG2SRAM_constraint_template") { + index_1("0.0080,0.0288,0.0616,0.1072,0.1920,0.3496,0.5952"); + index_2("0.0080,0.0288,0.0616,0.1072,0.1920,0.3496,0.5952"); + values ("0.9601,0.9425,0.9151,0.8761,0.7931,0.6564,0.4454",\ +"0.9675,0.9500,0.9226,0.8836,0.8005,0.6638,0.4529",\ +"0.9771,0.9595,0.9322,0.8931,0.8101,0.6734,0.4625",\ +"0.9903,0.9727,0.9453,0.9063,0.8233,0.6866,0.4756",\ +"1.0145,0.9969,0.9696,0.9305,0.8475,0.7108,0.4999",\ +"1.0450,1.0274,1.0000,0.9610,0.8780,0.7412,0.5303",\ +"1.1266,1.1090,1.0817,1.0426,0.9596,0.8229,0.6119"); + } + } +} + pin(B_BIST_CLK) { + direction : input; + capacitance : 0.00378957; + max_transition : "0.5952"; + clock : "true" ; + pin_func_type : active_rising ; + + timing () { + timing_type : "min_pulse_width"; + related_pin : "B_BIST_CLK"; + rise_constraint("CLKTRAN_constraint_template") { + index_1("0.008,0.5952"); + values("0.4,0.4"); + } + } + + related_power_pin : VDD; + related_ground_pin : VSS; + + internal_power() { + when : "!B_BIST_MEN & !B_BIST_WEN & !B_BIST_REN"; + rise_power("scalar"){ + values (0); + } + fall_power("scalar"){ + values (0); + } + } + internal_power() { + when : "!B_BIST_MEN & B_BIST_WEN & !B_BIST_REN"; + rise_power("scalar"){ + values (0.5614); + } + fall_power("scalar"){ + values (0); + } + } + internal_power() { + when : "B_BIST_MEN & B_BIST_WEN & !B_BIST_REN"; + rise_power("scalar"){ + values (35.0454); + } + fall_power("scalar"){ + values (0); + } + } + internal_power() { + when : "B_BIST_MEN & B_BIST_WEN & B_BIST_REN"; + rise_power("scalar"){ + values (37.3908); + } + fall_power("scalar"){ + values (0); + } + } + internal_power() { + when : "B_BIST_MEN & !B_BIST_WEN & B_BIST_REN"; + rise_power("scalar"){ + values (29.1692); + } + fall_power("scalar"){ + values (0); + } + } + internal_power() { + when : "!B_BIST_MEN & !B_BIST_WEN & B_BIST_REN"; + rise_power("scalar"){ + values (0.3780); + } + fall_power("scalar"){ + values (0); + } + } + internal_power() { + when : "!B_BIST_MEN & B_BIST_WEN & B_BIST_REN"; + rise_power("scalar"){ + values (1.1082); + } + fall_power("scalar"){ + values (0); + } + } + internal_power() { + when : "B_BIST_MEN & !B_BIST_WEN & !B_BIST_REN"; + rise_power("scalar"){ + values (0); + } + fall_power("scalar"){ + values (0); + } + } + } + bus(B_BIST_DIN) { + bus_type : D_31_0; + direction : input ; + capacitance : 0.00416317 ; + memory_write() { + address : B_BIST_ADDR ; + clocked_on : B_BIST_CLK; + } + + max_transition : "0.5952" ; + pin(B_BIST_DIN[31:0]) { + related_power_pin : VDD; + related_ground_pin : VSS; + internal_power() { + when : "B_BIST_MEN"; + rise_power("scalar"){ + values (0.0936); + } + fall_power("scalar"){ + values (0.0303); + } + } + internal_power() { + when : "!B_BIST_MEN"; + rise_power("scalar"){ + values (0.0900); + } + fall_power("scalar"){ + values (0.0290); + } + } + } + timing() { + timing_type : setup_rising; + related_pin : "B_BIST_CLK"; + when : "(B_BIST_WEN & B_BIST_MEN)"; + sdf_cond : "B_BIST_W_ACCESS"; + + rise_constraint("SIG2SRAM_constraint_template") { + index_1("0.0080,0.0288,0.0616,0.1072,0.1920,0.3496,0.5952"); + index_2("0.0080,0.0288,0.0616,0.1072,0.1920,0.3496,0.5952"); + values ("-0.9175,-0.8980,-0.8726,-0.8296,-0.7485,-0.6030,-0.3804",\ +"-0.9250,-0.9054,-0.8800,-0.8371,-0.7560,-0.6105,-0.3878",\ +"-0.9345,-0.9150,-0.8896,-0.8467,-0.7656,-0.6201,-0.3974",\ +"-0.9477,-0.9282,-0.9028,-0.8598,-0.7787,-0.6332,-0.4106",\ +"-0.9719,-0.9524,-0.9270,-0.8841,-0.8030,-0.6575,-0.4348",\ +"-1.0024,-0.9828,-0.9575,-0.9145,-0.8334,-0.6879,-0.4653",\ +"-1.0840,-1.0645,-1.0391,-0.9961,-0.9150,-0.7695,-0.5469"); + } + + fall_constraint("SIG2SRAM_constraint_template") { + index_1("0.0080,0.0288,0.0616,0.1072,0.1920,0.3496,0.5952"); + index_2("0.0080,0.0288,0.0616,0.1072,0.1920,0.3496,0.5952"); + values ("-0.8550,-0.8374,-0.8101,-0.7710,-0.6880,-0.5523,-0.3403",\ +"-0.8625,-0.8449,-0.8175,-0.7785,-0.6955,-0.5597,-0.3478",\ +"-0.8720,-0.8545,-0.8271,-0.7881,-0.7050,-0.5693,-0.3574",\ +"-0.8852,-0.8676,-0.8403,-0.8012,-0.7182,-0.5825,-0.3705",\ +"-0.9094,-0.8919,-0.8645,-0.8255,-0.7424,-0.6067,-0.3948",\ +"-0.9399,-0.9223,-0.8950,-0.8559,-0.7729,-0.6371,-0.4252",\ +"-1.0215,-1.0039,-0.9766,-0.9375,-0.8545,-0.7188,-0.5069"); + } + } + + timing() { + timing_type : hold_rising; + related_pin : "B_BIST_CLK"; + when : "(B_BIST_WEN & B_BIST_MEN)"; + sdf_cond : "B_BIST_W_ACCESS"; + + rise_constraint("SIG2SRAM_constraint_template") { + index_1("0.0080,0.0288,0.0616,0.1072,0.1920,0.3496,0.5952"); + index_2("0.0080,0.0288,0.0616,0.1072,0.1920,0.3496,0.5952"); + values ("1.0343,1.0128,0.9884,0.9454,0.8653,0.7189,0.4962",\ +"1.0418,1.0203,0.9959,0.9529,0.8728,0.7263,0.5037",\ +"1.0513,1.0298,1.0054,0.9625,0.8824,0.7359,0.5132",\ +"1.0645,1.0430,1.0186,0.9756,0.8955,0.7491,0.5264",\ +"1.0887,1.0673,1.0428,0.9999,0.9198,0.7733,0.5507",\ +"1.1192,1.0977,1.0733,1.0303,0.9502,0.8037,0.5811",\ +"1.2008,1.1793,1.1549,1.1119,1.0318,0.8854,0.6627"); + } + + fall_constraint("SIG2SRAM_constraint_template") { + index_1("0.0080,0.0288,0.0616,0.1072,0.1920,0.3496,0.5952"); + index_2("0.0080,0.0288,0.0616,0.1072,0.1920,0.3496,0.5952"); + values ("0.9601,0.9425,0.9151,0.8761,0.7931,0.6564,0.4454",\ +"0.9675,0.9500,0.9226,0.8836,0.8005,0.6638,0.4529",\ +"0.9771,0.9595,0.9322,0.8931,0.8101,0.6734,0.4625",\ +"0.9903,0.9727,0.9453,0.9063,0.8233,0.6866,0.4756",\ +"1.0145,0.9969,0.9696,0.9305,0.8475,0.7108,0.4999",\ +"1.0450,1.0274,1.0000,0.9610,0.8780,0.7412,0.5303",\ +"1.1266,1.1090,1.0817,1.0426,0.9596,0.8229,0.6119"); + } + } + } + +bus(B_DOUT) { + + bus_type : D_31_0; + direction : output ; + capacitance : 0 ; + max_capacitance : 0.064 ; + memory_read() { + address : B_ADDR ; + } + pin(B_DOUT[31:0]) { + related_power_pin : VDD; + related_ground_pin : VSS; + internal_power() { + rise_power("scalar") { + values (0); + } + fall_power("scalar") { + values (0); + } + } + } + timing() { + related_pin : "B_CLK"; + timing_type : rising_edge ; + timing_sense : non_unate ; + + cell_rise(SIG2SRAM_delay_template) { + index_1("0.0080,0.0288,0.0616,0.1072,0.1920,0.3496,0.5952"); + index_2("0.0008,0.0014,0.0051,0.0100,0.0339,0.0640"); + values ("6.5553,6.5586,6.5708,6.5847,6.6373,6.6952",\ +"6.5596,6.5630,6.5752,6.5891,6.6417,6.6995",\ +"6.5701,6.5734,6.5856,6.5995,6.6521,6.7100",\ +"6.5907,6.5941,6.6063,6.6202,6.6728,6.7306",\ +"6.6050,6.6083,6.6205,6.6345,6.6870,6.7449",\ +"6.6384,6.6418,6.6540,6.6679,6.7205,6.7783",\ +"6.7241,6.7275,6.7397,6.7536,6.8062,6.8640"); + } + cell_fall(SIG2SRAM_delay_template) { + index_1("0.0080,0.0288,0.0616,0.1072,0.1920,0.3496,0.5952"); + index_2("0.0008,0.0014,0.0051,0.0100,0.0339,0.0640"); + values ("6.4455,6.4477,6.4577,6.4694,6.5128,6.5566",\ +"6.4499,6.4521,6.4621,6.4738,6.5171,6.5610",\ +"6.4603,6.4625,6.4725,6.4842,6.5276,6.5714",\ +"6.4810,6.4832,6.4932,6.5049,6.5482,6.5921",\ +"6.4953,6.4974,6.5075,6.5191,6.5625,6.6063",\ +"6.5287,6.5309,6.5409,6.5526,6.5959,6.6398",\ +"6.6144,6.6166,6.6266,6.6383,6.6816,6.7255"); + } + + rise_transition(SRAM_load_template) { + index_1("0.0008,0.0014,0.0051,0.0100,0.0339,0.0640"); + values ("0.0560,0.0583,0.0696,0.0816,0.1519,0.2335"); + } + fall_transition(SRAM_load_template) { + index_1("0.0008,0.0014,0.0051,0.0100,0.0339,0.0640"); + values ("0.0428,0.0445,0.0538,0.0658,0.1181,0.1751"); + } + } +} +cell_leakage_power : 1906.3142; +} +} diff --git a/flow/platforms/ihp-sg13g2/lib/RM_IHPSG13_2P_512x32_c2_bm_bist_typ_1p20V_25C.lib b/flow/platforms/ihp-sg13g2/lib/RM_IHPSG13_2P_512x32_c2_bm_bist_typ_1p20V_25C.lib new file mode 100644 index 0000000000..ce9e019934 --- /dev/null +++ b/flow/platforms/ihp-sg13g2/lib/RM_IHPSG13_2P_512x32_c2_bm_bist_typ_1p20V_25C.lib @@ -0,0 +1,2886 @@ +/* ------------------------------------------------------*/ +/**/ +/* Copyright 2025 IHP PDK Authors*/ +/**/ +/* Licensed under the Apache License, Version 2.0 (the "License");*/ +/* you may not use this file except in compliance with the License.*/ +/* You may obtain a copy of the License at*/ +/* */ +/* https://www.apache.org/licenses/LICENSE-2.0*/ +/* */ +/* Unless required by applicable law or agreed to in writing, software*/ +/* distributed under the License is distributed on an "AS IS" BASIS,*/ +/* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.*/ +/* See the License for the specific language governing permissions and*/ +/* limitations under the License.*/ +/* */ +/* Generated on Wed Aug 27 13:11:29 2025 */ +/* */ +/* ------------------------------------------------------ */ +library(RM_IHPSG13_2P_512x32_c2_bm_bist_typ_1p20V_25C) { + technology (cmos) ; + delay_model : table_lookup ; + define ("add_pg_pin_to_lib", "library", "boolean"); + add_pg_pin_to_lib : true; + voltage_map ( VDD, 1.20); + voltage_map ( VDDARRAY, 1.20); + voltage_map ( VSS, 0.000000 ); + + date : "Wed Aug 27 13:11:26 2025" ; + comment : "IHP Microelectronics GmbH, 2023" ; + revision : 1.0.0 ; + simulation : true ; + nom_process : 1 ; + nom_temperature : 25 ; + nom_voltage : 1.20 ; + + operating_conditions("typ_1p20V_25C"){ + process : 1 ; + temperature : 25 ; + voltage : 1.20 ; + tree_type : "balanced_tree" ; + } + + default_operating_conditions : typ_1p20V_25C ; + default_max_transition : 1.0 ; + default_fanout_load : 1.0 ; + default_inout_pin_cap : 0.0 ; + default_input_pin_cap : 0.0 ; + default_output_pin_cap : 0.0 ; + default_cell_leakage_power : 0.0 ; + default_leakage_power_density : 0.0 ; + + slew_lower_threshold_pct_rise : 30 ; + slew_upper_threshold_pct_rise : 70 ; + input_threshold_pct_fall : 50 ; + output_threshold_pct_fall : 50 ; + input_threshold_pct_rise : 50 ; + output_threshold_pct_rise : 50 ; + slew_lower_threshold_pct_fall : 30 ; + slew_upper_threshold_pct_fall : 70 ; + slew_derate_from_library : 0.5; + k_volt_cell_leakage_power : 0.0 ; + k_temp_cell_leakage_power : 0.0 ; + k_process_cell_leakage_power : 0.0 ; + k_volt_internal_power : 0.0 ; + k_temp_internal_power : 0.0 ; + k_process_internal_power : 0.0 ; + + capacitive_load_unit (1,pf) ; + voltage_unit : "1V" ; + current_unit : "1uA" ; + time_unit : "1ns" ; + leakage_power_unit : "1nW" ; + pulling_resistance_unit : "1kohm"; + /* + ------------------------------------------------------------------------------------------ + implicit units overview: + cell_area unit : "um" + internal_power unit : "1e-12 * J/toggle = 1 * uW/MHz" + (capacitive_load_unit * voltage_unit^2) per toggle event + ------------------------------------------------------------------------------------------ + */ + library_features(report_delay_calculation); + define_cell_area (pad_drivers,pad_driver_sites) ; + + lu_table_template(CLKTRAN_constraint_template) { + variable_1 : constrained_pin_transition; + index_1 ( "0.010, 0.050, 0.200, 0.400, 1.000" ); + } + lu_table_template(SRAM_load_template) { + variable_1 : total_output_net_capacitance; + index_1 ( "0.0008,0.0014,0.0051,0.0100,0.0339,0.0640" ); + } + lu_table_template(SIG2SRAM_constraint_template) { + variable_1 : related_pin_transition; + variable_2 : constrained_pin_transition; + index_1 ( "0.0056,0.0232,0.0400,0.0728,0.1280,0.2440,0.4760" ); + index_2 ( "0.0056,0.0232,0.0400,0.0728,0.1280,0.2440,0.4760" ); + } + + lu_table_template(SIG2SRAM_delay_template) { + variable_1 : input_net_transition; + variable_2 : total_output_net_capacitance; + index_1 ( "0.0056,0.0232,0.0400,0.0728,0.1280,0.2440,0.4760" ); + index_2 ( "0.0008,0.0014,0.0051,0.0100,0.0339,0.0640" ); + } + + type (D_31_0) { + base_type : array; + data_type : bit; + bit_width : 32; + bit_from : 31; + bit_to : 0; + downto : true; + } + + type (A_8_0) { + base_type : array; + data_type : bit; + bit_width : 9; + bit_from : 8; + bit_to : 0; + downto : true; + } + +cell(RM_IHPSG13_2P_512x32_c2_bm_bist) { +pg_pin (VDD) { + pg_type : primary_power; + voltage_name : VDD; +} +pg_pin (VDDARRAY) { + pg_type : primary_power; + voltage_name : VDDARRAY; +} +pg_pin (VSS) { + pg_type : primary_ground; + voltage_name : VSS; +} + +memory() { + type : ram; + address_width : 9; + word_width : 32; +} + +interface_timing : false; +bus_naming_style : "%s[%d]" ; +area : 150650.1373 ; + + pin(A_DLY) { + direction : input ; + capacitance : 0.00401111 ; + max_transition : "1" ; + related_power_pin : VDD; + related_ground_pin : VSS; + internal_power() { + rise_power("scalar") { + values (0); + } + fall_power("scalar") { + values (0); + } + } + } + +bus(A_ADDR) { + bus_type : A_8_0; + direction : input ; + capacitance : 0.0121077 ; + pin(A_ADDR[0]) { + capacitance : 0.00568653 ; + } + pin(A_ADDR[1]) { + capacitance : 0.00767263 ; + } + pin(A_ADDR[2]) { + capacitance : 0.0105079 ; + } + pin(A_ADDR[3]) { + capacitance : 0.0068178 ; + } + pin(A_ADDR[4]) { + capacitance : 0.00624497 ; + } + pin(A_ADDR[5]) { + capacitance : 0.0105871 ; + } + pin(A_ADDR[6]) { + capacitance : 0.0130817 ; + } + pin(A_ADDR[7]) { + capacitance : 0.0104931 ; + } + max_transition : "0.476" ; + pin(A_ADDR[8:0]) { + related_power_pin : VDD; + related_ground_pin : VSS; + internal_power() { + when : "A_MEN"; + rise_power("scalar"){ + values (0.0106); + } + fall_power("scalar"){ + values (0.0054); + } + } + internal_power() { + when : "!A_MEN"; + rise_power("scalar"){ + values (0.0143); + } + fall_power("scalar"){ + values (0.0003); + } + } + } + timing() { + timing_type : setup_rising; + related_pin : "A_CLK"; + when : "((A_WEN | A_REN)& A_MEN)" + sdf_cond : "A_RW_ACCESS" + + rise_constraint("SIG2SRAM_constraint_template") { + index_1("0.0056,0.0232,0.0400,0.0728,0.1280,0.2440,0.4760"); + index_2("0.0056,0.0232,0.0400,0.0728,0.1280,0.2440,0.4760"); + values ("-0.4168,-0.3973,-0.3855,-0.3543,-0.3074,-0.2020,-0.0027",\ +"-0.4324,-0.4129,-0.4012,-0.3699,-0.3191,-0.2176,-0.0184",\ +"-0.4441,-0.4285,-0.4129,-0.3816,-0.3309,-0.2293,-0.0301",\ +"-0.4793,-0.4598,-0.4441,-0.4129,-0.3660,-0.2645,-0.0652",\ +"-0.5223,-0.5066,-0.4910,-0.4598,-0.4129,-0.3074,-0.1121",\ +"-0.6199,-0.6082,-0.5926,-0.5613,-0.5145,-0.4129,-0.2137",\ +"-0.8191,-0.8074,-0.7840,-0.7566,-0.7098,-0.6082,-0.4051"); + } + + fall_constraint("SIG2SRAM_constraint_template") { + index_1("0.0056,0.0232,0.0400,0.0728,0.1280,0.2440,0.4760"); + index_2("0.0056,0.0232,0.0400,0.0728,0.1280,0.2440,0.4760"); + values ("-0.3309,-0.3113,-0.2996,-0.2684,-0.2176,-0.1238,0.0637",\ +"-0.3465,-0.3309,-0.3152,-0.2840,-0.2332,-0.1395,0.0480",\ +"-0.3582,-0.3426,-0.3270,-0.2996,-0.2488,-0.1512,0.0324",\ +"-0.3895,-0.3738,-0.3582,-0.3309,-0.2801,-0.1863,0.0051",\ +"-0.4363,-0.4207,-0.4051,-0.3777,-0.3230,-0.2293,-0.0379",\ +"-0.5379,-0.5223,-0.5066,-0.4793,-0.4285,-0.3309,-0.1434",\ +"-0.7332,-0.7176,-0.7020,-0.6746,-0.6238,-0.5262,-0.3387"); + } + } + + + timing() { + timing_type : hold_rising; + related_pin : "A_CLK"; + when : "((A_WEN | A_REN)& A_MEN)" + sdf_cond : "A_RW_ACCESS" + + rise_constraint("SIG2SRAM_constraint_template") { + index_1("0.0056,0.0232,0.0400,0.0728,0.1280,0.2440,0.4760"); + index_2("0.0056,0.0232,0.0400,0.0728,0.1280,0.2440,0.4760"); + values ("0.5246,0.5051,0.4895,0.4582,0.4113,0.3059,0.1066",\ +"0.5402,0.5207,0.5051,0.4777,0.4270,0.3215,0.1223",\ +"0.5520,0.5324,0.5168,0.4895,0.4387,0.3371,0.1340",\ +"0.5832,0.5676,0.5520,0.5207,0.4738,0.3684,0.1691",\ +"0.6301,0.6105,0.5949,0.5676,0.5168,0.4113,0.2160",\ +"0.7316,0.7121,0.7004,0.6691,0.6223,0.5168,0.3176",\ +"0.9270,0.9230,0.8957,0.8645,0.8137,0.7121,0.5168"); + } + + fall_constraint("SIG2SRAM_constraint_template") { + index_1("0.0056,0.0232,0.0400,0.0728,0.1280,0.2440,0.4760"); + index_2("0.0056,0.0232,0.0400,0.0728,0.1280,0.2440,0.4760"); + values ("0.4309,0.4152,0.4035,0.3684,0.3215,0.2277,0.0363",\ +"0.4465,0.4309,0.4152,0.3879,0.3371,0.2395,0.0559",\ +"0.4582,0.4426,0.4309,0.3996,0.3488,0.2551,0.0715",\ +"0.4934,0.4777,0.4621,0.4348,0.3840,0.2863,0.0988",\ +"0.5363,0.5207,0.5051,0.4777,0.4270,0.3332,0.1418",\ +"0.6379,0.6262,0.6105,0.5793,0.5324,0.4348,0.2434",\ +"0.8332,0.8215,0.8059,0.7707,0.7238,0.6301,0.4387"); + } + } +} +pin(A_WEN) { + direction : input ; + capacitance : 0.00324098 ; + max_transition : "0.476" ; + related_power_pin : VDD; + related_ground_pin : VSS; + internal_power() { + when : "A_MEN"; + rise_power("scalar"){ + values (0.0046); + } + fall_power("scalar"){ + values (0.0040); + } + } + internal_power() { + when : "!A_MEN"; + rise_power("scalar"){ + values (0.0044); + } + fall_power("scalar"){ + values (0.0043); + } + } + timing() { + timing_type : setup_rising; + related_pin : "A_CLK"; + when : "A_MEN" + sdf_cond : "A_MEN" + + rise_constraint("SIG2SRAM_constraint_template") { + index_1("0.0056,0.0232,0.0400,0.0728,0.1280,0.2440,0.4760"); + index_2("0.0056,0.0232,0.0400,0.0728,0.1280,0.2440,0.4760"); + values ("0.2043,0.2199,0.2316,0.2629,0.3059,0.4113,0.6066",\ +"0.1887,0.2043,0.2160,0.2473,0.2941,0.3957,0.5949",\ +"0.1691,0.1848,0.2004,0.2316,0.2785,0.3801,0.5754",\ +"0.1379,0.1574,0.1691,0.2004,0.2473,0.3527,0.5480",\ +"0.0910,0.1066,0.1223,0.1535,0.2004,0.2980,0.4973",\ +"-0.0105,0.0051,0.0207,0.0520,0.0949,0.2004,0.3957",\ +"-0.2059,-0.1902,-0.1746,-0.1473,-0.1004,0.0051,0.2004"); + } + + fall_constraint("SIG2SRAM_constraint_template") { + index_1("0.0056,0.0232,0.0400,0.0728,0.1280,0.2440,0.4760"); + index_2("0.0056,0.0232,0.0400,0.0728,0.1280,0.2440,0.4760"); + values ("0.2941,0.3098,0.3215,0.3488,0.4035,0.4973,0.6887",\ +"0.2785,0.2941,0.3059,0.3332,0.3840,0.4816,0.6691",\ +"0.2629,0.2785,0.2902,0.3176,0.3684,0.4660,0.6535",\ +"0.2316,0.2473,0.2590,0.2863,0.3410,0.4348,0.6262",\ +"0.1848,0.2004,0.2121,0.2395,0.2902,0.3879,0.5754",\ +"0.0832,0.0988,0.1105,0.1379,0.1809,0.2746,0.4699",\ +"-0.1121,-0.0965,-0.0848,-0.0535,-0.0066,0.0910,0.2824"); + } + } + + + timing() { + timing_type : hold_rising; + related_pin : "A_CLK"; + when : "A_MEN" + sdf_cond : "A_MEN" + + rise_constraint("SIG2SRAM_constraint_template") { + index_1("0.0056,0.0232,0.0400,0.0728,0.1280,0.2440,0.4760"); + index_2("0.0056,0.0232,0.0400,0.0728,0.1280,0.2440,0.4760"); + values ("0.2473,0.2316,0.2160,0.1887,0.1379,0.0363,-0.1629",\ +"0.2629,0.2473,0.2316,0.2043,0.1535,0.0520,-0.1473",\ +"0.2785,0.2590,0.2434,0.2160,0.1652,0.0676,-0.1355",\ +"0.3098,0.2941,0.2785,0.2473,0.1965,0.0910,-0.1043",\ +"0.3527,0.3371,0.3215,0.2941,0.2434,0.1418,-0.0574",\ +"0.4582,0.4426,0.4270,0.3957,0.3488,0.2434,0.0480",\ +"0.6535,0.6379,0.6184,0.5910,0.5402,0.4426,0.2434"); + } + + fall_constraint("SIG2SRAM_constraint_template") { + index_1("0.0056,0.0232,0.0400,0.0728,0.1280,0.2440,0.4760"); + index_2("0.0056,0.0232,0.0400,0.0728,0.1280,0.2440,0.4760"); + values ("0.2395,0.2238,0.2121,0.1809,0.1301,0.0324,-0.1551",\ +"0.2551,0.2395,0.2277,0.1965,0.1457,0.0480,-0.1395",\ +"0.2668,0.2551,0.2395,0.2082,0.1574,0.0637,-0.1277",\ +"0.3020,0.2863,0.2707,0.2395,0.1887,0.0910,-0.0965",\ +"0.3449,0.3293,0.3176,0.2863,0.2355,0.1379,-0.0496",\ +"0.4504,0.4348,0.4191,0.3879,0.3371,0.2395,0.0559",\ +"0.6457,0.6301,0.6145,0.5871,0.5324,0.4309,0.2512"); + } + } + } +pin(A_REN) { + direction : input ; + capacitance : 0.00381634 ; + max_transition : "0.476" ; + related_power_pin : VDD; + related_ground_pin : VSS; + internal_power() { + when : "A_MEN"; + rise_power("scalar"){ + values (0.0061); + } + fall_power("scalar"){ + values (0.0022); + } + } + internal_power() { + when : "!A_MEN"; + rise_power("scalar"){ + values (0.0063); + } + fall_power("scalar"){ + values (0.0027); + } + } + timing() { + timing_type : setup_rising; + related_pin : "A_CLK"; + when : "A_MEN" + sdf_cond : "A_MEN" + + rise_constraint("SIG2SRAM_constraint_template") { + index_1("0.0056,0.0232,0.0400,0.0728,0.1280,0.2440,0.4760"); + index_2("0.0056,0.0232,0.0400,0.0728,0.1280,0.2440,0.4760"); + values ("-0.0301,-0.0145,0.0012,0.0324,0.0793,0.1809,0.3762",\ +"-0.0457,-0.0301,-0.0145,0.0168,0.0637,0.1613,0.3605",\ +"-0.0574,-0.0418,-0.0262,0.0051,0.0520,0.1496,0.3449",\ +"-0.0926,-0.0730,-0.0574,-0.0262,0.0207,0.1184,0.3137",\ +"-0.1395,-0.1238,-0.1082,-0.0770,-0.0301,0.0715,0.2707",\ +"-0.2410,-0.2254,-0.2098,-0.1746,-0.1355,-0.0340,0.1652",\ +"-0.4402,-0.4207,-0.4051,-0.3738,-0.3270,-0.2293,-0.0340"); + } + + fall_constraint("SIG2SRAM_constraint_template") { + index_1("0.0056,0.0232,0.0400,0.0728,0.1280,0.2440,0.4760"); + index_2("0.0056,0.0232,0.0400,0.0728,0.1280,0.2440,0.4760"); + values ("0.0988,0.1145,0.1262,0.1535,0.2043,0.3020,0.4855",\ +"0.0832,0.0988,0.1105,0.1418,0.1848,0.2824,0.4738",\ +"0.0676,0.0832,0.0949,0.1262,0.1730,0.2668,0.4621",\ +"0.0402,0.0559,0.0676,0.0988,0.1457,0.2434,0.4191",\ +"-0.0105,0.0012,0.0168,0.0480,0.0988,0.1965,0.3840",\ +"-0.1160,-0.0965,-0.0848,-0.0535,-0.0066,0.0988,0.2824",\ +"-0.3113,-0.2957,-0.2801,-0.2527,-0.2059,-0.1043,0.0832"); + } + } + + + timing() { + timing_type : hold_rising; + related_pin : "A_CLK"; + when : "A_MEN" + sdf_cond : "A_MEN" + + rise_constraint("SIG2SRAM_constraint_template") { + index_1("0.0056,0.0232,0.0400,0.0728,0.1280,0.2440,0.4760"); + index_2("0.0056,0.0232,0.0400,0.0728,0.1280,0.2440,0.4760"); + values ("0.2707,0.2551,0.2395,0.2121,0.1613,0.0598,-0.1395",\ +"0.2863,0.2707,0.2551,0.2238,0.1730,0.0715,-0.1238",\ +"0.2980,0.2824,0.2668,0.2395,0.1887,0.0871,-0.1121",\ +"0.3332,0.3176,0.3020,0.2707,0.2199,0.1184,-0.0809",\ +"0.3762,0.3605,0.3449,0.3176,0.2668,0.1613,-0.0340",\ +"0.4816,0.4621,0.4504,0.4191,0.3723,0.2629,0.0715",\ +"0.6770,0.6613,0.6418,0.6184,0.5637,0.4699,0.2629"); + } + + fall_constraint("SIG2SRAM_constraint_template") { + index_1("0.0056,0.0232,0.0400,0.0728,0.1280,0.2440,0.4760"); + index_2("0.0056,0.0232,0.0400,0.0728,0.1280,0.2440,0.4760"); + values ("0.2590,0.2434,0.2316,0.2004,0.1457,0.0520,-0.1355",\ +"0.2746,0.2590,0.2434,0.2160,0.1613,0.0676,-0.1199",\ +"0.2863,0.2707,0.2590,0.2277,0.1730,0.0832,-0.1082",\ +"0.3215,0.3059,0.2902,0.2590,0.2082,0.1105,-0.0770",\ +"0.3645,0.3488,0.3332,0.3059,0.2551,0.1535,-0.0340",\ +"0.4699,0.4543,0.4387,0.4074,0.3605,0.2551,0.0715",\ +"0.6652,0.6496,0.6340,0.6027,0.5520,0.4621,0.2707"); + } + } + } +pin(A_MEN) { + direction : input ; + capacitance : 0.00309605 ; + max_transition : "0.476" ; + related_power_pin : VDD; + related_ground_pin : VSS; + internal_power() { + rise_power("scalar"){ + values (0.0874); + } + fall_power("scalar"){ + values (0.0053); + } + } + timing() { + timing_type : setup_rising; + related_pin : "A_CLK"; + + rise_constraint("SIG2SRAM_constraint_template") { + index_1("0.0056,0.0232,0.0400,0.0728,0.1280,0.2440,0.4760"); + index_2("0.0056,0.0232,0.0400,0.0728,0.1280,0.2440,0.4760"); + values ("0.2043,0.2199,0.2316,0.2668,0.3098,0.4152,0.6066",\ +"0.1887,0.2043,0.2199,0.2512,0.2941,0.3996,0.5949",\ +"0.1730,0.1887,0.2043,0.2355,0.2824,0.3840,0.5793",\ +"0.1418,0.1574,0.1730,0.2043,0.2512,0.3566,0.5480",\ +"0.0949,0.1105,0.1262,0.1574,0.2043,0.3020,0.5051",\ +"-0.0066,0.0090,0.0246,0.0520,0.0988,0.2043,0.3996",\ +"-0.2020,-0.1863,-0.1746,-0.1434,-0.0965,0.0090,0.2082"); + } + + fall_constraint("SIG2SRAM_constraint_template") { + index_1("0.0056,0.0232,0.0400,0.0728,0.1280,0.2440,0.4760"); + index_2("0.0056,0.0232,0.0400,0.0728,0.1280,0.2440,0.4760"); + values ("0.2980,0.3137,0.3254,0.3527,0.4035,0.5012,0.6887",\ +"0.2824,0.2980,0.3098,0.3371,0.3879,0.4855,0.6730",\ +"0.2668,0.2824,0.2941,0.3215,0.3723,0.4699,0.6574",\ +"0.2355,0.2473,0.2629,0.2902,0.3410,0.4387,0.6262",\ +"0.1887,0.2004,0.2160,0.2395,0.2941,0.3918,0.5793",\ +"0.0871,0.1027,0.1145,0.1418,0.1848,0.2746,0.4816",\ +"-0.1082,-0.0965,-0.0809,-0.0496,-0.0027,0.0949,0.2863"); + } + } + + + timing() { + timing_type : hold_rising; + related_pin : "A_CLK"; + + rise_constraint("SIG2SRAM_constraint_template") { + index_1("0.0056,0.0232,0.0400,0.0728,0.1280,0.2440,0.4760"); + index_2("0.0056,0.0232,0.0400,0.0728,0.1280,0.2440,0.4760"); + values ("0.2512,0.2355,0.2199,0.1926,0.1418,0.0402,-0.1590",\ +"0.2668,0.2512,0.2355,0.2082,0.1574,0.0559,-0.1434",\ +"0.2824,0.2629,0.2512,0.2199,0.1691,0.0715,-0.1316",\ +"0.3137,0.2980,0.2824,0.2512,0.2004,0.0988,-0.0965",\ +"0.3566,0.3410,0.3254,0.2980,0.2473,0.1418,-0.0535",\ +"0.4621,0.4426,0.4309,0.3996,0.3527,0.2473,0.0520",\ +"0.6574,0.6418,0.6262,0.5949,0.5441,0.4465,0.2473"); + } + + fall_constraint("SIG2SRAM_constraint_template") { + index_1("0.0056,0.0232,0.0400,0.0728,0.1280,0.2440,0.4760"); + index_2("0.0056,0.0232,0.0400,0.0728,0.1280,0.2440,0.4760"); + values ("0.2395,0.2238,0.2121,0.1809,0.1301,0.0324,-0.1551",\ +"0.2551,0.2434,0.2277,0.1965,0.1457,0.0480,-0.1395",\ +"0.2707,0.2551,0.2395,0.2082,0.1574,0.0637,-0.1277",\ +"0.3020,0.2863,0.2707,0.2434,0.1926,0.0910,-0.0965",\ +"0.3449,0.3332,0.3176,0.2863,0.2355,0.1379,-0.0496",\ +"0.4504,0.4348,0.4230,0.3918,0.3410,0.2434,0.0559",\ +"0.6457,0.6301,0.6145,0.5910,0.5324,0.4387,0.2512"); + } + } + } +bus(A_BM) { + bus_type : D_31_0; + direction : input ; + capacitance : 0.00372627 ; + max_transition : "0.476" ; + pin(A_BM[31:0]) { + related_power_pin : VDD; + related_ground_pin : VSS; + internal_power() { + when : "A_MEN"; + rise_power("scalar"){ + values (0.1133); + } + fall_power("scalar"){ + values (0.0512); + } + } + internal_power() { + when : "!A_MEN"; + rise_power("scalar"){ + values (0.1175); + } + fall_power("scalar"){ + values (0.0489); + } + } + } + timing() { + timing_type : setup_rising; + related_pin : "A_CLK"; + when : "(A_WEN & A_MEN)" + sdf_cond : "A_RW_ACCESS" + + rise_constraint("SIG2SRAM_constraint_template") { + index_1("0.0056,0.0232,0.0400,0.0728,0.1280,0.2440,0.4760"); + index_2("0.0056,0.0232,0.0400,0.0728,0.1280,0.2440,0.4760"); + values ("-0.5146,-0.4990,-0.4853,-0.4531,-0.4062,-0.3017,-0.1103",\ +"-0.5196,-0.5040,-0.4903,-0.4581,-0.4112,-0.3067,-0.1153",\ +"-0.5241,-0.5085,-0.4948,-0.4626,-0.4157,-0.3112,-0.1198",\ +"-0.5332,-0.5176,-0.5039,-0.4717,-0.4248,-0.3203,-0.1289",\ +"-0.5405,-0.5248,-0.5112,-0.4789,-0.4321,-0.3276,-0.1362",\ +"-0.5706,-0.5549,-0.5413,-0.5090,-0.4621,-0.3577,-0.1663",\ +"-0.6281,-0.6125,-0.5988,-0.5666,-0.5197,-0.4153,-0.2238"); + } + + fall_constraint("SIG2SRAM_constraint_template") { + index_1("0.0056,0.0232,0.0400,0.0728,0.1280,0.2440,0.4760"); + index_2("0.0056,0.0232,0.0400,0.0728,0.1280,0.2440,0.4760"); + values ("-0.4765,-0.4619,-0.4482,-0.4199,-0.3691,-0.2715,-0.0888",\ +"-0.4815,-0.4669,-0.4532,-0.4249,-0.3741,-0.2765,-0.0938",\ +"-0.4860,-0.4714,-0.4577,-0.4294,-0.3786,-0.2809,-0.0983",\ +"-0.4951,-0.4805,-0.4668,-0.4385,-0.3877,-0.2900,-0.1074",\ +"-0.5024,-0.4877,-0.4741,-0.4457,-0.3950,-0.2973,-0.1147",\ +"-0.5325,-0.5178,-0.5041,-0.4758,-0.4250,-0.3274,-0.1448",\ +"-0.5901,-0.5754,-0.5617,-0.5334,-0.4826,-0.3850,-0.2024"); + } + } + + + timing() { + timing_type : hold_rising; + related_pin : "A_CLK"; + when : "(A_WEN & A_MEN)" + sdf_cond : "A_RW_ACCESS" + + rise_constraint("SIG2SRAM_constraint_template") { + index_1("0.0056,0.0232,0.0400,0.0728,0.1280,0.2440,0.4760"); + index_2("0.0056,0.0232,0.0400,0.0728,0.1280,0.2440,0.4760"); + values ("0.6250,0.6084,0.5957,0.5635,0.5156,0.4121,0.2197",\ +"0.6300,0.6134,0.6007,0.5685,0.5206,0.4171,0.2247",\ +"0.6345,0.6179,0.6052,0.5729,0.5251,0.4216,0.2292",\ +"0.6436,0.6270,0.6143,0.5820,0.5342,0.4307,0.2383",\ +"0.6508,0.6342,0.6215,0.5893,0.5415,0.4379,0.2456",\ +"0.6809,0.6643,0.6516,0.6194,0.5715,0.4680,0.2756",\ +"0.7385,0.7219,0.7092,0.6770,0.6291,0.5256,0.3332"); + } + + fall_constraint("SIG2SRAM_constraint_template") { + index_1("0.0056,0.0232,0.0400,0.0728,0.1280,0.2440,0.4760"); + index_2("0.0056,0.0232,0.0400,0.0728,0.1280,0.2440,0.4760"); + values ("0.5791,0.5644,0.5508,0.5224,0.4726,0.3799,0.1953",\ +"0.5841,0.5694,0.5558,0.5274,0.4776,0.3849,0.2003",\ +"0.5886,0.5739,0.5602,0.5319,0.4821,0.3893,0.2048",\ +"0.5977,0.5830,0.5693,0.5410,0.4912,0.3984,0.2139",\ +"0.6049,0.5903,0.5766,0.5483,0.4985,0.4057,0.2211",\ +"0.6350,0.6204,0.6067,0.5784,0.5286,0.4358,0.2512",\ +"0.6926,0.6780,0.6643,0.6360,0.5862,0.4934,0.3088"); + } + } +} + pin(A_CLK) { + direction : input; + capacitance : 0.00380014; + max_transition : "0.476"; + clock : "true" ; + pin_func_type : active_rising ; + + timing () { + timing_type : "min_pulse_width"; + related_pin : "A_CLK"; + rise_constraint("CLKTRAN_constraint_template") { + index_1("0.0056,0.476"); + values("0.21,0.21"); + } + } + + related_power_pin : VDD; + related_ground_pin : VSS; + + internal_power() { + when : "!A_MEN & !A_WEN & !A_REN"; + rise_power("scalar"){ + values (0); + } + fall_power("scalar"){ + values (0); + } + } + internal_power() { + when : "!A_MEN & A_WEN & !A_REN"; + rise_power("scalar"){ + values (0.5389); + } + fall_power("scalar"){ + values (0); + } + } + internal_power() { + when : "A_MEN & A_WEN & !A_REN"; + rise_power("scalar"){ + values (42.3165); + } + fall_power("scalar"){ + values (0); + } + } + internal_power() { + when : "A_MEN & A_WEN & A_REN"; + rise_power("scalar"){ + values (47.6101); + } + fall_power("scalar"){ + values (0); + } + } + internal_power() { + when : "A_MEN & !A_WEN & A_REN"; + rise_power("scalar"){ + values (36.0099); + } + fall_power("scalar"){ + values (0); + } + } + internal_power() { + when : "!A_MEN & !A_WEN & A_REN"; + rise_power("scalar"){ + values (0.3230); + } + fall_power("scalar"){ + values (0); + } + } + internal_power() { + when : "!A_MEN & A_WEN & A_REN"; + rise_power("scalar"){ + values (1.2182); + } + fall_power("scalar"){ + values (0); + } + } + internal_power() { + when : "A_MEN & !A_WEN & !A_REN"; + rise_power("scalar"){ + values (0); + } + fall_power("scalar"){ + values (0); + } + } + } + bus(A_DIN) { + bus_type : D_31_0; + direction : input ; + capacitance : 0.00500744 ; + memory_write() { + address : A_ADDR ; + clocked_on : A_CLK; + } + + max_transition : "0.476" ; + pin(A_DIN[31:0]) { + related_power_pin : VDD; + related_ground_pin : VSS; + internal_power() { + when : "A_MEN"; + rise_power("scalar"){ + values (0.1133); + } + fall_power("scalar"){ + values (0.0512); + } + } + internal_power() { + when : "!A_MEN"; + rise_power("scalar"){ + values (0.1175); + } + fall_power("scalar"){ + values (0.0489); + } + } + } + timing() { + timing_type : setup_rising; + related_pin : "A_CLK"; + when : "(A_WEN & A_MEN)"; + sdf_cond : "A_W_ACCESS"; + + rise_constraint("SIG2SRAM_constraint_template") { + index_1("0.0056,0.0232,0.0400,0.0728,0.1280,0.2440,0.4760"); + index_2("0.0056,0.0232,0.0400,0.0728,0.1280,0.2440,0.4760"); + values ("-0.5146,-0.4990,-0.4853,-0.4531,-0.4062,-0.3017,-0.1103",\ +"-0.5196,-0.5040,-0.4903,-0.4581,-0.4112,-0.3067,-0.1153",\ +"-0.5241,-0.5085,-0.4948,-0.4626,-0.4157,-0.3112,-0.1198",\ +"-0.5332,-0.5176,-0.5039,-0.4717,-0.4248,-0.3203,-0.1289",\ +"-0.5405,-0.5248,-0.5112,-0.4789,-0.4321,-0.3276,-0.1362",\ +"-0.5706,-0.5549,-0.5413,-0.5090,-0.4621,-0.3577,-0.1663",\ +"-0.6281,-0.6125,-0.5988,-0.5666,-0.5197,-0.4153,-0.2238"); + } + + fall_constraint("SIG2SRAM_constraint_template") { + index_1("0.0056,0.0232,0.0400,0.0728,0.1280,0.2440,0.4760"); + index_2("0.0056,0.0232,0.0400,0.0728,0.1280,0.2440,0.4760"); + values ("-0.4765,-0.4619,-0.4482,-0.4199,-0.3691,-0.2715,-0.0888",\ +"-0.4815,-0.4669,-0.4532,-0.4249,-0.3741,-0.2765,-0.0938",\ +"-0.4860,-0.4714,-0.4577,-0.4294,-0.3786,-0.2809,-0.0983",\ +"-0.4951,-0.4805,-0.4668,-0.4385,-0.3877,-0.2900,-0.1074",\ +"-0.5024,-0.4877,-0.4741,-0.4457,-0.3950,-0.2973,-0.1147",\ +"-0.5325,-0.5178,-0.5041,-0.4758,-0.4250,-0.3274,-0.1448",\ +"-0.5901,-0.5754,-0.5617,-0.5334,-0.4826,-0.3850,-0.2024"); + } + } + + timing() { + timing_type : hold_rising; + related_pin : "A_CLK"; + when : "(A_WEN & A_MEN)"; + sdf_cond : "A_W_ACCESS"; + + rise_constraint("SIG2SRAM_constraint_template") { + index_1("0.0056,0.0232,0.0400,0.0728,0.1280,0.2440,0.4760"); + index_2("0.0056,0.0232,0.0400,0.0728,0.1280,0.2440,0.4760"); + values ("0.6250,0.6084,0.5957,0.5635,0.5156,0.4121,0.2197",\ +"0.6300,0.6134,0.6007,0.5685,0.5206,0.4171,0.2247",\ +"0.6345,0.6179,0.6052,0.5729,0.5251,0.4216,0.2292",\ +"0.6436,0.6270,0.6143,0.5820,0.5342,0.4307,0.2383",\ +"0.6508,0.6342,0.6215,0.5893,0.5415,0.4379,0.2456",\ +"0.6809,0.6643,0.6516,0.6194,0.5715,0.4680,0.2756",\ +"0.7385,0.7219,0.7092,0.6770,0.6291,0.5256,0.3332"); + } + + fall_constraint("SIG2SRAM_constraint_template") { + index_1("0.0056,0.0232,0.0400,0.0728,0.1280,0.2440,0.4760"); + index_2("0.0056,0.0232,0.0400,0.0728,0.1280,0.2440,0.4760"); + values ("0.5791,0.5644,0.5508,0.5224,0.4726,0.3799,0.1953",\ +"0.5841,0.5694,0.5558,0.5274,0.4776,0.3849,0.2003",\ +"0.5886,0.5739,0.5602,0.5319,0.4821,0.3893,0.2048",\ +"0.5977,0.5830,0.5693,0.5410,0.4912,0.3984,0.2139",\ +"0.6049,0.5903,0.5766,0.5483,0.4985,0.4057,0.2211",\ +"0.6350,0.6204,0.6067,0.5784,0.5286,0.4358,0.2512",\ +"0.6926,0.6780,0.6643,0.6360,0.5862,0.4934,0.3088"); + } + } + } + + pin(A_BIST_EN) { + direction : input ; + capacitance : 0.00401111 ; + max_transition : "1" ; + related_power_pin : VDD; + related_ground_pin : VSS; + internal_power() { + rise_power("scalar") { + values (0); + } + fall_power("scalar") { + values (0); + } + } + } + +bus(A_BIST_ADDR) { + bus_type : A_8_0; + direction : input ; + capacitance : 0.0121077 ; + pin(A_BIST_ADDR[0]) { + capacitance : 0.00568653 ; + } + pin(A_BIST_ADDR[1]) { + capacitance : 0.00767263 ; + } + pin(A_BIST_ADDR[2]) { + capacitance : 0.0105079 ; + } + pin(A_BIST_ADDR[3]) { + capacitance : 0.0068178 ; + } + pin(A_BIST_ADDR[4]) { + capacitance : 0.00624497 ; + } + pin(A_BIST_ADDR[5]) { + capacitance : 0.0105871 ; + } + pin(A_BIST_ADDR[6]) { + capacitance : 0.0130817 ; + } + pin(A_BIST_ADDR[7]) { + capacitance : 0.0104931 ; + } + max_transition : "0.476" ; + pin(A_BIST_ADDR[8:0]) { + related_power_pin : VDD; + related_ground_pin : VSS; + internal_power() { + when : "A_BIST_MEN"; + rise_power("scalar"){ + values (0.0106); + } + fall_power("scalar"){ + values (0.0054); + } + } + internal_power() { + when : "!A_BIST_MEN"; + rise_power("scalar"){ + values (0.0143); + } + fall_power("scalar"){ + values (0.0003); + } + } + } + timing() { + timing_type : setup_rising; + related_pin : "A_BIST_CLK"; + when : "((A_BIST_WEN | A_BIST_REN)& A_BIST_MEN)" + sdf_cond : "A_BIST_RW_ACCESS" + + rise_constraint("SIG2SRAM_constraint_template") { + index_1("0.0056,0.0232,0.0400,0.0728,0.1280,0.2440,0.4760"); + index_2("0.0056,0.0232,0.0400,0.0728,0.1280,0.2440,0.4760"); + values ("-0.4168,-0.3973,-0.3855,-0.3543,-0.3074,-0.2020,-0.0027",\ +"-0.4324,-0.4129,-0.4012,-0.3699,-0.3191,-0.2176,-0.0184",\ +"-0.4441,-0.4285,-0.4129,-0.3816,-0.3309,-0.2293,-0.0301",\ +"-0.4793,-0.4598,-0.4441,-0.4129,-0.3660,-0.2645,-0.0652",\ +"-0.5223,-0.5066,-0.4910,-0.4598,-0.4129,-0.3074,-0.1121",\ +"-0.6199,-0.6082,-0.5926,-0.5613,-0.5145,-0.4129,-0.2137",\ +"-0.8191,-0.8074,-0.7840,-0.7566,-0.7098,-0.6082,-0.4051"); + } + + fall_constraint("SIG2SRAM_constraint_template") { + index_1("0.0056,0.0232,0.0400,0.0728,0.1280,0.2440,0.4760"); + index_2("0.0056,0.0232,0.0400,0.0728,0.1280,0.2440,0.4760"); + values ("-0.3309,-0.3113,-0.2996,-0.2684,-0.2176,-0.1238,0.0637",\ +"-0.3465,-0.3309,-0.3152,-0.2840,-0.2332,-0.1395,0.0480",\ +"-0.3582,-0.3426,-0.3270,-0.2996,-0.2488,-0.1512,0.0324",\ +"-0.3895,-0.3738,-0.3582,-0.3309,-0.2801,-0.1863,0.0051",\ +"-0.4363,-0.4207,-0.4051,-0.3777,-0.3230,-0.2293,-0.0379",\ +"-0.5379,-0.5223,-0.5066,-0.4793,-0.4285,-0.3309,-0.1434",\ +"-0.7332,-0.7176,-0.7020,-0.6746,-0.6238,-0.5262,-0.3387"); + } + } + + + timing() { + timing_type : hold_rising; + related_pin : "A_BIST_CLK"; + when : "((A_BIST_WEN | A_BIST_REN)& A_BIST_MEN)" + sdf_cond : "A_BIST_RW_ACCESS" + + rise_constraint("SIG2SRAM_constraint_template") { + index_1("0.0056,0.0232,0.0400,0.0728,0.1280,0.2440,0.4760"); + index_2("0.0056,0.0232,0.0400,0.0728,0.1280,0.2440,0.4760"); + values ("0.5246,0.5051,0.4895,0.4582,0.4113,0.3059,0.1066",\ +"0.5402,0.5207,0.5051,0.4777,0.4270,0.3215,0.1223",\ +"0.5520,0.5324,0.5168,0.4895,0.4387,0.3371,0.1340",\ +"0.5832,0.5676,0.5520,0.5207,0.4738,0.3684,0.1691",\ +"0.6301,0.6105,0.5949,0.5676,0.5168,0.4113,0.2160",\ +"0.7316,0.7121,0.7004,0.6691,0.6223,0.5168,0.3176",\ +"0.9270,0.9230,0.8957,0.8645,0.8137,0.7121,0.5168"); + } + + fall_constraint("SIG2SRAM_constraint_template") { + index_1("0.0056,0.0232,0.0400,0.0728,0.1280,0.2440,0.4760"); + index_2("0.0056,0.0232,0.0400,0.0728,0.1280,0.2440,0.4760"); + values ("0.4309,0.4152,0.4035,0.3684,0.3215,0.2277,0.0363",\ +"0.4465,0.4309,0.4152,0.3879,0.3371,0.2395,0.0559",\ +"0.4582,0.4426,0.4309,0.3996,0.3488,0.2551,0.0715",\ +"0.4934,0.4777,0.4621,0.4348,0.3840,0.2863,0.0988",\ +"0.5363,0.5207,0.5051,0.4777,0.4270,0.3332,0.1418",\ +"0.6379,0.6262,0.6105,0.5793,0.5324,0.4348,0.2434",\ +"0.8332,0.8215,0.8059,0.7707,0.7238,0.6301,0.4387"); + } + } +} +pin(A_BIST_WEN) { + direction : input ; + capacitance : 0.00324098 ; + max_transition : "0.476" ; + related_power_pin : VDD; + related_ground_pin : VSS; + internal_power() { + when : "A_BIST_MEN"; + rise_power("scalar"){ + values (0.0046); + } + fall_power("scalar"){ + values (0.0040); + } + } + internal_power() { + when : "!A_BIST_MEN"; + rise_power("scalar"){ + values (0.0044); + } + fall_power("scalar"){ + values (0.0043); + } + } + timing() { + timing_type : setup_rising; + related_pin : "A_BIST_CLK"; + when : "A_BIST_MEN" + sdf_cond : "A_BIST_MEN" + + rise_constraint("SIG2SRAM_constraint_template") { + index_1("0.0056,0.0232,0.0400,0.0728,0.1280,0.2440,0.4760"); + index_2("0.0056,0.0232,0.0400,0.0728,0.1280,0.2440,0.4760"); + values ("0.2043,0.2199,0.2316,0.2629,0.3059,0.4113,0.6066",\ +"0.1887,0.2043,0.2160,0.2473,0.2941,0.3957,0.5949",\ +"0.1691,0.1848,0.2004,0.2316,0.2785,0.3801,0.5754",\ +"0.1379,0.1574,0.1691,0.2004,0.2473,0.3527,0.5480",\ +"0.0910,0.1066,0.1223,0.1535,0.2004,0.2980,0.4973",\ +"-0.0105,0.0051,0.0207,0.0520,0.0949,0.2004,0.3957",\ +"-0.2059,-0.1902,-0.1746,-0.1473,-0.1004,0.0051,0.2004"); + } + + fall_constraint("SIG2SRAM_constraint_template") { + index_1("0.0056,0.0232,0.0400,0.0728,0.1280,0.2440,0.4760"); + index_2("0.0056,0.0232,0.0400,0.0728,0.1280,0.2440,0.4760"); + values ("0.2941,0.3098,0.3215,0.3488,0.4035,0.4973,0.6887",\ +"0.2785,0.2941,0.3059,0.3332,0.3840,0.4816,0.6691",\ +"0.2629,0.2785,0.2902,0.3176,0.3684,0.4660,0.6535",\ +"0.2316,0.2473,0.2590,0.2863,0.3410,0.4348,0.6262",\ +"0.1848,0.2004,0.2121,0.2395,0.2902,0.3879,0.5754",\ +"0.0832,0.0988,0.1105,0.1379,0.1809,0.2746,0.4699",\ +"-0.1121,-0.0965,-0.0848,-0.0535,-0.0066,0.0910,0.2824"); + } + } + + + timing() { + timing_type : hold_rising; + related_pin : "A_BIST_CLK"; + when : "A_BIST_MEN" + sdf_cond : "A_BIST_MEN" + + rise_constraint("SIG2SRAM_constraint_template") { + index_1("0.0056,0.0232,0.0400,0.0728,0.1280,0.2440,0.4760"); + index_2("0.0056,0.0232,0.0400,0.0728,0.1280,0.2440,0.4760"); + values ("0.2473,0.2316,0.2160,0.1887,0.1379,0.0363,-0.1629",\ +"0.2629,0.2473,0.2316,0.2043,0.1535,0.0520,-0.1473",\ +"0.2785,0.2590,0.2434,0.2160,0.1652,0.0676,-0.1355",\ +"0.3098,0.2941,0.2785,0.2473,0.1965,0.0910,-0.1043",\ +"0.3527,0.3371,0.3215,0.2941,0.2434,0.1418,-0.0574",\ +"0.4582,0.4426,0.4270,0.3957,0.3488,0.2434,0.0480",\ +"0.6535,0.6379,0.6184,0.5910,0.5402,0.4426,0.2434"); + } + + fall_constraint("SIG2SRAM_constraint_template") { + index_1("0.0056,0.0232,0.0400,0.0728,0.1280,0.2440,0.4760"); + index_2("0.0056,0.0232,0.0400,0.0728,0.1280,0.2440,0.4760"); + values ("0.2395,0.2238,0.2121,0.1809,0.1301,0.0324,-0.1551",\ +"0.2551,0.2395,0.2277,0.1965,0.1457,0.0480,-0.1395",\ +"0.2668,0.2551,0.2395,0.2082,0.1574,0.0637,-0.1277",\ +"0.3020,0.2863,0.2707,0.2395,0.1887,0.0910,-0.0965",\ +"0.3449,0.3293,0.3176,0.2863,0.2355,0.1379,-0.0496",\ +"0.4504,0.4348,0.4191,0.3879,0.3371,0.2395,0.0559",\ +"0.6457,0.6301,0.6145,0.5871,0.5324,0.4309,0.2512"); + } + } + } +pin(A_BIST_REN) { + direction : input ; + capacitance : 0.00381634 ; + max_transition : "0.476" ; + related_power_pin : VDD; + related_ground_pin : VSS; + internal_power() { + when : "A_BIST_MEN"; + rise_power("scalar"){ + values (0.0061); + } + fall_power("scalar"){ + values (0.0022); + } + } + internal_power() { + when : "!A_BIST_MEN"; + rise_power("scalar"){ + values (0.0063); + } + fall_power("scalar"){ + values (0.0027); + } + } + timing() { + timing_type : setup_rising; + related_pin : "A_BIST_CLK"; + when : "A_BIST_MEN" + sdf_cond : "A_BIST_MEN" + + rise_constraint("SIG2SRAM_constraint_template") { + index_1("0.0056,0.0232,0.0400,0.0728,0.1280,0.2440,0.4760"); + index_2("0.0056,0.0232,0.0400,0.0728,0.1280,0.2440,0.4760"); + values ("-0.0301,-0.0145,0.0012,0.0324,0.0793,0.1809,0.3762",\ +"-0.0457,-0.0301,-0.0145,0.0168,0.0637,0.1613,0.3605",\ +"-0.0574,-0.0418,-0.0262,0.0051,0.0520,0.1496,0.3449",\ +"-0.0926,-0.0730,-0.0574,-0.0262,0.0207,0.1184,0.3137",\ +"-0.1395,-0.1238,-0.1082,-0.0770,-0.0301,0.0715,0.2707",\ +"-0.2410,-0.2254,-0.2098,-0.1746,-0.1355,-0.0340,0.1652",\ +"-0.4402,-0.4207,-0.4051,-0.3738,-0.3270,-0.2293,-0.0340"); + } + + fall_constraint("SIG2SRAM_constraint_template") { + index_1("0.0056,0.0232,0.0400,0.0728,0.1280,0.2440,0.4760"); + index_2("0.0056,0.0232,0.0400,0.0728,0.1280,0.2440,0.4760"); + values ("0.0988,0.1145,0.1262,0.1535,0.2043,0.3020,0.4855",\ +"0.0832,0.0988,0.1105,0.1418,0.1848,0.2824,0.4738",\ +"0.0676,0.0832,0.0949,0.1262,0.1730,0.2668,0.4621",\ +"0.0402,0.0559,0.0676,0.0988,0.1457,0.2434,0.4191",\ +"-0.0105,0.0012,0.0168,0.0480,0.0988,0.1965,0.3840",\ +"-0.1160,-0.0965,-0.0848,-0.0535,-0.0066,0.0988,0.2824",\ +"-0.3113,-0.2957,-0.2801,-0.2527,-0.2059,-0.1043,0.0832"); + } + } + + + timing() { + timing_type : hold_rising; + related_pin : "A_BIST_CLK"; + when : "A_BIST_MEN" + sdf_cond : "A_BIST_MEN" + + rise_constraint("SIG2SRAM_constraint_template") { + index_1("0.0056,0.0232,0.0400,0.0728,0.1280,0.2440,0.4760"); + index_2("0.0056,0.0232,0.0400,0.0728,0.1280,0.2440,0.4760"); + values ("0.2707,0.2551,0.2395,0.2121,0.1613,0.0598,-0.1395",\ +"0.2863,0.2707,0.2551,0.2238,0.1730,0.0715,-0.1238",\ +"0.2980,0.2824,0.2668,0.2395,0.1887,0.0871,-0.1121",\ +"0.3332,0.3176,0.3020,0.2707,0.2199,0.1184,-0.0809",\ +"0.3762,0.3605,0.3449,0.3176,0.2668,0.1613,-0.0340",\ +"0.4816,0.4621,0.4504,0.4191,0.3723,0.2629,0.0715",\ +"0.6770,0.6613,0.6418,0.6184,0.5637,0.4699,0.2629"); + } + + fall_constraint("SIG2SRAM_constraint_template") { + index_1("0.0056,0.0232,0.0400,0.0728,0.1280,0.2440,0.4760"); + index_2("0.0056,0.0232,0.0400,0.0728,0.1280,0.2440,0.4760"); + values ("0.2590,0.2434,0.2316,0.2004,0.1457,0.0520,-0.1355",\ +"0.2746,0.2590,0.2434,0.2160,0.1613,0.0676,-0.1199",\ +"0.2863,0.2707,0.2590,0.2277,0.1730,0.0832,-0.1082",\ +"0.3215,0.3059,0.2902,0.2590,0.2082,0.1105,-0.0770",\ +"0.3645,0.3488,0.3332,0.3059,0.2551,0.1535,-0.0340",\ +"0.4699,0.4543,0.4387,0.4074,0.3605,0.2551,0.0715",\ +"0.6652,0.6496,0.6340,0.6027,0.5520,0.4621,0.2707"); + } + } + } +pin(A_BIST_MEN) { + direction : input ; + capacitance : 0.00309605 ; + max_transition : "0.476" ; + related_power_pin : VDD; + related_ground_pin : VSS; + internal_power() { + rise_power("scalar"){ + values (0.0874); + } + fall_power("scalar"){ + values (0.0053); + } + } + timing() { + timing_type : setup_rising; + related_pin : "A_BIST_CLK"; + + rise_constraint("SIG2SRAM_constraint_template") { + index_1("0.0056,0.0232,0.0400,0.0728,0.1280,0.2440,0.4760"); + index_2("0.0056,0.0232,0.0400,0.0728,0.1280,0.2440,0.4760"); + values ("0.2043,0.2199,0.2316,0.2668,0.3098,0.4152,0.6066",\ +"0.1887,0.2043,0.2199,0.2512,0.2941,0.3996,0.5949",\ +"0.1730,0.1887,0.2043,0.2355,0.2824,0.3840,0.5793",\ +"0.1418,0.1574,0.1730,0.2043,0.2512,0.3566,0.5480",\ +"0.0949,0.1105,0.1262,0.1574,0.2043,0.3020,0.5051",\ +"-0.0066,0.0090,0.0246,0.0520,0.0988,0.2043,0.3996",\ +"-0.2020,-0.1863,-0.1746,-0.1434,-0.0965,0.0090,0.2082"); + } + + fall_constraint("SIG2SRAM_constraint_template") { + index_1("0.0056,0.0232,0.0400,0.0728,0.1280,0.2440,0.4760"); + index_2("0.0056,0.0232,0.0400,0.0728,0.1280,0.2440,0.4760"); + values ("0.2980,0.3137,0.3254,0.3527,0.4035,0.5012,0.6887",\ +"0.2824,0.2980,0.3098,0.3371,0.3879,0.4855,0.6730",\ +"0.2668,0.2824,0.2941,0.3215,0.3723,0.4699,0.6574",\ +"0.2355,0.2473,0.2629,0.2902,0.3410,0.4387,0.6262",\ +"0.1887,0.2004,0.2160,0.2395,0.2941,0.3918,0.5793",\ +"0.0871,0.1027,0.1145,0.1418,0.1848,0.2746,0.4816",\ +"-0.1082,-0.0965,-0.0809,-0.0496,-0.0027,0.0949,0.2863"); + } + } + + + timing() { + timing_type : hold_rising; + related_pin : "A_BIST_CLK"; + + rise_constraint("SIG2SRAM_constraint_template") { + index_1("0.0056,0.0232,0.0400,0.0728,0.1280,0.2440,0.4760"); + index_2("0.0056,0.0232,0.0400,0.0728,0.1280,0.2440,0.4760"); + values ("0.2512,0.2355,0.2199,0.1926,0.1418,0.0402,-0.1590",\ +"0.2668,0.2512,0.2355,0.2082,0.1574,0.0559,-0.1434",\ +"0.2824,0.2629,0.2512,0.2199,0.1691,0.0715,-0.1316",\ +"0.3137,0.2980,0.2824,0.2512,0.2004,0.0988,-0.0965",\ +"0.3566,0.3410,0.3254,0.2980,0.2473,0.1418,-0.0535",\ +"0.4621,0.4426,0.4309,0.3996,0.3527,0.2473,0.0520",\ +"0.6574,0.6418,0.6262,0.5949,0.5441,0.4465,0.2473"); + } + + fall_constraint("SIG2SRAM_constraint_template") { + index_1("0.0056,0.0232,0.0400,0.0728,0.1280,0.2440,0.4760"); + index_2("0.0056,0.0232,0.0400,0.0728,0.1280,0.2440,0.4760"); + values ("0.2395,0.2238,0.2121,0.1809,0.1301,0.0324,-0.1551",\ +"0.2551,0.2434,0.2277,0.1965,0.1457,0.0480,-0.1395",\ +"0.2707,0.2551,0.2395,0.2082,0.1574,0.0637,-0.1277",\ +"0.3020,0.2863,0.2707,0.2434,0.1926,0.0910,-0.0965",\ +"0.3449,0.3332,0.3176,0.2863,0.2355,0.1379,-0.0496",\ +"0.4504,0.4348,0.4230,0.3918,0.3410,0.2434,0.0559",\ +"0.6457,0.6301,0.6145,0.5910,0.5324,0.4387,0.2512"); + } + } + } +bus(A_BIST_BM) { + bus_type : D_31_0; + direction : input ; + capacitance : 0.00349377 ; + max_transition : "0.476" ; + pin(A_BIST_BM[31:0]) { + related_power_pin : VDD; + related_ground_pin : VSS; + internal_power() { + when : "A_BIST_MEN"; + rise_power("scalar"){ + values (0.1133); + } + fall_power("scalar"){ + values (0.0512); + } + } + internal_power() { + when : "!A_BIST_MEN"; + rise_power("scalar"){ + values (0.1175); + } + fall_power("scalar"){ + values (0.0489); + } + } + } + timing() { + timing_type : setup_rising; + related_pin : "A_BIST_CLK"; + when : "(A_BIST_WEN & A_BIST_MEN)" + sdf_cond : "A_BIST_RW_ACCESS" + + rise_constraint("SIG2SRAM_constraint_template") { + index_1("0.0056,0.0232,0.0400,0.0728,0.1280,0.2440,0.4760"); + index_2("0.0056,0.0232,0.0400,0.0728,0.1280,0.2440,0.4760"); + values ("-0.5146,-0.4990,-0.4853,-0.4531,-0.4062,-0.3017,-0.1103",\ +"-0.5196,-0.5040,-0.4903,-0.4581,-0.4112,-0.3067,-0.1153",\ +"-0.5241,-0.5085,-0.4948,-0.4626,-0.4157,-0.3112,-0.1198",\ +"-0.5332,-0.5176,-0.5039,-0.4717,-0.4248,-0.3203,-0.1289",\ +"-0.5405,-0.5248,-0.5112,-0.4789,-0.4321,-0.3276,-0.1362",\ +"-0.5706,-0.5549,-0.5413,-0.5090,-0.4621,-0.3577,-0.1663",\ +"-0.6281,-0.6125,-0.5988,-0.5666,-0.5197,-0.4153,-0.2238"); + } + + fall_constraint("SIG2SRAM_constraint_template") { + index_1("0.0056,0.0232,0.0400,0.0728,0.1280,0.2440,0.4760"); + index_2("0.0056,0.0232,0.0400,0.0728,0.1280,0.2440,0.4760"); + values ("-0.4765,-0.4619,-0.4482,-0.4199,-0.3691,-0.2715,-0.0888",\ +"-0.4815,-0.4669,-0.4532,-0.4249,-0.3741,-0.2765,-0.0938",\ +"-0.4860,-0.4714,-0.4577,-0.4294,-0.3786,-0.2809,-0.0983",\ +"-0.4951,-0.4805,-0.4668,-0.4385,-0.3877,-0.2900,-0.1074",\ +"-0.5024,-0.4877,-0.4741,-0.4457,-0.3950,-0.2973,-0.1147",\ +"-0.5325,-0.5178,-0.5041,-0.4758,-0.4250,-0.3274,-0.1448",\ +"-0.5901,-0.5754,-0.5617,-0.5334,-0.4826,-0.3850,-0.2024"); + } + } + + + timing() { + timing_type : hold_rising; + related_pin : "A_BIST_CLK"; + when : "(A_BIST_WEN & A_BIST_MEN)" + sdf_cond : "A_BIST_RW_ACCESS" + + rise_constraint("SIG2SRAM_constraint_template") { + index_1("0.0056,0.0232,0.0400,0.0728,0.1280,0.2440,0.4760"); + index_2("0.0056,0.0232,0.0400,0.0728,0.1280,0.2440,0.4760"); + values ("0.6250,0.6084,0.5957,0.5635,0.5156,0.4121,0.2197",\ +"0.6300,0.6134,0.6007,0.5685,0.5206,0.4171,0.2247",\ +"0.6345,0.6179,0.6052,0.5729,0.5251,0.4216,0.2292",\ +"0.6436,0.6270,0.6143,0.5820,0.5342,0.4307,0.2383",\ +"0.6508,0.6342,0.6215,0.5893,0.5415,0.4379,0.2456",\ +"0.6809,0.6643,0.6516,0.6194,0.5715,0.4680,0.2756",\ +"0.7385,0.7219,0.7092,0.6770,0.6291,0.5256,0.3332"); + } + + fall_constraint("SIG2SRAM_constraint_template") { + index_1("0.0056,0.0232,0.0400,0.0728,0.1280,0.2440,0.4760"); + index_2("0.0056,0.0232,0.0400,0.0728,0.1280,0.2440,0.4760"); + values ("0.5791,0.5644,0.5508,0.5224,0.4726,0.3799,0.1953",\ +"0.5841,0.5694,0.5558,0.5274,0.4776,0.3849,0.2003",\ +"0.5886,0.5739,0.5602,0.5319,0.4821,0.3893,0.2048",\ +"0.5977,0.5830,0.5693,0.5410,0.4912,0.3984,0.2139",\ +"0.6049,0.5903,0.5766,0.5483,0.4985,0.4057,0.2211",\ +"0.6350,0.6204,0.6067,0.5784,0.5286,0.4358,0.2512",\ +"0.6926,0.6780,0.6643,0.6360,0.5862,0.4934,0.3088"); + } + } +} + pin(A_BIST_CLK) { + direction : input; + capacitance : 0.00380014; + max_transition : "0.476"; + clock : "true" ; + pin_func_type : active_rising ; + + timing () { + timing_type : "min_pulse_width"; + related_pin : "A_BIST_CLK"; + rise_constraint("CLKTRAN_constraint_template") { + index_1("0.0056,0.476"); + values("0.21,0.21"); + } + } + + related_power_pin : VDD; + related_ground_pin : VSS; + + internal_power() { + when : "!A_BIST_MEN & !A_BIST_WEN & !A_BIST_REN"; + rise_power("scalar"){ + values (0); + } + fall_power("scalar"){ + values (0); + } + } + internal_power() { + when : "!A_BIST_MEN & A_BIST_WEN & !A_BIST_REN"; + rise_power("scalar"){ + values (0.5389); + } + fall_power("scalar"){ + values (0); + } + } + internal_power() { + when : "A_BIST_MEN & A_BIST_WEN & !A_BIST_REN"; + rise_power("scalar"){ + values (42.3165); + } + fall_power("scalar"){ + values (0); + } + } + internal_power() { + when : "A_BIST_MEN & A_BIST_WEN & A_BIST_REN"; + rise_power("scalar"){ + values (47.6101); + } + fall_power("scalar"){ + values (0); + } + } + internal_power() { + when : "A_BIST_MEN & !A_BIST_WEN & A_BIST_REN"; + rise_power("scalar"){ + values (36.0099); + } + fall_power("scalar"){ + values (0); + } + } + internal_power() { + when : "!A_BIST_MEN & !A_BIST_WEN & A_BIST_REN"; + rise_power("scalar"){ + values (0.3230); + } + fall_power("scalar"){ + values (0); + } + } + internal_power() { + when : "!A_BIST_MEN & A_BIST_WEN & A_BIST_REN"; + rise_power("scalar"){ + values (1.2182); + } + fall_power("scalar"){ + values (0); + } + } + internal_power() { + when : "A_BIST_MEN & !A_BIST_WEN & !A_BIST_REN"; + rise_power("scalar"){ + values (0); + } + fall_power("scalar"){ + values (0); + } + } + } + bus(A_BIST_DIN) { + bus_type : D_31_0; + direction : input ; + capacitance : 0.00393889 ; + memory_write() { + address : A_BIST_ADDR ; + clocked_on : A_BIST_CLK; + } + + max_transition : "0.476" ; + pin(A_BIST_DIN[31:0]) { + related_power_pin : VDD; + related_ground_pin : VSS; + internal_power() { + when : "A_BIST_MEN"; + rise_power("scalar"){ + values (0.1133); + } + fall_power("scalar"){ + values (0.0512); + } + } + internal_power() { + when : "!A_BIST_MEN"; + rise_power("scalar"){ + values (0.1175); + } + fall_power("scalar"){ + values (0.0489); + } + } + } + timing() { + timing_type : setup_rising; + related_pin : "A_BIST_CLK"; + when : "(A_BIST_WEN & A_BIST_MEN)"; + sdf_cond : "A_BIST_W_ACCESS"; + + rise_constraint("SIG2SRAM_constraint_template") { + index_1("0.0056,0.0232,0.0400,0.0728,0.1280,0.2440,0.4760"); + index_2("0.0056,0.0232,0.0400,0.0728,0.1280,0.2440,0.4760"); + values ("-0.5146,-0.4990,-0.4853,-0.4531,-0.4062,-0.3017,-0.1103",\ +"-0.5196,-0.5040,-0.4903,-0.4581,-0.4112,-0.3067,-0.1153",\ +"-0.5241,-0.5085,-0.4948,-0.4626,-0.4157,-0.3112,-0.1198",\ +"-0.5332,-0.5176,-0.5039,-0.4717,-0.4248,-0.3203,-0.1289",\ +"-0.5405,-0.5248,-0.5112,-0.4789,-0.4321,-0.3276,-0.1362",\ +"-0.5706,-0.5549,-0.5413,-0.5090,-0.4621,-0.3577,-0.1663",\ +"-0.6281,-0.6125,-0.5988,-0.5666,-0.5197,-0.4153,-0.2238"); + } + + fall_constraint("SIG2SRAM_constraint_template") { + index_1("0.0056,0.0232,0.0400,0.0728,0.1280,0.2440,0.4760"); + index_2("0.0056,0.0232,0.0400,0.0728,0.1280,0.2440,0.4760"); + values ("-0.4765,-0.4619,-0.4482,-0.4199,-0.3691,-0.2715,-0.0888",\ +"-0.4815,-0.4669,-0.4532,-0.4249,-0.3741,-0.2765,-0.0938",\ +"-0.4860,-0.4714,-0.4577,-0.4294,-0.3786,-0.2809,-0.0983",\ +"-0.4951,-0.4805,-0.4668,-0.4385,-0.3877,-0.2900,-0.1074",\ +"-0.5024,-0.4877,-0.4741,-0.4457,-0.3950,-0.2973,-0.1147",\ +"-0.5325,-0.5178,-0.5041,-0.4758,-0.4250,-0.3274,-0.1448",\ +"-0.5901,-0.5754,-0.5617,-0.5334,-0.4826,-0.3850,-0.2024"); + } + } + + timing() { + timing_type : hold_rising; + related_pin : "A_BIST_CLK"; + when : "(A_BIST_WEN & A_BIST_MEN)"; + sdf_cond : "A_BIST_W_ACCESS"; + + rise_constraint("SIG2SRAM_constraint_template") { + index_1("0.0056,0.0232,0.0400,0.0728,0.1280,0.2440,0.4760"); + index_2("0.0056,0.0232,0.0400,0.0728,0.1280,0.2440,0.4760"); + values ("0.6250,0.6084,0.5957,0.5635,0.5156,0.4121,0.2197",\ +"0.6300,0.6134,0.6007,0.5685,0.5206,0.4171,0.2247",\ +"0.6345,0.6179,0.6052,0.5729,0.5251,0.4216,0.2292",\ +"0.6436,0.6270,0.6143,0.5820,0.5342,0.4307,0.2383",\ +"0.6508,0.6342,0.6215,0.5893,0.5415,0.4379,0.2456",\ +"0.6809,0.6643,0.6516,0.6194,0.5715,0.4680,0.2756",\ +"0.7385,0.7219,0.7092,0.6770,0.6291,0.5256,0.3332"); + } + + fall_constraint("SIG2SRAM_constraint_template") { + index_1("0.0056,0.0232,0.0400,0.0728,0.1280,0.2440,0.4760"); + index_2("0.0056,0.0232,0.0400,0.0728,0.1280,0.2440,0.4760"); + values ("0.5791,0.5644,0.5508,0.5224,0.4726,0.3799,0.1953",\ +"0.5841,0.5694,0.5558,0.5274,0.4776,0.3849,0.2003",\ +"0.5886,0.5739,0.5602,0.5319,0.4821,0.3893,0.2048",\ +"0.5977,0.5830,0.5693,0.5410,0.4912,0.3984,0.2139",\ +"0.6049,0.5903,0.5766,0.5483,0.4985,0.4057,0.2211",\ +"0.6350,0.6204,0.6067,0.5784,0.5286,0.4358,0.2512",\ +"0.6926,0.6780,0.6643,0.6360,0.5862,0.4934,0.3088"); + } + } + } + +bus(A_DOUT) { + + bus_type : D_31_0; + direction : output ; + capacitance : 0 ; + max_capacitance : 0.064 ; + memory_read() { + address : A_ADDR ; + } + pin(A_DOUT[31:0]) { + related_power_pin : VDD; + related_ground_pin : VSS; + internal_power() { + rise_power("scalar") { + values (0); + } + fall_power("scalar") { + values (0); + } + } + } + timing() { + related_pin : "A_CLK"; + timing_type : rising_edge ; + timing_sense : non_unate ; + + cell_rise(SIG2SRAM_delay_template) { + index_1("0.0056,0.0232,0.0400,0.0728,0.1280,0.2440,0.4760"); + index_2("0.0008,0.0014,0.0051,0.0100,0.0339,0.0640"); + values ("3.9022,3.9038,3.9114,3.9201,3.9525,3.9887",\ +"3.9073,3.9090,3.9166,3.9253,3.9577,3.9938",\ +"3.9105,3.9121,3.9198,3.9285,3.9609,3.9970",\ +"3.9230,3.9246,3.9322,3.9410,3.9733,4.0095",\ +"3.9288,3.9304,3.9381,3.9468,3.9792,4.0153",\ +"3.9598,3.9614,3.9690,3.9777,4.0101,4.0463",\ +"4.0155,4.0171,4.0247,4.0335,4.0658,4.1020"); + } + cell_fall(SIG2SRAM_delay_template) { + index_1("0.0056,0.0232,0.0400,0.0728,0.1280,0.2440,0.4760"); + index_2("0.0008,0.0014,0.0051,0.0100,0.0339,0.0640"); + values ("3.8419,3.8432,3.8493,3.8564,3.8829,3.9092",\ +"3.8471,3.8484,3.8545,3.8616,3.8881,3.9143",\ +"3.8503,3.8516,3.8577,3.8648,3.8913,3.9175",\ +"3.8627,3.8641,3.8701,3.8773,3.9038,3.9300",\ +"3.8686,3.8699,3.8760,3.8831,3.9096,3.9358",\ +"3.8995,3.9008,3.9069,3.9140,3.9406,3.9668",\ +"3.9552,3.9566,3.9626,3.9698,3.9963,4.0225"); + } + + rise_transition(SRAM_load_template) { + index_1("0.0008,0.0014,0.0051,0.0100,0.0339,0.0640"); + values ("0.0326,0.0341,0.0428,0.0518,0.0923,0.1492"); + } + fall_transition(SRAM_load_template) { + index_1("0.0008,0.0014,0.0051,0.0100,0.0339,0.0640"); + values ("0.0254,0.0265,0.0335,0.0402,0.0707,0.1039"); + } + } +} + pin(B_DLY) { + direction : input ; + capacitance : 0.00401111 ; + max_transition : "1" ; + related_power_pin : VDD; + related_ground_pin : VSS; + internal_power() { + rise_power("scalar") { + values (0); + } + fall_power("scalar") { + values (0); + } + } + } + +bus(B_ADDR) { + bus_type : A_8_0; + direction : input ; + capacitance : 0.0121077 ; + pin(B_ADDR[0]) { + capacitance : 0.00570093 ; + } + pin(B_ADDR[1]) { + capacitance : 0.00764555 ; + } + pin(B_ADDR[2]) { + capacitance : 0.0105375 ; + } + pin(B_ADDR[3]) { + capacitance : 0.0067894 ; + } + pin(B_ADDR[4]) { + capacitance : 0.00630967 ; + } + pin(B_ADDR[5]) { + capacitance : 0.0104132 ; + } + pin(B_ADDR[6]) { + capacitance : 0.0131402 ; + } + pin(B_ADDR[7]) { + capacitance : 0.0105203 ; + } + max_transition : "0.476" ; + pin(B_ADDR[8:0]) { + related_power_pin : VDD; + related_ground_pin : VSS; + internal_power() { + when : "B_MEN"; + rise_power("scalar"){ + values (0.0106); + } + fall_power("scalar"){ + values (0.0054); + } + } + internal_power() { + when : "!B_MEN"; + rise_power("scalar"){ + values (0.0143); + } + fall_power("scalar"){ + values (0.0003); + } + } + } + timing() { + timing_type : setup_rising; + related_pin : "B_CLK"; + when : "((B_WEN | B_REN)& B_MEN)" + sdf_cond : "B_RW_ACCESS" + + rise_constraint("SIG2SRAM_constraint_template") { + index_1("0.0056,0.0232,0.0400,0.0728,0.1280,0.2440,0.4760"); + index_2("0.0056,0.0232,0.0400,0.0728,0.1280,0.2440,0.4760"); + values ("-0.4168,-0.3973,-0.3855,-0.3543,-0.3074,-0.2020,-0.0027",\ +"-0.4324,-0.4129,-0.4012,-0.3699,-0.3191,-0.2176,-0.0184",\ +"-0.4441,-0.4285,-0.4129,-0.3816,-0.3309,-0.2293,-0.0301",\ +"-0.4793,-0.4598,-0.4441,-0.4129,-0.3660,-0.2645,-0.0652",\ +"-0.5223,-0.5066,-0.4910,-0.4598,-0.4129,-0.3074,-0.1121",\ +"-0.6199,-0.6082,-0.5926,-0.5613,-0.5145,-0.4129,-0.2137",\ +"-0.8191,-0.8074,-0.7840,-0.7566,-0.7098,-0.6082,-0.4051"); + } + + fall_constraint("SIG2SRAM_constraint_template") { + index_1("0.0056,0.0232,0.0400,0.0728,0.1280,0.2440,0.4760"); + index_2("0.0056,0.0232,0.0400,0.0728,0.1280,0.2440,0.4760"); + values ("-0.3309,-0.3113,-0.2996,-0.2684,-0.2176,-0.1238,0.0637",\ +"-0.3465,-0.3309,-0.3152,-0.2840,-0.2332,-0.1395,0.0480",\ +"-0.3582,-0.3426,-0.3270,-0.2996,-0.2488,-0.1512,0.0324",\ +"-0.3895,-0.3738,-0.3582,-0.3309,-0.2801,-0.1863,0.0051",\ +"-0.4363,-0.4207,-0.4051,-0.3777,-0.3230,-0.2293,-0.0379",\ +"-0.5379,-0.5223,-0.5066,-0.4793,-0.4285,-0.3309,-0.1434",\ +"-0.7332,-0.7176,-0.7020,-0.6746,-0.6238,-0.5262,-0.3387"); + } + } + + + timing() { + timing_type : hold_rising; + related_pin : "B_CLK"; + when : "((B_WEN | B_REN)& B_MEN)" + sdf_cond : "B_RW_ACCESS" + + rise_constraint("SIG2SRAM_constraint_template") { + index_1("0.0056,0.0232,0.0400,0.0728,0.1280,0.2440,0.4760"); + index_2("0.0056,0.0232,0.0400,0.0728,0.1280,0.2440,0.4760"); + values ("0.5246,0.5051,0.4895,0.4582,0.4113,0.3059,0.1066",\ +"0.5402,0.5207,0.5051,0.4777,0.4270,0.3215,0.1223",\ +"0.5520,0.5324,0.5168,0.4895,0.4387,0.3371,0.1340",\ +"0.5832,0.5676,0.5520,0.5207,0.4738,0.3684,0.1691",\ +"0.6301,0.6105,0.5949,0.5676,0.5168,0.4113,0.2160",\ +"0.7316,0.7121,0.7004,0.6691,0.6223,0.5168,0.3176",\ +"0.9270,0.9230,0.8957,0.8645,0.8137,0.7121,0.5168"); + } + + fall_constraint("SIG2SRAM_constraint_template") { + index_1("0.0056,0.0232,0.0400,0.0728,0.1280,0.2440,0.4760"); + index_2("0.0056,0.0232,0.0400,0.0728,0.1280,0.2440,0.4760"); + values ("0.4309,0.4152,0.4035,0.3684,0.3215,0.2277,0.0363",\ +"0.4465,0.4309,0.4152,0.3879,0.3371,0.2395,0.0559",\ +"0.4582,0.4426,0.4309,0.3996,0.3488,0.2551,0.0715",\ +"0.4934,0.4777,0.4621,0.4348,0.3840,0.2863,0.0988",\ +"0.5363,0.5207,0.5051,0.4777,0.4270,0.3332,0.1418",\ +"0.6379,0.6262,0.6105,0.5793,0.5324,0.4348,0.2434",\ +"0.8332,0.8215,0.8059,0.7707,0.7238,0.6301,0.4387"); + } + } +} +pin(B_WEN) { + direction : input ; + capacitance : 0.00324098 ; + max_transition : "0.476" ; + related_power_pin : VDD; + related_ground_pin : VSS; + internal_power() { + when : "B_MEN"; + rise_power("scalar"){ + values (0.0046); + } + fall_power("scalar"){ + values (0.0040); + } + } + internal_power() { + when : "!B_MEN"; + rise_power("scalar"){ + values (0.0044); + } + fall_power("scalar"){ + values (0.0043); + } + } + timing() { + timing_type : setup_rising; + related_pin : "B_CLK"; + when : "B_MEN" + sdf_cond : "B_MEN" + + rise_constraint("SIG2SRAM_constraint_template") { + index_1("0.0056,0.0232,0.0400,0.0728,0.1280,0.2440,0.4760"); + index_2("0.0056,0.0232,0.0400,0.0728,0.1280,0.2440,0.4760"); + values ("0.2043,0.2199,0.2316,0.2629,0.3059,0.4113,0.6066",\ +"0.1887,0.2043,0.2160,0.2473,0.2941,0.3957,0.5949",\ +"0.1691,0.1848,0.2004,0.2316,0.2785,0.3801,0.5754",\ +"0.1379,0.1574,0.1691,0.2004,0.2473,0.3527,0.5480",\ +"0.0910,0.1066,0.1223,0.1535,0.2004,0.2980,0.4973",\ +"-0.0105,0.0051,0.0207,0.0520,0.0949,0.2004,0.3957",\ +"-0.2059,-0.1902,-0.1746,-0.1473,-0.1004,0.0051,0.2004"); + } + + fall_constraint("SIG2SRAM_constraint_template") { + index_1("0.0056,0.0232,0.0400,0.0728,0.1280,0.2440,0.4760"); + index_2("0.0056,0.0232,0.0400,0.0728,0.1280,0.2440,0.4760"); + values ("0.2941,0.3098,0.3215,0.3488,0.4035,0.4973,0.6887",\ +"0.2785,0.2941,0.3059,0.3332,0.3840,0.4816,0.6691",\ +"0.2629,0.2785,0.2902,0.3176,0.3684,0.4660,0.6535",\ +"0.2316,0.2473,0.2590,0.2863,0.3410,0.4348,0.6262",\ +"0.1848,0.2004,0.2121,0.2395,0.2902,0.3879,0.5754",\ +"0.0832,0.0988,0.1105,0.1379,0.1809,0.2746,0.4699",\ +"-0.1121,-0.0965,-0.0848,-0.0535,-0.0066,0.0910,0.2824"); + } + } + + + timing() { + timing_type : hold_rising; + related_pin : "B_CLK"; + when : "B_MEN" + sdf_cond : "B_MEN" + + rise_constraint("SIG2SRAM_constraint_template") { + index_1("0.0056,0.0232,0.0400,0.0728,0.1280,0.2440,0.4760"); + index_2("0.0056,0.0232,0.0400,0.0728,0.1280,0.2440,0.4760"); + values ("0.2473,0.2316,0.2160,0.1887,0.1379,0.0363,-0.1629",\ +"0.2629,0.2473,0.2316,0.2043,0.1535,0.0520,-0.1473",\ +"0.2785,0.2590,0.2434,0.2160,0.1652,0.0676,-0.1355",\ +"0.3098,0.2941,0.2785,0.2473,0.1965,0.0910,-0.1043",\ +"0.3527,0.3371,0.3215,0.2941,0.2434,0.1418,-0.0574",\ +"0.4582,0.4426,0.4270,0.3957,0.3488,0.2434,0.0480",\ +"0.6535,0.6379,0.6184,0.5910,0.5402,0.4426,0.2434"); + } + + fall_constraint("SIG2SRAM_constraint_template") { + index_1("0.0056,0.0232,0.0400,0.0728,0.1280,0.2440,0.4760"); + index_2("0.0056,0.0232,0.0400,0.0728,0.1280,0.2440,0.4760"); + values ("0.2395,0.2238,0.2121,0.1809,0.1301,0.0324,-0.1551",\ +"0.2551,0.2395,0.2277,0.1965,0.1457,0.0480,-0.1395",\ +"0.2668,0.2551,0.2395,0.2082,0.1574,0.0637,-0.1277",\ +"0.3020,0.2863,0.2707,0.2395,0.1887,0.0910,-0.0965",\ +"0.3449,0.3293,0.3176,0.2863,0.2355,0.1379,-0.0496",\ +"0.4504,0.4348,0.4191,0.3879,0.3371,0.2395,0.0559",\ +"0.6457,0.6301,0.6145,0.5871,0.5324,0.4309,0.2512"); + } + } + } +pin(B_REN) { + direction : input ; + capacitance : 0.00381634 ; + max_transition : "0.476" ; + related_power_pin : VDD; + related_ground_pin : VSS; + internal_power() { + when : "B_MEN"; + rise_power("scalar"){ + values (0.0061); + } + fall_power("scalar"){ + values (0.0022); + } + } + internal_power() { + when : "!B_MEN"; + rise_power("scalar"){ + values (0.0063); + } + fall_power("scalar"){ + values (0.0027); + } + } + timing() { + timing_type : setup_rising; + related_pin : "B_CLK"; + when : "B_MEN" + sdf_cond : "B_MEN" + + rise_constraint("SIG2SRAM_constraint_template") { + index_1("0.0056,0.0232,0.0400,0.0728,0.1280,0.2440,0.4760"); + index_2("0.0056,0.0232,0.0400,0.0728,0.1280,0.2440,0.4760"); + values ("-0.0301,-0.0145,0.0012,0.0324,0.0793,0.1809,0.3762",\ +"-0.0457,-0.0301,-0.0145,0.0168,0.0637,0.1613,0.3605",\ +"-0.0574,-0.0418,-0.0262,0.0051,0.0520,0.1496,0.3449",\ +"-0.0926,-0.0730,-0.0574,-0.0262,0.0207,0.1184,0.3137",\ +"-0.1395,-0.1238,-0.1082,-0.0770,-0.0301,0.0715,0.2707",\ +"-0.2410,-0.2254,-0.2098,-0.1746,-0.1355,-0.0340,0.1652",\ +"-0.4402,-0.4207,-0.4051,-0.3738,-0.3270,-0.2293,-0.0340"); + } + + fall_constraint("SIG2SRAM_constraint_template") { + index_1("0.0056,0.0232,0.0400,0.0728,0.1280,0.2440,0.4760"); + index_2("0.0056,0.0232,0.0400,0.0728,0.1280,0.2440,0.4760"); + values ("0.0988,0.1145,0.1262,0.1535,0.2043,0.3020,0.4855",\ +"0.0832,0.0988,0.1105,0.1418,0.1848,0.2824,0.4738",\ +"0.0676,0.0832,0.0949,0.1262,0.1730,0.2668,0.4621",\ +"0.0402,0.0559,0.0676,0.0988,0.1457,0.2434,0.4191",\ +"-0.0105,0.0012,0.0168,0.0480,0.0988,0.1965,0.3840",\ +"-0.1160,-0.0965,-0.0848,-0.0535,-0.0066,0.0988,0.2824",\ +"-0.3113,-0.2957,-0.2801,-0.2527,-0.2059,-0.1043,0.0832"); + } + } + + + timing() { + timing_type : hold_rising; + related_pin : "B_CLK"; + when : "B_MEN" + sdf_cond : "B_MEN" + + rise_constraint("SIG2SRAM_constraint_template") { + index_1("0.0056,0.0232,0.0400,0.0728,0.1280,0.2440,0.4760"); + index_2("0.0056,0.0232,0.0400,0.0728,0.1280,0.2440,0.4760"); + values ("0.2707,0.2551,0.2395,0.2121,0.1613,0.0598,-0.1395",\ +"0.2863,0.2707,0.2551,0.2238,0.1730,0.0715,-0.1238",\ +"0.2980,0.2824,0.2668,0.2395,0.1887,0.0871,-0.1121",\ +"0.3332,0.3176,0.3020,0.2707,0.2199,0.1184,-0.0809",\ +"0.3762,0.3605,0.3449,0.3176,0.2668,0.1613,-0.0340",\ +"0.4816,0.4621,0.4504,0.4191,0.3723,0.2629,0.0715",\ +"0.6770,0.6613,0.6418,0.6184,0.5637,0.4699,0.2629"); + } + + fall_constraint("SIG2SRAM_constraint_template") { + index_1("0.0056,0.0232,0.0400,0.0728,0.1280,0.2440,0.4760"); + index_2("0.0056,0.0232,0.0400,0.0728,0.1280,0.2440,0.4760"); + values ("0.2590,0.2434,0.2316,0.2004,0.1457,0.0520,-0.1355",\ +"0.2746,0.2590,0.2434,0.2160,0.1613,0.0676,-0.1199",\ +"0.2863,0.2707,0.2590,0.2277,0.1730,0.0832,-0.1082",\ +"0.3215,0.3059,0.2902,0.2590,0.2082,0.1105,-0.0770",\ +"0.3645,0.3488,0.3332,0.3059,0.2551,0.1535,-0.0340",\ +"0.4699,0.4543,0.4387,0.4074,0.3605,0.2551,0.0715",\ +"0.6652,0.6496,0.6340,0.6027,0.5520,0.4621,0.2707"); + } + } + } +pin(B_MEN) { + direction : input ; + capacitance : 0.00309605 ; + max_transition : "0.476" ; + related_power_pin : VDD; + related_ground_pin : VSS; + internal_power() { + rise_power("scalar"){ + values (0.0874); + } + fall_power("scalar"){ + values (0.0053); + } + } + timing() { + timing_type : setup_rising; + related_pin : "B_CLK"; + + rise_constraint("SIG2SRAM_constraint_template") { + index_1("0.0056,0.0232,0.0400,0.0728,0.1280,0.2440,0.4760"); + index_2("0.0056,0.0232,0.0400,0.0728,0.1280,0.2440,0.4760"); + values ("0.2043,0.2199,0.2316,0.2668,0.3098,0.4152,0.6066",\ +"0.1887,0.2043,0.2199,0.2512,0.2941,0.3996,0.5949",\ +"0.1730,0.1887,0.2043,0.2355,0.2824,0.3840,0.5793",\ +"0.1418,0.1574,0.1730,0.2043,0.2512,0.3566,0.5480",\ +"0.0949,0.1105,0.1262,0.1574,0.2043,0.3020,0.5051",\ +"-0.0066,0.0090,0.0246,0.0520,0.0988,0.2043,0.3996",\ +"-0.2020,-0.1863,-0.1746,-0.1434,-0.0965,0.0090,0.2082"); + } + + fall_constraint("SIG2SRAM_constraint_template") { + index_1("0.0056,0.0232,0.0400,0.0728,0.1280,0.2440,0.4760"); + index_2("0.0056,0.0232,0.0400,0.0728,0.1280,0.2440,0.4760"); + values ("0.2980,0.3137,0.3254,0.3527,0.4035,0.5012,0.6887",\ +"0.2824,0.2980,0.3098,0.3371,0.3879,0.4855,0.6730",\ +"0.2668,0.2824,0.2941,0.3215,0.3723,0.4699,0.6574",\ +"0.2355,0.2473,0.2629,0.2902,0.3410,0.4387,0.6262",\ +"0.1887,0.2004,0.2160,0.2395,0.2941,0.3918,0.5793",\ +"0.0871,0.1027,0.1145,0.1418,0.1848,0.2746,0.4816",\ +"-0.1082,-0.0965,-0.0809,-0.0496,-0.0027,0.0949,0.2863"); + } + } + + + timing() { + timing_type : hold_rising; + related_pin : "B_CLK"; + + rise_constraint("SIG2SRAM_constraint_template") { + index_1("0.0056,0.0232,0.0400,0.0728,0.1280,0.2440,0.4760"); + index_2("0.0056,0.0232,0.0400,0.0728,0.1280,0.2440,0.4760"); + values ("0.2512,0.2355,0.2199,0.1926,0.1418,0.0402,-0.1590",\ +"0.2668,0.2512,0.2355,0.2082,0.1574,0.0559,-0.1434",\ +"0.2824,0.2629,0.2512,0.2199,0.1691,0.0715,-0.1316",\ +"0.3137,0.2980,0.2824,0.2512,0.2004,0.0988,-0.0965",\ +"0.3566,0.3410,0.3254,0.2980,0.2473,0.1418,-0.0535",\ +"0.4621,0.4426,0.4309,0.3996,0.3527,0.2473,0.0520",\ +"0.6574,0.6418,0.6262,0.5949,0.5441,0.4465,0.2473"); + } + + fall_constraint("SIG2SRAM_constraint_template") { + index_1("0.0056,0.0232,0.0400,0.0728,0.1280,0.2440,0.4760"); + index_2("0.0056,0.0232,0.0400,0.0728,0.1280,0.2440,0.4760"); + values ("0.2395,0.2238,0.2121,0.1809,0.1301,0.0324,-0.1551",\ +"0.2551,0.2434,0.2277,0.1965,0.1457,0.0480,-0.1395",\ +"0.2707,0.2551,0.2395,0.2082,0.1574,0.0637,-0.1277",\ +"0.3020,0.2863,0.2707,0.2434,0.1926,0.0910,-0.0965",\ +"0.3449,0.3332,0.3176,0.2863,0.2355,0.1379,-0.0496",\ +"0.4504,0.4348,0.4230,0.3918,0.3410,0.2434,0.0559",\ +"0.6457,0.6301,0.6145,0.5910,0.5324,0.4387,0.2512"); + } + } + } +bus(B_BM) { + bus_type : D_31_0; + direction : input ; + capacitance : 0.00312518 ; + max_transition : "0.476" ; + pin(B_BM[31:0]) { + related_power_pin : VDD; + related_ground_pin : VSS; + internal_power() { + when : "B_MEN"; + rise_power("scalar"){ + values (0.1133); + } + fall_power("scalar"){ + values (0.0512); + } + } + internal_power() { + when : "!B_MEN"; + rise_power("scalar"){ + values (0.1175); + } + fall_power("scalar"){ + values (0.0489); + } + } + } + timing() { + timing_type : setup_rising; + related_pin : "B_CLK"; + when : "(B_WEN & B_MEN)" + sdf_cond : "B_RW_ACCESS" + + rise_constraint("SIG2SRAM_constraint_template") { + index_1("0.0056,0.0232,0.0400,0.0728,0.1280,0.2440,0.4760"); + index_2("0.0056,0.0232,0.0400,0.0728,0.1280,0.2440,0.4760"); + values ("-0.5146,-0.4990,-0.4853,-0.4531,-0.4062,-0.3017,-0.1103",\ +"-0.5196,-0.5040,-0.4903,-0.4581,-0.4112,-0.3067,-0.1153",\ +"-0.5241,-0.5085,-0.4948,-0.4626,-0.4157,-0.3112,-0.1198",\ +"-0.5332,-0.5176,-0.5039,-0.4717,-0.4248,-0.3203,-0.1289",\ +"-0.5405,-0.5248,-0.5112,-0.4789,-0.4321,-0.3276,-0.1362",\ +"-0.5706,-0.5549,-0.5413,-0.5090,-0.4621,-0.3577,-0.1663",\ +"-0.6281,-0.6125,-0.5988,-0.5666,-0.5197,-0.4153,-0.2238"); + } + + fall_constraint("SIG2SRAM_constraint_template") { + index_1("0.0056,0.0232,0.0400,0.0728,0.1280,0.2440,0.4760"); + index_2("0.0056,0.0232,0.0400,0.0728,0.1280,0.2440,0.4760"); + values ("-0.4765,-0.4619,-0.4482,-0.4199,-0.3691,-0.2715,-0.0888",\ +"-0.4815,-0.4669,-0.4532,-0.4249,-0.3741,-0.2765,-0.0938",\ +"-0.4860,-0.4714,-0.4577,-0.4294,-0.3786,-0.2809,-0.0983",\ +"-0.4951,-0.4805,-0.4668,-0.4385,-0.3877,-0.2900,-0.1074",\ +"-0.5024,-0.4877,-0.4741,-0.4457,-0.3950,-0.2973,-0.1147",\ +"-0.5325,-0.5178,-0.5041,-0.4758,-0.4250,-0.3274,-0.1448",\ +"-0.5901,-0.5754,-0.5617,-0.5334,-0.4826,-0.3850,-0.2024"); + } + } + + + timing() { + timing_type : hold_rising; + related_pin : "B_CLK"; + when : "(B_WEN & B_MEN)" + sdf_cond : "B_RW_ACCESS" + + rise_constraint("SIG2SRAM_constraint_template") { + index_1("0.0056,0.0232,0.0400,0.0728,0.1280,0.2440,0.4760"); + index_2("0.0056,0.0232,0.0400,0.0728,0.1280,0.2440,0.4760"); + values ("0.6250,0.6084,0.5957,0.5635,0.5156,0.4121,0.2197",\ +"0.6300,0.6134,0.6007,0.5685,0.5206,0.4171,0.2247",\ +"0.6345,0.6179,0.6052,0.5729,0.5251,0.4216,0.2292",\ +"0.6436,0.6270,0.6143,0.5820,0.5342,0.4307,0.2383",\ +"0.6508,0.6342,0.6215,0.5893,0.5415,0.4379,0.2456",\ +"0.6809,0.6643,0.6516,0.6194,0.5715,0.4680,0.2756",\ +"0.7385,0.7219,0.7092,0.6770,0.6291,0.5256,0.3332"); + } + + fall_constraint("SIG2SRAM_constraint_template") { + index_1("0.0056,0.0232,0.0400,0.0728,0.1280,0.2440,0.4760"); + index_2("0.0056,0.0232,0.0400,0.0728,0.1280,0.2440,0.4760"); + values ("0.5791,0.5644,0.5508,0.5224,0.4726,0.3799,0.1953",\ +"0.5841,0.5694,0.5558,0.5274,0.4776,0.3849,0.2003",\ +"0.5886,0.5739,0.5602,0.5319,0.4821,0.3893,0.2048",\ +"0.5977,0.5830,0.5693,0.5410,0.4912,0.3984,0.2139",\ +"0.6049,0.5903,0.5766,0.5483,0.4985,0.4057,0.2211",\ +"0.6350,0.6204,0.6067,0.5784,0.5286,0.4358,0.2512",\ +"0.6926,0.6780,0.6643,0.6360,0.5862,0.4934,0.3088"); + } + } +} + pin(B_CLK) { + direction : input; + capacitance : 0.00380014; + max_transition : "0.476"; + clock : "true" ; + pin_func_type : active_rising ; + + timing () { + timing_type : "min_pulse_width"; + related_pin : "B_CLK"; + rise_constraint("CLKTRAN_constraint_template") { + index_1("0.0056,0.476"); + values("0.21,0.21"); + } + } + + related_power_pin : VDD; + related_ground_pin : VSS; + + internal_power() { + when : "!B_MEN & !B_WEN & !B_REN"; + rise_power("scalar"){ + values (0); + } + fall_power("scalar"){ + values (0); + } + } + internal_power() { + when : "!B_MEN & B_WEN & !B_REN"; + rise_power("scalar"){ + values (0.5389); + } + fall_power("scalar"){ + values (0); + } + } + internal_power() { + when : "B_MEN & B_WEN & !B_REN"; + rise_power("scalar"){ + values (42.3165); + } + fall_power("scalar"){ + values (0); + } + } + internal_power() { + when : "B_MEN & B_WEN & B_REN"; + rise_power("scalar"){ + values (47.6101); + } + fall_power("scalar"){ + values (0); + } + } + internal_power() { + when : "B_MEN & !B_WEN & B_REN"; + rise_power("scalar"){ + values (36.0099); + } + fall_power("scalar"){ + values (0); + } + } + internal_power() { + when : "!B_MEN & !B_WEN & B_REN"; + rise_power("scalar"){ + values (0.3230); + } + fall_power("scalar"){ + values (0); + } + } + internal_power() { + when : "!B_MEN & B_WEN & B_REN"; + rise_power("scalar"){ + values (1.2182); + } + fall_power("scalar"){ + values (0); + } + } + internal_power() { + when : "B_MEN & !B_WEN & !B_REN"; + rise_power("scalar"){ + values (0); + } + fall_power("scalar"){ + values (0); + } + } + } + bus(B_DIN) { + bus_type : D_31_0; + direction : input ; + capacitance : 0.00461776 ; + memory_write() { + address : B_ADDR ; + clocked_on : B_CLK; + } + + max_transition : "0.476" ; + pin(B_DIN[31:0]) { + related_power_pin : VDD; + related_ground_pin : VSS; + internal_power() { + when : "B_MEN"; + rise_power("scalar"){ + values (0.1133); + } + fall_power("scalar"){ + values (0.0512); + } + } + internal_power() { + when : "!B_MEN"; + rise_power("scalar"){ + values (0.1175); + } + fall_power("scalar"){ + values (0.0489); + } + } + } + timing() { + timing_type : setup_rising; + related_pin : "B_CLK"; + when : "(B_WEN & B_MEN)"; + sdf_cond : "B_W_ACCESS"; + + rise_constraint("SIG2SRAM_constraint_template") { + index_1("0.0056,0.0232,0.0400,0.0728,0.1280,0.2440,0.4760"); + index_2("0.0056,0.0232,0.0400,0.0728,0.1280,0.2440,0.4760"); + values ("-0.5146,-0.4990,-0.4853,-0.4531,-0.4062,-0.3017,-0.1103",\ +"-0.5196,-0.5040,-0.4903,-0.4581,-0.4112,-0.3067,-0.1153",\ +"-0.5241,-0.5085,-0.4948,-0.4626,-0.4157,-0.3112,-0.1198",\ +"-0.5332,-0.5176,-0.5039,-0.4717,-0.4248,-0.3203,-0.1289",\ +"-0.5405,-0.5248,-0.5112,-0.4789,-0.4321,-0.3276,-0.1362",\ +"-0.5706,-0.5549,-0.5413,-0.5090,-0.4621,-0.3577,-0.1663",\ +"-0.6281,-0.6125,-0.5988,-0.5666,-0.5197,-0.4153,-0.2238"); + } + + fall_constraint("SIG2SRAM_constraint_template") { + index_1("0.0056,0.0232,0.0400,0.0728,0.1280,0.2440,0.4760"); + index_2("0.0056,0.0232,0.0400,0.0728,0.1280,0.2440,0.4760"); + values ("-0.4765,-0.4619,-0.4482,-0.4199,-0.3691,-0.2715,-0.0888",\ +"-0.4815,-0.4669,-0.4532,-0.4249,-0.3741,-0.2765,-0.0938",\ +"-0.4860,-0.4714,-0.4577,-0.4294,-0.3786,-0.2809,-0.0983",\ +"-0.4951,-0.4805,-0.4668,-0.4385,-0.3877,-0.2900,-0.1074",\ +"-0.5024,-0.4877,-0.4741,-0.4457,-0.3950,-0.2973,-0.1147",\ +"-0.5325,-0.5178,-0.5041,-0.4758,-0.4250,-0.3274,-0.1448",\ +"-0.5901,-0.5754,-0.5617,-0.5334,-0.4826,-0.3850,-0.2024"); + } + } + + timing() { + timing_type : hold_rising; + related_pin : "B_CLK"; + when : "(B_WEN & B_MEN)"; + sdf_cond : "B_W_ACCESS"; + + rise_constraint("SIG2SRAM_constraint_template") { + index_1("0.0056,0.0232,0.0400,0.0728,0.1280,0.2440,0.4760"); + index_2("0.0056,0.0232,0.0400,0.0728,0.1280,0.2440,0.4760"); + values ("0.6250,0.6084,0.5957,0.5635,0.5156,0.4121,0.2197",\ +"0.6300,0.6134,0.6007,0.5685,0.5206,0.4171,0.2247",\ +"0.6345,0.6179,0.6052,0.5729,0.5251,0.4216,0.2292",\ +"0.6436,0.6270,0.6143,0.5820,0.5342,0.4307,0.2383",\ +"0.6508,0.6342,0.6215,0.5893,0.5415,0.4379,0.2456",\ +"0.6809,0.6643,0.6516,0.6194,0.5715,0.4680,0.2756",\ +"0.7385,0.7219,0.7092,0.6770,0.6291,0.5256,0.3332"); + } + + fall_constraint("SIG2SRAM_constraint_template") { + index_1("0.0056,0.0232,0.0400,0.0728,0.1280,0.2440,0.4760"); + index_2("0.0056,0.0232,0.0400,0.0728,0.1280,0.2440,0.4760"); + values ("0.5791,0.5644,0.5508,0.5224,0.4726,0.3799,0.1953",\ +"0.5841,0.5694,0.5558,0.5274,0.4776,0.3849,0.2003",\ +"0.5886,0.5739,0.5602,0.5319,0.4821,0.3893,0.2048",\ +"0.5977,0.5830,0.5693,0.5410,0.4912,0.3984,0.2139",\ +"0.6049,0.5903,0.5766,0.5483,0.4985,0.4057,0.2211",\ +"0.6350,0.6204,0.6067,0.5784,0.5286,0.4358,0.2512",\ +"0.6926,0.6780,0.6643,0.6360,0.5862,0.4934,0.3088"); + } + } + } + + pin(B_BIST_EN) { + direction : input ; + capacitance : 0.00401111 ; + max_transition : "1" ; + related_power_pin : VDD; + related_ground_pin : VSS; + internal_power() { + rise_power("scalar") { + values (0); + } + fall_power("scalar") { + values (0); + } + } + } + +bus(B_BIST_ADDR) { + bus_type : A_8_0; + direction : input ; + capacitance : 0.0121077 ; + pin(B_BIST_ADDR[0]) { + capacitance : 0.00570093 ; + } + pin(B_BIST_ADDR[1]) { + capacitance : 0.00764555 ; + } + pin(B_BIST_ADDR[2]) { + capacitance : 0.0105375 ; + } + pin(B_BIST_ADDR[3]) { + capacitance : 0.0067894 ; + } + pin(B_BIST_ADDR[4]) { + capacitance : 0.00630967 ; + } + pin(B_BIST_ADDR[5]) { + capacitance : 0.0104132 ; + } + pin(B_BIST_ADDR[6]) { + capacitance : 0.0131402 ; + } + pin(B_BIST_ADDR[7]) { + capacitance : 0.0105203 ; + } + max_transition : "0.476" ; + pin(B_BIST_ADDR[8:0]) { + related_power_pin : VDD; + related_ground_pin : VSS; + internal_power() { + when : "B_BIST_MEN"; + rise_power("scalar"){ + values (0.0106); + } + fall_power("scalar"){ + values (0.0054); + } + } + internal_power() { + when : "!B_BIST_MEN"; + rise_power("scalar"){ + values (0.0143); + } + fall_power("scalar"){ + values (0.0003); + } + } + } + timing() { + timing_type : setup_rising; + related_pin : "B_BIST_CLK"; + when : "((B_BIST_WEN | B_BIST_REN)& B_BIST_MEN)" + sdf_cond : "B_BIST_RW_ACCESS" + + rise_constraint("SIG2SRAM_constraint_template") { + index_1("0.0056,0.0232,0.0400,0.0728,0.1280,0.2440,0.4760"); + index_2("0.0056,0.0232,0.0400,0.0728,0.1280,0.2440,0.4760"); + values ("-0.4168,-0.3973,-0.3855,-0.3543,-0.3074,-0.2020,-0.0027",\ +"-0.4324,-0.4129,-0.4012,-0.3699,-0.3191,-0.2176,-0.0184",\ +"-0.4441,-0.4285,-0.4129,-0.3816,-0.3309,-0.2293,-0.0301",\ +"-0.4793,-0.4598,-0.4441,-0.4129,-0.3660,-0.2645,-0.0652",\ +"-0.5223,-0.5066,-0.4910,-0.4598,-0.4129,-0.3074,-0.1121",\ +"-0.6199,-0.6082,-0.5926,-0.5613,-0.5145,-0.4129,-0.2137",\ +"-0.8191,-0.8074,-0.7840,-0.7566,-0.7098,-0.6082,-0.4051"); + } + + fall_constraint("SIG2SRAM_constraint_template") { + index_1("0.0056,0.0232,0.0400,0.0728,0.1280,0.2440,0.4760"); + index_2("0.0056,0.0232,0.0400,0.0728,0.1280,0.2440,0.4760"); + values ("-0.3309,-0.3113,-0.2996,-0.2684,-0.2176,-0.1238,0.0637",\ +"-0.3465,-0.3309,-0.3152,-0.2840,-0.2332,-0.1395,0.0480",\ +"-0.3582,-0.3426,-0.3270,-0.2996,-0.2488,-0.1512,0.0324",\ +"-0.3895,-0.3738,-0.3582,-0.3309,-0.2801,-0.1863,0.0051",\ +"-0.4363,-0.4207,-0.4051,-0.3777,-0.3230,-0.2293,-0.0379",\ +"-0.5379,-0.5223,-0.5066,-0.4793,-0.4285,-0.3309,-0.1434",\ +"-0.7332,-0.7176,-0.7020,-0.6746,-0.6238,-0.5262,-0.3387"); + } + } + + + timing() { + timing_type : hold_rising; + related_pin : "B_BIST_CLK"; + when : "((B_BIST_WEN | B_BIST_REN)& B_BIST_MEN)" + sdf_cond : "B_BIST_RW_ACCESS" + + rise_constraint("SIG2SRAM_constraint_template") { + index_1("0.0056,0.0232,0.0400,0.0728,0.1280,0.2440,0.4760"); + index_2("0.0056,0.0232,0.0400,0.0728,0.1280,0.2440,0.4760"); + values ("0.5246,0.5051,0.4895,0.4582,0.4113,0.3059,0.1066",\ +"0.5402,0.5207,0.5051,0.4777,0.4270,0.3215,0.1223",\ +"0.5520,0.5324,0.5168,0.4895,0.4387,0.3371,0.1340",\ +"0.5832,0.5676,0.5520,0.5207,0.4738,0.3684,0.1691",\ +"0.6301,0.6105,0.5949,0.5676,0.5168,0.4113,0.2160",\ +"0.7316,0.7121,0.7004,0.6691,0.6223,0.5168,0.3176",\ +"0.9270,0.9230,0.8957,0.8645,0.8137,0.7121,0.5168"); + } + + fall_constraint("SIG2SRAM_constraint_template") { + index_1("0.0056,0.0232,0.0400,0.0728,0.1280,0.2440,0.4760"); + index_2("0.0056,0.0232,0.0400,0.0728,0.1280,0.2440,0.4760"); + values ("0.4309,0.4152,0.4035,0.3684,0.3215,0.2277,0.0363",\ +"0.4465,0.4309,0.4152,0.3879,0.3371,0.2395,0.0559",\ +"0.4582,0.4426,0.4309,0.3996,0.3488,0.2551,0.0715",\ +"0.4934,0.4777,0.4621,0.4348,0.3840,0.2863,0.0988",\ +"0.5363,0.5207,0.5051,0.4777,0.4270,0.3332,0.1418",\ +"0.6379,0.6262,0.6105,0.5793,0.5324,0.4348,0.2434",\ +"0.8332,0.8215,0.8059,0.7707,0.7238,0.6301,0.4387"); + } + } +} +pin(B_BIST_WEN) { + direction : input ; + capacitance : 0.00324098 ; + max_transition : "0.476" ; + related_power_pin : VDD; + related_ground_pin : VSS; + internal_power() { + when : "B_BIST_MEN"; + rise_power("scalar"){ + values (0.0046); + } + fall_power("scalar"){ + values (0.0040); + } + } + internal_power() { + when : "!B_BIST_MEN"; + rise_power("scalar"){ + values (0.0044); + } + fall_power("scalar"){ + values (0.0043); + } + } + timing() { + timing_type : setup_rising; + related_pin : "B_BIST_CLK"; + when : "B_BIST_MEN" + sdf_cond : "B_BIST_MEN" + + rise_constraint("SIG2SRAM_constraint_template") { + index_1("0.0056,0.0232,0.0400,0.0728,0.1280,0.2440,0.4760"); + index_2("0.0056,0.0232,0.0400,0.0728,0.1280,0.2440,0.4760"); + values ("0.2043,0.2199,0.2316,0.2629,0.3059,0.4113,0.6066",\ +"0.1887,0.2043,0.2160,0.2473,0.2941,0.3957,0.5949",\ +"0.1691,0.1848,0.2004,0.2316,0.2785,0.3801,0.5754",\ +"0.1379,0.1574,0.1691,0.2004,0.2473,0.3527,0.5480",\ +"0.0910,0.1066,0.1223,0.1535,0.2004,0.2980,0.4973",\ +"-0.0105,0.0051,0.0207,0.0520,0.0949,0.2004,0.3957",\ +"-0.2059,-0.1902,-0.1746,-0.1473,-0.1004,0.0051,0.2004"); + } + + fall_constraint("SIG2SRAM_constraint_template") { + index_1("0.0056,0.0232,0.0400,0.0728,0.1280,0.2440,0.4760"); + index_2("0.0056,0.0232,0.0400,0.0728,0.1280,0.2440,0.4760"); + values ("0.2941,0.3098,0.3215,0.3488,0.4035,0.4973,0.6887",\ +"0.2785,0.2941,0.3059,0.3332,0.3840,0.4816,0.6691",\ +"0.2629,0.2785,0.2902,0.3176,0.3684,0.4660,0.6535",\ +"0.2316,0.2473,0.2590,0.2863,0.3410,0.4348,0.6262",\ +"0.1848,0.2004,0.2121,0.2395,0.2902,0.3879,0.5754",\ +"0.0832,0.0988,0.1105,0.1379,0.1809,0.2746,0.4699",\ +"-0.1121,-0.0965,-0.0848,-0.0535,-0.0066,0.0910,0.2824"); + } + } + + + timing() { + timing_type : hold_rising; + related_pin : "B_BIST_CLK"; + when : "B_BIST_MEN" + sdf_cond : "B_BIST_MEN" + + rise_constraint("SIG2SRAM_constraint_template") { + index_1("0.0056,0.0232,0.0400,0.0728,0.1280,0.2440,0.4760"); + index_2("0.0056,0.0232,0.0400,0.0728,0.1280,0.2440,0.4760"); + values ("0.2473,0.2316,0.2160,0.1887,0.1379,0.0363,-0.1629",\ +"0.2629,0.2473,0.2316,0.2043,0.1535,0.0520,-0.1473",\ +"0.2785,0.2590,0.2434,0.2160,0.1652,0.0676,-0.1355",\ +"0.3098,0.2941,0.2785,0.2473,0.1965,0.0910,-0.1043",\ +"0.3527,0.3371,0.3215,0.2941,0.2434,0.1418,-0.0574",\ +"0.4582,0.4426,0.4270,0.3957,0.3488,0.2434,0.0480",\ +"0.6535,0.6379,0.6184,0.5910,0.5402,0.4426,0.2434"); + } + + fall_constraint("SIG2SRAM_constraint_template") { + index_1("0.0056,0.0232,0.0400,0.0728,0.1280,0.2440,0.4760"); + index_2("0.0056,0.0232,0.0400,0.0728,0.1280,0.2440,0.4760"); + values ("0.2395,0.2238,0.2121,0.1809,0.1301,0.0324,-0.1551",\ +"0.2551,0.2395,0.2277,0.1965,0.1457,0.0480,-0.1395",\ +"0.2668,0.2551,0.2395,0.2082,0.1574,0.0637,-0.1277",\ +"0.3020,0.2863,0.2707,0.2395,0.1887,0.0910,-0.0965",\ +"0.3449,0.3293,0.3176,0.2863,0.2355,0.1379,-0.0496",\ +"0.4504,0.4348,0.4191,0.3879,0.3371,0.2395,0.0559",\ +"0.6457,0.6301,0.6145,0.5871,0.5324,0.4309,0.2512"); + } + } + } +pin(B_BIST_REN) { + direction : input ; + capacitance : 0.00381634 ; + max_transition : "0.476" ; + related_power_pin : VDD; + related_ground_pin : VSS; + internal_power() { + when : "B_BIST_MEN"; + rise_power("scalar"){ + values (0.0061); + } + fall_power("scalar"){ + values (0.0022); + } + } + internal_power() { + when : "!B_BIST_MEN"; + rise_power("scalar"){ + values (0.0063); + } + fall_power("scalar"){ + values (0.0027); + } + } + timing() { + timing_type : setup_rising; + related_pin : "B_BIST_CLK"; + when : "B_BIST_MEN" + sdf_cond : "B_BIST_MEN" + + rise_constraint("SIG2SRAM_constraint_template") { + index_1("0.0056,0.0232,0.0400,0.0728,0.1280,0.2440,0.4760"); + index_2("0.0056,0.0232,0.0400,0.0728,0.1280,0.2440,0.4760"); + values ("-0.0301,-0.0145,0.0012,0.0324,0.0793,0.1809,0.3762",\ +"-0.0457,-0.0301,-0.0145,0.0168,0.0637,0.1613,0.3605",\ +"-0.0574,-0.0418,-0.0262,0.0051,0.0520,0.1496,0.3449",\ +"-0.0926,-0.0730,-0.0574,-0.0262,0.0207,0.1184,0.3137",\ +"-0.1395,-0.1238,-0.1082,-0.0770,-0.0301,0.0715,0.2707",\ +"-0.2410,-0.2254,-0.2098,-0.1746,-0.1355,-0.0340,0.1652",\ +"-0.4402,-0.4207,-0.4051,-0.3738,-0.3270,-0.2293,-0.0340"); + } + + fall_constraint("SIG2SRAM_constraint_template") { + index_1("0.0056,0.0232,0.0400,0.0728,0.1280,0.2440,0.4760"); + index_2("0.0056,0.0232,0.0400,0.0728,0.1280,0.2440,0.4760"); + values ("0.0988,0.1145,0.1262,0.1535,0.2043,0.3020,0.4855",\ +"0.0832,0.0988,0.1105,0.1418,0.1848,0.2824,0.4738",\ +"0.0676,0.0832,0.0949,0.1262,0.1730,0.2668,0.4621",\ +"0.0402,0.0559,0.0676,0.0988,0.1457,0.2434,0.4191",\ +"-0.0105,0.0012,0.0168,0.0480,0.0988,0.1965,0.3840",\ +"-0.1160,-0.0965,-0.0848,-0.0535,-0.0066,0.0988,0.2824",\ +"-0.3113,-0.2957,-0.2801,-0.2527,-0.2059,-0.1043,0.0832"); + } + } + + + timing() { + timing_type : hold_rising; + related_pin : "B_BIST_CLK"; + when : "B_BIST_MEN" + sdf_cond : "B_BIST_MEN" + + rise_constraint("SIG2SRAM_constraint_template") { + index_1("0.0056,0.0232,0.0400,0.0728,0.1280,0.2440,0.4760"); + index_2("0.0056,0.0232,0.0400,0.0728,0.1280,0.2440,0.4760"); + values ("0.2707,0.2551,0.2395,0.2121,0.1613,0.0598,-0.1395",\ +"0.2863,0.2707,0.2551,0.2238,0.1730,0.0715,-0.1238",\ +"0.2980,0.2824,0.2668,0.2395,0.1887,0.0871,-0.1121",\ +"0.3332,0.3176,0.3020,0.2707,0.2199,0.1184,-0.0809",\ +"0.3762,0.3605,0.3449,0.3176,0.2668,0.1613,-0.0340",\ +"0.4816,0.4621,0.4504,0.4191,0.3723,0.2629,0.0715",\ +"0.6770,0.6613,0.6418,0.6184,0.5637,0.4699,0.2629"); + } + + fall_constraint("SIG2SRAM_constraint_template") { + index_1("0.0056,0.0232,0.0400,0.0728,0.1280,0.2440,0.4760"); + index_2("0.0056,0.0232,0.0400,0.0728,0.1280,0.2440,0.4760"); + values ("0.2590,0.2434,0.2316,0.2004,0.1457,0.0520,-0.1355",\ +"0.2746,0.2590,0.2434,0.2160,0.1613,0.0676,-0.1199",\ +"0.2863,0.2707,0.2590,0.2277,0.1730,0.0832,-0.1082",\ +"0.3215,0.3059,0.2902,0.2590,0.2082,0.1105,-0.0770",\ +"0.3645,0.3488,0.3332,0.3059,0.2551,0.1535,-0.0340",\ +"0.4699,0.4543,0.4387,0.4074,0.3605,0.2551,0.0715",\ +"0.6652,0.6496,0.6340,0.6027,0.5520,0.4621,0.2707"); + } + } + } +pin(B_BIST_MEN) { + direction : input ; + capacitance : 0.00309605 ; + max_transition : "0.476" ; + related_power_pin : VDD; + related_ground_pin : VSS; + internal_power() { + rise_power("scalar"){ + values (0.0874); + } + fall_power("scalar"){ + values (0.0053); + } + } + timing() { + timing_type : setup_rising; + related_pin : "B_BIST_CLK"; + + rise_constraint("SIG2SRAM_constraint_template") { + index_1("0.0056,0.0232,0.0400,0.0728,0.1280,0.2440,0.4760"); + index_2("0.0056,0.0232,0.0400,0.0728,0.1280,0.2440,0.4760"); + values ("0.2043,0.2199,0.2316,0.2668,0.3098,0.4152,0.6066",\ +"0.1887,0.2043,0.2199,0.2512,0.2941,0.3996,0.5949",\ +"0.1730,0.1887,0.2043,0.2355,0.2824,0.3840,0.5793",\ +"0.1418,0.1574,0.1730,0.2043,0.2512,0.3566,0.5480",\ +"0.0949,0.1105,0.1262,0.1574,0.2043,0.3020,0.5051",\ +"-0.0066,0.0090,0.0246,0.0520,0.0988,0.2043,0.3996",\ +"-0.2020,-0.1863,-0.1746,-0.1434,-0.0965,0.0090,0.2082"); + } + + fall_constraint("SIG2SRAM_constraint_template") { + index_1("0.0056,0.0232,0.0400,0.0728,0.1280,0.2440,0.4760"); + index_2("0.0056,0.0232,0.0400,0.0728,0.1280,0.2440,0.4760"); + values ("0.2980,0.3137,0.3254,0.3527,0.4035,0.5012,0.6887",\ +"0.2824,0.2980,0.3098,0.3371,0.3879,0.4855,0.6730",\ +"0.2668,0.2824,0.2941,0.3215,0.3723,0.4699,0.6574",\ +"0.2355,0.2473,0.2629,0.2902,0.3410,0.4387,0.6262",\ +"0.1887,0.2004,0.2160,0.2395,0.2941,0.3918,0.5793",\ +"0.0871,0.1027,0.1145,0.1418,0.1848,0.2746,0.4816",\ +"-0.1082,-0.0965,-0.0809,-0.0496,-0.0027,0.0949,0.2863"); + } + } + + + timing() { + timing_type : hold_rising; + related_pin : "B_BIST_CLK"; + + rise_constraint("SIG2SRAM_constraint_template") { + index_1("0.0056,0.0232,0.0400,0.0728,0.1280,0.2440,0.4760"); + index_2("0.0056,0.0232,0.0400,0.0728,0.1280,0.2440,0.4760"); + values ("0.2512,0.2355,0.2199,0.1926,0.1418,0.0402,-0.1590",\ +"0.2668,0.2512,0.2355,0.2082,0.1574,0.0559,-0.1434",\ +"0.2824,0.2629,0.2512,0.2199,0.1691,0.0715,-0.1316",\ +"0.3137,0.2980,0.2824,0.2512,0.2004,0.0988,-0.0965",\ +"0.3566,0.3410,0.3254,0.2980,0.2473,0.1418,-0.0535",\ +"0.4621,0.4426,0.4309,0.3996,0.3527,0.2473,0.0520",\ +"0.6574,0.6418,0.6262,0.5949,0.5441,0.4465,0.2473"); + } + + fall_constraint("SIG2SRAM_constraint_template") { + index_1("0.0056,0.0232,0.0400,0.0728,0.1280,0.2440,0.4760"); + index_2("0.0056,0.0232,0.0400,0.0728,0.1280,0.2440,0.4760"); + values ("0.2395,0.2238,0.2121,0.1809,0.1301,0.0324,-0.1551",\ +"0.2551,0.2434,0.2277,0.1965,0.1457,0.0480,-0.1395",\ +"0.2707,0.2551,0.2395,0.2082,0.1574,0.0637,-0.1277",\ +"0.3020,0.2863,0.2707,0.2434,0.1926,0.0910,-0.0965",\ +"0.3449,0.3332,0.3176,0.2863,0.2355,0.1379,-0.0496",\ +"0.4504,0.4348,0.4230,0.3918,0.3410,0.2434,0.0559",\ +"0.6457,0.6301,0.6145,0.5910,0.5324,0.4387,0.2512"); + } + } + } +bus(B_BIST_BM) { + bus_type : D_31_0; + direction : input ; + capacitance : 0.00275526 ; + max_transition : "0.476" ; + pin(B_BIST_BM[31:0]) { + related_power_pin : VDD; + related_ground_pin : VSS; + internal_power() { + when : "B_BIST_MEN"; + rise_power("scalar"){ + values (0.1133); + } + fall_power("scalar"){ + values (0.0512); + } + } + internal_power() { + when : "!B_BIST_MEN"; + rise_power("scalar"){ + values (0.1175); + } + fall_power("scalar"){ + values (0.0489); + } + } + } + timing() { + timing_type : setup_rising; + related_pin : "B_BIST_CLK"; + when : "(B_BIST_WEN & B_BIST_MEN)" + sdf_cond : "B_BIST_RW_ACCESS" + + rise_constraint("SIG2SRAM_constraint_template") { + index_1("0.0056,0.0232,0.0400,0.0728,0.1280,0.2440,0.4760"); + index_2("0.0056,0.0232,0.0400,0.0728,0.1280,0.2440,0.4760"); + values ("-0.5146,-0.4990,-0.4853,-0.4531,-0.4062,-0.3017,-0.1103",\ +"-0.5196,-0.5040,-0.4903,-0.4581,-0.4112,-0.3067,-0.1153",\ +"-0.5241,-0.5085,-0.4948,-0.4626,-0.4157,-0.3112,-0.1198",\ +"-0.5332,-0.5176,-0.5039,-0.4717,-0.4248,-0.3203,-0.1289",\ +"-0.5405,-0.5248,-0.5112,-0.4789,-0.4321,-0.3276,-0.1362",\ +"-0.5706,-0.5549,-0.5413,-0.5090,-0.4621,-0.3577,-0.1663",\ +"-0.6281,-0.6125,-0.5988,-0.5666,-0.5197,-0.4153,-0.2238"); + } + + fall_constraint("SIG2SRAM_constraint_template") { + index_1("0.0056,0.0232,0.0400,0.0728,0.1280,0.2440,0.4760"); + index_2("0.0056,0.0232,0.0400,0.0728,0.1280,0.2440,0.4760"); + values ("-0.4765,-0.4619,-0.4482,-0.4199,-0.3691,-0.2715,-0.0888",\ +"-0.4815,-0.4669,-0.4532,-0.4249,-0.3741,-0.2765,-0.0938",\ +"-0.4860,-0.4714,-0.4577,-0.4294,-0.3786,-0.2809,-0.0983",\ +"-0.4951,-0.4805,-0.4668,-0.4385,-0.3877,-0.2900,-0.1074",\ +"-0.5024,-0.4877,-0.4741,-0.4457,-0.3950,-0.2973,-0.1147",\ +"-0.5325,-0.5178,-0.5041,-0.4758,-0.4250,-0.3274,-0.1448",\ +"-0.5901,-0.5754,-0.5617,-0.5334,-0.4826,-0.3850,-0.2024"); + } + } + + + timing() { + timing_type : hold_rising; + related_pin : "B_BIST_CLK"; + when : "(B_BIST_WEN & B_BIST_MEN)" + sdf_cond : "B_BIST_RW_ACCESS" + + rise_constraint("SIG2SRAM_constraint_template") { + index_1("0.0056,0.0232,0.0400,0.0728,0.1280,0.2440,0.4760"); + index_2("0.0056,0.0232,0.0400,0.0728,0.1280,0.2440,0.4760"); + values ("0.6250,0.6084,0.5957,0.5635,0.5156,0.4121,0.2197",\ +"0.6300,0.6134,0.6007,0.5685,0.5206,0.4171,0.2247",\ +"0.6345,0.6179,0.6052,0.5729,0.5251,0.4216,0.2292",\ +"0.6436,0.6270,0.6143,0.5820,0.5342,0.4307,0.2383",\ +"0.6508,0.6342,0.6215,0.5893,0.5415,0.4379,0.2456",\ +"0.6809,0.6643,0.6516,0.6194,0.5715,0.4680,0.2756",\ +"0.7385,0.7219,0.7092,0.6770,0.6291,0.5256,0.3332"); + } + + fall_constraint("SIG2SRAM_constraint_template") { + index_1("0.0056,0.0232,0.0400,0.0728,0.1280,0.2440,0.4760"); + index_2("0.0056,0.0232,0.0400,0.0728,0.1280,0.2440,0.4760"); + values ("0.5791,0.5644,0.5508,0.5224,0.4726,0.3799,0.1953",\ +"0.5841,0.5694,0.5558,0.5274,0.4776,0.3849,0.2003",\ +"0.5886,0.5739,0.5602,0.5319,0.4821,0.3893,0.2048",\ +"0.5977,0.5830,0.5693,0.5410,0.4912,0.3984,0.2139",\ +"0.6049,0.5903,0.5766,0.5483,0.4985,0.4057,0.2211",\ +"0.6350,0.6204,0.6067,0.5784,0.5286,0.4358,0.2512",\ +"0.6926,0.6780,0.6643,0.6360,0.5862,0.4934,0.3088"); + } + } +} + pin(B_BIST_CLK) { + direction : input; + capacitance : 0.00380014; + max_transition : "0.476"; + clock : "true" ; + pin_func_type : active_rising ; + + timing () { + timing_type : "min_pulse_width"; + related_pin : "B_BIST_CLK"; + rise_constraint("CLKTRAN_constraint_template") { + index_1("0.0056,0.476"); + values("0.21,0.21"); + } + } + + related_power_pin : VDD; + related_ground_pin : VSS; + + internal_power() { + when : "!B_BIST_MEN & !B_BIST_WEN & !B_BIST_REN"; + rise_power("scalar"){ + values (0); + } + fall_power("scalar"){ + values (0); + } + } + internal_power() { + when : "!B_BIST_MEN & B_BIST_WEN & !B_BIST_REN"; + rise_power("scalar"){ + values (0.5389); + } + fall_power("scalar"){ + values (0); + } + } + internal_power() { + when : "B_BIST_MEN & B_BIST_WEN & !B_BIST_REN"; + rise_power("scalar"){ + values (42.3165); + } + fall_power("scalar"){ + values (0); + } + } + internal_power() { + when : "B_BIST_MEN & B_BIST_WEN & B_BIST_REN"; + rise_power("scalar"){ + values (47.6101); + } + fall_power("scalar"){ + values (0); + } + } + internal_power() { + when : "B_BIST_MEN & !B_BIST_WEN & B_BIST_REN"; + rise_power("scalar"){ + values (36.0099); + } + fall_power("scalar"){ + values (0); + } + } + internal_power() { + when : "!B_BIST_MEN & !B_BIST_WEN & B_BIST_REN"; + rise_power("scalar"){ + values (0.3230); + } + fall_power("scalar"){ + values (0); + } + } + internal_power() { + when : "!B_BIST_MEN & B_BIST_WEN & B_BIST_REN"; + rise_power("scalar"){ + values (1.2182); + } + fall_power("scalar"){ + values (0); + } + } + internal_power() { + when : "B_BIST_MEN & !B_BIST_WEN & !B_BIST_REN"; + rise_power("scalar"){ + values (0); + } + fall_power("scalar"){ + values (0); + } + } + } + bus(B_BIST_DIN) { + bus_type : D_31_0; + direction : input ; + capacitance : 0.00414348 ; + memory_write() { + address : B_BIST_ADDR ; + clocked_on : B_BIST_CLK; + } + + max_transition : "0.476" ; + pin(B_BIST_DIN[31:0]) { + related_power_pin : VDD; + related_ground_pin : VSS; + internal_power() { + when : "B_BIST_MEN"; + rise_power("scalar"){ + values (0.1133); + } + fall_power("scalar"){ + values (0.0512); + } + } + internal_power() { + when : "!B_BIST_MEN"; + rise_power("scalar"){ + values (0.1175); + } + fall_power("scalar"){ + values (0.0489); + } + } + } + timing() { + timing_type : setup_rising; + related_pin : "B_BIST_CLK"; + when : "(B_BIST_WEN & B_BIST_MEN)"; + sdf_cond : "B_BIST_W_ACCESS"; + + rise_constraint("SIG2SRAM_constraint_template") { + index_1("0.0056,0.0232,0.0400,0.0728,0.1280,0.2440,0.4760"); + index_2("0.0056,0.0232,0.0400,0.0728,0.1280,0.2440,0.4760"); + values ("-0.5146,-0.4990,-0.4853,-0.4531,-0.4062,-0.3017,-0.1103",\ +"-0.5196,-0.5040,-0.4903,-0.4581,-0.4112,-0.3067,-0.1153",\ +"-0.5241,-0.5085,-0.4948,-0.4626,-0.4157,-0.3112,-0.1198",\ +"-0.5332,-0.5176,-0.5039,-0.4717,-0.4248,-0.3203,-0.1289",\ +"-0.5405,-0.5248,-0.5112,-0.4789,-0.4321,-0.3276,-0.1362",\ +"-0.5706,-0.5549,-0.5413,-0.5090,-0.4621,-0.3577,-0.1663",\ +"-0.6281,-0.6125,-0.5988,-0.5666,-0.5197,-0.4153,-0.2238"); + } + + fall_constraint("SIG2SRAM_constraint_template") { + index_1("0.0056,0.0232,0.0400,0.0728,0.1280,0.2440,0.4760"); + index_2("0.0056,0.0232,0.0400,0.0728,0.1280,0.2440,0.4760"); + values ("-0.4765,-0.4619,-0.4482,-0.4199,-0.3691,-0.2715,-0.0888",\ +"-0.4815,-0.4669,-0.4532,-0.4249,-0.3741,-0.2765,-0.0938",\ +"-0.4860,-0.4714,-0.4577,-0.4294,-0.3786,-0.2809,-0.0983",\ +"-0.4951,-0.4805,-0.4668,-0.4385,-0.3877,-0.2900,-0.1074",\ +"-0.5024,-0.4877,-0.4741,-0.4457,-0.3950,-0.2973,-0.1147",\ +"-0.5325,-0.5178,-0.5041,-0.4758,-0.4250,-0.3274,-0.1448",\ +"-0.5901,-0.5754,-0.5617,-0.5334,-0.4826,-0.3850,-0.2024"); + } + } + + timing() { + timing_type : hold_rising; + related_pin : "B_BIST_CLK"; + when : "(B_BIST_WEN & B_BIST_MEN)"; + sdf_cond : "B_BIST_W_ACCESS"; + + rise_constraint("SIG2SRAM_constraint_template") { + index_1("0.0056,0.0232,0.0400,0.0728,0.1280,0.2440,0.4760"); + index_2("0.0056,0.0232,0.0400,0.0728,0.1280,0.2440,0.4760"); + values ("0.6250,0.6084,0.5957,0.5635,0.5156,0.4121,0.2197",\ +"0.6300,0.6134,0.6007,0.5685,0.5206,0.4171,0.2247",\ +"0.6345,0.6179,0.6052,0.5729,0.5251,0.4216,0.2292",\ +"0.6436,0.6270,0.6143,0.5820,0.5342,0.4307,0.2383",\ +"0.6508,0.6342,0.6215,0.5893,0.5415,0.4379,0.2456",\ +"0.6809,0.6643,0.6516,0.6194,0.5715,0.4680,0.2756",\ +"0.7385,0.7219,0.7092,0.6770,0.6291,0.5256,0.3332"); + } + + fall_constraint("SIG2SRAM_constraint_template") { + index_1("0.0056,0.0232,0.0400,0.0728,0.1280,0.2440,0.4760"); + index_2("0.0056,0.0232,0.0400,0.0728,0.1280,0.2440,0.4760"); + values ("0.5791,0.5644,0.5508,0.5224,0.4726,0.3799,0.1953",\ +"0.5841,0.5694,0.5558,0.5274,0.4776,0.3849,0.2003",\ +"0.5886,0.5739,0.5602,0.5319,0.4821,0.3893,0.2048",\ +"0.5977,0.5830,0.5693,0.5410,0.4912,0.3984,0.2139",\ +"0.6049,0.5903,0.5766,0.5483,0.4985,0.4057,0.2211",\ +"0.6350,0.6204,0.6067,0.5784,0.5286,0.4358,0.2512",\ +"0.6926,0.6780,0.6643,0.6360,0.5862,0.4934,0.3088"); + } + } + } + +bus(B_DOUT) { + + bus_type : D_31_0; + direction : output ; + capacitance : 0 ; + max_capacitance : 0.064 ; + memory_read() { + address : B_ADDR ; + } + pin(B_DOUT[31:0]) { + related_power_pin : VDD; + related_ground_pin : VSS; + internal_power() { + rise_power("scalar") { + values (0); + } + fall_power("scalar") { + values (0); + } + } + } + timing() { + related_pin : "B_CLK"; + timing_type : rising_edge ; + timing_sense : non_unate ; + + cell_rise(SIG2SRAM_delay_template) { + index_1("0.0056,0.0232,0.0400,0.0728,0.1280,0.2440,0.4760"); + index_2("0.0008,0.0014,0.0051,0.0100,0.0339,0.0640"); + values ("3.9022,3.9038,3.9114,3.9201,3.9525,3.9887",\ +"3.9073,3.9090,3.9166,3.9253,3.9577,3.9938",\ +"3.9105,3.9121,3.9198,3.9285,3.9609,3.9970",\ +"3.9230,3.9246,3.9322,3.9410,3.9733,4.0095",\ +"3.9288,3.9304,3.9381,3.9468,3.9792,4.0153",\ +"3.9598,3.9614,3.9690,3.9777,4.0101,4.0463",\ +"4.0155,4.0171,4.0247,4.0335,4.0658,4.1020"); + } + cell_fall(SIG2SRAM_delay_template) { + index_1("0.0056,0.0232,0.0400,0.0728,0.1280,0.2440,0.4760"); + index_2("0.0008,0.0014,0.0051,0.0100,0.0339,0.0640"); + values ("3.8419,3.8432,3.8493,3.8564,3.8829,3.9092",\ +"3.8471,3.8484,3.8545,3.8616,3.8881,3.9143",\ +"3.8503,3.8516,3.8577,3.8648,3.8913,3.9175",\ +"3.8627,3.8641,3.8701,3.8773,3.9038,3.9300",\ +"3.8686,3.8699,3.8760,3.8831,3.9096,3.9358",\ +"3.8995,3.9008,3.9069,3.9140,3.9406,3.9668",\ +"3.9552,3.9566,3.9626,3.9698,3.9963,4.0225"); + } + + rise_transition(SRAM_load_template) { + index_1("0.0008,0.0014,0.0051,0.0100,0.0339,0.0640"); + values ("0.0326,0.0341,0.0428,0.0518,0.0923,0.1492"); + } + fall_transition(SRAM_load_template) { + index_1("0.0008,0.0014,0.0051,0.0100,0.0339,0.0640"); + values ("0.0254,0.0265,0.0335,0.0402,0.0707,0.1039"); + } + } +} +cell_leakage_power : 318.9007; +} +} diff --git a/flow/platforms/ihp-sg13g2/lib/RM_IHPSG13_2P_512x8_c2_bm_bist_fast_1p32V_m55C.lib b/flow/platforms/ihp-sg13g2/lib/RM_IHPSG13_2P_512x8_c2_bm_bist_fast_1p32V_m55C.lib new file mode 100644 index 0000000000..f5ad13ca9a --- /dev/null +++ b/flow/platforms/ihp-sg13g2/lib/RM_IHPSG13_2P_512x8_c2_bm_bist_fast_1p32V_m55C.lib @@ -0,0 +1,2886 @@ +/* ------------------------------------------------------*/ +/**/ +/* Copyright 2025 IHP PDK Authors*/ +/**/ +/* Licensed under the Apache License, Version 2.0 (the "License");*/ +/* you may not use this file except in compliance with the License.*/ +/* You may obtain a copy of the License at*/ +/* */ +/* https://www.apache.org/licenses/LICENSE-2.0*/ +/* */ +/* Unless required by applicable law or agreed to in writing, software*/ +/* distributed under the License is distributed on an "AS IS" BASIS,*/ +/* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.*/ +/* See the License for the specific language governing permissions and*/ +/* limitations under the License.*/ +/* */ +/* Generated on Wed Aug 27 13:34:37 2025 */ +/* */ +/* ------------------------------------------------------ */ +library(RM_IHPSG13_2P_512x8_c2_bm_bist_fast_1p32V_m55C) { + technology (cmos) ; + delay_model : table_lookup ; + define ("add_pg_pin_to_lib", "library", "boolean"); + add_pg_pin_to_lib : true; + voltage_map ( VDD, 1.32); + voltage_map ( VDDARRAY, 1.32); + voltage_map ( VSS, 0.000000 ); + + date : "Wed Aug 27 13:34:35 2025" ; + comment : "IHP Microelectronics GmbH, 2023" ; + revision : 1.0.0 ; + simulation : true ; + nom_process : 1 ; + nom_temperature : -55 ; + nom_voltage : 1.32 ; + + operating_conditions("fast_1p32V_m55C"){ + process : 1 ; + temperature : -55 ; + voltage : 1.32 ; + tree_type : "balanced_tree" ; + } + + default_operating_conditions : fast_1p32V_m55C ; + default_max_transition : 1.0 ; + default_fanout_load : 1.0 ; + default_inout_pin_cap : 0.0 ; + default_input_pin_cap : 0.0 ; + default_output_pin_cap : 0.0 ; + default_cell_leakage_power : 0.0 ; + default_leakage_power_density : 0.0 ; + + slew_lower_threshold_pct_rise : 30 ; + slew_upper_threshold_pct_rise : 70 ; + input_threshold_pct_fall : 50 ; + output_threshold_pct_fall : 50 ; + input_threshold_pct_rise : 50 ; + output_threshold_pct_rise : 50 ; + slew_lower_threshold_pct_fall : 30 ; + slew_upper_threshold_pct_fall : 70 ; + slew_derate_from_library : 0.5; + k_volt_cell_leakage_power : 0.0 ; + k_temp_cell_leakage_power : 0.0 ; + k_process_cell_leakage_power : 0.0 ; + k_volt_internal_power : 0.0 ; + k_temp_internal_power : 0.0 ; + k_process_internal_power : 0.0 ; + + capacitive_load_unit (1,pf) ; + voltage_unit : "1V" ; + current_unit : "1uA" ; + time_unit : "1ns" ; + leakage_power_unit : "1nW" ; + pulling_resistance_unit : "1kohm"; + /* + ------------------------------------------------------------------------------------------ + implicit units overview: + cell_area unit : "um" + internal_power unit : "1e-12 * J/toggle = 1 * uW/MHz" + (capacitive_load_unit * voltage_unit^2) per toggle event + ------------------------------------------------------------------------------------------ + */ + library_features(report_delay_calculation); + define_cell_area (pad_drivers,pad_driver_sites) ; + + lu_table_template(CLKTRAN_constraint_template) { + variable_1 : constrained_pin_transition; + index_1 ( "0.010, 0.050, 0.200, 0.400, 1.000" ); + } + lu_table_template(SRAM_load_template) { + variable_1 : total_output_net_capacitance; + index_1 ( "0.0008,0.0014,0.0051,0.0100,0.0339,0.0640" ); + } + lu_table_template(SIG2SRAM_constraint_template) { + variable_1 : related_pin_transition; + variable_2 : constrained_pin_transition; + index_1 ( "0.0040,0.0176,0.0344,0.0656,0.1120,0.2016,0.3800" ); + index_2 ( "0.0040,0.0176,0.0344,0.0656,0.1120,0.2016,0.3800" ); + } + + lu_table_template(SIG2SRAM_delay_template) { + variable_1 : input_net_transition; + variable_2 : total_output_net_capacitance; + index_1 ( "0.0040,0.0176,0.0344,0.0656,0.1120,0.2016,0.3800" ); + index_2 ( "0.0008,0.0014,0.0051,0.0100,0.0339,0.0640" ); + } + + type (D_7_0) { + base_type : array; + data_type : bit; + bit_width : 8; + bit_from : 7; + bit_to : 0; + downto : true; + } + + type (A_8_0) { + base_type : array; + data_type : bit; + bit_width : 9; + bit_from : 8; + bit_to : 0; + downto : true; + } + +cell(RM_IHPSG13_2P_512x8_c2_bm_bist) { +pg_pin (VDD) { + pg_type : primary_power; + voltage_name : VDD; +} +pg_pin (VDDARRAY) { + pg_type : primary_power; + voltage_name : VDDARRAY; +} +pg_pin (VSS) { + pg_type : primary_ground; + voltage_name : VSS; +} + +memory() { + type : ram; + address_width : 9; + word_width : 8; +} + +interface_timing : false; +bus_naming_style : "%s[%d]" ; +area : 57397.3309 ; + + pin(A_DLY) { + direction : input ; + capacitance : 0.00421562 ; + max_transition : "1" ; + related_power_pin : VDD; + related_ground_pin : VSS; + internal_power() { + rise_power("scalar") { + values (0); + } + fall_power("scalar") { + values (0); + } + } + } + +bus(A_ADDR) { + bus_type : A_8_0; + direction : input ; + capacitance : 0.0115194 ; + pin(A_ADDR[0]) { + capacitance : 0.00563454 ; + } + pin(A_ADDR[1]) { + capacitance : 0.00744185 ; + } + pin(A_ADDR[2]) { + capacitance : 0.0100611 ; + } + pin(A_ADDR[3]) { + capacitance : 0.00669965 ; + } + pin(A_ADDR[4]) { + capacitance : 0.00614331 ; + } + pin(A_ADDR[5]) { + capacitance : 0.0102172 ; + } + pin(A_ADDR[6]) { + capacitance : 0.0124225 ; + } + pin(A_ADDR[7]) { + capacitance : 0.010114 ; + } + max_transition : "0.38" ; + pin(A_ADDR[8:0]) { + related_power_pin : VDD; + related_ground_pin : VSS; + internal_power() { + when : "A_MEN"; + rise_power("scalar"){ + values (0.0129); + } + fall_power("scalar"){ + values (0.0027); + } + } + internal_power() { + when : "!A_MEN"; + rise_power("scalar"){ + values (0.0261); + } + fall_power("scalar"){ + values (0.0017); + } + } + } + timing() { + timing_type : setup_rising; + related_pin : "A_CLK"; + when : "((A_WEN | A_REN)& A_MEN)" + sdf_cond : "A_RW_ACCESS" + + rise_constraint("SIG2SRAM_constraint_template") { + index_1("0.0040,0.0176,0.0344,0.0656,0.1120,0.2016,0.3800"); + index_2("0.0040,0.0176,0.0344,0.0656,0.1120,0.2016,0.3800"); + values ("-0.2371,-0.2215,-0.2098,-0.1824,-0.1434,-0.0691,0.0676",\ +"-0.2449,-0.2332,-0.2176,-0.1902,-0.1551,-0.0770,0.0559",\ +"-0.2605,-0.2488,-0.2332,-0.2059,-0.1707,-0.0965,0.0441",\ +"-0.2879,-0.2723,-0.2605,-0.2332,-0.1941,-0.1199,0.0168",\ +"-0.3230,-0.3113,-0.2996,-0.2723,-0.2332,-0.1590,-0.0184",\ +"-0.4012,-0.3895,-0.3738,-0.3465,-0.3074,-0.2332,-0.0965",\ +"-0.5379,-0.5262,-0.5105,-0.4832,-0.4480,-0.3699,-0.2332"); + } + + fall_constraint("SIG2SRAM_constraint_template") { + index_1("0.0040,0.0176,0.0344,0.0656,0.1120,0.2016,0.3800"); + index_2("0.0040,0.0176,0.0344,0.0656,0.1120,0.2016,0.3800"); + values ("-0.1785,-0.1707,-0.1551,-0.1277,-0.0887,-0.0184,0.1145",\ +"-0.1902,-0.1785,-0.1629,-0.1355,-0.1004,-0.0262,0.1027",\ +"-0.2059,-0.1941,-0.1785,-0.1512,-0.1160,-0.0418,0.0871",\ +"-0.2293,-0.2176,-0.2059,-0.1785,-0.1434,-0.0691,0.0598",\ +"-0.2684,-0.2566,-0.2449,-0.2176,-0.1824,-0.1082,0.0207",\ +"-0.3465,-0.3348,-0.3191,-0.2918,-0.2566,-0.1824,-0.0535",\ +"-0.4832,-0.4715,-0.4559,-0.4324,-0.3934,-0.3191,-0.1902"); + } + } + + + timing() { + timing_type : hold_rising; + related_pin : "A_CLK"; + when : "((A_WEN | A_REN)& A_MEN)" + sdf_cond : "A_RW_ACCESS" + + rise_constraint("SIG2SRAM_constraint_template") { + index_1("0.0040,0.0176,0.0344,0.0656,0.1120,0.2016,0.3800"); + index_2("0.0040,0.0176,0.0344,0.0656,0.1120,0.2016,0.3800"); + values ("0.3410,0.3293,0.3137,0.2863,0.2473,0.1730,0.0324",\ +"0.3488,0.3371,0.3215,0.2941,0.2590,0.1809,0.0480",\ +"0.3684,0.3527,0.3371,0.3098,0.2746,0.1965,0.0598",\ +"0.3918,0.3762,0.3645,0.3371,0.2980,0.2238,0.0871",\ +"0.4309,0.4152,0.4035,0.3762,0.3371,0.2629,0.1223",\ +"0.5051,0.4934,0.4777,0.4504,0.4113,0.3371,0.1965",\ +"0.6418,0.6262,0.6145,0.5871,0.5520,0.4738,0.3332"); + } + + fall_constraint("SIG2SRAM_constraint_template") { + index_1("0.0040,0.0176,0.0344,0.0656,0.1120,0.2016,0.3800"); + index_2("0.0040,0.0176,0.0344,0.0656,0.1120,0.2016,0.3800"); + values ("0.2824,0.2707,0.2551,0.2277,0.1926,0.1184,-0.0105",\ +"0.2902,0.2785,0.2668,0.2395,0.2043,0.1301,0.0012",\ +"0.3059,0.2941,0.2824,0.2551,0.2199,0.1457,0.0168",\ +"0.3332,0.3215,0.3059,0.2785,0.2434,0.1691,0.0402",\ +"0.3723,0.3605,0.3449,0.3176,0.2824,0.2121,0.0793",\ +"0.4465,0.4348,0.4230,0.3918,0.3566,0.2824,0.1535",\ +"0.5832,0.5715,0.5598,0.5324,0.4934,0.4191,0.2902"); + } + } +} +pin(A_WEN) { + direction : input ; + capacitance : 0.00341384 ; + max_transition : "0.38" ; + related_power_pin : VDD; + related_ground_pin : VSS; + internal_power() { + when : "A_MEN"; + rise_power("scalar"){ + values (0.0072); + } + fall_power("scalar"){ + values (0.0153); + } + } + internal_power() { + when : "!A_MEN"; + rise_power("scalar"){ + values (0.0059); + } + fall_power("scalar"){ + values (0.0232); + } + } + timing() { + timing_type : setup_rising; + related_pin : "A_CLK"; + when : "A_MEN" + sdf_cond : "A_MEN" + + rise_constraint("SIG2SRAM_constraint_template") { + index_1("0.0040,0.0176,0.0344,0.0656,0.1120,0.2016,0.3800"); + index_2("0.0040,0.0176,0.0344,0.0656,0.1120,0.2016,0.3800"); + values ("0.1418,0.1496,0.1652,0.1887,0.2316,0.3059,0.4465",\ +"0.1301,0.1379,0.1535,0.1809,0.2199,0.2941,0.4348",\ +"0.1145,0.1262,0.1379,0.1652,0.2043,0.2785,0.4191",\ +"0.0871,0.0949,0.1105,0.1379,0.1770,0.2512,0.3879",\ +"0.0480,0.0598,0.0754,0.0988,0.1379,0.2082,0.3527",\ +"-0.0262,-0.0145,0.0012,0.0246,0.0676,0.1379,0.2785",\ +"-0.1668,-0.1551,-0.1395,-0.1121,-0.0730,0.0012,0.1418"); + } + + fall_constraint("SIG2SRAM_constraint_template") { + index_1("0.0040,0.0176,0.0344,0.0656,0.1120,0.2016,0.3800"); + index_2("0.0040,0.0176,0.0344,0.0656,0.1120,0.2016,0.3800"); + values ("0.2082,0.2160,0.2316,0.2590,0.2941,0.3684,0.5012",\ +"0.1926,0.2043,0.2199,0.2473,0.2824,0.3566,0.4895",\ +"0.1770,0.1887,0.2043,0.2316,0.2668,0.3410,0.4777",\ +"0.1535,0.1652,0.1770,0.2043,0.2395,0.3137,0.4504",\ +"0.1145,0.1262,0.1379,0.1652,0.2043,0.2746,0.4113",\ +"0.0402,0.0520,0.0676,0.0910,0.1262,0.2004,0.3332",\ +"-0.0965,-0.0848,-0.0730,-0.0457,-0.0066,0.0637,0.2004"); + } + } + + + timing() { + timing_type : hold_rising; + related_pin : "A_CLK"; + when : "A_MEN" + sdf_cond : "A_MEN" + + rise_constraint("SIG2SRAM_constraint_template") { + index_1("0.0040,0.0176,0.0344,0.0656,0.1120,0.2016,0.3800"); + index_2("0.0040,0.0176,0.0344,0.0656,0.1120,0.2016,0.3800"); + values ("0.1770,0.1652,0.1496,0.1223,0.0793,0.0090,-0.1316",\ +"0.1848,0.1730,0.1574,0.1301,0.0910,0.0168,-0.1199",\ +"0.2004,0.1887,0.1770,0.1496,0.1066,0.0363,-0.1043",\ +"0.2277,0.2160,0.2004,0.1730,0.1340,0.0598,-0.0809",\ +"0.2668,0.2551,0.2395,0.2121,0.1730,0.0988,-0.0418",\ +"0.3410,0.3293,0.3137,0.2863,0.2434,0.1730,0.0324",\ +"0.4816,0.4699,0.4543,0.4230,0.3801,0.3098,0.1730"); + } + + fall_constraint("SIG2SRAM_constraint_template") { + index_1("0.0040,0.0176,0.0344,0.0656,0.1120,0.2016,0.3800"); + index_2("0.0040,0.0176,0.0344,0.0656,0.1120,0.2016,0.3800"); + values ("0.1613,0.1496,0.1379,0.1066,0.0715,0.0012,-0.1355",\ +"0.1730,0.1613,0.1457,0.1184,0.0832,0.0129,-0.1238",\ +"0.1887,0.1770,0.1613,0.1340,0.0988,0.0246,-0.1121",\ +"0.2121,0.2043,0.1887,0.1613,0.1223,0.0520,-0.0848",\ +"0.2512,0.2434,0.2277,0.2004,0.1613,0.0910,-0.0457",\ +"0.3254,0.3176,0.3020,0.2746,0.2355,0.1652,0.0324",\ +"0.4660,0.4543,0.4387,0.4113,0.3723,0.3020,0.1691"); + } + } + } +pin(A_REN) { + direction : input ; + capacitance : 0.00390661 ; + max_transition : "0.38" ; + related_power_pin : VDD; + related_ground_pin : VSS; + internal_power() { + when : "A_MEN"; + rise_power("scalar"){ + values (0.0097); + } + fall_power("scalar"){ + values (0.0114); + } + } + internal_power() { + when : "!A_MEN"; + rise_power("scalar"){ + values (0.0259); + } + fall_power("scalar"){ + values (0.0195); + } + } + timing() { + timing_type : setup_rising; + related_pin : "A_CLK"; + when : "A_MEN" + sdf_cond : "A_MEN" + + rise_constraint("SIG2SRAM_constraint_template") { + index_1("0.0040,0.0176,0.0344,0.0656,0.1120,0.2016,0.3800"); + index_2("0.0040,0.0176,0.0344,0.0656,0.1120,0.2016,0.3800"); + values ("-0.0027,0.0090,0.0246,0.0520,0.0910,0.1613,0.3020",\ +"-0.0105,0.0012,0.0129,0.0363,0.0793,0.1535,0.2902",\ +"-0.0262,-0.0145,-0.0027,0.0246,0.0637,0.1379,0.2785",\ +"-0.0535,-0.0418,-0.0262,0.0012,0.0363,0.1105,0.2512",\ +"-0.0926,-0.0809,-0.0652,-0.0418,-0.0027,0.0715,0.2121",\ +"-0.1668,-0.1551,-0.1395,-0.1082,-0.0770,-0.0027,0.1379",\ +"-0.3035,-0.2918,-0.2762,-0.2488,-0.2137,-0.1434,-0.0027"); + } + + fall_constraint("SIG2SRAM_constraint_template") { + index_1("0.0040,0.0176,0.0344,0.0656,0.1120,0.2016,0.3800"); + index_2("0.0040,0.0176,0.0344,0.0656,0.1120,0.2016,0.3800"); + values ("0.0832,0.0949,0.1105,0.1379,0.1730,0.2473,0.3801",\ +"0.0754,0.0832,0.0988,0.1223,0.1613,0.2355,0.3684",\ +"0.0598,0.0676,0.0832,0.1066,0.1457,0.2121,0.3527",\ +"0.0324,0.0441,0.0598,0.0871,0.1223,0.1926,0.3293",\ +"-0.0066,0.0051,0.0168,0.0480,0.0832,0.1535,0.2902",\ +"-0.0809,-0.0691,-0.0574,-0.0301,0.0090,0.0832,0.2121",\ +"-0.2176,-0.2059,-0.1941,-0.1668,-0.1277,-0.0574,0.0793"); + } + } + + + timing() { + timing_type : hold_rising; + related_pin : "A_CLK"; + when : "A_MEN" + sdf_cond : "A_MEN" + + rise_constraint("SIG2SRAM_constraint_template") { + index_1("0.0040,0.0176,0.0344,0.0656,0.1120,0.2016,0.3800"); + index_2("0.0040,0.0176,0.0344,0.0656,0.1120,0.2016,0.3800"); + values ("0.1887,0.1770,0.1613,0.1340,0.0949,0.0207,-0.1160",\ +"0.1965,0.1848,0.1730,0.1457,0.1027,0.0324,-0.1082",\ +"0.2160,0.2004,0.1887,0.1613,0.1184,0.0480,-0.0926",\ +"0.2395,0.2277,0.2121,0.1848,0.1457,0.0715,-0.0652",\ +"0.2785,0.2668,0.2512,0.2238,0.1848,0.1105,-0.0262",\ +"0.3527,0.3410,0.3254,0.2980,0.2551,0.1848,0.0480",\ +"0.4934,0.4816,0.4660,0.4387,0.3957,0.3254,0.1887"); + } + + fall_constraint("SIG2SRAM_constraint_template") { + index_1("0.0040,0.0176,0.0344,0.0656,0.1120,0.2016,0.3800"); + index_2("0.0040,0.0176,0.0344,0.0656,0.1120,0.2016,0.3800"); + values ("0.1730,0.1613,0.1496,0.1184,0.0793,0.0129,-0.1238",\ +"0.1848,0.1730,0.1574,0.1301,0.0910,0.0207,-0.1121",\ +"0.2004,0.1887,0.1730,0.1457,0.1066,0.0363,-0.1004",\ +"0.2238,0.2121,0.2004,0.1691,0.1340,0.0598,-0.0730",\ +"0.2629,0.2512,0.2395,0.2121,0.1691,0.0988,-0.0340",\ +"0.3371,0.3254,0.3137,0.2863,0.2434,0.1730,0.0402",\ +"0.4777,0.4660,0.4504,0.4230,0.3840,0.3137,0.1809"); + } + } + } +pin(A_MEN) { + direction : input ; + capacitance : 0.00326046 ; + max_transition : "0.38" ; + related_power_pin : VDD; + related_ground_pin : VSS; + internal_power() { + rise_power("scalar"){ + values (0.0831); + } + fall_power("scalar"){ + values (0.0107); + } + } + timing() { + timing_type : setup_rising; + related_pin : "A_CLK"; + + rise_constraint("SIG2SRAM_constraint_template") { + index_1("0.0040,0.0176,0.0344,0.0656,0.1120,0.2016,0.3800"); + index_2("0.0040,0.0176,0.0344,0.0656,0.1120,0.2016,0.3800"); + values ("0.1418,0.1496,0.1652,0.1926,0.2316,0.3059,0.4465",\ +"0.1301,0.1379,0.1535,0.1809,0.2199,0.2941,0.4348",\ +"0.1145,0.1262,0.1418,0.1652,0.2043,0.2785,0.4191",\ +"0.0871,0.0949,0.1105,0.1379,0.1770,0.2512,0.3879",\ +"0.0480,0.0598,0.0754,0.0988,0.1379,0.2082,0.3488",\ +"-0.0262,-0.0145,0.0012,0.0285,0.0676,0.1379,0.2785",\ +"-0.1668,-0.1551,-0.1395,-0.1121,-0.0730,0.0012,0.1379"); + } + + fall_constraint("SIG2SRAM_constraint_template") { + index_1("0.0040,0.0176,0.0344,0.0656,0.1120,0.2016,0.3800"); + index_2("0.0040,0.0176,0.0344,0.0656,0.1120,0.2016,0.3800"); + values ("0.2082,0.2199,0.2316,0.2590,0.2980,0.3723,0.5051",\ +"0.1965,0.2082,0.2199,0.2473,0.2863,0.3605,0.4934",\ +"0.1809,0.1926,0.2043,0.2316,0.2707,0.3449,0.4777",\ +"0.1574,0.1691,0.1809,0.2082,0.2434,0.3176,0.4543",\ +"0.1145,0.1262,0.1418,0.1691,0.2043,0.2785,0.4113",\ +"0.0441,0.0559,0.0676,0.0949,0.1301,0.2004,0.3332",\ +"-0.0965,-0.0848,-0.0691,-0.0418,-0.0066,0.0676,0.2004"); + } + } + + + timing() { + timing_type : hold_rising; + related_pin : "A_CLK"; + + rise_constraint("SIG2SRAM_constraint_template") { + index_1("0.0040,0.0176,0.0344,0.0656,0.1120,0.2016,0.3800"); + index_2("0.0040,0.0176,0.0344,0.0656,0.1120,0.2016,0.3800"); + values ("0.1770,0.1652,0.1535,0.1262,0.0832,0.0129,-0.1277",\ +"0.1887,0.1770,0.1613,0.1340,0.0949,0.0207,-0.1199",\ +"0.2043,0.1926,0.1770,0.1496,0.1105,0.0363,-0.1043",\ +"0.2277,0.2160,0.2043,0.1770,0.1379,0.0598,-0.0770",\ +"0.2668,0.2551,0.2434,0.2160,0.1730,0.0988,-0.0379",\ +"0.3449,0.3332,0.3176,0.2902,0.2473,0.1730,0.0363",\ +"0.4816,0.4699,0.4543,0.4270,0.3840,0.3098,0.1770"); + } + + fall_constraint("SIG2SRAM_constraint_template") { + index_1("0.0040,0.0176,0.0344,0.0656,0.1120,0.2016,0.3800"); + index_2("0.0040,0.0176,0.0344,0.0656,0.1120,0.2016,0.3800"); + values ("0.1613,0.1496,0.1379,0.1105,0.0715,0.0012,-0.1355",\ +"0.1730,0.1613,0.1496,0.1184,0.0832,0.0129,-0.1238",\ +"0.1887,0.1770,0.1652,0.1340,0.0988,0.0285,-0.1121",\ +"0.2121,0.2043,0.1887,0.1613,0.1223,0.0520,-0.0848",\ +"0.2551,0.2434,0.2277,0.2004,0.1613,0.0910,-0.0418",\ +"0.3293,0.3176,0.3020,0.2746,0.2395,0.1652,0.0324",\ +"0.4660,0.4543,0.4426,0.4113,0.3762,0.3020,0.1691"); + } + } + } +bus(A_BM) { + bus_type : D_7_0; + direction : input ; + capacitance : 0.00388883 ; + max_transition : "0.38" ; + pin(A_BM[7:0]) { + related_power_pin : VDD; + related_ground_pin : VSS; + internal_power() { + when : "A_MEN"; + rise_power("scalar"){ + values (0.0400); + } + fall_power("scalar"){ + values (0.0357); + } + } + internal_power() { + when : "!A_MEN"; + rise_power("scalar"){ + values (0.0592); + } + fall_power("scalar"){ + values (0.0441); + } + } + } + timing() { + timing_type : setup_rising; + related_pin : "A_CLK"; + when : "(A_WEN & A_MEN)" + sdf_cond : "A_RW_ACCESS" + + rise_constraint("SIG2SRAM_constraint_template") { + index_1("0.0040,0.0176,0.0344,0.0656,0.1120,0.2016,0.3800"); + index_2("0.0040,0.0176,0.0344,0.0656,0.1120,0.2016,0.3800"); + values ("-0.1725,-0.1618,-0.1462,-0.1208,-0.0798,-0.0065,0.1282",\ +"-0.1764,-0.1657,-0.1501,-0.1247,-0.0836,-0.0104,0.1244",\ +"-0.1802,-0.1695,-0.1539,-0.1285,-0.0874,-0.0142,0.1206",\ +"-0.1835,-0.1727,-0.1571,-0.1317,-0.0907,-0.0175,0.1173",\ +"-0.1959,-0.1852,-0.1695,-0.1442,-0.1031,-0.0299,0.1049",\ +"-0.2135,-0.2028,-0.1872,-0.1618,-0.1208,-0.0475,0.0872",\ +"-0.2410,-0.2303,-0.2147,-0.1893,-0.1483,-0.0750,0.0597"); + } + + fall_constraint("SIG2SRAM_constraint_template") { + index_1("0.0040,0.0176,0.0344,0.0656,0.1120,0.2016,0.3800"); + index_2("0.0040,0.0176,0.0344,0.0656,0.1120,0.2016,0.3800"); + values ("-0.1491,-0.1374,-0.1247,-0.0973,-0.0602,0.0130,0.1409",\ +"-0.1530,-0.1413,-0.1286,-0.1012,-0.0641,0.0091,0.1370",\ +"-0.1568,-0.1451,-0.1324,-0.1050,-0.0679,0.0053,0.1333",\ +"-0.1600,-0.1483,-0.1356,-0.1083,-0.0712,0.0021,0.1300",\ +"-0.1725,-0.1608,-0.1481,-0.1207,-0.0836,-0.0104,0.1176",\ +"-0.1901,-0.1784,-0.1657,-0.1383,-0.1012,-0.0280,0.0999",\ +"-0.2176,-0.2059,-0.1932,-0.1658,-0.1287,-0.0555,0.0724"); + } + } + + + timing() { + timing_type : hold_rising; + related_pin : "A_CLK"; + when : "(A_WEN & A_MEN)" + sdf_cond : "A_RW_ACCESS" + + rise_constraint("SIG2SRAM_constraint_template") { + index_1("0.0040,0.0176,0.0344,0.0656,0.1120,0.2016,0.3800"); + index_2("0.0040,0.0176,0.0344,0.0656,0.1120,0.2016,0.3800"); + values ("0.2776,0.2678,0.2522,0.2259,0.1887,0.1145,-0.0202",\ +"0.2815,0.2717,0.2561,0.2297,0.1926,0.1184,-0.0164",\ +"0.2853,0.2755,0.2599,0.2335,0.1964,0.1222,-0.0126",\ +"0.2885,0.2788,0.2632,0.2368,0.1997,0.1255,-0.0093",\ +"0.3010,0.2912,0.2756,0.2492,0.2121,0.1379,0.0031",\ +"0.3186,0.3088,0.2932,0.2668,0.2297,0.1555,0.0208",\ +"0.3461,0.3363,0.3207,0.2944,0.2572,0.1830,0.0483"); + } + + fall_constraint("SIG2SRAM_constraint_template") { + index_1("0.0040,0.0176,0.0344,0.0656,0.1120,0.2016,0.3800"); + index_2("0.0040,0.0176,0.0344,0.0656,0.1120,0.2016,0.3800"); + values ("0.2493,0.2385,0.2249,0.1975,0.1614,0.0891,-0.0407",\ +"0.2532,0.2424,0.2288,0.2014,0.1653,0.0930,-0.0369",\ +"0.2570,0.2462,0.2326,0.2052,0.1691,0.0968,-0.0331",\ +"0.2602,0.2495,0.2358,0.2085,0.1723,0.1001,-0.0298",\ +"0.2727,0.2619,0.2483,0.2209,0.1848,0.1125,-0.0174",\ +"0.2903,0.2795,0.2659,0.2385,0.2024,0.1301,0.0002",\ +"0.3178,0.3070,0.2934,0.2660,0.2299,0.1576,0.0278"); + } + } +} + pin(A_CLK) { + direction : input; + capacitance : 0.00389386; + max_transition : "0.38"; + clock : "true" ; + pin_func_type : active_rising ; + + timing () { + timing_type : "min_pulse_width"; + related_pin : "A_CLK"; + rise_constraint("CLKTRAN_constraint_template") { + index_1("0.004,0.38"); + values("0.12,0.12"); + } + } + + related_power_pin : VDD; + related_ground_pin : VSS; + + internal_power() { + when : "!A_MEN & !A_WEN & !A_REN"; + rise_power("scalar"){ + values (0); + } + fall_power("scalar"){ + values (0); + } + } + internal_power() { + when : "!A_MEN & A_WEN & !A_REN"; + rise_power("scalar"){ + values (0.6678); + } + fall_power("scalar"){ + values (0); + } + } + internal_power() { + when : "A_MEN & A_WEN & !A_REN"; + rise_power("scalar"){ + values (17.5281); + } + fall_power("scalar"){ + values (0); + } + } + internal_power() { + when : "A_MEN & A_WEN & A_REN"; + rise_power("scalar"){ + values (17.8148); + } + fall_power("scalar"){ + values (0); + } + } + internal_power() { + when : "A_MEN & !A_WEN & A_REN"; + rise_power("scalar"){ + values (14.1173); + } + fall_power("scalar"){ + values (0); + } + } + internal_power() { + when : "!A_MEN & !A_WEN & A_REN"; + rise_power("scalar"){ + values (0.3934); + } + fall_power("scalar"){ + values (0); + } + } + internal_power() { + when : "!A_MEN & A_WEN & A_REN"; + rise_power("scalar"){ + values (0.6886); + } + fall_power("scalar"){ + values (0); + } + } + internal_power() { + when : "A_MEN & !A_WEN & !A_REN"; + rise_power("scalar"){ + values (0); + } + fall_power("scalar"){ + values (0); + } + } + } + bus(A_DIN) { + bus_type : D_7_0; + direction : input ; + capacitance : 0.00505326 ; + memory_write() { + address : A_ADDR ; + clocked_on : A_CLK; + } + + max_transition : "0.38" ; + pin(A_DIN[7:0]) { + related_power_pin : VDD; + related_ground_pin : VSS; + internal_power() { + when : "A_MEN"; + rise_power("scalar"){ + values (0.0400); + } + fall_power("scalar"){ + values (0.0357); + } + } + internal_power() { + when : "!A_MEN"; + rise_power("scalar"){ + values (0.0592); + } + fall_power("scalar"){ + values (0.0441); + } + } + } + timing() { + timing_type : setup_rising; + related_pin : "A_CLK"; + when : "(A_WEN & A_MEN)"; + sdf_cond : "A_W_ACCESS"; + + rise_constraint("SIG2SRAM_constraint_template") { + index_1("0.0040,0.0176,0.0344,0.0656,0.1120,0.2016,0.3800"); + index_2("0.0040,0.0176,0.0344,0.0656,0.1120,0.2016,0.3800"); + values ("-0.1725,-0.1618,-0.1462,-0.1208,-0.0798,-0.0065,0.1282",\ +"-0.1764,-0.1657,-0.1501,-0.1247,-0.0836,-0.0104,0.1244",\ +"-0.1802,-0.1695,-0.1539,-0.1285,-0.0874,-0.0142,0.1206",\ +"-0.1835,-0.1727,-0.1571,-0.1317,-0.0907,-0.0175,0.1173",\ +"-0.1959,-0.1852,-0.1695,-0.1442,-0.1031,-0.0299,0.1049",\ +"-0.2135,-0.2028,-0.1872,-0.1618,-0.1208,-0.0475,0.0872",\ +"-0.2410,-0.2303,-0.2147,-0.1893,-0.1483,-0.0750,0.0597"); + } + + fall_constraint("SIG2SRAM_constraint_template") { + index_1("0.0040,0.0176,0.0344,0.0656,0.1120,0.2016,0.3800"); + index_2("0.0040,0.0176,0.0344,0.0656,0.1120,0.2016,0.3800"); + values ("-0.1491,-0.1374,-0.1247,-0.0973,-0.0602,0.0130,0.1409",\ +"-0.1530,-0.1413,-0.1286,-0.1012,-0.0641,0.0091,0.1370",\ +"-0.1568,-0.1451,-0.1324,-0.1050,-0.0679,0.0053,0.1333",\ +"-0.1600,-0.1483,-0.1356,-0.1083,-0.0712,0.0021,0.1300",\ +"-0.1725,-0.1608,-0.1481,-0.1207,-0.0836,-0.0104,0.1176",\ +"-0.1901,-0.1784,-0.1657,-0.1383,-0.1012,-0.0280,0.0999",\ +"-0.2176,-0.2059,-0.1932,-0.1658,-0.1287,-0.0555,0.0724"); + } + } + + timing() { + timing_type : hold_rising; + related_pin : "A_CLK"; + when : "(A_WEN & A_MEN)"; + sdf_cond : "A_W_ACCESS"; + + rise_constraint("SIG2SRAM_constraint_template") { + index_1("0.0040,0.0176,0.0344,0.0656,0.1120,0.2016,0.3800"); + index_2("0.0040,0.0176,0.0344,0.0656,0.1120,0.2016,0.3800"); + values ("0.2776,0.2678,0.2522,0.2259,0.1887,0.1145,-0.0202",\ +"0.2815,0.2717,0.2561,0.2297,0.1926,0.1184,-0.0164",\ +"0.2853,0.2755,0.2599,0.2335,0.1964,0.1222,-0.0126",\ +"0.2885,0.2788,0.2632,0.2368,0.1997,0.1255,-0.0093",\ +"0.3010,0.2912,0.2756,0.2492,0.2121,0.1379,0.0031",\ +"0.3186,0.3088,0.2932,0.2668,0.2297,0.1555,0.0208",\ +"0.3461,0.3363,0.3207,0.2944,0.2572,0.1830,0.0483"); + } + + fall_constraint("SIG2SRAM_constraint_template") { + index_1("0.0040,0.0176,0.0344,0.0656,0.1120,0.2016,0.3800"); + index_2("0.0040,0.0176,0.0344,0.0656,0.1120,0.2016,0.3800"); + values ("0.2493,0.2385,0.2249,0.1975,0.1614,0.0891,-0.0407",\ +"0.2532,0.2424,0.2288,0.2014,0.1653,0.0930,-0.0369",\ +"0.2570,0.2462,0.2326,0.2052,0.1691,0.0968,-0.0331",\ +"0.2602,0.2495,0.2358,0.2085,0.1723,0.1001,-0.0298",\ +"0.2727,0.2619,0.2483,0.2209,0.1848,0.1125,-0.0174",\ +"0.2903,0.2795,0.2659,0.2385,0.2024,0.1301,0.0002",\ +"0.3178,0.3070,0.2934,0.2660,0.2299,0.1576,0.0278"); + } + } + } + + pin(A_BIST_EN) { + direction : input ; + capacitance : 0.00421562 ; + max_transition : "1" ; + related_power_pin : VDD; + related_ground_pin : VSS; + internal_power() { + rise_power("scalar") { + values (0); + } + fall_power("scalar") { + values (0); + } + } + } + +bus(A_BIST_ADDR) { + bus_type : A_8_0; + direction : input ; + capacitance : 0.0115194 ; + pin(A_BIST_ADDR[0]) { + capacitance : 0.00563454 ; + } + pin(A_BIST_ADDR[1]) { + capacitance : 0.00744185 ; + } + pin(A_BIST_ADDR[2]) { + capacitance : 0.0100611 ; + } + pin(A_BIST_ADDR[3]) { + capacitance : 0.00669965 ; + } + pin(A_BIST_ADDR[4]) { + capacitance : 0.00614331 ; + } + pin(A_BIST_ADDR[5]) { + capacitance : 0.0102172 ; + } + pin(A_BIST_ADDR[6]) { + capacitance : 0.0124225 ; + } + pin(A_BIST_ADDR[7]) { + capacitance : 0.010114 ; + } + max_transition : "0.38" ; + pin(A_BIST_ADDR[8:0]) { + related_power_pin : VDD; + related_ground_pin : VSS; + internal_power() { + when : "A_BIST_MEN"; + rise_power("scalar"){ + values (0.0129); + } + fall_power("scalar"){ + values (0.0027); + } + } + internal_power() { + when : "!A_BIST_MEN"; + rise_power("scalar"){ + values (0.0261); + } + fall_power("scalar"){ + values (0.0017); + } + } + } + timing() { + timing_type : setup_rising; + related_pin : "A_BIST_CLK"; + when : "((A_BIST_WEN | A_BIST_REN)& A_BIST_MEN)" + sdf_cond : "A_BIST_RW_ACCESS" + + rise_constraint("SIG2SRAM_constraint_template") { + index_1("0.0040,0.0176,0.0344,0.0656,0.1120,0.2016,0.3800"); + index_2("0.0040,0.0176,0.0344,0.0656,0.1120,0.2016,0.3800"); + values ("-0.2371,-0.2215,-0.2098,-0.1824,-0.1434,-0.0691,0.0676",\ +"-0.2449,-0.2332,-0.2176,-0.1902,-0.1551,-0.0770,0.0559",\ +"-0.2605,-0.2488,-0.2332,-0.2059,-0.1707,-0.0965,0.0441",\ +"-0.2879,-0.2723,-0.2605,-0.2332,-0.1941,-0.1199,0.0168",\ +"-0.3230,-0.3113,-0.2996,-0.2723,-0.2332,-0.1590,-0.0184",\ +"-0.4012,-0.3895,-0.3738,-0.3465,-0.3074,-0.2332,-0.0965",\ +"-0.5379,-0.5262,-0.5105,-0.4832,-0.4480,-0.3699,-0.2332"); + } + + fall_constraint("SIG2SRAM_constraint_template") { + index_1("0.0040,0.0176,0.0344,0.0656,0.1120,0.2016,0.3800"); + index_2("0.0040,0.0176,0.0344,0.0656,0.1120,0.2016,0.3800"); + values ("-0.1785,-0.1707,-0.1551,-0.1277,-0.0887,-0.0184,0.1145",\ +"-0.1902,-0.1785,-0.1629,-0.1355,-0.1004,-0.0262,0.1027",\ +"-0.2059,-0.1941,-0.1785,-0.1512,-0.1160,-0.0418,0.0871",\ +"-0.2293,-0.2176,-0.2059,-0.1785,-0.1434,-0.0691,0.0598",\ +"-0.2684,-0.2566,-0.2449,-0.2176,-0.1824,-0.1082,0.0207",\ +"-0.3465,-0.3348,-0.3191,-0.2918,-0.2566,-0.1824,-0.0535",\ +"-0.4832,-0.4715,-0.4559,-0.4324,-0.3934,-0.3191,-0.1902"); + } + } + + + timing() { + timing_type : hold_rising; + related_pin : "A_BIST_CLK"; + when : "((A_BIST_WEN | A_BIST_REN)& A_BIST_MEN)" + sdf_cond : "A_BIST_RW_ACCESS" + + rise_constraint("SIG2SRAM_constraint_template") { + index_1("0.0040,0.0176,0.0344,0.0656,0.1120,0.2016,0.3800"); + index_2("0.0040,0.0176,0.0344,0.0656,0.1120,0.2016,0.3800"); + values ("0.3410,0.3293,0.3137,0.2863,0.2473,0.1730,0.0324",\ +"0.3488,0.3371,0.3215,0.2941,0.2590,0.1809,0.0480",\ +"0.3684,0.3527,0.3371,0.3098,0.2746,0.1965,0.0598",\ +"0.3918,0.3762,0.3645,0.3371,0.2980,0.2238,0.0871",\ +"0.4309,0.4152,0.4035,0.3762,0.3371,0.2629,0.1223",\ +"0.5051,0.4934,0.4777,0.4504,0.4113,0.3371,0.1965",\ +"0.6418,0.6262,0.6145,0.5871,0.5520,0.4738,0.3332"); + } + + fall_constraint("SIG2SRAM_constraint_template") { + index_1("0.0040,0.0176,0.0344,0.0656,0.1120,0.2016,0.3800"); + index_2("0.0040,0.0176,0.0344,0.0656,0.1120,0.2016,0.3800"); + values ("0.2824,0.2707,0.2551,0.2277,0.1926,0.1184,-0.0105",\ +"0.2902,0.2785,0.2668,0.2395,0.2043,0.1301,0.0012",\ +"0.3059,0.2941,0.2824,0.2551,0.2199,0.1457,0.0168",\ +"0.3332,0.3215,0.3059,0.2785,0.2434,0.1691,0.0402",\ +"0.3723,0.3605,0.3449,0.3176,0.2824,0.2121,0.0793",\ +"0.4465,0.4348,0.4230,0.3918,0.3566,0.2824,0.1535",\ +"0.5832,0.5715,0.5598,0.5324,0.4934,0.4191,0.2902"); + } + } +} +pin(A_BIST_WEN) { + direction : input ; + capacitance : 0.00341384 ; + max_transition : "0.38" ; + related_power_pin : VDD; + related_ground_pin : VSS; + internal_power() { + when : "A_BIST_MEN"; + rise_power("scalar"){ + values (0.0072); + } + fall_power("scalar"){ + values (0.0153); + } + } + internal_power() { + when : "!A_BIST_MEN"; + rise_power("scalar"){ + values (0.0059); + } + fall_power("scalar"){ + values (0.0232); + } + } + timing() { + timing_type : setup_rising; + related_pin : "A_BIST_CLK"; + when : "A_BIST_MEN" + sdf_cond : "A_BIST_MEN" + + rise_constraint("SIG2SRAM_constraint_template") { + index_1("0.0040,0.0176,0.0344,0.0656,0.1120,0.2016,0.3800"); + index_2("0.0040,0.0176,0.0344,0.0656,0.1120,0.2016,0.3800"); + values ("0.1418,0.1496,0.1652,0.1887,0.2316,0.3059,0.4465",\ +"0.1301,0.1379,0.1535,0.1809,0.2199,0.2941,0.4348",\ +"0.1145,0.1262,0.1379,0.1652,0.2043,0.2785,0.4191",\ +"0.0871,0.0949,0.1105,0.1379,0.1770,0.2512,0.3879",\ +"0.0480,0.0598,0.0754,0.0988,0.1379,0.2082,0.3527",\ +"-0.0262,-0.0145,0.0012,0.0246,0.0676,0.1379,0.2785",\ +"-0.1668,-0.1551,-0.1395,-0.1121,-0.0730,0.0012,0.1418"); + } + + fall_constraint("SIG2SRAM_constraint_template") { + index_1("0.0040,0.0176,0.0344,0.0656,0.1120,0.2016,0.3800"); + index_2("0.0040,0.0176,0.0344,0.0656,0.1120,0.2016,0.3800"); + values ("0.2082,0.2160,0.2316,0.2590,0.2941,0.3684,0.5012",\ +"0.1926,0.2043,0.2199,0.2473,0.2824,0.3566,0.4895",\ +"0.1770,0.1887,0.2043,0.2316,0.2668,0.3410,0.4777",\ +"0.1535,0.1652,0.1770,0.2043,0.2395,0.3137,0.4504",\ +"0.1145,0.1262,0.1379,0.1652,0.2043,0.2746,0.4113",\ +"0.0402,0.0520,0.0676,0.0910,0.1262,0.2004,0.3332",\ +"-0.0965,-0.0848,-0.0730,-0.0457,-0.0066,0.0637,0.2004"); + } + } + + + timing() { + timing_type : hold_rising; + related_pin : "A_BIST_CLK"; + when : "A_BIST_MEN" + sdf_cond : "A_BIST_MEN" + + rise_constraint("SIG2SRAM_constraint_template") { + index_1("0.0040,0.0176,0.0344,0.0656,0.1120,0.2016,0.3800"); + index_2("0.0040,0.0176,0.0344,0.0656,0.1120,0.2016,0.3800"); + values ("0.1770,0.1652,0.1496,0.1223,0.0793,0.0090,-0.1316",\ +"0.1848,0.1730,0.1574,0.1301,0.0910,0.0168,-0.1199",\ +"0.2004,0.1887,0.1770,0.1496,0.1066,0.0363,-0.1043",\ +"0.2277,0.2160,0.2004,0.1730,0.1340,0.0598,-0.0809",\ +"0.2668,0.2551,0.2395,0.2121,0.1730,0.0988,-0.0418",\ +"0.3410,0.3293,0.3137,0.2863,0.2434,0.1730,0.0324",\ +"0.4816,0.4699,0.4543,0.4230,0.3801,0.3098,0.1730"); + } + + fall_constraint("SIG2SRAM_constraint_template") { + index_1("0.0040,0.0176,0.0344,0.0656,0.1120,0.2016,0.3800"); + index_2("0.0040,0.0176,0.0344,0.0656,0.1120,0.2016,0.3800"); + values ("0.1613,0.1496,0.1379,0.1066,0.0715,0.0012,-0.1355",\ +"0.1730,0.1613,0.1457,0.1184,0.0832,0.0129,-0.1238",\ +"0.1887,0.1770,0.1613,0.1340,0.0988,0.0246,-0.1121",\ +"0.2121,0.2043,0.1887,0.1613,0.1223,0.0520,-0.0848",\ +"0.2512,0.2434,0.2277,0.2004,0.1613,0.0910,-0.0457",\ +"0.3254,0.3176,0.3020,0.2746,0.2355,0.1652,0.0324",\ +"0.4660,0.4543,0.4387,0.4113,0.3723,0.3020,0.1691"); + } + } + } +pin(A_BIST_REN) { + direction : input ; + capacitance : 0.00390661 ; + max_transition : "0.38" ; + related_power_pin : VDD; + related_ground_pin : VSS; + internal_power() { + when : "A_BIST_MEN"; + rise_power("scalar"){ + values (0.0097); + } + fall_power("scalar"){ + values (0.0114); + } + } + internal_power() { + when : "!A_BIST_MEN"; + rise_power("scalar"){ + values (0.0259); + } + fall_power("scalar"){ + values (0.0195); + } + } + timing() { + timing_type : setup_rising; + related_pin : "A_BIST_CLK"; + when : "A_BIST_MEN" + sdf_cond : "A_BIST_MEN" + + rise_constraint("SIG2SRAM_constraint_template") { + index_1("0.0040,0.0176,0.0344,0.0656,0.1120,0.2016,0.3800"); + index_2("0.0040,0.0176,0.0344,0.0656,0.1120,0.2016,0.3800"); + values ("-0.0027,0.0090,0.0246,0.0520,0.0910,0.1613,0.3020",\ +"-0.0105,0.0012,0.0129,0.0363,0.0793,0.1535,0.2902",\ +"-0.0262,-0.0145,-0.0027,0.0246,0.0637,0.1379,0.2785",\ +"-0.0535,-0.0418,-0.0262,0.0012,0.0363,0.1105,0.2512",\ +"-0.0926,-0.0809,-0.0652,-0.0418,-0.0027,0.0715,0.2121",\ +"-0.1668,-0.1551,-0.1395,-0.1082,-0.0770,-0.0027,0.1379",\ +"-0.3035,-0.2918,-0.2762,-0.2488,-0.2137,-0.1434,-0.0027"); + } + + fall_constraint("SIG2SRAM_constraint_template") { + index_1("0.0040,0.0176,0.0344,0.0656,0.1120,0.2016,0.3800"); + index_2("0.0040,0.0176,0.0344,0.0656,0.1120,0.2016,0.3800"); + values ("0.0832,0.0949,0.1105,0.1379,0.1730,0.2473,0.3801",\ +"0.0754,0.0832,0.0988,0.1223,0.1613,0.2355,0.3684",\ +"0.0598,0.0676,0.0832,0.1066,0.1457,0.2121,0.3527",\ +"0.0324,0.0441,0.0598,0.0871,0.1223,0.1926,0.3293",\ +"-0.0066,0.0051,0.0168,0.0480,0.0832,0.1535,0.2902",\ +"-0.0809,-0.0691,-0.0574,-0.0301,0.0090,0.0832,0.2121",\ +"-0.2176,-0.2059,-0.1941,-0.1668,-0.1277,-0.0574,0.0793"); + } + } + + + timing() { + timing_type : hold_rising; + related_pin : "A_BIST_CLK"; + when : "A_BIST_MEN" + sdf_cond : "A_BIST_MEN" + + rise_constraint("SIG2SRAM_constraint_template") { + index_1("0.0040,0.0176,0.0344,0.0656,0.1120,0.2016,0.3800"); + index_2("0.0040,0.0176,0.0344,0.0656,0.1120,0.2016,0.3800"); + values ("0.1887,0.1770,0.1613,0.1340,0.0949,0.0207,-0.1160",\ +"0.1965,0.1848,0.1730,0.1457,0.1027,0.0324,-0.1082",\ +"0.2160,0.2004,0.1887,0.1613,0.1184,0.0480,-0.0926",\ +"0.2395,0.2277,0.2121,0.1848,0.1457,0.0715,-0.0652",\ +"0.2785,0.2668,0.2512,0.2238,0.1848,0.1105,-0.0262",\ +"0.3527,0.3410,0.3254,0.2980,0.2551,0.1848,0.0480",\ +"0.4934,0.4816,0.4660,0.4387,0.3957,0.3254,0.1887"); + } + + fall_constraint("SIG2SRAM_constraint_template") { + index_1("0.0040,0.0176,0.0344,0.0656,0.1120,0.2016,0.3800"); + index_2("0.0040,0.0176,0.0344,0.0656,0.1120,0.2016,0.3800"); + values ("0.1730,0.1613,0.1496,0.1184,0.0793,0.0129,-0.1238",\ +"0.1848,0.1730,0.1574,0.1301,0.0910,0.0207,-0.1121",\ +"0.2004,0.1887,0.1730,0.1457,0.1066,0.0363,-0.1004",\ +"0.2238,0.2121,0.2004,0.1691,0.1340,0.0598,-0.0730",\ +"0.2629,0.2512,0.2395,0.2121,0.1691,0.0988,-0.0340",\ +"0.3371,0.3254,0.3137,0.2863,0.2434,0.1730,0.0402",\ +"0.4777,0.4660,0.4504,0.4230,0.3840,0.3137,0.1809"); + } + } + } +pin(A_BIST_MEN) { + direction : input ; + capacitance : 0.00326046 ; + max_transition : "0.38" ; + related_power_pin : VDD; + related_ground_pin : VSS; + internal_power() { + rise_power("scalar"){ + values (0.0831); + } + fall_power("scalar"){ + values (0.0107); + } + } + timing() { + timing_type : setup_rising; + related_pin : "A_BIST_CLK"; + + rise_constraint("SIG2SRAM_constraint_template") { + index_1("0.0040,0.0176,0.0344,0.0656,0.1120,0.2016,0.3800"); + index_2("0.0040,0.0176,0.0344,0.0656,0.1120,0.2016,0.3800"); + values ("0.1418,0.1496,0.1652,0.1926,0.2316,0.3059,0.4465",\ +"0.1301,0.1379,0.1535,0.1809,0.2199,0.2941,0.4348",\ +"0.1145,0.1262,0.1418,0.1652,0.2043,0.2785,0.4191",\ +"0.0871,0.0949,0.1105,0.1379,0.1770,0.2512,0.3879",\ +"0.0480,0.0598,0.0754,0.0988,0.1379,0.2082,0.3488",\ +"-0.0262,-0.0145,0.0012,0.0285,0.0676,0.1379,0.2785",\ +"-0.1668,-0.1551,-0.1395,-0.1121,-0.0730,0.0012,0.1379"); + } + + fall_constraint("SIG2SRAM_constraint_template") { + index_1("0.0040,0.0176,0.0344,0.0656,0.1120,0.2016,0.3800"); + index_2("0.0040,0.0176,0.0344,0.0656,0.1120,0.2016,0.3800"); + values ("0.2082,0.2199,0.2316,0.2590,0.2980,0.3723,0.5051",\ +"0.1965,0.2082,0.2199,0.2473,0.2863,0.3605,0.4934",\ +"0.1809,0.1926,0.2043,0.2316,0.2707,0.3449,0.4777",\ +"0.1574,0.1691,0.1809,0.2082,0.2434,0.3176,0.4543",\ +"0.1145,0.1262,0.1418,0.1691,0.2043,0.2785,0.4113",\ +"0.0441,0.0559,0.0676,0.0949,0.1301,0.2004,0.3332",\ +"-0.0965,-0.0848,-0.0691,-0.0418,-0.0066,0.0676,0.2004"); + } + } + + + timing() { + timing_type : hold_rising; + related_pin : "A_BIST_CLK"; + + rise_constraint("SIG2SRAM_constraint_template") { + index_1("0.0040,0.0176,0.0344,0.0656,0.1120,0.2016,0.3800"); + index_2("0.0040,0.0176,0.0344,0.0656,0.1120,0.2016,0.3800"); + values ("0.1770,0.1652,0.1535,0.1262,0.0832,0.0129,-0.1277",\ +"0.1887,0.1770,0.1613,0.1340,0.0949,0.0207,-0.1199",\ +"0.2043,0.1926,0.1770,0.1496,0.1105,0.0363,-0.1043",\ +"0.2277,0.2160,0.2043,0.1770,0.1379,0.0598,-0.0770",\ +"0.2668,0.2551,0.2434,0.2160,0.1730,0.0988,-0.0379",\ +"0.3449,0.3332,0.3176,0.2902,0.2473,0.1730,0.0363",\ +"0.4816,0.4699,0.4543,0.4270,0.3840,0.3098,0.1770"); + } + + fall_constraint("SIG2SRAM_constraint_template") { + index_1("0.0040,0.0176,0.0344,0.0656,0.1120,0.2016,0.3800"); + index_2("0.0040,0.0176,0.0344,0.0656,0.1120,0.2016,0.3800"); + values ("0.1613,0.1496,0.1379,0.1105,0.0715,0.0012,-0.1355",\ +"0.1730,0.1613,0.1496,0.1184,0.0832,0.0129,-0.1238",\ +"0.1887,0.1770,0.1652,0.1340,0.0988,0.0285,-0.1121",\ +"0.2121,0.2043,0.1887,0.1613,0.1223,0.0520,-0.0848",\ +"0.2551,0.2434,0.2277,0.2004,0.1613,0.0910,-0.0418",\ +"0.3293,0.3176,0.3020,0.2746,0.2395,0.1652,0.0324",\ +"0.4660,0.4543,0.4426,0.4113,0.3762,0.3020,0.1691"); + } + } + } +bus(A_BIST_BM) { + bus_type : D_7_0; + direction : input ; + capacitance : 0.00353394 ; + max_transition : "0.38" ; + pin(A_BIST_BM[7:0]) { + related_power_pin : VDD; + related_ground_pin : VSS; + internal_power() { + when : "A_BIST_MEN"; + rise_power("scalar"){ + values (0.0400); + } + fall_power("scalar"){ + values (0.0357); + } + } + internal_power() { + when : "!A_BIST_MEN"; + rise_power("scalar"){ + values (0.0592); + } + fall_power("scalar"){ + values (0.0441); + } + } + } + timing() { + timing_type : setup_rising; + related_pin : "A_BIST_CLK"; + when : "(A_BIST_WEN & A_BIST_MEN)" + sdf_cond : "A_BIST_RW_ACCESS" + + rise_constraint("SIG2SRAM_constraint_template") { + index_1("0.0040,0.0176,0.0344,0.0656,0.1120,0.2016,0.3800"); + index_2("0.0040,0.0176,0.0344,0.0656,0.1120,0.2016,0.3800"); + values ("-0.1725,-0.1618,-0.1462,-0.1208,-0.0798,-0.0065,0.1282",\ +"-0.1764,-0.1657,-0.1501,-0.1247,-0.0836,-0.0104,0.1244",\ +"-0.1802,-0.1695,-0.1539,-0.1285,-0.0874,-0.0142,0.1206",\ +"-0.1835,-0.1727,-0.1571,-0.1317,-0.0907,-0.0175,0.1173",\ +"-0.1959,-0.1852,-0.1695,-0.1442,-0.1031,-0.0299,0.1049",\ +"-0.2135,-0.2028,-0.1872,-0.1618,-0.1208,-0.0475,0.0872",\ +"-0.2410,-0.2303,-0.2147,-0.1893,-0.1483,-0.0750,0.0597"); + } + + fall_constraint("SIG2SRAM_constraint_template") { + index_1("0.0040,0.0176,0.0344,0.0656,0.1120,0.2016,0.3800"); + index_2("0.0040,0.0176,0.0344,0.0656,0.1120,0.2016,0.3800"); + values ("-0.1491,-0.1374,-0.1247,-0.0973,-0.0602,0.0130,0.1409",\ +"-0.1530,-0.1413,-0.1286,-0.1012,-0.0641,0.0091,0.1370",\ +"-0.1568,-0.1451,-0.1324,-0.1050,-0.0679,0.0053,0.1333",\ +"-0.1600,-0.1483,-0.1356,-0.1083,-0.0712,0.0021,0.1300",\ +"-0.1725,-0.1608,-0.1481,-0.1207,-0.0836,-0.0104,0.1176",\ +"-0.1901,-0.1784,-0.1657,-0.1383,-0.1012,-0.0280,0.0999",\ +"-0.2176,-0.2059,-0.1932,-0.1658,-0.1287,-0.0555,0.0724"); + } + } + + + timing() { + timing_type : hold_rising; + related_pin : "A_BIST_CLK"; + when : "(A_BIST_WEN & A_BIST_MEN)" + sdf_cond : "A_BIST_RW_ACCESS" + + rise_constraint("SIG2SRAM_constraint_template") { + index_1("0.0040,0.0176,0.0344,0.0656,0.1120,0.2016,0.3800"); + index_2("0.0040,0.0176,0.0344,0.0656,0.1120,0.2016,0.3800"); + values ("0.2776,0.2678,0.2522,0.2259,0.1887,0.1145,-0.0202",\ +"0.2815,0.2717,0.2561,0.2297,0.1926,0.1184,-0.0164",\ +"0.2853,0.2755,0.2599,0.2335,0.1964,0.1222,-0.0126",\ +"0.2885,0.2788,0.2632,0.2368,0.1997,0.1255,-0.0093",\ +"0.3010,0.2912,0.2756,0.2492,0.2121,0.1379,0.0031",\ +"0.3186,0.3088,0.2932,0.2668,0.2297,0.1555,0.0208",\ +"0.3461,0.3363,0.3207,0.2944,0.2572,0.1830,0.0483"); + } + + fall_constraint("SIG2SRAM_constraint_template") { + index_1("0.0040,0.0176,0.0344,0.0656,0.1120,0.2016,0.3800"); + index_2("0.0040,0.0176,0.0344,0.0656,0.1120,0.2016,0.3800"); + values ("0.2493,0.2385,0.2249,0.1975,0.1614,0.0891,-0.0407",\ +"0.2532,0.2424,0.2288,0.2014,0.1653,0.0930,-0.0369",\ +"0.2570,0.2462,0.2326,0.2052,0.1691,0.0968,-0.0331",\ +"0.2602,0.2495,0.2358,0.2085,0.1723,0.1001,-0.0298",\ +"0.2727,0.2619,0.2483,0.2209,0.1848,0.1125,-0.0174",\ +"0.2903,0.2795,0.2659,0.2385,0.2024,0.1301,0.0002",\ +"0.3178,0.3070,0.2934,0.2660,0.2299,0.1576,0.0278"); + } + } +} + pin(A_BIST_CLK) { + direction : input; + capacitance : 0.00389386; + max_transition : "0.38"; + clock : "true" ; + pin_func_type : active_rising ; + + timing () { + timing_type : "min_pulse_width"; + related_pin : "A_BIST_CLK"; + rise_constraint("CLKTRAN_constraint_template") { + index_1("0.004,0.38"); + values("0.12,0.12"); + } + } + + related_power_pin : VDD; + related_ground_pin : VSS; + + internal_power() { + when : "!A_BIST_MEN & !A_BIST_WEN & !A_BIST_REN"; + rise_power("scalar"){ + values (0); + } + fall_power("scalar"){ + values (0); + } + } + internal_power() { + when : "!A_BIST_MEN & A_BIST_WEN & !A_BIST_REN"; + rise_power("scalar"){ + values (0.6678); + } + fall_power("scalar"){ + values (0); + } + } + internal_power() { + when : "A_BIST_MEN & A_BIST_WEN & !A_BIST_REN"; + rise_power("scalar"){ + values (17.5281); + } + fall_power("scalar"){ + values (0); + } + } + internal_power() { + when : "A_BIST_MEN & A_BIST_WEN & A_BIST_REN"; + rise_power("scalar"){ + values (17.8148); + } + fall_power("scalar"){ + values (0); + } + } + internal_power() { + when : "A_BIST_MEN & !A_BIST_WEN & A_BIST_REN"; + rise_power("scalar"){ + values (14.1173); + } + fall_power("scalar"){ + values (0); + } + } + internal_power() { + when : "!A_BIST_MEN & !A_BIST_WEN & A_BIST_REN"; + rise_power("scalar"){ + values (0.3934); + } + fall_power("scalar"){ + values (0); + } + } + internal_power() { + when : "!A_BIST_MEN & A_BIST_WEN & A_BIST_REN"; + rise_power("scalar"){ + values (0.6886); + } + fall_power("scalar"){ + values (0); + } + } + internal_power() { + when : "A_BIST_MEN & !A_BIST_WEN & !A_BIST_REN"; + rise_power("scalar"){ + values (0); + } + fall_power("scalar"){ + values (0); + } + } + } + bus(A_BIST_DIN) { + bus_type : D_7_0; + direction : input ; + capacitance : 0.00397186 ; + memory_write() { + address : A_BIST_ADDR ; + clocked_on : A_BIST_CLK; + } + + max_transition : "0.38" ; + pin(A_BIST_DIN[7:0]) { + related_power_pin : VDD; + related_ground_pin : VSS; + internal_power() { + when : "A_BIST_MEN"; + rise_power("scalar"){ + values (0.0400); + } + fall_power("scalar"){ + values (0.0357); + } + } + internal_power() { + when : "!A_BIST_MEN"; + rise_power("scalar"){ + values (0.0592); + } + fall_power("scalar"){ + values (0.0441); + } + } + } + timing() { + timing_type : setup_rising; + related_pin : "A_BIST_CLK"; + when : "(A_BIST_WEN & A_BIST_MEN)"; + sdf_cond : "A_BIST_W_ACCESS"; + + rise_constraint("SIG2SRAM_constraint_template") { + index_1("0.0040,0.0176,0.0344,0.0656,0.1120,0.2016,0.3800"); + index_2("0.0040,0.0176,0.0344,0.0656,0.1120,0.2016,0.3800"); + values ("-0.1725,-0.1618,-0.1462,-0.1208,-0.0798,-0.0065,0.1282",\ +"-0.1764,-0.1657,-0.1501,-0.1247,-0.0836,-0.0104,0.1244",\ +"-0.1802,-0.1695,-0.1539,-0.1285,-0.0874,-0.0142,0.1206",\ +"-0.1835,-0.1727,-0.1571,-0.1317,-0.0907,-0.0175,0.1173",\ +"-0.1959,-0.1852,-0.1695,-0.1442,-0.1031,-0.0299,0.1049",\ +"-0.2135,-0.2028,-0.1872,-0.1618,-0.1208,-0.0475,0.0872",\ +"-0.2410,-0.2303,-0.2147,-0.1893,-0.1483,-0.0750,0.0597"); + } + + fall_constraint("SIG2SRAM_constraint_template") { + index_1("0.0040,0.0176,0.0344,0.0656,0.1120,0.2016,0.3800"); + index_2("0.0040,0.0176,0.0344,0.0656,0.1120,0.2016,0.3800"); + values ("-0.1491,-0.1374,-0.1247,-0.0973,-0.0602,0.0130,0.1409",\ +"-0.1530,-0.1413,-0.1286,-0.1012,-0.0641,0.0091,0.1370",\ +"-0.1568,-0.1451,-0.1324,-0.1050,-0.0679,0.0053,0.1333",\ +"-0.1600,-0.1483,-0.1356,-0.1083,-0.0712,0.0021,0.1300",\ +"-0.1725,-0.1608,-0.1481,-0.1207,-0.0836,-0.0104,0.1176",\ +"-0.1901,-0.1784,-0.1657,-0.1383,-0.1012,-0.0280,0.0999",\ +"-0.2176,-0.2059,-0.1932,-0.1658,-0.1287,-0.0555,0.0724"); + } + } + + timing() { + timing_type : hold_rising; + related_pin : "A_BIST_CLK"; + when : "(A_BIST_WEN & A_BIST_MEN)"; + sdf_cond : "A_BIST_W_ACCESS"; + + rise_constraint("SIG2SRAM_constraint_template") { + index_1("0.0040,0.0176,0.0344,0.0656,0.1120,0.2016,0.3800"); + index_2("0.0040,0.0176,0.0344,0.0656,0.1120,0.2016,0.3800"); + values ("0.2776,0.2678,0.2522,0.2259,0.1887,0.1145,-0.0202",\ +"0.2815,0.2717,0.2561,0.2297,0.1926,0.1184,-0.0164",\ +"0.2853,0.2755,0.2599,0.2335,0.1964,0.1222,-0.0126",\ +"0.2885,0.2788,0.2632,0.2368,0.1997,0.1255,-0.0093",\ +"0.3010,0.2912,0.2756,0.2492,0.2121,0.1379,0.0031",\ +"0.3186,0.3088,0.2932,0.2668,0.2297,0.1555,0.0208",\ +"0.3461,0.3363,0.3207,0.2944,0.2572,0.1830,0.0483"); + } + + fall_constraint("SIG2SRAM_constraint_template") { + index_1("0.0040,0.0176,0.0344,0.0656,0.1120,0.2016,0.3800"); + index_2("0.0040,0.0176,0.0344,0.0656,0.1120,0.2016,0.3800"); + values ("0.2493,0.2385,0.2249,0.1975,0.1614,0.0891,-0.0407",\ +"0.2532,0.2424,0.2288,0.2014,0.1653,0.0930,-0.0369",\ +"0.2570,0.2462,0.2326,0.2052,0.1691,0.0968,-0.0331",\ +"0.2602,0.2495,0.2358,0.2085,0.1723,0.1001,-0.0298",\ +"0.2727,0.2619,0.2483,0.2209,0.1848,0.1125,-0.0174",\ +"0.2903,0.2795,0.2659,0.2385,0.2024,0.1301,0.0002",\ +"0.3178,0.3070,0.2934,0.2660,0.2299,0.1576,0.0278"); + } + } + } + +bus(A_DOUT) { + + bus_type : D_7_0; + direction : output ; + capacitance : 0 ; + max_capacitance : 0.064 ; + memory_read() { + address : A_ADDR ; + } + pin(A_DOUT[7:0]) { + related_power_pin : VDD; + related_ground_pin : VSS; + internal_power() { + rise_power("scalar") { + values (0); + } + fall_power("scalar") { + values (0); + } + } + } + timing() { + related_pin : "A_CLK"; + timing_type : rising_edge ; + timing_sense : non_unate ; + + cell_rise(SIG2SRAM_delay_template) { + index_1("0.0040,0.0176,0.0344,0.0656,0.1120,0.2016,0.3800"); + index_2("0.0008,0.0014,0.0051,0.0100,0.0339,0.0640"); + values ("2.2905,2.2915,2.2963,2.3018,2.3227,2.3462",\ +"2.2969,2.2979,2.3027,2.3082,2.3291,2.3526",\ +"2.2985,2.2995,2.3043,2.3098,2.3307,2.3542",\ +"2.3028,2.3038,2.3086,2.3141,2.3351,2.3586",\ +"2.3160,2.3170,2.3218,2.3273,2.3482,2.3717",\ +"2.3345,2.3355,2.3403,2.3459,2.3668,2.3903",\ +"2.3610,2.3621,2.3669,2.3724,2.3933,2.4168"); + } + cell_fall(SIG2SRAM_delay_template) { + index_1("0.0040,0.0176,0.0344,0.0656,0.1120,0.2016,0.3800"); + index_2("0.0008,0.0014,0.0051,0.0100,0.0339,0.0640"); + values ("2.2562,2.2571,2.2611,2.2656,2.2827,2.2995",\ +"2.2626,2.2634,2.2675,2.2720,2.2891,2.3058",\ +"2.2642,2.2650,2.2691,2.2736,2.2907,2.3074",\ +"2.2685,2.2694,2.2734,2.2780,2.2950,2.3118",\ +"2.2817,2.2825,2.2866,2.2911,2.3082,2.3249",\ +"2.3002,2.3011,2.3051,2.3097,2.3268,2.3435",\ +"2.3268,2.3276,2.3317,2.3362,2.3533,2.3700"); + } + + rise_transition(SRAM_load_template) { + index_1("0.0008,0.0014,0.0051,0.0100,0.0339,0.0640"); + values ("0.0206,0.0210,0.0265,0.0323,0.0606,0.0955"); + } + fall_transition(SRAM_load_template) { + index_1("0.0008,0.0014,0.0051,0.0100,0.0339,0.0640"); + values ("0.0170,0.0177,0.0222,0.0270,0.0451,0.0644"); + } + } +} + pin(B_DLY) { + direction : input ; + capacitance : 0.00421562 ; + max_transition : "1" ; + related_power_pin : VDD; + related_ground_pin : VSS; + internal_power() { + rise_power("scalar") { + values (0); + } + fall_power("scalar") { + values (0); + } + } + } + +bus(B_ADDR) { + bus_type : A_8_0; + direction : input ; + capacitance : 0.0115194 ; + pin(B_ADDR[0]) { + capacitance : 0.0056487 ; + } + pin(B_ADDR[1]) { + capacitance : 0.00741688 ; + } + pin(B_ADDR[2]) { + capacitance : 0.0100613 ; + } + pin(B_ADDR[3]) { + capacitance : 0.00667339 ; + } + pin(B_ADDR[4]) { + capacitance : 0.00620204 ; + } + pin(B_ADDR[5]) { + capacitance : 0.0101975 ; + } + pin(B_ADDR[6]) { + capacitance : 0.0124055 ; + } + pin(B_ADDR[7]) { + capacitance : 0.0101065 ; + } + max_transition : "0.38" ; + pin(B_ADDR[8:0]) { + related_power_pin : VDD; + related_ground_pin : VSS; + internal_power() { + when : "B_MEN"; + rise_power("scalar"){ + values (0.0129); + } + fall_power("scalar"){ + values (0.0027); + } + } + internal_power() { + when : "!B_MEN"; + rise_power("scalar"){ + values (0.0261); + } + fall_power("scalar"){ + values (0.0017); + } + } + } + timing() { + timing_type : setup_rising; + related_pin : "B_CLK"; + when : "((B_WEN | B_REN)& B_MEN)" + sdf_cond : "B_RW_ACCESS" + + rise_constraint("SIG2SRAM_constraint_template") { + index_1("0.0040,0.0176,0.0344,0.0656,0.1120,0.2016,0.3800"); + index_2("0.0040,0.0176,0.0344,0.0656,0.1120,0.2016,0.3800"); + values ("-0.2371,-0.2215,-0.2098,-0.1824,-0.1434,-0.0691,0.0676",\ +"-0.2449,-0.2332,-0.2176,-0.1902,-0.1551,-0.0770,0.0559",\ +"-0.2605,-0.2488,-0.2332,-0.2059,-0.1707,-0.0965,0.0441",\ +"-0.2879,-0.2723,-0.2605,-0.2332,-0.1941,-0.1199,0.0168",\ +"-0.3230,-0.3113,-0.2996,-0.2723,-0.2332,-0.1590,-0.0184",\ +"-0.4012,-0.3895,-0.3738,-0.3465,-0.3074,-0.2332,-0.0965",\ +"-0.5379,-0.5262,-0.5105,-0.4832,-0.4480,-0.3699,-0.2332"); + } + + fall_constraint("SIG2SRAM_constraint_template") { + index_1("0.0040,0.0176,0.0344,0.0656,0.1120,0.2016,0.3800"); + index_2("0.0040,0.0176,0.0344,0.0656,0.1120,0.2016,0.3800"); + values ("-0.1785,-0.1707,-0.1551,-0.1277,-0.0887,-0.0184,0.1145",\ +"-0.1902,-0.1785,-0.1629,-0.1355,-0.1004,-0.0262,0.1027",\ +"-0.2059,-0.1941,-0.1785,-0.1512,-0.1160,-0.0418,0.0871",\ +"-0.2293,-0.2176,-0.2059,-0.1785,-0.1434,-0.0691,0.0598",\ +"-0.2684,-0.2566,-0.2449,-0.2176,-0.1824,-0.1082,0.0207",\ +"-0.3465,-0.3348,-0.3191,-0.2918,-0.2566,-0.1824,-0.0535",\ +"-0.4832,-0.4715,-0.4559,-0.4324,-0.3934,-0.3191,-0.1902"); + } + } + + + timing() { + timing_type : hold_rising; + related_pin : "B_CLK"; + when : "((B_WEN | B_REN)& B_MEN)" + sdf_cond : "B_RW_ACCESS" + + rise_constraint("SIG2SRAM_constraint_template") { + index_1("0.0040,0.0176,0.0344,0.0656,0.1120,0.2016,0.3800"); + index_2("0.0040,0.0176,0.0344,0.0656,0.1120,0.2016,0.3800"); + values ("0.3410,0.3293,0.3137,0.2863,0.2473,0.1730,0.0324",\ +"0.3488,0.3371,0.3215,0.2941,0.2590,0.1809,0.0480",\ +"0.3684,0.3527,0.3371,0.3098,0.2746,0.1965,0.0598",\ +"0.3918,0.3762,0.3645,0.3371,0.2980,0.2238,0.0871",\ +"0.4309,0.4152,0.4035,0.3762,0.3371,0.2629,0.1223",\ +"0.5051,0.4934,0.4777,0.4504,0.4113,0.3371,0.1965",\ +"0.6418,0.6262,0.6145,0.5871,0.5520,0.4738,0.3332"); + } + + fall_constraint("SIG2SRAM_constraint_template") { + index_1("0.0040,0.0176,0.0344,0.0656,0.1120,0.2016,0.3800"); + index_2("0.0040,0.0176,0.0344,0.0656,0.1120,0.2016,0.3800"); + values ("0.2824,0.2707,0.2551,0.2277,0.1926,0.1184,-0.0105",\ +"0.2902,0.2785,0.2668,0.2395,0.2043,0.1301,0.0012",\ +"0.3059,0.2941,0.2824,0.2551,0.2199,0.1457,0.0168",\ +"0.3332,0.3215,0.3059,0.2785,0.2434,0.1691,0.0402",\ +"0.3723,0.3605,0.3449,0.3176,0.2824,0.2121,0.0793",\ +"0.4465,0.4348,0.4230,0.3918,0.3566,0.2824,0.1535",\ +"0.5832,0.5715,0.5598,0.5324,0.4934,0.4191,0.2902"); + } + } +} +pin(B_WEN) { + direction : input ; + capacitance : 0.00341384 ; + max_transition : "0.38" ; + related_power_pin : VDD; + related_ground_pin : VSS; + internal_power() { + when : "B_MEN"; + rise_power("scalar"){ + values (0.0072); + } + fall_power("scalar"){ + values (0.0153); + } + } + internal_power() { + when : "!B_MEN"; + rise_power("scalar"){ + values (0.0059); + } + fall_power("scalar"){ + values (0.0232); + } + } + timing() { + timing_type : setup_rising; + related_pin : "B_CLK"; + when : "B_MEN" + sdf_cond : "B_MEN" + + rise_constraint("SIG2SRAM_constraint_template") { + index_1("0.0040,0.0176,0.0344,0.0656,0.1120,0.2016,0.3800"); + index_2("0.0040,0.0176,0.0344,0.0656,0.1120,0.2016,0.3800"); + values ("0.1418,0.1496,0.1652,0.1887,0.2316,0.3059,0.4465",\ +"0.1301,0.1379,0.1535,0.1809,0.2199,0.2941,0.4348",\ +"0.1145,0.1262,0.1379,0.1652,0.2043,0.2785,0.4191",\ +"0.0871,0.0949,0.1105,0.1379,0.1770,0.2512,0.3879",\ +"0.0480,0.0598,0.0754,0.0988,0.1379,0.2082,0.3527",\ +"-0.0262,-0.0145,0.0012,0.0246,0.0676,0.1379,0.2785",\ +"-0.1668,-0.1551,-0.1395,-0.1121,-0.0730,0.0012,0.1418"); + } + + fall_constraint("SIG2SRAM_constraint_template") { + index_1("0.0040,0.0176,0.0344,0.0656,0.1120,0.2016,0.3800"); + index_2("0.0040,0.0176,0.0344,0.0656,0.1120,0.2016,0.3800"); + values ("0.2082,0.2160,0.2316,0.2590,0.2941,0.3684,0.5012",\ +"0.1926,0.2043,0.2199,0.2473,0.2824,0.3566,0.4895",\ +"0.1770,0.1887,0.2043,0.2316,0.2668,0.3410,0.4777",\ +"0.1535,0.1652,0.1770,0.2043,0.2395,0.3137,0.4504",\ +"0.1145,0.1262,0.1379,0.1652,0.2043,0.2746,0.4113",\ +"0.0402,0.0520,0.0676,0.0910,0.1262,0.2004,0.3332",\ +"-0.0965,-0.0848,-0.0730,-0.0457,-0.0066,0.0637,0.2004"); + } + } + + + timing() { + timing_type : hold_rising; + related_pin : "B_CLK"; + when : "B_MEN" + sdf_cond : "B_MEN" + + rise_constraint("SIG2SRAM_constraint_template") { + index_1("0.0040,0.0176,0.0344,0.0656,0.1120,0.2016,0.3800"); + index_2("0.0040,0.0176,0.0344,0.0656,0.1120,0.2016,0.3800"); + values ("0.1770,0.1652,0.1496,0.1223,0.0793,0.0090,-0.1316",\ +"0.1848,0.1730,0.1574,0.1301,0.0910,0.0168,-0.1199",\ +"0.2004,0.1887,0.1770,0.1496,0.1066,0.0363,-0.1043",\ +"0.2277,0.2160,0.2004,0.1730,0.1340,0.0598,-0.0809",\ +"0.2668,0.2551,0.2395,0.2121,0.1730,0.0988,-0.0418",\ +"0.3410,0.3293,0.3137,0.2863,0.2434,0.1730,0.0324",\ +"0.4816,0.4699,0.4543,0.4230,0.3801,0.3098,0.1730"); + } + + fall_constraint("SIG2SRAM_constraint_template") { + index_1("0.0040,0.0176,0.0344,0.0656,0.1120,0.2016,0.3800"); + index_2("0.0040,0.0176,0.0344,0.0656,0.1120,0.2016,0.3800"); + values ("0.1613,0.1496,0.1379,0.1066,0.0715,0.0012,-0.1355",\ +"0.1730,0.1613,0.1457,0.1184,0.0832,0.0129,-0.1238",\ +"0.1887,0.1770,0.1613,0.1340,0.0988,0.0246,-0.1121",\ +"0.2121,0.2043,0.1887,0.1613,0.1223,0.0520,-0.0848",\ +"0.2512,0.2434,0.2277,0.2004,0.1613,0.0910,-0.0457",\ +"0.3254,0.3176,0.3020,0.2746,0.2355,0.1652,0.0324",\ +"0.4660,0.4543,0.4387,0.4113,0.3723,0.3020,0.1691"); + } + } + } +pin(B_REN) { + direction : input ; + capacitance : 0.00390661 ; + max_transition : "0.38" ; + related_power_pin : VDD; + related_ground_pin : VSS; + internal_power() { + when : "B_MEN"; + rise_power("scalar"){ + values (0.0097); + } + fall_power("scalar"){ + values (0.0114); + } + } + internal_power() { + when : "!B_MEN"; + rise_power("scalar"){ + values (0.0259); + } + fall_power("scalar"){ + values (0.0195); + } + } + timing() { + timing_type : setup_rising; + related_pin : "B_CLK"; + when : "B_MEN" + sdf_cond : "B_MEN" + + rise_constraint("SIG2SRAM_constraint_template") { + index_1("0.0040,0.0176,0.0344,0.0656,0.1120,0.2016,0.3800"); + index_2("0.0040,0.0176,0.0344,0.0656,0.1120,0.2016,0.3800"); + values ("-0.0027,0.0090,0.0246,0.0520,0.0910,0.1613,0.3020",\ +"-0.0105,0.0012,0.0129,0.0363,0.0793,0.1535,0.2902",\ +"-0.0262,-0.0145,-0.0027,0.0246,0.0637,0.1379,0.2785",\ +"-0.0535,-0.0418,-0.0262,0.0012,0.0363,0.1105,0.2512",\ +"-0.0926,-0.0809,-0.0652,-0.0418,-0.0027,0.0715,0.2121",\ +"-0.1668,-0.1551,-0.1395,-0.1082,-0.0770,-0.0027,0.1379",\ +"-0.3035,-0.2918,-0.2762,-0.2488,-0.2137,-0.1434,-0.0027"); + } + + fall_constraint("SIG2SRAM_constraint_template") { + index_1("0.0040,0.0176,0.0344,0.0656,0.1120,0.2016,0.3800"); + index_2("0.0040,0.0176,0.0344,0.0656,0.1120,0.2016,0.3800"); + values ("0.0832,0.0949,0.1105,0.1379,0.1730,0.2473,0.3801",\ +"0.0754,0.0832,0.0988,0.1223,0.1613,0.2355,0.3684",\ +"0.0598,0.0676,0.0832,0.1066,0.1457,0.2121,0.3527",\ +"0.0324,0.0441,0.0598,0.0871,0.1223,0.1926,0.3293",\ +"-0.0066,0.0051,0.0168,0.0480,0.0832,0.1535,0.2902",\ +"-0.0809,-0.0691,-0.0574,-0.0301,0.0090,0.0832,0.2121",\ +"-0.2176,-0.2059,-0.1941,-0.1668,-0.1277,-0.0574,0.0793"); + } + } + + + timing() { + timing_type : hold_rising; + related_pin : "B_CLK"; + when : "B_MEN" + sdf_cond : "B_MEN" + + rise_constraint("SIG2SRAM_constraint_template") { + index_1("0.0040,0.0176,0.0344,0.0656,0.1120,0.2016,0.3800"); + index_2("0.0040,0.0176,0.0344,0.0656,0.1120,0.2016,0.3800"); + values ("0.1887,0.1770,0.1613,0.1340,0.0949,0.0207,-0.1160",\ +"0.1965,0.1848,0.1730,0.1457,0.1027,0.0324,-0.1082",\ +"0.2160,0.2004,0.1887,0.1613,0.1184,0.0480,-0.0926",\ +"0.2395,0.2277,0.2121,0.1848,0.1457,0.0715,-0.0652",\ +"0.2785,0.2668,0.2512,0.2238,0.1848,0.1105,-0.0262",\ +"0.3527,0.3410,0.3254,0.2980,0.2551,0.1848,0.0480",\ +"0.4934,0.4816,0.4660,0.4387,0.3957,0.3254,0.1887"); + } + + fall_constraint("SIG2SRAM_constraint_template") { + index_1("0.0040,0.0176,0.0344,0.0656,0.1120,0.2016,0.3800"); + index_2("0.0040,0.0176,0.0344,0.0656,0.1120,0.2016,0.3800"); + values ("0.1730,0.1613,0.1496,0.1184,0.0793,0.0129,-0.1238",\ +"0.1848,0.1730,0.1574,0.1301,0.0910,0.0207,-0.1121",\ +"0.2004,0.1887,0.1730,0.1457,0.1066,0.0363,-0.1004",\ +"0.2238,0.2121,0.2004,0.1691,0.1340,0.0598,-0.0730",\ +"0.2629,0.2512,0.2395,0.2121,0.1691,0.0988,-0.0340",\ +"0.3371,0.3254,0.3137,0.2863,0.2434,0.1730,0.0402",\ +"0.4777,0.4660,0.4504,0.4230,0.3840,0.3137,0.1809"); + } + } + } +pin(B_MEN) { + direction : input ; + capacitance : 0.00326046 ; + max_transition : "0.38" ; + related_power_pin : VDD; + related_ground_pin : VSS; + internal_power() { + rise_power("scalar"){ + values (0.0831); + } + fall_power("scalar"){ + values (0.0107); + } + } + timing() { + timing_type : setup_rising; + related_pin : "B_CLK"; + + rise_constraint("SIG2SRAM_constraint_template") { + index_1("0.0040,0.0176,0.0344,0.0656,0.1120,0.2016,0.3800"); + index_2("0.0040,0.0176,0.0344,0.0656,0.1120,0.2016,0.3800"); + values ("0.1418,0.1496,0.1652,0.1926,0.2316,0.3059,0.4465",\ +"0.1301,0.1379,0.1535,0.1809,0.2199,0.2941,0.4348",\ +"0.1145,0.1262,0.1418,0.1652,0.2043,0.2785,0.4191",\ +"0.0871,0.0949,0.1105,0.1379,0.1770,0.2512,0.3879",\ +"0.0480,0.0598,0.0754,0.0988,0.1379,0.2082,0.3488",\ +"-0.0262,-0.0145,0.0012,0.0285,0.0676,0.1379,0.2785",\ +"-0.1668,-0.1551,-0.1395,-0.1121,-0.0730,0.0012,0.1379"); + } + + fall_constraint("SIG2SRAM_constraint_template") { + index_1("0.0040,0.0176,0.0344,0.0656,0.1120,0.2016,0.3800"); + index_2("0.0040,0.0176,0.0344,0.0656,0.1120,0.2016,0.3800"); + values ("0.2082,0.2199,0.2316,0.2590,0.2980,0.3723,0.5051",\ +"0.1965,0.2082,0.2199,0.2473,0.2863,0.3605,0.4934",\ +"0.1809,0.1926,0.2043,0.2316,0.2707,0.3449,0.4777",\ +"0.1574,0.1691,0.1809,0.2082,0.2434,0.3176,0.4543",\ +"0.1145,0.1262,0.1418,0.1691,0.2043,0.2785,0.4113",\ +"0.0441,0.0559,0.0676,0.0949,0.1301,0.2004,0.3332",\ +"-0.0965,-0.0848,-0.0691,-0.0418,-0.0066,0.0676,0.2004"); + } + } + + + timing() { + timing_type : hold_rising; + related_pin : "B_CLK"; + + rise_constraint("SIG2SRAM_constraint_template") { + index_1("0.0040,0.0176,0.0344,0.0656,0.1120,0.2016,0.3800"); + index_2("0.0040,0.0176,0.0344,0.0656,0.1120,0.2016,0.3800"); + values ("0.1770,0.1652,0.1535,0.1262,0.0832,0.0129,-0.1277",\ +"0.1887,0.1770,0.1613,0.1340,0.0949,0.0207,-0.1199",\ +"0.2043,0.1926,0.1770,0.1496,0.1105,0.0363,-0.1043",\ +"0.2277,0.2160,0.2043,0.1770,0.1379,0.0598,-0.0770",\ +"0.2668,0.2551,0.2434,0.2160,0.1730,0.0988,-0.0379",\ +"0.3449,0.3332,0.3176,0.2902,0.2473,0.1730,0.0363",\ +"0.4816,0.4699,0.4543,0.4270,0.3840,0.3098,0.1770"); + } + + fall_constraint("SIG2SRAM_constraint_template") { + index_1("0.0040,0.0176,0.0344,0.0656,0.1120,0.2016,0.3800"); + index_2("0.0040,0.0176,0.0344,0.0656,0.1120,0.2016,0.3800"); + values ("0.1613,0.1496,0.1379,0.1105,0.0715,0.0012,-0.1355",\ +"0.1730,0.1613,0.1496,0.1184,0.0832,0.0129,-0.1238",\ +"0.1887,0.1770,0.1652,0.1340,0.0988,0.0285,-0.1121",\ +"0.2121,0.2043,0.1887,0.1613,0.1223,0.0520,-0.0848",\ +"0.2551,0.2434,0.2277,0.2004,0.1613,0.0910,-0.0418",\ +"0.3293,0.3176,0.3020,0.2746,0.2395,0.1652,0.0324",\ +"0.4660,0.4543,0.4426,0.4113,0.3762,0.3020,0.1691"); + } + } + } +bus(B_BM) { + bus_type : D_7_0; + direction : input ; + capacitance : 0.00334781 ; + max_transition : "0.38" ; + pin(B_BM[7:0]) { + related_power_pin : VDD; + related_ground_pin : VSS; + internal_power() { + when : "B_MEN"; + rise_power("scalar"){ + values (0.0400); + } + fall_power("scalar"){ + values (0.0357); + } + } + internal_power() { + when : "!B_MEN"; + rise_power("scalar"){ + values (0.0592); + } + fall_power("scalar"){ + values (0.0441); + } + } + } + timing() { + timing_type : setup_rising; + related_pin : "B_CLK"; + when : "(B_WEN & B_MEN)" + sdf_cond : "B_RW_ACCESS" + + rise_constraint("SIG2SRAM_constraint_template") { + index_1("0.0040,0.0176,0.0344,0.0656,0.1120,0.2016,0.3800"); + index_2("0.0040,0.0176,0.0344,0.0656,0.1120,0.2016,0.3800"); + values ("-0.1725,-0.1618,-0.1462,-0.1208,-0.0798,-0.0065,0.1282",\ +"-0.1764,-0.1657,-0.1501,-0.1247,-0.0836,-0.0104,0.1244",\ +"-0.1802,-0.1695,-0.1539,-0.1285,-0.0874,-0.0142,0.1206",\ +"-0.1835,-0.1727,-0.1571,-0.1317,-0.0907,-0.0175,0.1173",\ +"-0.1959,-0.1852,-0.1695,-0.1442,-0.1031,-0.0299,0.1049",\ +"-0.2135,-0.2028,-0.1872,-0.1618,-0.1208,-0.0475,0.0872",\ +"-0.2410,-0.2303,-0.2147,-0.1893,-0.1483,-0.0750,0.0597"); + } + + fall_constraint("SIG2SRAM_constraint_template") { + index_1("0.0040,0.0176,0.0344,0.0656,0.1120,0.2016,0.3800"); + index_2("0.0040,0.0176,0.0344,0.0656,0.1120,0.2016,0.3800"); + values ("-0.1491,-0.1374,-0.1247,-0.0973,-0.0602,0.0130,0.1409",\ +"-0.1530,-0.1413,-0.1286,-0.1012,-0.0641,0.0091,0.1370",\ +"-0.1568,-0.1451,-0.1324,-0.1050,-0.0679,0.0053,0.1333",\ +"-0.1600,-0.1483,-0.1356,-0.1083,-0.0712,0.0021,0.1300",\ +"-0.1725,-0.1608,-0.1481,-0.1207,-0.0836,-0.0104,0.1176",\ +"-0.1901,-0.1784,-0.1657,-0.1383,-0.1012,-0.0280,0.0999",\ +"-0.2176,-0.2059,-0.1932,-0.1658,-0.1287,-0.0555,0.0724"); + } + } + + + timing() { + timing_type : hold_rising; + related_pin : "B_CLK"; + when : "(B_WEN & B_MEN)" + sdf_cond : "B_RW_ACCESS" + + rise_constraint("SIG2SRAM_constraint_template") { + index_1("0.0040,0.0176,0.0344,0.0656,0.1120,0.2016,0.3800"); + index_2("0.0040,0.0176,0.0344,0.0656,0.1120,0.2016,0.3800"); + values ("0.2776,0.2678,0.2522,0.2259,0.1887,0.1145,-0.0202",\ +"0.2815,0.2717,0.2561,0.2297,0.1926,0.1184,-0.0164",\ +"0.2853,0.2755,0.2599,0.2335,0.1964,0.1222,-0.0126",\ +"0.2885,0.2788,0.2632,0.2368,0.1997,0.1255,-0.0093",\ +"0.3010,0.2912,0.2756,0.2492,0.2121,0.1379,0.0031",\ +"0.3186,0.3088,0.2932,0.2668,0.2297,0.1555,0.0208",\ +"0.3461,0.3363,0.3207,0.2944,0.2572,0.1830,0.0483"); + } + + fall_constraint("SIG2SRAM_constraint_template") { + index_1("0.0040,0.0176,0.0344,0.0656,0.1120,0.2016,0.3800"); + index_2("0.0040,0.0176,0.0344,0.0656,0.1120,0.2016,0.3800"); + values ("0.2493,0.2385,0.2249,0.1975,0.1614,0.0891,-0.0407",\ +"0.2532,0.2424,0.2288,0.2014,0.1653,0.0930,-0.0369",\ +"0.2570,0.2462,0.2326,0.2052,0.1691,0.0968,-0.0331",\ +"0.2602,0.2495,0.2358,0.2085,0.1723,0.1001,-0.0298",\ +"0.2727,0.2619,0.2483,0.2209,0.1848,0.1125,-0.0174",\ +"0.2903,0.2795,0.2659,0.2385,0.2024,0.1301,0.0002",\ +"0.3178,0.3070,0.2934,0.2660,0.2299,0.1576,0.0278"); + } + } +} + pin(B_CLK) { + direction : input; + capacitance : 0.00389386; + max_transition : "0.38"; + clock : "true" ; + pin_func_type : active_rising ; + + timing () { + timing_type : "min_pulse_width"; + related_pin : "B_CLK"; + rise_constraint("CLKTRAN_constraint_template") { + index_1("0.004,0.38"); + values("0.12,0.12"); + } + } + + related_power_pin : VDD; + related_ground_pin : VSS; + + internal_power() { + when : "!B_MEN & !B_WEN & !B_REN"; + rise_power("scalar"){ + values (0); + } + fall_power("scalar"){ + values (0); + } + } + internal_power() { + when : "!B_MEN & B_WEN & !B_REN"; + rise_power("scalar"){ + values (0.6678); + } + fall_power("scalar"){ + values (0); + } + } + internal_power() { + when : "B_MEN & B_WEN & !B_REN"; + rise_power("scalar"){ + values (17.5281); + } + fall_power("scalar"){ + values (0); + } + } + internal_power() { + when : "B_MEN & B_WEN & B_REN"; + rise_power("scalar"){ + values (17.8148); + } + fall_power("scalar"){ + values (0); + } + } + internal_power() { + when : "B_MEN & !B_WEN & B_REN"; + rise_power("scalar"){ + values (14.1173); + } + fall_power("scalar"){ + values (0); + } + } + internal_power() { + when : "!B_MEN & !B_WEN & B_REN"; + rise_power("scalar"){ + values (0.3934); + } + fall_power("scalar"){ + values (0); + } + } + internal_power() { + when : "!B_MEN & B_WEN & B_REN"; + rise_power("scalar"){ + values (0.6886); + } + fall_power("scalar"){ + values (0); + } + } + internal_power() { + when : "B_MEN & !B_WEN & !B_REN"; + rise_power("scalar"){ + values (0); + } + fall_power("scalar"){ + values (0); + } + } + } + bus(B_DIN) { + bus_type : D_7_0; + direction : input ; + capacitance : 0.00468868 ; + memory_write() { + address : B_ADDR ; + clocked_on : B_CLK; + } + + max_transition : "0.38" ; + pin(B_DIN[7:0]) { + related_power_pin : VDD; + related_ground_pin : VSS; + internal_power() { + when : "B_MEN"; + rise_power("scalar"){ + values (0.0400); + } + fall_power("scalar"){ + values (0.0357); + } + } + internal_power() { + when : "!B_MEN"; + rise_power("scalar"){ + values (0.0592); + } + fall_power("scalar"){ + values (0.0441); + } + } + } + timing() { + timing_type : setup_rising; + related_pin : "B_CLK"; + when : "(B_WEN & B_MEN)"; + sdf_cond : "B_W_ACCESS"; + + rise_constraint("SIG2SRAM_constraint_template") { + index_1("0.0040,0.0176,0.0344,0.0656,0.1120,0.2016,0.3800"); + index_2("0.0040,0.0176,0.0344,0.0656,0.1120,0.2016,0.3800"); + values ("-0.1725,-0.1618,-0.1462,-0.1208,-0.0798,-0.0065,0.1282",\ +"-0.1764,-0.1657,-0.1501,-0.1247,-0.0836,-0.0104,0.1244",\ +"-0.1802,-0.1695,-0.1539,-0.1285,-0.0874,-0.0142,0.1206",\ +"-0.1835,-0.1727,-0.1571,-0.1317,-0.0907,-0.0175,0.1173",\ +"-0.1959,-0.1852,-0.1695,-0.1442,-0.1031,-0.0299,0.1049",\ +"-0.2135,-0.2028,-0.1872,-0.1618,-0.1208,-0.0475,0.0872",\ +"-0.2410,-0.2303,-0.2147,-0.1893,-0.1483,-0.0750,0.0597"); + } + + fall_constraint("SIG2SRAM_constraint_template") { + index_1("0.0040,0.0176,0.0344,0.0656,0.1120,0.2016,0.3800"); + index_2("0.0040,0.0176,0.0344,0.0656,0.1120,0.2016,0.3800"); + values ("-0.1491,-0.1374,-0.1247,-0.0973,-0.0602,0.0130,0.1409",\ +"-0.1530,-0.1413,-0.1286,-0.1012,-0.0641,0.0091,0.1370",\ +"-0.1568,-0.1451,-0.1324,-0.1050,-0.0679,0.0053,0.1333",\ +"-0.1600,-0.1483,-0.1356,-0.1083,-0.0712,0.0021,0.1300",\ +"-0.1725,-0.1608,-0.1481,-0.1207,-0.0836,-0.0104,0.1176",\ +"-0.1901,-0.1784,-0.1657,-0.1383,-0.1012,-0.0280,0.0999",\ +"-0.2176,-0.2059,-0.1932,-0.1658,-0.1287,-0.0555,0.0724"); + } + } + + timing() { + timing_type : hold_rising; + related_pin : "B_CLK"; + when : "(B_WEN & B_MEN)"; + sdf_cond : "B_W_ACCESS"; + + rise_constraint("SIG2SRAM_constraint_template") { + index_1("0.0040,0.0176,0.0344,0.0656,0.1120,0.2016,0.3800"); + index_2("0.0040,0.0176,0.0344,0.0656,0.1120,0.2016,0.3800"); + values ("0.2776,0.2678,0.2522,0.2259,0.1887,0.1145,-0.0202",\ +"0.2815,0.2717,0.2561,0.2297,0.1926,0.1184,-0.0164",\ +"0.2853,0.2755,0.2599,0.2335,0.1964,0.1222,-0.0126",\ +"0.2885,0.2788,0.2632,0.2368,0.1997,0.1255,-0.0093",\ +"0.3010,0.2912,0.2756,0.2492,0.2121,0.1379,0.0031",\ +"0.3186,0.3088,0.2932,0.2668,0.2297,0.1555,0.0208",\ +"0.3461,0.3363,0.3207,0.2944,0.2572,0.1830,0.0483"); + } + + fall_constraint("SIG2SRAM_constraint_template") { + index_1("0.0040,0.0176,0.0344,0.0656,0.1120,0.2016,0.3800"); + index_2("0.0040,0.0176,0.0344,0.0656,0.1120,0.2016,0.3800"); + values ("0.2493,0.2385,0.2249,0.1975,0.1614,0.0891,-0.0407",\ +"0.2532,0.2424,0.2288,0.2014,0.1653,0.0930,-0.0369",\ +"0.2570,0.2462,0.2326,0.2052,0.1691,0.0968,-0.0331",\ +"0.2602,0.2495,0.2358,0.2085,0.1723,0.1001,-0.0298",\ +"0.2727,0.2619,0.2483,0.2209,0.1848,0.1125,-0.0174",\ +"0.2903,0.2795,0.2659,0.2385,0.2024,0.1301,0.0002",\ +"0.3178,0.3070,0.2934,0.2660,0.2299,0.1576,0.0278"); + } + } + } + + pin(B_BIST_EN) { + direction : input ; + capacitance : 0.00421562 ; + max_transition : "1" ; + related_power_pin : VDD; + related_ground_pin : VSS; + internal_power() { + rise_power("scalar") { + values (0); + } + fall_power("scalar") { + values (0); + } + } + } + +bus(B_BIST_ADDR) { + bus_type : A_8_0; + direction : input ; + capacitance : 0.0115194 ; + pin(B_BIST_ADDR[0]) { + capacitance : 0.0056487 ; + } + pin(B_BIST_ADDR[1]) { + capacitance : 0.00741688 ; + } + pin(B_BIST_ADDR[2]) { + capacitance : 0.0100613 ; + } + pin(B_BIST_ADDR[3]) { + capacitance : 0.00667339 ; + } + pin(B_BIST_ADDR[4]) { + capacitance : 0.00620204 ; + } + pin(B_BIST_ADDR[5]) { + capacitance : 0.0101975 ; + } + pin(B_BIST_ADDR[6]) { + capacitance : 0.0124055 ; + } + pin(B_BIST_ADDR[7]) { + capacitance : 0.0101065 ; + } + max_transition : "0.38" ; + pin(B_BIST_ADDR[8:0]) { + related_power_pin : VDD; + related_ground_pin : VSS; + internal_power() { + when : "B_BIST_MEN"; + rise_power("scalar"){ + values (0.0129); + } + fall_power("scalar"){ + values (0.0027); + } + } + internal_power() { + when : "!B_BIST_MEN"; + rise_power("scalar"){ + values (0.0261); + } + fall_power("scalar"){ + values (0.0017); + } + } + } + timing() { + timing_type : setup_rising; + related_pin : "B_BIST_CLK"; + when : "((B_BIST_WEN | B_BIST_REN)& B_BIST_MEN)" + sdf_cond : "B_BIST_RW_ACCESS" + + rise_constraint("SIG2SRAM_constraint_template") { + index_1("0.0040,0.0176,0.0344,0.0656,0.1120,0.2016,0.3800"); + index_2("0.0040,0.0176,0.0344,0.0656,0.1120,0.2016,0.3800"); + values ("-0.2371,-0.2215,-0.2098,-0.1824,-0.1434,-0.0691,0.0676",\ +"-0.2449,-0.2332,-0.2176,-0.1902,-0.1551,-0.0770,0.0559",\ +"-0.2605,-0.2488,-0.2332,-0.2059,-0.1707,-0.0965,0.0441",\ +"-0.2879,-0.2723,-0.2605,-0.2332,-0.1941,-0.1199,0.0168",\ +"-0.3230,-0.3113,-0.2996,-0.2723,-0.2332,-0.1590,-0.0184",\ +"-0.4012,-0.3895,-0.3738,-0.3465,-0.3074,-0.2332,-0.0965",\ +"-0.5379,-0.5262,-0.5105,-0.4832,-0.4480,-0.3699,-0.2332"); + } + + fall_constraint("SIG2SRAM_constraint_template") { + index_1("0.0040,0.0176,0.0344,0.0656,0.1120,0.2016,0.3800"); + index_2("0.0040,0.0176,0.0344,0.0656,0.1120,0.2016,0.3800"); + values ("-0.1785,-0.1707,-0.1551,-0.1277,-0.0887,-0.0184,0.1145",\ +"-0.1902,-0.1785,-0.1629,-0.1355,-0.1004,-0.0262,0.1027",\ +"-0.2059,-0.1941,-0.1785,-0.1512,-0.1160,-0.0418,0.0871",\ +"-0.2293,-0.2176,-0.2059,-0.1785,-0.1434,-0.0691,0.0598",\ +"-0.2684,-0.2566,-0.2449,-0.2176,-0.1824,-0.1082,0.0207",\ +"-0.3465,-0.3348,-0.3191,-0.2918,-0.2566,-0.1824,-0.0535",\ +"-0.4832,-0.4715,-0.4559,-0.4324,-0.3934,-0.3191,-0.1902"); + } + } + + + timing() { + timing_type : hold_rising; + related_pin : "B_BIST_CLK"; + when : "((B_BIST_WEN | B_BIST_REN)& B_BIST_MEN)" + sdf_cond : "B_BIST_RW_ACCESS" + + rise_constraint("SIG2SRAM_constraint_template") { + index_1("0.0040,0.0176,0.0344,0.0656,0.1120,0.2016,0.3800"); + index_2("0.0040,0.0176,0.0344,0.0656,0.1120,0.2016,0.3800"); + values ("0.3410,0.3293,0.3137,0.2863,0.2473,0.1730,0.0324",\ +"0.3488,0.3371,0.3215,0.2941,0.2590,0.1809,0.0480",\ +"0.3684,0.3527,0.3371,0.3098,0.2746,0.1965,0.0598",\ +"0.3918,0.3762,0.3645,0.3371,0.2980,0.2238,0.0871",\ +"0.4309,0.4152,0.4035,0.3762,0.3371,0.2629,0.1223",\ +"0.5051,0.4934,0.4777,0.4504,0.4113,0.3371,0.1965",\ +"0.6418,0.6262,0.6145,0.5871,0.5520,0.4738,0.3332"); + } + + fall_constraint("SIG2SRAM_constraint_template") { + index_1("0.0040,0.0176,0.0344,0.0656,0.1120,0.2016,0.3800"); + index_2("0.0040,0.0176,0.0344,0.0656,0.1120,0.2016,0.3800"); + values ("0.2824,0.2707,0.2551,0.2277,0.1926,0.1184,-0.0105",\ +"0.2902,0.2785,0.2668,0.2395,0.2043,0.1301,0.0012",\ +"0.3059,0.2941,0.2824,0.2551,0.2199,0.1457,0.0168",\ +"0.3332,0.3215,0.3059,0.2785,0.2434,0.1691,0.0402",\ +"0.3723,0.3605,0.3449,0.3176,0.2824,0.2121,0.0793",\ +"0.4465,0.4348,0.4230,0.3918,0.3566,0.2824,0.1535",\ +"0.5832,0.5715,0.5598,0.5324,0.4934,0.4191,0.2902"); + } + } +} +pin(B_BIST_WEN) { + direction : input ; + capacitance : 0.00341384 ; + max_transition : "0.38" ; + related_power_pin : VDD; + related_ground_pin : VSS; + internal_power() { + when : "B_BIST_MEN"; + rise_power("scalar"){ + values (0.0072); + } + fall_power("scalar"){ + values (0.0153); + } + } + internal_power() { + when : "!B_BIST_MEN"; + rise_power("scalar"){ + values (0.0059); + } + fall_power("scalar"){ + values (0.0232); + } + } + timing() { + timing_type : setup_rising; + related_pin : "B_BIST_CLK"; + when : "B_BIST_MEN" + sdf_cond : "B_BIST_MEN" + + rise_constraint("SIG2SRAM_constraint_template") { + index_1("0.0040,0.0176,0.0344,0.0656,0.1120,0.2016,0.3800"); + index_2("0.0040,0.0176,0.0344,0.0656,0.1120,0.2016,0.3800"); + values ("0.1418,0.1496,0.1652,0.1887,0.2316,0.3059,0.4465",\ +"0.1301,0.1379,0.1535,0.1809,0.2199,0.2941,0.4348",\ +"0.1145,0.1262,0.1379,0.1652,0.2043,0.2785,0.4191",\ +"0.0871,0.0949,0.1105,0.1379,0.1770,0.2512,0.3879",\ +"0.0480,0.0598,0.0754,0.0988,0.1379,0.2082,0.3527",\ +"-0.0262,-0.0145,0.0012,0.0246,0.0676,0.1379,0.2785",\ +"-0.1668,-0.1551,-0.1395,-0.1121,-0.0730,0.0012,0.1418"); + } + + fall_constraint("SIG2SRAM_constraint_template") { + index_1("0.0040,0.0176,0.0344,0.0656,0.1120,0.2016,0.3800"); + index_2("0.0040,0.0176,0.0344,0.0656,0.1120,0.2016,0.3800"); + values ("0.2082,0.2160,0.2316,0.2590,0.2941,0.3684,0.5012",\ +"0.1926,0.2043,0.2199,0.2473,0.2824,0.3566,0.4895",\ +"0.1770,0.1887,0.2043,0.2316,0.2668,0.3410,0.4777",\ +"0.1535,0.1652,0.1770,0.2043,0.2395,0.3137,0.4504",\ +"0.1145,0.1262,0.1379,0.1652,0.2043,0.2746,0.4113",\ +"0.0402,0.0520,0.0676,0.0910,0.1262,0.2004,0.3332",\ +"-0.0965,-0.0848,-0.0730,-0.0457,-0.0066,0.0637,0.2004"); + } + } + + + timing() { + timing_type : hold_rising; + related_pin : "B_BIST_CLK"; + when : "B_BIST_MEN" + sdf_cond : "B_BIST_MEN" + + rise_constraint("SIG2SRAM_constraint_template") { + index_1("0.0040,0.0176,0.0344,0.0656,0.1120,0.2016,0.3800"); + index_2("0.0040,0.0176,0.0344,0.0656,0.1120,0.2016,0.3800"); + values ("0.1770,0.1652,0.1496,0.1223,0.0793,0.0090,-0.1316",\ +"0.1848,0.1730,0.1574,0.1301,0.0910,0.0168,-0.1199",\ +"0.2004,0.1887,0.1770,0.1496,0.1066,0.0363,-0.1043",\ +"0.2277,0.2160,0.2004,0.1730,0.1340,0.0598,-0.0809",\ +"0.2668,0.2551,0.2395,0.2121,0.1730,0.0988,-0.0418",\ +"0.3410,0.3293,0.3137,0.2863,0.2434,0.1730,0.0324",\ +"0.4816,0.4699,0.4543,0.4230,0.3801,0.3098,0.1730"); + } + + fall_constraint("SIG2SRAM_constraint_template") { + index_1("0.0040,0.0176,0.0344,0.0656,0.1120,0.2016,0.3800"); + index_2("0.0040,0.0176,0.0344,0.0656,0.1120,0.2016,0.3800"); + values ("0.1613,0.1496,0.1379,0.1066,0.0715,0.0012,-0.1355",\ +"0.1730,0.1613,0.1457,0.1184,0.0832,0.0129,-0.1238",\ +"0.1887,0.1770,0.1613,0.1340,0.0988,0.0246,-0.1121",\ +"0.2121,0.2043,0.1887,0.1613,0.1223,0.0520,-0.0848",\ +"0.2512,0.2434,0.2277,0.2004,0.1613,0.0910,-0.0457",\ +"0.3254,0.3176,0.3020,0.2746,0.2355,0.1652,0.0324",\ +"0.4660,0.4543,0.4387,0.4113,0.3723,0.3020,0.1691"); + } + } + } +pin(B_BIST_REN) { + direction : input ; + capacitance : 0.00390661 ; + max_transition : "0.38" ; + related_power_pin : VDD; + related_ground_pin : VSS; + internal_power() { + when : "B_BIST_MEN"; + rise_power("scalar"){ + values (0.0097); + } + fall_power("scalar"){ + values (0.0114); + } + } + internal_power() { + when : "!B_BIST_MEN"; + rise_power("scalar"){ + values (0.0259); + } + fall_power("scalar"){ + values (0.0195); + } + } + timing() { + timing_type : setup_rising; + related_pin : "B_BIST_CLK"; + when : "B_BIST_MEN" + sdf_cond : "B_BIST_MEN" + + rise_constraint("SIG2SRAM_constraint_template") { + index_1("0.0040,0.0176,0.0344,0.0656,0.1120,0.2016,0.3800"); + index_2("0.0040,0.0176,0.0344,0.0656,0.1120,0.2016,0.3800"); + values ("-0.0027,0.0090,0.0246,0.0520,0.0910,0.1613,0.3020",\ +"-0.0105,0.0012,0.0129,0.0363,0.0793,0.1535,0.2902",\ +"-0.0262,-0.0145,-0.0027,0.0246,0.0637,0.1379,0.2785",\ +"-0.0535,-0.0418,-0.0262,0.0012,0.0363,0.1105,0.2512",\ +"-0.0926,-0.0809,-0.0652,-0.0418,-0.0027,0.0715,0.2121",\ +"-0.1668,-0.1551,-0.1395,-0.1082,-0.0770,-0.0027,0.1379",\ +"-0.3035,-0.2918,-0.2762,-0.2488,-0.2137,-0.1434,-0.0027"); + } + + fall_constraint("SIG2SRAM_constraint_template") { + index_1("0.0040,0.0176,0.0344,0.0656,0.1120,0.2016,0.3800"); + index_2("0.0040,0.0176,0.0344,0.0656,0.1120,0.2016,0.3800"); + values ("0.0832,0.0949,0.1105,0.1379,0.1730,0.2473,0.3801",\ +"0.0754,0.0832,0.0988,0.1223,0.1613,0.2355,0.3684",\ +"0.0598,0.0676,0.0832,0.1066,0.1457,0.2121,0.3527",\ +"0.0324,0.0441,0.0598,0.0871,0.1223,0.1926,0.3293",\ +"-0.0066,0.0051,0.0168,0.0480,0.0832,0.1535,0.2902",\ +"-0.0809,-0.0691,-0.0574,-0.0301,0.0090,0.0832,0.2121",\ +"-0.2176,-0.2059,-0.1941,-0.1668,-0.1277,-0.0574,0.0793"); + } + } + + + timing() { + timing_type : hold_rising; + related_pin : "B_BIST_CLK"; + when : "B_BIST_MEN" + sdf_cond : "B_BIST_MEN" + + rise_constraint("SIG2SRAM_constraint_template") { + index_1("0.0040,0.0176,0.0344,0.0656,0.1120,0.2016,0.3800"); + index_2("0.0040,0.0176,0.0344,0.0656,0.1120,0.2016,0.3800"); + values ("0.1887,0.1770,0.1613,0.1340,0.0949,0.0207,-0.1160",\ +"0.1965,0.1848,0.1730,0.1457,0.1027,0.0324,-0.1082",\ +"0.2160,0.2004,0.1887,0.1613,0.1184,0.0480,-0.0926",\ +"0.2395,0.2277,0.2121,0.1848,0.1457,0.0715,-0.0652",\ +"0.2785,0.2668,0.2512,0.2238,0.1848,0.1105,-0.0262",\ +"0.3527,0.3410,0.3254,0.2980,0.2551,0.1848,0.0480",\ +"0.4934,0.4816,0.4660,0.4387,0.3957,0.3254,0.1887"); + } + + fall_constraint("SIG2SRAM_constraint_template") { + index_1("0.0040,0.0176,0.0344,0.0656,0.1120,0.2016,0.3800"); + index_2("0.0040,0.0176,0.0344,0.0656,0.1120,0.2016,0.3800"); + values ("0.1730,0.1613,0.1496,0.1184,0.0793,0.0129,-0.1238",\ +"0.1848,0.1730,0.1574,0.1301,0.0910,0.0207,-0.1121",\ +"0.2004,0.1887,0.1730,0.1457,0.1066,0.0363,-0.1004",\ +"0.2238,0.2121,0.2004,0.1691,0.1340,0.0598,-0.0730",\ +"0.2629,0.2512,0.2395,0.2121,0.1691,0.0988,-0.0340",\ +"0.3371,0.3254,0.3137,0.2863,0.2434,0.1730,0.0402",\ +"0.4777,0.4660,0.4504,0.4230,0.3840,0.3137,0.1809"); + } + } + } +pin(B_BIST_MEN) { + direction : input ; + capacitance : 0.00326046 ; + max_transition : "0.38" ; + related_power_pin : VDD; + related_ground_pin : VSS; + internal_power() { + rise_power("scalar"){ + values (0.0831); + } + fall_power("scalar"){ + values (0.0107); + } + } + timing() { + timing_type : setup_rising; + related_pin : "B_BIST_CLK"; + + rise_constraint("SIG2SRAM_constraint_template") { + index_1("0.0040,0.0176,0.0344,0.0656,0.1120,0.2016,0.3800"); + index_2("0.0040,0.0176,0.0344,0.0656,0.1120,0.2016,0.3800"); + values ("0.1418,0.1496,0.1652,0.1926,0.2316,0.3059,0.4465",\ +"0.1301,0.1379,0.1535,0.1809,0.2199,0.2941,0.4348",\ +"0.1145,0.1262,0.1418,0.1652,0.2043,0.2785,0.4191",\ +"0.0871,0.0949,0.1105,0.1379,0.1770,0.2512,0.3879",\ +"0.0480,0.0598,0.0754,0.0988,0.1379,0.2082,0.3488",\ +"-0.0262,-0.0145,0.0012,0.0285,0.0676,0.1379,0.2785",\ +"-0.1668,-0.1551,-0.1395,-0.1121,-0.0730,0.0012,0.1379"); + } + + fall_constraint("SIG2SRAM_constraint_template") { + index_1("0.0040,0.0176,0.0344,0.0656,0.1120,0.2016,0.3800"); + index_2("0.0040,0.0176,0.0344,0.0656,0.1120,0.2016,0.3800"); + values ("0.2082,0.2199,0.2316,0.2590,0.2980,0.3723,0.5051",\ +"0.1965,0.2082,0.2199,0.2473,0.2863,0.3605,0.4934",\ +"0.1809,0.1926,0.2043,0.2316,0.2707,0.3449,0.4777",\ +"0.1574,0.1691,0.1809,0.2082,0.2434,0.3176,0.4543",\ +"0.1145,0.1262,0.1418,0.1691,0.2043,0.2785,0.4113",\ +"0.0441,0.0559,0.0676,0.0949,0.1301,0.2004,0.3332",\ +"-0.0965,-0.0848,-0.0691,-0.0418,-0.0066,0.0676,0.2004"); + } + } + + + timing() { + timing_type : hold_rising; + related_pin : "B_BIST_CLK"; + + rise_constraint("SIG2SRAM_constraint_template") { + index_1("0.0040,0.0176,0.0344,0.0656,0.1120,0.2016,0.3800"); + index_2("0.0040,0.0176,0.0344,0.0656,0.1120,0.2016,0.3800"); + values ("0.1770,0.1652,0.1535,0.1262,0.0832,0.0129,-0.1277",\ +"0.1887,0.1770,0.1613,0.1340,0.0949,0.0207,-0.1199",\ +"0.2043,0.1926,0.1770,0.1496,0.1105,0.0363,-0.1043",\ +"0.2277,0.2160,0.2043,0.1770,0.1379,0.0598,-0.0770",\ +"0.2668,0.2551,0.2434,0.2160,0.1730,0.0988,-0.0379",\ +"0.3449,0.3332,0.3176,0.2902,0.2473,0.1730,0.0363",\ +"0.4816,0.4699,0.4543,0.4270,0.3840,0.3098,0.1770"); + } + + fall_constraint("SIG2SRAM_constraint_template") { + index_1("0.0040,0.0176,0.0344,0.0656,0.1120,0.2016,0.3800"); + index_2("0.0040,0.0176,0.0344,0.0656,0.1120,0.2016,0.3800"); + values ("0.1613,0.1496,0.1379,0.1105,0.0715,0.0012,-0.1355",\ +"0.1730,0.1613,0.1496,0.1184,0.0832,0.0129,-0.1238",\ +"0.1887,0.1770,0.1652,0.1340,0.0988,0.0285,-0.1121",\ +"0.2121,0.2043,0.1887,0.1613,0.1223,0.0520,-0.0848",\ +"0.2551,0.2434,0.2277,0.2004,0.1613,0.0910,-0.0418",\ +"0.3293,0.3176,0.3020,0.2746,0.2395,0.1652,0.0324",\ +"0.4660,0.4543,0.4426,0.4113,0.3762,0.3020,0.1691"); + } + } + } +bus(B_BIST_BM) { + bus_type : D_7_0; + direction : input ; + capacitance : 0.00290564 ; + max_transition : "0.38" ; + pin(B_BIST_BM[7:0]) { + related_power_pin : VDD; + related_ground_pin : VSS; + internal_power() { + when : "B_BIST_MEN"; + rise_power("scalar"){ + values (0.0400); + } + fall_power("scalar"){ + values (0.0357); + } + } + internal_power() { + when : "!B_BIST_MEN"; + rise_power("scalar"){ + values (0.0592); + } + fall_power("scalar"){ + values (0.0441); + } + } + } + timing() { + timing_type : setup_rising; + related_pin : "B_BIST_CLK"; + when : "(B_BIST_WEN & B_BIST_MEN)" + sdf_cond : "B_BIST_RW_ACCESS" + + rise_constraint("SIG2SRAM_constraint_template") { + index_1("0.0040,0.0176,0.0344,0.0656,0.1120,0.2016,0.3800"); + index_2("0.0040,0.0176,0.0344,0.0656,0.1120,0.2016,0.3800"); + values ("-0.1725,-0.1618,-0.1462,-0.1208,-0.0798,-0.0065,0.1282",\ +"-0.1764,-0.1657,-0.1501,-0.1247,-0.0836,-0.0104,0.1244",\ +"-0.1802,-0.1695,-0.1539,-0.1285,-0.0874,-0.0142,0.1206",\ +"-0.1835,-0.1727,-0.1571,-0.1317,-0.0907,-0.0175,0.1173",\ +"-0.1959,-0.1852,-0.1695,-0.1442,-0.1031,-0.0299,0.1049",\ +"-0.2135,-0.2028,-0.1872,-0.1618,-0.1208,-0.0475,0.0872",\ +"-0.2410,-0.2303,-0.2147,-0.1893,-0.1483,-0.0750,0.0597"); + } + + fall_constraint("SIG2SRAM_constraint_template") { + index_1("0.0040,0.0176,0.0344,0.0656,0.1120,0.2016,0.3800"); + index_2("0.0040,0.0176,0.0344,0.0656,0.1120,0.2016,0.3800"); + values ("-0.1491,-0.1374,-0.1247,-0.0973,-0.0602,0.0130,0.1409",\ +"-0.1530,-0.1413,-0.1286,-0.1012,-0.0641,0.0091,0.1370",\ +"-0.1568,-0.1451,-0.1324,-0.1050,-0.0679,0.0053,0.1333",\ +"-0.1600,-0.1483,-0.1356,-0.1083,-0.0712,0.0021,0.1300",\ +"-0.1725,-0.1608,-0.1481,-0.1207,-0.0836,-0.0104,0.1176",\ +"-0.1901,-0.1784,-0.1657,-0.1383,-0.1012,-0.0280,0.0999",\ +"-0.2176,-0.2059,-0.1932,-0.1658,-0.1287,-0.0555,0.0724"); + } + } + + + timing() { + timing_type : hold_rising; + related_pin : "B_BIST_CLK"; + when : "(B_BIST_WEN & B_BIST_MEN)" + sdf_cond : "B_BIST_RW_ACCESS" + + rise_constraint("SIG2SRAM_constraint_template") { + index_1("0.0040,0.0176,0.0344,0.0656,0.1120,0.2016,0.3800"); + index_2("0.0040,0.0176,0.0344,0.0656,0.1120,0.2016,0.3800"); + values ("0.2776,0.2678,0.2522,0.2259,0.1887,0.1145,-0.0202",\ +"0.2815,0.2717,0.2561,0.2297,0.1926,0.1184,-0.0164",\ +"0.2853,0.2755,0.2599,0.2335,0.1964,0.1222,-0.0126",\ +"0.2885,0.2788,0.2632,0.2368,0.1997,0.1255,-0.0093",\ +"0.3010,0.2912,0.2756,0.2492,0.2121,0.1379,0.0031",\ +"0.3186,0.3088,0.2932,0.2668,0.2297,0.1555,0.0208",\ +"0.3461,0.3363,0.3207,0.2944,0.2572,0.1830,0.0483"); + } + + fall_constraint("SIG2SRAM_constraint_template") { + index_1("0.0040,0.0176,0.0344,0.0656,0.1120,0.2016,0.3800"); + index_2("0.0040,0.0176,0.0344,0.0656,0.1120,0.2016,0.3800"); + values ("0.2493,0.2385,0.2249,0.1975,0.1614,0.0891,-0.0407",\ +"0.2532,0.2424,0.2288,0.2014,0.1653,0.0930,-0.0369",\ +"0.2570,0.2462,0.2326,0.2052,0.1691,0.0968,-0.0331",\ +"0.2602,0.2495,0.2358,0.2085,0.1723,0.1001,-0.0298",\ +"0.2727,0.2619,0.2483,0.2209,0.1848,0.1125,-0.0174",\ +"0.2903,0.2795,0.2659,0.2385,0.2024,0.1301,0.0002",\ +"0.3178,0.3070,0.2934,0.2660,0.2299,0.1576,0.0278"); + } + } +} + pin(B_BIST_CLK) { + direction : input; + capacitance : 0.00389386; + max_transition : "0.38"; + clock : "true" ; + pin_func_type : active_rising ; + + timing () { + timing_type : "min_pulse_width"; + related_pin : "B_BIST_CLK"; + rise_constraint("CLKTRAN_constraint_template") { + index_1("0.004,0.38"); + values("0.12,0.12"); + } + } + + related_power_pin : VDD; + related_ground_pin : VSS; + + internal_power() { + when : "!B_BIST_MEN & !B_BIST_WEN & !B_BIST_REN"; + rise_power("scalar"){ + values (0); + } + fall_power("scalar"){ + values (0); + } + } + internal_power() { + when : "!B_BIST_MEN & B_BIST_WEN & !B_BIST_REN"; + rise_power("scalar"){ + values (0.6678); + } + fall_power("scalar"){ + values (0); + } + } + internal_power() { + when : "B_BIST_MEN & B_BIST_WEN & !B_BIST_REN"; + rise_power("scalar"){ + values (17.5281); + } + fall_power("scalar"){ + values (0); + } + } + internal_power() { + when : "B_BIST_MEN & B_BIST_WEN & B_BIST_REN"; + rise_power("scalar"){ + values (17.8148); + } + fall_power("scalar"){ + values (0); + } + } + internal_power() { + when : "B_BIST_MEN & !B_BIST_WEN & B_BIST_REN"; + rise_power("scalar"){ + values (14.1173); + } + fall_power("scalar"){ + values (0); + } + } + internal_power() { + when : "!B_BIST_MEN & !B_BIST_WEN & B_BIST_REN"; + rise_power("scalar"){ + values (0.3934); + } + fall_power("scalar"){ + values (0); + } + } + internal_power() { + when : "!B_BIST_MEN & B_BIST_WEN & B_BIST_REN"; + rise_power("scalar"){ + values (0.6886); + } + fall_power("scalar"){ + values (0); + } + } + internal_power() { + when : "B_BIST_MEN & !B_BIST_WEN & !B_BIST_REN"; + rise_power("scalar"){ + values (0); + } + fall_power("scalar"){ + values (0); + } + } + } + bus(B_BIST_DIN) { + bus_type : D_7_0; + direction : input ; + capacitance : 0.00417898 ; + memory_write() { + address : B_BIST_ADDR ; + clocked_on : B_BIST_CLK; + } + + max_transition : "0.38" ; + pin(B_BIST_DIN[7:0]) { + related_power_pin : VDD; + related_ground_pin : VSS; + internal_power() { + when : "B_BIST_MEN"; + rise_power("scalar"){ + values (0.0400); + } + fall_power("scalar"){ + values (0.0357); + } + } + internal_power() { + when : "!B_BIST_MEN"; + rise_power("scalar"){ + values (0.0592); + } + fall_power("scalar"){ + values (0.0441); + } + } + } + timing() { + timing_type : setup_rising; + related_pin : "B_BIST_CLK"; + when : "(B_BIST_WEN & B_BIST_MEN)"; + sdf_cond : "B_BIST_W_ACCESS"; + + rise_constraint("SIG2SRAM_constraint_template") { + index_1("0.0040,0.0176,0.0344,0.0656,0.1120,0.2016,0.3800"); + index_2("0.0040,0.0176,0.0344,0.0656,0.1120,0.2016,0.3800"); + values ("-0.1725,-0.1618,-0.1462,-0.1208,-0.0798,-0.0065,0.1282",\ +"-0.1764,-0.1657,-0.1501,-0.1247,-0.0836,-0.0104,0.1244",\ +"-0.1802,-0.1695,-0.1539,-0.1285,-0.0874,-0.0142,0.1206",\ +"-0.1835,-0.1727,-0.1571,-0.1317,-0.0907,-0.0175,0.1173",\ +"-0.1959,-0.1852,-0.1695,-0.1442,-0.1031,-0.0299,0.1049",\ +"-0.2135,-0.2028,-0.1872,-0.1618,-0.1208,-0.0475,0.0872",\ +"-0.2410,-0.2303,-0.2147,-0.1893,-0.1483,-0.0750,0.0597"); + } + + fall_constraint("SIG2SRAM_constraint_template") { + index_1("0.0040,0.0176,0.0344,0.0656,0.1120,0.2016,0.3800"); + index_2("0.0040,0.0176,0.0344,0.0656,0.1120,0.2016,0.3800"); + values ("-0.1491,-0.1374,-0.1247,-0.0973,-0.0602,0.0130,0.1409",\ +"-0.1530,-0.1413,-0.1286,-0.1012,-0.0641,0.0091,0.1370",\ +"-0.1568,-0.1451,-0.1324,-0.1050,-0.0679,0.0053,0.1333",\ +"-0.1600,-0.1483,-0.1356,-0.1083,-0.0712,0.0021,0.1300",\ +"-0.1725,-0.1608,-0.1481,-0.1207,-0.0836,-0.0104,0.1176",\ +"-0.1901,-0.1784,-0.1657,-0.1383,-0.1012,-0.0280,0.0999",\ +"-0.2176,-0.2059,-0.1932,-0.1658,-0.1287,-0.0555,0.0724"); + } + } + + timing() { + timing_type : hold_rising; + related_pin : "B_BIST_CLK"; + when : "(B_BIST_WEN & B_BIST_MEN)"; + sdf_cond : "B_BIST_W_ACCESS"; + + rise_constraint("SIG2SRAM_constraint_template") { + index_1("0.0040,0.0176,0.0344,0.0656,0.1120,0.2016,0.3800"); + index_2("0.0040,0.0176,0.0344,0.0656,0.1120,0.2016,0.3800"); + values ("0.2776,0.2678,0.2522,0.2259,0.1887,0.1145,-0.0202",\ +"0.2815,0.2717,0.2561,0.2297,0.1926,0.1184,-0.0164",\ +"0.2853,0.2755,0.2599,0.2335,0.1964,0.1222,-0.0126",\ +"0.2885,0.2788,0.2632,0.2368,0.1997,0.1255,-0.0093",\ +"0.3010,0.2912,0.2756,0.2492,0.2121,0.1379,0.0031",\ +"0.3186,0.3088,0.2932,0.2668,0.2297,0.1555,0.0208",\ +"0.3461,0.3363,0.3207,0.2944,0.2572,0.1830,0.0483"); + } + + fall_constraint("SIG2SRAM_constraint_template") { + index_1("0.0040,0.0176,0.0344,0.0656,0.1120,0.2016,0.3800"); + index_2("0.0040,0.0176,0.0344,0.0656,0.1120,0.2016,0.3800"); + values ("0.2493,0.2385,0.2249,0.1975,0.1614,0.0891,-0.0407",\ +"0.2532,0.2424,0.2288,0.2014,0.1653,0.0930,-0.0369",\ +"0.2570,0.2462,0.2326,0.2052,0.1691,0.0968,-0.0331",\ +"0.2602,0.2495,0.2358,0.2085,0.1723,0.1001,-0.0298",\ +"0.2727,0.2619,0.2483,0.2209,0.1848,0.1125,-0.0174",\ +"0.2903,0.2795,0.2659,0.2385,0.2024,0.1301,0.0002",\ +"0.3178,0.3070,0.2934,0.2660,0.2299,0.1576,0.0278"); + } + } + } + +bus(B_DOUT) { + + bus_type : D_7_0; + direction : output ; + capacitance : 0 ; + max_capacitance : 0.064 ; + memory_read() { + address : B_ADDR ; + } + pin(B_DOUT[7:0]) { + related_power_pin : VDD; + related_ground_pin : VSS; + internal_power() { + rise_power("scalar") { + values (0); + } + fall_power("scalar") { + values (0); + } + } + } + timing() { + related_pin : "B_CLK"; + timing_type : rising_edge ; + timing_sense : non_unate ; + + cell_rise(SIG2SRAM_delay_template) { + index_1("0.0040,0.0176,0.0344,0.0656,0.1120,0.2016,0.3800"); + index_2("0.0008,0.0014,0.0051,0.0100,0.0339,0.0640"); + values ("2.2905,2.2915,2.2963,2.3018,2.3227,2.3462",\ +"2.2969,2.2979,2.3027,2.3082,2.3291,2.3526",\ +"2.2985,2.2995,2.3043,2.3098,2.3307,2.3542",\ +"2.3028,2.3038,2.3086,2.3141,2.3351,2.3586",\ +"2.3160,2.3170,2.3218,2.3273,2.3482,2.3717",\ +"2.3345,2.3355,2.3403,2.3459,2.3668,2.3903",\ +"2.3610,2.3621,2.3669,2.3724,2.3933,2.4168"); + } + cell_fall(SIG2SRAM_delay_template) { + index_1("0.0040,0.0176,0.0344,0.0656,0.1120,0.2016,0.3800"); + index_2("0.0008,0.0014,0.0051,0.0100,0.0339,0.0640"); + values ("2.2562,2.2571,2.2611,2.2656,2.2827,2.2995",\ +"2.2626,2.2634,2.2675,2.2720,2.2891,2.3058",\ +"2.2642,2.2650,2.2691,2.2736,2.2907,2.3074",\ +"2.2685,2.2694,2.2734,2.2780,2.2950,2.3118",\ +"2.2817,2.2825,2.2866,2.2911,2.3082,2.3249",\ +"2.3002,2.3011,2.3051,2.3097,2.3268,2.3435",\ +"2.3268,2.3276,2.3317,2.3362,2.3533,2.3700"); + } + + rise_transition(SRAM_load_template) { + index_1("0.0008,0.0014,0.0051,0.0100,0.0339,0.0640"); + values ("0.0206,0.0210,0.0265,0.0323,0.0606,0.0955"); + } + fall_transition(SRAM_load_template) { + index_1("0.0008,0.0014,0.0051,0.0100,0.0339,0.0640"); + values ("0.0170,0.0177,0.0222,0.0270,0.0451,0.0644"); + } + } +} +cell_leakage_power : 225.8534; +} +} diff --git a/flow/platforms/ihp-sg13g2/lib/RM_IHPSG13_2P_512x8_c2_bm_bist_slow_1p08V_125C.lib b/flow/platforms/ihp-sg13g2/lib/RM_IHPSG13_2P_512x8_c2_bm_bist_slow_1p08V_125C.lib new file mode 100644 index 0000000000..c1bd5d0ef0 --- /dev/null +++ b/flow/platforms/ihp-sg13g2/lib/RM_IHPSG13_2P_512x8_c2_bm_bist_slow_1p08V_125C.lib @@ -0,0 +1,2886 @@ +/* ------------------------------------------------------*/ +/**/ +/* Copyright 2025 IHP PDK Authors*/ +/**/ +/* Licensed under the Apache License, Version 2.0 (the "License");*/ +/* you may not use this file except in compliance with the License.*/ +/* You may obtain a copy of the License at*/ +/* */ +/* https://www.apache.org/licenses/LICENSE-2.0*/ +/* */ +/* Unless required by applicable law or agreed to in writing, software*/ +/* distributed under the License is distributed on an "AS IS" BASIS,*/ +/* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.*/ +/* See the License for the specific language governing permissions and*/ +/* limitations under the License.*/ +/* */ +/* Generated on Wed Aug 27 13:34:36 2025 */ +/* */ +/* ------------------------------------------------------ */ +library(RM_IHPSG13_2P_512x8_c2_bm_bist_slow_1p08V_125C) { + technology (cmos) ; + delay_model : table_lookup ; + define ("add_pg_pin_to_lib", "library", "boolean"); + add_pg_pin_to_lib : true; + voltage_map ( VDD, 1.08); + voltage_map ( VDDARRAY, 1.08); + voltage_map ( VSS, 0.000000 ); + + date : "Wed Aug 27 13:34:35 2025" ; + comment : "IHP Microelectronics GmbH, 2023" ; + revision : 1.0.0 ; + simulation : true ; + nom_process : 1 ; + nom_temperature : 125 ; + nom_voltage : 1.08 ; + + operating_conditions("slow_1p08V_125C"){ + process : 1 ; + temperature : 125 ; + voltage : 1.08 ; + tree_type : "balanced_tree" ; + } + + default_operating_conditions : slow_1p08V_125C ; + default_max_transition : 1.0 ; + default_fanout_load : 1.0 ; + default_inout_pin_cap : 0.0 ; + default_input_pin_cap : 0.0 ; + default_output_pin_cap : 0.0 ; + default_cell_leakage_power : 0.0 ; + default_leakage_power_density : 0.0 ; + + slew_lower_threshold_pct_rise : 30 ; + slew_upper_threshold_pct_rise : 70 ; + input_threshold_pct_fall : 50 ; + output_threshold_pct_fall : 50 ; + input_threshold_pct_rise : 50 ; + output_threshold_pct_rise : 50 ; + slew_lower_threshold_pct_fall : 30 ; + slew_upper_threshold_pct_fall : 70 ; + slew_derate_from_library : 0.5; + k_volt_cell_leakage_power : 0.0 ; + k_temp_cell_leakage_power : 0.0 ; + k_process_cell_leakage_power : 0.0 ; + k_volt_internal_power : 0.0 ; + k_temp_internal_power : 0.0 ; + k_process_internal_power : 0.0 ; + + capacitive_load_unit (1,pf) ; + voltage_unit : "1V" ; + current_unit : "1uA" ; + time_unit : "1ns" ; + leakage_power_unit : "1nW" ; + pulling_resistance_unit : "1kohm"; + /* + ------------------------------------------------------------------------------------------ + implicit units overview: + cell_area unit : "um" + internal_power unit : "1e-12 * J/toggle = 1 * uW/MHz" + (capacitive_load_unit * voltage_unit^2) per toggle event + ------------------------------------------------------------------------------------------ + */ + library_features(report_delay_calculation); + define_cell_area (pad_drivers,pad_driver_sites) ; + + lu_table_template(CLKTRAN_constraint_template) { + variable_1 : constrained_pin_transition; + index_1 ( "0.010, 0.050, 0.200, 0.400, 1.000" ); + } + lu_table_template(SRAM_load_template) { + variable_1 : total_output_net_capacitance; + index_1 ( "0.0008,0.0014,0.0051,0.0100,0.0339,0.0640" ); + } + lu_table_template(SIG2SRAM_constraint_template) { + variable_1 : related_pin_transition; + variable_2 : constrained_pin_transition; + index_1 ( "0.0080,0.0288,0.0616,0.1072,0.1920,0.3496,0.5952" ); + index_2 ( "0.0080,0.0288,0.0616,0.1072,0.1920,0.3496,0.5952" ); + } + + lu_table_template(SIG2SRAM_delay_template) { + variable_1 : input_net_transition; + variable_2 : total_output_net_capacitance; + index_1 ( "0.0080,0.0288,0.0616,0.1072,0.1920,0.3496,0.5952" ); + index_2 ( "0.0008,0.0014,0.0051,0.0100,0.0339,0.0640" ); + } + + type (D_7_0) { + base_type : array; + data_type : bit; + bit_width : 8; + bit_from : 7; + bit_to : 0; + downto : true; + } + + type (A_8_0) { + base_type : array; + data_type : bit; + bit_width : 9; + bit_from : 8; + bit_to : 0; + downto : true; + } + +cell(RM_IHPSG13_2P_512x8_c2_bm_bist) { +pg_pin (VDD) { + pg_type : primary_power; + voltage_name : VDD; +} +pg_pin (VDDARRAY) { + pg_type : primary_power; + voltage_name : VDDARRAY; +} +pg_pin (VSS) { + pg_type : primary_ground; + voltage_name : VSS; +} + +memory() { + type : ram; + address_width : 9; + word_width : 8; +} + +interface_timing : false; +bus_naming_style : "%s[%d]" ; +area : 57397.3309 ; + + pin(A_DLY) { + direction : input ; + capacitance : 0.00387999 ; + max_transition : "1" ; + related_power_pin : VDD; + related_ground_pin : VSS; + internal_power() { + rise_power("scalar") { + values (0); + } + fall_power("scalar") { + values (0); + } + } + } + +bus(A_ADDR) { + bus_type : A_8_0; + direction : input ; + capacitance : 0.0129586 ; + pin(A_ADDR[0]) { + capacitance : 0.0058687 ; + } + pin(A_ADDR[1]) { + capacitance : 0.00807137 ; + } + pin(A_ADDR[2]) { + capacitance : 0.0112051 ; + } + pin(A_ADDR[3]) { + capacitance : 0.00709524 ; + } + pin(A_ADDR[4]) { + capacitance : 0.00648778 ; + } + pin(A_ADDR[5]) { + capacitance : 0.011209 ; + } + pin(A_ADDR[6]) { + capacitance : 0.0140441 ; + } + pin(A_ADDR[7]) { + capacitance : 0.0111199 ; + } + max_transition : "0.5952" ; + pin(A_ADDR[8:0]) { + related_power_pin : VDD; + related_ground_pin : VSS; + internal_power() { + when : "A_MEN"; + rise_power("scalar"){ + values (0.0103); + } + fall_power("scalar"){ + values (0.0079); + } + } + internal_power() { + when : "!A_MEN"; + rise_power("scalar"){ + values (0.0141); + } + fall_power("scalar"){ + values (0.0033); + } + } + } + timing() { + timing_type : setup_rising; + related_pin : "A_CLK"; + when : "((A_WEN | A_REN)& A_MEN)" + sdf_cond : "A_RW_ACCESS" + + rise_constraint("SIG2SRAM_constraint_template") { + index_1("0.0080,0.0288,0.0616,0.1072,0.1920,0.3496,0.5952"); + index_2("0.0080,0.0288,0.0616,0.1072,0.1920,0.3496,0.5952"); + values ("-0.7371,-0.7176,-0.6863,-0.6434,-0.5652,-0.4168,-0.1980",\ +"-0.7566,-0.7371,-0.7059,-0.6629,-0.5848,-0.4363,-0.2137",\ +"-0.7879,-0.7645,-0.7332,-0.6902,-0.6121,-0.4637,-0.2449",\ +"-0.8309,-0.8074,-0.7762,-0.7332,-0.6551,-0.5066,-0.2879",\ +"-0.9051,-0.8895,-0.8543,-0.8113,-0.7332,-0.5887,-0.3660",\ +"-1.0418,-1.0262,-0.9949,-0.9480,-0.8699,-0.7293,-0.5027",\ +"-1.2684,-1.2449,-1.2176,-1.1707,-1.0965,-0.9480,-0.7293"); + } + + fall_constraint("SIG2SRAM_constraint_template") { + index_1("0.0080,0.0288,0.0616,0.1072,0.1920,0.3496,0.5952"); + index_2("0.0080,0.0288,0.0616,0.1072,0.1920,0.3496,0.5952"); + values ("-0.5926,-0.5730,-0.5418,-0.4988,-0.4246,-0.2879,-0.0730",\ +"-0.6121,-0.5926,-0.5613,-0.5223,-0.4441,-0.3074,-0.0887",\ +"-0.6395,-0.6199,-0.5926,-0.5496,-0.4715,-0.3348,-0.1160",\ +"-0.6863,-0.6668,-0.6355,-0.5965,-0.5184,-0.3777,-0.1590",\ +"-0.7605,-0.7410,-0.7137,-0.6746,-0.5926,-0.4559,-0.2410",\ +"-0.9012,-0.8816,-0.8504,-0.8113,-0.7332,-0.5926,-0.3895",\ +"-1.1238,-1.1043,-1.0769,-1.0379,-0.9559,-0.8191,-0.6004"); + } + } + + + timing() { + timing_type : hold_rising; + related_pin : "A_CLK"; + when : "((A_WEN | A_REN)& A_MEN)" + sdf_cond : "A_RW_ACCESS" + + rise_constraint("SIG2SRAM_constraint_template") { + index_1("0.0080,0.0288,0.0616,0.1072,0.1920,0.3496,0.5952"); + index_2("0.0080,0.0288,0.0616,0.1072,0.1920,0.3496,0.5952"); + values ("0.8488,0.8293,0.7980,0.7551,0.6730,0.5285,0.3059",\ +"0.8684,0.8488,0.8176,0.7746,0.6926,0.5480,0.3254",\ +"0.8996,0.8801,0.8449,0.8020,0.7238,0.5754,0.3527",\ +"0.9426,0.9191,0.8918,0.8488,0.7668,0.6223,0.3996",\ +"1.0168,1.0012,0.9699,0.9230,0.8449,0.7004,0.4777",\ +"1.1574,1.1379,1.1105,1.0598,0.9816,0.8371,0.6184",\ +"1.3801,1.3605,1.3254,1.2980,1.2043,1.0637,0.8371"); + } + + fall_constraint("SIG2SRAM_constraint_template") { + index_1("0.0080,0.0288,0.0616,0.1072,0.1920,0.3496,0.5952"); + index_2("0.0080,0.0288,0.0616,0.1072,0.1920,0.3496,0.5952"); + values ("0.6965,0.6770,0.6496,0.6066,0.5246,0.3918,0.1730",\ +"0.7160,0.6965,0.6652,0.6262,0.5441,0.4113,0.1965",\ +"0.7473,0.7277,0.6965,0.6535,0.5754,0.4426,0.2238",\ +"0.7863,0.7707,0.7395,0.7004,0.6223,0.4855,0.2629",\ +"0.8684,0.8449,0.8176,0.7785,0.7004,0.5637,0.3449",\ +"1.0051,0.9855,0.9855,0.9113,0.8332,0.7004,0.4895",\ +"1.2277,1.2082,1.1809,1.1379,1.0598,0.9230,0.7004"); + } + } +} +pin(A_WEN) { + direction : input ; + capacitance : 0.00313551 ; + max_transition : "0.5952" ; + related_power_pin : VDD; + related_ground_pin : VSS; + internal_power() { + when : "A_MEN"; + rise_power("scalar"){ + values (0.0036); + } + fall_power("scalar"){ + values (0.0007); + } + } + internal_power() { + when : "!A_MEN"; + rise_power("scalar"){ + values (0.0049); + } + fall_power("scalar"){ + values (0.0003); + } + } + timing() { + timing_type : setup_rising; + related_pin : "A_CLK"; + when : "A_MEN" + sdf_cond : "A_MEN" + + rise_constraint("SIG2SRAM_constraint_template") { + index_1("0.0080,0.0288,0.0616,0.1072,0.1920,0.3496,0.5952"); + index_2("0.0080,0.0288,0.0616,0.1072,0.1920,0.3496,0.5952"); + values ("0.3137,0.3332,0.3605,0.4035,0.4816,0.6223,0.8488",\ +"0.2980,0.3176,0.3410,0.3840,0.4660,0.6027,0.8293",\ +"0.2629,0.2824,0.3098,0.3527,0.4348,0.5754,0.7980",\ +"0.2199,0.2395,0.2668,0.3098,0.3918,0.5324,0.7590",\ +"0.1418,0.1613,0.1887,0.2316,0.3137,0.4348,0.6730",\ +"0.0012,0.0207,0.0520,0.0910,0.1730,0.3098,0.5285",\ +"-0.2215,-0.2020,-0.1746,-0.1277,-0.0496,0.0910,0.3098"); + } + + fall_constraint("SIG2SRAM_constraint_template") { + index_1("0.0080,0.0288,0.0616,0.1072,0.1920,0.3496,0.5952"); + index_2("0.0080,0.0288,0.0616,0.1072,0.1920,0.3496,0.5952"); + values ("0.4504,0.4699,0.4973,0.5324,0.6027,0.7355,0.9699",\ +"0.4309,0.4504,0.4777,0.5129,0.5910,0.7160,0.9504",\ +"0.3996,0.4191,0.4465,0.4816,0.5520,0.6848,0.9191",\ +"0.3605,0.3762,0.4035,0.4387,0.5168,0.6418,0.8723",\ +"0.2785,0.2980,0.3215,0.3605,0.4348,0.5637,0.7980",\ +"0.1379,0.1574,0.1809,0.2199,0.2980,0.4309,0.6457",\ +"-0.0809,-0.0613,-0.0340,0.0051,0.0832,0.2160,0.4191"); + } + } + + + timing() { + timing_type : hold_rising; + related_pin : "A_CLK"; + when : "A_MEN" + sdf_cond : "A_MEN" + + rise_constraint("SIG2SRAM_constraint_template") { + index_1("0.0080,0.0288,0.0616,0.1072,0.1920,0.3496,0.5952"); + index_2("0.0080,0.0288,0.0616,0.1072,0.1920,0.3496,0.5952"); + values ("0.3723,0.3527,0.3215,0.2785,0.1965,0.0559,-0.1668",\ +"0.3918,0.3723,0.3449,0.2980,0.2160,0.0754,-0.1473",\ +"0.4152,0.3996,0.3684,0.3254,0.2434,0.1066,-0.1199",\ +"0.4621,0.4465,0.4152,0.3723,0.2863,0.1496,-0.0730",\ +"0.5324,0.5207,0.4895,0.4465,0.3645,0.2199,0.0051",\ +"0.6770,0.6535,0.6301,0.5832,0.5090,0.3605,0.1418",\ +"0.9035,0.8879,0.8566,0.8137,0.7316,0.5871,0.3684"); + } + + fall_constraint("SIG2SRAM_constraint_template") { + index_1("0.0080,0.0288,0.0616,0.1072,0.1920,0.3496,0.5952"); + index_2("0.0080,0.0288,0.0616,0.1072,0.1920,0.3496,0.5952"); + values ("0.3762,0.3566,0.3293,0.2863,0.2043,0.0676,-0.1434",\ +"0.3957,0.3762,0.3488,0.3059,0.2238,0.0871,-0.1199",\ +"0.4230,0.4035,0.3723,0.3332,0.2512,0.1184,-0.0965",\ +"0.4660,0.4465,0.4191,0.3762,0.2941,0.1613,-0.0496",\ +"0.5324,0.5168,0.4973,0.4543,0.3723,0.2316,0.0285",\ +"0.6809,0.6613,0.6340,0.5910,0.5129,0.3645,0.1652",\ +"0.9113,0.8918,0.8605,0.8176,0.7395,0.5988,0.3879"); + } + } + } +pin(A_REN) { + direction : input ; + capacitance : 0.00381144 ; + max_transition : "0.5952" ; + related_power_pin : VDD; + related_ground_pin : VSS; + internal_power() { + when : "A_MEN"; + rise_power("scalar"){ + values (0.0040); + } + fall_power("scalar"){ + values (0.0015); + } + } + internal_power() { + when : "!A_MEN"; + rise_power("scalar"){ + values (0.0040); + } + fall_power("scalar"){ + values (0.0013); + } + } + timing() { + timing_type : setup_rising; + related_pin : "A_CLK"; + when : "A_MEN" + sdf_cond : "A_MEN" + + rise_constraint("SIG2SRAM_constraint_template") { + index_1("0.0080,0.0288,0.0616,0.1072,0.1920,0.3496,0.5952"); + index_2("0.0080,0.0288,0.0616,0.1072,0.1920,0.3496,0.5952"); + values ("-0.0770,-0.0574,-0.0262,0.0168,0.0949,0.2355,0.4582",\ +"-0.0965,-0.0770,-0.0457,-0.0027,0.0754,0.2160,0.4387",\ +"-0.1199,-0.1004,-0.0730,-0.0262,0.0520,0.1887,0.4113",\ +"-0.1590,-0.1434,-0.1160,-0.0730,0.0051,0.1457,0.3645",\ +"-0.2449,-0.2254,-0.1941,-0.1473,-0.0770,0.0676,0.2863",\ +"-0.3816,-0.3699,-0.3387,-0.2801,-0.2215,-0.0770,0.1457",\ +"-0.6121,-0.5926,-0.5613,-0.5145,-0.4363,-0.2996,-0.0730"); + } + + fall_constraint("SIG2SRAM_constraint_template") { + index_1("0.0080,0.0288,0.0616,0.1072,0.1920,0.3496,0.5952"); + index_2("0.0080,0.0288,0.0616,0.1072,0.1920,0.3496,0.5952"); + values ("0.1262,0.1457,0.1691,0.2121,0.2824,0.4191,0.6457",\ +"0.1105,0.1262,0.1496,0.1887,0.2629,0.3996,0.6262",\ +"0.0793,0.0949,0.1223,0.1652,0.2395,0.3684,0.5949",\ +"0.0363,0.0559,0.0793,0.1223,0.2004,0.3410,0.5520",\ +"-0.0457,-0.0262,0.0012,0.0441,0.1301,0.2629,0.4738",\ +"-0.1902,-0.1746,-0.1434,-0.1043,-0.0184,0.1223,0.3332",\ +"-0.4129,-0.3934,-0.3660,-0.3230,-0.2449,-0.1043,0.1105"); + } + } + + + timing() { + timing_type : hold_rising; + related_pin : "A_CLK"; + when : "A_MEN" + sdf_cond : "A_MEN" + + rise_constraint("SIG2SRAM_constraint_template") { + index_1("0.0080,0.0288,0.0616,0.1072,0.1920,0.3496,0.5952"); + index_2("0.0080,0.0288,0.0616,0.1072,0.1920,0.3496,0.5952"); + values ("0.4113,0.3918,0.3645,0.3176,0.2395,0.0988,-0.1238",\ +"0.4309,0.4113,0.3840,0.3371,0.2590,0.1184,-0.1043",\ +"0.4582,0.4387,0.4113,0.3645,0.2824,0.1457,-0.0770",\ +"0.5051,0.4816,0.4543,0.4074,0.3293,0.1887,-0.0340",\ +"0.5715,0.5598,0.5324,0.4895,0.4035,0.2512,0.0441",\ +"0.7043,0.7004,0.6730,0.6262,0.5402,0.3957,0.1809",\ +"0.9387,0.9270,0.8957,0.8527,0.7746,0.6262,0.4074"); + } + + fall_constraint("SIG2SRAM_constraint_template") { + index_1("0.0080,0.0288,0.0616,0.1072,0.1920,0.3496,0.5952"); + index_2("0.0080,0.0288,0.0616,0.1072,0.1920,0.3496,0.5952"); + values ("0.4152,0.3918,0.3645,0.3215,0.2395,0.1027,-0.1082",\ +"0.4309,0.4113,0.3801,0.3410,0.2590,0.1223,-0.0926",\ +"0.4582,0.4387,0.4074,0.3684,0.2863,0.1496,-0.0613",\ +"0.5012,0.4816,0.4504,0.4074,0.3293,0.1887,-0.0145",\ +"0.5715,0.5559,0.5285,0.4816,0.3996,0.2512,0.0598",\ +"0.7160,0.7004,0.6691,0.6262,0.5520,0.4035,0.2004",\ +"0.9387,0.9191,0.8957,0.8488,0.7707,0.6262,0.4113"); + } + } + } +pin(A_MEN) { + direction : input ; + capacitance : 0.00300347 ; + max_transition : "0.5952" ; + related_power_pin : VDD; + related_ground_pin : VSS; + internal_power() { + rise_power("scalar"){ + values (0.0092); + } + fall_power("scalar"){ + values (0.0001); + } + } + timing() { + timing_type : setup_rising; + related_pin : "A_CLK"; + + rise_constraint("SIG2SRAM_constraint_template") { + index_1("0.0080,0.0288,0.0616,0.1072,0.1920,0.3496,0.5952"); + index_2("0.0080,0.0288,0.0616,0.1072,0.1920,0.3496,0.5952"); + values ("0.3215,0.3449,0.3684,0.4113,0.4895,0.6301,0.8527",\ +"0.3059,0.3254,0.3527,0.3957,0.4738,0.6145,0.8371",\ +"0.2746,0.2941,0.3215,0.3645,0.4426,0.5871,0.8059",\ +"0.2316,0.2512,0.2785,0.3215,0.3996,0.5402,0.7629",\ +"0.1496,0.1730,0.1965,0.2395,0.3215,0.4660,0.6848",\ +"0.0090,0.0285,0.0598,0.1027,0.1809,0.3176,0.5402",\ +"-0.2098,-0.1902,-0.1668,-0.1199,-0.0418,0.0988,0.3137"); + } + + fall_constraint("SIG2SRAM_constraint_template") { + index_1("0.0080,0.0288,0.0616,0.1072,0.1920,0.3496,0.5952"); + index_2("0.0080,0.0288,0.0616,0.1072,0.1920,0.3496,0.5952"); + values ("0.4582,0.4738,0.5012,0.5363,0.6145,0.7395,0.9738",\ +"0.4387,0.4543,0.4816,0.5207,0.5910,0.7199,0.9582",\ +"0.4035,0.4230,0.4504,0.4855,0.5637,0.6887,0.9230",\ +"0.3645,0.3840,0.4074,0.4465,0.5285,0.6496,0.8840",\ +"0.2824,0.3020,0.3254,0.3645,0.4465,0.5715,0.7980",\ +"0.1418,0.1613,0.1887,0.2238,0.3020,0.4309,0.6496",\ +"-0.0770,-0.0574,-0.0301,0.0090,0.0910,0.2238,0.4191"); + } + } + + + timing() { + timing_type : hold_rising; + related_pin : "A_CLK"; + + rise_constraint("SIG2SRAM_constraint_template") { + index_1("0.0080,0.0288,0.0616,0.1072,0.1920,0.3496,0.5952"); + index_2("0.0080,0.0288,0.0616,0.1072,0.1920,0.3496,0.5952"); + values ("0.3762,0.3605,0.3293,0.2863,0.2043,0.0637,-0.1629",\ +"0.3996,0.3801,0.3488,0.3020,0.2238,0.0832,-0.1395",\ +"0.4230,0.4074,0.3723,0.3293,0.2473,0.1105,-0.1121",\ +"0.4621,0.4465,0.4152,0.3762,0.2941,0.1535,-0.0691",\ +"0.5441,0.5285,0.4973,0.4465,0.3684,0.2316,0.0090",\ +"0.6848,0.6652,0.6301,0.5910,0.5129,0.3605,0.1496",\ +"0.9074,0.8918,0.8566,0.8215,0.7395,0.5910,0.3723"); + } + + fall_constraint("SIG2SRAM_constraint_template") { + index_1("0.0080,0.0288,0.0616,0.1072,0.1920,0.3496,0.5952"); + index_2("0.0080,0.0288,0.0616,0.1072,0.1920,0.3496,0.5952"); + values ("0.3762,0.3605,0.3332,0.2863,0.2043,0.0715,-0.1395",\ +"0.3996,0.3762,0.3488,0.3059,0.2238,0.0910,-0.1199",\ +"0.4270,0.4035,0.3762,0.3332,0.2512,0.1184,-0.0965",\ +"0.4699,0.4504,0.4191,0.3762,0.2941,0.1613,-0.0496",\ +"0.5441,0.5285,0.4973,0.4543,0.3762,0.2355,0.0324",\ +"0.6770,0.6613,0.6340,0.5949,0.5207,0.3762,0.1652",\ +"0.9074,0.8918,0.8605,0.8176,0.7395,0.6027,0.3918"); + } + } + } +bus(A_BM) { + bus_type : D_7_0; + direction : input ; + capacitance : 0.00359979 ; + max_transition : "0.5952" ; + pin(A_BM[7:0]) { + related_power_pin : VDD; + related_ground_pin : VSS; + internal_power() { + when : "A_MEN"; + rise_power("scalar"){ + values (0.0236); + } + fall_power("scalar"){ + values (0.0076); + } + } + internal_power() { + when : "!A_MEN"; + rise_power("scalar"){ + values (0.0230); + } + fall_power("scalar"){ + values (0.0072); + } + } + } + timing() { + timing_type : setup_rising; + related_pin : "A_CLK"; + when : "(A_WEN & A_MEN)" + sdf_cond : "A_RW_ACCESS" + + rise_constraint("SIG2SRAM_constraint_template") { + index_1("0.0080,0.0288,0.0616,0.1072,0.1920,0.3496,0.5952"); + index_2("0.0080,0.0288,0.0616,0.1072,0.1920,0.3496,0.5952"); + values ("-0.5886,-0.5690,-0.5437,-0.5007,-0.4196,-0.2741,-0.0515",\ +"-0.5960,-0.5765,-0.5511,-0.5082,-0.4271,-0.2816,-0.0589",\ +"-0.6056,-0.5861,-0.5607,-0.5177,-0.4367,-0.2912,-0.0685",\ +"-0.6188,-0.5992,-0.5739,-0.5309,-0.4498,-0.3043,-0.0817",\ +"-0.6430,-0.6235,-0.5981,-0.5551,-0.4741,-0.3286,-0.1059",\ +"-0.6735,-0.6539,-0.6285,-0.5856,-0.5045,-0.3590,-0.1364",\ +"-0.7551,-0.7356,-0.7102,-0.6672,-0.5861,-0.4406,-0.2180"); + } + + fall_constraint("SIG2SRAM_constraint_template") { + index_1("0.0080,0.0288,0.0616,0.1072,0.1920,0.3496,0.5952"); + index_2("0.0080,0.0288,0.0616,0.1072,0.1920,0.3496,0.5952"); + values ("-0.5261,-0.5085,-0.4812,-0.4421,-0.3591,-0.2233,-0.0114",\ +"-0.5335,-0.5160,-0.4886,-0.4496,-0.3665,-0.2308,-0.0189",\ +"-0.5431,-0.5255,-0.4982,-0.4591,-0.3761,-0.2404,-0.0285",\ +"-0.5563,-0.5387,-0.5114,-0.4723,-0.3893,-0.2535,-0.0416",\ +"-0.5805,-0.5629,-0.5356,-0.4965,-0.4135,-0.2778,-0.0659",\ +"-0.6110,-0.5934,-0.5660,-0.5270,-0.4440,-0.3082,-0.0963",\ +"-0.6926,-0.6750,-0.6477,-0.6086,-0.5256,-0.3898,-0.1779"); + } + } + + + timing() { + timing_type : hold_rising; + related_pin : "A_CLK"; + when : "(A_WEN & A_MEN)" + sdf_cond : "A_RW_ACCESS" + + rise_constraint("SIG2SRAM_constraint_template") { + index_1("0.0080,0.0288,0.0616,0.1072,0.1920,0.3496,0.5952"); + index_2("0.0080,0.0288,0.0616,0.1072,0.1920,0.3496,0.5952"); + values ("0.7036,0.6821,0.6577,0.6147,0.5347,0.3882,0.1655",\ +"0.7111,0.6896,0.6652,0.6222,0.5421,0.3956,0.1730",\ +"0.7207,0.6992,0.6747,0.6318,0.5517,0.4052,0.1826",\ +"0.7338,0.7123,0.6879,0.6449,0.5649,0.4184,0.1957",\ +"0.7581,0.7366,0.7122,0.6692,0.5891,0.4426,0.2200",\ +"0.7885,0.7670,0.7426,0.6996,0.6195,0.4731,0.2504",\ +"0.8701,0.8486,0.8242,0.7812,0.7012,0.5547,0.3320"); + } + + fall_constraint("SIG2SRAM_constraint_template") { + index_1("0.0080,0.0288,0.0616,0.1072,0.1920,0.3496,0.5952"); + index_2("0.0080,0.0288,0.0616,0.1072,0.1920,0.3496,0.5952"); + values ("0.6294,0.6118,0.5845,0.5454,0.4624,0.3257,0.1147",\ +"0.6368,0.6193,0.5919,0.5529,0.4699,0.3331,0.1222",\ +"0.6464,0.6288,0.6015,0.5625,0.4794,0.3427,0.1318",\ +"0.6596,0.6420,0.6147,0.5756,0.4926,0.3559,0.1449",\ +"0.6838,0.6663,0.6389,0.5998,0.5168,0.3801,0.1692",\ +"0.7143,0.6967,0.6693,0.6303,0.5473,0.4106,0.1996",\ +"0.7959,0.7783,0.7510,0.7119,0.6289,0.4922,0.2812"); + } + } +} + pin(A_CLK) { + direction : input; + capacitance : 0.00378957; + max_transition : "0.5952"; + clock : "true" ; + pin_func_type : active_rising ; + + timing () { + timing_type : "min_pulse_width"; + related_pin : "A_CLK"; + rise_constraint("CLKTRAN_constraint_template") { + index_1("0.008,0.5952"); + values("0.4,0.4"); + } + } + + related_power_pin : VDD; + related_ground_pin : VSS; + + internal_power() { + when : "!A_MEN & !A_WEN & !A_REN"; + rise_power("scalar"){ + values (0); + } + fall_power("scalar"){ + values (0); + } + } + internal_power() { + when : "!A_MEN & A_WEN & !A_REN"; + rise_power("scalar"){ + values (0.4713); + } + fall_power("scalar"){ + values (0); + } + } + internal_power() { + when : "A_MEN & A_WEN & !A_REN"; + rise_power("scalar"){ + values (11.6226); + } + fall_power("scalar"){ + values (0); + } + } + internal_power() { + when : "A_MEN & A_WEN & A_REN"; + rise_power("scalar"){ + values (11.8843); + } + fall_power("scalar"){ + values (0); + } + } + internal_power() { + when : "A_MEN & !A_WEN & A_REN"; + rise_power("scalar"){ + values (9.1367); + } + fall_power("scalar"){ + values (0); + } + } + internal_power() { + when : "!A_MEN & !A_WEN & A_REN"; + rise_power("scalar"){ + values (0.2857); + } + fall_power("scalar"){ + values (0); + } + } + internal_power() { + when : "!A_MEN & A_WEN & A_REN"; + rise_power("scalar"){ + values (0.4823); + } + fall_power("scalar"){ + values (0); + } + } + internal_power() { + when : "A_MEN & !A_WEN & !A_REN"; + rise_power("scalar"){ + values (0); + } + fall_power("scalar"){ + values (0); + } + } + } + bus(A_DIN) { + bus_type : D_7_0; + direction : input ; + capacitance : 0.00502163 ; + memory_write() { + address : A_ADDR ; + clocked_on : A_CLK; + } + + max_transition : "0.5952" ; + pin(A_DIN[7:0]) { + related_power_pin : VDD; + related_ground_pin : VSS; + internal_power() { + when : "A_MEN"; + rise_power("scalar"){ + values (0.0236); + } + fall_power("scalar"){ + values (0.0076); + } + } + internal_power() { + when : "!A_MEN"; + rise_power("scalar"){ + values (0.0230); + } + fall_power("scalar"){ + values (0.0072); + } + } + } + timing() { + timing_type : setup_rising; + related_pin : "A_CLK"; + when : "(A_WEN & A_MEN)"; + sdf_cond : "A_W_ACCESS"; + + rise_constraint("SIG2SRAM_constraint_template") { + index_1("0.0080,0.0288,0.0616,0.1072,0.1920,0.3496,0.5952"); + index_2("0.0080,0.0288,0.0616,0.1072,0.1920,0.3496,0.5952"); + values ("-0.5886,-0.5690,-0.5437,-0.5007,-0.4196,-0.2741,-0.0515",\ +"-0.5960,-0.5765,-0.5511,-0.5082,-0.4271,-0.2816,-0.0589",\ +"-0.6056,-0.5861,-0.5607,-0.5177,-0.4367,-0.2912,-0.0685",\ +"-0.6188,-0.5992,-0.5739,-0.5309,-0.4498,-0.3043,-0.0817",\ +"-0.6430,-0.6235,-0.5981,-0.5551,-0.4741,-0.3286,-0.1059",\ +"-0.6735,-0.6539,-0.6285,-0.5856,-0.5045,-0.3590,-0.1364",\ +"-0.7551,-0.7356,-0.7102,-0.6672,-0.5861,-0.4406,-0.2180"); + } + + fall_constraint("SIG2SRAM_constraint_template") { + index_1("0.0080,0.0288,0.0616,0.1072,0.1920,0.3496,0.5952"); + index_2("0.0080,0.0288,0.0616,0.1072,0.1920,0.3496,0.5952"); + values ("-0.5261,-0.5085,-0.4812,-0.4421,-0.3591,-0.2233,-0.0114",\ +"-0.5335,-0.5160,-0.4886,-0.4496,-0.3665,-0.2308,-0.0189",\ +"-0.5431,-0.5255,-0.4982,-0.4591,-0.3761,-0.2404,-0.0285",\ +"-0.5563,-0.5387,-0.5114,-0.4723,-0.3893,-0.2535,-0.0416",\ +"-0.5805,-0.5629,-0.5356,-0.4965,-0.4135,-0.2778,-0.0659",\ +"-0.6110,-0.5934,-0.5660,-0.5270,-0.4440,-0.3082,-0.0963",\ +"-0.6926,-0.6750,-0.6477,-0.6086,-0.5256,-0.3898,-0.1779"); + } + } + + timing() { + timing_type : hold_rising; + related_pin : "A_CLK"; + when : "(A_WEN & A_MEN)"; + sdf_cond : "A_W_ACCESS"; + + rise_constraint("SIG2SRAM_constraint_template") { + index_1("0.0080,0.0288,0.0616,0.1072,0.1920,0.3496,0.5952"); + index_2("0.0080,0.0288,0.0616,0.1072,0.1920,0.3496,0.5952"); + values ("0.7036,0.6821,0.6577,0.6147,0.5347,0.3882,0.1655",\ +"0.7111,0.6896,0.6652,0.6222,0.5421,0.3956,0.1730",\ +"0.7207,0.6992,0.6747,0.6318,0.5517,0.4052,0.1826",\ +"0.7338,0.7123,0.6879,0.6449,0.5649,0.4184,0.1957",\ +"0.7581,0.7366,0.7122,0.6692,0.5891,0.4426,0.2200",\ +"0.7885,0.7670,0.7426,0.6996,0.6195,0.4731,0.2504",\ +"0.8701,0.8486,0.8242,0.7812,0.7012,0.5547,0.3320"); + } + + fall_constraint("SIG2SRAM_constraint_template") { + index_1("0.0080,0.0288,0.0616,0.1072,0.1920,0.3496,0.5952"); + index_2("0.0080,0.0288,0.0616,0.1072,0.1920,0.3496,0.5952"); + values ("0.6294,0.6118,0.5845,0.5454,0.4624,0.3257,0.1147",\ +"0.6368,0.6193,0.5919,0.5529,0.4699,0.3331,0.1222",\ +"0.6464,0.6288,0.6015,0.5625,0.4794,0.3427,0.1318",\ +"0.6596,0.6420,0.6147,0.5756,0.4926,0.3559,0.1449",\ +"0.6838,0.6663,0.6389,0.5998,0.5168,0.3801,0.1692",\ +"0.7143,0.6967,0.6693,0.6303,0.5473,0.4106,0.1996",\ +"0.7959,0.7783,0.7510,0.7119,0.6289,0.4922,0.2812"); + } + } + } + + pin(A_BIST_EN) { + direction : input ; + capacitance : 0.00387999 ; + max_transition : "1" ; + related_power_pin : VDD; + related_ground_pin : VSS; + internal_power() { + rise_power("scalar") { + values (0); + } + fall_power("scalar") { + values (0); + } + } + } + +bus(A_BIST_ADDR) { + bus_type : A_8_0; + direction : input ; + capacitance : 0.0129586 ; + pin(A_BIST_ADDR[0]) { + capacitance : 0.0058687 ; + } + pin(A_BIST_ADDR[1]) { + capacitance : 0.00807137 ; + } + pin(A_BIST_ADDR[2]) { + capacitance : 0.0112051 ; + } + pin(A_BIST_ADDR[3]) { + capacitance : 0.00709524 ; + } + pin(A_BIST_ADDR[4]) { + capacitance : 0.00648778 ; + } + pin(A_BIST_ADDR[5]) { + capacitance : 0.011209 ; + } + pin(A_BIST_ADDR[6]) { + capacitance : 0.0140441 ; + } + pin(A_BIST_ADDR[7]) { + capacitance : 0.0111199 ; + } + max_transition : "0.5952" ; + pin(A_BIST_ADDR[8:0]) { + related_power_pin : VDD; + related_ground_pin : VSS; + internal_power() { + when : "A_BIST_MEN"; + rise_power("scalar"){ + values (0.0103); + } + fall_power("scalar"){ + values (0.0079); + } + } + internal_power() { + when : "!A_BIST_MEN"; + rise_power("scalar"){ + values (0.0141); + } + fall_power("scalar"){ + values (0.0033); + } + } + } + timing() { + timing_type : setup_rising; + related_pin : "A_BIST_CLK"; + when : "((A_BIST_WEN | A_BIST_REN)& A_BIST_MEN)" + sdf_cond : "A_BIST_RW_ACCESS" + + rise_constraint("SIG2SRAM_constraint_template") { + index_1("0.0080,0.0288,0.0616,0.1072,0.1920,0.3496,0.5952"); + index_2("0.0080,0.0288,0.0616,0.1072,0.1920,0.3496,0.5952"); + values ("-0.7371,-0.7176,-0.6863,-0.6434,-0.5652,-0.4168,-0.1980",\ +"-0.7566,-0.7371,-0.7059,-0.6629,-0.5848,-0.4363,-0.2137",\ +"-0.7879,-0.7645,-0.7332,-0.6902,-0.6121,-0.4637,-0.2449",\ +"-0.8309,-0.8074,-0.7762,-0.7332,-0.6551,-0.5066,-0.2879",\ +"-0.9051,-0.8895,-0.8543,-0.8113,-0.7332,-0.5887,-0.3660",\ +"-1.0418,-1.0262,-0.9949,-0.9480,-0.8699,-0.7293,-0.5027",\ +"-1.2684,-1.2449,-1.2176,-1.1707,-1.0965,-0.9480,-0.7293"); + } + + fall_constraint("SIG2SRAM_constraint_template") { + index_1("0.0080,0.0288,0.0616,0.1072,0.1920,0.3496,0.5952"); + index_2("0.0080,0.0288,0.0616,0.1072,0.1920,0.3496,0.5952"); + values ("-0.5926,-0.5730,-0.5418,-0.4988,-0.4246,-0.2879,-0.0730",\ +"-0.6121,-0.5926,-0.5613,-0.5223,-0.4441,-0.3074,-0.0887",\ +"-0.6395,-0.6199,-0.5926,-0.5496,-0.4715,-0.3348,-0.1160",\ +"-0.6863,-0.6668,-0.6355,-0.5965,-0.5184,-0.3777,-0.1590",\ +"-0.7605,-0.7410,-0.7137,-0.6746,-0.5926,-0.4559,-0.2410",\ +"-0.9012,-0.8816,-0.8504,-0.8113,-0.7332,-0.5926,-0.3895",\ +"-1.1238,-1.1043,-1.0769,-1.0379,-0.9559,-0.8191,-0.6004"); + } + } + + + timing() { + timing_type : hold_rising; + related_pin : "A_BIST_CLK"; + when : "((A_BIST_WEN | A_BIST_REN)& A_BIST_MEN)" + sdf_cond : "A_BIST_RW_ACCESS" + + rise_constraint("SIG2SRAM_constraint_template") { + index_1("0.0080,0.0288,0.0616,0.1072,0.1920,0.3496,0.5952"); + index_2("0.0080,0.0288,0.0616,0.1072,0.1920,0.3496,0.5952"); + values ("0.8488,0.8293,0.7980,0.7551,0.6730,0.5285,0.3059",\ +"0.8684,0.8488,0.8176,0.7746,0.6926,0.5480,0.3254",\ +"0.8996,0.8801,0.8449,0.8020,0.7238,0.5754,0.3527",\ +"0.9426,0.9191,0.8918,0.8488,0.7668,0.6223,0.3996",\ +"1.0168,1.0012,0.9699,0.9230,0.8449,0.7004,0.4777",\ +"1.1574,1.1379,1.1105,1.0598,0.9816,0.8371,0.6184",\ +"1.3801,1.3605,1.3254,1.2980,1.2043,1.0637,0.8371"); + } + + fall_constraint("SIG2SRAM_constraint_template") { + index_1("0.0080,0.0288,0.0616,0.1072,0.1920,0.3496,0.5952"); + index_2("0.0080,0.0288,0.0616,0.1072,0.1920,0.3496,0.5952"); + values ("0.6965,0.6770,0.6496,0.6066,0.5246,0.3918,0.1730",\ +"0.7160,0.6965,0.6652,0.6262,0.5441,0.4113,0.1965",\ +"0.7473,0.7277,0.6965,0.6535,0.5754,0.4426,0.2238",\ +"0.7863,0.7707,0.7395,0.7004,0.6223,0.4855,0.2629",\ +"0.8684,0.8449,0.8176,0.7785,0.7004,0.5637,0.3449",\ +"1.0051,0.9855,0.9855,0.9113,0.8332,0.7004,0.4895",\ +"1.2277,1.2082,1.1809,1.1379,1.0598,0.9230,0.7004"); + } + } +} +pin(A_BIST_WEN) { + direction : input ; + capacitance : 0.00313551 ; + max_transition : "0.5952" ; + related_power_pin : VDD; + related_ground_pin : VSS; + internal_power() { + when : "A_BIST_MEN"; + rise_power("scalar"){ + values (0.0036); + } + fall_power("scalar"){ + values (0.0007); + } + } + internal_power() { + when : "!A_BIST_MEN"; + rise_power("scalar"){ + values (0.0049); + } + fall_power("scalar"){ + values (0.0003); + } + } + timing() { + timing_type : setup_rising; + related_pin : "A_BIST_CLK"; + when : "A_BIST_MEN" + sdf_cond : "A_BIST_MEN" + + rise_constraint("SIG2SRAM_constraint_template") { + index_1("0.0080,0.0288,0.0616,0.1072,0.1920,0.3496,0.5952"); + index_2("0.0080,0.0288,0.0616,0.1072,0.1920,0.3496,0.5952"); + values ("0.3137,0.3332,0.3605,0.4035,0.4816,0.6223,0.8488",\ +"0.2980,0.3176,0.3410,0.3840,0.4660,0.6027,0.8293",\ +"0.2629,0.2824,0.3098,0.3527,0.4348,0.5754,0.7980",\ +"0.2199,0.2395,0.2668,0.3098,0.3918,0.5324,0.7590",\ +"0.1418,0.1613,0.1887,0.2316,0.3137,0.4348,0.6730",\ +"0.0012,0.0207,0.0520,0.0910,0.1730,0.3098,0.5285",\ +"-0.2215,-0.2020,-0.1746,-0.1277,-0.0496,0.0910,0.3098"); + } + + fall_constraint("SIG2SRAM_constraint_template") { + index_1("0.0080,0.0288,0.0616,0.1072,0.1920,0.3496,0.5952"); + index_2("0.0080,0.0288,0.0616,0.1072,0.1920,0.3496,0.5952"); + values ("0.4504,0.4699,0.4973,0.5324,0.6027,0.7355,0.9699",\ +"0.4309,0.4504,0.4777,0.5129,0.5910,0.7160,0.9504",\ +"0.3996,0.4191,0.4465,0.4816,0.5520,0.6848,0.9191",\ +"0.3605,0.3762,0.4035,0.4387,0.5168,0.6418,0.8723",\ +"0.2785,0.2980,0.3215,0.3605,0.4348,0.5637,0.7980",\ +"0.1379,0.1574,0.1809,0.2199,0.2980,0.4309,0.6457",\ +"-0.0809,-0.0613,-0.0340,0.0051,0.0832,0.2160,0.4191"); + } + } + + + timing() { + timing_type : hold_rising; + related_pin : "A_BIST_CLK"; + when : "A_BIST_MEN" + sdf_cond : "A_BIST_MEN" + + rise_constraint("SIG2SRAM_constraint_template") { + index_1("0.0080,0.0288,0.0616,0.1072,0.1920,0.3496,0.5952"); + index_2("0.0080,0.0288,0.0616,0.1072,0.1920,0.3496,0.5952"); + values ("0.3723,0.3527,0.3215,0.2785,0.1965,0.0559,-0.1668",\ +"0.3918,0.3723,0.3449,0.2980,0.2160,0.0754,-0.1473",\ +"0.4152,0.3996,0.3684,0.3254,0.2434,0.1066,-0.1199",\ +"0.4621,0.4465,0.4152,0.3723,0.2863,0.1496,-0.0730",\ +"0.5324,0.5207,0.4895,0.4465,0.3645,0.2199,0.0051",\ +"0.6770,0.6535,0.6301,0.5832,0.5090,0.3605,0.1418",\ +"0.9035,0.8879,0.8566,0.8137,0.7316,0.5871,0.3684"); + } + + fall_constraint("SIG2SRAM_constraint_template") { + index_1("0.0080,0.0288,0.0616,0.1072,0.1920,0.3496,0.5952"); + index_2("0.0080,0.0288,0.0616,0.1072,0.1920,0.3496,0.5952"); + values ("0.3762,0.3566,0.3293,0.2863,0.2043,0.0676,-0.1434",\ +"0.3957,0.3762,0.3488,0.3059,0.2238,0.0871,-0.1199",\ +"0.4230,0.4035,0.3723,0.3332,0.2512,0.1184,-0.0965",\ +"0.4660,0.4465,0.4191,0.3762,0.2941,0.1613,-0.0496",\ +"0.5324,0.5168,0.4973,0.4543,0.3723,0.2316,0.0285",\ +"0.6809,0.6613,0.6340,0.5910,0.5129,0.3645,0.1652",\ +"0.9113,0.8918,0.8605,0.8176,0.7395,0.5988,0.3879"); + } + } + } +pin(A_BIST_REN) { + direction : input ; + capacitance : 0.00381144 ; + max_transition : "0.5952" ; + related_power_pin : VDD; + related_ground_pin : VSS; + internal_power() { + when : "A_BIST_MEN"; + rise_power("scalar"){ + values (0.0040); + } + fall_power("scalar"){ + values (0.0015); + } + } + internal_power() { + when : "!A_BIST_MEN"; + rise_power("scalar"){ + values (0.0040); + } + fall_power("scalar"){ + values (0.0013); + } + } + timing() { + timing_type : setup_rising; + related_pin : "A_BIST_CLK"; + when : "A_BIST_MEN" + sdf_cond : "A_BIST_MEN" + + rise_constraint("SIG2SRAM_constraint_template") { + index_1("0.0080,0.0288,0.0616,0.1072,0.1920,0.3496,0.5952"); + index_2("0.0080,0.0288,0.0616,0.1072,0.1920,0.3496,0.5952"); + values ("-0.0770,-0.0574,-0.0262,0.0168,0.0949,0.2355,0.4582",\ +"-0.0965,-0.0770,-0.0457,-0.0027,0.0754,0.2160,0.4387",\ +"-0.1199,-0.1004,-0.0730,-0.0262,0.0520,0.1887,0.4113",\ +"-0.1590,-0.1434,-0.1160,-0.0730,0.0051,0.1457,0.3645",\ +"-0.2449,-0.2254,-0.1941,-0.1473,-0.0770,0.0676,0.2863",\ +"-0.3816,-0.3699,-0.3387,-0.2801,-0.2215,-0.0770,0.1457",\ +"-0.6121,-0.5926,-0.5613,-0.5145,-0.4363,-0.2996,-0.0730"); + } + + fall_constraint("SIG2SRAM_constraint_template") { + index_1("0.0080,0.0288,0.0616,0.1072,0.1920,0.3496,0.5952"); + index_2("0.0080,0.0288,0.0616,0.1072,0.1920,0.3496,0.5952"); + values ("0.1262,0.1457,0.1691,0.2121,0.2824,0.4191,0.6457",\ +"0.1105,0.1262,0.1496,0.1887,0.2629,0.3996,0.6262",\ +"0.0793,0.0949,0.1223,0.1652,0.2395,0.3684,0.5949",\ +"0.0363,0.0559,0.0793,0.1223,0.2004,0.3410,0.5520",\ +"-0.0457,-0.0262,0.0012,0.0441,0.1301,0.2629,0.4738",\ +"-0.1902,-0.1746,-0.1434,-0.1043,-0.0184,0.1223,0.3332",\ +"-0.4129,-0.3934,-0.3660,-0.3230,-0.2449,-0.1043,0.1105"); + } + } + + + timing() { + timing_type : hold_rising; + related_pin : "A_BIST_CLK"; + when : "A_BIST_MEN" + sdf_cond : "A_BIST_MEN" + + rise_constraint("SIG2SRAM_constraint_template") { + index_1("0.0080,0.0288,0.0616,0.1072,0.1920,0.3496,0.5952"); + index_2("0.0080,0.0288,0.0616,0.1072,0.1920,0.3496,0.5952"); + values ("0.4113,0.3918,0.3645,0.3176,0.2395,0.0988,-0.1238",\ +"0.4309,0.4113,0.3840,0.3371,0.2590,0.1184,-0.1043",\ +"0.4582,0.4387,0.4113,0.3645,0.2824,0.1457,-0.0770",\ +"0.5051,0.4816,0.4543,0.4074,0.3293,0.1887,-0.0340",\ +"0.5715,0.5598,0.5324,0.4895,0.4035,0.2512,0.0441",\ +"0.7043,0.7004,0.6730,0.6262,0.5402,0.3957,0.1809",\ +"0.9387,0.9270,0.8957,0.8527,0.7746,0.6262,0.4074"); + } + + fall_constraint("SIG2SRAM_constraint_template") { + index_1("0.0080,0.0288,0.0616,0.1072,0.1920,0.3496,0.5952"); + index_2("0.0080,0.0288,0.0616,0.1072,0.1920,0.3496,0.5952"); + values ("0.4152,0.3918,0.3645,0.3215,0.2395,0.1027,-0.1082",\ +"0.4309,0.4113,0.3801,0.3410,0.2590,0.1223,-0.0926",\ +"0.4582,0.4387,0.4074,0.3684,0.2863,0.1496,-0.0613",\ +"0.5012,0.4816,0.4504,0.4074,0.3293,0.1887,-0.0145",\ +"0.5715,0.5559,0.5285,0.4816,0.3996,0.2512,0.0598",\ +"0.7160,0.7004,0.6691,0.6262,0.5520,0.4035,0.2004",\ +"0.9387,0.9191,0.8957,0.8488,0.7707,0.6262,0.4113"); + } + } + } +pin(A_BIST_MEN) { + direction : input ; + capacitance : 0.00300347 ; + max_transition : "0.5952" ; + related_power_pin : VDD; + related_ground_pin : VSS; + internal_power() { + rise_power("scalar"){ + values (0.0092); + } + fall_power("scalar"){ + values (0.0001); + } + } + timing() { + timing_type : setup_rising; + related_pin : "A_BIST_CLK"; + + rise_constraint("SIG2SRAM_constraint_template") { + index_1("0.0080,0.0288,0.0616,0.1072,0.1920,0.3496,0.5952"); + index_2("0.0080,0.0288,0.0616,0.1072,0.1920,0.3496,0.5952"); + values ("0.3215,0.3449,0.3684,0.4113,0.4895,0.6301,0.8527",\ +"0.3059,0.3254,0.3527,0.3957,0.4738,0.6145,0.8371",\ +"0.2746,0.2941,0.3215,0.3645,0.4426,0.5871,0.8059",\ +"0.2316,0.2512,0.2785,0.3215,0.3996,0.5402,0.7629",\ +"0.1496,0.1730,0.1965,0.2395,0.3215,0.4660,0.6848",\ +"0.0090,0.0285,0.0598,0.1027,0.1809,0.3176,0.5402",\ +"-0.2098,-0.1902,-0.1668,-0.1199,-0.0418,0.0988,0.3137"); + } + + fall_constraint("SIG2SRAM_constraint_template") { + index_1("0.0080,0.0288,0.0616,0.1072,0.1920,0.3496,0.5952"); + index_2("0.0080,0.0288,0.0616,0.1072,0.1920,0.3496,0.5952"); + values ("0.4582,0.4738,0.5012,0.5363,0.6145,0.7395,0.9738",\ +"0.4387,0.4543,0.4816,0.5207,0.5910,0.7199,0.9582",\ +"0.4035,0.4230,0.4504,0.4855,0.5637,0.6887,0.9230",\ +"0.3645,0.3840,0.4074,0.4465,0.5285,0.6496,0.8840",\ +"0.2824,0.3020,0.3254,0.3645,0.4465,0.5715,0.7980",\ +"0.1418,0.1613,0.1887,0.2238,0.3020,0.4309,0.6496",\ +"-0.0770,-0.0574,-0.0301,0.0090,0.0910,0.2238,0.4191"); + } + } + + + timing() { + timing_type : hold_rising; + related_pin : "A_BIST_CLK"; + + rise_constraint("SIG2SRAM_constraint_template") { + index_1("0.0080,0.0288,0.0616,0.1072,0.1920,0.3496,0.5952"); + index_2("0.0080,0.0288,0.0616,0.1072,0.1920,0.3496,0.5952"); + values ("0.3762,0.3605,0.3293,0.2863,0.2043,0.0637,-0.1629",\ +"0.3996,0.3801,0.3488,0.3020,0.2238,0.0832,-0.1395",\ +"0.4230,0.4074,0.3723,0.3293,0.2473,0.1105,-0.1121",\ +"0.4621,0.4465,0.4152,0.3762,0.2941,0.1535,-0.0691",\ +"0.5441,0.5285,0.4973,0.4465,0.3684,0.2316,0.0090",\ +"0.6848,0.6652,0.6301,0.5910,0.5129,0.3605,0.1496",\ +"0.9074,0.8918,0.8566,0.8215,0.7395,0.5910,0.3723"); + } + + fall_constraint("SIG2SRAM_constraint_template") { + index_1("0.0080,0.0288,0.0616,0.1072,0.1920,0.3496,0.5952"); + index_2("0.0080,0.0288,0.0616,0.1072,0.1920,0.3496,0.5952"); + values ("0.3762,0.3605,0.3332,0.2863,0.2043,0.0715,-0.1395",\ +"0.3996,0.3762,0.3488,0.3059,0.2238,0.0910,-0.1199",\ +"0.4270,0.4035,0.3762,0.3332,0.2512,0.1184,-0.0965",\ +"0.4699,0.4504,0.4191,0.3762,0.2941,0.1613,-0.0496",\ +"0.5441,0.5285,0.4973,0.4543,0.3762,0.2355,0.0324",\ +"0.6770,0.6613,0.6340,0.5949,0.5207,0.3762,0.1652",\ +"0.9074,0.8918,0.8605,0.8176,0.7395,0.6027,0.3918"); + } + } + } +bus(A_BIST_BM) { + bus_type : D_7_0; + direction : input ; + capacitance : 0.00347781 ; + max_transition : "0.5952" ; + pin(A_BIST_BM[7:0]) { + related_power_pin : VDD; + related_ground_pin : VSS; + internal_power() { + when : "A_BIST_MEN"; + rise_power("scalar"){ + values (0.0236); + } + fall_power("scalar"){ + values (0.0076); + } + } + internal_power() { + when : "!A_BIST_MEN"; + rise_power("scalar"){ + values (0.0230); + } + fall_power("scalar"){ + values (0.0072); + } + } + } + timing() { + timing_type : setup_rising; + related_pin : "A_BIST_CLK"; + when : "(A_BIST_WEN & A_BIST_MEN)" + sdf_cond : "A_BIST_RW_ACCESS" + + rise_constraint("SIG2SRAM_constraint_template") { + index_1("0.0080,0.0288,0.0616,0.1072,0.1920,0.3496,0.5952"); + index_2("0.0080,0.0288,0.0616,0.1072,0.1920,0.3496,0.5952"); + values ("-0.5886,-0.5690,-0.5437,-0.5007,-0.4196,-0.2741,-0.0515",\ +"-0.5960,-0.5765,-0.5511,-0.5082,-0.4271,-0.2816,-0.0589",\ +"-0.6056,-0.5861,-0.5607,-0.5177,-0.4367,-0.2912,-0.0685",\ +"-0.6188,-0.5992,-0.5739,-0.5309,-0.4498,-0.3043,-0.0817",\ +"-0.6430,-0.6235,-0.5981,-0.5551,-0.4741,-0.3286,-0.1059",\ +"-0.6735,-0.6539,-0.6285,-0.5856,-0.5045,-0.3590,-0.1364",\ +"-0.7551,-0.7356,-0.7102,-0.6672,-0.5861,-0.4406,-0.2180"); + } + + fall_constraint("SIG2SRAM_constraint_template") { + index_1("0.0080,0.0288,0.0616,0.1072,0.1920,0.3496,0.5952"); + index_2("0.0080,0.0288,0.0616,0.1072,0.1920,0.3496,0.5952"); + values ("-0.5261,-0.5085,-0.4812,-0.4421,-0.3591,-0.2233,-0.0114",\ +"-0.5335,-0.5160,-0.4886,-0.4496,-0.3665,-0.2308,-0.0189",\ +"-0.5431,-0.5255,-0.4982,-0.4591,-0.3761,-0.2404,-0.0285",\ +"-0.5563,-0.5387,-0.5114,-0.4723,-0.3893,-0.2535,-0.0416",\ +"-0.5805,-0.5629,-0.5356,-0.4965,-0.4135,-0.2778,-0.0659",\ +"-0.6110,-0.5934,-0.5660,-0.5270,-0.4440,-0.3082,-0.0963",\ +"-0.6926,-0.6750,-0.6477,-0.6086,-0.5256,-0.3898,-0.1779"); + } + } + + + timing() { + timing_type : hold_rising; + related_pin : "A_BIST_CLK"; + when : "(A_BIST_WEN & A_BIST_MEN)" + sdf_cond : "A_BIST_RW_ACCESS" + + rise_constraint("SIG2SRAM_constraint_template") { + index_1("0.0080,0.0288,0.0616,0.1072,0.1920,0.3496,0.5952"); + index_2("0.0080,0.0288,0.0616,0.1072,0.1920,0.3496,0.5952"); + values ("0.7036,0.6821,0.6577,0.6147,0.5347,0.3882,0.1655",\ +"0.7111,0.6896,0.6652,0.6222,0.5421,0.3956,0.1730",\ +"0.7207,0.6992,0.6747,0.6318,0.5517,0.4052,0.1826",\ +"0.7338,0.7123,0.6879,0.6449,0.5649,0.4184,0.1957",\ +"0.7581,0.7366,0.7122,0.6692,0.5891,0.4426,0.2200",\ +"0.7885,0.7670,0.7426,0.6996,0.6195,0.4731,0.2504",\ +"0.8701,0.8486,0.8242,0.7812,0.7012,0.5547,0.3320"); + } + + fall_constraint("SIG2SRAM_constraint_template") { + index_1("0.0080,0.0288,0.0616,0.1072,0.1920,0.3496,0.5952"); + index_2("0.0080,0.0288,0.0616,0.1072,0.1920,0.3496,0.5952"); + values ("0.6294,0.6118,0.5845,0.5454,0.4624,0.3257,0.1147",\ +"0.6368,0.6193,0.5919,0.5529,0.4699,0.3331,0.1222",\ +"0.6464,0.6288,0.6015,0.5625,0.4794,0.3427,0.1318",\ +"0.6596,0.6420,0.6147,0.5756,0.4926,0.3559,0.1449",\ +"0.6838,0.6663,0.6389,0.5998,0.5168,0.3801,0.1692",\ +"0.7143,0.6967,0.6693,0.6303,0.5473,0.4106,0.1996",\ +"0.7959,0.7783,0.7510,0.7119,0.6289,0.4922,0.2812"); + } + } +} + pin(A_BIST_CLK) { + direction : input; + capacitance : 0.00378957; + max_transition : "0.5952"; + clock : "true" ; + pin_func_type : active_rising ; + + timing () { + timing_type : "min_pulse_width"; + related_pin : "A_BIST_CLK"; + rise_constraint("CLKTRAN_constraint_template") { + index_1("0.008,0.5952"); + values("0.4,0.4"); + } + } + + related_power_pin : VDD; + related_ground_pin : VSS; + + internal_power() { + when : "!A_BIST_MEN & !A_BIST_WEN & !A_BIST_REN"; + rise_power("scalar"){ + values (0); + } + fall_power("scalar"){ + values (0); + } + } + internal_power() { + when : "!A_BIST_MEN & A_BIST_WEN & !A_BIST_REN"; + rise_power("scalar"){ + values (0.4713); + } + fall_power("scalar"){ + values (0); + } + } + internal_power() { + when : "A_BIST_MEN & A_BIST_WEN & !A_BIST_REN"; + rise_power("scalar"){ + values (11.6226); + } + fall_power("scalar"){ + values (0); + } + } + internal_power() { + when : "A_BIST_MEN & A_BIST_WEN & A_BIST_REN"; + rise_power("scalar"){ + values (11.8843); + } + fall_power("scalar"){ + values (0); + } + } + internal_power() { + when : "A_BIST_MEN & !A_BIST_WEN & A_BIST_REN"; + rise_power("scalar"){ + values (9.1367); + } + fall_power("scalar"){ + values (0); + } + } + internal_power() { + when : "!A_BIST_MEN & !A_BIST_WEN & A_BIST_REN"; + rise_power("scalar"){ + values (0.2857); + } + fall_power("scalar"){ + values (0); + } + } + internal_power() { + when : "!A_BIST_MEN & A_BIST_WEN & A_BIST_REN"; + rise_power("scalar"){ + values (0.4823); + } + fall_power("scalar"){ + values (0); + } + } + internal_power() { + when : "A_BIST_MEN & !A_BIST_WEN & !A_BIST_REN"; + rise_power("scalar"){ + values (0); + } + fall_power("scalar"){ + values (0); + } + } + } + bus(A_BIST_DIN) { + bus_type : D_7_0; + direction : input ; + capacitance : 0.00396073 ; + memory_write() { + address : A_BIST_ADDR ; + clocked_on : A_BIST_CLK; + } + + max_transition : "0.5952" ; + pin(A_BIST_DIN[7:0]) { + related_power_pin : VDD; + related_ground_pin : VSS; + internal_power() { + when : "A_BIST_MEN"; + rise_power("scalar"){ + values (0.0236); + } + fall_power("scalar"){ + values (0.0076); + } + } + internal_power() { + when : "!A_BIST_MEN"; + rise_power("scalar"){ + values (0.0230); + } + fall_power("scalar"){ + values (0.0072); + } + } + } + timing() { + timing_type : setup_rising; + related_pin : "A_BIST_CLK"; + when : "(A_BIST_WEN & A_BIST_MEN)"; + sdf_cond : "A_BIST_W_ACCESS"; + + rise_constraint("SIG2SRAM_constraint_template") { + index_1("0.0080,0.0288,0.0616,0.1072,0.1920,0.3496,0.5952"); + index_2("0.0080,0.0288,0.0616,0.1072,0.1920,0.3496,0.5952"); + values ("-0.5886,-0.5690,-0.5437,-0.5007,-0.4196,-0.2741,-0.0515",\ +"-0.5960,-0.5765,-0.5511,-0.5082,-0.4271,-0.2816,-0.0589",\ +"-0.6056,-0.5861,-0.5607,-0.5177,-0.4367,-0.2912,-0.0685",\ +"-0.6188,-0.5992,-0.5739,-0.5309,-0.4498,-0.3043,-0.0817",\ +"-0.6430,-0.6235,-0.5981,-0.5551,-0.4741,-0.3286,-0.1059",\ +"-0.6735,-0.6539,-0.6285,-0.5856,-0.5045,-0.3590,-0.1364",\ +"-0.7551,-0.7356,-0.7102,-0.6672,-0.5861,-0.4406,-0.2180"); + } + + fall_constraint("SIG2SRAM_constraint_template") { + index_1("0.0080,0.0288,0.0616,0.1072,0.1920,0.3496,0.5952"); + index_2("0.0080,0.0288,0.0616,0.1072,0.1920,0.3496,0.5952"); + values ("-0.5261,-0.5085,-0.4812,-0.4421,-0.3591,-0.2233,-0.0114",\ +"-0.5335,-0.5160,-0.4886,-0.4496,-0.3665,-0.2308,-0.0189",\ +"-0.5431,-0.5255,-0.4982,-0.4591,-0.3761,-0.2404,-0.0285",\ +"-0.5563,-0.5387,-0.5114,-0.4723,-0.3893,-0.2535,-0.0416",\ +"-0.5805,-0.5629,-0.5356,-0.4965,-0.4135,-0.2778,-0.0659",\ +"-0.6110,-0.5934,-0.5660,-0.5270,-0.4440,-0.3082,-0.0963",\ +"-0.6926,-0.6750,-0.6477,-0.6086,-0.5256,-0.3898,-0.1779"); + } + } + + timing() { + timing_type : hold_rising; + related_pin : "A_BIST_CLK"; + when : "(A_BIST_WEN & A_BIST_MEN)"; + sdf_cond : "A_BIST_W_ACCESS"; + + rise_constraint("SIG2SRAM_constraint_template") { + index_1("0.0080,0.0288,0.0616,0.1072,0.1920,0.3496,0.5952"); + index_2("0.0080,0.0288,0.0616,0.1072,0.1920,0.3496,0.5952"); + values ("0.7036,0.6821,0.6577,0.6147,0.5347,0.3882,0.1655",\ +"0.7111,0.6896,0.6652,0.6222,0.5421,0.3956,0.1730",\ +"0.7207,0.6992,0.6747,0.6318,0.5517,0.4052,0.1826",\ +"0.7338,0.7123,0.6879,0.6449,0.5649,0.4184,0.1957",\ +"0.7581,0.7366,0.7122,0.6692,0.5891,0.4426,0.2200",\ +"0.7885,0.7670,0.7426,0.6996,0.6195,0.4731,0.2504",\ +"0.8701,0.8486,0.8242,0.7812,0.7012,0.5547,0.3320"); + } + + fall_constraint("SIG2SRAM_constraint_template") { + index_1("0.0080,0.0288,0.0616,0.1072,0.1920,0.3496,0.5952"); + index_2("0.0080,0.0288,0.0616,0.1072,0.1920,0.3496,0.5952"); + values ("0.6294,0.6118,0.5845,0.5454,0.4624,0.3257,0.1147",\ +"0.6368,0.6193,0.5919,0.5529,0.4699,0.3331,0.1222",\ +"0.6464,0.6288,0.6015,0.5625,0.4794,0.3427,0.1318",\ +"0.6596,0.6420,0.6147,0.5756,0.4926,0.3559,0.1449",\ +"0.6838,0.6663,0.6389,0.5998,0.5168,0.3801,0.1692",\ +"0.7143,0.6967,0.6693,0.6303,0.5473,0.4106,0.1996",\ +"0.7959,0.7783,0.7510,0.7119,0.6289,0.4922,0.2812"); + } + } + } + +bus(A_DOUT) { + + bus_type : D_7_0; + direction : output ; + capacitance : 0 ; + max_capacitance : 0.064 ; + memory_read() { + address : A_ADDR ; + } + pin(A_DOUT[7:0]) { + related_power_pin : VDD; + related_ground_pin : VSS; + internal_power() { + rise_power("scalar") { + values (0); + } + fall_power("scalar") { + values (0); + } + } + } + timing() { + related_pin : "A_CLK"; + timing_type : rising_edge ; + timing_sense : non_unate ; + + cell_rise(SIG2SRAM_delay_template) { + index_1("0.0080,0.0288,0.0616,0.1072,0.1920,0.3496,0.5952"); + index_2("0.0008,0.0014,0.0051,0.0100,0.0339,0.0640"); + values ("6.2592,6.2625,6.2747,6.2887,6.3412,6.3991",\ +"6.2635,6.2669,6.2791,6.2930,6.3456,6.4034",\ +"6.2740,6.2773,6.2895,6.3035,6.3560,6.4139",\ +"6.2946,6.2980,6.3102,6.3241,6.3767,6.4345",\ +"6.3089,6.3123,6.3244,6.3384,6.3909,6.4488",\ +"6.3423,6.3457,6.3579,6.3718,6.4244,6.4822",\ +"6.4280,6.4314,6.4436,6.4575,6.5101,6.5679"); + } + cell_fall(SIG2SRAM_delay_template) { + index_1("0.0080,0.0288,0.0616,0.1072,0.1920,0.3496,0.5952"); + index_2("0.0008,0.0014,0.0051,0.0100,0.0339,0.0640"); + values ("6.1494,6.1516,6.1617,6.1733,6.2167,6.2605",\ +"6.1538,6.1560,6.1660,6.1777,6.2211,6.2649",\ +"6.1642,6.1664,6.1765,6.1881,6.2315,6.2753",\ +"6.1849,6.1871,6.1971,6.2088,6.2521,6.2960",\ +"6.1992,6.2013,6.2114,6.2231,6.2664,6.3102",\ +"6.2326,6.2348,6.2448,6.2565,6.2998,6.3437",\ +"6.3183,6.3205,6.3305,6.3422,6.3855,6.4294"); + } + + rise_transition(SRAM_load_template) { + index_1("0.0008,0.0014,0.0051,0.0100,0.0339,0.0640"); + values ("0.0560,0.0583,0.0696,0.0816,0.1519,0.2335"); + } + fall_transition(SRAM_load_template) { + index_1("0.0008,0.0014,0.0051,0.0100,0.0339,0.0640"); + values ("0.0428,0.0445,0.0538,0.0658,0.1181,0.1751"); + } + } +} + pin(B_DLY) { + direction : input ; + capacitance : 0.00387999 ; + max_transition : "1" ; + related_power_pin : VDD; + related_ground_pin : VSS; + internal_power() { + rise_power("scalar") { + values (0); + } + fall_power("scalar") { + values (0); + } + } + } + +bus(B_ADDR) { + bus_type : A_8_0; + direction : input ; + capacitance : 0.0129586 ; + pin(B_ADDR[0]) { + capacitance : 0.00588404 ; + } + pin(B_ADDR[1]) { + capacitance : 0.0080425 ; + } + pin(B_ADDR[2]) { + capacitance : 0.0112051 ; + } + pin(B_ADDR[3]) { + capacitance : 0.00706428 ; + } + pin(B_ADDR[4]) { + capacitance : 0.00656149 ; + } + pin(B_ADDR[5]) { + capacitance : 0.0111839 ; + } + pin(B_ADDR[6]) { + capacitance : 0.0140236 ; + } + pin(B_ADDR[7]) { + capacitance : 0.0111118 ; + } + max_transition : "0.5952" ; + pin(B_ADDR[8:0]) { + related_power_pin : VDD; + related_ground_pin : VSS; + internal_power() { + when : "B_MEN"; + rise_power("scalar"){ + values (0.0103); + } + fall_power("scalar"){ + values (0.0079); + } + } + internal_power() { + when : "!B_MEN"; + rise_power("scalar"){ + values (0.0141); + } + fall_power("scalar"){ + values (0.0033); + } + } + } + timing() { + timing_type : setup_rising; + related_pin : "B_CLK"; + when : "((B_WEN | B_REN)& B_MEN)" + sdf_cond : "B_RW_ACCESS" + + rise_constraint("SIG2SRAM_constraint_template") { + index_1("0.0080,0.0288,0.0616,0.1072,0.1920,0.3496,0.5952"); + index_2("0.0080,0.0288,0.0616,0.1072,0.1920,0.3496,0.5952"); + values ("-0.7371,-0.7176,-0.6863,-0.6434,-0.5652,-0.4168,-0.1980",\ +"-0.7566,-0.7371,-0.7059,-0.6629,-0.5848,-0.4363,-0.2137",\ +"-0.7879,-0.7645,-0.7332,-0.6902,-0.6121,-0.4637,-0.2449",\ +"-0.8309,-0.8074,-0.7762,-0.7332,-0.6551,-0.5066,-0.2879",\ +"-0.9051,-0.8895,-0.8543,-0.8113,-0.7332,-0.5887,-0.3660",\ +"-1.0418,-1.0262,-0.9949,-0.9480,-0.8699,-0.7293,-0.5027",\ +"-1.2684,-1.2449,-1.2176,-1.1707,-1.0965,-0.9480,-0.7293"); + } + + fall_constraint("SIG2SRAM_constraint_template") { + index_1("0.0080,0.0288,0.0616,0.1072,0.1920,0.3496,0.5952"); + index_2("0.0080,0.0288,0.0616,0.1072,0.1920,0.3496,0.5952"); + values ("-0.5926,-0.5730,-0.5418,-0.4988,-0.4246,-0.2879,-0.0730",\ +"-0.6121,-0.5926,-0.5613,-0.5223,-0.4441,-0.3074,-0.0887",\ +"-0.6395,-0.6199,-0.5926,-0.5496,-0.4715,-0.3348,-0.1160",\ +"-0.6863,-0.6668,-0.6355,-0.5965,-0.5184,-0.3777,-0.1590",\ +"-0.7605,-0.7410,-0.7137,-0.6746,-0.5926,-0.4559,-0.2410",\ +"-0.9012,-0.8816,-0.8504,-0.8113,-0.7332,-0.5926,-0.3895",\ +"-1.1238,-1.1043,-1.0769,-1.0379,-0.9559,-0.8191,-0.6004"); + } + } + + + timing() { + timing_type : hold_rising; + related_pin : "B_CLK"; + when : "((B_WEN | B_REN)& B_MEN)" + sdf_cond : "B_RW_ACCESS" + + rise_constraint("SIG2SRAM_constraint_template") { + index_1("0.0080,0.0288,0.0616,0.1072,0.1920,0.3496,0.5952"); + index_2("0.0080,0.0288,0.0616,0.1072,0.1920,0.3496,0.5952"); + values ("0.8488,0.8293,0.7980,0.7551,0.6730,0.5285,0.3059",\ +"0.8684,0.8488,0.8176,0.7746,0.6926,0.5480,0.3254",\ +"0.8996,0.8801,0.8449,0.8020,0.7238,0.5754,0.3527",\ +"0.9426,0.9191,0.8918,0.8488,0.7668,0.6223,0.3996",\ +"1.0168,1.0012,0.9699,0.9230,0.8449,0.7004,0.4777",\ +"1.1574,1.1379,1.1105,1.0598,0.9816,0.8371,0.6184",\ +"1.3801,1.3605,1.3254,1.2980,1.2043,1.0637,0.8371"); + } + + fall_constraint("SIG2SRAM_constraint_template") { + index_1("0.0080,0.0288,0.0616,0.1072,0.1920,0.3496,0.5952"); + index_2("0.0080,0.0288,0.0616,0.1072,0.1920,0.3496,0.5952"); + values ("0.6965,0.6770,0.6496,0.6066,0.5246,0.3918,0.1730",\ +"0.7160,0.6965,0.6652,0.6262,0.5441,0.4113,0.1965",\ +"0.7473,0.7277,0.6965,0.6535,0.5754,0.4426,0.2238",\ +"0.7863,0.7707,0.7395,0.7004,0.6223,0.4855,0.2629",\ +"0.8684,0.8449,0.8176,0.7785,0.7004,0.5637,0.3449",\ +"1.0051,0.9855,0.9855,0.9113,0.8332,0.7004,0.4895",\ +"1.2277,1.2082,1.1809,1.1379,1.0598,0.9230,0.7004"); + } + } +} +pin(B_WEN) { + direction : input ; + capacitance : 0.00313551 ; + max_transition : "0.5952" ; + related_power_pin : VDD; + related_ground_pin : VSS; + internal_power() { + when : "B_MEN"; + rise_power("scalar"){ + values (0.0036); + } + fall_power("scalar"){ + values (0.0007); + } + } + internal_power() { + when : "!B_MEN"; + rise_power("scalar"){ + values (0.0049); + } + fall_power("scalar"){ + values (0.0003); + } + } + timing() { + timing_type : setup_rising; + related_pin : "B_CLK"; + when : "B_MEN" + sdf_cond : "B_MEN" + + rise_constraint("SIG2SRAM_constraint_template") { + index_1("0.0080,0.0288,0.0616,0.1072,0.1920,0.3496,0.5952"); + index_2("0.0080,0.0288,0.0616,0.1072,0.1920,0.3496,0.5952"); + values ("0.3137,0.3332,0.3605,0.4035,0.4816,0.6223,0.8488",\ +"0.2980,0.3176,0.3410,0.3840,0.4660,0.6027,0.8293",\ +"0.2629,0.2824,0.3098,0.3527,0.4348,0.5754,0.7980",\ +"0.2199,0.2395,0.2668,0.3098,0.3918,0.5324,0.7590",\ +"0.1418,0.1613,0.1887,0.2316,0.3137,0.4348,0.6730",\ +"0.0012,0.0207,0.0520,0.0910,0.1730,0.3098,0.5285",\ +"-0.2215,-0.2020,-0.1746,-0.1277,-0.0496,0.0910,0.3098"); + } + + fall_constraint("SIG2SRAM_constraint_template") { + index_1("0.0080,0.0288,0.0616,0.1072,0.1920,0.3496,0.5952"); + index_2("0.0080,0.0288,0.0616,0.1072,0.1920,0.3496,0.5952"); + values ("0.4504,0.4699,0.4973,0.5324,0.6027,0.7355,0.9699",\ +"0.4309,0.4504,0.4777,0.5129,0.5910,0.7160,0.9504",\ +"0.3996,0.4191,0.4465,0.4816,0.5520,0.6848,0.9191",\ +"0.3605,0.3762,0.4035,0.4387,0.5168,0.6418,0.8723",\ +"0.2785,0.2980,0.3215,0.3605,0.4348,0.5637,0.7980",\ +"0.1379,0.1574,0.1809,0.2199,0.2980,0.4309,0.6457",\ +"-0.0809,-0.0613,-0.0340,0.0051,0.0832,0.2160,0.4191"); + } + } + + + timing() { + timing_type : hold_rising; + related_pin : "B_CLK"; + when : "B_MEN" + sdf_cond : "B_MEN" + + rise_constraint("SIG2SRAM_constraint_template") { + index_1("0.0080,0.0288,0.0616,0.1072,0.1920,0.3496,0.5952"); + index_2("0.0080,0.0288,0.0616,0.1072,0.1920,0.3496,0.5952"); + values ("0.3723,0.3527,0.3215,0.2785,0.1965,0.0559,-0.1668",\ +"0.3918,0.3723,0.3449,0.2980,0.2160,0.0754,-0.1473",\ +"0.4152,0.3996,0.3684,0.3254,0.2434,0.1066,-0.1199",\ +"0.4621,0.4465,0.4152,0.3723,0.2863,0.1496,-0.0730",\ +"0.5324,0.5207,0.4895,0.4465,0.3645,0.2199,0.0051",\ +"0.6770,0.6535,0.6301,0.5832,0.5090,0.3605,0.1418",\ +"0.9035,0.8879,0.8566,0.8137,0.7316,0.5871,0.3684"); + } + + fall_constraint("SIG2SRAM_constraint_template") { + index_1("0.0080,0.0288,0.0616,0.1072,0.1920,0.3496,0.5952"); + index_2("0.0080,0.0288,0.0616,0.1072,0.1920,0.3496,0.5952"); + values ("0.3762,0.3566,0.3293,0.2863,0.2043,0.0676,-0.1434",\ +"0.3957,0.3762,0.3488,0.3059,0.2238,0.0871,-0.1199",\ +"0.4230,0.4035,0.3723,0.3332,0.2512,0.1184,-0.0965",\ +"0.4660,0.4465,0.4191,0.3762,0.2941,0.1613,-0.0496",\ +"0.5324,0.5168,0.4973,0.4543,0.3723,0.2316,0.0285",\ +"0.6809,0.6613,0.6340,0.5910,0.5129,0.3645,0.1652",\ +"0.9113,0.8918,0.8605,0.8176,0.7395,0.5988,0.3879"); + } + } + } +pin(B_REN) { + direction : input ; + capacitance : 0.00381144 ; + max_transition : "0.5952" ; + related_power_pin : VDD; + related_ground_pin : VSS; + internal_power() { + when : "B_MEN"; + rise_power("scalar"){ + values (0.0040); + } + fall_power("scalar"){ + values (0.0015); + } + } + internal_power() { + when : "!B_MEN"; + rise_power("scalar"){ + values (0.0040); + } + fall_power("scalar"){ + values (0.0013); + } + } + timing() { + timing_type : setup_rising; + related_pin : "B_CLK"; + when : "B_MEN" + sdf_cond : "B_MEN" + + rise_constraint("SIG2SRAM_constraint_template") { + index_1("0.0080,0.0288,0.0616,0.1072,0.1920,0.3496,0.5952"); + index_2("0.0080,0.0288,0.0616,0.1072,0.1920,0.3496,0.5952"); + values ("-0.0770,-0.0574,-0.0262,0.0168,0.0949,0.2355,0.4582",\ +"-0.0965,-0.0770,-0.0457,-0.0027,0.0754,0.2160,0.4387",\ +"-0.1199,-0.1004,-0.0730,-0.0262,0.0520,0.1887,0.4113",\ +"-0.1590,-0.1434,-0.1160,-0.0730,0.0051,0.1457,0.3645",\ +"-0.2449,-0.2254,-0.1941,-0.1473,-0.0770,0.0676,0.2863",\ +"-0.3816,-0.3699,-0.3387,-0.2801,-0.2215,-0.0770,0.1457",\ +"-0.6121,-0.5926,-0.5613,-0.5145,-0.4363,-0.2996,-0.0730"); + } + + fall_constraint("SIG2SRAM_constraint_template") { + index_1("0.0080,0.0288,0.0616,0.1072,0.1920,0.3496,0.5952"); + index_2("0.0080,0.0288,0.0616,0.1072,0.1920,0.3496,0.5952"); + values ("0.1262,0.1457,0.1691,0.2121,0.2824,0.4191,0.6457",\ +"0.1105,0.1262,0.1496,0.1887,0.2629,0.3996,0.6262",\ +"0.0793,0.0949,0.1223,0.1652,0.2395,0.3684,0.5949",\ +"0.0363,0.0559,0.0793,0.1223,0.2004,0.3410,0.5520",\ +"-0.0457,-0.0262,0.0012,0.0441,0.1301,0.2629,0.4738",\ +"-0.1902,-0.1746,-0.1434,-0.1043,-0.0184,0.1223,0.3332",\ +"-0.4129,-0.3934,-0.3660,-0.3230,-0.2449,-0.1043,0.1105"); + } + } + + + timing() { + timing_type : hold_rising; + related_pin : "B_CLK"; + when : "B_MEN" + sdf_cond : "B_MEN" + + rise_constraint("SIG2SRAM_constraint_template") { + index_1("0.0080,0.0288,0.0616,0.1072,0.1920,0.3496,0.5952"); + index_2("0.0080,0.0288,0.0616,0.1072,0.1920,0.3496,0.5952"); + values ("0.4113,0.3918,0.3645,0.3176,0.2395,0.0988,-0.1238",\ +"0.4309,0.4113,0.3840,0.3371,0.2590,0.1184,-0.1043",\ +"0.4582,0.4387,0.4113,0.3645,0.2824,0.1457,-0.0770",\ +"0.5051,0.4816,0.4543,0.4074,0.3293,0.1887,-0.0340",\ +"0.5715,0.5598,0.5324,0.4895,0.4035,0.2512,0.0441",\ +"0.7043,0.7004,0.6730,0.6262,0.5402,0.3957,0.1809",\ +"0.9387,0.9270,0.8957,0.8527,0.7746,0.6262,0.4074"); + } + + fall_constraint("SIG2SRAM_constraint_template") { + index_1("0.0080,0.0288,0.0616,0.1072,0.1920,0.3496,0.5952"); + index_2("0.0080,0.0288,0.0616,0.1072,0.1920,0.3496,0.5952"); + values ("0.4152,0.3918,0.3645,0.3215,0.2395,0.1027,-0.1082",\ +"0.4309,0.4113,0.3801,0.3410,0.2590,0.1223,-0.0926",\ +"0.4582,0.4387,0.4074,0.3684,0.2863,0.1496,-0.0613",\ +"0.5012,0.4816,0.4504,0.4074,0.3293,0.1887,-0.0145",\ +"0.5715,0.5559,0.5285,0.4816,0.3996,0.2512,0.0598",\ +"0.7160,0.7004,0.6691,0.6262,0.5520,0.4035,0.2004",\ +"0.9387,0.9191,0.8957,0.8488,0.7707,0.6262,0.4113"); + } + } + } +pin(B_MEN) { + direction : input ; + capacitance : 0.00300347 ; + max_transition : "0.5952" ; + related_power_pin : VDD; + related_ground_pin : VSS; + internal_power() { + rise_power("scalar"){ + values (0.0092); + } + fall_power("scalar"){ + values (0.0001); + } + } + timing() { + timing_type : setup_rising; + related_pin : "B_CLK"; + + rise_constraint("SIG2SRAM_constraint_template") { + index_1("0.0080,0.0288,0.0616,0.1072,0.1920,0.3496,0.5952"); + index_2("0.0080,0.0288,0.0616,0.1072,0.1920,0.3496,0.5952"); + values ("0.3215,0.3449,0.3684,0.4113,0.4895,0.6301,0.8527",\ +"0.3059,0.3254,0.3527,0.3957,0.4738,0.6145,0.8371",\ +"0.2746,0.2941,0.3215,0.3645,0.4426,0.5871,0.8059",\ +"0.2316,0.2512,0.2785,0.3215,0.3996,0.5402,0.7629",\ +"0.1496,0.1730,0.1965,0.2395,0.3215,0.4660,0.6848",\ +"0.0090,0.0285,0.0598,0.1027,0.1809,0.3176,0.5402",\ +"-0.2098,-0.1902,-0.1668,-0.1199,-0.0418,0.0988,0.3137"); + } + + fall_constraint("SIG2SRAM_constraint_template") { + index_1("0.0080,0.0288,0.0616,0.1072,0.1920,0.3496,0.5952"); + index_2("0.0080,0.0288,0.0616,0.1072,0.1920,0.3496,0.5952"); + values ("0.4582,0.4738,0.5012,0.5363,0.6145,0.7395,0.9738",\ +"0.4387,0.4543,0.4816,0.5207,0.5910,0.7199,0.9582",\ +"0.4035,0.4230,0.4504,0.4855,0.5637,0.6887,0.9230",\ +"0.3645,0.3840,0.4074,0.4465,0.5285,0.6496,0.8840",\ +"0.2824,0.3020,0.3254,0.3645,0.4465,0.5715,0.7980",\ +"0.1418,0.1613,0.1887,0.2238,0.3020,0.4309,0.6496",\ +"-0.0770,-0.0574,-0.0301,0.0090,0.0910,0.2238,0.4191"); + } + } + + + timing() { + timing_type : hold_rising; + related_pin : "B_CLK"; + + rise_constraint("SIG2SRAM_constraint_template") { + index_1("0.0080,0.0288,0.0616,0.1072,0.1920,0.3496,0.5952"); + index_2("0.0080,0.0288,0.0616,0.1072,0.1920,0.3496,0.5952"); + values ("0.3762,0.3605,0.3293,0.2863,0.2043,0.0637,-0.1629",\ +"0.3996,0.3801,0.3488,0.3020,0.2238,0.0832,-0.1395",\ +"0.4230,0.4074,0.3723,0.3293,0.2473,0.1105,-0.1121",\ +"0.4621,0.4465,0.4152,0.3762,0.2941,0.1535,-0.0691",\ +"0.5441,0.5285,0.4973,0.4465,0.3684,0.2316,0.0090",\ +"0.6848,0.6652,0.6301,0.5910,0.5129,0.3605,0.1496",\ +"0.9074,0.8918,0.8566,0.8215,0.7395,0.5910,0.3723"); + } + + fall_constraint("SIG2SRAM_constraint_template") { + index_1("0.0080,0.0288,0.0616,0.1072,0.1920,0.3496,0.5952"); + index_2("0.0080,0.0288,0.0616,0.1072,0.1920,0.3496,0.5952"); + values ("0.3762,0.3605,0.3332,0.2863,0.2043,0.0715,-0.1395",\ +"0.3996,0.3762,0.3488,0.3059,0.2238,0.0910,-0.1199",\ +"0.4270,0.4035,0.3762,0.3332,0.2512,0.1184,-0.0965",\ +"0.4699,0.4504,0.4191,0.3762,0.2941,0.1613,-0.0496",\ +"0.5441,0.5285,0.4973,0.4543,0.3762,0.2355,0.0324",\ +"0.6770,0.6613,0.6340,0.5949,0.5207,0.3762,0.1652",\ +"0.9074,0.8918,0.8605,0.8176,0.7395,0.6027,0.3918"); + } + } + } +bus(B_BM) { + bus_type : D_7_0; + direction : input ; + capacitance : 0.00293202 ; + max_transition : "0.5952" ; + pin(B_BM[7:0]) { + related_power_pin : VDD; + related_ground_pin : VSS; + internal_power() { + when : "B_MEN"; + rise_power("scalar"){ + values (0.0236); + } + fall_power("scalar"){ + values (0.0076); + } + } + internal_power() { + when : "!B_MEN"; + rise_power("scalar"){ + values (0.0230); + } + fall_power("scalar"){ + values (0.0072); + } + } + } + timing() { + timing_type : setup_rising; + related_pin : "B_CLK"; + when : "(B_WEN & B_MEN)" + sdf_cond : "B_RW_ACCESS" + + rise_constraint("SIG2SRAM_constraint_template") { + index_1("0.0080,0.0288,0.0616,0.1072,0.1920,0.3496,0.5952"); + index_2("0.0080,0.0288,0.0616,0.1072,0.1920,0.3496,0.5952"); + values ("-0.5886,-0.5690,-0.5437,-0.5007,-0.4196,-0.2741,-0.0515",\ +"-0.5960,-0.5765,-0.5511,-0.5082,-0.4271,-0.2816,-0.0589",\ +"-0.6056,-0.5861,-0.5607,-0.5177,-0.4367,-0.2912,-0.0685",\ +"-0.6188,-0.5992,-0.5739,-0.5309,-0.4498,-0.3043,-0.0817",\ +"-0.6430,-0.6235,-0.5981,-0.5551,-0.4741,-0.3286,-0.1059",\ +"-0.6735,-0.6539,-0.6285,-0.5856,-0.5045,-0.3590,-0.1364",\ +"-0.7551,-0.7356,-0.7102,-0.6672,-0.5861,-0.4406,-0.2180"); + } + + fall_constraint("SIG2SRAM_constraint_template") { + index_1("0.0080,0.0288,0.0616,0.1072,0.1920,0.3496,0.5952"); + index_2("0.0080,0.0288,0.0616,0.1072,0.1920,0.3496,0.5952"); + values ("-0.5261,-0.5085,-0.4812,-0.4421,-0.3591,-0.2233,-0.0114",\ +"-0.5335,-0.5160,-0.4886,-0.4496,-0.3665,-0.2308,-0.0189",\ +"-0.5431,-0.5255,-0.4982,-0.4591,-0.3761,-0.2404,-0.0285",\ +"-0.5563,-0.5387,-0.5114,-0.4723,-0.3893,-0.2535,-0.0416",\ +"-0.5805,-0.5629,-0.5356,-0.4965,-0.4135,-0.2778,-0.0659",\ +"-0.6110,-0.5934,-0.5660,-0.5270,-0.4440,-0.3082,-0.0963",\ +"-0.6926,-0.6750,-0.6477,-0.6086,-0.5256,-0.3898,-0.1779"); + } + } + + + timing() { + timing_type : hold_rising; + related_pin : "B_CLK"; + when : "(B_WEN & B_MEN)" + sdf_cond : "B_RW_ACCESS" + + rise_constraint("SIG2SRAM_constraint_template") { + index_1("0.0080,0.0288,0.0616,0.1072,0.1920,0.3496,0.5952"); + index_2("0.0080,0.0288,0.0616,0.1072,0.1920,0.3496,0.5952"); + values ("0.7036,0.6821,0.6577,0.6147,0.5347,0.3882,0.1655",\ +"0.7111,0.6896,0.6652,0.6222,0.5421,0.3956,0.1730",\ +"0.7207,0.6992,0.6747,0.6318,0.5517,0.4052,0.1826",\ +"0.7338,0.7123,0.6879,0.6449,0.5649,0.4184,0.1957",\ +"0.7581,0.7366,0.7122,0.6692,0.5891,0.4426,0.2200",\ +"0.7885,0.7670,0.7426,0.6996,0.6195,0.4731,0.2504",\ +"0.8701,0.8486,0.8242,0.7812,0.7012,0.5547,0.3320"); + } + + fall_constraint("SIG2SRAM_constraint_template") { + index_1("0.0080,0.0288,0.0616,0.1072,0.1920,0.3496,0.5952"); + index_2("0.0080,0.0288,0.0616,0.1072,0.1920,0.3496,0.5952"); + values ("0.6294,0.6118,0.5845,0.5454,0.4624,0.3257,0.1147",\ +"0.6368,0.6193,0.5919,0.5529,0.4699,0.3331,0.1222",\ +"0.6464,0.6288,0.6015,0.5625,0.4794,0.3427,0.1318",\ +"0.6596,0.6420,0.6147,0.5756,0.4926,0.3559,0.1449",\ +"0.6838,0.6663,0.6389,0.5998,0.5168,0.3801,0.1692",\ +"0.7143,0.6967,0.6693,0.6303,0.5473,0.4106,0.1996",\ +"0.7959,0.7783,0.7510,0.7119,0.6289,0.4922,0.2812"); + } + } +} + pin(B_CLK) { + direction : input; + capacitance : 0.00378957; + max_transition : "0.5952"; + clock : "true" ; + pin_func_type : active_rising ; + + timing () { + timing_type : "min_pulse_width"; + related_pin : "B_CLK"; + rise_constraint("CLKTRAN_constraint_template") { + index_1("0.008,0.5952"); + values("0.4,0.4"); + } + } + + related_power_pin : VDD; + related_ground_pin : VSS; + + internal_power() { + when : "!B_MEN & !B_WEN & !B_REN"; + rise_power("scalar"){ + values (0); + } + fall_power("scalar"){ + values (0); + } + } + internal_power() { + when : "!B_MEN & B_WEN & !B_REN"; + rise_power("scalar"){ + values (0.4713); + } + fall_power("scalar"){ + values (0); + } + } + internal_power() { + when : "B_MEN & B_WEN & !B_REN"; + rise_power("scalar"){ + values (11.6226); + } + fall_power("scalar"){ + values (0); + } + } + internal_power() { + when : "B_MEN & B_WEN & B_REN"; + rise_power("scalar"){ + values (11.8843); + } + fall_power("scalar"){ + values (0); + } + } + internal_power() { + when : "B_MEN & !B_WEN & B_REN"; + rise_power("scalar"){ + values (9.1367); + } + fall_power("scalar"){ + values (0); + } + } + internal_power() { + when : "!B_MEN & !B_WEN & B_REN"; + rise_power("scalar"){ + values (0.2857); + } + fall_power("scalar"){ + values (0); + } + } + internal_power() { + when : "!B_MEN & B_WEN & B_REN"; + rise_power("scalar"){ + values (0.4823); + } + fall_power("scalar"){ + values (0); + } + } + internal_power() { + when : "B_MEN & !B_WEN & !B_REN"; + rise_power("scalar"){ + values (0); + } + fall_power("scalar"){ + values (0); + } + } + } + bus(B_DIN) { + bus_type : D_7_0; + direction : input ; + capacitance : 0.00460366 ; + memory_write() { + address : B_ADDR ; + clocked_on : B_CLK; + } + + max_transition : "0.5952" ; + pin(B_DIN[7:0]) { + related_power_pin : VDD; + related_ground_pin : VSS; + internal_power() { + when : "B_MEN"; + rise_power("scalar"){ + values (0.0236); + } + fall_power("scalar"){ + values (0.0076); + } + } + internal_power() { + when : "!B_MEN"; + rise_power("scalar"){ + values (0.0230); + } + fall_power("scalar"){ + values (0.0072); + } + } + } + timing() { + timing_type : setup_rising; + related_pin : "B_CLK"; + when : "(B_WEN & B_MEN)"; + sdf_cond : "B_W_ACCESS"; + + rise_constraint("SIG2SRAM_constraint_template") { + index_1("0.0080,0.0288,0.0616,0.1072,0.1920,0.3496,0.5952"); + index_2("0.0080,0.0288,0.0616,0.1072,0.1920,0.3496,0.5952"); + values ("-0.5886,-0.5690,-0.5437,-0.5007,-0.4196,-0.2741,-0.0515",\ +"-0.5960,-0.5765,-0.5511,-0.5082,-0.4271,-0.2816,-0.0589",\ +"-0.6056,-0.5861,-0.5607,-0.5177,-0.4367,-0.2912,-0.0685",\ +"-0.6188,-0.5992,-0.5739,-0.5309,-0.4498,-0.3043,-0.0817",\ +"-0.6430,-0.6235,-0.5981,-0.5551,-0.4741,-0.3286,-0.1059",\ +"-0.6735,-0.6539,-0.6285,-0.5856,-0.5045,-0.3590,-0.1364",\ +"-0.7551,-0.7356,-0.7102,-0.6672,-0.5861,-0.4406,-0.2180"); + } + + fall_constraint("SIG2SRAM_constraint_template") { + index_1("0.0080,0.0288,0.0616,0.1072,0.1920,0.3496,0.5952"); + index_2("0.0080,0.0288,0.0616,0.1072,0.1920,0.3496,0.5952"); + values ("-0.5261,-0.5085,-0.4812,-0.4421,-0.3591,-0.2233,-0.0114",\ +"-0.5335,-0.5160,-0.4886,-0.4496,-0.3665,-0.2308,-0.0189",\ +"-0.5431,-0.5255,-0.4982,-0.4591,-0.3761,-0.2404,-0.0285",\ +"-0.5563,-0.5387,-0.5114,-0.4723,-0.3893,-0.2535,-0.0416",\ +"-0.5805,-0.5629,-0.5356,-0.4965,-0.4135,-0.2778,-0.0659",\ +"-0.6110,-0.5934,-0.5660,-0.5270,-0.4440,-0.3082,-0.0963",\ +"-0.6926,-0.6750,-0.6477,-0.6086,-0.5256,-0.3898,-0.1779"); + } + } + + timing() { + timing_type : hold_rising; + related_pin : "B_CLK"; + when : "(B_WEN & B_MEN)"; + sdf_cond : "B_W_ACCESS"; + + rise_constraint("SIG2SRAM_constraint_template") { + index_1("0.0080,0.0288,0.0616,0.1072,0.1920,0.3496,0.5952"); + index_2("0.0080,0.0288,0.0616,0.1072,0.1920,0.3496,0.5952"); + values ("0.7036,0.6821,0.6577,0.6147,0.5347,0.3882,0.1655",\ +"0.7111,0.6896,0.6652,0.6222,0.5421,0.3956,0.1730",\ +"0.7207,0.6992,0.6747,0.6318,0.5517,0.4052,0.1826",\ +"0.7338,0.7123,0.6879,0.6449,0.5649,0.4184,0.1957",\ +"0.7581,0.7366,0.7122,0.6692,0.5891,0.4426,0.2200",\ +"0.7885,0.7670,0.7426,0.6996,0.6195,0.4731,0.2504",\ +"0.8701,0.8486,0.8242,0.7812,0.7012,0.5547,0.3320"); + } + + fall_constraint("SIG2SRAM_constraint_template") { + index_1("0.0080,0.0288,0.0616,0.1072,0.1920,0.3496,0.5952"); + index_2("0.0080,0.0288,0.0616,0.1072,0.1920,0.3496,0.5952"); + values ("0.6294,0.6118,0.5845,0.5454,0.4624,0.3257,0.1147",\ +"0.6368,0.6193,0.5919,0.5529,0.4699,0.3331,0.1222",\ +"0.6464,0.6288,0.6015,0.5625,0.4794,0.3427,0.1318",\ +"0.6596,0.6420,0.6147,0.5756,0.4926,0.3559,0.1449",\ +"0.6838,0.6663,0.6389,0.5998,0.5168,0.3801,0.1692",\ +"0.7143,0.6967,0.6693,0.6303,0.5473,0.4106,0.1996",\ +"0.7959,0.7783,0.7510,0.7119,0.6289,0.4922,0.2812"); + } + } + } + + pin(B_BIST_EN) { + direction : input ; + capacitance : 0.00387999 ; + max_transition : "1" ; + related_power_pin : VDD; + related_ground_pin : VSS; + internal_power() { + rise_power("scalar") { + values (0); + } + fall_power("scalar") { + values (0); + } + } + } + +bus(B_BIST_ADDR) { + bus_type : A_8_0; + direction : input ; + capacitance : 0.0129586 ; + pin(B_BIST_ADDR[0]) { + capacitance : 0.00588404 ; + } + pin(B_BIST_ADDR[1]) { + capacitance : 0.0080425 ; + } + pin(B_BIST_ADDR[2]) { + capacitance : 0.0112051 ; + } + pin(B_BIST_ADDR[3]) { + capacitance : 0.00706428 ; + } + pin(B_BIST_ADDR[4]) { + capacitance : 0.00656149 ; + } + pin(B_BIST_ADDR[5]) { + capacitance : 0.0111839 ; + } + pin(B_BIST_ADDR[6]) { + capacitance : 0.0140236 ; + } + pin(B_BIST_ADDR[7]) { + capacitance : 0.0111118 ; + } + max_transition : "0.5952" ; + pin(B_BIST_ADDR[8:0]) { + related_power_pin : VDD; + related_ground_pin : VSS; + internal_power() { + when : "B_BIST_MEN"; + rise_power("scalar"){ + values (0.0103); + } + fall_power("scalar"){ + values (0.0079); + } + } + internal_power() { + when : "!B_BIST_MEN"; + rise_power("scalar"){ + values (0.0141); + } + fall_power("scalar"){ + values (0.0033); + } + } + } + timing() { + timing_type : setup_rising; + related_pin : "B_BIST_CLK"; + when : "((B_BIST_WEN | B_BIST_REN)& B_BIST_MEN)" + sdf_cond : "B_BIST_RW_ACCESS" + + rise_constraint("SIG2SRAM_constraint_template") { + index_1("0.0080,0.0288,0.0616,0.1072,0.1920,0.3496,0.5952"); + index_2("0.0080,0.0288,0.0616,0.1072,0.1920,0.3496,0.5952"); + values ("-0.7371,-0.7176,-0.6863,-0.6434,-0.5652,-0.4168,-0.1980",\ +"-0.7566,-0.7371,-0.7059,-0.6629,-0.5848,-0.4363,-0.2137",\ +"-0.7879,-0.7645,-0.7332,-0.6902,-0.6121,-0.4637,-0.2449",\ +"-0.8309,-0.8074,-0.7762,-0.7332,-0.6551,-0.5066,-0.2879",\ +"-0.9051,-0.8895,-0.8543,-0.8113,-0.7332,-0.5887,-0.3660",\ +"-1.0418,-1.0262,-0.9949,-0.9480,-0.8699,-0.7293,-0.5027",\ +"-1.2684,-1.2449,-1.2176,-1.1707,-1.0965,-0.9480,-0.7293"); + } + + fall_constraint("SIG2SRAM_constraint_template") { + index_1("0.0080,0.0288,0.0616,0.1072,0.1920,0.3496,0.5952"); + index_2("0.0080,0.0288,0.0616,0.1072,0.1920,0.3496,0.5952"); + values ("-0.5926,-0.5730,-0.5418,-0.4988,-0.4246,-0.2879,-0.0730",\ +"-0.6121,-0.5926,-0.5613,-0.5223,-0.4441,-0.3074,-0.0887",\ +"-0.6395,-0.6199,-0.5926,-0.5496,-0.4715,-0.3348,-0.1160",\ +"-0.6863,-0.6668,-0.6355,-0.5965,-0.5184,-0.3777,-0.1590",\ +"-0.7605,-0.7410,-0.7137,-0.6746,-0.5926,-0.4559,-0.2410",\ +"-0.9012,-0.8816,-0.8504,-0.8113,-0.7332,-0.5926,-0.3895",\ +"-1.1238,-1.1043,-1.0769,-1.0379,-0.9559,-0.8191,-0.6004"); + } + } + + + timing() { + timing_type : hold_rising; + related_pin : "B_BIST_CLK"; + when : "((B_BIST_WEN | B_BIST_REN)& B_BIST_MEN)" + sdf_cond : "B_BIST_RW_ACCESS" + + rise_constraint("SIG2SRAM_constraint_template") { + index_1("0.0080,0.0288,0.0616,0.1072,0.1920,0.3496,0.5952"); + index_2("0.0080,0.0288,0.0616,0.1072,0.1920,0.3496,0.5952"); + values ("0.8488,0.8293,0.7980,0.7551,0.6730,0.5285,0.3059",\ +"0.8684,0.8488,0.8176,0.7746,0.6926,0.5480,0.3254",\ +"0.8996,0.8801,0.8449,0.8020,0.7238,0.5754,0.3527",\ +"0.9426,0.9191,0.8918,0.8488,0.7668,0.6223,0.3996",\ +"1.0168,1.0012,0.9699,0.9230,0.8449,0.7004,0.4777",\ +"1.1574,1.1379,1.1105,1.0598,0.9816,0.8371,0.6184",\ +"1.3801,1.3605,1.3254,1.2980,1.2043,1.0637,0.8371"); + } + + fall_constraint("SIG2SRAM_constraint_template") { + index_1("0.0080,0.0288,0.0616,0.1072,0.1920,0.3496,0.5952"); + index_2("0.0080,0.0288,0.0616,0.1072,0.1920,0.3496,0.5952"); + values ("0.6965,0.6770,0.6496,0.6066,0.5246,0.3918,0.1730",\ +"0.7160,0.6965,0.6652,0.6262,0.5441,0.4113,0.1965",\ +"0.7473,0.7277,0.6965,0.6535,0.5754,0.4426,0.2238",\ +"0.7863,0.7707,0.7395,0.7004,0.6223,0.4855,0.2629",\ +"0.8684,0.8449,0.8176,0.7785,0.7004,0.5637,0.3449",\ +"1.0051,0.9855,0.9855,0.9113,0.8332,0.7004,0.4895",\ +"1.2277,1.2082,1.1809,1.1379,1.0598,0.9230,0.7004"); + } + } +} +pin(B_BIST_WEN) { + direction : input ; + capacitance : 0.00313551 ; + max_transition : "0.5952" ; + related_power_pin : VDD; + related_ground_pin : VSS; + internal_power() { + when : "B_BIST_MEN"; + rise_power("scalar"){ + values (0.0036); + } + fall_power("scalar"){ + values (0.0007); + } + } + internal_power() { + when : "!B_BIST_MEN"; + rise_power("scalar"){ + values (0.0049); + } + fall_power("scalar"){ + values (0.0003); + } + } + timing() { + timing_type : setup_rising; + related_pin : "B_BIST_CLK"; + when : "B_BIST_MEN" + sdf_cond : "B_BIST_MEN" + + rise_constraint("SIG2SRAM_constraint_template") { + index_1("0.0080,0.0288,0.0616,0.1072,0.1920,0.3496,0.5952"); + index_2("0.0080,0.0288,0.0616,0.1072,0.1920,0.3496,0.5952"); + values ("0.3137,0.3332,0.3605,0.4035,0.4816,0.6223,0.8488",\ +"0.2980,0.3176,0.3410,0.3840,0.4660,0.6027,0.8293",\ +"0.2629,0.2824,0.3098,0.3527,0.4348,0.5754,0.7980",\ +"0.2199,0.2395,0.2668,0.3098,0.3918,0.5324,0.7590",\ +"0.1418,0.1613,0.1887,0.2316,0.3137,0.4348,0.6730",\ +"0.0012,0.0207,0.0520,0.0910,0.1730,0.3098,0.5285",\ +"-0.2215,-0.2020,-0.1746,-0.1277,-0.0496,0.0910,0.3098"); + } + + fall_constraint("SIG2SRAM_constraint_template") { + index_1("0.0080,0.0288,0.0616,0.1072,0.1920,0.3496,0.5952"); + index_2("0.0080,0.0288,0.0616,0.1072,0.1920,0.3496,0.5952"); + values ("0.4504,0.4699,0.4973,0.5324,0.6027,0.7355,0.9699",\ +"0.4309,0.4504,0.4777,0.5129,0.5910,0.7160,0.9504",\ +"0.3996,0.4191,0.4465,0.4816,0.5520,0.6848,0.9191",\ +"0.3605,0.3762,0.4035,0.4387,0.5168,0.6418,0.8723",\ +"0.2785,0.2980,0.3215,0.3605,0.4348,0.5637,0.7980",\ +"0.1379,0.1574,0.1809,0.2199,0.2980,0.4309,0.6457",\ +"-0.0809,-0.0613,-0.0340,0.0051,0.0832,0.2160,0.4191"); + } + } + + + timing() { + timing_type : hold_rising; + related_pin : "B_BIST_CLK"; + when : "B_BIST_MEN" + sdf_cond : "B_BIST_MEN" + + rise_constraint("SIG2SRAM_constraint_template") { + index_1("0.0080,0.0288,0.0616,0.1072,0.1920,0.3496,0.5952"); + index_2("0.0080,0.0288,0.0616,0.1072,0.1920,0.3496,0.5952"); + values ("0.3723,0.3527,0.3215,0.2785,0.1965,0.0559,-0.1668",\ +"0.3918,0.3723,0.3449,0.2980,0.2160,0.0754,-0.1473",\ +"0.4152,0.3996,0.3684,0.3254,0.2434,0.1066,-0.1199",\ +"0.4621,0.4465,0.4152,0.3723,0.2863,0.1496,-0.0730",\ +"0.5324,0.5207,0.4895,0.4465,0.3645,0.2199,0.0051",\ +"0.6770,0.6535,0.6301,0.5832,0.5090,0.3605,0.1418",\ +"0.9035,0.8879,0.8566,0.8137,0.7316,0.5871,0.3684"); + } + + fall_constraint("SIG2SRAM_constraint_template") { + index_1("0.0080,0.0288,0.0616,0.1072,0.1920,0.3496,0.5952"); + index_2("0.0080,0.0288,0.0616,0.1072,0.1920,0.3496,0.5952"); + values ("0.3762,0.3566,0.3293,0.2863,0.2043,0.0676,-0.1434",\ +"0.3957,0.3762,0.3488,0.3059,0.2238,0.0871,-0.1199",\ +"0.4230,0.4035,0.3723,0.3332,0.2512,0.1184,-0.0965",\ +"0.4660,0.4465,0.4191,0.3762,0.2941,0.1613,-0.0496",\ +"0.5324,0.5168,0.4973,0.4543,0.3723,0.2316,0.0285",\ +"0.6809,0.6613,0.6340,0.5910,0.5129,0.3645,0.1652",\ +"0.9113,0.8918,0.8605,0.8176,0.7395,0.5988,0.3879"); + } + } + } +pin(B_BIST_REN) { + direction : input ; + capacitance : 0.00381144 ; + max_transition : "0.5952" ; + related_power_pin : VDD; + related_ground_pin : VSS; + internal_power() { + when : "B_BIST_MEN"; + rise_power("scalar"){ + values (0.0040); + } + fall_power("scalar"){ + values (0.0015); + } + } + internal_power() { + when : "!B_BIST_MEN"; + rise_power("scalar"){ + values (0.0040); + } + fall_power("scalar"){ + values (0.0013); + } + } + timing() { + timing_type : setup_rising; + related_pin : "B_BIST_CLK"; + when : "B_BIST_MEN" + sdf_cond : "B_BIST_MEN" + + rise_constraint("SIG2SRAM_constraint_template") { + index_1("0.0080,0.0288,0.0616,0.1072,0.1920,0.3496,0.5952"); + index_2("0.0080,0.0288,0.0616,0.1072,0.1920,0.3496,0.5952"); + values ("-0.0770,-0.0574,-0.0262,0.0168,0.0949,0.2355,0.4582",\ +"-0.0965,-0.0770,-0.0457,-0.0027,0.0754,0.2160,0.4387",\ +"-0.1199,-0.1004,-0.0730,-0.0262,0.0520,0.1887,0.4113",\ +"-0.1590,-0.1434,-0.1160,-0.0730,0.0051,0.1457,0.3645",\ +"-0.2449,-0.2254,-0.1941,-0.1473,-0.0770,0.0676,0.2863",\ +"-0.3816,-0.3699,-0.3387,-0.2801,-0.2215,-0.0770,0.1457",\ +"-0.6121,-0.5926,-0.5613,-0.5145,-0.4363,-0.2996,-0.0730"); + } + + fall_constraint("SIG2SRAM_constraint_template") { + index_1("0.0080,0.0288,0.0616,0.1072,0.1920,0.3496,0.5952"); + index_2("0.0080,0.0288,0.0616,0.1072,0.1920,0.3496,0.5952"); + values ("0.1262,0.1457,0.1691,0.2121,0.2824,0.4191,0.6457",\ +"0.1105,0.1262,0.1496,0.1887,0.2629,0.3996,0.6262",\ +"0.0793,0.0949,0.1223,0.1652,0.2395,0.3684,0.5949",\ +"0.0363,0.0559,0.0793,0.1223,0.2004,0.3410,0.5520",\ +"-0.0457,-0.0262,0.0012,0.0441,0.1301,0.2629,0.4738",\ +"-0.1902,-0.1746,-0.1434,-0.1043,-0.0184,0.1223,0.3332",\ +"-0.4129,-0.3934,-0.3660,-0.3230,-0.2449,-0.1043,0.1105"); + } + } + + + timing() { + timing_type : hold_rising; + related_pin : "B_BIST_CLK"; + when : "B_BIST_MEN" + sdf_cond : "B_BIST_MEN" + + rise_constraint("SIG2SRAM_constraint_template") { + index_1("0.0080,0.0288,0.0616,0.1072,0.1920,0.3496,0.5952"); + index_2("0.0080,0.0288,0.0616,0.1072,0.1920,0.3496,0.5952"); + values ("0.4113,0.3918,0.3645,0.3176,0.2395,0.0988,-0.1238",\ +"0.4309,0.4113,0.3840,0.3371,0.2590,0.1184,-0.1043",\ +"0.4582,0.4387,0.4113,0.3645,0.2824,0.1457,-0.0770",\ +"0.5051,0.4816,0.4543,0.4074,0.3293,0.1887,-0.0340",\ +"0.5715,0.5598,0.5324,0.4895,0.4035,0.2512,0.0441",\ +"0.7043,0.7004,0.6730,0.6262,0.5402,0.3957,0.1809",\ +"0.9387,0.9270,0.8957,0.8527,0.7746,0.6262,0.4074"); + } + + fall_constraint("SIG2SRAM_constraint_template") { + index_1("0.0080,0.0288,0.0616,0.1072,0.1920,0.3496,0.5952"); + index_2("0.0080,0.0288,0.0616,0.1072,0.1920,0.3496,0.5952"); + values ("0.4152,0.3918,0.3645,0.3215,0.2395,0.1027,-0.1082",\ +"0.4309,0.4113,0.3801,0.3410,0.2590,0.1223,-0.0926",\ +"0.4582,0.4387,0.4074,0.3684,0.2863,0.1496,-0.0613",\ +"0.5012,0.4816,0.4504,0.4074,0.3293,0.1887,-0.0145",\ +"0.5715,0.5559,0.5285,0.4816,0.3996,0.2512,0.0598",\ +"0.7160,0.7004,0.6691,0.6262,0.5520,0.4035,0.2004",\ +"0.9387,0.9191,0.8957,0.8488,0.7707,0.6262,0.4113"); + } + } + } +pin(B_BIST_MEN) { + direction : input ; + capacitance : 0.00300347 ; + max_transition : "0.5952" ; + related_power_pin : VDD; + related_ground_pin : VSS; + internal_power() { + rise_power("scalar"){ + values (0.0092); + } + fall_power("scalar"){ + values (0.0001); + } + } + timing() { + timing_type : setup_rising; + related_pin : "B_BIST_CLK"; + + rise_constraint("SIG2SRAM_constraint_template") { + index_1("0.0080,0.0288,0.0616,0.1072,0.1920,0.3496,0.5952"); + index_2("0.0080,0.0288,0.0616,0.1072,0.1920,0.3496,0.5952"); + values ("0.3215,0.3449,0.3684,0.4113,0.4895,0.6301,0.8527",\ +"0.3059,0.3254,0.3527,0.3957,0.4738,0.6145,0.8371",\ +"0.2746,0.2941,0.3215,0.3645,0.4426,0.5871,0.8059",\ +"0.2316,0.2512,0.2785,0.3215,0.3996,0.5402,0.7629",\ +"0.1496,0.1730,0.1965,0.2395,0.3215,0.4660,0.6848",\ +"0.0090,0.0285,0.0598,0.1027,0.1809,0.3176,0.5402",\ +"-0.2098,-0.1902,-0.1668,-0.1199,-0.0418,0.0988,0.3137"); + } + + fall_constraint("SIG2SRAM_constraint_template") { + index_1("0.0080,0.0288,0.0616,0.1072,0.1920,0.3496,0.5952"); + index_2("0.0080,0.0288,0.0616,0.1072,0.1920,0.3496,0.5952"); + values ("0.4582,0.4738,0.5012,0.5363,0.6145,0.7395,0.9738",\ +"0.4387,0.4543,0.4816,0.5207,0.5910,0.7199,0.9582",\ +"0.4035,0.4230,0.4504,0.4855,0.5637,0.6887,0.9230",\ +"0.3645,0.3840,0.4074,0.4465,0.5285,0.6496,0.8840",\ +"0.2824,0.3020,0.3254,0.3645,0.4465,0.5715,0.7980",\ +"0.1418,0.1613,0.1887,0.2238,0.3020,0.4309,0.6496",\ +"-0.0770,-0.0574,-0.0301,0.0090,0.0910,0.2238,0.4191"); + } + } + + + timing() { + timing_type : hold_rising; + related_pin : "B_BIST_CLK"; + + rise_constraint("SIG2SRAM_constraint_template") { + index_1("0.0080,0.0288,0.0616,0.1072,0.1920,0.3496,0.5952"); + index_2("0.0080,0.0288,0.0616,0.1072,0.1920,0.3496,0.5952"); + values ("0.3762,0.3605,0.3293,0.2863,0.2043,0.0637,-0.1629",\ +"0.3996,0.3801,0.3488,0.3020,0.2238,0.0832,-0.1395",\ +"0.4230,0.4074,0.3723,0.3293,0.2473,0.1105,-0.1121",\ +"0.4621,0.4465,0.4152,0.3762,0.2941,0.1535,-0.0691",\ +"0.5441,0.5285,0.4973,0.4465,0.3684,0.2316,0.0090",\ +"0.6848,0.6652,0.6301,0.5910,0.5129,0.3605,0.1496",\ +"0.9074,0.8918,0.8566,0.8215,0.7395,0.5910,0.3723"); + } + + fall_constraint("SIG2SRAM_constraint_template") { + index_1("0.0080,0.0288,0.0616,0.1072,0.1920,0.3496,0.5952"); + index_2("0.0080,0.0288,0.0616,0.1072,0.1920,0.3496,0.5952"); + values ("0.3762,0.3605,0.3332,0.2863,0.2043,0.0715,-0.1395",\ +"0.3996,0.3762,0.3488,0.3059,0.2238,0.0910,-0.1199",\ +"0.4270,0.4035,0.3762,0.3332,0.2512,0.1184,-0.0965",\ +"0.4699,0.4504,0.4191,0.3762,0.2941,0.1613,-0.0496",\ +"0.5441,0.5285,0.4973,0.4543,0.3762,0.2355,0.0324",\ +"0.6770,0.6613,0.6340,0.5949,0.5207,0.3762,0.1652",\ +"0.9074,0.8918,0.8605,0.8176,0.7395,0.6027,0.3918"); + } + } + } +bus(B_BIST_BM) { + bus_type : D_7_0; + direction : input ; + capacitance : 0.00261869 ; + max_transition : "0.5952" ; + pin(B_BIST_BM[7:0]) { + related_power_pin : VDD; + related_ground_pin : VSS; + internal_power() { + when : "B_BIST_MEN"; + rise_power("scalar"){ + values (0.0236); + } + fall_power("scalar"){ + values (0.0076); + } + } + internal_power() { + when : "!B_BIST_MEN"; + rise_power("scalar"){ + values (0.0230); + } + fall_power("scalar"){ + values (0.0072); + } + } + } + timing() { + timing_type : setup_rising; + related_pin : "B_BIST_CLK"; + when : "(B_BIST_WEN & B_BIST_MEN)" + sdf_cond : "B_BIST_RW_ACCESS" + + rise_constraint("SIG2SRAM_constraint_template") { + index_1("0.0080,0.0288,0.0616,0.1072,0.1920,0.3496,0.5952"); + index_2("0.0080,0.0288,0.0616,0.1072,0.1920,0.3496,0.5952"); + values ("-0.5886,-0.5690,-0.5437,-0.5007,-0.4196,-0.2741,-0.0515",\ +"-0.5960,-0.5765,-0.5511,-0.5082,-0.4271,-0.2816,-0.0589",\ +"-0.6056,-0.5861,-0.5607,-0.5177,-0.4367,-0.2912,-0.0685",\ +"-0.6188,-0.5992,-0.5739,-0.5309,-0.4498,-0.3043,-0.0817",\ +"-0.6430,-0.6235,-0.5981,-0.5551,-0.4741,-0.3286,-0.1059",\ +"-0.6735,-0.6539,-0.6285,-0.5856,-0.5045,-0.3590,-0.1364",\ +"-0.7551,-0.7356,-0.7102,-0.6672,-0.5861,-0.4406,-0.2180"); + } + + fall_constraint("SIG2SRAM_constraint_template") { + index_1("0.0080,0.0288,0.0616,0.1072,0.1920,0.3496,0.5952"); + index_2("0.0080,0.0288,0.0616,0.1072,0.1920,0.3496,0.5952"); + values ("-0.5261,-0.5085,-0.4812,-0.4421,-0.3591,-0.2233,-0.0114",\ +"-0.5335,-0.5160,-0.4886,-0.4496,-0.3665,-0.2308,-0.0189",\ +"-0.5431,-0.5255,-0.4982,-0.4591,-0.3761,-0.2404,-0.0285",\ +"-0.5563,-0.5387,-0.5114,-0.4723,-0.3893,-0.2535,-0.0416",\ +"-0.5805,-0.5629,-0.5356,-0.4965,-0.4135,-0.2778,-0.0659",\ +"-0.6110,-0.5934,-0.5660,-0.5270,-0.4440,-0.3082,-0.0963",\ +"-0.6926,-0.6750,-0.6477,-0.6086,-0.5256,-0.3898,-0.1779"); + } + } + + + timing() { + timing_type : hold_rising; + related_pin : "B_BIST_CLK"; + when : "(B_BIST_WEN & B_BIST_MEN)" + sdf_cond : "B_BIST_RW_ACCESS" + + rise_constraint("SIG2SRAM_constraint_template") { + index_1("0.0080,0.0288,0.0616,0.1072,0.1920,0.3496,0.5952"); + index_2("0.0080,0.0288,0.0616,0.1072,0.1920,0.3496,0.5952"); + values ("0.7036,0.6821,0.6577,0.6147,0.5347,0.3882,0.1655",\ +"0.7111,0.6896,0.6652,0.6222,0.5421,0.3956,0.1730",\ +"0.7207,0.6992,0.6747,0.6318,0.5517,0.4052,0.1826",\ +"0.7338,0.7123,0.6879,0.6449,0.5649,0.4184,0.1957",\ +"0.7581,0.7366,0.7122,0.6692,0.5891,0.4426,0.2200",\ +"0.7885,0.7670,0.7426,0.6996,0.6195,0.4731,0.2504",\ +"0.8701,0.8486,0.8242,0.7812,0.7012,0.5547,0.3320"); + } + + fall_constraint("SIG2SRAM_constraint_template") { + index_1("0.0080,0.0288,0.0616,0.1072,0.1920,0.3496,0.5952"); + index_2("0.0080,0.0288,0.0616,0.1072,0.1920,0.3496,0.5952"); + values ("0.6294,0.6118,0.5845,0.5454,0.4624,0.3257,0.1147",\ +"0.6368,0.6193,0.5919,0.5529,0.4699,0.3331,0.1222",\ +"0.6464,0.6288,0.6015,0.5625,0.4794,0.3427,0.1318",\ +"0.6596,0.6420,0.6147,0.5756,0.4926,0.3559,0.1449",\ +"0.6838,0.6663,0.6389,0.5998,0.5168,0.3801,0.1692",\ +"0.7143,0.6967,0.6693,0.6303,0.5473,0.4106,0.1996",\ +"0.7959,0.7783,0.7510,0.7119,0.6289,0.4922,0.2812"); + } + } +} + pin(B_BIST_CLK) { + direction : input; + capacitance : 0.00378957; + max_transition : "0.5952"; + clock : "true" ; + pin_func_type : active_rising ; + + timing () { + timing_type : "min_pulse_width"; + related_pin : "B_BIST_CLK"; + rise_constraint("CLKTRAN_constraint_template") { + index_1("0.008,0.5952"); + values("0.4,0.4"); + } + } + + related_power_pin : VDD; + related_ground_pin : VSS; + + internal_power() { + when : "!B_BIST_MEN & !B_BIST_WEN & !B_BIST_REN"; + rise_power("scalar"){ + values (0); + } + fall_power("scalar"){ + values (0); + } + } + internal_power() { + when : "!B_BIST_MEN & B_BIST_WEN & !B_BIST_REN"; + rise_power("scalar"){ + values (0.4713); + } + fall_power("scalar"){ + values (0); + } + } + internal_power() { + when : "B_BIST_MEN & B_BIST_WEN & !B_BIST_REN"; + rise_power("scalar"){ + values (11.6226); + } + fall_power("scalar"){ + values (0); + } + } + internal_power() { + when : "B_BIST_MEN & B_BIST_WEN & B_BIST_REN"; + rise_power("scalar"){ + values (11.8843); + } + fall_power("scalar"){ + values (0); + } + } + internal_power() { + when : "B_BIST_MEN & !B_BIST_WEN & B_BIST_REN"; + rise_power("scalar"){ + values (9.1367); + } + fall_power("scalar"){ + values (0); + } + } + internal_power() { + when : "!B_BIST_MEN & !B_BIST_WEN & B_BIST_REN"; + rise_power("scalar"){ + values (0.2857); + } + fall_power("scalar"){ + values (0); + } + } + internal_power() { + when : "!B_BIST_MEN & B_BIST_WEN & B_BIST_REN"; + rise_power("scalar"){ + values (0.4823); + } + fall_power("scalar"){ + values (0); + } + } + internal_power() { + when : "B_BIST_MEN & !B_BIST_WEN & !B_BIST_REN"; + rise_power("scalar"){ + values (0); + } + fall_power("scalar"){ + values (0); + } + } + } + bus(B_BIST_DIN) { + bus_type : D_7_0; + direction : input ; + capacitance : 0.00416317 ; + memory_write() { + address : B_BIST_ADDR ; + clocked_on : B_BIST_CLK; + } + + max_transition : "0.5952" ; + pin(B_BIST_DIN[7:0]) { + related_power_pin : VDD; + related_ground_pin : VSS; + internal_power() { + when : "B_BIST_MEN"; + rise_power("scalar"){ + values (0.0236); + } + fall_power("scalar"){ + values (0.0076); + } + } + internal_power() { + when : "!B_BIST_MEN"; + rise_power("scalar"){ + values (0.0230); + } + fall_power("scalar"){ + values (0.0072); + } + } + } + timing() { + timing_type : setup_rising; + related_pin : "B_BIST_CLK"; + when : "(B_BIST_WEN & B_BIST_MEN)"; + sdf_cond : "B_BIST_W_ACCESS"; + + rise_constraint("SIG2SRAM_constraint_template") { + index_1("0.0080,0.0288,0.0616,0.1072,0.1920,0.3496,0.5952"); + index_2("0.0080,0.0288,0.0616,0.1072,0.1920,0.3496,0.5952"); + values ("-0.5886,-0.5690,-0.5437,-0.5007,-0.4196,-0.2741,-0.0515",\ +"-0.5960,-0.5765,-0.5511,-0.5082,-0.4271,-0.2816,-0.0589",\ +"-0.6056,-0.5861,-0.5607,-0.5177,-0.4367,-0.2912,-0.0685",\ +"-0.6188,-0.5992,-0.5739,-0.5309,-0.4498,-0.3043,-0.0817",\ +"-0.6430,-0.6235,-0.5981,-0.5551,-0.4741,-0.3286,-0.1059",\ +"-0.6735,-0.6539,-0.6285,-0.5856,-0.5045,-0.3590,-0.1364",\ +"-0.7551,-0.7356,-0.7102,-0.6672,-0.5861,-0.4406,-0.2180"); + } + + fall_constraint("SIG2SRAM_constraint_template") { + index_1("0.0080,0.0288,0.0616,0.1072,0.1920,0.3496,0.5952"); + index_2("0.0080,0.0288,0.0616,0.1072,0.1920,0.3496,0.5952"); + values ("-0.5261,-0.5085,-0.4812,-0.4421,-0.3591,-0.2233,-0.0114",\ +"-0.5335,-0.5160,-0.4886,-0.4496,-0.3665,-0.2308,-0.0189",\ +"-0.5431,-0.5255,-0.4982,-0.4591,-0.3761,-0.2404,-0.0285",\ +"-0.5563,-0.5387,-0.5114,-0.4723,-0.3893,-0.2535,-0.0416",\ +"-0.5805,-0.5629,-0.5356,-0.4965,-0.4135,-0.2778,-0.0659",\ +"-0.6110,-0.5934,-0.5660,-0.5270,-0.4440,-0.3082,-0.0963",\ +"-0.6926,-0.6750,-0.6477,-0.6086,-0.5256,-0.3898,-0.1779"); + } + } + + timing() { + timing_type : hold_rising; + related_pin : "B_BIST_CLK"; + when : "(B_BIST_WEN & B_BIST_MEN)"; + sdf_cond : "B_BIST_W_ACCESS"; + + rise_constraint("SIG2SRAM_constraint_template") { + index_1("0.0080,0.0288,0.0616,0.1072,0.1920,0.3496,0.5952"); + index_2("0.0080,0.0288,0.0616,0.1072,0.1920,0.3496,0.5952"); + values ("0.7036,0.6821,0.6577,0.6147,0.5347,0.3882,0.1655",\ +"0.7111,0.6896,0.6652,0.6222,0.5421,0.3956,0.1730",\ +"0.7207,0.6992,0.6747,0.6318,0.5517,0.4052,0.1826",\ +"0.7338,0.7123,0.6879,0.6449,0.5649,0.4184,0.1957",\ +"0.7581,0.7366,0.7122,0.6692,0.5891,0.4426,0.2200",\ +"0.7885,0.7670,0.7426,0.6996,0.6195,0.4731,0.2504",\ +"0.8701,0.8486,0.8242,0.7812,0.7012,0.5547,0.3320"); + } + + fall_constraint("SIG2SRAM_constraint_template") { + index_1("0.0080,0.0288,0.0616,0.1072,0.1920,0.3496,0.5952"); + index_2("0.0080,0.0288,0.0616,0.1072,0.1920,0.3496,0.5952"); + values ("0.6294,0.6118,0.5845,0.5454,0.4624,0.3257,0.1147",\ +"0.6368,0.6193,0.5919,0.5529,0.4699,0.3331,0.1222",\ +"0.6464,0.6288,0.6015,0.5625,0.4794,0.3427,0.1318",\ +"0.6596,0.6420,0.6147,0.5756,0.4926,0.3559,0.1449",\ +"0.6838,0.6663,0.6389,0.5998,0.5168,0.3801,0.1692",\ +"0.7143,0.6967,0.6693,0.6303,0.5473,0.4106,0.1996",\ +"0.7959,0.7783,0.7510,0.7119,0.6289,0.4922,0.2812"); + } + } + } + +bus(B_DOUT) { + + bus_type : D_7_0; + direction : output ; + capacitance : 0 ; + max_capacitance : 0.064 ; + memory_read() { + address : B_ADDR ; + } + pin(B_DOUT[7:0]) { + related_power_pin : VDD; + related_ground_pin : VSS; + internal_power() { + rise_power("scalar") { + values (0); + } + fall_power("scalar") { + values (0); + } + } + } + timing() { + related_pin : "B_CLK"; + timing_type : rising_edge ; + timing_sense : non_unate ; + + cell_rise(SIG2SRAM_delay_template) { + index_1("0.0080,0.0288,0.0616,0.1072,0.1920,0.3496,0.5952"); + index_2("0.0008,0.0014,0.0051,0.0100,0.0339,0.0640"); + values ("6.2592,6.2625,6.2747,6.2887,6.3412,6.3991",\ +"6.2635,6.2669,6.2791,6.2930,6.3456,6.4034",\ +"6.2740,6.2773,6.2895,6.3035,6.3560,6.4139",\ +"6.2946,6.2980,6.3102,6.3241,6.3767,6.4345",\ +"6.3089,6.3123,6.3244,6.3384,6.3909,6.4488",\ +"6.3423,6.3457,6.3579,6.3718,6.4244,6.4822",\ +"6.4280,6.4314,6.4436,6.4575,6.5101,6.5679"); + } + cell_fall(SIG2SRAM_delay_template) { + index_1("0.0080,0.0288,0.0616,0.1072,0.1920,0.3496,0.5952"); + index_2("0.0008,0.0014,0.0051,0.0100,0.0339,0.0640"); + values ("6.1494,6.1516,6.1617,6.1733,6.2167,6.2605",\ +"6.1538,6.1560,6.1660,6.1777,6.2211,6.2649",\ +"6.1642,6.1664,6.1765,6.1881,6.2315,6.2753",\ +"6.1849,6.1871,6.1971,6.2088,6.2521,6.2960",\ +"6.1992,6.2013,6.2114,6.2231,6.2664,6.3102",\ +"6.2326,6.2348,6.2448,6.2565,6.2998,6.3437",\ +"6.3183,6.3205,6.3305,6.3422,6.3855,6.4294"); + } + + rise_transition(SRAM_load_template) { + index_1("0.0008,0.0014,0.0051,0.0100,0.0339,0.0640"); + values ("0.0560,0.0583,0.0696,0.0816,0.1519,0.2335"); + } + fall_transition(SRAM_load_template) { + index_1("0.0008,0.0014,0.0051,0.0100,0.0339,0.0640"); + values ("0.0428,0.0445,0.0538,0.0658,0.1181,0.1751"); + } + } +} +cell_leakage_power : 476.5786; +} +} diff --git a/flow/platforms/ihp-sg13g2/lib/RM_IHPSG13_2P_512x8_c2_bm_bist_typ_1p20V_25C.lib b/flow/platforms/ihp-sg13g2/lib/RM_IHPSG13_2P_512x8_c2_bm_bist_typ_1p20V_25C.lib new file mode 100644 index 0000000000..41dda2dc7f --- /dev/null +++ b/flow/platforms/ihp-sg13g2/lib/RM_IHPSG13_2P_512x8_c2_bm_bist_typ_1p20V_25C.lib @@ -0,0 +1,2886 @@ +/* ------------------------------------------------------*/ +/**/ +/* Copyright 2025 IHP PDK Authors*/ +/**/ +/* Licensed under the Apache License, Version 2.0 (the "License");*/ +/* you may not use this file except in compliance with the License.*/ +/* You may obtain a copy of the License at*/ +/* */ +/* https://www.apache.org/licenses/LICENSE-2.0*/ +/* */ +/* Unless required by applicable law or agreed to in writing, software*/ +/* distributed under the License is distributed on an "AS IS" BASIS,*/ +/* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.*/ +/* See the License for the specific language governing permissions and*/ +/* limitations under the License.*/ +/* */ +/* Generated on Wed Aug 27 13:34:38 2025 */ +/* */ +/* ------------------------------------------------------ */ +library(RM_IHPSG13_2P_512x8_c2_bm_bist_typ_1p20V_25C) { + technology (cmos) ; + delay_model : table_lookup ; + define ("add_pg_pin_to_lib", "library", "boolean"); + add_pg_pin_to_lib : true; + voltage_map ( VDD, 1.20); + voltage_map ( VDDARRAY, 1.20); + voltage_map ( VSS, 0.000000 ); + + date : "Wed Aug 27 13:34:35 2025" ; + comment : "IHP Microelectronics GmbH, 2023" ; + revision : 1.0.0 ; + simulation : true ; + nom_process : 1 ; + nom_temperature : 25 ; + nom_voltage : 1.20 ; + + operating_conditions("typ_1p20V_25C"){ + process : 1 ; + temperature : 25 ; + voltage : 1.20 ; + tree_type : "balanced_tree" ; + } + + default_operating_conditions : typ_1p20V_25C ; + default_max_transition : 1.0 ; + default_fanout_load : 1.0 ; + default_inout_pin_cap : 0.0 ; + default_input_pin_cap : 0.0 ; + default_output_pin_cap : 0.0 ; + default_cell_leakage_power : 0.0 ; + default_leakage_power_density : 0.0 ; + + slew_lower_threshold_pct_rise : 30 ; + slew_upper_threshold_pct_rise : 70 ; + input_threshold_pct_fall : 50 ; + output_threshold_pct_fall : 50 ; + input_threshold_pct_rise : 50 ; + output_threshold_pct_rise : 50 ; + slew_lower_threshold_pct_fall : 30 ; + slew_upper_threshold_pct_fall : 70 ; + slew_derate_from_library : 0.5; + k_volt_cell_leakage_power : 0.0 ; + k_temp_cell_leakage_power : 0.0 ; + k_process_cell_leakage_power : 0.0 ; + k_volt_internal_power : 0.0 ; + k_temp_internal_power : 0.0 ; + k_process_internal_power : 0.0 ; + + capacitive_load_unit (1,pf) ; + voltage_unit : "1V" ; + current_unit : "1uA" ; + time_unit : "1ns" ; + leakage_power_unit : "1nW" ; + pulling_resistance_unit : "1kohm"; + /* + ------------------------------------------------------------------------------------------ + implicit units overview: + cell_area unit : "um" + internal_power unit : "1e-12 * J/toggle = 1 * uW/MHz" + (capacitive_load_unit * voltage_unit^2) per toggle event + ------------------------------------------------------------------------------------------ + */ + library_features(report_delay_calculation); + define_cell_area (pad_drivers,pad_driver_sites) ; + + lu_table_template(CLKTRAN_constraint_template) { + variable_1 : constrained_pin_transition; + index_1 ( "0.010, 0.050, 0.200, 0.400, 1.000" ); + } + lu_table_template(SRAM_load_template) { + variable_1 : total_output_net_capacitance; + index_1 ( "0.0008,0.0014,0.0051,0.0100,0.0339,0.0640" ); + } + lu_table_template(SIG2SRAM_constraint_template) { + variable_1 : related_pin_transition; + variable_2 : constrained_pin_transition; + index_1 ( "0.0056,0.0232,0.0400,0.0728,0.1280,0.2440,0.4760" ); + index_2 ( "0.0056,0.0232,0.0400,0.0728,0.1280,0.2440,0.4760" ); + } + + lu_table_template(SIG2SRAM_delay_template) { + variable_1 : input_net_transition; + variable_2 : total_output_net_capacitance; + index_1 ( "0.0056,0.0232,0.0400,0.0728,0.1280,0.2440,0.4760" ); + index_2 ( "0.0008,0.0014,0.0051,0.0100,0.0339,0.0640" ); + } + + type (D_7_0) { + base_type : array; + data_type : bit; + bit_width : 8; + bit_from : 7; + bit_to : 0; + downto : true; + } + + type (A_8_0) { + base_type : array; + data_type : bit; + bit_width : 9; + bit_from : 8; + bit_to : 0; + downto : true; + } + +cell(RM_IHPSG13_2P_512x8_c2_bm_bist) { +pg_pin (VDD) { + pg_type : primary_power; + voltage_name : VDD; +} +pg_pin (VDDARRAY) { + pg_type : primary_power; + voltage_name : VDDARRAY; +} +pg_pin (VSS) { + pg_type : primary_ground; + voltage_name : VSS; +} + +memory() { + type : ram; + address_width : 9; + word_width : 8; +} + +interface_timing : false; +bus_naming_style : "%s[%d]" ; +area : 57397.3309 ; + + pin(A_DLY) { + direction : input ; + capacitance : 0.00401111 ; + max_transition : "1" ; + related_power_pin : VDD; + related_ground_pin : VSS; + internal_power() { + rise_power("scalar") { + values (0); + } + fall_power("scalar") { + values (0); + } + } + } + +bus(A_ADDR) { + bus_type : A_8_0; + direction : input ; + capacitance : 0.0121077 ; + pin(A_ADDR[0]) { + capacitance : 0.00568653 ; + } + pin(A_ADDR[1]) { + capacitance : 0.00767263 ; + } + pin(A_ADDR[2]) { + capacitance : 0.0105079 ; + } + pin(A_ADDR[3]) { + capacitance : 0.0068178 ; + } + pin(A_ADDR[4]) { + capacitance : 0.00624497 ; + } + pin(A_ADDR[5]) { + capacitance : 0.0105871 ; + } + pin(A_ADDR[6]) { + capacitance : 0.0130817 ; + } + pin(A_ADDR[7]) { + capacitance : 0.0104931 ; + } + max_transition : "0.476" ; + pin(A_ADDR[8:0]) { + related_power_pin : VDD; + related_ground_pin : VSS; + internal_power() { + when : "A_MEN"; + rise_power("scalar"){ + values (0.0112); + } + fall_power("scalar"){ + values (0.0057); + } + } + internal_power() { + when : "!A_MEN"; + rise_power("scalar"){ + values (0.0181); + } + fall_power("scalar"){ + values (0.0008); + } + } + } + timing() { + timing_type : setup_rising; + related_pin : "A_CLK"; + when : "((A_WEN | A_REN)& A_MEN)" + sdf_cond : "A_RW_ACCESS" + + rise_constraint("SIG2SRAM_constraint_template") { + index_1("0.0056,0.0232,0.0400,0.0728,0.1280,0.2440,0.4760"); + index_2("0.0056,0.0232,0.0400,0.0728,0.1280,0.2440,0.4760"); + values ("-0.4168,-0.3973,-0.3855,-0.3543,-0.3074,-0.2020,-0.0027",\ +"-0.4324,-0.4129,-0.4012,-0.3699,-0.3191,-0.2176,-0.0184",\ +"-0.4441,-0.4285,-0.4129,-0.3816,-0.3309,-0.2293,-0.0301",\ +"-0.4793,-0.4598,-0.4441,-0.4129,-0.3660,-0.2645,-0.0652",\ +"-0.5223,-0.5066,-0.4910,-0.4598,-0.4129,-0.3074,-0.1121",\ +"-0.6199,-0.6082,-0.5926,-0.5613,-0.5145,-0.4129,-0.2137",\ +"-0.8191,-0.8074,-0.7840,-0.7566,-0.7098,-0.6082,-0.4051"); + } + + fall_constraint("SIG2SRAM_constraint_template") { + index_1("0.0056,0.0232,0.0400,0.0728,0.1280,0.2440,0.4760"); + index_2("0.0056,0.0232,0.0400,0.0728,0.1280,0.2440,0.4760"); + values ("-0.3309,-0.3113,-0.2996,-0.2684,-0.2176,-0.1238,0.0637",\ +"-0.3465,-0.3309,-0.3152,-0.2840,-0.2332,-0.1395,0.0480",\ +"-0.3582,-0.3426,-0.3270,-0.2996,-0.2488,-0.1512,0.0324",\ +"-0.3895,-0.3738,-0.3582,-0.3309,-0.2801,-0.1863,0.0051",\ +"-0.4363,-0.4207,-0.4051,-0.3777,-0.3230,-0.2293,-0.0379",\ +"-0.5379,-0.5223,-0.5066,-0.4793,-0.4285,-0.3309,-0.1434",\ +"-0.7332,-0.7176,-0.7020,-0.6746,-0.6238,-0.5262,-0.3387"); + } + } + + + timing() { + timing_type : hold_rising; + related_pin : "A_CLK"; + when : "((A_WEN | A_REN)& A_MEN)" + sdf_cond : "A_RW_ACCESS" + + rise_constraint("SIG2SRAM_constraint_template") { + index_1("0.0056,0.0232,0.0400,0.0728,0.1280,0.2440,0.4760"); + index_2("0.0056,0.0232,0.0400,0.0728,0.1280,0.2440,0.4760"); + values ("0.5246,0.5051,0.4895,0.4582,0.4113,0.3059,0.1066",\ +"0.5402,0.5207,0.5051,0.4777,0.4270,0.3215,0.1223",\ +"0.5520,0.5324,0.5168,0.4895,0.4387,0.3371,0.1340",\ +"0.5832,0.5676,0.5520,0.5207,0.4738,0.3684,0.1691",\ +"0.6301,0.6105,0.5949,0.5676,0.5168,0.4113,0.2160",\ +"0.7316,0.7121,0.7004,0.6691,0.6223,0.5168,0.3176",\ +"0.9270,0.9230,0.8957,0.8645,0.8137,0.7121,0.5168"); + } + + fall_constraint("SIG2SRAM_constraint_template") { + index_1("0.0056,0.0232,0.0400,0.0728,0.1280,0.2440,0.4760"); + index_2("0.0056,0.0232,0.0400,0.0728,0.1280,0.2440,0.4760"); + values ("0.4309,0.4152,0.4035,0.3684,0.3215,0.2277,0.0363",\ +"0.4465,0.4309,0.4152,0.3879,0.3371,0.2395,0.0559",\ +"0.4582,0.4426,0.4309,0.3996,0.3488,0.2551,0.0715",\ +"0.4934,0.4777,0.4621,0.4348,0.3840,0.2863,0.0988",\ +"0.5363,0.5207,0.5051,0.4777,0.4270,0.3332,0.1418",\ +"0.6379,0.6262,0.6105,0.5793,0.5324,0.4348,0.2434",\ +"0.8332,0.8215,0.8059,0.7707,0.7238,0.6301,0.4387"); + } + } +} +pin(A_WEN) { + direction : input ; + capacitance : 0.00324098 ; + max_transition : "0.476" ; + related_power_pin : VDD; + related_ground_pin : VSS; + internal_power() { + when : "A_MEN"; + rise_power("scalar"){ + values (0.0046); + } + fall_power("scalar"){ + values (0.0038); + } + } + internal_power() { + when : "!A_MEN"; + rise_power("scalar"){ + values (0.0042); + } + fall_power("scalar"){ + values (0.0038); + } + } + timing() { + timing_type : setup_rising; + related_pin : "A_CLK"; + when : "A_MEN" + sdf_cond : "A_MEN" + + rise_constraint("SIG2SRAM_constraint_template") { + index_1("0.0056,0.0232,0.0400,0.0728,0.1280,0.2440,0.4760"); + index_2("0.0056,0.0232,0.0400,0.0728,0.1280,0.2440,0.4760"); + values ("0.2043,0.2199,0.2316,0.2629,0.3059,0.4113,0.6066",\ +"0.1887,0.2043,0.2160,0.2473,0.2941,0.3957,0.5949",\ +"0.1691,0.1848,0.2004,0.2316,0.2785,0.3801,0.5754",\ +"0.1379,0.1574,0.1691,0.2004,0.2473,0.3527,0.5480",\ +"0.0910,0.1066,0.1223,0.1535,0.2004,0.2980,0.4973",\ +"-0.0105,0.0051,0.0207,0.0520,0.0949,0.2004,0.3957",\ +"-0.2059,-0.1902,-0.1746,-0.1473,-0.1004,0.0051,0.2004"); + } + + fall_constraint("SIG2SRAM_constraint_template") { + index_1("0.0056,0.0232,0.0400,0.0728,0.1280,0.2440,0.4760"); + index_2("0.0056,0.0232,0.0400,0.0728,0.1280,0.2440,0.4760"); + values ("0.2941,0.3098,0.3215,0.3488,0.4035,0.4973,0.6887",\ +"0.2785,0.2941,0.3059,0.3332,0.3840,0.4816,0.6691",\ +"0.2629,0.2785,0.2902,0.3176,0.3684,0.4660,0.6535",\ +"0.2316,0.2473,0.2590,0.2863,0.3410,0.4348,0.6262",\ +"0.1848,0.2004,0.2121,0.2395,0.2902,0.3879,0.5754",\ +"0.0832,0.0988,0.1105,0.1379,0.1809,0.2746,0.4699",\ +"-0.1121,-0.0965,-0.0848,-0.0535,-0.0066,0.0910,0.2824"); + } + } + + + timing() { + timing_type : hold_rising; + related_pin : "A_CLK"; + when : "A_MEN" + sdf_cond : "A_MEN" + + rise_constraint("SIG2SRAM_constraint_template") { + index_1("0.0056,0.0232,0.0400,0.0728,0.1280,0.2440,0.4760"); + index_2("0.0056,0.0232,0.0400,0.0728,0.1280,0.2440,0.4760"); + values ("0.2473,0.2316,0.2160,0.1887,0.1379,0.0363,-0.1629",\ +"0.2629,0.2473,0.2316,0.2043,0.1535,0.0520,-0.1473",\ +"0.2785,0.2590,0.2434,0.2160,0.1652,0.0676,-0.1355",\ +"0.3098,0.2941,0.2785,0.2473,0.1965,0.0910,-0.1043",\ +"0.3527,0.3371,0.3215,0.2941,0.2434,0.1418,-0.0574",\ +"0.4582,0.4426,0.4270,0.3957,0.3488,0.2434,0.0480",\ +"0.6535,0.6379,0.6184,0.5910,0.5402,0.4426,0.2434"); + } + + fall_constraint("SIG2SRAM_constraint_template") { + index_1("0.0056,0.0232,0.0400,0.0728,0.1280,0.2440,0.4760"); + index_2("0.0056,0.0232,0.0400,0.0728,0.1280,0.2440,0.4760"); + values ("0.2395,0.2238,0.2121,0.1809,0.1301,0.0324,-0.1551",\ +"0.2551,0.2395,0.2277,0.1965,0.1457,0.0480,-0.1395",\ +"0.2668,0.2551,0.2395,0.2082,0.1574,0.0637,-0.1277",\ +"0.3020,0.2863,0.2707,0.2395,0.1887,0.0910,-0.0965",\ +"0.3449,0.3293,0.3176,0.2863,0.2355,0.1379,-0.0496",\ +"0.4504,0.4348,0.4191,0.3879,0.3371,0.2395,0.0559",\ +"0.6457,0.6301,0.6145,0.5871,0.5324,0.4309,0.2512"); + } + } + } +pin(A_REN) { + direction : input ; + capacitance : 0.00381634 ; + max_transition : "0.476" ; + related_power_pin : VDD; + related_ground_pin : VSS; + internal_power() { + when : "A_MEN"; + rise_power("scalar"){ + values (0.0061); + } + fall_power("scalar"){ + values (0.0020); + } + } + internal_power() { + when : "!A_MEN"; + rise_power("scalar"){ + values (0.0061); + } + fall_power("scalar"){ + values (0.0024); + } + } + timing() { + timing_type : setup_rising; + related_pin : "A_CLK"; + when : "A_MEN" + sdf_cond : "A_MEN" + + rise_constraint("SIG2SRAM_constraint_template") { + index_1("0.0056,0.0232,0.0400,0.0728,0.1280,0.2440,0.4760"); + index_2("0.0056,0.0232,0.0400,0.0728,0.1280,0.2440,0.4760"); + values ("-0.0301,-0.0145,0.0012,0.0324,0.0793,0.1809,0.3762",\ +"-0.0457,-0.0301,-0.0145,0.0168,0.0637,0.1613,0.3605",\ +"-0.0574,-0.0418,-0.0262,0.0051,0.0520,0.1496,0.3449",\ +"-0.0926,-0.0730,-0.0574,-0.0262,0.0207,0.1184,0.3137",\ +"-0.1395,-0.1238,-0.1082,-0.0770,-0.0301,0.0715,0.2707",\ +"-0.2410,-0.2254,-0.2098,-0.1746,-0.1355,-0.0340,0.1652",\ +"-0.4402,-0.4207,-0.4051,-0.3738,-0.3270,-0.2293,-0.0340"); + } + + fall_constraint("SIG2SRAM_constraint_template") { + index_1("0.0056,0.0232,0.0400,0.0728,0.1280,0.2440,0.4760"); + index_2("0.0056,0.0232,0.0400,0.0728,0.1280,0.2440,0.4760"); + values ("0.0988,0.1145,0.1262,0.1535,0.2043,0.3020,0.4855",\ +"0.0832,0.0988,0.1105,0.1418,0.1848,0.2824,0.4738",\ +"0.0676,0.0832,0.0949,0.1262,0.1730,0.2668,0.4621",\ +"0.0402,0.0559,0.0676,0.0988,0.1457,0.2434,0.4191",\ +"-0.0105,0.0012,0.0168,0.0480,0.0988,0.1965,0.3840",\ +"-0.1160,-0.0965,-0.0848,-0.0535,-0.0066,0.0988,0.2824",\ +"-0.3113,-0.2957,-0.2801,-0.2527,-0.2059,-0.1043,0.0832"); + } + } + + + timing() { + timing_type : hold_rising; + related_pin : "A_CLK"; + when : "A_MEN" + sdf_cond : "A_MEN" + + rise_constraint("SIG2SRAM_constraint_template") { + index_1("0.0056,0.0232,0.0400,0.0728,0.1280,0.2440,0.4760"); + index_2("0.0056,0.0232,0.0400,0.0728,0.1280,0.2440,0.4760"); + values ("0.2707,0.2551,0.2395,0.2121,0.1613,0.0598,-0.1395",\ +"0.2863,0.2707,0.2551,0.2238,0.1730,0.0715,-0.1238",\ +"0.2980,0.2824,0.2668,0.2395,0.1887,0.0871,-0.1121",\ +"0.3332,0.3176,0.3020,0.2707,0.2199,0.1184,-0.0809",\ +"0.3762,0.3605,0.3449,0.3176,0.2668,0.1613,-0.0340",\ +"0.4816,0.4621,0.4504,0.4191,0.3723,0.2629,0.0715",\ +"0.6770,0.6613,0.6418,0.6184,0.5637,0.4699,0.2629"); + } + + fall_constraint("SIG2SRAM_constraint_template") { + index_1("0.0056,0.0232,0.0400,0.0728,0.1280,0.2440,0.4760"); + index_2("0.0056,0.0232,0.0400,0.0728,0.1280,0.2440,0.4760"); + values ("0.2590,0.2434,0.2316,0.2004,0.1457,0.0520,-0.1355",\ +"0.2746,0.2590,0.2434,0.2160,0.1613,0.0676,-0.1199",\ +"0.2863,0.2707,0.2590,0.2277,0.1730,0.0832,-0.1082",\ +"0.3215,0.3059,0.2902,0.2590,0.2082,0.1105,-0.0770",\ +"0.3645,0.3488,0.3332,0.3059,0.2551,0.1535,-0.0340",\ +"0.4699,0.4543,0.4387,0.4074,0.3605,0.2551,0.0715",\ +"0.6652,0.6496,0.6340,0.6027,0.5520,0.4621,0.2707"); + } + } + } +pin(A_MEN) { + direction : input ; + capacitance : 0.00309605 ; + max_transition : "0.476" ; + related_power_pin : VDD; + related_ground_pin : VSS; + internal_power() { + rise_power("scalar"){ + values (0.0236); + } + fall_power("scalar"){ + values (0.0052); + } + } + timing() { + timing_type : setup_rising; + related_pin : "A_CLK"; + + rise_constraint("SIG2SRAM_constraint_template") { + index_1("0.0056,0.0232,0.0400,0.0728,0.1280,0.2440,0.4760"); + index_2("0.0056,0.0232,0.0400,0.0728,0.1280,0.2440,0.4760"); + values ("0.2043,0.2199,0.2316,0.2668,0.3098,0.4152,0.6066",\ +"0.1887,0.2043,0.2199,0.2512,0.2941,0.3996,0.5949",\ +"0.1730,0.1887,0.2043,0.2355,0.2824,0.3840,0.5793",\ +"0.1418,0.1574,0.1730,0.2043,0.2512,0.3566,0.5480",\ +"0.0949,0.1105,0.1262,0.1574,0.2043,0.3020,0.5051",\ +"-0.0066,0.0090,0.0246,0.0520,0.0988,0.2043,0.3996",\ +"-0.2020,-0.1863,-0.1746,-0.1434,-0.0965,0.0090,0.2082"); + } + + fall_constraint("SIG2SRAM_constraint_template") { + index_1("0.0056,0.0232,0.0400,0.0728,0.1280,0.2440,0.4760"); + index_2("0.0056,0.0232,0.0400,0.0728,0.1280,0.2440,0.4760"); + values ("0.2980,0.3137,0.3254,0.3527,0.4035,0.5012,0.6887",\ +"0.2824,0.2980,0.3098,0.3371,0.3879,0.4855,0.6730",\ +"0.2668,0.2824,0.2941,0.3215,0.3723,0.4699,0.6574",\ +"0.2355,0.2473,0.2629,0.2902,0.3410,0.4387,0.6262",\ +"0.1887,0.2004,0.2160,0.2395,0.2941,0.3918,0.5793",\ +"0.0871,0.1027,0.1145,0.1418,0.1848,0.2746,0.4816",\ +"-0.1082,-0.0965,-0.0809,-0.0496,-0.0027,0.0949,0.2863"); + } + } + + + timing() { + timing_type : hold_rising; + related_pin : "A_CLK"; + + rise_constraint("SIG2SRAM_constraint_template") { + index_1("0.0056,0.0232,0.0400,0.0728,0.1280,0.2440,0.4760"); + index_2("0.0056,0.0232,0.0400,0.0728,0.1280,0.2440,0.4760"); + values ("0.2512,0.2355,0.2199,0.1926,0.1418,0.0402,-0.1590",\ +"0.2668,0.2512,0.2355,0.2082,0.1574,0.0559,-0.1434",\ +"0.2824,0.2629,0.2512,0.2199,0.1691,0.0715,-0.1316",\ +"0.3137,0.2980,0.2824,0.2512,0.2004,0.0988,-0.0965",\ +"0.3566,0.3410,0.3254,0.2980,0.2473,0.1418,-0.0535",\ +"0.4621,0.4426,0.4309,0.3996,0.3527,0.2473,0.0520",\ +"0.6574,0.6418,0.6262,0.5949,0.5441,0.4465,0.2473"); + } + + fall_constraint("SIG2SRAM_constraint_template") { + index_1("0.0056,0.0232,0.0400,0.0728,0.1280,0.2440,0.4760"); + index_2("0.0056,0.0232,0.0400,0.0728,0.1280,0.2440,0.4760"); + values ("0.2395,0.2238,0.2121,0.1809,0.1301,0.0324,-0.1551",\ +"0.2551,0.2434,0.2277,0.1965,0.1457,0.0480,-0.1395",\ +"0.2707,0.2551,0.2395,0.2082,0.1574,0.0637,-0.1277",\ +"0.3020,0.2863,0.2707,0.2434,0.1926,0.0910,-0.0965",\ +"0.3449,0.3332,0.3176,0.2863,0.2355,0.1379,-0.0496",\ +"0.4504,0.4348,0.4230,0.3918,0.3410,0.2434,0.0559",\ +"0.6457,0.6301,0.6145,0.5910,0.5324,0.4387,0.2512"); + } + } + } +bus(A_BM) { + bus_type : D_7_0; + direction : input ; + capacitance : 0.00372627 ; + max_transition : "0.476" ; + pin(A_BM[7:0]) { + related_power_pin : VDD; + related_ground_pin : VSS; + internal_power() { + when : "A_MEN"; + rise_power("scalar"){ + values (0.0288); + } + fall_power("scalar"){ + values (0.0126); + } + } + internal_power() { + when : "!A_MEN"; + rise_power("scalar"){ + values (0.0317); + } + fall_power("scalar"){ + values (0.0122); + } + } + } + timing() { + timing_type : setup_rising; + related_pin : "A_CLK"; + when : "(A_WEN & A_MEN)" + sdf_cond : "A_RW_ACCESS" + + rise_constraint("SIG2SRAM_constraint_template") { + index_1("0.0056,0.0232,0.0400,0.0728,0.1280,0.2440,0.4760"); + index_2("0.0056,0.0232,0.0400,0.0728,0.1280,0.2440,0.4760"); + values ("-0.3214,-0.3057,-0.2921,-0.2598,-0.2130,-0.1085,0.0829",\ +"-0.3264,-0.3107,-0.2971,-0.2648,-0.2180,-0.1135,0.0779",\ +"-0.3308,-0.3152,-0.3015,-0.2693,-0.2224,-0.1179,0.0735",\ +"-0.3399,-0.3243,-0.3106,-0.2784,-0.2315,-0.1270,0.0644",\ +"-0.3472,-0.3316,-0.3179,-0.2857,-0.2388,-0.1343,0.0571",\ +"-0.3773,-0.3617,-0.3480,-0.3158,-0.2689,-0.1644,0.0270",\ +"-0.4349,-0.4193,-0.4056,-0.3734,-0.3265,-0.2220,-0.0306"); + } + + fall_constraint("SIG2SRAM_constraint_template") { + index_1("0.0056,0.0232,0.0400,0.0728,0.1280,0.2440,0.4760"); + index_2("0.0056,0.0232,0.0400,0.0728,0.1280,0.2440,0.4760"); + values ("-0.2833,-0.2686,-0.2550,-0.2266,-0.1759,-0.0782,0.1044",\ +"-0.2883,-0.2736,-0.2600,-0.2316,-0.1809,-0.0832,0.0994",\ +"-0.2927,-0.2781,-0.2644,-0.2361,-0.1853,-0.0877,0.0949",\ +"-0.3018,-0.2872,-0.2735,-0.2452,-0.1944,-0.0968,0.0858",\ +"-0.3091,-0.2945,-0.2808,-0.2525,-0.2017,-0.1040,0.0786",\ +"-0.3392,-0.3245,-0.3109,-0.2826,-0.2318,-0.1341,0.0485",\ +"-0.3968,-0.3821,-0.3685,-0.3402,-0.2894,-0.1917,-0.0091"); + } + } + + + timing() { + timing_type : hold_rising; + related_pin : "A_CLK"; + when : "(A_WEN & A_MEN)" + sdf_cond : "A_RW_ACCESS" + + rise_constraint("SIG2SRAM_constraint_template") { + index_1("0.0056,0.0232,0.0400,0.0728,0.1280,0.2440,0.4760"); + index_2("0.0056,0.0232,0.0400,0.0728,0.1280,0.2440,0.4760"); + values ("0.4304,0.4138,0.4011,0.3689,0.3210,0.2175,0.0251",\ +"0.4354,0.4188,0.4061,0.3739,0.3260,0.2225,0.0301",\ +"0.4399,0.4233,0.4106,0.3784,0.3305,0.2270,0.0346",\ +"0.4490,0.4324,0.4197,0.3875,0.3396,0.2361,0.0437",\ +"0.4563,0.4397,0.4270,0.3947,0.3469,0.2434,0.0510",\ +"0.4863,0.4697,0.4570,0.4248,0.3770,0.2734,0.0811",\ +"0.5440,0.5273,0.5147,0.4824,0.4346,0.3311,0.1387"); + } + + fall_constraint("SIG2SRAM_constraint_template") { + index_1("0.0056,0.0232,0.0400,0.0728,0.1280,0.2440,0.4760"); + index_2("0.0056,0.0232,0.0400,0.0728,0.1280,0.2440,0.4760"); + values ("0.3845,0.3699,0.3562,0.3279,0.2781,0.1853,0.0007",\ +"0.3895,0.3749,0.3612,0.3329,0.2831,0.1903,0.0057",\ +"0.3940,0.3793,0.3657,0.3374,0.2875,0.1948,0.0102",\ +"0.4031,0.3884,0.3748,0.3465,0.2966,0.2039,0.0193",\ +"0.4104,0.3957,0.3820,0.3537,0.3039,0.2111,0.0266",\ +"0.4404,0.4258,0.4121,0.3838,0.3340,0.2412,0.0567",\ +"0.4980,0.4834,0.4697,0.4414,0.3916,0.2988,0.1143"); + } + } +} + pin(A_CLK) { + direction : input; + capacitance : 0.00380014; + max_transition : "0.476"; + clock : "true" ; + pin_func_type : active_rising ; + + timing () { + timing_type : "min_pulse_width"; + related_pin : "A_CLK"; + rise_constraint("CLKTRAN_constraint_template") { + index_1("0.0056,0.476"); + values("0.21,0.21"); + } + } + + related_power_pin : VDD; + related_ground_pin : VSS; + + internal_power() { + when : "!A_MEN & !A_WEN & !A_REN"; + rise_power("scalar"){ + values (0); + } + fall_power("scalar"){ + values (0); + } + } + internal_power() { + when : "!A_MEN & A_WEN & !A_REN"; + rise_power("scalar"){ + values (0.5278); + } + fall_power("scalar"){ + values (0); + } + } + internal_power() { + when : "A_MEN & A_WEN & !A_REN"; + rise_power("scalar"){ + values (14.0418); + } + fall_power("scalar"){ + values (0); + } + } + internal_power() { + when : "A_MEN & A_WEN & A_REN"; + rise_power("scalar"){ + values (14.7504); + } + fall_power("scalar"){ + values (0); + } + } + internal_power() { + when : "A_MEN & !A_WEN & A_REN"; + rise_power("scalar"){ + values (11.3447); + } + fall_power("scalar"){ + values (0); + } + } + internal_power() { + when : "!A_MEN & !A_WEN & A_REN"; + rise_power("scalar"){ + values (0.3000); + } + fall_power("scalar"){ + values (0); + } + } + internal_power() { + when : "!A_MEN & A_WEN & A_REN"; + rise_power("scalar"){ + values (0.5369); + } + fall_power("scalar"){ + values (0); + } + } + internal_power() { + when : "A_MEN & !A_WEN & !A_REN"; + rise_power("scalar"){ + values (0); + } + fall_power("scalar"){ + values (0); + } + } + } + bus(A_DIN) { + bus_type : D_7_0; + direction : input ; + capacitance : 0.00500744 ; + memory_write() { + address : A_ADDR ; + clocked_on : A_CLK; + } + + max_transition : "0.476" ; + pin(A_DIN[7:0]) { + related_power_pin : VDD; + related_ground_pin : VSS; + internal_power() { + when : "A_MEN"; + rise_power("scalar"){ + values (0.0288); + } + fall_power("scalar"){ + values (0.0126); + } + } + internal_power() { + when : "!A_MEN"; + rise_power("scalar"){ + values (0.0317); + } + fall_power("scalar"){ + values (0.0122); + } + } + } + timing() { + timing_type : setup_rising; + related_pin : "A_CLK"; + when : "(A_WEN & A_MEN)"; + sdf_cond : "A_W_ACCESS"; + + rise_constraint("SIG2SRAM_constraint_template") { + index_1("0.0056,0.0232,0.0400,0.0728,0.1280,0.2440,0.4760"); + index_2("0.0056,0.0232,0.0400,0.0728,0.1280,0.2440,0.4760"); + values ("-0.3214,-0.3057,-0.2921,-0.2598,-0.2130,-0.1085,0.0829",\ +"-0.3264,-0.3107,-0.2971,-0.2648,-0.2180,-0.1135,0.0779",\ +"-0.3308,-0.3152,-0.3015,-0.2693,-0.2224,-0.1179,0.0735",\ +"-0.3399,-0.3243,-0.3106,-0.2784,-0.2315,-0.1270,0.0644",\ +"-0.3472,-0.3316,-0.3179,-0.2857,-0.2388,-0.1343,0.0571",\ +"-0.3773,-0.3617,-0.3480,-0.3158,-0.2689,-0.1644,0.0270",\ +"-0.4349,-0.4193,-0.4056,-0.3734,-0.3265,-0.2220,-0.0306"); + } + + fall_constraint("SIG2SRAM_constraint_template") { + index_1("0.0056,0.0232,0.0400,0.0728,0.1280,0.2440,0.4760"); + index_2("0.0056,0.0232,0.0400,0.0728,0.1280,0.2440,0.4760"); + values ("-0.2833,-0.2686,-0.2550,-0.2266,-0.1759,-0.0782,0.1044",\ +"-0.2883,-0.2736,-0.2600,-0.2316,-0.1809,-0.0832,0.0994",\ +"-0.2927,-0.2781,-0.2644,-0.2361,-0.1853,-0.0877,0.0949",\ +"-0.3018,-0.2872,-0.2735,-0.2452,-0.1944,-0.0968,0.0858",\ +"-0.3091,-0.2945,-0.2808,-0.2525,-0.2017,-0.1040,0.0786",\ +"-0.3392,-0.3245,-0.3109,-0.2826,-0.2318,-0.1341,0.0485",\ +"-0.3968,-0.3821,-0.3685,-0.3402,-0.2894,-0.1917,-0.0091"); + } + } + + timing() { + timing_type : hold_rising; + related_pin : "A_CLK"; + when : "(A_WEN & A_MEN)"; + sdf_cond : "A_W_ACCESS"; + + rise_constraint("SIG2SRAM_constraint_template") { + index_1("0.0056,0.0232,0.0400,0.0728,0.1280,0.2440,0.4760"); + index_2("0.0056,0.0232,0.0400,0.0728,0.1280,0.2440,0.4760"); + values ("0.4304,0.4138,0.4011,0.3689,0.3210,0.2175,0.0251",\ +"0.4354,0.4188,0.4061,0.3739,0.3260,0.2225,0.0301",\ +"0.4399,0.4233,0.4106,0.3784,0.3305,0.2270,0.0346",\ +"0.4490,0.4324,0.4197,0.3875,0.3396,0.2361,0.0437",\ +"0.4563,0.4397,0.4270,0.3947,0.3469,0.2434,0.0510",\ +"0.4863,0.4697,0.4570,0.4248,0.3770,0.2734,0.0811",\ +"0.5440,0.5273,0.5147,0.4824,0.4346,0.3311,0.1387"); + } + + fall_constraint("SIG2SRAM_constraint_template") { + index_1("0.0056,0.0232,0.0400,0.0728,0.1280,0.2440,0.4760"); + index_2("0.0056,0.0232,0.0400,0.0728,0.1280,0.2440,0.4760"); + values ("0.3845,0.3699,0.3562,0.3279,0.2781,0.1853,0.0007",\ +"0.3895,0.3749,0.3612,0.3329,0.2831,0.1903,0.0057",\ +"0.3940,0.3793,0.3657,0.3374,0.2875,0.1948,0.0102",\ +"0.4031,0.3884,0.3748,0.3465,0.2966,0.2039,0.0193",\ +"0.4104,0.3957,0.3820,0.3537,0.3039,0.2111,0.0266",\ +"0.4404,0.4258,0.4121,0.3838,0.3340,0.2412,0.0567",\ +"0.4980,0.4834,0.4697,0.4414,0.3916,0.2988,0.1143"); + } + } + } + + pin(A_BIST_EN) { + direction : input ; + capacitance : 0.00401111 ; + max_transition : "1" ; + related_power_pin : VDD; + related_ground_pin : VSS; + internal_power() { + rise_power("scalar") { + values (0); + } + fall_power("scalar") { + values (0); + } + } + } + +bus(A_BIST_ADDR) { + bus_type : A_8_0; + direction : input ; + capacitance : 0.0121077 ; + pin(A_BIST_ADDR[0]) { + capacitance : 0.00568653 ; + } + pin(A_BIST_ADDR[1]) { + capacitance : 0.00767263 ; + } + pin(A_BIST_ADDR[2]) { + capacitance : 0.0105079 ; + } + pin(A_BIST_ADDR[3]) { + capacitance : 0.0068178 ; + } + pin(A_BIST_ADDR[4]) { + capacitance : 0.00624497 ; + } + pin(A_BIST_ADDR[5]) { + capacitance : 0.0105871 ; + } + pin(A_BIST_ADDR[6]) { + capacitance : 0.0130817 ; + } + pin(A_BIST_ADDR[7]) { + capacitance : 0.0104931 ; + } + max_transition : "0.476" ; + pin(A_BIST_ADDR[8:0]) { + related_power_pin : VDD; + related_ground_pin : VSS; + internal_power() { + when : "A_BIST_MEN"; + rise_power("scalar"){ + values (0.0112); + } + fall_power("scalar"){ + values (0.0057); + } + } + internal_power() { + when : "!A_BIST_MEN"; + rise_power("scalar"){ + values (0.0181); + } + fall_power("scalar"){ + values (0.0008); + } + } + } + timing() { + timing_type : setup_rising; + related_pin : "A_BIST_CLK"; + when : "((A_BIST_WEN | A_BIST_REN)& A_BIST_MEN)" + sdf_cond : "A_BIST_RW_ACCESS" + + rise_constraint("SIG2SRAM_constraint_template") { + index_1("0.0056,0.0232,0.0400,0.0728,0.1280,0.2440,0.4760"); + index_2("0.0056,0.0232,0.0400,0.0728,0.1280,0.2440,0.4760"); + values ("-0.4168,-0.3973,-0.3855,-0.3543,-0.3074,-0.2020,-0.0027",\ +"-0.4324,-0.4129,-0.4012,-0.3699,-0.3191,-0.2176,-0.0184",\ +"-0.4441,-0.4285,-0.4129,-0.3816,-0.3309,-0.2293,-0.0301",\ +"-0.4793,-0.4598,-0.4441,-0.4129,-0.3660,-0.2645,-0.0652",\ +"-0.5223,-0.5066,-0.4910,-0.4598,-0.4129,-0.3074,-0.1121",\ +"-0.6199,-0.6082,-0.5926,-0.5613,-0.5145,-0.4129,-0.2137",\ +"-0.8191,-0.8074,-0.7840,-0.7566,-0.7098,-0.6082,-0.4051"); + } + + fall_constraint("SIG2SRAM_constraint_template") { + index_1("0.0056,0.0232,0.0400,0.0728,0.1280,0.2440,0.4760"); + index_2("0.0056,0.0232,0.0400,0.0728,0.1280,0.2440,0.4760"); + values ("-0.3309,-0.3113,-0.2996,-0.2684,-0.2176,-0.1238,0.0637",\ +"-0.3465,-0.3309,-0.3152,-0.2840,-0.2332,-0.1395,0.0480",\ +"-0.3582,-0.3426,-0.3270,-0.2996,-0.2488,-0.1512,0.0324",\ +"-0.3895,-0.3738,-0.3582,-0.3309,-0.2801,-0.1863,0.0051",\ +"-0.4363,-0.4207,-0.4051,-0.3777,-0.3230,-0.2293,-0.0379",\ +"-0.5379,-0.5223,-0.5066,-0.4793,-0.4285,-0.3309,-0.1434",\ +"-0.7332,-0.7176,-0.7020,-0.6746,-0.6238,-0.5262,-0.3387"); + } + } + + + timing() { + timing_type : hold_rising; + related_pin : "A_BIST_CLK"; + when : "((A_BIST_WEN | A_BIST_REN)& A_BIST_MEN)" + sdf_cond : "A_BIST_RW_ACCESS" + + rise_constraint("SIG2SRAM_constraint_template") { + index_1("0.0056,0.0232,0.0400,0.0728,0.1280,0.2440,0.4760"); + index_2("0.0056,0.0232,0.0400,0.0728,0.1280,0.2440,0.4760"); + values ("0.5246,0.5051,0.4895,0.4582,0.4113,0.3059,0.1066",\ +"0.5402,0.5207,0.5051,0.4777,0.4270,0.3215,0.1223",\ +"0.5520,0.5324,0.5168,0.4895,0.4387,0.3371,0.1340",\ +"0.5832,0.5676,0.5520,0.5207,0.4738,0.3684,0.1691",\ +"0.6301,0.6105,0.5949,0.5676,0.5168,0.4113,0.2160",\ +"0.7316,0.7121,0.7004,0.6691,0.6223,0.5168,0.3176",\ +"0.9270,0.9230,0.8957,0.8645,0.8137,0.7121,0.5168"); + } + + fall_constraint("SIG2SRAM_constraint_template") { + index_1("0.0056,0.0232,0.0400,0.0728,0.1280,0.2440,0.4760"); + index_2("0.0056,0.0232,0.0400,0.0728,0.1280,0.2440,0.4760"); + values ("0.4309,0.4152,0.4035,0.3684,0.3215,0.2277,0.0363",\ +"0.4465,0.4309,0.4152,0.3879,0.3371,0.2395,0.0559",\ +"0.4582,0.4426,0.4309,0.3996,0.3488,0.2551,0.0715",\ +"0.4934,0.4777,0.4621,0.4348,0.3840,0.2863,0.0988",\ +"0.5363,0.5207,0.5051,0.4777,0.4270,0.3332,0.1418",\ +"0.6379,0.6262,0.6105,0.5793,0.5324,0.4348,0.2434",\ +"0.8332,0.8215,0.8059,0.7707,0.7238,0.6301,0.4387"); + } + } +} +pin(A_BIST_WEN) { + direction : input ; + capacitance : 0.00324098 ; + max_transition : "0.476" ; + related_power_pin : VDD; + related_ground_pin : VSS; + internal_power() { + when : "A_BIST_MEN"; + rise_power("scalar"){ + values (0.0046); + } + fall_power("scalar"){ + values (0.0038); + } + } + internal_power() { + when : "!A_BIST_MEN"; + rise_power("scalar"){ + values (0.0042); + } + fall_power("scalar"){ + values (0.0038); + } + } + timing() { + timing_type : setup_rising; + related_pin : "A_BIST_CLK"; + when : "A_BIST_MEN" + sdf_cond : "A_BIST_MEN" + + rise_constraint("SIG2SRAM_constraint_template") { + index_1("0.0056,0.0232,0.0400,0.0728,0.1280,0.2440,0.4760"); + index_2("0.0056,0.0232,0.0400,0.0728,0.1280,0.2440,0.4760"); + values ("0.2043,0.2199,0.2316,0.2629,0.3059,0.4113,0.6066",\ +"0.1887,0.2043,0.2160,0.2473,0.2941,0.3957,0.5949",\ +"0.1691,0.1848,0.2004,0.2316,0.2785,0.3801,0.5754",\ +"0.1379,0.1574,0.1691,0.2004,0.2473,0.3527,0.5480",\ +"0.0910,0.1066,0.1223,0.1535,0.2004,0.2980,0.4973",\ +"-0.0105,0.0051,0.0207,0.0520,0.0949,0.2004,0.3957",\ +"-0.2059,-0.1902,-0.1746,-0.1473,-0.1004,0.0051,0.2004"); + } + + fall_constraint("SIG2SRAM_constraint_template") { + index_1("0.0056,0.0232,0.0400,0.0728,0.1280,0.2440,0.4760"); + index_2("0.0056,0.0232,0.0400,0.0728,0.1280,0.2440,0.4760"); + values ("0.2941,0.3098,0.3215,0.3488,0.4035,0.4973,0.6887",\ +"0.2785,0.2941,0.3059,0.3332,0.3840,0.4816,0.6691",\ +"0.2629,0.2785,0.2902,0.3176,0.3684,0.4660,0.6535",\ +"0.2316,0.2473,0.2590,0.2863,0.3410,0.4348,0.6262",\ +"0.1848,0.2004,0.2121,0.2395,0.2902,0.3879,0.5754",\ +"0.0832,0.0988,0.1105,0.1379,0.1809,0.2746,0.4699",\ +"-0.1121,-0.0965,-0.0848,-0.0535,-0.0066,0.0910,0.2824"); + } + } + + + timing() { + timing_type : hold_rising; + related_pin : "A_BIST_CLK"; + when : "A_BIST_MEN" + sdf_cond : "A_BIST_MEN" + + rise_constraint("SIG2SRAM_constraint_template") { + index_1("0.0056,0.0232,0.0400,0.0728,0.1280,0.2440,0.4760"); + index_2("0.0056,0.0232,0.0400,0.0728,0.1280,0.2440,0.4760"); + values ("0.2473,0.2316,0.2160,0.1887,0.1379,0.0363,-0.1629",\ +"0.2629,0.2473,0.2316,0.2043,0.1535,0.0520,-0.1473",\ +"0.2785,0.2590,0.2434,0.2160,0.1652,0.0676,-0.1355",\ +"0.3098,0.2941,0.2785,0.2473,0.1965,0.0910,-0.1043",\ +"0.3527,0.3371,0.3215,0.2941,0.2434,0.1418,-0.0574",\ +"0.4582,0.4426,0.4270,0.3957,0.3488,0.2434,0.0480",\ +"0.6535,0.6379,0.6184,0.5910,0.5402,0.4426,0.2434"); + } + + fall_constraint("SIG2SRAM_constraint_template") { + index_1("0.0056,0.0232,0.0400,0.0728,0.1280,0.2440,0.4760"); + index_2("0.0056,0.0232,0.0400,0.0728,0.1280,0.2440,0.4760"); + values ("0.2395,0.2238,0.2121,0.1809,0.1301,0.0324,-0.1551",\ +"0.2551,0.2395,0.2277,0.1965,0.1457,0.0480,-0.1395",\ +"0.2668,0.2551,0.2395,0.2082,0.1574,0.0637,-0.1277",\ +"0.3020,0.2863,0.2707,0.2395,0.1887,0.0910,-0.0965",\ +"0.3449,0.3293,0.3176,0.2863,0.2355,0.1379,-0.0496",\ +"0.4504,0.4348,0.4191,0.3879,0.3371,0.2395,0.0559",\ +"0.6457,0.6301,0.6145,0.5871,0.5324,0.4309,0.2512"); + } + } + } +pin(A_BIST_REN) { + direction : input ; + capacitance : 0.00381634 ; + max_transition : "0.476" ; + related_power_pin : VDD; + related_ground_pin : VSS; + internal_power() { + when : "A_BIST_MEN"; + rise_power("scalar"){ + values (0.0061); + } + fall_power("scalar"){ + values (0.0020); + } + } + internal_power() { + when : "!A_BIST_MEN"; + rise_power("scalar"){ + values (0.0061); + } + fall_power("scalar"){ + values (0.0024); + } + } + timing() { + timing_type : setup_rising; + related_pin : "A_BIST_CLK"; + when : "A_BIST_MEN" + sdf_cond : "A_BIST_MEN" + + rise_constraint("SIG2SRAM_constraint_template") { + index_1("0.0056,0.0232,0.0400,0.0728,0.1280,0.2440,0.4760"); + index_2("0.0056,0.0232,0.0400,0.0728,0.1280,0.2440,0.4760"); + values ("-0.0301,-0.0145,0.0012,0.0324,0.0793,0.1809,0.3762",\ +"-0.0457,-0.0301,-0.0145,0.0168,0.0637,0.1613,0.3605",\ +"-0.0574,-0.0418,-0.0262,0.0051,0.0520,0.1496,0.3449",\ +"-0.0926,-0.0730,-0.0574,-0.0262,0.0207,0.1184,0.3137",\ +"-0.1395,-0.1238,-0.1082,-0.0770,-0.0301,0.0715,0.2707",\ +"-0.2410,-0.2254,-0.2098,-0.1746,-0.1355,-0.0340,0.1652",\ +"-0.4402,-0.4207,-0.4051,-0.3738,-0.3270,-0.2293,-0.0340"); + } + + fall_constraint("SIG2SRAM_constraint_template") { + index_1("0.0056,0.0232,0.0400,0.0728,0.1280,0.2440,0.4760"); + index_2("0.0056,0.0232,0.0400,0.0728,0.1280,0.2440,0.4760"); + values ("0.0988,0.1145,0.1262,0.1535,0.2043,0.3020,0.4855",\ +"0.0832,0.0988,0.1105,0.1418,0.1848,0.2824,0.4738",\ +"0.0676,0.0832,0.0949,0.1262,0.1730,0.2668,0.4621",\ +"0.0402,0.0559,0.0676,0.0988,0.1457,0.2434,0.4191",\ +"-0.0105,0.0012,0.0168,0.0480,0.0988,0.1965,0.3840",\ +"-0.1160,-0.0965,-0.0848,-0.0535,-0.0066,0.0988,0.2824",\ +"-0.3113,-0.2957,-0.2801,-0.2527,-0.2059,-0.1043,0.0832"); + } + } + + + timing() { + timing_type : hold_rising; + related_pin : "A_BIST_CLK"; + when : "A_BIST_MEN" + sdf_cond : "A_BIST_MEN" + + rise_constraint("SIG2SRAM_constraint_template") { + index_1("0.0056,0.0232,0.0400,0.0728,0.1280,0.2440,0.4760"); + index_2("0.0056,0.0232,0.0400,0.0728,0.1280,0.2440,0.4760"); + values ("0.2707,0.2551,0.2395,0.2121,0.1613,0.0598,-0.1395",\ +"0.2863,0.2707,0.2551,0.2238,0.1730,0.0715,-0.1238",\ +"0.2980,0.2824,0.2668,0.2395,0.1887,0.0871,-0.1121",\ +"0.3332,0.3176,0.3020,0.2707,0.2199,0.1184,-0.0809",\ +"0.3762,0.3605,0.3449,0.3176,0.2668,0.1613,-0.0340",\ +"0.4816,0.4621,0.4504,0.4191,0.3723,0.2629,0.0715",\ +"0.6770,0.6613,0.6418,0.6184,0.5637,0.4699,0.2629"); + } + + fall_constraint("SIG2SRAM_constraint_template") { + index_1("0.0056,0.0232,0.0400,0.0728,0.1280,0.2440,0.4760"); + index_2("0.0056,0.0232,0.0400,0.0728,0.1280,0.2440,0.4760"); + values ("0.2590,0.2434,0.2316,0.2004,0.1457,0.0520,-0.1355",\ +"0.2746,0.2590,0.2434,0.2160,0.1613,0.0676,-0.1199",\ +"0.2863,0.2707,0.2590,0.2277,0.1730,0.0832,-0.1082",\ +"0.3215,0.3059,0.2902,0.2590,0.2082,0.1105,-0.0770",\ +"0.3645,0.3488,0.3332,0.3059,0.2551,0.1535,-0.0340",\ +"0.4699,0.4543,0.4387,0.4074,0.3605,0.2551,0.0715",\ +"0.6652,0.6496,0.6340,0.6027,0.5520,0.4621,0.2707"); + } + } + } +pin(A_BIST_MEN) { + direction : input ; + capacitance : 0.00309605 ; + max_transition : "0.476" ; + related_power_pin : VDD; + related_ground_pin : VSS; + internal_power() { + rise_power("scalar"){ + values (0.0236); + } + fall_power("scalar"){ + values (0.0052); + } + } + timing() { + timing_type : setup_rising; + related_pin : "A_BIST_CLK"; + + rise_constraint("SIG2SRAM_constraint_template") { + index_1("0.0056,0.0232,0.0400,0.0728,0.1280,0.2440,0.4760"); + index_2("0.0056,0.0232,0.0400,0.0728,0.1280,0.2440,0.4760"); + values ("0.2043,0.2199,0.2316,0.2668,0.3098,0.4152,0.6066",\ +"0.1887,0.2043,0.2199,0.2512,0.2941,0.3996,0.5949",\ +"0.1730,0.1887,0.2043,0.2355,0.2824,0.3840,0.5793",\ +"0.1418,0.1574,0.1730,0.2043,0.2512,0.3566,0.5480",\ +"0.0949,0.1105,0.1262,0.1574,0.2043,0.3020,0.5051",\ +"-0.0066,0.0090,0.0246,0.0520,0.0988,0.2043,0.3996",\ +"-0.2020,-0.1863,-0.1746,-0.1434,-0.0965,0.0090,0.2082"); + } + + fall_constraint("SIG2SRAM_constraint_template") { + index_1("0.0056,0.0232,0.0400,0.0728,0.1280,0.2440,0.4760"); + index_2("0.0056,0.0232,0.0400,0.0728,0.1280,0.2440,0.4760"); + values ("0.2980,0.3137,0.3254,0.3527,0.4035,0.5012,0.6887",\ +"0.2824,0.2980,0.3098,0.3371,0.3879,0.4855,0.6730",\ +"0.2668,0.2824,0.2941,0.3215,0.3723,0.4699,0.6574",\ +"0.2355,0.2473,0.2629,0.2902,0.3410,0.4387,0.6262",\ +"0.1887,0.2004,0.2160,0.2395,0.2941,0.3918,0.5793",\ +"0.0871,0.1027,0.1145,0.1418,0.1848,0.2746,0.4816",\ +"-0.1082,-0.0965,-0.0809,-0.0496,-0.0027,0.0949,0.2863"); + } + } + + + timing() { + timing_type : hold_rising; + related_pin : "A_BIST_CLK"; + + rise_constraint("SIG2SRAM_constraint_template") { + index_1("0.0056,0.0232,0.0400,0.0728,0.1280,0.2440,0.4760"); + index_2("0.0056,0.0232,0.0400,0.0728,0.1280,0.2440,0.4760"); + values ("0.2512,0.2355,0.2199,0.1926,0.1418,0.0402,-0.1590",\ +"0.2668,0.2512,0.2355,0.2082,0.1574,0.0559,-0.1434",\ +"0.2824,0.2629,0.2512,0.2199,0.1691,0.0715,-0.1316",\ +"0.3137,0.2980,0.2824,0.2512,0.2004,0.0988,-0.0965",\ +"0.3566,0.3410,0.3254,0.2980,0.2473,0.1418,-0.0535",\ +"0.4621,0.4426,0.4309,0.3996,0.3527,0.2473,0.0520",\ +"0.6574,0.6418,0.6262,0.5949,0.5441,0.4465,0.2473"); + } + + fall_constraint("SIG2SRAM_constraint_template") { + index_1("0.0056,0.0232,0.0400,0.0728,0.1280,0.2440,0.4760"); + index_2("0.0056,0.0232,0.0400,0.0728,0.1280,0.2440,0.4760"); + values ("0.2395,0.2238,0.2121,0.1809,0.1301,0.0324,-0.1551",\ +"0.2551,0.2434,0.2277,0.1965,0.1457,0.0480,-0.1395",\ +"0.2707,0.2551,0.2395,0.2082,0.1574,0.0637,-0.1277",\ +"0.3020,0.2863,0.2707,0.2434,0.1926,0.0910,-0.0965",\ +"0.3449,0.3332,0.3176,0.2863,0.2355,0.1379,-0.0496",\ +"0.4504,0.4348,0.4230,0.3918,0.3410,0.2434,0.0559",\ +"0.6457,0.6301,0.6145,0.5910,0.5324,0.4387,0.2512"); + } + } + } +bus(A_BIST_BM) { + bus_type : D_7_0; + direction : input ; + capacitance : 0.00349377 ; + max_transition : "0.476" ; + pin(A_BIST_BM[7:0]) { + related_power_pin : VDD; + related_ground_pin : VSS; + internal_power() { + when : "A_BIST_MEN"; + rise_power("scalar"){ + values (0.0288); + } + fall_power("scalar"){ + values (0.0126); + } + } + internal_power() { + when : "!A_BIST_MEN"; + rise_power("scalar"){ + values (0.0317); + } + fall_power("scalar"){ + values (0.0122); + } + } + } + timing() { + timing_type : setup_rising; + related_pin : "A_BIST_CLK"; + when : "(A_BIST_WEN & A_BIST_MEN)" + sdf_cond : "A_BIST_RW_ACCESS" + + rise_constraint("SIG2SRAM_constraint_template") { + index_1("0.0056,0.0232,0.0400,0.0728,0.1280,0.2440,0.4760"); + index_2("0.0056,0.0232,0.0400,0.0728,0.1280,0.2440,0.4760"); + values ("-0.3214,-0.3057,-0.2921,-0.2598,-0.2130,-0.1085,0.0829",\ +"-0.3264,-0.3107,-0.2971,-0.2648,-0.2180,-0.1135,0.0779",\ +"-0.3308,-0.3152,-0.3015,-0.2693,-0.2224,-0.1179,0.0735",\ +"-0.3399,-0.3243,-0.3106,-0.2784,-0.2315,-0.1270,0.0644",\ +"-0.3472,-0.3316,-0.3179,-0.2857,-0.2388,-0.1343,0.0571",\ +"-0.3773,-0.3617,-0.3480,-0.3158,-0.2689,-0.1644,0.0270",\ +"-0.4349,-0.4193,-0.4056,-0.3734,-0.3265,-0.2220,-0.0306"); + } + + fall_constraint("SIG2SRAM_constraint_template") { + index_1("0.0056,0.0232,0.0400,0.0728,0.1280,0.2440,0.4760"); + index_2("0.0056,0.0232,0.0400,0.0728,0.1280,0.2440,0.4760"); + values ("-0.2833,-0.2686,-0.2550,-0.2266,-0.1759,-0.0782,0.1044",\ +"-0.2883,-0.2736,-0.2600,-0.2316,-0.1809,-0.0832,0.0994",\ +"-0.2927,-0.2781,-0.2644,-0.2361,-0.1853,-0.0877,0.0949",\ +"-0.3018,-0.2872,-0.2735,-0.2452,-0.1944,-0.0968,0.0858",\ +"-0.3091,-0.2945,-0.2808,-0.2525,-0.2017,-0.1040,0.0786",\ +"-0.3392,-0.3245,-0.3109,-0.2826,-0.2318,-0.1341,0.0485",\ +"-0.3968,-0.3821,-0.3685,-0.3402,-0.2894,-0.1917,-0.0091"); + } + } + + + timing() { + timing_type : hold_rising; + related_pin : "A_BIST_CLK"; + when : "(A_BIST_WEN & A_BIST_MEN)" + sdf_cond : "A_BIST_RW_ACCESS" + + rise_constraint("SIG2SRAM_constraint_template") { + index_1("0.0056,0.0232,0.0400,0.0728,0.1280,0.2440,0.4760"); + index_2("0.0056,0.0232,0.0400,0.0728,0.1280,0.2440,0.4760"); + values ("0.4304,0.4138,0.4011,0.3689,0.3210,0.2175,0.0251",\ +"0.4354,0.4188,0.4061,0.3739,0.3260,0.2225,0.0301",\ +"0.4399,0.4233,0.4106,0.3784,0.3305,0.2270,0.0346",\ +"0.4490,0.4324,0.4197,0.3875,0.3396,0.2361,0.0437",\ +"0.4563,0.4397,0.4270,0.3947,0.3469,0.2434,0.0510",\ +"0.4863,0.4697,0.4570,0.4248,0.3770,0.2734,0.0811",\ +"0.5440,0.5273,0.5147,0.4824,0.4346,0.3311,0.1387"); + } + + fall_constraint("SIG2SRAM_constraint_template") { + index_1("0.0056,0.0232,0.0400,0.0728,0.1280,0.2440,0.4760"); + index_2("0.0056,0.0232,0.0400,0.0728,0.1280,0.2440,0.4760"); + values ("0.3845,0.3699,0.3562,0.3279,0.2781,0.1853,0.0007",\ +"0.3895,0.3749,0.3612,0.3329,0.2831,0.1903,0.0057",\ +"0.3940,0.3793,0.3657,0.3374,0.2875,0.1948,0.0102",\ +"0.4031,0.3884,0.3748,0.3465,0.2966,0.2039,0.0193",\ +"0.4104,0.3957,0.3820,0.3537,0.3039,0.2111,0.0266",\ +"0.4404,0.4258,0.4121,0.3838,0.3340,0.2412,0.0567",\ +"0.4980,0.4834,0.4697,0.4414,0.3916,0.2988,0.1143"); + } + } +} + pin(A_BIST_CLK) { + direction : input; + capacitance : 0.00380014; + max_transition : "0.476"; + clock : "true" ; + pin_func_type : active_rising ; + + timing () { + timing_type : "min_pulse_width"; + related_pin : "A_BIST_CLK"; + rise_constraint("CLKTRAN_constraint_template") { + index_1("0.0056,0.476"); + values("0.21,0.21"); + } + } + + related_power_pin : VDD; + related_ground_pin : VSS; + + internal_power() { + when : "!A_BIST_MEN & !A_BIST_WEN & !A_BIST_REN"; + rise_power("scalar"){ + values (0); + } + fall_power("scalar"){ + values (0); + } + } + internal_power() { + when : "!A_BIST_MEN & A_BIST_WEN & !A_BIST_REN"; + rise_power("scalar"){ + values (0.5278); + } + fall_power("scalar"){ + values (0); + } + } + internal_power() { + when : "A_BIST_MEN & A_BIST_WEN & !A_BIST_REN"; + rise_power("scalar"){ + values (14.0418); + } + fall_power("scalar"){ + values (0); + } + } + internal_power() { + when : "A_BIST_MEN & A_BIST_WEN & A_BIST_REN"; + rise_power("scalar"){ + values (14.7504); + } + fall_power("scalar"){ + values (0); + } + } + internal_power() { + when : "A_BIST_MEN & !A_BIST_WEN & A_BIST_REN"; + rise_power("scalar"){ + values (11.3447); + } + fall_power("scalar"){ + values (0); + } + } + internal_power() { + when : "!A_BIST_MEN & !A_BIST_WEN & A_BIST_REN"; + rise_power("scalar"){ + values (0.3000); + } + fall_power("scalar"){ + values (0); + } + } + internal_power() { + when : "!A_BIST_MEN & A_BIST_WEN & A_BIST_REN"; + rise_power("scalar"){ + values (0.5369); + } + fall_power("scalar"){ + values (0); + } + } + internal_power() { + when : "A_BIST_MEN & !A_BIST_WEN & !A_BIST_REN"; + rise_power("scalar"){ + values (0); + } + fall_power("scalar"){ + values (0); + } + } + } + bus(A_BIST_DIN) { + bus_type : D_7_0; + direction : input ; + capacitance : 0.00393889 ; + memory_write() { + address : A_BIST_ADDR ; + clocked_on : A_BIST_CLK; + } + + max_transition : "0.476" ; + pin(A_BIST_DIN[7:0]) { + related_power_pin : VDD; + related_ground_pin : VSS; + internal_power() { + when : "A_BIST_MEN"; + rise_power("scalar"){ + values (0.0288); + } + fall_power("scalar"){ + values (0.0126); + } + } + internal_power() { + when : "!A_BIST_MEN"; + rise_power("scalar"){ + values (0.0317); + } + fall_power("scalar"){ + values (0.0122); + } + } + } + timing() { + timing_type : setup_rising; + related_pin : "A_BIST_CLK"; + when : "(A_BIST_WEN & A_BIST_MEN)"; + sdf_cond : "A_BIST_W_ACCESS"; + + rise_constraint("SIG2SRAM_constraint_template") { + index_1("0.0056,0.0232,0.0400,0.0728,0.1280,0.2440,0.4760"); + index_2("0.0056,0.0232,0.0400,0.0728,0.1280,0.2440,0.4760"); + values ("-0.3214,-0.3057,-0.2921,-0.2598,-0.2130,-0.1085,0.0829",\ +"-0.3264,-0.3107,-0.2971,-0.2648,-0.2180,-0.1135,0.0779",\ +"-0.3308,-0.3152,-0.3015,-0.2693,-0.2224,-0.1179,0.0735",\ +"-0.3399,-0.3243,-0.3106,-0.2784,-0.2315,-0.1270,0.0644",\ +"-0.3472,-0.3316,-0.3179,-0.2857,-0.2388,-0.1343,0.0571",\ +"-0.3773,-0.3617,-0.3480,-0.3158,-0.2689,-0.1644,0.0270",\ +"-0.4349,-0.4193,-0.4056,-0.3734,-0.3265,-0.2220,-0.0306"); + } + + fall_constraint("SIG2SRAM_constraint_template") { + index_1("0.0056,0.0232,0.0400,0.0728,0.1280,0.2440,0.4760"); + index_2("0.0056,0.0232,0.0400,0.0728,0.1280,0.2440,0.4760"); + values ("-0.2833,-0.2686,-0.2550,-0.2266,-0.1759,-0.0782,0.1044",\ +"-0.2883,-0.2736,-0.2600,-0.2316,-0.1809,-0.0832,0.0994",\ +"-0.2927,-0.2781,-0.2644,-0.2361,-0.1853,-0.0877,0.0949",\ +"-0.3018,-0.2872,-0.2735,-0.2452,-0.1944,-0.0968,0.0858",\ +"-0.3091,-0.2945,-0.2808,-0.2525,-0.2017,-0.1040,0.0786",\ +"-0.3392,-0.3245,-0.3109,-0.2826,-0.2318,-0.1341,0.0485",\ +"-0.3968,-0.3821,-0.3685,-0.3402,-0.2894,-0.1917,-0.0091"); + } + } + + timing() { + timing_type : hold_rising; + related_pin : "A_BIST_CLK"; + when : "(A_BIST_WEN & A_BIST_MEN)"; + sdf_cond : "A_BIST_W_ACCESS"; + + rise_constraint("SIG2SRAM_constraint_template") { + index_1("0.0056,0.0232,0.0400,0.0728,0.1280,0.2440,0.4760"); + index_2("0.0056,0.0232,0.0400,0.0728,0.1280,0.2440,0.4760"); + values ("0.4304,0.4138,0.4011,0.3689,0.3210,0.2175,0.0251",\ +"0.4354,0.4188,0.4061,0.3739,0.3260,0.2225,0.0301",\ +"0.4399,0.4233,0.4106,0.3784,0.3305,0.2270,0.0346",\ +"0.4490,0.4324,0.4197,0.3875,0.3396,0.2361,0.0437",\ +"0.4563,0.4397,0.4270,0.3947,0.3469,0.2434,0.0510",\ +"0.4863,0.4697,0.4570,0.4248,0.3770,0.2734,0.0811",\ +"0.5440,0.5273,0.5147,0.4824,0.4346,0.3311,0.1387"); + } + + fall_constraint("SIG2SRAM_constraint_template") { + index_1("0.0056,0.0232,0.0400,0.0728,0.1280,0.2440,0.4760"); + index_2("0.0056,0.0232,0.0400,0.0728,0.1280,0.2440,0.4760"); + values ("0.3845,0.3699,0.3562,0.3279,0.2781,0.1853,0.0007",\ +"0.3895,0.3749,0.3612,0.3329,0.2831,0.1903,0.0057",\ +"0.3940,0.3793,0.3657,0.3374,0.2875,0.1948,0.0102",\ +"0.4031,0.3884,0.3748,0.3465,0.2966,0.2039,0.0193",\ +"0.4104,0.3957,0.3820,0.3537,0.3039,0.2111,0.0266",\ +"0.4404,0.4258,0.4121,0.3838,0.3340,0.2412,0.0567",\ +"0.4980,0.4834,0.4697,0.4414,0.3916,0.2988,0.1143"); + } + } + } + +bus(A_DOUT) { + + bus_type : D_7_0; + direction : output ; + capacitance : 0 ; + max_capacitance : 0.064 ; + memory_read() { + address : A_ADDR ; + } + pin(A_DOUT[7:0]) { + related_power_pin : VDD; + related_ground_pin : VSS; + internal_power() { + rise_power("scalar") { + values (0); + } + fall_power("scalar") { + values (0); + } + } + } + timing() { + related_pin : "A_CLK"; + timing_type : rising_edge ; + timing_sense : non_unate ; + + cell_rise(SIG2SRAM_delay_template) { + index_1("0.0056,0.0232,0.0400,0.0728,0.1280,0.2440,0.4760"); + index_2("0.0008,0.0014,0.0051,0.0100,0.0339,0.0640"); + values ("3.7348,3.7365,3.7441,3.7528,3.7852,3.8213",\ +"3.7400,3.7416,3.7492,3.7580,3.7904,3.8265",\ +"3.7432,3.7448,3.7524,3.7612,3.7935,3.8297",\ +"3.7557,3.7573,3.7649,3.7736,3.8060,3.8422",\ +"3.7615,3.7631,3.7707,3.7795,3.8118,3.8480",\ +"3.7925,3.7941,3.8017,3.8104,3.8428,3.8790",\ +"3.8482,3.8498,3.8574,3.8661,3.8985,3.9347"); + } + cell_fall(SIG2SRAM_delay_template) { + index_1("0.0056,0.0232,0.0400,0.0728,0.1280,0.2440,0.4760"); + index_2("0.0008,0.0014,0.0051,0.0100,0.0339,0.0640"); + values ("3.6746,3.6759,3.6820,3.6891,3.7156,3.7418",\ +"3.6797,3.6811,3.6871,3.6943,3.7208,3.7470",\ +"3.6829,3.6842,3.6903,3.6975,3.7240,3.7502",\ +"3.6954,3.6967,3.7028,3.7099,3.7364,3.7627",\ +"3.7012,3.7025,3.7086,3.7158,3.7423,3.7685",\ +"3.7322,3.7335,3.7396,3.7467,3.7732,3.7995",\ +"3.7879,3.7892,3.7953,3.8024,3.8289,3.8552"); + } + + rise_transition(SRAM_load_template) { + index_1("0.0008,0.0014,0.0051,0.0100,0.0339,0.0640"); + values ("0.0326,0.0341,0.0428,0.0518,0.0923,0.1492"); + } + fall_transition(SRAM_load_template) { + index_1("0.0008,0.0014,0.0051,0.0100,0.0339,0.0640"); + values ("0.0254,0.0265,0.0335,0.0402,0.0707,0.1039"); + } + } +} + pin(B_DLY) { + direction : input ; + capacitance : 0.00401111 ; + max_transition : "1" ; + related_power_pin : VDD; + related_ground_pin : VSS; + internal_power() { + rise_power("scalar") { + values (0); + } + fall_power("scalar") { + values (0); + } + } + } + +bus(B_ADDR) { + bus_type : A_8_0; + direction : input ; + capacitance : 0.0121077 ; + pin(B_ADDR[0]) { + capacitance : 0.00570093 ; + } + pin(B_ADDR[1]) { + capacitance : 0.00764555 ; + } + pin(B_ADDR[2]) { + capacitance : 0.0105375 ; + } + pin(B_ADDR[3]) { + capacitance : 0.0067894 ; + } + pin(B_ADDR[4]) { + capacitance : 0.00630967 ; + } + pin(B_ADDR[5]) { + capacitance : 0.0104132 ; + } + pin(B_ADDR[6]) { + capacitance : 0.0131402 ; + } + pin(B_ADDR[7]) { + capacitance : 0.0105203 ; + } + max_transition : "0.476" ; + pin(B_ADDR[8:0]) { + related_power_pin : VDD; + related_ground_pin : VSS; + internal_power() { + when : "B_MEN"; + rise_power("scalar"){ + values (0.0112); + } + fall_power("scalar"){ + values (0.0057); + } + } + internal_power() { + when : "!B_MEN"; + rise_power("scalar"){ + values (0.0181); + } + fall_power("scalar"){ + values (0.0008); + } + } + } + timing() { + timing_type : setup_rising; + related_pin : "B_CLK"; + when : "((B_WEN | B_REN)& B_MEN)" + sdf_cond : "B_RW_ACCESS" + + rise_constraint("SIG2SRAM_constraint_template") { + index_1("0.0056,0.0232,0.0400,0.0728,0.1280,0.2440,0.4760"); + index_2("0.0056,0.0232,0.0400,0.0728,0.1280,0.2440,0.4760"); + values ("-0.4168,-0.3973,-0.3855,-0.3543,-0.3074,-0.2020,-0.0027",\ +"-0.4324,-0.4129,-0.4012,-0.3699,-0.3191,-0.2176,-0.0184",\ +"-0.4441,-0.4285,-0.4129,-0.3816,-0.3309,-0.2293,-0.0301",\ +"-0.4793,-0.4598,-0.4441,-0.4129,-0.3660,-0.2645,-0.0652",\ +"-0.5223,-0.5066,-0.4910,-0.4598,-0.4129,-0.3074,-0.1121",\ +"-0.6199,-0.6082,-0.5926,-0.5613,-0.5145,-0.4129,-0.2137",\ +"-0.8191,-0.8074,-0.7840,-0.7566,-0.7098,-0.6082,-0.4051"); + } + + fall_constraint("SIG2SRAM_constraint_template") { + index_1("0.0056,0.0232,0.0400,0.0728,0.1280,0.2440,0.4760"); + index_2("0.0056,0.0232,0.0400,0.0728,0.1280,0.2440,0.4760"); + values ("-0.3309,-0.3113,-0.2996,-0.2684,-0.2176,-0.1238,0.0637",\ +"-0.3465,-0.3309,-0.3152,-0.2840,-0.2332,-0.1395,0.0480",\ +"-0.3582,-0.3426,-0.3270,-0.2996,-0.2488,-0.1512,0.0324",\ +"-0.3895,-0.3738,-0.3582,-0.3309,-0.2801,-0.1863,0.0051",\ +"-0.4363,-0.4207,-0.4051,-0.3777,-0.3230,-0.2293,-0.0379",\ +"-0.5379,-0.5223,-0.5066,-0.4793,-0.4285,-0.3309,-0.1434",\ +"-0.7332,-0.7176,-0.7020,-0.6746,-0.6238,-0.5262,-0.3387"); + } + } + + + timing() { + timing_type : hold_rising; + related_pin : "B_CLK"; + when : "((B_WEN | B_REN)& B_MEN)" + sdf_cond : "B_RW_ACCESS" + + rise_constraint("SIG2SRAM_constraint_template") { + index_1("0.0056,0.0232,0.0400,0.0728,0.1280,0.2440,0.4760"); + index_2("0.0056,0.0232,0.0400,0.0728,0.1280,0.2440,0.4760"); + values ("0.5246,0.5051,0.4895,0.4582,0.4113,0.3059,0.1066",\ +"0.5402,0.5207,0.5051,0.4777,0.4270,0.3215,0.1223",\ +"0.5520,0.5324,0.5168,0.4895,0.4387,0.3371,0.1340",\ +"0.5832,0.5676,0.5520,0.5207,0.4738,0.3684,0.1691",\ +"0.6301,0.6105,0.5949,0.5676,0.5168,0.4113,0.2160",\ +"0.7316,0.7121,0.7004,0.6691,0.6223,0.5168,0.3176",\ +"0.9270,0.9230,0.8957,0.8645,0.8137,0.7121,0.5168"); + } + + fall_constraint("SIG2SRAM_constraint_template") { + index_1("0.0056,0.0232,0.0400,0.0728,0.1280,0.2440,0.4760"); + index_2("0.0056,0.0232,0.0400,0.0728,0.1280,0.2440,0.4760"); + values ("0.4309,0.4152,0.4035,0.3684,0.3215,0.2277,0.0363",\ +"0.4465,0.4309,0.4152,0.3879,0.3371,0.2395,0.0559",\ +"0.4582,0.4426,0.4309,0.3996,0.3488,0.2551,0.0715",\ +"0.4934,0.4777,0.4621,0.4348,0.3840,0.2863,0.0988",\ +"0.5363,0.5207,0.5051,0.4777,0.4270,0.3332,0.1418",\ +"0.6379,0.6262,0.6105,0.5793,0.5324,0.4348,0.2434",\ +"0.8332,0.8215,0.8059,0.7707,0.7238,0.6301,0.4387"); + } + } +} +pin(B_WEN) { + direction : input ; + capacitance : 0.00324098 ; + max_transition : "0.476" ; + related_power_pin : VDD; + related_ground_pin : VSS; + internal_power() { + when : "B_MEN"; + rise_power("scalar"){ + values (0.0046); + } + fall_power("scalar"){ + values (0.0038); + } + } + internal_power() { + when : "!B_MEN"; + rise_power("scalar"){ + values (0.0042); + } + fall_power("scalar"){ + values (0.0038); + } + } + timing() { + timing_type : setup_rising; + related_pin : "B_CLK"; + when : "B_MEN" + sdf_cond : "B_MEN" + + rise_constraint("SIG2SRAM_constraint_template") { + index_1("0.0056,0.0232,0.0400,0.0728,0.1280,0.2440,0.4760"); + index_2("0.0056,0.0232,0.0400,0.0728,0.1280,0.2440,0.4760"); + values ("0.2043,0.2199,0.2316,0.2629,0.3059,0.4113,0.6066",\ +"0.1887,0.2043,0.2160,0.2473,0.2941,0.3957,0.5949",\ +"0.1691,0.1848,0.2004,0.2316,0.2785,0.3801,0.5754",\ +"0.1379,0.1574,0.1691,0.2004,0.2473,0.3527,0.5480",\ +"0.0910,0.1066,0.1223,0.1535,0.2004,0.2980,0.4973",\ +"-0.0105,0.0051,0.0207,0.0520,0.0949,0.2004,0.3957",\ +"-0.2059,-0.1902,-0.1746,-0.1473,-0.1004,0.0051,0.2004"); + } + + fall_constraint("SIG2SRAM_constraint_template") { + index_1("0.0056,0.0232,0.0400,0.0728,0.1280,0.2440,0.4760"); + index_2("0.0056,0.0232,0.0400,0.0728,0.1280,0.2440,0.4760"); + values ("0.2941,0.3098,0.3215,0.3488,0.4035,0.4973,0.6887",\ +"0.2785,0.2941,0.3059,0.3332,0.3840,0.4816,0.6691",\ +"0.2629,0.2785,0.2902,0.3176,0.3684,0.4660,0.6535",\ +"0.2316,0.2473,0.2590,0.2863,0.3410,0.4348,0.6262",\ +"0.1848,0.2004,0.2121,0.2395,0.2902,0.3879,0.5754",\ +"0.0832,0.0988,0.1105,0.1379,0.1809,0.2746,0.4699",\ +"-0.1121,-0.0965,-0.0848,-0.0535,-0.0066,0.0910,0.2824"); + } + } + + + timing() { + timing_type : hold_rising; + related_pin : "B_CLK"; + when : "B_MEN" + sdf_cond : "B_MEN" + + rise_constraint("SIG2SRAM_constraint_template") { + index_1("0.0056,0.0232,0.0400,0.0728,0.1280,0.2440,0.4760"); + index_2("0.0056,0.0232,0.0400,0.0728,0.1280,0.2440,0.4760"); + values ("0.2473,0.2316,0.2160,0.1887,0.1379,0.0363,-0.1629",\ +"0.2629,0.2473,0.2316,0.2043,0.1535,0.0520,-0.1473",\ +"0.2785,0.2590,0.2434,0.2160,0.1652,0.0676,-0.1355",\ +"0.3098,0.2941,0.2785,0.2473,0.1965,0.0910,-0.1043",\ +"0.3527,0.3371,0.3215,0.2941,0.2434,0.1418,-0.0574",\ +"0.4582,0.4426,0.4270,0.3957,0.3488,0.2434,0.0480",\ +"0.6535,0.6379,0.6184,0.5910,0.5402,0.4426,0.2434"); + } + + fall_constraint("SIG2SRAM_constraint_template") { + index_1("0.0056,0.0232,0.0400,0.0728,0.1280,0.2440,0.4760"); + index_2("0.0056,0.0232,0.0400,0.0728,0.1280,0.2440,0.4760"); + values ("0.2395,0.2238,0.2121,0.1809,0.1301,0.0324,-0.1551",\ +"0.2551,0.2395,0.2277,0.1965,0.1457,0.0480,-0.1395",\ +"0.2668,0.2551,0.2395,0.2082,0.1574,0.0637,-0.1277",\ +"0.3020,0.2863,0.2707,0.2395,0.1887,0.0910,-0.0965",\ +"0.3449,0.3293,0.3176,0.2863,0.2355,0.1379,-0.0496",\ +"0.4504,0.4348,0.4191,0.3879,0.3371,0.2395,0.0559",\ +"0.6457,0.6301,0.6145,0.5871,0.5324,0.4309,0.2512"); + } + } + } +pin(B_REN) { + direction : input ; + capacitance : 0.00381634 ; + max_transition : "0.476" ; + related_power_pin : VDD; + related_ground_pin : VSS; + internal_power() { + when : "B_MEN"; + rise_power("scalar"){ + values (0.0061); + } + fall_power("scalar"){ + values (0.0020); + } + } + internal_power() { + when : "!B_MEN"; + rise_power("scalar"){ + values (0.0061); + } + fall_power("scalar"){ + values (0.0024); + } + } + timing() { + timing_type : setup_rising; + related_pin : "B_CLK"; + when : "B_MEN" + sdf_cond : "B_MEN" + + rise_constraint("SIG2SRAM_constraint_template") { + index_1("0.0056,0.0232,0.0400,0.0728,0.1280,0.2440,0.4760"); + index_2("0.0056,0.0232,0.0400,0.0728,0.1280,0.2440,0.4760"); + values ("-0.0301,-0.0145,0.0012,0.0324,0.0793,0.1809,0.3762",\ +"-0.0457,-0.0301,-0.0145,0.0168,0.0637,0.1613,0.3605",\ +"-0.0574,-0.0418,-0.0262,0.0051,0.0520,0.1496,0.3449",\ +"-0.0926,-0.0730,-0.0574,-0.0262,0.0207,0.1184,0.3137",\ +"-0.1395,-0.1238,-0.1082,-0.0770,-0.0301,0.0715,0.2707",\ +"-0.2410,-0.2254,-0.2098,-0.1746,-0.1355,-0.0340,0.1652",\ +"-0.4402,-0.4207,-0.4051,-0.3738,-0.3270,-0.2293,-0.0340"); + } + + fall_constraint("SIG2SRAM_constraint_template") { + index_1("0.0056,0.0232,0.0400,0.0728,0.1280,0.2440,0.4760"); + index_2("0.0056,0.0232,0.0400,0.0728,0.1280,0.2440,0.4760"); + values ("0.0988,0.1145,0.1262,0.1535,0.2043,0.3020,0.4855",\ +"0.0832,0.0988,0.1105,0.1418,0.1848,0.2824,0.4738",\ +"0.0676,0.0832,0.0949,0.1262,0.1730,0.2668,0.4621",\ +"0.0402,0.0559,0.0676,0.0988,0.1457,0.2434,0.4191",\ +"-0.0105,0.0012,0.0168,0.0480,0.0988,0.1965,0.3840",\ +"-0.1160,-0.0965,-0.0848,-0.0535,-0.0066,0.0988,0.2824",\ +"-0.3113,-0.2957,-0.2801,-0.2527,-0.2059,-0.1043,0.0832"); + } + } + + + timing() { + timing_type : hold_rising; + related_pin : "B_CLK"; + when : "B_MEN" + sdf_cond : "B_MEN" + + rise_constraint("SIG2SRAM_constraint_template") { + index_1("0.0056,0.0232,0.0400,0.0728,0.1280,0.2440,0.4760"); + index_2("0.0056,0.0232,0.0400,0.0728,0.1280,0.2440,0.4760"); + values ("0.2707,0.2551,0.2395,0.2121,0.1613,0.0598,-0.1395",\ +"0.2863,0.2707,0.2551,0.2238,0.1730,0.0715,-0.1238",\ +"0.2980,0.2824,0.2668,0.2395,0.1887,0.0871,-0.1121",\ +"0.3332,0.3176,0.3020,0.2707,0.2199,0.1184,-0.0809",\ +"0.3762,0.3605,0.3449,0.3176,0.2668,0.1613,-0.0340",\ +"0.4816,0.4621,0.4504,0.4191,0.3723,0.2629,0.0715",\ +"0.6770,0.6613,0.6418,0.6184,0.5637,0.4699,0.2629"); + } + + fall_constraint("SIG2SRAM_constraint_template") { + index_1("0.0056,0.0232,0.0400,0.0728,0.1280,0.2440,0.4760"); + index_2("0.0056,0.0232,0.0400,0.0728,0.1280,0.2440,0.4760"); + values ("0.2590,0.2434,0.2316,0.2004,0.1457,0.0520,-0.1355",\ +"0.2746,0.2590,0.2434,0.2160,0.1613,0.0676,-0.1199",\ +"0.2863,0.2707,0.2590,0.2277,0.1730,0.0832,-0.1082",\ +"0.3215,0.3059,0.2902,0.2590,0.2082,0.1105,-0.0770",\ +"0.3645,0.3488,0.3332,0.3059,0.2551,0.1535,-0.0340",\ +"0.4699,0.4543,0.4387,0.4074,0.3605,0.2551,0.0715",\ +"0.6652,0.6496,0.6340,0.6027,0.5520,0.4621,0.2707"); + } + } + } +pin(B_MEN) { + direction : input ; + capacitance : 0.00309605 ; + max_transition : "0.476" ; + related_power_pin : VDD; + related_ground_pin : VSS; + internal_power() { + rise_power("scalar"){ + values (0.0236); + } + fall_power("scalar"){ + values (0.0052); + } + } + timing() { + timing_type : setup_rising; + related_pin : "B_CLK"; + + rise_constraint("SIG2SRAM_constraint_template") { + index_1("0.0056,0.0232,0.0400,0.0728,0.1280,0.2440,0.4760"); + index_2("0.0056,0.0232,0.0400,0.0728,0.1280,0.2440,0.4760"); + values ("0.2043,0.2199,0.2316,0.2668,0.3098,0.4152,0.6066",\ +"0.1887,0.2043,0.2199,0.2512,0.2941,0.3996,0.5949",\ +"0.1730,0.1887,0.2043,0.2355,0.2824,0.3840,0.5793",\ +"0.1418,0.1574,0.1730,0.2043,0.2512,0.3566,0.5480",\ +"0.0949,0.1105,0.1262,0.1574,0.2043,0.3020,0.5051",\ +"-0.0066,0.0090,0.0246,0.0520,0.0988,0.2043,0.3996",\ +"-0.2020,-0.1863,-0.1746,-0.1434,-0.0965,0.0090,0.2082"); + } + + fall_constraint("SIG2SRAM_constraint_template") { + index_1("0.0056,0.0232,0.0400,0.0728,0.1280,0.2440,0.4760"); + index_2("0.0056,0.0232,0.0400,0.0728,0.1280,0.2440,0.4760"); + values ("0.2980,0.3137,0.3254,0.3527,0.4035,0.5012,0.6887",\ +"0.2824,0.2980,0.3098,0.3371,0.3879,0.4855,0.6730",\ +"0.2668,0.2824,0.2941,0.3215,0.3723,0.4699,0.6574",\ +"0.2355,0.2473,0.2629,0.2902,0.3410,0.4387,0.6262",\ +"0.1887,0.2004,0.2160,0.2395,0.2941,0.3918,0.5793",\ +"0.0871,0.1027,0.1145,0.1418,0.1848,0.2746,0.4816",\ +"-0.1082,-0.0965,-0.0809,-0.0496,-0.0027,0.0949,0.2863"); + } + } + + + timing() { + timing_type : hold_rising; + related_pin : "B_CLK"; + + rise_constraint("SIG2SRAM_constraint_template") { + index_1("0.0056,0.0232,0.0400,0.0728,0.1280,0.2440,0.4760"); + index_2("0.0056,0.0232,0.0400,0.0728,0.1280,0.2440,0.4760"); + values ("0.2512,0.2355,0.2199,0.1926,0.1418,0.0402,-0.1590",\ +"0.2668,0.2512,0.2355,0.2082,0.1574,0.0559,-0.1434",\ +"0.2824,0.2629,0.2512,0.2199,0.1691,0.0715,-0.1316",\ +"0.3137,0.2980,0.2824,0.2512,0.2004,0.0988,-0.0965",\ +"0.3566,0.3410,0.3254,0.2980,0.2473,0.1418,-0.0535",\ +"0.4621,0.4426,0.4309,0.3996,0.3527,0.2473,0.0520",\ +"0.6574,0.6418,0.6262,0.5949,0.5441,0.4465,0.2473"); + } + + fall_constraint("SIG2SRAM_constraint_template") { + index_1("0.0056,0.0232,0.0400,0.0728,0.1280,0.2440,0.4760"); + index_2("0.0056,0.0232,0.0400,0.0728,0.1280,0.2440,0.4760"); + values ("0.2395,0.2238,0.2121,0.1809,0.1301,0.0324,-0.1551",\ +"0.2551,0.2434,0.2277,0.1965,0.1457,0.0480,-0.1395",\ +"0.2707,0.2551,0.2395,0.2082,0.1574,0.0637,-0.1277",\ +"0.3020,0.2863,0.2707,0.2434,0.1926,0.0910,-0.0965",\ +"0.3449,0.3332,0.3176,0.2863,0.2355,0.1379,-0.0496",\ +"0.4504,0.4348,0.4230,0.3918,0.3410,0.2434,0.0559",\ +"0.6457,0.6301,0.6145,0.5910,0.5324,0.4387,0.2512"); + } + } + } +bus(B_BM) { + bus_type : D_7_0; + direction : input ; + capacitance : 0.00312518 ; + max_transition : "0.476" ; + pin(B_BM[7:0]) { + related_power_pin : VDD; + related_ground_pin : VSS; + internal_power() { + when : "B_MEN"; + rise_power("scalar"){ + values (0.0288); + } + fall_power("scalar"){ + values (0.0126); + } + } + internal_power() { + when : "!B_MEN"; + rise_power("scalar"){ + values (0.0317); + } + fall_power("scalar"){ + values (0.0122); + } + } + } + timing() { + timing_type : setup_rising; + related_pin : "B_CLK"; + when : "(B_WEN & B_MEN)" + sdf_cond : "B_RW_ACCESS" + + rise_constraint("SIG2SRAM_constraint_template") { + index_1("0.0056,0.0232,0.0400,0.0728,0.1280,0.2440,0.4760"); + index_2("0.0056,0.0232,0.0400,0.0728,0.1280,0.2440,0.4760"); + values ("-0.3214,-0.3057,-0.2921,-0.2598,-0.2130,-0.1085,0.0829",\ +"-0.3264,-0.3107,-0.2971,-0.2648,-0.2180,-0.1135,0.0779",\ +"-0.3308,-0.3152,-0.3015,-0.2693,-0.2224,-0.1179,0.0735",\ +"-0.3399,-0.3243,-0.3106,-0.2784,-0.2315,-0.1270,0.0644",\ +"-0.3472,-0.3316,-0.3179,-0.2857,-0.2388,-0.1343,0.0571",\ +"-0.3773,-0.3617,-0.3480,-0.3158,-0.2689,-0.1644,0.0270",\ +"-0.4349,-0.4193,-0.4056,-0.3734,-0.3265,-0.2220,-0.0306"); + } + + fall_constraint("SIG2SRAM_constraint_template") { + index_1("0.0056,0.0232,0.0400,0.0728,0.1280,0.2440,0.4760"); + index_2("0.0056,0.0232,0.0400,0.0728,0.1280,0.2440,0.4760"); + values ("-0.2833,-0.2686,-0.2550,-0.2266,-0.1759,-0.0782,0.1044",\ +"-0.2883,-0.2736,-0.2600,-0.2316,-0.1809,-0.0832,0.0994",\ +"-0.2927,-0.2781,-0.2644,-0.2361,-0.1853,-0.0877,0.0949",\ +"-0.3018,-0.2872,-0.2735,-0.2452,-0.1944,-0.0968,0.0858",\ +"-0.3091,-0.2945,-0.2808,-0.2525,-0.2017,-0.1040,0.0786",\ +"-0.3392,-0.3245,-0.3109,-0.2826,-0.2318,-0.1341,0.0485",\ +"-0.3968,-0.3821,-0.3685,-0.3402,-0.2894,-0.1917,-0.0091"); + } + } + + + timing() { + timing_type : hold_rising; + related_pin : "B_CLK"; + when : "(B_WEN & B_MEN)" + sdf_cond : "B_RW_ACCESS" + + rise_constraint("SIG2SRAM_constraint_template") { + index_1("0.0056,0.0232,0.0400,0.0728,0.1280,0.2440,0.4760"); + index_2("0.0056,0.0232,0.0400,0.0728,0.1280,0.2440,0.4760"); + values ("0.4304,0.4138,0.4011,0.3689,0.3210,0.2175,0.0251",\ +"0.4354,0.4188,0.4061,0.3739,0.3260,0.2225,0.0301",\ +"0.4399,0.4233,0.4106,0.3784,0.3305,0.2270,0.0346",\ +"0.4490,0.4324,0.4197,0.3875,0.3396,0.2361,0.0437",\ +"0.4563,0.4397,0.4270,0.3947,0.3469,0.2434,0.0510",\ +"0.4863,0.4697,0.4570,0.4248,0.3770,0.2734,0.0811",\ +"0.5440,0.5273,0.5147,0.4824,0.4346,0.3311,0.1387"); + } + + fall_constraint("SIG2SRAM_constraint_template") { + index_1("0.0056,0.0232,0.0400,0.0728,0.1280,0.2440,0.4760"); + index_2("0.0056,0.0232,0.0400,0.0728,0.1280,0.2440,0.4760"); + values ("0.3845,0.3699,0.3562,0.3279,0.2781,0.1853,0.0007",\ +"0.3895,0.3749,0.3612,0.3329,0.2831,0.1903,0.0057",\ +"0.3940,0.3793,0.3657,0.3374,0.2875,0.1948,0.0102",\ +"0.4031,0.3884,0.3748,0.3465,0.2966,0.2039,0.0193",\ +"0.4104,0.3957,0.3820,0.3537,0.3039,0.2111,0.0266",\ +"0.4404,0.4258,0.4121,0.3838,0.3340,0.2412,0.0567",\ +"0.4980,0.4834,0.4697,0.4414,0.3916,0.2988,0.1143"); + } + } +} + pin(B_CLK) { + direction : input; + capacitance : 0.00380014; + max_transition : "0.476"; + clock : "true" ; + pin_func_type : active_rising ; + + timing () { + timing_type : "min_pulse_width"; + related_pin : "B_CLK"; + rise_constraint("CLKTRAN_constraint_template") { + index_1("0.0056,0.476"); + values("0.21,0.21"); + } + } + + related_power_pin : VDD; + related_ground_pin : VSS; + + internal_power() { + when : "!B_MEN & !B_WEN & !B_REN"; + rise_power("scalar"){ + values (0); + } + fall_power("scalar"){ + values (0); + } + } + internal_power() { + when : "!B_MEN & B_WEN & !B_REN"; + rise_power("scalar"){ + values (0.5278); + } + fall_power("scalar"){ + values (0); + } + } + internal_power() { + when : "B_MEN & B_WEN & !B_REN"; + rise_power("scalar"){ + values (14.0418); + } + fall_power("scalar"){ + values (0); + } + } + internal_power() { + when : "B_MEN & B_WEN & B_REN"; + rise_power("scalar"){ + values (14.7504); + } + fall_power("scalar"){ + values (0); + } + } + internal_power() { + when : "B_MEN & !B_WEN & B_REN"; + rise_power("scalar"){ + values (11.3447); + } + fall_power("scalar"){ + values (0); + } + } + internal_power() { + when : "!B_MEN & !B_WEN & B_REN"; + rise_power("scalar"){ + values (0.3000); + } + fall_power("scalar"){ + values (0); + } + } + internal_power() { + when : "!B_MEN & B_WEN & B_REN"; + rise_power("scalar"){ + values (0.5369); + } + fall_power("scalar"){ + values (0); + } + } + internal_power() { + when : "B_MEN & !B_WEN & !B_REN"; + rise_power("scalar"){ + values (0); + } + fall_power("scalar"){ + values (0); + } + } + } + bus(B_DIN) { + bus_type : D_7_0; + direction : input ; + capacitance : 0.00461776 ; + memory_write() { + address : B_ADDR ; + clocked_on : B_CLK; + } + + max_transition : "0.476" ; + pin(B_DIN[7:0]) { + related_power_pin : VDD; + related_ground_pin : VSS; + internal_power() { + when : "B_MEN"; + rise_power("scalar"){ + values (0.0288); + } + fall_power("scalar"){ + values (0.0126); + } + } + internal_power() { + when : "!B_MEN"; + rise_power("scalar"){ + values (0.0317); + } + fall_power("scalar"){ + values (0.0122); + } + } + } + timing() { + timing_type : setup_rising; + related_pin : "B_CLK"; + when : "(B_WEN & B_MEN)"; + sdf_cond : "B_W_ACCESS"; + + rise_constraint("SIG2SRAM_constraint_template") { + index_1("0.0056,0.0232,0.0400,0.0728,0.1280,0.2440,0.4760"); + index_2("0.0056,0.0232,0.0400,0.0728,0.1280,0.2440,0.4760"); + values ("-0.3214,-0.3057,-0.2921,-0.2598,-0.2130,-0.1085,0.0829",\ +"-0.3264,-0.3107,-0.2971,-0.2648,-0.2180,-0.1135,0.0779",\ +"-0.3308,-0.3152,-0.3015,-0.2693,-0.2224,-0.1179,0.0735",\ +"-0.3399,-0.3243,-0.3106,-0.2784,-0.2315,-0.1270,0.0644",\ +"-0.3472,-0.3316,-0.3179,-0.2857,-0.2388,-0.1343,0.0571",\ +"-0.3773,-0.3617,-0.3480,-0.3158,-0.2689,-0.1644,0.0270",\ +"-0.4349,-0.4193,-0.4056,-0.3734,-0.3265,-0.2220,-0.0306"); + } + + fall_constraint("SIG2SRAM_constraint_template") { + index_1("0.0056,0.0232,0.0400,0.0728,0.1280,0.2440,0.4760"); + index_2("0.0056,0.0232,0.0400,0.0728,0.1280,0.2440,0.4760"); + values ("-0.2833,-0.2686,-0.2550,-0.2266,-0.1759,-0.0782,0.1044",\ +"-0.2883,-0.2736,-0.2600,-0.2316,-0.1809,-0.0832,0.0994",\ +"-0.2927,-0.2781,-0.2644,-0.2361,-0.1853,-0.0877,0.0949",\ +"-0.3018,-0.2872,-0.2735,-0.2452,-0.1944,-0.0968,0.0858",\ +"-0.3091,-0.2945,-0.2808,-0.2525,-0.2017,-0.1040,0.0786",\ +"-0.3392,-0.3245,-0.3109,-0.2826,-0.2318,-0.1341,0.0485",\ +"-0.3968,-0.3821,-0.3685,-0.3402,-0.2894,-0.1917,-0.0091"); + } + } + + timing() { + timing_type : hold_rising; + related_pin : "B_CLK"; + when : "(B_WEN & B_MEN)"; + sdf_cond : "B_W_ACCESS"; + + rise_constraint("SIG2SRAM_constraint_template") { + index_1("0.0056,0.0232,0.0400,0.0728,0.1280,0.2440,0.4760"); + index_2("0.0056,0.0232,0.0400,0.0728,0.1280,0.2440,0.4760"); + values ("0.4304,0.4138,0.4011,0.3689,0.3210,0.2175,0.0251",\ +"0.4354,0.4188,0.4061,0.3739,0.3260,0.2225,0.0301",\ +"0.4399,0.4233,0.4106,0.3784,0.3305,0.2270,0.0346",\ +"0.4490,0.4324,0.4197,0.3875,0.3396,0.2361,0.0437",\ +"0.4563,0.4397,0.4270,0.3947,0.3469,0.2434,0.0510",\ +"0.4863,0.4697,0.4570,0.4248,0.3770,0.2734,0.0811",\ +"0.5440,0.5273,0.5147,0.4824,0.4346,0.3311,0.1387"); + } + + fall_constraint("SIG2SRAM_constraint_template") { + index_1("0.0056,0.0232,0.0400,0.0728,0.1280,0.2440,0.4760"); + index_2("0.0056,0.0232,0.0400,0.0728,0.1280,0.2440,0.4760"); + values ("0.3845,0.3699,0.3562,0.3279,0.2781,0.1853,0.0007",\ +"0.3895,0.3749,0.3612,0.3329,0.2831,0.1903,0.0057",\ +"0.3940,0.3793,0.3657,0.3374,0.2875,0.1948,0.0102",\ +"0.4031,0.3884,0.3748,0.3465,0.2966,0.2039,0.0193",\ +"0.4104,0.3957,0.3820,0.3537,0.3039,0.2111,0.0266",\ +"0.4404,0.4258,0.4121,0.3838,0.3340,0.2412,0.0567",\ +"0.4980,0.4834,0.4697,0.4414,0.3916,0.2988,0.1143"); + } + } + } + + pin(B_BIST_EN) { + direction : input ; + capacitance : 0.00401111 ; + max_transition : "1" ; + related_power_pin : VDD; + related_ground_pin : VSS; + internal_power() { + rise_power("scalar") { + values (0); + } + fall_power("scalar") { + values (0); + } + } + } + +bus(B_BIST_ADDR) { + bus_type : A_8_0; + direction : input ; + capacitance : 0.0121077 ; + pin(B_BIST_ADDR[0]) { + capacitance : 0.00570093 ; + } + pin(B_BIST_ADDR[1]) { + capacitance : 0.00764555 ; + } + pin(B_BIST_ADDR[2]) { + capacitance : 0.0105375 ; + } + pin(B_BIST_ADDR[3]) { + capacitance : 0.0067894 ; + } + pin(B_BIST_ADDR[4]) { + capacitance : 0.00630967 ; + } + pin(B_BIST_ADDR[5]) { + capacitance : 0.0104132 ; + } + pin(B_BIST_ADDR[6]) { + capacitance : 0.0131402 ; + } + pin(B_BIST_ADDR[7]) { + capacitance : 0.0105203 ; + } + max_transition : "0.476" ; + pin(B_BIST_ADDR[8:0]) { + related_power_pin : VDD; + related_ground_pin : VSS; + internal_power() { + when : "B_BIST_MEN"; + rise_power("scalar"){ + values (0.0112); + } + fall_power("scalar"){ + values (0.0057); + } + } + internal_power() { + when : "!B_BIST_MEN"; + rise_power("scalar"){ + values (0.0181); + } + fall_power("scalar"){ + values (0.0008); + } + } + } + timing() { + timing_type : setup_rising; + related_pin : "B_BIST_CLK"; + when : "((B_BIST_WEN | B_BIST_REN)& B_BIST_MEN)" + sdf_cond : "B_BIST_RW_ACCESS" + + rise_constraint("SIG2SRAM_constraint_template") { + index_1("0.0056,0.0232,0.0400,0.0728,0.1280,0.2440,0.4760"); + index_2("0.0056,0.0232,0.0400,0.0728,0.1280,0.2440,0.4760"); + values ("-0.4168,-0.3973,-0.3855,-0.3543,-0.3074,-0.2020,-0.0027",\ +"-0.4324,-0.4129,-0.4012,-0.3699,-0.3191,-0.2176,-0.0184",\ +"-0.4441,-0.4285,-0.4129,-0.3816,-0.3309,-0.2293,-0.0301",\ +"-0.4793,-0.4598,-0.4441,-0.4129,-0.3660,-0.2645,-0.0652",\ +"-0.5223,-0.5066,-0.4910,-0.4598,-0.4129,-0.3074,-0.1121",\ +"-0.6199,-0.6082,-0.5926,-0.5613,-0.5145,-0.4129,-0.2137",\ +"-0.8191,-0.8074,-0.7840,-0.7566,-0.7098,-0.6082,-0.4051"); + } + + fall_constraint("SIG2SRAM_constraint_template") { + index_1("0.0056,0.0232,0.0400,0.0728,0.1280,0.2440,0.4760"); + index_2("0.0056,0.0232,0.0400,0.0728,0.1280,0.2440,0.4760"); + values ("-0.3309,-0.3113,-0.2996,-0.2684,-0.2176,-0.1238,0.0637",\ +"-0.3465,-0.3309,-0.3152,-0.2840,-0.2332,-0.1395,0.0480",\ +"-0.3582,-0.3426,-0.3270,-0.2996,-0.2488,-0.1512,0.0324",\ +"-0.3895,-0.3738,-0.3582,-0.3309,-0.2801,-0.1863,0.0051",\ +"-0.4363,-0.4207,-0.4051,-0.3777,-0.3230,-0.2293,-0.0379",\ +"-0.5379,-0.5223,-0.5066,-0.4793,-0.4285,-0.3309,-0.1434",\ +"-0.7332,-0.7176,-0.7020,-0.6746,-0.6238,-0.5262,-0.3387"); + } + } + + + timing() { + timing_type : hold_rising; + related_pin : "B_BIST_CLK"; + when : "((B_BIST_WEN | B_BIST_REN)& B_BIST_MEN)" + sdf_cond : "B_BIST_RW_ACCESS" + + rise_constraint("SIG2SRAM_constraint_template") { + index_1("0.0056,0.0232,0.0400,0.0728,0.1280,0.2440,0.4760"); + index_2("0.0056,0.0232,0.0400,0.0728,0.1280,0.2440,0.4760"); + values ("0.5246,0.5051,0.4895,0.4582,0.4113,0.3059,0.1066",\ +"0.5402,0.5207,0.5051,0.4777,0.4270,0.3215,0.1223",\ +"0.5520,0.5324,0.5168,0.4895,0.4387,0.3371,0.1340",\ +"0.5832,0.5676,0.5520,0.5207,0.4738,0.3684,0.1691",\ +"0.6301,0.6105,0.5949,0.5676,0.5168,0.4113,0.2160",\ +"0.7316,0.7121,0.7004,0.6691,0.6223,0.5168,0.3176",\ +"0.9270,0.9230,0.8957,0.8645,0.8137,0.7121,0.5168"); + } + + fall_constraint("SIG2SRAM_constraint_template") { + index_1("0.0056,0.0232,0.0400,0.0728,0.1280,0.2440,0.4760"); + index_2("0.0056,0.0232,0.0400,0.0728,0.1280,0.2440,0.4760"); + values ("0.4309,0.4152,0.4035,0.3684,0.3215,0.2277,0.0363",\ +"0.4465,0.4309,0.4152,0.3879,0.3371,0.2395,0.0559",\ +"0.4582,0.4426,0.4309,0.3996,0.3488,0.2551,0.0715",\ +"0.4934,0.4777,0.4621,0.4348,0.3840,0.2863,0.0988",\ +"0.5363,0.5207,0.5051,0.4777,0.4270,0.3332,0.1418",\ +"0.6379,0.6262,0.6105,0.5793,0.5324,0.4348,0.2434",\ +"0.8332,0.8215,0.8059,0.7707,0.7238,0.6301,0.4387"); + } + } +} +pin(B_BIST_WEN) { + direction : input ; + capacitance : 0.00324098 ; + max_transition : "0.476" ; + related_power_pin : VDD; + related_ground_pin : VSS; + internal_power() { + when : "B_BIST_MEN"; + rise_power("scalar"){ + values (0.0046); + } + fall_power("scalar"){ + values (0.0038); + } + } + internal_power() { + when : "!B_BIST_MEN"; + rise_power("scalar"){ + values (0.0042); + } + fall_power("scalar"){ + values (0.0038); + } + } + timing() { + timing_type : setup_rising; + related_pin : "B_BIST_CLK"; + when : "B_BIST_MEN" + sdf_cond : "B_BIST_MEN" + + rise_constraint("SIG2SRAM_constraint_template") { + index_1("0.0056,0.0232,0.0400,0.0728,0.1280,0.2440,0.4760"); + index_2("0.0056,0.0232,0.0400,0.0728,0.1280,0.2440,0.4760"); + values ("0.2043,0.2199,0.2316,0.2629,0.3059,0.4113,0.6066",\ +"0.1887,0.2043,0.2160,0.2473,0.2941,0.3957,0.5949",\ +"0.1691,0.1848,0.2004,0.2316,0.2785,0.3801,0.5754",\ +"0.1379,0.1574,0.1691,0.2004,0.2473,0.3527,0.5480",\ +"0.0910,0.1066,0.1223,0.1535,0.2004,0.2980,0.4973",\ +"-0.0105,0.0051,0.0207,0.0520,0.0949,0.2004,0.3957",\ +"-0.2059,-0.1902,-0.1746,-0.1473,-0.1004,0.0051,0.2004"); + } + + fall_constraint("SIG2SRAM_constraint_template") { + index_1("0.0056,0.0232,0.0400,0.0728,0.1280,0.2440,0.4760"); + index_2("0.0056,0.0232,0.0400,0.0728,0.1280,0.2440,0.4760"); + values ("0.2941,0.3098,0.3215,0.3488,0.4035,0.4973,0.6887",\ +"0.2785,0.2941,0.3059,0.3332,0.3840,0.4816,0.6691",\ +"0.2629,0.2785,0.2902,0.3176,0.3684,0.4660,0.6535",\ +"0.2316,0.2473,0.2590,0.2863,0.3410,0.4348,0.6262",\ +"0.1848,0.2004,0.2121,0.2395,0.2902,0.3879,0.5754",\ +"0.0832,0.0988,0.1105,0.1379,0.1809,0.2746,0.4699",\ +"-0.1121,-0.0965,-0.0848,-0.0535,-0.0066,0.0910,0.2824"); + } + } + + + timing() { + timing_type : hold_rising; + related_pin : "B_BIST_CLK"; + when : "B_BIST_MEN" + sdf_cond : "B_BIST_MEN" + + rise_constraint("SIG2SRAM_constraint_template") { + index_1("0.0056,0.0232,0.0400,0.0728,0.1280,0.2440,0.4760"); + index_2("0.0056,0.0232,0.0400,0.0728,0.1280,0.2440,0.4760"); + values ("0.2473,0.2316,0.2160,0.1887,0.1379,0.0363,-0.1629",\ +"0.2629,0.2473,0.2316,0.2043,0.1535,0.0520,-0.1473",\ +"0.2785,0.2590,0.2434,0.2160,0.1652,0.0676,-0.1355",\ +"0.3098,0.2941,0.2785,0.2473,0.1965,0.0910,-0.1043",\ +"0.3527,0.3371,0.3215,0.2941,0.2434,0.1418,-0.0574",\ +"0.4582,0.4426,0.4270,0.3957,0.3488,0.2434,0.0480",\ +"0.6535,0.6379,0.6184,0.5910,0.5402,0.4426,0.2434"); + } + + fall_constraint("SIG2SRAM_constraint_template") { + index_1("0.0056,0.0232,0.0400,0.0728,0.1280,0.2440,0.4760"); + index_2("0.0056,0.0232,0.0400,0.0728,0.1280,0.2440,0.4760"); + values ("0.2395,0.2238,0.2121,0.1809,0.1301,0.0324,-0.1551",\ +"0.2551,0.2395,0.2277,0.1965,0.1457,0.0480,-0.1395",\ +"0.2668,0.2551,0.2395,0.2082,0.1574,0.0637,-0.1277",\ +"0.3020,0.2863,0.2707,0.2395,0.1887,0.0910,-0.0965",\ +"0.3449,0.3293,0.3176,0.2863,0.2355,0.1379,-0.0496",\ +"0.4504,0.4348,0.4191,0.3879,0.3371,0.2395,0.0559",\ +"0.6457,0.6301,0.6145,0.5871,0.5324,0.4309,0.2512"); + } + } + } +pin(B_BIST_REN) { + direction : input ; + capacitance : 0.00381634 ; + max_transition : "0.476" ; + related_power_pin : VDD; + related_ground_pin : VSS; + internal_power() { + when : "B_BIST_MEN"; + rise_power("scalar"){ + values (0.0061); + } + fall_power("scalar"){ + values (0.0020); + } + } + internal_power() { + when : "!B_BIST_MEN"; + rise_power("scalar"){ + values (0.0061); + } + fall_power("scalar"){ + values (0.0024); + } + } + timing() { + timing_type : setup_rising; + related_pin : "B_BIST_CLK"; + when : "B_BIST_MEN" + sdf_cond : "B_BIST_MEN" + + rise_constraint("SIG2SRAM_constraint_template") { + index_1("0.0056,0.0232,0.0400,0.0728,0.1280,0.2440,0.4760"); + index_2("0.0056,0.0232,0.0400,0.0728,0.1280,0.2440,0.4760"); + values ("-0.0301,-0.0145,0.0012,0.0324,0.0793,0.1809,0.3762",\ +"-0.0457,-0.0301,-0.0145,0.0168,0.0637,0.1613,0.3605",\ +"-0.0574,-0.0418,-0.0262,0.0051,0.0520,0.1496,0.3449",\ +"-0.0926,-0.0730,-0.0574,-0.0262,0.0207,0.1184,0.3137",\ +"-0.1395,-0.1238,-0.1082,-0.0770,-0.0301,0.0715,0.2707",\ +"-0.2410,-0.2254,-0.2098,-0.1746,-0.1355,-0.0340,0.1652",\ +"-0.4402,-0.4207,-0.4051,-0.3738,-0.3270,-0.2293,-0.0340"); + } + + fall_constraint("SIG2SRAM_constraint_template") { + index_1("0.0056,0.0232,0.0400,0.0728,0.1280,0.2440,0.4760"); + index_2("0.0056,0.0232,0.0400,0.0728,0.1280,0.2440,0.4760"); + values ("0.0988,0.1145,0.1262,0.1535,0.2043,0.3020,0.4855",\ +"0.0832,0.0988,0.1105,0.1418,0.1848,0.2824,0.4738",\ +"0.0676,0.0832,0.0949,0.1262,0.1730,0.2668,0.4621",\ +"0.0402,0.0559,0.0676,0.0988,0.1457,0.2434,0.4191",\ +"-0.0105,0.0012,0.0168,0.0480,0.0988,0.1965,0.3840",\ +"-0.1160,-0.0965,-0.0848,-0.0535,-0.0066,0.0988,0.2824",\ +"-0.3113,-0.2957,-0.2801,-0.2527,-0.2059,-0.1043,0.0832"); + } + } + + + timing() { + timing_type : hold_rising; + related_pin : "B_BIST_CLK"; + when : "B_BIST_MEN" + sdf_cond : "B_BIST_MEN" + + rise_constraint("SIG2SRAM_constraint_template") { + index_1("0.0056,0.0232,0.0400,0.0728,0.1280,0.2440,0.4760"); + index_2("0.0056,0.0232,0.0400,0.0728,0.1280,0.2440,0.4760"); + values ("0.2707,0.2551,0.2395,0.2121,0.1613,0.0598,-0.1395",\ +"0.2863,0.2707,0.2551,0.2238,0.1730,0.0715,-0.1238",\ +"0.2980,0.2824,0.2668,0.2395,0.1887,0.0871,-0.1121",\ +"0.3332,0.3176,0.3020,0.2707,0.2199,0.1184,-0.0809",\ +"0.3762,0.3605,0.3449,0.3176,0.2668,0.1613,-0.0340",\ +"0.4816,0.4621,0.4504,0.4191,0.3723,0.2629,0.0715",\ +"0.6770,0.6613,0.6418,0.6184,0.5637,0.4699,0.2629"); + } + + fall_constraint("SIG2SRAM_constraint_template") { + index_1("0.0056,0.0232,0.0400,0.0728,0.1280,0.2440,0.4760"); + index_2("0.0056,0.0232,0.0400,0.0728,0.1280,0.2440,0.4760"); + values ("0.2590,0.2434,0.2316,0.2004,0.1457,0.0520,-0.1355",\ +"0.2746,0.2590,0.2434,0.2160,0.1613,0.0676,-0.1199",\ +"0.2863,0.2707,0.2590,0.2277,0.1730,0.0832,-0.1082",\ +"0.3215,0.3059,0.2902,0.2590,0.2082,0.1105,-0.0770",\ +"0.3645,0.3488,0.3332,0.3059,0.2551,0.1535,-0.0340",\ +"0.4699,0.4543,0.4387,0.4074,0.3605,0.2551,0.0715",\ +"0.6652,0.6496,0.6340,0.6027,0.5520,0.4621,0.2707"); + } + } + } +pin(B_BIST_MEN) { + direction : input ; + capacitance : 0.00309605 ; + max_transition : "0.476" ; + related_power_pin : VDD; + related_ground_pin : VSS; + internal_power() { + rise_power("scalar"){ + values (0.0236); + } + fall_power("scalar"){ + values (0.0052); + } + } + timing() { + timing_type : setup_rising; + related_pin : "B_BIST_CLK"; + + rise_constraint("SIG2SRAM_constraint_template") { + index_1("0.0056,0.0232,0.0400,0.0728,0.1280,0.2440,0.4760"); + index_2("0.0056,0.0232,0.0400,0.0728,0.1280,0.2440,0.4760"); + values ("0.2043,0.2199,0.2316,0.2668,0.3098,0.4152,0.6066",\ +"0.1887,0.2043,0.2199,0.2512,0.2941,0.3996,0.5949",\ +"0.1730,0.1887,0.2043,0.2355,0.2824,0.3840,0.5793",\ +"0.1418,0.1574,0.1730,0.2043,0.2512,0.3566,0.5480",\ +"0.0949,0.1105,0.1262,0.1574,0.2043,0.3020,0.5051",\ +"-0.0066,0.0090,0.0246,0.0520,0.0988,0.2043,0.3996",\ +"-0.2020,-0.1863,-0.1746,-0.1434,-0.0965,0.0090,0.2082"); + } + + fall_constraint("SIG2SRAM_constraint_template") { + index_1("0.0056,0.0232,0.0400,0.0728,0.1280,0.2440,0.4760"); + index_2("0.0056,0.0232,0.0400,0.0728,0.1280,0.2440,0.4760"); + values ("0.2980,0.3137,0.3254,0.3527,0.4035,0.5012,0.6887",\ +"0.2824,0.2980,0.3098,0.3371,0.3879,0.4855,0.6730",\ +"0.2668,0.2824,0.2941,0.3215,0.3723,0.4699,0.6574",\ +"0.2355,0.2473,0.2629,0.2902,0.3410,0.4387,0.6262",\ +"0.1887,0.2004,0.2160,0.2395,0.2941,0.3918,0.5793",\ +"0.0871,0.1027,0.1145,0.1418,0.1848,0.2746,0.4816",\ +"-0.1082,-0.0965,-0.0809,-0.0496,-0.0027,0.0949,0.2863"); + } + } + + + timing() { + timing_type : hold_rising; + related_pin : "B_BIST_CLK"; + + rise_constraint("SIG2SRAM_constraint_template") { + index_1("0.0056,0.0232,0.0400,0.0728,0.1280,0.2440,0.4760"); + index_2("0.0056,0.0232,0.0400,0.0728,0.1280,0.2440,0.4760"); + values ("0.2512,0.2355,0.2199,0.1926,0.1418,0.0402,-0.1590",\ +"0.2668,0.2512,0.2355,0.2082,0.1574,0.0559,-0.1434",\ +"0.2824,0.2629,0.2512,0.2199,0.1691,0.0715,-0.1316",\ +"0.3137,0.2980,0.2824,0.2512,0.2004,0.0988,-0.0965",\ +"0.3566,0.3410,0.3254,0.2980,0.2473,0.1418,-0.0535",\ +"0.4621,0.4426,0.4309,0.3996,0.3527,0.2473,0.0520",\ +"0.6574,0.6418,0.6262,0.5949,0.5441,0.4465,0.2473"); + } + + fall_constraint("SIG2SRAM_constraint_template") { + index_1("0.0056,0.0232,0.0400,0.0728,0.1280,0.2440,0.4760"); + index_2("0.0056,0.0232,0.0400,0.0728,0.1280,0.2440,0.4760"); + values ("0.2395,0.2238,0.2121,0.1809,0.1301,0.0324,-0.1551",\ +"0.2551,0.2434,0.2277,0.1965,0.1457,0.0480,-0.1395",\ +"0.2707,0.2551,0.2395,0.2082,0.1574,0.0637,-0.1277",\ +"0.3020,0.2863,0.2707,0.2434,0.1926,0.0910,-0.0965",\ +"0.3449,0.3332,0.3176,0.2863,0.2355,0.1379,-0.0496",\ +"0.4504,0.4348,0.4230,0.3918,0.3410,0.2434,0.0559",\ +"0.6457,0.6301,0.6145,0.5910,0.5324,0.4387,0.2512"); + } + } + } +bus(B_BIST_BM) { + bus_type : D_7_0; + direction : input ; + capacitance : 0.00275526 ; + max_transition : "0.476" ; + pin(B_BIST_BM[7:0]) { + related_power_pin : VDD; + related_ground_pin : VSS; + internal_power() { + when : "B_BIST_MEN"; + rise_power("scalar"){ + values (0.0288); + } + fall_power("scalar"){ + values (0.0126); + } + } + internal_power() { + when : "!B_BIST_MEN"; + rise_power("scalar"){ + values (0.0317); + } + fall_power("scalar"){ + values (0.0122); + } + } + } + timing() { + timing_type : setup_rising; + related_pin : "B_BIST_CLK"; + when : "(B_BIST_WEN & B_BIST_MEN)" + sdf_cond : "B_BIST_RW_ACCESS" + + rise_constraint("SIG2SRAM_constraint_template") { + index_1("0.0056,0.0232,0.0400,0.0728,0.1280,0.2440,0.4760"); + index_2("0.0056,0.0232,0.0400,0.0728,0.1280,0.2440,0.4760"); + values ("-0.3214,-0.3057,-0.2921,-0.2598,-0.2130,-0.1085,0.0829",\ +"-0.3264,-0.3107,-0.2971,-0.2648,-0.2180,-0.1135,0.0779",\ +"-0.3308,-0.3152,-0.3015,-0.2693,-0.2224,-0.1179,0.0735",\ +"-0.3399,-0.3243,-0.3106,-0.2784,-0.2315,-0.1270,0.0644",\ +"-0.3472,-0.3316,-0.3179,-0.2857,-0.2388,-0.1343,0.0571",\ +"-0.3773,-0.3617,-0.3480,-0.3158,-0.2689,-0.1644,0.0270",\ +"-0.4349,-0.4193,-0.4056,-0.3734,-0.3265,-0.2220,-0.0306"); + } + + fall_constraint("SIG2SRAM_constraint_template") { + index_1("0.0056,0.0232,0.0400,0.0728,0.1280,0.2440,0.4760"); + index_2("0.0056,0.0232,0.0400,0.0728,0.1280,0.2440,0.4760"); + values ("-0.2833,-0.2686,-0.2550,-0.2266,-0.1759,-0.0782,0.1044",\ +"-0.2883,-0.2736,-0.2600,-0.2316,-0.1809,-0.0832,0.0994",\ +"-0.2927,-0.2781,-0.2644,-0.2361,-0.1853,-0.0877,0.0949",\ +"-0.3018,-0.2872,-0.2735,-0.2452,-0.1944,-0.0968,0.0858",\ +"-0.3091,-0.2945,-0.2808,-0.2525,-0.2017,-0.1040,0.0786",\ +"-0.3392,-0.3245,-0.3109,-0.2826,-0.2318,-0.1341,0.0485",\ +"-0.3968,-0.3821,-0.3685,-0.3402,-0.2894,-0.1917,-0.0091"); + } + } + + + timing() { + timing_type : hold_rising; + related_pin : "B_BIST_CLK"; + when : "(B_BIST_WEN & B_BIST_MEN)" + sdf_cond : "B_BIST_RW_ACCESS" + + rise_constraint("SIG2SRAM_constraint_template") { + index_1("0.0056,0.0232,0.0400,0.0728,0.1280,0.2440,0.4760"); + index_2("0.0056,0.0232,0.0400,0.0728,0.1280,0.2440,0.4760"); + values ("0.4304,0.4138,0.4011,0.3689,0.3210,0.2175,0.0251",\ +"0.4354,0.4188,0.4061,0.3739,0.3260,0.2225,0.0301",\ +"0.4399,0.4233,0.4106,0.3784,0.3305,0.2270,0.0346",\ +"0.4490,0.4324,0.4197,0.3875,0.3396,0.2361,0.0437",\ +"0.4563,0.4397,0.4270,0.3947,0.3469,0.2434,0.0510",\ +"0.4863,0.4697,0.4570,0.4248,0.3770,0.2734,0.0811",\ +"0.5440,0.5273,0.5147,0.4824,0.4346,0.3311,0.1387"); + } + + fall_constraint("SIG2SRAM_constraint_template") { + index_1("0.0056,0.0232,0.0400,0.0728,0.1280,0.2440,0.4760"); + index_2("0.0056,0.0232,0.0400,0.0728,0.1280,0.2440,0.4760"); + values ("0.3845,0.3699,0.3562,0.3279,0.2781,0.1853,0.0007",\ +"0.3895,0.3749,0.3612,0.3329,0.2831,0.1903,0.0057",\ +"0.3940,0.3793,0.3657,0.3374,0.2875,0.1948,0.0102",\ +"0.4031,0.3884,0.3748,0.3465,0.2966,0.2039,0.0193",\ +"0.4104,0.3957,0.3820,0.3537,0.3039,0.2111,0.0266",\ +"0.4404,0.4258,0.4121,0.3838,0.3340,0.2412,0.0567",\ +"0.4980,0.4834,0.4697,0.4414,0.3916,0.2988,0.1143"); + } + } +} + pin(B_BIST_CLK) { + direction : input; + capacitance : 0.00380014; + max_transition : "0.476"; + clock : "true" ; + pin_func_type : active_rising ; + + timing () { + timing_type : "min_pulse_width"; + related_pin : "B_BIST_CLK"; + rise_constraint("CLKTRAN_constraint_template") { + index_1("0.0056,0.476"); + values("0.21,0.21"); + } + } + + related_power_pin : VDD; + related_ground_pin : VSS; + + internal_power() { + when : "!B_BIST_MEN & !B_BIST_WEN & !B_BIST_REN"; + rise_power("scalar"){ + values (0); + } + fall_power("scalar"){ + values (0); + } + } + internal_power() { + when : "!B_BIST_MEN & B_BIST_WEN & !B_BIST_REN"; + rise_power("scalar"){ + values (0.5278); + } + fall_power("scalar"){ + values (0); + } + } + internal_power() { + when : "B_BIST_MEN & B_BIST_WEN & !B_BIST_REN"; + rise_power("scalar"){ + values (14.0418); + } + fall_power("scalar"){ + values (0); + } + } + internal_power() { + when : "B_BIST_MEN & B_BIST_WEN & B_BIST_REN"; + rise_power("scalar"){ + values (14.7504); + } + fall_power("scalar"){ + values (0); + } + } + internal_power() { + when : "B_BIST_MEN & !B_BIST_WEN & B_BIST_REN"; + rise_power("scalar"){ + values (11.3447); + } + fall_power("scalar"){ + values (0); + } + } + internal_power() { + when : "!B_BIST_MEN & !B_BIST_WEN & B_BIST_REN"; + rise_power("scalar"){ + values (0.3000); + } + fall_power("scalar"){ + values (0); + } + } + internal_power() { + when : "!B_BIST_MEN & B_BIST_WEN & B_BIST_REN"; + rise_power("scalar"){ + values (0.5369); + } + fall_power("scalar"){ + values (0); + } + } + internal_power() { + when : "B_BIST_MEN & !B_BIST_WEN & !B_BIST_REN"; + rise_power("scalar"){ + values (0); + } + fall_power("scalar"){ + values (0); + } + } + } + bus(B_BIST_DIN) { + bus_type : D_7_0; + direction : input ; + capacitance : 0.00414348 ; + memory_write() { + address : B_BIST_ADDR ; + clocked_on : B_BIST_CLK; + } + + max_transition : "0.476" ; + pin(B_BIST_DIN[7:0]) { + related_power_pin : VDD; + related_ground_pin : VSS; + internal_power() { + when : "B_BIST_MEN"; + rise_power("scalar"){ + values (0.0288); + } + fall_power("scalar"){ + values (0.0126); + } + } + internal_power() { + when : "!B_BIST_MEN"; + rise_power("scalar"){ + values (0.0317); + } + fall_power("scalar"){ + values (0.0122); + } + } + } + timing() { + timing_type : setup_rising; + related_pin : "B_BIST_CLK"; + when : "(B_BIST_WEN & B_BIST_MEN)"; + sdf_cond : "B_BIST_W_ACCESS"; + + rise_constraint("SIG2SRAM_constraint_template") { + index_1("0.0056,0.0232,0.0400,0.0728,0.1280,0.2440,0.4760"); + index_2("0.0056,0.0232,0.0400,0.0728,0.1280,0.2440,0.4760"); + values ("-0.3214,-0.3057,-0.2921,-0.2598,-0.2130,-0.1085,0.0829",\ +"-0.3264,-0.3107,-0.2971,-0.2648,-0.2180,-0.1135,0.0779",\ +"-0.3308,-0.3152,-0.3015,-0.2693,-0.2224,-0.1179,0.0735",\ +"-0.3399,-0.3243,-0.3106,-0.2784,-0.2315,-0.1270,0.0644",\ +"-0.3472,-0.3316,-0.3179,-0.2857,-0.2388,-0.1343,0.0571",\ +"-0.3773,-0.3617,-0.3480,-0.3158,-0.2689,-0.1644,0.0270",\ +"-0.4349,-0.4193,-0.4056,-0.3734,-0.3265,-0.2220,-0.0306"); + } + + fall_constraint("SIG2SRAM_constraint_template") { + index_1("0.0056,0.0232,0.0400,0.0728,0.1280,0.2440,0.4760"); + index_2("0.0056,0.0232,0.0400,0.0728,0.1280,0.2440,0.4760"); + values ("-0.2833,-0.2686,-0.2550,-0.2266,-0.1759,-0.0782,0.1044",\ +"-0.2883,-0.2736,-0.2600,-0.2316,-0.1809,-0.0832,0.0994",\ +"-0.2927,-0.2781,-0.2644,-0.2361,-0.1853,-0.0877,0.0949",\ +"-0.3018,-0.2872,-0.2735,-0.2452,-0.1944,-0.0968,0.0858",\ +"-0.3091,-0.2945,-0.2808,-0.2525,-0.2017,-0.1040,0.0786",\ +"-0.3392,-0.3245,-0.3109,-0.2826,-0.2318,-0.1341,0.0485",\ +"-0.3968,-0.3821,-0.3685,-0.3402,-0.2894,-0.1917,-0.0091"); + } + } + + timing() { + timing_type : hold_rising; + related_pin : "B_BIST_CLK"; + when : "(B_BIST_WEN & B_BIST_MEN)"; + sdf_cond : "B_BIST_W_ACCESS"; + + rise_constraint("SIG2SRAM_constraint_template") { + index_1("0.0056,0.0232,0.0400,0.0728,0.1280,0.2440,0.4760"); + index_2("0.0056,0.0232,0.0400,0.0728,0.1280,0.2440,0.4760"); + values ("0.4304,0.4138,0.4011,0.3689,0.3210,0.2175,0.0251",\ +"0.4354,0.4188,0.4061,0.3739,0.3260,0.2225,0.0301",\ +"0.4399,0.4233,0.4106,0.3784,0.3305,0.2270,0.0346",\ +"0.4490,0.4324,0.4197,0.3875,0.3396,0.2361,0.0437",\ +"0.4563,0.4397,0.4270,0.3947,0.3469,0.2434,0.0510",\ +"0.4863,0.4697,0.4570,0.4248,0.3770,0.2734,0.0811",\ +"0.5440,0.5273,0.5147,0.4824,0.4346,0.3311,0.1387"); + } + + fall_constraint("SIG2SRAM_constraint_template") { + index_1("0.0056,0.0232,0.0400,0.0728,0.1280,0.2440,0.4760"); + index_2("0.0056,0.0232,0.0400,0.0728,0.1280,0.2440,0.4760"); + values ("0.3845,0.3699,0.3562,0.3279,0.2781,0.1853,0.0007",\ +"0.3895,0.3749,0.3612,0.3329,0.2831,0.1903,0.0057",\ +"0.3940,0.3793,0.3657,0.3374,0.2875,0.1948,0.0102",\ +"0.4031,0.3884,0.3748,0.3465,0.2966,0.2039,0.0193",\ +"0.4104,0.3957,0.3820,0.3537,0.3039,0.2111,0.0266",\ +"0.4404,0.4258,0.4121,0.3838,0.3340,0.2412,0.0567",\ +"0.4980,0.4834,0.4697,0.4414,0.3916,0.2988,0.1143"); + } + } + } + +bus(B_DOUT) { + + bus_type : D_7_0; + direction : output ; + capacitance : 0 ; + max_capacitance : 0.064 ; + memory_read() { + address : B_ADDR ; + } + pin(B_DOUT[7:0]) { + related_power_pin : VDD; + related_ground_pin : VSS; + internal_power() { + rise_power("scalar") { + values (0); + } + fall_power("scalar") { + values (0); + } + } + } + timing() { + related_pin : "B_CLK"; + timing_type : rising_edge ; + timing_sense : non_unate ; + + cell_rise(SIG2SRAM_delay_template) { + index_1("0.0056,0.0232,0.0400,0.0728,0.1280,0.2440,0.4760"); + index_2("0.0008,0.0014,0.0051,0.0100,0.0339,0.0640"); + values ("3.7348,3.7365,3.7441,3.7528,3.7852,3.8213",\ +"3.7400,3.7416,3.7492,3.7580,3.7904,3.8265",\ +"3.7432,3.7448,3.7524,3.7612,3.7935,3.8297",\ +"3.7557,3.7573,3.7649,3.7736,3.8060,3.8422",\ +"3.7615,3.7631,3.7707,3.7795,3.8118,3.8480",\ +"3.7925,3.7941,3.8017,3.8104,3.8428,3.8790",\ +"3.8482,3.8498,3.8574,3.8661,3.8985,3.9347"); + } + cell_fall(SIG2SRAM_delay_template) { + index_1("0.0056,0.0232,0.0400,0.0728,0.1280,0.2440,0.4760"); + index_2("0.0008,0.0014,0.0051,0.0100,0.0339,0.0640"); + values ("3.6746,3.6759,3.6820,3.6891,3.7156,3.7418",\ +"3.6797,3.6811,3.6871,3.6943,3.7208,3.7470",\ +"3.6829,3.6842,3.6903,3.6975,3.7240,3.7502",\ +"3.6954,3.6967,3.7028,3.7099,3.7364,3.7627",\ +"3.7012,3.7025,3.7086,3.7158,3.7423,3.7685",\ +"3.7322,3.7335,3.7396,3.7467,3.7732,3.7995",\ +"3.7879,3.7892,3.7953,3.8024,3.8289,3.8552"); + } + + rise_transition(SRAM_load_template) { + index_1("0.0008,0.0014,0.0051,0.0100,0.0339,0.0640"); + values ("0.0326,0.0341,0.0428,0.0518,0.0923,0.1492"); + } + fall_transition(SRAM_load_template) { + index_1("0.0008,0.0014,0.0051,0.0100,0.0339,0.0640"); + values ("0.0254,0.0265,0.0335,0.0402,0.0707,0.1039"); + } + } +} +cell_leakage_power : 79.7252; +} +} diff --git a/flow/platforms/ihp-sg13g2/lib/RM_IHPSG13_2P_64x32_c2_fast_1p32V_m55C.lib b/flow/platforms/ihp-sg13g2/lib/RM_IHPSG13_2P_64x32_c2_fast_1p32V_m55C.lib new file mode 100644 index 0000000000..0f8b78ef72 --- /dev/null +++ b/flow/platforms/ihp-sg13g2/lib/RM_IHPSG13_2P_64x32_c2_fast_1p32V_m55C.lib @@ -0,0 +1,1380 @@ +/* ------------------------------------------------------*/ +/**/ +/* Copyright 2023 IHP PDK Authors*/ +/**/ +/* Licensed under the Apache License, Version 2.0 (the "License");*/ +/* you may not use this file except in compliance with the License.*/ +/* You may obtain a copy of the License at*/ +/* */ +/* https://www.apache.org/licenses/LICENSE-2.0*/ +/* */ +/* Unless required by applicable law or agreed to in writing, software*/ +/* distributed under the License is distributed on an "AS IS" BASIS,*/ +/* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.*/ +/* See the License for the specific language governing permissions and*/ +/* limitations under the License.*/ +/* */ +/* Generated on Thu Jun 12 11:08:43 2025 */ +/* */ +/* ------------------------------------------------------ */ +library(RM_IHPSG13_2P_64x32_c2_fast_1p32V_m55C) { + technology (cmos) ; + delay_model : table_lookup ; + define ("add_pg_pin_to_lib", "library", "boolean"); + add_pg_pin_to_lib : true; + voltage_map ( VDD, 1.32); + voltage_map ( VDDARRAY, 1.32); + voltage_map ( VSS, 0.000000 ); + + date : "Thu Jun 12 11:08:38 2025" ; + comment : "IHP Microelectronics GmbH, 2023" ; + revision : 1.0.0 ; + simulation : true ; + nom_process : 1 ; + nom_temperature : -55 ; + nom_voltage : 1.32 ; + + operating_conditions("fast_1p32V_m55C"){ + process : 1 ; + temperature : -55 ; + voltage : 1.32 ; + tree_type : "balanced_tree" ; + } + + default_operating_conditions : fast_1p32V_m55C ; + default_max_transition : 1.0 ; + default_fanout_load : 1.0 ; + default_inout_pin_cap : 0.0 ; + default_input_pin_cap : 0.0 ; + default_output_pin_cap : 0.0 ; + default_cell_leakage_power : 0.0 ; + default_leakage_power_density : 0.0 ; + + slew_lower_threshold_pct_rise : 30 ; + slew_upper_threshold_pct_rise : 70 ; + input_threshold_pct_fall : 50 ; + output_threshold_pct_fall : 50 ; + input_threshold_pct_rise : 50 ; + output_threshold_pct_rise : 50 ; + slew_lower_threshold_pct_fall : 30 ; + slew_upper_threshold_pct_fall : 70 ; + slew_derate_from_library : 0.5; + k_volt_cell_leakage_power : 0.0 ; + k_temp_cell_leakage_power : 0.0 ; + k_process_cell_leakage_power : 0.0 ; + k_volt_internal_power : 0.0 ; + k_temp_internal_power : 0.0 ; + k_process_internal_power : 0.0 ; + + capacitive_load_unit (1,pf) ; + voltage_unit : "1V" ; + current_unit : "1uA" ; + time_unit : "1ns" ; + leakage_power_unit : "1nW" ; + pulling_resistance_unit : "1kohm"; + /* + ------------------------------------------------------------------------------------------ + implicit units overview: + cell_area unit : "um" + internal_power unit : "1e-12 * J/toggle = 1 * uW/MHz" + (capacitive_load_unit * voltage_unit^2) per toggle event + ------------------------------------------------------------------------------------------ + */ + library_features(report_delay_calculation); + define_cell_area (pad_drivers,pad_driver_sites) ; + + lu_table_template(CLKTRAN_constraint_template) { + variable_1 : constrained_pin_transition; + index_1 ( "0.010, 0.050, 0.200, 0.400, 1.000" ); + } + lu_table_template(SRAM_load_template) { + variable_1 : total_output_net_capacitance; + index_1 ( "0.0008,0.0014,0.0051,0.0100,0.0339,0.0640" ); + } + lu_table_template(SIG2SRAM_constraint_template) { + variable_1 : related_pin_transition; + variable_2 : constrained_pin_transition; + index_1 ( "0.0040,0.0176,0.0344,0.0656,0.1120,0.2016,0.3800" ); + index_2 ( "0.0040,0.0176,0.0344,0.0656,0.1120,0.2016,0.3800" ); + } + + lu_table_template(SIG2SRAM_delay_template) { + variable_1 : input_net_transition; + variable_2 : total_output_net_capacitance; + index_1 ( "0.0040,0.0176,0.0344,0.0656,0.1120,0.2016,0.3800" ); + index_2 ( "0.0008,0.0014,0.0051,0.0100,0.0339,0.0640" ); + } + + type (D_31_0) { + base_type : array; + data_type : bit; + bit_width : 32; + bit_from : 31; + bit_to : 0; + downto : true; + } + + type (A_5_0) { + base_type : array; + data_type : bit; + bit_width : 6; + bit_from : 5; + bit_to : 0; + downto : true; + } + +cell(RM_IHPSG13_2P_64x32_c2) { +pg_pin (VDD) { + pg_type : primary_power; + voltage_name : VDD; +} +pg_pin (VDDARRAY) { + pg_type : primary_power; + voltage_name : VDDARRAY; +} +pg_pin (VSS) { + pg_type : primary_ground; + voltage_name : VSS; +} + +memory() { + type : ram; + address_width : 6; + word_width : 32; +} + +interface_timing : false; +bus_naming_style : "%s[%d]" ; +area : 52620.8821 ; + + pin(A_DLY) { + direction : input ; + capacitance : 0.00421562 ; + max_transition : "1" ; + related_power_pin : VDD; + related_ground_pin : VSS; + internal_power() { + rise_power("scalar") { + values (0); + } + fall_power("scalar") { + values (0); + } + } + } + +bus(A_ADDR) { + bus_type : A_5_0; + direction : input ; + capacitance : 0.0115194 ; + pin(A_ADDR[0]) { + capacitance : 0.00563454 ; + } + pin(A_ADDR[1]) { + capacitance : 0.00744185 ; + } + pin(A_ADDR[2]) { + capacitance : 0.0100611 ; + } + pin(A_ADDR[3]) { + capacitance : 0.00669965 ; + } + pin(A_ADDR[4]) { + capacitance : 0.00614331 ; + } + max_transition : "0.38" ; + pin(A_ADDR[5:0]) { + related_power_pin : VDD; + related_ground_pin : VSS; + internal_power() { + when : "A_MEN"; + rise_power("scalar"){ + values (0.0146); + } + fall_power("scalar"){ + values (0.0002); + } + } + internal_power() { + when : "!A_MEN"; + rise_power("scalar"){ + values (0.0300); + } + fall_power("scalar"){ + values (0.0015); + } + } + } + timing() { + timing_type : setup_rising; + related_pin : "A_CLK"; + when : "((A_WEN | A_REN)& A_MEN)" + sdf_cond : "A_RW_ACCESS" + + rise_constraint("SIG2SRAM_constraint_template") { + index_1("0.0040,0.0176,0.0344,0.0656,0.1120,0.2016,0.3800"); + index_2("0.0040,0.0176,0.0344,0.0656,0.1120,0.2016,0.3800"); + values ("-0.2371,-0.2215,-0.2098,-0.1824,-0.1434,-0.0691,0.0676",\ +"-0.2449,-0.2332,-0.2176,-0.1902,-0.1551,-0.0770,0.0559",\ +"-0.2605,-0.2488,-0.2332,-0.2059,-0.1707,-0.0965,0.0441",\ +"-0.2879,-0.2723,-0.2605,-0.2332,-0.1941,-0.1199,0.0168",\ +"-0.3230,-0.3113,-0.2996,-0.2723,-0.2332,-0.1590,-0.0184",\ +"-0.4012,-0.3895,-0.3738,-0.3465,-0.3074,-0.2332,-0.0965",\ +"-0.5379,-0.5262,-0.5105,-0.4832,-0.4480,-0.3699,-0.2332"); + } + + fall_constraint("SIG2SRAM_constraint_template") { + index_1("0.0040,0.0176,0.0344,0.0656,0.1120,0.2016,0.3800"); + index_2("0.0040,0.0176,0.0344,0.0656,0.1120,0.2016,0.3800"); + values ("-0.1785,-0.1707,-0.1551,-0.1277,-0.0887,-0.0184,0.1145",\ +"-0.1902,-0.1785,-0.1629,-0.1355,-0.1004,-0.0262,0.1027",\ +"-0.2059,-0.1941,-0.1785,-0.1512,-0.1160,-0.0418,0.0871",\ +"-0.2293,-0.2176,-0.2059,-0.1785,-0.1434,-0.0691,0.0598",\ +"-0.2684,-0.2566,-0.2449,-0.2176,-0.1824,-0.1082,0.0207",\ +"-0.3465,-0.3348,-0.3191,-0.2918,-0.2566,-0.1824,-0.0535",\ +"-0.4832,-0.4715,-0.4559,-0.4324,-0.3934,-0.3191,-0.1902"); + } + } + + + timing() { + timing_type : hold_rising; + related_pin : "A_CLK"; + when : "((A_WEN | A_REN)& A_MEN)" + sdf_cond : "A_RW_ACCESS" + + rise_constraint("SIG2SRAM_constraint_template") { + index_1("0.0040,0.0176,0.0344,0.0656,0.1120,0.2016,0.3800"); + index_2("0.0040,0.0176,0.0344,0.0656,0.1120,0.2016,0.3800"); + values ("0.3410,0.3293,0.3137,0.2863,0.2473,0.1730,0.0324",\ +"0.3488,0.3371,0.3215,0.2941,0.2590,0.1809,0.0480",\ +"0.3684,0.3527,0.3371,0.3098,0.2746,0.1965,0.0598",\ +"0.3918,0.3762,0.3645,0.3371,0.2980,0.2238,0.0871",\ +"0.4309,0.4152,0.4035,0.3762,0.3371,0.2629,0.1223",\ +"0.5051,0.4934,0.4777,0.4504,0.4113,0.3371,0.1965",\ +"0.6418,0.6262,0.6145,0.5871,0.5520,0.4738,0.3332"); + } + + fall_constraint("SIG2SRAM_constraint_template") { + index_1("0.0040,0.0176,0.0344,0.0656,0.1120,0.2016,0.3800"); + index_2("0.0040,0.0176,0.0344,0.0656,0.1120,0.2016,0.3800"); + values ("0.2824,0.2707,0.2551,0.2277,0.1926,0.1184,-0.0105",\ +"0.2902,0.2785,0.2668,0.2395,0.2043,0.1301,0.0012",\ +"0.3059,0.2941,0.2824,0.2551,0.2199,0.1457,0.0168",\ +"0.3332,0.3215,0.3059,0.2785,0.2434,0.1691,0.0402",\ +"0.3723,0.3605,0.3449,0.3176,0.2824,0.2121,0.0793",\ +"0.4465,0.4348,0.4230,0.3918,0.3566,0.2824,0.1535",\ +"0.5832,0.5715,0.5598,0.5324,0.4934,0.4191,0.2902"); + } + } +} +pin(A_WEN) { + direction : input ; + capacitance : 0.00341384 ; + max_transition : "0.38" ; + related_power_pin : VDD; + related_ground_pin : VSS; + internal_power() { + when : "A_MEN"; + rise_power("scalar"){ + values (0.0085); + } + fall_power("scalar"){ + values (0.0099); + } + } + internal_power() { + when : "!A_MEN"; + rise_power("scalar"){ + values (0.0074); + } + fall_power("scalar"){ + values (0.0341); + } + } + timing() { + timing_type : setup_rising; + related_pin : "A_CLK"; + when : "A_MEN" + sdf_cond : "A_MEN" + + rise_constraint("SIG2SRAM_constraint_template") { + index_1("0.0040,0.0176,0.0344,0.0656,0.1120,0.2016,0.3800"); + index_2("0.0040,0.0176,0.0344,0.0656,0.1120,0.2016,0.3800"); + values ("0.1418,0.1496,0.1652,0.1887,0.2316,0.3059,0.4465",\ +"0.1301,0.1379,0.1535,0.1809,0.2199,0.2941,0.4348",\ +"0.1145,0.1262,0.1379,0.1652,0.2043,0.2785,0.4191",\ +"0.0871,0.0949,0.1105,0.1379,0.1770,0.2512,0.3879",\ +"0.0480,0.0598,0.0754,0.0988,0.1379,0.2082,0.3527",\ +"-0.0262,-0.0145,0.0012,0.0246,0.0676,0.1379,0.2785",\ +"-0.1668,-0.1551,-0.1395,-0.1121,-0.0730,0.0012,0.1418"); + } + + fall_constraint("SIG2SRAM_constraint_template") { + index_1("0.0040,0.0176,0.0344,0.0656,0.1120,0.2016,0.3800"); + index_2("0.0040,0.0176,0.0344,0.0656,0.1120,0.2016,0.3800"); + values ("0.2082,0.2160,0.2316,0.2590,0.2941,0.3684,0.5012",\ +"0.1926,0.2043,0.2199,0.2473,0.2824,0.3566,0.4895",\ +"0.1770,0.1887,0.2043,0.2316,0.2668,0.3410,0.4777",\ +"0.1535,0.1652,0.1770,0.2043,0.2395,0.3137,0.4504",\ +"0.1145,0.1262,0.1379,0.1652,0.2043,0.2746,0.4113",\ +"0.0402,0.0520,0.0676,0.0910,0.1262,0.2004,0.3332",\ +"-0.0965,-0.0848,-0.0730,-0.0457,-0.0066,0.0637,0.2004"); + } + } + + + timing() { + timing_type : hold_rising; + related_pin : "A_CLK"; + when : "A_MEN" + sdf_cond : "A_MEN" + + rise_constraint("SIG2SRAM_constraint_template") { + index_1("0.0040,0.0176,0.0344,0.0656,0.1120,0.2016,0.3800"); + index_2("0.0040,0.0176,0.0344,0.0656,0.1120,0.2016,0.3800"); + values ("0.1770,0.1652,0.1496,0.1223,0.0793,0.0090,-0.1316",\ +"0.1848,0.1730,0.1574,0.1301,0.0910,0.0168,-0.1199",\ +"0.2004,0.1887,0.1770,0.1496,0.1066,0.0363,-0.1043",\ +"0.2277,0.2160,0.2004,0.1730,0.1340,0.0598,-0.0809",\ +"0.2668,0.2551,0.2395,0.2121,0.1730,0.0988,-0.0418",\ +"0.3410,0.3293,0.3137,0.2863,0.2434,0.1730,0.0324",\ +"0.4816,0.4699,0.4543,0.4230,0.3801,0.3098,0.1730"); + } + + fall_constraint("SIG2SRAM_constraint_template") { + index_1("0.0040,0.0176,0.0344,0.0656,0.1120,0.2016,0.3800"); + index_2("0.0040,0.0176,0.0344,0.0656,0.1120,0.2016,0.3800"); + values ("0.1613,0.1496,0.1379,0.1066,0.0715,0.0012,-0.1355",\ +"0.1730,0.1613,0.1457,0.1184,0.0832,0.0129,-0.1238",\ +"0.1887,0.1770,0.1613,0.1340,0.0988,0.0246,-0.1121",\ +"0.2121,0.2043,0.1887,0.1613,0.1223,0.0520,-0.0848",\ +"0.2512,0.2434,0.2277,0.2004,0.1613,0.0910,-0.0457",\ +"0.3254,0.3176,0.3020,0.2746,0.2355,0.1652,0.0324",\ +"0.4660,0.4543,0.4387,0.4113,0.3723,0.3020,0.1691"); + } + } + } +pin(A_REN) { + direction : input ; + capacitance : 0.00390661 ; + max_transition : "0.38" ; + related_power_pin : VDD; + related_ground_pin : VSS; + internal_power() { + when : "A_MEN"; + rise_power("scalar"){ + values (0.0111); + } + fall_power("scalar"){ + values (0.0100); + } + } + internal_power() { + when : "!A_MEN"; + rise_power("scalar"){ + values (0.0258); + } + fall_power("scalar"){ + values (0.0198); + } + } + timing() { + timing_type : setup_rising; + related_pin : "A_CLK"; + when : "A_MEN" + sdf_cond : "A_MEN" + + rise_constraint("SIG2SRAM_constraint_template") { + index_1("0.0040,0.0176,0.0344,0.0656,0.1120,0.2016,0.3800"); + index_2("0.0040,0.0176,0.0344,0.0656,0.1120,0.2016,0.3800"); + values ("-0.0027,0.0090,0.0246,0.0520,0.0910,0.1613,0.3020",\ +"-0.0105,0.0012,0.0129,0.0363,0.0793,0.1535,0.2902",\ +"-0.0262,-0.0145,-0.0027,0.0246,0.0637,0.1379,0.2785",\ +"-0.0535,-0.0418,-0.0262,0.0012,0.0363,0.1105,0.2512",\ +"-0.0926,-0.0809,-0.0652,-0.0418,-0.0027,0.0715,0.2121",\ +"-0.1668,-0.1551,-0.1395,-0.1082,-0.0770,-0.0027,0.1379",\ +"-0.3035,-0.2918,-0.2762,-0.2488,-0.2137,-0.1434,-0.0027"); + } + + fall_constraint("SIG2SRAM_constraint_template") { + index_1("0.0040,0.0176,0.0344,0.0656,0.1120,0.2016,0.3800"); + index_2("0.0040,0.0176,0.0344,0.0656,0.1120,0.2016,0.3800"); + values ("0.0832,0.0949,0.1105,0.1379,0.1730,0.2473,0.3801",\ +"0.0754,0.0832,0.0988,0.1223,0.1613,0.2355,0.3684",\ +"0.0598,0.0676,0.0832,0.1066,0.1457,0.2121,0.3527",\ +"0.0324,0.0441,0.0598,0.0871,0.1223,0.1926,0.3293",\ +"-0.0066,0.0051,0.0168,0.0480,0.0832,0.1535,0.2902",\ +"-0.0809,-0.0691,-0.0574,-0.0301,0.0090,0.0832,0.2121",\ +"-0.2176,-0.2059,-0.1941,-0.1668,-0.1277,-0.0574,0.0793"); + } + } + + + timing() { + timing_type : hold_rising; + related_pin : "A_CLK"; + when : "A_MEN" + sdf_cond : "A_MEN" + + rise_constraint("SIG2SRAM_constraint_template") { + index_1("0.0040,0.0176,0.0344,0.0656,0.1120,0.2016,0.3800"); + index_2("0.0040,0.0176,0.0344,0.0656,0.1120,0.2016,0.3800"); + values ("0.1887,0.1770,0.1613,0.1340,0.0949,0.0207,-0.1160",\ +"0.1965,0.1848,0.1730,0.1457,0.1027,0.0324,-0.1082",\ +"0.2160,0.2004,0.1887,0.1613,0.1184,0.0480,-0.0926",\ +"0.2395,0.2277,0.2121,0.1848,0.1457,0.0715,-0.0652",\ +"0.2785,0.2668,0.2512,0.2238,0.1848,0.1105,-0.0262",\ +"0.3527,0.3410,0.3254,0.2980,0.2551,0.1848,0.0480",\ +"0.4934,0.4816,0.4660,0.4387,0.3957,0.3254,0.1887"); + } + + fall_constraint("SIG2SRAM_constraint_template") { + index_1("0.0040,0.0176,0.0344,0.0656,0.1120,0.2016,0.3800"); + index_2("0.0040,0.0176,0.0344,0.0656,0.1120,0.2016,0.3800"); + values ("0.1730,0.1613,0.1496,0.1184,0.0793,0.0129,-0.1238",\ +"0.1848,0.1730,0.1574,0.1301,0.0910,0.0207,-0.1121",\ +"0.2004,0.1887,0.1730,0.1457,0.1066,0.0363,-0.1004",\ +"0.2238,0.2121,0.2004,0.1691,0.1340,0.0598,-0.0730",\ +"0.2629,0.2512,0.2395,0.2121,0.1691,0.0988,-0.0340",\ +"0.3371,0.3254,0.3137,0.2863,0.2434,0.1730,0.0402",\ +"0.4777,0.4660,0.4504,0.4230,0.3840,0.3137,0.1809"); + } + } + } +pin(A_MEN) { + direction : input ; + capacitance : 0.00326046 ; + max_transition : "0.38" ; + related_power_pin : VDD; + related_ground_pin : VSS; + internal_power() { + rise_power("scalar"){ + values (0.3396); + } + fall_power("scalar"){ + values (0.0093); + } + } + timing() { + timing_type : setup_rising; + related_pin : "A_CLK"; + + rise_constraint("SIG2SRAM_constraint_template") { + index_1("0.0040,0.0176,0.0344,0.0656,0.1120,0.2016,0.3800"); + index_2("0.0040,0.0176,0.0344,0.0656,0.1120,0.2016,0.3800"); + values ("0.1418,0.1496,0.1652,0.1926,0.2316,0.3059,0.4465",\ +"0.1301,0.1379,0.1535,0.1809,0.2199,0.2941,0.4348",\ +"0.1145,0.1262,0.1418,0.1652,0.2043,0.2785,0.4191",\ +"0.0871,0.0949,0.1105,0.1379,0.1770,0.2512,0.3879",\ +"0.0480,0.0598,0.0754,0.0988,0.1379,0.2082,0.3488",\ +"-0.0262,-0.0145,0.0012,0.0285,0.0676,0.1379,0.2785",\ +"-0.1668,-0.1551,-0.1395,-0.1121,-0.0730,0.0012,0.1379"); + } + + fall_constraint("SIG2SRAM_constraint_template") { + index_1("0.0040,0.0176,0.0344,0.0656,0.1120,0.2016,0.3800"); + index_2("0.0040,0.0176,0.0344,0.0656,0.1120,0.2016,0.3800"); + values ("0.2082,0.2199,0.2316,0.2590,0.2980,0.3723,0.5051",\ +"0.1965,0.2082,0.2199,0.2473,0.2863,0.3605,0.4934",\ +"0.1809,0.1926,0.2043,0.2316,0.2707,0.3449,0.4777",\ +"0.1574,0.1691,0.1809,0.2082,0.2434,0.3176,0.4543",\ +"0.1145,0.1262,0.1418,0.1691,0.2043,0.2785,0.4113",\ +"0.0441,0.0559,0.0676,0.0949,0.1301,0.2004,0.3332",\ +"-0.0965,-0.0848,-0.0691,-0.0418,-0.0066,0.0676,0.2004"); + } + } + + + timing() { + timing_type : hold_rising; + related_pin : "A_CLK"; + + rise_constraint("SIG2SRAM_constraint_template") { + index_1("0.0040,0.0176,0.0344,0.0656,0.1120,0.2016,0.3800"); + index_2("0.0040,0.0176,0.0344,0.0656,0.1120,0.2016,0.3800"); + values ("0.1770,0.1652,0.1535,0.1262,0.0832,0.0129,-0.1277",\ +"0.1887,0.1770,0.1613,0.1340,0.0949,0.0207,-0.1199",\ +"0.2043,0.1926,0.1770,0.1496,0.1105,0.0363,-0.1043",\ +"0.2277,0.2160,0.2043,0.1770,0.1379,0.0598,-0.0770",\ +"0.2668,0.2551,0.2434,0.2160,0.1730,0.0988,-0.0379",\ +"0.3449,0.3332,0.3176,0.2902,0.2473,0.1730,0.0363",\ +"0.4816,0.4699,0.4543,0.4270,0.3840,0.3098,0.1770"); + } + + fall_constraint("SIG2SRAM_constraint_template") { + index_1("0.0040,0.0176,0.0344,0.0656,0.1120,0.2016,0.3800"); + index_2("0.0040,0.0176,0.0344,0.0656,0.1120,0.2016,0.3800"); + values ("0.1613,0.1496,0.1379,0.1105,0.0715,0.0012,-0.1355",\ +"0.1730,0.1613,0.1496,0.1184,0.0832,0.0129,-0.1238",\ +"0.1887,0.1770,0.1652,0.1340,0.0988,0.0285,-0.1121",\ +"0.2121,0.2043,0.1887,0.1613,0.1223,0.0520,-0.0848",\ +"0.2551,0.2434,0.2277,0.2004,0.1613,0.0910,-0.0418",\ +"0.3293,0.3176,0.3020,0.2746,0.2395,0.1652,0.0324",\ +"0.4660,0.4543,0.4426,0.4113,0.3762,0.3020,0.1691"); + } + } + } + pin(A_CLK) { + direction : input; + capacitance : 0.00389386; + max_transition : "0.38"; + clock : "true" ; + pin_func_type : active_rising ; + + timing () { + timing_type : "min_pulse_width"; + related_pin : "A_CLK"; + rise_constraint("CLKTRAN_constraint_template") { + index_1("0.004,0.38"); + values("0.12,0.12"); + } + } + + related_power_pin : VDD; + related_ground_pin : VSS; + + internal_power() { + when : "!A_MEN & !A_WEN & !A_REN"; + rise_power("scalar"){ + values (0); + } + fall_power("scalar"){ + values (0); + } + } + internal_power() { + when : "!A_MEN & A_WEN & !A_REN"; + rise_power("scalar"){ + values (0.6237); + } + fall_power("scalar"){ + values (0); + } + } + internal_power() { + when : "A_MEN & A_WEN & !A_REN"; + rise_power("scalar"){ + values (33.3694); + } + fall_power("scalar"){ + values (0); + } + } + internal_power() { + when : "A_MEN & A_WEN & A_REN"; + rise_power("scalar"){ + values (37.6442); + } + fall_power("scalar"){ + values (0); + } + } + internal_power() { + when : "A_MEN & !A_WEN & A_REN"; + rise_power("scalar"){ + values (24.7144); + } + fall_power("scalar"){ + values (0); + } + } + internal_power() { + when : "!A_MEN & !A_WEN & A_REN"; + rise_power("scalar"){ + values (0.4148); + } + fall_power("scalar"){ + values (0); + } + } + internal_power() { + when : "!A_MEN & A_WEN & A_REN"; + rise_power("scalar"){ + values (1.5212); + } + fall_power("scalar"){ + values (0); + } + } + internal_power() { + when : "A_MEN & !A_WEN & !A_REN"; + rise_power("scalar"){ + values (0); + } + fall_power("scalar"){ + values (0); + } + } + } + bus(A_DIN) { + bus_type : D_31_0; + direction : input ; + capacitance : 0.00505326 ; + memory_write() { + address : A_ADDR ; + clocked_on : A_CLK; + } + + max_transition : "0.38" ; + pin(A_DIN[31:0]) { + related_power_pin : VDD; + related_ground_pin : VSS; + internal_power() { + when : "A_MEN"; + rise_power("scalar"){ + values (0.1417); + } + fall_power("scalar"){ + values (0.1431); + } + } + internal_power() { + when : "!A_MEN"; + rise_power("scalar"){ + values (0.1750); + } + fall_power("scalar"){ + values (0.1518); + } + } + } + timing() { + timing_type : setup_rising; + related_pin : "A_CLK"; + when : "(A_WEN & A_MEN)"; + sdf_cond : "A_W_ACCESS"; + + rise_constraint("SIG2SRAM_constraint_template") { + index_1("0.0040,0.0176,0.0344,0.0656,0.1120,0.2016,0.3800"); + index_2("0.0040,0.0176,0.0344,0.0656,0.1120,0.2016,0.3800"); + values ("-0.2756,-0.2649,-0.2493,-0.2219,-0.1848,-0.1096,0.0222",\ +"-0.2795,-0.2688,-0.2531,-0.2258,-0.1887,-0.1135,0.0183",\ +"-0.2832,-0.2725,-0.2568,-0.2295,-0.1924,-0.1172,0.0147",\ +"-0.2864,-0.2757,-0.2600,-0.2327,-0.1956,-0.1204,0.0115",\ +"-0.2990,-0.2883,-0.2726,-0.2453,-0.2082,-0.1330,-0.0012",\ +"-0.3166,-0.3059,-0.2903,-0.2629,-0.2258,-0.1506,-0.0188",\ +"-0.3441,-0.3334,-0.3178,-0.2904,-0.2533,-0.1781,-0.0463"); + } + + fall_constraint("SIG2SRAM_constraint_template") { + index_1("0.0040,0.0176,0.0344,0.0656,0.1120,0.2016,0.3800"); + index_2("0.0040,0.0176,0.0344,0.0656,0.1120,0.2016,0.3800"); + values ("-0.2483,-0.2375,-0.2239,-0.1965,-0.1594,-0.0872,0.0408",\ +"-0.2522,-0.2414,-0.2278,-0.2004,-0.1633,-0.0910,0.0369",\ +"-0.2559,-0.2451,-0.2314,-0.2041,-0.1670,-0.0947,0.0332",\ +"-0.2590,-0.2483,-0.2346,-0.2073,-0.1702,-0.0979,0.0300",\ +"-0.2717,-0.2609,-0.2473,-0.2199,-0.1828,-0.1105,0.0174",\ +"-0.2893,-0.2785,-0.2649,-0.2375,-0.2004,-0.1282,-0.0002",\ +"-0.3168,-0.3060,-0.2924,-0.2650,-0.2279,-0.1557,-0.0277"); + } + } + + timing() { + timing_type : hold_rising; + related_pin : "A_CLK"; + when : "(A_WEN & A_MEN)"; + sdf_cond : "A_W_ACCESS"; + + rise_constraint("SIG2SRAM_constraint_template") { + index_1("0.0040,0.0176,0.0344,0.0656,0.1120,0.2016,0.3800"); + index_2("0.0040,0.0176,0.0344,0.0656,0.1120,0.2016,0.3800"); + values ("0.3804,0.3687,0.3550,0.3287,0.2896,0.2193,0.0835",\ +"0.3843,0.3726,0.3589,0.3325,0.2935,0.2232,0.0874",\ +"0.3880,0.3763,0.3626,0.3362,0.2972,0.2268,0.0911",\ +"0.3912,0.3795,0.3658,0.3394,0.3004,0.2300,0.0943",\ +"0.4038,0.3921,0.3784,0.3520,0.3130,0.2427,0.1069",\ +"0.4214,0.4097,0.3960,0.3696,0.3306,0.2603,0.1245",\ +"0.4489,0.4372,0.4235,0.3972,0.3581,0.2878,0.1520"); + } + + fall_constraint("SIG2SRAM_constraint_template") { + index_1("0.0040,0.0176,0.0344,0.0656,0.1120,0.2016,0.3800"); + index_2("0.0040,0.0176,0.0344,0.0656,0.1120,0.2016,0.3800"); + values ("0.3501,0.3384,0.3248,0.2984,0.2613,0.1890,0.0601",\ +"0.3540,0.3423,0.3286,0.3023,0.2652,0.1929,0.0640",\ +"0.3577,0.3460,0.3323,0.3059,0.2688,0.1966,0.0677",\ +"0.3609,0.3492,0.3355,0.3091,0.2720,0.1998,0.0709",\ +"0.3735,0.3618,0.3481,0.3218,0.2847,0.2124,0.0835",\ +"0.3911,0.3794,0.3657,0.3394,0.3023,0.2300,0.1011",\ +"0.4186,0.4069,0.3932,0.3669,0.3298,0.2575,0.1286"); + } + } + } + +bus(A_DOUT) { + + bus_type : D_31_0; + direction : output ; + capacitance : 0 ; + max_capacitance : 0.064 ; + memory_read() { + address : A_ADDR ; + } + pin(A_DOUT[31:0]) { + related_power_pin : VDD; + related_ground_pin : VSS; + internal_power() { + rise_power("scalar") { + values (0); + } + fall_power("scalar") { + values (0); + } + } + } + timing() { + related_pin : "A_CLK"; + timing_type : rising_edge ; + timing_sense : non_unate ; + + cell_rise(SIG2SRAM_delay_template) { + index_1("0.0040,0.0176,0.0344,0.0656,0.1120,0.2016,0.3800"); + index_2("0.0008,0.0014,0.0051,0.0100,0.0339,0.0640"); + values ("1.8924,1.8934,1.8985,1.9037,1.9246,1.9482",\ +"1.8983,1.8993,1.9044,1.9096,1.9305,1.9541",\ +"1.9011,1.9021,1.9072,1.9124,1.9333,1.9569",\ +"1.9053,1.9063,1.9114,1.9166,1.9375,1.9611",\ +"1.9169,1.9179,1.9230,1.9282,1.9491,1.9727",\ +"1.9360,1.9370,1.9421,1.9473,1.9682,1.9918",\ +"1.9624,1.9634,1.9685,1.9737,1.9946,2.0182"); + } + cell_fall(SIG2SRAM_delay_template) { + index_1("0.0040,0.0176,0.0344,0.0656,0.1120,0.2016,0.3800"); + index_2("0.0008,0.0014,0.0051,0.0100,0.0339,0.0640"); + values ("1.8583,1.8591,1.8631,1.8679,1.8851,1.9017",\ +"1.8642,1.8651,1.8691,1.8738,1.8910,1.9076",\ +"1.8670,1.8678,1.8718,1.8766,1.8938,1.9104",\ +"1.8712,1.8720,1.8760,1.8808,1.8980,1.9146",\ +"1.8828,1.8836,1.8876,1.8924,1.9096,1.9262",\ +"1.9019,1.9028,1.9068,1.9115,1.9287,1.9453",\ +"1.9283,1.9291,1.9331,1.9379,1.9551,1.9717"); + } + + rise_transition(SRAM_load_template) { + index_1("0.0008,0.0014,0.0051,0.0100,0.0339,0.0640"); + values ("0.0206,0.0210,0.0265,0.0323,0.0606,0.0955"); + } + fall_transition(SRAM_load_template) { + index_1("0.0008,0.0014,0.0051,0.0100,0.0339,0.0640"); + values ("0.0170,0.0177,0.0222,0.0270,0.0451,0.0644"); + } + } +} + pin(B_DLY) { + direction : input ; + capacitance : 0.00421562 ; + max_transition : "1" ; + related_power_pin : VDD; + related_ground_pin : VSS; + internal_power() { + rise_power("scalar") { + values (0); + } + fall_power("scalar") { + values (0); + } + } + } + +bus(B_ADDR) { + bus_type : A_5_0; + direction : input ; + capacitance : 0.0115194 ; + pin(B_ADDR[0]) { + capacitance : 0.0056487 ; + } + pin(B_ADDR[1]) { + capacitance : 0.00741688 ; + } + pin(B_ADDR[2]) { + capacitance : 0.0100613 ; + } + pin(B_ADDR[3]) { + capacitance : 0.00667339 ; + } + pin(B_ADDR[4]) { + capacitance : 0.00620204 ; + } + max_transition : "0.38" ; + pin(B_ADDR[5:0]) { + related_power_pin : VDD; + related_ground_pin : VSS; + internal_power() { + when : "B_MEN"; + rise_power("scalar"){ + values (0.0146); + } + fall_power("scalar"){ + values (0.0002); + } + } + internal_power() { + when : "!B_MEN"; + rise_power("scalar"){ + values (0.0300); + } + fall_power("scalar"){ + values (0.0015); + } + } + } + timing() { + timing_type : setup_rising; + related_pin : "B_CLK"; + when : "((B_WEN | B_REN)& B_MEN)" + sdf_cond : "B_RW_ACCESS" + + rise_constraint("SIG2SRAM_constraint_template") { + index_1("0.0040,0.0176,0.0344,0.0656,0.1120,0.2016,0.3800"); + index_2("0.0040,0.0176,0.0344,0.0656,0.1120,0.2016,0.3800"); + values ("-0.2371,-0.2215,-0.2098,-0.1824,-0.1434,-0.0691,0.0676",\ +"-0.2449,-0.2332,-0.2176,-0.1902,-0.1551,-0.0770,0.0559",\ +"-0.2605,-0.2488,-0.2332,-0.2059,-0.1707,-0.0965,0.0441",\ +"-0.2879,-0.2723,-0.2605,-0.2332,-0.1941,-0.1199,0.0168",\ +"-0.3230,-0.3113,-0.2996,-0.2723,-0.2332,-0.1590,-0.0184",\ +"-0.4012,-0.3895,-0.3738,-0.3465,-0.3074,-0.2332,-0.0965",\ +"-0.5379,-0.5262,-0.5105,-0.4832,-0.4480,-0.3699,-0.2332"); + } + + fall_constraint("SIG2SRAM_constraint_template") { + index_1("0.0040,0.0176,0.0344,0.0656,0.1120,0.2016,0.3800"); + index_2("0.0040,0.0176,0.0344,0.0656,0.1120,0.2016,0.3800"); + values ("-0.1785,-0.1707,-0.1551,-0.1277,-0.0887,-0.0184,0.1145",\ +"-0.1902,-0.1785,-0.1629,-0.1355,-0.1004,-0.0262,0.1027",\ +"-0.2059,-0.1941,-0.1785,-0.1512,-0.1160,-0.0418,0.0871",\ +"-0.2293,-0.2176,-0.2059,-0.1785,-0.1434,-0.0691,0.0598",\ +"-0.2684,-0.2566,-0.2449,-0.2176,-0.1824,-0.1082,0.0207",\ +"-0.3465,-0.3348,-0.3191,-0.2918,-0.2566,-0.1824,-0.0535",\ +"-0.4832,-0.4715,-0.4559,-0.4324,-0.3934,-0.3191,-0.1902"); + } + } + + + timing() { + timing_type : hold_rising; + related_pin : "B_CLK"; + when : "((B_WEN | B_REN)& B_MEN)" + sdf_cond : "B_RW_ACCESS" + + rise_constraint("SIG2SRAM_constraint_template") { + index_1("0.0040,0.0176,0.0344,0.0656,0.1120,0.2016,0.3800"); + index_2("0.0040,0.0176,0.0344,0.0656,0.1120,0.2016,0.3800"); + values ("0.3410,0.3293,0.3137,0.2863,0.2473,0.1730,0.0324",\ +"0.3488,0.3371,0.3215,0.2941,0.2590,0.1809,0.0480",\ +"0.3684,0.3527,0.3371,0.3098,0.2746,0.1965,0.0598",\ +"0.3918,0.3762,0.3645,0.3371,0.2980,0.2238,0.0871",\ +"0.4309,0.4152,0.4035,0.3762,0.3371,0.2629,0.1223",\ +"0.5051,0.4934,0.4777,0.4504,0.4113,0.3371,0.1965",\ +"0.6418,0.6262,0.6145,0.5871,0.5520,0.4738,0.3332"); + } + + fall_constraint("SIG2SRAM_constraint_template") { + index_1("0.0040,0.0176,0.0344,0.0656,0.1120,0.2016,0.3800"); + index_2("0.0040,0.0176,0.0344,0.0656,0.1120,0.2016,0.3800"); + values ("0.2824,0.2707,0.2551,0.2277,0.1926,0.1184,-0.0105",\ +"0.2902,0.2785,0.2668,0.2395,0.2043,0.1301,0.0012",\ +"0.3059,0.2941,0.2824,0.2551,0.2199,0.1457,0.0168",\ +"0.3332,0.3215,0.3059,0.2785,0.2434,0.1691,0.0402",\ +"0.3723,0.3605,0.3449,0.3176,0.2824,0.2121,0.0793",\ +"0.4465,0.4348,0.4230,0.3918,0.3566,0.2824,0.1535",\ +"0.5832,0.5715,0.5598,0.5324,0.4934,0.4191,0.2902"); + } + } +} +pin(B_WEN) { + direction : input ; + capacitance : 0.00341384 ; + max_transition : "0.38" ; + related_power_pin : VDD; + related_ground_pin : VSS; + internal_power() { + when : "B_MEN"; + rise_power("scalar"){ + values (0.0085); + } + fall_power("scalar"){ + values (0.0099); + } + } + internal_power() { + when : "!B_MEN"; + rise_power("scalar"){ + values (0.0074); + } + fall_power("scalar"){ + values (0.0341); + } + } + timing() { + timing_type : setup_rising; + related_pin : "B_CLK"; + when : "B_MEN" + sdf_cond : "B_MEN" + + rise_constraint("SIG2SRAM_constraint_template") { + index_1("0.0040,0.0176,0.0344,0.0656,0.1120,0.2016,0.3800"); + index_2("0.0040,0.0176,0.0344,0.0656,0.1120,0.2016,0.3800"); + values ("0.1418,0.1496,0.1652,0.1887,0.2316,0.3059,0.4465",\ +"0.1301,0.1379,0.1535,0.1809,0.2199,0.2941,0.4348",\ +"0.1145,0.1262,0.1379,0.1652,0.2043,0.2785,0.4191",\ +"0.0871,0.0949,0.1105,0.1379,0.1770,0.2512,0.3879",\ +"0.0480,0.0598,0.0754,0.0988,0.1379,0.2082,0.3527",\ +"-0.0262,-0.0145,0.0012,0.0246,0.0676,0.1379,0.2785",\ +"-0.1668,-0.1551,-0.1395,-0.1121,-0.0730,0.0012,0.1418"); + } + + fall_constraint("SIG2SRAM_constraint_template") { + index_1("0.0040,0.0176,0.0344,0.0656,0.1120,0.2016,0.3800"); + index_2("0.0040,0.0176,0.0344,0.0656,0.1120,0.2016,0.3800"); + values ("0.2082,0.2160,0.2316,0.2590,0.2941,0.3684,0.5012",\ +"0.1926,0.2043,0.2199,0.2473,0.2824,0.3566,0.4895",\ +"0.1770,0.1887,0.2043,0.2316,0.2668,0.3410,0.4777",\ +"0.1535,0.1652,0.1770,0.2043,0.2395,0.3137,0.4504",\ +"0.1145,0.1262,0.1379,0.1652,0.2043,0.2746,0.4113",\ +"0.0402,0.0520,0.0676,0.0910,0.1262,0.2004,0.3332",\ +"-0.0965,-0.0848,-0.0730,-0.0457,-0.0066,0.0637,0.2004"); + } + } + + + timing() { + timing_type : hold_rising; + related_pin : "B_CLK"; + when : "B_MEN" + sdf_cond : "B_MEN" + + rise_constraint("SIG2SRAM_constraint_template") { + index_1("0.0040,0.0176,0.0344,0.0656,0.1120,0.2016,0.3800"); + index_2("0.0040,0.0176,0.0344,0.0656,0.1120,0.2016,0.3800"); + values ("0.1770,0.1652,0.1496,0.1223,0.0793,0.0090,-0.1316",\ +"0.1848,0.1730,0.1574,0.1301,0.0910,0.0168,-0.1199",\ +"0.2004,0.1887,0.1770,0.1496,0.1066,0.0363,-0.1043",\ +"0.2277,0.2160,0.2004,0.1730,0.1340,0.0598,-0.0809",\ +"0.2668,0.2551,0.2395,0.2121,0.1730,0.0988,-0.0418",\ +"0.3410,0.3293,0.3137,0.2863,0.2434,0.1730,0.0324",\ +"0.4816,0.4699,0.4543,0.4230,0.3801,0.3098,0.1730"); + } + + fall_constraint("SIG2SRAM_constraint_template") { + index_1("0.0040,0.0176,0.0344,0.0656,0.1120,0.2016,0.3800"); + index_2("0.0040,0.0176,0.0344,0.0656,0.1120,0.2016,0.3800"); + values ("0.1613,0.1496,0.1379,0.1066,0.0715,0.0012,-0.1355",\ +"0.1730,0.1613,0.1457,0.1184,0.0832,0.0129,-0.1238",\ +"0.1887,0.1770,0.1613,0.1340,0.0988,0.0246,-0.1121",\ +"0.2121,0.2043,0.1887,0.1613,0.1223,0.0520,-0.0848",\ +"0.2512,0.2434,0.2277,0.2004,0.1613,0.0910,-0.0457",\ +"0.3254,0.3176,0.3020,0.2746,0.2355,0.1652,0.0324",\ +"0.4660,0.4543,0.4387,0.4113,0.3723,0.3020,0.1691"); + } + } + } +pin(B_REN) { + direction : input ; + capacitance : 0.00390661 ; + max_transition : "0.38" ; + related_power_pin : VDD; + related_ground_pin : VSS; + internal_power() { + when : "B_MEN"; + rise_power("scalar"){ + values (0.0111); + } + fall_power("scalar"){ + values (0.0100); + } + } + internal_power() { + when : "!B_MEN"; + rise_power("scalar"){ + values (0.0258); + } + fall_power("scalar"){ + values (0.0198); + } + } + timing() { + timing_type : setup_rising; + related_pin : "B_CLK"; + when : "B_MEN" + sdf_cond : "B_MEN" + + rise_constraint("SIG2SRAM_constraint_template") { + index_1("0.0040,0.0176,0.0344,0.0656,0.1120,0.2016,0.3800"); + index_2("0.0040,0.0176,0.0344,0.0656,0.1120,0.2016,0.3800"); + values ("-0.0027,0.0090,0.0246,0.0520,0.0910,0.1613,0.3020",\ +"-0.0105,0.0012,0.0129,0.0363,0.0793,0.1535,0.2902",\ +"-0.0262,-0.0145,-0.0027,0.0246,0.0637,0.1379,0.2785",\ +"-0.0535,-0.0418,-0.0262,0.0012,0.0363,0.1105,0.2512",\ +"-0.0926,-0.0809,-0.0652,-0.0418,-0.0027,0.0715,0.2121",\ +"-0.1668,-0.1551,-0.1395,-0.1082,-0.0770,-0.0027,0.1379",\ +"-0.3035,-0.2918,-0.2762,-0.2488,-0.2137,-0.1434,-0.0027"); + } + + fall_constraint("SIG2SRAM_constraint_template") { + index_1("0.0040,0.0176,0.0344,0.0656,0.1120,0.2016,0.3800"); + index_2("0.0040,0.0176,0.0344,0.0656,0.1120,0.2016,0.3800"); + values ("0.0832,0.0949,0.1105,0.1379,0.1730,0.2473,0.3801",\ +"0.0754,0.0832,0.0988,0.1223,0.1613,0.2355,0.3684",\ +"0.0598,0.0676,0.0832,0.1066,0.1457,0.2121,0.3527",\ +"0.0324,0.0441,0.0598,0.0871,0.1223,0.1926,0.3293",\ +"-0.0066,0.0051,0.0168,0.0480,0.0832,0.1535,0.2902",\ +"-0.0809,-0.0691,-0.0574,-0.0301,0.0090,0.0832,0.2121",\ +"-0.2176,-0.2059,-0.1941,-0.1668,-0.1277,-0.0574,0.0793"); + } + } + + + timing() { + timing_type : hold_rising; + related_pin : "B_CLK"; + when : "B_MEN" + sdf_cond : "B_MEN" + + rise_constraint("SIG2SRAM_constraint_template") { + index_1("0.0040,0.0176,0.0344,0.0656,0.1120,0.2016,0.3800"); + index_2("0.0040,0.0176,0.0344,0.0656,0.1120,0.2016,0.3800"); + values ("0.1887,0.1770,0.1613,0.1340,0.0949,0.0207,-0.1160",\ +"0.1965,0.1848,0.1730,0.1457,0.1027,0.0324,-0.1082",\ +"0.2160,0.2004,0.1887,0.1613,0.1184,0.0480,-0.0926",\ +"0.2395,0.2277,0.2121,0.1848,0.1457,0.0715,-0.0652",\ +"0.2785,0.2668,0.2512,0.2238,0.1848,0.1105,-0.0262",\ +"0.3527,0.3410,0.3254,0.2980,0.2551,0.1848,0.0480",\ +"0.4934,0.4816,0.4660,0.4387,0.3957,0.3254,0.1887"); + } + + fall_constraint("SIG2SRAM_constraint_template") { + index_1("0.0040,0.0176,0.0344,0.0656,0.1120,0.2016,0.3800"); + index_2("0.0040,0.0176,0.0344,0.0656,0.1120,0.2016,0.3800"); + values ("0.1730,0.1613,0.1496,0.1184,0.0793,0.0129,-0.1238",\ +"0.1848,0.1730,0.1574,0.1301,0.0910,0.0207,-0.1121",\ +"0.2004,0.1887,0.1730,0.1457,0.1066,0.0363,-0.1004",\ +"0.2238,0.2121,0.2004,0.1691,0.1340,0.0598,-0.0730",\ +"0.2629,0.2512,0.2395,0.2121,0.1691,0.0988,-0.0340",\ +"0.3371,0.3254,0.3137,0.2863,0.2434,0.1730,0.0402",\ +"0.4777,0.4660,0.4504,0.4230,0.3840,0.3137,0.1809"); + } + } + } +pin(B_MEN) { + direction : input ; + capacitance : 0.00326046 ; + max_transition : "0.38" ; + related_power_pin : VDD; + related_ground_pin : VSS; + internal_power() { + rise_power("scalar"){ + values (0.3396); + } + fall_power("scalar"){ + values (0.0093); + } + } + timing() { + timing_type : setup_rising; + related_pin : "B_CLK"; + + rise_constraint("SIG2SRAM_constraint_template") { + index_1("0.0040,0.0176,0.0344,0.0656,0.1120,0.2016,0.3800"); + index_2("0.0040,0.0176,0.0344,0.0656,0.1120,0.2016,0.3800"); + values ("0.1418,0.1496,0.1652,0.1926,0.2316,0.3059,0.4465",\ +"0.1301,0.1379,0.1535,0.1809,0.2199,0.2941,0.4348",\ +"0.1145,0.1262,0.1418,0.1652,0.2043,0.2785,0.4191",\ +"0.0871,0.0949,0.1105,0.1379,0.1770,0.2512,0.3879",\ +"0.0480,0.0598,0.0754,0.0988,0.1379,0.2082,0.3488",\ +"-0.0262,-0.0145,0.0012,0.0285,0.0676,0.1379,0.2785",\ +"-0.1668,-0.1551,-0.1395,-0.1121,-0.0730,0.0012,0.1379"); + } + + fall_constraint("SIG2SRAM_constraint_template") { + index_1("0.0040,0.0176,0.0344,0.0656,0.1120,0.2016,0.3800"); + index_2("0.0040,0.0176,0.0344,0.0656,0.1120,0.2016,0.3800"); + values ("0.2082,0.2199,0.2316,0.2590,0.2980,0.3723,0.5051",\ +"0.1965,0.2082,0.2199,0.2473,0.2863,0.3605,0.4934",\ +"0.1809,0.1926,0.2043,0.2316,0.2707,0.3449,0.4777",\ +"0.1574,0.1691,0.1809,0.2082,0.2434,0.3176,0.4543",\ +"0.1145,0.1262,0.1418,0.1691,0.2043,0.2785,0.4113",\ +"0.0441,0.0559,0.0676,0.0949,0.1301,0.2004,0.3332",\ +"-0.0965,-0.0848,-0.0691,-0.0418,-0.0066,0.0676,0.2004"); + } + } + + + timing() { + timing_type : hold_rising; + related_pin : "B_CLK"; + + rise_constraint("SIG2SRAM_constraint_template") { + index_1("0.0040,0.0176,0.0344,0.0656,0.1120,0.2016,0.3800"); + index_2("0.0040,0.0176,0.0344,0.0656,0.1120,0.2016,0.3800"); + values ("0.1770,0.1652,0.1535,0.1262,0.0832,0.0129,-0.1277",\ +"0.1887,0.1770,0.1613,0.1340,0.0949,0.0207,-0.1199",\ +"0.2043,0.1926,0.1770,0.1496,0.1105,0.0363,-0.1043",\ +"0.2277,0.2160,0.2043,0.1770,0.1379,0.0598,-0.0770",\ +"0.2668,0.2551,0.2434,0.2160,0.1730,0.0988,-0.0379",\ +"0.3449,0.3332,0.3176,0.2902,0.2473,0.1730,0.0363",\ +"0.4816,0.4699,0.4543,0.4270,0.3840,0.3098,0.1770"); + } + + fall_constraint("SIG2SRAM_constraint_template") { + index_1("0.0040,0.0176,0.0344,0.0656,0.1120,0.2016,0.3800"); + index_2("0.0040,0.0176,0.0344,0.0656,0.1120,0.2016,0.3800"); + values ("0.1613,0.1496,0.1379,0.1105,0.0715,0.0012,-0.1355",\ +"0.1730,0.1613,0.1496,0.1184,0.0832,0.0129,-0.1238",\ +"0.1887,0.1770,0.1652,0.1340,0.0988,0.0285,-0.1121",\ +"0.2121,0.2043,0.1887,0.1613,0.1223,0.0520,-0.0848",\ +"0.2551,0.2434,0.2277,0.2004,0.1613,0.0910,-0.0418",\ +"0.3293,0.3176,0.3020,0.2746,0.2395,0.1652,0.0324",\ +"0.4660,0.4543,0.4426,0.4113,0.3762,0.3020,0.1691"); + } + } + } + pin(B_CLK) { + direction : input; + capacitance : 0.00389386; + max_transition : "0.38"; + clock : "true" ; + pin_func_type : active_rising ; + + timing () { + timing_type : "min_pulse_width"; + related_pin : "B_CLK"; + rise_constraint("CLKTRAN_constraint_template") { + index_1("0.004,0.38"); + values("0.12,0.12"); + } + } + + related_power_pin : VDD; + related_ground_pin : VSS; + + internal_power() { + when : "!B_MEN & !B_WEN & !B_REN"; + rise_power("scalar"){ + values (0); + } + fall_power("scalar"){ + values (0); + } + } + internal_power() { + when : "!B_MEN & B_WEN & !B_REN"; + rise_power("scalar"){ + values (0.6237); + } + fall_power("scalar"){ + values (0); + } + } + internal_power() { + when : "B_MEN & B_WEN & !B_REN"; + rise_power("scalar"){ + values (33.3694); + } + fall_power("scalar"){ + values (0); + } + } + internal_power() { + when : "B_MEN & B_WEN & B_REN"; + rise_power("scalar"){ + values (37.6442); + } + fall_power("scalar"){ + values (0); + } + } + internal_power() { + when : "B_MEN & !B_WEN & B_REN"; + rise_power("scalar"){ + values (24.7144); + } + fall_power("scalar"){ + values (0); + } + } + internal_power() { + when : "!B_MEN & !B_WEN & B_REN"; + rise_power("scalar"){ + values (0.4148); + } + fall_power("scalar"){ + values (0); + } + } + internal_power() { + when : "!B_MEN & B_WEN & B_REN"; + rise_power("scalar"){ + values (1.5212); + } + fall_power("scalar"){ + values (0); + } + } + internal_power() { + when : "B_MEN & !B_WEN & !B_REN"; + rise_power("scalar"){ + values (0); + } + fall_power("scalar"){ + values (0); + } + } + } + bus(B_DIN) { + bus_type : D_31_0; + direction : input ; + capacitance : 0.00468868 ; + memory_write() { + address : B_ADDR ; + clocked_on : B_CLK; + } + + max_transition : "0.38" ; + pin(B_DIN[31:0]) { + related_power_pin : VDD; + related_ground_pin : VSS; + internal_power() { + when : "B_MEN"; + rise_power("scalar"){ + values (0.1417); + } + fall_power("scalar"){ + values (0.1431); + } + } + internal_power() { + when : "!B_MEN"; + rise_power("scalar"){ + values (0.1750); + } + fall_power("scalar"){ + values (0.1518); + } + } + } + timing() { + timing_type : setup_rising; + related_pin : "B_CLK"; + when : "(B_WEN & B_MEN)"; + sdf_cond : "B_W_ACCESS"; + + rise_constraint("SIG2SRAM_constraint_template") { + index_1("0.0040,0.0176,0.0344,0.0656,0.1120,0.2016,0.3800"); + index_2("0.0040,0.0176,0.0344,0.0656,0.1120,0.2016,0.3800"); + values ("-0.2756,-0.2649,-0.2493,-0.2219,-0.1848,-0.1096,0.0222",\ +"-0.2795,-0.2688,-0.2531,-0.2258,-0.1887,-0.1135,0.0183",\ +"-0.2832,-0.2725,-0.2568,-0.2295,-0.1924,-0.1172,0.0147",\ +"-0.2864,-0.2757,-0.2600,-0.2327,-0.1956,-0.1204,0.0115",\ +"-0.2990,-0.2883,-0.2726,-0.2453,-0.2082,-0.1330,-0.0012",\ +"-0.3166,-0.3059,-0.2903,-0.2629,-0.2258,-0.1506,-0.0188",\ +"-0.3441,-0.3334,-0.3178,-0.2904,-0.2533,-0.1781,-0.0463"); + } + + fall_constraint("SIG2SRAM_constraint_template") { + index_1("0.0040,0.0176,0.0344,0.0656,0.1120,0.2016,0.3800"); + index_2("0.0040,0.0176,0.0344,0.0656,0.1120,0.2016,0.3800"); + values ("-0.2483,-0.2375,-0.2239,-0.1965,-0.1594,-0.0872,0.0408",\ +"-0.2522,-0.2414,-0.2278,-0.2004,-0.1633,-0.0910,0.0369",\ +"-0.2559,-0.2451,-0.2314,-0.2041,-0.1670,-0.0947,0.0332",\ +"-0.2590,-0.2483,-0.2346,-0.2073,-0.1702,-0.0979,0.0300",\ +"-0.2717,-0.2609,-0.2473,-0.2199,-0.1828,-0.1105,0.0174",\ +"-0.2893,-0.2785,-0.2649,-0.2375,-0.2004,-0.1282,-0.0002",\ +"-0.3168,-0.3060,-0.2924,-0.2650,-0.2279,-0.1557,-0.0277"); + } + } + + timing() { + timing_type : hold_rising; + related_pin : "B_CLK"; + when : "(B_WEN & B_MEN)"; + sdf_cond : "B_W_ACCESS"; + + rise_constraint("SIG2SRAM_constraint_template") { + index_1("0.0040,0.0176,0.0344,0.0656,0.1120,0.2016,0.3800"); + index_2("0.0040,0.0176,0.0344,0.0656,0.1120,0.2016,0.3800"); + values ("0.3804,0.3687,0.3550,0.3287,0.2896,0.2193,0.0835",\ +"0.3843,0.3726,0.3589,0.3325,0.2935,0.2232,0.0874",\ +"0.3880,0.3763,0.3626,0.3362,0.2972,0.2268,0.0911",\ +"0.3912,0.3795,0.3658,0.3394,0.3004,0.2300,0.0943",\ +"0.4038,0.3921,0.3784,0.3520,0.3130,0.2427,0.1069",\ +"0.4214,0.4097,0.3960,0.3696,0.3306,0.2603,0.1245",\ +"0.4489,0.4372,0.4235,0.3972,0.3581,0.2878,0.1520"); + } + + fall_constraint("SIG2SRAM_constraint_template") { + index_1("0.0040,0.0176,0.0344,0.0656,0.1120,0.2016,0.3800"); + index_2("0.0040,0.0176,0.0344,0.0656,0.1120,0.2016,0.3800"); + values ("0.3501,0.3384,0.3248,0.2984,0.2613,0.1890,0.0601",\ +"0.3540,0.3423,0.3286,0.3023,0.2652,0.1929,0.0640",\ +"0.3577,0.3460,0.3323,0.3059,0.2688,0.1966,0.0677",\ +"0.3609,0.3492,0.3355,0.3091,0.2720,0.1998,0.0709",\ +"0.3735,0.3618,0.3481,0.3218,0.2847,0.2124,0.0835",\ +"0.3911,0.3794,0.3657,0.3394,0.3023,0.2300,0.1011",\ +"0.4186,0.4069,0.3932,0.3669,0.3298,0.2575,0.1286"); + } + } + } + +bus(B_DOUT) { + + bus_type : D_31_0; + direction : output ; + capacitance : 0 ; + max_capacitance : 0.064 ; + memory_read() { + address : B_ADDR ; + } + pin(B_DOUT[31:0]) { + related_power_pin : VDD; + related_ground_pin : VSS; + internal_power() { + rise_power("scalar") { + values (0); + } + fall_power("scalar") { + values (0); + } + } + } + timing() { + related_pin : "B_CLK"; + timing_type : rising_edge ; + timing_sense : non_unate ; + + cell_rise(SIG2SRAM_delay_template) { + index_1("0.0040,0.0176,0.0344,0.0656,0.1120,0.2016,0.3800"); + index_2("0.0008,0.0014,0.0051,0.0100,0.0339,0.0640"); + values ("1.8924,1.8934,1.8985,1.9037,1.9246,1.9482",\ +"1.8983,1.8993,1.9044,1.9096,1.9305,1.9541",\ +"1.9011,1.9021,1.9072,1.9124,1.9333,1.9569",\ +"1.9053,1.9063,1.9114,1.9166,1.9375,1.9611",\ +"1.9169,1.9179,1.9230,1.9282,1.9491,1.9727",\ +"1.9360,1.9370,1.9421,1.9473,1.9682,1.9918",\ +"1.9624,1.9634,1.9685,1.9737,1.9946,2.0182"); + } + cell_fall(SIG2SRAM_delay_template) { + index_1("0.0040,0.0176,0.0344,0.0656,0.1120,0.2016,0.3800"); + index_2("0.0008,0.0014,0.0051,0.0100,0.0339,0.0640"); + values ("1.8583,1.8591,1.8631,1.8679,1.8851,1.9017",\ +"1.8642,1.8651,1.8691,1.8738,1.8910,1.9076",\ +"1.8670,1.8678,1.8718,1.8766,1.8938,1.9104",\ +"1.8712,1.8720,1.8760,1.8808,1.8980,1.9146",\ +"1.8828,1.8836,1.8876,1.8924,1.9096,1.9262",\ +"1.9019,1.9028,1.9068,1.9115,1.9287,1.9453",\ +"1.9283,1.9291,1.9331,1.9379,1.9551,1.9717"); + } + + rise_transition(SRAM_load_template) { + index_1("0.0008,0.0014,0.0051,0.0100,0.0339,0.0640"); + values ("0.0206,0.0210,0.0265,0.0323,0.0606,0.0955"); + } + fall_transition(SRAM_load_template) { + index_1("0.0008,0.0014,0.0051,0.0100,0.0339,0.0640"); + values ("0.0170,0.0177,0.0222,0.0270,0.0451,0.0644"); + } + } +} +cell_leakage_power : 112.9267; +} +} diff --git a/flow/platforms/ihp-sg13g2/lib/RM_IHPSG13_2P_64x32_c2_slow_1p08V_125C.lib b/flow/platforms/ihp-sg13g2/lib/RM_IHPSG13_2P_64x32_c2_slow_1p08V_125C.lib new file mode 100644 index 0000000000..6368b16da7 --- /dev/null +++ b/flow/platforms/ihp-sg13g2/lib/RM_IHPSG13_2P_64x32_c2_slow_1p08V_125C.lib @@ -0,0 +1,1380 @@ +/* ------------------------------------------------------*/ +/**/ +/* Copyright 2023 IHP PDK Authors*/ +/**/ +/* Licensed under the Apache License, Version 2.0 (the "License");*/ +/* you may not use this file except in compliance with the License.*/ +/* You may obtain a copy of the License at*/ +/* */ +/* https://www.apache.org/licenses/LICENSE-2.0*/ +/* */ +/* Unless required by applicable law or agreed to in writing, software*/ +/* distributed under the License is distributed on an "AS IS" BASIS,*/ +/* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.*/ +/* See the License for the specific language governing permissions and*/ +/* limitations under the License.*/ +/* */ +/* Generated on Thu Jun 12 11:08:41 2025 */ +/* */ +/* ------------------------------------------------------ */ +library(RM_IHPSG13_2P_64x32_c2_slow_1p08V_125C) { + technology (cmos) ; + delay_model : table_lookup ; + define ("add_pg_pin_to_lib", "library", "boolean"); + add_pg_pin_to_lib : true; + voltage_map ( VDD, 1.08); + voltage_map ( VDDARRAY, 1.08); + voltage_map ( VSS, 0.000000 ); + + date : "Thu Jun 12 11:08:38 2025" ; + comment : "IHP Microelectronics GmbH, 2023" ; + revision : 1.0.0 ; + simulation : true ; + nom_process : 1 ; + nom_temperature : 125 ; + nom_voltage : 1.08 ; + + operating_conditions("slow_1p08V_125C"){ + process : 1 ; + temperature : 125 ; + voltage : 1.08 ; + tree_type : "balanced_tree" ; + } + + default_operating_conditions : slow_1p08V_125C ; + default_max_transition : 1.0 ; + default_fanout_load : 1.0 ; + default_inout_pin_cap : 0.0 ; + default_input_pin_cap : 0.0 ; + default_output_pin_cap : 0.0 ; + default_cell_leakage_power : 0.0 ; + default_leakage_power_density : 0.0 ; + + slew_lower_threshold_pct_rise : 30 ; + slew_upper_threshold_pct_rise : 70 ; + input_threshold_pct_fall : 50 ; + output_threshold_pct_fall : 50 ; + input_threshold_pct_rise : 50 ; + output_threshold_pct_rise : 50 ; + slew_lower_threshold_pct_fall : 30 ; + slew_upper_threshold_pct_fall : 70 ; + slew_derate_from_library : 0.5; + k_volt_cell_leakage_power : 0.0 ; + k_temp_cell_leakage_power : 0.0 ; + k_process_cell_leakage_power : 0.0 ; + k_volt_internal_power : 0.0 ; + k_temp_internal_power : 0.0 ; + k_process_internal_power : 0.0 ; + + capacitive_load_unit (1,pf) ; + voltage_unit : "1V" ; + current_unit : "1uA" ; + time_unit : "1ns" ; + leakage_power_unit : "1nW" ; + pulling_resistance_unit : "1kohm"; + /* + ------------------------------------------------------------------------------------------ + implicit units overview: + cell_area unit : "um" + internal_power unit : "1e-12 * J/toggle = 1 * uW/MHz" + (capacitive_load_unit * voltage_unit^2) per toggle event + ------------------------------------------------------------------------------------------ + */ + library_features(report_delay_calculation); + define_cell_area (pad_drivers,pad_driver_sites) ; + + lu_table_template(CLKTRAN_constraint_template) { + variable_1 : constrained_pin_transition; + index_1 ( "0.010, 0.050, 0.200, 0.400, 1.000" ); + } + lu_table_template(SRAM_load_template) { + variable_1 : total_output_net_capacitance; + index_1 ( "0.0008,0.0014,0.0051,0.0100,0.0339,0.0640" ); + } + lu_table_template(SIG2SRAM_constraint_template) { + variable_1 : related_pin_transition; + variable_2 : constrained_pin_transition; + index_1 ( "0.0080,0.0288,0.0616,0.1072,0.1920,0.3496,0.5952" ); + index_2 ( "0.0080,0.0288,0.0616,0.1072,0.1920,0.3496,0.5952" ); + } + + lu_table_template(SIG2SRAM_delay_template) { + variable_1 : input_net_transition; + variable_2 : total_output_net_capacitance; + index_1 ( "0.0080,0.0288,0.0616,0.1072,0.1920,0.3496,0.5952" ); + index_2 ( "0.0008,0.0014,0.0051,0.0100,0.0339,0.0640" ); + } + + type (D_31_0) { + base_type : array; + data_type : bit; + bit_width : 32; + bit_from : 31; + bit_to : 0; + downto : true; + } + + type (A_5_0) { + base_type : array; + data_type : bit; + bit_width : 6; + bit_from : 5; + bit_to : 0; + downto : true; + } + +cell(RM_IHPSG13_2P_64x32_c2) { +pg_pin (VDD) { + pg_type : primary_power; + voltage_name : VDD; +} +pg_pin (VDDARRAY) { + pg_type : primary_power; + voltage_name : VDDARRAY; +} +pg_pin (VSS) { + pg_type : primary_ground; + voltage_name : VSS; +} + +memory() { + type : ram; + address_width : 6; + word_width : 32; +} + +interface_timing : false; +bus_naming_style : "%s[%d]" ; +area : 52620.8821 ; + + pin(A_DLY) { + direction : input ; + capacitance : 0.00387999 ; + max_transition : "1" ; + related_power_pin : VDD; + related_ground_pin : VSS; + internal_power() { + rise_power("scalar") { + values (0); + } + fall_power("scalar") { + values (0); + } + } + } + +bus(A_ADDR) { + bus_type : A_5_0; + direction : input ; + capacitance : 0.0129586 ; + pin(A_ADDR[0]) { + capacitance : 0.0058687 ; + } + pin(A_ADDR[1]) { + capacitance : 0.00807137 ; + } + pin(A_ADDR[2]) { + capacitance : 0.0112051 ; + } + pin(A_ADDR[3]) { + capacitance : 0.00709524 ; + } + pin(A_ADDR[4]) { + capacitance : 0.00648778 ; + } + max_transition : "0.5952" ; + pin(A_ADDR[5:0]) { + related_power_pin : VDD; + related_ground_pin : VSS; + internal_power() { + when : "A_MEN"; + rise_power("scalar"){ + values (0.0157); + } + fall_power("scalar"){ + values (0.0502); + } + } + internal_power() { + when : "!A_MEN"; + rise_power("scalar"){ + values (0.1305); + } + fall_power("scalar"){ + values (0.0135); + } + } + } + timing() { + timing_type : setup_rising; + related_pin : "A_CLK"; + when : "((A_WEN | A_REN)& A_MEN)" + sdf_cond : "A_RW_ACCESS" + + rise_constraint("SIG2SRAM_constraint_template") { + index_1("0.0080,0.0288,0.0616,0.1072,0.1920,0.3496,0.5952"); + index_2("0.0080,0.0288,0.0616,0.1072,0.1920,0.3496,0.5952"); + values ("-0.7371,-0.7176,-0.6863,-0.6434,-0.5652,-0.4168,-0.1980",\ +"-0.7566,-0.7371,-0.7059,-0.6629,-0.5848,-0.4363,-0.2137",\ +"-0.7879,-0.7645,-0.7332,-0.6902,-0.6121,-0.4637,-0.2449",\ +"-0.8309,-0.8074,-0.7762,-0.7332,-0.6551,-0.5066,-0.2879",\ +"-0.9051,-0.8895,-0.8543,-0.8113,-0.7332,-0.5887,-0.3660",\ +"-1.0418,-1.0262,-0.9949,-0.9480,-0.8699,-0.7293,-0.5027",\ +"-1.2684,-1.2449,-1.2176,-1.1707,-1.0965,-0.9480,-0.7293"); + } + + fall_constraint("SIG2SRAM_constraint_template") { + index_1("0.0080,0.0288,0.0616,0.1072,0.1920,0.3496,0.5952"); + index_2("0.0080,0.0288,0.0616,0.1072,0.1920,0.3496,0.5952"); + values ("-0.5926,-0.5730,-0.5418,-0.4988,-0.4246,-0.2879,-0.0730",\ +"-0.6121,-0.5926,-0.5613,-0.5223,-0.4441,-0.3074,-0.0887",\ +"-0.6395,-0.6199,-0.5926,-0.5496,-0.4715,-0.3348,-0.1160",\ +"-0.6863,-0.6668,-0.6355,-0.5965,-0.5184,-0.3777,-0.1590",\ +"-0.7605,-0.7410,-0.7137,-0.6746,-0.5926,-0.4559,-0.2410",\ +"-0.9012,-0.8816,-0.8504,-0.8113,-0.7332,-0.5926,-0.3895",\ +"-1.1238,-1.1043,-1.0769,-1.0379,-0.9559,-0.8191,-0.6004"); + } + } + + + timing() { + timing_type : hold_rising; + related_pin : "A_CLK"; + when : "((A_WEN | A_REN)& A_MEN)" + sdf_cond : "A_RW_ACCESS" + + rise_constraint("SIG2SRAM_constraint_template") { + index_1("0.0080,0.0288,0.0616,0.1072,0.1920,0.3496,0.5952"); + index_2("0.0080,0.0288,0.0616,0.1072,0.1920,0.3496,0.5952"); + values ("0.8488,0.8293,0.7980,0.7551,0.6730,0.5285,0.3059",\ +"0.8684,0.8488,0.8176,0.7746,0.6926,0.5480,0.3254",\ +"0.8996,0.8801,0.8449,0.8020,0.7238,0.5754,0.3527",\ +"0.9426,0.9191,0.8918,0.8488,0.7668,0.6223,0.3996",\ +"1.0168,1.0012,0.9699,0.9230,0.8449,0.7004,0.4777",\ +"1.1574,1.1379,1.1105,1.0598,0.9816,0.8371,0.6184",\ +"1.3801,1.3605,1.3254,1.2980,1.2043,1.0637,0.8371"); + } + + fall_constraint("SIG2SRAM_constraint_template") { + index_1("0.0080,0.0288,0.0616,0.1072,0.1920,0.3496,0.5952"); + index_2("0.0080,0.0288,0.0616,0.1072,0.1920,0.3496,0.5952"); + values ("0.6965,0.6770,0.6496,0.6066,0.5246,0.3918,0.1730",\ +"0.7160,0.6965,0.6652,0.6262,0.5441,0.4113,0.1965",\ +"0.7473,0.7277,0.6965,0.6535,0.5754,0.4426,0.2238",\ +"0.7863,0.7707,0.7395,0.7004,0.6223,0.4855,0.2629",\ +"0.8684,0.8449,0.8176,0.7785,0.7004,0.5637,0.3449",\ +"1.0051,0.9855,0.9855,0.9113,0.8332,0.7004,0.4895",\ +"1.2277,1.2082,1.1809,1.1379,1.0598,0.9230,0.7004"); + } + } +} +pin(A_WEN) { + direction : input ; + capacitance : 0.00313551 ; + max_transition : "0.5952" ; + related_power_pin : VDD; + related_ground_pin : VSS; + internal_power() { + when : "A_MEN"; + rise_power("scalar"){ + values (0.1721); + } + fall_power("scalar"){ + values (0.2400); + } + } + internal_power() { + when : "!A_MEN"; + rise_power("scalar"){ + values (0.0059); + } + fall_power("scalar"){ + values (0.0023); + } + } + timing() { + timing_type : setup_rising; + related_pin : "A_CLK"; + when : "A_MEN" + sdf_cond : "A_MEN" + + rise_constraint("SIG2SRAM_constraint_template") { + index_1("0.0080,0.0288,0.0616,0.1072,0.1920,0.3496,0.5952"); + index_2("0.0080,0.0288,0.0616,0.1072,0.1920,0.3496,0.5952"); + values ("0.3137,0.3332,0.3605,0.4035,0.4816,0.6223,0.8488",\ +"0.2980,0.3176,0.3410,0.3840,0.4660,0.6027,0.8293",\ +"0.2629,0.2824,0.3098,0.3527,0.4348,0.5754,0.7980",\ +"0.2199,0.2395,0.2668,0.3098,0.3918,0.5324,0.7590",\ +"0.1418,0.1613,0.1887,0.2316,0.3137,0.4348,0.6730",\ +"0.0012,0.0207,0.0520,0.0910,0.1730,0.3098,0.5285",\ +"-0.2215,-0.2020,-0.1746,-0.1277,-0.0496,0.0910,0.3098"); + } + + fall_constraint("SIG2SRAM_constraint_template") { + index_1("0.0080,0.0288,0.0616,0.1072,0.1920,0.3496,0.5952"); + index_2("0.0080,0.0288,0.0616,0.1072,0.1920,0.3496,0.5952"); + values ("0.4504,0.4699,0.4973,0.5324,0.6027,0.7355,0.9699",\ +"0.4309,0.4504,0.4777,0.5129,0.5910,0.7160,0.9504",\ +"0.3996,0.4191,0.4465,0.4816,0.5520,0.6848,0.9191",\ +"0.3605,0.3762,0.4035,0.4387,0.5168,0.6418,0.8723",\ +"0.2785,0.2980,0.3215,0.3605,0.4348,0.5637,0.7980",\ +"0.1379,0.1574,0.1809,0.2199,0.2980,0.4309,0.6457",\ +"-0.0809,-0.0613,-0.0340,0.0051,0.0832,0.2160,0.4191"); + } + } + + + timing() { + timing_type : hold_rising; + related_pin : "A_CLK"; + when : "A_MEN" + sdf_cond : "A_MEN" + + rise_constraint("SIG2SRAM_constraint_template") { + index_1("0.0080,0.0288,0.0616,0.1072,0.1920,0.3496,0.5952"); + index_2("0.0080,0.0288,0.0616,0.1072,0.1920,0.3496,0.5952"); + values ("0.3723,0.3527,0.3215,0.2785,0.1965,0.0559,-0.1668",\ +"0.3918,0.3723,0.3449,0.2980,0.2160,0.0754,-0.1473",\ +"0.4152,0.3996,0.3684,0.3254,0.2434,0.1066,-0.1199",\ +"0.4621,0.4465,0.4152,0.3723,0.2863,0.1496,-0.0730",\ +"0.5324,0.5207,0.4895,0.4465,0.3645,0.2199,0.0051",\ +"0.6770,0.6535,0.6301,0.5832,0.5090,0.3605,0.1418",\ +"0.9035,0.8879,0.8566,0.8137,0.7316,0.5871,0.3684"); + } + + fall_constraint("SIG2SRAM_constraint_template") { + index_1("0.0080,0.0288,0.0616,0.1072,0.1920,0.3496,0.5952"); + index_2("0.0080,0.0288,0.0616,0.1072,0.1920,0.3496,0.5952"); + values ("0.3762,0.3566,0.3293,0.2863,0.2043,0.0676,-0.1434",\ +"0.3957,0.3762,0.3488,0.3059,0.2238,0.0871,-0.1199",\ +"0.4230,0.4035,0.3723,0.3332,0.2512,0.1184,-0.0965",\ +"0.4660,0.4465,0.4191,0.3762,0.2941,0.1613,-0.0496",\ +"0.5324,0.5168,0.4973,0.4543,0.3723,0.2316,0.0285",\ +"0.6809,0.6613,0.6340,0.5910,0.5129,0.3645,0.1652",\ +"0.9113,0.8918,0.8605,0.8176,0.7395,0.5988,0.3879"); + } + } + } +pin(A_REN) { + direction : input ; + capacitance : 0.00381144 ; + max_transition : "0.5952" ; + related_power_pin : VDD; + related_ground_pin : VSS; + internal_power() { + when : "A_MEN"; + rise_power("scalar"){ + values (0.2069); + } + fall_power("scalar"){ + values (0.2018); + } + } + internal_power() { + when : "!A_MEN"; + rise_power("scalar"){ + values (0.0034); + } + fall_power("scalar"){ + values (0.0021); + } + } + timing() { + timing_type : setup_rising; + related_pin : "A_CLK"; + when : "A_MEN" + sdf_cond : "A_MEN" + + rise_constraint("SIG2SRAM_constraint_template") { + index_1("0.0080,0.0288,0.0616,0.1072,0.1920,0.3496,0.5952"); + index_2("0.0080,0.0288,0.0616,0.1072,0.1920,0.3496,0.5952"); + values ("-0.0770,-0.0574,-0.0262,0.0168,0.0949,0.2355,0.4582",\ +"-0.0965,-0.0770,-0.0457,-0.0027,0.0754,0.2160,0.4387",\ +"-0.1199,-0.1004,-0.0730,-0.0262,0.0520,0.1887,0.4113",\ +"-0.1590,-0.1434,-0.1160,-0.0730,0.0051,0.1457,0.3645",\ +"-0.2449,-0.2254,-0.1941,-0.1473,-0.0770,0.0676,0.2863",\ +"-0.3816,-0.3699,-0.3387,-0.2801,-0.2215,-0.0770,0.1457",\ +"-0.6121,-0.5926,-0.5613,-0.5145,-0.4363,-0.2996,-0.0730"); + } + + fall_constraint("SIG2SRAM_constraint_template") { + index_1("0.0080,0.0288,0.0616,0.1072,0.1920,0.3496,0.5952"); + index_2("0.0080,0.0288,0.0616,0.1072,0.1920,0.3496,0.5952"); + values ("0.1262,0.1457,0.1691,0.2121,0.2824,0.4191,0.6457",\ +"0.1105,0.1262,0.1496,0.1887,0.2629,0.3996,0.6262",\ +"0.0793,0.0949,0.1223,0.1652,0.2395,0.3684,0.5949",\ +"0.0363,0.0559,0.0793,0.1223,0.2004,0.3410,0.5520",\ +"-0.0457,-0.0262,0.0012,0.0441,0.1301,0.2629,0.4738",\ +"-0.1902,-0.1746,-0.1434,-0.1043,-0.0184,0.1223,0.3332",\ +"-0.4129,-0.3934,-0.3660,-0.3230,-0.2449,-0.1043,0.1105"); + } + } + + + timing() { + timing_type : hold_rising; + related_pin : "A_CLK"; + when : "A_MEN" + sdf_cond : "A_MEN" + + rise_constraint("SIG2SRAM_constraint_template") { + index_1("0.0080,0.0288,0.0616,0.1072,0.1920,0.3496,0.5952"); + index_2("0.0080,0.0288,0.0616,0.1072,0.1920,0.3496,0.5952"); + values ("0.4113,0.3918,0.3645,0.3176,0.2395,0.0988,-0.1238",\ +"0.4309,0.4113,0.3840,0.3371,0.2590,0.1184,-0.1043",\ +"0.4582,0.4387,0.4113,0.3645,0.2824,0.1457,-0.0770",\ +"0.5051,0.4816,0.4543,0.4074,0.3293,0.1887,-0.0340",\ +"0.5715,0.5598,0.5324,0.4895,0.4035,0.2512,0.0441",\ +"0.7043,0.7004,0.6730,0.6262,0.5402,0.3957,0.1809",\ +"0.9387,0.9270,0.8957,0.8527,0.7746,0.6262,0.4074"); + } + + fall_constraint("SIG2SRAM_constraint_template") { + index_1("0.0080,0.0288,0.0616,0.1072,0.1920,0.3496,0.5952"); + index_2("0.0080,0.0288,0.0616,0.1072,0.1920,0.3496,0.5952"); + values ("0.4152,0.3918,0.3645,0.3215,0.2395,0.1027,-0.1082",\ +"0.4309,0.4113,0.3801,0.3410,0.2590,0.1223,-0.0926",\ +"0.4582,0.4387,0.4074,0.3684,0.2863,0.1496,-0.0613",\ +"0.5012,0.4816,0.4504,0.4074,0.3293,0.1887,-0.0145",\ +"0.5715,0.5559,0.5285,0.4816,0.3996,0.2512,0.0598",\ +"0.7160,0.7004,0.6691,0.6262,0.5520,0.4035,0.2004",\ +"0.9387,0.9191,0.8957,0.8488,0.7707,0.6262,0.4113"); + } + } + } +pin(A_MEN) { + direction : input ; + capacitance : 0.00300347 ; + max_transition : "0.5952" ; + related_power_pin : VDD; + related_ground_pin : VSS; + internal_power() { + rise_power("scalar"){ + values (0.5519); + } + fall_power("scalar"){ + values (0.0392); + } + } + timing() { + timing_type : setup_rising; + related_pin : "A_CLK"; + + rise_constraint("SIG2SRAM_constraint_template") { + index_1("0.0080,0.0288,0.0616,0.1072,0.1920,0.3496,0.5952"); + index_2("0.0080,0.0288,0.0616,0.1072,0.1920,0.3496,0.5952"); + values ("0.3215,0.3449,0.3684,0.4113,0.4895,0.6301,0.8527",\ +"0.3059,0.3254,0.3527,0.3957,0.4738,0.6145,0.8371",\ +"0.2746,0.2941,0.3215,0.3645,0.4426,0.5871,0.8059",\ +"0.2316,0.2512,0.2785,0.3215,0.3996,0.5402,0.7629",\ +"0.1496,0.1730,0.1965,0.2395,0.3215,0.4660,0.6848",\ +"0.0090,0.0285,0.0598,0.1027,0.1809,0.3176,0.5402",\ +"-0.2098,-0.1902,-0.1668,-0.1199,-0.0418,0.0988,0.3137"); + } + + fall_constraint("SIG2SRAM_constraint_template") { + index_1("0.0080,0.0288,0.0616,0.1072,0.1920,0.3496,0.5952"); + index_2("0.0080,0.0288,0.0616,0.1072,0.1920,0.3496,0.5952"); + values ("0.4582,0.4738,0.5012,0.5363,0.6145,0.7395,0.9738",\ +"0.4387,0.4543,0.4816,0.5207,0.5910,0.7199,0.9582",\ +"0.4035,0.4230,0.4504,0.4855,0.5637,0.6887,0.9230",\ +"0.3645,0.3840,0.4074,0.4465,0.5285,0.6496,0.8840",\ +"0.2824,0.3020,0.3254,0.3645,0.4465,0.5715,0.7980",\ +"0.1418,0.1613,0.1887,0.2238,0.3020,0.4309,0.6496",\ +"-0.0770,-0.0574,-0.0301,0.0090,0.0910,0.2238,0.4191"); + } + } + + + timing() { + timing_type : hold_rising; + related_pin : "A_CLK"; + + rise_constraint("SIG2SRAM_constraint_template") { + index_1("0.0080,0.0288,0.0616,0.1072,0.1920,0.3496,0.5952"); + index_2("0.0080,0.0288,0.0616,0.1072,0.1920,0.3496,0.5952"); + values ("0.3762,0.3605,0.3293,0.2863,0.2043,0.0637,-0.1629",\ +"0.3996,0.3801,0.3488,0.3020,0.2238,0.0832,-0.1395",\ +"0.4230,0.4074,0.3723,0.3293,0.2473,0.1105,-0.1121",\ +"0.4621,0.4465,0.4152,0.3762,0.2941,0.1535,-0.0691",\ +"0.5441,0.5285,0.4973,0.4465,0.3684,0.2316,0.0090",\ +"0.6848,0.6652,0.6301,0.5910,0.5129,0.3605,0.1496",\ +"0.9074,0.8918,0.8566,0.8215,0.7395,0.5910,0.3723"); + } + + fall_constraint("SIG2SRAM_constraint_template") { + index_1("0.0080,0.0288,0.0616,0.1072,0.1920,0.3496,0.5952"); + index_2("0.0080,0.0288,0.0616,0.1072,0.1920,0.3496,0.5952"); + values ("0.3762,0.3605,0.3332,0.2863,0.2043,0.0715,-0.1395",\ +"0.3996,0.3762,0.3488,0.3059,0.2238,0.0910,-0.1199",\ +"0.4270,0.4035,0.3762,0.3332,0.2512,0.1184,-0.0965",\ +"0.4699,0.4504,0.4191,0.3762,0.2941,0.1613,-0.0496",\ +"0.5441,0.5285,0.4973,0.4543,0.3762,0.2355,0.0324",\ +"0.6770,0.6613,0.6340,0.5949,0.5207,0.3762,0.1652",\ +"0.9074,0.8918,0.8605,0.8176,0.7395,0.6027,0.3918"); + } + } + } + pin(A_CLK) { + direction : input; + capacitance : 0.00378957; + max_transition : "0.5952"; + clock : "true" ; + pin_func_type : active_rising ; + + timing () { + timing_type : "min_pulse_width"; + related_pin : "A_CLK"; + rise_constraint("CLKTRAN_constraint_template") { + index_1("0.008,0.5952"); + values("0.4,0.4"); + } + } + + related_power_pin : VDD; + related_ground_pin : VSS; + + internal_power() { + when : "!A_MEN & !A_WEN & !A_REN"; + rise_power("scalar"){ + values (0); + } + fall_power("scalar"){ + values (0); + } + } + internal_power() { + when : "!A_MEN & A_WEN & !A_REN"; + rise_power("scalar"){ + values (0.3989); + } + fall_power("scalar"){ + values (0); + } + } + internal_power() { + when : "A_MEN & A_WEN & !A_REN"; + rise_power("scalar"){ + values (21.7214); + } + fall_power("scalar"){ + values (0); + } + } + internal_power() { + when : "A_MEN & A_WEN & A_REN"; + rise_power("scalar"){ + values (24.3851); + } + fall_power("scalar"){ + values (0); + } + } + internal_power() { + when : "A_MEN & !A_WEN & A_REN"; + rise_power("scalar"){ + values (17.0893); + } + fall_power("scalar"){ + values (0); + } + } + internal_power() { + when : "!A_MEN & !A_WEN & A_REN"; + rise_power("scalar"){ + values (0.2951); + } + fall_power("scalar"){ + values (0); + } + } + internal_power() { + when : "!A_MEN & A_WEN & A_REN"; + rise_power("scalar"){ + values (0.9866); + } + fall_power("scalar"){ + values (0); + } + } + internal_power() { + when : "A_MEN & !A_WEN & !A_REN"; + rise_power("scalar"){ + values (0); + } + fall_power("scalar"){ + values (0); + } + } + } + bus(A_DIN) { + bus_type : D_31_0; + direction : input ; + capacitance : 0.00502163 ; + memory_write() { + address : A_ADDR ; + clocked_on : A_CLK; + } + + max_transition : "0.5952" ; + pin(A_DIN[31:0]) { + related_power_pin : VDD; + related_ground_pin : VSS; + internal_power() { + when : "A_MEN"; + rise_power("scalar"){ + values (0.2888); + } + fall_power("scalar"){ + values (0.5290); + } + } + internal_power() { + when : "!A_MEN"; + rise_power("scalar"){ + values (0.0897); + } + fall_power("scalar"){ + values (0.0306); + } + } + } + timing() { + timing_type : setup_rising; + related_pin : "A_CLK"; + when : "(A_WEN & A_MEN)"; + sdf_cond : "A_W_ACCESS"; + + rise_constraint("SIG2SRAM_constraint_template") { + index_1("0.0080,0.0288,0.0616,0.1072,0.1920,0.3496,0.5952"); + index_2("0.0080,0.0288,0.0616,0.1072,0.1920,0.3496,0.5952"); + values ("-0.8824,-0.8629,-0.8365,-0.7916,-0.7125,-0.5689,-0.3453",\ +"-0.8903,-0.8708,-0.8444,-0.7995,-0.7204,-0.5769,-0.3532",\ +"-0.8995,-0.8799,-0.8536,-0.8087,-0.7296,-0.5860,-0.3624",\ +"-0.9145,-0.8949,-0.8686,-0.8236,-0.7445,-0.6010,-0.3773",\ +"-0.9368,-0.9173,-0.8909,-0.8460,-0.7669,-0.6234,-0.3997",\ +"-0.9804,-0.9609,-0.9345,-0.8896,-0.8105,-0.6670,-0.4433",\ +"-1.0496,-1.0301,-1.0037,-0.9588,-0.8797,-0.7361,-0.5125"); + } + + fall_constraint("SIG2SRAM_constraint_template") { + index_1("0.0080,0.0288,0.0616,0.1072,0.1920,0.3496,0.5952"); + index_2("0.0080,0.0288,0.0616,0.1072,0.1920,0.3496,0.5952"); + values ("-0.8082,-0.7906,-0.7623,-0.7232,-0.6402,-0.5045,-0.2916",\ +"-0.8161,-0.7985,-0.7702,-0.7312,-0.6481,-0.5124,-0.2995",\ +"-0.8253,-0.8077,-0.7794,-0.7403,-0.6573,-0.5215,-0.3087",\ +"-0.8402,-0.8227,-0.7943,-0.7553,-0.6723,-0.5365,-0.3236",\ +"-0.8626,-0.8450,-0.8167,-0.7777,-0.6946,-0.5589,-0.3460",\ +"-0.9062,-0.8886,-0.8603,-0.8213,-0.7382,-0.6025,-0.3896",\ +"-0.9754,-0.9578,-0.9295,-0.8904,-0.8074,-0.6717,-0.4588"); + } + } + + timing() { + timing_type : hold_rising; + related_pin : "A_CLK"; + when : "(A_WEN & A_MEN)"; + sdf_cond : "A_W_ACCESS"; + + rise_constraint("SIG2SRAM_constraint_template") { + index_1("0.0080,0.0288,0.0616,0.1072,0.1920,0.3496,0.5952"); + index_2("0.0080,0.0288,0.0616,0.1072,0.1920,0.3496,0.5952"); + values ("0.9949,0.9744,0.9470,0.9041,0.8269,0.6834,0.4558",\ +"1.0028,0.9823,0.9550,0.9120,0.8348,0.6913,0.4637",\ +"1.0119,0.9914,0.9641,0.9211,0.8440,0.7004,0.4729",\ +"1.0269,1.0064,0.9791,0.9361,0.8590,0.7154,0.4879",\ +"1.0493,1.0288,1.0015,0.9585,0.8813,0.7378,0.5102",\ +"1.0929,1.0724,1.0451,1.0021,0.9249,0.7814,0.5538",\ +"1.1621,1.1416,1.1142,1.0713,0.9941,0.8506,0.6230"); + } + + fall_constraint("SIG2SRAM_constraint_template") { + index_1("0.0080,0.0288,0.0616,0.1072,0.1920,0.3496,0.5952"); + index_2("0.0080,0.0288,0.0616,0.1072,0.1920,0.3496,0.5952"); + values ("0.9129,0.8933,0.8670,0.8279,0.7449,0.6082,0.3992",\ +"0.9208,0.9012,0.8749,0.8358,0.7528,0.6161,0.4071",\ +"0.9299,0.9104,0.8840,0.8450,0.7619,0.6252,0.4163",\ +"0.9449,0.9254,0.8990,0.8599,0.7769,0.6402,0.4312",\ +"0.9673,0.9477,0.9214,0.8823,0.7993,0.6626,0.4536",\ +"1.0109,0.9913,0.9650,0.9259,0.8429,0.7062,0.4972",\ +"1.0801,1.0605,1.0342,0.9951,0.9121,0.7754,0.5664"); + } + } + } + +bus(A_DOUT) { + + bus_type : D_31_0; + direction : output ; + capacitance : 0 ; + max_capacitance : 0.064 ; + memory_read() { + address : A_ADDR ; + } + pin(A_DOUT[31:0]) { + related_power_pin : VDD; + related_ground_pin : VSS; + internal_power() { + rise_power("scalar") { + values (0); + } + fall_power("scalar") { + values (0); + } + } + } + timing() { + related_pin : "A_CLK"; + timing_type : rising_edge ; + timing_sense : non_unate ; + + cell_rise(SIG2SRAM_delay_template) { + index_1("0.0080,0.0288,0.0616,0.1072,0.1920,0.3496,0.5952"); + index_2("0.0008,0.0014,0.0051,0.0100,0.0339,0.0640"); + values ("5.2125,5.2152,5.2276,5.2418,5.2940,5.3520",\ +"5.2265,5.2291,5.2416,5.2557,5.3079,5.3659",\ +"5.2363,5.2389,5.2514,5.2655,5.3177,5.3757",\ +"5.2496,5.2522,5.2647,5.2788,5.3310,5.3890",\ +"5.2729,5.2755,5.2880,5.3021,5.3543,5.4123",\ +"5.3176,5.3202,5.3327,5.3468,5.3991,5.4570",\ +"5.3849,5.3875,5.4000,5.4141,5.4663,5.5243"); + } + cell_fall(SIG2SRAM_delay_template) { + index_1("0.0080,0.0288,0.0616,0.1072,0.1920,0.3496,0.5952"); + index_2("0.0008,0.0014,0.0051,0.0100,0.0339,0.0640"); + values ("5.1008,5.1030,5.1128,5.1242,5.1674,5.2119",\ +"5.1147,5.1169,5.1267,5.1381,5.1813,5.2258",\ +"5.1246,5.1267,5.1365,5.1479,5.1912,5.2357",\ +"5.1379,5.1400,5.1498,5.1612,5.2045,5.2490",\ +"5.1612,5.1633,5.1731,5.1845,5.2277,5.2723",\ +"5.2059,5.2081,5.2178,5.2292,5.2725,5.3170",\ +"5.2732,5.2753,5.2851,5.2965,5.3398,5.3843"); + } + + rise_transition(SRAM_load_template) { + index_1("0.0008,0.0014,0.0051,0.0100,0.0339,0.0640"); + values ("0.0560,0.0583,0.0696,0.0816,0.1519,0.2335"); + } + fall_transition(SRAM_load_template) { + index_1("0.0008,0.0014,0.0051,0.0100,0.0339,0.0640"); + values ("0.0428,0.0445,0.0538,0.0658,0.1181,0.1751"); + } + } +} + pin(B_DLY) { + direction : input ; + capacitance : 0.00387999 ; + max_transition : "1" ; + related_power_pin : VDD; + related_ground_pin : VSS; + internal_power() { + rise_power("scalar") { + values (0); + } + fall_power("scalar") { + values (0); + } + } + } + +bus(B_ADDR) { + bus_type : A_5_0; + direction : input ; + capacitance : 0.0129586 ; + pin(B_ADDR[0]) { + capacitance : 0.00588404 ; + } + pin(B_ADDR[1]) { + capacitance : 0.0080425 ; + } + pin(B_ADDR[2]) { + capacitance : 0.0112051 ; + } + pin(B_ADDR[3]) { + capacitance : 0.00706428 ; + } + pin(B_ADDR[4]) { + capacitance : 0.00656149 ; + } + max_transition : "0.5952" ; + pin(B_ADDR[5:0]) { + related_power_pin : VDD; + related_ground_pin : VSS; + internal_power() { + when : "B_MEN"; + rise_power("scalar"){ + values (0.0157); + } + fall_power("scalar"){ + values (0.0502); + } + } + internal_power() { + when : "!B_MEN"; + rise_power("scalar"){ + values (0.1305); + } + fall_power("scalar"){ + values (0.0135); + } + } + } + timing() { + timing_type : setup_rising; + related_pin : "B_CLK"; + when : "((B_WEN | B_REN)& B_MEN)" + sdf_cond : "B_RW_ACCESS" + + rise_constraint("SIG2SRAM_constraint_template") { + index_1("0.0080,0.0288,0.0616,0.1072,0.1920,0.3496,0.5952"); + index_2("0.0080,0.0288,0.0616,0.1072,0.1920,0.3496,0.5952"); + values ("-0.7371,-0.7176,-0.6863,-0.6434,-0.5652,-0.4168,-0.1980",\ +"-0.7566,-0.7371,-0.7059,-0.6629,-0.5848,-0.4363,-0.2137",\ +"-0.7879,-0.7645,-0.7332,-0.6902,-0.6121,-0.4637,-0.2449",\ +"-0.8309,-0.8074,-0.7762,-0.7332,-0.6551,-0.5066,-0.2879",\ +"-0.9051,-0.8895,-0.8543,-0.8113,-0.7332,-0.5887,-0.3660",\ +"-1.0418,-1.0262,-0.9949,-0.9480,-0.8699,-0.7293,-0.5027",\ +"-1.2684,-1.2449,-1.2176,-1.1707,-1.0965,-0.9480,-0.7293"); + } + + fall_constraint("SIG2SRAM_constraint_template") { + index_1("0.0080,0.0288,0.0616,0.1072,0.1920,0.3496,0.5952"); + index_2("0.0080,0.0288,0.0616,0.1072,0.1920,0.3496,0.5952"); + values ("-0.5926,-0.5730,-0.5418,-0.4988,-0.4246,-0.2879,-0.0730",\ +"-0.6121,-0.5926,-0.5613,-0.5223,-0.4441,-0.3074,-0.0887",\ +"-0.6395,-0.6199,-0.5926,-0.5496,-0.4715,-0.3348,-0.1160",\ +"-0.6863,-0.6668,-0.6355,-0.5965,-0.5184,-0.3777,-0.1590",\ +"-0.7605,-0.7410,-0.7137,-0.6746,-0.5926,-0.4559,-0.2410",\ +"-0.9012,-0.8816,-0.8504,-0.8113,-0.7332,-0.5926,-0.3895",\ +"-1.1238,-1.1043,-1.0769,-1.0379,-0.9559,-0.8191,-0.6004"); + } + } + + + timing() { + timing_type : hold_rising; + related_pin : "B_CLK"; + when : "((B_WEN | B_REN)& B_MEN)" + sdf_cond : "B_RW_ACCESS" + + rise_constraint("SIG2SRAM_constraint_template") { + index_1("0.0080,0.0288,0.0616,0.1072,0.1920,0.3496,0.5952"); + index_2("0.0080,0.0288,0.0616,0.1072,0.1920,0.3496,0.5952"); + values ("0.8488,0.8293,0.7980,0.7551,0.6730,0.5285,0.3059",\ +"0.8684,0.8488,0.8176,0.7746,0.6926,0.5480,0.3254",\ +"0.8996,0.8801,0.8449,0.8020,0.7238,0.5754,0.3527",\ +"0.9426,0.9191,0.8918,0.8488,0.7668,0.6223,0.3996",\ +"1.0168,1.0012,0.9699,0.9230,0.8449,0.7004,0.4777",\ +"1.1574,1.1379,1.1105,1.0598,0.9816,0.8371,0.6184",\ +"1.3801,1.3605,1.3254,1.2980,1.2043,1.0637,0.8371"); + } + + fall_constraint("SIG2SRAM_constraint_template") { + index_1("0.0080,0.0288,0.0616,0.1072,0.1920,0.3496,0.5952"); + index_2("0.0080,0.0288,0.0616,0.1072,0.1920,0.3496,0.5952"); + values ("0.6965,0.6770,0.6496,0.6066,0.5246,0.3918,0.1730",\ +"0.7160,0.6965,0.6652,0.6262,0.5441,0.4113,0.1965",\ +"0.7473,0.7277,0.6965,0.6535,0.5754,0.4426,0.2238",\ +"0.7863,0.7707,0.7395,0.7004,0.6223,0.4855,0.2629",\ +"0.8684,0.8449,0.8176,0.7785,0.7004,0.5637,0.3449",\ +"1.0051,0.9855,0.9855,0.9113,0.8332,0.7004,0.4895",\ +"1.2277,1.2082,1.1809,1.1379,1.0598,0.9230,0.7004"); + } + } +} +pin(B_WEN) { + direction : input ; + capacitance : 0.00313551 ; + max_transition : "0.5952" ; + related_power_pin : VDD; + related_ground_pin : VSS; + internal_power() { + when : "B_MEN"; + rise_power("scalar"){ + values (0.1721); + } + fall_power("scalar"){ + values (0.2400); + } + } + internal_power() { + when : "!B_MEN"; + rise_power("scalar"){ + values (0.0059); + } + fall_power("scalar"){ + values (0.0023); + } + } + timing() { + timing_type : setup_rising; + related_pin : "B_CLK"; + when : "B_MEN" + sdf_cond : "B_MEN" + + rise_constraint("SIG2SRAM_constraint_template") { + index_1("0.0080,0.0288,0.0616,0.1072,0.1920,0.3496,0.5952"); + index_2("0.0080,0.0288,0.0616,0.1072,0.1920,0.3496,0.5952"); + values ("0.3137,0.3332,0.3605,0.4035,0.4816,0.6223,0.8488",\ +"0.2980,0.3176,0.3410,0.3840,0.4660,0.6027,0.8293",\ +"0.2629,0.2824,0.3098,0.3527,0.4348,0.5754,0.7980",\ +"0.2199,0.2395,0.2668,0.3098,0.3918,0.5324,0.7590",\ +"0.1418,0.1613,0.1887,0.2316,0.3137,0.4348,0.6730",\ +"0.0012,0.0207,0.0520,0.0910,0.1730,0.3098,0.5285",\ +"-0.2215,-0.2020,-0.1746,-0.1277,-0.0496,0.0910,0.3098"); + } + + fall_constraint("SIG2SRAM_constraint_template") { + index_1("0.0080,0.0288,0.0616,0.1072,0.1920,0.3496,0.5952"); + index_2("0.0080,0.0288,0.0616,0.1072,0.1920,0.3496,0.5952"); + values ("0.4504,0.4699,0.4973,0.5324,0.6027,0.7355,0.9699",\ +"0.4309,0.4504,0.4777,0.5129,0.5910,0.7160,0.9504",\ +"0.3996,0.4191,0.4465,0.4816,0.5520,0.6848,0.9191",\ +"0.3605,0.3762,0.4035,0.4387,0.5168,0.6418,0.8723",\ +"0.2785,0.2980,0.3215,0.3605,0.4348,0.5637,0.7980",\ +"0.1379,0.1574,0.1809,0.2199,0.2980,0.4309,0.6457",\ +"-0.0809,-0.0613,-0.0340,0.0051,0.0832,0.2160,0.4191"); + } + } + + + timing() { + timing_type : hold_rising; + related_pin : "B_CLK"; + when : "B_MEN" + sdf_cond : "B_MEN" + + rise_constraint("SIG2SRAM_constraint_template") { + index_1("0.0080,0.0288,0.0616,0.1072,0.1920,0.3496,0.5952"); + index_2("0.0080,0.0288,0.0616,0.1072,0.1920,0.3496,0.5952"); + values ("0.3723,0.3527,0.3215,0.2785,0.1965,0.0559,-0.1668",\ +"0.3918,0.3723,0.3449,0.2980,0.2160,0.0754,-0.1473",\ +"0.4152,0.3996,0.3684,0.3254,0.2434,0.1066,-0.1199",\ +"0.4621,0.4465,0.4152,0.3723,0.2863,0.1496,-0.0730",\ +"0.5324,0.5207,0.4895,0.4465,0.3645,0.2199,0.0051",\ +"0.6770,0.6535,0.6301,0.5832,0.5090,0.3605,0.1418",\ +"0.9035,0.8879,0.8566,0.8137,0.7316,0.5871,0.3684"); + } + + fall_constraint("SIG2SRAM_constraint_template") { + index_1("0.0080,0.0288,0.0616,0.1072,0.1920,0.3496,0.5952"); + index_2("0.0080,0.0288,0.0616,0.1072,0.1920,0.3496,0.5952"); + values ("0.3762,0.3566,0.3293,0.2863,0.2043,0.0676,-0.1434",\ +"0.3957,0.3762,0.3488,0.3059,0.2238,0.0871,-0.1199",\ +"0.4230,0.4035,0.3723,0.3332,0.2512,0.1184,-0.0965",\ +"0.4660,0.4465,0.4191,0.3762,0.2941,0.1613,-0.0496",\ +"0.5324,0.5168,0.4973,0.4543,0.3723,0.2316,0.0285",\ +"0.6809,0.6613,0.6340,0.5910,0.5129,0.3645,0.1652",\ +"0.9113,0.8918,0.8605,0.8176,0.7395,0.5988,0.3879"); + } + } + } +pin(B_REN) { + direction : input ; + capacitance : 0.00381144 ; + max_transition : "0.5952" ; + related_power_pin : VDD; + related_ground_pin : VSS; + internal_power() { + when : "B_MEN"; + rise_power("scalar"){ + values (0.2069); + } + fall_power("scalar"){ + values (0.2018); + } + } + internal_power() { + when : "!B_MEN"; + rise_power("scalar"){ + values (0.0034); + } + fall_power("scalar"){ + values (0.0021); + } + } + timing() { + timing_type : setup_rising; + related_pin : "B_CLK"; + when : "B_MEN" + sdf_cond : "B_MEN" + + rise_constraint("SIG2SRAM_constraint_template") { + index_1("0.0080,0.0288,0.0616,0.1072,0.1920,0.3496,0.5952"); + index_2("0.0080,0.0288,0.0616,0.1072,0.1920,0.3496,0.5952"); + values ("-0.0770,-0.0574,-0.0262,0.0168,0.0949,0.2355,0.4582",\ +"-0.0965,-0.0770,-0.0457,-0.0027,0.0754,0.2160,0.4387",\ +"-0.1199,-0.1004,-0.0730,-0.0262,0.0520,0.1887,0.4113",\ +"-0.1590,-0.1434,-0.1160,-0.0730,0.0051,0.1457,0.3645",\ +"-0.2449,-0.2254,-0.1941,-0.1473,-0.0770,0.0676,0.2863",\ +"-0.3816,-0.3699,-0.3387,-0.2801,-0.2215,-0.0770,0.1457",\ +"-0.6121,-0.5926,-0.5613,-0.5145,-0.4363,-0.2996,-0.0730"); + } + + fall_constraint("SIG2SRAM_constraint_template") { + index_1("0.0080,0.0288,0.0616,0.1072,0.1920,0.3496,0.5952"); + index_2("0.0080,0.0288,0.0616,0.1072,0.1920,0.3496,0.5952"); + values ("0.1262,0.1457,0.1691,0.2121,0.2824,0.4191,0.6457",\ +"0.1105,0.1262,0.1496,0.1887,0.2629,0.3996,0.6262",\ +"0.0793,0.0949,0.1223,0.1652,0.2395,0.3684,0.5949",\ +"0.0363,0.0559,0.0793,0.1223,0.2004,0.3410,0.5520",\ +"-0.0457,-0.0262,0.0012,0.0441,0.1301,0.2629,0.4738",\ +"-0.1902,-0.1746,-0.1434,-0.1043,-0.0184,0.1223,0.3332",\ +"-0.4129,-0.3934,-0.3660,-0.3230,-0.2449,-0.1043,0.1105"); + } + } + + + timing() { + timing_type : hold_rising; + related_pin : "B_CLK"; + when : "B_MEN" + sdf_cond : "B_MEN" + + rise_constraint("SIG2SRAM_constraint_template") { + index_1("0.0080,0.0288,0.0616,0.1072,0.1920,0.3496,0.5952"); + index_2("0.0080,0.0288,0.0616,0.1072,0.1920,0.3496,0.5952"); + values ("0.4113,0.3918,0.3645,0.3176,0.2395,0.0988,-0.1238",\ +"0.4309,0.4113,0.3840,0.3371,0.2590,0.1184,-0.1043",\ +"0.4582,0.4387,0.4113,0.3645,0.2824,0.1457,-0.0770",\ +"0.5051,0.4816,0.4543,0.4074,0.3293,0.1887,-0.0340",\ +"0.5715,0.5598,0.5324,0.4895,0.4035,0.2512,0.0441",\ +"0.7043,0.7004,0.6730,0.6262,0.5402,0.3957,0.1809",\ +"0.9387,0.9270,0.8957,0.8527,0.7746,0.6262,0.4074"); + } + + fall_constraint("SIG2SRAM_constraint_template") { + index_1("0.0080,0.0288,0.0616,0.1072,0.1920,0.3496,0.5952"); + index_2("0.0080,0.0288,0.0616,0.1072,0.1920,0.3496,0.5952"); + values ("0.4152,0.3918,0.3645,0.3215,0.2395,0.1027,-0.1082",\ +"0.4309,0.4113,0.3801,0.3410,0.2590,0.1223,-0.0926",\ +"0.4582,0.4387,0.4074,0.3684,0.2863,0.1496,-0.0613",\ +"0.5012,0.4816,0.4504,0.4074,0.3293,0.1887,-0.0145",\ +"0.5715,0.5559,0.5285,0.4816,0.3996,0.2512,0.0598",\ +"0.7160,0.7004,0.6691,0.6262,0.5520,0.4035,0.2004",\ +"0.9387,0.9191,0.8957,0.8488,0.7707,0.6262,0.4113"); + } + } + } +pin(B_MEN) { + direction : input ; + capacitance : 0.00300347 ; + max_transition : "0.5952" ; + related_power_pin : VDD; + related_ground_pin : VSS; + internal_power() { + rise_power("scalar"){ + values (0.5519); + } + fall_power("scalar"){ + values (0.0392); + } + } + timing() { + timing_type : setup_rising; + related_pin : "B_CLK"; + + rise_constraint("SIG2SRAM_constraint_template") { + index_1("0.0080,0.0288,0.0616,0.1072,0.1920,0.3496,0.5952"); + index_2("0.0080,0.0288,0.0616,0.1072,0.1920,0.3496,0.5952"); + values ("0.3215,0.3449,0.3684,0.4113,0.4895,0.6301,0.8527",\ +"0.3059,0.3254,0.3527,0.3957,0.4738,0.6145,0.8371",\ +"0.2746,0.2941,0.3215,0.3645,0.4426,0.5871,0.8059",\ +"0.2316,0.2512,0.2785,0.3215,0.3996,0.5402,0.7629",\ +"0.1496,0.1730,0.1965,0.2395,0.3215,0.4660,0.6848",\ +"0.0090,0.0285,0.0598,0.1027,0.1809,0.3176,0.5402",\ +"-0.2098,-0.1902,-0.1668,-0.1199,-0.0418,0.0988,0.3137"); + } + + fall_constraint("SIG2SRAM_constraint_template") { + index_1("0.0080,0.0288,0.0616,0.1072,0.1920,0.3496,0.5952"); + index_2("0.0080,0.0288,0.0616,0.1072,0.1920,0.3496,0.5952"); + values ("0.4582,0.4738,0.5012,0.5363,0.6145,0.7395,0.9738",\ +"0.4387,0.4543,0.4816,0.5207,0.5910,0.7199,0.9582",\ +"0.4035,0.4230,0.4504,0.4855,0.5637,0.6887,0.9230",\ +"0.3645,0.3840,0.4074,0.4465,0.5285,0.6496,0.8840",\ +"0.2824,0.3020,0.3254,0.3645,0.4465,0.5715,0.7980",\ +"0.1418,0.1613,0.1887,0.2238,0.3020,0.4309,0.6496",\ +"-0.0770,-0.0574,-0.0301,0.0090,0.0910,0.2238,0.4191"); + } + } + + + timing() { + timing_type : hold_rising; + related_pin : "B_CLK"; + + rise_constraint("SIG2SRAM_constraint_template") { + index_1("0.0080,0.0288,0.0616,0.1072,0.1920,0.3496,0.5952"); + index_2("0.0080,0.0288,0.0616,0.1072,0.1920,0.3496,0.5952"); + values ("0.3762,0.3605,0.3293,0.2863,0.2043,0.0637,-0.1629",\ +"0.3996,0.3801,0.3488,0.3020,0.2238,0.0832,-0.1395",\ +"0.4230,0.4074,0.3723,0.3293,0.2473,0.1105,-0.1121",\ +"0.4621,0.4465,0.4152,0.3762,0.2941,0.1535,-0.0691",\ +"0.5441,0.5285,0.4973,0.4465,0.3684,0.2316,0.0090",\ +"0.6848,0.6652,0.6301,0.5910,0.5129,0.3605,0.1496",\ +"0.9074,0.8918,0.8566,0.8215,0.7395,0.5910,0.3723"); + } + + fall_constraint("SIG2SRAM_constraint_template") { + index_1("0.0080,0.0288,0.0616,0.1072,0.1920,0.3496,0.5952"); + index_2("0.0080,0.0288,0.0616,0.1072,0.1920,0.3496,0.5952"); + values ("0.3762,0.3605,0.3332,0.2863,0.2043,0.0715,-0.1395",\ +"0.3996,0.3762,0.3488,0.3059,0.2238,0.0910,-0.1199",\ +"0.4270,0.4035,0.3762,0.3332,0.2512,0.1184,-0.0965",\ +"0.4699,0.4504,0.4191,0.3762,0.2941,0.1613,-0.0496",\ +"0.5441,0.5285,0.4973,0.4543,0.3762,0.2355,0.0324",\ +"0.6770,0.6613,0.6340,0.5949,0.5207,0.3762,0.1652",\ +"0.9074,0.8918,0.8605,0.8176,0.7395,0.6027,0.3918"); + } + } + } + pin(B_CLK) { + direction : input; + capacitance : 0.00378957; + max_transition : "0.5952"; + clock : "true" ; + pin_func_type : active_rising ; + + timing () { + timing_type : "min_pulse_width"; + related_pin : "B_CLK"; + rise_constraint("CLKTRAN_constraint_template") { + index_1("0.008,0.5952"); + values("0.4,0.4"); + } + } + + related_power_pin : VDD; + related_ground_pin : VSS; + + internal_power() { + when : "!B_MEN & !B_WEN & !B_REN"; + rise_power("scalar"){ + values (0); + } + fall_power("scalar"){ + values (0); + } + } + internal_power() { + when : "!B_MEN & B_WEN & !B_REN"; + rise_power("scalar"){ + values (0.3989); + } + fall_power("scalar"){ + values (0); + } + } + internal_power() { + when : "B_MEN & B_WEN & !B_REN"; + rise_power("scalar"){ + values (21.7214); + } + fall_power("scalar"){ + values (0); + } + } + internal_power() { + when : "B_MEN & B_WEN & B_REN"; + rise_power("scalar"){ + values (24.3851); + } + fall_power("scalar"){ + values (0); + } + } + internal_power() { + when : "B_MEN & !B_WEN & B_REN"; + rise_power("scalar"){ + values (17.0893); + } + fall_power("scalar"){ + values (0); + } + } + internal_power() { + when : "!B_MEN & !B_WEN & B_REN"; + rise_power("scalar"){ + values (0.2951); + } + fall_power("scalar"){ + values (0); + } + } + internal_power() { + when : "!B_MEN & B_WEN & B_REN"; + rise_power("scalar"){ + values (0.9866); + } + fall_power("scalar"){ + values (0); + } + } + internal_power() { + when : "B_MEN & !B_WEN & !B_REN"; + rise_power("scalar"){ + values (0); + } + fall_power("scalar"){ + values (0); + } + } + } + bus(B_DIN) { + bus_type : D_31_0; + direction : input ; + capacitance : 0.00460366 ; + memory_write() { + address : B_ADDR ; + clocked_on : B_CLK; + } + + max_transition : "0.5952" ; + pin(B_DIN[31:0]) { + related_power_pin : VDD; + related_ground_pin : VSS; + internal_power() { + when : "B_MEN"; + rise_power("scalar"){ + values (0.2888); + } + fall_power("scalar"){ + values (0.5290); + } + } + internal_power() { + when : "!B_MEN"; + rise_power("scalar"){ + values (0.0897); + } + fall_power("scalar"){ + values (0.0306); + } + } + } + timing() { + timing_type : setup_rising; + related_pin : "B_CLK"; + when : "(B_WEN & B_MEN)"; + sdf_cond : "B_W_ACCESS"; + + rise_constraint("SIG2SRAM_constraint_template") { + index_1("0.0080,0.0288,0.0616,0.1072,0.1920,0.3496,0.5952"); + index_2("0.0080,0.0288,0.0616,0.1072,0.1920,0.3496,0.5952"); + values ("-0.8824,-0.8629,-0.8365,-0.7916,-0.7125,-0.5689,-0.3453",\ +"-0.8903,-0.8708,-0.8444,-0.7995,-0.7204,-0.5769,-0.3532",\ +"-0.8995,-0.8799,-0.8536,-0.8087,-0.7296,-0.5860,-0.3624",\ +"-0.9145,-0.8949,-0.8686,-0.8236,-0.7445,-0.6010,-0.3773",\ +"-0.9368,-0.9173,-0.8909,-0.8460,-0.7669,-0.6234,-0.3997",\ +"-0.9804,-0.9609,-0.9345,-0.8896,-0.8105,-0.6670,-0.4433",\ +"-1.0496,-1.0301,-1.0037,-0.9588,-0.8797,-0.7361,-0.5125"); + } + + fall_constraint("SIG2SRAM_constraint_template") { + index_1("0.0080,0.0288,0.0616,0.1072,0.1920,0.3496,0.5952"); + index_2("0.0080,0.0288,0.0616,0.1072,0.1920,0.3496,0.5952"); + values ("-0.8082,-0.7906,-0.7623,-0.7232,-0.6402,-0.5045,-0.2916",\ +"-0.8161,-0.7985,-0.7702,-0.7312,-0.6481,-0.5124,-0.2995",\ +"-0.8253,-0.8077,-0.7794,-0.7403,-0.6573,-0.5215,-0.3087",\ +"-0.8402,-0.8227,-0.7943,-0.7553,-0.6723,-0.5365,-0.3236",\ +"-0.8626,-0.8450,-0.8167,-0.7777,-0.6946,-0.5589,-0.3460",\ +"-0.9062,-0.8886,-0.8603,-0.8213,-0.7382,-0.6025,-0.3896",\ +"-0.9754,-0.9578,-0.9295,-0.8904,-0.8074,-0.6717,-0.4588"); + } + } + + timing() { + timing_type : hold_rising; + related_pin : "B_CLK"; + when : "(B_WEN & B_MEN)"; + sdf_cond : "B_W_ACCESS"; + + rise_constraint("SIG2SRAM_constraint_template") { + index_1("0.0080,0.0288,0.0616,0.1072,0.1920,0.3496,0.5952"); + index_2("0.0080,0.0288,0.0616,0.1072,0.1920,0.3496,0.5952"); + values ("0.9949,0.9744,0.9470,0.9041,0.8269,0.6834,0.4558",\ +"1.0028,0.9823,0.9550,0.9120,0.8348,0.6913,0.4637",\ +"1.0119,0.9914,0.9641,0.9211,0.8440,0.7004,0.4729",\ +"1.0269,1.0064,0.9791,0.9361,0.8590,0.7154,0.4879",\ +"1.0493,1.0288,1.0015,0.9585,0.8813,0.7378,0.5102",\ +"1.0929,1.0724,1.0451,1.0021,0.9249,0.7814,0.5538",\ +"1.1621,1.1416,1.1142,1.0713,0.9941,0.8506,0.6230"); + } + + fall_constraint("SIG2SRAM_constraint_template") { + index_1("0.0080,0.0288,0.0616,0.1072,0.1920,0.3496,0.5952"); + index_2("0.0080,0.0288,0.0616,0.1072,0.1920,0.3496,0.5952"); + values ("0.9129,0.8933,0.8670,0.8279,0.7449,0.6082,0.3992",\ +"0.9208,0.9012,0.8749,0.8358,0.7528,0.6161,0.4071",\ +"0.9299,0.9104,0.8840,0.8450,0.7619,0.6252,0.4163",\ +"0.9449,0.9254,0.8990,0.8599,0.7769,0.6402,0.4312",\ +"0.9673,0.9477,0.9214,0.8823,0.7993,0.6626,0.4536",\ +"1.0109,0.9913,0.9650,0.9259,0.8429,0.7062,0.4972",\ +"1.0801,1.0605,1.0342,0.9951,0.9121,0.7754,0.5664"); + } + } + } + +bus(B_DOUT) { + + bus_type : D_31_0; + direction : output ; + capacitance : 0 ; + max_capacitance : 0.064 ; + memory_read() { + address : B_ADDR ; + } + pin(B_DOUT[31:0]) { + related_power_pin : VDD; + related_ground_pin : VSS; + internal_power() { + rise_power("scalar") { + values (0); + } + fall_power("scalar") { + values (0); + } + } + } + timing() { + related_pin : "B_CLK"; + timing_type : rising_edge ; + timing_sense : non_unate ; + + cell_rise(SIG2SRAM_delay_template) { + index_1("0.0080,0.0288,0.0616,0.1072,0.1920,0.3496,0.5952"); + index_2("0.0008,0.0014,0.0051,0.0100,0.0339,0.0640"); + values ("5.2125,5.2152,5.2276,5.2418,5.2940,5.3520",\ +"5.2265,5.2291,5.2416,5.2557,5.3079,5.3659",\ +"5.2363,5.2389,5.2514,5.2655,5.3177,5.3757",\ +"5.2496,5.2522,5.2647,5.2788,5.3310,5.3890",\ +"5.2729,5.2755,5.2880,5.3021,5.3543,5.4123",\ +"5.3176,5.3202,5.3327,5.3468,5.3991,5.4570",\ +"5.3849,5.3875,5.4000,5.4141,5.4663,5.5243"); + } + cell_fall(SIG2SRAM_delay_template) { + index_1("0.0080,0.0288,0.0616,0.1072,0.1920,0.3496,0.5952"); + index_2("0.0008,0.0014,0.0051,0.0100,0.0339,0.0640"); + values ("5.1008,5.1030,5.1128,5.1242,5.1674,5.2119",\ +"5.1147,5.1169,5.1267,5.1381,5.1813,5.2258",\ +"5.1246,5.1267,5.1365,5.1479,5.1912,5.2357",\ +"5.1379,5.1400,5.1498,5.1612,5.2045,5.2490",\ +"5.1612,5.1633,5.1731,5.1845,5.2277,5.2723",\ +"5.2059,5.2081,5.2178,5.2292,5.2725,5.3170",\ +"5.2732,5.2753,5.2851,5.2965,5.3398,5.3843"); + } + + rise_transition(SRAM_load_template) { + index_1("0.0008,0.0014,0.0051,0.0100,0.0339,0.0640"); + values ("0.0560,0.0583,0.0696,0.0816,0.1519,0.2335"); + } + fall_transition(SRAM_load_template) { + index_1("0.0008,0.0014,0.0051,0.0100,0.0339,0.0640"); + values ("0.0428,0.0445,0.0538,0.0658,0.1181,0.1751"); + } + } +} +cell_leakage_power : 238.2893; +} +} diff --git a/flow/platforms/ihp-sg13g2/lib/RM_IHPSG13_2P_64x32_c2_typ_1p20V_25C.lib b/flow/platforms/ihp-sg13g2/lib/RM_IHPSG13_2P_64x32_c2_typ_1p20V_25C.lib new file mode 100644 index 0000000000..45b4b8f641 --- /dev/null +++ b/flow/platforms/ihp-sg13g2/lib/RM_IHPSG13_2P_64x32_c2_typ_1p20V_25C.lib @@ -0,0 +1,1380 @@ +/* ------------------------------------------------------*/ +/**/ +/* Copyright 2023 IHP PDK Authors*/ +/**/ +/* Licensed under the Apache License, Version 2.0 (the "License");*/ +/* you may not use this file except in compliance with the License.*/ +/* You may obtain a copy of the License at*/ +/* */ +/* https://www.apache.org/licenses/LICENSE-2.0*/ +/* */ +/* Unless required by applicable law or agreed to in writing, software*/ +/* distributed under the License is distributed on an "AS IS" BASIS,*/ +/* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.*/ +/* See the License for the specific language governing permissions and*/ +/* limitations under the License.*/ +/* */ +/* Generated on Thu Jun 12 11:08:45 2025 */ +/* */ +/* ------------------------------------------------------ */ +library(RM_IHPSG13_2P_64x32_c2_typ_1p20V_25C) { + technology (cmos) ; + delay_model : table_lookup ; + define ("add_pg_pin_to_lib", "library", "boolean"); + add_pg_pin_to_lib : true; + voltage_map ( VDD, 1.20); + voltage_map ( VDDARRAY, 1.20); + voltage_map ( VSS, 0.000000 ); + + date : "Thu Jun 12 11:08:38 2025" ; + comment : "IHP Microelectronics GmbH, 2023" ; + revision : 1.0.0 ; + simulation : true ; + nom_process : 1 ; + nom_temperature : 25 ; + nom_voltage : 1.20 ; + + operating_conditions("typ_1p20V_25C"){ + process : 1 ; + temperature : 25 ; + voltage : 1.20 ; + tree_type : "balanced_tree" ; + } + + default_operating_conditions : typ_1p20V_25C ; + default_max_transition : 1.0 ; + default_fanout_load : 1.0 ; + default_inout_pin_cap : 0.0 ; + default_input_pin_cap : 0.0 ; + default_output_pin_cap : 0.0 ; + default_cell_leakage_power : 0.0 ; + default_leakage_power_density : 0.0 ; + + slew_lower_threshold_pct_rise : 30 ; + slew_upper_threshold_pct_rise : 70 ; + input_threshold_pct_fall : 50 ; + output_threshold_pct_fall : 50 ; + input_threshold_pct_rise : 50 ; + output_threshold_pct_rise : 50 ; + slew_lower_threshold_pct_fall : 30 ; + slew_upper_threshold_pct_fall : 70 ; + slew_derate_from_library : 0.5; + k_volt_cell_leakage_power : 0.0 ; + k_temp_cell_leakage_power : 0.0 ; + k_process_cell_leakage_power : 0.0 ; + k_volt_internal_power : 0.0 ; + k_temp_internal_power : 0.0 ; + k_process_internal_power : 0.0 ; + + capacitive_load_unit (1,pf) ; + voltage_unit : "1V" ; + current_unit : "1uA" ; + time_unit : "1ns" ; + leakage_power_unit : "1nW" ; + pulling_resistance_unit : "1kohm"; + /* + ------------------------------------------------------------------------------------------ + implicit units overview: + cell_area unit : "um" + internal_power unit : "1e-12 * J/toggle = 1 * uW/MHz" + (capacitive_load_unit * voltage_unit^2) per toggle event + ------------------------------------------------------------------------------------------ + */ + library_features(report_delay_calculation); + define_cell_area (pad_drivers,pad_driver_sites) ; + + lu_table_template(CLKTRAN_constraint_template) { + variable_1 : constrained_pin_transition; + index_1 ( "0.010, 0.050, 0.200, 0.400, 1.000" ); + } + lu_table_template(SRAM_load_template) { + variable_1 : total_output_net_capacitance; + index_1 ( "0.0008,0.0014,0.0051,0.0100,0.0339,0.0640" ); + } + lu_table_template(SIG2SRAM_constraint_template) { + variable_1 : related_pin_transition; + variable_2 : constrained_pin_transition; + index_1 ( "0.0056,0.0232,0.0400,0.0728,0.1280,0.2440,0.4760" ); + index_2 ( "0.0056,0.0232,0.0400,0.0728,0.1280,0.2440,0.4760" ); + } + + lu_table_template(SIG2SRAM_delay_template) { + variable_1 : input_net_transition; + variable_2 : total_output_net_capacitance; + index_1 ( "0.0056,0.0232,0.0400,0.0728,0.1280,0.2440,0.4760" ); + index_2 ( "0.0008,0.0014,0.0051,0.0100,0.0339,0.0640" ); + } + + type (D_31_0) { + base_type : array; + data_type : bit; + bit_width : 32; + bit_from : 31; + bit_to : 0; + downto : true; + } + + type (A_5_0) { + base_type : array; + data_type : bit; + bit_width : 6; + bit_from : 5; + bit_to : 0; + downto : true; + } + +cell(RM_IHPSG13_2P_64x32_c2) { +pg_pin (VDD) { + pg_type : primary_power; + voltage_name : VDD; +} +pg_pin (VDDARRAY) { + pg_type : primary_power; + voltage_name : VDDARRAY; +} +pg_pin (VSS) { + pg_type : primary_ground; + voltage_name : VSS; +} + +memory() { + type : ram; + address_width : 6; + word_width : 32; +} + +interface_timing : false; +bus_naming_style : "%s[%d]" ; +area : 52620.8821 ; + + pin(A_DLY) { + direction : input ; + capacitance : 0.00401111 ; + max_transition : "1" ; + related_power_pin : VDD; + related_ground_pin : VSS; + internal_power() { + rise_power("scalar") { + values (0); + } + fall_power("scalar") { + values (0); + } + } + } + +bus(A_ADDR) { + bus_type : A_5_0; + direction : input ; + capacitance : 0.0121077 ; + pin(A_ADDR[0]) { + capacitance : 0.00568653 ; + } + pin(A_ADDR[1]) { + capacitance : 0.00767263 ; + } + pin(A_ADDR[2]) { + capacitance : 0.0105079 ; + } + pin(A_ADDR[3]) { + capacitance : 0.0068178 ; + } + pin(A_ADDR[4]) { + capacitance : 0.00624497 ; + } + max_transition : "0.476" ; + pin(A_ADDR[5:0]) { + related_power_pin : VDD; + related_ground_pin : VSS; + internal_power() { + when : "A_MEN"; + rise_power("scalar"){ + values (0.0394); + } + fall_power("scalar"){ + values (0.0421); + } + } + internal_power() { + when : "!A_MEN"; + rise_power("scalar"){ + values (0.0164); + } + fall_power("scalar"){ + values (0.0008); + } + } + } + timing() { + timing_type : setup_rising; + related_pin : "A_CLK"; + when : "((A_WEN | A_REN)& A_MEN)" + sdf_cond : "A_RW_ACCESS" + + rise_constraint("SIG2SRAM_constraint_template") { + index_1("0.0056,0.0232,0.0400,0.0728,0.1280,0.2440,0.4760"); + index_2("0.0056,0.0232,0.0400,0.0728,0.1280,0.2440,0.4760"); + values ("-0.4168,-0.3973,-0.3855,-0.3543,-0.3074,-0.2020,-0.0027",\ +"-0.4324,-0.4129,-0.4012,-0.3699,-0.3191,-0.2176,-0.0184",\ +"-0.4441,-0.4285,-0.4129,-0.3816,-0.3309,-0.2293,-0.0301",\ +"-0.4793,-0.4598,-0.4441,-0.4129,-0.3660,-0.2645,-0.0652",\ +"-0.5223,-0.5066,-0.4910,-0.4598,-0.4129,-0.3074,-0.1121",\ +"-0.6199,-0.6082,-0.5926,-0.5613,-0.5145,-0.4129,-0.2137",\ +"-0.8191,-0.8074,-0.7840,-0.7566,-0.7098,-0.6082,-0.4051"); + } + + fall_constraint("SIG2SRAM_constraint_template") { + index_1("0.0056,0.0232,0.0400,0.0728,0.1280,0.2440,0.4760"); + index_2("0.0056,0.0232,0.0400,0.0728,0.1280,0.2440,0.4760"); + values ("-0.3309,-0.3113,-0.2996,-0.2684,-0.2176,-0.1238,0.0637",\ +"-0.3465,-0.3309,-0.3152,-0.2840,-0.2332,-0.1395,0.0480",\ +"-0.3582,-0.3426,-0.3270,-0.2996,-0.2488,-0.1512,0.0324",\ +"-0.3895,-0.3738,-0.3582,-0.3309,-0.2801,-0.1863,0.0051",\ +"-0.4363,-0.4207,-0.4051,-0.3777,-0.3230,-0.2293,-0.0379",\ +"-0.5379,-0.5223,-0.5066,-0.4793,-0.4285,-0.3309,-0.1434",\ +"-0.7332,-0.7176,-0.7020,-0.6746,-0.6238,-0.5262,-0.3387"); + } + } + + + timing() { + timing_type : hold_rising; + related_pin : "A_CLK"; + when : "((A_WEN | A_REN)& A_MEN)" + sdf_cond : "A_RW_ACCESS" + + rise_constraint("SIG2SRAM_constraint_template") { + index_1("0.0056,0.0232,0.0400,0.0728,0.1280,0.2440,0.4760"); + index_2("0.0056,0.0232,0.0400,0.0728,0.1280,0.2440,0.4760"); + values ("0.5246,0.5051,0.4895,0.4582,0.4113,0.3059,0.1066",\ +"0.5402,0.5207,0.5051,0.4777,0.4270,0.3215,0.1223",\ +"0.5520,0.5324,0.5168,0.4895,0.4387,0.3371,0.1340",\ +"0.5832,0.5676,0.5520,0.5207,0.4738,0.3684,0.1691",\ +"0.6301,0.6105,0.5949,0.5676,0.5168,0.4113,0.2160",\ +"0.7316,0.7121,0.7004,0.6691,0.6223,0.5168,0.3176",\ +"0.9270,0.9230,0.8957,0.8645,0.8137,0.7121,0.5168"); + } + + fall_constraint("SIG2SRAM_constraint_template") { + index_1("0.0056,0.0232,0.0400,0.0728,0.1280,0.2440,0.4760"); + index_2("0.0056,0.0232,0.0400,0.0728,0.1280,0.2440,0.4760"); + values ("0.4309,0.4152,0.4035,0.3684,0.3215,0.2277,0.0363",\ +"0.4465,0.4309,0.4152,0.3879,0.3371,0.2395,0.0559",\ +"0.4582,0.4426,0.4309,0.3996,0.3488,0.2551,0.0715",\ +"0.4934,0.4777,0.4621,0.4348,0.3840,0.2863,0.0988",\ +"0.5363,0.5207,0.5051,0.4777,0.4270,0.3332,0.1418",\ +"0.6379,0.6262,0.6105,0.5793,0.5324,0.4348,0.2434",\ +"0.8332,0.8215,0.8059,0.7707,0.7238,0.6301,0.4387"); + } + } +} +pin(A_WEN) { + direction : input ; + capacitance : 0.00324098 ; + max_transition : "0.476" ; + related_power_pin : VDD; + related_ground_pin : VSS; + internal_power() { + when : "A_MEN"; + rise_power("scalar"){ + values (0.0323); + } + fall_power("scalar"){ + values (0.0552); + } + } + internal_power() { + when : "!A_MEN"; + rise_power("scalar"){ + values (0.0050); + } + fall_power("scalar"){ + values (0.0050); + } + } + timing() { + timing_type : setup_rising; + related_pin : "A_CLK"; + when : "A_MEN" + sdf_cond : "A_MEN" + + rise_constraint("SIG2SRAM_constraint_template") { + index_1("0.0056,0.0232,0.0400,0.0728,0.1280,0.2440,0.4760"); + index_2("0.0056,0.0232,0.0400,0.0728,0.1280,0.2440,0.4760"); + values ("0.2043,0.2199,0.2316,0.2629,0.3059,0.4113,0.6066",\ +"0.1887,0.2043,0.2160,0.2473,0.2941,0.3957,0.5949",\ +"0.1691,0.1848,0.2004,0.2316,0.2785,0.3801,0.5754",\ +"0.1379,0.1574,0.1691,0.2004,0.2473,0.3527,0.5480",\ +"0.0910,0.1066,0.1223,0.1535,0.2004,0.2980,0.4973",\ +"-0.0105,0.0051,0.0207,0.0520,0.0949,0.2004,0.3957",\ +"-0.2059,-0.1902,-0.1746,-0.1473,-0.1004,0.0051,0.2004"); + } + + fall_constraint("SIG2SRAM_constraint_template") { + index_1("0.0056,0.0232,0.0400,0.0728,0.1280,0.2440,0.4760"); + index_2("0.0056,0.0232,0.0400,0.0728,0.1280,0.2440,0.4760"); + values ("0.2941,0.3098,0.3215,0.3488,0.4035,0.4973,0.6887",\ +"0.2785,0.2941,0.3059,0.3332,0.3840,0.4816,0.6691",\ +"0.2629,0.2785,0.2902,0.3176,0.3684,0.4660,0.6535",\ +"0.2316,0.2473,0.2590,0.2863,0.3410,0.4348,0.6262",\ +"0.1848,0.2004,0.2121,0.2395,0.2902,0.3879,0.5754",\ +"0.0832,0.0988,0.1105,0.1379,0.1809,0.2746,0.4699",\ +"-0.1121,-0.0965,-0.0848,-0.0535,-0.0066,0.0910,0.2824"); + } + } + + + timing() { + timing_type : hold_rising; + related_pin : "A_CLK"; + when : "A_MEN" + sdf_cond : "A_MEN" + + rise_constraint("SIG2SRAM_constraint_template") { + index_1("0.0056,0.0232,0.0400,0.0728,0.1280,0.2440,0.4760"); + index_2("0.0056,0.0232,0.0400,0.0728,0.1280,0.2440,0.4760"); + values ("0.2473,0.2316,0.2160,0.1887,0.1379,0.0363,-0.1629",\ +"0.2629,0.2473,0.2316,0.2043,0.1535,0.0520,-0.1473",\ +"0.2785,0.2590,0.2434,0.2160,0.1652,0.0676,-0.1355",\ +"0.3098,0.2941,0.2785,0.2473,0.1965,0.0910,-0.1043",\ +"0.3527,0.3371,0.3215,0.2941,0.2434,0.1418,-0.0574",\ +"0.4582,0.4426,0.4270,0.3957,0.3488,0.2434,0.0480",\ +"0.6535,0.6379,0.6184,0.5910,0.5402,0.4426,0.2434"); + } + + fall_constraint("SIG2SRAM_constraint_template") { + index_1("0.0056,0.0232,0.0400,0.0728,0.1280,0.2440,0.4760"); + index_2("0.0056,0.0232,0.0400,0.0728,0.1280,0.2440,0.4760"); + values ("0.2395,0.2238,0.2121,0.1809,0.1301,0.0324,-0.1551",\ +"0.2551,0.2395,0.2277,0.1965,0.1457,0.0480,-0.1395",\ +"0.2668,0.2551,0.2395,0.2082,0.1574,0.0637,-0.1277",\ +"0.3020,0.2863,0.2707,0.2395,0.1887,0.0910,-0.0965",\ +"0.3449,0.3293,0.3176,0.2863,0.2355,0.1379,-0.0496",\ +"0.4504,0.4348,0.4191,0.3879,0.3371,0.2395,0.0559",\ +"0.6457,0.6301,0.6145,0.5871,0.5324,0.4309,0.2512"); + } + } + } +pin(A_REN) { + direction : input ; + capacitance : 0.00381634 ; + max_transition : "0.476" ; + related_power_pin : VDD; + related_ground_pin : VSS; + internal_power() { + when : "A_MEN"; + rise_power("scalar"){ + values (0.2409); + } + fall_power("scalar"){ + values (0.0203); + } + } + internal_power() { + when : "!A_MEN"; + rise_power("scalar"){ + values (0.0057); + } + fall_power("scalar"){ + values (0.0029); + } + } + timing() { + timing_type : setup_rising; + related_pin : "A_CLK"; + when : "A_MEN" + sdf_cond : "A_MEN" + + rise_constraint("SIG2SRAM_constraint_template") { + index_1("0.0056,0.0232,0.0400,0.0728,0.1280,0.2440,0.4760"); + index_2("0.0056,0.0232,0.0400,0.0728,0.1280,0.2440,0.4760"); + values ("-0.0301,-0.0145,0.0012,0.0324,0.0793,0.1809,0.3762",\ +"-0.0457,-0.0301,-0.0145,0.0168,0.0637,0.1613,0.3605",\ +"-0.0574,-0.0418,-0.0262,0.0051,0.0520,0.1496,0.3449",\ +"-0.0926,-0.0730,-0.0574,-0.0262,0.0207,0.1184,0.3137",\ +"-0.1395,-0.1238,-0.1082,-0.0770,-0.0301,0.0715,0.2707",\ +"-0.2410,-0.2254,-0.2098,-0.1746,-0.1355,-0.0340,0.1652",\ +"-0.4402,-0.4207,-0.4051,-0.3738,-0.3270,-0.2293,-0.0340"); + } + + fall_constraint("SIG2SRAM_constraint_template") { + index_1("0.0056,0.0232,0.0400,0.0728,0.1280,0.2440,0.4760"); + index_2("0.0056,0.0232,0.0400,0.0728,0.1280,0.2440,0.4760"); + values ("0.0988,0.1145,0.1262,0.1535,0.2043,0.3020,0.4855",\ +"0.0832,0.0988,0.1105,0.1418,0.1848,0.2824,0.4738",\ +"0.0676,0.0832,0.0949,0.1262,0.1730,0.2668,0.4621",\ +"0.0402,0.0559,0.0676,0.0988,0.1457,0.2434,0.4191",\ +"-0.0105,0.0012,0.0168,0.0480,0.0988,0.1965,0.3840",\ +"-0.1160,-0.0965,-0.0848,-0.0535,-0.0066,0.0988,0.2824",\ +"-0.3113,-0.2957,-0.2801,-0.2527,-0.2059,-0.1043,0.0832"); + } + } + + + timing() { + timing_type : hold_rising; + related_pin : "A_CLK"; + when : "A_MEN" + sdf_cond : "A_MEN" + + rise_constraint("SIG2SRAM_constraint_template") { + index_1("0.0056,0.0232,0.0400,0.0728,0.1280,0.2440,0.4760"); + index_2("0.0056,0.0232,0.0400,0.0728,0.1280,0.2440,0.4760"); + values ("0.2707,0.2551,0.2395,0.2121,0.1613,0.0598,-0.1395",\ +"0.2863,0.2707,0.2551,0.2238,0.1730,0.0715,-0.1238",\ +"0.2980,0.2824,0.2668,0.2395,0.1887,0.0871,-0.1121",\ +"0.3332,0.3176,0.3020,0.2707,0.2199,0.1184,-0.0809",\ +"0.3762,0.3605,0.3449,0.3176,0.2668,0.1613,-0.0340",\ +"0.4816,0.4621,0.4504,0.4191,0.3723,0.2629,0.0715",\ +"0.6770,0.6613,0.6418,0.6184,0.5637,0.4699,0.2629"); + } + + fall_constraint("SIG2SRAM_constraint_template") { + index_1("0.0056,0.0232,0.0400,0.0728,0.1280,0.2440,0.4760"); + index_2("0.0056,0.0232,0.0400,0.0728,0.1280,0.2440,0.4760"); + values ("0.2590,0.2434,0.2316,0.2004,0.1457,0.0520,-0.1355",\ +"0.2746,0.2590,0.2434,0.2160,0.1613,0.0676,-0.1199",\ +"0.2863,0.2707,0.2590,0.2277,0.1730,0.0832,-0.1082",\ +"0.3215,0.3059,0.2902,0.2590,0.2082,0.1105,-0.0770",\ +"0.3645,0.3488,0.3332,0.3059,0.2551,0.1535,-0.0340",\ +"0.4699,0.4543,0.4387,0.4074,0.3605,0.2551,0.0715",\ +"0.6652,0.6496,0.6340,0.6027,0.5520,0.4621,0.2707"); + } + } + } +pin(A_MEN) { + direction : input ; + capacitance : 0.00309605 ; + max_transition : "0.476" ; + related_power_pin : VDD; + related_ground_pin : VSS; + internal_power() { + rise_power("scalar"){ + values (0.0869); + } + fall_power("scalar"){ + values (0.0336); + } + } + timing() { + timing_type : setup_rising; + related_pin : "A_CLK"; + + rise_constraint("SIG2SRAM_constraint_template") { + index_1("0.0056,0.0232,0.0400,0.0728,0.1280,0.2440,0.4760"); + index_2("0.0056,0.0232,0.0400,0.0728,0.1280,0.2440,0.4760"); + values ("0.2043,0.2199,0.2316,0.2668,0.3098,0.4152,0.6066",\ +"0.1887,0.2043,0.2199,0.2512,0.2941,0.3996,0.5949",\ +"0.1730,0.1887,0.2043,0.2355,0.2824,0.3840,0.5793",\ +"0.1418,0.1574,0.1730,0.2043,0.2512,0.3566,0.5480",\ +"0.0949,0.1105,0.1262,0.1574,0.2043,0.3020,0.5051",\ +"-0.0066,0.0090,0.0246,0.0520,0.0988,0.2043,0.3996",\ +"-0.2020,-0.1863,-0.1746,-0.1434,-0.0965,0.0090,0.2082"); + } + + fall_constraint("SIG2SRAM_constraint_template") { + index_1("0.0056,0.0232,0.0400,0.0728,0.1280,0.2440,0.4760"); + index_2("0.0056,0.0232,0.0400,0.0728,0.1280,0.2440,0.4760"); + values ("0.2980,0.3137,0.3254,0.3527,0.4035,0.5012,0.6887",\ +"0.2824,0.2980,0.3098,0.3371,0.3879,0.4855,0.6730",\ +"0.2668,0.2824,0.2941,0.3215,0.3723,0.4699,0.6574",\ +"0.2355,0.2473,0.2629,0.2902,0.3410,0.4387,0.6262",\ +"0.1887,0.2004,0.2160,0.2395,0.2941,0.3918,0.5793",\ +"0.0871,0.1027,0.1145,0.1418,0.1848,0.2746,0.4816",\ +"-0.1082,-0.0965,-0.0809,-0.0496,-0.0027,0.0949,0.2863"); + } + } + + + timing() { + timing_type : hold_rising; + related_pin : "A_CLK"; + + rise_constraint("SIG2SRAM_constraint_template") { + index_1("0.0056,0.0232,0.0400,0.0728,0.1280,0.2440,0.4760"); + index_2("0.0056,0.0232,0.0400,0.0728,0.1280,0.2440,0.4760"); + values ("0.2512,0.2355,0.2199,0.1926,0.1418,0.0402,-0.1590",\ +"0.2668,0.2512,0.2355,0.2082,0.1574,0.0559,-0.1434",\ +"0.2824,0.2629,0.2512,0.2199,0.1691,0.0715,-0.1316",\ +"0.3137,0.2980,0.2824,0.2512,0.2004,0.0988,-0.0965",\ +"0.3566,0.3410,0.3254,0.2980,0.2473,0.1418,-0.0535",\ +"0.4621,0.4426,0.4309,0.3996,0.3527,0.2473,0.0520",\ +"0.6574,0.6418,0.6262,0.5949,0.5441,0.4465,0.2473"); + } + + fall_constraint("SIG2SRAM_constraint_template") { + index_1("0.0056,0.0232,0.0400,0.0728,0.1280,0.2440,0.4760"); + index_2("0.0056,0.0232,0.0400,0.0728,0.1280,0.2440,0.4760"); + values ("0.2395,0.2238,0.2121,0.1809,0.1301,0.0324,-0.1551",\ +"0.2551,0.2434,0.2277,0.1965,0.1457,0.0480,-0.1395",\ +"0.2707,0.2551,0.2395,0.2082,0.1574,0.0637,-0.1277",\ +"0.3020,0.2863,0.2707,0.2434,0.1926,0.0910,-0.0965",\ +"0.3449,0.3332,0.3176,0.2863,0.2355,0.1379,-0.0496",\ +"0.4504,0.4348,0.4230,0.3918,0.3410,0.2434,0.0559",\ +"0.6457,0.6301,0.6145,0.5910,0.5324,0.4387,0.2512"); + } + } + } + pin(A_CLK) { + direction : input; + capacitance : 0.00380014; + max_transition : "0.476"; + clock : "true" ; + pin_func_type : active_rising ; + + timing () { + timing_type : "min_pulse_width"; + related_pin : "A_CLK"; + rise_constraint("CLKTRAN_constraint_template") { + index_1("0.0056,0.476"); + values("0.21,0.21"); + } + } + + related_power_pin : VDD; + related_ground_pin : VSS; + + internal_power() { + when : "!A_MEN & !A_WEN & !A_REN"; + rise_power("scalar"){ + values (0); + } + fall_power("scalar"){ + values (0); + } + } + internal_power() { + when : "!A_MEN & A_WEN & !A_REN"; + rise_power("scalar"){ + values (0.9807); + } + fall_power("scalar"){ + values (0); + } + } + internal_power() { + when : "A_MEN & A_WEN & !A_REN"; + rise_power("scalar"){ + values (26.4624); + } + fall_power("scalar"){ + values (0); + } + } + internal_power() { + when : "A_MEN & A_WEN & A_REN"; + rise_power("scalar"){ + values (29.5662); + } + fall_power("scalar"){ + values (0); + } + } + internal_power() { + when : "A_MEN & !A_WEN & A_REN"; + rise_power("scalar"){ + values (20.3627); + } + fall_power("scalar"){ + values (0); + } + } + internal_power() { + when : "!A_MEN & !A_WEN & A_REN"; + rise_power("scalar"){ + values (0.2739); + } + fall_power("scalar"){ + values (0); + } + } + internal_power() { + when : "!A_MEN & A_WEN & A_REN"; + rise_power("scalar"){ + values (1.2089); + } + fall_power("scalar"){ + values (0); + } + } + internal_power() { + when : "A_MEN & !A_WEN & !A_REN"; + rise_power("scalar"){ + values (0); + } + fall_power("scalar"){ + values (0); + } + } + } + bus(A_DIN) { + bus_type : D_31_0; + direction : input ; + capacitance : 0.00500744 ; + memory_write() { + address : A_ADDR ; + clocked_on : A_CLK; + } + + max_transition : "0.476" ; + pin(A_DIN[31:0]) { + related_power_pin : VDD; + related_ground_pin : VSS; + internal_power() { + when : "A_MEN"; + rise_power("scalar"){ + values (0.1195); + } + fall_power("scalar"){ + values (0.0483); + } + } + internal_power() { + when : "!A_MEN"; + rise_power("scalar"){ + values (0.1113); + } + fall_power("scalar"){ + values (0.0477); + } + } + } + timing() { + timing_type : setup_rising; + related_pin : "A_CLK"; + when : "(A_WEN & A_MEN)"; + sdf_cond : "A_W_ACCESS"; + + rise_constraint("SIG2SRAM_constraint_template") { + index_1("0.0056,0.0232,0.0400,0.0728,0.1280,0.2440,0.4760"); + index_2("0.0056,0.0232,0.0400,0.0728,0.1280,0.2440,0.4760"); + values ("-0.4895,-0.4729,-0.4603,-0.4280,-0.3821,-0.2796,-0.0872",\ +"-0.4946,-0.4779,-0.4653,-0.4330,-0.3871,-0.2846,-0.0922",\ +"-0.4990,-0.4824,-0.4697,-0.4375,-0.3916,-0.2891,-0.0967",\ +"-0.5081,-0.4915,-0.4789,-0.4466,-0.4007,-0.2982,-0.1058",\ +"-0.5153,-0.4987,-0.4861,-0.4538,-0.4079,-0.3054,-0.1130",\ +"-0.5450,-0.5284,-0.5157,-0.4835,-0.4376,-0.3351,-0.1427",\ +"-0.6031,-0.5865,-0.5738,-0.5416,-0.4957,-0.3931,-0.2007"); + } + + fall_constraint("SIG2SRAM_constraint_template") { + index_1("0.0056,0.0232,0.0400,0.0728,0.1280,0.2440,0.4760"); + index_2("0.0056,0.0232,0.0400,0.0728,0.1280,0.2440,0.4760"); + values ("-0.4476,-0.4329,-0.4192,-0.3899,-0.3392,-0.2415,-0.0599",\ +"-0.4526,-0.4379,-0.4242,-0.3949,-0.3442,-0.2465,-0.0649",\ +"-0.4570,-0.4424,-0.4287,-0.3994,-0.3486,-0.2510,-0.0693",\ +"-0.4662,-0.4515,-0.4378,-0.4085,-0.3578,-0.2601,-0.0785",\ +"-0.4734,-0.4587,-0.4450,-0.4157,-0.3650,-0.2673,-0.0857",\ +"-0.5030,-0.4884,-0.4747,-0.4454,-0.3946,-0.2970,-0.1153",\ +"-0.5611,-0.5464,-0.5328,-0.5035,-0.4527,-0.3550,-0.1734"); + } + } + + timing() { + timing_type : hold_rising; + related_pin : "A_CLK"; + when : "(A_WEN & A_MEN)"; + sdf_cond : "A_W_ACCESS"; + + rise_constraint("SIG2SRAM_constraint_template") { + index_1("0.0056,0.0232,0.0400,0.0728,0.1280,0.2440,0.4760"); + index_2("0.0056,0.0232,0.0400,0.0728,0.1280,0.2440,0.4760"); + values ("0.5976,0.5820,0.5693,0.5361,0.4883,0.3896,0.1943",\ +"0.6027,0.5870,0.5743,0.5411,0.4933,0.3946,0.1993",\ +"0.6071,0.5915,0.5788,0.5456,0.4978,0.3991,0.2038",\ +"0.6162,0.6006,0.5879,0.5547,0.5069,0.4082,0.2129",\ +"0.6234,0.6078,0.5951,0.5619,0.5141,0.4154,0.2201",\ +"0.6531,0.6375,0.6248,0.5916,0.5437,0.4451,0.2498",\ +"0.7112,0.6956,0.6829,0.6497,0.6018,0.5032,0.3079"); + } + + fall_constraint("SIG2SRAM_constraint_template") { + index_1("0.0056,0.0232,0.0400,0.0728,0.1280,0.2440,0.4760"); + index_2("0.0056,0.0232,0.0400,0.0728,0.1280,0.2440,0.4760"); + values ("0.5488,0.5352,0.5215,0.4932,0.4424,0.3496,0.1621",\ +"0.5538,0.5402,0.5265,0.4982,0.4474,0.3546,0.1671",\ +"0.5583,0.5446,0.5310,0.5026,0.4519,0.3591,0.1716",\ +"0.5674,0.5537,0.5401,0.5118,0.4610,0.3682,0.1807",\ +"0.5746,0.5609,0.5473,0.5190,0.4682,0.3754,0.1879",\ +"0.6043,0.5906,0.5769,0.5486,0.4978,0.4051,0.2176",\ +"0.6623,0.6487,0.6350,0.6067,0.5559,0.4631,0.2756"); + } + } + } + +bus(A_DOUT) { + + bus_type : D_31_0; + direction : output ; + capacitance : 0 ; + max_capacitance : 0.064 ; + memory_read() { + address : A_ADDR ; + } + pin(A_DOUT[31:0]) { + related_power_pin : VDD; + related_ground_pin : VSS; + internal_power() { + rise_power("scalar") { + values (0); + } + fall_power("scalar") { + values (0); + } + } + } + timing() { + related_pin : "A_CLK"; + timing_type : rising_edge ; + timing_sense : non_unate ; + + cell_rise(SIG2SRAM_delay_template) { + index_1("0.0056,0.0232,0.0400,0.0728,0.1280,0.2440,0.4760"); + index_2("0.0008,0.0014,0.0051,0.0100,0.0339,0.0640"); + values ("3.0970,3.0986,3.1062,3.1150,3.1474,3.1835",\ +"3.1033,3.1050,3.1126,3.1213,3.1537,3.1898",\ +"3.1054,3.1071,3.1147,3.1234,3.1558,3.1919",\ +"3.1185,3.1201,3.1277,3.1365,3.1688,3.2050",\ +"3.1247,3.1263,3.1339,3.1427,3.1750,3.2112",\ +"3.1562,3.1578,3.1654,3.1741,3.2065,3.2427",\ +"3.2107,3.2123,3.2199,3.2286,3.2610,3.2972"); + } + cell_fall(SIG2SRAM_delay_template) { + index_1("0.0056,0.0232,0.0400,0.0728,0.1280,0.2440,0.4760"); + index_2("0.0008,0.0014,0.0051,0.0100,0.0339,0.0640"); + values ("3.0367,3.0381,3.0441,3.0513,3.0778,3.1040",\ +"3.0431,3.0444,3.0505,3.0576,3.0841,3.1103",\ +"3.0452,3.0465,3.0526,3.0597,3.0862,3.1124",\ +"3.0582,3.0596,3.0656,3.0728,3.0993,3.1255",\ +"3.0644,3.0658,3.0718,3.0790,3.1055,3.1317",\ +"3.0959,3.0972,3.1033,3.1104,3.1369,3.1632",\ +"3.1504,3.1517,3.1578,3.1649,3.1914,3.2177"); + } + + rise_transition(SRAM_load_template) { + index_1("0.0008,0.0014,0.0051,0.0100,0.0339,0.0640"); + values ("0.0326,0.0341,0.0428,0.0518,0.0923,0.1492"); + } + fall_transition(SRAM_load_template) { + index_1("0.0008,0.0014,0.0051,0.0100,0.0339,0.0640"); + values ("0.0254,0.0265,0.0335,0.0402,0.0707,0.1039"); + } + } +} + pin(B_DLY) { + direction : input ; + capacitance : 0.00401111 ; + max_transition : "1" ; + related_power_pin : VDD; + related_ground_pin : VSS; + internal_power() { + rise_power("scalar") { + values (0); + } + fall_power("scalar") { + values (0); + } + } + } + +bus(B_ADDR) { + bus_type : A_5_0; + direction : input ; + capacitance : 0.0121077 ; + pin(B_ADDR[0]) { + capacitance : 0.00570093 ; + } + pin(B_ADDR[1]) { + capacitance : 0.00764555 ; + } + pin(B_ADDR[2]) { + capacitance : 0.0105375 ; + } + pin(B_ADDR[3]) { + capacitance : 0.0067894 ; + } + pin(B_ADDR[4]) { + capacitance : 0.00630967 ; + } + max_transition : "0.476" ; + pin(B_ADDR[5:0]) { + related_power_pin : VDD; + related_ground_pin : VSS; + internal_power() { + when : "B_MEN"; + rise_power("scalar"){ + values (0.0394); + } + fall_power("scalar"){ + values (0.0421); + } + } + internal_power() { + when : "!B_MEN"; + rise_power("scalar"){ + values (0.0164); + } + fall_power("scalar"){ + values (0.0008); + } + } + } + timing() { + timing_type : setup_rising; + related_pin : "B_CLK"; + when : "((B_WEN | B_REN)& B_MEN)" + sdf_cond : "B_RW_ACCESS" + + rise_constraint("SIG2SRAM_constraint_template") { + index_1("0.0056,0.0232,0.0400,0.0728,0.1280,0.2440,0.4760"); + index_2("0.0056,0.0232,0.0400,0.0728,0.1280,0.2440,0.4760"); + values ("-0.4168,-0.3973,-0.3855,-0.3543,-0.3074,-0.2020,-0.0027",\ +"-0.4324,-0.4129,-0.4012,-0.3699,-0.3191,-0.2176,-0.0184",\ +"-0.4441,-0.4285,-0.4129,-0.3816,-0.3309,-0.2293,-0.0301",\ +"-0.4793,-0.4598,-0.4441,-0.4129,-0.3660,-0.2645,-0.0652",\ +"-0.5223,-0.5066,-0.4910,-0.4598,-0.4129,-0.3074,-0.1121",\ +"-0.6199,-0.6082,-0.5926,-0.5613,-0.5145,-0.4129,-0.2137",\ +"-0.8191,-0.8074,-0.7840,-0.7566,-0.7098,-0.6082,-0.4051"); + } + + fall_constraint("SIG2SRAM_constraint_template") { + index_1("0.0056,0.0232,0.0400,0.0728,0.1280,0.2440,0.4760"); + index_2("0.0056,0.0232,0.0400,0.0728,0.1280,0.2440,0.4760"); + values ("-0.3309,-0.3113,-0.2996,-0.2684,-0.2176,-0.1238,0.0637",\ +"-0.3465,-0.3309,-0.3152,-0.2840,-0.2332,-0.1395,0.0480",\ +"-0.3582,-0.3426,-0.3270,-0.2996,-0.2488,-0.1512,0.0324",\ +"-0.3895,-0.3738,-0.3582,-0.3309,-0.2801,-0.1863,0.0051",\ +"-0.4363,-0.4207,-0.4051,-0.3777,-0.3230,-0.2293,-0.0379",\ +"-0.5379,-0.5223,-0.5066,-0.4793,-0.4285,-0.3309,-0.1434",\ +"-0.7332,-0.7176,-0.7020,-0.6746,-0.6238,-0.5262,-0.3387"); + } + } + + + timing() { + timing_type : hold_rising; + related_pin : "B_CLK"; + when : "((B_WEN | B_REN)& B_MEN)" + sdf_cond : "B_RW_ACCESS" + + rise_constraint("SIG2SRAM_constraint_template") { + index_1("0.0056,0.0232,0.0400,0.0728,0.1280,0.2440,0.4760"); + index_2("0.0056,0.0232,0.0400,0.0728,0.1280,0.2440,0.4760"); + values ("0.5246,0.5051,0.4895,0.4582,0.4113,0.3059,0.1066",\ +"0.5402,0.5207,0.5051,0.4777,0.4270,0.3215,0.1223",\ +"0.5520,0.5324,0.5168,0.4895,0.4387,0.3371,0.1340",\ +"0.5832,0.5676,0.5520,0.5207,0.4738,0.3684,0.1691",\ +"0.6301,0.6105,0.5949,0.5676,0.5168,0.4113,0.2160",\ +"0.7316,0.7121,0.7004,0.6691,0.6223,0.5168,0.3176",\ +"0.9270,0.9230,0.8957,0.8645,0.8137,0.7121,0.5168"); + } + + fall_constraint("SIG2SRAM_constraint_template") { + index_1("0.0056,0.0232,0.0400,0.0728,0.1280,0.2440,0.4760"); + index_2("0.0056,0.0232,0.0400,0.0728,0.1280,0.2440,0.4760"); + values ("0.4309,0.4152,0.4035,0.3684,0.3215,0.2277,0.0363",\ +"0.4465,0.4309,0.4152,0.3879,0.3371,0.2395,0.0559",\ +"0.4582,0.4426,0.4309,0.3996,0.3488,0.2551,0.0715",\ +"0.4934,0.4777,0.4621,0.4348,0.3840,0.2863,0.0988",\ +"0.5363,0.5207,0.5051,0.4777,0.4270,0.3332,0.1418",\ +"0.6379,0.6262,0.6105,0.5793,0.5324,0.4348,0.2434",\ +"0.8332,0.8215,0.8059,0.7707,0.7238,0.6301,0.4387"); + } + } +} +pin(B_WEN) { + direction : input ; + capacitance : 0.00324098 ; + max_transition : "0.476" ; + related_power_pin : VDD; + related_ground_pin : VSS; + internal_power() { + when : "B_MEN"; + rise_power("scalar"){ + values (0.0323); + } + fall_power("scalar"){ + values (0.0552); + } + } + internal_power() { + when : "!B_MEN"; + rise_power("scalar"){ + values (0.0050); + } + fall_power("scalar"){ + values (0.0050); + } + } + timing() { + timing_type : setup_rising; + related_pin : "B_CLK"; + when : "B_MEN" + sdf_cond : "B_MEN" + + rise_constraint("SIG2SRAM_constraint_template") { + index_1("0.0056,0.0232,0.0400,0.0728,0.1280,0.2440,0.4760"); + index_2("0.0056,0.0232,0.0400,0.0728,0.1280,0.2440,0.4760"); + values ("0.2043,0.2199,0.2316,0.2629,0.3059,0.4113,0.6066",\ +"0.1887,0.2043,0.2160,0.2473,0.2941,0.3957,0.5949",\ +"0.1691,0.1848,0.2004,0.2316,0.2785,0.3801,0.5754",\ +"0.1379,0.1574,0.1691,0.2004,0.2473,0.3527,0.5480",\ +"0.0910,0.1066,0.1223,0.1535,0.2004,0.2980,0.4973",\ +"-0.0105,0.0051,0.0207,0.0520,0.0949,0.2004,0.3957",\ +"-0.2059,-0.1902,-0.1746,-0.1473,-0.1004,0.0051,0.2004"); + } + + fall_constraint("SIG2SRAM_constraint_template") { + index_1("0.0056,0.0232,0.0400,0.0728,0.1280,0.2440,0.4760"); + index_2("0.0056,0.0232,0.0400,0.0728,0.1280,0.2440,0.4760"); + values ("0.2941,0.3098,0.3215,0.3488,0.4035,0.4973,0.6887",\ +"0.2785,0.2941,0.3059,0.3332,0.3840,0.4816,0.6691",\ +"0.2629,0.2785,0.2902,0.3176,0.3684,0.4660,0.6535",\ +"0.2316,0.2473,0.2590,0.2863,0.3410,0.4348,0.6262",\ +"0.1848,0.2004,0.2121,0.2395,0.2902,0.3879,0.5754",\ +"0.0832,0.0988,0.1105,0.1379,0.1809,0.2746,0.4699",\ +"-0.1121,-0.0965,-0.0848,-0.0535,-0.0066,0.0910,0.2824"); + } + } + + + timing() { + timing_type : hold_rising; + related_pin : "B_CLK"; + when : "B_MEN" + sdf_cond : "B_MEN" + + rise_constraint("SIG2SRAM_constraint_template") { + index_1("0.0056,0.0232,0.0400,0.0728,0.1280,0.2440,0.4760"); + index_2("0.0056,0.0232,0.0400,0.0728,0.1280,0.2440,0.4760"); + values ("0.2473,0.2316,0.2160,0.1887,0.1379,0.0363,-0.1629",\ +"0.2629,0.2473,0.2316,0.2043,0.1535,0.0520,-0.1473",\ +"0.2785,0.2590,0.2434,0.2160,0.1652,0.0676,-0.1355",\ +"0.3098,0.2941,0.2785,0.2473,0.1965,0.0910,-0.1043",\ +"0.3527,0.3371,0.3215,0.2941,0.2434,0.1418,-0.0574",\ +"0.4582,0.4426,0.4270,0.3957,0.3488,0.2434,0.0480",\ +"0.6535,0.6379,0.6184,0.5910,0.5402,0.4426,0.2434"); + } + + fall_constraint("SIG2SRAM_constraint_template") { + index_1("0.0056,0.0232,0.0400,0.0728,0.1280,0.2440,0.4760"); + index_2("0.0056,0.0232,0.0400,0.0728,0.1280,0.2440,0.4760"); + values ("0.2395,0.2238,0.2121,0.1809,0.1301,0.0324,-0.1551",\ +"0.2551,0.2395,0.2277,0.1965,0.1457,0.0480,-0.1395",\ +"0.2668,0.2551,0.2395,0.2082,0.1574,0.0637,-0.1277",\ +"0.3020,0.2863,0.2707,0.2395,0.1887,0.0910,-0.0965",\ +"0.3449,0.3293,0.3176,0.2863,0.2355,0.1379,-0.0496",\ +"0.4504,0.4348,0.4191,0.3879,0.3371,0.2395,0.0559",\ +"0.6457,0.6301,0.6145,0.5871,0.5324,0.4309,0.2512"); + } + } + } +pin(B_REN) { + direction : input ; + capacitance : 0.00381634 ; + max_transition : "0.476" ; + related_power_pin : VDD; + related_ground_pin : VSS; + internal_power() { + when : "B_MEN"; + rise_power("scalar"){ + values (0.2409); + } + fall_power("scalar"){ + values (0.0203); + } + } + internal_power() { + when : "!B_MEN"; + rise_power("scalar"){ + values (0.0057); + } + fall_power("scalar"){ + values (0.0029); + } + } + timing() { + timing_type : setup_rising; + related_pin : "B_CLK"; + when : "B_MEN" + sdf_cond : "B_MEN" + + rise_constraint("SIG2SRAM_constraint_template") { + index_1("0.0056,0.0232,0.0400,0.0728,0.1280,0.2440,0.4760"); + index_2("0.0056,0.0232,0.0400,0.0728,0.1280,0.2440,0.4760"); + values ("-0.0301,-0.0145,0.0012,0.0324,0.0793,0.1809,0.3762",\ +"-0.0457,-0.0301,-0.0145,0.0168,0.0637,0.1613,0.3605",\ +"-0.0574,-0.0418,-0.0262,0.0051,0.0520,0.1496,0.3449",\ +"-0.0926,-0.0730,-0.0574,-0.0262,0.0207,0.1184,0.3137",\ +"-0.1395,-0.1238,-0.1082,-0.0770,-0.0301,0.0715,0.2707",\ +"-0.2410,-0.2254,-0.2098,-0.1746,-0.1355,-0.0340,0.1652",\ +"-0.4402,-0.4207,-0.4051,-0.3738,-0.3270,-0.2293,-0.0340"); + } + + fall_constraint("SIG2SRAM_constraint_template") { + index_1("0.0056,0.0232,0.0400,0.0728,0.1280,0.2440,0.4760"); + index_2("0.0056,0.0232,0.0400,0.0728,0.1280,0.2440,0.4760"); + values ("0.0988,0.1145,0.1262,0.1535,0.2043,0.3020,0.4855",\ +"0.0832,0.0988,0.1105,0.1418,0.1848,0.2824,0.4738",\ +"0.0676,0.0832,0.0949,0.1262,0.1730,0.2668,0.4621",\ +"0.0402,0.0559,0.0676,0.0988,0.1457,0.2434,0.4191",\ +"-0.0105,0.0012,0.0168,0.0480,0.0988,0.1965,0.3840",\ +"-0.1160,-0.0965,-0.0848,-0.0535,-0.0066,0.0988,0.2824",\ +"-0.3113,-0.2957,-0.2801,-0.2527,-0.2059,-0.1043,0.0832"); + } + } + + + timing() { + timing_type : hold_rising; + related_pin : "B_CLK"; + when : "B_MEN" + sdf_cond : "B_MEN" + + rise_constraint("SIG2SRAM_constraint_template") { + index_1("0.0056,0.0232,0.0400,0.0728,0.1280,0.2440,0.4760"); + index_2("0.0056,0.0232,0.0400,0.0728,0.1280,0.2440,0.4760"); + values ("0.2707,0.2551,0.2395,0.2121,0.1613,0.0598,-0.1395",\ +"0.2863,0.2707,0.2551,0.2238,0.1730,0.0715,-0.1238",\ +"0.2980,0.2824,0.2668,0.2395,0.1887,0.0871,-0.1121",\ +"0.3332,0.3176,0.3020,0.2707,0.2199,0.1184,-0.0809",\ +"0.3762,0.3605,0.3449,0.3176,0.2668,0.1613,-0.0340",\ +"0.4816,0.4621,0.4504,0.4191,0.3723,0.2629,0.0715",\ +"0.6770,0.6613,0.6418,0.6184,0.5637,0.4699,0.2629"); + } + + fall_constraint("SIG2SRAM_constraint_template") { + index_1("0.0056,0.0232,0.0400,0.0728,0.1280,0.2440,0.4760"); + index_2("0.0056,0.0232,0.0400,0.0728,0.1280,0.2440,0.4760"); + values ("0.2590,0.2434,0.2316,0.2004,0.1457,0.0520,-0.1355",\ +"0.2746,0.2590,0.2434,0.2160,0.1613,0.0676,-0.1199",\ +"0.2863,0.2707,0.2590,0.2277,0.1730,0.0832,-0.1082",\ +"0.3215,0.3059,0.2902,0.2590,0.2082,0.1105,-0.0770",\ +"0.3645,0.3488,0.3332,0.3059,0.2551,0.1535,-0.0340",\ +"0.4699,0.4543,0.4387,0.4074,0.3605,0.2551,0.0715",\ +"0.6652,0.6496,0.6340,0.6027,0.5520,0.4621,0.2707"); + } + } + } +pin(B_MEN) { + direction : input ; + capacitance : 0.00309605 ; + max_transition : "0.476" ; + related_power_pin : VDD; + related_ground_pin : VSS; + internal_power() { + rise_power("scalar"){ + values (0.0869); + } + fall_power("scalar"){ + values (0.0336); + } + } + timing() { + timing_type : setup_rising; + related_pin : "B_CLK"; + + rise_constraint("SIG2SRAM_constraint_template") { + index_1("0.0056,0.0232,0.0400,0.0728,0.1280,0.2440,0.4760"); + index_2("0.0056,0.0232,0.0400,0.0728,0.1280,0.2440,0.4760"); + values ("0.2043,0.2199,0.2316,0.2668,0.3098,0.4152,0.6066",\ +"0.1887,0.2043,0.2199,0.2512,0.2941,0.3996,0.5949",\ +"0.1730,0.1887,0.2043,0.2355,0.2824,0.3840,0.5793",\ +"0.1418,0.1574,0.1730,0.2043,0.2512,0.3566,0.5480",\ +"0.0949,0.1105,0.1262,0.1574,0.2043,0.3020,0.5051",\ +"-0.0066,0.0090,0.0246,0.0520,0.0988,0.2043,0.3996",\ +"-0.2020,-0.1863,-0.1746,-0.1434,-0.0965,0.0090,0.2082"); + } + + fall_constraint("SIG2SRAM_constraint_template") { + index_1("0.0056,0.0232,0.0400,0.0728,0.1280,0.2440,0.4760"); + index_2("0.0056,0.0232,0.0400,0.0728,0.1280,0.2440,0.4760"); + values ("0.2980,0.3137,0.3254,0.3527,0.4035,0.5012,0.6887",\ +"0.2824,0.2980,0.3098,0.3371,0.3879,0.4855,0.6730",\ +"0.2668,0.2824,0.2941,0.3215,0.3723,0.4699,0.6574",\ +"0.2355,0.2473,0.2629,0.2902,0.3410,0.4387,0.6262",\ +"0.1887,0.2004,0.2160,0.2395,0.2941,0.3918,0.5793",\ +"0.0871,0.1027,0.1145,0.1418,0.1848,0.2746,0.4816",\ +"-0.1082,-0.0965,-0.0809,-0.0496,-0.0027,0.0949,0.2863"); + } + } + + + timing() { + timing_type : hold_rising; + related_pin : "B_CLK"; + + rise_constraint("SIG2SRAM_constraint_template") { + index_1("0.0056,0.0232,0.0400,0.0728,0.1280,0.2440,0.4760"); + index_2("0.0056,0.0232,0.0400,0.0728,0.1280,0.2440,0.4760"); + values ("0.2512,0.2355,0.2199,0.1926,0.1418,0.0402,-0.1590",\ +"0.2668,0.2512,0.2355,0.2082,0.1574,0.0559,-0.1434",\ +"0.2824,0.2629,0.2512,0.2199,0.1691,0.0715,-0.1316",\ +"0.3137,0.2980,0.2824,0.2512,0.2004,0.0988,-0.0965",\ +"0.3566,0.3410,0.3254,0.2980,0.2473,0.1418,-0.0535",\ +"0.4621,0.4426,0.4309,0.3996,0.3527,0.2473,0.0520",\ +"0.6574,0.6418,0.6262,0.5949,0.5441,0.4465,0.2473"); + } + + fall_constraint("SIG2SRAM_constraint_template") { + index_1("0.0056,0.0232,0.0400,0.0728,0.1280,0.2440,0.4760"); + index_2("0.0056,0.0232,0.0400,0.0728,0.1280,0.2440,0.4760"); + values ("0.2395,0.2238,0.2121,0.1809,0.1301,0.0324,-0.1551",\ +"0.2551,0.2434,0.2277,0.1965,0.1457,0.0480,-0.1395",\ +"0.2707,0.2551,0.2395,0.2082,0.1574,0.0637,-0.1277",\ +"0.3020,0.2863,0.2707,0.2434,0.1926,0.0910,-0.0965",\ +"0.3449,0.3332,0.3176,0.2863,0.2355,0.1379,-0.0496",\ +"0.4504,0.4348,0.4230,0.3918,0.3410,0.2434,0.0559",\ +"0.6457,0.6301,0.6145,0.5910,0.5324,0.4387,0.2512"); + } + } + } + pin(B_CLK) { + direction : input; + capacitance : 0.00380014; + max_transition : "0.476"; + clock : "true" ; + pin_func_type : active_rising ; + + timing () { + timing_type : "min_pulse_width"; + related_pin : "B_CLK"; + rise_constraint("CLKTRAN_constraint_template") { + index_1("0.0056,0.476"); + values("0.21,0.21"); + } + } + + related_power_pin : VDD; + related_ground_pin : VSS; + + internal_power() { + when : "!B_MEN & !B_WEN & !B_REN"; + rise_power("scalar"){ + values (0); + } + fall_power("scalar"){ + values (0); + } + } + internal_power() { + when : "!B_MEN & B_WEN & !B_REN"; + rise_power("scalar"){ + values (0.9807); + } + fall_power("scalar"){ + values (0); + } + } + internal_power() { + when : "B_MEN & B_WEN & !B_REN"; + rise_power("scalar"){ + values (26.4624); + } + fall_power("scalar"){ + values (0); + } + } + internal_power() { + when : "B_MEN & B_WEN & B_REN"; + rise_power("scalar"){ + values (29.5662); + } + fall_power("scalar"){ + values (0); + } + } + internal_power() { + when : "B_MEN & !B_WEN & B_REN"; + rise_power("scalar"){ + values (20.3627); + } + fall_power("scalar"){ + values (0); + } + } + internal_power() { + when : "!B_MEN & !B_WEN & B_REN"; + rise_power("scalar"){ + values (0.2739); + } + fall_power("scalar"){ + values (0); + } + } + internal_power() { + when : "!B_MEN & B_WEN & B_REN"; + rise_power("scalar"){ + values (1.2089); + } + fall_power("scalar"){ + values (0); + } + } + internal_power() { + when : "B_MEN & !B_WEN & !B_REN"; + rise_power("scalar"){ + values (0); + } + fall_power("scalar"){ + values (0); + } + } + } + bus(B_DIN) { + bus_type : D_31_0; + direction : input ; + capacitance : 0.00461776 ; + memory_write() { + address : B_ADDR ; + clocked_on : B_CLK; + } + + max_transition : "0.476" ; + pin(B_DIN[31:0]) { + related_power_pin : VDD; + related_ground_pin : VSS; + internal_power() { + when : "B_MEN"; + rise_power("scalar"){ + values (0.1195); + } + fall_power("scalar"){ + values (0.0483); + } + } + internal_power() { + when : "!B_MEN"; + rise_power("scalar"){ + values (0.1113); + } + fall_power("scalar"){ + values (0.0477); + } + } + } + timing() { + timing_type : setup_rising; + related_pin : "B_CLK"; + when : "(B_WEN & B_MEN)"; + sdf_cond : "B_W_ACCESS"; + + rise_constraint("SIG2SRAM_constraint_template") { + index_1("0.0056,0.0232,0.0400,0.0728,0.1280,0.2440,0.4760"); + index_2("0.0056,0.0232,0.0400,0.0728,0.1280,0.2440,0.4760"); + values ("-0.4895,-0.4729,-0.4603,-0.4280,-0.3821,-0.2796,-0.0872",\ +"-0.4946,-0.4779,-0.4653,-0.4330,-0.3871,-0.2846,-0.0922",\ +"-0.4990,-0.4824,-0.4697,-0.4375,-0.3916,-0.2891,-0.0967",\ +"-0.5081,-0.4915,-0.4789,-0.4466,-0.4007,-0.2982,-0.1058",\ +"-0.5153,-0.4987,-0.4861,-0.4538,-0.4079,-0.3054,-0.1130",\ +"-0.5450,-0.5284,-0.5157,-0.4835,-0.4376,-0.3351,-0.1427",\ +"-0.6031,-0.5865,-0.5738,-0.5416,-0.4957,-0.3931,-0.2007"); + } + + fall_constraint("SIG2SRAM_constraint_template") { + index_1("0.0056,0.0232,0.0400,0.0728,0.1280,0.2440,0.4760"); + index_2("0.0056,0.0232,0.0400,0.0728,0.1280,0.2440,0.4760"); + values ("-0.4476,-0.4329,-0.4192,-0.3899,-0.3392,-0.2415,-0.0599",\ +"-0.4526,-0.4379,-0.4242,-0.3949,-0.3442,-0.2465,-0.0649",\ +"-0.4570,-0.4424,-0.4287,-0.3994,-0.3486,-0.2510,-0.0693",\ +"-0.4662,-0.4515,-0.4378,-0.4085,-0.3578,-0.2601,-0.0785",\ +"-0.4734,-0.4587,-0.4450,-0.4157,-0.3650,-0.2673,-0.0857",\ +"-0.5030,-0.4884,-0.4747,-0.4454,-0.3946,-0.2970,-0.1153",\ +"-0.5611,-0.5464,-0.5328,-0.5035,-0.4527,-0.3550,-0.1734"); + } + } + + timing() { + timing_type : hold_rising; + related_pin : "B_CLK"; + when : "(B_WEN & B_MEN)"; + sdf_cond : "B_W_ACCESS"; + + rise_constraint("SIG2SRAM_constraint_template") { + index_1("0.0056,0.0232,0.0400,0.0728,0.1280,0.2440,0.4760"); + index_2("0.0056,0.0232,0.0400,0.0728,0.1280,0.2440,0.4760"); + values ("0.5976,0.5820,0.5693,0.5361,0.4883,0.3896,0.1943",\ +"0.6027,0.5870,0.5743,0.5411,0.4933,0.3946,0.1993",\ +"0.6071,0.5915,0.5788,0.5456,0.4978,0.3991,0.2038",\ +"0.6162,0.6006,0.5879,0.5547,0.5069,0.4082,0.2129",\ +"0.6234,0.6078,0.5951,0.5619,0.5141,0.4154,0.2201",\ +"0.6531,0.6375,0.6248,0.5916,0.5437,0.4451,0.2498",\ +"0.7112,0.6956,0.6829,0.6497,0.6018,0.5032,0.3079"); + } + + fall_constraint("SIG2SRAM_constraint_template") { + index_1("0.0056,0.0232,0.0400,0.0728,0.1280,0.2440,0.4760"); + index_2("0.0056,0.0232,0.0400,0.0728,0.1280,0.2440,0.4760"); + values ("0.5488,0.5352,0.5215,0.4932,0.4424,0.3496,0.1621",\ +"0.5538,0.5402,0.5265,0.4982,0.4474,0.3546,0.1671",\ +"0.5583,0.5446,0.5310,0.5026,0.4519,0.3591,0.1716",\ +"0.5674,0.5537,0.5401,0.5118,0.4610,0.3682,0.1807",\ +"0.5746,0.5609,0.5473,0.5190,0.4682,0.3754,0.1879",\ +"0.6043,0.5906,0.5769,0.5486,0.4978,0.4051,0.2176",\ +"0.6623,0.6487,0.6350,0.6067,0.5559,0.4631,0.2756"); + } + } + } + +bus(B_DOUT) { + + bus_type : D_31_0; + direction : output ; + capacitance : 0 ; + max_capacitance : 0.064 ; + memory_read() { + address : B_ADDR ; + } + pin(B_DOUT[31:0]) { + related_power_pin : VDD; + related_ground_pin : VSS; + internal_power() { + rise_power("scalar") { + values (0); + } + fall_power("scalar") { + values (0); + } + } + } + timing() { + related_pin : "B_CLK"; + timing_type : rising_edge ; + timing_sense : non_unate ; + + cell_rise(SIG2SRAM_delay_template) { + index_1("0.0056,0.0232,0.0400,0.0728,0.1280,0.2440,0.4760"); + index_2("0.0008,0.0014,0.0051,0.0100,0.0339,0.0640"); + values ("3.0970,3.0986,3.1062,3.1150,3.1474,3.1835",\ +"3.1033,3.1050,3.1126,3.1213,3.1537,3.1898",\ +"3.1054,3.1071,3.1147,3.1234,3.1558,3.1919",\ +"3.1185,3.1201,3.1277,3.1365,3.1688,3.2050",\ +"3.1247,3.1263,3.1339,3.1427,3.1750,3.2112",\ +"3.1562,3.1578,3.1654,3.1741,3.2065,3.2427",\ +"3.2107,3.2123,3.2199,3.2286,3.2610,3.2972"); + } + cell_fall(SIG2SRAM_delay_template) { + index_1("0.0056,0.0232,0.0400,0.0728,0.1280,0.2440,0.4760"); + index_2("0.0008,0.0014,0.0051,0.0100,0.0339,0.0640"); + values ("3.0367,3.0381,3.0441,3.0513,3.0778,3.1040",\ +"3.0431,3.0444,3.0505,3.0576,3.0841,3.1103",\ +"3.0452,3.0465,3.0526,3.0597,3.0862,3.1124",\ +"3.0582,3.0596,3.0656,3.0728,3.0993,3.1255",\ +"3.0644,3.0658,3.0718,3.0790,3.1055,3.1317",\ +"3.0959,3.0972,3.1033,3.1104,3.1369,3.1632",\ +"3.1504,3.1517,3.1578,3.1649,3.1914,3.2177"); + } + + rise_transition(SRAM_load_template) { + index_1("0.0008,0.0014,0.0051,0.0100,0.0339,0.0640"); + values ("0.0326,0.0341,0.0428,0.0518,0.0923,0.1492"); + } + fall_transition(SRAM_load_template) { + index_1("0.0008,0.0014,0.0051,0.0100,0.0339,0.0640"); + values ("0.0254,0.0265,0.0335,0.0402,0.0707,0.1039"); + } + } +} +cell_leakage_power : 39.8626; +} +} diff --git a/flow/platforms/ihp-sg13g2/lib/sg13g2_io_fast_1p32V_3p6V_m40C.lib b/flow/platforms/ihp-sg13g2/lib/sg13g2_io_fast_1p32V_3p6V_m40C.lib index c42ff8c075..05244eaca5 100644 --- a/flow/platforms/ihp-sg13g2/lib/sg13g2_io_fast_1p32V_3p6V_m40C.lib +++ b/flow/platforms/ihp-sg13g2/lib/sg13g2_io_fast_1p32V_3p6V_m40C.lib @@ -219,6 +219,12 @@ library (sg13g2_io_fast_1p32V_3p6V_m40C) { index_1 ("0.02, 0.1, 0.17, 0.33, 0.64, 1.26, 2.5"); index_2 ("1, 3, 7, 9, 12, 15"); } + lu_table_template (delay_template_2x2) { + variable_1 : input_net_transition; + variable_2 : total_output_net_capacitance; + index_1 ("10, 200"); + index_2 ("500, 30000"); + } power_lut_template (passive_power_template_7x1_16) { variable_1 : input_transition_time; index_1 ("0.02, 0.1, 0.17, 0.33, 0.64, 1.26, 2.5"); @@ -294,6 +300,8 @@ library (sg13g2_io_fast_1p32V_3p6V_m40C) { cell (sg13g2_IOPadIn) { pad_cell : true; area : 14400; + dont_touch : true; + dont_use : true; cell_footprint : "input"; pad_drivers : 1; bond_pads : 1; @@ -484,6 +492,8 @@ library (sg13g2_io_fast_1p32V_3p6V_m40C) { cell (sg13g2_IOPadInOut16mA) { pad_cell : true; area : 14400; + dont_touch : true; + dont_use : true; cell_footprint : "inout"; pad_drivers : 1; bond_pads : 1; @@ -1178,6 +1188,8 @@ library (sg13g2_io_fast_1p32V_3p6V_m40C) { cell (sg13g2_IOPadInOut30mA) { pad_cell : true; area : 14400; + dont_touch : true; + dont_use : true; cell_footprint : "inout"; pad_drivers : 1; bond_pads : 1; @@ -1872,6 +1884,8 @@ library (sg13g2_io_fast_1p32V_3p6V_m40C) { cell (sg13g2_IOPadInOut4mA) { pad_cell : true; area : 14400; + dont_touch : true; + dont_use : true; cell_footprint : "inout"; pad_drivers : 1; bond_pads : 1; @@ -2566,6 +2580,8 @@ library (sg13g2_io_fast_1p32V_3p6V_m40C) { cell (sg13g2_IOPadOut16mA) { pad_cell : true; area : 14400; + dont_touch : true; + dont_use : true; cell_footprint : "inout"; pad_drivers : 1; bond_pads : 1; @@ -2757,6 +2773,8 @@ library (sg13g2_io_fast_1p32V_3p6V_m40C) { cell (sg13g2_IOPadOut30mA) { pad_cell : true; area : 14400; + dont_touch : true; + dont_use : true; cell_footprint : "inout"; pad_drivers : 1; bond_pads : 1; @@ -2948,6 +2966,8 @@ library (sg13g2_io_fast_1p32V_3p6V_m40C) { cell (sg13g2_IOPadOut4mA) { pad_cell : true; area : 14400; + dont_touch : true; + dont_use : true; cell_footprint : "inout"; pad_drivers : 1; bond_pads : 1; @@ -3139,6 +3159,8 @@ library (sg13g2_io_fast_1p32V_3p6V_m40C) { cell (sg13g2_IOPadTriOut16mA) { pad_cell : true; area : 14400; + dont_touch : true; + dont_use : true; cell_footprint : "tri_out"; pad_drivers : 1; bond_pads : 1; @@ -3605,6 +3627,8 @@ library (sg13g2_io_fast_1p32V_3p6V_m40C) { cell (sg13g2_IOPadTriOut30mA) { pad_cell : true; area : 14400; + dont_touch : true; + dont_use : true; cell_footprint : "tri_out"; pad_drivers : 1; bond_pads : 1; @@ -4071,6 +4095,8 @@ library (sg13g2_io_fast_1p32V_3p6V_m40C) { cell (sg13g2_IOPadTriOut4mA) { pad_cell : true; area : 14400; + dont_touch : true; + dont_use : true; cell_footprint : "tri_out"; pad_drivers : 1; bond_pads : 1; @@ -4596,4 +4622,77 @@ library (sg13g2_io_fast_1p32V_3p6V_m40C) { related_pg_pin : vdd; } } + cell (sg13g2_IOPadAnalog) { + area: 14400; + dont_touch : true; + dont_use : true; + timing_model_type : abstracted; + pad_cell : true; + pg_pin (vss) { + pg_type : primary_ground; + voltage_name : "vss"; + } + pg_pin (vdd) { + pg_type : primary_power; + voltage_name : "vdd"; + } + pg_pin (iovss) { + pg_type : primary_ground; + voltage_name : "iovss"; + } + pg_pin (iovdd) { + pg_type : primary_power; + voltage_name : "iovdd"; + } + pin (pad) { + direction : inout; + function : "(pad)"; + output_voltage : core_output; + related_ground_pin : vss; + related_power_pin : vdd; + max_capacitance : 500; + max_transition : 200; + timing () { + related_pin : "pad"; + timing_type : combinational; + cell_rise (delay_template_2x2) { + values ( \ + "1000, 1000", \ + "1000, 1000" \ + ); + } + rise_transition (delay_template_2x2) { + values ( \ + "200, 200", \ + "200, 200" \ + ); + } + cell_fall (delay_template_2x2) { + values ( \ + "1000, 1000", \ + "1000, 1000" \ + ); + } + fall_transition (delay_template_2x2) { + values ( \ + "200, 200", \ + "200, 200" \ + ); + } + } + } + pin (padres) { + direction : inout; + is_pad : false; + input_voltage : io_input; + related_ground_pin : iovss; + related_power_pin : iovdd; + max_transition : 200; + capacitance : 15.0; + rise_capacitance : 15.0; + rise_capacitance_range (12.0, 15.0); + fall_capacitance : 15.0; + fall_capacitance_range (12.0, 15.0); + } + } } diff --git a/flow/platforms/ihp-sg13g2/lib/sg13g2_io_fast_1p65V_3p6V_m40C.lib b/flow/platforms/ihp-sg13g2/lib/sg13g2_io_fast_1p65V_3p6V_m40C.lib index a8d38e287c..64a874e018 100644 --- a/flow/platforms/ihp-sg13g2/lib/sg13g2_io_fast_1p65V_3p6V_m40C.lib +++ b/flow/platforms/ihp-sg13g2/lib/sg13g2_io_fast_1p65V_3p6V_m40C.lib @@ -219,6 +219,12 @@ library (sg13g2_io_fast_1p65V_3p6V_m40C) { index_1 ("0.02, 0.1, 0.17, 0.33, 0.64, 1.26, 2.5"); index_2 ("1, 3, 7, 9, 12, 15"); } + lu_table_template (delay_template_2x2) { + variable_1 : input_net_transition; + variable_2 : total_output_net_capacitance; + index_1 ("10, 200"); + index_2 ("500, 30000"); + } power_lut_template (passive_power_template_7x1_16) { variable_1 : input_transition_time; index_1 ("0.02, 0.1, 0.17, 0.33, 0.64, 1.26, 2.5"); @@ -294,6 +300,8 @@ library (sg13g2_io_fast_1p65V_3p6V_m40C) { cell (sg13g2_IOPadIn) { pad_cell : true; area : 14400; + dont_touch : true; + dont_use : true; cell_footprint : "input"; pad_drivers : 1; bond_pads : 1; @@ -484,6 +492,8 @@ library (sg13g2_io_fast_1p65V_3p6V_m40C) { cell (sg13g2_IOPadInOut16mA) { pad_cell : true; area : 14400; + dont_touch : true; + dont_use : true; cell_footprint : "inout"; pad_drivers : 1; bond_pads : 1; @@ -1178,6 +1188,8 @@ library (sg13g2_io_fast_1p65V_3p6V_m40C) { cell (sg13g2_IOPadInOut30mA) { pad_cell : true; area : 14400; + dont_touch : true; + dont_use : true; cell_footprint : "inout"; pad_drivers : 1; bond_pads : 1; @@ -1872,6 +1884,8 @@ library (sg13g2_io_fast_1p65V_3p6V_m40C) { cell (sg13g2_IOPadInOut4mA) { pad_cell : true; area : 14400; + dont_touch : true; + dont_use : true; cell_footprint : "inout"; pad_drivers : 1; bond_pads : 1; @@ -2566,6 +2580,8 @@ library (sg13g2_io_fast_1p65V_3p6V_m40C) { cell (sg13g2_IOPadOut16mA) { pad_cell : true; area : 14400; + dont_touch : true; + dont_use : true; cell_footprint : "inout"; pad_drivers : 1; bond_pads : 1; @@ -2757,6 +2773,8 @@ library (sg13g2_io_fast_1p65V_3p6V_m40C) { cell (sg13g2_IOPadOut30mA) { pad_cell : true; area : 14400; + dont_touch : true; + dont_use : true; cell_footprint : "inout"; pad_drivers : 1; bond_pads : 1; @@ -2948,6 +2966,8 @@ library (sg13g2_io_fast_1p65V_3p6V_m40C) { cell (sg13g2_IOPadOut4mA) { pad_cell : true; area : 14400; + dont_touch : true; + dont_use : true; cell_footprint : "inout"; pad_drivers : 1; bond_pads : 1; @@ -3139,6 +3159,8 @@ library (sg13g2_io_fast_1p65V_3p6V_m40C) { cell (sg13g2_IOPadTriOut16mA) { pad_cell : true; area : 14400; + dont_touch : true; + dont_use : true; cell_footprint : "tri_out"; pad_drivers : 1; bond_pads : 1; @@ -3605,6 +3627,8 @@ library (sg13g2_io_fast_1p65V_3p6V_m40C) { cell (sg13g2_IOPadTriOut30mA) { pad_cell : true; area : 14400; + dont_touch : true; + dont_use : true; cell_footprint : "tri_out"; pad_drivers : 1; bond_pads : 1; @@ -4071,6 +4095,8 @@ library (sg13g2_io_fast_1p65V_3p6V_m40C) { cell (sg13g2_IOPadTriOut4mA) { pad_cell : true; area : 14400; + dont_touch : true; + dont_use : true; cell_footprint : "tri_out"; pad_drivers : 1; bond_pads : 1; @@ -4596,4 +4622,77 @@ library (sg13g2_io_fast_1p65V_3p6V_m40C) { related_pg_pin : vdd; } } + cell (sg13g2_IOPadAnalog) { + area: 14400; + dont_touch : true; + dont_use : true; + timing_model_type : abstracted; + pad_cell : true; + pg_pin (vss) { + pg_type : primary_ground; + voltage_name : "vss"; + } + pg_pin (vdd) { + pg_type : primary_power; + voltage_name : "vdd"; + } + pg_pin (iovss) { + pg_type : primary_ground; + voltage_name : "iovss"; + } + pg_pin (iovdd) { + pg_type : primary_power; + voltage_name : "iovdd"; + } + pin (pad) { + direction : inout; + function : "(pad)"; + output_voltage : core_output; + related_ground_pin : vss; + related_power_pin : vdd; + max_capacitance : 500; + max_transition : 200; + timing () { + related_pin : "pad"; + timing_type : combinational; + cell_rise (delay_template_2x2) { + values ( \ + "1000, 1000", \ + "1000, 1000" \ + ); + } + rise_transition (delay_template_2x2) { + values ( \ + "200, 200", \ + "200, 200" \ + ); + } + cell_fall (delay_template_2x2) { + values ( \ + "1000, 1000", \ + "1000, 1000" \ + ); + } + fall_transition (delay_template_2x2) { + values ( \ + "200, 200", \ + "200, 200" \ + ); + } + } + } + pin (padres) { + direction : inout; + is_pad : false; + input_voltage : io_input; + related_ground_pin : iovss; + related_power_pin : iovdd; + max_transition : 200; + capacitance : 15.0; + rise_capacitance : 15.0; + rise_capacitance_range (12.0, 15.0); + fall_capacitance : 15.0; + fall_capacitance_range (12.0, 15.0); + } + } } diff --git a/flow/platforms/ihp-sg13g2/lib/sg13g2_io_slow_1p08V_3p0V_125C.lib b/flow/platforms/ihp-sg13g2/lib/sg13g2_io_slow_1p08V_3p0V_125C.lib index 64cb1db0bb..84c04b6542 100644 --- a/flow/platforms/ihp-sg13g2/lib/sg13g2_io_slow_1p08V_3p0V_125C.lib +++ b/flow/platforms/ihp-sg13g2/lib/sg13g2_io_slow_1p08V_3p0V_125C.lib @@ -219,6 +219,12 @@ library (sg13g2_io_slow_1p08V_3p0V_125C) { index_1 ("0.02, 0.1, 0.17, 0.33, 0.64, 1.26, 2.5"); index_2 ("1, 3, 7, 9, 12, 15"); } + lu_table_template (delay_template_2x2) { + variable_1 : input_net_transition; + variable_2 : total_output_net_capacitance; + index_1 ("10, 200"); + index_2 ("500, 30000"); + } power_lut_template (passive_power_template_7x1_16) { variable_1 : input_transition_time; index_1 ("0.02, 0.1, 0.17, 0.33, 0.64, 1.26, 2.5"); @@ -294,6 +300,8 @@ library (sg13g2_io_slow_1p08V_3p0V_125C) { cell (sg13g2_IOPadIn) { pad_cell : true; area : 14400; + dont_touch : true; + dont_use : true; cell_footprint : "input"; pad_drivers : 1; bond_pads : 1; @@ -484,6 +492,8 @@ library (sg13g2_io_slow_1p08V_3p0V_125C) { cell (sg13g2_IOPadInOut16mA) { pad_cell : true; area : 14400; + dont_touch : true; + dont_use : true; cell_footprint : "inout"; pad_drivers : 1; bond_pads : 1; @@ -1178,6 +1188,8 @@ library (sg13g2_io_slow_1p08V_3p0V_125C) { cell (sg13g2_IOPadInOut30mA) { pad_cell : true; area : 14400; + dont_touch : true; + dont_use : true; cell_footprint : "inout"; pad_drivers : 1; bond_pads : 1; @@ -1872,6 +1884,8 @@ library (sg13g2_io_slow_1p08V_3p0V_125C) { cell (sg13g2_IOPadInOut4mA) { pad_cell : true; area : 14400; + dont_touch : true; + dont_use : true; cell_footprint : "inout"; pad_drivers : 1; bond_pads : 1; @@ -2566,6 +2580,8 @@ library (sg13g2_io_slow_1p08V_3p0V_125C) { cell (sg13g2_IOPadOut16mA) { pad_cell : true; area : 14400; + dont_touch : true; + dont_use : true; cell_footprint : "inout"; pad_drivers : 1; bond_pads : 1; @@ -2757,6 +2773,8 @@ library (sg13g2_io_slow_1p08V_3p0V_125C) { cell (sg13g2_IOPadOut30mA) { pad_cell : true; area : 14400; + dont_touch : true; + dont_use : true; cell_footprint : "inout"; pad_drivers : 1; bond_pads : 1; @@ -2948,6 +2966,8 @@ library (sg13g2_io_slow_1p08V_3p0V_125C) { cell (sg13g2_IOPadOut4mA) { pad_cell : true; area : 14400; + dont_touch : true; + dont_use : true; cell_footprint : "inout"; pad_drivers : 1; bond_pads : 1; @@ -3139,6 +3159,8 @@ library (sg13g2_io_slow_1p08V_3p0V_125C) { cell (sg13g2_IOPadTriOut16mA) { pad_cell : true; area : 14400; + dont_touch : true; + dont_use : true; cell_footprint : "tri_out"; pad_drivers : 1; bond_pads : 1; @@ -3605,6 +3627,8 @@ library (sg13g2_io_slow_1p08V_3p0V_125C) { cell (sg13g2_IOPadTriOut30mA) { pad_cell : true; area : 14400; + dont_touch : true; + dont_use : true; cell_footprint : "tri_out"; pad_drivers : 1; bond_pads : 1; @@ -4071,6 +4095,8 @@ library (sg13g2_io_slow_1p08V_3p0V_125C) { cell (sg13g2_IOPadTriOut4mA) { pad_cell : true; area : 14400; + dont_touch : true; + dont_use : true; cell_footprint : "tri_out"; pad_drivers : 1; bond_pads : 1; @@ -4596,4 +4622,77 @@ library (sg13g2_io_slow_1p08V_3p0V_125C) { related_pg_pin : vdd; } } + cell (sg13g2_IOPadAnalog) { + area: 14400; + dont_touch : true; + dont_use : true; + timing_model_type : abstracted; + pad_cell : true; + pg_pin (vss) { + pg_type : primary_ground; + voltage_name : "vss"; + } + pg_pin (vdd) { + pg_type : primary_power; + voltage_name : "vdd"; + } + pg_pin (iovss) { + pg_type : primary_ground; + voltage_name : "iovss"; + } + pg_pin (iovdd) { + pg_type : primary_power; + voltage_name : "iovdd"; + } + pin (pad) { + direction : inout; + function : "(pad)"; + output_voltage : core_output; + related_ground_pin : vss; + related_power_pin : vdd; + max_capacitance : 500; + max_transition : 200; + timing () { + related_pin : "pad"; + timing_type : combinational; + cell_rise (delay_template_2x2) { + values ( \ + "1000, 1000", \ + "1000, 1000" \ + ); + } + rise_transition (delay_template_2x2) { + values ( \ + "200, 200", \ + "200, 200" \ + ); + } + cell_fall (delay_template_2x2) { + values ( \ + "1000, 1000", \ + "1000, 1000" \ + ); + } + fall_transition (delay_template_2x2) { + values ( \ + "200, 200", \ + "200, 200" \ + ); + } + } + } + pin (padres) { + direction : inout; + is_pad : false; + input_voltage : io_input; + related_ground_pin : iovss; + related_power_pin : iovdd; + max_transition : 200; + capacitance : 15.0; + rise_capacitance : 15.0; + rise_capacitance_range (12.0, 15.0); + fall_capacitance : 15.0; + fall_capacitance_range (12.0, 15.0); + } + } } diff --git a/flow/platforms/ihp-sg13g2/lib/sg13g2_io_slow_1p35V_3p0V_125C.lib b/flow/platforms/ihp-sg13g2/lib/sg13g2_io_slow_1p35V_3p0V_125C.lib index 4f59f148b4..f09e5921b9 100644 --- a/flow/platforms/ihp-sg13g2/lib/sg13g2_io_slow_1p35V_3p0V_125C.lib +++ b/flow/platforms/ihp-sg13g2/lib/sg13g2_io_slow_1p35V_3p0V_125C.lib @@ -219,6 +219,12 @@ library (sg13g2_io_slow_1p35V_3p0V_125C) { index_1 ("0.02, 0.1, 0.17, 0.33, 0.64, 1.26, 2.5"); index_2 ("1, 3, 7, 9, 12, 15"); } + lu_table_template (delay_template_2x2) { + variable_1 : input_net_transition; + variable_2 : total_output_net_capacitance; + index_1 ("10, 200"); + index_2 ("500, 30000"); + } power_lut_template (passive_power_template_7x1_16) { variable_1 : input_transition_time; index_1 ("0.02, 0.1, 0.17, 0.33, 0.64, 1.26, 2.5"); @@ -294,6 +300,8 @@ library (sg13g2_io_slow_1p35V_3p0V_125C) { cell (sg13g2_IOPadIn) { pad_cell : true; area : 14400; + dont_touch : true; + dont_use : true; cell_footprint : "input"; pad_drivers : 1; bond_pads : 1; @@ -484,6 +492,8 @@ library (sg13g2_io_slow_1p35V_3p0V_125C) { cell (sg13g2_IOPadInOut16mA) { pad_cell : true; area : 14400; + dont_touch : true; + dont_use : true; cell_footprint : "inout"; pad_drivers : 1; bond_pads : 1; @@ -1178,6 +1188,8 @@ library (sg13g2_io_slow_1p35V_3p0V_125C) { cell (sg13g2_IOPadInOut30mA) { pad_cell : true; area : 14400; + dont_touch : true; + dont_use : true; cell_footprint : "inout"; pad_drivers : 1; bond_pads : 1; @@ -1872,6 +1884,8 @@ library (sg13g2_io_slow_1p35V_3p0V_125C) { cell (sg13g2_IOPadInOut4mA) { pad_cell : true; area : 14400; + dont_touch : true; + dont_use : true; cell_footprint : "inout"; pad_drivers : 1; bond_pads : 1; @@ -2566,6 +2580,8 @@ library (sg13g2_io_slow_1p35V_3p0V_125C) { cell (sg13g2_IOPadOut16mA) { pad_cell : true; area : 14400; + dont_touch : true; + dont_use : true; cell_footprint : "inout"; pad_drivers : 1; bond_pads : 1; @@ -2757,6 +2773,8 @@ library (sg13g2_io_slow_1p35V_3p0V_125C) { cell (sg13g2_IOPadOut30mA) { pad_cell : true; area : 14400; + dont_touch : true; + dont_use : true; cell_footprint : "inout"; pad_drivers : 1; bond_pads : 1; @@ -2948,6 +2966,8 @@ library (sg13g2_io_slow_1p35V_3p0V_125C) { cell (sg13g2_IOPadOut4mA) { pad_cell : true; area : 14400; + dont_touch : true; + dont_use : true; cell_footprint : "inout"; pad_drivers : 1; bond_pads : 1; @@ -3139,6 +3159,8 @@ library (sg13g2_io_slow_1p35V_3p0V_125C) { cell (sg13g2_IOPadTriOut16mA) { pad_cell : true; area : 14400; + dont_touch : true; + dont_use : true; cell_footprint : "tri_out"; pad_drivers : 1; bond_pads : 1; @@ -3605,6 +3627,8 @@ library (sg13g2_io_slow_1p35V_3p0V_125C) { cell (sg13g2_IOPadTriOut30mA) { pad_cell : true; area : 14400; + dont_touch : true; + dont_use : true; cell_footprint : "tri_out"; pad_drivers : 1; bond_pads : 1; @@ -4071,6 +4095,8 @@ library (sg13g2_io_slow_1p35V_3p0V_125C) { cell (sg13g2_IOPadTriOut4mA) { pad_cell : true; area : 14400; + dont_touch : true; + dont_use : true; cell_footprint : "tri_out"; pad_drivers : 1; bond_pads : 1; @@ -4596,4 +4622,77 @@ library (sg13g2_io_slow_1p35V_3p0V_125C) { related_pg_pin : vdd; } } + cell (sg13g2_IOPadAnalog) { + area: 14400; + dont_touch : true; + dont_use : true; + timing_model_type : abstracted; + pad_cell : true; + pg_pin (vss) { + pg_type : primary_ground; + voltage_name : "vss"; + } + pg_pin (vdd) { + pg_type : primary_power; + voltage_name : "vdd"; + } + pg_pin (iovss) { + pg_type : primary_ground; + voltage_name : "iovss"; + } + pg_pin (iovdd) { + pg_type : primary_power; + voltage_name : "iovdd"; + } + pin (pad) { + direction : inout; + function : "(pad)"; + output_voltage : core_output; + related_ground_pin : vss; + related_power_pin : vdd; + max_capacitance : 500; + max_transition : 200; + timing () { + related_pin : "pad"; + timing_type : combinational; + cell_rise (delay_template_2x2) { + values ( \ + "1000, 1000", \ + "1000, 1000" \ + ); + } + rise_transition (delay_template_2x2) { + values ( \ + "200, 200", \ + "200, 200" \ + ); + } + cell_fall (delay_template_2x2) { + values ( \ + "1000, 1000", \ + "1000, 1000" \ + ); + } + fall_transition (delay_template_2x2) { + values ( \ + "200, 200", \ + "200, 200" \ + ); + } + } + } + pin (padres) { + direction : inout; + is_pad : false; + input_voltage : io_input; + related_ground_pin : iovss; + related_power_pin : iovdd; + max_transition : 200; + capacitance : 15.0; + rise_capacitance : 15.0; + rise_capacitance_range (12.0, 15.0); + fall_capacitance : 15.0; + fall_capacitance_range (12.0, 15.0); + } + } } diff --git a/flow/platforms/ihp-sg13g2/lib/sg13g2_io_typ_1p2V_3p3V_25C.lib b/flow/platforms/ihp-sg13g2/lib/sg13g2_io_typ_1p2V_3p3V_25C.lib index ba6b43f67a..3e1aacbff1 100644 --- a/flow/platforms/ihp-sg13g2/lib/sg13g2_io_typ_1p2V_3p3V_25C.lib +++ b/flow/platforms/ihp-sg13g2/lib/sg13g2_io_typ_1p2V_3p3V_25C.lib @@ -219,6 +219,12 @@ library (sg13g2_io_typ_1p2V_3p3V_25C) { index_1 ("0.02, 0.1, 0.17, 0.33, 0.64, 1.26, 2.5"); index_2 ("1, 3, 7, 9, 12, 15"); } + lu_table_template (delay_template_2x2) { + variable_1 : input_net_transition; + variable_2 : total_output_net_capacitance; + index_1 ("10, 200"); + index_2 ("500, 30000"); + } power_lut_template (passive_power_template_7x1_16) { variable_1 : input_transition_time; index_1 ("0.02, 0.1, 0.17, 0.33, 0.64, 1.26, 2.5"); @@ -294,6 +300,8 @@ library (sg13g2_io_typ_1p2V_3p3V_25C) { cell (sg13g2_IOPadIn) { pad_cell : true; area : 14400; + dont_touch : true; + dont_use : true; cell_footprint : "input"; pad_drivers : 1; bond_pads : 1; @@ -484,6 +492,8 @@ library (sg13g2_io_typ_1p2V_3p3V_25C) { cell (sg13g2_IOPadInOut16mA) { pad_cell : true; area : 14400; + dont_touch : true; + dont_use : true; cell_footprint : "inout"; pad_drivers : 1; bond_pads : 1; @@ -1178,6 +1188,8 @@ library (sg13g2_io_typ_1p2V_3p3V_25C) { cell (sg13g2_IOPadInOut30mA) { pad_cell : true; area : 14400; + dont_touch : true; + dont_use : true; cell_footprint : "inout"; pad_drivers : 1; bond_pads : 1; @@ -1872,6 +1884,8 @@ library (sg13g2_io_typ_1p2V_3p3V_25C) { cell (sg13g2_IOPadInOut4mA) { pad_cell : true; area : 14400; + dont_touch : true; + dont_use : true; cell_footprint : "inout"; pad_drivers : 1; bond_pads : 1; @@ -2566,6 +2580,8 @@ library (sg13g2_io_typ_1p2V_3p3V_25C) { cell (sg13g2_IOPadOut16mA) { pad_cell : true; area : 14400; + dont_touch : true; + dont_use : true; cell_footprint : "inout"; pad_drivers : 1; bond_pads : 1; @@ -2757,6 +2773,8 @@ library (sg13g2_io_typ_1p2V_3p3V_25C) { cell (sg13g2_IOPadOut30mA) { pad_cell : true; area : 14400; + dont_touch : true; + dont_use : true; cell_footprint : "inout"; pad_drivers : 1; bond_pads : 1; @@ -2948,6 +2966,8 @@ library (sg13g2_io_typ_1p2V_3p3V_25C) { cell (sg13g2_IOPadOut4mA) { pad_cell : true; area : 14400; + dont_touch : true; + dont_use : true; cell_footprint : "inout"; pad_drivers : 1; bond_pads : 1; @@ -3139,6 +3159,8 @@ library (sg13g2_io_typ_1p2V_3p3V_25C) { cell (sg13g2_IOPadTriOut16mA) { pad_cell : true; area : 14400; + dont_touch : true; + dont_use : true; cell_footprint : "tri_out"; pad_drivers : 1; bond_pads : 1; @@ -3605,6 +3627,8 @@ library (sg13g2_io_typ_1p2V_3p3V_25C) { cell (sg13g2_IOPadTriOut30mA) { pad_cell : true; area : 14400; + dont_touch : true; + dont_use : true; cell_footprint : "tri_out"; pad_drivers : 1; bond_pads : 1; @@ -4071,6 +4095,8 @@ library (sg13g2_io_typ_1p2V_3p3V_25C) { cell (sg13g2_IOPadTriOut4mA) { pad_cell : true; area : 14400; + dont_touch : true; + dont_use : true; cell_footprint : "tri_out"; pad_drivers : 1; bond_pads : 1; @@ -4596,4 +4622,77 @@ library (sg13g2_io_typ_1p2V_3p3V_25C) { related_pg_pin : vdd; } } + cell (sg13g2_IOPadAnalog) { + area: 14400; + dont_touch : true; + dont_use : true; + timing_model_type : abstracted; + pad_cell : true; + pg_pin (vss) { + pg_type : primary_ground; + voltage_name : "vss"; + } + pg_pin (vdd) { + pg_type : primary_power; + voltage_name : "vdd"; + } + pg_pin (iovss) { + pg_type : primary_ground; + voltage_name : "iovss"; + } + pg_pin (iovdd) { + pg_type : primary_power; + voltage_name : "iovdd"; + } + pin (pad) { + direction : inout; + function : "(pad)"; + output_voltage : core_output; + related_ground_pin : vss; + related_power_pin : vdd; + max_capacitance : 500; + max_transition : 200; + timing () { + related_pin : "pad"; + timing_type : combinational; + cell_rise (delay_template_2x2) { + values ( \ + "1000, 1000", \ + "1000, 1000" \ + ); + } + rise_transition (delay_template_2x2) { + values ( \ + "200, 200", \ + "200, 200" \ + ); + } + cell_fall (delay_template_2x2) { + values ( \ + "1000, 1000", \ + "1000, 1000" \ + ); + } + fall_transition (delay_template_2x2) { + values ( \ + "200, 200", \ + "200, 200" \ + ); + } + } + } + pin (padres) { + direction : inout; + is_pad : false; + input_voltage : io_input; + related_ground_pin : iovss; + related_power_pin : iovdd; + max_transition : 200; + capacitance : 15.0; + rise_capacitance : 15.0; + rise_capacitance_range (12.0, 15.0); + fall_capacitance : 15.0; + fall_capacitance_range (12.0, 15.0); + } + } } diff --git a/flow/platforms/ihp-sg13g2/lib/sg13g2_io_typ_1p5V_3p3V_25C.lib b/flow/platforms/ihp-sg13g2/lib/sg13g2_io_typ_1p5V_3p3V_25C.lib index 73e301b713..a25a135e73 100644 --- a/flow/platforms/ihp-sg13g2/lib/sg13g2_io_typ_1p5V_3p3V_25C.lib +++ b/flow/platforms/ihp-sg13g2/lib/sg13g2_io_typ_1p5V_3p3V_25C.lib @@ -219,6 +219,12 @@ library (sg13g2_io_typ_1p5V_3p3V_25C) { index_1 ("0.02, 0.1, 0.17, 0.33, 0.64, 1.26, 2.5"); index_2 ("1, 3, 7, 9, 12, 15"); } + lu_table_template (delay_template_2x2) { + variable_1 : input_net_transition; + variable_2 : total_output_net_capacitance; + index_1 ("10, 200"); + index_2 ("500, 30000"); + } power_lut_template (passive_power_template_7x1_16) { variable_1 : input_transition_time; index_1 ("0.02, 0.1, 0.17, 0.33, 0.64, 1.26, 2.5"); @@ -294,6 +300,8 @@ library (sg13g2_io_typ_1p5V_3p3V_25C) { cell (sg13g2_IOPadIn) { pad_cell : true; area : 14400; + dont_touch : true; + dont_use : true; cell_footprint : "input"; pad_drivers : 1; bond_pads : 1; @@ -484,6 +492,8 @@ library (sg13g2_io_typ_1p5V_3p3V_25C) { cell (sg13g2_IOPadInOut16mA) { pad_cell : true; area : 14400; + dont_touch : true; + dont_use : true; cell_footprint : "inout"; pad_drivers : 1; bond_pads : 1; @@ -1178,6 +1188,8 @@ library (sg13g2_io_typ_1p5V_3p3V_25C) { cell (sg13g2_IOPadInOut30mA) { pad_cell : true; area : 14400; + dont_touch : true; + dont_use : true; cell_footprint : "inout"; pad_drivers : 1; bond_pads : 1; @@ -1872,6 +1884,8 @@ library (sg13g2_io_typ_1p5V_3p3V_25C) { cell (sg13g2_IOPadInOut4mA) { pad_cell : true; area : 14400; + dont_touch : true; + dont_use : true; cell_footprint : "inout"; pad_drivers : 1; bond_pads : 1; @@ -2566,6 +2580,8 @@ library (sg13g2_io_typ_1p5V_3p3V_25C) { cell (sg13g2_IOPadOut16mA) { pad_cell : true; area : 14400; + dont_touch : true; + dont_use : true; cell_footprint : "inout"; pad_drivers : 1; bond_pads : 1; @@ -2757,6 +2773,8 @@ library (sg13g2_io_typ_1p5V_3p3V_25C) { cell (sg13g2_IOPadOut30mA) { pad_cell : true; area : 14400; + dont_touch : true; + dont_use : true; cell_footprint : "inout"; pad_drivers : 1; bond_pads : 1; @@ -2948,6 +2966,8 @@ library (sg13g2_io_typ_1p5V_3p3V_25C) { cell (sg13g2_IOPadOut4mA) { pad_cell : true; area : 14400; + dont_touch : true; + dont_use : true; cell_footprint : "inout"; pad_drivers : 1; bond_pads : 1; @@ -3139,6 +3159,8 @@ library (sg13g2_io_typ_1p5V_3p3V_25C) { cell (sg13g2_IOPadTriOut16mA) { pad_cell : true; area : 14400; + dont_touch : true; + dont_use : true; cell_footprint : "tri_out"; pad_drivers : 1; bond_pads : 1; @@ -3605,6 +3627,8 @@ library (sg13g2_io_typ_1p5V_3p3V_25C) { cell (sg13g2_IOPadTriOut30mA) { pad_cell : true; area : 14400; + dont_touch : true; + dont_use : true; cell_footprint : "tri_out"; pad_drivers : 1; bond_pads : 1; @@ -4071,6 +4095,8 @@ library (sg13g2_io_typ_1p5V_3p3V_25C) { cell (sg13g2_IOPadTriOut4mA) { pad_cell : true; area : 14400; + dont_touch : true; + dont_use : true; cell_footprint : "tri_out"; pad_drivers : 1; bond_pads : 1; @@ -4596,4 +4622,77 @@ library (sg13g2_io_typ_1p5V_3p3V_25C) { related_pg_pin : vdd; } } + cell (sg13g2_IOPadAnalog) { + area: 14400; + dont_touch : true; + dont_use : true; + timing_model_type : abstracted; + pad_cell : true; + pg_pin (vss) { + pg_type : primary_ground; + voltage_name : "vss"; + } + pg_pin (vdd) { + pg_type : primary_power; + voltage_name : "vdd"; + } + pg_pin (iovss) { + pg_type : primary_ground; + voltage_name : "iovss"; + } + pg_pin (iovdd) { + pg_type : primary_power; + voltage_name : "iovdd"; + } + pin (pad) { + direction : inout; + function : "(pad)"; + output_voltage : core_output; + related_ground_pin : vss; + related_power_pin : vdd; + max_capacitance : 500; + max_transition : 200; + timing () { + related_pin : "pad"; + timing_type : combinational; + cell_rise (delay_template_2x2) { + values ( \ + "1000, 1000", \ + "1000, 1000" \ + ); + } + rise_transition (delay_template_2x2) { + values ( \ + "200, 200", \ + "200, 200" \ + ); + } + cell_fall (delay_template_2x2) { + values ( \ + "1000, 1000", \ + "1000, 1000" \ + ); + } + fall_transition (delay_template_2x2) { + values ( \ + "200, 200", \ + "200, 200" \ + ); + } + } + } + pin (padres) { + direction : inout; + is_pad : false; + input_voltage : io_input; + related_ground_pin : iovss; + related_power_pin : iovdd; + max_transition : 200; + capacitance : 15.0; + rise_capacitance : 15.0; + rise_capacitance_range (12.0, 15.0); + fall_capacitance : 15.0; + fall_capacitance_range (12.0, 15.0); + } + } } diff --git a/flow/platforms/ihp-sg13g2/lib/sg13g2_stdcell_fast_1p32V_m40C.lib b/flow/platforms/ihp-sg13g2/lib/sg13g2_stdcell_fast_1p32V_m40C.lib index fd479d3fd1..55b7f7792f 100644 --- a/flow/platforms/ihp-sg13g2/lib/sg13g2_stdcell_fast_1p32V_m40C.lib +++ b/flow/platforms/ihp-sg13g2/lib/sg13g2_stdcell_fast_1p32V_m40C.lib @@ -18,8 +18,8 @@ library (sg13g2_stdcell_fast_1p32V_m40C) { comment : "IHP Microelectronics GmbH, 2025"; - date : "$Date: Fri Jun 13 14:42:35 2025 $"; - revision : "$Revision: 0.1.3 $"; + date : "$Date: Tue Nov 4 20:01:33 2025 $"; + revision : "$Revision: 0.1.4 $"; delay_model : table_lookup; capacitive_load_unit (1,pf); current_unit : "1uA"; @@ -210,7 +210,7 @@ library (sg13g2_stdcell_fast_1p32V_m40C) { } cell (sg13g2_a21o_1) { area : 12.7008; - cell_footprint : "AO21"; + cell_footprint : "a21o"; cell_leakage_power : 357.438; leakage_power () { value : 353.267; @@ -483,7 +483,7 @@ library (sg13g2_stdcell_fast_1p32V_m40C) { } timing () { related_pin : "B1"; - sdf_cond : "A1 == 1'b1 & A2 == 1'b0"; + sdf_cond : "A1 == 1'b1 && A2 == 1'b0"; timing_sense : positive_unate; timing_type : combinational; when : "(A1 * !A2)"; @@ -542,7 +542,7 @@ library (sg13g2_stdcell_fast_1p32V_m40C) { } timing () { related_pin : "B1"; - sdf_cond : "A1 == 1'b0 & A2 == 1'b1"; + sdf_cond : "A1 == 1'b0 && A2 == 1'b1"; timing_sense : positive_unate; timing_type : combinational; when : "(!A1 * A2)"; @@ -601,7 +601,7 @@ library (sg13g2_stdcell_fast_1p32V_m40C) { } timing () { related_pin : "B1"; - sdf_cond : "A1 == 1'b0 & A2 == 1'b0"; + sdf_cond : "A1 == 1'b0 && A2 == 1'b0"; timing_sense : positive_unate; timing_type : combinational; when : "(!A1 * !A2)"; @@ -958,32 +958,32 @@ library (sg13g2_stdcell_fast_1p32V_m40C) { max_transition : 2.5074; capacitance : 0.0029376; rise_capacitance : 0.00287835; - rise_capacitance_range (0.00287835, 0.00287835); + rise_capacitance_range (0.00264548, 0.00304931); fall_capacitance : 0.00299685; - fall_capacitance_range (0.00299685, 0.00299685); + fall_capacitance_range (0.00253588, 0.00331871); } pin (A2) { direction : "input"; max_transition : 2.5074; capacitance : 0.00304896; rise_capacitance : 0.00308254; - rise_capacitance_range (0.00308254, 0.00308254); + rise_capacitance_range (0.00265247, 0.00332671); fall_capacitance : 0.00301538; - fall_capacitance_range (0.00301538, 0.00301538); + fall_capacitance_range (0.00262349, 0.00327491); } pin (B1) { direction : "input"; max_transition : 2.5074; capacitance : 0.00284024; rise_capacitance : 0.00292906; - rise_capacitance_range (0.00292906, 0.00292906); + rise_capacitance_range (0.0024562, 0.00327754); fall_capacitance : 0.00275142; - fall_capacitance_range (0.00275142, 0.00275142); + fall_capacitance_range (0.00248127, 0.00301178); } } cell (sg13g2_a21o_2) { area : 14.5152; - cell_footprint : "AO21"; + cell_footprint : "a21o"; cell_leakage_power : 496.685; leakage_power () { value : 512.719; @@ -1256,7 +1256,7 @@ library (sg13g2_stdcell_fast_1p32V_m40C) { } timing () { related_pin : "B1"; - sdf_cond : "A1 == 1'b1 & A2 == 1'b0"; + sdf_cond : "A1 == 1'b1 && A2 == 1'b0"; timing_sense : positive_unate; timing_type : combinational; when : "(A1 * !A2)"; @@ -1315,7 +1315,7 @@ library (sg13g2_stdcell_fast_1p32V_m40C) { } timing () { related_pin : "B1"; - sdf_cond : "A1 == 1'b0 & A2 == 1'b1"; + sdf_cond : "A1 == 1'b0 && A2 == 1'b1"; timing_sense : positive_unate; timing_type : combinational; when : "(!A1 * A2)"; @@ -1374,7 +1374,7 @@ library (sg13g2_stdcell_fast_1p32V_m40C) { } timing () { related_pin : "B1"; - sdf_cond : "A1 == 1'b0 & A2 == 1'b0"; + sdf_cond : "A1 == 1'b0 && A2 == 1'b0"; timing_sense : positive_unate; timing_type : combinational; when : "(!A1 * !A2)"; @@ -1731,27 +1731,27 @@ library (sg13g2_stdcell_fast_1p32V_m40C) { max_transition : 2.5074; capacitance : 0.00312547; rise_capacitance : 0.00304478; - rise_capacitance_range (0.00304478, 0.00304478); + rise_capacitance_range (0.00280666, 0.00324627); fall_capacitance : 0.00320615; - fall_capacitance_range (0.00320615, 0.00320615); + fall_capacitance_range (0.00275675, 0.00349997); } pin (A2) { direction : "input"; max_transition : 2.5074; capacitance : 0.00314666; rise_capacitance : 0.00316916; - rise_capacitance_range (0.00316916, 0.00316916); + rise_capacitance_range (0.00269701, 0.00344459); fall_capacitance : 0.00312416; - fall_capacitance_range (0.00312416, 0.00312416); + fall_capacitance_range (0.00274278, 0.0033653); } pin (B1) { direction : "input"; max_transition : 2.5074; capacitance : 0.0029621; rise_capacitance : 0.00303815; - rise_capacitance_range (0.00303815, 0.00303815); + rise_capacitance_range (0.00260713, 0.00342029); fall_capacitance : 0.00288605; - fall_capacitance_range (0.00288605, 0.00288605); + fall_capacitance_range (0.00265437, 0.00308866); } } cell (sg13g2_a21oi_1) { @@ -1767,11 +1767,11 @@ library (sg13g2_stdcell_fast_1p32V_m40C) { when : "!A1&!A2&B1&!Y"; } leakage_power () { - value : 280.264; + value : 280.265; when : "!A1&A2&!B1&Y"; } leakage_power () { - value : 347.811; + value : 347.812; when : "!A1&A2&B1&!Y"; } leakage_power () { @@ -1783,11 +1783,11 @@ library (sg13g2_stdcell_fast_1p32V_m40C) { when : "A1&!A2&B1&!Y"; } leakage_power () { - value : 302.597; + value : 302.598; when : "A1&A2&!B1&!Y"; } leakage_power () { - value : 382.443; + value : 382.444; when : "A1&A2&B1&!Y"; } pin (Y) { @@ -1803,52 +1803,52 @@ library (sg13g2_stdcell_fast_1p32V_m40C) { index_1 ("0.0186, 0.0966, 0.174, 0.3294, 0.6408, 1.263, 2.5074"); index_2 ("0.001, 0.0234, 0.039, 0.0648, 0.108, 0.18, 0.3"); values ( \ - "0.0321895, 0.115682, 0.172508, 0.266026, 0.422702, 0.684047, 1.11931", \ - "0.0483141, 0.142592, 0.200082, 0.294082, 0.451031, 0.712872, 1.14789", \ - "0.0556102, 0.163869, 0.22446, 0.319876, 0.477114, 0.738787, 1.17439", \ - "0.0632149, 0.197029, 0.26542, 0.367849, 0.529242, 0.791604, 1.22731", \ - "0.0711775, 0.244744, 0.326631, 0.444597, 0.620835, 0.893481, 1.33251", \ - "0.0809747, 0.308938, 0.414895, 0.559783, 0.767142, 1.0715, 1.53452", \ - "0.0852206, 0.387967, 0.528299, 0.718311, 0.979366, 1.3411, 1.8705" \ + "0.0321875, 0.115685, 0.172504, 0.266032, 0.423042, 0.684045, 1.11932", \ + "0.048314, 0.14256, 0.200104, 0.294067, 0.451029, 0.71288, 1.14791", \ + "0.0556101, 0.163869, 0.22446, 0.319875, 0.477107, 0.738777, 1.17439", \ + "0.0632148, 0.197029, 0.26542, 0.367849, 0.529242, 0.791603, 1.22722", \ + "0.0711775, 0.244744, 0.32663, 0.444596, 0.620834, 0.893481, 1.33251", \ + "0.0809747, 0.308938, 0.414787, 0.559783, 0.767143, 1.0715, 1.53452", \ + "0.0852205, 0.387967, 0.528303, 0.718311, 0.979365, 1.3411, 1.87049" \ ); } rise_transition (TIMING_DELAY_7x7ds1) { index_1 ("0.0186, 0.0966, 0.174, 0.3294, 0.6408, 1.263, 2.5074"); index_2 ("0.001, 0.0234, 0.039, 0.0648, 0.108, 0.18, 0.3"); values ( \ - "0.0183832, 0.133347, 0.213631, 0.346185, 0.568623, 0.938744, 1.55596", \ - "0.0283872, 0.137323, 0.21518, 0.346538, 0.568624, 0.939032, 1.55597", \ - "0.0379943, 0.147737, 0.222926, 0.350667, 0.56967, 0.939875, 1.55598", \ - "0.0563831, 0.17261, 0.246213, 0.36906, 0.580438, 0.942475, 1.56094", \ - "0.0872224, 0.219092, 0.29467, 0.416157, 0.620619, 0.968844, 1.56742", \ - "0.134025, 0.298981, 0.383943, 0.511235, 0.717795, 1.05685, 1.63063", \ - "0.208977, 0.428465, 0.5358, 0.681768, 0.901564, 1.25037, 1.81549" \ + "0.0183814, 0.133348, 0.213631, 0.346354, 0.568473, 0.938743, 1.55595", \ + "0.0283867, 0.137287, 0.215266, 0.347979, 0.568732, 0.939034, 1.55596", \ + "0.0379943, 0.147737, 0.222925, 0.350667, 0.569394, 0.939865, 1.55596", \ + "0.056383, 0.17261, 0.246213, 0.36906, 0.580438, 0.942474, 1.5565", \ + "0.0872223, 0.219092, 0.29467, 0.416157, 0.620631, 0.968844, 1.56774", \ + "0.134025, 0.298981, 0.383634, 0.511234, 0.717796, 1.05663, 1.63063", \ + "0.208977, 0.428465, 0.535798, 0.681768, 0.901564, 1.25036, 1.81549" \ ); } cell_fall (TIMING_DELAY_7x7ds1) { index_1 ("0.0186, 0.0966, 0.174, 0.3294, 0.6408, 1.263, 2.5074"); index_2 ("0.001, 0.0234, 0.039, 0.0648, 0.108, 0.18, 0.3"); values ( \ - "0.0296871, 0.0951098, 0.13906, 0.211504, 0.332489, 0.534208, 0.870146", \ - "0.0515782, 0.1329, 0.178437, 0.251149, 0.372122, 0.573677, 0.909421", \ - "0.0655212, 0.163334, 0.214063, 0.290635, 0.412972, 0.614419, 0.950178", \ - "0.0841367, 0.207691, 0.269446, 0.357518, 0.489273, 0.694902, 1.03087", \ - "0.110536, 0.269421, 0.347583, 0.456934, 0.612429, 0.840628, 1.18754", \ - "0.148352, 0.353474, 0.456303, 0.598213, 0.794158, 1.0694, 1.46683", \ - "0.203508, 0.47388, 0.604137, 0.789607, 1.04763, 1.39904, 1.89053" \ + "0.0296879, 0.0951124, 0.139163, 0.211465, 0.332491, 0.534207, 0.870144", \ + "0.0515782, 0.132909, 0.178438, 0.251154, 0.372124, 0.573745, 0.909405", \ + "0.0655212, 0.163334, 0.214063, 0.290635, 0.412972, 0.614463, 0.950178", \ + "0.0841367, 0.207691, 0.269446, 0.357518, 0.489273, 0.694901, 1.03087", \ + "0.110536, 0.269421, 0.347583, 0.456928, 0.612429, 0.840633, 1.1875", \ + "0.148351, 0.353474, 0.456303, 0.598212, 0.794158, 1.0694, 1.46683", \ + "0.203508, 0.473881, 0.604137, 0.789607, 1.04763, 1.39904, 1.89053" \ ); } fall_transition (TIMING_DELAY_7x7ds1) { index_1 ("0.0186, 0.0966, 0.174, 0.3294, 0.6408, 1.263, 2.5074"); index_2 ("0.001, 0.0234, 0.039, 0.0648, 0.108, 0.18, 0.3"); values ( \ - "0.020796, 0.105921, 0.165323, 0.264069, 0.429158, 0.704202, 1.16255", \ - "0.0350208, 0.115712, 0.170983, 0.265954, 0.429159, 0.704203, 1.16256", \ - "0.0462035, 0.133016, 0.186906, 0.277196, 0.434775, 0.707586, 1.16257", \ - "0.0643545, 0.167097, 0.22264, 0.311512, 0.460871, 0.719307, 1.16656", \ - "0.0935084, 0.221476, 0.287255, 0.381525, 0.531818, 0.777463, 1.2014", \ - "0.141109, 0.307904, 0.388658, 0.502731, 0.666794, 0.922449, 1.33024", \ - "0.221154, 0.442251, 0.546519, 0.691549, 0.893824, 1.18661, 1.6162" \ + "0.0207958, 0.105921, 0.165673, 0.263953, 0.429158, 0.704202, 1.16255", \ + "0.0350207, 0.115728, 0.171181, 0.265958, 0.429671, 0.704638, 1.16256", \ + "0.0462034, 0.133016, 0.186906, 0.277196, 0.434775, 0.705376, 1.16257", \ + "0.0643545, 0.167097, 0.22264, 0.311512, 0.460867, 0.719307, 1.16656", \ + "0.0935084, 0.221476, 0.287255, 0.381508, 0.531818, 0.777475, 1.20141", \ + "0.141109, 0.307904, 0.388657, 0.502731, 0.666798, 0.922449, 1.33024", \ + "0.221154, 0.44225, 0.546519, 0.691549, 0.893824, 1.18662, 1.6162" \ ); } } @@ -1860,52 +1860,52 @@ library (sg13g2_stdcell_fast_1p32V_m40C) { index_1 ("0.0186, 0.0966, 0.174, 0.3294, 0.6408, 1.263, 2.5074"); index_2 ("0.001, 0.0234, 0.039, 0.0648, 0.108, 0.18, 0.3"); values ( \ - "0.0376724, 0.120791, 0.177765, 0.271912, 0.429429, 0.691267, 1.12854", \ - "0.0566463, 0.148347, 0.205786, 0.299936, 0.45758, 0.720289, 1.15647", \ - "0.0662646, 0.170317, 0.230569, 0.326015, 0.483636, 0.745947, 1.18348", \ - "0.0775267, 0.204715, 0.27222, 0.374285, 0.535884, 0.799112, 1.23629", \ - "0.0917629, 0.254619, 0.335162, 0.452233, 0.62822, 0.900961, 1.34139", \ - "0.112129, 0.323971, 0.42637, 0.569732, 0.775618, 1.0795, 1.54335", \ - "0.1351, 0.413364, 0.549306, 0.734664, 0.991705, 1.35262, 1.87879" \ + "0.0376695, 0.120779, 0.177753, 0.272029, 0.429433, 0.691155, 1.12854", \ + "0.0566463, 0.148347, 0.20578, 0.299938, 0.45758, 0.720292, 1.15646", \ + "0.0662645, 0.170317, 0.230569, 0.326009, 0.483627, 0.745949, 1.18348", \ + "0.0775266, 0.204715, 0.27222, 0.374284, 0.535883, 0.799111, 1.23628", \ + "0.0917628, 0.254619, 0.335162, 0.452233, 0.628226, 0.90096, 1.34139", \ + "0.112129, 0.323971, 0.42637, 0.569732, 0.775619, 1.0795, 1.54335", \ + "0.1351, 0.413364, 0.549305, 0.734664, 0.991705, 1.35262, 1.87879" \ ); } rise_transition (TIMING_DELAY_7x7ds1) { index_1 ("0.0186, 0.0966, 0.174, 0.3294, 0.6408, 1.263, 2.5074"); index_2 ("0.001, 0.0234, 0.039, 0.0648, 0.108, 0.18, 0.3"); values ( \ - "0.0238832, 0.139797, 0.220638, 0.353995, 0.577119, 0.949364, 1.56904", \ - "0.0332763, 0.14361, 0.222125, 0.355021, 0.577264, 0.949372, 1.56942", \ - "0.042693, 0.153568, 0.229493, 0.358195, 0.578164, 0.951568, 1.56943", \ - "0.0608892, 0.178019, 0.252122, 0.376141, 0.588679, 0.952757, 1.57026", \ - "0.0904915, 0.223668, 0.300054, 0.422547, 0.628372, 0.978565, 1.58044", \ - "0.134994, 0.303038, 0.387194, 0.517005, 0.724177, 1.06625, 1.64302", \ - "0.204545, 0.427287, 0.534034, 0.682837, 0.906786, 1.25772, 1.82698" \ + "0.0238913, 0.139906, 0.220585, 0.353812, 0.577118, 0.948852, 1.56904", \ + "0.0332762, 0.14361, 0.22209, 0.355064, 0.577264, 0.949374, 1.56941", \ + "0.0426929, 0.153615, 0.229493, 0.358112, 0.578236, 0.95157, 1.56942", \ + "0.0608891, 0.178019, 0.252122, 0.376141, 0.588677, 0.952756, 1.57046", \ + "0.0904915, 0.223668, 0.300054, 0.422547, 0.628278, 0.97859, 1.58043", \ + "0.134994, 0.303038, 0.387195, 0.517006, 0.724157, 1.06625, 1.64302", \ + "0.204545, 0.427287, 0.534033, 0.682836, 0.906786, 1.25772, 1.82698" \ ); } cell_fall (TIMING_DELAY_7x7ds1) { index_1 ("0.0186, 0.0966, 0.174, 0.3294, 0.6408, 1.263, 2.5074"); index_2 ("0.001, 0.0234, 0.039, 0.0648, 0.108, 0.18, 0.3"); values ( \ - "0.0322622, 0.0973542, 0.14129, 0.213664, 0.334769, 0.53621, 0.872082", \ - "0.0524778, 0.128111, 0.17329, 0.246078, 0.367209, 0.56881, 0.904727", \ - "0.0654827, 0.153648, 0.202199, 0.277615, 0.399882, 0.601732, 0.937706", \ - "0.0819142, 0.192316, 0.248677, 0.331986, 0.460674, 0.665512, 1.00211", \ - "0.105224, 0.247994, 0.318184, 0.416688, 0.56206, 0.782353, 1.12713", \ + "0.0322614, 0.0973554, 0.141291, 0.213663, 0.334772, 0.536211, 0.872081", \ + "0.0524778, 0.128111, 0.17329, 0.246072, 0.367238, 0.568789, 0.904733", \ + "0.0654827, 0.153647, 0.202199, 0.277614, 0.399883, 0.601732, 0.937706", \ + "0.0819142, 0.192316, 0.248677, 0.331986, 0.460674, 0.665511, 1.00211", \ + "0.105224, 0.247994, 0.318184, 0.416688, 0.56206, 0.782352, 1.12713", \ "0.138578, 0.325439, 0.417099, 0.543275, 0.719572, 0.974059, 1.35146", \ - "0.18525, 0.436311, 0.553516, 0.719688, 0.949565, 1.26578, 1.70929" \ + "0.18525, 0.436311, 0.553516, 0.719688, 0.949564, 1.26578, 1.70929" \ ); } fall_transition (TIMING_DELAY_7x7ds1) { index_1 ("0.0186, 0.0966, 0.174, 0.3294, 0.6408, 1.263, 2.5074"); index_2 ("0.001, 0.0234, 0.039, 0.0648, 0.108, 0.18, 0.3"); values ( \ - "0.0202431, 0.106142, 0.165435, 0.264066, 0.429154, 0.704231, 1.16269", \ - "0.0298109, 0.111851, 0.168838, 0.26521, 0.429706, 0.704232, 1.1627", \ - "0.0394446, 0.123479, 0.178858, 0.272373, 0.432637, 0.705119, 1.16271", \ - "0.0572589, 0.148385, 0.203767, 0.295031, 0.449232, 0.713641, 1.16459", \ - "0.0863281, 0.192816, 0.25226, 0.344807, 0.497391, 0.751787, 1.18721", \ - "0.13236, 0.26698, 0.337325, 0.439259, 0.597755, 0.85095, 1.27374", \ - "0.205674, 0.386911, 0.473778, 0.598582, 0.780757, 1.0508, 1.47423" \ + "0.0202496, 0.106145, 0.165435, 0.26426, 0.429154, 0.704225, 1.16269", \ + "0.0298109, 0.111851, 0.168838, 0.265257, 0.429758, 0.704226, 1.1627", \ + "0.0394447, 0.123479, 0.178857, 0.272372, 0.432625, 0.705119, 1.16271", \ + "0.0572589, 0.148385, 0.203766, 0.295031, 0.449232, 0.713642, 1.16459", \ + "0.0863281, 0.192816, 0.25226, 0.344808, 0.497391, 0.751787, 1.18721", \ + "0.13236, 0.26698, 0.337325, 0.439259, 0.597754, 0.85095, 1.27374", \ + "0.205674, 0.386911, 0.473779, 0.598581, 0.780757, 1.05079, 1.47423" \ ); } } @@ -1919,38 +1919,38 @@ library (sg13g2_stdcell_fast_1p32V_m40C) { index_1 ("0.0186, 0.0966, 0.174, 0.3294, 0.6408, 1.263, 2.5074"); index_2 ("0.001, 0.0234, 0.039, 0.0648, 0.108, 0.18, 0.3"); values ( \ - "0.0308137, 0.115234, 0.17239, 0.266549, 0.423985, 0.686404, 1.12346", \ - "0.0509151, 0.148943, 0.206539, 0.30077, 0.458461, 0.721242, 1.15763", \ - "0.0622967, 0.177535, 0.239146, 0.334993, 0.492395, 0.754557, 1.19268", \ - "0.0778135, 0.221585, 0.293998, 0.399765, 0.56275, 0.825516, 1.26213", \ - "0.098901, 0.283021, 0.373012, 0.500281, 0.684769, 0.961472, 1.40147", \ - "0.128615, 0.367237, 0.483583, 0.644251, 0.87212, 1.19467, 1.67044", \ - "0.169407, 0.479763, 0.631397, 0.841094, 1.13116, 1.53699, 2.10598" \ + "0.0308081, 0.115219, 0.172533, 0.266549, 0.423989, 0.686404, 1.12347", \ + "0.050915, 0.148943, 0.206539, 0.30081, 0.458464, 0.721239, 1.15763", \ + "0.0622966, 0.177535, 0.239145, 0.334999, 0.492386, 0.754485, 1.19268", \ + "0.0778134, 0.221584, 0.293998, 0.399764, 0.562749, 0.825538, 1.26214", \ + "0.098901, 0.283021, 0.373012, 0.500281, 0.684759, 0.961471, 1.40147", \ + "0.128615, 0.367237, 0.483583, 0.64425, 0.872116, 1.19467, 1.67069", \ + "0.169407, 0.479763, 0.631396, 0.841093, 1.13116, 1.53699, 2.10598" \ ); } rise_transition (TIMING_DELAY_7x7ds1) { index_1 ("0.0186, 0.0966, 0.174, 0.3294, 0.6408, 1.263, 2.5074"); index_2 ("0.001, 0.0234, 0.039, 0.0648, 0.108, 0.18, 0.3"); values ( \ - "0.0243036, 0.139787, 0.22058, 0.353748, 0.57728, 0.949077, 1.56895", \ - "0.038713, 0.146507, 0.223305, 0.354962, 0.577281, 0.949429, 1.56952", \ - "0.0494385, 0.162717, 0.235569, 0.360883, 0.578785, 0.951334, 1.57064", \ - "0.0663741, 0.197091, 0.270155, 0.389528, 0.596271, 0.954914, 1.57065", \ - "0.0936841, 0.254124, 0.335004, 0.457607, 0.657528, 0.996412, 1.58753", \ - "0.139545, 0.344419, 0.441742, 0.583463, 0.793723, 1.12826, 1.68576", \ - "0.21683, 0.485551, 0.610657, 0.77999, 1.03237, 1.39437, 1.96011" \ + "0.0243176, 0.139775, 0.220729, 0.353748, 0.577279, 0.949077, 1.56895", \ + "0.038713, 0.146507, 0.223305, 0.354633, 0.57728, 0.9494, 1.56951", \ + "0.0494384, 0.162717, 0.235568, 0.360776, 0.578776, 0.949401, 1.57064", \ + "0.0663741, 0.19709, 0.270154, 0.389528, 0.59627, 0.955035, 1.57198", \ + "0.093684, 0.254124, 0.335004, 0.457606, 0.65768, 0.996406, 1.58751", \ + "0.139545, 0.344419, 0.441742, 0.583462, 0.793702, 1.12826, 1.68595", \ + "0.21683, 0.485551, 0.610656, 0.77999, 1.03237, 1.39437, 1.96011" \ ); } cell_fall (TIMING_DELAY_7x7ds1) { index_1 ("0.0186, 0.0966, 0.174, 0.3294, 0.6408, 1.263, 2.5074"); index_2 ("0.001, 0.0234, 0.039, 0.0648, 0.108, 0.18, 0.3"); values ( \ - "0.0168842, 0.0534109, 0.0767692, 0.115317, 0.179989, 0.287124, 0.466115", \ - "0.0316487, 0.0918308, 0.119924, 0.16136, 0.226549, 0.333882, 0.512554", \ - "0.0400216, 0.118344, 0.152984, 0.200927, 0.271648, 0.381415, 0.560367", \ - "0.0499813, 0.155748, 0.201055, 0.262238, 0.346657, 0.468494, 0.653785", \ - "0.0620243, 0.2047, 0.267186, 0.348882, 0.45834, 0.607248, 0.819587", \ - "0.076046, 0.268809, 0.35416, 0.467726, 0.617202, 0.813192, 1.07826", \ + "0.0168842, 0.0534228, 0.0767643, 0.115324, 0.179991, 0.287121, 0.466053", \ + "0.0316487, 0.0918308, 0.119935, 0.161367, 0.226546, 0.333857, 0.512553", \ + "0.0400216, 0.118344, 0.152984, 0.200927, 0.271648, 0.381415, 0.560368", \ + "0.0499813, 0.155748, 0.201055, 0.262238, 0.346657, 0.468495, 0.65376", \ + "0.0620243, 0.2047, 0.26719, 0.348882, 0.458345, 0.607254, 0.819633", \ + "0.076046, 0.268809, 0.354161, 0.467726, 0.617202, 0.813192, 1.07826", \ "0.0913731, 0.352373, 0.467508, 0.619523, 0.82797, 1.1009, 1.45488" \ ); } @@ -1958,13 +1958,13 @@ library (sg13g2_stdcell_fast_1p32V_m40C) { index_1 ("0.0186, 0.0966, 0.174, 0.3294, 0.6408, 1.263, 2.5074"); index_2 ("0.001, 0.0234, 0.039, 0.0648, 0.108, 0.18, 0.3"); values ( \ - "0.0123114, 0.056938, 0.0892943, 0.142389, 0.232137, 0.380984, 0.629846", \ - "0.0303159, 0.0739708, 0.102313, 0.150405, 0.235121, 0.381544, 0.629847", \ - "0.0435487, 0.0930379, 0.122113, 0.169136, 0.249274, 0.389182, 0.63179", \ - "0.0647707, 0.126374, 0.159822, 0.209289, 0.288777, 0.420519, 0.650292", \ - "0.0989181, 0.179984, 0.221189, 0.280098, 0.365676, 0.500647, 0.718302", \ - "0.1548, 0.265158, 0.319959, 0.395702, 0.500398, 0.648888, 0.87847", \ - "0.248808, 0.402429, 0.476396, 0.579069, 0.717291, 0.904329, 1.16793" \ + "0.0123113, 0.0569457, 0.0892889, 0.142356, 0.232137, 0.381159, 0.629822", \ + "0.0303159, 0.0739708, 0.102327, 0.150405, 0.235122, 0.381418, 0.629823", \ + "0.0435487, 0.0930379, 0.122113, 0.169136, 0.249274, 0.389182, 0.631791", \ + "0.0647707, 0.126375, 0.159822, 0.209289, 0.288777, 0.420519, 0.650196", \ + "0.0989181, 0.179984, 0.22119, 0.280098, 0.365673, 0.500556, 0.718161", \ + "0.1548, 0.265158, 0.31996, 0.395702, 0.500398, 0.648888, 0.878471", \ + "0.248808, 0.402428, 0.476396, 0.579069, 0.717291, 0.90433, 1.16793" \ ); } } @@ -1978,12 +1978,12 @@ library (sg13g2_stdcell_fast_1p32V_m40C) { index_1 ("0.0186, 0.0966, 0.174, 0.3294, 0.6408, 1.263, 2.5074"); index_2 ("0.001, 0.0234, 0.039, 0.0648, 0.108, 0.18, 0.3"); values ( \ - "0.0244425, 0.108432, 0.165314, 0.259087, 0.415833, 0.677068, 1.11235", \ - "0.0401629, 0.141908, 0.19944, 0.293225, 0.450206, 0.711887, 1.14653", \ - "0.0492152, 0.169727, 0.231718, 0.327503, 0.484117, 0.745475, 1.1809", \ - "0.0611031, 0.21211, 0.285471, 0.391737, 0.554445, 0.816219, 1.25106", \ - "0.0771845, 0.271048, 0.362554, 0.491036, 0.675789, 0.951995, 1.39054", \ - "0.0997262, 0.351294, 0.470264, 0.63211, 0.861217, 1.18423, 1.65892", \ + "0.0244427, 0.108436, 0.165301, 0.259086, 0.415834, 0.677115, 1.11234", \ + "0.0401759, 0.141908, 0.19944, 0.293241, 0.450207, 0.711868, 1.14654", \ + "0.0492152, 0.169727, 0.231718, 0.327502, 0.484134, 0.745487, 1.18091", \ + "0.0611031, 0.21211, 0.285471, 0.391737, 0.554469, 0.816219, 1.25094", \ + "0.0771845, 0.271047, 0.362554, 0.491036, 0.675788, 0.951994, 1.39054", \ + "0.0997261, 0.35137, 0.470264, 0.632109, 0.861217, 1.18423, 1.6589", \ "0.130921, 0.459495, 0.613905, 0.825775, 1.11711, 1.52347, 2.09272" \ ); } @@ -1991,39 +1991,39 @@ library (sg13g2_stdcell_fast_1p32V_m40C) { index_1 ("0.0186, 0.0966, 0.174, 0.3294, 0.6408, 1.263, 2.5074"); index_2 ("0.001, 0.0234, 0.039, 0.0648, 0.108, 0.18, 0.3"); values ( \ - "0.0193325, 0.133406, 0.213563, 0.346466, 0.568481, 0.93878, 1.55592", \ - "0.0337026, 0.140712, 0.216634, 0.34697, 0.568482, 0.939179, 1.55649", \ - "0.043449, 0.15732, 0.229584, 0.353711, 0.570371, 0.939896, 1.5565", \ - "0.0591849, 0.192037, 0.264665, 0.383052, 0.587993, 0.944987, 1.55651", \ - "0.084589, 0.248464, 0.329911, 0.451992, 0.650249, 0.987215, 1.57511", \ - "0.128132, 0.338628, 0.435382, 0.576417, 0.786766, 1.11952, 1.67385", \ - "0.204113, 0.479043, 0.60568, 0.773668, 1.02256, 1.38623, 1.94789" \ + "0.0193325, 0.13343, 0.213533, 0.346466, 0.568481, 0.938783, 1.55592", \ + "0.0337486, 0.14071, 0.216679, 0.34681, 0.568482, 0.939167, 1.55649", \ + "0.043449, 0.157319, 0.229587, 0.353711, 0.57026, 0.93992, 1.5565", \ + "0.0591849, 0.192037, 0.264665, 0.383051, 0.588107, 0.944974, 1.56312", \ + "0.0845891, 0.248464, 0.32991, 0.451993, 0.650231, 0.987215, 1.57511", \ + "0.128132, 0.338806, 0.435382, 0.576416, 0.786765, 1.11952, 1.67374", \ + "0.204113, 0.479043, 0.605679, 0.773668, 1.02256, 1.38623, 1.94782" \ ); } cell_fall (TIMING_DELAY_7x7ds1) { index_1 ("0.0186, 0.0966, 0.174, 0.3294, 0.6408, 1.263, 2.5074"); index_2 ("0.001, 0.0234, 0.039, 0.0648, 0.108, 0.18, 0.3"); values ( \ - "0.016614, 0.0531014, 0.0763735, 0.11479, 0.179243, 0.286105, 0.464904", \ - "0.030821, 0.0913117, 0.119424, 0.160772, 0.22588, 0.332902, 0.511258", \ - "0.0387632, 0.117706, 0.152312, 0.200233, 0.270848, 0.380362, 0.558976", \ - "0.0476557, 0.154614, 0.200039, 0.261271, 0.345652, 0.467324, 0.652438", \ - "0.0575246, 0.202675, 0.265413, 0.347106, 0.456779, 0.605744, 0.818493", \ - "0.0665144, 0.26502, 0.350858, 0.464854, 0.61479, 0.810922, 1.07623", \ - "0.0696352, 0.344911, 0.461473, 0.615045, 0.823954, 1.09809, 1.45224" \ + "0.016614, 0.053105, 0.0763725, 0.114797, 0.179233, 0.286103, 0.464903", \ + "0.030821, 0.0913117, 0.119424, 0.160774, 0.225867, 0.332866, 0.511271", \ + "0.0387632, 0.117706, 0.152312, 0.200233, 0.270848, 0.380363, 0.558977", \ + "0.0476557, 0.154614, 0.200039, 0.261272, 0.345652, 0.467324, 0.652397", \ + "0.0575246, 0.202675, 0.26543, 0.347106, 0.45677, 0.605749, 0.818493", \ + "0.0665144, 0.26502, 0.350858, 0.464854, 0.614961, 0.810922, 1.07623", \ + "0.0696353, 0.344911, 0.461473, 0.615046, 0.823954, 1.09809, 1.45224" \ ); } fall_transition (TIMING_DELAY_7x7ds1) { index_1 ("0.0186, 0.0966, 0.174, 0.3294, 0.6408, 1.263, 2.5074"); index_2 ("0.001, 0.0234, 0.039, 0.0648, 0.108, 0.18, 0.3"); values ( \ - "0.00913605, 0.0532466, 0.0852843, 0.138753, 0.228526, 0.377598, 0.626574", \ - "0.0226421, 0.0699875, 0.0987064, 0.146826, 0.231493, 0.378067, 0.627343", \ - "0.0331187, 0.0884606, 0.118117, 0.165405, 0.245642, 0.385578, 0.628431", \ - "0.0499284, 0.120516, 0.155281, 0.205113, 0.285162, 0.417137, 0.646781", \ - "0.0773665, 0.17271, 0.214934, 0.275441, 0.361684, 0.497409, 0.715097", \ - "0.123517, 0.253867, 0.311584, 0.390012, 0.495162, 0.645701, 0.875612", \ - "0.204236, 0.387565, 0.462987, 0.56953, 0.712658, 0.899547, 1.16283" \ + "0.00913607, 0.0532515, 0.0854191, 0.138776, 0.22851, 0.377598, 0.626574", \ + "0.0226421, 0.0699875, 0.0987065, 0.146823, 0.231551, 0.378095, 0.627342", \ + "0.0331187, 0.0884607, 0.118117, 0.165405, 0.245642, 0.385578, 0.628432", \ + "0.0499284, 0.120516, 0.155281, 0.205113, 0.285161, 0.417137, 0.64671", \ + "0.0773665, 0.17271, 0.215225, 0.275441, 0.361668, 0.496928, 0.715098", \ + "0.123517, 0.253867, 0.311584, 0.390012, 0.495321, 0.645701, 0.875612", \ + "0.204236, 0.387564, 0.462987, 0.56953, 0.712658, 0.899547, 1.16283" \ ); } } @@ -2037,52 +2037,52 @@ library (sg13g2_stdcell_fast_1p32V_m40C) { index_1 ("0.0186, 0.0966, 0.174, 0.3294, 0.6408, 1.263, 2.5074"); index_2 ("0.001, 0.0234, 0.039, 0.0648, 0.108, 0.18, 0.3"); values ( \ - "0.0206385, 0.0832203, 0.125253, 0.194604, 0.310649, 0.504163, 0.826273", \ - "0.0352597, 0.118914, 0.162862, 0.232537, 0.348522, 0.542386, 0.863894", \ - "0.0433072, 0.145898, 0.195642, 0.269461, 0.38637, 0.579557, 0.901668", \ - "0.0530852, 0.185261, 0.246739, 0.332768, 0.459776, 0.656576, 0.978693", \ - "0.0654625, 0.23859, 0.31776, 0.42632, 0.577826, 0.796151, 1.12926", \ - "0.0809791, 0.308948, 0.414638, 0.556677, 0.751031, 1.01916, 1.39968", \ - "0.099041, 0.398283, 0.538682, 0.728521, 0.986374, 1.33349, 1.81342" \ + "0.0206389, 0.0832102, 0.125253, 0.194606, 0.310656, 0.504163, 0.826279", \ + "0.0352597, 0.118914, 0.162848, 0.232526, 0.348575, 0.542335, 0.863873", \ + "0.0433072, 0.145897, 0.195642, 0.26946, 0.386384, 0.579477, 0.901664", \ + "0.0530851, 0.185261, 0.246739, 0.332768, 0.459776, 0.656581, 0.978691", \ + "0.0654624, 0.23859, 0.31776, 0.426319, 0.577826, 0.79615, 1.12926", \ + "0.080979, 0.308948, 0.414638, 0.556676, 0.75103, 1.01916, 1.39983", \ + "0.0990408, 0.398283, 0.538682, 0.728521, 0.986369, 1.33349, 1.81342" \ ); } rise_transition (TIMING_DELAY_7x7ds1) { index_1 ("0.0186, 0.0966, 0.174, 0.3294, 0.6408, 1.263, 2.5074"); index_2 ("0.001, 0.0234, 0.039, 0.0648, 0.108, 0.18, 0.3"); values ( \ - "0.0148966, 0.0993205, 0.159526, 0.259155, 0.425871, 0.703759, 1.1669", \ - "0.0294314, 0.110389, 0.1655, 0.260946, 0.426012, 0.70448, 1.16691", \ - "0.0394162, 0.128705, 0.181718, 0.272002, 0.430517, 0.704481, 1.16724", \ - "0.0550501, 0.164038, 0.219437, 0.307374, 0.456716, 0.717198, 1.16972", \ - "0.0795104, 0.219657, 0.285052, 0.379518, 0.52819, 0.775097, 1.20279", \ - "0.121918, 0.308223, 0.389657, 0.504455, 0.669179, 0.921242, 1.33011", \ - "0.197218, 0.442999, 0.554945, 0.702771, 0.901895, 1.19185, 1.62246" \ + "0.0148959, 0.0992949, 0.159525, 0.259159, 0.425824, 0.703759, 1.1669", \ + "0.0294314, 0.110397, 0.165466, 0.261029, 0.426058, 0.70443, 1.16691", \ + "0.0394162, 0.128715, 0.181718, 0.272002, 0.430633, 0.704431, 1.16724", \ + "0.0550501, 0.164038, 0.219436, 0.307374, 0.456716, 0.717244, 1.16971", \ + "0.0795103, 0.219657, 0.28505, 0.379518, 0.528189, 0.775097, 1.20279", \ + "0.121918, 0.308223, 0.389657, 0.504455, 0.669179, 0.921241, 1.33041", \ + "0.197218, 0.442999, 0.554945, 0.70277, 0.901891, 1.19185, 1.62246" \ ); } cell_fall (TIMING_DELAY_7x7ds1) { index_1 ("0.0186, 0.0966, 0.174, 0.3294, 0.6408, 1.263, 2.5074"); index_2 ("0.001, 0.0234, 0.039, 0.0648, 0.108, 0.18, 0.3"); values ( \ - "0.0163784, 0.0529463, 0.076218, 0.114624, 0.179076, 0.285957, 0.464418", \ - "0.0306432, 0.0910901, 0.119156, 0.160517, 0.225592, 0.33267, 0.511029", \ + "0.0163784, 0.0529383, 0.076209, 0.114606, 0.179085, 0.28595, 0.464749", \ + "0.0306432, 0.0910901, 0.119166, 0.160517, 0.225598, 0.33262, 0.511029", \ "0.038924, 0.117462, 0.152007, 0.199972, 0.270621, 0.380136, 0.558882", \ - "0.0487362, 0.154515, 0.199855, 0.261037, 0.34541, 0.467108, 0.652164", \ - "0.060787, 0.203352, 0.26577, 0.347223, 0.456711, 0.605467, 0.818341", \ - "0.0744693, 0.268683, 0.353005, 0.466173, 0.61563, 0.811264, 1.07648", \ - "0.0885975, 0.354906, 0.468743, 0.620349, 0.827771, 1.10037, 1.45333" \ + "0.0487362, 0.154515, 0.199855, 0.261037, 0.34541, 0.467108, 0.652104", \ + "0.060787, 0.203352, 0.26577, 0.347223, 0.456711, 0.60553, 0.81837", \ + "0.0744694, 0.268683, 0.353005, 0.466173, 0.61563, 0.811265, 1.07648", \ + "0.0885976, 0.354906, 0.468743, 0.620349, 0.827771, 1.10037, 1.45333" \ ); } fall_transition (TIMING_DELAY_7x7ds1) { index_1 ("0.0186, 0.0966, 0.174, 0.3294, 0.6408, 1.263, 2.5074"); index_2 ("0.001, 0.0234, 0.039, 0.0648, 0.108, 0.18, 0.3"); values ( \ - "0.00924645, 0.0532653, 0.085416, 0.138721, 0.228653, 0.377635, 0.626699", \ - "0.022823, 0.0701199, 0.0988094, 0.14688, 0.231574, 0.378073, 0.627347", \ - "0.0330934, 0.0886672, 0.11837, 0.165572, 0.245751, 0.385692, 0.62846", \ - "0.0494943, 0.120687, 0.155234, 0.205213, 0.285088, 0.416992, 0.646706", \ - "0.0760641, 0.172195, 0.215167, 0.275107, 0.361737, 0.497443, 0.715226", \ - "0.121147, 0.250933, 0.3103, 0.389395, 0.494758, 0.644875, 0.875516", \ - "0.201171, 0.380702, 0.458101, 0.56519, 0.706951, 0.897458, 1.16734" \ + "0.00924648, 0.0532571, 0.0853271, 0.13902, 0.228659, 0.377634, 0.626573", \ + "0.022823, 0.0701198, 0.0987531, 0.14688, 0.231566, 0.377892, 0.627347", \ + "0.0330934, 0.0886673, 0.11837, 0.165572, 0.245751, 0.385692, 0.62846", \ + "0.0494943, 0.120687, 0.155234, 0.205214, 0.285088, 0.416993, 0.646751", \ + "0.0760641, 0.172195, 0.215167, 0.275107, 0.361737, 0.497061, 0.715186", \ + "0.121147, 0.250933, 0.310301, 0.389395, 0.494758, 0.644875, 0.875517", \ + "0.201171, 0.380702, 0.458101, 0.56519, 0.706954, 0.897459, 1.16734" \ ); } } @@ -2094,38 +2094,38 @@ library (sg13g2_stdcell_fast_1p32V_m40C) { index_1 ("0.0186, 0.0966, 0.174, 0.3294, 0.6408, 1.263, 2.5074"); index_2 ("0.001, 0.0234, 0.039, 0.0648, 0.108, 0.18, 0.3"); values ( \ - "0.0308137, 0.115234, 0.17239, 0.266549, 0.423985, 0.686404, 1.12346", \ - "0.0509151, 0.148943, 0.206539, 0.30077, 0.458461, 0.721242, 1.15763", \ - "0.0622967, 0.177535, 0.239146, 0.334993, 0.492395, 0.754557, 1.19268", \ - "0.0778135, 0.221585, 0.293998, 0.399765, 0.56275, 0.825516, 1.26213", \ - "0.098901, 0.283021, 0.373012, 0.500281, 0.684769, 0.961472, 1.40147", \ - "0.128615, 0.367237, 0.483583, 0.644251, 0.87212, 1.19467, 1.67044", \ - "0.169407, 0.479763, 0.631397, 0.841094, 1.13116, 1.53699, 2.10598" \ + "0.0308081, 0.115219, 0.172533, 0.266549, 0.423989, 0.686404, 1.12347", \ + "0.050915, 0.148943, 0.206539, 0.30081, 0.458464, 0.721239, 1.15763", \ + "0.0622966, 0.177535, 0.239145, 0.334999, 0.492386, 0.754485, 1.19268", \ + "0.0778134, 0.221584, 0.293998, 0.399764, 0.562749, 0.825538, 1.26214", \ + "0.098901, 0.283021, 0.373012, 0.500281, 0.684759, 0.961471, 1.40147", \ + "0.128615, 0.367237, 0.483583, 0.64425, 0.872116, 1.19467, 1.67069", \ + "0.169407, 0.479763, 0.631396, 0.841093, 1.13116, 1.53699, 2.10598" \ ); } rise_transition (TIMING_DELAY_7x7ds1) { index_1 ("0.0186, 0.0966, 0.174, 0.3294, 0.6408, 1.263, 2.5074"); index_2 ("0.001, 0.0234, 0.039, 0.0648, 0.108, 0.18, 0.3"); values ( \ - "0.0243036, 0.139787, 0.22058, 0.353748, 0.57728, 0.949077, 1.56895", \ - "0.038713, 0.146507, 0.223305, 0.354962, 0.577281, 0.949429, 1.56952", \ - "0.0494385, 0.162717, 0.235569, 0.360883, 0.578785, 0.951334, 1.57064", \ - "0.0663741, 0.197091, 0.270155, 0.389528, 0.596271, 0.954914, 1.57065", \ - "0.0936841, 0.254124, 0.335004, 0.457607, 0.657528, 0.996412, 1.58753", \ - "0.139545, 0.344419, 0.441742, 0.583463, 0.793723, 1.12826, 1.68576", \ - "0.21683, 0.485551, 0.610657, 0.77999, 1.03237, 1.39437, 1.96011" \ + "0.0243176, 0.139775, 0.220729, 0.353748, 0.577279, 0.949077, 1.56895", \ + "0.038713, 0.146507, 0.223305, 0.354633, 0.57728, 0.9494, 1.56951", \ + "0.0494384, 0.162717, 0.235568, 0.360776, 0.578776, 0.949401, 1.57064", \ + "0.0663741, 0.19709, 0.270154, 0.389528, 0.59627, 0.955035, 1.57198", \ + "0.093684, 0.254124, 0.335004, 0.457606, 0.65768, 0.996406, 1.58751", \ + "0.139545, 0.344419, 0.441742, 0.583462, 0.793702, 1.12826, 1.68595", \ + "0.21683, 0.485551, 0.610656, 0.77999, 1.03237, 1.39437, 1.96011" \ ); } cell_fall (TIMING_DELAY_7x7ds1) { index_1 ("0.0186, 0.0966, 0.174, 0.3294, 0.6408, 1.263, 2.5074"); index_2 ("0.001, 0.0234, 0.039, 0.0648, 0.108, 0.18, 0.3"); values ( \ - "0.0168842, 0.0534109, 0.0767692, 0.115317, 0.179989, 0.287124, 0.466115", \ - "0.0316487, 0.0918308, 0.119924, 0.16136, 0.226549, 0.333882, 0.512554", \ - "0.0400216, 0.118344, 0.152984, 0.200927, 0.271648, 0.381415, 0.560367", \ - "0.0499813, 0.155748, 0.201055, 0.262238, 0.346657, 0.468494, 0.653785", \ - "0.0620243, 0.2047, 0.267186, 0.348882, 0.45834, 0.607248, 0.819587", \ - "0.076046, 0.268809, 0.35416, 0.467726, 0.617202, 0.813192, 1.07826", \ + "0.0168842, 0.0534228, 0.0767643, 0.115324, 0.179991, 0.287121, 0.466053", \ + "0.0316487, 0.0918308, 0.119935, 0.161367, 0.226546, 0.333857, 0.512553", \ + "0.0400216, 0.118344, 0.152984, 0.200927, 0.271648, 0.381415, 0.560368", \ + "0.0499813, 0.155748, 0.201055, 0.262238, 0.346657, 0.468495, 0.65376", \ + "0.0620243, 0.2047, 0.26719, 0.348882, 0.458345, 0.607254, 0.819633", \ + "0.076046, 0.268809, 0.354161, 0.467726, 0.617202, 0.813192, 1.07826", \ "0.0913731, 0.352373, 0.467508, 0.619523, 0.82797, 1.1009, 1.45488" \ ); } @@ -2133,13 +2133,13 @@ library (sg13g2_stdcell_fast_1p32V_m40C) { index_1 ("0.0186, 0.0966, 0.174, 0.3294, 0.6408, 1.263, 2.5074"); index_2 ("0.001, 0.0234, 0.039, 0.0648, 0.108, 0.18, 0.3"); values ( \ - "0.0123114, 0.056938, 0.0892943, 0.142389, 0.232137, 0.380984, 0.629846", \ - "0.0303159, 0.0739708, 0.102313, 0.150405, 0.235121, 0.381544, 0.629847", \ - "0.0435487, 0.0930379, 0.122113, 0.169136, 0.249274, 0.389182, 0.63179", \ - "0.0647707, 0.126374, 0.159822, 0.209289, 0.288777, 0.420519, 0.650292", \ - "0.0989181, 0.179984, 0.221189, 0.280098, 0.365676, 0.500647, 0.718302", \ - "0.1548, 0.265158, 0.319959, 0.395702, 0.500398, 0.648888, 0.87847", \ - "0.248808, 0.402429, 0.476396, 0.579069, 0.717291, 0.904329, 1.16793" \ + "0.0123113, 0.0569457, 0.0892889, 0.142356, 0.232137, 0.381159, 0.629822", \ + "0.0303159, 0.0739708, 0.102327, 0.150405, 0.235122, 0.381418, 0.629823", \ + "0.0435487, 0.0930379, 0.122113, 0.169136, 0.249274, 0.389182, 0.631791", \ + "0.0647707, 0.126375, 0.159822, 0.209289, 0.288777, 0.420519, 0.650196", \ + "0.0989181, 0.179984, 0.22119, 0.280098, 0.365673, 0.500556, 0.718161", \ + "0.1548, 0.265158, 0.31996, 0.395702, 0.500398, 0.648888, 0.878471", \ + "0.248808, 0.402428, 0.476396, 0.579069, 0.717291, 0.90433, 1.16793" \ ); } } @@ -2149,26 +2149,26 @@ library (sg13g2_stdcell_fast_1p32V_m40C) { index_1 ("0.0186, 0.0966, 0.174, 0.3294, 0.6408, 1.263, 2.5074"); index_2 ("0.001, 0.0234, 0.039, 0.0648, 0.108, 0.18, 0.3"); values ( \ - "0.00548231, 0.00592512, 0.00592338, 0.00585125, 0.0057413, 0.00545959, 0.00508418", \ - "0.00523441, 0.00566623, 0.00566589, 0.00569156, 0.00563974, 0.00546354, 0.00506628", \ - "0.00539807, 0.00552455, 0.00567787, 0.00564218, 0.00557506, 0.00550012, 0.00500404", \ - "0.00623996, 0.00579024, 0.00571615, 0.0057042, 0.00580951, 0.00530736, 0.00546395", \ - "0.00867047, 0.00708217, 0.00673969, 0.00642837, 0.00609279, 0.00596445, 0.00527309", \ - "0.0144146, 0.0109768, 0.0100856, 0.00909538, 0.00830223, 0.00729244, 0.00706747", \ - "0.0264606, 0.0210433, 0.0189911, 0.0169053, 0.0146533, 0.0126367, 0.0106714" \ + "0.00548013, 0.00592536, 0.0059224, 0.00586766, 0.0057591, 0.00546001, 0.00508478", \ + "0.00523488, 0.00563732, 0.00567562, 0.00580661, 0.00567085, 0.00546142, 0.00504078", \ + "0.00539872, 0.00552363, 0.00567788, 0.00564447, 0.00555239, 0.00549921, 0.00500278", \ + "0.00624053, 0.00579024, 0.00571605, 0.00570421, 0.00580958, 0.00537608, 0.00505937", \ + "0.00866992, 0.00708169, 0.00673889, 0.00643008, 0.00605642, 0.00609162, 0.00529837", \ + "0.0144163, 0.0109772, 0.0100823, 0.00909537, 0.0083163, 0.00733596, 0.00700528", \ + "0.0264605, 0.0210437, 0.0189913, 0.0169058, 0.0146467, 0.0126197, 0.010589" \ ); } fall_power (POWER_7x7ds1) { index_1 ("0.0186, 0.0966, 0.174, 0.3294, 0.6408, 1.263, 2.5074"); index_2 ("0.001, 0.0234, 0.039, 0.0648, 0.108, 0.18, 0.3"); values ( \ - "0.00357723, 0.00372422, 0.00368174, 0.00361723, 0.00348432, 0.00327164, 0.00289373", \ - "0.00346601, 0.00354813, 0.0035991, 0.0035265, 0.00337314, 0.00319243, 0.00275227", \ - "0.00385655, 0.0036327, 0.00358744, 0.00360798, 0.00340072, 0.00342518, 0.00276129", \ - "0.00501743, 0.00415565, 0.00401493, 0.00378018, 0.0037035, 0.00331059, 0.00285811", \ - "0.00766797, 0.00583378, 0.00535392, 0.00491334, 0.00431198, 0.00389504, 0.00347839", \ - "0.0134614, 0.0101084, 0.00902473, 0.00784781, 0.00677298, 0.00583495, 0.00437932", \ - "0.025502, 0.0205466, 0.0185013, 0.0160502, 0.0134316, 0.0112836, 0.0091128" \ + "0.00357969, 0.00372432, 0.00371493, 0.00360631, 0.00348419, 0.0032721, 0.00289375", \ + "0.0034613, 0.00355082, 0.00367504, 0.00352713, 0.00344776, 0.00325534, 0.00275064", \ + "0.00385629, 0.00363264, 0.00358733, 0.00362364, 0.0034008, 0.00319826, 0.00276117", \ + "0.0050136, 0.00415583, 0.0040157, 0.00378725, 0.0037183, 0.00331059, 0.00285817", \ + "0.00766756, 0.00583379, 0.00535204, 0.0049123, 0.00431198, 0.00390844, 0.00347966", \ + "0.0134619, 0.0101086, 0.00902475, 0.00784782, 0.0067809, 0.00583455, 0.00437188", \ + "0.0255017, 0.0205466, 0.0185013, 0.0160502, 0.0134319, 0.0112869, 0.0091128" \ ); } } @@ -2178,26 +2178,26 @@ library (sg13g2_stdcell_fast_1p32V_m40C) { index_1 ("0.0186, 0.0966, 0.174, 0.3294, 0.6408, 1.263, 2.5074"); index_2 ("0.001, 0.0234, 0.039, 0.0648, 0.108, 0.18, 0.3"); values ( \ - "0.00576288, 0.00583632, 0.00581207, 0.0057547, 0.00559689, 0.00532953, 0.00540594", \ - "0.00556511, 0.0057776, 0.00569903, 0.00569679, 0.00554889, 0.00532661, 0.00541775", \ - "0.00569615, 0.00568854, 0.00574196, 0.00568543, 0.00552806, 0.00556326, 0.00534628", \ - "0.00642686, 0.00600898, 0.0058741, 0.00578951, 0.00565982, 0.00538661, 0.00546431", \ - "0.00870741, 0.00731723, 0.00697165, 0.00662542, 0.00620655, 0.00615177, 0.00532798", \ - "0.0142272, 0.0113563, 0.0103638, 0.00944291, 0.0085456, 0.00744679, 0.00706978", \ - "0.0258174, 0.0214287, 0.0195453, 0.017446, 0.0152124, 0.0131048, 0.0107123" \ + "0.0057633, 0.00584107, 0.0058031, 0.00573779, 0.00559721, 0.00532159, 0.00540594", \ + "0.0055655, 0.0057776, 0.0057015, 0.00570576, 0.00554909, 0.00534409, 0.00541682", \ + "0.00569568, 0.00568754, 0.00574197, 0.00571847, 0.00551956, 0.00556334, 0.00534431", \ + "0.00642579, 0.00600874, 0.0058741, 0.00578948, 0.00576471, 0.00538688, 0.00503752", \ + "0.00870753, 0.00731723, 0.00696844, 0.00662539, 0.00622215, 0.00587627, 0.00536257", \ + "0.0142279, 0.011357, 0.0103639, 0.00944415, 0.00857333, 0.00744686, 0.00707727", \ + "0.025814, 0.0214287, 0.0195454, 0.0174461, 0.0152173, 0.0131071, 0.0107508" \ ); } fall_power (POWER_7x7ds1) { index_1 ("0.0186, 0.0966, 0.174, 0.3294, 0.6408, 1.263, 2.5074"); index_2 ("0.001, 0.0234, 0.039, 0.0648, 0.108, 0.18, 0.3"); values ( \ - "0.00570651, 0.00580254, 0.00571421, 0.00563874, 0.00551174, 0.00527286, 0.00485641", \ - "0.00544222, 0.00557998, 0.00563091, 0.00552511, 0.00547796, 0.00517954, 0.00483826", \ - "0.0055815, 0.00563541, 0.00555377, 0.00566877, 0.00541691, 0.00520845, 0.00481184", \ - "0.0063906, 0.00595116, 0.00587378, 0.00574588, 0.00567072, 0.00521257, 0.0048129", \ - "0.00874248, 0.00723055, 0.00685618, 0.00658665, 0.00618331, 0.00576409, 0.00602356", \ - "0.0142398, 0.0111501, 0.0101591, 0.0090832, 0.00837306, 0.00736707, 0.0062934", \ - "0.0257935, 0.0209698, 0.0189581, 0.0167157, 0.0145237, 0.0125394, 0.0105594" \ + "0.00570766, 0.00580103, 0.00571826, 0.00565512, 0.00551102, 0.00527253, 0.00485805", \ + "0.00544151, 0.00558, 0.00563175, 0.00552718, 0.00545982, 0.00519717, 0.00480906", \ + "0.00558691, 0.00563524, 0.00555382, 0.00566974, 0.00541802, 0.00520847, 0.00481197", \ + "0.00638923, 0.00595137, 0.00587707, 0.00574591, 0.00567156, 0.00521509, 0.00481792", \ + "0.00874248, 0.00722961, 0.00685687, 0.00658728, 0.00617307, 0.00576404, 0.0060256", \ + "0.0142402, 0.01115, 0.0101591, 0.00908328, 0.00837322, 0.00735874, 0.00628185", \ + "0.0257936, 0.0209697, 0.0189571, 0.0167154, 0.014523, 0.0125386, 0.0105721" \ ); } } @@ -2208,26 +2208,26 @@ library (sg13g2_stdcell_fast_1p32V_m40C) { index_1 ("0.0186, 0.0966, 0.174, 0.3294, 0.6408, 1.263, 2.5074"); index_2 ("0.001, 0.0234, 0.039, 0.0648, 0.108, 0.18, 0.3"); values ( \ - "0.00294532, 0.00334681, 0.00336152, 0.00330564, 0.0032042, 0.00295147, 0.00301317", \ - "0.00311131, 0.00316078, 0.00316114, 0.00318371, 0.00307681, 0.0028826, 0.00296287", \ - "0.00365467, 0.00325097, 0.00330652, 0.00315345, 0.00304741, 0.00309195, 0.00260429", \ - "0.00504651, 0.00403463, 0.00376095, 0.00353301, 0.00333358, 0.00311482, 0.00294944", \ - "0.00789616, 0.00595428, 0.00538777, 0.00475459, 0.00415528, 0.00363531, 0.00327403", \ - "0.0141676, 0.0107183, 0.00957501, 0.00847415, 0.00722698, 0.00577675, 0.00487678", \ - "0.0272985, 0.0217551, 0.0196859, 0.0174498, 0.01515, 0.0125084, 0.00980895" \ + "0.00294668, 0.00334666, 0.00337865, 0.00330605, 0.00320319, 0.00295052, 0.00302073", \ + "0.00311135, 0.00316121, 0.00316136, 0.00314555, 0.0030752, 0.0029268, 0.00296144", \ + "0.00365427, 0.00325018, 0.00330839, 0.00314844, 0.00304693, 0.00283986, 0.00260404", \ + "0.00504702, 0.00404144, 0.00376095, 0.00355013, 0.00333358, 0.00311057, 0.0027992", \ + "0.007897, 0.00595478, 0.00538839, 0.00475459, 0.00420277, 0.00363712, 0.00329944", \ + "0.0141671, 0.0107181, 0.00957533, 0.00847414, 0.0072301, 0.00577754, 0.00524927", \ + "0.0272974, 0.0217551, 0.0196858, 0.0174502, 0.0151501, 0.0124736, 0.00980804" \ ); } fall_power (POWER_7x7ds1) { index_1 ("0.0186, 0.0966, 0.174, 0.3294, 0.6408, 1.263, 2.5074"); index_2 ("0.001, 0.0234, 0.039, 0.0648, 0.108, 0.18, 0.3"); values ( \ - "0.00418784, 0.00478812, 0.00485666, 0.00475974, 0.00470876, 0.00441173, 0.00409178", \ - "0.004239, 0.00458007, 0.0046212, 0.00473685, 0.00460569, 0.00440605, 0.00403788", \ - "0.00479013, 0.00464978, 0.00469298, 0.00464092, 0.0047277, 0.00449922, 0.00399251", \ - "0.00620877, 0.00510632, 0.00504935, 0.00498269, 0.00467059, 0.00454187, 0.00418838", \ - "0.00922487, 0.00684297, 0.00644187, 0.0059604, 0.00564161, 0.00504356, 0.00450237", \ - "0.015696, 0.0115327, 0.0102486, 0.00906609, 0.00789983, 0.00707896, 0.00622881", \ - "0.0289602, 0.0227575, 0.0203821, 0.017738, 0.0150247, 0.0124315, 0.0107083" \ + "0.00418866, 0.00478648, 0.00485598, 0.00474753, 0.00470923, 0.00443316, 0.00406448", \ + "0.00423889, 0.00458009, 0.00463126, 0.00475875, 0.00460492, 0.00438139, 0.004089", \ + "0.00479028, 0.00465026, 0.00469295, 0.00462929, 0.0047277, 0.00449922, 0.00399277", \ + "0.00620818, 0.00510642, 0.00504935, 0.00497041, 0.00467059, 0.00454181, 0.00442258", \ + "0.00922496, 0.0068431, 0.00644188, 0.00596039, 0.0056475, 0.00497044, 0.00449706", \ + "0.0156958, 0.0115327, 0.0102487, 0.00906622, 0.00789983, 0.00707436, 0.00622874", \ + "0.0289602, 0.0227575, 0.0203824, 0.017738, 0.015025, 0.0124314, 0.010723" \ ); } } @@ -2238,26 +2238,26 @@ library (sg13g2_stdcell_fast_1p32V_m40C) { index_1 ("0.0186, 0.0966, 0.174, 0.3294, 0.6408, 1.263, 2.5074"); index_2 ("0.001, 0.0234, 0.039, 0.0648, 0.108, 0.18, 0.3"); values ( \ - "0.00260334, 0.00313396, 0.0031485, 0.00313011, 0.00297238, 0.00274466, 0.00231277", \ - "0.00293993, 0.00295417, 0.00291417, 0.00293613, 0.00286657, 0.0027303, 0.00233749", \ - "0.0035801, 0.00303668, 0.00308218, 0.00298313, 0.00285029, 0.00274957, 0.00229092", \ - "0.00506863, 0.00387328, 0.00355194, 0.00335497, 0.00316282, 0.00284193, 0.00229242", \ - "0.00807277, 0.00584082, 0.00525924, 0.00462911, 0.00398451, 0.00358805, 0.00274618", \ - "0.0145391, 0.0107139, 0.00949265, 0.00828519, 0.00708588, 0.00549963, 0.00488532", \ - "0.0278592, 0.0219188, 0.0198005, 0.017454, 0.0149814, 0.0124039, 0.00965656" \ + "0.00260126, 0.0031336, 0.00314558, 0.00313049, 0.00297213, 0.0027458, 0.00231149", \ + "0.0029436, 0.00295595, 0.00291644, 0.00293495, 0.00286097, 0.00271979, 0.00233859", \ + "0.00358011, 0.00303821, 0.00308901, 0.00298294, 0.00283663, 0.00274195, 0.00228981", \ + "0.00506916, 0.00387212, 0.0035486, 0.00335505, 0.00310957, 0.00285062, 0.00296401", \ + "0.0080724, 0.00584061, 0.00525913, 0.00462965, 0.00396242, 0.00353772, 0.0027469", \ + "0.0145402, 0.0107207, 0.00949274, 0.00828482, 0.00708575, 0.00549925, 0.0049276", \ + "0.0278606, 0.0219182, 0.0198004, 0.0174542, 0.0149812, 0.012404, 0.00960272" \ ); } fall_power (POWER_7x7ds1) { index_1 ("0.0186, 0.0966, 0.174, 0.3294, 0.6408, 1.263, 2.5074"); index_2 ("0.001, 0.0234, 0.039, 0.0648, 0.108, 0.18, 0.3"); values ( \ - "0.00207088, 0.00270742, 0.00268969, 0.0026411, 0.0025905, 0.00234456, 0.00206193", \ - "0.00214509, 0.00248999, 0.00252984, 0.00263925, 0.00251655, 0.00231922, 0.00227153", \ - "0.00270589, 0.00254808, 0.00259826, 0.00257548, 0.00259611, 0.00221267, 0.00191154", \ - "0.00417556, 0.00303504, 0.00295855, 0.0029033, 0.00266788, 0.00255448, 0.00227727", \ - "0.00725077, 0.00478432, 0.00434245, 0.00388293, 0.00354772, 0.00302698, 0.0022946", \ - "0.0137812, 0.0094417, 0.00816589, 0.00703378, 0.00583399, 0.0050843, 0.00418747", \ - "0.0272116, 0.0207627, 0.0183342, 0.0157622, 0.0131101, 0.0104936, 0.00859526" \ + "0.00207087, 0.0026899, 0.00270692, 0.002649, 0.00258962, 0.00234291, 0.00206185", \ + "0.00214557, 0.00248897, 0.00252983, 0.00263931, 0.00255716, 0.00229279, 0.00227579", \ + "0.00270575, 0.00254807, 0.0025967, 0.00257579, 0.00259644, 0.00224893, 0.00191154", \ + "0.00417559, 0.00303512, 0.00295855, 0.00289729, 0.00266794, 0.00255467, 0.00237749", \ + "0.00725095, 0.0047841, 0.00435114, 0.00388301, 0.00356536, 0.00296909, 0.0022946", \ + "0.0137812, 0.00944169, 0.00816633, 0.00703352, 0.00585458, 0.00511159, 0.0041876", \ + "0.027211, 0.0207626, 0.0183352, 0.0157623, 0.0131102, 0.0104936, 0.00860438" \ ); } } @@ -2268,26 +2268,26 @@ library (sg13g2_stdcell_fast_1p32V_m40C) { index_1 ("0.0186, 0.0966, 0.174, 0.3294, 0.6408, 1.263, 2.5074"); index_2 ("0.001, 0.0234, 0.039, 0.0648, 0.108, 0.18, 0.3"); values ( \ - "0.00261301, 0.00312408, 0.00314479, 0.00311576, 0.00298892, 0.00275417, 0.00274468", \ - "0.00299623, 0.00293288, 0.00296966, 0.00294356, 0.00286239, 0.00277412, 0.00268157", \ - "0.00369381, 0.00310022, 0.00304914, 0.0030567, 0.00285512, 0.00262453, 0.00270455", \ - "0.0052816, 0.00399384, 0.00368722, 0.00335695, 0.00332787, 0.00298493, 0.00271823", \ - "0.00848073, 0.0061053, 0.00544279, 0.00483386, 0.00408406, 0.00373204, 0.0032468", \ - "0.0153021, 0.0113123, 0.0100824, 0.00876916, 0.00750135, 0.00599796, 0.00457909", \ - "0.0293702, 0.0232801, 0.0210469, 0.0186317, 0.015922, 0.0132243, 0.0105137" \ + "0.00261296, 0.00312453, 0.00314482, 0.00311242, 0.00299654, 0.00275454, 0.00274531", \ + "0.00299836, 0.00293146, 0.00297414, 0.00293456, 0.00286717, 0.00277082, 0.00260081", \ + "0.00369337, 0.00308815, 0.00304914, 0.00305715, 0.00286702, 0.00262908, 0.00270265", \ + "0.00528141, 0.00399383, 0.00369662, 0.00335696, 0.00325443, 0.00291625, 0.00271823", \ + "0.00848033, 0.00610619, 0.00543875, 0.00484126, 0.00408406, 0.00373197, 0.00324832", \ + "0.0153021, 0.0113121, 0.0100827, 0.00876846, 0.00749987, 0.00600014, 0.00467315", \ + "0.0293697, 0.0232801, 0.0210469, 0.0186317, 0.0159202, 0.0132244, 0.0105139" \ ); } fall_power (POWER_7x7ds1) { index_1 ("0.0186, 0.0966, 0.174, 0.3294, 0.6408, 1.263, 2.5074"); index_2 ("0.001, 0.0234, 0.039, 0.0648, 0.108, 0.18, 0.3"); values ( \ - "0.00196954, 0.00260707, 0.00260461, 0.00254093, 0.00251942, 0.00223369, 0.00191331", \ - "0.00211555, 0.00236308, 0.00238553, 0.00248736, 0.00237179, 0.0021922, 0.00212671", \ - "0.00271749, 0.0024405, 0.00247975, 0.00238786, 0.00248609, 0.00222894, 0.00179766", \ - "0.00432452, 0.00300865, 0.00287507, 0.00276829, 0.00244644, 0.00241451, 0.00216866", \ - "0.00760174, 0.00491371, 0.00444775, 0.0039241, 0.00352107, 0.00286091, 0.00219989", \ - "0.0145198, 0.00993733, 0.00857922, 0.00736844, 0.00610119, 0.00510993, 0.00425575", \ - "0.0286883, 0.0219379, 0.019361, 0.0166354, 0.0137015, 0.010999, 0.00953458" \ + "0.00196977, 0.00260475, 0.00259132, 0.00260552, 0.00252205, 0.00223328, 0.00196594", \ + "0.00211588, 0.00236304, 0.00238075, 0.00249847, 0.0024178, 0.00214312, 0.00212672", \ + "0.0027174, 0.0024405, 0.00247021, 0.00237599, 0.00248596, 0.00216188, 0.00179766", \ + "0.00432495, 0.0030089, 0.00287459, 0.00276837, 0.00244617, 0.00241451, 0.00229839", \ + "0.00760103, 0.0049137, 0.00444827, 0.00392424, 0.00351991, 0.00293387, 0.00219963", \ + "0.0145263, 0.00993738, 0.00857967, 0.00736844, 0.00610141, 0.00511049, 0.00426384", \ + "0.0286883, 0.0219382, 0.019361, 0.0166354, 0.0137014, 0.0109989, 0.00953375" \ ); } } @@ -2297,26 +2297,26 @@ library (sg13g2_stdcell_fast_1p32V_m40C) { index_1 ("0.0186, 0.0966, 0.174, 0.3294, 0.6408, 1.263, 2.5074"); index_2 ("0.001, 0.0234, 0.039, 0.0648, 0.108, 0.18, 0.3"); values ( \ - "0.00294532, 0.00334681, 0.00336152, 0.00330564, 0.0032042, 0.00295147, 0.00301317", \ - "0.00311131, 0.00316078, 0.00316114, 0.00318371, 0.00307681, 0.0028826, 0.00296287", \ - "0.00365467, 0.00325097, 0.00330652, 0.00315345, 0.00304741, 0.00309195, 0.00260429", \ - "0.00504651, 0.00403463, 0.00376095, 0.00353301, 0.00333358, 0.00311482, 0.00294944", \ - "0.00789616, 0.00595428, 0.00538777, 0.00475459, 0.00415528, 0.00363531, 0.00327403", \ - "0.0141676, 0.0107183, 0.00957501, 0.00847415, 0.00722698, 0.00577675, 0.00487678", \ - "0.0272985, 0.0217551, 0.0196859, 0.0174498, 0.01515, 0.0125084, 0.00980895" \ + "0.00294668, 0.00334666, 0.00337865, 0.00330605, 0.00320319, 0.00295052, 0.00302073", \ + "0.00311135, 0.00316121, 0.00316136, 0.00314555, 0.0030752, 0.0029268, 0.00296144", \ + "0.00365427, 0.00325018, 0.00330839, 0.00314844, 0.00304693, 0.00283986, 0.00260404", \ + "0.00504702, 0.00404144, 0.00376095, 0.00355013, 0.00333358, 0.00311057, 0.0027992", \ + "0.007897, 0.00595478, 0.00538839, 0.00475459, 0.00420277, 0.00363712, 0.00329944", \ + "0.0141671, 0.0107181, 0.00957533, 0.00847414, 0.0072301, 0.00577754, 0.00524927", \ + "0.0272974, 0.0217551, 0.0196858, 0.0174502, 0.0151501, 0.0124736, 0.00980804" \ ); } fall_power (POWER_7x7ds1) { index_1 ("0.0186, 0.0966, 0.174, 0.3294, 0.6408, 1.263, 2.5074"); index_2 ("0.001, 0.0234, 0.039, 0.0648, 0.108, 0.18, 0.3"); values ( \ - "0.00196954, 0.00260707, 0.00260461, 0.00254093, 0.00251942, 0.00223369, 0.00191331", \ - "0.00211555, 0.00236308, 0.00238553, 0.00248736, 0.00237179, 0.0021922, 0.00212671", \ - "0.00271749, 0.0024405, 0.00247975, 0.00238786, 0.00248609, 0.00222894, 0.00179766", \ - "0.00432452, 0.00300865, 0.00287507, 0.00276829, 0.00244644, 0.00241451, 0.00216866", \ - "0.00760174, 0.00491371, 0.00444775, 0.0039241, 0.00352107, 0.00286091, 0.00219989", \ - "0.0145198, 0.00993733, 0.00857922, 0.00736844, 0.00610119, 0.00510993, 0.00425575", \ - "0.0286883, 0.0219379, 0.019361, 0.0166354, 0.0137015, 0.010999, 0.00953458" \ + "0.00196977, 0.00260475, 0.00259132, 0.00260552, 0.00252205, 0.00223328, 0.00196594", \ + "0.00211588, 0.00236304, 0.00238075, 0.00249847, 0.0024178, 0.00214312, 0.00212672", \ + "0.0027174, 0.0024405, 0.00247021, 0.00237599, 0.00248596, 0.00216188, 0.00179766", \ + "0.00432495, 0.0030089, 0.00287459, 0.00276837, 0.00244617, 0.00241451, 0.00229839", \ + "0.00760103, 0.0049137, 0.00444827, 0.00392424, 0.00351991, 0.00293387, 0.00219963", \ + "0.0145263, 0.00993738, 0.00857967, 0.00736844, 0.00610141, 0.00511049, 0.00426384", \ + "0.0286883, 0.0219382, 0.019361, 0.0166354, 0.0137014, 0.0109989, 0.00953375" \ ); } } @@ -2324,65 +2324,65 @@ library (sg13g2_stdcell_fast_1p32V_m40C) { pin (A1) { direction : "input"; max_transition : 2.5074; - capacitance : 0.00323069; - rise_capacitance : 0.00314872; - rise_capacitance_range (0.00314872, 0.00314872); - fall_capacitance : 0.00331266; - fall_capacitance_range (0.00331266, 0.00331266); + capacitance : 0.00323075; + rise_capacitance : 0.00314871; + rise_capacitance_range (0.00291325, 0.00343577); + fall_capacitance : 0.00331279; + fall_capacitance_range (0.00280195, 0.00376577); } pin (A2) { direction : "input"; max_transition : 2.5074; capacitance : 0.00330195; rise_capacitance : 0.00333727; - rise_capacitance_range (0.00333727, 0.00333727); + rise_capacitance_range (0.00286928, 0.00366758); fall_capacitance : 0.00326663; - fall_capacitance_range (0.00326663, 0.00326663); + fall_capacitance_range (0.00285116, 0.00360375); } pin (B1) { direction : "input"; max_transition : 2.5074; capacitance : 0.00306113; rise_capacitance : 0.00314353; - rise_capacitance_range (0.00314353, 0.00314353); + rise_capacitance_range (0.00262058, 0.00380347); fall_capacitance : 0.00297874; - fall_capacitance_range (0.00297874, 0.00297874); + fall_capacitance_range (0.00273018, 0.0034309); } } cell (sg13g2_a21oi_2) { area : 14.5152; cell_footprint : "a21oi"; - cell_leakage_power : 583.54; + cell_leakage_power : 583.538; leakage_power () { - value : 441.915; + value : 441.914; when : "!A1&!A2&!B1&Y"; } leakage_power () { - value : 586.832; + value : 586.831; when : "!A1&!A2&B1&!Y"; } leakage_power () { - value : 560.506; + value : 560.505; when : "!A1&A2&!B1&Y"; } leakage_power () { - value : 695.621; + value : 695.619; when : "!A1&A2&B1&!Y"; } leakage_power () { - value : 317.745; + value : 317.744; when : "A1&!A2&!B1&Y"; } leakage_power () { - value : 695.62; + value : 695.619; when : "A1&!A2&B1&!Y"; } leakage_power () { - value : 605.194; + value : 605.192; when : "A1&A2&!B1&!Y"; } leakage_power () { - value : 764.885; + value : 764.883; when : "A1&A2&B1&!Y"; } pin (Y) { @@ -2398,52 +2398,52 @@ library (sg13g2_stdcell_fast_1p32V_m40C) { index_1 ("0.0186, 0.0966, 0.174, 0.3294, 0.6408, 1.263, 2.5074"); index_2 ("0.001, 0.0468, 0.078, 0.1296, 0.216, 0.36, 0.6"); values ( \ - "0.0295458, 0.11589, 0.173157, 0.267584, 0.425697, 0.688397, 1.12744", \ - "0.0443468, 0.142613, 0.200577, 0.295258, 0.453439, 0.717415, 1.1554", \ - "0.0508618, 0.163565, 0.224613, 0.320782, 0.479193, 0.742664, 1.18195", \ - "0.0564533, 0.196636, 0.265446, 0.368486, 0.531112, 0.795542, 1.23439", \ - "0.0623551, 0.243968, 0.326167, 0.44487, 0.622322, 0.896677, 1.33906", \ - "0.0694549, 0.308095, 0.413853, 0.560761, 0.767914, 1.07327, 1.53986", \ - "0.0694559, 0.3863, 0.527358, 0.717387, 0.979614, 1.34365, 1.87313" \ + "0.029545, 0.115865, 0.173161, 0.267498, 0.425416, 0.688507, 1.12742", \ + "0.0443483, 0.142581, 0.200575, 0.295253, 0.453597, 0.717391, 1.15535", \ + "0.0508607, 0.163558, 0.224609, 0.320776, 0.479155, 0.742956, 1.18192", \ + "0.0565162, 0.196675, 0.265441, 0.368478, 0.531101, 0.795504, 1.23453", \ + "0.0623537, 0.243963, 0.326166, 0.444863, 0.622297, 0.896831, 1.33909", \ + "0.0694528, 0.308096, 0.413848, 0.559792, 0.767904, 1.07326, 1.53988", \ + "0.0694538, 0.386293, 0.527349, 0.717376, 0.978761, 1.34347, 1.8731" \ ); } rise_transition (TIMING_DELAY_7x7ds1) { index_1 ("0.0186, 0.0966, 0.174, 0.3294, 0.6408, 1.263, 2.5074"); index_2 ("0.001, 0.0468, 0.078, 0.1296, 0.216, 0.36, 0.6"); values ( \ - "0.0152167, 0.133748, 0.214789, 0.348709, 0.572864, 0.94676, 1.56946", \ - "0.0251381, 0.137652, 0.216364, 0.350124, 0.573062, 0.946864, 1.56947", \ - "0.0343057, 0.148109, 0.223976, 0.352792, 0.57403, 0.946865, 1.56948", \ - "0.0523225, 0.172418, 0.247047, 0.371169, 0.584572, 0.950054, 1.57637", \ - "0.0822066, 0.218775, 0.295076, 0.417797, 0.624331, 0.976072, 1.58073", \ - "0.127369, 0.298412, 0.382786, 0.513154, 0.720937, 1.06379, 1.64304", \ - "0.200882, 0.427287, 0.533145, 0.680453, 0.90402, 1.25544, 1.82819" \ + "0.0152162, 0.133709, 0.214788, 0.348568, 0.572762, 0.946446, 1.56942", \ + "0.0251395, 0.137662, 0.216347, 0.350476, 0.572876, 0.946839, 1.56943", \ + "0.0343056, 0.148097, 0.223965, 0.352783, 0.573717, 0.947759, 1.56944", \ + "0.052286, 0.172421, 0.247043, 0.371161, 0.584377, 0.950182, 1.57264", \ + "0.0822059, 0.218774, 0.295034, 0.417789, 0.624187, 0.976019, 1.58048", \ + "0.127367, 0.29842, 0.382787, 0.512318, 0.720926, 1.06359, 1.64299", \ + "0.200879, 0.427283, 0.533138, 0.680446, 0.903225, 1.25543, 1.82806" \ ); } cell_fall (TIMING_DELAY_7x7ds1) { index_1 ("0.0186, 0.0966, 0.174, 0.3294, 0.6408, 1.263, 2.5074"); index_2 ("0.001, 0.0468, 0.078, 0.1296, 0.216, 0.36, 0.6"); values ( \ - "0.0273323, 0.0947566, 0.138923, 0.211465, 0.332769, 0.535001, 0.871793", \ - "0.047871, 0.132562, 0.178172, 0.251059, 0.372346, 0.574269, 0.910974", \ - "0.0610482, 0.162856, 0.213785, 0.290549, 0.413286, 0.615206, 0.951784", \ - "0.0783652, 0.207091, 0.269061, 0.357389, 0.489447, 0.695587, 1.03247", \ - "0.103118, 0.268602, 0.347065, 0.456678, 0.612564, 0.841158, 1.18895", \ - "0.138663, 0.352615, 0.455665, 0.597648, 0.793952, 1.07001, 1.46826", \ - "0.190634, 0.472309, 0.603048, 0.789245, 1.04747, 1.39951, 1.89165" \ + "0.0273331, 0.0947666, 0.138828, 0.211462, 0.332758, 0.534991, 0.87179", \ + "0.0478709, 0.132554, 0.178171, 0.251066, 0.372331, 0.57435, 0.910956", \ + "0.0610481, 0.162855, 0.213775, 0.290549, 0.413241, 0.615202, 0.951832", \ + "0.0783652, 0.207091, 0.26906, 0.357388, 0.489445, 0.695585, 1.03232", \ + "0.103118, 0.268602, 0.347064, 0.456677, 0.612562, 0.84127, 1.18883", \ + "0.138663, 0.352615, 0.455665, 0.597647, 0.793951, 1.07, 1.46826", \ + "0.190635, 0.472309, 0.603048, 0.789244, 1.04747, 1.3995, 1.89164" \ ); } fall_transition (TIMING_DELAY_7x7ds1) { index_1 ("0.0186, 0.0966, 0.174, 0.3294, 0.6408, 1.263, 2.5074"); index_2 ("0.001, 0.0468, 0.078, 0.1296, 0.216, 0.36, 0.6"); values ( \ - "0.0184295, 0.105653, 0.165641, 0.264351, 0.430013, 0.706004, 1.16591", \ - "0.0320707, 0.115478, 0.171098, 0.266238, 0.430511, 0.706005, 1.16592", \ - "0.0426228, 0.132787, 0.186851, 0.277494, 0.435646, 0.709826, 1.16593", \ - "0.0597441, 0.166832, 0.22257, 0.311806, 0.461388, 0.721053, 1.16936", \ - "0.0875388, 0.221022, 0.286685, 0.381734, 0.53294, 0.779319, 1.20421", \ - "0.132521, 0.307457, 0.388199, 0.502762, 0.667372, 0.924035, 1.33363", \ - "0.208669, 0.441202, 0.545778, 0.691648, 0.894332, 1.18659, 1.61867" \ + "0.0184289, 0.105672, 0.165371, 0.264347, 0.430011, 0.706001, 1.1659", \ + "0.0320707, 0.115478, 0.171097, 0.266471, 0.430611, 0.706002, 1.16591", \ + "0.0426228, 0.132786, 0.186839, 0.277494, 0.435599, 0.709521, 1.16592", \ + "0.0597439, 0.166831, 0.22257, 0.311805, 0.461678, 0.721049, 1.16939", \ + "0.0875385, 0.221021, 0.286685, 0.381733, 0.532939, 0.779771, 1.20405", \ + "0.13252, 0.307457, 0.388199, 0.502761, 0.667366, 0.924033, 1.33362", \ + "0.208668, 0.4412, 0.545778, 0.691651, 0.894346, 1.18659, 1.61867" \ ); } } @@ -2455,52 +2455,52 @@ library (sg13g2_stdcell_fast_1p32V_m40C) { index_1 ("0.0186, 0.0966, 0.174, 0.3294, 0.6408, 1.263, 2.5074"); index_2 ("0.001, 0.0468, 0.078, 0.1296, 0.216, 0.36, 0.6"); values ( \ - "0.0352047, 0.120344, 0.177277, 0.27129, 0.42871, 0.690525, 1.12712", \ - "0.0532492, 0.147948, 0.205378, 0.299468, 0.456954, 0.719429, 1.1556", \ - "0.0622324, 0.169879, 0.230065, 0.325492, 0.482962, 0.745298, 1.18206", \ - "0.0723182, 0.20424, 0.271753, 0.373796, 0.535253, 0.798202, 1.235", \ - "0.0850071, 0.254213, 0.334558, 0.451741, 0.627708, 0.90036, 1.34023", \ - "0.103277, 0.323317, 0.426158, 0.569172, 0.774678, 1.07816, 1.54238", \ - "0.123333, 0.412431, 0.547904, 0.733388, 0.989571, 1.35189, 1.8782" \ + "0.0352077, 0.120326, 0.17738, 0.271178, 0.42842, 0.690289, 1.12709", \ + "0.0532487, 0.147975, 0.205383, 0.299459, 0.456942, 0.719395, 1.15555", \ + "0.0622381, 0.169876, 0.230094, 0.32547, 0.482943, 0.74526, 1.18208", \ + "0.0723169, 0.204236, 0.271748, 0.373845, 0.535242, 0.798209, 1.23496", \ + "0.0850056, 0.254209, 0.334553, 0.451734, 0.627698, 0.900344, 1.34011", \ + "0.103275, 0.323313, 0.426152, 0.569163, 0.774666, 1.07814, 1.54239", \ + "0.123329, 0.412423, 0.547895, 0.733376, 0.98942, 1.35187, 1.87825" \ ); } rise_transition (TIMING_DELAY_7x7ds1) { index_1 ("0.0186, 0.0966, 0.174, 0.3294, 0.6408, 1.263, 2.5074"); index_2 ("0.001, 0.0468, 0.078, 0.1296, 0.216, 0.36, 0.6"); values ( \ - "0.020632, 0.139159, 0.21988, 0.353295, 0.576426, 0.948298, 1.56805", \ - "0.0299299, 0.142903, 0.221451, 0.355392, 0.576531, 0.948638, 1.56806", \ - "0.0391376, 0.152974, 0.228898, 0.357439, 0.577566, 0.949613, 1.56813", \ - "0.0566038, 0.177416, 0.251584, 0.375487, 0.588079, 0.952115, 1.57198", \ - "0.0852631, 0.22315, 0.299747, 0.421993, 0.627808, 0.977802, 1.57951", \ - "0.127627, 0.302199, 0.38756, 0.516452, 0.723321, 1.06523, 1.64239", \ - "0.194914, 0.426537, 0.532918, 0.681791, 0.905094, 1.25729, 1.82678" \ + "0.0206634, 0.139128, 0.219908, 0.353112, 0.576305, 0.948623, 1.56801", \ + "0.0299291, 0.142915, 0.221452, 0.354221, 0.576516, 0.948624, 1.56802", \ + "0.039129, 0.152971, 0.228892, 0.357357, 0.577335, 0.949563, 1.56815", \ + "0.056603, 0.177413, 0.251578, 0.375427, 0.588063, 0.952022, 1.57194", \ + "0.0852623, 0.223145, 0.299742, 0.421984, 0.627797, 0.977783, 1.57949", \ + "0.127626, 0.302195, 0.387552, 0.516443, 0.723307, 1.06521, 1.64246", \ + "0.194913, 0.42635, 0.532912, 0.681781, 0.90476, 1.25727, 1.8268" \ ); } cell_fall (TIMING_DELAY_7x7ds1) { index_1 ("0.0186, 0.0966, 0.174, 0.3294, 0.6408, 1.263, 2.5074"); index_2 ("0.001, 0.0468, 0.078, 0.1296, 0.216, 0.36, 0.6"); values ( \ - "0.030216, 0.0972259, 0.141306, 0.213859, 0.33528, 0.537245, 0.873966", \ - "0.0496176, 0.128024, 0.173344, 0.246325, 0.367747, 0.569888, 0.906595", \ - "0.0618987, 0.153463, 0.202183, 0.277833, 0.400452, 0.602735, 0.939554", \ - "0.0770867, 0.192111, 0.248502, 0.332075, 0.46115, 0.66658, 1.00395", \ - "0.0985929, 0.247704, 0.317935, 0.416783, 0.5624, 0.783549, 1.12859", \ - "0.130069, 0.324831, 0.416673, 0.543647, 0.720556, 0.974817, 1.35338", \ - "0.173549, 0.435451, 0.553606, 0.719603, 0.950148, 1.26621, 1.71131" \ + "0.0302136, 0.097225, 0.141305, 0.213935, 0.335277, 0.537253, 0.873973", \ + "0.0496185, 0.128026, 0.173336, 0.246296, 0.367745, 0.569892, 0.906583", \ + "0.0618985, 0.153462, 0.202213, 0.277839, 0.400451, 0.602746, 0.939568", \ + "0.0770866, 0.192111, 0.248501, 0.332074, 0.461149, 0.666572, 1.00395", \ + "0.0985929, 0.247703, 0.317935, 0.416782, 0.562399, 0.783557, 1.12858", \ + "0.130069, 0.324831, 0.416673, 0.543646, 0.720555, 0.974815, 1.35338", \ + "0.173551, 0.435452, 0.553606, 0.719602, 0.950147, 1.26621, 1.71131" \ ); } fall_transition (TIMING_DELAY_7x7ds1) { index_1 ("0.0186, 0.0966, 0.174, 0.3294, 0.6408, 1.263, 2.5074"); index_2 ("0.001, 0.0468, 0.078, 0.1296, 0.216, 0.36, 0.6"); values ( \ - "0.0178316, 0.105597, 0.16539, 0.264357, 0.430005, 0.706174, 1.16606", \ - "0.0270798, 0.111603, 0.168804, 0.265848, 0.430482, 0.706175, 1.16607", \ - "0.0364775, 0.123095, 0.178862, 0.272607, 0.43332, 0.706809, 1.16608", \ - "0.0538252, 0.147944, 0.20375, 0.295135, 0.450029, 0.715735, 1.16783", \ - "0.0823762, 0.192444, 0.251921, 0.34505, 0.497711, 0.753644, 1.19042", \ - "0.12588, 0.266715, 0.337454, 0.44002, 0.598834, 0.851993, 1.27679", \ - "0.19719, 0.386081, 0.474777, 0.598642, 0.781395, 1.05174, 1.47697" \ + "0.0178312, 0.105607, 0.16539, 0.264364, 0.430004, 0.705992, 1.16605", \ + "0.0271151, 0.111609, 0.168807, 0.265626, 0.430476, 0.705993, 1.16606", \ + "0.0364774, 0.123069, 0.178849, 0.272515, 0.43332, 0.708407, 1.16607", \ + "0.0538251, 0.147944, 0.203747, 0.295135, 0.450028, 0.715426, 1.16783", \ + "0.0823759, 0.192444, 0.251922, 0.34505, 0.497712, 0.753724, 1.19043", \ + "0.125879, 0.266718, 0.337453, 0.440019, 0.598832, 0.851991, 1.27678", \ + "0.19719, 0.38608, 0.474776, 0.59864, 0.781393, 1.05174, 1.47696" \ ); } } @@ -2514,52 +2514,52 @@ library (sg13g2_stdcell_fast_1p32V_m40C) { index_1 ("0.0186, 0.0966, 0.174, 0.3294, 0.6408, 1.263, 2.5074"); index_2 ("0.001, 0.0468, 0.078, 0.1296, 0.216, 0.36, 0.6"); values ( \ - "0.0283247, 0.114854, 0.172139, 0.266069, 0.42368, 0.685467, 1.12211", \ - "0.0471336, 0.148576, 0.206241, 0.300454, 0.457953, 0.720513, 1.15645", \ - "0.0577013, 0.177157, 0.239035, 0.334819, 0.4921, 0.754208, 1.19176", \ - "0.0720437, 0.221036, 0.293494, 0.399226, 0.562075, 0.824588, 1.26062", \ - "0.0916192, 0.282367, 0.372515, 0.499685, 0.683904, 0.960504, 1.40009", \ - "0.119085, 0.366412, 0.482725, 0.64303, 0.870909, 1.19355, 1.66889", \ - "0.156684, 0.478498, 0.63094, 0.840734, 1.12996, 1.53569, 2.104" \ + "0.0283276, 0.11486, 0.172131, 0.266062, 0.42368, 0.685462, 1.12208", \ + "0.0471331, 0.148574, 0.206257, 0.300392, 0.457957, 0.720484, 1.15643", \ + "0.057701, 0.177155, 0.239029, 0.334796, 0.4921, 0.754243, 1.19057", \ + "0.0720426, 0.221033, 0.29349, 0.39922, 0.562071, 0.824562, 1.26077", \ + "0.0916172, 0.282363, 0.372507, 0.499682, 0.684193, 0.960487, 1.40008", \ + "0.119082, 0.366407, 0.483233, 0.643023, 0.870898, 1.19354, 1.66886", \ + "0.156676, 0.478489, 0.63093, 0.840723, 1.12995, 1.53567, 2.10383" \ ); } rise_transition (TIMING_DELAY_7x7ds1) { index_1 ("0.0186, 0.0966, 0.174, 0.3294, 0.6408, 1.263, 2.5074"); index_2 ("0.001, 0.0468, 0.078, 0.1296, 0.216, 0.36, 0.6"); values ( \ - "0.0211663, 0.139252, 0.220146, 0.353347, 0.576404, 0.948349, 1.56813", \ - "0.0349401, 0.145913, 0.222586, 0.355811, 0.576405, 0.948667, 1.56866", \ - "0.0448022, 0.162041, 0.234904, 0.360112, 0.578092, 0.948668, 1.56982", \ - "0.0604606, 0.196414, 0.269379, 0.38892, 0.595616, 0.954337, 1.57081", \ - "0.0863182, 0.253376, 0.334153, 0.456894, 0.656775, 0.995784, 1.58659", \ - "0.129963, 0.343358, 0.440732, 0.582229, 0.792915, 1.1276, 1.68488", \ - "0.203477, 0.484284, 0.610126, 0.779425, 1.02891, 1.39353, 1.95923" \ + "0.0211583, 0.139246, 0.220085, 0.353338, 0.57639, 0.948325, 1.56809", \ + "0.0349398, 0.14591, 0.222595, 0.355685, 0.576391, 0.948643, 1.56862", \ + "0.0448014, 0.162038, 0.234853, 0.36017, 0.578083, 0.948644, 1.56863", \ + "0.0604602, 0.196417, 0.269374, 0.388912, 0.595616, 0.95431, 1.57107", \ + "0.0863178, 0.253373, 0.334149, 0.456988, 0.657271, 0.995767, 1.58664", \ + "0.129962, 0.343355, 0.440855, 0.582224, 0.792903, 1.12757, 1.6847", \ + "0.203476, 0.484281, 0.610123, 0.779419, 1.02889, 1.39333, 1.95938" \ ); } cell_fall (TIMING_DELAY_7x7ds1) { index_1 ("0.0186, 0.0966, 0.174, 0.3294, 0.6408, 1.263, 2.5074"); index_2 ("0.001, 0.0468, 0.078, 0.1296, 0.216, 0.36, 0.6"); values ( \ - "0.0152711, 0.0531297, 0.0763908, 0.114834, 0.179321, 0.286123, 0.464654", \ - "0.0281106, 0.091408, 0.119537, 0.160808, 0.225877, 0.33289, 0.511124", \ - "0.0356153, 0.117905, 0.152481, 0.200353, 0.270974, 0.380457, 0.558835", \ - "0.0438661, 0.155085, 0.200438, 0.26151, 0.345868, 0.467509, 0.652356", \ - "0.0536481, 0.203862, 0.266356, 0.348025, 0.457297, 0.606192, 0.817871", \ - "0.0658291, 0.268019, 0.352991, 0.466684, 0.615877, 0.811904, 1.07655", \ - "0.0799706, 0.350684, 0.465868, 0.618558, 0.826914, 1.09919, 1.45274" \ + "0.0152756, 0.0531407, 0.0764104, 0.114874, 0.179332, 0.286198, 0.464458", \ + "0.0281121, 0.0914146, 0.119536, 0.160815, 0.225892, 0.332908, 0.511111", \ + "0.0356164, 0.11791, 0.152487, 0.200362, 0.270988, 0.380502, 0.558875", \ + "0.0438728, 0.15509, 0.200445, 0.26152, 0.345907, 0.467481, 0.65235", \ + "0.0536507, 0.203868, 0.266366, 0.348035, 0.457314, 0.606218, 0.817892", \ + "0.0658337, 0.268027, 0.353001, 0.466699, 0.615897, 0.811934, 1.07659", \ + "0.0799794, 0.350697, 0.465882, 0.618578, 0.826941, 1.09923, 1.45278" \ ); } fall_transition (TIMING_DELAY_7x7ds1) { index_1 ("0.0186, 0.0966, 0.174, 0.3294, 0.6408, 1.263, 2.5074"); index_2 ("0.001, 0.0468, 0.078, 0.1296, 0.216, 0.36, 0.6"); values ( \ - "0.0110963, 0.0567447, 0.0887999, 0.142017, 0.231604, 0.380221, 0.628643", \ - "0.0293384, 0.0738535, 0.102106, 0.150127, 0.234658, 0.380654, 0.628644", \ - "0.0424135, 0.0929302, 0.121905, 0.168827, 0.248759, 0.388388, 0.630616", \ - "0.0632816, 0.126222, 0.159563, 0.208857, 0.288424, 0.41984, 0.648992", \ - "0.0968336, 0.179827, 0.221003, 0.279748, 0.365437, 0.499995, 0.717322", \ - "0.151794, 0.264566, 0.319897, 0.394869, 0.50001, 0.648239, 0.877777", \ - "0.244801, 0.40288, 0.475645, 0.578423, 0.715978, 0.903482, 1.16668" \ + "0.0110971, 0.0567491, 0.0887044, 0.142027, 0.231592, 0.380359, 0.628657", \ + "0.0293384, 0.0738452, 0.102126, 0.15014, 0.234677, 0.380696, 0.628658", \ + "0.0424145, 0.0929347, 0.121911, 0.168847, 0.248858, 0.388539, 0.630588", \ + "0.0633177, 0.126226, 0.15957, 0.208843, 0.288459, 0.419833, 0.649181", \ + "0.0968347, 0.179833, 0.221011, 0.27976, 0.365455, 0.500003, 0.717406", \ + "0.151795, 0.264571, 0.319906, 0.395275, 0.500027, 0.648268, 0.877428", \ + "0.244737, 0.402886, 0.475481, 0.578438, 0.716003, 0.903514, 1.16632" \ ); } } @@ -2573,52 +2573,52 @@ library (sg13g2_stdcell_fast_1p32V_m40C) { index_1 ("0.0186, 0.0966, 0.174, 0.3294, 0.6408, 1.263, 2.5074"); index_2 ("0.001, 0.0468, 0.078, 0.1296, 0.216, 0.36, 0.6"); values ( \ - "0.0217723, 0.108718, 0.166117, 0.260519, 0.418695, 0.681865, 1.12057", \ - "0.0355873, 0.142255, 0.200333, 0.294828, 0.452969, 0.716903, 1.15477", \ - "0.043559, 0.170082, 0.232796, 0.329218, 0.487215, 0.750617, 1.19024", \ - "0.0539709, 0.212433, 0.286261, 0.393208, 0.55716, 0.82097, 1.25936", \ - "0.0681481, 0.271313, 0.363333, 0.4926, 0.678447, 0.956733, 1.39862", \ - "0.0883152, 0.352062, 0.471259, 0.634567, 0.864346, 1.18927, 1.66716", \ - "0.116709, 0.460247, 0.615337, 0.828849, 1.12148, 1.53016, 2.10233" \ + "0.0217703, 0.108769, 0.166067, 0.260469, 0.418468, 0.681834, 1.12054", \ + "0.0355868, 0.142209, 0.200285, 0.294771, 0.452962, 0.716883, 1.15476", \ + "0.0435767, 0.170085, 0.232756, 0.329209, 0.487177, 0.750676, 1.1902", \ + "0.0539697, 0.21243, 0.286257, 0.393202, 0.557151, 0.820948, 1.2591", \ + "0.0681463, 0.271309, 0.363328, 0.492594, 0.678556, 0.956717, 1.39853", \ + "0.0883118, 0.352057, 0.471253, 0.634558, 0.864334, 1.18925, 1.66713", \ + "0.116702, 0.460239, 0.615328, 0.828849, 1.12147, 1.53016, 2.10226" \ ); } rise_transition (TIMING_DELAY_7x7ds1) { index_1 ("0.0186, 0.0966, 0.174, 0.3294, 0.6408, 1.263, 2.5074"); index_2 ("0.001, 0.0468, 0.078, 0.1296, 0.216, 0.36, 0.6"); values ( \ - "0.0163038, 0.133793, 0.21469, 0.348754, 0.573016, 0.946488, 1.56951", \ - "0.0295296, 0.141108, 0.21776, 0.350183, 0.573022, 0.946845, 1.56984", \ - "0.0386468, 0.157637, 0.230634, 0.356153, 0.5747, 0.946944, 1.57119", \ - "0.0531778, 0.192655, 0.265527, 0.385199, 0.592292, 0.952619, 1.5712", \ - "0.0765517, 0.248257, 0.330406, 0.453528, 0.653986, 0.994434, 1.58802", \ - "0.117924, 0.339095, 0.436103, 0.578869, 0.790819, 1.12687, 1.68635", \ - "0.190862, 0.479136, 0.606245, 0.776137, 1.02663, 1.39283, 1.96114" \ + "0.0163092, 0.133845, 0.214659, 0.348727, 0.572849, 0.946464, 1.56948", \ + "0.0295293, 0.141101, 0.217721, 0.350584, 0.57285, 0.946801, 1.5698", \ + "0.0386599, 0.157706, 0.230476, 0.355873, 0.574196, 0.946818, 1.57117", \ + "0.0531778, 0.192652, 0.265524, 0.38522, 0.592279, 0.952644, 1.57118", \ + "0.0765516, 0.248254, 0.330401, 0.45352, 0.654164, 0.994409, 1.58807", \ + "0.117924, 0.339092, 0.436098, 0.578861, 0.790807, 1.12682, 1.68597", \ + "0.190862, 0.479134, 0.606242, 0.776132, 1.02662, 1.39281, 1.96113" \ ); } cell_fall (TIMING_DELAY_7x7ds1) { index_1 ("0.0186, 0.0966, 0.174, 0.3294, 0.6408, 1.263, 2.5074"); index_2 ("0.001, 0.0468, 0.078, 0.1296, 0.216, 0.36, 0.6"); values ( \ - "0.0149823, 0.0528313, 0.0760317, 0.114308, 0.178604, 0.285204, 0.463408", \ - "0.027298, 0.0909478, 0.119031, 0.160263, 0.225155, 0.331854, 0.509797", \ - "0.034018, 0.117216, 0.151825, 0.199692, 0.270176, 0.379438, 0.557484", \ - "0.0412985, 0.153939, 0.199406, 0.260584, 0.344881, 0.466299, 0.65092", \ - "0.0487259, 0.201768, 0.264544, 0.346397, 0.455751, 0.604699, 0.816693", \ - "0.054522, 0.264204, 0.349587, 0.463662, 0.613339, 0.809579, 1.07437", \ - "0.054523, 0.342577, 0.459802, 0.613428, 0.822559, 1.09616, 1.44993" \ + "0.0149744, 0.0528254, 0.0760298, 0.114328, 0.178616, 0.285229, 0.463204", \ + "0.0272912, 0.0909518, 0.119021, 0.160272, 0.225169, 0.331877, 0.509855", \ + "0.034019, 0.11722, 0.151831, 0.199696, 0.270208, 0.379463, 0.557554", \ + "0.0412882, 0.153964, 0.199412, 0.260592, 0.344907, 0.466323, 0.650933", \ + "0.0487283, 0.201774, 0.264553, 0.346337, 0.455768, 0.604724, 0.816728", \ + "0.054526, 0.264212, 0.349597, 0.463676, 0.613358, 0.809616, 1.07441", \ + "0.054527, 0.342589, 0.459817, 0.613541, 0.822583, 1.0962, 1.44993" \ ); } fall_transition (TIMING_DELAY_7x7ds1) { index_1 ("0.0186, 0.0966, 0.174, 0.3294, 0.6408, 1.263, 2.5074"); index_2 ("0.001, 0.0468, 0.078, 0.1296, 0.216, 0.36, 0.6"); values ( \ - "0.007879, 0.0528696, 0.0848765, 0.138451, 0.227789, 0.376616, 0.625165", \ - "0.0205894, 0.0696627, 0.098286, 0.146303, 0.230912, 0.376972, 0.625166", \ - "0.0302513, 0.0880581, 0.117863, 0.16493, 0.245087, 0.384819, 0.628573", \ - "0.0460679, 0.12005, 0.154558, 0.204704, 0.284325, 0.416159, 0.645425", \ - "0.0716867, 0.172232, 0.214899, 0.274792, 0.360892, 0.496492, 0.713818", \ - "0.115627, 0.252794, 0.311736, 0.389322, 0.494964, 0.644756, 0.874387", \ - "0.193488, 0.387986, 0.462687, 0.569042, 0.711359, 0.898448, 1.16146" \ + "0.00788382, 0.0528436, 0.0848671, 0.138408, 0.2278, 0.376649, 0.624944", \ + "0.0205977, 0.0696689, 0.0983185, 0.146314, 0.230894, 0.377084, 0.624996", \ + "0.0302518, 0.0880837, 0.11787, 0.164956, 0.245171, 0.384851, 0.627052", \ + "0.0460608, 0.120145, 0.154565, 0.204443, 0.284619, 0.41619, 0.645498", \ + "0.0716875, 0.172237, 0.214907, 0.274363, 0.36096, 0.49652, 0.713981", \ + "0.115627, 0.252799, 0.311745, 0.389334, 0.494983, 0.644806, 0.874135", \ + "0.193488, 0.387992, 0.462696, 0.568928, 0.711379, 0.89848, 1.16155" \ ); } } @@ -2632,52 +2632,52 @@ library (sg13g2_stdcell_fast_1p32V_m40C) { index_1 ("0.0186, 0.0966, 0.174, 0.3294, 0.6408, 1.263, 2.5074"); index_2 ("0.001, 0.0468, 0.078, 0.1296, 0.216, 0.36, 0.6"); values ( \ - "0.0185036, 0.083179, 0.125416, 0.195132, 0.311566, 0.505892, 0.829209", \ - "0.031272, 0.118862, 0.163065, 0.233083, 0.349649, 0.544342, 0.867706", \ - "0.0380986, 0.145848, 0.19579, 0.269824, 0.387254, 0.581252, 0.904803", \ - "0.0464974, 0.185061, 0.24675, 0.333136, 0.460536, 0.658209, 0.98183", \ - "0.0569949, 0.238271, 0.317753, 0.426732, 0.578729, 0.797758, 1.13221", \ - "0.0699266, 0.30862, 0.414946, 0.556804, 0.752007, 1.02084, 1.40262", \ - "0.0846662, 0.397826, 0.53885, 0.728982, 0.987462, 1.33525, 1.81674" \ + "0.0185025, 0.0831636, 0.125405, 0.19513, 0.311572, 0.505875, 0.829318", \ + "0.0312675, 0.118841, 0.163065, 0.233068, 0.349608, 0.543874, 0.867681", \ + "0.0380956, 0.145846, 0.195785, 0.269821, 0.387246, 0.58123, 0.904729", \ + "0.0464966, 0.185058, 0.246766, 0.333131, 0.460505, 0.658217, 0.981762", \ + "0.0569929, 0.238268, 0.317748, 0.426725, 0.578827, 0.797742, 1.13206", \ + "0.0699231, 0.308614, 0.414941, 0.556795, 0.752017, 1.02085, 1.40257", \ + "0.084659, 0.397818, 0.538841, 0.72897, 0.987446, 1.33523, 1.81671" \ ); } rise_transition (TIMING_DELAY_7x7ds1) { index_1 ("0.0186, 0.0966, 0.174, 0.3294, 0.6408, 1.263, 2.5074"); index_2 ("0.001, 0.0468, 0.078, 0.1296, 0.216, 0.36, 0.6"); values ( \ - "0.0126883, 0.0992415, 0.159821, 0.259901, 0.427486, 0.706912, 1.17244", \ - "0.0259966, 0.110249, 0.165664, 0.261754, 0.428021, 0.707661, 1.17275", \ - "0.0355365, 0.128628, 0.181891, 0.272702, 0.432097, 0.707662, 1.1729", \ - "0.0498527, 0.163865, 0.219574, 0.308084, 0.458155, 0.720538, 1.17619", \ - "0.0726805, 0.219354, 0.285065, 0.380454, 0.53005, 0.777689, 1.20857", \ - "0.112779, 0.307627, 0.389909, 0.504816, 0.670325, 0.92411, 1.33552", \ - "0.185344, 0.442322, 0.554397, 0.703126, 0.903226, 1.19387, 1.62893" \ + "0.0126981, 0.0992658, 0.159815, 0.259896, 0.427472, 0.706888, 1.1725", \ + "0.0259837, 0.110226, 0.165669, 0.261762, 0.427759, 0.707067, 1.17271", \ + "0.0355392, 0.128625, 0.181886, 0.272703, 0.432085, 0.707116, 1.17286", \ + "0.0498528, 0.163862, 0.219579, 0.308076, 0.45812, 0.720764, 1.17502", \ + "0.0726806, 0.219351, 0.285031, 0.380448, 0.529776, 0.777669, 1.20786", \ + "0.112779, 0.307624, 0.389906, 0.50481, 0.669865, 0.924133, 1.33546", \ + "0.185344, 0.44232, 0.554392, 0.70312, 0.903214, 1.19386, 1.62883" \ ); } cell_fall (TIMING_DELAY_7x7ds1) { index_1 ("0.0186, 0.0966, 0.174, 0.3294, 0.6408, 1.263, 2.5074"); index_2 ("0.001, 0.0468, 0.078, 0.1296, 0.216, 0.36, 0.6"); values ( \ - "0.0147438, 0.0526503, 0.0758511, 0.114155, 0.178441, 0.285072, 0.463276", \ - "0.0271401, 0.090683, 0.118774, 0.160083, 0.224956, 0.33172, 0.509593", \ - "0.0342726, 0.116997, 0.151553, 0.199441, 0.26999, 0.379254, 0.557515", \ - "0.0425739, 0.153831, 0.199286, 0.2604, 0.344648, 0.466157, 0.650728", \ - "0.0524134, 0.202428, 0.264951, 0.346277, 0.455677, 0.604191, 0.816596", \ - "0.0632387, 0.267347, 0.351736, 0.465126, 0.613916, 0.809765, 1.07454", \ - "0.07334, 0.352988, 0.467142, 0.618749, 0.826095, 1.09818, 1.4511" \ + "0.0147442, 0.0526551, 0.0758611, 0.114172, 0.178455, 0.285094, 0.463333", \ + "0.0271412, 0.0907055, 0.118797, 0.16007, 0.224984, 0.331731, 0.509733", \ + "0.0342736, 0.117001, 0.151559, 0.199458, 0.270004, 0.379302, 0.557477", \ + "0.0425754, 0.153837, 0.199293, 0.260411, 0.344667, 0.466131, 0.650767", \ + "0.0524159, 0.202434, 0.26496, 0.346289, 0.455694, 0.604206, 0.816632", \ + "0.0632432, 0.267355, 0.351746, 0.465141, 0.613934, 0.809795, 1.07458", \ + "0.07335, 0.353, 0.467156, 0.618768, 0.826122, 1.09822, 1.45113" \ ); } fall_transition (TIMING_DELAY_7x7ds1) { index_1 ("0.0186, 0.0966, 0.174, 0.3294, 0.6408, 1.263, 2.5074"); index_2 ("0.001, 0.0468, 0.078, 0.1296, 0.216, 0.36, 0.6"); values ( \ - "0.0080027, 0.0528616, 0.0849066, 0.138474, 0.227883, 0.37658, 0.625212", \ - "0.0207529, 0.0697647, 0.0984176, 0.146404, 0.23092, 0.377093, 0.626052", \ - "0.0302648, 0.0883105, 0.118051, 0.165174, 0.245143, 0.384752, 0.627105", \ - "0.0456146, 0.120157, 0.154805, 0.20481, 0.28469, 0.416242, 0.645561", \ - "0.0706571, 0.171617, 0.2147, 0.274491, 0.361176, 0.49663, 0.713878", \ - "0.113649, 0.250387, 0.309717, 0.388362, 0.493325, 0.644674, 0.874294", \ - "0.190844, 0.380084, 0.458117, 0.564347, 0.708487, 0.895543, 1.16027" \ + "0.00800319, 0.0528649, 0.0848877, 0.138487, 0.227904, 0.376612, 0.625267", \ + "0.0207531, 0.069792, 0.0983869, 0.146434, 0.230856, 0.377197, 0.625268", \ + "0.0302654, 0.0883147, 0.118058, 0.165074, 0.245267, 0.384799, 0.627173", \ + "0.045615, 0.120132, 0.154812, 0.204821, 0.284745, 0.416298, 0.645614", \ + "0.0706576, 0.171622, 0.214708, 0.274587, 0.360999, 0.496721, 0.713935", \ + "0.113649, 0.250393, 0.309725, 0.388375, 0.493678, 0.644707, 0.874343", \ + "0.190834, 0.380089, 0.458127, 0.56436, 0.708508, 0.895575, 1.16032" \ ); } } @@ -2689,52 +2689,52 @@ library (sg13g2_stdcell_fast_1p32V_m40C) { index_1 ("0.0186, 0.0966, 0.174, 0.3294, 0.6408, 1.263, 2.5074"); index_2 ("0.001, 0.0468, 0.078, 0.1296, 0.216, 0.36, 0.6"); values ( \ - "0.0283247, 0.114854, 0.172139, 0.266069, 0.42368, 0.685467, 1.12211", \ - "0.0471336, 0.148576, 0.206241, 0.300454, 0.457953, 0.720513, 1.15645", \ - "0.0577013, 0.177157, 0.239035, 0.334819, 0.4921, 0.754208, 1.19176", \ - "0.0720437, 0.221036, 0.293494, 0.399226, 0.562075, 0.824588, 1.26062", \ - "0.0916192, 0.282367, 0.372515, 0.499685, 0.683904, 0.960504, 1.40009", \ - "0.119085, 0.366412, 0.482725, 0.64303, 0.870909, 1.19355, 1.66889", \ - "0.156684, 0.478498, 0.63094, 0.840734, 1.12996, 1.53569, 2.104" \ + "0.0283276, 0.11486, 0.172131, 0.266062, 0.42368, 0.685462, 1.12208", \ + "0.0471331, 0.148574, 0.206257, 0.300392, 0.457957, 0.720484, 1.15643", \ + "0.057701, 0.177155, 0.239029, 0.334796, 0.4921, 0.754243, 1.19057", \ + "0.0720426, 0.221033, 0.29349, 0.39922, 0.562071, 0.824562, 1.26077", \ + "0.0916172, 0.282363, 0.372507, 0.499682, 0.684193, 0.960487, 1.40008", \ + "0.119082, 0.366407, 0.483233, 0.643023, 0.870898, 1.19354, 1.66886", \ + "0.156676, 0.478489, 0.63093, 0.840723, 1.12995, 1.53567, 2.10383" \ ); } rise_transition (TIMING_DELAY_7x7ds1) { index_1 ("0.0186, 0.0966, 0.174, 0.3294, 0.6408, 1.263, 2.5074"); index_2 ("0.001, 0.0468, 0.078, 0.1296, 0.216, 0.36, 0.6"); values ( \ - "0.0211663, 0.139252, 0.220146, 0.353347, 0.576404, 0.948349, 1.56813", \ - "0.0349401, 0.145913, 0.222586, 0.355811, 0.576405, 0.948667, 1.56866", \ - "0.0448022, 0.162041, 0.234904, 0.360112, 0.578092, 0.948668, 1.56982", \ - "0.0604606, 0.196414, 0.269379, 0.38892, 0.595616, 0.954337, 1.57081", \ - "0.0863182, 0.253376, 0.334153, 0.456894, 0.656775, 0.995784, 1.58659", \ - "0.129963, 0.343358, 0.440732, 0.582229, 0.792915, 1.1276, 1.68488", \ - "0.203477, 0.484284, 0.610126, 0.779425, 1.02891, 1.39353, 1.95923" \ + "0.0211583, 0.139246, 0.220085, 0.353338, 0.57639, 0.948325, 1.56809", \ + "0.0349398, 0.14591, 0.222595, 0.355685, 0.576391, 0.948643, 1.56862", \ + "0.0448014, 0.162038, 0.234853, 0.36017, 0.578083, 0.948644, 1.56863", \ + "0.0604602, 0.196417, 0.269374, 0.388912, 0.595616, 0.95431, 1.57107", \ + "0.0863178, 0.253373, 0.334149, 0.456988, 0.657271, 0.995767, 1.58664", \ + "0.129962, 0.343355, 0.440855, 0.582224, 0.792903, 1.12757, 1.6847", \ + "0.203476, 0.484281, 0.610123, 0.779419, 1.02889, 1.39333, 1.95938" \ ); } cell_fall (TIMING_DELAY_7x7ds1) { index_1 ("0.0186, 0.0966, 0.174, 0.3294, 0.6408, 1.263, 2.5074"); index_2 ("0.001, 0.0468, 0.078, 0.1296, 0.216, 0.36, 0.6"); values ( \ - "0.0152711, 0.0531297, 0.0763908, 0.114834, 0.179321, 0.286123, 0.464654", \ - "0.0281106, 0.091408, 0.119537, 0.160808, 0.225877, 0.33289, 0.511124", \ - "0.0356153, 0.117905, 0.152481, 0.200353, 0.270974, 0.380457, 0.558835", \ - "0.0438661, 0.155085, 0.200438, 0.26151, 0.345868, 0.467509, 0.652356", \ - "0.0536481, 0.203862, 0.266356, 0.348025, 0.457297, 0.606192, 0.817871", \ - "0.0658291, 0.268019, 0.352991, 0.466684, 0.615877, 0.811904, 1.07655", \ - "0.0799706, 0.350684, 0.465868, 0.618558, 0.826914, 1.09919, 1.45274" \ + "0.0152756, 0.0531407, 0.0764104, 0.114874, 0.179332, 0.286198, 0.464458", \ + "0.0281121, 0.0914146, 0.119536, 0.160815, 0.225892, 0.332908, 0.511111", \ + "0.0356164, 0.11791, 0.152487, 0.200362, 0.270988, 0.380502, 0.558875", \ + "0.0438728, 0.15509, 0.200445, 0.26152, 0.345907, 0.467481, 0.65235", \ + "0.0536507, 0.203868, 0.266366, 0.348035, 0.457314, 0.606218, 0.817892", \ + "0.0658337, 0.268027, 0.353001, 0.466699, 0.615897, 0.811934, 1.07659", \ + "0.0799794, 0.350697, 0.465882, 0.618578, 0.826941, 1.09923, 1.45278" \ ); } fall_transition (TIMING_DELAY_7x7ds1) { index_1 ("0.0186, 0.0966, 0.174, 0.3294, 0.6408, 1.263, 2.5074"); index_2 ("0.001, 0.0468, 0.078, 0.1296, 0.216, 0.36, 0.6"); values ( \ - "0.0110963, 0.0567447, 0.0887999, 0.142017, 0.231604, 0.380221, 0.628643", \ - "0.0293384, 0.0738535, 0.102106, 0.150127, 0.234658, 0.380654, 0.628644", \ - "0.0424135, 0.0929302, 0.121905, 0.168827, 0.248759, 0.388388, 0.630616", \ - "0.0632816, 0.126222, 0.159563, 0.208857, 0.288424, 0.41984, 0.648992", \ - "0.0968336, 0.179827, 0.221003, 0.279748, 0.365437, 0.499995, 0.717322", \ - "0.151794, 0.264566, 0.319897, 0.394869, 0.50001, 0.648239, 0.877777", \ - "0.244801, 0.40288, 0.475645, 0.578423, 0.715978, 0.903482, 1.16668" \ + "0.0110971, 0.0567491, 0.0887044, 0.142027, 0.231592, 0.380359, 0.628657", \ + "0.0293384, 0.0738452, 0.102126, 0.15014, 0.234677, 0.380696, 0.628658", \ + "0.0424145, 0.0929347, 0.121911, 0.168847, 0.248858, 0.388539, 0.630588", \ + "0.0633177, 0.126226, 0.15957, 0.208843, 0.288459, 0.419833, 0.649181", \ + "0.0968347, 0.179833, 0.221011, 0.27976, 0.365455, 0.500003, 0.717406", \ + "0.151795, 0.264571, 0.319906, 0.395275, 0.500027, 0.648268, 0.877428", \ + "0.244737, 0.402886, 0.475481, 0.578438, 0.716003, 0.903514, 1.16632" \ ); } } @@ -2744,26 +2744,26 @@ library (sg13g2_stdcell_fast_1p32V_m40C) { index_1 ("0.0186, 0.0966, 0.174, 0.3294, 0.6408, 1.263, 2.5074"); index_2 ("0.001, 0.0468, 0.078, 0.1296, 0.216, 0.36, 0.6"); values ( \ - "0.0109184, 0.0119413, 0.0119556, 0.0118368, 0.011598, 0.0110928, 0.0102978", \ - "0.0105189, 0.0113733, 0.0114483, 0.0116735, 0.0114036, 0.0109857, 0.0101948", \ - "0.0109481, 0.0111409, 0.0113852, 0.0112953, 0.0112293, 0.0108339, 0.010201", \ - "0.0127076, 0.0116627, 0.0115356, 0.0114904, 0.0116647, 0.0109677, 0.0113546", \ - "0.0177373, 0.0142572, 0.0135481, 0.0129112, 0.0122691, 0.0125331, 0.0106988", \ - "0.0293811, 0.0220903, 0.0201183, 0.0184549, 0.0167696, 0.0144392, 0.0141614", \ - "0.0535562, 0.0421862, 0.037932, 0.0336921, 0.0294244, 0.0254731, 0.0211031" \ + "0.0109218, 0.0119435, 0.0119567, 0.0118319, 0.0115584, 0.0110787, 0.0102968", \ + "0.0105221, 0.0114011, 0.0114593, 0.011721, 0.0113751, 0.0109779, 0.0102801", \ + "0.0109483, 0.0111298, 0.0114352, 0.011316, 0.0111776, 0.0110925, 0.010202", \ + "0.0127138, 0.0116664, 0.011537, 0.0114895, 0.0113531, 0.0109639, 0.0107103", \ + "0.0177357, 0.0142558, 0.0135678, 0.0129072, 0.0122853, 0.0126433, 0.0109299", \ + "0.0293823, 0.022092, 0.0201184, 0.0183063, 0.0167733, 0.0144193, 0.0142962", \ + "0.0535543, 0.0421854, 0.0379319, 0.0336908, 0.0293497, 0.0253808, 0.0211796" \ ); } fall_power (POWER_7x7ds1) { index_1 ("0.0186, 0.0966, 0.174, 0.3294, 0.6408, 1.263, 2.5074"); index_2 ("0.001, 0.0468, 0.078, 0.1296, 0.216, 0.36, 0.6"); values ( \ - "0.00638363, 0.00673752, 0.00672204, 0.00653081, 0.00627064, 0.00579447, 0.00502685", \ - "0.00622409, 0.00638555, 0.00663101, 0.00635651, 0.00615518, 0.00566185, 0.004843", \ - "0.00708364, 0.00661165, 0.0064772, 0.00650399, 0.00611494, 0.00621487, 0.00483877", \ - "0.00947403, 0.00761739, 0.00731737, 0.00686761, 0.00666845, 0.00609362, 0.00486103", \ - "0.0148879, 0.0109446, 0.00997519, 0.00911994, 0.00808177, 0.00717915, 0.00619905", \ - "0.026558, 0.0195784, 0.0173365, 0.0149958, 0.0128113, 0.0109693, 0.00809631", \ - "0.0507387, 0.0403936, 0.0362698, 0.0313157, 0.0261378, 0.0217667, 0.0173988" \ + "0.00637924, 0.00673977, 0.00666877, 0.00652846, 0.00627024, 0.00579255, 0.00502595", \ + "0.00622382, 0.00638033, 0.00663266, 0.0063115, 0.00620615, 0.00573408, 0.00483895", \ + "0.00708208, 0.00661199, 0.00647672, 0.00659106, 0.00610709, 0.00617489, 0.00488459", \ + "0.0094744, 0.00762059, 0.00731137, 0.00683729, 0.00673335, 0.00609365, 0.00483376", \ + "0.0148876, 0.0109455, 0.0099757, 0.0091198, 0.00808427, 0.00719056, 0.00600691", \ + "0.0265572, 0.0195787, 0.0173369, 0.0149959, 0.0128217, 0.010959, 0.00809671", \ + "0.0507403, 0.0403931, 0.0362701, 0.0313159, 0.0260993, 0.0217315, 0.0173081" \ ); } } @@ -2773,26 +2773,26 @@ library (sg13g2_stdcell_fast_1p32V_m40C) { index_1 ("0.0186, 0.0966, 0.174, 0.3294, 0.6408, 1.263, 2.5074"); index_2 ("0.001, 0.0468, 0.078, 0.1296, 0.216, 0.36, 0.6"); values ( \ - "0.0116005, 0.011787, 0.0117219, 0.0116179, 0.0113089, 0.0107671, 0.00997258", \ - "0.01123, 0.0116635, 0.0115244, 0.0116823, 0.0111673, 0.010775, 0.00997242", \ - "0.0115236, 0.011474, 0.0116309, 0.0113774, 0.0111427, 0.0109747, 0.0100052", \ - "0.0130445, 0.0121519, 0.0118307, 0.0117401, 0.0115382, 0.0109086, 0.0106595", \ - "0.0177099, 0.0147703, 0.0140932, 0.0133134, 0.012596, 0.0127566, 0.0109909", \ - "0.0288279, 0.0228523, 0.0209685, 0.0189765, 0.0171886, 0.0146959, 0.0144069", \ - "0.0520882, 0.0429888, 0.039162, 0.0349357, 0.0303485, 0.0262839, 0.0218085" \ + "0.0116048, 0.0117875, 0.0117244, 0.0115633, 0.0113186, 0.0108433, 0.00997668", \ + "0.0112296, 0.0115988, 0.0115252, 0.0115146, 0.0111671, 0.0107835, 0.00996685", \ + "0.0115303, 0.011497, 0.0116635, 0.0114467, 0.0111132, 0.0109722, 0.00996538", \ + "0.013044, 0.0121435, 0.0118664, 0.0117387, 0.0114539, 0.0109292, 0.0106572", \ + "0.0177107, 0.0147703, 0.0140912, 0.0133434, 0.0125854, 0.012694, 0.010672", \ + "0.0288267, 0.0228524, 0.0209679, 0.0189648, 0.0171813, 0.0146902, 0.0143366", \ + "0.0520867, 0.0429843, 0.0391622, 0.0349336, 0.0303768, 0.0262431, 0.0215789" \ ); } fall_power (POWER_7x7ds1) { index_1 ("0.0186, 0.0966, 0.174, 0.3294, 0.6408, 1.263, 2.5074"); index_2 ("0.001, 0.0468, 0.078, 0.1296, 0.216, 0.36, 0.6"); values ( \ - "0.0108392, 0.01101, 0.0109137, 0.0107408, 0.0104985, 0.0100681, 0.00927105", \ - "0.0103183, 0.0106477, 0.0108087, 0.0105795, 0.0103918, 0.00985901, 0.0090696", \ - "0.0106344, 0.0107284, 0.0106135, 0.0108459, 0.0102955, 0.00987708, 0.00902739", \ - "0.0122913, 0.0113363, 0.0111746, 0.0109311, 0.0107878, 0.0101434, 0.00905033", \ - "0.017085, 0.013926, 0.0131277, 0.0126366, 0.0118503, 0.0109648, 0.0100901", \ - "0.0282191, 0.0217471, 0.0197427, 0.0176895, 0.0162873, 0.0142157, 0.0118645", \ - "0.051432, 0.0413118, 0.0374424, 0.0328384, 0.0285685, 0.0243492, 0.0205427" \ + "0.0108509, 0.0110026, 0.0109145, 0.0107733, 0.0104973, 0.0100169, 0.00927404", \ + "0.0103203, 0.0106487, 0.0108052, 0.0105638, 0.0103887, 0.00985517, 0.00900196", \ + "0.0106362, 0.0106882, 0.0106082, 0.0108428, 0.010301, 0.0102522, 0.00903887", \ + "0.0122926, 0.0113335, 0.0111978, 0.0109313, 0.0107885, 0.0101414, 0.00904595", \ + "0.0170904, 0.0139129, 0.013141, 0.0126341, 0.0116991, 0.0110034, 0.0107786", \ + "0.0282197, 0.0217405, 0.0197431, 0.0176905, 0.0162897, 0.0143924, 0.011868", \ + "0.0514335, 0.0413121, 0.0374432, 0.0328382, 0.0285504, 0.0243496, 0.0205323" \ ); } } @@ -2803,26 +2803,26 @@ library (sg13g2_stdcell_fast_1p32V_m40C) { index_1 ("0.0186, 0.0966, 0.174, 0.3294, 0.6408, 1.263, 2.5074"); index_2 ("0.001, 0.0468, 0.078, 0.1296, 0.216, 0.36, 0.6"); values ( \ - "0.00602425, 0.00691993, 0.00697402, 0.00683795, 0.00666931, 0.00613977, 0.00530091", \ - "0.00645209, 0.00658143, 0.00651563, 0.00679049, 0.00636285, 0.00607855, 0.00529677", \ - "0.00759526, 0.00669443, 0.00677963, 0.00659645, 0.006317, 0.00598067, 0.00557497", \ - "0.0104524, 0.00829811, 0.00769067, 0.00728779, 0.00689949, 0.00644414, 0.00572835", \ - "0.0162866, 0.012142, 0.0110017, 0.00975471, 0.00857152, 0.00746951, 0.00583293", \ - "0.0289377, 0.0216695, 0.0193429, 0.0171004, 0.0145688, 0.0114204, 0.0106997", \ - "0.0553596, 0.0437736, 0.0396216, 0.0351753, 0.0303984, 0.0253365, 0.0198437" \ + "0.00603004, 0.00692394, 0.00697303, 0.00683653, 0.00667044, 0.00614219, 0.00528965", \ + "0.00644713, 0.00658726, 0.00651729, 0.00678256, 0.0063723, 0.0060761, 0.00529939", \ + "0.0075929, 0.00670586, 0.00678715, 0.00649858, 0.00631716, 0.00601291, 0.00524001", \ + "0.0104527, 0.00828577, 0.007719, 0.00733021, 0.00689769, 0.00646332, 0.00572373", \ + "0.0162876, 0.0121418, 0.0110012, 0.00979411, 0.0085835, 0.00815393, 0.00621741", \ + "0.0289368, 0.0216718, 0.0194306, 0.0170854, 0.0145661, 0.0114196, 0.0107433", \ + "0.055361, 0.0437731, 0.0396212, 0.0351745, 0.0303987, 0.0252448, 0.0197663" \ ); } fall_power (POWER_7x7ds1) { index_1 ("0.0186, 0.0966, 0.174, 0.3294, 0.6408, 1.263, 2.5074"); index_2 ("0.001, 0.0468, 0.078, 0.1296, 0.216, 0.36, 0.6"); values ( \ - "0.00755257, 0.00895731, 0.00901823, 0.00890988, 0.00880231, 0.00818556, 0.00756637", \ - "0.00795334, 0.00857752, 0.00863132, 0.00886903, 0.00858897, 0.00819965, 0.00752797", \ - "0.00907529, 0.00868562, 0.00880676, 0.00864137, 0.00881849, 0.00835212, 0.00736946", \ - "0.0120535, 0.0096156, 0.00945344, 0.00926926, 0.00874701, 0.00864589, 0.00805817", \ - "0.0182125, 0.0130948, 0.0122506, 0.0113317, 0.0106706, 0.00951681, 0.00844537", \ - "0.0312631, 0.022524, 0.0198467, 0.0174761, 0.015148, 0.0135274, 0.011996", \ - "0.0579346, 0.0449585, 0.0402046, 0.0349942, 0.0295773, 0.0242617, 0.0208429" \ + "0.00756869, 0.00896282, 0.00896855, 0.00889793, 0.00877694, 0.00825149, 0.00747694", \ + "0.00795205, 0.00858065, 0.00862112, 0.00887342, 0.0085911, 0.0082017, 0.00753847", \ + "0.00907595, 0.00868527, 0.00878066, 0.00865144, 0.00886699, 0.00828332, 0.00735557", \ + "0.012068, 0.0096156, 0.00945378, 0.00931064, 0.00875649, 0.00855526, 0.00780522", \ + "0.0182117, 0.0130927, 0.0122507, 0.011331, 0.0106672, 0.00950644, 0.0080087", \ + "0.0312628, 0.0225252, 0.0198401, 0.0175508, 0.0151171, 0.0135195, 0.0119358", \ + "0.0579234, 0.0449565, 0.0402186, 0.0349919, 0.0295383, 0.0242642, 0.0208236" \ ); } } @@ -2833,26 +2833,26 @@ library (sg13g2_stdcell_fast_1p32V_m40C) { index_1 ("0.0186, 0.0966, 0.174, 0.3294, 0.6408, 1.263, 2.5074"); index_2 ("0.001, 0.0468, 0.078, 0.1296, 0.216, 0.36, 0.6"); values ( \ - "0.00512483, 0.00628864, 0.00633127, 0.00624029, 0.00609761, 0.00548476, 0.00471767", \ - "0.00594445, 0.00584683, 0.00585756, 0.0060543, 0.00582106, 0.00546249, 0.00470333", \ - "0.00724707, 0.00611302, 0.00618047, 0.00597473, 0.005716, 0.00540203, 0.00495394", \ - "0.0103845, 0.00780831, 0.007148, 0.00668178, 0.00621498, 0.00579171, 0.00488862", \ - "0.0165233, 0.0116818, 0.0104669, 0.00921026, 0.00792218, 0.00755346, 0.0053544", \ - "0.0295589, 0.0214869, 0.0189581, 0.0166484, 0.0141935, 0.0108558, 0.00978135", \ - "0.056263, 0.0438252, 0.039549, 0.0348965, 0.0299494, 0.0247541, 0.0192667" \ + "0.00512286, 0.00630216, 0.00631693, 0.00626081, 0.00600466, 0.0054822, 0.00470238", \ + "0.00594496, 0.00593924, 0.00584705, 0.00607882, 0.00573705, 0.00546381, 0.00470367", \ + "0.00724962, 0.00612512, 0.00617871, 0.00592978, 0.00566479, 0.00537317, 0.00495306", \ + "0.0103848, 0.00780042, 0.00715148, 0.0067106, 0.00636558, 0.00583548, 0.00483436", \ + "0.0165221, 0.011684, 0.0104763, 0.00920993, 0.00802432, 0.00691802, 0.00540376", \ + "0.0295588, 0.0214857, 0.0189801, 0.0166573, 0.0141076, 0.0110993, 0.0101331", \ + "0.0562618, 0.0438248, 0.0395488, 0.0348995, 0.0299491, 0.0248325, 0.0192499" \ ); } fall_power (POWER_7x7ds1) { index_1 ("0.0186, 0.0966, 0.174, 0.3294, 0.6408, 1.263, 2.5074"); index_2 ("0.001, 0.0468, 0.078, 0.1296, 0.216, 0.36, 0.6"); values ( \ - "0.00333857, 0.00477547, 0.00477501, 0.00480902, 0.00459439, 0.00401798, 0.00350507", \ - "0.00370814, 0.00437495, 0.00445466, 0.00465538, 0.00451749, 0.00399776, 0.00327295", \ - "0.00492608, 0.00449169, 0.00462154, 0.0045415, 0.00464231, 0.00419498, 0.00385167", \ - "0.00800245, 0.00542617, 0.00527725, 0.00516447, 0.00479392, 0.00437313, 0.00396591", \ - "0.0142734, 0.00897817, 0.00813837, 0.0071732, 0.00647866, 0.00536794, 0.00421877", \ - "0.0274619, 0.0183409, 0.0157965, 0.0134481, 0.0110847, 0.00967194, 0.00779771", \ - "0.0543727, 0.0409612, 0.0360593, 0.03091, 0.0256497, 0.0204459, 0.0165463" \ + "0.00333852, 0.00481636, 0.0047665, 0.00475998, 0.00457058, 0.00403496, 0.0033155", \ + "0.00370996, 0.00437756, 0.00445191, 0.00465096, 0.00441646, 0.00401562, 0.00328267", \ + "0.00492651, 0.00449486, 0.00463107, 0.00447779, 0.00465214, 0.00419741, 0.00317536", \ + "0.00800186, 0.00545922, 0.00528585, 0.00511419, 0.00471901, 0.00434921, 0.00357575", \ + "0.0142723, 0.00897918, 0.0081395, 0.00707896, 0.00649148, 0.00532536, 0.00430244", \ + "0.0274619, 0.0183401, 0.0157964, 0.0134487, 0.0110802, 0.00953969, 0.00751151", \ + "0.054373, 0.0409593, 0.0360592, 0.0309291, 0.0256462, 0.0204425, 0.0165576" \ ); } } @@ -2863,26 +2863,26 @@ library (sg13g2_stdcell_fast_1p32V_m40C) { index_1 ("0.0186, 0.0966, 0.174, 0.3294, 0.6408, 1.263, 2.5074"); index_2 ("0.001, 0.0468, 0.078, 0.1296, 0.216, 0.36, 0.6"); values ( \ - "0.00515515, 0.00628254, 0.00632424, 0.00623941, 0.00601193, 0.005538, 0.0056204", \ - "0.00605883, 0.0058801, 0.00593352, 0.00585683, 0.0058504, 0.00563433, 0.00543979", \ - "0.00748275, 0.0062146, 0.00613384, 0.00613561, 0.00573102, 0.00530588, 0.00532231", \ - "0.0108432, 0.00801409, 0.00742585, 0.00672961, 0.00663172, 0.00583316, 0.0055461", \ - "0.0173826, 0.0122571, 0.0108884, 0.00971192, 0.00827222, 0.00738831, 0.0067878", \ - "0.0311402, 0.0226678, 0.020242, 0.0175479, 0.0150211, 0.0120257, 0.00945638", \ - "0.0594871, 0.0466216, 0.0421455, 0.0373016, 0.0318345, 0.0264994, 0.0212145" \ + "0.00515388, 0.0062732, 0.00632416, 0.00623909, 0.00601414, 0.00553734, 0.00559363", \ + "0.00605832, 0.00586225, 0.00592467, 0.00591917, 0.00580917, 0.00545349, 0.00543715", \ + "0.00747209, 0.00622951, 0.00613392, 0.00619931, 0.00570212, 0.00530131, 0.00550203", \ + "0.0108414, 0.0080097, 0.00743815, 0.00675749, 0.00671862, 0.00568919, 0.00549698", \ + "0.0173784, 0.0122567, 0.0108972, 0.0097011, 0.00816104, 0.0074121, 0.00677847", \ + "0.0311378, 0.0226684, 0.0202559, 0.0175555, 0.0149759, 0.0120278, 0.00929738", \ + "0.0594897, 0.0466233, 0.0421458, 0.0372979, 0.0318348, 0.0264997, 0.0210538" \ ); } fall_power (POWER_7x7ds1) { index_1 ("0.0186, 0.0966, 0.174, 0.3294, 0.6408, 1.263, 2.5074"); index_2 ("0.001, 0.0468, 0.078, 0.1296, 0.216, 0.36, 0.6"); values ( \ - "0.00314236, 0.00460187, 0.00456635, 0.00460746, 0.00441639, 0.00378247, 0.00330644", \ - "0.00367321, 0.00410241, 0.00417417, 0.00440679, 0.00422875, 0.00377214, 0.00360829", \ - "0.00498788, 0.00427619, 0.00438249, 0.00424408, 0.00435398, 0.00383568, 0.00300657", \ - "0.00825296, 0.0053889, 0.00516549, 0.00498876, 0.00437242, 0.00416747, 0.0033255", \ - "0.0149255, 0.00923266, 0.00831163, 0.00718049, 0.00643489, 0.0053067, 0.00382202", \ - "0.0289766, 0.0192959, 0.0167145, 0.0141506, 0.0112777, 0.00977812, 0.0079632", \ - "0.0575024, 0.04328, 0.0381213, 0.0326622, 0.0271258, 0.0212249, 0.0174042" \ + "0.00314244, 0.00461995, 0.00455835, 0.0046084, 0.00440765, 0.003831, 0.00331599", \ + "0.00367277, 0.0041137, 0.00416392, 0.00440538, 0.00421743, 0.00377367, 0.00303585", \ + "0.0049869, 0.00427474, 0.00437311, 0.00420951, 0.00437574, 0.00389118, 0.00300302", \ + "0.00825414, 0.00537113, 0.00516246, 0.00495331, 0.00447065, 0.00416955, 0.00330134", \ + "0.0149235, 0.00923163, 0.00831243, 0.00721211, 0.00643523, 0.00525243, 0.00405139", \ + "0.0289779, 0.0192967, 0.0167151, 0.0141198, 0.0113961, 0.00983229, 0.00787154", \ + "0.0575032, 0.0432793, 0.0381229, 0.0326624, 0.0271255, 0.0212201, 0.0172531" \ ); } } @@ -2892,26 +2892,26 @@ library (sg13g2_stdcell_fast_1p32V_m40C) { index_1 ("0.0186, 0.0966, 0.174, 0.3294, 0.6408, 1.263, 2.5074"); index_2 ("0.001, 0.0468, 0.078, 0.1296, 0.216, 0.36, 0.6"); values ( \ - "0.00602425, 0.00691993, 0.00697402, 0.00683795, 0.00666931, 0.00613977, 0.00530091", \ - "0.00645209, 0.00658143, 0.00651563, 0.00679049, 0.00636285, 0.00607855, 0.00529677", \ - "0.00759526, 0.00669443, 0.00677963, 0.00659645, 0.006317, 0.00598067, 0.00557497", \ - "0.0104524, 0.00829811, 0.00769067, 0.00728779, 0.00689949, 0.00644414, 0.00572835", \ - "0.0162866, 0.012142, 0.0110017, 0.00975471, 0.00857152, 0.00746951, 0.00583293", \ - "0.0289377, 0.0216695, 0.0193429, 0.0171004, 0.0145688, 0.0114204, 0.0106997", \ - "0.0553596, 0.0437736, 0.0396216, 0.0351753, 0.0303984, 0.0253365, 0.0198437" \ + "0.00603004, 0.00692394, 0.00697303, 0.00683653, 0.00667044, 0.00614219, 0.00528965", \ + "0.00644713, 0.00658726, 0.00651729, 0.00678256, 0.0063723, 0.0060761, 0.00529939", \ + "0.0075929, 0.00670586, 0.00678715, 0.00649858, 0.00631716, 0.00601291, 0.00524001", \ + "0.0104527, 0.00828577, 0.007719, 0.00733021, 0.00689769, 0.00646332, 0.00572373", \ + "0.0162876, 0.0121418, 0.0110012, 0.00979411, 0.0085835, 0.00815393, 0.00621741", \ + "0.0289368, 0.0216718, 0.0194306, 0.0170854, 0.0145661, 0.0114196, 0.0107433", \ + "0.055361, 0.0437731, 0.0396212, 0.0351745, 0.0303987, 0.0252448, 0.0197663" \ ); } fall_power (POWER_7x7ds1) { index_1 ("0.0186, 0.0966, 0.174, 0.3294, 0.6408, 1.263, 2.5074"); index_2 ("0.001, 0.0468, 0.078, 0.1296, 0.216, 0.36, 0.6"); values ( \ - "0.00314236, 0.00460187, 0.00456635, 0.00460746, 0.00441639, 0.00378247, 0.00330644", \ - "0.00367321, 0.00410241, 0.00417417, 0.00440679, 0.00422875, 0.00377214, 0.00360829", \ - "0.00498788, 0.00427619, 0.00438249, 0.00424408, 0.00435398, 0.00383568, 0.00300657", \ - "0.00825296, 0.0053889, 0.00516549, 0.00498876, 0.00437242, 0.00416747, 0.0033255", \ - "0.0149255, 0.00923266, 0.00831163, 0.00718049, 0.00643489, 0.0053067, 0.00382202", \ - "0.0289766, 0.0192959, 0.0167145, 0.0141506, 0.0112777, 0.00977812, 0.0079632", \ - "0.0575024, 0.04328, 0.0381213, 0.0326622, 0.0271258, 0.0212249, 0.0174042" \ + "0.00314244, 0.00461995, 0.00455835, 0.0046084, 0.00440765, 0.003831, 0.00331599", \ + "0.00367277, 0.0041137, 0.00416392, 0.00440538, 0.00421743, 0.00377367, 0.00303585", \ + "0.0049869, 0.00427474, 0.00437311, 0.00420951, 0.00437574, 0.00389118, 0.00300302", \ + "0.00825414, 0.00537113, 0.00516246, 0.00495331, 0.00447065, 0.00416955, 0.00330134", \ + "0.0149235, 0.00923163, 0.00831243, 0.00721211, 0.00643523, 0.00525243, 0.00405139", \ + "0.0289779, 0.0192967, 0.0167151, 0.0141198, 0.0113961, 0.00983229, 0.00787154", \ + "0.0575032, 0.0432793, 0.0381229, 0.0326624, 0.0271255, 0.0212201, 0.0172531" \ ); } } @@ -2919,29 +2919,29 @@ library (sg13g2_stdcell_fast_1p32V_m40C) { pin (A1) { direction : "input"; max_transition : 2.5074; - capacitance : 0.00624851; - rise_capacitance : 0.00608415; - rise_capacitance_range (0.00608415, 0.00608415); + capacitance : 0.0062486; + rise_capacitance : 0.00608434; + rise_capacitance_range (0.0055928, 0.00667379); fall_capacitance : 0.00641287; - fall_capacitance_range (0.00641287, 0.00641287); + fall_capacitance_range (0.00537826, 0.00737657); } pin (A2) { direction : "input"; max_transition : 2.5074; - capacitance : 0.00658673; - rise_capacitance : 0.00665696; - rise_capacitance_range (0.00665696, 0.00665696); - fall_capacitance : 0.00651651; - fall_capacitance_range (0.00651651, 0.00651651); + capacitance : 0.00658682; + rise_capacitance : 0.00665686; + rise_capacitance_range (0.00573892, 0.00732809); + fall_capacitance : 0.00651678; + fall_capacitance_range (0.00568643, 0.00720687); } pin (B1) { direction : "input"; max_transition : 2.5074; - capacitance : 0.0060058; - rise_capacitance : 0.00617319; - rise_capacitance_range (0.00617319, 0.00617319); - fall_capacitance : 0.00583842; - fall_capacitance_range (0.00583842, 0.00583842); + capacitance : 0.00600575; + rise_capacitance : 0.00617307; + rise_capacitance_range (0.00502203, 0.0076198); + fall_capacitance : 0.00583844; + fall_capacitance_range (0.00530035, 0.00681719); } } cell (sg13g2_a221oi_1) { @@ -5010,113 +5010,113 @@ library (sg13g2_stdcell_fast_1p32V_m40C) { max_transition : 2.5074; capacitance : 0.00318502; rise_capacitance : 0.00310119; - rise_capacitance_range (0.00310119, 0.00310119); + rise_capacitance_range (0.00291989, 0.00336685); fall_capacitance : 0.00326886; - fall_capacitance_range (0.00326886, 0.00326886); + fall_capacitance_range (0.00279316, 0.0037212); } pin (A2) { direction : "input"; max_transition : 2.5074; capacitance : 0.00325924; rise_capacitance : 0.00329036; - rise_capacitance_range (0.00329036, 0.00329036); + rise_capacitance_range (0.00285038, 0.0035971); fall_capacitance : 0.00322811; - fall_capacitance_range (0.00322811, 0.00322811); + fall_capacitance_range (0.0028345, 0.00360051); } pin (B1) { direction : "input"; max_transition : 2.5074; capacitance : 0.0031338; rise_capacitance : 0.00308759; - rise_capacitance_range (0.00308759, 0.00308759); + rise_capacitance_range (0.00273299, 0.00348902); fall_capacitance : 0.00318002; - fall_capacitance_range (0.00318002, 0.00318002); + fall_capacitance_range (0.00267765, 0.00358651); } pin (B2) { direction : "input"; max_transition : 2.5074; capacitance : 0.00326595; rise_capacitance : 0.00333515; - rise_capacitance_range (0.00333515, 0.00333515); + rise_capacitance_range (0.00277133, 0.00375492); fall_capacitance : 0.00319675; - fall_capacitance_range (0.00319675, 0.00319675); + fall_capacitance_range (0.00277706, 0.00352642); } pin (C1) { direction : "input"; max_transition : 2.5074; capacitance : 0.00303492; rise_capacitance : 0.0031326; - rise_capacitance_range (0.0031326, 0.0031326); + rise_capacitance_range (0.0026094, 0.00382197); fall_capacitance : 0.00293723; - fall_capacitance_range (0.00293723, 0.00293723); + fall_capacitance_range (0.00271095, 0.00325985); } } cell (sg13g2_a22oi_1) { area : 10.8486; cell_footprint : "a22oi"; - cell_leakage_power : 355.448; + cell_leakage_power : 355.472; leakage_power () { - value : 283.839; + value : 283.863; when : "!A1&!A2&!B1&!B2&Y"; } leakage_power () { - value : 221.756; + value : 221.78; when : "!A1&!A2&!B1&B2&Y"; } leakage_power () { - value : 343.135; + value : 343.159; when : "!A1&!A2&B1&!B2&Y"; } leakage_power () { - value : 451.267; + value : 451.291; when : "!A1&!A2&B1&B2&!Y"; } leakage_power () { - value : 343.222; + value : 343.246; when : "!A1&A2&!B1&!B2&Y"; } leakage_power () { - value : 281.138; + value : 281.162; when : "!A1&A2&!B1&B2&Y"; } leakage_power () { - value : 402.517; + value : 402.541; when : "!A1&A2&B1&!B2&Y"; } leakage_power () { - value : 505.748; + value : 505.773; when : "!A1&A2&B1&B2&!Y"; } leakage_power () { - value : 221.734; + value : 221.758; when : "A1&!A2&!B1&!B2&Y"; } leakage_power () { - value : 159.65; + value : 159.674; when : "A1&!A2&!B1&B2&Y"; } leakage_power () { - value : 281.029; + value : 281.053; when : "A1&!A2&B1&!B2&Y"; } leakage_power () { - value : 505.64; + value : 505.664; when : "A1&!A2&B1&B2&!Y"; } leakage_power () { - value : 306.993; + value : 307.018; when : "A1&A2&!B1&!B2&!Y"; } leakage_power () { - value : 433.559; + value : 433.583; when : "A1&A2&!B1&B2&!Y"; } leakage_power () { - value : 433.558; + value : 433.583; when : "A1&A2&B1&!B2&!Y"; } leakage_power () { - value : 512.383; + value : 512.407; when : "A1&A2&B1&B2&!Y"; } pin (Y) { @@ -5134,52 +5134,52 @@ library (sg13g2_stdcell_fast_1p32V_m40C) { index_1 ("0.0186, 0.0966, 0.174, 0.3294, 0.6408, 1.263, 2.5074"); index_2 ("0.001, 0.0234, 0.039, 0.0648, 0.108, 0.18, 0.3"); values ( \ - "0.0366166, 0.119904, 0.176697, 0.270368, 0.427164, 0.688669, 1.1242", \ - "0.0548638, 0.14732, 0.204808, 0.298898, 0.455923, 0.717968, 1.15286", \ - "0.0637813, 0.168984, 0.229324, 0.32472, 0.481968, 0.743493, 1.17967", \ - "0.0728717, 0.202801, 0.270424, 0.372629, 0.533818, 0.796415, 1.23229", \ - "0.082224, 0.250842, 0.332095, 0.449186, 0.625538, 0.89797, 1.33701", \ - "0.0940761, 0.315497, 0.420788, 0.564892, 0.770772, 1.0746, 1.53852", \ - "0.101846, 0.395856, 0.534413, 0.722909, 0.982928, 1.34438, 1.87319" \ + "0.0366168, 0.119876, 0.176701, 0.270511, 0.427522, 0.688666, 1.12419", \ + "0.054913, 0.147333, 0.204777, 0.298843, 0.456108, 0.717966, 1.15284", \ + "0.0637812, 0.168984, 0.229323, 0.324719, 0.481959, 0.743579, 1.17968", \ + "0.0728714, 0.2028, 0.270423, 0.372627, 0.533816, 0.796412, 1.23225", \ + "0.0822236, 0.250841, 0.332094, 0.449185, 0.625536, 0.897966, 1.33701", \ + "0.0940752, 0.315496, 0.420787, 0.56489, 0.770769, 1.0746, 1.53851", \ + "0.101845, 0.395854, 0.534411, 0.722908, 0.982924, 1.34438, 1.87318" \ ); } rise_transition (TIMING_DELAY_7x7ds1) { index_1 ("0.0186, 0.0966, 0.174, 0.3294, 0.6408, 1.263, 2.5074"); index_2 ("0.001, 0.0234, 0.039, 0.0648, 0.108, 0.18, 0.3"); values ( \ - "0.0221667, 0.137399, 0.21776, 0.350704, 0.573252, 0.94382, 1.56181", \ - "0.0318717, 0.140976, 0.219269, 0.350757, 0.573253, 0.944271, 1.5624", \ - "0.0414189, 0.150996, 0.226549, 0.354656, 0.573944, 0.944601, 1.56241", \ - "0.0603989, 0.175826, 0.249324, 0.372669, 0.584661, 0.947671, 1.56571", \ - "0.0936214, 0.221796, 0.297861, 0.419434, 0.624457, 0.973308, 1.57348", \ - "0.144699, 0.302907, 0.387668, 0.51501, 0.720498, 1.06049, 1.63597", \ - "0.22397, 0.435201, 0.537718, 0.68377, 0.905098, 1.25308, 1.82081" \ + "0.0221668, 0.13737, 0.217762, 0.350704, 0.573119, 0.943814, 1.5618", \ + "0.0318959, 0.141029, 0.219261, 0.351649, 0.57312, 0.944265, 1.56239", \ + "0.041422, 0.150995, 0.226548, 0.354732, 0.573895, 0.944802, 1.5624", \ + "0.0603987, 0.175825, 0.249322, 0.372666, 0.584658, 0.947658, 1.5649", \ + "0.0936212, 0.221795, 0.29786, 0.419433, 0.624453, 0.973301, 1.57351", \ + "0.144699, 0.302905, 0.387668, 0.515008, 0.720495, 1.06048, 1.63596", \ + "0.223969, 0.4352, 0.537716, 0.683775, 0.905095, 1.25308, 1.8208" \ ); } cell_fall (TIMING_DELAY_7x7ds1) { index_1 ("0.0186, 0.0966, 0.174, 0.3294, 0.6408, 1.263, 2.5074"); index_2 ("0.001, 0.0234, 0.039, 0.0648, 0.108, 0.18, 0.3"); values ( \ - "0.0332399, 0.0987589, 0.142817, 0.215272, 0.33637, 0.537887, 0.874097", \ - "0.0572997, 0.136759, 0.18215, 0.254883, 0.375902, 0.577452, 0.913234", \ - "0.0728011, 0.167726, 0.218104, 0.294502, 0.416838, 0.618409, 0.954135", \ - "0.0935251, 0.213189, 0.274334, 0.361846, 0.493304, 0.698785, 1.0347", \ - "0.122755, 0.276646, 0.353566, 0.46225, 0.617086, 0.844572, 1.19121", \ - "0.164875, 0.362298, 0.464472, 0.604757, 0.799719, 1.07422, 1.47124", \ - "0.225622, 0.485354, 0.615047, 0.798444, 1.05523, 1.40571, 1.89553" \ + "0.0332388, 0.0987516, 0.142816, 0.215276, 0.336379, 0.53798, 0.874116", \ + "0.0573001, 0.13676, 0.182153, 0.254884, 0.375872, 0.577462, 0.913237", \ + "0.0728015, 0.167727, 0.218106, 0.29452, 0.41687, 0.618405, 0.954171", \ + "0.0935257, 0.21319, 0.274307, 0.361849, 0.493309, 0.698792, 1.03472", \ + "0.122756, 0.276649, 0.353766, 0.462253, 0.617091, 0.84458, 1.19124", \ + "0.164876, 0.3623, 0.464475, 0.604761, 0.799725, 1.07423, 1.47121", \ + "0.225635, 0.485357, 0.615051, 0.798449, 1.05523, 1.40572, 1.89554" \ ); } fall_transition (TIMING_DELAY_7x7ds1) { index_1 ("0.0186, 0.0966, 0.174, 0.3294, 0.6408, 1.263, 2.5074"); index_2 ("0.001, 0.0234, 0.039, 0.0648, 0.108, 0.18, 0.3"); values ( \ - "0.0246754, 0.110072, 0.169773, 0.268332, 0.433331, 0.708009, 1.16687", \ - "0.038904, 0.119461, 0.174888, 0.269974, 0.433871, 0.708358, 1.16688", \ - "0.0511643, 0.136538, 0.190622, 0.28112, 0.438891, 0.709957, 1.16689", \ - "0.0705714, 0.170758, 0.226438, 0.315202, 0.4645, 0.723269, 1.1707", \ - "0.1011, 0.226053, 0.291141, 0.385279, 0.535799, 0.7816, 1.2049", \ - "0.15148, 0.313889, 0.393219, 0.506494, 0.670472, 0.92523, 1.33432", \ - "0.234912, 0.449712, 0.551892, 0.696654, 0.897782, 1.18818, 1.61951" \ + "0.024645, 0.110068, 0.169775, 0.268337, 0.433339, 0.708524, 1.16688", \ + "0.0389043, 0.119462, 0.174939, 0.270133, 0.433553, 0.708525, 1.16689", \ + "0.0511646, 0.13654, 0.190624, 0.281147, 0.438791, 0.709824, 1.1669", \ + "0.0705716, 0.170758, 0.226238, 0.315204, 0.464512, 0.723282, 1.17073", \ + "0.1011, 0.226068, 0.290736, 0.38526, 0.535805, 0.781611, 1.20457", \ + "0.15148, 0.313891, 0.393227, 0.506498, 0.670477, 0.925205, 1.33433", \ + "0.234826, 0.449714, 0.551895, 0.696658, 0.897787, 1.18819, 1.61953" \ ); } } @@ -5191,52 +5191,52 @@ library (sg13g2_stdcell_fast_1p32V_m40C) { index_1 ("0.0186, 0.0966, 0.174, 0.3294, 0.6408, 1.263, 2.5074"); index_2 ("0.001, 0.0234, 0.039, 0.0648, 0.108, 0.18, 0.3"); values ( \ - "0.0366166, 0.119904, 0.176697, 0.270368, 0.427164, 0.688669, 1.1242", \ - "0.0548638, 0.14732, 0.204808, 0.298898, 0.455923, 0.717968, 1.15286", \ - "0.0637813, 0.168984, 0.229324, 0.32472, 0.481968, 0.743493, 1.17967", \ - "0.0728717, 0.202801, 0.270424, 0.372629, 0.533818, 0.796415, 1.23229", \ - "0.082224, 0.250842, 0.332095, 0.449186, 0.625538, 0.89797, 1.33701", \ - "0.0940761, 0.315497, 0.420788, 0.564892, 0.770772, 1.0746, 1.53852", \ - "0.101846, 0.395856, 0.534413, 0.722909, 0.982928, 1.34438, 1.87319" \ + "0.0366168, 0.119876, 0.176701, 0.270511, 0.427522, 0.688666, 1.12419", \ + "0.054913, 0.147333, 0.204777, 0.298843, 0.456108, 0.717966, 1.15284", \ + "0.0637812, 0.168984, 0.229323, 0.324719, 0.481959, 0.743579, 1.17968", \ + "0.0728714, 0.2028, 0.270423, 0.372627, 0.533816, 0.796412, 1.23225", \ + "0.0822236, 0.250841, 0.332094, 0.449185, 0.625536, 0.897966, 1.33701", \ + "0.0940752, 0.315496, 0.420787, 0.56489, 0.770769, 1.0746, 1.53851", \ + "0.101845, 0.395854, 0.534411, 0.722908, 0.982924, 1.34438, 1.87318" \ ); } rise_transition (TIMING_DELAY_7x7ds1) { index_1 ("0.0186, 0.0966, 0.174, 0.3294, 0.6408, 1.263, 2.5074"); index_2 ("0.001, 0.0234, 0.039, 0.0648, 0.108, 0.18, 0.3"); values ( \ - "0.0221667, 0.137399, 0.21776, 0.350704, 0.573252, 0.94382, 1.56181", \ - "0.0318717, 0.140976, 0.219269, 0.350757, 0.573253, 0.944271, 1.5624", \ - "0.0414189, 0.150996, 0.226549, 0.354656, 0.573944, 0.944601, 1.56241", \ - "0.0603989, 0.175826, 0.249324, 0.372669, 0.584661, 0.947671, 1.56571", \ - "0.0936214, 0.221796, 0.297861, 0.419434, 0.624457, 0.973308, 1.57348", \ - "0.144699, 0.302907, 0.387668, 0.51501, 0.720498, 1.06049, 1.63597", \ - "0.22397, 0.435201, 0.537718, 0.68377, 0.905098, 1.25308, 1.82081" \ + "0.0221668, 0.13737, 0.217762, 0.350704, 0.573119, 0.943814, 1.5618", \ + "0.0318959, 0.141029, 0.219261, 0.351649, 0.57312, 0.944265, 1.56239", \ + "0.041422, 0.150995, 0.226548, 0.354732, 0.573895, 0.944802, 1.5624", \ + "0.0603987, 0.175825, 0.249322, 0.372666, 0.584658, 0.947658, 1.5649", \ + "0.0936212, 0.221795, 0.29786, 0.419433, 0.624453, 0.973301, 1.57351", \ + "0.144699, 0.302905, 0.387668, 0.515008, 0.720495, 1.06048, 1.63596", \ + "0.223969, 0.4352, 0.537716, 0.683775, 0.905095, 1.25308, 1.8208" \ ); } cell_fall (TIMING_DELAY_7x7ds1) { index_1 ("0.0186, 0.0966, 0.174, 0.3294, 0.6408, 1.263, 2.5074"); index_2 ("0.001, 0.0234, 0.039, 0.0648, 0.108, 0.18, 0.3"); values ( \ - "0.0332399, 0.0987589, 0.142817, 0.215272, 0.33637, 0.537887, 0.874097", \ - "0.0572997, 0.136759, 0.18215, 0.254883, 0.375902, 0.577452, 0.913234", \ - "0.0728011, 0.167726, 0.218104, 0.294502, 0.416838, 0.618409, 0.954135", \ - "0.0935251, 0.213189, 0.274334, 0.361846, 0.493304, 0.698785, 1.0347", \ - "0.122755, 0.276646, 0.353566, 0.46225, 0.617086, 0.844572, 1.19121", \ - "0.164875, 0.362298, 0.464472, 0.604757, 0.799719, 1.07422, 1.47124", \ - "0.225622, 0.485354, 0.615047, 0.798444, 1.05523, 1.40571, 1.89553" \ + "0.0332388, 0.0987516, 0.142816, 0.215276, 0.336379, 0.53798, 0.874116", \ + "0.0573001, 0.13676, 0.182153, 0.254884, 0.375872, 0.577462, 0.913237", \ + "0.0728015, 0.167727, 0.218106, 0.29452, 0.41687, 0.618405, 0.954171", \ + "0.0935257, 0.21319, 0.274307, 0.361849, 0.493309, 0.698792, 1.03472", \ + "0.122756, 0.276649, 0.353766, 0.462253, 0.617091, 0.84458, 1.19124", \ + "0.164876, 0.3623, 0.464475, 0.604761, 0.799725, 1.07423, 1.47121", \ + "0.225635, 0.485357, 0.615051, 0.798449, 1.05523, 1.40572, 1.89554" \ ); } fall_transition (TIMING_DELAY_7x7ds1) { index_1 ("0.0186, 0.0966, 0.174, 0.3294, 0.6408, 1.263, 2.5074"); index_2 ("0.001, 0.0234, 0.039, 0.0648, 0.108, 0.18, 0.3"); values ( \ - "0.0246754, 0.110072, 0.169773, 0.268332, 0.433331, 0.708009, 1.16687", \ - "0.038904, 0.119461, 0.174888, 0.269974, 0.433871, 0.708358, 1.16688", \ - "0.0511643, 0.136538, 0.190622, 0.28112, 0.438891, 0.709957, 1.16689", \ - "0.0705714, 0.170758, 0.226438, 0.315202, 0.4645, 0.723269, 1.1707", \ - "0.1011, 0.226053, 0.291141, 0.385279, 0.535799, 0.7816, 1.2049", \ - "0.15148, 0.313889, 0.393219, 0.506494, 0.670472, 0.92523, 1.33432", \ - "0.234912, 0.449712, 0.551892, 0.696654, 0.897782, 1.18818, 1.61951" \ + "0.024645, 0.110068, 0.169775, 0.268337, 0.433339, 0.708524, 1.16688", \ + "0.0389043, 0.119462, 0.174939, 0.270133, 0.433553, 0.708525, 1.16689", \ + "0.0511646, 0.13654, 0.190624, 0.281147, 0.438791, 0.709824, 1.1669", \ + "0.0705716, 0.170758, 0.226238, 0.315204, 0.464512, 0.723282, 1.17073", \ + "0.1011, 0.226068, 0.290736, 0.38526, 0.535805, 0.781611, 1.20457", \ + "0.15148, 0.313891, 0.393227, 0.506498, 0.670477, 0.925205, 1.33433", \ + "0.234826, 0.449714, 0.551895, 0.696658, 0.897787, 1.18819, 1.61953" \ ); } } @@ -5250,52 +5250,52 @@ library (sg13g2_stdcell_fast_1p32V_m40C) { index_1 ("0.0186, 0.0966, 0.174, 0.3294, 0.6408, 1.263, 2.5074"); index_2 ("0.001, 0.0234, 0.039, 0.0648, 0.108, 0.18, 0.3"); values ( \ - "0.0416176, 0.123839, 0.180301, 0.273568, 0.429628, 0.689872, 1.12331", \ - "0.0623582, 0.152109, 0.209057, 0.302504, 0.458778, 0.71934, 1.15184", \ - "0.0731861, 0.174452, 0.233962, 0.328663, 0.484945, 0.745161, 1.17902", \ - "0.0855391, 0.20958, 0.276255, 0.377304, 0.537444, 0.798537, 1.23207", \ - "0.100725, 0.259986, 0.33935, 0.455653, 0.629896, 0.900919, 1.33772", \ - "0.12215, 0.32968, 0.43159, 0.573126, 0.777902, 1.07885, 1.54029", \ - "0.148364, 0.419968, 0.553999, 0.738317, 0.994167, 1.35324, 1.87754" \ + "0.0416116, 0.123845, 0.180299, 0.273809, 0.42997, 0.689878, 1.12332", \ + "0.0623162, 0.152159, 0.209081, 0.302491, 0.458612, 0.719291, 1.15176", \ + "0.0731791, 0.174452, 0.233958, 0.328664, 0.484942, 0.745193, 1.17902", \ + "0.0855394, 0.209581, 0.276256, 0.377316, 0.537446, 0.79854, 1.23214", \ + "0.100725, 0.259987, 0.339352, 0.455655, 0.629902, 0.900923, 1.33775", \ + "0.122151, 0.329681, 0.431591, 0.573128, 0.777905, 1.07885, 1.54029", \ + "0.148364, 0.419969, 0.554, 0.738319, 0.994171, 1.35325, 1.87754" \ ); } rise_transition (TIMING_DELAY_7x7ds1) { index_1 ("0.0186, 0.0966, 0.174, 0.3294, 0.6408, 1.263, 2.5074"); index_2 ("0.001, 0.0234, 0.039, 0.0648, 0.108, 0.18, 0.3"); values ( \ - "0.0273325, 0.142324, 0.22245, 0.354769, 0.576274, 0.945042, 1.55991", \ - "0.0364064, 0.145822, 0.223803, 0.354891, 0.576275, 0.945414, 1.56032", \ - "0.0459806, 0.155658, 0.231063, 0.358838, 0.577047, 0.94754, 1.56033", \ - "0.0648583, 0.179972, 0.253565, 0.37669, 0.587681, 0.94891, 1.56359", \ - "0.0968212, 0.226119, 0.301764, 0.423345, 0.627252, 0.97453, 1.57179", \ - "0.145618, 0.306517, 0.390954, 0.517937, 0.723, 1.06207, 1.63456", \ - "0.219856, 0.43343, 0.538303, 0.68504, 0.906922, 1.25538, 1.81949" \ + "0.0273166, 0.142376, 0.222347, 0.35465, 0.576126, 0.945048, 1.55999", \ + "0.0363753, 0.14582, 0.223816, 0.354894, 0.576127, 0.945398, 1.56034", \ + "0.0460223, 0.155658, 0.231048, 0.35884, 0.577246, 0.947571, 1.56035", \ + "0.0648585, 0.179972, 0.253566, 0.376645, 0.587691, 0.948915, 1.56366", \ + "0.0968213, 0.22612, 0.301766, 0.423347, 0.627302, 0.974534, 1.57154", \ + "0.14562, 0.306518, 0.390956, 0.517938, 0.723003, 1.06208, 1.63444", \ + "0.219857, 0.433432, 0.538305, 0.685043, 0.906925, 1.25539, 1.8195" \ ); } cell_fall (TIMING_DELAY_7x7ds1) { index_1 ("0.0186, 0.0966, 0.174, 0.3294, 0.6408, 1.263, 2.5074"); index_2 ("0.001, 0.0234, 0.039, 0.0648, 0.108, 0.18, 0.3"); values ( \ - "0.0355765, 0.100878, 0.144889, 0.217373, 0.338541, 0.540056, 0.875938", \ - "0.0571986, 0.131729, 0.176873, 0.249687, 0.370866, 0.572568, 0.908415", \ - "0.0715089, 0.157544, 0.20599, 0.281319, 0.40356, 0.605455, 0.941344", \ - "0.0901792, 0.197076, 0.252957, 0.335852, 0.464365, 0.66928, 1.00579", \ - "0.116329, 0.254184, 0.323375, 0.421369, 0.566164, 0.786317, 1.13064", \ - "0.153868, 0.333886, 0.424075, 0.549688, 0.724785, 0.978733, 1.35558", \ - "0.205496, 0.447268, 0.563611, 0.726962, 0.956099, 1.27086, 1.71403" \ + "0.0355703, 0.100872, 0.144895, 0.217377, 0.338545, 0.540071, 0.875952", \ + "0.0572, 0.13173, 0.176875, 0.24974, 0.370913, 0.572527, 0.908295", \ + "0.0715095, 0.157549, 0.205965, 0.281323, 0.403579, 0.605473, 0.941449", \ + "0.0901799, 0.197078, 0.252959, 0.335855, 0.464406, 0.6693, 1.00581", \ + "0.116329, 0.254186, 0.323472, 0.421373, 0.56617, 0.786325, 1.13065", \ + "0.153869, 0.333889, 0.424079, 0.549692, 0.724792, 0.978742, 1.3556", \ + "0.205498, 0.447271, 0.563616, 0.726968, 0.956107, 1.27087, 1.71405" \ ); } fall_transition (TIMING_DELAY_7x7ds1) { index_1 ("0.0186, 0.0966, 0.174, 0.3294, 0.6408, 1.263, 2.5074"); index_2 ("0.001, 0.0234, 0.039, 0.0648, 0.108, 0.18, 0.3"); values ( \ - "0.0242445, 0.109923, 0.169772, 0.268324, 0.433437, 0.708532, 1.167", \ - "0.0337704, 0.11576, 0.173046, 0.269413, 0.43383, 0.708533, 1.16701", \ - "0.0435955, 0.127067, 0.18281, 0.276377, 0.436718, 0.709281, 1.16702", \ - "0.0617785, 0.152207, 0.207672, 0.298672, 0.453184, 0.718177, 1.16949", \ - "0.0917712, 0.196697, 0.255895, 0.348638, 0.501232, 0.755834, 1.19175", \ - "0.139467, 0.27185, 0.341503, 0.443985, 0.601588, 0.855011, 1.27766", \ - "0.216554, 0.391795, 0.478539, 0.603464, 0.783826, 1.05484, 1.47786" \ + "0.0242576, 0.109916, 0.169775, 0.268329, 0.433444, 0.708543, 1.16702", \ + "0.0337703, 0.115773, 0.173049, 0.269786, 0.435731, 0.708544, 1.16703", \ + "0.0435958, 0.127095, 0.182757, 0.276381, 0.436857, 0.711478, 1.16704", \ + "0.0617791, 0.152208, 0.207674, 0.298676, 0.453233, 0.718318, 1.16951", \ + "0.0917717, 0.196699, 0.256071, 0.348642, 0.501239, 0.755844, 1.19117", \ + "0.139467, 0.271852, 0.341505, 0.443988, 0.601594, 0.855021, 1.27768", \ + "0.216556, 0.391797, 0.478543, 0.603482, 0.783832, 1.05485, 1.47788" \ ); } } @@ -5307,52 +5307,52 @@ library (sg13g2_stdcell_fast_1p32V_m40C) { index_1 ("0.0186, 0.0966, 0.174, 0.3294, 0.6408, 1.263, 2.5074"); index_2 ("0.001, 0.0234, 0.039, 0.0648, 0.108, 0.18, 0.3"); values ( \ - "0.0416176, 0.123839, 0.180301, 0.273568, 0.429628, 0.689872, 1.12331", \ - "0.0623582, 0.152109, 0.209057, 0.302504, 0.458778, 0.71934, 1.15184", \ - "0.0731861, 0.174452, 0.233962, 0.328663, 0.484945, 0.745161, 1.17902", \ - "0.0855391, 0.20958, 0.276255, 0.377304, 0.537444, 0.798537, 1.23207", \ - "0.100725, 0.259986, 0.33935, 0.455653, 0.629896, 0.900919, 1.33772", \ - "0.12215, 0.32968, 0.43159, 0.573126, 0.777902, 1.07885, 1.54029", \ - "0.148364, 0.419968, 0.553999, 0.738317, 0.994167, 1.35324, 1.87754" \ + "0.0416116, 0.123845, 0.180299, 0.273809, 0.42997, 0.689878, 1.12332", \ + "0.0623162, 0.152159, 0.209081, 0.302491, 0.458612, 0.719291, 1.15176", \ + "0.0731791, 0.174452, 0.233958, 0.328664, 0.484942, 0.745193, 1.17902", \ + "0.0855394, 0.209581, 0.276256, 0.377316, 0.537446, 0.79854, 1.23214", \ + "0.100725, 0.259987, 0.339352, 0.455655, 0.629902, 0.900923, 1.33775", \ + "0.122151, 0.329681, 0.431591, 0.573128, 0.777905, 1.07885, 1.54029", \ + "0.148364, 0.419969, 0.554, 0.738319, 0.994171, 1.35325, 1.87754" \ ); } rise_transition (TIMING_DELAY_7x7ds1) { index_1 ("0.0186, 0.0966, 0.174, 0.3294, 0.6408, 1.263, 2.5074"); index_2 ("0.001, 0.0234, 0.039, 0.0648, 0.108, 0.18, 0.3"); values ( \ - "0.0273325, 0.142324, 0.22245, 0.354769, 0.576274, 0.945042, 1.55991", \ - "0.0364064, 0.145822, 0.223803, 0.354891, 0.576275, 0.945414, 1.56032", \ - "0.0459806, 0.155658, 0.231063, 0.358838, 0.577047, 0.94754, 1.56033", \ - "0.0648583, 0.179972, 0.253565, 0.37669, 0.587681, 0.94891, 1.56359", \ - "0.0968212, 0.226119, 0.301764, 0.423345, 0.627252, 0.97453, 1.57179", \ - "0.145618, 0.306517, 0.390954, 0.517937, 0.723, 1.06207, 1.63456", \ - "0.219856, 0.43343, 0.538303, 0.68504, 0.906922, 1.25538, 1.81949" \ + "0.0273166, 0.142376, 0.222347, 0.35465, 0.576126, 0.945048, 1.55999", \ + "0.0363753, 0.14582, 0.223816, 0.354894, 0.576127, 0.945398, 1.56034", \ + "0.0460223, 0.155658, 0.231048, 0.35884, 0.577246, 0.947571, 1.56035", \ + "0.0648585, 0.179972, 0.253566, 0.376645, 0.587691, 0.948915, 1.56366", \ + "0.0968213, 0.22612, 0.301766, 0.423347, 0.627302, 0.974534, 1.57154", \ + "0.14562, 0.306518, 0.390956, 0.517938, 0.723003, 1.06208, 1.63444", \ + "0.219857, 0.433432, 0.538305, 0.685043, 0.906925, 1.25539, 1.8195" \ ); } cell_fall (TIMING_DELAY_7x7ds1) { index_1 ("0.0186, 0.0966, 0.174, 0.3294, 0.6408, 1.263, 2.5074"); index_2 ("0.001, 0.0234, 0.039, 0.0648, 0.108, 0.18, 0.3"); values ( \ - "0.0355765, 0.100878, 0.144889, 0.217373, 0.338541, 0.540056, 0.875938", \ - "0.0571986, 0.131729, 0.176873, 0.249687, 0.370866, 0.572568, 0.908415", \ - "0.0715089, 0.157544, 0.20599, 0.281319, 0.40356, 0.605455, 0.941344", \ - "0.0901792, 0.197076, 0.252957, 0.335852, 0.464365, 0.66928, 1.00579", \ - "0.116329, 0.254184, 0.323375, 0.421369, 0.566164, 0.786317, 1.13064", \ - "0.153868, 0.333886, 0.424075, 0.549688, 0.724785, 0.978733, 1.35558", \ - "0.205496, 0.447268, 0.563611, 0.726962, 0.956099, 1.27086, 1.71403" \ + "0.0355703, 0.100872, 0.144895, 0.217377, 0.338545, 0.540071, 0.875952", \ + "0.0572, 0.13173, 0.176875, 0.24974, 0.370913, 0.572527, 0.908295", \ + "0.0715095, 0.157549, 0.205965, 0.281323, 0.403579, 0.605473, 0.941449", \ + "0.0901799, 0.197078, 0.252959, 0.335855, 0.464406, 0.6693, 1.00581", \ + "0.116329, 0.254186, 0.323472, 0.421373, 0.56617, 0.786325, 1.13065", \ + "0.153869, 0.333889, 0.424079, 0.549692, 0.724792, 0.978742, 1.3556", \ + "0.205498, 0.447271, 0.563616, 0.726968, 0.956107, 1.27087, 1.71405" \ ); } fall_transition (TIMING_DELAY_7x7ds1) { index_1 ("0.0186, 0.0966, 0.174, 0.3294, 0.6408, 1.263, 2.5074"); index_2 ("0.001, 0.0234, 0.039, 0.0648, 0.108, 0.18, 0.3"); values ( \ - "0.0242445, 0.109923, 0.169772, 0.268324, 0.433437, 0.708532, 1.167", \ - "0.0337704, 0.11576, 0.173046, 0.269413, 0.43383, 0.708533, 1.16701", \ - "0.0435955, 0.127067, 0.18281, 0.276377, 0.436718, 0.709281, 1.16702", \ - "0.0617785, 0.152207, 0.207672, 0.298672, 0.453184, 0.718177, 1.16949", \ - "0.0917712, 0.196697, 0.255895, 0.348638, 0.501232, 0.755834, 1.19175", \ - "0.139467, 0.27185, 0.341503, 0.443985, 0.601588, 0.855011, 1.27766", \ - "0.216554, 0.391795, 0.478539, 0.603464, 0.783826, 1.05484, 1.47786" \ + "0.0242576, 0.109916, 0.169775, 0.268329, 0.433444, 0.708543, 1.16702", \ + "0.0337703, 0.115773, 0.173049, 0.269786, 0.435731, 0.708544, 1.16703", \ + "0.0435958, 0.127095, 0.182757, 0.276381, 0.436857, 0.711478, 1.16704", \ + "0.0617791, 0.152208, 0.207674, 0.298676, 0.453233, 0.718318, 1.16951", \ + "0.0917717, 0.196699, 0.256071, 0.348642, 0.501239, 0.755844, 1.19117", \ + "0.139467, 0.271852, 0.341505, 0.443988, 0.601594, 0.855021, 1.27768", \ + "0.216556, 0.391797, 0.478543, 0.603482, 0.783832, 1.05485, 1.47788" \ ); } } @@ -5366,52 +5366,52 @@ library (sg13g2_stdcell_fast_1p32V_m40C) { index_1 ("0.0186, 0.0966, 0.174, 0.3294, 0.6408, 1.263, 2.5074"); index_2 ("0.001, 0.0234, 0.039, 0.0648, 0.108, 0.18, 0.3"); values ( \ - "0.0390751, 0.122461, 0.179501, 0.273164, 0.430385, 0.691586, 1.12718", \ - "0.0631151, 0.156791, 0.214118, 0.307832, 0.465555, 0.726183, 1.1615", \ - "0.0772059, 0.18634, 0.247308, 0.342444, 0.499242, 0.76064, 1.19695", \ - "0.0964641, 0.23195, 0.302854, 0.407482, 0.56943, 0.831183, 1.26623", \ - "0.122384, 0.295496, 0.383464, 0.508935, 0.691618, 0.967331, 1.40573", \ - "0.157834, 0.382056, 0.495997, 0.654124, 0.880212, 1.20079, 1.67459", \ - "0.204379, 0.496421, 0.645503, 0.852007, 1.13833, 1.54234, 2.10893" \ + "0.0390737, 0.122464, 0.179369, 0.27317, 0.430182, 0.691594, 1.12718", \ + "0.0631167, 0.156887, 0.214101, 0.307894, 0.464721, 0.726141, 1.16147", \ + "0.0772064, 0.186343, 0.247308, 0.34244, 0.499211, 0.760628, 1.19692", \ + "0.0964644, 0.231951, 0.302855, 0.407484, 0.569432, 0.831187, 1.26625", \ + "0.122385, 0.295496, 0.383465, 0.508936, 0.69162, 0.967334, 1.40575", \ + "0.157835, 0.382053, 0.495998, 0.654126, 0.880214, 1.2008, 1.67459", \ + "0.20438, 0.496423, 0.645505, 0.85201, 1.13833, 1.54234, 2.10894" \ ); } rise_transition (TIMING_DELAY_7x7ds1) { index_1 ("0.0186, 0.0966, 0.174, 0.3294, 0.6408, 1.263, 2.5074"); index_2 ("0.001, 0.0234, 0.039, 0.0648, 0.108, 0.18, 0.3"); values ( \ - "0.0330899, 0.148938, 0.229661, 0.362709, 0.585145, 0.956136, 1.57421", \ - "0.0474729, 0.155035, 0.231902, 0.363311, 0.585947, 0.956197, 1.57481", \ - "0.0599745, 0.170469, 0.243606, 0.369051, 0.586767, 0.956221, 1.57563", \ - "0.0791492, 0.20529, 0.277759, 0.397275, 0.603545, 0.961879, 1.57564", \ - "0.109715, 0.264201, 0.343416, 0.465556, 0.664716, 1.00298, 1.59252", \ - "0.159145, 0.35721, 0.453198, 0.592906, 0.802014, 1.13539, 1.69063", \ - "0.238854, 0.504086, 0.627343, 0.795501, 1.04287, 1.40501, 1.9669" \ + "0.0330895, 0.148938, 0.229613, 0.362712, 0.585328, 0.95614, 1.57422", \ + "0.0474773, 0.154902, 0.231901, 0.365696, 0.585329, 0.956243, 1.5748", \ + "0.0599745, 0.170467, 0.243635, 0.369073, 0.586636, 0.956244, 1.57563", \ + "0.0791492, 0.205291, 0.27776, 0.397274, 0.603548, 0.961884, 1.57739", \ + "0.109715, 0.264202, 0.343416, 0.465558, 0.664719, 1.00298, 1.59254", \ + "0.159146, 0.357646, 0.453199, 0.592907, 0.802017, 1.13539, 1.69065", \ + "0.238855, 0.504087, 0.627345, 0.795502, 1.04288, 1.40502, 1.96691" \ ); } cell_fall (TIMING_DELAY_7x7ds1) { index_1 ("0.0186, 0.0966, 0.174, 0.3294, 0.6408, 1.263, 2.5074"); index_2 ("0.001, 0.0234, 0.039, 0.0648, 0.108, 0.18, 0.3"); values ( \ - "0.0287905, 0.0937736, 0.137773, 0.210383, 0.331879, 0.533749, 0.869627", \ - "0.0461184, 0.12403, 0.169602, 0.242791, 0.364449, 0.566658, 0.902365", \ - "0.0568682, 0.148761, 0.198097, 0.274144, 0.397039, 0.599375, 0.935331", \ - "0.0696834, 0.186186, 0.243728, 0.327797, 0.45744, 0.663051, 0.999779", \ - "0.0871188, 0.239549, 0.311604, 0.411641, 0.558412, 0.779404, 1.12462", \ - "0.11094, 0.312832, 0.407254, 0.536041, 0.714165, 0.969518, 1.34816", \ - "0.141825, 0.413863, 0.5372, 0.707195, 0.939888, 1.25782, 1.70478" \ + "0.0287952, 0.0937583, 0.137769, 0.21038, 0.331871, 0.533741, 0.869515", \ + "0.046118, 0.124027, 0.169599, 0.242773, 0.364451, 0.56658, 0.902352", \ + "0.0568678, 0.148759, 0.198093, 0.274141, 0.397034, 0.599375, 0.935354", \ + "0.0696827, 0.186184, 0.243725, 0.327793, 0.457438, 0.663045, 0.999746", \ + "0.0871178, 0.239547, 0.311601, 0.411637, 0.558407, 0.779394, 1.1246", \ + "0.110938, 0.312829, 0.40725, 0.536036, 0.714141, 0.969507, 1.34814", \ + "0.141822, 0.413859, 0.537195, 0.706947, 0.939879, 1.2578, 1.70476" \ ); } fall_transition (TIMING_DELAY_7x7ds1) { index_1 ("0.0186, 0.0966, 0.174, 0.3294, 0.6408, 1.263, 2.5074"); index_2 ("0.001, 0.0234, 0.039, 0.0648, 0.108, 0.18, 0.3"); values ( \ - "0.0225427, 0.107117, 0.166568, 0.265085, 0.430028, 0.704697, 1.16363", \ - "0.0342715, 0.113535, 0.170241, 0.26642, 0.430835, 0.704795, 1.16364", \ - "0.0457887, 0.125537, 0.180502, 0.273576, 0.43347, 0.705414, 1.16365", \ - "0.0668815, 0.151264, 0.206098, 0.296399, 0.450387, 0.714706, 1.16515", \ - "0.102294, 0.197169, 0.255579, 0.346809, 0.498576, 0.752664, 1.1879", \ - "0.15766, 0.275282, 0.343111, 0.442971, 0.599354, 0.851919, 1.27339", \ - "0.247128, 0.403695, 0.486236, 0.607782, 0.785997, 1.05162, 1.4752" \ + "0.0225357, 0.107102, 0.166543, 0.26508, 0.430021, 0.704684, 1.1624", \ + "0.0342711, 0.113539, 0.170238, 0.266417, 0.4304, 0.704685, 1.1629", \ + "0.0457883, 0.125535, 0.180503, 0.273572, 0.43347, 0.705391, 1.16291", \ + "0.0668809, 0.151262, 0.206095, 0.296394, 0.450301, 0.714703, 1.16511", \ + "0.102293, 0.197169, 0.255567, 0.346806, 0.498569, 0.752652, 1.1881", \ + "0.157659, 0.275279, 0.34311, 0.442967, 0.599633, 0.851908, 1.27338", \ + "0.247127, 0.403691, 0.486233, 0.607701, 0.78599, 1.05161, 1.47517" \ ); } } @@ -5425,52 +5425,52 @@ library (sg13g2_stdcell_fast_1p32V_m40C) { index_1 ("0.0186, 0.0966, 0.174, 0.3294, 0.6408, 1.263, 2.5074"); index_2 ("0.001, 0.0234, 0.039, 0.0648, 0.108, 0.18, 0.3"); values ( \ - "0.0329437, 0.115801, 0.172399, 0.265681, 0.421988, 0.681754, 1.11497", \ - "0.054106, 0.150069, 0.207039, 0.300369, 0.456595, 0.71721, 1.15025", \ - "0.0660403, 0.178757, 0.239998, 0.334879, 0.490878, 0.751013, 1.18457", \ - "0.0822149, 0.222884, 0.294538, 0.39947, 0.561055, 0.821611, 1.25441", \ - "0.103773, 0.284203, 0.373236, 0.499649, 0.682495, 0.957505, 1.39393", \ - "0.133309, 0.366999, 0.483039, 0.642194, 0.869096, 1.18981, 1.66262", \ - "0.171893, 0.477505, 0.627678, 0.837491, 1.12456, 1.52852, 2.09469" \ + "0.0329389, 0.1158, 0.17252, 0.265685, 0.421986, 0.681972, 1.11496", \ + "0.0541058, 0.150048, 0.207024, 0.300312, 0.456657, 0.717228, 1.15025", \ + "0.0660482, 0.178829, 0.24002, 0.334878, 0.490901, 0.751059, 1.1846", \ + "0.0822147, 0.222883, 0.294538, 0.399425, 0.561053, 0.821607, 1.25439", \ + "0.103773, 0.284203, 0.373235, 0.499647, 0.682492, 0.957501, 1.39392", \ + "0.133309, 0.366998, 0.482869, 0.642199, 0.869061, 1.18981, 1.66262", \ + "0.171893, 0.477502, 0.627677, 0.837455, 1.12456, 1.52852, 2.09469" \ ); } rise_transition (TIMING_DELAY_7x7ds1) { index_1 ("0.0186, 0.0966, 0.174, 0.3294, 0.6408, 1.263, 2.5074"); index_2 ("0.001, 0.0234, 0.039, 0.0648, 0.108, 0.18, 0.3"); values ( \ - "0.0278787, 0.142574, 0.222613, 0.355062, 0.576488, 0.945609, 1.56068", \ - "0.0426016, 0.149036, 0.225367, 0.355498, 0.576489, 0.945767, 1.56069", \ - "0.0542252, 0.165162, 0.237512, 0.361799, 0.57817, 0.945768, 1.5607", \ - "0.0723922, 0.19992, 0.272294, 0.390636, 0.595418, 0.951426, 1.56248", \ - "0.101083, 0.257957, 0.338294, 0.459356, 0.657096, 0.993081, 1.57908", \ - "0.147216, 0.350798, 0.446925, 0.58657, 0.794851, 1.1256, 1.67792", \ - "0.224111, 0.495089, 0.6184, 0.787939, 1.03625, 1.39424, 1.95346" \ + "0.0278761, 0.142576, 0.222776, 0.355059, 0.576485, 0.945273, 1.56068", \ + "0.0426015, 0.149013, 0.225287, 0.357316, 0.576486, 0.945763, 1.56069", \ + "0.0542118, 0.165116, 0.237509, 0.361751, 0.578167, 0.945764, 1.5607", \ + "0.0723923, 0.199921, 0.272293, 0.390581, 0.595415, 0.951415, 1.56219", \ + "0.101082, 0.257956, 0.338294, 0.459353, 0.657093, 0.99308, 1.57907", \ + "0.147213, 0.350797, 0.446713, 0.586287, 0.794816, 1.1256, 1.67791", \ + "0.22411, 0.495087, 0.61841, 0.787921, 1.03625, 1.39423, 1.95345" \ ); } cell_fall (TIMING_DELAY_7x7ds1) { index_1 ("0.0186, 0.0966, 0.174, 0.3294, 0.6408, 1.263, 2.5074"); index_2 ("0.001, 0.0234, 0.039, 0.0648, 0.108, 0.18, 0.3"); values ( \ - "0.028384, 0.0929571, 0.136718, 0.208993, 0.329855, 0.531219, 0.867079", \ - "0.045358, 0.123118, 0.168531, 0.241359, 0.362451, 0.563991, 0.900028", \ - "0.0557161, 0.147704, 0.196851, 0.272642, 0.395021, 0.596898, 0.932898", \ - "0.0677696, 0.184786, 0.242222, 0.326067, 0.455392, 0.660521, 0.997135", \ - "0.083361, 0.237273, 0.30948, 0.40941, 0.555873, 0.776682, 1.12192", \ - "0.103439, 0.308953, 0.403836, 0.533189, 0.711224, 0.967404, 1.34551", \ - "0.125336, 0.406979, 0.531448, 0.701625, 0.93591, 1.2543, 1.70178" \ + "0.0283743, 0.0929501, 0.136707, 0.209006, 0.329846, 0.531408, 0.867067", \ + "0.0453575, 0.123172, 0.16853, 0.24135, 0.362475, 0.563989, 0.900011", \ + "0.0557153, 0.147703, 0.196848, 0.272638, 0.395015, 0.596862, 0.932879", \ + "0.067769, 0.184784, 0.24222, 0.326064, 0.455386, 0.660497, 0.997141", \ + "0.0833603, 0.237271, 0.309479, 0.409406, 0.555867, 0.77668, 1.12191", \ + "0.103438, 0.30895, 0.403832, 0.533184, 0.711217, 0.967393, 1.34549", \ + "0.125334, 0.406976, 0.531443, 0.701624, 0.935901, 1.25423, 1.7016" \ ); } fall_transition (TIMING_DELAY_7x7ds1) { index_1 ("0.0186, 0.0966, 0.174, 0.3294, 0.6408, 1.263, 2.5074"); index_2 ("0.001, 0.0234, 0.039, 0.0648, 0.108, 0.18, 0.3"); values ( \ - "0.0159307, 0.100858, 0.160257, 0.258825, 0.423859, 0.698713, 1.15673", \ - "0.0259492, 0.107161, 0.163925, 0.260031, 0.425346, 0.698714, 1.15682", \ - "0.0359096, 0.118993, 0.17412, 0.267247, 0.427265, 0.700897, 1.15683", \ - "0.0540747, 0.144059, 0.19949, 0.28999, 0.44424, 0.708461, 1.15945", \ - "0.084736, 0.189016, 0.24792, 0.340091, 0.49197, 0.746527, 1.18168", \ - "0.132456, 0.264504, 0.335548, 0.436105, 0.593344, 0.84627, 1.26844", \ - "0.211825, 0.388351, 0.475383, 0.596252, 0.781813, 1.0443, 1.46939" \ + "0.0159327, 0.100852, 0.160254, 0.258831, 0.42385, 0.698682, 1.15671", \ + "0.0259489, 0.107129, 0.163922, 0.260019, 0.425161, 0.698683, 1.15679", \ + "0.0359085, 0.118992, 0.174101, 0.267242, 0.427249, 0.701194, 1.1568", \ + "0.0540743, 0.144057, 0.199487, 0.289986, 0.444233, 0.708395, 1.15953", \ + "0.0847355, 0.189014, 0.247919, 0.340088, 0.491965, 0.746525, 1.18215", \ + "0.132456, 0.264503, 0.335545, 0.436101, 0.593338, 0.846278, 1.26842", \ + "0.211824, 0.388349, 0.475379, 0.596184, 0.781805, 1.04406, 1.46903" \ ); } } @@ -5482,52 +5482,52 @@ library (sg13g2_stdcell_fast_1p32V_m40C) { index_1 ("0.0186, 0.0966, 0.174, 0.3294, 0.6408, 1.263, 2.5074"); index_2 ("0.001, 0.0234, 0.039, 0.0648, 0.108, 0.18, 0.3"); values ( \ - "0.0390751, 0.122461, 0.179501, 0.273164, 0.430385, 0.691586, 1.12718", \ - "0.0631151, 0.156791, 0.214118, 0.307832, 0.465555, 0.726183, 1.1615", \ - "0.0772059, 0.18634, 0.247308, 0.342444, 0.499242, 0.76064, 1.19695", \ - "0.0964641, 0.23195, 0.302854, 0.407482, 0.56943, 0.831183, 1.26623", \ - "0.122384, 0.295496, 0.383464, 0.508935, 0.691618, 0.967331, 1.40573", \ - "0.157834, 0.382056, 0.495997, 0.654124, 0.880212, 1.20079, 1.67459", \ - "0.204379, 0.496421, 0.645503, 0.852007, 1.13833, 1.54234, 2.10893" \ + "0.0390737, 0.122464, 0.179369, 0.27317, 0.430182, 0.691594, 1.12718", \ + "0.0631167, 0.156887, 0.214101, 0.307894, 0.464721, 0.726141, 1.16147", \ + "0.0772064, 0.186343, 0.247308, 0.34244, 0.499211, 0.760628, 1.19692", \ + "0.0964644, 0.231951, 0.302855, 0.407484, 0.569432, 0.831187, 1.26625", \ + "0.122385, 0.295496, 0.383465, 0.508936, 0.69162, 0.967334, 1.40575", \ + "0.157835, 0.382053, 0.495998, 0.654126, 0.880214, 1.2008, 1.67459", \ + "0.20438, 0.496423, 0.645505, 0.85201, 1.13833, 1.54234, 2.10894" \ ); } rise_transition (TIMING_DELAY_7x7ds1) { index_1 ("0.0186, 0.0966, 0.174, 0.3294, 0.6408, 1.263, 2.5074"); index_2 ("0.001, 0.0234, 0.039, 0.0648, 0.108, 0.18, 0.3"); values ( \ - "0.0330899, 0.148938, 0.229661, 0.362709, 0.585145, 0.956136, 1.57421", \ - "0.0474729, 0.155035, 0.231902, 0.363311, 0.585947, 0.956197, 1.57481", \ - "0.0599745, 0.170469, 0.243606, 0.369051, 0.586767, 0.956221, 1.57563", \ - "0.0791492, 0.20529, 0.277759, 0.397275, 0.603545, 0.961879, 1.57564", \ - "0.109715, 0.264201, 0.343416, 0.465556, 0.664716, 1.00298, 1.59252", \ - "0.159145, 0.35721, 0.453198, 0.592906, 0.802014, 1.13539, 1.69063", \ - "0.238854, 0.504086, 0.627343, 0.795501, 1.04287, 1.40501, 1.9669" \ + "0.0330895, 0.148938, 0.229613, 0.362712, 0.585328, 0.95614, 1.57422", \ + "0.0474773, 0.154902, 0.231901, 0.365696, 0.585329, 0.956243, 1.5748", \ + "0.0599745, 0.170467, 0.243635, 0.369073, 0.586636, 0.956244, 1.57563", \ + "0.0791492, 0.205291, 0.27776, 0.397274, 0.603548, 0.961884, 1.57739", \ + "0.109715, 0.264202, 0.343416, 0.465558, 0.664719, 1.00298, 1.59254", \ + "0.159146, 0.357646, 0.453199, 0.592907, 0.802017, 1.13539, 1.69065", \ + "0.238855, 0.504087, 0.627345, 0.795502, 1.04288, 1.40502, 1.96691" \ ); } cell_fall (TIMING_DELAY_7x7ds1) { index_1 ("0.0186, 0.0966, 0.174, 0.3294, 0.6408, 1.263, 2.5074"); index_2 ("0.001, 0.0234, 0.039, 0.0648, 0.108, 0.18, 0.3"); values ( \ - "0.0287905, 0.0937736, 0.137773, 0.210383, 0.331879, 0.533749, 0.869627", \ - "0.0461184, 0.12403, 0.169602, 0.242791, 0.364449, 0.566658, 0.902365", \ - "0.0568682, 0.148761, 0.198097, 0.274144, 0.397039, 0.599375, 0.935331", \ - "0.0696834, 0.186186, 0.243728, 0.327797, 0.45744, 0.663051, 0.999779", \ - "0.0871188, 0.239549, 0.311604, 0.411641, 0.558412, 0.779404, 1.12462", \ - "0.11094, 0.312832, 0.407254, 0.536041, 0.714165, 0.969518, 1.34816", \ - "0.141825, 0.413863, 0.5372, 0.707195, 0.939888, 1.25782, 1.70478" \ + "0.0287952, 0.0937583, 0.137769, 0.21038, 0.331871, 0.533741, 0.869515", \ + "0.046118, 0.124027, 0.169599, 0.242773, 0.364451, 0.56658, 0.902352", \ + "0.0568678, 0.148759, 0.198093, 0.274141, 0.397034, 0.599375, 0.935354", \ + "0.0696827, 0.186184, 0.243725, 0.327793, 0.457438, 0.663045, 0.999746", \ + "0.0871178, 0.239547, 0.311601, 0.411637, 0.558407, 0.779394, 1.1246", \ + "0.110938, 0.312829, 0.40725, 0.536036, 0.714141, 0.969507, 1.34814", \ + "0.141822, 0.413859, 0.537195, 0.706947, 0.939879, 1.2578, 1.70476" \ ); } fall_transition (TIMING_DELAY_7x7ds1) { index_1 ("0.0186, 0.0966, 0.174, 0.3294, 0.6408, 1.263, 2.5074"); index_2 ("0.001, 0.0234, 0.039, 0.0648, 0.108, 0.18, 0.3"); values ( \ - "0.0225427, 0.107117, 0.166568, 0.265085, 0.430028, 0.704697, 1.16363", \ - "0.0342715, 0.113535, 0.170241, 0.26642, 0.430835, 0.704795, 1.16364", \ - "0.0457887, 0.125537, 0.180502, 0.273576, 0.43347, 0.705414, 1.16365", \ - "0.0668815, 0.151264, 0.206098, 0.296399, 0.450387, 0.714706, 1.16515", \ - "0.102294, 0.197169, 0.255579, 0.346809, 0.498576, 0.752664, 1.1879", \ - "0.15766, 0.275282, 0.343111, 0.442971, 0.599354, 0.851919, 1.27339", \ - "0.247128, 0.403695, 0.486236, 0.607782, 0.785997, 1.05162, 1.4752" \ + "0.0225357, 0.107102, 0.166543, 0.26508, 0.430021, 0.704684, 1.1624", \ + "0.0342711, 0.113539, 0.170238, 0.266417, 0.4304, 0.704685, 1.1629", \ + "0.0457883, 0.125535, 0.180503, 0.273572, 0.43347, 0.705391, 1.16291", \ + "0.0668809, 0.151262, 0.206095, 0.296394, 0.450301, 0.714703, 1.16511", \ + "0.102293, 0.197169, 0.255567, 0.346806, 0.498569, 0.752652, 1.1881", \ + "0.157659, 0.275279, 0.34311, 0.442967, 0.599633, 0.851908, 1.27338", \ + "0.247127, 0.403691, 0.486233, 0.607701, 0.78599, 1.05161, 1.47517" \ ); } } @@ -5541,52 +5541,52 @@ library (sg13g2_stdcell_fast_1p32V_m40C) { index_1 ("0.0186, 0.0966, 0.174, 0.3294, 0.6408, 1.263, 2.5074"); index_2 ("0.001, 0.0234, 0.039, 0.0648, 0.108, 0.18, 0.3"); values ( \ - "0.0336137, 0.117261, 0.174004, 0.267226, 0.423531, 0.683621, 1.11708", \ - "0.054479, 0.150916, 0.208245, 0.301579, 0.458002, 0.718787, 1.15162", \ - "0.0661447, 0.179563, 0.240936, 0.336118, 0.492303, 0.752313, 1.1864", \ - "0.0816472, 0.22323, 0.295139, 0.40027, 0.562095, 0.822794, 1.25597", \ - "0.101555, 0.283362, 0.373292, 0.499969, 0.68313, 0.958421, 1.39517", \ - "0.126644, 0.364276, 0.480231, 0.641334, 0.868845, 1.19009, 1.66301", \ - "0.154769, 0.466875, 0.620734, 0.832004, 1.1227, 1.52766, 2.09467" \ + "0.0336094, 0.117261, 0.174009, 0.267227, 0.423483, 0.683626, 1.11709", \ + "0.0544797, 0.150922, 0.208245, 0.301652, 0.458113, 0.718786, 1.1516", \ + "0.0661449, 0.179564, 0.240949, 0.336088, 0.492322, 0.752678, 1.18714", \ + "0.0816192, 0.223231, 0.29514, 0.400272, 0.562064, 0.822833, 1.25595", \ + "0.101556, 0.283363, 0.373293, 0.499971, 0.683132, 0.958425, 1.39518", \ + "0.126645, 0.364278, 0.480232, 0.641336, 0.868869, 1.1901, 1.66302", \ + "0.154771, 0.466877, 0.620737, 0.832007, 1.12269, 1.52766, 2.09468" \ ); } rise_transition (TIMING_DELAY_7x7ds1) { index_1 ("0.0186, 0.0966, 0.174, 0.3294, 0.6408, 1.263, 2.5074"); index_2 ("0.001, 0.0234, 0.039, 0.0648, 0.108, 0.18, 0.3"); values ( \ - "0.0275476, 0.142422, 0.222434, 0.35479, 0.576268, 0.945092, 1.55997", \ - "0.0422043, 0.148638, 0.224875, 0.355782, 0.576269, 0.945356, 1.56004", \ - "0.0538721, 0.164572, 0.237046, 0.361496, 0.57771, 0.945357, 1.5603", \ - "0.0726765, 0.199635, 0.27177, 0.390113, 0.595172, 0.950847, 1.56162", \ - "0.103479, 0.25782, 0.337972, 0.458558, 0.656558, 0.992604, 1.5787", \ - "0.153557, 0.352345, 0.44824, 0.586494, 0.79393, 1.12523, 1.67741", \ - "0.237129, 0.501301, 0.62427, 0.790565, 1.03852, 1.39509, 1.95456" \ + "0.0275504, 0.142423, 0.222435, 0.354792, 0.576097, 0.945098, 1.55998", \ + "0.0422042, 0.148643, 0.224876, 0.355076, 0.576098, 0.945375, 1.55999", \ + "0.0538723, 0.164573, 0.237058, 0.361369, 0.577734, 0.945472, 1.56175", \ + "0.0729932, 0.199636, 0.27177, 0.390114, 0.594919, 0.951, 1.56176", \ + "0.103479, 0.257821, 0.337974, 0.45856, 0.656561, 0.992598, 1.57871", \ + "0.153558, 0.352347, 0.448241, 0.586494, 0.794178, 1.12524, 1.67713", \ + "0.237129, 0.501303, 0.62427, 0.790566, 1.03852, 1.3951, 1.95457" \ ); } cell_fall (TIMING_DELAY_7x7ds1) { index_1 ("0.0186, 0.0966, 0.174, 0.3294, 0.6408, 1.263, 2.5074"); index_2 ("0.001, 0.0234, 0.039, 0.0648, 0.108, 0.18, 0.3"); values ( \ - "0.0259446, 0.0914912, 0.135555, 0.208166, 0.329597, 0.531535, 0.867408", \ - "0.044056, 0.128743, 0.174693, 0.247849, 0.369377, 0.571427, 0.907134", \ - "0.0554312, 0.158245, 0.209861, 0.287148, 0.41019, 0.612123, 0.947939", \ - "0.0700928, 0.201046, 0.264154, 0.353378, 0.486125, 0.692416, 1.02846", \ - "0.0904467, 0.259549, 0.340693, 0.451419, 0.608541, 0.837759, 1.18509", \ - "0.119355, 0.339534, 0.445651, 0.590229, 0.78846, 1.06528, 1.46344", \ - "0.161119, 0.449833, 0.585662, 0.775652, 1.03734, 1.39229, 1.88499" \ + "0.0259409, 0.0914936, 0.135557, 0.20815, 0.32959, 0.531521, 0.867395", \ + "0.0440557, 0.128741, 0.174693, 0.247846, 0.369327, 0.571338, 0.907106", \ + "0.0554308, 0.158244, 0.209859, 0.287142, 0.410177, 0.612113, 0.947846", \ + "0.0700924, 0.201044, 0.264151, 0.353375, 0.486114, 0.692407, 1.02845", \ + "0.0904241, 0.259547, 0.34069, 0.451415, 0.608534, 0.837751, 1.18507", \ + "0.119354, 0.33973, 0.445648, 0.590225, 0.788454, 1.06527, 1.46343", \ + "0.161116, 0.449829, 0.585706, 0.775646, 1.03733, 1.39238, 1.88497" \ ); } fall_transition (TIMING_DELAY_7x7ds1) { index_1 ("0.0186, 0.0966, 0.174, 0.3294, 0.6408, 1.263, 2.5074"); index_2 ("0.001, 0.0234, 0.039, 0.0648, 0.108, 0.18, 0.3"); values ( \ - "0.0233643, 0.107073, 0.166584, 0.264992, 0.429812, 0.70467, 1.16251", \ - "0.040709, 0.117591, 0.172424, 0.266997, 0.432985, 0.704671, 1.16265", \ - "0.054315, 0.135513, 0.188596, 0.27852, 0.435577, 0.708131, 1.16266", \ - "0.0764775, 0.170676, 0.225413, 0.313635, 0.461959, 0.720106, 1.16641", \ - "0.112584, 0.227444, 0.290533, 0.384152, 0.53358, 0.778734, 1.20172", \ - "0.171722, 0.318387, 0.395172, 0.507757, 0.669839, 0.923326, 1.33172", \ - "0.271131, 0.460812, 0.561345, 0.702097, 0.899668, 1.18888, 1.61798" \ + "0.0233652, 0.107071, 0.166583, 0.264977, 0.429804, 0.704658, 1.16249", \ + "0.0407086, 0.117589, 0.172408, 0.267011, 0.432909, 0.704659, 1.16255", \ + "0.0543147, 0.135512, 0.188613, 0.278513, 0.435591, 0.708105, 1.1635", \ + "0.0764772, 0.170674, 0.225411, 0.313631, 0.461961, 0.720092, 1.16639", \ + "0.112585, 0.227443, 0.290526, 0.384116, 0.533563, 0.778728, 1.2017", \ + "0.171722, 0.318169, 0.395228, 0.507754, 0.669832, 0.923315, 1.33174", \ + "0.27113, 0.46081, 0.56127, 0.702097, 0.899662, 1.18824, 1.61796" \ ); } } @@ -5600,52 +5600,52 @@ library (sg13g2_stdcell_fast_1p32V_m40C) { index_1 ("0.0186, 0.0966, 0.174, 0.3294, 0.6408, 1.263, 2.5074"); index_2 ("0.001, 0.0234, 0.039, 0.0648, 0.108, 0.18, 0.3"); values ( \ - "0.027582, 0.111632, 0.168532, 0.26223, 0.419324, 0.68058, 1.11612", \ - "0.0448121, 0.145133, 0.20284, 0.296658, 0.453707, 0.715629, 1.15061", \ - "0.0543819, 0.173097, 0.235248, 0.331075, 0.488048, 0.74959, 1.1861", \ - "0.0665057, 0.215363, 0.288607, 0.394827, 0.557685, 0.819795, 1.25487", \ - "0.0816296, 0.27345, 0.365194, 0.49368, 0.678285, 0.955245, 1.39415", \ - "0.100194, 0.351213, 0.470378, 0.633122, 0.86288, 1.18644, 1.66217", \ - "0.120101, 0.449922, 0.607044, 0.820948, 1.11424, 1.52276, 2.09304" \ + "0.0275822, 0.111625, 0.168539, 0.262224, 0.419325, 0.680368, 1.11612", \ + "0.0448101, 0.145129, 0.202839, 0.29664, 0.453823, 0.715624, 1.15058", \ + "0.0543817, 0.173096, 0.23527, 0.331074, 0.487983, 0.749576, 1.18609", \ + "0.0665056, 0.215363, 0.288606, 0.394821, 0.557682, 0.81978, 1.25505", \ + "0.0816295, 0.27345, 0.365194, 0.493678, 0.678283, 0.955242, 1.39415", \ + "0.100194, 0.351213, 0.470377, 0.633121, 0.862741, 1.18644, 1.66217", \ + "0.120101, 0.449922, 0.607043, 0.820946, 1.11424, 1.52275, 2.09304" \ ); } rise_transition (TIMING_DELAY_7x7ds1) { index_1 ("0.0186, 0.0966, 0.174, 0.3294, 0.6408, 1.263, 2.5074"); index_2 ("0.001, 0.0234, 0.039, 0.0648, 0.108, 0.18, 0.3"); values ( \ - "0.0226983, 0.137604, 0.217717, 0.350548, 0.572969, 0.943775, 1.56185", \ - "0.0377245, 0.144249, 0.220565, 0.351162, 0.57297, 0.944138, 1.56186", \ - "0.0486119, 0.160536, 0.232973, 0.357587, 0.574592, 0.944139, 1.5625", \ - "0.0666367, 0.196213, 0.268169, 0.386858, 0.592265, 0.94993, 1.56957", \ - "0.0954899, 0.253781, 0.334682, 0.456051, 0.654447, 0.991848, 1.58066", \ - "0.143455, 0.348586, 0.443583, 0.583237, 0.792188, 1.12494, 1.67935", \ - "0.225192, 0.496669, 0.621686, 0.78858, 1.03366, 1.39518, 1.95614" \ + "0.0226977, 0.137405, 0.217909, 0.350699, 0.572965, 0.943771, 1.56184", \ + "0.0377312, 0.144235, 0.220563, 0.352801, 0.573142, 0.944133, 1.56185", \ + "0.0486117, 0.160525, 0.23301, 0.357619, 0.574762, 0.944964, 1.5625", \ + "0.0666366, 0.196212, 0.268168, 0.386758, 0.592271, 0.949872, 1.56325", \ + "0.0954897, 0.25378, 0.334681, 0.45605, 0.654421, 0.991843, 1.58066", \ + "0.143455, 0.348585, 0.443581, 0.583235, 0.792312, 1.12494, 1.67934", \ + "0.225192, 0.496668, 0.621684, 0.788578, 1.03365, 1.39518, 1.95613" \ ); } cell_fall (TIMING_DELAY_7x7ds1) { index_1 ("0.0186, 0.0966, 0.174, 0.3294, 0.6408, 1.263, 2.5074"); index_2 ("0.001, 0.0234, 0.039, 0.0648, 0.108, 0.18, 0.3"); values ( \ - "0.0255086, 0.0906629, 0.13452, 0.206783, 0.327662, 0.529098, 0.865125", \ - "0.0430595, 0.127806, 0.173668, 0.246528, 0.367323, 0.56879, 0.904626", \ - "0.0538971, 0.157127, 0.208612, 0.285642, 0.408168, 0.609699, 0.945408", \ - "0.067526, 0.199297, 0.262356, 0.351518, 0.484019, 0.689861, 1.02596", \ - "0.0856826, 0.256526, 0.337973, 0.448703, 0.605851, 0.835166, 1.18243", \ - "0.109255, 0.334337, 0.440925, 0.586294, 0.784626, 1.06206, 1.46073", \ - "0.138163, 0.44065, 0.578056, 0.76898, 1.03269, 1.38767, 1.88221" \ + "0.0255083, 0.0906731, 0.134515, 0.20678, 0.327657, 0.529099, 0.865111", \ + "0.0430592, 0.127817, 0.173665, 0.246473, 0.367326, 0.568912, 0.904617", \ + "0.0538968, 0.157126, 0.208609, 0.285637, 0.408169, 0.609766, 0.945412", \ + "0.0675256, 0.199295, 0.262354, 0.351512, 0.484013, 0.689836, 1.02594", \ + "0.0856819, 0.256523, 0.338019, 0.4487, 0.605841, 0.835127, 1.18244", \ + "0.109254, 0.334569, 0.440918, 0.58629, 0.784619, 1.06205, 1.46069", \ + "0.138161, 0.440646, 0.577864, 0.768974, 1.03268, 1.38768, 1.88219" \ ); } fall_transition (TIMING_DELAY_7x7ds1) { index_1 ("0.0186, 0.0966, 0.174, 0.3294, 0.6408, 1.263, 2.5074"); index_2 ("0.001, 0.0234, 0.039, 0.0648, 0.108, 0.18, 0.3"); values ( \ - "0.0167021, 0.10073, 0.160293, 0.258824, 0.4238, 0.698734, 1.1569", \ - "0.0310317, 0.111234, 0.166118, 0.260793, 0.424881, 0.698735, 1.15691", \ - "0.0421922, 0.128769, 0.182267, 0.272322, 0.429465, 0.700221, 1.15692", \ - "0.0605541, 0.162878, 0.218189, 0.307178, 0.4558, 0.713812, 1.16099", \ - "0.0907628, 0.21827, 0.282472, 0.377397, 0.527406, 0.772748, 1.19525", \ - "0.141071, 0.305716, 0.384697, 0.498225, 0.663692, 0.917821, 1.32568", \ - "0.227564, 0.443038, 0.547538, 0.69219, 0.891296, 1.18116, 1.61261" \ + "0.0167018, 0.100744, 0.160291, 0.25882, 0.423793, 0.698721, 1.15688", \ + "0.0310314, 0.11121, 0.166116, 0.260732, 0.424874, 0.698722, 1.15689", \ + "0.0421919, 0.128767, 0.182263, 0.272321, 0.429388, 0.700354, 1.1569", \ + "0.0605539, 0.162877, 0.218187, 0.307172, 0.455727, 0.713732, 1.16096", \ + "0.0907624, 0.218268, 0.282449, 0.377393, 0.527393, 0.77255, 1.19526", \ + "0.141071, 0.305462, 0.385309, 0.498221, 0.663685, 0.91781, 1.32567", \ + "0.227563, 0.443036, 0.547176, 0.692183, 0.891289, 1.18114, 1.61259" \ ); } } @@ -5657,52 +5657,52 @@ library (sg13g2_stdcell_fast_1p32V_m40C) { index_1 ("0.0186, 0.0966, 0.174, 0.3294, 0.6408, 1.263, 2.5074"); index_2 ("0.001, 0.0234, 0.039, 0.0648, 0.108, 0.18, 0.3"); values ( \ - "0.0336137, 0.117261, 0.174004, 0.267226, 0.423531, 0.683621, 1.11708", \ - "0.054479, 0.150916, 0.208245, 0.301579, 0.458002, 0.718787, 1.15162", \ - "0.0661447, 0.179563, 0.240936, 0.336118, 0.492303, 0.752313, 1.1864", \ - "0.0816472, 0.22323, 0.295139, 0.40027, 0.562095, 0.822794, 1.25597", \ - "0.101555, 0.283362, 0.373292, 0.499969, 0.68313, 0.958421, 1.39517", \ - "0.126644, 0.364276, 0.480231, 0.641334, 0.868845, 1.19009, 1.66301", \ - "0.154769, 0.466875, 0.620734, 0.832004, 1.1227, 1.52766, 2.09467" \ + "0.0336094, 0.117261, 0.174009, 0.267227, 0.423483, 0.683626, 1.11709", \ + "0.0544797, 0.150922, 0.208245, 0.301652, 0.458113, 0.718786, 1.1516", \ + "0.0661449, 0.179564, 0.240949, 0.336088, 0.492322, 0.752678, 1.18714", \ + "0.0816192, 0.223231, 0.29514, 0.400272, 0.562064, 0.822833, 1.25595", \ + "0.101556, 0.283363, 0.373293, 0.499971, 0.683132, 0.958425, 1.39518", \ + "0.126645, 0.364278, 0.480232, 0.641336, 0.868869, 1.1901, 1.66302", \ + "0.154771, 0.466877, 0.620737, 0.832007, 1.12269, 1.52766, 2.09468" \ ); } rise_transition (TIMING_DELAY_7x7ds1) { index_1 ("0.0186, 0.0966, 0.174, 0.3294, 0.6408, 1.263, 2.5074"); index_2 ("0.001, 0.0234, 0.039, 0.0648, 0.108, 0.18, 0.3"); values ( \ - "0.0275476, 0.142422, 0.222434, 0.35479, 0.576268, 0.945092, 1.55997", \ - "0.0422043, 0.148638, 0.224875, 0.355782, 0.576269, 0.945356, 1.56004", \ - "0.0538721, 0.164572, 0.237046, 0.361496, 0.57771, 0.945357, 1.5603", \ - "0.0726765, 0.199635, 0.27177, 0.390113, 0.595172, 0.950847, 1.56162", \ - "0.103479, 0.25782, 0.337972, 0.458558, 0.656558, 0.992604, 1.5787", \ - "0.153557, 0.352345, 0.44824, 0.586494, 0.79393, 1.12523, 1.67741", \ - "0.237129, 0.501301, 0.62427, 0.790565, 1.03852, 1.39509, 1.95456" \ + "0.0275504, 0.142423, 0.222435, 0.354792, 0.576097, 0.945098, 1.55998", \ + "0.0422042, 0.148643, 0.224876, 0.355076, 0.576098, 0.945375, 1.55999", \ + "0.0538723, 0.164573, 0.237058, 0.361369, 0.577734, 0.945472, 1.56175", \ + "0.0729932, 0.199636, 0.27177, 0.390114, 0.594919, 0.951, 1.56176", \ + "0.103479, 0.257821, 0.337974, 0.45856, 0.656561, 0.992598, 1.57871", \ + "0.153558, 0.352347, 0.448241, 0.586494, 0.794178, 1.12524, 1.67713", \ + "0.237129, 0.501303, 0.62427, 0.790566, 1.03852, 1.3951, 1.95457" \ ); } cell_fall (TIMING_DELAY_7x7ds1) { index_1 ("0.0186, 0.0966, 0.174, 0.3294, 0.6408, 1.263, 2.5074"); index_2 ("0.001, 0.0234, 0.039, 0.0648, 0.108, 0.18, 0.3"); values ( \ - "0.0259446, 0.0914912, 0.135555, 0.208166, 0.329597, 0.531535, 0.867408", \ - "0.044056, 0.128743, 0.174693, 0.247849, 0.369377, 0.571427, 0.907134", \ - "0.0554312, 0.158245, 0.209861, 0.287148, 0.41019, 0.612123, 0.947939", \ - "0.0700928, 0.201046, 0.264154, 0.353378, 0.486125, 0.692416, 1.02846", \ - "0.0904467, 0.259549, 0.340693, 0.451419, 0.608541, 0.837759, 1.18509", \ - "0.119355, 0.339534, 0.445651, 0.590229, 0.78846, 1.06528, 1.46344", \ - "0.161119, 0.449833, 0.585662, 0.775652, 1.03734, 1.39229, 1.88499" \ + "0.0259409, 0.0914936, 0.135557, 0.20815, 0.32959, 0.531521, 0.867395", \ + "0.0440557, 0.128741, 0.174693, 0.247846, 0.369327, 0.571338, 0.907106", \ + "0.0554308, 0.158244, 0.209859, 0.287142, 0.410177, 0.612113, 0.947846", \ + "0.0700924, 0.201044, 0.264151, 0.353375, 0.486114, 0.692407, 1.02845", \ + "0.0904241, 0.259547, 0.34069, 0.451415, 0.608534, 0.837751, 1.18507", \ + "0.119354, 0.33973, 0.445648, 0.590225, 0.788454, 1.06527, 1.46343", \ + "0.161116, 0.449829, 0.585706, 0.775646, 1.03733, 1.39238, 1.88497" \ ); } fall_transition (TIMING_DELAY_7x7ds1) { index_1 ("0.0186, 0.0966, 0.174, 0.3294, 0.6408, 1.263, 2.5074"); index_2 ("0.001, 0.0234, 0.039, 0.0648, 0.108, 0.18, 0.3"); values ( \ - "0.0233643, 0.107073, 0.166584, 0.264992, 0.429812, 0.70467, 1.16251", \ - "0.040709, 0.117591, 0.172424, 0.266997, 0.432985, 0.704671, 1.16265", \ - "0.054315, 0.135513, 0.188596, 0.27852, 0.435577, 0.708131, 1.16266", \ - "0.0764775, 0.170676, 0.225413, 0.313635, 0.461959, 0.720106, 1.16641", \ - "0.112584, 0.227444, 0.290533, 0.384152, 0.53358, 0.778734, 1.20172", \ - "0.171722, 0.318387, 0.395172, 0.507757, 0.669839, 0.923326, 1.33172", \ - "0.271131, 0.460812, 0.561345, 0.702097, 0.899668, 1.18888, 1.61798" \ + "0.0233652, 0.107071, 0.166583, 0.264977, 0.429804, 0.704658, 1.16249", \ + "0.0407086, 0.117589, 0.172408, 0.267011, 0.432909, 0.704659, 1.16255", \ + "0.0543147, 0.135512, 0.188613, 0.278513, 0.435591, 0.708105, 1.1635", \ + "0.0764772, 0.170674, 0.225411, 0.313631, 0.461961, 0.720092, 1.16639", \ + "0.112585, 0.227443, 0.290526, 0.384116, 0.533563, 0.778728, 1.2017", \ + "0.171722, 0.318169, 0.395228, 0.507754, 0.669832, 0.923315, 1.33174", \ + "0.27113, 0.46081, 0.56127, 0.702097, 0.899662, 1.18824, 1.61796" \ ); } } @@ -5713,26 +5713,26 @@ library (sg13g2_stdcell_fast_1p32V_m40C) { index_1 ("0.0186, 0.0966, 0.174, 0.3294, 0.6408, 1.263, 2.5074"); index_2 ("0.001, 0.0234, 0.039, 0.0648, 0.108, 0.18, 0.3"); values ( \ - "0.00578193, 0.00615537, 0.00614988, 0.00608845, 0.00597884, 0.00569509, 0.00531864", \ - "0.00546114, 0.00586061, 0.00592896, 0.00590776, 0.0058618, 0.00571252, 0.00533625", \ - "0.00558037, 0.00574432, 0.00590681, 0.00584126, 0.00577682, 0.00568167, 0.00526932", \ - "0.00626555, 0.0059685, 0.00586989, 0.00591156, 0.0059423, 0.00564655, 0.00555532", \ - "0.00848179, 0.00711026, 0.00685335, 0.00654148, 0.0062987, 0.00642671, 0.00579393", \ - "0.0140766, 0.0108776, 0.0100695, 0.00917393, 0.00831475, 0.00728382, 0.00712184", \ - "0.0260475, 0.0208505, 0.0187577, 0.0166829, 0.0146194, 0.0126368, 0.0106917" \ + "0.0057817, 0.00615917, 0.00614999, 0.00610613, 0.00597947, 0.00569545, 0.00531829", \ + "0.00546462, 0.00591505, 0.00591776, 0.00599006, 0.00586572, 0.00571092, 0.00534059", \ + "0.00558099, 0.00574432, 0.00590434, 0.00592608, 0.00577538, 0.00566725, 0.00529031", \ + "0.00626602, 0.00596849, 0.00586979, 0.00591138, 0.00594631, 0.00565067, 0.00551251", \ + "0.00848097, 0.00710851, 0.00684517, 0.00653896, 0.00625363, 0.0061079, 0.00577495", \ + "0.0140767, 0.0108778, 0.010068, 0.00916919, 0.00835548, 0.00730658, 0.00719031", \ + "0.0260362, 0.0208504, 0.0187582, 0.0166776, 0.0146212, 0.0126494, 0.0106917" \ ); } fall_power (POWER_7x7ds1) { index_1 ("0.0186, 0.0966, 0.174, 0.3294, 0.6408, 1.263, 2.5074"); index_2 ("0.001, 0.0234, 0.039, 0.0648, 0.108, 0.18, 0.3"); values ( \ - "0.00548044, 0.00558625, 0.00554669, 0.00547516, 0.0053291, 0.00509598, 0.00469748", \ - "0.00530714, 0.00539828, 0.00551127, 0.00538772, 0.00528093, 0.00504103, 0.00463419", \ - "0.00565322, 0.00547589, 0.00543137, 0.00552577, 0.00524971, 0.0050778, 0.00462699", \ - "0.00672147, 0.00597595, 0.0058577, 0.00559908, 0.00555576, 0.00517067, 0.00464716", \ - "0.00929233, 0.00759423, 0.00714925, 0.00673472, 0.00616082, 0.00569076, 0.00558229", \ - "0.0150266, 0.0117644, 0.0107644, 0.00961059, 0.00854866, 0.00756049, 0.00624071", \ - "0.0269176, 0.022133, 0.0201598, 0.0177608, 0.0152723, 0.0130606, 0.0108265" \ + "0.00548548, 0.00558732, 0.00554704, 0.00547406, 0.00532324, 0.00511097, 0.00469774", \ + "0.00531491, 0.00539526, 0.0054977, 0.00540058, 0.00522946, 0.00504096, 0.00463317", \ + "0.00564965, 0.00547582, 0.00542954, 0.00544388, 0.00523932, 0.0050595, 0.00463003", \ + "0.00672675, 0.00597031, 0.00583745, 0.00561703, 0.0055502, 0.00517093, 0.00465185", \ + "0.00929199, 0.00758808, 0.00714474, 0.00672523, 0.0061632, 0.00562876, 0.0050814", \ + "0.0150263, 0.0117655, 0.0107593, 0.00959393, 0.00854874, 0.00756353, 0.00618803", \ + "0.026919, 0.0221342, 0.0201598, 0.0177608, 0.0152739, 0.0130664, 0.010848" \ ); } } @@ -5742,26 +5742,26 @@ library (sg13g2_stdcell_fast_1p32V_m40C) { index_1 ("0.0186, 0.0966, 0.174, 0.3294, 0.6408, 1.263, 2.5074"); index_2 ("0.001, 0.0234, 0.039, 0.0648, 0.108, 0.18, 0.3"); values ( \ - "0.00578193, 0.00615537, 0.00614988, 0.00608845, 0.00597884, 0.00569509, 0.00531864", \ - "0.00546114, 0.00586061, 0.00592896, 0.00590776, 0.0058618, 0.00571252, 0.00533625", \ - "0.00558037, 0.00574432, 0.00590681, 0.00584126, 0.00577682, 0.00568167, 0.00526932", \ - "0.00626555, 0.0059685, 0.00586989, 0.00591156, 0.0059423, 0.00564655, 0.00555532", \ - "0.00848179, 0.00711026, 0.00685335, 0.00654148, 0.0062987, 0.00642671, 0.00579393", \ - "0.0140766, 0.0108776, 0.0100695, 0.00917393, 0.00831475, 0.00728382, 0.00712184", \ - "0.0260475, 0.0208505, 0.0187577, 0.0166829, 0.0146194, 0.0126368, 0.0106917" \ + "0.0057817, 0.00615917, 0.00614999, 0.00610613, 0.00597947, 0.00569545, 0.00531829", \ + "0.00546462, 0.00591505, 0.00591776, 0.00599006, 0.00586572, 0.00571092, 0.00534059", \ + "0.00558099, 0.00574432, 0.00590434, 0.00592608, 0.00577538, 0.00566725, 0.00529031", \ + "0.00626602, 0.00596849, 0.00586979, 0.00591138, 0.00594631, 0.00565067, 0.00551251", \ + "0.00848097, 0.00710851, 0.00684517, 0.00653896, 0.00625363, 0.0061079, 0.00577495", \ + "0.0140767, 0.0108778, 0.010068, 0.00916919, 0.00835548, 0.00730658, 0.00719031", \ + "0.0260362, 0.0208504, 0.0187582, 0.0166776, 0.0146212, 0.0126494, 0.0106917" \ ); } fall_power (POWER_7x7ds1) { index_1 ("0.0186, 0.0966, 0.174, 0.3294, 0.6408, 1.263, 2.5074"); index_2 ("0.001, 0.0234, 0.039, 0.0648, 0.108, 0.18, 0.3"); values ( \ - "0.00548044, 0.00558625, 0.00554669, 0.00547516, 0.0053291, 0.00509598, 0.00469748", \ - "0.00530714, 0.00539828, 0.00551127, 0.00538772, 0.00528093, 0.00504103, 0.00463419", \ - "0.00565322, 0.00547589, 0.00543137, 0.00552577, 0.00524971, 0.0050778, 0.00462699", \ - "0.00672147, 0.00597595, 0.0058577, 0.00559908, 0.00555576, 0.00517067, 0.00464716", \ - "0.00929233, 0.00759423, 0.00714925, 0.00673472, 0.00616082, 0.00569076, 0.00558229", \ - "0.0150266, 0.0117644, 0.0107644, 0.00961059, 0.00854866, 0.00756049, 0.00624071", \ - "0.0269176, 0.022133, 0.0201598, 0.0177608, 0.0152723, 0.0130606, 0.0108265" \ + "0.00548548, 0.00558732, 0.00554704, 0.00547406, 0.00532324, 0.00511097, 0.00469774", \ + "0.00531491, 0.00539526, 0.0054977, 0.00540058, 0.00522946, 0.00504096, 0.00463317", \ + "0.00564965, 0.00547582, 0.00542954, 0.00544388, 0.00523932, 0.0050595, 0.00463003", \ + "0.00672675, 0.00597031, 0.00583745, 0.00561703, 0.0055502, 0.00517093, 0.00465185", \ + "0.00929199, 0.00758808, 0.00714474, 0.00672523, 0.0061632, 0.00562876, 0.0050814", \ + "0.0150263, 0.0117655, 0.0107593, 0.00959393, 0.00854874, 0.00756353, 0.00618803", \ + "0.026919, 0.0221342, 0.0201598, 0.0177608, 0.0152739, 0.0130664, 0.010848" \ ); } } @@ -5772,26 +5772,26 @@ library (sg13g2_stdcell_fast_1p32V_m40C) { index_1 ("0.0186, 0.0966, 0.174, 0.3294, 0.6408, 1.263, 2.5074"); index_2 ("0.001, 0.0234, 0.039, 0.0648, 0.108, 0.18, 0.3"); values ( \ - "0.00595904, 0.00601423, 0.00597916, 0.00590094, 0.00576188, 0.00550502, 0.00513138", \ - "0.00573708, 0.00590067, 0.00588344, 0.00580926, 0.0057002, 0.00551971, 0.00511192", \ - "0.00582882, 0.00583309, 0.00592884, 0.00580466, 0.0056627, 0.00572032, 0.00508887", \ - "0.00642331, 0.00612257, 0.00600801, 0.00596544, 0.00581912, 0.00555151, 0.00542372", \ - "0.00852519, 0.0073154, 0.00702403, 0.00670539, 0.00633929, 0.00624744, 0.00554744", \ - "0.0139194, 0.0112147, 0.0103402, 0.00939595, 0.00859183, 0.00736581, 0.00723195", \ - "0.0255042, 0.0211891, 0.0193265, 0.0172915, 0.0151323, 0.0131211, 0.0108481" \ + "0.00596143, 0.00601419, 0.00597046, 0.0059053, 0.00577627, 0.0055052, 0.00510822", \ + "0.00573803, 0.00590505, 0.00588412, 0.00580944, 0.00567951, 0.00549369, 0.00512509", \ + "0.00583119, 0.00583306, 0.00590212, 0.00580803, 0.00567352, 0.00572698, 0.00506209", \ + "0.00642458, 0.00612339, 0.00600173, 0.00595943, 0.00582149, 0.00555045, 0.00542879", \ + "0.00852521, 0.0073175, 0.00702369, 0.00667666, 0.00631959, 0.00645209, 0.00567025", \ + "0.0139198, 0.0112142, 0.0103413, 0.00939575, 0.00856402, 0.00736541, 0.00713071", \ + "0.0255043, 0.0211889, 0.0193261, 0.0172917, 0.0151318, 0.0131116, 0.0108633" \ ); } fall_power (POWER_7x7ds1) { index_1 ("0.0186, 0.0966, 0.174, 0.3294, 0.6408, 1.263, 2.5074"); index_2 ("0.001, 0.0234, 0.039, 0.0648, 0.108, 0.18, 0.3"); values ( \ - "0.00756044, 0.00756777, 0.00753459, 0.00745543, 0.00732792, 0.00708989, 0.00673208", \ - "0.00727363, 0.00739371, 0.0075188, 0.00735586, 0.00726975, 0.00700595, 0.00660544", \ - "0.00739138, 0.00740756, 0.00738034, 0.00749555, 0.00719632, 0.00701459, 0.00655625", \ - "0.00813605, 0.00775797, 0.00768426, 0.00752155, 0.00746784, 0.00714018, 0.00692943", \ - "0.0103834, 0.00899084, 0.00864703, 0.00840268, 0.00804349, 0.00759018, 0.00717481", \ - "0.0157626, 0.0128776, 0.0119129, 0.0109068, 0.0101918, 0.00921689, 0.00802591", \ - "0.027207, 0.0225704, 0.0207096, 0.0184164, 0.0162227, 0.0143037, 0.0123907" \ + "0.00755555, 0.00756766, 0.00753449, 0.00745592, 0.00732571, 0.00709112, 0.00673238", \ + "0.00727354, 0.00739345, 0.0075214, 0.00739737, 0.00746496, 0.00699925, 0.00661019", \ + "0.00739154, 0.00741526, 0.0073775, 0.00749656, 0.00721294, 0.00723607, 0.00663651", \ + "0.00813821, 0.00775393, 0.00768003, 0.00752177, 0.00746711, 0.00703168, 0.00692877", \ + "0.010382, 0.00899321, 0.00864999, 0.008403, 0.0080441, 0.00754841, 0.00716428", \ + "0.0157628, 0.0128814, 0.0119127, 0.0109063, 0.0101917, 0.00922877, 0.00803034", \ + "0.0272071, 0.0225701, 0.0207099, 0.0184303, 0.0162195, 0.0143035, 0.0123292" \ ); } } @@ -5801,26 +5801,26 @@ library (sg13g2_stdcell_fast_1p32V_m40C) { index_1 ("0.0186, 0.0966, 0.174, 0.3294, 0.6408, 1.263, 2.5074"); index_2 ("0.001, 0.0234, 0.039, 0.0648, 0.108, 0.18, 0.3"); values ( \ - "0.00595904, 0.00601423, 0.00597916, 0.00590094, 0.00576188, 0.00550502, 0.00513138", \ - "0.00573708, 0.00590067, 0.00588344, 0.00580926, 0.0057002, 0.00551971, 0.00511192", \ - "0.00582882, 0.00583309, 0.00592884, 0.00580466, 0.0056627, 0.00572032, 0.00508887", \ - "0.00642331, 0.00612257, 0.00600801, 0.00596544, 0.00581912, 0.00555151, 0.00542372", \ - "0.00852519, 0.0073154, 0.00702403, 0.00670539, 0.00633929, 0.00624744, 0.00554744", \ - "0.0139194, 0.0112147, 0.0103402, 0.00939595, 0.00859183, 0.00736581, 0.00723195", \ - "0.0255042, 0.0211891, 0.0193265, 0.0172915, 0.0151323, 0.0131211, 0.0108481" \ + "0.00596143, 0.00601419, 0.00597046, 0.0059053, 0.00577627, 0.0055052, 0.00510822", \ + "0.00573803, 0.00590505, 0.00588412, 0.00580944, 0.00567951, 0.00549369, 0.00512509", \ + "0.00583119, 0.00583306, 0.00590212, 0.00580803, 0.00567352, 0.00572698, 0.00506209", \ + "0.00642458, 0.00612339, 0.00600173, 0.00595943, 0.00582149, 0.00555045, 0.00542879", \ + "0.00852521, 0.0073175, 0.00702369, 0.00667666, 0.00631959, 0.00645209, 0.00567025", \ + "0.0139198, 0.0112142, 0.0103413, 0.00939575, 0.00856402, 0.00736541, 0.00713071", \ + "0.0255043, 0.0211889, 0.0193261, 0.0172917, 0.0151318, 0.0131116, 0.0108633" \ ); } fall_power (POWER_7x7ds1) { index_1 ("0.0186, 0.0966, 0.174, 0.3294, 0.6408, 1.263, 2.5074"); index_2 ("0.001, 0.0234, 0.039, 0.0648, 0.108, 0.18, 0.3"); values ( \ - "0.00756044, 0.00756777, 0.00753459, 0.00745543, 0.00732792, 0.00708989, 0.00673208", \ - "0.00727363, 0.00739371, 0.0075188, 0.00735586, 0.00726975, 0.00700595, 0.00660544", \ - "0.00739138, 0.00740756, 0.00738034, 0.00749555, 0.00719632, 0.00701459, 0.00655625", \ - "0.00813605, 0.00775797, 0.00768426, 0.00752155, 0.00746784, 0.00714018, 0.00692943", \ - "0.0103834, 0.00899084, 0.00864703, 0.00840268, 0.00804349, 0.00759018, 0.00717481", \ - "0.0157626, 0.0128776, 0.0119129, 0.0109068, 0.0101918, 0.00921689, 0.00802591", \ - "0.027207, 0.0225704, 0.0207096, 0.0184164, 0.0162227, 0.0143037, 0.0123907" \ + "0.00755555, 0.00756766, 0.00753449, 0.00745592, 0.00732571, 0.00709112, 0.00673238", \ + "0.00727354, 0.00739345, 0.0075214, 0.00739737, 0.00746496, 0.00699925, 0.00661019", \ + "0.00739154, 0.00741526, 0.0073775, 0.00749656, 0.00721294, 0.00723607, 0.00663651", \ + "0.00813821, 0.00775393, 0.00768003, 0.00752177, 0.00746711, 0.00703168, 0.00692877", \ + "0.010382, 0.00899321, 0.00864999, 0.008403, 0.0080441, 0.00754841, 0.00716428", \ + "0.0157628, 0.0128814, 0.0119127, 0.0109063, 0.0101917, 0.00922877, 0.00803034", \ + "0.0272071, 0.0225701, 0.0207099, 0.0184303, 0.0162195, 0.0143035, 0.0123292" \ ); } } @@ -5831,26 +5831,26 @@ library (sg13g2_stdcell_fast_1p32V_m40C) { index_1 ("0.0186, 0.0966, 0.174, 0.3294, 0.6408, 1.263, 2.5074"); index_2 ("0.001, 0.0234, 0.039, 0.0648, 0.108, 0.18, 0.3"); values ( \ - "0.0034932, 0.00362346, 0.0036165, 0.00355188, 0.0034243, 0.00315361, 0.00273761", \ - "0.00348494, 0.00355409, 0.00354985, 0.00346912, 0.00343839, 0.00314076, 0.00273376", \ - "0.00397589, 0.00361812, 0.00366747, 0.00348425, 0.0033268, 0.003124, 0.0028935", \ - "0.00514557, 0.00432031, 0.00405526, 0.00387161, 0.00359247, 0.003441, 0.00278425", \ - "0.00771356, 0.00607327, 0.00555011, 0.00498118, 0.00443715, 0.00388459, 0.00306874", \ - "0.0133829, 0.0105591, 0.0095264, 0.00844458, 0.0071844, 0.00576161, 0.00525257", \ - "0.0252529, 0.021076, 0.0192145, 0.0169693, 0.0145836, 0.0122047, 0.00937185" \ + "0.00349706, 0.00362391, 0.00360946, 0.00354176, 0.00343288, 0.00315399, 0.0027384", \ + "0.00348446, 0.00351478, 0.00354992, 0.00366313, 0.00332337, 0.0031436, 0.00276654", \ + "0.00397388, 0.00361473, 0.00360754, 0.00346216, 0.00332584, 0.00310909, 0.00286272", \ + "0.00514594, 0.00431494, 0.00405512, 0.00387641, 0.00374777, 0.00344097, 0.00307407", \ + "0.00771436, 0.00607328, 0.00555603, 0.00498137, 0.00443702, 0.00388478, 0.00307987", \ + "0.0133824, 0.0105792, 0.00952372, 0.00844396, 0.00716659, 0.00576161, 0.00525097", \ + "0.0252539, 0.021076, 0.0192148, 0.0169671, 0.0145849, 0.0122048, 0.00938371" \ ); } fall_power (POWER_7x7ds1) { index_1 ("0.0186, 0.0966, 0.174, 0.3294, 0.6408, 1.263, 2.5074"); index_2 ("0.001, 0.0234, 0.039, 0.0648, 0.108, 0.18, 0.3"); values ( \ - "0.0074084, 0.00784716, 0.00782166, 0.00778119, 0.00767095, 0.00740443, 0.00708168", \ - "0.00708092, 0.00758337, 0.00776241, 0.00768491, 0.00771367, 0.00740924, 0.00704582", \ - "0.00727963, 0.00752128, 0.00756514, 0.00773804, 0.00754418, 0.00736216, 0.00705621", \ - "0.00819388, 0.00777076, 0.00779262, 0.0077005, 0.007755, 0.00744565, 0.00700249", \ - "0.010664, 0.0089513, 0.00864511, 0.00842384, 0.00812011, 0.00779915, 0.0082077", \ - "0.0163361, 0.0127633, 0.0117747, 0.0107544, 0.010087, 0.0093847, 0.00815431", \ - "0.0282739, 0.022464, 0.0203423, 0.0180654, 0.0159208, 0.0139134, 0.0123501" \ + "0.00740635, 0.00783722, 0.00782657, 0.00778143, 0.00767077, 0.00740342, 0.00699321", \ + "0.00708196, 0.00757881, 0.00776828, 0.00768067, 0.00764117, 0.00740933, 0.0070681", \ + "0.00727917, 0.00753617, 0.00756242, 0.00772423, 0.00754476, 0.00734814, 0.0070068", \ + "0.0081928, 0.00777026, 0.00779567, 0.0077157, 0.00775209, 0.0074532, 0.00703274", \ + "0.010664, 0.00895064, 0.00865555, 0.00841884, 0.00814176, 0.00777583, 0.00795717", \ + "0.0163365, 0.0127624, 0.0117713, 0.0107547, 0.0101292, 0.00938296, 0.008197", \ + "0.0282735, 0.0224639, 0.0203423, 0.0180553, 0.0159209, 0.0139203, 0.0123494" \ ); } } @@ -5861,26 +5861,26 @@ library (sg13g2_stdcell_fast_1p32V_m40C) { index_1 ("0.0186, 0.0966, 0.174, 0.3294, 0.6408, 1.263, 2.5074"); index_2 ("0.001, 0.0234, 0.039, 0.0648, 0.108, 0.18, 0.3"); values ( \ - "0.00330382, 0.00350266, 0.00348196, 0.00342417, 0.00331562, 0.00306537, 0.00266266", \ - "0.003368, 0.00341239, 0.00339273, 0.00332407, 0.00323042, 0.00305082, 0.00257567", \ - "0.00393115, 0.00349178, 0.00352028, 0.00339215, 0.00324466, 0.00302385, 0.00260241", \ - "0.00518999, 0.00421768, 0.00395774, 0.00377016, 0.00355457, 0.00321008, 0.00288904", \ - "0.0078586, 0.00602524, 0.00550766, 0.00493004, 0.00430128, 0.00377594, 0.00310101", \ - "0.0136546, 0.0105904, 0.00951476, 0.00839472, 0.00715405, 0.00559759, 0.005253", \ - "0.0256407, 0.0212563, 0.019234, 0.0170529, 0.0146341, 0.0120642, 0.00947597" \ + "0.00330364, 0.00350266, 0.00350062, 0.00342644, 0.00331603, 0.00300535, 0.00266267", \ + "0.00336787, 0.00344702, 0.00338954, 0.00346328, 0.00322192, 0.0030503, 0.00257658", \ + "0.00392917, 0.00350324, 0.00352753, 0.00333368, 0.00322506, 0.00304324, 0.0026019", \ + "0.00518877, 0.00421634, 0.00395776, 0.00373845, 0.00355306, 0.00324318, 0.00280063", \ + "0.00785818, 0.00602776, 0.00550763, 0.00492846, 0.00430148, 0.0042306, 0.003101", \ + "0.0136531, 0.0105908, 0.00950766, 0.00839113, 0.00715648, 0.00574979, 0.0052501", \ + "0.0256413, 0.021256, 0.019232, 0.0170509, 0.0146342, 0.0120591, 0.00929956" \ ); } fall_power (POWER_7x7ds1) { index_1 ("0.0186, 0.0966, 0.174, 0.3294, 0.6408, 1.263, 2.5074"); index_2 ("0.001, 0.0234, 0.039, 0.0648, 0.108, 0.18, 0.3"); values ( \ - "0.00528554, 0.00574918, 0.00572735, 0.00568252, 0.00558528, 0.00531266, 0.00495455", \ - "0.00496793, 0.00545745, 0.00565183, 0.0055666, 0.00566298, 0.00529827, 0.00491863", \ - "0.00518185, 0.00543872, 0.00545517, 0.00563014, 0.00545216, 0.00542768, 0.00493686", \ - "0.00610922, 0.00567056, 0.00568963, 0.00559817, 0.00565418, 0.00534584, 0.00502858", \ - "0.00864429, 0.00687896, 0.00654641, 0.00635083, 0.00606033, 0.00574636, 0.00590388", \ - "0.0144025, 0.010708, 0.00979085, 0.0087439, 0.00803478, 0.0073766, 0.00611143", \ - "0.026501, 0.0204507, 0.0183493, 0.0159205, 0.0141468, 0.0118432, 0.0102626" \ + "0.00528515, 0.0057441, 0.00572613, 0.00568514, 0.00558374, 0.00532051, 0.00495528", \ + "0.00496794, 0.00546461, 0.0056546, 0.00556482, 0.00565192, 0.00529912, 0.00491698", \ + "0.005181, 0.00543188, 0.00546188, 0.0056473, 0.00546174, 0.00549371, 0.00493759", \ + "0.00610934, 0.00567029, 0.00569541, 0.00557355, 0.00565338, 0.00533122, 0.00496879", \ + "0.00864401, 0.00687846, 0.00654878, 0.0063523, 0.00609361, 0.00574676, 0.0060071", \ + "0.0144027, 0.0107075, 0.00979094, 0.00874297, 0.0080393, 0.00737981, 0.00611117", \ + "0.0265015, 0.020451, 0.0183498, 0.0159202, 0.0141469, 0.0118169, 0.0102853" \ ); } } @@ -5890,26 +5890,26 @@ library (sg13g2_stdcell_fast_1p32V_m40C) { index_1 ("0.0186, 0.0966, 0.174, 0.3294, 0.6408, 1.263, 2.5074"); index_2 ("0.001, 0.0234, 0.039, 0.0648, 0.108, 0.18, 0.3"); values ( \ - "0.0034932, 0.00362346, 0.0036165, 0.00355188, 0.0034243, 0.00315361, 0.00273761", \ - "0.00348494, 0.00355409, 0.00354985, 0.00346912, 0.00343839, 0.00314076, 0.00273376", \ - "0.00397589, 0.00361812, 0.00366747, 0.00348425, 0.0033268, 0.003124, 0.0028935", \ - "0.00514557, 0.00432031, 0.00405526, 0.00387161, 0.00359247, 0.003441, 0.00278425", \ - "0.00771356, 0.00607327, 0.00555011, 0.00498118, 0.00443715, 0.00388459, 0.00306874", \ - "0.0133829, 0.0105591, 0.0095264, 0.00844458, 0.0071844, 0.00576161, 0.00525257", \ - "0.0252529, 0.021076, 0.0192145, 0.0169693, 0.0145836, 0.0122047, 0.00937185" \ + "0.00349706, 0.00362391, 0.00360946, 0.00354176, 0.00343288, 0.00315399, 0.0027384", \ + "0.00348446, 0.00351478, 0.00354992, 0.00366313, 0.00332337, 0.0031436, 0.00276654", \ + "0.00397388, 0.00361473, 0.00360754, 0.00346216, 0.00332584, 0.00310909, 0.00286272", \ + "0.00514594, 0.00431494, 0.00405512, 0.00387641, 0.00374777, 0.00344097, 0.00307407", \ + "0.00771436, 0.00607328, 0.00555603, 0.00498137, 0.00443702, 0.00388478, 0.00307987", \ + "0.0133824, 0.0105792, 0.00952372, 0.00844396, 0.00716659, 0.00576161, 0.00525097", \ + "0.0252539, 0.021076, 0.0192148, 0.0169671, 0.0145849, 0.0122048, 0.00938371" \ ); } fall_power (POWER_7x7ds1) { index_1 ("0.0186, 0.0966, 0.174, 0.3294, 0.6408, 1.263, 2.5074"); index_2 ("0.001, 0.0234, 0.039, 0.0648, 0.108, 0.18, 0.3"); values ( \ - "0.0074084, 0.00784716, 0.00782166, 0.00778119, 0.00767095, 0.00740443, 0.00708168", \ - "0.00708092, 0.00758337, 0.00776241, 0.00768491, 0.00771367, 0.00740924, 0.00704582", \ - "0.00727963, 0.00752128, 0.00756514, 0.00773804, 0.00754418, 0.00736216, 0.00705621", \ - "0.00819388, 0.00777076, 0.00779262, 0.0077005, 0.007755, 0.00744565, 0.00700249", \ - "0.010664, 0.0089513, 0.00864511, 0.00842384, 0.00812011, 0.00779915, 0.0082077", \ - "0.0163361, 0.0127633, 0.0117747, 0.0107544, 0.010087, 0.0093847, 0.00815431", \ - "0.0282739, 0.022464, 0.0203423, 0.0180654, 0.0159208, 0.0139134, 0.0123501" \ + "0.00740635, 0.00783722, 0.00782657, 0.00778143, 0.00767077, 0.00740342, 0.00699321", \ + "0.00708196, 0.00757881, 0.00776828, 0.00768067, 0.00764117, 0.00740933, 0.0070681", \ + "0.00727917, 0.00753617, 0.00756242, 0.00772423, 0.00754476, 0.00734814, 0.0070068", \ + "0.0081928, 0.00777026, 0.00779567, 0.0077157, 0.00775209, 0.0074532, 0.00703274", \ + "0.010664, 0.00895064, 0.00865555, 0.00841884, 0.00814176, 0.00777583, 0.00795717", \ + "0.0163365, 0.0127624, 0.0117713, 0.0107547, 0.0101292, 0.00938296, 0.008197", \ + "0.0282735, 0.0224639, 0.0203423, 0.0180553, 0.0159209, 0.0139203, 0.0123494" \ ); } } @@ -5920,26 +5920,26 @@ library (sg13g2_stdcell_fast_1p32V_m40C) { index_1 ("0.0186, 0.0966, 0.174, 0.3294, 0.6408, 1.263, 2.5074"); index_2 ("0.001, 0.0234, 0.039, 0.0648, 0.108, 0.18, 0.3"); values ( \ - "0.00329452, 0.00370609, 0.00371565, 0.00365557, 0.00356298, 0.00329896, 0.00287126", \ - "0.00326296, 0.00351591, 0.00350973, 0.00353324, 0.0034303, 0.00329101, 0.00284657", \ - "0.00369232, 0.00347525, 0.00357856, 0.00349804, 0.0033958, 0.00319706, 0.00293775", \ - "0.004891, 0.00412011, 0.0039047, 0.00378262, 0.0036213, 0.00339099, 0.00299617", \ - "0.00768917, 0.00585691, 0.00529691, 0.00476613, 0.00429698, 0.00398834, 0.00314033", \ - "0.0133561, 0.0100823, 0.00896925, 0.00805598, 0.00694733, 0.00554662, 0.00526466", \ - "0.0256156, 0.0204539, 0.0184432, 0.0163311, 0.0141706, 0.0116797, 0.00926266" \ + "0.0032924, 0.00370601, 0.00371592, 0.00365568, 0.00353299, 0.00329875, 0.0028746", \ + "0.00326291, 0.00351644, 0.00349928, 0.00348826, 0.00343441, 0.00329347, 0.00285631", \ + "0.00369142, 0.00347526, 0.00357408, 0.00348548, 0.00339643, 0.0032225, 0.00303194", \ + "0.00489123, 0.0041188, 0.00391, 0.00377515, 0.00359966, 0.00342376, 0.00299555", \ + "0.00768965, 0.00585582, 0.00529716, 0.00476615, 0.00429711, 0.00383307, 0.00313901", \ + "0.0133553, 0.0100824, 0.00896905, 0.00805301, 0.00696616, 0.00562329, 0.0052428", \ + "0.025616, 0.0204539, 0.0184426, 0.0163307, 0.0141698, 0.0116749, 0.00926371" \ ); } fall_power (POWER_7x7ds1) { index_1 ("0.0186, 0.0966, 0.174, 0.3294, 0.6408, 1.263, 2.5074"); index_2 ("0.001, 0.0234, 0.039, 0.0648, 0.108, 0.18, 0.3"); values ( \ - "0.00525498, 0.00579584, 0.00580023, 0.0057444, 0.00564111, 0.00541358, 0.00492264", \ - "0.0051942, 0.00556354, 0.0057621, 0.00569866, 0.00590261, 0.00541113, 0.00497858", \ - "0.00563606, 0.00559485, 0.0056075, 0.00579051, 0.00554226, 0.00562554, 0.00499768", \ - "0.00687628, 0.00601087, 0.00594747, 0.00581957, 0.00579375, 0.00548804, 0.00537094", \ - "0.00958091, 0.00785732, 0.00711856, 0.00675738, 0.0062834, 0.00597012, 0.00555304", \ - "0.0155647, 0.0117, 0.0105889, 0.00951852, 0.00854418, 0.00764666, 0.00634984", \ - "0.0279256, 0.0220044, 0.0197659, 0.0173257, 0.0147992, 0.012845, 0.0108626" \ + "0.00525652, 0.00579363, 0.00580091, 0.00575182, 0.00564077, 0.00541358, 0.00492932", \ + "0.0051945, 0.00556355, 0.0056867, 0.00568747, 0.00590611, 0.00541715, 0.00495759", \ + "0.00563557, 0.0055853, 0.00559785, 0.00571083, 0.00552658, 0.0056053, 0.00503768", \ + "0.00687576, 0.00601094, 0.00594747, 0.00581911, 0.00582214, 0.0054879, 0.00541329", \ + "0.00957964, 0.00785727, 0.00712857, 0.006772, 0.00627131, 0.00594802, 0.00555357", \ + "0.0155646, 0.0117065, 0.0105829, 0.00951853, 0.00854426, 0.00764638, 0.00642279", \ + "0.0279259, 0.0220052, 0.01977, 0.0173259, 0.014881, 0.012848, 0.0108686" \ ); } } @@ -5950,26 +5950,26 @@ library (sg13g2_stdcell_fast_1p32V_m40C) { index_1 ("0.0186, 0.0966, 0.174, 0.3294, 0.6408, 1.263, 2.5074"); index_2 ("0.001, 0.0234, 0.039, 0.0648, 0.108, 0.18, 0.3"); values ( \ - "0.00301597, 0.00359353, 0.00357597, 0.00352896, 0.00345368, 0.00316276, 0.00277353", \ - "0.00313636, 0.00335069, 0.00336548, 0.00337707, 0.00332335, 0.00314041, 0.00274668", \ - "0.0036536, 0.00335001, 0.00345329, 0.00334184, 0.003268, 0.00314586, 0.00281874", \ - "0.00498122, 0.00404451, 0.00374984, 0.00364898, 0.00351592, 0.00321235, 0.00340782", \ - "0.0077601, 0.00582233, 0.0052333, 0.00470367, 0.00419126, 0.00394238, 0.00328167", \ - "0.0137276, 0.0101573, 0.00900214, 0.00797509, 0.00683615, 0.00545299, 0.00482974", \ - "0.0261195, 0.0206005, 0.0185839, 0.0163724, 0.0139968, 0.0116149, 0.00915127" \ + "0.00301588, 0.00357311, 0.00359241, 0.00354583, 0.00344312, 0.00318581, 0.002784", \ + "0.00313642, 0.00332769, 0.0033655, 0.00349763, 0.00332703, 0.00313998, 0.00274249", \ + "0.00365242, 0.00334448, 0.00345401, 0.00340027, 0.00328642, 0.00319528, 0.00286814", \ + "0.00498185, 0.00403572, 0.00377307, 0.00366094, 0.00346279, 0.00329674, 0.00287704", \ + "0.00776012, 0.00582236, 0.00523758, 0.00470345, 0.0042015, 0.00393689, 0.00328187", \ + "0.0137249, 0.0101571, 0.009002, 0.00797468, 0.0068526, 0.00542725, 0.00484923", \ + "0.0261199, 0.0206011, 0.0185841, 0.0163716, 0.0139973, 0.0116099, 0.00918146" \ ); } fall_power (POWER_7x7ds1) { index_1 ("0.0186, 0.0966, 0.174, 0.3294, 0.6408, 1.263, 2.5074"); index_2 ("0.001, 0.0234, 0.039, 0.0648, 0.108, 0.18, 0.3"); values ( \ - "0.00314029, 0.00369491, 0.00370426, 0.00366337, 0.00354706, 0.00333227, 0.00291278", \ - "0.00308453, 0.00346249, 0.00364771, 0.00356472, 0.00361797, 0.00329291, 0.00295331", \ - "0.00353699, 0.00348325, 0.00350012, 0.00367679, 0.00346273, 0.00331868, 0.00291521", \ - "0.0047996, 0.00391708, 0.0038257, 0.00374254, 0.00370552, 0.00339771, 0.00294885", \ - "0.0075697, 0.00579767, 0.00502059, 0.00471377, 0.00423641, 0.00383289, 0.00354502", \ - "0.0136197, 0.00963358, 0.00848578, 0.00741064, 0.00650883, 0.00561139, 0.00433563", \ - "0.0261096, 0.0199301, 0.0177233, 0.0153121, 0.0128345, 0.0107073, 0.00888325" \ + "0.00313912, 0.00369652, 0.00370359, 0.00366344, 0.0035471, 0.00333301, 0.00291291", \ + "0.00308404, 0.00345914, 0.00363757, 0.0035628, 0.00361899, 0.0032978, 0.00295276", \ + "0.00353628, 0.0035006, 0.00349979, 0.00361814, 0.00344341, 0.00333621, 0.00291679", \ + "0.00479889, 0.00391392, 0.00383062, 0.00374392, 0.00371588, 0.00341926, 0.00296974", \ + "0.00756978, 0.00579681, 0.00502558, 0.00471355, 0.00428794, 0.00389037, 0.00355284", \ + "0.0136197, 0.00964555, 0.00850071, 0.00740881, 0.0064928, 0.00561891, 0.00434941", \ + "0.0261093, 0.0199302, 0.0177044, 0.015312, 0.0128322, 0.0106905, 0.00892219" \ ); } } @@ -5979,26 +5979,26 @@ library (sg13g2_stdcell_fast_1p32V_m40C) { index_1 ("0.0186, 0.0966, 0.174, 0.3294, 0.6408, 1.263, 2.5074"); index_2 ("0.001, 0.0234, 0.039, 0.0648, 0.108, 0.18, 0.3"); values ( \ - "0.00329452, 0.00370609, 0.00371565, 0.00365557, 0.00356298, 0.00329896, 0.00287126", \ - "0.00326296, 0.00351591, 0.00350973, 0.00353324, 0.0034303, 0.00329101, 0.00284657", \ - "0.00369232, 0.00347525, 0.00357856, 0.00349804, 0.0033958, 0.00319706, 0.00293775", \ - "0.004891, 0.00412011, 0.0039047, 0.00378262, 0.0036213, 0.00339099, 0.00299617", \ - "0.00768917, 0.00585691, 0.00529691, 0.00476613, 0.00429698, 0.00398834, 0.00314033", \ - "0.0133561, 0.0100823, 0.00896925, 0.00805598, 0.00694733, 0.00554662, 0.00526466", \ - "0.0256156, 0.0204539, 0.0184432, 0.0163311, 0.0141706, 0.0116797, 0.00926266" \ + "0.0032924, 0.00370601, 0.00371592, 0.00365568, 0.00353299, 0.00329875, 0.0028746", \ + "0.00326291, 0.00351644, 0.00349928, 0.00348826, 0.00343441, 0.00329347, 0.00285631", \ + "0.00369142, 0.00347526, 0.00357408, 0.00348548, 0.00339643, 0.0032225, 0.00303194", \ + "0.00489123, 0.0041188, 0.00391, 0.00377515, 0.00359966, 0.00342376, 0.00299555", \ + "0.00768965, 0.00585582, 0.00529716, 0.00476615, 0.00429711, 0.00383307, 0.00313901", \ + "0.0133553, 0.0100824, 0.00896905, 0.00805301, 0.00696616, 0.00562329, 0.0052428", \ + "0.025616, 0.0204539, 0.0184426, 0.0163307, 0.0141698, 0.0116749, 0.00926371" \ ); } fall_power (POWER_7x7ds1) { index_1 ("0.0186, 0.0966, 0.174, 0.3294, 0.6408, 1.263, 2.5074"); index_2 ("0.001, 0.0234, 0.039, 0.0648, 0.108, 0.18, 0.3"); values ( \ - "0.00525498, 0.00579584, 0.00580023, 0.0057444, 0.00564111, 0.00541358, 0.00492264", \ - "0.0051942, 0.00556354, 0.0057621, 0.00569866, 0.00590261, 0.00541113, 0.00497858", \ - "0.00563606, 0.00559485, 0.0056075, 0.00579051, 0.00554226, 0.00562554, 0.00499768", \ - "0.00687628, 0.00601087, 0.00594747, 0.00581957, 0.00579375, 0.00548804, 0.00537094", \ - "0.00958091, 0.00785732, 0.00711856, 0.00675738, 0.0062834, 0.00597012, 0.00555304", \ - "0.0155647, 0.0117, 0.0105889, 0.00951852, 0.00854418, 0.00764666, 0.00634984", \ - "0.0279256, 0.0220044, 0.0197659, 0.0173257, 0.0147992, 0.012845, 0.0108626" \ + "0.00525652, 0.00579363, 0.00580091, 0.00575182, 0.00564077, 0.00541358, 0.00492932", \ + "0.0051945, 0.00556355, 0.0056867, 0.00568747, 0.00590611, 0.00541715, 0.00495759", \ + "0.00563557, 0.0055853, 0.00559785, 0.00571083, 0.00552658, 0.0056053, 0.00503768", \ + "0.00687576, 0.00601094, 0.00594747, 0.00581911, 0.00582214, 0.0054879, 0.00541329", \ + "0.00957964, 0.00785727, 0.00712857, 0.006772, 0.00627131, 0.00594802, 0.00555357", \ + "0.0155646, 0.0117065, 0.0105829, 0.00951853, 0.00854426, 0.00764638, 0.00642279", \ + "0.0279259, 0.0220052, 0.01977, 0.0173259, 0.014881, 0.012848, 0.0108686" \ ); } } @@ -6006,43 +6006,43 @@ library (sg13g2_stdcell_fast_1p32V_m40C) { pin (A1) { direction : "input"; max_transition : 2.5074; - capacitance : 0.00331964; - rise_capacitance : 0.00324224; - rise_capacitance_range (0.00324224, 0.00324224); - fall_capacitance : 0.00339705; - fall_capacitance_range (0.00339705, 0.00339705); + capacitance : 0.00331967; + rise_capacitance : 0.00324229; + rise_capacitance_range (0.00303417, 0.00351421); + fall_capacitance : 0.00339706; + fall_capacitance_range (0.00292977, 0.00384154); } pin (A2) { direction : "input"; max_transition : 2.5074; - capacitance : 0.00334804; - rise_capacitance : 0.00338855; - rise_capacitance_range (0.00338855, 0.00338855); - fall_capacitance : 0.00330754; - fall_capacitance_range (0.00330754, 0.00330754); + capacitance : 0.00334791; + rise_capacitance : 0.0033883; + rise_capacitance_range (0.00292359, 0.00370786); + fall_capacitance : 0.00330753; + fall_capacitance_range (0.00292158, 0.0036522); } pin (B1) { direction : "input"; max_transition : 2.5074; - capacitance : 0.00324665; - rise_capacitance : 0.00342704; - rise_capacitance_range (0.00342704, 0.00342704); - fall_capacitance : 0.00306627; - fall_capacitance_range (0.00306627, 0.00306627); + capacitance : 0.00324666; + rise_capacitance : 0.00342705; + rise_capacitance_range (0.00279566, 0.0038922); + fall_capacitance : 0.00306628; + fall_capacitance_range (0.00286463, 0.00335891); } pin (B2) { direction : "input"; max_transition : 2.5074; - capacitance : 0.00318968; - rise_capacitance : 0.00325292; - rise_capacitance_range (0.00325292, 0.00325292); - fall_capacitance : 0.00312643; - fall_capacitance_range (0.00312643, 0.00312643); + capacitance : 0.00318969; + rise_capacitance : 0.00325294; + rise_capacitance_range (0.00277145, 0.00371391); + fall_capacitance : 0.00312644; + fall_capacitance_range (0.00277816, 0.00356124); } } cell (sg13g2_and2_1) { area : 9.072; - cell_footprint : "AND2"; + cell_footprint : "and2"; cell_leakage_power : 284.751; leakage_power () { value : 341.224; @@ -6243,23 +6243,23 @@ library (sg13g2_stdcell_fast_1p32V_m40C) { max_transition : 2.5074; capacitance : 0.00273413; rise_capacitance : 0.00270742; - rise_capacitance_range (0.00270742, 0.00270742); + rise_capacitance_range (0.00243704, 0.00289522); fall_capacitance : 0.00276084; - fall_capacitance_range (0.00276084, 0.00276084); + fall_capacitance_range (0.00241598, 0.00303596); } pin (B) { direction : "input"; max_transition : 2.5074; capacitance : 0.00274293; rise_capacitance : 0.00281431; - rise_capacitance_range (0.00281431, 0.00281431); + rise_capacitance_range (0.0023867, 0.00306944); fall_capacitance : 0.00267154; - fall_capacitance_range (0.00267154, 0.00267154); + fall_capacitance_range (0.00245933, 0.00285539); } } cell (sg13g2_and2_2) { area : 10.8864; - cell_footprint : "AND2"; + cell_footprint : "and2"; cell_leakage_power : 422.922; leakage_power () { value : 420.318; @@ -6460,23 +6460,23 @@ library (sg13g2_stdcell_fast_1p32V_m40C) { max_transition : 2.5074; capacitance : 0.00271827; rise_capacitance : 0.00269873; - rise_capacitance_range (0.00269873, 0.00269873); + rise_capacitance_range (0.00247636, 0.00287108); fall_capacitance : 0.00273781; - fall_capacitance_range (0.00273781, 0.00273781); + fall_capacitance_range (0.00246339, 0.00296769); } pin (B) { direction : "input"; max_transition : 2.5074; capacitance : 0.00275205; rise_capacitance : 0.00282906; - rise_capacitance_range (0.00282906, 0.00282906); + rise_capacitance_range (0.0024267, 0.00307082); fall_capacitance : 0.00267503; - fall_capacitance_range (0.00267503, 0.00267503); + fall_capacitance_range (0.00249552, 0.00283892); } } cell (sg13g2_and3_1) { area : 12.7008; - cell_footprint : "AND3"; + cell_footprint : "and3"; cell_leakage_power : 329.142; leakage_power () { value : 472.329; @@ -6779,32 +6779,32 @@ library (sg13g2_stdcell_fast_1p32V_m40C) { max_transition : 2.5074; capacitance : 0.00272583; rise_capacitance : 0.0026738; - rise_capacitance_range (0.0026738, 0.0026738); + rise_capacitance_range (0.00243599, 0.00282817); fall_capacitance : 0.00277786; - fall_capacitance_range (0.00277786, 0.00277786); + fall_capacitance_range (0.00238712, 0.00310281); } pin (B) { direction : "input"; max_transition : 2.5074; capacitance : 0.0027182; rise_capacitance : 0.0027573; - rise_capacitance_range (0.0027573, 0.0027573); + rise_capacitance_range (0.00235036, 0.00299602); fall_capacitance : 0.00267911; - fall_capacitance_range (0.00267911, 0.00267911); + fall_capacitance_range (0.00239123, 0.00292071); } pin (C) { direction : "input"; max_transition : 2.5074; capacitance : 0.00272903; rise_capacitance : 0.0028054; - rise_capacitance_range (0.0028054, 0.0028054); + rise_capacitance_range (0.00239061, 0.00308291); fall_capacitance : 0.00265266; - fall_capacitance_range (0.00265266, 0.00265266); + fall_capacitance_range (0.00246358, 0.00282587); } } cell (sg13g2_and3_2) { area : 12.7008; - cell_footprint : "AND3"; + cell_footprint : "and3"; cell_leakage_power : 477.157; leakage_power () { value : 551.402; @@ -7107,32 +7107,32 @@ library (sg13g2_stdcell_fast_1p32V_m40C) { max_transition : 2.5074; capacitance : 0.00273297; rise_capacitance : 0.00269172; - rise_capacitance_range (0.00269172, 0.00269172); + rise_capacitance_range (0.00249222, 0.00283494); fall_capacitance : 0.00277422; - fall_capacitance_range (0.00277422, 0.00277422); + fall_capacitance_range (0.00246274, 0.00305186); } pin (B) { direction : "input"; max_transition : 2.5074; capacitance : 0.00272046; rise_capacitance : 0.0027685; - rise_capacitance_range (0.0027685, 0.0027685); + rise_capacitance_range (0.00237845, 0.00299842); fall_capacitance : 0.00267242; - fall_capacitance_range (0.00267242, 0.00267242); + fall_capacitance_range (0.00242965, 0.00288775); } pin (C) { direction : "input"; max_transition : 2.5074; capacitance : 0.00272834; rise_capacitance : 0.00281068; - rise_capacitance_range (0.00281068, 0.00281068); + rise_capacitance_range (0.00241169, 0.00307552); fall_capacitance : 0.002646; - fall_capacitance_range (0.002646, 0.002646); + fall_capacitance_range (0.00248174, 0.00280644); } } cell (sg13g2_and4_1) { area : 14.5152; - cell_footprint : "AND4"; + cell_footprint : "and4"; cell_leakage_power : 362.272; leakage_power () { value : 360.147; @@ -7553,41 +7553,41 @@ library (sg13g2_stdcell_fast_1p32V_m40C) { max_transition : 2.5074; capacitance : 0.00256062; rise_capacitance : 0.00249048; - rise_capacitance_range (0.00249048, 0.00249048); + rise_capacitance_range (0.00227163, 0.00262322); fall_capacitance : 0.00263077; - fall_capacitance_range (0.00263077, 0.00263077); + fall_capacitance_range (0.00221719, 0.00300604); } pin (B) { direction : "input"; max_transition : 2.5074; capacitance : 0.0026998; rise_capacitance : 0.00271725; - rise_capacitance_range (0.00271725, 0.00271725); + rise_capacitance_range (0.0023239, 0.00294716); fall_capacitance : 0.00268235; - fall_capacitance_range (0.00268235, 0.00268235); + fall_capacitance_range (0.00234783, 0.00297733); } pin (C) { direction : "input"; max_transition : 2.5074; capacitance : 0.00269413; rise_capacitance : 0.00274194; - rise_capacitance_range (0.00274194, 0.00274194); + rise_capacitance_range (0.00233711, 0.00300592); fall_capacitance : 0.00264631; - fall_capacitance_range (0.00264631, 0.00264631); + fall_capacitance_range (0.00238861, 0.00287715); } pin (D) { direction : "input"; max_transition : 2.5074; capacitance : 0.0027037; rise_capacitance : 0.00278174; - rise_capacitance_range (0.00278174, 0.00278174); + rise_capacitance_range (0.0023757, 0.00307675); fall_capacitance : 0.00262565; - fall_capacitance_range (0.00262565, 0.00262565); + fall_capacitance_range (0.00245097, 0.00279403); } } cell (sg13g2_and4_2) { area : 16.3296; - cell_footprint : "AND4"; + cell_footprint : "and4"; cell_leakage_power : 515.199; leakage_power () { value : 518; @@ -8008,41 +8008,41 @@ library (sg13g2_stdcell_fast_1p32V_m40C) { max_transition : 2.5074; capacitance : 0.00255276; rise_capacitance : 0.00249592; - rise_capacitance_range (0.00249592, 0.00249592); + rise_capacitance_range (0.00231404, 0.00261926); fall_capacitance : 0.00260959; - fall_capacitance_range (0.00260959, 0.00260959); + fall_capacitance_range (0.00227941, 0.00292803); } pin (B) { direction : "input"; max_transition : 2.5074; capacitance : 0.00268782; rise_capacitance : 0.00271574; - rise_capacitance_range (0.00271574, 0.00271574); + rise_capacitance_range (0.00233481, 0.00293959); fall_capacitance : 0.00265991; - fall_capacitance_range (0.00265991, 0.00265991); + fall_capacitance_range (0.00237616, 0.00292091); } pin (C) { direction : "input"; max_transition : 2.5074; capacitance : 0.00268695; rise_capacitance : 0.00274222; - rise_capacitance_range (0.00274222, 0.00274222); + rise_capacitance_range (0.00235179, 0.00299668); fall_capacitance : 0.00263169; - fall_capacitance_range (0.00263169, 0.00263169); + fall_capacitance_range (0.00240484, 0.00284267); } pin (D) { direction : "input"; max_transition : 2.5074; capacitance : 0.00269743; rise_capacitance : 0.00278131; - rise_capacitance_range (0.00278131, 0.00278131); + rise_capacitance_range (0.00239114, 0.00306387); fall_capacitance : 0.00261355; - fall_capacitance_range (0.00261355, 0.00261355); + fall_capacitance_range (0.0024575, 0.00277128); } } cell (sg13g2_antennanp) { area : 5.4432; - cell_footprint : "NP_ant"; + cell_footprint : "antennanp"; cell_leakage_power : 5.22716; dont_touch : true; dont_use : true; @@ -8059,9 +8059,9 @@ library (sg13g2_stdcell_fast_1p32V_m40C) { max_transition : 2.5074; capacitance : 0.00104572; rise_capacitance : 0.00101806; - rise_capacitance_range (0.00101806, 0.00101806); + rise_capacitance_range (0.000260085, 0.00160583); fall_capacitance : 0.00107338; - fall_capacitance_range (0.00107338, 0.00107338); + fall_capacitance_range (0.000265031, 0.00168402); internal_power () { rise_power (passive_POWER_7x1ds1) { index_1 ("0.0186, 0.0966, 0.174, 0.3294, 0.6408, 1.263, 2.5074"); @@ -8080,7 +8080,7 @@ library (sg13g2_stdcell_fast_1p32V_m40C) { } cell (sg13g2_buf_1) { area : 7.2576; - cell_footprint : "BU"; + cell_footprint : "buf"; cell_leakage_power : 203.405; leakage_power () { value : 216.125; @@ -8187,14 +8187,14 @@ library (sg13g2_stdcell_fast_1p32V_m40C) { max_transition : 2.5074; capacitance : 0.00244642; rise_capacitance : 0.00246791; - rise_capacitance_range (0.00246791, 0.00246791); + rise_capacitance_range (0.00220853, 0.00265597); fall_capacitance : 0.00242494; - fall_capacitance_range (0.00242494, 0.00242494); + fall_capacitance_range (0.00217873, 0.00265556); } } cell (sg13g2_buf_16) { area : 45.36; - cell_footprint : "BU"; + cell_footprint : "buf"; cell_leakage_power : 2605.75; leakage_power () { value : 2211.69; @@ -8301,14 +8301,14 @@ library (sg13g2_stdcell_fast_1p32V_m40C) { max_transition : 2.5074; capacitance : 0.0184071; rise_capacitance : 0.0186318; - rise_capacitance_range (0.0186318, 0.0186318); + rise_capacitance_range (0.0168169, 0.020073); fall_capacitance : 0.0181823; - fall_capacitance_range (0.0181823, 0.0181823); + fall_capacitance_range (0.0164653, 0.0197439); } } cell (sg13g2_buf_2) { area : 9.072; - cell_footprint : "BU"; + cell_footprint : "buf"; cell_leakage_power : 338.853; leakage_power () { value : 385.622; @@ -8415,14 +8415,14 @@ library (sg13g2_stdcell_fast_1p32V_m40C) { max_transition : 2.5074; capacitance : 0.0028222; rise_capacitance : 0.00285593; - rise_capacitance_range (0.00285593, 0.00285593); + rise_capacitance_range (0.0025994, 0.00305631); fall_capacitance : 0.00278847; - fall_capacitance_range (0.00278847, 0.00278847); + fall_capacitance_range (0.00254155, 0.00302898); } } cell (sg13g2_buf_4) { area : 14.5152; - cell_footprint : "BU"; + cell_footprint : "buf"; cell_leakage_power : 620.309; leakage_power () { value : 499.66; @@ -8529,14 +8529,14 @@ library (sg13g2_stdcell_fast_1p32V_m40C) { max_transition : 2.5074; capacitance : 0.00399415; rise_capacitance : 0.00411337; - rise_capacitance_range (0.00411337, 0.00411337); + rise_capacitance_range (0.00382198, 0.00431211); fall_capacitance : 0.00387494; - fall_capacitance_range (0.00387494, 0.00387494); + fall_capacitance_range (0.00349062, 0.00433865); } } cell (sg13g2_buf_8) { area : 23.5872; - cell_footprint : "BU"; + cell_footprint : "buf"; cell_leakage_power : 1302.88; leakage_power () { value : 1105.84; @@ -8643,14 +8643,14 @@ library (sg13g2_stdcell_fast_1p32V_m40C) { max_transition : 2.5074; capacitance : 0.00924632; rise_capacitance : 0.00935971; - rise_capacitance_range (0.00935971, 0.00935971); + rise_capacitance_range (0.00850047, 0.0100676); fall_capacitance : 0.00913294; - fall_capacitance_range (0.00913294, 0.00913294); + fall_capacitance_range (0.00833326, 0.00990206); } } cell (sg13g2_decap_4) { area : 7.2576; - cell_footprint : "DECAP"; + cell_footprint : "decap"; cell_leakage_power : 1468.61; dont_touch : true; dont_use : true; @@ -8658,7 +8658,7 @@ library (sg13g2_stdcell_fast_1p32V_m40C) { } cell (sg13g2_decap_8) { area : 12.7008; - cell_footprint : "DECAP"; + cell_footprint : "decap"; cell_leakage_power : 2937.24; dont_touch : true; dont_use : true; @@ -8666,7 +8666,7 @@ library (sg13g2_stdcell_fast_1p32V_m40C) { } cell (sg13g2_dfrbp_1) { area : 52.6176; - cell_footprint : "dffrr"; + cell_footprint : "dfrbp"; cell_leakage_power : 1160.68; leakage_power () { value : 1011.37; @@ -8723,6 +8723,7 @@ library (sg13g2_stdcell_fast_1p32V_m40C) { max_capacitance : 0.3; timing () { related_pin : "CLK"; + sdf_edges : start_edge; timing_sense : non_unate; timing_type : rising_edge; cell_rise (TIMING_DELAY_7x7ds1) { @@ -8780,6 +8781,7 @@ library (sg13g2_stdcell_fast_1p32V_m40C) { } timing () { related_pin : "RESET_B"; + sdf_edges : start_edge; timing_sense : positive_unate; timing_type : clear; cell_fall (TIMING_DELAY_7x7ds1) { @@ -8867,6 +8869,7 @@ library (sg13g2_stdcell_fast_1p32V_m40C) { max_capacitance : 0.3; timing () { related_pin : "CLK"; + sdf_edges : start_edge; timing_sense : non_unate; timing_type : rising_edge; cell_rise (TIMING_DELAY_7x7ds1) { @@ -8924,6 +8927,7 @@ library (sg13g2_stdcell_fast_1p32V_m40C) { } timing () { related_pin : "RESET_B"; + sdf_edges : start_edge; timing_sense : negative_unate; timing_type : preset; cell_rise (TIMING_DELAY_7x7ds1) { @@ -9010,9 +9014,9 @@ library (sg13g2_stdcell_fast_1p32V_m40C) { max_transition : 2.5074; capacitance : 0.00301993; rise_capacitance : 0.00319101; - rise_capacitance_range (0.00319101, 0.00319101); + rise_capacitance_range (0.00288838, 0.0034315); fall_capacitance : 0.0027633; - fall_capacitance_range (0.0027633, 0.0027633); + fall_capacitance_range (0.0027633, 0.00338418); timing () { related_pin : "CLK"; timing_type : min_pulse_width; @@ -9138,11 +9142,12 @@ library (sg13g2_stdcell_fast_1p32V_m40C) { max_transition : 2.5074; capacitance : 0.00165161; rise_capacitance : 0.00150745; - rise_capacitance_range (0.00150745, 0.00150745); + rise_capacitance_range (0.00143943, 0.00175012); fall_capacitance : 0.00179576; - fall_capacitance_range (0.00179576, 0.00179576); + fall_capacitance_range (0.00179576, 0.00282118); timing () { related_pin : "CLK"; + sdf_edges : both_edges; timing_type : hold_rising; rise_constraint (CONSTRAINT_4x4) { index_1 ("0.0186, 0.51636, 1.263, 2.5074"); @@ -9167,6 +9172,7 @@ library (sg13g2_stdcell_fast_1p32V_m40C) { } timing () { related_pin : "CLK"; + sdf_edges : both_edges; timing_type : setup_rising; rise_constraint (CONSTRAINT_4x4) { index_1 ("0.0186, 0.51636, 1.263, 2.5074"); @@ -9254,11 +9260,12 @@ library (sg13g2_stdcell_fast_1p32V_m40C) { max_transition : 2.5074; capacitance : 0.0055191; rise_capacitance : 0.00572369; - rise_capacitance_range (0.00572369, 0.00572369); + rise_capacitance_range (0.00467934, 0.00672269); fall_capacitance : 0.00537296; - fall_capacitance_range (0.00537296, 0.00537296); + fall_capacitance_range (0.00495432, 0.0056584); timing () { related_pin : "CLK"; + sdf_edges : both_edges; timing_type : recovery_rising; rise_constraint (CONSTRAINT_4x4) { index_1 ("0.0186, 0.51636, 1.263, 2.5074"); @@ -9273,6 +9280,7 @@ library (sg13g2_stdcell_fast_1p32V_m40C) { } timing () { related_pin : "CLK"; + sdf_edges : both_edges; timing_type : removal_rising; rise_constraint (CONSTRAINT_4x4) { index_1 ("0.0186, 0.51636, 1.263, 2.5074"); @@ -9371,14 +9379,14 @@ library (sg13g2_stdcell_fast_1p32V_m40C) { } } ff (IQ,IQN) { - clear : "RESET_B'"; + clear : "!RESET_B"; clocked_on : "CLK"; next_state : "D"; } } cell (sg13g2_dfrbp_2) { area : 54.432; - cell_footprint : "dffrr"; + cell_footprint : "dfrbp"; cell_leakage_power : 1383.55; leakage_power () { value : 1239.15; @@ -9435,6 +9443,7 @@ library (sg13g2_stdcell_fast_1p32V_m40C) { max_capacitance : 0.6; timing () { related_pin : "CLK"; + sdf_edges : start_edge; timing_sense : non_unate; timing_type : rising_edge; cell_rise (TIMING_DELAY_7x7ds1) { @@ -9492,6 +9501,7 @@ library (sg13g2_stdcell_fast_1p32V_m40C) { } timing () { related_pin : "RESET_B"; + sdf_edges : start_edge; timing_sense : positive_unate; timing_type : clear; cell_fall (TIMING_DELAY_7x7ds1) { @@ -9579,6 +9589,7 @@ library (sg13g2_stdcell_fast_1p32V_m40C) { max_capacitance : 0.6; timing () { related_pin : "CLK"; + sdf_edges : start_edge; timing_sense : non_unate; timing_type : rising_edge; cell_rise (TIMING_DELAY_7x7ds1) { @@ -9636,6 +9647,7 @@ library (sg13g2_stdcell_fast_1p32V_m40C) { } timing () { related_pin : "RESET_B"; + sdf_edges : start_edge; timing_sense : negative_unate; timing_type : preset; cell_rise (TIMING_DELAY_7x7ds1) { @@ -9722,9 +9734,9 @@ library (sg13g2_stdcell_fast_1p32V_m40C) { max_transition : 2.5074; capacitance : 0.00302862; rise_capacitance : 0.00319973; - rise_capacitance_range (0.00319973, 0.00319973); + rise_capacitance_range (0.00289797, 0.00344007); fall_capacitance : 0.00277195; - fall_capacitance_range (0.00277195, 0.00277195); + fall_capacitance_range (0.00277195, 0.00339285); timing () { related_pin : "CLK"; timing_type : min_pulse_width; @@ -9850,11 +9862,12 @@ library (sg13g2_stdcell_fast_1p32V_m40C) { max_transition : 2.5074; capacitance : 0.00165542; rise_capacitance : 0.00151112; - rise_capacitance_range (0.00151112, 0.00151112); + rise_capacitance_range (0.00144174, 0.00175349); fall_capacitance : 0.00179972; - fall_capacitance_range (0.00179972, 0.00179972); + fall_capacitance_range (0.00179972, 0.00282516); timing () { related_pin : "CLK"; + sdf_edges : both_edges; timing_type : hold_rising; rise_constraint (CONSTRAINT_4x4) { index_1 ("0.0186, 0.51636, 1.263, 2.5074"); @@ -9879,6 +9892,7 @@ library (sg13g2_stdcell_fast_1p32V_m40C) { } timing () { related_pin : "CLK"; + sdf_edges : both_edges; timing_type : setup_rising; rise_constraint (CONSTRAINT_4x4) { index_1 ("0.0186, 0.51636, 1.263, 2.5074"); @@ -9966,11 +9980,12 @@ library (sg13g2_stdcell_fast_1p32V_m40C) { max_transition : 2.5074; capacitance : 0.00556976; rise_capacitance : 0.00577329; - rise_capacitance_range (0.00577329, 0.00577329); + rise_capacitance_range (0.00471828, 0.00678095); fall_capacitance : 0.00542438; - fall_capacitance_range (0.00542438, 0.00542438); + fall_capacitance_range (0.00499965, 0.00571616); timing () { related_pin : "CLK"; + sdf_edges : both_edges; timing_type : recovery_rising; rise_constraint (CONSTRAINT_4x4) { index_1 ("0.0186, 0.51636, 1.263, 2.5074"); @@ -9985,6 +10000,7 @@ library (sg13g2_stdcell_fast_1p32V_m40C) { } timing () { related_pin : "CLK"; + sdf_edges : both_edges; timing_type : removal_rising; rise_constraint (CONSTRAINT_4x4) { index_1 ("0.0186, 0.51636, 1.263, 2.5074"); @@ -10083,7 +10099,7 @@ library (sg13g2_stdcell_fast_1p32V_m40C) { } } ff (IQ,IQN) { - clear : "RESET_B'"; + clear : "!RESET_B"; clocked_on : "CLK"; next_state : "D"; } @@ -10097,7 +10113,7 @@ library (sg13g2_stdcell_fast_1p32V_m40C) { when : "!CLK&!D&!RESET_B&!Q"; } leakage_power () { - value : 915.629; + value : 915.63; when : "!CLK&D&!RESET_B&!Q"; } leakage_power () { @@ -10105,7 +10121,7 @@ library (sg13g2_stdcell_fast_1p32V_m40C) { when : "CLK&!D&!RESET_B&!Q"; } leakage_power () { - value : 970.356; + value : 970.357; when : "CLK&D&!RESET_B&!Q"; } leakage_power () { @@ -10113,7 +10129,7 @@ library (sg13g2_stdcell_fast_1p32V_m40C) { when : "!CLK&!D&RESET_B&Q"; } leakage_power () { - value : 1034.62; + value : 1034.63; when : "!CLK&!D&RESET_B&!Q"; } leakage_power () { @@ -10147,89 +10163,91 @@ library (sg13g2_stdcell_fast_1p32V_m40C) { max_capacitance : 0.3; timing () { related_pin : "CLK"; + sdf_edges : start_edge; timing_sense : non_unate; timing_type : rising_edge; cell_rise (TIMING_DELAY_7x7ds1) { index_1 ("0.0186, 0.0966, 0.174, 0.3294, 0.6408, 1.263, 2.5074"); index_2 ("0.001, 0.0234, 0.039, 0.0648, 0.108, 0.18, 0.3"); values ( \ - "0.105832, 0.148145, 0.17582, 0.221333, 0.297392, 0.424129, 0.635228", \ - "0.135185, 0.177548, 0.205267, 0.250726, 0.326773, 0.453498, 0.664624", \ - "0.154997, 0.197306, 0.224979, 0.270501, 0.346531, 0.473204, 0.684483", \ - "0.182048, 0.224405, 0.252091, 0.297566, 0.37363, 0.500309, 0.711283", \ - "0.219947, 0.26244, 0.290103, 0.335459, 0.411689, 0.538363, 0.749308", \ - "0.272795, 0.31524, 0.342919, 0.388501, 0.464551, 0.591262, 0.802243", \ - "0.347388, 0.390165, 0.417822, 0.463359, 0.539411, 0.666131, 0.877272" \ + "0.105849, 0.148149, 0.175809, 0.221271, 0.297299, 0.423995, 0.634967", \ + "0.135208, 0.177468, 0.205145, 0.250646, 0.326652, 0.453305, 0.66435", \ + "0.155009, 0.197298, 0.224973, 0.270458, 0.346454, 0.47306, 0.68425", \ + "0.182091, 0.224398, 0.252071, 0.297525, 0.373553, 0.500172, 0.711047", \ + "0.21996, 0.262435, 0.290084, 0.33542, 0.411465, 0.538228, 0.749232", \ + "0.272802, 0.315238, 0.342896, 0.388457, 0.464471, 0.591122, 0.802004", \ + "0.347386, 0.39018, 0.417822, 0.46334, 0.539351, 0.66601, 0.877052" \ ); } rise_transition (TIMING_DELAY_7x7ds1) { index_1 ("0.0186, 0.0966, 0.174, 0.3294, 0.6408, 1.263, 2.5074"); index_2 ("0.001, 0.0234, 0.039, 0.0648, 0.108, 0.18, 0.3"); values ( \ - "0.0115855, 0.0664379, 0.106523, 0.173011, 0.284448, 0.470325, 0.780089", \ - "0.011599, 0.0664389, 0.106531, 0.173012, 0.284449, 0.470648, 0.78049", \ - "0.0116569, 0.0664458, 0.106532, 0.173013, 0.28445, 0.470649, 0.780491", \ - "0.0117305, 0.0664468, 0.106538, 0.173014, 0.284451, 0.47065, 0.780492", \ - "0.011993, 0.0664839, 0.106566, 0.173015, 0.284452, 0.470651, 0.780493", \ - "0.012495, 0.066551, 0.106588, 0.173021, 0.284486, 0.470652, 0.780494", \ - "0.013622, 0.066731, 0.106682, 0.17312, 0.284516, 0.470653, 0.780495" \ + "0.0115828, 0.0664086, 0.106481, 0.172913, 0.284268, 0.470102, 0.779859", \ + "0.0116165, 0.0664096, 0.106484, 0.172921, 0.284381, 0.470216, 0.780144", \ + "0.0116554, 0.0664195, 0.106485, 0.172926, 0.284382, 0.470217, 0.780145", \ + "0.0117859, 0.0664205, 0.106492, 0.172927, 0.284383, 0.470218, 0.780146", \ + "0.0119907, 0.0664563, 0.106519, 0.172928, 0.284384, 0.470219, 0.780147", \ + "0.012493, 0.066533, 0.106542, 0.172945, 0.284385, 0.47022, 0.780148", \ + "0.01358, 0.066702, 0.106633, 0.173067, 0.284386, 0.470221, 0.780149" \ ); } cell_fall (TIMING_DELAY_7x7ds1) { index_1 ("0.0186, 0.0966, 0.174, 0.3294, 0.6408, 1.263, 2.5074"); index_2 ("0.001, 0.0234, 0.039, 0.0648, 0.108, 0.18, 0.3"); values ( \ - "0.105984, 0.143013, 0.166326, 0.204533, 0.268399, 0.374794, 0.552125", \ - "0.134982, 0.172024, 0.195287, 0.233524, 0.297372, 0.403749, 0.581354", \ - "0.154105, 0.191126, 0.214431, 0.25262, 0.316472, 0.422839, 0.600069", \ - "0.179331, 0.21632, 0.239598, 0.277816, 0.34168, 0.448009, 0.625193", \ - "0.213528, 0.250817, 0.27381, 0.31203, 0.375899, 0.482616, 0.659421", \ - "0.260842, 0.297825, 0.321112, 0.359327, 0.423212, 0.529567, 0.706764", \ - "0.32355, 0.36053, 0.383822, 0.42203, 0.485915, 0.592277, 0.769506" \ + "0.105995, 0.143013, 0.166293, 0.204532, 0.268373, 0.37476, 0.552114", \ + "0.134969, 0.172001, 0.195283, 0.233504, 0.297348, 0.403731, 0.581335", \ + "0.154091, 0.191116, 0.214422, 0.252612, 0.316464, 0.422833, 0.600063", \ + "0.179241, 0.216256, 0.239567, 0.277757, 0.341628, 0.44795, 0.625153", \ + "0.213807, 0.250812, 0.273803, 0.312025, 0.37619, 0.482321, 0.659725", \ + "0.260837, 0.297821, 0.321109, 0.359325, 0.423212, 0.529569, 0.706798", \ + "0.323557, 0.360537, 0.383831, 0.422041, 0.485928, 0.592292, 0.769522" \ ); } fall_transition (TIMING_DELAY_7x7ds1) { index_1 ("0.0186, 0.0966, 0.174, 0.3294, 0.6408, 1.263, 2.5074"); index_2 ("0.001, 0.0234, 0.039, 0.0648, 0.108, 0.18, 0.3"); values ( \ - "0.0100573, 0.0539676, 0.0857779, 0.138686, 0.227568, 0.375701, 0.622741", \ - "0.0100583, 0.0539686, 0.0857789, 0.138699, 0.227569, 0.37591, 0.623057", \ - "0.0100593, 0.0539696, 0.0857799, 0.1387, 0.22757, 0.375911, 0.624116", \ - "0.0100603, 0.0539706, 0.0857809, 0.138701, 0.227571, 0.375912, 0.624117", \ - "0.0100613, 0.0539716, 0.0857819, 0.138706, 0.227572, 0.375913, 0.624118", \ - "0.0100623, 0.0539726, 0.0857829, 0.138707, 0.227573, 0.375914, 0.624119", \ - "0.010067, 0.0539736, 0.0857839, 0.138708, 0.227574, 0.375915, 0.62412" \ + "0.0100542, 0.0539627, 0.085776, 0.138679, 0.227594, 0.375797, 0.62274", \ + "0.0100552, 0.053963, 0.085777, 0.138697, 0.227595, 0.375911, 0.623271", \ + "0.0100562, 0.0539671, 0.085778, 0.138698, 0.227611, 0.375912, 0.624093", \ + "0.0100572, 0.0539702, 0.085779, 0.138699, 0.227612, 0.375913, 0.624094", \ + "0.0100582, 0.0539712, 0.08578, 0.138706, 0.227613, 0.375914, 0.624095", \ + "0.0100592, 0.0539722, 0.085781, 0.138707, 0.227614, 0.375915, 0.624096", \ + "0.010064, 0.0539732, 0.085782, 0.138708, 0.227615, 0.375916, 0.624097" \ ); } } timing () { related_pin : "RESET_B"; + sdf_edges : start_edge; timing_sense : positive_unate; timing_type : clear; cell_fall (TIMING_DELAY_7x7ds1) { index_1 ("0.0186, 0.0966, 0.174, 0.3294, 0.6408, 1.263, 2.5074"); index_2 ("0.001, 0.0234, 0.039, 0.0648, 0.108, 0.18, 0.3"); values ( \ - "0.147899, 0.184849, 0.208153, 0.246393, 0.310343, 0.416728, 0.593992", \ - "0.18553, 0.222452, 0.245759, 0.284027, 0.347903, 0.454357, 0.631987", \ - "0.21296, 0.249897, 0.273168, 0.311411, 0.375309, 0.481729, 0.65903", \ - "0.254144, 0.291089, 0.314388, 0.352624, 0.416533, 0.522902, 0.700121", \ - "0.311869, 0.348871, 0.37217, 0.410451, 0.474331, 0.580702, 0.757931", \ - "0.392279, 0.429273, 0.452544, 0.490838, 0.554805, 0.661158, 0.838516", \ - "0.501428, 0.538552, 0.561875, 0.600134, 0.664123, 0.770524, 0.947855" \ + "0.147876, 0.184856, 0.208164, 0.246407, 0.310361, 0.416716, 0.594097", \ + "0.185558, 0.222512, 0.245765, 0.284048, 0.347993, 0.45436, 0.632034", \ + "0.21299, 0.249911, 0.273183, 0.311428, 0.375327, 0.481749, 0.65905", \ + "0.254127, 0.291072, 0.314383, 0.352663, 0.41652, 0.522888, 0.700111", \ + "0.311855, 0.348858, 0.372159, 0.410439, 0.474321, 0.580694, 0.757924", \ + "0.392265, 0.429259, 0.45253, 0.490825, 0.554794, 0.661149, 0.838509", \ + "0.501413, 0.538536, 0.56186, 0.600105, 0.66411, 0.770513, 0.947835" \ ); } fall_transition (TIMING_DELAY_7x7ds1) { index_1 ("0.0186, 0.0966, 0.174, 0.3294, 0.6408, 1.263, 2.5074"); index_2 ("0.001, 0.0234, 0.039, 0.0648, 0.108, 0.18, 0.3"); values ( \ - "0.0099752, 0.0538576, 0.0856855, 0.138618, 0.227551, 0.375813, 0.622902", \ - "0.0099769, 0.0538748, 0.0856865, 0.138657, 0.227887, 0.375953, 0.623425", \ - "0.0100134, 0.0538806, 0.0856875, 0.138658, 0.227888, 0.375954, 0.624325", \ - "0.0100587, 0.0538852, 0.0856921, 0.138659, 0.227889, 0.375955, 0.624326", \ - "0.0101338, 0.0539142, 0.0857023, 0.138666, 0.22789, 0.375956, 0.624327", \ - "0.010271, 0.053961, 0.085722, 0.138667, 0.227891, 0.375957, 0.624328", \ - "0.010466, 0.054015, 0.085761, 0.138668, 0.227892, 0.375958, 0.624329" \ + "0.0099646, 0.0538899, 0.0856857, 0.138617, 0.22755, 0.375812, 0.62274", \ + "0.0099807, 0.0538909, 0.0856867, 0.138618, 0.227891, 0.375952, 0.623368", \ + "0.0100241, 0.0538919, 0.0856877, 0.138619, 0.227892, 0.375953, 0.624322", \ + "0.0100538, 0.0538929, 0.0856887, 0.138707, 0.227893, 0.375954, 0.624323", \ + "0.0101318, 0.0539126, 0.0857029, 0.138708, 0.227894, 0.375955, 0.624324", \ + "0.010269, 0.053959, 0.085721, 0.138709, 0.227895, 0.375956, 0.624325", \ + "0.010464, 0.054014, 0.085756, 0.13871, 0.227896, 0.375957, 0.624326" \ ); } } @@ -10239,26 +10257,26 @@ library (sg13g2_stdcell_fast_1p32V_m40C) { index_1 ("0.0186, 0.0966, 0.174, 0.3294, 0.6408, 1.263, 2.5074"); index_2 ("0.001, 0.0234, 0.039, 0.0648, 0.108, 0.18, 0.3"); values ( \ - "0.0312254, 0.0317033, 0.0317332, 0.0316906, 0.0315724, 0.0313129, 0.0312952", \ - "0.0309848, 0.0314463, 0.0315446, 0.0314227, 0.0313042, 0.0311356, 0.0310621", \ - "0.0316622, 0.0321173, 0.0321161, 0.0321412, 0.0322499, 0.031739, 0.0316821", \ - "0.0330957, 0.0335767, 0.0336399, 0.0336025, 0.0334188, 0.03342, 0.0330769", \ - "0.0365801, 0.0369556, 0.0370423, 0.0370926, 0.0371083, 0.0367968, 0.0366594", \ - "0.0444428, 0.0448245, 0.0449124, 0.0448822, 0.0449516, 0.0449308, 0.044785", \ - "0.0612115, 0.0615084, 0.061502, 0.0614883, 0.061579, 0.0615112, 0.0613783" \ + "0.031227, 0.0317143, 0.0317248, 0.031708, 0.0315665, 0.0313274, 0.0312469", \ + "0.0309814, 0.0314337, 0.0315249, 0.0314158, 0.0317828, 0.0310996, 0.0310329", \ + "0.0316676, 0.0321204, 0.0320898, 0.0321153, 0.0322427, 0.0317225, 0.0316765", \ + "0.0330985, 0.0335808, 0.033632, 0.0336078, 0.0334105, 0.0336562, 0.0330605", \ + "0.0365807, 0.0369562, 0.0370483, 0.0371179, 0.0371548, 0.0368534, 0.0366972", \ + "0.0444447, 0.0448194, 0.0449172, 0.0448887, 0.0449386, 0.0449504, 0.0447748", \ + "0.0612075, 0.061514, 0.061518, 0.0614922, 0.0615921, 0.061512, 0.061388" \ ); } fall_power (POWER_7x7ds1) { index_1 ("0.0186, 0.0966, 0.174, 0.3294, 0.6408, 1.263, 2.5074"); index_2 ("0.001, 0.0234, 0.039, 0.0648, 0.108, 0.18, 0.3"); values ( \ - "0.0322811, 0.0328693, 0.0328905, 0.0328463, 0.03272, 0.0325018, 0.032044", \ - "0.0323535, 0.0328867, 0.0329263, 0.0329804, 0.0328414, 0.0325656, 0.0321607", \ - "0.033079, 0.0336784, 0.0337099, 0.0335877, 0.0336775, 0.0335122, 0.0331199", \ - "0.034636, 0.0351843, 0.0352775, 0.0352874, 0.0351597, 0.0349858, 0.0351047", \ - "0.0381599, 0.0387536, 0.0387653, 0.0387975, 0.0388625, 0.0387695, 0.0378928", \ - "0.0457985, 0.0463482, 0.0463888, 0.0464552, 0.0463405, 0.0462937, 0.0464392", \ - "0.0619964, 0.0625883, 0.0625788, 0.0624703, 0.0624376, 0.0625044, 0.0624654" \ + "0.0322819, 0.0328769, 0.0328966, 0.0328623, 0.0327215, 0.0325295, 0.0320515", \ + "0.0323122, 0.0328692, 0.0328915, 0.0329654, 0.0328211, 0.032555, 0.03217", \ + "0.0330807, 0.0336837, 0.0337289, 0.0335936, 0.0337014, 0.0335169, 0.0330861", \ + "0.0346006, 0.0351795, 0.0352806, 0.0352934, 0.0351585, 0.0349588, 0.0347809", \ + "0.038172, 0.0387538, 0.0387729, 0.0388049, 0.0388676, 0.0387652, 0.0380535", \ + "0.0458005, 0.0463533, 0.0463939, 0.0464462, 0.0463585, 0.0462957, 0.0464157", \ + "0.0620112, 0.0625959, 0.0625875, 0.062486, 0.0624504, 0.0625085, 0.0624549" \ ); } } @@ -10273,13 +10291,13 @@ library (sg13g2_stdcell_fast_1p32V_m40C) { index_1 ("0.0186, 0.0966, 0.174, 0.3294, 0.6408, 1.263, 2.5074"); index_2 ("0.001, 0.0234, 0.039, 0.0648, 0.108, 0.18, 0.3"); values ( \ - "0.020728, 0.0212753, 0.0212992, 0.0212381, 0.021142, 0.0209392, 0.0204987", \ - "0.0207028, 0.0212403, 0.0213411, 0.0213087, 0.0211894, 0.0209389, 0.0206163", \ - "0.0211196, 0.0216243, 0.0216306, 0.0216457, 0.0218655, 0.0212818, 0.0211859", \ - "0.0220113, 0.0225522, 0.0226331, 0.0225895, 0.0223696, 0.0224404, 0.0217193", \ - "0.0239765, 0.0245439, 0.0245426, 0.024667, 0.0246306, 0.0244321, 0.0238498", \ - "0.0278678, 0.0283987, 0.0283675, 0.0284106, 0.0284476, 0.0285051, 0.0285026", \ - "0.0347696, 0.0352619, 0.035282, 0.0353033, 0.0353351, 0.0352375, 0.0351506" \ + "0.0207221, 0.0212793, 0.0213069, 0.0212553, 0.021163, 0.0209389, 0.0205033", \ + "0.0207013, 0.0212453, 0.0213411, 0.0212833, 0.0212125, 0.0209376, 0.0206455", \ + "0.0211321, 0.0216338, 0.0216388, 0.0216572, 0.0218776, 0.0212711, 0.021198", \ + "0.0220165, 0.0225526, 0.0226418, 0.0226392, 0.0223699, 0.0224443, 0.021727", \ + "0.0239757, 0.0245415, 0.0245456, 0.0246672, 0.0246647, 0.0244422, 0.0238545", \ + "0.0278728, 0.0284038, 0.0283739, 0.0284156, 0.0284491, 0.0284826, 0.0284941", \ + "0.0347702, 0.0352637, 0.0352844, 0.0352997, 0.0353444, 0.0352449, 0.0352481" \ ); } } @@ -10288,11 +10306,11 @@ library (sg13g2_stdcell_fast_1p32V_m40C) { clock : true; direction : "input"; max_transition : 2.5074; - capacitance : 0.00299338; - rise_capacitance : 0.00319043; - rise_capacitance_range (0.00319043, 0.00319043); - fall_capacitance : 0.00276349; - fall_capacitance_range (0.00276349, 0.00276349); + capacitance : 0.00299333; + rise_capacitance : 0.00319022; + rise_capacitance_range (0.00288864, 0.00343152); + fall_capacitance : 0.00276362; + fall_capacitance_range (0.00276362, 0.00338424); timing () { related_pin : "CLK"; timing_type : min_pulse_width; @@ -10314,13 +10332,13 @@ library (sg13g2_stdcell_fast_1p32V_m40C) { rise_power (passive_POWER_7x1ds1) { index_1 ("0.0186, 0.0966, 0.174, 0.3294, 0.6408, 1.263, 2.5074"); values ( \ - "0.0131281, 0.0130292, 0.0136506, 0.0150742, 0.018364, 0.0257381, 0.0417512" \ + "0.013126, 0.0130209, 0.0136515, 0.0150743, 0.0183649, 0.0257395, 0.0417534" \ ); } fall_power (passive_POWER_7x1ds1) { index_1 ("0.0186, 0.0966, 0.174, 0.3294, 0.6408, 1.263, 2.5074"); values ( \ - "0.0256871, 0.0256157, 0.0262599, 0.0278715, 0.0312167, 0.0388923, 0.0552797" \ + "0.0256911, 0.0256205, 0.0262598, 0.0278721, 0.031218, 0.038894, 0.055281" \ ); } } @@ -10334,7 +10352,7 @@ library (sg13g2_stdcell_fast_1p32V_m40C) { fall_power (passive_POWER_7x1ds1) { index_1 ("0.0186, 0.0966, 0.174, 0.3294, 0.6408, 1.263, 2.5074"); values ( \ - "0.0252795, 0.0252463, 0.0258233, 0.0274417, 0.0308141, 0.0384413, 0.0546963" \ + "0.0252797, 0.0252133, 0.0258233, 0.0274418, 0.030817, 0.0384407, 0.0546967" \ ); } } @@ -10343,13 +10361,13 @@ library (sg13g2_stdcell_fast_1p32V_m40C) { rise_power (passive_POWER_7x1ds1) { index_1 ("0.0186, 0.0966, 0.174, 0.3294, 0.6408, 1.263, 2.5074"); values ( \ - "0.0138002, 0.0136935, 0.0143269, 0.0156971, 0.0189986, 0.0263402, 0.0422153" \ + "0.0137946, 0.0136823, 0.0143273, 0.0156981, 0.0189973, 0.0263417, 0.0422179" \ ); } fall_power (passive_POWER_7x1ds1) { index_1 ("0.0186, 0.0966, 0.174, 0.3294, 0.6408, 1.263, 2.5074"); values ( \ - "0.0129403, 0.0129656, 0.013559, 0.0151378, 0.0184095, 0.0257543, 0.0414308" \ + "0.012938, 0.0129612, 0.0135588, 0.015138, 0.0184097, 0.0257549, 0.0414327" \ ); } } @@ -10363,7 +10381,7 @@ library (sg13g2_stdcell_fast_1p32V_m40C) { fall_power (passive_POWER_7x1ds1) { index_1 ("0.0186, 0.0966, 0.174, 0.3294, 0.6408, 1.263, 2.5074"); values ( \ - "0.0448223, 0.0448046, 0.0451378, 0.04665, 0.0499457, 0.0573946, 0.07288" \ + "0.0448064, 0.0448043, 0.04514, 0.0466524, 0.0499474, 0.0573965, 0.0728863" \ ); } } @@ -10372,13 +10390,13 @@ library (sg13g2_stdcell_fast_1p32V_m40C) { rise_power (passive_POWER_7x1ds1) { index_1 ("0.0186, 0.0966, 0.174, 0.3294, 0.6408, 1.263, 2.5074"); values ( \ - "0.0128724, 0.0127624, 0.0134111, 0.0147845, 0.0180807, 0.0254407, 0.0414521" \ + "0.0128719, 0.0127498, 0.0134107, 0.0147846, 0.0180818, 0.0254422, 0.0414543" \ ); } fall_power (passive_POWER_7x1ds1) { index_1 ("0.0186, 0.0966, 0.174, 0.3294, 0.6408, 1.263, 2.5074"); values ( \ - "0.0129128, 0.0129459, 0.0135423, 0.0151298, 0.0183946, 0.0257531, 0.0414368" \ + "0.0129175, 0.0129596, 0.0135429, 0.0151275, 0.0183956, 0.0257594, 0.041439" \ ); } } @@ -10387,13 +10405,13 @@ library (sg13g2_stdcell_fast_1p32V_m40C) { rise_power (passive_POWER_7x1ds1) { index_1 ("0.0186, 0.0966, 0.174, 0.3294, 0.6408, 1.263, 2.5074"); values ( \ - "0.0138387, 0.0137342, 0.0143553, 0.0157252, 0.0190227, 0.0263659, 0.0422403" \ + "0.0138223, 0.0137274, 0.0143575, 0.0157254, 0.0190224, 0.0263681, 0.042243" \ ); } fall_power (passive_POWER_7x1ds1) { index_1 ("0.0186, 0.0966, 0.174, 0.3294, 0.6408, 1.263, 2.5074"); values ( \ - "0.0129476, 0.0129567, 0.0135521, 0.0151318, 0.0184037, 0.0257485, 0.0414283" \ + "0.0129329, 0.0129599, 0.0135528, 0.015132, 0.0184056, 0.0257502, 0.0414312" \ ); } } @@ -10401,13 +10419,13 @@ library (sg13g2_stdcell_fast_1p32V_m40C) { rise_power (passive_POWER_7x1ds1) { index_1 ("0.0186, 0.0966, 0.174, 0.3294, 0.6408, 1.263, 2.5074"); values ( \ - "0.0131281, 0.0130292, 0.0136506, 0.0150742, 0.018364, 0.0257381, 0.0417512" \ + "0.013126, 0.0130209, 0.0136515, 0.0150743, 0.0183649, 0.0257395, 0.0417534" \ ); } fall_power (passive_POWER_7x1ds1) { index_1 ("0.0186, 0.0966, 0.174, 0.3294, 0.6408, 1.263, 2.5074"); values ( \ - "0.0252795, 0.0252463, 0.0258233, 0.0274417, 0.0308141, 0.0384413, 0.0546963" \ + "0.0252797, 0.0252133, 0.0258233, 0.0274418, 0.030817, 0.0384407, 0.0546967" \ ); } } @@ -10416,19 +10434,20 @@ library (sg13g2_stdcell_fast_1p32V_m40C) { direction : "input"; nextstate_type : "data"; max_transition : 2.5074; - capacitance : 0.0015098; - rise_capacitance : 0.00149625; - rise_capacitance_range (0.00149625, 0.00149625); - fall_capacitance : 0.00152335; - fall_capacitance_range (0.00152335, 0.00152335); + capacitance : 0.00150978; + rise_capacitance : 0.00149621; + rise_capacitance_range (0.00143707, 0.00175012); + fall_capacitance : 0.00152336; + fall_capacitance_range (0.00152336, 0.00182997); timing () { related_pin : "CLK"; + sdf_edges : both_edges; timing_type : hold_rising; rise_constraint (CONSTRAINT_4x4) { index_1 ("0.0186, 0.51636, 1.263, 2.5074"); index_2 ("0.0186, 0.51636, 1.263, 2.5074"); values ( \ - "-0.0415682, -0.000246497, 0.0215733, 0.0504408", \ + "-0.0415682, -0.000246497, 0.0215733, 0.0531392", \ "-0.144511, -0.101858, -0.0777053, -0.0488843", \ "-0.191311, -0.160934, -0.140315, -0.106057", \ "-0.239326, -0.223267, -0.207512, -0.180044" \ @@ -10447,6 +10466,7 @@ library (sg13g2_stdcell_fast_1p32V_m40C) { } timing () { related_pin : "CLK"; + sdf_edges : both_edges; timing_type : setup_rising; rise_constraint (CONSTRAINT_4x4) { index_1 ("0.0186, 0.51636, 1.263, 2.5074"); @@ -10454,7 +10474,7 @@ library (sg13g2_stdcell_fast_1p32V_m40C) { values ( \ "0.0758009, 0.0202131, -0.00614259, -0.036949", \ "0.196924, 0.129869, 0.0986846, 0.0653783", \ - "0.268464, 0.197648, 0.1646, 0.128657", \ + "0.268464, 0.195026, 0.1646, 0.128657", \ "0.349959, 0.272749, 0.241412, 0.206608" \ ); } @@ -10474,13 +10494,13 @@ library (sg13g2_stdcell_fast_1p32V_m40C) { rise_power (passive_POWER_7x1ds1) { index_1 ("0.0186, 0.0966, 0.174, 0.3294, 0.6408, 1.263, 2.5074"); values ( \ - "0.00165616, 0.0016993, 0.00194224, 0.00255563, 0.00394371, 0.00680715, 0.0128644" \ + "0.00165488, 0.00169989, 0.0019421, 0.00255551, 0.00394302, 0.0068072, 0.0128636" \ ); } fall_power (passive_POWER_7x1ds1) { index_1 ("0.0186, 0.0966, 0.174, 0.3294, 0.6408, 1.263, 2.5074"); values ( \ - "0.00129485, 0.00137965, 0.00163785, 0.00227559, 0.00365754, 0.00657316, 0.0126901" \ + "0.00129194, 0.00137659, 0.00163826, 0.00227615, 0.00365827, 0.00657348, 0.0126901" \ ); } } @@ -10489,13 +10509,13 @@ library (sg13g2_stdcell_fast_1p32V_m40C) { rise_power (passive_POWER_7x1ds1) { index_1 ("0.0186, 0.0966, 0.174, 0.3294, 0.6408, 1.263, 2.5074"); values ( \ - "0.0143843, 0.0144121, 0.0146952, 0.0151818, 0.0166166, 0.0198282, 0.0268039" \ + "0.0143885, 0.0144297, 0.014695, 0.0151821, 0.0166163, 0.0198289, 0.0268014" \ ); } fall_power (passive_POWER_7x1ds1) { index_1 ("0.0186, 0.0966, 0.174, 0.3294, 0.6408, 1.263, 2.5074"); values ( \ - "0.0108404, 0.010783, 0.0110599, 0.0116902, 0.0132365, 0.0165656, 0.0236874" \ + "0.0108412, 0.0107865, 0.0110564, 0.0116903, 0.0132367, 0.0165654, 0.0236871" \ ); } } @@ -10504,13 +10524,13 @@ library (sg13g2_stdcell_fast_1p32V_m40C) { rise_power (passive_POWER_7x1ds1) { index_1 ("0.0186, 0.0966, 0.174, 0.3294, 0.6408, 1.263, 2.5074"); values ( \ - "-6.2766e-05, -5.85679e-05, -5.79746e-05, -5.76726e-05, -5.79695e-05, -5.87536e-05, -5.66567e-05" \ + "-6.2405e-05, -5.85053e-05, -5.84439e-05, -5.75247e-05, -5.80417e-05, -5.80209e-05, -5.76432e-05" \ ); } fall_power (passive_POWER_7x1ds1) { index_1 ("0.0186, 0.0966, 0.174, 0.3294, 0.6408, 1.263, 2.5074"); values ( \ - "0.000305809, 0.00030645, 0.000307033, 0.000306071, 0.000307879, 0.000308476, 0.000309438" \ + "0.00030569, 0.000306425, 0.00030714, 0.000306107, 0.000307886, 0.000308545, 0.000309434" \ ); } } @@ -10518,13 +10538,13 @@ library (sg13g2_stdcell_fast_1p32V_m40C) { rise_power (passive_POWER_7x1ds1) { index_1 ("0.0186, 0.0966, 0.174, 0.3294, 0.6408, 1.263, 2.5074"); values ( \ - "0.00165616, 0.0016993, 0.00194224, 0.00255563, 0.00394371, 0.00680715, 0.0128644" \ + "0.00165488, 0.00169989, 0.0019421, 0.00255551, 0.00394302, 0.0068072, 0.0128636" \ ); } fall_power (passive_POWER_7x1ds1) { index_1 ("0.0186, 0.0966, 0.174, 0.3294, 0.6408, 1.263, 2.5074"); values ( \ - "0.00129485, 0.00137965, 0.00163785, 0.00227559, 0.00365754, 0.00657316, 0.0126901" \ + "0.00129194, 0.00137659, 0.00163826, 0.00227615, 0.00365827, 0.00657348, 0.0126901" \ ); } } @@ -10532,13 +10552,14 @@ library (sg13g2_stdcell_fast_1p32V_m40C) { pin (RESET_B) { direction : "input"; max_transition : 2.5074; - capacitance : 0.0054563; - rise_capacitance : 0.00555711; - rise_capacitance_range (0.00555711, 0.00555711); - fall_capacitance : 0.00537229; - fall_capacitance_range (0.00537229, 0.00537229); + capacitance : 0.00545659; + rise_capacitance : 0.00555736; + rise_capacitance_range (0.00467928, 0.00642922); + fall_capacitance : 0.00537262; + fall_capacitance_range (0.00495355, 0.00563074); timing () { related_pin : "CLK"; + sdf_edges : both_edges; timing_type : recovery_rising; rise_constraint (CONSTRAINT_4x4) { index_1 ("0.0186, 0.51636, 1.263, 2.5074"); @@ -10546,13 +10567,14 @@ library (sg13g2_stdcell_fast_1p32V_m40C) { values ( \ "0.0806913, 0.0252047, -0.000999033, -0.0315523", \ "0.196924, 0.132416, 0.106552, 0.0736253", \ - "0.286466, 0.223872, 0.194282, 0.159731", \ + "0.286466, 0.22125, 0.194282, 0.159731", \ "0.412022, 0.344223, 0.317686, 0.283348" \ ); } } timing () { related_pin : "CLK"; + sdf_edges : both_edges; timing_type : removal_rising; rise_constraint (CONSTRAINT_4x4) { index_1 ("0.0186, 0.51636, 1.263, 2.5074"); @@ -10580,13 +10602,13 @@ library (sg13g2_stdcell_fast_1p32V_m40C) { rise_power (passive_POWER_7x1ds1) { index_1 ("0.0186, 0.0966, 0.174, 0.3294, 0.6408, 1.263, 2.5074"); values ( \ - "0.00405883, 0.00397719, 0.00402717, 0.00437902, 0.00551878, 0.00821614, 0.0139408" \ + "0.00406605, 0.0039831, 0.00402759, 0.00438141, 0.00551897, 0.00821616, 0.0139392" \ ); } fall_power (passive_POWER_7x1ds1) { index_1 ("0.0186, 0.0966, 0.174, 0.3294, 0.6408, 1.263, 2.5074"); values ( \ - "0.0314869, 0.0311307, 0.031557, 0.033161, 0.0369033, 0.0450847, 0.0611336" \ + "0.031485, 0.0311264, 0.0315545, 0.0331598, 0.0369042, 0.04508, 0.0611305" \ ); } } @@ -10595,13 +10617,13 @@ library (sg13g2_stdcell_fast_1p32V_m40C) { rise_power (passive_POWER_7x1ds1) { index_1 ("0.0186, 0.0966, 0.174, 0.3294, 0.6408, 1.263, 2.5074"); values ( \ - "0.000910091, 0.000907203, 0.000908817, 0.00090711, 0.000910813, 0.000904221, 0.000908222" \ + "0.000909078, 0.000900274, 0.000908921, 0.000906666, 0.000911773, 0.000904291, 0.000908694" \ ); } fall_power (passive_POWER_7x1ds1) { index_1 ("0.0186, 0.0966, 0.174, 0.3294, 0.6408, 1.263, 2.5074"); values ( \ - "-0.000910091, -0.000907203, -0.000908817, -0.00090711, -0.000910813, -0.000904221, -0.000908222" \ + "-0.000909078, -0.000900274, -0.000908921, -0.000906666, -0.000911773, -0.000904291, -0.000908694" \ ); } } @@ -10610,13 +10632,13 @@ library (sg13g2_stdcell_fast_1p32V_m40C) { rise_power (passive_POWER_7x1ds1) { index_1 ("0.0186, 0.0966, 0.174, 0.3294, 0.6408, 1.263, 2.5074"); values ( \ - "0.0170093, 0.0167347, 0.0169137, 0.0173343, 0.0188969, 0.0228469, 0.0315894" \ + "0.0169671, 0.0167581, 0.0169149, 0.0173329, 0.0188951, 0.0228445, 0.031588" \ ); } fall_power (passive_POWER_7x1ds1) { index_1 ("0.0186, 0.0966, 0.174, 0.3294, 0.6408, 1.263, 2.5074"); values ( \ - "0.0108111, 0.0104632, 0.0104708, 0.0111697, 0.0128641, 0.0170275, 0.0260335" \ + "0.0108103, 0.0104665, 0.0104702, 0.0111711, 0.0128657, 0.0170251, 0.0260326" \ ); } } @@ -10625,13 +10647,13 @@ library (sg13g2_stdcell_fast_1p32V_m40C) { rise_power (passive_POWER_7x1ds1) { index_1 ("0.0186, 0.0966, 0.174, 0.3294, 0.6408, 1.263, 2.5074"); values ( \ - "0.000995011, 0.000988552, 0.000985758, 0.000990258, 0.000997669, 0.000988584, 0.000992153" \ + "0.000995552, 0.000987789, 0.000986878, 0.000991033, 0.000996129, 0.000988868, 0.000991857" \ ); } fall_power (passive_POWER_7x1ds1) { index_1 ("0.0186, 0.0966, 0.174, 0.3294, 0.6408, 1.263, 2.5074"); values ( \ - "-0.000995011, -0.000988552, -0.000985758, -0.000990258, -0.000997669, -0.000988584, -0.000992153" \ + "-0.000995552, -0.000987789, -0.000986878, -0.000991033, -0.000996129, -0.000988868, -0.000991857" \ ); } } @@ -10639,19 +10661,19 @@ library (sg13g2_stdcell_fast_1p32V_m40C) { rise_power (passive_POWER_7x1ds1) { index_1 ("0.0186, 0.0966, 0.174, 0.3294, 0.6408, 1.263, 2.5074"); values ( \ - "0.00405883, 0.00397719, 0.00402717, 0.00437902, 0.00551878, 0.00821614, 0.0139408" \ + "0.00406605, 0.0039831, 0.00402759, 0.00438141, 0.00551897, 0.00821616, 0.0139392" \ ); } fall_power (passive_POWER_7x1ds1) { index_1 ("0.0186, 0.0966, 0.174, 0.3294, 0.6408, 1.263, 2.5074"); values ( \ - "0.0108111, 0.0104632, 0.0104708, 0.0111697, 0.0128641, 0.0170275, 0.0260335" \ + "0.0108103, 0.0104665, 0.0104702, 0.0111711, 0.0128657, 0.0170251, 0.0260326" \ ); } } } ff (IQ,IQN) { - clear : "RESET_B'"; + clear : "!RESET_B"; clocked_on : "CLK"; next_state : "D"; } @@ -10715,6 +10737,7 @@ library (sg13g2_stdcell_fast_1p32V_m40C) { max_capacitance : 0.6; timing () { related_pin : "CLK"; + sdf_edges : start_edge; timing_sense : non_unate; timing_type : rising_edge; cell_rise (TIMING_DELAY_7x7ds1) { @@ -10725,7 +10748,7 @@ library (sg13g2_stdcell_fast_1p32V_m40C) { "0.142949, 0.189798, 0.217543, 0.263157, 0.339378, 0.46622, 0.677647", \ "0.162716, 0.209574, 0.237316, 0.282931, 0.359091, 0.485908, 0.697243", \ "0.189783, 0.236646, 0.264439, 0.310009, 0.386223, 0.513026, 0.724313", \ - "0.227701, 0.274649, 0.302431, 0.348022, 0.424238, 0.550918, 0.762366", \ + "0.227533, 0.274649, 0.302245, 0.347857, 0.424238, 0.550918, 0.762449", \ "0.280364, 0.327512, 0.355279, 0.400912, 0.477097, 0.60392, 0.815265", \ "0.354426, 0.401994, 0.429778, 0.475374, 0.551537, 0.678665, 0.890159" \ ); @@ -10738,7 +10761,7 @@ library (sg13g2_stdcell_fast_1p32V_m40C) { "0.0130759, 0.0677376, 0.107595, 0.174126, 0.285809, 0.472093, 0.782622", \ "0.0130953, 0.0677457, 0.107596, 0.174127, 0.28581, 0.472094, 0.783352", \ "0.0131956, 0.0677515, 0.107597, 0.174128, 0.285811, 0.472095, 0.783353", \ - "0.0133976, 0.0677746, 0.107598, 0.174129, 0.285812, 0.472096, 0.783354", \ + "0.0134, 0.0677746, 0.107622, 0.174129, 0.285812, 0.472096, 0.783354", \ "0.013855, 0.067897, 0.107641, 0.174162, 0.285832, 0.472097, 0.783355", \ "0.014815, 0.06814, 0.107725, 0.174163, 0.285833, 0.472169, 0.783356" \ ); @@ -10747,11 +10770,11 @@ library (sg13g2_stdcell_fast_1p32V_m40C) { index_1 ("0.0186, 0.0966, 0.174, 0.3294, 0.6408, 1.263, 2.5074"); index_2 ("0.001, 0.0468, 0.078, 0.1296, 0.216, 0.36, 0.6"); values ( \ - "0.114498, 0.156553, 0.180064, 0.218502, 0.282614, 0.389276, 0.566775", \ + "0.114498, 0.156553, 0.180064, 0.218502, 0.282614, 0.389276, 0.566774", \ "0.143487, 0.185471, 0.209031, 0.24747, 0.311528, 0.418217, 0.595802", \ "0.162576, 0.204585, 0.22811, 0.266537, 0.330613, 0.437199, 0.614817", \ "0.187809, 0.229763, 0.253308, 0.291749, 0.355824, 0.462395, 0.63995", \ - "0.222342, 0.26403, 0.287868, 0.326019, 0.390065, 0.497056, 0.674568", \ + "0.222033, 0.264327, 0.287868, 0.32631, 0.39034, 0.496766, 0.674312", \ "0.269311, 0.311278, 0.334823, 0.373268, 0.437326, 0.544035, 0.721541", \ "0.332018, 0.373953, 0.397491, 0.435936, 0.499991, 0.606632, 0.784276" \ ); @@ -10760,7 +10783,7 @@ library (sg13g2_stdcell_fast_1p32V_m40C) { index_1 ("0.0186, 0.0966, 0.174, 0.3294, 0.6408, 1.263, 2.5074"); index_2 ("0.001, 0.0468, 0.078, 0.1296, 0.216, 0.36, 0.6"); values ( \ - "0.0117934, 0.0563829, 0.0878324, 0.140714, 0.229709, 0.378515, 0.626289", \ + "0.0117934, 0.0563829, 0.0878324, 0.140714, 0.229709, 0.378515, 0.626286", \ "0.0117944, 0.0563839, 0.0878334, 0.140715, 0.229781, 0.378516, 0.6264", \ "0.0117997, 0.0563849, 0.0878811, 0.140716, 0.229782, 0.378517, 0.627093", \ "0.011806, 0.0563965, 0.0878821, 0.140717, 0.22979, 0.378518, 0.627094", \ @@ -10772,13 +10795,14 @@ library (sg13g2_stdcell_fast_1p32V_m40C) { } timing () { related_pin : "RESET_B"; + sdf_edges : start_edge; timing_sense : positive_unate; timing_type : clear; cell_fall (TIMING_DELAY_7x7ds1) { index_1 ("0.0186, 0.0966, 0.174, 0.3294, 0.6408, 1.263, 2.5074"); index_2 ("0.001, 0.0468, 0.078, 0.1296, 0.216, 0.36, 0.6"); values ( \ - "0.155597, 0.197355, 0.220917, 0.259371, 0.323514, 0.430318, 0.607855", \ + "0.155597, 0.197348, 0.220917, 0.259369, 0.323487, 0.430318, 0.607855", \ "0.193227, 0.234974, 0.258523, 0.296993, 0.361178, 0.467842, 0.645453", \ "0.220689, 0.262467, 0.286018, 0.324449, 0.388546, 0.495233, 0.67283", \ "0.261914, 0.303654, 0.327233, 0.365663, 0.429782, 0.536463, 0.714073", \ @@ -10791,8 +10815,8 @@ library (sg13g2_stdcell_fast_1p32V_m40C) { index_1 ("0.0186, 0.0966, 0.174, 0.3294, 0.6408, 1.263, 2.5074"); index_2 ("0.001, 0.0468, 0.078, 0.1296, 0.216, 0.36, 0.6"); values ( \ - "0.0116462, 0.0562704, 0.0877571, 0.140667, 0.229705, 0.378516, 0.62637", \ - "0.0116472, 0.0562714, 0.0877581, 0.140668, 0.230251, 0.378705, 0.626371", \ + "0.0116462, 0.0562698, 0.0877572, 0.140667, 0.229866, 0.378516, 0.62637", \ + "0.0116472, 0.0562701, 0.0877582, 0.140668, 0.230251, 0.378705, 0.626371", \ "0.0116482, 0.0562723, 0.0877692, 0.140669, 0.230252, 0.378706, 0.627137", \ "0.0116958, 0.0562999, 0.0878106, 0.14067, 0.230253, 0.378707, 0.627138", \ "0.0117791, 0.0563076, 0.0878309, 0.140671, 0.230254, 0.378708, 0.627139", \ @@ -10811,20 +10835,20 @@ library (sg13g2_stdcell_fast_1p32V_m40C) { "0.0352829, 0.036126, 0.0363592, 0.0362194, 0.0365082, 0.0354972, 0.0353292", \ "0.0359526, 0.0368062, 0.0368717, 0.0369379, 0.0369486, 0.0362296, 0.0364467", \ "0.0373682, 0.0382707, 0.038448, 0.0383943, 0.0381703, 0.0382547, 0.0375113", \ - "0.0407926, 0.04157, 0.0417999, 0.0418682, 0.041997, 0.041498, 0.041256", \ + "0.040825, 0.04157, 0.0417912, 0.0419118, 0.041997, 0.041498, 0.0411161", \ "0.0486552, 0.0493103, 0.049565, 0.0495655, 0.0496343, 0.0497064, 0.0494432", \ - "0.0654198, 0.0659073, 0.0659842, 0.0660226, 0.0662164, 0.0660513, 0.0659974" \ + "0.0654198, 0.0659073, 0.0659842, 0.0660226, 0.0662165, 0.0660513, 0.0659974" \ ); } fall_power (POWER_7x7ds1) { index_1 ("0.0186, 0.0966, 0.174, 0.3294, 0.6408, 1.263, 2.5074"); index_2 ("0.001, 0.0468, 0.078, 0.1296, 0.216, 0.36, 0.6"); values ( \ - "0.0363255, 0.037524, 0.0375807, 0.037521, 0.0373292, 0.0369139, 0.0360322", \ + "0.0363255, 0.037524, 0.0375807, 0.037521, 0.0373292, 0.0369139, 0.0360115", \ "0.0364092, 0.0375215, 0.0376529, 0.0380252, 0.0379276, 0.036931, 0.036169", \ "0.0371288, 0.0383562, 0.0384589, 0.0382753, 0.0385512, 0.0377323, 0.0370389", \ - "0.0386994, 0.039876, 0.0400894, 0.0401764, 0.0399062, 0.039468, 0.0393826", \ - "0.0422223, 0.0433466, 0.0435579, 0.043483, 0.0438009, 0.0435238, 0.0420791", \ + "0.0386994, 0.039876, 0.0400894, 0.0401764, 0.0399062, 0.039468, 0.0386984", \ + "0.0422036, 0.0433513, 0.0435579, 0.0434932, 0.0437738, 0.0434869, 0.0422723", \ "0.0498298, 0.0509636, 0.0510908, 0.0512669, 0.0512373, 0.0510978, 0.0512211", \ "0.0660233, 0.0672182, 0.0672315, 0.0671227, 0.0671185, 0.0672404, 0.0672905" \ ); @@ -10841,11 +10865,11 @@ library (sg13g2_stdcell_fast_1p32V_m40C) { index_1 ("0.0186, 0.0966, 0.174, 0.3294, 0.6408, 1.263, 2.5074"); index_2 ("0.001, 0.0468, 0.078, 0.1296, 0.216, 0.36, 0.6"); values ( \ - "0.0246934, 0.02569, 0.025783, 0.0257118, 0.0255056, 0.0252181, 0.0242454", \ + "0.0246934, 0.0257013, 0.025783, 0.0257118, 0.0255346, 0.0252181, 0.0242429", \ "0.0246197, 0.0256697, 0.0258769, 0.0258628, 0.0257439, 0.0252086, 0.0242845", \ "0.0250419, 0.0260913, 0.0260962, 0.0261904, 0.0267134, 0.0258333, 0.0249381", \ - "0.0259204, 0.026946, 0.0271323, 0.0270743, 0.0266587, 0.0269088, 0.0255917", \ - "0.0279019, 0.0289603, 0.0290411, 0.0292403, 0.0292923, 0.0287355, 0.0277142", \ + "0.0259204, 0.026946, 0.0271323, 0.0270742, 0.0266587, 0.0269088, 0.0255917", \ + "0.0279019, 0.0289603, 0.0290411, 0.0292403, 0.0292923, 0.0287275, 0.0277141", \ "0.0317746, 0.0327625, 0.0327867, 0.0329276, 0.0328711, 0.0331492, 0.0330994", \ "0.038653, 0.0395069, 0.0395818, 0.0396886, 0.0396963, 0.039683, 0.0395744" \ ); @@ -10856,11 +10880,11 @@ library (sg13g2_stdcell_fast_1p32V_m40C) { clock : true; direction : "input"; max_transition : 2.5074; - capacitance : 0.00300179; - rise_capacitance : 0.00319884; - rise_capacitance_range (0.00319884, 0.00319884); + capacitance : 0.0030018; + rise_capacitance : 0.00319885; + rise_capacitance_range (0.00289767, 0.00344015); fall_capacitance : 0.0027719; - fall_capacitance_range (0.0027719, 0.0027719); + fall_capacitance_range (0.0027719, 0.00339291); timing () { related_pin : "CLK"; timing_type : min_pulse_width; @@ -10882,13 +10906,13 @@ library (sg13g2_stdcell_fast_1p32V_m40C) { rise_power (passive_POWER_7x1ds1) { index_1 ("0.0186, 0.0966, 0.174, 0.3294, 0.6408, 1.263, 2.5074"); values ( \ - "0.0131993, 0.013112, 0.0137189, 0.0151476, 0.0184398, 0.0258067, 0.0418173" \ + "0.0131992, 0.013112, 0.0137189, 0.0151476, 0.0184398, 0.0258067, 0.0418173" \ ); } fall_power (passive_POWER_7x1ds1) { index_1 ("0.0186, 0.0966, 0.174, 0.3294, 0.6408, 1.263, 2.5074"); values ( \ - "0.0266438, 0.0265883, 0.027192, 0.0288229, 0.0321632, 0.0398439, 0.0561914" \ + "0.0266438, 0.0265882, 0.027192, 0.028823, 0.0321632, 0.0398439, 0.0561914" \ ); } } @@ -10911,7 +10935,7 @@ library (sg13g2_stdcell_fast_1p32V_m40C) { rise_power (passive_POWER_7x1ds1) { index_1 ("0.0186, 0.0966, 0.174, 0.3294, 0.6408, 1.263, 2.5074"); values ( \ - "0.0138853, 0.0137839, 0.0144047, 0.015763, 0.0190712, 0.0264084, 0.0422838" \ + "0.0138694, 0.0137839, 0.0144047, 0.015763, 0.0190712, 0.0264084, 0.0422838" \ ); } fall_power (passive_POWER_7x1ds1) { @@ -10940,7 +10964,7 @@ library (sg13g2_stdcell_fast_1p32V_m40C) { rise_power (passive_POWER_7x1ds1) { index_1 ("0.0186, 0.0966, 0.174, 0.3294, 0.6408, 1.263, 2.5074"); values ( \ - "0.0129442, 0.0128483, 0.0134811, 0.014851, 0.0181508, 0.0255108, 0.0415119" \ + "0.0129457, 0.0128483, 0.0134811, 0.014851, 0.0181508, 0.0255108, 0.0415119" \ ); } fall_power (passive_POWER_7x1ds1) { @@ -10961,7 +10985,7 @@ library (sg13g2_stdcell_fast_1p32V_m40C) { fall_power (passive_POWER_7x1ds1) { index_1 ("0.0186, 0.0966, 0.174, 0.3294, 0.6408, 1.263, 2.5074"); values ( \ - "0.012989, 0.013039, 0.0135884, 0.0151749, 0.0184395, 0.0257867, 0.0415454" \ + "0.0129919, 0.013039, 0.0135884, 0.0151749, 0.0184395, 0.0257867, 0.0415454" \ ); } } @@ -10969,7 +10993,7 @@ library (sg13g2_stdcell_fast_1p32V_m40C) { rise_power (passive_POWER_7x1ds1) { index_1 ("0.0186, 0.0966, 0.174, 0.3294, 0.6408, 1.263, 2.5074"); values ( \ - "0.0131993, 0.013112, 0.0137189, 0.0151476, 0.0184398, 0.0258067, 0.0418173" \ + "0.0131992, 0.013112, 0.0137189, 0.0151476, 0.0184398, 0.0258067, 0.0418173" \ ); } fall_power (passive_POWER_7x1ds1) { @@ -10986,11 +11010,12 @@ library (sg13g2_stdcell_fast_1p32V_m40C) { max_transition : 2.5074; capacitance : 0.00151362; rise_capacitance : 0.00150003; - rise_capacitance_range (0.00150003, 0.00150003); + rise_capacitance_range (0.0014422, 0.00175353); fall_capacitance : 0.00152721; - fall_capacitance_range (0.00152721, 0.00152721); + fall_capacitance_range (0.00152721, 0.00183445); timing () { related_pin : "CLK"; + sdf_edges : both_edges; timing_type : hold_rising; rise_constraint (CONSTRAINT_4x4) { index_1 ("0.0186, 0.51636, 1.263, 2.5074"); @@ -11015,6 +11040,7 @@ library (sg13g2_stdcell_fast_1p32V_m40C) { } timing () { related_pin : "CLK"; + sdf_edges : both_edges; timing_type : setup_rising; rise_constraint (CONSTRAINT_4x4) { index_1 ("0.0186, 0.51636, 1.263, 2.5074"); @@ -11033,7 +11059,7 @@ library (sg13g2_stdcell_fast_1p32V_m40C) { "0.0684653, -0.0272076, -0.0755806, -0.13409", \ "0.19942, 0.109498, 0.056726, -0.0060957", \ "0.296753, 0.21076, 0.161902, 0.100407", \ - "0.403927, 0.322231, 0.275311, 0.215462" \ + "0.403927, 0.322231, 0.272486, 0.215462" \ ); } } @@ -11042,13 +11068,13 @@ library (sg13g2_stdcell_fast_1p32V_m40C) { rise_power (passive_POWER_7x1ds1) { index_1 ("0.0186, 0.0966, 0.174, 0.3294, 0.6408, 1.263, 2.5074"); values ( \ - "0.00166137, 0.00171731, 0.00194383, 0.00255763, 0.00394592, 0.00680906, 0.0128642" \ + "0.00166114, 0.00171732, 0.00194383, 0.00255764, 0.00394593, 0.00680907, 0.0128642" \ ); } fall_power (passive_POWER_7x1ds1) { index_1 ("0.0186, 0.0966, 0.174, 0.3294, 0.6408, 1.263, 2.5074"); values ( \ - "0.00130136, 0.00138818, 0.00165316, 0.00228556, 0.00366689, 0.00658121, 0.0126972" \ + "0.00130362, 0.00138818, 0.00165317, 0.00228557, 0.00366689, 0.00658122, 0.0126972" \ ); } } @@ -11063,7 +11089,7 @@ library (sg13g2_stdcell_fast_1p32V_m40C) { fall_power (passive_POWER_7x1ds1) { index_1 ("0.0186, 0.0966, 0.174, 0.3294, 0.6408, 1.263, 2.5074"); values ( \ - "0.0108538, 0.0107927, 0.0110772, 0.0116993, 0.013252, 0.0165579, 0.023713" \ + "0.0108553, 0.0107927, 0.0110772, 0.0116993, 0.0132519, 0.0165579, 0.023713" \ ); } } @@ -11072,13 +11098,13 @@ library (sg13g2_stdcell_fast_1p32V_m40C) { rise_power (passive_POWER_7x1ds1) { index_1 ("0.0186, 0.0966, 0.174, 0.3294, 0.6408, 1.263, 2.5074"); values ( \ - "-5.97064e-05, -5.47811e-05, -5.53958e-05, -5.41129e-05, -5.37423e-05, -5.43489e-05, -5.33073e-05" \ + "-5.97081e-05, -5.47834e-05, -5.53976e-05, -5.41146e-05, -5.37439e-05, -5.43513e-05, -5.33097e-05" \ ); } fall_power (passive_POWER_7x1ds1) { index_1 ("0.0186, 0.0966, 0.174, 0.3294, 0.6408, 1.263, 2.5074"); values ( \ - "0.000302024, 0.000302505, 0.000303933, 0.000302803, 0.000304461, 0.000305429, 0.000306042" \ + "0.000302476, 0.000302501, 0.000303929, 0.000302799, 0.000304458, 0.000305426, 0.000306039" \ ); } } @@ -11086,13 +11112,13 @@ library (sg13g2_stdcell_fast_1p32V_m40C) { rise_power (passive_POWER_7x1ds1) { index_1 ("0.0186, 0.0966, 0.174, 0.3294, 0.6408, 1.263, 2.5074"); values ( \ - "0.00166137, 0.00171731, 0.00194383, 0.00255763, 0.00394592, 0.00680906, 0.0128642" \ + "0.00166114, 0.00171732, 0.00194383, 0.00255764, 0.00394593, 0.00680907, 0.0128642" \ ); } fall_power (passive_POWER_7x1ds1) { index_1 ("0.0186, 0.0966, 0.174, 0.3294, 0.6408, 1.263, 2.5074"); values ( \ - "0.00130136, 0.00138818, 0.00165316, 0.00228556, 0.00366689, 0.00658121, 0.0126972" \ + "0.00130362, 0.00138818, 0.00165317, 0.00228557, 0.00366689, 0.00658122, 0.0126972" \ ); } } @@ -11102,11 +11128,12 @@ library (sg13g2_stdcell_fast_1p32V_m40C) { max_transition : 2.5074; capacitance : 0.0055001; rise_capacitance : 0.00560039; - rise_capacitance_range (0.00560039, 0.00560039); + rise_capacitance_range (0.00472044, 0.0064738); fall_capacitance : 0.00541653; - fall_capacitance_range (0.00541653, 0.00541653); + fall_capacitance_range (0.00499497, 0.00567501); timing () { related_pin : "CLK"; + sdf_edges : both_edges; timing_type : recovery_rising; rise_constraint (CONSTRAINT_4x4) { index_1 ("0.0186, 0.51636, 1.263, 2.5074"); @@ -11121,6 +11148,7 @@ library (sg13g2_stdcell_fast_1p32V_m40C) { } timing () { related_pin : "CLK"; + sdf_edges : both_edges; timing_type : removal_rising; rise_constraint (CONSTRAINT_4x4) { index_1 ("0.0186, 0.51636, 1.263, 2.5074"); @@ -11148,7 +11176,7 @@ library (sg13g2_stdcell_fast_1p32V_m40C) { rise_power (passive_POWER_7x1ds1) { index_1 ("0.0186, 0.0966, 0.174, 0.3294, 0.6408, 1.263, 2.5074"); values ( \ - "0.00410818, 0.00402425, 0.00406984, 0.00442133, 0.00555755, 0.00826434, 0.0139763" \ + "0.00410801, 0.00402425, 0.00406985, 0.00442133, 0.00555755, 0.00826434, 0.0139763" \ ); } fall_power (passive_POWER_7x1ds1) { @@ -11163,13 +11191,13 @@ library (sg13g2_stdcell_fast_1p32V_m40C) { rise_power (passive_POWER_7x1ds1) { index_1 ("0.0186, 0.0966, 0.174, 0.3294, 0.6408, 1.263, 2.5074"); values ( \ - "0.000947853, 0.000944329, 0.000947404, 0.000945822, 0.000952774, 0.000945597, 0.000948012" \ + "0.000947857, 0.000944592, 0.000947407, 0.000945825, 0.000952777, 0.0009456, 0.000948015" \ ); } fall_power (passive_POWER_7x1ds1) { index_1 ("0.0186, 0.0966, 0.174, 0.3294, 0.6408, 1.263, 2.5074"); values ( \ - "-0.000947853, -0.000944329, -0.000947404, -0.000945822, -0.000952774, -0.000945597, -0.000948012" \ + "-0.000947857, -0.000944592, -0.000947407, -0.000945825, -0.000952777, -0.0009456, -0.000948015" \ ); } } @@ -11193,13 +11221,13 @@ library (sg13g2_stdcell_fast_1p32V_m40C) { rise_power (passive_POWER_7x1ds1) { index_1 ("0.0186, 0.0966, 0.174, 0.3294, 0.6408, 1.263, 2.5074"); values ( \ - "0.00103093, 0.00101961, 0.00102641, 0.00102286, 0.00103545, 0.0010289, 0.00103318" \ + "0.00103092, 0.0010196, 0.0010264, 0.00102285, 0.00103544, 0.00102889, 0.00103318" \ ); } fall_power (passive_POWER_7x1ds1) { index_1 ("0.0186, 0.0966, 0.174, 0.3294, 0.6408, 1.263, 2.5074"); values ( \ - "-0.00103093, -0.00101961, -0.00102641, -0.00102286, -0.00103545, -0.0010289, -0.00103318" \ + "-0.00103092, -0.0010196, -0.0010264, -0.00102285, -0.00103544, -0.00102889, -0.00103318" \ ); } } @@ -11207,7 +11235,7 @@ library (sg13g2_stdcell_fast_1p32V_m40C) { rise_power (passive_POWER_7x1ds1) { index_1 ("0.0186, 0.0966, 0.174, 0.3294, 0.6408, 1.263, 2.5074"); values ( \ - "0.00410818, 0.00402425, 0.00406984, 0.00442133, 0.00555755, 0.00826434, 0.0139763" \ + "0.00410801, 0.00402425, 0.00406985, 0.00442133, 0.00555755, 0.00826434, 0.0139763" \ ); } fall_power (passive_POWER_7x1ds1) { @@ -11219,14 +11247,14 @@ library (sg13g2_stdcell_fast_1p32V_m40C) { } } ff (IQ,IQN) { - clear : "RESET_B'"; + clear : "!RESET_B"; clocked_on : "CLK"; next_state : "D"; } } cell (sg13g2_dlhq_1) { area : 30.8448; - cell_footprint : "DLHQ"; + cell_footprint : "dlhq"; cell_leakage_power : 747.877; leakage_power () { value : 769.227; @@ -11316,6 +11344,7 @@ library (sg13g2_stdcell_fast_1p32V_m40C) { } timing () { related_pin : "GATE"; + sdf_edges : start_edge; timing_sense : non_unate; timing_type : rising_edge; cell_rise (TIMING_DELAY_7x7ds1) { @@ -11435,11 +11464,12 @@ library (sg13g2_stdcell_fast_1p32V_m40C) { max_transition : 2.5074; capacitance : 0.00246672; rise_capacitance : 0.00248634; - rise_capacitance_range (0.00248634, 0.00248634); + rise_capacitance_range (0.00222989, 0.00267504); fall_capacitance : 0.0024471; - fall_capacitance_range (0.0024471, 0.0024471); + fall_capacitance_range (0.00219933, 0.0026842); timing () { related_pin : "GATE"; + sdf_edges : both_edges; timing_type : hold_falling; rise_constraint (CONSTRAINT_4x4) { index_1 ("0.0186, 0.51636, 1.263, 2.5074"); @@ -11464,6 +11494,7 @@ library (sg13g2_stdcell_fast_1p32V_m40C) { } timing () { related_pin : "GATE"; + sdf_edges : both_edges; timing_type : setup_falling; rise_constraint (CONSTRAINT_4x4) { index_1 ("0.0186, 0.51636, 1.263, 2.5074"); @@ -11537,9 +11568,9 @@ library (sg13g2_stdcell_fast_1p32V_m40C) { max_transition : 2.5074; capacitance : 0.00247604; rise_capacitance : 0.00279419; - rise_capacitance_range (0.00279419, 0.00279419); + rise_capacitance_range (0.00247288, 0.00310144); fall_capacitance : 0.00183976; - fall_capacitance_range (0.00183976, 0.00183976); + fall_capacitance_range (0.00183976, 0.00293859); timing () { related_pin : "GATE"; timing_type : min_pulse_width; @@ -11587,7 +11618,7 @@ library (sg13g2_stdcell_fast_1p32V_m40C) { } cell (sg13g2_dlhr_1) { area : 32.6592; - cell_footprint : "DLHR"; + cell_footprint : "dlhr"; cell_leakage_power : 1055.34; leakage_power () { value : 1001.08; @@ -11693,6 +11724,7 @@ library (sg13g2_stdcell_fast_1p32V_m40C) { } timing () { related_pin : "GATE"; + sdf_edges : start_edge; timing_sense : non_unate; timing_type : rising_edge; cell_rise (TIMING_DELAY_7x7ds1) { @@ -11750,6 +11782,7 @@ library (sg13g2_stdcell_fast_1p32V_m40C) { } timing () { related_pin : "RESET_B"; + sdf_edges : start_edge; timing_sense : positive_unate; timing_type : clear; cell_fall (TIMING_DELAY_7x7ds1) { @@ -11923,6 +11956,7 @@ library (sg13g2_stdcell_fast_1p32V_m40C) { } timing () { related_pin : "GATE"; + sdf_edges : start_edge; timing_sense : non_unate; timing_type : rising_edge; cell_rise (TIMING_DELAY_7x7ds1) { @@ -11980,6 +12014,7 @@ library (sg13g2_stdcell_fast_1p32V_m40C) { } timing () { related_pin : "RESET_B"; + sdf_edges : start_edge; timing_sense : negative_unate; timing_type : preset; cell_rise (TIMING_DELAY_7x7ds1) { @@ -12094,11 +12129,12 @@ library (sg13g2_stdcell_fast_1p32V_m40C) { max_transition : 2.5074; capacitance : 0.00225499; rise_capacitance : 0.00243318; - rise_capacitance_range (0.00243318, 0.00243318); + rise_capacitance_range (0.00217066, 0.00262241); fall_capacitance : 0.0020768; - fall_capacitance_range (0.0020768, 0.0020768); + fall_capacitance_range (0.0020768, 0.00263284); timing () { related_pin : "GATE"; + sdf_edges : both_edges; timing_type : hold_falling; rise_constraint (CONSTRAINT_4x4) { index_1 ("0.0186, 0.51636, 1.263, 2.5074"); @@ -12123,6 +12159,7 @@ library (sg13g2_stdcell_fast_1p32V_m40C) { } timing () { related_pin : "GATE"; + sdf_edges : both_edges; timing_type : setup_falling; rise_constraint (CONSTRAINT_4x4) { index_1 ("0.0186, 0.51636, 1.263, 2.5074"); @@ -12196,9 +12233,9 @@ library (sg13g2_stdcell_fast_1p32V_m40C) { max_transition : 2.5074; capacitance : 0.00242762; rise_capacitance : 0.00277467; - rise_capacitance_range (0.00277467, 0.00277467); + rise_capacitance_range (0.00246205, 0.00307773); fall_capacitance : 0.00182028; - fall_capacitance_range (0.00182028, 0.00182028); + fall_capacitance_range (0.00182028, 0.00292273); timing () { related_pin : "GATE"; timing_type : min_pulse_width; @@ -12273,11 +12310,12 @@ library (sg13g2_stdcell_fast_1p32V_m40C) { max_transition : 2.5074; capacitance : 0.00336; rise_capacitance : 0.00353392; - rise_capacitance_range (0.00353392, 0.00353392); + rise_capacitance_range (0.00300742, 0.00381011); fall_capacitance : 0.00325566; - fall_capacitance_range (0.00325566, 0.00325566); + fall_capacitance_range (0.00299365, 0.00349332); timing () { related_pin : "GATE"; + sdf_edges : both_edges; timing_type : recovery_falling; rise_constraint (CONSTRAINT_4x4) { index_1 ("0.0186, 0.51636, 1.263, 2.5074"); @@ -12292,6 +12330,7 @@ library (sg13g2_stdcell_fast_1p32V_m40C) { } timing () { related_pin : "GATE"; + sdf_edges : both_edges; timing_type : removal_falling; rise_constraint (CONSTRAINT_4x4) { index_1 ("0.0186, 0.51636, 1.263, 2.5074"); @@ -12360,14 +12399,14 @@ library (sg13g2_stdcell_fast_1p32V_m40C) { } } latch (IQ,IQN) { - clear : "RESET_B'"; + clear : "!RESET_B"; data_in : "D"; enable : "GATE"; } } cell (sg13g2_dlhrq_1) { area : 27.216; - cell_footprint : "DLHRQ"; + cell_footprint : "dlhrq"; cell_leakage_power : 852.032; leakage_power () { value : 794.414; @@ -12473,6 +12512,7 @@ library (sg13g2_stdcell_fast_1p32V_m40C) { } timing () { related_pin : "GATE"; + sdf_edges : start_edge; timing_sense : non_unate; timing_type : rising_edge; cell_rise (TIMING_DELAY_7x7ds1) { @@ -12530,6 +12570,7 @@ library (sg13g2_stdcell_fast_1p32V_m40C) { } timing () { related_pin : "RESET_B"; + sdf_edges : start_edge; timing_sense : positive_unate; timing_type : clear; cell_fall (TIMING_DELAY_7x7ds1) { @@ -12644,11 +12685,12 @@ library (sg13g2_stdcell_fast_1p32V_m40C) { max_transition : 2.5074; capacitance : 0.00230331; rise_capacitance : 0.00252291; - rise_capacitance_range (0.00252291, 0.00252291); + rise_capacitance_range (0.00225973, 0.00271357); fall_capacitance : 0.00208371; - fall_capacitance_range (0.00208371, 0.00208371); + fall_capacitance_range (0.00208371, 0.00271682); timing () { related_pin : "GATE"; + sdf_edges : both_edges; timing_type : hold_falling; rise_constraint (CONSTRAINT_4x4) { index_1 ("0.0186, 0.51636, 1.263, 2.5074"); @@ -12673,6 +12715,7 @@ library (sg13g2_stdcell_fast_1p32V_m40C) { } timing () { related_pin : "GATE"; + sdf_edges : both_edges; timing_type : setup_falling; rise_constraint (CONSTRAINT_4x4) { index_1 ("0.0186, 0.51636, 1.263, 2.5074"); @@ -12746,9 +12789,9 @@ library (sg13g2_stdcell_fast_1p32V_m40C) { max_transition : 2.5074; capacitance : 0.00237209; rise_capacitance : 0.00279761; - rise_capacitance_range (0.00279761, 0.00279761); + rise_capacitance_range (0.00248564, 0.0030995); fall_capacitance : 0.0018402; - fall_capacitance_range (0.0018402, 0.0018402); + fall_capacitance_range (0.0018402, 0.00294546); timing () { related_pin : "GATE"; timing_type : min_pulse_width; @@ -12823,11 +12866,12 @@ library (sg13g2_stdcell_fast_1p32V_m40C) { max_transition : 2.5074; capacitance : 0.00318395; rise_capacitance : 0.0033164; - rise_capacitance_range (0.0033164, 0.0033164); + rise_capacitance_range (0.00279821, 0.00359539); fall_capacitance : 0.00308462; - fall_capacitance_range (0.00308462, 0.00308462); + fall_capacitance_range (0.00283789, 0.00329664); timing () { related_pin : "GATE"; + sdf_edges : both_edges; timing_type : recovery_falling; rise_constraint (CONSTRAINT_4x4) { index_1 ("0.0186, 0.51636, 1.263, 2.5074"); @@ -12842,6 +12886,7 @@ library (sg13g2_stdcell_fast_1p32V_m40C) { } timing () { related_pin : "GATE"; + sdf_edges : both_edges; timing_type : removal_falling; rise_constraint (CONSTRAINT_4x4) { index_1 ("0.0186, 0.51636, 1.263, 2.5074"); @@ -12910,14 +12955,14 @@ library (sg13g2_stdcell_fast_1p32V_m40C) { } } latch (IQ,IQN) { - clear : "RESET_B'"; + clear : "!RESET_B"; data_in : "D"; enable : "GATE"; } } cell (sg13g2_dllr_1) { area : 34.4736; - cell_footprint : "DLLR"; + cell_footprint : "dllr"; cell_leakage_power : 1072.35; leakage_power () { value : 1053.34; @@ -13039,6 +13084,7 @@ library (sg13g2_stdcell_fast_1p32V_m40C) { } timing () { related_pin : "GATE_N"; + sdf_edges : start_edge; timing_sense : non_unate; timing_type : falling_edge; cell_rise (TIMING_DELAY_7x7ds1) { @@ -13096,6 +13142,7 @@ library (sg13g2_stdcell_fast_1p32V_m40C) { } timing () { related_pin : "RESET_B"; + sdf_edges : start_edge; timing_sense : positive_unate; timing_type : clear; cell_fall (TIMING_DELAY_7x7ds1) { @@ -13269,6 +13316,7 @@ library (sg13g2_stdcell_fast_1p32V_m40C) { } timing () { related_pin : "GATE_N"; + sdf_edges : start_edge; timing_sense : non_unate; timing_type : falling_edge; cell_rise (TIMING_DELAY_7x7ds1) { @@ -13326,6 +13374,7 @@ library (sg13g2_stdcell_fast_1p32V_m40C) { } timing () { related_pin : "RESET_B"; + sdf_edges : start_edge; timing_sense : negative_unate; timing_type : preset; cell_rise (TIMING_DELAY_7x7ds1) { @@ -13440,11 +13489,12 @@ library (sg13g2_stdcell_fast_1p32V_m40C) { max_transition : 2.5074; capacitance : 0.00232651; rise_capacitance : 0.00250495; - rise_capacitance_range (0.00250495, 0.00250495); + rise_capacitance_range (0.00224235, 0.00269699); fall_capacitance : 0.00214806; - fall_capacitance_range (0.00214806, 0.00214806); + fall_capacitance_range (0.00214806, 0.00270292); timing () { related_pin : "GATE_N"; + sdf_edges : both_edges; timing_type : hold_rising; rise_constraint (CONSTRAINT_4x4) { index_1 ("0.0186, 0.51636, 1.263, 2.5074"); @@ -13469,6 +13519,7 @@ library (sg13g2_stdcell_fast_1p32V_m40C) { } timing () { related_pin : "GATE_N"; + sdf_edges : both_edges; timing_type : setup_rising; rise_constraint (CONSTRAINT_4x4) { index_1 ("0.0186, 0.51636, 1.263, 2.5074"); @@ -13542,9 +13593,9 @@ library (sg13g2_stdcell_fast_1p32V_m40C) { max_transition : 2.5074; capacitance : 0.00248991; rise_capacitance : 0.00190578; - rise_capacitance_range (0.00190578, 0.00190578); + rise_capacitance_range (0.00190578, 0.00314282); fall_capacitance : 0.00282371; - fall_capacitance_range (0.00282371, 0.00282371); + fall_capacitance_range (0.00260426, 0.00298894); timing () { related_pin : "GATE_N"; timing_type : min_pulse_width; @@ -13619,11 +13670,12 @@ library (sg13g2_stdcell_fast_1p32V_m40C) { max_transition : 2.5074; capacitance : 0.0033215; rise_capacitance : 0.00349646; - rise_capacitance_range (0.00349646, 0.00349646); + rise_capacitance_range (0.00297769, 0.00377625); fall_capacitance : 0.00321653; - fall_capacitance_range (0.00321653, 0.00321653); + fall_capacitance_range (0.00295672, 0.00345575); timing () { related_pin : "GATE_N"; + sdf_edges : both_edges; timing_type : recovery_rising; rise_constraint (CONSTRAINT_4x4) { index_1 ("0.0186, 0.51636, 1.263, 2.5074"); @@ -13638,6 +13690,7 @@ library (sg13g2_stdcell_fast_1p32V_m40C) { } timing () { related_pin : "GATE_N"; + sdf_edges : both_edges; timing_type : removal_rising; rise_constraint (CONSTRAINT_4x4) { index_1 ("0.0186, 0.51636, 1.263, 2.5074"); @@ -13706,14 +13759,14 @@ library (sg13g2_stdcell_fast_1p32V_m40C) { } } latch (IQ,IQN) { - clear : "RESET_B'"; + clear : "!RESET_B"; data_in : "D"; - enable : "GATE_N'"; + enable : "!GATE_N"; } } cell (sg13g2_dllrq_1) { area : 29.0304; - cell_footprint : "DLLRQ"; + cell_footprint : "dllrq"; cell_leakage_power : 852.005; leakage_power () { value : 846.69; @@ -13819,6 +13872,7 @@ library (sg13g2_stdcell_fast_1p32V_m40C) { } timing () { related_pin : "GATE_N"; + sdf_edges : start_edge; timing_sense : non_unate; timing_type : falling_edge; cell_rise (TIMING_DELAY_7x7ds1) { @@ -13876,6 +13930,7 @@ library (sg13g2_stdcell_fast_1p32V_m40C) { } timing () { related_pin : "RESET_B"; + sdf_edges : start_edge; timing_sense : positive_unate; timing_type : clear; cell_fall (TIMING_DELAY_7x7ds1) { @@ -13907,6 +13962,7 @@ library (sg13g2_stdcell_fast_1p32V_m40C) { } timing () { related_pin : "RESET_B"; + sdf_edges : start_edge; timing_sense : positive_unate; timing_type : preset; cell_rise (TIMING_DELAY_7x7ds1) { @@ -14029,11 +14085,12 @@ library (sg13g2_stdcell_fast_1p32V_m40C) { max_transition : 2.5074; capacitance : 0.00221551; rise_capacitance : 0.00243299; - rise_capacitance_range (0.00243299, 0.00243299); + rise_capacitance_range (0.00216984, 0.00262294); fall_capacitance : 0.00199802; - fall_capacitance_range (0.00199802, 0.00199802); + fall_capacitance_range (0.00199802, 0.0026279); timing () { related_pin : "GATE_N"; + sdf_edges : both_edges; timing_type : hold_rising; rise_constraint (CONSTRAINT_4x4) { index_1 ("0.0186, 0.51636, 1.263, 2.5074"); @@ -14058,6 +14115,7 @@ library (sg13g2_stdcell_fast_1p32V_m40C) { } timing () { related_pin : "GATE_N"; + sdf_edges : both_edges; timing_type : setup_rising; rise_constraint (CONSTRAINT_4x4) { index_1 ("0.0186, 0.51636, 1.263, 2.5074"); @@ -14131,9 +14189,9 @@ library (sg13g2_stdcell_fast_1p32V_m40C) { max_transition : 2.5074; capacitance : 0.00235452; rise_capacitance : 0.00278087; - rise_capacitance_range (0.00278087, 0.00278087); + rise_capacitance_range (0.00246401, 0.00308765); fall_capacitance : 0.00214134; - fall_capacitance_range (0.00214134, 0.00214134); + fall_capacitance_range (0.00214134, 0.00293179); timing () { related_pin : "GATE_N"; timing_type : min_pulse_width; @@ -14208,11 +14266,12 @@ library (sg13g2_stdcell_fast_1p32V_m40C) { max_transition : 2.5074; capacitance : 0.00324671; rise_capacitance : 0.00342282; - rise_capacitance_range (0.00342282, 0.00342282); + rise_capacitance_range (0.00273715, 0.00390891); fall_capacitance : 0.0030706; - fall_capacitance_range (0.0030706, 0.0030706); + fall_capacitance_range (0.00282096, 0.00328153); timing () { related_pin : "GATE_N"; + sdf_edges : both_edges; timing_type : recovery_rising; rise_constraint (CONSTRAINT_4x4) { index_1 ("0.0186, 0.51636, 1.263, 2.5074"); @@ -14227,6 +14286,7 @@ library (sg13g2_stdcell_fast_1p32V_m40C) { } timing () { related_pin : "GATE_N"; + sdf_edges : both_edges; timing_type : removal_rising; rise_constraint (CONSTRAINT_4x4) { index_1 ("0.0186, 0.51636, 1.263, 2.5074"); @@ -14295,14 +14355,14 @@ library (sg13g2_stdcell_fast_1p32V_m40C) { } } latch (IQ,IQN) { - clear : "RESET_B'"; + clear : "!RESET_B"; data_in : "D"; - enable : "GATE_N'"; + enable : "!GATE_N"; } } cell (sg13g2_dlygate4sd1_1) { area : 14.5152; - cell_footprint : "DLY1"; + cell_footprint : "dlygate4sd1"; cell_leakage_power : 324.83; leakage_power () { value : 340.955; @@ -14409,14 +14469,14 @@ library (sg13g2_stdcell_fast_1p32V_m40C) { max_transition : 2.5074; capacitance : 0.00160142; rise_capacitance : 0.0015992; - rise_capacitance_range (0.0015992, 0.0015992); + rise_capacitance_range (0.00141359, 0.00178965); fall_capacitance : 0.00160365; - fall_capacitance_range (0.00160365, 0.00160365); + fall_capacitance_range (0.00149738, 0.00167465); } } cell (sg13g2_dlygate4sd2_1) { area : 14.5152; - cell_footprint : "DLY2"; + cell_footprint : "dlygate4sd2"; cell_leakage_power : 418.479; leakage_power () { value : 434.603; @@ -14523,14 +14583,14 @@ library (sg13g2_stdcell_fast_1p32V_m40C) { max_transition : 2.5074; capacitance : 0.00159337; rise_capacitance : 0.00158968; - rise_capacitance_range (0.00158968, 0.00158968); + rise_capacitance_range (0.00142021, 0.00176701); fall_capacitance : 0.00159706; - fall_capacitance_range (0.00159706, 0.00159706); + fall_capacitance_range (0.00150542, 0.00166215); } } cell (sg13g2_dlygate4sd3_1) { area : 16.3296; - cell_footprint : "DLY4"; + cell_footprint : "dlygate4sd3"; cell_leakage_power : 955.345; leakage_power () { value : 971.449; @@ -14637,14 +14697,14 @@ library (sg13g2_stdcell_fast_1p32V_m40C) { max_transition : 2.5074; capacitance : 0.00160478; rise_capacitance : 0.00159309; - rise_capacitance_range (0.00159309, 0.00159309); + rise_capacitance_range (0.00146435, 0.00173888); fall_capacitance : 0.00161648; - fall_capacitance_range (0.00161648, 0.00161648); + fall_capacitance_range (0.00154064, 0.00167652); } } cell (sg13g2_ebufn_2) { area : 18.144; - cell_footprint : "BTL"; + cell_footprint : "ebufn"; cell_leakage_power : 523.634; leakage_power () { value : 298.636; @@ -14732,6 +14792,7 @@ library (sg13g2_stdcell_fast_1p32V_m40C) { } timing () { related_pin : "TE_B"; + sdf_edges : start_edge; timing_sense : positive_unate; timing_type : three_state_disable; cell_rise (TIMING_DELAY_7x7ds1) { @@ -14789,6 +14850,7 @@ library (sg13g2_stdcell_fast_1p32V_m40C) { } timing () { related_pin : "TE_B"; + sdf_edges : start_edge; timing_sense : negative_unate; timing_type : three_state_enable; cell_rise (TIMING_DELAY_7x7ds1) { @@ -14908,9 +14970,9 @@ library (sg13g2_stdcell_fast_1p32V_m40C) { max_transition : 2.5074; capacitance : 0.0028296; rise_capacitance : 0.00285583; - rise_capacitance_range (0.00285583, 0.00285583); + rise_capacitance_range (0.0025456, 0.00309162); fall_capacitance : 0.00280337; - fall_capacitance_range (0.00280337, 0.00280337); + fall_capacitance_range (0.00250893, 0.00312553); internal_power () { rise_power (passive_POWER_7x1ds1) { index_1 ("0.0186, 0.0966, 0.174, 0.3294, 0.6408, 1.263, 2.5074"); @@ -14931,9 +14993,9 @@ library (sg13g2_stdcell_fast_1p32V_m40C) { max_transition : 2.5074; capacitance : 0.00688516; rise_capacitance : 0.00699335; - rise_capacitance_range (0.00699335, 0.00699335); + rise_capacitance_range (0.00510598, 0.00830888); fall_capacitance : 0.00677697; - fall_capacitance_range (0.00677697, 0.00677697); + fall_capacitance_range (0.00503883, 0.00832168); internal_power () { rise_power (passive_POWER_7x1ds1) { index_1 ("0.0186, 0.0966, 0.174, 0.3294, 0.6408, 1.263, 2.5074"); @@ -14952,7 +15014,7 @@ library (sg13g2_stdcell_fast_1p32V_m40C) { } cell (sg13g2_ebufn_4) { area : 27.216; - cell_footprint : "BTL"; + cell_footprint : "ebufn"; cell_leakage_power : 876.365; leakage_power () { value : 377.107; @@ -15040,6 +15102,7 @@ library (sg13g2_stdcell_fast_1p32V_m40C) { } timing () { related_pin : "TE_B"; + sdf_edges : start_edge; timing_sense : positive_unate; timing_type : three_state_disable; cell_rise (TIMING_DELAY_7x7ds1) { @@ -15097,6 +15160,7 @@ library (sg13g2_stdcell_fast_1p32V_m40C) { } timing () { related_pin : "TE_B"; + sdf_edges : start_edge; timing_sense : negative_unate; timing_type : three_state_enable; cell_rise (TIMING_DELAY_7x7ds1) { @@ -15216,9 +15280,9 @@ library (sg13g2_stdcell_fast_1p32V_m40C) { max_transition : 2.5074; capacitance : 0.003185; rise_capacitance : 0.00322206; - rise_capacitance_range (0.00322206, 0.00322206); + rise_capacitance_range (0.00291177, 0.00348348); fall_capacitance : 0.00314794; - fall_capacitance_range (0.00314794, 0.00314794); + fall_capacitance_range (0.00286493, 0.00345198); internal_power () { rise_power (passive_POWER_7x1ds1) { index_1 ("0.0186, 0.0966, 0.174, 0.3294, 0.6408, 1.263, 2.5074"); @@ -15239,9 +15303,9 @@ library (sg13g2_stdcell_fast_1p32V_m40C) { max_transition : 2.5074; capacitance : 0.0112286; rise_capacitance : 0.0114396; - rise_capacitance_range (0.0114396, 0.0114396); + rise_capacitance_range (0.00786875, 0.0137938); fall_capacitance : 0.0110177; - fall_capacitance_range (0.0110177, 0.0110177); + fall_capacitance_range (0.00773565, 0.0138098); internal_power () { rise_power (passive_POWER_7x1ds1) { index_1 ("0.0186, 0.0966, 0.174, 0.3294, 0.6408, 1.263, 2.5074"); @@ -15260,7 +15324,7 @@ library (sg13g2_stdcell_fast_1p32V_m40C) { } cell (sg13g2_ebufn_8) { area : 45.36; - cell_footprint : "BTL"; + cell_footprint : "ebufn"; cell_leakage_power : 1634.29; leakage_power () { value : 596.369; @@ -15348,6 +15412,7 @@ library (sg13g2_stdcell_fast_1p32V_m40C) { } timing () { related_pin : "TE_B"; + sdf_edges : start_edge; timing_sense : positive_unate; timing_type : three_state_disable; cell_rise (TIMING_DELAY_7x7ds1) { @@ -15405,6 +15470,7 @@ library (sg13g2_stdcell_fast_1p32V_m40C) { } timing () { related_pin : "TE_B"; + sdf_edges : start_edge; timing_sense : negative_unate; timing_type : three_state_enable; cell_rise (TIMING_DELAY_7x7ds1) { @@ -15524,9 +15590,9 @@ library (sg13g2_stdcell_fast_1p32V_m40C) { max_transition : 2.5074; capacitance : 0.00622682; rise_capacitance : 0.00630117; - rise_capacitance_range (0.00630117, 0.00630117); + rise_capacitance_range (0.00564664, 0.00683199); fall_capacitance : 0.00615247; - fall_capacitance_range (0.00615247, 0.00615247); + fall_capacitance_range (0.00556331, 0.00678486); internal_power () { rise_power (passive_POWER_7x1ds1) { index_1 ("0.0186, 0.0966, 0.174, 0.3294, 0.6408, 1.263, 2.5074"); @@ -15547,9 +15613,9 @@ library (sg13g2_stdcell_fast_1p32V_m40C) { max_transition : 2.5074; capacitance : 0.018792; rise_capacitance : 0.0192173; - rise_capacitance_range (0.0192173, 0.0192173); + rise_capacitance_range (0.0119412, 0.0238371); fall_capacitance : 0.0183667; - fall_capacitance_range (0.0183667, 0.0183667); + fall_capacitance_range (0.0116933, 0.0238326); internal_power () { rise_power (passive_POWER_7x1ds1) { index_1 ("0.0186, 0.0966, 0.174, 0.3294, 0.6408, 1.263, 2.5074"); @@ -15568,7 +15634,7 @@ library (sg13g2_stdcell_fast_1p32V_m40C) { } cell (sg13g2_einvn_2) { area : 16.3296; - cell_footprint : "einvin"; + cell_footprint : "einvn"; cell_leakage_power : 660.352; leakage_power () { value : 581.54; @@ -15648,6 +15714,7 @@ library (sg13g2_stdcell_fast_1p32V_m40C) { } timing () { related_pin : "TE_B"; + sdf_edges : start_edge; timing_sense : positive_unate; timing_type : three_state_disable_rise; cell_rise (TIMING_DELAY_7x7ds1) { @@ -15679,6 +15746,7 @@ library (sg13g2_stdcell_fast_1p32V_m40C) { } timing () { related_pin : "TE_B"; + sdf_edges : start_edge; timing_sense : negative_unate; timing_type : three_state_enable_rise; cell_rise (TIMING_DELAY_7x7ds1) { @@ -15764,9 +15832,9 @@ library (sg13g2_stdcell_fast_1p32V_m40C) { max_transition : 2.5074; capacitance : 0.00427198; rise_capacitance : 0.00435546; - rise_capacitance_range (0.00435546, 0.00435546); + rise_capacitance_range (0.00246247, 0.00720793); fall_capacitance : 0.00418851; - fall_capacitance_range (0.00418851, 0.00418851); + fall_capacitance_range (0.00240715, 0.0069946); internal_power () { rise_power (passive_POWER_7x1ds1) { index_1 ("0.0186, 0.0966, 0.174, 0.3294, 0.6408, 1.263, 2.5074"); @@ -15787,9 +15855,9 @@ library (sg13g2_stdcell_fast_1p32V_m40C) { max_transition : 2.5074; capacitance : 0.00525488; rise_capacitance : 0.00589106; - rise_capacitance_range (0.00589106, 0.00589106); + rise_capacitance_range (0.00549702, 0.00609585); fall_capacitance : 0.00461871; - fall_capacitance_range (0.00461871, 0.00461871); + fall_capacitance_range (0.00335334, 0.00721474); internal_power () { rise_power (passive_POWER_7x1ds1) { index_1 ("0.0186, 0.0966, 0.174, 0.3294, 0.6408, 1.263, 2.5074"); @@ -15808,7 +15876,7 @@ library (sg13g2_stdcell_fast_1p32V_m40C) { } cell (sg13g2_einvn_4) { area : 23.5872; - cell_footprint : "einvin"; + cell_footprint : "einvn"; cell_leakage_power : 1312.66; leakage_power () { value : 1155.03; @@ -15888,6 +15956,7 @@ library (sg13g2_stdcell_fast_1p32V_m40C) { } timing () { related_pin : "TE_B"; + sdf_edges : start_edge; timing_sense : positive_unate; timing_type : three_state_disable_rise; cell_rise (TIMING_DELAY_7x7ds1) { @@ -15919,6 +15988,7 @@ library (sg13g2_stdcell_fast_1p32V_m40C) { } timing () { related_pin : "TE_B"; + sdf_edges : start_edge; timing_sense : negative_unate; timing_type : three_state_enable_rise; cell_rise (TIMING_DELAY_7x7ds1) { @@ -16004,9 +16074,9 @@ library (sg13g2_stdcell_fast_1p32V_m40C) { max_transition : 2.5074; capacitance : 0.00834186; rise_capacitance : 0.00850378; - rise_capacitance_range (0.00850378, 0.00850378); + rise_capacitance_range (0.00468454, 0.0143421); fall_capacitance : 0.00817994; - fall_capacitance_range (0.00817994, 0.00817994); + fall_capacitance_range (0.00458171, 0.0139425); internal_power () { rise_power (passive_POWER_7x1ds1) { index_1 ("0.0186, 0.0966, 0.174, 0.3294, 0.6408, 1.263, 2.5074"); @@ -16027,9 +16097,9 @@ library (sg13g2_stdcell_fast_1p32V_m40C) { max_transition : 2.5074; capacitance : 0.00980486; rise_capacitance : 0.0110021; - rise_capacitance_range (0.0110021, 0.0110021); + rise_capacitance_range (0.0100486, 0.011422); fall_capacitance : 0.00860764; - fall_capacitance_range (0.00860764, 0.00860764); + fall_capacitance_range (0.00611946, 0.0136357); internal_power () { rise_power (passive_POWER_7x1ds1) { index_1 ("0.0186, 0.0966, 0.174, 0.3294, 0.6408, 1.263, 2.5074"); @@ -16048,7 +16118,7 @@ library (sg13g2_stdcell_fast_1p32V_m40C) { } cell (sg13g2_einvn_8) { area : 39.9168; - cell_footprint : "ITL"; + cell_footprint : "einvn"; cell_leakage_power : 2546.27; leakage_power () { value : 2231.02; @@ -16128,6 +16198,7 @@ library (sg13g2_stdcell_fast_1p32V_m40C) { } timing () { related_pin : "TE_B"; + sdf_edges : start_edge; timing_sense : positive_unate; timing_type : three_state_disable_rise; cell_rise (TIMING_DELAY_7x7ds1) { @@ -16159,6 +16230,7 @@ library (sg13g2_stdcell_fast_1p32V_m40C) { } timing () { related_pin : "TE_B"; + sdf_edges : start_edge; timing_sense : negative_unate; timing_type : three_state_enable_rise; cell_rise (TIMING_DELAY_7x7ds1) { @@ -16244,9 +16316,9 @@ library (sg13g2_stdcell_fast_1p32V_m40C) { max_transition : 2.5074; capacitance : 0.0165038; rise_capacitance : 0.0168293; - rise_capacitance_range (0.0168293, 0.0168293); + rise_capacitance_range (0.00910225, 0.0286501); fall_capacitance : 0.0161784; - fall_capacitance_range (0.0161784, 0.0161784); + fall_capacitance_range (0.00887948, 0.0278941); internal_power () { rise_power (passive_POWER_7x1ds1) { index_1 ("0.0186, 0.0966, 0.174, 0.3294, 0.6408, 1.263, 2.5074"); @@ -16267,9 +16339,9 @@ library (sg13g2_stdcell_fast_1p32V_m40C) { max_transition : 2.5074; capacitance : 0.0167592; rise_capacitance : 0.0185868; - rise_capacitance_range (0.0185868, 0.0185868); + rise_capacitance_range (0.0160483, 0.0194013); fall_capacitance : 0.0149316; - fall_capacitance_range (0.0149316, 0.0149316); + fall_capacitance_range (0.0108066, 0.0237193); internal_power () { rise_power (passive_POWER_7x1ds1) { index_1 ("0.0186, 0.0966, 0.174, 0.3294, 0.6408, 1.263, 2.5074"); @@ -16320,7 +16392,7 @@ library (sg13g2_stdcell_fast_1p32V_m40C) { } cell (sg13g2_inv_1) { area : 5.4432; - cell_footprint : "IN"; + cell_footprint : "inv"; cell_leakage_power : 118.481; leakage_power () { value : 157.925; @@ -16427,14 +16499,14 @@ library (sg13g2_stdcell_fast_1p32V_m40C) { max_transition : 2.5074; capacitance : 0.00305794; rise_capacitance : 0.0031009; - rise_capacitance_range (0.0031009, 0.0031009); + rise_capacitance_range (0.00278963, 0.00354768); fall_capacitance : 0.00301498; - fall_capacitance_range (0.00301498, 0.00301498); + fall_capacitance_range (0.00277732, 0.00362526); } } cell (sg13g2_inv_16) { area : 34.4736; - cell_footprint : "IN"; + cell_footprint : "inv"; cell_leakage_power : 1895.1; leakage_power () { value : 2525.6; @@ -16541,14 +16613,14 @@ library (sg13g2_stdcell_fast_1p32V_m40C) { max_transition : 2.5074; capacitance : 0.0462692; rise_capacitance : 0.0468797; - rise_capacitance_range (0.0468797, 0.0468797); + rise_capacitance_range (0.0349366, 0.0561634); fall_capacitance : 0.0456587; - fall_capacitance_range (0.0456587, 0.0456587); + fall_capacitance_range (0.0352187, 0.0579716); } } cell (sg13g2_inv_2) { area : 7.2576; - cell_footprint : "IN"; + cell_footprint : "inv"; cell_leakage_power : 236.902; leakage_power () { value : 315.719; @@ -16655,14 +16727,14 @@ library (sg13g2_stdcell_fast_1p32V_m40C) { max_transition : 2.5074; capacitance : 0.00605625; rise_capacitance : 0.00613958; - rise_capacitance_range (0.00613958, 0.00613958); + rise_capacitance_range (0.00546183, 0.00711337); fall_capacitance : 0.00597292; - fall_capacitance_range (0.00597292, 0.00597292); + fall_capacitance_range (0.00544941, 0.00735526); } } cell (sg13g2_inv_4) { area : 10.8864; - cell_footprint : "IN"; + cell_footprint : "inv"; cell_leakage_power : 473.776; leakage_power () { value : 631.4; @@ -16769,14 +16841,14 @@ library (sg13g2_stdcell_fast_1p32V_m40C) { max_transition : 2.5074; capacitance : 0.0119894; rise_capacitance : 0.0121531; - rise_capacitance_range (0.0121531, 0.0121531); + rise_capacitance_range (0.01082, 0.0141546); fall_capacitance : 0.0118257; - fall_capacitance_range (0.0118257, 0.0118257); + fall_capacitance_range (0.0108133, 0.0147459); } } cell (sg13g2_inv_8) { area : 18.144; - cell_footprint : "IN"; + cell_footprint : "inv"; cell_leakage_power : 947.581; leakage_power () { value : 1262.86; @@ -16883,14 +16955,14 @@ library (sg13g2_stdcell_fast_1p32V_m40C) { max_transition : 2.5074; capacitance : 0.0239835; rise_capacitance : 0.0243054; - rise_capacitance_range (0.0243054, 0.0243054); + rise_capacitance_range (0.0214806, 0.0283944); fall_capacitance : 0.0236617; - fall_capacitance_range (0.0236617, 0.0236617); + fall_capacitance_range (0.0215091, 0.0296422); } } cell (sg13g2_lgcp_1) { area : 27.216; - cell_footprint : "gclk"; + cell_footprint : "lgcp"; cell_leakage_power : 826.732; clock_gating_integrated_cell : "latch_posedge"; dont_use : true; @@ -17014,9 +17086,9 @@ library (sg13g2_stdcell_fast_1p32V_m40C) { max_transition : 2.5074; capacitance : 0.00533845; rise_capacitance : 0.00540796; - rise_capacitance_range (0.00540796, 0.00540796); + rise_capacitance_range (0.00464721, 0.006268); fall_capacitance : 0.00526894; - fall_capacitance_range (0.00526894, 0.00526894); + fall_capacitance_range (0.00481949, 0.00561979); timing () { related_pin : "CLK"; timing_type : min_pulse_width; @@ -17054,11 +17126,12 @@ library (sg13g2_stdcell_fast_1p32V_m40C) { max_transition : 2.5074; capacitance : 0.00250231; rise_capacitance : 0.00280915; - rise_capacitance_range (0.00280915, 0.00280915); + rise_capacitance_range (0.00243272, 0.00306655); fall_capacitance : 0.00219548; - fall_capacitance_range (0.00219548, 0.00219548); + fall_capacitance_range (0.00219548, 0.00252533); timing () { related_pin : "CLK"; + sdf_edges : both_edges; timing_type : hold_rising; rise_constraint (CONSTRAINT_4x4) { index_1 ("0.0186, 0.51636, 1.263, 2.5074"); @@ -17083,6 +17156,7 @@ library (sg13g2_stdcell_fast_1p32V_m40C) { } timing () { related_pin : "CLK"; + sdf_edges : both_edges; timing_type : setup_rising; rise_constraint (CONSTRAINT_4x4) { index_1 ("0.0186, 0.51636, 1.263, 2.5074"); @@ -17293,7 +17367,7 @@ library (sg13g2_stdcell_fast_1p32V_m40C) { } timing () { related_pin : "S"; - sdf_cond : "A0 == 1'b0 & A1 == 1'b1"; + sdf_cond : "A0 == 1'b0 && A1 == 1'b1"; timing_sense : positive_unate; timing_type : combinational; when : "(!A0 * A1)"; @@ -17409,7 +17483,7 @@ library (sg13g2_stdcell_fast_1p32V_m40C) { } timing () { related_pin : "S"; - sdf_cond : "A0 == 1'b1 & A1 == 1'b0"; + sdf_cond : "A0 == 1'b1 && A1 == 1'b0"; timing_sense : negative_unate; timing_type : combinational; when : "(A0 * !A1)"; @@ -17619,27 +17693,27 @@ library (sg13g2_stdcell_fast_1p32V_m40C) { max_transition : 2.5074; capacitance : 0.00299286; rise_capacitance : 0.00304141; - rise_capacitance_range (0.00304141, 0.00304141); + rise_capacitance_range (0.00260783, 0.00337239); fall_capacitance : 0.00294431; - fall_capacitance_range (0.00294431, 0.00294431); + fall_capacitance_range (0.00258284, 0.00317295); } pin (A1) { direction : "input"; max_transition : 2.5074; capacitance : 0.00309682; rise_capacitance : 0.00314541; - rise_capacitance_range (0.00314541, 0.00314541); + rise_capacitance_range (0.0027162, 0.0034759); fall_capacitance : 0.00304822; - fall_capacitance_range (0.00304822, 0.00304822); + fall_capacitance_range (0.00268911, 0.00327266); } pin (S) { direction : "input"; max_transition : 2.5074; capacitance : 0.0055272; rise_capacitance : 0.0055525; - rise_capacitance_range (0.0055525, 0.0055525); + rise_capacitance_range (0.00466947, 0.00639041); fall_capacitance : 0.00550189; - fall_capacitance_range (0.00550189, 0.00550189); + fall_capacitance_range (0.00466881, 0.00642386); internal_power () { when : "(A0 * A1)"; rise_power (passive_POWER_7x1ds1) { @@ -17843,7 +17917,7 @@ library (sg13g2_stdcell_fast_1p32V_m40C) { } timing () { related_pin : "S"; - sdf_cond : "A0 == 1'b0 & A1 == 1'b1"; + sdf_cond : "A0 == 1'b0 && A1 == 1'b1"; timing_sense : positive_unate; timing_type : combinational; when : "(!A0 * A1)"; @@ -17959,7 +18033,7 @@ library (sg13g2_stdcell_fast_1p32V_m40C) { } timing () { related_pin : "S"; - sdf_cond : "A0 == 1'b1 & A1 == 1'b0"; + sdf_cond : "A0 == 1'b1 && A1 == 1'b0"; timing_sense : negative_unate; timing_type : combinational; when : "(A0 * !A1)"; @@ -18169,27 +18243,27 @@ library (sg13g2_stdcell_fast_1p32V_m40C) { max_transition : 2.5074; capacitance : 0.0029731; rise_capacitance : 0.0030172; - rise_capacitance_range (0.0030172, 0.0030172); + rise_capacitance_range (0.00265386, 0.00331566); fall_capacitance : 0.002929; - fall_capacitance_range (0.002929, 0.002929); + fall_capacitance_range (0.00262284, 0.00313548); } pin (A1) { direction : "input"; max_transition : 2.5074; capacitance : 0.0030765; rise_capacitance : 0.00312082; - rise_capacitance_range (0.00312082, 0.00312082); + rise_capacitance_range (0.00276218, 0.00341773); fall_capacitance : 0.00303218; - fall_capacitance_range (0.00303218, 0.00303218); + fall_capacitance_range (0.00272791, 0.00323262); } pin (S) { direction : "input"; max_transition : 2.5074; capacitance : 0.00551838; rise_capacitance : 0.00554292; - rise_capacitance_range (0.00554292, 0.00554292); + rise_capacitance_range (0.00466135, 0.00638221); fall_capacitance : 0.00549384; - fall_capacitance_range (0.00549384, 0.00549384); + fall_capacitance_range (0.00466772, 0.00641566); internal_power () { when : "(A0 * A1)"; rise_power (passive_POWER_7x1ds1) { @@ -18731,7 +18805,7 @@ library (sg13g2_stdcell_fast_1p32V_m40C) { } timing () { related_pin : "S0"; - sdf_cond : "A2 == 1'b0 & A3 == 1'b1 & S1 == 1'b1"; + sdf_cond : "A2 == 1'b0 && A3 == 1'b1 && S1 == 1'b1"; timing_sense : positive_unate; timing_type : combinational; when : "(!A2 * A3 * S1)"; @@ -18790,7 +18864,7 @@ library (sg13g2_stdcell_fast_1p32V_m40C) { } timing () { related_pin : "S0"; - sdf_cond : "A0 == 1'b0 & A1 == 1'b1 & S1 == 1'b0"; + sdf_cond : "A0 == 1'b0 && A1 == 1'b1 && S1 == 1'b0"; timing_sense : positive_unate; timing_type : combinational; when : "(!A0 * A1 * !S1)"; @@ -18906,7 +18980,7 @@ library (sg13g2_stdcell_fast_1p32V_m40C) { } timing () { related_pin : "S0"; - sdf_cond : "A2 == 1'b1 & A3 == 1'b0 & S1 == 1'b1"; + sdf_cond : "A2 == 1'b1 && A3 == 1'b0 && S1 == 1'b1"; timing_sense : negative_unate; timing_type : combinational; when : "(A2 * !A3 * S1)"; @@ -18965,7 +19039,7 @@ library (sg13g2_stdcell_fast_1p32V_m40C) { } timing () { related_pin : "S0"; - sdf_cond : "A0 == 1'b1 & A1 == 1'b0 & S1 == 1'b0"; + sdf_cond : "A0 == 1'b1 && A1 == 1'b0 && S1 == 1'b0"; timing_sense : negative_unate; timing_type : combinational; when : "(A0 * !A1 * !S1)"; @@ -19024,7 +19098,7 @@ library (sg13g2_stdcell_fast_1p32V_m40C) { } timing () { related_pin : "S1"; - sdf_cond : "A1 == 1'b0 & A3 == 1'b1 & S0 == 1'b1"; + sdf_cond : "A1 == 1'b0 && A3 == 1'b1 && S0 == 1'b1"; timing_sense : positive_unate; timing_type : combinational; when : "(!A1 * A3 * S0)"; @@ -19083,7 +19157,7 @@ library (sg13g2_stdcell_fast_1p32V_m40C) { } timing () { related_pin : "S1"; - sdf_cond : "A0 == 1'b0 & A2 == 1'b1 & S0 == 1'b0"; + sdf_cond : "A0 == 1'b0 && A2 == 1'b1 && S0 == 1'b0"; timing_sense : positive_unate; timing_type : combinational; when : "(!A0 * A2 * !S0)"; @@ -19199,7 +19273,7 @@ library (sg13g2_stdcell_fast_1p32V_m40C) { } timing () { related_pin : "S1"; - sdf_cond : "A1 == 1'b1 & A3 == 1'b0 & S0 == 1'b1"; + sdf_cond : "A1 == 1'b1 && A3 == 1'b0 && S0 == 1'b1"; timing_sense : negative_unate; timing_type : combinational; when : "(A1 * !A3 * S0)"; @@ -19258,7 +19332,7 @@ library (sg13g2_stdcell_fast_1p32V_m40C) { } timing () { related_pin : "S1"; - sdf_cond : "A0 == 1'b1 & A2 == 1'b0 & S0 == 1'b0"; + sdf_cond : "A0 == 1'b1 && A2 == 1'b0 && S0 == 1'b0"; timing_sense : negative_unate; timing_type : combinational; when : "(A0 * !A2 * !S0)"; @@ -19735,45 +19809,45 @@ library (sg13g2_stdcell_fast_1p32V_m40C) { max_transition : 2.5074; capacitance : 0.00304706; rise_capacitance : 0.00307374; - rise_capacitance_range (0.00307374, 0.00307374); + rise_capacitance_range (0.00260998, 0.00333358); fall_capacitance : 0.00302038; - fall_capacitance_range (0.00302038, 0.00302038); + fall_capacitance_range (0.00256997, 0.00329064); } pin (A1) { direction : "input"; max_transition : 2.5074; capacitance : 0.0030248; rise_capacitance : 0.00305095; - rise_capacitance_range (0.00305095, 0.00305095); + rise_capacitance_range (0.00261728, 0.00332074); fall_capacitance : 0.00299864; - fall_capacitance_range (0.00299864, 0.00299864); + fall_capacitance_range (0.00251973, 0.0032449); } pin (A2) { direction : "input"; max_transition : 2.5074; capacitance : 0.00304672; rise_capacitance : 0.00307268; - rise_capacitance_range (0.00307268, 0.00307268); + rise_capacitance_range (0.00261195, 0.00333149); fall_capacitance : 0.00302075; - fall_capacitance_range (0.00302075, 0.00302075); + fall_capacitance_range (0.00255513, 0.0032785); } pin (A3) { direction : "input"; max_transition : 2.5074; capacitance : 0.00310742; rise_capacitance : 0.00313097; - rise_capacitance_range (0.00313097, 0.00313097); + rise_capacitance_range (0.00267105, 0.00338709); fall_capacitance : 0.00308387; - fall_capacitance_range (0.00308387, 0.00308387); + fall_capacitance_range (0.00259793, 0.00333326); } pin (S0) { direction : "input"; max_transition : 2.5074; capacitance : 0.00882371; rise_capacitance : 0.0105038; - rise_capacitance_range (0.0105038, 0.0105038); + rise_capacitance_range (0.00792474, 0.0118041); fall_capacitance : 0.00714362; - fall_capacitance_range (0.00714362, 0.00714362); + fall_capacitance_range (0.00421064, 0.0104519); internal_power () { when : "(A2 * A3 * S1)"; rise_power (passive_POWER_7x1ds1) { @@ -19854,9 +19928,9 @@ library (sg13g2_stdcell_fast_1p32V_m40C) { max_transition : 2.5074; capacitance : 0.00536127; rise_capacitance : 0.00540084; - rise_capacitance_range (0.00540084, 0.00540084); + rise_capacitance_range (0.00448136, 0.00643169); fall_capacitance : 0.0053217; - fall_capacitance_range (0.0053217, 0.0053217); + fall_capacitance_range (0.00449173, 0.00632754); internal_power () { when : "(A1 * A3 * S0)"; rise_power (passive_POWER_7x1ds1) { @@ -20136,18 +20210,18 @@ library (sg13g2_stdcell_fast_1p32V_m40C) { max_transition : 2.5074; capacitance : 0.00307279; rise_capacitance : 0.00309042; - rise_capacitance_range (0.00309042, 0.00309042); + rise_capacitance_range (0.00278647, 0.00339731); fall_capacitance : 0.00305516; - fall_capacitance_range (0.00305516, 0.00305516); + fall_capacitance_range (0.00269157, 0.00381898); } pin (B) { direction : "input"; max_transition : 2.5074; capacitance : 0.00319639; rise_capacitance : 0.00333843; - rise_capacitance_range (0.00333843, 0.00333843); + rise_capacitance_range (0.0028359, 0.00368871); fall_capacitance : 0.00305434; - fall_capacitance_range (0.00305434, 0.00305434); + fall_capacitance_range (0.00284658, 0.00353392); } } cell (sg13g2_nand2_2) { @@ -20353,23 +20427,23 @@ library (sg13g2_stdcell_fast_1p32V_m40C) { max_transition : 2.5074; capacitance : 0.00596241; rise_capacitance : 0.00600246; - rise_capacitance_range (0.00600246, 0.00600246); + rise_capacitance_range (0.00537098, 0.00660371); fall_capacitance : 0.00592236; - fall_capacitance_range (0.00592236, 0.00592236); + fall_capacitance_range (0.00514706, 0.00766116); } pin (B) { direction : "input"; max_transition : 2.5074; capacitance : 0.00614413; rise_capacitance : 0.0064277; - rise_capacitance_range (0.0064277, 0.0064277); + rise_capacitance_range (0.00543964, 0.0071255); fall_capacitance : 0.00586056; - fall_capacitance_range (0.00586056, 0.00586056); + fall_capacitance_range (0.00541927, 0.00690733); } } cell (sg13g2_nand2b_1) { area : 9.072; - cell_footprint : "nand2b1"; + cell_footprint : "nand2b"; cell_leakage_power : 269.631; leakage_power () { value : 373.972; @@ -20570,9 +20644,9 @@ library (sg13g2_stdcell_fast_1p32V_m40C) { max_transition : 2.5074; capacitance : 0.00242664; rise_capacitance : 0.00244843; - rise_capacitance_range (0.00244843, 0.00244843); + rise_capacitance_range (0.00217892, 0.00264299); fall_capacitance : 0.00240485; - fall_capacitance_range (0.00240485, 0.00240485); + fall_capacitance_range (0.00215965, 0.00264266); internal_power () { when : "!B"; rise_power (passive_POWER_7x1ds1) { @@ -20608,14 +20682,14 @@ library (sg13g2_stdcell_fast_1p32V_m40C) { max_transition : 2.5074; capacitance : 0.00324437; rise_capacitance : 0.00338689; - rise_capacitance_range (0.00338689, 0.00338689); + rise_capacitance_range (0.00287996, 0.00373504); fall_capacitance : 0.00310185; - fall_capacitance_range (0.00310185, 0.00310185); + fall_capacitance_range (0.00289587, 0.00357911); } } cell (sg13g2_nand2b_2) { area : 14.5152; - cell_footprint : "nand2b2"; + cell_footprint : "nand2b"; cell_leakage_power : 447.515; leakage_power () { value : 672.236; @@ -20816,9 +20890,9 @@ library (sg13g2_stdcell_fast_1p32V_m40C) { max_transition : 2.5074; capacitance : 0.00237057; rise_capacitance : 0.00239557; - rise_capacitance_range (0.00239557, 0.00239557); + rise_capacitance_range (0.00219118, 0.00256501); fall_capacitance : 0.00234558; - fall_capacitance_range (0.00234558, 0.00234558); + fall_capacitance_range (0.00214833, 0.00254005); internal_power () { when : "!B"; rise_power (passive_POWER_7x1ds1) { @@ -20854,9 +20928,9 @@ library (sg13g2_stdcell_fast_1p32V_m40C) { max_transition : 2.5074; capacitance : 0.00598555; rise_capacitance : 0.00602596; - rise_capacitance_range (0.00602596, 0.00602596); + rise_capacitance_range (0.00539444, 0.00662977); fall_capacitance : 0.00594515; - fall_capacitance_range (0.00594515, 0.00594515); + fall_capacitance_range (0.00516295, 0.00768573); } } cell (sg13g2_nand3_1) { @@ -21164,32 +21238,32 @@ library (sg13g2_stdcell_fast_1p32V_m40C) { max_transition : 2.5074; capacitance : 0.00306468; rise_capacitance : 0.00306712; - rise_capacitance_range (0.00306712, 0.00306712); + rise_capacitance_range (0.0027871, 0.00330255); fall_capacitance : 0.00306223; - fall_capacitance_range (0.00306223, 0.00306223); + fall_capacitance_range (0.00263163, 0.00390574); } pin (B) { direction : "input"; max_transition : 2.5074; capacitance : 0.00322338; rise_capacitance : 0.00333913; - rise_capacitance_range (0.00333913, 0.00333913); + rise_capacitance_range (0.00284989, 0.00364849); fall_capacitance : 0.00310763; - fall_capacitance_range (0.00310763, 0.00310763); + fall_capacitance_range (0.00280853, 0.00369139); } pin (C) { direction : "input"; max_transition : 2.5074; capacitance : 0.00320122; rise_capacitance : 0.00335248; - rise_capacitance_range (0.00335248, 0.00335248); + rise_capacitance_range (0.00284987, 0.00371008); fall_capacitance : 0.00304997; - fall_capacitance_range (0.00304997, 0.00304997); + fall_capacitance_range (0.00287062, 0.00346409); } } cell (sg13g2_nand3b_1) { area : 12.7008; - cell_footprint : "nand3b1"; + cell_footprint : "nand3b"; cell_leakage_power : 315.513; leakage_power () { value : 201.697; @@ -21492,9 +21566,9 @@ library (sg13g2_stdcell_fast_1p32V_m40C) { max_transition : 2.5074; capacitance : 0.00240688; rise_capacitance : 0.00242844; - rise_capacitance_range (0.00242844, 0.00242844); + rise_capacitance_range (0.0021571, 0.00262319); fall_capacitance : 0.00238531; - fall_capacitance_range (0.00238531, 0.00238531); + fall_capacitance_range (0.00214014, 0.00262366); internal_power () { when : "(B * !C) + (!B)"; rise_power (passive_POWER_7x1ds1) { @@ -21530,18 +21604,18 @@ library (sg13g2_stdcell_fast_1p32V_m40C) { max_transition : 2.5074; capacitance : 0.00318726; rise_capacitance : 0.00330345; - rise_capacitance_range (0.00330345, 0.00330345); + rise_capacitance_range (0.00281096, 0.00361136); fall_capacitance : 0.00307107; - fall_capacitance_range (0.00307107, 0.00307107); + fall_capacitance_range (0.00277321, 0.00365302); } pin (C) { direction : "input"; max_transition : 2.5074; capacitance : 0.00321219; rise_capacitance : 0.00336317; - rise_capacitance_range (0.00336317, 0.00336317); + rise_capacitance_range (0.00286246, 0.00371959); fall_capacitance : 0.00306121; - fall_capacitance_range (0.00306121, 0.00306121); + fall_capacitance_range (0.00288239, 0.0034735); } } cell (sg13g2_nand4_1) { @@ -21625,25 +21699,25 @@ library (sg13g2_stdcell_fast_1p32V_m40C) { index_1 ("0.0186, 0.0966, 0.174, 0.3294, 0.6408, 1.263, 2.5074"); index_2 ("0.001, 0.0234, 0.039, 0.0648, 0.108, 0.18, 0.3"); values ( \ - "0.0200099, 0.0612065, 0.0887541, 0.134256, 0.210406, 0.337139, 0.548293", \ - "0.0359806, 0.0987233, 0.129716, 0.176778, 0.252969, 0.379709, 0.590928", \ - "0.0431896, 0.124169, 0.161425, 0.214158, 0.29412, 0.421515, 0.632558", \ - "0.0495488, 0.159554, 0.20816, 0.274259, 0.367388, 0.503826, 0.718044", \ - "0.0530432, 0.203478, 0.270755, 0.358338, 0.477157, 0.640312, 0.875342", \ - "0.0530442, 0.253226, 0.347394, 0.470165, 0.630276, 0.84528, 1.1341", \ - "0.0530452, 0.294926, 0.425689, 0.598747, 0.825769, 1.11838, 1.50652" \ + "0.0200099, 0.0612065, 0.0887494, 0.134312, 0.210406, 0.337139, 0.548504", \ + "0.0359806, 0.0987154, 0.129716, 0.176778, 0.25295, 0.379831, 0.590999", \ + "0.0431896, 0.124169, 0.161426, 0.214157, 0.29412, 0.421462, 0.632641", \ + "0.0495488, 0.159554, 0.20816, 0.274259, 0.367388, 0.503862, 0.718044", \ + "0.0530433, 0.203478, 0.270755, 0.358338, 0.477157, 0.640312, 0.875342", \ + "0.0530443, 0.253226, 0.347394, 0.470165, 0.630276, 0.84528, 1.1341", \ + "0.0530453, 0.294926, 0.425689, 0.598747, 0.825769, 1.11838, 1.50652" \ ); } rise_transition (TIMING_DELAY_7x7ds1) { index_1 ("0.0186, 0.0966, 0.174, 0.3294, 0.6408, 1.263, 2.5074"); index_2 ("0.001, 0.0234, 0.039, 0.0648, 0.108, 0.18, 0.3"); values ( \ - "0.0137748, 0.0696338, 0.110171, 0.176637, 0.288216, 0.474343, 0.784547", \ - "0.0299304, 0.0840537, 0.119833, 0.181519, 0.289557, 0.47442, 0.784548", \ - "0.0421865, 0.103367, 0.138858, 0.197499, 0.29935, 0.477685, 0.784549", \ - "0.0621404, 0.139381, 0.178152, 0.237459, 0.334921, 0.502128, 0.795501", \ - "0.0932552, 0.198697, 0.244808, 0.312287, 0.413503, 0.57566, 0.85018", \ - "0.145377, 0.292285, 0.356874, 0.438692, 0.557667, 0.731372, 1.00565", \ + "0.0137748, 0.0696338, 0.109921, 0.176709, 0.288216, 0.474343, 0.784353", \ + "0.0299304, 0.084062, 0.119833, 0.181515, 0.289523, 0.474344, 0.784449", \ + "0.0421865, 0.103367, 0.138858, 0.197499, 0.299351, 0.477691, 0.784667", \ + "0.0621404, 0.139381, 0.178152, 0.237459, 0.334921, 0.502145, 0.795501", \ + "0.0932551, 0.198697, 0.244808, 0.312287, 0.413503, 0.57566, 0.85018", \ + "0.145377, 0.292284, 0.356874, 0.438692, 0.557667, 0.731372, 1.00565", \ "0.23346, 0.438888, 0.530828, 0.649245, 0.798411, 1.00827, 1.30837" \ ); } @@ -21651,26 +21725,26 @@ library (sg13g2_stdcell_fast_1p32V_m40C) { index_1 ("0.0186, 0.0966, 0.174, 0.3294, 0.6408, 1.263, 2.5074"); index_2 ("0.001, 0.0234, 0.039, 0.0648, 0.108, 0.18, 0.3"); values ( \ - "0.0407545, 0.165633, 0.250754, 0.391102, 0.625788, 1.0172, 1.66865", \ - "0.0621832, 0.196735, 0.282037, 0.422775, 0.657632, 1.049, 1.70103", \ - "0.0772736, 0.2274, 0.315153, 0.456188, 0.69117, 1.08259, 1.73494", \ - "0.0993394, 0.277183, 0.373751, 0.521018, 0.757742, 1.14871, 1.80012", \ - "0.134088, 0.350423, 0.464205, 0.630658, 0.883386, 1.27997, 1.93082", \ - "0.189189, 0.458624, 0.598005, 0.797325, 1.08927, 1.52503, 2.19528", \ - "0.281494, 0.619569, 0.793734, 1.04154, 1.39476, 1.90928, 2.66134" \ + "0.0407584, 0.165678, 0.250754, 0.391094, 0.62579, 1.0172, 1.66915", \ + "0.0621831, 0.196735, 0.282034, 0.42276, 0.657627, 1.049, 1.70141", \ + "0.0772735, 0.2274, 0.315152, 0.456188, 0.691131, 1.08261, 1.73505", \ + "0.0993394, 0.277183, 0.37375, 0.521031, 0.757742, 1.14874, 1.80017", \ + "0.134088, 0.350423, 0.464205, 0.630658, 0.883385, 1.27997, 1.93087", \ + "0.189189, 0.458623, 0.598093, 0.797325, 1.08927, 1.52503, 2.19524", \ + "0.281494, 0.619568, 0.793733, 1.04154, 1.39475, 1.90927, 2.66134" \ ); } fall_transition (TIMING_DELAY_7x7ds1) { index_1 ("0.0186, 0.0966, 0.174, 0.3294, 0.6408, 1.263, 2.5074"); index_2 ("0.001, 0.0234, 0.039, 0.0648, 0.108, 0.18, 0.3"); values ( \ - "0.0367027, 0.201147, 0.315705, 0.504776, 0.821894, 1.35098, 2.23045", \ - "0.0490079, 0.204577, 0.316354, 0.506883, 0.821895, 1.35099, 2.23047", \ - "0.0600444, 0.217181, 0.324569, 0.508036, 0.822927, 1.351, 2.23062", \ - "0.0780622, 0.247642, 0.352661, 0.527673, 0.831271, 1.35187, 2.23063", \ - "0.107539, 0.302679, 0.412613, 0.587492, 0.877044, 1.37618, 2.23645", \ - "0.15893, 0.39171, 0.515539, 0.705377, 0.999621, 1.48252, 2.30242", \ - "0.246622, 0.526798, 0.680881, 0.89668, 1.22614, 1.72528, 2.53139" \ + "0.0367287, 0.201175, 0.315705, 0.504774, 0.821893, 1.35097, 2.23194", \ + "0.0490078, 0.204576, 0.316351, 0.506876, 0.821894, 1.35098, 2.23195", \ + "0.0600443, 0.217181, 0.324568, 0.508035, 0.822338, 1.35099, 2.23206", \ + "0.0780623, 0.247641, 0.35266, 0.527765, 0.831337, 1.35236, 2.23207", \ + "0.107539, 0.302679, 0.412613, 0.587467, 0.877037, 1.37618, 2.23663", \ + "0.15893, 0.391709, 0.516932, 0.705378, 0.999637, 1.48251, 2.30244", \ + "0.246622, 0.526797, 0.68088, 0.896679, 1.22614, 1.72528, 2.53139" \ ); } } @@ -21682,25 +21756,25 @@ library (sg13g2_stdcell_fast_1p32V_m40C) { index_1 ("0.0186, 0.0966, 0.174, 0.3294, 0.6408, 1.263, 2.5074"); index_2 ("0.001, 0.0234, 0.039, 0.0648, 0.108, 0.18, 0.3"); values ( \ - "0.0229188, 0.0638305, 0.0914015, 0.13692, 0.213058, 0.339718, 0.551025", \ - "0.0423477, 0.101839, 0.13254, 0.179388, 0.255712, 0.382417, 0.593523", \ - "0.0517628, 0.128016, 0.164641, 0.217187, 0.296789, 0.424058, 0.635121", \ - "0.0619623, 0.165053, 0.212616, 0.277921, 0.370356, 0.506603, 0.720624", \ - "0.070971, 0.211755, 0.277333, 0.363228, 0.48142, 0.643552, 0.878355", \ - "0.0736411, 0.266288, 0.357461, 0.478023, 0.636225, 0.850017, 1.13773", \ - "0.0736421, 0.317627, 0.443053, 0.611903, 0.836115, 1.12571, 1.5117" \ + "0.0229189, 0.0638098, 0.0913765, 0.136924, 0.213056, 0.339774, 0.551026", \ + "0.0423477, 0.101839, 0.132533, 0.179403, 0.25566, 0.382476, 0.593569", \ + "0.0517524, 0.128016, 0.16466, 0.217186, 0.296774, 0.424029, 0.635134", \ + "0.0619623, 0.165053, 0.212616, 0.277921, 0.370353, 0.506603, 0.720624", \ + "0.070971, 0.211755, 0.277333, 0.363228, 0.481408, 0.643552, 0.878355", \ + "0.0736412, 0.266288, 0.357461, 0.478023, 0.636225, 0.850017, 1.13773", \ + "0.0736422, 0.317627, 0.443053, 0.611903, 0.836115, 1.12571, 1.5117" \ ); } rise_transition (TIMING_DELAY_7x7ds1) { index_1 ("0.0186, 0.0966, 0.174, 0.3294, 0.6408, 1.263, 2.5074"); index_2 ("0.001, 0.0234, 0.039, 0.0648, 0.108, 0.18, 0.3"); values ( \ - "0.016081, 0.0725038, 0.113437, 0.179593, 0.291185, 0.4772, 0.787373", \ - "0.0325737, 0.0865534, 0.122405, 0.184295, 0.29248, 0.477201, 0.787374", \ - "0.0449807, 0.105793, 0.14126, 0.199967, 0.302133, 0.480592, 0.787664", \ - "0.0650768, 0.142159, 0.180643, 0.239755, 0.33763, 0.504768, 0.798256", \ - "0.0963304, 0.200693, 0.247626, 0.314187, 0.415496, 0.578075, 0.852983", \ - "0.147293, 0.293501, 0.357756, 0.440526, 0.560036, 0.734103, 1.00738", \ + "0.016081, 0.0724919, 0.113442, 0.179592, 0.291182, 0.477297, 0.787374", \ + "0.0325738, 0.0865534, 0.122405, 0.18437, 0.292417, 0.477298, 0.787375", \ + "0.044956, 0.105793, 0.141394, 0.199966, 0.302188, 0.480685, 0.787376", \ + "0.0650768, 0.142159, 0.180643, 0.239755, 0.337627, 0.504769, 0.798257", \ + "0.0963304, 0.200693, 0.247626, 0.314187, 0.415486, 0.578073, 0.852983", \ + "0.147293, 0.293501, 0.357755, 0.440526, 0.560036, 0.734103, 1.00738", \ "0.232379, 0.438434, 0.529742, 0.6481, 0.797782, 1.00931, 1.31085" \ ); } @@ -21708,26 +21782,26 @@ library (sg13g2_stdcell_fast_1p32V_m40C) { index_1 ("0.0186, 0.0966, 0.174, 0.3294, 0.6408, 1.263, 2.5074"); index_2 ("0.001, 0.0234, 0.039, 0.0648, 0.108, 0.18, 0.3"); values ( \ - "0.0508976, 0.17502, 0.259887, 0.400197, 0.634886, 1.02627, 1.67822", \ - "0.0699866, 0.202298, 0.287813, 0.428518, 0.663879, 1.05506, 1.70705", \ - "0.0833206, 0.22852, 0.316042, 0.45744, 0.692825, 1.08436, 1.73605", \ - "0.102402, 0.27244, 0.366578, 0.512878, 0.750028, 1.14203, 1.794", \ - "0.134832, 0.340508, 0.448588, 0.609393, 0.858535, 1.25544, 1.90803", \ - "0.188035, 0.443382, 0.575345, 0.762882, 1.04296, 1.46806, 2.13594", \ - "0.274909, 0.599392, 0.764144, 0.997532, 1.33132, 1.81685, 2.54433" \ + "0.0508694, 0.175019, 0.259886, 0.400287, 0.634895, 1.02627, 1.67822", \ + "0.0699865, 0.202306, 0.287813, 0.428619, 0.664484, 1.05486, 1.70762", \ + "0.0833205, 0.22852, 0.316041, 0.457441, 0.692804, 1.08426, 1.73625", \ + "0.102402, 0.272439, 0.366577, 0.512878, 0.749997, 1.14203, 1.79404", \ + "0.134832, 0.340508, 0.448588, 0.609392, 0.858534, 1.25549, 1.90806", \ + "0.188035, 0.443382, 0.575344, 0.762882, 1.04296, 1.46806, 2.13593", \ + "0.274908, 0.599392, 0.764143, 0.997531, 1.33132, 1.81684, 2.54433" \ ); } fall_transition (TIMING_DELAY_7x7ds1) { index_1 ("0.0186, 0.0966, 0.174, 0.3294, 0.6408, 1.263, 2.5074"); index_2 ("0.001, 0.0234, 0.039, 0.0648, 0.108, 0.18, 0.3"); values ( \ - "0.0367242, 0.201236, 0.315642, 0.504939, 0.821859, 1.35096, 2.23193", \ - "0.0467181, 0.203635, 0.316333, 0.50494, 0.82186, 1.35097, 2.23194", \ - "0.0572921, 0.212465, 0.321764, 0.506882, 0.82252, 1.35098, 2.23195", \ - "0.0765047, 0.236165, 0.342009, 0.520722, 0.828289, 1.3523, 2.23196", \ - "0.107264, 0.283465, 0.390288, 0.564952, 0.860403, 1.36742, 2.23445", \ - "0.157229, 0.363261, 0.480937, 0.660482, 0.953793, 1.4425, 2.27877", \ - "0.241667, 0.489745, 0.627515, 0.832397, 1.14341, 1.63181, 2.44555" \ + "0.036722, 0.201235, 0.315641, 0.504951, 0.821304, 1.35096, 2.23192", \ + "0.0467181, 0.203635, 0.316334, 0.507314, 0.822734, 1.35097, 2.23193", \ + "0.057292, 0.212465, 0.321764, 0.507315, 0.822735, 1.35098, 2.23194", \ + "0.0765046, 0.236165, 0.342062, 0.520721, 0.827991, 1.35187, 2.23195", \ + "0.107264, 0.283464, 0.390287, 0.564951, 0.860403, 1.3691, 2.23341", \ + "0.157229, 0.363261, 0.480936, 0.660481, 0.95379, 1.4425, 2.27877", \ + "0.241666, 0.489745, 0.627515, 0.832395, 1.14341, 1.6318, 2.44555" \ ); } } @@ -21739,52 +21813,52 @@ library (sg13g2_stdcell_fast_1p32V_m40C) { index_1 ("0.0186, 0.0966, 0.174, 0.3294, 0.6408, 1.263, 2.5074"); index_2 ("0.001, 0.0234, 0.039, 0.0648, 0.108, 0.18, 0.3"); values ( \ - "0.0244291, 0.0658932, 0.0935918, 0.139366, 0.21556, 0.342405, 0.553667", \ - "0.0462998, 0.104383, 0.134935, 0.181809, 0.257862, 0.384931, 0.596139", \ - "0.057538, 0.131255, 0.167405, 0.219767, 0.299282, 0.426532, 0.637707", \ - "0.0706845, 0.169809, 0.216502, 0.281089, 0.373228, 0.509277, 0.723228", \ + "0.0244289, 0.0658801, 0.0936093, 0.139428, 0.215568, 0.342452, 0.553623", \ + "0.0462997, 0.104386, 0.134942, 0.181812, 0.258012, 0.384944, 0.596086", \ + "0.057538, 0.131255, 0.167401, 0.219714, 0.299281, 0.426535, 0.637827", \ + "0.0706846, 0.169809, 0.216502, 0.281089, 0.373228, 0.509277, 0.72324", \ "0.0843507, 0.219225, 0.282847, 0.367886, 0.484664, 0.646855, 0.881045", \ - "0.0951851, 0.278154, 0.366791, 0.485212, 0.641647, 0.854182, 1.14116", \ - "0.0951861, 0.338603, 0.459969, 0.624831, 0.845537, 1.13262, 1.51757" \ + "0.0951852, 0.278154, 0.366791, 0.485212, 0.641647, 0.854182, 1.14116", \ + "0.0951862, 0.338603, 0.459969, 0.624831, 0.845537, 1.13262, 1.51757" \ ); } rise_transition (TIMING_DELAY_7x7ds1) { index_1 ("0.0186, 0.0966, 0.174, 0.3294, 0.6408, 1.263, 2.5074"); index_2 ("0.001, 0.0234, 0.039, 0.0648, 0.108, 0.18, 0.3"); values ( \ - "0.0182104, 0.0751229, 0.115639, 0.182377, 0.294002, 0.480149, 0.790428", \ - "0.034679, 0.0887151, 0.124706, 0.187018, 0.295151, 0.480708, 0.790429", \ - "0.0472588, 0.108057, 0.143608, 0.202447, 0.304769, 0.483482, 0.79043", \ - "0.0681083, 0.144266, 0.182729, 0.241881, 0.339876, 0.507556, 0.801209", \ - "0.100107, 0.202726, 0.249968, 0.31677, 0.418112, 0.580855, 0.855548", \ + "0.0182097, 0.0751028, 0.115512, 0.182496, 0.294005, 0.480184, 0.790374", \ + "0.0346791, 0.0887221, 0.12473, 0.186894, 0.295187, 0.480717, 0.790375", \ + "0.0472587, 0.108057, 0.143613, 0.202396, 0.304772, 0.483513, 0.790776", \ + "0.0681083, 0.144266, 0.182729, 0.241881, 0.339876, 0.507556, 0.801279", \ + "0.100107, 0.202726, 0.249968, 0.31677, 0.417995, 0.580855, 0.855548", \ "0.151632, 0.296316, 0.359509, 0.443222, 0.562086, 0.736441, 1.0095", \ - "0.234974, 0.439878, 0.531456, 0.649393, 0.799344, 1.01185, 1.3131" \ + "0.234974, 0.439878, 0.531457, 0.649393, 0.799344, 1.01185, 1.3131" \ ); } cell_fall (TIMING_DELAY_7x7ds1) { index_1 ("0.0186, 0.0966, 0.174, 0.3294, 0.6408, 1.263, 2.5074"); index_2 ("0.001, 0.0234, 0.039, 0.0648, 0.108, 0.18, 0.3"); values ( \ - "0.0564927, 0.180546, 0.265517, 0.405913, 0.640705, 1.0319, 1.68388", \ - "0.0745629, 0.204168, 0.289639, 0.43026, 0.666272, 1.057, 1.70936", \ - "0.0867472, 0.22534, 0.312269, 0.453488, 0.688882, 1.08055, 1.73287", \ - "0.102651, 0.260424, 0.352341, 0.497193, 0.733964, 1.12568, 1.77808", \ - "0.127791, 0.31698, 0.418773, 0.574027, 0.820175, 1.21561, 1.86829", \ - "0.172216, 0.405389, 0.526264, 0.701953, 0.969519, 1.38539, 2.04916", \ - "0.244719, 0.542716, 0.691531, 0.904199, 1.21511, 1.6741, 2.3803" \ + "0.05649, 0.180546, 0.265513, 0.40591, 0.640708, 1.0319, 1.68384", \ + "0.0745624, 0.20416, 0.28964, 0.430412, 0.665503, 1.05672, 1.70888", \ + "0.086747, 0.22534, 0.312268, 0.453487, 0.688935, 1.08055, 1.73241", \ + "0.102651, 0.260424, 0.35234, 0.49719, 0.733963, 1.12568, 1.77804", \ + "0.127791, 0.31698, 0.418772, 0.574026, 0.820173, 1.21561, 1.8683", \ + "0.172216, 0.405389, 0.526498, 0.701953, 0.969517, 1.38539, 2.04916", \ + "0.244719, 0.542716, 0.69153, 0.904198, 1.21511, 1.6741, 2.38029" \ ); } fall_transition (TIMING_DELAY_7x7ds1) { index_1 ("0.0186, 0.0966, 0.174, 0.3294, 0.6408, 1.263, 2.5074"); index_2 ("0.001, 0.0234, 0.039, 0.0648, 0.108, 0.18, 0.3"); values ( \ - "0.0365965, 0.201152, 0.315642, 0.504717, 0.822394, 1.351, 2.23193", \ - "0.0435285, 0.202938, 0.316094, 0.505215, 0.8227, 1.35101, 2.23194", \ - "0.0515617, 0.209371, 0.32016, 0.506474, 0.822701, 1.35102, 2.23195", \ - "0.0689823, 0.227318, 0.335297, 0.516644, 0.826775, 1.35505, 2.23196", \ - "0.10219, 0.265449, 0.373333, 0.550068, 0.851426, 1.36323, 2.23377", \ - "0.15523, 0.337837, 0.448852, 0.628126, 0.922622, 1.42057, 2.26693", \ - "0.24219, 0.457457, 0.583374, 0.775657, 1.07798, 1.5724, 2.39608" \ + "0.0366126, 0.201173, 0.315642, 0.504748, 0.822392, 1.351, 2.23194", \ + "0.0435291, 0.202941, 0.316091, 0.5071, 0.822393, 1.35101, 2.23195", \ + "0.0515616, 0.20937, 0.32016, 0.507101, 0.822426, 1.35102, 2.23196", \ + "0.0689822, 0.227317, 0.335297, 0.516637, 0.826768, 1.35282, 2.23197", \ + "0.10219, 0.265449, 0.373333, 0.550067, 0.851424, 1.36324, 2.23236", \ + "0.15523, 0.337836, 0.449278, 0.628126, 0.922617, 1.42057, 2.26693", \ + "0.242191, 0.457457, 0.583373, 0.775657, 1.07798, 1.57239, 2.39607" \ ); } } @@ -21796,24 +21870,24 @@ library (sg13g2_stdcell_fast_1p32V_m40C) { index_1 ("0.0186, 0.0966, 0.174, 0.3294, 0.6408, 1.263, 2.5074"); index_2 ("0.001, 0.0234, 0.039, 0.0648, 0.108, 0.18, 0.3"); values ( \ - "0.0249235, 0.0672765, 0.0952074, 0.141039, 0.217278, 0.344054, 0.555065", \ - "0.0488692, 0.106125, 0.136664, 0.183526, 0.259763, 0.386574, 0.597417", \ - "0.0614934, 0.133744, 0.169585, 0.221727, 0.301123, 0.428213, 0.639157", \ - "0.0770234, 0.173485, 0.219543, 0.283566, 0.375313, 0.511075, 0.724742", \ - "0.0947658, 0.225174, 0.287679, 0.371713, 0.488048, 0.648841, 0.882516", \ + "0.0249266, 0.0672736, 0.0952061, 0.141042, 0.217253, 0.34406, 0.555064", \ + "0.0488692, 0.106125, 0.136663, 0.183484, 0.259793, 0.386442, 0.597382", \ + "0.0614935, 0.133737, 0.169584, 0.221725, 0.301095, 0.428224, 0.639096", \ + "0.0770234, 0.173485, 0.219543, 0.283566, 0.375313, 0.511074, 0.724743", \ + "0.0947658, 0.225174, 0.287679, 0.371713, 0.488048, 0.648845, 0.882516", \ "0.113266, 0.288314, 0.375138, 0.491096, 0.646227, 0.857378, 1.14347", \ - "0.126398, 0.357814, 0.475999, 0.636675, 0.853265, 1.13812, 1.52117" \ + "0.126398, 0.357814, 0.475999, 0.636675, 0.853266, 1.13812, 1.52117" \ ); } rise_transition (TIMING_DELAY_7x7ds1) { index_1 ("0.0186, 0.0966, 0.174, 0.3294, 0.6408, 1.263, 2.5074"); index_2 ("0.001, 0.0234, 0.039, 0.0648, 0.108, 0.18, 0.3"); values ( \ - "0.0200657, 0.0774547, 0.117795, 0.184575, 0.296153, 0.481956, 0.791679", \ - "0.0366107, 0.0906919, 0.126756, 0.188943, 0.297294, 0.481957, 0.79168", \ - "0.0495292, 0.109705, 0.145519, 0.204303, 0.306771, 0.485181, 0.791722", \ - "0.0711214, 0.146096, 0.18454, 0.243876, 0.341731, 0.509227, 0.802338", \ - "0.104001, 0.204826, 0.251785, 0.318118, 0.419337, 0.582045, 0.856825", \ + "0.0200652, 0.077475, 0.117808, 0.184576, 0.29598, 0.481957, 0.791679", \ + "0.0366107, 0.0906919, 0.126741, 0.189012, 0.297214, 0.481958, 0.79168", \ + "0.0495289, 0.109838, 0.145521, 0.204297, 0.306757, 0.485156, 0.793582", \ + "0.0711213, 0.146096, 0.18454, 0.243876, 0.341731, 0.509228, 0.802339", \ + "0.104001, 0.204826, 0.251785, 0.318118, 0.419337, 0.582042, 0.856825", \ "0.155951, 0.298489, 0.361177, 0.44438, 0.563864, 0.73749, 1.0107", \ "0.240882, 0.442648, 0.532698, 0.64963, 0.800497, 1.0124, 1.31592" \ ); @@ -21822,26 +21896,26 @@ library (sg13g2_stdcell_fast_1p32V_m40C) { index_1 ("0.0186, 0.0966, 0.174, 0.3294, 0.6408, 1.263, 2.5074"); index_2 ("0.001, 0.0234, 0.039, 0.0648, 0.108, 0.18, 0.3"); values ( \ - "0.0589251, 0.182988, 0.267921, 0.408238, 0.643113, 1.03432, 1.6863", \ - "0.0765057, 0.204429, 0.289868, 0.430676, 0.666502, 1.05693, 1.70909", \ - "0.087995, 0.222091, 0.30857, 0.449735, 0.684958, 1.07635, 1.72868", \ - "0.101853, 0.249795, 0.339914, 0.484056, 0.72046, 1.11219, 1.76405", \ - "0.120534, 0.294008, 0.391724, 0.543888, 0.787499, 1.18216, 1.83443", \ - "0.152058, 0.364327, 0.476713, 0.644964, 0.905123, 1.31478, 1.97526", \ - "0.206943, 0.478215, 0.611683, 0.806875, 1.09953, 1.53917, 2.23293" \ + "0.0589214, 0.182989, 0.267919, 0.408235, 0.643115, 1.03431, 1.68629", \ + "0.076522, 0.204429, 0.289874, 0.430679, 0.666507, 1.05694, 1.70897", \ + "0.0879948, 0.222091, 0.308569, 0.44973, 0.684965, 1.07636, 1.72869", \ + "0.101853, 0.249795, 0.339914, 0.484056, 0.720459, 1.11219, 1.76433", \ + "0.120534, 0.294008, 0.391723, 0.543888, 0.787498, 1.18215, 1.83441", \ + "0.152057, 0.364326, 0.476713, 0.644963, 0.905122, 1.31478, 1.97522", \ + "0.206943, 0.478214, 0.611683, 0.806874, 1.09952, 1.53917, 2.23293" \ ); } fall_transition (TIMING_DELAY_7x7ds1) { index_1 ("0.0186, 0.0966, 0.174, 0.3294, 0.6408, 1.263, 2.5074"); index_2 ("0.001, 0.0234, 0.039, 0.0648, 0.108, 0.18, 0.3"); values ( \ - "0.0365484, 0.201059, 0.315637, 0.504858, 0.822394, 1.35098, 2.23193", \ - "0.0412338, 0.202321, 0.315847, 0.507074, 0.822691, 1.35099, 2.23194", \ - "0.0468032, 0.207204, 0.318938, 0.507075, 0.822692, 1.351, 2.23195", \ - "0.0598064, 0.221088, 0.330792, 0.51404, 0.825884, 1.35101, 2.23196", \ - "0.0901063, 0.251385, 0.360397, 0.541459, 0.845321, 1.36108, 2.23254", \ - "0.146423, 0.31255, 0.423849, 0.603194, 0.903859, 1.4086, 2.26041", \ - "0.233032, 0.424334, 0.541001, 0.726933, 1.03045, 1.52862, 2.36387" \ + "0.0365484, 0.201059, 0.315401, 0.504855, 0.822392, 1.35098, 2.23192", \ + "0.0412257, 0.202321, 0.315932, 0.507072, 0.82269, 1.35099, 2.23193", \ + "0.0468031, 0.207204, 0.318938, 0.507073, 0.822691, 1.351, 2.23194", \ + "0.0598063, 0.221088, 0.330788, 0.514125, 0.825882, 1.35101, 2.23195", \ + "0.0901061, 0.251385, 0.360345, 0.541464, 0.845319, 1.36107, 2.23196", \ + "0.146423, 0.312549, 0.423849, 0.603193, 0.903857, 1.4086, 2.26035", \ + "0.233031, 0.424333, 0.541, 0.726931, 1.03044, 1.52862, 2.36386" \ ); } } @@ -21851,26 +21925,26 @@ library (sg13g2_stdcell_fast_1p32V_m40C) { index_1 ("0.0186, 0.0966, 0.174, 0.3294, 0.6408, 1.263, 2.5074"); index_2 ("0.001, 0.0234, 0.039, 0.0648, 0.108, 0.18, 0.3"); values ( \ - "0.00228876, 0.00278076, 0.00276881, 0.00267578, 0.00254971, 0.00233492, 0.00192124", \ - "0.00233252, 0.00257871, 0.00268029, 0.00261356, 0.00255025, 0.00235246, 0.00190258", \ - "0.00277339, 0.00269983, 0.00267624, 0.00269836, 0.00256186, 0.00260973, 0.00188361", \ - "0.00398996, 0.00325589, 0.0031266, 0.00299105, 0.00274304, 0.00290703, 0.00219411", \ - "0.00663528, 0.0049765, 0.00433364, 0.00405734, 0.00355653, 0.00284861, 0.00300304", \ - "0.0124433, 0.0090788, 0.00805018, 0.00694442, 0.00602281, 0.00511748, 0.00389544", \ - "0.0244145, 0.0193104, 0.0173394, 0.0150788, 0.0127836, 0.0106067, 0.00852968" \ + "0.00228876, 0.00278077, 0.00272096, 0.00269133, 0.00254971, 0.00233492, 0.00188615", \ + "0.00233241, 0.00257988, 0.00268021, 0.00262159, 0.00263785, 0.00230285, 0.00194098", \ + "0.00277341, 0.00269984, 0.00267316, 0.00269927, 0.0025633, 0.00266517, 0.00192707", \ + "0.00398987, 0.00325583, 0.0031266, 0.00299112, 0.0027431, 0.00271743, 0.00219411", \ + "0.00663584, 0.00497651, 0.00433364, 0.00405713, 0.00355653, 0.00284841, 0.00300304", \ + "0.0124437, 0.00907832, 0.00805025, 0.00694443, 0.00602281, 0.00511748, 0.00389498", \ + "0.0244154, 0.0193104, 0.0173394, 0.0150787, 0.0127836, 0.0106067, 0.00852968" \ ); } fall_power (POWER_7x7ds1) { index_1 ("0.0186, 0.0966, 0.174, 0.3294, 0.6408, 1.263, 2.5074"); index_2 ("0.001, 0.0234, 0.039, 0.0648, 0.108, 0.18, 0.3"); values ( \ - "0.00510841, 0.00553617, 0.00555399, 0.00550955, 0.00538859, 0.00519446, 0.00486839", \ - "0.00505967, 0.00525232, 0.00535213, 0.00547441, 0.00528284, 0.00512112, 0.00481509", \ - "0.00547458, 0.00529221, 0.0054072, 0.0052796, 0.00526669, 0.00504434, 0.00478514", \ - "0.0065844, 0.00576488, 0.00558539, 0.00551942, 0.00534098, 0.00506871, 0.00478516", \ - "0.00914827, 0.00735849, 0.00686429, 0.00634391, 0.00602314, 0.00554775, 0.00525081", \ - "0.0147993, 0.0113485, 0.0102572, 0.0093074, 0.00814982, 0.00711126, 0.0069779", \ - "0.0267785, 0.0208577, 0.0189293, 0.0166608, 0.0145827, 0.0123561, 0.00985754" \ + "0.00512701, 0.00554129, 0.00555458, 0.0055096, 0.00538911, 0.00519636, 0.00483558", \ + "0.00505964, 0.00525393, 0.00535215, 0.00547343, 0.00527126, 0.00512213, 0.00484904", \ + "0.00547516, 0.00529214, 0.005407, 0.00528051, 0.00521792, 0.00505333, 0.00483904", \ + "0.00658353, 0.00576543, 0.00558556, 0.00554866, 0.00534192, 0.00509833, 0.00479005", \ + "0.00914862, 0.00735817, 0.00689001, 0.00633417, 0.00604068, 0.00554795, 0.00524619", \ + "0.0148001, 0.0113483, 0.0102897, 0.00931017, 0.00811578, 0.0071112, 0.00697952", \ + "0.0267787, 0.0208554, 0.0189306, 0.0166608, 0.0145865, 0.0123561, 0.00985749" \ ); } } @@ -21880,26 +21954,26 @@ library (sg13g2_stdcell_fast_1p32V_m40C) { index_1 ("0.0186, 0.0966, 0.174, 0.3294, 0.6408, 1.263, 2.5074"); index_2 ("0.001, 0.0234, 0.039, 0.0648, 0.108, 0.18, 0.3"); values ( \ - "0.00254638, 0.00274492, 0.00282465, 0.00266366, 0.00249039, 0.00227191, 0.00183608", \ - "0.0024776, 0.00262601, 0.00270323, 0.00259104, 0.0030004, 0.0022693, 0.0018288", \ - "0.00292066, 0.00277808, 0.00268436, 0.00270622, 0.00250787, 0.00273312, 0.0018831", \ - "0.00402042, 0.00333772, 0.00320284, 0.00301142, 0.0027676, 0.00292165, 0.00213159", \ - "0.00655063, 0.00506356, 0.00448748, 0.00408927, 0.00359011, 0.002984, 0.00279295", \ - "0.012149, 0.00920584, 0.00823609, 0.00715321, 0.00616571, 0.00528586, 0.00388987", \ - "0.0236533, 0.0194564, 0.0175923, 0.0154096, 0.0131135, 0.0109129, 0.00878337" \ + "0.00254636, 0.00278694, 0.00282317, 0.00266694, 0.00249026, 0.00230017, 0.00183025", \ + "0.00247761, 0.002626, 0.0026924, 0.00260483, 0.0028891, 0.00225487, 0.00184884", \ + "0.00291917, 0.00277789, 0.00269982, 0.00270364, 0.0025179, 0.00274896, 0.00183408", \ + "0.00402052, 0.00333778, 0.00320505, 0.00301142, 0.00272648, 0.00292165, 0.00213166", \ + "0.00655025, 0.00506355, 0.00448781, 0.0040893, 0.00364809, 0.00296641, 0.00278947", \ + "0.0121492, 0.00920545, 0.0082361, 0.00715312, 0.00616571, 0.00528586, 0.00388987", \ + "0.0236535, 0.0194564, 0.0175921, 0.0154096, 0.0131135, 0.0109129, 0.00876903" \ ); } fall_power (POWER_7x7ds1) { index_1 ("0.0186, 0.0966, 0.174, 0.3294, 0.6408, 1.263, 2.5074"); index_2 ("0.001, 0.0234, 0.039, 0.0648, 0.108, 0.18, 0.3"); values ( \ - "0.00741067, 0.00772088, 0.00770638, 0.00766589, 0.00754881, 0.00732777, 0.00704026", \ - "0.00711489, 0.00742, 0.00755371, 0.00748391, 0.00743123, 0.00723638, 0.00701494", \ - "0.00723769, 0.00735339, 0.00746828, 0.00739237, 0.00737192, 0.00718018, 0.00684804", \ - "0.0079721, 0.00755647, 0.00747213, 0.00762455, 0.00738645, 0.0071941, 0.0069362", \ - "0.0102705, 0.00875812, 0.00842435, 0.00805632, 0.00791776, 0.00745427, 0.00709114", \ - "0.0156376, 0.012318, 0.0114083, 0.0105094, 0.00964022, 0.00872791, 0.00854477", \ - "0.0271079, 0.0213403, 0.0193603, 0.0173421, 0.0153936, 0.0133503, 0.0112688" \ + "0.00741122, 0.00772018, 0.00770422, 0.00767391, 0.00751615, 0.00732748, 0.00705957", \ + "0.00711298, 0.00741972, 0.00754327, 0.00765291, 0.00750373, 0.00721604, 0.00701098", \ + "0.00723768, 0.00734679, 0.00746829, 0.00739249, 0.00737018, 0.00716582, 0.00692348", \ + "0.00797207, 0.00755534, 0.0074777, 0.00762455, 0.00737288, 0.00720346, 0.00693896", \ + "0.0102712, 0.00875537, 0.00841487, 0.00805658, 0.00791796, 0.00753009, 0.00699724", \ + "0.0156368, 0.012318, 0.0114073, 0.0105124, 0.00964302, 0.00872805, 0.00856911", \ + "0.0271079, 0.0213403, 0.0193605, 0.0173417, 0.0153926, 0.0133138, 0.0112685" \ ); } } @@ -21909,26 +21983,26 @@ library (sg13g2_stdcell_fast_1p32V_m40C) { index_1 ("0.0186, 0.0966, 0.174, 0.3294, 0.6408, 1.263, 2.5074"); index_2 ("0.001, 0.0234, 0.039, 0.0648, 0.108, 0.18, 0.3"); values ( \ - "0.00283111, 0.00296019, 0.0028818, 0.00279826, 0.00264882, 0.00239822, 0.00195578", \ - "0.00275313, 0.00277311, 0.00280932, 0.00272605, 0.00265662, 0.00244918, 0.00191871", \ - "0.00312945, 0.00296017, 0.00284038, 0.00282448, 0.00259897, 0.00235544, 0.00193162", \ - "0.00425805, 0.00354877, 0.00336503, 0.00311823, 0.00283763, 0.00281471, 0.00226365", \ - "0.00700789, 0.00520152, 0.00474808, 0.00433364, 0.00375614, 0.00307163, 0.00271873", \ - "0.0125943, 0.00970858, 0.00864177, 0.00752638, 0.00642924, 0.0054762, 0.00395688", \ - "0.0245849, 0.0202904, 0.0183924, 0.0160824, 0.0137145, 0.0113857, 0.00901465" \ + "0.00283124, 0.0029596, 0.00286592, 0.00282758, 0.002652, 0.00239481, 0.00199383", \ + "0.00275317, 0.00277364, 0.00282194, 0.0026765, 0.00282521, 0.00245612, 0.00190843", \ + "0.00312802, 0.00296015, 0.0028427, 0.00282159, 0.00260126, 0.00237655, 0.0019634", \ + "0.0042594, 0.00354877, 0.00336503, 0.00311826, 0.00283717, 0.00281465, 0.00206013", \ + "0.0070085, 0.00520123, 0.00474809, 0.00433367, 0.00385337, 0.00307163, 0.002719", \ + "0.0125941, 0.00970889, 0.00864179, 0.00752638, 0.00642938, 0.0054762, 0.00395669", \ + "0.0245845, 0.0202904, 0.018392, 0.0160824, 0.0137145, 0.0113857, 0.00901465" \ ); } fall_power (POWER_7x7ds1) { index_1 ("0.0186, 0.0966, 0.174, 0.3294, 0.6408, 1.263, 2.5074"); index_2 ("0.001, 0.0234, 0.039, 0.0648, 0.108, 0.18, 0.3"); values ( \ - "0.00937316, 0.00967021, 0.00966885, 0.00961438, 0.0095158, 0.00928776, 0.00904923", \ - "0.00904357, 0.00937728, 0.00951143, 0.00946844, 0.00944827, 0.00924281, 0.00902006", \ - "0.00905285, 0.00926252, 0.00943401, 0.00934906, 0.00931944, 0.00918147, 0.0088974", \ - "0.00953829, 0.00937803, 0.00933873, 0.00944963, 0.00927228, 0.00932331, 0.00885781", \ - "0.0115921, 0.0103434, 0.0101344, 0.00978388, 0.00971373, 0.00928713, 0.00923465", \ - "0.017106, 0.0138262, 0.0129261, 0.0121771, 0.0113926, 0.0105415, 0.0101762", \ - "0.0291128, 0.0232298, 0.0211785, 0.0191482, 0.0171785, 0.0153501, 0.0133111" \ + "0.00937344, 0.00967802, 0.00966875, 0.00961818, 0.00951485, 0.00928716, 0.00900742", \ + "0.00904344, 0.00937457, 0.00948807, 0.00960101, 0.00938363, 0.00917308, 0.0089842", \ + "0.00905205, 0.00926252, 0.00943435, 0.0093495, 0.00931745, 0.0091824, 0.00881445", \ + "0.00953678, 0.0093776, 0.00933874, 0.0094232, 0.00928098, 0.00919475, 0.00885447", \ + "0.0115938, 0.0103436, 0.0101408, 0.00981781, 0.00971373, 0.00928763, 0.00920938", \ + "0.017106, 0.0138264, 0.0129504, 0.0121768, 0.0113603, 0.0105414, 0.0102463", \ + "0.0291129, 0.0232296, 0.0211785, 0.0191484, 0.0171767, 0.0153565, 0.0132767" \ ); } } @@ -21938,26 +22012,26 @@ library (sg13g2_stdcell_fast_1p32V_m40C) { index_1 ("0.0186, 0.0966, 0.174, 0.3294, 0.6408, 1.263, 2.5074"); index_2 ("0.001, 0.0234, 0.039, 0.0648, 0.108, 0.18, 0.3"); values ( \ - "0.00305597, 0.00308095, 0.00300398, 0.00293821, 0.00279197, 0.00254243, 0.00214359", \ - "0.00300316, 0.00294204, 0.00297375, 0.00285529, 0.00297232, 0.00245762, 0.00198704", \ - "0.00338195, 0.00311942, 0.00299959, 0.00298074, 0.0027306, 0.00278581, 0.00201602", \ - "0.00459594, 0.00376351, 0.0035672, 0.00331832, 0.00300606, 0.00320154, 0.0024153", \ - "0.00738907, 0.00553048, 0.00502113, 0.00453597, 0.00401768, 0.00322477, 0.00307024", \ - "0.0132226, 0.0102004, 0.00908838, 0.00784348, 0.00674662, 0.00557188, 0.00396786", \ - "0.0259258, 0.0212718, 0.0193152, 0.0168436, 0.0143046, 0.0118357, 0.00954328" \ + "0.00305663, 0.00311853, 0.00300452, 0.00293888, 0.00277237, 0.00254229, 0.00214392", \ + "0.00300324, 0.00294203, 0.00295945, 0.00285969, 0.00321599, 0.00246736, 0.0019852", \ + "0.0033821, 0.00311172, 0.0030157, 0.00298086, 0.00272803, 0.00282524, 0.00237938", \ + "0.00459374, 0.0037633, 0.00356414, 0.00331723, 0.00300606, 0.00300851, 0.00223121", \ + "0.0073886, 0.00553066, 0.00502121, 0.00453597, 0.00401768, 0.00314665, 0.00307024", \ + "0.0132221, 0.0102008, 0.00908836, 0.00784347, 0.00674662, 0.00557189, 0.00397387", \ + "0.0259259, 0.0212719, 0.0193156, 0.0168441, 0.0143038, 0.0118358, 0.00954355" \ ); } fall_power (POWER_7x7ds1) { index_1 ("0.0186, 0.0966, 0.174, 0.3294, 0.6408, 1.263, 2.5074"); index_2 ("0.001, 0.0234, 0.039, 0.0648, 0.108, 0.18, 0.3"); values ( \ - "0.0112591, 0.0115543, 0.0115499, 0.0115005, 0.0113962, 0.0111911, 0.0109443", \ - "0.0109165, 0.0112505, 0.0113877, 0.0114728, 0.0113235, 0.0110525, 0.0107702", \ - "0.0108934, 0.0111405, 0.0113196, 0.0112229, 0.0111899, 0.0109911, 0.0107562", \ - "0.0112279, 0.0111844, 0.0111451, 0.011253, 0.011112, 0.010947, 0.0107205", \ - "0.0130331, 0.0120218, 0.0118567, 0.0116594, 0.0115439, 0.0111245, 0.0112767", \ - "0.0185979, 0.0154102, 0.014593, 0.0139167, 0.0132375, 0.0124458, 0.012358", \ - "0.0313129, 0.0253159, 0.0231966, 0.0211754, 0.0192172, 0.0171698, 0.0150333" \ + "0.0112648, 0.0115569, 0.0115371, 0.0115021, 0.0113963, 0.0111929, 0.0109443", \ + "0.0109155, 0.0112505, 0.011398, 0.0114731, 0.0113304, 0.0110538, 0.0108567", \ + "0.0108938, 0.0111405, 0.011318, 0.0112236, 0.0111896, 0.010982, 0.0108134", \ + "0.0112283, 0.011192, 0.011139, 0.0113507, 0.011112, 0.0109451, 0.0107351", \ + "0.0130321, 0.0120232, 0.0118522, 0.0116162, 0.011544, 0.0111243, 0.011103", \ + "0.0185973, 0.0154105, 0.014593, 0.0139155, 0.0132267, 0.0124458, 0.0119996", \ + "0.0313128, 0.0253164, 0.0231967, 0.0211753, 0.0192152, 0.0171831, 0.0150333" \ ); } } @@ -21967,36 +22041,36 @@ library (sg13g2_stdcell_fast_1p32V_m40C) { max_transition : 2.5074; capacitance : 0.00305578; rise_capacitance : 0.00304691; - rise_capacitance_range (0.00304691, 0.00304691); + rise_capacitance_range (0.00278215, 0.00324104); fall_capacitance : 0.00306465; - fall_capacitance_range (0.00306465, 0.00306465); + fall_capacitance_range (0.00261107, 0.00398624); } pin (B) { direction : "input"; max_transition : 2.5074; capacitance : 0.00322165; rise_capacitance : 0.00331862; - rise_capacitance_range (0.00331862, 0.00331862); + rise_capacitance_range (0.00284418, 0.00360807); fall_capacitance : 0.00312469; - fall_capacitance_range (0.00312469, 0.00312469); + fall_capacitance_range (0.00277205, 0.00380189); } pin (C) { direction : "input"; max_transition : 2.5074; - capacitance : 0.00324604; - rise_capacitance : 0.00337194; - rise_capacitance_range (0.00337194, 0.00337194); - fall_capacitance : 0.00312014; - fall_capacitance_range (0.00312014, 0.00312014); + capacitance : 0.00324602; + rise_capacitance : 0.00337193; + rise_capacitance_range (0.00288202, 0.00370059); + fall_capacitance : 0.00312011; + fall_capacitance_range (0.00286504, 0.00363295); } pin (D) { direction : "input"; max_transition : 2.5074; capacitance : 0.00322226; rise_capacitance : 0.00337661; - rise_capacitance_range (0.00337661, 0.00337661); - fall_capacitance : 0.0030679; - fall_capacitance_range (0.0030679, 0.0030679); + rise_capacitance_range (0.00287966, 0.00374455); + fall_capacitance : 0.00306791; + fall_capacitance_range (0.00290442, 0.00345183); } } cell (sg13g2_nor2_1) { @@ -22202,18 +22276,18 @@ library (sg13g2_stdcell_fast_1p32V_m40C) { max_transition : 2.5074; capacitance : 0.00326736; rise_capacitance : 0.00319229; - rise_capacitance_range (0.00319229, 0.00319229); + rise_capacitance_range (0.00294228, 0.00357974); fall_capacitance : 0.00334243; - fall_capacitance_range (0.00334243, 0.00334243); + fall_capacitance_range (0.00282655, 0.00370398); } pin (B) { direction : "input"; max_transition : 2.5074; capacitance : 0.00310197; rise_capacitance : 0.00319094; - rise_capacitance_range (0.00319094, 0.00319094); + rise_capacitance_range (0.00265509, 0.00385189); fall_capacitance : 0.003013; - fall_capacitance_range (0.003013, 0.003013); + fall_capacitance_range (0.00277035, 0.00335014); } } cell (sg13g2_nor2_2) { @@ -22419,18 +22493,18 @@ library (sg13g2_stdcell_fast_1p32V_m40C) { max_transition : 2.5074; capacitance : 0.00626776; rise_capacitance : 0.00613637; - rise_capacitance_range (0.00613637, 0.00613637); + rise_capacitance_range (0.00557837, 0.0069008); fall_capacitance : 0.00639916; - fall_capacitance_range (0.00639916, 0.00639916); + fall_capacitance_range (0.00539677, 0.00714871); } pin (B) { direction : "input"; max_transition : 2.5074; capacitance : 0.00599154; rise_capacitance : 0.00617685; - rise_capacitance_range (0.00617685, 0.00617685); + rise_capacitance_range (0.00498009, 0.00758136); fall_capacitance : 0.00580622; - fall_capacitance_range (0.00580622, 0.00580622); + fall_capacitance_range (0.00525978, 0.00649992); } } cell (sg13g2_nor2b_1) { @@ -22636,18 +22710,18 @@ library (sg13g2_stdcell_fast_1p32V_m40C) { max_transition : 2.5074; capacitance : 0.0031065; rise_capacitance : 0.00319555; - rise_capacitance_range (0.00319555, 0.00319555); + rise_capacitance_range (0.00266015, 0.00385665); fall_capacitance : 0.00301745; - fall_capacitance_range (0.00301745, 0.00301745); + fall_capacitance_range (0.00277282, 0.00335437); } pin (B_N) { direction : "input"; max_transition : 2.5074; capacitance : 0.00244898; rise_capacitance : 0.00247085; - rise_capacitance_range (0.00247085, 0.00247085); + rise_capacitance_range (0.00220989, 0.00265856); fall_capacitance : 0.00242711; - fall_capacitance_range (0.00242711, 0.00242711); + fall_capacitance_range (0.00218442, 0.0026558); internal_power () { when : "A"; rise_power (passive_POWER_7x1ds1) { @@ -22882,18 +22956,18 @@ library (sg13g2_stdcell_fast_1p32V_m40C) { max_transition : 2.5074; capacitance : 0.00603297; rise_capacitance : 0.00621868; - rise_capacitance_range (0.00621868, 0.00621868); + rise_capacitance_range (0.00507472, 0.00756443); fall_capacitance : 0.00584726; - fall_capacitance_range (0.00584726, 0.00584726); + fall_capacitance_range (0.00531965, 0.00661171); } pin (B_N) { direction : "input"; max_transition : 2.5074; capacitance : 0.00288334; rise_capacitance : 0.00291823; - rise_capacitance_range (0.00291823, 0.00291823); + rise_capacitance_range (0.00265599, 0.00312089); fall_capacitance : 0.00284846; - fall_capacitance_range (0.00284846, 0.00284846); + fall_capacitance_range (0.00259589, 0.0030893); internal_power () { when : "A"; rise_power (passive_POWER_7x1ds1) { @@ -23226,27 +23300,27 @@ library (sg13g2_stdcell_fast_1p32V_m40C) { max_transition : 2.5074; capacitance : 0.00324858; rise_capacitance : 0.00315172; - rise_capacitance_range (0.00315172, 0.00315172); + rise_capacitance_range (0.002944, 0.00353102); fall_capacitance : 0.00334544; - fall_capacitance_range (0.00334544, 0.00334544); + fall_capacitance_range (0.0028303, 0.00370988); } pin (B) { direction : "input"; max_transition : 2.5074; capacitance : 0.00324573; rise_capacitance : 0.00321103; - rise_capacitance_range (0.00321103, 0.00321103); + rise_capacitance_range (0.00281261, 0.00377767); fall_capacitance : 0.00328043; - fall_capacitance_range (0.00328043, 0.00328043); + fall_capacitance_range (0.0027804, 0.00357622); } pin (C) { direction : "input"; max_transition : 2.5074; capacitance : 0.00308237; rise_capacitance : 0.0031891; - rise_capacitance_range (0.0031891, 0.0031891); + rise_capacitance_range (0.0025854, 0.00404295); fall_capacitance : 0.00297564; - fall_capacitance_range (0.00297564, 0.00297564); + fall_capacitance_range (0.00274876, 0.0031871); } } cell (sg13g2_nor3_2) { @@ -23550,27 +23624,27 @@ library (sg13g2_stdcell_fast_1p32V_m40C) { max_transition : 2.5074; capacitance : 0.00622702; rise_capacitance : 0.00605026; - rise_capacitance_range (0.00605026, 0.00605026); + rise_capacitance_range (0.00561952, 0.0067883); fall_capacitance : 0.00640378; - fall_capacitance_range (0.00640378, 0.00640378); + fall_capacitance_range (0.00534944, 0.00717148); } pin (B) { direction : "input"; max_transition : 2.5074; capacitance : 0.00618874; rise_capacitance : 0.0061378; - rise_capacitance_range (0.0061378, 0.0061378); + rise_capacitance_range (0.00528585, 0.00725544); fall_capacitance : 0.00623968; - fall_capacitance_range (0.00623968, 0.00623968); + fall_capacitance_range (0.00524101, 0.00685923); } pin (C) { direction : "input"; max_transition : 2.5074; capacitance : 0.00593207; rise_capacitance : 0.0061626; - rise_capacitance_range (0.0061626, 0.0061626); + rise_capacitance_range (0.00485572, 0.00792589); fall_capacitance : 0.00570153; - fall_capacitance_range (0.00570153, 0.00570153); + fall_capacitance_range (0.00522014, 0.00616124); } } cell (sg13g2_nor4_1) { @@ -23996,104 +24070,104 @@ library (sg13g2_stdcell_fast_1p32V_m40C) { max_transition : 2.5074; capacitance : 0.00322292; rise_capacitance : 0.00312911; - rise_capacitance_range (0.00312911, 0.00312911); + rise_capacitance_range (0.00295676, 0.00347269); fall_capacitance : 0.00331674; - fall_capacitance_range (0.00331674, 0.00331674); + fall_capacitance_range (0.00280051, 0.00369806); } pin (B) { direction : "input"; max_transition : 2.5074; capacitance : 0.00322968; rise_capacitance : 0.00318485; - rise_capacitance_range (0.00318485, 0.00318485); + rise_capacitance_range (0.00285964, 0.00367196); fall_capacitance : 0.00327451; - fall_capacitance_range (0.00327451, 0.00327451); + fall_capacitance_range (0.00275923, 0.0036058); } pin (C) { direction : "input"; max_transition : 2.5074; capacitance : 0.00318905; rise_capacitance : 0.00318893; - rise_capacitance_range (0.00318893, 0.00318893); + rise_capacitance_range (0.00274091, 0.00383878); fall_capacitance : 0.00318918; - fall_capacitance_range (0.00318918, 0.00318918); + fall_capacitance_range (0.00270621, 0.00346559); } pin (D) { direction : "input"; max_transition : 2.5074; capacitance : 0.00301037; rise_capacitance : 0.00313837; - rise_capacitance_range (0.00313837, 0.00313837); + rise_capacitance_range (0.00254453, 0.00404537); fall_capacitance : 0.00288238; - fall_capacitance_range (0.00288238, 0.00288238); + fall_capacitance_range (0.00267228, 0.00304803); } } cell (sg13g2_nor4_2) { area : 21.7728; cell_footprint : "nor4"; - cell_leakage_power : 660.427; + cell_leakage_power : 660.428; leakage_power () { - value : 632.299; + value : 632.3; when : "!A&!B&!C&!D&Y"; } leakage_power () { - value : 722.459; + value : 722.46; when : "!A&!B&!C&D&!Y"; } leakage_power () { - value : 578.059; + value : 578.06; when : "!A&!B&C&!D&!Y"; } leakage_power () { - value : 783.509; + value : 783.51; when : "!A&!B&C&D&!Y"; } leakage_power () { - value : 446.834; + value : 446.835; when : "!A&B&!C&!D&!Y"; } leakage_power () { - value : 666.41; + value : 666.412; when : "!A&B&!C&D&!Y"; } leakage_power () { - value : 650.894; + value : 650.895; when : "!A&B&C&!D&!Y"; } leakage_power () { - value : 887.114; + value : 887.115; when : "!A&B&C&D&!Y"; } leakage_power () { - value : 316.104; + value : 316.105; when : "A&!B&!C&!D&!Y"; } leakage_power () { - value : 538.526; + value : 538.527; when : "A&!B&!C&D&!Y"; } leakage_power () { - value : 534.466; + value : 534.467; when : "A&!B&C&!D&!Y"; } leakage_power () { - value : 777.479; + value : 777.481; when : "A&!B&C&D&!Y"; } leakage_power () { - value : 520.825; + value : 520.826; when : "A&B&!C&!D&!Y"; } leakage_power () { - value : 762.962; + value : 762.963; when : "A&B&!C&D&!Y"; } leakage_power () { - value : 754.89; + value : 754.891; when : "A&B&C&!D&!Y"; } leakage_power () { - value : 994.007; + value : 994.008; when : "A&B&C&D&!Y"; } pin (Y) { @@ -24109,52 +24183,52 @@ library (sg13g2_stdcell_fast_1p32V_m40C) { index_1 ("0.0186, 0.0966, 0.174, 0.3294, 0.6408, 1.263, 2.5074"); index_2 ("0.001, 0.0468, 0.078, 0.1296, 0.216, 0.36, 0.6"); values ( \ - "0.0723751, 0.245408, 0.361343, 0.552556, 0.872915, 1.40579, 2.2943", \ - "0.0896217, 0.264537, 0.38087, 0.573532, 0.893037, 1.42663, 2.31631", \ - "0.0981769, 0.278689, 0.395328, 0.587104, 0.907717, 1.44187, 2.33118", \ - "0.10688, 0.300601, 0.419832, 0.612714, 0.933381, 1.46745, 2.35754", \ - "0.115333, 0.335061, 0.460623, 0.660148, 0.983914, 1.51778, 2.40706", \ - "0.130803, 0.391953, 0.531628, 0.743455, 1.08033, 1.62246, 2.51188", \ - "0.160913, 0.483797, 0.645866, 0.882265, 1.24724, 1.81414, 2.72623" \ + "0.0723848, 0.245389, 0.361321, 0.55252, 0.872849, 1.40572, 2.29484", \ + "0.0895982, 0.264536, 0.380979, 0.573502, 0.892948, 1.42653, 2.31518", \ + "0.0981689, 0.278701, 0.395306, 0.587051, 0.907631, 1.44178, 2.32973", \ + "0.106872, 0.30058, 0.419822, 0.612688, 0.933348, 1.468, 2.35738", \ + "0.115323, 0.335041, 0.460569, 0.660104, 0.983839, 1.5176, 2.40693", \ + "0.130614, 0.391955, 0.53156, 0.743407, 1.08026, 1.62235, 2.5116", \ + "0.160899, 0.483765, 0.645825, 0.88221, 1.24716, 1.81372, 2.72606" \ ); } rise_transition (TIMING_DELAY_7x7ds1) { index_1 ("0.0186, 0.0966, 0.174, 0.3294, 0.6408, 1.263, 2.5074"); index_2 ("0.001, 0.0468, 0.078, 0.1296, 0.216, 0.36, 0.6"); values ( \ - "0.0469189, 0.28385, 0.444751, 0.711009, 1.15726, 1.89982, 3.13825", \ - "0.0511949, 0.284011, 0.444862, 0.712021, 1.15727, 1.89983, 3.13934", \ - "0.056656, 0.286951, 0.446125, 0.712022, 1.15757, 1.90039, 3.13935", \ - "0.0689767, 0.29866, 0.454461, 0.715589, 1.15781, 1.9004, 3.13936", \ - "0.0986485, 0.327275, 0.480434, 0.736015, 1.16988, 1.90389, 3.13937", \ - "0.157502, 0.387886, 0.541371, 0.793579, 1.21717, 1.93471, 3.15121", \ - "0.24536, 0.505567, 0.6633, 0.913574, 1.33601, 2.03843, 3.22754" \ + "0.0469108, 0.283829, 0.444719, 0.710959, 1.15717, 1.89969, 3.13874", \ + "0.0511858, 0.283927, 0.445446, 0.711975, 1.15718, 1.8997, 3.13974", \ + "0.0566512, 0.286899, 0.446093, 0.711976, 1.15748, 1.90025, 3.13975", \ + "0.0689711, 0.298639, 0.454435, 0.715515, 1.15753, 1.90141, 3.13976", \ + "0.0986385, 0.327257, 0.480436, 0.735966, 1.16978, 1.90387, 3.13977", \ + "0.157415, 0.387869, 0.541318, 0.793531, 1.21647, 1.93459, 3.15082", \ + "0.245348, 0.505542, 0.663265, 0.913523, 1.33622, 2.0389, 3.22733" \ ); } cell_fall (TIMING_DELAY_7x7ds1) { index_1 ("0.0186, 0.0966, 0.174, 0.3294, 0.6408, 1.263, 2.5074"); index_2 ("0.001, 0.0468, 0.078, 0.1296, 0.216, 0.36, 0.6"); values ( \ - "0.0215966, 0.0599768, 0.0838979, 0.122791, 0.187392, 0.294188, 0.471779", \ - "0.0461806, 0.100828, 0.128165, 0.168991, 0.233914, 0.34074, 0.518439", \ - "0.0611705, 0.130356, 0.163178, 0.209769, 0.279428, 0.388378, 0.566154", \ - "0.0796914, 0.172621, 0.214863, 0.273459, 0.355883, 0.476028, 0.65961", \ - "0.103444, 0.228271, 0.28644, 0.363818, 0.470236, 0.61622, 0.825968", \ - "0.132258, 0.299599, 0.379538, 0.48837, 0.63301, 0.825064, 1.08648", \ - "0.165129, 0.392133, 0.499092, 0.645361, 0.847942, 1.11573, 1.46474" \ + "0.0215886, 0.0599664, 0.0839032, 0.122785, 0.187354, 0.294124, 0.471948", \ + "0.0461754, 0.100816, 0.128153, 0.16899, 0.233911, 0.340629, 0.518331", \ + "0.0611651, 0.130341, 0.163159, 0.209742, 0.279374, 0.388322, 0.566055", \ + "0.0796842, 0.172605, 0.214791, 0.273427, 0.355842, 0.475924, 0.659547", \ + "0.103435, 0.228251, 0.286415, 0.363784, 0.470187, 0.616149, 0.825766", \ + "0.132247, 0.299576, 0.37955, 0.488366, 0.632953, 0.824983, 1.08636", \ + "0.165112, 0.392106, 0.499054, 0.645312, 0.847874, 1.11563, 1.46461" \ ); } fall_transition (TIMING_DELAY_7x7ds1) { index_1 ("0.0186, 0.0966, 0.174, 0.3294, 0.6408, 1.263, 2.5074"); index_2 ("0.001, 0.0468, 0.078, 0.1296, 0.216, 0.36, 0.6"); values ( \ - "0.0162447, 0.0636501, 0.0960323, 0.149243, 0.238671, 0.387216, 0.63491", \ - "0.0321182, 0.0790286, 0.107769, 0.156393, 0.241266, 0.38766, 0.635477", \ - "0.0447644, 0.0976635, 0.126935, 0.174408, 0.254983, 0.394988, 0.637383", \ - "0.0659416, 0.131503, 0.164864, 0.214075, 0.293715, 0.425596, 0.655028", \ - "0.100983, 0.187642, 0.227428, 0.286405, 0.371063, 0.505261, 0.722345", \ - "0.158914, 0.276481, 0.329878, 0.402788, 0.506901, 0.654629, 0.883409", \ - "0.257422, 0.421505, 0.493149, 0.592522, 0.727981, 0.91277, 1.17316" \ + "0.0162418, 0.0636352, 0.0959886, 0.149217, 0.238609, 0.387127, 0.634949", \ + "0.0321147, 0.0790222, 0.107749, 0.156392, 0.241343, 0.387607, 0.635317", \ + "0.0447607, 0.0976506, 0.126916, 0.174424, 0.254872, 0.394901, 0.637165", \ + "0.0659376, 0.131447, 0.16474, 0.214101, 0.293533, 0.425564, 0.654889", \ + "0.100978, 0.187627, 0.227407, 0.286375, 0.371012, 0.505199, 0.722139", \ + "0.158908, 0.276465, 0.329802, 0.402717, 0.506846, 0.654549, 0.882351", \ + "0.257415, 0.42148, 0.493119, 0.592467, 0.72792, 0.91268, 1.17321" \ ); } } @@ -24166,52 +24240,52 @@ library (sg13g2_stdcell_fast_1p32V_m40C) { index_1 ("0.0186, 0.0966, 0.174, 0.3294, 0.6408, 1.263, 2.5074"); index_2 ("0.001, 0.0468, 0.078, 0.1296, 0.216, 0.36, 0.6"); values ( \ - "0.069364, 0.242379, 0.358294, 0.549535, 0.869546, 1.4028, 2.29135", \ - "0.0868318, 0.263283, 0.379687, 0.571177, 0.891691, 1.42551, 2.31361", \ - "0.0958621, 0.280323, 0.396935, 0.588769, 0.909474, 1.44304, 2.33307", \ - "0.106253, 0.310134, 0.430384, 0.623733, 0.944536, 1.47843, 2.36864", \ - "0.121978, 0.359416, 0.489185, 0.689976, 1.01547, 1.54966, 2.43817", \ - "0.155152, 0.442847, 0.587652, 0.808437, 1.15048, 1.69538, 2.58569", \ - "0.209595, 0.572804, 0.747922, 0.999594, 1.37757, 1.96086, 2.87682" \ + "0.0693577, 0.242369, 0.358279, 0.549495, 0.869476, 1.4027, 2.29201", \ + "0.0867793, 0.263271, 0.379699, 0.572186, 0.891871, 1.42536, 2.31343", \ + "0.0958303, 0.280283, 0.39691, 0.588711, 0.909422, 1.44355, 2.33189", \ + "0.106246, 0.310117, 0.430357, 0.623672, 0.944621, 1.47834, 2.3684", \ + "0.121971, 0.359397, 0.488924, 0.689873, 1.01543, 1.54964, 2.43769", \ + "0.15514, 0.44282, 0.587628, 0.807527, 1.15041, 1.69528, 2.5854", \ + "0.209576, 0.572765, 0.747884, 0.999529, 1.37749, 1.96075, 2.87637" \ ); } rise_transition (TIMING_DELAY_7x7ds1) { index_1 ("0.0186, 0.0966, 0.174, 0.3294, 0.6408, 1.263, 2.5074"); index_2 ("0.001, 0.0468, 0.078, 0.1296, 0.216, 0.36, 0.6"); values ( \ - "0.0469264, 0.283637, 0.444929, 0.711009, 1.15682, 1.89982, 3.13815", \ - "0.05355, 0.284448, 0.445669, 0.711281, 1.15692, 1.90111, 3.13985", \ - "0.0614534, 0.288426, 0.446604, 0.711282, 1.15755, 1.90112, 3.13986", \ - "0.0785722, 0.303935, 0.457753, 0.717084, 1.15881, 1.90228, 3.13987", \ - "0.11347, 0.34066, 0.491018, 0.742693, 1.17275, 1.9047, 3.13988", \ - "0.169896, 0.413978, 0.563292, 0.812612, 1.23128, 1.94177, 3.15376", \ - "0.257178, 0.542299, 0.702445, 0.952372, 1.37245, 2.06758, 3.24581" \ + "0.0469226, 0.283616, 0.444907, 0.710958, 1.15674, 1.89969, 3.13908", \ + "0.0535292, 0.284438, 0.445636, 0.712216, 1.15706, 1.9008, 3.13945", \ + "0.0614507, 0.288406, 0.446581, 0.712217, 1.15747, 1.90081, 3.13946", \ + "0.078567, 0.30392, 0.457722, 0.717083, 1.15893, 1.90082, 3.13947", \ + "0.113464, 0.34064, 0.490846, 0.742563, 1.17266, 1.9047, 3.13948", \ + "0.16989, 0.413961, 0.563266, 0.811613, 1.2309, 1.94173, 3.15423", \ + "0.257168, 0.542268, 0.702413, 0.952309, 1.37238, 2.06749, 3.24507" \ ); } cell_fall (TIMING_DELAY_7x7ds1) { index_1 ("0.0186, 0.0966, 0.174, 0.3294, 0.6408, 1.263, 2.5074"); index_2 ("0.001, 0.0468, 0.078, 0.1296, 0.216, 0.36, 0.6"); values ( \ - "0.0220562, 0.0593564, 0.0829374, 0.121568, 0.186073, 0.293032, 0.471337", \ - "0.0448722, 0.0996804, 0.126955, 0.167721, 0.232629, 0.339513, 0.517608", \ - "0.0583646, 0.128488, 0.161536, 0.208194, 0.278068, 0.387129, 0.565354", \ - "0.0743433, 0.16947, 0.212215, 0.271248, 0.354082, 0.474583, 0.658771", \ - "0.0934402, 0.222643, 0.282004, 0.360485, 0.467787, 0.614594, 0.825444", \ - "0.112435, 0.289639, 0.37151, 0.482238, 0.628548, 0.822023, 1.08476", \ - "0.127485, 0.37135, 0.483335, 0.633569, 0.839516, 1.11034, 1.46159" \ + "0.0220629, 0.0593652, 0.0829305, 0.121564, 0.186068, 0.293131, 0.471334", \ + "0.0448713, 0.0996789, 0.126951, 0.167724, 0.232629, 0.339505, 0.517608", \ + "0.0583636, 0.128486, 0.161534, 0.20819, 0.278064, 0.387122, 0.565334", \ + "0.0743423, 0.169467, 0.212213, 0.271245, 0.354082, 0.474575, 0.65875", \ + "0.0934402, 0.222639, 0.282001, 0.360556, 0.467779, 0.614669, 0.825506", \ + "0.112435, 0.289638, 0.371508, 0.482233, 0.628549, 0.822015, 1.0847", \ + "0.127489, 0.371351, 0.483339, 0.633565, 0.83951, 1.11033, 1.46158" \ ); } fall_transition (TIMING_DELAY_7x7ds1) { index_1 ("0.0186, 0.0966, 0.174, 0.3294, 0.6408, 1.263, 2.5074"); index_2 ("0.001, 0.0468, 0.078, 0.1296, 0.216, 0.36, 0.6"); values ( \ - "0.014967, 0.0613157, 0.0938553, 0.146898, 0.236785, 0.385674, 0.634148", \ - "0.0297617, 0.0769155, 0.105769, 0.154332, 0.239359, 0.385884, 0.634327", \ - "0.041811, 0.0953287, 0.125064, 0.172391, 0.253097, 0.393525, 0.636234", \ - "0.0621316, 0.128838, 0.163008, 0.212045, 0.291894, 0.424183, 0.654156", \ - "0.0957806, 0.184243, 0.224623, 0.282892, 0.36866, 0.503701, 0.72121", \ - "0.152737, 0.272467, 0.326784, 0.400689, 0.505064, 0.652202, 0.881638", \ - "0.24295, 0.418516, 0.489038, 0.591561, 0.726332, 0.911419, 1.1731" \ + "0.0149629, 0.0613685, 0.0938527, 0.146894, 0.236796, 0.385578, 0.634132", \ + "0.0297613, 0.076914, 0.105757, 0.154299, 0.23939, 0.386008, 0.634315", \ + "0.0418104, 0.0953273, 0.125064, 0.172408, 0.253084, 0.393558, 0.636209", \ + "0.0621309, 0.128806, 0.163006, 0.212043, 0.291901, 0.424174, 0.654126", \ + "0.0957795, 0.183931, 0.22462, 0.282962, 0.368656, 0.503823, 0.721416", \ + "0.152734, 0.272465, 0.32678, 0.400685, 0.505026, 0.652195, 0.882784", \ + "0.242947, 0.418512, 0.489011, 0.591556, 0.726325, 0.911409, 1.17309" \ ); } } @@ -24223,52 +24297,52 @@ library (sg13g2_stdcell_fast_1p32V_m40C) { index_1 ("0.0186, 0.0966, 0.174, 0.3294, 0.6408, 1.263, 2.5074"); index_2 ("0.001, 0.0468, 0.078, 0.1296, 0.216, 0.36, 0.6"); values ( \ - "0.0596621, 0.232726, 0.348584, 0.539839, 0.859898, 1.39312, 2.28168", \ - "0.07649, 0.255516, 0.371918, 0.563505, 0.883969, 1.4175, 2.3062", \ - "0.086387, 0.277417, 0.39429, 0.586151, 0.906799, 1.44096, 2.32942", \ - "0.100691, 0.317573, 0.439355, 0.633328, 0.954153, 1.4886, 2.3782", \ - "0.127236, 0.383198, 0.517517, 0.722202, 1.04893, 1.58331, 2.4733", \ - "0.173184, 0.487736, 0.644649, 0.876203, 1.22636, 1.77653, 2.66812", \ - "0.246049, 0.646765, 0.839877, 1.11399, 1.51621, 2.11865, 3.05042" \ + "0.0596597, 0.232712, 0.348735, 0.53979, 0.859883, 1.39297, 2.28152", \ + "0.0764859, 0.255473, 0.371697, 0.563406, 0.883914, 1.4174, 2.30604", \ + "0.0863827, 0.27742, 0.394323, 0.586087, 0.906729, 1.44103, 2.33007", \ + "0.100685, 0.317557, 0.439422, 0.633271, 0.954149, 1.48847, 2.37748", \ + "0.127233, 0.383181, 0.517574, 0.722136, 1.04889, 1.58335, 2.47241", \ + "0.173174, 0.487715, 0.644622, 0.875847, 1.22631, 1.77637, 2.66791", \ + "0.246032, 0.646737, 0.839842, 1.11394, 1.51614, 2.11864, 3.05025" \ ); } rise_transition (TIMING_DELAY_7x7ds1) { index_1 ("0.0186, 0.0966, 0.174, 0.3294, 0.6408, 1.263, 2.5074"); index_2 ("0.001, 0.0468, 0.078, 0.1296, 0.216, 0.36, 0.6"); values ( \ - "0.046957, 0.283732, 0.444767, 0.711148, 1.15682, 1.89982, 3.13815", \ - "0.0566974, 0.284684, 0.446467, 0.711303, 1.15683, 1.89983, 3.13816", \ - "0.0669458, 0.290537, 0.447441, 0.711388, 1.15751, 1.90037, 3.13817", \ - "0.0862867, 0.311312, 0.462306, 0.718908, 1.15845, 1.90059, 3.13927", \ - "0.118384, 0.356769, 0.504651, 0.752629, 1.1777, 1.9056, 3.13973", \ - "0.170014, 0.437628, 0.593298, 0.841021, 1.25368, 1.95395, 3.15911", \ - "0.255096, 0.575078, 0.746394, 1.0106, 1.43067, 2.1176, 3.27483" \ + "0.0469491, 0.283743, 0.44486, 0.71136, 1.15686, 1.89958, 3.13793", \ + "0.0566922, 0.284628, 0.445218, 0.711361, 1.15687, 1.89969, 3.13794", \ + "0.0669411, 0.290546, 0.447484, 0.71173, 1.15742, 1.90033, 3.13897", \ + "0.0862822, 0.311291, 0.462289, 0.718853, 1.15939, 1.90044, 3.14026", \ + "0.118322, 0.35675, 0.504986, 0.752383, 1.17752, 1.90614, 3.14027", \ + "0.170008, 0.437608, 0.593223, 0.840512, 1.25361, 1.95382, 3.15809", \ + "0.255088, 0.575058, 0.746366, 1.01056, 1.43061, 2.11782, 3.27484" \ ); } cell_fall (TIMING_DELAY_7x7ds1) { index_1 ("0.0186, 0.0966, 0.174, 0.3294, 0.6408, 1.263, 2.5074"); index_2 ("0.001, 0.0468, 0.078, 0.1296, 0.216, 0.36, 0.6"); values ( \ - "0.0211542, 0.0574062, 0.0806916, 0.119065, 0.183371, 0.290117, 0.468415", \ - "0.0412298, 0.0972367, 0.124556, 0.165357, 0.230103, 0.336866, 0.514757", \ - "0.0525416, 0.125153, 0.158561, 0.205478, 0.275416, 0.384491, 0.56266", \ - "0.0648927, 0.164503, 0.20801, 0.267794, 0.350929, 0.471747, 0.656029", \ - "0.0777825, 0.214754, 0.275695, 0.355437, 0.46364, 0.611024, 0.822781", \ - "0.0870147, 0.276971, 0.361245, 0.473929, 0.622143, 0.81701, 1.08098", \ - "0.0870157, 0.348408, 0.465278, 0.619437, 0.828554, 1.10248, 1.45655" \ + "0.0211543, 0.057406, 0.0806956, 0.119065, 0.183367, 0.290043, 0.468412", \ + "0.0412294, 0.0972365, 0.124553, 0.165357, 0.230104, 0.336857, 0.514763", \ + "0.0525411, 0.125153, 0.158561, 0.205477, 0.275449, 0.384504, 0.562669", \ + "0.0648922, 0.164449, 0.20801, 0.267793, 0.350929, 0.471746, 0.656031", \ + "0.0777826, 0.214754, 0.275694, 0.355433, 0.46364, 0.611259, 0.822849", \ + "0.0870177, 0.276971, 0.361243, 0.47393, 0.622143, 0.81701, 1.08098", \ + "0.0870187, 0.348411, 0.46528, 0.619438, 0.828554, 1.10248, 1.45655" \ ); } fall_transition (TIMING_DELAY_7x7ds1) { index_1 ("0.0186, 0.0966, 0.174, 0.3294, 0.6408, 1.263, 2.5074"); index_2 ("0.001, 0.0468, 0.078, 0.1296, 0.216, 0.36, 0.6"); values ( \ - "0.0127091, 0.0583995, 0.0907523, 0.143908, 0.233601, 0.382544, 0.631049", \ - "0.0267805, 0.0743553, 0.103143, 0.151573, 0.236379, 0.382971, 0.631791", \ - "0.0384114, 0.0928024, 0.122322, 0.169814, 0.250326, 0.390505, 0.633026", \ - "0.058076, 0.125989, 0.159563, 0.209548, 0.289311, 0.421439, 0.651208", \ - "0.0902399, 0.180184, 0.221421, 0.279905, 0.366386, 0.501371, 0.71926", \ - "0.142727, 0.26844, 0.322715, 0.397559, 0.502341, 0.650479, 0.879715", \ - "0.230627, 0.413793, 0.485822, 0.586357, 0.723301, 0.908217, 1.16919" \ + "0.0127089, 0.0583993, 0.0909256, 0.143906, 0.233599, 0.382648, 0.631049", \ + "0.0267803, 0.0743552, 0.103138, 0.151573, 0.236413, 0.382955, 0.6318", \ + "0.0384113, 0.0928024, 0.122322, 0.169794, 0.250305, 0.390479, 0.633161", \ + "0.0580756, 0.125902, 0.159563, 0.209548, 0.289311, 0.421439, 0.651268", \ + "0.090239, 0.180184, 0.221421, 0.279915, 0.366386, 0.501131, 0.719317", \ + "0.14272, 0.268439, 0.322719, 0.397559, 0.50234, 0.650478, 0.879715", \ + "0.230693, 0.413791, 0.485821, 0.586357, 0.7233, 0.908216, 1.16919" \ ); } } @@ -24280,52 +24354,52 @@ library (sg13g2_stdcell_fast_1p32V_m40C) { index_1 ("0.0186, 0.0966, 0.174, 0.3294, 0.6408, 1.263, 2.5074"); index_2 ("0.001, 0.0468, 0.078, 0.1296, 0.216, 0.36, 0.6"); values ( \ - "0.0408907, 0.215499, 0.331713, 0.523168, 0.843082, 1.37637, 2.26499", \ - "0.0611708, 0.241047, 0.35737, 0.549318, 0.870016, 1.40304, 2.29297", \ - "0.0743253, 0.268492, 0.384614, 0.575776, 0.896001, 1.43008, 2.31866", \ - "0.0941256, 0.318189, 0.440759, 0.63372, 0.95323, 1.48641, 2.37545", \ - "0.124622, 0.394455, 0.533504, 0.741529, 1.06749, 1.59921, 2.48555", \ - "0.173898, 0.50903, 0.674414, 0.918049, 1.27779, 1.83084, 2.71952", \ - "0.253822, 0.677484, 0.882597, 1.17578, 1.60384, 2.22933, 3.17416" \ + "0.0408884, 0.215498, 0.331692, 0.523132, 0.843079, 1.37627, 2.26484", \ + "0.0611684, 0.241033, 0.35729, 0.54928, 0.869618, 1.40334, 2.29281", \ + "0.0743222, 0.268479, 0.384591, 0.575761, 0.89595, 1.42998, 2.31917", \ + "0.0941209, 0.318177, 0.440737, 0.633678, 0.953129, 1.48636, 2.37534", \ + "0.124617, 0.39444, 0.533482, 0.741496, 1.06744, 1.5993, 2.48574", \ + "0.173889, 0.509016, 0.674529, 0.918013, 1.27759, 1.83075, 2.71932", \ + "0.253807, 0.677456, 0.882564, 1.17573, 1.60378, 2.22924, 3.17445" \ ); } rise_transition (TIMING_DELAY_7x7ds1) { index_1 ("0.0186, 0.0966, 0.174, 0.3294, 0.6408, 1.263, 2.5074"); index_2 ("0.001, 0.0468, 0.078, 0.1296, 0.216, 0.36, 0.6"); values ( \ - "0.0458013, 0.283626, 0.44488, 0.711255, 1.15755, 1.89982, 3.13815", \ - "0.0574805, 0.284759, 0.444974, 0.711694, 1.15756, 1.89983, 3.13929", \ - "0.0665832, 0.293184, 0.448522, 0.71172, 1.15757, 1.90035, 3.14001", \ - "0.0822509, 0.320664, 0.469432, 0.722305, 1.16018, 1.90047, 3.14002", \ - "0.111177, 0.374528, 0.525203, 0.769585, 1.18773, 1.90899, 3.14029", \ - "0.161591, 0.464743, 0.630005, 0.882474, 1.29271, 1.98053, 3.16993", \ - "0.247501, 0.615551, 0.798616, 1.0838, 1.51532, 2.20422, 3.33974" \ + "0.0457948, 0.283896, 0.444847, 0.711205, 1.15679, 1.89969, 3.13793", \ + "0.0574766, 0.284738, 0.446797, 0.711638, 1.1568, 1.90078, 3.13907", \ + "0.0665792, 0.293164, 0.448224, 0.711695, 1.15725, 1.90079, 3.13908", \ + "0.0822467, 0.320542, 0.469402, 0.72225, 1.15941, 1.9008, 3.13909", \ + "0.111173, 0.374502, 0.525174, 0.769548, 1.18793, 1.90947, 3.1391", \ + "0.161585, 0.464738, 0.629216, 0.882432, 1.29297, 1.98041, 3.17007", \ + "0.247494, 0.615532, 0.798598, 1.08376, 1.51579, 2.2043, 3.34019" \ ); } cell_fall (TIMING_DELAY_7x7ds1) { index_1 ("0.0186, 0.0966, 0.174, 0.3294, 0.6408, 1.263, 2.5074"); index_2 ("0.001, 0.0468, 0.078, 0.1296, 0.216, 0.36, 0.6"); values ( \ - "0.0179934, 0.0545587, 0.0776869, 0.115824, 0.179892, 0.286179, 0.46386", \ - "0.0338588, 0.0935807, 0.121136, 0.162121, 0.226757, 0.333087, 0.510447", \ - "0.0417616, 0.120513, 0.154466, 0.201811, 0.271843, 0.380708, 0.558377", \ - "0.0489543, 0.157803, 0.202593, 0.263097, 0.346781, 0.467658, 0.651632", \ - "0.053598, 0.204688, 0.267621, 0.348927, 0.457901, 0.606134, 0.817926", \ - "0.053599, 0.26176, 0.348667, 0.464184, 0.61455, 0.810707, 1.07466", \ - "0.0536, 0.322499, 0.444555, 0.602912, 0.816303, 1.0933, 1.44833" \ + "0.0179944, 0.0545589, 0.0776679, 0.115856, 0.179892, 0.286178, 0.463856", \ + "0.0338582, 0.0935911, 0.121149, 0.162119, 0.226755, 0.333087, 0.510431", \ + "0.041761, 0.120513, 0.154465, 0.20181, 0.271843, 0.380708, 0.55837", \ + "0.0489538, 0.157802, 0.202592, 0.263097, 0.346781, 0.467708, 0.651631", \ + "0.0535692, 0.204688, 0.267621, 0.348926, 0.457901, 0.606134, 0.817926", \ + "0.0535702, 0.261761, 0.348667, 0.464184, 0.614801, 0.810708, 1.07466", \ + "0.0535712, 0.322501, 0.444557, 0.602913, 0.816304, 1.0933, 1.44833" \ ); } fall_transition (TIMING_DELAY_7x7ds1) { index_1 ("0.0186, 0.0966, 0.174, 0.3294, 0.6408, 1.263, 2.5074"); index_2 ("0.001, 0.0468, 0.078, 0.1296, 0.216, 0.36, 0.6"); values ( \ - "0.0100319, 0.0550421, 0.0872431, 0.140455, 0.229443, 0.377865, 0.625422", \ - "0.0234721, 0.0713985, 0.0999665, 0.14806, 0.23251, 0.378353, 0.625468", \ - "0.0347325, 0.089777, 0.119171, 0.166461, 0.24646, 0.385837, 0.627547", \ - "0.0534544, 0.122306, 0.156346, 0.20616, 0.285731, 0.417047, 0.645895", \ - "0.0845167, 0.176972, 0.218061, 0.276774, 0.362558, 0.497376, 0.714115", \ - "0.135953, 0.263993, 0.320099, 0.395492, 0.498337, 0.646579, 0.875072", \ - "0.224319, 0.411811, 0.483468, 0.584515, 0.722604, 0.904839, 1.16475" \ + "0.0100318, 0.0550334, 0.087075, 0.140256, 0.229444, 0.377964, 0.625422", \ + "0.023472, 0.0713169, 0.100052, 0.148065, 0.232509, 0.378353, 0.626498", \ + "0.0347323, 0.089777, 0.11917, 0.166461, 0.24646, 0.385837, 0.627561", \ + "0.053454, 0.122305, 0.156346, 0.20616, 0.285731, 0.41707, 0.645894", \ + "0.0844802, 0.176972, 0.218061, 0.276774, 0.362558, 0.497376, 0.714115", \ + "0.135951, 0.263993, 0.320097, 0.395492, 0.497943, 0.646585, 0.875071", \ + "0.224319, 0.411809, 0.483466, 0.584514, 0.722603, 0.90484, 1.16475" \ ); } } @@ -24335,26 +24409,26 @@ library (sg13g2_stdcell_fast_1p32V_m40C) { index_1 ("0.0186, 0.0966, 0.174, 0.3294, 0.6408, 1.263, 2.5074"); index_2 ("0.001, 0.0468, 0.078, 0.1296, 0.216, 0.36, 0.6"); values ( \ - "0.0246112, 0.0251285, 0.0250941, 0.0249922, 0.0246997, 0.0246994, 0.0245331", \ - "0.0241113, 0.0248489, 0.0246837, 0.0247939, 0.0244965, 0.0245163, 0.0244384", \ - "0.0240867, 0.0243917, 0.0244479, 0.0245116, 0.0243812, 0.0244519, 0.0242604", \ - "0.0245061, 0.0243457, 0.0244786, 0.0245453, 0.0242339, 0.0242351, 0.0243788", \ - "0.0273498, 0.0258138, 0.0253791, 0.0252271, 0.0245656, 0.02515, 0.0244376", \ - "0.0374714, 0.0319428, 0.0307604, 0.0294841, 0.0279218, 0.0277707, 0.0266908", \ - "0.0614875, 0.0507682, 0.0474878, 0.0436738, 0.0402205, 0.0360338, 0.0340866" \ + "0.0246103, 0.0251152, 0.0250915, 0.0249741, 0.0246835, 0.0246993, 0.0245396", \ + "0.0241205, 0.0248393, 0.0247404, 0.0247747, 0.0244845, 0.0245175, 0.0242886", \ + "0.0240825, 0.0243814, 0.0244463, 0.0245067, 0.0243871, 0.0244451, 0.0243474", \ + "0.0245015, 0.0243617, 0.024562, 0.0243277, 0.0242253, 0.0239199, 0.0243788", \ + "0.0273465, 0.0258033, 0.0253428, 0.0252146, 0.0245917, 0.0261683, 0.0243896", \ + "0.0374671, 0.0319421, 0.0307544, 0.0294475, 0.0278913, 0.0277555, 0.0259738", \ + "0.0614882, 0.050768, 0.0474844, 0.0436753, 0.0401901, 0.0359621, 0.0339104" \ ); } fall_power (POWER_7x7ds1) { index_1 ("0.0186, 0.0966, 0.174, 0.3294, 0.6408, 1.263, 2.5074"); index_2 ("0.001, 0.0468, 0.078, 0.1296, 0.216, 0.36, 0.6"); values ( \ - "0.0071, 0.00708333, 0.00697298, 0.00678224, 0.0065883, 0.0060913, 0.00530715", \ - "0.00676695, 0.00676639, 0.00664012, 0.00675665, 0.00661159, 0.00586059, 0.00531785", \ - "0.00724236, 0.00698082, 0.00686496, 0.00652992, 0.00659556, 0.00598254, 0.0050208", \ - "0.00907657, 0.00775395, 0.00757943, 0.00730394, 0.00652018, 0.00635866, 0.00530778", \ - "0.014033, 0.0107775, 0.00983285, 0.00927486, 0.0084447, 0.00735853, 0.00579624", \ - "0.0251618, 0.0188083, 0.0165795, 0.0145666, 0.0126189, 0.0109817, 0.00943091", \ - "0.0491658, 0.03917, 0.035028, 0.0303089, 0.0252614, 0.0204132, 0.0170934" \ + "0.00712583, 0.00708789, 0.00698803, 0.00679132, 0.00661227, 0.00609455, 0.00546846", \ + "0.00676243, 0.00673014, 0.00664806, 0.00675976, 0.00653883, 0.00581647, 0.00528805", \ + "0.00725345, 0.00698653, 0.00685102, 0.00653506, 0.00660954, 0.00598544, 0.00502606", \ + "0.00908518, 0.00776238, 0.00755663, 0.00731531, 0.00664452, 0.00637608, 0.00571517", \ + "0.0140319, 0.0107791, 0.0098362, 0.00926376, 0.00847918, 0.0073776, 0.00560279", \ + "0.0251655, 0.0187993, 0.0165717, 0.0145691, 0.0125969, 0.0109894, 0.00915985", \ + "0.0491788, 0.0391756, 0.0350318, 0.0303134, 0.0252656, 0.0204204, 0.0172409" \ ); } } @@ -24364,26 +24438,26 @@ library (sg13g2_stdcell_fast_1p32V_m40C) { index_1 ("0.0186, 0.0966, 0.174, 0.3294, 0.6408, 1.263, 2.5074"); index_2 ("0.001, 0.0468, 0.078, 0.1296, 0.216, 0.36, 0.6"); values ( \ - "0.0197922, 0.0203219, 0.0203128, 0.0201971, 0.0198981, 0.0199226, 0.0195297", \ - "0.0193236, 0.0199896, 0.0199741, 0.0199141, 0.0197176, 0.0197267, 0.0197616", \ - "0.0193408, 0.0195984, 0.0196629, 0.0196653, 0.0195368, 0.0195138, 0.0194845", \ - "0.0199967, 0.019672, 0.0198678, 0.0197285, 0.0195944, 0.0196979, 0.019458", \ - "0.0233693, 0.0213923, 0.0208857, 0.020572, 0.0199073, 0.0200778, 0.0196483", \ - "0.0334837, 0.0279247, 0.0263218, 0.0248854, 0.023266, 0.0222761, 0.0215822", \ - "0.0557869, 0.0455188, 0.0422665, 0.0384834, 0.0349283, 0.0309029, 0.0286635" \ + "0.0197893, 0.0203259, 0.020318, 0.0201965, 0.0198858, 0.019922, 0.0196134", \ + "0.019322, 0.0199881, 0.0199747, 0.0200317, 0.0197484, 0.0198632, 0.0195798", \ + "0.0193373, 0.0195938, 0.0196661, 0.0196762, 0.0195356, 0.0196608, 0.0195533", \ + "0.0199955, 0.0196923, 0.0198476, 0.0197234, 0.019589, 0.0194972, 0.019373", \ + "0.0233696, 0.0213954, 0.0208676, 0.020574, 0.0198423, 0.0211555, 0.0196714", \ + "0.0334933, 0.0279238, 0.0263252, 0.0248195, 0.0232605, 0.0224116, 0.0211804", \ + "0.0557867, 0.0455239, 0.0422635, 0.0384791, 0.0349286, 0.0309067, 0.028608" \ ); } fall_power (POWER_7x7ds1) { index_1 ("0.0186, 0.0966, 0.174, 0.3294, 0.6408, 1.263, 2.5074"); index_2 ("0.001, 0.0468, 0.078, 0.1296, 0.216, 0.36, 0.6"); values ( \ - "0.00674087, 0.00675524, 0.00678812, 0.00650225, 0.00637372, 0.00586553, 0.00513656", \ - "0.00626146, 0.00648931, 0.00642877, 0.00654733, 0.00622279, 0.00561325, 0.00508504", \ - "0.00671542, 0.00665712, 0.0066418, 0.00633479, 0.00642271, 0.00591384, 0.00483542", \ - "0.00847978, 0.00736874, 0.00737749, 0.00704949, 0.0063336, 0.0062481, 0.00566207", \ - "0.0131558, 0.0101744, 0.00926615, 0.0086558, 0.00813024, 0.00685251, 0.00581748", \ - "0.0236899, 0.0177779, 0.0157224, 0.0139003, 0.0120344, 0.010443, 0.00884005", \ - "0.0458803, 0.0366976, 0.0329474, 0.0288445, 0.0240229, 0.0195274, 0.0165893" \ + "0.00672443, 0.00676072, 0.00678848, 0.00650981, 0.00635828, 0.0059077, 0.00513883", \ + "0.00626075, 0.00649469, 0.00641927, 0.00654295, 0.00621736, 0.00563939, 0.00508863", \ + "0.00671539, 0.00665265, 0.0066563, 0.00630979, 0.00640988, 0.00594846, 0.00483208", \ + "0.00848262, 0.00736171, 0.00738766, 0.00708274, 0.00633079, 0.00624801, 0.00567531", \ + "0.0131552, 0.010147, 0.00927547, 0.00866805, 0.00812471, 0.00670144, 0.00561602", \ + "0.0236897, 0.0177784, 0.0157217, 0.0139005, 0.0120352, 0.0104426, 0.00915353", \ + "0.0458822, 0.036698, 0.03295, 0.0288453, 0.0240242, 0.0195295, 0.0165633" \ ); } } @@ -24393,26 +24467,26 @@ library (sg13g2_stdcell_fast_1p32V_m40C) { index_1 ("0.0186, 0.0966, 0.174, 0.3294, 0.6408, 1.263, 2.5074"); index_2 ("0.001, 0.0468, 0.078, 0.1296, 0.216, 0.36, 0.6"); values ( \ - "0.015002, 0.0155437, 0.0155016, 0.0154142, 0.0151466, 0.0151325, 0.0147312", \ - "0.0145499, 0.0153187, 0.0152499, 0.0150818, 0.0149227, 0.014991, 0.0147227", \ - "0.014774, 0.0149057, 0.014886, 0.0148994, 0.0148117, 0.0148742, 0.0147207", \ - "0.0160253, 0.0152068, 0.0152619, 0.0150644, 0.014746, 0.0147665, 0.0148092", \ - "0.0201767, 0.0174681, 0.0167367, 0.0162961, 0.0154387, 0.0162246, 0.0150346", \ - "0.0300575, 0.0242574, 0.0226756, 0.0209831, 0.0190764, 0.0181802, 0.0169209", \ - "0.0509826, 0.0409916, 0.0378775, 0.0344556, 0.0306507, 0.0262276, 0.0243176" \ + "0.0149951, 0.0155316, 0.0155142, 0.0153957, 0.0151395, 0.0150975, 0.0147315", \ + "0.014552, 0.0150099, 0.0151288, 0.0150966, 0.014918, 0.0149917, 0.0147233", \ + "0.0147764, 0.0148647, 0.0149062, 0.0149254, 0.0148112, 0.0148323, 0.0146624", \ + "0.0160234, 0.0152195, 0.0152636, 0.0150747, 0.0148001, 0.0147945, 0.0148991", \ + "0.0201769, 0.0174556, 0.016748, 0.01623, 0.0153411, 0.0162795, 0.0148513", \ + "0.0300558, 0.0242534, 0.0226654, 0.0210067, 0.0191703, 0.0189358, 0.016595", \ + "0.0510003, 0.0410008, 0.0378796, 0.034457, 0.030616, 0.0262704, 0.0235243" \ ); } fall_power (POWER_7x7ds1) { index_1 ("0.0186, 0.0966, 0.174, 0.3294, 0.6408, 1.263, 2.5074"); index_2 ("0.001, 0.0468, 0.078, 0.1296, 0.216, 0.36, 0.6"); values ( \ - "0.00549537, 0.00579931, 0.00581009, 0.00557892, 0.00539843, 0.00495072, 0.00428475", \ - "0.00517638, 0.00573905, 0.00569545, 0.00581199, 0.00563379, 0.00495963, 0.00467159", \ - "0.00569824, 0.00581906, 0.0058408, 0.00561816, 0.00574199, 0.00509958, 0.00416673", \ - "0.00756668, 0.00649642, 0.00641635, 0.00632323, 0.00564043, 0.00558025, 0.00512423", \ - "0.0121237, 0.00908921, 0.00847081, 0.00777603, 0.00743638, 0.00632049, 0.00508349", \ - "0.0221704, 0.0164297, 0.0145458, 0.0127896, 0.0110645, 0.00982795, 0.00827573", \ - "0.0431797, 0.0343536, 0.0308372, 0.0268583, 0.0224168, 0.0182324, 0.0155211" \ + "0.00549504, 0.00579925, 0.00589797, 0.00558742, 0.00541614, 0.00493871, 0.0042825", \ + "0.00517295, 0.00573895, 0.00569306, 0.00581189, 0.00548772, 0.00494694, 0.00466881", \ + "0.00570277, 0.00582048, 0.00587887, 0.00559613, 0.0057572, 0.0051332, 0.00415002", \ + "0.00756295, 0.00647737, 0.00641799, 0.00632332, 0.00563968, 0.00552823, 0.00459192", \ + "0.0121198, 0.00908922, 0.00847095, 0.00774258, 0.00744228, 0.0063199, 0.00506821", \ + "0.0221712, 0.01643, 0.0145456, 0.0127898, 0.0110645, 0.0098279, 0.00827751", \ + "0.0432175, 0.0343543, 0.0308397, 0.0268595, 0.0224173, 0.0182328, 0.0155218" \ ); } } @@ -24422,26 +24496,26 @@ library (sg13g2_stdcell_fast_1p32V_m40C) { index_1 ("0.0186, 0.0966, 0.174, 0.3294, 0.6408, 1.263, 2.5074"); index_2 ("0.001, 0.0468, 0.078, 0.1296, 0.216, 0.36, 0.6"); values ( \ - "0.00932796, 0.0103186, 0.0103621, 0.0102563, 0.0100505, 0.0100284, 0.00963442", \ - "0.00966754, 0.00989989, 0.00987715, 0.00993528, 0.00976186, 0.00977899, 0.00960893", \ - "0.0106539, 0.00998638, 0.00990136, 0.00984199, 0.00970165, 0.00976523, 0.00967053", \ - "0.0129492, 0.0110108, 0.0108384, 0.0105208, 0.00996962, 0.00979795, 0.00981131", \ - "0.0179078, 0.0144535, 0.0134081, 0.0125585, 0.0111768, 0.0116969, 0.0103444", \ - "0.0281973, 0.0220863, 0.0202564, 0.0182279, 0.0159273, 0.0140802, 0.0124315", \ - "0.0502045, 0.0400283, 0.0367031, 0.0330792, 0.0289605, 0.0237407, 0.0216177" \ + "0.0093223, 0.0103313, 0.0103619, 0.0102558, 0.00999463, 0.0100252, 0.00963516", \ + "0.00965876, 0.00990075, 0.0100483, 0.00993478, 0.009713, 0.00991462, 0.0096094", \ + "0.0106532, 0.0100172, 0.00990191, 0.0098436, 0.00970149, 0.00976483, 0.00954081", \ + "0.0129448, 0.01101, 0.0108378, 0.0102804, 0.00995738, 0.00979805, 0.00957275", \ + "0.0179066, 0.0144402, 0.0133811, 0.0125726, 0.0113206, 0.011879, 0.010201", \ + "0.0281983, 0.0220818, 0.0202365, 0.0181841, 0.0158824, 0.0141593, 0.0124489", \ + "0.0502061, 0.0400132, 0.036699, 0.0330837, 0.0289961, 0.0239063, 0.0208624" \ ); } fall_power (POWER_7x7ds1) { index_1 ("0.0186, 0.0966, 0.174, 0.3294, 0.6408, 1.263, 2.5074"); index_2 ("0.001, 0.0468, 0.078, 0.1296, 0.216, 0.36, 0.6"); values ( \ - "0.00401495, 0.00503277, 0.00511518, 0.00502813, 0.0047811, 0.00426477, 0.00364364", \ - "0.00408337, 0.00496581, 0.00498522, 0.0051829, 0.0049927, 0.00451555, 0.00387277", \ - "0.00477835, 0.0050759, 0.00516514, 0.00502583, 0.00513481, 0.00468215, 0.00380279", \ - "0.0069608, 0.00566862, 0.00568831, 0.00562682, 0.00516189, 0.00495642, 0.00438833", \ - "0.0118085, 0.00835559, 0.00767365, 0.00705551, 0.00669287, 0.0057066, 0.00452991", \ - "0.0224503, 0.0155417, 0.0135846, 0.0120231, 0.010089, 0.00916976, 0.00763169", \ - "0.0446068, 0.0337635, 0.0297056, 0.0256272, 0.0214534, 0.0173082, 0.0145631" \ + "0.00401398, 0.00502636, 0.00506448, 0.00496791, 0.00476823, 0.00432192, 0.00359448", \ + "0.00408593, 0.0049816, 0.00499474, 0.00518441, 0.00495822, 0.00451547, 0.00439103", \ + "0.00477659, 0.0050752, 0.00515877, 0.00503125, 0.00513348, 0.00468213, 0.00379865", \ + "0.0069613, 0.00566831, 0.00569101, 0.00562166, 0.00518046, 0.00498432, 0.00439758", \ + "0.0118065, 0.00835132, 0.0076733, 0.0070561, 0.00669258, 0.00571039, 0.00452996", \ + "0.0224505, 0.0155418, 0.013585, 0.012023, 0.0101098, 0.0091087, 0.0076315", \ + "0.0446739, 0.0337663, 0.029707, 0.0256284, 0.0214541, 0.0173085, 0.0145625" \ ); } } @@ -24449,74 +24523,74 @@ library (sg13g2_stdcell_fast_1p32V_m40C) { pin (A) { direction : "input"; max_transition : 2.5074; - capacitance : 0.00623241; - rise_capacitance : 0.00604557; - rise_capacitance_range (0.00604557, 0.00604557); - fall_capacitance : 0.00641925; - fall_capacitance_range (0.00641925, 0.00641925); + capacitance : 0.00623537; + rise_capacitance : 0.0060486; + rise_capacitance_range (0.00570062, 0.00674763); + fall_capacitance : 0.00642213; + fall_capacitance_range (0.00539536, 0.00719369); } pin (B) { direction : "input"; max_transition : 2.5074; - capacitance : 0.00616692; - rise_capacitance : 0.00608383; - rise_capacitance_range (0.00608383, 0.00608383); - fall_capacitance : 0.00625; - fall_capacitance_range (0.00625, 0.00625); + capacitance : 0.00616685; + rise_capacitance : 0.00608385; + rise_capacitance_range (0.00542656, 0.00708036); + fall_capacitance : 0.00624985; + fall_capacitance_range (0.00525144, 0.00692071); } pin (C) { direction : "input"; max_transition : 2.5074; - capacitance : 0.00610376; - rise_capacitance : 0.00610751; - rise_capacitance_range (0.00610751, 0.00610751); - fall_capacitance : 0.00610001; - fall_capacitance_range (0.00610001, 0.00610001); + capacitance : 0.00610377; + rise_capacitance : 0.0061075; + rise_capacitance_range (0.00519512, 0.00745877); + fall_capacitance : 0.00610003; + fall_capacitance_range (0.0051741, 0.00665523); } pin (D) { direction : "input"; max_transition : 2.5074; capacitance : 0.0058909; - rise_capacitance : 0.00614982; - rise_capacitance_range (0.00614982, 0.00614982); - fall_capacitance : 0.00563199; - fall_capacitance_range (0.00563199, 0.00563199); + rise_capacitance : 0.00614981; + rise_capacitance_range (0.00486596, 0.00812183); + fall_capacitance : 0.005632; + fall_capacitance_range (0.00518877, 0.00596807); } } cell (sg13g2_o21ai_1) { area : 9.072; cell_footprint : "o21ai"; - cell_leakage_power : 372.578; + cell_leakage_power : 372.588; leakage_power () { - value : 230.592; + value : 230.602; when : "!A1&!A2&!B1&Y"; } leakage_power () { - value : 342.63; + value : 342.64; when : "A1&!A2&!B1&Y"; } leakage_power () { - value : 342.636; + value : 342.646; when : "!A1&A2&!B1&Y"; } leakage_power () { - value : 449.995; + value : 450.005; when : "A1&A2&!B1&Y"; } leakage_power () { - value : 170.7; + value : 170.71; when : "!A1&!A2&B1&Y"; } leakage_power () { - value : 398.692; + value : 398.702; when : "A1&!A2&B1&!Y"; } leakage_power () { - value : 473.344; + value : 473.354; when : "!A1&A2&B1&!Y"; } leakage_power () { - value : 572.037; + value : 572.047; when : "A1&A2&B1&!Y"; } pin (Y) { @@ -24532,52 +24606,52 @@ library (sg13g2_stdcell_fast_1p32V_m40C) { index_1 ("0.0186, 0.0966, 0.174, 0.3294, 0.6408, 1.263, 2.5074"); index_2 ("0.001, 0.0234, 0.039, 0.0648, 0.108, 0.18, 0.3"); values ( \ - "0.0463068, 0.147498, 0.216626, 0.330645, 0.521731, 0.83941, 1.36914", \ - "0.0667432, 0.174837, 0.244282, 0.358633, 0.549852, 0.867926, 1.39717", \ - "0.0786792, 0.197871, 0.269316, 0.384119, 0.575202, 0.893254, 1.42364", \ - "0.0957188, 0.236148, 0.314107, 0.434296, 0.627614, 0.946087, 1.47615", \ - "0.122002, 0.295476, 0.385624, 0.518837, 0.724388, 1.04928, 1.58055", \ - "0.164444, 0.3859, 0.496318, 0.653159, 0.887079, 1.23881, 1.78754", \ - "0.2278, 0.519095, 0.661646, 0.858733, 1.13751, 1.54406, 2.15008" \ + "0.0463081, 0.14749, 0.216723, 0.330652, 0.521618, 0.839427, 1.36919", \ + "0.0667436, 0.174828, 0.244291, 0.358524, 0.549855, 0.867581, 1.39722", \ + "0.0786796, 0.197872, 0.269306, 0.384123, 0.5752, 0.893239, 1.42366", \ + "0.0957193, 0.236149, 0.314112, 0.434299, 0.627614, 0.946101, 1.47606", \ + "0.122003, 0.295478, 0.385626, 0.51884, 0.724393, 1.04928, 1.58057", \ + "0.164445, 0.385902, 0.49632, 0.653162, 0.887083, 1.23882, 1.78756", \ + "0.227802, 0.519097, 0.66165, 0.858737, 1.13751, 1.54407, 2.15009" \ ); } rise_transition (TIMING_DELAY_7x7ds1) { index_1 ("0.0186, 0.0966, 0.174, 0.3294, 0.6408, 1.263, 2.5074"); index_2 ("0.001, 0.0234, 0.039, 0.0648, 0.108, 0.18, 0.3"); values ( \ - "0.0322231, 0.17219, 0.269361, 0.429633, 0.69836, 1.14626, 1.8912", \ - "0.0413386, 0.174716, 0.270217, 0.431453, 0.698965, 1.14627, 1.89174", \ - "0.0510251, 0.183641, 0.275927, 0.432509, 0.698966, 1.14628, 1.89175", \ - "0.0693797, 0.206895, 0.296553, 0.447255, 0.706377, 1.14771, 1.89259", \ - "0.0994541, 0.251574, 0.342948, 0.490557, 0.740447, 1.1673, 1.89839", \ - "0.145573, 0.331021, 0.428698, 0.581825, 0.830722, 1.24533, 1.94778", \ - "0.219324, 0.458855, 0.57718, 0.74594, 1.00804, 1.42852, 2.11721" \ + "0.0322224, 0.172191, 0.269361, 0.429634, 0.698313, 1.14627, 1.89195", \ + "0.0413389, 0.174813, 0.270052, 0.430748, 0.698971, 1.14628, 1.89196", \ + "0.0510255, 0.183643, 0.275937, 0.432489, 0.698972, 1.14629, 1.89197", \ + "0.0693798, 0.206896, 0.296549, 0.447247, 0.706375, 1.14834, 1.89334", \ + "0.0994544, 0.251575, 0.34295, 0.49056, 0.740453, 1.16731, 1.89841", \ + "0.145574, 0.331022, 0.4287, 0.581828, 0.830728, 1.24533, 1.94781", \ + "0.219216, 0.458856, 0.577182, 0.745943, 1.00805, 1.42852, 2.11722" \ ); } cell_fall (TIMING_DELAY_7x7ds1) { index_1 ("0.0186, 0.0966, 0.174, 0.3294, 0.6408, 1.263, 2.5074"); index_2 ("0.001, 0.0234, 0.039, 0.0648, 0.108, 0.18, 0.3"); values ( \ - "0.0338995, 0.0991163, 0.143332, 0.21625, 0.33823, 0.541359, 0.879938", \ - "0.0521613, 0.127554, 0.172991, 0.246282, 0.368363, 0.571551, 0.910122", \ - "0.0629488, 0.150466, 0.199239, 0.275126, 0.398322, 0.601681, 0.940415", \ - "0.0744357, 0.184589, 0.240542, 0.324219, 0.453491, 0.660083, 0.999185", \ - "0.0876259, 0.230797, 0.300943, 0.399142, 0.544852, 0.76665, 1.11325", \ - "0.101957, 0.290305, 0.38129, 0.507107, 0.68362, 0.938194, 1.31666", \ - "0.111458, 0.366126, 0.484773, 0.647462, 0.876272, 1.19327, 1.63579" \ + "0.0339022, 0.0991018, 0.143329, 0.216252, 0.338304, 0.54136, 0.879938", \ + "0.0521613, 0.127545, 0.172991, 0.246284, 0.368353, 0.57155, 0.910136", \ + "0.0629488, 0.150466, 0.199239, 0.275126, 0.398322, 0.60168, 0.940411", \ + "0.0744356, 0.184588, 0.240542, 0.324219, 0.453491, 0.660082, 0.99915", \ + "0.0876258, 0.230797, 0.300943, 0.39913, 0.544851, 0.76665, 1.11325", \ + "0.101956, 0.290304, 0.38129, 0.507106, 0.683619, 0.938194, 1.31666", \ + "0.111457, 0.366126, 0.484755, 0.647461, 0.876272, 1.19319, 1.63579" \ ); } fall_transition (TIMING_DELAY_7x7ds1) { index_1 ("0.0186, 0.0966, 0.174, 0.3294, 0.6408, 1.263, 2.5074"); index_2 ("0.001, 0.0234, 0.039, 0.0648, 0.108, 0.18, 0.3"); values ( \ - "0.0199075, 0.106747, 0.167043, 0.266988, 0.434244, 0.713018, 1.17763", \ - "0.0290773, 0.112332, 0.170268, 0.268062, 0.434613, 0.713019, 1.17764", \ - "0.0387239, 0.123522, 0.179908, 0.274899, 0.437577, 0.713791, 1.17765", \ - "0.0572106, 0.147868, 0.204216, 0.296674, 0.453792, 0.722344, 1.18005", \ - "0.0889903, 0.192314, 0.252074, 0.345706, 0.50051, 0.759575, 1.20147", \ - "0.138941, 0.267429, 0.336458, 0.438677, 0.599335, 0.856128, 1.28532", \ - "0.218704, 0.39327, 0.476517, 0.597887, 0.779453, 1.05172, 1.48105" \ + "0.0199073, 0.106753, 0.167043, 0.266988, 0.434234, 0.713017, 1.17763", \ + "0.0290772, 0.112333, 0.170268, 0.268145, 0.434584, 0.713018, 1.17764", \ + "0.0387239, 0.123521, 0.179938, 0.274894, 0.437576, 0.713791, 1.17765", \ + "0.0572107, 0.147868, 0.204216, 0.296674, 0.45379, 0.722341, 1.17936", \ + "0.0889903, 0.192314, 0.252074, 0.345495, 0.500509, 0.759575, 1.20147", \ + "0.138941, 0.267431, 0.336458, 0.438677, 0.599334, 0.856126, 1.28532", \ + "0.218704, 0.39327, 0.476364, 0.597887, 0.779452, 1.05163, 1.48105" \ ); } } @@ -24589,52 +24663,52 @@ library (sg13g2_stdcell_fast_1p32V_m40C) { index_1 ("0.0186, 0.0966, 0.174, 0.3294, 0.6408, 1.263, 2.5074"); index_2 ("0.001, 0.0234, 0.039, 0.0648, 0.108, 0.18, 0.3"); values ( \ - "0.0405469, 0.142543, 0.211759, 0.326005, 0.516768, 0.835071, 1.36437", \ - "0.0643528, 0.177069, 0.246496, 0.360914, 0.552007, 0.870165, 1.39944", \ - "0.079542, 0.2085, 0.280847, 0.395369, 0.586078, 0.904098, 1.4343", \ - "0.10189, 0.259324, 0.341563, 0.464418, 0.658153, 0.975907, 1.50589", \ - "0.135783, 0.333243, 0.433638, 0.576973, 0.789409, 1.11644, 1.64704", \ - "0.189665, 0.443243, 0.569088, 0.74671, 1.00154, 1.37099, 1.92877", \ - "0.274724, 0.605901, 0.768177, 0.993324, 1.31064, 1.76497, 2.41024" \ + "0.0405461, 0.142517, 0.211769, 0.326007, 0.516773, 0.835078, 1.36437", \ + "0.0643574, 0.177072, 0.246507, 0.360749, 0.551732, 0.870179, 1.39944", \ + "0.0795423, 0.208501, 0.280848, 0.395383, 0.586089, 0.904165, 1.43431", \ + "0.10189, 0.259325, 0.341603, 0.464424, 0.658156, 0.975902, 1.50601", \ + "0.135783, 0.333244, 0.43364, 0.576975, 0.789403, 1.11645, 1.64681", \ + "0.189666, 0.443245, 0.56909, 0.746713, 1.00155, 1.37099, 1.92877", \ + "0.274725, 0.605903, 0.76818, 0.993327, 1.31065, 1.76498, 2.41025" \ ); } rise_transition (TIMING_DELAY_7x7ds1) { index_1 ("0.0186, 0.0966, 0.174, 0.3294, 0.6408, 1.263, 2.5074"); index_2 ("0.001, 0.0234, 0.039, 0.0648, 0.108, 0.18, 0.3"); values ( \ - "0.0324324, 0.172175, 0.269335, 0.429734, 0.698612, 1.14598, 1.8912", \ - "0.0467202, 0.176556, 0.270646, 0.431071, 0.698859, 1.14599, 1.89229", \ - "0.0580353, 0.190839, 0.280013, 0.43369, 0.69886, 1.14619, 1.8923", \ - "0.0761043, 0.224636, 0.311895, 0.457406, 0.711185, 1.1484, 1.89401", \ - "0.104379, 0.282751, 0.376409, 0.522546, 0.764181, 1.17973, 1.90262", \ - "0.151306, 0.37351, 0.484647, 0.646427, 0.897061, 1.29806, 1.98085", \ - "0.227844, 0.520708, 0.655276, 0.847367, 1.1345, 1.5608, 2.2355" \ + "0.0324328, 0.172157, 0.26934, 0.429738, 0.698617, 1.14599, 1.89121", \ + "0.04672, 0.176551, 0.270686, 0.430552, 0.698618, 1.146, 1.89231", \ + "0.0580354, 0.190842, 0.280015, 0.433726, 0.698619, 1.14621, 1.89232", \ + "0.0761045, 0.224637, 0.312066, 0.457429, 0.71119, 1.14842, 1.89411", \ + "0.104379, 0.282752, 0.376411, 0.522549, 0.763865, 1.17974, 1.90143", \ + "0.151306, 0.373511, 0.484649, 0.646431, 0.896846, 1.29807, 1.98087", \ + "0.227844, 0.520708, 0.655278, 0.847369, 1.1345, 1.56079, 2.23551" \ ); } cell_fall (TIMING_DELAY_7x7ds1) { index_1 ("0.0186, 0.0966, 0.174, 0.3294, 0.6408, 1.263, 2.5074"); index_2 ("0.001, 0.0234, 0.039, 0.0648, 0.108, 0.18, 0.3"); values ( \ - "0.0285041, 0.0937227, 0.137695, 0.20999, 0.331255, 0.533189, 0.869455", \ - "0.0431993, 0.12167, 0.167161, 0.240139, 0.361466, 0.563491, 0.900208", \ - "0.0507942, 0.143705, 0.192943, 0.268843, 0.391451, 0.593711, 0.930485", \ - "0.0570019, 0.176, 0.233113, 0.317261, 0.446544, 0.652186, 0.989521", \ - "0.0605003, 0.218749, 0.290728, 0.39083, 0.536998, 0.758303, 1.10386", \ - "0.0605013, 0.272107, 0.366468, 0.495557, 0.673961, 0.929051, 1.3071", \ - "0.0605023, 0.331919, 0.458836, 0.627183, 0.861465, 1.17958, 1.62522" \ + "0.0284966, 0.0937217, 0.137694, 0.209983, 0.331164, 0.533193, 0.869461", \ + "0.0431993, 0.12167, 0.167161, 0.240139, 0.361508, 0.563491, 0.900207", \ + "0.0507942, 0.143705, 0.192943, 0.268843, 0.391448, 0.593711, 0.930468", \ + "0.0570018, 0.176, 0.233112, 0.317261, 0.446546, 0.652187, 0.989516", \ + "0.0605002, 0.218749, 0.290728, 0.39083, 0.536998, 0.758302, 1.10386", \ + "0.0605012, 0.272106, 0.366468, 0.495555, 0.67396, 0.929051, 1.3071", \ + "0.0605022, 0.331918, 0.458836, 0.627182, 0.861464, 1.17958, 1.62523" \ ); } fall_transition (TIMING_DELAY_7x7ds1) { index_1 ("0.0186, 0.0966, 0.174, 0.3294, 0.6408, 1.263, 2.5074"); index_2 ("0.001, 0.0234, 0.039, 0.0648, 0.108, 0.18, 0.3"); values ( \ - "0.0137637, 0.0993838, 0.159401, 0.258581, 0.424619, 0.701475, 1.16302", \ - "0.0231345, 0.105437, 0.162762, 0.259774, 0.42462, 0.701476, 1.16303", \ - "0.0329005, 0.116877, 0.172665, 0.266707, 0.428078, 0.70365, 1.16304", \ - "0.0513372, 0.141423, 0.197173, 0.288799, 0.444471, 0.710793, 1.16502", \ - "0.0838051, 0.185957, 0.244995, 0.338257, 0.491433, 0.748518, 1.18729", \ - "0.13369, 0.26184, 0.330673, 0.433189, 0.59134, 0.845955, 1.27268", \ - "0.213589, 0.39314, 0.472834, 0.594274, 0.773628, 1.04281, 1.47093" \ + "0.0137651, 0.0994816, 0.1594, 0.258579, 0.424656, 0.701478, 1.16302", \ + "0.0231345, 0.105436, 0.162761, 0.259775, 0.424773, 0.701479, 1.16303", \ + "0.0329004, 0.116877, 0.172665, 0.266693, 0.427906, 0.703648, 1.16304", \ + "0.0513371, 0.141423, 0.197173, 0.288791, 0.444641, 0.710971, 1.16511", \ + "0.0838051, 0.185957, 0.244995, 0.338257, 0.491432, 0.748517, 1.18729", \ + "0.13369, 0.26184, 0.330673, 0.43319, 0.59134, 0.845955, 1.27267", \ + "0.21359, 0.39314, 0.472833, 0.594271, 0.773628, 1.04279, 1.47201" \ ); } } @@ -24648,52 +24722,52 @@ library (sg13g2_stdcell_fast_1p32V_m40C) { index_1 ("0.0186, 0.0966, 0.174, 0.3294, 0.6408, 1.263, 2.5074"); index_2 ("0.001, 0.0234, 0.039, 0.0648, 0.108, 0.18, 0.3"); values ( \ - "0.0195218, 0.0710256, 0.105106, 0.161322, 0.255289, 0.412042, 0.672784", \ - "0.0354434, 0.109811, 0.146873, 0.204004, 0.298112, 0.4548, 0.716574", \ - "0.0444, 0.138004, 0.181204, 0.243659, 0.339947, 0.496785, 0.75793", \ - "0.0557507, 0.179545, 0.234484, 0.309835, 0.418341, 0.581601, 0.843927", \ - "0.0704136, 0.236533, 0.309532, 0.407554, 0.541181, 0.729265, 1.00824", \ - "0.0897421, 0.314347, 0.414423, 0.546057, 0.722424, 0.961764, 1.29267", \ - "0.113852, 0.416127, 0.5524, 0.733745, 0.97396, 1.29137, 1.72277" \ + "0.0195231, 0.0710275, 0.105104, 0.161304, 0.255451, 0.41186, 0.672774", \ + "0.0354401, 0.109835, 0.146871, 0.204001, 0.298109, 0.454773, 0.716548", \ + "0.0443997, 0.138003, 0.181203, 0.243657, 0.339967, 0.496832, 0.757937", \ + "0.0557425, 0.179544, 0.234482, 0.309833, 0.418337, 0.581582, 0.843905", \ + "0.0704131, 0.236532, 0.30953, 0.407551, 0.541179, 0.729256, 1.00823", \ + "0.0897413, 0.314345, 0.41442, 0.546054, 0.722419, 0.961758, 1.29266", \ + "0.113851, 0.416125, 0.552396, 0.733741, 0.973955, 1.29136, 1.72276" \ ); } rise_transition (TIMING_DELAY_7x7ds1) { index_1 ("0.0186, 0.0966, 0.174, 0.3294, 0.6408, 1.263, 2.5074"); index_2 ("0.001, 0.0234, 0.039, 0.0648, 0.108, 0.18, 0.3"); values ( \ - "0.0123855, 0.080915, 0.130188, 0.211538, 0.347843, 0.574962, 0.953466", \ - "0.027019, 0.0936342, 0.137811, 0.214615, 0.350179, 0.574966, 0.954322", \ - "0.0372493, 0.11256, 0.155663, 0.228021, 0.355155, 0.577124, 0.954323", \ - "0.0532526, 0.148038, 0.194049, 0.266102, 0.385998, 0.594804, 0.95997", \ - "0.0785272, 0.204228, 0.259645, 0.338829, 0.461751, 0.660499, 1.00303", \ - "0.12107, 0.294251, 0.366409, 0.462478, 0.603719, 0.813014, 1.14532", \ - "0.193717, 0.43291, 0.533149, 0.663478, 0.83528, 1.08348, 1.44447" \ + "0.0123862, 0.0809133, 0.130207, 0.211522, 0.348034, 0.5749, 0.953453", \ + "0.0270219, 0.0936809, 0.13781, 0.214623, 0.350174, 0.574901, 0.954304", \ + "0.0372492, 0.112559, 0.155661, 0.228019, 0.355173, 0.577183, 0.954305", \ + "0.0532644, 0.148037, 0.194047, 0.266134, 0.385992, 0.59478, 0.959611", \ + "0.0785269, 0.204227, 0.259643, 0.338826, 0.461741, 0.660519, 1.00305", \ + "0.12107, 0.294251, 0.366408, 0.462474, 0.603716, 0.813007, 1.1453", \ + "0.193716, 0.432909, 0.533144, 0.663475, 0.835275, 1.08347, 1.44446" \ ); } cell_fall (TIMING_DELAY_7x7ds1) { index_1 ("0.0186, 0.0966, 0.174, 0.3294, 0.6408, 1.263, 2.5074"); index_2 ("0.001, 0.0234, 0.039, 0.0648, 0.108, 0.18, 0.3"); values ( \ - "0.0226025, 0.0882785, 0.132297, 0.204663, 0.325765, 0.52779, 0.864395", \ - "0.0370252, 0.123197, 0.169344, 0.242304, 0.363524, 0.565456, 0.901971", \ - "0.0455124, 0.150353, 0.202218, 0.279611, 0.402474, 0.604524, 0.940915", \ - "0.0557446, 0.188767, 0.251963, 0.341487, 0.474469, 0.681047, 1.01797", \ - "0.0683815, 0.23991, 0.320453, 0.431351, 0.588658, 0.819117, 1.16695", \ - "0.0832627, 0.306813, 0.411612, 0.555903, 0.753588, 1.03127, 1.43106", \ - "0.0985737, 0.396826, 0.530137, 0.716085, 0.97725, 1.33065, 1.82278" \ + "0.0226026, 0.0882846, 0.132175, 0.204653, 0.325765, 0.527789, 0.864391", \ + "0.0370252, 0.123197, 0.169344, 0.242312, 0.363523, 0.565455, 0.901986", \ + "0.0455124, 0.150353, 0.202218, 0.279611, 0.402481, 0.604524, 0.940914", \ + "0.0557446, 0.188767, 0.251963, 0.341487, 0.474469, 0.681052, 1.01776", \ + "0.0683821, 0.23991, 0.320453, 0.431351, 0.588657, 0.819117, 1.16695", \ + "0.083263, 0.306813, 0.411612, 0.555903, 0.753587, 1.03124, 1.43106", \ + "0.0985743, 0.396827, 0.530137, 0.716085, 0.97725, 1.33065, 1.82278" \ ); } fall_transition (TIMING_DELAY_7x7ds1) { index_1 ("0.0186, 0.0966, 0.174, 0.3294, 0.6408, 1.263, 2.5074"); index_2 ("0.001, 0.0234, 0.039, 0.0648, 0.108, 0.18, 0.3"); values ( \ - "0.014837, 0.099324, 0.159417, 0.258539, 0.424661, 0.701471, 1.16288", \ - "0.0280752, 0.110136, 0.165444, 0.260578, 0.426447, 0.701472, 1.16298", \ - "0.0384612, 0.127631, 0.181535, 0.272274, 0.43036, 0.703223, 1.16299", \ - "0.054828, 0.160853, 0.217218, 0.30661, 0.457035, 0.716924, 1.16655", \ - "0.0817251, 0.213832, 0.279495, 0.375623, 0.528033, 0.776368, 1.20175", \ - "0.126278, 0.29545, 0.378226, 0.492577, 0.661662, 0.918615, 1.33173", \ - "0.203686, 0.42507, 0.530526, 0.677252, 0.880803, 1.17537, 1.61309" \ + "0.014837, 0.0993294, 0.159324, 0.258527, 0.42466, 0.70147, 1.16288", \ + "0.0280752, 0.11018, 0.165444, 0.260642, 0.426446, 0.701471, 1.16297", \ + "0.0384612, 0.127631, 0.181535, 0.272273, 0.430495, 0.703222, 1.16298", \ + "0.054828, 0.160853, 0.217218, 0.30661, 0.457003, 0.716931, 1.1662", \ + "0.0817241, 0.213832, 0.279495, 0.375622, 0.528032, 0.776366, 1.20174", \ + "0.126277, 0.29545, 0.378225, 0.492576, 0.661661, 0.918533, 1.33172", \ + "0.203685, 0.425069, 0.530526, 0.677251, 0.880802, 1.17537, 1.61309" \ ); } } @@ -24705,52 +24779,52 @@ library (sg13g2_stdcell_fast_1p32V_m40C) { index_1 ("0.0186, 0.0966, 0.174, 0.3294, 0.6408, 1.263, 2.5074"); index_2 ("0.001, 0.0234, 0.039, 0.0648, 0.108, 0.18, 0.3"); values ( \ - "0.0195218, 0.0710256, 0.105106, 0.161322, 0.255289, 0.412042, 0.672784", \ - "0.0354434, 0.109811, 0.146873, 0.204004, 0.298112, 0.4548, 0.716574", \ - "0.0444, 0.138004, 0.181204, 0.243659, 0.339947, 0.496785, 0.75793", \ - "0.0557507, 0.179545, 0.234484, 0.309835, 0.418341, 0.581601, 0.843927", \ - "0.0704136, 0.236533, 0.309532, 0.407554, 0.541181, 0.729265, 1.00824", \ - "0.0897421, 0.314347, 0.414423, 0.546057, 0.722424, 0.961764, 1.29267", \ - "0.113852, 0.416127, 0.5524, 0.733745, 0.97396, 1.29137, 1.72277" \ + "0.0195231, 0.0710275, 0.105104, 0.161304, 0.255451, 0.41186, 0.672774", \ + "0.0354401, 0.109835, 0.146871, 0.204001, 0.298109, 0.454773, 0.716548", \ + "0.0443997, 0.138003, 0.181203, 0.243657, 0.339967, 0.496832, 0.757937", \ + "0.0557425, 0.179544, 0.234482, 0.309833, 0.418337, 0.581582, 0.843905", \ + "0.0704131, 0.236532, 0.30953, 0.407551, 0.541179, 0.729256, 1.00823", \ + "0.0897413, 0.314345, 0.41442, 0.546054, 0.722419, 0.961758, 1.29266", \ + "0.113851, 0.416125, 0.552396, 0.733741, 0.973955, 1.29136, 1.72276" \ ); } rise_transition (TIMING_DELAY_7x7ds1) { index_1 ("0.0186, 0.0966, 0.174, 0.3294, 0.6408, 1.263, 2.5074"); index_2 ("0.001, 0.0234, 0.039, 0.0648, 0.108, 0.18, 0.3"); values ( \ - "0.0123855, 0.080915, 0.130188, 0.211538, 0.347843, 0.574962, 0.953466", \ - "0.027019, 0.0936342, 0.137811, 0.214615, 0.350179, 0.574966, 0.954322", \ - "0.0372493, 0.11256, 0.155663, 0.228021, 0.355155, 0.577124, 0.954323", \ - "0.0532526, 0.148038, 0.194049, 0.266102, 0.385998, 0.594804, 0.95997", \ - "0.0785272, 0.204228, 0.259645, 0.338829, 0.461751, 0.660499, 1.00303", \ - "0.12107, 0.294251, 0.366409, 0.462478, 0.603719, 0.813014, 1.14532", \ - "0.193717, 0.43291, 0.533149, 0.663478, 0.83528, 1.08348, 1.44447" \ + "0.0123862, 0.0809133, 0.130207, 0.211522, 0.348034, 0.5749, 0.953453", \ + "0.0270219, 0.0936809, 0.13781, 0.214623, 0.350174, 0.574901, 0.954304", \ + "0.0372492, 0.112559, 0.155661, 0.228019, 0.355173, 0.577183, 0.954305", \ + "0.0532644, 0.148037, 0.194047, 0.266134, 0.385992, 0.59478, 0.959611", \ + "0.0785269, 0.204227, 0.259643, 0.338826, 0.461741, 0.660519, 1.00305", \ + "0.12107, 0.294251, 0.366408, 0.462474, 0.603716, 0.813007, 1.1453", \ + "0.193716, 0.432909, 0.533144, 0.663475, 0.835275, 1.08347, 1.44446" \ ); } cell_fall (TIMING_DELAY_7x7ds1) { index_1 ("0.0186, 0.0966, 0.174, 0.3294, 0.6408, 1.263, 2.5074"); index_2 ("0.001, 0.0234, 0.039, 0.0648, 0.108, 0.18, 0.3"); values ( \ - "0.0226025, 0.0882785, 0.132297, 0.204663, 0.325765, 0.52779, 0.864395", \ - "0.0370252, 0.123197, 0.169344, 0.242304, 0.363524, 0.565456, 0.901971", \ - "0.0455124, 0.150353, 0.202218, 0.279611, 0.402474, 0.604524, 0.940915", \ - "0.0557446, 0.188767, 0.251963, 0.341487, 0.474469, 0.681047, 1.01797", \ - "0.0683815, 0.23991, 0.320453, 0.431351, 0.588658, 0.819117, 1.16695", \ - "0.0832627, 0.306813, 0.411612, 0.555903, 0.753588, 1.03127, 1.43106", \ - "0.0985737, 0.396826, 0.530137, 0.716085, 0.97725, 1.33065, 1.82278" \ + "0.0226026, 0.0882846, 0.132175, 0.204653, 0.325765, 0.527789, 0.864391", \ + "0.0370252, 0.123197, 0.169344, 0.242312, 0.363523, 0.565455, 0.901986", \ + "0.0455124, 0.150353, 0.202218, 0.279611, 0.402481, 0.604524, 0.940914", \ + "0.0557446, 0.188767, 0.251963, 0.341487, 0.474469, 0.681052, 1.01776", \ + "0.0683821, 0.23991, 0.320453, 0.431351, 0.588657, 0.819117, 1.16695", \ + "0.083263, 0.306813, 0.411612, 0.555903, 0.753587, 1.03124, 1.43106", \ + "0.0985743, 0.396827, 0.530137, 0.716085, 0.97725, 1.33065, 1.82278" \ ); } fall_transition (TIMING_DELAY_7x7ds1) { index_1 ("0.0186, 0.0966, 0.174, 0.3294, 0.6408, 1.263, 2.5074"); index_2 ("0.001, 0.0234, 0.039, 0.0648, 0.108, 0.18, 0.3"); values ( \ - "0.014837, 0.099324, 0.159417, 0.258539, 0.424661, 0.701471, 1.16288", \ - "0.0280752, 0.110136, 0.165444, 0.260578, 0.426447, 0.701472, 1.16298", \ - "0.0384612, 0.127631, 0.181535, 0.272274, 0.43036, 0.703223, 1.16299", \ - "0.054828, 0.160853, 0.217218, 0.30661, 0.457035, 0.716924, 1.16655", \ - "0.0817251, 0.213832, 0.279495, 0.375623, 0.528033, 0.776368, 1.20175", \ - "0.126278, 0.29545, 0.378226, 0.492577, 0.661662, 0.918615, 1.33173", \ - "0.203686, 0.42507, 0.530526, 0.677252, 0.880803, 1.17537, 1.61309" \ + "0.014837, 0.0993294, 0.159324, 0.258527, 0.42466, 0.70147, 1.16288", \ + "0.0280752, 0.11018, 0.165444, 0.260642, 0.426446, 0.701471, 1.16297", \ + "0.0384612, 0.127631, 0.181535, 0.272273, 0.430495, 0.703222, 1.16298", \ + "0.054828, 0.160853, 0.217218, 0.30661, 0.457003, 0.716931, 1.1662", \ + "0.0817241, 0.213832, 0.279495, 0.375622, 0.528032, 0.776366, 1.20174", \ + "0.126277, 0.29545, 0.378225, 0.492576, 0.661661, 0.918533, 1.33172", \ + "0.203685, 0.425069, 0.530526, 0.677251, 0.880802, 1.17537, 1.61309" \ ); } } @@ -24760,26 +24834,26 @@ library (sg13g2_stdcell_fast_1p32V_m40C) { index_1 ("0.0186, 0.0966, 0.174, 0.3294, 0.6408, 1.263, 2.5074"); index_2 ("0.001, 0.0234, 0.039, 0.0648, 0.108, 0.18, 0.3"); values ( \ - "0.00632467, 0.00639063, 0.00634907, 0.00626807, 0.00614038, 0.00590485, 0.00549404", \ - "0.00606658, 0.00620139, 0.00621967, 0.00628123, 0.00611472, 0.00581298, 0.00549947", \ - "0.00619966, 0.00619768, 0.00620313, 0.00614243, 0.00604504, 0.00580909, 0.00544204", \ - "0.00699319, 0.00655478, 0.00638031, 0.00637383, 0.00624292, 0.0060342, 0.00560943", \ - "0.00941705, 0.00796802, 0.00763071, 0.00713126, 0.006876, 0.0062752, 0.00659537", \ - "0.0151627, 0.0122953, 0.0113003, 0.0102722, 0.00915287, 0.00808185, 0.00773062", \ - "0.027216, 0.0228106, 0.0209445, 0.0187268, 0.0163261, 0.0140458, 0.0115103" \ + "0.00632692, 0.00638954, 0.00635385, 0.00626838, 0.00615653, 0.0059068, 0.00557317", \ + "0.00606307, 0.00620431, 0.00622102, 0.00623219, 0.00611471, 0.00584564, 0.00540748", \ + "0.00619975, 0.00619733, 0.0063106, 0.00614713, 0.00604442, 0.00579807, 0.00544207", \ + "0.00699102, 0.00654709, 0.00638118, 0.00641195, 0.00624304, 0.00606942, 0.00565824", \ + "0.00941576, 0.00797009, 0.00763032, 0.00713163, 0.0068661, 0.00627034, 0.0065947", \ + "0.015163, 0.012295, 0.011302, 0.0102654, 0.00922889, 0.0080859, 0.00774979", \ + "0.027243, 0.0228108, 0.0209447, 0.0187266, 0.0163204, 0.014076, 0.0115004" \ ); } fall_power (POWER_7x7ds1) { index_1 ("0.0186, 0.0966, 0.174, 0.3294, 0.6408, 1.263, 2.5074"); index_2 ("0.001, 0.0234, 0.039, 0.0648, 0.108, 0.18, 0.3"); values ( \ - "0.00582331, 0.00589852, 0.00584348, 0.00576302, 0.00562334, 0.00538649, 0.00500227", \ - "0.00550715, 0.0057081, 0.00582064, 0.00564572, 0.00556681, 0.00532597, 0.00494202", \ - "0.0056245, 0.00572455, 0.00568296, 0.00581303, 0.00552913, 0.00531969, 0.0048946", \ - "0.00638476, 0.00604524, 0.00598686, 0.00583038, 0.00582332, 0.00534657, 0.00520807", \ - "0.00873473, 0.00735444, 0.00700715, 0.00670142, 0.00627394, 0.00600885, 0.00554869", \ - "0.0143442, 0.0113115, 0.0103424, 0.00931772, 0.00860944, 0.00770156, 0.00648152", \ - "0.0261992, 0.0213526, 0.0194202, 0.017116, 0.0150075, 0.0128481, 0.010906" \ + "0.00582352, 0.00589907, 0.00584376, 0.00576577, 0.00564526, 0.00538582, 0.0050026", \ + "0.00550667, 0.00569781, 0.00582058, 0.00564945, 0.00557744, 0.00532598, 0.00494281", \ + "0.00562548, 0.00572846, 0.00567555, 0.00581239, 0.00552914, 0.00532003, 0.0048895", \ + "0.00638477, 0.00604513, 0.00598685, 0.00583019, 0.00582345, 0.005527, 0.00514227", \ + "0.00873484, 0.00735442, 0.00700718, 0.00670444, 0.00627414, 0.0059982, 0.00553239", \ + "0.0143447, 0.0113104, 0.0103424, 0.00931771, 0.00860988, 0.00773159, 0.00648252", \ + "0.0261993, 0.0213521, 0.019413, 0.0171161, 0.0150083, 0.0129151, 0.0109062" \ ); } } @@ -24789,26 +24863,26 @@ library (sg13g2_stdcell_fast_1p32V_m40C) { index_1 ("0.0186, 0.0966, 0.174, 0.3294, 0.6408, 1.263, 2.5074"); index_2 ("0.001, 0.0234, 0.039, 0.0648, 0.108, 0.18, 0.3"); values ( \ - "0.00318471, 0.00342383, 0.00340426, 0.00333212, 0.00323691, 0.0029863, 0.00252199", \ - "0.00316618, 0.0032077, 0.0032846, 0.00330875, 0.00316218, 0.00291318, 0.00254969", \ - "0.00364628, 0.00334099, 0.00337465, 0.00324863, 0.00307948, 0.00287104, 0.00249152", \ - "0.00487552, 0.00395941, 0.00370068, 0.00364872, 0.00330733, 0.00298103, 0.00274325", \ - "0.00750195, 0.00574245, 0.00522249, 0.00467556, 0.0042231, 0.00346059, 0.00310808", \ - "0.0132103, 0.0102391, 0.00919747, 0.00800997, 0.00683759, 0.00553, 0.00491873", \ - "0.0251535, 0.020725, 0.0188426, 0.0165879, 0.0142822, 0.0117735, 0.00878364" \ + "0.0031841, 0.00341983, 0.00340397, 0.00333253, 0.00323619, 0.0029878, 0.00252168", \ + "0.00316651, 0.00320879, 0.00330184, 0.00326573, 0.00312677, 0.00291377, 0.0025504", \ + "0.00364607, 0.00333917, 0.00330327, 0.00320767, 0.00309416, 0.00287751, 0.00249143", \ + "0.0048777, 0.00395679, 0.00371104, 0.00363472, 0.00330741, 0.00298059, 0.00275077", \ + "0.0075022, 0.00574402, 0.00523276, 0.00467554, 0.00418462, 0.00346164, 0.00297932", \ + "0.0132103, 0.0102398, 0.00919646, 0.00800348, 0.00685559, 0.00552966, 0.00491824", \ + "0.0251535, 0.0207246, 0.0188427, 0.0165799, 0.0142857, 0.0117218, 0.00878356" \ ); } fall_power (POWER_7x7ds1) { index_1 ("0.0186, 0.0966, 0.174, 0.3294, 0.6408, 1.263, 2.5074"); index_2 ("0.001, 0.0234, 0.039, 0.0648, 0.108, 0.18, 0.3"); values ( \ - "0.00550378, 0.00610647, 0.00612215, 0.00606196, 0.00595116, 0.00570359, 0.00530212", \ - "0.00512643, 0.00579625, 0.00596822, 0.00593957, 0.00585424, 0.00567307, 0.00534222", \ - "0.00532792, 0.00573913, 0.0057949, 0.00600954, 0.00584821, 0.00580587, 0.00529152", \ - "0.00620231, 0.00593665, 0.00598153, 0.00591031, 0.00599981, 0.00569884, 0.00581972", \ - "0.00865312, 0.00713288, 0.00680007, 0.00664445, 0.00632204, 0.00607902, 0.00628368", \ - "0.0142672, 0.010875, 0.00998067, 0.00914396, 0.00843759, 0.00772248, 0.0066754", \ - "0.0260065, 0.0205548, 0.0185348, 0.0163962, 0.0144265, 0.0123996, 0.0108578" \ + "0.00550381, 0.00612748, 0.00612178, 0.00606227, 0.00594811, 0.00573374, 0.00530075", \ + "0.00512651, 0.00579622, 0.00598816, 0.00593978, 0.00588795, 0.00567229, 0.00534222", \ + "0.00532763, 0.00573913, 0.0057949, 0.00601056, 0.00584196, 0.00580594, 0.00528799", \ + "0.00620337, 0.00593666, 0.00597137, 0.00593567, 0.00601721, 0.00569762, 0.00533448", \ + "0.00865278, 0.0071289, 0.00680065, 0.00664539, 0.00631131, 0.00607909, 0.00628341", \ + "0.014267, 0.0108751, 0.00998127, 0.00914332, 0.00843752, 0.00772314, 0.00667473", \ + "0.0260069, 0.0205548, 0.018535, 0.0163806, 0.0144265, 0.0123956, 0.0109578" \ ); } } @@ -24819,26 +24893,26 @@ library (sg13g2_stdcell_fast_1p32V_m40C) { index_1 ("0.0186, 0.0966, 0.174, 0.3294, 0.6408, 1.263, 2.5074"); index_2 ("0.001, 0.0234, 0.039, 0.0648, 0.108, 0.18, 0.3"); values ( \ - "0.00204044, 0.0027556, 0.00278716, 0.00273708, 0.00262948, 0.00243259, 0.00194262", \ - "0.00228311, 0.00244523, 0.00264136, 0.00256195, 0.0027354, 0.0023824, 0.00206825", \ - "0.00292357, 0.00257269, 0.00255042, 0.00268752, 0.00260142, 0.00236719, 0.00196072", \ - "0.00445323, 0.0033048, 0.00310478, 0.00288824, 0.00273779, 0.00253965, 0.00234838", \ - "0.00761299, 0.00540706, 0.00479909, 0.00417997, 0.0035783, 0.00300132, 0.00312167", \ - "0.0143623, 0.0103409, 0.0092145, 0.00783501, 0.00677594, 0.00546118, 0.00395259", \ - "0.0281494, 0.0222114, 0.0201141, 0.0176295, 0.0147572, 0.0121594, 0.00968655" \ + "0.00204102, 0.00275627, 0.00279017, 0.00274565, 0.00266398, 0.00237806, 0.00194399", \ + "0.00228963, 0.00244775, 0.00264135, 0.00256948, 0.00273538, 0.00232846, 0.00209014", \ + "0.0029229, 0.00255639, 0.0025504, 0.00268533, 0.00252355, 0.00237535, 0.001968", \ + "0.00445265, 0.00330481, 0.00310287, 0.00287707, 0.00274514, 0.00243208, 0.00233199", \ + "0.00761297, 0.00540829, 0.00479849, 0.00418249, 0.00360132, 0.00306996, 0.00309703", \ + "0.0143647, 0.0103398, 0.0092147, 0.00784887, 0.00676955, 0.00551204, 0.00401839", \ + "0.0281496, 0.0222117, 0.0201133, 0.0176296, 0.0147572, 0.0121595, 0.00977698" \ ); } fall_power (POWER_7x7ds1) { index_1 ("0.0186, 0.0966, 0.174, 0.3294, 0.6408, 1.263, 2.5074"); index_2 ("0.001, 0.0234, 0.039, 0.0648, 0.108, 0.18, 0.3"); values ( \ - "0.00277333, 0.00336921, 0.00339734, 0.0033383, 0.00323618, 0.00303259, 0.00265053", \ - "0.00290653, 0.00309797, 0.00327901, 0.00318369, 0.00328278, 0.00289208, 0.00255326", \ - "0.00349937, 0.00320722, 0.00316775, 0.00332771, 0.00308172, 0.0029625, 0.00250326", \ - "0.00494513, 0.0038319, 0.00363943, 0.00342719, 0.00339744, 0.00304119, 0.00253789", \ - "0.00808776, 0.00582648, 0.00519778, 0.00472439, 0.00409968, 0.0037458, 0.00303444", \ - "0.0147066, 0.0106179, 0.00940587, 0.00806632, 0.00699046, 0.00588027, 0.0043124", \ - "0.0282852, 0.0220568, 0.0197901, 0.017242, 0.0146874, 0.012009, 0.00980322" \ + "0.00277352, 0.00336899, 0.00338004, 0.0033313, 0.00323601, 0.00303304, 0.00264977", \ + "0.00290775, 0.00309002, 0.00327903, 0.00318089, 0.00328278, 0.00289208, 0.00259512", \ + "0.00350064, 0.00320678, 0.00316739, 0.00332768, 0.00309269, 0.00296266, 0.00250311", \ + "0.00494417, 0.00383198, 0.00363944, 0.00344867, 0.00341501, 0.0030405, 0.00258459", \ + "0.00808757, 0.00582676, 0.0051984, 0.00472219, 0.00409967, 0.0037458, 0.00303418", \ + "0.0147057, 0.010618, 0.00940625, 0.0080662, 0.00699046, 0.00586993, 0.00427492", \ + "0.0282855, 0.0220568, 0.0197897, 0.0172421, 0.0146874, 0.0120107, 0.00980676" \ ); } } @@ -24848,26 +24922,26 @@ library (sg13g2_stdcell_fast_1p32V_m40C) { index_1 ("0.0186, 0.0966, 0.174, 0.3294, 0.6408, 1.263, 2.5074"); index_2 ("0.001, 0.0234, 0.039, 0.0648, 0.108, 0.18, 0.3"); values ( \ - "0.00204044, 0.0027556, 0.00278716, 0.00273708, 0.00262948, 0.00243259, 0.00194262", \ - "0.00228311, 0.00244523, 0.00264136, 0.00256195, 0.0027354, 0.0023824, 0.00206825", \ - "0.00292357, 0.00257269, 0.00255042, 0.00268752, 0.00260142, 0.00236719, 0.00196072", \ - "0.00445323, 0.0033048, 0.00310478, 0.00288824, 0.00273779, 0.00253965, 0.00234838", \ - "0.00761299, 0.00540706, 0.00479909, 0.00417997, 0.0035783, 0.00300132, 0.00312167", \ - "0.0143623, 0.0103409, 0.0092145, 0.00783501, 0.00677594, 0.00546118, 0.00395259", \ - "0.0281494, 0.0222114, 0.0201141, 0.0176295, 0.0147572, 0.0121594, 0.00968655" \ + "0.00204102, 0.00275627, 0.00279017, 0.00274565, 0.00266398, 0.00237806, 0.00194399", \ + "0.00228963, 0.00244775, 0.00264135, 0.00256948, 0.00273538, 0.00232846, 0.00209014", \ + "0.0029229, 0.00255639, 0.0025504, 0.00268533, 0.00252355, 0.00237535, 0.001968", \ + "0.00445265, 0.00330481, 0.00310287, 0.00287707, 0.00274514, 0.00243208, 0.00233199", \ + "0.00761297, 0.00540829, 0.00479849, 0.00418249, 0.00360132, 0.00306996, 0.00309703", \ + "0.0143647, 0.0103398, 0.0092147, 0.00784887, 0.00676955, 0.00551204, 0.00401839", \ + "0.0281496, 0.0222117, 0.0201133, 0.0176296, 0.0147572, 0.0121595, 0.00977698" \ ); } fall_power (POWER_7x7ds1) { index_1 ("0.0186, 0.0966, 0.174, 0.3294, 0.6408, 1.263, 2.5074"); index_2 ("0.001, 0.0234, 0.039, 0.0648, 0.108, 0.18, 0.3"); values ( \ - "0.00277333, 0.00336921, 0.00339734, 0.0033383, 0.00323618, 0.00303259, 0.00265053", \ - "0.00290653, 0.00309797, 0.00327901, 0.00318369, 0.00328278, 0.00289208, 0.00255326", \ - "0.00349937, 0.00320722, 0.00316775, 0.00332771, 0.00308172, 0.0029625, 0.00250326", \ - "0.00494513, 0.0038319, 0.00363943, 0.00342719, 0.00339744, 0.00304119, 0.00253789", \ - "0.00808776, 0.00582648, 0.00519778, 0.00472439, 0.00409968, 0.0037458, 0.00303444", \ - "0.0147066, 0.0106179, 0.00940587, 0.00806632, 0.00699046, 0.00588027, 0.0043124", \ - "0.0282852, 0.0220568, 0.0197901, 0.017242, 0.0146874, 0.012009, 0.00980322" \ + "0.00277352, 0.00336899, 0.00338004, 0.0033313, 0.00323601, 0.00303304, 0.00264977", \ + "0.00290775, 0.00309002, 0.00327903, 0.00318089, 0.00328278, 0.00289208, 0.00259512", \ + "0.00350064, 0.00320678, 0.00316739, 0.00332768, 0.00309269, 0.00296266, 0.00250311", \ + "0.00494417, 0.00383198, 0.00363944, 0.00344867, 0.00341501, 0.0030405, 0.00258459", \ + "0.00808757, 0.00582676, 0.0051984, 0.00472219, 0.00409967, 0.0037458, 0.00303418", \ + "0.0147057, 0.010618, 0.00940625, 0.0080662, 0.00699046, 0.00586993, 0.00427492", \ + "0.0282855, 0.0220568, 0.0197897, 0.0172421, 0.0146874, 0.0120107, 0.00980676" \ ); } } @@ -24875,29 +24949,29 @@ library (sg13g2_stdcell_fast_1p32V_m40C) { pin (A1) { direction : "input"; max_transition : 2.5074; - capacitance : 0.00365468; - rise_capacitance : 0.00373877; - rise_capacitance_range (0.00373877, 0.00373877); - fall_capacitance : 0.00357058; - fall_capacitance_range (0.00357058, 0.00357058); + capacitance : 0.00365455; + rise_capacitance : 0.00373891; + rise_capacitance_range (0.0032575, 0.00419049); + fall_capacitance : 0.00357019; + fall_capacitance_range (0.00308644, 0.00386843); } pin (A2) { direction : "input"; max_transition : 2.5074; - capacitance : 0.00357871; - rise_capacitance : 0.00381903; - rise_capacitance_range (0.00381903, 0.00381903); - fall_capacitance : 0.00333839; - fall_capacitance_range (0.00333839, 0.00333839); + capacitance : 0.00357868; + rise_capacitance : 0.00381902; + rise_capacitance_range (0.0030603, 0.00454575); + fall_capacitance : 0.00333835; + fall_capacitance_range (0.00309988, 0.00352546); } pin (B1) { direction : "input"; max_transition : 2.5074; - capacitance : 0.0034208; - rise_capacitance : 0.00350017; - rise_capacitance_range (0.00350017, 0.00350017); - fall_capacitance : 0.00334144; - fall_capacitance_range (0.00334144, 0.00334144); + capacitance : 0.00342081; + rise_capacitance : 0.00350019; + rise_capacitance_range (0.00309238, 0.00402183); + fall_capacitance : 0.00334142; + fall_capacitance_range (0.00294271, 0.0037617); } } cell (sg13g2_or2_1) { @@ -25103,18 +25177,18 @@ library (sg13g2_stdcell_fast_1p32V_m40C) { max_transition : 2.5074; capacitance : 0.00266348; rise_capacitance : 0.0026261; - rise_capacitance_range (0.0026261, 0.0026261); + rise_capacitance_range (0.00240743, 0.00280931); fall_capacitance : 0.00270087; - fall_capacitance_range (0.00270087, 0.00270087); + fall_capacitance_range (0.0023139, 0.00291885); } pin (B) { direction : "input"; max_transition : 2.5074; capacitance : 0.00247331; rise_capacitance : 0.00255139; - rise_capacitance_range (0.00255139, 0.00255139); + rise_capacitance_range (0.00215961, 0.00283956); fall_capacitance : 0.00239523; - fall_capacitance_range (0.00239523, 0.00239523); + fall_capacitance_range (0.00218051, 0.00254719); } } cell (sg13g2_or2_2) { @@ -25320,18 +25394,18 @@ library (sg13g2_stdcell_fast_1p32V_m40C) { max_transition : 2.5074; capacitance : 0.00264548; rise_capacitance : 0.00260413; - rise_capacitance_range (0.00260413, 0.00260413); + rise_capacitance_range (0.00241935, 0.00277087); fall_capacitance : 0.00268683; - fall_capacitance_range (0.00268683, 0.00268683); + fall_capacitance_range (0.0023141, 0.00288906); } pin (B) { direction : "input"; max_transition : 2.5074; capacitance : 0.00244862; rise_capacitance : 0.00252171; - rise_capacitance_range (0.00252171, 0.00252171); + rise_capacitance_range (0.00221642, 0.00277233); fall_capacitance : 0.00237552; - fall_capacitance_range (0.00237552, 0.00237552); + fall_capacitance_range (0.00219657, 0.00251078); } } cell (sg13g2_or3_1) { @@ -25639,27 +25713,27 @@ library (sg13g2_stdcell_fast_1p32V_m40C) { max_transition : 2.5074; capacitance : 0.00281421; rise_capacitance : 0.00277955; - rise_capacitance_range (0.00277955, 0.00277955); + rise_capacitance_range (0.00258485, 0.00294638); fall_capacitance : 0.00284887; - fall_capacitance_range (0.00284887, 0.00284887); + fall_capacitance_range (0.00238248, 0.00314619); } pin (B) { direction : "input"; max_transition : 2.5074; capacitance : 0.00273909; rise_capacitance : 0.00276561; - rise_capacitance_range (0.00276561, 0.00276561); + rise_capacitance_range (0.00241968, 0.00301522); fall_capacitance : 0.00271257; - fall_capacitance_range (0.00271257, 0.00271257); + fall_capacitance_range (0.00226602, 0.00295683); } pin (C) { direction : "input"; max_transition : 2.5074; capacitance : 0.00259532; rise_capacitance : 0.00273444; - rise_capacitance_range (0.00273444, 0.00273444); + rise_capacitance_range (0.00225491, 0.00308844); fall_capacitance : 0.0024562; - fall_capacitance_range (0.0024562, 0.0024562); + fall_capacitance_range (0.00222928, 0.00260853); } } cell (sg13g2_or3_2) { @@ -25967,27 +26041,27 @@ library (sg13g2_stdcell_fast_1p32V_m40C) { max_transition : 2.5074; capacitance : 0.00280073; rise_capacitance : 0.00276376; - rise_capacitance_range (0.00276376, 0.00276376); + rise_capacitance_range (0.00259083, 0.00292255); fall_capacitance : 0.0028377; - fall_capacitance_range (0.0028377, 0.0028377); + fall_capacitance_range (0.00238356, 0.00311767); } pin (B) { direction : "input"; max_transition : 2.5074; capacitance : 0.00272651; rise_capacitance : 0.00274765; - rise_capacitance_range (0.00274765, 0.00274765); + rise_capacitance_range (0.0024476, 0.00298377); fall_capacitance : 0.00270537; - fall_capacitance_range (0.00270537, 0.00270537); + fall_capacitance_range (0.00227358, 0.00293884); } pin (C) { direction : "input"; max_transition : 2.5074; capacitance : 0.00257686; rise_capacitance : 0.00271086; - rise_capacitance_range (0.00271086, 0.00271086); + rise_capacitance_range (0.00233092, 0.00302501); fall_capacitance : 0.00244285; - fall_capacitance_range (0.00244285, 0.00244285); + fall_capacitance_range (0.00225103, 0.0025781); } } cell (sg13g2_or4_1) { @@ -26413,36 +26487,36 @@ library (sg13g2_stdcell_fast_1p32V_m40C) { max_transition : 2.5074; capacitance : 0.00280767; rise_capacitance : 0.00277195; - rise_capacitance_range (0.00277195, 0.00277195); + rise_capacitance_range (0.00259424, 0.00293555); fall_capacitance : 0.0028434; - fall_capacitance_range (0.0028434, 0.0028434); + fall_capacitance_range (0.00238684, 0.00316562); } pin (B) { direction : "input"; max_transition : 2.5074; capacitance : 0.00270956; rise_capacitance : 0.00272503; - rise_capacitance_range (0.00272503, 0.00272503); + rise_capacitance_range (0.00242079, 0.0029692); fall_capacitance : 0.0026941; - fall_capacitance_range (0.0026941, 0.0026941); + fall_capacitance_range (0.00225734, 0.0029779); } pin (C) { direction : "input"; max_transition : 2.5074; capacitance : 0.00267612; rise_capacitance : 0.00273322; - rise_capacitance_range (0.00273322, 0.00273322); + rise_capacitance_range (0.00233442, 0.00305364); fall_capacitance : 0.00261902; - fall_capacitance_range (0.00261902, 0.00261902); + fall_capacitance_range (0.002197, 0.00284965); } pin (D) { direction : "input"; max_transition : 2.5074; capacitance : 0.00257381; rise_capacitance : 0.00273533; - rise_capacitance_range (0.00273533, 0.00273533); + rise_capacitance_range (0.00224527, 0.00315227); fall_capacitance : 0.00241229; - fall_capacitance_range (0.00241229, 0.00241229); + fall_capacitance_range (0.00221253, 0.0025312); } } cell (sg13g2_or4_2) { @@ -26868,41 +26942,41 @@ library (sg13g2_stdcell_fast_1p32V_m40C) { max_transition : 2.5074; capacitance : 0.00278363; rise_capacitance : 0.00274505; - rise_capacitance_range (0.00274505, 0.00274505); + rise_capacitance_range (0.00258441, 0.00290019); fall_capacitance : 0.0028222; - fall_capacitance_range (0.0028222, 0.0028222); + fall_capacitance_range (0.00237396, 0.00312989); } pin (B) { direction : "input"; max_transition : 2.5074; capacitance : 0.00270312; rise_capacitance : 0.00271394; - rise_capacitance_range (0.00271394, 0.00271394); + rise_capacitance_range (0.00243538, 0.0029434); fall_capacitance : 0.0026923; - fall_capacitance_range (0.0026923, 0.0026923); + fall_capacitance_range (0.00226414, 0.00296642); } pin (C) { direction : "input"; max_transition : 2.5074; capacitance : 0.00266761; rise_capacitance : 0.00271757; - rise_capacitance_range (0.00271757, 0.00271757); + rise_capacitance_range (0.00237054, 0.0030173); fall_capacitance : 0.00261765; - fall_capacitance_range (0.00261765, 0.00261765); + fall_capacitance_range (0.00220499, 0.00284178); } pin (D) { direction : "input"; max_transition : 2.5074; capacitance : 0.00255761; rise_capacitance : 0.00271122; - rise_capacitance_range (0.00271122, 0.00271122); + rise_capacitance_range (0.00231564, 0.00307956); fall_capacitance : 0.002404; - fall_capacitance_range (0.002404, 0.002404); + fall_capacitance_range (0.00223469, 0.00251172); } } cell (sg13g2_sdfbbp_1) { area : 63.504; - cell_footprint : "sdfrrs"; + cell_footprint : "sdfbbp"; cell_leakage_power : 1677.4; dont_touch : true; dont_use : true; @@ -26998,6 +27072,7 @@ library (sg13g2_stdcell_fast_1p32V_m40C) { timing () { related_pin : "CLK"; sdf_cond : "SCE == 1'b1"; + sdf_edges : start_edge; timing_sense : non_unate; timing_type : rising_edge; when : "SCE"; @@ -27056,6 +27131,7 @@ library (sg13g2_stdcell_fast_1p32V_m40C) { } timing () { related_pin : "CLK"; + sdf_edges : start_edge; timing_sense : non_unate; timing_type : rising_edge; cell_rise (TIMING_DELAY_7x7ds1) { @@ -27113,6 +27189,7 @@ library (sg13g2_stdcell_fast_1p32V_m40C) { } timing () { related_pin : "RESET_B"; + sdf_edges : start_edge; timing_sense : positive_unate; timing_type : clear; cell_fall (TIMING_DELAY_7x7ds1) { @@ -27144,6 +27221,7 @@ library (sg13g2_stdcell_fast_1p32V_m40C) { } timing () { related_pin : "SET_B"; + sdf_edges : start_edge; timing_sense : negative_unate; timing_type : preset; cell_rise (TIMING_DELAY_7x7ds1) { @@ -27283,6 +27361,7 @@ library (sg13g2_stdcell_fast_1p32V_m40C) { timing () { related_pin : "CLK"; sdf_cond : "SCE == 1'b1"; + sdf_edges : start_edge; timing_sense : non_unate; timing_type : rising_edge; when : "SCE"; @@ -27341,6 +27420,7 @@ library (sg13g2_stdcell_fast_1p32V_m40C) { } timing () { related_pin : "CLK"; + sdf_edges : start_edge; timing_sense : non_unate; timing_type : rising_edge; cell_rise (TIMING_DELAY_7x7ds1) { @@ -27398,6 +27478,7 @@ library (sg13g2_stdcell_fast_1p32V_m40C) { } timing () { related_pin : "RESET_B"; + sdf_edges : start_edge; timing_sense : negative_unate; timing_type : preset; cell_rise (TIMING_DELAY_7x7ds1) { @@ -27429,6 +27510,7 @@ library (sg13g2_stdcell_fast_1p32V_m40C) { } timing () { related_pin : "SET_B"; + sdf_edges : start_edge; timing_sense : positive_unate; timing_type : clear; cell_fall (TIMING_DELAY_7x7ds1) { @@ -27566,9 +27648,9 @@ library (sg13g2_stdcell_fast_1p32V_m40C) { max_transition : 2.5074; capacitance : 0.00324932; rise_capacitance : 0.00328304; - rise_capacitance_range (0.00328304, 0.00328304); + rise_capacitance_range (0.00299313, 0.00352038); fall_capacitance : 0.00320718; - fall_capacitance_range (0.00320718, 0.00320718); + fall_capacitance_range (0.00293792, 0.00347322); timing () { related_pin : "CLK"; timing_type : min_pulse_width; @@ -27724,11 +27806,12 @@ library (sg13g2_stdcell_fast_1p32V_m40C) { max_transition : 2.5074; capacitance : 0.00209963; rise_capacitance : 0.00213169; - rise_capacitance_range (0.00213169, 0.00213169); + rise_capacitance_range (0.00192237, 0.00228689); fall_capacitance : 0.00206757; - fall_capacitance_range (0.00206757, 0.00206757); + fall_capacitance_range (0.0018916, 0.00219701); timing () { related_pin : "CLK"; + sdf_edges : both_edges; timing_type : hold_rising; rise_constraint (CONSTRAINT_4x4) { index_1 ("0.0186, 0.51636, 1.263, 2.5074"); @@ -27753,6 +27836,7 @@ library (sg13g2_stdcell_fast_1p32V_m40C) { } timing () { related_pin : "CLK"; + sdf_edges : both_edges; timing_type : setup_rising; rise_constraint (CONSTRAINT_4x4) { index_1 ("0.0186, 0.51636, 1.263, 2.5074"); @@ -27827,9 +27911,10 @@ library (sg13g2_stdcell_fast_1p32V_m40C) { rise_capacitance : 0.00187053; rise_capacitance_range (0.00187053, 0.00187053); fall_capacitance : 0.00187053; - fall_capacitance_range (0.00187053, 0.00187053); + fall_capacitance_range (0.00174038, 0.00200072); timing () { related_pin : "CLK"; + sdf_edges : both_edges; timing_type : recovery_rising; rise_constraint (CONSTRAINT_4x4) { index_1 ("0.0186, 0.51636, 1.263, 2.5074"); @@ -27844,6 +27929,7 @@ library (sg13g2_stdcell_fast_1p32V_m40C) { } timing () { related_pin : "CLK"; + sdf_edges : both_edges; timing_type : removal_rising; rise_constraint (CONSTRAINT_4x4) { index_1 ("0.0186, 0.51636, 1.263, 2.5074"); @@ -27873,11 +27959,12 @@ library (sg13g2_stdcell_fast_1p32V_m40C) { max_transition : 2.5074; capacitance : 0.00214532; rise_capacitance : 0.00215506; - rise_capacitance_range (0.00215506, 0.00215506); + rise_capacitance_range (0.00188544, 0.00233685); fall_capacitance : 0.00213558; - fall_capacitance_range (0.00213558, 0.00213558); + fall_capacitance_range (0.00185995, 0.00230675); timing () { related_pin : "CLK"; + sdf_edges : both_edges; timing_type : hold_rising; rise_constraint (CONSTRAINT_4x4) { index_1 ("0.0186, 0.51636, 1.263, 2.5074"); @@ -27902,6 +27989,7 @@ library (sg13g2_stdcell_fast_1p32V_m40C) { } timing () { related_pin : "CLK"; + sdf_edges : both_edges; timing_type : setup_rising; rise_constraint (CONSTRAINT_4x4) { index_1 ("0.0186, 0.51636, 1.263, 2.5074"); @@ -27975,11 +28063,12 @@ library (sg13g2_stdcell_fast_1p32V_m40C) { max_transition : 2.5074; capacitance : 0.00378653; rise_capacitance : 0.00417392; - rise_capacitance_range (0.00417392, 0.00417392); + rise_capacitance_range (0.00412728, 0.00476208); fall_capacitance : 0.00339913; - fall_capacitance_range (0.00339913, 0.00339913); + fall_capacitance_range (0.00339913, 0.00454054); timing () { related_pin : "CLK"; + sdf_edges : both_edges; timing_type : hold_rising; rise_constraint (CONSTRAINT_4x4) { index_1 ("0.0186, 0.51636, 1.263, 2.5074"); @@ -28004,6 +28093,7 @@ library (sg13g2_stdcell_fast_1p32V_m40C) { } timing () { related_pin : "CLK"; + sdf_edges : both_edges; timing_type : setup_rising; rise_constraint (CONSTRAINT_4x4) { index_1 ("0.0186, 0.51636, 1.263, 2.5074"); @@ -28108,9 +28198,10 @@ library (sg13g2_stdcell_fast_1p32V_m40C) { rise_capacitance : 0.00563188; rise_capacitance_range (0.00563188, 0.00563188); fall_capacitance : 0.00563188; - fall_capacitance_range (0.00563188, 0.00563188); + fall_capacitance_range (0.00523616, 0.00601019); timing () { related_pin : "CLK"; + sdf_edges : both_edges; timing_type : recovery_rising; rise_constraint (CONSTRAINT_4x4) { index_1 ("0.0186, 0.51636, 1.263, 2.5074"); @@ -28125,6 +28216,7 @@ library (sg13g2_stdcell_fast_1p32V_m40C) { } timing () { related_pin : "CLK"; + sdf_edges : both_edges; timing_type : removal_rising; rise_constraint (CONSTRAINT_4x4) { index_1 ("0.0186, 0.51636, 1.263, 2.5074"); @@ -28139,6 +28231,7 @@ library (sg13g2_stdcell_fast_1p32V_m40C) { } timing () { related_pin : "RESET_B"; + sdf_edges : both_edges; timing_type : non_seq_hold_rising; rise_constraint (CONSTRAINT_4x4) { index_1 ("0.0186, 0.51636, 1.263, 2.5074"); @@ -28153,6 +28246,7 @@ library (sg13g2_stdcell_fast_1p32V_m40C) { } timing () { related_pin : "RESET_B"; + sdf_edges : both_edges; timing_type : non_seq_setup_rising; rise_constraint (CONSTRAINT_4x4) { index_1 ("0.0186, 0.51636, 1.263, 2.5074"); @@ -28177,12 +28271,12 @@ library (sg13g2_stdcell_fast_1p32V_m40C) { } } ff (IQ,IQN) { - clear : "RESET_B'"; + clear : "!RESET_B"; clear_preset_var1 : "H"; clear_preset_var2 : "L"; clocked_on : "CLK"; - next_state : "(SCE*SCD)+(SCE'*D)"; - preset : "SET_B'"; + next_state : "(SCE*SCD)+(!SCE*D)"; + preset : "!SET_B"; } test_cell () { pin (Q) { @@ -28216,12 +28310,12 @@ library (sg13g2_stdcell_fast_1p32V_m40C) { direction : input; } ff (IQ,IQN) { - clear : "RESET_B'"; + clear : "!RESET_B"; clear_preset_var1 : H; clear_preset_var2 : L; clocked_on : "CLK"; next_state : "D"; - preset : "SET_B'"; + preset : "!SET_B"; } } } @@ -28242,7 +28336,7 @@ library (sg13g2_stdcell_fast_1p32V_m40C) { when : "!CLK&!D&!RESET_B&!SCD&!SCE&Q&!Q_N"; } leakage_power () { - value : 1696.84; + value : 1696.83; when : "CLK&!D&RESET_B&!SCD&!SCE&!Q"; } leakage_power () { @@ -28305,6 +28399,7 @@ library (sg13g2_stdcell_fast_1p32V_m40C) { timing () { related_pin : "CLK"; sdf_cond : "SCE == 1'b1"; + sdf_edges : start_edge; timing_sense : non_unate; timing_type : rising_edge; when : "SCE"; @@ -28312,7 +28407,7 @@ library (sg13g2_stdcell_fast_1p32V_m40C) { index_1 ("0.0186, 0.0966, 0.174, 0.3294, 0.6408, 1.263, 2.5074"); index_2 ("0.001, 0.0234, 0.039, 0.0648, 0.108, 0.18, 0.3"); values ( \ - "0.127731, 0.166113, 0.193799, 0.239647, 0.316496, 0.444608, 0.658185", \ + "0.127744, 0.166113, 0.19382, 0.239647, 0.316477, 0.444606, 0.658185", \ "0.157331, 0.195773, 0.223442, 0.269277, 0.346163, 0.474288, 0.687874", \ "0.177161, 0.215541, 0.243185, 0.289058, 0.365883, 0.494019, 0.707536", \ "0.204775, 0.243108, 0.270786, 0.316631, 0.393571, 0.521578, 0.735109", \ @@ -28325,24 +28420,24 @@ library (sg13g2_stdcell_fast_1p32V_m40C) { index_1 ("0.0186, 0.0966, 0.174, 0.3294, 0.6408, 1.263, 2.5074"); index_2 ("0.001, 0.0234, 0.039, 0.0648, 0.108, 0.18, 0.3"); values ( \ - "0.0137757, 0.0672613, 0.107614, 0.174679, 0.287077, 0.474407, 0.786891", \ - "0.0137767, 0.0672623, 0.107627, 0.17468, 0.287079, 0.474465, 0.786984", \ - "0.0138196, 0.0672633, 0.107634, 0.174681, 0.28708, 0.474466, 0.788483", \ - "0.0138352, 0.0672636, 0.107635, 0.174682, 0.287081, 0.474467, 0.788484", \ - "0.0140089, 0.0672985, 0.107636, 0.174683, 0.287082, 0.474468, 0.788485", \ - "0.014314, 0.067327, 0.107649, 0.174687, 0.287083, 0.474469, 0.788486", \ - "0.015374, 0.067482, 0.107714, 0.174733, 0.287129, 0.474487, 0.788487" \ + "0.0137898, 0.0672612, 0.107613, 0.174679, 0.287077, 0.474501, 0.786891", \ + "0.0137908, 0.0672622, 0.107627, 0.17468, 0.287079, 0.474502, 0.786984", \ + "0.0138196, 0.0672632, 0.107634, 0.174681, 0.28708, 0.474503, 0.788483", \ + "0.0138352, 0.0672636, 0.107635, 0.174682, 0.287081, 0.474504, 0.788484", \ + "0.0140089, 0.0672985, 0.107636, 0.174683, 0.287082, 0.474505, 0.788485", \ + "0.014314, 0.067327, 0.107649, 0.174687, 0.287083, 0.474506, 0.788486", \ + "0.015374, 0.067482, 0.107714, 0.174733, 0.287129, 0.474507, 0.788487" \ ); } cell_fall (TIMING_DELAY_7x7ds1) { index_1 ("0.0186, 0.0966, 0.174, 0.3294, 0.6408, 1.263, 2.5074"); index_2 ("0.001, 0.0234, 0.039, 0.0648, 0.108, 0.18, 0.3"); values ( \ - "0.118807, 0.153368, 0.176556, 0.214701, 0.278577, 0.384974, 0.562536", \ + "0.118805, 0.153368, 0.176556, 0.214701, 0.278577, 0.384974, 0.562536", \ "0.147983, 0.182578, 0.205747, 0.243913, 0.307788, 0.414217, 0.591691", \ "0.167194, 0.201811, 0.225008, 0.263153, 0.326999, 0.43339, 0.610808", \ "0.192587, 0.227211, 0.250391, 0.288548, 0.352392, 0.458788, 0.636099", \ - "0.227332, 0.261913, 0.28548, 0.323653, 0.387524, 0.494033, 0.671321", \ + "0.22773, 0.2623, 0.285085, 0.323653, 0.387119, 0.494033, 0.670898", \ "0.275218, 0.309779, 0.332952, 0.371126, 0.434999, 0.541467, 0.718745", \ "0.338492, 0.373041, 0.396197, 0.434383, 0.498249, 0.604692, 0.782035" \ ); @@ -28351,25 +28446,26 @@ library (sg13g2_stdcell_fast_1p32V_m40C) { index_1 ("0.0186, 0.0966, 0.174, 0.3294, 0.6408, 1.263, 2.5074"); index_2 ("0.001, 0.0234, 0.039, 0.0648, 0.108, 0.18, 0.3"); values ( \ - "0.0112882, 0.0543867, 0.0860959, 0.139023, 0.227859, 0.376214, 0.623362", \ - "0.0112892, 0.0543877, 0.0860991, 0.139024, 0.228038, 0.376407, 0.623526", \ - "0.0112902, 0.0543887, 0.0861037, 0.139025, 0.228039, 0.376408, 0.624382", \ - "0.0112912, 0.0543897, 0.0861047, 0.139026, 0.22804, 0.376409, 0.624383", \ - "0.0112922, 0.0543907, 0.0861057, 0.139027, 0.228041, 0.37641, 0.624384", \ - "0.0112932, 0.0543917, 0.0861067, 0.139028, 0.228042, 0.376411, 0.624385", \ - "0.0112942, 0.0543927, 0.086107, 0.139029, 0.228043, 0.376439, 0.624386" \ + "0.0112911, 0.0543867, 0.0860959, 0.139023, 0.227859, 0.376214, 0.623362", \ + "0.0112921, 0.0543877, 0.0860991, 0.139024, 0.228038, 0.376407, 0.623526", \ + "0.0112931, 0.0543887, 0.0861037, 0.139025, 0.228039, 0.376408, 0.624382", \ + "0.0112941, 0.0543897, 0.0861047, 0.139026, 0.22804, 0.376409, 0.624383", \ + "0.0112954, 0.0543907, 0.0861057, 0.139027, 0.228041, 0.37641, 0.624384", \ + "0.0112964, 0.0543917, 0.0861067, 0.139028, 0.228042, 0.376411, 0.624385", \ + "0.0112974, 0.0543927, 0.086107, 0.139029, 0.228043, 0.376439, 0.624386" \ ); } } timing () { related_pin : "CLK"; + sdf_edges : start_edge; timing_sense : non_unate; timing_type : rising_edge; cell_rise (TIMING_DELAY_7x7ds1) { index_1 ("0.0186, 0.0966, 0.174, 0.3294, 0.6408, 1.263, 2.5074"); index_2 ("0.001, 0.0234, 0.039, 0.0648, 0.108, 0.18, 0.3"); values ( \ - "0.127731, 0.166113, 0.193799, 0.239647, 0.316496, 0.444608, 0.658185", \ + "0.127744, 0.166113, 0.19382, 0.239647, 0.316477, 0.444606, 0.658185", \ "0.157331, 0.195773, 0.223442, 0.269277, 0.346163, 0.474288, 0.687874", \ "0.177161, 0.215541, 0.243185, 0.289058, 0.365883, 0.494019, 0.707536", \ "0.204775, 0.243108, 0.270786, 0.316631, 0.393571, 0.521578, 0.735109", \ @@ -28382,24 +28478,24 @@ library (sg13g2_stdcell_fast_1p32V_m40C) { index_1 ("0.0186, 0.0966, 0.174, 0.3294, 0.6408, 1.263, 2.5074"); index_2 ("0.001, 0.0234, 0.039, 0.0648, 0.108, 0.18, 0.3"); values ( \ - "0.0137757, 0.0672613, 0.107614, 0.174679, 0.287077, 0.474407, 0.786891", \ - "0.0137767, 0.0672623, 0.107627, 0.17468, 0.287079, 0.474465, 0.786984", \ - "0.0138196, 0.0672633, 0.107634, 0.174681, 0.28708, 0.474466, 0.788483", \ - "0.0138352, 0.0672636, 0.107635, 0.174682, 0.287081, 0.474467, 0.788484", \ - "0.0140089, 0.0672985, 0.107636, 0.174683, 0.287082, 0.474468, 0.788485", \ - "0.014314, 0.067327, 0.107649, 0.174687, 0.287083, 0.474469, 0.788486", \ - "0.015374, 0.067482, 0.107714, 0.174733, 0.287129, 0.474487, 0.788487" \ + "0.0137898, 0.0672612, 0.107613, 0.174679, 0.287077, 0.474501, 0.786891", \ + "0.0137908, 0.0672622, 0.107627, 0.17468, 0.287079, 0.474502, 0.786984", \ + "0.0138196, 0.0672632, 0.107634, 0.174681, 0.28708, 0.474503, 0.788483", \ + "0.0138352, 0.0672636, 0.107635, 0.174682, 0.287081, 0.474504, 0.788484", \ + "0.0140089, 0.0672985, 0.107636, 0.174683, 0.287082, 0.474505, 0.788485", \ + "0.014314, 0.067327, 0.107649, 0.174687, 0.287083, 0.474506, 0.788486", \ + "0.015374, 0.067482, 0.107714, 0.174733, 0.287129, 0.474507, 0.788487" \ ); } cell_fall (TIMING_DELAY_7x7ds1) { index_1 ("0.0186, 0.0966, 0.174, 0.3294, 0.6408, 1.263, 2.5074"); index_2 ("0.001, 0.0234, 0.039, 0.0648, 0.108, 0.18, 0.3"); values ( \ - "0.118807, 0.153368, 0.176556, 0.214701, 0.278577, 0.384974, 0.562536", \ + "0.118805, 0.153368, 0.176556, 0.214701, 0.278577, 0.384974, 0.562536", \ "0.147983, 0.182578, 0.205747, 0.243913, 0.307788, 0.414217, 0.591691", \ "0.167194, 0.201811, 0.225008, 0.263153, 0.326999, 0.43339, 0.610808", \ "0.192587, 0.227211, 0.250391, 0.288548, 0.352392, 0.458788, 0.636099", \ - "0.227332, 0.261913, 0.28548, 0.323653, 0.387524, 0.494033, 0.671321", \ + "0.22773, 0.2623, 0.285085, 0.323653, 0.387119, 0.494033, 0.670898", \ "0.275218, 0.309779, 0.332952, 0.371126, 0.434999, 0.541467, 0.718745", \ "0.338492, 0.373041, 0.396197, 0.434383, 0.498249, 0.604692, 0.782035" \ ); @@ -28408,44 +28504,45 @@ library (sg13g2_stdcell_fast_1p32V_m40C) { index_1 ("0.0186, 0.0966, 0.174, 0.3294, 0.6408, 1.263, 2.5074"); index_2 ("0.001, 0.0234, 0.039, 0.0648, 0.108, 0.18, 0.3"); values ( \ - "0.0112882, 0.0543867, 0.0860959, 0.139023, 0.227859, 0.376214, 0.623362", \ - "0.0112892, 0.0543877, 0.0860991, 0.139024, 0.228038, 0.376407, 0.623526", \ - "0.0112902, 0.0543887, 0.0861037, 0.139025, 0.228039, 0.376408, 0.624382", \ - "0.0112912, 0.0543897, 0.0861047, 0.139026, 0.22804, 0.376409, 0.624383", \ - "0.0112922, 0.0543907, 0.0861057, 0.139027, 0.228041, 0.37641, 0.624384", \ - "0.0112932, 0.0543917, 0.0861067, 0.139028, 0.228042, 0.376411, 0.624385", \ - "0.0112942, 0.0543927, 0.086107, 0.139029, 0.228043, 0.376439, 0.624386" \ + "0.0112911, 0.0543867, 0.0860959, 0.139023, 0.227859, 0.376214, 0.623362", \ + "0.0112921, 0.0543877, 0.0860991, 0.139024, 0.228038, 0.376407, 0.623526", \ + "0.0112931, 0.0543887, 0.0861037, 0.139025, 0.228039, 0.376408, 0.624382", \ + "0.0112941, 0.0543897, 0.0861047, 0.139026, 0.22804, 0.376409, 0.624383", \ + "0.0112954, 0.0543907, 0.0861057, 0.139027, 0.228041, 0.37641, 0.624384", \ + "0.0112964, 0.0543917, 0.0861067, 0.139028, 0.228042, 0.376411, 0.624385", \ + "0.0112974, 0.0543927, 0.086107, 0.139029, 0.228043, 0.376439, 0.624386" \ ); } } timing () { related_pin : "RESET_B"; + sdf_edges : start_edge; timing_sense : positive_unate; timing_type : clear; cell_fall (TIMING_DELAY_7x7ds1) { index_1 ("0.0186, 0.0966, 0.174, 0.3294, 0.6408, 1.263, 2.5074"); index_2 ("0.001, 0.0234, 0.039, 0.0648, 0.108, 0.18, 0.3"); values ( \ - "0.162753, 0.197211, 0.220425, 0.258674, 0.32249, 0.428965, 0.606442", \ - "0.200346, 0.234879, 0.258038, 0.296284, 0.360181, 0.466641, 0.644047", \ - "0.227957, 0.262377, 0.285537, 0.323767, 0.387585, 0.494089, 0.671436", \ - "0.269501, 0.303967, 0.32711, 0.365306, 0.429231, 0.535638, 0.712997", \ - "0.328502, 0.362945, 0.386069, 0.424293, 0.488258, 0.594659, 0.772019", \ - "0.410169, 0.444488, 0.46765, 0.505816, 0.569741, 0.676181, 0.853588", \ - "0.522487, 0.556649, 0.579748, 0.617933, 0.681901, 0.788363, 0.965826" \ + "0.162771, 0.197228, 0.220382, 0.258554, 0.322483, 0.428971, 0.606445", \ + "0.200353, 0.234884, 0.258057, 0.296317, 0.360216, 0.466647, 0.644041", \ + "0.227937, 0.26235, 0.285469, 0.323726, 0.387569, 0.494029, 0.671517", \ + "0.269644, 0.304142, 0.327301, 0.365521, 0.42945, 0.535831, 0.713163", \ + "0.328368, 0.362805, 0.385979, 0.424217, 0.488072, 0.594514, 0.771892", \ + "0.410085, 0.444406, 0.467579, 0.505735, 0.569658, 0.676099, 0.853506", \ + "0.522385, 0.556751, 0.579917, 0.61803, 0.6818, 0.788453, 0.96558" \ ); } fall_transition (TIMING_DELAY_7x7ds1) { index_1 ("0.0186, 0.0966, 0.174, 0.3294, 0.6408, 1.263, 2.5074"); index_2 ("0.001, 0.0234, 0.039, 0.0648, 0.108, 0.18, 0.3"); values ( \ - "0.0111518, 0.0542858, 0.0859864, 0.138941, 0.227913, 0.376246, 0.623624", \ - "0.0111528, 0.0542868, 0.0859874, 0.138985, 0.228831, 0.376247, 0.623625", \ - "0.0111569, 0.0542878, 0.0860217, 0.138986, 0.228832, 0.376285, 0.624272", \ - "0.0111971, 0.0542957, 0.0860222, 0.138987, 0.228833, 0.376286, 0.624273", \ - "0.011256, 0.054321, 0.0860232, 0.138988, 0.228834, 0.376287, 0.624274", \ - "0.011404, 0.054352, 0.086066, 0.138993, 0.228835, 0.376288, 0.624275", \ - "0.01158, 0.054421, 0.086067, 0.13901, 0.228836, 0.376289, 0.624276" \ + "0.0111368, 0.054286, 0.0860232, 0.139001, 0.227916, 0.376246, 0.623624", \ + "0.0111378, 0.054287, 0.0860565, 0.139002, 0.228557, 0.376247, 0.623625", \ + "0.0111517, 0.054288, 0.0860575, 0.139003, 0.228558, 0.376286, 0.623626", \ + "0.0111961, 0.0542979, 0.0860754, 0.139004, 0.228559, 0.376287, 0.623627", \ + "0.0112544, 0.0543127, 0.0860764, 0.139005, 0.22856, 0.376288, 0.623628", \ + "0.011403, 0.054352, 0.086093, 0.139006, 0.228561, 0.376289, 0.623629", \ + "0.01158, 0.054421, 0.086094, 0.139019, 0.228562, 0.37629, 0.62363" \ ); } } @@ -28456,24 +28553,24 @@ library (sg13g2_stdcell_fast_1p32V_m40C) { index_1 ("0.0186, 0.0966, 0.174, 0.3294, 0.6408, 1.263, 2.5074"); index_2 ("0.001, 0.0234, 0.039, 0.0648, 0.108, 0.18, 0.3"); values ( \ - "0.0377629, 0.0579819, 0.0716882, 0.0941901, 0.131786, 0.194148, 0.298286", \ + "0.0377708, 0.0579819, 0.0716898, 0.0941901, 0.131779, 0.194167, 0.298286", \ "0.0375575, 0.0577376, 0.0715621, 0.0939812, 0.131645, 0.193994, 0.297947", \ "0.0381746, 0.0582362, 0.0719594, 0.0945562, 0.132322, 0.194651, 0.299135", \ "0.039588, 0.0596891, 0.0734582, 0.0959308, 0.133449, 0.196426, 0.299885", \ - "0.0431431, 0.0630248, 0.0768132, 0.0994344, 0.137194, 0.199492, 0.303862", \ - "0.0510857, 0.0707071, 0.0845172, 0.107045, 0.144778, 0.207579, 0.311903", \ - "0.0681809, 0.0873286, 0.100981, 0.123539, 0.161334, 0.224009, 0.328583" \ + "0.0431431, 0.0630249, 0.0768132, 0.0994344, 0.137194, 0.199492, 0.303862", \ + "0.0510859, 0.0707072, 0.0845172, 0.107045, 0.144746, 0.207579, 0.311903", \ + "0.0681809, 0.0873287, 0.100981, 0.123539, 0.161334, 0.224009, 0.328583" \ ); } fall_power (POWER_7x7ds1) { index_1 ("0.0186, 0.0966, 0.174, 0.3294, 0.6408, 1.263, 2.5074"); index_2 ("0.001, 0.0234, 0.039, 0.0648, 0.108, 0.18, 0.3"); values ( \ - "0.0380647, 0.0583133, 0.0719595, 0.0943494, 0.131685, 0.193801, 0.297258", \ + "0.0380629, 0.0583133, 0.0719595, 0.0943493, 0.131685, 0.193801, 0.297258", \ "0.0381212, 0.0583355, 0.0720478, 0.09483, 0.131887, 0.193896, 0.297296", \ "0.0388717, 0.0591687, 0.0727739, 0.0951182, 0.133, 0.194694, 0.29847", \ - "0.0404081, 0.0607004, 0.0744548, 0.0969749, 0.134072, 0.196684, 0.30014", \ - "0.0439262, 0.0640949, 0.0778667, 0.100245, 0.138215, 0.200447, 0.303743", \ + "0.0404082, 0.0607018, 0.0744548, 0.0969749, 0.134072, 0.196685, 0.30014", \ + "0.043909, 0.0640788, 0.0778659, 0.100245, 0.138254, 0.200447, 0.303771", \ "0.0515805, 0.0717201, 0.0854172, 0.108039, 0.145608, 0.2082, 0.312859", \ "0.0678209, 0.0878719, 0.101445, 0.123805, 0.16143, 0.224322, 0.328602" \ ); @@ -28485,24 +28582,24 @@ library (sg13g2_stdcell_fast_1p32V_m40C) { index_1 ("0.0186, 0.0966, 0.174, 0.3294, 0.6408, 1.263, 2.5074"); index_2 ("0.001, 0.0234, 0.039, 0.0648, 0.108, 0.18, 0.3"); values ( \ - "0.0377629, 0.0579819, 0.0716882, 0.0941901, 0.131786, 0.194148, 0.298286", \ + "0.0377708, 0.0579819, 0.0716898, 0.0941901, 0.131779, 0.194167, 0.298286", \ "0.0375575, 0.0577376, 0.0715621, 0.0939812, 0.131645, 0.193994, 0.297947", \ "0.0381746, 0.0582362, 0.0719594, 0.0945562, 0.132322, 0.194651, 0.299135", \ "0.039588, 0.0596891, 0.0734582, 0.0959308, 0.133449, 0.196426, 0.299885", \ - "0.0431431, 0.0630248, 0.0768132, 0.0994344, 0.137194, 0.199492, 0.303862", \ - "0.0510857, 0.0707071, 0.0845172, 0.107045, 0.144778, 0.207579, 0.311903", \ - "0.0681809, 0.0873286, 0.100981, 0.123539, 0.161334, 0.224009, 0.328583" \ + "0.0431431, 0.0630249, 0.0768132, 0.0994344, 0.137194, 0.199492, 0.303862", \ + "0.0510859, 0.0707072, 0.0845172, 0.107045, 0.144746, 0.207579, 0.311903", \ + "0.0681809, 0.0873287, 0.100981, 0.123539, 0.161334, 0.224009, 0.328583" \ ); } fall_power (POWER_7x7ds1) { index_1 ("0.0186, 0.0966, 0.174, 0.3294, 0.6408, 1.263, 2.5074"); index_2 ("0.001, 0.0234, 0.039, 0.0648, 0.108, 0.18, 0.3"); values ( \ - "0.0380647, 0.0583133, 0.0719595, 0.0943494, 0.131685, 0.193801, 0.297258", \ + "0.0380629, 0.0583133, 0.0719595, 0.0943493, 0.131685, 0.193801, 0.297258", \ "0.0381212, 0.0583355, 0.0720478, 0.09483, 0.131887, 0.193896, 0.297296", \ "0.0388717, 0.0591687, 0.0727739, 0.0951182, 0.133, 0.194694, 0.29847", \ - "0.0404081, 0.0607004, 0.0744548, 0.0969749, 0.134072, 0.196684, 0.30014", \ - "0.0439262, 0.0640949, 0.0778667, 0.100245, 0.138215, 0.200447, 0.303743", \ + "0.0404082, 0.0607018, 0.0744548, 0.0969749, 0.134072, 0.196685, 0.30014", \ + "0.043909, 0.0640788, 0.0778659, 0.100245, 0.138254, 0.200447, 0.303771", \ "0.0515805, 0.0717201, 0.0854172, 0.108039, 0.145608, 0.2082, 0.312859", \ "0.0678209, 0.0878719, 0.101445, 0.123805, 0.16143, 0.224322, 0.328602" \ ); @@ -28519,13 +28616,13 @@ library (sg13g2_stdcell_fast_1p32V_m40C) { index_1 ("0.0186, 0.0966, 0.174, 0.3294, 0.6408, 1.263, 2.5074"); index_2 ("0.001, 0.0234, 0.039, 0.0648, 0.108, 0.18, 0.3"); values ( \ - "0.0458283, 0.0659964, 0.079651, 0.102066, 0.139402, 0.201532, 0.305053", \ - "0.0454738, 0.0656653, 0.0796059, 0.101807, 0.139417, 0.201213, 0.304686", \ - "0.0459083, 0.0660004, 0.0796217, 0.102215, 0.140354, 0.20174, 0.305368", \ - "0.0474873, 0.0675919, 0.0813518, 0.103725, 0.140939, 0.203985, 0.306594", \ - "0.0512612, 0.0713237, 0.0849721, 0.107672, 0.145389, 0.207287, 0.311224", \ - "0.0594827, 0.0793631, 0.0928951, 0.115517, 0.153195, 0.216146, 0.320146", \ - "0.075712, 0.0952993, 0.108882, 0.131442, 0.169019, 0.231774, 0.336212" \ + "0.0395108, 0.0596728, 0.073329, 0.0957066, 0.13308, 0.195214, 0.298732", \ + "0.039117, 0.0593075, 0.0732223, 0.0954548, 0.133018, 0.194846, 0.298231", \ + "0.0395783, 0.0596443, 0.0732997, 0.0958809, 0.133978, 0.1954, 0.298771", \ + "0.0410594, 0.0611744, 0.0749361, 0.0973347, 0.134488, 0.197546, 0.30024", \ + "0.0448904, 0.0649494, 0.0785949, 0.101283, 0.138993, 0.200684, 0.304724", \ + "0.0529312, 0.0728116, 0.0863461, 0.108966, 0.146644, 0.209603, 0.313681", \ + "0.06921, 0.0887898, 0.102377, 0.1249, 0.162517, 0.225254, 0.329584" \ ); } } @@ -28538,6 +28635,7 @@ library (sg13g2_stdcell_fast_1p32V_m40C) { timing () { related_pin : "CLK"; sdf_cond : "SCE == 1'b1"; + sdf_edges : start_edge; timing_sense : non_unate; timing_type : rising_edge; when : "SCE"; @@ -28549,7 +28647,7 @@ library (sg13g2_stdcell_fast_1p32V_m40C) { "0.120537, 0.176025, 0.205108, 0.251253, 0.327665, 0.454689, 0.666187", \ "0.13977, 0.195268, 0.224317, 0.270423, 0.346858, 0.473877, 0.685606", \ "0.165214, 0.220666, 0.249731, 0.295835, 0.372259, 0.499303, 0.710713", \ - "0.2004, 0.255337, 0.284791, 0.330957, 0.407361, 0.534106, 0.745884", \ + "0.2004, 0.255337, 0.284791, 0.330957, 0.406938, 0.534531, 0.745447", \ "0.248105, 0.303222, 0.332258, 0.378481, 0.454862, 0.581918, 0.793354", \ "0.311195, 0.366068, 0.395036, 0.441222, 0.517541, 0.644543, 0.856084" \ ); @@ -28562,16 +28660,16 @@ library (sg13g2_stdcell_fast_1p32V_m40C) { "0.0175989, 0.0742462, 0.111642, 0.175902, 0.286409, 0.472333, 0.782836", \ "0.0175999, 0.0742472, 0.111643, 0.175903, 0.28641, 0.472334, 0.782871", \ "0.0176197, 0.0742873, 0.111644, 0.175904, 0.286411, 0.472335, 0.782872", \ - "0.0176207, 0.0742888, 0.111645, 0.175916, 0.286412, 0.472335, 0.782873", \ - "0.0176217, 0.0742898, 0.111646, 0.175919, 0.286413, 0.472336, 0.782874", \ - "0.017746, 0.0742908, 0.111647, 0.17592, 0.286414, 0.472337, 0.782875" \ + "0.0176207, 0.0742888, 0.111645, 0.175916, 0.286472, 0.472336, 0.782873", \ + "0.0176217, 0.0742898, 0.111646, 0.175919, 0.286473, 0.472337, 0.782874", \ + "0.017746, 0.0742908, 0.111647, 0.17592, 0.286474, 0.472338, 0.782875" \ ); } cell_fall (TIMING_DELAY_7x7ds1) { index_1 ("0.0186, 0.0966, 0.174, 0.3294, 0.6408, 1.263, 2.5074"); index_2 ("0.001, 0.0234, 0.039, 0.0648, 0.108, 0.18, 0.3"); values ( \ - "0.0965053, 0.156056, 0.183193, 0.223903, 0.289008, 0.396455, 0.575127", \ + "0.0964786, 0.156056, 0.183197, 0.223903, 0.289022, 0.396454, 0.575128", \ "0.126078, 0.185656, 0.212798, 0.253414, 0.318669, 0.426083, 0.604818", \ "0.145884, 0.205465, 0.232621, 0.273224, 0.338426, 0.445873, 0.624552", \ "0.173342, 0.233013, 0.26019, 0.300851, 0.366066, 0.473488, 0.652156", \ @@ -28584,8 +28682,8 @@ library (sg13g2_stdcell_fast_1p32V_m40C) { index_1 ("0.0186, 0.0966, 0.174, 0.3294, 0.6408, 1.263, 2.5074"); index_2 ("0.001, 0.0234, 0.039, 0.0648, 0.108, 0.18, 0.3"); values ( \ - "0.0209155, 0.0703673, 0.0986241, 0.147625, 0.233835, 0.381405, 0.629855", \ - "0.0209655, 0.0703876, 0.0986251, 0.147626, 0.233845, 0.381689, 0.629896", \ + "0.0209167, 0.0703673, 0.0986061, 0.147625, 0.233835, 0.381406, 0.629856", \ + "0.0209655, 0.0703876, 0.0986071, 0.147626, 0.233845, 0.381689, 0.629896", \ "0.0210528, 0.0704166, 0.0986785, 0.147627, 0.233846, 0.38169, 0.631801", \ "0.0213751, 0.0706114, 0.0987239, 0.147628, 0.233847, 0.381691, 0.631802", \ "0.0222891, 0.0709358, 0.0989668, 0.147847, 0.233873, 0.381692, 0.631803", \ @@ -28596,6 +28694,7 @@ library (sg13g2_stdcell_fast_1p32V_m40C) { } timing () { related_pin : "CLK"; + sdf_edges : start_edge; timing_sense : non_unate; timing_type : rising_edge; cell_rise (TIMING_DELAY_7x7ds1) { @@ -28606,7 +28705,7 @@ library (sg13g2_stdcell_fast_1p32V_m40C) { "0.120537, 0.176025, 0.205108, 0.251253, 0.327665, 0.454689, 0.666187", \ "0.13977, 0.195268, 0.224317, 0.270423, 0.346858, 0.473877, 0.685606", \ "0.165214, 0.220666, 0.249731, 0.295835, 0.372259, 0.499303, 0.710713", \ - "0.2004, 0.255337, 0.284791, 0.330957, 0.407361, 0.534106, 0.745884", \ + "0.2004, 0.255337, 0.284791, 0.330957, 0.406938, 0.534531, 0.745447", \ "0.248105, 0.303222, 0.332258, 0.378481, 0.454862, 0.581918, 0.793354", \ "0.311195, 0.366068, 0.395036, 0.441222, 0.517541, 0.644543, 0.856084" \ ); @@ -28619,16 +28718,16 @@ library (sg13g2_stdcell_fast_1p32V_m40C) { "0.0175989, 0.0742462, 0.111642, 0.175902, 0.286409, 0.472333, 0.782836", \ "0.0175999, 0.0742472, 0.111643, 0.175903, 0.28641, 0.472334, 0.782871", \ "0.0176197, 0.0742873, 0.111644, 0.175904, 0.286411, 0.472335, 0.782872", \ - "0.0176207, 0.0742888, 0.111645, 0.175916, 0.286412, 0.472335, 0.782873", \ - "0.0176217, 0.0742898, 0.111646, 0.175919, 0.286413, 0.472336, 0.782874", \ - "0.017746, 0.0742908, 0.111647, 0.17592, 0.286414, 0.472337, 0.782875" \ + "0.0176207, 0.0742888, 0.111645, 0.175916, 0.286472, 0.472336, 0.782873", \ + "0.0176217, 0.0742898, 0.111646, 0.175919, 0.286473, 0.472337, 0.782874", \ + "0.017746, 0.0742908, 0.111647, 0.17592, 0.286474, 0.472338, 0.782875" \ ); } cell_fall (TIMING_DELAY_7x7ds1) { index_1 ("0.0186, 0.0966, 0.174, 0.3294, 0.6408, 1.263, 2.5074"); index_2 ("0.001, 0.0234, 0.039, 0.0648, 0.108, 0.18, 0.3"); values ( \ - "0.0965053, 0.156056, 0.183193, 0.223903, 0.289008, 0.396455, 0.575127", \ + "0.0964786, 0.156056, 0.183197, 0.223903, 0.289022, 0.396454, 0.575128", \ "0.126078, 0.185656, 0.212798, 0.253414, 0.318669, 0.426083, 0.604818", \ "0.145884, 0.205465, 0.232621, 0.273224, 0.338426, 0.445873, 0.624552", \ "0.173342, 0.233013, 0.26019, 0.300851, 0.366066, 0.473488, 0.652156", \ @@ -28641,8 +28740,8 @@ library (sg13g2_stdcell_fast_1p32V_m40C) { index_1 ("0.0186, 0.0966, 0.174, 0.3294, 0.6408, 1.263, 2.5074"); index_2 ("0.001, 0.0234, 0.039, 0.0648, 0.108, 0.18, 0.3"); values ( \ - "0.0209155, 0.0703673, 0.0986241, 0.147625, 0.233835, 0.381405, 0.629855", \ - "0.0209655, 0.0703876, 0.0986251, 0.147626, 0.233845, 0.381689, 0.629896", \ + "0.0209167, 0.0703673, 0.0986061, 0.147625, 0.233835, 0.381406, 0.629856", \ + "0.0209655, 0.0703876, 0.0986071, 0.147626, 0.233845, 0.381689, 0.629896", \ "0.0210528, 0.0704166, 0.0986785, 0.147627, 0.233846, 0.38169, 0.631801", \ "0.0213751, 0.0706114, 0.0987239, 0.147628, 0.233847, 0.381691, 0.631802", \ "0.0222891, 0.0709358, 0.0989668, 0.147847, 0.233873, 0.381692, 0.631803", \ @@ -28653,32 +28752,33 @@ library (sg13g2_stdcell_fast_1p32V_m40C) { } timing () { related_pin : "RESET_B"; + sdf_edges : start_edge; timing_sense : negative_unate; timing_type : preset; cell_rise (TIMING_DELAY_7x7ds1) { index_1 ("0.0186, 0.0966, 0.174, 0.3294, 0.6408, 1.263, 2.5074"); index_2 ("0.001, 0.0234, 0.039, 0.0648, 0.108, 0.18, 0.3"); values ( \ - "0.135714, 0.189585, 0.218394, 0.264363, 0.340744, 0.467891, 0.679353", \ - "0.173308, 0.227141, 0.255974, 0.301972, 0.378371, 0.50541, 0.717086", \ - "0.200873, 0.254704, 0.283503, 0.329583, 0.405907, 0.532979, 0.744559", \ - "0.24229, 0.296267, 0.325097, 0.371065, 0.447486, 0.574458, 0.78599", \ - "0.301071, 0.355321, 0.384126, 0.430082, 0.506519, 0.633561, 0.84503", \ - "0.382336, 0.436999, 0.465839, 0.511885, 0.588303, 0.71531, 0.926908", \ - "0.494264, 0.549445, 0.578283, 0.624425, 0.700811, 0.827894, 1.03963" \ + "0.135754, 0.189581, 0.218394, 0.264368, 0.340882, 0.467894, 0.679327", \ + "0.173315, 0.227146, 0.255979, 0.301961, 0.378428, 0.505418, 0.717121", \ + "0.200816, 0.254658, 0.283459, 0.329545, 0.405869, 0.532949, 0.744381", \ + "0.24246, 0.29644, 0.325299, 0.37135, 0.447663, 0.574697, 0.786205", \ + "0.300935, 0.355161, 0.384014, 0.430045, 0.506389, 0.633364, 0.844864", \ + "0.382267, 0.436912, 0.465755, 0.511801, 0.588216, 0.715225, 0.926825", \ + "0.494134, 0.549661, 0.578551, 0.624635, 0.700966, 0.828129, 1.03973" \ ); } rise_transition (TIMING_DELAY_7x7ds1) { index_1 ("0.0186, 0.0966, 0.174, 0.3294, 0.6408, 1.263, 2.5074"); index_2 ("0.001, 0.0234, 0.039, 0.0648, 0.108, 0.18, 0.3"); values ( \ - "0.0177891, 0.0730248, 0.110691, 0.175433, 0.286342, 0.472255, 0.782548", \ - "0.0178501, 0.0730258, 0.110712, 0.175434, 0.286361, 0.47246, 0.782639", \ - "0.0179419, 0.0730395, 0.110713, 0.175435, 0.286362, 0.472461, 0.782923", \ - "0.0182491, 0.073152, 0.110751, 0.175436, 0.286363, 0.472462, 0.782924", \ - "0.018798, 0.0733832, 0.110876, 0.175437, 0.286364, 0.472463, 0.782925", \ - "0.019678, 0.073729, 0.111063, 0.175572, 0.286365, 0.472464, 0.782926", \ - "0.020947, 0.074338, 0.11137, 0.17579, 0.286386, 0.472465, 0.782927" \ + "0.0178379, 0.0730214, 0.110691, 0.175408, 0.286309, 0.472255, 0.782568", \ + "0.0178497, 0.0730224, 0.110712, 0.175446, 0.286497, 0.47246, 0.782646", \ + "0.0179137, 0.0730374, 0.110713, 0.175447, 0.286498, 0.472461, 0.783929", \ + "0.0182674, 0.0731279, 0.110752, 0.175448, 0.286499, 0.472462, 0.78393", \ + "0.0187964, 0.0733807, 0.110878, 0.175477, 0.2865, 0.472463, 0.783931", \ + "0.019681, 0.073729, 0.11103, 0.175572, 0.286501, 0.472464, 0.783932", \ + "0.020921, 0.07435, 0.111447, 0.175795, 0.286502, 0.472465, 0.783933" \ ); } } @@ -28689,11 +28789,11 @@ library (sg13g2_stdcell_fast_1p32V_m40C) { index_1 ("0.0186, 0.0966, 0.174, 0.3294, 0.6408, 1.263, 2.5074"); index_2 ("0.001, 0.0234, 0.039, 0.0648, 0.108, 0.18, 0.3"); values ( \ - "0.0380717, 0.058418, 0.0721224, 0.0946355, 0.132154, 0.194594, 0.298639", \ + "0.0380733, 0.0584182, 0.0721224, 0.0946354, 0.132155, 0.194594, 0.298639", \ "0.0380785, 0.0584367, 0.0722212, 0.0946507, 0.133265, 0.194619, 0.298666", \ - "0.0388605, 0.0592317, 0.07287, 0.0954588, 0.133235, 0.195292, 0.299411", \ - "0.0404203, 0.0607968, 0.0745552, 0.0970908, 0.134483, 0.19736, 0.300824", \ - "0.043912, 0.0642036, 0.0779734, 0.100532, 0.138217, 0.200627, 0.304925", \ + "0.0388595, 0.0592317, 0.07287, 0.0954588, 0.133235, 0.195292, 0.299411", \ + "0.0404203, 0.0607968, 0.0745551, 0.0970908, 0.134483, 0.19736, 0.300824", \ + "0.043912, 0.0642036, 0.0779734, 0.100532, 0.138272, 0.200722, 0.304865", \ "0.0515674, 0.0718203, 0.0855882, 0.108076, 0.145894, 0.208594, 0.312957", \ "0.0678291, 0.0880174, 0.10163, 0.124127, 0.161938, 0.224527, 0.328764" \ ); @@ -28702,7 +28802,7 @@ library (sg13g2_stdcell_fast_1p32V_m40C) { index_1 ("0.0186, 0.0966, 0.174, 0.3294, 0.6408, 1.263, 2.5074"); index_2 ("0.001, 0.0234, 0.039, 0.0648, 0.108, 0.18, 0.3"); values ( \ - "0.0377633, 0.0579058, 0.0715427, 0.0939538, 0.131342, 0.193469, 0.296997", \ + "0.0377551, 0.0579058, 0.0715327, 0.0939538, 0.131342, 0.193469, 0.296996", \ "0.0375302, 0.0576557, 0.0713722, 0.094248, 0.131148, 0.19337, 0.296854", \ "0.0381614, 0.0582982, 0.0718796, 0.0942803, 0.132313, 0.194103, 0.298147", \ "0.039594, 0.0596235, 0.0733656, 0.0958792, 0.133034, 0.195699, 0.300193", \ @@ -28718,11 +28818,11 @@ library (sg13g2_stdcell_fast_1p32V_m40C) { index_1 ("0.0186, 0.0966, 0.174, 0.3294, 0.6408, 1.263, 2.5074"); index_2 ("0.001, 0.0234, 0.039, 0.0648, 0.108, 0.18, 0.3"); values ( \ - "0.0380717, 0.058418, 0.0721224, 0.0946355, 0.132154, 0.194594, 0.298639", \ + "0.0380733, 0.0584182, 0.0721224, 0.0946354, 0.132155, 0.194594, 0.298639", \ "0.0380785, 0.0584367, 0.0722212, 0.0946507, 0.133265, 0.194619, 0.298666", \ - "0.0388605, 0.0592317, 0.07287, 0.0954588, 0.133235, 0.195292, 0.299411", \ - "0.0404203, 0.0607968, 0.0745552, 0.0970908, 0.134483, 0.19736, 0.300824", \ - "0.043912, 0.0642036, 0.0779734, 0.100532, 0.138217, 0.200627, 0.304925", \ + "0.0388595, 0.0592317, 0.07287, 0.0954588, 0.133235, 0.195292, 0.299411", \ + "0.0404203, 0.0607968, 0.0745551, 0.0970908, 0.134483, 0.19736, 0.300824", \ + "0.043912, 0.0642036, 0.0779734, 0.100532, 0.138272, 0.200722, 0.304865", \ "0.0515674, 0.0718203, 0.0855882, 0.108076, 0.145894, 0.208594, 0.312957", \ "0.0678291, 0.0880174, 0.10163, 0.124127, 0.161938, 0.224527, 0.328764" \ ); @@ -28731,7 +28831,7 @@ library (sg13g2_stdcell_fast_1p32V_m40C) { index_1 ("0.0186, 0.0966, 0.174, 0.3294, 0.6408, 1.263, 2.5074"); index_2 ("0.001, 0.0234, 0.039, 0.0648, 0.108, 0.18, 0.3"); values ( \ - "0.0377633, 0.0579058, 0.0715427, 0.0939538, 0.131342, 0.193469, 0.296997", \ + "0.0377551, 0.0579058, 0.0715327, 0.0939538, 0.131342, 0.193469, 0.296996", \ "0.0375302, 0.0576557, 0.0713722, 0.094248, 0.131148, 0.19337, 0.296854", \ "0.0381614, 0.0582982, 0.0718796, 0.0942803, 0.132313, 0.194103, 0.298147", \ "0.039594, 0.0596235, 0.0733656, 0.0958792, 0.133034, 0.195699, 0.300193", \ @@ -28747,13 +28847,13 @@ library (sg13g2_stdcell_fast_1p32V_m40C) { index_1 ("0.0186, 0.0966, 0.174, 0.3294, 0.6408, 1.263, 2.5074"); index_2 ("0.001, 0.0234, 0.039, 0.0648, 0.108, 0.18, 0.3"); values ( \ - "0.0457957, 0.066121, 0.0798543, 0.102347, 0.139869, 0.202313, 0.30625", \ - "0.0454436, 0.065813, 0.0796681, 0.102008, 0.139549, 0.202073, 0.30597", \ - "0.0458888, 0.0660992, 0.0798217, 0.102505, 0.139999, 0.20238, 0.306459", \ - "0.0474678, 0.0677012, 0.0814549, 0.103901, 0.141412, 0.204633, 0.308407", \ - "0.0512324, 0.0714141, 0.0851788, 0.107739, 0.145419, 0.207658, 0.312684", \ - "0.0594401, 0.0794504, 0.0931059, 0.115777, 0.153453, 0.216262, 0.320276", \ - "0.0756587, 0.0954796, 0.109101, 0.13173, 0.169216, 0.232274, 0.336735" \ + "0.0394906, 0.0598011, 0.073547, 0.0960373, 0.133594, 0.195994, 0.299825", \ + "0.0390869, 0.0594552, 0.0733084, 0.0956391, 0.133268, 0.195715, 0.299636", \ + "0.0395614, 0.0597706, 0.0734782, 0.0961434, 0.133679, 0.195954, 0.300646", \ + "0.0410379, 0.0612955, 0.0750356, 0.0974498, 0.135028, 0.198065, 0.301626", \ + "0.0448562, 0.0650306, 0.0788108, 0.10136, 0.139075, 0.201091, 0.306412", \ + "0.0528929, 0.0729138, 0.0865482, 0.109235, 0.146956, 0.209768, 0.313706", \ + "0.0691497, 0.0889635, 0.10261, 0.125252, 0.162817, 0.225767, 0.330158" \ ); } fall_power (scalar) { @@ -28767,11 +28867,11 @@ library (sg13g2_stdcell_fast_1p32V_m40C) { clock : true; direction : input; max_transition : 2.5074; - capacitance : 0.00316763; - rise_capacitance : 0.00319929; - rise_capacitance_range (0.00319929, 0.00319929); + capacitance : 0.00316764; + rise_capacitance : 0.0031993; + rise_capacitance_range (0.00289738, 0.00344005); fall_capacitance : 0.00312693; - fall_capacitance_range (0.00312693, 0.00312693); + fall_capacitance_range (0.00284827, 0.00339291); timing () { related_pin : "CLK"; timing_type : min_pulse_width; @@ -28787,13 +28887,13 @@ library (sg13g2_stdcell_fast_1p32V_m40C) { rise_power (passive_POWER_7x1ds1) { index_1 ("0.0186, 0.0966, 0.174, 0.3294, 0.6408, 1.263, 2.5074"); values ( \ - "0.0132326, 0.0131097, 0.0137242, 0.0151713, 0.0184227, 0.0258007, 0.0418117" \ + "0.0132179, 0.0131097, 0.0137242, 0.0151713, 0.0184227, 0.0258007, 0.0418117" \ ); } fall_power (passive_POWER_7x1ds1) { index_1 ("0.0186, 0.0966, 0.174, 0.3294, 0.6408, 1.263, 2.5074"); values ( \ - "0.0128749, 0.0129251, 0.0134874, 0.0150808, 0.0183474, 0.0256759, 0.041378" \ + "0.0128749, 0.0129251, 0.0134874, 0.0150808, 0.0183474, 0.025676, 0.041378" \ ); } } @@ -28807,7 +28907,7 @@ library (sg13g2_stdcell_fast_1p32V_m40C) { fall_power (passive_POWER_7x1ds1) { index_1 ("0.0186, 0.0966, 0.174, 0.3294, 0.6408, 1.263, 2.5074"); values ( \ - "0.0254574, 0.0253673, 0.025994, 0.0276101, 0.0309388, 0.0386048, 0.0548382" \ + "0.025458, 0.0253673, 0.025994, 0.0276101, 0.0309388, 0.0386048, 0.0548382" \ ); } } @@ -28845,7 +28945,7 @@ library (sg13g2_stdcell_fast_1p32V_m40C) { rise_power (passive_POWER_7x1ds1) { index_1 ("0.0186, 0.0966, 0.174, 0.3294, 0.6408, 1.263, 2.5074"); values ( \ - "0.0132211, 0.0131096, 0.0137247, 0.0151714, 0.0184228, 0.0258009, 0.0418119" \ + "0.0132223, 0.0131096, 0.0137247, 0.0151714, 0.0184228, 0.0258009, 0.0418119" \ ); } fall_power (passive_POWER_7x1ds1) { @@ -28860,7 +28960,7 @@ library (sg13g2_stdcell_fast_1p32V_m40C) { rise_power (passive_POWER_7x1ds1) { index_1 ("0.0186, 0.0966, 0.174, 0.3294, 0.6408, 1.263, 2.5074"); values ( \ - "0.0125202, 0.0124133, 0.0130263, 0.0143801, 0.0176755, 0.0250202, 0.0408875" \ + "0.0125202, 0.0124132, 0.0130263, 0.0143801, 0.0176755, 0.0250202, 0.0408874" \ ); } fall_power (passive_POWER_7x1ds1) { @@ -28875,13 +28975,13 @@ library (sg13g2_stdcell_fast_1p32V_m40C) { rise_power (passive_POWER_7x1ds1) { index_1 ("0.0186, 0.0966, 0.174, 0.3294, 0.6408, 1.263, 2.5074"); values ( \ - "0.0129518, 0.012847, 0.0134829, 0.0148417, 0.0181441, 0.0255036, 0.0414506" \ + "0.0129511, 0.012847, 0.0134829, 0.0148417, 0.0181441, 0.0255036, 0.0414506" \ ); } fall_power (passive_POWER_7x1ds1) { index_1 ("0.0186, 0.0966, 0.174, 0.3294, 0.6408, 1.263, 2.5074"); values ( \ - "0.0131373, 0.013197, 0.0137285, 0.0153334, 0.0185979, 0.0259543, 0.0416509" \ + "0.0131374, 0.013197, 0.0137285, 0.0153334, 0.0185979, 0.0259543, 0.0416509" \ ); } } @@ -28889,13 +28989,13 @@ library (sg13g2_stdcell_fast_1p32V_m40C) { rise_power (passive_POWER_7x1ds1) { index_1 ("0.0186, 0.0966, 0.174, 0.3294, 0.6408, 1.263, 2.5074"); values ( \ - "0.0129518, 0.012847, 0.0134829, 0.0148417, 0.0181441, 0.0255036, 0.0414506" \ + "0.0129511, 0.012847, 0.0134829, 0.0148417, 0.0181441, 0.0255036, 0.0414506" \ ); } fall_power (passive_POWER_7x1ds1) { index_1 ("0.0186, 0.0966, 0.174, 0.3294, 0.6408, 1.263, 2.5074"); values ( \ - "0.0131373, 0.013197, 0.0137285, 0.0153334, 0.0185979, 0.0259543, 0.0416509" \ + "0.0131374, 0.013197, 0.0137285, 0.0153334, 0.0185979, 0.0259543, 0.0416509" \ ); } } @@ -28906,11 +29006,12 @@ library (sg13g2_stdcell_fast_1p32V_m40C) { max_transition : 2.5074; capacitance : 0.00297966; rise_capacitance : 0.00301494; - rise_capacitance_range (0.00301494, 0.00301494); + rise_capacitance_range (0.00261109, 0.00331679); fall_capacitance : 0.00294438; - fall_capacitance_range (0.00294438, 0.00294438); + fall_capacitance_range (0.00258212, 0.00317094); timing () { related_pin : "CLK"; + sdf_edges : both_edges; timing_type : hold_rising; rise_constraint (CONSTRAINT_4x4) { index_1 ("0.0186, 0.51636, 1.263, 2.5074"); @@ -28935,6 +29036,7 @@ library (sg13g2_stdcell_fast_1p32V_m40C) { } timing () { related_pin : "CLK"; + sdf_edges : both_edges; timing_type : setup_rising; rise_constraint (CONSTRAINT_4x4) { index_1 ("0.0186, 0.51636, 1.263, 2.5074"); @@ -28962,7 +29064,7 @@ library (sg13g2_stdcell_fast_1p32V_m40C) { rise_power (passive_POWER_7x1ds1) { index_1 ("0.0186, 0.0966, 0.174, 0.3294, 0.6408, 1.263, 2.5074"); values ( \ - "0.0253869, 0.0252374, 0.0255432, 0.0266358, 0.0293237, 0.0352084, 0.0480478" \ + "0.025387, 0.0252374, 0.0255432, 0.0266358, 0.0293237, 0.0352084, 0.0480478" \ ); } fall_power (passive_POWER_7x1ds1) { @@ -28976,7 +29078,7 @@ library (sg13g2_stdcell_fast_1p32V_m40C) { rise_power (passive_POWER_7x1ds1) { index_1 ("0.0186, 0.0966, 0.174, 0.3294, 0.6408, 1.263, 2.5074"); values ( \ - "0.0253869, 0.0252374, 0.0255432, 0.0266358, 0.0293237, 0.0352084, 0.0480478" \ + "0.025387, 0.0252374, 0.0255432, 0.0266358, 0.0293237, 0.0352084, 0.0480478" \ ); } fall_power (passive_POWER_7x1ds1) { @@ -28990,13 +29092,14 @@ library (sg13g2_stdcell_fast_1p32V_m40C) { pin (RESET_B) { direction : input; max_transition : 2.5074; - capacitance : 0.00541324; - rise_capacitance : 0.00541324; - rise_capacitance_range (0.00541324, 0.00541324); - fall_capacitance : 0.00541324; - fall_capacitance_range (0.00541324, 0.00541324); + capacitance : 0.00540968; + rise_capacitance : 0.00540968; + rise_capacitance_range (0.00540968, 0.00540968); + fall_capacitance : 0.00540968; + fall_capacitance_range (0.00501708, 0.00565032); timing () { related_pin : "CLK"; + sdf_edges : both_edges; timing_type : recovery_rising; rise_constraint (CONSTRAINT_4x4) { index_1 ("0.0186, 0.51636, 1.263, 2.5074"); @@ -29011,6 +29114,7 @@ library (sg13g2_stdcell_fast_1p32V_m40C) { } timing () { related_pin : "CLK"; + sdf_edges : both_edges; timing_type : removal_rising; rise_constraint (CONSTRAINT_4x4) { index_1 ("0.0186, 0.51636, 1.263, 2.5074"); @@ -29040,11 +29144,12 @@ library (sg13g2_stdcell_fast_1p32V_m40C) { max_transition : 2.5074; capacitance : 0.0030948; rise_capacitance : 0.0031187; - rise_capacitance_range (0.0031187, 0.0031187); + rise_capacitance_range (0.00271865, 0.00341988); fall_capacitance : 0.00304701; - fall_capacitance_range (0.00304701, 0.00304701); + fall_capacitance_range (0.00268876, 0.00327438); timing () { related_pin : "CLK"; + sdf_edges : both_edges; timing_type : hold_rising; rise_constraint (CONSTRAINT_4x4) { index_1 ("0.0186, 0.51636, 1.263, 2.5074"); @@ -29069,6 +29174,7 @@ library (sg13g2_stdcell_fast_1p32V_m40C) { } timing () { related_pin : "CLK"; + sdf_edges : both_edges; timing_type : setup_rising; rise_constraint (CONSTRAINT_4x4) { index_1 ("0.0186, 0.51636, 1.263, 2.5074"); @@ -29127,11 +29233,12 @@ library (sg13g2_stdcell_fast_1p32V_m40C) { max_transition : 2.5074; capacitance : 0.00529129; rise_capacitance : 0.00558994; - rise_capacitance_range (0.00558994, 0.00558994); + rise_capacitance_range (0.00472643, 0.00631037); fall_capacitance : 0.00499264; - fall_capacitance_range (0.00499264, 0.00499264); + fall_capacitance_range (0.00471737, 0.00553795); timing () { related_pin : "CLK"; + sdf_edges : both_edges; timing_type : hold_rising; rise_constraint (CONSTRAINT_4x4) { index_1 ("0.0186, 0.51636, 1.263, 2.5074"); @@ -29156,6 +29263,7 @@ library (sg13g2_stdcell_fast_1p32V_m40C) { } timing () { related_pin : "CLK"; + sdf_edges : both_edges; timing_type : setup_rising; rise_constraint (CONSTRAINT_4x4) { index_1 ("0.0186, 0.51636, 1.263, 2.5074"); @@ -29224,9 +29332,9 @@ library (sg13g2_stdcell_fast_1p32V_m40C) { } } ff (IQ,IQN) { - clear : "RESET_B'"; + clear : "!RESET_B"; clocked_on : "CLK"; - next_state : "(SCE*SCD)+(SCE'*D)"; + next_state : "(SCE*SCD)+(!SCE*D)"; } test_cell () { pin (Q) { @@ -29257,7 +29365,7 @@ library (sg13g2_stdcell_fast_1p32V_m40C) { signal_type : test_scan_enable; } ff (IQ,IQN) { - clear : "RESET_B'"; + clear : "!RESET_B"; clocked_on : "CLK"; next_state : "D"; } @@ -29288,7 +29396,7 @@ library (sg13g2_stdcell_fast_1p32V_m40C) { when : "CLK&!D&RESET_B&!SCD&!SCE&Q&!Q_N"; } leakage_power () { - value : 1954.35; + value : 1954.36; when : "!CLK&D&RESET_B&!SCD&!SCE&!Q&Q_N"; } leakage_power () { @@ -29332,7 +29440,7 @@ library (sg13g2_stdcell_fast_1p32V_m40C) { when : "CLK&!D&RESET_B&SCD&SCE&!Q&Q_N"; } leakage_power () { - value : 2073.51; + value : 2073.5; when : "CLK&!D&RESET_B&SCD&SCE&Q&!Q_N"; } pin (Q) { @@ -29343,6 +29451,7 @@ library (sg13g2_stdcell_fast_1p32V_m40C) { timing () { related_pin : "CLK"; sdf_cond : "SCE == 1'b1"; + sdf_edges : start_edge; timing_sense : non_unate; timing_type : rising_edge; when : "SCE"; @@ -29350,12 +29459,12 @@ library (sg13g2_stdcell_fast_1p32V_m40C) { index_1 ("0.0186, 0.0966, 0.174, 0.3294, 0.6408, 1.263, 2.5074"); index_2 ("0.001, 0.0468, 0.078, 0.1296, 0.216, 0.36, 0.6"); values ( \ - "0.162381, 0.198155, 0.225106, 0.270642, 0.347371, 0.475565, 0.689686", \ + "0.162381, 0.198155, 0.225106, 0.270642, 0.347371, 0.475602, 0.689686", \ "0.192116, 0.227818, 0.25474, 0.30031, 0.377082, 0.50532, 0.719516", \ "0.211853, 0.247619, 0.274524, 0.320026, 0.396769, 0.525065, 0.738968", \ "0.239222, 0.274974, 0.301924, 0.347372, 0.424148, 0.552382, 0.766295", \ - "0.278441, 0.313716, 0.340673, 0.386524, 0.463262, 0.591105, 0.80501", \ - "0.334424, 0.36972, 0.396566, 0.441966, 0.51873, 0.64686, 0.860886", \ + "0.278441, 0.313716, 0.340673, 0.386524, 0.46284, 0.591519, 0.805455", \ + "0.334453, 0.36972, 0.396566, 0.441966, 0.51873, 0.64686, 0.860886", \ "0.416899, 0.450611, 0.47724, 0.522553, 0.599202, 0.727387, 0.941348" \ ); } @@ -29363,7 +29472,7 @@ library (sg13g2_stdcell_fast_1p32V_m40C) { index_1 ("0.0186, 0.0966, 0.174, 0.3294, 0.6408, 1.263, 2.5074"); index_2 ("0.001, 0.0468, 0.078, 0.1296, 0.216, 0.36, 0.6"); values ( \ - "0.0157121, 0.0689396, 0.108755, 0.175783, 0.288426, 0.476382, 0.789906", \ + "0.0157121, 0.0689396, 0.108755, 0.175783, 0.288426, 0.476466, 0.789906", \ "0.0157341, 0.0689406, 0.108782, 0.175796, 0.288485, 0.476622, 0.789907", \ "0.0157345, 0.0689578, 0.108783, 0.175797, 0.288489, 0.476623, 0.790595", \ "0.0157605, 0.0689588, 0.108784, 0.175821, 0.28849, 0.476624, 0.790596", \ @@ -29376,7 +29485,7 @@ library (sg13g2_stdcell_fast_1p32V_m40C) { index_1 ("0.0186, 0.0966, 0.174, 0.3294, 0.6408, 1.263, 2.5074"); index_2 ("0.001, 0.0468, 0.078, 0.1296, 0.216, 0.36, 0.6"); values ( \ - "0.144765, 0.179553, 0.202643, 0.241097, 0.305419, 0.412885, 0.59205", \ + "0.144765, 0.179553, 0.202643, 0.241095, 0.305414, 0.412885, 0.59205", \ "0.174025, 0.208778, 0.231972, 0.27035, 0.334755, 0.442224, 0.621488", \ "0.193242, 0.22797, 0.251093, 0.289584, 0.353907, 0.461338, 0.640495", \ "0.218859, 0.253646, 0.276826, 0.315172, 0.37961, 0.486995, 0.666081", \ @@ -29389,30 +29498,31 @@ library (sg13g2_stdcell_fast_1p32V_m40C) { index_1 ("0.0186, 0.0966, 0.174, 0.3294, 0.6408, 1.263, 2.5074"); index_2 ("0.001, 0.0468, 0.078, 0.1296, 0.216, 0.36, 0.6"); values ( \ - "0.0134501, 0.0573406, 0.0887706, 0.141916, 0.231635, 0.381494, 0.631156", \ - "0.0134511, 0.0573416, 0.0887716, 0.141941, 0.231667, 0.381536, 0.631507", \ - "0.0134521, 0.0573426, 0.0887726, 0.141942, 0.231668, 0.381537, 0.631508", \ - "0.0134531, 0.0573585, 0.0887736, 0.141943, 0.231669, 0.381538, 0.631509", \ - "0.0134541, 0.0573595, 0.0887746, 0.141944, 0.23167, 0.381539, 0.63151", \ - "0.0134551, 0.0573605, 0.0887756, 0.141945, 0.231671, 0.38154, 0.631511", \ - "0.0134561, 0.0573615, 0.0887766, 0.141946, 0.231672, 0.381628, 0.631512" \ + "0.0134502, 0.0573405, 0.0887716, 0.141917, 0.231634, 0.381494, 0.631157", \ + "0.0134512, 0.0573415, 0.0887726, 0.141941, 0.231667, 0.381536, 0.631507", \ + "0.0134522, 0.0573425, 0.0887736, 0.141942, 0.231668, 0.381537, 0.631508", \ + "0.0134532, 0.0573585, 0.0887746, 0.141943, 0.231669, 0.381538, 0.631509", \ + "0.0134542, 0.0573595, 0.0887756, 0.141944, 0.23167, 0.381539, 0.63151", \ + "0.0134552, 0.0573605, 0.0887766, 0.141945, 0.231671, 0.38154, 0.631511", \ + "0.0134562, 0.0573615, 0.0887776, 0.141946, 0.231672, 0.381628, 0.631512" \ ); } } timing () { related_pin : "CLK"; + sdf_edges : start_edge; timing_sense : non_unate; timing_type : rising_edge; cell_rise (TIMING_DELAY_7x7ds1) { index_1 ("0.0186, 0.0966, 0.174, 0.3294, 0.6408, 1.263, 2.5074"); index_2 ("0.001, 0.0468, 0.078, 0.1296, 0.216, 0.36, 0.6"); values ( \ - "0.162381, 0.198155, 0.225106, 0.270642, 0.347371, 0.475565, 0.689686", \ + "0.162381, 0.198155, 0.225106, 0.270642, 0.347371, 0.475602, 0.689686", \ "0.192116, 0.227818, 0.25474, 0.30031, 0.377082, 0.50532, 0.719516", \ "0.211853, 0.247619, 0.274524, 0.320026, 0.396769, 0.525065, 0.738968", \ "0.239222, 0.274974, 0.301924, 0.347372, 0.424148, 0.552382, 0.766295", \ - "0.278441, 0.313716, 0.340673, 0.386524, 0.463262, 0.591105, 0.80501", \ - "0.334424, 0.36972, 0.396566, 0.441966, 0.51873, 0.64686, 0.860886", \ + "0.278441, 0.313716, 0.340673, 0.386524, 0.46284, 0.591519, 0.805455", \ + "0.334453, 0.36972, 0.396566, 0.441966, 0.51873, 0.64686, 0.860886", \ "0.416899, 0.450611, 0.47724, 0.522553, 0.599202, 0.727387, 0.941348" \ ); } @@ -29420,7 +29530,7 @@ library (sg13g2_stdcell_fast_1p32V_m40C) { index_1 ("0.0186, 0.0966, 0.174, 0.3294, 0.6408, 1.263, 2.5074"); index_2 ("0.001, 0.0468, 0.078, 0.1296, 0.216, 0.36, 0.6"); values ( \ - "0.0157121, 0.0689396, 0.108755, 0.175783, 0.288426, 0.476382, 0.789906", \ + "0.0157121, 0.0689396, 0.108755, 0.175783, 0.288426, 0.476466, 0.789906", \ "0.0157341, 0.0689406, 0.108782, 0.175796, 0.288485, 0.476622, 0.789907", \ "0.0157345, 0.0689578, 0.108783, 0.175797, 0.288489, 0.476623, 0.790595", \ "0.0157605, 0.0689588, 0.108784, 0.175821, 0.28849, 0.476624, 0.790596", \ @@ -29433,7 +29543,7 @@ library (sg13g2_stdcell_fast_1p32V_m40C) { index_1 ("0.0186, 0.0966, 0.174, 0.3294, 0.6408, 1.263, 2.5074"); index_2 ("0.001, 0.0468, 0.078, 0.1296, 0.216, 0.36, 0.6"); values ( \ - "0.144765, 0.179553, 0.202643, 0.241097, 0.305419, 0.412885, 0.59205", \ + "0.144765, 0.179553, 0.202643, 0.241095, 0.305414, 0.412885, 0.59205", \ "0.174025, 0.208778, 0.231972, 0.27035, 0.334755, 0.442224, 0.621488", \ "0.193242, 0.22797, 0.251093, 0.289584, 0.353907, 0.461338, 0.640495", \ "0.218859, 0.253646, 0.276826, 0.315172, 0.37961, 0.486995, 0.666081", \ @@ -29446,44 +29556,45 @@ library (sg13g2_stdcell_fast_1p32V_m40C) { index_1 ("0.0186, 0.0966, 0.174, 0.3294, 0.6408, 1.263, 2.5074"); index_2 ("0.001, 0.0468, 0.078, 0.1296, 0.216, 0.36, 0.6"); values ( \ - "0.0134501, 0.0573406, 0.0887706, 0.141916, 0.231635, 0.381494, 0.631156", \ - "0.0134511, 0.0573416, 0.0887716, 0.141941, 0.231667, 0.381536, 0.631507", \ - "0.0134521, 0.0573426, 0.0887726, 0.141942, 0.231668, 0.381537, 0.631508", \ - "0.0134531, 0.0573585, 0.0887736, 0.141943, 0.231669, 0.381538, 0.631509", \ - "0.0134541, 0.0573595, 0.0887746, 0.141944, 0.23167, 0.381539, 0.63151", \ - "0.0134551, 0.0573605, 0.0887756, 0.141945, 0.231671, 0.38154, 0.631511", \ - "0.0134561, 0.0573615, 0.0887766, 0.141946, 0.231672, 0.381628, 0.631512" \ + "0.0134502, 0.0573405, 0.0887716, 0.141917, 0.231634, 0.381494, 0.631157", \ + "0.0134512, 0.0573415, 0.0887726, 0.141941, 0.231667, 0.381536, 0.631507", \ + "0.0134522, 0.0573425, 0.0887736, 0.141942, 0.231668, 0.381537, 0.631508", \ + "0.0134532, 0.0573585, 0.0887746, 0.141943, 0.231669, 0.381538, 0.631509", \ + "0.0134542, 0.0573595, 0.0887756, 0.141944, 0.23167, 0.381539, 0.63151", \ + "0.0134552, 0.0573605, 0.0887766, 0.141945, 0.231671, 0.38154, 0.631511", \ + "0.0134562, 0.0573615, 0.0887776, 0.141946, 0.231672, 0.381628, 0.631512" \ ); } } timing () { related_pin : "RESET_B"; + sdf_edges : start_edge; timing_sense : positive_unate; timing_type : clear; cell_fall (TIMING_DELAY_7x7ds1) { index_1 ("0.0186, 0.0966, 0.174, 0.3294, 0.6408, 1.263, 2.5074"); index_2 ("0.001, 0.0468, 0.078, 0.1296, 0.216, 0.36, 0.6"); values ( \ - "0.18948, 0.224258, 0.247435, 0.285889, 0.350318, 0.457874, 0.63707", \ - "0.227065, 0.261747, 0.284891, 0.323379, 0.387794, 0.495449, 0.674663", \ - "0.25467, 0.289244, 0.312407, 0.350905, 0.415389, 0.522918, 0.702121", \ - "0.29633, 0.331289, 0.354415, 0.392805, 0.457336, 0.564796, 0.743881", \ - "0.355538, 0.390104, 0.413243, 0.451618, 0.516144, 0.623643, 0.802765", \ - "0.437814, 0.472372, 0.495504, 0.533932, 0.598401, 0.705838, 0.885071", \ - "0.551391, 0.585758, 0.608847, 0.646885, 0.711353, 0.818957, 0.998434" \ + "0.189545, 0.224262, 0.247451, 0.285928, 0.350351, 0.457903, 0.637106", \ + "0.227124, 0.261798, 0.284908, 0.323402, 0.387932, 0.495555, 0.674746", \ + "0.254693, 0.289187, 0.312364, 0.350854, 0.415408, 0.522834, 0.702063", \ + "0.296443, 0.331161, 0.354313, 0.392742, 0.457177, 0.564725, 0.743786", \ + "0.355226, 0.389776, 0.412963, 0.451343, 0.515867, 0.623333, 0.802519", \ + "0.437733, 0.471632, 0.494789, 0.533218, 0.597688, 0.705145, 0.884359", \ + "0.550561, 0.58578, 0.608861, 0.647249, 0.711483, 0.819079, 0.99849" \ ); } fall_transition (TIMING_DELAY_7x7ds1) { index_1 ("0.0186, 0.0966, 0.174, 0.3294, 0.6408, 1.263, 2.5074"); index_2 ("0.001, 0.0468, 0.078, 0.1296, 0.216, 0.36, 0.6"); values ( \ - "0.0131984, 0.0572702, 0.0887066, 0.141881, 0.231561, 0.381488, 0.631137", \ - "0.0131994, 0.0572712, 0.0887221, 0.141885, 0.231638, 0.381489, 0.631363", \ - "0.0132001, 0.0572722, 0.0887231, 0.141899, 0.231639, 0.38149, 0.631364", \ - "0.0132011, 0.0572732, 0.0887276, 0.1419, 0.23164, 0.381491, 0.631365", \ - "0.0132727, 0.0572903, 0.0887286, 0.141901, 0.231641, 0.381492, 0.631366", \ - "0.01338, 0.057292, 0.088729, 0.141902, 0.231642, 0.381493, 0.631367", \ - "0.013498, 0.057369, 0.08876, 0.141915, 0.231661, 0.381494, 0.631368" \ + "0.0132096, 0.0572442, 0.0887081, 0.141868, 0.231561, 0.381481, 0.631332", \ + "0.0132106, 0.0572582, 0.0887091, 0.141869, 0.231585, 0.381729, 0.631363", \ + "0.0132116, 0.0572592, 0.0887101, 0.141901, 0.231586, 0.38173, 0.631364", \ + "0.0132126, 0.0572602, 0.0887299, 0.141902, 0.231587, 0.381731, 0.631365", \ + "0.0132716, 0.0572612, 0.0887309, 0.141903, 0.231628, 0.381732, 0.631366", \ + "0.013385, 0.057299, 0.0887319, 0.141904, 0.231634, 0.381733, 0.631367", \ + "0.013479, 0.057368, 0.088774, 0.141905, 0.231661, 0.381734, 0.631368" \ ); } } @@ -29494,12 +29605,12 @@ library (sg13g2_stdcell_fast_1p32V_m40C) { index_1 ("0.0186, 0.0966, 0.174, 0.3294, 0.6408, 1.263, 2.5074"); index_2 ("0.001, 0.0468, 0.078, 0.1296, 0.216, 0.36, 0.6"); values ( \ - "0.0478914, 0.0878397, 0.115308, 0.160389, 0.235502, 0.360486, 0.568899", \ + "0.0478914, 0.0878397, 0.115308, 0.160389, 0.235502, 0.360422, 0.568899", \ "0.047656, 0.0876144, 0.115279, 0.160267, 0.23535, 0.360542, 0.568645", \ "0.0483197, 0.0882136, 0.115579, 0.160857, 0.236094, 0.362113, 0.569721", \ "0.0498179, 0.089621, 0.117181, 0.162287, 0.23736, 0.362894, 0.570881", \ - "0.0533117, 0.0928835, 0.120372, 0.165621, 0.241118, 0.36576, 0.57469", \ - "0.0614036, 0.100417, 0.12799, 0.173057, 0.248482, 0.374165, 0.583155", \ + "0.0533117, 0.0928835, 0.120372, 0.165621, 0.241255, 0.366013, 0.574624", \ + "0.0614214, 0.100417, 0.12799, 0.173057, 0.248482, 0.374165, 0.583155", \ "0.0788783, 0.116803, 0.144114, 0.189311, 0.264925, 0.390574, 0.59923" \ ); } @@ -29507,13 +29618,13 @@ library (sg13g2_stdcell_fast_1p32V_m40C) { index_1 ("0.0186, 0.0966, 0.174, 0.3294, 0.6408, 1.263, 2.5074"); index_2 ("0.001, 0.0468, 0.078, 0.1296, 0.216, 0.36, 0.6"); values ( \ - "0.0493128, 0.0901614, 0.117443, 0.162313, 0.237, 0.361356, 0.568399", \ - "0.0493169, 0.0901299, 0.117627, 0.162938, 0.237039, 0.361358, 0.568554", \ - "0.0501685, 0.0909816, 0.118171, 0.163073, 0.239339, 0.361888, 0.56907", \ + "0.049313, 0.0901614, 0.117427, 0.162313, 0.236995, 0.361356, 0.568065", \ + "0.0493169, 0.0901162, 0.117627, 0.162938, 0.237001, 0.361358, 0.568554", \ + "0.0501645, 0.0909787, 0.118171, 0.163073, 0.239339, 0.361888, 0.572922", \ "0.0515571, 0.0925366, 0.120031, 0.165028, 0.239136, 0.364842, 0.571201", \ "0.0550746, 0.0958501, 0.123458, 0.168172, 0.244143, 0.368549, 0.574634", \ - "0.0627557, 0.103424, 0.130937, 0.175972, 0.251389, 0.376842, 0.586148", \ - "0.079021, 0.119564, 0.146764, 0.191471, 0.266907, 0.392482, 0.60128" \ + "0.0627557, 0.103424, 0.130937, 0.176125, 0.251389, 0.376842, 0.586149", \ + "0.079021, 0.119564, 0.146764, 0.191471, 0.266907, 0.392482, 0.601269" \ ); } } @@ -29523,12 +29634,12 @@ library (sg13g2_stdcell_fast_1p32V_m40C) { index_1 ("0.0186, 0.0966, 0.174, 0.3294, 0.6408, 1.263, 2.5074"); index_2 ("0.001, 0.0468, 0.078, 0.1296, 0.216, 0.36, 0.6"); values ( \ - "0.0478914, 0.0878397, 0.115308, 0.160389, 0.235502, 0.360486, 0.568899", \ + "0.0478914, 0.0878397, 0.115308, 0.160389, 0.235502, 0.360422, 0.568899", \ "0.047656, 0.0876144, 0.115279, 0.160267, 0.23535, 0.360542, 0.568645", \ "0.0483197, 0.0882136, 0.115579, 0.160857, 0.236094, 0.362113, 0.569721", \ "0.0498179, 0.089621, 0.117181, 0.162287, 0.23736, 0.362894, 0.570881", \ - "0.0533117, 0.0928835, 0.120372, 0.165621, 0.241118, 0.36576, 0.57469", \ - "0.0614036, 0.100417, 0.12799, 0.173057, 0.248482, 0.374165, 0.583155", \ + "0.0533117, 0.0928835, 0.120372, 0.165621, 0.241255, 0.366013, 0.574624", \ + "0.0614214, 0.100417, 0.12799, 0.173057, 0.248482, 0.374165, 0.583155", \ "0.0788783, 0.116803, 0.144114, 0.189311, 0.264925, 0.390574, 0.59923" \ ); } @@ -29536,13 +29647,13 @@ library (sg13g2_stdcell_fast_1p32V_m40C) { index_1 ("0.0186, 0.0966, 0.174, 0.3294, 0.6408, 1.263, 2.5074"); index_2 ("0.001, 0.0468, 0.078, 0.1296, 0.216, 0.36, 0.6"); values ( \ - "0.0493128, 0.0901614, 0.117443, 0.162313, 0.237, 0.361356, 0.568399", \ - "0.0493169, 0.0901299, 0.117627, 0.162938, 0.237039, 0.361358, 0.568554", \ - "0.0501685, 0.0909816, 0.118171, 0.163073, 0.239339, 0.361888, 0.56907", \ + "0.049313, 0.0901614, 0.117427, 0.162313, 0.236995, 0.361356, 0.568065", \ + "0.0493169, 0.0901162, 0.117627, 0.162938, 0.237001, 0.361358, 0.568554", \ + "0.0501645, 0.0909787, 0.118171, 0.163073, 0.239339, 0.361888, 0.572922", \ "0.0515571, 0.0925366, 0.120031, 0.165028, 0.239136, 0.364842, 0.571201", \ "0.0550746, 0.0958501, 0.123458, 0.168172, 0.244143, 0.368549, 0.574634", \ - "0.0627557, 0.103424, 0.130937, 0.175972, 0.251389, 0.376842, 0.586148", \ - "0.079021, 0.119564, 0.146764, 0.191471, 0.266907, 0.392482, 0.60128" \ + "0.0627557, 0.103424, 0.130937, 0.176125, 0.251389, 0.376842, 0.586149", \ + "0.079021, 0.119564, 0.146764, 0.191471, 0.266907, 0.392482, 0.601269" \ ); } } @@ -29557,13 +29668,13 @@ library (sg13g2_stdcell_fast_1p32V_m40C) { index_1 ("0.0186, 0.0966, 0.174, 0.3294, 0.6408, 1.263, 2.5074"); index_2 ("0.001, 0.0468, 0.078, 0.1296, 0.216, 0.36, 0.6"); values ( \ - "0.0496187, 0.0903107, 0.117617, 0.162415, 0.237138, 0.3615, 0.568326", \ - "0.049216, 0.0900235, 0.117979, 0.162478, 0.236795, 0.361263, 0.568237", \ - "0.0496522, 0.0901799, 0.117484, 0.162817, 0.238417, 0.361669, 0.568549", \ - "0.0512058, 0.0919321, 0.119412, 0.164125, 0.238701, 0.365021, 0.57053", \ - "0.0551155, 0.0954961, 0.12293, 0.16821, 0.243569, 0.367257, 0.575705", \ - "0.0632606, 0.103249, 0.130443, 0.175807, 0.250993, 0.376663, 0.585206", \ - "0.0796153, 0.119198, 0.146395, 0.191492, 0.266459, 0.392067, 0.60128" \ + "0.0608571, 0.101535, 0.128829, 0.173662, 0.248377, 0.372764, 0.57989", \ + "0.0602808, 0.101071, 0.128541, 0.173625, 0.247906, 0.372479, 0.579321", \ + "0.0604688, 0.100984, 0.128307, 0.173588, 0.24922, 0.372391, 0.579339", \ + "0.0614271, 0.102113, 0.129531, 0.174352, 0.248759, 0.37455, 0.579876", \ + "0.0638388, 0.104211, 0.131683, 0.176836, 0.252056, 0.37549, 0.584453", \ + "0.0693541, 0.109383, 0.136595, 0.181949, 0.257187, 0.382901, 0.591641", \ + "0.0798691, 0.119354, 0.146488, 0.19159, 0.26666, 0.392261, 0.601431" \ ); } } @@ -29576,6 +29687,7 @@ library (sg13g2_stdcell_fast_1p32V_m40C) { timing () { related_pin : "CLK"; sdf_cond : "SCE == 1'b1"; + sdf_edges : start_edge; timing_sense : non_unate; timing_type : rising_edge; when : "SCE"; @@ -29583,7 +29695,7 @@ library (sg13g2_stdcell_fast_1p32V_m40C) { index_1 ("0.0186, 0.0966, 0.174, 0.3294, 0.6408, 1.263, 2.5074"); index_2 ("0.001, 0.0468, 0.078, 0.1296, 0.216, 0.36, 0.6"); values ( \ - "0.096376, 0.15833, 0.188534, 0.235343, 0.311943, 0.439247, 0.650965", \ + "0.0964104, 0.15833, 0.188534, 0.235343, 0.311943, 0.439247, 0.650965", \ "0.125626, 0.187582, 0.217762, 0.264515, 0.341195, 0.468474, 0.680211", \ "0.144857, 0.206813, 0.236957, 0.283807, 0.360393, 0.487614, 0.699371", \ "0.170439, 0.232387, 0.262594, 0.309326, 0.386017, 0.513192, 0.724878", \ @@ -29596,13 +29708,13 @@ library (sg13g2_stdcell_fast_1p32V_m40C) { index_1 ("0.0186, 0.0966, 0.174, 0.3294, 0.6408, 1.263, 2.5074"); index_2 ("0.001, 0.0468, 0.078, 0.1296, 0.216, 0.36, 0.6"); values ( \ - "0.0183597, 0.0783834, 0.115677, 0.179113, 0.28889, 0.474533, 0.785386", \ - "0.0183792, 0.0783844, 0.115678, 0.179114, 0.288891, 0.474534, 0.785387", \ - "0.0183802, 0.0783854, 0.115679, 0.179115, 0.288892, 0.474592, 0.787024", \ - "0.0183812, 0.0784242, 0.11568, 0.179116, 0.288893, 0.474593, 0.787025", \ - "0.0183822, 0.0784436, 0.115723, 0.179117, 0.288894, 0.474594, 0.787026", \ - "0.0183832, 0.0784446, 0.115724, 0.179118, 0.288895, 0.474595, 0.787027", \ - "0.0183842, 0.0784456, 0.115725, 0.179119, 0.288896, 0.474596, 0.787028" \ + "0.0183814, 0.0783834, 0.115677, 0.179113, 0.28889, 0.474533, 0.785386", \ + "0.0183824, 0.0783844, 0.115678, 0.179114, 0.288891, 0.474534, 0.785387", \ + "0.0183834, 0.0783854, 0.115679, 0.179115, 0.288892, 0.474592, 0.787024", \ + "0.0183844, 0.0784242, 0.11568, 0.179116, 0.288893, 0.474593, 0.787025", \ + "0.0183854, 0.0784436, 0.115723, 0.179117, 0.288894, 0.474594, 0.787026", \ + "0.0183864, 0.0784446, 0.115724, 0.179118, 0.288895, 0.474595, 0.787027", \ + "0.0183874, 0.0784456, 0.115725, 0.179119, 0.288896, 0.474596, 0.787028" \ ); } cell_fall (TIMING_DELAY_7x7ds1) { @@ -29613,7 +29725,7 @@ library (sg13g2_stdcell_fast_1p32V_m40C) { "0.136435, 0.203842, 0.232909, 0.275085, 0.341259, 0.449177, 0.628311", \ "0.156138, 0.223558, 0.252627, 0.294743, 0.36088, 0.468857, 0.648098", \ "0.183571, 0.250917, 0.280008, 0.322107, 0.388272, 0.496247, 0.67531", \ - "0.222603, 0.289596, 0.318715, 0.361295, 0.427053, 0.535557, 0.714163", \ + "0.222129, 0.290048, 0.319173, 0.361295, 0.427484, 0.535083, 0.714592", \ "0.278444, 0.346554, 0.375754, 0.418011, 0.484242, 0.5923, 0.771346", \ "0.356315, 0.42745, 0.456904, 0.499329, 0.565594, 0.673584, 0.852778" \ ); @@ -29626,7 +29738,7 @@ library (sg13g2_stdcell_fast_1p32V_m40C) { "0.0232843, 0.0776431, 0.106373, 0.15447, 0.239501, 0.386574, 0.634997", \ "0.0233452, 0.0776441, 0.106399, 0.154471, 0.239502, 0.386575, 0.63936", \ "0.0234348, 0.0777541, 0.1064, 0.154484, 0.239503, 0.386576, 0.639361", \ - "0.024013, 0.0779934, 0.106607, 0.154565, 0.239504, 0.386577, 0.639362", \ + "0.0240014, 0.0779979, 0.106608, 0.154565, 0.239504, 0.386577, 0.639362", \ "0.025805, 0.078771, 0.107088, 0.154988, 0.23964, 0.386578, 0.639363", \ "0.030673, 0.081384, 0.108912, 0.155914, 0.240296, 0.386654, 0.639364" \ ); @@ -29634,13 +29746,14 @@ library (sg13g2_stdcell_fast_1p32V_m40C) { } timing () { related_pin : "CLK"; + sdf_edges : start_edge; timing_sense : non_unate; timing_type : rising_edge; cell_rise (TIMING_DELAY_7x7ds1) { index_1 ("0.0186, 0.0966, 0.174, 0.3294, 0.6408, 1.263, 2.5074"); index_2 ("0.001, 0.0468, 0.078, 0.1296, 0.216, 0.36, 0.6"); values ( \ - "0.096376, 0.15833, 0.188534, 0.235343, 0.311943, 0.439247, 0.650965", \ + "0.0964104, 0.15833, 0.188534, 0.235343, 0.311943, 0.439247, 0.650965", \ "0.125626, 0.187582, 0.217762, 0.264515, 0.341195, 0.468474, 0.680211", \ "0.144857, 0.206813, 0.236957, 0.283807, 0.360393, 0.487614, 0.699371", \ "0.170439, 0.232387, 0.262594, 0.309326, 0.386017, 0.513192, 0.724878", \ @@ -29653,13 +29766,13 @@ library (sg13g2_stdcell_fast_1p32V_m40C) { index_1 ("0.0186, 0.0966, 0.174, 0.3294, 0.6408, 1.263, 2.5074"); index_2 ("0.001, 0.0468, 0.078, 0.1296, 0.216, 0.36, 0.6"); values ( \ - "0.0183597, 0.0783834, 0.115677, 0.179113, 0.28889, 0.474533, 0.785386", \ - "0.0183792, 0.0783844, 0.115678, 0.179114, 0.288891, 0.474534, 0.785387", \ - "0.0183802, 0.0783854, 0.115679, 0.179115, 0.288892, 0.474592, 0.787024", \ - "0.0183812, 0.0784242, 0.11568, 0.179116, 0.288893, 0.474593, 0.787025", \ - "0.0183822, 0.0784436, 0.115723, 0.179117, 0.288894, 0.474594, 0.787026", \ - "0.0183832, 0.0784446, 0.115724, 0.179118, 0.288895, 0.474595, 0.787027", \ - "0.0183842, 0.0784456, 0.115725, 0.179119, 0.288896, 0.474596, 0.787028" \ + "0.0183814, 0.0783834, 0.115677, 0.179113, 0.28889, 0.474533, 0.785386", \ + "0.0183824, 0.0783844, 0.115678, 0.179114, 0.288891, 0.474534, 0.785387", \ + "0.0183834, 0.0783854, 0.115679, 0.179115, 0.288892, 0.474592, 0.787024", \ + "0.0183844, 0.0784242, 0.11568, 0.179116, 0.288893, 0.474593, 0.787025", \ + "0.0183854, 0.0784436, 0.115723, 0.179117, 0.288894, 0.474594, 0.787026", \ + "0.0183864, 0.0784446, 0.115724, 0.179118, 0.288895, 0.474595, 0.787027", \ + "0.0183874, 0.0784456, 0.115725, 0.179119, 0.288896, 0.474596, 0.787028" \ ); } cell_fall (TIMING_DELAY_7x7ds1) { @@ -29670,7 +29783,7 @@ library (sg13g2_stdcell_fast_1p32V_m40C) { "0.136435, 0.203842, 0.232909, 0.275085, 0.341259, 0.449177, 0.628311", \ "0.156138, 0.223558, 0.252627, 0.294743, 0.36088, 0.468857, 0.648098", \ "0.183571, 0.250917, 0.280008, 0.322107, 0.388272, 0.496247, 0.67531", \ - "0.222603, 0.289596, 0.318715, 0.361295, 0.427053, 0.535557, 0.714163", \ + "0.222129, 0.290048, 0.319173, 0.361295, 0.427484, 0.535083, 0.714592", \ "0.278444, 0.346554, 0.375754, 0.418011, 0.484242, 0.5923, 0.771346", \ "0.356315, 0.42745, 0.456904, 0.499329, 0.565594, 0.673584, 0.852778" \ ); @@ -29683,7 +29796,7 @@ library (sg13g2_stdcell_fast_1p32V_m40C) { "0.0232843, 0.0776431, 0.106373, 0.15447, 0.239501, 0.386574, 0.634997", \ "0.0233452, 0.0776441, 0.106399, 0.154471, 0.239502, 0.386575, 0.63936", \ "0.0234348, 0.0777541, 0.1064, 0.154484, 0.239503, 0.386576, 0.639361", \ - "0.024013, 0.0779934, 0.106607, 0.154565, 0.239504, 0.386577, 0.639362", \ + "0.0240014, 0.0779979, 0.106608, 0.154565, 0.239504, 0.386577, 0.639362", \ "0.025805, 0.078771, 0.107088, 0.154988, 0.23964, 0.386578, 0.639363", \ "0.030673, 0.081384, 0.108912, 0.155914, 0.240296, 0.386654, 0.639364" \ ); @@ -29691,32 +29804,33 @@ library (sg13g2_stdcell_fast_1p32V_m40C) { } timing () { related_pin : "RESET_B"; + sdf_edges : start_edge; timing_sense : negative_unate; timing_type : preset; cell_rise (TIMING_DELAY_7x7ds1) { index_1 ("0.0186, 0.0966, 0.174, 0.3294, 0.6408, 1.263, 2.5074"); index_2 ("0.001, 0.0468, 0.078, 0.1296, 0.216, 0.36, 0.6"); values ( \ - "0.142176, 0.202266, 0.23212, 0.278764, 0.355449, 0.482638, 0.694471", \ - "0.179747, 0.239937, 0.269715, 0.31642, 0.393098, 0.520421, 0.732045", \ - "0.207318, 0.267401, 0.297217, 0.34389, 0.420496, 0.547859, 0.759502", \ - "0.248882, 0.309253, 0.339084, 0.385707, 0.462346, 0.589562, 0.801257", \ - "0.307786, 0.368075, 0.397938, 0.444636, 0.52125, 0.64847, 0.860074", \ - "0.389592, 0.450288, 0.480163, 0.526848, 0.603503, 0.730814, 0.94256", \ - "0.502537, 0.563669, 0.593309, 0.640265, 0.716995, 0.844006, 1.05586" \ + "0.14221, 0.202271, 0.232139, 0.278814, 0.355484, 0.482667, 0.6945", \ + "0.17975, 0.239858, 0.269755, 0.31642, 0.39311, 0.520667, 0.732092", \ + "0.207312, 0.267384, 0.2972, 0.343851, 0.420532, 0.547829, 0.759468", \ + "0.248924, 0.309143, 0.338968, 0.385589, 0.46227, 0.589427, 0.801165", \ + "0.307449, 0.367828, 0.397661, 0.444366, 0.520954, 0.648142, 0.859792", \ + "0.389453, 0.449558, 0.479413, 0.526139, 0.602787, 0.729982, 0.941853", \ + "0.501729, 0.563516, 0.59348, 0.640427, 0.716853, 0.844279, 1.05618" \ ); } rise_transition (TIMING_DELAY_7x7ds1) { index_1 ("0.0186, 0.0966, 0.174, 0.3294, 0.6408, 1.263, 2.5074"); index_2 ("0.001, 0.0468, 0.078, 0.1296, 0.216, 0.36, 0.6"); values ( \ - "0.0183412, 0.0769762, 0.114575, 0.178553, 0.288653, 0.474684, 0.785329", \ - "0.0183729, 0.0769772, 0.114576, 0.178554, 0.288925, 0.474715, 0.78533", \ - "0.0184593, 0.0769886, 0.114577, 0.178555, 0.288926, 0.474716, 0.787678", \ - "0.0186896, 0.0770453, 0.114632, 0.178556, 0.288927, 0.474717, 0.787679", \ - "0.019115, 0.0772125, 0.114693, 0.178566, 0.288928, 0.474718, 0.78768", \ - "0.019848, 0.077565, 0.114912, 0.178675, 0.288929, 0.474719, 0.787681", \ - "0.02098, 0.078135, 0.11532, 0.178909, 0.28893, 0.47472, 0.787682" \ + "0.0183413, 0.0769494, 0.114572, 0.178579, 0.288654, 0.474684, 0.78533", \ + "0.0183624, 0.0769504, 0.114573, 0.17858, 0.288913, 0.475148, 0.785331", \ + "0.018461, 0.0769999, 0.114574, 0.178581, 0.288914, 0.475149, 0.787682", \ + "0.018665, 0.0770387, 0.114633, 0.178582, 0.288915, 0.47515, 0.787683", \ + "0.0191035, 0.0772539, 0.114689, 0.178602, 0.288916, 0.475151, 0.787684", \ + "0.019821, 0.07756, 0.114939, 0.178668, 0.288917, 0.475152, 0.787685", \ + "0.02099, 0.07817, 0.11529, 0.178933, 0.288918, 0.475153, 0.787686" \ ); } } @@ -29727,12 +29841,12 @@ library (sg13g2_stdcell_fast_1p32V_m40C) { index_1 ("0.0186, 0.0966, 0.174, 0.3294, 0.6408, 1.263, 2.5074"); index_2 ("0.001, 0.0468, 0.078, 0.1296, 0.216, 0.36, 0.6"); values ( \ - "0.049337, 0.0902169, 0.117687, 0.16272, 0.237878, 0.362784, 0.570699", \ + "0.0493425, 0.090217, 0.117687, 0.162725, 0.237878, 0.362784, 0.570701", \ "0.0493256, 0.0902181, 0.117908, 0.162754, 0.238505, 0.362659, 0.570789", \ "0.0501997, 0.0910089, 0.118353, 0.163609, 0.238695, 0.363696, 0.573089", \ "0.0515955, 0.0926105, 0.120107, 0.165218, 0.24021, 0.36579, 0.573189", \ "0.0551087, 0.0959416, 0.12356, 0.168744, 0.244288, 0.369053, 0.577766", \ - "0.0627714, 0.103496, 0.131108, 0.176141, 0.251719, 0.377408, 0.586039", \ + "0.0627714, 0.103496, 0.131108, 0.176142, 0.251719, 0.377408, 0.586039", \ "0.0790465, 0.119644, 0.146965, 0.192035, 0.267711, 0.392942, 0.601923" \ ); } @@ -29740,12 +29854,12 @@ library (sg13g2_stdcell_fast_1p32V_m40C) { index_1 ("0.0186, 0.0966, 0.174, 0.3294, 0.6408, 1.263, 2.5074"); index_2 ("0.001, 0.0468, 0.078, 0.1296, 0.216, 0.36, 0.6"); values ( \ - "0.0479374, 0.0876833, 0.11503, 0.159895, 0.234636, 0.359085, 0.566369", \ + "0.0479374, 0.0876833, 0.11503, 0.159895, 0.234636, 0.359084, 0.56637", \ "0.0477188, 0.087416, 0.114963, 0.161131, 0.234565, 0.359173, 0.565993", \ "0.048381, 0.0880981, 0.115292, 0.160248, 0.236514, 0.359405, 0.569376", \ "0.0498577, 0.0895654, 0.117118, 0.162279, 0.23629, 0.361988, 0.568423", \ - "0.0533118, 0.0926902, 0.120328, 0.165226, 0.240932, 0.364939, 0.572063", \ - "0.061373, 0.100249, 0.127743, 0.172801, 0.248266, 0.373799, 0.582909", \ + "0.053341, 0.0926644, 0.120304, 0.165226, 0.240989, 0.36573, 0.572014", \ + "0.061373, 0.100249, 0.127744, 0.172801, 0.248267, 0.373799, 0.582909", \ "0.0788633, 0.116717, 0.14389, 0.188693, 0.264182, 0.389177, 0.598551" \ ); } @@ -29756,12 +29870,12 @@ library (sg13g2_stdcell_fast_1p32V_m40C) { index_1 ("0.0186, 0.0966, 0.174, 0.3294, 0.6408, 1.263, 2.5074"); index_2 ("0.001, 0.0468, 0.078, 0.1296, 0.216, 0.36, 0.6"); values ( \ - "0.049337, 0.0902169, 0.117687, 0.16272, 0.237878, 0.362784, 0.570699", \ + "0.0493425, 0.090217, 0.117687, 0.162725, 0.237878, 0.362784, 0.570701", \ "0.0493256, 0.0902181, 0.117908, 0.162754, 0.238505, 0.362659, 0.570789", \ "0.0501997, 0.0910089, 0.118353, 0.163609, 0.238695, 0.363696, 0.573089", \ "0.0515955, 0.0926105, 0.120107, 0.165218, 0.24021, 0.36579, 0.573189", \ "0.0551087, 0.0959416, 0.12356, 0.168744, 0.244288, 0.369053, 0.577766", \ - "0.0627714, 0.103496, 0.131108, 0.176141, 0.251719, 0.377408, 0.586039", \ + "0.0627714, 0.103496, 0.131108, 0.176142, 0.251719, 0.377408, 0.586039", \ "0.0790465, 0.119644, 0.146965, 0.192035, 0.267711, 0.392942, 0.601923" \ ); } @@ -29769,12 +29883,12 @@ library (sg13g2_stdcell_fast_1p32V_m40C) { index_1 ("0.0186, 0.0966, 0.174, 0.3294, 0.6408, 1.263, 2.5074"); index_2 ("0.001, 0.0468, 0.078, 0.1296, 0.216, 0.36, 0.6"); values ( \ - "0.0479374, 0.0876833, 0.11503, 0.159895, 0.234636, 0.359085, 0.566369", \ + "0.0479374, 0.0876833, 0.11503, 0.159895, 0.234636, 0.359084, 0.56637", \ "0.0477188, 0.087416, 0.114963, 0.161131, 0.234565, 0.359173, 0.565993", \ "0.048381, 0.0880981, 0.115292, 0.160248, 0.236514, 0.359405, 0.569376", \ "0.0498577, 0.0895654, 0.117118, 0.162279, 0.23629, 0.361988, 0.568423", \ - "0.0533118, 0.0926902, 0.120328, 0.165226, 0.240932, 0.364939, 0.572063", \ - "0.061373, 0.100249, 0.127743, 0.172801, 0.248266, 0.373799, 0.582909", \ + "0.053341, 0.0926644, 0.120304, 0.165226, 0.240989, 0.36573, 0.572014", \ + "0.061373, 0.100249, 0.127744, 0.172801, 0.248267, 0.373799, 0.582909", \ "0.0788633, 0.116717, 0.14389, 0.188693, 0.264182, 0.389177, 0.598551" \ ); } @@ -29785,13 +29899,13 @@ library (sg13g2_stdcell_fast_1p32V_m40C) { index_1 ("0.0186, 0.0966, 0.174, 0.3294, 0.6408, 1.263, 2.5074"); index_2 ("0.001, 0.0468, 0.078, 0.1296, 0.216, 0.36, 0.6"); values ( \ - "0.049623, 0.0903719, 0.117903, 0.162963, 0.238078, 0.363049, 0.570951", \ - "0.0492428, 0.0901597, 0.117653, 0.163046, 0.238054, 0.362726, 0.570529", \ - "0.0496953, 0.090394, 0.117832, 0.163416, 0.238045, 0.362766, 0.573216", \ - "0.0512385, 0.0920451, 0.11961, 0.164494, 0.239666, 0.365969, 0.572857", \ - "0.055104, 0.0955241, 0.123215, 0.168471, 0.243759, 0.367962, 0.578446", \ - "0.0632026, 0.103346, 0.130772, 0.176162, 0.251623, 0.377036, 0.585418", \ - "0.0795601, 0.119434, 0.146755, 0.192086, 0.267136, 0.392877, 0.601921" \ + "0.0608583, 0.101663, 0.129141, 0.174265, 0.24932, 0.374211, 0.582175", \ + "0.0603116, 0.101265, 0.128716, 0.174132, 0.24904, 0.374179, 0.581886", \ + "0.0605037, 0.10117, 0.128568, 0.174168, 0.249099, 0.373495, 0.584126", \ + "0.0614268, 0.102209, 0.129716, 0.174553, 0.249722, 0.375955, 0.583195", \ + "0.0638406, 0.104297, 0.131925, 0.177271, 0.252452, 0.37676, 0.586331", \ + "0.0692751, 0.109452, 0.136929, 0.182279, 0.257779, 0.383366, 0.591238", \ + "0.0798152, 0.119589, 0.146855, 0.192268, 0.26724, 0.39297, 0.602149" \ ); } fall_power (scalar) { @@ -29806,10 +29920,10 @@ library (sg13g2_stdcell_fast_1p32V_m40C) { direction : input; max_transition : 2.5074; capacitance : 0.0031676; - rise_capacitance : 0.00319928; - rise_capacitance_range (0.00319928, 0.00319928); + rise_capacitance : 0.00319927; + rise_capacitance_range (0.00289542, 0.00344215); fall_capacitance : 0.00312688; - fall_capacitance_range (0.00312688, 0.00312688); + fall_capacitance_range (0.00284931, 0.00339293); timing () { related_pin : "CLK"; timing_type : min_pulse_width; @@ -29825,13 +29939,13 @@ library (sg13g2_stdcell_fast_1p32V_m40C) { rise_power (passive_POWER_7x1ds1) { index_1 ("0.0186, 0.0966, 0.174, 0.3294, 0.6408, 1.263, 2.5074"); values ( \ - "0.0132358, 0.0131213, 0.0137271, 0.0151735, 0.0184215, 0.0257914, 0.041806" \ + "0.0132357, 0.0131212, 0.0137271, 0.0151735, 0.0184215, 0.0257914, 0.041806" \ ); } fall_power (passive_POWER_7x1ds1) { index_1 ("0.0186, 0.0966, 0.174, 0.3294, 0.6408, 1.263, 2.5074"); values ( \ - "0.0128951, 0.0129366, 0.0134973, 0.0150804, 0.0183503, 0.0256736, 0.0413761" \ + "0.0128952, 0.0129366, 0.0134973, 0.0150804, 0.0183503, 0.0256736, 0.0413762" \ ); } } @@ -29845,7 +29959,7 @@ library (sg13g2_stdcell_fast_1p32V_m40C) { fall_power (passive_POWER_7x1ds1) { index_1 ("0.0186, 0.0966, 0.174, 0.3294, 0.6408, 1.263, 2.5074"); values ( \ - "0.0254595, 0.0253801, 0.0260758, 0.0276128, 0.0309328, 0.0385992, 0.0548346" \ + "0.0254553, 0.0253801, 0.0260758, 0.0276128, 0.0309328, 0.0385992, 0.0548346" \ ); } } @@ -29859,7 +29973,7 @@ library (sg13g2_stdcell_fast_1p32V_m40C) { fall_power (passive_POWER_7x1ds1) { index_1 ("0.0186, 0.0966, 0.174, 0.3294, 0.6408, 1.263, 2.5074"); values ( \ - "0.0231942, 0.0233348, 0.0239912, 0.0257514, 0.0291685, 0.0367679, 0.0527762" \ + "0.023196, 0.0233348, 0.0239912, 0.0257514, 0.0291685, 0.0367679, 0.0527762" \ ); } } @@ -29868,7 +29982,7 @@ library (sg13g2_stdcell_fast_1p32V_m40C) { rise_power (passive_POWER_7x1ds1) { index_1 ("0.0186, 0.0966, 0.174, 0.3294, 0.6408, 1.263, 2.5074"); values ( \ - "0.0129611, 0.0128469, 0.0134902, 0.0148415, 0.0181445, 0.0255023, 0.0414169" \ + "0.0129558, 0.0128469, 0.0134902, 0.0148414, 0.0181445, 0.0255023, 0.0414169" \ ); } fall_power (passive_POWER_7x1ds1) { @@ -29883,13 +29997,13 @@ library (sg13g2_stdcell_fast_1p32V_m40C) { rise_power (passive_POWER_7x1ds1) { index_1 ("0.0186, 0.0966, 0.174, 0.3294, 0.6408, 1.263, 2.5074"); values ( \ - "0.0132401, 0.0131213, 0.0137271, 0.0151734, 0.0184215, 0.0257914, 0.0418062" \ + "0.0132402, 0.0131212, 0.0137271, 0.0151734, 0.0184215, 0.0257914, 0.0418062" \ ); } fall_power (passive_POWER_7x1ds1) { index_1 ("0.0186, 0.0966, 0.174, 0.3294, 0.6408, 1.263, 2.5074"); values ( \ - "0.0129013, 0.0129396, 0.0134974, 0.0150804, 0.0183504, 0.0256743, 0.0413763" \ + "0.0129012, 0.0129396, 0.0134973, 0.0150804, 0.0183503, 0.0256742, 0.0413762" \ ); } } @@ -29898,13 +30012,13 @@ library (sg13g2_stdcell_fast_1p32V_m40C) { rise_power (passive_POWER_7x1ds1) { index_1 ("0.0186, 0.0966, 0.174, 0.3294, 0.6408, 1.263, 2.5074"); values ( \ - "0.0125311, 0.0124179, 0.0130357, 0.0143882, 0.0176686, 0.0250178, 0.0408878" \ + "0.0125311, 0.0124179, 0.0130357, 0.0143882, 0.0176685, 0.0250177, 0.0408878" \ ); } fall_power (passive_POWER_7x1ds1) { index_1 ("0.0186, 0.0966, 0.174, 0.3294, 0.6408, 1.263, 2.5074"); values ( \ - "0.0111952, 0.0112495, 0.011794, 0.0133814, 0.0166455, 0.0239907, 0.0396745" \ + "0.0111952, 0.0112495, 0.0117939, 0.0133814, 0.0166455, 0.0239907, 0.0396745" \ ); } } @@ -29919,7 +30033,7 @@ library (sg13g2_stdcell_fast_1p32V_m40C) { fall_power (passive_POWER_7x1ds1) { index_1 ("0.0186, 0.0966, 0.174, 0.3294, 0.6408, 1.263, 2.5074"); values ( \ - "0.0131499, 0.0131982, 0.013751, 0.0153347, 0.0185977, 0.0259531, 0.0416485" \ + "0.0131498, 0.0131982, 0.013751, 0.0153347, 0.0185977, 0.0259531, 0.0416485" \ ); } } @@ -29927,7 +30041,7 @@ library (sg13g2_stdcell_fast_1p32V_m40C) { rise_power (passive_POWER_7x1ds1) { index_1 ("0.0186, 0.0966, 0.174, 0.3294, 0.6408, 1.263, 2.5074"); values ( \ - "0.0129611, 0.0128469, 0.0134902, 0.0148415, 0.0181445, 0.0255023, 0.0414169" \ + "0.0129598, 0.012847, 0.0134903, 0.0148414, 0.0181444, 0.025502, 0.0414161" \ ); } fall_power (passive_POWER_7x1ds1) { @@ -29944,11 +30058,12 @@ library (sg13g2_stdcell_fast_1p32V_m40C) { max_transition : 2.5074; capacitance : 0.00297723; rise_capacitance : 0.0030122; - rise_capacitance_range (0.0030122, 0.0030122); + rise_capacitance_range (0.002606, 0.00331438); fall_capacitance : 0.00294226; - fall_capacitance_range (0.00294226, 0.00294226); + fall_capacitance_range (0.00257973, 0.00316861); timing () { related_pin : "CLK"; + sdf_edges : both_edges; timing_type : hold_rising; rise_constraint (CONSTRAINT_4x4) { index_1 ("0.0186, 0.51636, 1.263, 2.5074"); @@ -29973,6 +30088,7 @@ library (sg13g2_stdcell_fast_1p32V_m40C) { } timing () { related_pin : "CLK"; + sdf_edges : both_edges; timing_type : setup_rising; rise_constraint (CONSTRAINT_4x4) { index_1 ("0.0186, 0.51636, 1.263, 2.5074"); @@ -30000,13 +30116,13 @@ library (sg13g2_stdcell_fast_1p32V_m40C) { rise_power (passive_POWER_7x1ds1) { index_1 ("0.0186, 0.0966, 0.174, 0.3294, 0.6408, 1.263, 2.5074"); values ( \ - "0.0251327, 0.0249882, 0.0252851, 0.0263807, 0.0290682, 0.0349582, 0.0477994" \ + "0.0251326, 0.0249882, 0.025285, 0.0263807, 0.0290681, 0.0349581, 0.0477994" \ ); } fall_power (passive_POWER_7x1ds1) { index_1 ("0.0186, 0.0966, 0.174, 0.3294, 0.6408, 1.263, 2.5074"); values ( \ - "0.0243888, 0.0243814, 0.0248992, 0.0262606, 0.0293135, 0.0355335, 0.0486894" \ + "0.0243894, 0.0243813, 0.0248992, 0.0262606, 0.0293135, 0.0355334, 0.0486894" \ ); } } @@ -30014,13 +30130,13 @@ library (sg13g2_stdcell_fast_1p32V_m40C) { rise_power (passive_POWER_7x1ds1) { index_1 ("0.0186, 0.0966, 0.174, 0.3294, 0.6408, 1.263, 2.5074"); values ( \ - "0.0251327, 0.0249882, 0.0252851, 0.0263807, 0.0290682, 0.0349582, 0.0477994" \ + "0.0251326, 0.0249882, 0.025285, 0.0263807, 0.0290681, 0.0349581, 0.0477994" \ ); } fall_power (passive_POWER_7x1ds1) { index_1 ("0.0186, 0.0966, 0.174, 0.3294, 0.6408, 1.263, 2.5074"); values ( \ - "0.0243888, 0.0243814, 0.0248992, 0.0262606, 0.0293135, 0.0355335, 0.0486894" \ + "0.0243894, 0.0243813, 0.0248992, 0.0262606, 0.0293135, 0.0355334, 0.0486894" \ ); } } @@ -30028,13 +30144,14 @@ library (sg13g2_stdcell_fast_1p32V_m40C) { pin (RESET_B) { direction : input; max_transition : 2.5074; - capacitance : 0.00541064; - rise_capacitance : 0.00541064; - rise_capacitance_range (0.00541064, 0.00541064); - fall_capacitance : 0.00541064; - fall_capacitance_range (0.00541064, 0.00541064); + capacitance : 0.00572022; + rise_capacitance : 0.00572022; + rise_capacitance_range (0.00572022, 0.00572022); + fall_capacitance : 0.00572022; + fall_capacitance_range (0.00510573, 0.00594361); timing () { related_pin : "CLK"; + sdf_edges : both_edges; timing_type : recovery_rising; rise_constraint (CONSTRAINT_4x4) { index_1 ("0.0186, 0.51636, 1.263, 2.5074"); @@ -30049,6 +30166,7 @@ library (sg13g2_stdcell_fast_1p32V_m40C) { } timing () { related_pin : "CLK"; + sdf_edges : both_edges; timing_type : removal_rising; rise_constraint (CONSTRAINT_4x4) { index_1 ("0.0186, 0.51636, 1.263, 2.5074"); @@ -30078,11 +30196,12 @@ library (sg13g2_stdcell_fast_1p32V_m40C) { max_transition : 2.5074; capacitance : 0.00309164; rise_capacitance : 0.00311543; - rise_capacitance_range (0.00311543, 0.00311543); + rise_capacitance_range (0.00271532, 0.00341658); fall_capacitance : 0.00304406; - fall_capacitance_range (0.00304406, 0.00304406); + fall_capacitance_range (0.00268557, 0.00327115); timing () { related_pin : "CLK"; + sdf_edges : both_edges; timing_type : hold_rising; rise_constraint (CONSTRAINT_4x4) { index_1 ("0.0186, 0.51636, 1.263, 2.5074"); @@ -30107,6 +30226,7 @@ library (sg13g2_stdcell_fast_1p32V_m40C) { } timing () { related_pin : "CLK"; + sdf_edges : both_edges; timing_type : setup_rising; rise_constraint (CONSTRAINT_4x4) { index_1 ("0.0186, 0.51636, 1.263, 2.5074"); @@ -30165,11 +30285,12 @@ library (sg13g2_stdcell_fast_1p32V_m40C) { max_transition : 2.5074; capacitance : 0.0052915; rise_capacitance : 0.00559007; - rise_capacitance_range (0.00559007, 0.00559007); + rise_capacitance_range (0.00473235, 0.00631032); fall_capacitance : 0.00499293; - fall_capacitance_range (0.00499293, 0.00499293); + fall_capacitance_range (0.00471666, 0.005538); timing () { related_pin : "CLK"; + sdf_edges : both_edges; timing_type : hold_rising; rise_constraint (CONSTRAINT_4x4) { index_1 ("0.0186, 0.51636, 1.263, 2.5074"); @@ -30194,6 +30315,7 @@ library (sg13g2_stdcell_fast_1p32V_m40C) { } timing () { related_pin : "CLK"; + sdf_edges : both_edges; timing_type : setup_rising; rise_constraint (CONSTRAINT_4x4) { index_1 ("0.0186, 0.51636, 1.263, 2.5074"); @@ -30221,13 +30343,13 @@ library (sg13g2_stdcell_fast_1p32V_m40C) { rise_power (passive_POWER_7x1ds1) { index_1 ("0.0186, 0.0966, 0.174, 0.3294, 0.6408, 1.263, 2.5074"); values ( \ - "0.027555, 0.0274478, 0.027796, 0.0287848, 0.0311102, 0.0363205, 0.047443" \ + "0.027555, 0.0274477, 0.027796, 0.0287848, 0.0311102, 0.0363205, 0.047443" \ ); } fall_power (passive_POWER_7x1ds1) { index_1 ("0.0186, 0.0966, 0.174, 0.3294, 0.6408, 1.263, 2.5074"); values ( \ - "0.0317727, 0.0317537, 0.0321297, 0.0332614, 0.0355716, 0.0407943, 0.0518453" \ + "0.0317726, 0.0317537, 0.0321297, 0.0332613, 0.0355716, 0.0407943, 0.0518452" \ ); } } @@ -30242,7 +30364,7 @@ library (sg13g2_stdcell_fast_1p32V_m40C) { fall_power (passive_POWER_7x1ds1) { index_1 ("0.0186, 0.0966, 0.174, 0.3294, 0.6408, 1.263, 2.5074"); values ( \ - "0.0359804, 0.0500984, 0.0512562, 0.0533321, 0.0581523, 0.0689243, 0.0914303" \ + "0.0359804, 0.0500984, 0.0512561, 0.0533321, 0.0581523, 0.0689243, 0.0914303" \ ); } } @@ -30256,15 +30378,15 @@ library (sg13g2_stdcell_fast_1p32V_m40C) { fall_power (passive_POWER_7x1ds1) { index_1 ("0.0186, 0.0966, 0.174, 0.3294, 0.6408, 1.263, 2.5074"); values ( \ - "0.0359804, 0.0500984, 0.0512562, 0.0533321, 0.0581523, 0.0689243, 0.0914303" \ + "0.0359804, 0.0500984, 0.0512561, 0.0533321, 0.0581523, 0.0689243, 0.0914303" \ ); } } } ff (IQ,IQN) { - clear : "RESET_B'"; + clear : "!RESET_B"; clocked_on : "CLK"; - next_state : "(SCE*SCD)+(SCE'*D)"; + next_state : "(SCE*SCD)+(!SCE*D)"; } test_cell () { pin (Q) { @@ -30295,7 +30417,7 @@ library (sg13g2_stdcell_fast_1p32V_m40C) { signal_type : test_scan_enable; } ff (IQ,IQN) { - clear : "RESET_B'"; + clear : "!RESET_B"; clocked_on : "CLK"; next_state : "D"; } @@ -30381,6 +30503,7 @@ library (sg13g2_stdcell_fast_1p32V_m40C) { timing () { related_pin : "CLK"; sdf_cond : "SCE == 1'b1"; + sdf_edges : start_edge; timing_sense : non_unate; timing_type : rising_edge; when : "SCE"; @@ -30440,6 +30563,7 @@ library (sg13g2_stdcell_fast_1p32V_m40C) { timing () { related_pin : "CLK"; sdf_cond : "SCE == 1'b0"; + sdf_edges : start_edge; timing_sense : non_unate; timing_type : rising_edge; when : "!SCE"; @@ -30498,6 +30622,7 @@ library (sg13g2_stdcell_fast_1p32V_m40C) { } timing () { related_pin : "CLK"; + sdf_edges : start_edge; timing_sense : non_unate; timing_type : rising_edge; cell_rise (TIMING_DELAY_7x7ds1) { @@ -30555,6 +30680,7 @@ library (sg13g2_stdcell_fast_1p32V_m40C) { } timing () { related_pin : "RESET_B"; + sdf_edges : start_edge; timing_sense : positive_unate; timing_type : clear; cell_fall (TIMING_DELAY_7x7ds1) { @@ -30701,9 +30827,9 @@ library (sg13g2_stdcell_fast_1p32V_m40C) { max_transition : 2.5074; capacitance : 0.00316744; rise_capacitance : 0.00319906; - rise_capacitance_range (0.00319906, 0.00319906); + rise_capacitance_range (0.00289473, 0.00344008); fall_capacitance : 0.00312679; - fall_capacitance_range (0.00312679, 0.00312679); + fall_capacitance_range (0.00284709, 0.00339283); timing () { related_pin : "CLK"; timing_type : min_pulse_width; @@ -30844,11 +30970,12 @@ library (sg13g2_stdcell_fast_1p32V_m40C) { max_transition : 2.5074; capacitance : 0.00297965; rise_capacitance : 0.00301491; - rise_capacitance_range (0.00301491, 0.00301491); + rise_capacitance_range (0.00261092, 0.00331678); fall_capacitance : 0.00294439; - fall_capacitance_range (0.00294439, 0.00294439); + fall_capacitance_range (0.00258226, 0.00317093); timing () { related_pin : "CLK"; + sdf_edges : both_edges; timing_type : hold_rising; rise_constraint (CONSTRAINT_4x4) { index_1 ("0.0186, 0.51636, 1.263, 2.5074"); @@ -30873,6 +31000,7 @@ library (sg13g2_stdcell_fast_1p32V_m40C) { } timing () { related_pin : "CLK"; + sdf_edges : both_edges; timing_type : setup_rising; rise_constraint (CONSTRAINT_4x4) { index_1 ("0.0186, 0.51636, 1.263, 2.5074"); @@ -30932,9 +31060,10 @@ library (sg13g2_stdcell_fast_1p32V_m40C) { rise_capacitance : 0.00540816; rise_capacitance_range (0.00540816, 0.00540816); fall_capacitance : 0.00540816; - fall_capacitance_range (0.00540816, 0.00540816); + fall_capacitance_range (0.00502072, 0.00570751); timing () { related_pin : "CLK"; + sdf_edges : both_edges; timing_type : recovery_rising; rise_constraint (CONSTRAINT_4x4) { index_1 ("0.0186, 0.51636, 1.263, 2.5074"); @@ -30949,6 +31078,7 @@ library (sg13g2_stdcell_fast_1p32V_m40C) { } timing () { related_pin : "CLK"; + sdf_edges : both_edges; timing_type : removal_rising; rise_constraint (CONSTRAINT_4x4) { index_1 ("0.0186, 0.51636, 1.263, 2.5074"); @@ -30978,11 +31108,12 @@ library (sg13g2_stdcell_fast_1p32V_m40C) { max_transition : 2.5074; capacitance : 0.00309389; rise_capacitance : 0.00311766; - rise_capacitance_range (0.00311766, 0.00311766); + rise_capacitance_range (0.00271715, 0.00341894); fall_capacitance : 0.00304634; - fall_capacitance_range (0.00304634, 0.00304634); + fall_capacitance_range (0.00268796, 0.00327344); timing () { related_pin : "CLK"; + sdf_edges : both_edges; timing_type : hold_rising; rise_constraint (CONSTRAINT_4x4) { index_1 ("0.0186, 0.51636, 1.263, 2.5074"); @@ -31007,6 +31138,7 @@ library (sg13g2_stdcell_fast_1p32V_m40C) { } timing () { related_pin : "CLK"; + sdf_edges : both_edges; timing_type : setup_rising; rise_constraint (CONSTRAINT_4x4) { index_1 ("0.0186, 0.51636, 1.263, 2.5074"); @@ -31065,11 +31197,12 @@ library (sg13g2_stdcell_fast_1p32V_m40C) { max_transition : 2.5074; capacitance : 0.00529119; rise_capacitance : 0.0055898; - rise_capacitance_range (0.0055898, 0.0055898); + rise_capacitance_range (0.0047285, 0.00631036); fall_capacitance : 0.00499259; - fall_capacitance_range (0.00499259, 0.00499259); + fall_capacitance_range (0.00471733, 0.00553795); timing () { related_pin : "CLK"; + sdf_edges : both_edges; timing_type : hold_rising; rise_constraint (CONSTRAINT_4x4) { index_1 ("0.0186, 0.51636, 1.263, 2.5074"); @@ -31094,6 +31227,7 @@ library (sg13g2_stdcell_fast_1p32V_m40C) { } timing () { related_pin : "CLK"; + sdf_edges : both_edges; timing_type : setup_rising; rise_constraint (CONSTRAINT_4x4) { index_1 ("0.0186, 0.51636, 1.263, 2.5074"); @@ -31162,9 +31296,9 @@ library (sg13g2_stdcell_fast_1p32V_m40C) { } } ff (IQ,IQN) { - clear : "RESET_B'"; + clear : "!RESET_B"; clocked_on : "CLK"; - next_state : "(SCE*SCD)+(SCE'*D)"; + next_state : "(SCE*SCD)+(!SCE*D)"; } test_cell () { pin (Q) { @@ -31190,7 +31324,7 @@ library (sg13g2_stdcell_fast_1p32V_m40C) { signal_type : test_scan_enable; } ff (IQ,IQN) { - clear : "RESET_B'"; + clear : "!RESET_B"; clocked_on : "CLK"; next_state : "D"; } @@ -31276,6 +31410,7 @@ library (sg13g2_stdcell_fast_1p32V_m40C) { timing () { related_pin : "CLK"; sdf_cond : "SCE == 1'b1"; + sdf_edges : start_edge; timing_sense : non_unate; timing_type : rising_edge; when : "SCE"; @@ -31335,6 +31470,7 @@ library (sg13g2_stdcell_fast_1p32V_m40C) { timing () { related_pin : "CLK"; sdf_cond : "SCE == 1'b0"; + sdf_edges : start_edge; timing_sense : non_unate; timing_type : rising_edge; when : "!SCE"; @@ -31393,6 +31529,7 @@ library (sg13g2_stdcell_fast_1p32V_m40C) { } timing () { related_pin : "CLK"; + sdf_edges : start_edge; timing_sense : non_unate; timing_type : rising_edge; cell_rise (TIMING_DELAY_7x7ds1) { @@ -31450,6 +31587,7 @@ library (sg13g2_stdcell_fast_1p32V_m40C) { } timing () { related_pin : "RESET_B"; + sdf_edges : start_edge; timing_sense : positive_unate; timing_type : clear; cell_fall (TIMING_DELAY_7x7ds1) { @@ -31596,9 +31734,9 @@ library (sg13g2_stdcell_fast_1p32V_m40C) { max_transition : 2.5074; capacitance : 0.00316737; rise_capacitance : 0.00319899; - rise_capacitance_range (0.00319899, 0.00319899); + rise_capacitance_range (0.00289751, 0.00344009); fall_capacitance : 0.00312673; - fall_capacitance_range (0.00312673, 0.00312673); + fall_capacitance_range (0.00284824, 0.00339282); timing () { related_pin : "CLK"; timing_type : min_pulse_width; @@ -31739,11 +31877,12 @@ library (sg13g2_stdcell_fast_1p32V_m40C) { max_transition : 2.5074; capacitance : 0.00297731; rise_capacitance : 0.00301239; - rise_capacitance_range (0.00301239, 0.00301239); + rise_capacitance_range (0.00260737, 0.00331444); fall_capacitance : 0.00294222; - fall_capacitance_range (0.00294222, 0.00294222); + fall_capacitance_range (0.00258122, 0.00316859); timing () { related_pin : "CLK"; + sdf_edges : both_edges; timing_type : hold_rising; rise_constraint (CONSTRAINT_4x4) { index_1 ("0.0186, 0.51636, 1.263, 2.5074"); @@ -31768,6 +31907,7 @@ library (sg13g2_stdcell_fast_1p32V_m40C) { } timing () { related_pin : "CLK"; + sdf_edges : both_edges; timing_type : setup_rising; rise_constraint (CONSTRAINT_4x4) { index_1 ("0.0186, 0.51636, 1.263, 2.5074"); @@ -31827,9 +31967,10 @@ library (sg13g2_stdcell_fast_1p32V_m40C) { rise_capacitance : 0.00541504; rise_capacitance_range (0.00541504, 0.00541504); fall_capacitance : 0.00541504; - fall_capacitance_range (0.00541504, 0.00541504); + fall_capacitance_range (0.00503764, 0.00570979); timing () { related_pin : "CLK"; + sdf_edges : both_edges; timing_type : recovery_rising; rise_constraint (CONSTRAINT_4x4) { index_1 ("0.0186, 0.51636, 1.263, 2.5074"); @@ -31844,6 +31985,7 @@ library (sg13g2_stdcell_fast_1p32V_m40C) { } timing () { related_pin : "CLK"; + sdf_edges : both_edges; timing_type : removal_rising; rise_constraint (CONSTRAINT_4x4) { index_1 ("0.0186, 0.51636, 1.263, 2.5074"); @@ -31873,11 +32015,12 @@ library (sg13g2_stdcell_fast_1p32V_m40C) { max_transition : 2.5074; capacitance : 0.00309243; rise_capacitance : 0.00311633; - rise_capacitance_range (0.00311633, 0.00311633); + rise_capacitance_range (0.00271634, 0.00341745); fall_capacitance : 0.00304464; - fall_capacitance_range (0.00304464, 0.00304464); + fall_capacitance_range (0.00268637, 0.003272); timing () { related_pin : "CLK"; + sdf_edges : both_edges; timing_type : hold_rising; rise_constraint (CONSTRAINT_4x4) { index_1 ("0.0186, 0.51636, 1.263, 2.5074"); @@ -31902,6 +32045,7 @@ library (sg13g2_stdcell_fast_1p32V_m40C) { } timing () { related_pin : "CLK"; + sdf_edges : both_edges; timing_type : setup_rising; rise_constraint (CONSTRAINT_4x4) { index_1 ("0.0186, 0.51636, 1.263, 2.5074"); @@ -31960,11 +32104,12 @@ library (sg13g2_stdcell_fast_1p32V_m40C) { max_transition : 2.5074; capacitance : 0.00529132; rise_capacitance : 0.00558977; - rise_capacitance_range (0.00558977, 0.00558977); + rise_capacitance_range (0.00472844, 0.00631037); fall_capacitance : 0.00499288; - fall_capacitance_range (0.00499288, 0.00499288); + fall_capacitance_range (0.00471734, 0.00553795); timing () { related_pin : "CLK"; + sdf_edges : both_edges; timing_type : hold_rising; rise_constraint (CONSTRAINT_4x4) { index_1 ("0.0186, 0.51636, 1.263, 2.5074"); @@ -31989,6 +32134,7 @@ library (sg13g2_stdcell_fast_1p32V_m40C) { } timing () { related_pin : "CLK"; + sdf_edges : both_edges; timing_type : setup_rising; rise_constraint (CONSTRAINT_4x4) { index_1 ("0.0186, 0.51636, 1.263, 2.5074"); @@ -32057,9 +32203,9 @@ library (sg13g2_stdcell_fast_1p32V_m40C) { } } ff (IQ,IQN) { - clear : "RESET_B'"; + clear : "!RESET_B"; clocked_on : "CLK"; - next_state : "(SCE*SCD)+(SCE'*D)"; + next_state : "(SCE*SCD)+(!SCE*D)"; } test_cell () { pin (Q) { @@ -32085,7 +32231,7 @@ library (sg13g2_stdcell_fast_1p32V_m40C) { signal_type : test_scan_enable; } ff (IQ,IQN) { - clear : "RESET_B'"; + clear : "!RESET_B"; clocked_on : "CLK"; next_state : "D"; } @@ -32093,7 +32239,7 @@ library (sg13g2_stdcell_fast_1p32V_m40C) { } cell (sg13g2_sighold) { area : 9.072; - cell_footprint : "keepstate"; + cell_footprint : "sighold"; cell_leakage_power : 404.05; dont_touch : true; dont_use : true; @@ -32131,7 +32277,7 @@ library (sg13g2_stdcell_fast_1p32V_m40C) { } cell (sg13g2_slgcp_1) { area : 30.8448; - cell_footprint : "sgclk"; + cell_footprint : "slgcp"; cell_leakage_power : 876.637; clock_gating_integrated_cell : "latch_posedge_precontrol"; dont_touch : true; @@ -32270,9 +32416,9 @@ library (sg13g2_stdcell_fast_1p32V_m40C) { max_transition : 2.5074; capacitance : 0.00539208; rise_capacitance : 0.00549342; - rise_capacitance_range (0.00549342, 0.00549342); + rise_capacitance_range (0.00466657, 0.00630834); fall_capacitance : 0.00529073; - fall_capacitance_range (0.00529073, 0.00529073); + fall_capacitance_range (0.00483904, 0.00564674); timing () { related_pin : "CLK"; timing_type : min_pulse_width; @@ -32310,11 +32456,12 @@ library (sg13g2_stdcell_fast_1p32V_m40C) { max_transition : 2.5074; capacitance : 0.00207848; rise_capacitance : 0.00252495; - rise_capacitance_range (0.00252495, 0.00252495); + rise_capacitance_range (0.00231635, 0.00275145); fall_capacitance : 0.001632; - fall_capacitance_range (0.001632, 0.001632); + fall_capacitance_range (0.001632, 0.00253253); timing () { related_pin : "CLK"; + sdf_edges : both_edges; timing_type : hold_rising; rise_constraint (CONSTRAINT_4x4) { index_1 ("0.0186, 0.51636, 1.263, 2.5074"); @@ -32339,6 +32486,7 @@ library (sg13g2_stdcell_fast_1p32V_m40C) { } timing () { related_pin : "CLK"; + sdf_edges : both_edges; timing_type : setup_rising; rise_constraint (CONSTRAINT_4x4) { index_1 ("0.0186, 0.51636, 1.263, 2.5074"); @@ -32397,11 +32545,12 @@ library (sg13g2_stdcell_fast_1p32V_m40C) { max_transition : 2.5074; capacitance : 0.00251435; rise_capacitance : 0.0024514; - rise_capacitance_range (0.0024514, 0.0024514); + rise_capacitance_range (0.00226832, 0.00261102); fall_capacitance : 0.0025773; - fall_capacitance_range (0.0025773, 0.0025773); + fall_capacitance_range (0.00237107, 0.0027381); timing () { related_pin : "CLK"; + sdf_edges : both_edges; timing_type : hold_rising; rise_constraint (CONSTRAINT_4x4) { index_1 ("0.0186, 0.51636, 1.263, 2.5074"); @@ -32426,6 +32575,7 @@ library (sg13g2_stdcell_fast_1p32V_m40C) { } timing () { related_pin : "CLK"; + sdf_edges : both_edges; timing_type : setup_rising; rise_constraint (CONSTRAINT_4x4) { index_1 ("0.0186, 0.51636, 1.263, 2.5074"); @@ -32466,7 +32616,7 @@ library (sg13g2_stdcell_fast_1p32V_m40C) { } cell (sg13g2_tiehi) { area : 7.2576; - cell_footprint : "tie1"; + cell_footprint : "tiehi"; cell_leakage_power : 230.883; pin (L_HI) { direction : "output"; @@ -32476,7 +32626,7 @@ library (sg13g2_stdcell_fast_1p32V_m40C) { } cell (sg13g2_tielo) { area : 7.2576; - cell_footprint : "tie0"; + cell_footprint : "tielo"; cell_leakage_power : 246.503; pin (L_LO) { direction : "output"; @@ -32486,7 +32636,7 @@ library (sg13g2_stdcell_fast_1p32V_m40C) { } cell (sg13g2_xnor2_1) { area : 14.5152; - cell_footprint : "xnor2_1"; + cell_footprint : "xnor2"; cell_leakage_power : 440.211; leakage_power () { value : 585.626; @@ -33043,23 +33193,23 @@ library (sg13g2_stdcell_fast_1p32V_m40C) { max_transition : 2.5074; capacitance : 0.00612626; rise_capacitance : 0.00613571; - rise_capacitance_range (0.00613571, 0.00613571); + rise_capacitance_range (0.00515757, 0.0071569); fall_capacitance : 0.00611681; - fall_capacitance_range (0.00611681, 0.00611681); + fall_capacitance_range (0.00514122, 0.00696147); } pin (B) { direction : "input"; max_transition : 2.5074; capacitance : 0.00544048; rise_capacitance : 0.0054567; - rise_capacitance_range (0.0054567, 0.0054567); + rise_capacitance_range (0.00475744, 0.00629391); fall_capacitance : 0.00542426; - fall_capacitance_range (0.00542426, 0.00542426); + fall_capacitance_range (0.00470076, 0.00619955); } } cell (sg13g2_xor2_1) { area : 14.5152; - cell_footprint : "xor2_1"; + cell_footprint : "xor2"; cell_leakage_power : 407.771; leakage_power () { value : 431.274; @@ -33616,18 +33766,18 @@ library (sg13g2_stdcell_fast_1p32V_m40C) { max_transition : 2.5074; capacitance : 0.00625451; rise_capacitance : 0.00628181; - rise_capacitance_range (0.00628181, 0.00628181); + rise_capacitance_range (0.00536188, 0.00706221); fall_capacitance : 0.00622722; - fall_capacitance_range (0.00622722, 0.00622722); + fall_capacitance_range (0.00513301, 0.00734245); } pin (B) { direction : "input"; max_transition : 2.5074; capacitance : 0.00548607; rise_capacitance : 0.00555033; - rise_capacitance_range (0.00555033, 0.00555033); + rise_capacitance_range (0.00475409, 0.00637819); fall_capacitance : 0.00542182; - fall_capacitance_range (0.00542182, 0.00542182); + fall_capacitance_range (0.00482928, 0.0061069); } } } diff --git a/flow/platforms/ihp-sg13g2/lib/sg13g2_stdcell_fast_1p65V_m40C.lib b/flow/platforms/ihp-sg13g2/lib/sg13g2_stdcell_fast_1p65V_m40C.lib index 7e50dc3d95..af7459a596 100644 --- a/flow/platforms/ihp-sg13g2/lib/sg13g2_stdcell_fast_1p65V_m40C.lib +++ b/flow/platforms/ihp-sg13g2/lib/sg13g2_stdcell_fast_1p65V_m40C.lib @@ -18,8 +18,8 @@ library (sg13g2_stdcell_fast_1p65V_m40C) { comment : "IHP Microelectronics GmbH, 2025"; - date : "$Date: Fri Jun 13 10:55:13 2025 $"; - revision : "$Revision: 0.1.3 $"; + date : "$Date: Tue Nov 4 15:58:07 2025 $"; + revision : "$Revision: 0.1.4 $"; delay_model : table_lookup; capacitive_load_unit (1,pf); current_unit : "1uA"; @@ -210,7 +210,7 @@ library (sg13g2_stdcell_fast_1p65V_m40C) { } cell (sg13g2_a21o_1) { area : 12.7008; - cell_footprint : "AO21"; + cell_footprint : "a21o"; cell_leakage_power : 1428.39; leakage_power () { value : 1253.01; @@ -483,7 +483,7 @@ library (sg13g2_stdcell_fast_1p65V_m40C) { } timing () { related_pin : "B1"; - sdf_cond : "A1 == 1'b1 & A2 == 1'b0"; + sdf_cond : "A1 == 1'b1 && A2 == 1'b0"; timing_sense : positive_unate; timing_type : combinational; when : "(A1 * !A2)"; @@ -542,7 +542,7 @@ library (sg13g2_stdcell_fast_1p65V_m40C) { } timing () { related_pin : "B1"; - sdf_cond : "A1 == 1'b0 & A2 == 1'b1"; + sdf_cond : "A1 == 1'b0 && A2 == 1'b1"; timing_sense : positive_unate; timing_type : combinational; when : "(!A1 * A2)"; @@ -601,7 +601,7 @@ library (sg13g2_stdcell_fast_1p65V_m40C) { } timing () { related_pin : "B1"; - sdf_cond : "A1 == 1'b0 & A2 == 1'b0"; + sdf_cond : "A1 == 1'b0 && A2 == 1'b0"; timing_sense : positive_unate; timing_type : combinational; when : "(!A1 * !A2)"; @@ -958,32 +958,32 @@ library (sg13g2_stdcell_fast_1p65V_m40C) { max_transition : 2.5074; capacitance : 0.00308648; rise_capacitance : 0.00297106; - rise_capacitance_range (0.00297106, 0.00297106); + rise_capacitance_range (0.0026844, 0.00316597); fall_capacitance : 0.00320191; - fall_capacitance_range (0.00320191, 0.00320191); + fall_capacitance_range (0.00262979, 0.00353297); } pin (A2) { direction : "input"; max_transition : 2.5074; capacitance : 0.00321316; rise_capacitance : 0.00325081; - rise_capacitance_range (0.00325081, 0.00325081); + rise_capacitance_range (0.00274445, 0.00348364); fall_capacitance : 0.0031755; - fall_capacitance_range (0.0031755, 0.0031755); + fall_capacitance_range (0.0027178, 0.00338684); } pin (B1) { direction : "input"; max_transition : 2.5074; capacitance : 0.00300687; rise_capacitance : 0.0032003; - rise_capacitance_range (0.0032003, 0.0032003); + rise_capacitance_range (0.00254132, 0.00382461); fall_capacitance : 0.00281345; - fall_capacitance_range (0.00281345, 0.00281345); + fall_capacitance_range (0.00255476, 0.00304377); } } cell (sg13g2_a21o_2) { area : 14.5152; - cell_footprint : "AO21"; + cell_footprint : "a21o"; cell_leakage_power : 1989.32; leakage_power () { value : 1987.45; @@ -1256,7 +1256,7 @@ library (sg13g2_stdcell_fast_1p65V_m40C) { } timing () { related_pin : "B1"; - sdf_cond : "A1 == 1'b1 & A2 == 1'b0"; + sdf_cond : "A1 == 1'b1 && A2 == 1'b0"; timing_sense : positive_unate; timing_type : combinational; when : "(A1 * !A2)"; @@ -1315,7 +1315,7 @@ library (sg13g2_stdcell_fast_1p65V_m40C) { } timing () { related_pin : "B1"; - sdf_cond : "A1 == 1'b0 & A2 == 1'b1"; + sdf_cond : "A1 == 1'b0 && A2 == 1'b1"; timing_sense : positive_unate; timing_type : combinational; when : "(!A1 * A2)"; @@ -1374,7 +1374,7 @@ library (sg13g2_stdcell_fast_1p65V_m40C) { } timing () { related_pin : "B1"; - sdf_cond : "A1 == 1'b0 & A2 == 1'b0"; + sdf_cond : "A1 == 1'b0 && A2 == 1'b0"; timing_sense : positive_unate; timing_type : combinational; when : "(!A1 * !A2)"; @@ -1731,27 +1731,27 @@ library (sg13g2_stdcell_fast_1p65V_m40C) { max_transition : 2.5074; capacitance : 0.00327536; rise_capacitance : 0.00315107; - rise_capacitance_range (0.00315107, 0.00315107); + rise_capacitance_range (0.00284451, 0.00340348); fall_capacitance : 0.00339965; - fall_capacitance_range (0.00339965, 0.00339965); + fall_capacitance_range (0.00285562, 0.00367903); } pin (A2) { direction : "input"; max_transition : 2.5074; capacitance : 0.00332135; rise_capacitance : 0.0033603; - rise_capacitance_range (0.0033603, 0.0033603); + rise_capacitance_range (0.00280095, 0.00363252); fall_capacitance : 0.00328241; - fall_capacitance_range (0.00328241, 0.00328241); + fall_capacitance_range (0.00284014, 0.00346958); } pin (B1) { direction : "input"; max_transition : 2.5074; capacitance : 0.0031365; rise_capacitance : 0.00332487; - rise_capacitance_range (0.00332487, 0.00332487); + rise_capacitance_range (0.00267907, 0.00401986); fall_capacitance : 0.00294813; - fall_capacitance_range (0.00294813, 0.00294813); + fall_capacitance_range (0.00271654, 0.00312752); } } cell (sg13g2_a21oi_1) { @@ -1759,7 +1759,7 @@ library (sg13g2_stdcell_fast_1p65V_m40C) { cell_footprint : "a21oi"; cell_leakage_power : 1213.56; leakage_power () { - value : 591.742; + value : 591.743; when : "!A1&!A2&!B1&Y"; } leakage_power () { @@ -1767,7 +1767,7 @@ library (sg13g2_stdcell_fast_1p65V_m40C) { when : "!A1&!A2&B1&!Y"; } leakage_power () { - value : 1071.33; + value : 1071.34; when : "!A1&A2&!B1&Y"; } leakage_power () { @@ -1775,7 +1775,7 @@ library (sg13g2_stdcell_fast_1p65V_m40C) { when : "!A1&A2&B1&!Y"; } leakage_power () { - value : 412.01; + value : 412.011; when : "A1&!A2&!B1&Y"; } leakage_power () { @@ -1803,38 +1803,38 @@ library (sg13g2_stdcell_fast_1p65V_m40C) { index_1 ("0.0186, 0.0966, 0.174, 0.3294, 0.6408, 1.263, 2.5074"); index_2 ("0.001, 0.0234, 0.039, 0.0648, 0.108, 0.18, 0.3"); values ( \ - "0.0233197, 0.0845, 0.125745, 0.193723, 0.307475, 0.497195, 0.812621", \ - "0.0309903, 0.103007, 0.145652, 0.21423, 0.328172, 0.517635, 0.833643", \ - "0.0344842, 0.11651, 0.162229, 0.233126, 0.348012, 0.537702, 0.85351", \ - "0.039488, 0.137367, 0.188346, 0.265444, 0.385581, 0.577894, 0.893765", \ - "0.0450919, 0.166735, 0.227712, 0.31542, 0.447674, 0.651653, 0.974195", \ - "0.0475133, 0.206043, 0.280404, 0.386724, 0.542313, 0.76816, 1.11581", \ - "0.0475143, 0.251435, 0.348241, 0.480531, 0.670018, 0.941885, 1.33275" \ + "0.0233197, 0.0844946, 0.125741, 0.193761, 0.307475, 0.497195, 0.812621", \ + "0.0309903, 0.103007, 0.145651, 0.214232, 0.32816, 0.517759, 0.833598", \ + "0.0344841, 0.11651, 0.162229, 0.233126, 0.34801, 0.537699, 0.853266", \ + "0.0394879, 0.137367, 0.188345, 0.265444, 0.38558, 0.577893, 0.893872", \ + "0.0450919, 0.166734, 0.227711, 0.31542, 0.447674, 0.651652, 0.974182", \ + "0.0475132, 0.206043, 0.280404, 0.386724, 0.542312, 0.76816, 1.11581", \ + "0.0475142, 0.251435, 0.348241, 0.48053, 0.670018, 0.941884, 1.33531" \ ); } rise_transition (TIMING_DELAY_7x7ds1) { index_1 ("0.0186, 0.0966, 0.174, 0.3294, 0.6408, 1.263, 2.5074"); index_2 ("0.001, 0.0234, 0.039, 0.0648, 0.108, 0.18, 0.3"); values ( \ - "0.0147391, 0.100037, 0.160196, 0.259518, 0.425973, 0.703438, 1.16567", \ - "0.0256359, 0.106707, 0.164046, 0.26112, 0.428376, 0.703439, 1.16573", \ - "0.0356808, 0.117823, 0.173724, 0.26799, 0.429635, 0.704096, 1.16574", \ - "0.0534517, 0.139709, 0.196239, 0.288462, 0.445329, 0.712665, 1.17334", \ - "0.0824357, 0.180478, 0.239636, 0.333096, 0.488172, 0.747626, 1.1901", \ - "0.130416, 0.24956, 0.315434, 0.416129, 0.577771, 0.835321, 1.26618", \ - "0.214631, 0.368088, 0.444904, 0.561716, 0.738788, 1.01372, 1.44307" \ + "0.014739, 0.100026, 0.160132, 0.259584, 0.425973, 0.703437, 1.16567", \ + "0.0256359, 0.106707, 0.164046, 0.261111, 0.426168, 0.703438, 1.1657", \ + "0.0356808, 0.117823, 0.173723, 0.26799, 0.429625, 0.704093, 1.16571", \ + "0.0534516, 0.139709, 0.196239, 0.288462, 0.445329, 0.712663, 1.17097", \ + "0.0824356, 0.180478, 0.239636, 0.333096, 0.488171, 0.747626, 1.19009", \ + "0.130415, 0.249559, 0.315434, 0.416128, 0.57777, 0.835319, 1.26618", \ + "0.214631, 0.368087, 0.444904, 0.561717, 0.738788, 1.01372, 1.44524" \ ); } cell_fall (TIMING_DELAY_7x7ds1) { index_1 ("0.0186, 0.0966, 0.174, 0.3294, 0.6408, 1.263, 2.5074"); index_2 ("0.001, 0.0234, 0.039, 0.0648, 0.108, 0.18, 0.3"); values ( \ - "0.0221482, 0.0695606, 0.100961, 0.152756, 0.239347, 0.383376, 0.623384", \ - "0.0364739, 0.0991588, 0.133598, 0.186814, 0.273625, 0.417746, 0.657571", \ - "0.0459838, 0.120275, 0.159794, 0.218171, 0.308323, 0.453147, 0.693097", \ - "0.0601314, 0.151474, 0.198998, 0.267401, 0.368619, 0.522038, 0.765421", \ - "0.0786571, 0.193559, 0.251963, 0.335579, 0.456046, 0.631944, 0.894865", \ - "0.106198, 0.254834, 0.327253, 0.43042, 0.579764, 0.791113, 1.09877", \ + "0.0221482, 0.0695629, 0.101002, 0.152761, 0.239259, 0.383494, 0.623383", \ + "0.0364739, 0.0991314, 0.133598, 0.186814, 0.273657, 0.417746, 0.657632", \ + "0.0459838, 0.120275, 0.159794, 0.218171, 0.308323, 0.453147, 0.692974", \ + "0.0601314, 0.151474, 0.198998, 0.267401, 0.368619, 0.52204, 0.765413", \ + "0.0787019, 0.193559, 0.251963, 0.335579, 0.456046, 0.631944, 0.894865", \ + "0.106198, 0.254834, 0.327253, 0.43042, 0.579764, 0.791115, 1.09877", \ "0.148487, 0.341857, 0.43679, 0.56742, 0.75049, 1.01523, 1.38992" \ ); } @@ -1842,13 +1842,13 @@ library (sg13g2_stdcell_fast_1p65V_m40C) { index_1 ("0.0186, 0.0966, 0.174, 0.3294, 0.6408, 1.263, 2.5074"); index_2 ("0.001, 0.0234, 0.039, 0.0648, 0.108, 0.18, 0.3"); values ( \ - "0.0171326, 0.0782323, 0.122374, 0.194101, 0.315081, 0.516536, 0.852508", \ - "0.0302989, 0.0917012, 0.131735, 0.199502, 0.316798, 0.516751, 0.852509", \ - "0.0414842, 0.108102, 0.148709, 0.214593, 0.326865, 0.520823, 0.853325", \ - "0.0607485, 0.136576, 0.180644, 0.248992, 0.359143, 0.544997, 0.865496", \ - "0.093007, 0.186331, 0.235168, 0.309996, 0.426326, 0.61133, 0.919367", \ - "0.148111, 0.270171, 0.328406, 0.414188, 0.542708, 0.741616, 1.05377", \ - "0.244993, 0.417697, 0.490274, 0.591817, 0.742633, 0.963442, 1.30601" \ + "0.0171326, 0.0782287, 0.122367, 0.194131, 0.314848, 0.516496, 0.852507", \ + "0.0302989, 0.0916775, 0.13176, 0.199502, 0.316831, 0.51675, 0.852508", \ + "0.0414842, 0.108102, 0.148709, 0.214593, 0.326865, 0.520823, 0.853225", \ + "0.0607485, 0.136576, 0.180644, 0.248992, 0.359143, 0.544998, 0.865512", \ + "0.093002, 0.186331, 0.235168, 0.309996, 0.426327, 0.61133, 0.919366", \ + "0.148111, 0.270171, 0.328406, 0.414188, 0.542708, 0.741617, 1.05377", \ + "0.244993, 0.417696, 0.490274, 0.591817, 0.742633, 0.963442, 1.30601" \ ); } } @@ -1860,52 +1860,52 @@ library (sg13g2_stdcell_fast_1p65V_m40C) { index_1 ("0.0186, 0.0966, 0.174, 0.3294, 0.6408, 1.263, 2.5074"); index_2 ("0.001, 0.0234, 0.039, 0.0648, 0.108, 0.18, 0.3"); values ( \ - "0.0277346, 0.0883106, 0.129698, 0.197926, 0.312217, 0.502876, 0.819877", \ - "0.037747, 0.10738, 0.149917, 0.218604, 0.332952, 0.523356, 0.840942", \ - "0.0431186, 0.121612, 0.167034, 0.23773, 0.352987, 0.54336, 0.860755", \ - "0.0526424, 0.144083, 0.194204, 0.270718, 0.390947, 0.583535, 0.900779", \ - "0.0668182, 0.177315, 0.236142, 0.323383, 0.454637, 0.658028, 0.981332", \ - "0.0856537, 0.226208, 0.296971, 0.399113, 0.552412, 0.776384, 1.12335", \ - "0.111103, 0.294771, 0.384331, 0.509296, 0.692164, 0.95574, 1.34737" \ + "0.0277331, 0.0883095, 0.129702, 0.197922, 0.312218, 0.502877, 0.820048", \ + "0.0377469, 0.10738, 0.149917, 0.218604, 0.332949, 0.523353, 0.84093", \ + "0.0431186, 0.121628, 0.167034, 0.23775, 0.352986, 0.543369, 0.860721", \ + "0.0526423, 0.144083, 0.194204, 0.270716, 0.390947, 0.583529, 0.900793", \ + "0.0668181, 0.177315, 0.236142, 0.323382, 0.454637, 0.658028, 0.981331", \ + "0.0856535, 0.226207, 0.296971, 0.399113, 0.552411, 0.776383, 1.12335", \ + "0.111103, 0.29477, 0.38433, 0.509295, 0.692164, 0.955739, 1.34736" \ ); } rise_transition (TIMING_DELAY_7x7ds1) { index_1 ("0.0186, 0.0966, 0.174, 0.3294, 0.6408, 1.263, 2.5074"); index_2 ("0.001, 0.0234, 0.039, 0.0648, 0.108, 0.18, 0.3"); values ( \ - "0.0193273, 0.105804, 0.166149, 0.265998, 0.433456, 0.712485, 1.17725", \ - "0.029911, 0.111955, 0.169799, 0.267585, 0.433648, 0.712486, 1.17726", \ - "0.0395019, 0.122723, 0.17928, 0.274283, 0.437046, 0.713129, 1.17736", \ - "0.056393, 0.144679, 0.201276, 0.294316, 0.452473, 0.721562, 1.18493", \ - "0.0839723, 0.183462, 0.243187, 0.339468, 0.49531, 0.755978, 1.20099", \ - "0.131115, 0.250824, 0.318503, 0.42052, 0.583099, 0.842656, 1.27626", \ - "0.210503, 0.36438, 0.44336, 0.560769, 0.73827, 1.01173, 1.45177" \ + "0.0193277, 0.105804, 0.166149, 0.265992, 0.433456, 0.712485, 1.17739", \ + "0.0299109, 0.111954, 0.169799, 0.267718, 0.433644, 0.712486, 1.1774", \ + "0.039502, 0.12275, 0.179278, 0.274347, 0.437045, 0.713138, 1.17741", \ + "0.0563931, 0.144679, 0.201275, 0.294322, 0.452472, 0.721682, 1.18513", \ + "0.0839723, 0.183462, 0.243186, 0.339467, 0.495309, 0.755978, 1.20099", \ + "0.131115, 0.250823, 0.318503, 0.42052, 0.583098, 0.842655, 1.27626", \ + "0.210503, 0.364381, 0.443359, 0.56077, 0.738271, 1.01173, 1.45176" \ ); } cell_fall (TIMING_DELAY_7x7ds1) { index_1 ("0.0186, 0.0966, 0.174, 0.3294, 0.6408, 1.263, 2.5074"); index_2 ("0.001, 0.0234, 0.039, 0.0648, 0.108, 0.18, 0.3"); values ( \ - "0.0232639, 0.0702535, 0.101661, 0.153447, 0.239934, 0.384178, 0.624092", \ - "0.0341101, 0.0911314, 0.124512, 0.177315, 0.264149, 0.408259, 0.648326", \ - "0.0409375, 0.107284, 0.143744, 0.199592, 0.288572, 0.433352, 0.673511", \ + "0.0232637, 0.0702461, 0.101688, 0.153441, 0.239936, 0.384182, 0.624077", \ + "0.0341101, 0.0911314, 0.124512, 0.177315, 0.264149, 0.408293, 0.648271", \ + "0.0409375, 0.107284, 0.143744, 0.199592, 0.288572, 0.43335, 0.673494", \ "0.0504486, 0.131654, 0.174203, 0.236186, 0.331878, 0.48178, 0.724114", \ - "0.0611595, 0.16465, 0.215557, 0.289656, 0.397721, 0.561778, 0.815399", \ - "0.0734606, 0.207962, 0.273606, 0.363704, 0.49482, 0.684567, 0.96541", \ - "0.0856237, 0.261966, 0.348833, 0.466132, 0.629641, 0.859829, 1.19318" \ + "0.0611595, 0.16465, 0.215557, 0.289656, 0.397721, 0.561777, 0.815398", \ + "0.0734606, 0.207962, 0.273606, 0.363704, 0.49482, 0.684567, 0.965438", \ + "0.0856238, 0.261966, 0.348832, 0.466132, 0.629641, 0.859829, 1.19318" \ ); } fall_transition (TIMING_DELAY_7x7ds1) { index_1 ("0.0186, 0.0966, 0.174, 0.3294, 0.6408, 1.263, 2.5074"); index_2 ("0.001, 0.0234, 0.039, 0.0648, 0.108, 0.18, 0.3"); values ( \ - "0.016268, 0.0781756, 0.121773, 0.19403, 0.314925, 0.516536, 0.851907", \ - "0.0266162, 0.086458, 0.127633, 0.197228, 0.316034, 0.517429, 0.852438", \ - "0.0374816, 0.0974933, 0.138638, 0.206257, 0.322095, 0.519157, 0.852923", \ - "0.0565776, 0.120825, 0.161636, 0.229123, 0.341865, 0.533308, 0.859887", \ - "0.0877304, 0.163587, 0.206221, 0.27533, 0.388189, 0.575348, 0.892015", \ - "0.140371, 0.241898, 0.288626, 0.362982, 0.479045, 0.667586, 0.980635", \ - "0.231682, 0.373772, 0.437071, 0.521657, 0.649147, 0.845446, 1.16438" \ + "0.0162652, 0.0781623, 0.122299, 0.194116, 0.314927, 0.516536, 0.851906", \ + "0.0266162, 0.0864579, 0.127633, 0.197314, 0.316034, 0.516554, 0.852394", \ + "0.0374815, 0.0974933, 0.138638, 0.206254, 0.322095, 0.518985, 0.852893", \ + "0.0565776, 0.120825, 0.161636, 0.229123, 0.341864, 0.533308, 0.859837", \ + "0.0877304, 0.163587, 0.206221, 0.27533, 0.388189, 0.575347, 0.892015", \ + "0.140371, 0.241898, 0.288626, 0.362981, 0.479045, 0.667585, 0.979792", \ + "0.231683, 0.373772, 0.437071, 0.521657, 0.649147, 0.845446, 1.16438" \ ); } } @@ -1919,38 +1919,38 @@ library (sg13g2_stdcell_fast_1p65V_m40C) { index_1 ("0.0186, 0.0966, 0.174, 0.3294, 0.6408, 1.263, 2.5074"); index_2 ("0.001, 0.0234, 0.039, 0.0648, 0.108, 0.18, 0.3"); values ( \ - "0.0234169, 0.084875, 0.126385, 0.194819, 0.30918, 0.499646, 0.817128", \ - "0.0386791, 0.11371, 0.156832, 0.225606, 0.339841, 0.530158, 0.847815", \ - "0.048307, 0.135686, 0.183361, 0.255444, 0.370797, 0.560933, 0.877792", \ - "0.063824, 0.168827, 0.224753, 0.306311, 0.429769, 0.623571, 0.940373", \ - "0.0886772, 0.217941, 0.28562, 0.382439, 0.52487, 0.737372, 1.06506", \ - "0.128101, 0.290282, 0.373719, 0.493302, 0.664633, 0.914265, 1.28235", \ - "0.193338, 0.402326, 0.5055, 0.654166, 0.868293, 1.17196, 1.60716" \ + "0.0234168, 0.0848981, 0.126422, 0.194819, 0.309179, 0.499639, 0.817269", \ + "0.0386791, 0.11371, 0.156832, 0.225603, 0.339858, 0.530145, 0.848097", \ + "0.0483069, 0.135688, 0.183361, 0.255444, 0.370755, 0.560859, 0.87779", \ + "0.0638239, 0.168827, 0.224753, 0.306311, 0.429769, 0.623565, 0.940372", \ + "0.0886771, 0.21794, 0.285294, 0.382439, 0.524869, 0.737372, 1.06506", \ + "0.128101, 0.290282, 0.373719, 0.493301, 0.664632, 0.914264, 1.28235", \ + "0.193338, 0.402326, 0.505499, 0.654165, 0.868292, 1.17195, 1.60716" \ ); } rise_transition (TIMING_DELAY_7x7ds1) { index_1 ("0.0186, 0.0966, 0.174, 0.3294, 0.6408, 1.263, 2.5074"); index_2 ("0.001, 0.0234, 0.039, 0.0648, 0.108, 0.18, 0.3"); values ( \ - "0.0201601, 0.105687, 0.16612, 0.266094, 0.433463, 0.712153, 1.17758", \ - "0.0322478, 0.116111, 0.172444, 0.268584, 0.434187, 0.712226, 1.17759", \ - "0.0411438, 0.131769, 0.187347, 0.279732, 0.439427, 0.713474, 1.1776", \ - "0.056074, 0.159302, 0.218279, 0.310423, 0.464309, 0.727615, 1.18812", \ - "0.0817699, 0.204025, 0.270855, 0.370652, 0.527378, 0.782801, 1.21691", \ - "0.12732, 0.275335, 0.353678, 0.468129, 0.642408, 0.907371, 1.3349", \ - "0.210043, 0.393118, 0.488044, 0.624347, 0.82657, 1.12567, 1.58004" \ + "0.0201609, 0.105598, 0.166154, 0.266093, 0.433462, 0.712149, 1.17731", \ + "0.0322478, 0.116111, 0.172444, 0.268669, 0.434193, 0.712235, 1.17751", \ + "0.0411438, 0.131767, 0.187347, 0.279732, 0.439387, 0.713461, 1.17752", \ + "0.0560739, 0.159302, 0.218279, 0.310422, 0.464309, 0.727614, 1.1881", \ + "0.0817772, 0.204025, 0.270176, 0.370652, 0.527378, 0.782925, 1.21687", \ + "0.12732, 0.275334, 0.353678, 0.468128, 0.642407, 0.90737, 1.3349", \ + "0.210043, 0.393118, 0.488045, 0.624348, 0.826569, 1.12567, 1.58003" \ ); } cell_fall (TIMING_DELAY_7x7ds1) { index_1 ("0.0186, 0.0966, 0.174, 0.3294, 0.6408, 1.263, 2.5074"); index_2 ("0.001, 0.0234, 0.039, 0.0648, 0.108, 0.18, 0.3"); values ( \ - "0.0126082, 0.041712, 0.0595089, 0.0887064, 0.137569, 0.218372, 0.353042", \ - "0.0199988, 0.0685698, 0.0917677, 0.125238, 0.176227, 0.2577, 0.392334", \ - "0.0236176, 0.0852969, 0.113667, 0.153244, 0.210536, 0.296473, 0.432556", \ - "0.0273876, 0.108003, 0.144357, 0.194059, 0.26351, 0.362275, 0.508985", \ - "0.0276326, 0.133549, 0.18103, 0.245665, 0.334581, 0.456551, 0.629493", \ - "0.0276336, 0.158345, 0.223146, 0.308993, 0.424899, 0.584339, 0.800877", \ + "0.0126082, 0.0417131, 0.0595115, 0.0887119, 0.137592, 0.21838, 0.353041", \ + "0.0199988, 0.0685698, 0.0917677, 0.125238, 0.176227, 0.257701, 0.392326", \ + "0.0236176, 0.0852969, 0.113667, 0.153244, 0.210534, 0.296473, 0.43255", \ + "0.0273876, 0.108003, 0.144358, 0.194059, 0.26351, 0.362275, 0.508985", \ + "0.0276326, 0.133549, 0.18103, 0.245665, 0.334581, 0.456552, 0.629493", \ + "0.0276336, 0.158345, 0.223146, 0.308994, 0.424899, 0.584339, 0.800877", \ "0.0276346, 0.16964, 0.258006, 0.376222, 0.533984, 0.742356, 1.02898" \ ); } @@ -1958,13 +1958,13 @@ library (sg13g2_stdcell_fast_1p65V_m40C) { index_1 ("0.0186, 0.0966, 0.174, 0.3294, 0.6408, 1.263, 2.5074"); index_2 ("0.001, 0.0234, 0.039, 0.0648, 0.108, 0.18, 0.3"); values ( \ - "0.0111526, 0.0440165, 0.0680948, 0.108575, 0.176895, 0.290586, 0.480126", \ - "0.0260377, 0.061662, 0.0841088, 0.120661, 0.183662, 0.29309, 0.481481", \ - "0.0378012, 0.0779931, 0.102219, 0.139796, 0.200918, 0.305091, 0.485963", \ - "0.0580884, 0.106986, 0.133747, 0.175023, 0.238835, 0.341386, 0.513872", \ - "0.0918334, 0.156066, 0.188532, 0.235464, 0.307008, 0.416192, 0.588019", \ - "0.148777, 0.239869, 0.279991, 0.336799, 0.422429, 0.54373, 0.733343", \ - "0.247887, 0.380612, 0.439018, 0.512763, 0.61425, 0.765927, 0.977567" \ + "0.0111526, 0.0440175, 0.0680955, 0.108581, 0.176936, 0.290586, 0.480126", \ + "0.0260377, 0.061662, 0.0841089, 0.120661, 0.183662, 0.293036, 0.480912", \ + "0.0378008, 0.077993, 0.102219, 0.139796, 0.200873, 0.305092, 0.485962", \ + "0.0580885, 0.106986, 0.133747, 0.175023, 0.238835, 0.341386, 0.513697", \ + "0.0918333, 0.156066, 0.188532, 0.235464, 0.307008, 0.416168, 0.588018", \ + "0.148777, 0.239868, 0.279991, 0.336799, 0.422429, 0.54373, 0.733344", \ + "0.247887, 0.380611, 0.439018, 0.512764, 0.61425, 0.765927, 0.977567" \ ); } } @@ -1978,52 +1978,52 @@ library (sg13g2_stdcell_fast_1p65V_m40C) { index_1 ("0.0186, 0.0966, 0.174, 0.3294, 0.6408, 1.263, 2.5074"); index_2 ("0.001, 0.0234, 0.039, 0.0648, 0.108, 0.18, 0.3"); values ( \ - "0.0182347, 0.0797292, 0.121013, 0.189087, 0.302942, 0.492402, 0.807817", \ - "0.030396, 0.108144, 0.151326, 0.219813, 0.333473, 0.522979, 0.838467", \ - "0.0383874, 0.129391, 0.177354, 0.249509, 0.364374, 0.553657, 0.868884", \ - "0.0515736, 0.161638, 0.217662, 0.299637, 0.423153, 0.616192, 0.93158", \ - "0.0725257, 0.208672, 0.27705, 0.374141, 0.517507, 0.729564, 1.05593", \ - "0.107036, 0.27864, 0.363699, 0.483671, 0.655333, 0.905735, 1.27198", \ - "0.165852, 0.387319, 0.492293, 0.641777, 0.855873, 1.16076, 1.595" \ + "0.0182347, 0.0797292, 0.12103, 0.189082, 0.302941, 0.492398, 0.808191", \ + "0.0303959, 0.108144, 0.151325, 0.219817, 0.333479, 0.523003, 0.838468", \ + "0.0383874, 0.129391, 0.177354, 0.249509, 0.364373, 0.553719, 0.868883", \ + "0.0515735, 0.161637, 0.217662, 0.299637, 0.423152, 0.616255, 0.93158", \ + "0.0725256, 0.208672, 0.277049, 0.374141, 0.517506, 0.729564, 1.05592", \ + "0.107036, 0.27864, 0.363699, 0.483671, 0.655333, 0.905741, 1.27198", \ + "0.165852, 0.387319, 0.492293, 0.641777, 0.855873, 1.16077, 1.595" \ ); } rise_transition (TIMING_DELAY_7x7ds1) { index_1 ("0.0186, 0.0966, 0.174, 0.3294, 0.6408, 1.263, 2.5074"); index_2 ("0.001, 0.0234, 0.039, 0.0648, 0.108, 0.18, 0.3"); values ( \ - "0.0160134, 0.100023, 0.160112, 0.259549, 0.425982, 0.703153, 1.16519", \ - "0.0272534, 0.111216, 0.166922, 0.26228, 0.426311, 0.703371, 1.1653", \ - "0.0352145, 0.127038, 0.182174, 0.273726, 0.432138, 0.704707, 1.16595", \ - "0.0494381, 0.154216, 0.213097, 0.304796, 0.457604, 0.719019, 1.17334", \ - "0.0745673, 0.198094, 0.264112, 0.364727, 0.521153, 0.774674, 1.20583", \ - "0.119299, 0.26991, 0.348918, 0.462472, 0.635254, 0.899738, 1.32493", \ - "0.201489, 0.385785, 0.480072, 0.617978, 0.819021, 1.11691, 1.56942" \ + "0.0160134, 0.100023, 0.16013, 0.259541, 0.425982, 0.703153, 1.166", \ + "0.0272534, 0.111216, 0.166915, 0.262286, 0.426317, 0.703383, 1.16601", \ + "0.0352145, 0.127038, 0.182173, 0.273725, 0.432141, 0.70485, 1.16602", \ + "0.049438, 0.154216, 0.213097, 0.304796, 0.457604, 0.719058, 1.17334", \ + "0.0745698, 0.198093, 0.264111, 0.364727, 0.521151, 0.774599, 1.20584", \ + "0.119299, 0.26991, 0.348918, 0.462472, 0.635256, 0.899738, 1.32493", \ + "0.201488, 0.385785, 0.480072, 0.617978, 0.81902, 1.11691, 1.56942" \ ); } cell_fall (TIMING_DELAY_7x7ds1) { index_1 ("0.0186, 0.0966, 0.174, 0.3294, 0.6408, 1.263, 2.5074"); index_2 ("0.001, 0.0234, 0.039, 0.0648, 0.108, 0.18, 0.3"); values ( \ - "0.0122352, 0.0412475, 0.0588761, 0.0878719, 0.136433, 0.2172, 0.351885", \ - "0.0187735, 0.0677375, 0.0908747, 0.124253, 0.1751, 0.25647, 0.391169", \ + "0.0122349, 0.0412481, 0.0588751, 0.0878694, 0.136452, 0.217195, 0.351882", \ + "0.0187735, 0.0677375, 0.0908748, 0.124253, 0.1751, 0.256471, 0.391169", \ "0.0214144, 0.0840269, 0.112494, 0.152014, 0.209255, 0.295203, 0.43134", \ - "0.0227312, 0.105944, 0.142433, 0.192391, 0.26192, 0.360842, 0.50781", \ - "0.0227322, 0.130029, 0.17817, 0.243172, 0.332693, 0.454896, 0.628078", \ - "0.0227332, 0.152501, 0.218608, 0.305807, 0.422112, 0.582415, 0.79911", \ - "0.0227342, 0.160987, 0.251569, 0.371414, 0.530446, 0.739776, 1.02688" \ + "0.0227313, 0.105944, 0.142433, 0.192391, 0.26192, 0.360842, 0.50781", \ + "0.0227323, 0.130029, 0.178171, 0.243172, 0.332693, 0.454896, 0.628078", \ + "0.0227333, 0.152501, 0.218608, 0.305807, 0.422112, 0.582416, 0.799111", \ + "0.0227343, 0.160987, 0.251569, 0.371414, 0.530446, 0.739776, 1.02688" \ ); } fall_transition (TIMING_DELAY_7x7ds1) { index_1 ("0.0186, 0.0966, 0.174, 0.3294, 0.6408, 1.263, 2.5074"); index_2 ("0.001, 0.0234, 0.039, 0.0648, 0.108, 0.18, 0.3"); values ( \ - "0.00785379, 0.0411285, 0.0652303, 0.105721, 0.174017, 0.28778, 0.477433", \ - "0.0193686, 0.0583146, 0.0811491, 0.117826, 0.180893, 0.290252, 0.478644", \ - "0.0287326, 0.0742202, 0.098838, 0.136712, 0.198058, 0.302226, 0.48322", \ - "0.0452059, 0.10202, 0.129872, 0.171846, 0.23605, 0.338477, 0.51115", \ - "0.073677, 0.149675, 0.182974, 0.231766, 0.303104, 0.412884, 0.585141", \ - "0.122875, 0.231395, 0.273648, 0.331481, 0.416774, 0.540925, 0.72976", \ - "0.214206, 0.367498, 0.428859, 0.504811, 0.607451, 0.758111, 0.973839" \ + "0.00785401, 0.0411318, 0.065231, 0.105972, 0.174064, 0.28778, 0.477434", \ + "0.0193686, 0.0583146, 0.081149, 0.117827, 0.180893, 0.290288, 0.478645", \ + "0.0287326, 0.0742203, 0.098838, 0.136712, 0.198058, 0.302226, 0.48322", \ + "0.0452059, 0.10202, 0.129872, 0.171846, 0.23605, 0.338477, 0.511151", \ + "0.0736769, 0.149675, 0.182974, 0.231766, 0.303105, 0.412884, 0.585141", \ + "0.122877, 0.231395, 0.273648, 0.331481, 0.416775, 0.540925, 0.729759", \ + "0.214207, 0.367499, 0.42886, 0.504809, 0.607451, 0.758111, 0.973838" \ ); } } @@ -2037,52 +2037,52 @@ library (sg13g2_stdcell_fast_1p65V_m40C) { index_1 ("0.0186, 0.0966, 0.174, 0.3294, 0.6408, 1.263, 2.5074"); index_2 ("0.001, 0.0234, 0.039, 0.0648, 0.108, 0.18, 0.3"); values ( \ - "0.0154512, 0.0620022, 0.0927659, 0.143487, 0.228215, 0.369454, 0.604449", \ - "0.0259492, 0.0908775, 0.12487, 0.177047, 0.26204, 0.403167, 0.638352", \ - "0.0325066, 0.110254, 0.149523, 0.206861, 0.294982, 0.436567, 0.671704", \ - "0.0425285, 0.1387, 0.186011, 0.253873, 0.353059, 0.502441, 0.739566", \ - "0.0574524, 0.178408, 0.237909, 0.321488, 0.440197, 0.612226, 0.867901", \ - "0.0801489, 0.235186, 0.309644, 0.414986, 0.563911, 0.772176, 1.07238", \ - "0.11691, 0.319181, 0.413308, 0.544272, 0.732474, 0.997392, 1.36497" \ + "0.0154504, 0.0620022, 0.0927621, 0.143487, 0.228214, 0.369415, 0.604448", \ + "0.0259492, 0.0908774, 0.12487, 0.177041, 0.26204, 0.40309, 0.638349", \ + "0.0325066, 0.110253, 0.149523, 0.206861, 0.295009, 0.436568, 0.671729", \ + "0.0425284, 0.1387, 0.186011, 0.253873, 0.353059, 0.502441, 0.739561", \ + "0.0574523, 0.178408, 0.237909, 0.321488, 0.440197, 0.612226, 0.8679", \ + "0.0801488, 0.235186, 0.309643, 0.414985, 0.563912, 0.772175, 1.07238", \ + "0.11691, 0.319181, 0.413308, 0.544271, 0.732473, 0.997391, 1.36497" \ ); } rise_transition (TIMING_DELAY_7x7ds1) { index_1 ("0.0186, 0.0966, 0.174, 0.3294, 0.6408, 1.263, 2.5074"); index_2 ("0.001, 0.0234, 0.039, 0.0648, 0.108, 0.18, 0.3"); values ( \ - "0.012614, 0.0748594, 0.120458, 0.19509, 0.32051, 0.529717, 0.878155", \ - "0.0240979, 0.0890528, 0.130138, 0.200297, 0.322187, 0.530253, 0.878188", \ - "0.0322116, 0.105437, 0.14724, 0.21519, 0.331769, 0.533622, 0.878811", \ - "0.0465999, 0.132697, 0.179086, 0.249474, 0.363315, 0.555542, 0.888982", \ - "0.0718759, 0.1761, 0.230876, 0.310517, 0.431139, 0.621484, 0.939373", \ - "0.11645, 0.246567, 0.311487, 0.407224, 0.546159, 0.753041, 1.07516", \ - "0.19991, 0.36247, 0.442558, 0.562568, 0.726716, 0.97124, 1.329" \ + "0.0126145, 0.074857, 0.120166, 0.19509, 0.320509, 0.529759, 0.878153", \ + "0.0240978, 0.0890528, 0.130138, 0.200266, 0.322188, 0.529805, 0.878216", \ + "0.0322116, 0.10541, 0.14724, 0.215191, 0.331796, 0.533629, 0.878841", \ + "0.0465998, 0.132697, 0.179086, 0.249473, 0.363314, 0.555541, 0.888923", \ + "0.0718759, 0.1761, 0.230876, 0.310517, 0.431138, 0.621484, 0.939372", \ + "0.11645, 0.246566, 0.311467, 0.407225, 0.54616, 0.753041, 1.07516", \ + "0.199909, 0.362469, 0.442558, 0.562567, 0.726715, 0.971239, 1.329" \ ); } cell_fall (TIMING_DELAY_7x7ds1) { index_1 ("0.0186, 0.0966, 0.174, 0.3294, 0.6408, 1.263, 2.5074"); index_2 ("0.001, 0.0234, 0.039, 0.0648, 0.108, 0.18, 0.3"); values ( \ - "0.0119961, 0.0410744, 0.058717, 0.0877036, 0.136212, 0.217043, 0.351724", \ - "0.0190271, 0.0676059, 0.0906787, 0.124081, 0.174928, 0.256309, 0.390993", \ + "0.0119959, 0.041074, 0.0587192, 0.0877115, 0.136214, 0.217046, 0.351723", \ + "0.0190271, 0.067606, 0.0906787, 0.124081, 0.174928, 0.256326, 0.390999", \ "0.0225297, 0.0841178, 0.112377, 0.151911, 0.209147, 0.295076, 0.431206", \ - "0.0259967, 0.106848, 0.142996, 0.19263, 0.261884, 0.360895, 0.507696", \ - "0.0259977, 0.133656, 0.180725, 0.244741, 0.333458, 0.455594, 0.628521", \ - "0.0259987, 0.163246, 0.226949, 0.311972, 0.426446, 0.584839, 0.800954", \ - "0.0259997, 0.188281, 0.274868, 0.390761, 0.545028, 0.750298, 1.03346" \ + "0.0259968, 0.106848, 0.142996, 0.19263, 0.261884, 0.360895, 0.507696", \ + "0.0259978, 0.133656, 0.180725, 0.244741, 0.333458, 0.455594, 0.628522", \ + "0.0259988, 0.163246, 0.226949, 0.311972, 0.426446, 0.584839, 0.800954", \ + "0.0259998, 0.188281, 0.274868, 0.390761, 0.545028, 0.750298, 1.03346" \ ); } fall_transition (TIMING_DELAY_7x7ds1) { index_1 ("0.0186, 0.0966, 0.174, 0.3294, 0.6408, 1.263, 2.5074"); index_2 ("0.001, 0.0234, 0.039, 0.0648, 0.108, 0.18, 0.3"); values ( \ - "0.00797866, 0.0411559, 0.0652392, 0.105826, 0.174016, 0.287779, 0.477433", \ - "0.0194484, 0.0584406, 0.0812195, 0.117889, 0.180892, 0.290299, 0.478167", \ - "0.0287482, 0.0741189, 0.098892, 0.13677, 0.198118, 0.302208, 0.483307", \ - "0.0451098, 0.101456, 0.129535, 0.171694, 0.236081, 0.338496, 0.511163", \ - "0.0732882, 0.14773, 0.181665, 0.230789, 0.302367, 0.412459, 0.584918", \ - "0.122375, 0.227384, 0.269227, 0.328067, 0.41526, 0.539329, 0.729067", \ - "0.214018, 0.359711, 0.420234, 0.497403, 0.599767, 0.752001, 0.970855" \ + "0.00797878, 0.0411582, 0.0652393, 0.105818, 0.174019, 0.287779, 0.477433", \ + "0.0194484, 0.0584406, 0.0812195, 0.117889, 0.180892, 0.290271, 0.478094", \ + "0.0287482, 0.0741189, 0.098892, 0.13677, 0.198118, 0.302206, 0.483307", \ + "0.0451099, 0.101456, 0.129535, 0.171694, 0.236081, 0.338496, 0.511163", \ + "0.0732882, 0.14773, 0.181665, 0.230789, 0.302367, 0.41246, 0.584921", \ + "0.122377, 0.227384, 0.269228, 0.328067, 0.41526, 0.53933, 0.729067", \ + "0.214017, 0.359711, 0.420235, 0.497402, 0.599768, 0.752002, 0.970856" \ ); } } @@ -2094,52 +2094,52 @@ library (sg13g2_stdcell_fast_1p65V_m40C) { index_1 ("0.0186, 0.0966, 0.174, 0.3294, 0.6408, 1.263, 2.5074"); index_2 ("0.001, 0.0234, 0.039, 0.0648, 0.108, 0.18, 0.3"); values ( \ - "0.0234169, 0.084875, 0.126385, 0.194819, 0.30918, 0.499646, 0.817128", \ - "0.0386791, 0.11371, 0.156832, 0.225606, 0.339841, 0.530158, 0.847815", \ - "0.048307, 0.135686, 0.183361, 0.255444, 0.370797, 0.560933, 0.877792", \ - "0.063824, 0.168827, 0.224753, 0.306311, 0.429769, 0.623571, 0.940373", \ - "0.0886772, 0.217941, 0.28562, 0.382439, 0.52487, 0.737372, 1.06506", \ - "0.128101, 0.290282, 0.373719, 0.493302, 0.664633, 0.914265, 1.28235", \ - "0.193338, 0.402326, 0.5055, 0.654166, 0.868293, 1.17196, 1.60716" \ + "0.0234168, 0.0848981, 0.126422, 0.194819, 0.309179, 0.499639, 0.817269", \ + "0.0386791, 0.11371, 0.156832, 0.225603, 0.339858, 0.530145, 0.848097", \ + "0.0483069, 0.135688, 0.183361, 0.255444, 0.370755, 0.560859, 0.87779", \ + "0.0638239, 0.168827, 0.224753, 0.306311, 0.429769, 0.623565, 0.940372", \ + "0.0886771, 0.21794, 0.285294, 0.382439, 0.524869, 0.737372, 1.06506", \ + "0.128101, 0.290282, 0.373719, 0.493301, 0.664632, 0.914264, 1.28235", \ + "0.193338, 0.402326, 0.505499, 0.654165, 0.868292, 1.17195, 1.60716" \ ); } rise_transition (TIMING_DELAY_7x7ds1) { index_1 ("0.0186, 0.0966, 0.174, 0.3294, 0.6408, 1.263, 2.5074"); index_2 ("0.001, 0.0234, 0.039, 0.0648, 0.108, 0.18, 0.3"); values ( \ - "0.0201601, 0.105687, 0.16612, 0.266094, 0.433463, 0.712153, 1.17758", \ - "0.0322478, 0.116111, 0.172444, 0.268584, 0.434187, 0.712226, 1.17759", \ - "0.0411438, 0.131769, 0.187347, 0.279732, 0.439427, 0.713474, 1.1776", \ - "0.056074, 0.159302, 0.218279, 0.310423, 0.464309, 0.727615, 1.18812", \ - "0.0817699, 0.204025, 0.270855, 0.370652, 0.527378, 0.782801, 1.21691", \ - "0.12732, 0.275335, 0.353678, 0.468129, 0.642408, 0.907371, 1.3349", \ - "0.210043, 0.393118, 0.488044, 0.624347, 0.82657, 1.12567, 1.58004" \ + "0.0201609, 0.105598, 0.166154, 0.266093, 0.433462, 0.712149, 1.17731", \ + "0.0322478, 0.116111, 0.172444, 0.268669, 0.434193, 0.712235, 1.17751", \ + "0.0411438, 0.131767, 0.187347, 0.279732, 0.439387, 0.713461, 1.17752", \ + "0.0560739, 0.159302, 0.218279, 0.310422, 0.464309, 0.727614, 1.1881", \ + "0.0817772, 0.204025, 0.270176, 0.370652, 0.527378, 0.782925, 1.21687", \ + "0.12732, 0.275334, 0.353678, 0.468128, 0.642407, 0.90737, 1.3349", \ + "0.210043, 0.393118, 0.488045, 0.624348, 0.826569, 1.12567, 1.58003" \ ); } cell_fall (TIMING_DELAY_7x7ds1) { index_1 ("0.0186, 0.0966, 0.174, 0.3294, 0.6408, 1.263, 2.5074"); index_2 ("0.001, 0.0234, 0.039, 0.0648, 0.108, 0.18, 0.3"); values ( \ - "0.0119961, 0.0410744, 0.058717, 0.0877036, 0.136212, 0.217043, 0.351724", \ - "0.0190271, 0.0676059, 0.0906787, 0.124081, 0.174928, 0.256309, 0.390993", \ + "0.0119959, 0.041074, 0.0587192, 0.0877115, 0.136214, 0.217046, 0.351723", \ + "0.0190271, 0.067606, 0.0906787, 0.124081, 0.174928, 0.256326, 0.390999", \ "0.0225297, 0.0841178, 0.112377, 0.151911, 0.209147, 0.295076, 0.431206", \ - "0.0259967, 0.106848, 0.142996, 0.19263, 0.261884, 0.360895, 0.507696", \ - "0.0259977, 0.133656, 0.180725, 0.244741, 0.333458, 0.455594, 0.628521", \ - "0.0259987, 0.163246, 0.226949, 0.311972, 0.426446, 0.584839, 0.800954", \ - "0.0259997, 0.188281, 0.274868, 0.390761, 0.545028, 0.750298, 1.03346" \ + "0.0259968, 0.106848, 0.142996, 0.19263, 0.261884, 0.360895, 0.507696", \ + "0.0259978, 0.133656, 0.180725, 0.244741, 0.333458, 0.455594, 0.628522", \ + "0.0259988, 0.163246, 0.226949, 0.311972, 0.426446, 0.584839, 0.800954", \ + "0.0259998, 0.188281, 0.274868, 0.390761, 0.545028, 0.750298, 1.03346" \ ); } fall_transition (TIMING_DELAY_7x7ds1) { index_1 ("0.0186, 0.0966, 0.174, 0.3294, 0.6408, 1.263, 2.5074"); index_2 ("0.001, 0.0234, 0.039, 0.0648, 0.108, 0.18, 0.3"); values ( \ - "0.00797866, 0.0411559, 0.0652392, 0.105826, 0.174016, 0.287779, 0.477433", \ - "0.0194484, 0.0584406, 0.0812195, 0.117889, 0.180892, 0.290299, 0.478167", \ - "0.0287482, 0.0741189, 0.098892, 0.13677, 0.198118, 0.302208, 0.483307", \ - "0.0451098, 0.101456, 0.129535, 0.171694, 0.236081, 0.338496, 0.511163", \ - "0.0732882, 0.14773, 0.181665, 0.230789, 0.302367, 0.412459, 0.584918", \ - "0.122375, 0.227384, 0.269227, 0.328067, 0.41526, 0.539329, 0.729067", \ - "0.214018, 0.359711, 0.420234, 0.497403, 0.599767, 0.752001, 0.970855" \ + "0.00797878, 0.0411582, 0.0652393, 0.105818, 0.174019, 0.287779, 0.477433", \ + "0.0194484, 0.0584406, 0.0812195, 0.117889, 0.180892, 0.290271, 0.478094", \ + "0.0287482, 0.0741189, 0.098892, 0.13677, 0.198118, 0.302206, 0.483307", \ + "0.0451099, 0.101456, 0.129535, 0.171694, 0.236081, 0.338496, 0.511163", \ + "0.0732882, 0.14773, 0.181665, 0.230789, 0.302367, 0.41246, 0.584921", \ + "0.122377, 0.227384, 0.269228, 0.328067, 0.41526, 0.53933, 0.729067", \ + "0.214017, 0.359711, 0.420235, 0.497402, 0.599768, 0.752002, 0.970856" \ ); } } @@ -2149,26 +2149,26 @@ library (sg13g2_stdcell_fast_1p65V_m40C) { index_1 ("0.0186, 0.0966, 0.174, 0.3294, 0.6408, 1.263, 2.5074"); index_2 ("0.001, 0.0234, 0.039, 0.0648, 0.108, 0.18, 0.3"); values ( \ - "0.00845739, 0.00933201, 0.00936946, 0.00930743, 0.00911644, 0.00878634, 0.00814405", \ - "0.00916568, 0.0090802, 0.0091918, 0.00919118, 0.00928593, 0.00857975, 0.00809186", \ - "0.0113601, 0.00997773, 0.00974087, 0.0096465, 0.00947962, 0.00878558, 0.00821103", \ - "0.0170366, 0.0132809, 0.0124053, 0.0115197, 0.0111236, 0.00979702, 0.00952135", \ - "0.0292626, 0.0225887, 0.0205359, 0.0181955, 0.0158529, 0.014187, 0.0118762", \ - "0.0544004, 0.0445612, 0.0404771, 0.0359418, 0.0313758, 0.0262163, 0.0213853", \ - "0.105161, 0.0921352, 0.0860055, 0.0782634, 0.0693741, 0.0597274, 0.0487107" \ + "0.00845741, 0.0093283, 0.00935265, 0.00931403, 0.00911629, 0.00878754, 0.00814359", \ + "0.00916571, 0.00908023, 0.00919179, 0.00932226, 0.00895887, 0.00865067, 0.00811618", \ + "0.0113601, 0.00997146, 0.00974087, 0.00964227, 0.00947498, 0.00878552, 0.00817858", \ + "0.0170366, 0.0132807, 0.0123999, 0.011454, 0.0111239, 0.0097966, 0.00917006", \ + "0.0292632, 0.0225888, 0.0205335, 0.0181958, 0.0158542, 0.014187, 0.0118788", \ + "0.0544004, 0.0445612, 0.0404771, 0.0359431, 0.0313794, 0.026216, 0.0213848", \ + "0.105197, 0.0921354, 0.0860113, 0.0782629, 0.069374, 0.0597274, 0.0490588" \ ); } fall_power (POWER_7x7ds1) { index_1 ("0.0186, 0.0966, 0.174, 0.3294, 0.6408, 1.263, 2.5074"); index_2 ("0.001, 0.0234, 0.039, 0.0648, 0.108, 0.18, 0.3"); values ( \ - "0.00551991, 0.00590093, 0.00585338, 0.00562411, 0.00543776, 0.00505283, 0.00437882", \ - "0.00682314, 0.00605579, 0.00597762, 0.00570599, 0.00593305, 0.00504395, 0.00430654", \ - "0.00929895, 0.00734521, 0.00680751, 0.00639194, 0.00644446, 0.00594844, 0.00460648", \ - "0.0151118, 0.0108899, 0.00982911, 0.00877407, 0.00755839, 0.00714473, 0.00530693", \ - "0.0274853, 0.0203771, 0.017972, 0.0154999, 0.013024, 0.0106173, 0.008991", \ - "0.0529097, 0.0427362, 0.0383318, 0.0332619, 0.0279642, 0.0226178, 0.0176072", \ - "0.104147, 0.091178, 0.0845862, 0.0761721, 0.0656312, 0.0545873, 0.0435821" \ + "0.00551991, 0.00589567, 0.00585079, 0.00564556, 0.00539451, 0.00504221, 0.00437843", \ + "0.00683, 0.00605866, 0.00597927, 0.00570599, 0.00548491, 0.00504381, 0.00433144", \ + "0.0093027, 0.00734523, 0.00680752, 0.00638075, 0.0064443, 0.00579204, 0.00458504", \ + "0.0151118, 0.0108884, 0.00982928, 0.00877318, 0.00756212, 0.00684296, 0.00530044", \ + "0.0274855, 0.0203763, 0.0179721, 0.0155004, 0.0130241, 0.0106171, 0.008991", \ + "0.0529098, 0.0427354, 0.0383321, 0.0332618, 0.0279635, 0.0226301, 0.0174997", \ + "0.104147, 0.0911781, 0.0845861, 0.0761716, 0.0656311, 0.0545874, 0.0435821" \ ); } } @@ -2178,26 +2178,26 @@ library (sg13g2_stdcell_fast_1p65V_m40C) { index_1 ("0.0186, 0.0966, 0.174, 0.3294, 0.6408, 1.263, 2.5074"); index_2 ("0.001, 0.0234, 0.039, 0.0648, 0.108, 0.18, 0.3"); values ( \ - "0.00895448, 0.00919005, 0.00911803, 0.00899368, 0.00877388, 0.00841101, 0.00781125", \ - "0.00955528, 0.00921657, 0.00919494, 0.00898832, 0.00872128, 0.00838458, 0.00767566", \ - "0.0116672, 0.0102264, 0.00993967, 0.00983397, 0.00941317, 0.00859485, 0.00800921", \ - "0.0174323, 0.0138324, 0.0128214, 0.0117529, 0.0112474, 0.00967122, 0.00940458", \ - "0.0300238, 0.023691, 0.0213962, 0.0190924, 0.0164758, 0.014539, 0.0120156", \ - "0.0558587, 0.0469086, 0.042923, 0.0380836, 0.0329937, 0.0273357, 0.0219153", \ - "0.10813, 0.096467, 0.0907143, 0.0829895, 0.0735655, 0.062329, 0.0514471" \ + "0.00895628, 0.00919014, 0.00912003, 0.00899107, 0.00877399, 0.00840974, 0.00778468", \ + "0.0095556, 0.00921545, 0.00920469, 0.00902355, 0.00873467, 0.00838261, 0.00770871", \ + "0.0116707, 0.0102345, 0.0099106, 0.0095891, 0.00941242, 0.00859787, 0.00798642", \ + "0.0174332, 0.0138325, 0.0128231, 0.0117394, 0.0112474, 0.00975167, 0.00940437", \ + "0.0300218, 0.0236934, 0.0213983, 0.0190925, 0.0164845, 0.0145391, 0.0119872", \ + "0.0558583, 0.0469121, 0.042923, 0.038098, 0.032994, 0.0272988, 0.0218897", \ + "0.10813, 0.0964676, 0.0907138, 0.08299, 0.0735656, 0.0623293, 0.0514445" \ ); } fall_power (POWER_7x7ds1) { index_1 ("0.0186, 0.0966, 0.174, 0.3294, 0.6408, 1.263, 2.5074"); index_2 ("0.001, 0.0234, 0.039, 0.0648, 0.108, 0.18, 0.3"); values ( \ - "0.00892397, 0.00924034, 0.00902368, 0.00892041, 0.00869134, 0.00837691, 0.00766322", \ - "0.00955089, 0.00921462, 0.00915143, 0.00895727, 0.00902922, 0.00857636, 0.00773721", \ - "0.0117475, 0.0102488, 0.00995989, 0.00949619, 0.00953506, 0.00875928, 0.00785007", \ - "0.0174621, 0.0136935, 0.0127807, 0.0118134, 0.0106383, 0.010187, 0.00877558", \ - "0.0301048, 0.0232246, 0.0208358, 0.0186173, 0.0161975, 0.0139041, 0.0122701", \ - "0.0561931, 0.0459331, 0.0416614, 0.0363898, 0.0311776, 0.0260612, 0.0212442", \ - "0.109354, 0.0957459, 0.0891471, 0.0804783, 0.0701485, 0.0588372, 0.0483839" \ + "0.0089276, 0.00923805, 0.00914767, 0.00893021, 0.00871796, 0.00837591, 0.00765356", \ + "0.00955565, 0.00921454, 0.00915169, 0.00899022, 0.00902922, 0.00831772, 0.00772517", \ + "0.011744, 0.0102456, 0.00995962, 0.00947761, 0.00953812, 0.0085397, 0.00783742", \ + "0.0174644, 0.0136918, 0.0127836, 0.0117961, 0.0106391, 0.0101702, 0.008821", \ + "0.0301056, 0.0232188, 0.0208372, 0.0186147, 0.0161975, 0.0137296, 0.0122636", \ + "0.0561933, 0.0459333, 0.0416615, 0.0363893, 0.0311777, 0.0260576, 0.0212367", \ + "0.109355, 0.0957461, 0.0891477, 0.0804783, 0.0701485, 0.0588373, 0.0483839" \ ); } } @@ -2208,26 +2208,26 @@ library (sg13g2_stdcell_fast_1p65V_m40C) { index_1 ("0.0186, 0.0966, 0.174, 0.3294, 0.6408, 1.263, 2.5074"); index_2 ("0.001, 0.0234, 0.039, 0.0648, 0.108, 0.18, 0.3"); values ( \ - "0.00457434, 0.00515597, 0.00518759, 0.00515707, 0.00499506, 0.00461554, 0.00406534", \ - "0.00660148, 0.00560358, 0.00551624, 0.00524274, 0.00504578, 0.00456624, 0.00399321", \ - "0.00945796, 0.00723974, 0.00670366, 0.00617403, 0.00569094, 0.0049182, 0.00423166", \ - "0.0155258, 0.011611, 0.010456, 0.00912272, 0.00790006, 0.00672255, 0.00609834", \ - "0.0285131, 0.0221933, 0.0199974, 0.0174676, 0.0146022, 0.0122438, 0.00961036", \ - "0.054509, 0.0450248, 0.0412304, 0.0368241, 0.0318709, 0.026201, 0.0207121", \ - "0.107633, 0.0946586, 0.089056, 0.081315, 0.0727276, 0.0628285, 0.0520734" \ + "0.00457415, 0.00513623, 0.0051919, 0.00515662, 0.00499506, 0.00461618, 0.00395823", \ + "0.00660078, 0.00560395, 0.00551623, 0.0053086, 0.00504591, 0.00456559, 0.00414778", \ + "0.00945797, 0.00726938, 0.00670367, 0.0061646, 0.00554225, 0.00491481, 0.00424016", \ + "0.0155258, 0.0116129, 0.0104561, 0.00912366, 0.00790006, 0.00672278, 0.00609925", \ + "0.0285078, 0.0221933, 0.019909, 0.0174952, 0.0146039, 0.0123242, 0.00917769", \ + "0.0545092, 0.0450246, 0.0412309, 0.0368242, 0.0318701, 0.0261835, 0.0207113", \ + "0.107635, 0.0946598, 0.0890562, 0.0813134, 0.0727276, 0.0628272, 0.0520736" \ ); } fall_power (POWER_7x7ds1) { index_1 ("0.0186, 0.0966, 0.174, 0.3294, 0.6408, 1.263, 2.5074"); index_2 ("0.001, 0.0234, 0.039, 0.0648, 0.108, 0.18, 0.3"); values ( \ - "0.00684557, 0.00776388, 0.00779177, 0.00761931, 0.00751437, 0.00716527, 0.0065497", \ - "0.00872237, 0.00807122, 0.00797146, 0.00786296, 0.00805075, 0.0072604, 0.00701762", \ - "0.0114786, 0.00932982, 0.00905021, 0.00863458, 0.00804984, 0.00830044, 0.0068342", \ - "0.0177632, 0.0131569, 0.0120799, 0.0110804, 0.0102036, 0.00875166, 0.0084458", \ - "0.0309023, 0.0236105, 0.0207051, 0.0182007, 0.0159434, 0.0135636, 0.0111312", \ - "0.0574149, 0.0463862, 0.0419276, 0.0367583, 0.0315222, 0.0260602, 0.0217444", \ - "0.111659, 0.0968751, 0.0899184, 0.0813015, 0.0711548, 0.0597117, 0.0490512" \ + "0.00684585, 0.00776398, 0.00779291, 0.00761764, 0.00753048, 0.00716959, 0.00655042", \ + "0.00872313, 0.00807122, 0.0079714, 0.00786296, 0.00805008, 0.00724292, 0.00680364", \ + "0.0114795, 0.00933036, 0.00905012, 0.0086329, 0.00805976, 0.00828161, 0.00683473", \ + "0.0177631, 0.0131567, 0.0120801, 0.0110805, 0.0101819, 0.00875158, 0.00845662", \ + "0.0309023, 0.0236104, 0.0207053, 0.0181997, 0.0159424, 0.0136392, 0.0111311", \ + "0.0574145, 0.0463855, 0.0419277, 0.0367607, 0.0315231, 0.0260602, 0.0217442", \ + "0.111662, 0.0968751, 0.0899191, 0.0813019, 0.0711541, 0.0597127, 0.0490512" \ ); } } @@ -2238,26 +2238,26 @@ library (sg13g2_stdcell_fast_1p65V_m40C) { index_1 ("0.0186, 0.0966, 0.174, 0.3294, 0.6408, 1.263, 2.5074"); index_2 ("0.001, 0.0234, 0.039, 0.0648, 0.108, 0.18, 0.3"); values ( \ - "0.00405099, 0.00471614, 0.0047876, 0.00475785, 0.00459711, 0.00422664, 0.00354085", \ - "0.00648353, 0.00522666, 0.00517565, 0.0049373, 0.00458506, 0.00420879, 0.00350787", \ - "0.00952877, 0.0069488, 0.00635326, 0.00604178, 0.00525955, 0.00455585, 0.0038893", \ - "0.0158523, 0.0114464, 0.0101912, 0.00874908, 0.00791168, 0.00606637, 0.00526904", \ - "0.029117, 0.0221861, 0.0198034, 0.0171521, 0.0142264, 0.0119698, 0.00856293", \ - "0.0555118, 0.0453729, 0.0415775, 0.0368912, 0.0316734, 0.0261163, 0.0203235", \ - "0.109067, 0.0952811, 0.0895108, 0.0816243, 0.0727547, 0.0627998, 0.0519149" \ + "0.00405344, 0.00471945, 0.00479868, 0.00476783, 0.00459611, 0.00422937, 0.0035405", \ + "0.00648397, 0.00521709, 0.00513953, 0.00493952, 0.00459792, 0.00420181, 0.00355472", \ + "0.00952879, 0.00694839, 0.0063544, 0.00584795, 0.0051436, 0.00456166, 0.0038893", \ + "0.015851, 0.0114462, 0.0101846, 0.00874941, 0.00791168, 0.00607513, 0.00526913", \ + "0.0291277, 0.0221805, 0.0198012, 0.0171396, 0.0142258, 0.0119267, 0.00918639", \ + "0.0555114, 0.0453723, 0.0415775, 0.0368876, 0.0316736, 0.0260942, 0.0203241", \ + "0.109064, 0.0952779, 0.0895107, 0.0816168, 0.0727565, 0.0628022, 0.0519149" \ ); } fall_power (POWER_7x7ds1) { index_1 ("0.0186, 0.0966, 0.174, 0.3294, 0.6408, 1.263, 2.5074"); index_2 ("0.001, 0.0234, 0.039, 0.0648, 0.108, 0.18, 0.3"); values ( \ - "0.00340299, 0.00435932, 0.00437472, 0.00420254, 0.00405969, 0.00373217, 0.00307598", \ - "0.00535768, 0.00464979, 0.00454523, 0.00443242, 0.00445906, 0.00379918, 0.00357063", \ - "0.00820353, 0.00592397, 0.00562884, 0.00523444, 0.0045998, 0.00469516, 0.00349737", \ - "0.0145414, 0.00975685, 0.00873425, 0.00775579, 0.00687438, 0.00541222, 0.0050682", \ - "0.0278445, 0.0203236, 0.0173779, 0.0149754, 0.0125318, 0.0102311, 0.00773186", \ - "0.0545566, 0.0432836, 0.0387769, 0.0335814, 0.0281029, 0.0229766, 0.0183845", \ - "0.108916, 0.0940097, 0.086923, 0.0782239, 0.0679121, 0.0560835, 0.046017" \ + "0.00340251, 0.00428369, 0.00437352, 0.0042962, 0.00408941, 0.00372861, 0.00307586", \ + "0.00535766, 0.00464979, 0.00454546, 0.00443242, 0.00445906, 0.00382901, 0.00357064", \ + "0.00820266, 0.00592399, 0.00562884, 0.00523444, 0.00460037, 0.00476002, 0.00349737", \ + "0.0145409, 0.00975614, 0.00873464, 0.00775579, 0.00687438, 0.00541214, 0.00506836", \ + "0.0278434, 0.0203231, 0.0173786, 0.014975, 0.0125324, 0.0102302, 0.00773301", \ + "0.0545924, 0.0432843, 0.0387769, 0.0335808, 0.0281034, 0.0229765, 0.0183845", \ + "0.108911, 0.0940101, 0.086922, 0.078224, 0.0679125, 0.056083, 0.046017" \ ); } } @@ -2268,26 +2268,26 @@ library (sg13g2_stdcell_fast_1p65V_m40C) { index_1 ("0.0186, 0.0966, 0.174, 0.3294, 0.6408, 1.263, 2.5074"); index_2 ("0.001, 0.0234, 0.039, 0.0648, 0.108, 0.18, 0.3"); values ( \ - "0.00412227, 0.00482796, 0.00488383, 0.00476606, 0.00459906, 0.00426986, 0.00408129", \ - "0.00680712, 0.0053868, 0.00523048, 0.00493137, 0.00471157, 0.00434975, 0.00412623", \ - "0.0101458, 0.00733476, 0.00666641, 0.00614857, 0.00539828, 0.0050157, 0.00378066", \ - "0.0170231, 0.0122307, 0.0108491, 0.00931649, 0.00804953, 0.00645423, 0.0065179", \ - "0.0313714, 0.0239685, 0.0214107, 0.018669, 0.0155641, 0.0124968, 0.0107338", \ - "0.0600204, 0.0493736, 0.0449382, 0.040261, 0.034644, 0.0284629, 0.0221688", \ - "0.117956, 0.103729, 0.0973846, 0.089364, 0.0795394, 0.0687892, 0.056923" \ + "0.00412187, 0.00483499, 0.0048108, 0.0047706, 0.00460031, 0.00427206, 0.00351616", \ + "0.00680765, 0.00538759, 0.00523049, 0.00492903, 0.0048338, 0.00428433, 0.00360407", \ + "0.0101459, 0.00733735, 0.00666638, 0.00616707, 0.00539483, 0.00533656, 0.00378485", \ + "0.0170239, 0.0122309, 0.0108492, 0.00934706, 0.00804953, 0.00645531, 0.00593737", \ + "0.0313733, 0.0239687, 0.0214109, 0.0186642, 0.015565, 0.0124511, 0.0107695", \ + "0.0600206, 0.0493736, 0.0449178, 0.0402615, 0.0346443, 0.0285628, 0.0221703", \ + "0.117956, 0.103729, 0.0973837, 0.089365, 0.0795421, 0.0687892, 0.056923" \ ); } fall_power (POWER_7x7ds1) { index_1 ("0.0186, 0.0966, 0.174, 0.3294, 0.6408, 1.263, 2.5074"); index_2 ("0.001, 0.0234, 0.039, 0.0648, 0.108, 0.18, 0.3"); values ( \ - "0.00318874, 0.00414221, 0.00416342, 0.00401069, 0.00387317, 0.00353866, 0.00288287", \ - "0.00547208, 0.00449174, 0.00432831, 0.004217, 0.0041354, 0.00361798, 0.00315872", \ - "0.0086208, 0.00594238, 0.00555624, 0.00511715, 0.00449548, 0.00457881, 0.00321988", \ - "0.0156266, 0.0102431, 0.00908766, 0.00793706, 0.00696347, 0.00529742, 0.00496158", \ - "0.0301251, 0.0219023, 0.0187417, 0.01595, 0.0131604, 0.0108194, 0.00832409", \ - "0.0592818, 0.0470337, 0.041999, 0.0364773, 0.0306473, 0.0246474, 0.0197035", \ - "0.118113, 0.102309, 0.094697, 0.0854916, 0.0742863, 0.0617351, 0.0501405" \ + "0.00319067, 0.00413817, 0.00416338, 0.00402189, 0.00387481, 0.00353757, 0.00288285", \ + "0.00547209, 0.00449174, 0.00432831, 0.004217, 0.0043731, 0.00357757, 0.00307986", \ + "0.00862081, 0.00594238, 0.00555592, 0.00511731, 0.00449548, 0.00460973, 0.00322029", \ + "0.0156252, 0.0102431, 0.00908818, 0.00793702, 0.00696355, 0.00529742, 0.00496249", \ + "0.0301249, 0.021903, 0.0187417, 0.0159494, 0.0131602, 0.0107347, 0.0083255", \ + "0.0592571, 0.0470334, 0.0419993, 0.0364777, 0.0306474, 0.0246468, 0.0197035", \ + "0.118112, 0.102309, 0.0946985, 0.0854922, 0.0742862, 0.061735, 0.0501404" \ ); } } @@ -2297,26 +2297,26 @@ library (sg13g2_stdcell_fast_1p65V_m40C) { index_1 ("0.0186, 0.0966, 0.174, 0.3294, 0.6408, 1.263, 2.5074"); index_2 ("0.001, 0.0234, 0.039, 0.0648, 0.108, 0.18, 0.3"); values ( \ - "0.00457434, 0.00515597, 0.00518759, 0.00515707, 0.00499506, 0.00461554, 0.00406534", \ - "0.00660148, 0.00560358, 0.00551624, 0.00524274, 0.00504578, 0.00456624, 0.00399321", \ - "0.00945796, 0.00723974, 0.00670366, 0.00617403, 0.00569094, 0.0049182, 0.00423166", \ - "0.0155258, 0.011611, 0.010456, 0.00912272, 0.00790006, 0.00672255, 0.00609834", \ - "0.0285131, 0.0221933, 0.0199974, 0.0174676, 0.0146022, 0.0122438, 0.00961036", \ - "0.054509, 0.0450248, 0.0412304, 0.0368241, 0.0318709, 0.026201, 0.0207121", \ - "0.107633, 0.0946586, 0.089056, 0.081315, 0.0727276, 0.0628285, 0.0520734" \ + "0.00457415, 0.00513623, 0.0051919, 0.00515662, 0.00499506, 0.00461618, 0.00395823", \ + "0.00660078, 0.00560395, 0.00551623, 0.0053086, 0.00504591, 0.00456559, 0.00414778", \ + "0.00945797, 0.00726938, 0.00670367, 0.0061646, 0.00554225, 0.00491481, 0.00424016", \ + "0.0155258, 0.0116129, 0.0104561, 0.00912366, 0.00790006, 0.00672278, 0.00609925", \ + "0.0285078, 0.0221933, 0.019909, 0.0174952, 0.0146039, 0.0123242, 0.00917769", \ + "0.0545092, 0.0450246, 0.0412309, 0.0368242, 0.0318701, 0.0261835, 0.0207113", \ + "0.107635, 0.0946598, 0.0890562, 0.0813134, 0.0727276, 0.0628272, 0.0520736" \ ); } fall_power (POWER_7x7ds1) { index_1 ("0.0186, 0.0966, 0.174, 0.3294, 0.6408, 1.263, 2.5074"); index_2 ("0.001, 0.0234, 0.039, 0.0648, 0.108, 0.18, 0.3"); values ( \ - "0.00318874, 0.00414221, 0.00416342, 0.00401069, 0.00387317, 0.00353866, 0.00288287", \ - "0.00547208, 0.00449174, 0.00432831, 0.004217, 0.0041354, 0.00361798, 0.00315872", \ - "0.0086208, 0.00594238, 0.00555624, 0.00511715, 0.00449548, 0.00457881, 0.00321988", \ - "0.0156266, 0.0102431, 0.00908766, 0.00793706, 0.00696347, 0.00529742, 0.00496158", \ - "0.0301251, 0.0219023, 0.0187417, 0.01595, 0.0131604, 0.0108194, 0.00832409", \ - "0.0592818, 0.0470337, 0.041999, 0.0364773, 0.0306473, 0.0246474, 0.0197035", \ - "0.118113, 0.102309, 0.094697, 0.0854916, 0.0742863, 0.0617351, 0.0501405" \ + "0.00319067, 0.00413817, 0.00416338, 0.00402189, 0.00387481, 0.00353757, 0.00288285", \ + "0.00547209, 0.00449174, 0.00432831, 0.004217, 0.0043731, 0.00357757, 0.00307986", \ + "0.00862081, 0.00594238, 0.00555592, 0.00511731, 0.00449548, 0.00460973, 0.00322029", \ + "0.0156252, 0.0102431, 0.00908818, 0.00793702, 0.00696355, 0.00529742, 0.00496249", \ + "0.0301249, 0.021903, 0.0187417, 0.0159494, 0.0131602, 0.0107347, 0.0083255", \ + "0.0592571, 0.0470334, 0.0419993, 0.0364777, 0.0306474, 0.0246468, 0.0197035", \ + "0.118112, 0.102309, 0.0946985, 0.0854922, 0.0742862, 0.061735, 0.0501404" \ ); } } @@ -2325,28 +2325,28 @@ library (sg13g2_stdcell_fast_1p65V_m40C) { direction : "input"; max_transition : 2.5074; capacitance : 0.00334901; - rise_capacitance : 0.00320786; - rise_capacitance_range (0.00320786, 0.00320786); - fall_capacitance : 0.00349015; - fall_capacitance_range (0.00349015, 0.00349015); + rise_capacitance : 0.00320785; + rise_capacitance_range (0.00296813, 0.00358599); + fall_capacitance : 0.00349016; + fall_capacitance_range (0.00291909, 0.00401934); } pin (A2) { direction : "input"; max_transition : 2.5074; - capacitance : 0.00345691; - rise_capacitance : 0.00349098; - rise_capacitance_range (0.00349098, 0.00349098); + capacitance : 0.00345694; + rise_capacitance : 0.00349105; + rise_capacitance_range (0.0029772, 0.00387032); fall_capacitance : 0.00342284; - fall_capacitance_range (0.00342284, 0.00342284); + fall_capacitance_range (0.00295909, 0.00372155); } pin (B1) { direction : "input"; max_transition : 2.5074; capacitance : 0.00316778; rise_capacitance : 0.00329856; - rise_capacitance_range (0.00329856, 0.00329856); - fall_capacitance : 0.003037; - fall_capacitance_range (0.003037, 0.003037); + rise_capacitance_range (0.00275436, 0.00462276); + fall_capacitance : 0.00303701; + fall_capacitance_range (0.00283471, 0.00341007); } } cell (sg13g2_a21oi_2) { @@ -2370,15 +2370,15 @@ library (sg13g2_stdcell_fast_1p65V_m40C) { when : "!A1&A2&B1&!Y"; } leakage_power () { - value : 823.985; + value : 823.982; when : "A1&!A2&!B1&Y"; } leakage_power () { - value : 3131.32; + value : 3131.31; when : "A1&!A2&B1&!Y"; } leakage_power () { - value : 2819.07; + value : 2819.06; when : "A1&A2&!B1&!Y"; } leakage_power () { @@ -2398,52 +2398,52 @@ library (sg13g2_stdcell_fast_1p65V_m40C) { index_1 ("0.0186, 0.0966, 0.174, 0.3294, 0.6408, 1.263, 2.5074"); index_2 ("0.001, 0.0468, 0.078, 0.1296, 0.216, 0.36, 0.6"); values ( \ - "0.0213387, 0.0848234, 0.126456, 0.195144, 0.309985, 0.501421, 0.820591", \ - "0.0279767, 0.103086, 0.14613, 0.215356, 0.330418, 0.522003, 0.840685", \ - "0.0308364, 0.116571, 0.162504, 0.234047, 0.350036, 0.541625, 0.860551", \ - "0.0348634, 0.137137, 0.188685, 0.266073, 0.387186, 0.581291, 0.900238", \ - "0.039041, 0.166299, 0.227447, 0.316049, 0.448812, 0.654378, 0.979919", \ - "0.0394534, 0.205313, 0.280116, 0.386702, 0.541781, 0.770044, 1.12002", \ - "0.0394544, 0.25041, 0.347932, 0.48021, 0.668527, 0.942674, 1.33799" \ + "0.021332, 0.0848255, 0.126447, 0.195138, 0.309978, 0.501287, 0.820567", \ + "0.0279215, 0.103083, 0.146127, 0.215358, 0.330422, 0.521983, 0.840658", \ + "0.0308354, 0.116567, 0.1625, 0.23402, 0.350032, 0.541602, 0.860529", \ + "0.034862, 0.137134, 0.188541, 0.266066, 0.387527, 0.581236, 0.900222", \ + "0.0390387, 0.166293, 0.227441, 0.316041, 0.448801, 0.654429, 0.979894", \ + "0.0394497, 0.205307, 0.280108, 0.386693, 0.541771, 0.770026, 1.11999", \ + "0.0394507, 0.2504, 0.347921, 0.480196, 0.668504, 0.942654, 1.33611" \ ); } rise_transition (TIMING_DELAY_7x7ds1) { index_1 ("0.0186, 0.0966, 0.174, 0.3294, 0.6408, 1.263, 2.5074"); index_2 ("0.001, 0.0468, 0.078, 0.1296, 0.216, 0.36, 0.6"); values ( \ - "0.0124803, 0.100624, 0.16149, 0.262005, 0.430409, 0.711143, 1.17903", \ - "0.0231786, 0.107199, 0.165208, 0.263513, 0.432499, 0.711191, 1.17904", \ - "0.0330541, 0.118169, 0.174783, 0.270289, 0.433977, 0.711946, 1.17905", \ - "0.0507173, 0.139968, 0.197194, 0.290505, 0.449353, 0.720168, 1.18154", \ - "0.0789048, 0.180336, 0.239305, 0.335018, 0.491807, 0.754505, 1.20268", \ - "0.125876, 0.249601, 0.315881, 0.417529, 0.579316, 0.841825, 1.27756", \ - "0.207986, 0.36832, 0.446793, 0.563054, 0.7392, 1.01914, 1.45561" \ + "0.0124926, 0.100603, 0.161479, 0.261996, 0.430396, 0.711055, 1.17899", \ + "0.0231525, 0.107196, 0.165245, 0.263486, 0.432476, 0.711169, 1.179", \ + "0.0330534, 0.118157, 0.174781, 0.270259, 0.433948, 0.711996, 1.17901", \ + "0.0507167, 0.139965, 0.19707, 0.290498, 0.449351, 0.720149, 1.1874", \ + "0.0789042, 0.180335, 0.239301, 0.335011, 0.491804, 0.754564, 1.20265", \ + "0.125873, 0.249598, 0.315877, 0.417521, 0.579311, 0.841804, 1.27751", \ + "0.207997, 0.368317, 0.446787, 0.563047, 0.739431, 1.01912, 1.4538" \ ); } cell_fall (TIMING_DELAY_7x7ds1) { index_1 ("0.0186, 0.0966, 0.174, 0.3294, 0.6408, 1.263, 2.5074"); index_2 ("0.001, 0.0468, 0.078, 0.1296, 0.216, 0.36, 0.6"); values ( \ - "0.0203577, 0.0693294, 0.100882, 0.152803, 0.239567, 0.384227, 0.624822", \ - "0.033688, 0.0988806, 0.133439, 0.186859, 0.273905, 0.418328, 0.659003", \ - "0.0426161, 0.119931, 0.159624, 0.218194, 0.30859, 0.453846, 0.694375", \ - "0.0559221, 0.150935, 0.198757, 0.267437, 0.368798, 0.522717, 0.766755", \ - "0.0733057, 0.193004, 0.251448, 0.335363, 0.456218, 0.632485, 0.896218", \ - "0.0993598, 0.253898, 0.327023, 0.429445, 0.57948, 0.791575, 1.10009", \ - "0.139794, 0.340722, 0.434813, 0.567265, 0.75122, 1.01517, 1.39023" \ + "0.0203529, 0.0693397, 0.100878, 0.1528, 0.23956, 0.384243, 0.624815", \ + "0.0336879, 0.0988755, 0.133437, 0.186858, 0.273882, 0.418409, 0.659014", \ + "0.0426162, 0.119948, 0.159623, 0.218193, 0.308596, 0.453844, 0.69444", \ + "0.0559224, 0.150935, 0.198756, 0.267436, 0.368797, 0.522715, 0.766766", \ + "0.0733007, 0.193005, 0.251448, 0.335363, 0.456217, 0.632483, 0.896215", \ + "0.0993622, 0.253899, 0.327023, 0.429445, 0.579479, 0.791572, 1.10009", \ + "0.139781, 0.340812, 0.434815, 0.567266, 0.751244, 1.01517, 1.39023" \ ); } fall_transition (TIMING_DELAY_7x7ds1) { index_1 ("0.0186, 0.0966, 0.174, 0.3294, 0.6408, 1.263, 2.5074"); index_2 ("0.001, 0.0468, 0.078, 0.1296, 0.216, 0.36, 0.6"); values ( \ - "0.0154943, 0.0781019, 0.122497, 0.194556, 0.316003, 0.518398, 0.8556", \ - "0.0281801, 0.0916392, 0.131874, 0.199932, 0.317953, 0.518452, 0.855601", \ - "0.0389622, 0.107895, 0.148788, 0.215069, 0.32817, 0.522681, 0.85614", \ - "0.0573523, 0.136747, 0.180749, 0.249056, 0.360159, 0.546807, 0.868764", \ - "0.0887015, 0.186248, 0.23521, 0.310224, 0.427183, 0.613249, 0.922421", \ - "0.142195, 0.271026, 0.328494, 0.41492, 0.543759, 0.743269, 1.05689", \ - "0.236692, 0.418679, 0.494132, 0.59303, 0.743129, 0.964552, 1.3085" \ + "0.0154961, 0.0781636, 0.122497, 0.194568, 0.316169, 0.5184, 0.855601", \ + "0.0281799, 0.0916337, 0.131887, 0.199859, 0.317647, 0.518517, 0.855602", \ + "0.0389621, 0.107911, 0.148783, 0.215076, 0.328174, 0.52268, 0.856238", \ + "0.0573521, 0.136747, 0.180748, 0.249055, 0.360156, 0.546806, 0.868778", \ + "0.0886269, 0.186248, 0.235209, 0.310224, 0.427181, 0.613248, 0.922417", \ + "0.142195, 0.271026, 0.328493, 0.414919, 0.543759, 0.743265, 1.05689", \ + "0.23727, 0.418467, 0.494131, 0.593029, 0.742053, 0.964551, 1.3085" \ ); } } @@ -2455,52 +2455,52 @@ library (sg13g2_stdcell_fast_1p65V_m40C) { index_1 ("0.0186, 0.0966, 0.174, 0.3294, 0.6408, 1.263, 2.5074"); index_2 ("0.001, 0.0468, 0.078, 0.1296, 0.216, 0.36, 0.6"); values ( \ - "0.0259065, 0.0880178, 0.129374, 0.197524, 0.311696, 0.502135, 0.818807", \ - "0.0352807, 0.107117, 0.149629, 0.218246, 0.332465, 0.522577, 0.839625", \ - "0.0402127, 0.121452, 0.166562, 0.237411, 0.352421, 0.542688, 0.859642", \ - "0.0489859, 0.143632, 0.193869, 0.27031, 0.390404, 0.582999, 0.899974", \ - "0.0621734, 0.176956, 0.236048, 0.323009, 0.454168, 0.657212, 0.98036", \ - "0.0798056, 0.225714, 0.296038, 0.398534, 0.550638, 0.775927, 1.12266", \ - "0.102798, 0.293668, 0.382804, 0.508437, 0.691522, 0.955014, 1.34657" \ + "0.0259108, 0.0879956, 0.129372, 0.197535, 0.311687, 0.502119, 0.818781", \ + "0.0352797, 0.107115, 0.149626, 0.218243, 0.332495, 0.522842, 0.839598", \ + "0.0402119, 0.121449, 0.166558, 0.237413, 0.352418, 0.54271, 0.859609", \ + "0.0489727, 0.143627, 0.193864, 0.27031, 0.390348, 0.583015, 0.899932", \ + "0.0621708, 0.17695, 0.236048, 0.323001, 0.454157, 0.657195, 0.980334", \ + "0.0798009, 0.225708, 0.296029, 0.398523, 0.550623, 0.775919, 1.1227", \ + "0.102789, 0.293658, 0.382793, 0.508422, 0.691504, 0.954986, 1.34654" \ ); } rise_transition (TIMING_DELAY_7x7ds1) { index_1 ("0.0186, 0.0966, 0.174, 0.3294, 0.6408, 1.263, 2.5074"); index_2 ("0.001, 0.0468, 0.078, 0.1296, 0.216, 0.36, 0.6"); values ( \ - "0.0170045, 0.105421, 0.165761, 0.265668, 0.43311, 0.712184, 1.177", \ - "0.0274507, 0.111551, 0.169426, 0.267208, 0.434983, 0.712185, 1.17701", \ - "0.0368286, 0.122515, 0.17893, 0.273941, 0.436728, 0.712956, 1.17711", \ - "0.0534085, 0.143996, 0.200911, 0.29404, 0.452094, 0.721227, 1.18497", \ - "0.0804085, 0.183218, 0.24371, 0.338883, 0.495053, 0.755654, 1.2007", \ - "0.1257, 0.250668, 0.318382, 0.418579, 0.581066, 0.842769, 1.27596", \ - "0.204322, 0.365592, 0.445018, 0.560311, 0.738172, 1.01166, 1.45228" \ + "0.0170106, 0.105212, 0.165756, 0.265671, 0.433097, 0.712163, 1.17697", \ + "0.0274501, 0.111544, 0.169421, 0.267309, 0.435088, 0.712164, 1.17698", \ + "0.0368276, 0.122512, 0.178925, 0.273941, 0.436722, 0.712796, 1.17707", \ + "0.0534979, 0.14399, 0.200906, 0.294007, 0.452023, 0.721236, 1.18492", \ + "0.0804077, 0.183221, 0.243709, 0.338875, 0.495041, 0.755605, 1.20063", \ + "0.125691, 0.250664, 0.318376, 0.419432, 0.581053, 0.84276, 1.27616", \ + "0.204329, 0.365589, 0.445012, 0.560288, 0.738159, 1.01163, 1.45225" \ ); } cell_fall (TIMING_DELAY_7x7ds1) { index_1 ("0.0186, 0.0966, 0.174, 0.3294, 0.6408, 1.263, 2.5074"); index_2 ("0.001, 0.0468, 0.078, 0.1296, 0.216, 0.36, 0.6"); values ( \ - "0.0217554, 0.0702054, 0.101757, 0.153652, 0.240493, 0.384895, 0.625666", \ - "0.0318906, 0.0910755, 0.124581, 0.177557, 0.264631, 0.4092, 0.649949", \ - "0.0381125, 0.107269, 0.14379, 0.199835, 0.289039, 0.434253, 0.67518", \ - "0.0469066, 0.131681, 0.174094, 0.236485, 0.332393, 0.482791, 0.725766", \ - "0.0567048, 0.164469, 0.215529, 0.289881, 0.398255, 0.56252, 0.817116", \ - "0.0677484, 0.207758, 0.273896, 0.363913, 0.495448, 0.685616, 0.967485", \ - "0.0782492, 0.261728, 0.34879, 0.466446, 0.630345, 0.861054, 1.1949" \ + "0.0217543, 0.0702097, 0.101755, 0.153657, 0.2405, 0.384907, 0.625673", \ + "0.0318905, 0.0910752, 0.124581, 0.177554, 0.26463, 0.409301, 0.650056", \ + "0.0381124, 0.107268, 0.14379, 0.199835, 0.289038, 0.43425, 0.675178", \ + "0.0469066, 0.131681, 0.174093, 0.236482, 0.332392, 0.482789, 0.725763", \ + "0.0567057, 0.164469, 0.215528, 0.289881, 0.398254, 0.562512, 0.817112", \ + "0.0677503, 0.207758, 0.273897, 0.363912, 0.495447, 0.685614, 0.967471", \ + "0.0782539, 0.261731, 0.348792, 0.466447, 0.630345, 0.861053, 1.1949" \ ); } fall_transition (TIMING_DELAY_7x7ds1) { index_1 ("0.0186, 0.0966, 0.174, 0.3294, 0.6408, 1.263, 2.5074"); index_2 ("0.001, 0.0468, 0.078, 0.1296, 0.216, 0.36, 0.6"); values ( \ - "0.0145751, 0.0780594, 0.122161, 0.194548, 0.315926, 0.518214, 0.855858", \ - "0.0249233, 0.0863482, 0.127751, 0.197645, 0.316996, 0.518695, 0.855859", \ - "0.0354605, 0.0974321, 0.138726, 0.206777, 0.323027, 0.521044, 0.85724", \ - "0.0541626, 0.120156, 0.161828, 0.229342, 0.342816, 0.535181, 0.863176", \ - "0.0846001, 0.163559, 0.206365, 0.275658, 0.3891, 0.577098, 0.895201", \ - "0.135858, 0.241878, 0.288783, 0.363451, 0.47885, 0.669561, 0.98302", \ - "0.22487, 0.373956, 0.437646, 0.522317, 0.650206, 0.848867, 1.16816" \ + "0.0145749, 0.0781008, 0.122161, 0.194548, 0.315916, 0.518317, 0.85589", \ + "0.0249232, 0.086348, 0.127751, 0.197661, 0.316983, 0.518632, 0.855891", \ + "0.0354605, 0.0974317, 0.138726, 0.206776, 0.323026, 0.52109, 0.857237", \ + "0.0541624, 0.120156, 0.161827, 0.229346, 0.342814, 0.53518, 0.863172", \ + "0.0845998, 0.163558, 0.206365, 0.275656, 0.389098, 0.576994, 0.895171", \ + "0.135857, 0.241877, 0.288782, 0.363449, 0.478851, 0.669563, 0.982823", \ + "0.224852, 0.373954, 0.437644, 0.522315, 0.650203, 0.848864, 1.16816" \ ); } } @@ -2514,52 +2514,52 @@ library (sg13g2_stdcell_fast_1p65V_m40C) { index_1 ("0.0186, 0.0966, 0.174, 0.3294, 0.6408, 1.263, 2.5074"); index_2 ("0.001, 0.0468, 0.078, 0.1296, 0.216, 0.36, 0.6"); values ( \ - "0.0216217, 0.0846718, 0.126141, 0.194474, 0.308724, 0.499202, 0.816094", \ - "0.0359276, 0.113443, 0.156583, 0.225257, 0.339367, 0.529552, 0.846904", \ - "0.0450246, 0.135465, 0.182979, 0.25508, 0.370269, 0.560205, 0.876808", \ - "0.0599671, 0.168465, 0.224341, 0.305766, 0.429232, 0.622892, 0.939318", \ - "0.0836034, 0.21747, 0.285309, 0.381863, 0.52421, 0.73658, 1.06383", \ - "0.121743, 0.289639, 0.373039, 0.492494, 0.663774, 0.913564, 1.28086", \ - "0.185417, 0.401262, 0.50474, 0.652908, 0.866688, 1.17067, 1.60525" \ + "0.0216226, 0.0846666, 0.126137, 0.194486, 0.308731, 0.499184, 0.816218", \ + "0.0359281, 0.113444, 0.156579, 0.225232, 0.339313, 0.529579, 0.847031", \ + "0.0450234, 0.135463, 0.182976, 0.255072, 0.370258, 0.560307, 0.876984", \ + "0.0599651, 0.168462, 0.224336, 0.305755, 0.429195, 0.622928, 0.939289", \ + "0.0835998, 0.217465, 0.285307, 0.381856, 0.524207, 0.736617, 1.06377", \ + "0.121735, 0.289631, 0.373029, 0.492484, 0.663761, 0.913545, 1.28074", \ + "0.185402, 0.401247, 0.504723, 0.652892, 0.866628, 1.17064, 1.60522" \ ); } rise_transition (TIMING_DELAY_7x7ds1) { index_1 ("0.0186, 0.0966, 0.174, 0.3294, 0.6408, 1.263, 2.5074"); index_2 ("0.001, 0.0468, 0.078, 0.1296, 0.216, 0.36, 0.6"); values ( \ - "0.0179138, 0.105186, 0.165747, 0.265695, 0.433113, 0.712095, 1.17729", \ - "0.0294137, 0.115695, 0.172061, 0.268252, 0.433883, 0.712096, 1.1773", \ - "0.0376543, 0.131478, 0.18697, 0.279361, 0.439034, 0.713565, 1.17735", \ - "0.0516953, 0.158893, 0.217986, 0.310396, 0.463999, 0.727361, 1.18398", \ - "0.07713, 0.203311, 0.270263, 0.370174, 0.527229, 0.78238, 1.21657", \ - "0.121279, 0.274858, 0.353032, 0.467489, 0.641877, 0.907196, 1.33497", \ - "0.20127, 0.392464, 0.487065, 0.623866, 0.825273, 1.12487, 1.58072" \ + "0.017916, 0.105182, 0.165742, 0.265705, 0.433137, 0.712081, 1.17703", \ + "0.0293065, 0.115695, 0.172054, 0.268234, 0.433428, 0.712082, 1.17718", \ + "0.037654, 0.131476, 0.186975, 0.279285, 0.439027, 0.71343, 1.17719", \ + "0.0516956, 0.158886, 0.217982, 0.310312, 0.463958, 0.727399, 1.18877", \ + "0.0771306, 0.203307, 0.27026, 0.370168, 0.526721, 0.782573, 1.2165", \ + "0.121281, 0.274861, 0.353029, 0.467483, 0.641868, 0.907178, 1.33483", \ + "0.201271, 0.392464, 0.487064, 0.623862, 0.825295, 1.12486, 1.58071" \ ); } cell_fall (TIMING_DELAY_7x7ds1) { index_1 ("0.0186, 0.0966, 0.174, 0.3294, 0.6408, 1.263, 2.5074"); index_2 ("0.001, 0.0468, 0.078, 0.1296, 0.216, 0.36, 0.6"); values ( \ - "0.0113263, 0.0414921, 0.0592448, 0.088368, 0.137066, 0.21775, 0.352047", \ - "0.017458, 0.068293, 0.0914137, 0.124857, 0.175778, 0.257078, 0.391336", \ - "0.0204418, 0.0848652, 0.113274, 0.15278, 0.21003, 0.295864, 0.43152", \ - "0.0232317, 0.107308, 0.143549, 0.193365, 0.262753, 0.361506, 0.507892", \ - "0.0232327, 0.132945, 0.180418, 0.245015, 0.333539, 0.455779, 0.628352", \ - "0.0232337, 0.157568, 0.222344, 0.30805, 0.423884, 0.582388, 0.79927", \ - "0.0232347, 0.168663, 0.257017, 0.375037, 0.532669, 0.740713, 1.02648" \ + "0.0113287, 0.0414916, 0.0592467, 0.0883777, 0.137084, 0.217764, 0.352078", \ + "0.0174596, 0.0682788, 0.0914185, 0.124847, 0.175778, 0.257086, 0.391356", \ + "0.0204435, 0.0848697, 0.113279, 0.15279, 0.210042, 0.295882, 0.431594", \ + "0.0232346, 0.107314, 0.143557, 0.193375, 0.262767, 0.361526, 0.507973", \ + "0.0232356, 0.132953, 0.180428, 0.245028, 0.333556, 0.455804, 0.628467", \ + "0.0232366, 0.157581, 0.222359, 0.308032, 0.423907, 0.582418, 0.799311", \ + "0.0232376, 0.168684, 0.257042, 0.375064, 0.532691, 0.740752, 1.02653" \ ); } fall_transition (TIMING_DELAY_7x7ds1) { index_1 ("0.0186, 0.0966, 0.174, 0.3294, 0.6408, 1.263, 2.5074"); index_2 ("0.001, 0.0468, 0.078, 0.1296, 0.216, 0.36, 0.6"); values ( \ - "0.0103711, 0.0438907, 0.0679333, 0.108356, 0.176573, 0.290101, 0.479566", \ - "0.0251329, 0.0615514, 0.0840009, 0.120504, 0.183424, 0.292737, 0.480751", \ - "0.0366732, 0.0778979, 0.102, 0.139615, 0.200648, 0.304668, 0.485303", \ - "0.0564822, 0.107075, 0.133852, 0.174906, 0.238835, 0.340964, 0.513294", \ - "0.0899199, 0.155977, 0.188016, 0.235242, 0.306283, 0.415461, 0.587002", \ - "0.146059, 0.239911, 0.280316, 0.336377, 0.420469, 0.54398, 0.731794", \ - "0.243273, 0.380481, 0.438909, 0.512554, 0.613816, 0.765193, 0.97743" \ + "0.0103726, 0.0438892, 0.0679258, 0.108366, 0.176597, 0.290129, 0.479611", \ + "0.0251385, 0.0615531, 0.083969, 0.120507, 0.183414, 0.292643, 0.481372", \ + "0.0366741, 0.0779018, 0.102083, 0.139536, 0.200628, 0.30468, 0.485315", \ + "0.0564836, 0.10708, 0.133859, 0.174911, 0.238644, 0.340976, 0.513412", \ + "0.0899233, 0.155981, 0.188023, 0.235252, 0.306288, 0.415485, 0.587191", \ + "0.14606, 0.239916, 0.280324, 0.336473, 0.420493, 0.544007, 0.731828", \ + "0.243274, 0.380488, 0.438919, 0.512566, 0.613795, 0.765223, 0.977474" \ ); } } @@ -2573,52 +2573,52 @@ library (sg13g2_stdcell_fast_1p65V_m40C) { index_1 ("0.0186, 0.0966, 0.174, 0.3294, 0.6408, 1.263, 2.5074"); index_2 ("0.001, 0.0468, 0.078, 0.1296, 0.216, 0.36, 0.6"); values ( \ - "0.0162705, 0.0801136, 0.121842, 0.190516, 0.305407, 0.496886, 0.815437", \ - "0.0271958, 0.108557, 0.152158, 0.221305, 0.336046, 0.527334, 0.846647", \ - "0.0346667, 0.129846, 0.178248, 0.251008, 0.367014, 0.558158, 0.876554", \ - "0.0469533, 0.162167, 0.218668, 0.301315, 0.425781, 0.620729, 0.9391", \ - "0.0668141, 0.209545, 0.278571, 0.376541, 0.52033, 0.734488, 1.06368", \ - "0.099907, 0.280023, 0.365432, 0.486745, 0.659383, 0.911217, 1.28073", \ - "0.1578, 0.389855, 0.495305, 0.645494, 0.861238, 1.16641, 1.6052" \ + "0.01626, 0.0801305, 0.121793, 0.190513, 0.305397, 0.496874, 0.815947", \ + "0.0271952, 0.108555, 0.152154, 0.221298, 0.336053, 0.527325, 0.846207", \ + "0.0346657, 0.129844, 0.178237, 0.251003, 0.367034, 0.558014, 0.876483", \ + "0.0469514, 0.162163, 0.218664, 0.301289, 0.425808, 0.620717, 0.939086", \ + "0.0668103, 0.209542, 0.278254, 0.376534, 0.52032, 0.734372, 1.06359", \ + "0.0998994, 0.279878, 0.365423, 0.486735, 0.65937, 0.911457, 1.28071", \ + "0.157785, 0.38984, 0.495289, 0.645477, 0.861219, 1.16674, 1.60517" \ ); } rise_transition (TIMING_DELAY_7x7ds1) { index_1 ("0.0186, 0.0966, 0.174, 0.3294, 0.6408, 1.263, 2.5074"); index_2 ("0.001, 0.0468, 0.078, 0.1296, 0.216, 0.36, 0.6"); values ( \ - "0.0137955, 0.100576, 0.161409, 0.261891, 0.430404, 0.710896, 1.17858", \ - "0.0240202, 0.111776, 0.168164, 0.264691, 0.43213, 0.710897, 1.1793", \ - "0.0314893, 0.127471, 0.183327, 0.276052, 0.436497, 0.712393, 1.17931", \ - "0.0451526, 0.154742, 0.214154, 0.307018, 0.461684, 0.72637, 1.19115", \ - "0.0693956, 0.19854, 0.265906, 0.366629, 0.524557, 0.781659, 1.21852", \ - "0.11251, 0.270124, 0.350022, 0.465083, 0.639399, 0.906739, 1.33678", \ - "0.193467, 0.385805, 0.482322, 0.619341, 0.824671, 1.1223, 1.58229" \ + "0.0137881, 0.100766, 0.161361, 0.262051, 0.430391, 0.710874, 1.17892", \ + "0.02402, 0.111773, 0.168124, 0.264727, 0.433661, 0.710875, 1.17893", \ + "0.0314893, 0.127468, 0.183313, 0.276029, 0.436522, 0.712132, 1.17923", \ + "0.0451526, 0.15474, 0.214151, 0.306992, 0.461692, 0.726414, 1.18334", \ + "0.0693959, 0.198539, 0.2654, 0.366623, 0.524545, 0.781672, 1.21844", \ + "0.112511, 0.268836, 0.350019, 0.465077, 0.639389, 0.907034, 1.33673", \ + "0.193468, 0.385805, 0.482321, 0.61934, 0.824662, 1.12296, 1.58226" \ ); } cell_fall (TIMING_DELAY_7x7ds1) { index_1 ("0.0186, 0.0966, 0.174, 0.3294, 0.6408, 1.263, 2.5074"); index_2 ("0.001, 0.0468, 0.078, 0.1296, 0.216, 0.36, 0.6"); values ( \ - "0.0109671, 0.0410565, 0.0586399, 0.0875507, 0.135934, 0.216503, 0.350815", \ - "0.016156, 0.0674798, 0.0905582, 0.123885, 0.174621, 0.255797, 0.390075", \ - "0.0178789, 0.0836382, 0.112085, 0.151557, 0.208721, 0.294552, 0.430253", \ - "0.0178852, 0.105242, 0.141761, 0.191634, 0.261104, 0.360064, 0.506578", \ - "0.0178862, 0.12909, 0.177363, 0.242321, 0.331393, 0.453958, 0.626879", \ - "0.0178872, 0.150745, 0.217141, 0.304455, 0.420741, 0.580186, 0.797667", \ - "0.0178882, 0.157589, 0.248826, 0.36882, 0.528252, 0.737751, 1.02424" \ + "0.0109712, 0.041053, 0.0586512, 0.0875546, 0.135926, 0.216536, 0.350852", \ + "0.016157, 0.0674833, 0.0905633, 0.123894, 0.174638, 0.255801, 0.390092", \ + "0.0178805, 0.0836422, 0.11209, 0.151563, 0.208745, 0.294571, 0.430293", \ + "0.0178878, 0.105247, 0.141772, 0.191644, 0.261118, 0.360083, 0.506611", \ + "0.0178888, 0.129096, 0.177371, 0.242333, 0.33141, 0.453982, 0.626906", \ + "0.0178898, 0.150757, 0.217154, 0.304454, 0.420762, 0.580212, 0.797616", \ + "0.0178908, 0.157611, 0.248849, 0.368846, 0.528283, 0.737792, 1.02429" \ ); } fall_transition (TIMING_DELAY_7x7ds1) { index_1 ("0.0186, 0.0966, 0.174, 0.3294, 0.6408, 1.263, 2.5074"); index_2 ("0.001, 0.0468, 0.078, 0.1296, 0.216, 0.36, 0.6"); values ( \ - "0.00680613, 0.0408675, 0.0649252, 0.10538, 0.173533, 0.287158, 0.476573", \ - "0.0175165, 0.0580804, 0.0808475, 0.117487, 0.180417, 0.289772, 0.477989", \ - "0.0262706, 0.0739225, 0.0985278, 0.136416, 0.197653, 0.301692, 0.482461", \ - "0.0417361, 0.101822, 0.129396, 0.171742, 0.235613, 0.33804, 0.510395", \ - "0.0688927, 0.14945, 0.182367, 0.231349, 0.302719, 0.412426, 0.584098", \ - "0.116952, 0.231066, 0.273385, 0.33107, 0.41605, 0.54074, 0.728438", \ - "0.206429, 0.366677, 0.428664, 0.506194, 0.60776, 0.760019, 0.974927" \ + "0.00680418, 0.0408717, 0.0649321, 0.105389, 0.173579, 0.28719, 0.476617", \ + "0.017517, 0.0580848, 0.0808529, 0.117512, 0.18045, 0.289673, 0.478007", \ + "0.0262713, 0.0739263, 0.098533, 0.136416, 0.197662, 0.301718, 0.482581", \ + "0.0417372, 0.101831, 0.129407, 0.171751, 0.235525, 0.338066, 0.510292", \ + "0.0687239, 0.149457, 0.182372, 0.231359, 0.302748, 0.41245, 0.584128", \ + "0.116859, 0.231071, 0.273395, 0.331088, 0.416066, 0.540762, 0.728374", \ + "0.206432, 0.366686, 0.428672, 0.506205, 0.607778, 0.760056, 0.97497" \ ); } } @@ -2632,52 +2632,52 @@ library (sg13g2_stdcell_fast_1p65V_m40C) { index_1 ("0.0186, 0.0966, 0.174, 0.3294, 0.6408, 1.263, 2.5074"); index_2 ("0.001, 0.0468, 0.078, 0.1296, 0.216, 0.36, 0.6"); values ( \ - "0.0137686, 0.0620747, 0.0930281, 0.143959, 0.229162, 0.371088, 0.607683", \ - "0.0230733, 0.0908904, 0.125093, 0.177525, 0.262974, 0.40481, 0.641182", \ - "0.0291012, 0.110262, 0.149704, 0.207322, 0.295881, 0.438383, 0.674595", \ - "0.0380495, 0.138867, 0.186178, 0.254467, 0.353912, 0.504027, 0.742346", \ - "0.0518246, 0.17838, 0.238112, 0.322015, 0.441148, 0.613852, 0.87076", \ - "0.073111, 0.235651, 0.310124, 0.415434, 0.565248, 0.774007, 1.07524", \ - "0.108527, 0.319459, 0.41404, 0.545434, 0.734183, 0.998919, 1.36673" \ + "0.0137687, 0.0620829, 0.0930218, 0.143975, 0.229158, 0.371167, 0.60768", \ + "0.0230726, 0.0908908, 0.12509, 0.177512, 0.262975, 0.404792, 0.64116", \ + "0.0290988, 0.110259, 0.149685, 0.207318, 0.29586, 0.438337, 0.674661", \ + "0.0380473, 0.138866, 0.186175, 0.254462, 0.353951, 0.504, 0.742322", \ + "0.0518204, 0.178374, 0.23802, 0.322007, 0.441342, 0.613837, 0.870734", \ + "0.0731025, 0.235642, 0.310114, 0.415424, 0.565223, 0.773989, 1.07522", \ + "0.108412, 0.319442, 0.414246, 0.545415, 0.734159, 0.999711, 1.3667" \ ); } rise_transition (TIMING_DELAY_7x7ds1) { index_1 ("0.0186, 0.0966, 0.174, 0.3294, 0.6408, 1.263, 2.5074"); index_2 ("0.001, 0.0468, 0.078, 0.1296, 0.216, 0.36, 0.6"); values ( \ - "0.0108362, 0.074939, 0.120622, 0.196046, 0.322324, 0.532983, 0.884", \ - "0.0213702, 0.0890611, 0.130498, 0.201159, 0.323904, 0.534439, 0.884173", \ - "0.0289215, 0.105499, 0.147574, 0.216049, 0.333502, 0.536867, 0.88466", \ - "0.0427395, 0.132964, 0.179191, 0.250176, 0.364806, 0.558715, 0.894492", \ - "0.0669249, 0.175988, 0.231097, 0.311517, 0.432413, 0.624355, 0.944714", \ - "0.110316, 0.246278, 0.311825, 0.408115, 0.547408, 0.75577, 1.08018", \ - "0.192871, 0.361734, 0.443163, 0.563115, 0.72781, 0.972873, 1.33232" \ + "0.0108356, 0.0749518, 0.120616, 0.19606, 0.322312, 0.532962, 0.883998", \ + "0.02137, 0.0890773, 0.130494, 0.201145, 0.323943, 0.533263, 0.884139", \ + "0.0289224, 0.105492, 0.14757, 0.216032, 0.333477, 0.536792, 0.884455", \ + "0.0427399, 0.132963, 0.179188, 0.250173, 0.364854, 0.558681, 0.894456", \ + "0.0669251, 0.175986, 0.230879, 0.311512, 0.432623, 0.624336, 0.944672", \ + "0.110317, 0.246277, 0.311822, 0.40811, 0.547396, 0.755764, 1.08014", \ + "0.191842, 0.361737, 0.443335, 0.563112, 0.72789, 0.973818, 1.33226" \ ); } cell_fall (TIMING_DELAY_7x7ds1) { index_1 ("0.0186, 0.0966, 0.174, 0.3294, 0.6408, 1.263, 2.5074"); index_2 ("0.001, 0.0468, 0.078, 0.1296, 0.216, 0.36, 0.6"); values ( \ - "0.0107179, 0.0408865, 0.0584723, 0.0873968, 0.135757, 0.216372, 0.35069", \ - "0.0165001, 0.067303, 0.0903646, 0.123691, 0.174461, 0.255623, 0.389939", \ - "0.0191618, 0.0836971, 0.111999, 0.151487, 0.208636, 0.294397, 0.4301", \ - "0.0214095, 0.106293, 0.142347, 0.192051, 0.261176, 0.359986, 0.506512", \ - "0.0214105, 0.133026, 0.179892, 0.243729, 0.332739, 0.454497, 0.627174", \ - "0.0214115, 0.161882, 0.225735, 0.310842, 0.42515, 0.583422, 0.799216", \ - "0.0214125, 0.186044, 0.2731, 0.388558, 0.543075, 0.748352, 1.0316" \ + "0.0107158, 0.0408864, 0.0584869, 0.0874179, 0.135789, 0.216381, 0.350729", \ + "0.0165014, 0.0673064, 0.0903696, 0.123699, 0.174467, 0.255644, 0.38998", \ + "0.0191634, 0.0837015, 0.112005, 0.151466, 0.208651, 0.294424, 0.43012", \ + "0.0214123, 0.106294, 0.142372, 0.192061, 0.26119, 0.360006, 0.50656", \ + "0.0214133, 0.132881, 0.179895, 0.243738, 0.332794, 0.454521, 0.627209", \ + "0.0214143, 0.161895, 0.22575, 0.310859, 0.425181, 0.583452, 0.799257", \ + "0.0214153, 0.186066, 0.273125, 0.388585, 0.543635, 0.748393, 1.03137" \ ); } fall_transition (TIMING_DELAY_7x7ds1) { index_1 ("0.0186, 0.0966, 0.174, 0.3294, 0.6408, 1.263, 2.5074"); index_2 ("0.001, 0.0468, 0.078, 0.1296, 0.216, 0.36, 0.6"); values ( \ - "0.00693241, 0.0408909, 0.0649392, 0.1054, 0.173585, 0.287186, 0.47662", \ - "0.0175966, 0.0582342, 0.0809723, 0.117551, 0.180482, 0.289702, 0.478033", \ - "0.0262903, 0.073937, 0.0985342, 0.13636, 0.197913, 0.301742, 0.482429", \ - "0.0418251, 0.101211, 0.129315, 0.17148, 0.235506, 0.338004, 0.510368", \ - "0.0689665, 0.147412, 0.181156, 0.230497, 0.301815, 0.411794, 0.584023", \ - "0.116668, 0.226974, 0.26999, 0.32758, 0.414738, 0.538638, 0.728106", \ - "0.207086, 0.359428, 0.419713, 0.496799, 0.598912, 0.750241, 0.969395" \ + "0.0069299, 0.040898, 0.0649449, 0.105501, 0.173619, 0.287217, 0.476667", \ + "0.017597, 0.0582378, 0.0809781, 0.11756, 0.180491, 0.289716, 0.477935", \ + "0.0262908, 0.0739402, 0.0985398, 0.136361, 0.197931, 0.30179, 0.482391", \ + "0.0418261, 0.101211, 0.128997, 0.17149, 0.235361, 0.338053, 0.510446", \ + "0.0689676, 0.147377, 0.181155, 0.230509, 0.301918, 0.41182, 0.584064", \ + "0.116671, 0.226978, 0.269996, 0.327591, 0.414739, 0.538665, 0.728148", \ + "0.207088, 0.359432, 0.419721, 0.49681, 0.599402, 0.75119, 0.9678" \ ); } } @@ -2689,52 +2689,52 @@ library (sg13g2_stdcell_fast_1p65V_m40C) { index_1 ("0.0186, 0.0966, 0.174, 0.3294, 0.6408, 1.263, 2.5074"); index_2 ("0.001, 0.0468, 0.078, 0.1296, 0.216, 0.36, 0.6"); values ( \ - "0.0216217, 0.0846718, 0.126141, 0.194474, 0.308724, 0.499202, 0.816094", \ - "0.0359276, 0.113443, 0.156583, 0.225257, 0.339367, 0.529552, 0.846904", \ - "0.0450246, 0.135465, 0.182979, 0.25508, 0.370269, 0.560205, 0.876808", \ - "0.0599671, 0.168465, 0.224341, 0.305766, 0.429232, 0.622892, 0.939318", \ - "0.0836034, 0.21747, 0.285309, 0.381863, 0.52421, 0.73658, 1.06383", \ - "0.121743, 0.289639, 0.373039, 0.492494, 0.663774, 0.913564, 1.28086", \ - "0.185417, 0.401262, 0.50474, 0.652908, 0.866688, 1.17067, 1.60525" \ + "0.0216226, 0.0846666, 0.126137, 0.194486, 0.308731, 0.499184, 0.816218", \ + "0.0359281, 0.113444, 0.156579, 0.225232, 0.339313, 0.529579, 0.847031", \ + "0.0450234, 0.135463, 0.182976, 0.255072, 0.370258, 0.560307, 0.876984", \ + "0.0599651, 0.168462, 0.224336, 0.305755, 0.429195, 0.622928, 0.939289", \ + "0.0835998, 0.217465, 0.285307, 0.381856, 0.524207, 0.736617, 1.06377", \ + "0.121735, 0.289631, 0.373029, 0.492484, 0.663761, 0.913545, 1.28074", \ + "0.185402, 0.401247, 0.504723, 0.652892, 0.866628, 1.17064, 1.60522" \ ); } rise_transition (TIMING_DELAY_7x7ds1) { index_1 ("0.0186, 0.0966, 0.174, 0.3294, 0.6408, 1.263, 2.5074"); index_2 ("0.001, 0.0468, 0.078, 0.1296, 0.216, 0.36, 0.6"); values ( \ - "0.0179138, 0.105186, 0.165747, 0.265695, 0.433113, 0.712095, 1.17729", \ - "0.0294137, 0.115695, 0.172061, 0.268252, 0.433883, 0.712096, 1.1773", \ - "0.0376543, 0.131478, 0.18697, 0.279361, 0.439034, 0.713565, 1.17735", \ - "0.0516953, 0.158893, 0.217986, 0.310396, 0.463999, 0.727361, 1.18398", \ - "0.07713, 0.203311, 0.270263, 0.370174, 0.527229, 0.78238, 1.21657", \ - "0.121279, 0.274858, 0.353032, 0.467489, 0.641877, 0.907196, 1.33497", \ - "0.20127, 0.392464, 0.487065, 0.623866, 0.825273, 1.12487, 1.58072" \ + "0.017916, 0.105182, 0.165742, 0.265705, 0.433137, 0.712081, 1.17703", \ + "0.0293065, 0.115695, 0.172054, 0.268234, 0.433428, 0.712082, 1.17718", \ + "0.037654, 0.131476, 0.186975, 0.279285, 0.439027, 0.71343, 1.17719", \ + "0.0516956, 0.158886, 0.217982, 0.310312, 0.463958, 0.727399, 1.18877", \ + "0.0771306, 0.203307, 0.27026, 0.370168, 0.526721, 0.782573, 1.2165", \ + "0.121281, 0.274861, 0.353029, 0.467483, 0.641868, 0.907178, 1.33483", \ + "0.201271, 0.392464, 0.487064, 0.623862, 0.825295, 1.12486, 1.58071" \ ); } cell_fall (TIMING_DELAY_7x7ds1) { index_1 ("0.0186, 0.0966, 0.174, 0.3294, 0.6408, 1.263, 2.5074"); index_2 ("0.001, 0.0468, 0.078, 0.1296, 0.216, 0.36, 0.6"); values ( \ - "0.0107179, 0.0408865, 0.0584723, 0.0873968, 0.135757, 0.216372, 0.35069", \ - "0.0165001, 0.067303, 0.0903646, 0.123691, 0.174461, 0.255623, 0.389939", \ - "0.0191618, 0.0836971, 0.111999, 0.151487, 0.208636, 0.294397, 0.4301", \ - "0.0214095, 0.106293, 0.142347, 0.192051, 0.261176, 0.359986, 0.506512", \ - "0.0214105, 0.133026, 0.179892, 0.243729, 0.332739, 0.454497, 0.627174", \ - "0.0214115, 0.161882, 0.225735, 0.310842, 0.42515, 0.583422, 0.799216", \ - "0.0214125, 0.186044, 0.2731, 0.388558, 0.543075, 0.748352, 1.0316" \ + "0.0107158, 0.0408864, 0.0584869, 0.0874179, 0.135789, 0.216381, 0.350729", \ + "0.0165014, 0.0673064, 0.0903696, 0.123699, 0.174467, 0.255644, 0.38998", \ + "0.0191634, 0.0837015, 0.112005, 0.151466, 0.208651, 0.294424, 0.43012", \ + "0.0214123, 0.106294, 0.142372, 0.192061, 0.26119, 0.360006, 0.50656", \ + "0.0214133, 0.132881, 0.179895, 0.243738, 0.332794, 0.454521, 0.627209", \ + "0.0214143, 0.161895, 0.22575, 0.310859, 0.425181, 0.583452, 0.799257", \ + "0.0214153, 0.186066, 0.273125, 0.388585, 0.543635, 0.748393, 1.03137" \ ); } fall_transition (TIMING_DELAY_7x7ds1) { index_1 ("0.0186, 0.0966, 0.174, 0.3294, 0.6408, 1.263, 2.5074"); index_2 ("0.001, 0.0468, 0.078, 0.1296, 0.216, 0.36, 0.6"); values ( \ - "0.00693241, 0.0408909, 0.0649392, 0.1054, 0.173585, 0.287186, 0.47662", \ - "0.0175966, 0.0582342, 0.0809723, 0.117551, 0.180482, 0.289702, 0.478033", \ - "0.0262903, 0.073937, 0.0985342, 0.13636, 0.197913, 0.301742, 0.482429", \ - "0.0418251, 0.101211, 0.129315, 0.17148, 0.235506, 0.338004, 0.510368", \ - "0.0689665, 0.147412, 0.181156, 0.230497, 0.301815, 0.411794, 0.584023", \ - "0.116668, 0.226974, 0.26999, 0.32758, 0.414738, 0.538638, 0.728106", \ - "0.207086, 0.359428, 0.419713, 0.496799, 0.598912, 0.750241, 0.969395" \ + "0.0069299, 0.040898, 0.0649449, 0.105501, 0.173619, 0.287217, 0.476667", \ + "0.017597, 0.0582378, 0.0809781, 0.11756, 0.180491, 0.289716, 0.477935", \ + "0.0262908, 0.0739402, 0.0985398, 0.136361, 0.197931, 0.30179, 0.482391", \ + "0.0418261, 0.101211, 0.128997, 0.17149, 0.235361, 0.338053, 0.510446", \ + "0.0689676, 0.147377, 0.181155, 0.230509, 0.301918, 0.41182, 0.584064", \ + "0.116671, 0.226978, 0.269996, 0.327591, 0.414739, 0.538665, 0.728148", \ + "0.207088, 0.359432, 0.419721, 0.49681, 0.599402, 0.75119, 0.9678" \ ); } } @@ -2744,26 +2744,26 @@ library (sg13g2_stdcell_fast_1p65V_m40C) { index_1 ("0.0186, 0.0966, 0.174, 0.3294, 0.6408, 1.263, 2.5074"); index_2 ("0.001, 0.0468, 0.078, 0.1296, 0.216, 0.36, 0.6"); values ( \ - "0.016878, 0.0188074, 0.0188695, 0.0187609, 0.0183491, 0.0176785, 0.016399", \ - "0.0186087, 0.01833, 0.0185257, 0.0185714, 0.018652, 0.0174884, 0.0161535", \ - "0.023186, 0.0201413, 0.0196299, 0.0195944, 0.0186854, 0.0177781, 0.0165622", \ - "0.0347308, 0.0267306, 0.0250859, 0.0231385, 0.0224021, 0.0197844, 0.0178421", \ - "0.0593944, 0.0452795, 0.0409244, 0.0365706, 0.0320622, 0.0284603, 0.0234053", \ - "0.109807, 0.0892259, 0.0811056, 0.071948, 0.0623417, 0.0521762, 0.0429427", \ - "0.211404, 0.18437, 0.172159, 0.156538, 0.137628, 0.119404, 0.0981105" \ + "0.0168756, 0.0188054, 0.0188688, 0.018764, 0.018354, 0.0175422, 0.0164012", \ + "0.0185957, 0.0182976, 0.0185788, 0.018752, 0.0186315, 0.0174555, 0.0162426", \ + "0.0231854, 0.0201142, 0.0196566, 0.0198146, 0.0186391, 0.0178325, 0.0165507", \ + "0.0347339, 0.0267309, 0.0250288, 0.0231206, 0.0225609, 0.0197544, 0.0195142", \ + "0.0593931, 0.0452793, 0.0409247, 0.0365491, 0.0318377, 0.0285273, 0.023568", \ + "0.109795, 0.0892292, 0.0810997, 0.071968, 0.0623301, 0.0524638, 0.0429958", \ + "0.21149, 0.184377, 0.172119, 0.15654, 0.137689, 0.119376, 0.0976806" \ ); } fall_power (POWER_7x7ds1) { index_1 ("0.0186, 0.0966, 0.174, 0.3294, 0.6408, 1.263, 2.5074"); index_2 ("0.001, 0.0468, 0.078, 0.1296, 0.216, 0.36, 0.6"); values ( \ - "0.00986874, 0.0106841, 0.0106372, 0.0102048, 0.00975863, 0.00902512, 0.0076494", \ - "0.0127561, 0.0110285, 0.0108424, 0.0103229, 0.0109467, 0.00893931, 0.00762742", \ - "0.0178738, 0.0136161, 0.0125462, 0.0117201, 0.0114121, 0.0109472, 0.00804678", \ - "0.0296475, 0.0207039, 0.0185666, 0.0163603, 0.0139373, 0.0131364, 0.0097686", \ - "0.0545015, 0.0396727, 0.0347275, 0.0297987, 0.0248881, 0.0198463, 0.0165569", \ - "0.105527, 0.0845713, 0.0755201, 0.0650077, 0.0544682, 0.0438513, 0.0339309", \ - "0.208023, 0.181012, 0.167729, 0.150959, 0.130218, 0.107367, 0.0853271" \ + "0.00986352, 0.0106986, 0.0106369, 0.0102015, 0.00977263, 0.00898391, 0.00776265", \ + "0.0127571, 0.0110185, 0.0108575, 0.0103035, 0.0106547, 0.00903425, 0.00758705", \ + "0.0178716, 0.0136299, 0.0126234, 0.0116969, 0.0113348, 0.0109425, 0.0079849", \ + "0.0296472, 0.0207008, 0.0185681, 0.0163582, 0.0138607, 0.0131422, 0.00951242", \ + "0.0544569, 0.0396695, 0.0347025, 0.0298145, 0.0248914, 0.0198412, 0.0165972", \ + "0.105528, 0.0845723, 0.0755213, 0.0650063, 0.0544692, 0.0439001, 0.0339245", \ + "0.208051, 0.181148, 0.167732, 0.15096, 0.130208, 0.107358, 0.0853278" \ ); } } @@ -2773,26 +2773,26 @@ library (sg13g2_stdcell_fast_1p65V_m40C) { index_1 ("0.0186, 0.0966, 0.174, 0.3294, 0.6408, 1.263, 2.5074"); index_2 ("0.001, 0.0468, 0.078, 0.1296, 0.216, 0.36, 0.6"); values ( \ - "0.01805, 0.0185842, 0.0184631, 0.0182066, 0.0177788, 0.0169493, 0.0157273", \ - "0.0193825, 0.0186364, 0.0188033, 0.0182441, 0.0182068, 0.0168646, 0.0157666", \ - "0.0237419, 0.0207047, 0.019998, 0.0198775, 0.0184847, 0.0173866, 0.0162294", \ - "0.0354257, 0.0277807, 0.0258061, 0.0236574, 0.0223074, 0.0196722, 0.0191005", \ - "0.0607926, 0.0476051, 0.0432642, 0.0383097, 0.0330811, 0.0290312, 0.0242463", \ - "0.112607, 0.0940488, 0.085909, 0.0759327, 0.0655446, 0.0547006, 0.0442702", \ - "0.217125, 0.192984, 0.181219, 0.165949, 0.147253, 0.124625, 0.102825" \ + "0.0180521, 0.0185261, 0.018463, 0.0181562, 0.0177782, 0.0169477, 0.0157269", \ + "0.0193839, 0.0186195, 0.0185269, 0.0185877, 0.0182499, 0.0170253, 0.0157672", \ + "0.0237428, 0.0206942, 0.0199897, 0.0195623, 0.0184644, 0.017319, 0.0161847", \ + "0.035433, 0.0277796, 0.0258012, 0.0236727, 0.0220317, 0.0196764, 0.0190823", \ + "0.0607889, 0.0476069, 0.043264, 0.0383289, 0.0331078, 0.0291169, 0.0240649", \ + "0.112589, 0.0940499, 0.085909, 0.07609, 0.0655622, 0.0546548, 0.0442924", \ + "0.217128, 0.192977, 0.18122, 0.165962, 0.147255, 0.124631, 0.103022" \ ); } fall_power (POWER_7x7ds1) { index_1 ("0.0186, 0.0966, 0.174, 0.3294, 0.6408, 1.263, 2.5074"); index_2 ("0.001, 0.0468, 0.078, 0.1296, 0.216, 0.36, 0.6"); values ( \ - "0.0169825, 0.0174442, 0.0173824, 0.0170679, 0.016625, 0.0158747, 0.0145612", \ - "0.0183547, 0.0176351, 0.0175231, 0.0170935, 0.0167402, 0.0159024, 0.0146323", \ - "0.0228341, 0.0196762, 0.0189699, 0.0181898, 0.018488, 0.0164668, 0.015435", \ - "0.0344884, 0.0264781, 0.024612, 0.0227413, 0.0205978, 0.0195044, 0.0166974", \ - "0.0599787, 0.0455551, 0.0407915, 0.0363147, 0.0315226, 0.0264323, 0.0236238", \ - "0.112415, 0.090962, 0.0823735, 0.0719257, 0.0613189, 0.0513826, 0.0413275", \ - "0.218619, 0.19051, 0.177376, 0.159925, 0.139182, 0.117146, 0.0960801" \ + "0.0169789, 0.0176668, 0.0173804, 0.0170799, 0.0166204, 0.0159399, 0.014714", \ + "0.0183547, 0.0176336, 0.0175205, 0.0171629, 0.0166701, 0.0159666, 0.0146645", \ + "0.0228337, 0.019678, 0.0189691, 0.0181904, 0.018488, 0.0173936, 0.015435", \ + "0.0344898, 0.0264819, 0.0246158, 0.0227536, 0.0205926, 0.0195077, 0.01669", \ + "0.0599798, 0.0455476, 0.0407879, 0.0362997, 0.0315133, 0.0266956, 0.0239282", \ + "0.112415, 0.0909618, 0.0823727, 0.0719284, 0.0612864, 0.0511363, 0.040487", \ + "0.218745, 0.190513, 0.177376, 0.159925, 0.139184, 0.117148, 0.0960805" \ ); } } @@ -2803,26 +2803,26 @@ library (sg13g2_stdcell_fast_1p65V_m40C) { index_1 ("0.0186, 0.0966, 0.174, 0.3294, 0.6408, 1.263, 2.5074"); index_2 ("0.001, 0.0468, 0.078, 0.1296, 0.216, 0.36, 0.6"); values ( \ - "0.00943674, 0.0106059, 0.010721, 0.0106321, 0.0102776, 0.0095728, 0.00836118", \ - "0.013703, 0.0115448, 0.0113711, 0.0109542, 0.0104075, 0.00959818, 0.0084241", \ - "0.0195499, 0.0148957, 0.0137334, 0.013028, 0.0114203, 0.010248, 0.0087431", \ - "0.03189, 0.0236175, 0.0212791, 0.0186277, 0.0161606, 0.0137125, 0.0114511", \ - "0.0580421, 0.0447765, 0.0404674, 0.0353366, 0.0296287, 0.0248476, 0.0189135", \ - "0.11042, 0.0905758, 0.0829061, 0.0740467, 0.0641426, 0.052916, 0.0417935", \ - "0.217024, 0.189978, 0.178749, 0.163083, 0.145845, 0.126163, 0.105091" \ + "0.00943081, 0.0106087, 0.0107209, 0.0106368, 0.0103535, 0.00965011, 0.00826233", \ + "0.0137095, 0.0115537, 0.011571, 0.0110138, 0.010301, 0.0096132, 0.00850816", \ + "0.0195498, 0.0148959, 0.013752, 0.012961, 0.0117167, 0.0102203, 0.00884361", \ + "0.0318953, 0.0236247, 0.0212639, 0.0184183, 0.0167735, 0.0137391, 0.0129204", \ + "0.0580389, 0.0447802, 0.0404685, 0.03537, 0.0294893, 0.0248502, 0.0189181", \ + "0.110419, 0.0905791, 0.0829049, 0.0740485, 0.0641356, 0.0529213, 0.041835", \ + "0.217029, 0.189979, 0.178729, 0.163077, 0.145828, 0.126168, 0.105101" \ ); } fall_power (POWER_7x7ds1) { index_1 ("0.0186, 0.0966, 0.174, 0.3294, 0.6408, 1.263, 2.5074"); index_2 ("0.001, 0.0468, 0.078, 0.1296, 0.216, 0.36, 0.6"); values ( \ - "0.0125655, 0.0145193, 0.0146233, 0.0142787, 0.0140484, 0.013361, 0.0121967", \ - "0.0167503, 0.0152374, 0.0148453, 0.0148311, 0.0152237, 0.0135941, 0.0130454", \ - "0.0225238, 0.0177141, 0.0171485, 0.0164359, 0.0152207, 0.0155735, 0.0126994", \ - "0.0352172, 0.0256105, 0.0233003, 0.0213682, 0.0193846, 0.0166264, 0.0160314", \ - "0.0616253, 0.0464011, 0.0404838, 0.0355432, 0.0305509, 0.0265371, 0.0219187", \ - "0.114974, 0.092193, 0.0831459, 0.0726856, 0.0617758, 0.0508586, 0.0424611", \ - "0.223168, 0.193381, 0.179464, 0.162123, 0.141411, 0.118657, 0.0974393" \ + "0.0125623, 0.0144677, 0.0144545, 0.0142991, 0.0140611, 0.0133601, 0.0121972", \ + "0.0167515, 0.015217, 0.0149843, 0.01481, 0.0146179, 0.0135507, 0.0135688", \ + "0.0225244, 0.0177204, 0.0171726, 0.0162775, 0.0152033, 0.015579, 0.0126944", \ + "0.0352177, 0.025611, 0.0232563, 0.0213152, 0.0195347, 0.0166921, 0.0161607", \ + "0.0617229, 0.0463811, 0.0404807, 0.0355257, 0.0306314, 0.0265574, 0.021974", \ + "0.115017, 0.0921943, 0.0831474, 0.0727671, 0.0617014, 0.0508275, 0.042399", \ + "0.2232, 0.193392, 0.179462, 0.16212, 0.141599, 0.118656, 0.0974428" \ ); } } @@ -2833,26 +2833,26 @@ library (sg13g2_stdcell_fast_1p65V_m40C) { index_1 ("0.0186, 0.0966, 0.174, 0.3294, 0.6408, 1.263, 2.5074"); index_2 ("0.001, 0.0468, 0.078, 0.1296, 0.216, 0.36, 0.6"); values ( \ - "0.00808851, 0.00947757, 0.00960375, 0.00951849, 0.00921774, 0.00854245, 0.00721304", \ - "0.0132553, 0.0104904, 0.0101872, 0.00987416, 0.00955752, 0.00843549, 0.00747713", \ - "0.0194826, 0.0139128, 0.0127243, 0.0117085, 0.0103664, 0.00913583, 0.007762", \ - "0.0323012, 0.0229073, 0.0203575, 0.0174491, 0.015811, 0.0126702, 0.0120806", \ - "0.0589834, 0.0443489, 0.0396833, 0.034341, 0.0285508, 0.0240031, 0.0171371", \ - "0.111851, 0.090571, 0.0828651, 0.0737131, 0.0632817, 0.0520264, 0.0407285", \ - "0.218808, 0.190065, 0.178541, 0.162501, 0.145212, 0.124798, 0.103873" \ + "0.00808408, 0.00953017, 0.00959806, 0.00954439, 0.00920349, 0.00854459, 0.00725202", \ + "0.0132558, 0.0104843, 0.0101543, 0.0098997, 0.0100884, 0.00843958, 0.00725448", \ + "0.0194834, 0.0139196, 0.0127484, 0.0116316, 0.0105197, 0.0090912, 0.00776875", \ + "0.0323, 0.0229089, 0.0203479, 0.0174424, 0.0153905, 0.0127259, 0.00974069", \ + "0.0589798, 0.0443499, 0.0395471, 0.0343916, 0.0283625, 0.023995, 0.0179209", \ + "0.11185, 0.0903451, 0.0828834, 0.073704, 0.0633027, 0.0519622, 0.0408617", \ + "0.21881, 0.190061, 0.178542, 0.1625, 0.145275, 0.124799, 0.104017" \ ); } fall_power (POWER_7x7ds1) { index_1 ("0.0186, 0.0966, 0.174, 0.3294, 0.6408, 1.263, 2.5074"); index_2 ("0.001, 0.0468, 0.078, 0.1296, 0.216, 0.36, 0.6"); values ( \ - "0.00569238, 0.00778564, 0.00761598, 0.00745867, 0.00714369, 0.00648141, 0.0051487", \ - "0.0100288, 0.00839057, 0.00812678, 0.00796028, 0.0082745, 0.00676263, 0.00632586", \ - "0.0159265, 0.0109829, 0.0103343, 0.00961706, 0.00837785, 0.00866747, 0.00600474", \ - "0.0287902, 0.0187157, 0.0165495, 0.0146112, 0.0127489, 0.010109, 0.00926119", \ - "0.0554663, 0.0397089, 0.033708, 0.0289688, 0.0237578, 0.0198444, 0.0152277", \ - "0.10898, 0.0854685, 0.076421, 0.0660262, 0.0547781, 0.0444107, 0.0357466", \ - "0.217674, 0.186347, 0.172791, 0.155422, 0.13453, 0.11184, 0.0914578" \ + "0.0056693, 0.0076379, 0.00762577, 0.0074595, 0.0072161, 0.00649425, 0.00515518", \ + "0.0100284, 0.00839124, 0.00813832, 0.00793547, 0.00859695, 0.00674597, 0.00630575", \ + "0.0159287, 0.0109832, 0.0103459, 0.00950149, 0.00839745, 0.00877489, 0.00602948", \ + "0.0287888, 0.0187481, 0.0165683, 0.0146121, 0.0127769, 0.0098006, 0.00914984", \ + "0.0554958, 0.0397061, 0.0337169, 0.0289604, 0.0238385, 0.0199016, 0.0142936", \ + "0.109114, 0.0854711, 0.0764221, 0.0660216, 0.0547779, 0.044429, 0.0355656", \ + "0.21734, 0.186275, 0.172798, 0.155407, 0.134476, 0.111841, 0.0914563" \ ); } } @@ -2863,26 +2863,26 @@ library (sg13g2_stdcell_fast_1p65V_m40C) { index_1 ("0.0186, 0.0966, 0.174, 0.3294, 0.6408, 1.263, 2.5074"); index_2 ("0.001, 0.0468, 0.078, 0.1296, 0.216, 0.36, 0.6"); values ( \ - "0.00825712, 0.00958911, 0.00969872, 0.00959882, 0.00918883, 0.00857813, 0.00710534", \ - "0.0139682, 0.0108049, 0.0105397, 0.00989333, 0.01004, 0.00921002, 0.00846004", \ - "0.0207925, 0.0147793, 0.0133859, 0.012391, 0.0109759, 0.00966956, 0.00774172", \ - "0.0347256, 0.0246455, 0.0216728, 0.018661, 0.0160769, 0.0129744, 0.0130014", \ - "0.0635947, 0.0479557, 0.0428751, 0.0373707, 0.0312595, 0.0251265, 0.0227088", \ - "0.121111, 0.0988609, 0.0899395, 0.0804032, 0.0692447, 0.057036, 0.0440874", \ - "0.237153, 0.207417, 0.194749, 0.178628, 0.158823, 0.137184, 0.112707" \ + "0.00825293, 0.00983356, 0.00969665, 0.00960828, 0.00918265, 0.00856546, 0.0084441", \ + "0.013966, 0.0107719, 0.0105394, 0.00989514, 0.0109148, 0.00866213, 0.0084589", \ + "0.0207906, 0.0147792, 0.0133097, 0.0123169, 0.0109578, 0.00976621, 0.0077081", \ + "0.0347233, 0.0246442, 0.021682, 0.0187452, 0.0160709, 0.0129717, 0.0130023", \ + "0.0635908, 0.0479597, 0.0428052, 0.0374116, 0.0312358, 0.025134, 0.0220074", \ + "0.121112, 0.0988629, 0.0899379, 0.0803359, 0.069249, 0.0570008, 0.0444367", \ + "0.237153, 0.207415, 0.194781, 0.178624, 0.158783, 0.137579, 0.112613" \ ); } fall_power (POWER_7x7ds1) { index_1 ("0.0186, 0.0966, 0.174, 0.3294, 0.6408, 1.263, 2.5074"); index_2 ("0.001, 0.0468, 0.078, 0.1296, 0.216, 0.36, 0.6"); values ( \ - "0.00528966, 0.00733542, 0.00719319, 0.0070525, 0.00680153, 0.00612678, 0.00475784", \ - "0.0103514, 0.00808244, 0.00777155, 0.00750109, 0.00776437, 0.00621785, 0.0058725", \ - "0.0168413, 0.0110262, 0.0101956, 0.00929068, 0.008139, 0.00832872, 0.00560389", \ - "0.0310134, 0.0198341, 0.0174062, 0.0151245, 0.012927, 0.00984899, 0.00901271", \ - "0.0601928, 0.0429924, 0.0364666, 0.0308965, 0.0254664, 0.0205689, 0.0157466", \ - "0.118681, 0.093102, 0.0831249, 0.071995, 0.060435, 0.0484207, 0.0385892", \ - "0.23624, 0.203845, 0.188454, 0.169696, 0.147304, 0.12224, 0.100051" \ + "0.00528132, 0.00734395, 0.00719368, 0.00714196, 0.00681243, 0.00612277, 0.00476237", \ + "0.0103521, 0.00808603, 0.00779291, 0.00753544, 0.00733159, 0.00617143, 0.00578908", \ + "0.0168407, 0.011019, 0.010193, 0.00928469, 0.00813376, 0.0084028, 0.00551271", \ + "0.0310148, 0.0198298, 0.0172686, 0.0151236, 0.0128203, 0.00974102, 0.00882666", \ + "0.0601931, 0.0429234, 0.0364194, 0.0308894, 0.0255059, 0.0206231, 0.0149026", \ + "0.118588, 0.0931021, 0.083129, 0.0719942, 0.0604411, 0.0484204, 0.0385248", \ + "0.236265, 0.204176, 0.188458, 0.169695, 0.147559, 0.122473, 0.0995794" \ ); } } @@ -2892,26 +2892,26 @@ library (sg13g2_stdcell_fast_1p65V_m40C) { index_1 ("0.0186, 0.0966, 0.174, 0.3294, 0.6408, 1.263, 2.5074"); index_2 ("0.001, 0.0468, 0.078, 0.1296, 0.216, 0.36, 0.6"); values ( \ - "0.00943674, 0.0106059, 0.010721, 0.0106321, 0.0102776, 0.0095728, 0.00836118", \ - "0.013703, 0.0115448, 0.0113711, 0.0109542, 0.0104075, 0.00959818, 0.0084241", \ - "0.0195499, 0.0148957, 0.0137334, 0.013028, 0.0114203, 0.010248, 0.0087431", \ - "0.03189, 0.0236175, 0.0212791, 0.0186277, 0.0161606, 0.0137125, 0.0114511", \ - "0.0580421, 0.0447765, 0.0404674, 0.0353366, 0.0296287, 0.0248476, 0.0189135", \ - "0.11042, 0.0905758, 0.0829061, 0.0740467, 0.0641426, 0.052916, 0.0417935", \ - "0.217024, 0.189978, 0.178749, 0.163083, 0.145845, 0.126163, 0.105091" \ + "0.00943081, 0.0106087, 0.0107209, 0.0106368, 0.0103535, 0.00965011, 0.00826233", \ + "0.0137095, 0.0115537, 0.011571, 0.0110138, 0.010301, 0.0096132, 0.00850816", \ + "0.0195498, 0.0148959, 0.013752, 0.012961, 0.0117167, 0.0102203, 0.00884361", \ + "0.0318953, 0.0236247, 0.0212639, 0.0184183, 0.0167735, 0.0137391, 0.0129204", \ + "0.0580389, 0.0447802, 0.0404685, 0.03537, 0.0294893, 0.0248502, 0.0189181", \ + "0.110419, 0.0905791, 0.0829049, 0.0740485, 0.0641356, 0.0529213, 0.041835", \ + "0.217029, 0.189979, 0.178729, 0.163077, 0.145828, 0.126168, 0.105101" \ ); } fall_power (POWER_7x7ds1) { index_1 ("0.0186, 0.0966, 0.174, 0.3294, 0.6408, 1.263, 2.5074"); index_2 ("0.001, 0.0468, 0.078, 0.1296, 0.216, 0.36, 0.6"); values ( \ - "0.00528966, 0.00733542, 0.00719319, 0.0070525, 0.00680153, 0.00612678, 0.00475784", \ - "0.0103514, 0.00808244, 0.00777155, 0.00750109, 0.00776437, 0.00621785, 0.0058725", \ - "0.0168413, 0.0110262, 0.0101956, 0.00929068, 0.008139, 0.00832872, 0.00560389", \ - "0.0310134, 0.0198341, 0.0174062, 0.0151245, 0.012927, 0.00984899, 0.00901271", \ - "0.0601928, 0.0429924, 0.0364666, 0.0308965, 0.0254664, 0.0205689, 0.0157466", \ - "0.118681, 0.093102, 0.0831249, 0.071995, 0.060435, 0.0484207, 0.0385892", \ - "0.23624, 0.203845, 0.188454, 0.169696, 0.147304, 0.12224, 0.100051" \ + "0.00528132, 0.00734395, 0.00719368, 0.00714196, 0.00681243, 0.00612277, 0.00476237", \ + "0.0103521, 0.00808603, 0.00779291, 0.00753544, 0.00733159, 0.00617143, 0.00578908", \ + "0.0168407, 0.011019, 0.010193, 0.00928469, 0.00813376, 0.0084028, 0.00551271", \ + "0.0310148, 0.0198298, 0.0172686, 0.0151236, 0.0128203, 0.00974102, 0.00882666", \ + "0.0601931, 0.0429234, 0.0364194, 0.0308894, 0.0255059, 0.0206231, 0.0149026", \ + "0.118588, 0.0931021, 0.083129, 0.0719942, 0.0604411, 0.0484204, 0.0385248", \ + "0.236265, 0.204176, 0.188458, 0.169695, 0.147559, 0.122473, 0.0995794" \ ); } } @@ -2919,29 +2919,29 @@ library (sg13g2_stdcell_fast_1p65V_m40C) { pin (A1) { direction : "input"; max_transition : 2.5074; - capacitance : 0.00648748; - rise_capacitance : 0.00620264; - rise_capacitance_range (0.00620264, 0.00620264); - fall_capacitance : 0.00677232; - fall_capacitance_range (0.00677232, 0.00677232); + capacitance : 0.00648746; + rise_capacitance : 0.00620263; + rise_capacitance_range (0.00571222, 0.00697317); + fall_capacitance : 0.00677229; + fall_capacitance_range (0.00561074, 0.007903); } pin (A2) { direction : "input"; max_transition : 2.5074; - capacitance : 0.0068959; - rise_capacitance : 0.0069616; - rise_capacitance_range (0.0069616, 0.0069616); - fall_capacitance : 0.0068302; - fall_capacitance_range (0.0068302, 0.0068302); + capacitance : 0.00689573; + rise_capacitance : 0.00696128; + rise_capacitance_range (0.00593967, 0.00773489); + fall_capacitance : 0.00683018; + fall_capacitance_range (0.00591115, 0.00743901); } pin (B1) { direction : "input"; max_transition : 2.5074; - capacitance : 0.00622251; - rise_capacitance : 0.00649178; - rise_capacitance_range (0.00649178, 0.00649178); - fall_capacitance : 0.00595324; - fall_capacitance_range (0.00595324, 0.00595324); + capacitance : 0.0062224; + rise_capacitance : 0.0064916; + rise_capacitance_range (0.00532462, 0.00934649); + fall_capacitance : 0.00595319; + fall_capacitance_range (0.00552051, 0.00672286); } } cell (sg13g2_a221oi_1) { @@ -5010,113 +5010,113 @@ library (sg13g2_stdcell_fast_1p65V_m40C) { max_transition : 2.5074; capacitance : 0.00330923; rise_capacitance : 0.00315745; - rise_capacitance_range (0.00315745, 0.00315745); + rise_capacitance_range (0.00295788, 0.00353722); fall_capacitance : 0.003461; - fall_capacitance_range (0.003461, 0.003461); + fall_capacitance_range (0.00289511, 0.00395972); } pin (A2) { direction : "input"; max_transition : 2.5074; capacitance : 0.00342087; rise_capacitance : 0.00343608; - rise_capacitance_range (0.00343608, 0.00343608); + rise_capacitance_range (0.00294884, 0.00377813); fall_capacitance : 0.00340567; - fall_capacitance_range (0.00340567, 0.00340567); + fall_capacitance_range (0.00293511, 0.00374133); } pin (B1) { direction : "input"; max_transition : 2.5074; capacitance : 0.00323747; rise_capacitance : 0.00317018; - rise_capacitance_range (0.00317018, 0.00317018); + rise_capacitance_range (0.00278477, 0.00383106); fall_capacitance : 0.00330476; - fall_capacitance_range (0.00330476, 0.00330476); + fall_capacitance_range (0.00275682, 0.00371766); } pin (B2) { direction : "input"; max_transition : 2.5074; capacitance : 0.00340885; rise_capacitance : 0.00350912; - rise_capacitance_range (0.00350912, 0.00350912); + rise_capacitance_range (0.00287925, 0.00413773); fall_capacitance : 0.00330858; - fall_capacitance_range (0.00330858, 0.00330858); + fall_capacitance_range (0.00285683, 0.00358841); } pin (C1) { direction : "input"; max_transition : 2.5074; capacitance : 0.00314112; rise_capacitance : 0.00330303; - rise_capacitance_range (0.00330303, 0.00330303); + rise_capacitance_range (0.0027179, 0.00476029); fall_capacitance : 0.00297922; - fall_capacitance_range (0.00297922, 0.00297922); + fall_capacitance_range (0.00279912, 0.00323503); } } cell (sg13g2_a22oi_1) { area : 10.8486; cell_footprint : "a22oi"; - cell_leakage_power : 1461.88; + cell_leakage_power : 1461.92; leakage_power () { - value : 766.292; + value : 766.33; when : "!A1&!A2&!B1&!B2&Y"; } leakage_power () { - value : 586.562; + value : 586.599; when : "!A1&!A2&!B1&B2&Y"; } leakage_power () { - value : 1245.88; + value : 1245.92; when : "!A1&!A2&B1&!B2&Y"; } leakage_power () { - value : 1823; + value : 1823.04; when : "!A1&!A2&B1&B2&!Y"; } leakage_power () { - value : 1246.02; + value : 1246.06; when : "!A1&A2&!B1&!B2&Y"; } leakage_power () { - value : 1066.29; + value : 1066.33; when : "!A1&A2&!B1&B2&Y"; } leakage_power () { - value : 1725.61; + value : 1725.65; when : "!A1&A2&B1&!B2&Y"; } leakage_power () { - value : 2295.34; + value : 2295.38; when : "!A1&A2&B1&B2&!Y"; } leakage_power () { - value : 586.527; + value : 586.565; when : "A1&!A2&!B1&!B2&Y"; } leakage_power () { - value : 406.797; + value : 406.834; when : "A1&!A2&!B1&B2&Y"; } leakage_power () { - value : 1066.12; + value : 1066.16; when : "A1&!A2&B1&!B2&Y"; } leakage_power () { - value : 2295.17; + value : 2295.21; when : "A1&!A2&B1&B2&!Y"; } leakage_power () { - value : 1416.91; + value : 1416.95; when : "A1&A2&!B1&!B2&!Y"; } leakage_power () { - value : 2092.86; + value : 2092.9; when : "A1&A2&!B1&B2&!Y"; } leakage_power () { - value : 2092.86; + value : 2092.9; when : "A1&A2&B1&!B2&!Y"; } leakage_power () { - value : 2677.79; + value : 2677.83; when : "A1&A2&B1&B2&!Y"; } pin (Y) { @@ -5134,52 +5134,52 @@ library (sg13g2_stdcell_fast_1p65V_m40C) { index_1 ("0.0186, 0.0966, 0.174, 0.3294, 0.6408, 1.263, 2.5074"); index_2 ("0.001, 0.0234, 0.039, 0.0648, 0.108, 0.18, 0.3"); values ( \ - "0.0265664, 0.0875211, 0.128818, 0.196873, 0.310734, 0.500541, 0.816564", \ - "0.0355477, 0.106235, 0.148869, 0.217466, 0.331518, 0.521314, 0.837447", \ - "0.0394164, 0.119933, 0.16537, 0.236264, 0.351267, 0.541112, 0.857326", \ - "0.045005, 0.140752, 0.19165, 0.268345, 0.388557, 0.580881, 0.897307", \ - "0.0516927, 0.170167, 0.230704, 0.318793, 0.450594, 0.654107, 0.977078", \ - "0.0560891, 0.209793, 0.283474, 0.389473, 0.544347, 0.770865, 1.11721", \ - "0.0560901, 0.255958, 0.351827, 0.48306, 0.670487, 0.941848, 1.33527" \ + "0.0265659, 0.08754, 0.128817, 0.196874, 0.310733, 0.500536, 0.816549", \ + "0.0355475, 0.106235, 0.14887, 0.21746, 0.33155, 0.521464, 0.837252", \ + "0.0394161, 0.119933, 0.165369, 0.236263, 0.351265, 0.541116, 0.857321", \ + "0.0450045, 0.140754, 0.191648, 0.268427, 0.388554, 0.580903, 0.897182", \ + "0.0516918, 0.170166, 0.230703, 0.318792, 0.450591, 0.654104, 0.977106", \ + "0.0560868, 0.209791, 0.28345, 0.38947, 0.54434, 0.770861, 1.11721", \ + "0.0560878, 0.255954, 0.351826, 0.483121, 0.670483, 0.941842, 1.33527" \ ); } rise_transition (TIMING_DELAY_7x7ds1) { index_1 ("0.0186, 0.0966, 0.174, 0.3294, 0.6408, 1.263, 2.5074"); index_2 ("0.001, 0.0234, 0.039, 0.0648, 0.108, 0.18, 0.3"); values ( \ - "0.0174281, 0.103153, 0.163379, 0.262818, 0.429637, 0.707699, 1.1708", \ - "0.0281319, 0.109391, 0.166998, 0.26438, 0.431624, 0.7077, 1.17081", \ - "0.0384267, 0.120392, 0.176427, 0.271066, 0.433197, 0.708492, 1.17082", \ - "0.0574003, 0.142347, 0.19875, 0.291182, 0.448615, 0.716661, 1.17472", \ - "0.0880595, 0.183004, 0.242458, 0.33649, 0.491355, 0.751195, 1.19471", \ - "0.138462, 0.253235, 0.319709, 0.420534, 0.580691, 0.839433, 1.27027", \ - "0.225373, 0.372962, 0.450801, 0.564725, 0.742853, 1.01469, 1.44894" \ + "0.017427, 0.10309, 0.163378, 0.262814, 0.429634, 0.707701, 1.17071", \ + "0.0281318, 0.10939, 0.166998, 0.264291, 0.42995, 0.707722, 1.17097", \ + "0.0384266, 0.120391, 0.176427, 0.271062, 0.433195, 0.708297, 1.17098", \ + "0.0574002, 0.142352, 0.198749, 0.291277, 0.44858, 0.716686, 1.1753", \ + "0.0880533, 0.183004, 0.242457, 0.336489, 0.491352, 0.751192, 1.19477", \ + "0.138463, 0.253237, 0.318724, 0.420532, 0.580684, 0.839432, 1.27027", \ + "0.225371, 0.372962, 0.450795, 0.564845, 0.742851, 1.01469, 1.44893" \ ); } cell_fall (TIMING_DELAY_7x7ds1) { index_1 ("0.0186, 0.0966, 0.174, 0.3294, 0.6408, 1.263, 2.5074"); index_2 ("0.001, 0.0234, 0.039, 0.0648, 0.108, 0.18, 0.3"); values ( \ - "0.0248151, 0.0721198, 0.103607, 0.155429, 0.241961, 0.386024, 0.626162", \ - "0.0407824, 0.102076, 0.136345, 0.189506, 0.276317, 0.420478, 0.660263", \ - "0.0512958, 0.123646, 0.162872, 0.221096, 0.311057, 0.455851, 0.695739", \ - "0.0668811, 0.155567, 0.202622, 0.270712, 0.371513, 0.524821, 0.768129", \ - "0.0873792, 0.198697, 0.256437, 0.339646, 0.459655, 0.635155, 0.897708", \ - "0.117602, 0.261287, 0.332486, 0.435373, 0.584155, 0.795165, 1.10225", \ - "0.163449, 0.350362, 0.442867, 0.57354, 0.755779, 1.0205, 1.39288" \ + "0.0248137, 0.0721245, 0.103628, 0.155407, 0.241963, 0.386045, 0.626183", \ + "0.0407829, 0.102078, 0.136347, 0.189507, 0.276327, 0.420315, 0.660309", \ + "0.0512964, 0.123648, 0.16288, 0.2211, 0.311085, 0.455854, 0.695857", \ + "0.0668819, 0.15557, 0.202609, 0.270707, 0.371517, 0.524848, 0.768151", \ + "0.0873806, 0.198699, 0.256439, 0.339649, 0.45966, 0.635138, 0.897706", \ + "0.117605, 0.26129, 0.33249, 0.435378, 0.58416, 0.795173, 1.10227", \ + "0.163454, 0.350368, 0.442872, 0.573547, 0.755788, 1.02051, 1.39289" \ ); } fall_transition (TIMING_DELAY_7x7ds1) { index_1 ("0.0186, 0.0966, 0.174, 0.3294, 0.6408, 1.263, 2.5074"); index_2 ("0.001, 0.0234, 0.039, 0.0648, 0.108, 0.18, 0.3"); values ( \ - "0.0199125, 0.0813073, 0.124923, 0.197219, 0.318194, 0.519495, 0.855061", \ - "0.0335817, 0.094435, 0.134567, 0.202438, 0.319987, 0.519803, 0.855563", \ - "0.0448782, 0.110818, 0.151404, 0.217398, 0.330005, 0.524127, 0.85637", \ - "0.0652646, 0.139598, 0.183511, 0.251618, 0.361961, 0.547928, 0.868457", \ - "0.0991937, 0.18942, 0.239508, 0.312565, 0.429677, 0.614393, 0.922221", \ - "0.156368, 0.274259, 0.333433, 0.418538, 0.545306, 0.744754, 1.05697", \ - "0.256488, 0.422878, 0.49751, 0.595725, 0.745718, 0.966106, 1.31002" \ + "0.0199003, 0.081309, 0.125059, 0.197184, 0.3182, 0.519722, 0.855077", \ + "0.0335819, 0.0944365, 0.134525, 0.202479, 0.319953, 0.52005, 0.85512", \ + "0.0448786, 0.110819, 0.151354, 0.217403, 0.330023, 0.524169, 0.855927", \ + "0.0652648, 0.1396, 0.183321, 0.25162, 0.36195, 0.547911, 0.86853", \ + "0.099194, 0.189421, 0.239511, 0.312568, 0.429682, 0.614369, 0.922228", \ + "0.156369, 0.27426, 0.333435, 0.418541, 0.545311, 0.744802, 1.05698", \ + "0.256489, 0.422879, 0.497504, 0.595787, 0.745617, 0.966114, 1.31001" \ ); } } @@ -5191,52 +5191,52 @@ library (sg13g2_stdcell_fast_1p65V_m40C) { index_1 ("0.0186, 0.0966, 0.174, 0.3294, 0.6408, 1.263, 2.5074"); index_2 ("0.001, 0.0234, 0.039, 0.0648, 0.108, 0.18, 0.3"); values ( \ - "0.0265664, 0.0875211, 0.128818, 0.196873, 0.310734, 0.500541, 0.816564", \ - "0.0355477, 0.106235, 0.148869, 0.217466, 0.331518, 0.521314, 0.837447", \ - "0.0394164, 0.119933, 0.16537, 0.236264, 0.351267, 0.541112, 0.857326", \ - "0.045005, 0.140752, 0.19165, 0.268345, 0.388557, 0.580881, 0.897307", \ - "0.0516927, 0.170167, 0.230704, 0.318793, 0.450594, 0.654107, 0.977078", \ - "0.0560891, 0.209793, 0.283474, 0.389473, 0.544347, 0.770865, 1.11721", \ - "0.0560901, 0.255958, 0.351827, 0.48306, 0.670487, 0.941848, 1.33527" \ + "0.0265659, 0.08754, 0.128817, 0.196874, 0.310733, 0.500536, 0.816549", \ + "0.0355475, 0.106235, 0.14887, 0.21746, 0.33155, 0.521464, 0.837252", \ + "0.0394161, 0.119933, 0.165369, 0.236263, 0.351265, 0.541116, 0.857321", \ + "0.0450045, 0.140754, 0.191648, 0.268427, 0.388554, 0.580903, 0.897182", \ + "0.0516918, 0.170166, 0.230703, 0.318792, 0.450591, 0.654104, 0.977106", \ + "0.0560868, 0.209791, 0.28345, 0.38947, 0.54434, 0.770861, 1.11721", \ + "0.0560878, 0.255954, 0.351826, 0.483121, 0.670483, 0.941842, 1.33527" \ ); } rise_transition (TIMING_DELAY_7x7ds1) { index_1 ("0.0186, 0.0966, 0.174, 0.3294, 0.6408, 1.263, 2.5074"); index_2 ("0.001, 0.0234, 0.039, 0.0648, 0.108, 0.18, 0.3"); values ( \ - "0.0174281, 0.103153, 0.163379, 0.262818, 0.429637, 0.707699, 1.1708", \ - "0.0281319, 0.109391, 0.166998, 0.26438, 0.431624, 0.7077, 1.17081", \ - "0.0384267, 0.120392, 0.176427, 0.271066, 0.433197, 0.708492, 1.17082", \ - "0.0574003, 0.142347, 0.19875, 0.291182, 0.448615, 0.716661, 1.17472", \ - "0.0880595, 0.183004, 0.242458, 0.33649, 0.491355, 0.751195, 1.19471", \ - "0.138462, 0.253235, 0.319709, 0.420534, 0.580691, 0.839433, 1.27027", \ - "0.225373, 0.372962, 0.450801, 0.564725, 0.742853, 1.01469, 1.44894" \ + "0.017427, 0.10309, 0.163378, 0.262814, 0.429634, 0.707701, 1.17071", \ + "0.0281318, 0.10939, 0.166998, 0.264291, 0.42995, 0.707722, 1.17097", \ + "0.0384266, 0.120391, 0.176427, 0.271062, 0.433195, 0.708297, 1.17098", \ + "0.0574002, 0.142352, 0.198749, 0.291277, 0.44858, 0.716686, 1.1753", \ + "0.0880533, 0.183004, 0.242457, 0.336489, 0.491352, 0.751192, 1.19477", \ + "0.138463, 0.253237, 0.318724, 0.420532, 0.580684, 0.839432, 1.27027", \ + "0.225371, 0.372962, 0.450795, 0.564845, 0.742851, 1.01469, 1.44893" \ ); } cell_fall (TIMING_DELAY_7x7ds1) { index_1 ("0.0186, 0.0966, 0.174, 0.3294, 0.6408, 1.263, 2.5074"); index_2 ("0.001, 0.0234, 0.039, 0.0648, 0.108, 0.18, 0.3"); values ( \ - "0.0248151, 0.0721198, 0.103607, 0.155429, 0.241961, 0.386024, 0.626162", \ - "0.0407824, 0.102076, 0.136345, 0.189506, 0.276317, 0.420478, 0.660263", \ - "0.0512958, 0.123646, 0.162872, 0.221096, 0.311057, 0.455851, 0.695739", \ - "0.0668811, 0.155567, 0.202622, 0.270712, 0.371513, 0.524821, 0.768129", \ - "0.0873792, 0.198697, 0.256437, 0.339646, 0.459655, 0.635155, 0.897708", \ - "0.117602, 0.261287, 0.332486, 0.435373, 0.584155, 0.795165, 1.10225", \ - "0.163449, 0.350362, 0.442867, 0.57354, 0.755779, 1.0205, 1.39288" \ + "0.0248137, 0.0721245, 0.103628, 0.155407, 0.241963, 0.386045, 0.626183", \ + "0.0407829, 0.102078, 0.136347, 0.189507, 0.276327, 0.420315, 0.660309", \ + "0.0512964, 0.123648, 0.16288, 0.2211, 0.311085, 0.455854, 0.695857", \ + "0.0668819, 0.15557, 0.202609, 0.270707, 0.371517, 0.524848, 0.768151", \ + "0.0873806, 0.198699, 0.256439, 0.339649, 0.45966, 0.635138, 0.897706", \ + "0.117605, 0.26129, 0.33249, 0.435378, 0.58416, 0.795173, 1.10227", \ + "0.163454, 0.350368, 0.442872, 0.573547, 0.755788, 1.02051, 1.39289" \ ); } fall_transition (TIMING_DELAY_7x7ds1) { index_1 ("0.0186, 0.0966, 0.174, 0.3294, 0.6408, 1.263, 2.5074"); index_2 ("0.001, 0.0234, 0.039, 0.0648, 0.108, 0.18, 0.3"); values ( \ - "0.0199125, 0.0813073, 0.124923, 0.197219, 0.318194, 0.519495, 0.855061", \ - "0.0335817, 0.094435, 0.134567, 0.202438, 0.319987, 0.519803, 0.855563", \ - "0.0448782, 0.110818, 0.151404, 0.217398, 0.330005, 0.524127, 0.85637", \ - "0.0652646, 0.139598, 0.183511, 0.251618, 0.361961, 0.547928, 0.868457", \ - "0.0991937, 0.18942, 0.239508, 0.312565, 0.429677, 0.614393, 0.922221", \ - "0.156368, 0.274259, 0.333433, 0.418538, 0.545306, 0.744754, 1.05697", \ - "0.256488, 0.422878, 0.49751, 0.595725, 0.745718, 0.966106, 1.31002" \ + "0.0199003, 0.081309, 0.125059, 0.197184, 0.3182, 0.519722, 0.855077", \ + "0.0335819, 0.0944365, 0.134525, 0.202479, 0.319953, 0.52005, 0.85512", \ + "0.0448786, 0.110819, 0.151354, 0.217403, 0.330023, 0.524169, 0.855927", \ + "0.0652648, 0.1396, 0.183321, 0.25162, 0.36195, 0.547911, 0.86853", \ + "0.099194, 0.189421, 0.239511, 0.312568, 0.429682, 0.614369, 0.922228", \ + "0.156369, 0.27426, 0.333435, 0.418541, 0.545311, 0.744802, 1.05698", \ + "0.256489, 0.422879, 0.497504, 0.595787, 0.745617, 0.966114, 1.31001" \ ); } } @@ -5250,52 +5250,52 @@ library (sg13g2_stdcell_fast_1p65V_m40C) { index_1 ("0.0186, 0.0966, 0.174, 0.3294, 0.6408, 1.263, 2.5074"); index_2 ("0.001, 0.0234, 0.039, 0.0648, 0.108, 0.18, 0.3"); values ( \ - "0.0305449, 0.0903404, 0.131292, 0.198877, 0.31204, 0.500498, 0.814685", \ - "0.0417565, 0.109962, 0.152007, 0.22003, 0.33326, 0.521801, 0.835768", \ - "0.0473204, 0.124379, 0.169117, 0.239209, 0.353289, 0.541893, 0.856068", \ - "0.0568441, 0.146519, 0.196499, 0.272255, 0.391281, 0.582276, 0.896527", \ - "0.0718488, 0.17987, 0.238422, 0.32474, 0.454458, 0.656946, 0.977285", \ - "0.0919554, 0.228955, 0.299029, 0.400616, 0.552763, 0.775204, 1.11953", \ - "0.118925, 0.298282, 0.385406, 0.510236, 0.692095, 0.954463, 1.34358" \ + "0.0305443, 0.0903667, 0.131294, 0.198878, 0.312044, 0.500503, 0.81469", \ + "0.0418084, 0.109962, 0.152042, 0.220024, 0.333225, 0.521982, 0.835813", \ + "0.0473207, 0.12438, 0.169118, 0.239199, 0.353297, 0.541881, 0.856075", \ + "0.0568442, 0.14652, 0.1965, 0.272256, 0.391281, 0.582272, 0.896455", \ + "0.0718488, 0.179871, 0.238424, 0.324741, 0.45446, 0.656871, 0.977292", \ + "0.091955, 0.228956, 0.299031, 0.400619, 0.552765, 0.775208, 1.11954", \ + "0.118924, 0.298283, 0.385407, 0.510318, 0.692097, 0.954471, 1.34229" \ ); } rise_transition (TIMING_DELAY_7x7ds1) { index_1 ("0.0186, 0.0966, 0.174, 0.3294, 0.6408, 1.263, 2.5074"); index_2 ("0.001, 0.0234, 0.039, 0.0648, 0.108, 0.18, 0.3"); values ( \ - "0.0217181, 0.107659, 0.167144, 0.266148, 0.431895, 0.708006, 1.16842", \ - "0.0321027, 0.113408, 0.170738, 0.267628, 0.433715, 0.70807, 1.16868", \ - "0.0420965, 0.124223, 0.180201, 0.274313, 0.435504, 0.710406, 1.16869", \ - "0.0600983, 0.146254, 0.20226, 0.294403, 0.450905, 0.717343, 1.17383", \ - "0.08928, 0.186353, 0.244419, 0.339747, 0.493374, 0.75193, 1.1927", \ - "0.138273, 0.254255, 0.320476, 0.420066, 0.581687, 0.839012, 1.26893", \ - "0.221132, 0.368755, 0.447473, 0.562715, 0.738115, 1.00785, 1.44509" \ + "0.0217145, 0.107271, 0.167149, 0.266149, 0.431898, 0.707988, 1.16843", \ + "0.0321277, 0.113409, 0.170741, 0.267566, 0.432458, 0.708266, 1.16867", \ + "0.0420966, 0.124232, 0.180202, 0.27429, 0.435511, 0.709037, 1.16868", \ + "0.0600986, 0.146255, 0.202261, 0.294405, 0.450906, 0.71731, 1.17271", \ + "0.0892804, 0.186354, 0.24442, 0.339749, 0.493377, 0.751847, 1.1927", \ + "0.138274, 0.254256, 0.320478, 0.420048, 0.58169, 0.839016, 1.26895", \ + "0.221132, 0.368757, 0.447475, 0.562442, 0.738118, 1.00789, 1.44416" \ ); } cell_fall (TIMING_DELAY_7x7ds1) { index_1 ("0.0186, 0.0966, 0.174, 0.3294, 0.6408, 1.263, 2.5074"); index_2 ("0.001, 0.0234, 0.039, 0.0648, 0.108, 0.18, 0.3"); values ( \ - "0.025728, 0.0727682, 0.10426, 0.156044, 0.242675, 0.386672, 0.627056", \ - "0.0377791, 0.0938512, 0.127162, 0.179927, 0.266776, 0.410952, 0.65097", \ - "0.0455862, 0.110383, 0.146509, 0.202311, 0.29123, 0.435958, 0.676121", \ - "0.05648, 0.135324, 0.177457, 0.23921, 0.334629, 0.4845, 0.726724", \ - "0.0688681, 0.169099, 0.219432, 0.29311, 0.400851, 0.564487, 0.818089", \ - "0.0840312, 0.213792, 0.278951, 0.368053, 0.498778, 0.687908, 0.968567", \ - "0.0995088, 0.269938, 0.355755, 0.472591, 0.635102, 0.864351, 1.19559" \ + "0.0257276, 0.0727644, 0.104262, 0.156052, 0.242603, 0.386683, 0.627071", \ + "0.0377796, 0.0938526, 0.127154, 0.179929, 0.266773, 0.410972, 0.650977", \ + "0.0455868, 0.110384, 0.146508, 0.202313, 0.291235, 0.435973, 0.676132", \ + "0.0564809, 0.135325, 0.17746, 0.239212, 0.334636, 0.484507, 0.726729", \ + "0.0688694, 0.169101, 0.219434, 0.293114, 0.400857, 0.564704, 0.818157", \ + "0.0840335, 0.213795, 0.278954, 0.368058, 0.498783, 0.687917, 0.968577", \ + "0.0995121, 0.269943, 0.355761, 0.472598, 0.63511, 0.864362, 1.19561" \ ); } fall_transition (TIMING_DELAY_7x7ds1) { index_1 ("0.0186, 0.0966, 0.174, 0.3294, 0.6408, 1.263, 2.5074"); index_2 ("0.001, 0.0234, 0.039, 0.0648, 0.108, 0.18, 0.3"); values ( \ - "0.0191694, 0.081236, 0.124975, 0.197163, 0.318192, 0.519474, 0.855511", \ - "0.0294585, 0.0893344, 0.130592, 0.200312, 0.319156, 0.519646, 0.855512", \ - "0.0403915, 0.100465, 0.141476, 0.209241, 0.325167, 0.522294, 0.856922", \ - "0.0599286, 0.123521, 0.164338, 0.232096, 0.344686, 0.536322, 0.862947", \ - "0.0918108, 0.166724, 0.209156, 0.277926, 0.391216, 0.57792, 0.894741", \ - "0.14636, 0.245032, 0.291284, 0.36572, 0.482323, 0.67053, 0.982661", \ - "0.239416, 0.377742, 0.439908, 0.523835, 0.651435, 0.850665, 1.16534" \ + "0.0191692, 0.0812775, 0.124977, 0.197135, 0.318176, 0.519484, 0.855526", \ + "0.0294589, 0.0893358, 0.130606, 0.200312, 0.319163, 0.519965, 0.855527", \ + "0.0403918, 0.100466, 0.14145, 0.209245, 0.325173, 0.522312, 0.856934", \ + "0.0599291, 0.123522, 0.164341, 0.232099, 0.344735, 0.536331, 0.862955", \ + "0.0918115, 0.166726, 0.209158, 0.27793, 0.391222, 0.578415, 0.894826", \ + "0.146357, 0.245036, 0.291287, 0.365724, 0.482329, 0.670539, 0.982649", \ + "0.239417, 0.377741, 0.439911, 0.523838, 0.651442, 0.850674, 1.1653" \ ); } } @@ -5307,52 +5307,52 @@ library (sg13g2_stdcell_fast_1p65V_m40C) { index_1 ("0.0186, 0.0966, 0.174, 0.3294, 0.6408, 1.263, 2.5074"); index_2 ("0.001, 0.0234, 0.039, 0.0648, 0.108, 0.18, 0.3"); values ( \ - "0.0305449, 0.0903404, 0.131292, 0.198877, 0.31204, 0.500498, 0.814685", \ - "0.0417565, 0.109962, 0.152007, 0.22003, 0.33326, 0.521801, 0.835768", \ - "0.0473204, 0.124379, 0.169117, 0.239209, 0.353289, 0.541893, 0.856068", \ - "0.0568441, 0.146519, 0.196499, 0.272255, 0.391281, 0.582276, 0.896527", \ - "0.0718488, 0.17987, 0.238422, 0.32474, 0.454458, 0.656946, 0.977285", \ - "0.0919554, 0.228955, 0.299029, 0.400616, 0.552763, 0.775204, 1.11953", \ - "0.118925, 0.298282, 0.385406, 0.510236, 0.692095, 0.954463, 1.34358" \ + "0.0305443, 0.0903667, 0.131294, 0.198878, 0.312044, 0.500503, 0.81469", \ + "0.0418084, 0.109962, 0.152042, 0.220024, 0.333225, 0.521982, 0.835813", \ + "0.0473207, 0.12438, 0.169118, 0.239199, 0.353297, 0.541881, 0.856075", \ + "0.0568442, 0.14652, 0.1965, 0.272256, 0.391281, 0.582272, 0.896455", \ + "0.0718488, 0.179871, 0.238424, 0.324741, 0.45446, 0.656871, 0.977292", \ + "0.091955, 0.228956, 0.299031, 0.400619, 0.552765, 0.775208, 1.11954", \ + "0.118924, 0.298283, 0.385407, 0.510318, 0.692097, 0.954471, 1.34229" \ ); } rise_transition (TIMING_DELAY_7x7ds1) { index_1 ("0.0186, 0.0966, 0.174, 0.3294, 0.6408, 1.263, 2.5074"); index_2 ("0.001, 0.0234, 0.039, 0.0648, 0.108, 0.18, 0.3"); values ( \ - "0.0217181, 0.107659, 0.167144, 0.266148, 0.431895, 0.708006, 1.16842", \ - "0.0321027, 0.113408, 0.170738, 0.267628, 0.433715, 0.70807, 1.16868", \ - "0.0420965, 0.124223, 0.180201, 0.274313, 0.435504, 0.710406, 1.16869", \ - "0.0600983, 0.146254, 0.20226, 0.294403, 0.450905, 0.717343, 1.17383", \ - "0.08928, 0.186353, 0.244419, 0.339747, 0.493374, 0.75193, 1.1927", \ - "0.138273, 0.254255, 0.320476, 0.420066, 0.581687, 0.839012, 1.26893", \ - "0.221132, 0.368755, 0.447473, 0.562715, 0.738115, 1.00785, 1.44509" \ + "0.0217145, 0.107271, 0.167149, 0.266149, 0.431898, 0.707988, 1.16843", \ + "0.0321277, 0.113409, 0.170741, 0.267566, 0.432458, 0.708266, 1.16867", \ + "0.0420966, 0.124232, 0.180202, 0.27429, 0.435511, 0.709037, 1.16868", \ + "0.0600986, 0.146255, 0.202261, 0.294405, 0.450906, 0.71731, 1.17271", \ + "0.0892804, 0.186354, 0.24442, 0.339749, 0.493377, 0.751847, 1.1927", \ + "0.138274, 0.254256, 0.320478, 0.420048, 0.58169, 0.839016, 1.26895", \ + "0.221132, 0.368757, 0.447475, 0.562442, 0.738118, 1.00789, 1.44416" \ ); } cell_fall (TIMING_DELAY_7x7ds1) { index_1 ("0.0186, 0.0966, 0.174, 0.3294, 0.6408, 1.263, 2.5074"); index_2 ("0.001, 0.0234, 0.039, 0.0648, 0.108, 0.18, 0.3"); values ( \ - "0.025728, 0.0727682, 0.10426, 0.156044, 0.242675, 0.386672, 0.627056", \ - "0.0377791, 0.0938512, 0.127162, 0.179927, 0.266776, 0.410952, 0.65097", \ - "0.0455862, 0.110383, 0.146509, 0.202311, 0.29123, 0.435958, 0.676121", \ - "0.05648, 0.135324, 0.177457, 0.23921, 0.334629, 0.4845, 0.726724", \ - "0.0688681, 0.169099, 0.219432, 0.29311, 0.400851, 0.564487, 0.818089", \ - "0.0840312, 0.213792, 0.278951, 0.368053, 0.498778, 0.687908, 0.968567", \ - "0.0995088, 0.269938, 0.355755, 0.472591, 0.635102, 0.864351, 1.19559" \ + "0.0257276, 0.0727644, 0.104262, 0.156052, 0.242603, 0.386683, 0.627071", \ + "0.0377796, 0.0938526, 0.127154, 0.179929, 0.266773, 0.410972, 0.650977", \ + "0.0455868, 0.110384, 0.146508, 0.202313, 0.291235, 0.435973, 0.676132", \ + "0.0564809, 0.135325, 0.17746, 0.239212, 0.334636, 0.484507, 0.726729", \ + "0.0688694, 0.169101, 0.219434, 0.293114, 0.400857, 0.564704, 0.818157", \ + "0.0840335, 0.213795, 0.278954, 0.368058, 0.498783, 0.687917, 0.968577", \ + "0.0995121, 0.269943, 0.355761, 0.472598, 0.63511, 0.864362, 1.19561" \ ); } fall_transition (TIMING_DELAY_7x7ds1) { index_1 ("0.0186, 0.0966, 0.174, 0.3294, 0.6408, 1.263, 2.5074"); index_2 ("0.001, 0.0234, 0.039, 0.0648, 0.108, 0.18, 0.3"); values ( \ - "0.0191694, 0.081236, 0.124975, 0.197163, 0.318192, 0.519474, 0.855511", \ - "0.0294585, 0.0893344, 0.130592, 0.200312, 0.319156, 0.519646, 0.855512", \ - "0.0403915, 0.100465, 0.141476, 0.209241, 0.325167, 0.522294, 0.856922", \ - "0.0599286, 0.123521, 0.164338, 0.232096, 0.344686, 0.536322, 0.862947", \ - "0.0918108, 0.166724, 0.209156, 0.277926, 0.391216, 0.57792, 0.894741", \ - "0.14636, 0.245032, 0.291284, 0.36572, 0.482323, 0.67053, 0.982661", \ - "0.239416, 0.377742, 0.439908, 0.523835, 0.651435, 0.850665, 1.16534" \ + "0.0191692, 0.0812775, 0.124977, 0.197135, 0.318176, 0.519484, 0.855526", \ + "0.0294589, 0.0893358, 0.130606, 0.200312, 0.319163, 0.519965, 0.855527", \ + "0.0403918, 0.100466, 0.14145, 0.209245, 0.325173, 0.522312, 0.856934", \ + "0.0599291, 0.123522, 0.164341, 0.232099, 0.344735, 0.536331, 0.862955", \ + "0.0918115, 0.166726, 0.209158, 0.27793, 0.391222, 0.578415, 0.894826", \ + "0.146357, 0.245036, 0.291287, 0.365724, 0.482329, 0.670539, 0.982649", \ + "0.239417, 0.377741, 0.439911, 0.523838, 0.651442, 0.850674, 1.1653" \ ); } } @@ -5366,52 +5366,52 @@ library (sg13g2_stdcell_fast_1p65V_m40C) { index_1 ("0.0186, 0.0966, 0.174, 0.3294, 0.6408, 1.263, 2.5074"); index_2 ("0.001, 0.0234, 0.039, 0.0648, 0.108, 0.18, 0.3"); values ( \ - "0.0296085, 0.0901144, 0.131404, 0.199471, 0.313348, 0.503087, 0.819235", \ - "0.0475904, 0.119469, 0.162129, 0.230511, 0.344259, 0.533864, 0.850545", \ - "0.0586169, 0.141788, 0.18876, 0.260296, 0.37508, 0.564436, 0.880123", \ - "0.0757387, 0.175473, 0.23034, 0.311204, 0.43387, 0.626856, 0.942476", \ - "0.102676, 0.224439, 0.290476, 0.385906, 0.528112, 0.739663, 1.06641", \ - "0.144641, 0.296128, 0.377499, 0.494665, 0.665163, 0.913989, 1.28101", \ - "0.21139, 0.406064, 0.506156, 0.651372, 0.861488, 1.16417, 1.59845" \ + "0.0296076, 0.0901099, 0.131411, 0.199488, 0.313346, 0.503114, 0.819228", \ + "0.0475906, 0.119462, 0.162118, 0.230491, 0.344252, 0.533897, 0.849762", \ + "0.0586172, 0.141788, 0.188761, 0.260297, 0.375095, 0.564434, 0.880129", \ + "0.0757393, 0.175473, 0.230344, 0.311205, 0.433872, 0.626859, 0.942481", \ + "0.102677, 0.224574, 0.290477, 0.385908, 0.528114, 0.739666, 1.06635", \ + "0.1447, 0.296129, 0.377502, 0.494665, 0.665196, 0.913993, 1.28101", \ + "0.211394, 0.406068, 0.506193, 0.651376, 0.861493, 1.16417, 1.59846" \ ); } rise_transition (TIMING_DELAY_7x7ds1) { index_1 ("0.0186, 0.0966, 0.174, 0.3294, 0.6408, 1.263, 2.5074"); index_2 ("0.001, 0.0234, 0.039, 0.0648, 0.108, 0.18, 0.3"); values ( \ - "0.0269089, 0.113026, 0.173283, 0.273001, 0.439864, 0.717908, 1.18148", \ - "0.040385, 0.122767, 0.179243, 0.275369, 0.440632, 0.717909, 1.18167", \ - "0.050862, 0.138786, 0.194048, 0.286223, 0.445661, 0.718905, 1.18168", \ - "0.0677149, 0.16759, 0.225579, 0.317375, 0.470397, 0.733026, 1.19262", \ - "0.0956571, 0.214621, 0.28, 0.378902, 0.534203, 0.788671, 1.22099", \ - "0.14433, 0.290439, 0.368182, 0.481271, 0.65262, 0.915958, 1.34015", \ - "0.230358, 0.414822, 0.510183, 0.646681, 0.845106, 1.1432, 1.5938" \ + "0.0269189, 0.113026, 0.17331, 0.273023, 0.439867, 0.71789, 1.18149", \ + "0.0403853, 0.122763, 0.179181, 0.275344, 0.440462, 0.717899, 1.18155", \ + "0.050862, 0.138786, 0.194049, 0.286224, 0.445704, 0.718911, 1.18156", \ + "0.0677151, 0.167591, 0.225581, 0.317379, 0.470393, 0.733031, 1.19358", \ + "0.095657, 0.214543, 0.28, 0.378904, 0.534205, 0.788678, 1.22094", \ + "0.144216, 0.29044, 0.368182, 0.481256, 0.652648, 0.915961, 1.34016", \ + "0.230357, 0.414822, 0.510147, 0.646681, 0.845108, 1.1432, 1.59382" \ ); } cell_fall (TIMING_DELAY_7x7ds1) { index_1 ("0.0186, 0.0966, 0.174, 0.3294, 0.6408, 1.263, 2.5074"); index_2 ("0.001, 0.0234, 0.039, 0.0648, 0.108, 0.18, 0.3"); values ( \ - "0.0207074, 0.0683544, 0.100079, 0.152148, 0.238676, 0.382709, 0.622698", \ - "0.0296346, 0.0888394, 0.122745, 0.175978, 0.262939, 0.40706, 0.647088", \ - "0.0348893, 0.104537, 0.141586, 0.198041, 0.287202, 0.432107, 0.672173", \ - "0.0412488, 0.127819, 0.171022, 0.234087, 0.330145, 0.480272, 0.722822", \ - "0.0460831, 0.157269, 0.20999, 0.285182, 0.394716, 0.559324, 0.813665", \ - "0.0460841, 0.191099, 0.26043, 0.354359, 0.488012, 0.679206, 0.96228", \ - "0.0460851, 0.21937, 0.312869, 0.438555, 0.610289, 0.846307, 1.1828" \ + "0.0207071, 0.0683446, 0.100075, 0.152117, 0.238675, 0.382731, 0.622687", \ + "0.0296341, 0.0888379, 0.122738, 0.175977, 0.262935, 0.407054, 0.647077", \ + "0.0348887, 0.104536, 0.141584, 0.198038, 0.287209, 0.432107, 0.67216", \ + "0.0412478, 0.127817, 0.171192, 0.234082, 0.33014, 0.480261, 0.722834", \ + "0.0460814, 0.157266, 0.209987, 0.28518, 0.39471, 0.559316, 0.813626", \ + "0.0460824, 0.191096, 0.260425, 0.354353, 0.488004, 0.679195, 0.962265", \ + "0.0460834, 0.219368, 0.312861, 0.438543, 0.610276, 0.846293, 1.18279" \ ); } fall_transition (TIMING_DELAY_7x7ds1) { index_1 ("0.0186, 0.0966, 0.174, 0.3294, 0.6408, 1.263, 2.5074"); index_2 ("0.001, 0.0234, 0.039, 0.0648, 0.108, 0.18, 0.3"); values ( \ - "0.0175375, 0.0787049, 0.12224, 0.194338, 0.315199, 0.516666, 0.852218", \ - "0.0293186, 0.0871934, 0.128197, 0.197656, 0.316331, 0.516765, 0.852219", \ - "0.0413226, 0.0985904, 0.139274, 0.206805, 0.322356, 0.519156, 0.852762", \ - "0.0626224, 0.122279, 0.162515, 0.229729, 0.342359, 0.533463, 0.860151", \ - "0.0972583, 0.166927, 0.208689, 0.275769, 0.388694, 0.575751, 0.892032", \ - "0.153728, 0.246139, 0.292757, 0.365457, 0.479543, 0.668337, 0.980503", \ - "0.249198, 0.379846, 0.442087, 0.527657, 0.653873, 0.848979, 1.16388" \ + "0.0175366, 0.0787036, 0.122237, 0.194319, 0.315193, 0.516439, 0.852184", \ + "0.0293183, 0.0871919, 0.128191, 0.197656, 0.316352, 0.516755, 0.852298", \ + "0.0413221, 0.0985888, 0.139272, 0.206747, 0.322344, 0.519342, 0.852658", \ + "0.0626219, 0.122277, 0.162513, 0.22973, 0.342347, 0.533536, 0.859903", \ + "0.0972575, 0.166928, 0.208686, 0.27587, 0.388688, 0.575741, 0.891958", \ + "0.153727, 0.246135, 0.292754, 0.365453, 0.479537, 0.668305, 0.980626", \ + "0.249196, 0.379656, 0.442084, 0.52849, 0.653056, 0.84897, 1.16432" \ ); } } @@ -5425,52 +5425,52 @@ library (sg13g2_stdcell_fast_1p65V_m40C) { index_1 ("0.0186, 0.0966, 0.174, 0.3294, 0.6408, 1.263, 2.5074"); index_2 ("0.001, 0.0234, 0.039, 0.0648, 0.108, 0.18, 0.3"); values ( \ - "0.0247913, 0.08506, 0.126043, 0.193718, 0.306786, 0.495661, 0.809695", \ - "0.0404899, 0.114048, 0.156726, 0.224735, 0.337795, 0.526262, 0.840146", \ - "0.0500552, 0.135843, 0.182905, 0.254365, 0.368598, 0.556939, 0.870513", \ - "0.0652862, 0.168287, 0.223367, 0.304475, 0.427059, 0.619177, 0.933187", \ - "0.0891211, 0.215527, 0.282291, 0.378568, 0.520588, 0.731612, 1.05658", \ - "0.1268, 0.284806, 0.367049, 0.485204, 0.65612, 0.904407, 1.27037", \ - "0.187941, 0.39144, 0.493329, 0.638494, 0.850766, 1.15375, 1.58576" \ + "0.0247855, 0.0850878, 0.12606, 0.193705, 0.30679, 0.495658, 0.809685", \ + "0.0404898, 0.114037, 0.156715, 0.224797, 0.337787, 0.52612, 0.840138", \ + "0.0500551, 0.135841, 0.182945, 0.254364, 0.368594, 0.556896, 0.870535", \ + "0.0652862, 0.168286, 0.223366, 0.304474, 0.427057, 0.619191, 0.932971", \ + "0.0891212, 0.215526, 0.28229, 0.378567, 0.520586, 0.731609, 1.05657", \ + "0.1268, 0.284805, 0.367048, 0.485203, 0.656119, 0.904404, 1.27037", \ + "0.187943, 0.39144, 0.493329, 0.638493, 0.850764, 1.15375, 1.58575" \ ); } rise_transition (TIMING_DELAY_7x7ds1) { index_1 ("0.0186, 0.0966, 0.174, 0.3294, 0.6408, 1.263, 2.5074"); index_2 ("0.001, 0.0234, 0.039, 0.0648, 0.108, 0.18, 0.3"); values ( \ - "0.0226851, 0.107518, 0.167361, 0.26637, 0.432225, 0.708326, 1.16887", \ - "0.0357655, 0.117867, 0.173673, 0.268844, 0.433161, 0.708327, 1.16888", \ - "0.0452508, 0.133961, 0.188701, 0.280064, 0.438231, 0.709716, 1.16889", \ - "0.0613417, 0.162486, 0.220368, 0.31132, 0.463341, 0.723786, 1.18137", \ - "0.0885181, 0.209158, 0.274575, 0.373188, 0.527779, 0.779945, 1.20894", \ - "0.135512, 0.284698, 0.361807, 0.474816, 0.645526, 0.907623, 1.32948", \ - "0.217349, 0.407369, 0.502802, 0.640524, 0.838679, 1.13301, 1.58063" \ + "0.0226762, 0.107427, 0.167376, 0.266337, 0.432199, 0.708322, 1.16886", \ + "0.0357654, 0.117851, 0.173659, 0.268974, 0.433192, 0.708323, 1.16887", \ + "0.0452505, 0.133959, 0.188729, 0.280062, 0.4381, 0.709668, 1.16888", \ + "0.0613415, 0.162485, 0.220367, 0.311345, 0.463329, 0.723825, 1.1818", \ + "0.0885178, 0.209158, 0.274574, 0.373187, 0.527777, 0.779942, 1.20893", \ + "0.135512, 0.284696, 0.361805, 0.474813, 0.645524, 0.907619, 1.32947", \ + "0.217349, 0.407367, 0.502799, 0.640521, 0.838676, 1.13301, 1.58005" \ ); } cell_fall (TIMING_DELAY_7x7ds1) { index_1 ("0.0186, 0.0966, 0.174, 0.3294, 0.6408, 1.263, 2.5074"); index_2 ("0.001, 0.0234, 0.039, 0.0648, 0.108, 0.18, 0.3"); values ( \ - "0.0201983, 0.0671405, 0.0985218, 0.150208, 0.236665, 0.380849, 0.620977", \ - "0.0284443, 0.0874352, 0.12105, 0.174015, 0.260876, 0.405095, 0.645139", \ - "0.0326934, 0.102842, 0.139688, 0.195977, 0.285181, 0.430016, 0.670143", \ - "0.0370971, 0.125456, 0.168761, 0.231768, 0.328022, 0.478183, 0.720748", \ - "0.0376896, 0.15374, 0.206872, 0.282471, 0.392357, 0.557252, 0.811453", \ - "0.0376906, 0.18543, 0.256164, 0.351042, 0.484862, 0.677466, 0.960295", \ - "0.0376916, 0.211412, 0.306818, 0.434038, 0.607008, 0.843836, 1.1827" \ + "0.0201869, 0.0671537, 0.0985086, 0.150205, 0.236771, 0.380893, 0.620963", \ + "0.0284438, 0.0874338, 0.121048, 0.174012, 0.260871, 0.405158, 0.645069", \ + "0.0326929, 0.102841, 0.139685, 0.19599, 0.285164, 0.429999, 0.670211", \ + "0.0370962, 0.125454, 0.168691, 0.231765, 0.327968, 0.478173, 0.720735", \ + "0.0376883, 0.153738, 0.206869, 0.282467, 0.392351, 0.557243, 0.811579", \ + "0.0376893, 0.185427, 0.25616, 0.351037, 0.484854, 0.677519, 0.960267", \ + "0.0376903, 0.211406, 0.306812, 0.43403, 0.606999, 0.843823, 1.18268" \ ); } fall_transition (TIMING_DELAY_7x7ds1) { index_1 ("0.0186, 0.0966, 0.174, 0.3294, 0.6408, 1.263, 2.5074"); index_2 ("0.001, 0.0234, 0.039, 0.0648, 0.108, 0.18, 0.3"); values ( \ - "0.0124014, 0.0738406, 0.11748, 0.189629, 0.310325, 0.511838, 0.847561", \ - "0.022881, 0.0823067, 0.12339, 0.192871, 0.311579, 0.512101, 0.847731", \ - "0.0332727, 0.0934104, 0.134361, 0.202003, 0.317619, 0.514606, 0.849342", \ - "0.0516964, 0.116367, 0.157587, 0.22507, 0.337504, 0.528724, 0.855295", \ - "0.0820182, 0.160195, 0.202579, 0.270786, 0.384023, 0.571019, 0.887414", \ - "0.132098, 0.237895, 0.286254, 0.359015, 0.474005, 0.663943, 0.976067", \ - "0.219746, 0.368384, 0.433917, 0.521681, 0.645993, 0.845657, 1.16278" \ + "0.0123987, 0.0738874, 0.117837, 0.189538, 0.310465, 0.511939, 0.847546", \ + "0.0228807, 0.082305, 0.123387, 0.192867, 0.311497, 0.513182, 0.847749", \ + "0.0332723, 0.093409, 0.134359, 0.202003, 0.317602, 0.514585, 0.848485", \ + "0.0516959, 0.116365, 0.157151, 0.225067, 0.33745, 0.528711, 0.855279", \ + "0.0820175, 0.160194, 0.202576, 0.270783, 0.384017, 0.571009, 0.887386", \ + "0.132056, 0.237892, 0.286251, 0.358987, 0.473997, 0.663991, 0.976045", \ + "0.219745, 0.368382, 0.433913, 0.521676, 0.645986, 0.845647, 1.16276" \ ); } } @@ -5482,52 +5482,52 @@ library (sg13g2_stdcell_fast_1p65V_m40C) { index_1 ("0.0186, 0.0966, 0.174, 0.3294, 0.6408, 1.263, 2.5074"); index_2 ("0.001, 0.0234, 0.039, 0.0648, 0.108, 0.18, 0.3"); values ( \ - "0.0296085, 0.0901144, 0.131404, 0.199471, 0.313348, 0.503087, 0.819235", \ - "0.0475904, 0.119469, 0.162129, 0.230511, 0.344259, 0.533864, 0.850545", \ - "0.0586169, 0.141788, 0.18876, 0.260296, 0.37508, 0.564436, 0.880123", \ - "0.0757387, 0.175473, 0.23034, 0.311204, 0.43387, 0.626856, 0.942476", \ - "0.102676, 0.224439, 0.290476, 0.385906, 0.528112, 0.739663, 1.06641", \ - "0.144641, 0.296128, 0.377499, 0.494665, 0.665163, 0.913989, 1.28101", \ - "0.21139, 0.406064, 0.506156, 0.651372, 0.861488, 1.16417, 1.59845" \ + "0.0296076, 0.0901099, 0.131411, 0.199488, 0.313346, 0.503114, 0.819228", \ + "0.0475906, 0.119462, 0.162118, 0.230491, 0.344252, 0.533897, 0.849762", \ + "0.0586172, 0.141788, 0.188761, 0.260297, 0.375095, 0.564434, 0.880129", \ + "0.0757393, 0.175473, 0.230344, 0.311205, 0.433872, 0.626859, 0.942481", \ + "0.102677, 0.224574, 0.290477, 0.385908, 0.528114, 0.739666, 1.06635", \ + "0.1447, 0.296129, 0.377502, 0.494665, 0.665196, 0.913993, 1.28101", \ + "0.211394, 0.406068, 0.506193, 0.651376, 0.861493, 1.16417, 1.59846" \ ); } rise_transition (TIMING_DELAY_7x7ds1) { index_1 ("0.0186, 0.0966, 0.174, 0.3294, 0.6408, 1.263, 2.5074"); index_2 ("0.001, 0.0234, 0.039, 0.0648, 0.108, 0.18, 0.3"); values ( \ - "0.0269089, 0.113026, 0.173283, 0.273001, 0.439864, 0.717908, 1.18148", \ - "0.040385, 0.122767, 0.179243, 0.275369, 0.440632, 0.717909, 1.18167", \ - "0.050862, 0.138786, 0.194048, 0.286223, 0.445661, 0.718905, 1.18168", \ - "0.0677149, 0.16759, 0.225579, 0.317375, 0.470397, 0.733026, 1.19262", \ - "0.0956571, 0.214621, 0.28, 0.378902, 0.534203, 0.788671, 1.22099", \ - "0.14433, 0.290439, 0.368182, 0.481271, 0.65262, 0.915958, 1.34015", \ - "0.230358, 0.414822, 0.510183, 0.646681, 0.845106, 1.1432, 1.5938" \ + "0.0269189, 0.113026, 0.17331, 0.273023, 0.439867, 0.71789, 1.18149", \ + "0.0403853, 0.122763, 0.179181, 0.275344, 0.440462, 0.717899, 1.18155", \ + "0.050862, 0.138786, 0.194049, 0.286224, 0.445704, 0.718911, 1.18156", \ + "0.0677151, 0.167591, 0.225581, 0.317379, 0.470393, 0.733031, 1.19358", \ + "0.095657, 0.214543, 0.28, 0.378904, 0.534205, 0.788678, 1.22094", \ + "0.144216, 0.29044, 0.368182, 0.481256, 0.652648, 0.915961, 1.34016", \ + "0.230357, 0.414822, 0.510147, 0.646681, 0.845108, 1.1432, 1.59382" \ ); } cell_fall (TIMING_DELAY_7x7ds1) { index_1 ("0.0186, 0.0966, 0.174, 0.3294, 0.6408, 1.263, 2.5074"); index_2 ("0.001, 0.0234, 0.039, 0.0648, 0.108, 0.18, 0.3"); values ( \ - "0.0207074, 0.0683544, 0.100079, 0.152148, 0.238676, 0.382709, 0.622698", \ - "0.0296346, 0.0888394, 0.122745, 0.175978, 0.262939, 0.40706, 0.647088", \ - "0.0348893, 0.104537, 0.141586, 0.198041, 0.287202, 0.432107, 0.672173", \ - "0.0412488, 0.127819, 0.171022, 0.234087, 0.330145, 0.480272, 0.722822", \ - "0.0460831, 0.157269, 0.20999, 0.285182, 0.394716, 0.559324, 0.813665", \ - "0.0460841, 0.191099, 0.26043, 0.354359, 0.488012, 0.679206, 0.96228", \ - "0.0460851, 0.21937, 0.312869, 0.438555, 0.610289, 0.846307, 1.1828" \ + "0.0207071, 0.0683446, 0.100075, 0.152117, 0.238675, 0.382731, 0.622687", \ + "0.0296341, 0.0888379, 0.122738, 0.175977, 0.262935, 0.407054, 0.647077", \ + "0.0348887, 0.104536, 0.141584, 0.198038, 0.287209, 0.432107, 0.67216", \ + "0.0412478, 0.127817, 0.171192, 0.234082, 0.33014, 0.480261, 0.722834", \ + "0.0460814, 0.157266, 0.209987, 0.28518, 0.39471, 0.559316, 0.813626", \ + "0.0460824, 0.191096, 0.260425, 0.354353, 0.488004, 0.679195, 0.962265", \ + "0.0460834, 0.219368, 0.312861, 0.438543, 0.610276, 0.846293, 1.18279" \ ); } fall_transition (TIMING_DELAY_7x7ds1) { index_1 ("0.0186, 0.0966, 0.174, 0.3294, 0.6408, 1.263, 2.5074"); index_2 ("0.001, 0.0234, 0.039, 0.0648, 0.108, 0.18, 0.3"); values ( \ - "0.0175375, 0.0787049, 0.12224, 0.194338, 0.315199, 0.516666, 0.852218", \ - "0.0293186, 0.0871934, 0.128197, 0.197656, 0.316331, 0.516765, 0.852219", \ - "0.0413226, 0.0985904, 0.139274, 0.206805, 0.322356, 0.519156, 0.852762", \ - "0.0626224, 0.122279, 0.162515, 0.229729, 0.342359, 0.533463, 0.860151", \ - "0.0972583, 0.166927, 0.208689, 0.275769, 0.388694, 0.575751, 0.892032", \ - "0.153728, 0.246139, 0.292757, 0.365457, 0.479543, 0.668337, 0.980503", \ - "0.249198, 0.379846, 0.442087, 0.527657, 0.653873, 0.848979, 1.16388" \ + "0.0175366, 0.0787036, 0.122237, 0.194319, 0.315193, 0.516439, 0.852184", \ + "0.0293183, 0.0871919, 0.128191, 0.197656, 0.316352, 0.516755, 0.852298", \ + "0.0413221, 0.0985888, 0.139272, 0.206747, 0.322344, 0.519342, 0.852658", \ + "0.0626219, 0.122277, 0.162513, 0.22973, 0.342347, 0.533536, 0.859903", \ + "0.0972575, 0.166928, 0.208686, 0.27587, 0.388688, 0.575741, 0.891958", \ + "0.153727, 0.246135, 0.292754, 0.365453, 0.479537, 0.668305, 0.980626", \ + "0.249196, 0.379656, 0.442084, 0.52849, 0.653056, 0.84897, 1.16432" \ ); } } @@ -5541,52 +5541,52 @@ library (sg13g2_stdcell_fast_1p65V_m40C) { index_1 ("0.0186, 0.0966, 0.174, 0.3294, 0.6408, 1.263, 2.5074"); index_2 ("0.001, 0.0234, 0.039, 0.0648, 0.108, 0.18, 0.3"); values ( \ - "0.0254219, 0.0862533, 0.127339, 0.195039, 0.308314, 0.496868, 0.811037", \ - "0.0405444, 0.114762, 0.157587, 0.225809, 0.338972, 0.527442, 0.84155", \ - "0.0492935, 0.136125, 0.183519, 0.255217, 0.369588, 0.557986, 0.871903", \ - "0.0624545, 0.167813, 0.223535, 0.3049, 0.427727, 0.620104, 0.934233", \ - "0.0812036, 0.21206, 0.280212, 0.377131, 0.520464, 0.7319, 1.05728", \ - "0.106904, 0.273599, 0.358833, 0.479986, 0.652745, 0.902846, 1.27003", \ - "0.141268, 0.360504, 0.467342, 0.618943, 0.836144, 1.14508, 1.58061" \ + "0.0254221, 0.0862812, 0.127476, 0.195037, 0.308322, 0.49687, 0.811187", \ + "0.0405442, 0.114763, 0.157589, 0.22581, 0.338976, 0.527428, 0.841564", \ + "0.0492938, 0.136125, 0.18352, 0.255218, 0.369602, 0.557968, 0.871923", \ + "0.0624873, 0.167814, 0.223521, 0.304901, 0.427718, 0.620135, 0.934289", \ + "0.0812045, 0.212062, 0.280203, 0.377133, 0.520468, 0.731903, 1.05728", \ + "0.106906, 0.273601, 0.358835, 0.479562, 0.652733, 0.902849, 1.27003", \ + "0.141272, 0.360508, 0.467346, 0.618947, 0.836149, 1.14508, 1.58061" \ ); } rise_transition (TIMING_DELAY_7x7ds1) { index_1 ("0.0186, 0.0966, 0.174, 0.3294, 0.6408, 1.263, 2.5074"); index_2 ("0.001, 0.0234, 0.039, 0.0648, 0.108, 0.18, 0.3"); values ( \ - "0.0222671, 0.10724, 0.167206, 0.266117, 0.431949, 0.707928, 1.16808", \ - "0.0353819, 0.117416, 0.173272, 0.268604, 0.432777, 0.707929, 1.16809", \ - "0.0453787, 0.133441, 0.188315, 0.279678, 0.437809, 0.709143, 1.16868", \ - "0.0625432, 0.162677, 0.220246, 0.311202, 0.462955, 0.723472, 1.17589", \ - "0.0921618, 0.210378, 0.274837, 0.373416, 0.52767, 0.779732, 1.20857", \ - "0.142836, 0.289036, 0.365415, 0.477849, 0.647025, 0.908356, 1.32937", \ - "0.232863, 0.419412, 0.513417, 0.647923, 0.84402, 1.13791, 1.58382" \ + "0.0222672, 0.107257, 0.167249, 0.266113, 0.431949, 0.707951, 1.1687", \ + "0.0353819, 0.117416, 0.173276, 0.268606, 0.432797, 0.707952, 1.16871", \ + "0.0453789, 0.133442, 0.188316, 0.279679, 0.437785, 0.709588, 1.16872", \ + "0.0625669, 0.162677, 0.220241, 0.311203, 0.462954, 0.72348, 1.18146", \ + "0.0921617, 0.210378, 0.274927, 0.373418, 0.527675, 0.779736, 1.20859", \ + "0.142836, 0.289001, 0.365416, 0.477495, 0.646953, 0.90836, 1.32938", \ + "0.232862, 0.419412, 0.513417, 0.647923, 0.844022, 1.13791, 1.58383" \ ); } cell_fall (TIMING_DELAY_7x7ds1) { index_1 ("0.0186, 0.0966, 0.174, 0.3294, 0.6408, 1.263, 2.5074"); index_2 ("0.001, 0.0234, 0.039, 0.0648, 0.108, 0.18, 0.3"); values ( \ - "0.0194885, 0.0676334, 0.0993999, 0.151431, 0.237994, 0.382112, 0.622016", \ - "0.0312051, 0.0967865, 0.131812, 0.185485, 0.272404, 0.416357, 0.656312", \ - "0.0387685, 0.117329, 0.157538, 0.216594, 0.306996, 0.451924, 0.691614", \ - "0.0498461, 0.147176, 0.19579, 0.264935, 0.366824, 0.520549, 0.763997", \ - "0.0625162, 0.185576, 0.245963, 0.331131, 0.45288, 0.629767, 0.893194", \ - "0.0760299, 0.236043, 0.313009, 0.419749, 0.572334, 0.785845, 1.09548", \ - "0.0851167, 0.294889, 0.397972, 0.537748, 0.729421, 1.00157, 1.38043" \ + "0.0194859, 0.0676361, 0.0993774, 0.151453, 0.238037, 0.382032, 0.622002", \ + "0.0312047, 0.0967874, 0.13181, 0.185488, 0.272398, 0.416354, 0.656304", \ + "0.0387676, 0.117333, 0.157536, 0.216591, 0.306993, 0.451908, 0.691598", \ + "0.0498452, 0.147174, 0.195787, 0.264925, 0.366818, 0.520537, 0.763967", \ + "0.0625151, 0.185574, 0.24596, 0.331127, 0.452875, 0.629759, 0.893202", \ + "0.0760273, 0.236039, 0.313005, 0.419744, 0.572328, 0.785836, 1.09546", \ + "0.0851123, 0.294883, 0.397965, 0.53774, 0.729412, 1.00156, 1.38041" \ ); } fall_transition (TIMING_DELAY_7x7ds1) { index_1 ("0.0186, 0.0966, 0.174, 0.3294, 0.6408, 1.263, 2.5074"); index_2 ("0.001, 0.0234, 0.039, 0.0648, 0.108, 0.18, 0.3"); values ( \ - "0.0186649, 0.0787407, 0.122191, 0.194307, 0.315199, 0.5166, 0.8522", \ - "0.0337897, 0.0926684, 0.132416, 0.199895, 0.316948, 0.516724, 0.852201", \ - "0.0466338, 0.109387, 0.149673, 0.215174, 0.327231, 0.520909, 0.853532", \ - "0.0688017, 0.138726, 0.181961, 0.249587, 0.359697, 0.545328, 0.865376", \ - "0.106018, 0.190871, 0.238655, 0.312105, 0.427621, 0.61193, 0.919541", \ - "0.167161, 0.278063, 0.334497, 0.419349, 0.544418, 0.74481, 1.05401", \ - "0.272442, 0.42897, 0.500478, 0.600905, 0.752971, 0.969475, 1.31018" \ + "0.0186655, 0.0787406, 0.122231, 0.194322, 0.31522, 0.516437, 0.852187", \ + "0.0337894, 0.092669, 0.132415, 0.199925, 0.317082, 0.516557, 0.852188", \ + "0.0466354, 0.109384, 0.149676, 0.21517, 0.327222, 0.520909, 0.852561", \ + "0.0688014, 0.138725, 0.181958, 0.249736, 0.359689, 0.545298, 0.865357", \ + "0.105975, 0.190869, 0.238652, 0.312104, 0.427614, 0.611921, 0.91954", \ + "0.16716, 0.278063, 0.334494, 0.419339, 0.544412, 0.744802, 1.05372", \ + "0.272443, 0.428973, 0.500475, 0.600901, 0.752965, 0.969467, 1.31016" \ ); } } @@ -5600,52 +5600,52 @@ library (sg13g2_stdcell_fast_1p65V_m40C) { index_1 ("0.0186, 0.0966, 0.174, 0.3294, 0.6408, 1.263, 2.5074"); index_2 ("0.001, 0.0234, 0.039, 0.0648, 0.108, 0.18, 0.3"); values ( \ - "0.0206512, 0.0821748, 0.123477, 0.19169, 0.305447, 0.495212, 0.811337", \ - "0.0329808, 0.110305, 0.15362, 0.222251, 0.336131, 0.525836, 0.841697", \ - "0.0402005, 0.131111, 0.179244, 0.251581, 0.366783, 0.556432, 0.87208", \ - "0.0511891, 0.161653, 0.218316, 0.300773, 0.424799, 0.618426, 0.934417", \ - "0.066499, 0.204795, 0.274221, 0.372731, 0.516717, 0.730309, 1.05747", \ - "0.0873705, 0.26463, 0.351077, 0.47375, 0.648992, 0.900557, 1.27029", \ - "0.116202, 0.349501, 0.458876, 0.611915, 0.831298, 1.14281, 1.58104" \ + "0.0206508, 0.0821905, 0.123476, 0.19156, 0.305445, 0.495208, 0.811371", \ + "0.0329808, 0.110304, 0.153618, 0.222259, 0.336132, 0.525593, 0.841681", \ + "0.0402004, 0.13111, 0.179226, 0.25158, 0.36678, 0.556427, 0.872078", \ + "0.0511892, 0.161653, 0.218316, 0.300774, 0.42479, 0.618423, 0.934302", \ + "0.0664991, 0.204795, 0.27422, 0.37273, 0.516715, 0.730307, 1.05747", \ + "0.0873711, 0.26463, 0.351528, 0.473749, 0.648905, 0.900553, 1.27029", \ + "0.116204, 0.349498, 0.458875, 0.611914, 0.831295, 1.14284, 1.58104" \ ); } rise_transition (TIMING_DELAY_7x7ds1) { index_1 ("0.0186, 0.0966, 0.174, 0.3294, 0.6408, 1.263, 2.5074"); index_2 ("0.001, 0.0234, 0.039, 0.0648, 0.108, 0.18, 0.3"); values ( \ - "0.0183408, 0.103097, 0.163297, 0.262965, 0.42966, 0.707615, 1.17109", \ - "0.0309488, 0.11385, 0.169768, 0.26542, 0.430468, 0.707616, 1.1711", \ - "0.0403291, 0.12998, 0.185055, 0.276725, 0.435663, 0.708971, 1.17111", \ - "0.0566772, 0.158616, 0.216886, 0.308351, 0.461091, 0.723206, 1.18306", \ - "0.0857335, 0.206039, 0.271545, 0.370841, 0.525896, 0.779191, 1.21094", \ - "0.134795, 0.283993, 0.363892, 0.474767, 0.644685, 0.907638, 1.33181", \ - "0.223154, 0.411941, 0.509444, 0.646549, 0.842729, 1.13664, 1.58609" \ + "0.0183439, 0.103109, 0.163296, 0.262823, 0.429676, 0.707611, 1.17074", \ + "0.0309488, 0.113853, 0.169759, 0.265482, 0.430012, 0.707612, 1.17075", \ + "0.0403288, 0.129979, 0.185037, 0.276725, 0.43567, 0.708946, 1.17106", \ + "0.0566771, 0.158615, 0.216885, 0.308348, 0.461082, 0.723202, 1.18281", \ + "0.0857332, 0.206039, 0.271544, 0.370839, 0.525893, 0.779187, 1.21091", \ + "0.134794, 0.283992, 0.36344, 0.474765, 0.644456, 0.907636, 1.3318", \ + "0.223155, 0.411926, 0.509442, 0.646546, 0.842724, 1.13665, 1.58608" \ ); } cell_fall (TIMING_DELAY_7x7ds1) { index_1 ("0.0186, 0.0966, 0.174, 0.3294, 0.6408, 1.263, 2.5074"); index_2 ("0.001, 0.0234, 0.039, 0.0648, 0.108, 0.18, 0.3"); values ( \ - "0.0189024, 0.0664718, 0.0978521, 0.149545, 0.236, 0.380195, 0.620082", \ - "0.029528, 0.0952283, 0.130089, 0.183525, 0.270362, 0.414525, 0.654387", \ - "0.035861, 0.115234, 0.155462, 0.214436, 0.304933, 0.449855, 0.689836", \ - "0.0441122, 0.144062, 0.192939, 0.262391, 0.364494, 0.518412, 0.761977", \ - "0.0511511, 0.18094, 0.24188, 0.32785, 0.450142, 0.627376, 0.891053", \ - "0.0566122, 0.22821, 0.307393, 0.415158, 0.568901, 0.783283, 1.09312", \ - "0.0566132, 0.28368, 0.389777, 0.531201, 0.724462, 0.997815, 1.37797" \ + "0.018902, 0.0664686, 0.0978509, 0.149543, 0.235987, 0.380186, 0.620062", \ + "0.0295277, 0.0952171, 0.130066, 0.183521, 0.270347, 0.414381, 0.654373", \ + "0.0358606, 0.115233, 0.155459, 0.214448, 0.30493, 0.449848, 0.689723", \ + "0.0441116, 0.144061, 0.192937, 0.262376, 0.364489, 0.518404, 0.761916", \ + "0.0511501, 0.180817, 0.241878, 0.327846, 0.450173, 0.627369, 0.891016", \ + "0.0566459, 0.228315, 0.307388, 0.415153, 0.568897, 0.783274, 1.09316", \ + "0.0566469, 0.283676, 0.389772, 0.531872, 0.724454, 0.997804, 1.37795" \ ); } fall_transition (TIMING_DELAY_7x7ds1) { index_1 ("0.0186, 0.0966, 0.174, 0.3294, 0.6408, 1.263, 2.5074"); index_2 ("0.001, 0.0234, 0.039, 0.0648, 0.108, 0.18, 0.3"); values ( \ - "0.0133757, 0.0739431, 0.117842, 0.189677, 0.310555, 0.511909, 0.847521", \ - "0.0261141, 0.0876956, 0.127573, 0.195172, 0.3124, 0.512453, 0.847906", \ - "0.0368263, 0.103846, 0.144582, 0.210456, 0.322542, 0.516237, 0.848445", \ - "0.0555218, 0.132331, 0.176145, 0.244883, 0.354809, 0.540697, 0.860855", \ - "0.087388, 0.182225, 0.232587, 0.306081, 0.422333, 0.60718, 0.914884", \ - "0.141362, 0.26928, 0.326334, 0.413232, 0.539122, 0.739543, 1.0491", \ - "0.238065, 0.415242, 0.491149, 0.591388, 0.745264, 0.964871, 1.30501" \ + "0.0133912, 0.0739303, 0.11784, 0.189673, 0.310548, 0.511898, 0.847493", \ + "0.0261138, 0.0876099, 0.127548, 0.195092, 0.312218, 0.512074, 0.847671", \ + "0.0368263, 0.103845, 0.144583, 0.210343, 0.322471, 0.516227, 0.84841", \ + "0.0555215, 0.132329, 0.176143, 0.244861, 0.3548, 0.540684, 0.860874", \ + "0.0873876, 0.18253, 0.232585, 0.306078, 0.422966, 0.607168, 0.914473", \ + "0.141537, 0.269419, 0.326332, 0.413228, 0.539118, 0.738742, 1.04935", \ + "0.238064, 0.41524, 0.491147, 0.591607, 0.745258, 0.964861, 1.30499" \ ); } } @@ -5657,52 +5657,52 @@ library (sg13g2_stdcell_fast_1p65V_m40C) { index_1 ("0.0186, 0.0966, 0.174, 0.3294, 0.6408, 1.263, 2.5074"); index_2 ("0.001, 0.0234, 0.039, 0.0648, 0.108, 0.18, 0.3"); values ( \ - "0.0206512, 0.0821748, 0.123477, 0.19169, 0.305447, 0.495212, 0.811337", \ - "0.0329808, 0.110305, 0.15362, 0.222251, 0.336131, 0.525836, 0.841697", \ - "0.0402005, 0.131111, 0.179244, 0.251581, 0.366783, 0.556432, 0.87208", \ - "0.0511891, 0.161653, 0.218316, 0.300773, 0.424799, 0.618426, 0.934417", \ - "0.066499, 0.204795, 0.274221, 0.372731, 0.516717, 0.730309, 1.05747", \ - "0.0873705, 0.26463, 0.351077, 0.47375, 0.648992, 0.900557, 1.27029", \ - "0.116202, 0.349501, 0.458876, 0.611915, 0.831298, 1.14281, 1.58104" \ + "0.0206508, 0.0821905, 0.123476, 0.19156, 0.305445, 0.495208, 0.811371", \ + "0.0329808, 0.110304, 0.153618, 0.222259, 0.336132, 0.525593, 0.841681", \ + "0.0402004, 0.13111, 0.179226, 0.25158, 0.36678, 0.556427, 0.872078", \ + "0.0511892, 0.161653, 0.218316, 0.300774, 0.42479, 0.618423, 0.934302", \ + "0.0664991, 0.204795, 0.27422, 0.37273, 0.516715, 0.730307, 1.05747", \ + "0.0873711, 0.26463, 0.351528, 0.473749, 0.648905, 0.900553, 1.27029", \ + "0.116204, 0.349498, 0.458875, 0.611914, 0.831295, 1.14284, 1.58104" \ ); } rise_transition (TIMING_DELAY_7x7ds1) { index_1 ("0.0186, 0.0966, 0.174, 0.3294, 0.6408, 1.263, 2.5074"); index_2 ("0.001, 0.0234, 0.039, 0.0648, 0.108, 0.18, 0.3"); values ( \ - "0.0183408, 0.103097, 0.163297, 0.262965, 0.42966, 0.707615, 1.17109", \ - "0.0309488, 0.11385, 0.169768, 0.26542, 0.430468, 0.707616, 1.1711", \ - "0.0403291, 0.12998, 0.185055, 0.276725, 0.435663, 0.708971, 1.17111", \ - "0.0566772, 0.158616, 0.216886, 0.308351, 0.461091, 0.723206, 1.18306", \ - "0.0857335, 0.206039, 0.271545, 0.370841, 0.525896, 0.779191, 1.21094", \ - "0.134795, 0.283993, 0.363892, 0.474767, 0.644685, 0.907638, 1.33181", \ - "0.223154, 0.411941, 0.509444, 0.646549, 0.842729, 1.13664, 1.58609" \ + "0.0183439, 0.103109, 0.163296, 0.262823, 0.429676, 0.707611, 1.17074", \ + "0.0309488, 0.113853, 0.169759, 0.265482, 0.430012, 0.707612, 1.17075", \ + "0.0403288, 0.129979, 0.185037, 0.276725, 0.43567, 0.708946, 1.17106", \ + "0.0566771, 0.158615, 0.216885, 0.308348, 0.461082, 0.723202, 1.18281", \ + "0.0857332, 0.206039, 0.271544, 0.370839, 0.525893, 0.779187, 1.21091", \ + "0.134794, 0.283992, 0.36344, 0.474765, 0.644456, 0.907636, 1.3318", \ + "0.223155, 0.411926, 0.509442, 0.646546, 0.842724, 1.13665, 1.58608" \ ); } cell_fall (TIMING_DELAY_7x7ds1) { index_1 ("0.0186, 0.0966, 0.174, 0.3294, 0.6408, 1.263, 2.5074"); index_2 ("0.001, 0.0234, 0.039, 0.0648, 0.108, 0.18, 0.3"); values ( \ - "0.0194885, 0.0676334, 0.0993999, 0.151431, 0.237994, 0.382112, 0.622016", \ - "0.0312051, 0.0967865, 0.131812, 0.185485, 0.272404, 0.416357, 0.656312", \ - "0.0387685, 0.117329, 0.157538, 0.216594, 0.306996, 0.451924, 0.691614", \ - "0.0498461, 0.147176, 0.19579, 0.264935, 0.366824, 0.520549, 0.763997", \ - "0.0625162, 0.185576, 0.245963, 0.331131, 0.45288, 0.629767, 0.893194", \ - "0.0760299, 0.236043, 0.313009, 0.419749, 0.572334, 0.785845, 1.09548", \ - "0.0851167, 0.294889, 0.397972, 0.537748, 0.729421, 1.00157, 1.38043" \ + "0.0194859, 0.0676361, 0.0993774, 0.151453, 0.238037, 0.382032, 0.622002", \ + "0.0312047, 0.0967874, 0.13181, 0.185488, 0.272398, 0.416354, 0.656304", \ + "0.0387676, 0.117333, 0.157536, 0.216591, 0.306993, 0.451908, 0.691598", \ + "0.0498452, 0.147174, 0.195787, 0.264925, 0.366818, 0.520537, 0.763967", \ + "0.0625151, 0.185574, 0.24596, 0.331127, 0.452875, 0.629759, 0.893202", \ + "0.0760273, 0.236039, 0.313005, 0.419744, 0.572328, 0.785836, 1.09546", \ + "0.0851123, 0.294883, 0.397965, 0.53774, 0.729412, 1.00156, 1.38041" \ ); } fall_transition (TIMING_DELAY_7x7ds1) { index_1 ("0.0186, 0.0966, 0.174, 0.3294, 0.6408, 1.263, 2.5074"); index_2 ("0.001, 0.0234, 0.039, 0.0648, 0.108, 0.18, 0.3"); values ( \ - "0.0186649, 0.0787407, 0.122191, 0.194307, 0.315199, 0.5166, 0.8522", \ - "0.0337897, 0.0926684, 0.132416, 0.199895, 0.316948, 0.516724, 0.852201", \ - "0.0466338, 0.109387, 0.149673, 0.215174, 0.327231, 0.520909, 0.853532", \ - "0.0688017, 0.138726, 0.181961, 0.249587, 0.359697, 0.545328, 0.865376", \ - "0.106018, 0.190871, 0.238655, 0.312105, 0.427621, 0.61193, 0.919541", \ - "0.167161, 0.278063, 0.334497, 0.419349, 0.544418, 0.74481, 1.05401", \ - "0.272442, 0.42897, 0.500478, 0.600905, 0.752971, 0.969475, 1.31018" \ + "0.0186655, 0.0787406, 0.122231, 0.194322, 0.31522, 0.516437, 0.852187", \ + "0.0337894, 0.092669, 0.132415, 0.199925, 0.317082, 0.516557, 0.852188", \ + "0.0466354, 0.109384, 0.149676, 0.21517, 0.327222, 0.520909, 0.852561", \ + "0.0688014, 0.138725, 0.181958, 0.249736, 0.359689, 0.545298, 0.865357", \ + "0.105975, 0.190869, 0.238652, 0.312104, 0.427614, 0.611921, 0.91954", \ + "0.16716, 0.278063, 0.334494, 0.419339, 0.544412, 0.744802, 1.05372", \ + "0.272443, 0.428973, 0.500475, 0.600901, 0.752965, 0.969467, 1.31016" \ ); } } @@ -5713,26 +5713,26 @@ library (sg13g2_stdcell_fast_1p65V_m40C) { index_1 ("0.0186, 0.0966, 0.174, 0.3294, 0.6408, 1.263, 2.5074"); index_2 ("0.001, 0.0234, 0.039, 0.0648, 0.108, 0.18, 0.3"); values ( \ - "0.00889681, 0.00969387, 0.00970996, 0.00963663, 0.00944008, 0.00910199, 0.00845242", \ - "0.00930781, 0.00935477, 0.00962891, 0.00943959, 0.00955232, 0.00900302, 0.00843349", \ - "0.01126, 0.0101553, 0.00998414, 0.00983335, 0.00981513, 0.00912773, 0.00853684", \ - "0.016632, 0.0132902, 0.012501, 0.0116588, 0.0112359, 0.0100745, 0.00925331", \ - "0.028723, 0.0223588, 0.0204269, 0.0182651, 0.0160103, 0.0142865, 0.0120381", \ - "0.0537777, 0.0442706, 0.0403307, 0.0360123, 0.0313389, 0.0263328, 0.0214243", \ - "0.104509, 0.0918033, 0.0857133, 0.0779894, 0.0690784, 0.0595661, 0.0491506" \ + "0.00889698, 0.00968581, 0.00971029, 0.0096388, 0.00944038, 0.00909333, 0.00845989", \ + "0.00930813, 0.00935782, 0.00956572, 0.00957104, 0.00930485, 0.00903045, 0.00849019", \ + "0.0112601, 0.0101539, 0.00999, 0.00982668, 0.00981521, 0.00909545, 0.008537", \ + "0.0166324, 0.0132911, 0.0124981, 0.011717, 0.0113311, 0.0100773, 0.00942353", \ + "0.028733, 0.0223605, 0.0204269, 0.0182635, 0.01601, 0.0142903, 0.0120995", \ + "0.0537774, 0.044271, 0.0402495, 0.0360123, 0.031333, 0.0264338, 0.0214481", \ + "0.104509, 0.0918036, 0.0857122, 0.078015, 0.0690794, 0.0595657, 0.0490874" \ ); } fall_power (POWER_7x7ds1) { index_1 ("0.0186, 0.0966, 0.174, 0.3294, 0.6408, 1.263, 2.5074"); index_2 ("0.001, 0.0234, 0.039, 0.0648, 0.108, 0.18, 0.3"); values ( \ - "0.00844763, 0.00872549, 0.00859144, 0.00847404, 0.00829485, 0.00790826, 0.00722525", \ - "0.00955586, 0.00888124, 0.00882697, 0.00854641, 0.00890495, 0.00789122, 0.00724698", \ - "0.0118658, 0.0101438, 0.00960594, 0.00921314, 0.00923191, 0.00837069, 0.00742713", \ - "0.0175241, 0.0135581, 0.0125961, 0.0115199, 0.0103593, 0.00982669, 0.00854287", \ - "0.0298135, 0.0229815, 0.0207445, 0.0181961, 0.0159047, 0.0134094, 0.0117789", \ - "0.054964, 0.0451381, 0.0408418, 0.0360606, 0.030604, 0.0254082, 0.020412", \ - "0.106396, 0.093437, 0.0868433, 0.0785179, 0.0682224, 0.0574389, 0.0463722" \ + "0.00845624, 0.00872722, 0.00862658, 0.00847511, 0.00829624, 0.00795864, 0.00724304", \ + "0.00955607, 0.00888166, 0.00882263, 0.00853163, 0.00851304, 0.00791899, 0.00716137", \ + "0.0118658, 0.0101391, 0.00961091, 0.00919177, 0.00918374, 0.00825935, 0.00736185", \ + "0.017518, 0.0135589, 0.012566, 0.0115277, 0.0103681, 0.00998802, 0.00824079", \ + "0.0298146, 0.022972, 0.0207419, 0.0181965, 0.0159055, 0.0133016, 0.0117778", \ + "0.0549641, 0.0451382, 0.0408425, 0.0360607, 0.0306046, 0.0253953, 0.0203746", \ + "0.106396, 0.0934372, 0.0868519, 0.078539, 0.068229, 0.0574414, 0.0463033" \ ); } } @@ -5742,26 +5742,26 @@ library (sg13g2_stdcell_fast_1p65V_m40C) { index_1 ("0.0186, 0.0966, 0.174, 0.3294, 0.6408, 1.263, 2.5074"); index_2 ("0.001, 0.0234, 0.039, 0.0648, 0.108, 0.18, 0.3"); values ( \ - "0.00889681, 0.00969387, 0.00970996, 0.00963663, 0.00944008, 0.00910199, 0.00845242", \ - "0.00930781, 0.00935477, 0.00962891, 0.00943959, 0.00955232, 0.00900302, 0.00843349", \ - "0.01126, 0.0101553, 0.00998414, 0.00983335, 0.00981513, 0.00912773, 0.00853684", \ - "0.016632, 0.0132902, 0.012501, 0.0116588, 0.0112359, 0.0100745, 0.00925331", \ - "0.028723, 0.0223588, 0.0204269, 0.0182651, 0.0160103, 0.0142865, 0.0120381", \ - "0.0537777, 0.0442706, 0.0403307, 0.0360123, 0.0313389, 0.0263328, 0.0214243", \ - "0.104509, 0.0918033, 0.0857133, 0.0779894, 0.0690784, 0.0595661, 0.0491506" \ + "0.00889698, 0.00968581, 0.00971029, 0.0096388, 0.00944038, 0.00909333, 0.00845989", \ + "0.00930813, 0.00935782, 0.00956572, 0.00957104, 0.00930485, 0.00903045, 0.00849019", \ + "0.0112601, 0.0101539, 0.00999, 0.00982668, 0.00981521, 0.00909545, 0.008537", \ + "0.0166324, 0.0132911, 0.0124981, 0.011717, 0.0113311, 0.0100773, 0.00942353", \ + "0.028733, 0.0223605, 0.0204269, 0.0182635, 0.01601, 0.0142903, 0.0120995", \ + "0.0537774, 0.044271, 0.0402495, 0.0360123, 0.031333, 0.0264338, 0.0214481", \ + "0.104509, 0.0918036, 0.0857122, 0.078015, 0.0690794, 0.0595657, 0.0490874" \ ); } fall_power (POWER_7x7ds1) { index_1 ("0.0186, 0.0966, 0.174, 0.3294, 0.6408, 1.263, 2.5074"); index_2 ("0.001, 0.0234, 0.039, 0.0648, 0.108, 0.18, 0.3"); values ( \ - "0.00844763, 0.00872549, 0.00859144, 0.00847404, 0.00829485, 0.00790826, 0.00722525", \ - "0.00955586, 0.00888124, 0.00882697, 0.00854641, 0.00890495, 0.00789122, 0.00724698", \ - "0.0118658, 0.0101438, 0.00960594, 0.00921314, 0.00923191, 0.00837069, 0.00742713", \ - "0.0175241, 0.0135581, 0.0125961, 0.0115199, 0.0103593, 0.00982669, 0.00854287", \ - "0.0298135, 0.0229815, 0.0207445, 0.0181961, 0.0159047, 0.0134094, 0.0117789", \ - "0.054964, 0.0451381, 0.0408418, 0.0360606, 0.030604, 0.0254082, 0.020412", \ - "0.106396, 0.093437, 0.0868433, 0.0785179, 0.0682224, 0.0574389, 0.0463722" \ + "0.00845624, 0.00872722, 0.00862658, 0.00847511, 0.00829624, 0.00795864, 0.00724304", \ + "0.00955607, 0.00888166, 0.00882263, 0.00853163, 0.00851304, 0.00791899, 0.00716137", \ + "0.0118658, 0.0101391, 0.00961091, 0.00919177, 0.00918374, 0.00825935, 0.00736185", \ + "0.017518, 0.0135589, 0.012566, 0.0115277, 0.0103681, 0.00998802, 0.00824079", \ + "0.0298146, 0.022972, 0.0207419, 0.0181965, 0.0159055, 0.0133016, 0.0117778", \ + "0.0549641, 0.0451382, 0.0408425, 0.0360607, 0.0306046, 0.0253953, 0.0203746", \ + "0.106396, 0.0934372, 0.0868519, 0.078539, 0.068229, 0.0574414, 0.0463033" \ ); } } @@ -5772,26 +5772,26 @@ library (sg13g2_stdcell_fast_1p65V_m40C) { index_1 ("0.0186, 0.0966, 0.174, 0.3294, 0.6408, 1.263, 2.5074"); index_2 ("0.001, 0.0234, 0.039, 0.0648, 0.108, 0.18, 0.3"); values ( \ - "0.00924281, 0.00948072, 0.00935366, 0.00924209, 0.0090439, 0.00860237, 0.00802868", \ - "0.00963993, 0.00943004, 0.00937561, 0.00929689, 0.00924707, 0.00861481, 0.00803758", \ - "0.0115325, 0.0103143, 0.0100391, 0.00998463, 0.00941069, 0.00903589, 0.00822714", \ - "0.0170233, 0.0136814, 0.0128001, 0.0117927, 0.0110767, 0.009893, 0.00925306", \ - "0.0295127, 0.0234642, 0.0212079, 0.0189701, 0.0163407, 0.014606, 0.0120549", \ - "0.0553381, 0.0466032, 0.0426623, 0.0377359, 0.0328542, 0.0271849, 0.0221292", \ - "0.107632, 0.0961984, 0.0902552, 0.0827515, 0.0734194, 0.062267, 0.0515751" \ + "0.00924129, 0.0094122, 0.00936792, 0.00926036, 0.00904548, 0.00865817, 0.00802881", \ + "0.00964656, 0.00944004, 0.00939586, 0.00921032, 0.00905347, 0.00864852, 0.00809937", \ + "0.0115324, 0.0103265, 0.0100304, 0.00998325, 0.00964839, 0.00881672, 0.00822692", \ + "0.0170242, 0.0136827, 0.0128116, 0.0118381, 0.0110804, 0.00994377, 0.00908209", \ + "0.0295112, 0.0234648, 0.0212114, 0.0189544, 0.0163162, 0.0145922, 0.011999", \ + "0.0553379, 0.0466052, 0.0426601, 0.0377309, 0.0328538, 0.0272686, 0.022112", \ + "0.107644, 0.0961969, 0.0902543, 0.0827701, 0.073419, 0.0623629, 0.0513358" \ ); } fall_power (POWER_7x7ds1) { index_1 ("0.0186, 0.0966, 0.174, 0.3294, 0.6408, 1.263, 2.5074"); index_2 ("0.001, 0.0234, 0.039, 0.0648, 0.108, 0.18, 0.3"); values ( \ - "0.0118068, 0.0120793, 0.0118646, 0.0117258, 0.0115238, 0.0111398, 0.0105154", \ - "0.0123124, 0.0120103, 0.0119719, 0.0117502, 0.011547, 0.0111412, 0.0104028", \ - "0.0143709, 0.0130617, 0.0126419, 0.0123063, 0.0124457, 0.0119105, 0.0108502", \ - "0.0198855, 0.0164131, 0.0155048, 0.0146133, 0.0133606, 0.0131609, 0.0116444", \ - "0.0323285, 0.025834, 0.0235171, 0.0213056, 0.0189509, 0.0165064, 0.0149674", \ - "0.0583285, 0.0484216, 0.0442212, 0.0390597, 0.0340968, 0.0288131, 0.0239525", \ - "0.111173, 0.0982214, 0.0916313, 0.0832063, 0.0729219, 0.0620566, 0.0504715" \ + "0.0118031, 0.0120111, 0.0118627, 0.0117324, 0.0115482, 0.0111179, 0.0104477", \ + "0.012312, 0.0120101, 0.0119722, 0.0117525, 0.0115488, 0.0112044, 0.0104522", \ + "0.0143686, 0.0130526, 0.0126573, 0.0123028, 0.012374, 0.0119063, 0.0108473", \ + "0.0198831, 0.0164138, 0.0155023, 0.0146006, 0.0134806, 0.0131609, 0.0116566", \ + "0.0323392, 0.0258328, 0.0235137, 0.0213019, 0.0189682, 0.0165947, 0.0150811", \ + "0.0583496, 0.0484215, 0.0442204, 0.0390601, 0.0340922, 0.0288108, 0.0239671", \ + "0.111172, 0.0982179, 0.0916307, 0.0832059, 0.0728823, 0.0620365, 0.0504672" \ ); } } @@ -5801,26 +5801,26 @@ library (sg13g2_stdcell_fast_1p65V_m40C) { index_1 ("0.0186, 0.0966, 0.174, 0.3294, 0.6408, 1.263, 2.5074"); index_2 ("0.001, 0.0234, 0.039, 0.0648, 0.108, 0.18, 0.3"); values ( \ - "0.00924281, 0.00948072, 0.00935366, 0.00924209, 0.0090439, 0.00860237, 0.00802868", \ - "0.00963993, 0.00943004, 0.00937561, 0.00929689, 0.00924707, 0.00861481, 0.00803758", \ - "0.0115325, 0.0103143, 0.0100391, 0.00998463, 0.00941069, 0.00903589, 0.00822714", \ - "0.0170233, 0.0136814, 0.0128001, 0.0117927, 0.0110767, 0.009893, 0.00925306", \ - "0.0295127, 0.0234642, 0.0212079, 0.0189701, 0.0163407, 0.014606, 0.0120549", \ - "0.0553381, 0.0466032, 0.0426623, 0.0377359, 0.0328542, 0.0271849, 0.0221292", \ - "0.107632, 0.0961984, 0.0902552, 0.0827515, 0.0734194, 0.062267, 0.0515751" \ + "0.00924129, 0.0094122, 0.00936792, 0.00926036, 0.00904548, 0.00865817, 0.00802881", \ + "0.00964656, 0.00944004, 0.00939586, 0.00921032, 0.00905347, 0.00864852, 0.00809937", \ + "0.0115324, 0.0103265, 0.0100304, 0.00998325, 0.00964839, 0.00881672, 0.00822692", \ + "0.0170242, 0.0136827, 0.0128116, 0.0118381, 0.0110804, 0.00994377, 0.00908209", \ + "0.0295112, 0.0234648, 0.0212114, 0.0189544, 0.0163162, 0.0145922, 0.011999", \ + "0.0553379, 0.0466052, 0.0426601, 0.0377309, 0.0328538, 0.0272686, 0.022112", \ + "0.107644, 0.0961969, 0.0902543, 0.0827701, 0.073419, 0.0623629, 0.0513358" \ ); } fall_power (POWER_7x7ds1) { index_1 ("0.0186, 0.0966, 0.174, 0.3294, 0.6408, 1.263, 2.5074"); index_2 ("0.001, 0.0234, 0.039, 0.0648, 0.108, 0.18, 0.3"); values ( \ - "0.0118068, 0.0120793, 0.0118646, 0.0117258, 0.0115238, 0.0111398, 0.0105154", \ - "0.0123124, 0.0120103, 0.0119719, 0.0117502, 0.011547, 0.0111412, 0.0104028", \ - "0.0143709, 0.0130617, 0.0126419, 0.0123063, 0.0124457, 0.0119105, 0.0108502", \ - "0.0198855, 0.0164131, 0.0155048, 0.0146133, 0.0133606, 0.0131609, 0.0116444", \ - "0.0323285, 0.025834, 0.0235171, 0.0213056, 0.0189509, 0.0165064, 0.0149674", \ - "0.0583285, 0.0484216, 0.0442212, 0.0390597, 0.0340968, 0.0288131, 0.0239525", \ - "0.111173, 0.0982214, 0.0916313, 0.0832063, 0.0729219, 0.0620566, 0.0504715" \ + "0.0118031, 0.0120111, 0.0118627, 0.0117324, 0.0115482, 0.0111179, 0.0104477", \ + "0.012312, 0.0120101, 0.0119722, 0.0117525, 0.0115488, 0.0112044, 0.0104522", \ + "0.0143686, 0.0130526, 0.0126573, 0.0123028, 0.012374, 0.0119063, 0.0108473", \ + "0.0198831, 0.0164138, 0.0155023, 0.0146006, 0.0134806, 0.0131609, 0.0116566", \ + "0.0323392, 0.0258328, 0.0235137, 0.0213019, 0.0189682, 0.0165947, 0.0150811", \ + "0.0583496, 0.0484215, 0.0442204, 0.0390601, 0.0340922, 0.0288108, 0.0239671", \ + "0.111172, 0.0982179, 0.0916307, 0.0832059, 0.0728823, 0.0620365, 0.0504672" \ ); } } @@ -5831,26 +5831,26 @@ library (sg13g2_stdcell_fast_1p65V_m40C) { index_1 ("0.0186, 0.0966, 0.174, 0.3294, 0.6408, 1.263, 2.5074"); index_2 ("0.001, 0.0234, 0.039, 0.0648, 0.108, 0.18, 0.3"); values ( \ - "0.00537154, 0.00560601, 0.00556361, 0.00547508, 0.00527908, 0.00489397, 0.00430201", \ - "0.00688648, 0.00606675, 0.00589013, 0.00571709, 0.00541248, 0.00495228, 0.00434136", \ - "0.00941978, 0.00751706, 0.006998, 0.00648408, 0.00591289, 0.00524393, 0.00450313", \ - "0.0149978, 0.0114743, 0.010326, 0.00910455, 0.00833135, 0.00683411, 0.00637461", \ - "0.0271236, 0.0213991, 0.0191511, 0.0166058, 0.0138324, 0.0117272, 0.00904718", \ - "0.0513477, 0.0432865, 0.0395307, 0.0349109, 0.0298861, 0.0242017, 0.0189294", \ - "0.101325, 0.0907824, 0.0851256, 0.0779384, 0.0688008, 0.0585353, 0.0478695" \ + "0.00537227, 0.00560551, 0.00557508, 0.00547312, 0.00527659, 0.0048855, 0.00430012", \ + "0.00688701, 0.00606513, 0.00587529, 0.00578375, 0.00539082, 0.00495963, 0.00430965", \ + "0.00941924, 0.00751736, 0.00699824, 0.00648488, 0.00586489, 0.0052424, 0.00450386", \ + "0.0149965, 0.0114745, 0.0103342, 0.00903226, 0.00794352, 0.00683435, 0.00662317", \ + "0.027127, 0.021409, 0.0191481, 0.0166138, 0.0138412, 0.0117288, 0.00921367", \ + "0.0513533, 0.0432732, 0.0395306, 0.0349245, 0.0298714, 0.0241775, 0.0189518", \ + "0.101324, 0.0907825, 0.0851317, 0.0779383, 0.0688012, 0.0585375, 0.0478616" \ ); } fall_power (POWER_7x7ds1) { index_1 ("0.0186, 0.0966, 0.174, 0.3294, 0.6408, 1.263, 2.5074"); index_2 ("0.001, 0.0234, 0.039, 0.0648, 0.108, 0.18, 0.3"); values ( \ - "0.0116285, 0.0126334, 0.0125114, 0.0124371, 0.0122796, 0.0119548, 0.011215", \ - "0.0123909, 0.0124647, 0.0125463, 0.0124274, 0.0127891, 0.0120183, 0.0112931", \ - "0.0146013, 0.0133404, 0.013149, 0.0129261, 0.0131789, 0.0126449, 0.0114816", \ - "0.0200984, 0.0164264, 0.015591, 0.0148871, 0.0140344, 0.0135261, 0.0128085", \ - "0.0321603, 0.0251706, 0.0229535, 0.0207966, 0.0188567, 0.0170033, 0.0155081", \ - "0.0570992, 0.0464827, 0.0421848, 0.0372907, 0.0324004, 0.0279621, 0.0238268", \ - "0.107684, 0.0935012, 0.0866887, 0.0780993, 0.0682424, 0.0577156, 0.0478994" \ + "0.0116311, 0.0126316, 0.0125104, 0.0124482, 0.0122806, 0.0119239, 0.011214", \ + "0.0123887, 0.0124212, 0.012545, 0.0124503, 0.0123832, 0.012004, 0.0113796", \ + "0.0146018, 0.0133391, 0.0131083, 0.0128984, 0.013015, 0.0122945, 0.011553", \ + "0.0200989, 0.0164256, 0.0156459, 0.0148812, 0.0140282, 0.0138187, 0.0122139", \ + "0.0321606, 0.0251668, 0.0229538, 0.0208043, 0.0188765, 0.016849, 0.0156069", \ + "0.0570981, 0.0464823, 0.0421855, 0.0372919, 0.0323652, 0.0279459, 0.0236534", \ + "0.107685, 0.0936588, 0.0866886, 0.0781833, 0.0681946, 0.0577088, 0.0479351" \ ); } } @@ -5861,26 +5861,26 @@ library (sg13g2_stdcell_fast_1p65V_m40C) { index_1 ("0.0186, 0.0966, 0.174, 0.3294, 0.6408, 1.263, 2.5074"); index_2 ("0.001, 0.0234, 0.039, 0.0648, 0.108, 0.18, 0.3"); values ( \ - "0.00503328, 0.00535299, 0.00531508, 0.00523186, 0.0050245, 0.00462955, 0.00400991", \ - "0.00682336, 0.00584662, 0.00571776, 0.00542775, 0.00521667, 0.00468744, 0.00399643", \ - "0.00952921, 0.00734348, 0.00680537, 0.00638293, 0.00582804, 0.00500168, 0.00427004", \ - "0.0153161, 0.0114174, 0.0101328, 0.00889462, 0.00774435, 0.00656547, 0.00637941", \ - "0.0276195, 0.0215332, 0.0191786, 0.0165881, 0.0137239, 0.0115212, 0.00842043", \ - "0.0521607, 0.0436672, 0.0397507, 0.0350641, 0.0299248, 0.0241772, 0.018852", \ - "0.102433, 0.0914388, 0.0857152, 0.0783034, 0.0692284, 0.0589107, 0.0477389" \ + "0.00503452, 0.00533321, 0.00531559, 0.00522445, 0.00504522, 0.00462915, 0.00400982", \ + "0.00682272, 0.00583894, 0.00571831, 0.00549698, 0.00522398, 0.00465886, 0.0039391", \ + "0.00952991, 0.00730646, 0.00678926, 0.00638563, 0.00565834, 0.00504047, 0.00427342", \ + "0.0153154, 0.011418, 0.0101304, 0.00888574, 0.00787022, 0.0065084, 0.00638573", \ + "0.0276194, 0.0215334, 0.0191843, 0.0166302, 0.0138331, 0.0115211, 0.0083649", \ + "0.0521603, 0.043669, 0.0397517, 0.0350603, 0.0299207, 0.0242446, 0.0188447", \ + "0.102434, 0.0914398, 0.0857161, 0.0783047, 0.0692005, 0.0589549, 0.0476433" \ ); } fall_power (POWER_7x7ds1) { index_1 ("0.0186, 0.0966, 0.174, 0.3294, 0.6408, 1.263, 2.5074"); index_2 ("0.001, 0.0234, 0.039, 0.0648, 0.108, 0.18, 0.3"); values ( \ - "0.00819921, 0.00911197, 0.00908814, 0.00902343, 0.00884319, 0.00849606, 0.00784801", \ - "0.00900301, 0.00900968, 0.00909595, 0.0090517, 0.00917292, 0.00855307, 0.00800272", \ - "0.0112365, 0.00991484, 0.0097009, 0.00948698, 0.00971843, 0.00912436, 0.00833671", \ - "0.0168554, 0.0130318, 0.0122561, 0.0115433, 0.0106354, 0.0103581, 0.00920348", \ - "0.0290707, 0.021903, 0.0195941, 0.0174674, 0.0156037, 0.0133332, 0.0122237", \ - "0.05415, 0.0433977, 0.0390704, 0.0340107, 0.0290434, 0.0247813, 0.0202665", \ - "0.105043, 0.090591, 0.0838275, 0.0753233, 0.0650183, 0.0550223, 0.0454093" \ + "0.00820228, 0.00912392, 0.00918275, 0.00901822, 0.00884552, 0.00853893, 0.00780573", \ + "0.00900328, 0.00900346, 0.00910339, 0.00905019, 0.00920247, 0.00887518, 0.00794285", \ + "0.0112357, 0.00991531, 0.00970769, 0.00946313, 0.00939745, 0.00885152, 0.00817361", \ + "0.0168555, 0.0130331, 0.0121783, 0.011544, 0.0106212, 0.010359, 0.00920247", \ + "0.0290762, 0.0219039, 0.0195962, 0.0174672, 0.0155764, 0.0133361, 0.0122334", \ + "0.0541509, 0.0433984, 0.0390699, 0.0340096, 0.0290553, 0.0247398, 0.020585", \ + "0.105045, 0.0906029, 0.0838292, 0.0753225, 0.065024, 0.0550229, 0.0454132" \ ); } } @@ -5890,26 +5890,26 @@ library (sg13g2_stdcell_fast_1p65V_m40C) { index_1 ("0.0186, 0.0966, 0.174, 0.3294, 0.6408, 1.263, 2.5074"); index_2 ("0.001, 0.0234, 0.039, 0.0648, 0.108, 0.18, 0.3"); values ( \ - "0.00537154, 0.00560601, 0.00556361, 0.00547508, 0.00527908, 0.00489397, 0.00430201", \ - "0.00688648, 0.00606675, 0.00589013, 0.00571709, 0.00541248, 0.00495228, 0.00434136", \ - "0.00941978, 0.00751706, 0.006998, 0.00648408, 0.00591289, 0.00524393, 0.00450313", \ - "0.0149978, 0.0114743, 0.010326, 0.00910455, 0.00833135, 0.00683411, 0.00637461", \ - "0.0271236, 0.0213991, 0.0191511, 0.0166058, 0.0138324, 0.0117272, 0.00904718", \ - "0.0513477, 0.0432865, 0.0395307, 0.0349109, 0.0298861, 0.0242017, 0.0189294", \ - "0.101325, 0.0907824, 0.0851256, 0.0779384, 0.0688008, 0.0585353, 0.0478695" \ + "0.00537227, 0.00560551, 0.00557508, 0.00547312, 0.00527659, 0.0048855, 0.00430012", \ + "0.00688701, 0.00606513, 0.00587529, 0.00578375, 0.00539082, 0.00495963, 0.00430965", \ + "0.00941924, 0.00751736, 0.00699824, 0.00648488, 0.00586489, 0.0052424, 0.00450386", \ + "0.0149965, 0.0114745, 0.0103342, 0.00903226, 0.00794352, 0.00683435, 0.00662317", \ + "0.027127, 0.021409, 0.0191481, 0.0166138, 0.0138412, 0.0117288, 0.00921367", \ + "0.0513533, 0.0432732, 0.0395306, 0.0349245, 0.0298714, 0.0241775, 0.0189518", \ + "0.101324, 0.0907825, 0.0851317, 0.0779383, 0.0688012, 0.0585375, 0.0478616" \ ); } fall_power (POWER_7x7ds1) { index_1 ("0.0186, 0.0966, 0.174, 0.3294, 0.6408, 1.263, 2.5074"); index_2 ("0.001, 0.0234, 0.039, 0.0648, 0.108, 0.18, 0.3"); values ( \ - "0.0116285, 0.0126334, 0.0125114, 0.0124371, 0.0122796, 0.0119548, 0.011215", \ - "0.0123909, 0.0124647, 0.0125463, 0.0124274, 0.0127891, 0.0120183, 0.0112931", \ - "0.0146013, 0.0133404, 0.013149, 0.0129261, 0.0131789, 0.0126449, 0.0114816", \ - "0.0200984, 0.0164264, 0.015591, 0.0148871, 0.0140344, 0.0135261, 0.0128085", \ - "0.0321603, 0.0251706, 0.0229535, 0.0207966, 0.0188567, 0.0170033, 0.0155081", \ - "0.0570992, 0.0464827, 0.0421848, 0.0372907, 0.0324004, 0.0279621, 0.0238268", \ - "0.107684, 0.0935012, 0.0866887, 0.0780993, 0.0682424, 0.0577156, 0.0478994" \ + "0.0116311, 0.0126316, 0.0125104, 0.0124482, 0.0122806, 0.0119239, 0.011214", \ + "0.0123887, 0.0124212, 0.012545, 0.0124503, 0.0123832, 0.012004, 0.0113796", \ + "0.0146018, 0.0133391, 0.0131083, 0.0128984, 0.013015, 0.0122945, 0.011553", \ + "0.0200989, 0.0164256, 0.0156459, 0.0148812, 0.0140282, 0.0138187, 0.0122139", \ + "0.0321606, 0.0251668, 0.0229538, 0.0208043, 0.0188765, 0.016849, 0.0156069", \ + "0.0570981, 0.0464823, 0.0421855, 0.0372919, 0.0323652, 0.0279459, 0.0236534", \ + "0.107685, 0.0936588, 0.0866886, 0.0781833, 0.0681946, 0.0577088, 0.0479351" \ ); } } @@ -5920,26 +5920,26 @@ library (sg13g2_stdcell_fast_1p65V_m40C) { index_1 ("0.0186, 0.0966, 0.174, 0.3294, 0.6408, 1.263, 2.5074"); index_2 ("0.001, 0.0234, 0.039, 0.0648, 0.108, 0.18, 0.3"); values ( \ - "0.00510295, 0.00575833, 0.00579882, 0.00574727, 0.00559119, 0.00519978, 0.00454568", \ - "0.00657598, 0.0059726, 0.00605576, 0.00587921, 0.00562172, 0.00516805, 0.00445976", \ - "0.00905605, 0.00725048, 0.00684177, 0.00658251, 0.0059466, 0.00541207, 0.00469997", \ - "0.0146501, 0.0110044, 0.00998219, 0.00886013, 0.00793357, 0.00685854, 0.00591215", \ - "0.0262307, 0.0202982, 0.0182404, 0.0159295, 0.0135075, 0.0115029, 0.0090369", \ - "0.0501772, 0.0412424, 0.0375924, 0.0332627, 0.0284258, 0.023322, 0.0184347", \ - "0.0992093, 0.0867522, 0.0810499, 0.0737405, 0.0650114, 0.0558915, 0.045738" \ + "0.0051025, 0.00575805, 0.00582958, 0.0057472, 0.00559451, 0.00522513, 0.00459194", \ + "0.00657383, 0.00597087, 0.00596536, 0.00587895, 0.00562193, 0.0051644, 0.00446722", \ + "0.00905552, 0.00724964, 0.00684171, 0.00657932, 0.00596072, 0.00544049, 0.00469818", \ + "0.0146536, 0.0110029, 0.0099533, 0.00880543, 0.00821253, 0.00679998, 0.00681003", \ + "0.0262308, 0.020297, 0.0182493, 0.0159252, 0.0134973, 0.0114927, 0.00867072", \ + "0.050177, 0.0412396, 0.0375916, 0.0331924, 0.0284466, 0.0233074, 0.018436", \ + "0.0992122, 0.0867515, 0.0810507, 0.0737496, 0.0650077, 0.0558917, 0.0457337" \ ); } fall_power (POWER_7x7ds1) { index_1 ("0.0186, 0.0966, 0.174, 0.3294, 0.6408, 1.263, 2.5074"); index_2 ("0.001, 0.0234, 0.039, 0.0648, 0.108, 0.18, 0.3"); values ( \ - "0.0083281, 0.00916933, 0.00918902, 0.00913017, 0.00898127, 0.00864404, 0.00795487", \ - "0.00975223, 0.00929298, 0.00937686, 0.00919368, 0.00962012, 0.00864538, 0.00800701", \ - "0.0121491, 0.0104563, 0.0100338, 0.0097991, 0.00995667, 0.00943265, 0.00835231", \ - "0.0177316, 0.0136457, 0.0127266, 0.0117587, 0.0108343, 0.0104752, 0.00882992", \ - "0.0297357, 0.0224946, 0.0202133, 0.018001, 0.0157936, 0.0136534, 0.0123299", \ - "0.0540194, 0.0434213, 0.0389856, 0.0343587, 0.0293329, 0.024742, 0.0201088", \ - "0.10361, 0.0892647, 0.0823973, 0.0740138, 0.0642528, 0.0540578, 0.0441905" \ + "0.00832888, 0.0093456, 0.00921197, 0.00915296, 0.00898386, 0.00860682, 0.00793344", \ + "0.00975029, 0.00932353, 0.00937263, 0.009202, 0.0097273, 0.00865242, 0.00793013", \ + "0.012149, 0.0104552, 0.0100317, 0.00976473, 0.00957043, 0.00944123, 0.00811526", \ + "0.0177319, 0.0136515, 0.0127443, 0.0118144, 0.0109479, 0.0105949, 0.00884739", \ + "0.0297394, 0.0224947, 0.0202119, 0.0180014, 0.0157921, 0.013651, 0.0124104", \ + "0.0540196, 0.0434192, 0.0389636, 0.034356, 0.0293358, 0.0247428, 0.0202082", \ + "0.103611, 0.0892759, 0.0823929, 0.0740142, 0.0642515, 0.054058, 0.0441982" \ ); } } @@ -5950,26 +5950,26 @@ library (sg13g2_stdcell_fast_1p65V_m40C) { index_1 ("0.0186, 0.0966, 0.174, 0.3294, 0.6408, 1.263, 2.5074"); index_2 ("0.001, 0.0234, 0.039, 0.0648, 0.108, 0.18, 0.3"); values ( \ - "0.00465697, 0.00550058, 0.00554243, 0.00551953, 0.00532958, 0.00500725, 0.00440212", \ - "0.00651806, 0.00573104, 0.00574152, 0.00564642, 0.00536468, 0.00496683, 0.00421784", \ - "0.00917991, 0.00705459, 0.00664899, 0.00621954, 0.00571659, 0.00521988, 0.00446322", \ - "0.0149783, 0.0108513, 0.00974733, 0.0086448, 0.00763897, 0.0065995, 0.00649724", \ - "0.0268568, 0.0203193, 0.018182, 0.0158469, 0.0132242, 0.0113151, 0.00862211", \ - "0.0509068, 0.0414199, 0.0377642, 0.0331523, 0.0282975, 0.023119, 0.0181374", \ - "0.100101, 0.0870495, 0.0813555, 0.0739495, 0.0649958, 0.0556207, 0.0454844" \ + "0.00465618, 0.005504, 0.00554244, 0.00548239, 0.00533854, 0.00500704, 0.00431865", \ + "0.00651808, 0.00572033, 0.00572007, 0.00564765, 0.00530017, 0.00491741, 0.00421595", \ + "0.00918042, 0.00707934, 0.00662239, 0.00621997, 0.00575226, 0.00519931, 0.00446423", \ + "0.0149787, 0.010851, 0.00973288, 0.00854399, 0.00796924, 0.00659917, 0.00645209", \ + "0.0268562, 0.0203196, 0.0181814, 0.0158568, 0.0132604, 0.0111655, 0.00857864", \ + "0.0509061, 0.0414195, 0.0378168, 0.0331526, 0.028288, 0.0231655, 0.0181443", \ + "0.100102, 0.0870586, 0.081356, 0.0739506, 0.0650052, 0.0556266, 0.0454796" \ ); } fall_power (POWER_7x7ds1) { index_1 ("0.0186, 0.0966, 0.174, 0.3294, 0.6408, 1.263, 2.5074"); index_2 ("0.001, 0.0234, 0.039, 0.0648, 0.108, 0.18, 0.3"); values ( \ - "0.00490694, 0.00580527, 0.0058847, 0.00573684, 0.00557788, 0.00524656, 0.00460906", \ - "0.00635517, 0.00592294, 0.00595095, 0.00580378, 0.00600291, 0.00539598, 0.00475447", \ - "0.00880003, 0.00702181, 0.00664635, 0.00633531, 0.00654861, 0.00607315, 0.00483651", \ - "0.01448, 0.0102328, 0.0092987, 0.00845595, 0.0074765, 0.00720264, 0.00574522", \ - "0.0265376, 0.0190633, 0.0168783, 0.0145823, 0.0124501, 0.0102173, 0.00890148", \ - "0.0509286, 0.0400158, 0.0356109, 0.0309816, 0.02604, 0.0213903, 0.0168283", \ - "0.100599, 0.08596, 0.0791077, 0.0705599, 0.0607062, 0.0508524, 0.04079" \ + "0.00490882, 0.00580626, 0.00588539, 0.00574213, 0.00557413, 0.00522165, 0.00460215", \ + "0.00635494, 0.00592562, 0.00593986, 0.00580229, 0.00613279, 0.00527022, 0.00465607", \ + "0.00880092, 0.00702126, 0.00663698, 0.00635846, 0.00646269, 0.0060729, 0.00485656", \ + "0.0144818, 0.0102319, 0.00929863, 0.00841523, 0.00745596, 0.00689623, 0.00570864", \ + "0.0265392, 0.0190521, 0.0168786, 0.0145798, 0.0125696, 0.0102162, 0.00883749", \ + "0.0509925, 0.0400282, 0.0356111, 0.0309813, 0.0260382, 0.0213139, 0.0167616", \ + "0.1006, 0.0859584, 0.0791082, 0.0706382, 0.0607064, 0.0508356, 0.040789" \ ); } } @@ -5979,26 +5979,26 @@ library (sg13g2_stdcell_fast_1p65V_m40C) { index_1 ("0.0186, 0.0966, 0.174, 0.3294, 0.6408, 1.263, 2.5074"); index_2 ("0.001, 0.0234, 0.039, 0.0648, 0.108, 0.18, 0.3"); values ( \ - "0.00510295, 0.00575833, 0.00579882, 0.00574727, 0.00559119, 0.00519978, 0.00454568", \ - "0.00657598, 0.0059726, 0.00605576, 0.00587921, 0.00562172, 0.00516805, 0.00445976", \ - "0.00905605, 0.00725048, 0.00684177, 0.00658251, 0.0059466, 0.00541207, 0.00469997", \ - "0.0146501, 0.0110044, 0.00998219, 0.00886013, 0.00793357, 0.00685854, 0.00591215", \ - "0.0262307, 0.0202982, 0.0182404, 0.0159295, 0.0135075, 0.0115029, 0.0090369", \ - "0.0501772, 0.0412424, 0.0375924, 0.0332627, 0.0284258, 0.023322, 0.0184347", \ - "0.0992093, 0.0867522, 0.0810499, 0.0737405, 0.0650114, 0.0558915, 0.045738" \ + "0.0051025, 0.00575805, 0.00582958, 0.0057472, 0.00559451, 0.00522513, 0.00459194", \ + "0.00657383, 0.00597087, 0.00596536, 0.00587895, 0.00562193, 0.0051644, 0.00446722", \ + "0.00905552, 0.00724964, 0.00684171, 0.00657932, 0.00596072, 0.00544049, 0.00469818", \ + "0.0146536, 0.0110029, 0.0099533, 0.00880543, 0.00821253, 0.00679998, 0.00681003", \ + "0.0262308, 0.020297, 0.0182493, 0.0159252, 0.0134973, 0.0114927, 0.00867072", \ + "0.050177, 0.0412396, 0.0375916, 0.0331924, 0.0284466, 0.0233074, 0.018436", \ + "0.0992122, 0.0867515, 0.0810507, 0.0737496, 0.0650077, 0.0558917, 0.0457337" \ ); } fall_power (POWER_7x7ds1) { index_1 ("0.0186, 0.0966, 0.174, 0.3294, 0.6408, 1.263, 2.5074"); index_2 ("0.001, 0.0234, 0.039, 0.0648, 0.108, 0.18, 0.3"); values ( \ - "0.0083281, 0.00916933, 0.00918902, 0.00913017, 0.00898127, 0.00864404, 0.00795487", \ - "0.00975223, 0.00929298, 0.00937686, 0.00919368, 0.00962012, 0.00864538, 0.00800701", \ - "0.0121491, 0.0104563, 0.0100338, 0.0097991, 0.00995667, 0.00943265, 0.00835231", \ - "0.0177316, 0.0136457, 0.0127266, 0.0117587, 0.0108343, 0.0104752, 0.00882992", \ - "0.0297357, 0.0224946, 0.0202133, 0.018001, 0.0157936, 0.0136534, 0.0123299", \ - "0.0540194, 0.0434213, 0.0389856, 0.0343587, 0.0293329, 0.024742, 0.0201088", \ - "0.10361, 0.0892647, 0.0823973, 0.0740138, 0.0642528, 0.0540578, 0.0441905" \ + "0.00832888, 0.0093456, 0.00921197, 0.00915296, 0.00898386, 0.00860682, 0.00793344", \ + "0.00975029, 0.00932353, 0.00937263, 0.009202, 0.0097273, 0.00865242, 0.00793013", \ + "0.012149, 0.0104552, 0.0100317, 0.00976473, 0.00957043, 0.00944123, 0.00811526", \ + "0.0177319, 0.0136515, 0.0127443, 0.0118144, 0.0109479, 0.0105949, 0.00884739", \ + "0.0297394, 0.0224947, 0.0202119, 0.0180014, 0.0157921, 0.013651, 0.0124104", \ + "0.0540196, 0.0434192, 0.0389636, 0.034356, 0.0293358, 0.0247428, 0.0202082", \ + "0.103611, 0.0892759, 0.0823929, 0.0740142, 0.0642515, 0.054058, 0.0441982" \ ); } } @@ -6006,43 +6006,43 @@ library (sg13g2_stdcell_fast_1p65V_m40C) { pin (A1) { direction : "input"; max_transition : 2.5074; - capacitance : 0.00343786; - rise_capacitance : 0.00330033; - rise_capacitance_range (0.00330033, 0.00330033); - fall_capacitance : 0.00357538; - fall_capacitance_range (0.00357538, 0.00357538); + capacitance : 0.00343779; + rise_capacitance : 0.00330019; + rise_capacitance_range (0.00308177, 0.00366168); + fall_capacitance : 0.00357539; + fall_capacitance_range (0.00303451, 0.00408309); } pin (A2) { direction : "input"; max_transition : 2.5074; - capacitance : 0.00350051; - rise_capacitance : 0.00353883; - rise_capacitance_range (0.00353883, 0.00353883); + capacitance : 0.0035005; + rise_capacitance : 0.00353881; + rise_capacitance_range (0.00302692, 0.00390142); fall_capacitance : 0.00346219; - fall_capacitance_range (0.00346219, 0.00346219); + fall_capacitance_range (0.00302026, 0.00376361); } pin (B1) { direction : "input"; max_transition : 2.5074; - capacitance : 0.00336987; - rise_capacitance : 0.00361881; - rise_capacitance_range (0.00361881, 0.00361881); - fall_capacitance : 0.00312093; - fall_capacitance_range (0.00312093, 0.00312093); + capacitance : 0.00336992; + rise_capacitance : 0.0036189; + rise_capacitance_range (0.00290382, 0.0043984); + fall_capacitance : 0.00312094; + fall_capacitance_range (0.00294372, 0.00335851); } pin (B2) { direction : "input"; max_transition : 2.5074; - capacitance : 0.00327411; - rise_capacitance : 0.00334906; - rise_capacitance_range (0.00334906, 0.00334906); - fall_capacitance : 0.00319916; - fall_capacitance_range (0.00319916, 0.00319916); + capacitance : 0.00327409; + rise_capacitance : 0.00334904; + rise_capacitance_range (0.0028586, 0.00410386); + fall_capacitance : 0.00319913; + fall_capacitance_range (0.00287737, 0.00361658); } } cell (sg13g2_and2_1) { area : 9.072; - cell_footprint : "AND2"; + cell_footprint : "and2"; cell_leakage_power : 1184.62; leakage_power () { value : 1417.22; @@ -6243,23 +6243,23 @@ library (sg13g2_stdcell_fast_1p65V_m40C) { max_transition : 2.5074; capacitance : 0.00286735; rise_capacitance : 0.00280951; - rise_capacitance_range (0.00280951, 0.00280951); + rise_capacitance_range (0.00249232, 0.00302567); fall_capacitance : 0.00292518; - fall_capacitance_range (0.00292518, 0.00292518); + fall_capacitance_range (0.0025065, 0.00325711); } pin (B) { direction : "input"; max_transition : 2.5074; capacitance : 0.00289023; rise_capacitance : 0.00300219; - rise_capacitance_range (0.00300219, 0.00300219); + rise_capacitance_range (0.00247595, 0.00326351); fall_capacitance : 0.00277827; - fall_capacitance_range (0.00277827, 0.00277827); + fall_capacitance_range (0.00253244, 0.00295478); } } cell (sg13g2_and2_2) { area : 10.8864; - cell_footprint : "AND2"; + cell_footprint : "and2"; cell_leakage_power : 1783.96; leakage_power () { value : 1625.88; @@ -6460,23 +6460,23 @@ library (sg13g2_stdcell_fast_1p65V_m40C) { max_transition : 2.5074; capacitance : 0.00283946; rise_capacitance : 0.00278993; - rise_capacitance_range (0.00278993, 0.00278993); + rise_capacitance_range (0.00251549, 0.00299636); fall_capacitance : 0.002889; - fall_capacitance_range (0.002889, 0.002889); + fall_capacitance_range (0.0025346, 0.00317935); } pin (B) { direction : "input"; max_transition : 2.5074; capacitance : 0.00289185; rise_capacitance : 0.00300389; - rise_capacitance_range (0.00300389, 0.00300389); + rise_capacitance_range (0.00251253, 0.00324514); fall_capacitance : 0.00277981; - fall_capacitance_range (0.00277981, 0.00277981); + fall_capacitance_range (0.00256057, 0.00295123); } } cell (sg13g2_and3_1) { area : 12.7008; - cell_footprint : "AND3"; + cell_footprint : "and3"; cell_leakage_power : 1378.37; leakage_power () { value : 2021.55; @@ -6779,32 +6779,32 @@ library (sg13g2_stdcell_fast_1p65V_m40C) { max_transition : 2.5074; capacitance : 0.00286435; rise_capacitance : 0.00273535; - rise_capacitance_range (0.00273535, 0.00273535); + rise_capacitance_range (0.00247727, 0.00288544); fall_capacitance : 0.00299335; - fall_capacitance_range (0.00299335, 0.00299335); + fall_capacitance_range (0.0024706, 0.00345403); } pin (B) { direction : "input"; max_transition : 2.5074; capacitance : 0.0028587; rise_capacitance : 0.00288221; - rise_capacitance_range (0.00288221, 0.00288221); + rise_capacitance_range (0.00240897, 0.00307801); fall_capacitance : 0.0028352; - fall_capacitance_range (0.0028352, 0.0028352); + fall_capacitance_range (0.00246338, 0.00313821); } pin (C) { direction : "input"; max_transition : 2.5074; capacitance : 0.00287984; rise_capacitance : 0.00299612; - rise_capacitance_range (0.00299612, 0.00299612); + rise_capacitance_range (0.00247597, 0.00327627); fall_capacitance : 0.00276356; - fall_capacitance_range (0.00276356, 0.00276356); + fall_capacitance_range (0.00253131, 0.00294633); } } cell (sg13g2_and3_2) { area : 12.7008; - cell_footprint : "AND3"; + cell_footprint : "and3"; cell_leakage_power : 2042.83; leakage_power () { value : 2230.18; @@ -7107,32 +7107,32 @@ library (sg13g2_stdcell_fast_1p65V_m40C) { max_transition : 2.5074; capacitance : 0.0028564; rise_capacitance : 0.00274849; - rise_capacitance_range (0.00274849, 0.00274849); + rise_capacitance_range (0.00252389, 0.00289634); fall_capacitance : 0.00296431; - fall_capacitance_range (0.00296431, 0.00296431); + fall_capacitance_range (0.00253157, 0.00335104); } pin (B) { direction : "input"; max_transition : 2.5074; capacitance : 0.00285307; rise_capacitance : 0.00288799; - rise_capacitance_range (0.00288799, 0.00288799); + rise_capacitance_range (0.00243451, 0.00307782); fall_capacitance : 0.00281816; - fall_capacitance_range (0.00281816, 0.00281816); + fall_capacitance_range (0.00249153, 0.00309579); } pin (C) { direction : "input"; max_transition : 2.5074; capacitance : 0.00287277; rise_capacitance : 0.00299237; - rise_capacitance_range (0.00299237, 0.00299237); + rise_capacitance_range (0.00249126, 0.00325642); fall_capacitance : 0.00275316; - fall_capacitance_range (0.00275316, 0.00275316); + fall_capacitance_range (0.00254383, 0.00292886); } } cell (sg13g2_and4_1) { area : 14.5152; - cell_footprint : "AND4"; + cell_footprint : "and4"; cell_leakage_power : 1505.63; leakage_power () { value : 1277.08; @@ -7553,41 +7553,41 @@ library (sg13g2_stdcell_fast_1p65V_m40C) { max_transition : 2.5074; capacitance : 0.00270786; rise_capacitance : 0.0025318; - rise_capacitance_range (0.0025318, 0.0025318); + rise_capacitance_range (0.00230999, 0.00265043); fall_capacitance : 0.00288392; - fall_capacitance_range (0.00288392, 0.00288392); + fall_capacitance_range (0.00229688, 0.00345099); } pin (B) { direction : "input"; max_transition : 2.5074; capacitance : 0.00284733; rise_capacitance : 0.002816; - rise_capacitance_range (0.002816, 0.002816); + rise_capacitance_range (0.00237537, 0.00298605); fall_capacitance : 0.00287866; - fall_capacitance_range (0.00287866, 0.00287866); + fall_capacitance_range (0.00241976, 0.00328816); } pin (C) { direction : "input"; max_transition : 2.5074; capacitance : 0.00283769; rise_capacitance : 0.00287741; - rise_capacitance_range (0.00287741, 0.00287741); + rise_capacitance_range (0.00239464, 0.00310084); fall_capacitance : 0.00279797; - fall_capacitance_range (0.00279797, 0.00279797); + fall_capacitance_range (0.00245287, 0.0030887); } pin (D) { direction : "input"; max_transition : 2.5074; capacitance : 0.00285652; rise_capacitance : 0.00297491; - rise_capacitance_range (0.00297491, 0.00297491); + rise_capacitance_range (0.0024587, 0.0032742); fall_capacitance : 0.00273813; - fall_capacitance_range (0.00273813, 0.00273813); + fall_capacitance_range (0.0025135, 0.00292506); } } cell (sg13g2_and4_2) { area : 16.3296; - cell_footprint : "AND4"; + cell_footprint : "and4"; cell_leakage_power : 2202.62; leakage_power () { value : 2006.63; @@ -8008,41 +8008,41 @@ library (sg13g2_stdcell_fast_1p65V_m40C) { max_transition : 2.5074; capacitance : 0.00268173; rise_capacitance : 0.00253342; - rise_capacitance_range (0.00253342, 0.00253342); + rise_capacitance_range (0.00234016, 0.00265154); fall_capacitance : 0.00283003; - fall_capacitance_range (0.00283003, 0.00283003); + fall_capacitance_range (0.0023467, 0.00331024); } pin (B) { direction : "input"; max_transition : 2.5074; capacitance : 0.0028259; rise_capacitance : 0.00281185; - rise_capacitance_range (0.00281185, 0.00281185); + rise_capacitance_range (0.00238668, 0.00297889); fall_capacitance : 0.00283996; - fall_capacitance_range (0.00283996, 0.00283996); + fall_capacitance_range (0.00244234, 0.00320839); } pin (C) { direction : "input"; max_transition : 2.5074; capacitance : 0.00282397; rise_capacitance : 0.00287436; - rise_capacitance_range (0.00287436, 0.00287436); + rise_capacitance_range (0.00240921, 0.00309069); fall_capacitance : 0.00277358; - fall_capacitance_range (0.00277358, 0.00277358); + fall_capacitance_range (0.00246796, 0.00303929); } pin (D) { direction : "input"; max_transition : 2.5074; capacitance : 0.002845; rise_capacitance : 0.00296784; - rise_capacitance_range (0.00296784, 0.00296784); + rise_capacitance_range (0.00246959, 0.0032514); fall_capacitance : 0.00272215; - fall_capacitance_range (0.00272215, 0.00272215); + fall_capacitance_range (0.00251779, 0.00290307); } } cell (sg13g2_antennanp) { area : 5.4432; - cell_footprint : "NP_ant"; + cell_footprint : "antennanp"; cell_leakage_power : 8.16743; dont_touch : true; dont_use : true; @@ -8059,9 +8059,9 @@ library (sg13g2_stdcell_fast_1p65V_m40C) { max_transition : 2.5074; capacitance : 0.00102989; rise_capacitance : 0.000996312; - rise_capacitance_range (0.000996312, 0.000996312); + rise_capacitance_range (0.000265164, 0.00156752); fall_capacitance : 0.00106347; - fall_capacitance_range (0.00106347, 0.00106347); + fall_capacitance_range (0.000270975, 0.00165929); internal_power () { rise_power (passive_POWER_7x1ds1) { index_1 ("0.0186, 0.0966, 0.174, 0.3294, 0.6408, 1.263, 2.5074"); @@ -8080,7 +8080,7 @@ library (sg13g2_stdcell_fast_1p65V_m40C) { } cell (sg13g2_buf_1) { area : 7.2576; - cell_footprint : "BU"; + cell_footprint : "buf"; cell_leakage_power : 797.513; leakage_power () { value : 883.19; @@ -8187,14 +8187,14 @@ library (sg13g2_stdcell_fast_1p65V_m40C) { max_transition : 2.5074; capacitance : 0.00257952; rise_capacitance : 0.00262204; - rise_capacitance_range (0.00262204, 0.00262204); + rise_capacitance_range (0.00228072, 0.0028898); fall_capacitance : 0.00253699; - fall_capacitance_range (0.00253699, 0.00253699); + fall_capacitance_range (0.00226479, 0.00276425); } } cell (sg13g2_buf_16) { area : 45.36; - cell_footprint : "BU"; + cell_footprint : "buf"; cell_leakage_power : 10319.4; leakage_power () { value : 7714.52; @@ -8301,14 +8301,14 @@ library (sg13g2_stdcell_fast_1p65V_m40C) { max_transition : 2.5074; capacitance : 0.0193695; rise_capacitance : 0.0197196; - rise_capacitance_range (0.0197196, 0.0197196); + rise_capacitance_range (0.0172049, 0.0217624); fall_capacitance : 0.0190195; - fall_capacitance_range (0.0190195, 0.0190195); + fall_capacitance_range (0.017029, 0.0206135); } } cell (sg13g2_buf_2) { area : 9.072; - cell_footprint : "BU"; + cell_footprint : "buf"; cell_leakage_power : 1336.14; leakage_power () { value : 1643.58; @@ -8415,14 +8415,14 @@ library (sg13g2_stdcell_fast_1p65V_m40C) { max_transition : 2.5074; capacitance : 0.00296674; rise_capacitance : 0.00301633; - rise_capacitance_range (0.00301633, 0.00301633); + rise_capacitance_range (0.00266176, 0.00330273); fall_capacitance : 0.00291716; - fall_capacitance_range (0.00291716, 0.00291716); + fall_capacitance_range (0.00262497, 0.00316726); } } cell (sg13g2_buf_4) { area : 14.5152; - cell_footprint : "BU"; + cell_footprint : "buf"; cell_leakage_power : 2412.17; leakage_power () { value : 1614.29; @@ -8529,14 +8529,14 @@ library (sg13g2_stdcell_fast_1p65V_m40C) { max_transition : 2.5074; capacitance : 0.00419591; rise_capacitance : 0.00426832; - rise_capacitance_range (0.00426832, 0.00426832); + rise_capacitance_range (0.00389185, 0.00451123); fall_capacitance : 0.0041235; - fall_capacitance_range (0.0041235, 0.0041235); + fall_capacitance_range (0.00360346, 0.00472188); } } cell (sg13g2_buf_8) { area : 23.5872; - cell_footprint : "BU"; + cell_footprint : "buf"; cell_leakage_power : 5159.68; leakage_power () { value : 3857.25; @@ -8643,14 +8643,14 @@ library (sg13g2_stdcell_fast_1p65V_m40C) { max_transition : 2.5074; capacitance : 0.00972672; rise_capacitance : 0.0099021; - rise_capacitance_range (0.0099021, 0.0099021); + rise_capacitance_range (0.00870302, 0.0109137); fall_capacitance : 0.00955133; - fall_capacitance_range (0.00955133, 0.00955133); + fall_capacitance_range (0.00860051, 0.010339); } } cell (sg13g2_decap_4) { area : 7.2576; - cell_footprint : "DECAP"; + cell_footprint : "decap"; cell_leakage_power : 5984.41; dont_touch : true; dont_use : true; @@ -8658,7 +8658,7 @@ library (sg13g2_stdcell_fast_1p65V_m40C) { } cell (sg13g2_decap_8) { area : 12.7008; - cell_footprint : "DECAP"; + cell_footprint : "decap"; cell_leakage_power : 11968.8; dont_touch : true; dont_use : true; @@ -8666,7 +8666,7 @@ library (sg13g2_stdcell_fast_1p65V_m40C) { } cell (sg13g2_dfrbp_1) { area : 52.6176; - cell_footprint : "dffrr"; + cell_footprint : "dfrbp"; cell_leakage_power : 4742.33; leakage_power () { value : 3924.49; @@ -8723,6 +8723,7 @@ library (sg13g2_stdcell_fast_1p65V_m40C) { max_capacitance : 0.3; timing () { related_pin : "CLK"; + sdf_edges : start_edge; timing_sense : non_unate; timing_type : rising_edge; cell_rise (TIMING_DELAY_7x7ds1) { @@ -8780,6 +8781,7 @@ library (sg13g2_stdcell_fast_1p65V_m40C) { } timing () { related_pin : "RESET_B"; + sdf_edges : start_edge; timing_sense : positive_unate; timing_type : clear; cell_fall (TIMING_DELAY_7x7ds1) { @@ -8867,6 +8869,7 @@ library (sg13g2_stdcell_fast_1p65V_m40C) { max_capacitance : 0.3; timing () { related_pin : "CLK"; + sdf_edges : start_edge; timing_sense : non_unate; timing_type : rising_edge; cell_rise (TIMING_DELAY_7x7ds1) { @@ -8924,6 +8927,7 @@ library (sg13g2_stdcell_fast_1p65V_m40C) { } timing () { related_pin : "RESET_B"; + sdf_edges : start_edge; timing_sense : negative_unate; timing_type : preset; cell_rise (TIMING_DELAY_7x7ds1) { @@ -9010,9 +9014,9 @@ library (sg13g2_stdcell_fast_1p65V_m40C) { max_transition : 2.5074; capacitance : 0.00319159; rise_capacitance : 0.00338271; - rise_capacitance_range (0.00338271, 0.00338271); + rise_capacitance_range (0.00296599, 0.00373708); fall_capacitance : 0.00290491; - fall_capacitance_range (0.00290491, 0.00290491); + fall_capacitance_range (0.00290491, 0.00351762); timing () { related_pin : "CLK"; timing_type : min_pulse_width; @@ -9138,11 +9142,12 @@ library (sg13g2_stdcell_fast_1p65V_m40C) { max_transition : 2.5074; capacitance : 0.00171429; rise_capacitance : 0.00156704; - rise_capacitance_range (0.00156704, 0.00156704); + rise_capacitance_range (0.00146244, 0.00190092); fall_capacitance : 0.00186154; - fall_capacitance_range (0.00186154, 0.00186154); + fall_capacitance_range (0.00186154, 0.00290503); timing () { related_pin : "CLK"; + sdf_edges : both_edges; timing_type : hold_rising; rise_constraint (CONSTRAINT_4x4) { index_1 ("0.0186, 0.51636, 1.263, 2.5074"); @@ -9167,6 +9172,7 @@ library (sg13g2_stdcell_fast_1p65V_m40C) { } timing () { related_pin : "CLK"; + sdf_edges : both_edges; timing_type : setup_rising; rise_constraint (CONSTRAINT_4x4) { index_1 ("0.0186, 0.51636, 1.263, 2.5074"); @@ -9254,11 +9260,12 @@ library (sg13g2_stdcell_fast_1p65V_m40C) { max_transition : 2.5074; capacitance : 0.00574763; rise_capacitance : 0.00605583; - rise_capacitance_range (0.00605583, 0.00605583); + rise_capacitance_range (0.00485591, 0.00682243); fall_capacitance : 0.00552749; - fall_capacitance_range (0.00552749, 0.00552749); + fall_capacitance_range (0.00507894, 0.00587669); timing () { related_pin : "CLK"; + sdf_edges : both_edges; timing_type : recovery_rising; rise_constraint (CONSTRAINT_4x4) { index_1 ("0.0186, 0.51636, 1.263, 2.5074"); @@ -9273,6 +9280,7 @@ library (sg13g2_stdcell_fast_1p65V_m40C) { } timing () { related_pin : "CLK"; + sdf_edges : both_edges; timing_type : removal_rising; rise_constraint (CONSTRAINT_4x4) { index_1 ("0.0186, 0.51636, 1.263, 2.5074"); @@ -9371,14 +9379,14 @@ library (sg13g2_stdcell_fast_1p65V_m40C) { } } ff (IQ,IQN) { - clear : "RESET_B'"; + clear : "!RESET_B"; clocked_on : "CLK"; next_state : "D"; } } cell (sg13g2_dfrbp_2) { area : 54.432; - cell_footprint : "dffrr"; + cell_footprint : "dfrbp"; cell_leakage_power : 5625.06; leakage_power () { value : 4838.53; @@ -9435,6 +9443,7 @@ library (sg13g2_stdcell_fast_1p65V_m40C) { max_capacitance : 0.6; timing () { related_pin : "CLK"; + sdf_edges : start_edge; timing_sense : non_unate; timing_type : rising_edge; cell_rise (TIMING_DELAY_7x7ds1) { @@ -9492,6 +9501,7 @@ library (sg13g2_stdcell_fast_1p65V_m40C) { } timing () { related_pin : "RESET_B"; + sdf_edges : start_edge; timing_sense : positive_unate; timing_type : clear; cell_fall (TIMING_DELAY_7x7ds1) { @@ -9579,6 +9589,7 @@ library (sg13g2_stdcell_fast_1p65V_m40C) { max_capacitance : 0.6; timing () { related_pin : "CLK"; + sdf_edges : start_edge; timing_sense : non_unate; timing_type : rising_edge; cell_rise (TIMING_DELAY_7x7ds1) { @@ -9636,6 +9647,7 @@ library (sg13g2_stdcell_fast_1p65V_m40C) { } timing () { related_pin : "RESET_B"; + sdf_edges : start_edge; timing_sense : negative_unate; timing_type : preset; cell_rise (TIMING_DELAY_7x7ds1) { @@ -9722,9 +9734,9 @@ library (sg13g2_stdcell_fast_1p65V_m40C) { max_transition : 2.5074; capacitance : 0.00319958; rise_capacitance : 0.00339125; - rise_capacitance_range (0.00339125, 0.00339125); + rise_capacitance_range (0.00297187, 0.0037457); fall_capacitance : 0.00291208; - fall_capacitance_range (0.00291208, 0.00291208); + fall_capacitance_range (0.00291208, 0.00352633); timing () { related_pin : "CLK"; timing_type : min_pulse_width; @@ -9850,11 +9862,12 @@ library (sg13g2_stdcell_fast_1p65V_m40C) { max_transition : 2.5074; capacitance : 0.00171802; rise_capacitance : 0.00157068; - rise_capacitance_range (0.00157068, 0.00157068); + rise_capacitance_range (0.00146664, 0.00190415); fall_capacitance : 0.00186536; - fall_capacitance_range (0.00186536, 0.00186536); + fall_capacitance_range (0.00186536, 0.00290881); timing () { related_pin : "CLK"; + sdf_edges : both_edges; timing_type : hold_rising; rise_constraint (CONSTRAINT_4x4) { index_1 ("0.0186, 0.51636, 1.263, 2.5074"); @@ -9879,6 +9892,7 @@ library (sg13g2_stdcell_fast_1p65V_m40C) { } timing () { related_pin : "CLK"; + sdf_edges : both_edges; timing_type : setup_rising; rise_constraint (CONSTRAINT_4x4) { index_1 ("0.0186, 0.51636, 1.263, 2.5074"); @@ -9966,11 +9980,12 @@ library (sg13g2_stdcell_fast_1p65V_m40C) { max_transition : 2.5074; capacitance : 0.00579858; rise_capacitance : 0.00610637; - rise_capacitance_range (0.00610637, 0.00610637); + rise_capacitance_range (0.00488821, 0.00687281); fall_capacitance : 0.00557873; - fall_capacitance_range (0.00557873, 0.00557873); + fall_capacitance_range (0.00512705, 0.00593004); timing () { related_pin : "CLK"; + sdf_edges : both_edges; timing_type : recovery_rising; rise_constraint (CONSTRAINT_4x4) { index_1 ("0.0186, 0.51636, 1.263, 2.5074"); @@ -9985,6 +10000,7 @@ library (sg13g2_stdcell_fast_1p65V_m40C) { } timing () { related_pin : "CLK"; + sdf_edges : both_edges; timing_type : removal_rising; rise_constraint (CONSTRAINT_4x4) { index_1 ("0.0186, 0.51636, 1.263, 2.5074"); @@ -10083,7 +10099,7 @@ library (sg13g2_stdcell_fast_1p65V_m40C) { } } ff (IQ,IQN) { - clear : "RESET_B'"; + clear : "!RESET_B"; clocked_on : "CLK"; next_state : "D"; } @@ -10147,89 +10163,91 @@ library (sg13g2_stdcell_fast_1p65V_m40C) { max_capacitance : 0.3; timing () { related_pin : "CLK"; + sdf_edges : start_edge; timing_sense : non_unate; timing_type : rising_edge; cell_rise (TIMING_DELAY_7x7ds1) { index_1 ("0.0186, 0.0966, 0.174, 0.3294, 0.6408, 1.263, 2.5074"); index_2 ("0.001, 0.0234, 0.039, 0.0648, 0.108, 0.18, 0.3"); values ( \ - "0.0750482, 0.106479, 0.127183, 0.160988, 0.21743, 0.311661, 0.468605", \ - "0.0940419, 0.12546, 0.146041, 0.17989, 0.236427, 0.330572, 0.487476", \ - "0.10648, 0.13789, 0.158441, 0.192278, 0.248867, 0.342964, 0.499832", \ - "0.124786, 0.156221, 0.176764, 0.210632, 0.267197, 0.36131, 0.518184", \ - "0.147501, 0.178964, 0.199517, 0.233373, 0.289976, 0.384103, 0.540965", \ - "0.176599, 0.208244, 0.228815, 0.26265, 0.319215, 0.413388, 0.570268", \ - "0.211244, 0.24329, 0.26384, 0.297684, 0.35421, 0.448409, 0.605276" \ + "0.0750484, 0.106467, 0.127161, 0.160974, 0.217344, 0.311503, 0.468404", \ + "0.0940555, 0.125476, 0.146025, 0.179861, 0.236371, 0.330508, 0.487269", \ + "0.106488, 0.137881, 0.158425, 0.192239, 0.248803, 0.342856, 0.499645", \ + "0.124801, 0.15619, 0.176739, 0.210569, 0.267088, 0.361185, 0.517975", \ + "0.14752, 0.178967, 0.199503, 0.233348, 0.289921, 0.383997, 0.540775", \ + "0.176613, 0.208264, 0.228825, 0.26264, 0.319173, 0.413295, 0.570089", \ + "0.211319, 0.24335, 0.263889, 0.297709, 0.354207, 0.448352, 0.605131" \ ); } rise_transition (TIMING_DELAY_7x7ds1) { index_1 ("0.0186, 0.0966, 0.174, 0.3294, 0.6408, 1.263, 2.5074"); index_2 ("0.001, 0.0234, 0.039, 0.0648, 0.108, 0.18, 0.3"); values ( \ - "0.0088197, 0.0507519, 0.0811334, 0.131675, 0.216378, 0.357949, 0.593786", \ - "0.0088531, 0.0507529, 0.0811344, 0.131676, 0.21641, 0.358665, 0.59475", \ - "0.0088967, 0.0507539, 0.0811354, 0.131677, 0.216411, 0.358666, 0.594751", \ - "0.0090035, 0.0507549, 0.0811364, 0.131678, 0.216418, 0.358667, 0.594752", \ - "0.0093009, 0.0507559, 0.0811374, 0.131679, 0.216428, 0.358668, 0.594753", \ - "0.009804, 0.0507569, 0.0811384, 0.13168, 0.216434, 0.358669, 0.594754", \ - "0.010726, 0.050821, 0.081172, 0.131725, 0.216467, 0.35867, 0.594755" \ + "0.0088312, 0.0505607, 0.0810781, 0.131607, 0.21627, 0.357858, 0.593477", \ + "0.0088496, 0.0505617, 0.0810791, 0.131608, 0.216299, 0.358028, 0.594441", \ + "0.0088954, 0.0505627, 0.0810801, 0.131609, 0.2163, 0.358029, 0.594442", \ + "0.0090151, 0.0505637, 0.0810811, 0.13161, 0.216301, 0.35803, 0.594443", \ + "0.0092993, 0.0505647, 0.0810821, 0.131611, 0.216315, 0.358031, 0.594444", \ + "0.009782, 0.050583, 0.0810831, 0.131612, 0.216317, 0.358032, 0.594445", \ + "0.010725, 0.050794, 0.081126, 0.131633, 0.216345, 0.358033, 0.594446" \ ); } cell_fall (TIMING_DELAY_7x7ds1) { index_1 ("0.0186, 0.0966, 0.174, 0.3294, 0.6408, 1.263, 2.5074"); index_2 ("0.001, 0.0234, 0.039, 0.0648, 0.108, 0.18, 0.3"); values ( \ - "0.0751625, 0.103065, 0.12064, 0.149515, 0.197721, 0.277994, 0.411764", \ - "0.093583, 0.121534, 0.139109, 0.167935, 0.216114, 0.29635, 0.430115", \ - "0.105393, 0.133303, 0.150877, 0.179713, 0.227885, 0.308113, 0.441816", \ - "0.122254, 0.150193, 0.167759, 0.196617, 0.244793, 0.325034, 0.458695", \ - "0.141742, 0.169642, 0.187209, 0.216085, 0.26424, 0.344471, 0.478195", \ - "0.165881, 0.193968, 0.211545, 0.240389, 0.288586, 0.368793, 0.502556", \ - "0.193333, 0.221236, 0.238816, 0.267658, 0.31586, 0.396087, 0.529849" \ + "0.0751271, 0.10304, 0.120651, 0.149478, 0.197752, 0.278009, 0.41174", \ + "0.093606, 0.121523, 0.139111, 0.167941, 0.216107, 0.296355, 0.430127", \ + "0.105371, 0.133288, 0.150853, 0.179698, 0.227901, 0.308116, 0.441811", \ + "0.122251, 0.150194, 0.167754, 0.196621, 0.244802, 0.325046, 0.458709", \ + "0.141744, 0.169644, 0.187214, 0.216091, 0.264248, 0.344502, 0.478207", \ + "0.16589, 0.193792, 0.211359, 0.2402, 0.2884, 0.368634, 0.502376", \ + "0.193387, 0.22129, 0.238872, 0.267716, 0.31592, 0.396139, 0.529912" \ ); } fall_transition (TIMING_DELAY_7x7ds1) { index_1 ("0.0186, 0.0966, 0.174, 0.3294, 0.6408, 1.263, 2.5074"); index_2 ("0.001, 0.0234, 0.039, 0.0648, 0.108, 0.18, 0.3"); values ( \ - "0.0076053, 0.0408892, 0.0650969, 0.105382, 0.173078, 0.286007, 0.474403", \ - "0.0076063, 0.0408902, 0.0650979, 0.105383, 0.173079, 0.286008, 0.474404", \ - "0.0076073, 0.0408912, 0.0650989, 0.10543, 0.17308, 0.286009, 0.474405", \ - "0.0076083, 0.0408922, 0.0650999, 0.105431, 0.173081, 0.28601, 0.474406", \ - "0.0076093, 0.0408932, 0.0651009, 0.105432, 0.173115, 0.286011, 0.474407", \ - "0.0076103, 0.0408942, 0.0651019, 0.105433, 0.173135, 0.286041, 0.474408", \ - "0.007655, 0.0408952, 0.0651029, 0.105434, 0.173136, 0.286077, 0.474409" \ + "0.0075763, 0.0408892, 0.0650954, 0.105378, 0.173197, 0.286007, 0.474403", \ + "0.0075923, 0.0408902, 0.0650964, 0.105379, 0.173198, 0.286008, 0.474858", \ + "0.0075973, 0.0408912, 0.0650974, 0.10538, 0.173199, 0.286009, 0.474859", \ + "0.0075983, 0.0408922, 0.0650984, 0.105381, 0.1732, 0.28601, 0.47486", \ + "0.0075993, 0.0408932, 0.0650994, 0.105382, 0.173201, 0.28602, 0.474861", \ + "0.0076003, 0.0408942, 0.0651004, 0.105398, 0.173202, 0.286045, 0.474862", \ + "0.007652, 0.0408952, 0.0651014, 0.105399, 0.173203, 0.286046, 0.474863" \ ); } } timing () { related_pin : "RESET_B"; + sdf_edges : start_edge; timing_sense : positive_unate; timing_type : clear; cell_fall (TIMING_DELAY_7x7ds1) { index_1 ("0.0186, 0.0966, 0.174, 0.3294, 0.6408, 1.263, 2.5074"); index_2 ("0.001, 0.0234, 0.039, 0.0648, 0.108, 0.18, 0.3"); values ( \ - "0.105477, 0.133377, 0.150919, 0.179774, 0.228025, 0.308294, 0.442133", \ - "0.13408, 0.161947, 0.179523, 0.208331, 0.256566, 0.336837, 0.470606", \ - "0.153111, 0.181073, 0.198642, 0.227569, 0.275737, 0.355996, 0.489717", \ - "0.181738, 0.209705, 0.227304, 0.256139, 0.304375, 0.384635, 0.518379", \ - "0.222709, 0.250663, 0.268206, 0.297085, 0.345345, 0.425647, 0.559286", \ - "0.284347, 0.312355, 0.3299, 0.358791, 0.407053, 0.487331, 0.621149", \ - "0.378683, 0.406717, 0.424294, 0.45323, 0.501404, 0.581694, 0.715547" \ + "0.105437, 0.133375, 0.150952, 0.179779, 0.22804, 0.308305, 0.442134", \ + "0.134032, 0.161937, 0.179514, 0.208323, 0.256559, 0.336831, 0.470496", \ + "0.153082, 0.181062, 0.198657, 0.227562, 0.275732, 0.355992, 0.489714", \ + "0.181726, 0.209693, 0.227294, 0.25613, 0.304368, 0.384632, 0.518375", \ + "0.222697, 0.25065, 0.268195, 0.297075, 0.345338, 0.425641, 0.559269", \ + "0.28433, 0.312301, 0.329884, 0.358774, 0.407039, 0.487334, 0.621141", \ + "0.378668, 0.406702, 0.424281, 0.453218, 0.501395, 0.581687, 0.715544" \ ); } fall_transition (TIMING_DELAY_7x7ds1) { index_1 ("0.0186, 0.0966, 0.174, 0.3294, 0.6408, 1.263, 2.5074"); index_2 ("0.001, 0.0234, 0.039, 0.0648, 0.108, 0.18, 0.3"); values ( \ - "0.0075844, 0.0408437, 0.0650466, 0.105332, 0.173047, 0.285989, 0.474248", \ - "0.0076045, 0.0408444, 0.0650476, 0.105381, 0.173107, 0.286078, 0.47465", \ - "0.0076097, 0.0408602, 0.0650486, 0.105382, 0.173108, 0.286079, 0.474651", \ - "0.0076746, 0.0408651, 0.0650537, 0.105383, 0.173109, 0.28608, 0.474652", \ - "0.0077533, 0.0408932, 0.0650547, 0.105384, 0.17311, 0.286081, 0.474653", \ - "0.007861, 0.040927, 0.065101, 0.105434, 0.173111, 0.286082, 0.474654", \ - "0.007991, 0.040969, 0.065102, 0.105435, 0.173118, 0.286083, 0.474655" \ + "0.0075771, 0.0408433, 0.0650607, 0.105331, 0.173023, 0.285988, 0.474247", \ + "0.0075826, 0.0408443, 0.0650617, 0.10538, 0.173105, 0.286078, 0.474611", \ + "0.0075986, 0.0408591, 0.0650627, 0.105381, 0.173106, 0.286079, 0.474612", \ + "0.0076726, 0.0408634, 0.0650637, 0.105382, 0.173107, 0.28608, 0.474613", \ + "0.0077515, 0.0408915, 0.0650647, 0.105386, 0.173108, 0.286081, 0.474614", \ + "0.007859, 0.040937, 0.065099, 0.105433, 0.173109, 0.286082, 0.474615", \ + "0.007989, 0.040967, 0.0651, 0.105434, 0.173118, 0.286083, 0.474616" \ ); } } @@ -10239,26 +10257,26 @@ library (sg13g2_stdcell_fast_1p65V_m40C) { index_1 ("0.0186, 0.0966, 0.174, 0.3294, 0.6408, 1.263, 2.5074"); index_2 ("0.001, 0.0234, 0.039, 0.0648, 0.108, 0.18, 0.3"); values ( \ - "0.0501437, 0.0506597, 0.0506871, 0.0506243, 0.0503113, 0.0499675, 0.0492485", \ - "0.0523651, 0.0528189, 0.0528386, 0.0531009, 0.0526168, 0.0524634, 0.0520086", \ - "0.055785, 0.0563292, 0.0563677, 0.0561474, 0.0562225, 0.0557189, 0.0558924", \ - "0.0644726, 0.064973, 0.0650504, 0.0651392, 0.0649509, 0.0644647, 0.0653713", \ - "0.0825095, 0.0829111, 0.0829693, 0.0830537, 0.083087, 0.0829396, 0.0821038", \ - "0.119944, 0.120311, 0.120187, 0.120232, 0.120119, 0.120197, 0.120107", \ - "0.195287, 0.195642, 0.195587, 0.195467, 0.195067, 0.195093, 0.194801" \ + "0.0500644, 0.0506154, 0.0506831, 0.050648, 0.0503138, 0.0499497, 0.0492525", \ + "0.0523739, 0.0528431, 0.0528403, 0.0531007, 0.052617, 0.0523025, 0.0520234", \ + "0.0557881, 0.0563358, 0.0563584, 0.0561435, 0.0562581, 0.0557634, 0.0558505", \ + "0.0644627, 0.0649503, 0.0650013, 0.065106, 0.0649294, 0.0644671, 0.0650679", \ + "0.0825156, 0.0829343, 0.0830055, 0.0830558, 0.0831164, 0.0829025, 0.0820193", \ + "0.119948, 0.120336, 0.120215, 0.120281, 0.120173, 0.120231, 0.12018", \ + "0.195565, 0.195669, 0.195708, 0.195629, 0.195139, 0.195207, 0.195001" \ ); } fall_power (POWER_7x7ds1) { index_1 ("0.0186, 0.0966, 0.174, 0.3294, 0.6408, 1.263, 2.5074"); index_2 ("0.001, 0.0234, 0.039, 0.0648, 0.108, 0.18, 0.3"); values ( \ - "0.0515972, 0.0522692, 0.0522539, 0.0522166, 0.0520235, 0.0517371, 0.0509121", \ - "0.0540604, 0.054752, 0.054698, 0.0547721, 0.0547191, 0.0551134, 0.0534215", \ - "0.0576241, 0.0583454, 0.0584232, 0.0583454, 0.0580217, 0.0584168, 0.0569327", \ - "0.0659122, 0.0666232, 0.0667602, 0.0668254, 0.0667737, 0.0663825, 0.0661322", \ - "0.083338, 0.0839961, 0.0841201, 0.0840149, 0.0841427, 0.0840801, 0.0838401", \ - "0.1185, 0.119292, 0.119202, 0.119054, 0.119177, 0.119028, 0.119066", \ - "0.189762, 0.190527, 0.190584, 0.190448, 0.190224, 0.189958, 0.189908" \ + "0.0515714, 0.0522411, 0.05229, 0.0521965, 0.0521134, 0.0517539, 0.050913", \ + "0.0540768, 0.054765, 0.05469, 0.0547768, 0.0545892, 0.0551222, 0.0537378", \ + "0.0576004, 0.0583256, 0.0584124, 0.05835, 0.0580233, 0.0583898, 0.0569372", \ + "0.0659246, 0.066645, 0.0667973, 0.0668454, 0.0667483, 0.066487, 0.066175", \ + "0.0833505, 0.0840156, 0.0841446, 0.08404, 0.0841956, 0.0841041, 0.0839127", \ + "0.118496, 0.119302, 0.119215, 0.119061, 0.119181, 0.119076, 0.119163", \ + "0.189851, 0.190561, 0.190444, 0.190494, 0.190269, 0.189986, 0.189972" \ ); } } @@ -10273,13 +10291,13 @@ library (sg13g2_stdcell_fast_1p65V_m40C) { index_1 ("0.0186, 0.0966, 0.174, 0.3294, 0.6408, 1.263, 2.5074"); index_2 ("0.001, 0.0234, 0.039, 0.0648, 0.108, 0.18, 0.3"); values ( \ - "0.000521298, 0.0011785, 0.0011586, 0.0010631, 0.000923898, 0.0005816, -7.26022e-05", \ - "0.000465598, 0.001069, 0.0010826, 0.0012119, 0.0008495, 0.0010043, -9.69023e-05", \ - "0.0004743, 0.0011731, 0.0012411, 0.0010741, 0.0011405, 0.000604801, 0.0012315", \ - "0.000406601, 0.0010677, 0.0012173, 0.0012417, 0.000990495, 0.000700898, 0.0012134", \ - "7.84993e-05, 0.000696704, 0.000688903, 0.0008187, 0.000840604, 0.000782602, -0.000192396", \ - "-0.000178002, 0.000392996, 0.000409, 0.000550002, 0.000354998, 0.000464998, 0.000424996", \ - "-0.000964999, -0.000392005, -0.000420004, -0.000490993, -0.000661999, -0.000442997, -0.000689" \ + "0.0004436, 0.0011458, 0.0011839, 0.0010296, 0.000877403, 0.000553302, -0.000100199", \ + "0.000450499, 0.0010876, 0.0011043, 0.001234, 0.000949398, 0.0010297, -9.42014e-05", \ + "0.000462599, 0.0011792, 0.0012638, 0.0011136, 0.0011518, 0.000617698, 0.0012467", \ + "0.000408597, 0.0010736, 0.001219, 0.0012494, 0.001178, 0.000665501, 0.0012341", \ + "7.99e-05, 0.000702098, 0.000709698, 0.000847794, 0.000895798, 0.000797495, -7.89016e-05", \ + "-0.000180997, 0.000375003, 0.000411004, 0.000528, 0.000391997, 0.000430003, 0.000459999", \ + "-0.000946999, -0.000387996, -0.000403002, -0.000471994, -0.000643998, -0.000429004, -0.000670001" \ ); } } @@ -10288,11 +10306,11 @@ library (sg13g2_stdcell_fast_1p65V_m40C) { clock : true; direction : "input"; max_transition : 2.5074; - capacitance : 0.00316207; - rise_capacitance : 0.00338205; - rise_capacitance_range (0.00338205, 0.00338205); - fall_capacitance : 0.00290543; - fall_capacitance_range (0.00290543, 0.00290543); + capacitance : 0.00316202; + rise_capacitance : 0.00338192; + rise_capacitance_range (0.00296527, 0.00373719); + fall_capacitance : 0.00290547; + fall_capacitance_range (0.00290547, 0.00351773); timing () { related_pin : "CLK"; timing_type : min_pulse_width; @@ -10314,13 +10332,13 @@ library (sg13g2_stdcell_fast_1p65V_m40C) { rise_power (passive_POWER_7x1ds1) { index_1 ("0.0186, 0.0966, 0.174, 0.3294, 0.6408, 1.263, 2.5074"); values ( \ - "0.0183245, 0.0204983, 0.0238475, 0.031825, 0.0485181, 0.0831425, 0.155142" \ + "0.0183241, 0.0204989, 0.0238509, 0.0318314, 0.0486445, 0.0831528, 0.155086" \ ); } fall_power (passive_POWER_7x1ds1) { index_1 ("0.0186, 0.0966, 0.174, 0.3294, 0.6408, 1.263, 2.5074"); values ( \ - "0.0422599, 0.0447169, 0.0483368, 0.0564882, 0.0736178, 0.108361, 0.180587" \ + "0.042276, 0.0447041, 0.0483388, 0.0564888, 0.0736198, 0.108366, 0.180604" \ ); } } @@ -10334,7 +10352,7 @@ library (sg13g2_stdcell_fast_1p65V_m40C) { fall_power (passive_POWER_7x1ds1) { index_1 ("0.0186, 0.0966, 0.174, 0.3294, 0.6408, 1.263, 2.5074"); values ( \ - "0.0397591, 0.0422038, 0.0458413, 0.0539761, 0.0710957, 0.105864, 0.178104" \ + "0.0397556, 0.0422197, 0.0458433, 0.0539759, 0.0710977, 0.105821, 0.178095" \ ); } } @@ -10343,13 +10361,13 @@ library (sg13g2_stdcell_fast_1p65V_m40C) { rise_power (passive_POWER_7x1ds1) { index_1 ("0.0186, 0.0966, 0.174, 0.3294, 0.6408, 1.263, 2.5074"); values ( \ - "0.0193553, 0.0214843, 0.0248515, 0.0327791, 0.0494646, 0.0840563, 0.155894" \ + "0.019349, 0.0214837, 0.0248884, 0.0327834, 0.0494684, 0.0840687, 0.156032" \ ); } fall_power (passive_POWER_7x1ds1) { index_1 ("0.0186, 0.0966, 0.174, 0.3294, 0.6408, 1.263, 2.5074"); values ( \ - "0.0199015, 0.0224003, 0.025935, 0.0336142, 0.0501783, 0.083634, 0.153135" \ + "0.0199089, 0.0224017, 0.0259378, 0.0336161, 0.0501825, 0.0836408, 0.153147" \ ); } } @@ -10363,7 +10381,7 @@ library (sg13g2_stdcell_fast_1p65V_m40C) { fall_power (passive_POWER_7x1ds1) { index_1 ("0.0186, 0.0966, 0.174, 0.3294, 0.6408, 1.263, 2.5074"); values ( \ - "0.0728721, 0.0746763, 0.0779986, 0.0857705, 0.102212, 0.136023, 0.20454" \ + "0.0728804, 0.0746814, 0.0780037, 0.0859138, 0.102215, 0.136033, 0.204402" \ ); } } @@ -10372,13 +10390,13 @@ library (sg13g2_stdcell_fast_1p65V_m40C) { rise_power (passive_POWER_7x1ds1) { index_1 ("0.0186, 0.0966, 0.174, 0.3294, 0.6408, 1.263, 2.5074"); values ( \ - "0.0178957, 0.0200552, 0.02343, 0.031374, 0.0481278, 0.0826373, 0.15463" \ + "0.0178899, 0.0200525, 0.0234422, 0.0313945, 0.0481339, 0.0826479, 0.154649" \ ); } fall_power (passive_POWER_7x1ds1) { index_1 ("0.0186, 0.0966, 0.174, 0.3294, 0.6408, 1.263, 2.5074"); values ( \ - "0.0198745, 0.0223759, 0.025917, 0.0336389, 0.0501853, 0.0836468, 0.153222" \ + "0.0198789, 0.0223779, 0.0259187, 0.033642, 0.0501885, 0.0836509, 0.153233" \ ); } } @@ -10387,13 +10405,13 @@ library (sg13g2_stdcell_fast_1p65V_m40C) { rise_power (passive_POWER_7x1ds1) { index_1 ("0.0186, 0.0966, 0.174, 0.3294, 0.6408, 1.263, 2.5074"); values ( \ - "0.0193977, 0.0215215, 0.0248774, 0.0328078, 0.0495286, 0.0840433, 0.155998" \ + "0.0194037, 0.0215243, 0.0249303, 0.0328146, 0.0494959, 0.0840552, 0.156013" \ ); } fall_power (passive_POWER_7x1ds1) { index_1 ("0.0186, 0.0966, 0.174, 0.3294, 0.6408, 1.263, 2.5074"); values ( \ - "0.0199036, 0.0223895, 0.0259249, 0.0336065, 0.0501664, 0.0836209, 0.153126" \ + "0.0199094, 0.0223951, 0.0259291, 0.0336089, 0.0501712, 0.083627, 0.153135" \ ); } } @@ -10401,13 +10419,13 @@ library (sg13g2_stdcell_fast_1p65V_m40C) { rise_power (passive_POWER_7x1ds1) { index_1 ("0.0186, 0.0966, 0.174, 0.3294, 0.6408, 1.263, 2.5074"); values ( \ - "0.0183245, 0.0204983, 0.0238475, 0.031825, 0.0485181, 0.0831425, 0.155142" \ + "0.0183241, 0.0204989, 0.0238509, 0.0318314, 0.0486445, 0.0831528, 0.155086" \ ); } fall_power (passive_POWER_7x1ds1) { index_1 ("0.0186, 0.0966, 0.174, 0.3294, 0.6408, 1.263, 2.5074"); values ( \ - "0.0397591, 0.0422038, 0.0458413, 0.0539761, 0.0710957, 0.105864, 0.178104" \ + "0.0397556, 0.0422197, 0.0458433, 0.0539759, 0.0710977, 0.105821, 0.178095" \ ); } } @@ -10416,13 +10434,14 @@ library (sg13g2_stdcell_fast_1p65V_m40C) { direction : "input"; nextstate_type : "data"; max_transition : 2.5074; - capacitance : 0.0015646; - rise_capacitance : 0.00154918; - rise_capacitance_range (0.00154918, 0.00154918); + capacitance : 0.00156464; + rise_capacitance : 0.00154926; + rise_capacitance_range (0.00146318, 0.00190098); fall_capacitance : 0.00158003; - fall_capacitance_range (0.00158003, 0.00158003); + fall_capacitance_range (0.00158003, 0.00189441); timing () { related_pin : "CLK"; + sdf_edges : both_edges; timing_type : hold_rising; rise_constraint (CONSTRAINT_4x4) { index_1 ("0.0186, 0.51636, 1.263, 2.5074"); @@ -10439,7 +10458,7 @@ library (sg13g2_stdcell_fast_1p65V_m40C) { index_2 ("0.0186, 0.51636, 1.263, 2.5074"); values ( \ "-0.0195615, 0.0272076, 0.0575781, 0.0855195", \ - "-0.104578, -0.066208, -0.0331243, -0.00490029", \ + "-0.104578, -0.0636615, -0.0331243, -0.00490029", \ "-0.160449, -0.132088, -0.105236, -0.0806326", \ "-0.223136, -0.206773, -0.184913, -0.165286" \ ); @@ -10447,12 +10466,13 @@ library (sg13g2_stdcell_fast_1p65V_m40C) { } timing () { related_pin : "CLK"; + sdf_edges : both_edges; timing_type : setup_rising; rise_constraint (CONSTRAINT_4x4) { index_1 ("0.0186, 0.51636, 1.263, 2.5074"); index_2 ("0.0186, 0.51636, 1.263, 2.5074"); values ( \ - "0.0489038, 0.0252047, 0.0144316, 0.0116216", \ + "0.0489038, 0.0252047, 0.0144316, 0.0089232", \ "0.127041, 0.094219, 0.0803277, 0.0791233", \ "0.178452, 0.142577, 0.129521, 0.131482", \ "0.217739, 0.179283, 0.170788, 0.174141" \ @@ -10474,13 +10494,13 @@ library (sg13g2_stdcell_fast_1p65V_m40C) { rise_power (passive_POWER_7x1ds1) { index_1 ("0.0186, 0.0966, 0.174, 0.3294, 0.6408, 1.263, 2.5074"); values ( \ - "0.00151089, 0.00241094, 0.0037698, 0.00668437, 0.0128817, 0.0254498, 0.0515061" \ + "0.00150615, 0.00241088, 0.00376985, 0.00668594, 0.0128808, 0.025449, 0.051545" \ ); } fall_power (passive_POWER_7x1ds1) { index_1 ("0.0186, 0.0966, 0.174, 0.3294, 0.6408, 1.263, 2.5074"); values ( \ - "0.0018981, 0.00292475, 0.00429855, 0.0072743, 0.0135342, 0.0260649, 0.0519345" \ + "0.00189781, 0.00292534, 0.00429907, 0.00727491, 0.0135336, 0.0260632, 0.0519308" \ ); } } @@ -10489,13 +10509,13 @@ library (sg13g2_stdcell_fast_1p65V_m40C) { rise_power (passive_POWER_7x1ds1) { index_1 ("0.0186, 0.0966, 0.174, 0.3294, 0.6408, 1.263, 2.5074"); values ( \ - "0.0220814, 0.0230489, 0.0244502, 0.0278221, 0.0352642, 0.0508388, 0.082301" \ + "0.0220606, 0.0230423, 0.0244473, 0.0278376, 0.0352592, 0.050833, 0.0822837" \ ); } fall_power (passive_POWER_7x1ds1) { index_1 ("0.0186, 0.0966, 0.174, 0.3294, 0.6408, 1.263, 2.5074"); values ( \ - "0.0177325, 0.0187665, 0.0204112, 0.0237996, 0.031339, 0.0463828, 0.0776788" \ + "0.0177819, 0.0187532, 0.0204114, 0.0237985, 0.0313376, 0.0463802, 0.0776741" \ ); } } @@ -10504,13 +10524,13 @@ library (sg13g2_stdcell_fast_1p65V_m40C) { rise_power (passive_POWER_7x1ds1) { index_1 ("0.0186, 0.0966, 0.174, 0.3294, 0.6408, 1.263, 2.5074"); values ( \ - "-0.000118215, -0.000112168, -0.000109786, -0.000110846, -0.000108794, -0.000108516, -0.000110345" \ + "-0.000116865, -0.000111497, -0.0001093, -0.000109694, -0.000108778, -0.0001105, -0.000110695" \ ); } fall_power (passive_POWER_7x1ds1) { index_1 ("0.0186, 0.0966, 0.174, 0.3294, 0.6408, 1.263, 2.5074"); values ( \ - "0.000360821, 0.000362249, 0.000359015, 0.000362218, 0.0003628, 0.000363277, 0.000362002" \ + "0.000360696, 0.000362526, 0.000358811, 0.000362211, 0.000362859, 0.000363681, 0.000362073" \ ); } } @@ -10518,13 +10538,13 @@ library (sg13g2_stdcell_fast_1p65V_m40C) { rise_power (passive_POWER_7x1ds1) { index_1 ("0.0186, 0.0966, 0.174, 0.3294, 0.6408, 1.263, 2.5074"); values ( \ - "0.00151089, 0.00241094, 0.0037698, 0.00668437, 0.0128817, 0.0254498, 0.0515061" \ + "0.00150615, 0.00241088, 0.00376985, 0.00668594, 0.0128808, 0.025449, 0.051545" \ ); } fall_power (passive_POWER_7x1ds1) { index_1 ("0.0186, 0.0966, 0.174, 0.3294, 0.6408, 1.263, 2.5074"); values ( \ - "0.0018981, 0.00292475, 0.00429855, 0.0072743, 0.0135342, 0.0260649, 0.0519345" \ + "0.00189781, 0.00292534, 0.00429907, 0.00727491, 0.0135336, 0.0260632, 0.0519308" \ ); } } @@ -10532,13 +10552,14 @@ library (sg13g2_stdcell_fast_1p65V_m40C) { pin (RESET_B) { direction : "input"; max_transition : 2.5074; - capacitance : 0.00566664; - rise_capacitance : 0.00584272; - rise_capacitance_range (0.00584272, 0.00584272); - fall_capacitance : 0.00551991; - fall_capacitance_range (0.00551991, 0.00551991); + capacitance : 0.00566709; + rise_capacitance : 0.00584307; + rise_capacitance_range (0.00481018, 0.00659639); + fall_capacitance : 0.00552044; + fall_capacitance_range (0.00507741, 0.00585675); timing () { related_pin : "CLK"; + sdf_edges : both_edges; timing_type : recovery_rising; rise_constraint (CONSTRAINT_4x4) { index_1 ("0.0186, 0.51636, 1.263, 2.5074"); @@ -10553,6 +10574,7 @@ library (sg13g2_stdcell_fast_1p65V_m40C) { } timing () { related_pin : "CLK"; + sdf_edges : both_edges; timing_type : removal_rising; rise_constraint (CONSTRAINT_4x4) { index_1 ("0.0186, 0.51636, 1.263, 2.5074"); @@ -10580,13 +10602,13 @@ library (sg13g2_stdcell_fast_1p65V_m40C) { rise_power (passive_POWER_7x1ds1) { index_1 ("0.0186, 0.0966, 0.174, 0.3294, 0.6408, 1.263, 2.5074"); values ( \ - "0.00298036, 0.00339735, 0.00450739, 0.0073048, 0.0134984, 0.0261874, 0.0520433" \ + "0.00298091, 0.0033961, 0.0045098, 0.00730023, 0.0134965, 0.0261867, 0.0520416" \ ); } fall_power (passive_POWER_7x1ds1) { index_1 ("0.0186, 0.0966, 0.174, 0.3294, 0.6408, 1.263, 2.5074"); values ( \ - "0.0502001, 0.052255, 0.0561045, 0.0650921, 0.0835564, 0.118551, 0.18547" \ + "0.0502451, 0.0522409, 0.056104, 0.0650898, 0.0835527, 0.118552, 0.185462" \ ); } } @@ -10610,13 +10632,13 @@ library (sg13g2_stdcell_fast_1p65V_m40C) { rise_power (passive_POWER_7x1ds1) { index_1 ("0.0186, 0.0966, 0.174, 0.3294, 0.6408, 1.263, 2.5074"); values ( \ - "0.02376, 0.0242949, 0.0258018, 0.0301717, 0.0398735, 0.0600826, 0.10182" \ + "0.0237006, 0.0242943, 0.0257978, 0.0301671, 0.0398682, 0.0600687, 0.101807" \ ); } fall_power (passive_POWER_7x1ds1) { index_1 ("0.0186, 0.0966, 0.174, 0.3294, 0.6408, 1.263, 2.5074"); values ( \ - "0.0165277, 0.0170592, 0.0186483, 0.0231022, 0.0329379, 0.0536023, 0.0954308" \ + "0.0165292, 0.0170596, 0.0186458, 0.023102, 0.0329384, 0.0536015, 0.095427" \ ); } } @@ -10639,19 +10661,19 @@ library (sg13g2_stdcell_fast_1p65V_m40C) { rise_power (passive_POWER_7x1ds1) { index_1 ("0.0186, 0.0966, 0.174, 0.3294, 0.6408, 1.263, 2.5074"); values ( \ - "0.02376, 0.0242949, 0.0258018, 0.0301717, 0.0398735, 0.0600826, 0.10182" \ + "0.0237006, 0.0242943, 0.0257978, 0.0301671, 0.0398682, 0.0600687, 0.101807" \ ); } fall_power (passive_POWER_7x1ds1) { index_1 ("0.0186, 0.0966, 0.174, 0.3294, 0.6408, 1.263, 2.5074"); values ( \ - "0.0502001, 0.052255, 0.0561045, 0.0650921, 0.0835564, 0.118551, 0.18547" \ + "0.0502451, 0.0522409, 0.056104, 0.0650898, 0.0835527, 0.118552, 0.185462" \ ); } } } ff (IQ,IQN) { - clear : "RESET_B'"; + clear : "!RESET_B"; clocked_on : "CLK"; next_state : "D"; } @@ -10715,13 +10737,14 @@ library (sg13g2_stdcell_fast_1p65V_m40C) { max_capacitance : 0.6; timing () { related_pin : "CLK"; + sdf_edges : start_edge; timing_sense : non_unate; timing_type : rising_edge; cell_rise (TIMING_DELAY_7x7ds1) { index_1 ("0.0186, 0.0966, 0.174, 0.3294, 0.6408, 1.263, 2.5074"); index_2 ("0.001, 0.0468, 0.078, 0.1296, 0.216, 0.36, 0.6"); values ( \ - "0.0809639, 0.115595, 0.136317, 0.17018, 0.226827, 0.3212, 0.478404", \ + "0.0809639, 0.115597, 0.136318, 0.17018, 0.226827, 0.3212, 0.478321", \ "0.0999024, 0.134517, 0.155194, 0.189096, 0.245726, 0.340082, 0.497252", \ "0.112317, 0.146962, 0.167616, 0.201535, 0.258164, 0.352486, 0.509645", \ "0.130519, 0.165172, 0.185824, 0.219771, 0.276397, 0.3707, 0.527812", \ @@ -10734,12 +10757,12 @@ library (sg13g2_stdcell_fast_1p65V_m40C) { index_1 ("0.0186, 0.0966, 0.174, 0.3294, 0.6408, 1.263, 2.5074"); index_2 ("0.001, 0.0468, 0.078, 0.1296, 0.216, 0.36, 0.6"); values ( \ - "0.0096959, 0.0517029, 0.0818631, 0.132395, 0.217453, 0.359389, 0.595901", \ - "0.0097269, 0.0517039, 0.0818641, 0.132396, 0.217454, 0.362189, 0.595902", \ - "0.0097714, 0.0517049, 0.0818651, 0.132411, 0.217455, 0.36219, 0.595903", \ - "0.0098941, 0.0517059, 0.0818661, 0.132422, 0.217456, 0.362191, 0.595904", \ - "0.0101331, 0.0517069, 0.0818671, 0.132423, 0.217462, 0.362192, 0.59603", \ - "0.010565, 0.0517079, 0.0818681, 0.132424, 0.217482, 0.362193, 0.596031", \ + "0.0096959, 0.0515001, 0.0818628, 0.132395, 0.217453, 0.359389, 0.595905", \ + "0.0097269, 0.0515011, 0.0818638, 0.132396, 0.217454, 0.362189, 0.595906", \ + "0.0097714, 0.0515021, 0.0818648, 0.132411, 0.217455, 0.36219, 0.595907", \ + "0.0098941, 0.0515031, 0.0818658, 0.132422, 0.217456, 0.362191, 0.595908", \ + "0.0101331, 0.0515419, 0.0818668, 0.132423, 0.217462, 0.362192, 0.59603", \ + "0.010565, 0.051668, 0.0818678, 0.132424, 0.217482, 0.362193, 0.596031", \ "0.01148, 0.051929, 0.081941, 0.132476, 0.217483, 0.362194, 0.596032" \ ); } @@ -10747,7 +10770,7 @@ library (sg13g2_stdcell_fast_1p65V_m40C) { index_1 ("0.0186, 0.0966, 0.174, 0.3294, 0.6408, 1.263, 2.5074"); index_2 ("0.001, 0.0468, 0.078, 0.1296, 0.216, 0.36, 0.6"); values ( \ - "0.0812522, 0.112718, 0.130504, 0.15951, 0.207839, 0.288412, 0.4224", \ + "0.0812519, 0.112714, 0.13049, 0.15951, 0.207839, 0.288413, 0.4224", \ "0.0997387, 0.131162, 0.148978, 0.177953, 0.226284, 0.306779, 0.440944", \ "0.11148, 0.142939, 0.160733, 0.189715, 0.238111, 0.318524, 0.452536", \ "0.128281, 0.159769, 0.177536, 0.206535, 0.254848, 0.335323, 0.469351", \ @@ -10760,8 +10783,8 @@ library (sg13g2_stdcell_fast_1p65V_m40C) { index_1 ("0.0186, 0.0966, 0.174, 0.3294, 0.6408, 1.263, 2.5074"); index_2 ("0.001, 0.0468, 0.078, 0.1296, 0.216, 0.36, 0.6"); values ( \ - "0.00887, 0.0425763, 0.0664744, 0.106729, 0.174604, 0.288083, 0.476999", \ - "0.008871, 0.0425928, 0.0664806, 0.10673, 0.174639, 0.288084, 0.477116", \ + "0.0088704, 0.0425804, 0.0664633, 0.106729, 0.174604, 0.288083, 0.476999", \ + "0.0088714, 0.0425928, 0.0664806, 0.10673, 0.174639, 0.288084, 0.477116", \ "0.0088717, 0.0425938, 0.0664816, 0.106731, 0.17464, 0.288085, 0.477117", \ "0.0088727, 0.0426086, 0.0664826, 0.106732, 0.174641, 0.288086, 0.477118", \ "0.0088737, 0.0426156, 0.0664836, 0.106733, 0.174642, 0.288087, 0.477119", \ @@ -10772,6 +10795,7 @@ library (sg13g2_stdcell_fast_1p65V_m40C) { } timing () { related_pin : "RESET_B"; + sdf_edges : start_edge; timing_sense : positive_unate; timing_type : clear; cell_fall (TIMING_DELAY_7x7ds1) { @@ -10791,8 +10815,8 @@ library (sg13g2_stdcell_fast_1p65V_m40C) { index_1 ("0.0186, 0.0966, 0.174, 0.3294, 0.6408, 1.263, 2.5074"); index_2 ("0.001, 0.0468, 0.078, 0.1296, 0.216, 0.36, 0.6"); values ( \ - "0.0087684, 0.0425754, 0.066492, 0.10676, 0.174598, 0.288077, 0.476986", \ - "0.0087694, 0.0425764, 0.066493, 0.106761, 0.174599, 0.288078, 0.477485", \ + "0.0087685, 0.0425754, 0.066492, 0.10676, 0.174598, 0.288077, 0.476986", \ + "0.0087695, 0.0425764, 0.066493, 0.106761, 0.174599, 0.288078, 0.477485", \ "0.0088151, 0.0425774, 0.066494, 0.106762, 0.1746, 0.288079, 0.477486", \ "0.0088548, 0.0425784, 0.066495, 0.106763, 0.174624, 0.28808, 0.477487", \ "0.0089303, 0.0425996, 0.066496, 0.106764, 0.174625, 0.288081, 0.477488", \ @@ -10807,11 +10831,11 @@ library (sg13g2_stdcell_fast_1p65V_m40C) { index_1 ("0.0186, 0.0966, 0.174, 0.3294, 0.6408, 1.263, 2.5074"); index_2 ("0.001, 0.0468, 0.078, 0.1296, 0.216, 0.36, 0.6"); values ( \ - "0.0575066, 0.0579605, 0.0579092, 0.0577451, 0.0573989, 0.056578, 0.05523", \ + "0.0575067, 0.0577881, 0.0579018, 0.0577453, 0.0573989, 0.0565746, 0.055334", \ "0.0596791, 0.0598812, 0.0599888, 0.0603126, 0.0598688, 0.0604005, 0.0573692", \ "0.0631521, 0.0635069, 0.0636481, 0.06331, 0.063503, 0.0623347, 0.0628157", \ "0.0717863, 0.0720155, 0.0722654, 0.0724663, 0.0722527, 0.0712997, 0.0715794", \ - "0.0896811, 0.0896957, 0.0899127, 0.0900848, 0.0902351, 0.0898905, 0.0879483", \ + "0.0896811, 0.0896957, 0.0899124, 0.0900848, 0.0902351, 0.0898905, 0.0879483", \ "0.12686, 0.126633, 0.126584, 0.126835, 0.126573, 0.127016, 0.126876", \ "0.202694, 0.201679, 0.201918, 0.20184, 0.201258, 0.201584, 0.201211" \ ); @@ -10820,9 +10844,9 @@ library (sg13g2_stdcell_fast_1p65V_m40C) { index_1 ("0.0186, 0.0966, 0.174, 0.3294, 0.6408, 1.263, 2.5074"); index_2 ("0.001, 0.0468, 0.078, 0.1296, 0.216, 0.36, 0.6"); values ( \ - "0.0589005, 0.0595175, 0.0596327, 0.05956, 0.0591653, 0.0585464, 0.0571443", \ + "0.0589017, 0.0595077, 0.059629, 0.05956, 0.0591659, 0.0585466, 0.0571443", \ "0.0614022, 0.0620679, 0.0620136, 0.0622856, 0.0618243, 0.0619094, 0.059663", \ - "0.0649163, 0.0656797, 0.0658967, 0.065576, 0.0652859, 0.0661014, 0.0635122", \ + "0.0649163, 0.0656797, 0.0658966, 0.065576, 0.0652859, 0.0661014, 0.0635122", \ "0.0732371, 0.0739144, 0.074224, 0.0744596, 0.0743478, 0.073269, 0.0731301", \ "0.0905951, 0.0912157, 0.0915614, 0.0914032, 0.0917116, 0.0917525, 0.0909297", \ "0.125592, 0.126483, 0.126468, 0.126382, 0.12663, 0.126514, 0.126628", \ @@ -10841,7 +10865,7 @@ library (sg13g2_stdcell_fast_1p65V_m40C) { index_1 ("0.0186, 0.0966, 0.174, 0.3294, 0.6408, 1.263, 2.5074"); index_2 ("0.001, 0.0468, 0.078, 0.1296, 0.216, 0.36, 0.6"); values ( \ - "0.000178501, 0.000544399, 0.0006225, 0.0006027, 0.000125401, -0.000427801, -0.0018642", \ + "0.000186, 0.000552401, 0.000629999, 0.000610098, 0.0001329, -0.000420302, -0.0018567", \ "0.000179, 0.000645302, 0.000727501, 0.0010498, 0.000531502, -0.000247899, -0.001249", \ "0.000220202, 0.000812605, 0.000947602, 0.0006859, 0.0008296, -0.0002895, 0.0006442", \ "0.000115596, 0.000551499, 0.000898093, 0.000946797, 0.000696197, -0.000147201, -0.0001458", \ @@ -10858,9 +10882,9 @@ library (sg13g2_stdcell_fast_1p65V_m40C) { max_transition : 2.5074; capacitance : 0.0031699; rise_capacitance : 0.00339035; - rise_capacitance_range (0.00339035, 0.00339035); + rise_capacitance_range (0.00297294, 0.003746); fall_capacitance : 0.00291271; - fall_capacitance_range (0.00291271, 0.00291271); + fall_capacitance_range (0.00291271, 0.00352645); timing () { related_pin : "CLK"; timing_type : min_pulse_width; @@ -10882,7 +10906,7 @@ library (sg13g2_stdcell_fast_1p65V_m40C) { rise_power (passive_POWER_7x1ds1) { index_1 ("0.0186, 0.0966, 0.174, 0.3294, 0.6408, 1.263, 2.5074"); values ( \ - "0.0184407, 0.020586, 0.0239903, 0.0319359, 0.0486296, 0.0832308, 0.155592" \ + "0.0184272, 0.020586, 0.0239903, 0.0319359, 0.0486296, 0.0832308, 0.155592" \ ); } fall_power (passive_POWER_7x1ds1) { @@ -10911,13 +10935,13 @@ library (sg13g2_stdcell_fast_1p65V_m40C) { rise_power (passive_POWER_7x1ds1) { index_1 ("0.0186, 0.0966, 0.174, 0.3294, 0.6408, 1.263, 2.5074"); values ( \ - "0.0194819, 0.0216508, 0.0249486, 0.0328924, 0.0495984, 0.0840974, 0.156288" \ + "0.01949, 0.0216508, 0.0249486, 0.0328924, 0.0495984, 0.0840974, 0.156288" \ ); } fall_power (passive_POWER_7x1ds1) { index_1 ("0.0186, 0.0966, 0.174, 0.3294, 0.6408, 1.263, 2.5074"); values ( \ - "0.0199606, 0.0224338, 0.0259876, 0.0336723, 0.0502281, 0.083686, 0.153169" \ + "0.0199606, 0.0224338, 0.0259876, 0.0336722, 0.050228, 0.083686, 0.153169" \ ); } } @@ -10940,13 +10964,13 @@ library (sg13g2_stdcell_fast_1p65V_m40C) { rise_power (passive_POWER_7x1ds1) { index_1 ("0.0186, 0.0966, 0.174, 0.3294, 0.6408, 1.263, 2.5074"); values ( \ - "0.0180233, 0.0201636, 0.0235098, 0.0315175, 0.0482342, 0.0827425, 0.155101" \ + "0.0180214, 0.0201637, 0.0235098, 0.0315175, 0.0482342, 0.0827425, 0.155101" \ ); } fall_power (passive_POWER_7x1ds1) { index_1 ("0.0186, 0.0966, 0.174, 0.3294, 0.6408, 1.263, 2.5074"); values ( \ - "0.0199425, 0.022409, 0.0259643, 0.0336971, 0.0502304, 0.0836838, 0.153256" \ + "0.0199424, 0.022409, 0.0259642, 0.033697, 0.0502304, 0.0836838, 0.153256" \ ); } } @@ -10955,13 +10979,13 @@ library (sg13g2_stdcell_fast_1p65V_m40C) { rise_power (passive_POWER_7x1ds1) { index_1 ("0.0186, 0.0966, 0.174, 0.3294, 0.6408, 1.263, 2.5074"); values ( \ - "0.0195417, 0.0216544, 0.0249898, 0.0329253, 0.0496267, 0.084187, 0.156319" \ + "0.0195229, 0.0216544, 0.0249898, 0.0329253, 0.0496267, 0.084187, 0.156319" \ ); } fall_power (passive_POWER_7x1ds1) { index_1 ("0.0186, 0.0966, 0.174, 0.3294, 0.6408, 1.263, 2.5074"); values ( \ - "0.0199613, 0.0224296, 0.0259794, 0.0336641, 0.0502167, 0.0836789, 0.153158" \ + "0.0199613, 0.0224296, 0.0259794, 0.033664, 0.0502167, 0.0836789, 0.153158" \ ); } } @@ -10969,7 +10993,7 @@ library (sg13g2_stdcell_fast_1p65V_m40C) { rise_power (passive_POWER_7x1ds1) { index_1 ("0.0186, 0.0966, 0.174, 0.3294, 0.6408, 1.263, 2.5074"); values ( \ - "0.0184407, 0.020586, 0.0239903, 0.0319359, 0.0486296, 0.0832308, 0.155592" \ + "0.0184272, 0.020586, 0.0239903, 0.0319359, 0.0486296, 0.0832308, 0.155592" \ ); } fall_power (passive_POWER_7x1ds1) { @@ -10986,11 +11010,12 @@ library (sg13g2_stdcell_fast_1p65V_m40C) { max_transition : 2.5074; capacitance : 0.00156839; rise_capacitance : 0.00155282; - rise_capacitance_range (0.00155282, 0.00155282); + rise_capacitance_range (0.00146727, 0.00190428); fall_capacitance : 0.00158395; - fall_capacitance_range (0.00158395, 0.00158395); + fall_capacitance_range (0.00158395, 0.00189662); timing () { related_pin : "CLK"; + sdf_edges : both_edges; timing_type : hold_rising; rise_constraint (CONSTRAINT_4x4) { index_1 ("0.0186, 0.51636, 1.263, 2.5074"); @@ -11015,6 +11040,7 @@ library (sg13g2_stdcell_fast_1p65V_m40C) { } timing () { related_pin : "CLK"; + sdf_edges : both_edges; timing_type : setup_rising; rise_constraint (CONSTRAINT_4x4) { index_1 ("0.0186, 0.51636, 1.263, 2.5074"); @@ -11033,7 +11059,7 @@ library (sg13g2_stdcell_fast_1p65V_m40C) { "0.0440134, -0.00474515, -0.0370039, -0.0612343", \ "0.142016, 0.094219, 0.0619709, 0.0351393", \ "0.209313, 0.166179, 0.134918, 0.111707", \ - "0.290595, 0.250757, 0.221637, 0.200705" \ + "0.290595, 0.250757, 0.221637, 0.197753" \ ); } } @@ -11042,13 +11068,13 @@ library (sg13g2_stdcell_fast_1p65V_m40C) { rise_power (passive_POWER_7x1ds1) { index_1 ("0.0186, 0.0966, 0.174, 0.3294, 0.6408, 1.263, 2.5074"); values ( \ - "0.00151918, 0.0024129, 0.00377421, 0.0066879, 0.0128815, 0.0254502, 0.0515289" \ + "0.00151935, 0.0024129, 0.00377421, 0.00668789, 0.0128815, 0.0254502, 0.0515289" \ ); } fall_power (passive_POWER_7x1ds1) { index_1 ("0.0186, 0.0966, 0.174, 0.3294, 0.6408, 1.263, 2.5074"); values ( \ - "0.00191305, 0.00294035, 0.00431612, 0.00728248, 0.0135435, 0.0260723, 0.0519342" \ + "0.00191306, 0.00294037, 0.00431612, 0.00728249, 0.0135435, 0.0260723, 0.0519342" \ ); } } @@ -11057,13 +11083,13 @@ library (sg13g2_stdcell_fast_1p65V_m40C) { rise_power (passive_POWER_7x1ds1) { index_1 ("0.0186, 0.0966, 0.174, 0.3294, 0.6408, 1.263, 2.5074"); values ( \ - "0.0220222, 0.0229934, 0.0244135, 0.0277802, 0.0352269, 0.050801, 0.0822464" \ + "0.0220216, 0.0229934, 0.0244135, 0.0277802, 0.0352271, 0.050801, 0.0822464" \ ); } fall_power (passive_POWER_7x1ds1) { index_1 ("0.0186, 0.0966, 0.174, 0.3294, 0.6408, 1.263, 2.5074"); values ( \ - "0.0178147, 0.0187907, 0.0204309, 0.0238379, 0.0313731, 0.046431, 0.0777259" \ + "0.0177769, 0.0187906, 0.0204309, 0.0238379, 0.0313731, 0.046431, 0.0777259" \ ); } } @@ -11072,13 +11098,13 @@ library (sg13g2_stdcell_fast_1p65V_m40C) { rise_power (passive_POWER_7x1ds1) { index_1 ("0.0186, 0.0966, 0.174, 0.3294, 0.6408, 1.263, 2.5074"); values ( \ - "-0.000111699, -0.000104505, -0.000105794, -0.000104512, -0.000104749, -0.00010419, -0.000106994" \ + "-0.000111375, -0.000104524, -0.000105814, -0.000104532, -0.000104768, -0.000104209, -0.000107005" \ ); } fall_power (passive_POWER_7x1ds1) { index_1 ("0.0186, 0.0966, 0.174, 0.3294, 0.6408, 1.263, 2.5074"); values ( \ - "0.000355516, 0.000357061, 0.000353846, 0.000356954, 0.000356933, 0.000358316, 0.000356937" \ + "0.000355468, 0.000357055, 0.00035384, 0.000356948, 0.000356918, 0.000358302, 0.000356923" \ ); } } @@ -11086,13 +11112,13 @@ library (sg13g2_stdcell_fast_1p65V_m40C) { rise_power (passive_POWER_7x1ds1) { index_1 ("0.0186, 0.0966, 0.174, 0.3294, 0.6408, 1.263, 2.5074"); values ( \ - "0.00151918, 0.0024129, 0.00377421, 0.0066879, 0.0128815, 0.0254502, 0.0515289" \ + "0.00151935, 0.0024129, 0.00377421, 0.00668789, 0.0128815, 0.0254502, 0.0515289" \ ); } fall_power (passive_POWER_7x1ds1) { index_1 ("0.0186, 0.0966, 0.174, 0.3294, 0.6408, 1.263, 2.5074"); values ( \ - "0.00191305, 0.00294035, 0.00431612, 0.00728248, 0.0135435, 0.0260723, 0.0519342" \ + "0.00191306, 0.00294037, 0.00431612, 0.00728249, 0.0135435, 0.0260723, 0.0519342" \ ); } } @@ -11102,17 +11128,18 @@ library (sg13g2_stdcell_fast_1p65V_m40C) { max_transition : 2.5074; capacitance : 0.00571065; rise_capacitance : 0.00588635; - rise_capacitance_range (0.00588635, 0.00588635); + rise_capacitance_range (0.00485247, 0.00664102); fall_capacitance : 0.00556423; - fall_capacitance_range (0.00556423, 0.00556423); + fall_capacitance_range (0.0051166, 0.005901); timing () { related_pin : "CLK"; + sdf_edges : both_edges; timing_type : recovery_rising; rise_constraint (CONSTRAINT_4x4) { index_1 ("0.0186, 0.51636, 1.263, 2.5074"); index_2 ("0.0186, 0.51636, 1.263, 2.5074"); values ( \ - "0.051349, 0.0277006, 0.0170034, 0.0143199", \ + "0.051349, 0.0277006, 0.0170034, 0.0116216", \ "0.132032, 0.104405, 0.0934398, 0.0928683", \ "0.211885, 0.187158, 0.178092, 0.182331", \ "0.309484, 0.286494, 0.280961, 0.292202" \ @@ -11121,6 +11148,7 @@ library (sg13g2_stdcell_fast_1p65V_m40C) { } timing () { related_pin : "CLK"; + sdf_edges : both_edges; timing_type : removal_rising; rise_constraint (CONSTRAINT_4x4) { index_1 ("0.0186, 0.51636, 1.263, 2.5074"); @@ -11148,13 +11176,13 @@ library (sg13g2_stdcell_fast_1p65V_m40C) { rise_power (passive_POWER_7x1ds1) { index_1 ("0.0186, 0.0966, 0.174, 0.3294, 0.6408, 1.263, 2.5074"); values ( \ - "0.00304216, 0.00345986, 0.00456724, 0.00735796, 0.0135365, 0.0262691, 0.0521803" \ + "0.00304215, 0.00345986, 0.00456724, 0.00735795, 0.0135365, 0.0262691, 0.0521803" \ ); } fall_power (passive_POWER_7x1ds1) { index_1 ("0.0186, 0.0966, 0.174, 0.3294, 0.6408, 1.263, 2.5074"); values ( \ - "0.0576276, 0.0596025, 0.0634022, 0.0724441, 0.090906, 0.125772, 0.192629" \ + "0.0576201, 0.0596025, 0.0634022, 0.0724441, 0.090906, 0.125772, 0.192629" \ ); } } @@ -11178,7 +11206,7 @@ library (sg13g2_stdcell_fast_1p65V_m40C) { rise_power (passive_POWER_7x1ds1) { index_1 ("0.0186, 0.0966, 0.174, 0.3294, 0.6408, 1.263, 2.5074"); values ( \ - "0.0237214, 0.0242839, 0.0258244, 0.0301941, 0.0398874, 0.0601426, 0.101642" \ + "0.0237214, 0.0242839, 0.0258244, 0.0301941, 0.0398874, 0.0601426, 0.101643" \ ); } fall_power (passive_POWER_7x1ds1) { @@ -11207,26 +11235,26 @@ library (sg13g2_stdcell_fast_1p65V_m40C) { rise_power (passive_POWER_7x1ds1) { index_1 ("0.0186, 0.0966, 0.174, 0.3294, 0.6408, 1.263, 2.5074"); values ( \ - "0.0237214, 0.0242839, 0.0258244, 0.0301941, 0.0398874, 0.0601426, 0.101642" \ + "0.0237214, 0.0242839, 0.0258244, 0.0301941, 0.0398874, 0.0601426, 0.101643" \ ); } fall_power (passive_POWER_7x1ds1) { index_1 ("0.0186, 0.0966, 0.174, 0.3294, 0.6408, 1.263, 2.5074"); values ( \ - "0.0576276, 0.0596025, 0.0634022, 0.0724441, 0.090906, 0.125772, 0.192629" \ + "0.0576201, 0.0596025, 0.0634022, 0.0724441, 0.090906, 0.125772, 0.192629" \ ); } } } ff (IQ,IQN) { - clear : "RESET_B'"; + clear : "!RESET_B"; clocked_on : "CLK"; next_state : "D"; } } cell (sg13g2_dlhq_1) { area : 30.8448; - cell_footprint : "DLHQ"; + cell_footprint : "dlhq"; cell_leakage_power : 3038.64; leakage_power () { value : 3276.21; @@ -11316,6 +11344,7 @@ library (sg13g2_stdcell_fast_1p65V_m40C) { } timing () { related_pin : "GATE"; + sdf_edges : start_edge; timing_sense : non_unate; timing_type : rising_edge; cell_rise (TIMING_DELAY_7x7ds1) { @@ -11435,11 +11464,12 @@ library (sg13g2_stdcell_fast_1p65V_m40C) { max_transition : 2.5074; capacitance : 0.00259884; rise_capacitance : 0.00263878; - rise_capacitance_range (0.00263878, 0.00263878); + rise_capacitance_range (0.00230245, 0.00289759); fall_capacitance : 0.00255891; - fall_capacitance_range (0.00255891, 0.00255891); + fall_capacitance_range (0.00228903, 0.00278522); timing () { related_pin : "GATE"; + sdf_edges : both_edges; timing_type : hold_falling; rise_constraint (CONSTRAINT_4x4) { index_1 ("0.0186, 0.51636, 1.263, 2.5074"); @@ -11464,6 +11494,7 @@ library (sg13g2_stdcell_fast_1p65V_m40C) { } timing () { related_pin : "GATE"; + sdf_edges : both_edges; timing_type : setup_falling; rise_constraint (CONSTRAINT_4x4) { index_1 ("0.0186, 0.51636, 1.263, 2.5074"); @@ -11537,9 +11568,9 @@ library (sg13g2_stdcell_fast_1p65V_m40C) { max_transition : 2.5074; capacitance : 0.00266288; rise_capacitance : 0.00302598; - rise_capacitance_range (0.00302598, 0.00302598); + rise_capacitance_range (0.00255377, 0.00350882); fall_capacitance : 0.0019367; - fall_capacitance_range (0.0019367, 0.0019367); + fall_capacitance_range (0.0019367, 0.00300166); timing () { related_pin : "GATE"; timing_type : min_pulse_width; @@ -11587,7 +11618,7 @@ library (sg13g2_stdcell_fast_1p65V_m40C) { } cell (sg13g2_dlhr_1) { area : 32.6592; - cell_footprint : "DLHR"; + cell_footprint : "dlhr"; cell_leakage_power : 4335.23; leakage_power () { value : 4049.92; @@ -11693,6 +11724,7 @@ library (sg13g2_stdcell_fast_1p65V_m40C) { } timing () { related_pin : "GATE"; + sdf_edges : start_edge; timing_sense : non_unate; timing_type : rising_edge; cell_rise (TIMING_DELAY_7x7ds1) { @@ -11750,6 +11782,7 @@ library (sg13g2_stdcell_fast_1p65V_m40C) { } timing () { related_pin : "RESET_B"; + sdf_edges : start_edge; timing_sense : positive_unate; timing_type : clear; cell_fall (TIMING_DELAY_7x7ds1) { @@ -11923,6 +11956,7 @@ library (sg13g2_stdcell_fast_1p65V_m40C) { } timing () { related_pin : "GATE"; + sdf_edges : start_edge; timing_sense : non_unate; timing_type : rising_edge; cell_rise (TIMING_DELAY_7x7ds1) { @@ -11980,6 +12014,7 @@ library (sg13g2_stdcell_fast_1p65V_m40C) { } timing () { related_pin : "RESET_B"; + sdf_edges : start_edge; timing_sense : negative_unate; timing_type : preset; cell_rise (TIMING_DELAY_7x7ds1) { @@ -12094,11 +12129,12 @@ library (sg13g2_stdcell_fast_1p65V_m40C) { max_transition : 2.5074; capacitance : 0.00238885; rise_capacitance : 0.00258712; - rise_capacitance_range (0.00258712, 0.00258712); + rise_capacitance_range (0.00224291, 0.00284439); fall_capacitance : 0.00219057; - fall_capacitance_range (0.00219057, 0.00219057); + fall_capacitance_range (0.00219057, 0.00273029); timing () { related_pin : "GATE"; + sdf_edges : both_edges; timing_type : hold_falling; rise_constraint (CONSTRAINT_4x4) { index_1 ("0.0186, 0.51636, 1.263, 2.5074"); @@ -12123,6 +12159,7 @@ library (sg13g2_stdcell_fast_1p65V_m40C) { } timing () { related_pin : "GATE"; + sdf_edges : both_edges; timing_type : setup_falling; rise_constraint (CONSTRAINT_4x4) { index_1 ("0.0186, 0.51636, 1.263, 2.5074"); @@ -12196,9 +12233,9 @@ library (sg13g2_stdcell_fast_1p65V_m40C) { max_transition : 2.5074; capacitance : 0.00260676; rise_capacitance : 0.00299963; - rise_capacitance_range (0.00299963, 0.00299963); + rise_capacitance_range (0.00253991, 0.00347551); fall_capacitance : 0.00191923; - fall_capacitance_range (0.00191923, 0.00191923); + fall_capacitance_range (0.00191923, 0.00298944); timing () { related_pin : "GATE"; timing_type : min_pulse_width; @@ -12273,11 +12310,12 @@ library (sg13g2_stdcell_fast_1p65V_m40C) { max_transition : 2.5074; capacitance : 0.00350562; rise_capacitance : 0.00371845; - rise_capacitance_range (0.00371845, 0.00371845); + rise_capacitance_range (0.00311914, 0.00386994); fall_capacitance : 0.00337792; - fall_capacitance_range (0.00337792, 0.00337792); + fall_capacitance_range (0.00308046, 0.00365009); timing () { related_pin : "GATE"; + sdf_edges : both_edges; timing_type : recovery_falling; rise_constraint (CONSTRAINT_4x4) { index_1 ("0.0186, 0.51636, 1.263, 2.5074"); @@ -12292,6 +12330,7 @@ library (sg13g2_stdcell_fast_1p65V_m40C) { } timing () { related_pin : "GATE"; + sdf_edges : both_edges; timing_type : removal_falling; rise_constraint (CONSTRAINT_4x4) { index_1 ("0.0186, 0.51636, 1.263, 2.5074"); @@ -12360,14 +12399,14 @@ library (sg13g2_stdcell_fast_1p65V_m40C) { } } latch (IQ,IQN) { - clear : "RESET_B'"; + clear : "!RESET_B"; data_in : "D"; enable : "GATE"; } } cell (sg13g2_dlhrq_1) { area : 27.216; - cell_footprint : "DLHRQ"; + cell_footprint : "dlhrq"; cell_leakage_power : 3579.74; leakage_power () { value : 3295.8; @@ -12473,6 +12512,7 @@ library (sg13g2_stdcell_fast_1p65V_m40C) { } timing () { related_pin : "GATE"; + sdf_edges : start_edge; timing_sense : non_unate; timing_type : rising_edge; cell_rise (TIMING_DELAY_7x7ds1) { @@ -12530,6 +12570,7 @@ library (sg13g2_stdcell_fast_1p65V_m40C) { } timing () { related_pin : "RESET_B"; + sdf_edges : start_edge; timing_sense : positive_unate; timing_type : clear; cell_fall (TIMING_DELAY_7x7ds1) { @@ -12644,11 +12685,12 @@ library (sg13g2_stdcell_fast_1p65V_m40C) { max_transition : 2.5074; capacitance : 0.0024358; rise_capacitance : 0.00267578; - rise_capacitance_range (0.00267578, 0.00267578); + rise_capacitance_range (0.00233212, 0.00293469); fall_capacitance : 0.00219582; - fall_capacitance_range (0.00219582, 0.00219582); + fall_capacitance_range (0.00219582, 0.00281666); timing () { related_pin : "GATE"; + sdf_edges : both_edges; timing_type : hold_falling; rise_constraint (CONSTRAINT_4x4) { index_1 ("0.0186, 0.51636, 1.263, 2.5074"); @@ -12673,6 +12715,7 @@ library (sg13g2_stdcell_fast_1p65V_m40C) { } timing () { related_pin : "GATE"; + sdf_edges : both_edges; timing_type : setup_falling; rise_constraint (CONSTRAINT_4x4) { index_1 ("0.0186, 0.51636, 1.263, 2.5074"); @@ -12746,9 +12789,9 @@ library (sg13g2_stdcell_fast_1p65V_m40C) { max_transition : 2.5074; capacitance : 0.0025395; rise_capacitance : 0.003021; - rise_capacitance_range (0.003021, 0.003021); + rise_capacitance_range (0.00256043, 0.00349661); fall_capacitance : 0.00193763; - fall_capacitance_range (0.00193763, 0.00193763); + fall_capacitance_range (0.00193763, 0.00301188); timing () { related_pin : "GATE"; timing_type : min_pulse_width; @@ -12823,11 +12866,12 @@ library (sg13g2_stdcell_fast_1p65V_m40C) { max_transition : 2.5074; capacitance : 0.00332327; rise_capacitance : 0.00349977; - rise_capacitance_range (0.00349977, 0.00349977); + rise_capacitance_range (0.00289727, 0.00365016); fall_capacitance : 0.00319088; - fall_capacitance_range (0.00319088, 0.00319088); + fall_capacitance_range (0.0029229, 0.00341951); timing () { related_pin : "GATE"; + sdf_edges : both_edges; timing_type : recovery_falling; rise_constraint (CONSTRAINT_4x4) { index_1 ("0.0186, 0.51636, 1.263, 2.5074"); @@ -12842,6 +12886,7 @@ library (sg13g2_stdcell_fast_1p65V_m40C) { } timing () { related_pin : "GATE"; + sdf_edges : both_edges; timing_type : removal_falling; rise_constraint (CONSTRAINT_4x4) { index_1 ("0.0186, 0.51636, 1.263, 2.5074"); @@ -12910,14 +12955,14 @@ library (sg13g2_stdcell_fast_1p65V_m40C) { } } latch (IQ,IQN) { - clear : "RESET_B'"; + clear : "!RESET_B"; data_in : "D"; enable : "GATE"; } } cell (sg13g2_dllr_1) { area : 34.4736; - cell_footprint : "DLLR"; + cell_footprint : "dllr"; cell_leakage_power : 4403.39; leakage_power () { value : 4299.66; @@ -13039,6 +13084,7 @@ library (sg13g2_stdcell_fast_1p65V_m40C) { } timing () { related_pin : "GATE_N"; + sdf_edges : start_edge; timing_sense : non_unate; timing_type : falling_edge; cell_rise (TIMING_DELAY_7x7ds1) { @@ -13096,6 +13142,7 @@ library (sg13g2_stdcell_fast_1p65V_m40C) { } timing () { related_pin : "RESET_B"; + sdf_edges : start_edge; timing_sense : positive_unate; timing_type : clear; cell_fall (TIMING_DELAY_7x7ds1) { @@ -13269,6 +13316,7 @@ library (sg13g2_stdcell_fast_1p65V_m40C) { } timing () { related_pin : "GATE_N"; + sdf_edges : start_edge; timing_sense : non_unate; timing_type : falling_edge; cell_rise (TIMING_DELAY_7x7ds1) { @@ -13326,6 +13374,7 @@ library (sg13g2_stdcell_fast_1p65V_m40C) { } timing () { related_pin : "RESET_B"; + sdf_edges : start_edge; timing_sense : negative_unate; timing_type : preset; cell_rise (TIMING_DELAY_7x7ds1) { @@ -13440,11 +13489,12 @@ library (sg13g2_stdcell_fast_1p65V_m40C) { max_transition : 2.5074; capacitance : 0.00246063; rise_capacitance : 0.00266064; - rise_capacitance_range (0.00266064, 0.00266064); + rise_capacitance_range (0.00231687, 0.00292086); fall_capacitance : 0.00226062; - fall_capacitance_range (0.00226062, 0.00226062); + fall_capacitance_range (0.00226062, 0.00279881); timing () { related_pin : "GATE_N"; + sdf_edges : both_edges; timing_type : hold_rising; rise_constraint (CONSTRAINT_4x4) { index_1 ("0.0186, 0.51636, 1.263, 2.5074"); @@ -13469,6 +13519,7 @@ library (sg13g2_stdcell_fast_1p65V_m40C) { } timing () { related_pin : "GATE_N"; + sdf_edges : both_edges; timing_type : setup_rising; rise_constraint (CONSTRAINT_4x4) { index_1 ("0.0186, 0.51636, 1.263, 2.5074"); @@ -13542,9 +13593,9 @@ library (sg13g2_stdcell_fast_1p65V_m40C) { max_transition : 2.5074; capacitance : 0.0026335; rise_capacitance : 0.00213452; - rise_capacitance_range (0.00213452, 0.00213452); + rise_capacitance_range (0.00213452, 0.00355715); fall_capacitance : 0.00291863; - fall_capacitance_range (0.00291863, 0.00291863); + fall_capacitance_range (0.00269458, 0.00304977); timing () { related_pin : "GATE_N"; timing_type : min_pulse_width; @@ -13619,11 +13670,12 @@ library (sg13g2_stdcell_fast_1p65V_m40C) { max_transition : 2.5074; capacitance : 0.00346691; rise_capacitance : 0.0036804; - rise_capacitance_range (0.0036804, 0.0036804); + rise_capacitance_range (0.00307812, 0.00383083); fall_capacitance : 0.00333882; - fall_capacitance_range (0.00333882, 0.00333882); + fall_capacitance_range (0.00304367, 0.00361137); timing () { related_pin : "GATE_N"; + sdf_edges : both_edges; timing_type : recovery_rising; rise_constraint (CONSTRAINT_4x4) { index_1 ("0.0186, 0.51636, 1.263, 2.5074"); @@ -13638,6 +13690,7 @@ library (sg13g2_stdcell_fast_1p65V_m40C) { } timing () { related_pin : "GATE_N"; + sdf_edges : both_edges; timing_type : removal_rising; rise_constraint (CONSTRAINT_4x4) { index_1 ("0.0186, 0.51636, 1.263, 2.5074"); @@ -13706,14 +13759,14 @@ library (sg13g2_stdcell_fast_1p65V_m40C) { } } latch (IQ,IQN) { - clear : "RESET_B'"; + clear : "!RESET_B"; data_in : "D"; - enable : "GATE_N'"; + enable : "!GATE_N"; } } cell (sg13g2_dllrq_1) { area : 29.0304; - cell_footprint : "DLLRQ"; + cell_footprint : "dllrq"; cell_leakage_power : 3579.71; leakage_power () { value : 3545.58; @@ -13819,6 +13872,7 @@ library (sg13g2_stdcell_fast_1p65V_m40C) { } timing () { related_pin : "GATE_N"; + sdf_edges : start_edge; timing_sense : non_unate; timing_type : falling_edge; cell_rise (TIMING_DELAY_7x7ds1) { @@ -13876,6 +13930,7 @@ library (sg13g2_stdcell_fast_1p65V_m40C) { } timing () { related_pin : "RESET_B"; + sdf_edges : start_edge; timing_sense : positive_unate; timing_type : clear; cell_fall (TIMING_DELAY_7x7ds1) { @@ -13907,6 +13962,7 @@ library (sg13g2_stdcell_fast_1p65V_m40C) { } timing () { related_pin : "RESET_B"; + sdf_edges : start_edge; timing_sense : positive_unate; timing_type : preset; cell_rise (TIMING_DELAY_7x7ds1) { @@ -14029,11 +14085,12 @@ library (sg13g2_stdcell_fast_1p65V_m40C) { max_transition : 2.5074; capacitance : 0.00234893; rise_capacitance : 0.00258859; - rise_capacitance_range (0.00258859, 0.00258859); + rise_capacitance_range (0.00224444, 0.00284805); fall_capacitance : 0.00210926; - fall_capacitance_range (0.00210926, 0.00210926); + fall_capacitance_range (0.00210926, 0.00272341); timing () { related_pin : "GATE_N"; + sdf_edges : both_edges; timing_type : hold_rising; rise_constraint (CONSTRAINT_4x4) { index_1 ("0.0186, 0.51636, 1.263, 2.5074"); @@ -14058,6 +14115,7 @@ library (sg13g2_stdcell_fast_1p65V_m40C) { } timing () { related_pin : "GATE_N"; + sdf_edges : both_edges; timing_type : setup_rising; rise_constraint (CONSTRAINT_4x4) { index_1 ("0.0186, 0.51636, 1.263, 2.5074"); @@ -14131,9 +14189,9 @@ library (sg13g2_stdcell_fast_1p65V_m40C) { max_transition : 2.5074; capacitance : 0.00249625; rise_capacitance : 0.00301741; - rise_capacitance_range (0.00301741, 0.00301741); + rise_capacitance_range (0.00254119, 0.00350527); fall_capacitance : 0.00223568; - fall_capacitance_range (0.00223568, 0.00223568); + fall_capacitance_range (0.00223568, 0.00299385); timing () { related_pin : "GATE_N"; timing_type : min_pulse_width; @@ -14208,11 +14266,12 @@ library (sg13g2_stdcell_fast_1p65V_m40C) { max_transition : 2.5074; capacitance : 0.0034014; rise_capacitance : 0.0036253; - rise_capacitance_range (0.0036253, 0.0036253); + rise_capacitance_range (0.00284993, 0.00394828); fall_capacitance : 0.0031775; - fall_capacitance_range (0.0031775, 0.0031775); + fall_capacitance_range (0.00290845, 0.00340202); timing () { related_pin : "GATE_N"; + sdf_edges : both_edges; timing_type : recovery_rising; rise_constraint (CONSTRAINT_4x4) { index_1 ("0.0186, 0.51636, 1.263, 2.5074"); @@ -14227,6 +14286,7 @@ library (sg13g2_stdcell_fast_1p65V_m40C) { } timing () { related_pin : "GATE_N"; + sdf_edges : both_edges; timing_type : removal_rising; rise_constraint (CONSTRAINT_4x4) { index_1 ("0.0186, 0.51636, 1.263, 2.5074"); @@ -14295,14 +14355,14 @@ library (sg13g2_stdcell_fast_1p65V_m40C) { } } latch (IQ,IQN) { - clear : "RESET_B'"; + clear : "!RESET_B"; data_in : "D"; - enable : "GATE_N'"; + enable : "!GATE_N"; } } cell (sg13g2_dlygate4sd1_1) { area : 14.5152; - cell_footprint : "DLY1"; + cell_footprint : "dlygate4sd1"; cell_leakage_power : 1219.16; leakage_power () { value : 1348.41; @@ -14409,14 +14469,14 @@ library (sg13g2_stdcell_fast_1p65V_m40C) { max_transition : 2.5074; capacitance : 0.00169497; rise_capacitance : 0.00173559; - rise_capacitance_range (0.00173559, 0.00173559); + rise_capacitance_range (0.00145652, 0.00201424); fall_capacitance : 0.00165435; - fall_capacitance_range (0.00165435, 0.00165435); + fall_capacitance_range (0.0015441, 0.00171358); } } cell (sg13g2_dlygate4sd2_1) { area : 14.5152; - cell_footprint : "DLY2"; + cell_footprint : "dlygate4sd2"; cell_leakage_power : 1671.65; leakage_power () { value : 1800.9; @@ -14523,14 +14583,14 @@ library (sg13g2_stdcell_fast_1p65V_m40C) { max_transition : 2.5074; capacitance : 0.00168185; rise_capacitance : 0.00171615; - rise_capacitance_range (0.00171615, 0.00171615); + rise_capacitance_range (0.00146011, 0.00198475); fall_capacitance : 0.00164755; - fall_capacitance_range (0.00164755, 0.00164755); + fall_capacitance_range (0.00154574, 0.00170567); } } cell (sg13g2_dlygate4sd3_1) { area : 16.3296; - cell_footprint : "DLY4"; + cell_footprint : "dlygate4sd3"; cell_leakage_power : 3848.28; leakage_power () { value : 3977.51; @@ -14637,14 +14697,14 @@ library (sg13g2_stdcell_fast_1p65V_m40C) { max_transition : 2.5074; capacitance : 0.00168027; rise_capacitance : 0.00169544; - rise_capacitance_range (0.00169544, 0.00169544); + rise_capacitance_range (0.00149405, 0.00191302); fall_capacitance : 0.0016651; - fall_capacitance_range (0.0016651, 0.0016651); + fall_capacitance_range (0.00157583, 0.00172303); } } cell (sg13g2_ebufn_2) { area : 18.144; - cell_footprint : "BTL"; + cell_footprint : "ebufn"; cell_leakage_power : 2120.06; leakage_power () { value : 1274.72; @@ -14732,6 +14792,7 @@ library (sg13g2_stdcell_fast_1p65V_m40C) { } timing () { related_pin : "TE_B"; + sdf_edges : start_edge; timing_sense : positive_unate; timing_type : three_state_disable; cell_rise (TIMING_DELAY_7x7ds1) { @@ -14789,6 +14850,7 @@ library (sg13g2_stdcell_fast_1p65V_m40C) { } timing () { related_pin : "TE_B"; + sdf_edges : start_edge; timing_sense : negative_unate; timing_type : three_state_enable; cell_rise (TIMING_DELAY_7x7ds1) { @@ -14908,9 +14970,9 @@ library (sg13g2_stdcell_fast_1p65V_m40C) { max_transition : 2.5074; capacitance : 0.00297968; rise_capacitance : 0.0030312; - rise_capacitance_range (0.0030312, 0.0030312); + rise_capacitance_range (0.00263722, 0.00336424); fall_capacitance : 0.00292816; - fall_capacitance_range (0.00292816, 0.00292816); + fall_capacitance_range (0.00261478, 0.00322723); internal_power () { rise_power (passive_POWER_7x1ds1) { index_1 ("0.0186, 0.0966, 0.174, 0.3294, 0.6408, 1.263, 2.5074"); @@ -14931,9 +14993,9 @@ library (sg13g2_stdcell_fast_1p65V_m40C) { max_transition : 2.5074; capacitance : 0.00723479; rise_capacitance : 0.00718107; - rise_capacitance_range (0.00718107, 0.00718107); + rise_capacitance_range (0.005355, 0.00847386); fall_capacitance : 0.00728851; - fall_capacitance_range (0.00728851, 0.00728851); + fall_capacitance_range (0.00536254, 0.00846688); internal_power () { rise_power (passive_POWER_7x1ds1) { index_1 ("0.0186, 0.0966, 0.174, 0.3294, 0.6408, 1.263, 2.5074"); @@ -14952,7 +15014,7 @@ library (sg13g2_stdcell_fast_1p65V_m40C) { } cell (sg13g2_ebufn_4) { area : 27.216; - cell_footprint : "BTL"; + cell_footprint : "ebufn"; cell_leakage_power : 3586.29; leakage_power () { value : 1562.62; @@ -15040,6 +15102,7 @@ library (sg13g2_stdcell_fast_1p65V_m40C) { } timing () { related_pin : "TE_B"; + sdf_edges : start_edge; timing_sense : positive_unate; timing_type : three_state_disable; cell_rise (TIMING_DELAY_7x7ds1) { @@ -15097,6 +15160,7 @@ library (sg13g2_stdcell_fast_1p65V_m40C) { } timing () { related_pin : "TE_B"; + sdf_edges : start_edge; timing_sense : negative_unate; timing_type : three_state_enable; cell_rise (TIMING_DELAY_7x7ds1) { @@ -15216,9 +15280,9 @@ library (sg13g2_stdcell_fast_1p65V_m40C) { max_transition : 2.5074; capacitance : 0.00334374; rise_capacitance : 0.00340791; - rise_capacitance_range (0.00340791, 0.00340791); + rise_capacitance_range (0.00299415, 0.00379263); fall_capacitance : 0.00327958; - fall_capacitance_range (0.00327958, 0.00327958); + fall_capacitance_range (0.00296731, 0.00357198); internal_power () { rise_power (passive_POWER_7x1ds1) { index_1 ("0.0186, 0.0966, 0.174, 0.3294, 0.6408, 1.263, 2.5074"); @@ -15239,9 +15303,9 @@ library (sg13g2_stdcell_fast_1p65V_m40C) { max_transition : 2.5074; capacitance : 0.0117721; rise_capacitance : 0.0116428; - rise_capacitance_range (0.0116428, 0.0116428); + rise_capacitance_range (0.00818129, 0.0140812); fall_capacitance : 0.0119014; - fall_capacitance_range (0.0119014, 0.0119014); + fall_capacitance_range (0.00817861, 0.0140753); internal_power () { rise_power (passive_POWER_7x1ds1) { index_1 ("0.0186, 0.0966, 0.174, 0.3294, 0.6408, 1.263, 2.5074"); @@ -15260,7 +15324,7 @@ library (sg13g2_stdcell_fast_1p65V_m40C) { } cell (sg13g2_ebufn_8) { area : 45.36; - cell_footprint : "BTL"; + cell_footprint : "ebufn"; cell_leakage_power : 6703.48; leakage_power () { value : 2395.69; @@ -15348,6 +15412,7 @@ library (sg13g2_stdcell_fast_1p65V_m40C) { } timing () { related_pin : "TE_B"; + sdf_edges : start_edge; timing_sense : positive_unate; timing_type : three_state_disable; cell_rise (TIMING_DELAY_7x7ds1) { @@ -15405,6 +15470,7 @@ library (sg13g2_stdcell_fast_1p65V_m40C) { } timing () { related_pin : "TE_B"; + sdf_edges : start_edge; timing_sense : negative_unate; timing_type : three_state_enable; cell_rise (TIMING_DELAY_7x7ds1) { @@ -15524,9 +15590,9 @@ library (sg13g2_stdcell_fast_1p65V_m40C) { max_transition : 2.5074; capacitance : 0.00654777; rise_capacitance : 0.0066757; - rise_capacitance_range (0.0066757, 0.0066757); + rise_capacitance_range (0.00581391, 0.00747198); fall_capacitance : 0.00641984; - fall_capacitance_range (0.00641984, 0.00641984); + fall_capacitance_range (0.00577373, 0.00702418); internal_power () { rise_power (passive_POWER_7x1ds1) { index_1 ("0.0186, 0.0966, 0.174, 0.3294, 0.6408, 1.263, 2.5074"); @@ -15547,9 +15613,9 @@ library (sg13g2_stdcell_fast_1p65V_m40C) { max_transition : 2.5074; capacitance : 0.0196598; rise_capacitance : 0.0193895; - rise_capacitance_range (0.0193895, 0.0193895); + rise_capacitance_range (0.0122624, 0.0243318); fall_capacitance : 0.0199302; - fall_capacitance_range (0.0199302, 0.0199302); + fall_capacitance_range (0.0122742, 0.0243091); internal_power () { rise_power (passive_POWER_7x1ds1) { index_1 ("0.0186, 0.0966, 0.174, 0.3294, 0.6408, 1.263, 2.5074"); @@ -15568,7 +15634,7 @@ library (sg13g2_stdcell_fast_1p65V_m40C) { } cell (sg13g2_einvn_2) { area : 16.3296; - cell_footprint : "einvin"; + cell_footprint : "einvn"; cell_leakage_power : 2724.86; leakage_power () { value : 2203.9; @@ -15648,6 +15714,7 @@ library (sg13g2_stdcell_fast_1p65V_m40C) { } timing () { related_pin : "TE_B"; + sdf_edges : start_edge; timing_sense : positive_unate; timing_type : three_state_disable_rise; cell_rise (TIMING_DELAY_7x7ds1) { @@ -15679,6 +15746,7 @@ library (sg13g2_stdcell_fast_1p65V_m40C) { } timing () { related_pin : "TE_B"; + sdf_edges : start_edge; timing_sense : negative_unate; timing_type : three_state_enable_rise; cell_rise (TIMING_DELAY_7x7ds1) { @@ -15764,9 +15832,9 @@ library (sg13g2_stdcell_fast_1p65V_m40C) { max_transition : 2.5074; capacitance : 0.00436716; rise_capacitance : 0.00446537; - rise_capacitance_range (0.00446537, 0.00446537); + rise_capacitance_range (0.00251912, 0.0080739); fall_capacitance : 0.00426895; - fall_capacitance_range (0.00426895, 0.00426895); + fall_capacitance_range (0.00244865, 0.00701376); internal_power () { rise_power (passive_POWER_7x1ds1) { index_1 ("0.0186, 0.0966, 0.174, 0.3294, 0.6408, 1.263, 2.5074"); @@ -15787,9 +15855,9 @@ library (sg13g2_stdcell_fast_1p65V_m40C) { max_transition : 2.5074; capacitance : 0.00548149; rise_capacitance : 0.00601973; - rise_capacitance_range (0.00601973, 0.00601973); + rise_capacitance_range (0.0055832, 0.00627837); fall_capacitance : 0.00494325; - fall_capacitance_range (0.00494325, 0.00494325); + fall_capacitance_range (0.0035808, 0.00737265); internal_power () { rise_power (passive_POWER_7x1ds1) { index_1 ("0.0186, 0.0966, 0.174, 0.3294, 0.6408, 1.263, 2.5074"); @@ -15808,7 +15876,7 @@ library (sg13g2_stdcell_fast_1p65V_m40C) { } cell (sg13g2_einvn_4) { area : 23.5872; - cell_footprint : "einvin"; + cell_footprint : "einvn"; cell_leakage_power : 5429.26; leakage_power () { value : 4387.32; @@ -15888,6 +15956,7 @@ library (sg13g2_stdcell_fast_1p65V_m40C) { } timing () { related_pin : "TE_B"; + sdf_edges : start_edge; timing_sense : positive_unate; timing_type : three_state_disable_rise; cell_rise (TIMING_DELAY_7x7ds1) { @@ -15919,6 +15988,7 @@ library (sg13g2_stdcell_fast_1p65V_m40C) { } timing () { related_pin : "TE_B"; + sdf_edges : start_edge; timing_sense : negative_unate; timing_type : three_state_enable_rise; cell_rise (TIMING_DELAY_7x7ds1) { @@ -16004,9 +16074,9 @@ library (sg13g2_stdcell_fast_1p65V_m40C) { max_transition : 2.5074; capacitance : 0.00852772; rise_capacitance : 0.00872015; - rise_capacitance_range (0.00872015, 0.00872015); + rise_capacitance_range (0.00477649, 0.0161366); fall_capacitance : 0.00833529; - fall_capacitance_range (0.00833529, 0.00833529); + fall_capacitance_range (0.00466091, 0.0139193); internal_power () { rise_power (passive_POWER_7x1ds1) { index_1 ("0.0186, 0.0966, 0.174, 0.3294, 0.6408, 1.263, 2.5074"); @@ -16027,9 +16097,9 @@ library (sg13g2_stdcell_fast_1p65V_m40C) { max_transition : 2.5074; capacitance : 0.0102165; rise_capacitance : 0.0112209; - rise_capacitance_range (0.0112209, 0.0112209); + rise_capacitance_range (0.0102028, 0.0117397); fall_capacitance : 0.00921216; - fall_capacitance_range (0.00921216, 0.00921216); + fall_capacitance_range (0.00650536, 0.0139128); internal_power () { rise_power (passive_POWER_7x1ds1) { index_1 ("0.0186, 0.0966, 0.174, 0.3294, 0.6408, 1.263, 2.5074"); @@ -16048,7 +16118,7 @@ library (sg13g2_stdcell_fast_1p65V_m40C) { } cell (sg13g2_einvn_8) { area : 39.9168; - cell_footprint : "ITL"; + cell_footprint : "einvn"; cell_leakage_power : 10649.9; leakage_power () { value : 8566.03; @@ -16128,6 +16198,7 @@ library (sg13g2_stdcell_fast_1p65V_m40C) { } timing () { related_pin : "TE_B"; + sdf_edges : start_edge; timing_sense : positive_unate; timing_type : three_state_disable_rise; cell_rise (TIMING_DELAY_7x7ds1) { @@ -16159,6 +16230,7 @@ library (sg13g2_stdcell_fast_1p65V_m40C) { } timing () { related_pin : "TE_B"; + sdf_edges : start_edge; timing_sense : negative_unate; timing_type : three_state_enable_rise; cell_rise (TIMING_DELAY_7x7ds1) { @@ -16244,9 +16316,9 @@ library (sg13g2_stdcell_fast_1p65V_m40C) { max_transition : 2.5074; capacitance : 0.0168651; rise_capacitance : 0.0172565; - rise_capacitance_range (0.0172565, 0.0172565); + rise_capacitance_range (0.00928612, 0.0322121); fall_capacitance : 0.0164737; - fall_capacitance_range (0.0164737, 0.0164737); + fall_capacitance_range (0.00900013, 0.0277937); internal_power () { rise_power (passive_POWER_7x1ds1) { index_1 ("0.0186, 0.0966, 0.174, 0.3294, 0.6408, 1.263, 2.5074"); @@ -16267,9 +16339,9 @@ library (sg13g2_stdcell_fast_1p65V_m40C) { max_transition : 2.5074; capacitance : 0.01738; rise_capacitance : 0.0187973; - rise_capacitance_range (0.0187973, 0.0187973); + rise_capacitance_range (0.0161959, 0.01968); fall_capacitance : 0.0159628; - fall_capacitance_range (0.0159628, 0.0159628); + fall_capacitance_range (0.0112814, 0.0242004); internal_power () { rise_power (passive_POWER_7x1ds1) { index_1 ("0.0186, 0.0966, 0.174, 0.3294, 0.6408, 1.263, 2.5074"); @@ -16320,7 +16392,7 @@ library (sg13g2_stdcell_fast_1p65V_m40C) { } cell (sg13g2_inv_1) { area : 5.4432; - cell_footprint : "IN"; + cell_footprint : "inv"; cell_leakage_power : 469.121; leakage_power () { value : 729.665; @@ -16427,14 +16499,14 @@ library (sg13g2_stdcell_fast_1p65V_m40C) { max_transition : 2.5074; capacitance : 0.00316801; rise_capacitance : 0.00321509; - rise_capacitance_range (0.00321509, 0.00321509); + rise_capacitance_range (0.00292441, 0.00392757); fall_capacitance : 0.00312092; - fall_capacitance_range (0.00312092, 0.00312092); + fall_capacitance_range (0.00292667, 0.00369815); } } cell (sg13g2_inv_16) { area : 34.4736; - cell_footprint : "IN"; + cell_footprint : "inv"; cell_leakage_power : 7505.02; leakage_power () { value : 11672.8; @@ -16541,14 +16613,14 @@ library (sg13g2_stdcell_fast_1p65V_m40C) { max_transition : 2.5074; capacitance : 0.0477772; rise_capacitance : 0.0484812; - rise_capacitance_range (0.0484812, 0.0484812); + rise_capacitance_range (0.0359032, 0.0618459); fall_capacitance : 0.0470731; - fall_capacitance_range (0.0470731, 0.0470731); + fall_capacitance_range (0.0362825, 0.0581928); } } cell (sg13g2_inv_2) { area : 7.2576; - cell_footprint : "IN"; + cell_footprint : "inv"; cell_leakage_power : 938.15; leakage_power () { value : 1459.13; @@ -16655,14 +16727,14 @@ library (sg13g2_stdcell_fast_1p65V_m40C) { max_transition : 2.5074; capacitance : 0.00627805; rise_capacitance : 0.00637234; - rise_capacitance_range (0.00637234, 0.00637234); + rise_capacitance_range (0.0057605, 0.00789927); fall_capacitance : 0.00618377; - fall_capacitance_range (0.00618377, 0.00618377); + fall_capacitance_range (0.00575531, 0.00743169); } } cell (sg13g2_inv_4) { area : 10.8864; - cell_footprint : "IN"; + cell_footprint : "inv"; cell_leakage_power : 1876.25; leakage_power () { value : 2918.19; @@ -16769,14 +16841,14 @@ library (sg13g2_stdcell_fast_1p65V_m40C) { max_transition : 2.5074; capacitance : 0.0124337; rise_capacitance : 0.0126207; - rise_capacitance_range (0.0126207, 0.0126207); + rise_capacitance_range (0.0114789, 0.0157323); fall_capacitance : 0.0122468; - fall_capacitance_range (0.0122468, 0.0122468); + fall_capacitance_range (0.0114653, 0.0148375); } } cell (sg13g2_inv_8) { area : 18.144; - cell_footprint : "IN"; + cell_footprint : "inv"; cell_leakage_power : 3752.56; leakage_power () { value : 5836.48; @@ -16883,14 +16955,14 @@ library (sg13g2_stdcell_fast_1p65V_m40C) { max_transition : 2.5074; capacitance : 0.0248666; rise_capacitance : 0.0252392; - rise_capacitance_range (0.0252392, 0.0252392); + rise_capacitance_range (0.0227736, 0.0315371); fall_capacitance : 0.024494; - fall_capacitance_range (0.024494, 0.024494); + fall_capacitance_range (0.0227677, 0.02975); } } cell (sg13g2_lgcp_1) { area : 27.216; - cell_footprint : "gclk"; + cell_footprint : "lgcp"; cell_leakage_power : 3484.21; clock_gating_integrated_cell : "latch_posedge"; dont_use : true; @@ -17014,9 +17086,9 @@ library (sg13g2_stdcell_fast_1p65V_m40C) { max_transition : 2.5074; capacitance : 0.00561194; rise_capacitance : 0.00576421; - rise_capacitance_range (0.00576421, 0.00576421); + rise_capacitance_range (0.00482728, 0.00675633); fall_capacitance : 0.00545968; - fall_capacitance_range (0.00545968, 0.00545968); + fall_capacitance_range (0.00498597, 0.00578574); timing () { related_pin : "CLK"; timing_type : min_pulse_width; @@ -17054,11 +17126,12 @@ library (sg13g2_stdcell_fast_1p65V_m40C) { max_transition : 2.5074; capacitance : 0.00263991; rise_capacitance : 0.00298092; - rise_capacitance_range (0.00298092, 0.00298092); + rise_capacitance_range (0.00248608, 0.00321915); fall_capacitance : 0.00229891; - fall_capacitance_range (0.00229891, 0.00229891); + fall_capacitance_range (0.00229891, 0.00264997); timing () { related_pin : "CLK"; + sdf_edges : both_edges; timing_type : hold_rising; rise_constraint (CONSTRAINT_4x4) { index_1 ("0.0186, 0.51636, 1.263, 2.5074"); @@ -17083,6 +17156,7 @@ library (sg13g2_stdcell_fast_1p65V_m40C) { } timing () { related_pin : "CLK"; + sdf_edges : both_edges; timing_type : setup_rising; rise_constraint (CONSTRAINT_4x4) { index_1 ("0.0186, 0.51636, 1.263, 2.5074"); @@ -17293,7 +17367,7 @@ library (sg13g2_stdcell_fast_1p65V_m40C) { } timing () { related_pin : "S"; - sdf_cond : "A0 == 1'b0 & A1 == 1'b1"; + sdf_cond : "A0 == 1'b0 && A1 == 1'b1"; timing_sense : positive_unate; timing_type : combinational; when : "(!A0 * A1)"; @@ -17409,7 +17483,7 @@ library (sg13g2_stdcell_fast_1p65V_m40C) { } timing () { related_pin : "S"; - sdf_cond : "A0 == 1'b1 & A1 == 1'b0"; + sdf_cond : "A0 == 1'b1 && A1 == 1'b0"; timing_sense : negative_unate; timing_type : combinational; when : "(A0 * !A1)"; @@ -17619,27 +17693,27 @@ library (sg13g2_stdcell_fast_1p65V_m40C) { max_transition : 2.5074; capacitance : 0.00314194; rise_capacitance : 0.00324948; - rise_capacitance_range (0.00324948, 0.00324948); + rise_capacitance_range (0.00265973, 0.00372952); fall_capacitance : 0.0030344; - fall_capacitance_range (0.0030344, 0.0030344); + fall_capacitance_range (0.00265614, 0.00323327); } pin (A1) { direction : "input"; max_transition : 2.5074; capacitance : 0.00324378; rise_capacitance : 0.00334835; - rise_capacitance_range (0.00334835, 0.00334835); + rise_capacitance_range (0.00272627, 0.00383393); fall_capacitance : 0.00313921; - fall_capacitance_range (0.00313921, 0.00313921); + fall_capacitance_range (0.00276408, 0.00333647); } pin (S) { direction : "input"; max_transition : 2.5074; capacitance : 0.00584922; rise_capacitance : 0.00590084; - rise_capacitance_range (0.00590084, 0.00590084); + rise_capacitance_range (0.00486015, 0.00668607); fall_capacitance : 0.00579759; - fall_capacitance_range (0.00579759, 0.00579759); + fall_capacitance_range (0.0048889, 0.00657285); internal_power () { when : "(A0 * A1)"; rise_power (passive_POWER_7x1ds1) { @@ -17843,7 +17917,7 @@ library (sg13g2_stdcell_fast_1p65V_m40C) { } timing () { related_pin : "S"; - sdf_cond : "A0 == 1'b0 & A1 == 1'b1"; + sdf_cond : "A0 == 1'b0 && A1 == 1'b1"; timing_sense : positive_unate; timing_type : combinational; when : "(!A0 * A1)"; @@ -17959,7 +18033,7 @@ library (sg13g2_stdcell_fast_1p65V_m40C) { } timing () { related_pin : "S"; - sdf_cond : "A0 == 1'b1 & A1 == 1'b0"; + sdf_cond : "A0 == 1'b1 && A1 == 1'b0"; timing_sense : negative_unate; timing_type : combinational; when : "(A0 * !A1)"; @@ -18169,27 +18243,27 @@ library (sg13g2_stdcell_fast_1p65V_m40C) { max_transition : 2.5074; capacitance : 0.00311067; rise_capacitance : 0.00320122; - rise_capacitance_range (0.00320122, 0.00320122); + rise_capacitance_range (0.00269647, 0.00363725); fall_capacitance : 0.00302012; - fall_capacitance_range (0.00302012, 0.00302012); + fall_capacitance_range (0.00268296, 0.00321378); } pin (A1) { direction : "input"; max_transition : 2.5074; capacitance : 0.00321213; rise_capacitance : 0.0033014; - rise_capacitance_range (0.0033014, 0.0033014); + rise_capacitance_range (0.0027772, 0.00374067); fall_capacitance : 0.00312285; - fall_capacitance_range (0.00312285, 0.00312285); + fall_capacitance_range (0.00278951, 0.00331575); } pin (S) { direction : "input"; max_transition : 2.5074; capacitance : 0.00583854; rise_capacitance : 0.00588953; - rise_capacitance_range (0.00588953, 0.00588953); + rise_capacitance_range (0.00485262, 0.00667785); fall_capacitance : 0.00578756; - fall_capacitance_range (0.00578756, 0.00578756); + fall_capacitance_range (0.004881, 0.00656463); internal_power () { when : "(A0 * A1)"; rise_power (passive_POWER_7x1ds1) { @@ -18731,7 +18805,7 @@ library (sg13g2_stdcell_fast_1p65V_m40C) { } timing () { related_pin : "S0"; - sdf_cond : "A2 == 1'b0 & A3 == 1'b1 & S1 == 1'b1"; + sdf_cond : "A2 == 1'b0 && A3 == 1'b1 && S1 == 1'b1"; timing_sense : positive_unate; timing_type : combinational; when : "(!A2 * A3 * S1)"; @@ -18790,7 +18864,7 @@ library (sg13g2_stdcell_fast_1p65V_m40C) { } timing () { related_pin : "S0"; - sdf_cond : "A0 == 1'b0 & A1 == 1'b1 & S1 == 1'b0"; + sdf_cond : "A0 == 1'b0 && A1 == 1'b1 && S1 == 1'b0"; timing_sense : positive_unate; timing_type : combinational; when : "(!A0 * A1 * !S1)"; @@ -18906,7 +18980,7 @@ library (sg13g2_stdcell_fast_1p65V_m40C) { } timing () { related_pin : "S0"; - sdf_cond : "A2 == 1'b1 & A3 == 1'b0 & S1 == 1'b1"; + sdf_cond : "A2 == 1'b1 && A3 == 1'b0 && S1 == 1'b1"; timing_sense : negative_unate; timing_type : combinational; when : "(A2 * !A3 * S1)"; @@ -18965,7 +19039,7 @@ library (sg13g2_stdcell_fast_1p65V_m40C) { } timing () { related_pin : "S0"; - sdf_cond : "A0 == 1'b1 & A1 == 1'b0 & S1 == 1'b0"; + sdf_cond : "A0 == 1'b1 && A1 == 1'b0 && S1 == 1'b0"; timing_sense : negative_unate; timing_type : combinational; when : "(A0 * !A1 * !S1)"; @@ -19024,7 +19098,7 @@ library (sg13g2_stdcell_fast_1p65V_m40C) { } timing () { related_pin : "S1"; - sdf_cond : "A1 == 1'b0 & A3 == 1'b1 & S0 == 1'b1"; + sdf_cond : "A1 == 1'b0 && A3 == 1'b1 && S0 == 1'b1"; timing_sense : positive_unate; timing_type : combinational; when : "(!A1 * A3 * S0)"; @@ -19083,7 +19157,7 @@ library (sg13g2_stdcell_fast_1p65V_m40C) { } timing () { related_pin : "S1"; - sdf_cond : "A0 == 1'b0 & A2 == 1'b1 & S0 == 1'b0"; + sdf_cond : "A0 == 1'b0 && A2 == 1'b1 && S0 == 1'b0"; timing_sense : positive_unate; timing_type : combinational; when : "(!A0 * A2 * !S0)"; @@ -19199,7 +19273,7 @@ library (sg13g2_stdcell_fast_1p65V_m40C) { } timing () { related_pin : "S1"; - sdf_cond : "A1 == 1'b1 & A3 == 1'b0 & S0 == 1'b1"; + sdf_cond : "A1 == 1'b1 && A3 == 1'b0 && S0 == 1'b1"; timing_sense : negative_unate; timing_type : combinational; when : "(A1 * !A3 * S0)"; @@ -19258,7 +19332,7 @@ library (sg13g2_stdcell_fast_1p65V_m40C) { } timing () { related_pin : "S1"; - sdf_cond : "A0 == 1'b1 & A2 == 1'b0 & S0 == 1'b0"; + sdf_cond : "A0 == 1'b1 && A2 == 1'b0 && S0 == 1'b0"; timing_sense : negative_unate; timing_type : combinational; when : "(A0 * !A2 * !S0)"; @@ -19735,45 +19809,45 @@ library (sg13g2_stdcell_fast_1p65V_m40C) { max_transition : 2.5074; capacitance : 0.00320426; rise_capacitance : 0.00323673; - rise_capacitance_range (0.00323673, 0.00323673); + rise_capacitance_range (0.0027104, 0.00346855); fall_capacitance : 0.00317178; - fall_capacitance_range (0.00317178, 0.00317178); + fall_capacitance_range (0.0026746, 0.00337647); } pin (A1) { direction : "input"; max_transition : 2.5074; capacitance : 0.00318361; rise_capacitance : 0.00321977; - rise_capacitance_range (0.00321977, 0.00321977); + rise_capacitance_range (0.00270031, 0.00346167); fall_capacitance : 0.00314745; - fall_capacitance_range (0.00314745, 0.00314745); + fall_capacitance_range (0.00264506, 0.00333853); } pin (A2) { direction : "input"; max_transition : 2.5074; capacitance : 0.00319506; rise_capacitance : 0.00323644; - rise_capacitance_range (0.00323644, 0.00323644); + rise_capacitance_range (0.0027088, 0.00346295); fall_capacitance : 0.00315367; - fall_capacitance_range (0.00315367, 0.00315367); + fall_capacitance_range (0.00266282, 0.00334052); } pin (A3) { direction : "input"; max_transition : 2.5074; capacitance : 0.00325868; rise_capacitance : 0.00329149; - rise_capacitance_range (0.00329149, 0.00329149); + rise_capacitance_range (0.00275675, 0.00352327); fall_capacitance : 0.00322586; - fall_capacitance_range (0.00322586, 0.00322586); + fall_capacitance_range (0.00271985, 0.00341783); } pin (S0) { direction : "input"; max_transition : 2.5074; capacitance : 0.00916877; rise_capacitance : 0.0109295; - rise_capacitance_range (0.0109295, 0.0109295); + rise_capacitance_range (0.00807897, 0.0121581); fall_capacitance : 0.00740802; - fall_capacitance_range (0.00740802, 0.00740802); + fall_capacitance_range (0.00434504, 0.0108376); internal_power () { when : "(A2 * A3 * S1)"; rise_power (passive_POWER_7x1ds1) { @@ -19854,9 +19928,9 @@ library (sg13g2_stdcell_fast_1p65V_m40C) { max_transition : 2.5074; capacitance : 0.00556092; rise_capacitance : 0.00564151; - rise_capacitance_range (0.00564151, 0.00564151); + rise_capacitance_range (0.00458902, 0.00700989); fall_capacitance : 0.00548032; - fall_capacitance_range (0.00548032, 0.00548032); + fall_capacitance_range (0.0046259, 0.00647521); internal_power () { when : "(A1 * A3 * S0)"; rise_power (passive_POWER_7x1ds1) { @@ -20136,18 +20210,18 @@ library (sg13g2_stdcell_fast_1p65V_m40C) { max_transition : 2.5074; capacitance : 0.00317426; rise_capacitance : 0.00315005; - rise_capacitance_range (0.00315005, 0.00315005); + rise_capacitance_range (0.00288145, 0.00352583); fall_capacitance : 0.00319847; - fall_capacitance_range (0.00319847, 0.00319847); + fall_capacitance_range (0.00284119, 0.00418972); } pin (B) { direction : "input"; max_transition : 2.5074; capacitance : 0.00333096; rise_capacitance : 0.00349961; - rise_capacitance_range (0.00349961, 0.00349961); + rise_capacitance_range (0.00295005, 0.00391688); fall_capacitance : 0.00316232; - fall_capacitance_range (0.00316232, 0.00316232); + fall_capacitance_range (0.00296169, 0.00366467); } } cell (sg13g2_nand2_2) { @@ -20353,23 +20427,23 @@ library (sg13g2_stdcell_fast_1p65V_m40C) { max_transition : 2.5074; capacitance : 0.00616529; rise_capacitance : 0.00611656; - rise_capacitance_range (0.00611656, 0.00611656); + rise_capacitance_range (0.00557403, 0.0068313); fall_capacitance : 0.00621402; - fall_capacitance_range (0.00621402, 0.00621402); + fall_capacitance_range (0.00546533, 0.00843968); } pin (B) { direction : "input"; max_transition : 2.5074; capacitance : 0.00640523; rise_capacitance : 0.00673338; - rise_capacitance_range (0.00673338, 0.00673338); + rise_capacitance_range (0.00565032, 0.00754572); fall_capacitance : 0.00607707; - fall_capacitance_range (0.00607707, 0.00607707); + fall_capacitance_range (0.00565302, 0.00718653); } } cell (sg13g2_nand2b_1) { area : 9.072; - cell_footprint : "nand2b1"; + cell_footprint : "nand2b"; cell_leakage_power : 1055.55; leakage_power () { value : 1612.73; @@ -20570,9 +20644,9 @@ library (sg13g2_stdcell_fast_1p65V_m40C) { max_transition : 2.5074; capacitance : 0.00255993; rise_capacitance : 0.00260414; - rise_capacitance_range (0.00260414, 0.00260414); + rise_capacitance_range (0.00225616, 0.00287215); fall_capacitance : 0.00251571; - fall_capacitance_range (0.00251571, 0.00251571); + fall_capacitance_range (0.00224292, 0.0027417); internal_power () { when : "!B"; rise_power (passive_POWER_7x1ds1) { @@ -20608,14 +20682,14 @@ library (sg13g2_stdcell_fast_1p65V_m40C) { max_transition : 2.5074; capacitance : 0.00337909; rise_capacitance : 0.00354821; - rise_capacitance_range (0.00354821, 0.00354821); + rise_capacitance_range (0.00299928, 0.00396054); fall_capacitance : 0.00320997; - fall_capacitance_range (0.00320997, 0.00320997); + fall_capacitance_range (0.00301128, 0.00371275); } } cell (sg13g2_nand2b_2) { area : 14.5152; - cell_footprint : "nand2b2"; + cell_footprint : "nand2b"; cell_leakage_power : 1748.12; leakage_power () { value : 2981.51; @@ -20816,9 +20890,9 @@ library (sg13g2_stdcell_fast_1p65V_m40C) { max_transition : 2.5074; capacitance : 0.00249054; rise_capacitance : 0.00252834; - rise_capacitance_range (0.00252834, 0.00252834); + rise_capacitance_range (0.00224343, 0.00277387); fall_capacitance : 0.00245274; - fall_capacitance_range (0.00245274, 0.00245274); + fall_capacitance_range (0.00221847, 0.00265411); internal_power () { when : "!B"; rise_power (passive_POWER_7x1ds1) { @@ -20854,9 +20928,9 @@ library (sg13g2_stdcell_fast_1p65V_m40C) { max_transition : 2.5074; capacitance : 0.00618967; rise_capacitance : 0.00613998; - rise_capacitance_range (0.00613998, 0.00613998); + rise_capacitance_range (0.00559783, 0.00685005); fall_capacitance : 0.00623935; - fall_capacitance_range (0.00623935, 0.00623935); + fall_capacitance_range (0.00548996, 0.0084708); } } cell (sg13g2_nand3_1) { @@ -21164,32 +21238,32 @@ library (sg13g2_stdcell_fast_1p65V_m40C) { max_transition : 2.5074; capacitance : 0.0031673; rise_capacitance : 0.00310287; - rise_capacitance_range (0.00310287, 0.00310287); + rise_capacitance_range (0.00285963, 0.00335496); fall_capacitance : 0.00323172; - fall_capacitance_range (0.00323172, 0.00323172); + fall_capacitance_range (0.00276675, 0.00449878); } pin (B) { direction : "input"; max_transition : 2.5074; capacitance : 0.00334893; rise_capacitance : 0.00345303; - rise_capacitance_range (0.00345303, 0.00345303); + rise_capacitance_range (0.00293071, 0.00373896); fall_capacitance : 0.00324484; - fall_capacitance_range (0.00324484, 0.00324484); + fall_capacitance_range (0.00292045, 0.00403966); } pin (C) { direction : "input"; max_transition : 2.5074; capacitance : 0.00334408; rise_capacitance : 0.00352903; - rise_capacitance_range (0.00352903, 0.00352903); + rise_capacitance_range (0.00296139, 0.00393315); fall_capacitance : 0.00315914; - fall_capacitance_range (0.00315914, 0.00315914); + fall_capacitance_range (0.0029651, 0.00362532); } } cell (sg13g2_nand3b_1) { area : 12.7008; - cell_footprint : "nand3b1"; + cell_footprint : "nand3b"; cell_leakage_power : 1221.35; leakage_power () { value : 532.652; @@ -21492,9 +21566,9 @@ library (sg13g2_stdcell_fast_1p65V_m40C) { max_transition : 2.5074; capacitance : 0.00254041; rise_capacitance : 0.00258416; - rise_capacitance_range (0.00258416, 0.00258416); + rise_capacitance_range (0.00223756, 0.00285161); fall_capacitance : 0.00249667; - fall_capacitance_range (0.00249667, 0.00249667); + fall_capacitance_range (0.0022238, 0.00272364); internal_power () { when : "(B * !C) + (!B)"; rise_power (passive_POWER_7x1ds1) { @@ -21530,18 +21604,18 @@ library (sg13g2_stdcell_fast_1p65V_m40C) { max_transition : 2.5074; capacitance : 0.00331327; rise_capacitance : 0.00341804; - rise_capacitance_range (0.00341804, 0.00341804); + rise_capacitance_range (0.00289174, 0.00370085); fall_capacitance : 0.00320849; - fall_capacitance_range (0.00320849, 0.00320849); + fall_capacitance_range (0.00288772, 0.00400294); } pin (C) { direction : "input"; max_transition : 2.5074; capacitance : 0.00335473; rise_capacitance : 0.00353856; - rise_capacitance_range (0.00353856, 0.00353856); + rise_capacitance_range (0.00296964, 0.00394012); fall_capacitance : 0.0031709; - fall_capacitance_range (0.0031709, 0.0031709); + fall_capacitance_range (0.00298095, 0.00363845); } } cell (sg13g2_nand4_1) { @@ -21625,12 +21699,12 @@ library (sg13g2_stdcell_fast_1p65V_m40C) { index_1 ("0.0186, 0.0966, 0.174, 0.3294, 0.6408, 1.263, 2.5074"); index_2 ("0.001, 0.0234, 0.039, 0.0648, 0.108, 0.18, 0.3"); values ( \ - "0.0151803, 0.0468192, 0.0673042, 0.101133, 0.157713, 0.25238, 0.408999", \ - "0.023343, 0.0747796, 0.099992, 0.136884, 0.194763, 0.289241, 0.446219", \ - "0.0253364, 0.0907231, 0.121449, 0.164617, 0.227938, 0.32513, 0.482769", \ - "0.0253374, 0.110404, 0.150479, 0.204489, 0.280392, 0.389607, 0.554677", \ + "0.0151803, 0.0468192, 0.067316, 0.101135, 0.157713, 0.25237, 0.409089", \ + "0.023343, 0.0747796, 0.0999921, 0.136884, 0.194763, 0.289241, 0.446219", \ + "0.0253364, 0.0907231, 0.121449, 0.164617, 0.227938, 0.325132, 0.48277", \ + "0.0253374, 0.110404, 0.150479, 0.204489, 0.280392, 0.389607, 0.554678", \ "0.0253384, 0.129848, 0.182761, 0.254658, 0.352043, 0.486879, 0.676933", \ - "0.0253394, 0.142706, 0.213067, 0.307863, 0.43854, 0.614405, 0.853508", \ + "0.0253394, 0.142706, 0.213067, 0.307863, 0.43854, 0.614406, 0.853508", \ "0.0253404, 0.142707, 0.224247, 0.35166, 0.523829, 0.760757, 1.07915" \ ); } @@ -21638,39 +21712,39 @@ library (sg13g2_stdcell_fast_1p65V_m40C) { index_1 ("0.0186, 0.0966, 0.174, 0.3294, 0.6408, 1.263, 2.5074"); index_2 ("0.001, 0.0234, 0.039, 0.0648, 0.108, 0.18, 0.3"); values ( \ - "0.0115436, 0.0531374, 0.0835554, 0.134284, 0.219297, 0.361347, 0.597185", \ - "0.0256565, 0.0698697, 0.0973678, 0.143383, 0.223523, 0.362071, 0.597198", \ - "0.0364686, 0.0877149, 0.116262, 0.161626, 0.238013, 0.370399, 0.599918", \ - "0.0558522, 0.118249, 0.150799, 0.199088, 0.275401, 0.40205, 0.619893", \ - "0.0882312, 0.169028, 0.209372, 0.265013, 0.349293, 0.478378, 0.68835", \ - "0.142024, 0.254146, 0.30442, 0.376018, 0.475089, 0.619839, 0.840959", \ - "0.236627, 0.399987, 0.466658, 0.556597, 0.681661, 0.863914, 1.1163" \ + "0.0115436, 0.0531372, 0.0835879, 0.134297, 0.219297, 0.361353, 0.59701", \ + "0.0256565, 0.0698696, 0.0973677, 0.143383, 0.223523, 0.362071, 0.597048", \ + "0.0364686, 0.0877149, 0.116261, 0.161626, 0.238012, 0.370451, 0.599918", \ + "0.0558522, 0.118249, 0.150799, 0.199088, 0.275401, 0.40205, 0.619897", \ + "0.0882311, 0.169028, 0.209372, 0.265013, 0.349292, 0.478378, 0.68835", \ + "0.142024, 0.254146, 0.304419, 0.376018, 0.475089, 0.619855, 0.840959", \ + "0.236627, 0.399986, 0.466658, 0.556597, 0.681661, 0.863913, 1.1163" \ ); } cell_fall (TIMING_DELAY_7x7ds1) { index_1 ("0.0186, 0.0966, 0.174, 0.3294, 0.6408, 1.263, 2.5074"); index_2 ("0.001, 0.0234, 0.039, 0.0648, 0.108, 0.18, 0.3"); values ( \ - "0.029029, 0.116153, 0.175329, 0.272957, 0.436029, 0.707879, 1.16083", \ - "0.0458195, 0.143819, 0.203698, 0.301298, 0.464452, 0.736538, 1.18883", \ - "0.059419, 0.168746, 0.232285, 0.331673, 0.49481, 0.766111, 1.21865", \ - "0.0823552, 0.208897, 0.280167, 0.387659, 0.556215, 0.828861, 1.2808", \ - "0.118027, 0.270509, 0.352599, 0.4748, 0.660257, 0.945986, 1.4027", \ - "0.179537, 0.369108, 0.466851, 0.610335, 0.822316, 1.14238, 1.62941", \ - "0.288541, 0.532625, 0.651651, 0.823631, 1.07684, 1.44606, 1.99952" \ + "0.029029, 0.11616, 0.175332, 0.272986, 0.436079, 0.707935, 1.16083", \ + "0.0458194, 0.143818, 0.203697, 0.30129, 0.464452, 0.736335, 1.18883", \ + "0.0594189, 0.168746, 0.232282, 0.331673, 0.494822, 0.766155, 1.21862", \ + "0.0823551, 0.208897, 0.280167, 0.387659, 0.556211, 0.828924, 1.2808", \ + "0.118027, 0.270509, 0.352598, 0.474799, 0.660256, 0.945985, 1.40269", \ + "0.179537, 0.369108, 0.466851, 0.610334, 0.822314, 1.14238, 1.62941", \ + "0.28854, 0.532624, 0.65165, 0.82363, 1.07683, 1.44606, 1.99952" \ ); } fall_transition (TIMING_DELAY_7x7ds1) { index_1 ("0.0186, 0.0966, 0.174, 0.3294, 0.6408, 1.263, 2.5074"); index_2 ("0.001, 0.0234, 0.039, 0.0648, 0.108, 0.18, 0.3"); values ( \ - "0.0275716, 0.144967, 0.227144, 0.36348, 0.590943, 0.970374, 1.60303", \ - "0.0385233, 0.152254, 0.230786, 0.364145, 0.591697, 0.970681, 1.60304", \ - "0.0479373, 0.16622, 0.242883, 0.371669, 0.593905, 0.972405, 1.60305", \ - "0.0657426, 0.19249, 0.270853, 0.398086, 0.612273, 0.979071, 1.60487", \ - "0.0974338, 0.23701, 0.321571, 0.453641, 0.66688, 1.02203, 1.62792", \ - "0.15063, 0.316487, 0.40719, 0.549275, 0.775346, 1.13422, 1.7236", \ - "0.24638, 0.449541, 0.557021, 0.71931, 0.957585, 1.34381, 1.94658" \ + "0.0275716, 0.144964, 0.227143, 0.363291, 0.590925, 0.97062, 1.60303", \ + "0.0385232, 0.152254, 0.230786, 0.364141, 0.591696, 0.971054, 1.60304", \ + "0.0479373, 0.16622, 0.242922, 0.371665, 0.59361, 0.972425, 1.60305", \ + "0.0657426, 0.19249, 0.270853, 0.398086, 0.61227, 0.979183, 1.60492", \ + "0.0974338, 0.23701, 0.321571, 0.453641, 0.666879, 1.02202, 1.62791", \ + "0.150629, 0.316486, 0.407189, 0.549274, 0.775344, 1.13422, 1.7236", \ + "0.246381, 0.449541, 0.557021, 0.71931, 0.957584, 1.34381, 1.94662" \ ); } } @@ -21682,52 +21756,52 @@ library (sg13g2_stdcell_fast_1p65V_m40C) { index_1 ("0.0186, 0.0966, 0.174, 0.3294, 0.6408, 1.263, 2.5074"); index_2 ("0.001, 0.0234, 0.039, 0.0648, 0.108, 0.18, 0.3"); values ( \ - "0.0176229, 0.0487704, 0.0692534, 0.103093, 0.159667, 0.25423, 0.410892", \ - "0.0287177, 0.0773923, 0.102234, 0.138958, 0.19674, 0.291178, 0.448122", \ - "0.0326577, 0.0941234, 0.124293, 0.167047, 0.23004, 0.327079, 0.484595", \ - "0.0356463, 0.115404, 0.154523, 0.207584, 0.283044, 0.391783, 0.556673", \ + "0.0176219, 0.0487712, 0.0692569, 0.103074, 0.159667, 0.254228, 0.411004", \ + "0.0287177, 0.0773923, 0.102234, 0.138958, 0.19674, 0.291189, 0.4481", \ + "0.0326577, 0.0941234, 0.124293, 0.167047, 0.230041, 0.327079, 0.484596", \ + "0.0356463, 0.115404, 0.154523, 0.207584, 0.283044, 0.391784, 0.556673", \ "0.0356473, 0.137894, 0.189212, 0.259791, 0.355779, 0.489802, 0.679349", \ - "0.0356483, 0.158275, 0.225115, 0.317071, 0.445254, 0.619892, 0.856815", \ - "0.0356493, 0.158958, 0.249939, 0.371958, 0.538605, 0.771928, 1.08479" \ + "0.0356483, 0.158275, 0.225115, 0.317071, 0.445254, 0.619892, 0.856816", \ + "0.0356493, 0.158958, 0.24994, 0.371959, 0.538605, 0.771929, 1.08479" \ ); } rise_transition (TIMING_DELAY_7x7ds1) { index_1 ("0.0186, 0.0966, 0.174, 0.3294, 0.6408, 1.263, 2.5074"); index_2 ("0.001, 0.0234, 0.039, 0.0648, 0.108, 0.18, 0.3"); values ( \ - "0.0136507, 0.0556155, 0.0860749, 0.136917, 0.221891, 0.363873, 0.599782", \ - "0.0286944, 0.0721398, 0.099667, 0.145737, 0.226031, 0.364585, 0.599783", \ - "0.0398189, 0.0901831, 0.118533, 0.163928, 0.240394, 0.372877, 0.603673", \ - "0.059169, 0.120471, 0.153099, 0.201262, 0.277676, 0.404337, 0.62238", \ - "0.0926588, 0.17182, 0.21048, 0.267554, 0.351527, 0.480671, 0.691096", \ - "0.147676, 0.256477, 0.30624, 0.376131, 0.476248, 0.622697, 0.842555", \ - "0.242691, 0.401469, 0.466556, 0.555873, 0.683618, 0.859778, 1.11562" \ + "0.0136335, 0.0556164, 0.0861447, 0.136896, 0.221891, 0.363873, 0.599671", \ + "0.0286944, 0.0721398, 0.099667, 0.145736, 0.226031, 0.364631, 0.599672", \ + "0.039819, 0.0901831, 0.11853, 0.163928, 0.240394, 0.372877, 0.603673", \ + "0.059169, 0.120471, 0.1531, 0.201262, 0.277676, 0.404288, 0.62238", \ + "0.092661, 0.17182, 0.21047, 0.267554, 0.351527, 0.480671, 0.691096", \ + "0.147676, 0.256478, 0.30624, 0.376131, 0.476248, 0.622697, 0.842555", \ + "0.242689, 0.40147, 0.466555, 0.555873, 0.683618, 0.859778, 1.11562" \ ); } cell_fall (TIMING_DELAY_7x7ds1) { index_1 ("0.0186, 0.0966, 0.174, 0.3294, 0.6408, 1.263, 2.5074"); index_2 ("0.001, 0.0234, 0.039, 0.0648, 0.108, 0.18, 0.3"); values ( \ - "0.0355021, 0.122313, 0.181529, 0.279013, 0.442467, 0.713984, 1.16684", \ - "0.0478004, 0.143611, 0.203606, 0.301486, 0.465059, 0.736938, 1.18981", \ - "0.0589938, 0.163599, 0.226172, 0.325385, 0.488992, 0.760867, 1.21381", \ - "0.0792834, 0.198332, 0.265833, 0.370427, 0.537676, 0.810341, 1.26299", \ - "0.111077, 0.252978, 0.330169, 0.444678, 0.623096, 0.904316, 1.36014", \ - "0.164362, 0.342221, 0.433025, 0.565795, 0.765294, 1.06981, 1.54413", \ - "0.256404, 0.487671, 0.600122, 0.759263, 0.995349, 1.34009, 1.86" \ + "0.0355097, 0.122313, 0.181518, 0.279013, 0.442122, 0.714204, 1.16683", \ + "0.0478004, 0.14361, 0.203606, 0.301521, 0.46508, 0.73662, 1.18981", \ + "0.0589938, 0.163599, 0.226172, 0.325385, 0.489005, 0.760839, 1.21384", \ + "0.0792833, 0.198332, 0.265832, 0.370427, 0.537675, 0.810355, 1.26298", \ + "0.111077, 0.252977, 0.330169, 0.444677, 0.623095, 0.904314, 1.36014", \ + "0.164362, 0.342221, 0.433024, 0.565794, 0.765292, 1.06981, 1.54413", \ + "0.256403, 0.48767, 0.600121, 0.759262, 0.995347, 1.3395, 1.86" \ ); } fall_transition (TIMING_DELAY_7x7ds1) { index_1 ("0.0186, 0.0966, 0.174, 0.3294, 0.6408, 1.263, 2.5074"); index_2 ("0.001, 0.0234, 0.039, 0.0648, 0.108, 0.18, 0.3"); values ( \ - "0.0274649, 0.145048, 0.227238, 0.363403, 0.591102, 0.970475, 1.60288", \ - "0.0380471, 0.150171, 0.22969, 0.363874, 0.591192, 0.971076, 1.60289", \ - "0.0483216, 0.16067, 0.238205, 0.368863, 0.593071, 0.972484, 1.6029", \ - "0.0672129, 0.182533, 0.259902, 0.387257, 0.604997, 0.975945, 1.60472", \ - "0.0987464, 0.223802, 0.30217, 0.430851, 0.644022, 1.00437, 1.6181", \ - "0.15224, 0.297345, 0.381009, 0.514898, 0.732154, 1.08589, 1.68258", \ - "0.245192, 0.425094, 0.522519, 0.667254, 0.894232, 1.25988, 1.85395" \ + "0.0274648, 0.145047, 0.227231, 0.363402, 0.590963, 0.970725, 1.60288", \ + "0.0380474, 0.150171, 0.229689, 0.36417, 0.591188, 0.970726, 1.60289", \ + "0.0483216, 0.16067, 0.238204, 0.368862, 0.593057, 0.97307, 1.60376", \ + "0.0672128, 0.182533, 0.259902, 0.387256, 0.604996, 0.976017, 1.60377", \ + "0.0987464, 0.223801, 0.30217, 0.430851, 0.644021, 1.00436, 1.61809", \ + "0.151937, 0.297344, 0.381009, 0.514896, 0.732153, 1.08589, 1.68258", \ + "0.245193, 0.425093, 0.522518, 0.667254, 0.894236, 1.25727, 1.85394" \ ); } } @@ -21739,52 +21813,52 @@ library (sg13g2_stdcell_fast_1p65V_m40C) { index_1 ("0.0186, 0.0966, 0.174, 0.3294, 0.6408, 1.263, 2.5074"); index_2 ("0.001, 0.0234, 0.039, 0.0648, 0.108, 0.18, 0.3"); values ( \ - "0.0189363, 0.0503698, 0.0709688, 0.104904, 0.161549, 0.256152, 0.412923", \ - "0.0323076, 0.0795355, 0.104185, 0.140815, 0.198607, 0.293089, 0.4501", \ - "0.0377968, 0.097005, 0.126783, 0.169237, 0.232034, 0.329055, 0.486574", \ + "0.0189363, 0.0503713, 0.0709787, 0.104902, 0.161546, 0.256152, 0.41322", \ + "0.0323076, 0.0795355, 0.104185, 0.140814, 0.198607, 0.293104, 0.450089", \ + "0.0377968, 0.097005, 0.126783, 0.169236, 0.232034, 0.329056, 0.486575", \ "0.044023, 0.11993, 0.15787, 0.210518, 0.285396, 0.393974, 0.558602", \ - "0.0479184, 0.145857, 0.195467, 0.264488, 0.359199, 0.492481, 0.681697", \ - "0.0479194, 0.173381, 0.237032, 0.326107, 0.45187, 0.623835, 0.860314", \ - "0.0479204, 0.19233, 0.277304, 0.393519, 0.555422, 0.782829, 1.09265" \ + "0.0479185, 0.145857, 0.195467, 0.264488, 0.359199, 0.492481, 0.681697", \ + "0.0479195, 0.173381, 0.237032, 0.326107, 0.45187, 0.623835, 0.860314", \ + "0.0479205, 0.19233, 0.277304, 0.393519, 0.555422, 0.782829, 1.09265" \ ); } rise_transition (TIMING_DELAY_7x7ds1) { index_1 ("0.0186, 0.0966, 0.174, 0.3294, 0.6408, 1.263, 2.5074"); index_2 ("0.001, 0.0234, 0.039, 0.0648, 0.108, 0.18, 0.3"); values ( \ - "0.0155796, 0.0578883, 0.0886595, 0.13936, 0.224346, 0.366429, 0.602485", \ - "0.0311839, 0.0742034, 0.101801, 0.147996, 0.228444, 0.367184, 0.602486", \ - "0.0428735, 0.0922724, 0.12063, 0.166023, 0.242674, 0.375357, 0.606168", \ - "0.0630411, 0.122912, 0.155124, 0.203474, 0.279943, 0.40668, 0.624949", \ - "0.0978769, 0.173977, 0.213148, 0.269926, 0.353376, 0.482671, 0.693174", \ + "0.0155795, 0.0578869, 0.0885106, 0.139261, 0.224345, 0.366429, 0.602376", \ + "0.0311837, 0.0742034, 0.101801, 0.147983, 0.228424, 0.367203, 0.602377", \ + "0.0428735, 0.0922724, 0.120631, 0.166023, 0.242674, 0.375358, 0.60617", \ + "0.0630412, 0.122912, 0.155124, 0.203474, 0.279943, 0.40668, 0.624949", \ + "0.0978768, 0.173977, 0.213148, 0.269926, 0.353376, 0.482671, 0.693174", \ "0.15636, 0.259648, 0.308434, 0.378307, 0.478047, 0.623782, 0.844142", \ - "0.256819, 0.409407, 0.469942, 0.559187, 0.683009, 0.860805, 1.11669" \ + "0.256818, 0.409409, 0.469941, 0.559187, 0.683004, 0.860805, 1.11669" \ ); } cell_fall (TIMING_DELAY_7x7ds1) { index_1 ("0.0186, 0.0966, 0.174, 0.3294, 0.6408, 1.263, 2.5074"); index_2 ("0.001, 0.0234, 0.039, 0.0648, 0.108, 0.18, 0.3"); values ( \ - "0.0393677, 0.126139, 0.185196, 0.282766, 0.446127, 0.717972, 1.17072", \ - "0.0487292, 0.141492, 0.201309, 0.299216, 0.462766, 0.734841, 1.18754", \ - "0.056726, 0.155762, 0.217186, 0.316095, 0.479531, 0.75182, 1.20472", \ - "0.0714979, 0.181867, 0.24649, 0.348688, 0.514478, 0.786659, 1.2391", \ - "0.0956784, 0.225675, 0.296626, 0.40527, 0.576976, 0.854413, 1.30818", \ - "0.1352, 0.298614, 0.380562, 0.50259, 0.688339, 0.979164, 1.44349", \ - "0.201017, 0.413535, 0.517056, 0.661458, 0.875085, 1.19493, 1.68421" \ + "0.039368, 0.126095, 0.185311, 0.282765, 0.445879, 0.717775, 1.17072", \ + "0.0487291, 0.141492, 0.201309, 0.299216, 0.462758, 0.734888, 1.18753", \ + "0.0567259, 0.155762, 0.217186, 0.316094, 0.479523, 0.751818, 1.20467", \ + "0.0714955, 0.181867, 0.24649, 0.348683, 0.514479, 0.786656, 1.23914", \ + "0.0956781, 0.225675, 0.296625, 0.405269, 0.577495, 0.854412, 1.30815", \ + "0.1352, 0.298613, 0.380561, 0.502589, 0.688338, 0.97862, 1.44348", \ + "0.201017, 0.413534, 0.517056, 0.661456, 0.875083, 1.19493, 1.68363" \ ); } fall_transition (TIMING_DELAY_7x7ds1) { index_1 ("0.0186, 0.0966, 0.174, 0.3294, 0.6408, 1.263, 2.5074"); index_2 ("0.001, 0.0234, 0.039, 0.0648, 0.108, 0.18, 0.3"); values ( \ - "0.0270987, 0.14493, 0.227255, 0.363379, 0.591083, 0.97073, 1.6033", \ - "0.0351281, 0.148602, 0.228989, 0.363718, 0.591497, 0.971218, 1.60331", \ - "0.044877, 0.15631, 0.235082, 0.367338, 0.59231, 0.971219, 1.60332", \ - "0.0653779, 0.173459, 0.251212, 0.380554, 0.601128, 0.974587, 1.60594", \ - "0.0988775, 0.211005, 0.286355, 0.414395, 0.629778, 0.994864, 1.61419", \ - "0.154754, 0.282817, 0.361474, 0.487956, 0.698509, 1.05636, 1.6599", \ - "0.252454, 0.41137, 0.49786, 0.632125, 0.843988, 1.19685, 1.78974" \ + "0.0270966, 0.144879, 0.227223, 0.363379, 0.590959, 0.97047, 1.60329", \ + "0.035128, 0.148601, 0.228988, 0.363717, 0.591488, 0.970729, 1.6033", \ + "0.0448769, 0.156309, 0.235082, 0.367337, 0.59218, 0.971001, 1.60331", \ + "0.0654015, 0.173458, 0.251212, 0.380519, 0.601057, 0.974226, 1.60599", \ + "0.0988774, 0.211005, 0.286354, 0.414394, 0.62997, 0.994862, 1.61416", \ + "0.154754, 0.282816, 0.361474, 0.487956, 0.698507, 1.05585, 1.65979", \ + "0.252453, 0.41137, 0.497856, 0.632124, 0.843986, 1.19684, 1.78925" \ ); } } @@ -21796,52 +21870,52 @@ library (sg13g2_stdcell_fast_1p65V_m40C) { index_1 ("0.0186, 0.0966, 0.174, 0.3294, 0.6408, 1.263, 2.5074"); index_2 ("0.001, 0.0234, 0.039, 0.0648, 0.108, 0.18, 0.3"); values ( \ - "0.0194291, 0.0514591, 0.072209, 0.106221, 0.16292, 0.257352, 0.413914", \ - "0.0345795, 0.0811014, 0.105584, 0.142166, 0.199856, 0.294168, 0.450902", \ - "0.0415105, 0.0992409, 0.128725, 0.170895, 0.233525, 0.330325, 0.487523", \ - "0.0505296, 0.123366, 0.161061, 0.212802, 0.287263, 0.395381, 0.559547", \ - "0.0606262, 0.152728, 0.200951, 0.268318, 0.362283, 0.494442, 0.682931", \ - "0.0698322, 0.188555, 0.248331, 0.335146, 0.457818, 0.628633, 0.862968", \ - "0.0741105, 0.228305, 0.306406, 0.416404, 0.570932, 0.793537, 1.09834" \ + "0.01943, 0.0514502, 0.0722094, 0.106219, 0.162882, 0.257346, 0.413832", \ + "0.0345795, 0.0811097, 0.105587, 0.142163, 0.199856, 0.294222, 0.450912", \ + "0.0415105, 0.0992406, 0.128725, 0.170895, 0.233525, 0.330332, 0.487523", \ + "0.0505296, 0.123366, 0.161061, 0.212802, 0.287263, 0.395382, 0.559547", \ + "0.0606263, 0.152728, 0.200952, 0.268318, 0.362283, 0.494442, 0.682931", \ + "0.0698324, 0.188555, 0.248331, 0.335146, 0.457818, 0.628633, 0.862968", \ + "0.0741111, 0.228306, 0.306406, 0.416405, 0.570932, 0.793537, 1.09834" \ ); } rise_transition (TIMING_DELAY_7x7ds1) { index_1 ("0.0186, 0.0966, 0.174, 0.3294, 0.6408, 1.263, 2.5074"); index_2 ("0.001, 0.0234, 0.039, 0.0648, 0.108, 0.18, 0.3"); values ( \ - "0.0172934, 0.0599687, 0.0908348, 0.141341, 0.226134, 0.367917, 0.603395", \ - "0.0335602, 0.0760728, 0.103598, 0.149827, 0.230167, 0.368745, 0.603396", \ - "0.0458468, 0.0942777, 0.122472, 0.16776, 0.244387, 0.376771, 0.607213", \ + "0.0172934, 0.059934, 0.0908342, 0.141175, 0.226121, 0.367915, 0.603352", \ + "0.0335602, 0.0760686, 0.103601, 0.149828, 0.230168, 0.368718, 0.603387", \ + "0.0458468, 0.0942783, 0.122472, 0.167759, 0.244387, 0.376819, 0.607213", \ "0.0667207, 0.125369, 0.157326, 0.205318, 0.281559, 0.408062, 0.625845", \ "0.103936, 0.177194, 0.215298, 0.271648, 0.355101, 0.483847, 0.694078", \ - "0.16737, 0.264333, 0.31307, 0.380357, 0.479073, 0.625446, 0.844931", \ - "0.279228, 0.416829, 0.47737, 0.56183, 0.685442, 0.859359, 1.1143" \ + "0.167371, 0.264333, 0.31307, 0.380357, 0.479073, 0.625446, 0.844931", \ + "0.279228, 0.416831, 0.47737, 0.56183, 0.685441, 0.859359, 1.1143" \ ); } cell_fall (TIMING_DELAY_7x7ds1) { index_1 ("0.0186, 0.0966, 0.174, 0.3294, 0.6408, 1.263, 2.5074"); index_2 ("0.001, 0.0234, 0.039, 0.0648, 0.108, 0.18, 0.3"); values ( \ - "0.0409027, 0.127581, 0.18682, 0.284297, 0.447679, 0.71898, 1.17214", \ - "0.0485391, 0.139058, 0.198717, 0.296599, 0.459998, 0.732293, 1.18496", \ - "0.0540649, 0.148552, 0.209392, 0.307919, 0.471329, 0.743363, 1.19672", \ - "0.0622568, 0.166584, 0.229108, 0.329612, 0.494461, 0.766472, 1.21877", \ - "0.0758876, 0.196853, 0.263663, 0.368188, 0.536555, 0.810973, 1.26382", \ - "0.097852, 0.248242, 0.324455, 0.438418, 0.615669, 0.896828, 1.35561", \ - "0.130409, 0.323054, 0.418233, 0.55489, 0.751104, 1.05233, 1.52465" \ + "0.0409033, 0.127583, 0.18682, 0.284297, 0.447678, 0.71916, 1.17214", \ + "0.0485391, 0.139058, 0.198716, 0.296616, 0.45997, 0.732291, 1.18496", \ + "0.0540647, 0.148552, 0.209391, 0.307919, 0.471323, 0.743346, 1.19678", \ + "0.0622565, 0.166583, 0.229107, 0.329612, 0.494459, 0.766471, 1.21905", \ + "0.0758873, 0.196854, 0.263662, 0.368187, 0.536769, 0.810947, 1.26383", \ + "0.0978456, 0.248241, 0.324454, 0.438417, 0.615668, 0.896827, 1.35561", \ + "0.130407, 0.323053, 0.418232, 0.554888, 0.751102, 1.05233, 1.52465" \ ); } fall_transition (TIMING_DELAY_7x7ds1) { index_1 ("0.0186, 0.0966, 0.174, 0.3294, 0.6408, 1.263, 2.5074"); index_2 ("0.001, 0.0234, 0.039, 0.0648, 0.108, 0.18, 0.3"); values ( \ - "0.0268895, 0.144871, 0.227204, 0.363354, 0.5911, 0.970321, 1.60307", \ - "0.0323415, 0.14749, 0.228422, 0.363516, 0.591371, 0.9707, 1.60308", \ - "0.040165, 0.153202, 0.23288, 0.366189, 0.591959, 0.97397, 1.6045", \ - "0.0600263, 0.166995, 0.245267, 0.376222, 0.598536, 0.973971, 1.60911", \ - "0.0957565, 0.201715, 0.275589, 0.402819, 0.620906, 0.988869, 1.61115", \ - "0.153178, 0.273341, 0.345716, 0.467642, 0.67715, 1.0381, 1.64746", \ - "0.256442, 0.4026, 0.48165, 0.609587, 0.813603, 1.15558, 1.7507" \ + "0.0268918, 0.144871, 0.227204, 0.363348, 0.591099, 0.970159, 1.60306", \ + "0.0323415, 0.147489, 0.228427, 0.363762, 0.591405, 0.970697, 1.60307", \ + "0.0401649, 0.153201, 0.232882, 0.366193, 0.591721, 0.973284, 1.60455", \ + "0.0600264, 0.166995, 0.245267, 0.376221, 0.598534, 0.973285, 1.60595", \ + "0.0957565, 0.201713, 0.275589, 0.402817, 0.620835, 0.988827, 1.61109", \ + "0.153275, 0.273341, 0.345716, 0.467641, 0.677149, 1.0381, 1.64745", \ + "0.256442, 0.4026, 0.481649, 0.609587, 0.813601, 1.15561, 1.75069" \ ); } } @@ -21851,26 +21925,26 @@ library (sg13g2_stdcell_fast_1p65V_m40C) { index_1 ("0.0186, 0.0966, 0.174, 0.3294, 0.6408, 1.263, 2.5074"); index_2 ("0.001, 0.0234, 0.039, 0.0648, 0.108, 0.18, 0.3"); values ( \ - "0.00373289, 0.00433602, 0.0043483, 0.00427192, 0.00409444, 0.00392062, 0.00315008", \ - "0.00531629, 0.00478416, 0.00465393, 0.00466161, 0.00442806, 0.00404277, 0.00323273", \ - "0.00773395, 0.00605708, 0.00569091, 0.00519416, 0.00520791, 0.00415686, 0.0032217", \ - "0.0130485, 0.00951498, 0.00856618, 0.00765644, 0.00661657, 0.00593638, 0.00444914", \ - "0.0243654, 0.0183774, 0.0165348, 0.0142285, 0.0119918, 0.00975898, 0.00774281", \ - "0.0475712, 0.038666, 0.0348502, 0.0307159, 0.0258595, 0.0212333, 0.0169441", \ - "0.0943368, 0.082476, 0.0769033, 0.0695585, 0.0605318, 0.0521806, 0.0424051" \ + "0.00373284, 0.00433579, 0.0043509, 0.00427657, 0.00409444, 0.00392773, 0.00309856", \ + "0.00531611, 0.00480034, 0.00465747, 0.00466169, 0.00443703, 0.00404277, 0.00314508", \ + "0.00773365, 0.0060571, 0.00569706, 0.00519416, 0.00516241, 0.00411103, 0.00322137", \ + "0.013049, 0.00951436, 0.00856619, 0.00765644, 0.00661657, 0.00588791, 0.00480598", \ + "0.0243653, 0.0183775, 0.0165341, 0.0142294, 0.0119857, 0.00974971, 0.00774306", \ + "0.0475711, 0.0386648, 0.0348501, 0.0307156, 0.0258598, 0.0211943, 0.0169444", \ + "0.0943365, 0.0824761, 0.0769033, 0.0695596, 0.0605323, 0.0521809, 0.0424038" \ ); } fall_power (POWER_7x7ds1) { index_1 ("0.0186, 0.0966, 0.174, 0.3294, 0.6408, 1.263, 2.5074"); index_2 ("0.001, 0.0234, 0.039, 0.0648, 0.108, 0.18, 0.3"); values ( \ - "0.00771179, 0.0083953, 0.00842881, 0.00841225, 0.00822794, 0.00784971, 0.00731581", \ - "0.00907537, 0.00855975, 0.00843223, 0.00832471, 0.00822491, 0.00781102, 0.00721057", \ - "0.0113676, 0.00950604, 0.00920646, 0.00889409, 0.00863788, 0.00822041, 0.00732974", \ - "0.0167559, 0.0128151, 0.0117431, 0.0107937, 0.00995634, 0.00922802, 0.00797526", \ - "0.0280868, 0.0212213, 0.0190613, 0.016931, 0.0146079, 0.0129651, 0.0105848", \ - "0.0517256, 0.040919, 0.0370113, 0.0326413, 0.0279642, 0.0231635, 0.0190368", \ - "0.0998145, 0.0846459, 0.0780602, 0.0702225, 0.061163, 0.0520427, 0.0423877" \ + "0.00770914, 0.00839534, 0.00843498, 0.00839545, 0.00823415, 0.00787423, 0.00733925", \ + "0.00907606, 0.00857636, 0.00843226, 0.00830771, 0.00822491, 0.00790028, 0.00720793", \ + "0.0113682, 0.00950633, 0.00920693, 0.00888802, 0.00860636, 0.0082102, 0.00731863", \ + "0.0167575, 0.0128151, 0.0117468, 0.010782, 0.01034, 0.00895934, 0.0079942", \ + "0.0280895, 0.0212243, 0.0190569, 0.0169495, 0.0146301, 0.0129977, 0.0105843", \ + "0.0517244, 0.040919, 0.0370119, 0.0326413, 0.0279779, 0.0231633, 0.0191695", \ + "0.0998151, 0.0846436, 0.0780529, 0.0702225, 0.0611657, 0.0520401, 0.042102" \ ); } } @@ -21880,26 +21954,26 @@ library (sg13g2_stdcell_fast_1p65V_m40C) { index_1 ("0.0186, 0.0966, 0.174, 0.3294, 0.6408, 1.263, 2.5074"); index_2 ("0.001, 0.0234, 0.039, 0.0648, 0.108, 0.18, 0.3"); values ( \ - "0.00404279, 0.00434321, 0.00430587, 0.00424113, 0.00400541, 0.00384213, 0.00300104", \ - "0.00541086, 0.00482861, 0.00461527, 0.00463885, 0.00423851, 0.00376078, 0.00297932", \ - "0.00785932, 0.00616479, 0.00572434, 0.00518315, 0.00507902, 0.00400476, 0.00353716", \ - "0.0131523, 0.00972562, 0.00876065, 0.00773424, 0.00658916, 0.00577674, 0.00479322", \ - "0.0246526, 0.01908, 0.0169599, 0.0147479, 0.0123666, 0.00997653, 0.0077459", \ - "0.0481074, 0.0398313, 0.0362251, 0.0317758, 0.0269039, 0.022139, 0.0174539", \ - "0.0955892, 0.0848173, 0.0794224, 0.0723181, 0.0633204, 0.0540099, 0.0437483" \ + "0.00404125, 0.00434385, 0.00432105, 0.00423635, 0.00400541, 0.00384059, 0.00304533", \ + "0.00541086, 0.00482863, 0.00461528, 0.00468558, 0.0041799, 0.00377639, 0.00297115", \ + "0.00785936, 0.00616479, 0.00570913, 0.00518355, 0.00507821, 0.00400462, 0.00353693", \ + "0.013154, 0.00972811, 0.0087612, 0.00772264, 0.00658916, 0.00585662, 0.00479601", \ + "0.0246501, 0.0190798, 0.0169573, 0.0147479, 0.0123666, 0.00997678, 0.0077459", \ + "0.0481089, 0.0398315, 0.0362242, 0.0317769, 0.0269039, 0.0221391, 0.0174543", \ + "0.0956002, 0.0848176, 0.0794228, 0.0723184, 0.0633205, 0.0540101, 0.043748" \ ); } fall_power (POWER_7x7ds1) { index_1 ("0.0186, 0.0966, 0.174, 0.3294, 0.6408, 1.263, 2.5074"); index_2 ("0.001, 0.0234, 0.039, 0.0648, 0.108, 0.18, 0.3"); values ( \ - "0.0113547, 0.011962, 0.0119686, 0.0119122, 0.0117715, 0.0113199, 0.0108316", \ - "0.0117385, 0.011805, 0.0117265, 0.011673, 0.01159, 0.0113242, 0.0106674", \ - "0.0136586, 0.0123524, 0.0122445, 0.0120007, 0.0118706, 0.0115603, 0.010836", \ - "0.0189093, 0.0153733, 0.0145029, 0.0136383, 0.0134699, 0.0126925, 0.0113518", \ - "0.0304192, 0.023569, 0.0214886, 0.0194454, 0.0172144, 0.015698, 0.0134261", \ - "0.054286, 0.0433687, 0.0392474, 0.0348214, 0.0304271, 0.0254639, 0.0218109", \ - "0.103202, 0.0878786, 0.0810381, 0.072624, 0.0637879, 0.0540701, 0.0448168" \ + "0.0113633, 0.0119622, 0.011967, 0.0119124, 0.0117004, 0.0113744, 0.0108319", \ + "0.0117406, 0.0118049, 0.0117269, 0.0117158, 0.0115729, 0.0112683, 0.0106877", \ + "0.0136582, 0.0123357, 0.0122436, 0.0120006, 0.0118659, 0.0115968, 0.0109108", \ + "0.018908, 0.0153732, 0.0145025, 0.0136384, 0.0131811, 0.0123677, 0.0112412", \ + "0.0304207, 0.0235685, 0.0214955, 0.0194446, 0.0171695, 0.0157046, 0.0134256", \ + "0.0543004, 0.0433683, 0.039244, 0.0348184, 0.0304274, 0.0255619, 0.0218267", \ + "0.103204, 0.0878785, 0.0810384, 0.0726237, 0.0637871, 0.0541015, 0.0448157" \ ); } } @@ -21909,26 +21983,26 @@ library (sg13g2_stdcell_fast_1p65V_m40C) { index_1 ("0.0186, 0.0966, 0.174, 0.3294, 0.6408, 1.263, 2.5074"); index_2 ("0.001, 0.0234, 0.039, 0.0648, 0.108, 0.18, 0.3"); values ( \ - "0.00440816, 0.00455359, 0.00452351, 0.00440986, 0.00412881, 0.00395887, 0.00313345", \ - "0.00570926, 0.00500289, 0.00477861, 0.00481284, 0.00435079, 0.00380198, 0.00308328", \ - "0.00822087, 0.00640627, 0.00589874, 0.0053905, 0.00522317, 0.00410134, 0.00350907", \ - "0.0138631, 0.0101994, 0.00908209, 0.00801042, 0.00677996, 0.00593845, 0.00423109", \ - "0.0261257, 0.0201976, 0.0178865, 0.015429, 0.0127846, 0.0102113, 0.00796683", \ - "0.0513627, 0.0424252, 0.0384229, 0.0336437, 0.0281879, 0.0229502, 0.0180609", \ - "0.102528, 0.0910477, 0.0848971, 0.0774681, 0.0677099, 0.0570482, 0.0458807" \ + "0.00440823, 0.00455682, 0.00449184, 0.0043567, 0.00412778, 0.0039588, 0.00327222", \ + "0.00570975, 0.0050029, 0.00477861, 0.00481216, 0.00425645, 0.00380631, 0.00308359", \ + "0.00821876, 0.00640628, 0.00592432, 0.00539066, 0.00522317, 0.00410174, 0.00350899", \ + "0.0138618, 0.010201, 0.00908019, 0.00801043, 0.00677996, 0.00593576, 0.00490084", \ + "0.0261274, 0.0201972, 0.0178866, 0.0154288, 0.0127846, 0.0102121, 0.00796683", \ + "0.0513618, 0.0424233, 0.0384235, 0.0336438, 0.028188, 0.0229316, 0.0180608", \ + "0.102498, 0.0910475, 0.0848964, 0.0774686, 0.067697, 0.0570491, 0.0458809" \ ); } fall_power (POWER_7x7ds1) { index_1 ("0.0186, 0.0966, 0.174, 0.3294, 0.6408, 1.263, 2.5074"); index_2 ("0.001, 0.0234, 0.039, 0.0648, 0.108, 0.18, 0.3"); values ( \ - "0.014582, 0.0151667, 0.0151984, 0.0151359, 0.0149584, 0.0145866, 0.0141011", \ - "0.0145644, 0.0148592, 0.0148178, 0.0148241, 0.0147952, 0.0144924, 0.0139695", \ - "0.0161443, 0.0152798, 0.0152253, 0.0151661, 0.0149261, 0.014519, 0.0141257", \ - "0.0213634, 0.0180583, 0.0173399, 0.0166106, 0.0161246, 0.0155852, 0.0147351", \ - "0.0336959, 0.0266402, 0.0245434, 0.0225511, 0.0203684, 0.0190108, 0.0167724", \ - "0.0593907, 0.0481411, 0.0437897, 0.0392304, 0.0343196, 0.0295651, 0.0256329", \ - "0.11195, 0.0964262, 0.0892279, 0.0802844, 0.0705821, 0.060553, 0.0502788" \ + "0.0145816, 0.0151659, 0.0152059, 0.0151369, 0.0149315, 0.0145593, 0.014101", \ + "0.0145645, 0.0148592, 0.0148178, 0.0148248, 0.0147944, 0.0144387, 0.0139706", \ + "0.0161431, 0.0152798, 0.0152256, 0.0151662, 0.0149332, 0.0145191, 0.0140683", \ + "0.0213678, 0.0180611, 0.0173411, 0.0166383, 0.0165234, 0.0157442, 0.0147708", \ + "0.0336989, 0.0266366, 0.0245418, 0.0225664, 0.0204855, 0.0190112, 0.0167521", \ + "0.0593989, 0.0481418, 0.043789, 0.0392307, 0.0343191, 0.0294228, 0.0255993", \ + "0.111949, 0.0964264, 0.0892259, 0.0802837, 0.070582, 0.0605517, 0.0502689" \ ); } } @@ -21938,26 +22012,26 @@ library (sg13g2_stdcell_fast_1p65V_m40C) { index_1 ("0.0186, 0.0966, 0.174, 0.3294, 0.6408, 1.263, 2.5074"); index_2 ("0.001, 0.0234, 0.039, 0.0648, 0.108, 0.18, 0.3"); values ( \ - "0.00471123, 0.00479015, 0.00473124, 0.0045549, 0.00431905, 0.00407903, 0.00325935", \ - "0.00607856, 0.00518751, 0.00492616, 0.00480755, 0.00434103, 0.00390041, 0.0031813", \ - "0.00869031, 0.00669738, 0.0061162, 0.00551338, 0.00520798, 0.00422318, 0.00365624", \ - "0.0147602, 0.0106703, 0.00954326, 0.008329, 0.00710529, 0.00623653, 0.00503466", \ - "0.0281036, 0.021466, 0.0188998, 0.0161398, 0.0134802, 0.0105468, 0.00817819", \ - "0.0555756, 0.0456336, 0.0411117, 0.0357425, 0.0297305, 0.0242753, 0.018792", \ - "0.111565, 0.0987536, 0.091994, 0.0834002, 0.0722155, 0.0605755, 0.0480904" \ + "0.00470989, 0.00476927, 0.00472988, 0.00451732, 0.00429855, 0.00408782, 0.00328517", \ + "0.00607813, 0.00518736, 0.00494163, 0.00488099, 0.00433746, 0.00389887, 0.00318503", \ + "0.00868701, 0.00670023, 0.0061162, 0.00548829, 0.0052079, 0.0042607, 0.00365624", \ + "0.0147604, 0.010669, 0.00954334, 0.00831926, 0.00710529, 0.00623653, 0.00459328", \ + "0.0281037, 0.0214652, 0.0188992, 0.0161414, 0.0134803, 0.0105858, 0.00817818", \ + "0.0555778, 0.0456341, 0.0411119, 0.0357482, 0.0297305, 0.0242766, 0.0187838", \ + "0.111566, 0.0987539, 0.0919929, 0.0834016, 0.0722156, 0.0605725, 0.0480991" \ ); } fall_power (POWER_7x7ds1) { index_1 ("0.0186, 0.0966, 0.174, 0.3294, 0.6408, 1.263, 2.5074"); index_2 ("0.001, 0.0234, 0.039, 0.0648, 0.108, 0.18, 0.3"); values ( \ - "0.0177046, 0.0182614, 0.0182904, 0.0182677, 0.0180642, 0.0176844, 0.0171342", \ - "0.017536, 0.0179217, 0.0179127, 0.017926, 0.0178512, 0.0175109, 0.0170951", \ - "0.0189167, 0.0182214, 0.0182314, 0.0182331, 0.0178849, 0.0179975, 0.0173333", \ - "0.0240244, 0.0210236, 0.0203289, 0.019622, 0.0193071, 0.0182453, 0.0183079", \ - "0.0372245, 0.0300657, 0.0278664, 0.0258109, 0.0238893, 0.0222549, 0.0201679", \ - "0.065325, 0.0538149, 0.0489866, 0.0439722, 0.0389357, 0.0340146, 0.0296965", \ - "0.122799, 0.107006, 0.0993452, 0.0900554, 0.0791137, 0.0678014, 0.0569443" \ + "0.0176927, 0.0182701, 0.018293, 0.0182724, 0.0180636, 0.0176522, 0.0171717", \ + "0.017536, 0.0179217, 0.0179203, 0.0179547, 0.0178576, 0.0175109, 0.0170953", \ + "0.0189168, 0.0182336, 0.0182358, 0.0181236, 0.0178969, 0.0179515, 0.0173424", \ + "0.0240266, 0.0210215, 0.0203289, 0.0196193, 0.0193046, 0.0182494, 0.0177752", \ + "0.0372264, 0.030066, 0.0278651, 0.0258018, 0.0238915, 0.0225403, 0.0201232", \ + "0.0653283, 0.0538139, 0.0489864, 0.0439713, 0.0389357, 0.0340156, 0.0296966", \ + "0.122794, 0.107006, 0.0993463, 0.0900593, 0.0791138, 0.0678047, 0.0568709" \ ); } } @@ -21967,36 +22041,36 @@ library (sg13g2_stdcell_fast_1p65V_m40C) { max_transition : 2.5074; capacitance : 0.00316076; rise_capacitance : 0.00306859; - rise_capacitance_range (0.00306859, 0.00306859); - fall_capacitance : 0.00325293; - fall_capacitance_range (0.00325293, 0.00325293); + rise_capacitance_range (0.00284999, 0.00326459); + fall_capacitance : 0.00325292; + fall_capacitance_range (0.00273293, 0.00472716); } pin (B) { direction : "input"; max_transition : 2.5074; capacitance : 0.0033464; rise_capacitance : 0.00340875; - rise_capacitance_range (0.00340875, 0.00340875); + rise_capacitance_range (0.0029073, 0.00364525); fall_capacitance : 0.00328405; - fall_capacitance_range (0.00328405, 0.00328405); + fall_capacitance_range (0.00287739, 0.00430825); } pin (C) { direction : "input"; max_transition : 2.5074; capacitance : 0.00337752; rise_capacitance : 0.00350145; - rise_capacitance_range (0.00350145, 0.00350145); + rise_capacitance_range (0.00295501, 0.00380174); fall_capacitance : 0.00325358; - fall_capacitance_range (0.00325358, 0.00325358); + fall_capacitance_range (0.00295572, 0.00396772); } pin (D) { direction : "input"; max_transition : 2.5074; - capacitance : 0.00337057; - rise_capacitance : 0.00356309; - rise_capacitance_range (0.00356309, 0.00356309); - fall_capacitance : 0.00317804; - fall_capacitance_range (0.00317804, 0.00317804); + capacitance : 0.00337059; + rise_capacitance : 0.00356308; + rise_capacitance_range (0.00298471, 0.00396804); + fall_capacitance : 0.00317809; + fall_capacitance_range (0.00299024, 0.00363618); } } cell (sg13g2_nor2_1) { @@ -22202,18 +22276,18 @@ library (sg13g2_stdcell_fast_1p65V_m40C) { max_transition : 2.5074; capacitance : 0.00339684; rise_capacitance : 0.00329976; - rise_capacitance_range (0.00329976, 0.00329976); + rise_capacitance_range (0.00302734, 0.00393066); fall_capacitance : 0.00349392; - fall_capacitance_range (0.00349392, 0.00349392); + fall_capacitance_range (0.00297449, 0.00380359); } pin (B) { direction : "input"; max_transition : 2.5074; capacitance : 0.00321123; rise_capacitance : 0.00335748; - rise_capacitance_range (0.00335748, 0.00335748); + rise_capacitance_range (0.00279836, 0.00467486); fall_capacitance : 0.00306497; - fall_capacitance_range (0.00306497, 0.00306497); + fall_capacitance_range (0.00287472, 0.00330274); } } cell (sg13g2_nor2_2) { @@ -22419,18 +22493,18 @@ library (sg13g2_stdcell_fast_1p65V_m40C) { max_transition : 2.5074; capacitance : 0.00655425; rise_capacitance : 0.00639181; - rise_capacitance_range (0.00639181, 0.00639181); + rise_capacitance_range (0.00575413, 0.00762418); fall_capacitance : 0.00671669; - fall_capacitance_range (0.00671669, 0.00671669); + fall_capacitance_range (0.00566229, 0.00734262); } pin (B) { direction : "input"; max_transition : 2.5074; capacitance : 0.00625078; rise_capacitance : 0.00658534; - rise_capacitance_range (0.00658534, 0.00658534); + rise_capacitance_range (0.0052877, 0.00928053); fall_capacitance : 0.00591621; - fall_capacitance_range (0.00591621, 0.00591621); + fall_capacitance_range (0.00547989, 0.00636397); } } cell (sg13g2_nor2b_1) { @@ -22636,18 +22710,18 @@ library (sg13g2_stdcell_fast_1p65V_m40C) { max_transition : 2.5074; capacitance : 0.00321543; rise_capacitance : 0.00336214; - rise_capacitance_range (0.00336214, 0.00336214); + rise_capacitance_range (0.00280468, 0.00468045); fall_capacitance : 0.00306871; - fall_capacitance_range (0.00306871, 0.00306871); + fall_capacitance_range (0.00287696, 0.00330043); } pin (B_N) { direction : "input"; max_transition : 2.5074; capacitance : 0.00257925; rise_capacitance : 0.00262091; - rise_capacitance_range (0.00262091, 0.00262091); + rise_capacitance_range (0.00228073, 0.00287734); fall_capacitance : 0.00253758; - fall_capacitance_range (0.00253758, 0.00253758); + fall_capacitance_range (0.00226754, 0.00276671); internal_power () { when : "A"; rise_power (passive_POWER_7x1ds1) { @@ -22882,18 +22956,18 @@ library (sg13g2_stdcell_fast_1p65V_m40C) { max_transition : 2.5074; capacitance : 0.00624508; rise_capacitance : 0.00653947; - rise_capacitance_range (0.00653947, 0.00653947); + rise_capacitance_range (0.00538272, 0.00915674); fall_capacitance : 0.00595068; - fall_capacitance_range (0.00595068, 0.00595068); + fall_capacitance_range (0.00553967, 0.00648207); } pin (B_N) { direction : "input"; max_transition : 2.5074; capacitance : 0.00302718; rise_capacitance : 0.00307855; - rise_capacitance_range (0.00307855, 0.00307855); + rise_capacitance_range (0.00272352, 0.00335967); fall_capacitance : 0.00297581; - fall_capacitance_range (0.00297581, 0.00297581); + fall_capacitance_range (0.00268381, 0.00322831); internal_power () { when : "A"; rise_power (passive_POWER_7x1ds1) { @@ -23226,27 +23300,27 @@ library (sg13g2_stdcell_fast_1p65V_m40C) { max_transition : 2.5074; capacitance : 0.00339273; rise_capacitance : 0.00326016; - rise_capacitance_range (0.00326016, 0.00326016); + rise_capacitance_range (0.00301107, 0.00390265); fall_capacitance : 0.0035253; - fall_capacitance_range (0.0035253, 0.0035253); + fall_capacitance_range (0.00296543, 0.00383117); } pin (B) { direction : "input"; max_transition : 2.5074; capacitance : 0.0033747; rise_capacitance : 0.003363; - rise_capacitance_range (0.003363, 0.003363); + rise_capacitance_range (0.00289546, 0.00446295); fall_capacitance : 0.00338641; - fall_capacitance_range (0.00338641, 0.00338641); + fall_capacitance_range (0.002876, 0.00359449); } pin (C) { direction : "input"; max_transition : 2.5074; capacitance : 0.00320029; rise_capacitance : 0.00339287; - rise_capacitance_range (0.00339287, 0.00339287); + rise_capacitance_range (0.0027066, 0.00514308); fall_capacitance : 0.00300771; - fall_capacitance_range (0.00300771, 0.00300771); + fall_capacitance_range (0.00283668, 0.00314735); } } cell (sg13g2_nor3_2) { @@ -23550,27 +23624,27 @@ library (sg13g2_stdcell_fast_1p65V_m40C) { max_transition : 2.5074; capacitance : 0.00651049; rise_capacitance : 0.00625724; - rise_capacitance_range (0.00625724, 0.00625724); + rise_capacitance_range (0.00576115, 0.0074824); fall_capacitance : 0.00676374; - fall_capacitance_range (0.00676374, 0.00676374); + fall_capacitance_range (0.00563529, 0.00741154); } pin (B) { direction : "input"; max_transition : 2.5074; capacitance : 0.00643981; rise_capacitance : 0.00643464; - rise_capacitance_range (0.00643464, 0.00643464); + rise_capacitance_range (0.00546261, 0.00861229); fall_capacitance : 0.00644498; - fall_capacitance_range (0.00644498, 0.00644498); + fall_capacitance_range (0.0054288, 0.00687537); } pin (C) { direction : "input"; max_transition : 2.5074; capacitance : 0.00616269; rise_capacitance : 0.00656413; - rise_capacitance_range (0.00656413, 0.00656413); + rise_capacitance_range (0.00511458, 0.0100841); fall_capacitance : 0.00576125; - fall_capacitance_range (0.00576125, 0.00576125); + fall_capacitance_range (0.00540517, 0.00605929); } } cell (sg13g2_nor4_1) { @@ -23996,36 +24070,36 @@ library (sg13g2_stdcell_fast_1p65V_m40C) { max_transition : 2.5074; capacitance : 0.00337161; rise_capacitance : 0.00322805; - rise_capacitance_range (0.00322805, 0.00322805); + rise_capacitance_range (0.00301315, 0.00381748); fall_capacitance : 0.00351517; - fall_capacitance_range (0.00351517, 0.00351517); + fall_capacitance_range (0.00293729, 0.00384598); } pin (B) { direction : "input"; max_transition : 2.5074; capacitance : 0.00335969; rise_capacitance : 0.00331804; - rise_capacitance_range (0.00331804, 0.00331804); + rise_capacitance_range (0.00292928, 0.0042438); fall_capacitance : 0.00340134; - fall_capacitance_range (0.00340134, 0.00340134); + fall_capacitance_range (0.00285217, 0.00364772); } pin (C) { direction : "input"; max_transition : 2.5074; capacitance : 0.00331493; rise_capacitance : 0.00335771; - rise_capacitance_range (0.00335771, 0.00335771); + rise_capacitance_range (0.00281573, 0.0046544); fall_capacitance : 0.00327215; - fall_capacitance_range (0.00327215, 0.00327215); + fall_capacitance_range (0.00278835, 0.00345099); } pin (D) { direction : "input"; max_transition : 2.5074; capacitance : 0.00312606; rise_capacitance : 0.00335013; - rise_capacitance_range (0.00335013, 0.00335013); + rise_capacitance_range (0.00264776, 0.00521422); fall_capacitance : 0.00290199; - fall_capacitance_range (0.00290199, 0.00290199); + fall_capacitance_range (0.00275016, 0.00300718); } } cell (sg13g2_nor4_2) { @@ -24073,7 +24147,7 @@ library (sg13g2_stdcell_fast_1p65V_m40C) { when : "A&!B&!C&D&!Y"; } leakage_power () { - value : 2698.48; + value : 2698.49; when : "A&!B&C&!D&!Y"; } leakage_power () { @@ -24093,7 +24167,7 @@ library (sg13g2_stdcell_fast_1p65V_m40C) { when : "A&B&C&!D&!Y"; } leakage_power () { - value : 5284.78; + value : 5284.79; when : "A&B&C&D&!Y"; } pin (Y) { @@ -24109,52 +24183,52 @@ library (sg13g2_stdcell_fast_1p65V_m40C) { index_1 ("0.0186, 0.0966, 0.174, 0.3294, 0.6408, 1.263, 2.5074"); index_2 ("0.001, 0.0468, 0.078, 0.1296, 0.216, 0.36, 0.6"); values ( \ - "0.0517553, 0.176782, 0.259989, 0.397618, 0.627556, 1.01125, 1.64915", \ - "0.0586396, 0.186318, 0.269978, 0.408105, 0.638842, 1.02179, 1.6604", \ - "0.0612931, 0.19281, 0.276961, 0.414688, 0.645068, 1.02829, 1.66848", \ - "0.0672586, 0.205167, 0.290698, 0.429374, 0.659025, 1.04166, 1.67989", \ - "0.0837721, 0.233887, 0.322179, 0.461858, 0.69257, 1.0736, 1.70881", \ - "0.113226, 0.289571, 0.384281, 0.531862, 0.764243, 1.14663, 1.78073", \ - "0.159929, 0.380799, 0.490628, 0.654089, 0.905196, 1.2981, 1.93531" \ + "0.0517569, 0.176762, 0.259964, 0.397577, 0.627505, 1.01115, 1.649", \ + "0.0586479, 0.186313, 0.269952, 0.408076, 0.638109, 1.02169, 1.66068", \ + "0.0614226, 0.192779, 0.276934, 0.414649, 0.644957, 1.0282, 1.66719", \ + "0.0672684, 0.205149, 0.290671, 0.429338, 0.658992, 1.04159, 1.67973", \ + "0.0837642, 0.233899, 0.322152, 0.461822, 0.692563, 1.07344, 1.7088", \ + "0.113216, 0.289548, 0.38425, 0.531822, 0.764181, 1.14657, 1.78064", \ + "0.159917, 0.380771, 0.490591, 0.65404, 0.905128, 1.298, 1.93517" \ ); } rise_transition (TIMING_DELAY_7x7ds1) { index_1 ("0.0186, 0.0966, 0.174, 0.3294, 0.6408, 1.263, 2.5074"); index_2 ("0.001, 0.0468, 0.078, 0.1296, 0.216, 0.36, 0.6"); values ( \ - "0.0363531, 0.212735, 0.332642, 0.530997, 0.863149, 1.41757, 2.33982", \ - "0.041966, 0.213967, 0.333047, 0.531575, 0.863987, 1.41806, 2.33983", \ - "0.0487695, 0.218586, 0.335928, 0.532246, 0.863988, 1.41807, 2.34114", \ - "0.0670509, 0.231001, 0.34628, 0.539493, 0.86703, 1.41808, 2.34222", \ - "0.101702, 0.25991, 0.373648, 0.562598, 0.883671, 1.42698, 2.35246", \ - "0.160398, 0.324735, 0.432848, 0.61937, 0.933378, 1.46448, 2.36609", \ - "0.270542, 0.445497, 0.560397, 0.741858, 1.04542, 1.56857, 2.45087" \ + "0.0363466, 0.212899, 0.332613, 0.530952, 0.863078, 1.41745, 2.33963", \ + "0.0419625, 0.213877, 0.333034, 0.531531, 0.863279, 1.41795, 2.34158", \ + "0.0488275, 0.218556, 0.335885, 0.532175, 0.86329, 1.41796, 2.34159", \ + "0.0670441, 0.23098, 0.346312, 0.539445, 0.866961, 1.41797, 2.34201", \ + "0.101695, 0.260009, 0.373649, 0.562552, 0.883649, 1.42694, 2.34839", \ + "0.160391, 0.324715, 0.43282, 0.619326, 0.933288, 1.46432, 2.36589", \ + "0.270538, 0.445474, 0.560366, 0.741812, 1.04535, 1.56847, 2.45066" \ ); } cell_fall (TIMING_DELAY_7x7ds1) { index_1 ("0.0186, 0.0966, 0.174, 0.3294, 0.6408, 1.263, 2.5074"); index_2 ("0.001, 0.0468, 0.078, 0.1296, 0.216, 0.36, 0.6"); values ( \ - "0.0165157, 0.0464661, 0.0645607, 0.0939575, 0.142621, 0.223272, 0.357324", \ - "0.0303333, 0.0755435, 0.0980185, 0.130746, 0.18123, 0.262331, 0.396433", \ - "0.0373048, 0.0941379, 0.121133, 0.15965, 0.216019, 0.301163, 0.436511", \ - "0.0447272, 0.118801, 0.153704, 0.201746, 0.269847, 0.367539, 0.513204", \ - "0.0482828, 0.146705, 0.191887, 0.254708, 0.342016, 0.462605, 0.633814", \ - "0.0482838, 0.174182, 0.236027, 0.318901, 0.432224, 0.59031, 0.805224", \ - "0.0482848, 0.192842, 0.275281, 0.387442, 0.540984, 0.74697, 1.03021" \ + "0.0165166, 0.046445, 0.0645389, 0.0939303, 0.142546, 0.223235, 0.357324", \ + "0.0303691, 0.0755317, 0.0980034, 0.130749, 0.181205, 0.262284, 0.396343", \ + "0.037298, 0.0941236, 0.121048, 0.159645, 0.215958, 0.30113, 0.436429", \ + "0.0447183, 0.118784, 0.153667, 0.201724, 0.26981, 0.367468, 0.5131", \ + "0.0482714, 0.146684, 0.19186, 0.254642, 0.341969, 0.46254, 0.633719", \ + "0.0482724, 0.174154, 0.235994, 0.318875, 0.432166, 0.590237, 0.805111", \ + "0.0482734, 0.192804, 0.275231, 0.387385, 0.540911, 0.74686, 1.03006" \ ); } fall_transition (TIMING_DELAY_7x7ds1) { index_1 ("0.0186, 0.0966, 0.174, 0.3294, 0.6408, 1.263, 2.5074"); index_2 ("0.001, 0.0468, 0.078, 0.1296, 0.216, 0.36, 0.6"); values ( \ - "0.0142339, 0.0497746, 0.0740633, 0.114647, 0.182852, 0.296142, 0.485242", \ - "0.0298469, 0.0669008, 0.0892393, 0.125951, 0.189084, 0.298587, 0.486069", \ - "0.043123, 0.0837734, 0.107737, 0.144979, 0.206043, 0.310045, 0.490832", \ - "0.0664569, 0.114883, 0.140841, 0.181197, 0.244311, 0.346171, 0.518595", \ - "0.108291, 0.168729, 0.19867, 0.243898, 0.314349, 0.421798, 0.592504", \ - "0.182796, 0.267738, 0.301952, 0.354136, 0.433731, 0.55357, 0.73912", \ - "0.319308, 0.444771, 0.492151, 0.555055, 0.644803, 0.783751, 0.992045" \ + "0.0142272, 0.0497621, 0.074045, 0.114681, 0.1827, 0.296069, 0.485067", \ + "0.0297969, 0.0668891, 0.0892285, 0.125941, 0.189099, 0.298518, 0.485954", \ + "0.043119, 0.0838229, 0.107742, 0.144861, 0.206084, 0.310051, 0.490724", \ + "0.0664519, 0.114816, 0.140816, 0.181215, 0.244276, 0.346031, 0.518464", \ + "0.108284, 0.168715, 0.198648, 0.244298, 0.314303, 0.421736, 0.592393", \ + "0.182789, 0.267719, 0.301927, 0.354107, 0.433685, 0.553496, 0.738709", \ + "0.319301, 0.444748, 0.492117, 0.555018, 0.644816, 0.783886, 0.991913" \ ); } } @@ -24166,52 +24240,52 @@ library (sg13g2_stdcell_fast_1p65V_m40C) { index_1 ("0.0186, 0.0966, 0.174, 0.3294, 0.6408, 1.263, 2.5074"); index_2 ("0.001, 0.0468, 0.078, 0.1296, 0.216, 0.36, 0.6"); values ( \ - "0.0497574, 0.174633, 0.25798, 0.395784, 0.625573, 1.00873, 1.64718", \ - "0.05789, 0.187509, 0.271194, 0.409124, 0.639309, 1.02298, 1.66186", \ - "0.0631999, 0.198645, 0.283085, 0.421034, 0.651241, 1.0344, 1.67374", \ - "0.0761476, 0.220611, 0.307389, 0.446936, 0.676605, 1.05957, 1.69735", \ - "0.104171, 0.265921, 0.355761, 0.499509, 0.732326, 1.11448, 1.7499", \ - "0.152583, 0.344887, 0.446567, 0.601, 0.839769, 1.23176, 1.86642", \ - "0.235074, 0.475262, 0.595628, 0.773696, 1.04078, 1.44605, 2.09932" \ + "0.0497536, 0.174618, 0.257969, 0.395859, 0.625514, 1.00864, 1.64708", \ + "0.0578847, 0.187496, 0.271166, 0.409156, 0.639306, 1.0229, 1.66279", \ + "0.0631947, 0.198685, 0.283065, 0.420835, 0.651181, 1.0344, 1.67491", \ + "0.0761416, 0.220583, 0.307365, 0.446836, 0.676585, 1.05938, 1.69737", \ + "0.1044, 0.265904, 0.355745, 0.499463, 0.732282, 1.11442, 1.74976", \ + "0.152567, 0.344861, 0.447406, 0.600957, 0.839743, 1.23166, 1.86616", \ + "0.235047, 0.475223, 0.595581, 0.773653, 1.04077, 1.44594, 2.09922" \ ); } rise_transition (TIMING_DELAY_7x7ds1) { index_1 ("0.0186, 0.0966, 0.174, 0.3294, 0.6408, 1.263, 2.5074"); index_2 ("0.001, 0.0468, 0.078, 0.1296, 0.216, 0.36, 0.6"); values ( \ - "0.0364298, 0.212631, 0.332506, 0.531223, 0.863152, 1.41684, 2.33982", \ - "0.0448047, 0.214561, 0.33329, 0.531224, 0.863366, 1.41806, 2.34184", \ - "0.0536843, 0.22098, 0.337244, 0.533, 0.864282, 1.41807, 2.34185", \ - "0.0722026, 0.236916, 0.350646, 0.542136, 0.86819, 1.4183, 2.34224", \ - "0.102543, 0.269383, 0.38177, 0.570073, 0.88899, 1.42914, 2.35684", \ - "0.154091, 0.33205, 0.445388, 0.6332, 0.946423, 1.47571, 2.37223", \ - "0.246772, 0.447616, 0.568682, 0.759109, 1.0748, 1.59497, 2.47297" \ + "0.0364285, 0.21261, 0.332637, 0.531202, 0.863079, 1.41672, 2.33963", \ + "0.0448016, 0.21454, 0.333256, 0.531203, 0.863343, 1.41795, 2.34071", \ + "0.0536797, 0.221021, 0.337215, 0.532818, 0.864214, 1.41796, 2.34139", \ + "0.0722228, 0.236923, 0.350617, 0.542035, 0.868126, 1.41796, 2.34203", \ + "0.10256, 0.269367, 0.381611, 0.570036, 0.888866, 1.42898, 2.3527", \ + "0.154086, 0.332032, 0.445863, 0.633157, 0.945788, 1.4756, 2.37188", \ + "0.246768, 0.447596, 0.568654, 0.759058, 1.07477, 1.59475, 2.47281" \ ); } cell_fall (TIMING_DELAY_7x7ds1) { index_1 ("0.0186, 0.0966, 0.174, 0.3294, 0.6408, 1.263, 2.5074"); index_2 ("0.001, 0.0468, 0.078, 0.1296, 0.216, 0.36, 0.6"); values ( \ - "0.0168926, 0.0460333, 0.0638634, 0.0929942, 0.141618, 0.222351, 0.356709", \ - "0.0293643, 0.0745336, 0.0969957, 0.129744, 0.180246, 0.261474, 0.395868", \ - "0.0350209, 0.0925156, 0.119632, 0.15833, 0.214893, 0.300304, 0.436039", \ - "0.0397866, 0.116017, 0.151115, 0.199868, 0.268155, 0.366338, 0.512583", \ - "0.0397876, 0.14081, 0.187273, 0.25114, 0.339532, 0.460945, 0.633056", \ - "0.0397886, 0.160343, 0.224981, 0.310605, 0.426613, 0.586661, 0.803184", \ - "0.0397896, 0.160344, 0.246672, 0.366091, 0.525591, 0.736772, 1.025" \ + "0.0168914, 0.046041, 0.0638384, 0.0929914, 0.141545, 0.222339, 0.356699", \ + "0.0293635, 0.0745325, 0.0970028, 0.129731, 0.180237, 0.261462, 0.395873", \ + "0.0350202, 0.0925103, 0.119692, 0.158327, 0.214891, 0.300294, 0.436018", \ + "0.0397862, 0.116019, 0.151181, 0.19988, 0.268167, 0.366305, 0.51247", \ + "0.0397872, 0.140809, 0.187271, 0.251137, 0.339527, 0.460938, 0.633045", \ + "0.0397882, 0.160345, 0.224981, 0.310602, 0.426608, 0.586698, 0.803173", \ + "0.0397892, 0.160346, 0.246677, 0.3662, 0.525589, 0.736766, 1.02498" \ ); } fall_transition (TIMING_DELAY_7x7ds1) { index_1 ("0.0186, 0.0966, 0.174, 0.3294, 0.6408, 1.263, 2.5074"); index_2 ("0.001, 0.0468, 0.078, 0.1296, 0.216, 0.36, 0.6"); values ( \ - "0.0130773, 0.0477425, 0.0720435, 0.112647, 0.180979, 0.294678, 0.484313", \ - "0.0275227, 0.0647956, 0.0872975, 0.124057, 0.187361, 0.29706, 0.485098", \ - "0.039619, 0.0813165, 0.105504, 0.143069, 0.204325, 0.308658, 0.489924", \ - "0.0610106, 0.111832, 0.138115, 0.179163, 0.242572, 0.344847, 0.517672", \ - "0.0978871, 0.163578, 0.194756, 0.240885, 0.31176, 0.420445, 0.591719", \ - "0.161006, 0.256902, 0.294238, 0.349107, 0.430674, 0.551524, 0.7386", \ - "0.273187, 0.417437, 0.472634, 0.542402, 0.637446, 0.780816, 0.990535" \ + "0.0130771, 0.0477961, 0.0719885, 0.112648, 0.180931, 0.29467, 0.4843", \ + "0.0275225, 0.0647944, 0.0873135, 0.124047, 0.187339, 0.297046, 0.484635", \ + "0.0396186, 0.0812876, 0.105545, 0.143073, 0.204315, 0.30867, 0.489915", \ + "0.06101, 0.111629, 0.13818, 0.179151, 0.24258, 0.344801, 0.517534", \ + "0.0976389, 0.163576, 0.194754, 0.240882, 0.311755, 0.420437, 0.591706", \ + "0.161005, 0.256892, 0.294235, 0.349103, 0.430668, 0.551404, 0.738589", \ + "0.273104, 0.417619, 0.472629, 0.541942, 0.637438, 0.780806, 0.990521" \ ); } } @@ -24223,52 +24297,52 @@ library (sg13g2_stdcell_fast_1p65V_m40C) { index_1 ("0.0186, 0.0966, 0.174, 0.3294, 0.6408, 1.263, 2.5074"); index_2 ("0.001, 0.0468, 0.078, 0.1296, 0.216, 0.36, 0.6"); values ( \ - "0.0426295, 0.16762, 0.250925, 0.388637, 0.618454, 1.00215, 1.64012", \ - "0.0529223, 0.184952, 0.268617, 0.406641, 0.636647, 1.02072, 1.6588", \ - "0.0627976, 0.20271, 0.287578, 0.425322, 0.65543, 1.03884, 1.6774", \ - "0.0829737, 0.236471, 0.325023, 0.465218, 0.695318, 1.07759, 1.71818", \ - "0.118895, 0.296287, 0.391729, 0.540732, 0.777325, 1.16077, 1.79616", \ - "0.18075, 0.395801, 0.506333, 0.670898, 0.926262, 1.32411, 1.9651", \ - "0.290149, 0.558286, 0.693461, 0.888505, 1.1768, 1.6103, 2.28577" \ + "0.0426282, 0.167609, 0.250905, 0.388603, 0.618402, 1.00207, 1.63995", \ + "0.0529189, 0.184939, 0.268606, 0.406378, 0.6366, 1.02014, 1.65896", \ + "0.0627936, 0.202731, 0.287566, 0.425293, 0.65541, 1.03874, 1.67727", \ + "0.0829931, 0.236464, 0.325002, 0.465186, 0.695303, 1.07765, 1.71805", \ + "0.118886, 0.29627, 0.391645, 0.540699, 0.777223, 1.16072, 1.79591", \ + "0.180736, 0.395564, 0.506304, 0.670859, 0.925814, 1.32363, 1.96497", \ + "0.290125, 0.558251, 0.69342, 0.888454, 1.17482, 1.61023, 2.28562" \ ); } rise_transition (TIMING_DELAY_7x7ds1) { index_1 ("0.0186, 0.0966, 0.174, 0.3294, 0.6408, 1.263, 2.5074"); index_2 ("0.001, 0.0468, 0.078, 0.1296, 0.216, 0.36, 0.6"); values ( \ - "0.0366122, 0.212729, 0.332566, 0.531037, 0.863423, 1.41756, 2.33983", \ - "0.0476654, 0.215595, 0.333592, 0.531743, 0.863828, 1.41757, 2.33984", \ - "0.0568497, 0.224027, 0.338983, 0.533402, 0.863829, 1.41758, 2.34075", \ - "0.0728087, 0.243818, 0.356465, 0.54562, 0.869457, 1.42215, 2.34316", \ - "0.100227, 0.280465, 0.394509, 0.581516, 0.897192, 1.43333, 2.35491", \ - "0.147582, 0.34778, 0.465136, 0.656997, 0.971405, 1.49446, 2.38206", \ - "0.23002, 0.462626, 0.595603, 0.798749, 1.11824, 1.64624, 2.51646" \ + "0.0366082, 0.212713, 0.332537, 0.530989, 0.863349, 1.41744, 2.33963", \ + "0.0476608, 0.215576, 0.33343, 0.532527, 0.863653, 1.41795, 2.34165", \ + "0.0568456, 0.224048, 0.338952, 0.533368, 0.863848, 1.41796, 2.34166", \ + "0.0727728, 0.243812, 0.356429, 0.545581, 0.869417, 1.41797, 2.34296", \ + "0.100223, 0.280444, 0.394518, 0.581474, 0.897251, 1.43345, 2.34486", \ + "0.147577, 0.346657, 0.465111, 0.656956, 0.970967, 1.49478, 2.38194", \ + "0.230014, 0.462607, 0.595575, 0.798709, 1.11991, 1.64613, 2.51629" \ ); } cell_fall (TIMING_DELAY_7x7ds1) { index_1 ("0.0186, 0.0966, 0.174, 0.3294, 0.6408, 1.263, 2.5074"); index_2 ("0.001, 0.0468, 0.078, 0.1296, 0.216, 0.36, 0.6"); values ( \ - "0.016138, 0.0445507, 0.0621507, 0.0911379, 0.139522, 0.220133, 0.354533", \ - "0.0263369, 0.0724626, 0.0949755, 0.127841, 0.178334, 0.259495, 0.393859", \ - "0.0300703, 0.0896808, 0.117077, 0.156068, 0.212792, 0.298323, 0.434015", \ - "0.0313587, 0.111634, 0.147531, 0.19672, 0.265495, 0.364006, 0.510411", \ - "0.0313597, 0.133119, 0.181168, 0.246215, 0.335722, 0.457806, 0.630431", \ - "0.0313607, 0.145145, 0.212702, 0.301673, 0.419652, 0.581881, 0.799571", \ - "0.0313617, 0.145146, 0.218996, 0.344471, 0.509965, 0.725517, 1.01708" \ + "0.0161391, 0.0445496, 0.0621529, 0.0911305, 0.139521, 0.220136, 0.354532", \ + "0.0263386, 0.0724624, 0.0949754, 0.127841, 0.178334, 0.259496, 0.39385", \ + "0.0300702, 0.0896844, 0.117077, 0.156107, 0.212774, 0.298323, 0.433998", \ + "0.0313624, 0.111634, 0.147565, 0.19672, 0.265554, 0.364086, 0.510414", \ + "0.0313634, 0.13312, 0.181169, 0.246215, 0.335722, 0.457806, 0.630431", \ + "0.0313644, 0.145148, 0.212705, 0.301675, 0.419653, 0.581893, 0.799571", \ + "0.0313654, 0.145149, 0.219005, 0.344478, 0.50997, 0.72552, 1.01708" \ ); } fall_transition (TIMING_DELAY_7x7ds1) { index_1 ("0.0186, 0.0966, 0.174, 0.3294, 0.6408, 1.263, 2.5074"); index_2 ("0.001, 0.0468, 0.078, 0.1296, 0.216, 0.36, 0.6"); values ( \ - "0.0109821, 0.0452647, 0.0694786, 0.110044, 0.17827, 0.292074, 0.481608", \ - "0.0241607, 0.062286, 0.0849153, 0.121701, 0.184932, 0.294421, 0.483333", \ - "0.0351636, 0.0785168, 0.102955, 0.140556, 0.201969, 0.306164, 0.487211", \ - "0.0544124, 0.10787, 0.1347, 0.176503, 0.240233, 0.342335, 0.51494", \ - "0.0872001, 0.158671, 0.19078, 0.237997, 0.308973, 0.417843, 0.589147", \ - "0.142059, 0.248028, 0.288391, 0.343864, 0.427579, 0.549326, 0.736183", \ - "0.237565, 0.39909, 0.458064, 0.532449, 0.632117, 0.776726, 0.987223" \ + "0.0109838, 0.0452626, 0.0695084, 0.110037, 0.17827, 0.29207, 0.481608", \ + "0.0241467, 0.062286, 0.0849153, 0.121701, 0.184932, 0.294516, 0.482263", \ + "0.0351636, 0.07855, 0.102955, 0.140634, 0.201856, 0.306164, 0.487286", \ + "0.0543887, 0.10787, 0.134875, 0.176503, 0.240135, 0.342381, 0.515064", \ + "0.0871999, 0.158671, 0.19078, 0.237997, 0.308973, 0.417843, 0.589147", \ + "0.14206, 0.248027, 0.28839, 0.343864, 0.42758, 0.549335, 0.736182", \ + "0.237565, 0.399089, 0.458062, 0.532448, 0.632115, 0.776724, 0.987289" \ ); } } @@ -24280,52 +24354,52 @@ library (sg13g2_stdcell_fast_1p65V_m40C) { index_1 ("0.0186, 0.0966, 0.174, 0.3294, 0.6408, 1.263, 2.5074"); index_2 ("0.001, 0.0468, 0.078, 0.1296, 0.216, 0.36, 0.6"); values ( \ - "0.0297166, 0.155058, 0.23861, 0.376352, 0.606224, 0.989589, 1.62808", \ - "0.0478664, 0.179615, 0.2627, 0.400168, 0.630015, 1.01339, 1.65235", \ - "0.0612084, 0.204589, 0.289154, 0.425965, 0.65506, 1.03764, 1.67607", \ - "0.0842018, 0.24743, 0.338153, 0.479163, 0.708545, 1.08934, 1.72723", \ - "0.123758, 0.316268, 0.418416, 0.573747, 0.814133, 1.19813, 1.83188", \ - "0.193582, 0.428134, 0.548259, 0.724113, 0.9929, 1.40382, 2.05018", \ - "0.318978, 0.610443, 0.75719, 0.966459, 1.27651, 1.74199, 2.44547" \ + "0.0297171, 0.155041, 0.23859, 0.376321, 0.606205, 0.989507, 1.62793", \ + "0.0478641, 0.179602, 0.262698, 0.400134, 0.629972, 1.01332, 1.65177", \ + "0.0612073, 0.204579, 0.289208, 0.425937, 0.655284, 1.03763, 1.67593", \ + "0.0841971, 0.247353, 0.338209, 0.47914, 0.708538, 1.08933, 1.72692", \ + "0.123755, 0.316253, 0.418394, 0.573715, 0.814085, 1.19805, 1.83176", \ + "0.19357, 0.428113, 0.548233, 0.724077, 0.992849, 1.40304, 2.0501", \ + "0.318958, 0.610442, 0.757148, 0.966587, 1.27645, 1.74073, 2.44595" \ ); } rise_transition (TIMING_DELAY_7x7ds1) { index_1 ("0.0186, 0.0966, 0.174, 0.3294, 0.6408, 1.263, 2.5074"); index_2 ("0.001, 0.0468, 0.078, 0.1296, 0.216, 0.36, 0.6"); values ( \ - "0.035702, 0.212612, 0.332681, 0.531195, 0.863347, 1.41726, 2.33982", \ - "0.0456099, 0.216249, 0.333762, 0.531484, 0.863348, 1.41809, 2.33987", \ - "0.0527608, 0.227569, 0.34137, 0.53425, 0.864496, 1.4181, 2.34076", \ - "0.0667697, 0.251692, 0.364963, 0.551945, 0.872147, 1.42124, 2.34316", \ - "0.0921931, 0.293356, 0.412404, 0.601036, 0.913417, 1.44217, 2.35055", \ - "0.136786, 0.365997, 0.493182, 0.69245, 1.01214, 1.53286, 2.40652", \ - "0.218567, 0.490576, 0.633158, 0.848876, 1.18855, 1.72604, 2.59678" \ + "0.0356904, 0.212593, 0.332651, 0.53115, 0.863081, 1.41714, 2.33963", \ + "0.045604, 0.216175, 0.333737, 0.531432, 0.863183, 1.41797, 2.33964", \ + "0.0527594, 0.227539, 0.341309, 0.534208, 0.864209, 1.41798, 2.34057", \ + "0.0667668, 0.251615, 0.364927, 0.551924, 0.872128, 1.42171, 2.34281", \ + "0.0921904, 0.29334, 0.412379, 0.600985, 0.913325, 1.44207, 2.35707", \ + "0.136781, 0.365981, 0.493159, 0.692411, 1.01207, 1.5322, 2.40633", \ + "0.218564, 0.490551, 0.633135, 0.849361, 1.18849, 1.72587, 2.59638" \ ); } cell_fall (TIMING_DELAY_7x7ds1) { index_1 ("0.0186, 0.0966, 0.174, 0.3294, 0.6408, 1.263, 2.5074"); index_2 ("0.001, 0.0468, 0.078, 0.1296, 0.216, 0.36, 0.6"); values ( \ - "0.0135117, 0.042396, 0.0599107, 0.0887011, 0.136894, 0.217256, 0.351122", \ - "0.0203128, 0.0694362, 0.0922327, 0.125263, 0.175755, 0.256647, 0.390507", \ - "0.0213575, 0.0856201, 0.113756, 0.153082, 0.209909, 0.295291, 0.43067", \ - "0.0213585, 0.105677, 0.142575, 0.192738, 0.262009, 0.360812, 0.506833", \ - "0.0213595, 0.123644, 0.17391, 0.240292, 0.33055, 0.453506, 0.626331", \ - "0.0213605, 0.12799, 0.198888, 0.291482, 0.411598, 0.575556, 0.79388", \ - "0.0213615, 0.127991, 0.198889, 0.323096, 0.493597, 0.712887, 1.00748" \ + "0.0135113, 0.042403, 0.0599096, 0.0886985, 0.136997, 0.217245, 0.35112", \ + "0.0203125, 0.069436, 0.0922325, 0.125258, 0.175755, 0.256641, 0.390508", \ + "0.0213572, 0.0856199, 0.113756, 0.153082, 0.209909, 0.295291, 0.430652", \ + "0.0213582, 0.105677, 0.142596, 0.192738, 0.261999, 0.360812, 0.506851", \ + "0.0213592, 0.123644, 0.173911, 0.240292, 0.33055, 0.453506, 0.626331", \ + "0.0213602, 0.127992, 0.19889, 0.291487, 0.4116, 0.575557, 0.79388", \ + "0.0213612, 0.127993, 0.198891, 0.323102, 0.493601, 0.71289, 1.00748" \ ); } fall_transition (TIMING_DELAY_7x7ds1) { index_1 ("0.0186, 0.0966, 0.174, 0.3294, 0.6408, 1.263, 2.5074"); index_2 ("0.001, 0.0468, 0.078, 0.1296, 0.216, 0.36, 0.6"); values ( \ - "0.00843959, 0.0424308, 0.0665171, 0.10685, 0.174782, 0.288037, 0.476829", \ - "0.0201207, 0.0594564, 0.0820523, 0.118662, 0.181521, 0.290494, 0.479023", \ - "0.0299412, 0.0755363, 0.0999614, 0.137634, 0.198726, 0.302415, 0.482608", \ - "0.0471178, 0.104567, 0.131666, 0.173434, 0.236698, 0.338836, 0.510627", \ - "0.0764009, 0.154499, 0.187149, 0.235326, 0.305272, 0.413677, 0.584928", \ - "0.125942, 0.242237, 0.284174, 0.339677, 0.423919, 0.545046, 0.731536", \ - "0.213294, 0.387771, 0.44959, 0.526164, 0.62726, 0.772693, 0.985454" \ + "0.00843953, 0.0424419, 0.0664575, 0.106824, 0.174842, 0.288033, 0.476829", \ + "0.0201205, 0.0594563, 0.0820523, 0.118649, 0.181537, 0.290458, 0.478426", \ + "0.0299411, 0.0755363, 0.0999615, 0.137634, 0.198726, 0.302415, 0.48249", \ + "0.0471176, 0.104567, 0.131959, 0.173434, 0.236754, 0.338836, 0.510616", \ + "0.0764004, 0.154498, 0.187149, 0.235326, 0.305215, 0.413677, 0.584928", \ + "0.125942, 0.242237, 0.284173, 0.339678, 0.423919, 0.545045, 0.731535", \ + "0.213294, 0.387771, 0.449588, 0.526157, 0.627259, 0.772689, 0.985452" \ ); } } @@ -24335,26 +24409,26 @@ library (sg13g2_stdcell_fast_1p65V_m40C) { index_1 ("0.0186, 0.0966, 0.174, 0.3294, 0.6408, 1.263, 2.5074"); index_2 ("0.001, 0.0468, 0.078, 0.1296, 0.216, 0.36, 0.6"); values ( \ - "0.0387444, 0.0398333, 0.0398228, 0.0396745, 0.0392662, 0.0385107, 0.0383419", \ - "0.0383793, 0.0389148, 0.0396654, 0.0390392, 0.0389816, 0.0383142, 0.0377334", \ - "0.0401903, 0.0394112, 0.0392721, 0.0398406, 0.0387614, 0.0382098, 0.0383506", \ - "0.0485497, 0.04369, 0.0426627, 0.0416924, 0.0403302, 0.0391589, 0.0386631", \ - "0.072454, 0.0604571, 0.0570757, 0.0532292, 0.0503823, 0.04597, 0.0451192", \ - "0.124251, 0.104701, 0.0971195, 0.0893479, 0.0797747, 0.0706517, 0.0622732", \ - "0.229948, 0.202737, 0.190508, 0.175705, 0.158181, 0.139119, 0.118361" \ + "0.0387824, 0.0398636, 0.0398213, 0.0396811, 0.039264, 0.0385038, 0.0379243", \ + "0.0383643, 0.0389345, 0.0389559, 0.0390622, 0.0387761, 0.0383132, 0.0385568", \ + "0.040193, 0.0394681, 0.0393156, 0.0395585, 0.0387161, 0.0381591, 0.0380312", \ + "0.0485449, 0.0436866, 0.0426531, 0.0414755, 0.0403252, 0.0390906, 0.0386538", \ + "0.0724542, 0.0604654, 0.0570901, 0.0532451, 0.0500874, 0.0458515, 0.0439757", \ + "0.124254, 0.104705, 0.097055, 0.0893435, 0.0796177, 0.0706678, 0.0624174", \ + "0.229948, 0.202741, 0.190524, 0.175724, 0.158182, 0.139089, 0.117916" \ ); } fall_power (POWER_7x7ds1) { index_1 ("0.0186, 0.0966, 0.174, 0.3294, 0.6408, 1.263, 2.5074"); index_2 ("0.001, 0.0468, 0.078, 0.1296, 0.216, 0.36, 0.6"); values ( \ - "0.0110753, 0.0110085, 0.0107726, 0.010595, 0.0102636, 0.00942275, 0.00829414", \ - "0.0126575, 0.0115357, 0.0110901, 0.0106804, 0.0103209, 0.00959079, 0.00848274", \ - "0.016835, 0.0135105, 0.0129001, 0.011973, 0.0108054, 0.011054, 0.00837888", \ - "0.0273618, 0.0200336, 0.0182041, 0.0162761, 0.0145983, 0.0117714, 0.0112256", \ - "0.0522093, 0.0380844, 0.0332518, 0.028711, 0.0247083, 0.0205379, 0.0158086", \ - "0.103341, 0.0820575, 0.0730846, 0.0632382, 0.0522544, 0.0428002, 0.0342506", \ - "0.208864, 0.180076, 0.165549, 0.147434, 0.127065, 0.104667, 0.0834419" \ + "0.0110643, 0.0110099, 0.0108168, 0.0106163, 0.0101399, 0.00940457, 0.00822071", \ + "0.0126403, 0.0115173, 0.011172, 0.0107895, 0.0102908, 0.00959854, 0.00842323", \ + "0.0168392, 0.01355, 0.0128244, 0.0119812, 0.0109127, 0.0111895, 0.0081787", \ + "0.0273707, 0.0200187, 0.0181904, 0.0163067, 0.0145209, 0.0116298, 0.0113991", \ + "0.052218, 0.0380866, 0.0332559, 0.028842, 0.0247283, 0.0206863, 0.0163843", \ + "0.103356, 0.0820699, 0.0730581, 0.0632536, 0.0522434, 0.0427119, 0.0341322", \ + "0.208895, 0.180097, 0.165568, 0.147458, 0.127185, 0.104584, 0.0834134" \ ); } } @@ -24364,26 +24438,26 @@ library (sg13g2_stdcell_fast_1p65V_m40C) { index_1 ("0.0186, 0.0966, 0.174, 0.3294, 0.6408, 1.263, 2.5074"); index_2 ("0.001, 0.0468, 0.078, 0.1296, 0.216, 0.36, 0.6"); values ( \ - "0.0309453, 0.0319736, 0.0319801, 0.0318282, 0.0314559, 0.0306785, 0.0305335", \ - "0.0307153, 0.0310901, 0.0317593, 0.0311931, 0.0309391, 0.0304887, 0.0306258", \ - "0.0330224, 0.0318861, 0.0317037, 0.031417, 0.0311019, 0.030306, 0.0307233", \ - "0.0418062, 0.0364936, 0.0352727, 0.0340115, 0.032691, 0.0315483, 0.0316369", \ - "0.063567, 0.0524817, 0.048842, 0.0451212, 0.0421078, 0.0378901, 0.0367026", \ - "0.109166, 0.0912851, 0.08474, 0.0773732, 0.0683801, 0.0608118, 0.0527066", \ - "0.202049, 0.176571, 0.165599, 0.152755, 0.138093, 0.120076, 0.101325" \ + "0.0309162, 0.031974, 0.0319887, 0.0318782, 0.0314517, 0.0306776, 0.0305324", \ + "0.0307125, 0.0310006, 0.0317629, 0.0311387, 0.0308987, 0.030491, 0.0309071", \ + "0.0330237, 0.0319512, 0.0317011, 0.0319288, 0.0311127, 0.0302591, 0.0306328", \ + "0.0418092, 0.036448, 0.0352579, 0.0341015, 0.032706, 0.0315005, 0.0316648", \ + "0.0635839, 0.0524832, 0.0488078, 0.0452136, 0.0422008, 0.0379788, 0.0367672", \ + "0.109174, 0.0912845, 0.0849328, 0.0773333, 0.068137, 0.0608349, 0.0517519", \ + "0.202109, 0.176591, 0.165629, 0.152767, 0.138082, 0.120068, 0.101373" \ ); } fall_power (POWER_7x7ds1) { index_1 ("0.0186, 0.0966, 0.174, 0.3294, 0.6408, 1.263, 2.5074"); index_2 ("0.001, 0.0468, 0.078, 0.1296, 0.216, 0.36, 0.6"); values ( \ - "0.010574, 0.01078, 0.0105163, 0.0102814, 0.00997137, 0.0091859, 0.00783831", \ - "0.0121213, 0.0112645, 0.0108143, 0.0105881, 0.0105731, 0.00935269, 0.00820118", \ - "0.015955, 0.0130649, 0.0126118, 0.0117181, 0.0107055, 0.0107953, 0.00829816", \ - "0.0256436, 0.0191727, 0.017481, 0.0159779, 0.0143577, 0.0117681, 0.0113317", \ - "0.0471637, 0.0354162, 0.0312795, 0.0274018, 0.0236807, 0.0199627, 0.0159112", \ - "0.0919672, 0.0744286, 0.0667292, 0.0583664, 0.0488597, 0.0403423, 0.0328962", \ - "0.184463, 0.159912, 0.148113, 0.133173, 0.115847, 0.0965323, 0.0786899" \ + "0.0105739, 0.010717, 0.0104757, 0.0102825, 0.00987021, 0.00918099, 0.00783528", \ + "0.0121081, 0.0112772, 0.0108286, 0.0105985, 0.0101264, 0.00930211, 0.00781401", \ + "0.0159528, 0.013083, 0.012622, 0.0118938, 0.0106743, 0.0104158, 0.00829861", \ + "0.0256407, 0.0191376, 0.0175296, 0.015965, 0.014378, 0.0118155, 0.0111796", \ + "0.0471198, 0.0354179, 0.0312823, 0.0274018, 0.0236784, 0.019961, 0.0158778", \ + "0.0919685, 0.074397, 0.0667322, 0.0583692, 0.0488649, 0.0403628, 0.0328969", \ + "0.184426, 0.159972, 0.14812, 0.133121, 0.115852, 0.0965362, 0.0786919" \ ); } } @@ -24393,26 +24467,26 @@ library (sg13g2_stdcell_fast_1p65V_m40C) { index_1 ("0.0186, 0.0966, 0.174, 0.3294, 0.6408, 1.263, 2.5074"); index_2 ("0.001, 0.0468, 0.078, 0.1296, 0.216, 0.36, 0.6"); values ( \ - "0.023049, 0.0241724, 0.0241537, 0.0240032, 0.0236086, 0.0228417, 0.0230293", \ - "0.0236932, 0.0234521, 0.0235181, 0.0235752, 0.0232429, 0.0225973, 0.0224727", \ - "0.027113, 0.0249431, 0.0244412, 0.0245069, 0.0234035, 0.0227411, 0.0227326", \ - "0.0363098, 0.0303184, 0.0288163, 0.0270559, 0.025648, 0.0247338, 0.0245192", \ - "0.0562669, 0.0456225, 0.0420821, 0.0382784, 0.0351495, 0.030789, 0.0293146", \ - "0.0975763, 0.0808875, 0.0746003, 0.0676959, 0.0595971, 0.0521036, 0.0430331", \ - "0.181706, 0.157354, 0.147574, 0.135903, 0.121942, 0.106517, 0.0889934" \ + "0.0230658, 0.0241685, 0.0241549, 0.0240274, 0.023608, 0.022843, 0.0226701", \ + "0.0237003, 0.0234859, 0.0235375, 0.023777, 0.0232975, 0.0226632, 0.02283", \ + "0.0271079, 0.0248477, 0.0242874, 0.0244588, 0.0234691, 0.0227381, 0.0227249", \ + "0.0363014, 0.0302377, 0.0287843, 0.0270433, 0.0255108, 0.0239799, 0.0241558", \ + "0.0562787, 0.0456441, 0.0421355, 0.0382803, 0.0349214, 0.0311853, 0.0278463", \ + "0.0975792, 0.0807144, 0.0745939, 0.0677276, 0.0598883, 0.0519369, 0.0433506", \ + "0.181705, 0.157353, 0.147576, 0.135911, 0.121494, 0.106377, 0.0889707" \ ); } fall_power (POWER_7x7ds1) { index_1 ("0.0186, 0.0966, 0.174, 0.3294, 0.6408, 1.263, 2.5074"); index_2 ("0.001, 0.0468, 0.078, 0.1296, 0.216, 0.36, 0.6"); values ( \ - "0.0088427, 0.0093864, 0.00927084, 0.00898855, 0.00857515, 0.00788832, 0.00669765", \ - "0.0107425, 0.01022, 0.00995035, 0.00958251, 0.00954907, 0.0083941, 0.00804928", \ - "0.0144181, 0.0119704, 0.0115711, 0.0108086, 0.00983468, 0.00960954, 0.00724555", \ - "0.0234072, 0.0175489, 0.0160805, 0.0148174, 0.0131618, 0.0105676, 0.0103209", \ - "0.0431512, 0.0325352, 0.0289096, 0.0255108, 0.0221068, 0.0186818, 0.0143622", \ - "0.0837515, 0.0676773, 0.0613369, 0.0539245, 0.0455517, 0.0382096, 0.0311744", \ - "0.167403, 0.14546, 0.135093, 0.121921, 0.106547, 0.0892617, 0.0727228" \ + "0.00884443, 0.00940544, 0.00934785, 0.00899045, 0.00857364, 0.00793154, 0.00670061", \ + "0.0107349, 0.0102198, 0.00994277, 0.00958259, 0.00953391, 0.00845641, 0.00726633", \ + "0.0144257, 0.0120255, 0.0115819, 0.0108966, 0.00973906, 0.0101679, 0.00730731", \ + "0.0234056, 0.0175463, 0.0161657, 0.0148173, 0.0134006, 0.0107276, 0.010515", \ + "0.0431513, 0.0325374, 0.0289302, 0.025457, 0.0221072, 0.0186307, 0.0144269", \ + "0.0837569, 0.0676801, 0.061338, 0.0539199, 0.0455765, 0.0382179, 0.0311756", \ + "0.167414, 0.145467, 0.135097, 0.121926, 0.106553, 0.089263, 0.0727706" \ ); } } @@ -24422,26 +24496,26 @@ library (sg13g2_stdcell_fast_1p65V_m40C) { index_1 ("0.0186, 0.0966, 0.174, 0.3294, 0.6408, 1.263, 2.5074"); index_2 ("0.001, 0.0468, 0.078, 0.1296, 0.216, 0.36, 0.6"); values ( \ - "0.0142245, 0.0156453, 0.0157616, 0.0157452, 0.015358, 0.0145856, 0.0143952", \ - "0.0177052, 0.015927, 0.0164246, 0.0155838, 0.0151232, 0.0145256, 0.0144731", \ - "0.0221898, 0.0186018, 0.0174999, 0.0171854, 0.0159346, 0.0148281, 0.0147956", \ - "0.0317857, 0.0251313, 0.0232707, 0.0209536, 0.0191962, 0.0173837, 0.0165424", \ - "0.0518091, 0.0411245, 0.0374356, 0.0335225, 0.0299507, 0.0253944, 0.0217408", \ - "0.0927289, 0.0761924, 0.0704209, 0.0633285, 0.0548063, 0.0465652, 0.0381768", \ - "0.176608, 0.152638, 0.143124, 0.13173, 0.117969, 0.102408, 0.085171" \ + "0.0142309, 0.0156433, 0.0157616, 0.0157329, 0.0153217, 0.0145457, 0.014394", \ + "0.0176976, 0.0159877, 0.0163906, 0.0155911, 0.0151865, 0.0145263, 0.0142918", \ + "0.0221921, 0.0186058, 0.0175966, 0.0171537, 0.0159526, 0.0147515, 0.0147872", \ + "0.0317889, 0.0252356, 0.0232645, 0.0209762, 0.0191913, 0.0174033, 0.0165136", \ + "0.051812, 0.0411381, 0.0374818, 0.0335318, 0.0299693, 0.024709, 0.0224223", \ + "0.0927448, 0.0761925, 0.0704231, 0.0633547, 0.0551254, 0.0470729, 0.0378375", \ + "0.17661, 0.152645, 0.143154, 0.131835, 0.117995, 0.102115, 0.0855758" \ ); } fall_power (POWER_7x7ds1) { index_1 ("0.0186, 0.0966, 0.174, 0.3294, 0.6408, 1.263, 2.5074"); index_2 ("0.001, 0.0468, 0.078, 0.1296, 0.216, 0.36, 0.6"); values ( \ - "0.00681903, 0.0083051, 0.00825368, 0.00804138, 0.0077129, 0.00707546, 0.00572536", \ - "0.009508, 0.00916237, 0.00890239, 0.00875655, 0.00933085, 0.00739491, 0.00786093", \ - "0.0133991, 0.010932, 0.0105876, 0.0100563, 0.00900627, 0.00899998, 0.00672576", \ - "0.0226221, 0.0163336, 0.0149618, 0.0138146, 0.0123409, 0.010142, 0.00968924", \ - "0.0424085, 0.0308527, 0.0272581, 0.0240894, 0.0203187, 0.0175174, 0.013885", \ - "0.0831079, 0.0655168, 0.0587079, 0.050947, 0.0427027, 0.0358369, 0.0292685", \ - "0.165675, 0.14148, 0.130909, 0.117196, 0.101744, 0.0842538, 0.0697124" \ + "0.00682154, 0.0084115, 0.00829844, 0.00797623, 0.0077534, 0.00706722, 0.00572286", \ + "0.00950724, 0.00916234, 0.00889238, 0.0087351, 0.00909652, 0.00738745, 0.00726637", \ + "0.0133987, 0.0109326, 0.0105873, 0.0100564, 0.00900624, 0.00930247, 0.00660997", \ + "0.0226237, 0.0163321, 0.0151235, 0.01382, 0.0123638, 0.0101421, 0.00957835", \ + "0.0424092, 0.0308541, 0.0272596, 0.0240904, 0.02034, 0.0175179, 0.0138851", \ + "0.0830955, 0.0655188, 0.0587087, 0.0509511, 0.042719, 0.0358381, 0.0292655", \ + "0.166003, 0.141487, 0.130915, 0.117201, 0.101753, 0.0842953, 0.0697165" \ ); } } @@ -24449,74 +24523,74 @@ library (sg13g2_stdcell_fast_1p65V_m40C) { pin (A) { direction : "input"; max_transition : 2.5074; - capacitance : 0.00653059; - rise_capacitance : 0.00624571; - rise_capacitance_range (0.00624571, 0.00624571); - fall_capacitance : 0.00681546; - fall_capacitance_range (0.00681546, 0.00681546); + capacitance : 0.00653379; + rise_capacitance : 0.0062492; + rise_capacitance_range (0.00582144, 0.00745107); + fall_capacitance : 0.00681838; + fall_capacitance_range (0.0056675, 0.00748586); } pin (B) { direction : "input"; max_transition : 2.5074; - capacitance : 0.00642794; - rise_capacitance : 0.00635376; - rise_capacitance_range (0.00635376, 0.00635376); - fall_capacitance : 0.00650213; - fall_capacitance_range (0.00650213, 0.00650213); + capacitance : 0.00642812; + rise_capacitance : 0.00635397; + rise_capacitance_range (0.0055607, 0.00827755); + fall_capacitance : 0.00650228; + fall_capacitance_range (0.0054254, 0.00699784); } pin (C) { direction : "input"; max_transition : 2.5074; capacitance : 0.0063592; - rise_capacitance : 0.00645203; - rise_capacitance_range (0.00645203, 0.00645203); - fall_capacitance : 0.00626637; - fall_capacitance_range (0.00626637, 0.00626637); + rise_capacitance : 0.00645201; + rise_capacitance_range (0.00534696, 0.00915912); + fall_capacitance : 0.00626639; + fall_capacitance_range (0.00532799, 0.0066242); } pin (D) { direction : "input"; max_transition : 2.5074; capacitance : 0.00612564; rise_capacitance : 0.00658368; - rise_capacitance_range (0.00658368, 0.00658368); + rise_capacitance_range (0.00508135, 0.0103989); fall_capacitance : 0.0056676; - fall_capacitance_range (0.0056676, 0.0056676); + fall_capacitance_range (0.00535656, 0.00587753); } } cell (sg13g2_o21ai_1) { area : 9.072; cell_footprint : "o21ai"; - cell_leakage_power : 1609.38; + cell_leakage_power : 1609.4; leakage_power () { - value : 629.352; + value : 629.368; when : "!A1&!A2&!B1&Y"; } leakage_power () { - value : 1367.99; + value : 1368; when : "A1&!A2&!B1&Y"; } leakage_power () { - value : 1368; + value : 1368.01; when : "!A1&A2&!B1&Y"; } leakage_power () { - value : 2099.39; + value : 2099.41; when : "A1&A2&!B1&Y"; } leakage_power () { - value : 444.842; + value : 444.858; when : "!A1&!A2&B1&Y"; } leakage_power () { - value : 1939.46; + value : 1939.47; when : "A1&!A2&B1&!Y"; } leakage_power () { - value : 2154.62; + value : 2154.63; when : "!A1&A2&B1&!Y"; } leakage_power () { - value : 2871.41; + value : 2871.42; when : "A1&A2&B1&!Y"; } pin (Y) { @@ -24532,52 +24606,52 @@ library (sg13g2_stdcell_fast_1p65V_m40C) { index_1 ("0.0186, 0.0966, 0.174, 0.3294, 0.6408, 1.263, 2.5074"); index_2 ("0.001, 0.0234, 0.039, 0.0648, 0.108, 0.18, 0.3"); values ( \ - "0.0344315, 0.108314, 0.15872, 0.24202, 0.381006, 0.612782, 0.999151", \ - "0.046849, 0.127972, 0.179063, 0.262407, 0.401756, 0.633297, 1.01973", \ - "0.0551051, 0.144138, 0.197484, 0.282329, 0.42162, 0.653407, 1.03944", \ - "0.0703811, 0.171442, 0.229566, 0.318729, 0.461514, 0.694077, 1.07989", \ - "0.0962275, 0.216035, 0.281703, 0.379531, 0.532812, 0.773508, 1.16243", \ - "0.136979, 0.285964, 0.364608, 0.478762, 0.648511, 0.909783, 1.31776", \ - "0.204662, 0.396551, 0.491824, 0.631493, 0.833739, 1.13278, 1.57925" \ + "0.0344352, 0.108346, 0.158716, 0.242021, 0.381021, 0.612786, 0.999299", \ + "0.0468494, 0.127976, 0.179065, 0.262407, 0.401517, 0.633439, 1.01974", \ + "0.0551056, 0.144139, 0.197477, 0.282331, 0.421629, 0.653293, 1.03943", \ + "0.0703818, 0.171443, 0.229567, 0.318729, 0.461485, 0.69407, 1.0799", \ + "0.0962286, 0.216032, 0.281705, 0.379533, 0.532816, 0.773514, 1.16239", \ + "0.136981, 0.286114, 0.364611, 0.478779, 0.648515, 0.909789, 1.31777", \ + "0.204665, 0.396554, 0.491704, 0.631497, 0.833745, 1.13279, 1.57926" \ ); } rise_transition (TIMING_DELAY_7x7ds1) { index_1 ("0.0186, 0.0966, 0.174, 0.3294, 0.6408, 1.263, 2.5074"); index_2 ("0.001, 0.0234, 0.039, 0.0648, 0.108, 0.18, 0.3"); values ( \ - "0.0258565, 0.130728, 0.203661, 0.324493, 0.526447, 0.863107, 1.42408", \ - "0.036197, 0.135596, 0.206253, 0.325192, 0.526952, 0.863108, 1.42414", \ - "0.0462726, 0.145634, 0.214489, 0.330311, 0.528498, 0.863348, 1.42415", \ - "0.0628706, 0.167321, 0.235544, 0.348276, 0.540866, 0.868944, 1.42817", \ - "0.0903809, 0.206642, 0.277726, 0.390546, 0.57965, 0.89789, 1.44076", \ - "0.138464, 0.276308, 0.354668, 0.471673, 0.663151, 0.97839, 1.50598", \ - "0.217788, 0.392029, 0.484196, 0.620108, 0.822146, 1.14787, 1.67375" \ + "0.0258572, 0.130797, 0.203646, 0.324495, 0.526427, 0.863115, 1.42415", \ + "0.0361973, 0.135602, 0.206255, 0.325167, 0.526428, 0.863116, 1.42416", \ + "0.0462728, 0.145635, 0.214492, 0.330314, 0.528462, 0.863819, 1.42417", \ + "0.0628702, 0.167322, 0.235546, 0.34828, 0.540826, 0.869047, 1.42818", \ + "0.0903809, 0.206632, 0.277728, 0.390549, 0.579655, 0.897898, 1.44072", \ + "0.138464, 0.276284, 0.35467, 0.471766, 0.663155, 0.978398, 1.50599", \ + "0.217788, 0.392031, 0.484633, 0.62011, 0.822151, 1.14787, 1.67343" \ ); } cell_fall (TIMING_DELAY_7x7ds1) { index_1 ("0.0186, 0.0966, 0.174, 0.3294, 0.6408, 1.263, 2.5074"); index_2 ("0.001, 0.0234, 0.039, 0.0648, 0.108, 0.18, 0.3"); values ( \ - "0.0251102, 0.0736848, 0.106346, 0.160217, 0.250332, 0.400476, 0.650391", \ - "0.0341283, 0.0925865, 0.127086, 0.181899, 0.272304, 0.422372, 0.672392", \ - "0.0386175, 0.106786, 0.144282, 0.202083, 0.294382, 0.445022, 0.695187", \ - "0.0429825, 0.127144, 0.170798, 0.234664, 0.333398, 0.488832, 0.740817", \ - "0.0435014, 0.15179, 0.203968, 0.280112, 0.39129, 0.560737, 0.823126", \ - "0.0435024, 0.176552, 0.24524, 0.339399, 0.473047, 0.669096, 0.957264", \ - "0.0435034, 0.193153, 0.28327, 0.406545, 0.577715, 0.812058, 1.15321" \ + "0.0251108, 0.0736744, 0.106351, 0.16022, 0.250309, 0.400359, 0.650396", \ + "0.0341283, 0.0925864, 0.127086, 0.181899, 0.272304, 0.422352, 0.672458", \ + "0.0386175, 0.106786, 0.144282, 0.202083, 0.294384, 0.445022, 0.695182", \ + "0.0429823, 0.127144, 0.170798, 0.234664, 0.333398, 0.488789, 0.740843", \ + "0.0434466, 0.15179, 0.203968, 0.280112, 0.39129, 0.560735, 0.823149", \ + "0.0434476, 0.176551, 0.245239, 0.339398, 0.473047, 0.669095, 0.957263", \ + "0.0434486, 0.193152, 0.283269, 0.406543, 0.577714, 0.812057, 1.15321" \ ); } fall_transition (TIMING_DELAY_7x7ds1) { index_1 ("0.0186, 0.0966, 0.174, 0.3294, 0.6408, 1.263, 2.5074"); index_2 ("0.001, 0.0234, 0.039, 0.0648, 0.108, 0.18, 0.3"); values ( \ - "0.0163717, 0.0813679, 0.127071, 0.202698, 0.329333, 0.540315, 0.891186", \ - "0.0266661, 0.0891196, 0.132416, 0.205546, 0.330036, 0.540316, 0.891728", \ - "0.0378322, 0.099943, 0.143021, 0.214074, 0.33558, 0.542333, 0.892204", \ - "0.0582635, 0.123327, 0.165936, 0.236265, 0.354588, 0.555583, 0.898009", \ - "0.0925731, 0.167999, 0.211596, 0.281707, 0.399692, 0.59636, 0.928475", \ - "0.149761, 0.250266, 0.297508, 0.371921, 0.490461, 0.688066, 1.01478", \ - "0.249359, 0.391794, 0.454283, 0.539935, 0.667109, 0.870147, 1.19559" \ + "0.0163703, 0.081296, 0.127074, 0.202701, 0.329333, 0.539884, 0.891185", \ + "0.026666, 0.0891194, 0.132427, 0.205546, 0.330036, 0.540132, 0.891263", \ + "0.0378322, 0.0999422, 0.143021, 0.214007, 0.335533, 0.542426, 0.892199", \ + "0.0582635, 0.123327, 0.165936, 0.236264, 0.354588, 0.555538, 0.898125", \ + "0.0924764, 0.167999, 0.211596, 0.281707, 0.399668, 0.596359, 0.928417", \ + "0.149761, 0.250266, 0.297507, 0.371921, 0.490461, 0.688066, 1.01478", \ + "0.249359, 0.391794, 0.454283, 0.539935, 0.667109, 0.870148, 1.19559" \ ); } } @@ -24589,52 +24663,52 @@ library (sg13g2_stdcell_fast_1p65V_m40C) { index_1 ("0.0186, 0.0966, 0.174, 0.3294, 0.6408, 1.263, 2.5074"); index_2 ("0.001, 0.0234, 0.039, 0.0648, 0.108, 0.18, 0.3"); values ( \ - "0.0307354, 0.10517, 0.155629, 0.238861, 0.378165, 0.610081, 0.996487", \ - "0.0494829, 0.135473, 0.186865, 0.270158, 0.409355, 0.64279, 1.0272", \ - "0.0625724, 0.160477, 0.215795, 0.301361, 0.440699, 0.672176, 1.05815", \ - "0.0840015, 0.199834, 0.263259, 0.357788, 0.503228, 0.736279, 1.12184", \ - "0.119994, 0.261741, 0.336051, 0.446016, 0.610026, 0.858516, 1.24987", \ - "0.181725, 0.357289, 0.449373, 0.581804, 0.773594, 1.05874, 1.48574", \ - "0.289466, 0.511891, 0.62683, 0.789958, 1.02605, 1.36433, 1.8604" \ + "0.0307365, 0.10519, 0.155618, 0.238866, 0.377998, 0.610088, 0.996496", \ + "0.0494832, 0.135474, 0.186866, 0.270133, 0.409203, 0.640805, 1.0272", \ + "0.0625727, 0.160477, 0.215796, 0.301363, 0.440703, 0.672219, 1.05816", \ + "0.0840019, 0.199835, 0.263267, 0.35779, 0.503261, 0.736283, 1.12152", \ + "0.119995, 0.261743, 0.336053, 0.446023, 0.610031, 0.858528, 1.24988", \ + "0.181727, 0.357291, 0.449375, 0.581805, 0.773598, 1.05874, 1.48592", \ + "0.289468, 0.511894, 0.626833, 0.789962, 1.02606, 1.36433, 1.86032" \ ); } rise_transition (TIMING_DELAY_7x7ds1) { index_1 ("0.0186, 0.0966, 0.174, 0.3294, 0.6408, 1.263, 2.5074"); index_2 ("0.001, 0.0234, 0.039, 0.0648, 0.108, 0.18, 0.3"); values ( \ - "0.0264463, 0.130603, 0.203567, 0.324352, 0.526465, 0.863226, 1.42425", \ - "0.0395087, 0.138862, 0.207929, 0.325677, 0.526489, 0.864651, 1.42426", \ - "0.0492318, 0.154169, 0.221248, 0.334374, 0.530165, 0.864652, 1.42427", \ - "0.064791, 0.183041, 0.251743, 0.362905, 0.550138, 0.872712, 1.42663", \ - "0.0907081, 0.229941, 0.306425, 0.422816, 0.609863, 0.919769, 1.45158", \ - "0.134425, 0.306931, 0.39501, 0.525181, 0.725544, 1.04171, 1.55707", \ - "0.212043, 0.429677, 0.537783, 0.693893, 0.92182, 1.26475, 1.79769" \ + "0.0264461, 0.130601, 0.203558, 0.324355, 0.52645, 0.863234, 1.42426", \ + "0.0395088, 0.138863, 0.207931, 0.325664, 0.526557, 0.863235, 1.42427", \ + "0.0492319, 0.154166, 0.22125, 0.334316, 0.530186, 0.863355, 1.42428", \ + "0.0647929, 0.183042, 0.251563, 0.362907, 0.550178, 0.872719, 1.43074", \ + "0.0907082, 0.229943, 0.306426, 0.422822, 0.609906, 0.919758, 1.45159", \ + "0.134423, 0.306933, 0.395012, 0.525186, 0.725548, 1.04172, 1.5572", \ + "0.212043, 0.429677, 0.537781, 0.693895, 0.921823, 1.26476, 1.79764" \ ); } cell_fall (TIMING_DELAY_7x7ds1) { index_1 ("0.0186, 0.0966, 0.174, 0.3294, 0.6408, 1.263, 2.5074"); index_2 ("0.001, 0.0234, 0.039, 0.0648, 0.108, 0.18, 0.3"); values ( \ - "0.0208107, 0.0697418, 0.10221, 0.155647, 0.245152, 0.39412, 0.642308", \ - "0.0268681, 0.0880967, 0.122743, 0.177392, 0.267205, 0.416361, 0.664718", \ - "0.0283542, 0.101477, 0.139459, 0.197365, 0.289332, 0.439089, 0.687561", \ - "0.0283552, 0.119966, 0.164411, 0.229098, 0.328073, 0.482949, 0.733396", \ - "0.0283562, 0.139385, 0.194595, 0.27255, 0.385086, 0.554199, 0.816104", \ - "0.0283572, 0.151677, 0.225613, 0.324517, 0.462101, 0.659553, 0.949846", \ - "0.0283582, 0.151678, 0.237675, 0.37113, 0.55112, 0.794078, 1.14138" \ + "0.0208104, 0.0697411, 0.102172, 0.155644, 0.245077, 0.394119, 0.642307", \ + "0.0268681, 0.0880966, 0.122743, 0.177392, 0.267204, 0.416362, 0.664717", \ + "0.0283542, 0.101477, 0.139459, 0.197365, 0.289369, 0.439104, 0.687548", \ + "0.0283552, 0.119966, 0.164411, 0.229098, 0.328074, 0.482948, 0.733401", \ + "0.0283562, 0.139385, 0.194595, 0.272549, 0.385086, 0.554198, 0.816064", \ + "0.0283572, 0.151676, 0.225613, 0.324516, 0.4622, 0.659552, 0.949845", \ + "0.0283582, 0.151677, 0.237673, 0.371129, 0.551118, 0.794076, 1.14138" \ ); } fall_transition (TIMING_DELAY_7x7ds1) { index_1 ("0.0186, 0.0966, 0.174, 0.3294, 0.6408, 1.263, 2.5074"); index_2 ("0.001, 0.0234, 0.039, 0.0648, 0.108, 0.18, 0.3"); values ( \ - "0.0111699, 0.0752195, 0.120469, 0.195396, 0.320915, 0.530381, 0.879136", \ - "0.0213349, 0.0832012, 0.126017, 0.198419, 0.322076, 0.530566, 0.879137", \ - "0.0316897, 0.0940153, 0.136637, 0.207149, 0.327571, 0.532593, 0.879499", \ - "0.0506984, 0.117318, 0.15934, 0.22952, 0.346888, 0.545972, 0.88583", \ - "0.0816384, 0.16174, 0.205346, 0.276471, 0.392336, 0.586889, 0.916404", \ - "0.131689, 0.242948, 0.291808, 0.365631, 0.484133, 0.679229, 1.004", \ - "0.216484, 0.37309, 0.443888, 0.534153, 0.661681, 0.864389, 1.18917" \ + "0.0111703, 0.0751793, 0.120703, 0.195396, 0.32107, 0.53038, 0.878434", \ + "0.0213348, 0.083201, 0.126016, 0.198373, 0.322077, 0.530381, 0.879128", \ + "0.0316897, 0.0940089, 0.136637, 0.207149, 0.327609, 0.532383, 0.879481", \ + "0.0506983, 0.117318, 0.15934, 0.229519, 0.34675, 0.545971, 0.885836", \ + "0.0816383, 0.16174, 0.205346, 0.276471, 0.392337, 0.586888, 0.91645", \ + "0.131689, 0.242949, 0.291807, 0.365631, 0.484189, 0.679228, 1.004", \ + "0.216483, 0.37309, 0.443889, 0.534153, 0.661681, 0.864389, 1.18917" \ ); } } @@ -24648,52 +24722,52 @@ library (sg13g2_stdcell_fast_1p65V_m40C) { index_1 ("0.0186, 0.0966, 0.174, 0.3294, 0.6408, 1.263, 2.5074"); index_2 ("0.001, 0.0234, 0.039, 0.0648, 0.108, 0.18, 0.3"); values ( \ - "0.0148562, 0.0542753, 0.0797022, 0.121588, 0.191624, 0.308231, 0.502856", \ - "0.0251879, 0.0846492, 0.114197, 0.158474, 0.229243, 0.346075, 0.540532", \ - "0.0310154, 0.104167, 0.139425, 0.18963, 0.264688, 0.383118, 0.577655", \ - "0.0389345, 0.132421, 0.176144, 0.237323, 0.324598, 0.453009, 0.652127", \ - "0.0494505, 0.170304, 0.227139, 0.304988, 0.412619, 0.565406, 0.7869", \ - "0.0620699, 0.222107, 0.294724, 0.396019, 0.535524, 0.72693, 0.996026", \ - "0.077112, 0.291344, 0.386113, 0.516333, 0.698206, 0.949861, 1.29035" \ + "0.014856, 0.054273, 0.0797017, 0.121597, 0.191621, 0.30823, 0.502847", \ + "0.0251876, 0.0846482, 0.114195, 0.158472, 0.22924, 0.34604, 0.540442", \ + "0.031015, 0.104166, 0.139424, 0.189628, 0.264685, 0.38307, 0.577578", \ + "0.038934, 0.13242, 0.176142, 0.237321, 0.324595, 0.453004, 0.652113", \ + "0.0494496, 0.170302, 0.227137, 0.304985, 0.412615, 0.5654, 0.786918", \ + "0.0620685, 0.222161, 0.294723, 0.396016, 0.535519, 0.726923, 0.996016", \ + "0.0771095, 0.291341, 0.386109, 0.516326, 0.698199, 0.949853, 1.29034" \ ); } rise_transition (TIMING_DELAY_7x7ds1) { index_1 ("0.0186, 0.0966, 0.174, 0.3294, 0.6408, 1.263, 2.5074"); index_2 ("0.001, 0.0234, 0.039, 0.0648, 0.108, 0.18, 0.3"); values ( \ - "0.0105989, 0.0618673, 0.0993279, 0.161439, 0.265551, 0.438969, 0.728064", \ - "0.0229814, 0.0772686, 0.111093, 0.168288, 0.2682, 0.440164, 0.72811", \ - "0.0317325, 0.0943128, 0.129078, 0.184938, 0.279945, 0.445074, 0.729351", \ - "0.0473713, 0.123017, 0.162337, 0.220766, 0.314559, 0.471353, 0.74387", \ - "0.0731631, 0.170543, 0.217245, 0.284661, 0.385586, 0.542708, 0.802753", \ - "0.117691, 0.244134, 0.305085, 0.38906, 0.505642, 0.679933, 0.947103", \ - "0.197971, 0.366442, 0.444775, 0.549704, 0.699136, 0.910352, 1.21203" \ + "0.0105987, 0.0618661, 0.0993262, 0.161472, 0.265548, 0.438961, 0.728051", \ + "0.0229819, 0.0772674, 0.111091, 0.168285, 0.268197, 0.439313, 0.728052", \ + "0.0317324, 0.0943115, 0.129077, 0.184935, 0.27994, 0.445061, 0.729293", \ + "0.0473711, 0.123006, 0.162335, 0.220764, 0.314555, 0.47133, 0.743862", \ + "0.073163, 0.170542, 0.217243, 0.284658, 0.385581, 0.542701, 0.802737", \ + "0.117691, 0.243842, 0.305105, 0.389057, 0.505638, 0.679926, 0.947087", \ + "0.19797, 0.366441, 0.444773, 0.549717, 0.699131, 0.910347, 1.21202" \ ); } cell_fall (TIMING_DELAY_7x7ds1) { index_1 ("0.0186, 0.0966, 0.174, 0.3294, 0.6408, 1.263, 2.5074"); index_2 ("0.001, 0.0234, 0.039, 0.0648, 0.108, 0.18, 0.3"); values ( \ - "0.0168906, 0.0664112, 0.0988883, 0.15237, 0.241754, 0.390771, 0.6392", \ - "0.0259136, 0.0936295, 0.12955, 0.18471, 0.274479, 0.423413, 0.671617", \ - "0.0316666, 0.112646, 0.15386, 0.21442, 0.307688, 0.457404, 0.705468", \ - "0.0394979, 0.140194, 0.18972, 0.260558, 0.365179, 0.523481, 0.774955", \ - "0.0472441, 0.176053, 0.236595, 0.323295, 0.447331, 0.628534, 0.899164", \ - "0.055715, 0.224209, 0.301271, 0.407944, 0.561603, 0.778391, 1.09363", \ - "0.0629573, 0.283973, 0.385022, 0.524083, 0.714335, 0.985432, 1.36784" \ + "0.0168881, 0.0664168, 0.0988838, 0.152365, 0.241885, 0.39079, 0.63901", \ + "0.0259136, 0.0936294, 0.12955, 0.184714, 0.274477, 0.423518, 0.671624", \ + "0.0316666, 0.112641, 0.153855, 0.21442, 0.307687, 0.457427, 0.70552", \ + "0.039498, 0.140194, 0.18972, 0.26059, 0.365179, 0.523589, 0.774943", \ + "0.0472444, 0.176053, 0.236595, 0.323295, 0.447331, 0.628533, 0.899163", \ + "0.0557158, 0.22421, 0.301272, 0.407944, 0.561603, 0.778391, 1.09378", \ + "0.0629593, 0.283974, 0.385023, 0.524084, 0.714335, 0.985432, 1.36784" \ ); } fall_transition (TIMING_DELAY_7x7ds1) { index_1 ("0.0186, 0.0966, 0.174, 0.3294, 0.6408, 1.263, 2.5074"); index_2 ("0.001, 0.0234, 0.039, 0.0648, 0.108, 0.18, 0.3"); values ( \ - "0.0123262, 0.075282, 0.120529, 0.195537, 0.32106, 0.53008, 0.878769", \ - "0.0238933, 0.0889902, 0.130448, 0.200825, 0.322623, 0.530487, 0.878953", \ - "0.0335273, 0.104611, 0.147104, 0.215913, 0.332728, 0.534536, 0.879636", \ - "0.0502592, 0.131916, 0.177892, 0.249275, 0.364443, 0.55779, 0.891159", \ - "0.0786386, 0.179259, 0.230462, 0.308453, 0.429821, 0.622902, 0.943753", \ - "0.127434, 0.25952, 0.31885, 0.408964, 0.542446, 0.750526, 1.07617", \ - "0.214693, 0.396072, 0.474699, 0.578067, 0.733913, 0.967756, 1.32119" \ + "0.0123241, 0.0752768, 0.120912, 0.195533, 0.320983, 0.530079, 0.879096", \ + "0.0238933, 0.0889902, 0.130448, 0.200791, 0.322617, 0.530751, 0.879097", \ + "0.0335273, 0.104481, 0.147143, 0.215912, 0.332728, 0.534534, 0.879212", \ + "0.0502591, 0.131916, 0.177892, 0.249348, 0.364442, 0.557944, 0.89115", \ + "0.0786385, 0.179258, 0.230462, 0.308452, 0.429821, 0.622901, 0.943752", \ + "0.127434, 0.259518, 0.318851, 0.408963, 0.542446, 0.750526, 1.0756", \ + "0.214692, 0.396071, 0.474699, 0.578065, 0.733913, 0.967754, 1.32119" \ ); } } @@ -24705,52 +24779,52 @@ library (sg13g2_stdcell_fast_1p65V_m40C) { index_1 ("0.0186, 0.0966, 0.174, 0.3294, 0.6408, 1.263, 2.5074"); index_2 ("0.001, 0.0234, 0.039, 0.0648, 0.108, 0.18, 0.3"); values ( \ - "0.0148562, 0.0542753, 0.0797022, 0.121588, 0.191624, 0.308231, 0.502856", \ - "0.0251879, 0.0846492, 0.114197, 0.158474, 0.229243, 0.346075, 0.540532", \ - "0.0310154, 0.104167, 0.139425, 0.18963, 0.264688, 0.383118, 0.577655", \ - "0.0389345, 0.132421, 0.176144, 0.237323, 0.324598, 0.453009, 0.652127", \ - "0.0494505, 0.170304, 0.227139, 0.304988, 0.412619, 0.565406, 0.7869", \ - "0.0620699, 0.222107, 0.294724, 0.396019, 0.535524, 0.72693, 0.996026", \ - "0.077112, 0.291344, 0.386113, 0.516333, 0.698206, 0.949861, 1.29035" \ + "0.014856, 0.054273, 0.0797017, 0.121597, 0.191621, 0.30823, 0.502847", \ + "0.0251876, 0.0846482, 0.114195, 0.158472, 0.22924, 0.34604, 0.540442", \ + "0.031015, 0.104166, 0.139424, 0.189628, 0.264685, 0.38307, 0.577578", \ + "0.038934, 0.13242, 0.176142, 0.237321, 0.324595, 0.453004, 0.652113", \ + "0.0494496, 0.170302, 0.227137, 0.304985, 0.412615, 0.5654, 0.786918", \ + "0.0620685, 0.222161, 0.294723, 0.396016, 0.535519, 0.726923, 0.996016", \ + "0.0771095, 0.291341, 0.386109, 0.516326, 0.698199, 0.949853, 1.29034" \ ); } rise_transition (TIMING_DELAY_7x7ds1) { index_1 ("0.0186, 0.0966, 0.174, 0.3294, 0.6408, 1.263, 2.5074"); index_2 ("0.001, 0.0234, 0.039, 0.0648, 0.108, 0.18, 0.3"); values ( \ - "0.0105989, 0.0618673, 0.0993279, 0.161439, 0.265551, 0.438969, 0.728064", \ - "0.0229814, 0.0772686, 0.111093, 0.168288, 0.2682, 0.440164, 0.72811", \ - "0.0317325, 0.0943128, 0.129078, 0.184938, 0.279945, 0.445074, 0.729351", \ - "0.0473713, 0.123017, 0.162337, 0.220766, 0.314559, 0.471353, 0.74387", \ - "0.0731631, 0.170543, 0.217245, 0.284661, 0.385586, 0.542708, 0.802753", \ - "0.117691, 0.244134, 0.305085, 0.38906, 0.505642, 0.679933, 0.947103", \ - "0.197971, 0.366442, 0.444775, 0.549704, 0.699136, 0.910352, 1.21203" \ + "0.0105987, 0.0618661, 0.0993262, 0.161472, 0.265548, 0.438961, 0.728051", \ + "0.0229819, 0.0772674, 0.111091, 0.168285, 0.268197, 0.439313, 0.728052", \ + "0.0317324, 0.0943115, 0.129077, 0.184935, 0.27994, 0.445061, 0.729293", \ + "0.0473711, 0.123006, 0.162335, 0.220764, 0.314555, 0.47133, 0.743862", \ + "0.073163, 0.170542, 0.217243, 0.284658, 0.385581, 0.542701, 0.802737", \ + "0.117691, 0.243842, 0.305105, 0.389057, 0.505638, 0.679926, 0.947087", \ + "0.19797, 0.366441, 0.444773, 0.549717, 0.699131, 0.910347, 1.21202" \ ); } cell_fall (TIMING_DELAY_7x7ds1) { index_1 ("0.0186, 0.0966, 0.174, 0.3294, 0.6408, 1.263, 2.5074"); index_2 ("0.001, 0.0234, 0.039, 0.0648, 0.108, 0.18, 0.3"); values ( \ - "0.0168906, 0.0664112, 0.0988883, 0.15237, 0.241754, 0.390771, 0.6392", \ - "0.0259136, 0.0936295, 0.12955, 0.18471, 0.274479, 0.423413, 0.671617", \ - "0.0316666, 0.112646, 0.15386, 0.21442, 0.307688, 0.457404, 0.705468", \ - "0.0394979, 0.140194, 0.18972, 0.260558, 0.365179, 0.523481, 0.774955", \ - "0.0472441, 0.176053, 0.236595, 0.323295, 0.447331, 0.628534, 0.899164", \ - "0.055715, 0.224209, 0.301271, 0.407944, 0.561603, 0.778391, 1.09363", \ - "0.0629573, 0.283973, 0.385022, 0.524083, 0.714335, 0.985432, 1.36784" \ + "0.0168881, 0.0664168, 0.0988838, 0.152365, 0.241885, 0.39079, 0.63901", \ + "0.0259136, 0.0936294, 0.12955, 0.184714, 0.274477, 0.423518, 0.671624", \ + "0.0316666, 0.112641, 0.153855, 0.21442, 0.307687, 0.457427, 0.70552", \ + "0.039498, 0.140194, 0.18972, 0.26059, 0.365179, 0.523589, 0.774943", \ + "0.0472444, 0.176053, 0.236595, 0.323295, 0.447331, 0.628533, 0.899163", \ + "0.0557158, 0.22421, 0.301272, 0.407944, 0.561603, 0.778391, 1.09378", \ + "0.0629593, 0.283974, 0.385023, 0.524084, 0.714335, 0.985432, 1.36784" \ ); } fall_transition (TIMING_DELAY_7x7ds1) { index_1 ("0.0186, 0.0966, 0.174, 0.3294, 0.6408, 1.263, 2.5074"); index_2 ("0.001, 0.0234, 0.039, 0.0648, 0.108, 0.18, 0.3"); values ( \ - "0.0123262, 0.075282, 0.120529, 0.195537, 0.32106, 0.53008, 0.878769", \ - "0.0238933, 0.0889902, 0.130448, 0.200825, 0.322623, 0.530487, 0.878953", \ - "0.0335273, 0.104611, 0.147104, 0.215913, 0.332728, 0.534536, 0.879636", \ - "0.0502592, 0.131916, 0.177892, 0.249275, 0.364443, 0.55779, 0.891159", \ - "0.0786386, 0.179259, 0.230462, 0.308453, 0.429821, 0.622902, 0.943753", \ - "0.127434, 0.25952, 0.31885, 0.408964, 0.542446, 0.750526, 1.07617", \ - "0.214693, 0.396072, 0.474699, 0.578067, 0.733913, 0.967756, 1.32119" \ + "0.0123241, 0.0752768, 0.120912, 0.195533, 0.320983, 0.530079, 0.879096", \ + "0.0238933, 0.0889902, 0.130448, 0.200791, 0.322617, 0.530751, 0.879097", \ + "0.0335273, 0.104481, 0.147143, 0.215912, 0.332728, 0.534534, 0.879212", \ + "0.0502591, 0.131916, 0.177892, 0.249348, 0.364442, 0.557944, 0.89115", \ + "0.0786385, 0.179258, 0.230462, 0.308452, 0.429821, 0.622901, 0.943752", \ + "0.127434, 0.259518, 0.318851, 0.408963, 0.542446, 0.750526, 1.0756", \ + "0.214692, 0.396071, 0.474699, 0.578065, 0.733913, 0.967754, 1.32119" \ ); } } @@ -24760,26 +24834,26 @@ library (sg13g2_stdcell_fast_1p65V_m40C) { index_1 ("0.0186, 0.0966, 0.174, 0.3294, 0.6408, 1.263, 2.5074"); index_2 ("0.001, 0.0234, 0.039, 0.0648, 0.108, 0.18, 0.3"); values ( \ - "0.00991448, 0.0101367, 0.0100837, 0.0100001, 0.00975941, 0.00936248, 0.00877118", \ - "0.0103754, 0.0101552, 0.0100189, 0.0100666, 0.00977481, 0.0092707, 0.00872212", \ - "0.0124111, 0.0110331, 0.0108189, 0.0104191, 0.010418, 0.00955169, 0.00891845", \ - "0.0179431, 0.0145082, 0.0135796, 0.0125888, 0.0117782, 0.0106108, 0.00999563", \ - "0.0301394, 0.0241023, 0.0219017, 0.0194893, 0.0170599, 0.0150489, 0.0130892", \ - "0.055204, 0.0465968, 0.042784, 0.0379484, 0.032675, 0.0273359, 0.0230664", \ - "0.106047, 0.0948108, 0.0890079, 0.0817544, 0.0721348, 0.0619324, 0.0510477" \ + "0.00992223, 0.0101563, 0.0100771, 0.00999933, 0.00977059, 0.00936276, 0.00878669", \ + "0.0103747, 0.0101452, 0.0100186, 0.0099233, 0.00968738, 0.00930828, 0.00872142", \ + "0.0124076, 0.0110455, 0.0108016, 0.0104195, 0.0106728, 0.00961231, 0.008857", \ + "0.0179471, 0.0145181, 0.0135749, 0.0125884, 0.0117071, 0.0106816, 0.00999598", \ + "0.0301386, 0.0241007, 0.0219, 0.0194877, 0.0170573, 0.0150029, 0.0128273", \ + "0.055204, 0.0466194, 0.0427842, 0.0379597, 0.0326766, 0.0273314, 0.0230663", \ + "0.106048, 0.0948104, 0.0890496, 0.0817582, 0.0721293, 0.0618665, 0.0507277" \ ); } fall_power (POWER_7x7ds1) { index_1 ("0.0186, 0.0966, 0.174, 0.3294, 0.6408, 1.263, 2.5074"); index_2 ("0.001, 0.0234, 0.039, 0.0648, 0.108, 0.18, 0.3"); values ( \ - "0.00906637, 0.00934563, 0.00919655, 0.00909643, 0.00889406, 0.00858953, 0.00768418", \ - "0.0094521, 0.00932259, 0.00929157, 0.00905248, 0.00972971, 0.00844932, 0.00785241", \ - "0.0113765, 0.0102091, 0.00995907, 0.00961272, 0.00972408, 0.00934304, 0.00799139", \ - "0.0165979, 0.0133407, 0.0125924, 0.0116822, 0.0106915, 0.010505, 0.00862914", \ - "0.0284954, 0.0222116, 0.0199666, 0.0179044, 0.0157145, 0.0136311, 0.0120933", \ - "0.0533118, 0.0435686, 0.0394516, 0.0348141, 0.0297817, 0.0254016, 0.0207259", \ - "0.10365, 0.0908127, 0.0843455, 0.0761795, 0.0666515, 0.0561629, 0.0456133" \ + "0.0090665, 0.00935823, 0.00919, 0.00909852, 0.00888209, 0.00847432, 0.00768913", \ + "0.00945152, 0.00932104, 0.00929361, 0.009063, 0.00887111, 0.00848987, 0.00772679", \ + "0.0113747, 0.0102078, 0.00995981, 0.00960024, 0.00947663, 0.00889211, 0.00802379", \ + "0.0165973, 0.0133401, 0.0125923, 0.0116939, 0.010691, 0.0105013, 0.00865974", \ + "0.0285018, 0.0222117, 0.0199662, 0.0179023, 0.0157176, 0.0136443, 0.012363", \ + "0.0533109, 0.0435701, 0.0394519, 0.0348133, 0.029783, 0.0254037, 0.0207238", \ + "0.10365, 0.0908123, 0.0843464, 0.0761788, 0.0666421, 0.0561691, 0.0456255" \ ); } } @@ -24789,26 +24863,26 @@ library (sg13g2_stdcell_fast_1p65V_m40C) { index_1 ("0.0186, 0.0966, 0.174, 0.3294, 0.6408, 1.263, 2.5074"); index_2 ("0.001, 0.0234, 0.039, 0.0648, 0.108, 0.18, 0.3"); values ( \ - "0.00487155, 0.00529086, 0.0052708, 0.00518499, 0.00498195, 0.00459334, 0.00401608", \ - "0.00634034, 0.00561956, 0.00539824, 0.00545299, 0.00499027, 0.00492642, 0.00396983", \ - "0.00880541, 0.0068098, 0.00646408, 0.00591059, 0.00582179, 0.00484371, 0.00403648", \ - "0.0141183, 0.0105678, 0.00936174, 0.00832842, 0.00714195, 0.00633037, 0.00496058", \ - "0.0255509, 0.0198439, 0.0176257, 0.0152338, 0.012712, 0.0108166, 0.00812298", \ - "0.0484932, 0.0403587, 0.0367456, 0.0323879, 0.027352, 0.0220016, 0.0177945", \ - "0.0953785, 0.0847218, 0.0793324, 0.0723927, 0.0639615, 0.0542983, 0.0436736" \ + "0.0048712, 0.00528502, 0.00527131, 0.00518557, 0.00499006, 0.00460593, 0.00401592", \ + "0.00634069, 0.00561946, 0.00535256, 0.00541901, 0.00499404, 0.00457928, 0.00396918", \ + "0.0088073, 0.00680703, 0.00647052, 0.00593661, 0.00597023, 0.00483575, 0.00404019", \ + "0.0141199, 0.0105668, 0.00934503, 0.00832842, 0.00711038, 0.00632945, 0.00566729", \ + "0.0255509, 0.0198453, 0.0176265, 0.0152425, 0.0126709, 0.0110494, 0.00812255", \ + "0.0484928, 0.0403588, 0.0367371, 0.0323932, 0.0273951, 0.0219951, 0.017492", \ + "0.0953781, 0.0847215, 0.0793284, 0.0723928, 0.0639957, 0.054297, 0.0437102" \ ); } fall_power (POWER_7x7ds1) { index_1 ("0.0186, 0.0966, 0.174, 0.3294, 0.6408, 1.263, 2.5074"); index_2 ("0.001, 0.0234, 0.039, 0.0648, 0.108, 0.18, 0.3"); values ( \ - "0.00857471, 0.00984609, 0.00971691, 0.00965029, 0.00947053, 0.00917112, 0.00854792", \ - "0.00912708, 0.00950825, 0.00965533, 0.00956539, 0.00992672, 0.00919189, 0.00851307", \ - "0.0110682, 0.0102337, 0.0101498, 0.00997467, 0.0101603, 0.00964899, 0.00873518", \ - "0.0160476, 0.012998, 0.0123379, 0.0118094, 0.011022, 0.0109227, 0.00921552", \ - "0.0270985, 0.0209383, 0.019029, 0.0174875, 0.0155762, 0.0137406, 0.0127342", \ - "0.0498969, 0.0404094, 0.0366253, 0.0323097, 0.0280633, 0.0242231, 0.0204377", \ - "0.0961796, 0.0831225, 0.0773199, 0.0698981, 0.0609791, 0.0520306, 0.0435637" \ + "0.00855879, 0.00969922, 0.00977284, 0.00967046, 0.0095304, 0.0091709, 0.00838812", \ + "0.00912638, 0.0095055, 0.00965744, 0.00955765, 0.00992777, 0.00911707, 0.008513", \ + "0.0110676, 0.0102332, 0.0101017, 0.00997448, 0.00990585, 0.00938231, 0.00870057", \ + "0.0160475, 0.012998, 0.0123417, 0.0117624, 0.010875, 0.0109226, 0.00921131", \ + "0.0271007, 0.0209372, 0.0190295, 0.0174874, 0.0155665, 0.0137526, 0.0124979", \ + "0.0498963, 0.04041, 0.0366258, 0.0323081, 0.0281351, 0.0242219, 0.0204596", \ + "0.0959221, 0.0831213, 0.0773209, 0.0698979, 0.0609865, 0.0520306, 0.0435336" \ ); } } @@ -24819,26 +24893,26 @@ library (sg13g2_stdcell_fast_1p65V_m40C) { index_1 ("0.0186, 0.0966, 0.174, 0.3294, 0.6408, 1.263, 2.5074"); index_2 ("0.001, 0.0234, 0.039, 0.0648, 0.108, 0.18, 0.3"); values ( \ - "0.00332019, 0.00431345, 0.0043887, 0.00434829, 0.00421176, 0.00386871, 0.00319076", \ - "0.00557239, 0.00461396, 0.00455907, 0.00460271, 0.00447006, 0.00406985, 0.00319381", \ - "0.00858412, 0.00616099, 0.00568362, 0.00529212, 0.00515808, 0.00417048, 0.00333391", \ - "0.014909, 0.0103868, 0.00922625, 0.0080344, 0.00686337, 0.00592461, 0.0051081", \ - "0.0280678, 0.0210004, 0.0185965, 0.0160413, 0.013419, 0.0108766, 0.00908155", \ - "0.0544883, 0.0446772, 0.040513, 0.0357758, 0.0300911, 0.0247522, 0.0191988", \ - "0.107989, 0.0949515, 0.0885443, 0.0808385, 0.0710122, 0.0608691, 0.0499309" \ + "0.00331671, 0.00434801, 0.00438814, 0.00434902, 0.00421269, 0.00386797, 0.00322761", \ + "0.00557216, 0.00460068, 0.00455505, 0.0045922, 0.00446562, 0.00384372, 0.00322451", \ + "0.00858356, 0.00616224, 0.00568362, 0.00529185, 0.0051566, 0.00414632, 0.00332111", \ + "0.0149085, 0.0103863, 0.00922788, 0.00804781, 0.00686519, 0.00641365, 0.00504853", \ + "0.0280672, 0.0210006, 0.0185952, 0.0160499, 0.0134312, 0.0108735, 0.00882533", \ + "0.0544887, 0.0446821, 0.0405189, 0.0357761, 0.0300904, 0.0247538, 0.0195186", \ + "0.10799, 0.0949519, 0.0885467, 0.0808139, 0.0710072, 0.0608809, 0.0499115" \ ); } fall_power (POWER_7x7ds1) { index_1 ("0.0186, 0.0966, 0.174, 0.3294, 0.6408, 1.263, 2.5074"); index_2 ("0.001, 0.0234, 0.039, 0.0648, 0.108, 0.18, 0.3"); values ( \ - "0.00428553, 0.00521629, 0.00519376, 0.00515809, 0.00498374, 0.00463286, 0.00395343", \ - "0.00625988, 0.00540527, 0.00535234, 0.00513805, 0.00576761, 0.00465458, 0.00397654", \ - "0.00908516, 0.00679076, 0.00626702, 0.00592899, 0.00587713, 0.0050497, 0.0041825", \ - "0.0154003, 0.0106567, 0.00951277, 0.00845167, 0.00722531, 0.00648942, 0.00491103", \ - "0.0283789, 0.0206445, 0.0181432, 0.0156491, 0.013139, 0.0106391, 0.00885057", \ - "0.0548182, 0.0436144, 0.0390663, 0.0341028, 0.0288715, 0.0236185, 0.0180726", \ - "0.107992, 0.0931453, 0.0863811, 0.0779454, 0.0677087, 0.0575117, 0.0460843" \ + "0.00427992, 0.00522944, 0.00529404, 0.00516181, 0.0049645, 0.00461801, 0.00402029", \ + "0.00626044, 0.00540528, 0.0053532, 0.0051557, 0.00576399, 0.00470092, 0.00397886", \ + "0.009085, 0.00679622, 0.00630557, 0.00592898, 0.00588885, 0.0050586, 0.00410943", \ + "0.0153993, 0.0106567, 0.00951279, 0.00841708, 0.00729132, 0.00686984, 0.0049212", \ + "0.0283793, 0.020645, 0.0181467, 0.0156489, 0.0131097, 0.0106695, 0.00885057", \ + "0.0548181, 0.0436113, 0.0390606, 0.0341031, 0.0288678, 0.0236085, 0.0180084", \ + "0.107982, 0.0931445, 0.0863818, 0.0779471, 0.0677092, 0.0575115, 0.0460804" \ ); } } @@ -24848,26 +24922,26 @@ library (sg13g2_stdcell_fast_1p65V_m40C) { index_1 ("0.0186, 0.0966, 0.174, 0.3294, 0.6408, 1.263, 2.5074"); index_2 ("0.001, 0.0234, 0.039, 0.0648, 0.108, 0.18, 0.3"); values ( \ - "0.00332019, 0.00431345, 0.0043887, 0.00434829, 0.00421176, 0.00386871, 0.00319076", \ - "0.00557239, 0.00461396, 0.00455907, 0.00460271, 0.00447006, 0.00406985, 0.00319381", \ - "0.00858412, 0.00616099, 0.00568362, 0.00529212, 0.00515808, 0.00417048, 0.00333391", \ - "0.014909, 0.0103868, 0.00922625, 0.0080344, 0.00686337, 0.00592461, 0.0051081", \ - "0.0280678, 0.0210004, 0.0185965, 0.0160413, 0.013419, 0.0108766, 0.00908155", \ - "0.0544883, 0.0446772, 0.040513, 0.0357758, 0.0300911, 0.0247522, 0.0191988", \ - "0.107989, 0.0949515, 0.0885443, 0.0808385, 0.0710122, 0.0608691, 0.0499309" \ + "0.00331671, 0.00434801, 0.00438814, 0.00434902, 0.00421269, 0.00386797, 0.00322761", \ + "0.00557216, 0.00460068, 0.00455505, 0.0045922, 0.00446562, 0.00384372, 0.00322451", \ + "0.00858356, 0.00616224, 0.00568362, 0.00529185, 0.0051566, 0.00414632, 0.00332111", \ + "0.0149085, 0.0103863, 0.00922788, 0.00804781, 0.00686519, 0.00641365, 0.00504853", \ + "0.0280672, 0.0210006, 0.0185952, 0.0160499, 0.0134312, 0.0108735, 0.00882533", \ + "0.0544887, 0.0446821, 0.0405189, 0.0357761, 0.0300904, 0.0247538, 0.0195186", \ + "0.10799, 0.0949519, 0.0885467, 0.0808139, 0.0710072, 0.0608809, 0.0499115" \ ); } fall_power (POWER_7x7ds1) { index_1 ("0.0186, 0.0966, 0.174, 0.3294, 0.6408, 1.263, 2.5074"); index_2 ("0.001, 0.0234, 0.039, 0.0648, 0.108, 0.18, 0.3"); values ( \ - "0.00428553, 0.00521629, 0.00519376, 0.00515809, 0.00498374, 0.00463286, 0.00395343", \ - "0.00625988, 0.00540527, 0.00535234, 0.00513805, 0.00576761, 0.00465458, 0.00397654", \ - "0.00908516, 0.00679076, 0.00626702, 0.00592899, 0.00587713, 0.0050497, 0.0041825", \ - "0.0154003, 0.0106567, 0.00951277, 0.00845167, 0.00722531, 0.00648942, 0.00491103", \ - "0.0283789, 0.0206445, 0.0181432, 0.0156491, 0.013139, 0.0106391, 0.00885057", \ - "0.0548182, 0.0436144, 0.0390663, 0.0341028, 0.0288715, 0.0236185, 0.0180726", \ - "0.107992, 0.0931453, 0.0863811, 0.0779454, 0.0677087, 0.0575117, 0.0460843" \ + "0.00427992, 0.00522944, 0.00529404, 0.00516181, 0.0049645, 0.00461801, 0.00402029", \ + "0.00626044, 0.00540528, 0.0053532, 0.0051557, 0.00576399, 0.00470092, 0.00397886", \ + "0.009085, 0.00679622, 0.00630557, 0.00592898, 0.00588885, 0.0050586, 0.00410943", \ + "0.0153993, 0.0106567, 0.00951279, 0.00841708, 0.00729132, 0.00686984, 0.0049212", \ + "0.0283793, 0.020645, 0.0181467, 0.0156489, 0.0131097, 0.0106695, 0.00885057", \ + "0.0548181, 0.0436113, 0.0390606, 0.0341031, 0.0288678, 0.0236085, 0.0180084", \ + "0.107982, 0.0931445, 0.0863818, 0.0779471, 0.0677092, 0.0575115, 0.0460804" \ ); } } @@ -24875,29 +24949,29 @@ library (sg13g2_stdcell_fast_1p65V_m40C) { pin (A1) { direction : "input"; max_transition : 2.5074; - capacitance : 0.00383199; - rise_capacitance : 0.00390965; - rise_capacitance_range (0.00390965, 0.00390965); - fall_capacitance : 0.00375433; - fall_capacitance_range (0.00375433, 0.00375433); + capacitance : 0.00383204; + rise_capacitance : 0.00390972; + rise_capacitance_range (0.00336096, 0.00450843); + fall_capacitance : 0.00375435; + fall_capacitance_range (0.00322422, 0.00399983); } pin (A2) { direction : "input"; max_transition : 2.5074; - capacitance : 0.00372818; - rise_capacitance : 0.00404627; - rise_capacitance_range (0.00404627, 0.00404627); - fall_capacitance : 0.00341009; - fall_capacitance_range (0.00341009, 0.00341009); + capacitance : 0.00372815; + rise_capacitance : 0.00404623; + rise_capacitance_range (0.00317697, 0.0053608); + fall_capacitance : 0.00341007; + fall_capacitance_range (0.00319313, 0.00357517); } pin (B1) { direction : "input"; max_transition : 2.5074; - capacitance : 0.00353641; - rise_capacitance : 0.00358287; - rise_capacitance_range (0.00358287, 0.00358287); - fall_capacitance : 0.00348996; - fall_capacitance_range (0.00348996, 0.00348996); + capacitance : 0.00353645; + rise_capacitance : 0.00358294; + rise_capacitance_range (0.00321207, 0.00423352); + fall_capacitance : 0.00348997; + fall_capacitance_range (0.00310429, 0.00403075); } } cell (sg13g2_or2_1) { @@ -25103,18 +25177,18 @@ library (sg13g2_stdcell_fast_1p65V_m40C) { max_transition : 2.5074; capacitance : 0.00280138; rise_capacitance : 0.00276716; - rise_capacitance_range (0.00276716, 0.00276716); + rise_capacitance_range (0.00245726, 0.00302729); fall_capacitance : 0.0028356; - fall_capacitance_range (0.0028356, 0.0028356); + fall_capacitance_range (0.00241298, 0.00300524); } pin (B) { direction : "input"; max_transition : 2.5074; capacitance : 0.00261781; rise_capacitance : 0.00279441; - rise_capacitance_range (0.00279441, 0.00279441); + rise_capacitance_range (0.00222908, 0.00329302); fall_capacitance : 0.0024412; - fall_capacitance_range (0.0024412, 0.0024412); + fall_capacitance_range (0.00223938, 0.00254926); } } cell (sg13g2_or2_2) { @@ -25320,18 +25394,18 @@ library (sg13g2_stdcell_fast_1p65V_m40C) { max_transition : 2.5074; capacitance : 0.00277326; rise_capacitance : 0.00272944; - rise_capacitance_range (0.00272944, 0.00272944); + rise_capacitance_range (0.00246082, 0.00297434); fall_capacitance : 0.00281708; - fall_capacitance_range (0.00281708, 0.00281708); + fall_capacitance_range (0.00241213, 0.00297775); } pin (B) { direction : "input"; max_transition : 2.5074; capacitance : 0.00257447; rise_capacitance : 0.00272539; - rise_capacitance_range (0.00272539, 0.00272539); + rise_capacitance_range (0.00226838, 0.00314964); fall_capacitance : 0.00242355; - fall_capacitance_range (0.00242355, 0.00242355); + fall_capacitance_range (0.00224309, 0.00253096); } } cell (sg13g2_or3_1) { @@ -25639,27 +25713,27 @@ library (sg13g2_stdcell_fast_1p65V_m40C) { max_transition : 2.5074; capacitance : 0.00296464; rise_capacitance : 0.00290333; - rise_capacitance_range (0.00290333, 0.00290333); + rise_capacitance_range (0.00262617, 0.00313753); fall_capacitance : 0.00302596; - fall_capacitance_range (0.00302596, 0.00302596); + fall_capacitance_range (0.0025006, 0.00327533); } pin (B) { direction : "input"; max_transition : 2.5074; capacitance : 0.00288918; rise_capacitance : 0.0029663; - rise_capacitance_range (0.0029663, 0.0029663); + rise_capacitance_range (0.00247505, 0.0033686); fall_capacitance : 0.00281207; - fall_capacitance_range (0.00281207, 0.00281207); + fall_capacitance_range (0.00234383, 0.00297882); } pin (C) { direction : "input"; max_transition : 2.5074; capacitance : 0.00275553; rise_capacitance : 0.00302632; - rise_capacitance_range (0.00302632, 0.00302632); + rise_capacitance_range (0.00232126, 0.00365168); fall_capacitance : 0.00248474; - fall_capacitance_range (0.00248474, 0.00248474); + fall_capacitance_range (0.00228412, 0.00258597); } } cell (sg13g2_or3_2) { @@ -25967,27 +26041,27 @@ library (sg13g2_stdcell_fast_1p65V_m40C) { max_transition : 2.5074; capacitance : 0.00294479; rise_capacitance : 0.00287859; - rise_capacitance_range (0.00287859, 0.00287859); + rise_capacitance_range (0.00262807, 0.00310681); fall_capacitance : 0.00301099; - fall_capacitance_range (0.00301099, 0.00301099); + fall_capacitance_range (0.00249798, 0.00324733); } pin (B) { direction : "input"; max_transition : 2.5074; capacitance : 0.00286512; rise_capacitance : 0.0029266; - rise_capacitance_range (0.0029266, 0.0029266); + rise_capacitance_range (0.00249577, 0.00330095); fall_capacitance : 0.00280365; - fall_capacitance_range (0.00280365, 0.00280365); + fall_capacitance_range (0.00234553, 0.00296688); } pin (C) { direction : "input"; max_transition : 2.5074; capacitance : 0.00271699; rise_capacitance : 0.00296037; - rise_capacitance_range (0.00296037, 0.00296037); + rise_capacitance_range (0.00238164, 0.00349758); fall_capacitance : 0.00247361; - fall_capacitance_range (0.00247361, 0.00247361); + fall_capacitance_range (0.00229255, 0.00257419); } } cell (sg13g2_or4_1) { @@ -26413,36 +26487,36 @@ library (sg13g2_stdcell_fast_1p65V_m40C) { max_transition : 2.5074; capacitance : 0.00296332; rise_capacitance : 0.00289441; - rise_capacitance_range (0.00289441, 0.00289441); + rise_capacitance_range (0.00263473, 0.00313623); fall_capacitance : 0.00303222; - fall_capacitance_range (0.00303222, 0.00303222); + fall_capacitance_range (0.00250379, 0.00331073); } pin (B) { direction : "input"; max_transition : 2.5074; capacitance : 0.00286039; rise_capacitance : 0.0029068; - rise_capacitance_range (0.0029068, 0.0029068); + rise_capacitance_range (0.00246562, 0.00329616); fall_capacitance : 0.00281397; - fall_capacitance_range (0.00281397, 0.00281397); + fall_capacitance_range (0.00232834, 0.00301953); } pin (C) { direction : "input"; max_transition : 2.5074; capacitance : 0.00283933; rise_capacitance : 0.00298327; - rise_capacitance_range (0.00298327, 0.00298327); + rise_capacitance_range (0.00238615, 0.00353898); fall_capacitance : 0.00269538; - fall_capacitance_range (0.00269538, 0.00269538); + fall_capacitance_range (0.00226324, 0.00283855); } pin (D) { direction : "input"; max_transition : 2.5074; capacitance : 0.00275096; rise_capacitance : 0.00307419; - rise_capacitance_range (0.00307419, 0.00307419); + rise_capacitance_range (0.00230187, 0.00385791); fall_capacitance : 0.00242774; - fall_capacitance_range (0.00242774, 0.00242774); + fall_capacitance_range (0.00226446, 0.00249895); } } cell (sg13g2_or4_2) { @@ -26868,41 +26942,41 @@ library (sg13g2_stdcell_fast_1p65V_m40C) { max_transition : 2.5074; capacitance : 0.00293271; rise_capacitance : 0.00285713; - rise_capacitance_range (0.00285713, 0.00285713); + rise_capacitance_range (0.00261817, 0.00309291); fall_capacitance : 0.00300829; - fall_capacitance_range (0.00300829, 0.00300829); + fall_capacitance_range (0.00248923, 0.00327561); } pin (B) { direction : "input"; max_transition : 2.5074; capacitance : 0.00284394; rise_capacitance : 0.00287614; - rise_capacitance_range (0.00287614, 0.00287614); + rise_capacitance_range (0.00248107, 0.00324552); fall_capacitance : 0.00281174; - fall_capacitance_range (0.00281174, 0.00281174); + fall_capacitance_range (0.00233578, 0.00301404); } pin (C) { direction : "input"; max_transition : 2.5074; capacitance : 0.00281609; rise_capacitance : 0.00293794; - rise_capacitance_range (0.00293794, 0.00293794); + rise_capacitance_range (0.00241603, 0.00344125); fall_capacitance : 0.00269424; - fall_capacitance_range (0.00269424, 0.00269424); + fall_capacitance_range (0.00227032, 0.00283657); } pin (D) { direction : "input"; max_transition : 2.5074; capacitance : 0.00270862; rise_capacitance : 0.00299563; - rise_capacitance_range (0.00299563, 0.00299563); + rise_capacitance_range (0.00236557, 0.00366023); fall_capacitance : 0.00242161; - fall_capacitance_range (0.00242161, 0.00242161); + fall_capacitance_range (0.00227527, 0.00249414); } } cell (sg13g2_sdfbbp_1) { area : 63.504; - cell_footprint : "sdfrrs"; + cell_footprint : "sdfbbp"; cell_leakage_power : 6694.12; dont_touch : true; dont_use : true; @@ -26998,6 +27072,7 @@ library (sg13g2_stdcell_fast_1p65V_m40C) { timing () { related_pin : "CLK"; sdf_cond : "SCE == 1'b1"; + sdf_edges : start_edge; timing_sense : non_unate; timing_type : rising_edge; when : "SCE"; @@ -27056,6 +27131,7 @@ library (sg13g2_stdcell_fast_1p65V_m40C) { } timing () { related_pin : "CLK"; + sdf_edges : start_edge; timing_sense : non_unate; timing_type : rising_edge; cell_rise (TIMING_DELAY_7x7ds1) { @@ -27113,6 +27189,7 @@ library (sg13g2_stdcell_fast_1p65V_m40C) { } timing () { related_pin : "RESET_B"; + sdf_edges : start_edge; timing_sense : positive_unate; timing_type : clear; cell_fall (TIMING_DELAY_7x7ds1) { @@ -27144,6 +27221,7 @@ library (sg13g2_stdcell_fast_1p65V_m40C) { } timing () { related_pin : "SET_B"; + sdf_edges : start_edge; timing_sense : negative_unate; timing_type : preset; cell_rise (TIMING_DELAY_7x7ds1) { @@ -27283,6 +27361,7 @@ library (sg13g2_stdcell_fast_1p65V_m40C) { timing () { related_pin : "CLK"; sdf_cond : "SCE == 1'b1"; + sdf_edges : start_edge; timing_sense : non_unate; timing_type : rising_edge; when : "SCE"; @@ -27341,6 +27420,7 @@ library (sg13g2_stdcell_fast_1p65V_m40C) { } timing () { related_pin : "CLK"; + sdf_edges : start_edge; timing_sense : non_unate; timing_type : rising_edge; cell_rise (TIMING_DELAY_7x7ds1) { @@ -27398,6 +27478,7 @@ library (sg13g2_stdcell_fast_1p65V_m40C) { } timing () { related_pin : "RESET_B"; + sdf_edges : start_edge; timing_sense : negative_unate; timing_type : preset; cell_rise (TIMING_DELAY_7x7ds1) { @@ -27429,6 +27510,7 @@ library (sg13g2_stdcell_fast_1p65V_m40C) { } timing () { related_pin : "SET_B"; + sdf_edges : start_edge; timing_sense : positive_unate; timing_type : clear; cell_fall (TIMING_DELAY_7x7ds1) { @@ -27566,9 +27648,9 @@ library (sg13g2_stdcell_fast_1p65V_m40C) { max_transition : 2.5074; capacitance : 0.00341488; rise_capacitance : 0.0034713; - rise_capacitance_range (0.0034713, 0.0034713); + rise_capacitance_range (0.0030682, 0.00381674); fall_capacitance : 0.00334435; - fall_capacitance_range (0.00334435, 0.00334435); + fall_capacitance_range (0.00303464, 0.00360462); timing () { related_pin : "CLK"; timing_type : min_pulse_width; @@ -27724,11 +27806,12 @@ library (sg13g2_stdcell_fast_1p65V_m40C) { max_transition : 2.5074; capacitance : 0.00217607; rise_capacitance : 0.00222433; - rise_capacitance_range (0.00222433, 0.00222433); + rise_capacitance_range (0.00195284, 0.00244091); fall_capacitance : 0.00212782; - fall_capacitance_range (0.00212782, 0.00212782); + fall_capacitance_range (0.00192901, 0.00226055); timing () { related_pin : "CLK"; + sdf_edges : both_edges; timing_type : hold_rising; rise_constraint (CONSTRAINT_4x4) { index_1 ("0.0186, 0.51636, 1.263, 2.5074"); @@ -27753,6 +27836,7 @@ library (sg13g2_stdcell_fast_1p65V_m40C) { } timing () { related_pin : "CLK"; + sdf_edges : both_edges; timing_type : setup_rising; rise_constraint (CONSTRAINT_4x4) { index_1 ("0.0186, 0.51636, 1.263, 2.5074"); @@ -27827,9 +27911,10 @@ library (sg13g2_stdcell_fast_1p65V_m40C) { rise_capacitance : 0.00195102; rise_capacitance_range (0.00195102, 0.00195102); fall_capacitance : 0.00195102; - fall_capacitance_range (0.00195102, 0.00195102); + fall_capacitance_range (0.00178706, 0.00209648); timing () { related_pin : "CLK"; + sdf_edges : both_edges; timing_type : recovery_rising; rise_constraint (CONSTRAINT_4x4) { index_1 ("0.0186, 0.51636, 1.263, 2.5074"); @@ -27844,6 +27929,7 @@ library (sg13g2_stdcell_fast_1p65V_m40C) { } timing () { related_pin : "CLK"; + sdf_edges : both_edges; timing_type : removal_rising; rise_constraint (CONSTRAINT_4x4) { index_1 ("0.0186, 0.51636, 1.263, 2.5074"); @@ -27873,11 +27959,12 @@ library (sg13g2_stdcell_fast_1p65V_m40C) { max_transition : 2.5074; capacitance : 0.00224525; rise_capacitance : 0.00225854; - rise_capacitance_range (0.00225854, 0.00225854); + rise_capacitance_range (0.00194665, 0.00241848); fall_capacitance : 0.00223196; - fall_capacitance_range (0.00223196, 0.00223196); + fall_capacitance_range (0.00192934, 0.00235762); timing () { related_pin : "CLK"; + sdf_edges : both_edges; timing_type : hold_rising; rise_constraint (CONSTRAINT_4x4) { index_1 ("0.0186, 0.51636, 1.263, 2.5074"); @@ -27902,6 +27989,7 @@ library (sg13g2_stdcell_fast_1p65V_m40C) { } timing () { related_pin : "CLK"; + sdf_edges : both_edges; timing_type : setup_rising; rise_constraint (CONSTRAINT_4x4) { index_1 ("0.0186, 0.51636, 1.263, 2.5074"); @@ -27975,11 +28063,12 @@ library (sg13g2_stdcell_fast_1p65V_m40C) { max_transition : 2.5074; capacitance : 0.0039541; rise_capacitance : 0.00434677; - rise_capacitance_range (0.00434677, 0.00434677); + rise_capacitance_range (0.00416928, 0.00502218); fall_capacitance : 0.00356143; - fall_capacitance_range (0.00356143, 0.00356143); + fall_capacitance_range (0.00356143, 0.00472863); timing () { related_pin : "CLK"; + sdf_edges : both_edges; timing_type : hold_rising; rise_constraint (CONSTRAINT_4x4) { index_1 ("0.0186, 0.51636, 1.263, 2.5074"); @@ -28004,6 +28093,7 @@ library (sg13g2_stdcell_fast_1p65V_m40C) { } timing () { related_pin : "CLK"; + sdf_edges : both_edges; timing_type : setup_rising; rise_constraint (CONSTRAINT_4x4) { index_1 ("0.0186, 0.51636, 1.263, 2.5074"); @@ -28108,9 +28198,10 @@ library (sg13g2_stdcell_fast_1p65V_m40C) { rise_capacitance : 0.00586704; rise_capacitance_range (0.00586704, 0.00586704); fall_capacitance : 0.00586704; - fall_capacitance_range (0.00586704, 0.00586704); + fall_capacitance_range (0.00538039, 0.00626709); timing () { related_pin : "CLK"; + sdf_edges : both_edges; timing_type : recovery_rising; rise_constraint (CONSTRAINT_4x4) { index_1 ("0.0186, 0.51636, 1.263, 2.5074"); @@ -28125,6 +28216,7 @@ library (sg13g2_stdcell_fast_1p65V_m40C) { } timing () { related_pin : "CLK"; + sdf_edges : both_edges; timing_type : removal_rising; rise_constraint (CONSTRAINT_4x4) { index_1 ("0.0186, 0.51636, 1.263, 2.5074"); @@ -28139,6 +28231,7 @@ library (sg13g2_stdcell_fast_1p65V_m40C) { } timing () { related_pin : "RESET_B"; + sdf_edges : both_edges; timing_type : non_seq_hold_rising; rise_constraint (CONSTRAINT_4x4) { index_1 ("0.0186, 0.51636, 1.263, 2.5074"); @@ -28153,6 +28246,7 @@ library (sg13g2_stdcell_fast_1p65V_m40C) { } timing () { related_pin : "RESET_B"; + sdf_edges : both_edges; timing_type : non_seq_setup_rising; rise_constraint (CONSTRAINT_4x4) { index_1 ("0.0186, 0.51636, 1.263, 2.5074"); @@ -28177,12 +28271,12 @@ library (sg13g2_stdcell_fast_1p65V_m40C) { } } ff (IQ,IQN) { - clear : "RESET_B'"; + clear : "!RESET_B"; clear_preset_var1 : "H"; clear_preset_var2 : "L"; clocked_on : "CLK"; - next_state : "(SCE*SCD)+(SCE'*D)"; - preset : "SET_B'"; + next_state : "(SCE*SCD)+(!SCE*D)"; + preset : "!SET_B"; } test_cell () { pin (Q) { @@ -28216,12 +28310,12 @@ library (sg13g2_stdcell_fast_1p65V_m40C) { direction : input; } ff (IQ,IQN) { - clear : "RESET_B'"; + clear : "!RESET_B"; clear_preset_var1 : H; clear_preset_var2 : L; clocked_on : "CLK"; next_state : "D"; - preset : "SET_B'"; + preset : "!SET_B"; } } } @@ -28305,6 +28399,7 @@ library (sg13g2_stdcell_fast_1p65V_m40C) { timing () { related_pin : "CLK"; sdf_cond : "SCE == 1'b1"; + sdf_edges : start_edge; timing_sense : non_unate; timing_type : rising_edge; when : "SCE"; @@ -28312,7 +28407,7 @@ library (sg13g2_stdcell_fast_1p65V_m40C) { index_1 ("0.0186, 0.0966, 0.174, 0.3294, 0.6408, 1.263, 2.5074"); index_2 ("0.001, 0.0234, 0.039, 0.0648, 0.108, 0.18, 0.3"); values ( \ - "0.0896464, 0.118507, 0.139103, 0.173272, 0.230436, 0.325787, 0.48471", \ + "0.0896405, 0.118507, 0.139103, 0.173266, 0.23049, 0.325787, 0.484713", \ "0.108693, 0.137544, 0.158119, 0.192262, 0.24944, 0.344747, 0.503711", \ "0.121378, 0.150183, 0.170808, 0.204927, 0.262071, 0.357364, 0.516225", \ "0.140243, 0.168973, 0.189579, 0.223673, 0.280855, 0.376152, 0.535006", \ @@ -28325,20 +28420,20 @@ library (sg13g2_stdcell_fast_1p65V_m40C) { index_1 ("0.0186, 0.0966, 0.174, 0.3294, 0.6408, 1.263, 2.5074"); index_2 ("0.001, 0.0234, 0.039, 0.0648, 0.108, 0.18, 0.3"); values ( \ - "0.0103689, 0.05111, 0.0817905, 0.132854, 0.218485, 0.361218, 0.598994", \ - "0.0103699, 0.051111, 0.0817931, 0.132855, 0.218486, 0.362526, 0.599017", \ - "0.0103838, 0.051112, 0.081811, 0.132856, 0.218487, 0.362527, 0.599018", \ - "0.0104606, 0.051113, 0.081812, 0.132857, 0.218488, 0.362528, 0.599019", \ - "0.0106725, 0.0511223, 0.0818214, 0.132895, 0.218489, 0.362529, 0.599088", \ - "0.011144, 0.051201, 0.081864, 0.132896, 0.21849, 0.36253, 0.599089", \ - "0.01208, 0.051405, 0.081923, 0.132946, 0.218491, 0.362531, 0.59909" \ + "0.0103477, 0.0510662, 0.0817905, 0.132866, 0.218456, 0.361218, 0.599277", \ + "0.0103636, 0.0510782, 0.0817931, 0.132867, 0.218457, 0.362526, 0.599278", \ + "0.0103838, 0.0510792, 0.081811, 0.132868, 0.218458, 0.362527, 0.599279", \ + "0.0104606, 0.0510844, 0.081812, 0.132869, 0.218459, 0.362528, 0.59928", \ + "0.0106725, 0.0511223, 0.0818214, 0.132895, 0.21846, 0.362529, 0.599281", \ + "0.011144, 0.051201, 0.081864, 0.132896, 0.218474, 0.36253, 0.599282", \ + "0.01208, 0.051405, 0.081923, 0.132946, 0.218486, 0.362531, 0.599283" \ ); } cell_fall (TIMING_DELAY_7x7ds1) { index_1 ("0.0186, 0.0966, 0.174, 0.3294, 0.6408, 1.263, 2.5074"); index_2 ("0.001, 0.0234, 0.039, 0.0648, 0.108, 0.18, 0.3"); values ( \ - "0.0838875, 0.11023, 0.127716, 0.156585, 0.204729, 0.285116, 0.418908", \ + "0.0838558, 0.110229, 0.127716, 0.156585, 0.204731, 0.285061, 0.418926", \ "0.102327, 0.128737, 0.146214, 0.17504, 0.223236, 0.303532, 0.437463", \ "0.114388, 0.140753, 0.158245, 0.187065, 0.235261, 0.315514, 0.449321", \ "0.131435, 0.157825, 0.175323, 0.204143, 0.252355, 0.332629, 0.466391", \ @@ -28351,25 +28446,26 @@ library (sg13g2_stdcell_fast_1p65V_m40C) { index_1 ("0.0186, 0.0966, 0.174, 0.3294, 0.6408, 1.263, 2.5074"); index_2 ("0.001, 0.0234, 0.039, 0.0648, 0.108, 0.18, 0.3"); values ( \ - "0.0085456, 0.0411824, 0.0653034, 0.105601, 0.173364, 0.286284, 0.474661", \ - "0.0085466, 0.0411834, 0.0653339, 0.105611, 0.173365, 0.286285, 0.474673", \ - "0.0085476, 0.0411844, 0.0653349, 0.105612, 0.173366, 0.286303, 0.474674", \ - "0.0085486, 0.0411854, 0.0653359, 0.105613, 0.173367, 0.286304, 0.474675", \ - "0.0085496, 0.0411864, 0.0653369, 0.105615, 0.173368, 0.286305, 0.474676", \ - "0.0085506, 0.0411874, 0.0653379, 0.105616, 0.173369, 0.286306, 0.474677", \ - "0.00856, 0.0411884, 0.0653389, 0.105619, 0.17337, 0.286388, 0.474769" \ + "0.0085455, 0.041206, 0.0653034, 0.105601, 0.173365, 0.286476, 0.474661", \ + "0.0085465, 0.041207, 0.0653339, 0.105611, 0.173366, 0.286477, 0.474673", \ + "0.0085475, 0.041208, 0.0653349, 0.105612, 0.173367, 0.286478, 0.474674", \ + "0.0085485, 0.041209, 0.0653359, 0.105613, 0.173368, 0.286479, 0.474675", \ + "0.0085495, 0.04121, 0.0653369, 0.105615, 0.173369, 0.28648, 0.474676", \ + "0.0085505, 0.041211, 0.0653379, 0.105616, 0.17337, 0.286481, 0.474677", \ + "0.00856, 0.041212, 0.0653389, 0.105619, 0.173371, 0.286482, 0.474769" \ ); } } timing () { related_pin : "CLK"; + sdf_edges : start_edge; timing_sense : non_unate; timing_type : rising_edge; cell_rise (TIMING_DELAY_7x7ds1) { index_1 ("0.0186, 0.0966, 0.174, 0.3294, 0.6408, 1.263, 2.5074"); index_2 ("0.001, 0.0234, 0.039, 0.0648, 0.108, 0.18, 0.3"); values ( \ - "0.0896464, 0.118507, 0.139103, 0.173272, 0.230436, 0.325787, 0.48471", \ + "0.0896405, 0.118507, 0.139103, 0.173266, 0.23049, 0.325787, 0.484713", \ "0.108693, 0.137544, 0.158119, 0.192262, 0.24944, 0.344747, 0.503711", \ "0.121378, 0.150183, 0.170808, 0.204927, 0.262071, 0.357364, 0.516225", \ "0.140243, 0.168973, 0.189579, 0.223673, 0.280855, 0.376152, 0.535006", \ @@ -28382,20 +28478,20 @@ library (sg13g2_stdcell_fast_1p65V_m40C) { index_1 ("0.0186, 0.0966, 0.174, 0.3294, 0.6408, 1.263, 2.5074"); index_2 ("0.001, 0.0234, 0.039, 0.0648, 0.108, 0.18, 0.3"); values ( \ - "0.0103689, 0.05111, 0.0817905, 0.132854, 0.218485, 0.361218, 0.598994", \ - "0.0103699, 0.051111, 0.0817931, 0.132855, 0.218486, 0.362526, 0.599017", \ - "0.0103838, 0.051112, 0.081811, 0.132856, 0.218487, 0.362527, 0.599018", \ - "0.0104606, 0.051113, 0.081812, 0.132857, 0.218488, 0.362528, 0.599019", \ - "0.0106725, 0.0511223, 0.0818214, 0.132895, 0.218489, 0.362529, 0.599088", \ - "0.011144, 0.051201, 0.081864, 0.132896, 0.21849, 0.36253, 0.599089", \ - "0.01208, 0.051405, 0.081923, 0.132946, 0.218491, 0.362531, 0.59909" \ + "0.0103477, 0.0510662, 0.0817905, 0.132866, 0.218456, 0.361218, 0.599277", \ + "0.0103636, 0.0510782, 0.0817931, 0.132867, 0.218457, 0.362526, 0.599278", \ + "0.0103838, 0.0510792, 0.081811, 0.132868, 0.218458, 0.362527, 0.599279", \ + "0.0104606, 0.0510844, 0.081812, 0.132869, 0.218459, 0.362528, 0.59928", \ + "0.0106725, 0.0511223, 0.0818214, 0.132895, 0.21846, 0.362529, 0.599281", \ + "0.011144, 0.051201, 0.081864, 0.132896, 0.218474, 0.36253, 0.599282", \ + "0.01208, 0.051405, 0.081923, 0.132946, 0.218486, 0.362531, 0.599283" \ ); } cell_fall (TIMING_DELAY_7x7ds1) { index_1 ("0.0186, 0.0966, 0.174, 0.3294, 0.6408, 1.263, 2.5074"); index_2 ("0.001, 0.0234, 0.039, 0.0648, 0.108, 0.18, 0.3"); values ( \ - "0.0838875, 0.11023, 0.127716, 0.156585, 0.204729, 0.285116, 0.418908", \ + "0.0838558, 0.110229, 0.127716, 0.156585, 0.204731, 0.285061, 0.418926", \ "0.102327, 0.128737, 0.146214, 0.17504, 0.223236, 0.303532, 0.437463", \ "0.114388, 0.140753, 0.158245, 0.187065, 0.235261, 0.315514, 0.449321", \ "0.131435, 0.157825, 0.175323, 0.204143, 0.252355, 0.332629, 0.466391", \ @@ -28408,18 +28504,19 @@ library (sg13g2_stdcell_fast_1p65V_m40C) { index_1 ("0.0186, 0.0966, 0.174, 0.3294, 0.6408, 1.263, 2.5074"); index_2 ("0.001, 0.0234, 0.039, 0.0648, 0.108, 0.18, 0.3"); values ( \ - "0.0085456, 0.0411824, 0.0653034, 0.105601, 0.173364, 0.286284, 0.474661", \ - "0.0085466, 0.0411834, 0.0653339, 0.105611, 0.173365, 0.286285, 0.474673", \ - "0.0085476, 0.0411844, 0.0653349, 0.105612, 0.173366, 0.286303, 0.474674", \ - "0.0085486, 0.0411854, 0.0653359, 0.105613, 0.173367, 0.286304, 0.474675", \ - "0.0085496, 0.0411864, 0.0653369, 0.105615, 0.173368, 0.286305, 0.474676", \ - "0.0085506, 0.0411874, 0.0653379, 0.105616, 0.173369, 0.286306, 0.474677", \ - "0.00856, 0.0411884, 0.0653389, 0.105619, 0.17337, 0.286388, 0.474769" \ + "0.0085455, 0.041206, 0.0653034, 0.105601, 0.173365, 0.286476, 0.474661", \ + "0.0085465, 0.041207, 0.0653339, 0.105611, 0.173366, 0.286477, 0.474673", \ + "0.0085475, 0.041208, 0.0653349, 0.105612, 0.173367, 0.286478, 0.474674", \ + "0.0085485, 0.041209, 0.0653359, 0.105613, 0.173368, 0.286479, 0.474675", \ + "0.0085495, 0.04121, 0.0653369, 0.105615, 0.173369, 0.28648, 0.474676", \ + "0.0085505, 0.041211, 0.0653379, 0.105616, 0.17337, 0.286481, 0.474677", \ + "0.00856, 0.041212, 0.0653389, 0.105619, 0.173371, 0.286482, 0.474769" \ ); } } timing () { related_pin : "RESET_B"; + sdf_edges : start_edge; timing_sense : positive_unate; timing_type : clear; cell_fall (TIMING_DELAY_7x7ds1) { @@ -28440,7 +28537,7 @@ library (sg13g2_stdcell_fast_1p65V_m40C) { index_2 ("0.001, 0.0234, 0.039, 0.0648, 0.108, 0.18, 0.3"); values ( \ "0.0084741, 0.0411765, 0.0652688, 0.105595, 0.17331, 0.286295, 0.474656", \ - "0.0084775, 0.0411775, 0.0652698, 0.105596, 0.173317, 0.286296, 0.475092", \ + "0.0084777, 0.0411775, 0.0652698, 0.105596, 0.173317, 0.286296, 0.475092", \ "0.0085054, 0.0411785, 0.0652708, 0.105597, 0.173318, 0.286297, 0.475093", \ "0.0085574, 0.0411795, 0.0652718, 0.105598, 0.173319, 0.286298, 0.475094", \ "0.008624, 0.0411805, 0.0652728, 0.105599, 0.17332, 0.286299, 0.475095", \ @@ -28456,7 +28553,7 @@ library (sg13g2_stdcell_fast_1p65V_m40C) { index_1 ("0.0186, 0.0966, 0.174, 0.3294, 0.6408, 1.263, 2.5074"); index_2 ("0.001, 0.0234, 0.039, 0.0648, 0.108, 0.18, 0.3"); values ( \ - "0.0623665, 0.0922717, 0.113534, 0.148642, 0.20726, 0.304856, 0.467145", \ + "0.0623429, 0.0922304, 0.113533, 0.14868, 0.207255, 0.304856, 0.46743", \ "0.0646608, 0.0943484, 0.115636, 0.151079, 0.209596, 0.307889, 0.469127", \ "0.0680773, 0.0978299, 0.119168, 0.154172, 0.212904, 0.310289, 0.475512", \ "0.076616, 0.106128, 0.127475, 0.162734, 0.221358, 0.318818, 0.482955", \ @@ -28469,12 +28566,12 @@ library (sg13g2_stdcell_fast_1p65V_m40C) { index_1 ("0.0186, 0.0966, 0.174, 0.3294, 0.6408, 1.263, 2.5074"); index_2 ("0.001, 0.0234, 0.039, 0.0648, 0.108, 0.18, 0.3"); values ( \ - "0.0638949, 0.094498, 0.115715, 0.150725, 0.209034, 0.306144, 0.46787", \ + "0.0638708, 0.0945131, 0.115715, 0.150725, 0.209033, 0.306239, 0.467866", \ "0.0662734, 0.0969419, 0.11811, 0.153453, 0.211561, 0.310486, 0.470229", \ - "0.0697273, 0.100569, 0.121932, 0.156619, 0.21502, 0.314371, 0.473604", \ + "0.0697273, 0.100567, 0.121932, 0.156619, 0.21502, 0.314371, 0.473604", \ "0.0782096, 0.108675, 0.130182, 0.165503, 0.22409, 0.320916, 0.483634", \ "0.095432, 0.126001, 0.147457, 0.182498, 0.241653, 0.339475, 0.501345", \ - "0.130888, 0.161394, 0.182479, 0.217419, 0.276627, 0.374451, 0.537922", \ + "0.130888, 0.161393, 0.182479, 0.217419, 0.276627, 0.374451, 0.537922", \ "0.202803, 0.232942, 0.254035, 0.289274, 0.347612, 0.445053, 0.608326" \ ); } @@ -28485,7 +28582,7 @@ library (sg13g2_stdcell_fast_1p65V_m40C) { index_1 ("0.0186, 0.0966, 0.174, 0.3294, 0.6408, 1.263, 2.5074"); index_2 ("0.001, 0.0234, 0.039, 0.0648, 0.108, 0.18, 0.3"); values ( \ - "0.0623665, 0.0922717, 0.113534, 0.148642, 0.20726, 0.304856, 0.467145", \ + "0.0623429, 0.0922304, 0.113533, 0.14868, 0.207255, 0.304856, 0.46743", \ "0.0646608, 0.0943484, 0.115636, 0.151079, 0.209596, 0.307889, 0.469127", \ "0.0680773, 0.0978299, 0.119168, 0.154172, 0.212904, 0.310289, 0.475512", \ "0.076616, 0.106128, 0.127475, 0.162734, 0.221358, 0.318818, 0.482955", \ @@ -28498,12 +28595,12 @@ library (sg13g2_stdcell_fast_1p65V_m40C) { index_1 ("0.0186, 0.0966, 0.174, 0.3294, 0.6408, 1.263, 2.5074"); index_2 ("0.001, 0.0234, 0.039, 0.0648, 0.108, 0.18, 0.3"); values ( \ - "0.0638949, 0.094498, 0.115715, 0.150725, 0.209034, 0.306144, 0.46787", \ + "0.0638708, 0.0945131, 0.115715, 0.150725, 0.209033, 0.306239, 0.467866", \ "0.0662734, 0.0969419, 0.11811, 0.153453, 0.211561, 0.310486, 0.470229", \ - "0.0697273, 0.100569, 0.121932, 0.156619, 0.21502, 0.314371, 0.473604", \ + "0.0697273, 0.100567, 0.121932, 0.156619, 0.21502, 0.314371, 0.473604", \ "0.0782096, 0.108675, 0.130182, 0.165503, 0.22409, 0.320916, 0.483634", \ "0.095432, 0.126001, 0.147457, 0.182498, 0.241653, 0.339475, 0.501345", \ - "0.130888, 0.161394, 0.182479, 0.217419, 0.276627, 0.374451, 0.537922", \ + "0.130888, 0.161393, 0.182479, 0.217419, 0.276627, 0.374451, 0.537922", \ "0.202803, 0.232942, 0.254035, 0.289274, 0.347612, 0.445053, 0.608326" \ ); } @@ -28520,7 +28617,7 @@ library (sg13g2_stdcell_fast_1p65V_m40C) { index_2 ("0.001, 0.0234, 0.039, 0.0648, 0.108, 0.18, 0.3"); values ( \ "0.0890548, 0.131834, 0.160937, 0.206183, 0.275335, 0.381294, 0.549479", \ - "0.0940229, 0.136866, 0.166616, 0.214931, 0.290222, 0.404373, 0.580807", \ + "0.0940226, 0.136866, 0.166616, 0.214931, 0.290222, 0.404373, 0.580807", \ "0.0980846, 0.140923, 0.17057, 0.219133, 0.298352, 0.418306, 0.602262", \ "0.107, 0.149563, 0.179432, 0.228621, 0.309494, 0.438082, 0.638256", \ "0.125769, 0.16762, 0.197344, 0.246316, 0.328855, 0.4644, 0.677334", \ @@ -28538,6 +28635,7 @@ library (sg13g2_stdcell_fast_1p65V_m40C) { timing () { related_pin : "CLK"; sdf_cond : "SCE == 1'b1"; + sdf_edges : start_edge; timing_sense : non_unate; timing_type : rising_edge; when : "SCE"; @@ -28545,7 +28643,7 @@ library (sg13g2_stdcell_fast_1p65V_m40C) { index_1 ("0.0186, 0.0966, 0.174, 0.3294, 0.6408, 1.263, 2.5074"); index_2 ("0.001, 0.0234, 0.039, 0.0648, 0.108, 0.18, 0.3"); values ( \ - "0.0651915, 0.10593, 0.127649, 0.162082, 0.218893, 0.313415, 0.470682", \ + "0.0651937, 0.10593, 0.127649, 0.162088, 0.218916, 0.313404, 0.470559", \ "0.0836899, 0.124369, 0.146099, 0.180473, 0.237321, 0.331749, 0.488974", \ "0.0957137, 0.136423, 0.158155, 0.192523, 0.249347, 0.34377, 0.501004", \ "0.112823, 0.153399, 0.175152, 0.209523, 0.26634, 0.360771, 0.517958", \ @@ -28558,20 +28656,20 @@ library (sg13g2_stdcell_fast_1p65V_m40C) { index_1 ("0.0186, 0.0966, 0.174, 0.3294, 0.6408, 1.263, 2.5074"); index_2 ("0.001, 0.0234, 0.039, 0.0648, 0.108, 0.18, 0.3"); values ( \ - "0.0131042, 0.0564432, 0.0849534, 0.133921, 0.217945, 0.359571, 0.595684", \ - "0.0131052, 0.0564442, 0.084955, 0.133922, 0.217957, 0.359772, 0.596536", \ - "0.0131062, 0.0564452, 0.0849644, 0.133923, 0.217958, 0.359773, 0.596537", \ - "0.0131072, 0.0564462, 0.0849846, 0.133924, 0.217959, 0.359774, 0.596538", \ - "0.0131082, 0.0564472, 0.0849856, 0.133925, 0.21796, 0.359775, 0.596539", \ - "0.0131092, 0.0564482, 0.0849866, 0.133926, 0.217961, 0.359776, 0.59654", \ - "0.013308, 0.0564492, 0.0849876, 0.133927, 0.217962, 0.359777, 0.596541" \ + "0.0131052, 0.0564432, 0.0849534, 0.133919, 0.217945, 0.359569, 0.595755", \ + "0.0131062, 0.0564442, 0.084955, 0.13392, 0.217957, 0.359772, 0.596536", \ + "0.0131072, 0.0564452, 0.0849644, 0.133921, 0.217958, 0.359773, 0.596537", \ + "0.0131082, 0.0564462, 0.0849846, 0.133922, 0.217959, 0.359774, 0.596538", \ + "0.0131092, 0.0564472, 0.0849856, 0.133923, 0.21796, 0.359775, 0.596539", \ + "0.0131102, 0.0564482, 0.0849866, 0.133924, 0.217961, 0.359776, 0.59654", \ + "0.013308, 0.0564492, 0.0849876, 0.133925, 0.217962, 0.359777, 0.596541" \ ); } cell_fall (TIMING_DELAY_7x7ds1) { index_1 ("0.0186, 0.0966, 0.174, 0.3294, 0.6408, 1.263, 2.5074"); index_2 ("0.001, 0.0234, 0.039, 0.0648, 0.108, 0.18, 0.3"); values ( \ - "0.068136, 0.111511, 0.132033, 0.162797, 0.212101, 0.293173, 0.428077", \ + "0.0681497, 0.111514, 0.132036, 0.162798, 0.212102, 0.293175, 0.428076", \ "0.0871667, 0.130491, 0.151052, 0.18181, 0.23109, 0.312218, 0.447168", \ "0.0998113, 0.143116, 0.163698, 0.19448, 0.243784, 0.324828, 0.459679", \ "0.118488, 0.161905, 0.182529, 0.213307, 0.262593, 0.34368, 0.478517", \ @@ -28584,25 +28682,26 @@ library (sg13g2_stdcell_fast_1p65V_m40C) { index_1 ("0.0186, 0.0966, 0.174, 0.3294, 0.6408, 1.263, 2.5074"); index_2 ("0.001, 0.0234, 0.039, 0.0648, 0.108, 0.18, 0.3"); values ( \ - "0.0153795, 0.0530935, 0.074825, 0.112279, 0.177984, 0.290173, 0.479854", \ - "0.0155023, 0.0531236, 0.0749691, 0.112316, 0.177985, 0.290356, 0.479855", \ - "0.0156688, 0.0531834, 0.0749801, 0.112354, 0.177986, 0.290357, 0.479856", \ - "0.0161179, 0.0534926, 0.0751279, 0.112387, 0.177987, 0.290358, 0.479857", \ - "0.0173996, 0.054091, 0.0755597, 0.11274, 0.178175, 0.29042, 0.479858", \ - "0.019884, 0.055834, 0.07671, 0.11349, 0.178522, 0.290611, 0.479859", \ + "0.0153907, 0.0530815, 0.0748725, 0.112279, 0.177985, 0.290176, 0.479432", \ + "0.0155023, 0.0531236, 0.0749691, 0.112316, 0.177986, 0.290356, 0.479601", \ + "0.0156688, 0.0531834, 0.0749801, 0.112354, 0.177987, 0.290357, 0.479602", \ + "0.0161179, 0.0534926, 0.0751279, 0.112387, 0.177988, 0.290358, 0.479603", \ + "0.0173996, 0.054091, 0.0755597, 0.11274, 0.178175, 0.29042, 0.479604", \ + "0.019884, 0.055834, 0.07671, 0.11349, 0.178522, 0.290611, 0.479628", \ "0.024002, 0.059522, 0.079412, 0.115117, 0.17949, 0.291051, 0.479978" \ ); } } timing () { related_pin : "CLK"; + sdf_edges : start_edge; timing_sense : non_unate; timing_type : rising_edge; cell_rise (TIMING_DELAY_7x7ds1) { index_1 ("0.0186, 0.0966, 0.174, 0.3294, 0.6408, 1.263, 2.5074"); index_2 ("0.001, 0.0234, 0.039, 0.0648, 0.108, 0.18, 0.3"); values ( \ - "0.0651915, 0.10593, 0.127649, 0.162082, 0.218893, 0.313415, 0.470682", \ + "0.0651937, 0.10593, 0.127649, 0.162088, 0.218916, 0.313404, 0.470559", \ "0.0836899, 0.124369, 0.146099, 0.180473, 0.237321, 0.331749, 0.488974", \ "0.0957137, 0.136423, 0.158155, 0.192523, 0.249347, 0.34377, 0.501004", \ "0.112823, 0.153399, 0.175152, 0.209523, 0.26634, 0.360771, 0.517958", \ @@ -28615,20 +28714,20 @@ library (sg13g2_stdcell_fast_1p65V_m40C) { index_1 ("0.0186, 0.0966, 0.174, 0.3294, 0.6408, 1.263, 2.5074"); index_2 ("0.001, 0.0234, 0.039, 0.0648, 0.108, 0.18, 0.3"); values ( \ - "0.0131042, 0.0564432, 0.0849534, 0.133921, 0.217945, 0.359571, 0.595684", \ - "0.0131052, 0.0564442, 0.084955, 0.133922, 0.217957, 0.359772, 0.596536", \ - "0.0131062, 0.0564452, 0.0849644, 0.133923, 0.217958, 0.359773, 0.596537", \ - "0.0131072, 0.0564462, 0.0849846, 0.133924, 0.217959, 0.359774, 0.596538", \ - "0.0131082, 0.0564472, 0.0849856, 0.133925, 0.21796, 0.359775, 0.596539", \ - "0.0131092, 0.0564482, 0.0849866, 0.133926, 0.217961, 0.359776, 0.59654", \ - "0.013308, 0.0564492, 0.0849876, 0.133927, 0.217962, 0.359777, 0.596541" \ + "0.0131052, 0.0564432, 0.0849534, 0.133919, 0.217945, 0.359569, 0.595755", \ + "0.0131062, 0.0564442, 0.084955, 0.13392, 0.217957, 0.359772, 0.596536", \ + "0.0131072, 0.0564452, 0.0849644, 0.133921, 0.217958, 0.359773, 0.596537", \ + "0.0131082, 0.0564462, 0.0849846, 0.133922, 0.217959, 0.359774, 0.596538", \ + "0.0131092, 0.0564472, 0.0849856, 0.133923, 0.21796, 0.359775, 0.596539", \ + "0.0131102, 0.0564482, 0.0849866, 0.133924, 0.217961, 0.359776, 0.59654", \ + "0.013308, 0.0564492, 0.0849876, 0.133925, 0.217962, 0.359777, 0.596541" \ ); } cell_fall (TIMING_DELAY_7x7ds1) { index_1 ("0.0186, 0.0966, 0.174, 0.3294, 0.6408, 1.263, 2.5074"); index_2 ("0.001, 0.0234, 0.039, 0.0648, 0.108, 0.18, 0.3"); values ( \ - "0.068136, 0.111511, 0.132033, 0.162797, 0.212101, 0.293173, 0.428077", \ + "0.0681497, 0.111514, 0.132036, 0.162798, 0.212102, 0.293175, 0.428076", \ "0.0871667, 0.130491, 0.151052, 0.18181, 0.23109, 0.312218, 0.447168", \ "0.0998113, 0.143116, 0.163698, 0.19448, 0.243784, 0.324828, 0.459679", \ "0.118488, 0.161905, 0.182529, 0.213307, 0.262593, 0.34368, 0.478517", \ @@ -28641,18 +28740,19 @@ library (sg13g2_stdcell_fast_1p65V_m40C) { index_1 ("0.0186, 0.0966, 0.174, 0.3294, 0.6408, 1.263, 2.5074"); index_2 ("0.001, 0.0234, 0.039, 0.0648, 0.108, 0.18, 0.3"); values ( \ - "0.0153795, 0.0530935, 0.074825, 0.112279, 0.177984, 0.290173, 0.479854", \ - "0.0155023, 0.0531236, 0.0749691, 0.112316, 0.177985, 0.290356, 0.479855", \ - "0.0156688, 0.0531834, 0.0749801, 0.112354, 0.177986, 0.290357, 0.479856", \ - "0.0161179, 0.0534926, 0.0751279, 0.112387, 0.177987, 0.290358, 0.479857", \ - "0.0173996, 0.054091, 0.0755597, 0.11274, 0.178175, 0.29042, 0.479858", \ - "0.019884, 0.055834, 0.07671, 0.11349, 0.178522, 0.290611, 0.479859", \ + "0.0153907, 0.0530815, 0.0748725, 0.112279, 0.177985, 0.290176, 0.479432", \ + "0.0155023, 0.0531236, 0.0749691, 0.112316, 0.177986, 0.290356, 0.479601", \ + "0.0156688, 0.0531834, 0.0749801, 0.112354, 0.177987, 0.290357, 0.479602", \ + "0.0161179, 0.0534926, 0.0751279, 0.112387, 0.177988, 0.290358, 0.479603", \ + "0.0173996, 0.054091, 0.0755597, 0.11274, 0.178175, 0.29042, 0.479604", \ + "0.019884, 0.055834, 0.07671, 0.11349, 0.178522, 0.290611, 0.479628", \ "0.024002, 0.059522, 0.079412, 0.115117, 0.17949, 0.291051, 0.479978" \ ); } } timing () { related_pin : "RESET_B"; + sdf_edges : start_edge; timing_sense : negative_unate; timing_type : preset; cell_rise (TIMING_DELAY_7x7ds1) { @@ -28673,7 +28773,7 @@ library (sg13g2_stdcell_fast_1p65V_m40C) { index_2 ("0.001, 0.0234, 0.039, 0.0648, 0.108, 0.18, 0.3"); values ( \ "0.0132404, 0.0556307, 0.0843766, 0.13357, 0.21784, 0.35937, 0.595729", \ - "0.0133218, 0.0556593, 0.0843776, 0.133571, 0.217841, 0.360261, 0.59573", \ + "0.0133218, 0.0556591, 0.0843776, 0.133571, 0.217841, 0.360261, 0.59573", \ "0.013465, 0.0557107, 0.0843955, 0.133572, 0.217842, 0.360262, 0.597517", \ "0.0137242, 0.0558629, 0.0844696, 0.133573, 0.217843, 0.360263, 0.597518", \ "0.014125, 0.0560924, 0.0846281, 0.13365, 0.217866, 0.360264, 0.597519", \ @@ -28689,11 +28789,11 @@ library (sg13g2_stdcell_fast_1p65V_m40C) { index_1 ("0.0186, 0.0966, 0.174, 0.3294, 0.6408, 1.263, 2.5074"); index_2 ("0.001, 0.0234, 0.039, 0.0648, 0.108, 0.18, 0.3"); values ( \ - "0.0638194, 0.0946676, 0.115957, 0.151184, 0.209746, 0.307461, 0.469634", \ + "0.0638141, 0.094667, 0.115957, 0.151158, 0.209779, 0.307414, 0.469748", \ "0.0662492, 0.0970531, 0.118402, 0.15372, 0.212214, 0.309784, 0.472903", \ "0.0697345, 0.100664, 0.121981, 0.15696, 0.21583, 0.313241, 0.477389", \ "0.0781827, 0.10885, 0.130218, 0.165573, 0.224079, 0.321635, 0.485515", \ - "0.095373, 0.126181, 0.14755, 0.182821, 0.241731, 0.339624, 0.502199", \ + "0.095373, 0.12618, 0.14755, 0.182821, 0.241731, 0.339624, 0.502199", \ "0.130791, 0.161561, 0.182664, 0.217904, 0.276648, 0.374858, 0.538083", \ "0.202554, 0.233391, 0.254437, 0.289703, 0.347872, 0.446032, 0.609159" \ ); @@ -28702,7 +28802,7 @@ library (sg13g2_stdcell_fast_1p65V_m40C) { index_1 ("0.0186, 0.0966, 0.174, 0.3294, 0.6408, 1.263, 2.5074"); index_2 ("0.001, 0.0234, 0.039, 0.0648, 0.108, 0.18, 0.3"); values ( \ - "0.0624562, 0.0921643, 0.113346, 0.148282, 0.206634, 0.303632, 0.465617", \ + "0.0623764, 0.0921689, 0.113335, 0.148266, 0.20663, 0.303597, 0.465222", \ "0.0646322, 0.0943254, 0.115465, 0.150794, 0.208729, 0.30684, 0.467636", \ "0.0680896, 0.0978154, 0.119101, 0.15382, 0.212257, 0.311166, 0.471367", \ "0.076586, 0.106026, 0.127488, 0.162657, 0.221133, 0.318046, 0.481978", \ @@ -28718,11 +28818,11 @@ library (sg13g2_stdcell_fast_1p65V_m40C) { index_1 ("0.0186, 0.0966, 0.174, 0.3294, 0.6408, 1.263, 2.5074"); index_2 ("0.001, 0.0234, 0.039, 0.0648, 0.108, 0.18, 0.3"); values ( \ - "0.0638194, 0.0946676, 0.115957, 0.151184, 0.209746, 0.307461, 0.469634", \ + "0.0638141, 0.094667, 0.115957, 0.151158, 0.209779, 0.307414, 0.469748", \ "0.0662492, 0.0970531, 0.118402, 0.15372, 0.212214, 0.309784, 0.472903", \ "0.0697345, 0.100664, 0.121981, 0.15696, 0.21583, 0.313241, 0.477389", \ "0.0781827, 0.10885, 0.130218, 0.165573, 0.224079, 0.321635, 0.485515", \ - "0.095373, 0.126181, 0.14755, 0.182821, 0.241731, 0.339624, 0.502199", \ + "0.095373, 0.12618, 0.14755, 0.182821, 0.241731, 0.339624, 0.502199", \ "0.130791, 0.161561, 0.182664, 0.217904, 0.276648, 0.374858, 0.538083", \ "0.202554, 0.233391, 0.254437, 0.289703, 0.347872, 0.446032, 0.609159" \ ); @@ -28731,7 +28831,7 @@ library (sg13g2_stdcell_fast_1p65V_m40C) { index_1 ("0.0186, 0.0966, 0.174, 0.3294, 0.6408, 1.263, 2.5074"); index_2 ("0.001, 0.0234, 0.039, 0.0648, 0.108, 0.18, 0.3"); values ( \ - "0.0624562, 0.0921643, 0.113346, 0.148282, 0.206634, 0.303632, 0.465617", \ + "0.0623764, 0.0921689, 0.113335, 0.148266, 0.20663, 0.303597, 0.465222", \ "0.0646322, 0.0943254, 0.115465, 0.150794, 0.208729, 0.30684, 0.467636", \ "0.0680896, 0.0978154, 0.119101, 0.15382, 0.212257, 0.311166, 0.471367", \ "0.076586, 0.106026, 0.127488, 0.162657, 0.221133, 0.318046, 0.481978", \ @@ -28748,7 +28848,7 @@ library (sg13g2_stdcell_fast_1p65V_m40C) { index_2 ("0.001, 0.0234, 0.039, 0.0648, 0.108, 0.18, 0.3"); values ( \ "0.0887175, 0.125622, 0.150594, 0.188956, 0.246582, 0.333418, 0.469778", \ - "0.0937488, 0.130643, 0.156195, 0.197625, 0.261047, 0.357065, 0.500476", \ + "0.0937488, 0.130642, 0.156195, 0.197625, 0.261078, 0.357065, 0.500476", \ "0.0977348, 0.134597, 0.160007, 0.201832, 0.269434, 0.371036, 0.523292", \ "0.106614, 0.14333, 0.16888, 0.211092, 0.280434, 0.390383, 0.554015", \ "0.125327, 0.161404, 0.186946, 0.22885, 0.299578, 0.415535, 0.596593", \ @@ -28769,9 +28869,9 @@ library (sg13g2_stdcell_fast_1p65V_m40C) { max_transition : 2.5074; capacitance : 0.00333557; rise_capacitance : 0.00339022; - rise_capacitance_range (0.00339022, 0.00339022); + rise_capacitance_range (0.00297349, 0.00374513); fall_capacitance : 0.0032653; - fall_capacitance_range (0.0032653, 0.0032653); + fall_capacitance_range (0.00294992, 0.00352645); timing () { related_pin : "CLK"; timing_type : min_pulse_width; @@ -28787,7 +28887,7 @@ library (sg13g2_stdcell_fast_1p65V_m40C) { rise_power (passive_POWER_7x1ds1) { index_1 ("0.0186, 0.0966, 0.174, 0.3294, 0.6408, 1.263, 2.5074"); values ( \ - "0.0184605, 0.0206176, 0.0240233, 0.031933, 0.0485984, 0.0832255, 0.155551" \ + "0.0184619, 0.0206176, 0.0240233, 0.031933, 0.0485984, 0.0832255, 0.155551" \ ); } fall_power (passive_POWER_7x1ds1) { @@ -28807,7 +28907,7 @@ library (sg13g2_stdcell_fast_1p65V_m40C) { fall_power (passive_POWER_7x1ds1) { index_1 ("0.0186, 0.0966, 0.174, 0.3294, 0.6408, 1.263, 2.5074"); values ( \ - "0.04001, 0.042437, 0.0460892, 0.0542146, 0.0713334, 0.106099, 0.178277" \ + "0.0400295, 0.042437, 0.0460892, 0.0542146, 0.0713334, 0.106099, 0.178277" \ ); } } @@ -28830,7 +28930,7 @@ library (sg13g2_stdcell_fast_1p65V_m40C) { rise_power (passive_POWER_7x1ds1) { index_1 ("0.0186, 0.0966, 0.174, 0.3294, 0.6408, 1.263, 2.5074"); values ( \ - "0.0180448, 0.0201815, 0.0235546, 0.0314813, 0.0481888, 0.0828052, 0.155059" \ + "0.0180449, 0.0201815, 0.0235546, 0.0314813, 0.0481888, 0.0828052, 0.155059" \ ); } fall_power (passive_POWER_7x1ds1) { @@ -28845,13 +28945,13 @@ library (sg13g2_stdcell_fast_1p65V_m40C) { rise_power (passive_POWER_7x1ds1) { index_1 ("0.0186, 0.0966, 0.174, 0.3294, 0.6408, 1.263, 2.5074"); values ( \ - "0.0184676, 0.0206182, 0.0240234, 0.0319329, 0.0485987, 0.0832245, 0.155552" \ + "0.0184902, 0.0206182, 0.0240234, 0.0319329, 0.0485986, 0.0832245, 0.155552" \ ); } fall_power (passive_POWER_7x1ds1) { index_1 ("0.0186, 0.0966, 0.174, 0.3294, 0.6408, 1.263, 2.5074"); values ( \ - "0.0198317, 0.0222984, 0.0258543, 0.0335789, 0.0501631, 0.0835771, 0.153101" \ + "0.0198317, 0.0222985, 0.0258543, 0.0335789, 0.0501631, 0.0835771, 0.153101" \ ); } } @@ -28866,7 +28966,7 @@ library (sg13g2_stdcell_fast_1p65V_m40C) { fall_power (passive_POWER_7x1ds1) { index_1 ("0.0186, 0.0966, 0.174, 0.3294, 0.6408, 1.263, 2.5074"); values ( \ - "0.00883233, 0.0113127, 0.0148351, 0.0225556, 0.0391073, 0.072483, 0.142049" \ + "0.00883234, 0.0113127, 0.0148352, 0.0225556, 0.0391073, 0.072483, 0.142049" \ ); } } @@ -28875,7 +28975,7 @@ library (sg13g2_stdcell_fast_1p65V_m40C) { rise_power (passive_POWER_7x1ds1) { index_1 ("0.0186, 0.0966, 0.174, 0.3294, 0.6408, 1.263, 2.5074"); values ( \ - "0.0180395, 0.0201819, 0.0235539, 0.0314825, 0.0481894, 0.0828056, 0.155059" \ + "0.0180394, 0.0201819, 0.0235539, 0.0314825, 0.0481894, 0.0828056, 0.155059" \ ); } fall_power (passive_POWER_7x1ds1) { @@ -28889,7 +28989,7 @@ library (sg13g2_stdcell_fast_1p65V_m40C) { rise_power (passive_POWER_7x1ds1) { index_1 ("0.0186, 0.0966, 0.174, 0.3294, 0.6408, 1.263, 2.5074"); values ( \ - "0.0180395, 0.0201819, 0.0235539, 0.0314825, 0.0481894, 0.0828056, 0.155059" \ + "0.0180394, 0.0201819, 0.0235539, 0.0314825, 0.0481894, 0.0828056, 0.155059" \ ); } fall_power (passive_POWER_7x1ds1) { @@ -28906,11 +29006,12 @@ library (sg13g2_stdcell_fast_1p65V_m40C) { max_transition : 2.5074; capacitance : 0.00312058; rise_capacitance : 0.00320591; - rise_capacitance_range (0.00320591, 0.00320591); + rise_capacitance_range (0.00266047, 0.00365775); fall_capacitance : 0.00303526; - fall_capacitance_range (0.00303526, 0.00303526); + fall_capacitance_range (0.00266068, 0.00322829); timing () { related_pin : "CLK"; + sdf_edges : both_edges; timing_type : hold_rising; rise_constraint (CONSTRAINT_4x4) { index_1 ("0.0186, 0.51636, 1.263, 2.5074"); @@ -28935,6 +29036,7 @@ library (sg13g2_stdcell_fast_1p65V_m40C) { } timing () { related_pin : "CLK"; + sdf_edges : both_edges; timing_type : setup_rising; rise_constraint (CONSTRAINT_4x4) { index_1 ("0.0186, 0.51636, 1.263, 2.5074"); @@ -28962,7 +29064,7 @@ library (sg13g2_stdcell_fast_1p65V_m40C) { rise_power (passive_POWER_7x1ds1) { index_1 ("0.0186, 0.0966, 0.174, 0.3294, 0.6408, 1.263, 2.5074"); values ( \ - "0.0377562, 0.0390101, 0.0414927, 0.0472219, 0.0598993, 0.0858544, 0.138601" \ + "0.0377571, 0.0390101, 0.0414927, 0.0472219, 0.0598993, 0.0858544, 0.138601" \ ); } fall_power (passive_POWER_7x1ds1) { @@ -28976,7 +29078,7 @@ library (sg13g2_stdcell_fast_1p65V_m40C) { rise_power (passive_POWER_7x1ds1) { index_1 ("0.0186, 0.0966, 0.174, 0.3294, 0.6408, 1.263, 2.5074"); values ( \ - "0.0377562, 0.0390101, 0.0414927, 0.0472219, 0.0598993, 0.0858544, 0.138601" \ + "0.0377571, 0.0390101, 0.0414927, 0.0472219, 0.0598993, 0.0858544, 0.138601" \ ); } fall_power (passive_POWER_7x1ds1) { @@ -28994,9 +29096,10 @@ library (sg13g2_stdcell_fast_1p65V_m40C) { rise_capacitance : 0.00561734; rise_capacitance_range (0.00561734, 0.00561734); fall_capacitance : 0.00561734; - fall_capacitance_range (0.00561734, 0.00561734); + fall_capacitance_range (0.00545059, 0.00579046); timing () { related_pin : "CLK"; + sdf_edges : both_edges; timing_type : recovery_rising; rise_constraint (CONSTRAINT_4x4) { index_1 ("0.0186, 0.51636, 1.263, 2.5074"); @@ -29011,6 +29114,7 @@ library (sg13g2_stdcell_fast_1p65V_m40C) { } timing () { related_pin : "CLK"; + sdf_edges : both_edges; timing_type : removal_rising; rise_constraint (CONSTRAINT_4x4) { index_1 ("0.0186, 0.51636, 1.263, 2.5074"); @@ -29040,11 +29144,12 @@ library (sg13g2_stdcell_fast_1p65V_m40C) { max_transition : 2.5074; capacitance : 0.00325308; rise_capacitance : 0.00330977; - rise_capacitance_range (0.00330977, 0.00330977); + rise_capacitance_range (0.00277162, 0.0037606); fall_capacitance : 0.00313971; - fall_capacitance_range (0.00313971, 0.00313971); + fall_capacitance_range (0.00276677, 0.00333187); timing () { related_pin : "CLK"; + sdf_edges : both_edges; timing_type : hold_rising; rise_constraint (CONSTRAINT_4x4) { index_1 ("0.0186, 0.51636, 1.263, 2.5074"); @@ -29052,7 +29157,7 @@ library (sg13g2_stdcell_fast_1p65V_m40C) { values ( \ "-0.0684653, -0.050163, -0.0401494, -0.0359068", \ "-0.124545, -0.106951, -0.0986846, -0.0928683", \ - "-0.152734, -0.137332, -0.126823, -0.123007", \ + "-0.155306, -0.137332, -0.126823, -0.123007", \ "-0.16647, -0.149044, -0.139714, -0.135771" \ ); } @@ -29069,6 +29174,7 @@ library (sg13g2_stdcell_fast_1p65V_m40C) { } timing () { related_pin : "CLK"; + sdf_edges : both_edges; timing_type : setup_rising; rise_constraint (CONSTRAINT_4x4) { index_1 ("0.0186, 0.51636, 1.263, 2.5074"); @@ -29096,7 +29202,7 @@ library (sg13g2_stdcell_fast_1p65V_m40C) { rise_power (passive_POWER_7x1ds1) { index_1 ("0.0186, 0.0966, 0.174, 0.3294, 0.6408, 1.263, 2.5074"); values ( \ - "0.0385395, 0.0398576, 0.0423422, 0.0480259, 0.0607698, 0.0868255, 0.139439" \ + "0.0385642, 0.0398576, 0.0423422, 0.0480259, 0.0607698, 0.0868255, 0.139439" \ ); } fall_power (passive_POWER_7x1ds1) { @@ -29110,7 +29216,7 @@ library (sg13g2_stdcell_fast_1p65V_m40C) { rise_power (passive_POWER_7x1ds1) { index_1 ("0.0186, 0.0966, 0.174, 0.3294, 0.6408, 1.263, 2.5074"); values ( \ - "0.0385395, 0.0398576, 0.0423422, 0.0480259, 0.0607698, 0.0868255, 0.139439" \ + "0.0385642, 0.0398576, 0.0423422, 0.0480259, 0.0607698, 0.0868255, 0.139439" \ ); } fall_power (passive_POWER_7x1ds1) { @@ -29127,11 +29233,12 @@ library (sg13g2_stdcell_fast_1p65V_m40C) { max_transition : 2.5074; capacitance : 0.00558352; rise_capacitance : 0.00594942; - rise_capacitance_range (0.00594942, 0.00594942); + rise_capacitance_range (0.0048976, 0.006562); fall_capacitance : 0.00521762; - fall_capacitance_range (0.00521762, 0.00521762); + fall_capacitance_range (0.00492736, 0.00572799); timing () { related_pin : "CLK"; + sdf_edges : both_edges; timing_type : hold_rising; rise_constraint (CONSTRAINT_4x4) { index_1 ("0.0186, 0.51636, 1.263, 2.5074"); @@ -29156,6 +29263,7 @@ library (sg13g2_stdcell_fast_1p65V_m40C) { } timing () { related_pin : "CLK"; + sdf_edges : both_edges; timing_type : setup_rising; rise_constraint (CONSTRAINT_4x4) { index_1 ("0.0186, 0.51636, 1.263, 2.5074"); @@ -29183,13 +29291,13 @@ library (sg13g2_stdcell_fast_1p65V_m40C) { rise_power (passive_POWER_7x1ds1) { index_1 ("0.0186, 0.0966, 0.174, 0.3294, 0.6408, 1.263, 2.5074"); values ( \ - "0.0399429, 0.0412545, 0.0436513, 0.0491442, 0.0610473, 0.0858362, 0.136748" \ + "0.0399431, 0.0412545, 0.0436513, 0.0491442, 0.0610473, 0.0858362, 0.136748" \ ); } fall_power (passive_POWER_7x1ds1) { index_1 ("0.0186, 0.0966, 0.174, 0.3294, 0.6408, 1.263, 2.5074"); values ( \ - "0.0499763, 0.0516472, 0.0541401, 0.0596135, 0.0712778, 0.0956962, 0.145503" \ + "0.0499763, 0.0516472, 0.0541401, 0.0596135, 0.0712777, 0.0956962, 0.145503" \ ); } } @@ -29204,7 +29312,7 @@ library (sg13g2_stdcell_fast_1p65V_m40C) { fall_power (passive_POWER_7x1ds1) { index_1 ("0.0186, 0.0966, 0.174, 0.3294, 0.6408, 1.263, 2.5074"); values ( \ - "0.0667349, 0.0804935, 0.0856477, 0.0969383, 0.121096, 0.170726, 0.270526" \ + "0.0667349, 0.0804935, 0.0856477, 0.0969384, 0.121096, 0.170726, 0.270526" \ ); } } @@ -29218,15 +29326,15 @@ library (sg13g2_stdcell_fast_1p65V_m40C) { fall_power (passive_POWER_7x1ds1) { index_1 ("0.0186, 0.0966, 0.174, 0.3294, 0.6408, 1.263, 2.5074"); values ( \ - "0.0667349, 0.0804935, 0.0856477, 0.0969383, 0.121096, 0.170726, 0.270526" \ + "0.0667349, 0.0804935, 0.0856477, 0.0969384, 0.121096, 0.170726, 0.270526" \ ); } } } ff (IQ,IQN) { - clear : "RESET_B'"; + clear : "!RESET_B"; clocked_on : "CLK"; - next_state : "(SCE*SCD)+(SCE'*D)"; + next_state : "(SCE*SCD)+(!SCE*D)"; } test_cell () { pin (Q) { @@ -29257,7 +29365,7 @@ library (sg13g2_stdcell_fast_1p65V_m40C) { signal_type : test_scan_enable; } ff (IQ,IQN) { - clear : "RESET_B'"; + clear : "!RESET_B"; clocked_on : "CLK"; next_state : "D"; } @@ -29288,11 +29396,11 @@ library (sg13g2_stdcell_fast_1p65V_m40C) { when : "CLK&!D&RESET_B&!SCD&!SCE&Q&!Q_N"; } leakage_power () { - value : 7857.47; + value : 7857.48; when : "!CLK&D&RESET_B&!SCD&!SCE&!Q&Q_N"; } leakage_power () { - value : 8032.02; + value : 8032.03; when : "!CLK&D&RESET_B&!SCD&!SCE&Q&!Q_N"; } leakage_power () { @@ -29300,7 +29408,7 @@ library (sg13g2_stdcell_fast_1p65V_m40C) { when : "CLK&D&RESET_B&!SCD&!SCE&!Q&Q_N"; } leakage_power () { - value : 8137.01; + value : 8137.02; when : "CLK&D&RESET_B&!SCD&!SCE&Q&!Q_N"; } leakage_power () { @@ -29343,6 +29451,7 @@ library (sg13g2_stdcell_fast_1p65V_m40C) { timing () { related_pin : "CLK"; sdf_cond : "SCE == 1'b1"; + sdf_edges : start_edge; timing_sense : non_unate; timing_type : rising_edge; when : "SCE"; @@ -29350,7 +29459,7 @@ library (sg13g2_stdcell_fast_1p65V_m40C) { index_1 ("0.0186, 0.0966, 0.174, 0.3294, 0.6408, 1.263, 2.5074"); index_2 ("0.001, 0.0468, 0.078, 0.1296, 0.216, 0.36, 0.6"); values ( \ - "0.113328, 0.140405, 0.160498, 0.194382, 0.251512, 0.347038, 0.50635", \ + "0.113328, 0.140406, 0.160502, 0.194382, 0.251512, 0.347037, 0.506243", \ "0.132451, 0.159493, 0.179623, 0.21349, 0.270594, 0.366075, 0.52543", \ "0.145009, 0.172054, 0.192169, 0.226057, 0.283219, 0.378605, 0.537945", \ "0.16379, 0.190752, 0.210901, 0.244752, 0.30193, 0.39735, 0.556578", \ @@ -29363,10 +29472,10 @@ library (sg13g2_stdcell_fast_1p65V_m40C) { index_1 ("0.0186, 0.0966, 0.174, 0.3294, 0.6408, 1.263, 2.5074"); index_2 ("0.001, 0.0468, 0.078, 0.1296, 0.216, 0.36, 0.6"); values ( \ - "0.0117027, 0.0523749, 0.0826275, 0.133723, 0.219594, 0.362882, 0.601644", \ - "0.0117097, 0.0523759, 0.0826285, 0.133724, 0.219595, 0.364652, 0.601678", \ - "0.0117107, 0.0523769, 0.0826295, 0.133725, 0.219596, 0.364653, 0.601679", \ - "0.0117492, 0.0523779, 0.0826305, 0.133726, 0.2196, 0.364654, 0.60168", \ + "0.0117027, 0.0523749, 0.0826269, 0.133723, 0.219594, 0.362882, 0.601614", \ + "0.0117097, 0.0523759, 0.0826279, 0.133724, 0.219595, 0.364652, 0.601678", \ + "0.0117107, 0.0523769, 0.0826289, 0.133725, 0.219596, 0.364653, 0.601679", \ + "0.0117492, 0.0523779, 0.0826299, 0.133726, 0.2196, 0.364654, 0.60168", \ "0.0118566, 0.052414, 0.082651, 0.133727, 0.219601, 0.364655, 0.601681", \ "0.012149, 0.052481, 0.082697, 0.133728, 0.219602, 0.364656, 0.601689", \ "0.012859, 0.052804, 0.082815, 0.133796, 0.219658, 0.364657, 0.601791" \ @@ -29376,7 +29485,7 @@ library (sg13g2_stdcell_fast_1p65V_m40C) { index_1 ("0.0186, 0.0966, 0.174, 0.3294, 0.6408, 1.263, 2.5074"); index_2 ("0.001, 0.0468, 0.078, 0.1296, 0.216, 0.36, 0.6"); values ( \ - "0.102081, 0.128507, 0.146071, 0.1751, 0.223736, 0.304889, 0.440128", \ + "0.102064, 0.128514, 0.146071, 0.175111, 0.223738, 0.304888, 0.440132", \ "0.12059, 0.146992, 0.164597, 0.193585, 0.242213, 0.32334, 0.458619", \ "0.132726, 0.159143, 0.176731, 0.205733, 0.254342, 0.335463, 0.470705", \ "0.149829, 0.176467, 0.194002, 0.222886, 0.271593, 0.352588, 0.487811", \ @@ -29389,25 +29498,26 @@ library (sg13g2_stdcell_fast_1p65V_m40C) { index_1 ("0.0186, 0.0966, 0.174, 0.3294, 0.6408, 1.263, 2.5074"); index_2 ("0.001, 0.0468, 0.078, 0.1296, 0.216, 0.36, 0.6"); values ( \ - "0.0102169, 0.0433362, 0.0672145, 0.107691, 0.176118, 0.290415, 0.480875", \ - "0.0102179, 0.0433372, 0.0672155, 0.107692, 0.176163, 0.290416, 0.480986", \ - "0.0102189, 0.0433614, 0.0672165, 0.107693, 0.176164, 0.290417, 0.480987", \ - "0.0102199, 0.0433624, 0.0672175, 0.107694, 0.176165, 0.290418, 0.480988", \ - "0.0102209, 0.0433634, 0.0672185, 0.107696, 0.176166, 0.290419, 0.480989", \ - "0.0102219, 0.0433644, 0.067219, 0.107697, 0.176167, 0.29042, 0.48099", \ - "0.0102229, 0.0433654, 0.06722, 0.107698, 0.176168, 0.290421, 0.480991" \ + "0.0102007, 0.0433351, 0.0672145, 0.107691, 0.176122, 0.290415, 0.480875", \ + "0.0102009, 0.0433361, 0.0672155, 0.107692, 0.176163, 0.290416, 0.480986", \ + "0.0102039, 0.0433614, 0.0672165, 0.107693, 0.176164, 0.290417, 0.480987", \ + "0.0102049, 0.0433624, 0.0672175, 0.107694, 0.176165, 0.290418, 0.480988", \ + "0.0102059, 0.0433634, 0.0672185, 0.107696, 0.176166, 0.290419, 0.480989", \ + "0.0102069, 0.0433644, 0.067219, 0.107697, 0.176167, 0.29042, 0.48099", \ + "0.0102079, 0.0433654, 0.06722, 0.107698, 0.176168, 0.290421, 0.480991" \ ); } } timing () { related_pin : "CLK"; + sdf_edges : start_edge; timing_sense : non_unate; timing_type : rising_edge; cell_rise (TIMING_DELAY_7x7ds1) { index_1 ("0.0186, 0.0966, 0.174, 0.3294, 0.6408, 1.263, 2.5074"); index_2 ("0.001, 0.0468, 0.078, 0.1296, 0.216, 0.36, 0.6"); values ( \ - "0.113328, 0.140405, 0.160498, 0.194382, 0.251512, 0.347038, 0.50635", \ + "0.113328, 0.140406, 0.160502, 0.194382, 0.251512, 0.347037, 0.506243", \ "0.132451, 0.159493, 0.179623, 0.21349, 0.270594, 0.366075, 0.52543", \ "0.145009, 0.172054, 0.192169, 0.226057, 0.283219, 0.378605, 0.537945", \ "0.16379, 0.190752, 0.210901, 0.244752, 0.30193, 0.39735, 0.556578", \ @@ -29420,10 +29530,10 @@ library (sg13g2_stdcell_fast_1p65V_m40C) { index_1 ("0.0186, 0.0966, 0.174, 0.3294, 0.6408, 1.263, 2.5074"); index_2 ("0.001, 0.0468, 0.078, 0.1296, 0.216, 0.36, 0.6"); values ( \ - "0.0117027, 0.0523749, 0.0826275, 0.133723, 0.219594, 0.362882, 0.601644", \ - "0.0117097, 0.0523759, 0.0826285, 0.133724, 0.219595, 0.364652, 0.601678", \ - "0.0117107, 0.0523769, 0.0826295, 0.133725, 0.219596, 0.364653, 0.601679", \ - "0.0117492, 0.0523779, 0.0826305, 0.133726, 0.2196, 0.364654, 0.60168", \ + "0.0117027, 0.0523749, 0.0826269, 0.133723, 0.219594, 0.362882, 0.601614", \ + "0.0117097, 0.0523759, 0.0826279, 0.133724, 0.219595, 0.364652, 0.601678", \ + "0.0117107, 0.0523769, 0.0826289, 0.133725, 0.219596, 0.364653, 0.601679", \ + "0.0117492, 0.0523779, 0.0826299, 0.133726, 0.2196, 0.364654, 0.60168", \ "0.0118566, 0.052414, 0.082651, 0.133727, 0.219601, 0.364655, 0.601681", \ "0.012149, 0.052481, 0.082697, 0.133728, 0.219602, 0.364656, 0.601689", \ "0.012859, 0.052804, 0.082815, 0.133796, 0.219658, 0.364657, 0.601791" \ @@ -29433,7 +29543,7 @@ library (sg13g2_stdcell_fast_1p65V_m40C) { index_1 ("0.0186, 0.0966, 0.174, 0.3294, 0.6408, 1.263, 2.5074"); index_2 ("0.001, 0.0468, 0.078, 0.1296, 0.216, 0.36, 0.6"); values ( \ - "0.102081, 0.128507, 0.146071, 0.1751, 0.223736, 0.304889, 0.440128", \ + "0.102064, 0.128514, 0.146071, 0.175111, 0.223738, 0.304888, 0.440132", \ "0.12059, 0.146992, 0.164597, 0.193585, 0.242213, 0.32334, 0.458619", \ "0.132726, 0.159143, 0.176731, 0.205733, 0.254342, 0.335463, 0.470705", \ "0.149829, 0.176467, 0.194002, 0.222886, 0.271593, 0.352588, 0.487811", \ @@ -29446,18 +29556,19 @@ library (sg13g2_stdcell_fast_1p65V_m40C) { index_1 ("0.0186, 0.0966, 0.174, 0.3294, 0.6408, 1.263, 2.5074"); index_2 ("0.001, 0.0468, 0.078, 0.1296, 0.216, 0.36, 0.6"); values ( \ - "0.0102169, 0.0433362, 0.0672145, 0.107691, 0.176118, 0.290415, 0.480875", \ - "0.0102179, 0.0433372, 0.0672155, 0.107692, 0.176163, 0.290416, 0.480986", \ - "0.0102189, 0.0433614, 0.0672165, 0.107693, 0.176164, 0.290417, 0.480987", \ - "0.0102199, 0.0433624, 0.0672175, 0.107694, 0.176165, 0.290418, 0.480988", \ - "0.0102209, 0.0433634, 0.0672185, 0.107696, 0.176166, 0.290419, 0.480989", \ - "0.0102219, 0.0433644, 0.067219, 0.107697, 0.176167, 0.29042, 0.48099", \ - "0.0102229, 0.0433654, 0.06722, 0.107698, 0.176168, 0.290421, 0.480991" \ + "0.0102007, 0.0433351, 0.0672145, 0.107691, 0.176122, 0.290415, 0.480875", \ + "0.0102009, 0.0433361, 0.0672155, 0.107692, 0.176163, 0.290416, 0.480986", \ + "0.0102039, 0.0433614, 0.0672165, 0.107693, 0.176164, 0.290417, 0.480987", \ + "0.0102049, 0.0433624, 0.0672175, 0.107694, 0.176165, 0.290418, 0.480988", \ + "0.0102059, 0.0433634, 0.0672185, 0.107696, 0.176166, 0.290419, 0.480989", \ + "0.0102069, 0.0433644, 0.067219, 0.107697, 0.176167, 0.29042, 0.48099", \ + "0.0102079, 0.0433654, 0.06722, 0.107698, 0.176168, 0.290421, 0.480991" \ ); } } timing () { related_pin : "RESET_B"; + sdf_edges : start_edge; timing_sense : positive_unate; timing_type : clear; cell_fall (TIMING_DELAY_7x7ds1) { @@ -29494,10 +29605,10 @@ library (sg13g2_stdcell_fast_1p65V_m40C) { index_1 ("0.0186, 0.0966, 0.174, 0.3294, 0.6408, 1.263, 2.5074"); index_2 ("0.001, 0.0468, 0.078, 0.1296, 0.216, 0.36, 0.6"); values ( \ - "0.0836681, 0.140365, 0.182727, 0.252812, 0.370012, 0.565248, 0.889816", \ + "0.0836681, 0.140365, 0.182719, 0.252785, 0.370012, 0.565248, 0.889954", \ "0.0859062, 0.142277, 0.184954, 0.255491, 0.372671, 0.569727, 0.892067", \ "0.0894382, 0.145901, 0.188248, 0.258289, 0.376048, 0.570367, 0.898857", \ - "0.0980133, 0.154107, 0.19666, 0.266994, 0.384043, 0.579129, 0.907174", \ + "0.0980133, 0.154108, 0.19666, 0.266994, 0.384043, 0.579129, 0.907174", \ "0.116571, 0.171813, 0.213996, 0.284614, 0.402325, 0.598258, 0.922942", \ "0.155098, 0.208338, 0.250442, 0.320669, 0.437974, 0.634531, 0.961059", \ "0.23351, 0.284051, 0.325832, 0.395607, 0.512319, 0.708581, 1.03459" \ @@ -29507,10 +29618,10 @@ library (sg13g2_stdcell_fast_1p65V_m40C) { index_1 ("0.0186, 0.0966, 0.174, 0.3294, 0.6408, 1.263, 2.5074"); index_2 ("0.001, 0.0468, 0.078, 0.1296, 0.216, 0.36, 0.6"); values ( \ - "0.0832292, 0.142824, 0.185331, 0.255266, 0.371993, 0.566323, 0.889753", \ + "0.0832257, 0.14282, 0.185331, 0.255282, 0.371951, 0.566322, 0.889746", \ "0.0855522, 0.14518, 0.187646, 0.258575, 0.374173, 0.569719, 0.891836", \ "0.0889796, 0.149075, 0.191741, 0.261328, 0.378025, 0.57436, 0.896646", \ - "0.0973151, 0.157107, 0.200008, 0.270613, 0.387773, 0.581664, 0.90923", \ + "0.0973147, 0.157107, 0.20001, 0.270613, 0.387772, 0.581664, 0.909231", \ "0.114659, 0.174265, 0.217131, 0.287274, 0.405148, 0.60144, 0.92458", \ "0.150332, 0.209611, 0.251662, 0.321892, 0.44005, 0.636239, 0.962987", \ "0.222292, 0.281184, 0.323703, 0.393988, 0.509926, 0.705664, 1.03194" \ @@ -29523,10 +29634,10 @@ library (sg13g2_stdcell_fast_1p65V_m40C) { index_1 ("0.0186, 0.0966, 0.174, 0.3294, 0.6408, 1.263, 2.5074"); index_2 ("0.001, 0.0468, 0.078, 0.1296, 0.216, 0.36, 0.6"); values ( \ - "0.0836681, 0.140365, 0.182727, 0.252812, 0.370012, 0.565248, 0.889816", \ + "0.0836681, 0.140365, 0.182719, 0.252785, 0.370012, 0.565248, 0.889954", \ "0.0859062, 0.142277, 0.184954, 0.255491, 0.372671, 0.569727, 0.892067", \ "0.0894382, 0.145901, 0.188248, 0.258289, 0.376048, 0.570367, 0.898857", \ - "0.0980133, 0.154107, 0.19666, 0.266994, 0.384043, 0.579129, 0.907174", \ + "0.0980133, 0.154108, 0.19666, 0.266994, 0.384043, 0.579129, 0.907174", \ "0.116571, 0.171813, 0.213996, 0.284614, 0.402325, 0.598258, 0.922942", \ "0.155098, 0.208338, 0.250442, 0.320669, 0.437974, 0.634531, 0.961059", \ "0.23351, 0.284051, 0.325832, 0.395607, 0.512319, 0.708581, 1.03459" \ @@ -29536,10 +29647,10 @@ library (sg13g2_stdcell_fast_1p65V_m40C) { index_1 ("0.0186, 0.0966, 0.174, 0.3294, 0.6408, 1.263, 2.5074"); index_2 ("0.001, 0.0468, 0.078, 0.1296, 0.216, 0.36, 0.6"); values ( \ - "0.0832292, 0.142824, 0.185331, 0.255266, 0.371993, 0.566323, 0.889753", \ + "0.0832257, 0.14282, 0.185331, 0.255282, 0.371951, 0.566322, 0.889746", \ "0.0855522, 0.14518, 0.187646, 0.258575, 0.374173, 0.569719, 0.891836", \ "0.0889796, 0.149075, 0.191741, 0.261328, 0.378025, 0.57436, 0.896646", \ - "0.0973151, 0.157107, 0.200008, 0.270613, 0.387773, 0.581664, 0.90923", \ + "0.0973147, 0.157107, 0.20001, 0.270613, 0.387772, 0.581664, 0.909231", \ "0.114659, 0.174265, 0.217131, 0.287274, 0.405148, 0.60144, 0.92458", \ "0.150332, 0.209611, 0.251662, 0.321892, 0.44005, 0.636239, 0.962987", \ "0.222292, 0.281184, 0.323703, 0.393988, 0.509926, 0.705664, 1.03194" \ @@ -29561,7 +29672,7 @@ library (sg13g2_stdcell_fast_1p65V_m40C) { "0.0875614, 0.172047, 0.231575, 0.329297, 0.48006, 0.711093, 1.06468", \ "0.0916624, 0.176347, 0.235285, 0.332907, 0.491572, 0.733912, 1.10274", \ "0.100739, 0.184751, 0.244186, 0.342753, 0.504096, 0.763361, 1.16031", \ - "0.119089, 0.202315, 0.261821, 0.359663, 0.524367, 0.795227, 1.22083", \ + "0.119089, 0.202315, 0.261821, 0.359663, 0.524366, 0.795227, 1.22083", \ "0.155956, 0.237442, 0.296363, 0.394292, 0.557708, 0.830984, 1.28443", \ "0.225369, 0.30421, 0.362449, 0.459228, 0.622505, 0.89597, 1.35098" \ ); @@ -29576,6 +29687,7 @@ library (sg13g2_stdcell_fast_1p65V_m40C) { timing () { related_pin : "CLK"; sdf_cond : "SCE == 1'b1"; + sdf_edges : start_edge; timing_sense : non_unate; timing_type : rising_edge; when : "SCE"; @@ -29583,33 +29695,33 @@ library (sg13g2_stdcell_fast_1p65V_m40C) { index_1 ("0.0186, 0.0966, 0.174, 0.3294, 0.6408, 1.263, 2.5074"); index_2 ("0.001, 0.0468, 0.078, 0.1296, 0.216, 0.36, 0.6"); values ( \ - "0.0690181, 0.113836, 0.136422, 0.171321, 0.228422, 0.323059, 0.480527", \ + "0.0690074, 0.113836, 0.136422, 0.171328, 0.228421, 0.323058, 0.480538", \ "0.0875339, 0.132344, 0.154894, 0.189767, 0.246857, 0.341494, 0.498998", \ "0.0996693, 0.144438, 0.16701, 0.20189, 0.258956, 0.353552, 0.511013", \ "0.116812, 0.161685, 0.184238, 0.218973, 0.276147, 0.370599, 0.528073", \ "0.137432, 0.181923, 0.204451, 0.23933, 0.296429, 0.391009, 0.548605", \ "0.162433, 0.206334, 0.228857, 0.263764, 0.320787, 0.415402, 0.572801", \ - "0.190344, 0.234446, 0.256875, 0.291753, 0.348757, 0.443385, 0.60084" \ + "0.190423, 0.23447, 0.256755, 0.291753, 0.348757, 0.443385, 0.60084" \ ); } rise_transition (TIMING_DELAY_7x7ds1) { index_1 ("0.0186, 0.0966, 0.174, 0.3294, 0.6408, 1.263, 2.5074"); index_2 ("0.001, 0.0468, 0.078, 0.1296, 0.216, 0.36, 0.6"); values ( \ - "0.0135516, 0.0594206, 0.0879365, 0.136282, 0.219869, 0.361216, 0.597866", \ - "0.0135526, 0.0594216, 0.0879375, 0.136283, 0.21987, 0.364214, 0.597867", \ - "0.0135536, 0.0594226, 0.0879385, 0.136284, 0.219871, 0.364215, 0.597868", \ - "0.0135546, 0.0594236, 0.0879395, 0.136292, 0.219872, 0.364216, 0.597869", \ - "0.0135556, 0.0594246, 0.0879405, 0.136293, 0.219873, 0.364217, 0.597957", \ - "0.0135566, 0.0594256, 0.0879415, 0.136294, 0.219874, 0.364218, 0.597958", \ - "0.013648, 0.0594266, 0.0879425, 0.136295, 0.219875, 0.364219, 0.597959" \ + "0.0135403, 0.0594206, 0.0879366, 0.136282, 0.219869, 0.361216, 0.597852", \ + "0.0135413, 0.0594216, 0.0879376, 0.136283, 0.21987, 0.364214, 0.597854", \ + "0.0135423, 0.0594226, 0.0879386, 0.136284, 0.219871, 0.364215, 0.597855", \ + "0.0135433, 0.0594236, 0.0879396, 0.136292, 0.219872, 0.364216, 0.597856", \ + "0.0135443, 0.0594246, 0.0879406, 0.136293, 0.219873, 0.364217, 0.597957", \ + "0.0135453, 0.0594256, 0.0879416, 0.136294, 0.219874, 0.364218, 0.597958", \ + "0.013641, 0.0594266, 0.0879426, 0.136295, 0.219875, 0.364219, 0.597959" \ ); } cell_fall (TIMING_DELAY_7x7ds1) { index_1 ("0.0186, 0.0966, 0.174, 0.3294, 0.6408, 1.263, 2.5074"); index_2 ("0.001, 0.0468, 0.078, 0.1296, 0.216, 0.36, 0.6"); values ( \ - "0.0751057, 0.123271, 0.145188, 0.1772, 0.227168, 0.30878, 0.443869", \ + "0.0750753, 0.123271, 0.14516, 0.177082, 0.227164, 0.308775, 0.443882", \ "0.0941096, 0.142266, 0.164205, 0.196109, 0.246192, 0.327655, 0.462903", \ "0.106753, 0.154868, 0.176813, 0.20873, 0.258804, 0.340268, 0.475466", \ "0.125559, 0.173616, 0.195599, 0.227519, 0.277676, 0.359131, 0.494263", \ @@ -29622,8 +29734,8 @@ library (sg13g2_stdcell_fast_1p65V_m40C) { index_1 ("0.0186, 0.0966, 0.174, 0.3294, 0.6408, 1.263, 2.5074"); index_2 ("0.001, 0.0468, 0.078, 0.1296, 0.216, 0.36, 0.6"); values ( \ - "0.0173946, 0.0581781, 0.0803767, 0.117268, 0.182132, 0.293786, 0.483051", \ - "0.0174146, 0.0581791, 0.0803777, 0.117269, 0.182133, 0.293849, 0.483507", \ + "0.0173917, 0.0581781, 0.0803615, 0.117294, 0.182132, 0.293785, 0.483254", \ + "0.0174146, 0.0581791, 0.0803707, 0.117295, 0.182133, 0.293849, 0.483507", \ "0.0174854, 0.0581801, 0.0804373, 0.117301, 0.182134, 0.29385, 0.483508", \ "0.0177969, 0.0583927, 0.0804976, 0.117379, 0.182135, 0.293851, 0.483509", \ "0.0188527, 0.0589836, 0.0809376, 0.117585, 0.182237, 0.293885, 0.48351", \ @@ -29634,39 +29746,40 @@ library (sg13g2_stdcell_fast_1p65V_m40C) { } timing () { related_pin : "CLK"; + sdf_edges : start_edge; timing_sense : non_unate; timing_type : rising_edge; cell_rise (TIMING_DELAY_7x7ds1) { index_1 ("0.0186, 0.0966, 0.174, 0.3294, 0.6408, 1.263, 2.5074"); index_2 ("0.001, 0.0468, 0.078, 0.1296, 0.216, 0.36, 0.6"); values ( \ - "0.0690181, 0.113836, 0.136422, 0.171321, 0.228422, 0.323059, 0.480527", \ + "0.0690074, 0.113836, 0.136422, 0.171328, 0.228421, 0.323058, 0.480538", \ "0.0875339, 0.132344, 0.154894, 0.189767, 0.246857, 0.341494, 0.498998", \ "0.0996693, 0.144438, 0.16701, 0.20189, 0.258956, 0.353552, 0.511013", \ "0.116812, 0.161685, 0.184238, 0.218973, 0.276147, 0.370599, 0.528073", \ "0.137432, 0.181923, 0.204451, 0.23933, 0.296429, 0.391009, 0.548605", \ "0.162433, 0.206334, 0.228857, 0.263764, 0.320787, 0.415402, 0.572801", \ - "0.190344, 0.234446, 0.256875, 0.291753, 0.348757, 0.443385, 0.60084" \ + "0.190423, 0.23447, 0.256755, 0.291753, 0.348757, 0.443385, 0.60084" \ ); } rise_transition (TIMING_DELAY_7x7ds1) { index_1 ("0.0186, 0.0966, 0.174, 0.3294, 0.6408, 1.263, 2.5074"); index_2 ("0.001, 0.0468, 0.078, 0.1296, 0.216, 0.36, 0.6"); values ( \ - "0.0135516, 0.0594206, 0.0879365, 0.136282, 0.219869, 0.361216, 0.597866", \ - "0.0135526, 0.0594216, 0.0879375, 0.136283, 0.21987, 0.364214, 0.597867", \ - "0.0135536, 0.0594226, 0.0879385, 0.136284, 0.219871, 0.364215, 0.597868", \ - "0.0135546, 0.0594236, 0.0879395, 0.136292, 0.219872, 0.364216, 0.597869", \ - "0.0135556, 0.0594246, 0.0879405, 0.136293, 0.219873, 0.364217, 0.597957", \ - "0.0135566, 0.0594256, 0.0879415, 0.136294, 0.219874, 0.364218, 0.597958", \ - "0.013648, 0.0594266, 0.0879425, 0.136295, 0.219875, 0.364219, 0.597959" \ + "0.0135403, 0.0594206, 0.0879366, 0.136282, 0.219869, 0.361216, 0.597852", \ + "0.0135413, 0.0594216, 0.0879376, 0.136283, 0.21987, 0.364214, 0.597854", \ + "0.0135423, 0.0594226, 0.0879386, 0.136284, 0.219871, 0.364215, 0.597855", \ + "0.0135433, 0.0594236, 0.0879396, 0.136292, 0.219872, 0.364216, 0.597856", \ + "0.0135443, 0.0594246, 0.0879406, 0.136293, 0.219873, 0.364217, 0.597957", \ + "0.0135453, 0.0594256, 0.0879416, 0.136294, 0.219874, 0.364218, 0.597958", \ + "0.013641, 0.0594266, 0.0879426, 0.136295, 0.219875, 0.364219, 0.597959" \ ); } cell_fall (TIMING_DELAY_7x7ds1) { index_1 ("0.0186, 0.0966, 0.174, 0.3294, 0.6408, 1.263, 2.5074"); index_2 ("0.001, 0.0468, 0.078, 0.1296, 0.216, 0.36, 0.6"); values ( \ - "0.0751057, 0.123271, 0.145188, 0.1772, 0.227168, 0.30878, 0.443869", \ + "0.0750753, 0.123271, 0.14516, 0.177082, 0.227164, 0.308775, 0.443882", \ "0.0941096, 0.142266, 0.164205, 0.196109, 0.246192, 0.327655, 0.462903", \ "0.106753, 0.154868, 0.176813, 0.20873, 0.258804, 0.340268, 0.475466", \ "0.125559, 0.173616, 0.195599, 0.227519, 0.277676, 0.359131, 0.494263", \ @@ -29679,8 +29792,8 @@ library (sg13g2_stdcell_fast_1p65V_m40C) { index_1 ("0.0186, 0.0966, 0.174, 0.3294, 0.6408, 1.263, 2.5074"); index_2 ("0.001, 0.0468, 0.078, 0.1296, 0.216, 0.36, 0.6"); values ( \ - "0.0173946, 0.0581781, 0.0803767, 0.117268, 0.182132, 0.293786, 0.483051", \ - "0.0174146, 0.0581791, 0.0803777, 0.117269, 0.182133, 0.293849, 0.483507", \ + "0.0173917, 0.0581781, 0.0803615, 0.117294, 0.182132, 0.293785, 0.483254", \ + "0.0174146, 0.0581791, 0.0803707, 0.117295, 0.182133, 0.293849, 0.483507", \ "0.0174854, 0.0581801, 0.0804373, 0.117301, 0.182134, 0.29385, 0.483508", \ "0.0177969, 0.0583927, 0.0804976, 0.117379, 0.182135, 0.293851, 0.483509", \ "0.0188527, 0.0589836, 0.0809376, 0.117585, 0.182237, 0.293885, 0.48351", \ @@ -29691,6 +29804,7 @@ library (sg13g2_stdcell_fast_1p65V_m40C) { } timing () { related_pin : "RESET_B"; + sdf_edges : start_edge; timing_sense : negative_unate; timing_type : preset; cell_rise (TIMING_DELAY_7x7ds1) { @@ -29727,20 +29841,20 @@ library (sg13g2_stdcell_fast_1p65V_m40C) { index_1 ("0.0186, 0.0966, 0.174, 0.3294, 0.6408, 1.263, 2.5074"); index_2 ("0.001, 0.0468, 0.078, 0.1296, 0.216, 0.36, 0.6"); values ( \ - "0.0832941, 0.143126, 0.185737, 0.255935, 0.3732, 0.568353, 0.892829", \ + "0.083304, 0.143126, 0.185737, 0.255938, 0.373197, 0.568352, 0.892955", \ "0.0856223, 0.145439, 0.18802, 0.258814, 0.375857, 0.574866, 0.895296", \ - "0.0890747, 0.14916, 0.191765, 0.261813, 0.379447, 0.573807, 0.904051", \ - "0.0973543, 0.157245, 0.200134, 0.270751, 0.387931, 0.582952, 0.909287", \ - "0.114677, 0.174496, 0.217154, 0.287712, 0.405552, 0.601379, 0.926053", \ - "0.150276, 0.209704, 0.251986, 0.322653, 0.439918, 0.636319, 0.962967", \ - "0.222162, 0.281589, 0.323844, 0.394248, 0.511049, 0.707607, 1.03385" \ + "0.0890747, 0.14916, 0.191765, 0.261813, 0.379447, 0.573808, 0.904051", \ + "0.0973542, 0.157243, 0.200131, 0.270716, 0.387931, 0.582989, 0.909287", \ + "0.114677, 0.174496, 0.217154, 0.287711, 0.405549, 0.601371, 0.926062", \ + "0.150276, 0.209704, 0.251987, 0.322653, 0.439918, 0.636319, 0.962967", \ + "0.221038, 0.28032, 0.322689, 0.394244, 0.511049, 0.707607, 1.03385" \ ); } fall_power (POWER_7x7ds1) { index_1 ("0.0186, 0.0966, 0.174, 0.3294, 0.6408, 1.263, 2.5074"); index_2 ("0.001, 0.0468, 0.078, 0.1296, 0.216, 0.36, 0.6"); values ( \ - "0.0851214, 0.141453, 0.183765, 0.253497, 0.37012, 0.564385, 0.887824", \ + "0.0852051, 0.141453, 0.183715, 0.253531, 0.370123, 0.5644, 0.88791", \ "0.0873446, 0.143486, 0.185786, 0.256489, 0.372532, 0.56752, 0.890062", \ "0.0908859, 0.147245, 0.189693, 0.258876, 0.375933, 0.572091, 0.894101", \ "0.0993125, 0.155231, 0.197646, 0.268246, 0.385225, 0.57833, 0.907263", \ @@ -29756,20 +29870,20 @@ library (sg13g2_stdcell_fast_1p65V_m40C) { index_1 ("0.0186, 0.0966, 0.174, 0.3294, 0.6408, 1.263, 2.5074"); index_2 ("0.001, 0.0468, 0.078, 0.1296, 0.216, 0.36, 0.6"); values ( \ - "0.0832941, 0.143126, 0.185737, 0.255935, 0.3732, 0.568353, 0.892829", \ + "0.083304, 0.143126, 0.185737, 0.255938, 0.373197, 0.568352, 0.892955", \ "0.0856223, 0.145439, 0.18802, 0.258814, 0.375857, 0.574866, 0.895296", \ - "0.0890747, 0.14916, 0.191765, 0.261813, 0.379447, 0.573807, 0.904051", \ - "0.0973543, 0.157245, 0.200134, 0.270751, 0.387931, 0.582952, 0.909287", \ - "0.114677, 0.174496, 0.217154, 0.287712, 0.405552, 0.601379, 0.926053", \ - "0.150276, 0.209704, 0.251986, 0.322653, 0.439918, 0.636319, 0.962967", \ - "0.222162, 0.281589, 0.323844, 0.394248, 0.511049, 0.707607, 1.03385" \ + "0.0890747, 0.14916, 0.191765, 0.261813, 0.379447, 0.573808, 0.904051", \ + "0.0973542, 0.157243, 0.200131, 0.270716, 0.387931, 0.582989, 0.909287", \ + "0.114677, 0.174496, 0.217154, 0.287711, 0.405549, 0.601371, 0.926062", \ + "0.150276, 0.209704, 0.251987, 0.322653, 0.439918, 0.636319, 0.962967", \ + "0.221038, 0.28032, 0.322689, 0.394244, 0.511049, 0.707607, 1.03385" \ ); } fall_power (POWER_7x7ds1) { index_1 ("0.0186, 0.0966, 0.174, 0.3294, 0.6408, 1.263, 2.5074"); index_2 ("0.001, 0.0468, 0.078, 0.1296, 0.216, 0.36, 0.6"); values ( \ - "0.0851214, 0.141453, 0.183765, 0.253497, 0.37012, 0.564385, 0.887824", \ + "0.0852051, 0.141453, 0.183715, 0.253531, 0.370123, 0.5644, 0.88791", \ "0.0873446, 0.143486, 0.185786, 0.256489, 0.372532, 0.56752, 0.890062", \ "0.0908859, 0.147245, 0.189693, 0.258876, 0.375933, 0.572091, 0.894101", \ "0.0993125, 0.155231, 0.197646, 0.268246, 0.385225, 0.57833, 0.907263", \ @@ -29786,7 +29900,7 @@ library (sg13g2_stdcell_fast_1p65V_m40C) { index_2 ("0.001, 0.0468, 0.078, 0.1296, 0.216, 0.36, 0.6"); values ( \ "0.0853184, 0.157722, 0.207736, 0.28546, 0.403069, 0.578857, 0.854207", \ - "0.0873009, 0.159651, 0.210837, 0.293865, 0.422045, 0.614734, 0.906073", \ + "0.0873008, 0.159651, 0.210837, 0.293866, 0.4225, 0.614734, 0.906073", \ "0.0913754, 0.163516, 0.214462, 0.298242, 0.434066, 0.639654, 0.950394", \ "0.100372, 0.172111, 0.223387, 0.307621, 0.446624, 0.667539, 0.997519", \ "0.118633, 0.189941, 0.240994, 0.324907, 0.46576, 0.696918, 1.06038", \ @@ -29805,11 +29919,11 @@ library (sg13g2_stdcell_fast_1p65V_m40C) { clock : true; direction : input; max_transition : 2.5074; - capacitance : 0.00333581; - rise_capacitance : 0.0033906; - rise_capacitance_range (0.0033906, 0.0033906); + capacitance : 0.00333586; + rise_capacitance : 0.00339069; + rise_capacitance_range (0.00297385, 0.00376156); fall_capacitance : 0.00326536; - fall_capacitance_range (0.00326536, 0.00326536); + fall_capacitance_range (0.00294909, 0.00352652); timing () { related_pin : "CLK"; timing_type : min_pulse_width; @@ -29825,7 +29939,7 @@ library (sg13g2_stdcell_fast_1p65V_m40C) { rise_power (passive_POWER_7x1ds1) { index_1 ("0.0186, 0.0966, 0.174, 0.3294, 0.6408, 1.263, 2.5074"); values ( \ - "0.0184973, 0.0206306, 0.0240451, 0.03193, 0.0485903, 0.0832379, 0.15546" \ + "0.0184719, 0.0206306, 0.0240451, 0.03193, 0.0485898, 0.0832379, 0.15546" \ ); } fall_power (passive_POWER_7x1ds1) { @@ -29845,7 +29959,7 @@ library (sg13g2_stdcell_fast_1p65V_m40C) { fall_power (passive_POWER_7x1ds1) { index_1 ("0.0186, 0.0966, 0.174, 0.3294, 0.6408, 1.263, 2.5074"); values ( \ - "0.0399837, 0.042435, 0.0460841, 0.0542017, 0.0713223, 0.106083, 0.178261" \ + "0.0399838, 0.042435, 0.0460842, 0.0542017, 0.0713223, 0.106083, 0.178261" \ ); } } @@ -29859,7 +29973,7 @@ library (sg13g2_stdcell_fast_1p65V_m40C) { fall_power (passive_POWER_7x1ds1) { index_1 ("0.0186, 0.0966, 0.174, 0.3294, 0.6408, 1.263, 2.5074"); values ( \ - "0.0369569, 0.0395893, 0.0433453, 0.0513625, 0.0683996, 0.102329, 0.173028" \ + "0.036957, 0.0395893, 0.0433453, 0.0513625, 0.0683996, 0.102329, 0.173028" \ ); } } @@ -29868,13 +29982,13 @@ library (sg13g2_stdcell_fast_1p65V_m40C) { rise_power (passive_POWER_7x1ds1) { index_1 ("0.0186, 0.0966, 0.174, 0.3294, 0.6408, 1.263, 2.5074"); values ( \ - "0.0180462, 0.0202154, 0.0235263, 0.031513, 0.0481913, 0.0827613, 0.155268" \ + "0.0180459, 0.0202154, 0.0235263, 0.031513, 0.0481913, 0.0827613, 0.155268" \ ); } fall_power (passive_POWER_7x1ds1) { index_1 ("0.0186, 0.0966, 0.174, 0.3294, 0.6408, 1.263, 2.5074"); values ( \ - "0.0202272, 0.0226956, 0.0262283, 0.0339497, 0.0505147, 0.0839054, 0.153385" \ + "0.0202272, 0.0226956, 0.0262283, 0.0339497, 0.0505146, 0.0839054, 0.153385" \ ); } } @@ -29883,13 +29997,13 @@ library (sg13g2_stdcell_fast_1p65V_m40C) { rise_power (passive_POWER_7x1ds1) { index_1 ("0.0186, 0.0966, 0.174, 0.3294, 0.6408, 1.263, 2.5074"); values ( \ - "0.0184999, 0.0206298, 0.0240449, 0.03193, 0.0485905, 0.0832379, 0.15546" \ + "0.0184865, 0.0206298, 0.0240449, 0.0319299, 0.0485904, 0.0832379, 0.15546" \ ); } fall_power (passive_POWER_7x1ds1) { index_1 ("0.0186, 0.0966, 0.174, 0.3294, 0.6408, 1.263, 2.5074"); values ( \ - "0.0198702, 0.0223069, 0.025856, 0.0335753, 0.0501528, 0.0835545, 0.153111" \ + "0.0198701, 0.0223068, 0.0258559, 0.0335752, 0.0501527, 0.0835544, 0.153111" \ ); } } @@ -29898,7 +30012,7 @@ library (sg13g2_stdcell_fast_1p65V_m40C) { rise_power (passive_POWER_7x1ds1) { index_1 ("0.0186, 0.0966, 0.174, 0.3294, 0.6408, 1.263, 2.5074"); values ( \ - "0.0113861, 0.0135237, 0.0168811, 0.0247437, 0.0414863, 0.0759804, 0.148105" \ + "0.0113861, 0.0135237, 0.0168812, 0.0247437, 0.0414863, 0.0759804, 0.148105" \ ); } fall_power (passive_POWER_7x1ds1) { @@ -29913,7 +30027,7 @@ library (sg13g2_stdcell_fast_1p65V_m40C) { rise_power (passive_POWER_7x1ds1) { index_1 ("0.0186, 0.0966, 0.174, 0.3294, 0.6408, 1.263, 2.5074"); values ( \ - "0.0180662, 0.0202155, 0.023526, 0.031512, 0.0481914, 0.0827614, 0.155268" \ + "0.0180652, 0.0202155, 0.023526, 0.031512, 0.0481914, 0.0827614, 0.155268" \ ); } fall_power (passive_POWER_7x1ds1) { @@ -29927,13 +30041,13 @@ library (sg13g2_stdcell_fast_1p65V_m40C) { rise_power (passive_POWER_7x1ds1) { index_1 ("0.0186, 0.0966, 0.174, 0.3294, 0.6408, 1.263, 2.5074"); values ( \ - "0.0180462, 0.0202154, 0.0235263, 0.031513, 0.0481913, 0.0827613, 0.155268" \ + "0.0180459, 0.0202154, 0.0235263, 0.031513, 0.0481913, 0.0827613, 0.155268" \ ); } fall_power (passive_POWER_7x1ds1) { index_1 ("0.0186, 0.0966, 0.174, 0.3294, 0.6408, 1.263, 2.5074"); values ( \ - "0.0202272, 0.0226956, 0.0262283, 0.0339497, 0.0505147, 0.0839054, 0.153385" \ + "0.0202272, 0.0226956, 0.0262283, 0.0339497, 0.0505146, 0.0839054, 0.153385" \ ); } } @@ -29944,11 +30058,12 @@ library (sg13g2_stdcell_fast_1p65V_m40C) { max_transition : 2.5074; capacitance : 0.00311795; rise_capacitance : 0.00320345; - rise_capacitance_range (0.00320345, 0.00320345); + rise_capacitance_range (0.00265777, 0.00365523); fall_capacitance : 0.00303244; - fall_capacitance_range (0.00303244, 0.00303244); + fall_capacitance_range (0.00265492, 0.00322601); timing () { related_pin : "CLK"; + sdf_edges : both_edges; timing_type : hold_rising; rise_constraint (CONSTRAINT_4x4) { index_1 ("0.0186, 0.51636, 1.263, 2.5074"); @@ -29973,6 +30088,7 @@ library (sg13g2_stdcell_fast_1p65V_m40C) { } timing () { related_pin : "CLK"; + sdf_edges : both_edges; timing_type : setup_rising; rise_constraint (CONSTRAINT_4x4) { index_1 ("0.0186, 0.51636, 1.263, 2.5074"); @@ -30000,13 +30116,13 @@ library (sg13g2_stdcell_fast_1p65V_m40C) { rise_power (passive_POWER_7x1ds1) { index_1 ("0.0186, 0.0966, 0.174, 0.3294, 0.6408, 1.263, 2.5074"); values ( \ - "0.0376827, 0.0389741, 0.041466, 0.0471887, 0.0598682, 0.0858249, 0.13858" \ + "0.0377076, 0.038974, 0.0414659, 0.0471886, 0.0598681, 0.0858248, 0.13858" \ ); } fall_power (passive_POWER_7x1ds1) { index_1 ("0.0186, 0.0966, 0.174, 0.3294, 0.6408, 1.263, 2.5074"); values ( \ - "0.0410171, 0.0431073, 0.0460238, 0.0524313, 0.0651985, 0.0910352, 0.143645" \ + "0.0410169, 0.0431073, 0.0460238, 0.0524313, 0.0651985, 0.0910352, 0.143645" \ ); } } @@ -30014,13 +30130,13 @@ library (sg13g2_stdcell_fast_1p65V_m40C) { rise_power (passive_POWER_7x1ds1) { index_1 ("0.0186, 0.0966, 0.174, 0.3294, 0.6408, 1.263, 2.5074"); values ( \ - "0.0376827, 0.0389741, 0.041466, 0.0471887, 0.0598682, 0.0858249, 0.13858" \ + "0.0377076, 0.038974, 0.0414659, 0.0471886, 0.0598681, 0.0858248, 0.13858" \ ); } fall_power (passive_POWER_7x1ds1) { index_1 ("0.0186, 0.0966, 0.174, 0.3294, 0.6408, 1.263, 2.5074"); values ( \ - "0.0410171, 0.0431073, 0.0460238, 0.0524313, 0.0651985, 0.0910352, 0.143645" \ + "0.0410169, 0.0431073, 0.0460238, 0.0524313, 0.0651985, 0.0910352, 0.143645" \ ); } } @@ -30032,9 +30148,10 @@ library (sg13g2_stdcell_fast_1p65V_m40C) { rise_capacitance : 0.0055647; rise_capacitance_range (0.0055647, 0.0055647); fall_capacitance : 0.0055647; - fall_capacitance_range (0.0055647, 0.0055647); + fall_capacitance_range (0.0051309, 0.0057974); timing () { related_pin : "CLK"; + sdf_edges : both_edges; timing_type : recovery_rising; rise_constraint (CONSTRAINT_4x4) { index_1 ("0.0186, 0.51636, 1.263, 2.5074"); @@ -30049,6 +30166,7 @@ library (sg13g2_stdcell_fast_1p65V_m40C) { } timing () { related_pin : "CLK"; + sdf_edges : both_edges; timing_type : removal_rising; rise_constraint (CONSTRAINT_4x4) { index_1 ("0.0186, 0.51636, 1.263, 2.5074"); @@ -30078,11 +30196,12 @@ library (sg13g2_stdcell_fast_1p65V_m40C) { max_transition : 2.5074; capacitance : 0.00324979; rise_capacitance : 0.00330646; - rise_capacitance_range (0.00330646, 0.00330646); + rise_capacitance_range (0.00276844, 0.00375718); fall_capacitance : 0.00313645; - fall_capacitance_range (0.00313645, 0.00313645); + fall_capacitance_range (0.00276341, 0.00332868); timing () { related_pin : "CLK"; + sdf_edges : both_edges; timing_type : hold_rising; rise_constraint (CONSTRAINT_4x4) { index_1 ("0.0186, 0.51636, 1.263, 2.5074"); @@ -30098,7 +30217,7 @@ library (sg13g2_stdcell_fast_1p65V_m40C) { index_1 ("0.0186, 0.51636, 1.263, 2.5074"); index_2 ("0.0186, 0.51636, 1.263, 2.5074"); values ( \ - "-0.063575, -0.0202131, 0.0112861, 0.0342506", \ + "-0.063575, -0.0177173, 0.0112861, 0.0342506", \ "-0.144511, -0.0993119, -0.0698381, -0.0461353", \ "-0.204169, -0.160934, -0.13222, -0.106057", \ "-0.2825, -0.237012, -0.207512, -0.182995" \ @@ -30107,6 +30226,7 @@ library (sg13g2_stdcell_fast_1p65V_m40C) { } timing () { related_pin : "CLK"; + sdf_edges : both_edges; timing_type : setup_rising; rise_constraint (CONSTRAINT_4x4) { index_1 ("0.0186, 0.51636, 1.263, 2.5074"); @@ -30134,13 +30254,13 @@ library (sg13g2_stdcell_fast_1p65V_m40C) { rise_power (passive_POWER_7x1ds1) { index_1 ("0.0186, 0.0966, 0.174, 0.3294, 0.6408, 1.263, 2.5074"); values ( \ - "0.0385166, 0.0398174, 0.042305, 0.0480029, 0.060733, 0.0867914, 0.139418" \ + "0.0385167, 0.0398174, 0.042305, 0.0480029, 0.060733, 0.0867914, 0.139418" \ ); } fall_power (passive_POWER_7x1ds1) { index_1 ("0.0186, 0.0966, 0.174, 0.3294, 0.6408, 1.263, 2.5074"); values ( \ - "0.0351715, 0.0372256, 0.0402013, 0.0466986, 0.0595361, 0.0854844, 0.13836" \ + "0.0351715, 0.0372256, 0.0402013, 0.0466986, 0.0595361, 0.0854845, 0.13836" \ ); } } @@ -30148,13 +30268,13 @@ library (sg13g2_stdcell_fast_1p65V_m40C) { rise_power (passive_POWER_7x1ds1) { index_1 ("0.0186, 0.0966, 0.174, 0.3294, 0.6408, 1.263, 2.5074"); values ( \ - "0.0385166, 0.0398174, 0.042305, 0.0480029, 0.060733, 0.0867914, 0.139418" \ + "0.0385167, 0.0398174, 0.042305, 0.0480029, 0.060733, 0.0867914, 0.139418" \ ); } fall_power (passive_POWER_7x1ds1) { index_1 ("0.0186, 0.0966, 0.174, 0.3294, 0.6408, 1.263, 2.5074"); values ( \ - "0.0351715, 0.0372256, 0.0402013, 0.0466986, 0.0595361, 0.0854844, 0.13836" \ + "0.0351715, 0.0372256, 0.0402013, 0.0466986, 0.0595361, 0.0854845, 0.13836" \ ); } } @@ -30165,11 +30285,12 @@ library (sg13g2_stdcell_fast_1p65V_m40C) { max_transition : 2.5074; capacitance : 0.00558357; rise_capacitance : 0.00594896; - rise_capacitance_range (0.00594896, 0.00594896); + rise_capacitance_range (0.00489536, 0.00656184); fall_capacitance : 0.00521818; - fall_capacitance_range (0.00521818, 0.00521818); + fall_capacitance_range (0.00492568, 0.00572813); timing () { related_pin : "CLK"; + sdf_edges : both_edges; timing_type : hold_rising; rise_constraint (CONSTRAINT_4x4) { index_1 ("0.0186, 0.51636, 1.263, 2.5074"); @@ -30194,6 +30315,7 @@ library (sg13g2_stdcell_fast_1p65V_m40C) { } timing () { related_pin : "CLK"; + sdf_edges : both_edges; timing_type : setup_rising; rise_constraint (CONSTRAINT_4x4) { index_1 ("0.0186, 0.51636, 1.263, 2.5074"); @@ -30221,13 +30343,13 @@ library (sg13g2_stdcell_fast_1p65V_m40C) { rise_power (passive_POWER_7x1ds1) { index_1 ("0.0186, 0.0966, 0.174, 0.3294, 0.6408, 1.263, 2.5074"); values ( \ - "0.0399354, 0.0412533, 0.0436531, 0.0491439, 0.0610452, 0.0858195, 0.136709" \ + "0.0399354, 0.0412533, 0.0436531, 0.0491439, 0.0610451, 0.0858195, 0.136709" \ ); } fall_power (passive_POWER_7x1ds1) { index_1 ("0.0186, 0.0966, 0.174, 0.3294, 0.6408, 1.263, 2.5074"); values ( \ - "0.0499313, 0.0516323, 0.0541111, 0.0595769, 0.0712401, 0.0956563, 0.145461" \ + "0.0499361, 0.0516322, 0.054111, 0.0595768, 0.07124, 0.0956562, 0.145461" \ ); } } @@ -30236,13 +30358,13 @@ library (sg13g2_stdcell_fast_1p65V_m40C) { rise_power (passive_POWER_7x1ds1) { index_1 ("0.0186, 0.0966, 0.174, 0.3294, 0.6408, 1.263, 2.5074"); values ( \ - "0.0454794, 0.0478443, 0.0524625, 0.0636623, 0.0881267, 0.138747, 0.240978" \ + "0.0454947, 0.0478444, 0.0524625, 0.0636623, 0.0881267, 0.138747, 0.240978" \ ); } fall_power (passive_POWER_7x1ds1) { index_1 ("0.0186, 0.0966, 0.174, 0.3294, 0.6408, 1.263, 2.5074"); values ( \ - "0.0667629, 0.0804495, 0.0856261, 0.0969152, 0.121041, 0.170681, 0.270474" \ + "0.066763, 0.0804495, 0.0856261, 0.0969152, 0.121041, 0.170681, 0.270474" \ ); } } @@ -30250,21 +30372,21 @@ library (sg13g2_stdcell_fast_1p65V_m40C) { rise_power (passive_POWER_7x1ds1) { index_1 ("0.0186, 0.0966, 0.174, 0.3294, 0.6408, 1.263, 2.5074"); values ( \ - "0.0454794, 0.0478443, 0.0524625, 0.0636623, 0.0881267, 0.138747, 0.240978" \ + "0.0454947, 0.0478444, 0.0524625, 0.0636623, 0.0881267, 0.138747, 0.240978" \ ); } fall_power (passive_POWER_7x1ds1) { index_1 ("0.0186, 0.0966, 0.174, 0.3294, 0.6408, 1.263, 2.5074"); values ( \ - "0.0667629, 0.0804495, 0.0856261, 0.0969152, 0.121041, 0.170681, 0.270474" \ + "0.066763, 0.0804495, 0.0856261, 0.0969152, 0.121041, 0.170681, 0.270474" \ ); } } } ff (IQ,IQN) { - clear : "RESET_B'"; + clear : "!RESET_B"; clocked_on : "CLK"; - next_state : "(SCE*SCD)+(SCE'*D)"; + next_state : "(SCE*SCD)+(!SCE*D)"; } test_cell () { pin (Q) { @@ -30295,7 +30417,7 @@ library (sg13g2_stdcell_fast_1p65V_m40C) { signal_type : test_scan_enable; } ff (IQ,IQN) { - clear : "RESET_B'"; + clear : "!RESET_B"; clocked_on : "CLK"; next_state : "D"; } @@ -30381,6 +30503,7 @@ library (sg13g2_stdcell_fast_1p65V_m40C) { timing () { related_pin : "CLK"; sdf_cond : "SCE == 1'b1"; + sdf_edges : start_edge; timing_sense : non_unate; timing_type : rising_edge; when : "SCE"; @@ -30440,6 +30563,7 @@ library (sg13g2_stdcell_fast_1p65V_m40C) { timing () { related_pin : "CLK"; sdf_cond : "SCE == 1'b0"; + sdf_edges : start_edge; timing_sense : non_unate; timing_type : rising_edge; when : "!SCE"; @@ -30498,6 +30622,7 @@ library (sg13g2_stdcell_fast_1p65V_m40C) { } timing () { related_pin : "CLK"; + sdf_edges : start_edge; timing_sense : non_unate; timing_type : rising_edge; cell_rise (TIMING_DELAY_7x7ds1) { @@ -30555,6 +30680,7 @@ library (sg13g2_stdcell_fast_1p65V_m40C) { } timing () { related_pin : "RESET_B"; + sdf_edges : start_edge; timing_sense : positive_unate; timing_type : clear; cell_fall (TIMING_DELAY_7x7ds1) { @@ -30701,9 +30827,9 @@ library (sg13g2_stdcell_fast_1p65V_m40C) { max_transition : 2.5074; capacitance : 0.003336; rise_capacitance : 0.00339097; - rise_capacitance_range (0.00339097, 0.00339097); + rise_capacitance_range (0.0029746, 0.00374945); fall_capacitance : 0.00326533; - fall_capacitance_range (0.00326533, 0.00326533); + fall_capacitance_range (0.00294866, 0.00352635); timing () { related_pin : "CLK"; timing_type : min_pulse_width; @@ -30745,7 +30871,7 @@ library (sg13g2_stdcell_fast_1p65V_m40C) { fall_power (passive_POWER_7x1ds1) { index_1 ("0.0186, 0.0966, 0.174, 0.3294, 0.6408, 1.263, 2.5074"); values ( \ - "0.0399791, 0.0424482, 0.0460863, 0.0542239, 0.0713683, 0.106117, 0.178264" \ + "0.039979, 0.0424482, 0.0460862, 0.0542238, 0.0713683, 0.106117, 0.178264" \ ); } } @@ -30844,11 +30970,12 @@ library (sg13g2_stdcell_fast_1p65V_m40C) { max_transition : 2.5074; capacitance : 0.00312057; rise_capacitance : 0.0032059; - rise_capacitance_range (0.0032059, 0.0032059); + rise_capacitance_range (0.00266042, 0.00365774); fall_capacitance : 0.00303525; - fall_capacitance_range (0.00303525, 0.00303525); + fall_capacitance_range (0.00266067, 0.00322828); timing () { related_pin : "CLK"; + sdf_edges : both_edges; timing_type : hold_rising; rise_constraint (CONSTRAINT_4x4) { index_1 ("0.0186, 0.51636, 1.263, 2.5074"); @@ -30873,6 +31000,7 @@ library (sg13g2_stdcell_fast_1p65V_m40C) { } timing () { related_pin : "CLK"; + sdf_edges : both_edges; timing_type : setup_rising; rise_constraint (CONSTRAINT_4x4) { index_1 ("0.0186, 0.51636, 1.263, 2.5074"); @@ -30932,9 +31060,10 @@ library (sg13g2_stdcell_fast_1p65V_m40C) { rise_capacitance : 0.00559445; rise_capacitance_range (0.00559445, 0.00559445); fall_capacitance : 0.00559445; - fall_capacitance_range (0.00559445, 0.00559445); + fall_capacitance_range (0.00512437, 0.00594721); timing () { related_pin : "CLK"; + sdf_edges : both_edges; timing_type : recovery_rising; rise_constraint (CONSTRAINT_4x4) { index_1 ("0.0186, 0.51636, 1.263, 2.5074"); @@ -30949,6 +31078,7 @@ library (sg13g2_stdcell_fast_1p65V_m40C) { } timing () { related_pin : "CLK"; + sdf_edges : both_edges; timing_type : removal_rising; rise_constraint (CONSTRAINT_4x4) { index_1 ("0.0186, 0.51636, 1.263, 2.5074"); @@ -30978,11 +31108,12 @@ library (sg13g2_stdcell_fast_1p65V_m40C) { max_transition : 2.5074; capacitance : 0.00325207; rise_capacitance : 0.00330872; - rise_capacitance_range (0.00330872, 0.00330872); + rise_capacitance_range (0.00276989, 0.00375966); fall_capacitance : 0.00313876; - fall_capacitance_range (0.00313876, 0.00313876); + fall_capacitance_range (0.00276581, 0.00333093); timing () { related_pin : "CLK"; + sdf_edges : both_edges; timing_type : hold_rising; rise_constraint (CONSTRAINT_4x4) { index_1 ("0.0186, 0.51636, 1.263, 2.5074"); @@ -31007,6 +31138,7 @@ library (sg13g2_stdcell_fast_1p65V_m40C) { } timing () { related_pin : "CLK"; + sdf_edges : both_edges; timing_type : setup_rising; rise_constraint (CONSTRAINT_4x4) { index_1 ("0.0186, 0.51636, 1.263, 2.5074"); @@ -31034,7 +31166,7 @@ library (sg13g2_stdcell_fast_1p65V_m40C) { rise_power (passive_POWER_7x1ds1) { index_1 ("0.0186, 0.0966, 0.174, 0.3294, 0.6408, 1.263, 2.5074"); values ( \ - "0.038535, 0.0398559, 0.0423427, 0.0480211, 0.0607675, 0.0868257, 0.139437" \ + "0.038535, 0.0398559, 0.0423427, 0.0480211, 0.0607674, 0.0868257, 0.139437" \ ); } fall_power (passive_POWER_7x1ds1) { @@ -31048,7 +31180,7 @@ library (sg13g2_stdcell_fast_1p65V_m40C) { rise_power (passive_POWER_7x1ds1) { index_1 ("0.0186, 0.0966, 0.174, 0.3294, 0.6408, 1.263, 2.5074"); values ( \ - "0.038535, 0.0398559, 0.0423427, 0.0480211, 0.0607675, 0.0868257, 0.139437" \ + "0.038535, 0.0398559, 0.0423427, 0.0480211, 0.0607674, 0.0868257, 0.139437" \ ); } fall_power (passive_POWER_7x1ds1) { @@ -31065,11 +31197,12 @@ library (sg13g2_stdcell_fast_1p65V_m40C) { max_transition : 2.5074; capacitance : 0.00558363; rise_capacitance : 0.00594935; - rise_capacitance_range (0.00594935, 0.00594935); + rise_capacitance_range (0.00489759, 0.006562); fall_capacitance : 0.00521791; - fall_capacitance_range (0.00521791, 0.00521791); + fall_capacitance_range (0.00492896, 0.00572799); timing () { related_pin : "CLK"; + sdf_edges : both_edges; timing_type : hold_rising; rise_constraint (CONSTRAINT_4x4) { index_1 ("0.0186, 0.51636, 1.263, 2.5074"); @@ -31094,6 +31227,7 @@ library (sg13g2_stdcell_fast_1p65V_m40C) { } timing () { related_pin : "CLK"; + sdf_edges : both_edges; timing_type : setup_rising; rise_constraint (CONSTRAINT_4x4) { index_1 ("0.0186, 0.51636, 1.263, 2.5074"); @@ -31162,9 +31296,9 @@ library (sg13g2_stdcell_fast_1p65V_m40C) { } } ff (IQ,IQN) { - clear : "RESET_B'"; + clear : "!RESET_B"; clocked_on : "CLK"; - next_state : "(SCE*SCD)+(SCE'*D)"; + next_state : "(SCE*SCD)+(!SCE*D)"; } test_cell () { pin (Q) { @@ -31190,7 +31324,7 @@ library (sg13g2_stdcell_fast_1p65V_m40C) { signal_type : test_scan_enable; } ff (IQ,IQN) { - clear : "RESET_B'"; + clear : "!RESET_B"; clocked_on : "CLK"; next_state : "D"; } @@ -31253,11 +31387,11 @@ library (sg13g2_stdcell_fast_1p65V_m40C) { when : "!CLK&!D&RESET_B&SCD&SCE&Q"; } leakage_power () { - value : 7697.93; + value : 7697.92; when : "CLK&!D&RESET_B&!SCD&SCE&!Q"; } leakage_power () { - value : 6264.93; + value : 6264.92; when : "CLK&!D&RESET_B&!SCD&SCE&Q"; } leakage_power () { @@ -31276,6 +31410,7 @@ library (sg13g2_stdcell_fast_1p65V_m40C) { timing () { related_pin : "CLK"; sdf_cond : "SCE == 1'b1"; + sdf_edges : start_edge; timing_sense : non_unate; timing_type : rising_edge; when : "SCE"; @@ -31335,6 +31470,7 @@ library (sg13g2_stdcell_fast_1p65V_m40C) { timing () { related_pin : "CLK"; sdf_cond : "SCE == 1'b0"; + sdf_edges : start_edge; timing_sense : non_unate; timing_type : rising_edge; when : "!SCE"; @@ -31393,6 +31529,7 @@ library (sg13g2_stdcell_fast_1p65V_m40C) { } timing () { related_pin : "CLK"; + sdf_edges : start_edge; timing_sense : non_unate; timing_type : rising_edge; cell_rise (TIMING_DELAY_7x7ds1) { @@ -31450,6 +31587,7 @@ library (sg13g2_stdcell_fast_1p65V_m40C) { } timing () { related_pin : "RESET_B"; + sdf_edges : start_edge; timing_sense : positive_unate; timing_type : clear; cell_fall (TIMING_DELAY_7x7ds1) { @@ -31596,9 +31734,9 @@ library (sg13g2_stdcell_fast_1p65V_m40C) { max_transition : 2.5074; capacitance : 0.00333584; rise_capacitance : 0.00339074; - rise_capacitance_range (0.00339074, 0.00339074); + rise_capacitance_range (0.00297419, 0.00374946); fall_capacitance : 0.00326526; - fall_capacitance_range (0.00326526, 0.00326526); + fall_capacitance_range (0.0029482, 0.00352635); timing () { related_pin : "CLK"; timing_type : min_pulse_width; @@ -31663,7 +31801,7 @@ library (sg13g2_stdcell_fast_1p65V_m40C) { rise_power (passive_POWER_7x1ds1) { index_1 ("0.0186, 0.0966, 0.174, 0.3294, 0.6408, 1.263, 2.5074"); values ( \ - "0.0179803, 0.0201376, 0.0235035, 0.0315426, 0.0482847, 0.0827541, 0.155114" \ + "0.0179803, 0.0201376, 0.0235035, 0.0315426, 0.0482848, 0.0827541, 0.155114" \ ); } fall_power (passive_POWER_7x1ds1) { @@ -31739,11 +31877,12 @@ library (sg13g2_stdcell_fast_1p65V_m40C) { max_transition : 2.5074; capacitance : 0.00311793; rise_capacitance : 0.00320345; - rise_capacitance_range (0.00320345, 0.00320345); + rise_capacitance_range (0.00265723, 0.00365539); fall_capacitance : 0.00303241; - fall_capacitance_range (0.00303241, 0.00303241); + fall_capacitance_range (0.00265521, 0.00322594); timing () { related_pin : "CLK"; + sdf_edges : both_edges; timing_type : hold_rising; rise_constraint (CONSTRAINT_4x4) { index_1 ("0.0186, 0.51636, 1.263, 2.5074"); @@ -31768,6 +31907,7 @@ library (sg13g2_stdcell_fast_1p65V_m40C) { } timing () { related_pin : "CLK"; + sdf_edges : both_edges; timing_type : setup_rising; rise_constraint (CONSTRAINT_4x4) { index_1 ("0.0186, 0.51636, 1.263, 2.5074"); @@ -31827,9 +31967,10 @@ library (sg13g2_stdcell_fast_1p65V_m40C) { rise_capacitance : 0.00559919; rise_capacitance_range (0.00559919, 0.00559919); fall_capacitance : 0.00559919; - fall_capacitance_range (0.00559919, 0.00559919); + fall_capacitance_range (0.00513885, 0.00595193); timing () { related_pin : "CLK"; + sdf_edges : both_edges; timing_type : recovery_rising; rise_constraint (CONSTRAINT_4x4) { index_1 ("0.0186, 0.51636, 1.263, 2.5074"); @@ -31844,6 +31985,7 @@ library (sg13g2_stdcell_fast_1p65V_m40C) { } timing () { related_pin : "CLK"; + sdf_edges : both_edges; timing_type : removal_rising; rise_constraint (CONSTRAINT_4x4) { index_1 ("0.0186, 0.51636, 1.263, 2.5074"); @@ -31873,11 +32015,12 @@ library (sg13g2_stdcell_fast_1p65V_m40C) { max_transition : 2.5074; capacitance : 0.00325067; rise_capacitance : 0.00330734; - rise_capacitance_range (0.00330734, 0.00330734); + rise_capacitance_range (0.00276886, 0.00375822); fall_capacitance : 0.00313733; - fall_capacitance_range (0.00313733, 0.00313733); + fall_capacitance_range (0.0027644, 0.0033295); timing () { related_pin : "CLK"; + sdf_edges : both_edges; timing_type : hold_rising; rise_constraint (CONSTRAINT_4x4) { index_1 ("0.0186, 0.51636, 1.263, 2.5074"); @@ -31902,6 +32045,7 @@ library (sg13g2_stdcell_fast_1p65V_m40C) { } timing () { related_pin : "CLK"; + sdf_edges : both_edges; timing_type : setup_rising; rise_constraint (CONSTRAINT_4x4) { index_1 ("0.0186, 0.51636, 1.263, 2.5074"); @@ -31960,11 +32104,12 @@ library (sg13g2_stdcell_fast_1p65V_m40C) { max_transition : 2.5074; capacitance : 0.00558384; rise_capacitance : 0.00594935; - rise_capacitance_range (0.00594935, 0.00594935); + rise_capacitance_range (0.00489759, 0.006562); fall_capacitance : 0.00521832; - fall_capacitance_range (0.00521832, 0.00521832); + fall_capacitance_range (0.00492893, 0.00572799); timing () { related_pin : "CLK"; + sdf_edges : both_edges; timing_type : hold_rising; rise_constraint (CONSTRAINT_4x4) { index_1 ("0.0186, 0.51636, 1.263, 2.5074"); @@ -31989,6 +32134,7 @@ library (sg13g2_stdcell_fast_1p65V_m40C) { } timing () { related_pin : "CLK"; + sdf_edges : both_edges; timing_type : setup_rising; rise_constraint (CONSTRAINT_4x4) { index_1 ("0.0186, 0.51636, 1.263, 2.5074"); @@ -32057,9 +32203,9 @@ library (sg13g2_stdcell_fast_1p65V_m40C) { } } ff (IQ,IQN) { - clear : "RESET_B'"; + clear : "!RESET_B"; clocked_on : "CLK"; - next_state : "(SCE*SCD)+(SCE'*D)"; + next_state : "(SCE*SCD)+(!SCE*D)"; } test_cell () { pin (Q) { @@ -32085,7 +32231,7 @@ library (sg13g2_stdcell_fast_1p65V_m40C) { signal_type : test_scan_enable; } ff (IQ,IQN) { - clear : "RESET_B'"; + clear : "!RESET_B"; clocked_on : "CLK"; next_state : "D"; } @@ -32093,7 +32239,7 @@ library (sg13g2_stdcell_fast_1p65V_m40C) { } cell (sg13g2_sighold) { area : 9.072; - cell_footprint : "keepstate"; + cell_footprint : "sighold"; cell_leakage_power : 1643.61; dont_touch : true; dont_use : true; @@ -32131,7 +32277,7 @@ library (sg13g2_stdcell_fast_1p65V_m40C) { } cell (sg13g2_slgcp_1) { area : 30.8448; - cell_footprint : "sgclk"; + cell_footprint : "slgcp"; cell_leakage_power : 3666.94; clock_gating_integrated_cell : "latch_posedge_precontrol"; dont_touch : true; @@ -32270,9 +32416,9 @@ library (sg13g2_stdcell_fast_1p65V_m40C) { max_transition : 2.5074; capacitance : 0.00566951; rise_capacitance : 0.00585066; - rise_capacitance_range (0.00585066, 0.00585066); + rise_capacitance_range (0.00484058, 0.00676772); fall_capacitance : 0.00548836; - fall_capacitance_range (0.00548836, 0.00548836); + fall_capacitance_range (0.00500771, 0.00581865); timing () { related_pin : "CLK"; timing_type : min_pulse_width; @@ -32310,11 +32456,12 @@ library (sg13g2_stdcell_fast_1p65V_m40C) { max_transition : 2.5074; capacitance : 0.00219604; rise_capacitance : 0.00273045; - rise_capacitance_range (0.00273045, 0.00273045); + rise_capacitance_range (0.00235753, 0.00313406); fall_capacitance : 0.00166162; - fall_capacitance_range (0.00166162, 0.00166162); + fall_capacitance_range (0.00166162, 0.00255966); timing () { related_pin : "CLK"; + sdf_edges : both_edges; timing_type : hold_rising; rise_constraint (CONSTRAINT_4x4) { index_1 ("0.0186, 0.51636, 1.263, 2.5074"); @@ -32339,6 +32486,7 @@ library (sg13g2_stdcell_fast_1p65V_m40C) { } timing () { related_pin : "CLK"; + sdf_edges : both_edges; timing_type : setup_rising; rise_constraint (CONSTRAINT_4x4) { index_1 ("0.0186, 0.51636, 1.263, 2.5074"); @@ -32397,11 +32545,12 @@ library (sg13g2_stdcell_fast_1p65V_m40C) { max_transition : 2.5074; capacitance : 0.00263511; rise_capacitance : 0.00257659; - rise_capacitance_range (0.00257659, 0.00257659); + rise_capacitance_range (0.00231691, 0.0028123); fall_capacitance : 0.00269362; - fall_capacitance_range (0.00269362, 0.00269362); + fall_capacitance_range (0.00246285, 0.00281544); timing () { related_pin : "CLK"; + sdf_edges : both_edges; timing_type : hold_rising; rise_constraint (CONSTRAINT_4x4) { index_1 ("0.0186, 0.51636, 1.263, 2.5074"); @@ -32426,6 +32575,7 @@ library (sg13g2_stdcell_fast_1p65V_m40C) { } timing () { related_pin : "CLK"; + sdf_edges : both_edges; timing_type : setup_rising; rise_constraint (CONSTRAINT_4x4) { index_1 ("0.0186, 0.51636, 1.263, 2.5074"); @@ -32466,7 +32616,7 @@ library (sg13g2_stdcell_fast_1p65V_m40C) { } cell (sg13g2_tiehi) { area : 7.2576; - cell_footprint : "tie1"; + cell_footprint : "tiehi"; cell_leakage_power : 977.89; pin (L_HI) { direction : "output"; @@ -32476,7 +32626,7 @@ library (sg13g2_stdcell_fast_1p65V_m40C) { } cell (sg13g2_tielo) { area : 7.2576; - cell_footprint : "tie0"; + cell_footprint : "tielo"; cell_leakage_power : 1134.26; pin (L_LO) { direction : "output"; @@ -32486,7 +32636,7 @@ library (sg13g2_stdcell_fast_1p65V_m40C) { } cell (sg13g2_xnor2_1) { area : 14.5152; - cell_footprint : "xnor2_1"; + cell_footprint : "xnor2"; cell_leakage_power : 1834.59; leakage_power () { value : 2725.61; @@ -33043,23 +33193,23 @@ library (sg13g2_stdcell_fast_1p65V_m40C) { max_transition : 2.5074; capacitance : 0.00644683; rise_capacitance : 0.00646025; - rise_capacitance_range (0.00646025, 0.00646025); + rise_capacitance_range (0.00533518, 0.00739705); fall_capacitance : 0.0064334; - fall_capacitance_range (0.0064334, 0.0064334); + fall_capacitance_range (0.00535646, 0.00711987); } pin (B) { direction : "input"; max_transition : 2.5074; capacitance : 0.00565297; rise_capacitance : 0.00567735; - rise_capacitance_range (0.00567735, 0.00567735); + rise_capacitance_range (0.00498872, 0.00677542); fall_capacitance : 0.00562859; - fall_capacitance_range (0.00562859, 0.00562859); + fall_capacitance_range (0.00486627, 0.0065265); } } cell (sg13g2_xor2_1) { area : 14.5152; - cell_footprint : "xor2_1"; + cell_footprint : "xor2"; cell_leakage_power : 1605.4; leakage_power () { value : 1457.16; @@ -33616,18 +33766,18 @@ library (sg13g2_stdcell_fast_1p65V_m40C) { max_transition : 2.5074; capacitance : 0.00657785; rise_capacitance : 0.00658325; - rise_capacitance_range (0.00658325, 0.00658325); + rise_capacitance_range (0.005499, 0.00731499); fall_capacitance : 0.00657245; - fall_capacitance_range (0.00657245, 0.00657245); + fall_capacitance_range (0.00536251, 0.00749488); } pin (B) { direction : "input"; max_transition : 2.5074; capacitance : 0.00569246; rise_capacitance : 0.00576961; - rise_capacitance_range (0.00576961, 0.00576961); + rise_capacitance_range (0.00486863, 0.00688243); fall_capacitance : 0.00561531; - fall_capacitance_range (0.00561531, 0.00561531); + fall_capacitance_range (0.00506592, 0.00629664); } } } diff --git a/flow/platforms/ihp-sg13g2/lib/sg13g2_stdcell_slow_1p08V_125C.lib b/flow/platforms/ihp-sg13g2/lib/sg13g2_stdcell_slow_1p08V_125C.lib index 6dd075da10..a8077d89a5 100644 --- a/flow/platforms/ihp-sg13g2/lib/sg13g2_stdcell_slow_1p08V_125C.lib +++ b/flow/platforms/ihp-sg13g2/lib/sg13g2_stdcell_slow_1p08V_125C.lib @@ -18,8 +18,8 @@ library (sg13g2_stdcell_slow_1p08V_125C) { comment : "IHP Microelectronics GmbH, 2025"; - date : "$Date: Fri Jun 13 13:26:46 2025 $"; - revision : "$Revision: 0.1.3 $"; + date : "$Date: Tue Nov 4 18:39:49 2025 $"; + revision : "$Revision: 0.1.4 $"; delay_model : table_lookup; capacitive_load_unit (1,pf); current_unit : "1uA"; @@ -210,7 +210,7 @@ library (sg13g2_stdcell_slow_1p08V_125C) { } cell (sg13g2_a21o_1) { area : 12.7008; - cell_footprint : "AO21"; + cell_footprint : "a21o"; cell_leakage_power : 650.173; leakage_power () { value : 628.06; @@ -483,7 +483,7 @@ library (sg13g2_stdcell_slow_1p08V_125C) { } timing () { related_pin : "B1"; - sdf_cond : "A1 == 1'b1 & A2 == 1'b0"; + sdf_cond : "A1 == 1'b1 && A2 == 1'b0"; timing_sense : positive_unate; timing_type : combinational; when : "(A1 * !A2)"; @@ -542,7 +542,7 @@ library (sg13g2_stdcell_slow_1p08V_125C) { } timing () { related_pin : "B1"; - sdf_cond : "A1 == 1'b0 & A2 == 1'b1"; + sdf_cond : "A1 == 1'b0 && A2 == 1'b1"; timing_sense : positive_unate; timing_type : combinational; when : "(!A1 * A2)"; @@ -601,7 +601,7 @@ library (sg13g2_stdcell_slow_1p08V_125C) { } timing () { related_pin : "B1"; - sdf_cond : "A1 == 1'b0 & A2 == 1'b0"; + sdf_cond : "A1 == 1'b0 && A2 == 1'b0"; timing_sense : positive_unate; timing_type : combinational; when : "(!A1 * !A2)"; @@ -958,32 +958,32 @@ library (sg13g2_stdcell_slow_1p08V_125C) { max_transition : 2.5074; capacitance : 0.00253334; rise_capacitance : 0.00255682; - rise_capacitance_range (0.00255682, 0.00255682); + rise_capacitance_range (0.00238449, 0.00269146); fall_capacitance : 0.00250986; - fall_capacitance_range (0.00250986, 0.00250986); + fall_capacitance_range (0.00225284, 0.00283316); } pin (A2) { direction : "input"; max_transition : 2.5074; capacitance : 0.00260367; rise_capacitance : 0.00265225; - rise_capacitance_range (0.00265225, 0.00265225); + rise_capacitance_range (0.00237528, 0.00294267); fall_capacitance : 0.00255508; - fall_capacitance_range (0.00255508, 0.00255508); + fall_capacitance_range (0.00234665, 0.00285008); } pin (B1) { direction : "input"; max_transition : 2.5074; capacitance : 0.0024607; rise_capacitance : 0.00251472; - rise_capacitance_range (0.00251472, 0.00251472); + rise_capacitance_range (0.00217826, 0.00274763); fall_capacitance : 0.00240668; - fall_capacitance_range (0.00240668, 0.00240668); + fall_capacitance_range (0.00218255, 0.00259251); } } cell (sg13g2_a21o_2) { area : 14.5152; - cell_footprint : "AO21"; + cell_footprint : "a21o"; cell_leakage_power : 929.312; leakage_power () { value : 1133.82; @@ -1256,7 +1256,7 @@ library (sg13g2_stdcell_slow_1p08V_125C) { } timing () { related_pin : "B1"; - sdf_cond : "A1 == 1'b1 & A2 == 1'b0"; + sdf_cond : "A1 == 1'b1 && A2 == 1'b0"; timing_sense : positive_unate; timing_type : combinational; when : "(A1 * !A2)"; @@ -1315,7 +1315,7 @@ library (sg13g2_stdcell_slow_1p08V_125C) { } timing () { related_pin : "B1"; - sdf_cond : "A1 == 1'b0 & A2 == 1'b1"; + sdf_cond : "A1 == 1'b0 && A2 == 1'b1"; timing_sense : positive_unate; timing_type : combinational; when : "(!A1 * A2)"; @@ -1374,7 +1374,7 @@ library (sg13g2_stdcell_slow_1p08V_125C) { } timing () { related_pin : "B1"; - sdf_cond : "A1 == 1'b0 & A2 == 1'b0"; + sdf_cond : "A1 == 1'b0 && A2 == 1'b0"; timing_sense : positive_unate; timing_type : combinational; when : "(!A1 * !A2)"; @@ -1731,33 +1731,33 @@ library (sg13g2_stdcell_slow_1p08V_125C) { max_transition : 2.5074; capacitance : 0.0027076; rise_capacitance : 0.00270628; - rise_capacitance_range (0.00270628, 0.00270628); + rise_capacitance_range (0.00253717, 0.00285216); fall_capacitance : 0.00270893; - fall_capacitance_range (0.00270893, 0.00270893); + fall_capacitance_range (0.00245565, 0.00302222); } pin (A2) { direction : "input"; max_transition : 2.5074; capacitance : 0.00267717; rise_capacitance : 0.00270783; - rise_capacitance_range (0.00270783, 0.00270783); + rise_capacitance_range (0.00240346, 0.00302625); fall_capacitance : 0.00264651; - fall_capacitance_range (0.00264651, 0.00264651); + fall_capacitance_range (0.00243674, 0.00293492); } pin (B1) { direction : "input"; max_transition : 2.5074; capacitance : 0.00257443; rise_capacitance : 0.00261069; - rise_capacitance_range (0.00261069, 0.00261069); + rise_capacitance_range (0.00233015, 0.00284477); fall_capacitance : 0.00253818; - fall_capacitance_range (0.00253818, 0.00253818); + fall_capacitance_range (0.0023473, 0.00269004); } } cell (sg13g2_a21oi_1) { area : 9.072; cell_footprint : "a21oi"; - cell_leakage_power : 439.035; + cell_leakage_power : 439.036; leakage_power () { value : 180.608; when : "!A1&!A2&!B1&Y"; @@ -1767,7 +1767,7 @@ library (sg13g2_stdcell_slow_1p08V_125C) { when : "!A1&!A2&B1&!Y"; } leakage_power () { - value : 274.49; + value : 274.491; when : "!A1&A2&!B1&Y"; } leakage_power () { @@ -1779,7 +1779,7 @@ library (sg13g2_stdcell_slow_1p08V_125C) { when : "A1&!A2&!B1&Y"; } leakage_power () { - value : 488.072; + value : 488.073; when : "A1&!A2&B1&!Y"; } leakage_power () { @@ -1803,12 +1803,12 @@ library (sg13g2_stdcell_slow_1p08V_125C) { index_1 ("0.0186, 0.0966, 0.174, 0.3294, 0.6408, 1.263, 2.5074"); index_2 ("0.001, 0.0234, 0.039, 0.0648, 0.108, 0.18, 0.3"); values ( \ - "0.0694622, 0.275387, 0.416857, 0.650431, 1.04163, 1.69354, 2.78023", \ - "0.102001, 0.311923, 0.453785, 0.688435, 1.07939, 1.73278, 2.81863", \ - "0.125308, 0.345166, 0.487329, 0.721847, 1.11367, 1.76595, 2.85427", \ - "0.159292, 0.406853, 0.551882, 0.786695, 1.17872, 1.83527, 2.91873", \ - "0.198123, 0.507278, 0.666397, 0.910419, 1.30482, 1.95762, 3.045", \ - "0.235073, 0.654947, 0.849696, 1.12466, 1.54402, 2.20595, 3.29364", \ + "0.0694598, 0.275392, 0.416798, 0.65034, 1.0419, 1.69357, 2.78023", \ + "0.101991, 0.311877, 0.453784, 0.688433, 1.07939, 1.73279, 2.81936", \ + "0.125331, 0.345166, 0.487323, 0.721786, 1.11364, 1.76597, 2.85425", \ + "0.159292, 0.406853, 0.551879, 0.786694, 1.17872, 1.83216, 2.91882", \ + "0.198123, 0.507278, 0.666396, 0.910413, 1.30482, 1.95762, 3.04483", \ + "0.235073, 0.654947, 0.849695, 1.12466, 1.54402, 2.20595, 3.29398", \ "0.274011, 0.864115, 1.12072, 1.46651, 1.95734, 2.67928, 3.79911" \ ); } @@ -1816,12 +1816,12 @@ library (sg13g2_stdcell_slow_1p08V_125C) { index_1 ("0.0186, 0.0966, 0.174, 0.3294, 0.6408, 1.263, 2.5074"); index_2 ("0.001, 0.0234, 0.039, 0.0648, 0.108, 0.18, 0.3"); values ( \ - "0.0433339, 0.322964, 0.517677, 0.839721, 1.3786, 2.27688, 3.77404", \ - "0.0486301, 0.323731, 0.518305, 0.839722, 1.37861, 2.27695, 3.77531", \ - "0.0580601, 0.325373, 0.518306, 0.839723, 1.37862, 2.27783, 3.77532", \ - "0.0771734, 0.33981, 0.525761, 0.841421, 1.38433, 2.28077, 3.77533", \ - "0.11662, 0.386014, 0.563412, 0.863872, 1.3863, 2.28078, 3.77534", \ - "0.18802, 0.487052, 0.664609, 0.951792, 1.44585, 2.30413, 3.79558", \ + "0.0433505, 0.322981, 0.517741, 0.839547, 1.37852, 2.27696, 3.77404", \ + "0.0486001, 0.323107, 0.518305, 0.839652, 1.37941, 2.27697, 3.77405", \ + "0.0580498, 0.325373, 0.518306, 0.839653, 1.37942, 2.27783, 3.77492", \ + "0.0771734, 0.33981, 0.52576, 0.841421, 1.38433, 2.2784, 3.77493", \ + "0.11662, 0.386014, 0.563412, 0.86379, 1.3863, 2.27841, 3.77494", \ + "0.18802, 0.487051, 0.664609, 0.951793, 1.44585, 2.30413, 3.79197", \ "0.315741, 0.670476, 0.864093, 1.16165, 1.64002, 2.4543, 3.86161" \ ); } @@ -1829,25 +1829,25 @@ library (sg13g2_stdcell_slow_1p08V_125C) { index_1 ("0.0186, 0.0966, 0.174, 0.3294, 0.6408, 1.263, 2.5074"); index_2 ("0.001, 0.0234, 0.039, 0.0648, 0.108, 0.18, 0.3"); values ( \ - "0.0594867, 0.21615, 0.322424, 0.497534, 0.790171, 1.27748, 2.08945", \ - "0.0941977, 0.257966, 0.364291, 0.539486, 0.832173, 1.31967, 2.13222", \ - "0.119516, 0.29972, 0.406858, 0.581974, 0.8746, 1.36275, 2.17407", \ - "0.157677, 0.375365, 0.490211, 0.668579, 0.961017, 1.44827, 2.26086", \ - "0.20902, 0.492107, 0.629178, 0.828986, 1.13141, 1.61862, 2.4289", \ - "0.278679, 0.662814, 0.839654, 1.08493, 1.43623, 1.95661, 2.77469", \ - "0.371483, 0.893753, 1.13947, 1.46524, 1.91071, 2.52992, 3.43242" \ + "0.0594955, 0.21609, 0.322406, 0.497396, 0.79019, 1.27748, 2.08942", \ + "0.0942006, 0.257973, 0.364292, 0.539461, 0.832173, 1.31968, 2.13223", \ + "0.119516, 0.299696, 0.406881, 0.581778, 0.874578, 1.36206, 2.17405", \ + "0.157677, 0.375365, 0.490211, 0.668556, 0.961017, 1.44827, 2.2609", \ + "0.208926, 0.492107, 0.629178, 0.828986, 1.13141, 1.61862, 2.42885", \ + "0.278679, 0.662813, 0.839654, 1.08493, 1.43623, 1.95661, 2.77489", \ + "0.371483, 0.893752, 1.13947, 1.46524, 1.91071, 2.52992, 3.43242" \ ); } fall_transition (TIMING_DELAY_7x7ds1) { index_1 ("0.0186, 0.0966, 0.174, 0.3294, 0.6408, 1.263, 2.5074"); index_2 ("0.001, 0.0234, 0.039, 0.0648, 0.108, 0.18, 0.3"); values ( \ - "0.0439009, 0.246011, 0.385998, 0.617889, 1.00552, 1.65007, 2.72766", \ - "0.0556834, 0.246953, 0.385999, 0.61789, 1.00553, 1.65127, 2.72767", \ - "0.0701621, 0.25673, 0.390191, 0.61845, 1.00554, 1.65191, 2.72768", \ - "0.0971684, 0.288848, 0.414293, 0.631069, 1.00902, 1.65192, 2.72856", \ - "0.140132, 0.361819, 0.487321, 0.690317, 1.04353, 1.6617, 2.73261", \ - "0.207841, 0.493783, 0.633951, 0.841346, 1.18003, 1.75333, 2.76586", \ + "0.0439488, 0.245773, 0.385998, 0.618044, 1.00552, 1.65007, 2.72772", \ + "0.0556177, 0.247161, 0.385999, 0.618045, 1.00553, 1.65127, 2.72773", \ + "0.0701621, 0.256626, 0.390718, 0.619232, 1.00554, 1.65128, 2.72774", \ + "0.0971684, 0.288848, 0.414292, 0.631032, 1.00902, 1.65129, 2.72856", \ + "0.139871, 0.361819, 0.487321, 0.690316, 1.04353, 1.6617, 2.7329", \ + "0.207841, 0.493791, 0.633951, 0.841346, 1.18003, 1.75334, 2.76468", \ "0.317871, 0.709556, 0.881889, 1.12346, 1.47866, 2.04464, 2.98952" \ ); } @@ -1860,37 +1860,37 @@ library (sg13g2_stdcell_slow_1p08V_125C) { index_1 ("0.0186, 0.0966, 0.174, 0.3294, 0.6408, 1.263, 2.5074"); index_2 ("0.001, 0.0234, 0.039, 0.0648, 0.108, 0.18, 0.3"); values ( \ - "0.080908, 0.286959, 0.428903, 0.663157, 1.05528, 1.70851, 2.79729", \ - "0.115586, 0.324185, 0.466148, 0.701059, 1.09312, 1.74751, 2.83534", \ - "0.141636, 0.357886, 0.500129, 0.734674, 1.12731, 1.78058, 2.87094", \ - "0.180354, 0.420607, 0.565153, 0.799967, 1.19253, 1.846, 2.93528", \ - "0.229254, 0.523617, 0.681127, 0.924385, 1.31893, 1.97275, 3.06183", \ - "0.281799, 0.67608, 0.867475, 1.14052, 1.55859, 2.2216, 3.31054", \ - "0.342228, 0.8937, 1.14453, 1.48612, 1.97479, 2.69553, 3.81668" \ + "0.080929, 0.286954, 0.428853, 0.663185, 1.05527, 1.70854, 2.79729", \ + "0.115598, 0.32415, 0.466156, 0.701061, 1.09288, 1.74752, 2.83525", \ + "0.141636, 0.357885, 0.500129, 0.734728, 1.12731, 1.78058, 2.87094", \ + "0.180354, 0.420607, 0.565152, 0.799966, 1.19236, 1.846, 2.93527", \ + "0.229254, 0.523617, 0.681127, 0.924382, 1.31893, 1.97264, 3.06289", \ + "0.281799, 0.67608, 0.867475, 1.14052, 1.55859, 2.2216, 3.31071", \ + "0.342228, 0.893699, 1.14453, 1.48612, 1.97479, 2.69561, 3.81668" \ ); } rise_transition (TIMING_DELAY_7x7ds1) { index_1 ("0.0186, 0.0966, 0.174, 0.3294, 0.6408, 1.263, 2.5074"); index_2 ("0.001, 0.0234, 0.039, 0.0648, 0.108, 0.18, 0.3"); values ( \ - "0.0541798, 0.33534, 0.530848, 0.853084, 1.39449, 2.29343, 3.79403", \ - "0.0582181, 0.335407, 0.530849, 0.853869, 1.3945, 2.2943, 3.7959", \ - "0.0671546, 0.3376, 0.531609, 0.855225, 1.39451, 2.29431, 3.79618", \ - "0.0857529, 0.35107, 0.538071, 0.855499, 1.39467, 2.29502, 3.79619", \ - "0.123817, 0.396613, 0.574344, 0.877126, 1.40122, 2.29654, 3.7962", \ - "0.193713, 0.494421, 0.674549, 0.963515, 1.45942, 2.31981, 3.81218", \ - "0.31428, 0.677262, 0.871069, 1.16988, 1.65228, 2.46929, 3.88049" \ + "0.0541675, 0.33534, 0.530848, 0.853516, 1.39449, 2.29343, 3.79403", \ + "0.0582057, 0.336049, 0.530849, 0.853876, 1.3945, 2.2943, 3.79476", \ + "0.0671546, 0.337602, 0.531608, 0.853877, 1.39451, 2.29431, 3.79618", \ + "0.0857529, 0.35107, 0.53807, 0.855498, 1.39568, 2.29502, 3.79619", \ + "0.123817, 0.396613, 0.574347, 0.877124, 1.40122, 2.29561, 3.7962", \ + "0.193713, 0.494421, 0.674548, 0.963516, 1.45942, 2.31981, 3.82063", \ + "0.314279, 0.677261, 0.871033, 1.16988, 1.65228, 2.4694, 3.88049" \ ); } cell_fall (TIMING_DELAY_7x7ds1) { index_1 ("0.0186, 0.0966, 0.174, 0.3294, 0.6408, 1.263, 2.5074"); index_2 ("0.001, 0.0234, 0.039, 0.0648, 0.108, 0.18, 0.3"); values ( \ - "0.0661013, 0.222596, 0.328723, 0.503786, 0.796452, 1.28383, 2.09578", \ - "0.101732, 0.262949, 0.36927, 0.544649, 0.837176, 1.32466, 2.13672", \ - "0.128251, 0.300915, 0.408107, 0.583446, 0.876263, 1.3637, 2.17583", \ + "0.0661043, 0.222471, 0.328723, 0.503787, 0.796451, 1.28384, 2.09578", \ + "0.10174, 0.262932, 0.369314, 0.544462, 0.837188, 1.32466, 2.13654", \ + "0.128251, 0.300922, 0.408109, 0.583444, 0.876309, 1.3637, 2.1758", \ "0.170185, 0.370863, 0.483692, 0.661949, 0.955425, 1.44313, 2.25606", \ - "0.226156, 0.483136, 0.612694, 0.806881, 1.10889, 1.59811, 2.41025", \ + "0.226156, 0.483136, 0.612694, 0.806881, 1.10889, 1.59814, 2.41025", \ "0.301575, 0.655248, 0.817746, 1.04772, 1.38529, 1.90099, 2.72123", \ "0.404792, 0.897772, 1.12458, 1.4237, 1.83716, 2.42733, 3.31278" \ ); @@ -1899,13 +1899,13 @@ library (sg13g2_stdcell_slow_1p08V_125C) { index_1 ("0.0186, 0.0966, 0.174, 0.3294, 0.6408, 1.263, 2.5074"); index_2 ("0.001, 0.0234, 0.039, 0.0648, 0.108, 0.18, 0.3"); values ( \ - "0.0438457, 0.246103, 0.386277, 0.617898, 1.0054, 1.65006, 2.72725", \ - "0.0504205, 0.246712, 0.386294, 0.617958, 1.00552, 1.65007, 2.72726", \ - "0.0602386, 0.252756, 0.389093, 0.622358, 1.00553, 1.65012, 2.72727", \ + "0.0438455, 0.245891, 0.38594, 0.617897, 1.00546, 1.65006, 2.7277", \ + "0.0504278, 0.246713, 0.385941, 0.617898, 1.00552, 1.65007, 2.72771", \ + "0.0602395, 0.252755, 0.389142, 0.622357, 1.00553, 1.65013, 2.72772", \ "0.0807638, 0.274085, 0.404478, 0.626481, 1.00799, 1.65084, 2.72864", \ - "0.118853, 0.327016, 0.45479, 0.667451, 1.0305, 1.65862, 2.72999", \ - "0.183654, 0.431746, 0.565314, 0.773585, 1.12484, 1.72143, 2.75463", \ - "0.291388, 0.615595, 0.771246, 0.997351, 1.34534, 1.92719, 2.908" \ + "0.118853, 0.327016, 0.45479, 0.667451, 1.0305, 1.65878, 2.7304", \ + "0.183654, 0.431746, 0.565314, 0.773593, 1.12483, 1.72143, 2.75463", \ + "0.291388, 0.615629, 0.771246, 0.997351, 1.34534, 1.92719, 2.908" \ ); } } @@ -1919,38 +1919,38 @@ library (sg13g2_stdcell_slow_1p08V_125C) { index_1 ("0.0186, 0.0966, 0.174, 0.3294, 0.6408, 1.263, 2.5074"); index_2 ("0.001, 0.0234, 0.039, 0.0648, 0.108, 0.18, 0.3"); values ( \ - "0.0655844, 0.274581, 0.416499, 0.65114, 1.04296, 1.69623, 2.78503", \ - "0.0966175, 0.30891, 0.451474, 0.686572, 1.07906, 1.73356, 2.82172", \ - "0.121116, 0.346766, 0.489357, 0.724461, 1.11722, 1.77098, 2.86159", \ + "0.0655825, 0.274576, 0.416499, 0.651144, 1.04296, 1.69623, 2.78502", \ + "0.0966071, 0.308944, 0.451499, 0.686572, 1.07907, 1.73355, 2.82173", \ + "0.121116, 0.346783, 0.489338, 0.724443, 1.11724, 1.77094, 2.86158", \ "0.156675, 0.419643, 0.565089, 0.799758, 1.19235, 1.84578, 2.93527", \ - "0.202241, 0.535853, 0.70025, 0.946418, 1.33951, 1.99197, 3.08251", \ - "0.257432, 0.70613, 0.914637, 1.20407, 1.63014, 2.29214, 3.37746", \ - "0.330025, 0.936553, 1.21801, 1.59502, 2.11722, 2.86114, 3.98812" \ + "0.202241, 0.535853, 0.70025, 0.946418, 1.33951, 1.99197, 3.08263", \ + "0.257432, 0.70613, 0.914637, 1.20407, 1.63014, 2.29214, 3.3774", \ + "0.330025, 0.936552, 1.21801, 1.59502, 2.11721, 2.86112, 3.98811" \ ); } rise_transition (TIMING_DELAY_7x7ds1) { index_1 ("0.0186, 0.0966, 0.174, 0.3294, 0.6408, 1.263, 2.5074"); index_2 ("0.001, 0.0234, 0.039, 0.0648, 0.108, 0.18, 0.3"); values ( \ - "0.0542766, 0.335723, 0.530834, 0.85363, 1.39329, 2.29344, 3.79401", \ - "0.0640157, 0.335724, 0.531141, 0.853631, 1.39451, 2.29479, 3.79495", \ - "0.0799126, 0.339406, 0.531477, 0.853632, 1.39452, 2.29555, 3.79525", \ - "0.10694, 0.36282, 0.544039, 0.856345, 1.39562, 2.29556, 3.79526", \ - "0.152156, 0.432921, 0.602036, 0.892021, 1.4057, 2.29659, 3.79655", \ - "0.218724, 0.565145, 0.74301, 1.02035, 1.49614, 2.33324, 3.80174", \ - "0.328766, 0.787924, 0.999426, 1.30514, 1.77655, 2.55769, 3.92717" \ + "0.0542794, 0.335724, 0.530834, 0.853629, 1.39329, 2.29344, 3.79401", \ + "0.0639523, 0.336046, 0.531168, 0.85363, 1.39451, 2.29479, 3.7949", \ + "0.0799125, 0.339403, 0.531476, 0.853631, 1.39452, 2.29555, 3.79525", \ + "0.10694, 0.36282, 0.544039, 0.856344, 1.39562, 2.29556, 3.79526", \ + "0.152156, 0.432921, 0.602035, 0.89202, 1.4057, 2.29659, 3.79669", \ + "0.218724, 0.565145, 0.74301, 1.02032, 1.49614, 2.33345, 3.8037", \ + "0.328766, 0.787926, 0.999426, 1.30514, 1.77655, 2.55859, 3.92675" \ ); } cell_fall (TIMING_DELAY_7x7ds1) { index_1 ("0.0186, 0.0966, 0.174, 0.3294, 0.6408, 1.263, 2.5074"); index_2 ("0.001, 0.0234, 0.039, 0.0648, 0.108, 0.18, 0.3"); values ( \ - "0.0307694, 0.115847, 0.173601, 0.269007, 0.428771, 0.695101, 1.1388", \ - "0.0601285, 0.165737, 0.224089, 0.319586, 0.47938, 0.746283, 1.1898", \ - "0.0781049, 0.208833, 0.272132, 0.369595, 0.52964, 0.795781, 1.24041", \ - "0.104772, 0.280158, 0.356281, 0.464952, 0.63041, 0.897352, 1.3406", \ + "0.030776, 0.115798, 0.173588, 0.269019, 0.428777, 0.695061, 1.13879", \ + "0.0601463, 0.165736, 0.224107, 0.319625, 0.479362, 0.746269, 1.18928", \ + "0.0781048, 0.208837, 0.272132, 0.369654, 0.529608, 0.795649, 1.24042", \ + "0.104772, 0.280158, 0.356281, 0.464952, 0.630416, 0.897472, 1.3406", \ "0.137504, 0.38495, 0.485836, 0.62113, 0.814213, 1.09513, 1.54057", \ - "0.177746, 0.532043, 0.67639, 0.859253, 1.10571, 1.44507, 1.93193", \ + "0.177746, 0.532043, 0.67639, 0.859253, 1.10571, 1.4449, 1.93193", \ "0.227834, 0.728491, 0.938168, 1.20519, 1.54397, 1.99101, 2.59177" \ ); } @@ -1958,13 +1958,13 @@ library (sg13g2_stdcell_slow_1p08V_125C) { index_1 ("0.0186, 0.0966, 0.174, 0.3294, 0.6408, 1.263, 2.5074"); index_2 ("0.001, 0.0234, 0.039, 0.0648, 0.108, 0.18, 0.3"); values ( \ - "0.0206747, 0.135168, 0.212557, 0.340555, 0.555137, 0.913006, 1.50943", \ - "0.0422348, 0.141941, 0.215099, 0.340743, 0.555138, 0.913544, 1.50944", \ - "0.0623299, 0.160091, 0.228363, 0.347701, 0.556698, 0.913545, 1.51009", \ - "0.0951207, 0.200748, 0.267011, 0.378147, 0.574059, 0.918411, 1.5101", \ - "0.145721, 0.278363, 0.348867, 0.461524, 0.644039, 0.962001, 1.52362", \ - "0.227721, 0.408975, 0.496195, 0.619583, 0.8115, 1.1175, 1.63497", \ - "0.359594, 0.617425, 0.739347, 0.898497, 1.12029, 1.44672, 1.96178" \ + "0.0206713, 0.135208, 0.212542, 0.340562, 0.555137, 0.912992, 1.50945", \ + "0.042207, 0.141941, 0.215085, 0.34077, 0.555138, 0.913545, 1.50946", \ + "0.0623299, 0.160096, 0.228363, 0.347759, 0.5567, 0.913546, 1.51009", \ + "0.0951207, 0.200748, 0.267011, 0.378147, 0.574097, 0.918429, 1.5101", \ + "0.145721, 0.278363, 0.348867, 0.461524, 0.64404, 0.962002, 1.52362", \ + "0.227721, 0.408975, 0.496195, 0.619583, 0.8115, 1.11716, 1.63497", \ + "0.359594, 0.617425, 0.739347, 0.898498, 1.12029, 1.44672, 1.96178" \ ); } } @@ -1978,38 +1978,38 @@ library (sg13g2_stdcell_slow_1p08V_125C) { index_1 ("0.0186, 0.0966, 0.174, 0.3294, 0.6408, 1.263, 2.5074"); index_2 ("0.001, 0.0234, 0.039, 0.0648, 0.108, 0.18, 0.3"); values ( \ - "0.0516052, 0.259695, 0.401102, 0.634921, 1.02597, 1.6781, 2.76464", \ - "0.0800215, 0.293974, 0.43598, 0.670429, 1.06215, 1.71437, 2.80111", \ - "0.100098, 0.331785, 0.47387, 0.708362, 1.10026, 1.75327, 2.84072", \ - "0.128099, 0.403645, 0.549628, 0.783674, 1.1751, 1.82904, 2.91562", \ - "0.162683, 0.516924, 0.683186, 0.930034, 1.32264, 1.9737, 3.06117", \ - "0.204212, 0.681252, 0.893581, 1.18599, 1.61255, 2.27413, 3.35704", \ - "0.257606, 0.902606, 1.19002, 1.57119, 2.09646, 2.8415, 3.96722" \ + "0.0516079, 0.2597, 0.401111, 0.634917, 1.02597, 1.6781, 2.76455", \ + "0.0800247, 0.293999, 0.43607, 0.670465, 1.06215, 1.71515, 2.80218", \ + "0.100098, 0.331785, 0.4739, 0.708218, 1.1003, 1.75325, 2.84092", \ + "0.128099, 0.403645, 0.549642, 0.783715, 1.1751, 1.82904, 2.91488", \ + "0.162682, 0.516924, 0.683186, 0.930033, 1.32264, 1.97389, 3.05997", \ + "0.204212, 0.681252, 0.893581, 1.18599, 1.61255, 2.27413, 3.35698", \ + "0.257606, 0.902606, 1.19002, 1.57119, 2.09646, 2.84149, 3.96722" \ ); } rise_transition (TIMING_DELAY_7x7ds1) { index_1 ("0.0186, 0.0966, 0.174, 0.3294, 0.6408, 1.263, 2.5074"); index_2 ("0.001, 0.0234, 0.039, 0.0648, 0.108, 0.18, 0.3"); values ( \ - "0.0433995, 0.323008, 0.517804, 0.839671, 1.37858, 2.27701, 3.77404", \ - "0.0564649, 0.323009, 0.517931, 0.839725, 1.37879, 2.2774, 3.77405", \ - "0.0732249, 0.327927, 0.518647, 0.839726, 1.3788, 2.27741, 3.77406", \ - "0.100161, 0.352904, 0.53159, 0.842696, 1.37881, 2.27921, 3.77407", \ - "0.143631, 0.424661, 0.591726, 0.879718, 1.39123, 2.27922, 3.77408", \ - "0.207674, 0.558606, 0.734601, 1.01026, 1.48276, 2.31763, 3.7794", \ - "0.315566, 0.78028, 0.990353, 1.29671, 1.76332, 2.5435, 3.9088" \ + "0.0434054, 0.323006, 0.51773, 0.83967, 1.37858, 2.27701, 3.77403", \ + "0.0564503, 0.323007, 0.517986, 0.839671, 1.37879, 2.27702, 3.77404", \ + "0.0732248, 0.327928, 0.518471, 0.839812, 1.3788, 2.2771, 3.77405", \ + "0.100161, 0.352904, 0.531628, 0.842276, 1.37881, 2.27919, 3.77457", \ + "0.143631, 0.42466, 0.591725, 0.879717, 1.39094, 2.2792, 3.77458", \ + "0.207674, 0.558606, 0.734601, 1.01026, 1.48305, 2.31763, 3.79414", \ + "0.315566, 0.780279, 0.990353, 1.29671, 1.76333, 2.5435, 3.90876" \ ); } cell_fall (TIMING_DELAY_7x7ds1) { index_1 ("0.0186, 0.0966, 0.174, 0.3294, 0.6408, 1.263, 2.5074"); index_2 ("0.001, 0.0234, 0.039, 0.0648, 0.108, 0.18, 0.3"); values ( \ - "0.0305188, 0.115459, 0.173147, 0.268458, 0.428006, 0.693957, 1.13752", \ - "0.0595968, 0.165365, 0.223698, 0.319085, 0.478599, 0.74512, 1.18774", \ - "0.0774045, 0.208401, 0.271689, 0.369145, 0.52876, 0.794714, 1.2388", \ - "0.103332, 0.279537, 0.355718, 0.464344, 0.629654, 0.896505, 1.33928", \ + "0.0305169, 0.115475, 0.173085, 0.268458, 0.42803, 0.693936, 1.13751", \ + "0.0596757, 0.165365, 0.223698, 0.319046, 0.478546, 0.745192, 1.18774", \ + "0.0774045, 0.208397, 0.271688, 0.369139, 0.528713, 0.794534, 1.23883", \ + "0.103332, 0.279537, 0.355718, 0.464344, 0.629614, 0.896505, 1.33928", \ "0.134872, 0.383936, 0.484892, 0.620242, 0.813272, 1.09405, 1.53891", \ - "0.173693, 0.530079, 0.674694, 0.857883, 1.10446, 1.44342, 1.93033", \ + "0.173693, 0.530079, 0.674694, 0.857884, 1.10446, 1.44342, 1.93033", \ "0.218824, 0.72482, 0.934762, 1.20208, 1.54172, 1.98866, 2.5894" \ ); } @@ -2017,12 +2017,12 @@ library (sg13g2_stdcell_slow_1p08V_125C) { index_1 ("0.0186, 0.0966, 0.174, 0.3294, 0.6408, 1.263, 2.5074"); index_2 ("0.001, 0.0234, 0.039, 0.0648, 0.108, 0.18, 0.3"); values ( \ - "0.0169732, 0.12708, 0.204717, 0.332748, 0.547368, 0.905077, 1.50135", \ - "0.0335519, 0.133852, 0.207139, 0.33301, 0.547369, 0.905667, 1.50193", \ - "0.0478566, 0.151984, 0.220435, 0.339946, 0.548999, 0.905668, 1.50221", \ - "0.0732937, 0.191455, 0.258622, 0.370334, 0.566271, 0.91122, 1.50222", \ - "0.113606, 0.266967, 0.339511, 0.45335, 0.636196, 0.95408, 1.51613", \ - "0.179086, 0.394181, 0.483502, 0.609915, 0.802444, 1.10974, 1.62729", \ + "0.0169747, 0.127076, 0.204557, 0.332742, 0.547655, 0.905152, 1.50135", \ + "0.0334937, 0.133852, 0.207132, 0.333015, 0.547774, 0.90567, 1.50193", \ + "0.0478566, 0.151985, 0.220435, 0.339908, 0.548974, 0.905671, 1.5022", \ + "0.0732937, 0.191455, 0.258622, 0.370334, 0.566278, 0.911221, 1.50221", \ + "0.113606, 0.266967, 0.339511, 0.453351, 0.636196, 0.954045, 1.51613", \ + "0.179086, 0.394181, 0.483502, 0.609332, 0.802445, 1.10974, 1.62729", \ "0.285983, 0.594596, 0.722873, 0.885502, 1.11309, 1.43708, 1.95447" \ ); } @@ -2037,12 +2037,12 @@ library (sg13g2_stdcell_slow_1p08V_125C) { index_1 ("0.0186, 0.0966, 0.174, 0.3294, 0.6408, 1.263, 2.5074"); index_2 ("0.001, 0.0234, 0.039, 0.0648, 0.108, 0.18, 0.3"); values ( \ - "0.0412852, 0.194222, 0.298135, 0.470015, 0.757475, 1.23688, 2.0355", \ - "0.0706382, 0.232953, 0.337334, 0.509381, 0.797143, 1.27656, 2.07599", \ - "0.0896817, 0.274268, 0.379137, 0.551203, 0.838698, 1.31838, 2.1171", \ - "0.116021, 0.347129, 0.460072, 0.633832, 0.921239, 1.40071, 2.19942", \ - "0.147715, 0.45722, 0.593332, 0.787224, 1.08269, 1.56118, 2.35915", \ - "0.184379, 0.610931, 0.794996, 1.03712, 1.37854, 1.88445, 2.68414", \ + "0.0412848, 0.194215, 0.298135, 0.470008, 0.757405, 1.2363, 2.03548", \ + "0.0706371, 0.232935, 0.337371, 0.509377, 0.797164, 1.27655, 2.07599", \ + "0.0896816, 0.274231, 0.379109, 0.551201, 0.838794, 1.31828, 2.11712", \ + "0.116021, 0.347129, 0.45994, 0.633832, 0.921239, 1.40071, 2.20146", \ + "0.147715, 0.45722, 0.593332, 0.787223, 1.08269, 1.56118, 2.35915", \ + "0.184379, 0.610931, 0.794995, 1.03712, 1.37854, 1.88444, 2.68389", \ "0.228873, 0.818289, 1.07278, 1.40415, 1.84778, 2.45436, 3.32555" \ ); } @@ -2050,24 +2050,24 @@ library (sg13g2_stdcell_slow_1p08V_125C) { index_1 ("0.0186, 0.0966, 0.174, 0.3294, 0.6408, 1.263, 2.5074"); index_2 ("0.001, 0.0234, 0.039, 0.0648, 0.108, 0.18, 0.3"); values ( \ - "0.031461, 0.239743, 0.384769, 0.625119, 1.02687, 1.69774, 2.81642", \ - "0.0469013, 0.240513, 0.38477, 0.62512, 1.02688, 1.69775, 2.81643", \ - "0.0636333, 0.249379, 0.388097, 0.626397, 1.02691, 1.69776, 2.81644", \ - "0.0911691, 0.281704, 0.409727, 0.634136, 1.02766, 1.69777, 2.81645", \ - "0.13315, 0.357683, 0.481465, 0.687644, 1.05507, 1.7031, 2.81646", \ - "0.196329, 0.492115, 0.629395, 0.83669, 1.17762, 1.77591, 2.83701", \ - "0.302625, 0.706549, 0.880636, 1.12499, 1.48156, 2.05172, 3.03186" \ + "0.0314609, 0.239742, 0.384769, 0.625119, 1.02686, 1.69743, 2.81642", \ + "0.0468764, 0.240295, 0.38477, 0.62512, 1.02687, 1.69765, 2.81643", \ + "0.0636333, 0.249401, 0.387916, 0.625293, 1.02702, 1.69766, 2.81644", \ + "0.0911691, 0.281704, 0.409537, 0.634134, 1.02766, 1.69767, 2.81645", \ + "0.13315, 0.357684, 0.481465, 0.687644, 1.05507, 1.70309, 2.81646", \ + "0.196328, 0.492115, 0.629395, 0.836689, 1.17762, 1.77585, 2.8365", \ + "0.302625, 0.706549, 0.880636, 1.12499, 1.48155, 2.05172, 3.03186" \ ); } cell_fall (TIMING_DELAY_7x7ds1) { index_1 ("0.0186, 0.0966, 0.174, 0.3294, 0.6408, 1.263, 2.5074"); index_2 ("0.001, 0.0234, 0.039, 0.0648, 0.108, 0.18, 0.3"); values ( \ - "0.030269, 0.115274, 0.17298, 0.268239, 0.427875, 0.693755, 1.13704", \ - "0.0591205, 0.164953, 0.223271, 0.31864, 0.478199, 0.744826, 1.1873", \ - "0.0769083, 0.207916, 0.271273, 0.36863, 0.528332, 0.793999, 1.23849", \ - "0.10307, 0.278976, 0.355181, 0.46385, 0.629305, 0.89576, 1.33881", \ - "0.13526, 0.383428, 0.484275, 0.619872, 0.812839, 1.09368, 1.53843", \ + "0.0302727, 0.115269, 0.172978, 0.268269, 0.427786, 0.693759, 1.13704", \ + "0.0591133, 0.164954, 0.223293, 0.318612, 0.4782, 0.744794, 1.18741", \ + "0.0769083, 0.207907, 0.271279, 0.36865, 0.528318, 0.793999, 1.23849", \ + "0.10307, 0.278976, 0.355202, 0.463855, 0.629351, 0.896022, 1.33877", \ + "0.13526, 0.383428, 0.484275, 0.619873, 0.812839, 1.09368, 1.53843", \ "0.175702, 0.530044, 0.674354, 0.856536, 1.10446, 1.44275, 1.92963", \ "0.225306, 0.726586, 0.935434, 1.20298, 1.54177, 1.98845, 2.58911" \ ); @@ -2076,13 +2076,13 @@ library (sg13g2_stdcell_slow_1p08V_125C) { index_1 ("0.0186, 0.0966, 0.174, 0.3294, 0.6408, 1.263, 2.5074"); index_2 ("0.001, 0.0234, 0.039, 0.0648, 0.108, 0.18, 0.3"); values ( \ - "0.0170131, 0.127065, 0.204728, 0.332894, 0.547348, 0.905066, 1.50167", \ - "0.0339147, 0.134006, 0.207201, 0.333025, 0.547349, 0.90567, 1.50168", \ - "0.0482318, 0.15233, 0.220591, 0.340017, 0.549011, 0.905671, 1.50221", \ - "0.073602, 0.19187, 0.258837, 0.370496, 0.566374, 0.910312, 1.50222", \ - "0.113351, 0.267463, 0.339993, 0.453629, 0.636404, 0.954219, 1.51551", \ - "0.177356, 0.394171, 0.483843, 0.611147, 0.802568, 1.11012, 1.62741", \ - "0.282413, 0.591669, 0.722189, 0.884203, 1.10979, 1.43853, 1.95419" \ + "0.0170171, 0.127071, 0.204728, 0.332772, 0.547394, 0.905066, 1.50188", \ + "0.0339215, 0.133998, 0.207293, 0.332979, 0.547395, 0.905666, 1.50189", \ + "0.0482318, 0.152173, 0.220523, 0.340254, 0.54899, 0.905667, 1.50221", \ + "0.073602, 0.19187, 0.259062, 0.370493, 0.566312, 0.910636, 1.50222", \ + "0.113351, 0.267463, 0.339993, 0.453629, 0.636404, 0.95422, 1.51553", \ + "0.177356, 0.394171, 0.483843, 0.611147, 0.802569, 1.11012, 1.62741", \ + "0.282413, 0.591669, 0.722189, 0.884203, 1.10979, 1.43853, 1.9542" \ ); } } @@ -2094,38 +2094,38 @@ library (sg13g2_stdcell_slow_1p08V_125C) { index_1 ("0.0186, 0.0966, 0.174, 0.3294, 0.6408, 1.263, 2.5074"); index_2 ("0.001, 0.0234, 0.039, 0.0648, 0.108, 0.18, 0.3"); values ( \ - "0.0655844, 0.274581, 0.416499, 0.65114, 1.04296, 1.69623, 2.78503", \ - "0.0966175, 0.30891, 0.451474, 0.686572, 1.07906, 1.73356, 2.82172", \ - "0.121116, 0.346766, 0.489357, 0.724461, 1.11722, 1.77098, 2.86159", \ + "0.0655825, 0.274576, 0.416499, 0.651144, 1.04296, 1.69623, 2.78502", \ + "0.0966071, 0.308944, 0.451499, 0.686572, 1.07907, 1.73355, 2.82173", \ + "0.121116, 0.346783, 0.489338, 0.724443, 1.11724, 1.77094, 2.86158", \ "0.156675, 0.419643, 0.565089, 0.799758, 1.19235, 1.84578, 2.93527", \ - "0.202241, 0.535853, 0.70025, 0.946418, 1.33951, 1.99197, 3.08251", \ - "0.257432, 0.70613, 0.914637, 1.20407, 1.63014, 2.29214, 3.37746", \ - "0.330025, 0.936553, 1.21801, 1.59502, 2.11722, 2.86114, 3.98812" \ + "0.202241, 0.535853, 0.70025, 0.946418, 1.33951, 1.99197, 3.08263", \ + "0.257432, 0.70613, 0.914637, 1.20407, 1.63014, 2.29214, 3.3774", \ + "0.330025, 0.936552, 1.21801, 1.59502, 2.11721, 2.86112, 3.98811" \ ); } rise_transition (TIMING_DELAY_7x7ds1) { index_1 ("0.0186, 0.0966, 0.174, 0.3294, 0.6408, 1.263, 2.5074"); index_2 ("0.001, 0.0234, 0.039, 0.0648, 0.108, 0.18, 0.3"); values ( \ - "0.0542766, 0.335723, 0.530834, 0.85363, 1.39329, 2.29344, 3.79401", \ - "0.0640157, 0.335724, 0.531141, 0.853631, 1.39451, 2.29479, 3.79495", \ - "0.0799126, 0.339406, 0.531477, 0.853632, 1.39452, 2.29555, 3.79525", \ - "0.10694, 0.36282, 0.544039, 0.856345, 1.39562, 2.29556, 3.79526", \ - "0.152156, 0.432921, 0.602036, 0.892021, 1.4057, 2.29659, 3.79655", \ - "0.218724, 0.565145, 0.74301, 1.02035, 1.49614, 2.33324, 3.80174", \ - "0.328766, 0.787924, 0.999426, 1.30514, 1.77655, 2.55769, 3.92717" \ + "0.0542794, 0.335724, 0.530834, 0.853629, 1.39329, 2.29344, 3.79401", \ + "0.0639523, 0.336046, 0.531168, 0.85363, 1.39451, 2.29479, 3.7949", \ + "0.0799125, 0.339403, 0.531476, 0.853631, 1.39452, 2.29555, 3.79525", \ + "0.10694, 0.36282, 0.544039, 0.856344, 1.39562, 2.29556, 3.79526", \ + "0.152156, 0.432921, 0.602035, 0.89202, 1.4057, 2.29659, 3.79669", \ + "0.218724, 0.565145, 0.74301, 1.02032, 1.49614, 2.33345, 3.8037", \ + "0.328766, 0.787926, 0.999426, 1.30514, 1.77655, 2.55859, 3.92675" \ ); } cell_fall (TIMING_DELAY_7x7ds1) { index_1 ("0.0186, 0.0966, 0.174, 0.3294, 0.6408, 1.263, 2.5074"); index_2 ("0.001, 0.0234, 0.039, 0.0648, 0.108, 0.18, 0.3"); values ( \ - "0.0307694, 0.115847, 0.173601, 0.269007, 0.428771, 0.695101, 1.1388", \ - "0.0601285, 0.165737, 0.224089, 0.319586, 0.47938, 0.746283, 1.1898", \ - "0.0781049, 0.208833, 0.272132, 0.369595, 0.52964, 0.795781, 1.24041", \ - "0.104772, 0.280158, 0.356281, 0.464952, 0.63041, 0.897352, 1.3406", \ + "0.030776, 0.115798, 0.173588, 0.269019, 0.428777, 0.695061, 1.13879", \ + "0.0601463, 0.165736, 0.224107, 0.319625, 0.479362, 0.746269, 1.18928", \ + "0.0781048, 0.208837, 0.272132, 0.369654, 0.529608, 0.795649, 1.24042", \ + "0.104772, 0.280158, 0.356281, 0.464952, 0.630416, 0.897472, 1.3406", \ "0.137504, 0.38495, 0.485836, 0.62113, 0.814213, 1.09513, 1.54057", \ - "0.177746, 0.532043, 0.67639, 0.859253, 1.10571, 1.44507, 1.93193", \ + "0.177746, 0.532043, 0.67639, 0.859253, 1.10571, 1.4449, 1.93193", \ "0.227834, 0.728491, 0.938168, 1.20519, 1.54397, 1.99101, 2.59177" \ ); } @@ -2133,13 +2133,13 @@ library (sg13g2_stdcell_slow_1p08V_125C) { index_1 ("0.0186, 0.0966, 0.174, 0.3294, 0.6408, 1.263, 2.5074"); index_2 ("0.001, 0.0234, 0.039, 0.0648, 0.108, 0.18, 0.3"); values ( \ - "0.0206747, 0.135168, 0.212557, 0.340555, 0.555137, 0.913006, 1.50943", \ - "0.0422348, 0.141941, 0.215099, 0.340743, 0.555138, 0.913544, 1.50944", \ - "0.0623299, 0.160091, 0.228363, 0.347701, 0.556698, 0.913545, 1.51009", \ - "0.0951207, 0.200748, 0.267011, 0.378147, 0.574059, 0.918411, 1.5101", \ - "0.145721, 0.278363, 0.348867, 0.461524, 0.644039, 0.962001, 1.52362", \ - "0.227721, 0.408975, 0.496195, 0.619583, 0.8115, 1.1175, 1.63497", \ - "0.359594, 0.617425, 0.739347, 0.898497, 1.12029, 1.44672, 1.96178" \ + "0.0206713, 0.135208, 0.212542, 0.340562, 0.555137, 0.912992, 1.50945", \ + "0.042207, 0.141941, 0.215085, 0.34077, 0.555138, 0.913545, 1.50946", \ + "0.0623299, 0.160096, 0.228363, 0.347759, 0.5567, 0.913546, 1.51009", \ + "0.0951207, 0.200748, 0.267011, 0.378147, 0.574097, 0.918429, 1.5101", \ + "0.145721, 0.278363, 0.348867, 0.461524, 0.64404, 0.962002, 1.52362", \ + "0.227721, 0.408975, 0.496195, 0.619583, 0.8115, 1.11716, 1.63497", \ + "0.359594, 0.617425, 0.739347, 0.898498, 1.12029, 1.44672, 1.96178" \ ); } } @@ -2149,26 +2149,26 @@ library (sg13g2_stdcell_slow_1p08V_125C) { index_1 ("0.0186, 0.0966, 0.174, 0.3294, 0.6408, 1.263, 2.5074"); index_2 ("0.001, 0.0234, 0.039, 0.0648, 0.108, 0.18, 0.3"); values ( \ - "0.00353583, 0.00366543, 0.00363802, 0.0035775, 0.00349303, 0.00332224, 0.00313742", \ - "0.00331207, 0.00357784, 0.00359495, 0.00355737, 0.00345988, 0.00334019, 0.00317522", \ - "0.00326082, 0.00350852, 0.00351571, 0.00350964, 0.00344887, 0.00331395, 0.0031976", \ - "0.00323251, 0.00341878, 0.00346848, 0.00348779, 0.00355821, 0.00341869, 0.00310695", \ - "0.00328261, 0.00334589, 0.00337141, 0.00351678, 0.00340616, 0.00322714, 0.00311003", \ - "0.0036545, 0.00346415, 0.0034519, 0.00338142, 0.00348615, 0.00324488, 0.00345224", \ - "0.0050454, 0.00405576, 0.00391439, 0.00379812, 0.00356914, 0.00340432, 0.00357264" \ + "0.00353875, 0.00366487, 0.00364026, 0.00358135, 0.00347961, 0.00332433, 0.0031373", \ + "0.00331156, 0.00356934, 0.00359495, 0.00355732, 0.00349058, 0.0033396, 0.00311403", \ + "0.00325995, 0.00350852, 0.00351784, 0.00351054, 0.00346258, 0.00332793, 0.00320022", \ + "0.0032324, 0.00341878, 0.00346847, 0.00348778, 0.00355832, 0.00330966, 0.00312536", \ + "0.00328293, 0.00333868, 0.0033714, 0.00342391, 0.00340626, 0.00322354, 0.0031057", \ + "0.00365484, 0.00346415, 0.00345213, 0.00338143, 0.00348615, 0.00324488, 0.00339553", \ + "0.00504526, 0.00405575, 0.00391482, 0.00379796, 0.00356971, 0.00340432, 0.00356938" \ ); } fall_power (POWER_7x7ds1) { index_1 ("0.0186, 0.0966, 0.174, 0.3294, 0.6408, 1.263, 2.5074"); index_2 ("0.001, 0.0234, 0.039, 0.0648, 0.108, 0.18, 0.3"); values ( \ - "0.00276115, 0.00274409, 0.00271286, 0.00266659, 0.00257548, 0.00241496, 0.00219788", \ - "0.00249204, 0.00262742, 0.0026092, 0.00258317, 0.00251048, 0.0023811, 0.00215274", \ - "0.00244092, 0.0026096, 0.00258521, 0.0025538, 0.0024879, 0.00238956, 0.00205557", \ - "0.00249346, 0.00253623, 0.00256158, 0.00250371, 0.00245146, 0.00232097, 0.00215771", \ - "0.0027425, 0.0026092, 0.00258124, 0.00252692, 0.00268205, 0.0023068, 0.0023333", \ - "0.00343391, 0.00293265, 0.00290043, 0.00280394, 0.00255427, 0.00248098, 0.00221235", \ - "0.00507797, 0.00401975, 0.00372724, 0.00344452, 0.00320583, 0.00266999, 0.00239259" \ + "0.00275626, 0.00273833, 0.0027127, 0.00266947, 0.00257523, 0.00241509, 0.00218718", \ + "0.00248855, 0.00262697, 0.00260988, 0.00257048, 0.0025102, 0.00238143, 0.00215407", \ + "0.00244025, 0.00260339, 0.00257999, 0.00256703, 0.00248712, 0.00235972, 0.00205232", \ + "0.00249351, 0.00253625, 0.00256034, 0.00250364, 0.00245146, 0.00232124, 0.00216043", \ + "0.00273629, 0.00260925, 0.00258124, 0.00252699, 0.00268205, 0.0023068, 0.00235204", \ + "0.00343396, 0.00292885, 0.00290043, 0.00280394, 0.00255437, 0.00251845, 0.00225899", \ + "0.00507831, 0.00401975, 0.00372735, 0.00344593, 0.00320589, 0.00266999, 0.00239259" \ ); } } @@ -2178,26 +2178,26 @@ library (sg13g2_stdcell_slow_1p08V_125C) { index_1 ("0.0186, 0.0966, 0.174, 0.3294, 0.6408, 1.263, 2.5074"); index_2 ("0.001, 0.0234, 0.039, 0.0648, 0.108, 0.18, 0.3"); values ( \ - "0.00373912, 0.00372081, 0.00369339, 0.00362967, 0.0035515, 0.00355025, 0.00345652", \ - "0.00359952, 0.00366782, 0.00365191, 0.00362282, 0.00353217, 0.00338366, 0.00348955", \ - "0.00355866, 0.00363983, 0.00363532, 0.00364343, 0.00351001, 0.00334824, 0.00347166", \ - "0.00353327, 0.00361085, 0.00360332, 0.00358805, 0.00352819, 0.00334668, 0.00345648", \ - "0.00356406, 0.00358062, 0.00357514, 0.00364429, 0.00346328, 0.00338248, 0.00342117", \ - "0.00385403, 0.00370193, 0.00368203, 0.00354397, 0.00364776, 0.00338495, 0.00376187", \ - "0.0050496, 0.00430524, 0.0041497, 0.00401047, 0.00376226, 0.00357566, 0.00382448" \ + "0.00373808, 0.00372559, 0.00369195, 0.00363929, 0.00355108, 0.00355159, 0.00345695", \ + "0.00359959, 0.00368111, 0.00365306, 0.00362294, 0.00352901, 0.00338379, 0.00343762", \ + "0.00355869, 0.00365224, 0.00363532, 0.00359529, 0.00351001, 0.00335066, 0.00348084", \ + "0.00353366, 0.00361083, 0.00360332, 0.00358805, 0.00355767, 0.00334591, 0.0034516", \ + "0.00356441, 0.00358062, 0.00357483, 0.00364421, 0.00346334, 0.00334971, 0.00339824", \ + "0.00385399, 0.00370152, 0.00368203, 0.00354401, 0.00364884, 0.00338788, 0.00384254", \ + "0.00504974, 0.00430498, 0.00414715, 0.00401052, 0.00379802, 0.00355652, 0.00382373" \ ); } fall_power (POWER_7x7ds1) { index_1 ("0.0186, 0.0966, 0.174, 0.3294, 0.6408, 1.263, 2.5074"); index_2 ("0.001, 0.0234, 0.039, 0.0648, 0.108, 0.18, 0.3"); values ( \ - "0.00392822, 0.00390024, 0.00386634, 0.0038145, 0.00372741, 0.00356228, 0.00334727", \ - "0.00373841, 0.0038087, 0.0037885, 0.00375915, 0.00367189, 0.00350084, 0.00328834", \ - "0.00367826, 0.00380704, 0.00376364, 0.00386328, 0.00365968, 0.00350548, 0.00322404", \ - "0.00364274, 0.00372343, 0.00374577, 0.00369074, 0.00364811, 0.00352941, 0.00334028", \ - "0.00370921, 0.00375164, 0.0037345, 0.00368569, 0.003704, 0.00356962, 0.00333345", \ - "0.00411298, 0.00388284, 0.00389373, 0.00384357, 0.00364127, 0.00365423, 0.00341308", \ - "0.00538381, 0.00460076, 0.00443802, 0.00427379, 0.00413416, 0.00370277, 0.00345083" \ + "0.0039284, 0.00389288, 0.00386254, 0.00381462, 0.00373025, 0.00356183, 0.00334455", \ + "0.00374372, 0.00380879, 0.00378581, 0.00374671, 0.00367235, 0.003501, 0.0032715", \ + "0.00367762, 0.00380729, 0.00376635, 0.00386294, 0.00366167, 0.00348837, 0.0032334", \ + "0.00364295, 0.00372347, 0.00374561, 0.00369075, 0.00364811, 0.00352941, 0.00334028", \ + "0.00371069, 0.00375179, 0.00373449, 0.00368569, 0.00370304, 0.0035595, 0.00333237", \ + "0.00411312, 0.00388227, 0.00389389, 0.00384057, 0.00363782, 0.00365418, 0.00341302", \ + "0.00538387, 0.00459367, 0.00443802, 0.00427379, 0.00413261, 0.00370267, 0.00345056" \ ); } } @@ -2208,26 +2208,26 @@ library (sg13g2_stdcell_slow_1p08V_125C) { index_1 ("0.0186, 0.0966, 0.174, 0.3294, 0.6408, 1.263, 2.5074"); index_2 ("0.001, 0.0234, 0.039, 0.0648, 0.108, 0.18, 0.3"); values ( \ - "0.00216344, 0.00234842, 0.00231633, 0.00226997, 0.00215248, 0.0021734, 0.00207107", \ - "0.00195261, 0.00217208, 0.00221189, 0.00217935, 0.00212275, 0.00200079, 0.00206137", \ - "0.00194423, 0.00211119, 0.0021275, 0.00212693, 0.00208496, 0.00197653, 0.00207016", \ - "0.0020239, 0.00205516, 0.00210695, 0.00213106, 0.0020847, 0.00190905, 0.00202487", \ - "0.00231767, 0.00217682, 0.00213286, 0.00218484, 0.00201358, 0.00191831, 0.00205943", \ - "0.00307013, 0.00252011, 0.00238571, 0.00220665, 0.00222724, 0.00187115, 0.00198655", \ - "0.0047986, 0.00360517, 0.00335073, 0.003035, 0.00267017, 0.00231095, 0.00232803" \ + "0.0021645, 0.00234819, 0.00231644, 0.00227021, 0.00215097, 0.00217331, 0.00207064", \ + "0.00195182, 0.00218669, 0.00221231, 0.00217932, 0.00212967, 0.00200053, 0.00206343", \ + "0.00194412, 0.00210628, 0.00212791, 0.00213464, 0.00208588, 0.0019759, 0.00207445", \ + "0.00202395, 0.00205516, 0.00210691, 0.00213108, 0.0020847, 0.0019089, 0.00202492", \ + "0.0023176, 0.00217682, 0.00213286, 0.00218484, 0.00201434, 0.00191831, 0.0020425", \ + "0.00307003, 0.00252174, 0.00238779, 0.00221567, 0.00222838, 0.00186397, 0.0020781", \ + "0.0047986, 0.00360587, 0.00335074, 0.00303497, 0.00267017, 0.00236053, 0.00227921" \ ); } fall_power (POWER_7x7ds1) { index_1 ("0.0186, 0.0966, 0.174, 0.3294, 0.6408, 1.263, 2.5074"); index_2 ("0.001, 0.0234, 0.039, 0.0648, 0.108, 0.18, 0.3"); values ( \ - "0.00278472, 0.00300474, 0.00298944, 0.00293255, 0.00285306, 0.00270405, 0.00247918", \ - "0.00252663, 0.00294133, 0.00294311, 0.00292472, 0.00286033, 0.00279887, 0.00254344", \ - "0.00249826, 0.00283886, 0.00291337, 0.00289007, 0.00284848, 0.00275022, 0.00258341", \ - "0.00259922, 0.00280061, 0.00281242, 0.00285843, 0.00286729, 0.00305214, 0.00243574", \ - "0.002929, 0.00280041, 0.00285743, 0.00285179, 0.00275208, 0.00289415, 0.00248178", \ - "0.0037847, 0.003151, 0.00304099, 0.00302487, 0.00297211, 0.00269015, 0.00250425", \ - "0.0056517, 0.0043219, 0.00394636, 0.00371613, 0.00340792, 0.0033162, 0.00263256" \ + "0.00278498, 0.0030082, 0.00298504, 0.00293001, 0.00285348, 0.00270619, 0.00247504", \ + "0.00252945, 0.00294132, 0.00294116, 0.00292793, 0.00288544, 0.0027993, 0.0025144", \ + "0.00249857, 0.00284402, 0.0029133, 0.00288607, 0.00284639, 0.00273722, 0.00258361", \ + "0.00259907, 0.00280061, 0.00281242, 0.00285843, 0.00290725, 0.00306119, 0.00243618", \ + "0.00292894, 0.00280042, 0.00285741, 0.00284955, 0.00275219, 0.00289415, 0.00248173", \ + "0.0037843, 0.003151, 0.00304099, 0.00302487, 0.00297211, 0.00270375, 0.00250761", \ + "0.00565163, 0.00432188, 0.00394638, 0.0037094, 0.00341079, 0.0033162, 0.00263256" \ ); } } @@ -2238,26 +2238,26 @@ library (sg13g2_stdcell_slow_1p08V_125C) { index_1 ("0.0186, 0.0966, 0.174, 0.3294, 0.6408, 1.263, 2.5074"); index_2 ("0.001, 0.0234, 0.039, 0.0648, 0.108, 0.18, 0.3"); values ( \ - "0.0018772, 0.00213609, 0.00212031, 0.00207274, 0.00197334, 0.00180121, 0.00160654", \ - "0.00169438, 0.00195666, 0.00198845, 0.0019754, 0.00192627, 0.00178068, 0.00160978", \ - "0.00171865, 0.00190529, 0.00196581, 0.00193849, 0.00186692, 0.00175555, 0.00160973", \ - "0.00182697, 0.00184106, 0.00187848, 0.00189066, 0.00183125, 0.00177421, 0.00157213", \ - "0.00217096, 0.00198154, 0.00192213, 0.00196165, 0.00179008, 0.00165314, 0.00153204", \ - "0.00300558, 0.00235239, 0.0021925, 0.00200366, 0.0020357, 0.00167566, 0.00152842", \ - "0.00484831, 0.00346702, 0.00318143, 0.00286254, 0.00243708, 0.00213887, 0.00224038" \ + "0.00187412, 0.0021383, 0.00211985, 0.00207295, 0.00197328, 0.00180131, 0.00160357", \ + "0.00169433, 0.00195537, 0.00198987, 0.00197246, 0.00192602, 0.00180789, 0.00158404", \ + "0.00171869, 0.00190527, 0.00192084, 0.00193391, 0.00186837, 0.00175556, 0.00161829", \ + "0.00182684, 0.00184101, 0.00187812, 0.00188215, 0.00183125, 0.00177394, 0.00154484", \ + "0.0021709, 0.00198153, 0.00192215, 0.00196141, 0.00186332, 0.00168528, 0.00151133", \ + "0.00300595, 0.00235255, 0.00219267, 0.00200366, 0.00197193, 0.00167545, 0.0018868", \ + "0.00484885, 0.00346702, 0.00318143, 0.00286288, 0.00243703, 0.00213881, 0.00204085" \ ); } fall_power (POWER_7x7ds1) { index_1 ("0.0186, 0.0966, 0.174, 0.3294, 0.6408, 1.263, 2.5074"); index_2 ("0.001, 0.0234, 0.039, 0.0648, 0.108, 0.18, 0.3"); values ( \ - "0.0015658, 0.00178876, 0.00177071, 0.00172059, 0.0016448, 0.00150629, 0.00125215", \ - "0.00130842, 0.00171454, 0.00172567, 0.00171612, 0.00166474, 0.00156669, 0.00128471", \ - "0.00127955, 0.00162224, 0.00169009, 0.00169075, 0.00168178, 0.00155443, 0.00137279", \ - "0.00137638, 0.00158859, 0.00159103, 0.00164043, 0.00167826, 0.00184174, 0.00127452", \ - "0.00172243, 0.00158598, 0.00164975, 0.00163554, 0.00153128, 0.00159124, 0.001202", \ - "0.00259858, 0.00195733, 0.00184427, 0.00183623, 0.00179076, 0.00146358, 0.00125891", \ - "0.00448672, 0.00314424, 0.00273282, 0.00253421, 0.00227424, 0.00211163, 0.00141428" \ + "0.00156639, 0.00178931, 0.00176231, 0.00171998, 0.00165224, 0.00149743, 0.0012299", \ + "0.00130524, 0.00171454, 0.00172628, 0.00170583, 0.00169171, 0.00158235, 0.00128455", \ + "0.00127971, 0.0016219, 0.00169007, 0.00170077, 0.00162938, 0.0015313, 0.00137022", \ + "0.00137638, 0.00158888, 0.00159103, 0.00164043, 0.00167943, 0.00184579, 0.00127447", \ + "0.00172242, 0.00158598, 0.00164975, 0.00163557, 0.00153128, 0.00166733, 0.00132936", \ + "0.00259876, 0.00195733, 0.00184426, 0.00181463, 0.00179029, 0.00146358, 0.00125891", \ + "0.00448679, 0.00314418, 0.00273284, 0.0025342, 0.00227424, 0.00211169, 0.00141325" \ ); } } @@ -2268,26 +2268,26 @@ library (sg13g2_stdcell_slow_1p08V_125C) { index_1 ("0.0186, 0.0966, 0.174, 0.3294, 0.6408, 1.263, 2.5074"); index_2 ("0.001, 0.0234, 0.039, 0.0648, 0.108, 0.18, 0.3"); values ( \ - "0.00187247, 0.00214337, 0.00211919, 0.00206943, 0.00195941, 0.00196153, 0.00188144", \ - "0.00170716, 0.00195948, 0.00198603, 0.00197779, 0.00189241, 0.00192684, 0.00184396", \ - "0.00172609, 0.00191275, 0.00196205, 0.00195908, 0.00187648, 0.00188569, 0.00182579", \ - "0.00184804, 0.00182456, 0.0019069, 0.00187587, 0.00181882, 0.00186758, 0.00180765", \ - "0.00220553, 0.00202901, 0.00191641, 0.00193876, 0.00179937, 0.00186869, 0.00175889", \ - "0.00308569, 0.00240451, 0.0022381, 0.00206826, 0.00193458, 0.00193414, 0.00184444", \ - "0.005006, 0.00352438, 0.00320347, 0.00285702, 0.00253091, 0.00206993, 0.00203629" \ + "0.00187258, 0.00214194, 0.00211904, 0.00206911, 0.00196092, 0.00197231, 0.00188174", \ + "0.00170687, 0.00197489, 0.00198256, 0.00197812, 0.00190165, 0.00192668, 0.00183666", \ + "0.00172608, 0.00192812, 0.00197359, 0.00193447, 0.00187846, 0.00181147, 0.0018263", \ + "0.00184803, 0.00182456, 0.00190835, 0.00191979, 0.00181893, 0.00186758, 0.00182673", \ + "0.0022056, 0.00202902, 0.00191643, 0.00193875, 0.00179322, 0.00186371, 0.00175824", \ + "0.0030857, 0.00240449, 0.00223811, 0.00206826, 0.00193453, 0.00194582, 0.00187312", \ + "0.00500604, 0.00352447, 0.00320347, 0.00286725, 0.00253048, 0.00214225, 0.00203673" \ ); } fall_power (POWER_7x7ds1) { index_1 ("0.0186, 0.0966, 0.174, 0.3294, 0.6408, 1.263, 2.5074"); index_2 ("0.001, 0.0234, 0.039, 0.0648, 0.108, 0.18, 0.3"); values ( \ - "0.00152331, 0.00175644, 0.00174041, 0.00169653, 0.00161089, 0.0014722, 0.00119882", \ - "0.00126153, 0.00165122, 0.00165984, 0.00164003, 0.00159949, 0.00152316, 0.00121645", \ - "0.00125141, 0.00155461, 0.0016258, 0.00161845, 0.00161436, 0.00146591, 0.00129198", \ - "0.00136322, 0.0015171, 0.00154261, 0.00157372, 0.00161615, 0.00183907, 0.00118388", \ - "0.0017519, 0.00153714, 0.00159167, 0.00156475, 0.00146649, 0.00154259, 0.00128075", \ - "0.00263422, 0.00194958, 0.00181599, 0.00184142, 0.00173433, 0.00138639, 0.0012218", \ - "0.00460125, 0.00316815, 0.00276714, 0.0025255, 0.00218909, 0.00205622, 0.00142032" \ + "0.0015233, 0.00175706, 0.00174011, 0.00168451, 0.00160863, 0.00147331, 0.00122443", \ + "0.00126128, 0.0016518, 0.0016613, 0.00165047, 0.00159831, 0.00152048, 0.00122737", \ + "0.00125142, 0.00155084, 0.00161463, 0.00162595, 0.00161308, 0.00142788, 0.00129093", \ + "0.00136339, 0.0015171, 0.00153482, 0.00156341, 0.00161598, 0.00165778, 0.0011816", \ + "0.00175156, 0.00153714, 0.00159167, 0.00156475, 0.00146649, 0.00154259, 0.00128053", \ + "0.00263394, 0.00194948, 0.00181599, 0.00184142, 0.00171506, 0.00138627, 0.0012225", \ + "0.00460117, 0.00316815, 0.00276716, 0.0025255, 0.00218908, 0.00205622, 0.00142032" \ ); } } @@ -2297,26 +2297,26 @@ library (sg13g2_stdcell_slow_1p08V_125C) { index_1 ("0.0186, 0.0966, 0.174, 0.3294, 0.6408, 1.263, 2.5074"); index_2 ("0.001, 0.0234, 0.039, 0.0648, 0.108, 0.18, 0.3"); values ( \ - "0.00187247, 0.00214337, 0.00211919, 0.00206943, 0.00195941, 0.00196153, 0.00188144", \ - "0.00170716, 0.00195948, 0.00198603, 0.00197779, 0.00189241, 0.00192684, 0.00184396", \ - "0.00172609, 0.00191275, 0.00196205, 0.00195908, 0.00187648, 0.00188569, 0.00182579", \ - "0.00184804, 0.00182456, 0.0019069, 0.00187587, 0.00181882, 0.00186758, 0.00180765", \ - "0.00220553, 0.00202901, 0.00191641, 0.00193876, 0.00179937, 0.00186869, 0.00175889", \ - "0.00308569, 0.00240451, 0.0022381, 0.00206826, 0.00193458, 0.00193414, 0.00184444", \ - "0.005006, 0.00352438, 0.00320347, 0.00285702, 0.00253091, 0.00206993, 0.00203629" \ + "0.00187258, 0.00214194, 0.00211904, 0.00206911, 0.00196092, 0.00197231, 0.00188174", \ + "0.00170687, 0.00197489, 0.00198256, 0.00197812, 0.00190165, 0.00192668, 0.00183666", \ + "0.00172608, 0.00192812, 0.00197359, 0.00193447, 0.00187846, 0.00181147, 0.0018263", \ + "0.00184803, 0.00182456, 0.00190835, 0.00191979, 0.00181893, 0.00186758, 0.00182673", \ + "0.0022056, 0.00202902, 0.00191643, 0.00193875, 0.00179322, 0.00186371, 0.00175824", \ + "0.0030857, 0.00240449, 0.00223811, 0.00206826, 0.00193453, 0.00194582, 0.00187312", \ + "0.00500604, 0.00352447, 0.00320347, 0.00286725, 0.00253048, 0.00214225, 0.00203673" \ ); } fall_power (POWER_7x7ds1) { index_1 ("0.0186, 0.0966, 0.174, 0.3294, 0.6408, 1.263, 2.5074"); index_2 ("0.001, 0.0234, 0.039, 0.0648, 0.108, 0.18, 0.3"); values ( \ - "0.0015658, 0.00178876, 0.00177071, 0.00172059, 0.0016448, 0.00150629, 0.00125215", \ - "0.00130842, 0.00171454, 0.00172567, 0.00171612, 0.00166474, 0.00156669, 0.00128471", \ - "0.00127955, 0.00162224, 0.00169009, 0.00169075, 0.00168178, 0.00155443, 0.00137279", \ - "0.00137638, 0.00158859, 0.00159103, 0.00164043, 0.00167826, 0.00184174, 0.00127452", \ - "0.00172243, 0.00158598, 0.00164975, 0.00163554, 0.00153128, 0.00159124, 0.001202", \ - "0.00259858, 0.00195733, 0.00184427, 0.00183623, 0.00179076, 0.00146358, 0.00125891", \ - "0.00448672, 0.00314424, 0.00273282, 0.00253421, 0.00227424, 0.00211163, 0.00141428" \ + "0.00156639, 0.00178931, 0.00176231, 0.00171998, 0.00165224, 0.00149743, 0.0012299", \ + "0.00130524, 0.00171454, 0.00172628, 0.00170583, 0.00169171, 0.00158235, 0.00128455", \ + "0.00127971, 0.0016219, 0.00169007, 0.00170077, 0.00162938, 0.0015313, 0.00137022", \ + "0.00137638, 0.00158888, 0.00159103, 0.00164043, 0.00167943, 0.00184579, 0.00127447", \ + "0.00172242, 0.00158598, 0.00164975, 0.00163557, 0.00153128, 0.00166733, 0.00132936", \ + "0.00259876, 0.00195733, 0.00184426, 0.00181463, 0.00179029, 0.00146358, 0.00125891", \ + "0.00448679, 0.00314418, 0.00273284, 0.0025342, 0.00227424, 0.00211169, 0.00141325" \ ); } } @@ -2325,56 +2325,56 @@ library (sg13g2_stdcell_slow_1p08V_125C) { direction : "input"; max_transition : 2.5074; capacitance : 0.0028228; - rise_capacitance : 0.00283348; - rise_capacitance_range (0.00283348, 0.00283348); - fall_capacitance : 0.00281212; - fall_capacitance_range (0.00281212, 0.00281212); + rise_capacitance : 0.00283346; + rise_capacitance_range (0.00261337, 0.00302499); + fall_capacitance : 0.00281213; + fall_capacitance_range (0.00247251, 0.003186); } pin (A2) { direction : "input"; max_transition : 2.5074; - capacitance : 0.00282847; + capacitance : 0.00282843; rise_capacitance : 0.00288079; - rise_capacitance_range (0.00288079, 0.00288079); - fall_capacitance : 0.00277614; - fall_capacitance_range (0.00277614, 0.00277614); + rise_capacitance_range (0.00256338, 0.00322426); + fall_capacitance : 0.00277608; + fall_capacitance_range (0.00252925, 0.00311833); } pin (B1) { direction : "input"; max_transition : 2.5074; - capacitance : 0.00271824; - rise_capacitance : 0.00278337; - rise_capacitance_range (0.00278337, 0.00278337); - fall_capacitance : 0.00265311; - fall_capacitance_range (0.00265311, 0.00265311); + capacitance : 0.00271819; + rise_capacitance : 0.00278329; + rise_capacitance_range (0.00227099, 0.00311794); + fall_capacitance : 0.00265308; + fall_capacitance_range (0.00236362, 0.00293124); } } cell (sg13g2_a21oi_2) { area : 14.5152; cell_footprint : "a21oi"; - cell_leakage_power : 878.054; + cell_leakage_power : 878.053; leakage_power () { - value : 361.2; + value : 361.199; when : "!A1&!A2&!B1&Y"; } leakage_power () { - value : 980.235; + value : 980.234; when : "!A1&!A2&B1&!Y"; } leakage_power () { - value : 548.965; + value : 548.964; when : "!A1&A2&!B1&Y"; } leakage_power () { - value : 976.128; + value : 976.127; when : "!A1&A2&B1&!Y"; } leakage_power () { - value : 518.959; + value : 518.958; when : "A1&!A2&!B1&Y"; } leakage_power () { - value : 976.128; + value : 976.127; when : "A1&!A2&B1&!Y"; } leakage_power () { @@ -2382,7 +2382,7 @@ library (sg13g2_stdcell_slow_1p08V_125C) { when : "A1&A2&!B1&!Y"; } leakage_power () { - value : 621.296; + value : 621.295; when : "A1&A2&B1&!Y"; } pin (Y) { @@ -2398,52 +2398,52 @@ library (sg13g2_stdcell_slow_1p08V_125C) { index_1 ("0.0186, 0.0966, 0.174, 0.3294, 0.6408, 1.263, 2.5074"); index_2 ("0.001, 0.0468, 0.078, 0.1296, 0.216, 0.36, 0.6"); values ( \ - "0.0625709, 0.274486, 0.416368, 0.651079, 1.0434, 1.69759, 2.78807", \ - "0.0945237, 0.310965, 0.453351, 0.68878, 1.08088, 1.73676, 2.82714", \ - "0.116486, 0.344148, 0.486756, 0.722022, 1.11534, 1.76977, 2.86197", \ - "0.147735, 0.405608, 0.551225, 0.786718, 1.18041, 1.83472, 2.92745", \ - "0.180992, 0.505848, 0.665334, 0.910261, 1.3059, 1.96084, 3.05413", \ - "0.209791, 0.652592, 0.848009, 1.12388, 1.5444, 2.20883, 3.30031", \ - "0.238008, 0.86086, 1.1186, 1.46477, 1.95705, 2.68121, 3.80449" \ + "0.0625888, 0.274511, 0.416447, 0.650741, 1.0434, 1.69757, 2.78804", \ + "0.0944736, 0.311011, 0.453324, 0.688754, 1.08091, 1.73675, 2.82602", \ + "0.116484, 0.344154, 0.486828, 0.722018, 1.11536, 1.76975, 2.86192", \ + "0.147735, 0.405605, 0.551219, 0.786708, 1.18041, 1.8347, 2.92604", \ + "0.180992, 0.505845, 0.66533, 0.910256, 1.30589, 1.96119, 3.05415", \ + "0.20979, 0.652588, 0.848004, 1.12388, 1.54439, 2.20881, 3.30034", \ + "0.238064, 0.860855, 1.11859, 1.46476, 1.95703, 2.68119, 3.80445" \ ); } rise_transition (TIMING_DELAY_7x7ds1) { index_1 ("0.0186, 0.0966, 0.174, 0.3294, 0.6408, 1.263, 2.5074"); index_2 ("0.001, 0.0468, 0.078, 0.1296, 0.216, 0.36, 0.6"); values ( \ - "0.0346737, 0.321803, 0.517252, 0.840522, 1.38152, 2.28332, 3.78638", \ - "0.0403504, 0.322368, 0.517793, 0.840523, 1.38153, 2.28341, 3.78639", \ - "0.049623, 0.323986, 0.517794, 0.840524, 1.38154, 2.28386, 3.78718", \ - "0.0678792, 0.338601, 0.525057, 0.842085, 1.38706, 2.28387, 3.78719", \ - "0.105897, 0.385068, 0.562498, 0.8647, 1.38912, 2.28388, 3.78832", \ - "0.174712, 0.485394, 0.663695, 0.952596, 1.4487, 2.31034, 3.8049", \ - "0.299076, 0.668262, 0.86295, 1.16129, 1.64214, 2.45921, 3.87344" \ + "0.0346795, 0.3218, 0.51717, 0.840351, 1.3815, 2.28329, 3.78633", \ + "0.0403309, 0.321985, 0.517766, 0.841319, 1.38151, 2.28338, 3.78634", \ + "0.0496235, 0.324118, 0.517767, 0.84132, 1.38152, 2.28383, 3.78714", \ + "0.0678787, 0.338645, 0.525052, 0.842304, 1.38704, 2.28384, 3.78715", \ + "0.105896, 0.385064, 0.562496, 0.864551, 1.38913, 2.28385, 3.78826", \ + "0.174712, 0.485391, 0.66369, 0.952577, 1.44848, 2.31031, 3.8111", \ + "0.299227, 0.668258, 0.862943, 1.16128, 1.64213, 2.45919, 3.8734" \ ); } cell_fall (TIMING_DELAY_7x7ds1) { index_1 ("0.0186, 0.0966, 0.174, 0.3294, 0.6408, 1.263, 2.5074"); index_2 ("0.001, 0.0468, 0.078, 0.1296, 0.216, 0.36, 0.6"); values ( \ - "0.0537784, 0.214738, 0.321279, 0.496413, 0.789529, 1.27743, 2.09034", \ - "0.0870584, 0.25663, 0.363005, 0.538452, 0.831509, 1.31961, 2.13307", \ - "0.110889, 0.298328, 0.405622, 0.580704, 0.873908, 1.3618, 2.17493", \ - "0.146501, 0.373759, 0.488919, 0.667515, 0.960283, 1.44807, 2.26176", \ - "0.194075, 0.490352, 0.62763, 0.827692, 1.13072, 1.61843, 2.4299", \ - "0.258511, 0.660168, 0.837742, 1.08348, 1.43536, 1.95623, 2.77569", \ - "0.343764, 0.890072, 1.13711, 1.46299, 1.90964, 2.52947, 3.43307" \ + "0.0537904, 0.214743, 0.321286, 0.496399, 0.78954, 1.27743, 2.09037", \ + "0.0870353, 0.256641, 0.363008, 0.538403, 0.831583, 1.31964, 2.13307", \ + "0.110881, 0.29833, 0.405671, 0.580687, 0.873929, 1.3618, 2.17495", \ + "0.146501, 0.373758, 0.488918, 0.667516, 0.960282, 1.4481, 2.26176", \ + "0.194074, 0.490352, 0.62763, 0.827691, 1.13072, 1.61843, 2.4299", \ + "0.258511, 0.660168, 0.837741, 1.08347, 1.43535, 1.95623, 2.77569", \ + "0.343764, 0.890071, 1.13711, 1.46299, 1.90964, 2.52946, 3.43307" \ ); } fall_transition (TIMING_DELAY_7x7ds1) { index_1 ("0.0186, 0.0966, 0.174, 0.3294, 0.6408, 1.263, 2.5074"); index_2 ("0.001, 0.0468, 0.078, 0.1296, 0.216, 0.36, 0.6"); values ( \ - "0.0376362, 0.244351, 0.385206, 0.616998, 1.00522, 1.65071, 2.73004", \ - "0.0498091, 0.245604, 0.385207, 0.616999, 1.00523, 1.65193, 2.73005", \ - "0.0630993, 0.255282, 0.389515, 0.621442, 1.00524, 1.65194, 2.73006", \ - "0.0882587, 0.287583, 0.413395, 0.630315, 1.00871, 1.65195, 2.73078", \ - "0.128771, 0.360357, 0.486295, 0.689479, 1.04322, 1.66231, 2.73079", \ - "0.192857, 0.492387, 0.631868, 0.840549, 1.17997, 1.75422, 2.76721", \ - "0.295415, 0.706627, 0.88005, 1.12256, 1.47784, 2.04508, 2.9916" \ + "0.037638, 0.24459, 0.385206, 0.616552, 1.00522, 1.65071, 2.72991", \ + "0.0498167, 0.2456, 0.385207, 0.616553, 1.00523, 1.65077, 2.72992", \ + "0.0631285, 0.255332, 0.389517, 0.62144, 1.00524, 1.65184, 2.72993", \ + "0.0882586, 0.287582, 0.413394, 0.630322, 1.00793, 1.65185, 2.73078", \ + "0.128771, 0.360358, 0.486296, 0.689479, 1.04322, 1.6623, 2.73547", \ + "0.192857, 0.492388, 0.631867, 0.840547, 1.17996, 1.75421, 2.7672", \ + "0.295415, 0.706626, 0.880049, 1.12256, 1.47784, 2.04508, 2.99159" \ ); } } @@ -2455,52 +2455,52 @@ library (sg13g2_stdcell_slow_1p08V_125C) { index_1 ("0.0186, 0.0966, 0.174, 0.3294, 0.6408, 1.263, 2.5074"); index_2 ("0.001, 0.0468, 0.078, 0.1296, 0.216, 0.36, 0.6"); values ( \ - "0.0745315, 0.285665, 0.427495, 0.661649, 1.05367, 1.70658, 2.79488", \ - "0.108765, 0.32281, 0.464747, 0.699559, 1.09129, 1.74456, 2.83257", \ - "0.133808, 0.356576, 0.498666, 0.733177, 1.12567, 1.77904, 2.8685", \ - "0.170715, 0.419298, 0.563769, 0.798544, 1.19114, 1.84411, 2.93282", \ - "0.215843, 0.522139, 0.679726, 0.923206, 1.31732, 1.97078, 3.06064", \ - "0.262325, 0.674087, 0.86597, 1.13921, 1.55754, 2.21944, 3.30877", \ - "0.314463, 0.891085, 1.14265, 1.48446, 1.97321, 2.69392, 3.81448" \ + "0.0745109, 0.285673, 0.427502, 0.661767, 1.05366, 1.70654, 2.7948", \ + "0.108731, 0.322826, 0.464802, 0.699534, 1.09124, 1.74553, 2.83294", \ + "0.133777, 0.356545, 0.498687, 0.733348, 1.12568, 1.77901, 2.86845", \ + "0.170714, 0.419295, 0.563765, 0.798542, 1.19113, 1.84409, 2.93278", \ + "0.215841, 0.522136, 0.679722, 0.923218, 1.31745, 1.97077, 3.05913", \ + "0.262324, 0.674083, 0.865964, 1.1392, 1.55753, 2.21952, 3.30852", \ + "0.314462, 0.891081, 1.14264, 1.48445, 1.9732, 2.69438, 3.81446" \ ); } rise_transition (TIMING_DELAY_7x7ds1) { index_1 ("0.0186, 0.0966, 0.174, 0.3294, 0.6408, 1.263, 2.5074"); index_2 ("0.001, 0.0468, 0.078, 0.1296, 0.216, 0.36, 0.6"); values ( \ - "0.0456333, 0.333573, 0.52872, 0.851853, 1.3922, 2.29103, 3.79136", \ - "0.0499823, 0.33372, 0.528721, 0.851854, 1.39221, 2.29276, 3.79137", \ - "0.058685, 0.335413, 0.528722, 0.852226, 1.39222, 2.29277, 3.79328", \ - "0.0762736, 0.349015, 0.536155, 0.853359, 1.3937, 2.29289, 3.79329", \ - "0.113434, 0.394967, 0.572667, 0.875039, 1.39895, 2.2929, 3.79469", \ - "0.180533, 0.49202, 0.67253, 0.961588, 1.45766, 2.31853, 3.81761", \ - "0.296077, 0.676047, 0.867767, 1.16785, 1.65024, 2.4671, 3.87754" \ + "0.0456491, 0.333566, 0.528714, 0.85145, 1.39218, 2.291, 3.79131", \ + "0.0499669, 0.33459, 0.528715, 0.851747, 1.39219, 2.29186, 3.79234", \ + "0.0586067, 0.335505, 0.529004, 0.85206, 1.3922, 2.29187, 3.79322", \ + "0.076273, 0.349011, 0.536151, 0.853257, 1.39368, 2.29285, 3.79323", \ + "0.113434, 0.394963, 0.572641, 0.874939, 1.39923, 2.29286, 3.79324", \ + "0.180533, 0.492016, 0.672524, 0.961579, 1.45764, 2.3182, 3.81282", \ + "0.296076, 0.676043, 0.867761, 1.1678, 1.65021, 2.46761, 3.87877" \ ); } cell_fall (TIMING_DELAY_7x7ds1) { index_1 ("0.0186, 0.0966, 0.174, 0.3294, 0.6408, 1.263, 2.5074"); index_2 ("0.001, 0.0468, 0.078, 0.1296, 0.216, 0.36, 0.6"); values ( \ - "0.0609476, 0.221727, 0.328007, 0.503282, 0.796309, 1.28424, 2.09722", \ - "0.0958097, 0.262107, 0.368596, 0.544089, 0.837031, 1.3251, 2.13822", \ - "0.121494, 0.300111, 0.407402, 0.582938, 0.876108, 1.36416, 2.17722", \ - "0.161243, 0.369843, 0.482998, 0.661483, 0.955288, 1.44355, 2.25746", \ - "0.213797, 0.482087, 0.611988, 0.806278, 1.10874, 1.59867, 2.4117", \ - "0.283424, 0.653608, 0.816519, 1.0474, 1.38516, 1.90145, 2.72268", \ - "0.37863, 0.895382, 1.12252, 1.42328, 1.8359, 2.4282, 3.31311" \ + "0.0609442, 0.221712, 0.328002, 0.503417, 0.796303, 1.28423, 2.09716", \ + "0.0958269, 0.262167, 0.368653, 0.544184, 0.837034, 1.32507, 2.13817", \ + "0.121471, 0.300082, 0.407423, 0.582942, 0.876125, 1.36414, 2.17724", \ + "0.161243, 0.369843, 0.482997, 0.661481, 0.955286, 1.44354, 2.25749", \ + "0.213797, 0.482087, 0.611987, 0.806277, 1.10873, 1.59859, 2.41171", \ + "0.283424, 0.653607, 0.816518, 1.0474, 1.38516, 1.90144, 2.7227", \ + "0.37863, 0.895382, 1.12252, 1.42328, 1.8359, 2.42819, 3.3131" \ ); } fall_transition (TIMING_DELAY_7x7ds1) { index_1 ("0.0186, 0.0966, 0.174, 0.3294, 0.6408, 1.263, 2.5074"); index_2 ("0.001, 0.0468, 0.078, 0.1296, 0.216, 0.36, 0.6"); values ( \ - "0.0374951, 0.244496, 0.384706, 0.617008, 1.00433, 1.65193, 2.73", \ - "0.0442276, 0.245069, 0.384707, 0.61702, 1.00518, 1.65194, 2.73001", \ - "0.0534955, 0.251303, 0.387378, 0.621386, 1.00519, 1.65201, 2.73002", \ - "0.0730568, 0.272567, 0.403343, 0.626162, 1.00669, 1.65202, 2.7309", \ - "0.10915, 0.325515, 0.453938, 0.665706, 1.03026, 1.65937, 2.73245", \ - "0.171904, 0.430137, 0.562926, 0.77277, 1.12522, 1.72162, 2.75682", \ - "0.274491, 0.615613, 0.770031, 0.995829, 1.34538, 1.92882, 2.90966" \ + "0.0375192, 0.244495, 0.384706, 0.616419, 1.0041, 1.65122, 2.72945", \ + "0.0442285, 0.245067, 0.384707, 0.617081, 1.00518, 1.65123, 2.72946", \ + "0.0535138, 0.251288, 0.387867, 0.621386, 1.00519, 1.65197, 2.72947", \ + "0.0730567, 0.272566, 0.403342, 0.626161, 1.0067, 1.65198, 2.73094", \ + "0.10915, 0.325514, 0.453937, 0.6657, 1.03017, 1.65736, 2.73146", \ + "0.171904, 0.430136, 0.562924, 0.77277, 1.12547, 1.72161, 2.75701", \ + "0.274491, 0.615612, 0.77003, 0.995827, 1.34538, 1.92882, 2.9097" \ ); } } @@ -2514,52 +2514,52 @@ library (sg13g2_stdcell_slow_1p08V_125C) { index_1 ("0.0186, 0.0966, 0.174, 0.3294, 0.6408, 1.263, 2.5074"); index_2 ("0.001, 0.0468, 0.078, 0.1296, 0.216, 0.36, 0.6"); values ( \ - "0.0589572, 0.273303, 0.415247, 0.649717, 1.04138, 1.69436, 2.78265", \ - "0.0892376, 0.307733, 0.450241, 0.685289, 1.07751, 1.73174, 2.81903", \ - "0.111935, 0.345631, 0.488109, 0.722782, 1.11534, 1.76915, 2.85919", \ - "0.144774, 0.41833, 0.56379, 0.798397, 1.19061, 1.84804, 2.93287", \ - "0.186067, 0.534343, 0.698819, 0.945033, 1.33803, 1.99023, 3.08028", \ - "0.23607, 0.704135, 0.912903, 1.20265, 1.62853, 2.29027, 3.37483", \ - "0.301298, 0.934005, 1.21578, 1.59293, 2.11522, 2.85865, 3.9854" \ + "0.0589485, 0.273325, 0.415249, 0.649742, 1.04139, 1.69437, 2.78264", \ + "0.0891804, 0.307737, 0.450263, 0.685248, 1.07748, 1.73173, 2.81902", \ + "0.111959, 0.345661, 0.488124, 0.722949, 1.1158, 1.76912, 2.85827", \ + "0.144775, 0.418305, 0.563787, 0.798371, 1.19062, 1.84382, 2.93282", \ + "0.186066, 0.534341, 0.698815, 0.945014, 1.338, 1.99019, 3.07877", \ + "0.236069, 0.704132, 0.912899, 1.20264, 1.62851, 2.29025, 3.37486", \ + "0.301296, 0.934001, 1.21578, 1.59292, 2.11521, 2.85849, 3.98537" \ ); } rise_transition (TIMING_DELAY_7x7ds1) { index_1 ("0.0186, 0.0966, 0.174, 0.3294, 0.6408, 1.263, 2.5074"); index_2 ("0.001, 0.0468, 0.078, 0.1296, 0.216, 0.36, 0.6"); values ( \ - "0.045707, 0.333621, 0.528706, 0.85146, 1.39121, 2.29105, 3.79135", \ - "0.0559809, 0.334079, 0.529283, 0.851461, 1.3923, 2.29237, 3.79196", \ - "0.0711533, 0.337323, 0.529284, 0.852059, 1.39231, 2.29312, 3.79256", \ - "0.0962716, 0.360961, 0.541347, 0.854186, 1.39232, 2.29548, 3.79257", \ - "0.13834, 0.430916, 0.599758, 0.889769, 1.40354, 2.29549, 3.79392", \ - "0.200309, 0.562641, 0.741401, 1.0181, 1.49392, 2.33197, 3.80096", \ - "0.303797, 0.786802, 0.996301, 1.30384, 1.77298, 2.55563, 3.92443" \ + "0.0457091, 0.333616, 0.52865, 0.851451, 1.391, 2.29136, 3.79131", \ + "0.0559979, 0.334084, 0.529281, 0.851452, 1.39228, 2.29234, 3.79192", \ + "0.0711318, 0.337406, 0.529393, 0.851971, 1.39229, 2.2931, 3.79193", \ + "0.0962536, 0.360915, 0.541489, 0.854252, 1.39369, 2.29311, 3.79247", \ + "0.13834, 0.430913, 0.599752, 0.889747, 1.40394, 2.29326, 3.79248", \ + "0.200308, 0.562643, 0.741396, 1.0181, 1.4939, 2.33208, 3.80715", \ + "0.303797, 0.786799, 0.996019, 1.30384, 1.77297, 2.55561, 3.92438" \ ); } cell_fall (TIMING_DELAY_7x7ds1) { index_1 ("0.0186, 0.0966, 0.174, 0.3294, 0.6408, 1.263, 2.5074"); index_2 ("0.001, 0.0468, 0.078, 0.1296, 0.216, 0.36, 0.6"); values ( \ - "0.0274385, 0.114985, 0.172681, 0.267905, 0.427457, 0.693373, 1.13645", \ - "0.0539808, 0.16482, 0.223172, 0.318464, 0.478027, 0.744661, 1.18708", \ - "0.0700525, 0.207698, 0.271175, 0.368508, 0.52823, 0.793928, 1.23806", \ - "0.0929408, 0.278232, 0.354368, 0.463671, 0.629002, 0.895379, 1.33799", \ - "0.120755, 0.383278, 0.484274, 0.619904, 0.812843, 1.09345, 1.53826", \ - "0.154627, 0.529779, 0.674179, 0.857486, 1.10426, 1.44303, 1.92964", \ - "0.195042, 0.725127, 0.934739, 1.2028, 1.54189, 1.9889, 2.58923" \ + "0.0274363, 0.114927, 0.172651, 0.267928, 0.427466, 0.693393, 1.13652", \ + "0.0539977, 0.164859, 0.223161, 0.318463, 0.478014, 0.74466, 1.18705", \ + "0.0699873, 0.207712, 0.271194, 0.368559, 0.528267, 0.794015, 1.23813", \ + "0.0929416, 0.278236, 0.354375, 0.463721, 0.629014, 0.895425, 1.338", \ + "0.120756, 0.383283, 0.484285, 0.619915, 0.812918, 1.09348, 1.53822", \ + "0.154629, 0.529785, 0.674188, 0.857497, 1.10432, 1.44306, 1.92982", \ + "0.195045, 0.725098, 0.934749, 1.20282, 1.54191, 1.98894, 2.58927" \ ); } fall_transition (TIMING_DELAY_7x7ds1) { index_1 ("0.0186, 0.0966, 0.174, 0.3294, 0.6408, 1.263, 2.5074"); index_2 ("0.001, 0.0468, 0.078, 0.1296, 0.216, 0.36, 0.6"); values ( \ - "0.0169748, 0.134488, 0.211827, 0.339662, 0.554021, 0.911501, 1.50742", \ - "0.0397399, 0.141382, 0.21439, 0.339868, 0.554022, 0.912042, 1.50743", \ - "0.0599578, 0.159674, 0.227734, 0.346898, 0.555581, 0.912043, 1.50843", \ - "0.0926357, 0.200902, 0.266924, 0.377504, 0.573067, 0.916654, 1.50844", \ - "0.142594, 0.278045, 0.348385, 0.460772, 0.64304, 0.960297, 1.52187", \ - "0.223031, 0.408423, 0.495701, 0.618915, 0.810582, 1.11642, 1.6329", \ - "0.352365, 0.616506, 0.739097, 0.897969, 1.11969, 1.44546, 1.96029" \ + "0.016968, 0.13448, 0.211803, 0.339668, 0.554044, 0.911538, 1.50759", \ + "0.0397301, 0.141367, 0.214396, 0.339877, 0.554045, 0.91208, 1.5076", \ + "0.0600405, 0.1597, 0.227726, 0.346891, 0.5556, 0.912081, 1.50849", \ + "0.0926366, 0.200906, 0.26693, 0.377502, 0.573099, 0.916708, 1.5085", \ + "0.142595, 0.278051, 0.348358, 0.460789, 0.643148, 0.960267, 1.52194", \ + "0.223032, 0.408429, 0.49571, 0.618928, 0.810581, 1.11645, 1.63334", \ + "0.352366, 0.616469, 0.739106, 0.897981, 1.11971, 1.44549, 1.9606" \ ); } } @@ -2573,52 +2573,52 @@ library (sg13g2_stdcell_slow_1p08V_125C) { index_1 ("0.0186, 0.0966, 0.174, 0.3294, 0.6408, 1.263, 2.5074"); index_2 ("0.001, 0.0468, 0.078, 0.1296, 0.216, 0.36, 0.6"); values ( \ - "0.0446293, 0.258916, 0.400817, 0.63544, 1.02785, 1.68206, 2.77262", \ - "0.0713382, 0.293213, 0.435721, 0.671053, 1.06402, 1.71951, 2.80905", \ - "0.0886647, 0.331033, 0.47361, 0.708699, 1.10224, 1.7569, 2.84924", \ - "0.11267, 0.40276, 0.549213, 0.78429, 1.17739, 1.83261, 2.92285", \ - "0.141901, 0.515799, 0.682735, 0.930513, 1.32454, 1.97787, 3.07004", \ - "0.176662, 0.679667, 0.892958, 1.18625, 1.61439, 2.27814, 3.36503", \ - "0.221339, 0.900263, 1.18918, 1.57162, 2.09835, 2.84571, 3.9751" \ + "0.0446332, 0.258939, 0.400818, 0.635437, 1.02784, 1.68208, 2.77258", \ + "0.0713178, 0.293126, 0.435825, 0.67103, 1.06402, 1.71951, 2.80893", \ + "0.0886252, 0.331031, 0.473668, 0.708946, 1.10221, 1.75684, 2.84929", \ + "0.112669, 0.402755, 0.549212, 0.784296, 1.17696, 1.83584, 2.92282", \ + "0.141901, 0.515796, 0.682731, 0.930506, 1.32453, 1.9777, 3.0701", \ + "0.176661, 0.679663, 0.892954, 1.18624, 1.61438, 2.27809, 3.36492", \ + "0.221337, 0.900259, 1.18917, 1.57134, 2.09834, 2.84569, 3.97503" \ ); } rise_transition (TIMING_DELAY_7x7ds1) { index_1 ("0.0186, 0.0966, 0.174, 0.3294, 0.6408, 1.263, 2.5074"); index_2 ("0.001, 0.0468, 0.078, 0.1296, 0.216, 0.36, 0.6"); values ( \ - "0.0346797, 0.321765, 0.517232, 0.840416, 1.38148, 2.28332, 3.78638", \ - "0.0485852, 0.321766, 0.517493, 0.840417, 1.38168, 2.28359, 3.78639", \ - "0.0642678, 0.326619, 0.517979, 0.840466, 1.38169, 2.28367, 3.78683", \ - "0.0898887, 0.35187, 0.53118, 0.843694, 1.3817, 2.28368, 3.78688", \ - "0.128602, 0.423562, 0.591566, 0.880451, 1.39391, 2.28496, 3.78802", \ - "0.187534, 0.557201, 0.734123, 1.01089, 1.48571, 2.3239, 3.80733", \ - "0.288494, 0.776279, 0.989386, 1.2973, 1.76609, 2.54998, 3.92019" \ + "0.0346807, 0.321755, 0.517226, 0.840406, 1.38146, 2.28329, 3.78633", \ + "0.0485683, 0.321756, 0.517227, 0.840534, 1.38166, 2.2833, 3.78634", \ + "0.0642877, 0.326622, 0.517831, 0.840535, 1.38167, 2.28364, 3.78679", \ + "0.0898883, 0.351867, 0.531182, 0.843658, 1.38193, 2.28707, 3.78684", \ + "0.128602, 0.423558, 0.591561, 0.880442, 1.3939, 2.28708, 3.78808", \ + "0.187533, 0.557198, 0.734118, 1.01088, 1.48569, 2.32387, 3.7972", \ + "0.288494, 0.776276, 0.989381, 1.29706, 1.76608, 2.54994, 3.92007" \ ); } cell_fall (TIMING_DELAY_7x7ds1) { index_1 ("0.0186, 0.0966, 0.174, 0.3294, 0.6408, 1.263, 2.5074"); index_2 ("0.001, 0.0468, 0.078, 0.1296, 0.216, 0.36, 0.6"); values ( \ - "0.0271778, 0.114601, 0.172258, 0.267385, 0.426726, 0.69227, 1.13502", \ - "0.0534436, 0.164484, 0.222791, 0.317943, 0.477127, 0.743567, 1.18564", \ - "0.0691604, 0.207493, 0.270755, 0.368009, 0.527386, 0.792865, 1.2366", \ - "0.0913721, 0.277635, 0.353753, 0.463057, 0.628267, 0.894342, 1.33656", \ - "0.117862, 0.382275, 0.483407, 0.618964, 0.811795, 1.09235, 1.53662", \ - "0.149763, 0.52782, 0.67259, 0.856078, 1.10307, 1.44154, 1.92799", \ - "0.185182, 0.721491, 0.931782, 1.19996, 1.53945, 1.98696, 2.58684" \ + "0.027183, 0.11462, 0.17224, 0.267398, 0.426695, 0.692284, 1.13511", \ + "0.0534462, 0.164502, 0.222729, 0.317956, 0.477188, 0.743559, 1.18555", \ + "0.0691591, 0.207497, 0.270757, 0.368006, 0.527496, 0.792891, 1.23562", \ + "0.0913729, 0.27764, 0.35376, 0.463068, 0.628312, 0.894359, 1.33669", \ + "0.117863, 0.38228, 0.483414, 0.618967, 0.811847, 1.09239, 1.53666", \ + "0.149765, 0.527826, 0.672599, 0.85609, 1.10308, 1.44157, 1.928", \ + "0.185184, 0.721498, 0.931792, 1.19997, 1.53947, 1.98699, 2.58688" \ ); } fall_transition (TIMING_DELAY_7x7ds1) { index_1 ("0.0186, 0.0966, 0.174, 0.3294, 0.6408, 1.263, 2.5074"); index_2 ("0.001, 0.0468, 0.078, 0.1296, 0.216, 0.36, 0.6"); values ( \ - "0.0137459, 0.125984, 0.203435, 0.331444, 0.545861, 0.903126, 1.49973", \ - "0.0297102, 0.132882, 0.205999, 0.33185, 0.54626, 0.903731, 1.49974", \ - "0.0431378, 0.150991, 0.219362, 0.338725, 0.547496, 0.903917, 1.49975", \ - "0.0674458, 0.191057, 0.258066, 0.369268, 0.564915, 0.908723, 1.49976", \ - "0.104703, 0.265862, 0.338211, 0.452184, 0.634794, 0.952399, 1.51289", \ - "0.165252, 0.392669, 0.482186, 0.608422, 0.801539, 1.10844, 1.62496", \ - "0.265969, 0.592316, 0.721968, 0.883489, 1.10851, 1.4355, 1.95174" \ + "0.0137449, 0.125985, 0.203449, 0.331459, 0.545837, 0.903164, 1.49862", \ + "0.0297009, 0.132887, 0.206018, 0.33172, 0.545959, 0.90377, 1.49871", \ + "0.0431406, 0.150996, 0.219331, 0.338716, 0.547475, 0.903942, 1.49872", \ + "0.0674464, 0.191061, 0.258073, 0.369246, 0.565064, 0.908759, 1.49873", \ + "0.104703, 0.265867, 0.338224, 0.451884, 0.634884, 0.952464, 1.51295", \ + "0.165253, 0.392674, 0.482194, 0.608433, 0.801562, 1.10845, 1.62502", \ + "0.26597, 0.592322, 0.721978, 0.883502, 1.10853, 1.43554, 1.95179" \ ); } } @@ -2632,52 +2632,52 @@ library (sg13g2_stdcell_slow_1p08V_125C) { index_1 ("0.0186, 0.0966, 0.174, 0.3294, 0.6408, 1.263, 2.5074"); index_2 ("0.001, 0.0468, 0.078, 0.1296, 0.216, 0.36, 0.6"); values ( \ - "0.0361709, 0.193352, 0.297483, 0.469574, 0.757681, 1.23758, 2.03827", \ - "0.0631035, 0.232114, 0.336658, 0.509029, 0.797331, 1.27767, 2.07796", \ - "0.0794648, 0.27324, 0.378215, 0.550712, 0.838924, 1.31923, 2.1199", \ - "0.101892, 0.346105, 0.459105, 0.633447, 0.921423, 1.40158, 2.20389", \ - "0.128524, 0.456053, 0.592452, 0.786734, 1.08276, 1.56213, 2.3617", \ - "0.158621, 0.608987, 0.793666, 1.03682, 1.37853, 1.88537, 2.68658", \ - "0.19401, 0.815129, 1.07084, 1.40263, 1.84729, 2.45501, 3.32778" \ + "0.0361324, 0.19338, 0.297465, 0.469668, 0.757539, 1.23792, 2.03801", \ + "0.0631341, 0.232137, 0.336686, 0.509033, 0.797295, 1.2776, 2.07792", \ + "0.0794659, 0.273174, 0.378195, 0.550554, 0.839091, 1.31939, 2.11974", \ + "0.101891, 0.34614, 0.459098, 0.633407, 0.921439, 1.40137, 2.20386", \ + "0.128523, 0.45605, 0.592448, 0.786728, 1.08275, 1.56211, 2.36162", \ + "0.15862, 0.608983, 0.793662, 1.03682, 1.37852, 1.88534, 2.68655", \ + "0.194008, 0.815218, 1.07084, 1.40262, 1.84728, 2.45499, 3.32775" \ ); } rise_transition (TIMING_DELAY_7x7ds1) { index_1 ("0.0186, 0.0966, 0.174, 0.3294, 0.6408, 1.263, 2.5074"); index_2 ("0.001, 0.0468, 0.078, 0.1296, 0.216, 0.36, 0.6"); values ( \ - "0.0250264, 0.238376, 0.383743, 0.624699, 1.02719, 1.69962, 2.81875", \ - "0.0406099, 0.238975, 0.383744, 0.6247, 1.0272, 1.69963, 2.81933", \ - "0.0567165, 0.248146, 0.387115, 0.624729, 1.02743, 1.69964, 2.81934", \ - "0.0818686, 0.2807, 0.408669, 0.633934, 1.02807, 1.69965, 2.82141", \ - "0.119985, 0.356239, 0.480521, 0.687589, 1.05568, 1.70512, 2.82142", \ - "0.17806, 0.490786, 0.627975, 0.835937, 1.17801, 1.77809, 2.84048", \ - "0.277426, 0.701917, 0.879139, 1.12513, 1.48339, 2.05403, 3.03611" \ + "0.0250104, 0.238365, 0.383731, 0.624642, 1.02774, 1.69969, 2.82086", \ + "0.0405831, 0.238964, 0.383733, 0.624643, 1.02775, 1.6997, 2.82087", \ + "0.0567146, 0.248157, 0.387239, 0.624644, 1.02776, 1.69971, 2.82088", \ + "0.0818683, 0.280547, 0.408674, 0.633959, 1.02812, 1.70104, 2.82136", \ + "0.119985, 0.356237, 0.480516, 0.687585, 1.05595, 1.7051, 2.82137", \ + "0.17806, 0.490783, 0.62797, 0.835929, 1.178, 1.77802, 2.84044", \ + "0.277426, 0.704589, 0.879133, 1.12512, 1.48338, 2.05401, 3.03606" \ ); } cell_fall (TIMING_DELAY_7x7ds1) { index_1 ("0.0186, 0.0966, 0.174, 0.3294, 0.6408, 1.263, 2.5074"); index_2 ("0.001, 0.0468, 0.078, 0.1296, 0.216, 0.36, 0.6"); values ( \ - "0.0269269, 0.114413, 0.172066, 0.267188, 0.426476, 0.692063, 1.13459", \ - "0.0529818, 0.164056, 0.222373, 0.317568, 0.4769, 0.743175, 1.18502", \ - "0.0687152, 0.206935, 0.270295, 0.367512, 0.526941, 0.792515, 1.23627", \ - "0.0911795, 0.277071, 0.354033, 0.46258, 0.627898, 0.893949, 1.33618", \ - "0.118377, 0.38177, 0.482801, 0.618504, 0.811515, 1.09194, 1.53624", \ - "0.152185, 0.527669, 0.672358, 0.854746, 1.10257, 1.4411, 1.92727", \ - "0.192581, 0.72313, 0.93259, 1.20044, 1.5395, 1.98669, 2.58672" \ + "0.0269241, 0.114403, 0.172064, 0.267199, 0.426501, 0.692109, 1.13486", \ + "0.0529848, 0.164101, 0.222323, 0.317518, 0.476883, 0.743223, 1.18512", \ + "0.0687186, 0.206934, 0.27032, 0.367538, 0.526945, 0.792469, 1.23633", \ + "0.0911621, 0.277033, 0.354043, 0.46259, 0.627936, 0.893976, 1.33622", \ + "0.118378, 0.381775, 0.482808, 0.618514, 0.811531, 1.09206, 1.5363", \ + "0.152186, 0.527675, 0.672366, 0.854758, 1.10258, 1.44113, 1.92732", \ + "0.192582, 0.723137, 0.9326, 1.20046, 1.53952, 1.98686, 2.58678" \ ); } fall_transition (TIMING_DELAY_7x7ds1) { index_1 ("0.0186, 0.0966, 0.174, 0.3294, 0.6408, 1.263, 2.5074"); index_2 ("0.001, 0.0468, 0.078, 0.1296, 0.216, 0.36, 0.6"); values ( \ - "0.0137951, 0.125984, 0.20345, 0.331421, 0.545825, 0.903144, 1.49866", \ - "0.0300958, 0.132977, 0.206194, 0.331728, 0.545826, 0.903754, 1.49936", \ - "0.0436099, 0.15112, 0.219664, 0.338825, 0.547729, 0.903977, 1.49967", \ - "0.0676899, 0.191475, 0.257916, 0.369492, 0.56496, 0.908793, 1.49968", \ - "0.10434, 0.265968, 0.338915, 0.452537, 0.635453, 0.952429, 1.51303", \ - "0.163713, 0.392835, 0.4827, 0.609305, 0.801723, 1.10792, 1.62534", \ - "0.262399, 0.59036, 0.721125, 0.883331, 1.10848, 1.4352, 1.95208" \ + "0.0137972, 0.125998, 0.203539, 0.331436, 0.545848, 0.903181, 1.49863", \ + "0.0301029, 0.132969, 0.206187, 0.331707, 0.545849, 0.90379, 1.49867", \ + "0.0436066, 0.151127, 0.219523, 0.338825, 0.547507, 0.904518, 1.49973", \ + "0.0676838, 0.191359, 0.257922, 0.369503, 0.565281, 0.908831, 1.49974", \ + "0.10434, 0.265973, 0.338924, 0.452549, 0.635462, 0.952559, 1.51392", \ + "0.163713, 0.392841, 0.482707, 0.609311, 0.801743, 1.10782, 1.62539", \ + "0.262401, 0.590367, 0.721133, 0.883344, 1.1085, 1.43536, 1.9522" \ ); } } @@ -2689,52 +2689,52 @@ library (sg13g2_stdcell_slow_1p08V_125C) { index_1 ("0.0186, 0.0966, 0.174, 0.3294, 0.6408, 1.263, 2.5074"); index_2 ("0.001, 0.0468, 0.078, 0.1296, 0.216, 0.36, 0.6"); values ( \ - "0.0589572, 0.273303, 0.415247, 0.649717, 1.04138, 1.69436, 2.78265", \ - "0.0892376, 0.307733, 0.450241, 0.685289, 1.07751, 1.73174, 2.81903", \ - "0.111935, 0.345631, 0.488109, 0.722782, 1.11534, 1.76915, 2.85919", \ - "0.144774, 0.41833, 0.56379, 0.798397, 1.19061, 1.84804, 2.93287", \ - "0.186067, 0.534343, 0.698819, 0.945033, 1.33803, 1.99023, 3.08028", \ - "0.23607, 0.704135, 0.912903, 1.20265, 1.62853, 2.29027, 3.37483", \ - "0.301298, 0.934005, 1.21578, 1.59293, 2.11522, 2.85865, 3.9854" \ + "0.0589485, 0.273325, 0.415249, 0.649742, 1.04139, 1.69437, 2.78264", \ + "0.0891804, 0.307737, 0.450263, 0.685248, 1.07748, 1.73173, 2.81902", \ + "0.111959, 0.345661, 0.488124, 0.722949, 1.1158, 1.76912, 2.85827", \ + "0.144775, 0.418305, 0.563787, 0.798371, 1.19062, 1.84382, 2.93282", \ + "0.186066, 0.534341, 0.698815, 0.945014, 1.338, 1.99019, 3.07877", \ + "0.236069, 0.704132, 0.912899, 1.20264, 1.62851, 2.29025, 3.37486", \ + "0.301296, 0.934001, 1.21578, 1.59292, 2.11521, 2.85849, 3.98537" \ ); } rise_transition (TIMING_DELAY_7x7ds1) { index_1 ("0.0186, 0.0966, 0.174, 0.3294, 0.6408, 1.263, 2.5074"); index_2 ("0.001, 0.0468, 0.078, 0.1296, 0.216, 0.36, 0.6"); values ( \ - "0.045707, 0.333621, 0.528706, 0.85146, 1.39121, 2.29105, 3.79135", \ - "0.0559809, 0.334079, 0.529283, 0.851461, 1.3923, 2.29237, 3.79196", \ - "0.0711533, 0.337323, 0.529284, 0.852059, 1.39231, 2.29312, 3.79256", \ - "0.0962716, 0.360961, 0.541347, 0.854186, 1.39232, 2.29548, 3.79257", \ - "0.13834, 0.430916, 0.599758, 0.889769, 1.40354, 2.29549, 3.79392", \ - "0.200309, 0.562641, 0.741401, 1.0181, 1.49392, 2.33197, 3.80096", \ - "0.303797, 0.786802, 0.996301, 1.30384, 1.77298, 2.55563, 3.92443" \ + "0.0457091, 0.333616, 0.52865, 0.851451, 1.391, 2.29136, 3.79131", \ + "0.0559979, 0.334084, 0.529281, 0.851452, 1.39228, 2.29234, 3.79192", \ + "0.0711318, 0.337406, 0.529393, 0.851971, 1.39229, 2.2931, 3.79193", \ + "0.0962536, 0.360915, 0.541489, 0.854252, 1.39369, 2.29311, 3.79247", \ + "0.13834, 0.430913, 0.599752, 0.889747, 1.40394, 2.29326, 3.79248", \ + "0.200308, 0.562643, 0.741396, 1.0181, 1.4939, 2.33208, 3.80715", \ + "0.303797, 0.786799, 0.996019, 1.30384, 1.77297, 2.55561, 3.92438" \ ); } cell_fall (TIMING_DELAY_7x7ds1) { index_1 ("0.0186, 0.0966, 0.174, 0.3294, 0.6408, 1.263, 2.5074"); index_2 ("0.001, 0.0468, 0.078, 0.1296, 0.216, 0.36, 0.6"); values ( \ - "0.0274385, 0.114985, 0.172681, 0.267905, 0.427457, 0.693373, 1.13645", \ - "0.0539808, 0.16482, 0.223172, 0.318464, 0.478027, 0.744661, 1.18708", \ - "0.0700525, 0.207698, 0.271175, 0.368508, 0.52823, 0.793928, 1.23806", \ - "0.0929408, 0.278232, 0.354368, 0.463671, 0.629002, 0.895379, 1.33799", \ - "0.120755, 0.383278, 0.484274, 0.619904, 0.812843, 1.09345, 1.53826", \ - "0.154627, 0.529779, 0.674179, 0.857486, 1.10426, 1.44303, 1.92964", \ - "0.195042, 0.725127, 0.934739, 1.2028, 1.54189, 1.9889, 2.58923" \ + "0.0274363, 0.114927, 0.172651, 0.267928, 0.427466, 0.693393, 1.13652", \ + "0.0539977, 0.164859, 0.223161, 0.318463, 0.478014, 0.74466, 1.18705", \ + "0.0699873, 0.207712, 0.271194, 0.368559, 0.528267, 0.794015, 1.23813", \ + "0.0929416, 0.278236, 0.354375, 0.463721, 0.629014, 0.895425, 1.338", \ + "0.120756, 0.383283, 0.484285, 0.619915, 0.812918, 1.09348, 1.53822", \ + "0.154629, 0.529785, 0.674188, 0.857497, 1.10432, 1.44306, 1.92982", \ + "0.195045, 0.725098, 0.934749, 1.20282, 1.54191, 1.98894, 2.58927" \ ); } fall_transition (TIMING_DELAY_7x7ds1) { index_1 ("0.0186, 0.0966, 0.174, 0.3294, 0.6408, 1.263, 2.5074"); index_2 ("0.001, 0.0468, 0.078, 0.1296, 0.216, 0.36, 0.6"); values ( \ - "0.0169748, 0.134488, 0.211827, 0.339662, 0.554021, 0.911501, 1.50742", \ - "0.0397399, 0.141382, 0.21439, 0.339868, 0.554022, 0.912042, 1.50743", \ - "0.0599578, 0.159674, 0.227734, 0.346898, 0.555581, 0.912043, 1.50843", \ - "0.0926357, 0.200902, 0.266924, 0.377504, 0.573067, 0.916654, 1.50844", \ - "0.142594, 0.278045, 0.348385, 0.460772, 0.64304, 0.960297, 1.52187", \ - "0.223031, 0.408423, 0.495701, 0.618915, 0.810582, 1.11642, 1.6329", \ - "0.352365, 0.616506, 0.739097, 0.897969, 1.11969, 1.44546, 1.96029" \ + "0.016968, 0.13448, 0.211803, 0.339668, 0.554044, 0.911538, 1.50759", \ + "0.0397301, 0.141367, 0.214396, 0.339877, 0.554045, 0.91208, 1.5076", \ + "0.0600405, 0.1597, 0.227726, 0.346891, 0.5556, 0.912081, 1.50849", \ + "0.0926366, 0.200906, 0.26693, 0.377502, 0.573099, 0.916708, 1.5085", \ + "0.142595, 0.278051, 0.348358, 0.460789, 0.643148, 0.960267, 1.52194", \ + "0.223032, 0.408429, 0.49571, 0.618928, 0.810581, 1.11645, 1.63334", \ + "0.352366, 0.616469, 0.739106, 0.897981, 1.11971, 1.44549, 1.9606" \ ); } } @@ -2744,26 +2744,26 @@ library (sg13g2_stdcell_slow_1p08V_125C) { index_1 ("0.0186, 0.0966, 0.174, 0.3294, 0.6408, 1.263, 2.5074"); index_2 ("0.001, 0.0468, 0.078, 0.1296, 0.216, 0.36, 0.6"); values ( \ - "0.00706189, 0.00739762, 0.00733966, 0.00724058, 0.00705379, 0.00671051, 0.0063462", \ - "0.00664422, 0.00721703, 0.00725364, 0.00719346, 0.00700887, 0.00673441, 0.00635501", \ - "0.00655616, 0.00708035, 0.00709892, 0.00708344, 0.00696697, 0.00669794, 0.00646971", \ - "0.00651395, 0.00691022, 0.00699832, 0.00703764, 0.00719138, 0.00664498, 0.00637046", \ - "0.00664073, 0.00676943, 0.00681626, 0.00708565, 0.0067673, 0.00651055, 0.00647728", \ - "0.00746664, 0.00700126, 0.00698149, 0.00674965, 0.00702204, 0.00654849, 0.00692475", \ - "0.0103671, 0.00819661, 0.00793703, 0.0076555, 0.00729061, 0.00686802, 0.00719662" \ + "0.00706384, 0.00739899, 0.0073426, 0.00723861, 0.00705617, 0.00671027, 0.00634565", \ + "0.0066421, 0.00720726, 0.00725242, 0.00721079, 0.00701772, 0.00673454, 0.00639316", \ + "0.00655626, 0.00708427, 0.00711153, 0.00709268, 0.006969, 0.00669749, 0.00646132", \ + "0.00651218, 0.00690578, 0.0069916, 0.00705101, 0.00719127, 0.00664493, 0.00633883", \ + "0.00664052, 0.00675739, 0.00681904, 0.00692251, 0.00676372, 0.00652226, 0.0064803", \ + "0.00746641, 0.00700128, 0.00698092, 0.00684417, 0.00703026, 0.00654861, 0.00715732", \ + "0.010371, 0.0081959, 0.00793705, 0.00765506, 0.0072186, 0.00687523, 0.00720363" \ ); } fall_power (POWER_7x7ds1) { index_1 ("0.0186, 0.0966, 0.174, 0.3294, 0.6408, 1.263, 2.5074"); index_2 ("0.001, 0.0468, 0.078, 0.1296, 0.216, 0.36, 0.6"); values ( \ - "0.00493753, 0.00491563, 0.00488139, 0.00476697, 0.00459447, 0.00426257, 0.00380016", \ - "0.00438572, 0.00467286, 0.0046536, 0.00458796, 0.00445841, 0.00420306, 0.00374003", \ - "0.00427809, 0.00464403, 0.00459956, 0.00477202, 0.00440875, 0.0041501, 0.00361918", \ - "0.00441259, 0.00450254, 0.00457263, 0.00445283, 0.00435551, 0.00406248, 0.00374644", \ - "0.00496024, 0.00465606, 0.00463442, 0.00448562, 0.00480185, 0.00405135, 0.00364533", \ - "0.00639895, 0.00530867, 0.00520752, 0.00501689, 0.00455657, 0.00441969, 0.00374549", \ - "0.00973807, 0.00747012, 0.00690835, 0.006305, 0.00584653, 0.00476521, 0.00422291" \ + "0.00492681, 0.00492383, 0.00487163, 0.00474155, 0.00459872, 0.00426309, 0.00383699", \ + "0.00438442, 0.0046799, 0.00466548, 0.00458666, 0.00446105, 0.00415394, 0.00374115", \ + "0.0042836, 0.00466112, 0.004603, 0.00477245, 0.00441067, 0.00414924, 0.00359266", \ + "0.00440837, 0.00450254, 0.00456927, 0.0044531, 0.00434409, 0.00408663, 0.00374649", \ + "0.00496039, 0.00465611, 0.00463947, 0.00448602, 0.00480184, 0.0040514, 0.00412142", \ + "0.00639362, 0.00530867, 0.00520909, 0.00501684, 0.00455604, 0.00441974, 0.00374494", \ + "0.0097387, 0.00746976, 0.00690838, 0.00630532, 0.00584178, 0.0047651, 0.00422293" \ ); } } @@ -2773,26 +2773,26 @@ library (sg13g2_stdcell_slow_1p08V_125C) { index_1 ("0.0186, 0.0966, 0.174, 0.3294, 0.6408, 1.263, 2.5074"); index_2 ("0.001, 0.0468, 0.078, 0.1296, 0.216, 0.36, 0.6"); values ( \ - "0.00753586, 0.0075427, 0.00747138, 0.00736437, 0.00718931, 0.0067818, 0.00640765", \ - "0.00726231, 0.00743136, 0.00738269, 0.00731946, 0.00710008, 0.00682319, 0.00641432", \ - "0.00718546, 0.00734707, 0.00731943, 0.00728086, 0.0070877, 0.00680835, 0.00658162", \ - "0.00713044, 0.0072985, 0.00735544, 0.00732536, 0.00719161, 0.00680181, 0.00646445", \ - "0.00720554, 0.00726258, 0.00722796, 0.00734654, 0.00698597, 0.00672262, 0.00656061", \ - "0.00782835, 0.00747553, 0.00745494, 0.00726125, 0.00739091, 0.00684948, 0.0074097", \ - "0.0102865, 0.00872384, 0.00835778, 0.00810413, 0.00760734, 0.0072087, 0.00701089" \ + "0.00754062, 0.00753812, 0.00747357, 0.00737205, 0.00719046, 0.00678144, 0.00640257", \ + "0.00726159, 0.00747748, 0.0073829, 0.00731782, 0.0071302, 0.00682141, 0.00639626", \ + "0.00718659, 0.00739326, 0.0073309, 0.00730735, 0.00709441, 0.00678244, 0.00658477", \ + "0.00712846, 0.00729948, 0.00728302, 0.0073218, 0.00719156, 0.00680166, 0.00646846", \ + "0.00720349, 0.00725674, 0.00724152, 0.00740195, 0.00717105, 0.00672195, 0.00645236", \ + "0.00782608, 0.00747611, 0.00746103, 0.00725903, 0.00739075, 0.00673748, 0.00725832", \ + "0.0102862, 0.008724, 0.00836101, 0.0081042, 0.00760725, 0.00726266, 0.00746165" \ ); } fall_power (POWER_7x7ds1) { index_1 ("0.0186, 0.0966, 0.174, 0.3294, 0.6408, 1.263, 2.5074"); index_2 ("0.001, 0.0468, 0.078, 0.1296, 0.216, 0.36, 0.6"); values ( \ - "0.00740737, 0.00734899, 0.00728435, 0.00718445, 0.00699645, 0.00675288, 0.00624576", \ - "0.00700019, 0.00717369, 0.00711691, 0.00706407, 0.00689567, 0.00658293, 0.00613599", \ - "0.00688002, 0.00716603, 0.0071016, 0.0072672, 0.00686726, 0.00662467, 0.00602955", \ - "0.00681651, 0.00699934, 0.00705292, 0.00696112, 0.00679843, 0.00660645, 0.0062291", \ - "0.00697254, 0.00705269, 0.0070265, 0.00689887, 0.00724032, 0.0066694, 0.00620606", \ - "0.007792, 0.00732559, 0.00729099, 0.00720714, 0.00684913, 0.00687741, 0.00639802", \ - "0.0104018, 0.00877839, 0.00841676, 0.00810798, 0.00775279, 0.00701044, 0.00640544" \ + "0.0074158, 0.0073454, 0.00728499, 0.00717086, 0.00698959, 0.00668138, 0.00624586", \ + "0.00701005, 0.00718089, 0.00710701, 0.00706945, 0.00689531, 0.00658314, 0.00613219", \ + "0.00688657, 0.007165, 0.00708388, 0.00727101, 0.00686994, 0.00660987, 0.00602601", \ + "0.00681654, 0.00699933, 0.00705291, 0.00696105, 0.00679581, 0.0066064, 0.00623102", \ + "0.00697361, 0.00705449, 0.0070267, 0.00691688, 0.00696828, 0.00651256, 0.00621155", \ + "0.00779541, 0.00732308, 0.0072907, 0.00720158, 0.00684852, 0.0068776, 0.00619246", \ + "0.0104011, 0.00877884, 0.00841724, 0.00810839, 0.0077529, 0.00701044, 0.00639009" \ ); } } @@ -2803,26 +2803,26 @@ library (sg13g2_stdcell_slow_1p08V_125C) { index_1 ("0.0186, 0.0966, 0.174, 0.3294, 0.6408, 1.263, 2.5074"); index_2 ("0.001, 0.0468, 0.078, 0.1296, 0.216, 0.36, 0.6"); values ( \ - "0.0044295, 0.0048422, 0.00478463, 0.00468597, 0.00446336, 0.00409791, 0.00369564", \ - "0.00402597, 0.00451435, 0.00457799, 0.00451564, 0.00441056, 0.00415788, 0.00379189", \ - "0.00402285, 0.00434617, 0.00440832, 0.00442492, 0.0043318, 0.00408241, 0.00380006", \ - "0.00420322, 0.00426144, 0.00428616, 0.0043982, 0.0042079, 0.00422197, 0.0036347", \ - "0.00482207, 0.00451169, 0.00441141, 0.00452799, 0.00423486, 0.00389719, 0.00368935", \ - "0.00638974, 0.00518772, 0.00495771, 0.00456848, 0.00461026, 0.00395118, 0.0037492", \ - "0.00993352, 0.00738233, 0.00684096, 0.00624893, 0.00551499, 0.00482689, 0.00441351" \ + "0.00442583, 0.00484394, 0.00479311, 0.00468666, 0.00446542, 0.00412688, 0.00369642", \ + "0.00402183, 0.00451444, 0.00457641, 0.00451496, 0.0044098, 0.00415631, 0.00379223", \ + "0.0040307, 0.00435334, 0.00440409, 0.0044254, 0.00433356, 0.00408355, 0.0036952", \ + "0.00419597, 0.00425648, 0.00436543, 0.00439933, 0.00434571, 0.00397077, 0.00363375", \ + "0.00481698, 0.0045121, 0.00441052, 0.00443202, 0.00419894, 0.00393097, 0.00358371", \ + "0.006388, 0.00519118, 0.00495826, 0.00456816, 0.00461949, 0.00401396, 0.00404665", \ + "0.00993247, 0.00738242, 0.00684227, 0.00624203, 0.0053772, 0.00473631, 0.00471372" \ ); } fall_power (POWER_7x7ds1) { index_1 ("0.0186, 0.0966, 0.174, 0.3294, 0.6408, 1.263, 2.5074"); index_2 ("0.001, 0.0468, 0.078, 0.1296, 0.216, 0.36, 0.6"); values ( \ - "0.00489793, 0.00550541, 0.0054757, 0.00535792, 0.00521242, 0.0049378, 0.00445727", \ - "0.00445552, 0.00536571, 0.00537781, 0.0053434, 0.00523734, 0.00508467, 0.0045276", \ - "0.00445445, 0.00516572, 0.00531405, 0.00526963, 0.0051787, 0.00498389, 0.00468174", \ - "0.00471014, 0.00511289, 0.00514465, 0.00520898, 0.00527313, 0.00561386, 0.00437688", \ - "0.00544485, 0.00508778, 0.0051995, 0.00522165, 0.00501784, 0.00524489, 0.00471948", \ - "0.00719669, 0.00580987, 0.00558732, 0.00553578, 0.00546505, 0.00485641, 0.00450463", \ - "0.0110158, 0.00817303, 0.00734163, 0.00692304, 0.00631829, 0.00604841, 0.00478653" \ + "0.00489919, 0.00550048, 0.00547093, 0.0053515, 0.00521122, 0.00493599, 0.00443088", \ + "0.00445428, 0.00536788, 0.00538244, 0.00534049, 0.00522448, 0.00508065, 0.00452966", \ + "0.00445719, 0.0051646, 0.00531035, 0.00527533, 0.00518255, 0.00498638, 0.00468352", \ + "0.00471067, 0.00511057, 0.0051379, 0.00519382, 0.00523383, 0.00561911, 0.00439282", \ + "0.0054446, 0.00509401, 0.00519091, 0.00522242, 0.00501383, 0.00513643, 0.00471047", \ + "0.00719645, 0.00581129, 0.0055869, 0.00553651, 0.00545964, 0.00485635, 0.00452485", \ + "0.0110158, 0.00817055, 0.00734241, 0.0069236, 0.00631389, 0.00604053, 0.00474994" \ ); } } @@ -2833,26 +2833,26 @@ library (sg13g2_stdcell_slow_1p08V_125C) { index_1 ("0.0186, 0.0966, 0.174, 0.3294, 0.6408, 1.263, 2.5074"); index_2 ("0.001, 0.0468, 0.078, 0.1296, 0.216, 0.36, 0.6"); values ( \ - "0.00365201, 0.00429693, 0.00425893, 0.0041594, 0.00396498, 0.00362605, 0.00323731", \ - "0.00337575, 0.0039308, 0.00399908, 0.00397213, 0.00386833, 0.00362813, 0.00324086", \ - "0.00345037, 0.00382666, 0.00388779, 0.003896, 0.0037494, 0.00353912, 0.00329106", \ - "0.00370534, 0.00369699, 0.00382758, 0.00382764, 0.00369795, 0.0034631, 0.00312487", \ - "0.00443952, 0.00397431, 0.00387663, 0.00389592, 0.00376052, 0.00342361, 0.00322258", \ - "0.00618987, 0.0047337, 0.00441807, 0.00404036, 0.00410073, 0.0034794, 0.00385359", \ - "0.00999338, 0.0069119, 0.00639301, 0.00575181, 0.00497935, 0.00433065, 0.00394012" \ + "0.00365643, 0.00429584, 0.0042591, 0.00415893, 0.00396469, 0.00362703, 0.00323632", \ + "0.00337589, 0.00392344, 0.00399417, 0.00397896, 0.00386846, 0.00356583, 0.00319628", \ + "0.00345782, 0.00382686, 0.00385844, 0.00389932, 0.00374965, 0.00353864, 0.00329081", \ + "0.00370612, 0.00369711, 0.00381514, 0.0038084, 0.00374979, 0.00370671, 0.00307929", \ + "0.00443665, 0.00397938, 0.00387651, 0.00388264, 0.00360509, 0.00335784, 0.00322397", \ + "0.00619017, 0.00473454, 0.00440677, 0.00404184, 0.00410564, 0.00338205, 0.00330874", \ + "0.00999327, 0.00691253, 0.00639297, 0.00573988, 0.0048373, 0.00433258, 0.00394053" \ ); } fall_power (POWER_7x7ds1) { index_1 ("0.0186, 0.0966, 0.174, 0.3294, 0.6408, 1.263, 2.5074"); index_2 ("0.001, 0.0468, 0.078, 0.1296, 0.216, 0.36, 0.6"); values ( \ - "0.00246726, 0.00307852, 0.00304617, 0.00293367, 0.00278614, 0.0025067, 0.00208516", \ - "0.00201349, 0.00293094, 0.00295423, 0.00293716, 0.00293038, 0.00268236, 0.0020727", \ - "0.00201755, 0.0027525, 0.00287464, 0.00287969, 0.00277382, 0.00263393, 0.00224552", \ - "0.00227099, 0.00269422, 0.00266599, 0.00278519, 0.00280605, 0.00299828, 0.00198518", \ - "0.00303944, 0.00266734, 0.00277892, 0.00281415, 0.00256657, 0.00284224, 0.00187703", \ - "0.00483488, 0.00341984, 0.00315627, 0.00315497, 0.00309559, 0.00244757, 0.00214657", \ - "0.00871384, 0.00580084, 0.00498605, 0.00456231, 0.00395579, 0.00365198, 0.00246145" \ + "0.0024655, 0.00307768, 0.00303835, 0.00293561, 0.00278617, 0.0025062, 0.00199549", \ + "0.00201318, 0.00293056, 0.00295184, 0.00291996, 0.00284338, 0.00267146, 0.00206774", \ + "0.00201738, 0.00274709, 0.00288345, 0.00287832, 0.00290981, 0.00262462, 0.00209296", \ + "0.00227097, 0.00269416, 0.00266598, 0.00275568, 0.00299829, 0.00299705, 0.00198662", \ + "0.00303893, 0.00266691, 0.00278632, 0.00278512, 0.00256398, 0.00284061, 0.00189279", \ + "0.00483481, 0.00341988, 0.00315606, 0.00315454, 0.00309154, 0.00251634, 0.00217561", \ + "0.00871434, 0.00580062, 0.00498565, 0.00456198, 0.00395664, 0.00365794, 0.0024261" \ ); } } @@ -2863,26 +2863,26 @@ library (sg13g2_stdcell_slow_1p08V_125C) { index_1 ("0.0186, 0.0966, 0.174, 0.3294, 0.6408, 1.263, 2.5074"); index_2 ("0.001, 0.0468, 0.078, 0.1296, 0.216, 0.36, 0.6"); values ( \ - "0.00365893, 0.00430404, 0.00425301, 0.00415123, 0.00394772, 0.00391848, 0.00369862", \ - "0.00339775, 0.00393406, 0.00397974, 0.0039726, 0.0038314, 0.00385863, 0.0038964", \ - "0.00348395, 0.00387934, 0.0039488, 0.00388021, 0.00377019, 0.00379276, 0.00367736", \ - "0.00373925, 0.00368309, 0.00382602, 0.00382223, 0.00365331, 0.00371356, 0.00374606", \ - "0.00452182, 0.00407807, 0.00386981, 0.00389071, 0.0036374, 0.00389968, 0.00358471", \ - "0.00636258, 0.00483785, 0.00450343, 0.00422519, 0.00393472, 0.00390027, 0.00364558", \ - "0.0103102, 0.00705131, 0.00644574, 0.00576452, 0.00496883, 0.00422619, 0.00418321" \ + "0.00365426, 0.00430729, 0.00425194, 0.00415798, 0.0039513, 0.00395745, 0.00402271", \ + "0.00339945, 0.00395526, 0.00399878, 0.00397034, 0.00381506, 0.00385838, 0.00391965", \ + "0.0034847, 0.00385448, 0.00395486, 0.00385413, 0.00377254, 0.00376469, 0.00367328", \ + "0.00373689, 0.00366778, 0.0038249, 0.0037681, 0.00365628, 0.00385952, 0.003746", \ + "0.00452285, 0.00407864, 0.00387537, 0.00390323, 0.00363632, 0.00393021, 0.00361092", \ + "0.00636225, 0.0048378, 0.00449176, 0.00422553, 0.00393592, 0.00404323, 0.0036438", \ + "0.0103097, 0.00709055, 0.00644671, 0.00576453, 0.00507107, 0.00410987, 0.00417606" \ ); } fall_power (POWER_7x7ds1) { index_1 ("0.0186, 0.0966, 0.174, 0.3294, 0.6408, 1.263, 2.5074"); index_2 ("0.001, 0.0468, 0.078, 0.1296, 0.216, 0.36, 0.6"); values ( \ - "0.00238104, 0.00300945, 0.00298111, 0.00286047, 0.00272068, 0.00244037, 0.00186705", \ - "0.00193808, 0.00278168, 0.00282563, 0.00279131, 0.00268481, 0.00253619, 0.00193877", \ - "0.00197113, 0.00259595, 0.00273213, 0.00276118, 0.00264809, 0.00253804, 0.00212706", \ - "0.00225294, 0.00254391, 0.00253545, 0.00260766, 0.00296731, 0.00286455, 0.00184522", \ - "0.00309286, 0.00255321, 0.00267292, 0.00264639, 0.00241841, 0.00269188, 0.00209377", \ - "0.00493009, 0.00336001, 0.00311115, 0.00313241, 0.00296608, 0.00232902, 0.001941", \ - "0.00899368, 0.00579093, 0.00508289, 0.0045716, 0.00392326, 0.0035493, 0.00229489" \ + "0.00238022, 0.00300953, 0.00298692, 0.00287131, 0.00272124, 0.0024442, 0.00194325", \ + "0.00193826, 0.00279222, 0.00282065, 0.00281811, 0.00267687, 0.00253804, 0.00191866", \ + "0.00196768, 0.00260146, 0.00272987, 0.00272986, 0.00276921, 0.00261473, 0.00212549", \ + "0.00225136, 0.00253268, 0.00253555, 0.00260754, 0.00269754, 0.00286352, 0.00184355", \ + "0.0030936, 0.00255337, 0.00267048, 0.00264092, 0.00245072, 0.00270036, 0.00204882", \ + "0.00492908, 0.00336038, 0.00311102, 0.00313898, 0.00296355, 0.00233335, 0.00199822", \ + "0.00899319, 0.00579146, 0.00508396, 0.0045718, 0.00392218, 0.00361613, 0.00232037" \ ); } } @@ -2892,26 +2892,26 @@ library (sg13g2_stdcell_slow_1p08V_125C) { index_1 ("0.0186, 0.0966, 0.174, 0.3294, 0.6408, 1.263, 2.5074"); index_2 ("0.001, 0.0468, 0.078, 0.1296, 0.216, 0.36, 0.6"); values ( \ - "0.00365893, 0.00430404, 0.00425301, 0.00415123, 0.00394772, 0.00391848, 0.00369862", \ - "0.00339775, 0.00393406, 0.00397974, 0.0039726, 0.0038314, 0.00385863, 0.0038964", \ - "0.00348395, 0.00387934, 0.0039488, 0.00388021, 0.00377019, 0.00379276, 0.00367736", \ - "0.00373925, 0.00368309, 0.00382602, 0.00382223, 0.00365331, 0.00371356, 0.00374606", \ - "0.00452182, 0.00407807, 0.00386981, 0.00389071, 0.0036374, 0.00389968, 0.00358471", \ - "0.00636258, 0.00483785, 0.00450343, 0.00422519, 0.00393472, 0.00390027, 0.00364558", \ - "0.0103102, 0.00705131, 0.00644574, 0.00576452, 0.00496883, 0.00422619, 0.00418321" \ + "0.00365426, 0.00430729, 0.00425194, 0.00415798, 0.0039513, 0.00395745, 0.00402271", \ + "0.00339945, 0.00395526, 0.00399878, 0.00397034, 0.00381506, 0.00385838, 0.00391965", \ + "0.0034847, 0.00385448, 0.00395486, 0.00385413, 0.00377254, 0.00376469, 0.00367328", \ + "0.00373689, 0.00366778, 0.0038249, 0.0037681, 0.00365628, 0.00385952, 0.003746", \ + "0.00452285, 0.00407864, 0.00387537, 0.00390323, 0.00363632, 0.00393021, 0.00361092", \ + "0.00636225, 0.0048378, 0.00449176, 0.00422553, 0.00393592, 0.00404323, 0.0036438", \ + "0.0103097, 0.00709055, 0.00644671, 0.00576453, 0.00507107, 0.00410987, 0.00417606" \ ); } fall_power (POWER_7x7ds1) { index_1 ("0.0186, 0.0966, 0.174, 0.3294, 0.6408, 1.263, 2.5074"); index_2 ("0.001, 0.0468, 0.078, 0.1296, 0.216, 0.36, 0.6"); values ( \ - "0.00246726, 0.00307852, 0.00304617, 0.00293367, 0.00278614, 0.0025067, 0.00208516", \ - "0.00201349, 0.00293094, 0.00295423, 0.00293716, 0.00293038, 0.00268236, 0.0020727", \ - "0.00201755, 0.0027525, 0.00287464, 0.00287969, 0.00277382, 0.00263393, 0.00224552", \ - "0.00227099, 0.00269422, 0.00266599, 0.00278519, 0.00280605, 0.00299828, 0.00198518", \ - "0.00303944, 0.00266734, 0.00277892, 0.00281415, 0.00256657, 0.00284224, 0.00187703", \ - "0.00483488, 0.00341984, 0.00315627, 0.00315497, 0.00309559, 0.00244757, 0.00214657", \ - "0.00871384, 0.00580084, 0.00498605, 0.00456231, 0.00395579, 0.00365198, 0.00246145" \ + "0.0024655, 0.00307768, 0.00303835, 0.00293561, 0.00278617, 0.0025062, 0.00199549", \ + "0.00201318, 0.00293056, 0.00295184, 0.00291996, 0.00284338, 0.00267146, 0.00206774", \ + "0.00201738, 0.00274709, 0.00288345, 0.00287832, 0.00290981, 0.00262462, 0.00209296", \ + "0.00227097, 0.00269416, 0.00266598, 0.00275568, 0.00299829, 0.00299705, 0.00198662", \ + "0.00303893, 0.00266691, 0.00278632, 0.00278512, 0.00256398, 0.00284061, 0.00189279", \ + "0.00483481, 0.00341988, 0.00315606, 0.00315454, 0.00309154, 0.00251634, 0.00217561", \ + "0.00871434, 0.00580062, 0.00498565, 0.00456198, 0.00395664, 0.00365794, 0.0024261" \ ); } } @@ -2919,29 +2919,29 @@ library (sg13g2_stdcell_slow_1p08V_125C) { pin (A1) { direction : "input"; max_transition : 2.5074; - capacitance : 0.00543006; - rise_capacitance : 0.00545177; - rise_capacitance_range (0.00545177, 0.00545177); - fall_capacitance : 0.00540835; - fall_capacitance_range (0.00540835, 0.00540835); + capacitance : 0.00543015; + rise_capacitance : 0.00545205; + rise_capacitance_range (0.00498168, 0.00585378); + fall_capacitance : 0.00540825; + fall_capacitance_range (0.00469751, 0.00617867); } pin (A2) { direction : "input"; max_transition : 2.5074; - capacitance : 0.00563877; - rise_capacitance : 0.00574351; - rise_capacitance_range (0.00574351, 0.00574351); - fall_capacitance : 0.00553404; - fall_capacitance_range (0.00553404, 0.00553404); + capacitance : 0.005639; + rise_capacitance : 0.00574346; + rise_capacitance_range (0.0051209, 0.00641566); + fall_capacitance : 0.00553453; + fall_capacitance_range (0.00504122, 0.00622747); } pin (B1) { direction : "input"; max_transition : 2.5074; - capacitance : 0.00531905; - rise_capacitance : 0.00544928; - rise_capacitance_range (0.00544928, 0.00544928); - fall_capacitance : 0.00518882; - fall_capacitance_range (0.00518882, 0.00518882); + capacitance : 0.0053191; + rise_capacitance : 0.00544949; + rise_capacitance_range (0.00426434, 0.00618993); + fall_capacitance : 0.00518872; + fall_capacitance_range (0.00454878, 0.00580999); } } cell (sg13g2_a221oi_1) { @@ -5010,113 +5010,113 @@ library (sg13g2_stdcell_slow_1p08V_125C) { max_transition : 2.5074; capacitance : 0.00277648; rise_capacitance : 0.00278948; - rise_capacitance_range (0.00278948, 0.00278948); + rise_capacitance_range (0.00263174, 0.00295037); fall_capacitance : 0.00276348; - fall_capacitance_range (0.00276348, 0.00276348); + fall_capacitance_range (0.00247478, 0.00304419); } pin (A2) { direction : "input"; max_transition : 2.5074; capacitance : 0.00278302; rise_capacitance : 0.0028385; - rise_capacitance_range (0.0028385, 0.0028385); + rise_capacitance_range (0.00253479, 0.00314536); fall_capacitance : 0.00272755; - fall_capacitance_range (0.00272755, 0.00272755); + fall_capacitance_range (0.00251516, 0.00300204); } pin (B1) { direction : "input"; max_transition : 2.5074; capacitance : 0.00274018; rise_capacitance : 0.0027598; - rise_capacitance_range (0.0027598, 0.0027598); + rise_capacitance_range (0.00245558, 0.00299524); fall_capacitance : 0.00272056; - fall_capacitance_range (0.00272056, 0.00272056); + fall_capacitance_range (0.00237199, 0.0030942); } pin (B2) { direction : "input"; max_transition : 2.5074; capacitance : 0.00280602; rise_capacitance : 0.00286841; - rise_capacitance_range (0.00286841, 0.00286841); + rise_capacitance_range (0.00246083, 0.00323855); fall_capacitance : 0.00274363; - fall_capacitance_range (0.00274363, 0.00274363); + fall_capacitance_range (0.0024732, 0.00309389); } pin (C1) { direction : "input"; max_transition : 2.5074; capacitance : 0.00269884; rise_capacitance : 0.00276741; - rise_capacitance_range (0.00276741, 0.00276741); + rise_capacitance_range (0.00231646, 0.00309237); fall_capacitance : 0.00263026; - fall_capacitance_range (0.00263026, 0.00263026); + fall_capacitance_range (0.00237854, 0.00284387); } } cell (sg13g2_a22oi_1) { area : 10.8486; cell_footprint : "a22oi"; - cell_leakage_power : 562.873; + cell_leakage_power : 562.89; leakage_power () { - value : 90.9635; + value : 90.9796; when : "!A1&!A2&!B1&!B2&Y"; } leakage_power () { - value : 169.843; + value : 169.859; when : "!A1&!A2&!B1&B2&Y"; } leakage_power () { - value : 184.847; + value : 184.863; when : "!A1&!A2&B1&!B2&Y"; } leakage_power () { - value : 967.801; + value : 967.817; when : "!A1&!A2&B1&B2&!Y"; } leakage_power () { - value : 184.91; + value : 184.926; when : "!A1&A2&!B1&!B2&Y"; } leakage_power () { - value : 263.789; + value : 263.806; when : "!A1&A2&!B1&B2&Y"; } leakage_power () { - value : 278.793; + value : 278.809; when : "!A1&A2&B1&!B2&Y"; } leakage_power () { - value : 965.795; + value : 965.811; when : "!A1&A2&B1&B2&!Y"; } leakage_power () { - value : 169.806; + value : 169.822; when : "A1&!A2&!B1&!B2&Y"; } leakage_power () { - value : 248.686; + value : 248.702; when : "A1&!A2&!B1&B2&Y"; } leakage_power () { - value : 263.689; + value : 263.705; when : "A1&!A2&B1&!B2&Y"; } leakage_power () { - value : 965.722; + value : 965.738; when : "A1&!A2&B1&B2&!Y"; } leakage_power () { - value : 1261.3; + value : 1261.31; when : "A1&A2&!B1&!B2&!Y"; } leakage_power () { - value : 1244.1; + value : 1244.12; when : "A1&A2&!B1&B2&!Y"; } leakage_power () { - value : 1244.1; + value : 1244.12; when : "A1&A2&B1&!B2&!Y"; } leakage_power () { - value : 501.829; + value : 501.845; when : "A1&A2&B1&B2&!Y"; } pin (Y) { @@ -5134,52 +5134,52 @@ library (sg13g2_stdcell_slow_1p08V_125C) { index_1 ("0.0186, 0.0966, 0.174, 0.3294, 0.6408, 1.263, 2.5074"); index_2 ("0.001, 0.0234, 0.039, 0.0648, 0.108, 0.18, 0.3"); values ( \ - "0.0810644, 0.2865, 0.427867, 0.661765, 1.05319, 1.70553, 2.79188", \ - "0.115394, 0.324026, 0.465864, 0.700425, 1.09158, 1.74517, 2.83104", \ - "0.141536, 0.357809, 0.499997, 0.734479, 1.12646, 1.77874, 2.86776", \ - "0.17945, 0.420311, 0.565018, 0.799641, 1.19205, 1.84832, 2.932", \ - "0.226169, 0.522303, 0.68022, 0.923594, 1.31793, 1.97076, 3.06061", \ - "0.273006, 0.67336, 0.865456, 1.13885, 1.55656, 2.21886, 3.30703", \ - "0.320317, 0.886703, 1.13939, 1.48273, 1.97176, 2.69208, 3.81243" \ + "0.0810838, 0.286501, 0.427865, 0.661761, 1.05289, 1.70495, 2.79189", \ + "0.115394, 0.324028, 0.465819, 0.700427, 1.09249, 1.74516, 2.83083", \ + "0.141494, 0.357796, 0.50005, 0.734478, 1.12646, 1.77874, 2.86674", \ + "0.179449, 0.420311, 0.565017, 0.799639, 1.19204, 1.84832, 2.932", \ + "0.226169, 0.522302, 0.680219, 0.923594, 1.3179, 1.97076, 3.05963", \ + "0.273006, 0.673359, 0.865454, 1.13885, 1.55656, 2.21885, 3.30702", \ + "0.320317, 0.886702, 1.13939, 1.48273, 1.97175, 2.69208, 3.8123" \ ); } rise_transition (TIMING_DELAY_7x7ds1) { index_1 ("0.0186, 0.0966, 0.174, 0.3294, 0.6408, 1.263, 2.5074"); index_2 ("0.001, 0.0234, 0.039, 0.0648, 0.108, 0.18, 0.3"); values ( \ - "0.0533226, 0.333262, 0.528054, 0.85001, 1.38924, 2.28786, 3.78579", \ - "0.0575622, 0.333263, 0.528055, 0.850109, 1.38931, 2.28803, 3.78587", \ - "0.0668462, 0.335237, 0.528125, 0.850755, 1.38949, 2.28828, 3.78588", \ - "0.0856428, 0.348424, 0.535121, 0.85145, 1.39128, 2.29162, 3.78624", \ - "0.124241, 0.393414, 0.571032, 0.873194, 1.39674, 2.29163, 3.78794", \ - "0.197966, 0.493496, 0.671392, 0.959574, 1.45455, 2.31431, 3.81094", \ - "0.333093, 0.677951, 0.870239, 1.16756, 1.64769, 2.46245, 3.87175" \ + "0.053316, 0.333261, 0.528056, 0.850008, 1.38927, 2.28796, 3.78578", \ + "0.057562, 0.333865, 0.528057, 0.850105, 1.38928, 2.28803, 3.78579", \ + "0.066799, 0.335225, 0.528309, 0.850753, 1.38949, 2.28809, 3.7858", \ + "0.0856426, 0.348422, 0.535121, 0.851447, 1.39128, 2.29162, 3.78623", \ + "0.124241, 0.393412, 0.571031, 0.873194, 1.39675, 2.29163, 3.78835", \ + "0.197966, 0.493495, 0.671392, 0.959572, 1.45461, 2.31432, 3.81094", \ + "0.333093, 0.67795, 0.870238, 1.16756, 1.64768, 2.46245, 3.87217" \ ); } cell_fall (TIMING_DELAY_7x7ds1) { index_1 ("0.0186, 0.0966, 0.174, 0.3294, 0.6408, 1.263, 2.5074"); index_2 ("0.001, 0.0234, 0.039, 0.0648, 0.108, 0.18, 0.3"); values ( \ - "0.0679785, 0.225422, 0.331885, 0.507103, 0.799961, 1.28753, 2.0996", \ - "0.104714, 0.267118, 0.373597, 0.549159, 0.841945, 1.3296, 2.14185", \ - "0.132385, 0.308964, 0.41621, 0.591559, 0.884361, 1.37209, 2.18378", \ - "0.175401, 0.38577, 0.500098, 0.678216, 0.971112, 1.45852, 2.27145", \ - "0.232756, 0.505144, 0.640476, 0.839139, 1.14093, 1.62839, 2.43902", \ - "0.311503, 0.679835, 0.854293, 1.09749, 1.4471, 1.9672, 2.78509", \ - "0.417501, 0.917533, 1.16014, 1.48131, 1.92415, 2.54157, 3.44317" \ + "0.0679888, 0.225425, 0.331882, 0.507089, 0.799961, 1.28753, 2.09961", \ + "0.104717, 0.267126, 0.373644, 0.549087, 0.841955, 1.32962, 2.14191", \ + "0.132399, 0.30897, 0.416307, 0.591607, 0.884343, 1.37212, 2.18377", \ + "0.175401, 0.385754, 0.500105, 0.678273, 0.971117, 1.45858, 2.27144", \ + "0.232757, 0.505145, 0.640478, 0.839142, 1.14095, 1.6284, 2.43904", \ + "0.311505, 0.679837, 0.854296, 1.09749, 1.4471, 1.96727, 2.78511", \ + "0.417502, 0.917535, 1.16015, 1.48132, 1.92415, 2.54158, 3.44316" \ ); } fall_transition (TIMING_DELAY_7x7ds1) { index_1 ("0.0186, 0.0966, 0.174, 0.3294, 0.6408, 1.263, 2.5074"); index_2 ("0.001, 0.0234, 0.039, 0.0648, 0.108, 0.18, 0.3"); values ( \ - "0.0537988, 0.25602, 0.396326, 0.628279, 1.01612, 1.6607, 2.73662", \ - "0.0643237, 0.257152, 0.396327, 0.62828, 1.01613, 1.66071, 2.73831", \ - "0.0793714, 0.265796, 0.400168, 0.632525, 1.01614, 1.66171, 2.73832", \ - "0.10764, 0.297471, 0.423505, 0.64077, 1.01852, 1.66172, 2.73926", \ - "0.154457, 0.370315, 0.495756, 0.698835, 1.05336, 1.67165, 2.74375", \ - "0.226443, 0.503872, 0.641059, 0.849699, 1.18842, 1.76269, 2.77615", \ - "0.344052, 0.719923, 0.891302, 1.13588, 1.48642, 2.05534, 2.99883" \ + "0.0538954, 0.25602, 0.396329, 0.628298, 1.01613, 1.66071, 2.73665", \ + "0.0643492, 0.257131, 0.39633, 0.628299, 1.01614, 1.66072, 2.73834", \ + "0.0793633, 0.265881, 0.400644, 0.632534, 1.01615, 1.66172, 2.73835", \ + "0.10764, 0.297484, 0.423607, 0.640794, 1.01853, 1.66173, 2.73926", \ + "0.154457, 0.370317, 0.495758, 0.69884, 1.05263, 1.67178, 2.74377", \ + "0.226444, 0.503868, 0.641062, 0.849704, 1.18842, 1.76324, 2.77617", \ + "0.344052, 0.719924, 0.891305, 1.13588, 1.48643, 2.05378, 2.99882" \ ); } } @@ -5191,52 +5191,52 @@ library (sg13g2_stdcell_slow_1p08V_125C) { index_1 ("0.0186, 0.0966, 0.174, 0.3294, 0.6408, 1.263, 2.5074"); index_2 ("0.001, 0.0234, 0.039, 0.0648, 0.108, 0.18, 0.3"); values ( \ - "0.0810644, 0.2865, 0.427867, 0.661765, 1.05319, 1.70553, 2.79188", \ - "0.115394, 0.324026, 0.465864, 0.700425, 1.09158, 1.74517, 2.83104", \ - "0.141536, 0.357809, 0.499997, 0.734479, 1.12646, 1.77874, 2.86776", \ - "0.17945, 0.420311, 0.565018, 0.799641, 1.19205, 1.84832, 2.932", \ - "0.226169, 0.522303, 0.68022, 0.923594, 1.31793, 1.97076, 3.06061", \ - "0.273006, 0.67336, 0.865456, 1.13885, 1.55656, 2.21886, 3.30703", \ - "0.320317, 0.886703, 1.13939, 1.48273, 1.97176, 2.69208, 3.81243" \ + "0.0810838, 0.286501, 0.427865, 0.661761, 1.05289, 1.70495, 2.79189", \ + "0.115394, 0.324028, 0.465819, 0.700427, 1.09249, 1.74516, 2.83083", \ + "0.141494, 0.357796, 0.50005, 0.734478, 1.12646, 1.77874, 2.86674", \ + "0.179449, 0.420311, 0.565017, 0.799639, 1.19204, 1.84832, 2.932", \ + "0.226169, 0.522302, 0.680219, 0.923594, 1.3179, 1.97076, 3.05963", \ + "0.273006, 0.673359, 0.865454, 1.13885, 1.55656, 2.21885, 3.30702", \ + "0.320317, 0.886702, 1.13939, 1.48273, 1.97175, 2.69208, 3.8123" \ ); } rise_transition (TIMING_DELAY_7x7ds1) { index_1 ("0.0186, 0.0966, 0.174, 0.3294, 0.6408, 1.263, 2.5074"); index_2 ("0.001, 0.0234, 0.039, 0.0648, 0.108, 0.18, 0.3"); values ( \ - "0.0533226, 0.333262, 0.528054, 0.85001, 1.38924, 2.28786, 3.78579", \ - "0.0575622, 0.333263, 0.528055, 0.850109, 1.38931, 2.28803, 3.78587", \ - "0.0668462, 0.335237, 0.528125, 0.850755, 1.38949, 2.28828, 3.78588", \ - "0.0856428, 0.348424, 0.535121, 0.85145, 1.39128, 2.29162, 3.78624", \ - "0.124241, 0.393414, 0.571032, 0.873194, 1.39674, 2.29163, 3.78794", \ - "0.197966, 0.493496, 0.671392, 0.959574, 1.45455, 2.31431, 3.81094", \ - "0.333093, 0.677951, 0.870239, 1.16756, 1.64769, 2.46245, 3.87175" \ + "0.053316, 0.333261, 0.528056, 0.850008, 1.38927, 2.28796, 3.78578", \ + "0.057562, 0.333865, 0.528057, 0.850105, 1.38928, 2.28803, 3.78579", \ + "0.066799, 0.335225, 0.528309, 0.850753, 1.38949, 2.28809, 3.7858", \ + "0.0856426, 0.348422, 0.535121, 0.851447, 1.39128, 2.29162, 3.78623", \ + "0.124241, 0.393412, 0.571031, 0.873194, 1.39675, 2.29163, 3.78835", \ + "0.197966, 0.493495, 0.671392, 0.959572, 1.45461, 2.31432, 3.81094", \ + "0.333093, 0.67795, 0.870238, 1.16756, 1.64768, 2.46245, 3.87217" \ ); } cell_fall (TIMING_DELAY_7x7ds1) { index_1 ("0.0186, 0.0966, 0.174, 0.3294, 0.6408, 1.263, 2.5074"); index_2 ("0.001, 0.0234, 0.039, 0.0648, 0.108, 0.18, 0.3"); values ( \ - "0.0679785, 0.225422, 0.331885, 0.507103, 0.799961, 1.28753, 2.0996", \ - "0.104714, 0.267118, 0.373597, 0.549159, 0.841945, 1.3296, 2.14185", \ - "0.132385, 0.308964, 0.41621, 0.591559, 0.884361, 1.37209, 2.18378", \ - "0.175401, 0.38577, 0.500098, 0.678216, 0.971112, 1.45852, 2.27145", \ - "0.232756, 0.505144, 0.640476, 0.839139, 1.14093, 1.62839, 2.43902", \ - "0.311503, 0.679835, 0.854293, 1.09749, 1.4471, 1.9672, 2.78509", \ - "0.417501, 0.917533, 1.16014, 1.48131, 1.92415, 2.54157, 3.44317" \ + "0.0679888, 0.225425, 0.331882, 0.507089, 0.799961, 1.28753, 2.09961", \ + "0.104717, 0.267126, 0.373644, 0.549087, 0.841955, 1.32962, 2.14191", \ + "0.132399, 0.30897, 0.416307, 0.591607, 0.884343, 1.37212, 2.18377", \ + "0.175401, 0.385754, 0.500105, 0.678273, 0.971117, 1.45858, 2.27144", \ + "0.232757, 0.505145, 0.640478, 0.839142, 1.14095, 1.6284, 2.43904", \ + "0.311505, 0.679837, 0.854296, 1.09749, 1.4471, 1.96727, 2.78511", \ + "0.417502, 0.917535, 1.16015, 1.48132, 1.92415, 2.54158, 3.44316" \ ); } fall_transition (TIMING_DELAY_7x7ds1) { index_1 ("0.0186, 0.0966, 0.174, 0.3294, 0.6408, 1.263, 2.5074"); index_2 ("0.001, 0.0234, 0.039, 0.0648, 0.108, 0.18, 0.3"); values ( \ - "0.0537988, 0.25602, 0.396326, 0.628279, 1.01612, 1.6607, 2.73662", \ - "0.0643237, 0.257152, 0.396327, 0.62828, 1.01613, 1.66071, 2.73831", \ - "0.0793714, 0.265796, 0.400168, 0.632525, 1.01614, 1.66171, 2.73832", \ - "0.10764, 0.297471, 0.423505, 0.64077, 1.01852, 1.66172, 2.73926", \ - "0.154457, 0.370315, 0.495756, 0.698835, 1.05336, 1.67165, 2.74375", \ - "0.226443, 0.503872, 0.641059, 0.849699, 1.18842, 1.76269, 2.77615", \ - "0.344052, 0.719923, 0.891302, 1.13588, 1.48642, 2.05534, 2.99883" \ + "0.0538954, 0.25602, 0.396329, 0.628298, 1.01613, 1.66071, 2.73665", \ + "0.0643492, 0.257131, 0.39633, 0.628299, 1.01614, 1.66072, 2.73834", \ + "0.0793633, 0.265881, 0.400644, 0.632534, 1.01615, 1.66172, 2.73835", \ + "0.10764, 0.297484, 0.423607, 0.640794, 1.01853, 1.66173, 2.73926", \ + "0.154457, 0.370317, 0.495758, 0.69884, 1.05263, 1.67178, 2.74377", \ + "0.226444, 0.503868, 0.641062, 0.849704, 1.18842, 1.76324, 2.77617", \ + "0.344052, 0.719924, 0.891305, 1.13588, 1.48643, 2.05378, 2.99882" \ ); } } @@ -5250,52 +5250,52 @@ library (sg13g2_stdcell_slow_1p08V_125C) { index_1 ("0.0186, 0.0966, 0.174, 0.3294, 0.6408, 1.263, 2.5074"); index_2 ("0.001, 0.0234, 0.039, 0.0648, 0.108, 0.18, 0.3"); values ( \ - "0.091409, 0.296287, 0.437541, 0.671122, 1.06158, 1.71238, 2.797", \ - "0.127783, 0.334461, 0.475851, 0.70998, 1.1004, 1.75244, 2.83684", \ - "0.155952, 0.368861, 0.510427, 0.744263, 1.13595, 1.78604, 2.87267", \ - "0.198072, 0.432542, 0.576117, 0.810015, 1.20126, 1.85591, 2.93719", \ - "0.25277, 0.537185, 0.693093, 0.934972, 1.32784, 1.97887, 3.06614", \ - "0.312913, 0.692208, 0.881418, 1.15237, 1.56808, 2.22811, 3.31407", \ - "0.379764, 0.913413, 1.16109, 1.49984, 1.98659, 2.70448, 3.82033" \ + "0.0914098, 0.296252, 0.437584, 0.671162, 1.06158, 1.71234, 2.797", \ + "0.127788, 0.334385, 0.475866, 0.709982, 1.10019, 1.75245, 2.8369", \ + "0.156015, 0.368852, 0.510436, 0.744255, 1.13595, 1.78605, 2.87266", \ + "0.198072, 0.432543, 0.576121, 0.810022, 1.20127, 1.85199, 2.9372", \ + "0.25277, 0.537186, 0.693094, 0.934974, 1.32783, 1.97887, 3.06615", \ + "0.312913, 0.692209, 0.881419, 1.15238, 1.56808, 2.22811, 3.31409", \ + "0.379764, 0.913414, 1.16109, 1.49985, 1.9866, 2.70449, 3.82034" \ ); } rise_transition (TIMING_DELAY_7x7ds1) { index_1 ("0.0186, 0.0966, 0.174, 0.3294, 0.6408, 1.263, 2.5074"); index_2 ("0.001, 0.0234, 0.039, 0.0648, 0.108, 0.18, 0.3"); values ( \ - "0.0634958, 0.343694, 0.538222, 0.859831, 1.39819, 2.29408, 3.78995", \ - "0.066705, 0.343695, 0.538223, 0.860176, 1.3982, 2.29526, 3.78996", \ - "0.075389, 0.345547, 0.539573, 0.860177, 1.39922, 2.29527, 3.78997", \ - "0.0939564, 0.35816, 0.545111, 0.861301, 1.40024, 2.29896, 3.7905", \ - "0.131462, 0.402385, 0.579913, 0.88246, 1.40535, 2.29897, 3.79201", \ - "0.20413, 0.499618, 0.679335, 0.967736, 1.46334, 2.32059, 3.80804", \ - "0.333949, 0.683624, 0.875141, 1.17523, 1.65571, 2.46924, 3.87606" \ + "0.0634983, 0.343695, 0.538243, 0.859847, 1.39819, 2.29467, 3.78996", \ + "0.0667207, 0.344355, 0.538244, 0.860176, 1.39878, 2.29527, 3.78997", \ + "0.0754297, 0.345476, 0.539562, 0.860177, 1.39922, 2.29528, 3.78998", \ + "0.0939567, 0.358161, 0.544962, 0.861087, 1.40024, 2.29529, 3.79051", \ + "0.131462, 0.402385, 0.579924, 0.882462, 1.40526, 2.29556, 3.79202", \ + "0.20413, 0.499619, 0.679336, 0.967786, 1.46334, 2.32059, 3.80008", \ + "0.333949, 0.683626, 0.875142, 1.17523, 1.65571, 2.46925, 3.87607" \ ); } cell_fall (TIMING_DELAY_7x7ds1) { index_1 ("0.0186, 0.0966, 0.174, 0.3294, 0.6408, 1.263, 2.5074"); index_2 ("0.001, 0.0234, 0.039, 0.0648, 0.108, 0.18, 0.3"); values ( \ - "0.0739557, 0.231182, 0.337682, 0.51298, 0.805843, 1.29361, 2.10546", \ - "0.110629, 0.271401, 0.378014, 0.553429, 0.846451, 1.33392, 2.14617", \ - "0.13869, 0.309465, 0.416764, 0.592334, 0.885372, 1.37313, 2.18517", \ - "0.18418, 0.38003, 0.49271, 0.67087, 0.964447, 1.45232, 2.26541", \ - "0.246314, 0.494321, 0.622852, 0.816278, 1.11819, 1.60747, 2.41958", \ - "0.330797, 0.670024, 0.830115, 1.05865, 1.39546, 1.91014, 2.73045", \ - "0.447879, 0.91921, 1.14171, 1.43809, 1.84925, 2.4382, 3.32191" \ + "0.0739574, 0.231191, 0.337681, 0.512992, 0.805852, 1.29361, 2.10549", \ + "0.11063, 0.271401, 0.378023, 0.553412, 0.846363, 1.33393, 2.14619", \ + "0.138683, 0.309452, 0.41677, 0.592283, 0.885326, 1.37314, 2.18516", \ + "0.184181, 0.380031, 0.492712, 0.670879, 0.964445, 1.45233, 2.26547", \ + "0.246315, 0.494322, 0.622855, 0.816274, 1.1182, 1.60748, 2.4196", \ + "0.330798, 0.670026, 0.830118, 1.05866, 1.39547, 1.91015, 2.73047", \ + "0.44788, 0.919212, 1.14171, 1.43809, 1.84925, 2.43821, 3.32166" \ ); } fall_transition (TIMING_DELAY_7x7ds1) { index_1 ("0.0186, 0.0966, 0.174, 0.3294, 0.6408, 1.263, 2.5074"); index_2 ("0.001, 0.0234, 0.039, 0.0648, 0.108, 0.18, 0.3"); values ( \ - "0.0538295, 0.256218, 0.396229, 0.628296, 1.016, 1.66213, 2.73665", \ - "0.0597795, 0.256787, 0.396262, 0.628297, 1.01603, 1.66214, 2.73666", \ - "0.0698077, 0.262156, 0.399188, 0.632193, 1.01604, 1.66215, 2.73781", \ - "0.0906338, 0.283287, 0.414116, 0.636554, 1.01842, 1.66216, 2.73915", \ - "0.131095, 0.335393, 0.464271, 0.676091, 1.04057, 1.66906, 2.74435", \ - "0.198422, 0.44074, 0.573001, 0.782439, 1.13524, 1.73104, 2.76339", \ - "0.310224, 0.626651, 0.780861, 1.00412, 1.35439, 1.93547, 2.91783" \ + "0.05383, 0.25619, 0.396232, 0.6283, 1.01601, 1.66207, 2.73558", \ + "0.0597799, 0.256586, 0.396408, 0.628301, 1.01607, 1.66208, 2.73606", \ + "0.0697967, 0.262433, 0.399192, 0.629078, 1.01608, 1.66209, 2.73784", \ + "0.0906208, 0.283289, 0.414119, 0.636498, 1.01758, 1.6621, 2.73917", \ + "0.131096, 0.335395, 0.464278, 0.676045, 1.04058, 1.66904, 2.74437", \ + "0.198423, 0.440741, 0.573004, 0.782444, 1.13524, 1.73105, 2.76341", \ + "0.310225, 0.626654, 0.780863, 1.00412, 1.3544, 1.93547, 2.91761" \ ); } } @@ -5307,52 +5307,52 @@ library (sg13g2_stdcell_slow_1p08V_125C) { index_1 ("0.0186, 0.0966, 0.174, 0.3294, 0.6408, 1.263, 2.5074"); index_2 ("0.001, 0.0234, 0.039, 0.0648, 0.108, 0.18, 0.3"); values ( \ - "0.091409, 0.296287, 0.437541, 0.671122, 1.06158, 1.71238, 2.797", \ - "0.127783, 0.334461, 0.475851, 0.70998, 1.1004, 1.75244, 2.83684", \ - "0.155952, 0.368861, 0.510427, 0.744263, 1.13595, 1.78604, 2.87267", \ - "0.198072, 0.432542, 0.576117, 0.810015, 1.20126, 1.85591, 2.93719", \ - "0.25277, 0.537185, 0.693093, 0.934972, 1.32784, 1.97887, 3.06614", \ - "0.312913, 0.692208, 0.881418, 1.15237, 1.56808, 2.22811, 3.31407", \ - "0.379764, 0.913413, 1.16109, 1.49984, 1.98659, 2.70448, 3.82033" \ + "0.0914098, 0.296252, 0.437584, 0.671162, 1.06158, 1.71234, 2.797", \ + "0.127788, 0.334385, 0.475866, 0.709982, 1.10019, 1.75245, 2.8369", \ + "0.156015, 0.368852, 0.510436, 0.744255, 1.13595, 1.78605, 2.87266", \ + "0.198072, 0.432543, 0.576121, 0.810022, 1.20127, 1.85199, 2.9372", \ + "0.25277, 0.537186, 0.693094, 0.934974, 1.32783, 1.97887, 3.06615", \ + "0.312913, 0.692209, 0.881419, 1.15238, 1.56808, 2.22811, 3.31409", \ + "0.379764, 0.913414, 1.16109, 1.49985, 1.9866, 2.70449, 3.82034" \ ); } rise_transition (TIMING_DELAY_7x7ds1) { index_1 ("0.0186, 0.0966, 0.174, 0.3294, 0.6408, 1.263, 2.5074"); index_2 ("0.001, 0.0234, 0.039, 0.0648, 0.108, 0.18, 0.3"); values ( \ - "0.0634958, 0.343694, 0.538222, 0.859831, 1.39819, 2.29408, 3.78995", \ - "0.066705, 0.343695, 0.538223, 0.860176, 1.3982, 2.29526, 3.78996", \ - "0.075389, 0.345547, 0.539573, 0.860177, 1.39922, 2.29527, 3.78997", \ - "0.0939564, 0.35816, 0.545111, 0.861301, 1.40024, 2.29896, 3.7905", \ - "0.131462, 0.402385, 0.579913, 0.88246, 1.40535, 2.29897, 3.79201", \ - "0.20413, 0.499618, 0.679335, 0.967736, 1.46334, 2.32059, 3.80804", \ - "0.333949, 0.683624, 0.875141, 1.17523, 1.65571, 2.46924, 3.87606" \ + "0.0634983, 0.343695, 0.538243, 0.859847, 1.39819, 2.29467, 3.78996", \ + "0.0667207, 0.344355, 0.538244, 0.860176, 1.39878, 2.29527, 3.78997", \ + "0.0754297, 0.345476, 0.539562, 0.860177, 1.39922, 2.29528, 3.78998", \ + "0.0939567, 0.358161, 0.544962, 0.861087, 1.40024, 2.29529, 3.79051", \ + "0.131462, 0.402385, 0.579924, 0.882462, 1.40526, 2.29556, 3.79202", \ + "0.20413, 0.499619, 0.679336, 0.967786, 1.46334, 2.32059, 3.80008", \ + "0.333949, 0.683626, 0.875142, 1.17523, 1.65571, 2.46925, 3.87607" \ ); } cell_fall (TIMING_DELAY_7x7ds1) { index_1 ("0.0186, 0.0966, 0.174, 0.3294, 0.6408, 1.263, 2.5074"); index_2 ("0.001, 0.0234, 0.039, 0.0648, 0.108, 0.18, 0.3"); values ( \ - "0.0739557, 0.231182, 0.337682, 0.51298, 0.805843, 1.29361, 2.10546", \ - "0.110629, 0.271401, 0.378014, 0.553429, 0.846451, 1.33392, 2.14617", \ - "0.13869, 0.309465, 0.416764, 0.592334, 0.885372, 1.37313, 2.18517", \ - "0.18418, 0.38003, 0.49271, 0.67087, 0.964447, 1.45232, 2.26541", \ - "0.246314, 0.494321, 0.622852, 0.816278, 1.11819, 1.60747, 2.41958", \ - "0.330797, 0.670024, 0.830115, 1.05865, 1.39546, 1.91014, 2.73045", \ - "0.447879, 0.91921, 1.14171, 1.43809, 1.84925, 2.4382, 3.32191" \ + "0.0739574, 0.231191, 0.337681, 0.512992, 0.805852, 1.29361, 2.10549", \ + "0.11063, 0.271401, 0.378023, 0.553412, 0.846363, 1.33393, 2.14619", \ + "0.138683, 0.309452, 0.41677, 0.592283, 0.885326, 1.37314, 2.18516", \ + "0.184181, 0.380031, 0.492712, 0.670879, 0.964445, 1.45233, 2.26547", \ + "0.246315, 0.494322, 0.622855, 0.816274, 1.1182, 1.60748, 2.4196", \ + "0.330798, 0.670026, 0.830118, 1.05866, 1.39547, 1.91015, 2.73047", \ + "0.44788, 0.919212, 1.14171, 1.43809, 1.84925, 2.43821, 3.32166" \ ); } fall_transition (TIMING_DELAY_7x7ds1) { index_1 ("0.0186, 0.0966, 0.174, 0.3294, 0.6408, 1.263, 2.5074"); index_2 ("0.001, 0.0234, 0.039, 0.0648, 0.108, 0.18, 0.3"); values ( \ - "0.0538295, 0.256218, 0.396229, 0.628296, 1.016, 1.66213, 2.73665", \ - "0.0597795, 0.256787, 0.396262, 0.628297, 1.01603, 1.66214, 2.73666", \ - "0.0698077, 0.262156, 0.399188, 0.632193, 1.01604, 1.66215, 2.73781", \ - "0.0906338, 0.283287, 0.414116, 0.636554, 1.01842, 1.66216, 2.73915", \ - "0.131095, 0.335393, 0.464271, 0.676091, 1.04057, 1.66906, 2.74435", \ - "0.198422, 0.44074, 0.573001, 0.782439, 1.13524, 1.73104, 2.76339", \ - "0.310224, 0.626651, 0.780861, 1.00412, 1.35439, 1.93547, 2.91783" \ + "0.05383, 0.25619, 0.396232, 0.6283, 1.01601, 1.66207, 2.73558", \ + "0.0597799, 0.256586, 0.396408, 0.628301, 1.01607, 1.66208, 2.73606", \ + "0.0697967, 0.262433, 0.399192, 0.629078, 1.01608, 1.66209, 2.73784", \ + "0.0906208, 0.283289, 0.414119, 0.636498, 1.01758, 1.6621, 2.73917", \ + "0.131096, 0.335395, 0.464278, 0.676045, 1.04058, 1.66904, 2.74437", \ + "0.198423, 0.440741, 0.573004, 0.782444, 1.13524, 1.73105, 2.76341", \ + "0.310225, 0.626654, 0.780863, 1.00412, 1.3544, 1.93547, 2.91761" \ ); } } @@ -5366,52 +5366,52 @@ library (sg13g2_stdcell_slow_1p08V_125C) { index_1 ("0.0186, 0.0966, 0.174, 0.3294, 0.6408, 1.263, 2.5074"); index_2 ("0.001, 0.0234, 0.039, 0.0648, 0.108, 0.18, 0.3"); values ( \ - "0.0850602, 0.29211, 0.433911, 0.668354, 1.05971, 1.71206, 2.79922", \ - "0.118216, 0.327543, 0.469721, 0.704544, 1.09603, 1.74897, 2.83609", \ - "0.14728, 0.365812, 0.507978, 0.742402, 1.13472, 1.78717, 2.876", \ - "0.190818, 0.439822, 0.58417, 0.818255, 1.21008, 1.86238, 2.9498", \ - "0.248829, 0.55959, 0.721133, 0.965477, 1.35766, 2.0085, 3.09697", \ - "0.319979, 0.737519, 0.94035, 1.2257, 1.64928, 2.30935, 3.39243", \ - "0.412751, 0.978518, 1.25206, 1.62209, 2.13936, 2.87943, 4.00364" \ + "0.0851044, 0.292101, 0.433985, 0.668349, 1.0598, 1.71207, 2.79925", \ + "0.118219, 0.327569, 0.469814, 0.704551, 1.09602, 1.74952, 2.83598", \ + "0.147271, 0.365834, 0.50799, 0.7426, 1.1347, 1.78718, 2.876", \ + "0.190818, 0.439823, 0.584171, 0.818256, 1.21009, 1.86229, 2.9498", \ + "0.248829, 0.559591, 0.721134, 0.965478, 1.35767, 2.00849, 3.09576", \ + "0.319979, 0.737519, 0.940351, 1.2257, 1.64928, 2.30937, 3.39245", \ + "0.412752, 0.978519, 1.25206, 1.62209, 2.13936, 2.87943, 4.00365" \ ); } rise_transition (TIMING_DELAY_7x7ds1) { index_1 ("0.0186, 0.0966, 0.174, 0.3294, 0.6408, 1.263, 2.5074"); index_2 ("0.001, 0.0234, 0.039, 0.0648, 0.108, 0.18, 0.3"); values ( \ - "0.0745406, 0.35605, 0.551901, 0.874254, 1.41331, 2.31341, 3.81053", \ - "0.0808624, 0.357081, 0.551902, 0.874255, 1.41438, 2.31463, 3.81228", \ - "0.0958529, 0.359722, 0.553049, 0.875242, 1.41439, 2.31464, 3.8127", \ - "0.12464, 0.380694, 0.562822, 0.876625, 1.41495, 2.31465, 3.81271", \ - "0.172666, 0.448898, 0.618351, 0.910402, 1.42519, 2.31466, 3.81324", \ - "0.248329, 0.581702, 0.75849, 1.03674, 1.51266, 2.35211, 3.82433", \ - "0.367418, 0.810651, 1.01891, 1.32178, 1.79041, 2.57412, 3.94256" \ + "0.0744861, 0.356047, 0.551903, 0.874256, 1.41336, 2.31341, 3.81054", \ + "0.0808772, 0.357237, 0.551904, 0.874257, 1.41438, 2.31439, 3.81213", \ + "0.095866, 0.359738, 0.553094, 0.874258, 1.41439, 2.3144, 3.81271", \ + "0.12464, 0.380694, 0.562823, 0.87663, 1.41495, 2.31441, 3.81272", \ + "0.172666, 0.448899, 0.618352, 0.910403, 1.42516, 2.31618, 3.81273", \ + "0.248329, 0.581703, 0.758491, 1.03674, 1.51258, 2.35203, 3.82795", \ + "0.367418, 0.810652, 1.01891, 1.32292, 1.79001, 2.57412, 3.94257" \ ); } cell_fall (TIMING_DELAY_7x7ds1) { index_1 ("0.0186, 0.0966, 0.174, 0.3294, 0.6408, 1.263, 2.5074"); index_2 ("0.001, 0.0234, 0.039, 0.0648, 0.108, 0.18, 0.3"); values ( \ - "0.0588535, 0.212356, 0.31833, 0.493111, 0.785968, 1.27381, 2.08656", \ - "0.0917363, 0.253276, 0.359482, 0.534852, 0.827744, 1.31573, 2.12868", \ - "0.115268, 0.290773, 0.398073, 0.573749, 0.866653, 1.35564, 2.16763", \ - "0.150768, 0.359152, 0.472962, 0.651793, 0.945715, 1.43408, 2.24708", \ - "0.196544, 0.46821, 0.599908, 0.795574, 1.09876, 1.58896, 2.40212", \ - "0.256109, 0.634552, 0.800876, 1.0336, 1.37357, 1.89086, 2.71273", \ - "0.336351, 0.867623, 1.10029, 1.4054, 1.82219, 2.41585, 3.3034" \ + "0.0588513, 0.212329, 0.318328, 0.493114, 0.785972, 1.27365, 2.08656", \ + "0.0917363, 0.25321, 0.359484, 0.534739, 0.827756, 1.31572, 2.12867", \ + "0.115268, 0.290792, 0.398071, 0.573631, 0.866636, 1.35562, 2.1676", \ + "0.150768, 0.35915, 0.47296, 0.651813, 0.945708, 1.43409, 2.24858", \ + "0.196544, 0.468208, 0.599906, 0.79557, 1.09875, 1.58894, 2.40211", \ + "0.256108, 0.63455, 0.800873, 1.03359, 1.37356, 1.89085, 2.71268", \ + "0.33635, 0.867621, 1.10029, 1.4054, 1.82218, 2.41584, 3.30338" \ ); } fall_transition (TIMING_DELAY_7x7ds1) { index_1 ("0.0186, 0.0966, 0.174, 0.3294, 0.6408, 1.263, 2.5074"); index_2 ("0.001, 0.0234, 0.039, 0.0648, 0.108, 0.18, 0.3"); values ( \ - "0.0491742, 0.249991, 0.389657, 0.620537, 1.00748, 1.65154, 2.72768", \ - "0.0583327, 0.250803, 0.389658, 0.620538, 1.00749, 1.65168, 2.72769", \ - "0.0710187, 0.25721, 0.392604, 0.621088, 1.0075, 1.65251, 2.7277", \ - "0.0960564, 0.279721, 0.409083, 0.629932, 1.00995, 1.65252, 2.72771", \ - "0.142704, 0.334653, 0.46076, 0.670963, 1.03428, 1.65942, 2.72772", \ - "0.222681, 0.444201, 0.573113, 0.780172, 1.12957, 1.72389, 2.75356", \ - "0.353629, 0.633939, 0.784715, 1.005, 1.35097, 1.92973, 2.91073" \ + "0.0491738, 0.250016, 0.389654, 0.620529, 1.00747, 1.65146, 2.7265", \ + "0.058335, 0.250787, 0.3898, 0.620591, 1.00749, 1.65166, 2.72733", \ + "0.0710176, 0.257179, 0.392542, 0.623406, 1.0075, 1.6525, 2.72734", \ + "0.096056, 0.279719, 0.40908, 0.630026, 1.00994, 1.65251, 2.72752", \ + "0.142703, 0.334651, 0.460764, 0.670956, 1.03427, 1.66028, 2.72753", \ + "0.222681, 0.444199, 0.57311, 0.780167, 1.12956, 1.72387, 2.75354", \ + "0.353629, 0.63393, 0.784711, 1.005, 1.35096, 1.92971, 2.91071" \ ); } } @@ -5425,52 +5425,52 @@ library (sg13g2_stdcell_slow_1p08V_125C) { index_1 ("0.0186, 0.0966, 0.174, 0.3294, 0.6408, 1.263, 2.5074"); index_2 ("0.001, 0.0234, 0.039, 0.0648, 0.108, 0.18, 0.3"); values ( \ - "0.0719485, 0.277811, 0.419159, 0.652692, 1.04328, 1.69405, 2.77872", \ - "0.103688, 0.313216, 0.454924, 0.688843, 1.07958, 1.7307, 2.81631", \ - "0.129902, 0.351512, 0.493154, 0.727047, 1.11818, 1.76921, 2.85558", \ - "0.168106, 0.42488, 0.569368, 0.802723, 1.19356, 1.84831, 2.92938", \ - "0.217912, 0.542034, 0.705033, 0.949674, 1.34108, 1.99071, 3.07556", \ - "0.277838, 0.714448, 0.920564, 1.20814, 1.63218, 2.2914, 3.37211", \ - "0.354575, 0.947076, 1.2259, 1.59961, 2.11894, 2.8602, 3.98309" \ + "0.0719638, 0.277779, 0.419164, 0.652709, 1.04315, 1.69402, 2.77874", \ + "0.103714, 0.313254, 0.454865, 0.688858, 1.07958, 1.73158, 2.81513", \ + "0.129894, 0.351503, 0.493148, 0.72705, 1.11818, 1.76922, 2.85555", \ + "0.168106, 0.424879, 0.569367, 0.802708, 1.19355, 1.84423, 2.9293", \ + "0.217912, 0.542033, 0.705032, 0.94966, 1.34108, 1.99058, 3.07556", \ + "0.277838, 0.714447, 0.920563, 1.20814, 1.63218, 2.29139, 3.37206", \ + "0.354575, 0.947075, 1.22589, 1.59961, 2.11893, 2.86019, 3.98308" \ ); } rise_transition (TIMING_DELAY_7x7ds1) { index_1 ("0.0186, 0.0966, 0.174, 0.3294, 0.6408, 1.263, 2.5074"); index_2 ("0.001, 0.0234, 0.039, 0.0648, 0.108, 0.18, 0.3"); values ( \ - "0.0639976, 0.344113, 0.538898, 0.86083, 1.39908, 2.29673, 3.79065", \ - "0.0725719, 0.345249, 0.539272, 0.860831, 1.39946, 2.29678, 3.79066", \ - "0.0885402, 0.347993, 0.539628, 0.860832, 1.39947, 2.29679, 3.79112", \ - "0.117309, 0.370777, 0.551312, 0.863135, 1.40059, 2.29952, 3.79124", \ - "0.164408, 0.440211, 0.608636, 0.898743, 1.41066, 2.29953, 3.79125", \ - "0.237033, 0.57326, 0.750326, 1.02622, 1.50052, 2.33592, 3.81164", \ - "0.350757, 0.799485, 1.00743, 1.31227, 1.78161, 2.55998, 3.92356" \ + "0.0640501, 0.344271, 0.539095, 0.860831, 1.39816, 2.29579, 3.79064", \ + "0.072554, 0.345251, 0.539248, 0.860832, 1.39946, 2.29622, 3.79092", \ + "0.0886372, 0.347941, 0.539526, 0.860833, 1.39947, 2.29623, 3.79112", \ + "0.117309, 0.370776, 0.55131, 0.863169, 1.40059, 2.29624, 3.79123", \ + "0.164407, 0.44021, 0.608635, 0.898204, 1.41065, 2.29636, 3.79124", \ + "0.237033, 0.573244, 0.750325, 1.02621, 1.50051, 2.33591, 3.81821", \ + "0.350756, 0.799485, 1.00742, 1.31227, 1.78161, 2.55997, 3.92355" \ ); } cell_fall (TIMING_DELAY_7x7ds1) { index_1 ("0.0186, 0.0966, 0.174, 0.3294, 0.6408, 1.263, 2.5074"); index_2 ("0.001, 0.0234, 0.039, 0.0648, 0.108, 0.18, 0.3"); values ( \ - "0.0583679, 0.211542, 0.317209, 0.491596, 0.783805, 1.27079, 2.08289", \ - "0.0911534, 0.252455, 0.358374, 0.533159, 0.825634, 1.31277, 2.12466", \ - "0.114462, 0.289955, 0.397041, 0.572071, 0.864612, 1.35273, 2.16382", \ - "0.149739, 0.358215, 0.471859, 0.65036, 0.943645, 1.43132, 2.24457", \ - "0.194765, 0.466935, 0.598568, 0.793808, 1.09659, 1.58608, 2.39841", \ - "0.252465, 0.632414, 0.799051, 1.03149, 1.3711, 1.88782, 2.70876", \ - "0.329467, 0.863225, 1.09672, 1.40241, 1.81895, 2.41283, 3.29903" \ + "0.058378, 0.211496, 0.317148, 0.491643, 0.783791, 1.27079, 2.0828", \ + "0.0911538, 0.252428, 0.358335, 0.533121, 0.825626, 1.31274, 2.12464", \ + "0.11446, 0.289945, 0.396994, 0.572093, 0.864556, 1.35254, 2.16378", \ + "0.149738, 0.358213, 0.471857, 0.650379, 0.943639, 1.43131, 2.24461", \ + "0.194813, 0.466933, 0.598565, 0.793804, 1.09666, 1.58606, 2.39839", \ + "0.252464, 0.632412, 0.799048, 1.03148, 1.37109, 1.88771, 2.70862", \ + "0.329466, 0.863222, 1.09672, 1.40281, 1.81894, 2.41282, 3.29901" \ ); } fall_transition (TIMING_DELAY_7x7ds1) { index_1 ("0.0186, 0.0966, 0.174, 0.3294, 0.6408, 1.263, 2.5074"); index_2 ("0.001, 0.0234, 0.039, 0.0648, 0.108, 0.18, 0.3"); values ( \ - "0.0362332, 0.236929, 0.376636, 0.607629, 0.995099, 1.63913, 2.71608", \ - "0.0442818, 0.237735, 0.377126, 0.60763, 0.995158, 1.64024, 2.71609", \ - "0.0548842, 0.244078, 0.379523, 0.609374, 0.995159, 1.64111, 2.7161", \ - "0.0761407, 0.266203, 0.396216, 0.616854, 0.996882, 1.64112, 2.71611", \ - "0.115751, 0.320616, 0.44714, 0.658019, 1.02145, 1.64798, 2.71998", \ - "0.185176, 0.427034, 0.558248, 0.765621, 1.11577, 1.71107, 2.74172", \ - "0.297958, 0.614028, 0.770672, 0.990661, 1.33813, 1.91967, 2.89734" \ + "0.0362328, 0.236732, 0.376783, 0.607981, 0.994593, 1.63921, 2.71606", \ + "0.0442843, 0.237567, 0.376784, 0.607982, 0.995151, 1.64022, 2.71607", \ + "0.0548845, 0.243869, 0.37942, 0.609332, 0.995152, 1.64091, 2.71608", \ + "0.0761404, 0.266201, 0.396213, 0.617436, 0.996875, 1.64092, 2.71609", \ + "0.115668, 0.320614, 0.447153, 0.658014, 1.02167, 1.64794, 2.71996", \ + "0.185175, 0.427032, 0.558246, 0.765616, 1.11577, 1.71062, 2.74159", \ + "0.297957, 0.614026, 0.770668, 0.989548, 1.33812, 1.91966, 2.8973" \ ); } } @@ -5482,52 +5482,52 @@ library (sg13g2_stdcell_slow_1p08V_125C) { index_1 ("0.0186, 0.0966, 0.174, 0.3294, 0.6408, 1.263, 2.5074"); index_2 ("0.001, 0.0234, 0.039, 0.0648, 0.108, 0.18, 0.3"); values ( \ - "0.0850602, 0.29211, 0.433911, 0.668354, 1.05971, 1.71206, 2.79922", \ - "0.118216, 0.327543, 0.469721, 0.704544, 1.09603, 1.74897, 2.83609", \ - "0.14728, 0.365812, 0.507978, 0.742402, 1.13472, 1.78717, 2.876", \ - "0.190818, 0.439822, 0.58417, 0.818255, 1.21008, 1.86238, 2.9498", \ - "0.248829, 0.55959, 0.721133, 0.965477, 1.35766, 2.0085, 3.09697", \ - "0.319979, 0.737519, 0.94035, 1.2257, 1.64928, 2.30935, 3.39243", \ - "0.412751, 0.978518, 1.25206, 1.62209, 2.13936, 2.87943, 4.00364" \ + "0.0851044, 0.292101, 0.433985, 0.668349, 1.0598, 1.71207, 2.79925", \ + "0.118219, 0.327569, 0.469814, 0.704551, 1.09602, 1.74952, 2.83598", \ + "0.147271, 0.365834, 0.50799, 0.7426, 1.1347, 1.78718, 2.876", \ + "0.190818, 0.439823, 0.584171, 0.818256, 1.21009, 1.86229, 2.9498", \ + "0.248829, 0.559591, 0.721134, 0.965478, 1.35767, 2.00849, 3.09576", \ + "0.319979, 0.737519, 0.940351, 1.2257, 1.64928, 2.30937, 3.39245", \ + "0.412752, 0.978519, 1.25206, 1.62209, 2.13936, 2.87943, 4.00365" \ ); } rise_transition (TIMING_DELAY_7x7ds1) { index_1 ("0.0186, 0.0966, 0.174, 0.3294, 0.6408, 1.263, 2.5074"); index_2 ("0.001, 0.0234, 0.039, 0.0648, 0.108, 0.18, 0.3"); values ( \ - "0.0745406, 0.35605, 0.551901, 0.874254, 1.41331, 2.31341, 3.81053", \ - "0.0808624, 0.357081, 0.551902, 0.874255, 1.41438, 2.31463, 3.81228", \ - "0.0958529, 0.359722, 0.553049, 0.875242, 1.41439, 2.31464, 3.8127", \ - "0.12464, 0.380694, 0.562822, 0.876625, 1.41495, 2.31465, 3.81271", \ - "0.172666, 0.448898, 0.618351, 0.910402, 1.42519, 2.31466, 3.81324", \ - "0.248329, 0.581702, 0.75849, 1.03674, 1.51266, 2.35211, 3.82433", \ - "0.367418, 0.810651, 1.01891, 1.32178, 1.79041, 2.57412, 3.94256" \ + "0.0744861, 0.356047, 0.551903, 0.874256, 1.41336, 2.31341, 3.81054", \ + "0.0808772, 0.357237, 0.551904, 0.874257, 1.41438, 2.31439, 3.81213", \ + "0.095866, 0.359738, 0.553094, 0.874258, 1.41439, 2.3144, 3.81271", \ + "0.12464, 0.380694, 0.562823, 0.87663, 1.41495, 2.31441, 3.81272", \ + "0.172666, 0.448899, 0.618352, 0.910403, 1.42516, 2.31618, 3.81273", \ + "0.248329, 0.581703, 0.758491, 1.03674, 1.51258, 2.35203, 3.82795", \ + "0.367418, 0.810652, 1.01891, 1.32292, 1.79001, 2.57412, 3.94257" \ ); } cell_fall (TIMING_DELAY_7x7ds1) { index_1 ("0.0186, 0.0966, 0.174, 0.3294, 0.6408, 1.263, 2.5074"); index_2 ("0.001, 0.0234, 0.039, 0.0648, 0.108, 0.18, 0.3"); values ( \ - "0.0588535, 0.212356, 0.31833, 0.493111, 0.785968, 1.27381, 2.08656", \ - "0.0917363, 0.253276, 0.359482, 0.534852, 0.827744, 1.31573, 2.12868", \ - "0.115268, 0.290773, 0.398073, 0.573749, 0.866653, 1.35564, 2.16763", \ - "0.150768, 0.359152, 0.472962, 0.651793, 0.945715, 1.43408, 2.24708", \ - "0.196544, 0.46821, 0.599908, 0.795574, 1.09876, 1.58896, 2.40212", \ - "0.256109, 0.634552, 0.800876, 1.0336, 1.37357, 1.89086, 2.71273", \ - "0.336351, 0.867623, 1.10029, 1.4054, 1.82219, 2.41585, 3.3034" \ + "0.0588513, 0.212329, 0.318328, 0.493114, 0.785972, 1.27365, 2.08656", \ + "0.0917363, 0.25321, 0.359484, 0.534739, 0.827756, 1.31572, 2.12867", \ + "0.115268, 0.290792, 0.398071, 0.573631, 0.866636, 1.35562, 2.1676", \ + "0.150768, 0.35915, 0.47296, 0.651813, 0.945708, 1.43409, 2.24858", \ + "0.196544, 0.468208, 0.599906, 0.79557, 1.09875, 1.58894, 2.40211", \ + "0.256108, 0.63455, 0.800873, 1.03359, 1.37356, 1.89085, 2.71268", \ + "0.33635, 0.867621, 1.10029, 1.4054, 1.82218, 2.41584, 3.30338" \ ); } fall_transition (TIMING_DELAY_7x7ds1) { index_1 ("0.0186, 0.0966, 0.174, 0.3294, 0.6408, 1.263, 2.5074"); index_2 ("0.001, 0.0234, 0.039, 0.0648, 0.108, 0.18, 0.3"); values ( \ - "0.0491742, 0.249991, 0.389657, 0.620537, 1.00748, 1.65154, 2.72768", \ - "0.0583327, 0.250803, 0.389658, 0.620538, 1.00749, 1.65168, 2.72769", \ - "0.0710187, 0.25721, 0.392604, 0.621088, 1.0075, 1.65251, 2.7277", \ - "0.0960564, 0.279721, 0.409083, 0.629932, 1.00995, 1.65252, 2.72771", \ - "0.142704, 0.334653, 0.46076, 0.670963, 1.03428, 1.65942, 2.72772", \ - "0.222681, 0.444201, 0.573113, 0.780172, 1.12957, 1.72389, 2.75356", \ - "0.353629, 0.633939, 0.784715, 1.005, 1.35097, 1.92973, 2.91073" \ + "0.0491738, 0.250016, 0.389654, 0.620529, 1.00747, 1.65146, 2.7265", \ + "0.058335, 0.250787, 0.3898, 0.620591, 1.00749, 1.65166, 2.72733", \ + "0.0710176, 0.257179, 0.392542, 0.623406, 1.0075, 1.6525, 2.72734", \ + "0.096056, 0.279719, 0.40908, 0.630026, 1.00994, 1.65251, 2.72752", \ + "0.142703, 0.334651, 0.460764, 0.670956, 1.03427, 1.66028, 2.72753", \ + "0.222681, 0.444199, 0.57311, 0.780167, 1.12956, 1.72387, 2.75354", \ + "0.353629, 0.63393, 0.784711, 1.005, 1.35096, 1.92971, 2.91071" \ ); } } @@ -5541,52 +5541,52 @@ library (sg13g2_stdcell_slow_1p08V_125C) { index_1 ("0.0186, 0.0966, 0.174, 0.3294, 0.6408, 1.263, 2.5074"); index_2 ("0.001, 0.0234, 0.039, 0.0648, 0.108, 0.18, 0.3"); values ( \ - "0.0733945, 0.280293, 0.421675, 0.655356, 1.04569, 1.69656, 2.78126", \ - "0.104277, 0.315215, 0.457127, 0.691717, 1.08237, 1.73351, 2.81905", \ - "0.130288, 0.352754, 0.494972, 0.728887, 1.12057, 1.7718, 2.8582", \ - "0.167926, 0.425827, 0.570638, 0.804532, 1.19575, 1.84663, 2.93341", \ - "0.217287, 0.542498, 0.705703, 0.951006, 1.34277, 1.99288, 3.07785", \ - "0.276208, 0.714271, 0.920702, 1.20894, 1.63315, 2.29285, 3.37421", \ - "0.350934, 0.945589, 1.22482, 1.59936, 2.11929, 2.86114, 3.9846" \ + "0.0733978, 0.280291, 0.421709, 0.655359, 1.0457, 1.69655, 2.78124", \ + "0.104229, 0.315222, 0.457114, 0.691723, 1.08237, 1.73369, 2.81797", \ + "0.130289, 0.352767, 0.494941, 0.728968, 1.12052, 1.77182, 2.85821", \ + "0.167926, 0.425828, 0.570638, 0.804533, 1.19576, 1.84669, 2.93342", \ + "0.217288, 0.542498, 0.705704, 0.951006, 1.34279, 1.99288, 3.07798", \ + "0.276208, 0.714271, 0.920703, 1.20895, 1.63315, 2.29287, 3.37403", \ + "0.350935, 0.94559, 1.22482, 1.59936, 2.11929, 2.86114, 3.98457" \ ); } rise_transition (TIMING_DELAY_7x7ds1) { index_1 ("0.0186, 0.0966, 0.174, 0.3294, 0.6408, 1.263, 2.5074"); index_2 ("0.001, 0.0234, 0.039, 0.0648, 0.108, 0.18, 0.3"); values ( \ - "0.0635214, 0.343674, 0.538273, 0.859842, 1.39753, 2.29505, 3.78995", \ - "0.0716616, 0.345228, 0.538274, 0.860471, 1.39809, 2.29506, 3.78996", \ - "0.0876399, 0.34708, 0.538803, 0.860472, 1.3981, 2.29562, 3.79057", \ - "0.11673, 0.369593, 0.550278, 0.861921, 1.4, 2.29582, 3.79058", \ - "0.164383, 0.439129, 0.607504, 0.897202, 1.41, 2.29583, 3.79059", \ - "0.238147, 0.573247, 0.749361, 1.02618, 1.49938, 2.33499, 3.80488", \ - "0.358139, 0.801284, 1.00869, 1.31159, 1.78051, 2.55792, 3.92203" \ + "0.063523, 0.343682, 0.538471, 0.859844, 1.39753, 2.29468, 3.78996", \ + "0.0717293, 0.345238, 0.538472, 0.860472, 1.3981, 2.29469, 3.78997", \ + "0.0877006, 0.347088, 0.538809, 0.860481, 1.39811, 2.29564, 3.79058", \ + "0.11673, 0.369594, 0.550278, 0.861922, 1.40001, 2.29565, 3.79059", \ + "0.164383, 0.439131, 0.607505, 0.89706, 1.40983, 2.29566, 3.7906", \ + "0.238148, 0.573248, 0.749362, 1.02618, 1.49939, 2.33499, 3.81428", \ + "0.358139, 0.801284, 1.0087, 1.31159, 1.78051, 2.558, 3.92237" \ ); } cell_fall (TIMING_DELAY_7x7ds1) { index_1 ("0.0186, 0.0966, 0.174, 0.3294, 0.6408, 1.263, 2.5074"); index_2 ("0.001, 0.0234, 0.039, 0.0648, 0.108, 0.18, 0.3"); values ( \ - "0.0514663, 0.205908, 0.311786, 0.486703, 0.779612, 1.26745, 2.08018", \ - "0.0825932, 0.248269, 0.354478, 0.529742, 0.822822, 1.31069, 2.12363", \ - "0.103833, 0.289476, 0.396807, 0.572154, 0.86512, 1.35361, 2.16597", \ - "0.13527, 0.363219, 0.479285, 0.658267, 0.951519, 1.43913, 2.25338", \ - "0.176744, 0.476214, 0.6158, 0.817443, 1.12115, 1.60938, 2.42094", \ - "0.230616, 0.639304, 0.821177, 1.07073, 1.42423, 1.9468, 2.76673", \ - "0.301976, 0.860272, 1.11347, 1.44554, 1.89486, 2.51817, 3.42322" \ + "0.0514689, 0.205904, 0.311744, 0.48672, 0.779614, 1.26743, 2.08002", \ + "0.0825694, 0.248271, 0.354503, 0.52972, 0.822781, 1.31071, 2.12342", \ + "0.103825, 0.289486, 0.396812, 0.572128, 0.865122, 1.35317, 2.16595", \ + "0.135232, 0.363217, 0.479283, 0.658326, 0.95155, 1.43927, 2.25227", \ + "0.176743, 0.476213, 0.615798, 0.817439, 1.12113, 1.60936, 2.42087", \ + "0.230616, 0.639179, 0.821175, 1.07065, 1.42422, 1.94679, 2.76671", \ + "0.301975, 0.860269, 1.11347, 1.44553, 1.89486, 2.51816, 3.42337" \ ); } fall_transition (TIMING_DELAY_7x7ds1) { index_1 ("0.0186, 0.0966, 0.174, 0.3294, 0.6408, 1.263, 2.5074"); index_2 ("0.001, 0.0234, 0.039, 0.0648, 0.108, 0.18, 0.3"); values ( \ - "0.0493684, 0.250013, 0.389529, 0.620724, 1.00755, 1.65189, 2.72568", \ - "0.0658307, 0.251387, 0.389589, 0.620725, 1.00756, 1.6519, 2.72572", \ - "0.084396, 0.261583, 0.394355, 0.621455, 1.00757, 1.6523, 2.72638", \ - "0.118176, 0.295376, 0.419454, 0.634915, 1.01069, 1.65231, 2.72729", \ - "0.171786, 0.371615, 0.493941, 0.695095, 1.04685, 1.66279, 2.72739", \ - "0.256213, 0.509411, 0.642543, 0.847514, 1.18381, 1.75672, 2.76623", \ - "0.393927, 0.731149, 0.897695, 1.1353, 1.48605, 2.04906, 2.98967" \ + "0.0493617, 0.25001, 0.389533, 0.620718, 1.00754, 1.65187, 2.72725", \ + "0.0658375, 0.25138, 0.389583, 0.620719, 1.00755, 1.65188, 2.72726", \ + "0.0843828, 0.261572, 0.394342, 0.623851, 1.00756, 1.65189, 2.72727", \ + "0.118231, 0.295374, 0.419451, 0.634915, 1.0111, 1.6519, 2.72804", \ + "0.171785, 0.371612, 0.493938, 0.695091, 1.04685, 1.66278, 2.72805", \ + "0.256213, 0.509387, 0.642541, 0.847543, 1.1838, 1.75639, 2.7662", \ + "0.393926, 0.731146, 0.89769, 1.13529, 1.48604, 2.04905, 2.99033" \ ); } } @@ -5600,52 +5600,52 @@ library (sg13g2_stdcell_slow_1p08V_125C) { index_1 ("0.0186, 0.0966, 0.174, 0.3294, 0.6408, 1.263, 2.5074"); index_2 ("0.001, 0.0234, 0.039, 0.0648, 0.108, 0.18, 0.3"); values ( \ - "0.0601801, 0.26733, 0.408683, 0.642535, 1.03369, 1.6858, 2.77281", \ - "0.0893143, 0.302014, 0.444024, 0.678614, 1.07024, 1.72363, 2.80991", \ - "0.111382, 0.339604, 0.481898, 0.71637, 1.10855, 1.76105, 2.84983", \ - "0.14323, 0.41181, 0.557445, 0.791804, 1.1833, 1.83591, 2.92435", \ - "0.182553, 0.52617, 0.691423, 0.938024, 1.33083, 1.98183, 3.06953", \ - "0.229072, 0.692298, 0.903003, 1.19409, 1.6205, 2.28224, 3.36539", \ - "0.286716, 0.915339, 1.20095, 1.58015, 2.1045, 2.84955, 3.97607" \ + "0.0601661, 0.267333, 0.408695, 0.642537, 1.03368, 1.68581, 2.7728", \ + "0.0892772, 0.302014, 0.444062, 0.678611, 1.07024, 1.72286, 2.81062", \ + "0.111382, 0.339598, 0.481918, 0.716353, 1.10853, 1.76092, 2.84982", \ + "0.14323, 0.41181, 0.557444, 0.791823, 1.18329, 1.83588, 2.92492", \ + "0.182553, 0.526169, 0.691422, 0.938019, 1.33083, 1.98241, 3.0709", \ + "0.229072, 0.692297, 0.903002, 1.19408, 1.6205, 2.28222, 3.36563", \ + "0.286716, 0.915339, 1.20094, 1.58015, 2.10449, 2.84954, 3.97607" \ ); } rise_transition (TIMING_DELAY_7x7ds1) { index_1 ("0.0186, 0.0966, 0.174, 0.3294, 0.6408, 1.263, 2.5074"); index_2 ("0.001, 0.0234, 0.039, 0.0648, 0.108, 0.18, 0.3"); values ( \ - "0.0532633, 0.333144, 0.528037, 0.850157, 1.38926, 2.28797, 3.78579", \ - "0.0645433, 0.333145, 0.528289, 0.850158, 1.38948, 2.288, 3.78664", \ - "0.0815824, 0.337376, 0.528628, 0.850159, 1.38949, 2.2883, 3.78665", \ - "0.110418, 0.361297, 0.541585, 0.852833, 1.39407, 2.28831, 3.78666", \ - "0.158209, 0.432258, 0.599999, 0.888796, 1.40123, 2.28839, 3.78667", \ - "0.228985, 0.567352, 0.743266, 1.01817, 1.49261, 2.32801, 3.8051", \ - "0.346591, 0.79446, 1.00155, 1.30649, 1.77182, 2.55297, 3.91914" \ + "0.0532687, 0.333157, 0.528034, 0.850155, 1.38926, 2.28796, 3.78578", \ + "0.0645431, 0.333158, 0.528333, 0.850156, 1.38948, 2.28797, 3.78579", \ + "0.0815761, 0.337516, 0.528629, 0.850157, 1.38949, 2.28829, 3.78623", \ + "0.110418, 0.361296, 0.541591, 0.85265, 1.39406, 2.2883, 3.78624", \ + "0.158208, 0.432258, 0.599998, 0.888781, 1.40122, 2.2901, 3.78749", \ + "0.228985, 0.567351, 0.743266, 1.01817, 1.4926, 2.328, 3.80864", \ + "0.346591, 0.794459, 1.00155, 1.30649, 1.77185, 2.55244, 3.91913" \ ); } cell_fall (TIMING_DELAY_7x7ds1) { index_1 ("0.0186, 0.0966, 0.174, 0.3294, 0.6408, 1.263, 2.5074"); index_2 ("0.001, 0.0234, 0.039, 0.0648, 0.108, 0.18, 0.3"); values ( \ - "0.0510213, 0.205049, 0.310683, 0.485231, 0.777571, 1.2645, 2.07618", \ - "0.0819835, 0.247482, 0.353353, 0.528058, 0.820809, 1.30782, 2.12007", \ - "0.102849, 0.288648, 0.395758, 0.570647, 0.863087, 1.35024, 2.16211", \ - "0.133892, 0.362209, 0.478168, 0.656894, 0.94957, 1.43661, 2.24944", \ - "0.173857, 0.474669, 0.614314, 0.815738, 1.11881, 1.60658, 2.41718", \ - "0.225989, 0.636595, 0.818838, 1.06815, 1.42151, 1.9437, 2.76232", \ - "0.29298, 0.855319, 1.1087, 1.4415, 1.89093, 2.51407, 3.41869" \ + "0.0510048, 0.205054, 0.310685, 0.485366, 0.777573, 1.26449, 2.07617", \ + "0.0819973, 0.247478, 0.353359, 0.52822, 0.820745, 1.30779, 2.12006", \ + "0.102855, 0.288673, 0.395783, 0.570709, 0.863126, 1.35033, 2.16209", \ + "0.133892, 0.362208, 0.478166, 0.656821, 0.949527, 1.43658, 2.24945", \ + "0.173857, 0.474668, 0.614312, 0.815735, 1.1188, 1.60656, 2.41688", \ + "0.225988, 0.636593, 0.818835, 1.06814, 1.42151, 1.94369, 2.7623", \ + "0.29298, 0.855317, 1.1087, 1.44149, 1.89092, 2.51406, 3.41877" \ ); } fall_transition (TIMING_DELAY_7x7ds1) { index_1 ("0.0186, 0.0966, 0.174, 0.3294, 0.6408, 1.263, 2.5074"); index_2 ("0.001, 0.0234, 0.039, 0.0648, 0.108, 0.18, 0.3"); values ( \ - "0.0364263, 0.23691, 0.376548, 0.607316, 0.995199, 1.63952, 2.71433", \ - "0.0508009, 0.238301, 0.377828, 0.607748, 0.9952, 1.63953, 2.71605", \ - "0.0662177, 0.248348, 0.381341, 0.611382, 0.995201, 1.63957, 2.71606", \ - "0.0939332, 0.281768, 0.406252, 0.621757, 0.998806, 1.64148, 2.71607", \ - "0.138034, 0.356168, 0.480425, 0.682172, 1.03342, 1.65009, 2.7224", \ - "0.209674, 0.489847, 0.628379, 0.833351, 1.17197, 1.74382, 2.75231", \ - "0.325573, 0.70465, 0.878111, 1.12117, 1.47079, 2.03585, 2.97883" \ + "0.0364295, 0.236908, 0.376544, 0.608026, 0.995191, 1.63947, 2.71431", \ + "0.0507935, 0.238299, 0.378887, 0.608027, 0.995192, 1.63959, 2.71603", \ + "0.0662089, 0.248347, 0.381093, 0.608666, 0.995193, 1.63968, 2.71604", \ + "0.093933, 0.281766, 0.406249, 0.622144, 0.998605, 1.64147, 2.71605", \ + "0.138034, 0.356166, 0.480422, 0.682172, 1.03341, 1.64898, 2.72248", \ + "0.209673, 0.489846, 0.628376, 0.833352, 1.17196, 1.7438, 2.75259", \ + "0.325572, 0.704648, 0.878108, 1.12116, 1.47078, 2.03584, 2.97977" \ ); } } @@ -5657,52 +5657,52 @@ library (sg13g2_stdcell_slow_1p08V_125C) { index_1 ("0.0186, 0.0966, 0.174, 0.3294, 0.6408, 1.263, 2.5074"); index_2 ("0.001, 0.0234, 0.039, 0.0648, 0.108, 0.18, 0.3"); values ( \ - "0.0733945, 0.280293, 0.421675, 0.655356, 1.04569, 1.69656, 2.78126", \ - "0.104277, 0.315215, 0.457127, 0.691717, 1.08237, 1.73351, 2.81905", \ - "0.130288, 0.352754, 0.494972, 0.728887, 1.12057, 1.7718, 2.8582", \ - "0.167926, 0.425827, 0.570638, 0.804532, 1.19575, 1.84663, 2.93341", \ - "0.217287, 0.542498, 0.705703, 0.951006, 1.34277, 1.99288, 3.07785", \ - "0.276208, 0.714271, 0.920702, 1.20894, 1.63315, 2.29285, 3.37421", \ - "0.350934, 0.945589, 1.22482, 1.59936, 2.11929, 2.86114, 3.9846" \ + "0.0733978, 0.280291, 0.421709, 0.655359, 1.0457, 1.69655, 2.78124", \ + "0.104229, 0.315222, 0.457114, 0.691723, 1.08237, 1.73369, 2.81797", \ + "0.130289, 0.352767, 0.494941, 0.728968, 1.12052, 1.77182, 2.85821", \ + "0.167926, 0.425828, 0.570638, 0.804533, 1.19576, 1.84669, 2.93342", \ + "0.217288, 0.542498, 0.705704, 0.951006, 1.34279, 1.99288, 3.07798", \ + "0.276208, 0.714271, 0.920703, 1.20895, 1.63315, 2.29287, 3.37403", \ + "0.350935, 0.94559, 1.22482, 1.59936, 2.11929, 2.86114, 3.98457" \ ); } rise_transition (TIMING_DELAY_7x7ds1) { index_1 ("0.0186, 0.0966, 0.174, 0.3294, 0.6408, 1.263, 2.5074"); index_2 ("0.001, 0.0234, 0.039, 0.0648, 0.108, 0.18, 0.3"); values ( \ - "0.0635214, 0.343674, 0.538273, 0.859842, 1.39753, 2.29505, 3.78995", \ - "0.0716616, 0.345228, 0.538274, 0.860471, 1.39809, 2.29506, 3.78996", \ - "0.0876399, 0.34708, 0.538803, 0.860472, 1.3981, 2.29562, 3.79057", \ - "0.11673, 0.369593, 0.550278, 0.861921, 1.4, 2.29582, 3.79058", \ - "0.164383, 0.439129, 0.607504, 0.897202, 1.41, 2.29583, 3.79059", \ - "0.238147, 0.573247, 0.749361, 1.02618, 1.49938, 2.33499, 3.80488", \ - "0.358139, 0.801284, 1.00869, 1.31159, 1.78051, 2.55792, 3.92203" \ + "0.063523, 0.343682, 0.538471, 0.859844, 1.39753, 2.29468, 3.78996", \ + "0.0717293, 0.345238, 0.538472, 0.860472, 1.3981, 2.29469, 3.78997", \ + "0.0877006, 0.347088, 0.538809, 0.860481, 1.39811, 2.29564, 3.79058", \ + "0.11673, 0.369594, 0.550278, 0.861922, 1.40001, 2.29565, 3.79059", \ + "0.164383, 0.439131, 0.607505, 0.89706, 1.40983, 2.29566, 3.7906", \ + "0.238148, 0.573248, 0.749362, 1.02618, 1.49939, 2.33499, 3.81428", \ + "0.358139, 0.801284, 1.0087, 1.31159, 1.78051, 2.558, 3.92237" \ ); } cell_fall (TIMING_DELAY_7x7ds1) { index_1 ("0.0186, 0.0966, 0.174, 0.3294, 0.6408, 1.263, 2.5074"); index_2 ("0.001, 0.0234, 0.039, 0.0648, 0.108, 0.18, 0.3"); values ( \ - "0.0514663, 0.205908, 0.311786, 0.486703, 0.779612, 1.26745, 2.08018", \ - "0.0825932, 0.248269, 0.354478, 0.529742, 0.822822, 1.31069, 2.12363", \ - "0.103833, 0.289476, 0.396807, 0.572154, 0.86512, 1.35361, 2.16597", \ - "0.13527, 0.363219, 0.479285, 0.658267, 0.951519, 1.43913, 2.25338", \ - "0.176744, 0.476214, 0.6158, 0.817443, 1.12115, 1.60938, 2.42094", \ - "0.230616, 0.639304, 0.821177, 1.07073, 1.42423, 1.9468, 2.76673", \ - "0.301976, 0.860272, 1.11347, 1.44554, 1.89486, 2.51817, 3.42322" \ + "0.0514689, 0.205904, 0.311744, 0.48672, 0.779614, 1.26743, 2.08002", \ + "0.0825694, 0.248271, 0.354503, 0.52972, 0.822781, 1.31071, 2.12342", \ + "0.103825, 0.289486, 0.396812, 0.572128, 0.865122, 1.35317, 2.16595", \ + "0.135232, 0.363217, 0.479283, 0.658326, 0.95155, 1.43927, 2.25227", \ + "0.176743, 0.476213, 0.615798, 0.817439, 1.12113, 1.60936, 2.42087", \ + "0.230616, 0.639179, 0.821175, 1.07065, 1.42422, 1.94679, 2.76671", \ + "0.301975, 0.860269, 1.11347, 1.44553, 1.89486, 2.51816, 3.42337" \ ); } fall_transition (TIMING_DELAY_7x7ds1) { index_1 ("0.0186, 0.0966, 0.174, 0.3294, 0.6408, 1.263, 2.5074"); index_2 ("0.001, 0.0234, 0.039, 0.0648, 0.108, 0.18, 0.3"); values ( \ - "0.0493684, 0.250013, 0.389529, 0.620724, 1.00755, 1.65189, 2.72568", \ - "0.0658307, 0.251387, 0.389589, 0.620725, 1.00756, 1.6519, 2.72572", \ - "0.084396, 0.261583, 0.394355, 0.621455, 1.00757, 1.6523, 2.72638", \ - "0.118176, 0.295376, 0.419454, 0.634915, 1.01069, 1.65231, 2.72729", \ - "0.171786, 0.371615, 0.493941, 0.695095, 1.04685, 1.66279, 2.72739", \ - "0.256213, 0.509411, 0.642543, 0.847514, 1.18381, 1.75672, 2.76623", \ - "0.393927, 0.731149, 0.897695, 1.1353, 1.48605, 2.04906, 2.98967" \ + "0.0493617, 0.25001, 0.389533, 0.620718, 1.00754, 1.65187, 2.72725", \ + "0.0658375, 0.25138, 0.389583, 0.620719, 1.00755, 1.65188, 2.72726", \ + "0.0843828, 0.261572, 0.394342, 0.623851, 1.00756, 1.65189, 2.72727", \ + "0.118231, 0.295374, 0.419451, 0.634915, 1.0111, 1.6519, 2.72804", \ + "0.171785, 0.371612, 0.493938, 0.695091, 1.04685, 1.66278, 2.72805", \ + "0.256213, 0.509387, 0.642541, 0.847543, 1.1838, 1.75639, 2.7662", \ + "0.393926, 0.731146, 0.89769, 1.13529, 1.48604, 2.04905, 2.99033" \ ); } } @@ -5713,26 +5713,26 @@ library (sg13g2_stdcell_slow_1p08V_125C) { index_1 ("0.0186, 0.0966, 0.174, 0.3294, 0.6408, 1.263, 2.5074"); index_2 ("0.001, 0.0234, 0.039, 0.0648, 0.108, 0.18, 0.3"); values ( \ - "0.00379555, 0.0038917, 0.00386501, 0.0038045, 0.00370174, 0.00353301, 0.00336465", \ - "0.00356052, 0.00379203, 0.00379853, 0.00378008, 0.00369111, 0.0035721, 0.00340914", \ - "0.00350308, 0.00371621, 0.00373811, 0.00376005, 0.00367443, 0.00352613, 0.00337065", \ - "0.00346174, 0.00364151, 0.00370556, 0.00373565, 0.00370325, 0.0036042, 0.0033575", \ - "0.00348681, 0.00356432, 0.00359459, 0.00373062, 0.00362134, 0.00348385, 0.00342071", \ - "0.00377208, 0.00366212, 0.00365857, 0.00354704, 0.00364779, 0.00341493, 0.00403231", \ - "0.00497939, 0.00418158, 0.00406478, 0.00396311, 0.00371719, 0.00358607, 0.00357629" \ + "0.00379572, 0.00389214, 0.00386453, 0.00380436, 0.00371928, 0.00354811, 0.0033655", \ + "0.00356052, 0.00380556, 0.00379786, 0.00378008, 0.00371694, 0.00357534, 0.00338663", \ + "0.00350347, 0.00372787, 0.00374056, 0.00376002, 0.00367446, 0.00353806, 0.00362039", \ + "0.00346217, 0.003645, 0.00370557, 0.00373565, 0.00370325, 0.00360414, 0.00335762", \ + "0.00348679, 0.00356432, 0.00359422, 0.00373053, 0.00356663, 0.00348391, 0.00341665", \ + "0.00377201, 0.0036627, 0.00365834, 0.00355596, 0.00368341, 0.00344274, 0.0037781", \ + "0.00498005, 0.00418198, 0.00406463, 0.00396288, 0.00374357, 0.00358705, 0.00400793" \ ); } fall_power (POWER_7x7ds1) { index_1 ("0.0186, 0.0966, 0.174, 0.3294, 0.6408, 1.263, 2.5074"); index_2 ("0.001, 0.0234, 0.039, 0.0648, 0.108, 0.18, 0.3"); values ( \ - "0.00403907, 0.00401958, 0.00398316, 0.00393804, 0.00385371, 0.00368857, 0.00342111", \ - "0.00378813, 0.00391977, 0.00387536, 0.00385464, 0.00376573, 0.00360163, 0.00340265", \ - "0.00373046, 0.00387979, 0.0038323, 0.00396012, 0.00374988, 0.0036076, 0.00334144", \ - "0.00374284, 0.00379715, 0.00383378, 0.0037742, 0.00371012, 0.00359178, 0.00341559", \ - "0.00397705, 0.00388218, 0.00384454, 0.00376545, 0.00393864, 0.00360295, 0.00355131", \ - "0.00462114, 0.00421227, 0.00415557, 0.00406346, 0.00380141, 0.00379716, 0.00352527", \ - "0.00620934, 0.00522372, 0.0049745, 0.00473523, 0.00443904, 0.00393079, 0.00362199" \ + "0.00404616, 0.0040182, 0.00398264, 0.00393843, 0.00385354, 0.00368811, 0.00342045", \ + "0.00378371, 0.00392456, 0.00388012, 0.00385039, 0.00376687, 0.00360951, 0.00339944", \ + "0.00372347, 0.00388328, 0.00383783, 0.00395942, 0.00374914, 0.00360952, 0.0033414", \ + "0.00374373, 0.00379588, 0.00383821, 0.00377562, 0.00371012, 0.00359499, 0.00341474", \ + "0.00397824, 0.00388218, 0.00384455, 0.00376785, 0.00379467, 0.00356724, 0.00355115", \ + "0.0046197, 0.00421271, 0.00415591, 0.00406351, 0.00380135, 0.00380409, 0.00352516", \ + "0.00620923, 0.00522402, 0.00497478, 0.00473521, 0.00443915, 0.00391744, 0.00362274" \ ); } } @@ -5742,26 +5742,26 @@ library (sg13g2_stdcell_slow_1p08V_125C) { index_1 ("0.0186, 0.0966, 0.174, 0.3294, 0.6408, 1.263, 2.5074"); index_2 ("0.001, 0.0234, 0.039, 0.0648, 0.108, 0.18, 0.3"); values ( \ - "0.00379555, 0.0038917, 0.00386501, 0.0038045, 0.00370174, 0.00353301, 0.00336465", \ - "0.00356052, 0.00379203, 0.00379853, 0.00378008, 0.00369111, 0.0035721, 0.00340914", \ - "0.00350308, 0.00371621, 0.00373811, 0.00376005, 0.00367443, 0.00352613, 0.00337065", \ - "0.00346174, 0.00364151, 0.00370556, 0.00373565, 0.00370325, 0.0036042, 0.0033575", \ - "0.00348681, 0.00356432, 0.00359459, 0.00373062, 0.00362134, 0.00348385, 0.00342071", \ - "0.00377208, 0.00366212, 0.00365857, 0.00354704, 0.00364779, 0.00341493, 0.00403231", \ - "0.00497939, 0.00418158, 0.00406478, 0.00396311, 0.00371719, 0.00358607, 0.00357629" \ + "0.00379572, 0.00389214, 0.00386453, 0.00380436, 0.00371928, 0.00354811, 0.0033655", \ + "0.00356052, 0.00380556, 0.00379786, 0.00378008, 0.00371694, 0.00357534, 0.00338663", \ + "0.00350347, 0.00372787, 0.00374056, 0.00376002, 0.00367446, 0.00353806, 0.00362039", \ + "0.00346217, 0.003645, 0.00370557, 0.00373565, 0.00370325, 0.00360414, 0.00335762", \ + "0.00348679, 0.00356432, 0.00359422, 0.00373053, 0.00356663, 0.00348391, 0.00341665", \ + "0.00377201, 0.0036627, 0.00365834, 0.00355596, 0.00368341, 0.00344274, 0.0037781", \ + "0.00498005, 0.00418198, 0.00406463, 0.00396288, 0.00374357, 0.00358705, 0.00400793" \ ); } fall_power (POWER_7x7ds1) { index_1 ("0.0186, 0.0966, 0.174, 0.3294, 0.6408, 1.263, 2.5074"); index_2 ("0.001, 0.0234, 0.039, 0.0648, 0.108, 0.18, 0.3"); values ( \ - "0.00403907, 0.00401958, 0.00398316, 0.00393804, 0.00385371, 0.00368857, 0.00342111", \ - "0.00378813, 0.00391977, 0.00387536, 0.00385464, 0.00376573, 0.00360163, 0.00340265", \ - "0.00373046, 0.00387979, 0.0038323, 0.00396012, 0.00374988, 0.0036076, 0.00334144", \ - "0.00374284, 0.00379715, 0.00383378, 0.0037742, 0.00371012, 0.00359178, 0.00341559", \ - "0.00397705, 0.00388218, 0.00384454, 0.00376545, 0.00393864, 0.00360295, 0.00355131", \ - "0.00462114, 0.00421227, 0.00415557, 0.00406346, 0.00380141, 0.00379716, 0.00352527", \ - "0.00620934, 0.00522372, 0.0049745, 0.00473523, 0.00443904, 0.00393079, 0.00362199" \ + "0.00404616, 0.0040182, 0.00398264, 0.00393843, 0.00385354, 0.00368811, 0.00342045", \ + "0.00378371, 0.00392456, 0.00388012, 0.00385039, 0.00376687, 0.00360951, 0.00339944", \ + "0.00372347, 0.00388328, 0.00383783, 0.00395942, 0.00374914, 0.00360952, 0.0033414", \ + "0.00374373, 0.00379588, 0.00383821, 0.00377562, 0.00371012, 0.00359499, 0.00341474", \ + "0.00397824, 0.00388218, 0.00384455, 0.00376785, 0.00379467, 0.00356724, 0.00355115", \ + "0.0046197, 0.00421271, 0.00415591, 0.00406351, 0.00380135, 0.00380409, 0.00352516", \ + "0.00620923, 0.00522402, 0.00497478, 0.00473521, 0.00443915, 0.00391744, 0.00362274" \ ); } } @@ -5772,26 +5772,26 @@ library (sg13g2_stdcell_slow_1p08V_125C) { index_1 ("0.0186, 0.0966, 0.174, 0.3294, 0.6408, 1.263, 2.5074"); index_2 ("0.001, 0.0234, 0.039, 0.0648, 0.108, 0.18, 0.3"); values ( \ - "0.00391473, 0.00389416, 0.00385703, 0.00379574, 0.0037169, 0.00352963, 0.00336321", \ - "0.00377576, 0.00383718, 0.00381652, 0.00378988, 0.00369959, 0.00355159, 0.00335509", \ - "0.00373289, 0.00380101, 0.00381154, 0.00375019, 0.00371094, 0.00353339, 0.00363476", \ - "0.00370319, 0.00378108, 0.00377672, 0.00381254, 0.00372389, 0.00361322, 0.00335055", \ - "0.00371362, 0.00375009, 0.00373507, 0.00377518, 0.00365319, 0.00349875, 0.00343765", \ - "0.00394504, 0.00383327, 0.00383705, 0.00373091, 0.00376097, 0.00348735, 0.0036802", \ - "0.00499157, 0.00436476, 0.00422793, 0.0041407, 0.00395618, 0.00373128, 0.00392446" \ + "0.00391471, 0.00389312, 0.00385934, 0.0038082, 0.00371663, 0.00353049, 0.00336314", \ + "0.00377588, 0.00385379, 0.00381574, 0.00378994, 0.00370087, 0.00355155, 0.003624", \ + "0.00373435, 0.00380062, 0.00381187, 0.00375174, 0.00371336, 0.0035335, 0.0036363", \ + "0.00370369, 0.00378109, 0.0037862, 0.00379977, 0.00372395, 0.00351462, 0.00335055", \ + "0.00371357, 0.00375006, 0.00372688, 0.00377597, 0.00368033, 0.00348897, 0.0034377", \ + "0.00394515, 0.00383319, 0.00383349, 0.00369918, 0.00375131, 0.00351353, 0.00349693", \ + "0.00499168, 0.00436498, 0.0042281, 0.00413799, 0.00394245, 0.00373236, 0.00392538" \ ); } fall_power (POWER_7x7ds1) { index_1 ("0.0186, 0.0966, 0.174, 0.3294, 0.6408, 1.263, 2.5074"); index_2 ("0.001, 0.0234, 0.039, 0.0648, 0.108, 0.18, 0.3"); values ( \ - "0.00517694, 0.00514326, 0.00510739, 0.00506743, 0.00497781, 0.00483551, 0.00455915", \ - "0.00500568, 0.00506582, 0.00502257, 0.00499012, 0.00491315, 0.0047305, 0.00449221", \ - "0.00494379, 0.0050363, 0.00499803, 0.00509555, 0.00489798, 0.00476254, 0.00449926", \ - "0.00489631, 0.0049625, 0.00499171, 0.00492677, 0.00488091, 0.00474313, 0.00455041", \ - "0.00495671, 0.00498542, 0.00496862, 0.00492166, 0.00495365, 0.00472882, 0.00476188", \ - "0.00532107, 0.00511294, 0.0051167, 0.00504162, 0.00489682, 0.00489346, 0.00457279", \ - "0.0065294, 0.00582665, 0.00567181, 0.0054904, 0.00537513, 0.00490732, 0.00470246" \ + "0.00517694, 0.00514314, 0.00510694, 0.00506683, 0.00497881, 0.00484204, 0.00456105", \ + "0.00500564, 0.00504483, 0.00502517, 0.00499059, 0.00491476, 0.00473066, 0.00449227", \ + "0.00493625, 0.00505354, 0.00499379, 0.00498725, 0.00489659, 0.00476336, 0.00449939", \ + "0.0048975, 0.00496217, 0.00499161, 0.00493515, 0.00486453, 0.00472645, 0.00454847", \ + "0.0049535, 0.00498528, 0.00497873, 0.00492684, 0.00508489, 0.00473516, 0.00476041", \ + "0.00532118, 0.0051131, 0.00511299, 0.00507882, 0.00489674, 0.00489162, 0.00457294", \ + "0.00652932, 0.00582663, 0.00567167, 0.005486, 0.00537573, 0.00490465, 0.00467527" \ ); } } @@ -5801,26 +5801,26 @@ library (sg13g2_stdcell_slow_1p08V_125C) { index_1 ("0.0186, 0.0966, 0.174, 0.3294, 0.6408, 1.263, 2.5074"); index_2 ("0.001, 0.0234, 0.039, 0.0648, 0.108, 0.18, 0.3"); values ( \ - "0.00391473, 0.00389416, 0.00385703, 0.00379574, 0.0037169, 0.00352963, 0.00336321", \ - "0.00377576, 0.00383718, 0.00381652, 0.00378988, 0.00369959, 0.00355159, 0.00335509", \ - "0.00373289, 0.00380101, 0.00381154, 0.00375019, 0.00371094, 0.00353339, 0.00363476", \ - "0.00370319, 0.00378108, 0.00377672, 0.00381254, 0.00372389, 0.00361322, 0.00335055", \ - "0.00371362, 0.00375009, 0.00373507, 0.00377518, 0.00365319, 0.00349875, 0.00343765", \ - "0.00394504, 0.00383327, 0.00383705, 0.00373091, 0.00376097, 0.00348735, 0.0036802", \ - "0.00499157, 0.00436476, 0.00422793, 0.0041407, 0.00395618, 0.00373128, 0.00392446" \ + "0.00391471, 0.00389312, 0.00385934, 0.0038082, 0.00371663, 0.00353049, 0.00336314", \ + "0.00377588, 0.00385379, 0.00381574, 0.00378994, 0.00370087, 0.00355155, 0.003624", \ + "0.00373435, 0.00380062, 0.00381187, 0.00375174, 0.00371336, 0.0035335, 0.0036363", \ + "0.00370369, 0.00378109, 0.0037862, 0.00379977, 0.00372395, 0.00351462, 0.00335055", \ + "0.00371357, 0.00375006, 0.00372688, 0.00377597, 0.00368033, 0.00348897, 0.0034377", \ + "0.00394515, 0.00383319, 0.00383349, 0.00369918, 0.00375131, 0.00351353, 0.00349693", \ + "0.00499168, 0.00436498, 0.0042281, 0.00413799, 0.00394245, 0.00373236, 0.00392538" \ ); } fall_power (POWER_7x7ds1) { index_1 ("0.0186, 0.0966, 0.174, 0.3294, 0.6408, 1.263, 2.5074"); index_2 ("0.001, 0.0234, 0.039, 0.0648, 0.108, 0.18, 0.3"); values ( \ - "0.00517694, 0.00514326, 0.00510739, 0.00506743, 0.00497781, 0.00483551, 0.00455915", \ - "0.00500568, 0.00506582, 0.00502257, 0.00499012, 0.00491315, 0.0047305, 0.00449221", \ - "0.00494379, 0.0050363, 0.00499803, 0.00509555, 0.00489798, 0.00476254, 0.00449926", \ - "0.00489631, 0.0049625, 0.00499171, 0.00492677, 0.00488091, 0.00474313, 0.00455041", \ - "0.00495671, 0.00498542, 0.00496862, 0.00492166, 0.00495365, 0.00472882, 0.00476188", \ - "0.00532107, 0.00511294, 0.0051167, 0.00504162, 0.00489682, 0.00489346, 0.00457279", \ - "0.0065294, 0.00582665, 0.00567181, 0.0054904, 0.00537513, 0.00490732, 0.00470246" \ + "0.00517694, 0.00514314, 0.00510694, 0.00506683, 0.00497881, 0.00484204, 0.00456105", \ + "0.00500564, 0.00504483, 0.00502517, 0.00499059, 0.00491476, 0.00473066, 0.00449227", \ + "0.00493625, 0.00505354, 0.00499379, 0.00498725, 0.00489659, 0.00476336, 0.00449939", \ + "0.0048975, 0.00496217, 0.00499161, 0.00493515, 0.00486453, 0.00472645, 0.00454847", \ + "0.0049535, 0.00498528, 0.00497873, 0.00492684, 0.00508489, 0.00473516, 0.00476041", \ + "0.00532118, 0.0051131, 0.00511299, 0.00507882, 0.00489674, 0.00489162, 0.00457294", \ + "0.00652932, 0.00582663, 0.00567167, 0.005486, 0.00537573, 0.00490465, 0.00467527" \ ); } } @@ -5831,26 +5831,26 @@ library (sg13g2_stdcell_slow_1p08V_125C) { index_1 ("0.0186, 0.0966, 0.174, 0.3294, 0.6408, 1.263, 2.5074"); index_2 ("0.001, 0.0234, 0.039, 0.0648, 0.108, 0.18, 0.3"); values ( \ - "0.00263223, 0.00263494, 0.00260688, 0.00255521, 0.00244819, 0.00229293, 0.00235193", \ - "0.0024116, 0.0025535, 0.00252422, 0.0025035, 0.00242909, 0.00230131, 0.0023678", \ - "0.00238016, 0.00248363, 0.00251077, 0.00250171, 0.0024062, 0.00224644, 0.00211848", \ - "0.00241165, 0.0024632, 0.00245097, 0.0024493, 0.00241694, 0.00222406, 0.00206928", \ - "0.00264413, 0.00257745, 0.00251411, 0.00260941, 0.00238627, 0.00222632, 0.0023642", \ - "0.00329693, 0.00286356, 0.00275806, 0.0025863, 0.00259916, 0.00224133, 0.00247656", \ - "0.00480783, 0.00396234, 0.00365399, 0.00336889, 0.00302813, 0.0026654, 0.00238552" \ + "0.00263309, 0.00263263, 0.00260925, 0.00255517, 0.00244266, 0.00229446, 0.00235263", \ + "0.00241147, 0.00255421, 0.00252719, 0.00250417, 0.00242876, 0.00229879, 0.00208245", \ + "0.00237657, 0.00248534, 0.00251202, 0.00247056, 0.0024054, 0.00224629, 0.002119", \ + "0.00241151, 0.00246321, 0.00245068, 0.00244712, 0.00241694, 0.00222306, 0.00206922", \ + "0.00264453, 0.0025775, 0.00251423, 0.00257487, 0.00235049, 0.00228391, 0.00204191", \ + "0.00329694, 0.00286404, 0.00275577, 0.00258628, 0.00255562, 0.00224287, 0.00229944", \ + "0.00480818, 0.00396225, 0.00365433, 0.00338041, 0.00296154, 0.00266507, 0.00250439" \ ); } fall_power (POWER_7x7ds1) { index_1 ("0.0186, 0.0966, 0.174, 0.3294, 0.6408, 1.263, 2.5074"); index_2 ("0.001, 0.0234, 0.039, 0.0648, 0.108, 0.18, 0.3"); values ( \ - "0.00475042, 0.00482412, 0.00480327, 0.00474579, 0.00466517, 0.00448835, 0.00426667", \ - "0.00447292, 0.00478622, 0.00477631, 0.00476788, 0.00469854, 0.00453399, 0.00432513", \ - "0.00440488, 0.00476187, 0.00475059, 0.00474555, 0.00468074, 0.00457769, 0.00429323", \ - "0.0043645, 0.00460933, 0.00470393, 0.00467568, 0.00469587, 0.00452921, 0.00431584", \ - "0.00446147, 0.00457252, 0.00461504, 0.00462784, 0.00484578, 0.00452762, 0.00430244", \ - "0.00493676, 0.00467134, 0.00470249, 0.0047254, 0.00455988, 0.00463125, 0.00436082", \ - "0.00634316, 0.00539042, 0.00522838, 0.00507711, 0.00499207, 0.00459776, 0.00443853" \ + "0.00475036, 0.00482879, 0.00480356, 0.00474475, 0.00466279, 0.0044853, 0.00419033", \ + "0.00447812, 0.0047751, 0.00479183, 0.00477089, 0.00469887, 0.00453477, 0.00432525", \ + "0.00440531, 0.00475903, 0.00475039, 0.00483256, 0.00468017, 0.00457841, 0.00429192", \ + "0.00436438, 0.00460898, 0.00470416, 0.00468033, 0.00469593, 0.00451748, 0.00433807", \ + "0.00446181, 0.00457252, 0.00461715, 0.00461538, 0.00484584, 0.00456988, 0.00429937", \ + "0.00493713, 0.00467148, 0.00470683, 0.00472511, 0.00455933, 0.00462741, 0.00436212", \ + "0.00634341, 0.00538733, 0.00522838, 0.00507711, 0.00499207, 0.00459765, 0.00443847" \ ); } } @@ -5861,26 +5861,26 @@ library (sg13g2_stdcell_slow_1p08V_125C) { index_1 ("0.0186, 0.0966, 0.174, 0.3294, 0.6408, 1.263, 2.5074"); index_2 ("0.001, 0.0234, 0.039, 0.0648, 0.108, 0.18, 0.3"); values ( \ - "0.00247482, 0.00250749, 0.00247343, 0.00242643, 0.00233557, 0.00215881, 0.0019682", \ - "0.00224774, 0.00242596, 0.0024182, 0.00236328, 0.00229532, 0.00215916, 0.0019454", \ - "0.00223096, 0.00235906, 0.0023613, 0.00232797, 0.00226371, 0.00212159, 0.00200439", \ - "0.00228588, 0.00233008, 0.00235083, 0.00237916, 0.00230419, 0.00222817, 0.00196017", \ - "0.00255274, 0.00243397, 0.00239813, 0.00236958, 0.00228197, 0.00215672, 0.00190915", \ - "0.00325047, 0.00275352, 0.00264834, 0.00245807, 0.002503, 0.00215298, 0.00234457", \ - "0.00483576, 0.00386198, 0.00354392, 0.00324278, 0.00289683, 0.00255613, 0.00235182" \ + "0.00247443, 0.0025098, 0.00248196, 0.00242363, 0.00231824, 0.00216839, 0.00196861", \ + "0.0022479, 0.00242669, 0.00241692, 0.00236331, 0.00229518, 0.00217123, 0.00191822", \ + "0.00223143, 0.00234834, 0.00236036, 0.00233212, 0.00226415, 0.00212179, 0.0020042", \ + "0.0022856, 0.00232994, 0.00235082, 0.00236726, 0.00230416, 0.00209368, 0.00195996", \ + "0.00255265, 0.00243499, 0.00239809, 0.00237437, 0.00228154, 0.00209208, 0.00190914", \ + "0.00325047, 0.0027552, 0.00264835, 0.00245819, 0.002503, 0.00215298, 0.00242873", \ + "0.00483599, 0.0038619, 0.00354244, 0.00325546, 0.00289683, 0.00253322, 0.00235187" \ ); } fall_power (POWER_7x7ds1) { index_1 ("0.0186, 0.0966, 0.174, 0.3294, 0.6408, 1.263, 2.5074"); index_2 ("0.001, 0.0234, 0.039, 0.0648, 0.108, 0.18, 0.3"); values ( \ - "0.00352371, 0.00361504, 0.00359138, 0.00353871, 0.00345462, 0.00329327, 0.00308526", \ - "0.00326058, 0.00356695, 0.00358833, 0.00354806, 0.00349413, 0.00336251, 0.00310431", \ - "0.00318041, 0.00353608, 0.00353062, 0.00355658, 0.00348857, 0.00338807, 0.00308416", \ - "0.0031379, 0.00342036, 0.00348612, 0.00347722, 0.00356267, 0.00331036, 0.00316578", \ - "0.00324134, 0.00337347, 0.00339181, 0.00340485, 0.00361989, 0.00340418, 0.00320793", \ - "0.00372916, 0.00347856, 0.00349965, 0.00351494, 0.00335481, 0.00342771, 0.00317433", \ - "0.00515705, 0.00420973, 0.00408429, 0.00388896, 0.00380335, 0.00343457, 0.00323341" \ + "0.00352377, 0.00361077, 0.00359172, 0.00354144, 0.00344839, 0.0032986, 0.00308327", \ + "0.00326091, 0.00356401, 0.00356941, 0.00354838, 0.00349428, 0.00336157, 0.00310433", \ + "0.0031806, 0.00353081, 0.00354202, 0.00355679, 0.00348643, 0.00338302, 0.00308482", \ + "0.00313695, 0.00342051, 0.00348612, 0.00348601, 0.00356283, 0.00331036, 0.00316768", \ + "0.00324243, 0.00337347, 0.00339099, 0.00340523, 0.00357541, 0.00340385, 0.00320798", \ + "0.00372893, 0.0034786, 0.00349817, 0.00349793, 0.00334415, 0.00341307, 0.00317165", \ + "0.00515705, 0.00421013, 0.00408304, 0.00387643, 0.003811, 0.00343535, 0.00323407" \ ); } } @@ -5890,26 +5890,26 @@ library (sg13g2_stdcell_slow_1p08V_125C) { index_1 ("0.0186, 0.0966, 0.174, 0.3294, 0.6408, 1.263, 2.5074"); index_2 ("0.001, 0.0234, 0.039, 0.0648, 0.108, 0.18, 0.3"); values ( \ - "0.00263223, 0.00263494, 0.00260688, 0.00255521, 0.00244819, 0.00229293, 0.00235193", \ - "0.0024116, 0.0025535, 0.00252422, 0.0025035, 0.00242909, 0.00230131, 0.0023678", \ - "0.00238016, 0.00248363, 0.00251077, 0.00250171, 0.0024062, 0.00224644, 0.00211848", \ - "0.00241165, 0.0024632, 0.00245097, 0.0024493, 0.00241694, 0.00222406, 0.00206928", \ - "0.00264413, 0.00257745, 0.00251411, 0.00260941, 0.00238627, 0.00222632, 0.0023642", \ - "0.00329693, 0.00286356, 0.00275806, 0.0025863, 0.00259916, 0.00224133, 0.00247656", \ - "0.00480783, 0.00396234, 0.00365399, 0.00336889, 0.00302813, 0.0026654, 0.00238552" \ + "0.00263309, 0.00263263, 0.00260925, 0.00255517, 0.00244266, 0.00229446, 0.00235263", \ + "0.00241147, 0.00255421, 0.00252719, 0.00250417, 0.00242876, 0.00229879, 0.00208245", \ + "0.00237657, 0.00248534, 0.00251202, 0.00247056, 0.0024054, 0.00224629, 0.002119", \ + "0.00241151, 0.00246321, 0.00245068, 0.00244712, 0.00241694, 0.00222306, 0.00206922", \ + "0.00264453, 0.0025775, 0.00251423, 0.00257487, 0.00235049, 0.00228391, 0.00204191", \ + "0.00329694, 0.00286404, 0.00275577, 0.00258628, 0.00255562, 0.00224287, 0.00229944", \ + "0.00480818, 0.00396225, 0.00365433, 0.00338041, 0.00296154, 0.00266507, 0.00250439" \ ); } fall_power (POWER_7x7ds1) { index_1 ("0.0186, 0.0966, 0.174, 0.3294, 0.6408, 1.263, 2.5074"); index_2 ("0.001, 0.0234, 0.039, 0.0648, 0.108, 0.18, 0.3"); values ( \ - "0.00475042, 0.00482412, 0.00480327, 0.00474579, 0.00466517, 0.00448835, 0.00426667", \ - "0.00447292, 0.00478622, 0.00477631, 0.00476788, 0.00469854, 0.00453399, 0.00432513", \ - "0.00440488, 0.00476187, 0.00475059, 0.00474555, 0.00468074, 0.00457769, 0.00429323", \ - "0.0043645, 0.00460933, 0.00470393, 0.00467568, 0.00469587, 0.00452921, 0.00431584", \ - "0.00446147, 0.00457252, 0.00461504, 0.00462784, 0.00484578, 0.00452762, 0.00430244", \ - "0.00493676, 0.00467134, 0.00470249, 0.0047254, 0.00455988, 0.00463125, 0.00436082", \ - "0.00634316, 0.00539042, 0.00522838, 0.00507711, 0.00499207, 0.00459776, 0.00443853" \ + "0.00475036, 0.00482879, 0.00480356, 0.00474475, 0.00466279, 0.0044853, 0.00419033", \ + "0.00447812, 0.0047751, 0.00479183, 0.00477089, 0.00469887, 0.00453477, 0.00432525", \ + "0.00440531, 0.00475903, 0.00475039, 0.00483256, 0.00468017, 0.00457841, 0.00429192", \ + "0.00436438, 0.00460898, 0.00470416, 0.00468033, 0.00469593, 0.00451748, 0.00433807", \ + "0.00446181, 0.00457252, 0.00461715, 0.00461538, 0.00484584, 0.00456988, 0.00429937", \ + "0.00493713, 0.00467148, 0.00470683, 0.00472511, 0.00455933, 0.00462741, 0.00436212", \ + "0.00634341, 0.00538733, 0.00522838, 0.00507711, 0.00499207, 0.00459765, 0.00443847" \ ); } } @@ -5920,26 +5920,26 @@ library (sg13g2_stdcell_slow_1p08V_125C) { index_1 ("0.0186, 0.0966, 0.174, 0.3294, 0.6408, 1.263, 2.5074"); index_2 ("0.001, 0.0234, 0.039, 0.0648, 0.108, 0.18, 0.3"); values ( \ - "0.00244388, 0.00256185, 0.00253427, 0.00248655, 0.00237854, 0.00220935, 0.00202863", \ - "0.0021536, 0.00245346, 0.00244618, 0.00244565, 0.00236504, 0.00220492, 0.00203008", \ - "0.00210614, 0.00233492, 0.00237551, 0.00238276, 0.00232729, 0.00220891, 0.00206732", \ - "0.00214981, 0.00227557, 0.00231338, 0.00238146, 0.00234927, 0.00217331, 0.0020206", \ - "0.00242156, 0.0023463, 0.00233066, 0.00243597, 0.00223367, 0.00211944, 0.00195286", \ - "0.0030887, 0.00262233, 0.00253597, 0.00238607, 0.00241533, 0.00214266, 0.00219035", \ - "0.00473064, 0.00364425, 0.0033338, 0.00310487, 0.00278426, 0.00249576, 0.00232708" \ + "0.00244369, 0.00256628, 0.00254061, 0.00248669, 0.00238122, 0.00219137, 0.00202881", \ + "0.00215284, 0.00245375, 0.00244549, 0.00244582, 0.00236459, 0.00222599, 0.00205701", \ + "0.00210845, 0.00234433, 0.00237754, 0.00238485, 0.00232309, 0.00219745, 0.00206706", \ + "0.00214846, 0.00227455, 0.00231333, 0.00238406, 0.00234926, 0.00214249, 0.00204394", \ + "0.00242002, 0.00234592, 0.00233065, 0.0023891, 0.00225808, 0.00211971, 0.00195616", \ + "0.00308814, 0.00262123, 0.00253597, 0.00238606, 0.00239551, 0.00214245, 0.0024183", \ + "0.00473106, 0.00364517, 0.00333453, 0.00310486, 0.00278431, 0.00245903, 0.00231913" \ ); } fall_power (POWER_7x7ds1) { index_1 ("0.0186, 0.0966, 0.174, 0.3294, 0.6408, 1.263, 2.5074"); index_2 ("0.001, 0.0234, 0.039, 0.0648, 0.108, 0.18, 0.3"); values ( \ - "0.00352432, 0.00367348, 0.00364869, 0.00360046, 0.00351475, 0.00335913, 0.00308615", \ - "0.00323871, 0.00360514, 0.00361342, 0.00360388, 0.00354094, 0.00337127, 0.00309684", \ - "0.0032033, 0.00355135, 0.00356546, 0.00357145, 0.00352099, 0.00341337, 0.00314931", \ - "0.00325121, 0.00344094, 0.00352655, 0.0035102, 0.00347604, 0.0033449, 0.00318046", \ - "0.00354995, 0.00348075, 0.0034904, 0.00346355, 0.00367126, 0.00331692, 0.00313453", \ - "0.00431482, 0.00382909, 0.0037216, 0.00364213, 0.00346515, 0.00350973, 0.00326818", \ - "0.00609985, 0.00486343, 0.00457252, 0.00427373, 0.00407711, 0.00357952, 0.00332945" \ + "0.00352009, 0.00367331, 0.00364768, 0.00360087, 0.00351505, 0.00335897, 0.00311044", \ + "0.00323701, 0.00361765, 0.0036129, 0.00360295, 0.00354062, 0.00337147, 0.00315029", \ + "0.00319783, 0.00356886, 0.0035657, 0.00365916, 0.00352144, 0.00338761, 0.00314964", \ + "0.00325127, 0.00344083, 0.00352654, 0.00351167, 0.00351226, 0.00335293, 0.00316053", \ + "0.00354961, 0.00348073, 0.00348768, 0.00346355, 0.00367043, 0.00331523, 0.00315397", \ + "0.0043153, 0.0038357, 0.00372158, 0.00366136, 0.00346526, 0.00349863, 0.00323366", \ + "0.00609983, 0.00486589, 0.00458219, 0.00427353, 0.00407711, 0.00357946, 0.00331246" \ ); } } @@ -5950,26 +5950,26 @@ library (sg13g2_stdcell_slow_1p08V_125C) { index_1 ("0.0186, 0.0966, 0.174, 0.3294, 0.6408, 1.263, 2.5074"); index_2 ("0.001, 0.0234, 0.039, 0.0648, 0.108, 0.18, 0.3"); values ( \ - "0.00223237, 0.00243673, 0.00241242, 0.00235915, 0.00226786, 0.00210088, 0.0019072", \ - "0.00196027, 0.00228682, 0.00231828, 0.002301, 0.00223915, 0.00210061, 0.00191893", \ - "0.00194728, 0.00221809, 0.00224496, 0.00225023, 0.00220183, 0.00208211, 0.00195982", \ - "0.00202374, 0.00213161, 0.00217851, 0.0022065, 0.00228915, 0.00204088, 0.00187651", \ - "0.00238782, 0.0022124, 0.002195, 0.00225754, 0.00214256, 0.00198165, 0.00186238", \ - "0.00307792, 0.0025221, 0.0024139, 0.00224198, 0.00225308, 0.00200492, 0.00215242", \ - "0.00482509, 0.00356318, 0.00323983, 0.00298784, 0.00257485, 0.0023653, 0.00225108" \ + "0.00223309, 0.00243617, 0.00241198, 0.00236034, 0.00226808, 0.00210088, 0.00190679", \ + "0.00195769, 0.0022868, 0.00231906, 0.00230086, 0.00224008, 0.00209588, 0.00216459", \ + "0.00194544, 0.00220797, 0.0022426, 0.00224949, 0.00219578, 0.00208221, 0.00195897", \ + "0.00202381, 0.00213163, 0.00217865, 0.00223166, 0.00228915, 0.00204022, 0.00190148", \ + "0.00238776, 0.00221279, 0.002195, 0.00228992, 0.0021092, 0.00205511, 0.00192533", \ + "0.003078, 0.00252258, 0.0024149, 0.00224195, 0.00231492, 0.00198269, 0.00254627", \ + "0.00482503, 0.00356304, 0.00324006, 0.00298781, 0.00261271, 0.00235802, 0.00225113" \ ); } fall_power (POWER_7x7ds1) { index_1 ("0.0186, 0.0966, 0.174, 0.3294, 0.6408, 1.263, 2.5074"); index_2 ("0.001, 0.0234, 0.039, 0.0648, 0.108, 0.18, 0.3"); values ( \ - "0.00229492, 0.00245947, 0.00243444, 0.00238503, 0.00231831, 0.00215502, 0.00188786", \ - "0.00201989, 0.00237803, 0.00244278, 0.00238835, 0.00234358, 0.00217707, 0.00199177", \ - "0.00197526, 0.00234221, 0.00235802, 0.00245077, 0.00232434, 0.0021838, 0.00197466", \ - "0.00202948, 0.00224174, 0.00230919, 0.00229529, 0.00229808, 0.00222465, 0.00198166", \ - "0.00232908, 0.00225842, 0.00228304, 0.00226565, 0.0023933, 0.00214866, 0.00219321", \ - "0.00311823, 0.00262565, 0.00254236, 0.00245611, 0.00227445, 0.00229567, 0.00196932", \ - "0.00493104, 0.00365126, 0.00339544, 0.0031042, 0.00286465, 0.00239076, 0.00214813" \ + "0.00229614, 0.00245979, 0.00243443, 0.00240031, 0.00231884, 0.0021473, 0.00188793", \ + "0.0020186, 0.00237793, 0.0024919, 0.00239052, 0.00234205, 0.00218942, 0.00199174", \ + "0.00197572, 0.00234033, 0.00235426, 0.00236488, 0.00230779, 0.00218864, 0.00197433", \ + "0.00202939, 0.00224176, 0.0023096, 0.00230116, 0.00228223, 0.00222232, 0.00198053", \ + "0.00232922, 0.0022602, 0.00228314, 0.00226382, 0.00239759, 0.00208754, 0.00220021", \ + "0.00311865, 0.00262542, 0.00254297, 0.00245521, 0.00227461, 0.00229643, 0.00194089", \ + "0.00493134, 0.00365127, 0.00339541, 0.00310423, 0.00286274, 0.00238822, 0.00215914" \ ); } } @@ -5979,26 +5979,26 @@ library (sg13g2_stdcell_slow_1p08V_125C) { index_1 ("0.0186, 0.0966, 0.174, 0.3294, 0.6408, 1.263, 2.5074"); index_2 ("0.001, 0.0234, 0.039, 0.0648, 0.108, 0.18, 0.3"); values ( \ - "0.00244388, 0.00256185, 0.00253427, 0.00248655, 0.00237854, 0.00220935, 0.00202863", \ - "0.0021536, 0.00245346, 0.00244618, 0.00244565, 0.00236504, 0.00220492, 0.00203008", \ - "0.00210614, 0.00233492, 0.00237551, 0.00238276, 0.00232729, 0.00220891, 0.00206732", \ - "0.00214981, 0.00227557, 0.00231338, 0.00238146, 0.00234927, 0.00217331, 0.0020206", \ - "0.00242156, 0.0023463, 0.00233066, 0.00243597, 0.00223367, 0.00211944, 0.00195286", \ - "0.0030887, 0.00262233, 0.00253597, 0.00238607, 0.00241533, 0.00214266, 0.00219035", \ - "0.00473064, 0.00364425, 0.0033338, 0.00310487, 0.00278426, 0.00249576, 0.00232708" \ + "0.00244369, 0.00256628, 0.00254061, 0.00248669, 0.00238122, 0.00219137, 0.00202881", \ + "0.00215284, 0.00245375, 0.00244549, 0.00244582, 0.00236459, 0.00222599, 0.00205701", \ + "0.00210845, 0.00234433, 0.00237754, 0.00238485, 0.00232309, 0.00219745, 0.00206706", \ + "0.00214846, 0.00227455, 0.00231333, 0.00238406, 0.00234926, 0.00214249, 0.00204394", \ + "0.00242002, 0.00234592, 0.00233065, 0.0023891, 0.00225808, 0.00211971, 0.00195616", \ + "0.00308814, 0.00262123, 0.00253597, 0.00238606, 0.00239551, 0.00214245, 0.0024183", \ + "0.00473106, 0.00364517, 0.00333453, 0.00310486, 0.00278431, 0.00245903, 0.00231913" \ ); } fall_power (POWER_7x7ds1) { index_1 ("0.0186, 0.0966, 0.174, 0.3294, 0.6408, 1.263, 2.5074"); index_2 ("0.001, 0.0234, 0.039, 0.0648, 0.108, 0.18, 0.3"); values ( \ - "0.00352432, 0.00367348, 0.00364869, 0.00360046, 0.00351475, 0.00335913, 0.00308615", \ - "0.00323871, 0.00360514, 0.00361342, 0.00360388, 0.00354094, 0.00337127, 0.00309684", \ - "0.0032033, 0.00355135, 0.00356546, 0.00357145, 0.00352099, 0.00341337, 0.00314931", \ - "0.00325121, 0.00344094, 0.00352655, 0.0035102, 0.00347604, 0.0033449, 0.00318046", \ - "0.00354995, 0.00348075, 0.0034904, 0.00346355, 0.00367126, 0.00331692, 0.00313453", \ - "0.00431482, 0.00382909, 0.0037216, 0.00364213, 0.00346515, 0.00350973, 0.00326818", \ - "0.00609985, 0.00486343, 0.00457252, 0.00427373, 0.00407711, 0.00357952, 0.00332945" \ + "0.00352009, 0.00367331, 0.00364768, 0.00360087, 0.00351505, 0.00335897, 0.00311044", \ + "0.00323701, 0.00361765, 0.0036129, 0.00360295, 0.00354062, 0.00337147, 0.00315029", \ + "0.00319783, 0.00356886, 0.0035657, 0.00365916, 0.00352144, 0.00338761, 0.00314964", \ + "0.00325127, 0.00344083, 0.00352654, 0.00351167, 0.00351226, 0.00335293, 0.00316053", \ + "0.00354961, 0.00348073, 0.00348768, 0.00346355, 0.00367043, 0.00331523, 0.00315397", \ + "0.0043153, 0.0038357, 0.00372158, 0.00366136, 0.00346526, 0.00349863, 0.00323366", \ + "0.00609983, 0.00486589, 0.00458219, 0.00427353, 0.00407711, 0.00357946, 0.00331246" \ ); } } @@ -6006,43 +6006,43 @@ library (sg13g2_stdcell_slow_1p08V_125C) { pin (A1) { direction : "input"; max_transition : 2.5074; - capacitance : 0.00291585; - rise_capacitance : 0.00292852; - rise_capacitance_range (0.00292852, 0.00292852); + capacitance : 0.00291584; + rise_capacitance : 0.00292849; + rise_capacitance_range (0.0027413, 0.0031042); fall_capacitance : 0.00290318; - fall_capacitance_range (0.00290318, 0.00290318); + fall_capacitance_range (0.00261174, 0.00324634); } pin (A2) { direction : "input"; max_transition : 2.5074; - capacitance : 0.00287686; - rise_capacitance : 0.00293143; - rise_capacitance_range (0.00293143, 0.00293143); - fall_capacitance : 0.00282228; - fall_capacitance_range (0.00282228, 0.00282228); + capacitance : 0.00287689; + rise_capacitance : 0.00293146; + rise_capacitance_range (0.00261768, 0.00326461); + fall_capacitance : 0.00282232; + fall_capacitance_range (0.00259982, 0.00314363); } pin (B1) { direction : "input"; max_transition : 2.5074; - capacitance : 0.00285293; - rise_capacitance : 0.00295675; - rise_capacitance_range (0.00295675, 0.00295675); - fall_capacitance : 0.00274912; - fall_capacitance_range (0.00274912, 0.00274912); + capacitance : 0.00285296; + rise_capacitance : 0.00295683; + rise_capacitance_range (0.0024936, 0.0033536); + fall_capacitance : 0.00274909; + fall_capacitance_range (0.00253579, 0.00293904); } pin (B2) { direction : "input"; max_transition : 2.5074; - capacitance : 0.00285818; - rise_capacitance : 0.00292024; - rise_capacitance_range (0.00292024, 0.00292024); - fall_capacitance : 0.00279611; - fall_capacitance_range (0.00279611, 0.00279611); + capacitance : 0.00285816; + rise_capacitance : 0.0029202; + rise_capacitance_range (0.00246129, 0.00319843); + fall_capacitance : 0.00279613; + fall_capacitance_range (0.00242832, 0.00304707); } } cell (sg13g2_and2_1) { area : 9.072; - cell_footprint : "AND2"; + cell_footprint : "and2"; cell_leakage_power : 635.37; leakage_power () { value : 854.873; @@ -6243,23 +6243,23 @@ library (sg13g2_stdcell_slow_1p08V_125C) { max_transition : 2.5074; capacitance : 0.00238471; rise_capacitance : 0.00239905; - rise_capacitance_range (0.00239905, 0.00239905); + rise_capacitance_range (0.00218761, 0.00255551); fall_capacitance : 0.00237036; - fall_capacitance_range (0.00237036, 0.00237036); + fall_capacitance_range (0.00213496, 0.00254416); } pin (B) { direction : "input"; max_transition : 2.5074; capacitance : 0.0023652; rise_capacitance : 0.00240373; - rise_capacitance_range (0.00240373, 0.00240373); + rise_capacitance_range (0.0021504, 0.00269265); fall_capacitance : 0.00232667; - fall_capacitance_range (0.00232667, 0.00232667); + fall_capacitance_range (0.00219017, 0.00245226); } } cell (sg13g2_and2_2) { area : 10.8864; - cell_footprint : "AND2"; + cell_footprint : "and2"; cell_leakage_power : 1027.41; leakage_power () { value : 989.949; @@ -6460,23 +6460,23 @@ library (sg13g2_stdcell_slow_1p08V_125C) { max_transition : 2.5074; capacitance : 0.00238973; rise_capacitance : 0.00240514; - rise_capacitance_range (0.00240514, 0.00240514); + rise_capacitance_range (0.00224501, 0.00253541); fall_capacitance : 0.00237431; - fall_capacitance_range (0.00237431, 0.00237431); + fall_capacitance_range (0.00219851, 0.00251515); } pin (B) { direction : "input"; max_transition : 2.5074; capacitance : 0.00238665; rise_capacitance : 0.00242858; - rise_capacitance_range (0.00242858, 0.00242858); + rise_capacitance_range (0.00219244, 0.0027018); fall_capacitance : 0.00234473; - fall_capacitance_range (0.00234473, 0.00234473); + fall_capacitance_range (0.00223493, 0.0024511); } } cell (sg13g2_and3_1) { area : 12.7008; - cell_footprint : "AND3"; + cell_footprint : "and3"; cell_leakage_power : 629.027; leakage_power () { value : 1214.68; @@ -6779,32 +6779,32 @@ library (sg13g2_stdcell_slow_1p08V_125C) { max_transition : 2.5074; capacitance : 0.00238063; rise_capacitance : 0.00239233; - rise_capacitance_range (0.00239233, 0.00239233); + rise_capacitance_range (0.00219708, 0.00253056); fall_capacitance : 0.00236893; - fall_capacitance_range (0.00236893, 0.00236893); + fall_capacitance_range (0.00212439, 0.00255729); } pin (B) { direction : "input"; max_transition : 2.5074; capacitance : 0.00234382; rise_capacitance : 0.00237893; - rise_capacitance_range (0.00237893, 0.00237893); + rise_capacitance_range (0.00212187, 0.00266769); fall_capacitance : 0.00230871; - fall_capacitance_range (0.00230871, 0.00230871); + fall_capacitance_range (0.00212637, 0.00245851); } pin (C) { direction : "input"; max_transition : 2.5074; capacitance : 0.0023538; rise_capacitance : 0.00239144; - rise_capacitance_range (0.00239144, 0.00239144); + rise_capacitance_range (0.00215175, 0.00265742); fall_capacitance : 0.00231616; - fall_capacitance_range (0.00231616, 0.00231616); + fall_capacitance_range (0.00220172, 0.00242782); } } cell (sg13g2_and3_2) { area : 12.7008; - cell_footprint : "AND3"; + cell_footprint : "and3"; cell_leakage_power : 1063.9; leakage_power () { value : 1349.75; @@ -7107,32 +7107,32 @@ library (sg13g2_stdcell_slow_1p08V_125C) { max_transition : 2.5074; capacitance : 0.00240717; rise_capacitance : 0.00242003; - rise_capacitance_range (0.00242003, 0.00242003); + rise_capacitance_range (0.00226534, 0.0025367); fall_capacitance : 0.00239431; - fall_capacitance_range (0.00239431, 0.00239431); + fall_capacitance_range (0.002209, 0.00255005); } pin (B) { direction : "input"; max_transition : 2.5074; capacitance : 0.00235856; rise_capacitance : 0.00239665; - rise_capacitance_range (0.00239665, 0.00239665); + rise_capacitance_range (0.00215361, 0.00267224); fall_capacitance : 0.00232047; - fall_capacitance_range (0.00232047, 0.00232047); + fall_capacitance_range (0.00216726, 0.00244861); } pin (C) { direction : "input"; max_transition : 2.5074; capacitance : 0.00236248; rise_capacitance : 0.00240402; - rise_capacitance_range (0.00240402, 0.00240402); + rise_capacitance_range (0.00217918, 0.00266128); fall_capacitance : 0.00232093; - fall_capacitance_range (0.00232093, 0.00232093); + fall_capacitance_range (0.00222152, 0.0024189); } } cell (sg13g2_and4_1) { area : 14.5152; - cell_footprint : "AND4"; + cell_footprint : "and4"; cell_leakage_power : 599.268; leakage_power () { value : 508.407; @@ -7553,41 +7553,41 @@ library (sg13g2_stdcell_slow_1p08V_125C) { max_transition : 2.5074; capacitance : 0.00221593; rise_capacitance : 0.0022256; - rise_capacitance_range (0.0022256, 0.0022256); + rise_capacitance_range (0.00204371, 0.00235219); fall_capacitance : 0.00220625; - fall_capacitance_range (0.00220625, 0.00220625); + fall_capacitance_range (0.00197049, 0.00240627); } pin (B) { direction : "input"; max_transition : 2.5074; capacitance : 0.00232724; rise_capacitance : 0.00235868; - rise_capacitance_range (0.00235868, 0.00235868); + rise_capacitance_range (0.00210421, 0.00264771); fall_capacitance : 0.00229581; - fall_capacitance_range (0.00229581, 0.00229581); + fall_capacitance_range (0.00209681, 0.00246003); } pin (C) { direction : "input"; max_transition : 2.5074; capacitance : 0.00232339; rise_capacitance : 0.00235716; - rise_capacitance_range (0.00235716, 0.00235716); + rise_capacitance_range (0.00211455, 0.00262875); fall_capacitance : 0.00228961; - fall_capacitance_range (0.00228961, 0.00228961); + fall_capacitance_range (0.00213021, 0.0024246); } pin (D) { direction : "input"; max_transition : 2.5074; capacitance : 0.0023321; rise_capacitance : 0.00236918; - rise_capacitance_range (0.00236918, 0.00236918); + rise_capacitance_range (0.00214205, 0.00261625); fall_capacitance : 0.00229502; - fall_capacitance_range (0.00229502, 0.00229502); + fall_capacitance_range (0.00219166, 0.00239706); } } cell (sg13g2_and4_2) { area : 16.3296; - cell_footprint : "AND4"; + cell_footprint : "and4"; cell_leakage_power : 1055.54; leakage_power () { value : 986.096; @@ -8008,41 +8008,41 @@ library (sg13g2_stdcell_slow_1p08V_125C) { max_transition : 2.5074; capacitance : 0.00222742; rise_capacitance : 0.0022386; - rise_capacitance_range (0.0022386, 0.0022386); + rise_capacitance_range (0.00209304, 0.0023468); fall_capacitance : 0.00221625; - fall_capacitance_range (0.00221625, 0.00221625); + fall_capacitance_range (0.00203631, 0.00238158); } pin (B) { direction : "input"; max_transition : 2.5074; capacitance : 0.00232868; rise_capacitance : 0.00236291; - rise_capacitance_range (0.00236291, 0.00236291); + rise_capacitance_range (0.00212268, 0.00264031); fall_capacitance : 0.00229444; - fall_capacitance_range (0.00229444, 0.00229444); + fall_capacitance_range (0.00212376, 0.00243507); } pin (C) { direction : "input"; max_transition : 2.5074; capacitance : 0.00232578; rise_capacitance : 0.00236258; - rise_capacitance_range (0.00236258, 0.00236258); + rise_capacitance_range (0.00212869, 0.00262788); fall_capacitance : 0.00228897; - fall_capacitance_range (0.00228897, 0.00228897); + fall_capacitance_range (0.0021475, 0.00240556); } pin (D) { direction : "input"; max_transition : 2.5074; capacitance : 0.00233359; rise_capacitance : 0.00237382; - rise_capacitance_range (0.00237382, 0.00237382); + rise_capacitance_range (0.00215952, 0.00261729); fall_capacitance : 0.00229337; - fall_capacitance_range (0.00229337, 0.00229337); + fall_capacitance_range (0.00220268, 0.00238341); } } cell (sg13g2_antennanp) { area : 5.4432; - cell_footprint : "NP_ant"; + cell_footprint : "antennanp"; cell_leakage_power : 3.5654; dont_touch : true; dont_use : true; @@ -8059,9 +8059,9 @@ library (sg13g2_stdcell_slow_1p08V_125C) { max_transition : 2.5074; capacitance : 0.00111883; rise_capacitance : 0.00107904; - rise_capacitance_range (0.00107904, 0.00107904); + rise_capacitance_range (0.0002285, 0.00176666); fall_capacitance : 0.00115861; - fall_capacitance_range (0.00115861, 0.00115861); + fall_capacitance_range (0.000222338, 0.00189149); internal_power () { rise_power (passive_POWER_7x1ds1) { index_1 ("0.0186, 0.0966, 0.174, 0.3294, 0.6408, 1.263, 2.5074"); @@ -8080,7 +8080,7 @@ library (sg13g2_stdcell_slow_1p08V_125C) { } cell (sg13g2_buf_1) { area : 7.2576; - cell_footprint : "BU"; + cell_footprint : "buf"; cell_leakage_power : 531.712; leakage_power () { value : 568.96; @@ -8187,14 +8187,14 @@ library (sg13g2_stdcell_slow_1p08V_125C) { max_transition : 2.5074; capacitance : 0.00211528; rise_capacitance : 0.00214982; - rise_capacitance_range (0.00214982, 0.00214982); + rise_capacitance_range (0.00196024, 0.00228989); fall_capacitance : 0.00208074; - fall_capacitance_range (0.00208074, 0.00208074); + fall_capacitance_range (0.00191501, 0.00223262); } } cell (sg13g2_buf_16) { area : 45.36; - cell_footprint : "BU"; + cell_footprint : "buf"; cell_leakage_power : 6741.44; leakage_power () { value : 5028.76; @@ -8301,14 +8301,14 @@ library (sg13g2_stdcell_slow_1p08V_125C) { max_transition : 2.5074; capacitance : 0.0159226; rise_capacitance : 0.0162359; - rise_capacitance_range (0.0162359, 0.0162359); + rise_capacitance_range (0.0149544, 0.0172776); fall_capacitance : 0.0156093; - fall_capacitance_range (0.0156093, 0.0156093); + fall_capacitance_range (0.0145123, 0.01661); } } cell (sg13g2_buf_2) { area : 9.072; - cell_footprint : "BU"; + cell_footprint : "buf"; cell_leakage_power : 882.336; leakage_power () { value : 1067.14; @@ -8415,14 +8415,14 @@ library (sg13g2_stdcell_slow_1p08V_125C) { max_transition : 2.5074; capacitance : 0.00245261; rise_capacitance : 0.00250186; - rise_capacitance_range (0.00250186, 0.00250186); + rise_capacitance_range (0.00232514, 0.0026462); fall_capacitance : 0.00240337; - fall_capacitance_range (0.00240337, 0.00240337); + fall_capacitance_range (0.00224886, 0.00255611); } } cell (sg13g2_buf_4) { area : 14.5152; - cell_footprint : "BU"; + cell_footprint : "buf"; cell_leakage_power : 1653.2; leakage_power () { value : 1257.51; @@ -8529,14 +8529,14 @@ library (sg13g2_stdcell_slow_1p08V_125C) { max_transition : 2.5074; capacitance : 0.00346371; rise_capacitance : 0.00362851; - rise_capacitance_range (0.00362851, 0.00362851); + rise_capacitance_range (0.00341474, 0.00379208); fall_capacitance : 0.00329891; - fall_capacitance_range (0.00329891, 0.00329891); + fall_capacitance_range (0.00309696, 0.00353517); } } cell (sg13g2_buf_8) { area : 23.5872; - cell_footprint : "BU"; + cell_footprint : "buf"; cell_leakage_power : 3370.78; leakage_power () { value : 2514.38; @@ -8643,14 +8643,14 @@ library (sg13g2_stdcell_slow_1p08V_125C) { max_transition : 2.5074; capacitance : 0.00800451; rise_capacitance : 0.00816044; - rise_capacitance_range (0.00816044, 0.00816044); + rise_capacitance_range (0.00757625, 0.00866592); fall_capacitance : 0.00784857; - fall_capacitance_range (0.00784857, 0.00784857); + fall_capacitance_range (0.00733712, 0.00833494); } } cell (sg13g2_decap_4) { area : 7.2576; - cell_footprint : "DECAP"; + cell_footprint : "decap"; cell_leakage_power : 98.643; dont_touch : true; dont_use : true; @@ -8658,7 +8658,7 @@ library (sg13g2_stdcell_slow_1p08V_125C) { } cell (sg13g2_decap_8) { area : 12.7008; - cell_footprint : "DECAP"; + cell_footprint : "decap"; cell_leakage_power : 197.301; dont_touch : true; dont_use : true; @@ -8666,7 +8666,7 @@ library (sg13g2_stdcell_slow_1p08V_125C) { } cell (sg13g2_dfrbp_1) { area : 52.6176; - cell_footprint : "dffrr"; + cell_footprint : "dfrbp"; cell_leakage_power : 2633.71; leakage_power () { value : 2300.37; @@ -8723,6 +8723,7 @@ library (sg13g2_stdcell_slow_1p08V_125C) { max_capacitance : 0.3; timing () { related_pin : "CLK"; + sdf_edges : start_edge; timing_sense : non_unate; timing_type : rising_edge; cell_rise (TIMING_DELAY_7x7ds1) { @@ -8780,6 +8781,7 @@ library (sg13g2_stdcell_slow_1p08V_125C) { } timing () { related_pin : "RESET_B"; + sdf_edges : start_edge; timing_sense : positive_unate; timing_type : clear; cell_fall (TIMING_DELAY_7x7ds1) { @@ -8867,6 +8869,7 @@ library (sg13g2_stdcell_slow_1p08V_125C) { max_capacitance : 0.3; timing () { related_pin : "CLK"; + sdf_edges : start_edge; timing_sense : non_unate; timing_type : rising_edge; cell_rise (TIMING_DELAY_7x7ds1) { @@ -8924,6 +8927,7 @@ library (sg13g2_stdcell_slow_1p08V_125C) { } timing () { related_pin : "RESET_B"; + sdf_edges : start_edge; timing_sense : negative_unate; timing_type : preset; cell_rise (TIMING_DELAY_7x7ds1) { @@ -9010,9 +9014,9 @@ library (sg13g2_stdcell_slow_1p08V_125C) { max_transition : 2.5074; capacitance : 0.0026139; rise_capacitance : 0.00278645; - rise_capacitance_range (0.00278645, 0.00278645); + rise_capacitance_range (0.00257555, 0.00296099); fall_capacitance : 0.00235507; - fall_capacitance_range (0.00235507, 0.00235507); + fall_capacitance_range (0.00235507, 0.00284966); timing () { related_pin : "CLK"; timing_type : min_pulse_width; @@ -9138,11 +9142,12 @@ library (sg13g2_stdcell_slow_1p08V_125C) { max_transition : 2.5074; capacitance : 0.00146328; rise_capacitance : 0.00133949; - rise_capacitance_range (0.00133949, 0.00133949); + rise_capacitance_range (0.00126474, 0.00148589); fall_capacitance : 0.00158707; - fall_capacitance_range (0.00158707, 0.00158707); + fall_capacitance_range (0.00158707, 0.00251104); timing () { related_pin : "CLK"; + sdf_edges : both_edges; timing_type : hold_rising; rise_constraint (CONSTRAINT_4x4) { index_1 ("0.0186, 0.51636, 1.263, 2.5074"); @@ -9167,6 +9172,7 @@ library (sg13g2_stdcell_slow_1p08V_125C) { } timing () { related_pin : "CLK"; + sdf_edges : both_edges; timing_type : setup_rising; rise_constraint (CONSTRAINT_4x4) { index_1 ("0.0186, 0.51636, 1.263, 2.5074"); @@ -9254,11 +9260,12 @@ library (sg13g2_stdcell_slow_1p08V_125C) { max_transition : 2.5074; capacitance : 0.00477877; rise_capacitance : 0.00473937; - rise_capacitance_range (0.00473937, 0.00473937); + rise_capacitance_range (0.00432145, 0.00600567); fall_capacitance : 0.00480691; - fall_capacitance_range (0.00480691, 0.00480691); + fall_capacitance_range (0.00451207, 0.00497179); timing () { related_pin : "CLK"; + sdf_edges : both_edges; timing_type : recovery_rising; rise_constraint (CONSTRAINT_4x4) { index_1 ("0.0186, 0.51636, 1.263, 2.5074"); @@ -9273,6 +9280,7 @@ library (sg13g2_stdcell_slow_1p08V_125C) { } timing () { related_pin : "CLK"; + sdf_edges : both_edges; timing_type : removal_rising; rise_constraint (CONSTRAINT_4x4) { index_1 ("0.0186, 0.51636, 1.263, 2.5074"); @@ -9371,14 +9379,14 @@ library (sg13g2_stdcell_slow_1p08V_125C) { } } ff (IQ,IQN) { - clear : "RESET_B'"; + clear : "!RESET_B"; clocked_on : "CLK"; next_state : "D"; } } cell (sg13g2_dfrbp_2) { area : 54.432; - cell_footprint : "dffrr"; + cell_footprint : "dfrbp"; cell_leakage_power : 3213.9; leakage_power () { value : 2889.54; @@ -9435,6 +9443,7 @@ library (sg13g2_stdcell_slow_1p08V_125C) { max_capacitance : 0.6; timing () { related_pin : "CLK"; + sdf_edges : start_edge; timing_sense : non_unate; timing_type : rising_edge; cell_rise (TIMING_DELAY_7x7ds1) { @@ -9492,6 +9501,7 @@ library (sg13g2_stdcell_slow_1p08V_125C) { } timing () { related_pin : "RESET_B"; + sdf_edges : start_edge; timing_sense : positive_unate; timing_type : clear; cell_fall (TIMING_DELAY_7x7ds1) { @@ -9579,6 +9589,7 @@ library (sg13g2_stdcell_slow_1p08V_125C) { max_capacitance : 0.6; timing () { related_pin : "CLK"; + sdf_edges : start_edge; timing_sense : non_unate; timing_type : rising_edge; cell_rise (TIMING_DELAY_7x7ds1) { @@ -9636,6 +9647,7 @@ library (sg13g2_stdcell_slow_1p08V_125C) { } timing () { related_pin : "RESET_B"; + sdf_edges : start_edge; timing_sense : negative_unate; timing_type : preset; cell_rise (TIMING_DELAY_7x7ds1) { @@ -9722,9 +9734,9 @@ library (sg13g2_stdcell_slow_1p08V_125C) { max_transition : 2.5074; capacitance : 0.00262194; rise_capacitance : 0.00279438; - rise_capacitance_range (0.00279438, 0.00279438); + rise_capacitance_range (0.00257938, 0.00297036); fall_capacitance : 0.00236329; - fall_capacitance_range (0.00236329, 0.00236329); + fall_capacitance_range (0.00236329, 0.00285871); timing () { related_pin : "CLK"; timing_type : min_pulse_width; @@ -9850,11 +9862,12 @@ library (sg13g2_stdcell_slow_1p08V_125C) { max_transition : 2.5074; capacitance : 0.00146718; rise_capacitance : 0.00134338; - rise_capacitance_range (0.00134338, 0.00134338); + rise_capacitance_range (0.00126826, 0.00148811); fall_capacitance : 0.00159099; - fall_capacitance_range (0.00159099, 0.00159099); + fall_capacitance_range (0.00159099, 0.00251518); timing () { related_pin : "CLK"; + sdf_edges : both_edges; timing_type : hold_rising; rise_constraint (CONSTRAINT_4x4) { index_1 ("0.0186, 0.51636, 1.263, 2.5074"); @@ -9879,6 +9892,7 @@ library (sg13g2_stdcell_slow_1p08V_125C) { } timing () { related_pin : "CLK"; + sdf_edges : both_edges; timing_type : setup_rising; rise_constraint (CONSTRAINT_4x4) { index_1 ("0.0186, 0.51636, 1.263, 2.5074"); @@ -9966,11 +9980,12 @@ library (sg13g2_stdcell_slow_1p08V_125C) { max_transition : 2.5074; capacitance : 0.00483019; rise_capacitance : 0.0047898; - rise_capacitance_range (0.0047898, 0.0047898); + rise_capacitance_range (0.00437051, 0.00605665); fall_capacitance : 0.00485903; - fall_capacitance_range (0.00485903, 0.00485903); + fall_capacitance_range (0.00455864, 0.00502533); timing () { related_pin : "CLK"; + sdf_edges : both_edges; timing_type : recovery_rising; rise_constraint (CONSTRAINT_4x4) { index_1 ("0.0186, 0.51636, 1.263, 2.5074"); @@ -9985,6 +10000,7 @@ library (sg13g2_stdcell_slow_1p08V_125C) { } timing () { related_pin : "CLK"; + sdf_edges : both_edges; timing_type : removal_rising; rise_constraint (CONSTRAINT_4x4) { index_1 ("0.0186, 0.51636, 1.263, 2.5074"); @@ -10083,7 +10099,7 @@ library (sg13g2_stdcell_slow_1p08V_125C) { } } ff (IQ,IQN) { - clear : "RESET_B'"; + clear : "!RESET_B"; clocked_on : "CLK"; next_state : "D"; } @@ -10147,89 +10163,91 @@ library (sg13g2_stdcell_slow_1p08V_125C) { max_capacitance : 0.3; timing () { related_pin : "CLK"; + sdf_edges : start_edge; timing_sense : non_unate; timing_type : rising_edge; cell_rise (TIMING_DELAY_7x7ds1) { index_1 ("0.0186, 0.0966, 0.174, 0.3294, 0.6408, 1.263, 2.5074"); index_2 ("0.001, 0.0234, 0.039, 0.0648, 0.108, 0.18, 0.3"); values ( \ - "0.241695, 0.343876, 0.411924, 0.523818, 0.710853, 1.02258, 1.5418", \ - "0.285629, 0.387877, 0.455918, 0.567784, 0.754911, 1.06692, 1.58635", \ - "0.319728, 0.422138, 0.490138, 0.602159, 0.789152, 1.10115, 1.62067", \ - "0.374076, 0.476665, 0.544556, 0.656487, 0.843593, 1.15539, 1.67469", \ - "0.451792, 0.554349, 0.622234, 0.734238, 0.921253, 1.23285, 1.75232", \ - "0.561128, 0.663317, 0.731315, 0.843118, 1.03034, 1.34193, 1.86116", \ - "0.70997, 0.812324, 0.880325, 0.992187, 1.17937, 1.49109, 2.01037" \ + "0.241692, 0.343959, 0.411761, 0.523828, 0.710789, 1.0226, 1.54159", \ + "0.285578, 0.3879, 0.455922, 0.567733, 0.755253, 1.06672, 1.58559", \ + "0.319695, 0.422251, 0.490084, 0.602078, 0.789103, 1.1013, 1.62026", \ + "0.374023, 0.476662, 0.544645, 0.656402, 0.843517, 1.15525, 1.67445", \ + "0.451803, 0.554339, 0.622211, 0.734185, 0.921162, 1.23269, 1.75186", \ + "0.561033, 0.663201, 0.73115, 0.843044, 1.03028, 1.34174, 1.86088", \ + "0.709969, 0.812319, 0.880305, 0.992142, 1.17929, 1.49096, 2.01009" \ ); } rise_transition (TIMING_DELAY_7x7ds1) { index_1 ("0.0186, 0.0966, 0.174, 0.3294, 0.6408, 1.263, 2.5074"); index_2 ("0.001, 0.0234, 0.039, 0.0648, 0.108, 0.18, 0.3"); values ( \ - "0.0265069, 0.159417, 0.255807, 0.415514, 0.683163, 1.12993, 1.87425", \ - "0.0266414, 0.159435, 0.255874, 0.415599, 0.683288, 1.12994, 1.87426", \ - "0.0266424, 0.159436, 0.255875, 0.4156, 0.683991, 1.12995, 1.87427", \ - "0.0266434, 0.15946, 0.255876, 0.415601, 0.683992, 1.12996, 1.87514", \ - "0.0267048, 0.159461, 0.255877, 0.415602, 0.683993, 1.12997, 1.87515", \ - "0.027209, 0.159536, 0.255878, 0.415603, 0.683994, 1.13013, 1.87516", \ - "0.028205, 0.159611, 0.255888, 0.415708, 0.683995, 1.13014, 1.87517" \ + "0.0265056, 0.159389, 0.255754, 0.415429, 0.683018, 1.12969, 1.87354", \ + "0.0265215, 0.159418, 0.255785, 0.41543, 0.683512, 1.1297, 1.87355", \ + "0.0265455, 0.159419, 0.255786, 0.415431, 0.683769, 1.1305, 1.87357", \ + "0.0265465, 0.159427, 0.255795, 0.415432, 0.68377, 1.13051, 1.87475", \ + "0.0267047, 0.159428, 0.2558, 0.415548, 0.683771, 1.13052, 1.87476", \ + "0.027185, 0.159488, 0.255801, 0.415549, 0.683772, 1.13053, 1.87477", \ + "0.028135, 0.159641, 0.255836, 0.415623, 0.683773, 1.13054, 1.87478" \ ); } cell_fall (TIMING_DELAY_7x7ds1) { index_1 ("0.0186, 0.0966, 0.174, 0.3294, 0.6408, 1.263, 2.5074"); index_2 ("0.001, 0.0234, 0.039, 0.0648, 0.108, 0.18, 0.3"); values ( \ - "0.240738, 0.330805, 0.388669, 0.483917, 0.643133, 0.90838, 1.35003", \ - "0.284945, 0.374974, 0.432868, 0.527956, 0.687258, 0.952332, 1.39453", \ - "0.318904, 0.409097, 0.467003, 0.562158, 0.721349, 0.986463, 1.42839", \ - "0.372096, 0.462294, 0.520183, 0.615346, 0.77453, 1.03972, 1.48172", \ - "0.445937, 0.536192, 0.594, 0.689267, 0.848444, 1.11352, 1.55557", \ - "0.547071, 0.637161, 0.695004, 0.790245, 0.949431, 1.21455, 1.65638", \ - "0.679172, 0.769323, 0.827219, 0.922402, 1.08158, 1.34685, 1.78847" \ + "0.240798, 0.330793, 0.388591, 0.483901, 0.643062, 0.908327, 1.35007", \ + "0.284711, 0.374872, 0.432757, 0.527885, 0.687264, 0.95241, 1.39434", \ + "0.318932, 0.409041, 0.46685, 0.562105, 0.72124, 0.986351, 1.42892", \ + "0.372083, 0.462281, 0.520172, 0.615337, 0.774521, 1.03971, 1.48172", \ + "0.445924, 0.53618, 0.593989, 0.689258, 0.848436, 1.11351, 1.55556", \ + "0.546974, 0.637099, 0.694994, 0.790136, 0.949374, 1.21451, 1.65643", \ + "0.679208, 0.769314, 0.827211, 0.922396, 1.08158, 1.34684, 1.78851" \ ); } fall_transition (TIMING_DELAY_7x7ds1) { index_1 ("0.0186, 0.0966, 0.174, 0.3294, 0.6408, 1.263, 2.5074"); index_2 ("0.001, 0.0234, 0.039, 0.0648, 0.108, 0.18, 0.3"); values ( \ - "0.0233361, 0.129692, 0.206297, 0.334021, 0.54766, 0.904176, 1.49931", \ - "0.0233371, 0.129693, 0.206337, 0.334022, 0.547661, 0.904219, 1.49932", \ - "0.0233381, 0.129694, 0.206338, 0.334023, 0.54921, 0.904559, 1.49933", \ - "0.0233391, 0.129695, 0.206339, 0.334024, 0.549211, 0.90456, 1.49947", \ - "0.0233401, 0.129696, 0.206412, 0.334046, 0.549212, 0.904561, 1.49948", \ - "0.0233411, 0.129697, 0.206413, 0.334047, 0.549213, 0.904562, 1.49949", \ - "0.0233421, 0.129698, 0.206433, 0.334048, 0.549214, 0.904563, 1.4995" \ + "0.023342, 0.12969, 0.206334, 0.33383, 0.54766, 0.904175, 1.49907", \ + "0.023343, 0.129691, 0.207741, 0.333858, 0.547661, 0.904217, 1.49908", \ + "0.023344, 0.129692, 0.207742, 0.333859, 0.549216, 0.904766, 1.49909", \ + "0.023345, 0.129693, 0.207743, 0.33386, 0.549217, 0.904767, 1.49947", \ + "0.023346, 0.129694, 0.207744, 0.334044, 0.549218, 0.904768, 1.49948", \ + "0.023347, 0.129695, 0.207745, 0.334045, 0.549219, 0.904769, 1.49949", \ + "0.023354, 0.129696, 0.207746, 0.334046, 0.54922, 0.90477, 1.4995" \ ); } } timing () { related_pin : "RESET_B"; + sdf_edges : start_edge; timing_sense : positive_unate; timing_type : clear; cell_fall (TIMING_DELAY_7x7ds1) { index_1 ("0.0186, 0.0966, 0.174, 0.3294, 0.6408, 1.263, 2.5074"); index_2 ("0.001, 0.0234, 0.039, 0.0648, 0.108, 0.18, 0.3"); values ( \ - "0.346535, 0.436293, 0.494252, 0.589568, 0.748769, 1.01395, 1.45601", \ - "0.39107, 0.481105, 0.538895, 0.634096, 0.793582, 1.05859, 1.50043", \ - "0.435199, 0.525039, 0.582924, 0.67815, 0.837442, 1.10263, 1.54467", \ - "0.510403, 0.600303, 0.658214, 0.753531, 0.912748, 1.17806, 1.61989", \ - "0.626985, 0.716909, 0.774812, 0.869999, 1.02925, 1.29443, 1.73634", \ - "0.79333, 0.883295, 0.94118, 1.03655, 1.19575, 1.46093, 1.90284", \ - "1.02945, 1.11956, 1.17748, 1.27286, 1.43211, 1.69725, 2.13913" \ + "0.346447, 0.436278, 0.49416, 0.589487, 0.748687, 1.01388, 1.45604", \ + "0.391188, 0.48102, 0.538838, 0.634075, 0.793484, 1.05867, 1.5007", \ + "0.435187, 0.525041, 0.58291, 0.678136, 0.838043, 1.10262, 1.54469", \ + "0.510221, 0.600266, 0.658067, 0.753384, 0.912701, 1.1779, 1.6198", \ + "0.626972, 0.716896, 0.7748, 0.869989, 1.02924, 1.29441, 1.73634", \ + "0.793316, 0.883281, 0.941168, 1.03655, 1.19574, 1.46092, 1.90283", \ + "1.02944, 1.11954, 1.17747, 1.27285, 1.4321, 1.69723, 2.13912" \ ); } fall_transition (TIMING_DELAY_7x7ds1) { index_1 ("0.0186, 0.0966, 0.174, 0.3294, 0.6408, 1.263, 2.5074"); index_2 ("0.001, 0.0234, 0.039, 0.0648, 0.108, 0.18, 0.3"); values ( \ - "0.0230409, 0.129414, 0.206196, 0.333766, 0.547652, 0.904224, 1.49848", \ - "0.0230419, 0.129432, 0.206208, 0.333785, 0.547653, 0.904225, 1.49849", \ - "0.0230429, 0.12949, 0.206303, 0.333875, 0.548019, 0.904665, 1.4985", \ - "0.023084, 0.129491, 0.206304, 0.333876, 0.54802, 0.904666, 1.49854", \ - "0.023093, 0.129512, 0.206305, 0.333921, 0.548021, 0.904667, 1.49927", \ - "0.023261, 0.129513, 0.206332, 0.333938, 0.548022, 0.904668, 1.49928", \ - "0.023588, 0.129525, 0.206397, 0.333939, 0.548023, 0.904669, 1.49929" \ + "0.02301, 0.129384, 0.206198, 0.333755, 0.547651, 0.904871, 1.49849", \ + "0.0230274, 0.1294, 0.206202, 0.333784, 0.547652, 0.904872, 1.4985", \ + "0.02303, 0.129484, 0.206302, 0.333874, 0.548505, 0.904873, 1.49851", \ + "0.0230828, 0.129533, 0.206303, 0.333875, 0.548506, 0.904874, 1.49856", \ + "0.023091, 0.129534, 0.206304, 0.33392, 0.548507, 0.904875, 1.49927", \ + "0.023259, 0.129535, 0.20633, 0.333921, 0.548508, 0.904876, 1.49928", \ + "0.023585, 0.129536, 0.206395, 0.333922, 0.548509, 0.904877, 1.49929" \ ); } } @@ -10239,26 +10257,26 @@ library (sg13g2_stdcell_slow_1p08V_125C) { index_1 ("0.0186, 0.0966, 0.174, 0.3294, 0.6408, 1.263, 2.5074"); index_2 ("0.001, 0.0234, 0.039, 0.0648, 0.108, 0.18, 0.3"); values ( \ - "0.0199953, 0.0203, 0.0203043, 0.0202745, 0.0201854, 0.0201878, 0.0200927", \ - "0.0196336, 0.0199587, 0.0199283, 0.0199006, 0.0198229, 0.0196907, 0.0197386", \ - "0.019508, 0.0198652, 0.0198883, 0.019824, 0.0197776, 0.0195725, 0.0196526", \ - "0.0194591, 0.019756, 0.0197787, 0.0198836, 0.0196951, 0.0195052, 0.0195779", \ - "0.0197072, 0.0200647, 0.0200713, 0.020047, 0.0200269, 0.0197649, 0.0206857", \ - "0.020574, 0.0208659, 0.0208726, 0.020935, 0.0208619, 0.0206243, 0.0209346", \ - "0.0225285, 0.0228108, 0.0228703, 0.0228441, 0.0228296, 0.0228765, 0.0225682" \ + "0.0199945, 0.0203122, 0.020289, 0.0202764, 0.0201718, 0.0200437, 0.0200783", \ + "0.0196322, 0.019957, 0.0199403, 0.0199031, 0.0198633, 0.0197047, 0.0196994", \ + "0.0195012, 0.0198746, 0.0198807, 0.0198168, 0.019772, 0.0196284, 0.0196539", \ + "0.0194509, 0.0197554, 0.0197871, 0.0198816, 0.0197842, 0.019505, 0.0195783", \ + "0.0197104, 0.0200675, 0.0200711, 0.0200463, 0.0200265, 0.0197638, 0.0199636", \ + "0.020587, 0.0208806, 0.0208825, 0.0209553, 0.0209204, 0.0206762, 0.0208786", \ + "0.0225255, 0.0228113, 0.0228715, 0.0228442, 0.0228234, 0.0228701, 0.0224849" \ ); } fall_power (POWER_7x7ds1) { index_1 ("0.0186, 0.0966, 0.174, 0.3294, 0.6408, 1.263, 2.5074"); index_2 ("0.001, 0.0234, 0.039, 0.0648, 0.108, 0.18, 0.3"); values ( \ - "0.0206891, 0.0210323, 0.021036, 0.0210189, 0.0209318, 0.0207809, 0.0205217", \ - "0.0203885, 0.0207395, 0.0207414, 0.0206852, 0.0206169, 0.0204861, 0.0202064", \ - "0.0203762, 0.0207507, 0.0208324, 0.0207105, 0.0207308, 0.0204797, 0.020224", \ - "0.0204442, 0.0207909, 0.020777, 0.0208119, 0.0206982, 0.0205296, 0.0202876", \ - "0.0208745, 0.0212489, 0.0212756, 0.0212849, 0.0211198, 0.0211983, 0.0207826", \ - "0.0217598, 0.0220935, 0.0221542, 0.0221297, 0.0221551, 0.0219205, 0.0216074", \ - "0.0238251, 0.0241698, 0.0242001, 0.0242253, 0.0242271, 0.0241642, 0.024183" \ + "0.0206892, 0.0210327, 0.021034, 0.021006, 0.0209226, 0.0207823, 0.0205346", \ + "0.0203794, 0.0207429, 0.0208193, 0.0206832, 0.0206275, 0.0204902, 0.0202088", \ + "0.0203781, 0.0207365, 0.0208075, 0.0207132, 0.0207212, 0.0204658, 0.0202535", \ + "0.0204445, 0.020792, 0.0207783, 0.0208132, 0.0206999, 0.0205316, 0.0202894", \ + "0.0208774, 0.0212502, 0.0212771, 0.0212862, 0.0211216, 0.0212019, 0.0207846", \ + "0.0217696, 0.0221099, 0.0221718, 0.0221501, 0.0221522, 0.0218963, 0.0217218", \ + "0.0238271, 0.0241708, 0.0241997, 0.0242194, 0.024229, 0.024167, 0.0242073" \ ); } } @@ -10273,13 +10291,13 @@ library (sg13g2_stdcell_slow_1p08V_125C) { index_1 ("0.0186, 0.0966, 0.174, 0.3294, 0.6408, 1.263, 2.5074"); index_2 ("0.001, 0.0234, 0.039, 0.0648, 0.108, 0.18, 0.3"); values ( \ - "0.0128996, 0.0132125, 0.0132334, 0.0132141, 0.0131308, 0.0129922, 0.0127024", \ - "0.0127899, 0.0131066, 0.0131087, 0.0130733, 0.0130311, 0.0128871, 0.0125738", \ - "0.0126721, 0.0130445, 0.0130188, 0.0129672, 0.0129069, 0.0127581, 0.0124866", \ - "0.0126332, 0.0129633, 0.0129656, 0.0130343, 0.0128821, 0.0127307, 0.0124633", \ - "0.0128537, 0.0131855, 0.0131871, 0.0131314, 0.0131353, 0.0131103, 0.0127639", \ - "0.0131051, 0.0134299, 0.0134339, 0.0135049, 0.0134292, 0.0131779, 0.0134806", \ - "0.0139256, 0.0142537, 0.0142515, 0.0143147, 0.0142897, 0.0143288, 0.0140924" \ + "0.0128883, 0.0132081, 0.0132205, 0.0131973, 0.0131176, 0.01301, 0.0126935", \ + "0.0128002, 0.0131038, 0.013107, 0.0130728, 0.0130282, 0.0128708, 0.0126206", \ + "0.0126773, 0.0130489, 0.0130239, 0.0129725, 0.0129544, 0.0127642, 0.0124931", \ + "0.012625, 0.0129674, 0.0129605, 0.0130232, 0.0128897, 0.0127287, 0.012465", \ + "0.0128567, 0.0131872, 0.0132063, 0.0131337, 0.0131361, 0.0131127, 0.0127884", \ + "0.0131091, 0.0134344, 0.0134374, 0.0135108, 0.0134324, 0.0131607, 0.0134851", \ + "0.013927, 0.0142554, 0.0142528, 0.0143261, 0.014292, 0.0143626, 0.0139922" \ ); } } @@ -10288,11 +10306,11 @@ library (sg13g2_stdcell_slow_1p08V_125C) { clock : true; direction : "input"; max_transition : 2.5074; - capacitance : 0.00258673; - rise_capacitance : 0.00278533; - rise_capacitance_range (0.00278533, 0.00278533); - fall_capacitance : 0.00235504; - fall_capacitance_range (0.00235504, 0.00235504); + capacitance : 0.00258675; + rise_capacitance : 0.00278519; + rise_capacitance_range (0.00257383, 0.00296084); + fall_capacitance : 0.00235524; + fall_capacitance_range (0.00235524, 0.00284967); timing () { related_pin : "CLK"; timing_type : min_pulse_width; @@ -10314,13 +10332,13 @@ library (sg13g2_stdcell_slow_1p08V_125C) { rise_power (passive_POWER_7x1ds1) { index_1 ("0.0186, 0.0966, 0.174, 0.3294, 0.6408, 1.263, 2.5074"); values ( \ - "0.00889184, 0.00852655, 0.00848718, 0.00846546, 0.00882867, 0.00958228, 0.0115326" \ + "0.00889507, 0.00853049, 0.00848786, 0.00846404, 0.0088287, 0.00958256, 0.0115304" \ ); } fall_power (passive_POWER_7x1ds1) { index_1 ("0.0186, 0.0966, 0.174, 0.3294, 0.6408, 1.263, 2.5074"); values ( \ - "0.0211425, 0.0208094, 0.0206882, 0.0207326, 0.0210372, 0.0217204, 0.0235918" \ + "0.0211455, 0.0208165, 0.0206923, 0.0207307, 0.0210368, 0.0217215, 0.0235909" \ ); } } @@ -10334,7 +10352,7 @@ library (sg13g2_stdcell_slow_1p08V_125C) { fall_power (passive_POWER_7x1ds1) { index_1 ("0.0186, 0.0966, 0.174, 0.3294, 0.6408, 1.263, 2.5074"); values ( \ - "0.0167414, 0.0163999, 0.0162829, 0.0163273, 0.0166346, 0.0173146, 0.019186" \ + "0.0167398, 0.0164187, 0.0162866, 0.0163221, 0.0166347, 0.0173184, 0.0191861" \ ); } } @@ -10343,13 +10361,13 @@ library (sg13g2_stdcell_slow_1p08V_125C) { rise_power (passive_POWER_7x1ds1) { index_1 ("0.0186, 0.0966, 0.174, 0.3294, 0.6408, 1.263, 2.5074"); values ( \ - "0.00925474, 0.00890685, 0.0088845, 0.00886992, 0.00921754, 0.00995497, 0.0119187" \ + "0.00926864, 0.00891117, 0.00887904, 0.00886787, 0.0092169, 0.00995512, 0.011922" \ ); } fall_power (passive_POWER_7x1ds1) { index_1 ("0.0186, 0.0966, 0.174, 0.3294, 0.6408, 1.263, 2.5074"); values ( \ - "0.00871229, 0.00839571, 0.00833499, 0.00839705, 0.00872641, 0.00943875, 0.0113358" \ + "0.00872121, 0.00839445, 0.00833511, 0.00840086, 0.008725, 0.00943836, 0.011336" \ ); } } @@ -10363,7 +10381,7 @@ library (sg13g2_stdcell_slow_1p08V_125C) { fall_power (passive_POWER_7x1ds1) { index_1 ("0.0186, 0.0966, 0.174, 0.3294, 0.6408, 1.263, 2.5074"); values ( \ - "0.028893, 0.0243665, 0.0242542, 0.0240365, 0.0242463, 0.0250284, 0.0270293" \ + "0.0300715, 0.0243634, 0.0242574, 0.0240429, 0.0242468, 0.0250307, 0.0270411" \ ); } } @@ -10372,13 +10390,13 @@ library (sg13g2_stdcell_slow_1p08V_125C) { rise_power (passive_POWER_7x1ds1) { index_1 ("0.0186, 0.0966, 0.174, 0.3294, 0.6408, 1.263, 2.5074"); values ( \ - "0.00875736, 0.00839794, 0.00836799, 0.00835305, 0.00870647, 0.00944629, 0.0114143" \ + "0.00875916, 0.00839784, 0.00836224, 0.00834933, 0.00870674, 0.00944353, 0.0114146" \ ); } fall_power (passive_POWER_7x1ds1) { index_1 ("0.0186, 0.0966, 0.174, 0.3294, 0.6408, 1.263, 2.5074"); values ( \ - "0.00864535, 0.0083231, 0.00826122, 0.00834033, 0.00863682, 0.00937083, 0.0112597" \ + "0.00865069, 0.00832669, 0.00826163, 0.00833485, 0.00864075, 0.0093713, 0.0112599" \ ); } } @@ -10387,13 +10405,13 @@ library (sg13g2_stdcell_slow_1p08V_125C) { rise_power (passive_POWER_7x1ds1) { index_1 ("0.0186, 0.0966, 0.174, 0.3294, 0.6408, 1.263, 2.5074"); values ( \ - "0.00916178, 0.00879981, 0.0087735, 0.00875177, 0.00910096, 0.00984059, 0.0118008" \ + "0.00915813, 0.00879884, 0.00876625, 0.00875787, 0.00910365, 0.00983956, 0.0118" \ ); } fall_power (passive_POWER_7x1ds1) { index_1 ("0.0186, 0.0966, 0.174, 0.3294, 0.6408, 1.263, 2.5074"); values ( \ - "0.00868071, 0.00836064, 0.00830086, 0.00835761, 0.00869035, 0.00940442, 0.0113008" \ + "0.00868617, 0.00836205, 0.00830091, 0.00836047, 0.0086909, 0.00940295, 0.0113011" \ ); } } @@ -10401,13 +10419,13 @@ library (sg13g2_stdcell_slow_1p08V_125C) { rise_power (passive_POWER_7x1ds1) { index_1 ("0.0186, 0.0966, 0.174, 0.3294, 0.6408, 1.263, 2.5074"); values ( \ - "0.00889184, 0.00852655, 0.00848718, 0.00846546, 0.00882867, 0.00958228, 0.0115326" \ + "0.00889507, 0.00853049, 0.00848786, 0.00846404, 0.0088287, 0.00958256, 0.0115304" \ ); } fall_power (passive_POWER_7x1ds1) { index_1 ("0.0186, 0.0966, 0.174, 0.3294, 0.6408, 1.263, 2.5074"); values ( \ - "0.0167414, 0.0163999, 0.0162829, 0.0163273, 0.0166346, 0.0173146, 0.019186" \ + "0.0167398, 0.0164187, 0.0162866, 0.0163221, 0.0166347, 0.0173184, 0.0191861" \ ); } } @@ -10416,19 +10434,20 @@ library (sg13g2_stdcell_slow_1p08V_125C) { direction : "input"; nextstate_type : "data"; max_transition : 2.5074; - capacitance : 0.00134519; - rise_capacitance : 0.00133529; - rise_capacitance_range (0.00133529, 0.00133529); - fall_capacitance : 0.00135509; - fall_capacitance_range (0.00135509, 0.00135509); + capacitance : 0.00134516; + rise_capacitance : 0.00133522; + rise_capacitance_range (0.00126446, 0.00148588); + fall_capacitance : 0.0013551; + fall_capacitance_range (0.0013551, 0.00169167); timing () { related_pin : "CLK"; + sdf_edges : both_edges; timing_type : hold_rising; rise_constraint (CONSTRAINT_4x4) { index_1 ("0.0186, 0.51636, 1.263, 2.5074"); index_2 ("0.0186, 0.51636, 1.263, 2.5074"); values ( \ - "-0.0978076, -0.0202131, 0.0318604, 0.0855195", \ + "-0.0978076, -0.0227089, 0.0318604, 0.0855195", \ "-0.279286, -0.198624, -0.143266, -0.0846213", \ "-0.409912, -0.341881, -0.283328, -0.22188", \ "-0.541543, -0.481673, -0.430684, -0.374845" \ @@ -10438,7 +10457,7 @@ library (sg13g2_stdcell_slow_1p08V_125C) { index_1 ("0.0186, 0.51636, 1.263, 2.5074"); index_2 ("0.0186, 0.51636, 1.263, 2.5074"); values ( \ - "-0.0489038, 0.0945949, 0.199026, 0.314881", \ + "-0.0489038, 0.0945949, 0.199026, 0.312182", \ "-0.249336, -0.106951, 0.000967038, 0.121554", \ "-0.404768, -0.27632, -0.175394, -0.0495581", \ "-0.568527, -0.467928, -0.374185, -0.256784" \ @@ -10447,6 +10466,7 @@ library (sg13g2_stdcell_slow_1p08V_125C) { } timing () { related_pin : "CLK"; + sdf_edges : both_edges; timing_type : setup_rising; rise_constraint (CONSTRAINT_4x4) { index_1 ("0.0186, 0.51636, 1.263, 2.5074"); @@ -10474,13 +10494,13 @@ library (sg13g2_stdcell_slow_1p08V_125C) { rise_power (passive_POWER_7x1ds1) { index_1 ("0.0186, 0.0966, 0.174, 0.3294, 0.6408, 1.263, 2.5074"); values ( \ - "0.00145132, 0.00133957, 0.00132275, 0.00135974, 0.00147773, 0.00178345, 0.00248621" \ + "0.00145011, 0.0013395, 0.0013225, 0.00135888, 0.0014777, 0.00178357, 0.00248614" \ ); } fall_power (passive_POWER_7x1ds1) { index_1 ("0.0186, 0.0966, 0.174, 0.3294, 0.6408, 1.263, 2.5074"); values ( \ - "0.00108957, 0.000964331, 0.00095539, 0.000978066, 0.00114291, 0.00141627, 0.00209744" \ + "0.00109038, 0.000965698, 0.000956211, 0.00097846, 0.00114331, 0.00141123, 0.00209798" \ ); } } @@ -10489,13 +10509,13 @@ library (sg13g2_stdcell_slow_1p08V_125C) { rise_power (passive_POWER_7x1ds1) { index_1 ("0.0186, 0.0966, 0.174, 0.3294, 0.6408, 1.263, 2.5074"); values ( \ - "0.00946202, 0.00944182, 0.00938342, 0.00938137, 0.00942788, 0.0097029, 0.0104119" \ + "0.00945179, 0.00942724, 0.00938829, 0.00938096, 0.00942999, 0.0097026, 0.0104119" \ ); } fall_power (passive_POWER_7x1ds1) { index_1 ("0.0186, 0.0966, 0.174, 0.3294, 0.6408, 1.263, 2.5074"); values ( \ - "0.00710737, 0.0070571, 0.00697927, 0.00696499, 0.00703479, 0.00730709, 0.0080615" \ + "0.00711333, 0.00703671, 0.00698371, 0.00696179, 0.00703524, 0.00730755, 0.00806168" \ ); } } @@ -10504,13 +10524,13 @@ library (sg13g2_stdcell_slow_1p08V_125C) { rise_power (passive_POWER_7x1ds1) { index_1 ("0.0186, 0.0966, 0.174, 0.3294, 0.6408, 1.263, 2.5074"); values ( \ - "-4.65294e-05, -5.08558e-05, -5.01926e-05, -4.9967e-05, -4.99304e-05, -5.16965e-05, -5.24495e-05" \ + "-4.59019e-05, -5.06312e-05, -5.00995e-05, -4.9967e-05, -4.99303e-05, -5.1678e-05, -5.24497e-05" \ ); } fall_power (passive_POWER_7x1ds1) { index_1 ("0.0186, 0.0966, 0.174, 0.3294, 0.6408, 1.263, 2.5074"); values ( \ - "4.65294e-05, 5.08558e-05, 5.01926e-05, 4.9967e-05, 4.99304e-05, 5.16965e-05, 5.24495e-05" \ + "4.59019e-05, 5.06312e-05, 5.00995e-05, 4.9967e-05, 4.99303e-05, 5.1678e-05, 5.24497e-05" \ ); } } @@ -10518,13 +10538,13 @@ library (sg13g2_stdcell_slow_1p08V_125C) { rise_power (passive_POWER_7x1ds1) { index_1 ("0.0186, 0.0966, 0.174, 0.3294, 0.6408, 1.263, 2.5074"); values ( \ - "0.00145132, 0.00133957, 0.00132275, 0.00135974, 0.00147773, 0.00178345, 0.00248621" \ + "0.00145011, 0.0013395, 0.0013225, 0.00135888, 0.0014777, 0.00178357, 0.00248614" \ ); } fall_power (passive_POWER_7x1ds1) { index_1 ("0.0186, 0.0966, 0.174, 0.3294, 0.6408, 1.263, 2.5074"); values ( \ - "0.00108957, 0.000964331, 0.00095539, 0.000978066, 0.00114291, 0.00141627, 0.00209744" \ + "0.00109038, 0.000965698, 0.000956211, 0.00097846, 0.00114331, 0.00141123, 0.00209798" \ ); } } @@ -10532,13 +10552,14 @@ library (sg13g2_stdcell_slow_1p08V_125C) { pin (RESET_B) { direction : "input"; max_transition : 2.5074; - capacitance : 0.00474057; - rise_capacitance : 0.00465687; - rise_capacitance_range (0.00465687, 0.00465687); - fall_capacitance : 0.00481032; - fall_capacitance_range (0.00481032, 0.00481032); + capacitance : 0.00474071; + rise_capacitance : 0.00465698; + rise_capacitance_range (0.00430454, 0.00531221); + fall_capacitance : 0.00481048; + fall_capacitance_range (0.00450852, 0.00496871); timing () { related_pin : "CLK"; + sdf_edges : both_edges; timing_type : recovery_rising; rise_constraint (CONSTRAINT_4x4) { index_1 ("0.0186, 0.51636, 1.263, 2.5074"); @@ -10553,12 +10574,13 @@ library (sg13g2_stdcell_slow_1p08V_125C) { } timing () { related_pin : "CLK"; + sdf_edges : both_edges; timing_type : removal_rising; rise_constraint (CONSTRAINT_4x4) { index_1 ("0.0186, 0.51636, 1.263, 2.5074"); index_2 ("0.0186, 0.51636, 1.263, 2.5074"); values ( \ - "-0.166273, -0.0826087, -0.0272905, 0.0261555", \ + "-0.166273, -0.0826087, -0.0298623, 0.0288539", \ "-0.359152, -0.264832, -0.211448, -0.153346", \ "-0.535929, -0.433665, -0.375073, -0.315104", \ "-0.738524, -0.632868, -0.571931, -0.510616" \ @@ -10580,13 +10602,13 @@ library (sg13g2_stdcell_slow_1p08V_125C) { rise_power (passive_POWER_7x1ds1) { index_1 ("0.0186, 0.0966, 0.174, 0.3294, 0.6408, 1.263, 2.5074"); values ( \ - "0.00283098, 0.00274396, 0.00271725, 0.00271337, 0.00273207, 0.00289191, 0.00343117" \ + "0.00282912, 0.00274276, 0.00271808, 0.00271374, 0.00273257, 0.00289184, 0.00343216" \ ); } fall_power (passive_POWER_7x1ds1) { index_1 ("0.0186, 0.0966, 0.174, 0.3294, 0.6408, 1.263, 2.5074"); values ( \ - "0.0205256, 0.0201554, 0.0199577, 0.0198111, 0.0200663, 0.0205865, 0.0223025" \ + "0.020536, 0.02017, 0.0199486, 0.01982, 0.0200664, 0.0205866, 0.0223027" \ ); } } @@ -10595,13 +10617,13 @@ library (sg13g2_stdcell_slow_1p08V_125C) { rise_power (passive_POWER_7x1ds1) { index_1 ("0.0186, 0.0966, 0.174, 0.3294, 0.6408, 1.263, 2.5074"); values ( \ - "0.00092813, 0.000921571, 0.000923763, 0.000919029, 0.000916766, 0.000921703, 0.000923678" \ + "0.000921847, 0.000922894, 0.000922518, 0.00091998, 0.000917505, 0.000920885, 0.000924615" \ ); } fall_power (passive_POWER_7x1ds1) { index_1 ("0.0186, 0.0966, 0.174, 0.3294, 0.6408, 1.263, 2.5074"); values ( \ - "-0.000406984, -0.000515254, -0.000545693, -0.000571961, -0.000595511, -0.000613404, -0.000632936" \ + "-0.000407867, -0.000516505, -0.000545419, -0.000571596, -0.000595909, -0.000613023, -0.000633001" \ ); } } @@ -10610,13 +10632,13 @@ library (sg13g2_stdcell_slow_1p08V_125C) { rise_power (passive_POWER_7x1ds1) { index_1 ("0.0186, 0.0966, 0.174, 0.3294, 0.6408, 1.263, 2.5074"); values ( \ - "0.011194, 0.0110473, 0.0109679, 0.0109189, 0.0109286, 0.0111402, 0.0118975" \ + "0.0111886, 0.0110545, 0.0109621, 0.0109179, 0.0109287, 0.0111387, 0.0118971" \ ); } fall_power (passive_POWER_7x1ds1) { index_1 ("0.0186, 0.0966, 0.174, 0.3294, 0.6408, 1.263, 2.5074"); values ( \ - "0.00746962, 0.00720363, 0.0071085, 0.00700432, 0.00699845, 0.00724018, 0.00811054" \ + "0.0074778, 0.00720324, 0.007104, 0.00700446, 0.0069974, 0.00723773, 0.00810972" \ ); } } @@ -10625,13 +10647,13 @@ library (sg13g2_stdcell_slow_1p08V_125C) { rise_power (passive_POWER_7x1ds1) { index_1 ("0.0186, 0.0966, 0.174, 0.3294, 0.6408, 1.263, 2.5074"); values ( \ - "0.000885302, 0.000886923, 0.000885512, 0.000881554, 0.000883617, 0.000884828, 0.000883197" \ + "0.000887416, 0.000885871, 0.00088742, 0.000883782, 0.000881803, 0.000885219, 0.000883467" \ ); } fall_power (passive_POWER_7x1ds1) { index_1 ("0.0186, 0.0966, 0.174, 0.3294, 0.6408, 1.263, 2.5074"); values ( \ - "-0.000629003, -0.000711647, -0.000737433, -0.000758506, -0.000774591, -0.000788307, -0.00080494" \ + "-0.000627917, -0.00071121, -0.000738571, -0.000759788, -0.000774639, -0.000789048, -0.000804651" \ ); } } @@ -10639,19 +10661,19 @@ library (sg13g2_stdcell_slow_1p08V_125C) { rise_power (passive_POWER_7x1ds1) { index_1 ("0.0186, 0.0966, 0.174, 0.3294, 0.6408, 1.263, 2.5074"); values ( \ - "0.00283098, 0.00274396, 0.00271725, 0.00271337, 0.00273207, 0.00289191, 0.00343117" \ + "0.00282912, 0.00274276, 0.00271808, 0.00271374, 0.00273257, 0.00289184, 0.00343216" \ ); } fall_power (passive_POWER_7x1ds1) { index_1 ("0.0186, 0.0966, 0.174, 0.3294, 0.6408, 1.263, 2.5074"); values ( \ - "0.00746962, 0.00720363, 0.0071085, 0.00700432, 0.00699845, 0.00724018, 0.00811054" \ + "0.0074778, 0.00720324, 0.007104, 0.00700446, 0.0069974, 0.00723773, 0.00810972" \ ); } } } ff (IQ,IQN) { - clear : "RESET_B'"; + clear : "!RESET_B"; clocked_on : "CLK"; next_state : "D"; } @@ -10715,13 +10737,14 @@ library (sg13g2_stdcell_slow_1p08V_125C) { max_capacitance : 0.6; timing () { related_pin : "CLK"; + sdf_edges : start_edge; timing_sense : non_unate; timing_type : rising_edge; cell_rise (TIMING_DELAY_7x7ds1) { index_1 ("0.0186, 0.0966, 0.174, 0.3294, 0.6408, 1.263, 2.5074"); index_2 ("0.001, 0.0468, 0.078, 0.1296, 0.216, 0.36, 0.6"); values ( \ - "0.259189, 0.37065, 0.438655, 0.55076, 0.737992, 1.04979, 1.56989", \ + "0.259329, 0.370675, 0.438673, 0.550761, 0.737903, 1.05003, 1.56987", \ "0.303063, 0.414594, 0.482639, 0.594619, 0.78215, 1.0937, 1.6137", \ "0.337158, 0.448665, 0.516644, 0.628612, 0.815889, 1.12874, 1.64765", \ "0.391341, 0.502852, 0.570893, 0.682846, 0.870122, 1.18217, 1.70275", \ @@ -10734,11 +10757,11 @@ library (sg13g2_stdcell_slow_1p08V_125C) { index_1 ("0.0186, 0.0966, 0.174, 0.3294, 0.6408, 1.263, 2.5074"); index_2 ("0.001, 0.0468, 0.078, 0.1296, 0.216, 0.36, 0.6"); values ( \ - "0.0297077, 0.16116, 0.257153, 0.416965, 0.685112, 1.13195, 1.87663", \ - "0.0297087, 0.161161, 0.257381, 0.416966, 0.68518, 1.13196, 1.87664", \ - "0.0297097, 0.161184, 0.257382, 0.418049, 0.685695, 1.13271, 1.87665", \ - "0.0297107, 0.161185, 0.257383, 0.41805, 0.685696, 1.13272, 1.87857", \ - "0.0298488, 0.161186, 0.257384, 0.418051, 0.685697, 1.13273, 1.87858", \ + "0.0296137, 0.161186, 0.257153, 0.416965, 0.684918, 1.13195, 1.87663", \ + "0.0296397, 0.161187, 0.257381, 0.416966, 0.68518, 1.13196, 1.87664", \ + "0.0296407, 0.161188, 0.257382, 0.418049, 0.685695, 1.13271, 1.87665", \ + "0.0297097, 0.161189, 0.257383, 0.41805, 0.685696, 1.13272, 1.87857", \ + "0.0298488, 0.16119, 0.257384, 0.418051, 0.685697, 1.13273, 1.87858", \ "0.030204, 0.16123, 0.257385, 0.418052, 0.685698, 1.13274, 1.87859", \ "0.031289, 0.161282, 0.257386, 0.418053, 0.685699, 1.13275, 1.8786" \ ); @@ -10747,7 +10770,7 @@ library (sg13g2_stdcell_slow_1p08V_125C) { index_1 ("0.0186, 0.0966, 0.174, 0.3294, 0.6408, 1.263, 2.5074"); index_2 ("0.001, 0.0468, 0.078, 0.1296, 0.216, 0.36, 0.6"); values ( \ - "0.258963, 0.359848, 0.418165, 0.513665, 0.673418, 0.938734, 1.38109", \ + "0.258975, 0.359847, 0.418128, 0.513646, 0.673166, 0.938602, 1.38087", \ "0.302954, 0.404013, 0.462335, 0.558493, 0.717296, 0.983112, 1.42528", \ "0.33718, 0.43816, 0.496409, 0.59193, 0.751463, 1.01689, 1.46008", \ "0.390287, 0.49122, 0.549527, 0.64506, 0.804514, 1.07002, 1.51299", \ @@ -10760,11 +10783,11 @@ library (sg13g2_stdcell_slow_1p08V_125C) { index_1 ("0.0186, 0.0966, 0.174, 0.3294, 0.6408, 1.263, 2.5074"); index_2 ("0.001, 0.0468, 0.078, 0.1296, 0.216, 0.36, 0.6"); values ( \ - "0.0270352, 0.134417, 0.210366, 0.337775, 0.551765, 0.908701, 1.50364", \ - "0.0270362, 0.134418, 0.210627, 0.338405, 0.551798, 0.908704, 1.50365", \ - "0.0270372, 0.134419, 0.210628, 0.338406, 0.551799, 0.908839, 1.50523", \ - "0.0270382, 0.13442, 0.210629, 0.338407, 0.551832, 0.909571, 1.50528", \ - "0.0270392, 0.134421, 0.21063, 0.338408, 0.551833, 0.909572, 1.50529", \ + "0.0270342, 0.134373, 0.210527, 0.337774, 0.55177, 0.908746, 1.50344", \ + "0.0270352, 0.134374, 0.210627, 0.338405, 0.551798, 0.908747, 1.50364", \ + "0.0270362, 0.134393, 0.210628, 0.338406, 0.551799, 0.908839, 1.50523", \ + "0.0270372, 0.134412, 0.210629, 0.338407, 0.551832, 0.909571, 1.50528", \ + "0.0270382, 0.134413, 0.21063, 0.338408, 0.551833, 0.909572, 1.50529", \ "0.02705, 0.134437, 0.210631, 0.338409, 0.551841, 0.909573, 1.5053", \ "0.027051, 0.134438, 0.210632, 0.33841, 0.551842, 0.909574, 1.50531" \ ); @@ -10772,14 +10795,15 @@ library (sg13g2_stdcell_slow_1p08V_125C) { } timing () { related_pin : "RESET_B"; + sdf_edges : start_edge; timing_sense : positive_unate; timing_type : clear; cell_fall (TIMING_DELAY_7x7ds1) { index_1 ("0.0186, 0.0966, 0.174, 0.3294, 0.6408, 1.263, 2.5074"); index_2 ("0.001, 0.0468, 0.078, 0.1296, 0.216, 0.36, 0.6"); values ( \ - "0.362637, 0.463082, 0.521432, 0.617012, 0.776637, 1.0422, 1.48456", \ - "0.407241, 0.507744, 0.566047, 0.661638, 0.821176, 1.08669, 1.52906", \ + "0.362637, 0.463083, 0.521372, 0.617012, 0.776772, 1.04221, 1.48456", \ + "0.407283, 0.507678, 0.566049, 0.661711, 0.821176, 1.0867, 1.52906", \ "0.451399, 0.55184, 0.610151, 0.70566, 0.865618, 1.13095, 1.57344", \ "0.526438, 0.626903, 0.685227, 0.78093, 0.940497, 1.20614, 1.6496", \ "0.643159, 0.743633, 0.801913, 0.897543, 1.05704, 1.32246, 1.76482", \ @@ -10791,12 +10815,12 @@ library (sg13g2_stdcell_slow_1p08V_125C) { index_1 ("0.0186, 0.0966, 0.174, 0.3294, 0.6408, 1.263, 2.5074"); index_2 ("0.001, 0.0468, 0.078, 0.1296, 0.216, 0.36, 0.6"); values ( \ - "0.0266284, 0.134315, 0.210352, 0.337715, 0.55176, 0.908842, 1.5045", \ - "0.0266391, 0.134316, 0.210353, 0.337821, 0.551786, 0.908843, 1.50451", \ - "0.0266397, 0.134317, 0.210448, 0.338814, 0.552336, 0.908844, 1.50456", \ - "0.0266592, 0.134318, 0.210449, 0.338815, 0.552337, 0.909158, 1.50584", \ - "0.0266602, 0.134319, 0.21045, 0.338816, 0.552338, 0.909201, 1.50585", \ - "0.026795, 0.13432, 0.210451, 0.338817, 0.552339, 0.909202, 1.50586", \ + "0.0266287, 0.134314, 0.210353, 0.337715, 0.551765, 0.908844, 1.50449", \ + "0.0266297, 0.134315, 0.210354, 0.337842, 0.551786, 0.908845, 1.5045", \ + "0.0266397, 0.134316, 0.210448, 0.338814, 0.552336, 0.908846, 1.50456", \ + "0.0266592, 0.134317, 0.210449, 0.338815, 0.552337, 0.909158, 1.50584", \ + "0.0266602, 0.134318, 0.21045, 0.338816, 0.552338, 0.909201, 1.50585", \ + "0.026795, 0.134319, 0.210451, 0.338817, 0.552339, 0.909202, 1.50586", \ "0.027051, 0.134363, 0.210452, 0.338818, 0.55234, 0.909203, 1.50587" \ ); } @@ -10807,26 +10831,26 @@ library (sg13g2_stdcell_slow_1p08V_125C) { index_1 ("0.0186, 0.0966, 0.174, 0.3294, 0.6408, 1.263, 2.5074"); index_2 ("0.001, 0.0468, 0.078, 0.1296, 0.216, 0.36, 0.6"); values ( \ - "0.0224946, 0.0231328, 0.0231639, 0.0231342, 0.0229871, 0.0229773, 0.0228427", \ + "0.0224882, 0.0231412, 0.0231677, 0.0231342, 0.022988, 0.0230056, 0.0228373", \ "0.0221088, 0.022756, 0.0228031, 0.0227569, 0.0226598, 0.0222956, 0.0224555", \ - "0.0219924, 0.0227444, 0.0227348, 0.0227399, 0.0225846, 0.0223088, 0.0222701", \ + "0.0219924, 0.0227444, 0.0227348, 0.0227399, 0.0225846, 0.0223088, 0.0222697", \ "0.0218979, 0.0225393, 0.0226234, 0.0226802, 0.022517, 0.0221273, 0.0223877", \ "0.0221819, 0.0229001, 0.0229878, 0.0228795, 0.0228887, 0.0227085, 0.023683", \ "0.0230487, 0.023718, 0.0237565, 0.0238962, 0.0238214, 0.0232382, 0.0240655", \ - "0.024976, 0.025579, 0.0257067, 0.0257433, 0.0257318, 0.0257688, 0.0250492" \ + "0.024976, 0.025579, 0.0257067, 0.0257433, 0.0257319, 0.0257688, 0.0250492" \ ); } fall_power (POWER_7x7ds1) { index_1 ("0.0186, 0.0966, 0.174, 0.3294, 0.6408, 1.263, 2.5074"); index_2 ("0.001, 0.0468, 0.078, 0.1296, 0.216, 0.36, 0.6"); values ( \ - "0.0230622, 0.0238628, 0.0238903, 0.0238563, 0.0237422, 0.0234245, 0.022889", \ + "0.0230653, 0.0238628, 0.0238973, 0.0238492, 0.023679, 0.02342, 0.0228473", \ "0.022754, 0.023602, 0.0236269, 0.0236476, 0.0234075, 0.0231677, 0.0226", \ "0.0227593, 0.023615, 0.0237861, 0.0237102, 0.0234199, 0.0231023, 0.0227974", \ "0.0227983, 0.0236074, 0.0236094, 0.0236718, 0.0234513, 0.0232541, 0.0227889", \ "0.0232597, 0.0241134, 0.0241886, 0.0241742, 0.0238524, 0.0242757, 0.0231974", \ - "0.0241282, 0.0249301, 0.0250643, 0.0250671, 0.0251152, 0.0247172, 0.0241117", \ - "0.0262017, 0.0269853, 0.0270807, 0.027084, 0.0271809, 0.0271583, 0.0270927" \ + "0.0241287, 0.0249301, 0.0250643, 0.0250671, 0.0251152, 0.0247172, 0.0241117", \ + "0.0262017, 0.0269853, 0.0270807, 0.027084, 0.0271809, 0.0271583, 0.0270926" \ ); } } @@ -10841,9 +10865,9 @@ library (sg13g2_stdcell_slow_1p08V_125C) { index_1 ("0.0186, 0.0966, 0.174, 0.3294, 0.6408, 1.263, 2.5074"); index_2 ("0.001, 0.0468, 0.078, 0.1296, 0.216, 0.36, 0.6"); values ( \ - "0.0151868, 0.0159175, 0.0159454, 0.0159345, 0.015785, 0.015521, 0.0149804", \ - "0.0151382, 0.0158145, 0.0158389, 0.0158182, 0.0156663, 0.015387, 0.0148845", \ - "0.0149802, 0.0158472, 0.0157469, 0.0158174, 0.0156391, 0.0153429, 0.0148247", \ + "0.0151868, 0.0159208, 0.0159367, 0.0159345, 0.0158057, 0.0155195, 0.0149787", \ + "0.0151466, 0.015817, 0.0158386, 0.0158047, 0.0156663, 0.0153811, 0.0148647", \ + "0.0149802, 0.0158472, 0.0157469, 0.0158174, 0.0156391, 0.0153429, 0.0148245", \ "0.0149358, 0.0156721, 0.015686, 0.0158692, 0.0157011, 0.0153477, 0.0149504", \ "0.0151563, 0.0159126, 0.0158741, 0.0158547, 0.0158031, 0.0158272, 0.0150235", \ "0.0154153, 0.0161659, 0.0161616, 0.0162574, 0.0162384, 0.0156999, 0.0163435", \ @@ -10858,9 +10882,9 @@ library (sg13g2_stdcell_slow_1p08V_125C) { max_transition : 2.5074; capacitance : 0.00259484; rise_capacitance : 0.00279302; - rise_capacitance_range (0.00279302, 0.00279302); + rise_capacitance_range (0.00257638, 0.00297008); fall_capacitance : 0.00236364; - fall_capacitance_range (0.00236364, 0.00236364); + fall_capacitance_range (0.00236364, 0.00285873); timing () { related_pin : "CLK"; timing_type : min_pulse_width; @@ -10882,13 +10906,13 @@ library (sg13g2_stdcell_slow_1p08V_125C) { rise_power (passive_POWER_7x1ds1) { index_1 ("0.0186, 0.0966, 0.174, 0.3294, 0.6408, 1.263, 2.5074"); values ( \ - "0.00891548, 0.0085433, 0.0085156, 0.00848873, 0.00885849, 0.0095991, 0.0115594" \ + "0.00892089, 0.0085433, 0.00851561, 0.00848874, 0.0088585, 0.0095991, 0.0115594" \ ); } fall_power (passive_POWER_7x1ds1) { index_1 ("0.0186, 0.0966, 0.174, 0.3294, 0.6408, 1.263, 2.5074"); values ( \ - "0.0248021, 0.0244729, 0.0243333, 0.0243871, 0.0246865, 0.0253863, 0.0272479" \ + "0.0247937, 0.0244729, 0.0243333, 0.0243871, 0.0246865, 0.0253863, 0.0272479" \ ); } } @@ -10902,7 +10926,7 @@ library (sg13g2_stdcell_slow_1p08V_125C) { fall_power (passive_POWER_7x1ds1) { index_1 ("0.0186, 0.0966, 0.174, 0.3294, 0.6408, 1.263, 2.5074"); values ( \ - "0.0166988, 0.01636, 0.0162269, 0.0162852, 0.0165844, 0.0172846, 0.0191478" \ + "0.0166988, 0.0163599, 0.016227, 0.0162852, 0.0165844, 0.0172846, 0.0191478" \ ); } } @@ -10911,13 +10935,13 @@ library (sg13g2_stdcell_slow_1p08V_125C) { rise_power (passive_POWER_7x1ds1) { index_1 ("0.0186, 0.0966, 0.174, 0.3294, 0.6408, 1.263, 2.5074"); values ( \ - "0.00933431, 0.00898698, 0.00895565, 0.00894296, 0.00929321, 0.0100262, 0.0119947" \ + "0.00933517, 0.00899258, 0.00895565, 0.00894296, 0.00929321, 0.0100262, 0.0119947" \ ); } fall_power (passive_POWER_7x1ds1) { index_1 ("0.0186, 0.0966, 0.174, 0.3294, 0.6408, 1.263, 2.5074"); values ( \ - "0.00868654, 0.00836605, 0.00830132, 0.0083774, 0.00868046, 0.00940956, 0.0112745" \ + "0.00868654, 0.00836626, 0.00830132, 0.0083774, 0.00868046, 0.00940956, 0.0112746" \ ); } } @@ -10931,7 +10955,7 @@ library (sg13g2_stdcell_slow_1p08V_125C) { fall_power (passive_POWER_7x1ds1) { index_1 ("0.0186, 0.0966, 0.174, 0.3294, 0.6408, 1.263, 2.5074"); values ( \ - "0.0306407, 0.0304, 0.030261, 0.0300671, 0.0302418, 0.0310694, 0.0329519" \ + "0.0306407, 0.0304005, 0.030261, 0.0300671, 0.0302418, 0.0310694, 0.0329519" \ ); } } @@ -10940,13 +10964,13 @@ library (sg13g2_stdcell_slow_1p08V_125C) { rise_power (passive_POWER_7x1ds1) { index_1 ("0.0186, 0.0966, 0.174, 0.3294, 0.6408, 1.263, 2.5074"); values ( \ - "0.00884981, 0.008483, 0.00844303, 0.00841389, 0.00878073, 0.0095168, 0.0114897" \ + "0.00884985, 0.00848297, 0.00844302, 0.00841389, 0.00878073, 0.0095168, 0.0114897" \ ); } fall_power (passive_POWER_7x1ds1) { index_1 ("0.0186, 0.0966, 0.174, 0.3294, 0.6408, 1.263, 2.5074"); values ( \ - "0.00861738, 0.0082976, 0.00822718, 0.00830645, 0.00861561, 0.00933506, 0.0112188" \ + "0.00861741, 0.00829321, 0.00822718, 0.00830645, 0.00861561, 0.00933506, 0.0112188" \ ); } } @@ -10955,13 +10979,13 @@ library (sg13g2_stdcell_slow_1p08V_125C) { rise_power (passive_POWER_7x1ds1) { index_1 ("0.0186, 0.0966, 0.174, 0.3294, 0.6408, 1.263, 2.5074"); values ( \ - "0.00923708, 0.00887373, 0.00884538, 0.00882272, 0.00918043, 0.00991653, 0.0118737" \ + "0.00922409, 0.00887368, 0.00884538, 0.00882272, 0.00918044, 0.00991654, 0.0118737" \ ); } fall_power (passive_POWER_7x1ds1) { index_1 ("0.0186, 0.0966, 0.174, 0.3294, 0.6408, 1.263, 2.5074"); values ( \ - "0.00864867, 0.00832818, 0.00826669, 0.0083293, 0.00864454, 0.00937425, 0.0112382" \ + "0.00864868, 0.00832816, 0.00826669, 0.0083293, 0.00864454, 0.00937425, 0.0112382" \ ); } } @@ -10969,13 +10993,13 @@ library (sg13g2_stdcell_slow_1p08V_125C) { rise_power (passive_POWER_7x1ds1) { index_1 ("0.0186, 0.0966, 0.174, 0.3294, 0.6408, 1.263, 2.5074"); values ( \ - "0.00923708, 0.00887373, 0.00884538, 0.00882272, 0.00918043, 0.00991653, 0.0118737" \ + "0.00922409, 0.00887368, 0.00884538, 0.00882272, 0.00918044, 0.00991654, 0.0118737" \ ); } fall_power (passive_POWER_7x1ds1) { index_1 ("0.0186, 0.0966, 0.174, 0.3294, 0.6408, 1.263, 2.5074"); values ( \ - "0.0166988, 0.01636, 0.0162269, 0.0162852, 0.0165844, 0.0172846, 0.0191478" \ + "0.0166988, 0.0163599, 0.016227, 0.0162852, 0.0165844, 0.0172846, 0.0191478" \ ); } } @@ -10986,11 +11010,12 @@ library (sg13g2_stdcell_slow_1p08V_125C) { max_transition : 2.5074; capacitance : 0.00134888; rise_capacitance : 0.00133891; - rise_capacitance_range (0.00133891, 0.00133891); + rise_capacitance_range (0.00126868, 0.00148811); fall_capacitance : 0.00135884; - fall_capacitance_range (0.00135884, 0.00135884); + fall_capacitance_range (0.00135884, 0.001695); timing () { related_pin : "CLK"; + sdf_edges : both_edges; timing_type : hold_rising; rise_constraint (CONSTRAINT_4x4) { index_1 ("0.0186, 0.51636, 1.263, 2.5074"); @@ -10999,7 +11024,7 @@ library (sg13g2_stdcell_slow_1p08V_125C) { "-0.100253, -0.0227089, 0.0292886, 0.0855195", \ "-0.281782, -0.198624, -0.143266, -0.0846213", \ "-0.415055, -0.341881, -0.283328, -0.22188", \ - "-0.54694, -0.484422, -0.433509, -0.374845" \ + "-0.549638, -0.484422, -0.433509, -0.374845" \ ); } fall_constraint (CONSTRAINT_4x4) { @@ -11015,6 +11040,7 @@ library (sg13g2_stdcell_slow_1p08V_125C) { } timing () { related_pin : "CLK"; + sdf_edges : both_edges; timing_type : setup_rising; rise_constraint (CONSTRAINT_4x4) { index_1 ("0.0186, 0.51636, 1.263, 2.5074"); @@ -11042,13 +11068,13 @@ library (sg13g2_stdcell_slow_1p08V_125C) { rise_power (passive_POWER_7x1ds1) { index_1 ("0.0186, 0.0966, 0.174, 0.3294, 0.6408, 1.263, 2.5074"); values ( \ - "0.00145462, 0.0013415, 0.0013252, 0.00136222, 0.00147987, 0.00179139, 0.00250197" \ + "0.00145213, 0.00134151, 0.00132521, 0.00136223, 0.00147987, 0.00179139, 0.00250198" \ ); } fall_power (passive_POWER_7x1ds1) { index_1 ("0.0186, 0.0966, 0.174, 0.3294, 0.6408, 1.263, 2.5074"); values ( \ - "0.00109722, 0.000972251, 0.000961389, 0.000986755, 0.0011493, 0.00141756, 0.00210322" \ + "0.00109722, 0.000972251, 0.000961384, 0.00098675, 0.0011493, 0.00141756, 0.00210322" \ ); } } @@ -11057,13 +11083,13 @@ library (sg13g2_stdcell_slow_1p08V_125C) { rise_power (passive_POWER_7x1ds1) { index_1 ("0.0186, 0.0966, 0.174, 0.3294, 0.6408, 1.263, 2.5074"); values ( \ - "0.00945323, 0.00941704, 0.00936318, 0.00936205, 0.00941739, 0.00969225, 0.0103966" \ + "0.00945322, 0.00941723, 0.00936318, 0.00936205, 0.00941739, 0.00969225, 0.0103966" \ ); } fall_power (passive_POWER_7x1ds1) { index_1 ("0.0186, 0.0966, 0.174, 0.3294, 0.6408, 1.263, 2.5074"); values ( \ - "0.00713576, 0.00705148, 0.00699628, 0.00697245, 0.00704364, 0.00731888, 0.00807502" \ + "0.00713571, 0.00705148, 0.00699628, 0.00697245, 0.00704364, 0.00731888, 0.00807502" \ ); } } @@ -11072,13 +11098,13 @@ library (sg13g2_stdcell_slow_1p08V_125C) { rise_power (passive_POWER_7x1ds1) { index_1 ("0.0186, 0.0966, 0.174, 0.3294, 0.6408, 1.263, 2.5074"); values ( \ - "-4.29805e-05, -4.82123e-05, -4.72489e-05, -4.77372e-05, -4.79861e-05, -4.97195e-05, -5.01217e-05" \ + "-4.34529e-05, -4.82123e-05, -4.72117e-05, -4.77372e-05, -4.79861e-05, -4.97194e-05, -5.01217e-05" \ ); } fall_power (passive_POWER_7x1ds1) { index_1 ("0.0186, 0.0966, 0.174, 0.3294, 0.6408, 1.263, 2.5074"); values ( \ - "4.29805e-05, 4.82123e-05, 4.72489e-05, 4.77372e-05, 4.79861e-05, 4.97195e-05, 5.01217e-05" \ + "4.34529e-05, 4.82123e-05, 4.72117e-05, 4.77372e-05, 4.79861e-05, 4.97194e-05, 5.01217e-05" \ ); } } @@ -11086,13 +11112,13 @@ library (sg13g2_stdcell_slow_1p08V_125C) { rise_power (passive_POWER_7x1ds1) { index_1 ("0.0186, 0.0966, 0.174, 0.3294, 0.6408, 1.263, 2.5074"); values ( \ - "0.00145462, 0.0013415, 0.0013252, 0.00136222, 0.00147987, 0.00179139, 0.00250197" \ + "0.00145213, 0.00134151, 0.00132521, 0.00136223, 0.00147987, 0.00179139, 0.00250198" \ ); } fall_power (passive_POWER_7x1ds1) { index_1 ("0.0186, 0.0966, 0.174, 0.3294, 0.6408, 1.263, 2.5074"); values ( \ - "0.00109722, 0.000972251, 0.000961389, 0.000986755, 0.0011493, 0.00141756, 0.00210322" \ + "0.00109722, 0.000972251, 0.000961384, 0.00098675, 0.0011493, 0.00141756, 0.00210322" \ ); } } @@ -11102,17 +11128,18 @@ library (sg13g2_stdcell_slow_1p08V_125C) { max_transition : 2.5074; capacitance : 0.00478539; rise_capacitance : 0.00470093; - rise_capacitance_range (0.00470093, 0.00470093); + rise_capacitance_range (0.0043457, 0.00535759); fall_capacitance : 0.00485578; - fall_capacitance_range (0.00485578, 0.00485578); + fall_capacitance_range (0.00455051, 0.00501304); timing () { related_pin : "CLK"; + sdf_edges : both_edges; timing_type : recovery_rising; rise_constraint (CONSTRAINT_4x4) { index_1 ("0.0186, 0.51636, 1.263, 2.5074"); index_2 ("0.0186, 0.51636, 1.263, 2.5074"); values ( \ - "0.200506, 0.105071, 0.0555801, 0.000828112", \ + "0.202951, 0.105071, 0.0555801, 0.000828112", \ "0.399086, 0.292843, 0.242917, 0.189083", \ "0.582221, 0.470379, 0.41285, 0.354653", \ "0.800586, 0.68235, 0.619955, 0.563744" \ @@ -11121,6 +11148,7 @@ library (sg13g2_stdcell_slow_1p08V_125C) { } timing () { related_pin : "CLK"; + sdf_edges : both_edges; timing_type : removal_rising; rise_constraint (CONSTRAINT_4x4) { index_1 ("0.0186, 0.51636, 1.263, 2.5074"); @@ -11148,7 +11176,7 @@ library (sg13g2_stdcell_slow_1p08V_125C) { rise_power (passive_POWER_7x1ds1) { index_1 ("0.0186, 0.0966, 0.174, 0.3294, 0.6408, 1.263, 2.5074"); values ( \ - "0.00285614, 0.00277145, 0.00274624, 0.002741, 0.00275817, 0.00291643, 0.00345858" \ + "0.00285615, 0.00277146, 0.00274626, 0.00274101, 0.00275818, 0.00291644, 0.00345859" \ ); } fall_power (passive_POWER_7x1ds1) { @@ -11163,13 +11191,13 @@ library (sg13g2_stdcell_slow_1p08V_125C) { rise_power (passive_POWER_7x1ds1) { index_1 ("0.0186, 0.0966, 0.174, 0.3294, 0.6408, 1.263, 2.5074"); values ( \ - "0.000951847, 0.000949401, 0.000946113, 0.000946929, 0.000942678, 0.000947589, 0.000950936" \ + "0.000951651, 0.000949401, 0.000946113, 0.000946924, 0.000942678, 0.000947589, 0.000951033" \ ); } fall_power (passive_POWER_7x1ds1) { index_1 ("0.0186, 0.0966, 0.174, 0.3294, 0.6408, 1.263, 2.5074"); values ( \ - "-0.000433184, -0.000542045, -0.000571279, -0.000596653, -0.000622967, -0.000639907, -0.000658741" \ + "-0.00043318, -0.000542019, -0.00057127, -0.000596644, -0.000622957, -0.000639903, -0.000658731" \ ); } } @@ -11178,13 +11206,13 @@ library (sg13g2_stdcell_slow_1p08V_125C) { rise_power (passive_POWER_7x1ds1) { index_1 ("0.0186, 0.0966, 0.174, 0.3294, 0.6408, 1.263, 2.5074"); values ( \ - "0.0112049, 0.011058, 0.0109754, 0.0109298, 0.0109371, 0.0111493, 0.0119083" \ + "0.0112043, 0.0110579, 0.0109753, 0.0109298, 0.0109371, 0.0111493, 0.0119083" \ ); } fall_power (passive_POWER_7x1ds1) { index_1 ("0.0186, 0.0966, 0.174, 0.3294, 0.6408, 1.263, 2.5074"); values ( \ - "0.00746369, 0.00719051, 0.00709182, 0.00698079, 0.00698921, 0.00722311, 0.00810139" \ + "0.00746368, 0.00719051, 0.00709182, 0.00698079, 0.00698921, 0.00722311, 0.00810139" \ ); } } @@ -11193,13 +11221,13 @@ library (sg13g2_stdcell_slow_1p08V_125C) { rise_power (passive_POWER_7x1ds1) { index_1 ("0.0186, 0.0966, 0.174, 0.3294, 0.6408, 1.263, 2.5074"); values ( \ - "0.000915827, 0.000912808, 0.000912479, 0.000909615, 0.000907604, 0.000911173, 0.000910264" \ + "0.000915788, 0.000912808, 0.000912479, 0.000909615, 0.000907598, 0.000911173, 0.000910264" \ ); } fall_power (passive_POWER_7x1ds1) { index_1 ("0.0186, 0.0966, 0.174, 0.3294, 0.6408, 1.263, 2.5074"); values ( \ - "-0.000652922, -0.000738898, -0.000763983, -0.000785212, -0.000800279, -0.000815082, -0.000831615" \ + "-0.000652922, -0.00073928, -0.000763977, -0.000785212, -0.000800274, -0.000815077, -0.00083161" \ ); } } @@ -11207,26 +11235,26 @@ library (sg13g2_stdcell_slow_1p08V_125C) { rise_power (passive_POWER_7x1ds1) { index_1 ("0.0186, 0.0966, 0.174, 0.3294, 0.6408, 1.263, 2.5074"); values ( \ - "0.00285614, 0.00277145, 0.00274624, 0.002741, 0.00275817, 0.00291643, 0.00345858" \ + "0.00285615, 0.00277146, 0.00274626, 0.00274101, 0.00275818, 0.00291644, 0.00345859" \ ); } fall_power (passive_POWER_7x1ds1) { index_1 ("0.0186, 0.0966, 0.174, 0.3294, 0.6408, 1.263, 2.5074"); values ( \ - "0.00746369, 0.00719051, 0.00709182, 0.00698079, 0.00698921, 0.00722311, 0.00810139" \ + "0.00746368, 0.00719051, 0.00709182, 0.00698079, 0.00698921, 0.00722311, 0.00810139" \ ); } } } ff (IQ,IQN) { - clear : "RESET_B'"; + clear : "!RESET_B"; clocked_on : "CLK"; next_state : "D"; } } cell (sg13g2_dlhq_1) { area : 30.8448; - cell_footprint : "DLHQ"; + cell_footprint : "dlhq"; cell_leakage_power : 1700.59; leakage_power () { value : 1648.82; @@ -11316,6 +11344,7 @@ library (sg13g2_stdcell_slow_1p08V_125C) { } timing () { related_pin : "GATE"; + sdf_edges : start_edge; timing_sense : non_unate; timing_type : rising_edge; cell_rise (TIMING_DELAY_7x7ds1) { @@ -11435,11 +11464,12 @@ library (sg13g2_stdcell_slow_1p08V_125C) { max_transition : 2.5074; capacitance : 0.00213349; rise_capacitance : 0.00216732; - rise_capacitance_range (0.00216732, 0.00216732); + rise_capacitance_range (0.00197474, 0.00230876); fall_capacitance : 0.00209966; - fall_capacitance_range (0.00209966, 0.00209966); + fall_capacitance_range (0.0019346, 0.00225461); timing () { related_pin : "GATE"; + sdf_edges : both_edges; timing_type : hold_falling; rise_constraint (CONSTRAINT_4x4) { index_1 ("0.0186, 0.51636, 1.263, 2.5074"); @@ -11464,6 +11494,7 @@ library (sg13g2_stdcell_slow_1p08V_125C) { } timing () { related_pin : "GATE"; + sdf_edges : both_edges; timing_type : setup_falling; rise_constraint (CONSTRAINT_4x4) { index_1 ("0.0186, 0.51636, 1.263, 2.5074"); @@ -11537,9 +11568,9 @@ library (sg13g2_stdcell_slow_1p08V_125C) { max_transition : 2.5074; capacitance : 0.00212897; rise_capacitance : 0.00241689; - rise_capacitance_range (0.00241689, 0.00241689); + rise_capacitance_range (0.00220669, 0.00261245); fall_capacitance : 0.00155314; - fall_capacitance_range (0.00155314, 0.00155314); + fall_capacitance_range (0.00155314, 0.00253857); timing () { related_pin : "GATE"; timing_type : min_pulse_width; @@ -11587,7 +11618,7 @@ library (sg13g2_stdcell_slow_1p08V_125C) { } cell (sg13g2_dlhr_1) { area : 32.6592; - cell_footprint : "DLHR"; + cell_footprint : "dlhr"; cell_leakage_power : 2349.9; leakage_power () { value : 2052.82; @@ -11693,6 +11724,7 @@ library (sg13g2_stdcell_slow_1p08V_125C) { } timing () { related_pin : "GATE"; + sdf_edges : start_edge; timing_sense : non_unate; timing_type : rising_edge; cell_rise (TIMING_DELAY_7x7ds1) { @@ -11750,6 +11782,7 @@ library (sg13g2_stdcell_slow_1p08V_125C) { } timing () { related_pin : "RESET_B"; + sdf_edges : start_edge; timing_sense : positive_unate; timing_type : clear; cell_fall (TIMING_DELAY_7x7ds1) { @@ -11923,6 +11956,7 @@ library (sg13g2_stdcell_slow_1p08V_125C) { } timing () { related_pin : "GATE"; + sdf_edges : start_edge; timing_sense : non_unate; timing_type : rising_edge; cell_rise (TIMING_DELAY_7x7ds1) { @@ -11980,6 +12014,7 @@ library (sg13g2_stdcell_slow_1p08V_125C) { } timing () { related_pin : "RESET_B"; + sdf_edges : start_edge; timing_sense : negative_unate; timing_type : preset; cell_rise (TIMING_DELAY_7x7ds1) { @@ -12094,11 +12129,12 @@ library (sg13g2_stdcell_slow_1p08V_125C) { max_transition : 2.5074; capacitance : 0.00193192; rise_capacitance : 0.00211195; - rise_capacitance_range (0.00211195, 0.00211195); + rise_capacitance_range (0.00191495, 0.00225736); fall_capacitance : 0.00175188; - fall_capacitance_range (0.00175188, 0.00175188); + fall_capacitance_range (0.00175188, 0.00220221); timing () { related_pin : "GATE"; + sdf_edges : both_edges; timing_type : hold_falling; rise_constraint (CONSTRAINT_4x4) { index_1 ("0.0186, 0.51636, 1.263, 2.5074"); @@ -12123,6 +12159,7 @@ library (sg13g2_stdcell_slow_1p08V_125C) { } timing () { related_pin : "GATE"; + sdf_edges : both_edges; timing_type : setup_falling; rise_constraint (CONSTRAINT_4x4) { index_1 ("0.0186, 0.51636, 1.263, 2.5074"); @@ -12196,9 +12233,9 @@ library (sg13g2_stdcell_slow_1p08V_125C) { max_transition : 2.5074; capacitance : 0.00208662; rise_capacitance : 0.0024004; - rise_capacitance_range (0.0024004, 0.0024004); + rise_capacitance_range (0.00219626, 0.00259388); fall_capacitance : 0.00153751; - fall_capacitance_range (0.00153751, 0.00153751); + fall_capacitance_range (0.00153751, 0.00252154); timing () { related_pin : "GATE"; timing_type : min_pulse_width; @@ -12273,11 +12310,12 @@ library (sg13g2_stdcell_slow_1p08V_125C) { max_transition : 2.5074; capacitance : 0.00288318; rise_capacitance : 0.00294015; - rise_capacitance_range (0.00294015, 0.00294015); + rise_capacitance_range (0.00270739, 0.0032091); fall_capacitance : 0.00284899; - fall_capacitance_range (0.00284899, 0.00284899); + fall_capacitance_range (0.00267302, 0.00297691); timing () { related_pin : "GATE"; + sdf_edges : both_edges; timing_type : recovery_falling; rise_constraint (CONSTRAINT_4x4) { index_1 ("0.0186, 0.51636, 1.263, 2.5074"); @@ -12292,6 +12330,7 @@ library (sg13g2_stdcell_slow_1p08V_125C) { } timing () { related_pin : "GATE"; + sdf_edges : both_edges; timing_type : removal_falling; rise_constraint (CONSTRAINT_4x4) { index_1 ("0.0186, 0.51636, 1.263, 2.5074"); @@ -12360,14 +12399,14 @@ library (sg13g2_stdcell_slow_1p08V_125C) { } } latch (IQ,IQN) { - clear : "RESET_B'"; + clear : "!RESET_B"; data_in : "D"; enable : "GATE"; } } cell (sg13g2_dlhrq_1) { area : 27.216; - cell_footprint : "DLHRQ"; + cell_footprint : "dlhrq"; cell_leakage_power : 1837.18; leakage_power () { value : 1556.96; @@ -12473,6 +12512,7 @@ library (sg13g2_stdcell_slow_1p08V_125C) { } timing () { related_pin : "GATE"; + sdf_edges : start_edge; timing_sense : non_unate; timing_type : rising_edge; cell_rise (TIMING_DELAY_7x7ds1) { @@ -12530,6 +12570,7 @@ library (sg13g2_stdcell_slow_1p08V_125C) { } timing () { related_pin : "RESET_B"; + sdf_edges : start_edge; timing_sense : positive_unate; timing_type : clear; cell_fall (TIMING_DELAY_7x7ds1) { @@ -12644,11 +12685,12 @@ library (sg13g2_stdcell_slow_1p08V_125C) { max_transition : 2.5074; capacitance : 0.00198577; rise_capacitance : 0.00220408; - rise_capacitance_range (0.00220408, 0.00220408); + rise_capacitance_range (0.00200904, 0.00234885); fall_capacitance : 0.00176747; - fall_capacitance_range (0.00176747, 0.00176747); + fall_capacitance_range (0.00176747, 0.00228825); timing () { related_pin : "GATE"; + sdf_edges : both_edges; timing_type : hold_falling; rise_constraint (CONSTRAINT_4x4) { index_1 ("0.0186, 0.51636, 1.263, 2.5074"); @@ -12673,6 +12715,7 @@ library (sg13g2_stdcell_slow_1p08V_125C) { } timing () { related_pin : "GATE"; + sdf_edges : both_edges; timing_type : setup_falling; rise_constraint (CONSTRAINT_4x4) { index_1 ("0.0186, 0.51636, 1.263, 2.5074"); @@ -12746,9 +12789,9 @@ library (sg13g2_stdcell_slow_1p08V_125C) { max_transition : 2.5074; capacitance : 0.00204094; rise_capacitance : 0.00242486; - rise_capacitance_range (0.00242486, 0.00242486); + rise_capacitance_range (0.00222211, 0.00261693); fall_capacitance : 0.00156105; - fall_capacitance_range (0.00156105, 0.00156105); + fall_capacitance_range (0.00156105, 0.00254517); timing () { related_pin : "GATE"; timing_type : min_pulse_width; @@ -12823,11 +12866,12 @@ library (sg13g2_stdcell_slow_1p08V_125C) { max_transition : 2.5074; capacitance : 0.00272212; rise_capacitance : 0.00274479; - rise_capacitance_range (0.00274479, 0.00274479); + rise_capacitance_range (0.00251429, 0.0030155); fall_capacitance : 0.00270512; - fall_capacitance_range (0.00270512, 0.00270512); + fall_capacitance_range (0.00252457, 0.00282582); timing () { related_pin : "GATE"; + sdf_edges : both_edges; timing_type : recovery_falling; rise_constraint (CONSTRAINT_4x4) { index_1 ("0.0186, 0.51636, 1.263, 2.5074"); @@ -12842,6 +12886,7 @@ library (sg13g2_stdcell_slow_1p08V_125C) { } timing () { related_pin : "GATE"; + sdf_edges : both_edges; timing_type : removal_falling; rise_constraint (CONSTRAINT_4x4) { index_1 ("0.0186, 0.51636, 1.263, 2.5074"); @@ -12910,14 +12955,14 @@ library (sg13g2_stdcell_slow_1p08V_125C) { } } latch (IQ,IQN) { - clear : "RESET_B'"; + clear : "!RESET_B"; data_in : "D"; enable : "GATE"; } } cell (sg13g2_dllr_1) { area : 34.4736; - cell_footprint : "DLLR"; + cell_footprint : "dllr"; cell_leakage_power : 2408.13; leakage_power () { value : 2260.31; @@ -13039,6 +13084,7 @@ library (sg13g2_stdcell_slow_1p08V_125C) { } timing () { related_pin : "GATE_N"; + sdf_edges : start_edge; timing_sense : non_unate; timing_type : falling_edge; cell_rise (TIMING_DELAY_7x7ds1) { @@ -13096,6 +13142,7 @@ library (sg13g2_stdcell_slow_1p08V_125C) { } timing () { related_pin : "RESET_B"; + sdf_edges : start_edge; timing_sense : positive_unate; timing_type : clear; cell_fall (TIMING_DELAY_7x7ds1) { @@ -13269,6 +13316,7 @@ library (sg13g2_stdcell_slow_1p08V_125C) { } timing () { related_pin : "GATE_N"; + sdf_edges : start_edge; timing_sense : non_unate; timing_type : falling_edge; cell_rise (TIMING_DELAY_7x7ds1) { @@ -13326,6 +13374,7 @@ library (sg13g2_stdcell_slow_1p08V_125C) { } timing () { related_pin : "RESET_B"; + sdf_edges : start_edge; timing_sense : negative_unate; timing_type : preset; cell_rise (TIMING_DELAY_7x7ds1) { @@ -13440,11 +13489,12 @@ library (sg13g2_stdcell_slow_1p08V_125C) { max_transition : 2.5074; capacitance : 0.00200246; rise_capacitance : 0.00218223; - rise_capacitance_range (0.00218223, 0.00218223); + rise_capacitance_range (0.00198148, 0.00232759); fall_capacitance : 0.00182269; - fall_capacitance_range (0.00182269, 0.00182269); + fall_capacitance_range (0.00182269, 0.00227399); timing () { related_pin : "GATE_N"; + sdf_edges : both_edges; timing_type : hold_rising; rise_constraint (CONSTRAINT_4x4) { index_1 ("0.0186, 0.51636, 1.263, 2.5074"); @@ -13469,6 +13519,7 @@ library (sg13g2_stdcell_slow_1p08V_125C) { } timing () { related_pin : "GATE_N"; + sdf_edges : both_edges; timing_type : setup_rising; rise_constraint (CONSTRAINT_4x4) { index_1 ("0.0186, 0.51636, 1.263, 2.5074"); @@ -13542,9 +13593,9 @@ library (sg13g2_stdcell_slow_1p08V_125C) { max_transition : 2.5074; capacitance : 0.00215272; rise_capacitance : 0.00161632; - rise_capacitance_range (0.00161632, 0.00161632); + rise_capacitance_range (0.00161632, 0.00265499); fall_capacitance : 0.00245923; - fall_capacitance_range (0.00245923, 0.00245923); + fall_capacitance_range (0.00229903, 0.00258974); timing () { related_pin : "GATE_N"; timing_type : min_pulse_width; @@ -13619,11 +13670,12 @@ library (sg13g2_stdcell_slow_1p08V_125C) { max_transition : 2.5074; capacitance : 0.00284471; rise_capacitance : 0.00290402; - rise_capacitance_range (0.00290402, 0.00290402); + rise_capacitance_range (0.00267156, 0.00317857); fall_capacitance : 0.00280913; - fall_capacitance_range (0.00280913, 0.00280913); + fall_capacitance_range (0.00263281, 0.00293857); timing () { related_pin : "GATE_N"; + sdf_edges : both_edges; timing_type : recovery_rising; rise_constraint (CONSTRAINT_4x4) { index_1 ("0.0186, 0.51636, 1.263, 2.5074"); @@ -13638,6 +13690,7 @@ library (sg13g2_stdcell_slow_1p08V_125C) { } timing () { related_pin : "GATE_N"; + sdf_edges : both_edges; timing_type : removal_rising; rise_constraint (CONSTRAINT_4x4) { index_1 ("0.0186, 0.51636, 1.263, 2.5074"); @@ -13706,14 +13759,14 @@ library (sg13g2_stdcell_slow_1p08V_125C) { } } latch (IQ,IQN) { - clear : "RESET_B'"; + clear : "!RESET_B"; data_in : "D"; - enable : "GATE_N'"; + enable : "!GATE_N"; } } cell (sg13g2_dllrq_1) { area : 29.0304; - cell_footprint : "DLLRQ"; + cell_footprint : "dllrq"; cell_leakage_power : 1837.09; leakage_power () { value : 1764.41; @@ -13819,6 +13872,7 @@ library (sg13g2_stdcell_slow_1p08V_125C) { } timing () { related_pin : "GATE_N"; + sdf_edges : start_edge; timing_sense : non_unate; timing_type : falling_edge; cell_rise (TIMING_DELAY_7x7ds1) { @@ -13876,6 +13930,7 @@ library (sg13g2_stdcell_slow_1p08V_125C) { } timing () { related_pin : "RESET_B"; + sdf_edges : start_edge; timing_sense : positive_unate; timing_type : clear; cell_fall (TIMING_DELAY_7x7ds1) { @@ -13907,6 +13962,7 @@ library (sg13g2_stdcell_slow_1p08V_125C) { } timing () { related_pin : "RESET_B"; + sdf_edges : start_edge; timing_sense : positive_unate; timing_type : preset; cell_rise (TIMING_DELAY_7x7ds1) { @@ -14029,11 +14085,12 @@ library (sg13g2_stdcell_slow_1p08V_125C) { max_transition : 2.5074; capacitance : 0.00189558; rise_capacitance : 0.00211176; - rise_capacitance_range (0.00211176, 0.00211176); + rise_capacitance_range (0.00191598, 0.00225536); fall_capacitance : 0.0016794; - fall_capacitance_range (0.0016794, 0.0016794); + fall_capacitance_range (0.0016794, 0.00219958); timing () { related_pin : "GATE_N"; + sdf_edges : both_edges; timing_type : hold_rising; rise_constraint (CONSTRAINT_4x4) { index_1 ("0.0186, 0.51636, 1.263, 2.5074"); @@ -14058,6 +14115,7 @@ library (sg13g2_stdcell_slow_1p08V_125C) { } timing () { related_pin : "GATE_N"; + sdf_edges : both_edges; timing_type : setup_rising; rise_constraint (CONSTRAINT_4x4) { index_1 ("0.0186, 0.51636, 1.263, 2.5074"); @@ -14131,9 +14189,9 @@ library (sg13g2_stdcell_slow_1p08V_125C) { max_transition : 2.5074; capacitance : 0.00201932; rise_capacitance : 0.00240227; - rise_capacitance_range (0.00240227, 0.00240227); + rise_capacitance_range (0.00219974, 0.00259924); fall_capacitance : 0.00182784; - fall_capacitance_range (0.00182784, 0.00182784); + fall_capacitance_range (0.00182784, 0.00253191); timing () { related_pin : "GATE_N"; timing_type : min_pulse_width; @@ -14208,11 +14266,12 @@ library (sg13g2_stdcell_slow_1p08V_125C) { max_transition : 2.5074; capacitance : 0.00273167; rise_capacitance : 0.00277238; - rise_capacitance_range (0.00277238, 0.00277238); + rise_capacitance_range (0.00246003, 0.00321263); fall_capacitance : 0.00269095; - fall_capacitance_range (0.00269095, 0.00269095); + fall_capacitance_range (0.00251044, 0.00281188); timing () { related_pin : "GATE_N"; + sdf_edges : both_edges; timing_type : recovery_rising; rise_constraint (CONSTRAINT_4x4) { index_1 ("0.0186, 0.51636, 1.263, 2.5074"); @@ -14227,6 +14286,7 @@ library (sg13g2_stdcell_slow_1p08V_125C) { } timing () { related_pin : "GATE_N"; + sdf_edges : both_edges; timing_type : removal_rising; rise_constraint (CONSTRAINT_4x4) { index_1 ("0.0186, 0.51636, 1.263, 2.5074"); @@ -14295,14 +14355,14 @@ library (sg13g2_stdcell_slow_1p08V_125C) { } } latch (IQ,IQN) { - clear : "RESET_B'"; + clear : "!RESET_B"; data_in : "D"; - enable : "GATE_N'"; + enable : "!GATE_N"; } } cell (sg13g2_dlygate4sd1_1) { area : 14.5152; - cell_footprint : "DLY1"; + cell_footprint : "dlygate4sd1"; cell_leakage_power : 914.862; leakage_power () { value : 1032.12; @@ -14409,14 +14469,14 @@ library (sg13g2_stdcell_slow_1p08V_125C) { max_transition : 2.5074; capacitance : 0.00139527; rise_capacitance : 0.00138026; - rise_capacitance_range (0.00138026, 0.00138026); + rise_capacitance_range (0.00127186, 0.0014824); fall_capacitance : 0.00141027; - fall_capacitance_range (0.00141027, 0.00141027); + fall_capacitance_range (0.00133083, 0.00146908); } } cell (sg13g2_dlygate4sd2_1) { area : 14.5152; - cell_footprint : "DLY2"; + cell_footprint : "dlygate4sd2"; cell_leakage_power : 957.877; leakage_power () { value : 1075.13; @@ -14523,14 +14583,14 @@ library (sg13g2_stdcell_slow_1p08V_125C) { max_transition : 2.5074; capacitance : 0.00139424; rise_capacitance : 0.00137866; - rise_capacitance_range (0.00137866, 0.00137866); + rise_capacitance_range (0.00128451, 0.00147246); fall_capacitance : 0.00140983; - fall_capacitance_range (0.00140983, 0.00140983); + fall_capacitance_range (0.00134688, 0.00145988); } } cell (sg13g2_dlygate4sd3_1) { area : 16.3296; - cell_footprint : "DLY4"; + cell_footprint : "dlygate4sd3"; cell_leakage_power : 1811.32; leakage_power () { value : 1928.58; @@ -14637,14 +14697,14 @@ library (sg13g2_stdcell_slow_1p08V_125C) { max_transition : 2.5074; capacitance : 0.00141853; rise_capacitance : 0.00140126; - rise_capacitance_range (0.00140126, 0.00140126); + rise_capacitance_range (0.00133638, 0.00147315); fall_capacitance : 0.0014358; - fall_capacitance_range (0.0014358, 0.0014358); + fall_capacitance_range (0.0013895, 0.00147571); } } cell (sg13g2_ebufn_2) { area : 18.144; - cell_footprint : "BTL"; + cell_footprint : "ebufn"; cell_leakage_power : 931.976; leakage_power () { value : 932.334; @@ -14732,6 +14792,7 @@ library (sg13g2_stdcell_slow_1p08V_125C) { } timing () { related_pin : "TE_B"; + sdf_edges : start_edge; timing_sense : positive_unate; timing_type : three_state_disable; cell_rise (TIMING_DELAY_7x7ds1) { @@ -14789,6 +14850,7 @@ library (sg13g2_stdcell_slow_1p08V_125C) { } timing () { related_pin : "TE_B"; + sdf_edges : start_edge; timing_sense : negative_unate; timing_type : three_state_enable; cell_rise (TIMING_DELAY_7x7ds1) { @@ -14908,9 +14970,9 @@ library (sg13g2_stdcell_slow_1p08V_125C) { max_transition : 2.5074; capacitance : 0.00244351; rise_capacitance : 0.00248873; - rise_capacitance_range (0.00248873, 0.00248873); + rise_capacitance_range (0.00224974, 0.0026664); fall_capacitance : 0.00239828; - fall_capacitance_range (0.00239828, 0.00239828); + fall_capacitance_range (0.00219785, 0.00258931); internal_power () { rise_power (passive_POWER_7x1ds1) { index_1 ("0.0186, 0.0966, 0.174, 0.3294, 0.6408, 1.263, 2.5074"); @@ -14931,9 +14993,9 @@ library (sg13g2_stdcell_slow_1p08V_125C) { max_transition : 2.5074; capacitance : 0.00598987; rise_capacitance : 0.00618203; - rise_capacitance_range (0.00618203, 0.00618203); + rise_capacitance_range (0.00507062, 0.00760265); fall_capacitance : 0.0057977; - fall_capacitance_range (0.0057977, 0.0057977); + fall_capacitance_range (0.00444574, 0.00631522); internal_power () { rise_power (passive_POWER_7x1ds1) { index_1 ("0.0186, 0.0966, 0.174, 0.3294, 0.6408, 1.263, 2.5074"); @@ -14952,7 +15014,7 @@ library (sg13g2_stdcell_slow_1p08V_125C) { } cell (sg13g2_ebufn_4) { area : 27.216; - cell_footprint : "BTL"; + cell_footprint : "ebufn"; cell_leakage_power : 1399.03; leakage_power () { value : 1111.31; @@ -15040,6 +15102,7 @@ library (sg13g2_stdcell_slow_1p08V_125C) { } timing () { related_pin : "TE_B"; + sdf_edges : start_edge; timing_sense : positive_unate; timing_type : three_state_disable; cell_rise (TIMING_DELAY_7x7ds1) { @@ -15097,6 +15160,7 @@ library (sg13g2_stdcell_slow_1p08V_125C) { } timing () { related_pin : "TE_B"; + sdf_edges : start_edge; timing_sense : negative_unate; timing_type : three_state_enable; cell_rise (TIMING_DELAY_7x7ds1) { @@ -15216,9 +15280,9 @@ library (sg13g2_stdcell_slow_1p08V_125C) { max_transition : 2.5074; capacitance : 0.00277225; rise_capacitance : 0.0028256; - rise_capacitance_range (0.0028256, 0.0028256); + rise_capacitance_range (0.00259963, 0.00300771); fall_capacitance : 0.0027189; - fall_capacitance_range (0.0027189, 0.0027189); + fall_capacitance_range (0.00253532, 0.00289441); internal_power () { rise_power (passive_POWER_7x1ds1) { index_1 ("0.0186, 0.0966, 0.174, 0.3294, 0.6408, 1.263, 2.5074"); @@ -15239,9 +15303,9 @@ library (sg13g2_stdcell_slow_1p08V_125C) { max_transition : 2.5074; capacitance : 0.00983354; rise_capacitance : 0.0101927; - rise_capacitance_range (0.0101927, 0.0101927); + rise_capacitance_range (0.00813438, 0.0131686); fall_capacitance : 0.00947442; - fall_capacitance_range (0.00947442, 0.00947442); + fall_capacitance_range (0.00691778, 0.0103646); internal_power () { rise_power (passive_POWER_7x1ds1) { index_1 ("0.0186, 0.0966, 0.174, 0.3294, 0.6408, 1.263, 2.5074"); @@ -15260,7 +15324,7 @@ library (sg13g2_stdcell_slow_1p08V_125C) { } cell (sg13g2_ebufn_8) { area : 45.36; - cell_footprint : "BTL"; + cell_footprint : "ebufn"; cell_leakage_power : 2491.38; leakage_power () { value : 1744.86; @@ -15348,6 +15412,7 @@ library (sg13g2_stdcell_slow_1p08V_125C) { } timing () { related_pin : "TE_B"; + sdf_edges : start_edge; timing_sense : positive_unate; timing_type : three_state_disable; cell_rise (TIMING_DELAY_7x7ds1) { @@ -15405,6 +15470,7 @@ library (sg13g2_stdcell_slow_1p08V_125C) { } timing () { related_pin : "TE_B"; + sdf_edges : start_edge; timing_sense : negative_unate; timing_type : three_state_enable; cell_rise (TIMING_DELAY_7x7ds1) { @@ -15524,9 +15590,9 @@ library (sg13g2_stdcell_slow_1p08V_125C) { max_transition : 2.5074; capacitance : 0.00539666; rise_capacitance : 0.00550323; - rise_capacitance_range (0.00550323, 0.00550323); + rise_capacitance_range (0.00502061, 0.00587809); fall_capacitance : 0.0052901; - fall_capacitance_range (0.0052901, 0.0052901); + fall_capacitance_range (0.00490736, 0.00565855); internal_power () { rise_power (passive_POWER_7x1ds1) { index_1 ("0.0186, 0.0966, 0.174, 0.3294, 0.6408, 1.263, 2.5074"); @@ -15547,9 +15613,9 @@ library (sg13g2_stdcell_slow_1p08V_125C) { max_transition : 2.5074; capacitance : 0.0165732; rise_capacitance : 0.0172166; - rise_capacitance_range (0.0172166, 0.0172166); + rise_capacitance_range (0.0130955, 0.0235026); fall_capacitance : 0.0159299; - fall_capacitance_range (0.0159299, 0.0159299); + fall_capacitance_range (0.0107163, 0.0176123); internal_power () { rise_power (passive_POWER_7x1ds1) { index_1 ("0.0186, 0.0966, 0.174, 0.3294, 0.6408, 1.263, 2.5074"); @@ -15568,7 +15634,7 @@ library (sg13g2_stdcell_slow_1p08V_125C) { } cell (sg13g2_einvn_2) { area : 16.3296; - cell_footprint : "einvin"; + cell_footprint : "einvn"; cell_leakage_power : 697.533; leakage_power () { value : 355.005; @@ -15648,6 +15714,7 @@ library (sg13g2_stdcell_slow_1p08V_125C) { } timing () { related_pin : "TE_B"; + sdf_edges : start_edge; timing_sense : positive_unate; timing_type : three_state_disable_rise; cell_rise (TIMING_DELAY_7x7ds1) { @@ -15679,6 +15746,7 @@ library (sg13g2_stdcell_slow_1p08V_125C) { } timing () { related_pin : "TE_B"; + sdf_edges : start_edge; timing_sense : negative_unate; timing_type : three_state_enable_rise; cell_rise (TIMING_DELAY_7x7ds1) { @@ -15764,9 +15832,9 @@ library (sg13g2_stdcell_slow_1p08V_125C) { max_transition : 2.5074; capacitance : 0.00401197; rise_capacitance : 0.00417223; - rise_capacitance_range (0.00417223, 0.00417223); + rise_capacitance_range (0.00283203, 0.00614082); fall_capacitance : 0.00385171; - fall_capacitance_range (0.00385171, 0.00385171); + fall_capacitance_range (0.0024205, 0.00587967); internal_power () { rise_power (passive_POWER_7x1ds1) { index_1 ("0.0186, 0.0966, 0.174, 0.3294, 0.6408, 1.263, 2.5074"); @@ -15787,9 +15855,9 @@ library (sg13g2_stdcell_slow_1p08V_125C) { max_transition : 2.5074; capacitance : 0.00452548; rise_capacitance : 0.00523847; - rise_capacitance_range (0.00523847, 0.00523847); + rise_capacitance_range (0.00491152, 0.00541795); fall_capacitance : 0.00381249; - fall_capacitance_range (0.00381249, 0.00381249); + fall_capacitance_range (0.00290043, 0.00541466); internal_power () { rise_power (passive_POWER_7x1ds1) { index_1 ("0.0186, 0.0966, 0.174, 0.3294, 0.6408, 1.263, 2.5074"); @@ -15808,7 +15876,7 @@ library (sg13g2_stdcell_slow_1p08V_125C) { } cell (sg13g2_einvn_4) { area : 23.5872; - cell_footprint : "einvin"; + cell_footprint : "einvn"; cell_leakage_power : 1402.49; leakage_power () { value : 717.432; @@ -15888,6 +15956,7 @@ library (sg13g2_stdcell_slow_1p08V_125C) { } timing () { related_pin : "TE_B"; + sdf_edges : start_edge; timing_sense : positive_unate; timing_type : three_state_disable_rise; cell_rise (TIMING_DELAY_7x7ds1) { @@ -15919,6 +15988,7 @@ library (sg13g2_stdcell_slow_1p08V_125C) { } timing () { related_pin : "TE_B"; + sdf_edges : start_edge; timing_sense : negative_unate; timing_type : three_state_enable_rise; cell_rise (TIMING_DELAY_7x7ds1) { @@ -16004,9 +16074,9 @@ library (sg13g2_stdcell_slow_1p08V_125C) { max_transition : 2.5074; capacitance : 0.00780205; rise_capacitance : 0.00811194; - rise_capacitance_range (0.00811194, 0.00811194); + rise_capacitance_range (0.0053834, 0.0121818); fall_capacitance : 0.00749215; - fall_capacitance_range (0.00749215, 0.00749215); + fall_capacitance_range (0.00459692, 0.0116839); internal_power () { rise_power (passive_POWER_7x1ds1) { index_1 ("0.0186, 0.0966, 0.174, 0.3294, 0.6408, 1.263, 2.5074"); @@ -16027,9 +16097,9 @@ library (sg13g2_stdcell_slow_1p08V_125C) { max_transition : 2.5074; capacitance : 0.00843215; rise_capacitance : 0.0097858; - rise_capacitance_range (0.0097858, 0.0097858); + rise_capacitance_range (0.00899861, 0.0101696); fall_capacitance : 0.00707851; - fall_capacitance_range (0.00707851, 0.00707851); + fall_capacitance_range (0.00532672, 0.0101444); internal_power () { rise_power (passive_POWER_7x1ds1) { index_1 ("0.0186, 0.0966, 0.174, 0.3294, 0.6408, 1.263, 2.5074"); @@ -16048,7 +16118,7 @@ library (sg13g2_stdcell_slow_1p08V_125C) { } cell (sg13g2_einvn_8) { area : 39.9168; - cell_footprint : "ITL"; + cell_footprint : "einvn"; cell_leakage_power : 2669.69; leakage_power () { value : 1299.58; @@ -16128,6 +16198,7 @@ library (sg13g2_stdcell_slow_1p08V_125C) { } timing () { related_pin : "TE_B"; + sdf_edges : start_edge; timing_sense : positive_unate; timing_type : three_state_disable_rise; cell_rise (TIMING_DELAY_7x7ds1) { @@ -16159,6 +16230,7 @@ library (sg13g2_stdcell_slow_1p08V_125C) { } timing () { related_pin : "TE_B"; + sdf_edges : start_edge; timing_sense : negative_unate; timing_type : three_state_enable_rise; cell_rise (TIMING_DELAY_7x7ds1) { @@ -16244,9 +16316,9 @@ library (sg13g2_stdcell_slow_1p08V_125C) { max_transition : 2.5074; capacitance : 0.0154312; rise_capacitance : 0.0160489; - rise_capacitance_range (0.0160489, 0.0160489); + rise_capacitance_range (0.0104984, 0.0243161); fall_capacitance : 0.0148135; - fall_capacitance_range (0.0148135, 0.0148135); + fall_capacitance_range (0.00897834, 0.0233492); internal_power () { rise_power (passive_POWER_7x1ds1) { index_1 ("0.0186, 0.0966, 0.174, 0.3294, 0.6408, 1.263, 2.5074"); @@ -16267,9 +16339,9 @@ library (sg13g2_stdcell_slow_1p08V_125C) { max_transition : 2.5074; capacitance : 0.014513; rise_capacitance : 0.0166349; - rise_capacitance_range (0.0166349, 0.0166349); + rise_capacitance_range (0.0145606, 0.0173602); fall_capacitance : 0.0123912; - fall_capacitance_range (0.0123912, 0.0123912); + fall_capacitance_range (0.010013, 0.0173846); internal_power () { rise_power (passive_POWER_7x1ds1) { index_1 ("0.0186, 0.0966, 0.174, 0.3294, 0.6408, 1.263, 2.5074"); @@ -16320,7 +16392,7 @@ library (sg13g2_stdcell_slow_1p08V_125C) { } cell (sg13g2_inv_1) { area : 5.4432; - cell_footprint : "IN"; + cell_footprint : "inv"; cell_leakage_power : 306.521; leakage_power () { value : 477.753; @@ -16427,14 +16499,14 @@ library (sg13g2_stdcell_slow_1p08V_125C) { max_transition : 2.5074; capacitance : 0.0027026; rise_capacitance : 0.00275916; - rise_capacitance_range (0.00275916, 0.00275916); + rise_capacitance_range (0.0024003, 0.00303269); fall_capacitance : 0.00264605; - fall_capacitance_range (0.00264605, 0.00264605); + fall_capacitance_range (0.00238329, 0.00297076); } } cell (sg13g2_inv_16) { area : 34.4736; - cell_footprint : "IN"; + cell_footprint : "inv"; cell_leakage_power : 4902.84; leakage_power () { value : 7643.12; @@ -16541,14 +16613,14 @@ library (sg13g2_stdcell_slow_1p08V_125C) { max_transition : 2.5074; capacitance : 0.0411388; rise_capacitance : 0.0419824; - rise_capacitance_range (0.0419824, 0.0419824); + rise_capacitance_range (0.0308508, 0.0484986); fall_capacitance : 0.0402952; - fall_capacitance_range (0.0402952, 0.0402952); + fall_capacitance_range (0.0313173, 0.0481504); } } cell (sg13g2_inv_2) { area : 7.2576; - cell_footprint : "IN"; + cell_footprint : "inv"; cell_leakage_power : 612.864; leakage_power () { value : 955.403; @@ -16655,14 +16727,14 @@ library (sg13g2_stdcell_slow_1p08V_125C) { max_transition : 2.5074; capacitance : 0.00534309; rise_capacitance : 0.00545452; - rise_capacitance_range (0.00545452, 0.00545452); + rise_capacitance_range (0.00460259, 0.00607948); fall_capacitance : 0.00523167; - fall_capacitance_range (0.00523167, 0.00523167); + fall_capacitance_range (0.00460985, 0.00600937); } } cell (sg13g2_inv_4) { area : 10.8864; - cell_footprint : "IN"; + cell_footprint : "inv"; cell_leakage_power : 1225.71; leakage_power () { value : 1910.78; @@ -16769,14 +16841,14 @@ library (sg13g2_stdcell_slow_1p08V_125C) { max_transition : 2.5074; capacitance : 0.0105523; rise_capacitance : 0.0107742; - rise_capacitance_range (0.0107742, 0.0107742); + rise_capacitance_range (0.00902995, 0.0120869); fall_capacitance : 0.0103304; - fall_capacitance_range (0.0103304, 0.0103304); + fall_capacitance_range (0.00906551, 0.0120003); } } cell (sg13g2_inv_8) { area : 18.144; - cell_footprint : "IN"; + cell_footprint : "inv"; cell_leakage_power : 2451.44; leakage_power () { value : 3821.6; @@ -16883,14 +16955,14 @@ library (sg13g2_stdcell_slow_1p08V_125C) { max_transition : 2.5074; capacitance : 0.0211172; rise_capacitance : 0.0215595; - rise_capacitance_range (0.0215595, 0.0215595); + rise_capacitance_range (0.0179564, 0.0242704); fall_capacitance : 0.0206749; - fall_capacitance_range (0.0206749, 0.0206749); + fall_capacitance_range (0.017995, 0.0241486); } } cell (sg13g2_lgcp_1) { area : 27.216; - cell_footprint : "gclk"; + cell_footprint : "lgcp"; cell_leakage_power : 1819.5; clock_gating_integrated_cell : "latch_posedge"; dont_use : true; @@ -17014,9 +17086,9 @@ library (sg13g2_stdcell_slow_1p08V_125C) { max_transition : 2.5074; capacitance : 0.00458603; rise_capacitance : 0.00459629; - rise_capacitance_range (0.00459629, 0.00459629); + rise_capacitance_range (0.00415896, 0.00512584); fall_capacitance : 0.00457576; - fall_capacitance_range (0.00457576, 0.00457576); + fall_capacitance_range (0.0042423, 0.0048246); timing () { related_pin : "CLK"; timing_type : min_pulse_width; @@ -17054,11 +17126,12 @@ library (sg13g2_stdcell_slow_1p08V_125C) { max_transition : 2.5074; capacitance : 0.00216722; rise_capacitance : 0.00229449; - rise_capacitance_range (0.00229449, 0.00229449); + rise_capacitance_range (0.0020961, 0.00246389); fall_capacitance : 0.00203994; - fall_capacitance_range (0.00203994, 0.00203994); + fall_capacitance_range (0.00201883, 0.00226758); timing () { related_pin : "CLK"; + sdf_edges : both_edges; timing_type : hold_rising; rise_constraint (CONSTRAINT_4x4) { index_1 ("0.0186, 0.51636, 1.263, 2.5074"); @@ -17083,6 +17156,7 @@ library (sg13g2_stdcell_slow_1p08V_125C) { } timing () { related_pin : "CLK"; + sdf_edges : both_edges; timing_type : setup_rising; rise_constraint (CONSTRAINT_4x4) { index_1 ("0.0186, 0.51636, 1.263, 2.5074"); @@ -17293,7 +17367,7 @@ library (sg13g2_stdcell_slow_1p08V_125C) { } timing () { related_pin : "S"; - sdf_cond : "A0 == 1'b0 & A1 == 1'b1"; + sdf_cond : "A0 == 1'b0 && A1 == 1'b1"; timing_sense : positive_unate; timing_type : combinational; when : "(!A0 * A1)"; @@ -17409,7 +17483,7 @@ library (sg13g2_stdcell_slow_1p08V_125C) { } timing () { related_pin : "S"; - sdf_cond : "A0 == 1'b1 & A1 == 1'b0"; + sdf_cond : "A0 == 1'b1 && A1 == 1'b0"; timing_sense : negative_unate; timing_type : combinational; when : "(A0 * !A1)"; @@ -17619,27 +17693,27 @@ library (sg13g2_stdcell_slow_1p08V_125C) { max_transition : 2.5074; capacitance : 0.00259449; rise_capacitance : 0.00262687; - rise_capacitance_range (0.00262687, 0.00262687); + rise_capacitance_range (0.0023345, 0.00284793); fall_capacitance : 0.0025621; - fall_capacitance_range (0.0025621, 0.0025621); + fall_capacitance_range (0.0022669, 0.00274773); } pin (A1) { direction : "input"; max_transition : 2.5074; capacitance : 0.00270181; rise_capacitance : 0.00272998; - rise_capacitance_range (0.00272998, 0.00272998); + rise_capacitance_range (0.00243798, 0.00294983); fall_capacitance : 0.00267364; - fall_capacitance_range (0.00267364, 0.00267364); + fall_capacitance_range (0.00241652, 0.00285133); } pin (S) { direction : "input"; max_transition : 2.5074; capacitance : 0.00463938; rise_capacitance : 0.00470463; - rise_capacitance_range (0.00470463, 0.00470463); + rise_capacitance_range (0.00410784, 0.00558688); fall_capacitance : 0.00457413; - fall_capacitance_range (0.00457413, 0.00457413); + fall_capacitance_range (0.00408591, 0.00543383); internal_power () { when : "(A0 * A1)"; rise_power (passive_POWER_7x1ds1) { @@ -17843,7 +17917,7 @@ library (sg13g2_stdcell_slow_1p08V_125C) { } timing () { related_pin : "S"; - sdf_cond : "A0 == 1'b0 & A1 == 1'b1"; + sdf_cond : "A0 == 1'b0 && A1 == 1'b1"; timing_sense : positive_unate; timing_type : combinational; when : "(!A0 * A1)"; @@ -17959,7 +18033,7 @@ library (sg13g2_stdcell_slow_1p08V_125C) { } timing () { related_pin : "S"; - sdf_cond : "A0 == 1'b1 & A1 == 1'b0"; + sdf_cond : "A0 == 1'b1 && A1 == 1'b0"; timing_sense : negative_unate; timing_type : combinational; when : "(A0 * !A1)"; @@ -18169,27 +18243,27 @@ library (sg13g2_stdcell_slow_1p08V_125C) { max_transition : 2.5074; capacitance : 0.00259668; rise_capacitance : 0.00262997; - rise_capacitance_range (0.00262997, 0.00262997); + rise_capacitance_range (0.00238724, 0.002825); fall_capacitance : 0.00256338; - fall_capacitance_range (0.00256338, 0.00256338); + fall_capacitance_range (0.00232269, 0.00272178); } pin (A1) { direction : "input"; max_transition : 2.5074; capacitance : 0.00270178; rise_capacitance : 0.0027325; - rise_capacitance_range (0.0027325, 0.0027325); + rise_capacitance_range (0.0024879, 0.00292819); fall_capacitance : 0.00267105; - fall_capacitance_range (0.00267105, 0.00267105); + fall_capacitance_range (0.00245205, 0.00282436); } pin (S) { direction : "input"; max_transition : 2.5074; capacitance : 0.00463233; rise_capacitance : 0.00469804; - rise_capacitance_range (0.00469804, 0.00469804); + rise_capacitance_range (0.00410425, 0.00557877); fall_capacitance : 0.00456663; - fall_capacitance_range (0.00456663, 0.00456663); + fall_capacitance_range (0.0040755, 0.00542569); internal_power () { when : "(A0 * A1)"; rise_power (passive_POWER_7x1ds1) { @@ -18731,7 +18805,7 @@ library (sg13g2_stdcell_slow_1p08V_125C) { } timing () { related_pin : "S0"; - sdf_cond : "A2 == 1'b0 & A3 == 1'b1 & S1 == 1'b1"; + sdf_cond : "A2 == 1'b0 && A3 == 1'b1 && S1 == 1'b1"; timing_sense : positive_unate; timing_type : combinational; when : "(!A2 * A3 * S1)"; @@ -18790,7 +18864,7 @@ library (sg13g2_stdcell_slow_1p08V_125C) { } timing () { related_pin : "S0"; - sdf_cond : "A0 == 1'b0 & A1 == 1'b1 & S1 == 1'b0"; + sdf_cond : "A0 == 1'b0 && A1 == 1'b1 && S1 == 1'b0"; timing_sense : positive_unate; timing_type : combinational; when : "(!A0 * A1 * !S1)"; @@ -18906,7 +18980,7 @@ library (sg13g2_stdcell_slow_1p08V_125C) { } timing () { related_pin : "S0"; - sdf_cond : "A2 == 1'b1 & A3 == 1'b0 & S1 == 1'b1"; + sdf_cond : "A2 == 1'b1 && A3 == 1'b0 && S1 == 1'b1"; timing_sense : negative_unate; timing_type : combinational; when : "(A2 * !A3 * S1)"; @@ -18965,7 +19039,7 @@ library (sg13g2_stdcell_slow_1p08V_125C) { } timing () { related_pin : "S0"; - sdf_cond : "A0 == 1'b1 & A1 == 1'b0 & S1 == 1'b0"; + sdf_cond : "A0 == 1'b1 && A1 == 1'b0 && S1 == 1'b0"; timing_sense : negative_unate; timing_type : combinational; when : "(A0 * !A1 * !S1)"; @@ -19024,7 +19098,7 @@ library (sg13g2_stdcell_slow_1p08V_125C) { } timing () { related_pin : "S1"; - sdf_cond : "A1 == 1'b0 & A3 == 1'b1 & S0 == 1'b1"; + sdf_cond : "A1 == 1'b0 && A3 == 1'b1 && S0 == 1'b1"; timing_sense : positive_unate; timing_type : combinational; when : "(!A1 * A3 * S0)"; @@ -19083,7 +19157,7 @@ library (sg13g2_stdcell_slow_1p08V_125C) { } timing () { related_pin : "S1"; - sdf_cond : "A0 == 1'b0 & A2 == 1'b1 & S0 == 1'b0"; + sdf_cond : "A0 == 1'b0 && A2 == 1'b1 && S0 == 1'b0"; timing_sense : positive_unate; timing_type : combinational; when : "(!A0 * A2 * !S0)"; @@ -19199,7 +19273,7 @@ library (sg13g2_stdcell_slow_1p08V_125C) { } timing () { related_pin : "S1"; - sdf_cond : "A1 == 1'b1 & A3 == 1'b0 & S0 == 1'b1"; + sdf_cond : "A1 == 1'b1 && A3 == 1'b0 && S0 == 1'b1"; timing_sense : negative_unate; timing_type : combinational; when : "(A1 * !A3 * S0)"; @@ -19258,7 +19332,7 @@ library (sg13g2_stdcell_slow_1p08V_125C) { } timing () { related_pin : "S1"; - sdf_cond : "A0 == 1'b1 & A2 == 1'b0 & S0 == 1'b0"; + sdf_cond : "A0 == 1'b1 && A2 == 1'b0 && S0 == 1'b0"; timing_sense : negative_unate; timing_type : combinational; when : "(A0 * !A2 * !S0)"; @@ -19735,45 +19809,45 @@ library (sg13g2_stdcell_slow_1p08V_125C) { max_transition : 2.5074; capacitance : 0.00256068; rise_capacitance : 0.00260632; - rise_capacitance_range (0.00260632, 0.00260632); + rise_capacitance_range (0.00233544, 0.00288656); fall_capacitance : 0.00251504; - fall_capacitance_range (0.00251504, 0.00251504); + fall_capacitance_range (0.00228859, 0.00280753); } pin (A1) { direction : "input"; max_transition : 2.5074; capacitance : 0.00254015; rise_capacitance : 0.00258688; - rise_capacitance_range (0.00258688, 0.00258688); + rise_capacitance_range (0.00233546, 0.00286512); fall_capacitance : 0.00249343; - fall_capacitance_range (0.00249343, 0.00249343); + fall_capacitance_range (0.00222587, 0.00278571); } pin (A2) { direction : "input"; max_transition : 2.5074; capacitance : 0.00256061; rise_capacitance : 0.0026065; - rise_capacitance_range (0.0026065, 0.0026065); + rise_capacitance_range (0.00233792, 0.00288245); fall_capacitance : 0.00251473; - fall_capacitance_range (0.00251473, 0.00251473); + fall_capacitance_range (0.00225678, 0.00280771); } pin (A3) { direction : "input"; max_transition : 2.5074; capacitance : 0.00262273; rise_capacitance : 0.00266823; - rise_capacitance_range (0.00266823, 0.00266823); + rise_capacitance_range (0.00238822, 0.00294166); fall_capacitance : 0.00257723; - fall_capacitance_range (0.00257723, 0.00257723); + fall_capacitance_range (0.00229904, 0.00287092); } pin (S0) { direction : "input"; max_transition : 2.5074; capacitance : 0.00781619; rise_capacitance : 0.00932325; - rise_capacitance_range (0.00932325, 0.00932325); + rise_capacitance_range (0.00691618, 0.0107088); fall_capacitance : 0.00630914; - fall_capacitance_range (0.00630914, 0.00630914); + fall_capacitance_range (0.00416072, 0.00921211); internal_power () { when : "(A2 * A3 * S1)"; rise_power (passive_POWER_7x1ds1) { @@ -19854,9 +19928,9 @@ library (sg13g2_stdcell_slow_1p08V_125C) { max_transition : 2.5074; capacitance : 0.00472555; rise_capacitance : 0.00478658; - rise_capacitance_range (0.00478658, 0.00478658); + rise_capacitance_range (0.00402648, 0.00555491); fall_capacitance : 0.00466452; - fall_capacitance_range (0.00466452, 0.00466452); + fall_capacitance_range (0.00401761, 0.00534916); internal_power () { when : "(A1 * A3 * S0)"; rise_power (passive_POWER_7x1ds1) { @@ -20136,18 +20210,18 @@ library (sg13g2_stdcell_slow_1p08V_125C) { max_transition : 2.5074; capacitance : 0.00272248; rise_capacitance : 0.00277468; - rise_capacitance_range (0.00277468, 0.00277468); + rise_capacitance_range (0.00242924, 0.0029993); fall_capacitance : 0.00267027; - fall_capacitance_range (0.00267027, 0.00267027); + fall_capacitance_range (0.00230414, 0.0030129); } pin (B) { direction : "input"; max_transition : 2.5074; capacitance : 0.00278739; rise_capacitance : 0.00288191; - rise_capacitance_range (0.00288191, 0.00288191); + rise_capacitance_range (0.00251623, 0.00323939); fall_capacitance : 0.00269288; - fall_capacitance_range (0.00269288, 0.00269288); + fall_capacitance_range (0.00249856, 0.00293859); } } cell (sg13g2_nand2_2) { @@ -20353,23 +20427,23 @@ library (sg13g2_stdcell_slow_1p08V_125C) { max_transition : 2.5074; capacitance : 0.00526732; rise_capacitance : 0.00538044; - rise_capacitance_range (0.00538044, 0.00538044); + rise_capacitance_range (0.0046237, 0.00583821); fall_capacitance : 0.0051542; - fall_capacitance_range (0.0051542, 0.0051542); + fall_capacitance_range (0.00433638, 0.00594065); } pin (B) { direction : "input"; max_transition : 2.5074; capacitance : 0.00533956; rise_capacitance : 0.00553447; - rise_capacitance_range (0.00553447, 0.00553447); + rise_capacitance_range (0.00480553, 0.00622311); fall_capacitance : 0.00514465; - fall_capacitance_range (0.00514465, 0.00514465); + fall_capacitance_range (0.0047248, 0.00567278); } } cell (sg13g2_nand2b_1) { area : 9.072; - cell_footprint : "nand2b1"; + cell_footprint : "nand2b"; cell_leakage_power : 541.445; leakage_power () { value : 1046.64; @@ -20570,9 +20644,9 @@ library (sg13g2_stdcell_slow_1p08V_125C) { max_transition : 2.5074; capacitance : 0.00209247; rise_capacitance : 0.00212662; - rise_capacitance_range (0.00212662, 0.00212662); + rise_capacitance_range (0.00191742, 0.00227526); fall_capacitance : 0.00205833; - fall_capacitance_range (0.00205833, 0.00205833); + fall_capacitance_range (0.00189168, 0.00221333); internal_power () { when : "!B"; rise_power (passive_POWER_7x1ds1) { @@ -20608,14 +20682,14 @@ library (sg13g2_stdcell_slow_1p08V_125C) { max_transition : 2.5074; capacitance : 0.00283461; rise_capacitance : 0.00292952; - rise_capacitance_range (0.00292952, 0.00292952); + rise_capacitance_range (0.00255356, 0.00328619); fall_capacitance : 0.0027397; - fall_capacitance_range (0.0027397, 0.0027397); + fall_capacitance_range (0.00254112, 0.00298346); } } cell (sg13g2_nand2b_2) { area : 14.5152; - cell_footprint : "nand2b2"; + cell_footprint : "nand2b"; cell_leakage_power : 852.367; leakage_power () { value : 2001.46; @@ -20816,9 +20890,9 @@ library (sg13g2_stdcell_slow_1p08V_125C) { max_transition : 2.5074; capacitance : 0.00205966; rise_capacitance : 0.00209716; - rise_capacitance_range (0.00209716, 0.00209716); + rise_capacitance_range (0.00196298, 0.00221119); fall_capacitance : 0.00202215; - fall_capacitance_range (0.00202215, 0.00202215); + fall_capacitance_range (0.00189825, 0.00214427); internal_power () { when : "!B"; rise_power (passive_POWER_7x1ds1) { @@ -20854,9 +20928,9 @@ library (sg13g2_stdcell_slow_1p08V_125C) { max_transition : 2.5074; capacitance : 0.00529057; rise_capacitance : 0.0054052; - rise_capacitance_range (0.0054052, 0.0054052); + rise_capacitance_range (0.00464557, 0.00586339); fall_capacitance : 0.00517595; - fall_capacitance_range (0.00517595, 0.00517595); + fall_capacitance_range (0.00433858, 0.00596731); } } cell (sg13g2_nand3_1) { @@ -21164,32 +21238,32 @@ library (sg13g2_stdcell_slow_1p08V_125C) { max_transition : 2.5074; capacitance : 0.00271728; rise_capacitance : 0.00276639; - rise_capacitance_range (0.00276639, 0.00276639); + rise_capacitance_range (0.00245945, 0.00295158); fall_capacitance : 0.00266817; - fall_capacitance_range (0.00266817, 0.00266817); + fall_capacitance_range (0.0022847, 0.00300547); } pin (B) { direction : "input"; max_transition : 2.5074; capacitance : 0.00282041; rise_capacitance : 0.00290798; - rise_capacitance_range (0.00290798, 0.00290798); + rise_capacitance_range (0.00255491, 0.00325501); fall_capacitance : 0.00273284; - fall_capacitance_range (0.00273284, 0.00273284); + fall_capacitance_range (0.00247374, 0.00299323); } pin (C) { direction : "input"; max_transition : 2.5074; capacitance : 0.00278768; rise_capacitance : 0.00288345; - rise_capacitance_range (0.00288345, 0.00288345); + rise_capacitance_range (0.00254011, 0.0032037); fall_capacitance : 0.00269191; - fall_capacitance_range (0.00269191, 0.00269191); + fall_capacitance_range (0.00254249, 0.00289563); } } cell (sg13g2_nand3b_1) { area : 12.7008; - cell_footprint : "nand3b1"; + cell_footprint : "nand3b"; cell_leakage_power : 476.689; leakage_power () { value : 138.731; @@ -21492,9 +21566,9 @@ library (sg13g2_stdcell_slow_1p08V_125C) { max_transition : 2.5074; capacitance : 0.00207277; rise_capacitance : 0.00210708; - rise_capacitance_range (0.00210708, 0.00210708); + rise_capacitance_range (0.00189813, 0.00225571); fall_capacitance : 0.00203845; - fall_capacitance_range (0.00203845, 0.00203845); + fall_capacitance_range (0.00187179, 0.00219394); internal_power () { when : "(B * !C) + (!B)"; rise_power (passive_POWER_7x1ds1) { @@ -21530,18 +21604,18 @@ library (sg13g2_stdcell_slow_1p08V_125C) { max_transition : 2.5074; capacitance : 0.00278377; rise_capacitance : 0.00287163; - rise_capacitance_range (0.00287163, 0.00287163); + rise_capacitance_range (0.00250622, 0.00321951); fall_capacitance : 0.0026959; - fall_capacitance_range (0.0026959, 0.0026959); + fall_capacitance_range (0.00242823, 0.00295451); } pin (C) { direction : "input"; max_transition : 2.5074; capacitance : 0.00279915; rise_capacitance : 0.00289522; - rise_capacitance_range (0.00289522, 0.00289522); + rise_capacitance_range (0.00255426, 0.00321379); fall_capacitance : 0.00270308; - fall_capacitance_range (0.00270308, 0.00270308); + fall_capacitance_range (0.00255296, 0.00290618); } } cell (sg13g2_nand4_1) { @@ -21625,11 +21699,11 @@ library (sg13g2_stdcell_slow_1p08V_125C) { index_1 ("0.0186, 0.0966, 0.174, 0.3294, 0.6408, 1.263, 2.5074"); index_2 ("0.001, 0.0234, 0.039, 0.0648, 0.108, 0.18, 0.3"); values ( \ - "0.038254, 0.136918, 0.204526, 0.31631, 0.503511, 0.815099, 1.33471", \ - "0.0715789, 0.1818, 0.249521, 0.361292, 0.549329, 0.860305, 1.38019", \ - "0.0932177, 0.225796, 0.295925, 0.408018, 0.595098, 0.908175, 1.42678", \ + "0.0382515, 0.13693, 0.20455, 0.316303, 0.503539, 0.81507, 1.33475", \ + "0.0715791, 0.181774, 0.249497, 0.361271, 0.548603, 0.860259, 1.38017", \ + "0.0932177, 0.22579, 0.295898, 0.40802, 0.595098, 0.906795, 1.42678", \ "0.123138, 0.298532, 0.379495, 0.498456, 0.686615, 0.997459, 1.51728", \ - "0.158688, 0.40449, 0.509695, 0.652937, 0.860028, 1.17868, 1.69659", \ + "0.158688, 0.40449, 0.509695, 0.652937, 0.860028, 1.17869, 1.69659", \ "0.195862, 0.548884, 0.699171, 0.893112, 1.15194, 1.51277, 2.05421", \ "0.23066, 0.7423, 0.957829, 1.23652, 1.5937, 2.06584, 2.70879" \ ); @@ -21638,25 +21712,25 @@ library (sg13g2_stdcell_slow_1p08V_125C) { index_1 ("0.0186, 0.0966, 0.174, 0.3294, 0.6408, 1.263, 2.5074"); index_2 ("0.001, 0.0234, 0.039, 0.0648, 0.108, 0.18, 0.3"); values ( \ - "0.0294298, 0.167827, 0.264643, 0.424614, 0.692623, 1.13963, 1.88403", \ - "0.0452463, 0.170489, 0.265069, 0.425212, 0.693486, 1.13964, 1.88404", \ - "0.0632522, 0.183955, 0.272757, 0.426959, 0.693487, 1.14057, 1.88411", \ + "0.0294248, 0.167863, 0.264656, 0.424614, 0.692668, 1.13948, 1.88395", \ + "0.0452462, 0.170476, 0.264974, 0.425147, 0.692669, 1.13949, 1.88396", \ + "0.0632522, 0.183989, 0.27276, 0.426886, 0.692908, 1.1395, 1.88411", \ "0.0933695, 0.221586, 0.303549, 0.446073, 0.699627, 1.14106, 1.88412", \ - "0.14318, 0.298493, 0.383202, 0.516538, 0.748974, 1.16197, 1.8925", \ + "0.14318, 0.298493, 0.383202, 0.516538, 0.748974, 1.16198, 1.8925", \ "0.219045, 0.432341, 0.531525, 0.675131, 0.898167, 1.27826, 1.94914", \ - "0.344446, 0.649294, 0.783666, 0.959824, 1.21246, 1.59434, 2.22188" \ + "0.344446, 0.649294, 0.783666, 0.959825, 1.21246, 1.59434, 2.22188" \ ); } cell_fall (TIMING_DELAY_7x7ds1) { index_1 ("0.0186, 0.0966, 0.174, 0.3294, 0.6408, 1.263, 2.5074"); index_2 ("0.001, 0.0234, 0.039, 0.0648, 0.108, 0.18, 0.3"); values ( \ - "0.0917144, 0.386864, 0.589753, 0.925076, 1.4864, 2.42207, 3.98116", \ - "0.119071, 0.418764, 0.623145, 0.958385, 1.52032, 2.45625, 4.01508", \ - "0.143446, 0.452299, 0.65594, 0.992689, 1.55477, 2.49043, 4.05049", \ - "0.182093, 0.521481, 0.726746, 1.06269, 1.62446, 2.56038, 4.11994", \ - "0.234392, 0.641042, 0.861864, 1.20291, 1.76384, 2.69918, 4.25877", \ - "0.308996, 0.825042, 1.08489, 1.46425, 2.04658, 2.98319, 4.5388", \ + "0.0917201, 0.386855, 0.589748, 0.925089, 1.48642, 2.42206, 3.98063", \ + "0.119039, 0.418681, 0.623161, 0.958365, 1.52031, 2.45624, 4.01506", \ + "0.143446, 0.452299, 0.655956, 0.992688, 1.55465, 2.49044, 4.05055", \ + "0.182093, 0.52148, 0.726745, 1.06256, 1.62429, 2.56044, 4.11992", \ + "0.234392, 0.641042, 0.861863, 1.20291, 1.76392, 2.69883, 4.25879", \ + "0.308995, 0.825042, 1.08488, 1.46425, 2.04658, 2.98319, 4.53878", \ "0.416239, 1.08861, 1.41805, 1.8767, 2.54187, 3.53994, 5.11221" \ ); } @@ -21664,13 +21738,13 @@ library (sg13g2_stdcell_slow_1p08V_125C) { index_1 ("0.0186, 0.0966, 0.174, 0.3294, 0.6408, 1.263, 2.5074"); index_2 ("0.001, 0.0234, 0.039, 0.0648, 0.108, 0.18, 0.3"); values ( \ - "0.0844309, 0.466747, 0.732596, 1.17172, 1.90732, 3.1334, 5.17726", \ - "0.09217, 0.466748, 0.733408, 1.17211, 1.90736, 3.13549, 5.17936", \ - "0.106602, 0.469352, 0.733582, 1.17275, 1.90759, 3.13611, 5.17937", \ - "0.134133, 0.486726, 0.740875, 1.18065, 1.90998, 3.13612, 5.17938", \ - "0.18192, 0.548417, 0.787577, 1.19826, 1.91386, 3.13613, 5.17939", \ - "0.254084, 0.678005, 0.918665, 1.30934, 1.98424, 3.15944, 5.21698", \ - "0.37251, 0.901299, 1.17235, 1.57486, 2.22987, 3.33488, 5.27074" \ + "0.0844195, 0.466746, 0.732596, 1.17171, 1.90732, 3.1334, 5.18133", \ + "0.0922228, 0.466747, 0.733406, 1.17211, 1.90735, 3.13549, 5.18134", \ + "0.106602, 0.469351, 0.733861, 1.17275, 1.90901, 3.13611, 5.18135", \ + "0.134133, 0.486725, 0.740874, 1.18048, 1.90902, 3.13612, 5.18136", \ + "0.18192, 0.548416, 0.787576, 1.19826, 1.91585, 3.13613, 5.18137", \ + "0.254084, 0.678005, 0.918664, 1.30934, 1.98424, 3.15944, 5.21691", \ + "0.37251, 0.901299, 1.17235, 1.57486, 2.22987, 3.33488, 5.27073" \ ); } } @@ -21682,11 +21756,11 @@ library (sg13g2_stdcell_slow_1p08V_125C) { index_1 ("0.0186, 0.0966, 0.174, 0.3294, 0.6408, 1.263, 2.5074"); index_2 ("0.001, 0.0234, 0.039, 0.0648, 0.108, 0.18, 0.3"); values ( \ - "0.0441479, 0.142897, 0.210608, 0.32268, 0.509793, 0.821476, 1.341", \ - "0.0802031, 0.187718, 0.255479, 0.367336, 0.554619, 0.866428, 1.3864", \ - "0.105119, 0.232185, 0.302076, 0.414247, 0.60114, 0.913885, 1.4327", \ - "0.140969, 0.306476, 0.386389, 0.504765, 0.692881, 1.00396, 1.52321", \ - "0.185382, 0.415511, 0.518614, 0.660244, 0.866554, 1.18351, 1.70284", \ + "0.0440997, 0.142878, 0.210619, 0.322681, 0.509781, 0.821425, 1.34102", \ + "0.0802194, 0.187711, 0.2555, 0.367425, 0.554563, 0.866437, 1.3864", \ + "0.10512, 0.232152, 0.302069, 0.414224, 0.601258, 0.913917, 1.43334", \ + "0.140969, 0.306476, 0.386389, 0.504765, 0.692865, 1.00396, 1.52337", \ + "0.185382, 0.415511, 0.518614, 0.660244, 0.866554, 1.18351, 1.70282", \ "0.235031, 0.565438, 0.712545, 0.902861, 1.15969, 1.51981, 2.05978", \ "0.28798, 0.766831, 0.977381, 1.25167, 1.60498, 2.07486, 2.71443" \ ); @@ -21695,11 +21769,11 @@ library (sg13g2_stdcell_slow_1p08V_125C) { index_1 ("0.0186, 0.0966, 0.174, 0.3294, 0.6408, 1.263, 2.5074"); index_2 ("0.001, 0.0234, 0.039, 0.0648, 0.108, 0.18, 0.3"); values ( \ - "0.0345991, 0.173599, 0.270421, 0.430637, 0.698815, 1.14545, 1.88992", \ - "0.0482831, 0.175803, 0.270542, 0.431501, 0.698816, 1.14613, 1.89004", \ - "0.0658944, 0.188705, 0.278016, 0.432617, 0.698851, 1.14669, 1.89017", \ - "0.0953572, 0.22544, 0.307981, 0.451181, 0.705384, 1.14744, 1.89018", \ - "0.145055, 0.302021, 0.386717, 0.521368, 0.754221, 1.1677, 1.90013", \ + "0.0346008, 0.173425, 0.270399, 0.430637, 0.698819, 1.14537, 1.88992", \ + "0.0483362, 0.175809, 0.270666, 0.430638, 0.69882, 1.14613, 1.89004", \ + "0.0658939, 0.188722, 0.27801, 0.432602, 0.698852, 1.1467, 1.8903", \ + "0.0953572, 0.22544, 0.307981, 0.451181, 0.705377, 1.14744, 1.89031", \ + "0.145055, 0.302021, 0.386717, 0.521368, 0.754221, 1.1677, 1.89937", \ "0.221144, 0.433527, 0.533263, 0.678468, 0.902056, 1.2834, 1.95526", \ "0.343341, 0.652664, 0.784329, 0.962318, 1.2165, 1.59736, 2.22812" \ ); @@ -21708,26 +21782,26 @@ library (sg13g2_stdcell_slow_1p08V_125C) { index_1 ("0.0186, 0.0966, 0.174, 0.3294, 0.6408, 1.263, 2.5074"); index_2 ("0.001, 0.0234, 0.039, 0.0648, 0.108, 0.18, 0.3"); values ( \ - "0.113244, 0.406905, 0.609678, 0.94511, 1.50641, 2.442, 4.00127", \ - "0.142594, 0.440459, 0.643818, 0.979673, 1.54141, 2.47738, 4.0368", \ - "0.167662, 0.473264, 0.677127, 1.01309, 1.57499, 2.51126, 4.07084", \ - "0.208906, 0.539116, 0.744779, 1.08153, 1.64379, 2.58043, 4.13983", \ - "0.263977, 0.65444, 0.873035, 1.21551, 1.7788, 2.71509, 4.27606", \ - "0.339752, 0.839585, 1.09124, 1.46394, 2.04652, 2.98777, 4.54775", \ - "0.455019, 1.11469, 1.43121, 1.87366, 2.52303, 3.51561, 5.09375" \ + "0.113245, 0.406928, 0.609685, 0.945108, 1.5064, 2.44199, 4.00128", \ + "0.142582, 0.440367, 0.64381, 0.979674, 1.54122, 2.47732, 4.0368", \ + "0.167661, 0.473264, 0.677136, 1.01306, 1.57503, 2.51092, 4.07083", \ + "0.208906, 0.539116, 0.744796, 1.08153, 1.64379, 2.58043, 4.13957", \ + "0.263977, 0.65444, 0.873034, 1.21551, 1.7788, 2.71563, 4.27614", \ + "0.339751, 0.839584, 1.09124, 1.46394, 2.04652, 2.98777, 4.54779", \ + "0.455018, 1.11469, 1.43121, 1.87366, 2.52303, 3.5156, 5.09386" \ ); } fall_transition (TIMING_DELAY_7x7ds1) { index_1 ("0.0186, 0.0966, 0.174, 0.3294, 0.6408, 1.263, 2.5074"); index_2 ("0.001, 0.0234, 0.039, 0.0648, 0.108, 0.18, 0.3"); values ( \ - "0.0846171, 0.467129, 0.732835, 1.17172, 1.9073, 3.1334, 5.17684", \ - "0.0894737, 0.46713, 0.732836, 1.17211, 1.90814, 3.13352, 5.17685", \ - "0.0994224, 0.468527, 0.734059, 1.17212, 1.90815, 3.13353, 5.18038", \ - "0.12198, 0.480632, 0.73851, 1.17455, 1.90937, 3.13369, 5.18167", \ - "0.166521, 0.526167, 0.771571, 1.19059, 1.91233, 3.13656, 5.18168", \ - "0.240316, 0.632469, 0.872529, 1.272, 1.96163, 3.15463, 5.18169", \ - "0.356981, 0.833817, 1.08848, 1.48237, 2.14649, 3.27886, 5.24559" \ + "0.0846407, 0.466798, 0.732821, 1.17172, 1.90851, 3.1334, 5.17683", \ + "0.0894537, 0.466799, 0.732822, 1.17211, 1.90852, 3.13352, 5.17684", \ + "0.0994222, 0.468526, 0.73406, 1.1728, 1.90853, 3.1347, 5.18037", \ + "0.12198, 0.480631, 0.738527, 1.17455, 1.90936, 3.13471, 5.18038", \ + "0.166521, 0.526167, 0.77157, 1.19059, 1.91233, 3.13608, 5.18039", \ + "0.240315, 0.632468, 0.872528, 1.272, 1.96163, 3.15467, 5.1804", \ + "0.356981, 0.833817, 1.08848, 1.48303, 2.14649, 3.27886, 5.23972" \ ); } } @@ -21739,10 +21813,10 @@ library (sg13g2_stdcell_slow_1p08V_125C) { index_1 ("0.0186, 0.0966, 0.174, 0.3294, 0.6408, 1.263, 2.5074"); index_2 ("0.001, 0.0234, 0.039, 0.0648, 0.108, 0.18, 0.3"); values ( \ - "0.0473092, 0.147789, 0.215901, 0.328082, 0.51557, 0.827625, 1.34728", \ - "0.0853458, 0.192403, 0.260508, 0.372699, 0.560461, 0.872492, 1.39243", \ - "0.112748, 0.237106, 0.307097, 0.419393, 0.606648, 0.918823, 1.43888", \ - "0.152702, 0.312843, 0.392141, 0.510299, 0.698431, 1.00966, 1.52936", \ + "0.0473085, 0.147759, 0.215975, 0.328113, 0.515694, 0.827564, 1.34729", \ + "0.0853458, 0.192381, 0.260473, 0.372761, 0.56044, 0.872241, 1.39244", \ + "0.112747, 0.237099, 0.307063, 0.419462, 0.606736, 0.91963, 1.43888", \ + "0.152702, 0.312843, 0.392141, 0.510299, 0.69843, 1.00968, 1.52936", \ "0.204192, 0.424579, 0.526073, 0.666729, 0.872456, 1.18946, 1.70757", \ "0.26391, 0.579507, 0.723741, 0.911837, 1.16744, 1.52595, 2.06602", \ "0.332042, 0.788219, 0.994749, 1.26493, 1.61584, 2.08325, 2.7228" \ @@ -21752,39 +21826,39 @@ library (sg13g2_stdcell_slow_1p08V_125C) { index_1 ("0.0186, 0.0966, 0.174, 0.3294, 0.6408, 1.263, 2.5074"); index_2 ("0.001, 0.0234, 0.039, 0.0648, 0.108, 0.18, 0.3"); values ( \ - "0.0392707, 0.178572, 0.275471, 0.435853, 0.704067, 1.15107, 1.89565", \ - "0.051544, 0.180546, 0.275617, 0.435854, 0.704355, 1.15124, 1.89584", \ - "0.0689575, 0.192967, 0.282672, 0.437804, 0.706451, 1.15125, 1.89613", \ - "0.097801, 0.228843, 0.312078, 0.45579, 0.710491, 1.15144, 1.89614", \ - "0.147769, 0.304973, 0.389909, 0.524632, 0.758653, 1.17351, 1.90451", \ + "0.039271, 0.178672, 0.275521, 0.435865, 0.704026, 1.15109, 1.896", \ + "0.051544, 0.180557, 0.275604, 0.436131, 0.704143, 1.1511, 1.89601", \ + "0.0689575, 0.192965, 0.282648, 0.437631, 0.706546, 1.15182, 1.89613", \ + "0.097801, 0.228843, 0.312078, 0.45579, 0.710505, 1.15201, 1.89614", \ + "0.147769, 0.304973, 0.389909, 0.524632, 0.758654, 1.17351, 1.90578", \ "0.224824, 0.436792, 0.536268, 0.681648, 0.906146, 1.28775, 1.96042", \ - "0.346541, 0.655209, 0.786973, 0.964952, 1.22035, 1.60153, 2.23287" \ + "0.346542, 0.655209, 0.786973, 0.964952, 1.22035, 1.60153, 2.23287" \ ); } cell_fall (TIMING_DELAY_7x7ds1) { index_1 ("0.0186, 0.0966, 0.174, 0.3294, 0.6408, 1.263, 2.5074"); index_2 ("0.001, 0.0234, 0.039, 0.0648, 0.108, 0.18, 0.3"); values ( \ - "0.125614, 0.419462, 0.622073, 0.957424, 1.51878, 2.45437, 4.01366", \ - "0.155824, 0.452905, 0.656441, 0.992713, 1.55427, 2.48988, 4.04935", \ - "0.180502, 0.482842, 0.686731, 1.02267, 1.5846, 2.5209, 4.08041", \ - "0.221503, 0.540898, 0.746095, 1.0826, 1.64489, 2.58146, 4.14078", \ - "0.277583, 0.642326, 0.857355, 1.19826, 1.76133, 2.69766, 4.25853", \ - "0.350619, 0.809005, 1.04924, 1.41363, 1.99225, 2.93231, 4.49261", \ - "0.45185, 1.06165, 1.35759, 1.7763, 2.4082, 3.3885, 4.96387" \ + "0.125623, 0.419469, 0.622156, 0.957422, 1.51855, 2.45436, 4.01363", \ + "0.155807, 0.452942, 0.656378, 0.992768, 1.55392, 2.48989, 4.04935", \ + "0.180502, 0.482873, 0.686746, 1.02266, 1.58459, 2.52061, 4.08038", \ + "0.221503, 0.540897, 0.746094, 1.08256, 1.64489, 2.58144, 4.14086", \ + "0.277583, 0.642325, 0.857354, 1.19826, 1.76133, 2.69824, 4.25856", \ + "0.350619, 0.809005, 1.04924, 1.41362, 1.99225, 2.93231, 4.49262", \ + "0.45185, 1.06165, 1.35759, 1.7763, 2.4082, 3.3885, 4.96384" \ ); } fall_transition (TIMING_DELAY_7x7ds1) { index_1 ("0.0186, 0.0966, 0.174, 0.3294, 0.6408, 1.263, 2.5074"); index_2 ("0.001, 0.0234, 0.039, 0.0648, 0.108, 0.18, 0.3"); values ( \ - "0.0844967, 0.466543, 0.732734, 1.17163, 1.90734, 3.1334, 5.17685", \ - "0.0873131, 0.466617, 0.732735, 1.17264, 1.90737, 3.13549, 5.18036", \ - "0.0944064, 0.468196, 0.732736, 1.17303, 1.90807, 3.13628, 5.18037", \ - "0.110595, 0.476638, 0.736638, 1.17697, 1.90808, 3.13629, 5.18166", \ - "0.146732, 0.511761, 0.76271, 1.18652, 1.91151, 3.13659, 5.18167", \ - "0.215417, 0.597916, 0.84176, 1.25109, 1.9515, 3.15232, 5.18168", \ - "0.34055, 0.772438, 1.02183, 1.42256, 2.09966, 3.25076, 5.23378" \ + "0.0844754, 0.466541, 0.732286, 1.17163, 1.90809, 3.1334, 5.18017", \ + "0.0873422, 0.466616, 0.733162, 1.17261, 1.9081, 3.13341, 5.18035", \ + "0.0944063, 0.467634, 0.733163, 1.17301, 1.90811, 3.13475, 5.18036", \ + "0.110595, 0.476636, 0.736638, 1.1732, 1.90812, 3.13476, 5.18154", \ + "0.146732, 0.511761, 0.762709, 1.18665, 1.9115, 3.13477, 5.18155", \ + "0.215417, 0.597915, 0.841759, 1.25108, 1.9515, 3.15232, 5.18434", \ + "0.34055, 0.772438, 1.02183, 1.42256, 2.09966, 3.25039, 5.22977" \ ); } } @@ -21796,38 +21870,38 @@ library (sg13g2_stdcell_slow_1p08V_125C) { index_1 ("0.0186, 0.0966, 0.174, 0.3294, 0.6408, 1.263, 2.5074"); index_2 ("0.001, 0.0234, 0.039, 0.0648, 0.108, 0.18, 0.3"); values ( \ - "0.0483167, 0.151252, 0.21984, 0.33248, 0.520265, 0.83224, 1.35202", \ - "0.0881704, 0.195777, 0.264333, 0.376991, 0.564949, 0.876765, 1.39651", \ - "0.117587, 0.240929, 0.310954, 0.423683, 0.611303, 0.924075, 1.44354", \ + "0.0483176, 0.151224, 0.219864, 0.332445, 0.520261, 0.832292, 1.35186", \ + "0.0881534, 0.195781, 0.264365, 0.376907, 0.564802, 0.876759, 1.39668", \ + "0.117587, 0.240903, 0.311014, 0.423665, 0.611107, 0.924041, 1.44353", \ "0.160742, 0.317779, 0.396696, 0.514719, 0.702947, 1.01436, 1.53372", \ - "0.218008, 0.43203, 0.532166, 0.671999, 0.87729, 1.19388, 1.71196", \ - "0.285916, 0.591253, 0.733314, 0.919278, 1.17322, 1.53129, 2.07134", \ - "0.367544, 0.807244, 1.01003, 1.27693, 1.6246, 2.08984, 2.72958" \ + "0.218008, 0.43203, 0.532166, 0.671999, 0.877294, 1.19388, 1.71193", \ + "0.285916, 0.591253, 0.733314, 0.919278, 1.17322, 1.53129, 2.07126", \ + "0.367544, 0.807244, 1.01003, 1.27693, 1.6246, 2.08984, 2.72934" \ ); } rise_transition (TIMING_DELAY_7x7ds1) { index_1 ("0.0186, 0.0966, 0.174, 0.3294, 0.6408, 1.263, 2.5074"); index_2 ("0.001, 0.0234, 0.039, 0.0648, 0.108, 0.18, 0.3"); values ( \ - "0.0434101, 0.183453, 0.280118, 0.440371, 0.708503, 1.15537, 1.90002", \ - "0.0546537, 0.184939, 0.28033, 0.440689, 0.70872, 1.15538, 1.90003", \ - "0.0715229, 0.196762, 0.286965, 0.442171, 0.710338, 1.15584, 1.90004", \ - "0.100408, 0.232078, 0.315799, 0.459855, 0.714571, 1.15585, 1.90005", \ - "0.14921, 0.308541, 0.393069, 0.528196, 0.762326, 1.17678, 1.90995", \ - "0.227842, 0.440884, 0.538973, 0.68418, 0.909482, 1.29095, 1.96293", \ - "0.350394, 0.656244, 0.787551, 0.968041, 1.22167, 1.60519, 2.2343" \ + "0.043409, 0.183201, 0.280108, 0.440371, 0.708504, 1.15537, 1.89904", \ + "0.0546633, 0.184886, 0.280335, 0.440372, 0.708753, 1.15538, 1.89937", \ + "0.0715229, 0.196752, 0.286942, 0.44204, 0.711078, 1.15585, 1.89968", \ + "0.100408, 0.232077, 0.315796, 0.459855, 0.714571, 1.15586, 1.89969", \ + "0.14921, 0.308541, 0.393069, 0.528196, 0.762296, 1.17677, 1.91012", \ + "0.227842, 0.440884, 0.538973, 0.68418, 0.909483, 1.29095, 1.96293", \ + "0.350394, 0.656244, 0.787551, 0.968042, 1.22167, 1.60517, 2.23445" \ ); } cell_fall (TIMING_DELAY_7x7ds1) { index_1 ("0.0186, 0.0966, 0.174, 0.3294, 0.6408, 1.263, 2.5074"); index_2 ("0.001, 0.0234, 0.039, 0.0648, 0.108, 0.18, 0.3"); values ( \ - "0.131516, 0.425364, 0.628069, 0.963355, 1.52452, 2.46027, 4.01929", \ - "0.162852, 0.459682, 0.663112, 0.999044, 1.56073, 2.49642, 4.05594", \ - "0.18772, 0.488067, 0.691837, 1.02835, 1.58979, 2.5259, 4.08476", \ - "0.228521, 0.541352, 0.746238, 1.08288, 1.64531, 2.58148, 4.14072", \ - "0.284952, 0.631271, 0.844102, 1.18413, 1.74725, 2.68428, 4.24419", \ - "0.358904, 0.777869, 1.01118, 1.37031, 1.9472, 2.88654, 4.4464", \ + "0.131526, 0.425363, 0.628058, 0.963361, 1.52452, 2.46027, 4.01957", \ + "0.162791, 0.459669, 0.66311, 0.999025, 1.56073, 2.49648, 4.05593", \ + "0.187699, 0.488066, 0.691841, 1.02788, 1.58979, 2.52611, 4.08478", \ + "0.228521, 0.541351, 0.746238, 1.08288, 1.6453, 2.58148, 4.14058", \ + "0.284951, 0.631271, 0.844102, 1.18413, 1.74725, 2.68428, 4.24419", \ + "0.358904, 0.777869, 1.01117, 1.37031, 1.9472, 2.88654, 4.44641", \ "0.4497, 1.00362, 1.28159, 1.68503, 2.30644, 3.28123, 4.85366" \ ); } @@ -21835,13 +21909,13 @@ library (sg13g2_stdcell_slow_1p08V_125C) { index_1 ("0.0186, 0.0966, 0.174, 0.3294, 0.6408, 1.263, 2.5074"); index_2 ("0.001, 0.0234, 0.039, 0.0648, 0.108, 0.18, 0.3"); values ( \ - "0.0845026, 0.466578, 0.732277, 1.17173, 1.91005, 3.13338, 5.18323", \ - "0.0861668, 0.466707, 0.732283, 1.17282, 1.91006, 3.13339, 5.18324", \ - "0.0911677, 0.467204, 0.733404, 1.17283, 1.91007, 3.13476, 5.18325", \ - "0.102525, 0.47429, 0.735546, 1.1765, 1.91008, 3.13477, 5.18326", \ - "0.128678, 0.501701, 0.756815, 1.18393, 1.91009, 3.13478, 5.18327", \ - "0.184321, 0.569796, 0.820687, 1.2377, 1.94437, 3.14712, 5.18328", \ - "0.305156, 0.715592, 0.970391, 1.37931, 2.06804, 3.23478, 5.22289" \ + "0.0844991, 0.466577, 0.732273, 1.17173, 1.91005, 3.13338, 5.17683", \ + "0.0861656, 0.466706, 0.732284, 1.17282, 1.91006, 3.13339, 5.18017", \ + "0.0912446, 0.467203, 0.73337, 1.17283, 1.91007, 3.13611, 5.18018", \ + "0.102525, 0.474091, 0.735545, 1.1765, 1.91008, 3.13612, 5.18375", \ + "0.128678, 0.501619, 0.756815, 1.18393, 1.91258, 3.13613, 5.18376", \ + "0.184321, 0.569796, 0.820687, 1.2377, 1.94437, 3.14712, 5.18377", \ + "0.305156, 0.715591, 0.97039, 1.37931, 2.06804, 3.23458, 5.22288" \ ); } } @@ -21851,26 +21925,26 @@ library (sg13g2_stdcell_slow_1p08V_125C) { index_1 ("0.0186, 0.0966, 0.174, 0.3294, 0.6408, 1.263, 2.5074"); index_2 ("0.001, 0.0234, 0.039, 0.0648, 0.108, 0.18, 0.3"); values ( \ - "0.00160005, 0.00173976, 0.00171349, 0.00166576, 0.00157845, 0.00140093, 0.00110517", \ - "0.00136597, 0.00169643, 0.00170209, 0.00170522, 0.00164252, 0.001438, 0.0011164", \ - "0.00132231, 0.00161745, 0.00170402, 0.00163942, 0.00158202, 0.00152251, 0.00118602", \ - "0.00136284, 0.00154262, 0.0015906, 0.00168741, 0.00156258, 0.00147392, 0.00114126", \ - "0.00163906, 0.00165098, 0.00166366, 0.00157334, 0.0016302, 0.00138386, 0.00134013", \ - "0.00240518, 0.0018649, 0.00180565, 0.00175247, 0.00158914, 0.00150346, 0.00113763", \ - "0.00411592, 0.00284268, 0.00257597, 0.00232781, 0.00209783, 0.00178581, 0.00134917" \ + "0.00159985, 0.00174034, 0.00171648, 0.00166772, 0.00157864, 0.00139169, 0.00111838", \ + "0.00136574, 0.00167585, 0.00168215, 0.00169812, 0.00159867, 0.00143663, 0.00111673", \ + "0.00132232, 0.00162069, 0.00165929, 0.0016366, 0.00158202, 0.00142213, 0.00118602", \ + "0.00136302, 0.00154261, 0.0015906, 0.00168751, 0.00156258, 0.00147392, 0.00114141", \ + "0.00163906, 0.00165106, 0.00166364, 0.00157334, 0.0016302, 0.00139032, 0.00133863", \ + "0.00240511, 0.0018649, 0.00180565, 0.00175244, 0.00158914, 0.00150346, 0.00113731", \ + "0.00411592, 0.0028425, 0.00257597, 0.00232781, 0.00209733, 0.00178581, 0.00134923" \ ); } fall_power (POWER_7x7ds1) { index_1 ("0.0186, 0.0966, 0.174, 0.3294, 0.6408, 1.263, 2.5074"); index_2 ("0.001, 0.0234, 0.039, 0.0648, 0.108, 0.18, 0.3"); values ( \ - "0.00375018, 0.00387234, 0.0038543, 0.00379753, 0.00370524, 0.00353337, 0.00334234", \ - "0.00345121, 0.0037298, 0.00376456, 0.00373341, 0.00366032, 0.00353359, 0.0033555", \ - "0.00342431, 0.00365395, 0.00369933, 0.00370196, 0.00363733, 0.00350566, 0.00328623", \ - "0.00349213, 0.00361753, 0.00360976, 0.00374375, 0.00360266, 0.00345736, 0.00332921", \ - "0.00378017, 0.00360586, 0.00362718, 0.00363944, 0.00370851, 0.00344816, 0.00324396", \ - "0.00448329, 0.00399329, 0.003874, 0.00369945, 0.00379477, 0.0035394, 0.00394814", \ - "0.00617137, 0.00505062, 0.00475033, 0.00446001, 0.00402663, 0.00384403, 0.00347235" \ + "0.00375689, 0.00387309, 0.00385347, 0.00379711, 0.00370457, 0.00353405, 0.00339067", \ + "0.00345188, 0.00372522, 0.00376517, 0.00373365, 0.00364393, 0.00353352, 0.00336163", \ + "0.0034243, 0.00365431, 0.0036993, 0.003702, 0.0036535, 0.00350655, 0.00328801", \ + "0.00349209, 0.00361752, 0.00360973, 0.00373253, 0.00358626, 0.00348535, 0.00332874", \ + "0.00378007, 0.00360585, 0.0036272, 0.00359771, 0.00360135, 0.00343464, 0.00323184", \ + "0.00448376, 0.00399343, 0.00385044, 0.00369923, 0.00379477, 0.0035393, 0.0039472", \ + "0.00617053, 0.0050506, 0.0047506, 0.00446225, 0.00402141, 0.00384403, 0.0035133" \ ); } } @@ -21880,26 +21954,26 @@ library (sg13g2_stdcell_slow_1p08V_125C) { index_1 ("0.0186, 0.0966, 0.174, 0.3294, 0.6408, 1.263, 2.5074"); index_2 ("0.001, 0.0234, 0.039, 0.0648, 0.108, 0.18, 0.3"); values ( \ - "0.00184211, 0.00185457, 0.00181428, 0.0017645, 0.00166322, 0.00149826, 0.00121007", \ - "0.00159853, 0.00178382, 0.00181049, 0.00180168, 0.00167247, 0.00153242, 0.00120189", \ - "0.00153347, 0.00174516, 0.00175967, 0.00173199, 0.00164532, 0.00157622, 0.00121795", \ - "0.00154505, 0.00168104, 0.00170005, 0.00175412, 0.00164861, 0.00155628, 0.00122036", \ - "0.00178679, 0.00179483, 0.00177507, 0.00169756, 0.00171763, 0.00146857, 0.0014707", \ - "0.00244213, 0.00200006, 0.00193065, 0.001887, 0.00166909, 0.00159175, 0.00116569", \ - "0.00399383, 0.00298688, 0.00273043, 0.0024424, 0.00223274, 0.00190348, 0.00137584" \ + "0.00184085, 0.00184801, 0.00181405, 0.00176427, 0.00167648, 0.0014776, 0.0012134", \ + "0.00159873, 0.00178823, 0.00181406, 0.00175087, 0.00166059, 0.00153279, 0.00120218", \ + "0.00153328, 0.00174072, 0.00177014, 0.0017295, 0.00165121, 0.00157663, 0.0012539", \ + "0.00154505, 0.00168006, 0.00170005, 0.00175412, 0.00166027, 0.00155617, 0.0012191", \ + "0.00178768, 0.00179491, 0.00177507, 0.00169755, 0.00171763, 0.00146857, 0.00144858", \ + "0.00244296, 0.0019999, 0.00193059, 0.00189267, 0.00166909, 0.00159175, 0.00116579", \ + "0.00399373, 0.00298722, 0.00273043, 0.0024424, 0.00223274, 0.00190348, 0.00137584" \ ); } fall_power (POWER_7x7ds1) { index_1 ("0.0186, 0.0966, 0.174, 0.3294, 0.6408, 1.263, 2.5074"); index_2 ("0.001, 0.0234, 0.039, 0.0648, 0.108, 0.18, 0.3"); values ( \ - "0.00503992, 0.00510721, 0.00507715, 0.00501561, 0.00492087, 0.00475409, 0.00455452", \ - "0.00480046, 0.00499623, 0.00500254, 0.00498093, 0.00491569, 0.0047396, 0.00455625", \ - "0.00473622, 0.00493629, 0.00498417, 0.0049435, 0.00488215, 0.00472543, 0.00456948", \ - "0.00470731, 0.00490589, 0.00489609, 0.00490244, 0.00485585, 0.00470589, 0.00457273", \ - "0.00477588, 0.00481478, 0.00485366, 0.0048814, 0.00480628, 0.00470797, 0.00449162", \ - "0.0051969, 0.00497256, 0.00492765, 0.0048366, 0.00497933, 0.00475592, 0.00450688", \ - "0.00652152, 0.00569411, 0.00549856, 0.00531989, 0.00501169, 0.00494773, 0.00468979" \ + "0.00504028, 0.00510387, 0.00507947, 0.00501585, 0.00493596, 0.00474781, 0.00455526", \ + "0.0048003, 0.00499811, 0.00500248, 0.00498106, 0.00490406, 0.00474383, 0.00455673", \ + "0.00473499, 0.00493629, 0.00498378, 0.00495661, 0.00488328, 0.00474714, 0.00457033", \ + "0.00470729, 0.00490647, 0.00489613, 0.00490245, 0.00485615, 0.00470685, 0.00457526", \ + "0.00477576, 0.00481477, 0.00485367, 0.00488143, 0.00479631, 0.00471238, 0.00449316", \ + "0.00519714, 0.00497247, 0.00492762, 0.00483672, 0.00494781, 0.00475514, 0.0045048", \ + "0.00652151, 0.0056946, 0.00549892, 0.00531533, 0.00501148, 0.0049477, 0.00463062" \ ); } } @@ -21909,26 +21983,26 @@ library (sg13g2_stdcell_slow_1p08V_125C) { index_1 ("0.0186, 0.0966, 0.174, 0.3294, 0.6408, 1.263, 2.5074"); index_2 ("0.001, 0.0234, 0.039, 0.0648, 0.108, 0.18, 0.3"); values ( \ - "0.00208784, 0.00204835, 0.00200948, 0.00195362, 0.00185002, 0.0016871, 0.001379", \ - "0.00185672, 0.00195154, 0.00196075, 0.0019143, 0.00182698, 0.00165326, 0.00139021", \ - "0.00179605, 0.00192159, 0.00191485, 0.00189605, 0.00191, 0.00165118, 0.00139753", \ - "0.00179326, 0.00186847, 0.00187137, 0.00189467, 0.00182774, 0.00164807, 0.00133279", \ - "0.00200346, 0.00199702, 0.00197093, 0.00185267, 0.00192737, 0.00162179, 0.00155843", \ - "0.00264735, 0.0022423, 0.00213979, 0.00208778, 0.00184044, 0.00174981, 0.00129487", \ - "0.00415585, 0.00321551, 0.00293533, 0.00266285, 0.00245443, 0.00207383, 0.00157118" \ + "0.00208847, 0.00204975, 0.00201679, 0.0019563, 0.0018616, 0.0016911, 0.00140161", \ + "0.00185672, 0.00195145, 0.00195695, 0.00192672, 0.00181852, 0.00164598, 0.00139047", \ + "0.00179669, 0.00192044, 0.00191424, 0.00187747, 0.00191429, 0.00169248, 0.00134922", \ + "0.00179325, 0.00186823, 0.00187137, 0.00189468, 0.00181344, 0.00166968, 0.00133279", \ + "0.00200389, 0.00199328, 0.00196992, 0.00185061, 0.00194126, 0.00162179, 0.00158589", \ + "0.00264735, 0.0022423, 0.00213963, 0.00208779, 0.00184044, 0.00174981, 0.00129487", \ + "0.00415586, 0.0032155, 0.00293528, 0.00266313, 0.00245443, 0.00207378, 0.00157118" \ ); } fall_power (POWER_7x7ds1) { index_1 ("0.0186, 0.0966, 0.174, 0.3294, 0.6408, 1.263, 2.5074"); index_2 ("0.001, 0.0234, 0.039, 0.0648, 0.108, 0.18, 0.3"); values ( \ - "0.00615882, 0.00622545, 0.00619717, 0.00613909, 0.00605334, 0.00587936, 0.00568675", \ - "0.00592121, 0.00611518, 0.00612198, 0.00610865, 0.00602581, 0.00588621, 0.00569909", \ - "0.00585219, 0.00608205, 0.00606924, 0.00606943, 0.00600021, 0.00589034, 0.0056386", \ - "0.00581168, 0.0059946, 0.0060149, 0.00607798, 0.00596022, 0.00581725, 0.00569604", \ - "0.00582323, 0.00588926, 0.00596217, 0.00601131, 0.00618478, 0.00582504, 0.00562641", \ - "0.00607254, 0.00600946, 0.00599931, 0.00591942, 0.00606043, 0.00583012, 0.00563445", \ - "0.00716543, 0.0065405, 0.00641217, 0.00632778, 0.00606398, 0.00603241, 0.00579971" \ + "0.00615796, 0.00622552, 0.00619462, 0.00613907, 0.00605461, 0.00587878, 0.00573516", \ + "0.00592139, 0.00611629, 0.00612871, 0.00611056, 0.0060245, 0.00586293, 0.00569957", \ + "0.00585168, 0.00608456, 0.00606883, 0.00606976, 0.00599986, 0.00586649, 0.00563943", \ + "0.00581172, 0.00600314, 0.0060149, 0.0060168, 0.00596029, 0.00581667, 0.00567521", \ + "0.00582265, 0.00588926, 0.00596218, 0.00598956, 0.00592755, 0.00580757, 0.00564627", \ + "0.00607221, 0.00600947, 0.00599905, 0.00593594, 0.00606044, 0.00583007, 0.00571519", \ + "0.00716519, 0.00654051, 0.00641213, 0.00632785, 0.00606399, 0.00600168, 0.00573368" \ ); } } @@ -21938,26 +22012,26 @@ library (sg13g2_stdcell_slow_1p08V_125C) { index_1 ("0.0186, 0.0966, 0.174, 0.3294, 0.6408, 1.263, 2.5074"); index_2 ("0.001, 0.0234, 0.039, 0.0648, 0.108, 0.18, 0.3"); values ( \ - "0.00228818, 0.00224036, 0.00219103, 0.00213587, 0.00205001, 0.00186375, 0.00161718", \ - "0.00209836, 0.00212686, 0.00216239, 0.00209029, 0.00199707, 0.00179861, 0.00158761", \ - "0.00205091, 0.0021135, 0.00210006, 0.00207793, 0.00203651, 0.00183574, 0.00151822", \ - "0.00205391, 0.00207154, 0.00206468, 0.00211047, 0.00197828, 0.00177952, 0.00148917", \ - "0.00225198, 0.00222897, 0.00216601, 0.00204606, 0.00208902, 0.00180637, 0.00176857", \ - "0.00286772, 0.00249558, 0.00237712, 0.00229761, 0.00203569, 0.00194876, 0.00148071", \ - "0.00436616, 0.0034377, 0.00315799, 0.00290442, 0.00263932, 0.00230884, 0.00181899" \ + "0.00228867, 0.00222735, 0.0021925, 0.00213352, 0.00205106, 0.00186182, 0.00159485", \ + "0.00210016, 0.00212817, 0.00218082, 0.00206793, 0.00198982, 0.00179834, 0.00155665", \ + "0.00205121, 0.00211155, 0.00209767, 0.00208085, 0.00209319, 0.00183434, 0.00151805", \ + "0.00205392, 0.00207129, 0.00206456, 0.00211048, 0.00197838, 0.00177952, 0.00148907", \ + "0.00225314, 0.00222901, 0.00217746, 0.00204606, 0.00211683, 0.00178512, 0.00177861", \ + "0.00286791, 0.00249771, 0.00237714, 0.00229761, 0.00203584, 0.00194876, 0.00147508", \ + "0.00436616, 0.0034377, 0.00315786, 0.00290451, 0.00264023, 0.00229826, 0.00181726" \ ); } fall_power (POWER_7x7ds1) { index_1 ("0.0186, 0.0966, 0.174, 0.3294, 0.6408, 1.263, 2.5074"); index_2 ("0.001, 0.0234, 0.039, 0.0648, 0.108, 0.18, 0.3"); values ( \ - "0.00722593, 0.0072947, 0.00725847, 0.00721066, 0.0071441, 0.00695872, 0.00681589", \ - "0.00699271, 0.00718498, 0.00718595, 0.0071747, 0.00710295, 0.00692835, 0.00679575", \ - "0.00692447, 0.00715098, 0.00716297, 0.00714707, 0.00706908, 0.00693768, 0.00678263", \ - "0.00687417, 0.00706792, 0.00707528, 0.00713882, 0.00705557, 0.00688198, 0.00677205", \ - "0.00685803, 0.00696617, 0.00702306, 0.00707191, 0.00718524, 0.00684713, 0.00668793", \ - "0.00702491, 0.00702071, 0.00702784, 0.0069599, 0.00705575, 0.00684747, 0.0066975", \ - "0.00789609, 0.00745586, 0.00737038, 0.00729244, 0.00705896, 0.00705582, 0.00677456" \ + "0.00722686, 0.00729342, 0.00726233, 0.00721088, 0.00714347, 0.00695913, 0.00675843", \ + "0.00699088, 0.00718482, 0.00718984, 0.00717478, 0.00710334, 0.00692869, 0.00679615", \ + "0.00691689, 0.00715133, 0.0071633, 0.00713318, 0.007069, 0.00695349, 0.00678224", \ + "0.0068737, 0.00705741, 0.00707518, 0.0071388, 0.00705553, 0.006882, 0.0068011", \ + "0.0068586, 0.00695468, 0.00702306, 0.00707171, 0.00714222, 0.00684708, 0.00668793", \ + "0.00702481, 0.00702071, 0.00702788, 0.00695977, 0.00705575, 0.00684752, 0.00669762", \ + "0.00789701, 0.00745579, 0.00737038, 0.00729221, 0.00706239, 0.00707114, 0.00677461" \ ); } } @@ -21965,38 +22039,38 @@ library (sg13g2_stdcell_slow_1p08V_125C) { pin (A) { direction : "input"; max_transition : 2.5074; - capacitance : 0.0027103; - rise_capacitance : 0.00275752; - rise_capacitance_range (0.00275752, 0.00275752); + capacitance : 0.00271028; + rise_capacitance : 0.00275747; + rise_capacitance_range (0.0024724, 0.00291941); fall_capacitance : 0.00266309; - fall_capacitance_range (0.00266309, 0.00266309); + fall_capacitance_range (0.00229329, 0.00300513); } pin (B) { direction : "input"; max_transition : 2.5074; - capacitance : 0.00282323; - rise_capacitance : 0.00290573; - rise_capacitance_range (0.00290573, 0.00290573); + capacitance : 0.00282328; + rise_capacitance : 0.00290583; + rise_capacitance_range (0.00255929, 0.00324953); fall_capacitance : 0.00274074; - fall_capacitance_range (0.00274074, 0.00274074); + fall_capacitance_range (0.00246378, 0.00301706); } pin (C) { direction : "input"; max_transition : 2.5074; - capacitance : 0.00284012; - rise_capacitance : 0.00292993; - rise_capacitance_range (0.00292993, 0.00292993); - fall_capacitance : 0.00275032; - fall_capacitance_range (0.00275032, 0.00275032); + capacitance : 0.00284003; + rise_capacitance : 0.00292978; + rise_capacitance_range (0.00258775, 0.00324675); + fall_capacitance : 0.00275029; + fall_capacitance_range (0.00254554, 0.00297839); } pin (D) { direction : "input"; max_transition : 2.5074; - capacitance : 0.00280717; + capacitance : 0.00280719; rise_capacitance : 0.00290168; - rise_capacitance_range (0.00290168, 0.00290168); - fall_capacitance : 0.00271265; - fall_capacitance_range (0.00271265, 0.00271265); + rise_capacitance_range (0.00257043, 0.00317397); + fall_capacitance : 0.00271269; + fall_capacitance_range (0.00258602, 0.0028953); } } cell (sg13g2_nor2_1) { @@ -22202,18 +22276,18 @@ library (sg13g2_stdcell_slow_1p08V_125C) { max_transition : 2.5074; capacitance : 0.00283987; rise_capacitance : 0.00285283; - rise_capacitance_range (0.00285283, 0.00285283); + rise_capacitance_range (0.00261555, 0.00308099); fall_capacitance : 0.00282691; - fall_capacitance_range (0.00282691, 0.00282691); + fall_capacitance_range (0.00248165, 0.00320937); } pin (B) { direction : "input"; max_transition : 2.5074; capacitance : 0.00275839; rise_capacitance : 0.00282514; - rise_capacitance_range (0.00282514, 0.00282514); + rise_capacitance_range (0.00228539, 0.00316391); fall_capacitance : 0.00269164; - fall_capacitance_range (0.00269164, 0.00269164); + fall_capacitance_range (0.00239833, 0.00293221); } } cell (sg13g2_nor2_2) { @@ -22419,18 +22493,18 @@ library (sg13g2_stdcell_slow_1p08V_125C) { max_transition : 2.5074; capacitance : 0.0054019; rise_capacitance : 0.00542901; - rise_capacitance_range (0.00542901, 0.00542901); + rise_capacitance_range (0.00493126, 0.00589464); fall_capacitance : 0.00537479; - fall_capacitance_range (0.00537479, 0.00537479); + fall_capacitance_range (0.00473051, 0.00615734); } pin (B) { direction : "input"; max_transition : 2.5074; capacitance : 0.00527112; rise_capacitance : 0.00540165; - rise_capacitance_range (0.00540165, 0.00540165); + rise_capacitance_range (0.00418156, 0.00615371); fall_capacitance : 0.00514058; - fall_capacitance_range (0.00514058, 0.00514058); + fall_capacitance_range (0.0045013, 0.00567365); } } cell (sg13g2_nor2b_1) { @@ -22636,18 +22710,18 @@ library (sg13g2_stdcell_slow_1p08V_125C) { max_transition : 2.5074; capacitance : 0.0027628; rise_capacitance : 0.00282972; - rise_capacitance_range (0.00282972, 0.00282972); + rise_capacitance_range (0.00228378, 0.00316939); fall_capacitance : 0.00269589; - fall_capacitance_range (0.00269589, 0.00269589); + fall_capacitance_range (0.0024012, 0.00293688); } pin (B_N) { direction : "input"; max_transition : 2.5074; capacitance : 0.00211773; rise_capacitance : 0.00215244; - rise_capacitance_range (0.00215244, 0.00215244); + rise_capacitance_range (0.00196067, 0.00229315); fall_capacitance : 0.00208302; - fall_capacitance_range (0.00208302, 0.00208302); + fall_capacitance_range (0.00191915, 0.00223302); internal_power () { when : "A"; rise_power (passive_POWER_7x1ds1) { @@ -22882,18 +22956,18 @@ library (sg13g2_stdcell_slow_1p08V_125C) { max_transition : 2.5074; capacitance : 0.00535429; rise_capacitance : 0.00549727; - rise_capacitance_range (0.00549727, 0.00549727); + rise_capacitance_range (0.00424759, 0.00620778); fall_capacitance : 0.00521132; - fall_capacitance_range (0.00521132, 0.00521132); + fall_capacitance_range (0.00456824, 0.0057597); } pin (B_N) { direction : "input"; max_transition : 2.5074; capacitance : 0.00251403; rise_capacitance : 0.00256289; - rise_capacitance_range (0.00256289, 0.00256289); + rise_capacitance_range (0.00237898, 0.0027097); fall_capacitance : 0.00246517; - fall_capacitance_range (0.00246517, 0.00246517); + fall_capacitance_range (0.00231363, 0.00261631); internal_power () { when : "A"; rise_power (passive_POWER_7x1ds1) { @@ -23226,27 +23300,27 @@ library (sg13g2_stdcell_slow_1p08V_125C) { max_transition : 2.5074; capacitance : 0.00280718; rise_capacitance : 0.0028091; - rise_capacitance_range (0.0028091, 0.0028091); + rise_capacitance_range (0.00263624, 0.00301834); fall_capacitance : 0.00280526; - fall_capacitance_range (0.00280526, 0.00280526); + fall_capacitance_range (0.00249435, 0.00315358); } pin (B) { direction : "input"; max_transition : 2.5074; capacitance : 0.00282615; rise_capacitance : 0.00284362; - rise_capacitance_range (0.00284362, 0.00284362); + rise_capacitance_range (0.00249474, 0.00313886); fall_capacitance : 0.00280867; - fall_capacitance_range (0.00280867, 0.00280867); + fall_capacitance_range (0.00245644, 0.00318681); } pin (C) { direction : "input"; max_transition : 2.5074; capacitance : 0.00273757; rise_capacitance : 0.00280318; - rise_capacitance_range (0.00280318, 0.00280318); + rise_capacitance_range (0.00228986, 0.0031901); fall_capacitance : 0.00267197; - fall_capacitance_range (0.00267197, 0.00267197); + fall_capacitance_range (0.0023954, 0.00285214); } } cell (sg13g2_nor3_2) { @@ -23550,27 +23624,27 @@ library (sg13g2_stdcell_slow_1p08V_125C) { max_transition : 2.5074; capacitance : 0.00535751; rise_capacitance : 0.00537801; - rise_capacitance_range (0.00537801, 0.00537801); + rise_capacitance_range (0.00500807, 0.00578941); fall_capacitance : 0.00533702; - fall_capacitance_range (0.00533702, 0.00533702); + fall_capacitance_range (0.00468269, 0.00603301); } pin (B) { direction : "input"; max_transition : 2.5074; capacitance : 0.00536983; rise_capacitance : 0.00541885; - rise_capacitance_range (0.00541885, 0.00541885); + rise_capacitance_range (0.00468197, 0.00600669); fall_capacitance : 0.00532082; - fall_capacitance_range (0.00532082, 0.00532082); + fall_capacitance_range (0.00462166, 0.00608924); } pin (C) { direction : "input"; max_transition : 2.5074; capacitance : 0.00525564; rise_capacitance : 0.00540159; - rise_capacitance_range (0.00540159, 0.00540159); + rise_capacitance_range (0.0042324, 0.00620587); fall_capacitance : 0.0051097; - fall_capacitance_range (0.0051097, 0.0051097); + fall_capacitance_range (0.00450809, 0.00551334); } } cell (sg13g2_nor4_1) { @@ -23996,48 +24070,48 @@ library (sg13g2_stdcell_slow_1p08V_125C) { max_transition : 2.5074; capacitance : 0.00278429; rise_capacitance : 0.00279501; - rise_capacitance_range (0.00279501, 0.00279501); + rise_capacitance_range (0.00264916, 0.00297576); fall_capacitance : 0.00277357; - fall_capacitance_range (0.00277357, 0.00277357); + fall_capacitance_range (0.00247062, 0.00307781); } pin (B) { direction : "input"; max_transition : 2.5074; capacitance : 0.00280837; rise_capacitance : 0.00282963; - rise_capacitance_range (0.00282963, 0.00282963); + rise_capacitance_range (0.0025449, 0.00308515); fall_capacitance : 0.00278711; - fall_capacitance_range (0.00278711, 0.00278711); + fall_capacitance_range (0.00244401, 0.00313795); } pin (C) { direction : "input"; max_transition : 2.5074; capacitance : 0.00278351; rise_capacitance : 0.00281774; - rise_capacitance_range (0.00281774, 0.00281774); + rise_capacitance_range (0.00245385, 0.00313452); fall_capacitance : 0.00274927; - fall_capacitance_range (0.00274927, 0.00274927); + fall_capacitance_range (0.00240417, 0.003123); } pin (D) { direction : "input"; max_transition : 2.5074; capacitance : 0.00267719; rise_capacitance : 0.00275373; - rise_capacitance_range (0.00275373, 0.00275373); + rise_capacitance_range (0.00228302, 0.00314132); fall_capacitance : 0.00260066; - fall_capacitance_range (0.00260066, 0.00260066); + fall_capacitance_range (0.00234537, 0.00275315); } } cell (sg13g2_nor4_2) { area : 21.7728; cell_footprint : "nor4"; - cell_leakage_power : 895.974; + cell_leakage_power : 895.975; leakage_power () { - value : 1081.27; + value : 1081.28; when : "!A&!B&!C&!D&Y"; } leakage_power () { - value : 992.664; + value : 992.665; when : "!A&!B&!C&D&!Y"; } leakage_power () { @@ -24053,15 +24127,15 @@ library (sg13g2_stdcell_slow_1p08V_125C) { when : "!A&B&!C&!D&!Y"; } leakage_power () { - value : 534.612; + value : 534.613; when : "!A&B&!C&D&!Y"; } leakage_power () { - value : 913.623; + value : 913.624; when : "!A&B&C&!D&!Y"; } leakage_power () { - value : 448.136; + value : 448.137; when : "!A&B&C&D&!Y"; } leakage_power () { @@ -24069,15 +24143,15 @@ library (sg13g2_stdcell_slow_1p08V_125C) { when : "A&!B&!C&!D&!Y"; } leakage_power () { - value : 541.6; + value : 541.601; when : "A&!B&!C&D&!Y"; } leakage_power () { - value : 919.761; + value : 919.762; when : "A&!B&C&!D&!Y"; } leakage_power () { - value : 447.491; + value : 447.492; when : "A&!B&C&D&!Y"; } leakage_power () { @@ -24085,15 +24159,15 @@ library (sg13g2_stdcell_slow_1p08V_125C) { when : "A&B&!C&!D&!Y"; } leakage_power () { - value : 462.124; + value : 462.125; when : "A&B&!C&D&!Y"; } leakage_power () { - value : 842.646; + value : 842.647; when : "A&B&C&!D&!Y"; } leakage_power () { - value : 418.344; + value : 418.345; when : "A&B&C&D&!Y"; } pin (Y) { @@ -24109,52 +24183,52 @@ library (sg13g2_stdcell_slow_1p08V_125C) { index_1 ("0.0186, 0.0966, 0.174, 0.3294, 0.6408, 1.263, 2.5074"); index_2 ("0.001, 0.0468, 0.078, 0.1296, 0.216, 0.36, 0.6"); values ( \ - "0.168655, 0.599221, 0.888773, 1.36759, 2.16941, 3.5046, 5.73118", \ - "0.198661, 0.630532, 0.921103, 1.40048, 2.20255, 3.53832, 5.76578", \ - "0.223437, 0.656215, 0.948121, 1.42686, 2.2295, 3.56582, 5.7928", \ - "0.261682, 0.701761, 0.992673, 1.47284, 2.27578, 3.61228, 5.84106", \ - "0.310588, 0.778095, 1.07143, 1.55179, 2.35545, 3.69303, 5.9198", \ - "0.365208, 0.897179, 1.20567, 1.69581, 2.50049, 3.83849, 6.06646", \ - "0.411259, 1.07756, 1.42322, 1.95091, 2.78557, 4.13446, 6.36294" \ + "0.168764, 0.599153, 0.888827, 1.36757, 2.16933, 3.50492, 5.73087", \ + "0.198678, 0.63047, 0.921063, 1.40064, 2.20245, 3.53823, 5.7654", \ + "0.223432, 0.656064, 0.948086, 1.42673, 2.22919, 3.56625, 5.79261", \ + "0.261674, 0.701734, 0.992636, 1.47316, 2.27571, 3.61213, 5.83909", \ + "0.310578, 0.778073, 1.0714, 1.55174, 2.35538, 3.69291, 5.91961", \ + "0.365197, 0.897155, 1.20574, 1.6957, 2.50057, 3.83835, 6.06604", \ + "0.411246, 1.07753, 1.42319, 1.95085, 2.78549, 4.13432, 6.36269" \ ); } rise_transition (TIMING_DELAY_7x7ds1) { index_1 ("0.0186, 0.0966, 0.174, 0.3294, 0.6408, 1.263, 2.5074"); index_2 ("0.001, 0.0468, 0.078, 0.1296, 0.216, 0.36, 0.6"); values ( \ - "0.109554, 0.684266, 1.07425, 1.72076, 2.80224, 4.60182, 7.60356", \ - "0.110008, 0.684267, 1.07504, 1.72077, 2.80225, 4.60183, 7.60753", \ - "0.11368, 0.684317, 1.07592, 1.72078, 2.80226, 4.60288, 7.60754", \ - "0.123931, 0.685865, 1.07693, 1.72079, 2.80227, 4.60407, 7.60793", \ - "0.145289, 0.702019, 1.08433, 1.7223, 2.80353, 4.60455, 7.60794", \ - "0.195968, 0.757294, 1.12826, 1.74892, 2.81074, 4.60456, 7.60795", \ - "0.321142, 0.883891, 1.25409, 1.86082, 2.88882, 4.63979, 7.612" \ + "0.109523, 0.684236, 1.0749, 1.7207, 2.8021, 4.60396, 7.60232", \ + "0.109992, 0.684237, 1.075, 1.72071, 2.80211, 4.60397, 7.60352", \ + "0.113693, 0.684238, 1.07589, 1.72072, 2.80212, 4.60689, 7.60447", \ + "0.123925, 0.685838, 1.07653, 1.72073, 2.80213, 4.6069, 7.60709", \ + "0.145284, 0.701991, 1.0843, 1.72233, 2.80346, 4.60691, 7.60766", \ + "0.195961, 0.757267, 1.12961, 1.7488, 2.81051, 4.60692, 7.60767", \ + "0.321133, 0.883868, 1.25406, 1.86036, 2.88844, 4.64008, 7.61556" \ ); } cell_fall (TIMING_DELAY_7x7ds1) { index_1 ("0.0186, 0.0966, 0.174, 0.3294, 0.6408, 1.263, 2.5074"); index_2 ("0.001, 0.0468, 0.078, 0.1296, 0.216, 0.36, 0.6"); values ( \ - "0.0388479, 0.132948, 0.192842, 0.289231, 0.449842, 0.716115, 1.15923", \ - "0.0807356, 0.183164, 0.242499, 0.339042, 0.499534, 0.766331, 1.20898", \ - "0.109653, 0.229146, 0.291672, 0.389307, 0.549681, 0.815848, 1.25943", \ - "0.15335, 0.307011, 0.379814, 0.486466, 0.65101, 0.917292, 1.35973", \ - "0.211824, 0.42289, 0.517875, 0.648212, 0.837578, 1.1161, 1.56021", \ - "0.291232, 0.590595, 0.722067, 0.896493, 1.13535, 1.47006, 1.9532", \ - "0.392952, 0.815134, 1.008, 1.25966, 1.58557, 2.02346, 2.61693" \ + "0.0388364, 0.132918, 0.192836, 0.289195, 0.449789, 0.716047, 1.15881", \ + "0.0807546, 0.183159, 0.242446, 0.33905, 0.49957, 0.766244, 1.20904", \ + "0.109623, 0.229121, 0.291636, 0.389312, 0.549693, 0.815736, 1.25923", \ + "0.153344, 0.306996, 0.379791, 0.486469, 0.651047, 0.91722, 1.35962", \ + "0.211816, 0.422873, 0.517852, 0.648185, 0.8375, 1.11592, 1.56002", \ + "0.291223, 0.590576, 0.722042, 0.896458, 1.13529, 1.46998, 1.95322", \ + "0.393439, 0.815111, 1.00798, 1.25962, 1.58551, 2.02346, 2.6169" \ ); } fall_transition (TIMING_DELAY_7x7ds1) { index_1 ("0.0186, 0.0966, 0.174, 0.3294, 0.6408, 1.263, 2.5074"); index_2 ("0.001, 0.0468, 0.078, 0.1296, 0.216, 0.36, 0.6"); values ( \ - "0.0323383, 0.149774, 0.228082, 0.355753, 0.570415, 0.927229, 1.52351", \ - "0.0481448, 0.154071, 0.22901, 0.356618, 0.570416, 0.928071, 1.52352", \ - "0.063056, 0.170232, 0.240298, 0.361222, 0.571351, 0.928072, 1.52384", \ - "0.09041, 0.208474, 0.276728, 0.389139, 0.587473, 0.9324, 1.52385", \ - "0.136607, 0.284038, 0.355983, 0.470486, 0.654039, 0.974471, 1.53607", \ - "0.210579, 0.413187, 0.501347, 0.626336, 0.821042, 1.12665, 1.64549", \ - "0.33467, 0.622295, 0.746959, 0.90315, 1.12798, 1.45342, 1.97076" \ + "0.0323264, 0.150208, 0.228056, 0.355715, 0.570354, 0.927198, 1.52211", \ + "0.0481264, 0.154112, 0.228987, 0.356148, 0.570355, 0.927972, 1.52237", \ + "0.063071, 0.170233, 0.240276, 0.361184, 0.571239, 0.927973, 1.52368", \ + "0.0905815, 0.208468, 0.276716, 0.389277, 0.587515, 0.932302, 1.52369", \ + "0.136602, 0.283379, 0.35596, 0.470455, 0.654048, 0.974081, 1.53656", \ + "0.210572, 0.413171, 0.501289, 0.626304, 0.819158, 1.12655, 1.64562", \ + "0.334279, 0.622276, 0.744483, 0.903456, 1.12792, 1.45377, 1.97053" \ ); } } @@ -24166,52 +24240,52 @@ library (sg13g2_stdcell_slow_1p08V_125C) { index_1 ("0.0186, 0.0966, 0.174, 0.3294, 0.6408, 1.263, 2.5074"); index_2 ("0.001, 0.0468, 0.078, 0.1296, 0.216, 0.36, 0.6"); values ( \ - "0.162388, 0.592908, 0.882616, 1.36137, 2.16278, 3.49876, 5.72529", \ - "0.190939, 0.622737, 0.913493, 1.3928, 2.19475, 3.53127, 5.75719", \ - "0.215683, 0.649501, 0.94015, 1.42053, 2.22268, 3.55954, 5.78525", \ - "0.253735, 0.69871, 0.989706, 1.46977, 2.27275, 3.60925, 5.8381", \ - "0.30195, 0.78638, 1.08058, 1.56084, 2.36466, 3.70229, 5.92925", \ - "0.355441, 0.929926, 1.24377, 1.73637, 2.54218, 3.87913, 6.10735", \ - "0.412968, 1.15172, 1.51475, 2.05444, 2.89468, 4.24618, 6.47487" \ + "0.162377, 0.592843, 0.882581, 1.36133, 2.16272, 3.49864, 5.7251", \ + "0.190947, 0.622637, 0.91348, 1.39278, 2.19465, 3.53117, 5.758", \ + "0.215679, 0.649477, 0.940161, 1.41993, 2.22257, 3.55942, 5.785", \ + "0.253727, 0.698678, 0.989571, 1.46974, 2.27267, 3.60913, 5.83792", \ + "0.301942, 0.78636, 1.08055, 1.56082, 2.36461, 3.70228, 5.92909", \ + "0.355432, 0.929905, 1.24371, 1.73624, 2.54213, 3.8795, 6.10707", \ + "0.412956, 1.1517, 1.51472, 2.05442, 2.89461, 4.24601, 6.47467" \ ); } rise_transition (TIMING_DELAY_7x7ds1) { index_1 ("0.0186, 0.0966, 0.174, 0.3294, 0.6408, 1.263, 2.5074"); index_2 ("0.001, 0.0468, 0.078, 0.1296, 0.216, 0.36, 0.6"); values ( \ - "0.109487, 0.684338, 1.07494, 1.72075, 2.80045, 4.60409, 7.60749", \ - "0.110527, 0.684339, 1.07503, 1.72076, 2.80192, 4.6041, 7.6075", \ - "0.116422, 0.685066, 1.07504, 1.72091, 2.80393, 4.60696, 7.60751", \ - "0.130919, 0.6868, 1.0762, 1.72092, 2.80394, 4.60697, 7.60807", \ - "0.161892, 0.708364, 1.08572, 1.72356, 2.80395, 4.60698, 7.60808", \ - "0.230016, 0.780535, 1.1439, 1.75663, 2.81297, 4.6092, 7.60809", \ - "0.37225, 0.940479, 1.30352, 1.8937, 2.90738, 4.64866, 7.62439" \ + "0.109484, 0.683846, 1.07491, 1.7207, 2.80036, 4.60394, 7.60725", \ + "0.110499, 0.68412, 1.075, 1.72071, 2.80182, 4.60395, 7.60726", \ + "0.11641, 0.685046, 1.07501, 1.72072, 2.80384, 4.6068, 7.60727", \ + "0.130912, 0.686823, 1.08084, 1.72073, 2.80385, 4.60681, 7.60782", \ + "0.161885, 0.708341, 1.08629, 1.72351, 2.80386, 4.60682, 7.60783", \ + "0.230009, 0.780511, 1.14303, 1.75661, 2.81247, 4.60752, 7.60784", \ + "0.372242, 0.940455, 1.30348, 1.89366, 2.90724, 4.64843, 7.62418" \ ); } cell_fall (TIMING_DELAY_7x7ds1) { index_1 ("0.0186, 0.0966, 0.174, 0.3294, 0.6408, 1.263, 2.5074"); index_2 ("0.001, 0.0468, 0.078, 0.1296, 0.216, 0.36, 0.6"); values ( \ - "0.0401848, 0.130934, 0.189531, 0.285583, 0.445723, 0.711824, 1.15517", \ - "0.0801234, 0.181077, 0.239812, 0.335753, 0.495721, 0.762308, 1.20511", \ - "0.107021, 0.226441, 0.288646, 0.385842, 0.545828, 0.811923, 1.25556", \ - "0.147122, 0.302911, 0.375959, 0.482573, 0.647069, 0.913355, 1.35581", \ - "0.199879, 0.416165, 0.511981, 0.643067, 0.832926, 1.11198, 1.55635", \ - "0.269904, 0.578929, 0.712965, 0.888727, 1.12959, 1.4652, 1.94872", \ - "0.355655, 0.794889, 0.991102, 1.24706, 1.57609, 2.01609, 2.61147" \ + "0.0401917, 0.13094, 0.189534, 0.285582, 0.445709, 0.711793, 1.15515", \ + "0.0800709, 0.181075, 0.239739, 0.335609, 0.495683, 0.76227, 1.20525", \ + "0.107047, 0.226431, 0.288647, 0.385899, 0.545786, 0.811834, 1.25548", \ + "0.14712, 0.30291, 0.375956, 0.48257, 0.647027, 0.913346, 1.3558", \ + "0.199877, 0.416163, 0.511979, 0.643064, 0.83291, 1.11199, 1.55634", \ + "0.269902, 0.578925, 0.712961, 0.888721, 1.12958, 1.46521, 1.94869", \ + "0.355653, 0.794886, 0.991094, 1.24705, 1.57608, 2.01608, 2.61146" \ ); } fall_transition (TIMING_DELAY_7x7ds1) { index_1 ("0.0186, 0.0966, 0.174, 0.3294, 0.6408, 1.263, 2.5074"); index_2 ("0.001, 0.0468, 0.078, 0.1296, 0.216, 0.36, 0.6"); values ( \ - "0.030137, 0.144715, 0.222417, 0.350683, 0.565603, 0.923027, 1.51875", \ - "0.0444553, 0.149629, 0.224032, 0.35089, 0.565604, 0.923375, 1.51956", \ - "0.0591324, 0.165931, 0.235819, 0.356814, 0.566469, 0.923376, 1.52028", \ - "0.0860071, 0.204334, 0.272431, 0.385225, 0.583089, 0.927438, 1.52029", \ - "0.131058, 0.280323, 0.351881, 0.46739, 0.650352, 0.970149, 1.53351", \ - "0.204424, 0.409855, 0.497575, 0.621718, 0.81695, 1.12437, 1.6427", \ - "0.326155, 0.619183, 0.74132, 0.899672, 1.12653, 1.45215, 1.9681" \ + "0.0301521, 0.144713, 0.222352, 0.350677, 0.565596, 0.923017, 1.51874", \ + "0.0446359, 0.14963, 0.224038, 0.35085, 0.565597, 0.923526, 1.51898", \ + "0.0591113, 0.165903, 0.235773, 0.356798, 0.566698, 0.923527, 1.52026", \ + "0.0860062, 0.204332, 0.272428, 0.385439, 0.583166, 0.927592, 1.52027", \ + "0.131057, 0.280322, 0.351879, 0.467387, 0.650458, 0.970379, 1.53349", \ + "0.204423, 0.409854, 0.497894, 0.621717, 0.816864, 1.12361, 1.64272", \ + "0.326152, 0.61918, 0.74131, 0.899669, 1.12652, 1.45214, 1.96785" \ ); } } @@ -24223,52 +24297,52 @@ library (sg13g2_stdcell_slow_1p08V_125C) { index_1 ("0.0186, 0.0966, 0.174, 0.3294, 0.6408, 1.263, 2.5074"); index_2 ("0.001, 0.0468, 0.078, 0.1296, 0.216, 0.36, 0.6"); values ( \ - "0.140686, 0.571339, 0.861018, 1.33978, 2.14118, 3.47707, 5.70308", \ - "0.166453, 0.59838, 0.88893, 1.36845, 2.17072, 3.50681, 5.73291", \ - "0.1902, 0.62636, 0.917081, 1.39681, 2.19987, 3.53543, 5.76325", \ - "0.227165, 0.681818, 0.972748, 1.45328, 2.25693, 3.59235, 5.82205", \ - "0.274228, 0.785571, 1.08136, 1.56217, 2.36575, 3.70347, 5.9304", \ - "0.329345, 0.957485, 1.27917, 1.77593, 2.58306, 3.92002, 6.14786", \ - "0.413418, 1.22082, 1.60476, 2.16262, 3.01368, 4.36907, 6.59887" \ + "0.140669, 0.571317, 0.860997, 1.33961, 2.14111, 3.47695, 5.70253", \ + "0.16646, 0.598359, 0.888901, 1.3684, 2.17065, 3.50672, 5.73441", \ + "0.190195, 0.626341, 0.917077, 1.39679, 2.19981, 3.53531, 5.76306", \ + "0.22716, 0.681799, 0.972673, 1.45323, 2.25686, 3.59229, 5.82185", \ + "0.274221, 0.785552, 1.08132, 1.56213, 2.36491, 3.70207, 5.93025", \ + "0.329337, 0.957466, 1.27915, 1.7758, 2.58304, 3.9195, 6.14788", \ + "0.413408, 1.22035, 1.60473, 2.16224, 3.01387, 4.36853, 6.59872" \ ); } rise_transition (TIMING_DELAY_7x7ds1) { index_1 ("0.0186, 0.0966, 0.174, 0.3294, 0.6408, 1.263, 2.5074"); index_2 ("0.001, 0.0468, 0.078, 0.1296, 0.216, 0.36, 0.6"); values ( \ - "0.109496, 0.684218, 1.07481, 1.72082, 2.80203, 4.6041, 7.60491", \ - "0.111756, 0.684219, 1.07482, 1.72083, 2.80221, 4.60411, 7.60492", \ - "0.12092, 0.687072, 1.0749, 1.72084, 2.80222, 4.60412, 7.60588", \ - "0.14116, 0.68847, 1.07929, 1.72085, 2.80281, 4.60413, 7.61285", \ - "0.183198, 0.717771, 1.09057, 1.72443, 2.80341, 4.60433, 7.61286", \ - "0.2613, 0.812741, 1.16434, 1.76817, 2.81739, 4.60852, 7.61287", \ - "0.39288, 1.00838, 1.36819, 1.94186, 2.93502, 4.66052, 7.62794" \ + "0.109566, 0.684194, 1.07477, 1.7207, 2.80194, 4.60395, 7.60734", \ + "0.111751, 0.684195, 1.07478, 1.72071, 2.80211, 4.60396, 7.60796", \ + "0.120914, 0.687046, 1.07486, 1.72072, 2.80212, 4.60397, 7.60797", \ + "0.141154, 0.688445, 1.07929, 1.72073, 2.80272, 4.60398, 7.61261", \ + "0.183192, 0.717751, 1.09042, 1.72437, 2.80273, 4.60399, 7.61262", \ + "0.261294, 0.812722, 1.16431, 1.76803, 2.81737, 4.61425, 7.61263", \ + "0.392873, 1.00753, 1.36816, 1.94176, 2.93535, 4.65755, 7.6277" \ ); } cell_fall (TIMING_DELAY_7x7ds1) { index_1 ("0.0186, 0.0966, 0.174, 0.3294, 0.6408, 1.263, 2.5074"); index_2 ("0.001, 0.0468, 0.078, 0.1296, 0.216, 0.36, 0.6"); values ( \ - "0.0386673, 0.125809, 0.183701, 0.279151, 0.438709, 0.704508, 1.14739", \ - "0.0755881, 0.176413, 0.234569, 0.329842, 0.489434, 0.755633, 1.19825", \ - "0.0994851, 0.220849, 0.283189, 0.380199, 0.53951, 0.805168, 1.2486", \ - "0.134586, 0.295777, 0.369443, 0.476405, 0.640892, 0.907176, 1.34934", \ - "0.179372, 0.405593, 0.502889, 0.635135, 0.824991, 1.10527, 1.54938", \ - "0.235492, 0.561877, 0.699778, 0.877753, 1.11991, 1.45638, 1.94119", \ - "0.299817, 0.767465, 0.968949, 1.23, 1.5628, 2.0056, 2.60278" \ + "0.0386921, 0.12581, 0.183776, 0.279144, 0.43867, 0.704512, 1.14751", \ + "0.0756003, 0.176412, 0.234547, 0.329848, 0.489402, 0.755658, 1.19824", \ + "0.0994843, 0.220849, 0.283189, 0.38022, 0.53951, 0.805167, 1.2486", \ + "0.134585, 0.295777, 0.369442, 0.476405, 0.640859, 0.907175, 1.34934", \ + "0.17937, 0.405593, 0.502888, 0.635134, 0.82499, 1.10542, 1.54938", \ + "0.235489, 0.561885, 0.699777, 0.877753, 1.11976, 1.45654, 1.94122", \ + "0.299815, 0.767464, 0.968948, 1.22999, 1.5628, 2.0056, 2.60278" \ ); } fall_transition (TIMING_DELAY_7x7ds1) { index_1 ("0.0186, 0.0966, 0.174, 0.3294, 0.6408, 1.263, 2.5074"); index_2 ("0.001, 0.0468, 0.078, 0.1296, 0.216, 0.36, 0.6"); values ( \ - "0.0252861, 0.138933, 0.216138, 0.34458, 0.558956, 0.916456, 1.5134", \ - "0.0398598, 0.144278, 0.218334, 0.344581, 0.559237, 0.91742, 1.51341", \ - "0.0546022, 0.161138, 0.230522, 0.35109, 0.560281, 0.917421, 1.51371", \ - "0.0806604, 0.199835, 0.267712, 0.380038, 0.577245, 0.922374, 1.51372", \ - "0.124965, 0.275322, 0.347357, 0.462008, 0.645749, 0.964752, 1.52632", \ - "0.198688, 0.405089, 0.492148, 0.617457, 0.81157, 1.11876, 1.63719", \ - "0.317774, 0.613224, 0.737865, 0.895435, 1.11959, 1.44727, 1.96551" \ + "0.0252885, 0.138933, 0.216237, 0.344581, 0.558942, 0.916455, 1.51225", \ + "0.0398519, 0.144278, 0.218314, 0.344582, 0.559118, 0.917423, 1.51255", \ + "0.0546018, 0.161138, 0.230513, 0.351059, 0.56035, 0.917424, 1.51371", \ + "0.0806602, 0.199834, 0.267712, 0.380038, 0.577648, 0.922374, 1.51372", \ + "0.124964, 0.276044, 0.347357, 0.462008, 0.645748, 0.964879, 1.52631", \ + "0.19869, 0.405052, 0.492148, 0.617456, 0.811654, 1.11917, 1.63713", \ + "0.317771, 0.613224, 0.737864, 0.89531, 1.11959, 1.44727, 1.96551" \ ); } } @@ -24280,52 +24354,52 @@ library (sg13g2_stdcell_slow_1p08V_125C) { index_1 ("0.0186, 0.0966, 0.174, 0.3294, 0.6408, 1.263, 2.5074"); index_2 ("0.001, 0.0468, 0.078, 0.1296, 0.216, 0.36, 0.6"); values ( \ - "0.0973769, 0.531807, 0.82141, 1.30007, 2.10213, 3.43771, 5.66389", \ - "0.120982, 0.555585, 0.84656, 1.32658, 2.12884, 3.46578, 5.6927", \ - "0.145413, 0.584057, 0.8755, 1.35613, 2.15921, 3.4959, 5.72326", \ - "0.181943, 0.643549, 0.935305, 1.4144, 2.21813, 3.55577, 5.78624", \ - "0.231682, 0.761796, 1.05692, 1.53531, 2.33787, 3.67412, 5.90135", \ - "0.295558, 0.951882, 1.27927, 1.77634, 2.57781, 3.91062, 6.13619", \ - "0.387957, 1.23053, 1.63206, 2.20519, 3.06205, 4.41084, 6.63212" \ + "0.0973389, 0.531792, 0.821354, 1.30001, 2.10178, 3.4376, 5.66499", \ + "0.120979, 0.555559, 0.846535, 1.3266, 2.12877, 3.4653, 5.69233", \ + "0.145449, 0.584054, 0.875431, 1.35635, 2.15875, 3.4958, 5.72271", \ + "0.181938, 0.643534, 0.935379, 1.41434, 2.21735, 3.5564, 5.78262", \ + "0.231677, 0.761779, 1.05692, 1.53523, 2.33777, 3.67434, 5.90117", \ + "0.29555, 0.951866, 1.27925, 1.7763, 2.57774, 3.90979, 6.13602", \ + "0.387947, 1.2305, 1.63203, 2.20516, 3.06203, 4.41074, 6.63194" \ ); } rise_transition (TIMING_DELAY_7x7ds1) { index_1 ("0.0186, 0.0966, 0.174, 0.3294, 0.6408, 1.263, 2.5074"); index_2 ("0.001, 0.0468, 0.078, 0.1296, 0.216, 0.36, 0.6"); values ( \ - "0.108529, 0.684197, 1.07437, 1.72012, 2.80374, 4.6041, 7.60363", \ - "0.111795, 0.684386, 1.07478, 1.72064, 2.80375, 4.60411, 7.60752", \ - "0.125325, 0.684387, 1.07479, 1.72065, 2.80376, 4.60412, 7.60753", \ - "0.151323, 0.690371, 1.07712, 1.72194, 2.80377, 4.60413, 7.60848", \ - "0.194656, 0.732458, 1.09661, 1.72541, 2.80378, 4.60414, 7.60849", \ - "0.265534, 0.852968, 1.1992, 1.78797, 2.82283, 4.61318, 7.6085", \ - "0.381835, 1.08008, 1.44605, 2.01947, 2.99099, 4.68384, 7.62996" \ + "0.108485, 0.684187, 1.07471, 1.72047, 2.80197, 4.60395, 7.60793", \ + "0.111801, 0.684338, 1.07474, 1.72048, 2.80198, 4.60422, 7.60794", \ + "0.125345, 0.684339, 1.07475, 1.72068, 2.80199, 4.60423, 7.60795", \ + "0.151318, 0.690352, 1.07476, 1.72184, 2.802, 4.60424, 7.60796", \ + "0.194651, 0.732298, 1.09728, 1.7253, 2.80201, 4.60425, 7.60797", \ + "0.265528, 0.854477, 1.19916, 1.78793, 2.82209, 4.60426, 7.60798", \ + "0.381828, 1.08006, 1.44602, 2.01945, 2.99234, 4.68369, 7.62974" \ ); } cell_fall (TIMING_DELAY_7x7ds1) { index_1 ("0.0186, 0.0966, 0.174, 0.3294, 0.6408, 1.263, 2.5074"); index_2 ("0.001, 0.0468, 0.078, 0.1296, 0.216, 0.36, 0.6"); values ( \ - "0.0326416, 0.118842, 0.176354, 0.271387, 0.430476, 0.695786, 1.13772", \ - "0.0643809, 0.169456, 0.227431, 0.322367, 0.481588, 0.747347, 1.18904", \ - "0.0836958, 0.213237, 0.275684, 0.372772, 0.531694, 0.796994, 1.23989", \ - "0.111551, 0.285004, 0.359802, 0.46754, 0.632214, 0.897818, 1.33913", \ - "0.143487, 0.391981, 0.491356, 0.625367, 0.817034, 1.0968, 1.54024", \ - "0.18106, 0.539366, 0.683093, 0.864355, 1.10927, 1.44628, 1.9319", \ - "0.217017, 0.734497, 0.94323, 1.21014, 1.54757, 1.99308, 2.59104" \ + "0.0326412, 0.118833, 0.176365, 0.271387, 0.43051, 0.695783, 1.13773", \ + "0.0643853, 0.169443, 0.227451, 0.322394, 0.48152, 0.747352, 1.1891", \ + "0.083695, 0.213236, 0.275683, 0.372708, 0.531693, 0.79695, 1.23983", \ + "0.11155, 0.285004, 0.359801, 0.467566, 0.632212, 0.897818, 1.33951", \ + "0.143467, 0.39198, 0.491355, 0.625367, 0.817034, 1.09674, 1.54026", \ + "0.181057, 0.539365, 0.683092, 0.864354, 1.10927, 1.44628, 1.9319", \ + "0.217015, 0.734493, 0.943229, 1.21014, 1.54757, 1.99308, 2.59104" \ ); } fall_transition (TIMING_DELAY_7x7ds1) { index_1 ("0.0186, 0.0966, 0.174, 0.3294, 0.6408, 1.263, 2.5074"); index_2 ("0.001, 0.0468, 0.078, 0.1296, 0.216, 0.36, 0.6"); values ( \ - "0.0193516, 0.131817, 0.209146, 0.336919, 0.550979, 0.907736, 1.50256", \ - "0.035243, 0.13802, 0.211476, 0.337058, 0.55098, 0.908406, 1.50257", \ - "0.0498732, 0.15562, 0.224288, 0.344094, 0.552572, 0.908407, 1.50343", \ - "0.0759529, 0.19526, 0.262426, 0.373959, 0.569561, 0.913314, 1.50344", \ - "0.120785, 0.27007, 0.34212, 0.456058, 0.638896, 0.956431, 1.51732", \ - "0.193051, 0.400046, 0.486918, 0.613199, 0.806321, 1.11237, 1.62863", \ - "0.313008, 0.608211, 0.732587, 0.889971, 1.11596, 1.43893, 1.95482" \ + "0.0193669, 0.131826, 0.209143, 0.337074, 0.550979, 0.907736, 1.50242", \ + "0.0351602, 0.138016, 0.211373, 0.337234, 0.551686, 0.908405, 1.50243", \ + "0.0498728, 0.155619, 0.224405, 0.34402, 0.552572, 0.908406, 1.50344", \ + "0.0759522, 0.19526, 0.262426, 0.374027, 0.569557, 0.913315, 1.50345", \ + "0.12075, 0.27007, 0.342119, 0.456053, 0.638895, 0.956354, 1.51711", \ + "0.193049, 0.400046, 0.486918, 0.613199, 0.80632, 1.11237, 1.62863", \ + "0.313005, 0.60821, 0.732588, 0.88997, 1.11596, 1.43893, 1.95484" \ ); } } @@ -24335,26 +24409,26 @@ library (sg13g2_stdcell_slow_1p08V_125C) { index_1 ("0.0186, 0.0966, 0.174, 0.3294, 0.6408, 1.263, 2.5074"); index_2 ("0.001, 0.0468, 0.078, 0.1296, 0.216, 0.36, 0.6"); values ( \ - "0.0151906, 0.0154022, 0.0153221, 0.0152174, 0.0151703, 0.0150744, 0.0150577", \ - "0.0149005, 0.0151788, 0.0152009, 0.0151245, 0.0149703, 0.014924, 0.0149356", \ - "0.0148026, 0.0150783, 0.015135, 0.0150557, 0.0149425, 0.0149447, 0.0149396", \ - "0.0147529, 0.0149596, 0.0150279, 0.0149578, 0.0148551, 0.0148872, 0.0149027", \ - "0.0147023, 0.0148873, 0.0148419, 0.0148772, 0.0147452, 0.0148244, 0.0149771", \ - "0.0148925, 0.0148449, 0.0147975, 0.0148851, 0.0147744, 0.014745, 0.0147893", \ - "0.0163206, 0.0154879, 0.0153336, 0.0150208, 0.0150417, 0.0149336, 0.0147297" \ + "0.015188, 0.0153937, 0.0153319, 0.015217, 0.0152104, 0.0151039, 0.0148546", \ + "0.0148982, 0.0151769, 0.0152001, 0.015129, 0.0149867, 0.0149244, 0.0148876", \ + "0.0148009, 0.0150649, 0.0151336, 0.0150504, 0.0149212, 0.0150483, 0.015061", \ + "0.0147505, 0.01494, 0.0149935, 0.0149627, 0.0148529, 0.0148856, 0.0148918", \ + "0.0146989, 0.0148894, 0.0148471, 0.0149332, 0.0147428, 0.0148226, 0.0149757", \ + "0.0148905, 0.0148412, 0.0148212, 0.0148986, 0.0146131, 0.0148213, 0.0147366", \ + "0.0163182, 0.015484, 0.0153135, 0.0150549, 0.0150305, 0.0148379, 0.0147571" \ ); } fall_power (POWER_7x7ds1) { index_1 ("0.0186, 0.0966, 0.174, 0.3294, 0.6408, 1.263, 2.5074"); index_2 ("0.001, 0.0468, 0.078, 0.1296, 0.216, 0.36, 0.6"); values ( \ - "0.00551963, 0.00540021, 0.00542001, 0.00526368, 0.00509827, 0.00479749, 0.00439319", \ - "0.00515739, 0.00520566, 0.00511916, 0.0051208, 0.00484366, 0.00466301, 0.00411165", \ - "0.00502155, 0.00506908, 0.00510483, 0.00495158, 0.00479207, 0.00458816, 0.00418266", \ - "0.00500021, 0.005073, 0.00501593, 0.00493448, 0.00512704, 0.00492886, 0.00401479", \ - "0.00533477, 0.00516432, 0.00512274, 0.0050185, 0.00470616, 0.00485079, 0.00424102", \ - "0.00646732, 0.00577101, 0.00551207, 0.00549439, 0.00516142, 0.00464709, 0.00415361", \ - "0.0094452, 0.0076784, 0.00723366, 0.00656503, 0.00615291, 0.00573647, 0.00434297" \ + "0.00551224, 0.00546837, 0.00542141, 0.00526503, 0.00509786, 0.00479735, 0.00422839", \ + "0.00514008, 0.00522131, 0.00521051, 0.00509105, 0.00484203, 0.00466422, 0.00413307", \ + "0.00504178, 0.00507913, 0.00510959, 0.00495509, 0.00479667, 0.0045893, 0.00416687", \ + "0.00500334, 0.00507141, 0.00502365, 0.00495389, 0.00487924, 0.00492994, 0.00402047", \ + "0.00534728, 0.00514025, 0.00512427, 0.00505963, 0.00471825, 0.00483306, 0.00397578", \ + "0.00646835, 0.00577432, 0.00552566, 0.00549281, 0.005234, 0.00465473, 0.00426017", \ + "0.00944596, 0.00768108, 0.00711099, 0.00657366, 0.00615441, 0.00585166, 0.00431455" \ ); } } @@ -24364,26 +24438,26 @@ library (sg13g2_stdcell_slow_1p08V_125C) { index_1 ("0.0186, 0.0966, 0.174, 0.3294, 0.6408, 1.263, 2.5074"); index_2 ("0.001, 0.0468, 0.078, 0.1296, 0.216, 0.36, 0.6"); values ( \ - "0.0125219, 0.0127324, 0.0126816, 0.0125633, 0.0125046, 0.0124612, 0.012291", \ - "0.0122315, 0.012517, 0.0125345, 0.0124558, 0.0123089, 0.0123785, 0.0121679", \ - "0.0121289, 0.0124255, 0.0124186, 0.0124035, 0.0122975, 0.0123714, 0.0121297", \ - "0.012079, 0.0122853, 0.0123221, 0.0122844, 0.0121847, 0.012192, 0.0122848", \ - "0.012057, 0.0122343, 0.0121661, 0.0122326, 0.0121048, 0.0121353, 0.0123175", \ - "0.0123441, 0.0122407, 0.0121977, 0.0122339, 0.0119801, 0.0122037, 0.0122297", \ - "0.0141641, 0.0130021, 0.012838, 0.0125091, 0.0124148, 0.0124935, 0.0122412" \ + "0.0125241, 0.0127312, 0.0126737, 0.0125644, 0.0125225, 0.0124615, 0.0122896", \ + "0.0122606, 0.0125136, 0.0125344, 0.0124569, 0.0123272, 0.0123749, 0.0122897", \ + "0.0121312, 0.0124249, 0.0124211, 0.0123765, 0.0122779, 0.0123625, 0.0121232", \ + "0.0120804, 0.0122903, 0.0124257, 0.0122802, 0.0121836, 0.0121935, 0.0123017", \ + "0.0120571, 0.0122316, 0.0121967, 0.0121969, 0.012103, 0.0121386, 0.0123181", \ + "0.012345, 0.0122443, 0.0121755, 0.0123171, 0.0119764, 0.0121673, 0.012229", \ + "0.0141617, 0.0130038, 0.0128438, 0.0124877, 0.0124375, 0.0124916, 0.0122583" \ ); } fall_power (POWER_7x7ds1) { index_1 ("0.0186, 0.0966, 0.174, 0.3294, 0.6408, 1.263, 2.5074"); index_2 ("0.001, 0.0468, 0.078, 0.1296, 0.216, 0.36, 0.6"); values ( \ - "0.00508315, 0.00498693, 0.00492772, 0.00481839, 0.00468116, 0.00433722, 0.00382406", \ - "0.00465274, 0.00482733, 0.00476476, 0.00470131, 0.0044973, 0.00433472, 0.003785", \ - "0.00450313, 0.00468975, 0.00472757, 0.00460088, 0.00443848, 0.00419058, 0.00384783", \ - "0.00444169, 0.00466311, 0.0046463, 0.00458247, 0.00454293, 0.00408218, 0.00370244", \ - "0.00475494, 0.00473845, 0.00471348, 0.00466627, 0.00434591, 0.00462871, 0.0041248", \ - "0.00590027, 0.00524927, 0.00503782, 0.00498205, 0.00495916, 0.00422956, 0.00373806", \ - "0.00888214, 0.00716414, 0.0065238, 0.00607985, 0.00583615, 0.00540342, 0.00401526" \ + "0.00506626, 0.00498866, 0.00492682, 0.00481765, 0.00467884, 0.00433301, 0.00382312", \ + "0.00467108, 0.00482353, 0.0048044, 0.00468051, 0.00449465, 0.00428493, 0.00378618", \ + "0.00450494, 0.00468085, 0.00472831, 0.00458704, 0.00445476, 0.0042012, 0.0038379", \ + "0.00444097, 0.00467566, 0.00463522, 0.00458864, 0.00481787, 0.00491436, 0.00370272", \ + "0.0047518, 0.00473907, 0.0047144, 0.00472096, 0.00432947, 0.00463498, 0.00412458", \ + "0.00590326, 0.00524925, 0.00504731, 0.00497997, 0.00491358, 0.00429682, 0.00373491", \ + "0.00888135, 0.00716427, 0.0065226, 0.00608121, 0.00582558, 0.00540243, 0.0040038" \ ); } } @@ -24393,26 +24467,26 @@ library (sg13g2_stdcell_slow_1p08V_125C) { index_1 ("0.0186, 0.0966, 0.174, 0.3294, 0.6408, 1.263, 2.5074"); index_2 ("0.001, 0.0468, 0.078, 0.1296, 0.216, 0.36, 0.6"); values ( \ - "0.00981646, 0.0100227, 0.00997469, 0.00985888, 0.00984065, 0.00963914, 0.00953747", \ - "0.00952712, 0.00980554, 0.00980138, 0.00974286, 0.00961247, 0.00958692, 0.00944653", \ - "0.00940556, 0.00977062, 0.00972406, 0.0096704, 0.00954123, 0.00952099, 0.00965277", \ - "0.00937997, 0.00956424, 0.0096847, 0.00957268, 0.0095157, 0.0094681, 0.00970825", \ - "0.00943192, 0.00953924, 0.00950635, 0.00950319, 0.00940599, 0.00943142, 0.00961073", \ - "0.0100323, 0.00966937, 0.00957796, 0.00952147, 0.0093292, 0.009501, 0.0094276", \ - "0.0124667, 0.0108253, 0.0105403, 0.0100414, 0.00989787, 0.00966626, 0.0097356" \ + "0.00981172, 0.0100247, 0.00997335, 0.00984678, 0.00984366, 0.00963926, 0.00954186", \ + "0.00954002, 0.00980752, 0.00980039, 0.00974268, 0.00962848, 0.00958728, 0.00954774", \ + "0.00940286, 0.00977045, 0.00971558, 0.0096707, 0.00954852, 0.00960547, 0.0096728", \ + "0.00938363, 0.00956404, 0.00968809, 0.00957274, 0.00951558, 0.00946874, 0.00970954", \ + "0.00943334, 0.00954468, 0.00948211, 0.00950433, 0.00939583, 0.00946543, 0.00961168", \ + "0.0100312, 0.0096361, 0.00956221, 0.00952636, 0.00931025, 0.00961565, 0.00924142", \ + "0.0124651, 0.0108126, 0.0105459, 0.0100375, 0.00995565, 0.0098224, 0.00973178" \ ); } fall_power (POWER_7x7ds1) { index_1 ("0.0186, 0.0966, 0.174, 0.3294, 0.6408, 1.263, 2.5074"); index_2 ("0.001, 0.0468, 0.078, 0.1296, 0.216, 0.36, 0.6"); values ( \ - "0.00398857, 0.00401697, 0.00390219, 0.0038283, 0.00362689, 0.00332202, 0.00292201", \ - "0.00361436, 0.00400265, 0.00395754, 0.00386675, 0.00375019, 0.00353237, 0.00299083", \ - "0.003469, 0.00386283, 0.00394358, 0.00383936, 0.00368305, 0.00345748, 0.00310007", \ - "0.00344197, 0.0038614, 0.00385318, 0.00382812, 0.0037969, 0.00387306, 0.00298312", \ - "0.00380483, 0.0038401, 0.00392504, 0.00381461, 0.00349827, 0.00378239, 0.00327729", \ - "0.00503208, 0.00438133, 0.00418173, 0.0041761, 0.00411571, 0.003542, 0.00295817", \ - "0.00806814, 0.00624244, 0.00558407, 0.00522878, 0.00489404, 0.00471569, 0.00348604" \ + "0.00399645, 0.00401652, 0.00392144, 0.00382748, 0.00363714, 0.00332192, 0.00284229", \ + "0.00362076, 0.00400261, 0.00395599, 0.00388075, 0.0037353, 0.003536, 0.00298877", \ + "0.00346817, 0.00386283, 0.00395824, 0.00384306, 0.00368552, 0.00345774, 0.00310006", \ + "0.00344583, 0.00386138, 0.00385324, 0.00382811, 0.00411084, 0.00387305, 0.00298311", \ + "0.00380721, 0.0038596, 0.00393268, 0.0038146, 0.00349836, 0.00390141, 0.00327765", \ + "0.00503244, 0.00438515, 0.00418209, 0.00417657, 0.00410765, 0.00352476, 0.00297744", \ + "0.0080683, 0.00624302, 0.00558426, 0.00529192, 0.00489404, 0.00471563, 0.00348615" \ ); } } @@ -24422,26 +24496,26 @@ library (sg13g2_stdcell_slow_1p08V_125C) { index_1 ("0.0186, 0.0966, 0.174, 0.3294, 0.6408, 1.263, 2.5074"); index_2 ("0.001, 0.0468, 0.078, 0.1296, 0.216, 0.36, 0.6"); values ( \ - "0.0066338, 0.00710145, 0.00704825, 0.00693178, 0.00689596, 0.00681554, 0.00675645", \ - "0.00625737, 0.00675264, 0.00679168, 0.00676875, 0.00662004, 0.00660071, 0.00660947", \ - "0.00622236, 0.00658917, 0.00666325, 0.00665996, 0.00656624, 0.00658406, 0.00659397", \ - "0.00644917, 0.00647104, 0.00655563, 0.00659685, 0.0064573, 0.00654971, 0.00665888", \ - "0.00695912, 0.00660499, 0.00651961, 0.00675662, 0.00637016, 0.00638474, 0.00644858", \ - "0.00829283, 0.00720082, 0.00693916, 0.00696464, 0.00643579, 0.0066362, 0.00639339", \ - "0.0113839, 0.00917323, 0.00857536, 0.00798056, 0.00756436, 0.00707363, 0.00687947" \ + "0.00663243, 0.00710705, 0.00705227, 0.00694506, 0.00694681, 0.00681538, 0.00687535", \ + "0.00624071, 0.0067435, 0.00679143, 0.00675743, 0.00662014, 0.00668737, 0.00660009", \ + "0.00622005, 0.00658934, 0.0066603, 0.00666434, 0.00655588, 0.00660147, 0.00657301", \ + "0.00645138, 0.00647093, 0.00650747, 0.00659614, 0.00645471, 0.0065465, 0.00642315", \ + "0.00695873, 0.00658492, 0.006503, 0.00646441, 0.00634598, 0.00646336, 0.00647621", \ + "0.00829242, 0.00718742, 0.00695619, 0.0068955, 0.00642732, 0.00638168, 0.00638362", \ + "0.0113844, 0.00917379, 0.00858116, 0.00792371, 0.00761324, 0.00712179, 0.00687799" \ ); } fall_power (POWER_7x7ds1) { index_1 ("0.0186, 0.0966, 0.174, 0.3294, 0.6408, 1.263, 2.5074"); index_2 ("0.001, 0.0468, 0.078, 0.1296, 0.216, 0.36, 0.6"); values ( \ - "0.00275982, 0.00312473, 0.00307907, 0.0029832, 0.00283107, 0.00254192, 0.00202064", \ - "0.00239809, 0.00315889, 0.00315852, 0.00310145, 0.00300073, 0.00282944, 0.00230309", \ - "0.00231963, 0.00305017, 0.00315298, 0.00313758, 0.00298268, 0.00278903, 0.0024563", \ - "0.0024086, 0.00300768, 0.00300164, 0.00302393, 0.00303342, 0.0029685, 0.00219028", \ - "0.00302188, 0.00296474, 0.00310732, 0.00310999, 0.00288994, 0.00307476, 0.00255011", \ - "0.00433066, 0.00358832, 0.00329248, 0.00345683, 0.00341178, 0.00281815, 0.00248566", \ - "0.00761531, 0.00537387, 0.0048022, 0.00443912, 0.0042318, 0.00383155, 0.00256397" \ + "0.00276101, 0.00312559, 0.00308017, 0.00300311, 0.00282143, 0.00254403, 0.00204859", \ + "0.00239552, 0.00315849, 0.00314361, 0.00312068, 0.00310227, 0.00283034, 0.00229901", \ + "0.0023185, 0.00305018, 0.00316416, 0.00312509, 0.00298273, 0.00279917, 0.00245677", \ + "0.00240867, 0.00300767, 0.00300162, 0.00304275, 0.00314863, 0.00296855, 0.00219092", \ + "0.00302079, 0.0029647, 0.00310731, 0.00305846, 0.00288988, 0.00310626, 0.00247439", \ + "0.0043314, 0.00358952, 0.00329148, 0.00345678, 0.00341172, 0.00281858, 0.0024756", \ + "0.00761547, 0.00537381, 0.00480147, 0.00443513, 0.0042325, 0.00383154, 0.00253003" \ ); } } @@ -24449,74 +24523,74 @@ library (sg13g2_stdcell_slow_1p08V_125C) { pin (A) { direction : "input"; max_transition : 2.5074; - capacitance : 0.00535407; - rise_capacitance : 0.00537604; - rise_capacitance_range (0.00537604, 0.00537604); - fall_capacitance : 0.0053321; - fall_capacitance_range (0.0053321, 0.0053321); + capacitance : 0.00535724; + rise_capacitance : 0.00537918; + rise_capacitance_range (0.00508235, 0.00574967); + fall_capacitance : 0.0053353; + fall_capacitance_range (0.00472534, 0.00593733); } pin (B) { direction : "input"; max_transition : 2.5074; - capacitance : 0.0053304; - rise_capacitance : 0.0053727; - rise_capacitance_range (0.0053727, 0.0053727); - fall_capacitance : 0.0052881; - fall_capacitance_range (0.0052881, 0.0052881); + capacitance : 0.00533014; + rise_capacitance : 0.00537269; + rise_capacitance_range (0.0048076, 0.00589003); + fall_capacitance : 0.00528758; + fall_capacitance_range (0.00462416, 0.00596254); } pin (C) { direction : "input"; max_transition : 2.5074; - capacitance : 0.00529818; - rise_capacitance : 0.00536386; - rise_capacitance_range (0.00536386, 0.00536386); + capacitance : 0.00529822; + rise_capacitance : 0.00536393; + rise_capacitance_range (0.00463161, 0.00601727); fall_capacitance : 0.0052325; - fall_capacitance_range (0.0052325, 0.0052325); + fall_capacitance_range (0.00457372, 0.00597528); } pin (D) { direction : "input"; max_transition : 2.5074; - capacitance : 0.00522292; - rise_capacitance : 0.00537605; - rise_capacitance_range (0.00537605, 0.00537605); + capacitance : 0.00522295; + rise_capacitance : 0.00537611; + rise_capacitance_range (0.00432672, 0.00621468); fall_capacitance : 0.00506979; - fall_capacitance_range (0.00506979, 0.00506979); + fall_capacitance_range (0.00452557, 0.0053934); } } cell (sg13g2_o21ai_1) { area : 9.072; cell_footprint : "o21ai"; - cell_leakage_power : 493.338; + cell_leakage_power : 493.345; leakage_power () { - value : 110.295; + value : 110.302; when : "!A1&!A2&!B1&Y"; } leakage_power () { - value : 248.181; + value : 248.188; when : "A1&!A2&!B1&Y"; } leakage_power () { - value : 248.185; + value : 248.191; when : "!A1&A2&!B1&Y"; } leakage_power () { - value : 248.395; + value : 248.401; when : "A1&A2&!B1&Y"; } leakage_power () { - value : 418.494; + value : 418.501; when : "!A1&!A2&B1&Y"; } leakage_power () { - value : 1064.93; + value : 1064.94; when : "A1&!A2&B1&!Y"; } leakage_power () { - value : 899.564; + value : 899.57; when : "!A1&A2&B1&!Y"; } leakage_power () { - value : 708.662; + value : 708.669; when : "A1&A2&B1&!Y"; } pin (Y) { @@ -24532,38 +24606,38 @@ library (sg13g2_stdcell_slow_1p08V_125C) { index_1 ("0.0186, 0.0966, 0.174, 0.3294, 0.6408, 1.263, 2.5074"); index_2 ("0.001, 0.0234, 0.039, 0.0648, 0.108, 0.18, 0.3"); values ( \ - "0.0972159, 0.338476, 0.504007, 0.77671, 1.23363, 1.99425, 3.26189", \ - "0.130636, 0.373987, 0.540202, 0.812838, 1.26973, 2.03126, 3.29978", \ - "0.156737, 0.406314, 0.572076, 0.845518, 1.30224, 2.06335, 3.33136", \ - "0.196541, 0.467712, 0.634736, 0.908225, 1.36535, 2.12712, 3.39526", \ - "0.249634, 0.570962, 0.749573, 1.02903, 1.48691, 2.24876, 3.5164", \ - "0.315816, 0.729321, 0.938754, 1.246, 1.7229, 2.4883, 3.75626", \ - "0.412967, 0.964325, 1.23018, 1.60107, 2.14248, 2.95907, 4.24816" \ + "0.0972316, 0.338443, 0.503993, 0.776742, 1.23333, 1.99419, 3.26195", \ + "0.130637, 0.373962, 0.539743, 0.813037, 1.26973, 2.03127, 3.29979", \ + "0.156737, 0.406315, 0.572078, 0.845516, 1.30225, 2.06338, 3.33138", \ + "0.196541, 0.467713, 0.634738, 0.908229, 1.36527, 2.12713, 3.39473", \ + "0.249635, 0.570963, 0.749575, 1.02906, 1.48676, 2.24876, 3.51637", \ + "0.315816, 0.729323, 0.938756, 1.246, 1.72292, 2.48831, 3.75613", \ + "0.412968, 0.964327, 1.23018, 1.60107, 2.14248, 2.95908, 4.24817" \ ); } rise_transition (TIMING_DELAY_7x7ds1) { index_1 ("0.0186, 0.0966, 0.174, 0.3294, 0.6408, 1.263, 2.5074"); index_2 ("0.001, 0.0234, 0.039, 0.0648, 0.108, 0.18, 0.3"); values ( \ - "0.0708383, 0.396921, 0.623281, 0.997253, 1.6229, 2.66566, 4.40283", \ - "0.0739471, 0.397335, 0.623568, 0.997357, 1.62291, 2.66567, 4.40284", \ - "0.083168, 0.398387, 0.624636, 0.997358, 1.62385, 2.66568, 4.40285", \ - "0.102925, 0.409793, 0.628443, 0.997926, 1.62416, 2.66569, 4.40286", \ - "0.141768, 0.452896, 0.660451, 1.01495, 1.6281, 2.6657, 4.40287", \ - "0.213015, 0.550642, 0.758486, 1.09531, 1.67617, 2.68392, 4.40288", \ - "0.32734, 0.731063, 0.952822, 1.29711, 1.85841, 2.81294, 4.46722" \ + "0.0708386, 0.396923, 0.623286, 0.997258, 1.62268, 2.66567, 4.40285", \ + "0.073916, 0.39712, 0.62387, 0.997259, 1.62269, 2.66568, 4.40286", \ + "0.0831684, 0.398389, 0.624709, 0.99726, 1.62384, 2.66569, 4.40287", \ + "0.102925, 0.409798, 0.628445, 0.998384, 1.62411, 2.6657, 4.40304", \ + "0.141768, 0.452897, 0.660456, 1.015, 1.62687, 2.66571, 4.40305", \ + "0.213016, 0.550643, 0.758487, 1.09531, 1.67646, 2.68393, 4.40519", \ + "0.327341, 0.731064, 0.952824, 1.29712, 1.85841, 2.81285, 4.46723" \ ); } cell_fall (TIMING_DELAY_7x7ds1) { index_1 ("0.0186, 0.0966, 0.174, 0.3294, 0.6408, 1.263, 2.5074"); index_2 ("0.001, 0.0234, 0.039, 0.0648, 0.108, 0.18, 0.3"); values ( \ - "0.0705917, 0.229032, 0.337172, 0.515993, 0.814414, 1.31194, 2.14088", \ - "0.104435, 0.267652, 0.376012, 0.554676, 0.853444, 1.35109, 2.1805", \ - "0.128689, 0.303067, 0.412224, 0.591016, 0.889855, 1.38748, 2.21652", \ - "0.165384, 0.36742, 0.482255, 0.663834, 0.963337, 1.4612, 2.29132", \ - "0.211104, 0.468939, 0.600124, 0.797293, 1.10524, 1.60444, 2.43394", \ - "0.266388, 0.618932, 0.783162, 1.01573, 1.35901, 1.88416, 2.72112", \ + "0.0705865, 0.229027, 0.337178, 0.516008, 0.814422, 1.31193, 2.14093", \ + "0.104383, 0.267651, 0.375971, 0.554821, 0.853518, 1.35111, 2.18049", \ + "0.128689, 0.303031, 0.412211, 0.591021, 0.889871, 1.38746, 2.21651", \ + "0.165384, 0.36742, 0.482254, 0.663833, 0.963336, 1.46119, 2.29132", \ + "0.211104, 0.468939, 0.600124, 0.797293, 1.10524, 1.60444, 2.43371", \ + "0.266387, 0.618932, 0.783162, 1.01573, 1.35901, 1.88416, 2.72123", \ "0.333474, 0.820888, 1.04755, 1.35052, 1.76665, 2.36632, 3.26747" \ ); } @@ -24571,12 +24645,12 @@ library (sg13g2_stdcell_slow_1p08V_125C) { index_1 ("0.0186, 0.0966, 0.174, 0.3294, 0.6408, 1.263, 2.5074"); index_2 ("0.001, 0.0234, 0.039, 0.0648, 0.108, 0.18, 0.3"); values ( \ - "0.0437592, 0.251627, 0.395777, 0.63359, 1.0325, 1.69664, 2.80369", \ - "0.0498583, 0.252185, 0.395778, 0.63383, 1.03309, 1.69665, 2.80518", \ - "0.0595585, 0.257903, 0.398496, 0.637963, 1.0331, 1.69774, 2.80526", \ - "0.0795448, 0.278633, 0.41336, 0.642959, 1.03463, 1.69775, 2.80678", \ - "0.117745, 0.330739, 0.463495, 0.681796, 1.05731, 1.70485, 2.81089", \ - "0.186998, 0.435208, 0.572404, 0.788567, 1.15111, 1.76586, 2.83016", \ + "0.0437599, 0.251625, 0.395777, 0.634112, 1.0325, 1.69664, 2.80369", \ + "0.0499254, 0.252187, 0.395778, 0.634333, 1.03304, 1.69749, 2.80518", \ + "0.0595567, 0.257883, 0.398499, 0.637985, 1.03305, 1.69774, 2.80526", \ + "0.0795449, 0.278633, 0.41336, 0.642959, 1.03463, 1.69775, 2.80677", \ + "0.117745, 0.330739, 0.463495, 0.681796, 1.05731, 1.70485, 2.81111", \ + "0.186998, 0.435208, 0.572403, 0.788567, 1.15111, 1.76586, 2.83207", \ "0.299659, 0.616058, 0.775672, 1.00833, 1.3703, 1.97022, 2.98443" \ ); } @@ -24589,52 +24663,52 @@ library (sg13g2_stdcell_slow_1p08V_125C) { index_1 ("0.0186, 0.0966, 0.174, 0.3294, 0.6408, 1.263, 2.5074"); index_2 ("0.001, 0.0234, 0.039, 0.0648, 0.108, 0.18, 0.3"); values ( \ - "0.0864, 0.328697, 0.493955, 0.767168, 1.22363, 1.9844, 3.25214", \ - "0.117187, 0.363002, 0.529003, 0.802444, 1.25922, 2.02024, 3.2893", \ - "0.144788, 0.400437, 0.566338, 0.839821, 1.29696, 2.05808, 3.32637", \ - "0.186491, 0.474691, 0.641926, 0.915142, 1.37209, 2.1339, 3.40103", \ - "0.243928, 0.598676, 0.782107, 1.06238, 1.51845, 2.2789, 3.5461", \ - "0.319758, 0.786564, 1.01106, 1.33144, 1.81329, 2.57658, 3.84073", \ - "0.430311, 1.04961, 1.34693, 1.75363, 2.32643, 3.15991, 4.4532" \ + "0.0864038, 0.328681, 0.493959, 0.767164, 1.22363, 1.9844, 3.25215", \ + "0.117187, 0.363004, 0.529018, 0.802421, 1.25924, 2.02027, 3.2893", \ + "0.144789, 0.400419, 0.56634, 0.839995, 1.29697, 2.05807, 3.32637", \ + "0.186491, 0.474692, 0.641928, 0.915122, 1.37242, 2.13393, 3.40104", \ + "0.243928, 0.598676, 0.782108, 1.06238, 1.51843, 2.2789, 3.54599", \ + "0.319759, 0.786565, 1.01106, 1.33144, 1.8133, 2.57663, 3.84076", \ + "0.430311, 1.04962, 1.34693, 1.75363, 2.32643, 3.16002, 4.45321" \ ); } rise_transition (TIMING_DELAY_7x7ds1) { index_1 ("0.0186, 0.0966, 0.174, 0.3294, 0.6408, 1.263, 2.5074"); index_2 ("0.001, 0.0234, 0.039, 0.0648, 0.108, 0.18, 0.3"); values ( \ - "0.0708879, 0.397351, 0.623364, 0.99729, 1.62315, 2.66566, 4.40283", \ - "0.0780032, 0.397352, 0.624007, 0.997291, 1.62316, 2.66646, 4.40284", \ - "0.0931948, 0.399368, 0.624008, 0.997292, 1.62317, 2.66647, 4.40285", \ - "0.121288, 0.417906, 0.631662, 0.997629, 1.62394, 2.66648, 4.40286", \ - "0.164435, 0.483075, 0.680899, 1.02575, 1.62888, 2.66649, 4.40287", \ - "0.233036, 0.615101, 0.817275, 1.14103, 1.70199, 2.69145, 4.40316", \ - "0.339981, 0.835649, 1.07656, 1.42177, 1.9638, 2.88319, 4.49969" \ + "0.0708881, 0.397344, 0.62334, 0.997293, 1.62315, 2.66567, 4.40285", \ + "0.0780036, 0.397345, 0.62401, 0.997294, 1.62316, 2.66647, 4.40286", \ + "0.093195, 0.399493, 0.624011, 0.997295, 1.62317, 2.66648, 4.40287", \ + "0.121288, 0.417907, 0.631664, 0.997598, 1.62318, 2.66649, 4.40288", \ + "0.164435, 0.483074, 0.68087, 1.02574, 1.62905, 2.6665, 4.40289", \ + "0.233034, 0.615102, 0.817278, 1.14103, 1.702, 2.6915, 4.40317", \ + "0.339982, 0.835651, 1.07656, 1.42178, 1.96375, 2.8834, 4.4997" \ ); } cell_fall (TIMING_DELAY_7x7ds1) { index_1 ("0.0186, 0.0966, 0.174, 0.3294, 0.6408, 1.263, 2.5074"); index_2 ("0.001, 0.0234, 0.039, 0.0648, 0.108, 0.18, 0.3"); values ( \ - "0.0594263, 0.216197, 0.323703, 0.50164, 0.799137, 1.29489, 2.12147", \ - "0.0896642, 0.255265, 0.363215, 0.541279, 0.839131, 1.33503, 2.16218", \ - "0.11003, 0.290034, 0.399122, 0.577458, 0.87539, 1.37182, 2.19834", \ - "0.139384, 0.352744, 0.468322, 0.650036, 0.948746, 1.44543, 2.27316", \ - "0.17255, 0.450308, 0.583948, 0.782192, 1.09044, 1.58865, 2.41593", \ - "0.206739, 0.592926, 0.762799, 0.997593, 1.34267, 1.86787, 2.70356", \ - "0.242587, 0.782825, 1.01628, 1.32545, 1.74628, 2.34845, 3.24969" \ + "0.0594451, 0.21621, 0.323705, 0.501642, 0.798963, 1.2949, 2.12146", \ + "0.0896731, 0.255265, 0.3632, 0.541265, 0.839132, 1.33504, 2.16218", \ + "0.11003, 0.290033, 0.399122, 0.57745, 0.875469, 1.37181, 2.19834", \ + "0.139384, 0.352744, 0.468324, 0.650036, 0.948746, 1.44543, 2.27315", \ + "0.172518, 0.450164, 0.583948, 0.782191, 1.09044, 1.58865, 2.41615", \ + "0.206739, 0.592926, 0.762799, 0.997592, 1.34267, 1.86787, 2.70356", \ + "0.242586, 0.782821, 1.01628, 1.32545, 1.74628, 2.34845, 3.24938" \ ); } fall_transition (TIMING_DELAY_7x7ds1) { index_1 ("0.0186, 0.0966, 0.174, 0.3294, 0.6408, 1.263, 2.5074"); index_2 ("0.001, 0.0234, 0.039, 0.0648, 0.108, 0.18, 0.3"); values ( \ - "0.0313108, 0.237307, 0.380757, 0.617908, 1.01577, 1.6769, 2.77997", \ - "0.0387632, 0.238186, 0.381692, 0.618392, 1.01578, 1.67801, 2.78203", \ - "0.0486501, 0.244043, 0.383859, 0.620843, 1.01579, 1.67802, 2.78204", \ - "0.0686074, 0.265794, 0.39945, 0.626861, 1.01741, 1.67803, 2.78315", \ - "0.106941, 0.319165, 0.450397, 0.667359, 1.04114, 1.68449, 2.78316", \ - "0.178039, 0.425377, 0.560097, 0.775052, 1.1359, 1.74757, 2.80962", \ - "0.293286, 0.606918, 0.768869, 0.996617, 1.36002, 1.9546, 2.9629" \ + "0.0313101, 0.237311, 0.380757, 0.617908, 1.01505, 1.6769, 2.7816", \ + "0.0387512, 0.238186, 0.38171, 0.617909, 1.01506, 1.67801, 2.78203", \ + "0.0486501, 0.244042, 0.383859, 0.62084, 1.01573, 1.67802, 2.78204", \ + "0.0686073, 0.265794, 0.399619, 0.626862, 1.0174, 1.67803, 2.78315", \ + "0.106991, 0.319219, 0.450396, 0.667358, 1.04114, 1.68449, 2.78902", \ + "0.178039, 0.425377, 0.560097, 0.775051, 1.1359, 1.74788, 2.80962", \ + "0.293286, 0.606922, 0.768869, 0.996616, 1.36002, 1.9546, 2.9611" \ ); } } @@ -24648,52 +24722,52 @@ library (sg13g2_stdcell_slow_1p08V_125C) { index_1 ("0.0186, 0.0966, 0.174, 0.3294, 0.6408, 1.263, 2.5074"); index_2 ("0.001, 0.0234, 0.039, 0.0648, 0.108, 0.18, 0.3"); values ( \ - "0.0361858, 0.15438, 0.234718, 0.366727, 0.588587, 0.957472, 1.57262", \ - "0.0667849, 0.198173, 0.278524, 0.41108, 0.63271, 1.003, 1.61807", \ - "0.0860625, 0.242416, 0.324667, 0.457291, 0.678895, 1.04825, 1.66366", \ - "0.113772, 0.317444, 0.410168, 0.548007, 0.76974, 1.13878, 1.7551", \ - "0.148705, 0.42913, 0.546223, 0.707947, 0.945406, 1.31712, 1.93083", \ - "0.191474, 0.583586, 0.749314, 0.961054, 1.24962, 1.66147, 2.28904", \ - "0.247866, 0.799261, 1.03194, 1.33188, 1.72306, 2.24299, 2.96479" \ + "0.0361821, 0.154372, 0.23471, 0.366721, 0.588561, 0.957195, 1.5726", \ + "0.0667844, 0.198182, 0.27847, 0.410991, 0.632656, 1.00296, 1.61736", \ + "0.0860834, 0.242415, 0.324651, 0.457264, 0.678895, 1.04821, 1.66453", \ + "0.113772, 0.317443, 0.410167, 0.548004, 0.769738, 1.13877, 1.75526", \ + "0.148705, 0.429129, 0.546221, 0.707945, 0.945402, 1.31702, 1.93072", \ + "0.191473, 0.583584, 0.749312, 0.961051, 1.24961, 1.66144, 2.28907", \ + "0.247865, 0.79926, 1.03193, 1.33188, 1.72305, 2.24315, 2.96478" \ ); } rise_transition (TIMING_DELAY_7x7ds1) { index_1 ("0.0186, 0.0966, 0.174, 0.3294, 0.6408, 1.263, 2.5074"); index_2 ("0.001, 0.0234, 0.039, 0.0648, 0.108, 0.18, 0.3"); values ( \ - "0.0244804, 0.186931, 0.300451, 0.487569, 0.801602, 1.32476, 2.19749", \ - "0.0405402, 0.188383, 0.300452, 0.48757, 0.801603, 1.32597, 2.1975", \ - "0.057371, 0.200523, 0.305987, 0.488586, 0.801604, 1.32598, 2.19751", \ - "0.0841078, 0.236622, 0.333395, 0.50338, 0.805312, 1.32728, 2.19865", \ - "0.125045, 0.312829, 0.410674, 0.568158, 0.845893, 1.33904, 2.19866", \ - "0.187339, 0.445088, 0.558325, 0.723274, 0.985906, 1.4383, 2.24261", \ - "0.291681, 0.651989, 0.805157, 1.01013, 1.29912, 1.74127, 2.48633" \ + "0.0244754, 0.186931, 0.300402, 0.487566, 0.801675, 1.32477, 2.19748", \ + "0.0405403, 0.188386, 0.300403, 0.487567, 0.801676, 1.32597, 2.19759", \ + "0.0573485, 0.200521, 0.305871, 0.488592, 0.801677, 1.32598, 2.1976", \ + "0.0841077, 0.236621, 0.33339, 0.503377, 0.805309, 1.32599, 2.19874", \ + "0.125045, 0.312825, 0.410659, 0.568155, 0.845888, 1.33927, 2.19875", \ + "0.187339, 0.445086, 0.558311, 0.723271, 0.985901, 1.43809, 2.24302", \ + "0.291681, 0.651988, 0.805156, 1.01013, 1.29912, 1.74218, 2.48772" \ ); } cell_fall (TIMING_DELAY_7x7ds1) { index_1 ("0.0186, 0.0966, 0.174, 0.3294, 0.6408, 1.263, 2.5074"); index_2 ("0.001, 0.0234, 0.039, 0.0648, 0.108, 0.18, 0.3"); values ( \ - "0.0456682, 0.203403, 0.310953, 0.488686, 0.786397, 1.2822, 2.10872", \ - "0.0724076, 0.242918, 0.35084, 0.528886, 0.826773, 1.32282, 2.14961", \ - "0.0894285, 0.281969, 0.391162, 0.569341, 0.867107, 1.36319, 2.18996", \ - "0.114585, 0.351103, 0.469522, 0.651693, 0.949554, 1.44557, 2.27313", \ - "0.144423, 0.45423, 0.596813, 0.802025, 1.11153, 1.60775, 2.43311", \ - "0.181487, 0.599571, 0.783204, 1.0381, 1.3975, 1.92903, 2.76251", \ - "0.225096, 0.788188, 1.04162, 1.37948, 1.83397, 2.46767, 3.38808" \ + "0.0456678, 0.203411, 0.311006, 0.48869, 0.786397, 1.2822, 2.10876", \ + "0.0724203, 0.242917, 0.350752, 0.528911, 0.826776, 1.3228, 2.14962", \ + "0.0894285, 0.281973, 0.391162, 0.569339, 0.867221, 1.36385, 2.18992", \ + "0.114585, 0.351103, 0.469544, 0.651693, 0.949553, 1.44559, 2.2731", \ + "0.144423, 0.45423, 0.596813, 0.802023, 1.11153, 1.60775, 2.43296", \ + "0.181487, 0.599571, 0.7832, 1.03811, 1.39748, 1.92903, 2.76262", \ + "0.225096, 0.788188, 1.04162, 1.37891, 1.83397, 2.46767, 3.38798" \ ); } fall_transition (TIMING_DELAY_7x7ds1) { index_1 ("0.0186, 0.0966, 0.174, 0.3294, 0.6408, 1.263, 2.5074"); index_2 ("0.001, 0.0234, 0.039, 0.0648, 0.108, 0.18, 0.3"); values ( \ - "0.0315855, 0.23729, 0.380725, 0.617918, 1.01577, 1.6769, 2.77997", \ - "0.0460495, 0.238954, 0.382252, 0.618181, 1.01578, 1.67691, 2.77998", \ - "0.0612252, 0.249542, 0.385677, 0.620216, 1.01579, 1.67805, 2.77999", \ - "0.0861588, 0.283213, 0.411208, 0.632866, 1.01956, 1.67806, 2.78303", \ - "0.125963, 0.357871, 0.485864, 0.693248, 1.05471, 1.68891, 2.78782", \ - "0.189746, 0.487099, 0.63192, 0.844447, 1.19342, 1.78257, 2.82167", \ - "0.292828, 0.693085, 0.876734, 1.12541, 1.49198, 2.0749, 3.04616" \ + "0.0315856, 0.237291, 0.380999, 0.618342, 1.01577, 1.6769, 2.77998", \ + "0.0460618, 0.238954, 0.381077, 0.618343, 1.01578, 1.67691, 2.77999", \ + "0.0612252, 0.249546, 0.385677, 0.620215, 1.01579, 1.67866, 2.78", \ + "0.0861587, 0.283213, 0.411142, 0.632866, 1.01956, 1.67867, 2.78301", \ + "0.125963, 0.357871, 0.485857, 0.69324, 1.05439, 1.68891, 2.78811", \ + "0.189746, 0.487099, 0.631919, 0.844449, 1.19338, 1.78257, 2.81886", \ + "0.292828, 0.693084, 0.876734, 1.1243, 1.49198, 2.0749, 3.04627" \ ); } } @@ -24705,52 +24779,52 @@ library (sg13g2_stdcell_slow_1p08V_125C) { index_1 ("0.0186, 0.0966, 0.174, 0.3294, 0.6408, 1.263, 2.5074"); index_2 ("0.001, 0.0234, 0.039, 0.0648, 0.108, 0.18, 0.3"); values ( \ - "0.0361858, 0.15438, 0.234718, 0.366727, 0.588587, 0.957472, 1.57262", \ - "0.0667849, 0.198173, 0.278524, 0.41108, 0.63271, 1.003, 1.61807", \ - "0.0860625, 0.242416, 0.324667, 0.457291, 0.678895, 1.04825, 1.66366", \ - "0.113772, 0.317444, 0.410168, 0.548007, 0.76974, 1.13878, 1.7551", \ - "0.148705, 0.42913, 0.546223, 0.707947, 0.945406, 1.31712, 1.93083", \ - "0.191474, 0.583586, 0.749314, 0.961054, 1.24962, 1.66147, 2.28904", \ - "0.247866, 0.799261, 1.03194, 1.33188, 1.72306, 2.24299, 2.96479" \ + "0.0361821, 0.154372, 0.23471, 0.366721, 0.588561, 0.957195, 1.5726", \ + "0.0667844, 0.198182, 0.27847, 0.410991, 0.632656, 1.00296, 1.61736", \ + "0.0860834, 0.242415, 0.324651, 0.457264, 0.678895, 1.04821, 1.66453", \ + "0.113772, 0.317443, 0.410167, 0.548004, 0.769738, 1.13877, 1.75526", \ + "0.148705, 0.429129, 0.546221, 0.707945, 0.945402, 1.31702, 1.93072", \ + "0.191473, 0.583584, 0.749312, 0.961051, 1.24961, 1.66144, 2.28907", \ + "0.247865, 0.79926, 1.03193, 1.33188, 1.72305, 2.24315, 2.96478" \ ); } rise_transition (TIMING_DELAY_7x7ds1) { index_1 ("0.0186, 0.0966, 0.174, 0.3294, 0.6408, 1.263, 2.5074"); index_2 ("0.001, 0.0234, 0.039, 0.0648, 0.108, 0.18, 0.3"); values ( \ - "0.0244804, 0.186931, 0.300451, 0.487569, 0.801602, 1.32476, 2.19749", \ - "0.0405402, 0.188383, 0.300452, 0.48757, 0.801603, 1.32597, 2.1975", \ - "0.057371, 0.200523, 0.305987, 0.488586, 0.801604, 1.32598, 2.19751", \ - "0.0841078, 0.236622, 0.333395, 0.50338, 0.805312, 1.32728, 2.19865", \ - "0.125045, 0.312829, 0.410674, 0.568158, 0.845893, 1.33904, 2.19866", \ - "0.187339, 0.445088, 0.558325, 0.723274, 0.985906, 1.4383, 2.24261", \ - "0.291681, 0.651989, 0.805157, 1.01013, 1.29912, 1.74127, 2.48633" \ + "0.0244754, 0.186931, 0.300402, 0.487566, 0.801675, 1.32477, 2.19748", \ + "0.0405403, 0.188386, 0.300403, 0.487567, 0.801676, 1.32597, 2.19759", \ + "0.0573485, 0.200521, 0.305871, 0.488592, 0.801677, 1.32598, 2.1976", \ + "0.0841077, 0.236621, 0.33339, 0.503377, 0.805309, 1.32599, 2.19874", \ + "0.125045, 0.312825, 0.410659, 0.568155, 0.845888, 1.33927, 2.19875", \ + "0.187339, 0.445086, 0.558311, 0.723271, 0.985901, 1.43809, 2.24302", \ + "0.291681, 0.651988, 0.805156, 1.01013, 1.29912, 1.74218, 2.48772" \ ); } cell_fall (TIMING_DELAY_7x7ds1) { index_1 ("0.0186, 0.0966, 0.174, 0.3294, 0.6408, 1.263, 2.5074"); index_2 ("0.001, 0.0234, 0.039, 0.0648, 0.108, 0.18, 0.3"); values ( \ - "0.0456682, 0.203403, 0.310953, 0.488686, 0.786397, 1.2822, 2.10872", \ - "0.0724076, 0.242918, 0.35084, 0.528886, 0.826773, 1.32282, 2.14961", \ - "0.0894285, 0.281969, 0.391162, 0.569341, 0.867107, 1.36319, 2.18996", \ - "0.114585, 0.351103, 0.469522, 0.651693, 0.949554, 1.44557, 2.27313", \ - "0.144423, 0.45423, 0.596813, 0.802025, 1.11153, 1.60775, 2.43311", \ - "0.181487, 0.599571, 0.783204, 1.0381, 1.3975, 1.92903, 2.76251", \ - "0.225096, 0.788188, 1.04162, 1.37948, 1.83397, 2.46767, 3.38808" \ + "0.0456678, 0.203411, 0.311006, 0.48869, 0.786397, 1.2822, 2.10876", \ + "0.0724203, 0.242917, 0.350752, 0.528911, 0.826776, 1.3228, 2.14962", \ + "0.0894285, 0.281973, 0.391162, 0.569339, 0.867221, 1.36385, 2.18992", \ + "0.114585, 0.351103, 0.469544, 0.651693, 0.949553, 1.44559, 2.2731", \ + "0.144423, 0.45423, 0.596813, 0.802023, 1.11153, 1.60775, 2.43296", \ + "0.181487, 0.599571, 0.7832, 1.03811, 1.39748, 1.92903, 2.76262", \ + "0.225096, 0.788188, 1.04162, 1.37891, 1.83397, 2.46767, 3.38798" \ ); } fall_transition (TIMING_DELAY_7x7ds1) { index_1 ("0.0186, 0.0966, 0.174, 0.3294, 0.6408, 1.263, 2.5074"); index_2 ("0.001, 0.0234, 0.039, 0.0648, 0.108, 0.18, 0.3"); values ( \ - "0.0315855, 0.23729, 0.380725, 0.617918, 1.01577, 1.6769, 2.77997", \ - "0.0460495, 0.238954, 0.382252, 0.618181, 1.01578, 1.67691, 2.77998", \ - "0.0612252, 0.249542, 0.385677, 0.620216, 1.01579, 1.67805, 2.77999", \ - "0.0861588, 0.283213, 0.411208, 0.632866, 1.01956, 1.67806, 2.78303", \ - "0.125963, 0.357871, 0.485864, 0.693248, 1.05471, 1.68891, 2.78782", \ - "0.189746, 0.487099, 0.63192, 0.844447, 1.19342, 1.78257, 2.82167", \ - "0.292828, 0.693085, 0.876734, 1.12541, 1.49198, 2.0749, 3.04616" \ + "0.0315856, 0.237291, 0.380999, 0.618342, 1.01577, 1.6769, 2.77998", \ + "0.0460618, 0.238954, 0.381077, 0.618343, 1.01578, 1.67691, 2.77999", \ + "0.0612252, 0.249546, 0.385677, 0.620215, 1.01579, 1.67866, 2.78", \ + "0.0861587, 0.283213, 0.411142, 0.632866, 1.01956, 1.67867, 2.78301", \ + "0.125963, 0.357871, 0.485857, 0.69324, 1.05439, 1.68891, 2.78811", \ + "0.189746, 0.487099, 0.631919, 0.844449, 1.19338, 1.78257, 2.81886", \ + "0.292828, 0.693084, 0.876734, 1.1243, 1.49198, 2.0749, 3.04627" \ ); } } @@ -24760,26 +24834,26 @@ library (sg13g2_stdcell_slow_1p08V_125C) { index_1 ("0.0186, 0.0966, 0.174, 0.3294, 0.6408, 1.263, 2.5074"); index_2 ("0.001, 0.0234, 0.039, 0.0648, 0.108, 0.18, 0.3"); values ( \ - "0.00414069, 0.00412226, 0.00410082, 0.00403408, 0.0039427, 0.00377541, 0.00386933", \ - "0.00397467, 0.00405793, 0.00404869, 0.00398923, 0.00390134, 0.00376238, 0.00385334", \ - "0.00392458, 0.00403233, 0.00402917, 0.00397013, 0.00390941, 0.00374512, 0.00384539", \ - "0.00389995, 0.00398988, 0.00400626, 0.00394131, 0.00389663, 0.00373585, 0.00382197", \ - "0.003972, 0.00393591, 0.00396622, 0.00390478, 0.00394512, 0.0037055, 0.00373535", \ - "0.00443849, 0.0041685, 0.00412332, 0.00400217, 0.00409317, 0.00393587, 0.00381901", \ - "0.00605574, 0.0050847, 0.0048476, 0.00462892, 0.0042715, 0.00416686, 0.00410166" \ + "0.00414146, 0.0041192, 0.00409487, 0.00403765, 0.00392724, 0.00377309, 0.00387179", \ + "0.0039744, 0.00405113, 0.0040395, 0.00399502, 0.00390216, 0.00376239, 0.00385328", \ + "0.00392519, 0.00403233, 0.00402905, 0.00396899, 0.00390799, 0.00374496, 0.00384512", \ + "0.00389746, 0.00399551, 0.00400622, 0.0039693, 0.00390208, 0.00373622, 0.00378548", \ + "0.00396829, 0.00393591, 0.00396549, 0.0039154, 0.00387136, 0.00370551, 0.00383878", \ + "0.00443569, 0.00416894, 0.00412516, 0.0040022, 0.0041463, 0.00393587, 0.00385704", \ + "0.00605427, 0.00508497, 0.0048476, 0.00461709, 0.00427193, 0.00413896, 0.00410127" \ ); } fall_power (POWER_7x7ds1) { index_1 ("0.0186, 0.0966, 0.174, 0.3294, 0.6408, 1.263, 2.5074"); index_2 ("0.001, 0.0234, 0.039, 0.0648, 0.108, 0.18, 0.3"); values ( \ - "0.0039024, 0.00386144, 0.0038299, 0.00376734, 0.00367137, 0.00352469, 0.0032716", \ - "0.00367696, 0.00377814, 0.00373758, 0.00370505, 0.00363257, 0.00347729, 0.00327963", \ - "0.00360644, 0.00377416, 0.00371902, 0.00379571, 0.00361049, 0.00349557, 0.00326974", \ - "0.00356587, 0.00367448, 0.00371857, 0.0036736, 0.00359198, 0.00344303, 0.00333492", \ - "0.00366277, 0.00371179, 0.00370545, 0.00365235, 0.00366306, 0.00346759, 0.00348626", \ - "0.00418256, 0.00390974, 0.00389873, 0.00385946, 0.0036564, 0.00369515, 0.00343582", \ - "0.00579233, 0.00487127, 0.00465727, 0.00442866, 0.00425444, 0.00382533, 0.00361388" \ + "0.00390247, 0.00386113, 0.00382946, 0.00379129, 0.00367201, 0.00352433, 0.00327394", \ + "0.00367533, 0.00377833, 0.00373833, 0.00371902, 0.00363773, 0.0035015, 0.0032801", \ + "0.00360633, 0.00377359, 0.00372544, 0.00379648, 0.00361136, 0.00349408, 0.0032694", \ + "0.00356628, 0.00367448, 0.00372061, 0.00367374, 0.00359198, 0.00344254, 0.00333493", \ + "0.00366242, 0.00371018, 0.00371739, 0.00363489, 0.00366382, 0.00346787, 0.00349542", \ + "0.00418218, 0.0039099, 0.00389873, 0.00385952, 0.0036564, 0.00370966, 0.00367073", \ + "0.00579188, 0.00487097, 0.00465713, 0.00442866, 0.00425584, 0.00382533, 0.00361388" \ ); } } @@ -24789,26 +24863,26 @@ library (sg13g2_stdcell_slow_1p08V_125C) { index_1 ("0.0186, 0.0966, 0.174, 0.3294, 0.6408, 1.263, 2.5074"); index_2 ("0.001, 0.0234, 0.039, 0.0648, 0.108, 0.18, 0.3"); values ( \ - "0.00241772, 0.00245389, 0.00241544, 0.00236559, 0.00227361, 0.00210025, 0.00219273", \ - "0.0021445, 0.00231921, 0.00233249, 0.00229631, 0.00221349, 0.00208633, 0.00217102", \ - "0.00211328, 0.00226126, 0.00227634, 0.00225447, 0.00218169, 0.00204056, 0.00211795", \ - "0.0021905, 0.00225008, 0.00226048, 0.00222076, 0.00217947, 0.00203193, 0.00207136", \ - "0.00250018, 0.00234661, 0.00233419, 0.00224679, 0.0023986, 0.00198623, 0.00207013", \ - "0.00330752, 0.00273747, 0.00256667, 0.00242599, 0.00235709, 0.00205899, 0.00209482", \ - "0.00513632, 0.00402553, 0.00369972, 0.00329576, 0.00285465, 0.00259623, 0.00254598" \ + "0.00241742, 0.00245609, 0.00242133, 0.00236539, 0.00227315, 0.00209991, 0.00219304", \ + "0.00214449, 0.00231924, 0.00233256, 0.00229589, 0.00221351, 0.0020864, 0.00217116", \ + "0.00211474, 0.00227115, 0.00227645, 0.00225406, 0.00218117, 0.00204042, 0.00212532", \ + "0.00218694, 0.00225008, 0.00226047, 0.00222052, 0.00216863, 0.00203234, 0.00207509", \ + "0.00250038, 0.00234627, 0.00232754, 0.00224854, 0.00220533, 0.00198617, 0.00207819", \ + "0.00330514, 0.00273825, 0.00256507, 0.00242598, 0.00235753, 0.00205934, 0.00209088", \ + "0.00513673, 0.00402548, 0.00369971, 0.00329547, 0.00282112, 0.00261422, 0.00254474" \ ); } fall_power (POWER_7x7ds1) { index_1 ("0.0186, 0.0966, 0.174, 0.3294, 0.6408, 1.263, 2.5074"); index_2 ("0.001, 0.0234, 0.039, 0.0648, 0.108, 0.18, 0.3"); values ( \ - "0.00365152, 0.00379596, 0.00376766, 0.00372295, 0.00364823, 0.00347175, 0.00323429", \ - "0.00331819, 0.00374358, 0.00377054, 0.00373717, 0.00365449, 0.00352413, 0.00332165", \ - "0.00322347, 0.00367215, 0.0037003, 0.00375695, 0.0036472, 0.00352806, 0.00327651", \ - "0.00318852, 0.00354092, 0.00363575, 0.00363594, 0.00360948, 0.00348858, 0.0033659", \ - "0.00333749, 0.00350016, 0.00357282, 0.00357908, 0.00378844, 0.00345608, 0.00333138", \ - "0.00395351, 0.00368036, 0.00368376, 0.00369822, 0.00356352, 0.00361383, 0.00360874", \ - "0.00567697, 0.00462536, 0.00445197, 0.00418436, 0.00413155, 0.00372561, 0.00353388" \ + "0.00365288, 0.00379527, 0.00376733, 0.00372256, 0.00363081, 0.00347137, 0.00326026", \ + "0.00331783, 0.0037436, 0.00376943, 0.00372071, 0.00365449, 0.0035243, 0.00332175", \ + "0.00322378, 0.00367791, 0.00370031, 0.00375772, 0.00365157, 0.00352764, 0.00327344", \ + "0.00318839, 0.00354092, 0.00363681, 0.00363594, 0.00359989, 0.00348847, 0.00336571", \ + "0.00333634, 0.00349877, 0.00356245, 0.00357908, 0.00378663, 0.00345598, 0.00358108", \ + "0.00395328, 0.00368062, 0.00368392, 0.0036983, 0.00356358, 0.00364945, 0.00360825", \ + "0.00567691, 0.00462513, 0.00445234, 0.00418433, 0.00413166, 0.00372562, 0.00351367" \ ); } } @@ -24819,26 +24893,26 @@ library (sg13g2_stdcell_slow_1p08V_125C) { index_1 ("0.0186, 0.0966, 0.174, 0.3294, 0.6408, 1.263, 2.5074"); index_2 ("0.001, 0.0234, 0.039, 0.0648, 0.108, 0.18, 0.3"); values ( \ - "0.00150891, 0.00182492, 0.00181105, 0.00173594, 0.00167062, 0.00147217, 0.00119969", \ - "0.00126757, 0.00165593, 0.00173908, 0.00168459, 0.00161761, 0.00152603, 0.00129079", \ - "0.00128383, 0.00158432, 0.00161723, 0.00163618, 0.00157762, 0.00145882, 0.00122358", \ - "0.00141732, 0.00147534, 0.0015498, 0.00159215, 0.00153084, 0.00155343, 0.00128738", \ - "0.00185897, 0.00165304, 0.00161194, 0.00159007, 0.00161364, 0.00147799, 0.00112092", \ - "0.00286235, 0.00205892, 0.00191595, 0.00180287, 0.00158367, 0.00160909, 0.00123369", \ - "0.00511213, 0.00341554, 0.00305162, 0.00268186, 0.00235962, 0.00191042, 0.00151628" \ + "0.00150936, 0.00182322, 0.00181085, 0.00173623, 0.00166674, 0.00145719, 0.00119949", \ + "0.00126745, 0.00165596, 0.00174266, 0.001681, 0.00161498, 0.00152096, 0.00124974", \ + "0.00128446, 0.00158448, 0.0016121, 0.00175085, 0.00157765, 0.00145808, 0.00126256", \ + "0.00141769, 0.00147535, 0.00154637, 0.00161933, 0.00153083, 0.00147064, 0.0012904", \ + "0.00185922, 0.00165294, 0.00159877, 0.00159006, 0.0016249, 0.00144805, 0.0011182", \ + "0.00286246, 0.00205916, 0.00191144, 0.00180576, 0.00158496, 0.00162502, 0.0011963", \ + "0.0051121, 0.00341554, 0.00305165, 0.00268214, 0.0023592, 0.0018654, 0.00151595" \ ); } fall_power (POWER_7x7ds1) { index_1 ("0.0186, 0.0966, 0.174, 0.3294, 0.6408, 1.263, 2.5074"); index_2 ("0.001, 0.0234, 0.039, 0.0648, 0.108, 0.18, 0.3"); values ( \ - "0.00208074, 0.00231433, 0.00228952, 0.00224252, 0.00217342, 0.00200032, 0.00174847", \ - "0.00181763, 0.00216044, 0.00222723, 0.00217262, 0.00212468, 0.00196774, 0.00173637", \ - "0.00182759, 0.0021233, 0.00213745, 0.00216968, 0.0020923, 0.00197791, 0.00171266", \ - "0.001977, 0.00202493, 0.00209366, 0.00208963, 0.00207521, 0.00194564, 0.00179452", \ - "0.00243567, 0.00217039, 0.00212606, 0.00209148, 0.0022221, 0.00188767, 0.00195867", \ - "0.00345378, 0.00270197, 0.00264981, 0.00241492, 0.00215932, 0.00219819, 0.0018162", \ - "0.0057258, 0.00428442, 0.00389396, 0.0034066, 0.00304322, 0.00247977, 0.00217651" \ + "0.00207946, 0.00231491, 0.0022967, 0.00225139, 0.00217331, 0.00200021, 0.0017497", \ + "0.00181802, 0.00216046, 0.00219416, 0.00217433, 0.00212462, 0.0019584, 0.00173685", \ + "0.00182772, 0.00212334, 0.00213745, 0.00216972, 0.00209243, 0.00200482, 0.00171155", \ + "0.001977, 0.00202493, 0.0020939, 0.00208963, 0.00207521, 0.00195094, 0.00179354", \ + "0.00243492, 0.00217148, 0.0021275, 0.00207534, 0.00222732, 0.00188757, 0.00196715", \ + "0.0034536, 0.00270218, 0.00264812, 0.00241809, 0.00216011, 0.00219803, 0.00204916", \ + "0.00572587, 0.00428441, 0.00389422, 0.00338896, 0.00304322, 0.00247982, 0.00217539" \ ); } } @@ -24848,26 +24922,26 @@ library (sg13g2_stdcell_slow_1p08V_125C) { index_1 ("0.0186, 0.0966, 0.174, 0.3294, 0.6408, 1.263, 2.5074"); index_2 ("0.001, 0.0234, 0.039, 0.0648, 0.108, 0.18, 0.3"); values ( \ - "0.00150891, 0.00182492, 0.00181105, 0.00173594, 0.00167062, 0.00147217, 0.00119969", \ - "0.00126757, 0.00165593, 0.00173908, 0.00168459, 0.00161761, 0.00152603, 0.00129079", \ - "0.00128383, 0.00158432, 0.00161723, 0.00163618, 0.00157762, 0.00145882, 0.00122358", \ - "0.00141732, 0.00147534, 0.0015498, 0.00159215, 0.00153084, 0.00155343, 0.00128738", \ - "0.00185897, 0.00165304, 0.00161194, 0.00159007, 0.00161364, 0.00147799, 0.00112092", \ - "0.00286235, 0.00205892, 0.00191595, 0.00180287, 0.00158367, 0.00160909, 0.00123369", \ - "0.00511213, 0.00341554, 0.00305162, 0.00268186, 0.00235962, 0.00191042, 0.00151628" \ + "0.00150936, 0.00182322, 0.00181085, 0.00173623, 0.00166674, 0.00145719, 0.00119949", \ + "0.00126745, 0.00165596, 0.00174266, 0.001681, 0.00161498, 0.00152096, 0.00124974", \ + "0.00128446, 0.00158448, 0.0016121, 0.00175085, 0.00157765, 0.00145808, 0.00126256", \ + "0.00141769, 0.00147535, 0.00154637, 0.00161933, 0.00153083, 0.00147064, 0.0012904", \ + "0.00185922, 0.00165294, 0.00159877, 0.00159006, 0.0016249, 0.00144805, 0.0011182", \ + "0.00286246, 0.00205916, 0.00191144, 0.00180576, 0.00158496, 0.00162502, 0.0011963", \ + "0.0051121, 0.00341554, 0.00305165, 0.00268214, 0.0023592, 0.0018654, 0.00151595" \ ); } fall_power (POWER_7x7ds1) { index_1 ("0.0186, 0.0966, 0.174, 0.3294, 0.6408, 1.263, 2.5074"); index_2 ("0.001, 0.0234, 0.039, 0.0648, 0.108, 0.18, 0.3"); values ( \ - "0.00208074, 0.00231433, 0.00228952, 0.00224252, 0.00217342, 0.00200032, 0.00174847", \ - "0.00181763, 0.00216044, 0.00222723, 0.00217262, 0.00212468, 0.00196774, 0.00173637", \ - "0.00182759, 0.0021233, 0.00213745, 0.00216968, 0.0020923, 0.00197791, 0.00171266", \ - "0.001977, 0.00202493, 0.00209366, 0.00208963, 0.00207521, 0.00194564, 0.00179452", \ - "0.00243567, 0.00217039, 0.00212606, 0.00209148, 0.0022221, 0.00188767, 0.00195867", \ - "0.00345378, 0.00270197, 0.00264981, 0.00241492, 0.00215932, 0.00219819, 0.0018162", \ - "0.0057258, 0.00428442, 0.00389396, 0.0034066, 0.00304322, 0.00247977, 0.00217651" \ + "0.00207946, 0.00231491, 0.0022967, 0.00225139, 0.00217331, 0.00200021, 0.0017497", \ + "0.00181802, 0.00216046, 0.00219416, 0.00217433, 0.00212462, 0.0019584, 0.00173685", \ + "0.00182772, 0.00212334, 0.00213745, 0.00216972, 0.00209243, 0.00200482, 0.00171155", \ + "0.001977, 0.00202493, 0.0020939, 0.00208963, 0.00207521, 0.00195094, 0.00179354", \ + "0.00243492, 0.00217148, 0.0021275, 0.00207534, 0.00222732, 0.00188757, 0.00196715", \ + "0.0034536, 0.00270218, 0.00264812, 0.00241809, 0.00216011, 0.00219803, 0.00204916", \ + "0.00572587, 0.00428441, 0.00389422, 0.00338896, 0.00304322, 0.00247982, 0.00217539" \ ); } } @@ -24876,28 +24950,28 @@ library (sg13g2_stdcell_slow_1p08V_125C) { direction : "input"; max_transition : 2.5074; capacitance : 0.00313366; - rise_capacitance : 0.00322856; - rise_capacitance_range (0.00322856, 0.00322856); - fall_capacitance : 0.00303876; - fall_capacitance_range (0.00303876, 0.00303876); + rise_capacitance : 0.00322852; + rise_capacitance_range (0.0028894, 0.0035875); + fall_capacitance : 0.00303881; + fall_capacitance_range (0.00273407, 0.00340724); } pin (A2) { direction : "input"; max_transition : 2.5074; - capacitance : 0.0031367; - rise_capacitance : 0.00328693; - rise_capacitance_range (0.00328693, 0.00328693); - fall_capacitance : 0.00298647; - fall_capacitance_range (0.00298647, 0.00298647); + capacitance : 0.00313676; + rise_capacitance : 0.00328698; + rise_capacitance_range (0.00269986, 0.00373865); + fall_capacitance : 0.00298655; + fall_capacitance_range (0.0027299, 0.00314304); } pin (B1) { direction : "input"; max_transition : 2.5074; - capacitance : 0.00302599; - rise_capacitance : 0.00311529; - rise_capacitance_range (0.00311529, 0.00311529); - fall_capacitance : 0.0029367; - fall_capacitance_range (0.0029367, 0.0029367); + capacitance : 0.00302602; + rise_capacitance : 0.00311536; + rise_capacitance_range (0.00268123, 0.00344148); + fall_capacitance : 0.00293667; + fall_capacitance_range (0.00250911, 0.00319584); } } cell (sg13g2_or2_1) { @@ -25103,18 +25177,18 @@ library (sg13g2_stdcell_slow_1p08V_125C) { max_transition : 2.5074; capacitance : 0.00230635; rise_capacitance : 0.00232097; - rise_capacitance_range (0.00232097, 0.00232097); + rise_capacitance_range (0.00217309, 0.002445); fall_capacitance : 0.00229174; - fall_capacitance_range (0.00229174, 0.00229174); + fall_capacitance_range (0.00206572, 0.00256108); } pin (B) { direction : "input"; max_transition : 2.5074; capacitance : 0.00215225; rise_capacitance : 0.00219324; - rise_capacitance_range (0.00219324, 0.00219324); + rise_capacitance_range (0.00191951, 0.00238552); fall_capacitance : 0.00211125; - fall_capacitance_range (0.00211125, 0.00211125); + fall_capacitance_range (0.00193054, 0.00224352); } } cell (sg13g2_or2_2) { @@ -25320,18 +25394,18 @@ library (sg13g2_stdcell_slow_1p08V_125C) { max_transition : 2.5074; capacitance : 0.00229836; rise_capacitance : 0.00231181; - rise_capacitance_range (0.00231181, 0.00231181); + rise_capacitance_range (0.00219045, 0.00241763); fall_capacitance : 0.00228491; - fall_capacitance_range (0.00228491, 0.00228491); + fall_capacitance_range (0.00207089, 0.00254041); } pin (B) { direction : "input"; max_transition : 2.5074; capacitance : 0.00214728; rise_capacitance : 0.00219118; - rise_capacitance_range (0.00219118, 0.00219118); + rise_capacitance_range (0.00198688, 0.00235024); fall_capacitance : 0.00210338; - fall_capacitance_range (0.00210338, 0.00210338); + fall_capacitance_range (0.00195939, 0.00221104); } } cell (sg13g2_or3_1) { @@ -25639,27 +25713,27 @@ library (sg13g2_stdcell_slow_1p08V_125C) { max_transition : 2.5074; capacitance : 0.00241239; rise_capacitance : 0.00245634; - rise_capacitance_range (0.00245634, 0.00245634); + rise_capacitance_range (0.00231762, 0.00256771); fall_capacitance : 0.00236843; - fall_capacitance_range (0.00236843, 0.00236843); + fall_capacitance_range (0.00211282, 0.00267539); } pin (B) { direction : "input"; max_transition : 2.5074; capacitance : 0.0023499; rise_capacitance : 0.00240039; - rise_capacitance_range (0.00240039, 0.00240039); + rise_capacitance_range (0.0021464, 0.00257582); fall_capacitance : 0.0022994; - fall_capacitance_range (0.0022994, 0.0022994); + fall_capacitance_range (0.0020153, 0.00262341); } pin (C) { direction : "input"; max_transition : 2.5074; capacitance : 0.00224838; rise_capacitance : 0.00232448; - rise_capacitance_range (0.00232448, 0.00232448); + rise_capacitance_range (0.00201961, 0.00255685); fall_capacitance : 0.00217228; - fall_capacitance_range (0.00217228, 0.00217228); + fall_capacitance_range (0.00196757, 0.002316); } } cell (sg13g2_or3_2) { @@ -25967,27 +26041,27 @@ library (sg13g2_stdcell_slow_1p08V_125C) { max_transition : 2.5074; capacitance : 0.00240657; rise_capacitance : 0.00244872; - rise_capacitance_range (0.00244872, 0.00244872); + rise_capacitance_range (0.00232182, 0.00254919); fall_capacitance : 0.00236442; - fall_capacitance_range (0.00236442, 0.00236442); + fall_capacitance_range (0.00211589, 0.00266335); } pin (B) { direction : "input"; max_transition : 2.5074; capacitance : 0.00234842; rise_capacitance : 0.00239971; - rise_capacitance_range (0.00239971, 0.00239971); + rise_capacitance_range (0.00216924, 0.00255491); fall_capacitance : 0.00229712; - fall_capacitance_range (0.00229712, 0.00229712); + fall_capacitance_range (0.00201865, 0.00261003); } pin (C) { direction : "input"; max_transition : 2.5074; capacitance : 0.00224914; rise_capacitance : 0.00233005; - rise_capacitance_range (0.00233005, 0.00233005); + rise_capacitance_range (0.00208829, 0.00252781); fall_capacitance : 0.00216823; - fall_capacitance_range (0.00216823, 0.00216823); + fall_capacitance_range (0.00199951, 0.00228661); } } cell (sg13g2_or4_1) { @@ -26413,36 +26487,36 @@ library (sg13g2_stdcell_slow_1p08V_125C) { max_transition : 2.5074; capacitance : 0.00240836; rise_capacitance : 0.00245523; - rise_capacitance_range (0.00245523, 0.00245523); + rise_capacitance_range (0.00233242, 0.00255653); fall_capacitance : 0.00236149; - fall_capacitance_range (0.00236149, 0.00236149); + fall_capacitance_range (0.00211925, 0.00263556); } pin (B) { direction : "input"; max_transition : 2.5074; capacitance : 0.00232261; rise_capacitance : 0.00237554; - rise_capacitance_range (0.00237554, 0.00237554); + rise_capacitance_range (0.00214536, 0.00253076); fall_capacitance : 0.00226968; - fall_capacitance_range (0.00226968, 0.00226968); + fall_capacitance_range (0.00200853, 0.00257142); } pin (C) { direction : "input"; max_transition : 2.5074; capacitance : 0.00229174; rise_capacitance : 0.00234888; - rise_capacitance_range (0.00234888, 0.00234888); + rise_capacitance_range (0.00208182, 0.00255534); fall_capacitance : 0.0022346; - fall_capacitance_range (0.0022346, 0.0022346); + fall_capacitance_range (0.00195552, 0.00255865); } pin (D) { direction : "input"; max_transition : 2.5074; capacitance : 0.00222881; rise_capacitance : 0.0023076; - rise_capacitance_range (0.0023076, 0.0023076); + rise_capacitance_range (0.00202022, 0.00256582); fall_capacitance : 0.00215002; - fall_capacitance_range (0.00215002, 0.00215002); + fall_capacitance_range (0.00196512, 0.0022756); } } cell (sg13g2_or4_2) { @@ -26868,41 +26942,41 @@ library (sg13g2_stdcell_slow_1p08V_125C) { max_transition : 2.5074; capacitance : 0.00239092; rise_capacitance : 0.00243533; - rise_capacitance_range (0.00243533, 0.00243533); + rise_capacitance_range (0.00231705, 0.00252759); fall_capacitance : 0.00234651; - fall_capacitance_range (0.00234651, 0.00234651); + fall_capacitance_range (0.00211096, 0.00261815); } pin (B) { direction : "input"; max_transition : 2.5074; capacitance : 0.00232425; rise_capacitance : 0.00237519; - rise_capacitance_range (0.00237519, 0.00237519); + rise_capacitance_range (0.0021557, 0.00251706); fall_capacitance : 0.00227332; - fall_capacitance_range (0.00227332, 0.00227332); + fall_capacitance_range (0.00201937, 0.00256959); } pin (C) { direction : "input"; max_transition : 2.5074; capacitance : 0.00229495; rise_capacitance : 0.00235196; - rise_capacitance_range (0.00235196, 0.00235196); + rise_capacitance_range (0.00210854, 0.00253596); fall_capacitance : 0.00223793; - fall_capacitance_range (0.00223793, 0.00223793); + fall_capacitance_range (0.001968, 0.00255166); } pin (D) { direction : "input"; max_transition : 2.5074; capacitance : 0.00223226; rise_capacitance : 0.00231596; - rise_capacitance_range (0.00231596, 0.00231596); + rise_capacitance_range (0.00209166, 0.00253147); fall_capacitance : 0.00214856; - fall_capacitance_range (0.00214856, 0.00214856); + fall_capacitance_range (0.00199194, 0.00225394); } } cell (sg13g2_sdfbbp_1) { area : 63.504; - cell_footprint : "sdfrrs"; + cell_footprint : "sdfbbp"; cell_leakage_power : 3658.31; dont_touch : true; dont_use : true; @@ -26998,6 +27072,7 @@ library (sg13g2_stdcell_slow_1p08V_125C) { timing () { related_pin : "CLK"; sdf_cond : "SCE == 1'b1"; + sdf_edges : start_edge; timing_sense : non_unate; timing_type : rising_edge; when : "SCE"; @@ -27056,6 +27131,7 @@ library (sg13g2_stdcell_slow_1p08V_125C) { } timing () { related_pin : "CLK"; + sdf_edges : start_edge; timing_sense : non_unate; timing_type : rising_edge; cell_rise (TIMING_DELAY_7x7ds1) { @@ -27113,6 +27189,7 @@ library (sg13g2_stdcell_slow_1p08V_125C) { } timing () { related_pin : "RESET_B"; + sdf_edges : start_edge; timing_sense : positive_unate; timing_type : clear; cell_fall (TIMING_DELAY_7x7ds1) { @@ -27144,6 +27221,7 @@ library (sg13g2_stdcell_slow_1p08V_125C) { } timing () { related_pin : "SET_B"; + sdf_edges : start_edge; timing_sense : negative_unate; timing_type : preset; cell_rise (TIMING_DELAY_7x7ds1) { @@ -27283,6 +27361,7 @@ library (sg13g2_stdcell_slow_1p08V_125C) { timing () { related_pin : "CLK"; sdf_cond : "SCE == 1'b1"; + sdf_edges : start_edge; timing_sense : non_unate; timing_type : rising_edge; when : "SCE"; @@ -27341,6 +27420,7 @@ library (sg13g2_stdcell_slow_1p08V_125C) { } timing () { related_pin : "CLK"; + sdf_edges : start_edge; timing_sense : non_unate; timing_type : rising_edge; cell_rise (TIMING_DELAY_7x7ds1) { @@ -27398,6 +27478,7 @@ library (sg13g2_stdcell_slow_1p08V_125C) { } timing () { related_pin : "RESET_B"; + sdf_edges : start_edge; timing_sense : negative_unate; timing_type : preset; cell_rise (TIMING_DELAY_7x7ds1) { @@ -27429,6 +27510,7 @@ library (sg13g2_stdcell_slow_1p08V_125C) { } timing () { related_pin : "SET_B"; + sdf_edges : start_edge; timing_sense : positive_unate; timing_type : clear; cell_fall (TIMING_DELAY_7x7ds1) { @@ -27566,9 +27648,9 @@ library (sg13g2_stdcell_slow_1p08V_125C) { max_transition : 2.5074; capacitance : 0.00283326; rise_capacitance : 0.0028799; - rise_capacitance_range (0.0028799, 0.0028799); + rise_capacitance_range (0.0026808, 0.00304963); fall_capacitance : 0.00277497; - fall_capacitance_range (0.00277497, 0.00277497); + fall_capacitance_range (0.00260953, 0.00294117); timing () { related_pin : "CLK"; timing_type : min_pulse_width; @@ -27724,11 +27806,12 @@ library (sg13g2_stdcell_slow_1p08V_125C) { max_transition : 2.5074; capacitance : 0.00187534; rise_capacitance : 0.00190447; - rise_capacitance_range (0.00190447, 0.00190447); + rise_capacitance_range (0.00174127, 0.00200793); fall_capacitance : 0.00184621; - fall_capacitance_range (0.00184621, 0.00184621); + fall_capacitance_range (0.00170625, 0.00193834); timing () { related_pin : "CLK"; + sdf_edges : both_edges; timing_type : hold_rising; rise_constraint (CONSTRAINT_4x4) { index_1 ("0.0186, 0.51636, 1.263, 2.5074"); @@ -27753,6 +27836,7 @@ library (sg13g2_stdcell_slow_1p08V_125C) { } timing () { related_pin : "CLK"; + sdf_edges : both_edges; timing_type : setup_rising; rise_constraint (CONSTRAINT_4x4) { index_1 ("0.0186, 0.51636, 1.263, 2.5074"); @@ -27827,9 +27911,10 @@ library (sg13g2_stdcell_slow_1p08V_125C) { rise_capacitance : 0.0016314; rise_capacitance_range (0.0016314, 0.0016314); fall_capacitance : 0.0016314; - fall_capacitance_range (0.0016314, 0.0016314); + fall_capacitance_range (0.00155518, 0.00171159); timing () { related_pin : "CLK"; + sdf_edges : both_edges; timing_type : recovery_rising; rise_constraint (CONSTRAINT_4x4) { index_1 ("0.0186, 0.51636, 1.263, 2.5074"); @@ -27844,6 +27929,7 @@ library (sg13g2_stdcell_slow_1p08V_125C) { } timing () { related_pin : "CLK"; + sdf_edges : both_edges; timing_type : removal_rising; rise_constraint (CONSTRAINT_4x4) { index_1 ("0.0186, 0.51636, 1.263, 2.5074"); @@ -27873,11 +27959,12 @@ library (sg13g2_stdcell_slow_1p08V_125C) { max_transition : 2.5074; capacitance : 0.00183755; rise_capacitance : 0.00186116; - rise_capacitance_range (0.00186116, 0.00186116); + rise_capacitance_range (0.00170229, 0.00203755); fall_capacitance : 0.00181393; - fall_capacitance_range (0.00181393, 0.00181393); + fall_capacitance_range (0.00167411, 0.00200273); timing () { related_pin : "CLK"; + sdf_edges : both_edges; timing_type : hold_rising; rise_constraint (CONSTRAINT_4x4) { index_1 ("0.0186, 0.51636, 1.263, 2.5074"); @@ -27902,6 +27989,7 @@ library (sg13g2_stdcell_slow_1p08V_125C) { } timing () { related_pin : "CLK"; + sdf_edges : both_edges; timing_type : setup_rising; rise_constraint (CONSTRAINT_4x4) { index_1 ("0.0186, 0.51636, 1.263, 2.5074"); @@ -27975,11 +28063,12 @@ library (sg13g2_stdcell_slow_1p08V_125C) { max_transition : 2.5074; capacitance : 0.00333703; rise_capacitance : 0.00364441; - rise_capacitance_range (0.00364441, 0.00364441); + rise_capacitance_range (0.00351442, 0.00397945); fall_capacitance : 0.00302966; - fall_capacitance_range (0.00302966, 0.00302966); + fall_capacitance_range (0.00302966, 0.00391338); timing () { related_pin : "CLK"; + sdf_edges : both_edges; timing_type : hold_rising; rise_constraint (CONSTRAINT_4x4) { index_1 ("0.0186, 0.51636, 1.263, 2.5074"); @@ -28004,6 +28093,7 @@ library (sg13g2_stdcell_slow_1p08V_125C) { } timing () { related_pin : "CLK"; + sdf_edges : both_edges; timing_type : setup_rising; rise_constraint (CONSTRAINT_4x4) { index_1 ("0.0186, 0.51636, 1.263, 2.5074"); @@ -28108,9 +28198,10 @@ library (sg13g2_stdcell_slow_1p08V_125C) { rise_capacitance : 0.00493068; rise_capacitance_range (0.00493068, 0.00493068); fall_capacitance : 0.00493068; - fall_capacitance_range (0.00493068, 0.00493068); + fall_capacitance_range (0.00470063, 0.00516164); timing () { related_pin : "CLK"; + sdf_edges : both_edges; timing_type : recovery_rising; rise_constraint (CONSTRAINT_4x4) { index_1 ("0.0186, 0.51636, 1.263, 2.5074"); @@ -28125,6 +28216,7 @@ library (sg13g2_stdcell_slow_1p08V_125C) { } timing () { related_pin : "CLK"; + sdf_edges : both_edges; timing_type : removal_rising; rise_constraint (CONSTRAINT_4x4) { index_1 ("0.0186, 0.51636, 1.263, 2.5074"); @@ -28139,6 +28231,7 @@ library (sg13g2_stdcell_slow_1p08V_125C) { } timing () { related_pin : "RESET_B"; + sdf_edges : both_edges; timing_type : non_seq_hold_rising; rise_constraint (CONSTRAINT_4x4) { index_1 ("0.0186, 0.51636, 1.263, 2.5074"); @@ -28153,6 +28246,7 @@ library (sg13g2_stdcell_slow_1p08V_125C) { } timing () { related_pin : "RESET_B"; + sdf_edges : both_edges; timing_type : non_seq_setup_rising; rise_constraint (CONSTRAINT_4x4) { index_1 ("0.0186, 0.51636, 1.263, 2.5074"); @@ -28177,12 +28271,12 @@ library (sg13g2_stdcell_slow_1p08V_125C) { } } ff (IQ,IQN) { - clear : "RESET_B'"; + clear : "!RESET_B"; clear_preset_var1 : "H"; clear_preset_var2 : "L"; clocked_on : "CLK"; - next_state : "(SCE*SCD)+(SCE'*D)"; - preset : "SET_B'"; + next_state : "(SCE*SCD)+(!SCE*D)"; + preset : "!SET_B"; } test_cell () { pin (Q) { @@ -28216,12 +28310,12 @@ library (sg13g2_stdcell_slow_1p08V_125C) { direction : input; } ff (IQ,IQN) { - clear : "RESET_B'"; + clear : "!RESET_B"; clear_preset_var1 : H; clear_preset_var2 : L; clocked_on : "CLK"; next_state : "D"; - preset : "SET_B'"; + preset : "!SET_B"; } } } @@ -28286,7 +28380,7 @@ library (sg13g2_stdcell_slow_1p08V_125C) { when : "CLK&!D&RESET_B&!SCD&SCE&!Q&Q_N"; } leakage_power () { - value : 3870.08; + value : 3870.07; when : "CLK&!D&RESET_B&!SCD&SCE&Q&!Q_N"; } leakage_power () { @@ -28305,6 +28399,7 @@ library (sg13g2_stdcell_slow_1p08V_125C) { timing () { related_pin : "CLK"; sdf_cond : "SCE == 1'b1"; + sdf_edges : start_edge; timing_sense : non_unate; timing_type : rising_edge; when : "SCE"; @@ -28312,8 +28407,8 @@ library (sg13g2_stdcell_slow_1p08V_125C) { index_1 ("0.0186, 0.0966, 0.174, 0.3294, 0.6408, 1.263, 2.5074"); index_2 ("0.001, 0.0234, 0.039, 0.0648, 0.108, 0.18, 0.3"); values ( \ - "0.294156, 0.386382, 0.453605, 0.565876, 0.753826, 1.06741, 1.58984", \ - "0.33809, 0.430176, 0.497758, 0.610246, 0.79785, 1.11144, 1.63376", \ + "0.294119, 0.386179, 0.453855, 0.565929, 0.753903, 1.0672, 1.58942", \ + "0.33809, 0.430176, 0.497759, 0.610246, 0.797852, 1.11147, 1.63376", \ "0.372171, 0.464398, 0.532001, 0.643957, 0.832149, 1.14636, 1.66763", \ "0.42667, 0.518635, 0.586172, 0.698362, 0.886304, 1.19965, 1.72436", \ "0.504965, 0.596871, 0.664562, 0.776772, 0.964657, 1.27789, 1.80023", \ @@ -28325,20 +28420,20 @@ library (sg13g2_stdcell_slow_1p08V_125C) { index_1 ("0.0186, 0.0966, 0.174, 0.3294, 0.6408, 1.263, 2.5074"); index_2 ("0.001, 0.0234, 0.039, 0.0648, 0.108, 0.18, 0.3"); values ( \ - "0.0313298, 0.160763, 0.257388, 0.418067, 0.687192, 1.13528, 1.88266", \ - "0.0313308, 0.1608, 0.257446, 0.418099, 0.687193, 1.13529, 1.88292", \ - "0.0313318, 0.160801, 0.257498, 0.418565, 0.687194, 1.1358, 1.88293", \ - "0.0313741, 0.160802, 0.257499, 0.418566, 0.687195, 1.13674, 1.88521", \ - "0.0314032, 0.16082, 0.257508, 0.418567, 0.687196, 1.13675, 1.88522", \ - "0.031628, 0.160821, 0.257509, 0.418568, 0.687197, 1.13676, 1.88523", \ - "0.032356, 0.160865, 0.25751, 0.418569, 0.687198, 1.13677, 1.88524" \ + "0.0312777, 0.160778, 0.257454, 0.417728, 0.686646, 1.13529, 1.88234", \ + "0.0313053, 0.1608, 0.257455, 0.418099, 0.686647, 1.1353, 1.88292", \ + "0.0313063, 0.160801, 0.257498, 0.418565, 0.686828, 1.1358, 1.88293", \ + "0.0313741, 0.160802, 0.257499, 0.418566, 0.686829, 1.13674, 1.88521", \ + "0.0314032, 0.16082, 0.257508, 0.418567, 0.686833, 1.13675, 1.88522", \ + "0.031628, 0.160821, 0.257509, 0.418568, 0.686834, 1.13676, 1.88523", \ + "0.032356, 0.160865, 0.25751, 0.418569, 0.686835, 1.13677, 1.88524" \ ); } cell_fall (TIMING_DELAY_7x7ds1) { index_1 ("0.0186, 0.0966, 0.174, 0.3294, 0.6408, 1.263, 2.5074"); index_2 ("0.001, 0.0234, 0.039, 0.0648, 0.108, 0.18, 0.3"); values ( \ - "0.269703, 0.354181, 0.411773, 0.506806, 0.665883, 0.931231, 1.37324", \ + "0.269734, 0.354149, 0.411754, 0.506829, 0.665901, 0.931223, 1.37324", \ "0.313702, 0.398206, 0.45572, 0.550798, 0.709991, 0.975232, 1.41729", \ "0.348019, 0.432429, 0.490056, 0.585132, 0.744239, 1.00942, 1.45244", \ "0.401293, 0.485682, 0.54319, 0.638319, 0.797378, 1.06253, 1.50463", \ @@ -28351,11 +28446,11 @@ library (sg13g2_stdcell_slow_1p08V_125C) { index_1 ("0.0186, 0.0966, 0.174, 0.3294, 0.6408, 1.263, 2.5074"); index_2 ("0.001, 0.0234, 0.039, 0.0648, 0.108, 0.18, 0.3"); values ( \ - "0.0258499, 0.130518, 0.207023, 0.334642, 0.548339, 0.904959, 1.49945", \ - "0.0258509, 0.130519, 0.207166, 0.334643, 0.54838, 0.90496, 1.49946", \ - "0.0258519, 0.13052, 0.207167, 0.334644, 0.548535, 0.905078, 1.50036", \ - "0.0258525, 0.130525, 0.207168, 0.334645, 0.548606, 0.905079, 1.50037", \ - "0.0258823, 0.130526, 0.207169, 0.334646, 0.548607, 0.905407, 1.50038", \ + "0.0258348, 0.130514, 0.207046, 0.334643, 0.54834, 0.904959, 1.49958", \ + "0.0258449, 0.130515, 0.207166, 0.334644, 0.54838, 0.90496, 1.49959", \ + "0.0258459, 0.130516, 0.207167, 0.334645, 0.548535, 0.905078, 1.50036", \ + "0.0258525, 0.130525, 0.207168, 0.334646, 0.548606, 0.905079, 1.50037", \ + "0.0258823, 0.130526, 0.207169, 0.334647, 0.548607, 0.905407, 1.50038", \ "0.0258833, 0.130527, 0.20717, 0.334673, 0.548608, 0.905408, 1.50039", \ "0.0258843, 0.130528, 0.207187, 0.334674, 0.548609, 0.905409, 1.5004" \ ); @@ -28363,14 +28458,15 @@ library (sg13g2_stdcell_slow_1p08V_125C) { } timing () { related_pin : "CLK"; + sdf_edges : start_edge; timing_sense : non_unate; timing_type : rising_edge; cell_rise (TIMING_DELAY_7x7ds1) { index_1 ("0.0186, 0.0966, 0.174, 0.3294, 0.6408, 1.263, 2.5074"); index_2 ("0.001, 0.0234, 0.039, 0.0648, 0.108, 0.18, 0.3"); values ( \ - "0.294156, 0.386382, 0.453605, 0.565876, 0.753826, 1.06741, 1.58984", \ - "0.33809, 0.430176, 0.497758, 0.610246, 0.79785, 1.11144, 1.63376", \ + "0.294119, 0.386179, 0.453855, 0.565929, 0.753903, 1.0672, 1.58942", \ + "0.33809, 0.430176, 0.497759, 0.610246, 0.797852, 1.11147, 1.63376", \ "0.372171, 0.464398, 0.532001, 0.643957, 0.832149, 1.14636, 1.66763", \ "0.42667, 0.518635, 0.586172, 0.698362, 0.886304, 1.19965, 1.72436", \ "0.504965, 0.596871, 0.664562, 0.776772, 0.964657, 1.27789, 1.80023", \ @@ -28382,20 +28478,20 @@ library (sg13g2_stdcell_slow_1p08V_125C) { index_1 ("0.0186, 0.0966, 0.174, 0.3294, 0.6408, 1.263, 2.5074"); index_2 ("0.001, 0.0234, 0.039, 0.0648, 0.108, 0.18, 0.3"); values ( \ - "0.0313298, 0.160763, 0.257388, 0.418067, 0.687192, 1.13528, 1.88266", \ - "0.0313308, 0.1608, 0.257446, 0.418099, 0.687193, 1.13529, 1.88292", \ - "0.0313318, 0.160801, 0.257498, 0.418565, 0.687194, 1.1358, 1.88293", \ - "0.0313741, 0.160802, 0.257499, 0.418566, 0.687195, 1.13674, 1.88521", \ - "0.0314032, 0.16082, 0.257508, 0.418567, 0.687196, 1.13675, 1.88522", \ - "0.031628, 0.160821, 0.257509, 0.418568, 0.687197, 1.13676, 1.88523", \ - "0.032356, 0.160865, 0.25751, 0.418569, 0.687198, 1.13677, 1.88524" \ + "0.0312777, 0.160778, 0.257454, 0.417728, 0.686646, 1.13529, 1.88234", \ + "0.0313053, 0.1608, 0.257455, 0.418099, 0.686647, 1.1353, 1.88292", \ + "0.0313063, 0.160801, 0.257498, 0.418565, 0.686828, 1.1358, 1.88293", \ + "0.0313741, 0.160802, 0.257499, 0.418566, 0.686829, 1.13674, 1.88521", \ + "0.0314032, 0.16082, 0.257508, 0.418567, 0.686833, 1.13675, 1.88522", \ + "0.031628, 0.160821, 0.257509, 0.418568, 0.686834, 1.13676, 1.88523", \ + "0.032356, 0.160865, 0.25751, 0.418569, 0.686835, 1.13677, 1.88524" \ ); } cell_fall (TIMING_DELAY_7x7ds1) { index_1 ("0.0186, 0.0966, 0.174, 0.3294, 0.6408, 1.263, 2.5074"); index_2 ("0.001, 0.0234, 0.039, 0.0648, 0.108, 0.18, 0.3"); values ( \ - "0.269703, 0.354181, 0.411773, 0.506806, 0.665883, 0.931231, 1.37324", \ + "0.269734, 0.354149, 0.411754, 0.506829, 0.665901, 0.931223, 1.37324", \ "0.313702, 0.398206, 0.45572, 0.550798, 0.709991, 0.975232, 1.41729", \ "0.348019, 0.432429, 0.490056, 0.585132, 0.744239, 1.00942, 1.45244", \ "0.401293, 0.485682, 0.54319, 0.638319, 0.797378, 1.06253, 1.50463", \ @@ -28408,11 +28504,11 @@ library (sg13g2_stdcell_slow_1p08V_125C) { index_1 ("0.0186, 0.0966, 0.174, 0.3294, 0.6408, 1.263, 2.5074"); index_2 ("0.001, 0.0234, 0.039, 0.0648, 0.108, 0.18, 0.3"); values ( \ - "0.0258499, 0.130518, 0.207023, 0.334642, 0.548339, 0.904959, 1.49945", \ - "0.0258509, 0.130519, 0.207166, 0.334643, 0.54838, 0.90496, 1.49946", \ - "0.0258519, 0.13052, 0.207167, 0.334644, 0.548535, 0.905078, 1.50036", \ - "0.0258525, 0.130525, 0.207168, 0.334645, 0.548606, 0.905079, 1.50037", \ - "0.0258823, 0.130526, 0.207169, 0.334646, 0.548607, 0.905407, 1.50038", \ + "0.0258348, 0.130514, 0.207046, 0.334643, 0.54834, 0.904959, 1.49958", \ + "0.0258449, 0.130515, 0.207166, 0.334644, 0.54838, 0.90496, 1.49959", \ + "0.0258459, 0.130516, 0.207167, 0.334645, 0.548535, 0.905078, 1.50036", \ + "0.0258525, 0.130525, 0.207168, 0.334646, 0.548606, 0.905079, 1.50037", \ + "0.0258823, 0.130526, 0.207169, 0.334647, 0.548607, 0.905407, 1.50038", \ "0.0258833, 0.130527, 0.20717, 0.334673, 0.548608, 0.905408, 1.50039", \ "0.0258843, 0.130528, 0.207187, 0.334674, 0.548609, 0.905409, 1.5004" \ ); @@ -28420,32 +28516,33 @@ library (sg13g2_stdcell_slow_1p08V_125C) { } timing () { related_pin : "RESET_B"; + sdf_edges : start_edge; timing_sense : positive_unate; timing_type : clear; cell_fall (TIMING_DELAY_7x7ds1) { index_1 ("0.0186, 0.0966, 0.174, 0.3294, 0.6408, 1.263, 2.5074"); index_2 ("0.001, 0.0234, 0.039, 0.0648, 0.108, 0.18, 0.3"); values ( \ - "0.379878, 0.464323, 0.523201, 0.626049, 0.813389, 1.15096, 1.74375", \ - "0.424557, 0.508838, 0.566807, 0.66614, 0.845335, 1.1708, 1.75029", \ - "0.46871, 0.552965, 0.610714, 0.708131, 0.881508, 1.1974, 1.76446", \ - "0.54384, 0.628251, 0.685858, 0.782038, 0.948729, 1.24962, 1.79612", \ - "0.662045, 0.746452, 0.803927, 0.898933, 1.06032, 1.34362, 1.85828", \ - "0.829906, 0.914066, 0.971668, 1.06678, 1.22593, 1.49619, 1.97376", \ - "1.06885, 1.15354, 1.20987, 1.30753, 1.46514, 1.73226, 2.18145" \ + "0.379907, 0.464167, 0.523008, 0.625887, 0.81324, 1.15082, 1.74361", \ + "0.424588, 0.508842, 0.566835, 0.666174, 0.845411, 1.17076, 1.75031", \ + "0.468814, 0.553142, 0.610829, 0.7082, 0.88182, 1.1976, 1.76467", \ + "0.544034, 0.628243, 0.685892, 0.781873, 0.948709, 1.24967, 1.79614", \ + "0.661886, 0.746228, 0.803853, 0.898907, 1.06034, 1.34382, 1.85841", \ + "0.829938, 0.914163, 0.971719, 1.06675, 1.22634, 1.49655, 1.97366", \ + "1.06882, 1.15201, 1.20925, 1.30685, 1.46458, 1.73085, 2.18124" \ ); } fall_transition (TIMING_DELAY_7x7ds1) { index_1 ("0.0186, 0.0966, 0.174, 0.3294, 0.6408, 1.263, 2.5074"); index_2 ("0.001, 0.0234, 0.039, 0.0648, 0.108, 0.18, 0.3"); values ( \ - "0.0254325, 0.130338, 0.20687, 0.334389, 0.548591, 0.904948, 1.4994", \ - "0.025481, 0.130339, 0.206908, 0.334463, 0.548592, 0.90495, 1.49941", \ - "0.0254843, 0.13034, 0.207069, 0.335359, 0.548593, 0.905024, 1.50057", \ - "0.0254853, 0.130347, 0.20707, 0.33536, 0.548594, 0.906439, 1.50058", \ - "0.025533, 0.130348, 0.207071, 0.335361, 0.54868, 0.90644, 1.50059", \ - "0.025659, 0.130349, 0.207072, 0.335362, 0.548681, 0.906441, 1.5006", \ - "0.025971, 0.13035, 0.207073, 0.335363, 0.548682, 0.906442, 1.50061" \ + "0.0254703, 0.130344, 0.206909, 0.334389, 0.5486, 0.904949, 1.49933", \ + "0.0254768, 0.130345, 0.206973, 0.334461, 0.548601, 0.90495, 1.49952", \ + "0.025483, 0.130346, 0.20707, 0.335376, 0.548602, 0.905073, 1.50058", \ + "0.025484, 0.130347, 0.207071, 0.335377, 0.548603, 0.90644, 1.50059", \ + "0.025528, 0.130348, 0.207072, 0.335378, 0.54862, 0.906441, 1.50214", \ + "0.025692, 0.130349, 0.207073, 0.335379, 0.548621, 0.906442, 1.50215", \ + "0.02597, 0.13035, 0.207074, 0.33538, 0.548622, 0.906443, 1.50216" \ ); } } @@ -28456,25 +28553,25 @@ library (sg13g2_stdcell_slow_1p08V_125C) { index_1 ("0.0186, 0.0966, 0.174, 0.3294, 0.6408, 1.263, 2.5074"); index_2 ("0.001, 0.0234, 0.039, 0.0648, 0.108, 0.18, 0.3"); values ( \ - "0.0233513, 0.0370636, 0.0461835, 0.0612661, 0.0864009, 0.128251, 0.197838", \ - "0.0229842, 0.0366509, 0.0458181, 0.0609147, 0.0859958, 0.127848, 0.19761", \ + "0.0233392, 0.0370227, 0.0462195, 0.0612483, 0.0863705, 0.12819, 0.197932", \ + "0.0229842, 0.0366509, 0.0458187, 0.0609147, 0.085996, 0.127851, 0.19761", \ "0.0228644, 0.0366217, 0.0457375, 0.0608734, 0.0859436, 0.127839, 0.197462", \ "0.0227876, 0.0364182, 0.0456173, 0.0607487, 0.0858271, 0.127822, 0.197672", \ "0.0230708, 0.0367106, 0.0459336, 0.0609925, 0.0862144, 0.127897, 0.198504", \ "0.0238577, 0.0374283, 0.0466152, 0.061776, 0.086957, 0.128676, 0.199059", \ - "0.0259209, 0.0394055, 0.0486246, 0.0637547, 0.0889483, 0.130966, 0.200591" \ + "0.0259209, 0.0394055, 0.0486245, 0.0637547, 0.0889483, 0.130966, 0.200591" \ ); } fall_power (POWER_7x7ds1) { index_1 ("0.0186, 0.0966, 0.174, 0.3294, 0.6408, 1.263, 2.5074"); index_2 ("0.001, 0.0234, 0.039, 0.0648, 0.108, 0.18, 0.3"); values ( \ - "0.0242382, 0.0378239, 0.046927, 0.0618893, 0.0868706, 0.12843, 0.197755", \ + "0.0242428, 0.0378119, 0.0469289, 0.0619048, 0.0868725, 0.12843, 0.197741", \ "0.0239224, 0.0374926, 0.0466148, 0.0615661, 0.0865456, 0.128106, 0.197448", \ "0.023902, 0.0375429, 0.0467128, 0.0616485, 0.086562, 0.128115, 0.197613", \ "0.0239325, 0.0375145, 0.0465913, 0.0617521, 0.0865534, 0.128089, 0.197469", \ "0.0243842, 0.0380381, 0.0471596, 0.0620744, 0.087055, 0.129732, 0.197949", \ - "0.0253022, 0.038865, 0.0480784, 0.0631326, 0.0883587, 0.12978, 0.19928", \ + "0.0253022, 0.038865, 0.0480784, 0.0631321, 0.0883587, 0.12978, 0.19928", \ "0.027366, 0.0408994, 0.0500946, 0.0651122, 0.0904051, 0.132443, 0.202165" \ ); } @@ -28485,25 +28582,25 @@ library (sg13g2_stdcell_slow_1p08V_125C) { index_1 ("0.0186, 0.0966, 0.174, 0.3294, 0.6408, 1.263, 2.5074"); index_2 ("0.001, 0.0234, 0.039, 0.0648, 0.108, 0.18, 0.3"); values ( \ - "0.0233513, 0.0370636, 0.0461835, 0.0612661, 0.0864009, 0.128251, 0.197838", \ - "0.0229842, 0.0366509, 0.0458181, 0.0609147, 0.0859958, 0.127848, 0.19761", \ + "0.0233392, 0.0370227, 0.0462195, 0.0612483, 0.0863705, 0.12819, 0.197932", \ + "0.0229842, 0.0366509, 0.0458187, 0.0609147, 0.085996, 0.127851, 0.19761", \ "0.0228644, 0.0366217, 0.0457375, 0.0608734, 0.0859436, 0.127839, 0.197462", \ "0.0227876, 0.0364182, 0.0456173, 0.0607487, 0.0858271, 0.127822, 0.197672", \ "0.0230708, 0.0367106, 0.0459336, 0.0609925, 0.0862144, 0.127897, 0.198504", \ "0.0238577, 0.0374283, 0.0466152, 0.061776, 0.086957, 0.128676, 0.199059", \ - "0.0259209, 0.0394055, 0.0486246, 0.0637547, 0.0889483, 0.130966, 0.200591" \ + "0.0259209, 0.0394055, 0.0486245, 0.0637547, 0.0889483, 0.130966, 0.200591" \ ); } fall_power (POWER_7x7ds1) { index_1 ("0.0186, 0.0966, 0.174, 0.3294, 0.6408, 1.263, 2.5074"); index_2 ("0.001, 0.0234, 0.039, 0.0648, 0.108, 0.18, 0.3"); values ( \ - "0.0242382, 0.0378239, 0.046927, 0.0618893, 0.0868706, 0.12843, 0.197755", \ + "0.0242428, 0.0378119, 0.0469289, 0.0619048, 0.0868725, 0.12843, 0.197741", \ "0.0239224, 0.0374926, 0.0466148, 0.0615661, 0.0865456, 0.128106, 0.197448", \ "0.023902, 0.0375429, 0.0467128, 0.0616485, 0.086562, 0.128115, 0.197613", \ "0.0239325, 0.0375145, 0.0465913, 0.0617521, 0.0865534, 0.128089, 0.197469", \ "0.0243842, 0.0380381, 0.0471596, 0.0620744, 0.087055, 0.129732, 0.197949", \ - "0.0253022, 0.038865, 0.0480784, 0.0631326, 0.0883587, 0.12978, 0.19928", \ + "0.0253022, 0.038865, 0.0480784, 0.0631321, 0.0883587, 0.12978, 0.19928", \ "0.027366, 0.0408994, 0.0500946, 0.0651122, 0.0904051, 0.132443, 0.202165" \ ); } @@ -28519,13 +28616,13 @@ library (sg13g2_stdcell_slow_1p08V_125C) { index_1 ("0.0186, 0.0966, 0.174, 0.3294, 0.6408, 1.263, 2.5074"); index_2 ("0.001, 0.0234, 0.039, 0.0648, 0.108, 0.18, 0.3"); values ( \ - "0.0247081, 0.0353776, 0.0426884, 0.0556031, 0.0797974, 0.124262, 0.203691", \ - "0.0244495, 0.0350657, 0.0422278, 0.0545741, 0.0772966, 0.119734, 0.196866", \ - "0.0242358, 0.0350485, 0.0420147, 0.0541353, 0.0758138, 0.11661, 0.191657", \ - "0.0240411, 0.0347155, 0.0418852, 0.053921, 0.0743378, 0.112561, 0.183963", \ - "0.0240287, 0.0347333, 0.0418078, 0.0534996, 0.0735394, 0.10866, 0.174576", \ - "0.0243343, 0.0350367, 0.0422261, 0.054095, 0.0736191, 0.106506, 0.168236", \ - "0.0254452, 0.0360473, 0.043186, 0.0551664, 0.0750512, 0.107973, 0.1626" \ + "0.0317642, 0.0424207, 0.0497246, 0.062641, 0.0868011, 0.131304, 0.210736", \ + "0.0312152, 0.0418234, 0.0489811, 0.0613312, 0.0840789, 0.126491, 0.203587", \ + "0.0309999, 0.041827, 0.0487584, 0.0608793, 0.0825725, 0.123354, 0.198402", \ + "0.0307794, 0.0414086, 0.0485502, 0.0606479, 0.0810194, 0.119297, 0.190709", \ + "0.0307511, 0.04141, 0.0484458, 0.0600922, 0.0801829, 0.115317, 0.181415", \ + "0.0310318, 0.0416888, 0.0488172, 0.0606561, 0.0800056, 0.113044, 0.174876", \ + "0.0321247, 0.0426742, 0.0497801, 0.0617706, 0.0814752, 0.114264, 0.169332" \ ); } } @@ -28538,6 +28635,7 @@ library (sg13g2_stdcell_slow_1p08V_125C) { timing () { related_pin : "CLK"; sdf_cond : "SCE == 1'b1"; + sdf_edges : start_edge; timing_sense : non_unate; timing_type : rising_edge; when : "SCE"; @@ -28545,7 +28643,7 @@ library (sg13g2_stdcell_slow_1p08V_125C) { index_1 ("0.0186, 0.0966, 0.174, 0.3294, 0.6408, 1.263, 2.5074"); index_2 ("0.001, 0.0234, 0.039, 0.0648, 0.108, 0.18, 0.3"); values ( \ - "0.206973, 0.335277, 0.405103, 0.517834, 0.705122, 1.01749, 1.53795", \ + "0.206969, 0.335286, 0.405145, 0.51791, 0.705295, 1.01749, 1.53798", \ "0.250954, 0.379342, 0.449129, 0.561726, 0.749695, 1.06192, 1.58152", \ "0.285331, 0.4135, 0.483373, 0.596124, 0.783629, 1.09608, 1.61635", \ "0.338554, 0.466991, 0.53679, 0.64936, 0.836894, 1.14933, 1.67053", \ @@ -28558,21 +28656,21 @@ library (sg13g2_stdcell_slow_1p08V_125C) { index_1 ("0.0186, 0.0966, 0.174, 0.3294, 0.6408, 1.263, 2.5074"); index_2 ("0.001, 0.0234, 0.039, 0.0648, 0.108, 0.18, 0.3"); values ( \ - "0.0397468, 0.173403, 0.264308, 0.420346, 0.686902, 1.13355, 1.87816", \ - "0.0397478, 0.173404, 0.264609, 0.42035, 0.68693, 1.13356, 1.87821", \ - "0.0397488, 0.173438, 0.26461, 0.420351, 0.686953, 1.13357, 1.87857", \ - "0.0397498, 0.173439, 0.264611, 0.420352, 0.686954, 1.13358, 1.87992", \ - "0.0398086, 0.173464, 0.264612, 0.420353, 0.686955, 1.13359, 1.87993", \ - "0.039866, 0.173539, 0.264613, 0.420354, 0.686956, 1.1336, 1.87994", \ - "0.039867, 0.173542, 0.264614, 0.420429, 0.686957, 1.13361, 1.87995" \ + "0.0397457, 0.1734, 0.26431, 0.420344, 0.686645, 1.13356, 1.87816", \ + "0.0397467, 0.173401, 0.264609, 0.42035, 0.68693, 1.13357, 1.87821", \ + "0.0397477, 0.173438, 0.26461, 0.420351, 0.686953, 1.13358, 1.87857", \ + "0.0397487, 0.173439, 0.264611, 0.420352, 0.686954, 1.13359, 1.87992", \ + "0.0398086, 0.173464, 0.264612, 0.420353, 0.686955, 1.1336, 1.87993", \ + "0.039866, 0.173539, 0.264613, 0.420354, 0.686956, 1.13361, 1.87994", \ + "0.039867, 0.173542, 0.264614, 0.420429, 0.686957, 1.13362, 1.87995" \ ); } cell_fall (TIMING_DELAY_7x7ds1) { index_1 ("0.0186, 0.0966, 0.174, 0.3294, 0.6408, 1.263, 2.5074"); index_2 ("0.001, 0.0234, 0.039, 0.0648, 0.108, 0.18, 0.3"); values ( \ - "0.218946, 0.360028, 0.425044, 0.524142, 0.684795, 0.95119, 1.39489", \ - "0.262851, 0.403876, 0.468908, 0.567879, 0.728854, 0.995194, 1.43883", \ + "0.218926, 0.359942, 0.425006, 0.52404, 0.684891, 0.951326, 1.3949", \ + "0.262851, 0.403876, 0.468908, 0.567879, 0.728855, 0.995244, 1.43883", \ "0.297107, 0.438085, 0.50312, 0.602115, 0.762971, 1.02935, 1.47331", \ "0.351503, 0.492607, 0.557675, 0.656644, 0.817458, 1.08399, 1.52762", \ "0.429714, 0.570763, 0.635857, 0.735033, 0.895877, 1.16229, 1.60592", \ @@ -28584,11 +28682,11 @@ library (sg13g2_stdcell_slow_1p08V_125C) { index_1 ("0.0186, 0.0966, 0.174, 0.3294, 0.6408, 1.263, 2.5074"); index_2 ("0.001, 0.0234, 0.039, 0.0648, 0.108, 0.18, 0.3"); values ( \ - "0.049408, 0.164814, 0.232243, 0.350711, 0.558654, 0.913943, 1.50934", \ - "0.0494133, 0.164815, 0.232244, 0.350712, 0.558655, 0.913944, 1.50936", \ - "0.0494598, 0.164832, 0.232245, 0.350713, 0.558656, 0.91401, 1.50937", \ - "0.049736, 0.164884, 0.232327, 0.350714, 0.559008, 0.914838, 1.50938", \ - "0.0502133, 0.164973, 0.232404, 0.350715, 0.559009, 0.914839, 1.5101", \ + "0.0494125, 0.164812, 0.232092, 0.350715, 0.558641, 0.913437, 1.50934", \ + "0.0494133, 0.164813, 0.232226, 0.350716, 0.558642, 0.913652, 1.50936", \ + "0.0494598, 0.164832, 0.232227, 0.350717, 0.558643, 0.91401, 1.50937", \ + "0.049736, 0.164884, 0.232327, 0.350718, 0.559008, 0.914838, 1.50938", \ + "0.0502133, 0.164973, 0.232404, 0.350719, 0.559009, 0.914839, 1.5101", \ "0.052032, 0.165542, 0.232647, 0.350807, 0.55901, 0.91484, 1.51011", \ "0.057257, 0.167196, 0.233421, 0.351349, 0.559011, 0.914841, 1.51012" \ ); @@ -28596,13 +28694,14 @@ library (sg13g2_stdcell_slow_1p08V_125C) { } timing () { related_pin : "CLK"; + sdf_edges : start_edge; timing_sense : non_unate; timing_type : rising_edge; cell_rise (TIMING_DELAY_7x7ds1) { index_1 ("0.0186, 0.0966, 0.174, 0.3294, 0.6408, 1.263, 2.5074"); index_2 ("0.001, 0.0234, 0.039, 0.0648, 0.108, 0.18, 0.3"); values ( \ - "0.206973, 0.335277, 0.405103, 0.517834, 0.705122, 1.01749, 1.53795", \ + "0.206969, 0.335286, 0.405145, 0.51791, 0.705295, 1.01749, 1.53798", \ "0.250954, 0.379342, 0.449129, 0.561726, 0.749695, 1.06192, 1.58152", \ "0.285331, 0.4135, 0.483373, 0.596124, 0.783629, 1.09608, 1.61635", \ "0.338554, 0.466991, 0.53679, 0.64936, 0.836894, 1.14933, 1.67053", \ @@ -28615,21 +28714,21 @@ library (sg13g2_stdcell_slow_1p08V_125C) { index_1 ("0.0186, 0.0966, 0.174, 0.3294, 0.6408, 1.263, 2.5074"); index_2 ("0.001, 0.0234, 0.039, 0.0648, 0.108, 0.18, 0.3"); values ( \ - "0.0397468, 0.173403, 0.264308, 0.420346, 0.686902, 1.13355, 1.87816", \ - "0.0397478, 0.173404, 0.264609, 0.42035, 0.68693, 1.13356, 1.87821", \ - "0.0397488, 0.173438, 0.26461, 0.420351, 0.686953, 1.13357, 1.87857", \ - "0.0397498, 0.173439, 0.264611, 0.420352, 0.686954, 1.13358, 1.87992", \ - "0.0398086, 0.173464, 0.264612, 0.420353, 0.686955, 1.13359, 1.87993", \ - "0.039866, 0.173539, 0.264613, 0.420354, 0.686956, 1.1336, 1.87994", \ - "0.039867, 0.173542, 0.264614, 0.420429, 0.686957, 1.13361, 1.87995" \ + "0.0397457, 0.1734, 0.26431, 0.420344, 0.686645, 1.13356, 1.87816", \ + "0.0397467, 0.173401, 0.264609, 0.42035, 0.68693, 1.13357, 1.87821", \ + "0.0397477, 0.173438, 0.26461, 0.420351, 0.686953, 1.13358, 1.87857", \ + "0.0397487, 0.173439, 0.264611, 0.420352, 0.686954, 1.13359, 1.87992", \ + "0.0398086, 0.173464, 0.264612, 0.420353, 0.686955, 1.1336, 1.87993", \ + "0.039866, 0.173539, 0.264613, 0.420354, 0.686956, 1.13361, 1.87994", \ + "0.039867, 0.173542, 0.264614, 0.420429, 0.686957, 1.13362, 1.87995" \ ); } cell_fall (TIMING_DELAY_7x7ds1) { index_1 ("0.0186, 0.0966, 0.174, 0.3294, 0.6408, 1.263, 2.5074"); index_2 ("0.001, 0.0234, 0.039, 0.0648, 0.108, 0.18, 0.3"); values ( \ - "0.218946, 0.360028, 0.425044, 0.524142, 0.684795, 0.95119, 1.39489", \ - "0.262851, 0.403876, 0.468908, 0.567879, 0.728854, 0.995194, 1.43883", \ + "0.218926, 0.359942, 0.425006, 0.52404, 0.684891, 0.951326, 1.3949", \ + "0.262851, 0.403876, 0.468908, 0.567879, 0.728855, 0.995244, 1.43883", \ "0.297107, 0.438085, 0.50312, 0.602115, 0.762971, 1.02935, 1.47331", \ "0.351503, 0.492607, 0.557675, 0.656644, 0.817458, 1.08399, 1.52762", \ "0.429714, 0.570763, 0.635857, 0.735033, 0.895877, 1.16229, 1.60592", \ @@ -28641,11 +28740,11 @@ library (sg13g2_stdcell_slow_1p08V_125C) { index_1 ("0.0186, 0.0966, 0.174, 0.3294, 0.6408, 1.263, 2.5074"); index_2 ("0.001, 0.0234, 0.039, 0.0648, 0.108, 0.18, 0.3"); values ( \ - "0.049408, 0.164814, 0.232243, 0.350711, 0.558654, 0.913943, 1.50934", \ - "0.0494133, 0.164815, 0.232244, 0.350712, 0.558655, 0.913944, 1.50936", \ - "0.0494598, 0.164832, 0.232245, 0.350713, 0.558656, 0.91401, 1.50937", \ - "0.049736, 0.164884, 0.232327, 0.350714, 0.559008, 0.914838, 1.50938", \ - "0.0502133, 0.164973, 0.232404, 0.350715, 0.559009, 0.914839, 1.5101", \ + "0.0494125, 0.164812, 0.232092, 0.350715, 0.558641, 0.913437, 1.50934", \ + "0.0494133, 0.164813, 0.232226, 0.350716, 0.558642, 0.913652, 1.50936", \ + "0.0494598, 0.164832, 0.232227, 0.350717, 0.558643, 0.91401, 1.50937", \ + "0.049736, 0.164884, 0.232327, 0.350718, 0.559008, 0.914838, 1.50938", \ + "0.0502133, 0.164973, 0.232404, 0.350719, 0.559009, 0.914839, 1.5101", \ "0.052032, 0.165542, 0.232647, 0.350807, 0.55901, 0.91484, 1.51011", \ "0.057257, 0.167196, 0.233421, 0.351349, 0.559011, 0.914841, 1.51012" \ ); @@ -28653,32 +28752,33 @@ library (sg13g2_stdcell_slow_1p08V_125C) { } timing () { related_pin : "RESET_B"; + sdf_edges : start_edge; timing_sense : negative_unate; timing_type : preset; cell_rise (TIMING_DELAY_7x7ds1) { index_1 ("0.0186, 0.0966, 0.174, 0.3294, 0.6408, 1.263, 2.5074"); index_2 ("0.001, 0.0234, 0.039, 0.0648, 0.108, 0.18, 0.3"); values ( \ - "0.318144, 0.442972, 0.512444, 0.624892, 0.812564, 1.12469, 1.64499", \ - "0.36273, 0.487434, 0.556868, 0.66945, 0.857074, 1.16935, 1.68957", \ - "0.406912, 0.531481, 0.600911, 0.713464, 0.901108, 1.21337, 1.73382", \ - "0.482113, 0.606845, 0.676108, 0.789027, 0.976594, 1.28878, 1.80875", \ - "0.600043, 0.725014, 0.794234, 0.906687, 1.09448, 1.40696, 1.92661", \ - "0.767312, 0.8926, 0.961902, 1.07467, 1.26205, 1.57475, 2.09504", \ - "1.00523, 1.13245, 1.20082, 1.31561, 1.50066, 1.81512, 2.33454" \ + "0.318085, 0.442753, 0.512259, 0.624798, 0.812434, 1.12454, 1.64482", \ + "0.362652, 0.48728, 0.556753, 0.669417, 0.857011, 1.16923, 1.68952", \ + "0.406578, 0.531402, 0.600785, 0.713379, 0.901067, 1.21335, 1.73364", \ + "0.48211, 0.606597, 0.675957, 0.788623, 0.976167, 1.28842, 1.80831", \ + "0.600126, 0.724812, 0.794382, 0.906941, 1.09461, 1.40703, 1.92718", \ + "0.767795, 0.893413, 0.962214, 1.07459, 1.26254, 1.57482, 2.09431", \ + "1.00717, 1.13201, 1.20095, 1.31353, 1.50315, 1.81577, 2.3352" \ ); } rise_transition (TIMING_DELAY_7x7ds1) { index_1 ("0.0186, 0.0966, 0.174, 0.3294, 0.6408, 1.263, 2.5074"); index_2 ("0.001, 0.0234, 0.039, 0.0648, 0.108, 0.18, 0.3"); values ( \ - "0.0402041, 0.170678, 0.26242, 0.419637, 0.686891, 1.13351, 1.87813", \ - "0.0402051, 0.170686, 0.262421, 0.4198, 0.686892, 1.13352, 1.87814", \ - "0.0402061, 0.170687, 0.262422, 0.419801, 0.686893, 1.13353, 1.87848", \ - "0.0402787, 0.170713, 0.262427, 0.419802, 0.686894, 1.13354, 1.87849", \ - "0.040711, 0.170809, 0.262428, 0.419803, 0.686895, 1.13355, 1.87906", \ - "0.041871, 0.171076, 0.262575, 0.419804, 0.686896, 1.13356, 1.87907", \ - "0.044064, 0.171657, 0.262898, 0.419805, 0.686897, 1.13357, 1.87908" \ + "0.0401634, 0.170699, 0.262416, 0.419637, 0.686566, 1.1335, 1.87813", \ + "0.0401644, 0.17073, 0.262417, 0.419794, 0.686873, 1.13351, 1.87814", \ + "0.0401654, 0.170731, 0.262418, 0.419795, 0.686874, 1.13352, 1.87848", \ + "0.0402584, 0.170732, 0.262419, 0.419796, 0.686875, 1.13353, 1.87849", \ + "0.040725, 0.170803, 0.26242, 0.419797, 0.686876, 1.13354, 1.87881", \ + "0.04192, 0.171046, 0.262575, 0.419798, 0.686877, 1.13355, 1.87882", \ + "0.044274, 0.171737, 0.262855, 0.419799, 0.686878, 1.13356, 1.87883" \ ); } } @@ -28689,21 +28789,21 @@ library (sg13g2_stdcell_slow_1p08V_125C) { index_1 ("0.0186, 0.0966, 0.174, 0.3294, 0.6408, 1.263, 2.5074"); index_2 ("0.001, 0.0234, 0.039, 0.0648, 0.108, 0.18, 0.3"); values ( \ - "0.024234, 0.0378789, 0.0470579, 0.0620988, 0.0872147, 0.129002, 0.19872", \ + "0.0242335, 0.0378802, 0.047046, 0.0621167, 0.0871987, 0.129002, 0.198725", \ "0.0239256, 0.0376741, 0.0467546, 0.0617869, 0.0869398, 0.12874, 0.198422", \ "0.0239138, 0.0376106, 0.0468082, 0.0618077, 0.0869204, 0.128677, 0.198409", \ "0.0239584, 0.0375719, 0.0467297, 0.0619594, 0.0870374, 0.128717, 0.198584", \ "0.0244187, 0.0380823, 0.0472652, 0.0622653, 0.0874444, 0.129161, 0.19955", \ "0.0252944, 0.0389285, 0.0480754, 0.0632546, 0.0884255, 0.130082, 0.200474", \ - "0.0273778, 0.0409673, 0.0501884, 0.0652722, 0.0904053, 0.132545, 0.20201" \ + "0.0273778, 0.0409672, 0.0501884, 0.0652722, 0.0904053, 0.132545, 0.20201" \ ); } fall_power (POWER_7x7ds1) { index_1 ("0.0186, 0.0966, 0.174, 0.3294, 0.6408, 1.263, 2.5074"); index_2 ("0.001, 0.0234, 0.039, 0.0648, 0.108, 0.18, 0.3"); values ( \ - "0.0233255, 0.0369535, 0.0460986, 0.0610943, 0.0860293, 0.127615, 0.19696", \ - "0.0229946, 0.0366911, 0.0456897, 0.0606873, 0.0856772, 0.127205, 0.196583", \ + "0.0233259, 0.036947, 0.0460877, 0.061062, 0.0860385, 0.127596, 0.196973", \ + "0.0229946, 0.0366912, 0.0456898, 0.0606873, 0.0856771, 0.127209, 0.196539", \ "0.0228679, 0.0365428, 0.0457764, 0.0608438, 0.0856017, 0.127178, 0.196577", \ "0.0227999, 0.036364, 0.0454925, 0.0606792, 0.0855545, 0.12718, 0.19634", \ "0.0230815, 0.0366914, 0.0459004, 0.0608293, 0.0857736, 0.128488, 0.196722", \ @@ -28718,21 +28818,21 @@ library (sg13g2_stdcell_slow_1p08V_125C) { index_1 ("0.0186, 0.0966, 0.174, 0.3294, 0.6408, 1.263, 2.5074"); index_2 ("0.001, 0.0234, 0.039, 0.0648, 0.108, 0.18, 0.3"); values ( \ - "0.024234, 0.0378789, 0.0470579, 0.0620988, 0.0872147, 0.129002, 0.19872", \ + "0.0242335, 0.0378802, 0.047046, 0.0621167, 0.0871987, 0.129002, 0.198725", \ "0.0239256, 0.0376741, 0.0467546, 0.0617869, 0.0869398, 0.12874, 0.198422", \ "0.0239138, 0.0376106, 0.0468082, 0.0618077, 0.0869204, 0.128677, 0.198409", \ "0.0239584, 0.0375719, 0.0467297, 0.0619594, 0.0870374, 0.128717, 0.198584", \ "0.0244187, 0.0380823, 0.0472652, 0.0622653, 0.0874444, 0.129161, 0.19955", \ "0.0252944, 0.0389285, 0.0480754, 0.0632546, 0.0884255, 0.130082, 0.200474", \ - "0.0273778, 0.0409673, 0.0501884, 0.0652722, 0.0904053, 0.132545, 0.20201" \ + "0.0273778, 0.0409672, 0.0501884, 0.0652722, 0.0904053, 0.132545, 0.20201" \ ); } fall_power (POWER_7x7ds1) { index_1 ("0.0186, 0.0966, 0.174, 0.3294, 0.6408, 1.263, 2.5074"); index_2 ("0.001, 0.0234, 0.039, 0.0648, 0.108, 0.18, 0.3"); values ( \ - "0.0233255, 0.0369535, 0.0460986, 0.0610943, 0.0860293, 0.127615, 0.19696", \ - "0.0229946, 0.0366911, 0.0456897, 0.0606873, 0.0856772, 0.127205, 0.196583", \ + "0.0233259, 0.036947, 0.0460877, 0.061062, 0.0860385, 0.127596, 0.196973", \ + "0.0229946, 0.0366912, 0.0456898, 0.0606873, 0.0856771, 0.127209, 0.196539", \ "0.0228679, 0.0365428, 0.0457764, 0.0608438, 0.0856017, 0.127178, 0.196577", \ "0.0227999, 0.036364, 0.0454925, 0.0606792, 0.0855545, 0.12718, 0.19634", \ "0.0230815, 0.0366914, 0.0459004, 0.0608293, 0.0857736, 0.128488, 0.196722", \ @@ -28747,13 +28847,13 @@ library (sg13g2_stdcell_slow_1p08V_125C) { index_1 ("0.0186, 0.0966, 0.174, 0.3294, 0.6408, 1.263, 2.5074"); index_2 ("0.001, 0.0234, 0.039, 0.0648, 0.108, 0.18, 0.3"); values ( \ - "0.0247182, 0.035472, 0.0428434, 0.0558259, 0.0800898, 0.124795, 0.204424", \ - "0.0244386, 0.0351462, 0.0423529, 0.0547933, 0.0776824, 0.120286, 0.197636", \ - "0.0242374, 0.0349596, 0.0421667, 0.0542258, 0.0761575, 0.117083, 0.192443", \ - "0.0240582, 0.0347998, 0.0420093, 0.0538381, 0.0751923, 0.113011, 0.184856", \ - "0.0240384, 0.0347862, 0.0418974, 0.0537564, 0.0739298, 0.109202, 0.175571", \ - "0.0243408, 0.035083, 0.0423466, 0.0541969, 0.0736901, 0.107345, 0.166966", \ - "0.0254459, 0.036076, 0.043353, 0.0553101, 0.0752333, 0.108057, 0.163297" \ + "0.0287289, 0.0394625, 0.046824, 0.0598427, 0.0840752, 0.128806, 0.208437", \ + "0.0285884, 0.039301, 0.0465051, 0.0589492, 0.0818313, 0.124449, 0.201783", \ + "0.0283623, 0.039103, 0.0464489, 0.0583719, 0.0802985, 0.121195, 0.196623", \ + "0.0282192, 0.0389656, 0.0461722, 0.0580104, 0.0795484, 0.117246, 0.189018", \ + "0.0282767, 0.0390211, 0.0461416, 0.0578991, 0.0779953, 0.113397, 0.1798", \ + "0.0288893, 0.0396641, 0.0468681, 0.0587178, 0.0781772, 0.111696, 0.171417", \ + "0.0306806, 0.041215, 0.0484874, 0.0604337, 0.0802642, 0.11316, 0.168531" \ ); } fall_power (scalar) { @@ -28769,9 +28869,9 @@ library (sg13g2_stdcell_slow_1p08V_125C) { max_transition : 2.5074; capacitance : 0.00274803; rise_capacitance : 0.002793; - rise_capacitance_range (0.002793, 0.002793); + rise_capacitance_range (0.00258026, 0.00297026); fall_capacitance : 0.00269021; - fall_capacitance_range (0.00269021, 0.00269021); + fall_capacitance_range (0.00251552, 0.00285873); timing () { related_pin : "CLK"; timing_type : min_pulse_width; @@ -28787,13 +28887,13 @@ library (sg13g2_stdcell_slow_1p08V_125C) { rise_power (passive_POWER_7x1ds1) { index_1 ("0.0186, 0.0966, 0.174, 0.3294, 0.6408, 1.263, 2.5074"); values ( \ - "0.00892536, 0.00855627, 0.00851673, 0.00850277, 0.00886079, 0.00960149, 0.0115641" \ + "0.00892186, 0.00855628, 0.00851673, 0.00850278, 0.0088608, 0.00960149, 0.0115641" \ ); } fall_power (passive_POWER_7x1ds1) { index_1 ("0.0186, 0.0966, 0.174, 0.3294, 0.6408, 1.263, 2.5074"); values ( \ - "0.00862354, 0.00828685, 0.00822542, 0.00828908, 0.00859614, 0.00932844, 0.0112045" \ + "0.00862092, 0.00828685, 0.00822542, 0.00828908, 0.00859614, 0.00932844, 0.0112045" \ ); } } @@ -28821,7 +28921,7 @@ library (sg13g2_stdcell_slow_1p08V_125C) { fall_power (passive_POWER_7x1ds1) { index_1 ("0.0186, 0.0966, 0.174, 0.3294, 0.6408, 1.263, 2.5074"); values ( \ - "0.015379, 0.0150963, 0.0150515, 0.0151714, 0.0155744, 0.0163411, 0.0183564" \ + "0.015379, 0.0150974, 0.0150515, 0.0151714, 0.0155744, 0.0163411, 0.0183549" \ ); } } @@ -28830,13 +28930,13 @@ library (sg13g2_stdcell_slow_1p08V_125C) { rise_power (passive_POWER_7x1ds1) { index_1 ("0.0186, 0.0966, 0.174, 0.3294, 0.6408, 1.263, 2.5074"); values ( \ - "0.0088079, 0.0084294, 0.00841498, 0.00837897, 0.00874968, 0.00949189, 0.0114749" \ + "0.00881463, 0.00842939, 0.00841496, 0.00837897, 0.00874967, 0.00949189, 0.0114749" \ ); } fall_power (passive_POWER_7x1ds1) { index_1 ("0.0186, 0.0966, 0.174, 0.3294, 0.6408, 1.263, 2.5074"); values ( \ - "0.00847399, 0.00814364, 0.00808774, 0.00815059, 0.00845981, 0.00918341, 0.0110637" \ + "0.00847399, 0.00814363, 0.00808774, 0.00815059, 0.00845981, 0.00918341, 0.0110637" \ ); } } @@ -28845,13 +28945,13 @@ library (sg13g2_stdcell_slow_1p08V_125C) { rise_power (passive_POWER_7x1ds1) { index_1 ("0.0186, 0.0966, 0.174, 0.3294, 0.6408, 1.263, 2.5074"); values ( \ - "0.0089245, 0.00855178, 0.00852264, 0.0085037, 0.00886102, 0.0096016, 0.0115647" \ + "0.0089251, 0.00855177, 0.00852264, 0.00850369, 0.00886102, 0.0096016, 0.0115647" \ ); } fall_power (passive_POWER_7x1ds1) { index_1 ("0.0186, 0.0966, 0.174, 0.3294, 0.6408, 1.263, 2.5074"); values ( \ - "0.00862807, 0.00828905, 0.00823209, 0.00828918, 0.00859622, 0.00932853, 0.0112046" \ + "0.00862697, 0.00828906, 0.00823199, 0.00828918, 0.00859622, 0.00932853, 0.0112046" \ ); } } @@ -28860,13 +28960,13 @@ library (sg13g2_stdcell_slow_1p08V_125C) { rise_power (passive_POWER_7x1ds1) { index_1 ("0.0186, 0.0966, 0.174, 0.3294, 0.6408, 1.263, 2.5074"); values ( \ - "0.000409456, 4.39926e-05, 1.12067e-05, -6.96328e-07, 0.000349301, 0.00108486, 0.00305267" \ + "0.000396713, 4.39896e-05, 1.12037e-05, -6.99344e-07, 0.000349298, 0.00108485, 0.00305267" \ ); } fall_power (passive_POWER_7x1ds1) { index_1 ("0.0186, 0.0966, 0.174, 0.3294, 0.6408, 1.263, 2.5074"); values ( \ - "0.000935634, 0.000607425, 0.00055175, 0.000614932, 0.000914234, 0.00164545, 0.00351089" \ + "0.000935642, 0.000607437, 0.000551753, 0.000614934, 0.000914236, 0.00164546, 0.00351089" \ ); } } @@ -28875,13 +28975,13 @@ library (sg13g2_stdcell_slow_1p08V_125C) { rise_power (passive_POWER_7x1ds1) { index_1 ("0.0186, 0.0966, 0.174, 0.3294, 0.6408, 1.263, 2.5074"); values ( \ - "0.00885342, 0.00847991, 0.00844117, 0.00841282, 0.00878343, 0.0095256, 0.0115091" \ + "0.00885335, 0.0084799, 0.00844116, 0.00841282, 0.00878343, 0.0095256, 0.0115091" \ ); } fall_power (passive_POWER_7x1ds1) { index_1 ("0.0186, 0.0966, 0.174, 0.3294, 0.6408, 1.263, 2.5074"); values ( \ - "0.00858692, 0.00825341, 0.00819917, 0.00826282, 0.008572, 0.00929564, 0.0111755" \ + "0.00858694, 0.00825313, 0.00819918, 0.00826283, 0.00857201, 0.00929565, 0.0111755" \ ); } } @@ -28889,13 +28989,13 @@ library (sg13g2_stdcell_slow_1p08V_125C) { rise_power (passive_POWER_7x1ds1) { index_1 ("0.0186, 0.0966, 0.174, 0.3294, 0.6408, 1.263, 2.5074"); values ( \ - "0.0088079, 0.0084294, 0.00841498, 0.00837897, 0.00874968, 0.00949189, 0.0114749" \ + "0.00881463, 0.00842939, 0.00841496, 0.00837897, 0.00874967, 0.00949189, 0.0114749" \ ); } fall_power (passive_POWER_7x1ds1) { index_1 ("0.0186, 0.0966, 0.174, 0.3294, 0.6408, 1.263, 2.5074"); values ( \ - "0.00862807, 0.00828905, 0.00823209, 0.00828918, 0.00859622, 0.00932853, 0.0112046" \ + "0.00862697, 0.00828906, 0.00823199, 0.00828918, 0.00859622, 0.00932853, 0.0112046" \ ); } } @@ -28906,11 +29006,12 @@ library (sg13g2_stdcell_slow_1p08V_125C) { max_transition : 2.5074; capacitance : 0.0025946; rise_capacitance : 0.00262695; - rise_capacitance_range (0.00262695, 0.00262695); + rise_capacitance_range (0.00233633, 0.00284892); fall_capacitance : 0.00256225; - fall_capacitance_range (0.00256225, 0.00256225); + fall_capacitance_range (0.00226636, 0.00274656); timing () { related_pin : "CLK"; + sdf_edges : both_edges; timing_type : hold_rising; rise_constraint (CONSTRAINT_4x4) { index_1 ("0.0186, 0.51636, 1.263, 2.5074"); @@ -28926,7 +29027,7 @@ library (sg13g2_stdcell_slow_1p08V_125C) { index_1 ("0.0186, 0.51636, 1.263, 2.5074"); index_2 ("0.0186, 0.51636, 1.263, 2.5074"); values ( \ - "-0.217622, -0.0726254, 0.0318604, 0.142185", \ + "-0.217622, -0.0701296, 0.0318604, 0.142185", \ "-0.386606, -0.239367, -0.135398, -0.0241433", \ "-0.517926, -0.37335, -0.269836, -0.156906", \ "-0.657573, -0.514661, -0.413734, -0.301057" \ @@ -28935,12 +29036,13 @@ library (sg13g2_stdcell_slow_1p08V_125C) { } timing () { related_pin : "CLK"; + sdf_edges : both_edges; timing_type : setup_rising; rise_constraint (CONSTRAINT_4x4) { index_1 ("0.0186, 0.51636, 1.263, 2.5074"); index_2 ("0.0186, 0.51636, 1.263, 2.5074"); values ( \ - "0.32032, 0.224871, 0.173882, 0.114159", \ + "0.32032, 0.224871, 0.17131, 0.114159", \ "0.491431, 0.394701, 0.342569, 0.285298", \ "0.613082, 0.517582, 0.466817, 0.408327", \ "0.741222, 0.643863, 0.594531, 0.534228" \ @@ -28962,13 +29064,13 @@ library (sg13g2_stdcell_slow_1p08V_125C) { rise_power (passive_POWER_7x1ds1) { index_1 ("0.0186, 0.0966, 0.174, 0.3294, 0.6408, 1.263, 2.5074"); values ( \ - "0.0169512, 0.0167139, 0.016604, 0.0165502, 0.0167442, 0.0174011, 0.0190695" \ + "0.0169511, 0.0167139, 0.016604, 0.0165502, 0.0167442, 0.0174011, 0.0190695" \ ); } fall_power (passive_POWER_7x1ds1) { index_1 ("0.0186, 0.0966, 0.174, 0.3294, 0.6408, 1.263, 2.5074"); values ( \ - "0.022822, 0.0225384, 0.02247, 0.0225038, 0.0228032, 0.0235291, 0.0252463" \ + "0.0228127, 0.0225384, 0.02247, 0.0225038, 0.0228032, 0.0235291, 0.0252463" \ ); } } @@ -28976,13 +29078,13 @@ library (sg13g2_stdcell_slow_1p08V_125C) { rise_power (passive_POWER_7x1ds1) { index_1 ("0.0186, 0.0966, 0.174, 0.3294, 0.6408, 1.263, 2.5074"); values ( \ - "0.0169512, 0.0167139, 0.016604, 0.0165502, 0.0167442, 0.0174011, 0.0190695" \ + "0.0169511, 0.0167139, 0.016604, 0.0165502, 0.0167442, 0.0174011, 0.0190695" \ ); } fall_power (passive_POWER_7x1ds1) { index_1 ("0.0186, 0.0966, 0.174, 0.3294, 0.6408, 1.263, 2.5074"); values ( \ - "0.022822, 0.0225384, 0.02247, 0.0225038, 0.0228032, 0.0235291, 0.0252463" \ + "0.0228127, 0.0225384, 0.02247, 0.0225038, 0.0228032, 0.0235291, 0.0252463" \ ); } } @@ -28990,13 +29092,14 @@ library (sg13g2_stdcell_slow_1p08V_125C) { pin (RESET_B) { direction : input; max_transition : 2.5074; - capacitance : 0.00520246; - rise_capacitance : 0.00520246; - rise_capacitance_range (0.00520246, 0.00520246); - fall_capacitance : 0.00520246; - fall_capacitance_range (0.00520246, 0.00520246); + capacitance : 0.00498428; + rise_capacitance : 0.00498428; + rise_capacitance_range (0.00498428, 0.00498428); + fall_capacitance : 0.00498428; + fall_capacitance_range (0.00451626, 0.00534159); timing () { related_pin : "CLK"; + sdf_edges : both_edges; timing_type : recovery_rising; rise_constraint (CONSTRAINT_4x4) { index_1 ("0.0186, 0.51636, 1.263, 2.5074"); @@ -29011,12 +29114,13 @@ library (sg13g2_stdcell_slow_1p08V_125C) { } timing () { related_pin : "CLK"; + sdf_edges : both_edges; timing_type : removal_rising; rise_constraint (CONSTRAINT_4x4) { index_1 ("0.0186, 0.51636, 1.263, 2.5074"); index_2 ("0.0186, 0.51636, 1.263, 2.5074"); values ( \ - "-0.173609, -0.0876004, -0.0350059, 0.0261555", \ + "-0.173609, -0.0876004, -0.0350059, 0.0234572", \ "-0.364144, -0.267378, -0.214071, -0.156095", \ "-0.541072, -0.436287, -0.377771, -0.317928", \ "-0.746619, -0.638366, -0.577581, -0.513568" \ @@ -29040,17 +29144,18 @@ library (sg13g2_stdcell_slow_1p08V_125C) { max_transition : 2.5074; capacitance : 0.00270864; rise_capacitance : 0.00273028; - rise_capacitance_range (0.00273028, 0.00273028); + rise_capacitance_range (0.00243947, 0.00295089); fall_capacitance : 0.00266537; - fall_capacitance_range (0.00266537, 0.00266537); + fall_capacitance_range (0.00237286, 0.00284951); timing () { related_pin : "CLK"; + sdf_edges : both_edges; timing_type : hold_rising; rise_constraint (CONSTRAINT_4x4) { index_1 ("0.0186, 0.51636, 1.263, 2.5074"); index_2 ("0.0186, 0.51636, 1.263, 2.5074"); values ( \ - "-0.227403, -0.1475, -0.0967285, -0.0386052", \ + "-0.227403, -0.1475, -0.0967285, -0.0359068", \ "-0.39659, -0.320854, -0.266519, -0.208326", \ "-0.517926, -0.441532, -0.391263, -0.332053", \ "-0.646779, -0.569641, -0.521082, -0.46044" \ @@ -29069,13 +29174,14 @@ library (sg13g2_stdcell_slow_1p08V_125C) { } timing () { related_pin : "CLK"; + sdf_edges : both_edges; timing_type : setup_rising; rise_constraint (CONSTRAINT_4x4) { index_1 ("0.0186, 0.51636, 1.263, 2.5074"); index_2 ("0.0186, 0.51636, 1.263, 2.5074"); values ( \ - "0.32032, 0.224871, 0.17131, 0.114159", \ - "0.491431, 0.394701, 0.342569, 0.285298", \ + "0.32032, 0.224871, 0.173882, 0.114159", \ + "0.493927, 0.394701, 0.342569, 0.285298", \ "0.615654, 0.517582, 0.466817, 0.408327", \ "0.74392, 0.646612, 0.597356, 0.53718" \ ); @@ -29102,7 +29208,7 @@ library (sg13g2_stdcell_slow_1p08V_125C) { fall_power (passive_POWER_7x1ds1) { index_1 ("0.0186, 0.0966, 0.174, 0.3294, 0.6408, 1.263, 2.5074"); values ( \ - "0.00741839, 0.00714317, 0.00707395, 0.00711727, 0.00740846, 0.00814438, 0.00986381" \ + "0.00742095, 0.00714317, 0.00707395, 0.00711727, 0.00740846, 0.00814438, 0.00986381" \ ); } } @@ -29116,7 +29222,7 @@ library (sg13g2_stdcell_slow_1p08V_125C) { fall_power (passive_POWER_7x1ds1) { index_1 ("0.0186, 0.0966, 0.174, 0.3294, 0.6408, 1.263, 2.5074"); values ( \ - "0.00741839, 0.00714317, 0.00707395, 0.00711727, 0.00740846, 0.00814438, 0.00986381" \ + "0.00742095, 0.00714317, 0.00707395, 0.00711727, 0.00740846, 0.00814438, 0.00986381" \ ); } } @@ -29127,11 +29233,12 @@ library (sg13g2_stdcell_slow_1p08V_125C) { max_transition : 2.5074; capacitance : 0.00438664; rise_capacitance : 0.00448755; - rise_capacitance_range (0.00448755, 0.00448755); + rise_capacitance_range (0.00414095, 0.00484533); fall_capacitance : 0.00428574; - fall_capacitance_range (0.00428574, 0.00428574); + fall_capacitance_range (0.00413309, 0.00475281); timing () { related_pin : "CLK"; + sdf_edges : both_edges; timing_type : hold_rising; rise_constraint (CONSTRAINT_4x4) { index_1 ("0.0186, 0.51636, 1.263, 2.5074"); @@ -29156,6 +29263,7 @@ library (sg13g2_stdcell_slow_1p08V_125C) { } timing () { related_pin : "CLK"; + sdf_edges : both_edges; timing_type : setup_rising; rise_constraint (CONSTRAINT_4x4) { index_1 ("0.0186, 0.51636, 1.263, 2.5074"); @@ -29198,7 +29306,7 @@ library (sg13g2_stdcell_slow_1p08V_125C) { rise_power (passive_POWER_7x1ds1) { index_1 ("0.0186, 0.0966, 0.174, 0.3294, 0.6408, 1.263, 2.5074"); values ( \ - "0.0205506, 0.020279, 0.0202018, 0.0202174, 0.0205607, 0.0216227, 0.0242679" \ + "0.0205504, 0.0202794, 0.0202018, 0.0202174, 0.0205607, 0.0216227, 0.0242679" \ ); } fall_power (passive_POWER_7x1ds1) { @@ -29212,7 +29320,7 @@ library (sg13g2_stdcell_slow_1p08V_125C) { rise_power (passive_POWER_7x1ds1) { index_1 ("0.0186, 0.0966, 0.174, 0.3294, 0.6408, 1.263, 2.5074"); values ( \ - "0.0205506, 0.020279, 0.0202018, 0.0202174, 0.0205607, 0.0216227, 0.0242679" \ + "0.0205504, 0.0202794, 0.0202018, 0.0202174, 0.0205607, 0.0216227, 0.0242679" \ ); } fall_power (passive_POWER_7x1ds1) { @@ -29224,9 +29332,9 @@ library (sg13g2_stdcell_slow_1p08V_125C) { } } ff (IQ,IQN) { - clear : "RESET_B'"; + clear : "!RESET_B"; clocked_on : "CLK"; - next_state : "(SCE*SCD)+(SCE'*D)"; + next_state : "(SCE*SCD)+(!SCE*D)"; } test_cell () { pin (Q) { @@ -29257,7 +29365,7 @@ library (sg13g2_stdcell_slow_1p08V_125C) { signal_type : test_scan_enable; } ff (IQ,IQN) { - clear : "RESET_B'"; + clear : "!RESET_B"; clocked_on : "CLK"; next_state : "D"; } @@ -29343,6 +29451,7 @@ library (sg13g2_stdcell_slow_1p08V_125C) { timing () { related_pin : "CLK"; sdf_cond : "SCE == 1'b1"; + sdf_edges : start_edge; timing_sense : non_unate; timing_type : rising_edge; when : "SCE"; @@ -29350,8 +29459,8 @@ library (sg13g2_stdcell_slow_1p08V_125C) { index_1 ("0.0186, 0.0966, 0.174, 0.3294, 0.6408, 1.263, 2.5074"); index_2 ("0.001, 0.0468, 0.078, 0.1296, 0.216, 0.36, 0.6"); values ( \ - "0.375344, 0.459977, 0.525733, 0.636978, 0.824594, 1.13781, 1.66051", \ - "0.419279, 0.503952, 0.569806, 0.680926, 0.868488, 1.1818, 1.70412", \ + "0.375423, 0.459911, 0.525613, 0.636979, 0.824598, 1.13786, 1.66042", \ + "0.419278, 0.503952, 0.569806, 0.680926, 0.868488, 1.1818, 1.70412", \ "0.453764, 0.538442, 0.604101, 0.715443, 0.902847, 1.21627, 1.73896", \ "0.508169, 0.593034, 0.658808, 0.770023, 0.957415, 1.27082, 1.79342", \ "0.586026, 0.670889, 0.736703, 0.847726, 1.03518, 1.3483, 1.87103", \ @@ -29363,20 +29472,20 @@ library (sg13g2_stdcell_slow_1p08V_125C) { index_1 ("0.0186, 0.0966, 0.174, 0.3294, 0.6408, 1.263, 2.5074"); index_2 ("0.001, 0.0468, 0.078, 0.1296, 0.216, 0.36, 0.6"); values ( \ - "0.0354944, 0.163211, 0.258925, 0.419226, 0.688475, 1.13773, 1.88596", \ - "0.0354954, 0.163233, 0.258926, 0.419283, 0.688599, 1.13774, 1.88634", \ - "0.0354964, 0.163257, 0.259029, 0.41951, 0.688875, 1.13775, 1.88635", \ - "0.0355132, 0.163258, 0.25903, 0.419511, 0.688876, 1.13848, 1.88636", \ - "0.0355142, 0.163259, 0.259037, 0.419512, 0.688877, 1.13849, 1.88637", \ - "0.035593, 0.163281, 0.259038, 0.419513, 0.688878, 1.1385, 1.88638", \ - "0.035863, 0.163282, 0.259039, 0.419514, 0.688879, 1.13851, 1.88639" \ + "0.0355121, 0.163254, 0.259048, 0.419226, 0.688475, 1.13773, 1.88572", \ + "0.0355131, 0.163255, 0.259049, 0.419283, 0.688599, 1.13774, 1.88634", \ + "0.0355141, 0.163257, 0.25905, 0.41951, 0.688875, 1.13775, 1.88635", \ + "0.0355151, 0.163258, 0.259051, 0.419511, 0.688876, 1.13848, 1.88636", \ + "0.0355161, 0.163259, 0.259052, 0.419512, 0.688877, 1.13849, 1.88637", \ + "0.035593, 0.163281, 0.259053, 0.419513, 0.688878, 1.1385, 1.88638", \ + "0.035863, 0.163282, 0.259054, 0.419514, 0.688879, 1.13851, 1.88639" \ ); } cell_fall (TIMING_DELAY_7x7ds1) { index_1 ("0.0186, 0.0966, 0.174, 0.3294, 0.6408, 1.263, 2.5074"); index_2 ("0.001, 0.0468, 0.078, 0.1296, 0.216, 0.36, 0.6"); values ( \ - "0.32723, 0.411299, 0.468507, 0.563427, 0.723285, 0.98952, 1.43362", \ + "0.327239, 0.411296, 0.468478, 0.563562, 0.723267, 0.98952, 1.43362", \ "0.371165, 0.455223, 0.512415, 0.607625, 0.767006, 1.03347, 1.4775", \ "0.405324, 0.489206, 0.546374, 0.641415, 0.801215, 1.06758, 1.51151", \ "0.459164, 0.54314, 0.600309, 0.695349, 0.855055, 1.12135, 1.56534", \ @@ -29389,26 +29498,27 @@ library (sg13g2_stdcell_slow_1p08V_125C) { index_1 ("0.0186, 0.0966, 0.174, 0.3294, 0.6408, 1.263, 2.5074"); index_2 ("0.001, 0.0468, 0.078, 0.1296, 0.216, 0.36, 0.6"); values ( \ - "0.0302845, 0.135904, 0.211722, 0.339321, 0.554011, 0.912358, 1.50955", \ - "0.0302855, 0.135905, 0.211725, 0.339386, 0.554012, 0.912936, 1.50962", \ - "0.0302865, 0.135916, 0.211884, 0.339387, 0.554218, 0.912937, 1.50985", \ - "0.0302875, 0.135917, 0.211885, 0.339388, 0.554219, 0.91396, 1.51047", \ - "0.0302885, 0.135918, 0.211886, 0.339389, 0.55422, 0.913961, 1.51048", \ - "0.0302895, 0.135919, 0.211887, 0.33939, 0.554221, 0.913962, 1.51049", \ - "0.0302905, 0.13592, 0.211888, 0.339398, 0.554222, 0.913963, 1.5105" \ + "0.0301375, 0.135904, 0.211697, 0.339335, 0.554012, 0.912358, 1.50955", \ + "0.0301385, 0.135905, 0.211725, 0.339386, 0.554013, 0.912937, 1.50962", \ + "0.030228, 0.135916, 0.211884, 0.339387, 0.554218, 0.912938, 1.50985", \ + "0.0302386, 0.135917, 0.211885, 0.339388, 0.554219, 0.91396, 1.51047", \ + "0.030271, 0.135918, 0.211886, 0.339389, 0.55422, 0.913961, 1.51048", \ + "0.030272, 0.135919, 0.211887, 0.33939, 0.554221, 0.913962, 1.51049", \ + "0.030273, 0.13592, 0.211888, 0.339398, 0.554222, 0.913963, 1.5105" \ ); } } timing () { related_pin : "CLK"; + sdf_edges : start_edge; timing_sense : non_unate; timing_type : rising_edge; cell_rise (TIMING_DELAY_7x7ds1) { index_1 ("0.0186, 0.0966, 0.174, 0.3294, 0.6408, 1.263, 2.5074"); index_2 ("0.001, 0.0468, 0.078, 0.1296, 0.216, 0.36, 0.6"); values ( \ - "0.375344, 0.459977, 0.525733, 0.636978, 0.824594, 1.13781, 1.66051", \ - "0.419279, 0.503952, 0.569806, 0.680926, 0.868488, 1.1818, 1.70412", \ + "0.375423, 0.459911, 0.525613, 0.636979, 0.824598, 1.13786, 1.66042", \ + "0.419278, 0.503952, 0.569806, 0.680926, 0.868488, 1.1818, 1.70412", \ "0.453764, 0.538442, 0.604101, 0.715443, 0.902847, 1.21627, 1.73896", \ "0.508169, 0.593034, 0.658808, 0.770023, 0.957415, 1.27082, 1.79342", \ "0.586026, 0.670889, 0.736703, 0.847726, 1.03518, 1.3483, 1.87103", \ @@ -29420,20 +29530,20 @@ library (sg13g2_stdcell_slow_1p08V_125C) { index_1 ("0.0186, 0.0966, 0.174, 0.3294, 0.6408, 1.263, 2.5074"); index_2 ("0.001, 0.0468, 0.078, 0.1296, 0.216, 0.36, 0.6"); values ( \ - "0.0354944, 0.163211, 0.258925, 0.419226, 0.688475, 1.13773, 1.88596", \ - "0.0354954, 0.163233, 0.258926, 0.419283, 0.688599, 1.13774, 1.88634", \ - "0.0354964, 0.163257, 0.259029, 0.41951, 0.688875, 1.13775, 1.88635", \ - "0.0355132, 0.163258, 0.25903, 0.419511, 0.688876, 1.13848, 1.88636", \ - "0.0355142, 0.163259, 0.259037, 0.419512, 0.688877, 1.13849, 1.88637", \ - "0.035593, 0.163281, 0.259038, 0.419513, 0.688878, 1.1385, 1.88638", \ - "0.035863, 0.163282, 0.259039, 0.419514, 0.688879, 1.13851, 1.88639" \ + "0.0355121, 0.163254, 0.259048, 0.419226, 0.688475, 1.13773, 1.88572", \ + "0.0355131, 0.163255, 0.259049, 0.419283, 0.688599, 1.13774, 1.88634", \ + "0.0355141, 0.163257, 0.25905, 0.41951, 0.688875, 1.13775, 1.88635", \ + "0.0355151, 0.163258, 0.259051, 0.419511, 0.688876, 1.13848, 1.88636", \ + "0.0355161, 0.163259, 0.259052, 0.419512, 0.688877, 1.13849, 1.88637", \ + "0.035593, 0.163281, 0.259053, 0.419513, 0.688878, 1.1385, 1.88638", \ + "0.035863, 0.163282, 0.259054, 0.419514, 0.688879, 1.13851, 1.88639" \ ); } cell_fall (TIMING_DELAY_7x7ds1) { index_1 ("0.0186, 0.0966, 0.174, 0.3294, 0.6408, 1.263, 2.5074"); index_2 ("0.001, 0.0468, 0.078, 0.1296, 0.216, 0.36, 0.6"); values ( \ - "0.32723, 0.411299, 0.468507, 0.563427, 0.723285, 0.98952, 1.43362", \ + "0.327239, 0.411296, 0.468478, 0.563562, 0.723267, 0.98952, 1.43362", \ "0.371165, 0.455223, 0.512415, 0.607625, 0.767006, 1.03347, 1.4775", \ "0.405324, 0.489206, 0.546374, 0.641415, 0.801215, 1.06758, 1.51151", \ "0.459164, 0.54314, 0.600309, 0.695349, 0.855055, 1.12135, 1.56534", \ @@ -29446,44 +29556,45 @@ library (sg13g2_stdcell_slow_1p08V_125C) { index_1 ("0.0186, 0.0966, 0.174, 0.3294, 0.6408, 1.263, 2.5074"); index_2 ("0.001, 0.0468, 0.078, 0.1296, 0.216, 0.36, 0.6"); values ( \ - "0.0302845, 0.135904, 0.211722, 0.339321, 0.554011, 0.912358, 1.50955", \ - "0.0302855, 0.135905, 0.211725, 0.339386, 0.554012, 0.912936, 1.50962", \ - "0.0302865, 0.135916, 0.211884, 0.339387, 0.554218, 0.912937, 1.50985", \ - "0.0302875, 0.135917, 0.211885, 0.339388, 0.554219, 0.91396, 1.51047", \ - "0.0302885, 0.135918, 0.211886, 0.339389, 0.55422, 0.913961, 1.51048", \ - "0.0302895, 0.135919, 0.211887, 0.33939, 0.554221, 0.913962, 1.51049", \ - "0.0302905, 0.13592, 0.211888, 0.339398, 0.554222, 0.913963, 1.5105" \ + "0.0301375, 0.135904, 0.211697, 0.339335, 0.554012, 0.912358, 1.50955", \ + "0.0301385, 0.135905, 0.211725, 0.339386, 0.554013, 0.912937, 1.50962", \ + "0.030228, 0.135916, 0.211884, 0.339387, 0.554218, 0.912938, 1.50985", \ + "0.0302386, 0.135917, 0.211885, 0.339388, 0.554219, 0.91396, 1.51047", \ + "0.030271, 0.135918, 0.211886, 0.339389, 0.55422, 0.913961, 1.51048", \ + "0.030272, 0.135919, 0.211887, 0.33939, 0.554221, 0.913962, 1.51049", \ + "0.030273, 0.13592, 0.211888, 0.339398, 0.554222, 0.913963, 1.5105" \ ); } } timing () { related_pin : "RESET_B"; + sdf_edges : start_edge; timing_sense : positive_unate; timing_type : clear; cell_fall (TIMING_DELAY_7x7ds1) { index_1 ("0.0186, 0.0966, 0.174, 0.3294, 0.6408, 1.263, 2.5074"); index_2 ("0.001, 0.0468, 0.078, 0.1296, 0.216, 0.36, 0.6"); values ( \ - "0.439003, 0.52304, 0.581186, 0.683315, 0.868369, 1.20356, 1.79476", \ - "0.483701, 0.567666, 0.625253, 0.72398, 0.901615, 1.22493, 1.80313", \ - "0.528015, 0.612054, 0.669434, 0.766601, 0.939341, 1.25328, 1.81918", \ - "0.603418, 0.687669, 0.745026, 0.840848, 1.00757, 1.30776, 1.8537", \ - "0.721168, 0.805054, 0.862191, 0.957752, 1.11978, 1.40319, 1.91783", \ - "0.889079, 0.973486, 1.03075, 1.12592, 1.28593, 1.55696, 2.035", \ - "1.13185, 1.21321, 1.26963, 1.36714, 1.52532, 1.79256, 2.24534" \ + "0.43919, 0.523246, 0.581454, 0.683173, 0.868575, 1.20372, 1.7951", \ + "0.483691, 0.567574, 0.625239, 0.723958, 0.901604, 1.22498, 1.80311", \ + "0.52784, 0.611775, 0.669276, 0.766438, 0.939047, 1.25307, 1.81907", \ + "0.603428, 0.687855, 0.744927, 0.840941, 1.00744, 1.3077, 1.85376", \ + "0.721369, 0.80521, 0.862551, 0.957634, 1.11945, 1.40311, 1.91778", \ + "0.889, 0.973428, 1.03077, 1.12583, 1.28559, 1.55675, 2.03418", \ + "1.13012, 1.21499, 1.2708, 1.36594, 1.52603, 1.79433, 2.24447" \ ); } fall_transition (TIMING_DELAY_7x7ds1) { index_1 ("0.0186, 0.0966, 0.174, 0.3294, 0.6408, 1.263, 2.5074"); index_2 ("0.001, 0.0468, 0.078, 0.1296, 0.216, 0.36, 0.6"); values ( \ - "0.0295999, 0.135728, 0.211552, 0.339187, 0.554305, 0.91223, 1.50948", \ - "0.0296678, 0.135888, 0.211558, 0.33927, 0.554306, 0.912743, 1.50949", \ - "0.0296688, 0.135889, 0.211559, 0.339801, 0.554307, 0.912744, 1.5095", \ - "0.0296698, 0.13589, 0.21156, 0.339802, 0.554308, 0.913357, 1.51079", \ - "0.0296708, 0.135891, 0.211665, 0.339803, 0.554309, 0.913358, 1.5108", \ - "0.02977, 0.135892, 0.211666, 0.339804, 0.55431, 0.913359, 1.51081", \ - "0.029931, 0.135893, 0.211667, 0.339805, 0.554311, 0.91336, 1.51082" \ + "0.0296059, 0.13573, 0.211597, 0.339231, 0.554294, 0.913026, 1.50933", \ + "0.0296693, 0.13574, 0.211598, 0.339269, 0.554295, 0.913027, 1.50937", \ + "0.0296703, 0.135741, 0.211599, 0.339797, 0.554511, 0.913028, 1.50947", \ + "0.0296713, 0.135742, 0.2116, 0.339798, 0.554512, 0.913397, 1.51083", \ + "0.0296723, 0.135743, 0.21171, 0.339799, 0.554513, 0.913398, 1.51084", \ + "0.029769, 0.135798, 0.211711, 0.3398, 0.554514, 0.913399, 1.51085", \ + "0.029904, 0.135811, 0.211712, 0.339801, 0.554515, 0.9134, 1.51086" \ ); } } @@ -29494,8 +29605,8 @@ library (sg13g2_stdcell_slow_1p08V_125C) { index_1 ("0.0186, 0.0966, 0.174, 0.3294, 0.6408, 1.263, 2.5074"); index_2 ("0.001, 0.0468, 0.078, 0.1296, 0.216, 0.36, 0.6"); values ( \ - "0.0291977, 0.0569511, 0.0753238, 0.105481, 0.155857, 0.239532, 0.378955", \ - "0.0288353, 0.056564, 0.0749374, 0.105114, 0.155444, 0.239135, 0.37857", \ + "0.0291972, 0.0569593, 0.0753177, 0.105481, 0.155856, 0.239537, 0.378776", \ + "0.0288348, 0.056564, 0.0749374, 0.10511, 0.155444, 0.239134, 0.37857", \ "0.0287244, 0.0565392, 0.074859, 0.105086, 0.155425, 0.239033, 0.378604", \ "0.0286459, 0.0564001, 0.0748063, 0.105135, 0.155263, 0.239156, 0.378547", \ "0.0289696, 0.0566931, 0.0751209, 0.105187, 0.155752, 0.239166, 0.378946", \ @@ -29507,7 +29618,7 @@ library (sg13g2_stdcell_slow_1p08V_125C) { index_1 ("0.0186, 0.0966, 0.174, 0.3294, 0.6408, 1.263, 2.5074"); index_2 ("0.001, 0.0468, 0.078, 0.1296, 0.216, 0.36, 0.6"); values ( \ - "0.029757, 0.0576036, 0.0758511, 0.105817, 0.155775, 0.238937, 0.377597", \ + "0.0297601, 0.0576033, 0.0758259, 0.105822, 0.155782, 0.238937, 0.377597", \ "0.0294232, 0.0572868, 0.0755346, 0.105527, 0.155414, 0.238711, 0.377294", \ "0.0293926, 0.0573823, 0.0755868, 0.105458, 0.155487, 0.238589, 0.377247", \ "0.0294448, 0.0573102, 0.0755409, 0.105893, 0.155906, 0.238914, 0.377268", \ @@ -29523,8 +29634,8 @@ library (sg13g2_stdcell_slow_1p08V_125C) { index_1 ("0.0186, 0.0966, 0.174, 0.3294, 0.6408, 1.263, 2.5074"); index_2 ("0.001, 0.0468, 0.078, 0.1296, 0.216, 0.36, 0.6"); values ( \ - "0.0291977, 0.0569511, 0.0753238, 0.105481, 0.155857, 0.239532, 0.378955", \ - "0.0288353, 0.056564, 0.0749374, 0.105114, 0.155444, 0.239135, 0.37857", \ + "0.0291972, 0.0569593, 0.0753177, 0.105481, 0.155856, 0.239537, 0.378776", \ + "0.0288348, 0.056564, 0.0749374, 0.10511, 0.155444, 0.239134, 0.37857", \ "0.0287244, 0.0565392, 0.074859, 0.105086, 0.155425, 0.239033, 0.378604", \ "0.0286459, 0.0564001, 0.0748063, 0.105135, 0.155263, 0.239156, 0.378547", \ "0.0289696, 0.0566931, 0.0751209, 0.105187, 0.155752, 0.239166, 0.378946", \ @@ -29536,7 +29647,7 @@ library (sg13g2_stdcell_slow_1p08V_125C) { index_1 ("0.0186, 0.0966, 0.174, 0.3294, 0.6408, 1.263, 2.5074"); index_2 ("0.001, 0.0468, 0.078, 0.1296, 0.216, 0.36, 0.6"); values ( \ - "0.029757, 0.0576036, 0.0758511, 0.105817, 0.155775, 0.238937, 0.377597", \ + "0.0297601, 0.0576033, 0.0758259, 0.105822, 0.155782, 0.238937, 0.377597", \ "0.0294232, 0.0572868, 0.0755346, 0.105527, 0.155414, 0.238711, 0.377294", \ "0.0293926, 0.0573823, 0.0755868, 0.105458, 0.155487, 0.238589, 0.377247", \ "0.0294448, 0.0573102, 0.0755409, 0.105893, 0.155906, 0.238914, 0.377268", \ @@ -29557,13 +29668,13 @@ library (sg13g2_stdcell_slow_1p08V_125C) { index_1 ("0.0186, 0.0966, 0.174, 0.3294, 0.6408, 1.263, 2.5074"); index_2 ("0.001, 0.0468, 0.078, 0.1296, 0.216, 0.36, 0.6"); values ( \ - "0.037077, 0.0588864, 0.0733756, 0.0988038, 0.146138, 0.233638, 0.390995", \ - "0.0364875, 0.0582443, 0.0726219, 0.0970048, 0.141632, 0.225238, 0.378002", \ - "0.0363222, 0.0581224, 0.0723822, 0.096391, 0.139305, 0.219791, 0.368291", \ - "0.0361226, 0.0579615, 0.0722996, 0.0964279, 0.136854, 0.212594, 0.354399", \ - "0.0360878, 0.0578732, 0.0720744, 0.0954099, 0.135485, 0.205096, 0.336656", \ - "0.036379, 0.0581292, 0.0724479, 0.0958486, 0.134912, 0.200838, 0.324185", \ - "0.0375242, 0.0589621, 0.0733191, 0.0973043, 0.136768, 0.202209, 0.312231" \ + "0.0300328, 0.0518518, 0.0663189, 0.091728, 0.139057, 0.226757, 0.383968", \ + "0.0297214, 0.0514748, 0.065846, 0.09024, 0.134912, 0.218524, 0.371242", \ + "0.0295672, 0.0513686, 0.0656281, 0.0896493, 0.132603, 0.212883, 0.361543", \ + "0.0293964, 0.0512889, 0.0656301, 0.0894975, 0.130106, 0.205931, 0.347644", \ + "0.0293563, 0.0512721, 0.0654337, 0.0889325, 0.128918, 0.198412, 0.329928", \ + "0.0296691, 0.051516, 0.0659196, 0.0895044, 0.12861, 0.194633, 0.317608", \ + "0.0308158, 0.0524139, 0.0668267, 0.0908242, 0.130558, 0.195946, 0.305279" \ ); } } @@ -29576,6 +29687,7 @@ library (sg13g2_stdcell_slow_1p08V_125C) { timing () { related_pin : "CLK"; sdf_cond : "SCE == 1'b1"; + sdf_edges : start_edge; timing_sense : non_unate; timing_type : rising_edge; when : "SCE"; @@ -29583,7 +29695,7 @@ library (sg13g2_stdcell_slow_1p08V_125C) { index_1 ("0.0186, 0.0966, 0.174, 0.3294, 0.6408, 1.263, 2.5074"); index_2 ("0.001, 0.0468, 0.078, 0.1296, 0.216, 0.36, 0.6"); values ( \ - "0.217441, 0.36095, 0.432659, 0.546119, 0.733796, 1.04641, 1.56682", \ + "0.217358, 0.360901, 0.432589, 0.546119, 0.733826, 1.04642, 1.56687", \ "0.261282, 0.404925, 0.476564, 0.58998, 0.777946, 1.09065, 1.61086", \ "0.29552, 0.439152, 0.510829, 0.62429, 0.811954, 1.12564, 1.64496", \ "0.34892, 0.492641, 0.564306, 0.677557, 0.86551, 1.17813, 1.69819", \ @@ -29596,11 +29708,11 @@ library (sg13g2_stdcell_slow_1p08V_125C) { index_1 ("0.0186, 0.0966, 0.174, 0.3294, 0.6408, 1.263, 2.5074"); index_2 ("0.001, 0.0468, 0.078, 0.1296, 0.216, 0.36, 0.6"); values ( \ - "0.040896, 0.18108, 0.271147, 0.425068, 0.69022, 1.13678, 1.88175", \ - "0.040897, 0.181081, 0.271238, 0.42533, 0.690332, 1.1371, 1.88176", \ - "0.040898, 0.181082, 0.271239, 0.42601, 0.691464, 1.13763, 1.88177", \ - "0.040899, 0.181083, 0.27124, 0.426011, 0.691465, 1.13764, 1.88296", \ - "0.040954, 0.181084, 0.271241, 0.426012, 0.691466, 1.13765, 1.88297", \ + "0.0409443, 0.181078, 0.271158, 0.425068, 0.690045, 1.13678, 1.88178", \ + "0.0409453, 0.181079, 0.271238, 0.42533, 0.690332, 1.1371, 1.88179", \ + "0.0409463, 0.18108, 0.271239, 0.42601, 0.691464, 1.13763, 1.8818", \ + "0.0409473, 0.181081, 0.27124, 0.426011, 0.691465, 1.13764, 1.88296", \ + "0.040954, 0.181082, 0.271241, 0.426012, 0.691466, 1.13765, 1.88297", \ "0.040995, 0.181206, 0.271242, 0.426013, 0.691467, 1.13766, 1.88298", \ "0.040996, 0.181304, 0.271267, 0.426014, 0.691468, 1.13767, 1.88299" \ ); @@ -29609,8 +29721,8 @@ library (sg13g2_stdcell_slow_1p08V_125C) { index_1 ("0.0186, 0.0966, 0.174, 0.3294, 0.6408, 1.263, 2.5074"); index_2 ("0.001, 0.0468, 0.078, 0.1296, 0.216, 0.36, 0.6"); values ( \ - "0.242387, 0.403236, 0.47231, 0.574139, 0.73675, 1.00379, 1.44802", \ - "0.286456, 0.447399, 0.516371, 0.618122, 0.780715, 1.04789, 1.49194", \ + "0.242643, 0.403267, 0.472492, 0.574338, 0.73665, 1.0037, 1.44807", \ + "0.286456, 0.447399, 0.516371, 0.618122, 0.780715, 1.04775, 1.49194", \ "0.320865, 0.481803, 0.550858, 0.652651, 0.815102, 1.08292, 1.52652", \ "0.375302, 0.536292, 0.605346, 0.707215, 0.869596, 1.13687, 1.58083", \ "0.453264, 0.614103, 0.683237, 0.78527, 0.947604, 1.21466, 1.65882", \ @@ -29622,9 +29734,9 @@ library (sg13g2_stdcell_slow_1p08V_125C) { index_1 ("0.0186, 0.0966, 0.174, 0.3294, 0.6408, 1.263, 2.5074"); index_2 ("0.001, 0.0468, 0.078, 0.1296, 0.216, 0.36, 0.6"); values ( \ - "0.0541857, 0.180941, 0.248823, 0.364647, 0.569705, 0.922889, 1.51828", \ - "0.0542436, 0.180942, 0.248849, 0.364648, 0.569842, 0.922892, 1.51831", \ - "0.0542646, 0.180957, 0.248852, 0.364649, 0.570668, 0.923506, 1.51832", \ + "0.0542102, 0.180941, 0.248853, 0.364426, 0.569992, 0.922761, 1.51828", \ + "0.0542439, 0.180942, 0.248854, 0.364427, 0.569993, 0.922875, 1.51831", \ + "0.0542646, 0.180957, 0.248855, 0.364557, 0.570668, 0.923506, 1.51832", \ "0.054408, 0.181136, 0.248899, 0.364688, 0.570669, 0.923507, 1.51904", \ "0.0545323, 0.181142, 0.249004, 0.364689, 0.57067, 0.923508, 1.51905", \ "0.055466, 0.181491, 0.249196, 0.364811, 0.570671, 0.923509, 1.51906", \ @@ -29634,13 +29746,14 @@ library (sg13g2_stdcell_slow_1p08V_125C) { } timing () { related_pin : "CLK"; + sdf_edges : start_edge; timing_sense : non_unate; timing_type : rising_edge; cell_rise (TIMING_DELAY_7x7ds1) { index_1 ("0.0186, 0.0966, 0.174, 0.3294, 0.6408, 1.263, 2.5074"); index_2 ("0.001, 0.0468, 0.078, 0.1296, 0.216, 0.36, 0.6"); values ( \ - "0.217441, 0.36095, 0.432659, 0.546119, 0.733796, 1.04641, 1.56682", \ + "0.217358, 0.360901, 0.432589, 0.546119, 0.733826, 1.04642, 1.56687", \ "0.261282, 0.404925, 0.476564, 0.58998, 0.777946, 1.09065, 1.61086", \ "0.29552, 0.439152, 0.510829, 0.62429, 0.811954, 1.12564, 1.64496", \ "0.34892, 0.492641, 0.564306, 0.677557, 0.86551, 1.17813, 1.69819", \ @@ -29653,11 +29766,11 @@ library (sg13g2_stdcell_slow_1p08V_125C) { index_1 ("0.0186, 0.0966, 0.174, 0.3294, 0.6408, 1.263, 2.5074"); index_2 ("0.001, 0.0468, 0.078, 0.1296, 0.216, 0.36, 0.6"); values ( \ - "0.040896, 0.18108, 0.271147, 0.425068, 0.69022, 1.13678, 1.88175", \ - "0.040897, 0.181081, 0.271238, 0.42533, 0.690332, 1.1371, 1.88176", \ - "0.040898, 0.181082, 0.271239, 0.42601, 0.691464, 1.13763, 1.88177", \ - "0.040899, 0.181083, 0.27124, 0.426011, 0.691465, 1.13764, 1.88296", \ - "0.040954, 0.181084, 0.271241, 0.426012, 0.691466, 1.13765, 1.88297", \ + "0.0409443, 0.181078, 0.271158, 0.425068, 0.690045, 1.13678, 1.88178", \ + "0.0409453, 0.181079, 0.271238, 0.42533, 0.690332, 1.1371, 1.88179", \ + "0.0409463, 0.18108, 0.271239, 0.42601, 0.691464, 1.13763, 1.8818", \ + "0.0409473, 0.181081, 0.27124, 0.426011, 0.691465, 1.13764, 1.88296", \ + "0.040954, 0.181082, 0.271241, 0.426012, 0.691466, 1.13765, 1.88297", \ "0.040995, 0.181206, 0.271242, 0.426013, 0.691467, 1.13766, 1.88298", \ "0.040996, 0.181304, 0.271267, 0.426014, 0.691468, 1.13767, 1.88299" \ ); @@ -29666,8 +29779,8 @@ library (sg13g2_stdcell_slow_1p08V_125C) { index_1 ("0.0186, 0.0966, 0.174, 0.3294, 0.6408, 1.263, 2.5074"); index_2 ("0.001, 0.0468, 0.078, 0.1296, 0.216, 0.36, 0.6"); values ( \ - "0.242387, 0.403236, 0.47231, 0.574139, 0.73675, 1.00379, 1.44802", \ - "0.286456, 0.447399, 0.516371, 0.618122, 0.780715, 1.04789, 1.49194", \ + "0.242643, 0.403267, 0.472492, 0.574338, 0.73665, 1.0037, 1.44807", \ + "0.286456, 0.447399, 0.516371, 0.618122, 0.780715, 1.04775, 1.49194", \ "0.320865, 0.481803, 0.550858, 0.652651, 0.815102, 1.08292, 1.52652", \ "0.375302, 0.536292, 0.605346, 0.707215, 0.869596, 1.13687, 1.58083", \ "0.453264, 0.614103, 0.683237, 0.78527, 0.947604, 1.21466, 1.65882", \ @@ -29679,9 +29792,9 @@ library (sg13g2_stdcell_slow_1p08V_125C) { index_1 ("0.0186, 0.0966, 0.174, 0.3294, 0.6408, 1.263, 2.5074"); index_2 ("0.001, 0.0468, 0.078, 0.1296, 0.216, 0.36, 0.6"); values ( \ - "0.0541857, 0.180941, 0.248823, 0.364647, 0.569705, 0.922889, 1.51828", \ - "0.0542436, 0.180942, 0.248849, 0.364648, 0.569842, 0.922892, 1.51831", \ - "0.0542646, 0.180957, 0.248852, 0.364649, 0.570668, 0.923506, 1.51832", \ + "0.0542102, 0.180941, 0.248853, 0.364426, 0.569992, 0.922761, 1.51828", \ + "0.0542439, 0.180942, 0.248854, 0.364427, 0.569993, 0.922875, 1.51831", \ + "0.0542646, 0.180957, 0.248855, 0.364557, 0.570668, 0.923506, 1.51832", \ "0.054408, 0.181136, 0.248899, 0.364688, 0.570669, 0.923507, 1.51904", \ "0.0545323, 0.181142, 0.249004, 0.364689, 0.57067, 0.923508, 1.51905", \ "0.055466, 0.181491, 0.249196, 0.364811, 0.570671, 0.923509, 1.51906", \ @@ -29691,32 +29804,33 @@ library (sg13g2_stdcell_slow_1p08V_125C) { } timing () { related_pin : "RESET_B"; + sdf_edges : start_edge; timing_sense : negative_unate; timing_type : preset; cell_rise (TIMING_DELAY_7x7ds1) { index_1 ("0.0186, 0.0966, 0.174, 0.3294, 0.6408, 1.263, 2.5074"); index_2 ("0.001, 0.0468, 0.078, 0.1296, 0.216, 0.36, 0.6"); values ( \ - "0.331749, 0.471147, 0.542162, 0.655601, 0.843399, 1.15591, 1.67647", \ - "0.376321, 0.515616, 0.586664, 0.70008, 0.887961, 1.20041, 1.72108", \ - "0.420392, 0.559738, 0.630788, 0.744094, 0.932307, 1.24505, 1.76523", \ - "0.495969, 0.635211, 0.706448, 0.819809, 1.00786, 1.3205, 1.84069", \ - "0.613718, 0.752903, 0.824262, 0.937191, 1.12548, 1.43781, 1.95839", \ - "0.780862, 0.92129, 0.992204, 1.10571, 1.29353, 1.6061, 2.12691", \ - "1.02247, 1.1629, 1.23254, 1.34575, 1.53271, 1.84765, 2.36828" \ + "0.331769, 0.471213, 0.542147, 0.655423, 0.843497, 1.15597, 1.67651", \ + "0.376398, 0.515603, 0.5867, 0.700095, 0.888098, 1.20042, 1.72106", \ + "0.420505, 0.559618, 0.630873, 0.744203, 0.932161, 1.24521, 1.76486", \ + "0.495919, 0.635357, 0.706428, 0.819798, 1.00793, 1.32041, 1.84061", \ + "0.613731, 0.75313, 0.824338, 0.937505, 1.12544, 1.43786, 1.95805", \ + "0.780861, 0.92132, 0.992995, 1.10589, 1.2936, 1.6062, 2.12615", \ + "1.02068, 1.16307, 1.23256, 1.34598, 1.53269, 1.84775, 2.3673" \ ); } rise_transition (TIMING_DELAY_7x7ds1) { index_1 ("0.0186, 0.0966, 0.174, 0.3294, 0.6408, 1.263, 2.5074"); index_2 ("0.001, 0.0468, 0.078, 0.1296, 0.216, 0.36, 0.6"); values ( \ - "0.0409448, 0.178073, 0.268851, 0.424176, 0.690003, 1.13672, 1.88174", \ - "0.0409877, 0.178074, 0.268946, 0.424297, 0.690064, 1.13673, 1.88175", \ - "0.0409887, 0.178075, 0.268947, 0.424298, 0.690454, 1.13722, 1.88176", \ - "0.0412154, 0.178076, 0.268948, 0.424299, 0.690455, 1.13723, 1.88177", \ - "0.041451, 0.178256, 0.268949, 0.4243, 0.690456, 1.13724, 1.88178", \ - "0.042618, 0.178449, 0.269103, 0.424301, 0.690457, 1.13725, 1.88179", \ - "0.044671, 0.178828, 0.269411, 0.424302, 0.690458, 1.13726, 1.8818" \ + "0.0409911, 0.177989, 0.268851, 0.424119, 0.690144, 1.13674, 1.88173", \ + "0.0410377, 0.178013, 0.268962, 0.424297, 0.690145, 1.13675, 1.88175", \ + "0.0410659, 0.178086, 0.268963, 0.424298, 0.690146, 1.1372, 1.88176", \ + "0.0412007, 0.178087, 0.268964, 0.424299, 0.690147, 1.13721, 1.88177", \ + "0.041455, 0.178257, 0.268965, 0.4243, 0.690148, 1.13722, 1.88178", \ + "0.042618, 0.178448, 0.269103, 0.424301, 0.690149, 1.13723, 1.88179", \ + "0.044665, 0.179028, 0.269411, 0.424302, 0.69015, 1.13724, 1.8818" \ ); } } @@ -29727,10 +29841,10 @@ library (sg13g2_stdcell_slow_1p08V_125C) { index_1 ("0.0186, 0.0966, 0.174, 0.3294, 0.6408, 1.263, 2.5074"); index_2 ("0.001, 0.0468, 0.078, 0.1296, 0.216, 0.36, 0.6"); values ( \ - "0.0307028, 0.0585763, 0.0769734, 0.107118, 0.157349, 0.241039, 0.380424", \ + "0.0306921, 0.058571, 0.0769575, 0.107118, 0.157353, 0.24104, 0.380319", \ "0.0303697, 0.0582549, 0.0766474, 0.106824, 0.157076, 0.240891, 0.380112", \ "0.0303509, 0.0583964, 0.0766887, 0.106949, 0.157356, 0.24095, 0.380081", \ - "0.0304015, 0.0582633, 0.0766717, 0.106942, 0.157205, 0.240805, 0.380292", \ + "0.0304015, 0.0582633, 0.0766718, 0.106942, 0.157205, 0.240805, 0.380292", \ "0.0308356, 0.0588114, 0.0772372, 0.107214, 0.157768, 0.241072, 0.3807", \ "0.031702, 0.059608, 0.0779401, 0.10829, 0.158665, 0.242023, 0.382747", \ "0.0338069, 0.0615854, 0.0800953, 0.110235, 0.160575, 0.244909, 0.384033" \ @@ -29740,8 +29854,8 @@ library (sg13g2_stdcell_slow_1p08V_125C) { index_1 ("0.0186, 0.0966, 0.174, 0.3294, 0.6408, 1.263, 2.5074"); index_2 ("0.001, 0.0468, 0.078, 0.1296, 0.216, 0.36, 0.6"); values ( \ - "0.0291787, 0.0567575, 0.0750385, 0.105043, 0.155088, 0.238274, 0.377044", \ - "0.0288556, 0.0563848, 0.074676, 0.104665, 0.15473, 0.237851, 0.376694", \ + "0.0291954, 0.0567769, 0.0750468, 0.105054, 0.155091, 0.238278, 0.377049", \ + "0.0288556, 0.0563848, 0.0746758, 0.104665, 0.15473, 0.237894, 0.376694", \ "0.0287394, 0.0563895, 0.074614, 0.104612, 0.154851, 0.238056, 0.376656", \ "0.0286346, 0.0561893, 0.0745282, 0.105119, 0.154662, 0.237812, 0.376523", \ "0.0289588, 0.0565847, 0.0750375, 0.104918, 0.155021, 0.239587, 0.376776", \ @@ -29756,10 +29870,10 @@ library (sg13g2_stdcell_slow_1p08V_125C) { index_1 ("0.0186, 0.0966, 0.174, 0.3294, 0.6408, 1.263, 2.5074"); index_2 ("0.001, 0.0468, 0.078, 0.1296, 0.216, 0.36, 0.6"); values ( \ - "0.0307028, 0.0585763, 0.0769734, 0.107118, 0.157349, 0.241039, 0.380424", \ + "0.0306921, 0.058571, 0.0769575, 0.107118, 0.157353, 0.24104, 0.380319", \ "0.0303697, 0.0582549, 0.0766474, 0.106824, 0.157076, 0.240891, 0.380112", \ "0.0303509, 0.0583964, 0.0766887, 0.106949, 0.157356, 0.24095, 0.380081", \ - "0.0304015, 0.0582633, 0.0766717, 0.106942, 0.157205, 0.240805, 0.380292", \ + "0.0304015, 0.0582633, 0.0766718, 0.106942, 0.157205, 0.240805, 0.380292", \ "0.0308356, 0.0588114, 0.0772372, 0.107214, 0.157768, 0.241072, 0.3807", \ "0.031702, 0.059608, 0.0779401, 0.10829, 0.158665, 0.242023, 0.382747", \ "0.0338069, 0.0615854, 0.0800953, 0.110235, 0.160575, 0.244909, 0.384033" \ @@ -29769,8 +29883,8 @@ library (sg13g2_stdcell_slow_1p08V_125C) { index_1 ("0.0186, 0.0966, 0.174, 0.3294, 0.6408, 1.263, 2.5074"); index_2 ("0.001, 0.0468, 0.078, 0.1296, 0.216, 0.36, 0.6"); values ( \ - "0.0291787, 0.0567575, 0.0750385, 0.105043, 0.155088, 0.238274, 0.377044", \ - "0.0288556, 0.0563848, 0.074676, 0.104665, 0.15473, 0.237851, 0.376694", \ + "0.0291954, 0.0567769, 0.0750468, 0.105054, 0.155091, 0.238278, 0.377049", \ + "0.0288556, 0.0563848, 0.0746758, 0.104665, 0.15473, 0.237894, 0.376694", \ "0.0287394, 0.0563895, 0.074614, 0.104612, 0.154851, 0.238056, 0.376656", \ "0.0286346, 0.0561893, 0.0745282, 0.105119, 0.154662, 0.237812, 0.376523", \ "0.0289588, 0.0565847, 0.0750375, 0.104918, 0.155021, 0.239587, 0.376776", \ @@ -29785,13 +29899,13 @@ library (sg13g2_stdcell_slow_1p08V_125C) { index_1 ("0.0186, 0.0966, 0.174, 0.3294, 0.6408, 1.263, 2.5074"); index_2 ("0.001, 0.0468, 0.078, 0.1296, 0.216, 0.36, 0.6"); values ( \ - "0.0300602, 0.0520044, 0.0665091, 0.092153, 0.139656, 0.22767, 0.385485", \ - "0.0297344, 0.0515333, 0.0659867, 0.0905579, 0.135637, 0.219669, 0.372785", \ - "0.0295978, 0.051607, 0.0657805, 0.0899029, 0.133396, 0.214224, 0.363158", \ - "0.0294084, 0.0513507, 0.0657723, 0.089446, 0.131094, 0.206947, 0.349061", \ - "0.029401, 0.0513717, 0.0655866, 0.089353, 0.129619, 0.200457, 0.331248", \ - "0.0296927, 0.0515955, 0.0660666, 0.0899184, 0.129039, 0.19597, 0.314721", \ - "0.030873, 0.0524686, 0.0670563, 0.0909998, 0.130988, 0.196514, 0.306898" \ + "0.0300633, 0.0519483, 0.0665175, 0.0921992, 0.139684, 0.227568, 0.385516", \ + "0.0297363, 0.051535, 0.0659869, 0.0905592, 0.135615, 0.219671, 0.37277", \ + "0.0295988, 0.0515414, 0.0657959, 0.0899493, 0.133314, 0.214196, 0.36322", \ + "0.0294033, 0.0513667, 0.0657845, 0.0894475, 0.130946, 0.206848, 0.349068", \ + "0.0294003, 0.0513393, 0.0655851, 0.089325, 0.129723, 0.200462, 0.331354", \ + "0.0296929, 0.0515966, 0.0660926, 0.0899293, 0.128769, 0.195849, 0.314807", \ + "0.0308436, 0.0525464, 0.0670571, 0.0910082, 0.131004, 0.196457, 0.30707" \ ); } fall_power (scalar) { @@ -29807,9 +29921,9 @@ library (sg13g2_stdcell_slow_1p08V_125C) { max_transition : 2.5074; capacitance : 0.00274809; rise_capacitance : 0.00279302; - rise_capacitance_range (0.00279302, 0.00279302); + rise_capacitance_range (0.00257842, 0.00297196); fall_capacitance : 0.00269034; - fall_capacitance_range (0.00269034, 0.00269034); + fall_capacitance_range (0.00251543, 0.00285873); timing () { related_pin : "CLK"; timing_type : min_pulse_width; @@ -29825,13 +29939,13 @@ library (sg13g2_stdcell_slow_1p08V_125C) { rise_power (passive_POWER_7x1ds1) { index_1 ("0.0186, 0.0966, 0.174, 0.3294, 0.6408, 1.263, 2.5074"); values ( \ - "0.00894353, 0.00855805, 0.00852259, 0.00851044, 0.00886369, 0.00961455, 0.0115646" \ + "0.00893593, 0.00855806, 0.0085226, 0.00851045, 0.0088637, 0.00961456, 0.0115646" \ ); } fall_power (passive_POWER_7x1ds1) { index_1 ("0.0186, 0.0966, 0.174, 0.3294, 0.6408, 1.263, 2.5074"); values ( \ - "0.00862761, 0.00829809, 0.0082277, 0.00828939, 0.00859388, 0.00933431, 0.0112034" \ + "0.00862779, 0.0082981, 0.0082277, 0.00828939, 0.00859389, 0.00933431, 0.0112034" \ ); } } @@ -29845,7 +29959,7 @@ library (sg13g2_stdcell_slow_1p08V_125C) { fall_power (passive_POWER_7x1ds1) { index_1 ("0.0186, 0.0966, 0.174, 0.3294, 0.6408, 1.263, 2.5074"); values ( \ - "0.0167079, 0.0163768, 0.01624, 0.0162769, 0.0165927, 0.0172807, 0.0191457" \ + "0.0167079, 0.0163772, 0.01624, 0.0162769, 0.0165928, 0.0172807, 0.0191457" \ ); } } @@ -29868,7 +29982,7 @@ library (sg13g2_stdcell_slow_1p08V_125C) { rise_power (passive_POWER_7x1ds1) { index_1 ("0.0186, 0.0966, 0.174, 0.3294, 0.6408, 1.263, 2.5074"); values ( \ - "0.00882267, 0.00844839, 0.00841413, 0.00839153, 0.00875155, 0.00949224, 0.0114772" \ + "0.0088231, 0.00844839, 0.00841413, 0.00839152, 0.00875155, 0.00949223, 0.0114772" \ ); } fall_power (passive_POWER_7x1ds1) { @@ -29883,13 +29997,13 @@ library (sg13g2_stdcell_slow_1p08V_125C) { rise_power (passive_POWER_7x1ds1) { index_1 ("0.0186, 0.0966, 0.174, 0.3294, 0.6408, 1.263, 2.5074"); values ( \ - "0.00892064, 0.00856715, 0.00851758, 0.00850718, 0.00886298, 0.00961529, 0.0115647" \ + "0.00891882, 0.00856712, 0.0085172, 0.00850716, 0.00886296, 0.00961527, 0.0115647" \ ); } fall_power (passive_POWER_7x1ds1) { index_1 ("0.0186, 0.0966, 0.174, 0.3294, 0.6408, 1.263, 2.5074"); values ( \ - "0.00863406, 0.00829698, 0.00823682, 0.00829034, 0.00859571, 0.00933431, 0.0112027" \ + "0.00863402, 0.00829684, 0.00823678, 0.0082903, 0.00859567, 0.00933427, 0.0112026" \ ); } } @@ -29898,13 +30012,13 @@ library (sg13g2_stdcell_slow_1p08V_125C) { rise_power (passive_POWER_7x1ds1) { index_1 ("0.0186, 0.0966, 0.174, 0.3294, 0.6408, 1.263, 2.5074"); values ( \ - "0.000409588, 4.894e-05, 1.32671e-05, -4.2056e-06, 0.000350999, 0.00109511, 0.00305281" \ + "0.000409305, 4.89298e-05, 1.32569e-05, -4.21577e-06, 0.000350989, 0.0010951, 0.0030528" \ ); } fall_power (passive_POWER_7x1ds1) { index_1 ("0.0186, 0.0966, 0.174, 0.3294, 0.6408, 1.263, 2.5074"); values ( \ - "0.000941701, 0.00060662, 0.000560688, 0.000620323, 0.000912754, 0.00164565, 0.00351101" \ + "0.000941696, 0.000606588, 0.000560683, 0.000620318, 0.000912749, 0.00164564, 0.00351101" \ ); } } @@ -29913,13 +30027,13 @@ library (sg13g2_stdcell_slow_1p08V_125C) { rise_power (passive_POWER_7x1ds1) { index_1 ("0.0186, 0.0966, 0.174, 0.3294, 0.6408, 1.263, 2.5074"); values ( \ - "0.00883167, 0.00848, 0.00844811, 0.00842584, 0.00878517, 0.00952653, 0.0115102" \ + "0.00884589, 0.00848001, 0.00844811, 0.00842567, 0.00878518, 0.00952655, 0.0115102" \ ); } fall_power (passive_POWER_7x1ds1) { index_1 ("0.0186, 0.0966, 0.174, 0.3294, 0.6408, 1.263, 2.5074"); values ( \ - "0.00859882, 0.00825944, 0.00820867, 0.00826151, 0.0085728, 0.00930989, 0.0111774" \ + "0.00859884, 0.00825944, 0.00820867, 0.00826151, 0.0085728, 0.00930989, 0.0111774" \ ); } } @@ -29927,13 +30041,13 @@ library (sg13g2_stdcell_slow_1p08V_125C) { rise_power (passive_POWER_7x1ds1) { index_1 ("0.0186, 0.0966, 0.174, 0.3294, 0.6408, 1.263, 2.5074"); values ( \ - "0.00882267, 0.00844839, 0.00841413, 0.00839153, 0.00875155, 0.00949224, 0.0114772" \ + "0.0088231, 0.00844839, 0.00841413, 0.00839152, 0.00875155, 0.00949223, 0.0114772" \ ); } fall_power (passive_POWER_7x1ds1) { index_1 ("0.0186, 0.0966, 0.174, 0.3294, 0.6408, 1.263, 2.5074"); values ( \ - "0.00863406, 0.00829698, 0.00823682, 0.00829034, 0.00859571, 0.00933431, 0.0112027" \ + "0.00863402, 0.00829684, 0.00823678, 0.0082903, 0.00859567, 0.00933427, 0.0112026" \ ); } } @@ -29944,11 +30058,12 @@ library (sg13g2_stdcell_slow_1p08V_125C) { max_transition : 2.5074; capacitance : 0.00259169; rise_capacitance : 0.00262419; - rise_capacitance_range (0.00262419, 0.00262419); + rise_capacitance_range (0.00233263, 0.00284655); fall_capacitance : 0.00255918; - fall_capacitance_range (0.00255918, 0.00255918); + fall_capacitance_range (0.00226346, 0.0027442); timing () { related_pin : "CLK"; + sdf_edges : both_edges; timing_type : hold_rising; rise_constraint (CONSTRAINT_4x4) { index_1 ("0.0186, 0.51636, 1.263, 2.5074"); @@ -29967,12 +30082,13 @@ library (sg13g2_stdcell_slow_1p08V_125C) { "-0.215177, -0.0676338, 0.0344321, 0.142185", \ "-0.384111, -0.236821, -0.132776, -0.0241433", \ "-0.515355, -0.370727, -0.267138, -0.156906", \ - "-0.657573, -0.511912, -0.410909, -0.301057" \ + "-0.654874, -0.511912, -0.410909, -0.301057" \ ); } } timing () { related_pin : "CLK"; + sdf_edges : both_edges; timing_type : setup_rising; rise_constraint (CONSTRAINT_4x4) { index_1 ("0.0186, 0.51636, 1.263, 2.5074"); @@ -30000,13 +30116,13 @@ library (sg13g2_stdcell_slow_1p08V_125C) { rise_power (passive_POWER_7x1ds1) { index_1 ("0.0186, 0.0966, 0.174, 0.3294, 0.6408, 1.263, 2.5074"); values ( \ - "0.0181759, 0.0179476, 0.0178367, 0.0177795, 0.0179814, 0.01863, 0.0203027" \ + "0.0181753, 0.0179475, 0.0178366, 0.0177794, 0.0179814, 0.0186299, 0.0203027" \ ); } fall_power (passive_POWER_7x1ds1) { index_1 ("0.0186, 0.0966, 0.174, 0.3294, 0.6408, 1.263, 2.5074"); values ( \ - "0.0228254, 0.0225325, 0.0224671, 0.0225064, 0.0228023, 0.0235294, 0.0252492" \ + "0.0228254, 0.0225326, 0.022467, 0.0225064, 0.0228023, 0.0235294, 0.0252492" \ ); } } @@ -30014,13 +30130,13 @@ library (sg13g2_stdcell_slow_1p08V_125C) { rise_power (passive_POWER_7x1ds1) { index_1 ("0.0186, 0.0966, 0.174, 0.3294, 0.6408, 1.263, 2.5074"); values ( \ - "0.0181759, 0.0179476, 0.0178367, 0.0177795, 0.0179814, 0.01863, 0.0203027" \ + "0.0181753, 0.0179475, 0.0178366, 0.0177794, 0.0179814, 0.0186299, 0.0203027" \ ); } fall_power (passive_POWER_7x1ds1) { index_1 ("0.0186, 0.0966, 0.174, 0.3294, 0.6408, 1.263, 2.5074"); values ( \ - "0.0228254, 0.0225325, 0.0224671, 0.0225064, 0.0228023, 0.0235294, 0.0252492" \ + "0.0228254, 0.0225326, 0.022467, 0.0225064, 0.0228023, 0.0235294, 0.0252492" \ ); } } @@ -30028,13 +30144,14 @@ library (sg13g2_stdcell_slow_1p08V_125C) { pin (RESET_B) { direction : input; max_transition : 2.5074; - capacitance : 0.00515959; - rise_capacitance : 0.00515959; - rise_capacitance_range (0.00515959, 0.00515959); - fall_capacitance : 0.00515959; - fall_capacitance_range (0.00515959, 0.00515959); + capacitance : 0.00520209; + rise_capacitance : 0.00520209; + rise_capacitance_range (0.00520209, 0.00520209); + fall_capacitance : 0.00520209; + fall_capacitance_range (0.00493033, 0.00534686); timing () { related_pin : "CLK"; + sdf_edges : both_edges; timing_type : recovery_rising; rise_constraint (CONSTRAINT_4x4) { index_1 ("0.0186, 0.51636, 1.263, 2.5074"); @@ -30049,12 +30166,13 @@ library (sg13g2_stdcell_slow_1p08V_125C) { } timing () { related_pin : "CLK"; + sdf_edges : both_edges; timing_type : removal_rising; rise_constraint (CONSTRAINT_4x4) { index_1 ("0.0186, 0.51636, 1.263, 2.5074"); index_2 ("0.0186, 0.51636, 1.263, 2.5074"); values ( \ - "-0.176054, -0.0876004, -0.0350059, 0.0207588", \ + "-0.176054, -0.0876004, -0.0350059, 0.0234572", \ "-0.36664, -0.269925, -0.216693, -0.158844", \ "-0.543644, -0.43891, -0.380469, -0.320753", \ "-0.752016, -0.641114, -0.580406, -0.519471" \ @@ -30078,11 +30196,12 @@ library (sg13g2_stdcell_slow_1p08V_125C) { max_transition : 2.5074; capacitance : 0.00270551; rise_capacitance : 0.00272724; - rise_capacitance_range (0.00272724, 0.00272724); + rise_capacitance_range (0.00243679, 0.00294761); fall_capacitance : 0.00266205; - fall_capacitance_range (0.00266205, 0.00266205); + fall_capacitance_range (0.00236925, 0.00284624); timing () { related_pin : "CLK"; + sdf_edges : both_edges; timing_type : hold_rising; rise_constraint (CONSTRAINT_4x4) { index_1 ("0.0186, 0.51636, 1.263, 2.5074"); @@ -30107,6 +30226,7 @@ library (sg13g2_stdcell_slow_1p08V_125C) { } timing () { related_pin : "CLK"; + sdf_edges : both_edges; timing_type : setup_rising; rise_constraint (CONSTRAINT_4x4) { index_1 ("0.0186, 0.51636, 1.263, 2.5074"); @@ -30134,7 +30254,7 @@ library (sg13g2_stdcell_slow_1p08V_125C) { rise_power (passive_POWER_7x1ds1) { index_1 ("0.0186, 0.0966, 0.174, 0.3294, 0.6408, 1.263, 2.5074"); values ( \ - "0.018311, 0.0180684, 0.0179534, 0.0178995, 0.0181076, 0.01876, 0.0204229" \ + "0.0183109, 0.0180684, 0.0179534, 0.0178995, 0.0181076, 0.01876, 0.0204229" \ ); } fall_power (passive_POWER_7x1ds1) { @@ -30148,7 +30268,7 @@ library (sg13g2_stdcell_slow_1p08V_125C) { rise_power (passive_POWER_7x1ds1) { index_1 ("0.0186, 0.0966, 0.174, 0.3294, 0.6408, 1.263, 2.5074"); values ( \ - "0.018311, 0.0180684, 0.0179534, 0.0178995, 0.0181076, 0.01876, 0.0204229" \ + "0.0183109, 0.0180684, 0.0179534, 0.0178995, 0.0181076, 0.01876, 0.0204229" \ ); } fall_power (passive_POWER_7x1ds1) { @@ -30165,11 +30285,12 @@ library (sg13g2_stdcell_slow_1p08V_125C) { max_transition : 2.5074; capacitance : 0.00438614; rise_capacitance : 0.00448671; - rise_capacitance_range (0.00448671, 0.00448671); + rise_capacitance_range (0.00413845, 0.00484532); fall_capacitance : 0.00428557; - fall_capacitance_range (0.00428557, 0.00428557); + fall_capacitance_range (0.00413486, 0.00475282); timing () { related_pin : "CLK"; + sdf_edges : both_edges; timing_type : hold_rising; rise_constraint (CONSTRAINT_4x4) { index_1 ("0.0186, 0.51636, 1.263, 2.5074"); @@ -30194,6 +30315,7 @@ library (sg13g2_stdcell_slow_1p08V_125C) { } timing () { related_pin : "CLK"; + sdf_edges : both_edges; timing_type : setup_rising; rise_constraint (CONSTRAINT_4x4) { index_1 ("0.0186, 0.51636, 1.263, 2.5074"); @@ -30201,7 +30323,7 @@ library (sg13g2_stdcell_slow_1p08V_125C) { values ( \ "0.32521, 0.229862, 0.179025, 0.119556", \ "0.496423, 0.402341, 0.350436, 0.290796", \ - "0.628513, 0.533317, 0.480309, 0.419627", \ + "0.625941, 0.533317, 0.480309, 0.419627", \ "0.768206, 0.671353, 0.619955, 0.560792" \ ); } @@ -30227,7 +30349,7 @@ library (sg13g2_stdcell_slow_1p08V_125C) { fall_power (passive_POWER_7x1ds1) { index_1 ("0.0186, 0.0966, 0.174, 0.3294, 0.6408, 1.263, 2.5074"); values ( \ - "0.02082, 0.0206104, 0.0205778, 0.0206253, 0.0208045, 0.021292, 0.0225234" \ + "0.0208196, 0.0206104, 0.0205778, 0.0206252, 0.0208045, 0.021292, 0.0225234" \ ); } } @@ -30242,7 +30364,7 @@ library (sg13g2_stdcell_slow_1p08V_125C) { fall_power (passive_POWER_7x1ds1) { index_1 ("0.0186, 0.0966, 0.174, 0.3294, 0.6408, 1.263, 2.5074"); values ( \ - "0.00842724, 0.0238934, 0.0270449, 0.0278157, 0.0282512, 0.0292252, 0.0318937" \ + "0.00842725, 0.023894, 0.0270449, 0.0278157, 0.0282512, 0.0292252, 0.0318937" \ ); } } @@ -30256,15 +30378,15 @@ library (sg13g2_stdcell_slow_1p08V_125C) { fall_power (passive_POWER_7x1ds1) { index_1 ("0.0186, 0.0966, 0.174, 0.3294, 0.6408, 1.263, 2.5074"); values ( \ - "0.00842724, 0.0238934, 0.0270449, 0.0278157, 0.0282512, 0.0292252, 0.0318937" \ + "0.00842725, 0.023894, 0.0270449, 0.0278157, 0.0282512, 0.0292252, 0.0318937" \ ); } } } ff (IQ,IQN) { - clear : "RESET_B'"; + clear : "!RESET_B"; clocked_on : "CLK"; - next_state : "(SCE*SCD)+(SCE'*D)"; + next_state : "(SCE*SCD)+(!SCE*D)"; } test_cell () { pin (Q) { @@ -30295,7 +30417,7 @@ library (sg13g2_stdcell_slow_1p08V_125C) { signal_type : test_scan_enable; } ff (IQ,IQN) { - clear : "RESET_B'"; + clear : "!RESET_B"; clocked_on : "CLK"; next_state : "D"; } @@ -30381,6 +30503,7 @@ library (sg13g2_stdcell_slow_1p08V_125C) { timing () { related_pin : "CLK"; sdf_cond : "SCE == 1'b1"; + sdf_edges : start_edge; timing_sense : non_unate; timing_type : rising_edge; when : "SCE"; @@ -30440,6 +30563,7 @@ library (sg13g2_stdcell_slow_1p08V_125C) { timing () { related_pin : "CLK"; sdf_cond : "SCE == 1'b0"; + sdf_edges : start_edge; timing_sense : non_unate; timing_type : rising_edge; when : "!SCE"; @@ -30498,6 +30622,7 @@ library (sg13g2_stdcell_slow_1p08V_125C) { } timing () { related_pin : "CLK"; + sdf_edges : start_edge; timing_sense : non_unate; timing_type : rising_edge; cell_rise (TIMING_DELAY_7x7ds1) { @@ -30555,6 +30680,7 @@ library (sg13g2_stdcell_slow_1p08V_125C) { } timing () { related_pin : "RESET_B"; + sdf_edges : start_edge; timing_sense : positive_unate; timing_type : clear; cell_fall (TIMING_DELAY_7x7ds1) { @@ -30701,9 +30827,9 @@ library (sg13g2_stdcell_slow_1p08V_125C) { max_transition : 2.5074; capacitance : 0.00274789; rise_capacitance : 0.00279302; - rise_capacitance_range (0.00279302, 0.00279302); + rise_capacitance_range (0.00257789, 0.00297001); fall_capacitance : 0.00268985; - fall_capacitance_range (0.00268985, 0.00268985); + fall_capacitance_range (0.00251319, 0.00285864); timing () { related_pin : "CLK"; timing_type : min_pulse_width; @@ -30844,11 +30970,12 @@ library (sg13g2_stdcell_slow_1p08V_125C) { max_transition : 2.5074; capacitance : 0.0025946; rise_capacitance : 0.00262696; - rise_capacitance_range (0.00262696, 0.00262696); + rise_capacitance_range (0.00233696, 0.00284891); fall_capacitance : 0.00256224; - fall_capacitance_range (0.00256224, 0.00256224); + fall_capacitance_range (0.00226638, 0.00274654); timing () { related_pin : "CLK"; + sdf_edges : both_edges; timing_type : hold_rising; rise_constraint (CONSTRAINT_4x4) { index_1 ("0.0186, 0.51636, 1.263, 2.5074"); @@ -30873,6 +31000,7 @@ library (sg13g2_stdcell_slow_1p08V_125C) { } timing () { related_pin : "CLK"; + sdf_edges : both_edges; timing_type : setup_rising; rise_constraint (CONSTRAINT_4x4) { index_1 ("0.0186, 0.51636, 1.263, 2.5074"); @@ -30932,9 +31060,10 @@ library (sg13g2_stdcell_slow_1p08V_125C) { rise_capacitance : 0.00483064; rise_capacitance_range (0.00483064, 0.00483064); fall_capacitance : 0.00483064; - fall_capacitance_range (0.00483064, 0.00483064); + fall_capacitance_range (0.00457175, 0.00500661); timing () { related_pin : "CLK"; + sdf_edges : both_edges; timing_type : recovery_rising; rise_constraint (CONSTRAINT_4x4) { index_1 ("0.0186, 0.51636, 1.263, 2.5074"); @@ -30949,6 +31078,7 @@ library (sg13g2_stdcell_slow_1p08V_125C) { } timing () { related_pin : "CLK"; + sdf_edges : both_edges; timing_type : removal_rising; rise_constraint (CONSTRAINT_4x4) { index_1 ("0.0186, 0.51636, 1.263, 2.5074"); @@ -30978,11 +31108,12 @@ library (sg13g2_stdcell_slow_1p08V_125C) { max_transition : 2.5074; capacitance : 0.00270745; rise_capacitance : 0.00272898; - rise_capacitance_range (0.00272898, 0.00272898); + rise_capacitance_range (0.002438, 0.00294994); fall_capacitance : 0.00266439; - fall_capacitance_range (0.00266439, 0.00266439); + fall_capacitance_range (0.0023717, 0.00284856); timing () { related_pin : "CLK"; + sdf_edges : both_edges; timing_type : hold_rising; rise_constraint (CONSTRAINT_4x4) { index_1 ("0.0186, 0.51636, 1.263, 2.5074"); @@ -31007,6 +31138,7 @@ library (sg13g2_stdcell_slow_1p08V_125C) { } timing () { related_pin : "CLK"; + sdf_edges : both_edges; timing_type : setup_rising; rise_constraint (CONSTRAINT_4x4) { index_1 ("0.0186, 0.51636, 1.263, 2.5074"); @@ -31065,11 +31197,12 @@ library (sg13g2_stdcell_slow_1p08V_125C) { max_transition : 2.5074; capacitance : 0.0043864; rise_capacitance : 0.00448718; - rise_capacitance_range (0.00448718, 0.00448718); + rise_capacitance_range (0.00414454, 0.00484533); fall_capacitance : 0.00428563; - fall_capacitance_range (0.00428563, 0.00428563); + fall_capacitance_range (0.00413312, 0.00475281); timing () { related_pin : "CLK"; + sdf_edges : both_edges; timing_type : hold_rising; rise_constraint (CONSTRAINT_4x4) { index_1 ("0.0186, 0.51636, 1.263, 2.5074"); @@ -31094,6 +31227,7 @@ library (sg13g2_stdcell_slow_1p08V_125C) { } timing () { related_pin : "CLK"; + sdf_edges : both_edges; timing_type : setup_rising; rise_constraint (CONSTRAINT_4x4) { index_1 ("0.0186, 0.51636, 1.263, 2.5074"); @@ -31162,9 +31296,9 @@ library (sg13g2_stdcell_slow_1p08V_125C) { } } ff (IQ,IQN) { - clear : "RESET_B'"; + clear : "!RESET_B"; clocked_on : "CLK"; - next_state : "(SCE*SCD)+(SCE'*D)"; + next_state : "(SCE*SCD)+(!SCE*D)"; } test_cell () { pin (Q) { @@ -31190,7 +31324,7 @@ library (sg13g2_stdcell_slow_1p08V_125C) { signal_type : test_scan_enable; } ff (IQ,IQN) { - clear : "RESET_B'"; + clear : "!RESET_B"; clocked_on : "CLK"; next_state : "D"; } @@ -31276,6 +31410,7 @@ library (sg13g2_stdcell_slow_1p08V_125C) { timing () { related_pin : "CLK"; sdf_cond : "SCE == 1'b1"; + sdf_edges : start_edge; timing_sense : non_unate; timing_type : rising_edge; when : "SCE"; @@ -31335,6 +31470,7 @@ library (sg13g2_stdcell_slow_1p08V_125C) { timing () { related_pin : "CLK"; sdf_cond : "SCE == 1'b0"; + sdf_edges : start_edge; timing_sense : non_unate; timing_type : rising_edge; when : "!SCE"; @@ -31393,6 +31529,7 @@ library (sg13g2_stdcell_slow_1p08V_125C) { } timing () { related_pin : "CLK"; + sdf_edges : start_edge; timing_sense : non_unate; timing_type : rising_edge; cell_rise (TIMING_DELAY_7x7ds1) { @@ -31450,6 +31587,7 @@ library (sg13g2_stdcell_slow_1p08V_125C) { } timing () { related_pin : "RESET_B"; + sdf_edges : start_edge; timing_sense : positive_unate; timing_type : clear; cell_fall (TIMING_DELAY_7x7ds1) { @@ -31596,9 +31734,9 @@ library (sg13g2_stdcell_slow_1p08V_125C) { max_transition : 2.5074; capacitance : 0.00274781; rise_capacitance : 0.00279299; - rise_capacitance_range (0.00279299, 0.00279299); + rise_capacitance_range (0.00257509, 0.00297484); fall_capacitance : 0.00268972; - fall_capacitance_range (0.00268972, 0.00268972); + fall_capacitance_range (0.0025133, 0.00285863); timing () { related_pin : "CLK"; timing_type : min_pulse_width; @@ -31693,13 +31831,13 @@ library (sg13g2_stdcell_slow_1p08V_125C) { rise_power (passive_POWER_7x1ds1) { index_1 ("0.0186, 0.0966, 0.174, 0.3294, 0.6408, 1.263, 2.5074"); values ( \ - "0.00406569, 0.0037058, 0.00368312, 0.00366272, 0.00401568, 0.00476318, 0.00671289" \ + "0.00406569, 0.0037058, 0.00368312, 0.00366272, 0.00401568, 0.00476319, 0.0067129" \ ); } fall_power (passive_POWER_7x1ds1) { index_1 ("0.0186, 0.0966, 0.174, 0.3294, 0.6408, 1.263, 2.5074"); values ( \ - "0.00457945, 0.00427115, 0.00420907, 0.00429149, 0.00458962, 0.00531816, 0.00718973" \ + "0.00457946, 0.00427115, 0.00420907, 0.00429149, 0.00458962, 0.00531816, 0.00718973" \ ); } } @@ -31739,11 +31877,12 @@ library (sg13g2_stdcell_slow_1p08V_125C) { max_transition : 2.5074; capacitance : 0.00259217; rise_capacitance : 0.00262449; - rise_capacitance_range (0.00262449, 0.00262449); + rise_capacitance_range (0.00233325, 0.00284656); fall_capacitance : 0.00255986; - fall_capacitance_range (0.00255986, 0.00255986); + fall_capacitance_range (0.00226355, 0.0027442); timing () { related_pin : "CLK"; + sdf_edges : both_edges; timing_type : hold_rising; rise_constraint (CONSTRAINT_4x4) { index_1 ("0.0186, 0.51636, 1.263, 2.5074"); @@ -31768,6 +31907,7 @@ library (sg13g2_stdcell_slow_1p08V_125C) { } timing () { related_pin : "CLK"; + sdf_edges : both_edges; timing_type : setup_rising; rise_constraint (CONSTRAINT_4x4) { index_1 ("0.0186, 0.51636, 1.263, 2.5074"); @@ -31827,9 +31967,10 @@ library (sg13g2_stdcell_slow_1p08V_125C) { rise_capacitance : 0.00484206; rise_capacitance_range (0.00484206, 0.00484206); fall_capacitance : 0.00484206; - fall_capacitance_range (0.00484206, 0.00484206); + fall_capacitance_range (0.0045943, 0.00501083); timing () { related_pin : "CLK"; + sdf_edges : both_edges; timing_type : recovery_rising; rise_constraint (CONSTRAINT_4x4) { index_1 ("0.0186, 0.51636, 1.263, 2.5074"); @@ -31844,6 +31985,7 @@ library (sg13g2_stdcell_slow_1p08V_125C) { } timing () { related_pin : "CLK"; + sdf_edges : both_edges; timing_type : removal_rising; rise_constraint (CONSTRAINT_4x4) { index_1 ("0.0186, 0.51636, 1.263, 2.5074"); @@ -31873,11 +32015,12 @@ library (sg13g2_stdcell_slow_1p08V_125C) { max_transition : 2.5074; capacitance : 0.00270627; rise_capacitance : 0.0027279; - rise_capacitance_range (0.0027279, 0.0027279); + rise_capacitance_range (0.00243702, 0.00294851); fall_capacitance : 0.002663; - fall_capacitance_range (0.002663, 0.002663); + fall_capacitance_range (0.00237056, 0.00284713); timing () { related_pin : "CLK"; + sdf_edges : both_edges; timing_type : hold_rising; rise_constraint (CONSTRAINT_4x4) { index_1 ("0.0186, 0.51636, 1.263, 2.5074"); @@ -31902,6 +32045,7 @@ library (sg13g2_stdcell_slow_1p08V_125C) { } timing () { related_pin : "CLK"; + sdf_edges : both_edges; timing_type : setup_rising; rise_constraint (CONSTRAINT_4x4) { index_1 ("0.0186, 0.51636, 1.263, 2.5074"); @@ -31960,11 +32104,12 @@ library (sg13g2_stdcell_slow_1p08V_125C) { max_transition : 2.5074; capacitance : 0.00438637; rise_capacitance : 0.00448703; - rise_capacitance_range (0.00448703, 0.00448703); + rise_capacitance_range (0.00414482, 0.00484533); fall_capacitance : 0.0042857; - fall_capacitance_range (0.0042857, 0.0042857); + fall_capacitance_range (0.00413311, 0.00475281); timing () { related_pin : "CLK"; + sdf_edges : both_edges; timing_type : hold_rising; rise_constraint (CONSTRAINT_4x4) { index_1 ("0.0186, 0.51636, 1.263, 2.5074"); @@ -31989,6 +32134,7 @@ library (sg13g2_stdcell_slow_1p08V_125C) { } timing () { related_pin : "CLK"; + sdf_edges : both_edges; timing_type : setup_rising; rise_constraint (CONSTRAINT_4x4) { index_1 ("0.0186, 0.51636, 1.263, 2.5074"); @@ -32037,7 +32183,7 @@ library (sg13g2_stdcell_slow_1p08V_125C) { fall_power (passive_POWER_7x1ds1) { index_1 ("0.0186, 0.0966, 0.174, 0.3294, 0.6408, 1.263, 2.5074"); values ( \ - "0.0121117, 0.0275782, 0.0307214, 0.0314967, 0.0319216, 0.0329014, 0.0355608" \ + "0.0121118, 0.0275782, 0.0307214, 0.0314967, 0.0319216, 0.0329014, 0.0355608" \ ); } } @@ -32051,15 +32197,15 @@ library (sg13g2_stdcell_slow_1p08V_125C) { fall_power (passive_POWER_7x1ds1) { index_1 ("0.0186, 0.0966, 0.174, 0.3294, 0.6408, 1.263, 2.5074"); values ( \ - "0.0121117, 0.0275782, 0.0307214, 0.0314967, 0.0319216, 0.0329014, 0.0355608" \ + "0.0121118, 0.0275782, 0.0307214, 0.0314967, 0.0319216, 0.0329014, 0.0355608" \ ); } } } ff (IQ,IQN) { - clear : "RESET_B'"; + clear : "!RESET_B"; clocked_on : "CLK"; - next_state : "(SCE*SCD)+(SCE'*D)"; + next_state : "(SCE*SCD)+(!SCE*D)"; } test_cell () { pin (Q) { @@ -32085,7 +32231,7 @@ library (sg13g2_stdcell_slow_1p08V_125C) { signal_type : test_scan_enable; } ff (IQ,IQN) { - clear : "RESET_B'"; + clear : "!RESET_B"; clocked_on : "CLK"; next_state : "D"; } @@ -32093,7 +32239,7 @@ library (sg13g2_stdcell_slow_1p08V_125C) { } cell (sg13g2_sighold) { area : 9.072; - cell_footprint : "keepstate"; + cell_footprint : "sighold"; cell_leakage_power : 571.883; dont_touch : true; dont_use : true; @@ -32131,7 +32277,7 @@ library (sg13g2_stdcell_slow_1p08V_125C) { } cell (sg13g2_slgcp_1) { area : 30.8448; - cell_footprint : "sgclk"; + cell_footprint : "slgcp"; cell_leakage_power : 2008.5; clock_gating_integrated_cell : "latch_posedge_precontrol"; dont_touch : true; @@ -32270,9 +32416,9 @@ library (sg13g2_stdcell_slow_1p08V_125C) { max_transition : 2.5074; capacitance : 0.00460823; rise_capacitance : 0.00462816; - rise_capacitance_range (0.00462816, 0.00462816); + rise_capacitance_range (0.00416025, 0.00515401); fall_capacitance : 0.0045883; - fall_capacitance_range (0.0045883, 0.0045883); + fall_capacitance_range (0.00425884, 0.00483719); timing () { related_pin : "CLK"; timing_type : min_pulse_width; @@ -32310,11 +32456,12 @@ library (sg13g2_stdcell_slow_1p08V_125C) { max_transition : 2.5074; capacitance : 0.00181841; rise_capacitance : 0.00217509; - rise_capacitance_range (0.00217509, 0.00217509); + rise_capacitance_range (0.00188897, 0.00231858); fall_capacitance : 0.00146173; - fall_capacitance_range (0.00146173, 0.00146173); + fall_capacitance_range (0.00146173, 0.00240672); timing () { related_pin : "CLK"; + sdf_edges : both_edges; timing_type : hold_rising; rise_constraint (CONSTRAINT_4x4) { index_1 ("0.0186, 0.51636, 1.263, 2.5074"); @@ -32339,6 +32486,7 @@ library (sg13g2_stdcell_slow_1p08V_125C) { } timing () { related_pin : "CLK"; + sdf_edges : both_edges; timing_type : setup_rising; rise_constraint (CONSTRAINT_4x4) { index_1 ("0.0186, 0.51636, 1.263, 2.5074"); @@ -32397,11 +32545,12 @@ library (sg13g2_stdcell_slow_1p08V_125C) { max_transition : 2.5074; capacitance : 0.00217686; rise_capacitance : 0.00215817; - rise_capacitance_range (0.00215817, 0.00215817); + rise_capacitance_range (0.00202732, 0.00225961); fall_capacitance : 0.00219555; - fall_capacitance_range (0.00219555, 0.00219555); + fall_capacitance_range (0.00201619, 0.0023806); timing () { related_pin : "CLK"; + sdf_edges : both_edges; timing_type : hold_rising; rise_constraint (CONSTRAINT_4x4) { index_1 ("0.0186, 0.51636, 1.263, 2.5074"); @@ -32426,6 +32575,7 @@ library (sg13g2_stdcell_slow_1p08V_125C) { } timing () { related_pin : "CLK"; + sdf_edges : both_edges; timing_type : setup_rising; rise_constraint (CONSTRAINT_4x4) { index_1 ("0.0186, 0.51636, 1.263, 2.5074"); @@ -32466,7 +32616,7 @@ library (sg13g2_stdcell_slow_1p08V_125C) { } cell (sg13g2_tiehi) { area : 7.2576; - cell_footprint : "tie1"; + cell_footprint : "tiehi"; cell_leakage_power : 14.3388; pin (L_HI) { direction : "output"; @@ -32476,7 +32626,7 @@ library (sg13g2_stdcell_slow_1p08V_125C) { } cell (sg13g2_tielo) { area : 7.2576; - cell_footprint : "tie0"; + cell_footprint : "tielo"; cell_leakage_power : 12.6011; pin (L_LO) { direction : "output"; @@ -32486,7 +32636,7 @@ library (sg13g2_stdcell_slow_1p08V_125C) { } cell (sg13g2_xnor2_1) { area : 14.5152; - cell_footprint : "xnor2_1"; + cell_footprint : "xnor2"; cell_leakage_power : 857.223; leakage_power () { value : 863.231; @@ -33043,23 +33193,23 @@ library (sg13g2_stdcell_slow_1p08V_125C) { max_transition : 2.5074; capacitance : 0.00519616; rise_capacitance : 0.00524664; - rise_capacitance_range (0.00524664, 0.00524664); + rise_capacitance_range (0.00462678, 0.00632694); fall_capacitance : 0.00514567; - fall_capacitance_range (0.00514567, 0.00514567); + fall_capacitance_range (0.00455424, 0.00609896); } pin (B) { direction : "input"; max_transition : 2.5074; capacitance : 0.00479228; rise_capacitance : 0.00481824; - rise_capacitance_range (0.00481824, 0.00481824); + rise_capacitance_range (0.00416546, 0.00556204); fall_capacitance : 0.00476633; - fall_capacitance_range (0.00476633, 0.00476633); + fall_capacitance_range (0.00414032, 0.00532668); } } cell (sg13g2_xor2_1) { area : 14.5152; - cell_footprint : "xor2_1"; + cell_footprint : "xor2"; cell_leakage_power : 861.635; leakage_power () { value : 674.436; @@ -33616,18 +33766,18 @@ library (sg13g2_stdcell_slow_1p08V_125C) { max_transition : 2.5074; capacitance : 0.00531493; rise_capacitance : 0.00541231; - rise_capacitance_range (0.00541231, 0.00541231); + rise_capacitance_range (0.00478448, 0.006253); fall_capacitance : 0.00521755; - fall_capacitance_range (0.00521755, 0.00521755); + fall_capacitance_range (0.0045606, 0.00647646); } pin (B) { direction : "input"; max_transition : 2.5074; capacitance : 0.00483906; rise_capacitance : 0.00492934; - rise_capacitance_range (0.00492934, 0.00492934); + rise_capacitance_range (0.00425643, 0.00556846); fall_capacitance : 0.00474878; - fall_capacitance_range (0.00474878, 0.00474878); + fall_capacitance_range (0.00419741, 0.00538214); } } } diff --git a/flow/platforms/ihp-sg13g2/lib/sg13g2_stdcell_slow_1p35V_125C.lib b/flow/platforms/ihp-sg13g2/lib/sg13g2_stdcell_slow_1p35V_125C.lib index c63f5ced87..854d22118b 100644 --- a/flow/platforms/ihp-sg13g2/lib/sg13g2_stdcell_slow_1p35V_125C.lib +++ b/flow/platforms/ihp-sg13g2/lib/sg13g2_stdcell_slow_1p35V_125C.lib @@ -18,8 +18,8 @@ library (sg13g2_stdcell_slow_1p35V_125C) { comment : "IHP Microelectronics GmbH, 2025"; - date : "$Date: Fri Jun 13 09:39:46 2025 $"; - revision : "$Revision: 0.1.3 $"; + date : "$Date: Tue Nov 4 14:39:22 2025 $"; + revision : "$Revision: 0.1.4 $"; delay_model : table_lookup; capacitive_load_unit (1,pf); current_unit : "1uA"; @@ -210,7 +210,7 @@ library (sg13g2_stdcell_slow_1p35V_125C) { } cell (sg13g2_a21o_1) { area : 12.7008; - cell_footprint : "AO21"; + cell_footprint : "a21o"; cell_leakage_power : 1032.39; leakage_power () { value : 999.305; @@ -483,7 +483,7 @@ library (sg13g2_stdcell_slow_1p35V_125C) { } timing () { related_pin : "B1"; - sdf_cond : "A1 == 1'b1 & A2 == 1'b0"; + sdf_cond : "A1 == 1'b1 && A2 == 1'b0"; timing_sense : positive_unate; timing_type : combinational; when : "(A1 * !A2)"; @@ -542,7 +542,7 @@ library (sg13g2_stdcell_slow_1p35V_125C) { } timing () { related_pin : "B1"; - sdf_cond : "A1 == 1'b0 & A2 == 1'b1"; + sdf_cond : "A1 == 1'b0 && A2 == 1'b1"; timing_sense : positive_unate; timing_type : combinational; when : "(!A1 * A2)"; @@ -601,7 +601,7 @@ library (sg13g2_stdcell_slow_1p35V_125C) { } timing () { related_pin : "B1"; - sdf_cond : "A1 == 1'b0 & A2 == 1'b0"; + sdf_cond : "A1 == 1'b0 && A2 == 1'b0"; timing_sense : positive_unate; timing_type : combinational; when : "(!A1 * !A2)"; @@ -958,32 +958,32 @@ library (sg13g2_stdcell_slow_1p35V_125C) { max_transition : 2.5074; capacitance : 0.00268661; rise_capacitance : 0.00266023; - rise_capacitance_range (0.00266023, 0.00266023); + rise_capacitance_range (0.0024347, 0.00283986); fall_capacitance : 0.00271299; - fall_capacitance_range (0.00271299, 0.00271299); + fall_capacitance_range (0.00234008, 0.0030132); } pin (A2) { direction : "input"; max_transition : 2.5074; capacitance : 0.00279159; rise_capacitance : 0.00283979; - rise_capacitance_range (0.00283979, 0.00283979); + rise_capacitance_range (0.00244473, 0.00309132); fall_capacitance : 0.0027434; - fall_capacitance_range (0.0027434, 0.0027434); + fall_capacitance_range (0.00242906, 0.0029947); } pin (B1) { direction : "input"; max_transition : 2.5074; capacitance : 0.00260427; rise_capacitance : 0.00269792; - rise_capacitance_range (0.00269792, 0.00269792); + rise_capacitance_range (0.00224301, 0.00306998); fall_capacitance : 0.00251062; - fall_capacitance_range (0.00251062, 0.00251062); + fall_capacitance_range (0.00227383, 0.00271702); } } cell (sg13g2_a21o_2) { area : 14.5152; - cell_footprint : "AO21"; + cell_footprint : "a21o"; cell_leakage_power : 1473.24; leakage_power () { value : 1800.47; @@ -1256,7 +1256,7 @@ library (sg13g2_stdcell_slow_1p35V_125C) { } timing () { related_pin : "B1"; - sdf_cond : "A1 == 1'b1 & A2 == 1'b0"; + sdf_cond : "A1 == 1'b1 && A2 == 1'b0"; timing_sense : positive_unate; timing_type : combinational; when : "(A1 * !A2)"; @@ -1315,7 +1315,7 @@ library (sg13g2_stdcell_slow_1p35V_125C) { } timing () { related_pin : "B1"; - sdf_cond : "A1 == 1'b0 & A2 == 1'b1"; + sdf_cond : "A1 == 1'b0 && A2 == 1'b1"; timing_sense : positive_unate; timing_type : combinational; when : "(!A1 * A2)"; @@ -1374,7 +1374,7 @@ library (sg13g2_stdcell_slow_1p35V_125C) { } timing () { related_pin : "B1"; - sdf_cond : "A1 == 1'b0 & A2 == 1'b0"; + sdf_cond : "A1 == 1'b0 && A2 == 1'b0"; timing_sense : positive_unate; timing_type : combinational; when : "(!A1 * !A2)"; @@ -1731,27 +1731,27 @@ library (sg13g2_stdcell_slow_1p35V_125C) { max_transition : 2.5074; capacitance : 0.00286423; rise_capacitance : 0.00281677; - rise_capacitance_range (0.00281677, 0.00281677); + rise_capacitance_range (0.00258588, 0.00302978); fall_capacitance : 0.0029117; - fall_capacitance_range (0.0029117, 0.0029117); + fall_capacitance_range (0.00254618, 0.00319291); } pin (A2) { direction : "input"; max_transition : 2.5074; capacitance : 0.00287607; rise_capacitance : 0.0029132; - rise_capacitance_range (0.0029132, 0.0029132); + rise_capacitance_range (0.00247673, 0.00318925); fall_capacitance : 0.00283894; - fall_capacitance_range (0.00283894, 0.00283894); + fall_capacitance_range (0.00252971, 0.00307696); } pin (B1) { direction : "input"; max_transition : 2.5074; capacitance : 0.00271859; rise_capacitance : 0.00279887; - rise_capacitance_range (0.00279887, 0.00279887); + rise_capacitance_range (0.00238831, 0.00319852); fall_capacitance : 0.00263832; - fall_capacitance_range (0.00263832, 0.00263832); + fall_capacitance_range (0.00243391, 0.00280228); } } cell (sg13g2_a21oi_1) { @@ -1759,11 +1759,11 @@ library (sg13g2_stdcell_slow_1p35V_125C) { cell_footprint : "a21oi"; cell_leakage_power : 703.809; leakage_power () { - value : 285.066; + value : 285.067; when : "!A1&!A2&!B1&Y"; } leakage_power () { - value : 796.157; + value : 796.158; when : "!A1&!A2&B1&!Y"; } leakage_power () { @@ -1775,11 +1775,11 @@ library (sg13g2_stdcell_slow_1p35V_125C) { when : "!A1&A2&B1&!Y"; } leakage_power () { - value : 396.721; + value : 396.722; when : "A1&!A2&!B1&Y"; } leakage_power () { - value : 803.546; + value : 803.547; when : "A1&!A2&B1&!Y"; } leakage_power () { @@ -1803,52 +1803,52 @@ library (sg13g2_stdcell_slow_1p35V_125C) { index_1 ("0.0186, 0.0966, 0.174, 0.3294, 0.6408, 1.263, 2.5074"); index_2 ("0.001, 0.0234, 0.039, 0.0648, 0.108, 0.18, 0.3"); values ( \ - "0.0469791, 0.184128, 0.277638, 0.432339, 0.69121, 1.12251, 1.84136", \ - "0.0679733, 0.211383, 0.305436, 0.460432, 0.720053, 1.15081, 1.87029", \ - "0.0789738, 0.235656, 0.330681, 0.485916, 0.745131, 1.17789, 1.896", \ - "0.0919185, 0.276508, 0.377155, 0.535621, 0.795012, 1.22649, 1.94618", \ - "0.110499, 0.341006, 0.456648, 0.627514, 0.895485, 1.32881, 2.04778", \ - "0.132189, 0.43106, 0.569344, 0.769936, 1.06662, 1.52174, 2.24745", \ - "0.157533, 0.553624, 0.732821, 0.977778, 1.33083, 1.84531, 2.62028" \ + "0.0469789, 0.184105, 0.277634, 0.432335, 0.691214, 1.1225, 1.84136", \ + "0.0679732, 0.211383, 0.305452, 0.460566, 0.720053, 1.15083, 1.87028", \ + "0.0789738, 0.235658, 0.330681, 0.48592, 0.745131, 1.17789, 1.89599", \ + "0.0919185, 0.276508, 0.377155, 0.53562, 0.795012, 1.22665, 1.94616", \ + "0.110499, 0.341006, 0.456648, 0.627514, 0.895484, 1.3288, 2.04762", \ + "0.132188, 0.43106, 0.569343, 0.769936, 1.06662, 1.52175, 2.24745", \ + "0.157533, 0.553624, 0.732821, 0.977778, 1.33083, 1.84535, 2.62028" \ ); } rise_transition (TIMING_DELAY_7x7ds1) { index_1 ("0.0186, 0.0966, 0.174, 0.3294, 0.6408, 1.263, 2.5074"); index_2 ("0.001, 0.0234, 0.039, 0.0648, 0.108, 0.18, 0.3"); values ( \ - "0.0301777, 0.220974, 0.353789, 0.573404, 0.941364, 1.55447, 2.57622", \ - "0.0389729, 0.221891, 0.355942, 0.573539, 0.941861, 1.55501, 2.57623", \ - "0.0499953, 0.228224, 0.356928, 0.574928, 0.943507, 1.5556, 2.57624", \ - "0.070718, 0.249387, 0.372697, 0.582334, 0.943508, 1.55561, 2.57625", \ - "0.110261, 0.296624, 0.417673, 0.619829, 0.96541, 1.5623, 2.57937", \ - "0.173856, 0.384595, 0.511122, 0.712796, 1.04923, 1.6183, 2.60135", \ - "0.272516, 0.537899, 0.67662, 0.891742, 1.23573, 1.7975, 2.73684" \ + "0.0301784, 0.220985, 0.35379, 0.573404, 0.941376, 1.55447, 2.57622", \ + "0.0389729, 0.221891, 0.354372, 0.573731, 0.941861, 1.55501, 2.57623", \ + "0.0499953, 0.228267, 0.356927, 0.573914, 0.943506, 1.5556, 2.57624", \ + "0.070718, 0.249386, 0.372697, 0.582335, 0.943507, 1.55561, 2.57625", \ + "0.110261, 0.296624, 0.417673, 0.61983, 0.96541, 1.56221, 2.57781", \ + "0.173856, 0.384595, 0.511121, 0.712796, 1.04923, 1.61831, 2.60135", \ + "0.272517, 0.537898, 0.676619, 0.891742, 1.23573, 1.79772, 2.73684" \ ); } cell_fall (TIMING_DELAY_7x7ds1) { index_1 ("0.0186, 0.0966, 0.174, 0.3294, 0.6408, 1.263, 2.5074"); index_2 ("0.001, 0.0234, 0.039, 0.0648, 0.108, 0.18, 0.3"); values ( \ - "0.0401011, 0.140681, 0.20866, 0.320576, 0.507839, 0.8192, 1.33833", \ - "0.0648042, 0.177638, 0.245934, 0.357732, 0.544797, 0.856584, 1.37559", \ - "0.0799575, 0.21029, 0.282256, 0.395531, 0.582624, 0.893963, 1.4134", \ - "0.101425, 0.261765, 0.344202, 0.466661, 0.658194, 0.969764, 1.48867", \ - "0.129317, 0.334231, 0.435906, 0.5805, 0.79485, 1.11837, 1.63823", \ - "0.167056, 0.430705, 0.562809, 0.743694, 1.00281, 1.37517, 1.93018", \ - "0.216167, 0.558697, 0.728117, 0.967152, 1.29696, 1.75628, 2.40783" \ + "0.0401014, 0.140688, 0.208593, 0.320577, 0.507575, 0.819384, 1.33832", \ + "0.0648042, 0.177631, 0.245879, 0.357733, 0.544782, 0.856813, 1.3756", \ + "0.0799575, 0.2103, 0.282256, 0.395561, 0.582624, 0.894146, 1.41342", \ + "0.101425, 0.261765, 0.344202, 0.46666, 0.658214, 0.969822, 1.48863", \ + "0.129317, 0.334231, 0.435906, 0.5805, 0.79485, 1.11837, 1.63822", \ + "0.167057, 0.430705, 0.562571, 0.743694, 1.00281, 1.37516, 1.93018", \ + "0.216167, 0.558697, 0.728117, 0.967152, 1.29696, 1.75628, 2.40772" \ ); } fall_transition (TIMING_DELAY_7x7ds1) { index_1 ("0.0186, 0.0966, 0.174, 0.3294, 0.6408, 1.263, 2.5074"); index_2 ("0.001, 0.0234, 0.039, 0.0648, 0.108, 0.18, 0.3"); values ( \ - "0.0301269, 0.159822, 0.250502, 0.3998, 0.649867, 1.06553, 1.7591", \ - "0.0442641, 0.165547, 0.252283, 0.399801, 0.649868, 1.06629, 1.76042", \ - "0.0575944, 0.18096, 0.263766, 0.405602, 0.650783, 1.06739, 1.76043", \ - "0.0795486, 0.21749, 0.298883, 0.433132, 0.666626, 1.07084, 1.76044", \ - "0.113665, 0.281383, 0.368345, 0.505298, 0.727381, 1.10909, 1.7742", \ - "0.170694, 0.383986, 0.488108, 0.640506, 0.87263, 1.2441, 1.86923", \ - "0.265336, 0.545141, 0.678776, 0.862497, 1.13274, 1.52808, 2.1531" \ + "0.030141, 0.159841, 0.250216, 0.399803, 0.649701, 1.06637, 1.7591", \ + "0.0442641, 0.165569, 0.252563, 0.399804, 0.649724, 1.06638, 1.76042", \ + "0.0575944, 0.181003, 0.263766, 0.405536, 0.650783, 1.06639, 1.76043", \ + "0.0795486, 0.21749, 0.298883, 0.433132, 0.666452, 1.07077, 1.76044", \ + "0.113665, 0.281383, 0.368345, 0.505298, 0.72738, 1.10909, 1.7742", \ + "0.170694, 0.383986, 0.487915, 0.640505, 0.87263, 1.2441, 1.86923", \ + "0.265336, 0.545142, 0.678776, 0.862497, 1.13274, 1.52808, 2.15301" \ ); } } @@ -1860,12 +1860,12 @@ library (sg13g2_stdcell_slow_1p35V_125C) { index_1 ("0.0186, 0.0966, 0.174, 0.3294, 0.6408, 1.263, 2.5074"); index_2 ("0.001, 0.0234, 0.039, 0.0648, 0.108, 0.18, 0.3"); values ( \ - "0.0555811, 0.192438, 0.286022, 0.441048, 0.700318, 1.13292, 1.85348", \ - "0.0789808, 0.220183, 0.314267, 0.469379, 0.72946, 1.16156, 1.88237", \ - "0.0929325, 0.245043, 0.33981, 0.49509, 0.754904, 1.18814, 1.90744", \ - "0.110378, 0.287054, 0.387031, 0.545036, 0.804836, 1.23714, 1.95826", \ - "0.13629, 0.353694, 0.467937, 0.638099, 0.905757, 1.33974, 2.05964", \ - "0.170261, 0.448088, 0.584178, 0.782842, 1.07812, 1.53256, 2.25956", \ + "0.0555556, 0.192438, 0.286025, 0.441048, 0.700344, 1.13292, 1.85353", \ + "0.078981, 0.2202, 0.314281, 0.469358, 0.729444, 1.16155, 1.88235", \ + "0.0929324, 0.245043, 0.33981, 0.49509, 0.754961, 1.18812, 1.90828", \ + "0.110378, 0.287054, 0.387031, 0.545036, 0.804836, 1.23747, 1.9583", \ + "0.13629, 0.353694, 0.467937, 0.638099, 0.905756, 1.33965, 2.05981", \ + "0.170261, 0.448087, 0.584178, 0.782842, 1.07812, 1.53256, 2.2596", \ "0.217163, 0.581018, 0.754709, 0.995071, 1.34434, 1.85818, 2.63387" \ ); } @@ -1873,39 +1873,39 @@ library (sg13g2_stdcell_slow_1p35V_125C) { index_1 ("0.0186, 0.0966, 0.174, 0.3294, 0.6408, 1.263, 2.5074"); index_2 ("0.001, 0.0234, 0.039, 0.0648, 0.108, 0.18, 0.3"); values ( \ - "0.0389542, 0.231257, 0.364225, 0.584913, 0.954052, 1.5686, 2.59304", \ - "0.0463395, 0.231593, 0.367441, 0.584914, 0.954053, 1.56861, 2.59305", \ - "0.0569907, 0.237628, 0.367442, 0.585941, 0.954138, 1.5701, 2.59306", \ - "0.077903, 0.258127, 0.382344, 0.593277, 0.955601, 1.57011, 2.59307", \ - "0.115329, 0.304502, 0.426625, 0.629864, 0.977094, 1.57611, 2.59912", \ - "0.174315, 0.391584, 0.518458, 0.722807, 1.05981, 1.63117, 2.61785", \ - "0.264844, 0.540442, 0.681145, 0.897268, 1.24409, 1.80843, 2.75183" \ + "0.0389304, 0.231257, 0.364224, 0.584913, 0.953993, 1.5686, 2.59304", \ + "0.0463397, 0.231672, 0.365557, 0.584914, 0.953994, 1.56861, 2.59305", \ + "0.0569908, 0.237628, 0.367107, 0.58594, 0.954355, 1.5701, 2.59389", \ + "0.0779029, 0.258127, 0.382343, 0.593275, 0.955602, 1.57011, 2.5939", \ + "0.115328, 0.304502, 0.426625, 0.629864, 0.977093, 1.57588, 2.59542", \ + "0.174315, 0.391583, 0.518459, 0.722806, 1.05981, 1.63117, 2.61776", \ + "0.264844, 0.540443, 0.681145, 0.897267, 1.24409, 1.80843, 2.75182" \ ); } cell_fall (TIMING_DELAY_7x7ds1) { index_1 ("0.0186, 0.0966, 0.174, 0.3294, 0.6408, 1.263, 2.5074"); index_2 ("0.001, 0.0234, 0.039, 0.0648, 0.108, 0.18, 0.3"); values ( \ - "0.0446789, 0.14497, 0.212891, 0.325003, 0.511934, 0.82365, 1.34263", \ - "0.0678323, 0.176542, 0.244857, 0.356872, 0.544074, 0.855852, 1.37489", \ - "0.082538, 0.204168, 0.275013, 0.388272, 0.575635, 0.887323, 1.40694", \ - "0.102517, 0.249626, 0.328112, 0.447851, 0.638813, 0.951352, 1.47095", \ - "0.127821, 0.315211, 0.408731, 0.544728, 0.751545, 1.07321, 1.59462", \ + "0.0446823, 0.144968, 0.21289, 0.324818, 0.511932, 0.823492, 1.34263", \ + "0.0678323, 0.176542, 0.244891, 0.356914, 0.54401, 0.856208, 1.37489", \ + "0.0825379, 0.204168, 0.275014, 0.388262, 0.575634, 0.88751, 1.40693", \ + "0.102517, 0.249626, 0.328112, 0.447851, 0.638812, 0.951352, 1.47068", \ + "0.12782, 0.315211, 0.408731, 0.544727, 0.751545, 1.07321, 1.59462", \ "0.162291, 0.405703, 0.526029, 0.692598, 0.932193, 1.28756, 1.83502", \ - "0.206482, 0.527612, 0.682588, 0.900557, 1.20279, 1.62362, 2.2402" \ + "0.206482, 0.527612, 0.682587, 0.900557, 1.20279, 1.62362, 2.2402" \ ); } fall_transition (TIMING_DELAY_7x7ds1) { index_1 ("0.0186, 0.0966, 0.174, 0.3294, 0.6408, 1.263, 2.5074"); index_2 ("0.001, 0.0234, 0.039, 0.0648, 0.108, 0.18, 0.3"); values ( \ - "0.0298896, 0.160009, 0.250205, 0.399781, 0.649, 1.06636, 1.76064", \ - "0.0391655, 0.163346, 0.251769, 0.40069, 0.649001, 1.06637, 1.76065", \ - "0.0496646, 0.173467, 0.258833, 0.403691, 0.649874, 1.06655, 1.76066", \ - "0.0700595, 0.198992, 0.282149, 0.421148, 0.660058, 1.06885, 1.76067", \ - "0.10359, 0.249386, 0.334606, 0.471592, 0.701201, 1.09396, 1.76979", \ - "0.158776, 0.336075, 0.430355, 0.575498, 0.803986, 1.18539, 1.83131", \ - "0.24582, 0.476752, 0.594183, 0.760338, 1.00827, 1.39332, 2.02784" \ + "0.0298574, 0.16001, 0.250201, 0.399666, 0.649, 1.06651, 1.76064", \ + "0.0391655, 0.163345, 0.251847, 0.399768, 0.649781, 1.06666, 1.76065", \ + "0.0496647, 0.173467, 0.258691, 0.403296, 0.650822, 1.06667, 1.76066", \ + "0.0700595, 0.198992, 0.282149, 0.421149, 0.660055, 1.06885, 1.76067", \ + "0.10359, 0.249386, 0.334605, 0.471592, 0.701201, 1.09396, 1.76979", \ + "0.158776, 0.336075, 0.430355, 0.575498, 0.803986, 1.18539, 1.8313", \ + "0.24582, 0.476752, 0.594182, 0.760337, 1.00827, 1.39332, 2.02784" \ ); } } @@ -1919,52 +1919,52 @@ library (sg13g2_stdcell_slow_1p35V_125C) { index_1 ("0.0186, 0.0966, 0.174, 0.3294, 0.6408, 1.263, 2.5074"); index_2 ("0.001, 0.0234, 0.039, 0.0648, 0.108, 0.18, 0.3"); values ( \ - "0.0446056, 0.183381, 0.277309, 0.43262, 0.692182, 1.12454, 1.84514", \ - "0.0692652, 0.214483, 0.308733, 0.464031, 0.724398, 1.15689, 1.87854", \ - "0.0854907, 0.247179, 0.342232, 0.497472, 0.757193, 1.19051, 1.91078", \ - "0.108113, 0.302983, 0.405818, 0.564281, 0.823336, 1.2558, 1.97625", \ - "0.144083, 0.388409, 0.510955, 0.687658, 0.95777, 1.39034, 2.10923", \ - "0.192728, 0.504638, 0.6583, 0.876211, 1.18751, 1.65035, 2.37617", \ - "0.264101, 0.668574, 0.865355, 1.13822, 1.5307, 2.07897, 2.87969" \ + "0.0446147, 0.183386, 0.277309, 0.432799, 0.692142, 1.12454, 1.84518", \ + "0.0691555, 0.214481, 0.308624, 0.464197, 0.724394, 1.15673, 1.87853", \ + "0.0854908, 0.247179, 0.342229, 0.497473, 0.757185, 1.19051, 1.91053", \ + "0.108113, 0.302983, 0.405818, 0.564281, 0.823323, 1.25579, 1.97625", \ + "0.144083, 0.388409, 0.510954, 0.687658, 0.95777, 1.39039, 2.10923", \ + "0.192728, 0.504638, 0.6583, 0.876211, 1.18739, 1.65037, 2.37617", \ + "0.264101, 0.668574, 0.865355, 1.13822, 1.5307, 2.07897, 2.87968" \ ); } rise_transition (TIMING_DELAY_7x7ds1) { index_1 ("0.0186, 0.0966, 0.174, 0.3294, 0.6408, 1.263, 2.5074"); index_2 ("0.001, 0.0234, 0.039, 0.0648, 0.108, 0.18, 0.3"); values ( \ - "0.0389562, 0.231114, 0.3644, 0.584725, 0.953686, 1.56847, 2.59304", \ - "0.0525552, 0.232237, 0.36612, 0.584726, 0.954149, 1.56899, 2.59336", \ - "0.0659114, 0.24261, 0.369039, 0.585514, 0.954294, 1.56902, 2.59337", \ - "0.0877069, 0.274373, 0.393614, 0.598578, 0.956843, 1.56903, 2.59338", \ - "0.12166, 0.337525, 0.458879, 0.654501, 0.99092, 1.58033, 2.59462", \ - "0.179302, 0.441878, 0.581042, 0.786073, 1.1146, 1.66549, 2.63077", \ - "0.276619, 0.608004, 0.772358, 1.01611, 1.37538, 1.92892, 2.83414" \ + "0.038986, 0.231114, 0.364399, 0.584646, 0.953598, 1.56847, 2.59312", \ + "0.0526167, 0.232233, 0.3644, 0.584681, 0.95415, 1.56899, 2.59335", \ + "0.0659114, 0.24261, 0.369047, 0.585416, 0.954273, 1.56902, 2.59362", \ + "0.0877069, 0.274373, 0.393614, 0.598577, 0.95686, 1.56903, 2.59363", \ + "0.12166, 0.337523, 0.45888, 0.6545, 0.99092, 1.58037, 2.59364", \ + "0.179303, 0.441877, 0.581042, 0.786076, 1.11484, 1.66551, 2.63076", \ + "0.276619, 0.608004, 0.772357, 1.01611, 1.37538, 1.92892, 2.83424" \ ); } cell_fall (TIMING_DELAY_7x7ds1) { index_1 ("0.0186, 0.0966, 0.174, 0.3294, 0.6408, 1.263, 2.5074"); index_2 ("0.001, 0.0234, 0.039, 0.0648, 0.108, 0.18, 0.3"); values ( \ - "0.0225572, 0.082311, 0.122416, 0.188573, 0.29938, 0.483475, 0.790229", \ - "0.0400611, 0.122997, 0.165595, 0.232432, 0.34309, 0.527383, 0.834068", \ - "0.0491533, 0.153238, 0.202129, 0.27395, 0.386704, 0.570693, 0.877554", \ - "0.0606939, 0.197305, 0.258811, 0.343913, 0.468302, 0.658443, 0.965621", \ - "0.0726168, 0.256549, 0.337975, 0.446724, 0.597694, 0.814713, 1.13595", \ - "0.0832671, 0.330227, 0.44127, 0.588351, 0.784621, 1.05279, 1.43127", \ - "0.0889202, 0.422031, 0.568375, 0.76834, 1.03712, 1.39037, 1.87096" \ + "0.0225571, 0.0823262, 0.12237, 0.188576, 0.299381, 0.483521, 0.790227", \ + "0.0400611, 0.123013, 0.165595, 0.232431, 0.343111, 0.527319, 0.83407", \ + "0.0491533, 0.153211, 0.202151, 0.27395, 0.386701, 0.570709, 0.87753", \ + "0.0606939, 0.197305, 0.258811, 0.343913, 0.468302, 0.658442, 0.965656", \ + "0.0726168, 0.256549, 0.337975, 0.446724, 0.597694, 0.814713, 1.13586", \ + "0.083265, 0.330227, 0.44127, 0.588351, 0.784622, 1.05279, 1.43127", \ + "0.0889202, 0.421998, 0.568379, 0.768341, 1.03712, 1.39037, 1.87112" \ ); } fall_transition (TIMING_DELAY_7x7ds1) { index_1 ("0.0186, 0.0966, 0.174, 0.3294, 0.6408, 1.263, 2.5074"); index_2 ("0.001, 0.0234, 0.039, 0.0648, 0.108, 0.18, 0.3"); values ( \ - "0.0167873, 0.0929403, 0.1461, 0.234115, 0.381881, 0.627141, 1.03677", \ - "0.0373074, 0.105549, 0.153552, 0.237123, 0.38279, 0.627142, 1.03746", \ - "0.0525246, 0.125416, 0.171898, 0.250708, 0.389255, 0.628938, 1.03747", \ - "0.0775905, 0.164406, 0.213145, 0.290782, 0.420471, 0.647278, 1.04257", \ - "0.1181, 0.225835, 0.28408, 0.36806, 0.501349, 0.71502, 1.08507", \ - "0.184865, 0.327085, 0.399912, 0.502741, 0.649976, 0.878385, 1.23483", \ - "0.294307, 0.488266, 0.585649, 0.719031, 0.903129, 1.16822, 1.55289" \ + "0.016816, 0.0929191, 0.14609, 0.234114, 0.381882, 0.627565, 1.03678", \ + "0.0373074, 0.105556, 0.153552, 0.237137, 0.382801, 0.627566, 1.03745", \ + "0.0525246, 0.125432, 0.171889, 0.250811, 0.389254, 0.628958, 1.03746", \ + "0.0775905, 0.164406, 0.213145, 0.290782, 0.420471, 0.647271, 1.0426", \ + "0.1181, 0.225835, 0.28408, 0.36806, 0.501348, 0.71502, 1.08548", \ + "0.18486, 0.327084, 0.399913, 0.502741, 0.649976, 0.878385, 1.23483", \ + "0.294307, 0.488008, 0.585644, 0.720075, 0.903129, 1.16822, 1.55089" \ ); } } @@ -1978,12 +1978,12 @@ library (sg13g2_stdcell_slow_1p35V_125C) { index_1 ("0.0186, 0.0966, 0.174, 0.3294, 0.6408, 1.263, 2.5074"); index_2 ("0.001, 0.0234, 0.039, 0.0648, 0.108, 0.18, 0.3"); values ( \ - "0.0346017, 0.172698, 0.266418, 0.421137, 0.680024, 1.11134, 1.8302", \ - "0.0554808, 0.203877, 0.297716, 0.452626, 0.71233, 1.14362, 1.86352", \ - "0.0679532, 0.236284, 0.331236, 0.48604, 0.745031, 1.17772, 1.89514", \ - "0.0855985, 0.290675, 0.394224, 0.552845, 0.81145, 1.24236, 1.96143", \ - "0.115274, 0.373041, 0.497419, 0.675209, 0.945524, 1.37748, 2.09427", \ - "0.155214, 0.485679, 0.641557, 0.861821, 1.17387, 1.63664, 2.36135", \ + "0.0346029, 0.172693, 0.26642, 0.42114, 0.680047, 1.11133, 1.8298", \ + "0.0554808, 0.203873, 0.297716, 0.452624, 0.712331, 1.14328, 1.86353", \ + "0.0679532, 0.236295, 0.331239, 0.486025, 0.745029, 1.17772, 1.89492", \ + "0.0855985, 0.290675, 0.394224, 0.552845, 0.811448, 1.24212, 1.96142", \ + "0.115274, 0.373041, 0.497418, 0.675209, 0.945522, 1.37745, 2.09443", \ + "0.155214, 0.485504, 0.641557, 0.861821, 1.17387, 1.63664, 2.36135", \ "0.214722, 0.643103, 0.844072, 1.1189, 1.5134, 2.06389, 2.8639" \ ); } @@ -1991,39 +1991,39 @@ library (sg13g2_stdcell_slow_1p35V_125C) { index_1 ("0.0186, 0.0966, 0.174, 0.3294, 0.6408, 1.263, 2.5074"); index_2 ("0.001, 0.0234, 0.039, 0.0648, 0.108, 0.18, 0.3"); values ( \ - "0.0302348, 0.220994, 0.353848, 0.573464, 0.941361, 1.55461, 2.57623", \ - "0.0454484, 0.222742, 0.354155, 0.573966, 0.942324, 1.55462, 2.57648", \ - "0.0583273, 0.234002, 0.359124, 0.575276, 0.942325, 1.55582, 2.57649", \ - "0.0780174, 0.266542, 0.384785, 0.587995, 0.94459, 1.55583, 2.5765", \ - "0.111904, 0.330642, 0.450931, 0.645369, 0.980012, 1.56705, 2.57651", \ - "0.167661, 0.433645, 0.573445, 0.777826, 1.10507, 1.65307, 2.61612", \ - "0.263797, 0.596977, 0.762513, 1.00784, 1.3651, 1.91718, 2.82033" \ + "0.0302354, 0.221179, 0.353847, 0.573464, 0.941364, 1.55461, 2.5768", \ + "0.0454483, 0.222675, 0.354155, 0.573465, 0.942324, 1.555, 2.57681", \ + "0.0583273, 0.234001, 0.359129, 0.574608, 0.942325, 1.55583, 2.57695", \ + "0.0780173, 0.266541, 0.384785, 0.587994, 0.944589, 1.55584, 2.57696", \ + "0.111904, 0.330643, 0.450931, 0.645369, 0.980011, 1.56692, 2.57784", \ + "0.167661, 0.433507, 0.573445, 0.777825, 1.10507, 1.65307, 2.61445", \ + "0.263797, 0.596978, 0.762513, 1.00784, 1.3651, 1.91718, 2.82032" \ ); } cell_fall (TIMING_DELAY_7x7ds1) { index_1 ("0.0186, 0.0966, 0.174, 0.3294, 0.6408, 1.263, 2.5074"); index_2 ("0.001, 0.0234, 0.039, 0.0648, 0.108, 0.18, 0.3"); values ( \ - "0.0222556, 0.0817897, 0.121687, 0.187574, 0.298088, 0.481729, 0.788106", \ - "0.0392927, 0.122374, 0.16483, 0.231464, 0.341741, 0.526136, 0.831768", \ - "0.0478218, 0.152401, 0.201236, 0.272983, 0.385253, 0.569266, 0.875383", \ - "0.0583032, 0.19603, 0.257488, 0.342567, 0.466764, 0.656459, 0.963491", \ + "0.0222555, 0.0817889, 0.121687, 0.187567, 0.298076, 0.481728, 0.788113", \ + "0.0392927, 0.122378, 0.16483, 0.231466, 0.341739, 0.526128, 0.831766", \ + "0.0478205, 0.152401, 0.201227, 0.273023, 0.38525, 0.569215, 0.875389", \ + "0.0583032, 0.19603, 0.257488, 0.342567, 0.466764, 0.656459, 0.963401", \ "0.0679495, 0.254298, 0.335919, 0.444657, 0.5956, 0.812446, 1.13348", \ - "0.0735829, 0.326028, 0.437489, 0.584913, 0.781303, 1.04985, 1.42859", \ - "0.0735839, 0.413914, 0.561137, 0.762058, 1.03254, 1.38681, 1.86733" \ + "0.0735829, 0.326027, 0.437462, 0.584913, 0.781303, 1.04985, 1.42859", \ + "0.0735839, 0.413671, 0.561137, 0.76242, 1.03254, 1.38681, 1.8677" \ ); } fall_transition (TIMING_DELAY_7x7ds1) { index_1 ("0.0186, 0.0966, 0.174, 0.3294, 0.6408, 1.263, 2.5074"); index_2 ("0.001, 0.0234, 0.039, 0.0648, 0.108, 0.18, 0.3"); values ( \ - "0.0126653, 0.0872317, 0.140429, 0.228731, 0.376181, 0.621776, 1.03142", \ - "0.0276401, 0.0998452, 0.147963, 0.231512, 0.376551, 0.622698, 1.03207", \ - "0.03985, 0.119127, 0.166185, 0.245058, 0.38345, 0.623592, 1.03208", \ - "0.0598218, 0.15685, 0.206789, 0.284849, 0.414839, 0.641562, 1.03796", \ - "0.0924933, 0.216667, 0.276363, 0.361372, 0.49545, 0.709278, 1.07969", \ - "0.147461, 0.313757, 0.389324, 0.494066, 0.642834, 0.870216, 1.22976", \ - "0.240531, 0.469092, 0.571611, 0.709794, 0.894991, 1.15865, 1.54565" \ + "0.0126653, 0.0872314, 0.140428, 0.228723, 0.376182, 0.621776, 1.03142", \ + "0.0276401, 0.0998591, 0.147963, 0.231399, 0.376549, 0.622695, 1.03206", \ + "0.0398507, 0.119127, 0.166176, 0.245155, 0.383444, 0.623522, 1.03207", \ + "0.0598218, 0.15685, 0.206789, 0.284849, 0.414812, 0.641562, 1.03793", \ + "0.0924932, 0.216668, 0.276363, 0.361372, 0.49545, 0.709296, 1.07969", \ + "0.147461, 0.313758, 0.389119, 0.494064, 0.642829, 0.870216, 1.22976", \ + "0.24053, 0.469386, 0.571612, 0.709508, 0.89499, 1.15865, 1.54568" \ ); } } @@ -2037,52 +2037,52 @@ library (sg13g2_stdcell_slow_1p35V_125C) { index_1 ("0.0186, 0.0966, 0.174, 0.3294, 0.6408, 1.263, 2.5074"); index_2 ("0.001, 0.0234, 0.039, 0.0648, 0.108, 0.18, 0.3"); values ( \ - "0.0285086, 0.130592, 0.199932, 0.314391, 0.505847, 0.82496, 1.35669", \ - "0.0484506, 0.165583, 0.235026, 0.349638, 0.541191, 0.860892, 1.39279", \ - "0.0596306, 0.198671, 0.27129, 0.386297, 0.577901, 0.89716, 1.42923", \ - "0.0749158, 0.250979, 0.334403, 0.457364, 0.650414, 0.968911, 1.50059", \ + "0.0285095, 0.13059, 0.199936, 0.314409, 0.505845, 0.824961, 1.35668", \ + "0.0484506, 0.165583, 0.235026, 0.349637, 0.54166, 0.860895, 1.39282", \ + "0.0596306, 0.198671, 0.27129, 0.386304, 0.577857, 0.897151, 1.4293", \ + "0.0749157, 0.250979, 0.334403, 0.457364, 0.650413, 0.969182, 1.50058", \ "0.0996333, 0.326729, 0.432287, 0.577377, 0.78991, 1.11585, 1.64677", \ "0.130427, 0.42871, 0.563363, 0.750791, 1.01004, 1.37883, 1.93405", \ - "0.172778, 0.565717, 0.744765, 0.985835, 1.32103, 1.78639, 2.43254" \ + "0.172778, 0.565716, 0.744765, 0.985834, 1.32102, 1.78639, 2.43253" \ ); } rise_transition (TIMING_DELAY_7x7ds1) { index_1 ("0.0186, 0.0966, 0.174, 0.3294, 0.6408, 1.263, 2.5074"); index_2 ("0.001, 0.0234, 0.039, 0.0648, 0.108, 0.18, 0.3"); values ( \ - "0.0221134, 0.16466, 0.264259, 0.429156, 0.705292, 1.16522, 1.93194", \ - "0.0385743, 0.168652, 0.265332, 0.429157, 0.705368, 1.16523, 1.93195", \ - "0.0512211, 0.183838, 0.274551, 0.432295, 0.705369, 1.16554, 1.93196", \ - "0.0706213, 0.219533, 0.306911, 0.454004, 0.714312, 1.16624, 1.93197", \ - "0.104395, 0.284687, 0.376925, 0.522467, 0.765176, 1.19181, 1.93857", \ - "0.159536, 0.385683, 0.49838, 0.659486, 0.907009, 1.30862, 2.00572", \ - "0.25387, 0.551945, 0.687699, 0.884286, 1.17257, 1.59364, 2.26397" \ + "0.0221131, 0.164659, 0.264258, 0.429157, 0.705236, 1.16521, 1.93194", \ + "0.0385743, 0.168652, 0.265333, 0.429158, 0.705759, 1.16522, 1.93195", \ + "0.0512211, 0.183838, 0.274551, 0.432299, 0.70576, 1.16552, 1.93196", \ + "0.0706213, 0.219534, 0.306911, 0.454004, 0.714311, 1.16665, 1.93197", \ + "0.104395, 0.284687, 0.376924, 0.522468, 0.765176, 1.19181, 1.94746", \ + "0.159536, 0.385683, 0.49838, 0.659485, 0.90701, 1.30861, 2.00572", \ + "0.253871, 0.551945, 0.6877, 0.884285, 1.17257, 1.59364, 2.26398" \ ); } cell_fall (TIMING_DELAY_7x7ds1) { index_1 ("0.0186, 0.0966, 0.174, 0.3294, 0.6408, 1.263, 2.5074"); index_2 ("0.001, 0.0234, 0.039, 0.0648, 0.108, 0.18, 0.3"); values ( \ - "0.021973, 0.0815705, 0.121452, 0.187355, 0.297876, 0.481527, 0.787887", \ - "0.038869, 0.121931, 0.164524, 0.231113, 0.341417, 0.525532, 0.831429", \ - "0.0476547, 0.151978, 0.200846, 0.272496, 0.384969, 0.568481, 0.875116", \ - "0.0591723, 0.195742, 0.257181, 0.342207, 0.466427, 0.656156, 0.963047", \ - "0.0710704, 0.254625, 0.33583, 0.444484, 0.595308, 0.812415, 1.1333", \ - "0.0822072, 0.328949, 0.438943, 0.585747, 0.781647, 1.04983, 1.4283", \ - "0.0863206, 0.423248, 0.568561, 0.766565, 1.03514, 1.38813, 1.86839" \ + "0.0219731, 0.0815542, 0.12145, 0.187358, 0.297881, 0.481535, 0.787723", \ + "0.038869, 0.121931, 0.164524, 0.231113, 0.34142, 0.525103, 0.831401", \ + "0.0476547, 0.151978, 0.200855, 0.272501, 0.385004, 0.568489, 0.874997", \ + "0.0591723, 0.195742, 0.257181, 0.342207, 0.466427, 0.656167, 0.963126", \ + "0.0710705, 0.254625, 0.33583, 0.444484, 0.595308, 0.812415, 1.1333", \ + "0.0822071, 0.328949, 0.438942, 0.585747, 0.781647, 1.04983, 1.4283", \ + "0.0863207, 0.423615, 0.568557, 0.766566, 1.03514, 1.38813, 1.86839" \ ); } fall_transition (TIMING_DELAY_7x7ds1) { index_1 ("0.0186, 0.0966, 0.174, 0.3294, 0.6408, 1.263, 2.5074"); index_2 ("0.001, 0.0234, 0.039, 0.0648, 0.108, 0.18, 0.3"); values ( \ - "0.0127511, 0.0872332, 0.140455, 0.228545, 0.376185, 0.621776, 1.03142", \ - "0.0280188, 0.100018, 0.148036, 0.231423, 0.376553, 0.622512, 1.03143", \ - "0.0400896, 0.119398, 0.166359, 0.245174, 0.383446, 0.623628, 1.03177", \ - "0.0595377, 0.157068, 0.206831, 0.285033, 0.415036, 0.641717, 1.03741", \ + "0.0127511, 0.0872829, 0.140455, 0.228547, 0.376185, 0.621776, 1.03157", \ + "0.0280188, 0.100019, 0.148036, 0.231424, 0.376554, 0.621871, 1.03158", \ + "0.0400896, 0.119398, 0.166302, 0.245203, 0.383487, 0.623609, 1.03202", \ + "0.0595377, 0.157068, 0.206831, 0.285033, 0.415036, 0.641605, 1.0375", \ "0.0910953, 0.216451, 0.276449, 0.36152, 0.496327, 0.710054, 1.08065", \ "0.144104, 0.311834, 0.389639, 0.493368, 0.643341, 0.871975, 1.23", \ - "0.235224, 0.462623, 0.565646, 0.70463, 0.891884, 1.16085, 1.54433" \ + "0.235224, 0.462753, 0.565641, 0.704619, 0.891884, 1.16085, 1.54419" \ ); } } @@ -2094,52 +2094,52 @@ library (sg13g2_stdcell_slow_1p35V_125C) { index_1 ("0.0186, 0.0966, 0.174, 0.3294, 0.6408, 1.263, 2.5074"); index_2 ("0.001, 0.0234, 0.039, 0.0648, 0.108, 0.18, 0.3"); values ( \ - "0.0446056, 0.183381, 0.277309, 0.43262, 0.692182, 1.12454, 1.84514", \ - "0.0692652, 0.214483, 0.308733, 0.464031, 0.724398, 1.15689, 1.87854", \ - "0.0854907, 0.247179, 0.342232, 0.497472, 0.757193, 1.19051, 1.91078", \ - "0.108113, 0.302983, 0.405818, 0.564281, 0.823336, 1.2558, 1.97625", \ - "0.144083, 0.388409, 0.510955, 0.687658, 0.95777, 1.39034, 2.10923", \ - "0.192728, 0.504638, 0.6583, 0.876211, 1.18751, 1.65035, 2.37617", \ - "0.264101, 0.668574, 0.865355, 1.13822, 1.5307, 2.07897, 2.87969" \ + "0.0446147, 0.183386, 0.277309, 0.432799, 0.692142, 1.12454, 1.84518", \ + "0.0691555, 0.214481, 0.308624, 0.464197, 0.724394, 1.15673, 1.87853", \ + "0.0854908, 0.247179, 0.342229, 0.497473, 0.757185, 1.19051, 1.91053", \ + "0.108113, 0.302983, 0.405818, 0.564281, 0.823323, 1.25579, 1.97625", \ + "0.144083, 0.388409, 0.510954, 0.687658, 0.95777, 1.39039, 2.10923", \ + "0.192728, 0.504638, 0.6583, 0.876211, 1.18739, 1.65037, 2.37617", \ + "0.264101, 0.668574, 0.865355, 1.13822, 1.5307, 2.07897, 2.87968" \ ); } rise_transition (TIMING_DELAY_7x7ds1) { index_1 ("0.0186, 0.0966, 0.174, 0.3294, 0.6408, 1.263, 2.5074"); index_2 ("0.001, 0.0234, 0.039, 0.0648, 0.108, 0.18, 0.3"); values ( \ - "0.0389562, 0.231114, 0.3644, 0.584725, 0.953686, 1.56847, 2.59304", \ - "0.0525552, 0.232237, 0.36612, 0.584726, 0.954149, 1.56899, 2.59336", \ - "0.0659114, 0.24261, 0.369039, 0.585514, 0.954294, 1.56902, 2.59337", \ - "0.0877069, 0.274373, 0.393614, 0.598578, 0.956843, 1.56903, 2.59338", \ - "0.12166, 0.337525, 0.458879, 0.654501, 0.99092, 1.58033, 2.59462", \ - "0.179302, 0.441878, 0.581042, 0.786073, 1.1146, 1.66549, 2.63077", \ - "0.276619, 0.608004, 0.772358, 1.01611, 1.37538, 1.92892, 2.83414" \ + "0.038986, 0.231114, 0.364399, 0.584646, 0.953598, 1.56847, 2.59312", \ + "0.0526167, 0.232233, 0.3644, 0.584681, 0.95415, 1.56899, 2.59335", \ + "0.0659114, 0.24261, 0.369047, 0.585416, 0.954273, 1.56902, 2.59362", \ + "0.0877069, 0.274373, 0.393614, 0.598577, 0.95686, 1.56903, 2.59363", \ + "0.12166, 0.337523, 0.45888, 0.6545, 0.99092, 1.58037, 2.59364", \ + "0.179303, 0.441877, 0.581042, 0.786076, 1.11484, 1.66551, 2.63076", \ + "0.276619, 0.608004, 0.772357, 1.01611, 1.37538, 1.92892, 2.83424" \ ); } cell_fall (TIMING_DELAY_7x7ds1) { index_1 ("0.0186, 0.0966, 0.174, 0.3294, 0.6408, 1.263, 2.5074"); index_2 ("0.001, 0.0234, 0.039, 0.0648, 0.108, 0.18, 0.3"); values ( \ - "0.0225572, 0.082311, 0.122416, 0.188573, 0.29938, 0.483475, 0.790229", \ - "0.0400611, 0.122997, 0.165595, 0.232432, 0.34309, 0.527383, 0.834068", \ - "0.0491533, 0.153238, 0.202129, 0.27395, 0.386704, 0.570693, 0.877554", \ - "0.0606939, 0.197305, 0.258811, 0.343913, 0.468302, 0.658443, 0.965621", \ - "0.0726168, 0.256549, 0.337975, 0.446724, 0.597694, 0.814713, 1.13595", \ - "0.0832671, 0.330227, 0.44127, 0.588351, 0.784621, 1.05279, 1.43127", \ - "0.0889202, 0.422031, 0.568375, 0.76834, 1.03712, 1.39037, 1.87096" \ + "0.0225571, 0.0823262, 0.12237, 0.188576, 0.299381, 0.483521, 0.790227", \ + "0.0400611, 0.123013, 0.165595, 0.232431, 0.343111, 0.527319, 0.83407", \ + "0.0491533, 0.153211, 0.202151, 0.27395, 0.386701, 0.570709, 0.87753", \ + "0.0606939, 0.197305, 0.258811, 0.343913, 0.468302, 0.658442, 0.965656", \ + "0.0726168, 0.256549, 0.337975, 0.446724, 0.597694, 0.814713, 1.13586", \ + "0.083265, 0.330227, 0.44127, 0.588351, 0.784622, 1.05279, 1.43127", \ + "0.0889202, 0.421998, 0.568379, 0.768341, 1.03712, 1.39037, 1.87112" \ ); } fall_transition (TIMING_DELAY_7x7ds1) { index_1 ("0.0186, 0.0966, 0.174, 0.3294, 0.6408, 1.263, 2.5074"); index_2 ("0.001, 0.0234, 0.039, 0.0648, 0.108, 0.18, 0.3"); values ( \ - "0.0167873, 0.0929403, 0.1461, 0.234115, 0.381881, 0.627141, 1.03677", \ - "0.0373074, 0.105549, 0.153552, 0.237123, 0.38279, 0.627142, 1.03746", \ - "0.0525246, 0.125416, 0.171898, 0.250708, 0.389255, 0.628938, 1.03747", \ - "0.0775905, 0.164406, 0.213145, 0.290782, 0.420471, 0.647278, 1.04257", \ - "0.1181, 0.225835, 0.28408, 0.36806, 0.501349, 0.71502, 1.08507", \ - "0.184865, 0.327085, 0.399912, 0.502741, 0.649976, 0.878385, 1.23483", \ - "0.294307, 0.488266, 0.585649, 0.719031, 0.903129, 1.16822, 1.55289" \ + "0.016816, 0.0929191, 0.14609, 0.234114, 0.381882, 0.627565, 1.03678", \ + "0.0373074, 0.105556, 0.153552, 0.237137, 0.382801, 0.627566, 1.03745", \ + "0.0525246, 0.125432, 0.171889, 0.250811, 0.389254, 0.628958, 1.03746", \ + "0.0775905, 0.164406, 0.213145, 0.290782, 0.420471, 0.647271, 1.0426", \ + "0.1181, 0.225835, 0.28408, 0.36806, 0.501348, 0.71502, 1.08548", \ + "0.18486, 0.327084, 0.399913, 0.502741, 0.649976, 0.878385, 1.23483", \ + "0.294307, 0.488008, 0.585644, 0.720075, 0.903129, 1.16822, 1.55089" \ ); } } @@ -2149,26 +2149,26 @@ library (sg13g2_stdcell_slow_1p35V_125C) { index_1 ("0.0186, 0.0966, 0.174, 0.3294, 0.6408, 1.263, 2.5074"); index_2 ("0.001, 0.0234, 0.039, 0.0648, 0.108, 0.18, 0.3"); values ( \ - "0.00550365, 0.00583899, 0.00581105, 0.00574974, 0.00559015, 0.00533191, 0.00498909", \ - "0.00517606, 0.00559743, 0.00573145, 0.00563936, 0.00555949, 0.00532202, 0.00502336", \ - "0.00520841, 0.00551769, 0.00551474, 0.00557651, 0.00560945, 0.00535342, 0.00494305", \ - "0.0056263, 0.00546128, 0.00554951, 0.00553699, 0.00564292, 0.00519841, 0.00497754", \ - "0.00725002, 0.00616841, 0.00595285, 0.00584124, 0.00557855, 0.00575788, 0.0051543", \ - "0.0115628, 0.00871166, 0.00801353, 0.00744951, 0.00669481, 0.0066198, 0.00620012", \ - "0.0209123, 0.0157524, 0.0141641, 0.0124802, 0.0109705, 0.00916, 0.00817969" \ + "0.00549392, 0.005844, 0.00581459, 0.00575701, 0.00559586, 0.00533173, 0.00498885", \ + "0.00517579, 0.00559741, 0.00566078, 0.00564016, 0.00555949, 0.00532352, 0.00510556", \ + "0.00520843, 0.00551186, 0.00551474, 0.00552403, 0.0056094, 0.00535347, 0.00501652", \ + "0.00562622, 0.00546125, 0.00554919, 0.00553705, 0.00564395, 0.00529287, 0.0049936", \ + "0.007249, 0.00617074, 0.00595287, 0.0058413, 0.00557855, 0.00547355, 0.00514345", \ + "0.0115623, 0.00871175, 0.00801355, 0.00744645, 0.00669481, 0.00661952, 0.00615321", \ + "0.0209137, 0.0157523, 0.0141637, 0.0124801, 0.0109592, 0.00919846, 0.00816206" \ ); } fall_power (POWER_7x7ds1) { index_1 ("0.0186, 0.0966, 0.174, 0.3294, 0.6408, 1.263, 2.5074"); index_2 ("0.001, 0.0234, 0.039, 0.0648, 0.108, 0.18, 0.3"); values ( \ - "0.0041926, 0.00423362, 0.0042142, 0.00413473, 0.00402252, 0.0037498, 0.00335068", \ - "0.00394683, 0.00414147, 0.00405473, 0.00399832, 0.00390262, 0.0037042, 0.00334415", \ - "0.0041468, 0.00407838, 0.0041116, 0.00399961, 0.00392297, 0.00383578, 0.00324972", \ - "0.00491347, 0.00449482, 0.00428475, 0.00419702, 0.00405777, 0.00401524, 0.0032206", \ - "0.00684826, 0.00546457, 0.00513194, 0.00478617, 0.00433534, 0.00452276, 0.00363041", \ - "0.0111212, 0.00843491, 0.00756844, 0.00681237, 0.00607951, 0.00510034, 0.00484569", \ - "0.0202415, 0.0159255, 0.0141636, 0.0124151, 0.0106046, 0.00890494, 0.00702311" \ + "0.00419332, 0.00423493, 0.00420144, 0.00413571, 0.00400646, 0.00380495, 0.00334968", \ + "0.00394611, 0.00414516, 0.00406315, 0.00399816, 0.00391127, 0.00369622, 0.00334479", \ + "0.0041469, 0.00407383, 0.0041116, 0.00398674, 0.00392445, 0.00365327, 0.0032524", \ + "0.00491402, 0.00449114, 0.00428475, 0.00419702, 0.00403661, 0.00436447, 0.003205", \ + "0.00684933, 0.00546549, 0.00513193, 0.00479624, 0.00433541, 0.00452276, 0.00363041", \ + "0.0111204, 0.00843408, 0.00753862, 0.00681237, 0.00606863, 0.00510149, 0.00484522", \ + "0.0202415, 0.0159254, 0.0141636, 0.0124143, 0.0106045, 0.00890544, 0.00700991" \ ); } } @@ -2178,26 +2178,26 @@ library (sg13g2_stdcell_slow_1p35V_125C) { index_1 ("0.0186, 0.0966, 0.174, 0.3294, 0.6408, 1.263, 2.5074"); index_2 ("0.001, 0.0234, 0.039, 0.0648, 0.108, 0.18, 0.3"); values ( \ - "0.00585883, 0.00592357, 0.00584865, 0.00579211, 0.00563182, 0.00533178, 0.00505511", \ - "0.00564293, 0.00581994, 0.00591198, 0.00570652, 0.00559494, 0.00530955, 0.00510817", \ - "0.00565608, 0.00578479, 0.00570294, 0.00568638, 0.00557887, 0.00541038, 0.00500741", \ - "0.00600501, 0.00579476, 0.005801, 0.00571667, 0.00562178, 0.00532049, 0.00497218", \ - "0.00746169, 0.00654305, 0.00631472, 0.00612816, 0.00579274, 0.00566438, 0.00546455", \ - "0.0115331, 0.00911815, 0.00846243, 0.00784835, 0.00703793, 0.00655194, 0.00645963", \ - "0.0204209, 0.0162672, 0.0147682, 0.0130374, 0.0113846, 0.00958113, 0.00844341" \ + "0.0058581, 0.00592398, 0.00584846, 0.00578632, 0.00562813, 0.00533211, 0.00505947", \ + "0.00564164, 0.00577522, 0.00581757, 0.00569724, 0.00558872, 0.00530972, 0.00510408", \ + "0.00565697, 0.00578469, 0.00570295, 0.00568638, 0.00559424, 0.00540932, 0.00555301", \ + "0.00600511, 0.00579476, 0.00580173, 0.00571722, 0.00562178, 0.00533109, 0.00499632", \ + "0.00746235, 0.00654403, 0.00631623, 0.00612733, 0.00579294, 0.0059396, 0.00563753", \ + "0.0115332, 0.00911815, 0.00846243, 0.00784753, 0.00703635, 0.00652817, 0.0068433", \ + "0.0204207, 0.0162673, 0.0147684, 0.0130375, 0.0113838, 0.00958127, 0.00841966" \ ); } fall_power (POWER_7x7ds1) { index_1 ("0.0186, 0.0966, 0.174, 0.3294, 0.6408, 1.263, 2.5074"); index_2 ("0.001, 0.0234, 0.039, 0.0648, 0.108, 0.18, 0.3"); values ( \ - "0.00618114, 0.00616218, 0.00610543, 0.00606036, 0.00589243, 0.00570974, 0.00533554", \ - "0.00587387, 0.00607086, 0.00598781, 0.00600447, 0.00578526, 0.00562097, 0.00526589", \ - "0.00590929, 0.00598444, 0.00601823, 0.00590686, 0.00580894, 0.00564136, 0.00517047", \ - "0.00635052, 0.00616682, 0.00608053, 0.00599534, 0.00604254, 0.00631938, 0.00515747", \ - "0.0078732, 0.00689304, 0.00676852, 0.00650903, 0.00612821, 0.00633451, 0.00586608", \ - "0.0117952, 0.0093918, 0.00872165, 0.00819312, 0.00759621, 0.00665473, 0.00654586", \ - "0.0202912, 0.0161882, 0.0146139, 0.0130717, 0.0115063, 0.0101023, 0.00858118" \ + "0.00617791, 0.00616265, 0.00611152, 0.00604368, 0.00589223, 0.00572671, 0.0053348", \ + "0.00587144, 0.00607086, 0.0059928, 0.00593017, 0.00581794, 0.00566066, 0.00526625", \ + "0.00590656, 0.0059844, 0.00600893, 0.00588727, 0.00616445, 0.00560335, 0.00516988", \ + "0.00635474, 0.00616684, 0.0060805, 0.00601819, 0.00587204, 0.00631938, 0.00515337", \ + "0.00787159, 0.006894, 0.00676614, 0.00650842, 0.00612821, 0.00633437, 0.00586608", \ + "0.0117966, 0.00939172, 0.00872166, 0.00819312, 0.00759621, 0.00674048, 0.00653595", \ + "0.0202913, 0.0161884, 0.0146139, 0.0130718, 0.0115063, 0.0101185, 0.00858112" \ ); } } @@ -2208,26 +2208,26 @@ library (sg13g2_stdcell_slow_1p35V_125C) { index_1 ("0.0186, 0.0966, 0.174, 0.3294, 0.6408, 1.263, 2.5074"); index_2 ("0.001, 0.0234, 0.039, 0.0648, 0.108, 0.18, 0.3"); values ( \ - "0.00322944, 0.00360613, 0.00359112, 0.00352623, 0.0033917, 0.00312013, 0.00279831", \ - "0.00316043, 0.00334579, 0.00345031, 0.00335136, 0.00330793, 0.00311307, 0.00280246", \ - "0.0035149, 0.0034036, 0.00330377, 0.00329217, 0.00329697, 0.00307773, 0.00270481", \ - "0.00437132, 0.00365595, 0.00358632, 0.00343666, 0.0033695, 0.00302704, 0.00275469", \ - "0.00646647, 0.0049712, 0.00454131, 0.00418682, 0.00367543, 0.00357402, 0.00291529", \ - "0.0111765, 0.00828723, 0.00745565, 0.00651674, 0.00547486, 0.005155, 0.0042142", \ - "0.0210261, 0.0159917, 0.0145029, 0.0127974, 0.0109876, 0.00853809, 0.0072705" \ + "0.00323562, 0.0036112, 0.00359157, 0.00353485, 0.00338327, 0.00311983, 0.00324358", \ + "0.00315797, 0.00333515, 0.00334778, 0.00335163, 0.00329332, 0.00310095, 0.00280399", \ + "0.0035149, 0.0034036, 0.00330652, 0.00330303, 0.00329636, 0.00307778, 0.00323511", \ + "0.00437036, 0.00365599, 0.00358623, 0.00343693, 0.00327755, 0.00302665, 0.00275483", \ + "0.00646904, 0.00496701, 0.00454215, 0.00418682, 0.00367556, 0.00357705, 0.00288711", \ + "0.0111782, 0.00828593, 0.00745626, 0.00651673, 0.00547624, 0.00508815, 0.00421366", \ + "0.0210261, 0.0159917, 0.0145029, 0.0127972, 0.010988, 0.00853809, 0.00722825" \ ); } fall_power (POWER_7x7ds1) { index_1 ("0.0186, 0.0966, 0.174, 0.3294, 0.6408, 1.263, 2.5074"); index_2 ("0.001, 0.0234, 0.039, 0.0648, 0.108, 0.18, 0.3"); values ( \ - "0.00436995, 0.00486599, 0.00481036, 0.00473969, 0.0046773, 0.00440061, 0.004018", \ - "0.00426644, 0.00467871, 0.00478489, 0.00476832, 0.00476198, 0.00443584, 0.00411754", \ - "0.00458077, 0.0047195, 0.00472304, 0.0047379, 0.00475634, 0.00472059, 0.00403841", \ - "0.00555317, 0.00508052, 0.00502526, 0.00486534, 0.00470162, 0.0046965, 0.00412859", \ - "0.00767023, 0.00603668, 0.00572741, 0.00549244, 0.00526661, 0.00467816, 0.00496508", \ - "0.0124969, 0.0092999, 0.00827844, 0.00743512, 0.00684069, 0.00629177, 0.004936", \ - "0.0221647, 0.0169338, 0.0151587, 0.0132216, 0.0114088, 0.00982953, 0.00855808" \ + "0.00437177, 0.00482513, 0.00480505, 0.00475087, 0.00467712, 0.00444537, 0.0040177", \ + "0.00426644, 0.00468081, 0.00478489, 0.00478075, 0.00476398, 0.00445677, 0.00412174", \ + "0.00458088, 0.00471121, 0.00469388, 0.00472526, 0.00475727, 0.00468579, 0.00407884", \ + "0.00555302, 0.00508025, 0.00502526, 0.00488619, 0.00470156, 0.00495202, 0.00419273", \ + "0.00767072, 0.00603603, 0.00572741, 0.00549244, 0.00526798, 0.0046781, 0.00477136", \ + "0.0124957, 0.00929989, 0.00827861, 0.00743512, 0.00684552, 0.0062919, 0.00493695", \ + "0.0221624, 0.0169378, 0.0151608, 0.0132207, 0.0114088, 0.00982964, 0.00846046" \ ); } } @@ -2238,26 +2238,26 @@ library (sg13g2_stdcell_slow_1p35V_125C) { index_1 ("0.0186, 0.0966, 0.174, 0.3294, 0.6408, 1.263, 2.5074"); index_2 ("0.001, 0.0234, 0.039, 0.0648, 0.108, 0.18, 0.3"); values ( \ - "0.00274325, 0.00323887, 0.0032356, 0.00317673, 0.00302343, 0.0027657, 0.00243481", \ - "0.00280564, 0.00295076, 0.00301414, 0.00302904, 0.00297367, 0.00271793, 0.00245895", \ - "0.00322997, 0.00302001, 0.00295172, 0.00297916, 0.00290242, 0.00275943, 0.00244096", \ - "0.00418479, 0.00332737, 0.00326762, 0.00306404, 0.00300901, 0.00268845, 0.00237278", \ - "0.00645171, 0.00470319, 0.00423366, 0.0038387, 0.0033579, 0.00362315, 0.00252552", \ - "0.0113591, 0.00809036, 0.00722677, 0.00624061, 0.00517051, 0.00471255, 0.00396736", \ - "0.021437, 0.0158617, 0.0143242, 0.0125807, 0.0106177, 0.00821828, 0.00694946" \ + "0.00274203, 0.00324413, 0.00323603, 0.00317785, 0.00303127, 0.00275635, 0.00245718", \ + "0.00280408, 0.00294918, 0.00301414, 0.00299938, 0.00297363, 0.00272282, 0.00245885", \ + "0.00322997, 0.00302095, 0.00295749, 0.00293656, 0.00289357, 0.00274207, 0.0024259", \ + "0.0041848, 0.00332738, 0.00326759, 0.00306391, 0.00300902, 0.00268909, 0.00237203", \ + "0.00645174, 0.00470569, 0.00423363, 0.00383869, 0.00335783, 0.00360681, 0.00265141", \ + "0.011358, 0.00808359, 0.00722693, 0.00624414, 0.00517071, 0.00471255, 0.00372732", \ + "0.0214368, 0.0158622, 0.0143242, 0.0125806, 0.0106183, 0.00821828, 0.00700301" \ ); } fall_power (POWER_7x7ds1) { index_1 ("0.0186, 0.0966, 0.174, 0.3294, 0.6408, 1.263, 2.5074"); index_2 ("0.001, 0.0234, 0.039, 0.0648, 0.108, 0.18, 0.3"); values ( \ - "0.00236035, 0.00283813, 0.0028018, 0.00276835, 0.00267062, 0.00242858, 0.0020335", \ - "0.00225087, 0.00267828, 0.00276565, 0.00270908, 0.00266452, 0.00261171, 0.00214794", \ - "0.00257572, 0.00270715, 0.00271584, 0.0027393, 0.00279618, 0.0028542, 0.00212454", \ - "0.00358429, 0.00309059, 0.00303714, 0.00290639, 0.00273597, 0.00307879, 0.00299507", \ - "0.00574373, 0.00407652, 0.00373518, 0.00352298, 0.00327676, 0.00270311, 0.00292363", \ - "0.0106443, 0.00731577, 0.0062741, 0.00536801, 0.00484249, 0.00418765, 0.00300101", \ - "0.0203919, 0.0149833, 0.0132028, 0.0112945, 0.00952957, 0.00785159, 0.00643899" \ + "0.00236034, 0.00283818, 0.00280142, 0.00276738, 0.00266892, 0.00242894, 0.00203455", \ + "0.00225076, 0.00267762, 0.00276564, 0.00269503, 0.00266396, 0.00261118, 0.00209027", \ + "0.00257592, 0.00270715, 0.00271265, 0.00272357, 0.0028066, 0.00284601, 0.00212637", \ + "0.00358436, 0.00309059, 0.00303715, 0.0029062, 0.00270167, 0.00308169, 0.00299183", \ + "0.00574396, 0.00407641, 0.00373519, 0.00352298, 0.0032773, 0.00272821, 0.00291911", \ + "0.0106443, 0.00731597, 0.00624368, 0.00536785, 0.00485167, 0.00418725, 0.00300094", \ + "0.0203924, 0.014978, 0.0132026, 0.0113186, 0.00952936, 0.00785197, 0.00646312" \ ); } } @@ -2268,26 +2268,26 @@ library (sg13g2_stdcell_slow_1p35V_125C) { index_1 ("0.0186, 0.0966, 0.174, 0.3294, 0.6408, 1.263, 2.5074"); index_2 ("0.001, 0.0234, 0.039, 0.0648, 0.108, 0.18, 0.3"); values ( \ - "0.00274946, 0.0032433, 0.00323589, 0.0031819, 0.0030454, 0.00279636, 0.00287165", \ - "0.00284786, 0.0029984, 0.00301108, 0.00298173, 0.00293473, 0.00270741, 0.00277169", \ - "0.00331107, 0.00301808, 0.00307628, 0.00294315, 0.00286749, 0.00271107, 0.00273303", \ - "0.00434528, 0.00343081, 0.00325276, 0.00319902, 0.00297781, 0.0027282, 0.00278439", \ - "0.006784, 0.00488076, 0.00442041, 0.00387139, 0.00359003, 0.0029708, 0.00302672", \ - "0.0120149, 0.00851309, 0.0075573, 0.00660781, 0.00549375, 0.00464574, 0.00369569", \ - "0.0227417, 0.0169886, 0.0152738, 0.0132406, 0.0112082, 0.00914574, 0.00682556" \ + "0.00274831, 0.00324361, 0.00323654, 0.00318275, 0.00305991, 0.00279393, 0.0028719", \ + "0.0028487, 0.00299704, 0.00300687, 0.00298176, 0.00297739, 0.00270742, 0.00277421", \ + "0.00330989, 0.00301816, 0.0030763, 0.00294447, 0.00288151, 0.00271408, 0.00273987", \ + "0.0043455, 0.00342191, 0.00325262, 0.00319864, 0.00297781, 0.00275525, 0.0027899", \ + "0.0067831, 0.00488133, 0.00442276, 0.00387387, 0.00358866, 0.00297074, 0.00342629", \ + "0.0120143, 0.00851337, 0.00755722, 0.00660781, 0.00549395, 0.00464982, 0.00369203", \ + "0.0227416, 0.0169888, 0.0152738, 0.0132401, 0.0112082, 0.00908357, 0.00683154" \ ); } fall_power (POWER_7x7ds1) { index_1 ("0.0186, 0.0966, 0.174, 0.3294, 0.6408, 1.263, 2.5074"); index_2 ("0.001, 0.0234, 0.039, 0.0648, 0.108, 0.18, 0.3"); values ( \ - "0.00226398, 0.0027603, 0.00272784, 0.00265352, 0.00258954, 0.00235194, 0.00195783", \ - "0.00217723, 0.00253844, 0.00264279, 0.00257391, 0.00254115, 0.00241829, 0.00197447", \ - "0.00255612, 0.00258916, 0.00256191, 0.00258798, 0.00266818, 0.00250573, 0.00197481", \ - "0.00362709, 0.00301158, 0.00294898, 0.00280983, 0.00262645, 0.00293832, 0.00275542", \ - "0.00597605, 0.00412222, 0.00372405, 0.00347465, 0.00325379, 0.00269198, 0.00289388", \ - "0.0110474, 0.00749765, 0.00675703, 0.00551698, 0.0049573, 0.00432521, 0.00291566", \ - "0.0216123, 0.0158754, 0.0139724, 0.0118103, 0.00988595, 0.00840633, 0.00664263" \ + "0.00226406, 0.00276252, 0.00272446, 0.00265344, 0.00259032, 0.00235288, 0.00190809", \ + "0.00217703, 0.00253843, 0.00264279, 0.00257506, 0.00254123, 0.00235516, 0.001977", \ + "0.00255584, 0.00258914, 0.00258935, 0.00259852, 0.0026803, 0.00270136, 0.00206271", \ + "0.00362663, 0.00301067, 0.00294898, 0.00280973, 0.00262645, 0.00251708, 0.00206057", \ + "0.00597606, 0.00412228, 0.00372406, 0.00347466, 0.00325366, 0.00269198, 0.00289381", \ + "0.0110471, 0.0074982, 0.00675696, 0.00551724, 0.00495723, 0.00432515, 0.00291553", \ + "0.021612, 0.0158905, 0.0139693, 0.011811, 0.0098859, 0.00840652, 0.00671109" \ ); } } @@ -2297,26 +2297,26 @@ library (sg13g2_stdcell_slow_1p35V_125C) { index_1 ("0.0186, 0.0966, 0.174, 0.3294, 0.6408, 1.263, 2.5074"); index_2 ("0.001, 0.0234, 0.039, 0.0648, 0.108, 0.18, 0.3"); values ( \ - "0.00274946, 0.0032433, 0.00323589, 0.0031819, 0.0030454, 0.00279636, 0.00287165", \ - "0.00284786, 0.0029984, 0.00301108, 0.00298173, 0.00293473, 0.00270741, 0.00277169", \ - "0.00331107, 0.00301808, 0.00307628, 0.00294315, 0.00286749, 0.00271107, 0.00273303", \ - "0.00434528, 0.00343081, 0.00325276, 0.00319902, 0.00297781, 0.0027282, 0.00278439", \ - "0.006784, 0.00488076, 0.00442041, 0.00387139, 0.00359003, 0.0029708, 0.00302672", \ - "0.0120149, 0.00851309, 0.0075573, 0.00660781, 0.00549375, 0.00464574, 0.00369569", \ - "0.0227417, 0.0169886, 0.0152738, 0.0132406, 0.0112082, 0.00914574, 0.00682556" \ + "0.00274831, 0.00324361, 0.00323654, 0.00318275, 0.00305991, 0.00279393, 0.0028719", \ + "0.0028487, 0.00299704, 0.00300687, 0.00298176, 0.00297739, 0.00270742, 0.00277421", \ + "0.00330989, 0.00301816, 0.0030763, 0.00294447, 0.00288151, 0.00271408, 0.00273987", \ + "0.0043455, 0.00342191, 0.00325262, 0.00319864, 0.00297781, 0.00275525, 0.0027899", \ + "0.0067831, 0.00488133, 0.00442276, 0.00387387, 0.00358866, 0.00297074, 0.00342629", \ + "0.0120143, 0.00851337, 0.00755722, 0.00660781, 0.00549395, 0.00464982, 0.00369203", \ + "0.0227416, 0.0169888, 0.0152738, 0.0132401, 0.0112082, 0.00908357, 0.00683154" \ ); } fall_power (POWER_7x7ds1) { index_1 ("0.0186, 0.0966, 0.174, 0.3294, 0.6408, 1.263, 2.5074"); index_2 ("0.001, 0.0234, 0.039, 0.0648, 0.108, 0.18, 0.3"); values ( \ - "0.00226398, 0.0027603, 0.00272784, 0.00265352, 0.00258954, 0.00235194, 0.00195783", \ - "0.00217723, 0.00253844, 0.00264279, 0.00257391, 0.00254115, 0.00241829, 0.00197447", \ - "0.00255612, 0.00258916, 0.00256191, 0.00258798, 0.00266818, 0.00250573, 0.00197481", \ - "0.00362709, 0.00301158, 0.00294898, 0.00280983, 0.00262645, 0.00293832, 0.00275542", \ - "0.00597605, 0.00412222, 0.00372405, 0.00347465, 0.00325379, 0.00269198, 0.00289388", \ - "0.0110474, 0.00749765, 0.00675703, 0.00551698, 0.0049573, 0.00432521, 0.00291566", \ - "0.0216123, 0.0158754, 0.0139724, 0.0118103, 0.00988595, 0.00840633, 0.00664263" \ + "0.00226406, 0.00276252, 0.00272446, 0.00265344, 0.00259032, 0.00235288, 0.00190809", \ + "0.00217703, 0.00253843, 0.00264279, 0.00257506, 0.00254123, 0.00235516, 0.001977", \ + "0.00255584, 0.00258914, 0.00258935, 0.00259852, 0.0026803, 0.00270136, 0.00206271", \ + "0.00362663, 0.00301067, 0.00294898, 0.00280973, 0.00262645, 0.00251708, 0.00206057", \ + "0.00597606, 0.00412228, 0.00372406, 0.00347466, 0.00325366, 0.00269198, 0.00289381", \ + "0.0110471, 0.0074982, 0.00675696, 0.00551724, 0.00495723, 0.00432515, 0.00291553", \ + "0.021612, 0.0158905, 0.0139693, 0.011811, 0.0098859, 0.00840652, 0.00671109" \ ); } } @@ -2324,37 +2324,37 @@ library (sg13g2_stdcell_slow_1p35V_125C) { pin (A1) { direction : "input"; max_transition : 2.5074; - capacitance : 0.00295986; - rise_capacitance : 0.00290691; - rise_capacitance_range (0.00290691, 0.00290691); + capacitance : 0.00295988; + rise_capacitance : 0.00290694; + rise_capacitance_range (0.00267696, 0.00320996); fall_capacitance : 0.00301282; - fall_capacitance_range (0.00301282, 0.00301282); + fall_capacitance_range (0.00258189, 0.00339441); } pin (A2) { direction : "input"; max_transition : 2.5074; - capacitance : 0.00301979; - rise_capacitance : 0.00306716; - rise_capacitance_range (0.00306716, 0.00306716); - fall_capacitance : 0.00297242; - fall_capacitance_range (0.00297242, 0.00297242); + capacitance : 0.0030198; + rise_capacitance : 0.00306717; + rise_capacitance_range (0.00264434, 0.00340405); + fall_capacitance : 0.00297244; + fall_capacitance_range (0.00263173, 0.00327915); } pin (B1) { direction : "input"; max_transition : 2.5074; - capacitance : 0.00281643; + capacitance : 0.00281644; rise_capacitance : 0.00289618; - rise_capacitance_range (0.00289618, 0.00289618); - fall_capacitance : 0.00273669; - fall_capacitance_range (0.00273669, 0.00273669); + rise_capacitance_range (0.00237277, 0.00358393); + fall_capacitance : 0.0027367; + fall_capacitance_range (0.00249165, 0.00305431); } } cell (sg13g2_a21oi_2) { area : 14.5152; cell_footprint : "a21oi"; - cell_leakage_power : 1407.6; + cell_leakage_power : 1407.59; leakage_power () { - value : 570.109; + value : 570.107; when : "!A1&!A2&!B1&Y"; } leakage_power () { @@ -2362,7 +2362,7 @@ library (sg13g2_stdcell_slow_1p35V_125C) { when : "!A1&!A2&B1&!Y"; } leakage_power () { - value : 872.933; + value : 872.932; when : "!A1&A2&!B1&Y"; } leakage_power () { @@ -2370,7 +2370,7 @@ library (sg13g2_stdcell_slow_1p35V_125C) { when : "!A1&A2&B1&!Y"; } leakage_power () { - value : 793.419; + value : 793.418; when : "A1&!A2&!B1&Y"; } leakage_power () { @@ -2382,7 +2382,7 @@ library (sg13g2_stdcell_slow_1p35V_125C) { when : "A1&A2&!B1&!Y"; } leakage_power () { - value : 1029.43; + value : 1029.42; when : "A1&A2&B1&!Y"; } pin (Y) { @@ -2398,52 +2398,52 @@ library (sg13g2_stdcell_slow_1p35V_125C) { index_1 ("0.0186, 0.0966, 0.174, 0.3294, 0.6408, 1.263, 2.5074"); index_2 ("0.001, 0.0468, 0.078, 0.1296, 0.216, 0.36, 0.6"); values ( \ - "0.0424638, 0.183713, 0.277744, 0.433142, 0.693025, 1.12659, 1.84878", \ - "0.062372, 0.210944, 0.305497, 0.461262, 0.721995, 1.15472, 1.87782", \ - "0.0719557, 0.235089, 0.330526, 0.486422, 0.746923, 1.18159, 1.90249", \ - "0.0827491, 0.275713, 0.376871, 0.53592, 0.796664, 1.2307, 1.95319", \ - "0.0978537, 0.339863, 0.455587, 0.62759, 0.896695, 1.3321, 2.05424", \ - "0.115506, 0.429476, 0.568448, 0.769635, 1.06695, 1.52406, 2.25268", \ - "0.135363, 0.549922, 0.731251, 0.977037, 1.33091, 1.84661, 2.62723" \ + "0.0424548, 0.183707, 0.27773, 0.433139, 0.692957, 1.12657, 1.84875", \ + "0.0623531, 0.210935, 0.305413, 0.461255, 0.722, 1.15471, 1.87779", \ + "0.0719544, 0.235061, 0.330522, 0.486474, 0.747171, 1.18157, 1.90245", \ + "0.0827483, 0.27571, 0.376867, 0.535918, 0.796597, 1.23068, 1.95314", \ + "0.0979134, 0.33986, 0.455583, 0.627583, 0.896685, 1.33208, 2.0543", \ + "0.115504, 0.429472, 0.568443, 0.769627, 1.06694, 1.52407, 2.25255", \ + "0.135361, 0.550865, 0.730713, 0.977028, 1.3309, 1.84659, 2.6272" \ ); } rise_transition (TIMING_DELAY_7x7ds1) { index_1 ("0.0186, 0.0966, 0.174, 0.3294, 0.6408, 1.263, 2.5074"); index_2 ("0.001, 0.0468, 0.078, 0.1296, 0.216, 0.36, 0.6"); values ( \ - "0.024385, 0.220444, 0.353971, 0.574919, 0.945181, 1.56133, 2.58865", \ - "0.0334865, 0.221346, 0.354506, 0.574928, 0.945182, 1.56184, 2.58938", \ - "0.0440902, 0.227818, 0.35705, 0.575704, 0.94688, 1.56261, 2.5895", \ - "0.0641484, 0.248814, 0.372939, 0.583717, 0.946881, 1.56262, 2.58951", \ - "0.102994, 0.295928, 0.417299, 0.621094, 0.968789, 1.56899, 2.58952", \ - "0.165148, 0.383556, 0.510618, 0.712873, 1.05198, 1.62435, 2.61399", \ - "0.261888, 0.537038, 0.676014, 0.890933, 1.23907, 1.80263, 2.74901" \ + "0.0243879, 0.220481, 0.353968, 0.57491, 0.944759, 1.5613, 2.58861", \ + "0.0335033, 0.221348, 0.35577, 0.574923, 0.945152, 1.56182, 2.58934", \ + "0.044083, 0.227819, 0.35704, 0.57552, 0.945153, 1.56259, 2.58935", \ + "0.0641478, 0.248816, 0.372951, 0.5837, 0.94732, 1.5626, 2.58936", \ + "0.103009, 0.295926, 0.417294, 0.621086, 0.968777, 1.56897, 2.58937", \ + "0.165147, 0.383553, 0.510613, 0.712866, 1.05197, 1.62416, 2.61363", \ + "0.261887, 0.535797, 0.675087, 0.890924, 1.23906, 1.8026, 2.74944" \ ); } cell_fall (TIMING_DELAY_7x7ds1) { index_1 ("0.0186, 0.0966, 0.174, 0.3294, 0.6408, 1.263, 2.5074"); index_2 ("0.001, 0.0468, 0.078, 0.1296, 0.216, 0.36, 0.6"); values ( \ - "0.0363752, 0.139817, 0.207967, 0.320039, 0.507502, 0.819401, 1.33935", \ - "0.0595417, 0.176808, 0.245245, 0.357238, 0.544598, 0.857028, 1.37667", \ - "0.0736989, 0.209472, 0.281527, 0.39501, 0.582429, 0.894414, 1.41513", \ - "0.093514, 0.260642, 0.343351, 0.466027, 0.657832, 0.970064, 1.48943", \ - "0.118681, 0.33286, 0.434969, 0.579827, 0.794682, 1.11851, 1.63922", \ - "0.153875, 0.428873, 0.560944, 0.742978, 1.00251, 1.37541, 1.93074", \ - "0.198988, 0.55625, 0.726247, 0.965561, 1.29624, 1.75632, 2.40921" \ + "0.0363831, 0.139815, 0.207978, 0.319979, 0.507507, 0.819437, 1.33934", \ + "0.0595416, 0.176761, 0.245208, 0.35725, 0.544619, 0.85676, 1.37661", \ + "0.0736973, 0.209463, 0.281526, 0.395014, 0.582421, 0.894228, 1.41455", \ + "0.0935139, 0.260641, 0.343351, 0.466027, 0.657906, 0.969987, 1.48934", \ + "0.11868, 0.332859, 0.434968, 0.579826, 0.794681, 1.11851, 1.63922", \ + "0.153875, 0.428873, 0.560944, 0.74307, 1.00251, 1.3754, 1.93074", \ + "0.198989, 0.55625, 0.726247, 0.96556, 1.29637, 1.75631, 2.40923" \ ); } fall_transition (TIMING_DELAY_7x7ds1) { index_1 ("0.0186, 0.0966, 0.174, 0.3294, 0.6408, 1.263, 2.5074"); index_2 ("0.001, 0.0468, 0.078, 0.1296, 0.216, 0.36, 0.6"); values ( \ - "0.0262217, 0.158989, 0.249903, 0.399553, 0.649961, 1.06754, 1.7616", \ - "0.0401112, 0.164714, 0.251993, 0.39962, 0.64999, 1.06755, 1.76296", \ - "0.0526766, 0.180257, 0.263292, 0.405332, 0.651626, 1.06756, 1.76297", \ - "0.073088, 0.217227, 0.298536, 0.432898, 0.66664, 1.07284, 1.76298", \ - "0.106672, 0.280638, 0.367692, 0.504562, 0.727783, 1.1096, 1.77568", \ - "0.159986, 0.382943, 0.487328, 0.640063, 0.873102, 1.2446, 1.87141", \ - "0.251052, 0.543414, 0.677319, 0.862832, 1.13457, 1.52961, 2.15535" \ + "0.0262213, 0.158991, 0.249903, 0.399567, 0.650101, 1.06692, 1.76159", \ + "0.0401112, 0.164632, 0.251965, 0.400271, 0.650102, 1.06738, 1.76296", \ + "0.0526777, 0.180244, 0.263227, 0.405313, 0.651624, 1.06848, 1.76346", \ + "0.0730879, 0.217227, 0.298536, 0.432898, 0.666676, 1.07178, 1.76347", \ + "0.106673, 0.280638, 0.367691, 0.504562, 0.727783, 1.1096, 1.77568", \ + "0.159985, 0.382943, 0.487326, 0.640199, 0.873101, 1.2446, 1.8714", \ + "0.251053, 0.543413, 0.677318, 0.862831, 1.13447, 1.52999, 2.15586" \ ); } } @@ -2455,52 +2455,52 @@ library (sg13g2_stdcell_slow_1p35V_125C) { index_1 ("0.0186, 0.0966, 0.174, 0.3294, 0.6408, 1.263, 2.5074"); index_2 ("0.001, 0.0468, 0.078, 0.1296, 0.216, 0.36, 0.6"); values ( \ - "0.0514226, 0.191665, 0.28509, 0.440248, 0.699219, 1.1316, 1.85178", \ - "0.0740962, 0.219387, 0.313471, 0.468468, 0.728434, 1.15978, 1.88057", \ - "0.0869658, 0.244185, 0.338961, 0.494191, 0.753895, 1.18685, 1.90575", \ - "0.102904, 0.286193, 0.386199, 0.544135, 0.803793, 1.23638, 1.95656", \ - "0.126544, 0.352693, 0.467207, 0.637102, 0.904881, 1.33859, 2.05825", \ - "0.157422, 0.446888, 0.583094, 0.78125, 1.07691, 1.53169, 2.25843", \ - "0.200166, 0.57942, 0.753605, 0.993603, 1.34328, 1.85708, 2.63228" \ + "0.0514258, 0.191664, 0.285083, 0.440249, 0.699465, 1.13158, 1.85175", \ + "0.074096, 0.219384, 0.313336, 0.468601, 0.728462, 1.15977, 1.87991", \ + "0.0871154, 0.244178, 0.338965, 0.494165, 0.753783, 1.18672, 1.90588", \ + "0.102909, 0.28619, 0.386195, 0.544134, 0.803783, 1.23592, 1.95638", \ + "0.126543, 0.35269, 0.467203, 0.637095, 0.904871, 1.33857, 2.05824", \ + "0.15742, 0.446884, 0.583088, 0.781239, 1.07689, 1.53167, 2.25825", \ + "0.200163, 0.579414, 0.753598, 0.993593, 1.34326, 1.85706, 2.63226" \ ); } rise_transition (TIMING_DELAY_7x7ds1) { index_1 ("0.0186, 0.0966, 0.174, 0.3294, 0.6408, 1.263, 2.5074"); index_2 ("0.001, 0.0468, 0.078, 0.1296, 0.216, 0.36, 0.6"); values ( \ - "0.0332705, 0.229901, 0.363071, 0.583631, 0.952661, 1.56728, 2.59159", \ - "0.0409982, 0.230328, 0.366216, 0.583632, 0.952662, 1.56766, 2.5916", \ - "0.0513478, 0.236346, 0.366217, 0.585463, 0.952663, 1.56767, 2.59161", \ - "0.0712632, 0.256876, 0.381157, 0.59192, 0.954283, 1.56794, 2.59162", \ - "0.107807, 0.302974, 0.425478, 0.628502, 0.975917, 1.575, 2.5929", \ - "0.164633, 0.390254, 0.517513, 0.719818, 1.05866, 1.63002, 2.61611", \ - "0.252087, 0.538109, 0.678211, 0.895653, 1.24294, 1.8074, 2.75078" \ + "0.0332696, 0.229897, 0.363066, 0.58363, 0.95229, 1.56726, 2.59156", \ + "0.0409975, 0.230404, 0.364764, 0.583631, 0.95266, 1.56764, 2.59252", \ + "0.0512745, 0.236339, 0.365803, 0.585605, 0.952661, 1.56767, 2.59253", \ + "0.071372, 0.256873, 0.381152, 0.591919, 0.954269, 1.56768, 2.59274", \ + "0.107806, 0.302971, 0.425473, 0.628502, 0.975905, 1.57474, 2.59398", \ + "0.164632, 0.39025, 0.517508, 0.719798, 1.05865, 1.63003, 2.61605", \ + "0.252085, 0.538106, 0.678206, 0.895386, 1.24293, 1.80738, 2.75056" \ ); } cell_fall (TIMING_DELAY_7x7ds1) { index_1 ("0.0186, 0.0966, 0.174, 0.3294, 0.6408, 1.263, 2.5074"); index_2 ("0.001, 0.0468, 0.078, 0.1296, 0.216, 0.36, 0.6"); values ( \ - "0.0413624, 0.144493, 0.212528, 0.324605, 0.512021, 0.824001, 1.34398", \ - "0.0636652, 0.176115, 0.24457, 0.356752, 0.544167, 0.856485, 1.37632", \ - "0.0773911, 0.203647, 0.274678, 0.388068, 0.575761, 0.888065, 1.4083", \ - "0.0959756, 0.24894, 0.327753, 0.447652, 0.638927, 0.951915, 1.47217", \ - "0.118869, 0.314783, 0.408222, 0.544446, 0.751716, 1.0737, 1.59594", \ - "0.150322, 0.404548, 0.525049, 0.692024, 0.932446, 1.28801, 1.83578", \ - "0.1906, 0.525871, 0.681424, 0.899585, 1.2021, 1.624, 2.24096" \ + "0.0413669, 0.144495, 0.212537, 0.324807, 0.512228, 0.824251, 1.34398", \ + "0.063665, 0.176115, 0.244548, 0.356765, 0.544243, 0.856762, 1.37631", \ + "0.0773747, 0.203646, 0.274677, 0.38806, 0.57576, 0.887847, 1.40837", \ + "0.0959754, 0.248939, 0.327752, 0.447651, 0.638931, 0.951914, 1.47233", \ + "0.118869, 0.314782, 0.408222, 0.544446, 0.751714, 1.0737, 1.59593", \ + "0.150322, 0.404548, 0.525048, 0.692023, 0.932445, 1.288, 1.83578", \ + "0.190601, 0.525871, 0.681423, 0.899585, 1.2021, 1.62399, 2.24096" \ ); } fall_transition (TIMING_DELAY_7x7ds1) { index_1 ("0.0186, 0.0966, 0.174, 0.3294, 0.6408, 1.263, 2.5074"); index_2 ("0.001, 0.0468, 0.078, 0.1296, 0.216, 0.36, 0.6"); values ( \ - "0.0259471, 0.159231, 0.249809, 0.39937, 0.649208, 1.06607, 1.76316", \ - "0.0351032, 0.162642, 0.250973, 0.399788, 0.65001, 1.06738, 1.76317", \ - "0.045365, 0.172532, 0.258313, 0.403387, 0.650551, 1.06739, 1.76318", \ - "0.064685, 0.198162, 0.281441, 0.420961, 0.660294, 1.06999, 1.76319", \ - "0.0977357, 0.248016, 0.333361, 0.471196, 0.701327, 1.09457, 1.77239", \ - "0.151121, 0.335772, 0.430118, 0.574021, 0.80415, 1.18669, 1.83419", \ - "0.23445, 0.475912, 0.59288, 0.76026, 1.00898, 1.39787, 2.03144" \ + "0.0259499, 0.159231, 0.249814, 0.3995, 0.65011, 1.06744, 1.76315", \ + "0.0351032, 0.162642, 0.251164, 0.399553, 0.650124, 1.06767, 1.76316", \ + "0.0453721, 0.172532, 0.258313, 0.40307, 0.65055, 1.06768, 1.76317", \ + "0.0646853, 0.198162, 0.281438, 0.420961, 0.660569, 1.06999, 1.76318", \ + "0.0977355, 0.248016, 0.333361, 0.471194, 0.701328, 1.09459, 1.77237", \ + "0.15112, 0.335772, 0.430114, 0.57402, 0.804149, 1.18669, 1.83419", \ + "0.23445, 0.47591, 0.592879, 0.760259, 1.00898, 1.39786, 2.03144" \ ); } } @@ -2514,52 +2514,52 @@ library (sg13g2_stdcell_slow_1p35V_125C) { index_1 ("0.0186, 0.0966, 0.174, 0.3294, 0.6408, 1.263, 2.5074"); index_2 ("0.001, 0.0468, 0.078, 0.1296, 0.216, 0.36, 0.6"); values ( \ - "0.0403407, 0.18263, 0.276597, 0.431767, 0.690847, 1.12327, 1.84342", \ - "0.0639163, 0.213783, 0.307992, 0.463355, 0.723587, 1.15542, 1.87609", \ - "0.0787043, 0.246424, 0.341459, 0.496628, 0.756143, 1.18914, 1.90851", \ - "0.0996643, 0.302122, 0.40496, 0.563334, 0.8222, 1.25447, 1.97441", \ - "0.133349, 0.387238, 0.509664, 0.686739, 0.956889, 1.38912, 2.10719", \ - "0.179008, 0.503267, 0.657196, 0.875351, 1.18629, 1.64886, 2.37432", \ - "0.246095, 0.666804, 0.863822, 1.13669, 1.52849, 2.07766, 2.87778" \ + "0.0403404, 0.182618, 0.276588, 0.431758, 0.691157, 1.12326, 1.84344", \ + "0.0639127, 0.213785, 0.307879, 0.463335, 0.723576, 1.15542, 1.87597", \ + "0.0787037, 0.246422, 0.341454, 0.496629, 0.756342, 1.18912, 1.90843", \ + "0.0996637, 0.30212, 0.404953, 0.563327, 0.822189, 1.25409, 1.97428", \ + "0.133348, 0.387212, 0.50966, 0.686733, 0.95677, 1.38903, 2.10765", \ + "0.179005, 0.503263, 0.657191, 0.875346, 1.18628, 1.64885, 2.37429", \ + "0.246089, 0.666798, 0.864048, 1.13668, 1.52848, 2.07752, 2.87775" \ ); } rise_transition (TIMING_DELAY_7x7ds1) { index_1 ("0.0186, 0.0966, 0.174, 0.3294, 0.6408, 1.263, 2.5074"); index_2 ("0.001, 0.0468, 0.078, 0.1296, 0.216, 0.36, 0.6"); values ( \ - "0.0332598, 0.229687, 0.363001, 0.583551, 0.952167, 1.56709, 2.5916", \ - "0.0468761, 0.230933, 0.365025, 0.583552, 0.952848, 1.5671, 2.59176", \ - "0.059291, 0.241322, 0.367709, 0.584882, 0.953015, 1.56763, 2.59177", \ - "0.0792073, 0.273223, 0.39247, 0.597344, 0.955544, 1.56764, 2.59178", \ - "0.111523, 0.336315, 0.45778, 0.653357, 0.989716, 1.57843, 2.59263", \ - "0.165852, 0.440154, 0.580071, 0.785046, 1.11348, 1.66428, 2.62915", \ - "0.259125, 0.607108, 0.769968, 1.01538, 1.37414, 1.92762, 2.83338" \ + "0.0332588, 0.229684, 0.362994, 0.583545, 0.95233, 1.56707, 2.59156", \ + "0.0468045, 0.230906, 0.363978, 0.583546, 0.952834, 1.56759, 2.59158", \ + "0.0592905, 0.241318, 0.367704, 0.585765, 0.952835, 1.56761, 2.59159", \ + "0.0792062, 0.27322, 0.392312, 0.597333, 0.955529, 1.56762, 2.5916", \ + "0.111523, 0.336611, 0.457777, 0.65335, 0.98967, 1.57861, 2.59161", \ + "0.165852, 0.440151, 0.580066, 0.785041, 1.11362, 1.66426, 2.62911", \ + "0.259126, 0.607106, 0.770291, 1.01538, 1.37413, 1.92748, 2.83326" \ ); } cell_fall (TIMING_DELAY_7x7ds1) { index_1 ("0.0186, 0.0966, 0.174, 0.3294, 0.6408, 1.263, 2.5074"); index_2 ("0.001, 0.0468, 0.078, 0.1296, 0.216, 0.36, 0.6"); values ( \ - "0.0200878, 0.0817708, 0.121766, 0.187831, 0.298476, 0.482333, 0.788652", \ - "0.0354332, 0.122363, 0.16496, 0.231595, 0.342092, 0.52617, 0.832516", \ - "0.0429962, 0.152329, 0.20134, 0.273238, 0.38554, 0.569937, 0.876103", \ - "0.0525148, 0.196357, 0.257869, 0.342999, 0.4673, 0.657231, 0.964013", \ - "0.0612419, 0.255222, 0.336689, 0.445608, 0.596554, 0.813504, 1.13437", \ - "0.0691554, 0.328618, 0.439842, 0.58672, 0.782718, 1.0512, 1.42912", \ - "0.0720318, 0.419624, 0.565992, 0.765939, 1.03536, 1.38862, 1.86888" \ + "0.020084, 0.0817563, 0.121741, 0.187838, 0.298482, 0.482537, 0.788672", \ + "0.0354339, 0.122371, 0.164965, 0.231604, 0.342137, 0.526191, 0.832541", \ + "0.0429905, 0.152388, 0.201382, 0.273239, 0.385824, 0.569954, 0.876156", \ + "0.0525158, 0.196373, 0.257875, 0.343007, 0.46733, 0.65723, 0.964076", \ + "0.0612438, 0.255228, 0.3367, 0.445618, 0.596569, 0.813526, 1.13441", \ + "0.0691563, 0.328625, 0.439872, 0.586732, 0.782734, 1.05123, 1.42916", \ + "0.0720631, 0.419635, 0.566004, 0.765954, 1.03538, 1.38865, 1.86891" \ ); } fall_transition (TIMING_DELAY_7x7ds1) { index_1 ("0.0186, 0.0966, 0.174, 0.3294, 0.6408, 1.263, 2.5074"); index_2 ("0.001, 0.0468, 0.078, 0.1296, 0.216, 0.36, 0.6"); values ( \ - "0.0144672, 0.0924941, 0.145586, 0.233518, 0.381114, 0.626585, 1.0353", \ - "0.0355566, 0.10522, 0.153101, 0.236518, 0.381173, 0.626586, 1.03531", \ - "0.0506349, 0.12516, 0.171572, 0.250143, 0.388519, 0.62793, 1.03551", \ - "0.0755045, 0.164103, 0.212817, 0.290247, 0.419881, 0.646483, 1.04123", \ - "0.115405, 0.22551, 0.283682, 0.367608, 0.500474, 0.714226, 1.08405", \ - "0.180573, 0.326609, 0.399459, 0.502359, 0.649674, 0.875774, 1.23355", \ - "0.289133, 0.48812, 0.585181, 0.71882, 0.902524, 1.16736, 1.55068" \ + "0.0144625, 0.0925067, 0.145586, 0.233531, 0.381132, 0.626515, 1.03531", \ + "0.0355573, 0.105222, 0.153123, 0.236529, 0.381192, 0.626554, 1.03532", \ + "0.0506383, 0.125153, 0.171595, 0.250198, 0.388516, 0.627927, 1.03592", \ + "0.0755053, 0.164098, 0.212823, 0.290251, 0.419913, 0.64612, 1.04131", \ + "0.115405, 0.225515, 0.283687, 0.367617, 0.50049, 0.714252, 1.08409", \ + "0.180574, 0.326615, 0.399581, 0.50237, 0.649758, 0.875798, 1.23446", \ + "0.289141, 0.488106, 0.58519, 0.718832, 0.902541, 1.16739, 1.55065" \ ); } } @@ -2573,52 +2573,52 @@ library (sg13g2_stdcell_slow_1p35V_125C) { index_1 ("0.0186, 0.0966, 0.174, 0.3294, 0.6408, 1.263, 2.5074"); index_2 ("0.001, 0.0468, 0.078, 0.1296, 0.216, 0.36, 0.6"); values ( \ - "0.0301862, 0.172435, 0.26658, 0.422052, 0.682209, 1.11554, 1.83771", \ - "0.0488072, 0.203644, 0.297918, 0.45383, 0.71452, 1.14732, 1.8694", \ - "0.0596273, 0.236037, 0.331421, 0.486972, 0.747404, 1.18167, 1.90257", \ - "0.075222, 0.29032, 0.39434, 0.553614, 0.813241, 1.24613, 1.96904", \ - "0.101817, 0.372516, 0.497775, 0.676164, 0.947657, 1.38135, 2.10177", \ - "0.13788, 0.484903, 0.641495, 0.862805, 1.17611, 1.64095, 2.36865", \ - "0.192602, 0.642402, 0.844231, 1.12022, 1.51522, 2.06856, 2.87193" \ + "0.0301858, 0.172432, 0.266576, 0.422029, 0.681884, 1.11552, 1.83769", \ + "0.048776, 0.203641, 0.297924, 0.4537, 0.714514, 1.14774, 1.86962", \ + "0.059627, 0.236035, 0.33142, 0.486966, 0.74701, 1.18166, 1.90256", \ + "0.0752212, 0.290318, 0.394335, 0.553608, 0.813382, 1.24612, 1.96883", \ + "0.101816, 0.372513, 0.497771, 0.676158, 0.947638, 1.38144, 2.10168", \ + "0.137878, 0.484899, 0.641489, 0.862799, 1.1761, 1.64093, 2.36864", \ + "0.192597, 0.642397, 0.844224, 1.12021, 1.51521, 2.06854, 2.8719" \ ); } rise_transition (TIMING_DELAY_7x7ds1) { index_1 ("0.0186, 0.0966, 0.174, 0.3294, 0.6408, 1.263, 2.5074"); index_2 ("0.001, 0.0468, 0.078, 0.1296, 0.216, 0.36, 0.6"); values ( \ - "0.0244791, 0.220518, 0.354144, 0.57492, 0.944903, 1.56135, 2.58865", \ - "0.0394329, 0.222372, 0.35441, 0.575268, 0.9452, 1.56192, 2.58959", \ - "0.050745, 0.233613, 0.359504, 0.575733, 0.945201, 1.56259, 2.5896", \ - "0.0686863, 0.266129, 0.385167, 0.589415, 0.947916, 1.5626, 2.5903", \ - "0.100882, 0.329644, 0.451481, 0.646718, 0.983121, 1.57368, 2.5912", \ - "0.153387, 0.432987, 0.572371, 0.779113, 1.10812, 1.65964, 2.62762", \ - "0.245395, 0.59899, 0.762324, 1.0062, 1.36608, 1.92301, 2.83159" \ + "0.0244762, 0.220514, 0.354146, 0.57491, 0.944493, 1.56132, 2.58861", \ + "0.0394411, 0.222368, 0.354412, 0.575352, 0.945185, 1.56145, 2.58958", \ + "0.0507447, 0.23361, 0.359372, 0.575725, 0.94662, 1.56256, 2.58962", \ + "0.0686859, 0.266126, 0.385041, 0.589407, 0.947999, 1.56257, 2.58963", \ + "0.100882, 0.329643, 0.451476, 0.646711, 0.983271, 1.57369, 2.59111", \ + "0.153389, 0.432985, 0.571698, 0.779286, 1.10811, 1.65964, 2.62754", \ + "0.245395, 0.598988, 0.76232, 1.00619, 1.36607, 1.92299, 2.83155" \ ); } cell_fall (TIMING_DELAY_7x7ds1) { index_1 ("0.0186, 0.0966, 0.174, 0.3294, 0.6408, 1.263, 2.5074"); index_2 ("0.001, 0.0468, 0.078, 0.1296, 0.216, 0.36, 0.6"); values ( \ - "0.019781, 0.0812116, 0.121037, 0.186828, 0.297198, 0.480547, 0.786286", \ - "0.0344767, 0.121734, 0.164252, 0.230701, 0.340785, 0.525928, 0.830112", \ - "0.0413888, 0.151628, 0.200453, 0.272201, 0.384456, 0.568093, 0.873701", \ - "0.0497975, 0.194949, 0.256591, 0.341665, 0.465755, 0.655278, 0.961622", \ - "0.0562848, 0.25287, 0.334622, 0.44356, 0.594439, 0.811237, 1.13188", \ - "0.0578071, 0.32425, 0.43587, 0.58358, 0.779767, 1.04818, 1.42661", \ - "0.0578081, 0.41119, 0.559029, 0.759741, 1.03053, 1.38436, 1.86582" \ + "0.0197815, 0.0811983, 0.121045, 0.186838, 0.297212, 0.480555, 0.786215", \ + "0.0344774, 0.121737, 0.164256, 0.230702, 0.340751, 0.524626, 0.830149", \ + "0.0413798, 0.151657, 0.200448, 0.272205, 0.384496, 0.568012, 0.873913", \ + "0.0497987, 0.194964, 0.256597, 0.341668, 0.465771, 0.65528, 0.961705", \ + "0.0562866, 0.252875, 0.334631, 0.44357, 0.594453, 0.811259, 1.13192", \ + "0.0578101, 0.32426, 0.43597, 0.583594, 0.779557, 1.04824, 1.42658", \ + "0.0578111, 0.4114, 0.55904, 0.759682, 1.03055, 1.38439, 1.86552" \ ); } fall_transition (TIMING_DELAY_7x7ds1) { index_1 ("0.0186, 0.0966, 0.174, 0.3294, 0.6408, 1.263, 2.5074"); index_2 ("0.001, 0.0468, 0.078, 0.1296, 0.216, 0.36, 0.6"); values ( \ - "0.0105525, 0.0864979, 0.139678, 0.227649, 0.37514, 0.620459, 1.02986", \ - "0.0246404, 0.0992007, 0.147243, 0.230741, 0.375513, 0.622347, 1.03004", \ - "0.035981, 0.118542, 0.165482, 0.244289, 0.382448, 0.622348, 1.03018", \ - "0.0548343, 0.156131, 0.206005, 0.284223, 0.413981, 0.640356, 1.03605", \ - "0.0852529, 0.216245, 0.275412, 0.360559, 0.49519, 0.708181, 1.07903", \ - "0.137058, 0.312643, 0.389648, 0.493505, 0.643314, 0.869744, 1.22957", \ - "0.226359, 0.467972, 0.56896, 0.709058, 0.894037, 1.16128, 1.54624" \ + "0.0105532, 0.0865135, 0.139659, 0.227674, 0.375158, 0.620488, 1.02932", \ + "0.0246409, 0.0992039, 0.147283, 0.230747, 0.375292, 0.620616, 1.02955", \ + "0.0359944, 0.118519, 0.165536, 0.244304, 0.382484, 0.622229, 1.03004", \ + "0.0548348, 0.156285, 0.206011, 0.284077, 0.413995, 0.640365, 1.03543", \ + "0.0852534, 0.216249, 0.275418, 0.360569, 0.49521, 0.708199, 1.07907", \ + "0.13706, 0.312642, 0.389784, 0.493515, 0.642334, 0.869715, 1.22867", \ + "0.22682, 0.468223, 0.568969, 0.709049, 0.894056, 1.16131, 1.5438" \ ); } } @@ -2632,52 +2632,52 @@ library (sg13g2_stdcell_slow_1p35V_125C) { index_1 ("0.0186, 0.0966, 0.174, 0.3294, 0.6408, 1.263, 2.5074"); index_2 ("0.001, 0.0468, 0.078, 0.1296, 0.216, 0.36, 0.6"); values ( \ - "0.0251636, 0.130157, 0.199682, 0.314428, 0.506482, 0.826253, 1.35929", \ - "0.042711, 0.165182, 0.23479, 0.349831, 0.541918, 0.862123, 1.39537", \ - "0.0522361, 0.198184, 0.271024, 0.38639, 0.578348, 0.898302, 1.43179", \ - "0.0654093, 0.250326, 0.33404, 0.457213, 0.65082, 0.970301, 1.50384", \ - "0.0871453, 0.325905, 0.431542, 0.577373, 0.79023, 1.11709, 1.64915", \ - "0.114205, 0.427462, 0.562628, 0.750485, 1.01043, 1.38005, 1.93659", \ - "0.152026, 0.563918, 0.743744, 0.985846, 1.32243, 1.78761, 2.43501" \ + "0.0251589, 0.130167, 0.199677, 0.314433, 0.506465, 0.826251, 1.35926", \ + "0.0426913, 0.165183, 0.234773, 0.349801, 0.541938, 0.862057, 1.39534", \ + "0.0521935, 0.198182, 0.271018, 0.386411, 0.578367, 0.898304, 1.43176", \ + "0.0654085, 0.250297, 0.334036, 0.457207, 0.650811, 0.9703, 1.50311", \ + "0.0871438, 0.325902, 0.431539, 0.577367, 0.790221, 1.117, 1.6491", \ + "0.114202, 0.427457, 0.562623, 0.750478, 1.01038, 1.38003, 1.93666", \ + "0.15202, 0.563911, 0.743736, 0.985824, 1.32242, 1.7876, 2.43498" \ ); } rise_transition (TIMING_DELAY_7x7ds1) { index_1 ("0.0186, 0.0966, 0.174, 0.3294, 0.6408, 1.263, 2.5074"); index_2 ("0.001, 0.0468, 0.078, 0.1296, 0.216, 0.36, 0.6"); values ( \ - "0.017977, 0.163931, 0.263842, 0.429278, 0.7062, 1.16769, 1.93659", \ - "0.0336657, 0.167955, 0.264835, 0.429279, 0.706398, 1.1677, 1.93674", \ - "0.0450381, 0.183177, 0.274157, 0.432688, 0.706399, 1.16792, 1.93675", \ - "0.062564, 0.218901, 0.306594, 0.454157, 0.71529, 1.16793, 1.93698", \ - "0.0943567, 0.283876, 0.376251, 0.522592, 0.766043, 1.19439, 1.95263", \ - "0.146882, 0.384481, 0.497726, 0.659597, 0.90761, 1.31087, 2.01048", \ - "0.237912, 0.550028, 0.686756, 0.883398, 1.17212, 1.59558, 2.26905" \ + "0.0179775, 0.163936, 0.263837, 0.42927, 0.706191, 1.16767, 1.93655", \ + "0.0337767, 0.167946, 0.26492, 0.429271, 0.706395, 1.16768, 1.9367", \ + "0.0450394, 0.183174, 0.274146, 0.432457, 0.70656, 1.16799, 1.93671", \ + "0.0625638, 0.218824, 0.306589, 0.454149, 0.715276, 1.16804, 1.93672", \ + "0.0943566, 0.283873, 0.376248, 0.522594, 0.76603, 1.19421, 1.94619", \ + "0.146882, 0.38448, 0.497722, 0.659591, 0.907787, 1.31085, 2.01057", \ + "0.237911, 0.550024, 0.686753, 0.88341, 1.1721, 1.59558, 2.26903" \ ); } cell_fall (TIMING_DELAY_7x7ds1) { index_1 ("0.0186, 0.0966, 0.174, 0.3294, 0.6408, 1.263, 2.5074"); index_2 ("0.001, 0.0468, 0.078, 0.1296, 0.216, 0.36, 0.6"); values ( \ - "0.0194898, 0.0809938, 0.120836, 0.186607, 0.296765, 0.480337, 0.786064", \ - "0.034088, 0.121371, 0.163883, 0.230346, 0.340473, 0.524349, 0.829768", \ - "0.0413587, 0.151166, 0.200031, 0.271837, 0.384125, 0.5677, 0.873538", \ - "0.050807, 0.194771, 0.256256, 0.341289, 0.465479, 0.654931, 0.961382", \ - "0.0598048, 0.253267, 0.334704, 0.443367, 0.594183, 0.811132, 1.13166", \ - "0.0670517, 0.327142, 0.437347, 0.584544, 0.779916, 1.04813, 1.42631", \ - "0.0670527, 0.420734, 0.566348, 0.764477, 1.03319, 1.3862, 1.86606" \ + "0.0194881, 0.0809989, 0.12084, 0.186621, 0.297, 0.480344, 0.786093", \ + "0.0340886, 0.121363, 0.163889, 0.230354, 0.340495, 0.524449, 0.829846", \ + "0.0413583, 0.151093, 0.20005, 0.271829, 0.384145, 0.567735, 0.873582", \ + "0.050809, 0.194769, 0.256262, 0.341298, 0.465492, 0.654951, 0.961397", \ + "0.0598075, 0.253272, 0.334711, 0.443377, 0.594197, 0.811144, 1.13169", \ + "0.0670539, 0.327171, 0.437354, 0.584524, 0.779933, 1.04816, 1.42635", \ + "0.0670549, 0.420744, 0.56636, 0.765052, 1.03321, 1.38623, 1.86589" \ ); } fall_transition (TIMING_DELAY_7x7ds1) { index_1 ("0.0186, 0.0966, 0.174, 0.3294, 0.6408, 1.263, 2.5074"); index_2 ("0.001, 0.0468, 0.078, 0.1296, 0.216, 0.36, 0.6"); values ( \ - "0.0106571, 0.0865014, 0.139656, 0.22767, 0.375138, 0.620477, 1.02977", \ - "0.0249956, 0.0993498, 0.147317, 0.230778, 0.375306, 0.620971, 1.02993", \ - "0.0361667, 0.118859, 0.165686, 0.244396, 0.38253, 0.622289, 1.03002", \ - "0.0544352, 0.156327, 0.206246, 0.284303, 0.414111, 0.6404, 1.03572", \ - "0.0840578, 0.216091, 0.27561, 0.360632, 0.495378, 0.708664, 1.07805", \ - "0.134107, 0.310488, 0.388659, 0.492654, 0.642651, 0.869759, 1.22895", \ - "0.221737, 0.461209, 0.563704, 0.705012, 0.890392, 1.15594, 1.54417" \ + "0.0106595, 0.0865059, 0.139656, 0.227677, 0.375174, 0.620507, 1.02982", \ + "0.0249959, 0.099332, 0.147323, 0.230619, 0.375508, 0.620643, 1.03032", \ + "0.0361684, 0.11891, 0.165744, 0.244478, 0.382508, 0.622325, 1.03033", \ + "0.0544381, 0.156312, 0.206252, 0.284312, 0.414134, 0.640487, 1.03566", \ + "0.0840566, 0.216095, 0.275616, 0.360666, 0.495396, 0.708681, 1.07914", \ + "0.134104, 0.310447, 0.388654, 0.492761, 0.642668, 0.869784, 1.22937", \ + "0.221616, 0.461213, 0.563719, 0.704606, 0.890409, 1.15599, 1.5432" \ ); } } @@ -2689,52 +2689,52 @@ library (sg13g2_stdcell_slow_1p35V_125C) { index_1 ("0.0186, 0.0966, 0.174, 0.3294, 0.6408, 1.263, 2.5074"); index_2 ("0.001, 0.0468, 0.078, 0.1296, 0.216, 0.36, 0.6"); values ( \ - "0.0403407, 0.18263, 0.276597, 0.431767, 0.690847, 1.12327, 1.84342", \ - "0.0639163, 0.213783, 0.307992, 0.463355, 0.723587, 1.15542, 1.87609", \ - "0.0787043, 0.246424, 0.341459, 0.496628, 0.756143, 1.18914, 1.90851", \ - "0.0996643, 0.302122, 0.40496, 0.563334, 0.8222, 1.25447, 1.97441", \ - "0.133349, 0.387238, 0.509664, 0.686739, 0.956889, 1.38912, 2.10719", \ - "0.179008, 0.503267, 0.657196, 0.875351, 1.18629, 1.64886, 2.37432", \ - "0.246095, 0.666804, 0.863822, 1.13669, 1.52849, 2.07766, 2.87778" \ + "0.0403404, 0.182618, 0.276588, 0.431758, 0.691157, 1.12326, 1.84344", \ + "0.0639127, 0.213785, 0.307879, 0.463335, 0.723576, 1.15542, 1.87597", \ + "0.0787037, 0.246422, 0.341454, 0.496629, 0.756342, 1.18912, 1.90843", \ + "0.0996637, 0.30212, 0.404953, 0.563327, 0.822189, 1.25409, 1.97428", \ + "0.133348, 0.387212, 0.50966, 0.686733, 0.95677, 1.38903, 2.10765", \ + "0.179005, 0.503263, 0.657191, 0.875346, 1.18628, 1.64885, 2.37429", \ + "0.246089, 0.666798, 0.864048, 1.13668, 1.52848, 2.07752, 2.87775" \ ); } rise_transition (TIMING_DELAY_7x7ds1) { index_1 ("0.0186, 0.0966, 0.174, 0.3294, 0.6408, 1.263, 2.5074"); index_2 ("0.001, 0.0468, 0.078, 0.1296, 0.216, 0.36, 0.6"); values ( \ - "0.0332598, 0.229687, 0.363001, 0.583551, 0.952167, 1.56709, 2.5916", \ - "0.0468761, 0.230933, 0.365025, 0.583552, 0.952848, 1.5671, 2.59176", \ - "0.059291, 0.241322, 0.367709, 0.584882, 0.953015, 1.56763, 2.59177", \ - "0.0792073, 0.273223, 0.39247, 0.597344, 0.955544, 1.56764, 2.59178", \ - "0.111523, 0.336315, 0.45778, 0.653357, 0.989716, 1.57843, 2.59263", \ - "0.165852, 0.440154, 0.580071, 0.785046, 1.11348, 1.66428, 2.62915", \ - "0.259125, 0.607108, 0.769968, 1.01538, 1.37414, 1.92762, 2.83338" \ + "0.0332588, 0.229684, 0.362994, 0.583545, 0.95233, 1.56707, 2.59156", \ + "0.0468045, 0.230906, 0.363978, 0.583546, 0.952834, 1.56759, 2.59158", \ + "0.0592905, 0.241318, 0.367704, 0.585765, 0.952835, 1.56761, 2.59159", \ + "0.0792062, 0.27322, 0.392312, 0.597333, 0.955529, 1.56762, 2.5916", \ + "0.111523, 0.336611, 0.457777, 0.65335, 0.98967, 1.57861, 2.59161", \ + "0.165852, 0.440151, 0.580066, 0.785041, 1.11362, 1.66426, 2.62911", \ + "0.259126, 0.607106, 0.770291, 1.01538, 1.37413, 1.92748, 2.83326" \ ); } cell_fall (TIMING_DELAY_7x7ds1) { index_1 ("0.0186, 0.0966, 0.174, 0.3294, 0.6408, 1.263, 2.5074"); index_2 ("0.001, 0.0468, 0.078, 0.1296, 0.216, 0.36, 0.6"); values ( \ - "0.0200878, 0.0817708, 0.121766, 0.187831, 0.298476, 0.482333, 0.788652", \ - "0.0354332, 0.122363, 0.16496, 0.231595, 0.342092, 0.52617, 0.832516", \ - "0.0429962, 0.152329, 0.20134, 0.273238, 0.38554, 0.569937, 0.876103", \ - "0.0525148, 0.196357, 0.257869, 0.342999, 0.4673, 0.657231, 0.964013", \ - "0.0612419, 0.255222, 0.336689, 0.445608, 0.596554, 0.813504, 1.13437", \ - "0.0691554, 0.328618, 0.439842, 0.58672, 0.782718, 1.0512, 1.42912", \ - "0.0720318, 0.419624, 0.565992, 0.765939, 1.03536, 1.38862, 1.86888" \ + "0.020084, 0.0817563, 0.121741, 0.187838, 0.298482, 0.482537, 0.788672", \ + "0.0354339, 0.122371, 0.164965, 0.231604, 0.342137, 0.526191, 0.832541", \ + "0.0429905, 0.152388, 0.201382, 0.273239, 0.385824, 0.569954, 0.876156", \ + "0.0525158, 0.196373, 0.257875, 0.343007, 0.46733, 0.65723, 0.964076", \ + "0.0612438, 0.255228, 0.3367, 0.445618, 0.596569, 0.813526, 1.13441", \ + "0.0691563, 0.328625, 0.439872, 0.586732, 0.782734, 1.05123, 1.42916", \ + "0.0720631, 0.419635, 0.566004, 0.765954, 1.03538, 1.38865, 1.86891" \ ); } fall_transition (TIMING_DELAY_7x7ds1) { index_1 ("0.0186, 0.0966, 0.174, 0.3294, 0.6408, 1.263, 2.5074"); index_2 ("0.001, 0.0468, 0.078, 0.1296, 0.216, 0.36, 0.6"); values ( \ - "0.0144672, 0.0924941, 0.145586, 0.233518, 0.381114, 0.626585, 1.0353", \ - "0.0355566, 0.10522, 0.153101, 0.236518, 0.381173, 0.626586, 1.03531", \ - "0.0506349, 0.12516, 0.171572, 0.250143, 0.388519, 0.62793, 1.03551", \ - "0.0755045, 0.164103, 0.212817, 0.290247, 0.419881, 0.646483, 1.04123", \ - "0.115405, 0.22551, 0.283682, 0.367608, 0.500474, 0.714226, 1.08405", \ - "0.180573, 0.326609, 0.399459, 0.502359, 0.649674, 0.875774, 1.23355", \ - "0.289133, 0.48812, 0.585181, 0.71882, 0.902524, 1.16736, 1.55068" \ + "0.0144625, 0.0925067, 0.145586, 0.233531, 0.381132, 0.626515, 1.03531", \ + "0.0355573, 0.105222, 0.153123, 0.236529, 0.381192, 0.626554, 1.03532", \ + "0.0506383, 0.125153, 0.171595, 0.250198, 0.388516, 0.627927, 1.03592", \ + "0.0755053, 0.164098, 0.212823, 0.290251, 0.419913, 0.64612, 1.04131", \ + "0.115405, 0.225515, 0.283687, 0.367617, 0.50049, 0.714252, 1.08409", \ + "0.180574, 0.326615, 0.399581, 0.50237, 0.649758, 0.875798, 1.23446", \ + "0.289141, 0.488106, 0.58519, 0.718832, 0.902541, 1.16739, 1.55065" \ ); } } @@ -2744,26 +2744,26 @@ library (sg13g2_stdcell_slow_1p35V_125C) { index_1 ("0.0186, 0.0966, 0.174, 0.3294, 0.6408, 1.263, 2.5074"); index_2 ("0.001, 0.0468, 0.078, 0.1296, 0.216, 0.36, 0.6"); values ( \ - "0.0109537, 0.0117827, 0.0117231, 0.0116252, 0.011332, 0.0107447, 0.0101611", \ - "0.0103955, 0.0112685, 0.0114074, 0.0113581, 0.0112455, 0.0107464, 0.010395", \ - "0.010493, 0.0111613, 0.0111359, 0.011175, 0.0113297, 0.0107825, 0.0102151", \ - "0.0114397, 0.0110136, 0.0112299, 0.011243, 0.0109218, 0.0106451, 0.0100495", \ - "0.0148582, 0.0124457, 0.0119941, 0.0118, 0.011284, 0.0116836, 0.0101137", \ - "0.0236798, 0.0175422, 0.0161647, 0.014952, 0.0135235, 0.0130757, 0.0120104", \ - "0.0425589, 0.0315096, 0.0284752, 0.0250588, 0.0221906, 0.0183837, 0.0166758" \ + "0.010955, 0.0117794, 0.0117203, 0.011614, 0.0112797, 0.0107486, 0.0101604", \ + "0.0103886, 0.0113034, 0.0115456, 0.0113741, 0.0112529, 0.0107473, 0.0102581", \ + "0.0104919, 0.0111594, 0.0111344, 0.0111612, 0.0110464, 0.0107859, 0.0101204", \ + "0.0114398, 0.0110192, 0.0112012, 0.0111326, 0.0112561, 0.0106357, 0.010043", \ + "0.0148619, 0.0124453, 0.0119936, 0.011813, 0.0112856, 0.0116831, 0.0101633", \ + "0.0236798, 0.0175422, 0.0161654, 0.0149377, 0.013509, 0.0131594, 0.0112408", \ + "0.0425589, 0.0315829, 0.0284, 0.0250467, 0.0221558, 0.0183849, 0.0168793" \ ); } fall_power (POWER_7x7ds1) { index_1 ("0.0186, 0.0966, 0.174, 0.3294, 0.6408, 1.263, 2.5074"); index_2 ("0.001, 0.0468, 0.078, 0.1296, 0.216, 0.36, 0.6"); values ( \ - "0.00747818, 0.00760166, 0.007574, 0.00740954, 0.00719657, 0.00677223, 0.00584041", \ - "0.00701834, 0.00740824, 0.00726488, 0.00717189, 0.00698699, 0.00656899, 0.00583853", \ - "0.00747751, 0.00730281, 0.00738212, 0.00714701, 0.00694713, 0.00644746, 0.00573308", \ - "0.00907196, 0.00815127, 0.00773194, 0.00749606, 0.00735523, 0.00734843, 0.00552902", \ - "0.0130997, 0.0100912, 0.00941815, 0.00869598, 0.00789161, 0.00814198, 0.00669015", \ - "0.021705, 0.0160315, 0.0141893, 0.0127995, 0.011326, 0.00911021, 0.00869654", \ - "0.0401211, 0.0310345, 0.0274527, 0.0239587, 0.0203891, 0.0170046, 0.013193" \ + "0.0074725, 0.00759998, 0.00757578, 0.00741109, 0.00722723, 0.00670059, 0.00583883", \ + "0.00701704, 0.00736092, 0.00726499, 0.00728385, 0.00697898, 0.00656707, 0.00583522", \ + "0.00747232, 0.00728757, 0.00736627, 0.00712376, 0.00693216, 0.00682252, 0.00590449", \ + "0.00908343, 0.00816018, 0.00773194, 0.00749632, 0.00730288, 0.00722353, 0.00564523", \ + "0.013098, 0.0100928, 0.00941428, 0.00871923, 0.0078916, 0.00814601, 0.00669013", \ + "0.0217072, 0.0160319, 0.014192, 0.0128165, 0.011322, 0.00911042, 0.00869761", \ + "0.0401217, 0.0310346, 0.0274529, 0.0239587, 0.0203944, 0.0170913, 0.0133199" \ ); } } @@ -2773,26 +2773,26 @@ library (sg13g2_stdcell_slow_1p35V_125C) { index_1 ("0.0186, 0.0966, 0.174, 0.3294, 0.6408, 1.263, 2.5074"); index_2 ("0.001, 0.0468, 0.078, 0.1296, 0.216, 0.36, 0.6"); values ( \ - "0.0118249, 0.0119816, 0.0118467, 0.0117229, 0.0113808, 0.010806, 0.0102533", \ - "0.0113978, 0.0117718, 0.0119657, 0.0115322, 0.0113449, 0.0108292, 0.010232", \ - "0.0114344, 0.0116727, 0.0115285, 0.0115831, 0.0112291, 0.0108259, 0.0101736", \ - "0.0121723, 0.0117198, 0.0117455, 0.0115582, 0.0113872, 0.0108552, 0.0101312", \ - "0.015211, 0.0132017, 0.0127947, 0.0123449, 0.0117522, 0.0117631, 0.0105852", \ - "0.02347, 0.0183831, 0.0170666, 0.015687, 0.0141909, 0.013832, 0.0118358", \ - "0.0413607, 0.0326298, 0.0295505, 0.0261388, 0.0229136, 0.0193418, 0.0172828" \ + "0.0118259, 0.0119794, 0.011847, 0.0117273, 0.0113615, 0.0108087, 0.0102554", \ + "0.0114021, 0.011706, 0.0118301, 0.0115239, 0.0113287, 0.010828, 0.0103117", \ + "0.0114393, 0.0116679, 0.0115312, 0.0116009, 0.0112263, 0.010858, 0.0103002", \ + "0.0121812, 0.0117198, 0.0117459, 0.0115579, 0.0113883, 0.010765, 0.0103404", \ + "0.0152074, 0.0131936, 0.0127925, 0.0123845, 0.0117316, 0.0118984, 0.0105442", \ + "0.0234693, 0.0183838, 0.0170653, 0.015737, 0.0142189, 0.013656, 0.012229", \ + "0.0413605, 0.0326302, 0.0295444, 0.0261454, 0.0228888, 0.0193292, 0.0170163" \ ); } fall_power (POWER_7x7ds1) { index_1 ("0.0186, 0.0966, 0.174, 0.3294, 0.6408, 1.263, 2.5074"); index_2 ("0.001, 0.0468, 0.078, 0.1296, 0.216, 0.36, 0.6"); values ( \ - "0.0116666, 0.0116536, 0.0115677, 0.0114093, 0.0110841, 0.0105716, 0.0100023", \ - "0.0110502, 0.0114146, 0.0113055, 0.0112519, 0.0110085, 0.0105785, 0.00986819", \ - "0.0111118, 0.0112801, 0.011358, 0.0111711, 0.011, 0.010519, 0.0096179", \ - "0.0120414, 0.0116419, 0.0115079, 0.0113436, 0.0112767, 0.0106491, 0.00970197", \ - "0.0151724, 0.0131064, 0.0127814, 0.0123497, 0.0115301, 0.0115306, 0.0110807", \ - "0.0231262, 0.0180862, 0.0167589, 0.0156, 0.0145253, 0.0128176, 0.0124076", \ - "0.0402589, 0.031652, 0.0284638, 0.0254209, 0.0222444, 0.0198278, 0.016541" \ + "0.011649, 0.0116536, 0.0115762, 0.0114451, 0.0112061, 0.0107422, 0.0099996", \ + "0.0110501, 0.011414, 0.0113025, 0.0112064, 0.0109807, 0.0106166, 0.00983006", \ + "0.0111002, 0.0112801, 0.011358, 0.0110989, 0.0109998, 0.0105743, 0.00980939", \ + "0.0120394, 0.0116419, 0.0114619, 0.0113415, 0.0113298, 0.0105954, 0.00969901", \ + "0.015176, 0.0131065, 0.0127874, 0.01237, 0.0115491, 0.0119556, 0.0110462", \ + "0.0231233, 0.0180854, 0.0167318, 0.015609, 0.0145229, 0.0127479, 0.0124072", \ + "0.0402591, 0.0316506, 0.0284638, 0.0254243, 0.0222443, 0.0198272, 0.0166637" \ ); } } @@ -2803,26 +2803,26 @@ library (sg13g2_stdcell_slow_1p35V_125C) { index_1 ("0.0186, 0.0966, 0.174, 0.3294, 0.6408, 1.263, 2.5074"); index_2 ("0.001, 0.0468, 0.078, 0.1296, 0.216, 0.36, 0.6"); values ( \ - "0.00663149, 0.00744558, 0.00740209, 0.00732532, 0.0070021, 0.00647118, 0.00582525", \ - "0.00656867, 0.00687457, 0.00715392, 0.006945, 0.00685194, 0.00633569, 0.0058573", \ - "0.00728813, 0.00702965, 0.00686167, 0.00689125, 0.00679812, 0.00636601, 0.00575097", \ - "0.00910221, 0.00757481, 0.00742066, 0.00707522, 0.00700639, 0.00626803, 0.00572413", \ - "0.0133989, 0.0101774, 0.00930848, 0.00859777, 0.00758981, 0.00823723, 0.00611039", \ - "0.0229749, 0.016838, 0.0152529, 0.0132192, 0.0111987, 0.00974118, 0.0083185", \ - "0.0428841, 0.0322866, 0.029184, 0.0259372, 0.0220806, 0.0177437, 0.0146772" \ + "0.00661231, 0.00743761, 0.00740163, 0.00730881, 0.00702327, 0.0064705, 0.00583128", \ + "0.00656062, 0.00688622, 0.00704036, 0.0069559, 0.00688372, 0.00643407, 0.00581512", \ + "0.00729384, 0.00702991, 0.0068567, 0.00698216, 0.00675572, 0.0063651, 0.00575537", \ + "0.00909239, 0.00757477, 0.00740474, 0.00707681, 0.00700332, 0.00630886, 0.00578076", \ + "0.0134036, 0.0102018, 0.00932481, 0.00859572, 0.00759286, 0.00807205, 0.0060049", \ + "0.0229761, 0.0168409, 0.0152488, 0.0132831, 0.0112556, 0.0097453, 0.00828983", \ + "0.0428838, 0.0322863, 0.0292109, 0.0259334, 0.0220794, 0.0177274, 0.0149117" \ ); } fall_power (POWER_7x7ds1) { index_1 ("0.0186, 0.0966, 0.174, 0.3294, 0.6408, 1.263, 2.5074"); index_2 ("0.001, 0.0468, 0.078, 0.1296, 0.216, 0.36, 0.6"); values ( \ - "0.00775091, 0.00900519, 0.00885843, 0.00872883, 0.00859763, 0.00812255, 0.00727856", \ - "0.0077343, 0.00860596, 0.00882956, 0.00879592, 0.00855127, 0.00819029, 0.00737458", \ - "0.00843357, 0.00866986, 0.00862699, 0.00869616, 0.00872226, 0.00841417, 0.00734482", \ - "0.0105357, 0.00941812, 0.00931013, 0.00902795, 0.00873642, 0.00854349, 0.00919855", \ - "0.0149127, 0.0113385, 0.0106848, 0.0102262, 0.00967502, 0.00868887, 0.00882557", \ - "0.0246532, 0.017554, 0.0157042, 0.0142126, 0.0129552, 0.0117482, 0.00943245", \ - "0.044285, 0.0332007, 0.0296481, 0.0255866, 0.0221752, 0.0189545, 0.0162771" \ + "0.00774911, 0.00892226, 0.00885485, 0.00874223, 0.00859276, 0.00814664, 0.00721003", \ + "0.00773148, 0.00859995, 0.00881386, 0.00879608, 0.00855524, 0.00819014, 0.00733871", \ + "0.00846628, 0.00868206, 0.00868099, 0.00872484, 0.00874507, 0.00828628, 0.0075255", \ + "0.0105367, 0.00940921, 0.00928962, 0.00901546, 0.00874368, 0.00915445, 0.00879212", \ + "0.0149117, 0.0113286, 0.0106731, 0.0102244, 0.00968017, 0.00863587, 0.00870038", \ + "0.0246534, 0.0175536, 0.0157154, 0.0142125, 0.0130009, 0.0117628, 0.00924224", \ + "0.0442868, 0.0332069, 0.0296539, 0.0255868, 0.0221666, 0.0189422, 0.0161722" \ ); } } @@ -2833,26 +2833,26 @@ library (sg13g2_stdcell_slow_1p35V_125C) { index_1 ("0.0186, 0.0966, 0.174, 0.3294, 0.6408, 1.263, 2.5074"); index_2 ("0.001, 0.0468, 0.078, 0.1296, 0.216, 0.36, 0.6"); values ( \ - "0.00537791, 0.00649773, 0.00651117, 0.00638601, 0.00608094, 0.00552666, 0.00490348", \ - "0.0056652, 0.00593756, 0.00605902, 0.00608876, 0.00594124, 0.00547345, 0.00493987", \ - "0.00654531, 0.00611289, 0.00596233, 0.00589503, 0.00576739, 0.00551599, 0.00491121", \ - "0.00860754, 0.00667766, 0.00652683, 0.00624396, 0.00584968, 0.00532963, 0.00503833", \ - "0.0132715, 0.00940707, 0.00852376, 0.00770544, 0.00672835, 0.00737365, 0.00527824", \ - "0.0232485, 0.0162121, 0.0144311, 0.0125005, 0.0103446, 0.00893541, 0.00784155", \ - "0.0435915, 0.0318626, 0.0286747, 0.0250371, 0.0211873, 0.0165736, 0.0140752" \ + "0.00537789, 0.00649769, 0.00651002, 0.00638066, 0.00607883, 0.00555569, 0.00490529", \ + "0.00565566, 0.00593818, 0.00605943, 0.00610881, 0.00594213, 0.0055296, 0.0049739", \ + "0.00654342, 0.00604366, 0.00596958, 0.0058952, 0.00604627, 0.00550357, 0.00487335", \ + "0.00860678, 0.00667767, 0.00656403, 0.00620366, 0.00597181, 0.00532365, 0.00470741", \ + "0.0132743, 0.00940714, 0.00846119, 0.00770976, 0.0067269, 0.00697736, 0.0053474", \ + "0.0232511, 0.0162115, 0.0143886, 0.0124894, 0.0103462, 0.00963223, 0.00783154", \ + "0.0435923, 0.031861, 0.0286728, 0.025053, 0.0211872, 0.0166006, 0.0139923" \ ); } fall_power (POWER_7x7ds1) { index_1 ("0.0186, 0.0966, 0.174, 0.3294, 0.6408, 1.263, 2.5074"); index_2 ("0.001, 0.0468, 0.078, 0.1296, 0.216, 0.36, 0.6"); values ( \ - "0.00373064, 0.004942, 0.00482646, 0.00471152, 0.00458471, 0.00409562, 0.00326296", \ - "0.00370963, 0.00458667, 0.00478548, 0.00469593, 0.00454925, 0.00477481, 0.0034985", \ - "0.00445809, 0.0046488, 0.0046373, 0.00470179, 0.00475911, 0.0050267, 0.00351009", \ - "0.00661806, 0.00539003, 0.00530136, 0.0050659, 0.00463467, 0.005419, 0.00472878", \ - "0.0110818, 0.00741149, 0.00668681, 0.00628159, 0.00585484, 0.00469679, 0.0050502", \ - "0.020817, 0.0135938, 0.0118595, 0.0102361, 0.0092826, 0.00755861, 0.00556633", \ - "0.0406729, 0.0292824, 0.0257021, 0.0218028, 0.0183565, 0.0152783, 0.0126096" \ + "0.00373162, 0.0050183, 0.00483881, 0.00471039, 0.004584, 0.00409064, 0.00316054", \ + "0.00371024, 0.00458658, 0.00478539, 0.00465311, 0.00451107, 0.00422793, 0.00339525", \ + "0.00445566, 0.00466041, 0.00467985, 0.0047017, 0.00475092, 0.00609281, 0.00356158", \ + "0.00661931, 0.00540899, 0.00529724, 0.00504592, 0.00463815, 0.00541294, 0.00495585", \ + "0.0110832, 0.00741052, 0.00668688, 0.00627397, 0.0058575, 0.00465028, 0.00511088", \ + "0.0208158, 0.0135928, 0.0118748, 0.0102349, 0.0090494, 0.0077337, 0.00526822", \ + "0.040754, 0.029298, 0.0257017, 0.0217919, 0.0183432, 0.0152041, 0.0123555" \ ); } } @@ -2863,26 +2863,26 @@ library (sg13g2_stdcell_slow_1p35V_125C) { index_1 ("0.0186, 0.0966, 0.174, 0.3294, 0.6408, 1.263, 2.5074"); index_2 ("0.001, 0.0468, 0.078, 0.1296, 0.216, 0.36, 0.6"); values ( \ - "0.00539449, 0.00650566, 0.00650785, 0.00639019, 0.00615013, 0.00561596, 0.00573245", \ - "0.00574834, 0.00597317, 0.00602439, 0.00603092, 0.00591874, 0.00543861, 0.0055727", \ - "0.00672494, 0.00605552, 0.00618496, 0.00598298, 0.0058168, 0.00542628, 0.00548746", \ - "0.0089307, 0.00688754, 0.00653703, 0.00649311, 0.00591353, 0.00531964, 0.00572029", \ - "0.0139673, 0.00983063, 0.00885514, 0.00780793, 0.00747339, 0.00604424, 0.00720287", \ - "0.0245994, 0.0170721, 0.0151632, 0.0132475, 0.0110119, 0.0093194, 0.00735325", \ - "0.0462792, 0.0340372, 0.0305805, 0.0265128, 0.0226173, 0.0183432, 0.0138625" \ + "0.00538872, 0.00650594, 0.00650773, 0.00639108, 0.00613851, 0.00562224, 0.00573451", \ + "0.00577401, 0.00598416, 0.00604261, 0.00602411, 0.00591532, 0.00543175, 0.00557172", \ + "0.00672063, 0.00606944, 0.00618396, 0.00594773, 0.0058256, 0.00542564, 0.00548649", \ + "0.00892968, 0.0068616, 0.00655389, 0.00650404, 0.00591508, 0.00539702, 0.00562561", \ + "0.0139649, 0.0098305, 0.00884548, 0.00782321, 0.00747252, 0.00590436, 0.00633941", \ + "0.0245985, 0.0170739, 0.0151631, 0.0132239, 0.0110172, 0.00931895, 0.00735845", \ + "0.0462779, 0.0340358, 0.0305838, 0.0264915, 0.0226111, 0.0181977, 0.0138547" \ ); } fall_power (POWER_7x7ds1) { index_1 ("0.0186, 0.0966, 0.174, 0.3294, 0.6408, 1.263, 2.5074"); index_2 ("0.001, 0.0468, 0.078, 0.1296, 0.216, 0.36, 0.6"); values ( \ - "0.0035479, 0.00477438, 0.00467828, 0.00454515, 0.00431193, 0.00394643, 0.00309778", \ - "0.00359402, 0.00431613, 0.0045113, 0.00445224, 0.00427616, 0.00403675, 0.00323585", \ - "0.00444216, 0.00443318, 0.00442306, 0.00443164, 0.00449248, 0.00477605, 0.00330416", \ - "0.00677473, 0.0053087, 0.00511714, 0.00480575, 0.00434728, 0.00504907, 0.00476615", \ - "0.011603, 0.00753182, 0.00670251, 0.00619274, 0.00572018, 0.00443746, 0.00480801", \ - "0.0219902, 0.0142005, 0.0123939, 0.0105856, 0.00927504, 0.00771971, 0.00523827", \ - "0.0430926, 0.0310148, 0.0271323, 0.0229944, 0.0190636, 0.0156772, 0.0129168" \ + "0.00354736, 0.00477427, 0.00466742, 0.00454486, 0.00442405, 0.00394151, 0.00308874", \ + "0.0035956, 0.00430666, 0.00452685, 0.00437174, 0.00430969, 0.00404822, 0.00329685", \ + "0.00444312, 0.00442427, 0.00440495, 0.00445253, 0.00449291, 0.00475823, 0.00330902", \ + "0.00677526, 0.00526965, 0.00511975, 0.00480283, 0.00439481, 0.00436904, 0.00474494", \ + "0.0116038, 0.00753168, 0.00670892, 0.00620421, 0.00565069, 0.00443574, 0.00502363", \ + "0.0219511, 0.0142028, 0.0123947, 0.0105774, 0.00927193, 0.00780413, 0.00549216", \ + "0.0431065, 0.0310142, 0.027119, 0.0230603, 0.0190639, 0.0155908, 0.0125183" \ ); } } @@ -2892,26 +2892,26 @@ library (sg13g2_stdcell_slow_1p35V_125C) { index_1 ("0.0186, 0.0966, 0.174, 0.3294, 0.6408, 1.263, 2.5074"); index_2 ("0.001, 0.0468, 0.078, 0.1296, 0.216, 0.36, 0.6"); values ( \ - "0.00539449, 0.00650566, 0.00650785, 0.00639019, 0.00615013, 0.00561596, 0.00573245", \ - "0.00574834, 0.00597317, 0.00602439, 0.00603092, 0.00591874, 0.00543861, 0.0055727", \ - "0.00672494, 0.00605552, 0.00618496, 0.00598298, 0.0058168, 0.00542628, 0.00548746", \ - "0.0089307, 0.00688754, 0.00653703, 0.00649311, 0.00591353, 0.00531964, 0.00572029", \ - "0.0139673, 0.00983063, 0.00885514, 0.00780793, 0.00747339, 0.00604424, 0.00720287", \ - "0.0245994, 0.0170721, 0.0151632, 0.0132475, 0.0110119, 0.0093194, 0.00735325", \ - "0.0462792, 0.0340372, 0.0305805, 0.0265128, 0.0226173, 0.0183432, 0.0138625" \ + "0.00538872, 0.00650594, 0.00650773, 0.00639108, 0.00613851, 0.00562224, 0.00573451", \ + "0.00577401, 0.00598416, 0.00604261, 0.00602411, 0.00591532, 0.00543175, 0.00557172", \ + "0.00672063, 0.00606944, 0.00618396, 0.00594773, 0.0058256, 0.00542564, 0.00548649", \ + "0.00892968, 0.0068616, 0.00655389, 0.00650404, 0.00591508, 0.00539702, 0.00562561", \ + "0.0139649, 0.0098305, 0.00884548, 0.00782321, 0.00747252, 0.00590436, 0.00633941", \ + "0.0245985, 0.0170739, 0.0151631, 0.0132239, 0.0110172, 0.00931895, 0.00735845", \ + "0.0462779, 0.0340358, 0.0305838, 0.0264915, 0.0226111, 0.0181977, 0.0138547" \ ); } fall_power (POWER_7x7ds1) { index_1 ("0.0186, 0.0966, 0.174, 0.3294, 0.6408, 1.263, 2.5074"); index_2 ("0.001, 0.0468, 0.078, 0.1296, 0.216, 0.36, 0.6"); values ( \ - "0.0035479, 0.00477438, 0.00467828, 0.00454515, 0.00431193, 0.00394643, 0.00309778", \ - "0.00359402, 0.00431613, 0.0045113, 0.00445224, 0.00427616, 0.00403675, 0.00323585", \ - "0.00444216, 0.00443318, 0.00442306, 0.00443164, 0.00449248, 0.00477605, 0.00330416", \ - "0.00677473, 0.0053087, 0.00511714, 0.00480575, 0.00434728, 0.00504907, 0.00476615", \ - "0.011603, 0.00753182, 0.00670251, 0.00619274, 0.00572018, 0.00443746, 0.00480801", \ - "0.0219902, 0.0142005, 0.0123939, 0.0105856, 0.00927504, 0.00771971, 0.00523827", \ - "0.0430926, 0.0310148, 0.0271323, 0.0229944, 0.0190636, 0.0156772, 0.0129168" \ + "0.00354736, 0.00477427, 0.00466742, 0.00454486, 0.00442405, 0.00394151, 0.00308874", \ + "0.0035956, 0.00430666, 0.00452685, 0.00437174, 0.00430969, 0.00404822, 0.00329685", \ + "0.00444312, 0.00442427, 0.00440495, 0.00445253, 0.00449291, 0.00475823, 0.00330902", \ + "0.00677526, 0.00526965, 0.00511975, 0.00480283, 0.00439481, 0.00436904, 0.00474494", \ + "0.0116038, 0.00753168, 0.00670892, 0.00620421, 0.00565069, 0.00443574, 0.00502363", \ + "0.0219511, 0.0142028, 0.0123947, 0.0105774, 0.00927193, 0.00780413, 0.00549216", \ + "0.0431065, 0.0310142, 0.027119, 0.0230603, 0.0190639, 0.0155908, 0.0125183" \ ); } } @@ -2919,29 +2919,29 @@ library (sg13g2_stdcell_slow_1p35V_125C) { pin (A1) { direction : "input"; max_transition : 2.5074; - capacitance : 0.00570659; - rise_capacitance : 0.0056005; - rise_capacitance_range (0.0056005, 0.0056005); - fall_capacitance : 0.00581268; - fall_capacitance_range (0.00581268, 0.00581268); + capacitance : 0.00570661; + rise_capacitance : 0.00560055; + rise_capacitance_range (0.00511646, 0.00623296); + fall_capacitance : 0.00581267; + fall_capacitance_range (0.0049267, 0.00660859); } pin (A2) { direction : "input"; max_transition : 2.5074; - capacitance : 0.00601964; - rise_capacitance : 0.00611291; - rise_capacitance_range (0.00611291, 0.00611291); - fall_capacitance : 0.00592637; - fall_capacitance_range (0.00592637, 0.00592637); + capacitance : 0.00601975; + rise_capacitance : 0.00611293; + rise_capacitance_range (0.00527141, 0.00680194); + fall_capacitance : 0.00592658; + fall_capacitance_range (0.00523471, 0.00654881); } pin (B1) { direction : "input"; max_transition : 2.5074; - capacitance : 0.00551833; - rise_capacitance : 0.00568136; - rise_capacitance_range (0.00568136, 0.00568136); - fall_capacitance : 0.0053553; - fall_capacitance_range (0.0053553, 0.0053553); + capacitance : 0.00551829; + rise_capacitance : 0.00568128; + rise_capacitance_range (0.0045007, 0.0072063); + fall_capacitance : 0.00535531; + fall_capacitance_range (0.00482208, 0.00603741); } } cell (sg13g2_a221oi_1) { @@ -5010,113 +5010,113 @@ library (sg13g2_stdcell_slow_1p35V_125C) { max_transition : 2.5074; capacitance : 0.00291106; rise_capacitance : 0.00286002; - rise_capacitance_range (0.00286002, 0.00286002); + rise_capacitance_range (0.00268759, 0.00313151); fall_capacitance : 0.0029621; - fall_capacitance_range (0.0029621, 0.0029621); + fall_capacitance_range (0.00257286, 0.00334875); } pin (A2) { direction : "input"; max_transition : 2.5074; capacitance : 0.00297217; rise_capacitance : 0.00302043; - rise_capacitance_range (0.00302043, 0.00302043); + rise_capacitance_range (0.00261421, 0.00332456); fall_capacitance : 0.00292391; - fall_capacitance_range (0.00292391, 0.00292391); + fall_capacitance_range (0.00261217, 0.00325682); } pin (B1) { direction : "input"; max_transition : 2.5074; capacitance : 0.00286379; rise_capacitance : 0.00284064; - rise_capacitance_range (0.00284064, 0.00284064); + rise_capacitance_range (0.00251006, 0.00326258); fall_capacitance : 0.00288693; - fall_capacitance_range (0.00288693, 0.00288693); + fall_capacitance_range (0.00245911, 0.00325082); } pin (B2) { direction : "input"; max_transition : 2.5074; capacitance : 0.00298327; rise_capacitance : 0.00305928; - rise_capacitance_range (0.00305928, 0.00305928); + rise_capacitance_range (0.00253716, 0.00347339); fall_capacitance : 0.00290725; - fall_capacitance_range (0.00290725, 0.00290725); + fall_capacitance_range (0.00255686, 0.00322002); } pin (C1) { direction : "input"; max_transition : 2.5074; capacitance : 0.00279294; rise_capacitance : 0.00288318; - rise_capacitance_range (0.00288318, 0.00288318); + rise_capacitance_range (0.00239242, 0.00357896); fall_capacitance : 0.00270271; - fall_capacitance_range (0.00270271, 0.00270271); + fall_capacitance_range (0.00248753, 0.00293591); } } cell (sg13g2_a22oi_1) { area : 10.8486; cell_footprint : "a22oi"; - cell_leakage_power : 900.793; + cell_leakage_power : 900.818; leakage_power () { - value : 158.843; + value : 158.869; when : "!A1&!A2&!B1&!B2&Y"; } leakage_power () { - value : 270.499; + value : 270.524; when : "!A1&!A2&!B1&B2&Y"; } leakage_power () { - value : 310.256; + value : 310.281; when : "!A1&!A2&B1&!B2&Y"; } leakage_power () { - value : 1556.9; + value : 1556.92; when : "!A1&!A2&B1&B2&!Y"; } leakage_power () { - value : 310.354; + value : 310.38; when : "!A1&A2&!B1&!B2&Y"; } leakage_power () { - value : 422.01; + value : 422.035; when : "!A1&A2&!B1&B2&Y"; } leakage_power () { - value : 461.767; + value : 461.792; when : "!A1&A2&B1&!B2&Y"; } leakage_power () { - value : 1564.36; + value : 1564.39; when : "!A1&A2&B1&B2&!Y"; } leakage_power () { - value : 270.445; + value : 270.47; when : "A1&!A2&!B1&!B2&Y"; } leakage_power () { - value : 382.1; + value : 382.125; when : "A1&!A2&!B1&B2&Y"; } leakage_power () { - value : 421.857; + value : 421.883; when : "A1&!A2&B1&!B2&Y"; } leakage_power () { - value : 1564.25; + value : 1564.27; when : "A1&!A2&B1&B2&!Y"; } leakage_power () { - value : 1965.44; + value : 1965.46; when : "A1&A2&!B1&!B2&!Y"; } leakage_power () { - value : 1968.85; + value : 1968.88; when : "A1&A2&!B1&B2&!Y"; } leakage_power () { - value : 1968.85; + value : 1968.88; when : "A1&A2&B1&!B2&!Y"; } leakage_power () { - value : 815.902; + value : 815.927; when : "A1&A2&B1&B2&!Y"; } pin (Y) { @@ -5134,52 +5134,52 @@ library (sg13g2_stdcell_slow_1p35V_125C) { index_1 ("0.0186, 0.0966, 0.174, 0.3294, 0.6408, 1.263, 2.5074"); index_2 ("0.001, 0.0234, 0.039, 0.0648, 0.108, 0.18, 0.3"); values ( \ - "0.0544736, 0.191239, 0.284871, 0.439589, 0.69863, 1.13007, 1.84922", \ - "0.0775115, 0.219468, 0.313536, 0.468762, 0.728365, 1.15891, 1.87858", \ - "0.0908987, 0.244063, 0.338776, 0.494149, 0.753552, 1.18527, 1.9051", \ - "0.106227, 0.28524, 0.38559, 0.54363, 0.803336, 1.23527, 1.955", \ - "0.127253, 0.350226, 0.465117, 0.635556, 0.903403, 1.33695, 2.05594", \ - "0.151512, 0.440897, 0.578616, 0.778222, 1.07414, 1.52905, 2.25455", \ - "0.182443, 0.565343, 0.742808, 0.98738, 1.33807, 1.85251, 2.62757" \ + "0.0544802, 0.191238, 0.284872, 0.439589, 0.6986, 1.13007, 1.84922", \ + "0.0775757, 0.219464, 0.313535, 0.46876, 0.728362, 1.15891, 1.87858", \ + "0.0907142, 0.244065, 0.338775, 0.494158, 0.753559, 1.18605, 1.9051", \ + "0.106226, 0.285239, 0.385589, 0.54363, 0.803321, 1.23526, 1.95503", \ + "0.127252, 0.350225, 0.465116, 0.635555, 0.9034, 1.33694, 2.05594", \ + "0.151511, 0.440896, 0.578615, 0.778221, 1.07413, 1.52904, 2.25452", \ + "0.182441, 0.565341, 0.742806, 0.987378, 1.33806, 1.8525, 2.62756" \ ); } rise_transition (TIMING_DELAY_7x7ds1) { index_1 ("0.0186, 0.0966, 0.174, 0.3294, 0.6408, 1.263, 2.5074"); index_2 ("0.001, 0.0234, 0.039, 0.0648, 0.108, 0.18, 0.3"); values ( \ - "0.036964, 0.227872, 0.360875, 0.580735, 0.948907, 1.56248, 2.58504", \ - "0.0447615, 0.228657, 0.362281, 0.580736, 0.949281, 1.56249, 2.58505", \ - "0.0556822, 0.234475, 0.363638, 0.583023, 0.949831, 1.5625, 2.58578", \ - "0.0771584, 0.254969, 0.378855, 0.589164, 0.95084, 1.56327, 2.58579", \ - "0.117721, 0.30195, 0.423461, 0.625814, 0.972175, 1.57002, 2.58756", \ - "0.186162, 0.390284, 0.516338, 0.719503, 1.05547, 1.62523, 2.60939", \ - "0.292133, 0.546547, 0.683744, 0.898059, 1.24181, 1.8035, 2.74449" \ + "0.0369688, 0.227872, 0.360873, 0.580733, 0.948905, 1.5624, 2.58503", \ + "0.0447006, 0.228739, 0.361941, 0.580734, 0.949278, 1.56242, 2.58504", \ + "0.0555359, 0.234451, 0.363639, 0.582794, 0.949841, 1.56279, 2.58577", \ + "0.0771582, 0.254966, 0.378854, 0.589156, 0.950827, 1.56327, 2.58578", \ + "0.117722, 0.30195, 0.42346, 0.625813, 0.972168, 1.57002, 2.58755", \ + "0.186162, 0.390283, 0.516336, 0.719501, 1.05547, 1.62528, 2.60935", \ + "0.292134, 0.546546, 0.683743, 0.898058, 1.24181, 1.8035, 2.74448" \ ); } cell_fall (TIMING_DELAY_7x7ds1) { index_1 ("0.0186, 0.0966, 0.174, 0.3294, 0.6408, 1.263, 2.5074"); index_2 ("0.001, 0.0234, 0.039, 0.0648, 0.108, 0.18, 0.3"); values ( \ - "0.0455417, 0.146516, 0.214709, 0.326671, 0.514107, 0.825571, 1.34475", \ - "0.0724998, 0.183516, 0.251867, 0.363883, 0.551079, 0.862682, 1.38197", \ - "0.0896494, 0.216709, 0.288317, 0.401662, 0.588758, 0.900432, 1.41933", \ - "0.113812, 0.26936, 0.351053, 0.473018, 0.664347, 0.976093, 1.49494", \ - "0.14531, 0.343723, 0.444268, 0.587795, 0.80162, 1.12467, 1.64459", \ - "0.188315, 0.443043, 0.573166, 0.753112, 1.01056, 1.38232, 1.93659", \ - "0.244778, 0.574616, 0.742252, 0.978897, 1.30639, 1.76495, 2.41526" \ + "0.0455333, 0.146509, 0.214637, 0.326675, 0.51391, 0.825585, 1.34476", \ + "0.0724868, 0.183517, 0.251864, 0.363884, 0.551044, 0.862701, 1.38199", \ + "0.0896501, 0.216714, 0.28833, 0.401661, 0.588769, 0.900391, 1.42033", \ + "0.113813, 0.26932, 0.351055, 0.47303, 0.664346, 0.9761, 1.49491", \ + "0.145311, 0.343714, 0.44427, 0.587799, 0.801633, 1.12467, 1.64443", \ + "0.188316, 0.443045, 0.573169, 0.753116, 1.01065, 1.38232, 1.93661", \ + "0.24478, 0.574619, 0.742255, 0.978901, 1.30639, 1.76496, 2.41528" \ ); } fall_transition (TIMING_DELAY_7x7ds1) { index_1 ("0.0186, 0.0966, 0.174, 0.3294, 0.6408, 1.263, 2.5074"); index_2 ("0.001, 0.0234, 0.039, 0.0648, 0.108, 0.18, 0.3"); values ( \ - "0.0366046, 0.166686, 0.25699, 0.406471, 0.655859, 1.07343, 1.76615", \ - "0.0505913, 0.171643, 0.259088, 0.408105, 0.656584, 1.07344, 1.76723", \ - "0.0645874, 0.186847, 0.269766, 0.412455, 0.657624, 1.07345, 1.76724", \ - "0.0881569, 0.223245, 0.304455, 0.439242, 0.672823, 1.07838, 1.76725", \ - "0.124586, 0.287199, 0.373919, 0.511213, 0.73325, 1.11468, 1.77821", \ - "0.185151, 0.391478, 0.495053, 0.646088, 0.879651, 1.2508, 1.87558", \ - "0.285261, 0.55473, 0.686425, 0.870499, 1.1417, 1.53506, 2.15922" \ + "0.0366018, 0.166681, 0.256925, 0.406476, 0.656771, 1.07344, 1.76617", \ + "0.050628, 0.171626, 0.259082, 0.406477, 0.656772, 1.07345, 1.76725", \ + "0.0645852, 0.186858, 0.269826, 0.41247, 0.657592, 1.07346, 1.76726", \ + "0.0881572, 0.223428, 0.304456, 0.439205, 0.672837, 1.07839, 1.76727", \ + "0.124587, 0.287249, 0.373921, 0.511216, 0.733264, 1.11501, 1.78076", \ + "0.185151, 0.39148, 0.495055, 0.646084, 0.879668, 1.25059, 1.87556", \ + "0.285261, 0.554731, 0.686427, 0.870502, 1.14171, 1.53507, 2.15924" \ ); } } @@ -5191,52 +5191,52 @@ library (sg13g2_stdcell_slow_1p35V_125C) { index_1 ("0.0186, 0.0966, 0.174, 0.3294, 0.6408, 1.263, 2.5074"); index_2 ("0.001, 0.0234, 0.039, 0.0648, 0.108, 0.18, 0.3"); values ( \ - "0.0544736, 0.191239, 0.284871, 0.439589, 0.69863, 1.13007, 1.84922", \ - "0.0775115, 0.219468, 0.313536, 0.468762, 0.728365, 1.15891, 1.87858", \ - "0.0908987, 0.244063, 0.338776, 0.494149, 0.753552, 1.18527, 1.9051", \ - "0.106227, 0.28524, 0.38559, 0.54363, 0.803336, 1.23527, 1.955", \ - "0.127253, 0.350226, 0.465117, 0.635556, 0.903403, 1.33695, 2.05594", \ - "0.151512, 0.440897, 0.578616, 0.778222, 1.07414, 1.52905, 2.25455", \ - "0.182443, 0.565343, 0.742808, 0.98738, 1.33807, 1.85251, 2.62757" \ + "0.0544802, 0.191238, 0.284872, 0.439589, 0.6986, 1.13007, 1.84922", \ + "0.0775757, 0.219464, 0.313535, 0.46876, 0.728362, 1.15891, 1.87858", \ + "0.0907142, 0.244065, 0.338775, 0.494158, 0.753559, 1.18605, 1.9051", \ + "0.106226, 0.285239, 0.385589, 0.54363, 0.803321, 1.23526, 1.95503", \ + "0.127252, 0.350225, 0.465116, 0.635555, 0.9034, 1.33694, 2.05594", \ + "0.151511, 0.440896, 0.578615, 0.778221, 1.07413, 1.52904, 2.25452", \ + "0.182441, 0.565341, 0.742806, 0.987378, 1.33806, 1.8525, 2.62756" \ ); } rise_transition (TIMING_DELAY_7x7ds1) { index_1 ("0.0186, 0.0966, 0.174, 0.3294, 0.6408, 1.263, 2.5074"); index_2 ("0.001, 0.0234, 0.039, 0.0648, 0.108, 0.18, 0.3"); values ( \ - "0.036964, 0.227872, 0.360875, 0.580735, 0.948907, 1.56248, 2.58504", \ - "0.0447615, 0.228657, 0.362281, 0.580736, 0.949281, 1.56249, 2.58505", \ - "0.0556822, 0.234475, 0.363638, 0.583023, 0.949831, 1.5625, 2.58578", \ - "0.0771584, 0.254969, 0.378855, 0.589164, 0.95084, 1.56327, 2.58579", \ - "0.117721, 0.30195, 0.423461, 0.625814, 0.972175, 1.57002, 2.58756", \ - "0.186162, 0.390284, 0.516338, 0.719503, 1.05547, 1.62523, 2.60939", \ - "0.292133, 0.546547, 0.683744, 0.898059, 1.24181, 1.8035, 2.74449" \ + "0.0369688, 0.227872, 0.360873, 0.580733, 0.948905, 1.5624, 2.58503", \ + "0.0447006, 0.228739, 0.361941, 0.580734, 0.949278, 1.56242, 2.58504", \ + "0.0555359, 0.234451, 0.363639, 0.582794, 0.949841, 1.56279, 2.58577", \ + "0.0771582, 0.254966, 0.378854, 0.589156, 0.950827, 1.56327, 2.58578", \ + "0.117722, 0.30195, 0.42346, 0.625813, 0.972168, 1.57002, 2.58755", \ + "0.186162, 0.390283, 0.516336, 0.719501, 1.05547, 1.62528, 2.60935", \ + "0.292134, 0.546546, 0.683743, 0.898058, 1.24181, 1.8035, 2.74448" \ ); } cell_fall (TIMING_DELAY_7x7ds1) { index_1 ("0.0186, 0.0966, 0.174, 0.3294, 0.6408, 1.263, 2.5074"); index_2 ("0.001, 0.0234, 0.039, 0.0648, 0.108, 0.18, 0.3"); values ( \ - "0.0455417, 0.146516, 0.214709, 0.326671, 0.514107, 0.825571, 1.34475", \ - "0.0724998, 0.183516, 0.251867, 0.363883, 0.551079, 0.862682, 1.38197", \ - "0.0896494, 0.216709, 0.288317, 0.401662, 0.588758, 0.900432, 1.41933", \ - "0.113812, 0.26936, 0.351053, 0.473018, 0.664347, 0.976093, 1.49494", \ - "0.14531, 0.343723, 0.444268, 0.587795, 0.80162, 1.12467, 1.64459", \ - "0.188315, 0.443043, 0.573166, 0.753112, 1.01056, 1.38232, 1.93659", \ - "0.244778, 0.574616, 0.742252, 0.978897, 1.30639, 1.76495, 2.41526" \ + "0.0455333, 0.146509, 0.214637, 0.326675, 0.51391, 0.825585, 1.34476", \ + "0.0724868, 0.183517, 0.251864, 0.363884, 0.551044, 0.862701, 1.38199", \ + "0.0896501, 0.216714, 0.28833, 0.401661, 0.588769, 0.900391, 1.42033", \ + "0.113813, 0.26932, 0.351055, 0.47303, 0.664346, 0.9761, 1.49491", \ + "0.145311, 0.343714, 0.44427, 0.587799, 0.801633, 1.12467, 1.64443", \ + "0.188316, 0.443045, 0.573169, 0.753116, 1.01065, 1.38232, 1.93661", \ + "0.24478, 0.574619, 0.742255, 0.978901, 1.30639, 1.76496, 2.41528" \ ); } fall_transition (TIMING_DELAY_7x7ds1) { index_1 ("0.0186, 0.0966, 0.174, 0.3294, 0.6408, 1.263, 2.5074"); index_2 ("0.001, 0.0234, 0.039, 0.0648, 0.108, 0.18, 0.3"); values ( \ - "0.0366046, 0.166686, 0.25699, 0.406471, 0.655859, 1.07343, 1.76615", \ - "0.0505913, 0.171643, 0.259088, 0.408105, 0.656584, 1.07344, 1.76723", \ - "0.0645874, 0.186847, 0.269766, 0.412455, 0.657624, 1.07345, 1.76724", \ - "0.0881569, 0.223245, 0.304455, 0.439242, 0.672823, 1.07838, 1.76725", \ - "0.124586, 0.287199, 0.373919, 0.511213, 0.73325, 1.11468, 1.77821", \ - "0.185151, 0.391478, 0.495053, 0.646088, 0.879651, 1.2508, 1.87558", \ - "0.285261, 0.55473, 0.686425, 0.870499, 1.1417, 1.53506, 2.15922" \ + "0.0366018, 0.166681, 0.256925, 0.406476, 0.656771, 1.07344, 1.76617", \ + "0.050628, 0.171626, 0.259082, 0.406477, 0.656772, 1.07345, 1.76725", \ + "0.0645852, 0.186858, 0.269826, 0.41247, 0.657592, 1.07346, 1.76726", \ + "0.0881572, 0.223428, 0.304456, 0.439205, 0.672837, 1.07839, 1.76727", \ + "0.124587, 0.287249, 0.373921, 0.511216, 0.733264, 1.11501, 1.78076", \ + "0.185151, 0.39148, 0.495055, 0.646084, 0.879668, 1.25059, 1.87556", \ + "0.285261, 0.554731, 0.686427, 0.870502, 1.14171, 1.53507, 2.15924" \ ); } } @@ -5250,52 +5250,52 @@ library (sg13g2_stdcell_slow_1p35V_125C) { index_1 ("0.0186, 0.0966, 0.174, 0.3294, 0.6408, 1.263, 2.5074"); index_2 ("0.001, 0.0234, 0.039, 0.0648, 0.108, 0.18, 0.3"); values ( \ - "0.0622486, 0.19791, 0.291203, 0.445509, 0.703807, 1.13346, 1.85118", \ - "0.0874533, 0.226858, 0.320411, 0.474841, 0.733215, 1.16297, 1.88061", \ - "0.102998, 0.25202, 0.346351, 0.500827, 0.759485, 1.19032, 1.90801", \ - "0.122507, 0.294675, 0.393832, 0.550911, 0.809585, 1.24019, 1.95741", \ - "0.150148, 0.362071, 0.475019, 0.644064, 0.910274, 1.3423, 2.05896", \ - "0.185552, 0.457276, 0.591533, 0.788748, 1.08287, 1.53505, 2.25873", \ - "0.23626, 0.590301, 0.762765, 1.00321, 1.34954, 1.86193, 2.63332" \ + "0.0622417, 0.197887, 0.291201, 0.445526, 0.703813, 1.13346, 1.85114", \ + "0.087531, 0.226929, 0.320464, 0.476794, 0.733144, 1.16315, 1.88042", \ + "0.102983, 0.252119, 0.346316, 0.500828, 0.759454, 1.1894, 1.90635", \ + "0.122507, 0.294676, 0.393833, 0.550927, 0.809495, 1.24019, 1.95744", \ + "0.150148, 0.362072, 0.47502, 0.644065, 0.910276, 1.3422, 2.05896", \ + "0.185552, 0.457277, 0.591534, 0.788749, 1.08287, 1.53505, 2.2587", \ + "0.236259, 0.590302, 0.762766, 1.00322, 1.34954, 1.86194, 2.63333" \ ); } rise_transition (TIMING_DELAY_7x7ds1) { index_1 ("0.0186, 0.0966, 0.174, 0.3294, 0.6408, 1.263, 2.5074"); index_2 ("0.001, 0.0234, 0.039, 0.0648, 0.108, 0.18, 0.3"); values ( \ - "0.0451161, 0.23614, 0.368989, 0.58813, 0.955402, 1.56689, 2.58696", \ - "0.0518727, 0.23678, 0.369289, 0.588175, 0.955841, 1.5669, 2.58697", \ - "0.0624087, 0.242314, 0.371472, 0.588878, 0.95598, 1.56787, 2.58697", \ - "0.0838233, 0.262383, 0.386229, 0.596281, 0.957823, 1.5681, 2.58698", \ - "0.122721, 0.308931, 0.430178, 0.632451, 0.978395, 1.57501, 2.58699", \ - "0.1869, 0.396255, 0.522416, 0.724581, 1.06138, 1.62969, 2.61195", \ - "0.284695, 0.546618, 0.684982, 0.902257, 1.24632, 1.80741, 2.74601" \ + "0.0451163, 0.236124, 0.36899, 0.58811, 0.955406, 1.5669, 2.58697", \ + "0.0518312, 0.236855, 0.368991, 0.589964, 0.955851, 1.56773, 2.58698", \ + "0.062415, 0.242276, 0.371489, 0.589965, 0.95597, 1.56774, 2.58791", \ + "0.0838234, 0.262383, 0.38623, 0.596271, 0.957456, 1.5681, 2.58792", \ + "0.122721, 0.308932, 0.43018, 0.632452, 0.978398, 1.57492, 2.58793", \ + "0.1869, 0.396255, 0.522417, 0.724496, 1.06138, 1.62967, 2.61226", \ + "0.284298, 0.546619, 0.684983, 0.90226, 1.24632, 1.80742, 2.74602" \ ); } cell_fall (TIMING_DELAY_7x7ds1) { index_1 ("0.0186, 0.0966, 0.174, 0.3294, 0.6408, 1.263, 2.5074"); index_2 ("0.001, 0.0234, 0.039, 0.0648, 0.108, 0.18, 0.3"); values ( \ - "0.049711, 0.150522, 0.218595, 0.330658, 0.518027, 0.829547, 1.34874", \ - "0.0742281, 0.182029, 0.250441, 0.362595, 0.549881, 0.861582, 1.38086", \ - "0.0905318, 0.20996, 0.280723, 0.393958, 0.58147, 0.893147, 1.41287", \ - "0.113017, 0.256251, 0.334282, 0.4538, 0.644722, 0.957292, 1.47656", \ - "0.142335, 0.323788, 0.415943, 0.551422, 0.75778, 1.07916, 1.60052", \ - "0.182012, 0.416906, 0.53538, 0.700099, 0.939527, 1.29405, 1.84029", \ - "0.233163, 0.54213, 0.695642, 0.91063, 1.21102, 1.6319, 2.24671" \ + "0.0497136, 0.150525, 0.218599, 0.330661, 0.518127, 0.829705, 1.34875", \ + "0.0742253, 0.182028, 0.25044, 0.362621, 0.549887, 0.861604, 1.38088", \ + "0.0905323, 0.209985, 0.280732, 0.393957, 0.581448, 0.893399, 1.41289", \ + "0.113018, 0.256252, 0.334315, 0.453806, 0.644713, 0.9573, 1.47658", \ + "0.142336, 0.32379, 0.415946, 0.551423, 0.757784, 1.07917, 1.60053", \ + "0.182013, 0.416908, 0.535383, 0.700095, 0.939533, 1.29406, 1.84029", \ + "0.233164, 0.542133, 0.695645, 0.910635, 1.21102, 1.63243, 2.24722" \ ); } fall_transition (TIMING_DELAY_7x7ds1) { index_1 ("0.0186, 0.0966, 0.174, 0.3294, 0.6408, 1.263, 2.5074"); index_2 ("0.001, 0.0234, 0.039, 0.0648, 0.108, 0.18, 0.3"); values ( \ - "0.0364535, 0.166569, 0.257152, 0.406485, 0.656684, 1.07343, 1.76762", \ - "0.0455436, 0.169683, 0.258227, 0.409437, 0.656685, 1.07344, 1.76763", \ - "0.0560723, 0.179509, 0.265155, 0.409931, 0.657192, 1.07345, 1.76764", \ - "0.077361, 0.205049, 0.28829, 0.427723, 0.666854, 1.07576, 1.76765", \ - "0.11178, 0.254952, 0.339861, 0.477616, 0.707375, 1.10039, 1.77674", \ - "0.168933, 0.342961, 0.436611, 0.581337, 0.809758, 1.19164, 1.83769", \ - "0.260193, 0.485089, 0.600039, 0.766656, 1.01512, 1.40019, 2.03532" \ + "0.0364518, 0.166571, 0.257144, 0.406491, 0.656693, 1.07331, 1.76763", \ + "0.0455077, 0.169682, 0.258148, 0.409474, 0.656694, 1.07332, 1.76764", \ + "0.0560733, 0.179545, 0.265293, 0.409923, 0.657044, 1.07333, 1.76765", \ + "0.0773615, 0.20505, 0.288182, 0.42773, 0.666838, 1.07577, 1.76766", \ + "0.11178, 0.254954, 0.339862, 0.477618, 0.70738, 1.1005, 1.77677", \ + "0.168933, 0.342961, 0.436613, 0.581335, 0.809764, 1.1922, 1.83769", \ + "0.260194, 0.485091, 0.600042, 0.76666, 1.01512, 1.40058, 2.0339" \ ); } } @@ -5307,52 +5307,52 @@ library (sg13g2_stdcell_slow_1p35V_125C) { index_1 ("0.0186, 0.0966, 0.174, 0.3294, 0.6408, 1.263, 2.5074"); index_2 ("0.001, 0.0234, 0.039, 0.0648, 0.108, 0.18, 0.3"); values ( \ - "0.0622486, 0.19791, 0.291203, 0.445509, 0.703807, 1.13346, 1.85118", \ - "0.0874533, 0.226858, 0.320411, 0.474841, 0.733215, 1.16297, 1.88061", \ - "0.102998, 0.25202, 0.346351, 0.500827, 0.759485, 1.19032, 1.90801", \ - "0.122507, 0.294675, 0.393832, 0.550911, 0.809585, 1.24019, 1.95741", \ - "0.150148, 0.362071, 0.475019, 0.644064, 0.910274, 1.3423, 2.05896", \ - "0.185552, 0.457276, 0.591533, 0.788748, 1.08287, 1.53505, 2.25873", \ - "0.23626, 0.590301, 0.762765, 1.00321, 1.34954, 1.86193, 2.63332" \ + "0.0622417, 0.197887, 0.291201, 0.445526, 0.703813, 1.13346, 1.85114", \ + "0.087531, 0.226929, 0.320464, 0.476794, 0.733144, 1.16315, 1.88042", \ + "0.102983, 0.252119, 0.346316, 0.500828, 0.759454, 1.1894, 1.90635", \ + "0.122507, 0.294676, 0.393833, 0.550927, 0.809495, 1.24019, 1.95744", \ + "0.150148, 0.362072, 0.47502, 0.644065, 0.910276, 1.3422, 2.05896", \ + "0.185552, 0.457277, 0.591534, 0.788749, 1.08287, 1.53505, 2.2587", \ + "0.236259, 0.590302, 0.762766, 1.00322, 1.34954, 1.86194, 2.63333" \ ); } rise_transition (TIMING_DELAY_7x7ds1) { index_1 ("0.0186, 0.0966, 0.174, 0.3294, 0.6408, 1.263, 2.5074"); index_2 ("0.001, 0.0234, 0.039, 0.0648, 0.108, 0.18, 0.3"); values ( \ - "0.0451161, 0.23614, 0.368989, 0.58813, 0.955402, 1.56689, 2.58696", \ - "0.0518727, 0.23678, 0.369289, 0.588175, 0.955841, 1.5669, 2.58697", \ - "0.0624087, 0.242314, 0.371472, 0.588878, 0.95598, 1.56787, 2.58697", \ - "0.0838233, 0.262383, 0.386229, 0.596281, 0.957823, 1.5681, 2.58698", \ - "0.122721, 0.308931, 0.430178, 0.632451, 0.978395, 1.57501, 2.58699", \ - "0.1869, 0.396255, 0.522416, 0.724581, 1.06138, 1.62969, 2.61195", \ - "0.284695, 0.546618, 0.684982, 0.902257, 1.24632, 1.80741, 2.74601" \ + "0.0451163, 0.236124, 0.36899, 0.58811, 0.955406, 1.5669, 2.58697", \ + "0.0518312, 0.236855, 0.368991, 0.589964, 0.955851, 1.56773, 2.58698", \ + "0.062415, 0.242276, 0.371489, 0.589965, 0.95597, 1.56774, 2.58791", \ + "0.0838234, 0.262383, 0.38623, 0.596271, 0.957456, 1.5681, 2.58792", \ + "0.122721, 0.308932, 0.43018, 0.632452, 0.978398, 1.57492, 2.58793", \ + "0.1869, 0.396255, 0.522417, 0.724496, 1.06138, 1.62967, 2.61226", \ + "0.284298, 0.546619, 0.684983, 0.90226, 1.24632, 1.80742, 2.74602" \ ); } cell_fall (TIMING_DELAY_7x7ds1) { index_1 ("0.0186, 0.0966, 0.174, 0.3294, 0.6408, 1.263, 2.5074"); index_2 ("0.001, 0.0234, 0.039, 0.0648, 0.108, 0.18, 0.3"); values ( \ - "0.049711, 0.150522, 0.218595, 0.330658, 0.518027, 0.829547, 1.34874", \ - "0.0742281, 0.182029, 0.250441, 0.362595, 0.549881, 0.861582, 1.38086", \ - "0.0905318, 0.20996, 0.280723, 0.393958, 0.58147, 0.893147, 1.41287", \ - "0.113017, 0.256251, 0.334282, 0.4538, 0.644722, 0.957292, 1.47656", \ - "0.142335, 0.323788, 0.415943, 0.551422, 0.75778, 1.07916, 1.60052", \ - "0.182012, 0.416906, 0.53538, 0.700099, 0.939527, 1.29405, 1.84029", \ - "0.233163, 0.54213, 0.695642, 0.91063, 1.21102, 1.6319, 2.24671" \ + "0.0497136, 0.150525, 0.218599, 0.330661, 0.518127, 0.829705, 1.34875", \ + "0.0742253, 0.182028, 0.25044, 0.362621, 0.549887, 0.861604, 1.38088", \ + "0.0905323, 0.209985, 0.280732, 0.393957, 0.581448, 0.893399, 1.41289", \ + "0.113018, 0.256252, 0.334315, 0.453806, 0.644713, 0.9573, 1.47658", \ + "0.142336, 0.32379, 0.415946, 0.551423, 0.757784, 1.07917, 1.60053", \ + "0.182013, 0.416908, 0.535383, 0.700095, 0.939533, 1.29406, 1.84029", \ + "0.233164, 0.542133, 0.695645, 0.910635, 1.21102, 1.63243, 2.24722" \ ); } fall_transition (TIMING_DELAY_7x7ds1) { index_1 ("0.0186, 0.0966, 0.174, 0.3294, 0.6408, 1.263, 2.5074"); index_2 ("0.001, 0.0234, 0.039, 0.0648, 0.108, 0.18, 0.3"); values ( \ - "0.0364535, 0.166569, 0.257152, 0.406485, 0.656684, 1.07343, 1.76762", \ - "0.0455436, 0.169683, 0.258227, 0.409437, 0.656685, 1.07344, 1.76763", \ - "0.0560723, 0.179509, 0.265155, 0.409931, 0.657192, 1.07345, 1.76764", \ - "0.077361, 0.205049, 0.28829, 0.427723, 0.666854, 1.07576, 1.76765", \ - "0.11178, 0.254952, 0.339861, 0.477616, 0.707375, 1.10039, 1.77674", \ - "0.168933, 0.342961, 0.436611, 0.581337, 0.809758, 1.19164, 1.83769", \ - "0.260193, 0.485089, 0.600039, 0.766656, 1.01512, 1.40019, 2.03532" \ + "0.0364518, 0.166571, 0.257144, 0.406491, 0.656693, 1.07331, 1.76763", \ + "0.0455077, 0.169682, 0.258148, 0.409474, 0.656694, 1.07332, 1.76764", \ + "0.0560733, 0.179545, 0.265293, 0.409923, 0.657044, 1.07333, 1.76765", \ + "0.0773615, 0.20505, 0.288182, 0.42773, 0.666838, 1.07577, 1.76766", \ + "0.11178, 0.254954, 0.339862, 0.477618, 0.70738, 1.1005, 1.77677", \ + "0.168933, 0.342961, 0.436613, 0.581335, 0.809764, 1.1922, 1.83769", \ + "0.260194, 0.485091, 0.600042, 0.76666, 1.01512, 1.40058, 2.0339" \ ); } } @@ -5366,52 +5366,52 @@ library (sg13g2_stdcell_slow_1p35V_125C) { index_1 ("0.0186, 0.0966, 0.174, 0.3294, 0.6408, 1.263, 2.5074"); index_2 ("0.001, 0.0234, 0.039, 0.0648, 0.108, 0.18, 0.3"); values ( \ - "0.0581292, 0.195279, 0.289258, 0.44407, 0.703021, 1.13414, 1.85373", \ - "0.0856845, 0.227107, 0.321252, 0.478077, 0.735745, 1.16666, 1.88727", \ - "0.105602, 0.260275, 0.354747, 0.509646, 0.768866, 1.2009, 1.91882", \ - "0.133844, 0.317614, 0.419093, 0.576581, 0.834987, 1.26601, 1.9854", \ - "0.176099, 0.405742, 0.52562, 0.700702, 0.969537, 1.40108, 2.1185", \ - "0.232182, 0.525405, 0.675994, 0.89075, 1.19995, 1.66018, 2.38525", \ - "0.31212, 0.693223, 0.885225, 1.15354, 1.54342, 2.08945, 2.88719" \ + "0.0581271, 0.195277, 0.289225, 0.444074, 0.703057, 1.13396, 1.85374", \ + "0.0857869, 0.227224, 0.321142, 0.476069, 0.735793, 1.16662, 1.88577", \ + "0.105493, 0.260276, 0.354729, 0.509634, 0.768767, 1.20088, 1.91881", \ + "0.133844, 0.317615, 0.419093, 0.576581, 0.834989, 1.2664, 1.98549", \ + "0.1761, 0.405743, 0.525615, 0.700703, 0.969548, 1.40094, 2.11834", \ + "0.232182, 0.525407, 0.675851, 0.890751, 1.19995, 1.66018, 2.38526", \ + "0.312121, 0.693225, 0.885226, 1.15354, 1.54342, 2.08945, 2.88719" \ ); } rise_transition (TIMING_DELAY_7x7ds1) { index_1 ("0.0186, 0.0966, 0.174, 0.3294, 0.6408, 1.263, 2.5074"); index_2 ("0.001, 0.0234, 0.039, 0.0648, 0.108, 0.18, 0.3"); values ( \ - "0.0540494, 0.246358, 0.379431, 0.599889, 0.968134, 1.58182, 2.60502", \ - "0.065211, 0.247265, 0.379432, 0.601288, 0.96849, 1.58263, 2.60538", \ - "0.0798812, 0.256415, 0.38359, 0.603924, 0.968491, 1.58266, 2.60539", \ - "0.104134, 0.287369, 0.406764, 0.612298, 0.971136, 1.58267, 2.6054", \ - "0.142041, 0.351183, 0.471932, 0.66778, 1.0046, 1.59326, 2.60541", \ - "0.203345, 0.459606, 0.595655, 0.800788, 1.12787, 1.67816, 2.64266", \ - "0.303236, 0.630585, 0.793506, 1.03483, 1.39053, 1.94264, 2.84738" \ + "0.0540495, 0.246359, 0.379433, 0.599891, 0.968187, 1.58198, 2.60503", \ + "0.0652139, 0.247205, 0.382567, 0.599892, 0.968465, 1.58264, 2.60598", \ + "0.0799743, 0.256416, 0.38362, 0.60392, 0.968466, 1.58267, 2.60599", \ + "0.104134, 0.28737, 0.406808, 0.612301, 0.97109, 1.58268, 2.606", \ + "0.142042, 0.351184, 0.471897, 0.667781, 1.00422, 1.59306, 2.60616", \ + "0.203346, 0.459607, 0.595541, 0.800789, 1.12788, 1.67817, 2.64266", \ + "0.303235, 0.630584, 0.793506, 1.03483, 1.39054, 1.94265, 2.84738" \ ); } cell_fall (TIMING_DELAY_7x7ds1) { index_1 ("0.0186, 0.0966, 0.174, 0.3294, 0.6408, 1.263, 2.5074"); index_2 ("0.001, 0.0234, 0.039, 0.0648, 0.108, 0.18, 0.3"); values ( \ - "0.0398056, 0.139203, 0.207333, 0.319528, 0.507296, 0.819149, 1.33818", \ - "0.0600411, 0.170736, 0.239424, 0.352046, 0.539913, 0.852347, 1.37107", \ - "0.0721119, 0.197711, 0.269294, 0.383193, 0.571389, 0.883517, 1.40291", \ - "0.0878217, 0.241731, 0.321583, 0.442357, 0.634384, 0.947496, 1.46676", \ - "0.106575, 0.305179, 0.400594, 0.538368, 0.746406, 1.0689, 1.59071", \ - "0.129735, 0.391067, 0.514598, 0.683598, 0.926009, 1.28272, 1.83023", \ - "0.155513, 0.503627, 0.66409, 0.886276, 1.19133, 1.61651, 2.23373" \ + "0.0398161, 0.139224, 0.207334, 0.319541, 0.50717, 0.819128, 1.33818", \ + "0.0600143, 0.170735, 0.239435, 0.351993, 0.53998, 0.852043, 1.37105", \ + "0.0721115, 0.19771, 0.269304, 0.383201, 0.571384, 0.883505, 1.40294", \ + "0.0878212, 0.241729, 0.32158, 0.442354, 0.634379, 0.947487, 1.46675", \ + "0.106574, 0.305177, 0.400592, 0.538365, 0.7464, 1.06889, 1.59069", \ + "0.129734, 0.391076, 0.514595, 0.683594, 0.926002, 1.28271, 1.83024", \ + "0.155511, 0.503624, 0.664086, 0.88625, 1.19133, 1.6165, 2.23371" \ ); } fall_transition (TIMING_DELAY_7x7ds1) { index_1 ("0.0186, 0.0966, 0.174, 0.3294, 0.6408, 1.263, 2.5074"); index_2 ("0.001, 0.0234, 0.039, 0.0648, 0.108, 0.18, 0.3"); values ( \ - "0.0326983, 0.161552, 0.25177, 0.400673, 0.65005, 1.06583, 1.75842", \ - "0.0444024, 0.165176, 0.253039, 0.402238, 0.650188, 1.06617, 1.75843", \ - "0.0569665, 0.175705, 0.260534, 0.404503, 0.650888, 1.06618, 1.75844", \ - "0.0807714, 0.202318, 0.284441, 0.42276, 0.661377, 1.06922, 1.75893", \ - "0.121003, 0.253943, 0.337371, 0.473479, 0.702536, 1.09505, 1.76975", \ - "0.187172, 0.344245, 0.436135, 0.578834, 0.806254, 1.18663, 1.83156", \ - "0.2926, 0.493922, 0.605753, 0.768688, 1.01366, 1.39615, 2.03031" \ + "0.0327126, 0.161539, 0.251767, 0.400669, 0.650019, 1.06581, 1.75838", \ + "0.0443692, 0.165176, 0.25302, 0.403645, 0.650199, 1.06586, 1.75841", \ + "0.0569661, 0.175704, 0.260547, 0.404673, 0.650882, 1.06589, 1.75842", \ + "0.080771, 0.202317, 0.284431, 0.422763, 0.661373, 1.06922, 1.75893", \ + "0.121002, 0.253941, 0.337368, 0.473472, 0.702563, 1.09488, 1.76975", \ + "0.187171, 0.344255, 0.436131, 0.578831, 0.806247, 1.18664, 1.83133", \ + "0.2926, 0.49392, 0.60575, 0.766823, 1.01365, 1.39614, 2.03029" \ ); } } @@ -5425,52 +5425,52 @@ library (sg13g2_stdcell_slow_1p35V_125C) { index_1 ("0.0186, 0.0966, 0.174, 0.3294, 0.6408, 1.263, 2.5074"); index_2 ("0.001, 0.0234, 0.039, 0.0648, 0.108, 0.18, 0.3"); values ( \ - "0.0485488, 0.185176, 0.27848, 0.433031, 0.691133, 1.12148, 1.83849", \ - "0.0740695, 0.217005, 0.310635, 0.465025, 0.723911, 1.15357, 1.8707", \ - "0.091404, 0.249881, 0.344307, 0.498426, 0.756933, 1.18796, 1.90373", \ - "0.115459, 0.305995, 0.408007, 0.565535, 0.823131, 1.253, 1.97017", \ - "0.152567, 0.391477, 0.512742, 0.688652, 0.957559, 1.38812, 2.1033", \ - "0.201506, 0.507399, 0.659769, 0.876414, 1.18653, 1.64683, 2.36986", \ - "0.271102, 0.66928, 0.864375, 1.13585, 1.52687, 2.07435, 2.87088" \ + "0.0485485, 0.185188, 0.27848, 0.433029, 0.691127, 1.12147, 1.83848", \ + "0.0740632, 0.217001, 0.310481, 0.465073, 0.723809, 1.15423, 1.87109", \ + "0.0913693, 0.249874, 0.34429, 0.498465, 0.756676, 1.18797, 1.90373", \ + "0.115459, 0.305995, 0.408006, 0.565534, 0.823127, 1.25319, 1.97017", \ + "0.152566, 0.391476, 0.512741, 0.68865, 0.957557, 1.38812, 2.10316", \ + "0.201506, 0.507399, 0.659768, 0.876412, 1.18653, 1.64682, 2.36985", \ + "0.271102, 0.669279, 0.864374, 1.13585, 1.52687, 2.07426, 2.87088" \ ); } rise_transition (TIMING_DELAY_7x7ds1) { index_1 ("0.0186, 0.0966, 0.174, 0.3294, 0.6408, 1.263, 2.5074"); index_2 ("0.001, 0.0234, 0.039, 0.0648, 0.108, 0.18, 0.3"); values ( \ - "0.0454838, 0.236689, 0.369331, 0.588724, 0.955992, 1.56784, 2.58746", \ - "0.0584676, 0.237821, 0.370287, 0.588725, 0.956284, 1.56785, 2.58747", \ - "0.0727048, 0.247872, 0.373867, 0.591644, 0.956445, 1.56936, 2.58748", \ - "0.096498, 0.279542, 0.398216, 0.602259, 0.95911, 1.56937, 2.58749", \ - "0.132289, 0.343462, 0.463722, 0.658412, 0.993196, 1.57978, 2.58761", \ - "0.190762, 0.450666, 0.587239, 0.791497, 1.11803, 1.66513, 2.62525", \ - "0.287733, 0.619422, 0.783639, 1.02648, 1.37988, 1.92995, 2.8312" \ + "0.0454837, 0.23669, 0.369334, 0.588721, 0.955988, 1.56783, 2.58745", \ + "0.0585309, 0.237819, 0.36995, 0.588722, 0.956284, 1.56784, 2.58746", \ + "0.072693, 0.24787, 0.373993, 0.589229, 0.956541, 1.56935, 2.58839", \ + "0.0964978, 0.279542, 0.398214, 0.602151, 0.959106, 1.56936, 2.5884", \ + "0.132288, 0.343461, 0.463721, 0.65841, 0.993193, 1.57978, 2.58841", \ + "0.190762, 0.450665, 0.587238, 0.791588, 1.11803, 1.66511, 2.62523", \ + "0.287732, 0.619421, 0.783638, 1.02648, 1.37988, 1.92948, 2.83119" \ ); } cell_fall (TIMING_DELAY_7x7ds1) { index_1 ("0.0186, 0.0966, 0.174, 0.3294, 0.6408, 1.263, 2.5074"); index_2 ("0.001, 0.0234, 0.039, 0.0648, 0.108, 0.18, 0.3"); values ( \ - "0.0392838, 0.137937, 0.205599, 0.317171, 0.504165, 0.815503, 1.33448", \ - "0.0591691, 0.169487, 0.237735, 0.349764, 0.536783, 0.848501, 1.3674", \ - "0.0709771, 0.196311, 0.267556, 0.380842, 0.568249, 0.879814, 1.39944", \ - "0.0857623, 0.239966, 0.319504, 0.439877, 0.631233, 0.943774, 1.46323", \ - "0.102686, 0.302655, 0.397868, 0.535525, 0.742988, 1.06519, 1.58701", \ - "0.121993, 0.386548, 0.510615, 0.679844, 0.922134, 1.27865, 1.82653", \ - "0.138391, 0.49609, 0.657084, 0.88059, 1.18772, 1.61187, 2.22991" \ + "0.0392851, 0.137941, 0.205612, 0.317165, 0.504286, 0.815491, 1.33447", \ + "0.059228, 0.169491, 0.237738, 0.349758, 0.536709, 0.84849, 1.36737", \ + "0.0709956, 0.19631, 0.267554, 0.380867, 0.568253, 0.879882, 1.39942", \ + "0.0857618, 0.239965, 0.319502, 0.439874, 0.631235, 0.943765, 1.46309", \ + "0.102685, 0.302653, 0.397865, 0.535301, 0.743091, 1.06519, 1.58699", \ + "0.121992, 0.386546, 0.510612, 0.679839, 0.922128, 1.27865, 1.82652", \ + "0.13839, 0.496087, 0.65708, 0.880583, 1.18771, 1.61185, 2.22987" \ ); } fall_transition (TIMING_DELAY_7x7ds1) { index_1 ("0.0186, 0.0966, 0.174, 0.3294, 0.6408, 1.263, 2.5074"); index_2 ("0.001, 0.0234, 0.039, 0.0648, 0.108, 0.18, 0.3"); values ( \ - "0.0234547, 0.152713, 0.242994, 0.391757, 0.641319, 1.05726, 1.75051", \ - "0.0337322, 0.156228, 0.244349, 0.393106, 0.64132, 1.05827, 1.75052", \ - "0.0445198, 0.166678, 0.251691, 0.396104, 0.642558, 1.05828, 1.75053", \ - "0.0649474, 0.192792, 0.275226, 0.413912, 0.653132, 1.06067, 1.75054", \ - "0.100221, 0.243206, 0.327505, 0.464527, 0.69414, 1.08557, 1.76033", \ - "0.157434, 0.332671, 0.426104, 0.568739, 0.797768, 1.17823, 1.82303", \ - "0.25005, 0.475021, 0.592777, 0.757825, 1.00236, 1.39064, 2.02199" \ + "0.0234573, 0.152712, 0.242997, 0.391753, 0.64182, 1.05724, 1.75049", \ + "0.0337326, 0.156231, 0.244175, 0.393245, 0.641821, 1.0583, 1.7505", \ + "0.0444809, 0.166677, 0.251688, 0.396127, 0.642254, 1.05831, 1.75051", \ + "0.064947, 0.19279, 0.275223, 0.413912, 0.652335, 1.06065, 1.75052", \ + "0.10022, 0.243204, 0.327503, 0.464188, 0.693999, 1.08571, 1.76008", \ + "0.157434, 0.33267, 0.426102, 0.568735, 0.797762, 1.17822, 1.82302", \ + "0.249819, 0.475019, 0.592774, 0.757812, 1.00235, 1.39062, 2.0208" \ ); } } @@ -5482,52 +5482,52 @@ library (sg13g2_stdcell_slow_1p35V_125C) { index_1 ("0.0186, 0.0966, 0.174, 0.3294, 0.6408, 1.263, 2.5074"); index_2 ("0.001, 0.0234, 0.039, 0.0648, 0.108, 0.18, 0.3"); values ( \ - "0.0581292, 0.195279, 0.289258, 0.44407, 0.703021, 1.13414, 1.85373", \ - "0.0856845, 0.227107, 0.321252, 0.478077, 0.735745, 1.16666, 1.88727", \ - "0.105602, 0.260275, 0.354747, 0.509646, 0.768866, 1.2009, 1.91882", \ - "0.133844, 0.317614, 0.419093, 0.576581, 0.834987, 1.26601, 1.9854", \ - "0.176099, 0.405742, 0.52562, 0.700702, 0.969537, 1.40108, 2.1185", \ - "0.232182, 0.525405, 0.675994, 0.89075, 1.19995, 1.66018, 2.38525", \ - "0.31212, 0.693223, 0.885225, 1.15354, 1.54342, 2.08945, 2.88719" \ + "0.0581271, 0.195277, 0.289225, 0.444074, 0.703057, 1.13396, 1.85374", \ + "0.0857869, 0.227224, 0.321142, 0.476069, 0.735793, 1.16662, 1.88577", \ + "0.105493, 0.260276, 0.354729, 0.509634, 0.768767, 1.20088, 1.91881", \ + "0.133844, 0.317615, 0.419093, 0.576581, 0.834989, 1.2664, 1.98549", \ + "0.1761, 0.405743, 0.525615, 0.700703, 0.969548, 1.40094, 2.11834", \ + "0.232182, 0.525407, 0.675851, 0.890751, 1.19995, 1.66018, 2.38526", \ + "0.312121, 0.693225, 0.885226, 1.15354, 1.54342, 2.08945, 2.88719" \ ); } rise_transition (TIMING_DELAY_7x7ds1) { index_1 ("0.0186, 0.0966, 0.174, 0.3294, 0.6408, 1.263, 2.5074"); index_2 ("0.001, 0.0234, 0.039, 0.0648, 0.108, 0.18, 0.3"); values ( \ - "0.0540494, 0.246358, 0.379431, 0.599889, 0.968134, 1.58182, 2.60502", \ - "0.065211, 0.247265, 0.379432, 0.601288, 0.96849, 1.58263, 2.60538", \ - "0.0798812, 0.256415, 0.38359, 0.603924, 0.968491, 1.58266, 2.60539", \ - "0.104134, 0.287369, 0.406764, 0.612298, 0.971136, 1.58267, 2.6054", \ - "0.142041, 0.351183, 0.471932, 0.66778, 1.0046, 1.59326, 2.60541", \ - "0.203345, 0.459606, 0.595655, 0.800788, 1.12787, 1.67816, 2.64266", \ - "0.303236, 0.630585, 0.793506, 1.03483, 1.39053, 1.94264, 2.84738" \ + "0.0540495, 0.246359, 0.379433, 0.599891, 0.968187, 1.58198, 2.60503", \ + "0.0652139, 0.247205, 0.382567, 0.599892, 0.968465, 1.58264, 2.60598", \ + "0.0799743, 0.256416, 0.38362, 0.60392, 0.968466, 1.58267, 2.60599", \ + "0.104134, 0.28737, 0.406808, 0.612301, 0.97109, 1.58268, 2.606", \ + "0.142042, 0.351184, 0.471897, 0.667781, 1.00422, 1.59306, 2.60616", \ + "0.203346, 0.459607, 0.595541, 0.800789, 1.12788, 1.67817, 2.64266", \ + "0.303235, 0.630584, 0.793506, 1.03483, 1.39054, 1.94265, 2.84738" \ ); } cell_fall (TIMING_DELAY_7x7ds1) { index_1 ("0.0186, 0.0966, 0.174, 0.3294, 0.6408, 1.263, 2.5074"); index_2 ("0.001, 0.0234, 0.039, 0.0648, 0.108, 0.18, 0.3"); values ( \ - "0.0398056, 0.139203, 0.207333, 0.319528, 0.507296, 0.819149, 1.33818", \ - "0.0600411, 0.170736, 0.239424, 0.352046, 0.539913, 0.852347, 1.37107", \ - "0.0721119, 0.197711, 0.269294, 0.383193, 0.571389, 0.883517, 1.40291", \ - "0.0878217, 0.241731, 0.321583, 0.442357, 0.634384, 0.947496, 1.46676", \ - "0.106575, 0.305179, 0.400594, 0.538368, 0.746406, 1.0689, 1.59071", \ - "0.129735, 0.391067, 0.514598, 0.683598, 0.926009, 1.28272, 1.83023", \ - "0.155513, 0.503627, 0.66409, 0.886276, 1.19133, 1.61651, 2.23373" \ + "0.0398161, 0.139224, 0.207334, 0.319541, 0.50717, 0.819128, 1.33818", \ + "0.0600143, 0.170735, 0.239435, 0.351993, 0.53998, 0.852043, 1.37105", \ + "0.0721115, 0.19771, 0.269304, 0.383201, 0.571384, 0.883505, 1.40294", \ + "0.0878212, 0.241729, 0.32158, 0.442354, 0.634379, 0.947487, 1.46675", \ + "0.106574, 0.305177, 0.400592, 0.538365, 0.7464, 1.06889, 1.59069", \ + "0.129734, 0.391076, 0.514595, 0.683594, 0.926002, 1.28271, 1.83024", \ + "0.155511, 0.503624, 0.664086, 0.88625, 1.19133, 1.6165, 2.23371" \ ); } fall_transition (TIMING_DELAY_7x7ds1) { index_1 ("0.0186, 0.0966, 0.174, 0.3294, 0.6408, 1.263, 2.5074"); index_2 ("0.001, 0.0234, 0.039, 0.0648, 0.108, 0.18, 0.3"); values ( \ - "0.0326983, 0.161552, 0.25177, 0.400673, 0.65005, 1.06583, 1.75842", \ - "0.0444024, 0.165176, 0.253039, 0.402238, 0.650188, 1.06617, 1.75843", \ - "0.0569665, 0.175705, 0.260534, 0.404503, 0.650888, 1.06618, 1.75844", \ - "0.0807714, 0.202318, 0.284441, 0.42276, 0.661377, 1.06922, 1.75893", \ - "0.121003, 0.253943, 0.337371, 0.473479, 0.702536, 1.09505, 1.76975", \ - "0.187172, 0.344245, 0.436135, 0.578834, 0.806254, 1.18663, 1.83156", \ - "0.2926, 0.493922, 0.605753, 0.768688, 1.01366, 1.39615, 2.03031" \ + "0.0327126, 0.161539, 0.251767, 0.400669, 0.650019, 1.06581, 1.75838", \ + "0.0443692, 0.165176, 0.25302, 0.403645, 0.650199, 1.06586, 1.75841", \ + "0.0569661, 0.175704, 0.260547, 0.404673, 0.650882, 1.06589, 1.75842", \ + "0.080771, 0.202317, 0.284431, 0.422763, 0.661373, 1.06922, 1.75893", \ + "0.121002, 0.253941, 0.337368, 0.473472, 0.702563, 1.09488, 1.76975", \ + "0.187171, 0.344255, 0.436131, 0.578831, 0.806247, 1.18664, 1.83133", \ + "0.2926, 0.49392, 0.60575, 0.766823, 1.01365, 1.39614, 2.03029" \ ); } } @@ -5541,52 +5541,52 @@ library (sg13g2_stdcell_slow_1p35V_125C) { index_1 ("0.0186, 0.0966, 0.174, 0.3294, 0.6408, 1.263, 2.5074"); index_2 ("0.001, 0.0234, 0.039, 0.0648, 0.108, 0.18, 0.3"); values ( \ - "0.0494973, 0.187061, 0.280539, 0.435178, 0.693352, 1.12366, 1.84077", \ - "0.0745059, 0.218354, 0.312263, 0.466942, 0.726056, 1.15574, 1.87428", \ - "0.091487, 0.250859, 0.345508, 0.500192, 0.758634, 1.18986, 1.90602", \ - "0.114943, 0.306523, 0.408824, 0.566626, 0.824769, 1.25481, 1.97145", \ - "0.150542, 0.391283, 0.513163, 0.689394, 0.958674, 1.38932, 2.10538", \ - "0.19548, 0.505717, 0.658561, 0.876373, 1.18689, 1.64773, 2.37116", \ - "0.254668, 0.661187, 0.859109, 1.13247, 1.52432, 2.07361, 2.87113" \ + "0.0494961, 0.187061, 0.280521, 0.435178, 0.693394, 1.12366, 1.84071", \ + "0.0744912, 0.218364, 0.312255, 0.466907, 0.725953, 1.15574, 1.8743", \ + "0.0915108, 0.250859, 0.345523, 0.500193, 0.758635, 1.18987, 1.90603", \ + "0.114943, 0.306524, 0.408825, 0.566627, 0.824692, 1.25515, 1.97149", \ + "0.150542, 0.391283, 0.513164, 0.689395, 0.95868, 1.38947, 2.10513", \ + "0.19548, 0.505718, 0.658563, 0.876374, 1.1869, 1.64773, 2.37117", \ + "0.254669, 0.661189, 0.859111, 1.13247, 1.52432, 2.07362, 2.87113" \ ); } rise_transition (TIMING_DELAY_7x7ds1) { index_1 ("0.0186, 0.0966, 0.174, 0.3294, 0.6408, 1.263, 2.5074"); index_2 ("0.001, 0.0234, 0.039, 0.0648, 0.108, 0.18, 0.3"); values ( \ - "0.0450394, 0.236272, 0.368866, 0.588481, 0.955366, 1.56728, 2.58696", \ - "0.0577287, 0.237238, 0.369309, 0.588482, 0.955717, 1.5678, 2.58729", \ - "0.0720539, 0.247061, 0.373333, 0.591329, 0.956131, 1.56783, 2.5873", \ - "0.0962227, 0.278719, 0.397359, 0.601608, 0.958289, 1.56784, 2.58731", \ - "0.133659, 0.342938, 0.463371, 0.657503, 0.99235, 1.57863, 2.58833", \ - "0.196851, 0.452188, 0.588096, 0.790538, 1.11726, 1.66446, 2.62559", \ - "0.304305, 0.625833, 0.786546, 1.02791, 1.37942, 1.92952, 2.8312" \ + "0.0450396, 0.236273, 0.368732, 0.588482, 0.955434, 1.56728, 2.58696", \ + "0.0577695, 0.237238, 0.370072, 0.588483, 0.956196, 1.5678, 2.5873", \ + "0.0721047, 0.247061, 0.373356, 0.591331, 0.956197, 1.56783, 2.58731", \ + "0.0962228, 0.27872, 0.397359, 0.60161, 0.958532, 1.56784, 2.58756", \ + "0.133659, 0.342938, 0.463371, 0.657508, 0.99239, 1.57849, 2.58757", \ + "0.19685, 0.452189, 0.588097, 0.790541, 1.11727, 1.66447, 2.6256", \ + "0.304305, 0.625834, 0.786547, 1.0279, 1.37942, 1.92952, 2.83119" \ ); } cell_fall (TIMING_DELAY_7x7ds1) { index_1 ("0.0186, 0.0966, 0.174, 0.3294, 0.6408, 1.263, 2.5074"); index_2 ("0.001, 0.0234, 0.039, 0.0648, 0.108, 0.18, 0.3"); values ( \ - "0.0348791, 0.134822, 0.202964, 0.31525, 0.503021, 0.814836, 1.33389", \ - "0.0559636, 0.171826, 0.240451, 0.352854, 0.540647, 0.852974, 1.37179", \ - "0.0681658, 0.203845, 0.276481, 0.390548, 0.578309, 0.890195, 1.4095", \ - "0.0848657, 0.253645, 0.337557, 0.461265, 0.653783, 0.965938, 1.48443", \ - "0.106014, 0.323086, 0.42711, 0.574019, 0.789672, 1.11427, 1.63434", \ - "0.132773, 0.413849, 0.550023, 0.734743, 0.996078, 1.36996, 1.92589", \ - "0.165232, 0.532298, 0.708139, 0.951245, 1.28596, 1.74884, 2.40209" \ + "0.0348867, 0.134816, 0.202972, 0.315247, 0.503013, 0.814806, 1.33388", \ + "0.055953, 0.171824, 0.240441, 0.352874, 0.540635, 0.853051, 1.37179", \ + "0.0681646, 0.203869, 0.2765, 0.390525, 0.578328, 0.890235, 1.40948", \ + "0.0848653, 0.253644, 0.337555, 0.461262, 0.653718, 0.965927, 1.48444", \ + "0.106013, 0.323085, 0.427107, 0.574016, 0.789666, 1.11426, 1.63432", \ + "0.132772, 0.413847, 0.550021, 0.734739, 0.996073, 1.36995, 1.92587", \ + "0.16523, 0.532295, 0.708019, 0.951246, 1.2859, 1.74883, 2.4021" \ ); } fall_transition (TIMING_DELAY_7x7ds1) { index_1 ("0.0186, 0.0966, 0.174, 0.3294, 0.6408, 1.263, 2.5074"); index_2 ("0.001, 0.0234, 0.039, 0.0648, 0.108, 0.18, 0.3"); values ( \ - "0.0331532, 0.161577, 0.251745, 0.400705, 0.650082, 1.06578, 1.75878", \ - "0.0509396, 0.167496, 0.253933, 0.400836, 0.650118, 1.06607, 1.75879", \ - "0.0668468, 0.183666, 0.265761, 0.406828, 0.651496, 1.06608, 1.7588", \ - "0.0932662, 0.221434, 0.301669, 0.435029, 0.66772, 1.07098, 1.75898", \ - "0.135088, 0.286757, 0.372345, 0.508016, 0.729007, 1.10958, 1.77395", \ - "0.205332, 0.393839, 0.495117, 0.64489, 0.874773, 1.24553, 1.86985", \ - "0.322107, 0.564113, 0.693283, 0.872758, 1.13879, 1.53079, 2.15455" \ + "0.0331467, 0.161537, 0.251648, 0.4007, 0.65008, 1.06582, 1.75876", \ + "0.0509394, 0.167494, 0.253944, 0.400915, 0.650111, 1.06584, 1.75877", \ + "0.0668471, 0.183679, 0.265749, 0.406795, 0.651534, 1.06585, 1.75878", \ + "0.0932658, 0.221395, 0.301667, 0.435025, 0.66774, 1.07096, 1.75895", \ + "0.135088, 0.286766, 0.372343, 0.508012, 0.729001, 1.10956, 1.77393", \ + "0.205331, 0.393839, 0.495114, 0.644887, 0.874766, 1.24611, 1.86983", \ + "0.322106, 0.564111, 0.692775, 0.87275, 1.13884, 1.53078, 2.15426" \ ); } } @@ -5600,52 +5600,52 @@ library (sg13g2_stdcell_slow_1p35V_125C) { index_1 ("0.0186, 0.0966, 0.174, 0.3294, 0.6408, 1.263, 2.5074"); index_2 ("0.001, 0.0234, 0.039, 0.0648, 0.108, 0.18, 0.3"); values ( \ - "0.0399452, 0.178059, 0.271643, 0.426591, 0.685455, 1.11691, 1.83602", \ - "0.0622816, 0.209139, 0.303188, 0.458294, 0.718029, 1.14899, 1.86798", \ - "0.0760114, 0.241412, 0.336536, 0.491567, 0.750907, 1.18339, 1.90119", \ - "0.0949189, 0.295875, 0.399281, 0.558059, 0.816761, 1.24796, 1.96755", \ - "0.124516, 0.378204, 0.502079, 0.679953, 0.950423, 1.38282, 2.10026", \ - "0.160975, 0.48875, 0.64462, 0.865127, 1.17796, 1.64094, 2.36641", \ - "0.20962, 0.639835, 0.841797, 1.11766, 1.5132, 2.06572, 2.86611" \ + "0.0399445, 0.178058, 0.27165, 0.426587, 0.685231, 1.11691, 1.83598", \ + "0.0622806, 0.209184, 0.303199, 0.458314, 0.718008, 1.14898, 1.86955", \ + "0.0760109, 0.241412, 0.336536, 0.491566, 0.750905, 1.18339, 1.90121", \ + "0.0949188, 0.295874, 0.399279, 0.558097, 0.816758, 1.24787, 1.9665", \ + "0.124521, 0.378203, 0.502071, 0.679952, 0.950421, 1.38262, 2.10049", \ + "0.160975, 0.48875, 0.644619, 0.865129, 1.17796, 1.64094, 2.3664", \ + "0.20962, 0.639834, 0.841796, 1.11766, 1.51319, 2.06572, 2.86611" \ ); } rise_transition (TIMING_DELAY_7x7ds1) { index_1 ("0.0186, 0.0966, 0.174, 0.3294, 0.6408, 1.263, 2.5074"); index_2 ("0.001, 0.0234, 0.039, 0.0648, 0.108, 0.18, 0.3"); values ( \ - "0.0367722, 0.228114, 0.360875, 0.580685, 0.948909, 1.56246, 2.58503", \ - "0.0514852, 0.229338, 0.361333, 0.580936, 0.949288, 1.56303, 2.58599", \ - "0.0653274, 0.239952, 0.366013, 0.583021, 0.949289, 1.56304, 2.586", \ - "0.0877743, 0.272378, 0.390733, 0.594684, 0.951805, 1.56305, 2.58601", \ - "0.125099, 0.337777, 0.457109, 0.651699, 0.986769, 1.5747, 2.58768", \ - "0.18656, 0.444445, 0.58232, 0.785432, 1.11207, 1.6608, 2.62306", \ - "0.291207, 0.620702, 0.779908, 1.02056, 1.37368, 1.92598, 2.82897" \ + "0.0367661, 0.228113, 0.360879, 0.580684, 0.948826, 1.56245, 2.58501", \ + "0.0514858, 0.229378, 0.361973, 0.580685, 0.949287, 1.56303, 2.58531", \ + "0.0653276, 0.239951, 0.36601, 0.583017, 0.949288, 1.56304, 2.58588", \ + "0.0877743, 0.272378, 0.390725, 0.594721, 0.951814, 1.56305, 2.58589", \ + "0.125103, 0.337776, 0.456908, 0.651695, 0.986681, 1.57487, 2.5859", \ + "0.186406, 0.444444, 0.58232, 0.785427, 1.11206, 1.6608, 2.62291", \ + "0.291207, 0.620701, 0.779907, 1.02055, 1.37371, 1.92598, 2.82897" \ ); } cell_fall (TIMING_DELAY_7x7ds1) { index_1 ("0.0186, 0.0966, 0.174, 0.3294, 0.6408, 1.263, 2.5074"); index_2 ("0.001, 0.0234, 0.039, 0.0648, 0.108, 0.18, 0.3"); values ( \ - "0.0343674, 0.133566, 0.201197, 0.312896, 0.499746, 0.811193, 1.33022", \ - "0.0548187, 0.170574, 0.238809, 0.350554, 0.537592, 0.849375, 1.36812", \ - "0.0665243, 0.202284, 0.27468, 0.388234, 0.57517, 0.886853, 1.40598", \ - "0.0822414, 0.251489, 0.335312, 0.458665, 0.650516, 0.962251, 1.48117", \ - "0.100897, 0.31987, 0.423864, 0.570594, 0.786074, 1.11049, 1.63054", \ - "0.122193, 0.408167, 0.54498, 0.729927, 0.991534, 1.36575, 1.92189", \ - "0.142365, 0.522379, 0.699269, 0.944254, 1.27979, 1.74377, 2.39778" \ + "0.0343693, 0.133563, 0.201198, 0.312897, 0.499958, 0.811211, 1.33021", \ + "0.0548185, 0.170574, 0.238808, 0.350552, 0.53749, 0.849448, 1.36813", \ + "0.0664872, 0.202314, 0.274678, 0.388207, 0.575161, 0.886569, 1.40597", \ + "0.082241, 0.251487, 0.33531, 0.458662, 0.65051, 0.962277, 1.48116", \ + "0.100897, 0.319868, 0.423862, 0.570591, 0.786069, 1.11043, 1.63047", \ + "0.122192, 0.408165, 0.544978, 0.729924, 0.991529, 1.36573, 1.92187", \ + "0.142361, 0.522376, 0.699266, 0.944249, 1.27979, 1.74378, 2.39776" \ ); } fall_transition (TIMING_DELAY_7x7ds1) { index_1 ("0.0186, 0.0966, 0.174, 0.3294, 0.6408, 1.263, 2.5074"); index_2 ("0.001, 0.0234, 0.039, 0.0648, 0.108, 0.18, 0.3"); values ( \ - "0.0238986, 0.152797, 0.24271, 0.39179, 0.641313, 1.05791, 1.75052", \ - "0.0390947, 0.158547, 0.245178, 0.391939, 0.641314, 1.05792, 1.75053", \ - "0.05222, 0.174632, 0.256849, 0.398353, 0.642731, 1.05839, 1.75054", \ - "0.0737958, 0.211463, 0.292226, 0.425988, 0.658942, 1.06332, 1.75112", \ - "0.109616, 0.274802, 0.362491, 0.498615, 0.720443, 1.10084, 1.765", \ - "0.169451, 0.37982, 0.482505, 0.634073, 0.864761, 1.23793, 1.86107", \ - "0.270322, 0.542313, 0.676827, 0.860222, 1.12707, 1.52239, 2.14565" \ + "0.0238946, 0.152585, 0.242708, 0.391786, 0.64184, 1.05724, 1.7505", \ + "0.0390945, 0.158534, 0.244998, 0.393042, 0.641841, 1.05774, 1.75051", \ + "0.0522221, 0.174513, 0.256847, 0.398349, 0.642749, 1.05806, 1.75052", \ + "0.0737956, 0.211462, 0.292223, 0.425984, 0.658719, 1.06253, 1.75111", \ + "0.109616, 0.2748, 0.362488, 0.498611, 0.720458, 1.10077, 1.76359", \ + "0.169452, 0.379818, 0.482502, 0.63407, 0.866641, 1.23792, 1.86105", \ + "0.270321, 0.542311, 0.676825, 0.860218, 1.12706, 1.52237, 2.14563" \ ); } } @@ -5657,52 +5657,52 @@ library (sg13g2_stdcell_slow_1p35V_125C) { index_1 ("0.0186, 0.0966, 0.174, 0.3294, 0.6408, 1.263, 2.5074"); index_2 ("0.001, 0.0234, 0.039, 0.0648, 0.108, 0.18, 0.3"); values ( \ - "0.0494973, 0.187061, 0.280539, 0.435178, 0.693352, 1.12366, 1.84077", \ - "0.0745059, 0.218354, 0.312263, 0.466942, 0.726056, 1.15574, 1.87428", \ - "0.091487, 0.250859, 0.345508, 0.500192, 0.758634, 1.18986, 1.90602", \ - "0.114943, 0.306523, 0.408824, 0.566626, 0.824769, 1.25481, 1.97145", \ - "0.150542, 0.391283, 0.513163, 0.689394, 0.958674, 1.38932, 2.10538", \ - "0.19548, 0.505717, 0.658561, 0.876373, 1.18689, 1.64773, 2.37116", \ - "0.254668, 0.661187, 0.859109, 1.13247, 1.52432, 2.07361, 2.87113" \ + "0.0494961, 0.187061, 0.280521, 0.435178, 0.693394, 1.12366, 1.84071", \ + "0.0744912, 0.218364, 0.312255, 0.466907, 0.725953, 1.15574, 1.8743", \ + "0.0915108, 0.250859, 0.345523, 0.500193, 0.758635, 1.18987, 1.90603", \ + "0.114943, 0.306524, 0.408825, 0.566627, 0.824692, 1.25515, 1.97149", \ + "0.150542, 0.391283, 0.513164, 0.689395, 0.95868, 1.38947, 2.10513", \ + "0.19548, 0.505718, 0.658563, 0.876374, 1.1869, 1.64773, 2.37117", \ + "0.254669, 0.661189, 0.859111, 1.13247, 1.52432, 2.07362, 2.87113" \ ); } rise_transition (TIMING_DELAY_7x7ds1) { index_1 ("0.0186, 0.0966, 0.174, 0.3294, 0.6408, 1.263, 2.5074"); index_2 ("0.001, 0.0234, 0.039, 0.0648, 0.108, 0.18, 0.3"); values ( \ - "0.0450394, 0.236272, 0.368866, 0.588481, 0.955366, 1.56728, 2.58696", \ - "0.0577287, 0.237238, 0.369309, 0.588482, 0.955717, 1.5678, 2.58729", \ - "0.0720539, 0.247061, 0.373333, 0.591329, 0.956131, 1.56783, 2.5873", \ - "0.0962227, 0.278719, 0.397359, 0.601608, 0.958289, 1.56784, 2.58731", \ - "0.133659, 0.342938, 0.463371, 0.657503, 0.99235, 1.57863, 2.58833", \ - "0.196851, 0.452188, 0.588096, 0.790538, 1.11726, 1.66446, 2.62559", \ - "0.304305, 0.625833, 0.786546, 1.02791, 1.37942, 1.92952, 2.8312" \ + "0.0450396, 0.236273, 0.368732, 0.588482, 0.955434, 1.56728, 2.58696", \ + "0.0577695, 0.237238, 0.370072, 0.588483, 0.956196, 1.5678, 2.5873", \ + "0.0721047, 0.247061, 0.373356, 0.591331, 0.956197, 1.56783, 2.58731", \ + "0.0962228, 0.27872, 0.397359, 0.60161, 0.958532, 1.56784, 2.58756", \ + "0.133659, 0.342938, 0.463371, 0.657508, 0.99239, 1.57849, 2.58757", \ + "0.19685, 0.452189, 0.588097, 0.790541, 1.11727, 1.66447, 2.6256", \ + "0.304305, 0.625834, 0.786547, 1.0279, 1.37942, 1.92952, 2.83119" \ ); } cell_fall (TIMING_DELAY_7x7ds1) { index_1 ("0.0186, 0.0966, 0.174, 0.3294, 0.6408, 1.263, 2.5074"); index_2 ("0.001, 0.0234, 0.039, 0.0648, 0.108, 0.18, 0.3"); values ( \ - "0.0348791, 0.134822, 0.202964, 0.31525, 0.503021, 0.814836, 1.33389", \ - "0.0559636, 0.171826, 0.240451, 0.352854, 0.540647, 0.852974, 1.37179", \ - "0.0681658, 0.203845, 0.276481, 0.390548, 0.578309, 0.890195, 1.4095", \ - "0.0848657, 0.253645, 0.337557, 0.461265, 0.653783, 0.965938, 1.48443", \ - "0.106014, 0.323086, 0.42711, 0.574019, 0.789672, 1.11427, 1.63434", \ - "0.132773, 0.413849, 0.550023, 0.734743, 0.996078, 1.36996, 1.92589", \ - "0.165232, 0.532298, 0.708139, 0.951245, 1.28596, 1.74884, 2.40209" \ + "0.0348867, 0.134816, 0.202972, 0.315247, 0.503013, 0.814806, 1.33388", \ + "0.055953, 0.171824, 0.240441, 0.352874, 0.540635, 0.853051, 1.37179", \ + "0.0681646, 0.203869, 0.2765, 0.390525, 0.578328, 0.890235, 1.40948", \ + "0.0848653, 0.253644, 0.337555, 0.461262, 0.653718, 0.965927, 1.48444", \ + "0.106013, 0.323085, 0.427107, 0.574016, 0.789666, 1.11426, 1.63432", \ + "0.132772, 0.413847, 0.550021, 0.734739, 0.996073, 1.36995, 1.92587", \ + "0.16523, 0.532295, 0.708019, 0.951246, 1.2859, 1.74883, 2.4021" \ ); } fall_transition (TIMING_DELAY_7x7ds1) { index_1 ("0.0186, 0.0966, 0.174, 0.3294, 0.6408, 1.263, 2.5074"); index_2 ("0.001, 0.0234, 0.039, 0.0648, 0.108, 0.18, 0.3"); values ( \ - "0.0331532, 0.161577, 0.251745, 0.400705, 0.650082, 1.06578, 1.75878", \ - "0.0509396, 0.167496, 0.253933, 0.400836, 0.650118, 1.06607, 1.75879", \ - "0.0668468, 0.183666, 0.265761, 0.406828, 0.651496, 1.06608, 1.7588", \ - "0.0932662, 0.221434, 0.301669, 0.435029, 0.66772, 1.07098, 1.75898", \ - "0.135088, 0.286757, 0.372345, 0.508016, 0.729007, 1.10958, 1.77395", \ - "0.205332, 0.393839, 0.495117, 0.64489, 0.874773, 1.24553, 1.86985", \ - "0.322107, 0.564113, 0.693283, 0.872758, 1.13879, 1.53079, 2.15455" \ + "0.0331467, 0.161537, 0.251648, 0.4007, 0.65008, 1.06582, 1.75876", \ + "0.0509394, 0.167494, 0.253944, 0.400915, 0.650111, 1.06584, 1.75877", \ + "0.0668471, 0.183679, 0.265749, 0.406795, 0.651534, 1.06585, 1.75878", \ + "0.0932658, 0.221395, 0.301667, 0.435025, 0.66774, 1.07096, 1.75895", \ + "0.135088, 0.286766, 0.372343, 0.508012, 0.729001, 1.10956, 1.77393", \ + "0.205331, 0.393839, 0.495114, 0.644887, 0.874766, 1.24611, 1.86983", \ + "0.322106, 0.564111, 0.692775, 0.87275, 1.13884, 1.53078, 2.15426" \ ); } } @@ -5713,26 +5713,26 @@ library (sg13g2_stdcell_slow_1p35V_125C) { index_1 ("0.0186, 0.0966, 0.174, 0.3294, 0.6408, 1.263, 2.5074"); index_2 ("0.001, 0.0234, 0.039, 0.0648, 0.108, 0.18, 0.3"); values ( \ - "0.00588922, 0.00617906, 0.00615248, 0.0060821, 0.00591506, 0.00566093, 0.00532551", \ - "0.00552549, 0.0059444, 0.00604164, 0.00596594, 0.00589154, 0.00561032, 0.00543999", \ - "0.00552835, 0.0058456, 0.00583776, 0.00594442, 0.00588775, 0.00559635, 0.00547912", \ - "0.00583379, 0.00574834, 0.00588153, 0.00580519, 0.00584609, 0.00560758, 0.00528822", \ - "0.00725633, 0.00636973, 0.00617826, 0.00611475, 0.00585822, 0.00611505, 0.00547777", \ - "0.0113682, 0.00877865, 0.00815628, 0.00765831, 0.0069592, 0.00670112, 0.00636633", \ - "0.0206094, 0.0156724, 0.0141458, 0.0125865, 0.0110741, 0.00942872, 0.00853288" \ + "0.00588983, 0.00617957, 0.00615307, 0.00608857, 0.00592484, 0.00565815, 0.00532586", \ + "0.00552533, 0.00598173, 0.0060234, 0.00595791, 0.00589162, 0.00561127, 0.00544017", \ + "0.00551603, 0.00584413, 0.0058376, 0.00594175, 0.0058885, 0.00560613, 0.00548019", \ + "0.00583399, 0.00574663, 0.00588158, 0.00590795, 0.00583936, 0.00560738, 0.00531037", \ + "0.00725661, 0.00637222, 0.00622255, 0.00611475, 0.00587828, 0.00611499, 0.00547729", \ + "0.0113681, 0.00877845, 0.00815637, 0.00765831, 0.00695947, 0.00683684, 0.00618511", \ + "0.020609, 0.0156721, 0.0141533, 0.0125864, 0.0110744, 0.0094627, 0.00853274" \ ); } fall_power (POWER_7x7ds1) { index_1 ("0.0186, 0.0966, 0.174, 0.3294, 0.6408, 1.263, 2.5074"); index_2 ("0.001, 0.0234, 0.039, 0.0648, 0.108, 0.18, 0.3"); values ( \ - "0.00622321, 0.00622411, 0.00617633, 0.00610921, 0.00597819, 0.0058018, 0.00534654", \ - "0.00594358, 0.00612045, 0.00604746, 0.00607685, 0.00588922, 0.00565071, 0.00529172", \ - "0.00609654, 0.00604346, 0.00608252, 0.00598857, 0.00585913, 0.00559989, 0.00523665", \ - "0.00677587, 0.00644429, 0.00624719, 0.00615538, 0.00600989, 0.0060811, 0.00521386", \ - "0.00861332, 0.00737624, 0.0070555, 0.00673399, 0.0062914, 0.00646079, 0.00534847", \ - "0.0127781, 0.0102832, 0.00943306, 0.00873137, 0.00799254, 0.0069528, 0.00680945", \ - "0.0217825, 0.0176731, 0.0159663, 0.0143029, 0.0125455, 0.0108648, 0.00891828" \ + "0.00621298, 0.00622372, 0.00617567, 0.00611012, 0.0059969, 0.00580175, 0.00534621", \ + "0.0059437, 0.00612017, 0.00604766, 0.00595423, 0.00587652, 0.00560563, 0.00529113", \ + "0.00609401, 0.00604285, 0.0060839, 0.00598927, 0.00585436, 0.00561155, 0.00533043", \ + "0.00678152, 0.00644806, 0.00626162, 0.00615093, 0.00601083, 0.0060817, 0.00518266", \ + "0.00861207, 0.0073766, 0.00706286, 0.00673408, 0.0063193, 0.00645694, 0.00554119", \ + "0.0127782, 0.0102832, 0.00943467, 0.00874155, 0.00806391, 0.00703349, 0.00680842", \ + "0.0217831, 0.0176728, 0.0159661, 0.0143022, 0.0125433, 0.0108672, 0.00891726" \ ); } } @@ -5742,26 +5742,26 @@ library (sg13g2_stdcell_slow_1p35V_125C) { index_1 ("0.0186, 0.0966, 0.174, 0.3294, 0.6408, 1.263, 2.5074"); index_2 ("0.001, 0.0234, 0.039, 0.0648, 0.108, 0.18, 0.3"); values ( \ - "0.00588922, 0.00617906, 0.00615248, 0.0060821, 0.00591506, 0.00566093, 0.00532551", \ - "0.00552549, 0.0059444, 0.00604164, 0.00596594, 0.00589154, 0.00561032, 0.00543999", \ - "0.00552835, 0.0058456, 0.00583776, 0.00594442, 0.00588775, 0.00559635, 0.00547912", \ - "0.00583379, 0.00574834, 0.00588153, 0.00580519, 0.00584609, 0.00560758, 0.00528822", \ - "0.00725633, 0.00636973, 0.00617826, 0.00611475, 0.00585822, 0.00611505, 0.00547777", \ - "0.0113682, 0.00877865, 0.00815628, 0.00765831, 0.0069592, 0.00670112, 0.00636633", \ - "0.0206094, 0.0156724, 0.0141458, 0.0125865, 0.0110741, 0.00942872, 0.00853288" \ + "0.00588983, 0.00617957, 0.00615307, 0.00608857, 0.00592484, 0.00565815, 0.00532586", \ + "0.00552533, 0.00598173, 0.0060234, 0.00595791, 0.00589162, 0.00561127, 0.00544017", \ + "0.00551603, 0.00584413, 0.0058376, 0.00594175, 0.0058885, 0.00560613, 0.00548019", \ + "0.00583399, 0.00574663, 0.00588158, 0.00590795, 0.00583936, 0.00560738, 0.00531037", \ + "0.00725661, 0.00637222, 0.00622255, 0.00611475, 0.00587828, 0.00611499, 0.00547729", \ + "0.0113681, 0.00877845, 0.00815637, 0.00765831, 0.00695947, 0.00683684, 0.00618511", \ + "0.020609, 0.0156721, 0.0141533, 0.0125864, 0.0110744, 0.0094627, 0.00853274" \ ); } fall_power (POWER_7x7ds1) { index_1 ("0.0186, 0.0966, 0.174, 0.3294, 0.6408, 1.263, 2.5074"); index_2 ("0.001, 0.0234, 0.039, 0.0648, 0.108, 0.18, 0.3"); values ( \ - "0.00622321, 0.00622411, 0.00617633, 0.00610921, 0.00597819, 0.0058018, 0.00534654", \ - "0.00594358, 0.00612045, 0.00604746, 0.00607685, 0.00588922, 0.00565071, 0.00529172", \ - "0.00609654, 0.00604346, 0.00608252, 0.00598857, 0.00585913, 0.00559989, 0.00523665", \ - "0.00677587, 0.00644429, 0.00624719, 0.00615538, 0.00600989, 0.0060811, 0.00521386", \ - "0.00861332, 0.00737624, 0.0070555, 0.00673399, 0.0062914, 0.00646079, 0.00534847", \ - "0.0127781, 0.0102832, 0.00943306, 0.00873137, 0.00799254, 0.0069528, 0.00680945", \ - "0.0217825, 0.0176731, 0.0159663, 0.0143029, 0.0125455, 0.0108648, 0.00891828" \ + "0.00621298, 0.00622372, 0.00617567, 0.00611012, 0.0059969, 0.00580175, 0.00534621", \ + "0.0059437, 0.00612017, 0.00604766, 0.00595423, 0.00587652, 0.00560563, 0.00529113", \ + "0.00609401, 0.00604285, 0.0060839, 0.00598927, 0.00585436, 0.00561155, 0.00533043", \ + "0.00678152, 0.00644806, 0.00626162, 0.00615093, 0.00601083, 0.0060817, 0.00518266", \ + "0.00861207, 0.0073766, 0.00706286, 0.00673408, 0.0063193, 0.00645694, 0.00554119", \ + "0.0127782, 0.0102832, 0.00943467, 0.00874155, 0.00806391, 0.00703349, 0.00680842", \ + "0.0217831, 0.0176728, 0.0159661, 0.0143022, 0.0125433, 0.0108672, 0.00891726" \ ); } } @@ -5772,26 +5772,26 @@ library (sg13g2_stdcell_slow_1p35V_125C) { index_1 ("0.0186, 0.0966, 0.174, 0.3294, 0.6408, 1.263, 2.5074"); index_2 ("0.001, 0.0234, 0.039, 0.0648, 0.108, 0.18, 0.3"); values ( \ - "0.00611899, 0.00613812, 0.00609877, 0.00601394, 0.00585652, 0.00558272, 0.00530431", \ - "0.00588104, 0.00603498, 0.00602297, 0.00595728, 0.00584621, 0.00555335, 0.00531256", \ - "0.00588986, 0.00603184, 0.00595825, 0.00590315, 0.00582811, 0.00561214, 0.00530601", \ - "0.00614996, 0.00601115, 0.0060514, 0.0060242, 0.00585994, 0.00560508, 0.00521157", \ - "0.00744572, 0.00667837, 0.00642472, 0.00631689, 0.00603649, 0.00574728, 0.00531313", \ - "0.0113546, 0.00913666, 0.00849951, 0.00790597, 0.00714272, 0.006808, 0.00630345", \ - "0.0201754, 0.0161093, 0.014639, 0.0130821, 0.0114434, 0.00963343, 0.00863263" \ + "0.00611881, 0.00614023, 0.00609907, 0.00602036, 0.00585646, 0.00558307, 0.00529956", \ + "0.0058862, 0.00604263, 0.00600684, 0.00607984, 0.00584355, 0.00558613, 0.0053228", \ + "0.00588715, 0.00598635, 0.00595408, 0.00590849, 0.00582735, 0.00556871, 0.00534333", \ + "0.00615133, 0.00601114, 0.00605545, 0.00595814, 0.005989, 0.00560502, 0.00522534", \ + "0.00744592, 0.00667588, 0.00643336, 0.00631687, 0.00603649, 0.0058723, 0.00540005", \ + "0.0113551, 0.00913562, 0.00850123, 0.00790124, 0.0071496, 0.00680277, 0.00594715", \ + "0.0201687, 0.0161099, 0.0146439, 0.0130797, 0.0114164, 0.00974523, 0.00865242" \ ); } fall_power (POWER_7x7ds1) { index_1 ("0.0186, 0.0966, 0.174, 0.3294, 0.6408, 1.263, 2.5074"); index_2 ("0.001, 0.0234, 0.039, 0.0648, 0.108, 0.18, 0.3"); values ( \ - "0.0081541, 0.00809894, 0.00806782, 0.00798632, 0.00787938, 0.00767206, 0.00727941", \ - "0.00784587, 0.00801225, 0.00791223, 0.00810412, 0.00774861, 0.0075526, 0.00715825", \ - "0.00786439, 0.00790354, 0.00795469, 0.00783666, 0.0077419, 0.00755111, 0.00712451", \ - "0.00824252, 0.00809835, 0.00802118, 0.00796998, 0.00783009, 0.00837514, 0.00710454", \ - "0.00969003, 0.00881238, 0.00865313, 0.00844819, 0.00804851, 0.00807732, 0.00761012", \ - "0.0134793, 0.0112764, 0.0105992, 0.0100787, 0.00952159, 0.00869461, 0.00844108", \ - "0.0218564, 0.0179723, 0.0164267, 0.0149127, 0.013394, 0.0120712, 0.0104945" \ + "0.00815392, 0.00809916, 0.00806485, 0.00798657, 0.00789103, 0.00765661, 0.00727988", \ + "0.00784935, 0.00799662, 0.00791255, 0.00810513, 0.00776262, 0.00752592, 0.00715823", \ + "0.00786335, 0.00790285, 0.0079581, 0.00783801, 0.00774812, 0.00749128, 0.00712646", \ + "0.00825262, 0.00809835, 0.00797129, 0.00797042, 0.00787205, 0.00837528, 0.00710515", \ + "0.00968998, 0.00881493, 0.00865549, 0.00844816, 0.0080485, 0.00822512, 0.00761039", \ + "0.0134797, 0.0112744, 0.0105994, 0.0100802, 0.00951431, 0.00859126, 0.00843943", \ + "0.0218571, 0.017972, 0.0164264, 0.0149101, 0.0133944, 0.0121049, 0.0105149" \ ); } } @@ -5801,26 +5801,26 @@ library (sg13g2_stdcell_slow_1p35V_125C) { index_1 ("0.0186, 0.0966, 0.174, 0.3294, 0.6408, 1.263, 2.5074"); index_2 ("0.001, 0.0234, 0.039, 0.0648, 0.108, 0.18, 0.3"); values ( \ - "0.00611899, 0.00613812, 0.00609877, 0.00601394, 0.00585652, 0.00558272, 0.00530431", \ - "0.00588104, 0.00603498, 0.00602297, 0.00595728, 0.00584621, 0.00555335, 0.00531256", \ - "0.00588986, 0.00603184, 0.00595825, 0.00590315, 0.00582811, 0.00561214, 0.00530601", \ - "0.00614996, 0.00601115, 0.0060514, 0.0060242, 0.00585994, 0.00560508, 0.00521157", \ - "0.00744572, 0.00667837, 0.00642472, 0.00631689, 0.00603649, 0.00574728, 0.00531313", \ - "0.0113546, 0.00913666, 0.00849951, 0.00790597, 0.00714272, 0.006808, 0.00630345", \ - "0.0201754, 0.0161093, 0.014639, 0.0130821, 0.0114434, 0.00963343, 0.00863263" \ + "0.00611881, 0.00614023, 0.00609907, 0.00602036, 0.00585646, 0.00558307, 0.00529956", \ + "0.0058862, 0.00604263, 0.00600684, 0.00607984, 0.00584355, 0.00558613, 0.0053228", \ + "0.00588715, 0.00598635, 0.00595408, 0.00590849, 0.00582735, 0.00556871, 0.00534333", \ + "0.00615133, 0.00601114, 0.00605545, 0.00595814, 0.005989, 0.00560502, 0.00522534", \ + "0.00744592, 0.00667588, 0.00643336, 0.00631687, 0.00603649, 0.0058723, 0.00540005", \ + "0.0113551, 0.00913562, 0.00850123, 0.00790124, 0.0071496, 0.00680277, 0.00594715", \ + "0.0201687, 0.0161099, 0.0146439, 0.0130797, 0.0114164, 0.00974523, 0.00865242" \ ); } fall_power (POWER_7x7ds1) { index_1 ("0.0186, 0.0966, 0.174, 0.3294, 0.6408, 1.263, 2.5074"); index_2 ("0.001, 0.0234, 0.039, 0.0648, 0.108, 0.18, 0.3"); values ( \ - "0.0081541, 0.00809894, 0.00806782, 0.00798632, 0.00787938, 0.00767206, 0.00727941", \ - "0.00784587, 0.00801225, 0.00791223, 0.00810412, 0.00774861, 0.0075526, 0.00715825", \ - "0.00786439, 0.00790354, 0.00795469, 0.00783666, 0.0077419, 0.00755111, 0.00712451", \ - "0.00824252, 0.00809835, 0.00802118, 0.00796998, 0.00783009, 0.00837514, 0.00710454", \ - "0.00969003, 0.00881238, 0.00865313, 0.00844819, 0.00804851, 0.00807732, 0.00761012", \ - "0.0134793, 0.0112764, 0.0105992, 0.0100787, 0.00952159, 0.00869461, 0.00844108", \ - "0.0218564, 0.0179723, 0.0164267, 0.0149127, 0.013394, 0.0120712, 0.0104945" \ + "0.00815392, 0.00809916, 0.00806485, 0.00798657, 0.00789103, 0.00765661, 0.00727988", \ + "0.00784935, 0.00799662, 0.00791255, 0.00810513, 0.00776262, 0.00752592, 0.00715823", \ + "0.00786335, 0.00790285, 0.0079581, 0.00783801, 0.00774812, 0.00749128, 0.00712646", \ + "0.00825262, 0.00809835, 0.00797129, 0.00797042, 0.00787205, 0.00837528, 0.00710515", \ + "0.00968998, 0.00881493, 0.00865549, 0.00844816, 0.0080485, 0.00822512, 0.00761039", \ + "0.0134797, 0.0112744, 0.0105994, 0.0100802, 0.00951431, 0.00859126, 0.00843943", \ + "0.0218571, 0.017972, 0.0164264, 0.0149101, 0.0133944, 0.0121049, 0.0105149" \ ); } } @@ -5831,26 +5831,26 @@ library (sg13g2_stdcell_slow_1p35V_125C) { index_1 ("0.0186, 0.0966, 0.174, 0.3294, 0.6408, 1.263, 2.5074"); index_2 ("0.001, 0.0234, 0.039, 0.0648, 0.108, 0.18, 0.3"); values ( \ - "0.00397024, 0.00406972, 0.00403848, 0.00398349, 0.00380097, 0.00352344, 0.00321945", \ - "0.00378921, 0.00389836, 0.00389552, 0.0039734, 0.00375082, 0.00351737, 0.0032434", \ - "0.00403316, 0.00396701, 0.00392934, 0.0039911, 0.0037298, 0.0035342, 0.00315116", \ - "0.00476502, 0.00421374, 0.00419181, 0.00398975, 0.00379196, 0.00353736, 0.00316447", \ - "0.00663303, 0.00537614, 0.0049641, 0.0046655, 0.0041657, 0.00379778, 0.00333775", \ - "0.0108749, 0.00852692, 0.00771638, 0.00678719, 0.00582236, 0.0050365, 0.0044346", \ - "0.0196993, 0.0159108, 0.0143689, 0.0126349, 0.0107604, 0.00862896, 0.00730249" \ + "0.00396998, 0.00407004, 0.00403584, 0.0039833, 0.00379371, 0.00352557, 0.00321897", \ + "0.00378666, 0.00391482, 0.00404223, 0.00383696, 0.00376415, 0.00351507, 0.0032012", \ + "0.00404037, 0.00398733, 0.00392966, 0.00399133, 0.0037225, 0.00353234, 0.00311317", \ + "0.00476454, 0.00421457, 0.00419246, 0.00395437, 0.00377411, 0.00350822, 0.0031694", \ + "0.00662925, 0.00537707, 0.00497385, 0.00466548, 0.00415027, 0.00386588, 0.00339878", \ + "0.0108748, 0.00852815, 0.00770637, 0.00678717, 0.00582276, 0.00503611, 0.00444281", \ + "0.019699, 0.015911, 0.0143686, 0.0126341, 0.0107716, 0.00864879, 0.00747497" \ ); } fall_power (POWER_7x7ds1) { index_1 ("0.0186, 0.0966, 0.174, 0.3294, 0.6408, 1.263, 2.5074"); index_2 ("0.001, 0.0234, 0.039, 0.0648, 0.108, 0.18, 0.3"); values ( \ - "0.00749842, 0.00776861, 0.00775417, 0.00768125, 0.0075546, 0.00729937, 0.00687792", \ - "0.00713082, 0.00770317, 0.00766347, 0.00776714, 0.00758272, 0.00737929, 0.00691513", \ - "0.00717771, 0.00753437, 0.0076677, 0.00759667, 0.00792358, 0.00733642, 0.00692591", \ - "0.00768064, 0.00763789, 0.00762125, 0.00765081, 0.00758496, 0.00790522, 0.00692295", \ - "0.00931314, 0.00828346, 0.00818963, 0.00804147, 0.00776666, 0.0080584, 0.00735529", \ - "0.0133042, 0.0106676, 0.0100082, 0.00956336, 0.00908696, 0.00834781, 0.00820635", \ - "0.0219398, 0.0172792, 0.015659, 0.0141821, 0.0126808, 0.0115098, 0.0102143" \ + "0.00750413, 0.00776573, 0.00775495, 0.00768237, 0.00754046, 0.00729062, 0.00682564", \ + "0.00712553, 0.00768786, 0.00766576, 0.00787863, 0.00758699, 0.00734951, 0.00691467", \ + "0.0071784, 0.00753348, 0.0076665, 0.00760433, 0.00792371, 0.00730945, 0.00693122", \ + "0.00768007, 0.00763789, 0.00759292, 0.00767394, 0.00769078, 0.00812827, 0.00692233", \ + "0.00931279, 0.00828379, 0.00819036, 0.00802592, 0.00777264, 0.00805746, 0.00737695", \ + "0.0133015, 0.0106647, 0.0100119, 0.00956162, 0.00908289, 0.00832674, 0.00818907", \ + "0.0219403, 0.0172792, 0.0156587, 0.0140985, 0.0126812, 0.0115193, 0.0102155" \ ); } } @@ -5861,26 +5861,26 @@ library (sg13g2_stdcell_slow_1p35V_125C) { index_1 ("0.0186, 0.0966, 0.174, 0.3294, 0.6408, 1.263, 2.5074"); index_2 ("0.001, 0.0234, 0.039, 0.0648, 0.108, 0.18, 0.3"); values ( \ - "0.00368531, 0.00383863, 0.00379993, 0.0037364, 0.00356496, 0.00326974, 0.00297329", \ - "0.00354355, 0.00370178, 0.00371075, 0.00362211, 0.0035321, 0.00326011, 0.0030221", \ - "0.0038379, 0.00372017, 0.00365348, 0.00369254, 0.00353066, 0.00335364, 0.00287839", \ - "0.00465815, 0.00399414, 0.00392704, 0.00374424, 0.00364555, 0.00340114, 0.00296824", \ - "0.00661659, 0.00519744, 0.00477052, 0.00446022, 0.00395356, 0.00426254, 0.00313182", \ - "0.0109928, 0.00839779, 0.00754426, 0.006594, 0.00564499, 0.00485931, 0.00432468", \ - "0.019954, 0.0158707, 0.0142836, 0.012562, 0.0106197, 0.00849739, 0.0072159" \ + "0.00368521, 0.00383844, 0.00379602, 0.0037364, 0.00356756, 0.00327316, 0.00297263", \ + "0.00354744, 0.0037014, 0.00368369, 0.00362632, 0.00354315, 0.00327886, 0.00293754", \ + "0.00384168, 0.00375734, 0.00366634, 0.00359407, 0.00354854, 0.00335395, 0.00300663", \ + "0.00465806, 0.00399411, 0.00395901, 0.00371153, 0.00364565, 0.00326664, 0.00296905", \ + "0.00661563, 0.00520416, 0.00476731, 0.00446014, 0.00395497, 0.00426254, 0.00313684", \ + "0.0109927, 0.00839582, 0.00754566, 0.00657734, 0.00564527, 0.00484246, 0.00445259", \ + "0.0199544, 0.0158676, 0.0142837, 0.0125622, 0.0106187, 0.00848631, 0.00716191" \ ); } fall_power (POWER_7x7ds1) { index_1 ("0.0186, 0.0966, 0.174, 0.3294, 0.6408, 1.263, 2.5074"); index_2 ("0.001, 0.0234, 0.039, 0.0648, 0.108, 0.18, 0.3"); values ( \ - "0.00547197, 0.00577345, 0.00575222, 0.00567266, 0.005543, 0.00531555, 0.00488649", \ - "0.00509816, 0.00568039, 0.00569726, 0.00576757, 0.00555965, 0.00543067, 0.00497197", \ - "0.00516336, 0.00554021, 0.00565141, 0.00562852, 0.00579819, 0.00537804, 0.00495911", \ - "0.00568404, 0.00564275, 0.00560732, 0.00566152, 0.00566487, 0.00592149, 0.0049508", \ - "0.00733815, 0.00629625, 0.00618862, 0.00603751, 0.00577989, 0.00595321, 0.00566739", \ - "0.0114045, 0.00874532, 0.00810871, 0.00758213, 0.00713938, 0.00626343, 0.00623159", \ - "0.0201271, 0.0153018, 0.0137574, 0.012304, 0.0107399, 0.0097291, 0.0081968" \ + "0.00547304, 0.00577253, 0.00575075, 0.0056732, 0.00559019, 0.00531392, 0.00488699", \ + "0.00510637, 0.00568036, 0.00568404, 0.00577995, 0.00554835, 0.00541026, 0.00495929", \ + "0.0051616, 0.00554045, 0.00565069, 0.00562849, 0.00570061, 0.00535618, 0.0049593", \ + "0.00568417, 0.00564281, 0.00560714, 0.00566198, 0.0057407, 0.00592899, 0.00493598", \ + "0.00733888, 0.00629474, 0.00619057, 0.00603282, 0.00579955, 0.00599507, 0.0056475", \ + "0.0114043, 0.00874544, 0.00810889, 0.00758229, 0.00713931, 0.00631537, 0.00617338", \ + "0.0201024, 0.015303, 0.0137574, 0.0123047, 0.0107366, 0.00973116, 0.00816902" \ ); } } @@ -5890,26 +5890,26 @@ library (sg13g2_stdcell_slow_1p35V_125C) { index_1 ("0.0186, 0.0966, 0.174, 0.3294, 0.6408, 1.263, 2.5074"); index_2 ("0.001, 0.0234, 0.039, 0.0648, 0.108, 0.18, 0.3"); values ( \ - "0.00397024, 0.00406972, 0.00403848, 0.00398349, 0.00380097, 0.00352344, 0.00321945", \ - "0.00378921, 0.00389836, 0.00389552, 0.0039734, 0.00375082, 0.00351737, 0.0032434", \ - "0.00403316, 0.00396701, 0.00392934, 0.0039911, 0.0037298, 0.0035342, 0.00315116", \ - "0.00476502, 0.00421374, 0.00419181, 0.00398975, 0.00379196, 0.00353736, 0.00316447", \ - "0.00663303, 0.00537614, 0.0049641, 0.0046655, 0.0041657, 0.00379778, 0.00333775", \ - "0.0108749, 0.00852692, 0.00771638, 0.00678719, 0.00582236, 0.0050365, 0.0044346", \ - "0.0196993, 0.0159108, 0.0143689, 0.0126349, 0.0107604, 0.00862896, 0.00730249" \ + "0.00396998, 0.00407004, 0.00403584, 0.0039833, 0.00379371, 0.00352557, 0.00321897", \ + "0.00378666, 0.00391482, 0.00404223, 0.00383696, 0.00376415, 0.00351507, 0.0032012", \ + "0.00404037, 0.00398733, 0.00392966, 0.00399133, 0.0037225, 0.00353234, 0.00311317", \ + "0.00476454, 0.00421457, 0.00419246, 0.00395437, 0.00377411, 0.00350822, 0.0031694", \ + "0.00662925, 0.00537707, 0.00497385, 0.00466548, 0.00415027, 0.00386588, 0.00339878", \ + "0.0108748, 0.00852815, 0.00770637, 0.00678717, 0.00582276, 0.00503611, 0.00444281", \ + "0.019699, 0.015911, 0.0143686, 0.0126341, 0.0107716, 0.00864879, 0.00747497" \ ); } fall_power (POWER_7x7ds1) { index_1 ("0.0186, 0.0966, 0.174, 0.3294, 0.6408, 1.263, 2.5074"); index_2 ("0.001, 0.0234, 0.039, 0.0648, 0.108, 0.18, 0.3"); values ( \ - "0.00749842, 0.00776861, 0.00775417, 0.00768125, 0.0075546, 0.00729937, 0.00687792", \ - "0.00713082, 0.00770317, 0.00766347, 0.00776714, 0.00758272, 0.00737929, 0.00691513", \ - "0.00717771, 0.00753437, 0.0076677, 0.00759667, 0.00792358, 0.00733642, 0.00692591", \ - "0.00768064, 0.00763789, 0.00762125, 0.00765081, 0.00758496, 0.00790522, 0.00692295", \ - "0.00931314, 0.00828346, 0.00818963, 0.00804147, 0.00776666, 0.0080584, 0.00735529", \ - "0.0133042, 0.0106676, 0.0100082, 0.00956336, 0.00908696, 0.00834781, 0.00820635", \ - "0.0219398, 0.0172792, 0.015659, 0.0141821, 0.0126808, 0.0115098, 0.0102143" \ + "0.00750413, 0.00776573, 0.00775495, 0.00768237, 0.00754046, 0.00729062, 0.00682564", \ + "0.00712553, 0.00768786, 0.00766576, 0.00787863, 0.00758699, 0.00734951, 0.00691467", \ + "0.0071784, 0.00753348, 0.0076665, 0.00760433, 0.00792371, 0.00730945, 0.00693122", \ + "0.00768007, 0.00763789, 0.00759292, 0.00767394, 0.00769078, 0.00812827, 0.00692233", \ + "0.00931279, 0.00828379, 0.00819036, 0.00802592, 0.00777264, 0.00805746, 0.00737695", \ + "0.0133015, 0.0106647, 0.0100119, 0.00956162, 0.00908289, 0.00832674, 0.00818907", \ + "0.0219403, 0.0172792, 0.0156587, 0.0140985, 0.0126812, 0.0115193, 0.0102155" \ ); } } @@ -5920,26 +5920,26 @@ library (sg13g2_stdcell_slow_1p35V_125C) { index_1 ("0.0186, 0.0966, 0.174, 0.3294, 0.6408, 1.263, 2.5074"); index_2 ("0.001, 0.0234, 0.039, 0.0648, 0.108, 0.18, 0.3"); values ( \ - "0.00366095, 0.0039959, 0.00397322, 0.00393732, 0.0037492, 0.00350464, 0.00317464", \ - "0.00341838, 0.00375941, 0.00379775, 0.00377041, 0.00371606, 0.00348382, 0.00322786", \ - "0.00367047, 0.00375657, 0.00370116, 0.00381326, 0.003679, 0.0034846, 0.00315197", \ - "0.00445925, 0.00390095, 0.00389877, 0.00376583, 0.00373143, 0.00345787, 0.00309244", \ - "0.00633898, 0.00501132, 0.00465161, 0.00437915, 0.00395817, 0.00435053, 0.00329821", \ - "0.010744, 0.00808516, 0.00728272, 0.00641971, 0.00552979, 0.00481885, 0.00452308", \ - "0.0199146, 0.0153345, 0.0136933, 0.0122167, 0.0102557, 0.00816418, 0.00709474" \ + "0.0036608, 0.00399604, 0.00396715, 0.00393709, 0.00375591, 0.00350412, 0.00320159", \ + "0.00341496, 0.00375932, 0.00383446, 0.0037553, 0.0037013, 0.00348373, 0.00323269", \ + "0.00367154, 0.00375657, 0.0037114, 0.00381324, 0.00368659, 0.0034846, 0.00318891", \ + "0.00445925, 0.00390081, 0.00389743, 0.00376025, 0.00373846, 0.00343196, 0.0031977", \ + "0.00633811, 0.00501142, 0.00465171, 0.00438245, 0.00395309, 0.00363421, 0.00329572", \ + "0.0107437, 0.00808563, 0.00728417, 0.00641231, 0.00552966, 0.00481898, 0.00452265", \ + "0.0199143, 0.0153347, 0.0136933, 0.0122168, 0.0102535, 0.00816431, 0.00709563" \ ); } fall_power (POWER_7x7ds1) { index_1 ("0.0186, 0.0966, 0.174, 0.3294, 0.6408, 1.263, 2.5074"); index_2 ("0.001, 0.0234, 0.039, 0.0648, 0.108, 0.18, 0.3"); values ( \ - "0.00546779, 0.00584423, 0.00583319, 0.00577002, 0.00565809, 0.00539188, 0.00497341", \ - "0.00528151, 0.00574683, 0.00575053, 0.00574731, 0.00566577, 0.00546461, 0.00501686", \ - "0.00552118, 0.00565541, 0.00578408, 0.00572106, 0.00567053, 0.00538822, 0.00500646", \ - "0.0063117, 0.00600685, 0.0058744, 0.00584904, 0.00572268, 0.00577376, 0.00502851", \ - "0.00825874, 0.00685767, 0.00661476, 0.00639402, 0.00600707, 0.00607615, 0.00601542", \ - "0.0126743, 0.00982418, 0.00882702, 0.00820517, 0.00756733, 0.00668804, 0.00652317", \ - "0.0217655, 0.016831, 0.0150958, 0.0134636, 0.0118077, 0.0102966, 0.00852711" \ + "0.00546554, 0.00584237, 0.00582521, 0.00577033, 0.00565739, 0.00539235, 0.00497222", \ + "0.00528413, 0.00574732, 0.00574885, 0.00575452, 0.00566183, 0.00545651, 0.00501845", \ + "0.00552243, 0.00564891, 0.00578469, 0.00571958, 0.00565504, 0.0054308, 0.00500734", \ + "0.00631142, 0.00600672, 0.00587443, 0.00584883, 0.00579903, 0.00577376, 0.00504423", \ + "0.00826, 0.0068607, 0.00659496, 0.00639865, 0.00600701, 0.00620992, 0.00600359", \ + "0.0126741, 0.00982373, 0.00882749, 0.0082057, 0.00755559, 0.00676575, 0.00652976", \ + "0.0217655, 0.0168315, 0.0150937, 0.0134639, 0.0118012, 0.0103123, 0.00855269" \ ); } } @@ -5950,26 +5950,26 @@ library (sg13g2_stdcell_slow_1p35V_125C) { index_1 ("0.0186, 0.0966, 0.174, 0.3294, 0.6408, 1.263, 2.5074"); index_2 ("0.001, 0.0234, 0.039, 0.0648, 0.108, 0.18, 0.3"); values ( \ - "0.00329222, 0.00377043, 0.00374416, 0.003698, 0.00352906, 0.00325014, 0.00293811", \ - "0.00314384, 0.00350098, 0.00355653, 0.00355908, 0.00348586, 0.00325396, 0.00299886", \ - "0.00348744, 0.00346086, 0.00346348, 0.00353895, 0.0034018, 0.00326109, 0.00295406", \ - "0.00433211, 0.00368462, 0.00367124, 0.00354531, 0.00358507, 0.00320776, 0.0028702", \ - "0.00639279, 0.00486541, 0.00443664, 0.00415721, 0.00372755, 0.00398815, 0.00317275", \ - "0.0109336, 0.00793872, 0.00713989, 0.0062024, 0.00530687, 0.00501846, 0.00427565", \ - "0.0203127, 0.0153692, 0.0136351, 0.0120123, 0.0100717, 0.00813361, 0.00686269" \ + "0.00328651, 0.00377041, 0.00374824, 0.00369237, 0.00352931, 0.00325022, 0.00291733", \ + "0.00314399, 0.00350612, 0.00358898, 0.00353828, 0.00348512, 0.00325375, 0.00299825", \ + "0.0034875, 0.0034618, 0.00347204, 0.00353881, 0.00340213, 0.00325386, 0.00295445", \ + "0.00433212, 0.00368454, 0.00367415, 0.00352853, 0.0034117, 0.00319602, 0.00292294", \ + "0.00639122, 0.00486354, 0.00444258, 0.00416305, 0.00373218, 0.00410062, 0.00306088", \ + "0.0109325, 0.00793978, 0.00714043, 0.00621791, 0.00530667, 0.00499425, 0.0041929", \ + "0.0203111, 0.015369, 0.0136356, 0.0120116, 0.0100369, 0.008014, 0.0068525" \ ); } fall_power (POWER_7x7ds1) { index_1 ("0.0186, 0.0966, 0.174, 0.3294, 0.6408, 1.263, 2.5074"); index_2 ("0.001, 0.0234, 0.039, 0.0648, 0.108, 0.18, 0.3"); values ( \ - "0.00344801, 0.00385568, 0.00382538, 0.00376449, 0.00363464, 0.00344479, 0.00300084", \ - "0.00326779, 0.00374443, 0.00377505, 0.00374023, 0.00365233, 0.00345623, 0.00301409", \ - "0.00350975, 0.00368091, 0.00377114, 0.00372604, 0.00375329, 0.00352796, 0.00306974", \ - "0.00433192, 0.00400384, 0.00387226, 0.00384313, 0.00374083, 0.00382384, 0.00305228", \ - "0.00631143, 0.00485358, 0.00463645, 0.00439593, 0.0040265, 0.00420331, 0.00349588", \ - "0.0107774, 0.00786081, 0.00684931, 0.00619926, 0.00550535, 0.00479738, 0.00443373", \ - "0.0199729, 0.0148432, 0.0131569, 0.0115455, 0.00980306, 0.00838221, 0.00656329" \ + "0.00344685, 0.00384643, 0.00382826, 0.00376515, 0.00368925, 0.00341495, 0.00300109", \ + "0.00326659, 0.00376713, 0.00378295, 0.00380264, 0.00364125, 0.00349975, 0.00301341", \ + "0.00351217, 0.00366448, 0.00377116, 0.00372455, 0.0037543, 0.00349245, 0.00307031", \ + "0.0043322, 0.00400408, 0.00387246, 0.00384325, 0.00375465, 0.00379479, 0.00307945", \ + "0.00631176, 0.0048536, 0.00463537, 0.00439225, 0.00400234, 0.00419627, 0.00378828", \ + "0.0107772, 0.0078596, 0.00684887, 0.00619622, 0.00560595, 0.0047971, 0.00443238", \ + "0.019973, 0.0148422, 0.0131566, 0.011545, 0.00980274, 0.0083831, 0.0065723" \ ); } } @@ -5979,26 +5979,26 @@ library (sg13g2_stdcell_slow_1p35V_125C) { index_1 ("0.0186, 0.0966, 0.174, 0.3294, 0.6408, 1.263, 2.5074"); index_2 ("0.001, 0.0234, 0.039, 0.0648, 0.108, 0.18, 0.3"); values ( \ - "0.00366095, 0.0039959, 0.00397322, 0.00393732, 0.0037492, 0.00350464, 0.00317464", \ - "0.00341838, 0.00375941, 0.00379775, 0.00377041, 0.00371606, 0.00348382, 0.00322786", \ - "0.00367047, 0.00375657, 0.00370116, 0.00381326, 0.003679, 0.0034846, 0.00315197", \ - "0.00445925, 0.00390095, 0.00389877, 0.00376583, 0.00373143, 0.00345787, 0.00309244", \ - "0.00633898, 0.00501132, 0.00465161, 0.00437915, 0.00395817, 0.00435053, 0.00329821", \ - "0.010744, 0.00808516, 0.00728272, 0.00641971, 0.00552979, 0.00481885, 0.00452308", \ - "0.0199146, 0.0153345, 0.0136933, 0.0122167, 0.0102557, 0.00816418, 0.00709474" \ + "0.0036608, 0.00399604, 0.00396715, 0.00393709, 0.00375591, 0.00350412, 0.00320159", \ + "0.00341496, 0.00375932, 0.00383446, 0.0037553, 0.0037013, 0.00348373, 0.00323269", \ + "0.00367154, 0.00375657, 0.0037114, 0.00381324, 0.00368659, 0.0034846, 0.00318891", \ + "0.00445925, 0.00390081, 0.00389743, 0.00376025, 0.00373846, 0.00343196, 0.0031977", \ + "0.00633811, 0.00501142, 0.00465171, 0.00438245, 0.00395309, 0.00363421, 0.00329572", \ + "0.0107437, 0.00808563, 0.00728417, 0.00641231, 0.00552966, 0.00481898, 0.00452265", \ + "0.0199143, 0.0153347, 0.0136933, 0.0122168, 0.0102535, 0.00816431, 0.00709563" \ ); } fall_power (POWER_7x7ds1) { index_1 ("0.0186, 0.0966, 0.174, 0.3294, 0.6408, 1.263, 2.5074"); index_2 ("0.001, 0.0234, 0.039, 0.0648, 0.108, 0.18, 0.3"); values ( \ - "0.00546779, 0.00584423, 0.00583319, 0.00577002, 0.00565809, 0.00539188, 0.00497341", \ - "0.00528151, 0.00574683, 0.00575053, 0.00574731, 0.00566577, 0.00546461, 0.00501686", \ - "0.00552118, 0.00565541, 0.00578408, 0.00572106, 0.00567053, 0.00538822, 0.00500646", \ - "0.0063117, 0.00600685, 0.0058744, 0.00584904, 0.00572268, 0.00577376, 0.00502851", \ - "0.00825874, 0.00685767, 0.00661476, 0.00639402, 0.00600707, 0.00607615, 0.00601542", \ - "0.0126743, 0.00982418, 0.00882702, 0.00820517, 0.00756733, 0.00668804, 0.00652317", \ - "0.0217655, 0.016831, 0.0150958, 0.0134636, 0.0118077, 0.0102966, 0.00852711" \ + "0.00546554, 0.00584237, 0.00582521, 0.00577033, 0.00565739, 0.00539235, 0.00497222", \ + "0.00528413, 0.00574732, 0.00574885, 0.00575452, 0.00566183, 0.00545651, 0.00501845", \ + "0.00552243, 0.00564891, 0.00578469, 0.00571958, 0.00565504, 0.0054308, 0.00500734", \ + "0.00631142, 0.00600672, 0.00587443, 0.00584883, 0.00579903, 0.00577376, 0.00504423", \ + "0.00826, 0.0068607, 0.00659496, 0.00639865, 0.00600701, 0.00620992, 0.00600359", \ + "0.0126741, 0.00982373, 0.00882749, 0.0082057, 0.00755559, 0.00676575, 0.00652976", \ + "0.0217655, 0.0168315, 0.0150937, 0.0134639, 0.0118012, 0.0103123, 0.00855269" \ ); } } @@ -6006,43 +6006,43 @@ library (sg13g2_stdcell_slow_1p35V_125C) { pin (A1) { direction : "input"; max_transition : 2.5074; - capacitance : 0.00304818; - rise_capacitance : 0.00300076; - rise_capacitance_range (0.00300076, 0.00300076); + capacitance : 0.00304816; + rise_capacitance : 0.00300073; + rise_capacitance_range (0.0028002, 0.00328447); fall_capacitance : 0.0030956; - fall_capacitance_range (0.0030956, 0.0030956); + fall_capacitance_range (0.00270719, 0.00346205); } pin (A2) { direction : "input"; max_transition : 2.5074; - capacitance : 0.0030642; - rise_capacitance : 0.00311863; - rise_capacitance_range (0.00311863, 0.00311863); - fall_capacitance : 0.00300976; - fall_capacitance_range (0.00300976, 0.00300976); + capacitance : 0.00306399; + rise_capacitance : 0.00311848; + rise_capacitance_range (0.00269571, 0.00344096); + fall_capacitance : 0.0030095; + fall_capacitance_range (0.00270022, 0.00331172); } pin (B1) { direction : "input"; max_transition : 2.5074; - capacitance : 0.00299089; - rise_capacitance : 0.00315284; - rise_capacitance_range (0.00315284, 0.00315284); - fall_capacitance : 0.00282894; - fall_capacitance_range (0.00282894, 0.00282894); + capacitance : 0.00299093; + rise_capacitance : 0.00315282; + rise_capacitance_range (0.00257053, 0.00361973); + fall_capacitance : 0.00282904; + fall_capacitance_range (0.0026372, 0.00304401); } pin (B2) { direction : "input"; max_transition : 2.5074; - capacitance : 0.00294615; + capacitance : 0.00294614; rise_capacitance : 0.00300962; - rise_capacitance_range (0.00300962, 0.00300962); + rise_capacitance_range (0.00254029, 0.00350567); fall_capacitance : 0.00288267; - fall_capacitance_range (0.00288267, 0.00288267); + fall_capacitance_range (0.00254511, 0.00318881); } } cell (sg13g2_and2_1) { area : 9.072; - cell_footprint : "AND2"; + cell_footprint : "and2"; cell_leakage_power : 1010.75; leakage_power () { value : 1352.74; @@ -6243,23 +6243,23 @@ library (sg13g2_stdcell_slow_1p35V_125C) { max_transition : 2.5074; capacitance : 0.00251391; rise_capacitance : 0.00251369; - rise_capacitance_range (0.00251369, 0.00251369); + rise_capacitance_range (0.0022442, 0.00272356); fall_capacitance : 0.00251413; - fall_capacitance_range (0.00251413, 0.00251413); + fall_capacitance_range (0.00222785, 0.00272943); } pin (B) { direction : "input"; max_transition : 2.5074; capacitance : 0.00251994; rise_capacitance : 0.00259434; - rise_capacitance_range (0.00259434, 0.00259434); + rise_capacitance_range (0.0022052, 0.00285879); fall_capacitance : 0.00244554; - fall_capacitance_range (0.00244554, 0.00244554); + fall_capacitance_range (0.00227039, 0.00259336); } } cell (sg13g2_and2_2) { area : 10.8864; - cell_footprint : "AND2"; + cell_footprint : "and2"; cell_leakage_power : 1632.72; leakage_power () { value : 1558.32; @@ -6460,23 +6460,23 @@ library (sg13g2_stdcell_slow_1p35V_125C) { max_transition : 2.5074; capacitance : 0.00250504; rise_capacitance : 0.00250592; - rise_capacitance_range (0.00250592, 0.00250592); + rise_capacitance_range (0.00229243, 0.0026898); fall_capacitance : 0.00250417; - fall_capacitance_range (0.00250417, 0.00250417); + fall_capacitance_range (0.00227836, 0.00268875); } pin (B) { direction : "input"; max_transition : 2.5074; capacitance : 0.00253225; rise_capacitance : 0.00260845; - rise_capacitance_range (0.00260845, 0.00260845); + rise_capacitance_range (0.00224705, 0.00285472); fall_capacitance : 0.00245606; - fall_capacitance_range (0.00245606, 0.00245606); + fall_capacitance_range (0.00230932, 0.00258912); } } cell (sg13g2_and3_1) { area : 12.7008; - cell_footprint : "AND3"; + cell_footprint : "and3"; cell_leakage_power : 1009.27; leakage_power () { value : 1926.2; @@ -6779,32 +6779,32 @@ library (sg13g2_stdcell_slow_1p35V_125C) { max_transition : 2.5074; capacitance : 0.00250263; rise_capacitance : 0.00248285; - rise_capacitance_range (0.00248285, 0.00248285); + rise_capacitance_range (0.00224899, 0.00265438); fall_capacitance : 0.0025224; - fall_capacitance_range (0.0025224, 0.0025224); + fall_capacitance_range (0.00220817, 0.00277738); } pin (B) { direction : "input"; max_transition : 2.5074; capacitance : 0.00249193; rise_capacitance : 0.00254225; - rise_capacitance_range (0.00254225, 0.00254225); + rise_capacitance_range (0.00217213, 0.0027918); fall_capacitance : 0.00244161; - fall_capacitance_range (0.00244161, 0.00244161); + fall_capacitance_range (0.00220563, 0.00263563); } pin (C) { direction : "input"; max_transition : 2.5074; capacitance : 0.00250647; rise_capacitance : 0.00258184; - rise_capacitance_range (0.00258184, 0.00258184); + rise_capacitance_range (0.00221051, 0.00285955); fall_capacitance : 0.0024311; - fall_capacitance_range (0.0024311, 0.0024311); + fall_capacitance_range (0.00227833, 0.00257201); } } cell (sg13g2_and3_2) { area : 12.7008; - cell_footprint : "AND3"; + cell_footprint : "and3"; cell_leakage_power : 1700.65; leakage_power () { value : 2131.77; @@ -7107,32 +7107,32 @@ library (sg13g2_stdcell_slow_1p35V_125C) { max_transition : 2.5074; capacitance : 0.00251767; rise_capacitance : 0.00250144; - rise_capacitance_range (0.00250144, 0.00250144); + rise_capacitance_range (0.00230839, 0.00265549); fall_capacitance : 0.0025339; - fall_capacitance_range (0.0025339, 0.0025339); + fall_capacitance_range (0.00228381, 0.00275627); } pin (B) { direction : "input"; max_transition : 2.5074; capacitance : 0.00249838; rise_capacitance : 0.00255308; - rise_capacitance_range (0.00255308, 0.00255308); + rise_capacitance_range (0.002202, 0.00279307); fall_capacitance : 0.00244368; - fall_capacitance_range (0.00244368, 0.00244368); + fall_capacitance_range (0.00224335, 0.00261531); } pin (C) { direction : "input"; max_transition : 2.5074; capacitance : 0.00250877; rise_capacitance : 0.00258712; - rise_capacitance_range (0.00258712, 0.00258712); + rise_capacitance_range (0.00223352, 0.00285177); fall_capacitance : 0.00243042; - fall_capacitance_range (0.00243042, 0.00243042); + fall_capacitance_range (0.00229753, 0.00255936); } } cell (sg13g2_and4_1) { area : 14.5152; - cell_footprint : "AND4"; + cell_footprint : "and4"; cell_leakage_power : 969.96; leakage_power () { value : 829.588; @@ -7553,41 +7553,41 @@ library (sg13g2_stdcell_slow_1p35V_125C) { max_transition : 2.5074; capacitance : 0.00233654; rise_capacitance : 0.00230224; - rise_capacitance_range (0.00230224, 0.00230224); + rise_capacitance_range (0.002089, 0.00244934); fall_capacitance : 0.00237083; - fall_capacitance_range (0.00237083, 0.00237083); + fall_capacitance_range (0.00204491, 0.00266235); } pin (B) { direction : "input"; max_transition : 2.5074; capacitance : 0.00247269; rise_capacitance : 0.00250574; - rise_capacitance_range (0.00250574, 0.00250574); + rise_capacitance_range (0.00214947, 0.00274235); fall_capacitance : 0.00243963; - fall_capacitance_range (0.00243963, 0.00243963); + fall_capacitance_range (0.00216807, 0.00267351); } pin (C) { direction : "input"; max_transition : 2.5074; capacitance : 0.00246842; rise_capacitance : 0.00252154; - rise_capacitance_range (0.00252154, 0.00252154); + rise_capacitance_range (0.00215795, 0.00278871); fall_capacitance : 0.00241529; - fall_capacitance_range (0.00241529, 0.00241529); + fall_capacitance_range (0.00220582, 0.00259571); } pin (D) { direction : "input"; max_transition : 2.5074; capacitance : 0.00248219; rise_capacitance : 0.00255668; - rise_capacitance_range (0.00255668, 0.00255668); + rise_capacitance_range (0.00219791, 0.00284731); fall_capacitance : 0.00240771; - fall_capacitance_range (0.00240771, 0.00240771); + fall_capacitance_range (0.00227124, 0.00254431); } } cell (sg13g2_and4_2) { area : 16.3296; - cell_footprint : "AND4"; + cell_footprint : "and4"; cell_leakage_power : 1696.02; leakage_power () { value : 1590.35; @@ -8008,41 +8008,41 @@ library (sg13g2_stdcell_slow_1p35V_125C) { max_transition : 2.5074; capacitance : 0.0023354; rise_capacitance : 0.00230809; - rise_capacitance_range (0.00230809, 0.00230809); + rise_capacitance_range (0.00213273, 0.00244122); fall_capacitance : 0.00236271; - fall_capacitance_range (0.00236271, 0.00236271); + fall_capacitance_range (0.00210416, 0.00261164); } pin (B) { direction : "input"; max_transition : 2.5074; capacitance : 0.00246537; rise_capacitance : 0.00250431; - rise_capacitance_range (0.00250431, 0.00250431); + rise_capacitance_range (0.00216625, 0.00273323); fall_capacitance : 0.00242643; - fall_capacitance_range (0.00242643, 0.00242643); + fall_capacitance_range (0.00219652, 0.00263467); } pin (C) { direction : "input"; max_transition : 2.5074; capacitance : 0.00246539; rise_capacitance : 0.00252284; - rise_capacitance_range (0.00252284, 0.00252284); + rise_capacitance_range (0.0021765, 0.00278109); fall_capacitance : 0.00240793; - fall_capacitance_range (0.00240793, 0.00240793); + fall_capacitance_range (0.00222205, 0.00257811); } pin (D) { direction : "input"; max_transition : 2.5074; capacitance : 0.00247738; rise_capacitance : 0.00255536; - rise_capacitance_range (0.00255536, 0.00255536); + rise_capacitance_range (0.00221293, 0.00283324); fall_capacitance : 0.00239939; - fall_capacitance_range (0.00239939, 0.00239939); + fall_capacitance_range (0.00227701, 0.00252498); } } cell (sg13g2_antennanp) { area : 5.4432; - cell_footprint : "NP_ant"; + cell_footprint : "antennanp"; cell_leakage_power : 5.55024; dont_touch : true; dont_use : true; @@ -8059,9 +8059,9 @@ library (sg13g2_stdcell_slow_1p35V_125C) { max_transition : 2.5074; capacitance : 0.00110438; rise_capacitance : 0.00106045; - rise_capacitance_range (0.00106045, 0.00106045); + rise_capacitance_range (0.000256365, 0.00171399); fall_capacitance : 0.00114831; - fall_capacitance_range (0.00114831, 0.00114831); + fall_capacitance_range (0.000257235, 0.00184881); internal_power () { rise_power (passive_POWER_7x1ds1) { index_1 ("0.0186, 0.0966, 0.174, 0.3294, 0.6408, 1.263, 2.5074"); @@ -8080,7 +8080,7 @@ library (sg13g2_stdcell_slow_1p35V_125C) { } cell (sg13g2_buf_1) { area : 7.2576; - cell_footprint : "BU"; + cell_footprint : "buf"; cell_leakage_power : 837.685; leakage_power () { value : 899.765; @@ -8187,14 +8187,14 @@ library (sg13g2_stdcell_slow_1p35V_125C) { max_transition : 2.5074; capacitance : 0.00224013; rise_capacitance : 0.00227519; - rise_capacitance_range (0.00227519, 0.00227519); + rise_capacitance_range (0.00202103, 0.00247639); fall_capacitance : 0.00220507; - fall_capacitance_range (0.00220507, 0.00220507); + fall_capacitance_range (0.00200158, 0.00238857); } } cell (sg13g2_buf_16) { area : 45.36; - cell_footprint : "BU"; + cell_footprint : "buf"; cell_leakage_power : 10631.1; leakage_power () { value : 7855.69; @@ -8301,14 +8301,14 @@ library (sg13g2_stdcell_slow_1p35V_125C) { max_transition : 2.5074; capacitance : 0.0168355; rise_capacitance : 0.0171634; - rise_capacitance_range (0.0171634, 0.0171634); + rise_capacitance_range (0.0153768, 0.0187179); fall_capacitance : 0.0165076; - fall_capacitance_range (0.0165076, 0.0165076); + fall_capacitance_range (0.0151209, 0.0177196); } } cell (sg13g2_buf_2) { area : 9.072; - cell_footprint : "BU"; + cell_footprint : "buf"; cell_leakage_power : 1391.03; leakage_power () { value : 1691.89; @@ -8415,14 +8415,14 @@ library (sg13g2_stdcell_slow_1p35V_125C) { max_transition : 2.5074; capacitance : 0.00258756; rise_capacitance : 0.00263586; - rise_capacitance_range (0.00263586, 0.00263586); + rise_capacitance_range (0.00238705, 0.00285253); fall_capacitance : 0.00253927; - fall_capacitance_range (0.00253927, 0.00253927); + fall_capacitance_range (0.00233971, 0.00272903); } } cell (sg13g2_buf_4) { area : 14.5152; - cell_footprint : "BU"; + cell_footprint : "buf"; cell_leakage_power : 2605.01; leakage_power () { value : 1952.91; @@ -8529,14 +8529,14 @@ library (sg13g2_stdcell_slow_1p35V_125C) { max_transition : 2.5074; capacitance : 0.003649; rise_capacitance : 0.00378551; - rise_capacitance_range (0.00378551, 0.00378551); + rise_capacitance_range (0.00349787, 0.00400297); fall_capacitance : 0.00351248; - fall_capacitance_range (0.00351248, 0.00351248); + fall_capacitance_range (0.00321403, 0.00386788); } } cell (sg13g2_buf_8) { area : 23.5872; - cell_footprint : "BU"; + cell_footprint : "buf"; cell_leakage_power : 5315.64; leakage_power () { value : 3927.85; @@ -8643,14 +8643,14 @@ library (sg13g2_stdcell_slow_1p35V_125C) { max_transition : 2.5074; capacitance : 0.00845659; rise_capacitance : 0.00861956; - rise_capacitance_range (0.00861956, 0.00861956); + rise_capacitance_range (0.00777547, 0.00938412); fall_capacitance : 0.00829363; - fall_capacitance_range (0.00829363, 0.00829363); + fall_capacitance_range (0.00764476, 0.00888996); } } cell (sg13g2_decap_4) { area : 7.2576; - cell_footprint : "DECAP"; + cell_footprint : "decap"; cell_leakage_power : 425.4; dont_touch : true; dont_use : true; @@ -8658,7 +8658,7 @@ library (sg13g2_stdcell_slow_1p35V_125C) { } cell (sg13g2_decap_8) { area : 12.7008; - cell_footprint : "DECAP"; + cell_footprint : "decap"; cell_leakage_power : 850.824; dont_touch : true; dont_use : true; @@ -8666,7 +8666,7 @@ library (sg13g2_stdcell_slow_1p35V_125C) { } cell (sg13g2_dfrbp_1) { area : 52.6176; - cell_footprint : "dffrr"; + cell_footprint : "dfrbp"; cell_leakage_power : 4168.37; leakage_power () { value : 3647.61; @@ -8723,6 +8723,7 @@ library (sg13g2_stdcell_slow_1p35V_125C) { max_capacitance : 0.3; timing () { related_pin : "CLK"; + sdf_edges : start_edge; timing_sense : non_unate; timing_type : rising_edge; cell_rise (TIMING_DELAY_7x7ds1) { @@ -8780,6 +8781,7 @@ library (sg13g2_stdcell_slow_1p35V_125C) { } timing () { related_pin : "RESET_B"; + sdf_edges : start_edge; timing_sense : positive_unate; timing_type : clear; cell_fall (TIMING_DELAY_7x7ds1) { @@ -8867,6 +8869,7 @@ library (sg13g2_stdcell_slow_1p35V_125C) { max_capacitance : 0.3; timing () { related_pin : "CLK"; + sdf_edges : start_edge; timing_sense : non_unate; timing_type : rising_edge; cell_rise (TIMING_DELAY_7x7ds1) { @@ -8924,6 +8927,7 @@ library (sg13g2_stdcell_slow_1p35V_125C) { } timing () { related_pin : "RESET_B"; + sdf_edges : start_edge; timing_sense : negative_unate; timing_type : preset; cell_rise (TIMING_DELAY_7x7ds1) { @@ -9010,9 +9014,9 @@ library (sg13g2_stdcell_slow_1p35V_125C) { max_transition : 2.5074; capacitance : 0.00276883; rise_capacitance : 0.00294361; - rise_capacitance_range (0.00294361, 0.00294361); + rise_capacitance_range (0.00264499, 0.00320945); fall_capacitance : 0.00250665; - fall_capacitance_range (0.00250665, 0.00250665); + fall_capacitance_range (0.00250665, 0.00303903); timing () { related_pin : "CLK"; timing_type : min_pulse_width; @@ -9138,11 +9142,12 @@ library (sg13g2_stdcell_slow_1p35V_125C) { max_transition : 2.5074; capacitance : 0.00152757; rise_capacitance : 0.00139848; - rise_capacitance_range (0.00139848, 0.00139848); + rise_capacitance_range (0.00129661, 0.00162892); fall_capacitance : 0.00165667; - fall_capacitance_range (0.00165667, 0.00165667); + fall_capacitance_range (0.00165667, 0.00261736); timing () { related_pin : "CLK"; + sdf_edges : both_edges; timing_type : hold_rising; rise_constraint (CONSTRAINT_4x4) { index_1 ("0.0186, 0.51636, 1.263, 2.5074"); @@ -9167,6 +9172,7 @@ library (sg13g2_stdcell_slow_1p35V_125C) { } timing () { related_pin : "CLK"; + sdf_edges : both_edges; timing_type : setup_rising; rise_constraint (CONSTRAINT_4x4) { index_1 ("0.0186, 0.51636, 1.263, 2.5074"); @@ -9254,11 +9260,12 @@ library (sg13g2_stdcell_slow_1p35V_125C) { max_transition : 2.5074; capacitance : 0.00503345; rise_capacitance : 0.00509001; - rise_capacitance_range (0.00509001, 0.00509001); + rise_capacitance_range (0.00441558, 0.00629686); fall_capacitance : 0.00499304; - fall_capacitance_range (0.00499304, 0.00499304); + fall_capacitance_range (0.00465319, 0.00521438); timing () { related_pin : "CLK"; + sdf_edges : both_edges; timing_type : recovery_rising; rise_constraint (CONSTRAINT_4x4) { index_1 ("0.0186, 0.51636, 1.263, 2.5074"); @@ -9273,6 +9280,7 @@ library (sg13g2_stdcell_slow_1p35V_125C) { } timing () { related_pin : "CLK"; + sdf_edges : both_edges; timing_type : removal_rising; rise_constraint (CONSTRAINT_4x4) { index_1 ("0.0186, 0.51636, 1.263, 2.5074"); @@ -9371,14 +9379,14 @@ library (sg13g2_stdcell_slow_1p35V_125C) { } } ff (IQ,IQN) { - clear : "RESET_B'"; + clear : "!RESET_B"; clocked_on : "CLK"; next_state : "D"; } } cell (sg13g2_dfrbp_2) { area : 54.432; - cell_footprint : "dffrr"; + cell_footprint : "dfrbp"; cell_leakage_power : 5083.62; leakage_power () { value : 4578.35; @@ -9435,6 +9443,7 @@ library (sg13g2_stdcell_slow_1p35V_125C) { max_capacitance : 0.6; timing () { related_pin : "CLK"; + sdf_edges : start_edge; timing_sense : non_unate; timing_type : rising_edge; cell_rise (TIMING_DELAY_7x7ds1) { @@ -9492,6 +9501,7 @@ library (sg13g2_stdcell_slow_1p35V_125C) { } timing () { related_pin : "RESET_B"; + sdf_edges : start_edge; timing_sense : positive_unate; timing_type : clear; cell_fall (TIMING_DELAY_7x7ds1) { @@ -9579,6 +9589,7 @@ library (sg13g2_stdcell_slow_1p35V_125C) { max_capacitance : 0.6; timing () { related_pin : "CLK"; + sdf_edges : start_edge; timing_sense : non_unate; timing_type : rising_edge; cell_rise (TIMING_DELAY_7x7ds1) { @@ -9636,6 +9647,7 @@ library (sg13g2_stdcell_slow_1p35V_125C) { } timing () { related_pin : "RESET_B"; + sdf_edges : start_edge; timing_sense : negative_unate; timing_type : preset; cell_rise (TIMING_DELAY_7x7ds1) { @@ -9722,9 +9734,9 @@ library (sg13g2_stdcell_slow_1p35V_125C) { max_transition : 2.5074; capacitance : 0.00277757; rise_capacitance : 0.00295249; - rise_capacitance_range (0.00295249, 0.00295249); + rise_capacitance_range (0.00265195, 0.00321689); fall_capacitance : 0.00251519; - fall_capacitance_range (0.00251519, 0.00251519); + fall_capacitance_range (0.00251519, 0.003048); timing () { related_pin : "CLK"; timing_type : min_pulse_width; @@ -9850,11 +9862,12 @@ library (sg13g2_stdcell_slow_1p35V_125C) { max_transition : 2.5074; capacitance : 0.00153139; rise_capacitance : 0.00140213; - rise_capacitance_range (0.00140213, 0.00140213); + rise_capacitance_range (0.0013002, 0.00163228); fall_capacitance : 0.00166064; - fall_capacitance_range (0.00166064, 0.00166064); + fall_capacitance_range (0.00166064, 0.00262405); timing () { related_pin : "CLK"; + sdf_edges : both_edges; timing_type : hold_rising; rise_constraint (CONSTRAINT_4x4) { index_1 ("0.0186, 0.51636, 1.263, 2.5074"); @@ -9879,6 +9892,7 @@ library (sg13g2_stdcell_slow_1p35V_125C) { } timing () { related_pin : "CLK"; + sdf_edges : both_edges; timing_type : setup_rising; rise_constraint (CONSTRAINT_4x4) { index_1 ("0.0186, 0.51636, 1.263, 2.5074"); @@ -9966,11 +9980,12 @@ library (sg13g2_stdcell_slow_1p35V_125C) { max_transition : 2.5074; capacitance : 0.00508378; rise_capacitance : 0.00513995; - rise_capacitance_range (0.00513995, 0.00513995); + rise_capacitance_range (0.00446058, 0.00634438); fall_capacitance : 0.00504367; - fall_capacitance_range (0.00504367, 0.00504367); + fall_capacitance_range (0.00469896, 0.00526913); timing () { related_pin : "CLK"; + sdf_edges : both_edges; timing_type : recovery_rising; rise_constraint (CONSTRAINT_4x4) { index_1 ("0.0186, 0.51636, 1.263, 2.5074"); @@ -9985,6 +10000,7 @@ library (sg13g2_stdcell_slow_1p35V_125C) { } timing () { related_pin : "CLK"; + sdf_edges : both_edges; timing_type : removal_rising; rise_constraint (CONSTRAINT_4x4) { index_1 ("0.0186, 0.51636, 1.263, 2.5074"); @@ -10083,7 +10099,7 @@ library (sg13g2_stdcell_slow_1p35V_125C) { } } ff (IQ,IQN) { - clear : "RESET_B'"; + clear : "!RESET_B"; clocked_on : "CLK"; next_state : "D"; } @@ -10101,7 +10117,7 @@ library (sg13g2_stdcell_slow_1p35V_125C) { when : "!CLK&D&!RESET_B&!Q"; } leakage_power () { - value : 3240.68; + value : 3240.69; when : "CLK&!D&!RESET_B&!Q"; } leakage_power () { @@ -10147,89 +10163,91 @@ library (sg13g2_stdcell_slow_1p35V_125C) { max_capacitance : 0.3; timing () { related_pin : "CLK"; + sdf_edges : start_edge; timing_sense : non_unate; timing_type : rising_edge; cell_rise (TIMING_DELAY_7x7ds1) { index_1 ("0.0186, 0.0966, 0.174, 0.3294, 0.6408, 1.263, 2.5074"); index_2 ("0.001, 0.0234, 0.039, 0.0648, 0.108, 0.18, 0.3"); values ( \ - "0.156687, 0.22615, 0.272266, 0.348327, 0.475286, 0.687156, 1.03982", \ - "0.188836, 0.258383, 0.304581, 0.380603, 0.507726, 0.720197, 1.07207", \ - "0.210367, 0.279987, 0.326174, 0.402219, 0.529365, 0.740892, 1.09592", \ - "0.2419, 0.311354, 0.357585, 0.433632, 0.560695, 0.772289, 1.125", \ - "0.284086, 0.353543, 0.399724, 0.475766, 0.602824, 0.814532, 1.16702", \ - "0.34126, 0.410689, 0.456885, 0.532852, 0.66001, 0.871654, 1.22428", \ - "0.415848, 0.485519, 0.531693, 0.607874, 0.735137, 0.946781, 1.29952" \ + "0.156634, 0.226105, 0.272198, 0.348189, 0.475331, 0.687016, 1.03953", \ + "0.18878, 0.258363, 0.304555, 0.380622, 0.507644, 0.720071, 1.072", \ + "0.210377, 0.28001, 0.32618, 0.40222, 0.529289, 0.74083, 1.0939", \ + "0.241947, 0.311415, 0.357628, 0.433571, 0.560622, 0.772188, 1.1248", \ + "0.284095, 0.353545, 0.399706, 0.475732, 0.602755, 0.814379, 1.1668", \ + "0.341274, 0.410681, 0.456865, 0.532812, 0.659935, 0.871574, 1.22405", \ + "0.415875, 0.485523, 0.531645, 0.60772, 0.735051, 0.94654, 1.29932" \ ); } rise_transition (TIMING_DELAY_7x7ds1) { index_1 ("0.0186, 0.0966, 0.174, 0.3294, 0.6408, 1.263, 2.5074"); index_2 ("0.001, 0.0234, 0.039, 0.0648, 0.108, 0.18, 0.3"); values ( \ - "0.0185754, 0.11062, 0.177775, 0.288989, 0.475367, 0.786361, 1.30447", \ - "0.0186036, 0.110621, 0.177776, 0.289981, 0.475746, 0.787062, 1.30448", \ - "0.0186046, 0.110622, 0.177777, 0.289982, 0.475747, 0.787843, 1.30696", \ - "0.0187065, 0.110652, 0.177778, 0.289983, 0.475748, 0.787844, 1.30851", \ - "0.0188952, 0.110653, 0.177779, 0.289984, 0.475749, 0.787845, 1.30852", \ - "0.019382, 0.110688, 0.177793, 0.289985, 0.47575, 0.787846, 1.30853", \ - "0.020517, 0.110803, 0.177835, 0.289986, 0.475751, 0.787847, 1.30854" \ + "0.0185785, 0.110593, 0.177731, 0.288819, 0.475226, 0.786155, 1.30421", \ + "0.0185795, 0.110594, 0.177732, 0.289244, 0.475628, 0.786794, 1.30422", \ + "0.0185805, 0.1106, 0.177733, 0.289245, 0.475629, 0.786835, 1.30444", \ + "0.0186832, 0.11063, 0.177738, 0.289246, 0.47563, 0.786836, 1.30822", \ + "0.0188888, 0.110631, 0.177739, 0.289247, 0.475631, 0.786837, 1.30823", \ + "0.019381, 0.11066, 0.177748, 0.289248, 0.475632, 0.786838, 1.30824", \ + "0.020514, 0.110776, 0.177787, 0.289249, 0.475633, 0.786839, 1.30825" \ ); } cell_fall (TIMING_DELAY_7x7ds1) { index_1 ("0.0186, 0.0966, 0.174, 0.3294, 0.6408, 1.263, 2.5074"); index_2 ("0.001, 0.0234, 0.039, 0.0648, 0.108, 0.18, 0.3"); values ( \ - "0.155201, 0.217765, 0.257793, 0.32345, 0.43336, 0.616724, 0.92202", \ - "0.187189, 0.249784, 0.289782, 0.355569, 0.465572, 0.648739, 0.954635", \ - "0.208269, 0.270936, 0.310914, 0.376734, 0.486679, 0.669863, 0.975119", \ - "0.238457, 0.301088, 0.341094, 0.406865, 0.516845, 0.699976, 1.00519", \ - "0.276594, 0.339127, 0.379195, 0.44494, 0.554891, 0.738094, 1.04326", \ - "0.327961, 0.390513, 0.430475, 0.496287, 0.606269, 0.789397, 1.09457", \ - "0.391502, 0.454026, 0.494049, 0.559818, 0.669841, 0.852996, 1.15837" \ + "0.15519, 0.217684, 0.257746, 0.323494, 0.433436, 0.61677, 0.921887", \ + "0.187205, 0.249829, 0.289797, 0.355613, 0.465593, 0.648776, 0.954671", \ + "0.208273, 0.270906, 0.31087, 0.376762, 0.486688, 0.669865, 0.975162", \ + "0.238445, 0.300922, 0.341084, 0.4067, 0.516685, 0.699811, 1.00518", \ + "0.27654, 0.339171, 0.379142, 0.444941, 0.554882, 0.738097, 1.04326", \ + "0.327953, 0.390506, 0.43047, 0.496283, 0.606276, 0.789443, 1.09458", \ + "0.391505, 0.454028, 0.494051, 0.559821, 0.669848, 0.853006, 1.15838" \ ); } fall_transition (TIMING_DELAY_7x7ds1) { index_1 ("0.0186, 0.0966, 0.174, 0.3294, 0.6408, 1.263, 2.5074"); index_2 ("0.001, 0.0234, 0.039, 0.0648, 0.108, 0.18, 0.3"); values ( \ - "0.0159111, 0.0886175, 0.141299, 0.228715, 0.37592, 0.620482, 1.0287", \ - "0.0159121, 0.0886185, 0.1413, 0.228894, 0.375921, 0.620524, 1.02912", \ - "0.0159131, 0.0886195, 0.141301, 0.228937, 0.375922, 0.622321, 1.0293", \ - "0.0159141, 0.0886619, 0.141302, 0.228938, 0.375923, 0.622322, 1.02931", \ - "0.0159151, 0.0886629, 0.141303, 0.228939, 0.375924, 0.622323, 1.02932", \ - "0.0159161, 0.0886639, 0.141304, 0.22894, 0.375925, 0.622324, 1.02933", \ - "0.015937, 0.0886649, 0.141305, 0.228941, 0.375926, 0.622325, 1.02934" \ + "0.0159408, 0.0886092, 0.141209, 0.22883, 0.37592, 0.620479, 1.0287", \ + "0.0159418, 0.0886102, 0.141298, 0.228831, 0.375921, 0.620524, 1.02912", \ + "0.0159428, 0.0886479, 0.141299, 0.228936, 0.375922, 0.621031, 1.02931", \ + "0.0159438, 0.0886528, 0.1413, 0.228937, 0.375923, 0.621032, 1.02932", \ + "0.0159448, 0.0886538, 0.141301, 0.228938, 0.375924, 0.621033, 1.02933", \ + "0.0159458, 0.0886548, 0.141302, 0.228939, 0.375925, 0.621034, 1.02934", \ + "0.0159468, 0.0886558, 0.141303, 0.22894, 0.375926, 0.621035, 1.02935" \ ); } } timing () { related_pin : "RESET_B"; + sdf_edges : start_edge; timing_sense : positive_unate; timing_type : clear; cell_fall (TIMING_DELAY_7x7ds1) { index_1 ("0.0186, 0.0966, 0.174, 0.3294, 0.6408, 1.263, 2.5074"); index_2 ("0.001, 0.0234, 0.039, 0.0648, 0.108, 0.18, 0.3"); values ( \ - "0.223314, 0.285762, 0.325845, 0.391643, 0.501693, 0.684986, 0.990206", \ - "0.262004, 0.324481, 0.364505, 0.430401, 0.540359, 0.723557, 1.0288", \ - "0.295254, 0.357718, 0.39775, 0.463635, 0.57363, 0.756899, 1.0627", \ - "0.347123, 0.40962, 0.449647, 0.515422, 0.625433, 0.808631, 1.11388", \ - "0.425074, 0.487621, 0.527664, 0.593565, 0.703558, 0.886714, 1.19194", \ - "0.533024, 0.595607, 0.635589, 0.701513, 0.811529, 0.994731, 1.29996", \ - "0.682623, 0.745295, 0.785257, 0.851182, 0.961223, 1.14444, 1.44987" \ + "0.223265, 0.285795, 0.32575, 0.391664, 0.501651, 0.684957, 0.990203", \ + "0.261991, 0.324453, 0.36444, 0.430274, 0.540347, 0.72356, 1.02884", \ + "0.295209, 0.357669, 0.397751, 0.463659, 0.573628, 0.756903, 1.0627", \ + "0.347114, 0.409623, 0.449638, 0.515478, 0.625433, 0.808637, 1.11402", \ + "0.425063, 0.48761, 0.527655, 0.593556, 0.703551, 0.886708, 1.19194", \ + "0.533011, 0.595595, 0.635578, 0.701503, 0.811521, 0.994724, 1.29995", \ + "0.682607, 0.745281, 0.785237, 0.851167, 0.961212, 1.14443, 1.44986" \ ); } fall_transition (TIMING_DELAY_7x7ds1) { index_1 ("0.0186, 0.0966, 0.174, 0.3294, 0.6408, 1.263, 2.5074"); index_2 ("0.001, 0.0234, 0.039, 0.0648, 0.108, 0.18, 0.3"); values ( \ - "0.0158818, 0.0884881, 0.141111, 0.22871, 0.375914, 0.620479, 1.02854", \ - "0.0159175, 0.0885096, 0.141112, 0.228889, 0.375915, 0.620506, 1.02926", \ - "0.0159185, 0.0885106, 0.141183, 0.22889, 0.375918, 0.621192, 1.02936", \ - "0.0159256, 0.0885116, 0.141184, 0.228891, 0.375919, 0.621193, 1.02955", \ - "0.0160163, 0.0885572, 0.141185, 0.228892, 0.37592, 0.621194, 1.02956", \ - "0.016289, 0.088561, 0.141222, 0.228893, 0.375921, 0.621195, 1.02957", \ - "0.016481, 0.088629, 0.141291, 0.228894, 0.375922, 0.621196, 1.02958" \ + "0.0158719, 0.0885036, 0.141171, 0.228709, 0.375916, 0.620477, 1.02854", \ + "0.0158765, 0.0885046, 0.141172, 0.228882, 0.375917, 0.620506, 1.02874", \ + "0.0158775, 0.0885568, 0.141173, 0.228904, 0.375918, 0.621191, 1.02936", \ + "0.0159194, 0.0885578, 0.141174, 0.228905, 0.375919, 0.621192, 1.0295", \ + "0.0160146, 0.0885588, 0.141241, 0.228906, 0.37592, 0.621193, 1.02951", \ + "0.016288, 0.088559, 0.141242, 0.228907, 0.375921, 0.621194, 1.02952", \ + "0.016483, 0.088627, 0.141243, 0.228908, 0.375922, 0.621195, 1.02953" \ ); } } @@ -10239,26 +10257,26 @@ library (sg13g2_stdcell_slow_1p35V_125C) { index_1 ("0.0186, 0.0966, 0.174, 0.3294, 0.6408, 1.263, 2.5074"); index_2 ("0.001, 0.0234, 0.039, 0.0648, 0.108, 0.18, 0.3"); values ( \ - "0.0314921, 0.0319363, 0.0319442, 0.0319219, 0.0317635, 0.031509, 0.0315041", \ - "0.0311718, 0.0316926, 0.0316403, 0.0317358, 0.0315342, 0.0313621, 0.0308737", \ - "0.0313953, 0.0318058, 0.0318571, 0.0319221, 0.0317097, 0.0315974, 0.0314402", \ - "0.0324991, 0.0329378, 0.0329767, 0.0328909, 0.0329729, 0.0326811, 0.0328403", \ - "0.0349499, 0.0353498, 0.0354606, 0.0354818, 0.0352831, 0.0352577, 0.0346487", \ - "0.040633, 0.0410297, 0.0410693, 0.0410646, 0.0411872, 0.0409891, 0.040391", \ - "0.0529189, 0.0532576, 0.0532283, 0.0533267, 0.0532905, 0.0532486, 0.0532629" \ + "0.0314776, 0.0319323, 0.0319312, 0.0318919, 0.0317836, 0.0315083, 0.0314653", \ + "0.0311558, 0.0316858, 0.0316431, 0.0316569, 0.0315256, 0.0313263, 0.0312266", \ + "0.0314159, 0.0318375, 0.0319168, 0.032012, 0.0317334, 0.0315625, 0.0311872", \ + "0.0324996, 0.03295, 0.0329674, 0.0329059, 0.0329675, 0.0326517, 0.0326224", \ + "0.0349509, 0.0353508, 0.0354624, 0.0354817, 0.0352831, 0.0352341, 0.0346523", \ + "0.0406351, 0.0410299, 0.0410737, 0.0410878, 0.0411798, 0.0410601, 0.0403913", \ + "0.0529197, 0.0532528, 0.0532998, 0.0533025, 0.0533043, 0.0532573, 0.053297" \ ); } fall_power (POWER_7x7ds1) { index_1 ("0.0186, 0.0966, 0.174, 0.3294, 0.6408, 1.263, 2.5074"); index_2 ("0.001, 0.0234, 0.039, 0.0648, 0.108, 0.18, 0.3"); values ( \ - "0.0325965, 0.03312, 0.0331423, 0.033069, 0.0329258, 0.0327319, 0.0323003", \ - "0.0324405, 0.0329823, 0.0330847, 0.0330099, 0.03283, 0.0325412, 0.0322383", \ - "0.0328028, 0.033303, 0.0333114, 0.0333669, 0.0332434, 0.033175, 0.0325818", \ - "0.034001, 0.0345464, 0.0345967, 0.0345432, 0.0344079, 0.0345659, 0.034225", \ - "0.0365465, 0.0370876, 0.0370695, 0.0371867, 0.0371355, 0.0366466, 0.03687", \ - "0.0423369, 0.0428532, 0.0429151, 0.0429213, 0.0428564, 0.0428961, 0.0423642", \ - "0.0540149, 0.0545135, 0.0545122, 0.0544915, 0.0545635, 0.0545802, 0.0545797" \ + "0.0325994, 0.0331141, 0.0331192, 0.033085, 0.0329691, 0.0327566, 0.0322782", \ + "0.0324386, 0.0329856, 0.0330842, 0.0329639, 0.0328214, 0.032544, 0.0322434", \ + "0.0328565, 0.0333184, 0.0333262, 0.0334036, 0.0332364, 0.0331054, 0.0326131", \ + "0.0340093, 0.0345561, 0.0346247, 0.0345145, 0.0343889, 0.0345052, 0.0341933", \ + "0.0365498, 0.0370915, 0.0370727, 0.037199, 0.0371038, 0.0366518, 0.0368803", \ + "0.0423386, 0.0428604, 0.0429196, 0.0429328, 0.0428408, 0.0428544, 0.0422814", \ + "0.0540222, 0.0545188, 0.0545185, 0.0544968, 0.0545711, 0.0545822, 0.0545628" \ ); } } @@ -10273,13 +10291,13 @@ library (sg13g2_stdcell_slow_1p35V_125C) { index_1 ("0.0186, 0.0966, 0.174, 0.3294, 0.6408, 1.263, 2.5074"); index_2 ("0.001, 0.0234, 0.039, 0.0648, 0.108, 0.18, 0.3"); values ( \ - "0.0206917, 0.0211672, 0.0211826, 0.0211422, 0.0210631, 0.0208315, 0.0204059", \ - "0.0205556, 0.0211412, 0.0210626, 0.0210363, 0.0208999, 0.0207137, 0.0203293", \ - "0.0206625, 0.0211337, 0.0212069, 0.0211619, 0.0210345, 0.0208692, 0.0204459", \ - "0.0212128, 0.0216982, 0.0216862, 0.0216595, 0.0218251, 0.021728, 0.0209245", \ - "0.0225623, 0.023064, 0.0231074, 0.0231795, 0.0228657, 0.0229494, 0.0222305", \ - "0.0253576, 0.0258112, 0.0259155, 0.0259047, 0.0259101, 0.0259135, 0.0250406", \ - "0.0305538, 0.0310115, 0.0310059, 0.030977, 0.0311122, 0.0310982, 0.0311358" \ + "0.0206899, 0.021177, 0.0211811, 0.0211603, 0.0210643, 0.0208293, 0.0204121", \ + "0.0205545, 0.0211283, 0.0210882, 0.0210149, 0.0208826, 0.0207195, 0.0202556", \ + "0.0206719, 0.0211566, 0.0212152, 0.0211838, 0.0211273, 0.0208814, 0.0204674", \ + "0.021213, 0.0216957, 0.0216937, 0.0216575, 0.0218305, 0.0217317, 0.0210072", \ + "0.0225657, 0.0230684, 0.023125, 0.0231817, 0.0228714, 0.0229475, 0.0223123", \ + "0.025355, 0.0258113, 0.0259189, 0.025944, 0.0259584, 0.0259534, 0.0251219", \ + "0.0305555, 0.0310216, 0.0310033, 0.0309677, 0.0311149, 0.0311017, 0.0311379" \ ); } } @@ -10288,11 +10306,11 @@ library (sg13g2_stdcell_slow_1p35V_125C) { clock : true; direction : "input"; max_transition : 2.5074; - capacitance : 0.00274167; - rise_capacitance : 0.00294292; - rise_capacitance_range (0.00294292, 0.00294292); - fall_capacitance : 0.00250687; - fall_capacitance_range (0.00250687, 0.00250687); + capacitance : 0.00274154; + rise_capacitance : 0.00294254; + rise_capacitance_range (0.00264718, 0.00320931); + fall_capacitance : 0.00250703; + fall_capacitance_range (0.00250703, 0.00303905); timing () { related_pin : "CLK"; timing_type : min_pulse_width; @@ -10314,13 +10332,13 @@ library (sg13g2_stdcell_slow_1p35V_125C) { rise_power (passive_POWER_7x1ds1) { index_1 ("0.0186, 0.0966, 0.174, 0.3294, 0.6408, 1.263, 2.5074"); values ( \ - "0.0137586, 0.0135447, 0.0137971, 0.0147927, 0.0172222, 0.0227175, 0.0343203" \ + "0.013765, 0.0135386, 0.0137817, 0.0147899, 0.01722, 0.0227182, 0.0343202" \ ); } fall_power (passive_POWER_7x1ds1) { index_1 ("0.0186, 0.0966, 0.174, 0.3294, 0.6408, 1.263, 2.5074"); values ( \ - "0.0328212, 0.0325685, 0.0329861, 0.0339098, 0.036632, 0.0422305, 0.0547232" \ + "0.0328079, 0.0325765, 0.0329976, 0.0339092, 0.0366255, 0.0422301, 0.0547247" \ ); } } @@ -10334,7 +10352,7 @@ library (sg13g2_stdcell_slow_1p35V_125C) { fall_power (passive_POWER_7x1ds1) { index_1 ("0.0186, 0.0966, 0.174, 0.3294, 0.6408, 1.263, 2.5074"); values ( \ - "0.0260785, 0.025849, 0.0262522, 0.0271766, 0.0299025, 0.0355065, 0.0479921" \ + "0.0260888, 0.0258481, 0.0262696, 0.0271787, 0.0298997, 0.0355043, 0.0479926" \ ); } } @@ -10343,13 +10361,13 @@ library (sg13g2_stdcell_slow_1p35V_125C) { rise_power (passive_POWER_7x1ds1) { index_1 ("0.0186, 0.0966, 0.174, 0.3294, 0.6408, 1.263, 2.5074"); values ( \ - "0.0143141, 0.0141263, 0.0143852, 0.0154149, 0.0177903, 0.0232516, 0.0348556" \ + "0.0143332, 0.0141187, 0.014364, 0.0154158, 0.0178087, 0.0232464, 0.0348611" \ ); } fall_power (passive_POWER_7x1ds1) { index_1 ("0.0186, 0.0966, 0.174, 0.3294, 0.6408, 1.263, 2.5074"); values ( \ - "0.0135301, 0.0133161, 0.0137286, 0.0146409, 0.0173172, 0.0227311, 0.0347916" \ + "0.0135364, 0.0133178, 0.0137188, 0.0146411, 0.0173195, 0.0227327, 0.0347927" \ ); } } @@ -10363,7 +10381,7 @@ library (sg13g2_stdcell_slow_1p35V_125C) { fall_power (passive_POWER_7x1ds1) { index_1 ("0.0186, 0.0966, 0.174, 0.3294, 0.6408, 1.263, 2.5074"); values ( \ - "0.0381424, 0.0388935, 0.0388981, 0.0396864, 0.0421886, 0.0479547, 0.0599781" \ + "0.0381198, 0.0388952, 0.0389002, 0.0396874, 0.0421914, 0.0479563, 0.0599798" \ ); } } @@ -10372,13 +10390,13 @@ library (sg13g2_stdcell_slow_1p35V_125C) { rise_power (passive_POWER_7x1ds1) { index_1 ("0.0186, 0.0966, 0.174, 0.3294, 0.6408, 1.263, 2.5074"); values ( \ - "0.0135045, 0.0132945, 0.0135301, 0.0145211, 0.0169115, 0.022465, 0.0340864" \ + "0.0135076, 0.0132878, 0.0135173, 0.0145207, 0.0169088, 0.0224648, 0.0340855" \ ); } fall_power (passive_POWER_7x1ds1) { index_1 ("0.0186, 0.0966, 0.174, 0.3294, 0.6408, 1.263, 2.5074"); values ( \ - "0.0134278, 0.0132225, 0.0136252, 0.0145553, 0.0172073, 0.0226642, 0.0347129" \ + "0.0134527, 0.0132199, 0.0136236, 0.014559, 0.0172081, 0.0226648, 0.0347144" \ ); } } @@ -10387,13 +10405,13 @@ library (sg13g2_stdcell_slow_1p35V_125C) { rise_power (passive_POWER_7x1ds1) { index_1 ("0.0186, 0.0966, 0.174, 0.3294, 0.6408, 1.263, 2.5074"); values ( \ - "0.0141262, 0.0139342, 0.0141721, 0.0152285, 0.0175295, 0.0230484, 0.0346619" \ + "0.0141496, 0.0139237, 0.0141765, 0.0152258, 0.0176152, 0.0230453, 0.0346656" \ ); } fall_power (passive_POWER_7x1ds1) { index_1 ("0.0186, 0.0966, 0.174, 0.3294, 0.6408, 1.263, 2.5074"); values ( \ - "0.0134698, 0.0132413, 0.0136523, 0.0145539, 0.0172282, 0.0226511, 0.0347083" \ + "0.0134591, 0.0132348, 0.0136348, 0.0145585, 0.0172281, 0.0226543, 0.0347107" \ ); } } @@ -10401,13 +10419,13 @@ library (sg13g2_stdcell_slow_1p35V_125C) { rise_power (passive_POWER_7x1ds1) { index_1 ("0.0186, 0.0966, 0.174, 0.3294, 0.6408, 1.263, 2.5074"); values ( \ - "0.0137586, 0.0135447, 0.0137971, 0.0147927, 0.0172222, 0.0227175, 0.0343203" \ + "0.013765, 0.0135386, 0.0137817, 0.0147899, 0.01722, 0.0227182, 0.0343202" \ ); } fall_power (passive_POWER_7x1ds1) { index_1 ("0.0186, 0.0966, 0.174, 0.3294, 0.6408, 1.263, 2.5074"); values ( \ - "0.0260785, 0.025849, 0.0262522, 0.0271766, 0.0299025, 0.0355065, 0.0479921" \ + "0.0260888, 0.0258481, 0.0262696, 0.0271787, 0.0298997, 0.0355043, 0.0479926" \ ); } } @@ -10416,13 +10434,14 @@ library (sg13g2_stdcell_slow_1p35V_125C) { direction : "input"; nextstate_type : "data"; max_transition : 2.5074; - capacitance : 0.00139734; - rise_capacitance : 0.00138872; - rise_capacitance_range (0.00138872, 0.00138872); - fall_capacitance : 0.00140596; - fall_capacitance_range (0.00140596, 0.00140596); + capacitance : 0.00139735; + rise_capacitance : 0.00138871; + rise_capacitance_range (0.00129674, 0.00162891); + fall_capacitance : 0.00140598; + fall_capacitance_range (0.00140598, 0.00174349); timing () { related_pin : "CLK"; + sdf_edges : both_edges; timing_type : hold_rising; rise_constraint (CONSTRAINT_4x4) { index_1 ("0.0186, 0.51636, 1.263, 2.5074"); @@ -10447,6 +10466,7 @@ library (sg13g2_stdcell_slow_1p35V_125C) { } timing () { related_pin : "CLK"; + sdf_edges : both_edges; timing_type : setup_rising; rise_constraint (CONSTRAINT_4x4) { index_1 ("0.0186, 0.51636, 1.263, 2.5074"); @@ -10462,10 +10482,10 @@ library (sg13g2_stdcell_slow_1p35V_125C) { index_1 ("0.0186, 0.51636, 1.263, 2.5074"); index_2 ("0.0186, 0.51636, 1.263, 2.5074"); values ( \ - "0.102698, 0.000246497, -0.0524346, -0.109805", \ + "0.102698, 0.000246497, -0.0550064, -0.109805", \ "0.264311, 0.16552, 0.106552, 0.0461353", \ - "0.399625, 0.299922, 0.24825, 0.187981", \ - "0.544241, 0.451434, 0.399609, 0.34533" \ + "0.399625, 0.302544, 0.24825, 0.187981", \ + "0.54694, 0.451434, 0.399609, 0.34533" \ ); } } @@ -10474,13 +10494,13 @@ library (sg13g2_stdcell_slow_1p35V_125C) { rise_power (passive_POWER_7x1ds1) { index_1 ("0.0186, 0.0966, 0.174, 0.3294, 0.6408, 1.263, 2.5074"); values ( \ - "0.00212513, 0.00206759, 0.00220151, 0.00257904, 0.00348149, 0.00543453, 0.00960279" \ + "0.00212909, 0.0020723, 0.00220187, 0.00257906, 0.00348151, 0.00542549, 0.00960225" \ ); } fall_power (passive_POWER_7x1ds1) { index_1 ("0.0186, 0.0966, 0.174, 0.3294, 0.6408, 1.263, 2.5074"); values ( \ - "0.00157201, 0.00152089, 0.00166316, 0.00206543, 0.00300823, 0.00503992, 0.00935341" \ + "0.00156844, 0.0015227, 0.00166386, 0.00206617, 0.00300848, 0.00504036, 0.00935351" \ ); } } @@ -10489,13 +10509,13 @@ library (sg13g2_stdcell_slow_1p35V_125C) { rise_power (passive_POWER_7x1ds1) { index_1 ("0.0186, 0.0966, 0.174, 0.3294, 0.6408, 1.263, 2.5074"); values ( \ - "0.0148901, 0.0148487, 0.0149837, 0.0153601, 0.0162048, 0.0184774, 0.0231065" \ + "0.0148831, 0.0148523, 0.0149899, 0.0153595, 0.0162032, 0.0184809, 0.023106" \ ); } fall_power (passive_POWER_7x1ds1) { index_1 ("0.0186, 0.0966, 0.174, 0.3294, 0.6408, 1.263, 2.5074"); values ( \ - "0.0113415, 0.0112665, 0.0113783, 0.0117981, 0.0129129, 0.0151722, 0.0203475" \ + "0.0113477, 0.0112679, 0.0113718, 0.0117985, 0.0129206, 0.0151719, 0.0203476" \ ); } } @@ -10504,13 +10524,13 @@ library (sg13g2_stdcell_slow_1p35V_125C) { rise_power (passive_POWER_7x1ds1) { index_1 ("0.0186, 0.0966, 0.174, 0.3294, 0.6408, 1.263, 2.5074"); values ( \ - "-0.000106371, -0.000107997, -0.000106858, -0.000105127, -0.000103116, -0.000103231, -0.000102874" \ + "-0.000111046, -0.000106067, -0.000105219, -0.000105727, -0.000103113, -0.000103224, -0.000102797" \ ); } fall_power (passive_POWER_7x1ds1) { index_1 ("0.0186, 0.0966, 0.174, 0.3294, 0.6408, 1.263, 2.5074"); values ( \ - "0.000126514, 0.000131962, 0.000132232, 0.000129159, 0.000133197, 0.000133602, 0.00013448" \ + "0.000125417, 0.000131972, 0.000132428, 0.000129356, 0.000133175, 0.000133583, 0.000134506" \ ); } } @@ -10518,13 +10538,13 @@ library (sg13g2_stdcell_slow_1p35V_125C) { rise_power (passive_POWER_7x1ds1) { index_1 ("0.0186, 0.0966, 0.174, 0.3294, 0.6408, 1.263, 2.5074"); values ( \ - "0.00212513, 0.00206759, 0.00220151, 0.00257904, 0.00348149, 0.00543453, 0.00960279" \ + "0.00212909, 0.0020723, 0.00220187, 0.00257906, 0.00348151, 0.00542549, 0.00960225" \ ); } fall_power (passive_POWER_7x1ds1) { index_1 ("0.0186, 0.0966, 0.174, 0.3294, 0.6408, 1.263, 2.5074"); values ( \ - "0.00157201, 0.00152089, 0.00166316, 0.00206543, 0.00300823, 0.00503992, 0.00935341" \ + "0.00156844, 0.0015227, 0.00166386, 0.00206617, 0.00300848, 0.00504036, 0.00935351" \ ); } } @@ -10532,19 +10552,20 @@ library (sg13g2_stdcell_slow_1p35V_125C) { pin (RESET_B) { direction : "input"; max_transition : 2.5074; - capacitance : 0.00497146; - rise_capacitance : 0.00494458; - rise_capacitance_range (0.00494458, 0.00494458); - fall_capacitance : 0.00499386; - fall_capacitance_range (0.00499386, 0.00499386); + capacitance : 0.00497166; + rise_capacitance : 0.0049448; + rise_capacitance_range (0.00438594, 0.00546822); + fall_capacitance : 0.00499405; + fall_capacitance_range (0.00465214, 0.00519483); timing () { related_pin : "CLK"; + sdf_edges : both_edges; timing_type : recovery_rising; rise_constraint (CONSTRAINT_4x4) { index_1 ("0.0186, 0.51636, 1.263, 2.5074"); index_2 ("0.0186, 0.51636, 1.263, 2.5074"); values ( \ - "0.117369, 0.0576505, 0.0350059, 0.0143199", \ + "0.117369, 0.0601463, 0.0350059, 0.0143199", \ "0.24684, 0.180799, 0.156378, 0.131354", \ "0.350761, 0.278943, 0.253646, 0.22753", \ "0.484877, 0.412948, 0.385484, 0.363039" \ @@ -10553,12 +10574,13 @@ library (sg13g2_stdcell_slow_1p35V_125C) { } timing () { related_pin : "CLK"; + sdf_edges : both_edges; timing_type : removal_rising; rise_constraint (CONSTRAINT_4x4) { index_1 ("0.0186, 0.51636, 1.263, 2.5074"); index_2 ("0.0186, 0.51636, 1.263, 2.5074"); values ( \ - "-0.100253, -0.050163, -0.0298623, -0.00622484", \ + "-0.100253, -0.050163, -0.0272905, -0.0089232", \ "-0.226874, -0.168066, -0.145888, -0.123107", \ "-0.325043, -0.265831, -0.242853, -0.219055", \ "-0.452497, -0.393705, -0.374185, -0.351233" \ @@ -10580,13 +10602,13 @@ library (sg13g2_stdcell_slow_1p35V_125C) { rise_power (passive_POWER_7x1ds1) { index_1 ("0.0186, 0.0966, 0.174, 0.3294, 0.6408, 1.263, 2.5074"); values ( \ - "0.00430815, 0.00418376, 0.00421849, 0.00440557, 0.0051172, 0.0069094, 0.0107276" \ + "0.00431156, 0.00418478, 0.00422174, 0.00440844, 0.00511829, 0.0069079, 0.0107273" \ ); } fall_power (passive_POWER_7x1ds1) { index_1 ("0.0186, 0.0966, 0.174, 0.3294, 0.6408, 1.263, 2.5074"); values ( \ - "0.0323944, 0.0319061, 0.0320455, 0.0328321, 0.0353819, 0.0411127, 0.0529332" \ + "0.03239, 0.0319042, 0.0320419, 0.0328324, 0.035387, 0.0411171, 0.0529345" \ ); } } @@ -10595,13 +10617,13 @@ library (sg13g2_stdcell_slow_1p35V_125C) { rise_power (passive_POWER_7x1ds1) { index_1 ("0.0186, 0.0966, 0.174, 0.3294, 0.6408, 1.263, 2.5074"); values ( \ - "0.00134815, 0.00133956, 0.0013411, 0.00134248, 0.00134676, 0.0013448, 0.0013474" \ + "0.00134291, 0.00134259, 0.00134175, 0.00134013, 0.00134496, 0.00134404, 0.00134667" \ ); } fall_power (passive_POWER_7x1ds1) { index_1 ("0.0186, 0.0966, 0.174, 0.3294, 0.6408, 1.263, 2.5074"); values ( \ - "-0.000805841, -0.000969791, -0.00100817, -0.00104302, -0.00106863, -0.00110101, -0.00112624" \ + "-0.000806876, -0.000969288, -0.0010102, -0.00104341, -0.00106888, -0.00110259, -0.00112644" \ ); } } @@ -10610,13 +10632,13 @@ library (sg13g2_stdcell_slow_1p35V_125C) { rise_power (passive_POWER_7x1ds1) { index_1 ("0.0186, 0.0966, 0.174, 0.3294, 0.6408, 1.263, 2.5074"); values ( \ - "0.0174934, 0.0172512, 0.0173058, 0.0176244, 0.0185686, 0.0211937, 0.0269516" \ + "0.0174934, 0.0172576, 0.0173057, 0.0176202, 0.0185684, 0.0211947, 0.0269531" \ ); } fall_power (passive_POWER_7x1ds1) { index_1 ("0.0186, 0.0966, 0.174, 0.3294, 0.6408, 1.263, 2.5074"); values ( \ - "0.0115752, 0.0112325, 0.0112328, 0.0114494, 0.0125757, 0.0155193, 0.0218747" \ + "0.0115742, 0.0112296, 0.0112287, 0.0114492, 0.0125732, 0.0155211, 0.0218742" \ ); } } @@ -10625,13 +10647,13 @@ library (sg13g2_stdcell_slow_1p35V_125C) { rise_power (passive_POWER_7x1ds1) { index_1 ("0.0186, 0.0966, 0.174, 0.3294, 0.6408, 1.263, 2.5074"); values ( \ - "0.00131983, 0.00130537, 0.00130175, 0.00130233, 0.00130857, 0.00130871, 0.00130621" \ + "0.00130916, 0.00130693, 0.00129806, 0.00130427, 0.00131064, 0.00130901, 0.00130691" \ ); } fall_power (passive_POWER_7x1ds1) { index_1 ("0.0186, 0.0966, 0.174, 0.3294, 0.6408, 1.263, 2.5074"); values ( \ - "-0.00113745, -0.00125671, -0.00128657, -0.00130233, -0.00130857, -0.00130871, -0.00130621" \ + "-0.0011433, -0.00125646, -0.00128711, -0.00130427, -0.00131064, -0.00130901, -0.00130691" \ ); } } @@ -10639,19 +10661,19 @@ library (sg13g2_stdcell_slow_1p35V_125C) { rise_power (passive_POWER_7x1ds1) { index_1 ("0.0186, 0.0966, 0.174, 0.3294, 0.6408, 1.263, 2.5074"); values ( \ - "0.00430815, 0.00418376, 0.00421849, 0.00440557, 0.0051172, 0.0069094, 0.0107276" \ + "0.00431156, 0.00418478, 0.00422174, 0.00440844, 0.00511829, 0.0069079, 0.0107273" \ ); } fall_power (passive_POWER_7x1ds1) { index_1 ("0.0186, 0.0966, 0.174, 0.3294, 0.6408, 1.263, 2.5074"); values ( \ - "0.0115752, 0.0112325, 0.0112328, 0.0114494, 0.0125757, 0.0155193, 0.0218747" \ + "0.0115742, 0.0112296, 0.0112287, 0.0114492, 0.0125732, 0.0155211, 0.0218742" \ ); } } } ff (IQ,IQN) { - clear : "RESET_B'"; + clear : "!RESET_B"; clocked_on : "CLK"; next_state : "D"; } @@ -10715,13 +10737,14 @@ library (sg13g2_stdcell_slow_1p35V_125C) { max_capacitance : 0.6; timing () { related_pin : "CLK"; + sdf_edges : start_edge; timing_sense : non_unate; timing_type : rising_edge; cell_rise (TIMING_DELAY_7x7ds1) { index_1 ("0.0186, 0.0966, 0.174, 0.3294, 0.6408, 1.263, 2.5074"); index_2 ("0.001, 0.0468, 0.078, 0.1296, 0.216, 0.36, 0.6"); values ( \ - "0.168776, 0.244594, 0.290792, 0.366918, 0.494146, 0.705968, 1.0592", \ + "0.168776, 0.244565, 0.290789, 0.366918, 0.494087, 0.706003, 1.05923", \ "0.200857, 0.27662, 0.322847, 0.398989, 0.526158, 0.738158, 1.09096", \ "0.222265, 0.298059, 0.344246, 0.420345, 0.547706, 0.759467, 1.11356", \ "0.253894, 0.329642, 0.37585, 0.451937, 0.579148, 0.790878, 1.14395", \ @@ -10734,12 +10757,12 @@ library (sg13g2_stdcell_slow_1p35V_125C) { index_1 ("0.0186, 0.0966, 0.174, 0.3294, 0.6408, 1.263, 2.5074"); index_2 ("0.001, 0.0468, 0.078, 0.1296, 0.216, 0.36, 0.6"); values ( \ - "0.0204032, 0.111506, 0.178364, 0.289673, 0.476389, 0.787684, 1.30647", \ - "0.0204339, 0.111507, 0.178371, 0.290852, 0.476415, 0.787775, 1.30682", \ - "0.0204572, 0.111579, 0.178377, 0.290853, 0.476416, 0.79035, 1.30833", \ - "0.0205056, 0.11158, 0.178378, 0.290854, 0.476417, 0.790351, 1.30834", \ - "0.020691, 0.111581, 0.178379, 0.290855, 0.47647, 0.790352, 1.30835", \ - "0.021112, 0.111633, 0.178414, 0.290856, 0.476471, 0.790353, 1.30836", \ + "0.0204032, 0.11152, 0.178443, 0.289674, 0.476389, 0.787689, 1.30647", \ + "0.020434, 0.111521, 0.178444, 0.290852, 0.476415, 0.787775, 1.30682", \ + "0.0204572, 0.111579, 0.178445, 0.290853, 0.476416, 0.79035, 1.30833", \ + "0.0205056, 0.11158, 0.178446, 0.290854, 0.476417, 0.790351, 1.30834", \ + "0.020691, 0.111581, 0.178447, 0.290855, 0.47647, 0.790352, 1.30835", \ + "0.021112, 0.111633, 0.178448, 0.290856, 0.476471, 0.790353, 1.30836", \ "0.022075, 0.111809, 0.178498, 0.290857, 0.476472, 0.790354, 1.30837" \ ); } @@ -10747,11 +10770,11 @@ library (sg13g2_stdcell_slow_1p35V_125C) { index_1 ("0.0186, 0.0966, 0.174, 0.3294, 0.6408, 1.263, 2.5074"); index_2 ("0.001, 0.0468, 0.078, 0.1296, 0.216, 0.36, 0.6"); values ( \ - "0.16682, 0.237015, 0.277337, 0.34334, 0.453508, 0.637003, 0.942478", \ + "0.166816, 0.237032, 0.277339, 0.343357, 0.453593, 0.637002, 0.942607", \ "0.198837, 0.26901, 0.309288, 0.375397, 0.48555, 0.66906, 0.974596", \ "0.219866, 0.290034, 0.330408, 0.39643, 0.506586, 0.690096, 0.995561", \ "0.249966, 0.32008, 0.360438, 0.426557, 0.536612, 0.719999, 1.02559", \ - "0.288206, 0.358258, 0.39859, 0.464602, 0.574786, 0.758337, 1.06372", \ + "0.288206, 0.358308, 0.39859, 0.464602, 0.574786, 0.758233, 1.06374", \ "0.339821, 0.409961, 0.450265, 0.516256, 0.626487, 0.809875, 1.11545", \ "0.40329, 0.473385, 0.51366, 0.579703, 0.689862, 0.873324, 1.17902" \ ); @@ -10760,25 +10783,26 @@ library (sg13g2_stdcell_slow_1p35V_125C) { index_1 ("0.0186, 0.0966, 0.174, 0.3294, 0.6408, 1.263, 2.5074"); index_2 ("0.001, 0.0468, 0.078, 0.1296, 0.216, 0.36, 0.6"); values ( \ - "0.0181857, 0.0916605, 0.143769, 0.231087, 0.378398, 0.623318, 1.03216", \ - "0.0181867, 0.0916775, 0.143807, 0.231088, 0.378399, 0.623319, 1.03274", \ - "0.0181954, 0.0916806, 0.143808, 0.231106, 0.3784, 0.623919, 1.03285", \ - "0.0182052, 0.0916816, 0.143809, 0.231162, 0.378401, 0.62392, 1.03286", \ - "0.0182062, 0.0916826, 0.14381, 0.231163, 0.378402, 0.623921, 1.03287", \ - "0.0182072, 0.0916836, 0.143811, 0.231164, 0.378403, 0.623922, 1.03288", \ - "0.0182082, 0.0916846, 0.143812, 0.231255, 0.378404, 0.623923, 1.03289" \ + "0.0181994, 0.0916316, 0.143768, 0.231085, 0.378398, 0.623319, 1.03243", \ + "0.0182004, 0.0916774, 0.143807, 0.231086, 0.378399, 0.62332, 1.03274", \ + "0.0182014, 0.0916806, 0.143808, 0.231106, 0.3784, 0.623919, 1.03275", \ + "0.0182052, 0.0916816, 0.143809, 0.231162, 0.378401, 0.62392, 1.03276", \ + "0.0182062, 0.0916826, 0.14381, 0.231163, 0.378402, 0.623921, 1.03277", \ + "0.0182072, 0.0916836, 0.143811, 0.231164, 0.378403, 0.623922, 1.03278", \ + "0.0182082, 0.0916846, 0.143812, 0.231255, 0.378404, 0.623923, 1.03279" \ ); } } timing () { related_pin : "RESET_B"; + sdf_edges : start_edge; timing_sense : positive_unate; timing_type : clear; cell_fall (TIMING_DELAY_7x7ds1) { index_1 ("0.0186, 0.0966, 0.174, 0.3294, 0.6408, 1.263, 2.5074"); index_2 ("0.001, 0.0468, 0.078, 0.1296, 0.216, 0.36, 0.6"); values ( \ - "0.233769, 0.303658, 0.343891, 0.4099, 0.520291, 0.703876, 1.00967", \ + "0.233777, 0.303642, 0.34393, 0.410054, 0.520249, 0.7038, 1.0097", \ "0.272305, 0.342185, 0.382482, 0.448631, 0.55886, 0.74256, 1.04852", \ "0.305549, 0.375388, 0.415683, 0.481748, 0.592037, 0.775612, 1.0817", \ "0.357617, 0.427507, 0.467754, 0.533833, 0.643988, 0.827531, 1.13325", \ @@ -10791,10 +10815,10 @@ library (sg13g2_stdcell_slow_1p35V_125C) { index_1 ("0.0186, 0.0966, 0.174, 0.3294, 0.6408, 1.263, 2.5074"); index_2 ("0.001, 0.0468, 0.078, 0.1296, 0.216, 0.36, 0.6"); values ( \ - "0.017996, 0.0915131, 0.143733, 0.231052, 0.378394, 0.623717, 1.0321", \ - "0.0180158, 0.091514, 0.143734, 0.231218, 0.378395, 0.623718, 1.03211", \ - "0.0180168, 0.0915147, 0.143735, 0.231219, 0.378396, 0.62389, 1.03246", \ - "0.0180367, 0.0915157, 0.143736, 0.23122, 0.378397, 0.623891, 1.03381", \ + "0.0180048, 0.0915158, 0.14363, 0.231054, 0.378394, 0.623319, 1.0321", \ + "0.0180158, 0.0915168, 0.143674, 0.231218, 0.378395, 0.623613, 1.03211", \ + "0.0180168, 0.0915178, 0.143715, 0.231219, 0.378396, 0.62389, 1.03246", \ + "0.0180367, 0.0915188, 0.143716, 0.23122, 0.378397, 0.623891, 1.03381", \ "0.0181374, 0.0915725, 0.143742, 0.231221, 0.378398, 0.623892, 1.03382", \ "0.018294, 0.0915735, 0.143743, 0.231222, 0.378399, 0.623893, 1.03383", \ "0.018528, 0.091736, 0.143744, 0.231223, 0.3784, 0.623894, 1.03384" \ @@ -10807,26 +10831,26 @@ library (sg13g2_stdcell_slow_1p35V_125C) { index_1 ("0.0186, 0.0966, 0.174, 0.3294, 0.6408, 1.263, 2.5074"); index_2 ("0.001, 0.0468, 0.078, 0.1296, 0.216, 0.36, 0.6"); values ( \ - "0.0356025, 0.0363806, 0.0364557, 0.0363832, 0.0361816, 0.0356366, 0.0357441", \ - "0.0352655, 0.0362026, 0.0361853, 0.0362726, 0.0358232, 0.0354095, 0.0354423", \ - "0.0354904, 0.0361769, 0.0363728, 0.0363311, 0.0361991, 0.0361408, 0.0353857", \ - "0.036575, 0.0373542, 0.0374125, 0.0373417, 0.0374422, 0.0369973, 0.0368461", \ - "0.039007, 0.0396842, 0.0399583, 0.0400298, 0.0395498, 0.0395656, 0.0388655", \ - "0.0447063, 0.0454151, 0.0455199, 0.0455271, 0.0457557, 0.0454488, 0.0444139", \ - "0.0570586, 0.0575479, 0.0576987, 0.0578974, 0.0578621, 0.0578883, 0.0579965" \ + "0.0356026, 0.0363707, 0.0364496, 0.036408, 0.036169, 0.0356637, 0.0357506", \ + "0.0352655, 0.0361932, 0.0361854, 0.0362726, 0.0358232, 0.0354095, 0.0354423", \ + "0.0354904, 0.0361769, 0.0363728, 0.036331, 0.0361991, 0.0361408, 0.0353857", \ + "0.036575, 0.0373542, 0.0374124, 0.0373417, 0.0374422, 0.0369973, 0.0368461", \ + "0.039007, 0.0396845, 0.0399583, 0.0400298, 0.0395498, 0.0395656, 0.0388655", \ + "0.0447063, 0.0454151, 0.0455198, 0.0455271, 0.0457557, 0.0454488, 0.0444139", \ + "0.0570586, 0.0575479, 0.0576987, 0.057898, 0.0578621, 0.0578883, 0.0579965" \ ); } fall_power (POWER_7x7ds1) { index_1 ("0.0186, 0.0966, 0.174, 0.3294, 0.6408, 1.263, 2.5074"); index_2 ("0.001, 0.0468, 0.078, 0.1296, 0.216, 0.36, 0.6"); values ( \ - "0.0365875, 0.0376287, 0.0376676, 0.0376171, 0.0374727, 0.0369726, 0.0359648", \ - "0.0364412, 0.0374853, 0.0375953, 0.0374696, 0.0372664, 0.0368218, 0.0360771", \ - "0.0367761, 0.0377977, 0.0378471, 0.0380275, 0.0379789, 0.0373158, 0.0363245", \ + "0.0365855, 0.0376067, 0.0376756, 0.037608, 0.0374825, 0.0369723, 0.0361822", \ + "0.0364412, 0.0374852, 0.0375965, 0.0374696, 0.0372664, 0.0368218, 0.0360774", \ + "0.0367761, 0.0377977, 0.0378471, 0.0380275, 0.0379789, 0.0373158, 0.0364239", \ "0.0380263, 0.0391, 0.0391656, 0.0390202, 0.0389129, 0.0386246, 0.0388769", \ - "0.0405515, 0.04161, 0.0416427, 0.0418575, 0.0417905, 0.0408079, 0.0413826", \ + "0.0405515, 0.0416097, 0.0416427, 0.0418575, 0.0417905, 0.040987, 0.0415103", \ "0.0462722, 0.0473065, 0.0473742, 0.0475126, 0.0474625, 0.0476011, 0.0464471", \ - "0.058009, 0.0589478, 0.0589791, 0.0590921, 0.0591464, 0.0592459, 0.0592098" \ + "0.058009, 0.0589476, 0.0589789, 0.0590921, 0.0591464, 0.0592459, 0.0592098" \ ); } } @@ -10841,8 +10865,8 @@ library (sg13g2_stdcell_slow_1p35V_125C) { index_1 ("0.0186, 0.0966, 0.174, 0.3294, 0.6408, 1.263, 2.5074"); index_2 ("0.001, 0.0468, 0.078, 0.1296, 0.216, 0.36, 0.6"); values ( \ - "0.0245749, 0.0254694, 0.0255347, 0.0254618, 0.0253266, 0.0249568, 0.0240542", \ - "0.0244053, 0.0253369, 0.0254974, 0.0253407, 0.0251665, 0.0247903, 0.0240763", \ + "0.0245685, 0.0254701, 0.0255189, 0.025483, 0.0253213, 0.024888, 0.0240645", \ + "0.0244053, 0.0253369, 0.0254974, 0.0253407, 0.0251665, 0.0247903, 0.0240762", \ "0.0245277, 0.0254329, 0.0255983, 0.0254759, 0.0253253, 0.0249154, 0.0241686", \ "0.0251382, 0.026083, 0.0260538, 0.0260725, 0.0264492, 0.0256073, 0.024924", \ "0.026452, 0.027356, 0.0275229, 0.0275826, 0.02702, 0.0271181, 0.0258206", \ @@ -10858,9 +10882,9 @@ library (sg13g2_stdcell_slow_1p35V_125C) { max_transition : 2.5074; capacitance : 0.00275065; rise_capacitance : 0.00295183; - rise_capacitance_range (0.00295183, 0.00295183); + rise_capacitance_range (0.00265234, 0.00321669); fall_capacitance : 0.00251593; - fall_capacitance_range (0.00251593, 0.00251593); + fall_capacitance_range (0.00251593, 0.00304803); timing () { related_pin : "CLK"; timing_type : min_pulse_width; @@ -10882,7 +10906,7 @@ library (sg13g2_stdcell_slow_1p35V_125C) { rise_power (passive_POWER_7x1ds1) { index_1 ("0.0186, 0.0966, 0.174, 0.3294, 0.6408, 1.263, 2.5074"); values ( \ - "0.0138112, 0.0135854, 0.0138185, 0.0148441, 0.0172682, 0.0227549, 0.0343686" \ + "0.0137884, 0.0135854, 0.0138185, 0.0148441, 0.0172682, 0.0227549, 0.0343686" \ ); } fall_power (passive_POWER_7x1ds1) { @@ -10902,7 +10926,7 @@ library (sg13g2_stdcell_slow_1p35V_125C) { fall_power (passive_POWER_7x1ds1) { index_1 ("0.0186, 0.0966, 0.174, 0.3294, 0.6408, 1.263, 2.5074"); values ( \ - "0.0260375, 0.0257727, 0.0261633, 0.0271288, 0.0297938, 0.0354228, 0.0479257" \ + "0.0260375, 0.0257727, 0.0261633, 0.0271289, 0.0297938, 0.0354228, 0.0479256" \ ); } } @@ -10911,13 +10935,13 @@ library (sg13g2_stdcell_slow_1p35V_125C) { rise_power (passive_POWER_7x1ds1) { index_1 ("0.0186, 0.0966, 0.174, 0.3294, 0.6408, 1.263, 2.5074"); values ( \ - "0.0144468, 0.0142495, 0.0144815, 0.0155365, 0.017853, 0.0233502, 0.0349661" \ + "0.0144282, 0.0142495, 0.0144815, 0.0155365, 0.0178531, 0.0233502, 0.0349661" \ ); } fall_power (passive_POWER_7x1ds1) { index_1 ("0.0186, 0.0966, 0.174, 0.3294, 0.6408, 1.263, 2.5074"); values ( \ - "0.0134922, 0.0132614, 0.0136676, 0.0146026, 0.0172634, 0.0226833, 0.0347397" \ + "0.0134922, 0.0132568, 0.0136676, 0.0146026, 0.0172634, 0.0226833, 0.0347397" \ ); } } @@ -10931,7 +10955,7 @@ library (sg13g2_stdcell_slow_1p35V_125C) { fall_power (passive_POWER_7x1ds1) { index_1 ("0.0186, 0.0966, 0.174, 0.3294, 0.6408, 1.263, 2.5074"); values ( \ - "0.0482469, 0.0488776, 0.0488987, 0.0496901, 0.0522002, 0.0577809, 0.0698078" \ + "0.0482469, 0.0488776, 0.0488987, 0.0496901, 0.0522002, 0.0577809, 0.0698079" \ ); } } @@ -10940,13 +10964,13 @@ library (sg13g2_stdcell_slow_1p35V_125C) { rise_power (passive_POWER_7x1ds1) { index_1 ("0.0186, 0.0966, 0.174, 0.3294, 0.6408, 1.263, 2.5074"); values ( \ - "0.0136199, 0.0133989, 0.0136215, 0.0146581, 0.0170363, 0.022575, 0.0341998" \ + "0.0136196, 0.0133989, 0.0136215, 0.0146581, 0.0170362, 0.022575, 0.0341998" \ ); } fall_power (passive_POWER_7x1ds1) { index_1 ("0.0186, 0.0966, 0.174, 0.3294, 0.6408, 1.263, 2.5074"); values ( \ - "0.0133916, 0.0131613, 0.0135748, 0.0145156, 0.0171546, 0.0225903, 0.0346636" \ + "0.0133923, 0.0131613, 0.0135748, 0.0145156, 0.0171546, 0.0225903, 0.0346636" \ ); } } @@ -10955,13 +10979,13 @@ library (sg13g2_stdcell_slow_1p35V_125C) { rise_power (passive_POWER_7x1ds1) { index_1 ("0.0186, 0.0966, 0.174, 0.3294, 0.6408, 1.263, 2.5074"); values ( \ - "0.0142581, 0.0140543, 0.0142797, 0.0153371, 0.017721, 0.0231611, 0.0347688" \ + "0.0142573, 0.0140543, 0.0142797, 0.0153371, 0.0177232, 0.0231612, 0.0347688" \ ); } fall_power (passive_POWER_7x1ds1) { index_1 ("0.0186, 0.0966, 0.174, 0.3294, 0.6408, 1.263, 2.5074"); values ( \ - "0.0134161, 0.0131785, 0.0135834, 0.0145174, 0.0171797, 0.022603, 0.0346602" \ + "0.013416, 0.0131785, 0.0135834, 0.0145174, 0.0171797, 0.022603, 0.0346602" \ ); } } @@ -10969,13 +10993,13 @@ library (sg13g2_stdcell_slow_1p35V_125C) { rise_power (passive_POWER_7x1ds1) { index_1 ("0.0186, 0.0966, 0.174, 0.3294, 0.6408, 1.263, 2.5074"); values ( \ - "0.0142581, 0.0140543, 0.0142797, 0.0153371, 0.017721, 0.0231611, 0.0347688" \ + "0.0142573, 0.0140543, 0.0142797, 0.0153371, 0.0177232, 0.0231612, 0.0347688" \ ); } fall_power (passive_POWER_7x1ds1) { index_1 ("0.0186, 0.0966, 0.174, 0.3294, 0.6408, 1.263, 2.5074"); values ( \ - "0.0260375, 0.0257727, 0.0261633, 0.0271288, 0.0297938, 0.0354228, 0.0479257" \ + "0.0260375, 0.0257727, 0.0261633, 0.0271289, 0.0297938, 0.0354228, 0.0479256" \ ); } } @@ -10986,11 +11010,12 @@ library (sg13g2_stdcell_slow_1p35V_125C) { max_transition : 2.5074; capacitance : 0.0014011; rise_capacitance : 0.00139241; - rise_capacitance_range (0.00139241, 0.00139241); + rise_capacitance_range (0.00130002, 0.0016323); fall_capacitance : 0.0014098; - fall_capacitance_range (0.0014098, 0.0014098); + fall_capacitance_range (0.0014098, 0.0017478); timing () { related_pin : "CLK"; + sdf_edges : both_edges; timing_type : hold_rising; rise_constraint (CONSTRAINT_4x4) { index_1 ("0.0186, 0.51636, 1.263, 2.5074"); @@ -11009,18 +11034,19 @@ library (sg13g2_stdcell_slow_1p35V_125C) { "-0.039123, 0.04967, 0.0987266, 0.152979", \ "-0.184445, -0.101858, -0.0488588, 0.0088447", \ "-0.294182, -0.223872, -0.178092, -0.120182", \ - "-0.406625, -0.355219, -0.317686, -0.26859" \ + "-0.409323, -0.355219, -0.317686, -0.26859" \ ); } } timing () { related_pin : "CLK"; + sdf_edges : both_edges; timing_type : setup_rising; rise_constraint (CONSTRAINT_4x4) { index_1 ("0.0186, 0.51636, 1.263, 2.5074"); index_2 ("0.0186, 0.51636, 1.263, 2.5074"); values ( \ - "0.107588, 0.050163, 0.0272905, 0.00622484", \ + "0.107588, 0.050163, 0.0272905, 0.00352648", \ "0.24684, 0.178252, 0.151133, 0.123107", \ "0.33533, 0.257963, 0.229361, 0.199281", \ "0.425513, 0.346972, 0.314861, 0.289251" \ @@ -11042,13 +11068,13 @@ library (sg13g2_stdcell_slow_1p35V_125C) { rise_power (passive_POWER_7x1ds1) { index_1 ("0.0186, 0.0966, 0.174, 0.3294, 0.6408, 1.263, 2.5074"); values ( \ - "0.00213132, 0.00207656, 0.00220151, 0.0025828, 0.00348265, 0.00542912, 0.00960377" \ + "0.00213104, 0.00207657, 0.00220152, 0.00258281, 0.00348266, 0.00542914, 0.00960379" \ ); } fall_power (passive_POWER_7x1ds1) { index_1 ("0.0186, 0.0966, 0.174, 0.3294, 0.6408, 1.263, 2.5074"); values ( \ - "0.00158225, 0.00153153, 0.00167693, 0.00207607, 0.00301846, 0.00504861, 0.00935986" \ + "0.0015821, 0.00153153, 0.00167693, 0.00207607, 0.00301846, 0.00504861, 0.00935986" \ ); } } @@ -11057,13 +11083,13 @@ library (sg13g2_stdcell_slow_1p35V_125C) { rise_power (passive_POWER_7x1ds1) { index_1 ("0.0186, 0.0966, 0.174, 0.3294, 0.6408, 1.263, 2.5074"); values ( \ - "0.0148756, 0.0148242, 0.0149707, 0.0153253, 0.0161928, 0.0183908, 0.0230849" \ + "0.0148756, 0.0148242, 0.0149707, 0.0153253, 0.0161928, 0.0183907, 0.023085" \ ); } fall_power (passive_POWER_7x1ds1) { index_1 ("0.0186, 0.0966, 0.174, 0.3294, 0.6408, 1.263, 2.5074"); values ( \ - "0.0113699, 0.0112881, 0.0114009, 0.0118169, 0.0129365, 0.0151883, 0.0203547" \ + "0.0113699, 0.0112881, 0.0114009, 0.0118168, 0.0129365, 0.0151883, 0.0203547" \ ); } } @@ -11072,13 +11098,13 @@ library (sg13g2_stdcell_slow_1p35V_125C) { rise_power (passive_POWER_7x1ds1) { index_1 ("0.0186, 0.0966, 0.174, 0.3294, 0.6408, 1.263, 2.5074"); values ( \ - "-0.000106095, -0.000103199, -0.00010355, -0.000101296, -0.000100231, -9.87344e-05, -9.9358e-05" \ + "-0.000105888, -0.000103411, -0.00010355, -0.000101296, -0.000100231, -9.87344e-05, -9.9358e-05" \ ); } fall_power (passive_POWER_7x1ds1) { index_1 ("0.0186, 0.0966, 0.174, 0.3294, 0.6408, 1.263, 2.5074"); values ( \ - "0.000122662, 0.000129056, 0.000128655, 0.000125366, 0.000129461, 0.000129805, 0.000131103" \ + "0.000122653, 0.000129003, 0.000128645, 0.000125364, 0.000129458, 0.000129795, 0.0001311" \ ); } } @@ -11086,13 +11112,13 @@ library (sg13g2_stdcell_slow_1p35V_125C) { rise_power (passive_POWER_7x1ds1) { index_1 ("0.0186, 0.0966, 0.174, 0.3294, 0.6408, 1.263, 2.5074"); values ( \ - "0.00213132, 0.00207656, 0.00220151, 0.0025828, 0.00348265, 0.00542912, 0.00960377" \ + "0.00213104, 0.00207657, 0.00220152, 0.00258281, 0.00348266, 0.00542914, 0.00960379" \ ); } fall_power (passive_POWER_7x1ds1) { index_1 ("0.0186, 0.0966, 0.174, 0.3294, 0.6408, 1.263, 2.5074"); values ( \ - "0.00158225, 0.00153153, 0.00167693, 0.00207607, 0.00301846, 0.00504861, 0.00935986" \ + "0.0015821, 0.00153153, 0.00167693, 0.00207607, 0.00301846, 0.00504861, 0.00935986" \ ); } } @@ -11102,11 +11128,12 @@ library (sg13g2_stdcell_slow_1p35V_125C) { max_transition : 2.5074; capacitance : 0.00501563; rise_capacitance : 0.00498884; - rise_capacitance_range (0.00498884, 0.00498884); + rise_capacitance_range (0.00443363, 0.00551379); fall_capacitance : 0.00503795; - fall_capacitance_range (0.00503795, 0.00503795); + fall_capacitance_range (0.00468869, 0.0052392); timing () { related_pin : "CLK"; + sdf_edges : both_edges; timing_type : recovery_rising; rise_constraint (CONSTRAINT_4x4) { index_1 ("0.0186, 0.51636, 1.263, 2.5074"); @@ -11121,6 +11148,7 @@ library (sg13g2_stdcell_slow_1p35V_125C) { } timing () { related_pin : "CLK"; + sdf_edges : both_edges; timing_type : removal_rising; rise_constraint (CONSTRAINT_4x4) { index_1 ("0.0186, 0.51636, 1.263, 2.5074"); @@ -11148,13 +11176,13 @@ library (sg13g2_stdcell_slow_1p35V_125C) { rise_power (passive_POWER_7x1ds1) { index_1 ("0.0186, 0.0966, 0.174, 0.3294, 0.6408, 1.263, 2.5074"); values ( \ - "0.00435397, 0.00423134, 0.00426874, 0.00444429, 0.00515338, 0.00694705, 0.0107687" \ + "0.00435398, 0.00423135, 0.00426875, 0.0044443, 0.00515339, 0.00694706, 0.0107687" \ ); } fall_power (passive_POWER_7x1ds1) { index_1 ("0.0186, 0.0966, 0.174, 0.3294, 0.6408, 1.263, 2.5074"); values ( \ - "0.0363093, 0.0358109, 0.0359737, 0.0368241, 0.0392937, 0.0450381, 0.0568439" \ + "0.0363094, 0.035811, 0.0359737, 0.0368241, 0.0392937, 0.0450381, 0.0568439" \ ); } } @@ -11163,13 +11191,13 @@ library (sg13g2_stdcell_slow_1p35V_125C) { rise_power (passive_POWER_7x1ds1) { index_1 ("0.0186, 0.0966, 0.174, 0.3294, 0.6408, 1.263, 2.5074"); values ( \ - "0.0013971, 0.00138467, 0.00138012, 0.00138075, 0.00138989, 0.00138768, 0.00138875" \ + "0.00139099, 0.00138466, 0.00138114, 0.00138075, 0.00138989, 0.00138833, 0.00138875" \ ); } fall_power (passive_POWER_7x1ds1) { index_1 ("0.0186, 0.0966, 0.174, 0.3294, 0.6408, 1.263, 2.5074"); values ( \ - "-0.000846807, -0.00100919, -0.0010541, -0.00108446, -0.00111042, -0.00114103, -0.00116509" \ + "-0.000846799, -0.00100917, -0.00105409, -0.00108445, -0.00111042, -0.00114101, -0.00116508" \ ); } } @@ -11178,7 +11206,7 @@ library (sg13g2_stdcell_slow_1p35V_125C) { rise_power (passive_POWER_7x1ds1) { index_1 ("0.0186, 0.0966, 0.174, 0.3294, 0.6408, 1.263, 2.5074"); values ( \ - "0.0175106, 0.0172734, 0.0173173, 0.0176366, 0.0185712, 0.0212078, 0.0269495" \ + "0.0175104, 0.0172734, 0.0173173, 0.0176366, 0.0185712, 0.0212078, 0.0269495" \ ); } fall_power (passive_POWER_7x1ds1) { @@ -11193,13 +11221,13 @@ library (sg13g2_stdcell_slow_1p35V_125C) { rise_power (passive_POWER_7x1ds1) { index_1 ("0.0186, 0.0966, 0.174, 0.3294, 0.6408, 1.263, 2.5074"); values ( \ - "0.0013504, 0.00134616, 0.00134688, 0.00134637, 0.00135111, 0.00134902, 0.00134757" \ + "0.00135076, 0.00134615, 0.00134686, 0.00134635, 0.0013511, 0.00134901, 0.00134756" \ ); } fall_power (passive_POWER_7x1ds1) { index_1 ("0.0186, 0.0966, 0.174, 0.3294, 0.6408, 1.263, 2.5074"); values ( \ - "-0.00118149, -0.00129707, -0.00132918, -0.00134637, -0.00135111, -0.00134902, -0.00134757" \ + "-0.00117994, -0.00129708, -0.00132919, -0.00134635, -0.0013511, -0.00134901, -0.00134756" \ ); } } @@ -11207,7 +11235,7 @@ library (sg13g2_stdcell_slow_1p35V_125C) { rise_power (passive_POWER_7x1ds1) { index_1 ("0.0186, 0.0966, 0.174, 0.3294, 0.6408, 1.263, 2.5074"); values ( \ - "0.00435397, 0.00423134, 0.00426874, 0.00444429, 0.00515338, 0.00694705, 0.0107687" \ + "0.00435398, 0.00423135, 0.00426875, 0.0044443, 0.00515339, 0.00694706, 0.0107687" \ ); } fall_power (passive_POWER_7x1ds1) { @@ -11219,14 +11247,14 @@ library (sg13g2_stdcell_slow_1p35V_125C) { } } ff (IQ,IQN) { - clear : "RESET_B'"; + clear : "!RESET_B"; clocked_on : "CLK"; next_state : "D"; } } cell (sg13g2_dlhq_1) { area : 30.8448; - cell_footprint : "DLHQ"; + cell_footprint : "dlhq"; cell_leakage_power : 2682.43; leakage_power () { value : 2596.3; @@ -11316,6 +11344,7 @@ library (sg13g2_stdcell_slow_1p35V_125C) { } timing () { related_pin : "GATE"; + sdf_edges : start_edge; timing_sense : non_unate; timing_type : rising_edge; cell_rise (TIMING_DELAY_7x7ds1) { @@ -11435,11 +11464,12 @@ library (sg13g2_stdcell_slow_1p35V_125C) { max_transition : 2.5074; capacitance : 0.00226045; rise_capacitance : 0.00229486; - rise_capacitance_range (0.00229486, 0.00229486); + rise_capacitance_range (0.00204349, 0.00249532); fall_capacitance : 0.00222604; - fall_capacitance_range (0.00222604, 0.00222604); + fall_capacitance_range (0.00202544, 0.00241091); timing () { related_pin : "GATE"; + sdf_edges : both_edges; timing_type : hold_falling; rise_constraint (CONSTRAINT_4x4) { index_1 ("0.0186, 0.51636, 1.263, 2.5074"); @@ -11464,6 +11494,7 @@ library (sg13g2_stdcell_slow_1p35V_125C) { } timing () { related_pin : "GATE"; + sdf_edges : both_edges; timing_type : setup_falling; rise_constraint (CONSTRAINT_4x4) { index_1 ("0.0186, 0.51636, 1.263, 2.5074"); @@ -11537,9 +11568,9 @@ library (sg13g2_stdcell_slow_1p35V_125C) { max_transition : 2.5074; capacitance : 0.0022803; rise_capacitance : 0.00258464; - rise_capacitance_range (0.00258464, 0.00258464); + rise_capacitance_range (0.00227254, 0.00290849); fall_capacitance : 0.00167161; - fall_capacitance_range (0.00167161, 0.00167161); + fall_capacitance_range (0.00167161, 0.00266648); timing () { related_pin : "GATE"; timing_type : min_pulse_width; @@ -11587,7 +11618,7 @@ library (sg13g2_stdcell_slow_1p35V_125C) { } cell (sg13g2_dlhr_1) { area : 32.6592; - cell_footprint : "DLHR"; + cell_footprint : "dlhr"; cell_leakage_power : 3717.17; leakage_power () { value : 3241.39; @@ -11693,6 +11724,7 @@ library (sg13g2_stdcell_slow_1p35V_125C) { } timing () { related_pin : "GATE"; + sdf_edges : start_edge; timing_sense : non_unate; timing_type : rising_edge; cell_rise (TIMING_DELAY_7x7ds1) { @@ -11750,6 +11782,7 @@ library (sg13g2_stdcell_slow_1p35V_125C) { } timing () { related_pin : "RESET_B"; + sdf_edges : start_edge; timing_sense : positive_unate; timing_type : clear; cell_fall (TIMING_DELAY_7x7ds1) { @@ -11923,6 +11956,7 @@ library (sg13g2_stdcell_slow_1p35V_125C) { } timing () { related_pin : "GATE"; + sdf_edges : start_edge; timing_sense : non_unate; timing_type : rising_edge; cell_rise (TIMING_DELAY_7x7ds1) { @@ -11980,6 +12014,7 @@ library (sg13g2_stdcell_slow_1p35V_125C) { } timing () { related_pin : "RESET_B"; + sdf_edges : start_edge; timing_sense : negative_unate; timing_type : preset; cell_rise (TIMING_DELAY_7x7ds1) { @@ -12094,11 +12129,12 @@ library (sg13g2_stdcell_slow_1p35V_125C) { max_transition : 2.5074; capacitance : 0.0020589; rise_capacitance : 0.00224092; - rise_capacitance_range (0.00224092, 0.00224092); + rise_capacitance_range (0.00198021, 0.00244345); fall_capacitance : 0.00187689; - fall_capacitance_range (0.00187689, 0.00187689); + fall_capacitance_range (0.00187689, 0.00235797); timing () { related_pin : "GATE"; + sdf_edges : both_edges; timing_type : hold_falling; rise_constraint (CONSTRAINT_4x4) { index_1 ("0.0186, 0.51636, 1.263, 2.5074"); @@ -12123,6 +12159,7 @@ library (sg13g2_stdcell_slow_1p35V_125C) { } timing () { related_pin : "GATE"; + sdf_edges : both_edges; timing_type : setup_falling; rise_constraint (CONSTRAINT_4x4) { index_1 ("0.0186, 0.51636, 1.263, 2.5074"); @@ -12196,9 +12233,9 @@ library (sg13g2_stdcell_slow_1p35V_125C) { max_transition : 2.5074; capacitance : 0.00223524; rise_capacitance : 0.00256611; - rise_capacitance_range (0.00256611, 0.00256611); + rise_capacitance_range (0.00225999, 0.00288572); fall_capacitance : 0.00165622; - fall_capacitance_range (0.00165622, 0.00165622); + fall_capacitance_range (0.00165622, 0.00265043); timing () { related_pin : "GATE"; timing_type : min_pulse_width; @@ -12273,11 +12310,12 @@ library (sg13g2_stdcell_slow_1p35V_125C) { max_transition : 2.5074; capacitance : 0.00304148; rise_capacitance : 0.00313419; - rise_capacitance_range (0.00313419, 0.00313419); + rise_capacitance_range (0.00277909, 0.00331331); fall_capacitance : 0.00298585; - fall_capacitance_range (0.00298585, 0.00298585); + fall_capacitance_range (0.00276772, 0.00316512); timing () { related_pin : "GATE"; + sdf_edges : both_edges; timing_type : recovery_falling; rise_constraint (CONSTRAINT_4x4) { index_1 ("0.0186, 0.51636, 1.263, 2.5074"); @@ -12292,6 +12330,7 @@ library (sg13g2_stdcell_slow_1p35V_125C) { } timing () { related_pin : "GATE"; + sdf_edges : both_edges; timing_type : removal_falling; rise_constraint (CONSTRAINT_4x4) { index_1 ("0.0186, 0.51636, 1.263, 2.5074"); @@ -12360,14 +12399,14 @@ library (sg13g2_stdcell_slow_1p35V_125C) { } } latch (IQ,IQN) { - clear : "RESET_B'"; + clear : "!RESET_B"; data_in : "D"; enable : "GATE"; } } cell (sg13g2_dlhrq_1) { area : 27.216; - cell_footprint : "DLHRQ"; + cell_footprint : "dlhrq"; cell_leakage_power : 2911.1; leakage_power () { value : 2461.77; @@ -12473,6 +12512,7 @@ library (sg13g2_stdcell_slow_1p35V_125C) { } timing () { related_pin : "GATE"; + sdf_edges : start_edge; timing_sense : non_unate; timing_type : rising_edge; cell_rise (TIMING_DELAY_7x7ds1) { @@ -12530,6 +12570,7 @@ library (sg13g2_stdcell_slow_1p35V_125C) { } timing () { related_pin : "RESET_B"; + sdf_edges : start_edge; timing_sense : positive_unate; timing_type : clear; cell_fall (TIMING_DELAY_7x7ds1) { @@ -12644,11 +12685,12 @@ library (sg13g2_stdcell_slow_1p35V_125C) { max_transition : 2.5074; capacitance : 0.00211075; rise_capacitance : 0.00233059; - rise_capacitance_range (0.00233059, 0.00233059); + rise_capacitance_range (0.0020716, 0.00253274); fall_capacitance : 0.00189091; - fall_capacitance_range (0.00189091, 0.00189091); + fall_capacitance_range (0.00189091, 0.00244363); timing () { related_pin : "GATE"; + sdf_edges : both_edges; timing_type : hold_falling; rise_constraint (CONSTRAINT_4x4) { index_1 ("0.0186, 0.51636, 1.263, 2.5074"); @@ -12673,6 +12715,7 @@ library (sg13g2_stdcell_slow_1p35V_125C) { } timing () { related_pin : "GATE"; + sdf_edges : both_edges; timing_type : setup_falling; rise_constraint (CONSTRAINT_4x4) { index_1 ("0.0186, 0.51636, 1.263, 2.5074"); @@ -12746,9 +12789,9 @@ library (sg13g2_stdcell_slow_1p35V_125C) { max_transition : 2.5074; capacitance : 0.0021829; rise_capacitance : 0.00258846; - rise_capacitance_range (0.00258846, 0.00258846); + rise_capacitance_range (0.00228563, 0.00290443); fall_capacitance : 0.00167594; - fall_capacitance_range (0.00167594, 0.00167594); + fall_capacitance_range (0.00167594, 0.00267394); timing () { related_pin : "GATE"; timing_type : min_pulse_width; @@ -12823,11 +12866,12 @@ library (sg13g2_stdcell_slow_1p35V_125C) { max_transition : 2.5074; capacitance : 0.00287657; rise_capacitance : 0.00293662; - rise_capacitance_range (0.00293662, 0.00293662); + rise_capacitance_range (0.00258302, 0.00311894); fall_capacitance : 0.00283154; - fall_capacitance_range (0.00283154, 0.00283154); + fall_capacitance_range (0.00261891, 0.00298981); timing () { related_pin : "GATE"; + sdf_edges : both_edges; timing_type : recovery_falling; rise_constraint (CONSTRAINT_4x4) { index_1 ("0.0186, 0.51636, 1.263, 2.5074"); @@ -12842,6 +12886,7 @@ library (sg13g2_stdcell_slow_1p35V_125C) { } timing () { related_pin : "GATE"; + sdf_edges : both_edges; timing_type : removal_falling; rise_constraint (CONSTRAINT_4x4) { index_1 ("0.0186, 0.51636, 1.263, 2.5074"); @@ -12910,14 +12955,14 @@ library (sg13g2_stdcell_slow_1p35V_125C) { } } latch (IQ,IQN) { - clear : "RESET_B'"; + clear : "!RESET_B"; data_in : "D"; enable : "GATE"; } } cell (sg13g2_dllr_1) { area : 34.4736; - cell_footprint : "DLLR"; + cell_footprint : "dllr"; cell_leakage_power : 3809.48; leakage_power () { value : 3573.21; @@ -13039,6 +13084,7 @@ library (sg13g2_stdcell_slow_1p35V_125C) { } timing () { related_pin : "GATE_N"; + sdf_edges : start_edge; timing_sense : non_unate; timing_type : falling_edge; cell_rise (TIMING_DELAY_7x7ds1) { @@ -13096,6 +13142,7 @@ library (sg13g2_stdcell_slow_1p35V_125C) { } timing () { related_pin : "RESET_B"; + sdf_edges : start_edge; timing_sense : positive_unate; timing_type : clear; cell_fall (TIMING_DELAY_7x7ds1) { @@ -13269,6 +13316,7 @@ library (sg13g2_stdcell_slow_1p35V_125C) { } timing () { related_pin : "GATE_N"; + sdf_edges : start_edge; timing_sense : non_unate; timing_type : falling_edge; cell_rise (TIMING_DELAY_7x7ds1) { @@ -13326,6 +13374,7 @@ library (sg13g2_stdcell_slow_1p35V_125C) { } timing () { related_pin : "RESET_B"; + sdf_edges : start_edge; timing_sense : negative_unate; timing_type : preset; cell_rise (TIMING_DELAY_7x7ds1) { @@ -13440,11 +13489,12 @@ library (sg13g2_stdcell_slow_1p35V_125C) { max_transition : 2.5074; capacitance : 0.00213088; rise_capacitance : 0.00231286; - rise_capacitance_range (0.00231286, 0.00231286); + rise_capacitance_range (0.0020514, 0.00251721); fall_capacitance : 0.00194889; - fall_capacitance_range (0.00194889, 0.00194889); + fall_capacitance_range (0.00194889, 0.00242889); timing () { related_pin : "GATE_N"; + sdf_edges : both_edges; timing_type : hold_rising; rise_constraint (CONSTRAINT_4x4) { index_1 ("0.0186, 0.51636, 1.263, 2.5074"); @@ -13469,6 +13519,7 @@ library (sg13g2_stdcell_slow_1p35V_125C) { } timing () { related_pin : "GATE_N"; + sdf_edges : both_edges; timing_type : setup_rising; rise_constraint (CONSTRAINT_4x4) { index_1 ("0.0186, 0.51636, 1.263, 2.5074"); @@ -13542,9 +13593,9 @@ library (sg13g2_stdcell_slow_1p35V_125C) { max_transition : 2.5074; capacitance : 0.00228726; rise_capacitance : 0.0017735; - rise_capacitance_range (0.0017735, 0.0017735); + rise_capacitance_range (0.0017735, 0.00294853); fall_capacitance : 0.00258084; - fall_capacitance_range (0.00258084, 0.00258084); + fall_capacitance_range (0.00239894, 0.00271464); timing () { related_pin : "GATE_N"; timing_type : min_pulse_width; @@ -13619,11 +13670,12 @@ library (sg13g2_stdcell_slow_1p35V_125C) { max_transition : 2.5074; capacitance : 0.00300387; rise_capacitance : 0.00309882; - rise_capacitance_range (0.00309882, 0.00309882); + rise_capacitance_range (0.00274271, 0.00328213); fall_capacitance : 0.00294689; - fall_capacitance_range (0.00294689, 0.00294689); + fall_capacitance_range (0.00272795, 0.00312719); timing () { related_pin : "GATE_N"; + sdf_edges : both_edges; timing_type : recovery_rising; rise_constraint (CONSTRAINT_4x4) { index_1 ("0.0186, 0.51636, 1.263, 2.5074"); @@ -13638,6 +13690,7 @@ library (sg13g2_stdcell_slow_1p35V_125C) { } timing () { related_pin : "GATE_N"; + sdf_edges : both_edges; timing_type : removal_rising; rise_constraint (CONSTRAINT_4x4) { index_1 ("0.0186, 0.51636, 1.263, 2.5074"); @@ -13706,14 +13759,14 @@ library (sg13g2_stdcell_slow_1p35V_125C) { } } latch (IQ,IQN) { - clear : "RESET_B'"; + clear : "!RESET_B"; data_in : "D"; - enable : "GATE_N'"; + enable : "!GATE_N"; } } cell (sg13g2_dllrq_1) { area : 29.0304; - cell_footprint : "DLLRQ"; + cell_footprint : "dllrq"; cell_leakage_power : 2910.99; leakage_power () { value : 2793.54; @@ -13819,6 +13872,7 @@ library (sg13g2_stdcell_slow_1p35V_125C) { } timing () { related_pin : "GATE_N"; + sdf_edges : start_edge; timing_sense : non_unate; timing_type : falling_edge; cell_rise (TIMING_DELAY_7x7ds1) { @@ -13876,6 +13930,7 @@ library (sg13g2_stdcell_slow_1p35V_125C) { } timing () { related_pin : "RESET_B"; + sdf_edges : start_edge; timing_sense : positive_unate; timing_type : clear; cell_fall (TIMING_DELAY_7x7ds1) { @@ -13907,6 +13962,7 @@ library (sg13g2_stdcell_slow_1p35V_125C) { } timing () { related_pin : "RESET_B"; + sdf_edges : start_edge; timing_sense : positive_unate; timing_type : preset; cell_rise (TIMING_DELAY_7x7ds1) { @@ -14029,11 +14085,12 @@ library (sg13g2_stdcell_slow_1p35V_125C) { max_transition : 2.5074; capacitance : 0.00202299; rise_capacitance : 0.00224083; - rise_capacitance_range (0.00224083, 0.00224083); + rise_capacitance_range (0.00198057, 0.00244224); fall_capacitance : 0.00180516; - fall_capacitance_range (0.00180516, 0.00180516); + fall_capacitance_range (0.00180516, 0.00235511); timing () { related_pin : "GATE_N"; + sdf_edges : both_edges; timing_type : hold_rising; rise_constraint (CONSTRAINT_4x4) { index_1 ("0.0186, 0.51636, 1.263, 2.5074"); @@ -14058,6 +14115,7 @@ library (sg13g2_stdcell_slow_1p35V_125C) { } timing () { related_pin : "GATE_N"; + sdf_edges : both_edges; timing_type : setup_rising; rise_constraint (CONSTRAINT_4x4) { index_1 ("0.0186, 0.51636, 1.263, 2.5074"); @@ -14131,9 +14189,9 @@ library (sg13g2_stdcell_slow_1p35V_125C) { max_transition : 2.5074; capacitance : 0.00215466; rise_capacitance : 0.00257224; - rise_capacitance_range (0.00257224, 0.00257224); + rise_capacitance_range (0.00226425, 0.00289308); fall_capacitance : 0.00194587; - fall_capacitance_range (0.00194587, 0.00194587); + fall_capacitance_range (0.00194587, 0.00265852); timing () { related_pin : "GATE_N"; timing_type : min_pulse_width; @@ -14208,11 +14266,12 @@ library (sg13g2_stdcell_slow_1p35V_125C) { max_transition : 2.5074; capacitance : 0.00290701; rise_capacitance : 0.00299666; - rise_capacitance_range (0.00299666, 0.00299666); + rise_capacitance_range (0.00253421, 0.00331094); fall_capacitance : 0.00281737; - fall_capacitance_range (0.00281737, 0.00281737); + fall_capacitance_range (0.00260234, 0.00297499); timing () { related_pin : "GATE_N"; + sdf_edges : both_edges; timing_type : recovery_rising; rise_constraint (CONSTRAINT_4x4) { index_1 ("0.0186, 0.51636, 1.263, 2.5074"); @@ -14227,6 +14286,7 @@ library (sg13g2_stdcell_slow_1p35V_125C) { } timing () { related_pin : "GATE_N"; + sdf_edges : both_edges; timing_type : removal_rising; rise_constraint (CONSTRAINT_4x4) { index_1 ("0.0186, 0.51636, 1.263, 2.5074"); @@ -14295,14 +14355,14 @@ library (sg13g2_stdcell_slow_1p35V_125C) { } } latch (IQ,IQN) { - clear : "RESET_B'"; + clear : "!RESET_B"; data_in : "D"; - enable : "GATE_N'"; + enable : "!GATE_N"; } } cell (sg13g2_dlygate4sd1_1) { area : 14.5152; - cell_footprint : "DLY1"; + cell_footprint : "dlygate4sd1"; cell_leakage_power : 1439.16; leakage_power () { value : 1627.55; @@ -14409,14 +14469,14 @@ library (sg13g2_stdcell_slow_1p35V_125C) { max_transition : 2.5074; capacitance : 0.00147529; rise_capacitance : 0.00147667; - rise_capacitance_range (0.00147667, 0.00147667); + rise_capacitance_range (0.00130451, 0.00165791); fall_capacitance : 0.00147391; - fall_capacitance_range (0.00147391, 0.00147391); + fall_capacitance_range (0.00138187, 0.00153609); } } cell (sg13g2_dlygate4sd2_1) { area : 14.5152; - cell_footprint : "DLY2"; + cell_footprint : "dlygate4sd2"; cell_leakage_power : 1459.32; leakage_power () { value : 1647.7; @@ -14523,14 +14583,14 @@ library (sg13g2_stdcell_slow_1p35V_125C) { max_transition : 2.5074; capacitance : 0.0014694; rise_capacitance : 0.00146848; - rise_capacitance_range (0.00146848, 0.00146848); + rise_capacitance_range (0.0013144, 0.00163462); fall_capacitance : 0.00147031; - fall_capacitance_range (0.00147031, 0.00147031); + fall_capacitance_range (0.00139175, 0.00152747); } } cell (sg13g2_dlygate4sd3_1) { area : 16.3296; - cell_footprint : "DLY4"; + cell_footprint : "dlygate4sd3"; cell_leakage_power : 2742.91; leakage_power () { value : 2931.3; @@ -14637,14 +14697,14 @@ library (sg13g2_stdcell_slow_1p35V_125C) { max_transition : 2.5074; capacitance : 0.00148353; rise_capacitance : 0.00147481; - rise_capacitance_range (0.00147481, 0.00147481); + rise_capacitance_range (0.00135986, 0.00161054); fall_capacitance : 0.00149226; - fall_capacitance_range (0.00149226, 0.00149226); + fall_capacitance_range (0.00143023, 0.00154251); } } cell (sg13g2_ebufn_2) { area : 18.144; - cell_footprint : "BTL"; + cell_footprint : "ebufn"; cell_leakage_power : 1486.29; leakage_power () { value : 1479.5; @@ -14732,6 +14792,7 @@ library (sg13g2_stdcell_slow_1p35V_125C) { } timing () { related_pin : "TE_B"; + sdf_edges : start_edge; timing_sense : positive_unate; timing_type : three_state_disable; cell_rise (TIMING_DELAY_7x7ds1) { @@ -14789,6 +14850,7 @@ library (sg13g2_stdcell_slow_1p35V_125C) { } timing () { related_pin : "TE_B"; + sdf_edges : start_edge; timing_sense : negative_unate; timing_type : three_state_enable; cell_rise (TIMING_DELAY_7x7ds1) { @@ -14908,9 +14970,9 @@ library (sg13g2_stdcell_slow_1p35V_125C) { max_transition : 2.5074; capacitance : 0.0025864; rise_capacitance : 0.00263288; - rise_capacitance_range (0.00263288, 0.00263288); + rise_capacitance_range (0.00232847, 0.002884); fall_capacitance : 0.00253993; - fall_capacitance_range (0.00253993, 0.00253993); + fall_capacitance_range (0.00230391, 0.00277243); internal_power () { rise_power (passive_POWER_7x1ds1) { index_1 ("0.0186, 0.0966, 0.174, 0.3294, 0.6408, 1.263, 2.5074"); @@ -14931,9 +14993,9 @@ library (sg13g2_stdcell_slow_1p35V_125C) { max_transition : 2.5074; capacitance : 0.00612185; rise_capacitance : 0.00641128; - rise_capacitance_range (0.00641128, 0.00641128); + rise_capacitance_range (0.0046877, 0.00759473); fall_capacitance : 0.00583243; - fall_capacitance_range (0.00583243, 0.00583243); + fall_capacitance_range (0.00466384, 0.00754209); internal_power () { rise_power (passive_POWER_7x1ds1) { index_1 ("0.0186, 0.0966, 0.174, 0.3294, 0.6408, 1.263, 2.5074"); @@ -14952,7 +15014,7 @@ library (sg13g2_stdcell_slow_1p35V_125C) { } cell (sg13g2_ebufn_4) { area : 27.216; - cell_footprint : "BTL"; + cell_footprint : "ebufn"; cell_leakage_power : 2240.96; leakage_power () { value : 1765.52; @@ -15040,6 +15102,7 @@ library (sg13g2_stdcell_slow_1p35V_125C) { } timing () { related_pin : "TE_B"; + sdf_edges : start_edge; timing_sense : positive_unate; timing_type : three_state_disable; cell_rise (TIMING_DELAY_7x7ds1) { @@ -15097,6 +15160,7 @@ library (sg13g2_stdcell_slow_1p35V_125C) { } timing () { related_pin : "TE_B"; + sdf_edges : start_edge; timing_sense : negative_unate; timing_type : three_state_enable; cell_rise (TIMING_DELAY_7x7ds1) { @@ -15216,9 +15280,9 @@ library (sg13g2_stdcell_slow_1p35V_125C) { max_transition : 2.5074; capacitance : 0.00292051; rise_capacitance : 0.00297514; - rise_capacitance_range (0.00297514, 0.00297514); + rise_capacitance_range (0.00267539, 0.00324843); fall_capacitance : 0.00286588; - fall_capacitance_range (0.00286588, 0.00286588); + fall_capacitance_range (0.00264244, 0.00308415); internal_power () { rise_power (passive_POWER_7x1ds1) { index_1 ("0.0186, 0.0966, 0.174, 0.3294, 0.6408, 1.263, 2.5074"); @@ -15239,9 +15303,9 @@ library (sg13g2_stdcell_slow_1p35V_125C) { max_transition : 2.5074; capacitance : 0.009943; rise_capacitance : 0.0104956; - rise_capacitance_range (0.0104956, 0.0104956); + rise_capacitance_range (0.00725939, 0.0126822); fall_capacitance : 0.00939036; - fall_capacitance_range (0.00939036, 0.00939036); + fall_capacitance_range (0.00722233, 0.0126114); internal_power () { rise_power (passive_POWER_7x1ds1) { index_1 ("0.0186, 0.0966, 0.174, 0.3294, 0.6408, 1.263, 2.5074"); @@ -15260,7 +15324,7 @@ library (sg13g2_stdcell_slow_1p35V_125C) { } cell (sg13g2_ebufn_8) { area : 45.36; - cell_footprint : "BTL"; + cell_footprint : "ebufn"; cell_leakage_power : 3998.34; leakage_power () { value : 2770.18; @@ -15348,6 +15412,7 @@ library (sg13g2_stdcell_slow_1p35V_125C) { } timing () { related_pin : "TE_B"; + sdf_edges : start_edge; timing_sense : positive_unate; timing_type : three_state_disable; cell_rise (TIMING_DELAY_7x7ds1) { @@ -15405,6 +15470,7 @@ library (sg13g2_stdcell_slow_1p35V_125C) { } timing () { related_pin : "TE_B"; + sdf_edges : start_edge; timing_sense : negative_unate; timing_type : three_state_enable; cell_rise (TIMING_DELAY_7x7ds1) { @@ -15524,9 +15590,9 @@ library (sg13g2_stdcell_slow_1p35V_125C) { max_transition : 2.5074; capacitance : 0.0056978; rise_capacitance : 0.00580872; - rise_capacitance_range (0.00580872, 0.00580872); + rise_capacitance_range (0.00517073, 0.00636887); fall_capacitance : 0.00558688; - fall_capacitance_range (0.00558688, 0.00558688); + fall_capacitance_range (0.00511766, 0.00604008); internal_power () { rise_power (passive_POWER_7x1ds1) { index_1 ("0.0186, 0.0966, 0.174, 0.3294, 0.6408, 1.263, 2.5074"); @@ -15547,9 +15613,9 @@ library (sg13g2_stdcell_slow_1p35V_125C) { max_transition : 2.5074; capacitance : 0.016568; rise_capacitance : 0.0176246; - rise_capacitance_range (0.0176246, 0.0176246); + rise_capacitance_range (0.0111459, 0.0219895); fall_capacitance : 0.0155115; - fall_capacitance_range (0.0155115, 0.0155115); + fall_capacitance_range (0.0110637, 0.0219001); internal_power () { rise_power (passive_POWER_7x1ds1) { index_1 ("0.0186, 0.0966, 0.174, 0.3294, 0.6408, 1.263, 2.5074"); @@ -15568,7 +15634,7 @@ library (sg13g2_stdcell_slow_1p35V_125C) { } cell (sg13g2_einvn_2) { area : 16.3296; - cell_footprint : "einvin"; + cell_footprint : "einvn"; cell_leakage_power : 1149.3; leakage_power () { value : 594.24; @@ -15648,6 +15714,7 @@ library (sg13g2_stdcell_slow_1p35V_125C) { } timing () { related_pin : "TE_B"; + sdf_edges : start_edge; timing_sense : positive_unate; timing_type : three_state_disable_rise; cell_rise (TIMING_DELAY_7x7ds1) { @@ -15679,6 +15746,7 @@ library (sg13g2_stdcell_slow_1p35V_125C) { } timing () { related_pin : "TE_B"; + sdf_edges : start_edge; timing_sense : negative_unate; timing_type : three_state_enable_rise; cell_rise (TIMING_DELAY_7x7ds1) { @@ -15764,9 +15832,9 @@ library (sg13g2_stdcell_slow_1p35V_125C) { max_transition : 2.5074; capacitance : 0.00412225; rise_capacitance : 0.00425822; - rise_capacitance_range (0.00425822, 0.00425822); + rise_capacitance_range (0.00282478, 0.00686728); fall_capacitance : 0.00398628; - fall_capacitance_range (0.00398628, 0.00398628); + fall_capacitance_range (0.00248052, 0.00612966); internal_power () { rise_power (passive_POWER_7x1ds1) { index_1 ("0.0186, 0.0966, 0.174, 0.3294, 0.6408, 1.263, 2.5074"); @@ -15787,9 +15855,9 @@ library (sg13g2_stdcell_slow_1p35V_125C) { max_transition : 2.5074; capacitance : 0.00479549; rise_capacitance : 0.00540568; - rise_capacitance_range (0.00540568, 0.00540568); + rise_capacitance_range (0.00502707, 0.00561274); fall_capacitance : 0.00418529; - fall_capacitance_range (0.00418529, 0.00418529); + fall_capacitance_range (0.00309287, 0.0065908); internal_power () { rise_power (passive_POWER_7x1ds1) { index_1 ("0.0186, 0.0966, 0.174, 0.3294, 0.6408, 1.263, 2.5074"); @@ -15808,7 +15876,7 @@ library (sg13g2_stdcell_slow_1p35V_125C) { } cell (sg13g2_einvn_4) { area : 23.5872; - cell_footprint : "einvin"; + cell_footprint : "einvn"; cell_leakage_power : 2309.88; leakage_power () { value : 1199.74; @@ -15888,6 +15956,7 @@ library (sg13g2_stdcell_slow_1p35V_125C) { } timing () { related_pin : "TE_B"; + sdf_edges : start_edge; timing_sense : positive_unate; timing_type : three_state_disable_rise; cell_rise (TIMING_DELAY_7x7ds1) { @@ -15919,6 +15988,7 @@ library (sg13g2_stdcell_slow_1p35V_125C) { } timing () { related_pin : "TE_B"; + sdf_edges : start_edge; timing_sense : negative_unate; timing_type : three_state_enable_rise; cell_rise (TIMING_DELAY_7x7ds1) { @@ -16004,9 +16074,9 @@ library (sg13g2_stdcell_slow_1p35V_125C) { max_transition : 2.5074; capacitance : 0.00802136; rise_capacitance : 0.00828825; - rise_capacitance_range (0.00828825, 0.00828825); + rise_capacitance_range (0.00536574, 0.0136945); fall_capacitance : 0.00775447; - fall_capacitance_range (0.00775447, 0.00775447); + fall_capacitance_range (0.00470749, 0.0121591); internal_power () { rise_power (passive_POWER_7x1ds1) { index_1 ("0.0186, 0.0966, 0.174, 0.3294, 0.6408, 1.263, 2.5074"); @@ -16027,9 +16097,9 @@ library (sg13g2_stdcell_slow_1p35V_125C) { max_transition : 2.5074; capacitance : 0.00894257; rise_capacitance : 0.0100969; - rise_capacitance_range (0.0100969, 0.0100969); + rise_capacitance_range (0.00922883, 0.0105354); fall_capacitance : 0.00778826; - fall_capacitance_range (0.00778826, 0.00778826); + fall_capacitance_range (0.00565981, 0.0124613); internal_power () { rise_power (passive_POWER_7x1ds1) { index_1 ("0.0186, 0.0966, 0.174, 0.3294, 0.6408, 1.263, 2.5074"); @@ -16048,7 +16118,7 @@ library (sg13g2_stdcell_slow_1p35V_125C) { } cell (sg13g2_einvn_8) { area : 39.9168; - cell_footprint : "ITL"; + cell_footprint : "einvn"; cell_leakage_power : 4413.88; leakage_power () { value : 2193.61; @@ -16128,6 +16198,7 @@ library (sg13g2_stdcell_slow_1p35V_125C) { } timing () { related_pin : "TE_B"; + sdf_edges : start_edge; timing_sense : positive_unate; timing_type : three_state_disable_rise; cell_rise (TIMING_DELAY_7x7ds1) { @@ -16159,6 +16230,7 @@ library (sg13g2_stdcell_slow_1p35V_125C) { } timing () { related_pin : "TE_B"; + sdf_edges : start_edge; timing_sense : negative_unate; timing_type : three_state_enable_rise; cell_rise (TIMING_DELAY_7x7ds1) { @@ -16244,9 +16316,9 @@ library (sg13g2_stdcell_slow_1p35V_125C) { max_transition : 2.5074; capacitance : 0.0158604; rise_capacitance : 0.0163981; - rise_capacitance_range (0.0163981, 0.0163981); + rise_capacitance_range (0.010451, 0.0273774); fall_capacitance : 0.0153227; - fall_capacitance_range (0.0153227, 0.0153227); + fall_capacitance_range (0.00914165, 0.024269); internal_power () { rise_power (passive_POWER_7x1ds1) { index_1 ("0.0186, 0.0966, 0.174, 0.3294, 0.6408, 1.263, 2.5074"); @@ -16267,9 +16339,9 @@ library (sg13g2_stdcell_slow_1p35V_125C) { max_transition : 2.5074; capacitance : 0.0153189; rise_capacitance : 0.0170621; - rise_capacitance_range (0.0170621, 0.0170621); + rise_capacitance_range (0.0148426, 0.0178372); fall_capacitance : 0.0135757; - fall_capacitance_range (0.0135757, 0.0135757); + fall_capacitance_range (0.0103826, 0.0218209); internal_power () { rise_power (passive_POWER_7x1ds1) { index_1 ("0.0186, 0.0966, 0.174, 0.3294, 0.6408, 1.263, 2.5074"); @@ -16320,7 +16392,7 @@ library (sg13g2_stdcell_slow_1p35V_125C) { } cell (sg13g2_inv_1) { area : 5.4432; - cell_footprint : "IN"; + cell_footprint : "inv"; cell_leakage_power : 483.362; leakage_power () { value : 760.856; @@ -16427,14 +16499,14 @@ library (sg13g2_stdcell_slow_1p35V_125C) { max_transition : 2.5074; capacitance : 0.00280948; rise_capacitance : 0.00285879; - rise_capacitance_range (0.00285879, 0.00285879); + rise_capacitance_range (0.00252316, 0.00334029); fall_capacitance : 0.00276016; - fall_capacitance_range (0.00276016, 0.00276016); + fall_capacitance_range (0.00253687, 0.00317569); } } cell (sg13g2_inv_16) { area : 34.4736; - cell_footprint : "IN"; + cell_footprint : "inv"; cell_leakage_power : 7731.68; leakage_power () { value : 12172.3; @@ -16541,14 +16613,14 @@ library (sg13g2_stdcell_slow_1p35V_125C) { max_transition : 2.5074; capacitance : 0.0426729; rise_capacitance : 0.0434025; - rise_capacitance_range (0.0434025, 0.0434025); + rise_capacitance_range (0.0321698, 0.0534186); fall_capacitance : 0.0419432; - fall_capacitance_range (0.0419432, 0.0419432); + fall_capacitance_range (0.0329646, 0.0508759); } } cell (sg13g2_inv_2) { area : 7.2576; - cell_footprint : "IN"; + cell_footprint : "inv"; cell_leakage_power : 966.47; leakage_power () { value : 1521.55; @@ -16655,14 +16727,14 @@ library (sg13g2_stdcell_slow_1p35V_125C) { max_transition : 2.5074; capacitance : 0.0055606; rise_capacitance : 0.00565928; - rise_capacitance_range (0.00565928, 0.00565928); + rise_capacitance_range (0.00490332, 0.00674536); fall_capacitance : 0.00546193; - fall_capacitance_range (0.00546193, 0.00546193); + fall_capacitance_range (0.00495154, 0.00640593); } } cell (sg13g2_inv_4) { area : 10.8864; - cell_footprint : "IN"; + cell_footprint : "inv"; cell_leakage_power : 1932.92; leakage_power () { value : 3043.07; @@ -16769,14 +16841,14 @@ library (sg13g2_stdcell_slow_1p35V_125C) { max_transition : 2.5074; capacitance : 0.0109915; rise_capacitance : 0.0111884; - rise_capacitance_range (0.0111884, 0.0111884); + rise_capacitance_range (0.00966245, 0.013436); fall_capacitance : 0.0107946; - fall_capacitance_range (0.0107946, 0.0107946); + fall_capacitance_range (0.00978945, 0.0127794); } } cell (sg13g2_inv_8) { area : 18.144; - cell_footprint : "IN"; + cell_footprint : "inv"; cell_leakage_power : 3865.87; leakage_power () { value : 6086.21; @@ -16883,14 +16955,14 @@ library (sg13g2_stdcell_slow_1p35V_125C) { max_transition : 2.5074; capacitance : 0.0219908; rise_capacitance : 0.0223848; - rise_capacitance_range (0.0223848, 0.0223848); + rise_capacitance_range (0.0192024, 0.02699); fall_capacitance : 0.0215968; - fall_capacitance_range (0.0215968, 0.0215968); + fall_capacitance_range (0.0194592, 0.0256704); } } cell (sg13g2_lgcp_1) { area : 27.216; - cell_footprint : "gclk"; + cell_footprint : "lgcp"; cell_leakage_power : 2874.13; clock_gating_integrated_cell : "latch_posedge"; dont_use : true; @@ -17014,9 +17086,9 @@ library (sg13g2_stdcell_slow_1p35V_125C) { max_transition : 2.5074; capacitance : 0.00486489; rise_capacitance : 0.00492064; - rise_capacitance_range (0.00492064, 0.00492064); + rise_capacitance_range (0.00428164, 0.00558331); fall_capacitance : 0.00480914; - fall_capacitance_range (0.00480914, 0.00480914); + fall_capacitance_range (0.00443059, 0.0050878); timing () { related_pin : "CLK"; timing_type : min_pulse_width; @@ -17054,11 +17126,12 @@ library (sg13g2_stdcell_slow_1p35V_125C) { max_transition : 2.5074; capacitance : 0.00228664; rise_capacitance : 0.00246089; - rise_capacitance_range (0.00246089, 0.00246089); + rise_capacitance_range (0.00224353, 0.00262817); fall_capacitance : 0.00211239; - fall_capacitance_range (0.00211239, 0.00211239); + fall_capacitance_range (0.00211239, 0.00230395); timing () { related_pin : "CLK"; + sdf_edges : both_edges; timing_type : hold_rising; rise_constraint (CONSTRAINT_4x4) { index_1 ("0.0186, 0.51636, 1.263, 2.5074"); @@ -17083,6 +17156,7 @@ library (sg13g2_stdcell_slow_1p35V_125C) { } timing () { related_pin : "CLK"; + sdf_edges : both_edges; timing_type : setup_rising; rise_constraint (CONSTRAINT_4x4) { index_1 ("0.0186, 0.51636, 1.263, 2.5074"); @@ -17293,7 +17367,7 @@ library (sg13g2_stdcell_slow_1p35V_125C) { } timing () { related_pin : "S"; - sdf_cond : "A0 == 1'b0 & A1 == 1'b1"; + sdf_cond : "A0 == 1'b0 && A1 == 1'b1"; timing_sense : positive_unate; timing_type : combinational; when : "(!A0 * A1)"; @@ -17409,7 +17483,7 @@ library (sg13g2_stdcell_slow_1p35V_125C) { } timing () { related_pin : "S"; - sdf_cond : "A0 == 1'b1 & A1 == 1'b0"; + sdf_cond : "A0 == 1'b1 && A1 == 1'b0"; timing_sense : negative_unate; timing_type : combinational; when : "(A0 * !A1)"; @@ -17619,27 +17693,27 @@ library (sg13g2_stdcell_slow_1p35V_125C) { max_transition : 2.5074; capacitance : 0.00272944; rise_capacitance : 0.00277926; - rise_capacitance_range (0.00277926, 0.00277926); + rise_capacitance_range (0.00238821, 0.00311322); fall_capacitance : 0.00267962; - fall_capacitance_range (0.00267962, 0.00267962); + fall_capacitance_range (0.00236278, 0.00286467); } pin (A1) { direction : "input"; max_transition : 2.5074; capacitance : 0.00284812; rise_capacitance : 0.00291374; - rise_capacitance_range (0.00291374, 0.00291374); + rise_capacitance_range (0.00249811, 0.00327764); fall_capacitance : 0.00278249; - fall_capacitance_range (0.00278249, 0.00278249); + fall_capacitance_range (0.00246308, 0.00296754); } pin (S) { direction : "input"; max_transition : 2.5074; capacitance : 0.00497888; rise_capacitance : 0.00505186; - rise_capacitance_range (0.00505186, 0.00505186); + rise_capacitance_range (0.00426969, 0.0059195); fall_capacitance : 0.00490589; - fall_capacitance_range (0.00490589, 0.00490589); + fall_capacitance_range (0.0042822, 0.00583903); internal_power () { when : "(A0 * A1)"; rise_power (passive_POWER_7x1ds1) { @@ -17843,7 +17917,7 @@ library (sg13g2_stdcell_slow_1p35V_125C) { } timing () { related_pin : "S"; - sdf_cond : "A0 == 1'b0 & A1 == 1'b1"; + sdf_cond : "A0 == 1'b0 && A1 == 1'b1"; timing_sense : positive_unate; timing_type : combinational; when : "(!A0 * A1)"; @@ -17959,7 +18033,7 @@ library (sg13g2_stdcell_slow_1p35V_125C) { } timing () { related_pin : "S"; - sdf_cond : "A0 == 1'b1 & A1 == 1'b0"; + sdf_cond : "A0 == 1'b1 && A1 == 1'b0"; timing_sense : negative_unate; timing_type : combinational; when : "(A0 * !A1)"; @@ -18169,27 +18243,27 @@ library (sg13g2_stdcell_slow_1p35V_125C) { max_transition : 2.5074; capacitance : 0.00272955; rise_capacitance : 0.0027862; - rise_capacitance_range (0.0027862, 0.0027862); + rise_capacitance_range (0.00243495, 0.00310821); fall_capacitance : 0.0026729; - fall_capacitance_range (0.0026729, 0.0026729); + fall_capacitance_range (0.00240555, 0.00284143); } pin (A1) { direction : "input"; max_transition : 2.5074; capacitance : 0.00283369; rise_capacitance : 0.00288918; - rise_capacitance_range (0.00288918, 0.00288918); + rise_capacitance_range (0.00254145, 0.00321058); fall_capacitance : 0.0027782; - fall_capacitance_range (0.0027782, 0.0027782); + fall_capacitance_range (0.00253311, 0.00294373); } pin (S) { direction : "input"; max_transition : 2.5074; capacitance : 0.00497025; rise_capacitance : 0.0050428; - rise_capacitance_range (0.0050428, 0.0050428); + rise_capacitance_range (0.00426035, 0.00591376); fall_capacitance : 0.0048977; - fall_capacitance_range (0.0048977, 0.0048977); + fall_capacitance_range (0.00427615, 0.00583085); internal_power () { when : "(A0 * A1)"; rise_power (passive_POWER_7x1ds1) { @@ -18731,7 +18805,7 @@ library (sg13g2_stdcell_slow_1p35V_125C) { } timing () { related_pin : "S0"; - sdf_cond : "A2 == 1'b0 & A3 == 1'b1 & S1 == 1'b1"; + sdf_cond : "A2 == 1'b0 && A3 == 1'b1 && S1 == 1'b1"; timing_sense : positive_unate; timing_type : combinational; when : "(!A2 * A3 * S1)"; @@ -18790,7 +18864,7 @@ library (sg13g2_stdcell_slow_1p35V_125C) { } timing () { related_pin : "S0"; - sdf_cond : "A0 == 1'b0 & A1 == 1'b1 & S1 == 1'b0"; + sdf_cond : "A0 == 1'b0 && A1 == 1'b1 && S1 == 1'b0"; timing_sense : positive_unate; timing_type : combinational; when : "(!A0 * A1 * !S1)"; @@ -18906,7 +18980,7 @@ library (sg13g2_stdcell_slow_1p35V_125C) { } timing () { related_pin : "S0"; - sdf_cond : "A2 == 1'b1 & A3 == 1'b0 & S1 == 1'b1"; + sdf_cond : "A2 == 1'b1 && A3 == 1'b0 && S1 == 1'b1"; timing_sense : negative_unate; timing_type : combinational; when : "(A2 * !A3 * S1)"; @@ -18965,7 +19039,7 @@ library (sg13g2_stdcell_slow_1p35V_125C) { } timing () { related_pin : "S0"; - sdf_cond : "A0 == 1'b1 & A1 == 1'b0 & S1 == 1'b0"; + sdf_cond : "A0 == 1'b1 && A1 == 1'b0 && S1 == 1'b0"; timing_sense : negative_unate; timing_type : combinational; when : "(A0 * !A1 * !S1)"; @@ -19024,7 +19098,7 @@ library (sg13g2_stdcell_slow_1p35V_125C) { } timing () { related_pin : "S1"; - sdf_cond : "A1 == 1'b0 & A3 == 1'b1 & S0 == 1'b1"; + sdf_cond : "A1 == 1'b0 && A3 == 1'b1 && S0 == 1'b1"; timing_sense : positive_unate; timing_type : combinational; when : "(!A1 * A3 * S0)"; @@ -19083,7 +19157,7 @@ library (sg13g2_stdcell_slow_1p35V_125C) { } timing () { related_pin : "S1"; - sdf_cond : "A0 == 1'b0 & A2 == 1'b1 & S0 == 1'b0"; + sdf_cond : "A0 == 1'b0 && A2 == 1'b1 && S0 == 1'b0"; timing_sense : positive_unate; timing_type : combinational; when : "(!A0 * A2 * !S0)"; @@ -19199,7 +19273,7 @@ library (sg13g2_stdcell_slow_1p35V_125C) { } timing () { related_pin : "S1"; - sdf_cond : "A1 == 1'b1 & A3 == 1'b0 & S0 == 1'b1"; + sdf_cond : "A1 == 1'b1 && A3 == 1'b0 && S0 == 1'b1"; timing_sense : negative_unate; timing_type : combinational; when : "(A1 * !A3 * S0)"; @@ -19258,7 +19332,7 @@ library (sg13g2_stdcell_slow_1p35V_125C) { } timing () { related_pin : "S1"; - sdf_cond : "A0 == 1'b1 & A2 == 1'b0 & S0 == 1'b0"; + sdf_cond : "A0 == 1'b1 && A2 == 1'b0 && S0 == 1'b0"; timing_sense : negative_unate; timing_type : combinational; when : "(A0 * !A2 * !S0)"; @@ -19735,45 +19809,45 @@ library (sg13g2_stdcell_slow_1p35V_125C) { max_transition : 2.5074; capacitance : 0.00274785; rise_capacitance : 0.00278792; - rise_capacitance_range (0.00278792, 0.00278792); + rise_capacitance_range (0.00241452, 0.00301812); fall_capacitance : 0.00270779; - fall_capacitance_range (0.00270779, 0.00270779); + fall_capacitance_range (0.00237604, 0.00294177); } pin (A1) { direction : "input"; max_transition : 2.5074; capacitance : 0.00272834; rise_capacitance : 0.00276288; - rise_capacitance_range (0.00276288, 0.00276288); + rise_capacitance_range (0.00240822, 0.0030042); fall_capacitance : 0.00269379; - fall_capacitance_range (0.00269379, 0.00269379); + fall_capacitance_range (0.00232185, 0.00292742); } pin (A2) { direction : "input"; max_transition : 2.5074; capacitance : 0.00274988; rise_capacitance : 0.00278737; - rise_capacitance_range (0.00278737, 0.00278737); + rise_capacitance_range (0.00240348, 0.00301521); fall_capacitance : 0.00271239; - fall_capacitance_range (0.00271239, 0.00271239); + fall_capacitance_range (0.00235548, 0.00294393); } pin (A3) { direction : "input"; max_transition : 2.5074; capacitance : 0.00281191; rise_capacitance : 0.00284666; - rise_capacitance_range (0.00284666, 0.00284666); + rise_capacitance_range (0.00246127, 0.00307969); fall_capacitance : 0.00277717; - fall_capacitance_range (0.00277717, 0.00277717); + fall_capacitance_range (0.00239872, 0.00300812); } pin (S0) { direction : "input"; max_transition : 2.5074; capacitance : 0.0081614; rise_capacitance : 0.0097315; - rise_capacitance_range (0.0097315, 0.0097315); + rise_capacitance_range (0.0071098, 0.0112861); fall_capacitance : 0.0065913; - fall_capacitance_range (0.0065913, 0.0065913); + fall_capacitance_range (0.00414746, 0.00964417); internal_power () { when : "(A2 * A3 * S1)"; rise_power (passive_POWER_7x1ds1) { @@ -19854,9 +19928,9 @@ library (sg13g2_stdcell_slow_1p35V_125C) { max_transition : 2.5074; capacitance : 0.0049402; rise_capacitance : 0.00500874; - rise_capacitance_range (0.00500874, 0.00500874); + rise_capacitance_range (0.00413372, 0.00604326); fall_capacitance : 0.00487166; - fall_capacitance_range (0.00487166, 0.00487166); + fall_capacitance_range (0.00416619, 0.00565521); internal_power () { when : "(A1 * A3 * S0)"; rise_power (passive_POWER_7x1ds1) { @@ -20136,18 +20210,18 @@ library (sg13g2_stdcell_slow_1p35V_125C) { max_transition : 2.5074; capacitance : 0.00282287; rise_capacitance : 0.00285162; - rise_capacitance_range (0.00285162, 0.00285162); + rise_capacitance_range (0.00252945, 0.00319284); fall_capacitance : 0.00279412; - fall_capacitance_range (0.00279412, 0.00279412); + fall_capacitance_range (0.00244803, 0.00331798); } pin (B) { direction : "input"; max_transition : 2.5074; capacitance : 0.00293691; rise_capacitance : 0.00306913; - rise_capacitance_range (0.00306913, 0.00306913); + rise_capacitance_range (0.00260169, 0.00343209); fall_capacitance : 0.00280469; - fall_capacitance_range (0.00280469, 0.00280469); + fall_capacitance_range (0.00261851, 0.0031472); } } cell (sg13g2_nand2_2) { @@ -20353,23 +20427,23 @@ library (sg13g2_stdcell_slow_1p35V_125C) { max_transition : 2.5074; capacitance : 0.00546692; rise_capacitance : 0.00553157; - rise_capacitance_range (0.00553157, 0.00553157); + rise_capacitance_range (0.00484321, 0.00620942); fall_capacitance : 0.00540228; - fall_capacitance_range (0.00540228, 0.00540228); + fall_capacitance_range (0.00465446, 0.00659647); } pin (B) { direction : "input"; max_transition : 2.5074; capacitance : 0.00563036; rise_capacitance : 0.00589502; - rise_capacitance_range (0.00589502, 0.00589502); + rise_capacitance_range (0.00497832, 0.00662146); fall_capacitance : 0.00536571; - fall_capacitance_range (0.00536571, 0.00536571); + fall_capacitance_range (0.00496399, 0.00610809); } } cell (sg13g2_nand2b_1) { area : 9.072; - cell_footprint : "nand2b1"; + cell_footprint : "nand2b"; cell_leakage_power : 860.188; leakage_power () { value : 1660.51; @@ -20570,9 +20644,9 @@ library (sg13g2_stdcell_slow_1p35V_125C) { max_transition : 2.5074; capacitance : 0.00221933; rise_capacitance : 0.00225599; - rise_capacitance_range (0.00225599, 0.00225599); + rise_capacitance_range (0.00198662, 0.00246397); fall_capacitance : 0.00218268; - fall_capacitance_range (0.00218268, 0.00218268); + fall_capacitance_range (0.00197977, 0.00236902); internal_power () { when : "!B"; rise_power (passive_POWER_7x1ds1) { @@ -20608,14 +20682,14 @@ library (sg13g2_stdcell_slow_1p35V_125C) { max_transition : 2.5074; capacitance : 0.00298455; rise_capacitance : 0.00311757; - rise_capacitance_range (0.00311757, 0.00311757); + rise_capacitance_range (0.00264032, 0.00347392); fall_capacitance : 0.00285154; - fall_capacitance_range (0.00285154, 0.00285154); + fall_capacitance_range (0.00266427, 0.0031923); } } cell (sg13g2_nand2b_2) { area : 14.5152; - cell_footprint : "nand2b2"; + cell_footprint : "nand2b"; cell_leakage_power : 1357.36; leakage_power () { value : 3178.7; @@ -20816,9 +20890,9 @@ library (sg13g2_stdcell_slow_1p35V_125C) { max_transition : 2.5074; capacitance : 0.00217088; rise_capacitance : 0.00220641; - rise_capacitance_range (0.00220641, 0.00220641); + rise_capacitance_range (0.00201033, 0.00238341); fall_capacitance : 0.00213535; - fall_capacitance_range (0.00213535, 0.00213535); + fall_capacitance_range (0.00197505, 0.00229002); internal_power () { when : "!B"; rise_power (passive_POWER_7x1ds1) { @@ -20854,9 +20928,9 @@ library (sg13g2_stdcell_slow_1p35V_125C) { max_transition : 2.5074; capacitance : 0.00549084; rise_capacitance : 0.00555528; - rise_capacitance_range (0.00555528, 0.00555528); + rise_capacitance_range (0.00486877, 0.00623284); fall_capacitance : 0.00542639; - fall_capacitance_range (0.00542639, 0.00542639); + fall_capacitance_range (0.00467175, 0.00662485); } } cell (sg13g2_nand3_1) { @@ -21164,32 +21238,32 @@ library (sg13g2_stdcell_slow_1p35V_125C) { max_transition : 2.5074; capacitance : 0.00281382; rise_capacitance : 0.00283003; - rise_capacitance_range (0.00283003, 0.00283003); + rise_capacitance_range (0.00254061, 0.00308521); fall_capacitance : 0.00279761; - fall_capacitance_range (0.00279761, 0.00279761); + fall_capacitance_range (0.00240854, 0.00337563); } pin (B) { direction : "input"; max_transition : 2.5074; capacitance : 0.00296264; rise_capacitance : 0.00307333; - rise_capacitance_range (0.00307333, 0.00307333); + rise_capacitance_range (0.00262085, 0.00338946); fall_capacitance : 0.00285195; - fall_capacitance_range (0.00285195, 0.00285195); + fall_capacitance_range (0.00258428, 0.00326876); } pin (C) { direction : "input"; max_transition : 2.5074; capacitance : 0.00294071; rise_capacitance : 0.003079; - rise_capacitance_range (0.003079, 0.003079); + rise_capacitance_range (0.00262105, 0.003437); fall_capacitance : 0.00280242; - fall_capacitance_range (0.00280242, 0.00280242); + fall_capacitance_range (0.00264787, 0.00310668); } } cell (sg13g2_nand3b_1) { area : 12.7008; - cell_footprint : "nand3b1"; + cell_footprint : "nand3b"; cell_leakage_power : 766.479; leakage_power () { value : 221.532; @@ -21492,9 +21566,9 @@ library (sg13g2_stdcell_slow_1p35V_125C) { max_transition : 2.5074; capacitance : 0.00219965; rise_capacitance : 0.00223612; - rise_capacitance_range (0.00223612, 0.00223612); + rise_capacitance_range (0.00196518, 0.00244433); fall_capacitance : 0.00216319; - fall_capacitance_range (0.00216319, 0.00216319); + fall_capacitance_range (0.00195848, 0.00234977); internal_power () { when : "(B * !C) + (!B)"; rise_power (passive_POWER_7x1ds1) { @@ -21530,18 +21604,18 @@ library (sg13g2_stdcell_slow_1p35V_125C) { max_transition : 2.5074; capacitance : 0.00292661; rise_capacitance : 0.00303753; - rise_capacitance_range (0.00303753, 0.00303753); + rise_capacitance_range (0.0025789, 0.00335546); fall_capacitance : 0.00281569; - fall_capacitance_range (0.00281569, 0.00281569); + fall_capacitance_range (0.00254558, 0.00322988); } pin (C) { direction : "input"; max_transition : 2.5074; capacitance : 0.00295093; rise_capacitance : 0.00308878; - rise_capacitance_range (0.00308878, 0.00308878); + rise_capacitance_range (0.00263209, 0.00344401); fall_capacitance : 0.00281307; - fall_capacitance_range (0.00281307, 0.00281307); + fall_capacitance_range (0.00265636, 0.00311598); } } cell (sg13g2_nand4_1) { @@ -21625,52 +21699,52 @@ library (sg13g2_stdcell_slow_1p35V_125C) { index_1 ("0.0186, 0.0966, 0.174, 0.3294, 0.6408, 1.263, 2.5074"); index_2 ("0.001, 0.0234, 0.039, 0.0648, 0.108, 0.18, 0.3"); values ( \ - "0.0272344, 0.0946592, 0.140679, 0.216608, 0.343641, 0.555421, 0.908395", \ - "0.0493333, 0.133559, 0.180375, 0.256327, 0.383453, 0.595002, 0.948625", \ - "0.0604544, 0.166239, 0.21798, 0.296463, 0.423914, 0.635529, 0.988431", \ - "0.0735306, 0.214527, 0.278412, 0.367916, 0.502433, 0.714999, 1.06756", \ + "0.0272344, 0.094658, 0.140947, 0.216605, 0.343671, 0.55542, 0.908405", \ + "0.0493203, 0.133558, 0.180375, 0.256318, 0.383311, 0.595112, 0.947992", \ + "0.0604544, 0.166239, 0.21798, 0.296464, 0.423912, 0.635529, 0.989798", \ + "0.0735306, 0.214527, 0.278412, 0.367916, 0.502433, 0.714998, 1.06756", \ "0.0895379, 0.281842, 0.366332, 0.480786, 0.639104, 0.870094, 1.22785", \ - "0.0965452, 0.363383, 0.479297, 0.632112, 0.841429, 1.12265, 1.52385", \ - "0.0965462, 0.452691, 0.615341, 0.828355, 1.10821, 1.48727, 1.99203" \ + "0.0965453, 0.363383, 0.479297, 0.632112, 0.841429, 1.12265, 1.52385", \ + "0.0965463, 0.452691, 0.615341, 0.828355, 1.10808, 1.48727, 1.99203" \ ); } rise_transition (TIMING_DELAY_7x7ds1) { index_1 ("0.0186, 0.0966, 0.174, 0.3294, 0.6408, 1.263, 2.5074"); index_2 ("0.001, 0.0234, 0.039, 0.0648, 0.108, 0.18, 0.3"); values ( \ - "0.0206329, 0.11729, 0.184049, 0.295448, 0.482051, 0.793166, 1.31132", \ - "0.0379518, 0.12379, 0.187058, 0.295871, 0.482052, 0.793167, 1.31221", \ - "0.0531011, 0.141898, 0.200999, 0.303782, 0.484416, 0.794576, 1.31222", \ - "0.0769761, 0.180078, 0.238273, 0.334896, 0.503009, 0.79969, 1.31223", \ + "0.0206329, 0.11729, 0.184366, 0.295448, 0.482066, 0.793167, 1.31135", \ + "0.0378731, 0.123765, 0.187054, 0.295938, 0.482302, 0.793168, 1.31148", \ + "0.0531012, 0.141898, 0.200984, 0.303837, 0.484414, 0.794576, 1.31264", \ + "0.0769761, 0.180078, 0.238273, 0.334896, 0.503009, 0.799689, 1.31265", \ "0.117572, 0.246839, 0.311948, 0.410405, 0.571258, 0.845851, 1.33239", \ "0.184347, 0.358941, 0.437054, 0.552834, 0.723925, 0.992371, 1.44123", \ - "0.295749, 0.540429, 0.647271, 0.786944, 0.995439, 1.29015, 1.74722" \ + "0.295749, 0.540429, 0.647271, 0.786944, 0.994321, 1.29015, 1.74722" \ ); } cell_fall (TIMING_DELAY_7x7ds1) { index_1 ("0.0186, 0.0966, 0.174, 0.3294, 0.6408, 1.263, 2.5074"); index_2 ("0.001, 0.0234, 0.039, 0.0648, 0.108, 0.18, 0.3"); values ( \ - "0.0561369, 0.236792, 0.360467, 0.564907, 0.906806, 1.47656, 2.42612", \ - "0.0787819, 0.266306, 0.390405, 0.595057, 0.93739, 1.50739, 2.45704", \ - "0.0952399, 0.296808, 0.421575, 0.626081, 0.970215, 1.53842, 2.48815", \ - "0.120101, 0.352121, 0.483431, 0.690525, 1.03237, 1.60169, 2.55206", \ - "0.155717, 0.43505, 0.583938, 0.808665, 1.15786, 1.7267, 2.67385", \ - "0.211582, 0.556759, 0.735228, 0.996123, 1.38446, 1.97826, 2.92919", \ - "0.297887, 0.729708, 0.953611, 1.2715, 1.72978, 2.40363, 3.41986" \ + "0.0561336, 0.236846, 0.360467, 0.564909, 0.906798, 1.47656, 2.42613", \ + "0.0787854, 0.266283, 0.390405, 0.595016, 0.937417, 1.50745, 2.45667", \ + "0.0952395, 0.296807, 0.421574, 0.62608, 0.97021, 1.5384, 2.48814", \ + "0.120101, 0.35212, 0.483431, 0.690526, 1.03237, 1.60212, 2.552", \ + "0.155717, 0.43505, 0.583938, 0.808664, 1.15786, 1.7267, 2.67411", \ + "0.211581, 0.556758, 0.735228, 0.996122, 1.38446, 1.97819, 2.92906", \ + "0.297887, 0.729707, 0.953611, 1.2715, 1.72978, 2.40363, 3.41986" \ ); } fall_transition (TIMING_DELAY_7x7ds1) { index_1 ("0.0186, 0.0966, 0.174, 0.3294, 0.6408, 1.263, 2.5074"); index_2 ("0.001, 0.0234, 0.039, 0.0648, 0.108, 0.18, 0.3"); values ( \ - "0.052957, 0.290716, 0.456137, 0.730114, 1.18819, 1.95185, 3.22435", \ - "0.0647923, 0.291902, 0.456348, 0.730115, 1.18822, 1.95186, 3.22436", \ - "0.0769717, 0.300565, 0.459964, 0.730828, 1.19016, 1.95187, 3.22437", \ - "0.0990844, 0.32954, 0.482023, 0.741741, 1.19056, 1.95224, 3.22438", \ - "0.133671, 0.389752, 0.543173, 0.793235, 1.22082, 1.9597, 3.22621", \ - "0.19133, 0.492737, 0.660539, 0.917364, 1.33508, 2.03723, 3.2537", \ - "0.292673, 0.659327, 0.852656, 1.14359, 1.58074, 2.28154, 3.43967" \ + "0.0529576, 0.291048, 0.456136, 0.730114, 1.18826, 1.95175, 3.22434", \ + "0.0648773, 0.291921, 0.456137, 0.730115, 1.18827, 1.95183, 3.22435", \ + "0.076972, 0.300564, 0.459963, 0.730805, 1.19016, 1.95184, 3.22436", \ + "0.0990843, 0.32954, 0.482023, 0.741743, 1.19056, 1.95185, 3.22437", \ + "0.133671, 0.389752, 0.543165, 0.793235, 1.22081, 1.95969, 3.22438", \ + "0.19133, 0.492737, 0.660538, 0.917364, 1.33507, 2.03736, 3.25234", \ + "0.292673, 0.659326, 0.852656, 1.14359, 1.58074, 2.28153, 3.43967" \ ); } } @@ -21682,52 +21756,52 @@ library (sg13g2_stdcell_slow_1p35V_125C) { index_1 ("0.0186, 0.0966, 0.174, 0.3294, 0.6408, 1.263, 2.5074"); index_2 ("0.001, 0.0234, 0.039, 0.0648, 0.108, 0.18, 0.3"); values ( \ - "0.0315773, 0.0989242, 0.145067, 0.220904, 0.348033, 0.559941, 0.912773", \ - "0.0570854, 0.138048, 0.184701, 0.260644, 0.387831, 0.599554, 0.952617", \ - "0.0712232, 0.171349, 0.222613, 0.300936, 0.428247, 0.639925, 0.992777", \ - "0.0887097, 0.221355, 0.284059, 0.37286, 0.506838, 0.719375, 1.07201", \ + "0.0315803, 0.0989244, 0.145004, 0.220899, 0.348033, 0.559949, 0.912781", \ + "0.0571128, 0.138048, 0.18471, 0.260623, 0.387831, 0.599565, 0.952486", \ + "0.0712231, 0.171349, 0.222614, 0.300925, 0.428275, 0.639967, 0.992744", \ + "0.0887097, 0.221355, 0.284059, 0.372861, 0.506838, 0.719375, 1.07194", \ "0.111766, 0.291363, 0.374121, 0.486884, 0.644514, 0.874653, 1.23222", \ "0.12974, 0.378147, 0.490808, 0.641241, 0.848482, 1.12833, 1.52849", \ - "0.13487, 0.477522, 0.634327, 0.842652, 1.11888, 1.49601, 1.99856" \ + "0.134871, 0.477522, 0.634327, 0.842652, 1.11888, 1.49601, 1.99856" \ ); } rise_transition (TIMING_DELAY_7x7ds1) { index_1 ("0.0186, 0.0966, 0.174, 0.3294, 0.6408, 1.263, 2.5074"); index_2 ("0.001, 0.0234, 0.039, 0.0648, 0.108, 0.18, 0.3"); values ( \ - "0.0247457, 0.1212, 0.188772, 0.30027, 0.486942, 0.798012, 1.31655", \ - "0.0411288, 0.127902, 0.191512, 0.300561, 0.486943, 0.798013, 1.31656", \ - "0.0570959, 0.145694, 0.20505, 0.308261, 0.488974, 0.79864, 1.31657", \ - "0.0818244, 0.183439, 0.241996, 0.338867, 0.507406, 0.804445, 1.31764", \ + "0.0247457, 0.121201, 0.18872, 0.300167, 0.486942, 0.798012, 1.31651", \ + "0.0412363, 0.127902, 0.191503, 0.300571, 0.486943, 0.798013, 1.31652", \ + "0.057096, 0.145694, 0.205056, 0.308258, 0.489014, 0.798014, 1.31653", \ + "0.0818244, 0.183439, 0.241988, 0.338887, 0.507409, 0.804396, 1.31685", \ "0.121704, 0.25042, 0.315188, 0.414378, 0.575249, 0.850346, 1.33765", \ - "0.186834, 0.360023, 0.441012, 0.55726, 0.727555, 0.996774, 1.44583", \ - "0.293468, 0.540639, 0.645919, 0.789748, 0.99844, 1.29396, 1.75145" \ + "0.186834, 0.360022, 0.441012, 0.55726, 0.727555, 0.996774, 1.44583", \ + "0.293468, 0.540639, 0.645919, 0.789748, 0.998441, 1.29396, 1.75145" \ ); } cell_fall (TIMING_DELAY_7x7ds1) { index_1 ("0.0186, 0.0966, 0.174, 0.3294, 0.6408, 1.263, 2.5074"); index_2 ("0.001, 0.0234, 0.039, 0.0648, 0.108, 0.18, 0.3"); values ( \ - "0.0701597, 0.249849, 0.373455, 0.577684, 0.919733, 1.48943, 2.43895", \ - "0.0908511, 0.277149, 0.401256, 0.60613, 0.94805, 1.51827, 2.46723", \ - "0.105648, 0.303726, 0.428762, 0.633789, 0.976262, 1.54588, 2.49556", \ - "0.127876, 0.352169, 0.482638, 0.690207, 1.03313, 1.60368, 2.5539", \ - "0.160561, 0.428929, 0.573422, 0.794201, 1.14388, 1.7152, 2.66462", \ - "0.214867, 0.545876, 0.716037, 0.966631, 1.34516, 1.9364, 2.89082", \ - "0.298826, 0.716166, 0.929915, 1.23254, 1.67093, 2.32138, 3.32385" \ + "0.0701568, 0.249844, 0.37345, 0.577689, 0.919741, 1.48943, 2.43895", \ + "0.090851, 0.277106, 0.401355, 0.605909, 0.948046, 1.51828, 2.46721", \ + "0.105757, 0.303726, 0.428794, 0.633784, 0.976245, 1.54581, 2.49556", \ + "0.127876, 0.352171, 0.482638, 0.690207, 1.0332, 1.60379, 2.55307", \ + "0.160561, 0.428928, 0.573421, 0.7942, 1.14388, 1.7152, 2.6647", \ + "0.214867, 0.545876, 0.716036, 0.966631, 1.34515, 1.9364, 2.89081", \ + "0.298826, 0.716166, 0.929914, 1.23254, 1.67093, 2.32137, 3.32384" \ ); } fall_transition (TIMING_DELAY_7x7ds1) { index_1 ("0.0186, 0.0966, 0.174, 0.3294, 0.6408, 1.263, 2.5074"); index_2 ("0.001, 0.0234, 0.039, 0.0648, 0.108, 0.18, 0.3"); values ( \ - "0.0530997, 0.290812, 0.456145, 0.729592, 1.18826, 1.95175, 3.22435", \ - "0.0621605, 0.291623, 0.456635, 0.729756, 1.18827, 1.95176, 3.22436", \ - "0.0731247, 0.297691, 0.458778, 0.730102, 1.18828, 1.95177, 3.22437", \ - "0.0953651, 0.319347, 0.474431, 0.737961, 1.18878, 1.95178, 3.22438", \ - "0.131363, 0.36994, 0.521563, 0.774484, 1.2099, 1.95674, 3.22439", \ - "0.188915, 0.460704, 0.620678, 0.871093, 1.2943, 2.01009, 3.24437", \ - "0.285768, 0.610683, 0.797396, 1.06376, 1.49183, 2.19081, 3.37294" \ + "0.053107, 0.290812, 0.456144, 0.729596, 1.18825, 1.95175, 3.22434", \ + "0.0621605, 0.291489, 0.456433, 0.729597, 1.18826, 1.95176, 3.22435", \ + "0.0731969, 0.297691, 0.4588, 0.733172, 1.18827, 1.95177, 3.22436", \ + "0.0953651, 0.319446, 0.474339, 0.73796, 1.1897, 1.95319, 3.22437", \ + "0.131363, 0.369939, 0.521562, 0.774502, 1.2103, 1.95674, 3.22438", \ + "0.188915, 0.460703, 0.620678, 0.871094, 1.29429, 2.01008, 3.24436", \ + "0.285768, 0.610683, 0.797395, 1.06376, 1.49183, 2.19081, 3.37302" \ ); } } @@ -21739,10 +21813,10 @@ library (sg13g2_stdcell_slow_1p35V_125C) { index_1 ("0.0186, 0.0966, 0.174, 0.3294, 0.6408, 1.263, 2.5074"); index_2 ("0.001, 0.0234, 0.039, 0.0648, 0.108, 0.18, 0.3"); values ( \ - "0.0340075, 0.102509, 0.148773, 0.224942, 0.352242, 0.564085, 0.917255", \ - "0.0619498, 0.141709, 0.188435, 0.264366, 0.391662, 0.603548, 0.956608", \ - "0.0784228, 0.175719, 0.226603, 0.304806, 0.432245, 0.643985, 0.996878", \ - "0.0995656, 0.227167, 0.288878, 0.377222, 0.510976, 0.72352, 1.0761", \ + "0.03401, 0.10251, 0.148803, 0.224924, 0.352232, 0.564068, 0.917241", \ + "0.0619498, 0.141707, 0.18842, 0.264367, 0.391634, 0.603564, 0.95661", \ + "0.0784228, 0.175719, 0.226603, 0.304835, 0.432241, 0.644191, 0.996893", \ + "0.0995656, 0.227167, 0.288878, 0.377222, 0.510976, 0.72352, 1.076", \ "0.128133, 0.299604, 0.381111, 0.492721, 0.649161, 0.878986, 1.23647", \ "0.155754, 0.391025, 0.500935, 0.649042, 0.85467, 1.13376, 1.53323", \ "0.177628, 0.499788, 0.652157, 0.856086, 1.12961, 1.50304, 2.00483" \ @@ -21752,10 +21826,10 @@ library (sg13g2_stdcell_slow_1p35V_125C) { index_1 ("0.0186, 0.0966, 0.174, 0.3294, 0.6408, 1.263, 2.5074"); index_2 ("0.001, 0.0234, 0.039, 0.0648, 0.108, 0.18, 0.3"); values ( \ - "0.0285633, 0.12542, 0.19293, 0.304476, 0.491427, 0.802517, 1.32106", \ - "0.044215, 0.131628, 0.195659, 0.304835, 0.491428, 0.802759, 1.32107", \ - "0.0600776, 0.14908, 0.208775, 0.312384, 0.493504, 0.80276, 1.32108", \ - "0.0858858, 0.18652, 0.245498, 0.342602, 0.511597, 0.809044, 1.32109", \ + "0.0285933, 0.125421, 0.193023, 0.304504, 0.491427, 0.802585, 1.32125", \ + "0.044215, 0.13163, 0.195611, 0.304837, 0.491428, 0.802762, 1.32126", \ + "0.0600777, 0.149081, 0.208737, 0.312399, 0.493318, 0.802763, 1.32127", \ + "0.0858858, 0.18652, 0.245498, 0.342602, 0.511597, 0.809044, 1.32573", \ "0.126799, 0.253681, 0.31837, 0.418189, 0.578813, 0.854433, 1.3421", \ "0.192093, 0.36276, 0.443543, 0.560456, 0.730461, 1.00004, 1.45007", \ "0.298639, 0.541443, 0.64699, 0.791816, 1.0013, 1.30024, 1.75496" \ @@ -21765,26 +21839,26 @@ library (sg13g2_stdcell_slow_1p35V_125C) { index_1 ("0.0186, 0.0966, 0.174, 0.3294, 0.6408, 1.263, 2.5074"); index_2 ("0.001, 0.0234, 0.039, 0.0648, 0.108, 0.18, 0.3"); values ( \ - "0.0783881, 0.258128, 0.381654, 0.585925, 0.927698, 1.49729, 2.44717", \ - "0.098327, 0.28268, 0.406808, 0.611663, 0.95369, 1.52386, 2.47314", \ - "0.11194, 0.304325, 0.429149, 0.634174, 0.976502, 1.54644, 2.49605", \ - "0.131354, 0.343471, 0.472428, 0.679284, 1.02204, 1.59228, 2.54285", \ - "0.157078, 0.406374, 0.545835, 0.762627, 1.11062, 1.68152, 2.63102", \ - "0.200811, 0.505997, 0.665767, 0.904952, 1.27337, 1.85943, 2.81172", \ - "0.270903, 0.654821, 0.850494, 1.13208, 1.54384, 2.17389, 3.16346" \ + "0.0784068, 0.258134, 0.381652, 0.585919, 0.927725, 1.4973, 2.44715", \ + "0.0983269, 0.282713, 0.406924, 0.611685, 0.953975, 1.52386, 2.47314", \ + "0.111939, 0.304322, 0.429146, 0.634174, 0.976453, 1.54642, 2.49602", \ + "0.131407, 0.343471, 0.472427, 0.679283, 1.02204, 1.59259, 2.54286", \ + "0.157078, 0.406374, 0.545835, 0.762624, 1.11062, 1.68152, 2.63096", \ + "0.200811, 0.505997, 0.665767, 0.904951, 1.27337, 1.85943, 2.81171", \ + "0.270903, 0.65482, 0.850493, 1.13208, 1.54384, 2.17389, 3.16346" \ ); } fall_transition (TIMING_DELAY_7x7ds1) { index_1 ("0.0186, 0.0966, 0.174, 0.3294, 0.6408, 1.263, 2.5074"); index_2 ("0.001, 0.0234, 0.039, 0.0648, 0.108, 0.18, 0.3"); values ( \ - "0.0530805, 0.29089, 0.456183, 0.72936, 1.18736, 1.95019, 3.22435", \ - "0.0591162, 0.291377, 0.456617, 0.729828, 1.18741, 1.95184, 3.22436", \ - "0.0674199, 0.295792, 0.458094, 0.73456, 1.18742, 1.95185, 3.22437", \ - "0.0858994, 0.311968, 0.469932, 0.735795, 1.18836, 1.95327, 3.22438", \ - "0.122133, 0.351305, 0.505851, 0.763791, 1.20451, 1.95495, 3.22439", \ - "0.184212, 0.432453, 0.58638, 0.841319, 1.26906, 1.99654, 3.23955", \ - "0.282539, 0.570754, 0.741557, 1.00391, 1.42726, 2.13617, 3.33998" \ + "0.0530519, 0.290893, 0.456181, 0.729342, 1.18665, 1.95019, 3.22435", \ + "0.0591161, 0.291402, 0.456533, 0.72986, 1.18827, 1.95184, 3.22436", \ + "0.0674195, 0.29571, 0.457988, 0.734559, 1.18828, 1.95185, 3.22437", \ + "0.085947, 0.311968, 0.469931, 0.735801, 1.18836, 1.95186, 3.22438", \ + "0.122133, 0.351304, 0.505852, 0.763788, 1.20451, 1.95495, 3.22439", \ + "0.184212, 0.432452, 0.586377, 0.841317, 1.26906, 1.99654, 3.24221", \ + "0.282539, 0.570753, 0.741555, 1.00391, 1.42726, 2.13617, 3.33998" \ ); } } @@ -21796,10 +21870,10 @@ library (sg13g2_stdcell_slow_1p35V_125C) { index_1 ("0.0186, 0.0966, 0.174, 0.3294, 0.6408, 1.263, 2.5074"); index_2 ("0.001, 0.0234, 0.039, 0.0648, 0.108, 0.18, 0.3"); values ( \ - "0.0348556, 0.105089, 0.151843, 0.228227, 0.355535, 0.567352, 0.920112", \ - "0.0647812, 0.144333, 0.191229, 0.267528, 0.394864, 0.606783, 0.960209", \ - "0.0832638, 0.178983, 0.229836, 0.307968, 0.435544, 0.647195, 0.999851", \ - "0.1074, 0.231712, 0.292935, 0.38092, 0.514342, 0.726706, 1.07906", \ + "0.0348592, 0.105094, 0.151846, 0.228226, 0.355537, 0.56735, 0.920107", \ + "0.0647819, 0.144332, 0.191209, 0.267529, 0.395007, 0.606682, 0.95959", \ + "0.0832638, 0.178953, 0.229838, 0.307967, 0.435567, 0.647227, 1.00008", \ + "0.1074, 0.231712, 0.292935, 0.380918, 0.514342, 0.726736, 1.0791", \ "0.140809, 0.306465, 0.387045, 0.497335, 0.653257, 0.882418, 1.2395", \ "0.176823, 0.402057, 0.509685, 0.656781, 0.860296, 1.13811, 1.5368", \ "0.215149, 0.520044, 0.667893, 0.867423, 1.13797, 1.5104, 2.00943" \ @@ -21809,39 +21883,39 @@ library (sg13g2_stdcell_slow_1p35V_125C) { index_1 ("0.0186, 0.0966, 0.174, 0.3294, 0.6408, 1.263, 2.5074"); index_2 ("0.001, 0.0234, 0.039, 0.0648, 0.108, 0.18, 0.3"); values ( \ - "0.0318983, 0.129399, 0.196919, 0.3084, 0.494959, 0.806132, 1.3244", \ - "0.0471838, 0.135197, 0.199334, 0.30865, 0.49496, 0.806133, 1.32455", \ - "0.0629387, 0.152213, 0.212076, 0.315946, 0.496863, 0.806134, 1.32456", \ - "0.0896642, 0.189591, 0.248604, 0.345789, 0.514899, 0.812423, 1.32558", \ + "0.0318863, 0.129369, 0.19702, 0.308399, 0.49496, 0.806122, 1.32439", \ + "0.0471833, 0.135198, 0.199275, 0.30865, 0.494961, 0.806123, 1.3244", \ + "0.0629386, 0.152199, 0.212113, 0.315875, 0.496926, 0.806124, 1.32441", \ + "0.0896642, 0.189591, 0.248604, 0.345789, 0.514899, 0.812277, 1.32616", \ "0.131089, 0.256589, 0.321645, 0.420809, 0.582206, 0.857487, 1.34419", \ "0.197255, 0.365735, 0.446553, 0.561613, 0.733332, 1.003, 1.45225", \ - "0.303619, 0.542892, 0.649655, 0.793849, 1.00305, 1.30161, 1.75738" \ + "0.303619, 0.542891, 0.649655, 0.793848, 1.00305, 1.30161, 1.75738" \ ); } cell_fall (TIMING_DELAY_7x7ds1) { index_1 ("0.0186, 0.0966, 0.174, 0.3294, 0.6408, 1.263, 2.5074"); index_2 ("0.001, 0.0234, 0.039, 0.0648, 0.108, 0.18, 0.3"); values ( \ - "0.0825626, 0.262298, 0.385829, 0.5901, 0.932112, 1.50186, 2.45135", \ - "0.102281, 0.285512, 0.409631, 0.614527, 0.956743, 1.52617, 2.47626", \ - "0.115422, 0.304185, 0.428867, 0.633832, 0.9763, 1.54597, 2.49621", \ - "0.133026, 0.335859, 0.463752, 0.670212, 1.01299, 1.58312, 2.53409", \ - "0.153745, 0.385612, 0.521559, 0.735823, 1.08298, 1.6537, 2.60315", \ - "0.183841, 0.464347, 0.616502, 0.848438, 1.21153, 1.79389, 2.74706", \ - "0.235049, 0.58622, 0.765268, 1.02845, 1.42617, 2.04358, 3.02427" \ + "0.0825739, 0.262298, 0.385823, 0.590051, 0.93211, 1.50185, 2.45135", \ + "0.102306, 0.285512, 0.40963, 0.614313, 0.956484, 1.52616, 2.47625", \ + "0.115422, 0.304184, 0.428895, 0.633824, 0.976299, 1.54597, 2.49565", \ + "0.133026, 0.335859, 0.46375, 0.670222, 1.01298, 1.58311, 2.53409", \ + "0.153745, 0.385612, 0.521559, 0.735822, 1.08293, 1.65369, 2.60315", \ + "0.18384, 0.464347, 0.616502, 0.848438, 1.21153, 1.79389, 2.74706", \ + "0.235048, 0.586219, 0.765267, 1.02845, 1.42617, 2.04358, 3.02443" \ ); } fall_transition (TIMING_DELAY_7x7ds1) { index_1 ("0.0186, 0.0966, 0.174, 0.3294, 0.6408, 1.263, 2.5074"); index_2 ("0.001, 0.0234, 0.039, 0.0648, 0.108, 0.18, 0.3"); values ( \ - "0.0530726, 0.290863, 0.456125, 0.729412, 1.18819, 1.95175, 3.22435", \ - "0.0570889, 0.29118, 0.456756, 0.729777, 1.18826, 1.95176, 3.22442", \ - "0.0629171, 0.294383, 0.457408, 0.730007, 1.18827, 1.95177, 3.22443", \ - "0.0764901, 0.306863, 0.466804, 0.734497, 1.1888, 1.95266, 3.22444", \ - "0.106878, 0.338265, 0.495252, 0.757002, 1.20133, 1.95452, 3.23493", \ - "0.170948, 0.403369, 0.560486, 0.820691, 1.25349, 1.98905, 3.23692", \ - "0.271986, 0.529485, 0.691537, 0.95122, 1.38596, 2.1045, 3.32085" \ + "0.0530841, 0.290863, 0.456126, 0.729577, 1.18819, 1.95175, 3.22434", \ + "0.0570922, 0.29118, 0.456754, 0.729578, 1.1882, 1.95176, 3.22441", \ + "0.062917, 0.294383, 0.457487, 0.734392, 1.18821, 1.95177, 3.22442", \ + "0.07649, 0.306858, 0.466787, 0.734393, 1.1888, 1.95266, 3.22443", \ + "0.106878, 0.338265, 0.495252, 0.757001, 1.20191, 1.95383, 3.23492", \ + "0.170948, 0.403368, 0.560486, 0.82069, 1.25349, 1.98905, 3.23679", \ + "0.271987, 0.529484, 0.691535, 0.951219, 1.38596, 2.10452, 3.32116" \ ); } } @@ -21851,26 +21925,26 @@ library (sg13g2_stdcell_slow_1p35V_125C) { index_1 ("0.0186, 0.0966, 0.174, 0.3294, 0.6408, 1.263, 2.5074"); index_2 ("0.001, 0.0234, 0.039, 0.0648, 0.108, 0.18, 0.3"); values ( \ - "0.00240156, 0.00282834, 0.00274717, 0.00267572, 0.00252426, 0.00227723, 0.00181051", \ - "0.00227514, 0.00266502, 0.00266344, 0.00293181, 0.00253917, 0.00230051, 0.00195059", \ - "0.00253017, 0.00259947, 0.00269355, 0.00259918, 0.00297108, 0.00246648, 0.00183677", \ - "0.00337976, 0.0029022, 0.00279956, 0.00277416, 0.00273026, 0.00243119, 0.00193557", \ - "0.00541779, 0.00391395, 0.00363846, 0.00328343, 0.00299687, 0.00288249, 0.00247452", \ - "0.00984521, 0.0069621, 0.00606194, 0.00529254, 0.00462912, 0.00353143, 0.00360341", \ - "0.0190699, 0.0143042, 0.012654, 0.0109337, 0.00915277, 0.00740094, 0.00584359" \ + "0.00240154, 0.00282792, 0.00279424, 0.00267482, 0.0025504, 0.00227833, 0.00185381", \ + "0.00227281, 0.00266069, 0.00266395, 0.00278991, 0.00258963, 0.00230077, 0.00185337", \ + "0.00252972, 0.00259947, 0.00268784, 0.00260309, 0.00297094, 0.00246641, 0.00205865", \ + "0.00337979, 0.0029022, 0.00279956, 0.00277418, 0.00273026, 0.00243099, 0.0019355", \ + "0.00541715, 0.00391395, 0.00364223, 0.00329025, 0.00299687, 0.00288249, 0.00247458", \ + "0.00984514, 0.0069621, 0.00606194, 0.00529254, 0.00462913, 0.00353143, 0.00360267", \ + "0.0190698, 0.0143041, 0.012654, 0.0109337, 0.00908018, 0.00740094, 0.00581034" \ ); } fall_power (POWER_7x7ds1) { index_1 ("0.0186, 0.0966, 0.174, 0.3294, 0.6408, 1.263, 2.5074"); index_2 ("0.001, 0.0234, 0.039, 0.0648, 0.108, 0.18, 0.3"); values ( \ - "0.00559749, 0.00590451, 0.00589506, 0.00585071, 0.00572546, 0.00547435, 0.00524032", \ - "0.00536638, 0.00567086, 0.0057221, 0.00570703, 0.00564984, 0.0054221, 0.00517475", \ - "0.00562892, 0.00567262, 0.00565541, 0.00568025, 0.00570659, 0.00539717, 0.00518153", \ - "0.00641162, 0.0058362, 0.005858, 0.00579197, 0.00559026, 0.00550562, 0.00509448", \ - "0.00829448, 0.0069344, 0.00653395, 0.00629004, 0.00602565, 0.00564117, 0.00546112", \ - "0.0124743, 0.00968454, 0.00893648, 0.00818204, 0.00730334, 0.00707674, 0.00638513", \ - "0.0215892, 0.0167275, 0.0151562, 0.0135759, 0.0118529, 0.00990118, 0.008697" \ + "0.00559762, 0.00591162, 0.00589521, 0.00585112, 0.00572856, 0.00549675, 0.00524197", \ + "0.00536872, 0.0056695, 0.00571499, 0.00570228, 0.00565083, 0.00546051, 0.00506258", \ + "0.00563006, 0.00567283, 0.00565583, 0.00568213, 0.00570999, 0.00540369, 0.00518064", \ + "0.00641179, 0.00583613, 0.00585799, 0.00579337, 0.00559165, 0.00537491, 0.00509313", \ + "0.00829448, 0.00693428, 0.00652665, 0.00628999, 0.00602381, 0.00564118, 0.00529603", \ + "0.0124764, 0.0096829, 0.00893648, 0.00818183, 0.00730335, 0.00708487, 0.00637687", \ + "0.0215888, 0.0167277, 0.0151577, 0.0135759, 0.011853, 0.00990113, 0.00869721" \ ); } } @@ -21880,26 +21954,26 @@ library (sg13g2_stdcell_slow_1p35V_125C) { index_1 ("0.0186, 0.0966, 0.174, 0.3294, 0.6408, 1.263, 2.5074"); index_2 ("0.001, 0.0234, 0.039, 0.0648, 0.108, 0.18, 0.3"); values ( \ - "0.00279856, 0.00291968, 0.00290026, 0.00281359, 0.0026501, 0.00238972, 0.00194726", \ - "0.00257094, 0.00284779, 0.00281235, 0.00305544, 0.00263872, 0.00240697, 0.0019324", \ - "0.00279702, 0.0027837, 0.00284043, 0.00273342, 0.00306131, 0.00246344, 0.00195646", \ - "0.00355921, 0.00309809, 0.00297113, 0.00291113, 0.00269651, 0.00263014, 0.00210387", \ - "0.00544513, 0.00415438, 0.00384934, 0.0035312, 0.00316481, 0.00325722, 0.00273116", \ - "0.00957924, 0.00716977, 0.0063733, 0.00560963, 0.00486289, 0.00374405, 0.00358688", \ - "0.0185623, 0.0146615, 0.0130565, 0.0112768, 0.0095103, 0.0077323, 0.00602997" \ + "0.00279662, 0.00291774, 0.00288654, 0.00279379, 0.00264926, 0.0023908, 0.0019914", \ + "0.00257517, 0.00284779, 0.00281776, 0.00291817, 0.00263872, 0.0024011, 0.00194165", \ + "0.00279616, 0.00278367, 0.00284873, 0.00273769, 0.00313796, 0.00238002, 0.00191838", \ + "0.00355915, 0.00309752, 0.00298448, 0.00290982, 0.0028354, 0.00258984, 0.00194583", \ + "0.00544352, 0.00415438, 0.00384983, 0.00353814, 0.00316501, 0.00325722, 0.00273116", \ + "0.00957968, 0.00717046, 0.00637332, 0.00560963, 0.00486362, 0.00374405, 0.00358688", \ + "0.0185623, 0.0146616, 0.0130566, 0.0112768, 0.00951041, 0.0077323, 0.00602997" \ ); } fall_power (POWER_7x7ds1) { index_1 ("0.0186, 0.0966, 0.174, 0.3294, 0.6408, 1.263, 2.5074"); index_2 ("0.001, 0.0234, 0.039, 0.0648, 0.108, 0.18, 0.3"); values ( \ - "0.00776088, 0.00796427, 0.00794257, 0.00786703, 0.00776582, 0.00752688, 0.00724982", \ - "0.00740086, 0.00775057, 0.0077995, 0.00778892, 0.00766659, 0.00748468, 0.00712805", \ - "0.00742596, 0.00773514, 0.00766938, 0.00769946, 0.00761749, 0.00740239, 0.00710983", \ - "0.00784865, 0.00766603, 0.00776108, 0.00775092, 0.00755446, 0.00737438, 0.00716853", \ - "0.00934625, 0.00843527, 0.00817345, 0.00799129, 0.00813521, 0.00753271, 0.00721973", \ - "0.0131919, 0.0107104, 0.0101118, 0.009507, 0.00880258, 0.00848345, 0.00765837", \ - "0.0216212, 0.0170105, 0.0157274, 0.0141201, 0.0127834, 0.0109785, 0.00996382" \ + "0.00776208, 0.00796339, 0.0079426, 0.00786605, 0.00776623, 0.00752732, 0.00725107", \ + "0.00740085, 0.00774517, 0.00778203, 0.0077593, 0.00766754, 0.00748419, 0.00712779", \ + "0.00743556, 0.00773492, 0.00767605, 0.00783589, 0.00762504, 0.00740531, 0.00711045", \ + "0.00784979, 0.00766201, 0.00774229, 0.00775098, 0.00757435, 0.00747409, 0.00714917", \ + "0.00934742, 0.00843636, 0.00817355, 0.0080176, 0.00787805, 0.00753291, 0.00733896", \ + "0.013191, 0.0107104, 0.0101094, 0.00946577, 0.00880219, 0.00848372, 0.00765854", \ + "0.0216182, 0.0170102, 0.0157227, 0.0141203, 0.0127877, 0.0109783, 0.0099624" \ ); } } @@ -21909,26 +21983,26 @@ library (sg13g2_stdcell_slow_1p35V_125C) { index_1 ("0.0186, 0.0966, 0.174, 0.3294, 0.6408, 1.263, 2.5074"); index_2 ("0.001, 0.0234, 0.039, 0.0648, 0.108, 0.18, 0.3"); values ( \ - "0.00319501, 0.00319891, 0.00315396, 0.00306654, 0.00293595, 0.00263323, 0.00219999", \ - "0.00294267, 0.00310394, 0.00306502, 0.00314305, 0.00283802, 0.00260223, 0.00211064", \ - "0.00313074, 0.00305568, 0.00309324, 0.00296204, 0.00299847, 0.00258116, 0.00211261", \ - "0.00383223, 0.00339497, 0.00323441, 0.003166, 0.0030098, 0.00263636, 0.00211427", \ - "0.00572386, 0.0044887, 0.00415811, 0.00377791, 0.0034012, 0.00330766, 0.00274839", \ - "0.0100623, 0.00758133, 0.00674396, 0.00590806, 0.00508426, 0.00405343, 0.0038474", \ - "0.0191889, 0.0151753, 0.0135734, 0.0118406, 0.00998177, 0.00819605, 0.00634431" \ + "0.00319551, 0.00319948, 0.00316111, 0.00307025, 0.0029347, 0.00264545, 0.00220782", \ + "0.00294208, 0.00311117, 0.00306807, 0.00307508, 0.00282325, 0.00260378, 0.00211142", \ + "0.00313033, 0.00305563, 0.00309633, 0.00296997, 0.00333686, 0.00257196, 0.00209961", \ + "0.00383226, 0.00339497, 0.00323441, 0.003166, 0.00300807, 0.00263642, 0.00265565", \ + "0.00572392, 0.00448881, 0.00415811, 0.00377958, 0.0034012, 0.00330766, 0.00274691", \ + "0.0100635, 0.00758131, 0.00674506, 0.00590787, 0.00511132, 0.00405343, 0.00389291", \ + "0.0191883, 0.0151755, 0.0135734, 0.0118406, 0.00998177, 0.00819606, 0.00634431" \ ); } fall_power (POWER_7x7ds1) { index_1 ("0.0186, 0.0966, 0.174, 0.3294, 0.6408, 1.263, 2.5074"); index_2 ("0.001, 0.0234, 0.039, 0.0648, 0.108, 0.18, 0.3"); values ( \ - "0.00963568, 0.00984055, 0.00980425, 0.00974203, 0.0096092, 0.00937941, 0.00913806", \ - "0.0092448, 0.00961959, 0.00966014, 0.00963805, 0.00952878, 0.00934426, 0.00903947", \ - "0.00921717, 0.00957549, 0.00953183, 0.00973354, 0.00947591, 0.00927653, 0.00899409", \ - "0.00943931, 0.00943866, 0.00955596, 0.00952211, 0.00941903, 0.00935184, 0.00901742", \ - "0.0106374, 0.0100025, 0.0098215, 0.00974475, 0.00965584, 0.00930917, 0.00901633", \ - "0.0144011, 0.0121157, 0.0115909, 0.0111548, 0.0105325, 0.0105367, 0.00972397", \ - "0.023097, 0.0184652, 0.017093, 0.015674, 0.014292, 0.0126713, 0.0117444" \ + "0.00963747, 0.00983766, 0.00980863, 0.00972778, 0.00959419, 0.00937958, 0.00913428", \ + "0.00924478, 0.00961862, 0.00965046, 0.00963425, 0.00955966, 0.00934358, 0.00904005", \ + "0.0092164, 0.00956244, 0.00952176, 0.00973358, 0.00947715, 0.00927591, 0.00899381", \ + "0.00944493, 0.00942607, 0.00955596, 0.00947803, 0.00941909, 0.00920602, 0.00901742", \ + "0.0106363, 0.0100036, 0.00982719, 0.00974219, 0.00964204, 0.00930917, 0.00917923", \ + "0.014401, 0.0121158, 0.0115909, 0.011156, 0.0105324, 0.0105367, 0.00982743", \ + "0.0230979, 0.0184652, 0.0170931, 0.015674, 0.0142994, 0.0126972, 0.0117445" \ ); } } @@ -21938,26 +22012,26 @@ library (sg13g2_stdcell_slow_1p35V_125C) { index_1 ("0.0186, 0.0966, 0.174, 0.3294, 0.6408, 1.263, 2.5074"); index_2 ("0.001, 0.0234, 0.039, 0.0648, 0.108, 0.18, 0.3"); values ( \ - "0.00350223, 0.00346913, 0.00342893, 0.00333791, 0.00316841, 0.00291664, 0.00245405", \ - "0.00331791, 0.00339462, 0.0032934, 0.00332914, 0.00305446, 0.00282236, 0.00246312", \ - "0.00350462, 0.00336165, 0.00336663, 0.00323191, 0.00345592, 0.00279707, 0.00239852", \ - "0.00419949, 0.00370967, 0.00353484, 0.00345397, 0.00322311, 0.00312291, 0.00259517", \ - "0.00609776, 0.00484495, 0.00451502, 0.00405761, 0.00372909, 0.00352163, 0.0026169", \ - "0.010562, 0.00805875, 0.00717284, 0.00627221, 0.00546722, 0.00440789, 0.00407944", \ - "0.0200848, 0.0159786, 0.0142616, 0.0123941, 0.0104504, 0.00862307, 0.00654249" \ + "0.00351165, 0.00346676, 0.00343465, 0.00333784, 0.00316601, 0.00294713, 0.0024541", \ + "0.00331976, 0.00339374, 0.00334496, 0.0033292, 0.00307447, 0.00281163, 0.00236426", \ + "0.00350297, 0.00335936, 0.00337111, 0.00320637, 0.00320727, 0.00280806, 0.00236352", \ + "0.00419954, 0.00370975, 0.00353483, 0.00345393, 0.00322265, 0.00309619, 0.00262836", \ + "0.0060953, 0.00484577, 0.00451502, 0.0040633, 0.00372958, 0.00352163, 0.0026181", \ + "0.0105633, 0.00805735, 0.00717285, 0.00627226, 0.00545332, 0.00440789, 0.00407944", \ + "0.0200848, 0.0159782, 0.0142616, 0.0123941, 0.0104516, 0.00862307, 0.00654249" \ ); } fall_power (POWER_7x7ds1) { index_1 ("0.0186, 0.0966, 0.174, 0.3294, 0.6408, 1.263, 2.5074"); index_2 ("0.001, 0.0234, 0.039, 0.0648, 0.108, 0.18, 0.3"); values ( \ - "0.0114411, 0.0116268, 0.0115949, 0.0115271, 0.0114159, 0.0111835, 0.0109361", \ - "0.0110198, 0.0114214, 0.0114485, 0.0114355, 0.0113498, 0.0110685, 0.0108991", \ - "0.0109834, 0.0113638, 0.0113162, 0.0113441, 0.0112621, 0.0110087, 0.0108777", \ - "0.0111147, 0.0111845, 0.0112915, 0.0112653, 0.0112699, 0.0110594, 0.010817", \ - "0.0120795, 0.0116368, 0.0115017, 0.0114479, 0.0115419, 0.0110409, 0.0114953", \ - "0.0156471, 0.0135881, 0.0131487, 0.0128066, 0.0122381, 0.0122366, 0.0115529", \ - "0.0246603, 0.020053, 0.0186153, 0.0171895, 0.0160136, 0.0145527, 0.0134652" \ + "0.0114265, 0.0116258, 0.0115981, 0.0115341, 0.011416, 0.0111818, 0.0109371", \ + "0.0110215, 0.0114214, 0.0114484, 0.0114096, 0.0113091, 0.0110688, 0.0108992", \ + "0.0109834, 0.0113638, 0.0113182, 0.0115211, 0.0112614, 0.0110268, 0.0107906", \ + "0.0111153, 0.0111792, 0.0113123, 0.0112827, 0.0112699, 0.0110594, 0.0108169", \ + "0.0120796, 0.0116364, 0.0115029, 0.011448, 0.0114103, 0.0110175, 0.0114952", \ + "0.0156471, 0.0135884, 0.0131484, 0.0128058, 0.0122434, 0.0122364, 0.011548", \ + "0.0246596, 0.0200531, 0.0186161, 0.0171895, 0.0160136, 0.0144885, 0.0135055" \ ); } } @@ -21965,38 +22039,38 @@ library (sg13g2_stdcell_slow_1p35V_125C) { pin (A) { direction : "input"; max_transition : 2.5074; - capacitance : 0.00280417; - rise_capacitance : 0.00281153; - rise_capacitance_range (0.00281153, 0.00281153); - fall_capacitance : 0.00279681; - fall_capacitance_range (0.00279681, 0.00279681); + capacitance : 0.00280421; + rise_capacitance : 0.00281154; + rise_capacitance_range (0.00254257, 0.00302228); + fall_capacitance : 0.00279689; + fall_capacitance_range (0.00239782, 0.00343708); } pin (B) { direction : "input"; max_transition : 2.5074; - capacitance : 0.00296064; - rise_capacitance : 0.00305608; - rise_capacitance_range (0.00305608, 0.00305608); - fall_capacitance : 0.0028652; - fall_capacitance_range (0.0028652, 0.0028652); + capacitance : 0.00296059; + rise_capacitance : 0.003056; + rise_capacitance_range (0.00261931, 0.00335022); + fall_capacitance : 0.00286518; + fall_capacitance_range (0.00255927, 0.00334286); } pin (C) { direction : "input"; max_transition : 2.5074; - capacitance : 0.00298469; - rise_capacitance : 0.00310189; - rise_capacitance_range (0.00310189, 0.00310189); - fall_capacitance : 0.00286748; - fall_capacitance_range (0.00286748, 0.00286748); + capacitance : 0.00298468; + rise_capacitance : 0.00310183; + rise_capacitance_range (0.00265296, 0.00343328); + fall_capacitance : 0.00286753; + fall_capacitance_range (0.00264339, 0.0032401); } pin (D) { direction : "input"; max_transition : 2.5074; - capacitance : 0.00296223; - rise_capacitance : 0.00310278; - rise_capacitance_range (0.00310278, 0.00310278); + capacitance : 0.00296224; + rise_capacitance : 0.00310281; + rise_capacitance_range (0.00264791, 0.0034646); fall_capacitance : 0.00282167; - fall_capacitance_range (0.00282167, 0.00282167); + fall_capacitance_range (0.00268215, 0.00310864); } } cell (sg13g2_nor2_1) { @@ -22202,18 +22276,18 @@ library (sg13g2_stdcell_slow_1p35V_125C) { max_transition : 2.5074; capacitance : 0.00299429; rise_capacitance : 0.00294815; - rise_capacitance_range (0.00294815, 0.00294815); + rise_capacitance_range (0.00269694, 0.00335271); fall_capacitance : 0.00304043; - fall_capacitance_range (0.00304043, 0.00304043); + fall_capacitance_range (0.00259719, 0.00335815); } pin (B) { direction : "input"; max_transition : 2.5074; capacitance : 0.00285646; rise_capacitance : 0.00294211; - rise_capacitance_range (0.00294211, 0.00294211); + rise_capacitance_range (0.00239153, 0.00363163); fall_capacitance : 0.0027708; - fall_capacitance_range (0.0027708, 0.0027708); + fall_capacitance_range (0.00252533, 0.00301292); } } cell (sg13g2_nor2_2) { @@ -22419,18 +22493,18 @@ library (sg13g2_stdcell_slow_1p35V_125C) { max_transition : 2.5074; capacitance : 0.00571985; rise_capacitance : 0.00564091; - rise_capacitance_range (0.00564091, 0.00564091); + rise_capacitance_range (0.00510046, 0.00644909); fall_capacitance : 0.00579879; - fall_capacitance_range (0.00579879, 0.00579879); + fall_capacitance_range (0.00494834, 0.00645401); } pin (B) { direction : "input"; max_transition : 2.5074; capacitance : 0.00549295; rise_capacitance : 0.00567337; - rise_capacitance_range (0.00567337, 0.00567337); + rise_capacitance_range (0.00442741, 0.00716953); fall_capacitance : 0.00531254; - fall_capacitance_range (0.00531254, 0.00531254); + fall_capacitance_range (0.00477587, 0.00580591); } } cell (sg13g2_nor2b_1) { @@ -22636,18 +22710,18 @@ library (sg13g2_stdcell_slow_1p35V_125C) { max_transition : 2.5074; capacitance : 0.00286103; rise_capacitance : 0.0029466; - rise_capacitance_range (0.0029466, 0.0029466); + rise_capacitance_range (0.00239347, 0.00363704); fall_capacitance : 0.00277545; - fall_capacitance_range (0.00277545, 0.00277545); + fall_capacitance_range (0.00252921, 0.00301606); } pin (B_N) { direction : "input"; max_transition : 2.5074; capacitance : 0.0022427; rise_capacitance : 0.0022787; - rise_capacitance_range (0.0022787, 0.0022787); + rise_capacitance_range (0.00202157, 0.00247512); fall_capacitance : 0.00220671; - fall_capacitance_range (0.00220671, 0.00220671); + fall_capacitance_range (0.00200781, 0.00238893); internal_power () { when : "A"; rise_power (passive_POWER_7x1ds1) { @@ -22882,18 +22956,18 @@ library (sg13g2_stdcell_slow_1p35V_125C) { max_transition : 2.5074; capacitance : 0.00554738; rise_capacitance : 0.00572632; - rise_capacitance_range (0.00572632, 0.00572632); + rise_capacitance_range (0.00451092, 0.00714811); fall_capacitance : 0.00536845; - fall_capacitance_range (0.00536845, 0.00536845); + fall_capacitance_range (0.00483542, 0.00590453); } pin (B_N) { direction : "input"; max_transition : 2.5074; capacitance : 0.00264889; rise_capacitance : 0.00269805; - rise_capacitance_range (0.00269805, 0.00269805); + rise_capacitance_range (0.00244533, 0.00291496); fall_capacitance : 0.00259974; - fall_capacitance_range (0.00259974, 0.00259974); + fall_capacitance_range (0.0023961, 0.00278928); internal_power () { when : "A"; rise_power (passive_POWER_7x1ds1) { @@ -23226,27 +23300,27 @@ library (sg13g2_stdcell_slow_1p35V_125C) { max_transition : 2.5074; capacitance : 0.00296654; rise_capacitance : 0.00290327; - rise_capacitance_range (0.00290327, 0.00290327); + rise_capacitance_range (0.00270337, 0.00329018); fall_capacitance : 0.00302981; - fall_capacitance_range (0.00302981, 0.00302981); + fall_capacitance_range (0.00260098, 0.00336947); } pin (B) { direction : "input"; max_transition : 2.5074; capacitance : 0.00296901; rise_capacitance : 0.00295431; - rise_capacitance_range (0.00295431, 0.00295431); + rise_capacitance_range (0.00257276, 0.00353905); fall_capacitance : 0.00298371; - fall_capacitance_range (0.00298371, 0.00298371); + fall_capacitance_range (0.0025527, 0.00326999); } pin (C) { direction : "input"; max_transition : 2.5074; capacitance : 0.00283574; rise_capacitance : 0.00293328; - rise_capacitance_range (0.00293328, 0.00293328); + rise_capacitance_range (0.00236792, 0.00378437); fall_capacitance : 0.0027382; - fall_capacitance_range (0.0027382, 0.0027382); + fall_capacitance_range (0.00250954, 0.00289985); } } cell (sg13g2_nor3_2) { @@ -23550,27 +23624,27 @@ library (sg13g2_stdcell_slow_1p35V_125C) { max_transition : 2.5074; capacitance : 0.00567117; rise_capacitance : 0.00556035; - rise_capacitance_range (0.00556035, 0.00556035); + rise_capacitance_range (0.00515892, 0.00631267); fall_capacitance : 0.00578199; - fall_capacitance_range (0.00578199, 0.00578199); + fall_capacitance_range (0.00490253, 0.00647033); } pin (B) { direction : "input"; max_transition : 2.5074; capacitance : 0.00564388; rise_capacitance : 0.00563219; - rise_capacitance_range (0.00563219, 0.00563219); + rise_capacitance_range (0.0048188, 0.00678443); fall_capacitance : 0.00565556; - fall_capacitance_range (0.00565556, 0.00565556); + fall_capacitance_range (0.00481301, 0.00624889); } pin (C) { direction : "input"; max_transition : 2.5074; capacitance : 0.00544856; rise_capacitance : 0.00565782; - rise_capacitance_range (0.00565782, 0.00565782); + rise_capacitance_range (0.00442026, 0.00744071); fall_capacitance : 0.00523929; - fall_capacitance_range (0.00523929, 0.00523929); + fall_capacitance_range (0.00475474, 0.00558766); } } cell (sg13g2_nor4_1) { @@ -23996,36 +24070,36 @@ library (sg13g2_stdcell_slow_1p35V_125C) { max_transition : 2.5074; capacitance : 0.00294338; rise_capacitance : 0.00288354; - rise_capacitance_range (0.00288354, 0.00288354); + rise_capacitance_range (0.00271527, 0.00322835); fall_capacitance : 0.00300321; - fall_capacitance_range (0.00300321, 0.00300321); + fall_capacitance_range (0.00257462, 0.00335534); } pin (B) { direction : "input"; max_transition : 2.5074; capacitance : 0.00295065; rise_capacitance : 0.00293106; - rise_capacitance_range (0.00293106, 0.00293106); + rise_capacitance_range (0.00261176, 0.00342424); fall_capacitance : 0.00297025; - fall_capacitance_range (0.00297025, 0.00297025); + fall_capacitance_range (0.00253225, 0.00328886); } pin (C) { direction : "input"; max_transition : 2.5074; capacitance : 0.00291686; rise_capacitance : 0.00293177; - rise_capacitance_range (0.00293177, 0.00293177); + rise_capacitance_range (0.00252143, 0.00358228); fall_capacitance : 0.00290196; - fall_capacitance_range (0.00290196, 0.00290196); + fall_capacitance_range (0.00248941, 0.00317368); } pin (D) { direction : "input"; max_transition : 2.5074; capacitance : 0.00276989; rise_capacitance : 0.00288391; - rise_capacitance_range (0.00288391, 0.00288391); + rise_capacitance_range (0.0023475, 0.00376641); fall_capacitance : 0.00265587; - fall_capacitance_range (0.00265587, 0.00265587); + fall_capacitance_range (0.00245013, 0.00278429); } } cell (sg13g2_nor4_2) { @@ -24041,11 +24115,11 @@ library (sg13g2_stdcell_slow_1p35V_125C) { when : "!A&!B&!C&D&!Y"; } leakage_power () { - value : 2036.11; + value : 2036.12; when : "!A&!B&C&!D&!Y"; } leakage_power () { - value : 886.661; + value : 886.662; when : "!A&!B&C&D&!Y"; } leakage_power () { @@ -24053,7 +24127,7 @@ library (sg13g2_stdcell_slow_1p35V_125C) { when : "!A&B&!C&!D&!Y"; } leakage_power () { - value : 886.023; + value : 886.025; when : "!A&B&!C&D&!Y"; } leakage_power () { @@ -24061,7 +24135,7 @@ library (sg13g2_stdcell_slow_1p35V_125C) { when : "!A&B&C&!D&!Y"; } leakage_power () { - value : 798.137; + value : 798.139; when : "!A&B&C&D&!Y"; } leakage_power () { @@ -24069,7 +24143,7 @@ library (sg13g2_stdcell_slow_1p35V_125C) { when : "A&!B&!C&!D&!Y"; } leakage_power () { - value : 884.971; + value : 884.972; when : "A&!B&!C&D&!Y"; } leakage_power () { @@ -24077,7 +24151,7 @@ library (sg13g2_stdcell_slow_1p35V_125C) { when : "A&!B&C&!D&!Y"; } leakage_power () { - value : 790.286; + value : 790.287; when : "A&!B&C&D&!Y"; } leakage_power () { @@ -24085,7 +24159,7 @@ library (sg13g2_stdcell_slow_1p35V_125C) { when : "A&B&!C&!D&!Y"; } leakage_power () { - value : 804.394; + value : 804.396; when : "A&B&!C&D&!Y"; } leakage_power () { @@ -24093,7 +24167,7 @@ library (sg13g2_stdcell_slow_1p35V_125C) { when : "A&B&C&!D&!Y"; } leakage_power () { - value : 778.351; + value : 778.352; when : "A&B&C&D&!Y"; } pin (Y) { @@ -24109,52 +24183,52 @@ library (sg13g2_stdcell_slow_1p35V_125C) { index_1 ("0.0186, 0.0966, 0.174, 0.3294, 0.6408, 1.263, 2.5074"); index_2 ("0.001, 0.0468, 0.078, 0.1296, 0.216, 0.36, 0.6"); values ( \ - "0.110834, 0.393758, 0.583362, 0.896729, 1.42109, 2.29577, 3.75053", \ - "0.131097, 0.414593, 0.604981, 0.919014, 1.44385, 2.31886, 3.77592", \ - "0.143333, 0.429948, 0.620312, 0.934834, 1.45972, 2.33411, 3.79235", \ - "0.15789, 0.455658, 0.64653, 0.960784, 1.48604, 2.36073, 3.81791", \ - "0.1762, 0.498588, 0.694649, 1.01168, 1.53639, 2.41192, 3.87039", \ - "0.200397, 0.566852, 0.773937, 1.10116, 1.63318, 2.50693, 3.96214", \ - "0.251566, 0.686064, 0.91623, 1.26056, 1.81476, 2.70304, 4.15992" \ + "0.110823, 0.393563, 0.583543, 0.896705, 1.42102, 2.29479, 3.75099", \ + "0.131068, 0.414569, 0.604952, 0.918967, 1.4439, 2.31886, 3.77579", \ + "0.143152, 0.429862, 0.620247, 0.934648, 1.45965, 2.33444, 3.79055", \ + "0.157882, 0.455638, 0.646509, 0.960877, 1.48598, 2.36067, 3.81754", \ + "0.176192, 0.498568, 0.694622, 1.01164, 1.53634, 2.4108, 3.87017", \ + "0.200389, 0.566831, 0.773908, 1.10111, 1.63312, 2.5067, 3.96195", \ + "0.250873, 0.686037, 0.916196, 1.26051, 1.81469, 2.70294, 4.16012" \ ); } rise_transition (TIMING_DELAY_7x7ds1) { index_1 ("0.0186, 0.0966, 0.174, 0.3294, 0.6408, 1.263, 2.5074"); index_2 ("0.001, 0.0468, 0.078, 0.1296, 0.216, 0.36, 0.6"); values ( \ - "0.0774556, 0.466695, 0.731821, 1.16892, 1.90164, 3.1239, 5.16069", \ - "0.0798308, 0.466696, 0.731822, 1.1696, 1.90165, 3.12391, 5.1607", \ - "0.085754, 0.467345, 0.731834, 1.16961, 1.90253, 3.12457, 5.16071", \ - "0.0979543, 0.473782, 0.734015, 1.17009, 1.90254, 3.12458, 5.16101", \ - "0.127625, 0.497509, 0.752325, 1.17857, 1.9055, 3.1246, 5.16361", \ - "0.199162, 0.556025, 0.805324, 1.22312, 1.93078, 3.13324, 5.16583", \ - "0.317477, 0.677564, 0.925267, 1.33474, 2.02799, 3.20202, 5.19045" \ + "0.0774859, 0.46689, 0.731344, 1.169, 1.90156, 3.12265, 5.15775", \ + "0.0798274, 0.466891, 0.731721, 1.16956, 1.90172, 3.12369, 5.15947", \ + "0.0857639, 0.467325, 0.735455, 1.1696, 1.90245, 3.1237, 5.16121", \ + "0.0979459, 0.473768, 0.735456, 1.17185, 1.90246, 3.12371, 5.16122", \ + "0.127619, 0.497488, 0.752307, 1.17854, 1.90412, 3.13037, 5.16335", \ + "0.199153, 0.556005, 0.805294, 1.22306, 1.9306, 3.1325, 5.16558", \ + "0.316978, 0.677543, 0.925237, 1.33468, 2.02828, 3.20189, 5.19024" \ ); } cell_fall (TIMING_DELAY_7x7ds1) { index_1 ("0.0186, 0.0966, 0.174, 0.3294, 0.6408, 1.263, 2.5074"); index_2 ("0.001, 0.0468, 0.078, 0.1296, 0.216, 0.36, 0.6"); values ( \ - "0.0286439, 0.0940563, 0.135265, 0.202195, 0.31324, 0.497316, 0.802869", \ - "0.05747, 0.136236, 0.178507, 0.245696, 0.356482, 0.540441, 0.846174", \ - "0.0741589, 0.169454, 0.216903, 0.287792, 0.400191, 0.584002, 0.889853", \ - "0.096237, 0.218777, 0.277245, 0.360051, 0.482655, 0.671577, 0.977645", \ - "0.122406, 0.286474, 0.362321, 0.467307, 0.61486, 0.829138, 1.1483", \ - "0.152, 0.370226, 0.474279, 0.615265, 0.805925, 1.06981, 1.44515", \ - "0.179627, 0.471703, 0.609639, 0.801713, 1.06376, 1.41159, 1.88775" \ + "0.0286463, 0.0940378, 0.135252, 0.202133, 0.313207, 0.497276, 0.802788", \ + "0.0574661, 0.136166, 0.178572, 0.245685, 0.356372, 0.540309, 0.84604", \ + "0.0741557, 0.169456, 0.216826, 0.287735, 0.400183, 0.583959, 0.889605", \ + "0.0962306, 0.218764, 0.277257, 0.360027, 0.482605, 0.671495, 0.977689", \ + "0.122398, 0.286458, 0.3623, 0.467274, 0.614821, 0.828882, 1.14823", \ + "0.15199, 0.370205, 0.474362, 0.615231, 0.805879, 1.06974, 1.44506", \ + "0.179614, 0.471826, 0.609779, 0.801671, 1.0637, 1.41152, 1.88721" \ ); } fall_transition (TIMING_DELAY_7x7ds1) { index_1 ("0.0186, 0.0966, 0.174, 0.3294, 0.6408, 1.263, 2.5074"); index_2 ("0.001, 0.0468, 0.078, 0.1296, 0.216, 0.36, 0.6"); values ( \ - "0.0238877, 0.104923, 0.158153, 0.246224, 0.393782, 0.63886, 1.04824", \ - "0.0412189, 0.114846, 0.164045, 0.248442, 0.39451, 0.639051, 1.04825", \ - "0.0561644, 0.133861, 0.181075, 0.261002, 0.400315, 0.640776, 1.04826", \ - "0.0813384, 0.173069, 0.222018, 0.299788, 0.430242, 0.657348, 1.05344", \ - "0.122142, 0.235858, 0.294023, 0.37696, 0.509719, 0.724285, 1.09519", \ - "0.192792, 0.342614, 0.412781, 0.514302, 0.659156, 0.885713, 1.24348", \ - "0.311105, 0.513529, 0.607604, 0.737729, 0.917596, 1.17772, 1.56193" \ + "0.0238904, 0.104667, 0.158134, 0.246198, 0.39373, 0.638793, 1.0478", \ + "0.0412155, 0.11485, 0.16397, 0.248458, 0.394453, 0.638915, 1.04807", \ + "0.0559531, 0.133883, 0.181103, 0.260836, 0.399877, 0.640164, 1.04808", \ + "0.0813343, 0.17306, 0.22207, 0.299761, 0.430235, 0.657871, 1.05349", \ + "0.122137, 0.235844, 0.294004, 0.377036, 0.509639, 0.724017, 1.09488", \ + "0.192786, 0.342599, 0.412658, 0.514271, 0.659113, 0.885642, 1.24463", \ + "0.311098, 0.513603, 0.606835, 0.737693, 0.917538, 1.17765, 1.56092" \ ); } } @@ -24166,52 +24240,52 @@ library (sg13g2_stdcell_slow_1p35V_125C) { index_1 ("0.0186, 0.0966, 0.174, 0.3294, 0.6408, 1.263, 2.5074"); index_2 ("0.001, 0.0468, 0.078, 0.1296, 0.216, 0.36, 0.6"); values ( \ - "0.106237, 0.389064, 0.578815, 0.892127, 1.417, 2.2903, 3.74641", \ - "0.126759, 0.410825, 0.60125, 0.915263, 1.44011, 2.31518, 3.77092", \ - "0.139652, 0.428677, 0.619026, 0.933682, 1.4585, 2.33292, 3.79114", \ - "0.155891, 0.461551, 0.652666, 0.966844, 1.49276, 2.36652, 3.8237", \ - "0.181673, 0.52115, 0.718822, 1.03615, 1.56119, 2.43542, 3.89477", \ - "0.226711, 0.619049, 0.832983, 1.16476, 1.69814, 2.57247, 4.02717", \ - "0.311501, 0.788505, 1.02547, 1.38941, 1.95346, 2.84933, 4.30755" \ + "0.106234, 0.389046, 0.57879, 0.892065, 1.4163, 2.29105, 3.7476", \ + "0.126785, 0.410805, 0.601222, 0.915243, 1.44007, 2.31511, 3.77073", \ + "0.139647, 0.428655, 0.619002, 0.933393, 1.45848, 2.33282, 3.79097", \ + "0.155884, 0.461533, 0.652641, 0.966796, 1.49189, 2.36642, 3.82354", \ + "0.181666, 0.521132, 0.718794, 1.03613, 1.5611, 2.43672, 3.8946", \ + "0.226702, 0.619029, 0.832956, 1.16428, 1.69807, 2.57239, 4.02698", \ + "0.311486, 0.788481, 1.02543, 1.38937, 1.9534, 2.84923, 4.30751" \ ); } rise_transition (TIMING_DELAY_7x7ds1) { index_1 ("0.0186, 0.0966, 0.174, 0.3294, 0.6408, 1.263, 2.5074"); index_2 ("0.001, 0.0468, 0.078, 0.1296, 0.216, 0.36, 0.6"); values ( \ - "0.0774805, 0.466693, 0.731304, 1.16893, 1.90217, 3.12278, 5.15799", \ - "0.0814847, 0.466694, 0.731864, 1.16894, 1.90218, 3.12387, 5.158", \ - "0.0899954, 0.467606, 0.735405, 1.16932, 1.90219, 3.12471, 5.15968", \ - "0.107478, 0.476536, 0.735406, 1.16952, 1.9022, 3.12472, 5.15969", \ - "0.145464, 0.507553, 0.758541, 1.18156, 1.90752, 3.12796, 5.1597", \ - "0.218041, 0.579438, 0.825092, 1.23655, 1.93668, 3.13454, 5.16155", \ - "0.328513, 0.715554, 0.962907, 1.37156, 2.05746, 3.21623, 5.19444" \ + "0.0774489, 0.466672, 0.731271, 1.16888, 1.90109, 3.12375, 5.1593", \ + "0.0814686, 0.466673, 0.731833, 1.16956, 1.90155, 3.12376, 5.15931", \ + "0.0899903, 0.467573, 0.731834, 1.16957, 1.90156, 3.12459, 5.15947", \ + "0.107473, 0.476597, 0.735174, 1.17114, 1.90206, 3.1246, 5.15948", \ + "0.145458, 0.507586, 0.758508, 1.18154, 1.90518, 3.12513, 5.15949", \ + "0.218035, 0.579418, 0.825052, 1.23588, 1.93669, 3.1348, 5.16133", \ + "0.328505, 0.715534, 0.962877, 1.37151, 2.05738, 3.21613, 5.19452" \ ); } cell_fall (TIMING_DELAY_7x7ds1) { index_1 ("0.0186, 0.0966, 0.174, 0.3294, 0.6408, 1.263, 2.5074"); index_2 ("0.001, 0.0468, 0.078, 0.1296, 0.216, 0.36, 0.6"); values ( \ - "0.0296241, 0.0927536, 0.133245, 0.199658, 0.31034, 0.494057, 0.800292", \ - "0.0566057, 0.134526, 0.176548, 0.243289, 0.353757, 0.537461, 0.843507", \ - "0.0716859, 0.167114, 0.214442, 0.285282, 0.397388, 0.581323, 0.887154", \ - "0.0911543, 0.216078, 0.274868, 0.357848, 0.480489, 0.669523, 0.976247", \ - "0.112249, 0.280179, 0.357127, 0.462905, 0.611041, 0.825885, 1.14559", \ - "0.132128, 0.359156, 0.46553, 0.607915, 0.800396, 1.06554, 1.44228", \ - "0.139714, 0.450574, 0.593201, 0.788994, 1.05454, 1.40506, 1.88275" \ + "0.0296138, 0.0927517, 0.133258, 0.199653, 0.310355, 0.494048, 0.800289", \ + "0.0566259, 0.134525, 0.176544, 0.243287, 0.353678, 0.537499, 0.843458", \ + "0.0716853, 0.167112, 0.214436, 0.285284, 0.397391, 0.581318, 0.887141", \ + "0.0911852, 0.216077, 0.274866, 0.357845, 0.480469, 0.669519, 0.976344", \ + "0.112248, 0.280177, 0.357125, 0.462962, 0.611179, 0.826071, 1.14574", \ + "0.132127, 0.359268, 0.465575, 0.608243, 0.800494, 1.06555, 1.44196", \ + "0.139712, 0.450573, 0.593199, 0.788989, 1.05454, 1.40471, 1.88289" \ ); } fall_transition (TIMING_DELAY_7x7ds1) { index_1 ("0.0186, 0.0966, 0.174, 0.3294, 0.6408, 1.263, 2.5074"); index_2 ("0.001, 0.0468, 0.078, 0.1296, 0.216, 0.36, 0.6"); values ( \ - "0.0222904, 0.100652, 0.154068, 0.242169, 0.389623, 0.635453, 1.04571", \ - "0.0380169, 0.111274, 0.160297, 0.244419, 0.390698, 0.635454, 1.04572", \ - "0.0518389, 0.130453, 0.177528, 0.25722, 0.396679, 0.637407, 1.04573", \ - "0.0757733, 0.168474, 0.217235, 0.2956, 0.426508, 0.65396, 1.05039", \ - "0.115128, 0.231483, 0.28901, 0.373228, 0.506769, 0.721215, 1.09159", \ - "0.182327, 0.336737, 0.408578, 0.509289, 0.655718, 0.882708, 1.24097", \ - "0.293762, 0.505397, 0.601066, 0.732177, 0.913928, 1.17446, 1.55816" \ + "0.0222864, 0.100616, 0.154061, 0.242165, 0.389619, 0.63545, 1.04569", \ + "0.0380231, 0.111272, 0.160244, 0.244388, 0.391419, 0.635451, 1.0457", \ + "0.051838, 0.130452, 0.17754, 0.257219, 0.396711, 0.637399, 1.04571", \ + "0.0757603, 0.168473, 0.21776, 0.295612, 0.426488, 0.653964, 1.05051", \ + "0.115127, 0.231482, 0.289008, 0.373284, 0.50662, 0.721222, 1.09254", \ + "0.182326, 0.336578, 0.408052, 0.509047, 0.655811, 0.88269, 1.24201", \ + "0.293761, 0.505393, 0.601062, 0.732174, 0.913417, 1.17479, 1.56082" \ ); } } @@ -24223,52 +24297,52 @@ library (sg13g2_stdcell_slow_1p35V_125C) { index_1 ("0.0186, 0.0966, 0.174, 0.3294, 0.6408, 1.263, 2.5074"); index_2 ("0.001, 0.0468, 0.078, 0.1296, 0.216, 0.36, 0.6"); values ( \ - "0.0911, 0.374007, 0.563668, 0.876983, 1.40138, 2.27517, 3.7314", \ - "0.110532, 0.395716, 0.587044, 0.900131, 1.42502, 2.2991, 3.7573", \ - "0.123815, 0.417275, 0.608055, 0.922607, 1.44726, 2.32276, 3.77843", \ - "0.143898, 0.460868, 0.652242, 0.966303, 1.49153, 2.36592, 3.82307", \ - "0.18169, 0.540892, 0.741585, 1.05974, 1.58459, 2.45826, 3.91763", \ - "0.246815, 0.669822, 0.894515, 1.23269, 1.76815, 2.64322, 4.09776", \ - "0.354148, 0.876612, 1.13614, 1.52406, 2.10651, 3.01168, 4.46989" \ + "0.0910878, 0.373988, 0.563646, 0.876944, 1.40126, 2.27508, 3.73122", \ + "0.110517, 0.395698, 0.586034, 0.9001, 1.42484, 2.29915, 3.75715", \ + "0.123811, 0.417234, 0.608033, 0.922597, 1.4472, 2.32267, 3.77828", \ + "0.143893, 0.460859, 0.65222, 0.966277, 1.49202, 2.36582, 3.82294", \ + "0.181685, 0.540899, 0.741563, 1.05943, 1.58429, 2.45962, 3.91741", \ + "0.246807, 0.669798, 0.894491, 1.23265, 1.76808, 2.64309, 4.09756", \ + "0.354134, 0.876589, 1.1361, 1.52402, 2.10675, 3.01158, 4.46968" \ ); } rise_transition (TIMING_DELAY_7x7ds1) { index_1 ("0.0186, 0.0966, 0.174, 0.3294, 0.6408, 1.263, 2.5074"); index_2 ("0.001, 0.0468, 0.078, 0.1296, 0.216, 0.36, 0.6"); values ( \ - "0.0775072, 0.46671, 0.731301, 1.16893, 1.90164, 3.12278, 5.158", \ - "0.084221, 0.466711, 0.732573, 1.16894, 1.90281, 3.12279, 5.15984", \ - "0.0955391, 0.468324, 0.733969, 1.17018, 1.90285, 3.12381, 5.15985", \ - "0.117063, 0.480528, 0.73698, 1.17094, 1.90286, 3.12432, 5.15986", \ - "0.155967, 0.521378, 0.766929, 1.1853, 1.90992, 3.12501, 5.16022", \ - "0.219027, 0.607118, 0.852199, 1.25622, 1.94677, 3.13692, 5.16023", \ - "0.323296, 0.752665, 1.01365, 1.42906, 2.10356, 3.24064, 5.20411" \ + "0.0774816, 0.466689, 0.731271, 1.16888, 1.90272, 3.12265, 5.16085", \ + "0.0841877, 0.46669, 0.731671, 1.16889, 1.90273, 3.12266, 5.16086", \ + "0.0955354, 0.468462, 0.733939, 1.17016, 1.90277, 3.12368, 5.16087", \ + "0.117058, 0.480513, 0.736949, 1.17017, 1.90278, 3.12415, 5.16088", \ + "0.155961, 0.52146, 0.766898, 1.18522, 1.91067, 3.12416, 5.16089", \ + "0.219022, 0.607074, 0.852171, 1.25616, 1.94645, 3.13672, 5.1609", \ + "0.323296, 0.752647, 1.01347, 1.42902, 2.10372, 3.24066, 5.20416" \ ); } cell_fall (TIMING_DELAY_7x7ds1) { index_1 ("0.0186, 0.0966, 0.174, 0.3294, 0.6408, 1.263, 2.5074"); index_2 ("0.001, 0.0468, 0.078, 0.1296, 0.216, 0.36, 0.6"); values ( \ - "0.028543, 0.0891414, 0.129151, 0.195086, 0.305453, 0.489008, 0.794967", \ - "0.0524767, 0.130921, 0.172742, 0.239089, 0.349257, 0.532779, 0.838612", \ - "0.0652564, 0.162621, 0.210155, 0.281007, 0.393047, 0.576575, 0.882295", \ - "0.0805467, 0.2098, 0.269424, 0.352816, 0.47577, 0.664893, 0.971391", \ - "0.094718, 0.271004, 0.34938, 0.456268, 0.605335, 0.821029, 1.14103", \ - "0.102644, 0.344185, 0.452435, 0.598457, 0.792752, 1.05923, 1.43612", \ - "0.102645, 0.425181, 0.572827, 0.773023, 1.04321, 1.39546, 1.87562" \ + "0.028546, 0.0891495, 0.129118, 0.195094, 0.305449, 0.488974, 0.794851", \ + "0.0524762, 0.13092, 0.172739, 0.23909, 0.349254, 0.53284, 0.838628", \ + "0.0652557, 0.16262, 0.210155, 0.281007, 0.393017, 0.576602, 0.882475", \ + "0.080546, 0.2098, 0.269427, 0.352826, 0.47577, 0.664892, 0.971565", \ + "0.0947175, 0.271004, 0.34938, 0.456342, 0.60537, 0.820779, 1.14102", \ + "0.102642, 0.344232, 0.452643, 0.598471, 0.79275, 1.05901, 1.43671", \ + "0.102643, 0.425666, 0.572833, 0.77302, 1.0432, 1.39547, 1.8756" \ ); } fall_transition (TIMING_DELAY_7x7ds1) { index_1 ("0.0186, 0.0966, 0.174, 0.3294, 0.6408, 1.263, 2.5074"); index_2 ("0.001, 0.0468, 0.078, 0.1296, 0.216, 0.36, 0.6"); values ( \ - "0.0185976, 0.0958056, 0.149111, 0.237285, 0.384738, 0.6308, 1.03967", \ - "0.0338554, 0.107048, 0.155792, 0.239813, 0.386496, 0.630801, 1.04038", \ - "0.0468442, 0.12607, 0.173401, 0.252823, 0.391917, 0.631863, 1.04044", \ - "0.0693537, 0.164136, 0.213336, 0.291815, 0.422126, 0.649309, 1.04584", \ - "0.107621, 0.225818, 0.284389, 0.368737, 0.502348, 0.716902, 1.0879", \ - "0.171417, 0.329505, 0.403182, 0.504261, 0.651483, 0.878414, 1.23775", \ - "0.27845, 0.499818, 0.594631, 0.727086, 0.908964, 1.1705, 1.55649" \ + "0.0186045, 0.0957996, 0.149109, 0.237285, 0.384737, 0.6308, 1.04061", \ + "0.0338551, 0.107048, 0.155736, 0.239812, 0.386472, 0.630801, 1.04062", \ + "0.046844, 0.126066, 0.173401, 0.252822, 0.391586, 0.63244, 1.04063", \ + "0.0693533, 0.164136, 0.213338, 0.291818, 0.422126, 0.649308, 1.04517", \ + "0.10762, 0.225818, 0.284392, 0.368632, 0.502328, 0.716511, 1.08788", \ + "0.171419, 0.329846, 0.402997, 0.504336, 0.651484, 0.87848, 1.23802", \ + "0.278448, 0.498421, 0.594625, 0.727088, 0.908961, 1.1705, 1.55643" \ ); } } @@ -24280,52 +24354,52 @@ library (sg13g2_stdcell_slow_1p35V_125C) { index_1 ("0.0186, 0.0966, 0.174, 0.3294, 0.6408, 1.263, 2.5074"); index_2 ("0.001, 0.0468, 0.078, 0.1296, 0.216, 0.36, 0.6"); values ( \ - "0.0610804, 0.346608, 0.536533, 0.850064, 1.37449, 2.24835, 3.7046", \ - "0.0840652, 0.368909, 0.559734, 0.873962, 1.3998, 2.27441, 3.7304", \ - "0.102098, 0.395545, 0.585653, 0.899774, 1.42566, 2.29971, 3.75543", \ - "0.12989, 0.450637, 0.64044, 0.952767, 1.47711, 2.35138, 3.80803", \ - "0.176586, 0.549623, 0.751189, 1.06717, 1.58861, 2.46031, 3.91782", \ - "0.247916, 0.697371, 0.931213, 1.27602, 1.81314, 2.68154, 4.1311", \ - "0.364343, 0.919826, 1.19773, 1.60915, 2.2116, 3.12703, 4.58115" \ + "0.0610803, 0.346714, 0.536511, 0.850032, 1.37443, 2.24826, 3.70589", \ + "0.0840628, 0.368834, 0.559713, 0.873888, 1.39976, 2.27432, 3.73025", \ + "0.102095, 0.395522, 0.585705, 0.899746, 1.42561, 2.30039, 3.75609", \ + "0.129887, 0.450612, 0.640444, 0.952947, 1.47719, 2.35131, 3.8077", \ + "0.176581, 0.549609, 0.751169, 1.0671, 1.58855, 2.4614, 3.91765", \ + "0.247908, 0.697355, 0.931191, 1.27599, 1.81309, 2.68142, 4.13051", \ + "0.364331, 0.919806, 1.1977, 1.60911, 2.21155, 3.12695, 4.58096" \ ); } rise_transition (TIMING_DELAY_7x7ds1) { index_1 ("0.0186, 0.0966, 0.174, 0.3294, 0.6408, 1.263, 2.5074"); index_2 ("0.001, 0.0468, 0.078, 0.1296, 0.216, 0.36, 0.6"); values ( \ - "0.0756951, 0.466948, 0.731116, 1.16897, 1.90164, 3.12278, 5.158", \ - "0.0847383, 0.467061, 0.731764, 1.16962, 1.90225, 3.12382, 5.15801", \ - "0.0961555, 0.468571, 0.731892, 1.16981, 1.90226, 3.12463, 5.15995", \ - "0.114704, 0.485494, 0.738708, 1.17095, 1.90227, 3.12464, 5.16101", \ - "0.148078, 0.53854, 0.78047, 1.19211, 1.91213, 3.12465, 5.16102", \ - "0.206928, 0.639981, 0.888011, 1.28927, 1.96732, 3.14394, 5.16103", \ - "0.309418, 0.802242, 1.08044, 1.50392, 2.17741, 3.29529, 5.22761" \ + "0.0756704, 0.466669, 0.731081, 1.16892, 1.90156, 3.12265, 5.15961", \ + "0.084732, 0.466749, 0.731731, 1.16957, 1.90218, 3.12369, 5.15962", \ + "0.0960847, 0.468589, 0.731732, 1.16975, 1.90219, 3.1237, 5.16029", \ + "0.1147, 0.485458, 0.738692, 1.17413, 1.9022, 3.12371, 5.1603", \ + "0.148074, 0.538519, 0.780441, 1.19203, 1.91204, 3.12372, 5.16031", \ + "0.206923, 0.639964, 0.887988, 1.28923, 1.96721, 3.14272, 5.16119", \ + "0.309413, 0.802226, 1.07902, 1.50388, 2.17734, 3.29517, 5.22632" \ ); } cell_fall (TIMING_DELAY_7x7ds1) { index_1 ("0.0186, 0.0966, 0.174, 0.3294, 0.6408, 1.263, 2.5074"); index_2 ("0.001, 0.0468, 0.078, 0.1296, 0.216, 0.36, 0.6"); values ( \ - "0.0239588, 0.0842035, 0.123933, 0.189646, 0.299717, 0.482985, 0.788259", \ - "0.0431424, 0.125554, 0.167652, 0.233892, 0.343741, 0.526909, 0.832229", \ - "0.0523714, 0.156256, 0.2044, 0.275582, 0.387451, 0.570756, 0.876075", \ - "0.0618515, 0.200386, 0.261252, 0.345539, 0.469018, 0.658081, 0.964058", \ - "0.0665229, 0.258706, 0.339726, 0.448066, 0.598056, 0.814451, 1.134", \ - "0.0665239, 0.32581, 0.438476, 0.586292, 0.782893, 1.05089, 1.42888", \ - "0.0665249, 0.396164, 0.549352, 0.754299, 1.02878, 1.38444, 1.8657" \ + "0.0239558, 0.0841947, 0.123935, 0.189642, 0.29972, 0.482991, 0.788105", \ + "0.0431419, 0.125555, 0.167652, 0.233894, 0.343754, 0.526918, 0.832241", \ + "0.0523707, 0.156256, 0.2044, 0.275583, 0.387451, 0.570802, 0.875965", \ + "0.0618506, 0.200386, 0.261251, 0.345539, 0.469008, 0.658081, 0.964021", \ + "0.0664021, 0.258705, 0.339725, 0.448065, 0.598055, 0.814451, 1.13404", \ + "0.0664031, 0.325929, 0.43833, 0.58672, 0.782919, 1.05087, 1.42878", \ + "0.0664041, 0.396053, 0.549346, 0.754503, 1.02763, 1.3842, 1.86623" \ ); } fall_transition (TIMING_DELAY_7x7ds1) { index_1 ("0.0186, 0.0966, 0.174, 0.3294, 0.6408, 1.263, 2.5074"); index_2 ("0.001, 0.0468, 0.078, 0.1296, 0.216, 0.36, 0.6"); values ( \ - "0.0140972, 0.0903539, 0.143426, 0.2314, 0.378522, 0.623853, 1.03196", \ - "0.0289429, 0.102316, 0.150533, 0.234115, 0.378933, 0.623854, 1.03209", \ - "0.0413665, 0.121455, 0.168589, 0.247503, 0.38561, 0.625192, 1.03234", \ - "0.0629793, 0.159494, 0.209012, 0.287128, 0.416747, 0.643049, 1.03777", \ - "0.0996573, 0.220781, 0.279246, 0.363617, 0.49773, 0.710851, 1.08011", \ - "0.161601, 0.323818, 0.397865, 0.49921, 0.646289, 0.872077, 1.2297", \ - "0.266464, 0.493944, 0.590686, 0.7224, 0.903455, 1.16794, 1.54641" \ + "0.0140978, 0.0903667, 0.143425, 0.231403, 0.378521, 0.623831, 1.03255", \ + "0.0289426, 0.102412, 0.150541, 0.234033, 0.378947, 0.623832, 1.03256", \ + "0.0413661, 0.121454, 0.168588, 0.247382, 0.38561, 0.625253, 1.03257", \ + "0.062979, 0.159485, 0.209011, 0.287128, 0.416744, 0.643156, 1.0384", \ + "0.0996543, 0.22078, 0.279246, 0.363617, 0.49669, 0.710851, 1.08065", \ + "0.161601, 0.323701, 0.398189, 0.498966, 0.646226, 0.872094, 1.22978", \ + "0.266405, 0.493412, 0.590693, 0.723893, 0.904661, 1.16414, 1.54743" \ ); } } @@ -24335,26 +24409,26 @@ library (sg13g2_stdcell_slow_1p35V_125C) { index_1 ("0.0186, 0.0966, 0.174, 0.3294, 0.6408, 1.263, 2.5074"); index_2 ("0.001, 0.0468, 0.078, 0.1296, 0.216, 0.36, 0.6"); values ( \ - "0.0241579, 0.0246292, 0.0245762, 0.0244021, 0.0240859, 0.0240078, 0.0240358", \ - "0.0236995, 0.0241688, 0.0242352, 0.0241817, 0.0239481, 0.0239111, 0.0239663", \ - "0.0235593, 0.0239824, 0.0240157, 0.0240176, 0.0238752, 0.0238126, 0.0239081", \ - "0.023659, 0.023857, 0.0239219, 0.0238175, 0.0236776, 0.0234991, 0.0238608", \ - "0.0250421, 0.024171, 0.0242827, 0.0238639, 0.0236634, 0.023735, 0.023736", \ - "0.0316398, 0.0277746, 0.0268444, 0.0260874, 0.025016, 0.0251977, 0.0247139", \ - "0.0496793, 0.0401553, 0.0376928, 0.0349551, 0.0320201, 0.0305612, 0.0281791" \ + "0.0241569, 0.0246249, 0.0245591, 0.024418, 0.0240824, 0.0240349, 0.023968", \ + "0.0237, 0.0241782, 0.0242132, 0.0241749, 0.0239746, 0.0239218, 0.0239674", \ + "0.0235334, 0.0239798, 0.0242517, 0.024022, 0.0238731, 0.0237905, 0.0237927", \ + "0.0236581, 0.0239178, 0.0238846, 0.0239003, 0.0236754, 0.0236879, 0.0236727", \ + "0.0250422, 0.0242001, 0.0241285, 0.0238646, 0.0235995, 0.0241115, 0.0237336", \ + "0.031637, 0.0277699, 0.0268036, 0.0260556, 0.0251012, 0.0255447, 0.0245221", \ + "0.0496765, 0.0401542, 0.0376883, 0.0349108, 0.0321216, 0.0300198, 0.0276101" \ ); } fall_power (POWER_7x7ds1) { index_1 ("0.0186, 0.0966, 0.174, 0.3294, 0.6408, 1.263, 2.5074"); index_2 ("0.001, 0.0468, 0.078, 0.1296, 0.216, 0.36, 0.6"); values ( \ - "0.0085888, 0.00852414, 0.00839757, 0.00819728, 0.0080387, 0.00761647, 0.00679302", \ - "0.00812159, 0.00808265, 0.00814107, 0.00791476, 0.0078094, 0.00722794, 0.00644107", \ - "0.00832033, 0.00820859, 0.00806256, 0.00793859, 0.00768034, 0.00742793, 0.00640515", \ - "0.00937262, 0.00881408, 0.00855749, 0.00818771, 0.00772672, 0.00758521, 0.00866521", \ - "0.0127221, 0.0104039, 0.00992639, 0.00934534, 0.008731, 0.00761811, 0.00818705", \ - "0.020625, 0.0158162, 0.0142174, 0.0127772, 0.0116422, 0.0103702, 0.00794055", \ - "0.0384282, 0.0298445, 0.0266232, 0.0229794, 0.0195558, 0.0166192, 0.0145398" \ + "0.00856689, 0.00848266, 0.00840084, 0.00822906, 0.00803999, 0.00763616, 0.00679317", \ + "0.00814133, 0.00807078, 0.00818285, 0.00790166, 0.00778587, 0.00722559, 0.00654727", \ + "0.00832959, 0.00817347, 0.0080171, 0.00792254, 0.00772004, 0.00743689, 0.00649914", \ + "0.0093696, 0.00883295, 0.00859133, 0.00808388, 0.00775268, 0.00833558, 0.00852891", \ + "0.0127251, 0.0103916, 0.00993238, 0.00936467, 0.00871169, 0.00759302, 0.00816441", \ + "0.0206288, 0.0158204, 0.014236, 0.0127824, 0.0116279, 0.0102912, 0.00812229", \ + "0.0384332, 0.0298484, 0.0266821, 0.0230015, 0.0195644, 0.0166845, 0.0143407" \ ); } } @@ -24364,26 +24438,26 @@ library (sg13g2_stdcell_slow_1p35V_125C) { index_1 ("0.0186, 0.0966, 0.174, 0.3294, 0.6408, 1.263, 2.5074"); index_2 ("0.001, 0.0468, 0.078, 0.1296, 0.216, 0.36, 0.6"); values ( \ - "0.0197104, 0.0201769, 0.0201325, 0.0199569, 0.0196661, 0.0195896, 0.0193729", \ - "0.0192399, 0.0197178, 0.019799, 0.0197253, 0.0195026, 0.0195423, 0.0193101", \ - "0.0191094, 0.019701, 0.0197974, 0.0195779, 0.0193877, 0.0193747, 0.0194488", \ - "0.0193202, 0.0193781, 0.0194535, 0.0193385, 0.0191903, 0.0191887, 0.0192573", \ - "0.0211111, 0.0199626, 0.0199057, 0.0195085, 0.0193227, 0.0195016, 0.0191661", \ - "0.0279706, 0.0237835, 0.0226481, 0.0218651, 0.0206869, 0.0212757, 0.0199585", \ - "0.0447057, 0.0357868, 0.0329639, 0.0304497, 0.0273722, 0.0260056, 0.0231387" \ + "0.0197059, 0.0201709, 0.0201322, 0.0199574, 0.0196292, 0.0196358, 0.0195294", \ + "0.0192385, 0.0197181, 0.0197993, 0.019733, 0.0194963, 0.0195439, 0.0193006", \ + "0.0191076, 0.0197297, 0.019544, 0.0195459, 0.0193976, 0.019378, 0.0194473", \ + "0.0193188, 0.0193639, 0.0194539, 0.0194261, 0.0192244, 0.0192994, 0.0190575", \ + "0.0211089, 0.0199424, 0.0198936, 0.0195128, 0.0191766, 0.0193629, 0.0191315", \ + "0.0279719, 0.0237809, 0.0227131, 0.0218317, 0.0207077, 0.0207611, 0.0197375", \ + "0.0447075, 0.0357849, 0.032961, 0.0304378, 0.0273793, 0.0258747, 0.0243051" \ ); } fall_power (POWER_7x7ds1) { index_1 ("0.0186, 0.0966, 0.174, 0.3294, 0.6408, 1.263, 2.5074"); index_2 ("0.001, 0.0468, 0.078, 0.1296, 0.216, 0.36, 0.6"); values ( \ - "0.0079048, 0.00785487, 0.00781271, 0.00762116, 0.00735857, 0.00688966, 0.00628206", \ - "0.00742526, 0.00752687, 0.00764429, 0.00749292, 0.00729616, 0.00658181, 0.00588743", \ - "0.00755573, 0.00765167, 0.00750473, 0.00743901, 0.00743204, 0.00680385, 0.00602502", \ - "0.00862139, 0.0081328, 0.00791889, 0.00763332, 0.00722241, 0.00800869, 0.00618405", \ - "0.0117683, 0.00969784, 0.00918091, 0.00877835, 0.00838438, 0.00726241, 0.00759881", \ - "0.0192702, 0.0147332, 0.0134475, 0.0118758, 0.0110217, 0.00984408, 0.00747739", \ - "0.0356225, 0.0277874, 0.0249839, 0.0215683, 0.0185306, 0.0158941, 0.0134526" \ + "0.00790864, 0.00786146, 0.00781365, 0.00762067, 0.00736323, 0.00690175, 0.0062837", \ + "0.00741357, 0.00752468, 0.00762327, 0.00735997, 0.00755073, 0.0066479, 0.00585707", \ + "0.00755516, 0.00765099, 0.00753997, 0.00747727, 0.00743709, 0.00680406, 0.0060608", \ + "0.0086247, 0.00813187, 0.00799284, 0.00769546, 0.007255, 0.00751123, 0.00613305", \ + "0.0117716, 0.00969742, 0.00917657, 0.00880039, 0.00827074, 0.00722421, 0.0077803", \ + "0.0192703, 0.014739, 0.01338, 0.0119428, 0.0110487, 0.00990069, 0.0079159", \ + "0.0356246, 0.0277879, 0.0249848, 0.0215686, 0.0186391, 0.0158245, 0.0138099" \ ); } } @@ -24393,26 +24467,26 @@ library (sg13g2_stdcell_slow_1p35V_125C) { index_1 ("0.0186, 0.0966, 0.174, 0.3294, 0.6408, 1.263, 2.5074"); index_2 ("0.001, 0.0468, 0.078, 0.1296, 0.216, 0.36, 0.6"); values ( \ - "0.015213, 0.0156882, 0.0156327, 0.0154588, 0.0151473, 0.0150925, 0.0151713", \ - "0.01474, 0.0152091, 0.0153531, 0.0152247, 0.015033, 0.0148913, 0.0149986", \ - "0.014715, 0.0151672, 0.015222, 0.0151461, 0.0149192, 0.0148535, 0.0147304", \ - "0.0152689, 0.0151101, 0.015082, 0.0149636, 0.0148056, 0.0148673, 0.014807", \ - "0.0178584, 0.0160243, 0.0159233, 0.0153171, 0.0151465, 0.015094, 0.0148456", \ - "0.0249751, 0.02037, 0.0191614, 0.01811, 0.0166256, 0.0169901, 0.0155696", \ - "0.0406038, 0.0319075, 0.0293926, 0.0267878, 0.0237878, 0.0220953, 0.0198254" \ + "0.0152105, 0.0156827, 0.0156271, 0.0154604, 0.0151687, 0.0150955, 0.014894", \ + "0.0147477, 0.0152024, 0.0152935, 0.0152231, 0.0150256, 0.0150142, 0.0149903", \ + "0.0147166, 0.015204, 0.0152216, 0.0151464, 0.0149188, 0.0148584, 0.0147303", \ + "0.015271, 0.0150721, 0.0150819, 0.0149368, 0.0148057, 0.0148921, 0.0148283", \ + "0.017861, 0.0160287, 0.0159391, 0.0152941, 0.0151463, 0.0148674, 0.0151015", \ + "0.0249753, 0.0203621, 0.0191581, 0.0181126, 0.0166127, 0.0170354, 0.0153597", \ + "0.0406028, 0.0319058, 0.0293893, 0.0268854, 0.0237369, 0.021724, 0.0188329" \ ); } fall_power (POWER_7x7ds1) { index_1 ("0.0186, 0.0966, 0.174, 0.3294, 0.6408, 1.263, 2.5074"); index_2 ("0.001, 0.0468, 0.078, 0.1296, 0.216, 0.36, 0.6"); values ( \ - "0.0062248, 0.00634575, 0.00627698, 0.0061418, 0.00589716, 0.00551942, 0.00461502", \ - "0.00592407, 0.00630746, 0.00642496, 0.006207, 0.00635946, 0.00563063, 0.00475871", \ - "0.0061529, 0.00644891, 0.00638811, 0.0063398, 0.0061821, 0.00563469, 0.00496295", \ - "0.00725816, 0.00691185, 0.00683684, 0.00656882, 0.0061463, 0.00662428, 0.0071475", \ - "0.0105224, 0.00842439, 0.0079354, 0.00759515, 0.00720204, 0.00612629, 0.00680359", \ - "0.0175822, 0.0133726, 0.0121662, 0.0106549, 0.00986793, 0.00875333, 0.00651594", \ - "0.0329535, 0.0255039, 0.0229817, 0.0199332, 0.0171065, 0.0145297, 0.0126886" \ + "0.00623147, 0.00633598, 0.00626654, 0.00614514, 0.00589889, 0.00550772, 0.00476027", \ + "0.00591869, 0.00630814, 0.00641523, 0.00620685, 0.0063453, 0.00564372, 0.00472265", \ + "0.00615459, 0.00645163, 0.00638801, 0.00633967, 0.0062973, 0.00572488, 0.00492418", \ + "0.00725275, 0.00690668, 0.00682672, 0.00651113, 0.00614619, 0.00704447, 0.00568915", \ + "0.0105231, 0.00842558, 0.00793344, 0.00759709, 0.00716238, 0.00614917, 0.00680383", \ + "0.0175824, 0.0133674, 0.0122049, 0.0105722, 0.00986735, 0.00872497, 0.00664251", \ + "0.0329539, 0.0255402, 0.0229815, 0.0199341, 0.0171044, 0.01453, 0.012569" \ ); } } @@ -24422,26 +24496,26 @@ library (sg13g2_stdcell_slow_1p35V_125C) { index_1 ("0.0186, 0.0966, 0.174, 0.3294, 0.6408, 1.263, 2.5074"); index_2 ("0.001, 0.0468, 0.078, 0.1296, 0.216, 0.36, 0.6"); values ( \ - "0.009943, 0.0108276, 0.0107667, 0.010671, 0.0103527, 0.0103125, 0.0103885", \ - "0.00977376, 0.0102237, 0.0103252, 0.0103219, 0.0101719, 0.0101259, 0.0100036", \ - "0.0103728, 0.010244, 0.0101981, 0.0102107, 0.0100339, 0.0100881, 0.0102399", \ - "0.011947, 0.0107635, 0.0106446, 0.010319, 0.0100367, 0.00983962, 0.0101399", \ - "0.0153958, 0.0126368, 0.0120367, 0.0112336, 0.0108384, 0.0102799, 0.0102803", \ - "0.0230801, 0.0181029, 0.0165671, 0.0151417, 0.013308, 0.0134543, 0.0113265", \ - "0.0392465, 0.0304708, 0.0278811, 0.0248666, 0.0214658, 0.0196127, 0.0169081" \ + "0.00989959, 0.0108014, 0.0107628, 0.010667, 0.0103511, 0.0103148, 0.0103139", \ + "0.00976548, 0.0102044, 0.0103227, 0.0103184, 0.010173, 0.0101254, 0.0100039", \ + "0.0103789, 0.0102499, 0.0101905, 0.0102099, 0.0100341, 0.00998781, 0.0102147", \ + "0.0119475, 0.0106932, 0.0106445, 0.0105142, 0.0100161, 0.00993641, 0.00974885", \ + "0.0153951, 0.0126333, 0.0121879, 0.0112382, 0.0108371, 0.0103505, 0.0102229", \ + "0.0230829, 0.0181127, 0.0165684, 0.015132, 0.0132902, 0.0121921, 0.0114254", \ + "0.0392445, 0.0304781, 0.0278428, 0.0248621, 0.0214692, 0.0196333, 0.0168771" \ ); } fall_power (POWER_7x7ds1) { index_1 ("0.0186, 0.0966, 0.174, 0.3294, 0.6408, 1.263, 2.5074"); index_2 ("0.001, 0.0468, 0.078, 0.1296, 0.216, 0.36, 0.6"); values ( \ - "0.00428001, 0.00508609, 0.00500675, 0.00491738, 0.00469193, 0.00437815, 0.0034519", \ - "0.00427251, 0.00506858, 0.00524171, 0.00512361, 0.00503497, 0.00463064, 0.00378591", \ - "0.0046899, 0.00520294, 0.00516384, 0.00521454, 0.00533666, 0.00490312, 0.00399807", \ - "0.00599085, 0.00576108, 0.00576895, 0.00553369, 0.00515446, 0.00584919, 0.00513196", \ - "0.00937021, 0.00717656, 0.00671116, 0.00652073, 0.00614707, 0.00500757, 0.0055075", \ - "0.0169692, 0.0120129, 0.0108138, 0.00943102, 0.00866199, 0.00758297, 0.00530126", \ - "0.0329777, 0.0243098, 0.0214188, 0.0182488, 0.0157578, 0.0135576, 0.0109813" \ + "0.00428078, 0.00517459, 0.00500737, 0.00491621, 0.00469574, 0.00437939, 0.00354151", \ + "0.00427222, 0.00509097, 0.00524172, 0.00511196, 0.00503829, 0.00463669, 0.00376675", \ + "0.00469108, 0.00520267, 0.00516384, 0.00517638, 0.00533666, 0.00488233, 0.00397057", \ + "0.0059887, 0.00575798, 0.00576896, 0.00553363, 0.0050842, 0.00509448, 0.00456936", \ + "0.00936246, 0.00717362, 0.00671084, 0.00652049, 0.0059927, 0.00500757, 0.00523967", \ + "0.0169659, 0.0120036, 0.0108559, 0.00938199, 0.00865724, 0.00758802, 0.00527643", \ + "0.0329804, 0.0242988, 0.0214196, 0.0184064, 0.0155845, 0.0132205, 0.0110405" \ ); } } @@ -24449,74 +24523,74 @@ library (sg13g2_stdcell_slow_1p35V_125C) { pin (A) { direction : "input"; max_transition : 2.5074; - capacitance : 0.00567299; - rise_capacitance : 0.00555525; - rise_capacitance_range (0.00555525, 0.00555525); - fall_capacitance : 0.00579074; - fall_capacitance_range (0.00579074, 0.00579074); + capacitance : 0.00567591; + rise_capacitance : 0.00555824; + rise_capacitance_range (0.00522084, 0.0062588); + fall_capacitance : 0.00579358; + fall_capacitance_range (0.00494053, 0.00650139); } pin (B) { direction : "input"; max_transition : 2.5074; - capacitance : 0.00561145; - rise_capacitance : 0.00557502; - rise_capacitance_range (0.00557502, 0.00557502); - fall_capacitance : 0.00564789; - fall_capacitance_range (0.00564789, 0.00564789); + capacitance : 0.0056115; + rise_capacitance : 0.00557517; + rise_capacitance_range (0.00494119, 0.00657995); + fall_capacitance : 0.00564784; + fall_capacitance_range (0.00480457, 0.00629753); } pin (C) { direction : "input"; max_transition : 2.5074; - capacitance : 0.00556339; - rise_capacitance : 0.00559468; - rise_capacitance_range (0.00559468, 0.00559468); - fall_capacitance : 0.00553209; - fall_capacitance_range (0.00553209, 0.00553209); + capacitance : 0.0055634; + rise_capacitance : 0.00559469; + rise_capacitance_range (0.00476533, 0.00694801); + fall_capacitance : 0.00553211; + fall_capacitance_range (0.00474082, 0.00607573); } pin (D) { direction : "input"; max_transition : 2.5074; - capacitance : 0.00541208; - rise_capacitance : 0.00564198; - rise_capacitance_range (0.00564198, 0.00564198); + capacitance : 0.00541207; + rise_capacitance : 0.00564195; + rise_capacitance_range (0.00447015, 0.00756889); fall_capacitance : 0.00518218; - fall_capacitance_range (0.00518218, 0.00518218); + fall_capacitance_range (0.00474994, 0.00544242); } } cell (sg13g2_o21ai_1) { area : 9.072; cell_footprint : "o21ai"; - cell_leakage_power : 778.44; + cell_leakage_power : 778.45; leakage_power () { - value : 178.554; + value : 178.564; when : "!A1&!A2&!B1&Y"; } leakage_power () { - value : 407.983; + value : 407.993; when : "A1&!A2&!B1&Y"; } leakage_power () { - value : 407.989; + value : 407.999; when : "!A1&A2&!B1&Y"; } leakage_power () { - value : 428.45; + value : 428.46; when : "A1&A2&!B1&Y"; } leakage_power () { - value : 630.285; + value : 630.296; when : "!A1&!A2&B1&Y"; } leakage_power () { - value : 1640.42; + value : 1640.43; when : "A1&!A2&B1&!Y"; } leakage_power () { - value : 1400.58; + value : 1400.59; when : "!A1&A2&B1&!Y"; } leakage_power () { - value : 1133.26; + value : 1133.27; when : "A1&A2&B1&!Y"; } pin (Y) { @@ -24532,52 +24606,52 @@ library (sg13g2_stdcell_slow_1p35V_125C) { index_1 ("0.0186, 0.0966, 0.174, 0.3294, 0.6408, 1.263, 2.5074"); index_2 ("0.001, 0.0234, 0.039, 0.0648, 0.108, 0.18, 0.3"); values ( \ - "0.067483, 0.228436, 0.33866, 0.520584, 0.825058, 1.33223, 2.17744", \ - "0.0910433, 0.255647, 0.366083, 0.548765, 0.852957, 1.3608, 2.20516", \ - "0.106218, 0.280203, 0.391025, 0.573412, 0.878509, 1.38599, 2.23114", \ - "0.12837, 0.323904, 0.439059, 0.622606, 0.927157, 1.43495, 2.2819", \ - "0.164784, 0.396543, 0.523842, 0.717699, 1.02766, 1.53501, 2.37971", \ - "0.218077, 0.505542, 0.652993, 0.873552, 1.20762, 1.72989, 2.57727", \ - "0.300081, 0.670949, 0.853944, 1.11109, 1.49874, 2.07288, 2.96034" \ + "0.0674838, 0.228443, 0.338661, 0.520584, 0.825067, 1.33226, 2.17745", \ + "0.0910436, 0.255639, 0.366139, 0.5487, 0.852947, 1.3608, 2.20558", \ + "0.106208, 0.280191, 0.391027, 0.573342, 0.878513, 1.38596, 2.23174", \ + "0.12837, 0.323906, 0.43906, 0.622638, 0.92716, 1.43496, 2.28183", \ + "0.164785, 0.396544, 0.523827, 0.717701, 1.02765, 1.53501, 2.38071", \ + "0.218078, 0.505544, 0.652995, 0.873558, 1.20762, 1.72989, 2.57719", \ + "0.300082, 0.670951, 0.853946, 1.11109, 1.49874, 2.07289, 2.96035" \ ); } rise_transition (TIMING_DELAY_7x7ds1) { index_1 ("0.0186, 0.0966, 0.174, 0.3294, 0.6408, 1.263, 2.5074"); index_2 ("0.001, 0.0234, 0.039, 0.0648, 0.108, 0.18, 0.3"); values ( \ - "0.0513646, 0.275553, 0.431139, 0.688083, 1.1184, 1.83404, 3.02942", \ - "0.0579638, 0.275924, 0.43114, 0.688645, 1.11857, 1.83486, 3.02943", \ - "0.06889, 0.280547, 0.432689, 0.688646, 1.11858, 1.83492, 3.03008", \ - "0.0903605, 0.299575, 0.445419, 0.693799, 1.12032, 1.83493, 3.03009", \ - "0.128483, 0.344547, 0.487544, 0.725621, 1.13562, 1.83989, 3.03167", \ - "0.186895, 0.430198, 0.577157, 0.814083, 1.21138, 1.8838, 3.04557", \ - "0.279892, 0.580311, 0.739752, 0.989261, 1.3933, 2.0511, 3.15946" \ + "0.0513667, 0.275554, 0.431141, 0.688092, 1.11841, 1.83405, 3.02943", \ + "0.0579592, 0.275934, 0.431997, 0.688602, 1.11857, 1.83487, 3.02944", \ + "0.0689878, 0.28053, 0.432691, 0.688603, 1.11858, 1.83491, 3.02945", \ + "0.0903609, 0.299578, 0.445421, 0.693908, 1.11993, 1.83492, 3.02951", \ + "0.128484, 0.344548, 0.487363, 0.725636, 1.13566, 1.83886, 3.03269", \ + "0.186896, 0.430199, 0.577159, 0.814013, 1.21138, 1.88381, 3.04584", \ + "0.279892, 0.580312, 0.739754, 0.989262, 1.39331, 2.05111, 3.15947" \ ); } cell_fall (TIMING_DELAY_7x7ds1) { index_1 ("0.0186, 0.0966, 0.174, 0.3294, 0.6408, 1.263, 2.5074"); index_2 ("0.001, 0.0234, 0.039, 0.0648, 0.108, 0.18, 0.3"); values ( \ - "0.0490163, 0.153769, 0.225116, 0.342794, 0.539892, 0.867829, 1.41473", \ - "0.0710479, 0.183846, 0.255559, 0.373397, 0.570385, 0.898741, 1.44516", \ - "0.0840753, 0.209614, 0.283711, 0.402594, 0.599763, 0.928128, 1.47545", \ - "0.100427, 0.251417, 0.333032, 0.458115, 0.658553, 0.987348, 1.53422", \ - "0.118136, 0.310349, 0.406873, 0.547857, 0.763526, 1.10063, 1.64898", \ - "0.137852, 0.387638, 0.510482, 0.682331, 0.930378, 1.30048, 1.87261", \ - "0.15473, 0.48511, 0.642537, 0.864807, 1.17539, 1.60972, 2.24939" \ + "0.0490291, 0.153719, 0.225112, 0.342795, 0.539891, 0.86783, 1.41472", \ + "0.0710479, 0.183852, 0.255558, 0.373436, 0.570509, 0.898729, 1.44526", \ + "0.0840749, 0.2096, 0.283721, 0.402597, 0.599762, 0.927945, 1.47545", \ + "0.100427, 0.251416, 0.333032, 0.458115, 0.658554, 0.987205, 1.5341", \ + "0.118135, 0.310349, 0.406873, 0.547857, 0.763525, 1.10065, 1.64898", \ + "0.13785, 0.387637, 0.510481, 0.682331, 0.930377, 1.30048, 1.8726", \ + "0.15473, 0.485109, 0.642536, 0.864807, 1.17539, 1.60971, 2.24939" \ ); } fall_transition (TIMING_DELAY_7x7ds1) { index_1 ("0.0186, 0.0966, 0.174, 0.3294, 0.6408, 1.263, 2.5074"); index_2 ("0.001, 0.0234, 0.039, 0.0648, 0.108, 0.18, 0.3"); values ( \ - "0.0306181, 0.169121, 0.265241, 0.42381, 0.689744, 1.13251, 1.87063", \ - "0.0395979, 0.171897, 0.266017, 0.423963, 0.689745, 1.13252, 1.87174", \ - "0.050147, 0.181543, 0.27289, 0.427309, 0.690698, 1.13253, 1.8724", \ - "0.0708691, 0.20696, 0.295638, 0.444192, 0.699752, 1.13547, 1.87241", \ - "0.107828, 0.256746, 0.347018, 0.493187, 0.73877, 1.15837, 1.88036", \ - "0.169268, 0.345796, 0.445553, 0.597246, 0.840551, 1.24803, 1.93848", \ - "0.265582, 0.494359, 0.61161, 0.783592, 1.04589, 1.45504, 2.13201" \ + "0.0306526, 0.168991, 0.265241, 0.423809, 0.689744, 1.13251, 1.87062", \ + "0.0395978, 0.171891, 0.266001, 0.424485, 0.689745, 1.13252, 1.87063", \ + "0.0501462, 0.181595, 0.2729, 0.427294, 0.690697, 1.13424, 1.8724", \ + "0.070869, 0.206959, 0.295638, 0.444191, 0.699541, 1.13625, 1.87241", \ + "0.107828, 0.256745, 0.347018, 0.493187, 0.73877, 1.15833, 1.88035", \ + "0.169272, 0.345796, 0.445553, 0.597245, 0.84055, 1.24803, 1.93848", \ + "0.265579, 0.494359, 0.61161, 0.783591, 1.04589, 1.45504, 2.13201" \ ); } } @@ -24589,52 +24663,52 @@ library (sg13g2_stdcell_slow_1p35V_125C) { index_1 ("0.0186, 0.0966, 0.174, 0.3294, 0.6408, 1.263, 2.5074"); index_2 ("0.001, 0.0234, 0.039, 0.0648, 0.108, 0.18, 0.3"); values ( \ - "0.0591099, 0.221063, 0.331497, 0.513602, 0.81795, 1.32506, 2.17029", \ - "0.0854691, 0.252543, 0.363239, 0.545966, 0.849844, 1.35783, 2.20383", \ - "0.104989, 0.285974, 0.396849, 0.578865, 0.883925, 1.39147, 2.23642", \ - "0.134435, 0.346007, 0.462802, 0.646096, 0.950066, 1.45687, 2.30202", \ - "0.181688, 0.441844, 0.576694, 0.775958, 1.08661, 1.59268, 2.4375", \ - "0.250515, 0.576743, 0.744797, 0.982318, 1.33034, 1.85907, 2.70419", \ - "0.35846, 0.780086, 0.987453, 1.28424, 1.71331, 2.32234, 3.22814" \ + "0.0591085, 0.221066, 0.331416, 0.513603, 0.817955, 1.32505, 2.1703", \ + "0.0854976, 0.252535, 0.363247, 0.545933, 0.850238, 1.35785, 2.2038", \ + "0.104989, 0.285981, 0.396778, 0.578869, 0.883591, 1.39146, 2.23643", \ + "0.134435, 0.346008, 0.462803, 0.646098, 0.950131, 1.45702, 2.30202", \ + "0.181688, 0.441845, 0.576696, 0.77596, 1.08664, 1.59282, 2.4374", \ + "0.250516, 0.576744, 0.744802, 0.98232, 1.33032, 1.85907, 2.70435", \ + "0.358461, 0.780087, 0.987455, 1.28425, 1.71332, 2.32234, 3.22793" \ ); } rise_transition (TIMING_DELAY_7x7ds1) { index_1 ("0.0186, 0.0966, 0.174, 0.3294, 0.6408, 1.263, 2.5074"); index_2 ("0.001, 0.0234, 0.039, 0.0648, 0.108, 0.18, 0.3"); values ( \ - "0.0513988, 0.275515, 0.430948, 0.68797, 1.11848, 1.83404, 3.02982", \ - "0.063288, 0.276098, 0.432217, 0.68853, 1.11849, 1.83485, 3.02983", \ - "0.0773174, 0.283932, 0.433776, 0.688531, 1.1187, 1.83486, 3.03008", \ - "0.100099, 0.313107, 0.453535, 0.696961, 1.12039, 1.83487, 3.03009", \ - "0.135809, 0.375619, 0.51597, 0.745071, 1.14484, 1.841, 3.0301", \ - "0.19301, 0.482719, 0.638309, 0.874136, 1.25649, 1.91025, 3.05173", \ - "0.286406, 0.648221, 0.833992, 1.10548, 1.5136, 2.15392, 3.22415" \ + "0.0513989, 0.275519, 0.431116, 0.687973, 1.11849, 1.83405, 3.02983", \ + "0.0632603, 0.276185, 0.432219, 0.688501, 1.1185, 1.83486, 3.02984", \ + "0.0773175, 0.283916, 0.433908, 0.688502, 1.11851, 1.83487, 3.0301", \ + "0.100099, 0.313108, 0.453537, 0.696964, 1.11881, 1.83488, 3.03011", \ + "0.13581, 0.375621, 0.515972, 0.745074, 1.14493, 1.84134, 3.03012", \ + "0.193011, 0.48272, 0.638315, 0.874132, 1.25626, 1.91025, 3.05316", \ + "0.286406, 0.648221, 0.833994, 1.10548, 1.51361, 2.15393, 3.22409" \ ); } cell_fall (TIMING_DELAY_7x7ds1) { index_1 ("0.0186, 0.0966, 0.174, 0.3294, 0.6408, 1.263, 2.5074"); index_2 ("0.001, 0.0234, 0.039, 0.0648, 0.108, 0.18, 0.3"); values ( \ - "0.0411239, 0.145322, 0.216298, 0.333497, 0.529541, 0.856334, 1.40096", \ - "0.0594023, 0.175393, 0.246991, 0.364411, 0.560688, 0.887547, 1.43236", \ - "0.0690517, 0.200336, 0.274757, 0.393485, 0.590106, 0.917308, 1.46205", \ - "0.0792113, 0.240214, 0.323016, 0.448573, 0.648651, 0.97658, 1.52184", \ - "0.0864468, 0.295862, 0.394312, 0.537288, 0.753048, 1.08982, 1.63677", \ - "0.0879259, 0.365617, 0.493305, 0.667473, 0.918387, 1.28872, 1.86041", \ - "0.0879269, 0.448213, 0.613586, 0.841754, 1.15745, 1.59489, 2.23598" \ + "0.0411273, 0.145322, 0.2163, 0.333495, 0.529637, 0.856331, 1.40095", \ + "0.0594023, 0.175385, 0.246994, 0.36441, 0.560688, 0.887549, 1.43236", \ + "0.0690982, 0.200335, 0.274757, 0.393481, 0.590059, 0.917321, 1.4627", \ + "0.0792113, 0.240213, 0.323016, 0.448573, 0.648637, 0.97664, 1.52184", \ + "0.0864467, 0.295862, 0.394312, 0.537287, 0.753047, 1.08982, 1.63677", \ + "0.0879257, 0.365617, 0.493305, 0.667493, 0.918386, 1.28872, 1.86041", \ + "0.0879267, 0.448213, 0.613585, 0.841753, 1.15745, 1.59489, 2.23598" \ ); } fall_transition (TIMING_DELAY_7x7ds1) { index_1 ("0.0186, 0.0966, 0.174, 0.3294, 0.6408, 1.263, 2.5074"); index_2 ("0.001, 0.0234, 0.039, 0.0648, 0.108, 0.18, 0.3"); values ( \ - "0.0211047, 0.158147, 0.25372, 0.411752, 0.676333, 1.11729, 1.85352", \ - "0.0307679, 0.161381, 0.254959, 0.412484, 0.676334, 1.1173, 1.85353", \ - "0.0413024, 0.171333, 0.261826, 0.415246, 0.677106, 1.11738, 1.85354", \ - "0.0618476, 0.196924, 0.285028, 0.43254, 0.686688, 1.12004, 1.85366", \ - "0.0993466, 0.247414, 0.337127, 0.482339, 0.726273, 1.14421, 1.85973", \ - "0.16077, 0.337141, 0.435529, 0.585865, 0.829576, 1.23492, 1.92077", \ - "0.257356, 0.486847, 0.60677, 0.77927, 1.0352, 1.44473, 2.1166" \ + "0.0211035, 0.158146, 0.253724, 0.411752, 0.676354, 1.11729, 1.85223", \ + "0.0307679, 0.161383, 0.254962, 0.412484, 0.676355, 1.1173, 1.85351", \ + "0.0413098, 0.171333, 0.261834, 0.415267, 0.677062, 1.11738, 1.85352", \ + "0.0618475, 0.196924, 0.285028, 0.432534, 0.686491, 1.12031, 1.85366", \ + "0.0993466, 0.247414, 0.337126, 0.482338, 0.726273, 1.14421, 1.85973", \ + "0.16077, 0.337141, 0.435529, 0.586569, 0.829575, 1.23492, 1.92076", \ + "0.257356, 0.486847, 0.60677, 0.779269, 1.0352, 1.44473, 2.1166" \ ); } } @@ -24648,52 +24722,52 @@ library (sg13g2_stdcell_slow_1p35V_125C) { index_1 ("0.0186, 0.0966, 0.174, 0.3294, 0.6408, 1.263, 2.5074"); index_2 ("0.001, 0.0234, 0.039, 0.0648, 0.108, 0.18, 0.3"); values ( \ - "0.0258878, 0.106825, 0.161352, 0.251494, 0.402211, 0.653364, 1.07188", \ - "0.0464878, 0.145717, 0.200947, 0.291179, 0.442111, 0.693615, 1.11206", \ - "0.0579398, 0.180289, 0.239983, 0.331889, 0.482851, 0.734164, 1.15321", \ - "0.0734754, 0.233073, 0.304674, 0.406861, 0.562677, 0.813948, 1.23267", \ - "0.0977869, 0.30932, 0.402997, 0.529542, 0.708105, 0.97371, 1.39424", \ - "0.126212, 0.412723, 0.53565, 0.703284, 0.931767, 1.24586, 1.70266", \ - "0.162425, 0.549861, 0.71899, 0.942011, 1.24359, 1.65709, 2.2141" \ + "0.025885, 0.106825, 0.16137, 0.251485, 0.402301, 0.653362, 1.07185", \ + "0.0464876, 0.145718, 0.200942, 0.291178, 0.442146, 0.693614, 1.11205", \ + "0.0579396, 0.180289, 0.239949, 0.331896, 0.482844, 0.734372, 1.1532", \ + "0.0734751, 0.233072, 0.304672, 0.406857, 0.562674, 0.813984, 1.23243", \ + "0.0977865, 0.309319, 0.402993, 0.52954, 0.708101, 0.973721, 1.39425", \ + "0.126212, 0.412721, 0.535648, 0.703282, 0.931763, 1.24614, 1.70265", \ + "0.162424, 0.549859, 0.718987, 0.942008, 1.24379, 1.65708, 2.2141" \ ); } rise_transition (TIMING_DELAY_7x7ds1) { index_1 ("0.0186, 0.0966, 0.174, 0.3294, 0.6408, 1.263, 2.5074"); index_2 ("0.001, 0.0234, 0.039, 0.0648, 0.108, 0.18, 0.3"); values ( \ - "0.017494, 0.130391, 0.209467, 0.340441, 0.559715, 0.925252, 1.53398", \ - "0.034188, 0.136137, 0.211445, 0.340442, 0.559727, 0.925253, 1.53418", \ - "0.0472181, 0.153345, 0.223495, 0.346253, 0.560534, 0.925645, 1.53419", \ - "0.0674298, 0.190684, 0.259498, 0.373477, 0.575014, 0.92849, 1.5342", \ - "0.102446, 0.255587, 0.331194, 0.447411, 0.636431, 0.965557, 1.54661", \ - "0.158852, 0.359221, 0.453001, 0.587697, 0.786085, 1.10102, 1.63822", \ - "0.2527, 0.530636, 0.648131, 0.812927, 1.05326, 1.39642, 1.92756" \ + "0.0174942, 0.130388, 0.209486, 0.340439, 0.559724, 0.925236, 1.53411", \ + "0.034188, 0.136137, 0.211438, 0.34044, 0.559725, 0.925237, 1.53417", \ + "0.0472179, 0.153344, 0.223445, 0.346249, 0.56054, 0.925466, 1.53418", \ + "0.0674295, 0.190684, 0.259496, 0.373444, 0.57501, 0.928522, 1.53419", \ + "0.102446, 0.255586, 0.331044, 0.447408, 0.636429, 0.965493, 1.54665", \ + "0.158851, 0.35922, 0.452999, 0.587694, 0.78608, 1.10125, 1.6382", \ + "0.2527, 0.530634, 0.648129, 0.812925, 1.05228, 1.39641, 1.92755" \ ); } cell_fall (TIMING_DELAY_7x7ds1) { index_1 ("0.0186, 0.0966, 0.174, 0.3294, 0.6408, 1.263, 2.5074"); index_2 ("0.001, 0.0234, 0.039, 0.0648, 0.108, 0.18, 0.3"); values ( \ - "0.0314588, 0.136037, 0.207014, 0.324247, 0.52058, 0.847145, 1.39173", \ - "0.0489434, 0.171213, 0.242755, 0.36006, 0.556319, 0.883168, 1.42789", \ - "0.0590124, 0.201709, 0.277385, 0.396349, 0.592454, 0.91939, 1.46475", \ - "0.0725693, 0.248713, 0.335885, 0.4645, 0.665273, 0.992145, 1.53671", \ - "0.0883658, 0.313823, 0.420904, 0.572673, 0.796862, 1.13557, 1.68091", \ - "0.107353, 0.397568, 0.536478, 0.726427, 0.996077, 1.38402, 1.96336", \ - "0.12611, 0.507408, 0.684082, 0.931485, 1.27344, 1.74976, 2.42654" \ + "0.0314594, 0.136041, 0.207137, 0.324262, 0.520455, 0.847104, 1.39173", \ + "0.0489292, 0.171213, 0.24275, 0.360063, 0.55631, 0.883172, 1.4279", \ + "0.0590126, 0.201697, 0.277383, 0.396367, 0.592502, 0.919436, 1.46476", \ + "0.0725693, 0.248713, 0.335885, 0.464496, 0.665276, 0.992229, 1.53672", \ + "0.0883659, 0.313823, 0.420904, 0.572673, 0.796861, 1.13552, 1.68091", \ + "0.107353, 0.397568, 0.536478, 0.726324, 0.996077, 1.38402, 1.96336", \ + "0.12611, 0.507408, 0.684086, 0.931484, 1.27344, 1.74975, 2.42654" \ ); } fall_transition (TIMING_DELAY_7x7ds1) { index_1 ("0.0186, 0.0966, 0.174, 0.3294, 0.6408, 1.263, 2.5074"); index_2 ("0.001, 0.0234, 0.039, 0.0648, 0.108, 0.18, 0.3"); values ( \ - "0.0217047, 0.158421, 0.25375, 0.411757, 0.67639, 1.11729, 1.85223", \ - "0.0366002, 0.164092, 0.25578, 0.412049, 0.676391, 1.1173, 1.85351", \ - "0.0484598, 0.180099, 0.267414, 0.417657, 0.677299, 1.11808, 1.85352", \ - "0.0680459, 0.216639, 0.302737, 0.445158, 0.692851, 1.12131, 1.85366", \ - "0.100503, 0.278529, 0.372494, 0.517289, 0.753175, 1.15858, 1.86401", \ - "0.154042, 0.379036, 0.489028, 0.651061, 0.897924, 1.29331, 1.95734", \ - "0.245157, 0.535081, 0.675891, 0.871438, 1.15639, 1.5764, 2.23898" \ + "0.0217076, 0.158421, 0.253855, 0.411757, 0.676365, 1.11729, 1.85223", \ + "0.0365361, 0.164018, 0.255775, 0.41252, 0.676366, 1.1173, 1.85351", \ + "0.0484597, 0.180168, 0.267491, 0.41766, 0.677599, 1.11813, 1.85352", \ + "0.0680459, 0.216639, 0.302737, 0.445162, 0.692836, 1.12143, 1.85365", \ + "0.100503, 0.278529, 0.372493, 0.517288, 0.753174, 1.15839, 1.86401", \ + "0.154042, 0.379035, 0.489027, 0.651003, 0.897923, 1.29331, 1.95734", \ + "0.245157, 0.53508, 0.675882, 0.871436, 1.15639, 1.57639, 2.23899" \ ); } } @@ -24705,52 +24779,52 @@ library (sg13g2_stdcell_slow_1p35V_125C) { index_1 ("0.0186, 0.0966, 0.174, 0.3294, 0.6408, 1.263, 2.5074"); index_2 ("0.001, 0.0234, 0.039, 0.0648, 0.108, 0.18, 0.3"); values ( \ - "0.0258878, 0.106825, 0.161352, 0.251494, 0.402211, 0.653364, 1.07188", \ - "0.0464878, 0.145717, 0.200947, 0.291179, 0.442111, 0.693615, 1.11206", \ - "0.0579398, 0.180289, 0.239983, 0.331889, 0.482851, 0.734164, 1.15321", \ - "0.0734754, 0.233073, 0.304674, 0.406861, 0.562677, 0.813948, 1.23267", \ - "0.0977869, 0.30932, 0.402997, 0.529542, 0.708105, 0.97371, 1.39424", \ - "0.126212, 0.412723, 0.53565, 0.703284, 0.931767, 1.24586, 1.70266", \ - "0.162425, 0.549861, 0.71899, 0.942011, 1.24359, 1.65709, 2.2141" \ + "0.025885, 0.106825, 0.16137, 0.251485, 0.402301, 0.653362, 1.07185", \ + "0.0464876, 0.145718, 0.200942, 0.291178, 0.442146, 0.693614, 1.11205", \ + "0.0579396, 0.180289, 0.239949, 0.331896, 0.482844, 0.734372, 1.1532", \ + "0.0734751, 0.233072, 0.304672, 0.406857, 0.562674, 0.813984, 1.23243", \ + "0.0977865, 0.309319, 0.402993, 0.52954, 0.708101, 0.973721, 1.39425", \ + "0.126212, 0.412721, 0.535648, 0.703282, 0.931763, 1.24614, 1.70265", \ + "0.162424, 0.549859, 0.718987, 0.942008, 1.24379, 1.65708, 2.2141" \ ); } rise_transition (TIMING_DELAY_7x7ds1) { index_1 ("0.0186, 0.0966, 0.174, 0.3294, 0.6408, 1.263, 2.5074"); index_2 ("0.001, 0.0234, 0.039, 0.0648, 0.108, 0.18, 0.3"); values ( \ - "0.017494, 0.130391, 0.209467, 0.340441, 0.559715, 0.925252, 1.53398", \ - "0.034188, 0.136137, 0.211445, 0.340442, 0.559727, 0.925253, 1.53418", \ - "0.0472181, 0.153345, 0.223495, 0.346253, 0.560534, 0.925645, 1.53419", \ - "0.0674298, 0.190684, 0.259498, 0.373477, 0.575014, 0.92849, 1.5342", \ - "0.102446, 0.255587, 0.331194, 0.447411, 0.636431, 0.965557, 1.54661", \ - "0.158852, 0.359221, 0.453001, 0.587697, 0.786085, 1.10102, 1.63822", \ - "0.2527, 0.530636, 0.648131, 0.812927, 1.05326, 1.39642, 1.92756" \ + "0.0174942, 0.130388, 0.209486, 0.340439, 0.559724, 0.925236, 1.53411", \ + "0.034188, 0.136137, 0.211438, 0.34044, 0.559725, 0.925237, 1.53417", \ + "0.0472179, 0.153344, 0.223445, 0.346249, 0.56054, 0.925466, 1.53418", \ + "0.0674295, 0.190684, 0.259496, 0.373444, 0.57501, 0.928522, 1.53419", \ + "0.102446, 0.255586, 0.331044, 0.447408, 0.636429, 0.965493, 1.54665", \ + "0.158851, 0.35922, 0.452999, 0.587694, 0.78608, 1.10125, 1.6382", \ + "0.2527, 0.530634, 0.648129, 0.812925, 1.05228, 1.39641, 1.92755" \ ); } cell_fall (TIMING_DELAY_7x7ds1) { index_1 ("0.0186, 0.0966, 0.174, 0.3294, 0.6408, 1.263, 2.5074"); index_2 ("0.001, 0.0234, 0.039, 0.0648, 0.108, 0.18, 0.3"); values ( \ - "0.0314588, 0.136037, 0.207014, 0.324247, 0.52058, 0.847145, 1.39173", \ - "0.0489434, 0.171213, 0.242755, 0.36006, 0.556319, 0.883168, 1.42789", \ - "0.0590124, 0.201709, 0.277385, 0.396349, 0.592454, 0.91939, 1.46475", \ - "0.0725693, 0.248713, 0.335885, 0.4645, 0.665273, 0.992145, 1.53671", \ - "0.0883658, 0.313823, 0.420904, 0.572673, 0.796862, 1.13557, 1.68091", \ - "0.107353, 0.397568, 0.536478, 0.726427, 0.996077, 1.38402, 1.96336", \ - "0.12611, 0.507408, 0.684082, 0.931485, 1.27344, 1.74976, 2.42654" \ + "0.0314594, 0.136041, 0.207137, 0.324262, 0.520455, 0.847104, 1.39173", \ + "0.0489292, 0.171213, 0.24275, 0.360063, 0.55631, 0.883172, 1.4279", \ + "0.0590126, 0.201697, 0.277383, 0.396367, 0.592502, 0.919436, 1.46476", \ + "0.0725693, 0.248713, 0.335885, 0.464496, 0.665276, 0.992229, 1.53672", \ + "0.0883659, 0.313823, 0.420904, 0.572673, 0.796861, 1.13552, 1.68091", \ + "0.107353, 0.397568, 0.536478, 0.726324, 0.996077, 1.38402, 1.96336", \ + "0.12611, 0.507408, 0.684086, 0.931484, 1.27344, 1.74975, 2.42654" \ ); } fall_transition (TIMING_DELAY_7x7ds1) { index_1 ("0.0186, 0.0966, 0.174, 0.3294, 0.6408, 1.263, 2.5074"); index_2 ("0.001, 0.0234, 0.039, 0.0648, 0.108, 0.18, 0.3"); values ( \ - "0.0217047, 0.158421, 0.25375, 0.411757, 0.67639, 1.11729, 1.85223", \ - "0.0366002, 0.164092, 0.25578, 0.412049, 0.676391, 1.1173, 1.85351", \ - "0.0484598, 0.180099, 0.267414, 0.417657, 0.677299, 1.11808, 1.85352", \ - "0.0680459, 0.216639, 0.302737, 0.445158, 0.692851, 1.12131, 1.85366", \ - "0.100503, 0.278529, 0.372494, 0.517289, 0.753175, 1.15858, 1.86401", \ - "0.154042, 0.379036, 0.489028, 0.651061, 0.897924, 1.29331, 1.95734", \ - "0.245157, 0.535081, 0.675891, 0.871438, 1.15639, 1.5764, 2.23898" \ + "0.0217076, 0.158421, 0.253855, 0.411757, 0.676365, 1.11729, 1.85223", \ + "0.0365361, 0.164018, 0.255775, 0.41252, 0.676366, 1.1173, 1.85351", \ + "0.0484597, 0.180168, 0.267491, 0.41766, 0.677599, 1.11813, 1.85352", \ + "0.0680459, 0.216639, 0.302737, 0.445162, 0.692836, 1.12143, 1.85365", \ + "0.100503, 0.278529, 0.372493, 0.517288, 0.753174, 1.15839, 1.86401", \ + "0.154042, 0.379035, 0.489027, 0.651003, 0.897923, 1.29331, 1.95734", \ + "0.245157, 0.53508, 0.675882, 0.871436, 1.15639, 1.57639, 2.23899" \ ); } } @@ -24760,26 +24834,26 @@ library (sg13g2_stdcell_slow_1p35V_125C) { index_1 ("0.0186, 0.0966, 0.174, 0.3294, 0.6408, 1.263, 2.5074"); index_2 ("0.001, 0.0234, 0.039, 0.0648, 0.108, 0.18, 0.3"); values ( \ - "0.00656167, 0.0065954, 0.00654534, 0.00646341, 0.00630086, 0.00602674, 0.0057955", \ - "0.00627665, 0.00645407, 0.00642544, 0.00640371, 0.00626277, 0.00598053, 0.00571073", \ - "0.00630351, 0.0063805, 0.00636793, 0.00631681, 0.00623319, 0.00595701, 0.00573305", \ - "0.00672489, 0.0064886, 0.0065804, 0.0063755, 0.0062696, 0.00599228, 0.00574486", \ - "0.00842272, 0.00735367, 0.00708476, 0.00693598, 0.00655288, 0.0061739, 0.00605432", \ - "0.012788, 0.0102604, 0.00949694, 0.00871262, 0.00803761, 0.00721946, 0.00690288", \ - "0.0222752, 0.0180386, 0.016384, 0.0144989, 0.0128281, 0.0106714, 0.00959221" \ + "0.00656161, 0.0065957, 0.0065442, 0.0064561, 0.006301, 0.00602607, 0.00579419", \ + "0.00628121, 0.00649496, 0.00647273, 0.00640117, 0.0062582, 0.00598672, 0.00570351", \ + "0.00630211, 0.00640819, 0.00635968, 0.00632103, 0.00623319, 0.00598096, 0.00571851", \ + "0.00673016, 0.00649081, 0.00658034, 0.0063483, 0.00625949, 0.00599085, 0.00578084", \ + "0.00842361, 0.0073632, 0.00707489, 0.00688959, 0.00667369, 0.00613993, 0.00609431", \ + "0.012788, 0.0102589, 0.00948789, 0.00867186, 0.00803754, 0.00721817, 0.00727008", \ + "0.0222746, 0.0180384, 0.0163842, 0.0144953, 0.0127872, 0.0106715, 0.00962479" \ ); } fall_power (POWER_7x7ds1) { index_1 ("0.0186, 0.0966, 0.174, 0.3294, 0.6408, 1.263, 2.5074"); index_2 ("0.001, 0.0234, 0.039, 0.0648, 0.108, 0.18, 0.3"); values ( \ - "0.00611813, 0.00611025, 0.00606337, 0.00597196, 0.00585834, 0.00559124, 0.00520924", \ - "0.00578387, 0.00604073, 0.00600179, 0.00586667, 0.00574323, 0.00553147, 0.00520206", \ - "0.00579466, 0.00589916, 0.00598458, 0.00586322, 0.00574952, 0.00550154, 0.00525577", \ - "0.00622801, 0.006105, 0.00600473, 0.00599715, 0.00577657, 0.00582082, 0.00528487", \ - "0.00781195, 0.00687194, 0.00670799, 0.00645453, 0.00612376, 0.00627472, 0.00541811", \ - "0.0119589, 0.00953499, 0.00887666, 0.00832246, 0.00759146, 0.00674167, 0.00675721", \ - "0.0210106, 0.0168058, 0.015184, 0.0135937, 0.0119939, 0.0105039, 0.0089255" \ + "0.00611846, 0.00610325, 0.00606367, 0.00597252, 0.00585743, 0.00559201, 0.00520841", \ + "0.00577943, 0.00603082, 0.00593732, 0.00591174, 0.00575202, 0.00553043, 0.00511079", \ + "0.00579362, 0.00590441, 0.0059849, 0.00596428, 0.00574953, 0.00563951, 0.00525577", \ + "0.00622534, 0.00610576, 0.0060048, 0.0059977, 0.005768, 0.00604017, 0.00520807", \ + "0.0078128, 0.00687136, 0.0067073, 0.00645445, 0.00612376, 0.00643147, 0.00541852", \ + "0.011955, 0.00953458, 0.00887647, 0.00832384, 0.0075966, 0.0067416, 0.00675735", \ + "0.0210083, 0.0168061, 0.0151927, 0.0135938, 0.0120006, 0.0105038, 0.00892523" \ ); } } @@ -24789,26 +24863,26 @@ library (sg13g2_stdcell_slow_1p35V_125C) { index_1 ("0.0186, 0.0966, 0.174, 0.3294, 0.6408, 1.263, 2.5074"); index_2 ("0.001, 0.0234, 0.039, 0.0648, 0.108, 0.18, 0.3"); values ( \ - "0.00362719, 0.00379896, 0.00375437, 0.0036812, 0.00354591, 0.00324878, 0.00293264", \ - "0.00339053, 0.00362969, 0.00366177, 0.00358184, 0.00342825, 0.00320632, 0.00288113", \ - "0.00368924, 0.00359049, 0.00356513, 0.00352626, 0.00346906, 0.00319034, 0.00296113", \ - "0.00449074, 0.00388572, 0.00378506, 0.00376723, 0.00352447, 0.00319973, 0.00290152", \ - "0.00649026, 0.00506278, 0.00463689, 0.00440493, 0.0038892, 0.00346635, 0.00306339", \ - "0.010936, 0.0082925, 0.00745764, 0.00645998, 0.00560214, 0.0045389, 0.00394959", \ - "0.0201019, 0.0159071, 0.0142938, 0.0124846, 0.0105092, 0.0082818, 0.00707981" \ + "0.0036276, 0.003799, 0.00376094, 0.00368043, 0.00355287, 0.00325036, 0.00293304", \ + "0.00339605, 0.00363362, 0.00366191, 0.00358727, 0.00343269, 0.00320661, 0.00293429", \ + "0.00369059, 0.00359175, 0.00356861, 0.0035143, 0.00342344, 0.00318386, 0.00296007", \ + "0.00449074, 0.00388465, 0.00378508, 0.00376719, 0.00347778, 0.00320095, 0.00290152", \ + "0.00649017, 0.00506247, 0.00463685, 0.00440518, 0.00389643, 0.0034122, 0.00310034", \ + "0.0109319, 0.00828903, 0.0074615, 0.00646532, 0.0055971, 0.00453862, 0.00430728", \ + "0.0201028, 0.0159079, 0.0142957, 0.0124846, 0.0105297, 0.00828186, 0.00765462" \ ); } fall_power (POWER_7x7ds1) { index_1 ("0.0186, 0.0966, 0.174, 0.3294, 0.6408, 1.263, 2.5074"); index_2 ("0.001, 0.0234, 0.039, 0.0648, 0.108, 0.18, 0.3"); values ( \ - "0.00568301, 0.00610375, 0.00608186, 0.00602505, 0.00587977, 0.00563482, 0.00525308", \ - "0.00523249, 0.00596173, 0.00600762, 0.00603149, 0.00590254, 0.00562577, 0.0053089", \ - "0.00527818, 0.00580065, 0.00596169, 0.00594264, 0.00584756, 0.00569002, 0.00526261", \ - "0.00580846, 0.00588552, 0.00587827, 0.00597642, 0.00586148, 0.00590868, 0.00533517", \ - "0.00748145, 0.00656785, 0.00648324, 0.00635822, 0.00612537, 0.00606672, 0.00571544", \ - "0.0116042, 0.00905005, 0.00849116, 0.00792085, 0.00750063, 0.00665307, 0.0068186", \ - "0.0205068, 0.0159034, 0.0144887, 0.0130612, 0.011425, 0.0102474, 0.00885128" \ + "0.00568288, 0.00610411, 0.00608231, 0.00602461, 0.0059037, 0.00563398, 0.00521672", \ + "0.00523242, 0.00596112, 0.00600665, 0.00603195, 0.00590254, 0.00563173, 0.00530872", \ + "0.00528209, 0.00580075, 0.00595314, 0.00594441, 0.00585714, 0.00569041, 0.00537492", \ + "0.00580858, 0.00588553, 0.00587827, 0.00595809, 0.00584154, 0.00567935, 0.00533511", \ + "0.00748181, 0.00656755, 0.00648325, 0.00635846, 0.00612551, 0.00648519, 0.00571836", \ + "0.0116049, 0.00904993, 0.00849267, 0.00796105, 0.00749955, 0.00665307, 0.00660024", \ + "0.0205077, 0.0159042, 0.0144886, 0.0130609, 0.0114009, 0.0102466, 0.00884485" \ ); } } @@ -24819,26 +24893,26 @@ library (sg13g2_stdcell_slow_1p35V_125C) { index_1 ("0.0186, 0.0966, 0.174, 0.3294, 0.6408, 1.263, 2.5074"); index_2 ("0.001, 0.0234, 0.039, 0.0648, 0.108, 0.18, 0.3"); values ( \ - "0.00221496, 0.00284393, 0.00283071, 0.00276501, 0.0026522, 0.0023534, 0.00191898", \ - "0.00219013, 0.00258138, 0.00262084, 0.00261872, 0.00259629, 0.00234172, 0.00190262", \ - "0.00262616, 0.00252364, 0.00265654, 0.00267066, 0.00249885, 0.00234982, 0.00191478", \ - "0.00374382, 0.00290913, 0.00275154, 0.00276279, 0.0026193, 0.00246941, 0.00195185", \ - "0.00622106, 0.00425463, 0.00385644, 0.00342498, 0.0031389, 0.0026067, 0.00319774", \ - "0.0115612, 0.00800662, 0.00695496, 0.00607952, 0.00501824, 0.00396586, 0.00410426", \ - "0.0224682, 0.016683, 0.0149191, 0.0127908, 0.0107453, 0.00869593, 0.00641188" \ + "0.00221494, 0.00284377, 0.00282818, 0.00276545, 0.00263847, 0.00237024, 0.00190671", \ + "0.00219034, 0.00260551, 0.00262742, 0.00261784, 0.00255414, 0.00234207, 0.00190265", \ + "0.00262566, 0.00252919, 0.00263632, 0.00267428, 0.00249875, 0.0023657, 0.00191512", \ + "0.00374367, 0.0029142, 0.00275221, 0.00275353, 0.0026193, 0.00281506, 0.00190412", \ + "0.00622118, 0.00425558, 0.00384992, 0.0034289, 0.00313898, 0.00260722, 0.00279141", \ + "0.0115611, 0.00800233, 0.00695496, 0.00607374, 0.00501265, 0.0040204, 0.00377759", \ + "0.0224683, 0.0166824, 0.0149192, 0.0127858, 0.0107022, 0.00869583, 0.00647496" \ ); } fall_power (POWER_7x7ds1) { index_1 ("0.0186, 0.0966, 0.174, 0.3294, 0.6408, 1.263, 2.5074"); index_2 ("0.001, 0.0234, 0.039, 0.0648, 0.108, 0.18, 0.3"); values ( \ - "0.00307271, 0.00356362, 0.00353774, 0.0034757, 0.00336776, 0.00311995, 0.00267861", \ - "0.00299174, 0.00335878, 0.00336986, 0.00336606, 0.00326825, 0.00305852, 0.00268619", \ - "0.00337508, 0.00330753, 0.00341064, 0.00335885, 0.00323527, 0.00309696, 0.00270133", \ - "0.00444957, 0.00380331, 0.00360872, 0.00356664, 0.00332506, 0.0034025, 0.00280044", \ - "0.00686268, 0.00504089, 0.00468404, 0.00425238, 0.00380914, 0.00393735, 0.00291656", \ - "0.011976, 0.00876479, 0.00755159, 0.00669736, 0.00585334, 0.00487171, 0.00464951", \ - "0.0224339, 0.0171682, 0.0152432, 0.0135118, 0.0113637, 0.0095981, 0.00714568" \ + "0.00307111, 0.00356328, 0.00354975, 0.0034762, 0.00335659, 0.00311544, 0.00267833", \ + "0.00298848, 0.00339546, 0.00336921, 0.00339988, 0.00326771, 0.00305901, 0.0026877", \ + "0.0033751, 0.0033043, 0.00341208, 0.00336052, 0.0032315, 0.00310583, 0.00270294", \ + "0.00444812, 0.00380301, 0.00360872, 0.0035669, 0.00332873, 0.00410135, 0.00279131", \ + "0.00686273, 0.00504126, 0.00468404, 0.00425177, 0.00385854, 0.00402897, 0.00291655", \ + "0.0119762, 0.00876479, 0.00755158, 0.00670312, 0.00585327, 0.00487171, 0.00464035", \ + "0.0224339, 0.017169, 0.0152434, 0.0135117, 0.0113611, 0.00959732, 0.00715417" \ ); } } @@ -24848,26 +24922,26 @@ library (sg13g2_stdcell_slow_1p35V_125C) { index_1 ("0.0186, 0.0966, 0.174, 0.3294, 0.6408, 1.263, 2.5074"); index_2 ("0.001, 0.0234, 0.039, 0.0648, 0.108, 0.18, 0.3"); values ( \ - "0.00221496, 0.00284393, 0.00283071, 0.00276501, 0.0026522, 0.0023534, 0.00191898", \ - "0.00219013, 0.00258138, 0.00262084, 0.00261872, 0.00259629, 0.00234172, 0.00190262", \ - "0.00262616, 0.00252364, 0.00265654, 0.00267066, 0.00249885, 0.00234982, 0.00191478", \ - "0.00374382, 0.00290913, 0.00275154, 0.00276279, 0.0026193, 0.00246941, 0.00195185", \ - "0.00622106, 0.00425463, 0.00385644, 0.00342498, 0.0031389, 0.0026067, 0.00319774", \ - "0.0115612, 0.00800662, 0.00695496, 0.00607952, 0.00501824, 0.00396586, 0.00410426", \ - "0.0224682, 0.016683, 0.0149191, 0.0127908, 0.0107453, 0.00869593, 0.00641188" \ + "0.00221494, 0.00284377, 0.00282818, 0.00276545, 0.00263847, 0.00237024, 0.00190671", \ + "0.00219034, 0.00260551, 0.00262742, 0.00261784, 0.00255414, 0.00234207, 0.00190265", \ + "0.00262566, 0.00252919, 0.00263632, 0.00267428, 0.00249875, 0.0023657, 0.00191512", \ + "0.00374367, 0.0029142, 0.00275221, 0.00275353, 0.0026193, 0.00281506, 0.00190412", \ + "0.00622118, 0.00425558, 0.00384992, 0.0034289, 0.00313898, 0.00260722, 0.00279141", \ + "0.0115611, 0.00800233, 0.00695496, 0.00607374, 0.00501265, 0.0040204, 0.00377759", \ + "0.0224683, 0.0166824, 0.0149192, 0.0127858, 0.0107022, 0.00869583, 0.00647496" \ ); } fall_power (POWER_7x7ds1) { index_1 ("0.0186, 0.0966, 0.174, 0.3294, 0.6408, 1.263, 2.5074"); index_2 ("0.001, 0.0234, 0.039, 0.0648, 0.108, 0.18, 0.3"); values ( \ - "0.00307271, 0.00356362, 0.00353774, 0.0034757, 0.00336776, 0.00311995, 0.00267861", \ - "0.00299174, 0.00335878, 0.00336986, 0.00336606, 0.00326825, 0.00305852, 0.00268619", \ - "0.00337508, 0.00330753, 0.00341064, 0.00335885, 0.00323527, 0.00309696, 0.00270133", \ - "0.00444957, 0.00380331, 0.00360872, 0.00356664, 0.00332506, 0.0034025, 0.00280044", \ - "0.00686268, 0.00504089, 0.00468404, 0.00425238, 0.00380914, 0.00393735, 0.00291656", \ - "0.011976, 0.00876479, 0.00755159, 0.00669736, 0.00585334, 0.00487171, 0.00464951", \ - "0.0224339, 0.0171682, 0.0152432, 0.0135118, 0.0113637, 0.0095981, 0.00714568" \ + "0.00307111, 0.00356328, 0.00354975, 0.0034762, 0.00335659, 0.00311544, 0.00267833", \ + "0.00298848, 0.00339546, 0.00336921, 0.00339988, 0.00326771, 0.00305901, 0.0026877", \ + "0.0033751, 0.0033043, 0.00341208, 0.00336052, 0.0032315, 0.00310583, 0.00270294", \ + "0.00444812, 0.00380301, 0.00360872, 0.0035669, 0.00332873, 0.00410135, 0.00279131", \ + "0.00686273, 0.00504126, 0.00468404, 0.00425177, 0.00385854, 0.00402897, 0.00291655", \ + "0.0119762, 0.00876479, 0.00755158, 0.00670312, 0.00585327, 0.00487171, 0.00464035", \ + "0.0224339, 0.017169, 0.0152434, 0.0135117, 0.0113611, 0.00959732, 0.00715417" \ ); } } @@ -24876,28 +24950,28 @@ library (sg13g2_stdcell_slow_1p35V_125C) { direction : "input"; max_transition : 2.5074; capacitance : 0.00334236; - rise_capacitance : 0.00341895; - rise_capacitance_range (0.00341895, 0.00341895); - fall_capacitance : 0.00326576; - fall_capacitance_range (0.00326576, 0.00326576); + rise_capacitance : 0.00341898; + rise_capacitance_range (0.00299069, 0.0038357); + fall_capacitance : 0.00326574; + fall_capacitance_range (0.00285017, 0.0035668); } pin (A2) { direction : "input"; max_transition : 2.5074; - capacitance : 0.00328808; - rise_capacitance : 0.00349203; - rise_capacitance_range (0.00349203, 0.00349203); - fall_capacitance : 0.00308412; - fall_capacitance_range (0.00308412, 0.00308412); + capacitance : 0.00328807; + rise_capacitance : 0.00349204; + rise_capacitance_range (0.00279903, 0.00414238); + fall_capacitance : 0.0030841; + fall_capacitance_range (0.00284503, 0.00326132); } pin (B1) { direction : "input"; max_transition : 2.5074; - capacitance : 0.00314615; - rise_capacitance : 0.00321543; - rise_capacitance_range (0.00321543, 0.00321543); - fall_capacitance : 0.00307686; - fall_capacitance_range (0.00307686, 0.00307686); + capacitance : 0.00314616; + rise_capacitance : 0.00321546; + rise_capacitance_range (0.00280057, 0.00369111); + fall_capacitance : 0.00307687; + fall_capacitance_range (0.00267361, 0.00344422); } } cell (sg13g2_or2_1) { @@ -25103,18 +25177,18 @@ library (sg13g2_stdcell_slow_1p35V_125C) { max_transition : 2.5074; capacitance : 0.00245028; rise_capacitance : 0.00243437; - rise_capacitance_range (0.00243437, 0.00243437); + rise_capacitance_range (0.00222741, 0.00261987); fall_capacitance : 0.00246619; - fall_capacitance_range (0.00246619, 0.00246619); + fall_capacitance_range (0.00214204, 0.00267758); } pin (B) { direction : "input"; max_transition : 2.5074; capacitance : 0.00227246; rise_capacitance : 0.00235035; - rise_capacitance_range (0.00235035, 0.00235035); + rise_capacitance_range (0.00197632, 0.00265039); fall_capacitance : 0.00219457; - fall_capacitance_range (0.00219457, 0.00219457); + fall_capacitance_range (0.00200474, 0.00232015); } } cell (sg13g2_or2_2) { @@ -25320,18 +25394,18 @@ library (sg13g2_stdcell_slow_1p35V_125C) { max_transition : 2.5074; capacitance : 0.00243353; rise_capacitance : 0.00241218; - rise_capacitance_range (0.00241218, 0.00241218); + rise_capacitance_range (0.00223894, 0.0025816); fall_capacitance : 0.00245488; - fall_capacitance_range (0.00245488, 0.00245488); + fall_capacitance_range (0.00214441, 0.00265467); } pin (B) { direction : "input"; max_transition : 2.5074; capacitance : 0.00225231; rise_capacitance : 0.00232398; - rise_capacitance_range (0.00232398, 0.00232398); + rise_capacitance_range (0.00203703, 0.00258128); fall_capacitance : 0.00218064; - fall_capacitance_range (0.00218064, 0.00218064); + fall_capacitance_range (0.00202331, 0.00229204); } } cell (sg13g2_or3_1) { @@ -25639,27 +25713,27 @@ library (sg13g2_stdcell_slow_1p35V_125C) { max_transition : 2.5074; capacitance : 0.00257004; rise_capacitance : 0.00256235; - rise_capacitance_range (0.00256235, 0.00256235); + rise_capacitance_range (0.00237405, 0.00273135); fall_capacitance : 0.00257774; - fall_capacitance_range (0.00257774, 0.00257774); + fall_capacitance_range (0.00219736, 0.00286023); } pin (B) { direction : "input"; max_transition : 2.5074; capacitance : 0.00249936; rise_capacitance : 0.00253978; - rise_capacitance_range (0.00253978, 0.00253978); + rise_capacitance_range (0.00220849, 0.00280588); fall_capacitance : 0.00245895; - fall_capacitance_range (0.00245895, 0.00245895); + fall_capacitance_range (0.00208444, 0.0027038); } pin (C) { direction : "input"; max_transition : 2.5074; capacitance : 0.0023729; rise_capacitance : 0.00250071; - rise_capacitance_range (0.00250071, 0.00250071); + rise_capacitance_range (0.00206736, 0.00286884); fall_capacitance : 0.00224509; - fall_capacitance_range (0.00224509, 0.00224509); + fall_capacitance_range (0.00204473, 0.0023723); } } cell (sg13g2_or3_2) { @@ -25967,27 +26041,27 @@ library (sg13g2_stdcell_slow_1p35V_125C) { max_transition : 2.5074; capacitance : 0.00255865; rise_capacitance : 0.00254755; - rise_capacitance_range (0.00254755, 0.00254755); + rise_capacitance_range (0.00237871, 0.00270613); fall_capacitance : 0.00256975; - fall_capacitance_range (0.00256975, 0.00256975); + fall_capacitance_range (0.00219996, 0.00283948); } pin (B) { direction : "input"; max_transition : 2.5074; capacitance : 0.00248887; rise_capacitance : 0.00252309; - rise_capacitance_range (0.00252309, 0.00252309); + rise_capacitance_range (0.00222852, 0.00276716); fall_capacitance : 0.00245465; - fall_capacitance_range (0.00245465, 0.00245465); + fall_capacitance_range (0.00208813, 0.00269067); } pin (C) { direction : "input"; max_transition : 2.5074; capacitance : 0.0023605; rise_capacitance : 0.00248361; - rise_capacitance_range (0.00248361, 0.00248361); + rise_capacitance_range (0.00213891, 0.00280332); fall_capacitance : 0.00223739; - fall_capacitance_range (0.00223739, 0.00223739); + fall_capacitance_range (0.00206685, 0.00235155); } } cell (sg13g2_or4_1) { @@ -26413,36 +26487,36 @@ library (sg13g2_stdcell_slow_1p35V_125C) { max_transition : 2.5074; capacitance : 0.00256401; rise_capacitance : 0.00255601; - rise_capacitance_range (0.00255601, 0.00255601); + rise_capacitance_range (0.00238955, 0.00272011); fall_capacitance : 0.002572; - fall_capacitance_range (0.002572, 0.002572); + fall_capacitance_range (0.00220422, 0.00287692); } pin (B) { direction : "input"; max_transition : 2.5074; capacitance : 0.00246805; rise_capacitance : 0.00249995; - rise_capacitance_range (0.00249995, 0.00249995); + rise_capacitance_range (0.00220285, 0.00275023); fall_capacitance : 0.00243616; - fall_capacitance_range (0.00243616, 0.00243616); + fall_capacitance_range (0.00207725, 0.00271712); } pin (C) { direction : "input"; max_transition : 2.5074; capacitance : 0.00243845; rise_capacitance : 0.00250225; - rise_capacitance_range (0.00250225, 0.00250225); + rise_capacitance_range (0.00213752, 0.00283483); fall_capacitance : 0.00237465; - fall_capacitance_range (0.00237465, 0.00237465); + fall_capacitance_range (0.00202115, 0.00260769); } pin (D) { direction : "input"; max_transition : 2.5074; capacitance : 0.00235403; rise_capacitance : 0.00249693; - rise_capacitance_range (0.00249693, 0.00249693); + rise_capacitance_range (0.0020664, 0.00292356); fall_capacitance : 0.00221112; - fall_capacitance_range (0.00221112, 0.00221112); + fall_capacitance_range (0.00203499, 0.00231087); } } cell (sg13g2_or4_2) { @@ -26868,41 +26942,41 @@ library (sg13g2_stdcell_slow_1p35V_125C) { max_transition : 2.5074; capacitance : 0.00254135; rise_capacitance : 0.00252946; - rise_capacitance_range (0.00252946, 0.00252946); + rise_capacitance_range (0.00237647, 0.00268249); fall_capacitance : 0.00255323; - fall_capacitance_range (0.00255323, 0.00255323); + fall_capacitance_range (0.00219272, 0.00284661); } pin (B) { direction : "input"; max_transition : 2.5074; capacitance : 0.0024628; rise_capacitance : 0.00248937; - rise_capacitance_range (0.00248937, 0.00248937); + rise_capacitance_range (0.00221211, 0.00272292); fall_capacitance : 0.00243623; - fall_capacitance_range (0.00243623, 0.00243623); + fall_capacitance_range (0.00208472, 0.00270947); } pin (C) { direction : "input"; max_transition : 2.5074; capacitance : 0.00243217; rise_capacitance : 0.00248879; - rise_capacitance_range (0.00248879, 0.00248879); + rise_capacitance_range (0.00216391, 0.00279224); fall_capacitance : 0.00237555; - fall_capacitance_range (0.00237555, 0.00237555); + fall_capacitance_range (0.00203112, 0.00260281); } pin (D) { direction : "input"; max_transition : 2.5074; capacitance : 0.00234305; rise_capacitance : 0.00247879; - rise_capacitance_range (0.00247879, 0.00247879); + rise_capacitance_range (0.00213443, 0.00284957); fall_capacitance : 0.00220732; - fall_capacitance_range (0.00220732, 0.00220732); + fall_capacitance_range (0.00205825, 0.00229828); } } cell (sg13g2_sdfbbp_1) { area : 63.504; - cell_footprint : "sdfrrs"; + cell_footprint : "sdfbbp"; cell_leakage_power : 5790.66; dont_touch : true; dont_use : true; @@ -26998,6 +27072,7 @@ library (sg13g2_stdcell_slow_1p35V_125C) { timing () { related_pin : "CLK"; sdf_cond : "SCE == 1'b1"; + sdf_edges : start_edge; timing_sense : non_unate; timing_type : rising_edge; when : "SCE"; @@ -27056,6 +27131,7 @@ library (sg13g2_stdcell_slow_1p35V_125C) { } timing () { related_pin : "CLK"; + sdf_edges : start_edge; timing_sense : non_unate; timing_type : rising_edge; cell_rise (TIMING_DELAY_7x7ds1) { @@ -27113,6 +27189,7 @@ library (sg13g2_stdcell_slow_1p35V_125C) { } timing () { related_pin : "RESET_B"; + sdf_edges : start_edge; timing_sense : positive_unate; timing_type : clear; cell_fall (TIMING_DELAY_7x7ds1) { @@ -27144,6 +27221,7 @@ library (sg13g2_stdcell_slow_1p35V_125C) { } timing () { related_pin : "SET_B"; + sdf_edges : start_edge; timing_sense : negative_unate; timing_type : preset; cell_rise (TIMING_DELAY_7x7ds1) { @@ -27283,6 +27361,7 @@ library (sg13g2_stdcell_slow_1p35V_125C) { timing () { related_pin : "CLK"; sdf_cond : "SCE == 1'b1"; + sdf_edges : start_edge; timing_sense : non_unate; timing_type : rising_edge; when : "SCE"; @@ -27341,6 +27420,7 @@ library (sg13g2_stdcell_slow_1p35V_125C) { } timing () { related_pin : "CLK"; + sdf_edges : start_edge; timing_sense : non_unate; timing_type : rising_edge; cell_rise (TIMING_DELAY_7x7ds1) { @@ -27398,6 +27478,7 @@ library (sg13g2_stdcell_slow_1p35V_125C) { } timing () { related_pin : "RESET_B"; + sdf_edges : start_edge; timing_sense : negative_unate; timing_type : preset; cell_rise (TIMING_DELAY_7x7ds1) { @@ -27429,6 +27510,7 @@ library (sg13g2_stdcell_slow_1p35V_125C) { } timing () { related_pin : "SET_B"; + sdf_edges : start_edge; timing_sense : positive_unate; timing_type : clear; cell_fall (TIMING_DELAY_7x7ds1) { @@ -27566,9 +27648,9 @@ library (sg13g2_stdcell_slow_1p35V_125C) { max_transition : 2.5074; capacitance : 0.00298563; rise_capacitance : 0.00303456; - rise_capacitance_range (0.00303456, 0.00303456); + rise_capacitance_range (0.00274728, 0.00328835); fall_capacitance : 0.00292447; - fall_capacitance_range (0.00292447, 0.00292447); + fall_capacitance_range (0.00271081, 0.00312951); timing () { related_pin : "CLK"; timing_type : min_pulse_width; @@ -27724,11 +27806,12 @@ library (sg13g2_stdcell_slow_1p35V_125C) { max_transition : 2.5074; capacitance : 0.00194676; rise_capacitance : 0.00198011; - rise_capacitance_range (0.00198011, 0.00198011); + rise_capacitance_range (0.0017783, 0.00212911); fall_capacitance : 0.00191341; - fall_capacitance_range (0.00191341, 0.00191341); + fall_capacitance_range (0.00175719, 0.00202297); timing () { related_pin : "CLK"; + sdf_edges : both_edges; timing_type : hold_rising; rise_constraint (CONSTRAINT_4x4) { index_1 ("0.0186, 0.51636, 1.263, 2.5074"); @@ -27753,6 +27836,7 @@ library (sg13g2_stdcell_slow_1p35V_125C) { } timing () { related_pin : "CLK"; + sdf_edges : both_edges; timing_type : setup_rising; rise_constraint (CONSTRAINT_4x4) { index_1 ("0.0186, 0.51636, 1.263, 2.5074"); @@ -27827,9 +27911,10 @@ library (sg13g2_stdcell_slow_1p35V_125C) { rise_capacitance : 0.00171449; rise_capacitance_range (0.00171449, 0.00171449); fall_capacitance : 0.00171449; - fall_capacitance_range (0.00171449, 0.00171449); + fall_capacitance_range (0.00160866, 0.00182208); timing () { related_pin : "CLK"; + sdf_edges : both_edges; timing_type : recovery_rising; rise_constraint (CONSTRAINT_4x4) { index_1 ("0.0186, 0.51636, 1.263, 2.5074"); @@ -27844,6 +27929,7 @@ library (sg13g2_stdcell_slow_1p35V_125C) { } timing () { related_pin : "CLK"; + sdf_edges : both_edges; timing_type : removal_rising; rise_constraint (CONSTRAINT_4x4) { index_1 ("0.0186, 0.51636, 1.263, 2.5074"); @@ -27873,11 +27959,12 @@ library (sg13g2_stdcell_slow_1p35V_125C) { max_transition : 2.5074; capacitance : 0.00195759; rise_capacitance : 0.00197736; - rise_capacitance_range (0.00197736, 0.00197736); + rise_capacitance_range (0.00174616, 0.00212679); fall_capacitance : 0.00193782; - fall_capacitance_range (0.00193782, 0.00193782); + fall_capacitance_range (0.00172997, 0.00208772); timing () { related_pin : "CLK"; + sdf_edges : both_edges; timing_type : hold_rising; rise_constraint (CONSTRAINT_4x4) { index_1 ("0.0186, 0.51636, 1.263, 2.5074"); @@ -27902,6 +27989,7 @@ library (sg13g2_stdcell_slow_1p35V_125C) { } timing () { related_pin : "CLK"; + sdf_edges : both_edges; timing_type : setup_rising; rise_constraint (CONSTRAINT_4x4) { index_1 ("0.0186, 0.51636, 1.263, 2.5074"); @@ -27975,11 +28063,12 @@ library (sg13g2_stdcell_slow_1p35V_125C) { max_transition : 2.5074; capacitance : 0.00349924; rise_capacitance : 0.00381092; - rise_capacitance_range (0.00381092, 0.00381092); + rise_capacitance_range (0.00360381, 0.00422103); fall_capacitance : 0.00318756; - fall_capacitance_range (0.00318756, 0.00318756); + fall_capacitance_range (0.00318756, 0.00414677); timing () { related_pin : "CLK"; + sdf_edges : both_edges; timing_type : hold_rising; rise_constraint (CONSTRAINT_4x4) { index_1 ("0.0186, 0.51636, 1.263, 2.5074"); @@ -28004,6 +28093,7 @@ library (sg13g2_stdcell_slow_1p35V_125C) { } timing () { related_pin : "CLK"; + sdf_edges : both_edges; timing_type : setup_rising; rise_constraint (CONSTRAINT_4x4) { index_1 ("0.0186, 0.51636, 1.263, 2.5074"); @@ -28108,9 +28198,10 @@ library (sg13g2_stdcell_slow_1p35V_125C) { rise_capacitance : 0.00516883; rise_capacitance_range (0.00516883, 0.00516883); fall_capacitance : 0.00516883; - fall_capacitance_range (0.00516883, 0.00516883); + fall_capacitance_range (0.00485117, 0.00547056); timing () { related_pin : "CLK"; + sdf_edges : both_edges; timing_type : recovery_rising; rise_constraint (CONSTRAINT_4x4) { index_1 ("0.0186, 0.51636, 1.263, 2.5074"); @@ -28125,6 +28216,7 @@ library (sg13g2_stdcell_slow_1p35V_125C) { } timing () { related_pin : "CLK"; + sdf_edges : both_edges; timing_type : removal_rising; rise_constraint (CONSTRAINT_4x4) { index_1 ("0.0186, 0.51636, 1.263, 2.5074"); @@ -28139,6 +28231,7 @@ library (sg13g2_stdcell_slow_1p35V_125C) { } timing () { related_pin : "RESET_B"; + sdf_edges : both_edges; timing_type : non_seq_hold_rising; rise_constraint (CONSTRAINT_4x4) { index_1 ("0.0186, 0.51636, 1.263, 2.5074"); @@ -28153,6 +28246,7 @@ library (sg13g2_stdcell_slow_1p35V_125C) { } timing () { related_pin : "RESET_B"; + sdf_edges : both_edges; timing_type : non_seq_setup_rising; rise_constraint (CONSTRAINT_4x4) { index_1 ("0.0186, 0.51636, 1.263, 2.5074"); @@ -28177,12 +28271,12 @@ library (sg13g2_stdcell_slow_1p35V_125C) { } } ff (IQ,IQN) { - clear : "RESET_B'"; + clear : "!RESET_B"; clear_preset_var1 : "H"; clear_preset_var2 : "L"; clocked_on : "CLK"; - next_state : "(SCE*SCD)+(SCE'*D)"; - preset : "SET_B'"; + next_state : "(SCE*SCD)+(!SCE*D)"; + preset : "!SET_B"; } test_cell () { pin (Q) { @@ -28216,12 +28310,12 @@ library (sg13g2_stdcell_slow_1p35V_125C) { direction : input; } ff (IQ,IQN) { - clear : "RESET_B'"; + clear : "!RESET_B"; clear_preset_var1 : H; clear_preset_var2 : L; clocked_on : "CLK"; next_state : "D"; - preset : "SET_B'"; + preset : "!SET_B"; } } } @@ -28258,7 +28352,7 @@ library (sg13g2_stdcell_slow_1p35V_125C) { when : "!CLK&D&RESET_B&!SCD&!SCE&Q&!Q_N"; } leakage_power () { - value : 6319.37; + value : 6319.36; when : "CLK&D&RESET_B&!SCD&!SCE&!Q&Q_N"; } leakage_power () { @@ -28305,6 +28399,7 @@ library (sg13g2_stdcell_slow_1p35V_125C) { timing () { related_pin : "CLK"; sdf_cond : "SCE == 1'b1"; + sdf_edges : start_edge; timing_sense : non_unate; timing_type : rising_edge; when : "SCE"; @@ -28312,7 +28407,7 @@ library (sg13g2_stdcell_slow_1p35V_125C) { index_1 ("0.0186, 0.0966, 0.174, 0.3294, 0.6408, 1.263, 2.5074"); index_2 ("0.001, 0.0234, 0.039, 0.0648, 0.108, 0.18, 0.3"); values ( \ - "0.188269, 0.251861, 0.298154, 0.374117, 0.502028, 0.715163, 1.0705", \ + "0.188284, 0.251957, 0.297943, 0.374507, 0.502028, 0.715148, 1.07049", \ "0.220849, 0.284537, 0.330551, 0.406891, 0.534705, 0.747692, 1.10264", \ "0.242341, 0.305941, 0.351995, 0.428346, 0.555955, 0.769036, 1.12441", \ "0.274319, 0.337862, 0.383868, 0.460129, 0.587918, 0.800807, 1.15595", \ @@ -28325,22 +28420,22 @@ library (sg13g2_stdcell_slow_1p35V_125C) { index_1 ("0.0186, 0.0966, 0.174, 0.3294, 0.6408, 1.263, 2.5074"); index_2 ("0.001, 0.0234, 0.039, 0.0648, 0.108, 0.18, 0.3"); values ( \ - "0.0220552, 0.111518, 0.178939, 0.290671, 0.478062, 0.790506, 1.31123", \ - "0.0220562, 0.111519, 0.17894, 0.291071, 0.478063, 0.790507, 1.31124", \ - "0.0220572, 0.11152, 0.178941, 0.291072, 0.478064, 0.794149, 1.31195", \ - "0.0220582, 0.111521, 0.178942, 0.291073, 0.478065, 0.79415, 1.31196", \ - "0.0221449, 0.111522, 0.178949, 0.291074, 0.478066, 0.794151, 1.31197", \ - "0.02235, 0.111553, 0.17895, 0.291075, 0.478067, 0.794152, 1.31198", \ - "0.02335, 0.111679, 0.179011, 0.291076, 0.478068, 0.794153, 1.31199" \ + "0.0220504, 0.111514, 0.178898, 0.290688, 0.478061, 0.790618, 1.31123", \ + "0.0220514, 0.111515, 0.178899, 0.291071, 0.478062, 0.790619, 1.31124", \ + "0.0220524, 0.111516, 0.1789, 0.291072, 0.478063, 0.794149, 1.31195", \ + "0.0220534, 0.111517, 0.178901, 0.291073, 0.478064, 0.79415, 1.31196", \ + "0.0221449, 0.111521, 0.178949, 0.291074, 0.478065, 0.794151, 1.31197", \ + "0.02235, 0.111553, 0.17895, 0.291075, 0.478066, 0.794152, 1.31198", \ + "0.02335, 0.111679, 0.179011, 0.291076, 0.478067, 0.794153, 1.31199" \ ); } cell_fall (TIMING_DELAY_7x7ds1) { index_1 ("0.0186, 0.0966, 0.174, 0.3294, 0.6408, 1.263, 2.5074"); index_2 ("0.001, 0.0234, 0.039, 0.0648, 0.108, 0.18, 0.3"); values ( \ - "0.172455, 0.231938, 0.271822, 0.337482, 0.44743, 0.63067, 0.936247", \ + "0.172494, 0.231937, 0.27182, 0.337516, 0.447465, 0.630718, 0.936232", \ "0.204745, 0.264419, 0.304227, 0.369941, 0.479875, 0.663182, 0.96884", \ - "0.225737, 0.285275, 0.325126, 0.390887, 0.500892, 0.684158, 0.989502", \ + "0.225737, 0.285275, 0.325126, 0.390895, 0.500882, 0.684158, 0.989502", \ "0.256245, 0.315839, 0.355684, 0.421381, 0.531323, 0.714529, 1.01984", \ "0.295025, 0.354546, 0.394387, 0.460123, 0.570085, 0.753305, 1.05863", \ "0.347047, 0.406621, 0.446482, 0.512192, 0.62217, 0.805375, 1.11068", \ @@ -28351,25 +28446,26 @@ library (sg13g2_stdcell_slow_1p35V_125C) { index_1 ("0.0186, 0.0966, 0.174, 0.3294, 0.6408, 1.263, 2.5074"); index_2 ("0.001, 0.0234, 0.039, 0.0648, 0.108, 0.18, 0.3"); values ( \ - "0.0176441, 0.0891501, 0.141763, 0.229296, 0.376012, 0.621498, 1.02929", \ - "0.0176451, 0.0891511, 0.141764, 0.229329, 0.37605, 0.621513, 1.02981", \ - "0.0176488, 0.0891521, 0.141765, 0.22933, 0.376232, 0.621891, 1.02992", \ - "0.0176498, 0.0891531, 0.141766, 0.229331, 0.376233, 0.621892, 1.02993", \ - "0.0176567, 0.0891541, 0.141767, 0.229332, 0.376246, 0.621893, 1.02994", \ - "0.0176577, 0.0891551, 0.141768, 0.229333, 0.376247, 0.621894, 1.02995", \ + "0.0176024, 0.08915, 0.141763, 0.22918, 0.376012, 0.621497, 1.02929", \ + "0.017618, 0.089151, 0.141764, 0.229329, 0.37605, 0.621513, 1.02981", \ + "0.0176488, 0.089152, 0.141765, 0.22933, 0.376051, 0.621891, 1.02992", \ + "0.0176498, 0.089153, 0.141766, 0.229331, 0.376052, 0.621892, 1.02993", \ + "0.0176567, 0.089154, 0.141767, 0.229332, 0.376246, 0.621893, 1.02994", \ + "0.0176577, 0.089155, 0.141768, 0.229333, 0.376247, 0.621894, 1.02995", \ "0.0176587, 0.089163, 0.141769, 0.229334, 0.376248, 0.621895, 1.02996" \ ); } } timing () { related_pin : "CLK"; + sdf_edges : start_edge; timing_sense : non_unate; timing_type : rising_edge; cell_rise (TIMING_DELAY_7x7ds1) { index_1 ("0.0186, 0.0966, 0.174, 0.3294, 0.6408, 1.263, 2.5074"); index_2 ("0.001, 0.0234, 0.039, 0.0648, 0.108, 0.18, 0.3"); values ( \ - "0.188269, 0.251861, 0.298154, 0.374117, 0.502028, 0.715163, 1.0705", \ + "0.188284, 0.251957, 0.297943, 0.374507, 0.502028, 0.715148, 1.07049", \ "0.220849, 0.284537, 0.330551, 0.406891, 0.534705, 0.747692, 1.10264", \ "0.242341, 0.305941, 0.351995, 0.428346, 0.555955, 0.769036, 1.12441", \ "0.274319, 0.337862, 0.383868, 0.460129, 0.587918, 0.800807, 1.15595", \ @@ -28382,22 +28478,22 @@ library (sg13g2_stdcell_slow_1p35V_125C) { index_1 ("0.0186, 0.0966, 0.174, 0.3294, 0.6408, 1.263, 2.5074"); index_2 ("0.001, 0.0234, 0.039, 0.0648, 0.108, 0.18, 0.3"); values ( \ - "0.0220552, 0.111518, 0.178939, 0.290671, 0.478062, 0.790506, 1.31123", \ - "0.0220562, 0.111519, 0.17894, 0.291071, 0.478063, 0.790507, 1.31124", \ - "0.0220572, 0.11152, 0.178941, 0.291072, 0.478064, 0.794149, 1.31195", \ - "0.0220582, 0.111521, 0.178942, 0.291073, 0.478065, 0.79415, 1.31196", \ - "0.0221449, 0.111522, 0.178949, 0.291074, 0.478066, 0.794151, 1.31197", \ - "0.02235, 0.111553, 0.17895, 0.291075, 0.478067, 0.794152, 1.31198", \ - "0.02335, 0.111679, 0.179011, 0.291076, 0.478068, 0.794153, 1.31199" \ + "0.0220504, 0.111514, 0.178898, 0.290688, 0.478061, 0.790618, 1.31123", \ + "0.0220514, 0.111515, 0.178899, 0.291071, 0.478062, 0.790619, 1.31124", \ + "0.0220524, 0.111516, 0.1789, 0.291072, 0.478063, 0.794149, 1.31195", \ + "0.0220534, 0.111517, 0.178901, 0.291073, 0.478064, 0.79415, 1.31196", \ + "0.0221449, 0.111521, 0.178949, 0.291074, 0.478065, 0.794151, 1.31197", \ + "0.02235, 0.111553, 0.17895, 0.291075, 0.478066, 0.794152, 1.31198", \ + "0.02335, 0.111679, 0.179011, 0.291076, 0.478067, 0.794153, 1.31199" \ ); } cell_fall (TIMING_DELAY_7x7ds1) { index_1 ("0.0186, 0.0966, 0.174, 0.3294, 0.6408, 1.263, 2.5074"); index_2 ("0.001, 0.0234, 0.039, 0.0648, 0.108, 0.18, 0.3"); values ( \ - "0.172455, 0.231938, 0.271822, 0.337482, 0.44743, 0.63067, 0.936247", \ + "0.172494, 0.231937, 0.27182, 0.337516, 0.447465, 0.630718, 0.936232", \ "0.204745, 0.264419, 0.304227, 0.369941, 0.479875, 0.663182, 0.96884", \ - "0.225737, 0.285275, 0.325126, 0.390887, 0.500892, 0.684158, 0.989502", \ + "0.225737, 0.285275, 0.325126, 0.390895, 0.500882, 0.684158, 0.989502", \ "0.256245, 0.315839, 0.355684, 0.421381, 0.531323, 0.714529, 1.01984", \ "0.295025, 0.354546, 0.394387, 0.460123, 0.570085, 0.753305, 1.05863", \ "0.347047, 0.406621, 0.446482, 0.512192, 0.62217, 0.805375, 1.11068", \ @@ -28408,30 +28504,31 @@ library (sg13g2_stdcell_slow_1p35V_125C) { index_1 ("0.0186, 0.0966, 0.174, 0.3294, 0.6408, 1.263, 2.5074"); index_2 ("0.001, 0.0234, 0.039, 0.0648, 0.108, 0.18, 0.3"); values ( \ - "0.0176441, 0.0891501, 0.141763, 0.229296, 0.376012, 0.621498, 1.02929", \ - "0.0176451, 0.0891511, 0.141764, 0.229329, 0.37605, 0.621513, 1.02981", \ - "0.0176488, 0.0891521, 0.141765, 0.22933, 0.376232, 0.621891, 1.02992", \ - "0.0176498, 0.0891531, 0.141766, 0.229331, 0.376233, 0.621892, 1.02993", \ - "0.0176567, 0.0891541, 0.141767, 0.229332, 0.376246, 0.621893, 1.02994", \ - "0.0176577, 0.0891551, 0.141768, 0.229333, 0.376247, 0.621894, 1.02995", \ + "0.0176024, 0.08915, 0.141763, 0.22918, 0.376012, 0.621497, 1.02929", \ + "0.017618, 0.089151, 0.141764, 0.229329, 0.37605, 0.621513, 1.02981", \ + "0.0176488, 0.089152, 0.141765, 0.22933, 0.376051, 0.621891, 1.02992", \ + "0.0176498, 0.089153, 0.141766, 0.229331, 0.376052, 0.621892, 1.02993", \ + "0.0176567, 0.089154, 0.141767, 0.229332, 0.376246, 0.621893, 1.02994", \ + "0.0176577, 0.089155, 0.141768, 0.229333, 0.376247, 0.621894, 1.02995", \ "0.0176587, 0.089163, 0.141769, 0.229334, 0.376248, 0.621895, 1.02996" \ ); } } timing () { related_pin : "RESET_B"; + sdf_edges : start_edge; timing_sense : positive_unate; timing_type : clear; cell_fall (TIMING_DELAY_7x7ds1) { index_1 ("0.0186, 0.0966, 0.174, 0.3294, 0.6408, 1.263, 2.5074"); index_2 ("0.001, 0.0234, 0.039, 0.0648, 0.108, 0.18, 0.3"); values ( \ - "0.243871, 0.303366, 0.343142, 0.408098, 0.51563, 0.69299, 0.986849", \ - "0.282439, 0.341993, 0.381801, 0.447179, 0.555448, 0.733874, 1.02882", \ + "0.243871, 0.303365, 0.343142, 0.408097, 0.51563, 0.692997, 0.98685", \ + "0.282439, 0.341993, 0.381806, 0.447179, 0.555448, 0.733874, 1.02882", \ "0.315934, 0.375429, 0.415383, 0.480948, 0.589724, 0.769032, 1.06487", \ "0.368378, 0.427862, 0.467777, 0.533388, 0.642802, 0.82324, 1.12071", \ "0.447423, 0.506809, 0.546718, 0.612483, 0.722293, 0.904199, 1.20417", \ - "0.557259, 0.616423, 0.656578, 0.722193, 0.832108, 1.01509, 1.31809", \ + "0.557259, 0.616423, 0.656578, 0.722193, 0.832114, 1.01509, 1.31809", \ "0.710065, 0.769668, 0.809392, 0.875127, 0.984718, 1.16846, 1.47362" \ ); } @@ -28439,11 +28536,11 @@ library (sg13g2_stdcell_slow_1p35V_125C) { index_1 ("0.0186, 0.0966, 0.174, 0.3294, 0.6408, 1.263, 2.5074"); index_2 ("0.001, 0.0234, 0.039, 0.0648, 0.108, 0.18, 0.3"); values ( \ - "0.0174393, 0.0890822, 0.141635, 0.229243, 0.376235, 0.621333, 1.02986", \ - "0.0174403, 0.0890839, 0.141657, 0.229244, 0.376236, 0.621374, 1.02987", \ - "0.0174461, 0.0890849, 0.141658, 0.229245, 0.376237, 0.621375, 1.02988", \ - "0.0174728, 0.0890859, 0.141659, 0.229246, 0.376238, 0.621376, 1.03067", \ - "0.0175981, 0.0891002, 0.14166, 0.229247, 0.376239, 0.621377, 1.03068", \ + "0.0174394, 0.0890823, 0.141635, 0.229243, 0.376235, 0.621333, 1.02986", \ + "0.0174404, 0.0890838, 0.141636, 0.229244, 0.376236, 0.621374, 1.02987", \ + "0.0174461, 0.0890848, 0.141641, 0.229245, 0.376237, 0.621375, 1.02988", \ + "0.0174728, 0.0890858, 0.141642, 0.229246, 0.376238, 0.621376, 1.03067", \ + "0.0175981, 0.0891002, 0.141643, 0.229247, 0.376239, 0.621377, 1.03068", \ "0.017732, 0.089144, 0.141665, 0.229248, 0.37624, 0.621378, 1.03069", \ "0.017983, 0.08921, 0.141688, 0.229264, 0.376241, 0.621379, 1.0307" \ ); @@ -28456,12 +28553,12 @@ library (sg13g2_stdcell_slow_1p35V_125C) { index_1 ("0.0186, 0.0966, 0.174, 0.3294, 0.6408, 1.263, 2.5074"); index_2 ("0.001, 0.0234, 0.039, 0.0648, 0.108, 0.18, 0.3"); values ( \ - "0.0372992, 0.058232, 0.0726363, 0.0960644, 0.135346, 0.200751, 0.309708", \ - "0.0370415, 0.0580784, 0.072483, 0.0959578, 0.135105, 0.200433, 0.30929", \ + "0.0372999, 0.058259, 0.0725659, 0.0961652, 0.135346, 0.200809, 0.309706", \ + "0.0370415, 0.0580784, 0.0724831, 0.0959578, 0.135105, 0.200433, 0.309289", \ "0.0372047, 0.0581166, 0.0724707, 0.096118, 0.135541, 0.201591, 0.309662", \ "0.0383673, 0.0592577, 0.0735781, 0.0970711, 0.136711, 0.201847, 0.310647", \ - "0.0408208, 0.0615769, 0.0760285, 0.0995775, 0.138701, 0.204329, 0.313015", \ - "0.046489, 0.0670684, 0.0814229, 0.104966, 0.144562, 0.210058, 0.318605", \ + "0.0408208, 0.0615769, 0.0760284, 0.0995775, 0.138701, 0.204329, 0.313015", \ + "0.0464893, 0.0670684, 0.0814229, 0.104966, 0.144562, 0.210058, 0.318605", \ "0.0591741, 0.0793522, 0.0936716, 0.117329, 0.1567, 0.222275, 0.331659" \ ); } @@ -28469,11 +28566,11 @@ library (sg13g2_stdcell_slow_1p35V_125C) { index_1 ("0.0186, 0.0966, 0.174, 0.3294, 0.6408, 1.263, 2.5074"); index_2 ("0.001, 0.0234, 0.039, 0.0648, 0.108, 0.18, 0.3"); values ( \ - "0.0398815, 0.0609083, 0.0751683, 0.0985482, 0.137553, 0.202484, 0.310765", \ + "0.0398748, 0.0609081, 0.0751677, 0.0985377, 0.137562, 0.202493, 0.31076", \ "0.0397232, 0.0609247, 0.0752677, 0.098627, 0.137443, 0.202424, 0.310832", \ - "0.0400527, 0.0610557, 0.0753733, 0.0989776, 0.137784, 0.202947, 0.311125", \ + "0.0400527, 0.0610557, 0.0753733, 0.0990473, 0.137959, 0.202947, 0.311125", \ "0.0413263, 0.0624664, 0.0767193, 0.100029, 0.139352, 0.204262, 0.312262", \ - "0.0437817, 0.0648771, 0.0790939, 0.102883, 0.141902, 0.206759, 0.317805", \ + "0.0437817, 0.0648769, 0.0790939, 0.102883, 0.141902, 0.206759, 0.317805", \ "0.0493232, 0.0703994, 0.0846845, 0.108283, 0.147533, 0.213227, 0.320949", \ "0.0612432, 0.0821544, 0.0963474, 0.11994, 0.159427, 0.225019, 0.334266" \ ); @@ -28485,12 +28582,12 @@ library (sg13g2_stdcell_slow_1p35V_125C) { index_1 ("0.0186, 0.0966, 0.174, 0.3294, 0.6408, 1.263, 2.5074"); index_2 ("0.001, 0.0234, 0.039, 0.0648, 0.108, 0.18, 0.3"); values ( \ - "0.0372992, 0.058232, 0.0726363, 0.0960644, 0.135346, 0.200751, 0.309708", \ - "0.0370415, 0.0580784, 0.072483, 0.0959578, 0.135105, 0.200433, 0.30929", \ + "0.0372999, 0.058259, 0.0725659, 0.0961652, 0.135346, 0.200809, 0.309706", \ + "0.0370415, 0.0580784, 0.0724831, 0.0959578, 0.135105, 0.200433, 0.309289", \ "0.0372047, 0.0581166, 0.0724707, 0.096118, 0.135541, 0.201591, 0.309662", \ "0.0383673, 0.0592577, 0.0735781, 0.0970711, 0.136711, 0.201847, 0.310647", \ - "0.0408208, 0.0615769, 0.0760285, 0.0995775, 0.138701, 0.204329, 0.313015", \ - "0.046489, 0.0670684, 0.0814229, 0.104966, 0.144562, 0.210058, 0.318605", \ + "0.0408208, 0.0615769, 0.0760284, 0.0995775, 0.138701, 0.204329, 0.313015", \ + "0.0464893, 0.0670684, 0.0814229, 0.104966, 0.144562, 0.210058, 0.318605", \ "0.0591741, 0.0793522, 0.0936716, 0.117329, 0.1567, 0.222275, 0.331659" \ ); } @@ -28498,11 +28595,11 @@ library (sg13g2_stdcell_slow_1p35V_125C) { index_1 ("0.0186, 0.0966, 0.174, 0.3294, 0.6408, 1.263, 2.5074"); index_2 ("0.001, 0.0234, 0.039, 0.0648, 0.108, 0.18, 0.3"); values ( \ - "0.0398815, 0.0609083, 0.0751683, 0.0985482, 0.137553, 0.202484, 0.310765", \ + "0.0398748, 0.0609081, 0.0751677, 0.0985377, 0.137562, 0.202493, 0.31076", \ "0.0397232, 0.0609247, 0.0752677, 0.098627, 0.137443, 0.202424, 0.310832", \ - "0.0400527, 0.0610557, 0.0753733, 0.0989776, 0.137784, 0.202947, 0.311125", \ + "0.0400527, 0.0610557, 0.0753733, 0.0990473, 0.137959, 0.202947, 0.311125", \ "0.0413263, 0.0624664, 0.0767193, 0.100029, 0.139352, 0.204262, 0.312262", \ - "0.0437817, 0.0648771, 0.0790939, 0.102883, 0.141902, 0.206759, 0.317805", \ + "0.0437817, 0.0648769, 0.0790939, 0.102883, 0.141902, 0.206759, 0.317805", \ "0.0493232, 0.0703994, 0.0846845, 0.108283, 0.147533, 0.213227, 0.320949", \ "0.0612432, 0.0821544, 0.0963474, 0.11994, 0.159427, 0.225019, 0.334266" \ ); @@ -28519,13 +28616,13 @@ library (sg13g2_stdcell_slow_1p35V_125C) { index_1 ("0.0186, 0.0966, 0.174, 0.3294, 0.6408, 1.263, 2.5074"); index_2 ("0.001, 0.0234, 0.039, 0.0648, 0.108, 0.18, 0.3"); values ( \ - "0.0533626, 0.075235, 0.0900673, 0.114221, 0.154066, 0.219692, 0.328468", \ - "0.055813, 0.0777504, 0.0925791, 0.116849, 0.156987, 0.223013, 0.332241", \ - "0.0574619, 0.0793237, 0.0944122, 0.118584, 0.158934, 0.225304, 0.334823", \ - "0.0582664, 0.0801312, 0.0949326, 0.11947, 0.161183, 0.227253, 0.337029", \ - "0.0607917, 0.0824765, 0.0975532, 0.122065, 0.162473, 0.230808, 0.341088", \ - "0.0664693, 0.0882038, 0.103168, 0.127787, 0.169014, 0.237038, 0.348885", \ - "0.0784905, 0.0999765, 0.114522, 0.139028, 0.180447, 0.249092, 0.36309" \ + "0.0533626, 0.075235, 0.0900669, 0.114222, 0.154067, 0.219695, 0.32847", \ + "0.055813, 0.0777506, 0.0925815, 0.116849, 0.156988, 0.223014, 0.332244", \ + "0.0574619, 0.0793239, 0.0944125, 0.118584, 0.158935, 0.225305, 0.334826", \ + "0.0582664, 0.0801314, 0.0949329, 0.119471, 0.161184, 0.227255, 0.337031", \ + "0.0607917, 0.0824767, 0.0975535, 0.122066, 0.162474, 0.230809, 0.34109", \ + "0.0664693, 0.088204, 0.103168, 0.127787, 0.168901, 0.236977, 0.348888", \ + "0.0784905, 0.0999767, 0.114522, 0.139028, 0.180448, 0.249094, 0.363093" \ ); } } @@ -28538,6 +28635,7 @@ library (sg13g2_stdcell_slow_1p35V_125C) { timing () { related_pin : "CLK"; sdf_cond : "SCE == 1'b1"; + sdf_edges : start_edge; timing_sense : non_unate; timing_type : rising_edge; when : "SCE"; @@ -28545,8 +28643,8 @@ library (sg13g2_stdcell_slow_1p35V_125C) { index_1 ("0.0186, 0.0966, 0.174, 0.3294, 0.6408, 1.263, 2.5074"); index_2 ("0.001, 0.0234, 0.039, 0.0648, 0.108, 0.18, 0.3"); values ( \ - "0.133289, 0.219258, 0.266747, 0.343406, 0.47089, 0.682881, 1.03601", \ - "0.165495, 0.251577, 0.299069, 0.375677, 0.502991, 0.716117, 1.06837", \ + "0.133246, 0.219243, 0.266747, 0.343507, 0.470893, 0.682965, 1.03639", \ + "0.165495, 0.251577, 0.299069, 0.375677, 0.502996, 0.716117, 1.06837", \ "0.186504, 0.272513, 0.320054, 0.396615, 0.524118, 0.736277, 1.09182", \ "0.216943, 0.302937, 0.350405, 0.426966, 0.554432, 0.766419, 1.1196", \ "0.255757, 0.341713, 0.389209, 0.465855, 0.593259, 0.805284, 1.15827", \ @@ -28558,20 +28656,20 @@ library (sg13g2_stdcell_slow_1p35V_125C) { index_1 ("0.0186, 0.0966, 0.174, 0.3294, 0.6408, 1.263, 2.5074"); index_2 ("0.001, 0.0234, 0.039, 0.0648, 0.108, 0.18, 0.3"); values ( \ - "0.0266994, 0.119665, 0.183213, 0.291991, 0.47757, 0.788659, 1.30726", \ - "0.0267165, 0.119666, 0.183214, 0.292868, 0.478483, 0.789671, 1.30738", \ - "0.0267175, 0.119667, 0.183252, 0.292869, 0.478484, 0.789672, 1.30957", \ - "0.0267185, 0.119668, 0.183253, 0.29287, 0.478485, 0.789673, 1.31192", \ - "0.0267195, 0.119707, 0.18335, 0.292871, 0.478486, 0.789674, 1.31193", \ - "0.0267205, 0.119708, 0.183351, 0.292872, 0.478487, 0.789675, 1.31194", \ - "0.026757, 0.119709, 0.183352, 0.292873, 0.478488, 0.789676, 1.31195" \ + "0.0266235, 0.119583, 0.183188, 0.291986, 0.47757, 0.788658, 1.30727", \ + "0.0267165, 0.119639, 0.183192, 0.292868, 0.478485, 0.789671, 1.30738", \ + "0.0267175, 0.11964, 0.183252, 0.292869, 0.478486, 0.789672, 1.30957", \ + "0.0267185, 0.119647, 0.183253, 0.29287, 0.478487, 0.789673, 1.31192", \ + "0.0267195, 0.119707, 0.18335, 0.292871, 0.478488, 0.789674, 1.31193", \ + "0.0267205, 0.119708, 0.183351, 0.292872, 0.478489, 0.789675, 1.31194", \ + "0.026757, 0.119709, 0.183352, 0.292873, 0.47849, 0.789676, 1.31195" \ ); } cell_fall (TIMING_DELAY_7x7ds1) { index_1 ("0.0186, 0.0966, 0.174, 0.3294, 0.6408, 1.263, 2.5074"); index_2 ("0.001, 0.0234, 0.039, 0.0648, 0.108, 0.18, 0.3"); values ( \ - "0.141, 0.237225, 0.282564, 0.351445, 0.462666, 0.6468, 0.953422", \ + "0.141044, 0.237213, 0.282534, 0.351443, 0.462666, 0.646847, 0.953422", \ "0.173341, 0.269603, 0.314924, 0.383761, 0.49508, 0.679365, 0.985932", \ "0.194947, 0.291157, 0.336536, 0.405323, 0.516701, 0.700942, 1.00767", \ "0.226842, 0.3229, 0.368287, 0.437086, 0.548467, 0.732627, 1.03919", \ @@ -28584,9 +28682,9 @@ library (sg13g2_stdcell_slow_1p35V_125C) { index_1 ("0.0186, 0.0966, 0.174, 0.3294, 0.6408, 1.263, 2.5074"); index_2 ("0.001, 0.0234, 0.039, 0.0648, 0.108, 0.18, 0.3"); values ( \ - "0.0327558, 0.113013, 0.159549, 0.240817, 0.383417, 0.626929, 1.03696", \ - "0.0328093, 0.113136, 0.159577, 0.240818, 0.383617, 0.62693, 1.03697", \ - "0.0330225, 0.113137, 0.15958, 0.240955, 0.383618, 0.628464, 1.037", \ + "0.0328138, 0.112989, 0.1596, 0.240823, 0.383417, 0.626894, 1.03696", \ + "0.0328148, 0.113136, 0.159601, 0.240824, 0.383617, 0.626895, 1.03697", \ + "0.0330225, 0.113137, 0.159602, 0.240955, 0.383618, 0.628464, 1.037", \ "0.0332077, 0.113138, 0.159699, 0.240956, 0.383619, 0.628465, 1.03701", \ "0.0339349, 0.113395, 0.159929, 0.240983, 0.38362, 0.628466, 1.03702", \ "0.036086, 0.114188, 0.160294, 0.24116, 0.383621, 0.628467, 1.03703", \ @@ -28596,14 +28694,15 @@ library (sg13g2_stdcell_slow_1p35V_125C) { } timing () { related_pin : "CLK"; + sdf_edges : start_edge; timing_sense : non_unate; timing_type : rising_edge; cell_rise (TIMING_DELAY_7x7ds1) { index_1 ("0.0186, 0.0966, 0.174, 0.3294, 0.6408, 1.263, 2.5074"); index_2 ("0.001, 0.0234, 0.039, 0.0648, 0.108, 0.18, 0.3"); values ( \ - "0.133289, 0.219258, 0.266747, 0.343406, 0.47089, 0.682881, 1.03601", \ - "0.165495, 0.251577, 0.299069, 0.375677, 0.502991, 0.716117, 1.06837", \ + "0.133246, 0.219243, 0.266747, 0.343507, 0.470893, 0.682965, 1.03639", \ + "0.165495, 0.251577, 0.299069, 0.375677, 0.502996, 0.716117, 1.06837", \ "0.186504, 0.272513, 0.320054, 0.396615, 0.524118, 0.736277, 1.09182", \ "0.216943, 0.302937, 0.350405, 0.426966, 0.554432, 0.766419, 1.1196", \ "0.255757, 0.341713, 0.389209, 0.465855, 0.593259, 0.805284, 1.15827", \ @@ -28615,20 +28714,20 @@ library (sg13g2_stdcell_slow_1p35V_125C) { index_1 ("0.0186, 0.0966, 0.174, 0.3294, 0.6408, 1.263, 2.5074"); index_2 ("0.001, 0.0234, 0.039, 0.0648, 0.108, 0.18, 0.3"); values ( \ - "0.0266994, 0.119665, 0.183213, 0.291991, 0.47757, 0.788659, 1.30726", \ - "0.0267165, 0.119666, 0.183214, 0.292868, 0.478483, 0.789671, 1.30738", \ - "0.0267175, 0.119667, 0.183252, 0.292869, 0.478484, 0.789672, 1.30957", \ - "0.0267185, 0.119668, 0.183253, 0.29287, 0.478485, 0.789673, 1.31192", \ - "0.0267195, 0.119707, 0.18335, 0.292871, 0.478486, 0.789674, 1.31193", \ - "0.0267205, 0.119708, 0.183351, 0.292872, 0.478487, 0.789675, 1.31194", \ - "0.026757, 0.119709, 0.183352, 0.292873, 0.478488, 0.789676, 1.31195" \ + "0.0266235, 0.119583, 0.183188, 0.291986, 0.47757, 0.788658, 1.30727", \ + "0.0267165, 0.119639, 0.183192, 0.292868, 0.478485, 0.789671, 1.30738", \ + "0.0267175, 0.11964, 0.183252, 0.292869, 0.478486, 0.789672, 1.30957", \ + "0.0267185, 0.119647, 0.183253, 0.29287, 0.478487, 0.789673, 1.31192", \ + "0.0267195, 0.119707, 0.18335, 0.292871, 0.478488, 0.789674, 1.31193", \ + "0.0267205, 0.119708, 0.183351, 0.292872, 0.478489, 0.789675, 1.31194", \ + "0.026757, 0.119709, 0.183352, 0.292873, 0.47849, 0.789676, 1.31195" \ ); } cell_fall (TIMING_DELAY_7x7ds1) { index_1 ("0.0186, 0.0966, 0.174, 0.3294, 0.6408, 1.263, 2.5074"); index_2 ("0.001, 0.0234, 0.039, 0.0648, 0.108, 0.18, 0.3"); values ( \ - "0.141, 0.237225, 0.282564, 0.351445, 0.462666, 0.6468, 0.953422", \ + "0.141044, 0.237213, 0.282534, 0.351443, 0.462666, 0.646847, 0.953422", \ "0.173341, 0.269603, 0.314924, 0.383761, 0.49508, 0.679365, 0.985932", \ "0.194947, 0.291157, 0.336536, 0.405323, 0.516701, 0.700942, 1.00767", \ "0.226842, 0.3229, 0.368287, 0.437086, 0.548467, 0.732627, 1.03919", \ @@ -28641,9 +28740,9 @@ library (sg13g2_stdcell_slow_1p35V_125C) { index_1 ("0.0186, 0.0966, 0.174, 0.3294, 0.6408, 1.263, 2.5074"); index_2 ("0.001, 0.0234, 0.039, 0.0648, 0.108, 0.18, 0.3"); values ( \ - "0.0327558, 0.113013, 0.159549, 0.240817, 0.383417, 0.626929, 1.03696", \ - "0.0328093, 0.113136, 0.159577, 0.240818, 0.383617, 0.62693, 1.03697", \ - "0.0330225, 0.113137, 0.15958, 0.240955, 0.383618, 0.628464, 1.037", \ + "0.0328138, 0.112989, 0.1596, 0.240823, 0.383417, 0.626894, 1.03696", \ + "0.0328148, 0.113136, 0.159601, 0.240824, 0.383617, 0.626895, 1.03697", \ + "0.0330225, 0.113137, 0.159602, 0.240955, 0.383618, 0.628464, 1.037", \ "0.0332077, 0.113138, 0.159699, 0.240956, 0.383619, 0.628465, 1.03701", \ "0.0339349, 0.113395, 0.159929, 0.240983, 0.38362, 0.628466, 1.03702", \ "0.036086, 0.114188, 0.160294, 0.24116, 0.383621, 0.628467, 1.03703", \ @@ -28653,32 +28752,33 @@ library (sg13g2_stdcell_slow_1p35V_125C) { } timing () { related_pin : "RESET_B"; + sdf_edges : start_edge; timing_sense : negative_unate; timing_type : preset; cell_rise (TIMING_DELAY_7x7ds1) { index_1 ("0.0186, 0.0966, 0.174, 0.3294, 0.6408, 1.263, 2.5074"); index_2 ("0.001, 0.0234, 0.039, 0.0648, 0.108, 0.18, 0.3"); values ( \ - "0.204892, 0.288947, 0.336215, 0.412656, 0.540109, 0.752063, 1.1056", \ - "0.243627, 0.327584, 0.374875, 0.451276, 0.578885, 0.790871, 1.1441", \ - "0.276884, 0.360894, 0.408163, 0.484606, 0.612113, 0.824074, 1.17746", \ - "0.329176, 0.413251, 0.46043, 0.536931, 0.664378, 0.876491, 1.22992", \ - "0.408147, 0.49242, 0.539666, 0.616125, 0.743495, 0.955549, 1.30859", \ - "0.517488, 0.602364, 0.649628, 0.725752, 0.853457, 1.06534, 1.41843", \ - "0.67019, 0.755856, 0.802837, 0.879206, 1.00644, 1.21882, 1.57219" \ + "0.204956, 0.288942, 0.336268, 0.412642, 0.540181, 0.752164, 1.10524", \ + "0.243615, 0.327614, 0.374794, 0.451278, 0.578927, 0.791015, 1.14454", \ + "0.276831, 0.360983, 0.408301, 0.484683, 0.612211, 0.824169, 1.17759", \ + "0.329155, 0.413246, 0.460502, 0.536931, 0.664385, 0.876492, 1.22992", \ + "0.40809, 0.492421, 0.539666, 0.616126, 0.743496, 0.95555, 1.3086", \ + "0.517487, 0.602364, 0.649628, 0.725754, 0.853424, 1.06534, 1.41843", \ + "0.67019, 0.755592, 0.802838, 0.879327, 1.00645, 1.21927, 1.57237" \ ); } rise_transition (TIMING_DELAY_7x7ds1) { index_1 ("0.0186, 0.0966, 0.174, 0.3294, 0.6408, 1.263, 2.5074"); index_2 ("0.001, 0.0234, 0.039, 0.0648, 0.108, 0.18, 0.3"); values ( \ - "0.0270836, 0.118073, 0.182136, 0.291441, 0.477401, 0.788422, 1.30724", \ - "0.0272121, 0.118081, 0.1822, 0.29183, 0.477471, 0.788622, 1.30733", \ - "0.02723, 0.118136, 0.182201, 0.291831, 0.477942, 0.788623, 1.30734", \ - "0.0275339, 0.118235, 0.182202, 0.291832, 0.477943, 0.788624, 1.30813", \ - "0.028209, 0.118347, 0.182231, 0.291833, 0.477944, 0.788625, 1.30814", \ - "0.029249, 0.118761, 0.182464, 0.291834, 0.477945, 0.788626, 1.30815", \ - "0.030924, 0.119417, 0.18276, 0.291835, 0.477946, 0.788627, 1.30816" \ + "0.0271845, 0.118073, 0.182142, 0.29144, 0.477398, 0.78848, 1.30724", \ + "0.0271855, 0.118102, 0.182304, 0.29183, 0.477471, 0.788546, 1.3074", \ + "0.0272125, 0.118148, 0.182305, 0.291831, 0.477546, 0.788547, 1.30741", \ + "0.0275091, 0.118223, 0.182306, 0.291832, 0.477547, 0.788548, 1.30813", \ + "0.0281564, 0.118346, 0.182307, 0.291833, 0.477548, 0.788549, 1.30814", \ + "0.029249, 0.118761, 0.182464, 0.291834, 0.477549, 0.78855, 1.30815", \ + "0.030925, 0.119415, 0.18276, 0.291835, 0.47755, 0.788551, 1.30816" \ ); } } @@ -28689,25 +28789,25 @@ library (sg13g2_stdcell_slow_1p35V_125C) { index_1 ("0.0186, 0.0966, 0.174, 0.3294, 0.6408, 1.263, 2.5074"); index_2 ("0.001, 0.0234, 0.039, 0.0648, 0.108, 0.18, 0.3"); values ( \ - "0.03991, 0.0610784, 0.0753985, 0.0988684, 0.138206, 0.203428, 0.312284", \ - "0.0397267, 0.0610282, 0.0752458, 0.0989729, 0.138278, 0.203682, 0.312299", \ - "0.0400982, 0.061196, 0.0756168, 0.0992575, 0.138327, 0.20366, 0.31323", \ + "0.0399065, 0.0610761, 0.0753905, 0.0989157, 0.138206, 0.203442, 0.312429", \ + "0.0397267, 0.0610282, 0.0752458, 0.0989729, 0.138277, 0.203685, 0.312299", \ + "0.0400982, 0.061196, 0.0756168, 0.0992045, 0.138327, 0.203661, 0.31323", \ "0.0412959, 0.0625299, 0.0768411, 0.100296, 0.139936, 0.205091, 0.315078", \ "0.0437966, 0.0649236, 0.0793428, 0.102933, 0.142042, 0.207626, 0.316203", \ - "0.0493278, 0.0704909, 0.0847988, 0.108368, 0.147873, 0.213187, 0.322026", \ - "0.061254, 0.0822723, 0.0966064, 0.120255, 0.159567, 0.225168, 0.33463" \ + "0.0493278, 0.070491, 0.0847988, 0.108368, 0.147873, 0.213187, 0.322026", \ + "0.061254, 0.0822723, 0.0966059, 0.120255, 0.159564, 0.225165, 0.33463" \ ); } fall_power (POWER_7x7ds1) { index_1 ("0.0186, 0.0966, 0.174, 0.3294, 0.6408, 1.263, 2.5074"); index_2 ("0.001, 0.0234, 0.039, 0.0648, 0.108, 0.18, 0.3"); values ( \ - "0.037319, 0.0581661, 0.0724398, 0.095842, 0.134834, 0.199714, 0.308248", \ + "0.0373144, 0.0581761, 0.0723905, 0.0958392, 0.134835, 0.199792, 0.308247", \ "0.0370198, 0.0579964, 0.0721626, 0.0955943, 0.134613, 0.199541, 0.308002", \ "0.0372123, 0.0580162, 0.072298, 0.0960083, 0.134996, 0.199968, 0.308197", \ "0.0383285, 0.0592372, 0.0734809, 0.0967509, 0.136039, 0.201058, 0.309647", \ "0.0408232, 0.061557, 0.0758456, 0.0995837, 0.138548, 0.203452, 0.312925", \ - "0.0464952, 0.0670395, 0.0812513, 0.10495, 0.144317, 0.209986, 0.318308", \ + "0.0464952, 0.0670394, 0.0812513, 0.10495, 0.144317, 0.209986, 0.318308", \ "0.0591409, 0.0792916, 0.0934945, 0.117076, 0.156364, 0.222082, 0.331352" \ ); } @@ -28718,25 +28818,25 @@ library (sg13g2_stdcell_slow_1p35V_125C) { index_1 ("0.0186, 0.0966, 0.174, 0.3294, 0.6408, 1.263, 2.5074"); index_2 ("0.001, 0.0234, 0.039, 0.0648, 0.108, 0.18, 0.3"); values ( \ - "0.03991, 0.0610784, 0.0753985, 0.0988684, 0.138206, 0.203428, 0.312284", \ - "0.0397267, 0.0610282, 0.0752458, 0.0989729, 0.138278, 0.203682, 0.312299", \ - "0.0400982, 0.061196, 0.0756168, 0.0992575, 0.138327, 0.20366, 0.31323", \ + "0.0399065, 0.0610761, 0.0753905, 0.0989157, 0.138206, 0.203442, 0.312429", \ + "0.0397267, 0.0610282, 0.0752458, 0.0989729, 0.138277, 0.203685, 0.312299", \ + "0.0400982, 0.061196, 0.0756168, 0.0992045, 0.138327, 0.203661, 0.31323", \ "0.0412959, 0.0625299, 0.0768411, 0.100296, 0.139936, 0.205091, 0.315078", \ "0.0437966, 0.0649236, 0.0793428, 0.102933, 0.142042, 0.207626, 0.316203", \ - "0.0493278, 0.0704909, 0.0847988, 0.108368, 0.147873, 0.213187, 0.322026", \ - "0.061254, 0.0822723, 0.0966064, 0.120255, 0.159567, 0.225168, 0.33463" \ + "0.0493278, 0.070491, 0.0847988, 0.108368, 0.147873, 0.213187, 0.322026", \ + "0.061254, 0.0822723, 0.0966059, 0.120255, 0.159564, 0.225165, 0.33463" \ ); } fall_power (POWER_7x7ds1) { index_1 ("0.0186, 0.0966, 0.174, 0.3294, 0.6408, 1.263, 2.5074"); index_2 ("0.001, 0.0234, 0.039, 0.0648, 0.108, 0.18, 0.3"); values ( \ - "0.037319, 0.0581661, 0.0724398, 0.095842, 0.134834, 0.199714, 0.308248", \ + "0.0373144, 0.0581761, 0.0723905, 0.0958392, 0.134835, 0.199792, 0.308247", \ "0.0370198, 0.0579964, 0.0721626, 0.0955943, 0.134613, 0.199541, 0.308002", \ "0.0372123, 0.0580162, 0.072298, 0.0960083, 0.134996, 0.199968, 0.308197", \ "0.0383285, 0.0592372, 0.0734809, 0.0967509, 0.136039, 0.201058, 0.309647", \ "0.0408232, 0.061557, 0.0758456, 0.0995837, 0.138548, 0.203452, 0.312925", \ - "0.0464952, 0.0670395, 0.0812513, 0.10495, 0.144317, 0.209986, 0.318308", \ + "0.0464952, 0.0670394, 0.0812513, 0.10495, 0.144317, 0.209986, 0.318308", \ "0.0591409, 0.0792916, 0.0934945, 0.117076, 0.156364, 0.222082, 0.331352" \ ); } @@ -28747,13 +28847,13 @@ library (sg13g2_stdcell_slow_1p35V_125C) { index_1 ("0.0186, 0.0966, 0.174, 0.3294, 0.6408, 1.263, 2.5074"); index_2 ("0.001, 0.0234, 0.039, 0.0648, 0.108, 0.18, 0.3"); values ( \ - "0.0401592, 0.0617358, 0.0762852, 0.100045, 0.139245, 0.203761, 0.310795", \ - "0.0396968, 0.0612547, 0.0758583, 0.0998407, 0.13929, 0.204206, 0.311564", \ - "0.0397857, 0.0613543, 0.07609, 0.100248, 0.139826, 0.204885, 0.312637", \ - "0.0405733, 0.0620594, 0.0766802, 0.100837, 0.14065, 0.206611, 0.314972", \ - "0.0430894, 0.0645202, 0.0791492, 0.103297, 0.143401, 0.210147, 0.319144", \ - "0.0487582, 0.0701259, 0.0848476, 0.10895, 0.149262, 0.215741, 0.326895", \ - "0.0609915, 0.0817334, 0.0962191, 0.12036, 0.160764, 0.227795, 0.3395" \ + "0.0401751, 0.0617205, 0.0762961, 0.100056, 0.139211, 0.203783, 0.310819", \ + "0.0396928, 0.0612497, 0.0758908, 0.0998443, 0.139279, 0.204202, 0.311717", \ + "0.0397824, 0.0614006, 0.0760797, 0.100139, 0.139664, 0.204903, 0.312677", \ + "0.0405815, 0.0620625, 0.0766825, 0.100847, 0.140707, 0.206614, 0.314976", \ + "0.0430765, 0.0645163, 0.0791536, 0.103292, 0.143426, 0.210174, 0.318919", \ + "0.0487618, 0.070129, 0.0848505, 0.108947, 0.149264, 0.21575, 0.326898", \ + "0.060995, 0.0817419, 0.0962275, 0.120409, 0.160785, 0.227847, 0.339527" \ ); } fall_power (scalar) { @@ -28769,9 +28869,9 @@ library (sg13g2_stdcell_slow_1p35V_125C) { max_transition : 2.5074; capacitance : 0.00290365; rise_capacitance : 0.00295155; - rise_capacitance_range (0.00295155, 0.00295155); + rise_capacitance_range (0.00265742, 0.0032134); fall_capacitance : 0.00284206; - fall_capacitance_range (0.00284206, 0.00284206); + fall_capacitance_range (0.0026165, 0.00304803); timing () { related_pin : "CLK"; timing_type : min_pulse_width; @@ -28787,7 +28887,7 @@ library (sg13g2_stdcell_slow_1p35V_125C) { rise_power (passive_POWER_7x1ds1) { index_1 ("0.0186, 0.0966, 0.174, 0.3294, 0.6408, 1.263, 2.5074"); values ( \ - "0.0138247, 0.0136055, 0.0138384, 0.0148369, 0.0172739, 0.0227633, 0.0343659" \ + "0.0138096, 0.0136055, 0.0138384, 0.0148369, 0.0172739, 0.0227633, 0.0343659" \ ); } fall_power (passive_POWER_7x1ds1) { @@ -28821,7 +28921,7 @@ library (sg13g2_stdcell_slow_1p35V_125C) { fall_power (passive_POWER_7x1ds1) { index_1 ("0.0186, 0.0966, 0.174, 0.3294, 0.6408, 1.263, 2.5074"); values ( \ - "0.0243011, 0.0241463, 0.0246006, 0.02556, 0.0284385, 0.0340773, 0.0465118" \ + "0.0242966, 0.0241322, 0.0246006, 0.02556, 0.0284385, 0.0340773, 0.0465118" \ ); } } @@ -28830,7 +28930,7 @@ library (sg13g2_stdcell_slow_1p35V_125C) { rise_power (passive_POWER_7x1ds1) { index_1 ("0.0186, 0.0966, 0.174, 0.3294, 0.6408, 1.263, 2.5074"); values ( \ - "0.0135354, 0.0133114, 0.0135393, 0.0145409, 0.016949, 0.0225244, 0.0340891" \ + "0.0135294, 0.0133114, 0.0135395, 0.0145409, 0.016949, 0.0225239, 0.0340891" \ ); } fall_power (passive_POWER_7x1ds1) { @@ -28845,13 +28945,13 @@ library (sg13g2_stdcell_slow_1p35V_125C) { rise_power (passive_POWER_7x1ds1) { index_1 ("0.0186, 0.0966, 0.174, 0.3294, 0.6408, 1.263, 2.5074"); values ( \ - "0.0138284, 0.0136055, 0.0138389, 0.0148348, 0.0172719, 0.0227635, 0.0343661" \ + "0.013824, 0.0136055, 0.0138389, 0.0148348, 0.0172719, 0.0227635, 0.0343661" \ ); } fall_power (passive_POWER_7x1ds1) { index_1 ("0.0186, 0.0966, 0.174, 0.3294, 0.6408, 1.263, 2.5074"); values ( \ - "0.0133665, 0.0131028, 0.013537, 0.0144282, 0.0170889, 0.0225318, 0.0345949" \ + "0.0133665, 0.0131148, 0.013537, 0.0144282, 0.0170889, 0.0225318, 0.0345949" \ ); } } @@ -28860,13 +28960,13 @@ library (sg13g2_stdcell_slow_1p35V_125C) { rise_power (passive_POWER_7x1ds1) { index_1 ("0.0186, 0.0966, 0.174, 0.3294, 0.6408, 1.263, 2.5074"); values ( \ - "0.000410744, 0.000204865, 0.000444002, 0.00147093, 0.0038247, 0.00933092, 0.020915" \ + "0.000410748, 0.000204868, 0.000444005, 0.00147093, 0.0038247, 0.00933092, 0.020915" \ ); } fall_power (passive_POWER_7x1ds1) { index_1 ("0.0186, 0.0966, 0.174, 0.3294, 0.6408, 1.263, 2.5074"); values ( \ - "0.00135247, 0.00110294, 0.00150439, 0.00243552, 0.00510107, 0.01052, 0.0225856" \ + "0.00135248, 0.00110295, 0.0015044, 0.00243552, 0.00510107, 0.01052, 0.0225856" \ ); } } @@ -28875,13 +28975,13 @@ library (sg13g2_stdcell_slow_1p35V_125C) { rise_power (passive_POWER_7x1ds1) { index_1 ("0.0186, 0.0966, 0.174, 0.3294, 0.6408, 1.263, 2.5074"); values ( \ - "0.0136374, 0.0134079, 0.0136383, 0.0146416, 0.0170463, 0.022623, 0.0341883" \ + "0.0136229, 0.0134079, 0.0136383, 0.0146416, 0.0170463, 0.0226228, 0.0341883" \ ); } fall_power (passive_POWER_7x1ds1) { index_1 ("0.0186, 0.0966, 0.174, 0.3294, 0.6408, 1.263, 2.5074"); values ( \ - "0.0133131, 0.0130637, 0.0134699, 0.0144118, 0.0170509, 0.0224876, 0.0345662" \ + "0.0133132, 0.0130637, 0.0134699, 0.0144118, 0.0170509, 0.0224876, 0.0345662" \ ); } } @@ -28889,13 +28989,13 @@ library (sg13g2_stdcell_slow_1p35V_125C) { rise_power (passive_POWER_7x1ds1) { index_1 ("0.0186, 0.0966, 0.174, 0.3294, 0.6408, 1.263, 2.5074"); values ( \ - "0.0135354, 0.0133114, 0.0135393, 0.0145409, 0.016949, 0.0225244, 0.0340891" \ + "0.0135294, 0.0133114, 0.0135395, 0.0145409, 0.016949, 0.0225239, 0.0340891" \ ); } fall_power (passive_POWER_7x1ds1) { index_1 ("0.0186, 0.0966, 0.174, 0.3294, 0.6408, 1.263, 2.5074"); values ( \ - "0.0133619, 0.0131156, 0.0135368, 0.014428, 0.0170886, 0.0225316, 0.0345947" \ + "0.0133665, 0.0131148, 0.013537, 0.0144282, 0.0170889, 0.0225318, 0.0345949" \ ); } } @@ -28906,11 +29006,12 @@ library (sg13g2_stdcell_slow_1p35V_125C) { max_transition : 2.5074; capacitance : 0.00273021; rise_capacitance : 0.00278062; - rise_capacitance_range (0.00278062, 0.00278062); + rise_capacitance_range (0.00239108, 0.00311394); fall_capacitance : 0.00267981; - fall_capacitance_range (0.00267981, 0.00267981); + fall_capacitance_range (0.00236305, 0.00286573); timing () { related_pin : "CLK"; + sdf_edges : both_edges; timing_type : hold_rising; rise_constraint (CONSTRAINT_4x4) { index_1 ("0.0186, 0.51636, 1.263, 2.5074"); @@ -28935,6 +29036,7 @@ library (sg13g2_stdcell_slow_1p35V_125C) { } timing () { related_pin : "CLK"; + sdf_edges : both_edges; timing_type : setup_rising; rise_constraint (CONSTRAINT_4x4) { index_1 ("0.0186, 0.51636, 1.263, 2.5074"); @@ -28962,7 +29064,7 @@ library (sg13g2_stdcell_slow_1p35V_125C) { rise_power (passive_POWER_7x1ds1) { index_1 ("0.0186, 0.0966, 0.174, 0.3294, 0.6408, 1.263, 2.5074"); values ( \ - "0.0265618, 0.0263294, 0.0264623, 0.0271166, 0.0290189, 0.0332197, 0.0426063" \ + "0.0265683, 0.0263294, 0.0264623, 0.0271166, 0.0290189, 0.0332197, 0.0426063" \ ); } fall_power (passive_POWER_7x1ds1) { @@ -28976,7 +29078,7 @@ library (sg13g2_stdcell_slow_1p35V_125C) { rise_power (passive_POWER_7x1ds1) { index_1 ("0.0186, 0.0966, 0.174, 0.3294, 0.6408, 1.263, 2.5074"); values ( \ - "0.0265618, 0.0263294, 0.0264623, 0.0271166, 0.0290189, 0.0332197, 0.0426063" \ + "0.0265683, 0.0263294, 0.0264623, 0.0271166, 0.0290189, 0.0332197, 0.0426063" \ ); } fall_power (passive_POWER_7x1ds1) { @@ -28990,13 +29092,14 @@ library (sg13g2_stdcell_slow_1p35V_125C) { pin (RESET_B) { direction : input; max_transition : 2.5074; - capacitance : 0.00507982; - rise_capacitance : 0.00507982; - rise_capacitance_range (0.00507982, 0.00507982); - fall_capacitance : 0.00507982; - fall_capacitance_range (0.00507982, 0.00507982); + capacitance : 0.00508023; + rise_capacitance : 0.00508023; + rise_capacitance_range (0.00508023, 0.00508023); + fall_capacitance : 0.00508023; + fall_capacitance_range (0.00470956, 0.00523655); timing () { related_pin : "CLK"; + sdf_edges : both_edges; timing_type : recovery_rising; rise_constraint (CONSTRAINT_4x4) { index_1 ("0.0186, 0.51636, 1.263, 2.5074"); @@ -29011,6 +29114,7 @@ library (sg13g2_stdcell_slow_1p35V_125C) { } timing () { related_pin : "CLK"; + sdf_edges : both_edges; timing_type : removal_rising; rise_constraint (CONSTRAINT_4x4) { index_1 ("0.0186, 0.51636, 1.263, 2.5074"); @@ -29040,11 +29144,12 @@ library (sg13g2_stdcell_slow_1p35V_125C) { max_transition : 2.5074; capacitance : 0.0028504; rise_capacitance : 0.00288431; - rise_capacitance_range (0.00288431, 0.00288431); + rise_capacitance_range (0.0024983, 0.00321559); fall_capacitance : 0.00278256; - fall_capacitance_range (0.00278256, 0.00278256); + fall_capacitance_range (0.00246382, 0.00296881); timing () { related_pin : "CLK"; + sdf_edges : both_edges; timing_type : hold_rising; rise_constraint (CONSTRAINT_4x4) { index_1 ("0.0186, 0.51636, 1.263, 2.5074"); @@ -29062,13 +29167,14 @@ library (sg13g2_stdcell_slow_1p35V_125C) { values ( \ "-0.141821, -0.0551547, -0.0067163, 0.0450441", \ "-0.259319, -0.173159, -0.127531, -0.0736253", \ - "-0.36362, -0.27632, -0.229361, -0.173856", \ + "-0.361048, -0.27632, -0.229361, -0.173856", \ "-0.474084, -0.390956, -0.340285, -0.286299" \ ); } } timing () { related_pin : "CLK"; + sdf_edges : both_edges; timing_type : setup_rising; rise_constraint (CONSTRAINT_4x4) { index_1 ("0.0186, 0.51636, 1.263, 2.5074"); @@ -29096,7 +29202,7 @@ library (sg13g2_stdcell_slow_1p35V_125C) { rise_power (passive_POWER_7x1ds1) { index_1 ("0.0186, 0.0966, 0.174, 0.3294, 0.6408, 1.263, 2.5074"); values ( \ - "0.0267655, 0.0265158, 0.0266741, 0.0273101, 0.029222, 0.0333905, 0.0427955" \ + "0.0267654, 0.0265158, 0.0266741, 0.0273101, 0.029222, 0.0333905, 0.0427955" \ ); } fall_power (passive_POWER_7x1ds1) { @@ -29110,7 +29216,7 @@ library (sg13g2_stdcell_slow_1p35V_125C) { rise_power (passive_POWER_7x1ds1) { index_1 ("0.0186, 0.0966, 0.174, 0.3294, 0.6408, 1.263, 2.5074"); values ( \ - "0.0267655, 0.0265158, 0.0266741, 0.0273101, 0.029222, 0.0333905, 0.0427955" \ + "0.0267654, 0.0265158, 0.0266741, 0.0273101, 0.029222, 0.0333905, 0.0427955" \ ); } fall_power (passive_POWER_7x1ds1) { @@ -29127,11 +29233,12 @@ library (sg13g2_stdcell_slow_1p35V_125C) { max_transition : 2.5074; capacitance : 0.00465483; rise_capacitance : 0.00476862; - rise_capacitance_range (0.00476862, 0.00476862); + rise_capacitance_range (0.00429818, 0.0051453); fall_capacitance : 0.00454105; - fall_capacitance_range (0.00454105, 0.00454105); + fall_capacitance_range (0.00433692, 0.0050251); timing () { related_pin : "CLK"; + sdf_edges : both_edges; timing_type : hold_rising; rise_constraint (CONSTRAINT_4x4) { index_1 ("0.0186, 0.51636, 1.263, 2.5074"); @@ -29156,6 +29263,7 @@ library (sg13g2_stdcell_slow_1p35V_125C) { } timing () { related_pin : "CLK"; + sdf_edges : both_edges; timing_type : setup_rising; rise_constraint (CONSTRAINT_4x4) { index_1 ("0.0186, 0.51636, 1.263, 2.5074"); @@ -29189,7 +29297,7 @@ library (sg13g2_stdcell_slow_1p35V_125C) { fall_power (passive_POWER_7x1ds1) { index_1 ("0.0186, 0.0966, 0.174, 0.3294, 0.6408, 1.263, 2.5074"); values ( \ - "0.0327793, 0.032657, 0.0328195, 0.0335135, 0.0352408, 0.0390729, 0.0473013" \ + "0.0327792, 0.0326611, 0.0328195, 0.0335135, 0.0352408, 0.0390729, 0.0473013" \ ); } } @@ -29204,7 +29312,7 @@ library (sg13g2_stdcell_slow_1p35V_125C) { fall_power (passive_POWER_7x1ds1) { index_1 ("0.0186, 0.0966, 0.174, 0.3294, 0.6408, 1.263, 2.5074"); values ( \ - "0.0214884, 0.0430131, 0.0448433, 0.0463248, 0.049748, 0.0577416, 0.0748223" \ + "0.0214879, 0.0430131, 0.0448433, 0.0463248, 0.049748, 0.0577416, 0.0748223" \ ); } } @@ -29218,15 +29326,15 @@ library (sg13g2_stdcell_slow_1p35V_125C) { fall_power (passive_POWER_7x1ds1) { index_1 ("0.0186, 0.0966, 0.174, 0.3294, 0.6408, 1.263, 2.5074"); values ( \ - "0.0214884, 0.0430131, 0.0448433, 0.0463248, 0.049748, 0.0577416, 0.0748223" \ + "0.0214879, 0.0430131, 0.0448433, 0.0463248, 0.049748, 0.0577416, 0.0748223" \ ); } } } ff (IQ,IQN) { - clear : "RESET_B'"; + clear : "!RESET_B"; clocked_on : "CLK"; - next_state : "(SCE*SCD)+(SCE'*D)"; + next_state : "(SCE*SCD)+(!SCE*D)"; } test_cell () { pin (Q) { @@ -29257,7 +29365,7 @@ library (sg13g2_stdcell_slow_1p35V_125C) { signal_type : test_scan_enable; } ff (IQ,IQN) { - clear : "RESET_B'"; + clear : "!RESET_B"; clocked_on : "CLK"; next_state : "D"; } @@ -29324,7 +29432,7 @@ library (sg13g2_stdcell_slow_1p35V_125C) { when : "CLK&!D&RESET_B&!SCD&SCE&!Q&Q_N"; } leakage_power () { - value : 7101.83; + value : 7101.82; when : "CLK&!D&RESET_B&!SCD&SCE&Q&!Q_N"; } leakage_power () { @@ -29343,6 +29451,7 @@ library (sg13g2_stdcell_slow_1p35V_125C) { timing () { related_pin : "CLK"; sdf_cond : "SCE == 1'b1"; + sdf_edges : start_edge; timing_sense : non_unate; timing_type : rising_edge; when : "SCE"; @@ -29350,7 +29459,7 @@ library (sg13g2_stdcell_slow_1p35V_125C) { index_1 ("0.0186, 0.0966, 0.174, 0.3294, 0.6408, 1.263, 2.5074"); index_2 ("0.001, 0.0468, 0.078, 0.1296, 0.216, 0.36, 0.6"); values ( \ - "0.23927, 0.298327, 0.343287, 0.41899, 0.5466, 0.759577, 1.11526", \ + "0.239248, 0.298327, 0.343297, 0.41899, 0.546599, 0.759583, 1.11526", \ "0.271794, 0.33075, 0.375885, 0.451557, 0.579608, 0.792233, 1.14776", \ "0.293306, 0.352477, 0.397494, 0.473328, 0.600895, 0.813936, 1.16912", \ "0.324889, 0.384028, 0.429024, 0.504643, 0.632203, 0.845468, 1.20071", \ @@ -29363,9 +29472,9 @@ library (sg13g2_stdcell_slow_1p35V_125C) { index_1 ("0.0186, 0.0966, 0.174, 0.3294, 0.6408, 1.263, 2.5074"); index_2 ("0.001, 0.0468, 0.078, 0.1296, 0.216, 0.36, 0.6"); values ( \ - "0.0244912, 0.112916, 0.17964, 0.291393, 0.479079, 0.792007, 1.31371", \ - "0.024522, 0.112917, 0.179641, 0.291394, 0.479773, 0.792008, 1.31372", \ - "0.024523, 0.112918, 0.17965, 0.291428, 0.479774, 0.792543, 1.31387", \ + "0.0245072, 0.112916, 0.179638, 0.291393, 0.479079, 0.792202, 1.31371", \ + "0.0245219, 0.112917, 0.179639, 0.291394, 0.479773, 0.792203, 1.31372", \ + "0.0245229, 0.112918, 0.17965, 0.291428, 0.479774, 0.792543, 1.31387", \ "0.0245535, 0.112929, 0.179651, 0.291429, 0.479775, 0.792544, 1.31442", \ "0.0245985, 0.11293, 0.179652, 0.29143, 0.479776, 0.792545, 1.31443", \ "0.02471, 0.112966, 0.179674, 0.291431, 0.479777, 0.792546, 1.31444", \ @@ -29376,11 +29485,11 @@ library (sg13g2_stdcell_slow_1p35V_125C) { index_1 ("0.0186, 0.0966, 0.174, 0.3294, 0.6408, 1.263, 2.5074"); index_2 ("0.001, 0.0468, 0.078, 0.1296, 0.216, 0.36, 0.6"); values ( \ - "0.208109, 0.267982, 0.307794, 0.373655, 0.483991, 0.668163, 0.975223", \ + "0.207933, 0.268, 0.307793, 0.373584, 0.484179, 0.668147, 0.975236", \ "0.240408, 0.300454, 0.340306, 0.406164, 0.516575, 0.701039, 1.00775", \ "0.261615, 0.321694, 0.361466, 0.427326, 0.537829, 0.721997, 1.02916", \ - "0.292347, 0.352334, 0.392305, 0.458139, 0.568552, 0.752509, 1.05949", \ - "0.331212, 0.39127, 0.431008, 0.496872, 0.607298, 0.791429, 1.09831", \ + "0.292347, 0.352334, 0.392157, 0.458007, 0.568404, 0.752663, 1.05961", \ + "0.331268, 0.39122, 0.431063, 0.496872, 0.607355, 0.791429, 1.09831", \ "0.383518, 0.443564, 0.483312, 0.54918, 0.659622, 0.843711, 1.15064", \ "0.449129, 0.509013, 0.548717, 0.614732, 0.725029, 0.909228, 1.21631" \ ); @@ -29389,25 +29498,26 @@ library (sg13g2_stdcell_slow_1p35V_125C) { index_1 ("0.0186, 0.0966, 0.174, 0.3294, 0.6408, 1.263, 2.5074"); index_2 ("0.001, 0.0468, 0.078, 0.1296, 0.216, 0.36, 0.6"); values ( \ - "0.0204673, 0.0926557, 0.144631, 0.232211, 0.379767, 0.626154, 1.03668", \ - "0.0204972, 0.0926567, 0.144745, 0.232255, 0.380072, 0.626839, 1.03684", \ - "0.0204982, 0.0926577, 0.144746, 0.232375, 0.380073, 0.62684, 1.03685", \ - "0.0204992, 0.0926933, 0.144747, 0.232376, 0.380074, 0.626841, 1.03686", \ - "0.0205002, 0.0926943, 0.144779, 0.232377, 0.380075, 0.626842, 1.03687", \ - "0.0205012, 0.0926953, 0.14478, 0.232378, 0.380076, 0.626843, 1.03692", \ - "0.0205022, 0.0926963, 0.144781, 0.232379, 0.380077, 0.626844, 1.03693" \ + "0.0205064, 0.0926872, 0.144631, 0.232211, 0.379767, 0.626154, 1.03668", \ + "0.0205074, 0.0926882, 0.144745, 0.232255, 0.380072, 0.626839, 1.03684", \ + "0.0205084, 0.0926892, 0.144746, 0.232375, 0.380073, 0.62684, 1.03685", \ + "0.0205094, 0.0926933, 0.144747, 0.232376, 0.380074, 0.626841, 1.03736", \ + "0.0205104, 0.0926943, 0.14478, 0.232377, 0.380075, 0.626842, 1.03737", \ + "0.0205114, 0.0926953, 0.144781, 0.232378, 0.380076, 0.626843, 1.03738", \ + "0.0205124, 0.0926963, 0.144782, 0.232379, 0.380077, 0.626844, 1.03739" \ ); } } timing () { related_pin : "CLK"; + sdf_edges : start_edge; timing_sense : non_unate; timing_type : rising_edge; cell_rise (TIMING_DELAY_7x7ds1) { index_1 ("0.0186, 0.0966, 0.174, 0.3294, 0.6408, 1.263, 2.5074"); index_2 ("0.001, 0.0468, 0.078, 0.1296, 0.216, 0.36, 0.6"); values ( \ - "0.23927, 0.298327, 0.343287, 0.41899, 0.5466, 0.759577, 1.11526", \ + "0.239248, 0.298327, 0.343297, 0.41899, 0.546599, 0.759583, 1.11526", \ "0.271794, 0.33075, 0.375885, 0.451557, 0.579608, 0.792233, 1.14776", \ "0.293306, 0.352477, 0.397494, 0.473328, 0.600895, 0.813936, 1.16912", \ "0.324889, 0.384028, 0.429024, 0.504643, 0.632203, 0.845468, 1.20071", \ @@ -29420,9 +29530,9 @@ library (sg13g2_stdcell_slow_1p35V_125C) { index_1 ("0.0186, 0.0966, 0.174, 0.3294, 0.6408, 1.263, 2.5074"); index_2 ("0.001, 0.0468, 0.078, 0.1296, 0.216, 0.36, 0.6"); values ( \ - "0.0244912, 0.112916, 0.17964, 0.291393, 0.479079, 0.792007, 1.31371", \ - "0.024522, 0.112917, 0.179641, 0.291394, 0.479773, 0.792008, 1.31372", \ - "0.024523, 0.112918, 0.17965, 0.291428, 0.479774, 0.792543, 1.31387", \ + "0.0245072, 0.112916, 0.179638, 0.291393, 0.479079, 0.792202, 1.31371", \ + "0.0245219, 0.112917, 0.179639, 0.291394, 0.479773, 0.792203, 1.31372", \ + "0.0245229, 0.112918, 0.17965, 0.291428, 0.479774, 0.792543, 1.31387", \ "0.0245535, 0.112929, 0.179651, 0.291429, 0.479775, 0.792544, 1.31442", \ "0.0245985, 0.11293, 0.179652, 0.29143, 0.479776, 0.792545, 1.31443", \ "0.02471, 0.112966, 0.179674, 0.291431, 0.479777, 0.792546, 1.31444", \ @@ -29433,11 +29543,11 @@ library (sg13g2_stdcell_slow_1p35V_125C) { index_1 ("0.0186, 0.0966, 0.174, 0.3294, 0.6408, 1.263, 2.5074"); index_2 ("0.001, 0.0468, 0.078, 0.1296, 0.216, 0.36, 0.6"); values ( \ - "0.208109, 0.267982, 0.307794, 0.373655, 0.483991, 0.668163, 0.975223", \ + "0.207933, 0.268, 0.307793, 0.373584, 0.484179, 0.668147, 0.975236", \ "0.240408, 0.300454, 0.340306, 0.406164, 0.516575, 0.701039, 1.00775", \ "0.261615, 0.321694, 0.361466, 0.427326, 0.537829, 0.721997, 1.02916", \ - "0.292347, 0.352334, 0.392305, 0.458139, 0.568552, 0.752509, 1.05949", \ - "0.331212, 0.39127, 0.431008, 0.496872, 0.607298, 0.791429, 1.09831", \ + "0.292347, 0.352334, 0.392157, 0.458007, 0.568404, 0.752663, 1.05961", \ + "0.331268, 0.39122, 0.431063, 0.496872, 0.607355, 0.791429, 1.09831", \ "0.383518, 0.443564, 0.483312, 0.54918, 0.659622, 0.843711, 1.15064", \ "0.449129, 0.509013, 0.548717, 0.614732, 0.725029, 0.909228, 1.21631" \ ); @@ -29446,30 +29556,31 @@ library (sg13g2_stdcell_slow_1p35V_125C) { index_1 ("0.0186, 0.0966, 0.174, 0.3294, 0.6408, 1.263, 2.5074"); index_2 ("0.001, 0.0468, 0.078, 0.1296, 0.216, 0.36, 0.6"); values ( \ - "0.0204673, 0.0926557, 0.144631, 0.232211, 0.379767, 0.626154, 1.03668", \ - "0.0204972, 0.0926567, 0.144745, 0.232255, 0.380072, 0.626839, 1.03684", \ - "0.0204982, 0.0926577, 0.144746, 0.232375, 0.380073, 0.62684, 1.03685", \ - "0.0204992, 0.0926933, 0.144747, 0.232376, 0.380074, 0.626841, 1.03686", \ - "0.0205002, 0.0926943, 0.144779, 0.232377, 0.380075, 0.626842, 1.03687", \ - "0.0205012, 0.0926953, 0.14478, 0.232378, 0.380076, 0.626843, 1.03692", \ - "0.0205022, 0.0926963, 0.144781, 0.232379, 0.380077, 0.626844, 1.03693" \ + "0.0205064, 0.0926872, 0.144631, 0.232211, 0.379767, 0.626154, 1.03668", \ + "0.0205074, 0.0926882, 0.144745, 0.232255, 0.380072, 0.626839, 1.03684", \ + "0.0205084, 0.0926892, 0.144746, 0.232375, 0.380073, 0.62684, 1.03685", \ + "0.0205094, 0.0926933, 0.144747, 0.232376, 0.380074, 0.626841, 1.03736", \ + "0.0205104, 0.0926943, 0.14478, 0.232377, 0.380075, 0.626842, 1.03737", \ + "0.0205114, 0.0926953, 0.144781, 0.232378, 0.380076, 0.626843, 1.03738", \ + "0.0205124, 0.0926963, 0.144782, 0.232379, 0.380077, 0.626844, 1.03739" \ ); } } timing () { related_pin : "RESET_B"; + sdf_edges : start_edge; timing_sense : positive_unate; timing_type : clear; cell_fall (TIMING_DELAY_7x7ds1) { index_1 ("0.0186, 0.0966, 0.174, 0.3294, 0.6408, 1.263, 2.5074"); index_2 ("0.001, 0.0468, 0.078, 0.1296, 0.216, 0.36, 0.6"); values ( \ - "0.281109, 0.341135, 0.380836, 0.44617, 0.554291, 0.732844, 1.02854", \ + "0.281108, 0.34113, 0.380837, 0.446118, 0.554292, 0.732844, 1.02854", \ "0.319654, 0.379694, 0.419486, 0.485189, 0.594086, 0.773647, 1.07032", \ "0.353019, 0.413206, 0.452897, 0.518783, 0.628235, 0.808611, 1.10629", \ "0.405715, 0.465567, 0.50541, 0.571398, 0.681384, 0.862958, 1.16223", \ - "0.484999, 0.544616, 0.584514, 0.650418, 0.760742, 0.943628, 1.2453", \ - "0.595336, 0.655047, 0.694921, 0.761154, 0.87158, 1.05546, 1.3601", \ + "0.485015, 0.544616, 0.584514, 0.650418, 0.760742, 0.943628, 1.2453", \ + "0.595336, 0.655047, 0.695109, 0.760916, 0.871567, 1.05547, 1.3601", \ "0.750193, 0.809306, 0.849456, 0.915294, 1.02506, 1.20957, 1.51676" \ ); } @@ -29477,11 +29588,11 @@ library (sg13g2_stdcell_slow_1p35V_125C) { index_1 ("0.0186, 0.0966, 0.174, 0.3294, 0.6408, 1.263, 2.5074"); index_2 ("0.001, 0.0468, 0.078, 0.1296, 0.216, 0.36, 0.6"); values ( \ - "0.020134, 0.0926413, 0.144691, 0.232316, 0.379999, 0.626428, 1.03728", \ - "0.0201377, 0.092644, 0.144692, 0.232317, 0.38, 0.62644, 1.03729", \ + "0.0201342, 0.0926279, 0.144691, 0.232317, 0.379999, 0.626428, 1.03728", \ + "0.0201377, 0.092644, 0.144692, 0.232318, 0.38, 0.62644, 1.03729", \ "0.0201387, 0.092645, 0.144693, 0.232326, 0.382245, 0.626441, 1.0373", \ "0.0201495, 0.092646, 0.144694, 0.232327, 0.382246, 0.626442, 1.03926", \ - "0.0202018, 0.092652, 0.144695, 0.232328, 0.382247, 0.626443, 1.03927", \ + "0.020198, 0.092652, 0.144695, 0.232328, 0.382247, 0.626443, 1.03927", \ "0.020294, 0.092669, 0.144696, 0.232329, 0.382248, 0.626444, 1.03928", \ "0.020451, 0.092744, 0.14473, 0.23233, 0.382249, 0.626468, 1.03929" \ ); @@ -29494,26 +29605,26 @@ library (sg13g2_stdcell_slow_1p35V_125C) { index_1 ("0.0186, 0.0966, 0.174, 0.3294, 0.6408, 1.263, 2.5074"); index_2 ("0.001, 0.0468, 0.078, 0.1296, 0.216, 0.36, 0.6"); values ( \ - "0.0484205, 0.0898167, 0.118446, 0.165456, 0.244077, 0.374753, 0.592774", \ + "0.0484168, 0.0898165, 0.118434, 0.165456, 0.244077, 0.374884, 0.592774", \ "0.0481888, 0.0895568, 0.118494, 0.165252, 0.244314, 0.37446, 0.592496", \ "0.0484239, 0.0897393, 0.118529, 0.165551, 0.244315, 0.375312, 0.592789", \ - "0.0494499, 0.0907528, 0.119224, 0.166443, 0.245778, 0.376324, 0.594205", \ + "0.0494499, 0.0907528, 0.119224, 0.166443, 0.245777, 0.376324, 0.594205", \ "0.0519535, 0.0930104, 0.121876, 0.169136, 0.247314, 0.378809, 0.595936", \ "0.0578285, 0.0984955, 0.127338, 0.17447, 0.253636, 0.384552, 0.601572", \ - "0.0705502, 0.11051, 0.139186, 0.186435, 0.265431, 0.396707, 0.615141" \ + "0.0705504, 0.11051, 0.139186, 0.186435, 0.265431, 0.396707, 0.615141" \ ); } fall_power (POWER_7x7ds1) { index_1 ("0.0186, 0.0966, 0.174, 0.3294, 0.6408, 1.263, 2.5074"); index_2 ("0.001, 0.0468, 0.078, 0.1296, 0.216, 0.36, 0.6"); values ( \ - "0.0480298, 0.0904484, 0.118944, 0.165786, 0.243865, 0.37375, 0.590428", \ - "0.0478921, 0.09066, 0.118966, 0.165743, 0.24392, 0.376997, 0.590476", \ - "0.0481875, 0.0906882, 0.119288, 0.166994, 0.24444, 0.374165, 0.591307", \ - "0.0494437, 0.0921389, 0.120723, 0.167347, 0.245941, 0.375673, 0.591919", \ - "0.0519353, 0.094456, 0.123136, 0.170552, 0.248072, 0.37784, 0.597361", \ - "0.0575829, 0.100162, 0.128507, 0.175998, 0.254788, 0.385895, 0.602408", \ - "0.0696084, 0.111674, 0.140144, 0.187457, 0.266057, 0.397228, 0.61615" \ + "0.0480233, 0.0904383, 0.118943, 0.165778, 0.243956, 0.373748, 0.590418", \ + "0.0478921, 0.09066, 0.118966, 0.165743, 0.243926, 0.37403, 0.590476", \ + "0.0481875, 0.0906882, 0.119288, 0.166994, 0.24444, 0.374165, 0.590865", \ + "0.0494437, 0.0921388, 0.12078, 0.167367, 0.246051, 0.376931, 0.592099", \ + "0.0519332, 0.0944945, 0.123153, 0.170553, 0.248653, 0.37784, 0.597361", \ + "0.057583, 0.100162, 0.128507, 0.175998, 0.254788, 0.385895, 0.602408", \ + "0.0696084, 0.111674, 0.140143, 0.187457, 0.265834, 0.397228, 0.61615" \ ); } } @@ -29523,26 +29634,26 @@ library (sg13g2_stdcell_slow_1p35V_125C) { index_1 ("0.0186, 0.0966, 0.174, 0.3294, 0.6408, 1.263, 2.5074"); index_2 ("0.001, 0.0468, 0.078, 0.1296, 0.216, 0.36, 0.6"); values ( \ - "0.0484205, 0.0898167, 0.118446, 0.165456, 0.244077, 0.374753, 0.592774", \ + "0.0484168, 0.0898165, 0.118434, 0.165456, 0.244077, 0.374884, 0.592774", \ "0.0481888, 0.0895568, 0.118494, 0.165252, 0.244314, 0.37446, 0.592496", \ "0.0484239, 0.0897393, 0.118529, 0.165551, 0.244315, 0.375312, 0.592789", \ - "0.0494499, 0.0907528, 0.119224, 0.166443, 0.245778, 0.376324, 0.594205", \ + "0.0494499, 0.0907528, 0.119224, 0.166443, 0.245777, 0.376324, 0.594205", \ "0.0519535, 0.0930104, 0.121876, 0.169136, 0.247314, 0.378809, 0.595936", \ "0.0578285, 0.0984955, 0.127338, 0.17447, 0.253636, 0.384552, 0.601572", \ - "0.0705502, 0.11051, 0.139186, 0.186435, 0.265431, 0.396707, 0.615141" \ + "0.0705504, 0.11051, 0.139186, 0.186435, 0.265431, 0.396707, 0.615141" \ ); } fall_power (POWER_7x7ds1) { index_1 ("0.0186, 0.0966, 0.174, 0.3294, 0.6408, 1.263, 2.5074"); index_2 ("0.001, 0.0468, 0.078, 0.1296, 0.216, 0.36, 0.6"); values ( \ - "0.0480298, 0.0904484, 0.118944, 0.165786, 0.243865, 0.37375, 0.590428", \ - "0.0478921, 0.09066, 0.118966, 0.165743, 0.24392, 0.376997, 0.590476", \ - "0.0481875, 0.0906882, 0.119288, 0.166994, 0.24444, 0.374165, 0.591307", \ - "0.0494437, 0.0921389, 0.120723, 0.167347, 0.245941, 0.375673, 0.591919", \ - "0.0519353, 0.094456, 0.123136, 0.170552, 0.248072, 0.37784, 0.597361", \ - "0.0575829, 0.100162, 0.128507, 0.175998, 0.254788, 0.385895, 0.602408", \ - "0.0696084, 0.111674, 0.140144, 0.187457, 0.266057, 0.397228, 0.61615" \ + "0.0480233, 0.0904383, 0.118943, 0.165778, 0.243956, 0.373748, 0.590418", \ + "0.0478921, 0.09066, 0.118966, 0.165743, 0.243926, 0.37403, 0.590476", \ + "0.0481875, 0.0906882, 0.119288, 0.166994, 0.24444, 0.374165, 0.590865", \ + "0.0494437, 0.0921388, 0.12078, 0.167367, 0.246051, 0.376931, 0.592099", \ + "0.0519332, 0.0944945, 0.123153, 0.170553, 0.248653, 0.37784, 0.597361", \ + "0.057583, 0.100162, 0.128507, 0.175998, 0.254788, 0.385895, 0.602408", \ + "0.0696084, 0.111674, 0.140143, 0.187457, 0.265834, 0.397228, 0.61615" \ ); } } @@ -29557,12 +29668,12 @@ library (sg13g2_stdcell_slow_1p35V_125C) { index_1 ("0.0186, 0.0966, 0.174, 0.3294, 0.6408, 1.263, 2.5074"); index_2 ("0.001, 0.0468, 0.078, 0.1296, 0.216, 0.36, 0.6"); values ( \ - "0.0632758, 0.107368, 0.137065, 0.185514, 0.265389, 0.396892, 0.614653", \ + "0.0632756, 0.107385, 0.137065, 0.185511, 0.26539, 0.396892, 0.614653", \ "0.0657582, 0.109853, 0.139577, 0.188298, 0.268764, 0.401006, 0.619557", \ "0.0673126, 0.111558, 0.141772, 0.190323, 0.271962, 0.40385, 0.622949", \ "0.0682077, 0.112145, 0.141913, 0.191137, 0.274297, 0.406066, 0.627878", \ - "0.0707353, 0.114791, 0.144894, 0.193906, 0.275004, 0.41192, 0.632995", \ - "0.0765076, 0.120352, 0.150231, 0.199569, 0.281919, 0.417736, 0.64179", \ + "0.0707138, 0.114791, 0.144894, 0.193906, 0.275004, 0.41192, 0.632995", \ + "0.0765076, 0.120352, 0.150099, 0.199578, 0.281835, 0.417837, 0.64179", \ "0.0885172, 0.131753, 0.161449, 0.210287, 0.29344, 0.430416, 0.658417" \ ); } @@ -29576,6 +29687,7 @@ library (sg13g2_stdcell_slow_1p35V_125C) { timing () { related_pin : "CLK"; sdf_cond : "SCE == 1'b1"; + sdf_edges : start_edge; timing_sense : non_unate; timing_type : rising_edge; when : "SCE"; @@ -29583,37 +29695,37 @@ library (sg13g2_stdcell_slow_1p35V_125C) { index_1 ("0.0186, 0.0966, 0.174, 0.3294, 0.6408, 1.263, 2.5074"); index_2 ("0.001, 0.0468, 0.078, 0.1296, 0.216, 0.36, 0.6"); values ( \ - "0.139532, 0.234847, 0.283604, 0.360872, 0.488243, 0.700531, 1.0541", \ - "0.171791, 0.267165, 0.31596, 0.393121, 0.52066, 0.733608, 1.08631", \ + "0.139524, 0.234906, 0.283609, 0.360781, 0.48832, 0.700468, 1.05409", \ + "0.171791, 0.267165, 0.31596, 0.39312, 0.52066, 0.733608, 1.08631", \ "0.19293, 0.288304, 0.337054, 0.414188, 0.541909, 0.754231, 1.10861", \ - "0.223552, 0.319078, 0.367617, 0.444909, 0.572521, 0.784744, 1.13815", \ - "0.262599, 0.357924, 0.406703, 0.483797, 0.611373, 0.82385, 1.17677", \ + "0.223685, 0.318894, 0.367799, 0.444703, 0.572521, 0.784744, 1.13815", \ + "0.262599, 0.357924, 0.406703, 0.483797, 0.611429, 0.823793, 1.17677", \ "0.315654, 0.410788, 0.45954, 0.536691, 0.664245, 0.876471, 1.22977", \ - "0.380807, 0.475385, 0.524053, 0.601369, 0.728876, 0.941037, 1.2948" \ + "0.380807, 0.475385, 0.524072, 0.601369, 0.728876, 0.941037, 1.2948" \ ); } rise_transition (TIMING_DELAY_7x7ds1) { index_1 ("0.0186, 0.0966, 0.174, 0.3294, 0.6408, 1.263, 2.5074"); index_2 ("0.001, 0.0468, 0.078, 0.1296, 0.216, 0.36, 0.6"); values ( \ - "0.0268127, 0.124134, 0.187292, 0.294925, 0.47949, 0.790562, 1.30961", \ - "0.0268961, 0.124135, 0.18736, 0.296271, 0.479555, 0.791018, 1.30966", \ - "0.0268971, 0.124157, 0.187361, 0.296272, 0.479556, 0.792499, 1.31147", \ - "0.0268981, 0.124158, 0.187362, 0.296273, 0.479557, 0.7925, 1.31148", \ - "0.0268991, 0.124227, 0.187423, 0.296274, 0.479558, 0.792501, 1.31149", \ - "0.0269001, 0.124233, 0.187459, 0.296275, 0.479559, 0.792502, 1.3115", \ - "0.0269011, 0.124234, 0.18746, 0.296276, 0.47956, 0.792503, 1.31151" \ + "0.0268273, 0.124144, 0.187289, 0.294926, 0.479643, 0.790562, 1.30961", \ + "0.0268961, 0.124145, 0.18736, 0.295799, 0.479644, 0.791018, 1.30966", \ + "0.0268971, 0.124157, 0.187361, 0.2958, 0.479645, 0.792499, 1.31147", \ + "0.0268981, 0.124158, 0.187362, 0.295801, 0.479646, 0.7925, 1.31148", \ + "0.0268991, 0.124227, 0.187423, 0.295802, 0.479647, 0.792501, 1.31149", \ + "0.0269001, 0.124233, 0.187459, 0.295803, 0.479648, 0.792502, 1.3115", \ + "0.0269011, 0.124234, 0.18746, 0.295804, 0.479649, 0.792503, 1.31151" \ ); } cell_fall (TIMING_DELAY_7x7ds1) { index_1 ("0.0186, 0.0966, 0.174, 0.3294, 0.6408, 1.263, 2.5074"); index_2 ("0.001, 0.0468, 0.078, 0.1296, 0.216, 0.36, 0.6"); values ( \ - "0.154985, 0.263402, 0.311464, 0.382251, 0.494942, 0.679597, 0.986654", \ + "0.154985, 0.2634, 0.311474, 0.382414, 0.494942, 0.679635, 0.986548", \ "0.187431, 0.295881, 0.343957, 0.414954, 0.527426, 0.712106, 1.01923", \ - "0.209049, 0.317433, 0.365538, 0.436547, 0.548964, 0.733734, 1.04124", \ + "0.209049, 0.317444, 0.365538, 0.436547, 0.548964, 0.733734, 1.04124", \ "0.240778, 0.349057, 0.397129, 0.468017, 0.580585, 0.765297, 1.07222", \ - "0.283332, 0.391512, 0.439664, 0.510693, 0.623113, 0.807884, 1.1148", \ + "0.283299, 0.391506, 0.439662, 0.510693, 0.623115, 0.807884, 1.1148", \ "0.342392, 0.450738, 0.498967, 0.570059, 0.682673, 0.867468, 1.1743", \ "0.42167, 0.532316, 0.580678, 0.65186, 0.76457, 0.949277, 1.25629" \ ); @@ -29622,55 +29734,56 @@ library (sg13g2_stdcell_slow_1p35V_125C) { index_1 ("0.0186, 0.0966, 0.174, 0.3294, 0.6408, 1.263, 2.5074"); index_2 ("0.001, 0.0468, 0.078, 0.1296, 0.216, 0.36, 0.6"); values ( \ - "0.0360665, 0.12342, 0.170533, 0.250245, 0.390788, 0.632892, 1.04165", \ - "0.0360803, 0.123429, 0.170731, 0.251145, 0.390974, 0.632893, 1.04174", \ - "0.0361274, 0.1235, 0.170732, 0.251146, 0.390975, 0.632894, 1.04206", \ - "0.0361375, 0.123501, 0.170733, 0.251147, 0.390976, 0.63338, 1.04207", \ - "0.0364778, 0.123868, 0.170734, 0.251148, 0.391024, 0.633381, 1.04208", \ - "0.037892, 0.124367, 0.171144, 0.251149, 0.391069, 0.633382, 1.04209", \ - "0.042742, 0.126481, 0.172466, 0.251551, 0.391447, 0.633387, 1.0421" \ + "0.0360665, 0.123365, 0.170529, 0.250025, 0.390788, 0.632866, 1.04177", \ + "0.0360803, 0.123429, 0.170731, 0.251145, 0.390974, 0.632867, 1.04178", \ + "0.0361274, 0.123507, 0.170732, 0.251146, 0.390975, 0.632877, 1.04204", \ + "0.0361375, 0.123508, 0.170733, 0.251147, 0.390976, 0.63338, 1.04205", \ + "0.0364637, 0.123746, 0.170734, 0.251148, 0.391027, 0.633381, 1.04206", \ + "0.037892, 0.124367, 0.171144, 0.251149, 0.391069, 0.633382, 1.04207", \ + "0.042742, 0.126481, 0.172466, 0.251551, 0.391447, 0.633387, 1.04208" \ ); } } timing () { related_pin : "CLK"; + sdf_edges : start_edge; timing_sense : non_unate; timing_type : rising_edge; cell_rise (TIMING_DELAY_7x7ds1) { index_1 ("0.0186, 0.0966, 0.174, 0.3294, 0.6408, 1.263, 2.5074"); index_2 ("0.001, 0.0468, 0.078, 0.1296, 0.216, 0.36, 0.6"); values ( \ - "0.139532, 0.234847, 0.283604, 0.360872, 0.488243, 0.700531, 1.0541", \ - "0.171791, 0.267165, 0.31596, 0.393121, 0.52066, 0.733608, 1.08631", \ + "0.139524, 0.234906, 0.283609, 0.360781, 0.48832, 0.700468, 1.05409", \ + "0.171791, 0.267165, 0.31596, 0.39312, 0.52066, 0.733608, 1.08631", \ "0.19293, 0.288304, 0.337054, 0.414188, 0.541909, 0.754231, 1.10861", \ - "0.223552, 0.319078, 0.367617, 0.444909, 0.572521, 0.784744, 1.13815", \ - "0.262599, 0.357924, 0.406703, 0.483797, 0.611373, 0.82385, 1.17677", \ + "0.223685, 0.318894, 0.367799, 0.444703, 0.572521, 0.784744, 1.13815", \ + "0.262599, 0.357924, 0.406703, 0.483797, 0.611429, 0.823793, 1.17677", \ "0.315654, 0.410788, 0.45954, 0.536691, 0.664245, 0.876471, 1.22977", \ - "0.380807, 0.475385, 0.524053, 0.601369, 0.728876, 0.941037, 1.2948" \ + "0.380807, 0.475385, 0.524072, 0.601369, 0.728876, 0.941037, 1.2948" \ ); } rise_transition (TIMING_DELAY_7x7ds1) { index_1 ("0.0186, 0.0966, 0.174, 0.3294, 0.6408, 1.263, 2.5074"); index_2 ("0.001, 0.0468, 0.078, 0.1296, 0.216, 0.36, 0.6"); values ( \ - "0.0268127, 0.124134, 0.187292, 0.294925, 0.47949, 0.790562, 1.30961", \ - "0.0268961, 0.124135, 0.18736, 0.296271, 0.479555, 0.791018, 1.30966", \ - "0.0268971, 0.124157, 0.187361, 0.296272, 0.479556, 0.792499, 1.31147", \ - "0.0268981, 0.124158, 0.187362, 0.296273, 0.479557, 0.7925, 1.31148", \ - "0.0268991, 0.124227, 0.187423, 0.296274, 0.479558, 0.792501, 1.31149", \ - "0.0269001, 0.124233, 0.187459, 0.296275, 0.479559, 0.792502, 1.3115", \ - "0.0269011, 0.124234, 0.18746, 0.296276, 0.47956, 0.792503, 1.31151" \ + "0.0268273, 0.124144, 0.187289, 0.294926, 0.479643, 0.790562, 1.30961", \ + "0.0268961, 0.124145, 0.18736, 0.295799, 0.479644, 0.791018, 1.30966", \ + "0.0268971, 0.124157, 0.187361, 0.2958, 0.479645, 0.792499, 1.31147", \ + "0.0268981, 0.124158, 0.187362, 0.295801, 0.479646, 0.7925, 1.31148", \ + "0.0268991, 0.124227, 0.187423, 0.295802, 0.479647, 0.792501, 1.31149", \ + "0.0269001, 0.124233, 0.187459, 0.295803, 0.479648, 0.792502, 1.3115", \ + "0.0269011, 0.124234, 0.18746, 0.295804, 0.479649, 0.792503, 1.31151" \ ); } cell_fall (TIMING_DELAY_7x7ds1) { index_1 ("0.0186, 0.0966, 0.174, 0.3294, 0.6408, 1.263, 2.5074"); index_2 ("0.001, 0.0468, 0.078, 0.1296, 0.216, 0.36, 0.6"); values ( \ - "0.154985, 0.263402, 0.311464, 0.382251, 0.494942, 0.679597, 0.986654", \ + "0.154985, 0.2634, 0.311474, 0.382414, 0.494942, 0.679635, 0.986548", \ "0.187431, 0.295881, 0.343957, 0.414954, 0.527426, 0.712106, 1.01923", \ - "0.209049, 0.317433, 0.365538, 0.436547, 0.548964, 0.733734, 1.04124", \ + "0.209049, 0.317444, 0.365538, 0.436547, 0.548964, 0.733734, 1.04124", \ "0.240778, 0.349057, 0.397129, 0.468017, 0.580585, 0.765297, 1.07222", \ - "0.283332, 0.391512, 0.439664, 0.510693, 0.623113, 0.807884, 1.1148", \ + "0.283299, 0.391506, 0.439662, 0.510693, 0.623115, 0.807884, 1.1148", \ "0.342392, 0.450738, 0.498967, 0.570059, 0.682673, 0.867468, 1.1743", \ "0.42167, 0.532316, 0.580678, 0.65186, 0.76457, 0.949277, 1.25629" \ ); @@ -29679,30 +29792,31 @@ library (sg13g2_stdcell_slow_1p35V_125C) { index_1 ("0.0186, 0.0966, 0.174, 0.3294, 0.6408, 1.263, 2.5074"); index_2 ("0.001, 0.0468, 0.078, 0.1296, 0.216, 0.36, 0.6"); values ( \ - "0.0360665, 0.12342, 0.170533, 0.250245, 0.390788, 0.632892, 1.04165", \ - "0.0360803, 0.123429, 0.170731, 0.251145, 0.390974, 0.632893, 1.04174", \ - "0.0361274, 0.1235, 0.170732, 0.251146, 0.390975, 0.632894, 1.04206", \ - "0.0361375, 0.123501, 0.170733, 0.251147, 0.390976, 0.63338, 1.04207", \ - "0.0364778, 0.123868, 0.170734, 0.251148, 0.391024, 0.633381, 1.04208", \ - "0.037892, 0.124367, 0.171144, 0.251149, 0.391069, 0.633382, 1.04209", \ - "0.042742, 0.126481, 0.172466, 0.251551, 0.391447, 0.633387, 1.0421" \ + "0.0360665, 0.123365, 0.170529, 0.250025, 0.390788, 0.632866, 1.04177", \ + "0.0360803, 0.123429, 0.170731, 0.251145, 0.390974, 0.632867, 1.04178", \ + "0.0361274, 0.123507, 0.170732, 0.251146, 0.390975, 0.632877, 1.04204", \ + "0.0361375, 0.123508, 0.170733, 0.251147, 0.390976, 0.63338, 1.04205", \ + "0.0364637, 0.123746, 0.170734, 0.251148, 0.391027, 0.633381, 1.04206", \ + "0.037892, 0.124367, 0.171144, 0.251149, 0.391069, 0.633382, 1.04207", \ + "0.042742, 0.126481, 0.172466, 0.251551, 0.391447, 0.633387, 1.04208" \ ); } } timing () { related_pin : "RESET_B"; + sdf_edges : start_edge; timing_sense : negative_unate; timing_type : preset; cell_rise (TIMING_DELAY_7x7ds1) { index_1 ("0.0186, 0.0966, 0.174, 0.3294, 0.6408, 1.263, 2.5074"); index_2 ("0.001, 0.0468, 0.078, 0.1296, 0.216, 0.36, 0.6"); values ( \ - "0.213738, 0.306662, 0.355048, 0.432109, 0.559647, 0.77206, 1.12531", \ + "0.213791, 0.306733, 0.355049, 0.432089, 0.559688, 0.77206, 1.12531", \ "0.252272, 0.345271, 0.393573, 0.470698, 0.598656, 0.810591, 1.16454", \ "0.285668, 0.378759, 0.426947, 0.504089, 0.631717, 0.844026, 1.19713", \ "0.338222, 0.431156, 0.47948, 0.556452, 0.684098, 0.896368, 1.24969", \ "0.417232, 0.510041, 0.5584, 0.635439, 0.763036, 0.975275, 1.32856", \ - "0.527031, 0.620505, 0.668884, 0.746066, 0.873522, 1.08576, 1.43911", \ + "0.527031, 0.620678, 0.668884, 0.746066, 0.873522, 1.08587, 1.43909", \ "0.681006, 0.774735, 0.823531, 0.900255, 1.0271, 1.23998, 1.59391" \ ); } @@ -29710,12 +29824,12 @@ library (sg13g2_stdcell_slow_1p35V_125C) { index_1 ("0.0186, 0.0966, 0.174, 0.3294, 0.6408, 1.263, 2.5074"); index_2 ("0.001, 0.0468, 0.078, 0.1296, 0.216, 0.36, 0.6"); values ( \ - "0.0270945, 0.122429, 0.186048, 0.294295, 0.479334, 0.790532, 1.3094", \ - "0.0270946, 0.12243, 0.186238, 0.294331, 0.479705, 0.790533, 1.30974", \ - "0.02718, 0.122431, 0.186239, 0.294332, 0.479706, 0.790534, 1.30989", \ + "0.0271285, 0.122407, 0.186048, 0.294293, 0.47935, 0.790532, 1.3094", \ + "0.0271295, 0.122409, 0.186238, 0.294331, 0.479705, 0.790533, 1.30974", \ + "0.02718, 0.122417, 0.186239, 0.294332, 0.479706, 0.790534, 1.30989", \ "0.0273719, 0.12249, 0.18624, 0.294333, 0.479707, 0.790535, 1.30998", \ "0.0278663, 0.12262, 0.186241, 0.294334, 0.479708, 0.790536, 1.30999", \ - "0.028744, 0.123001, 0.186312, 0.294335, 0.479709, 0.790537, 1.31", \ + "0.028744, 0.12298, 0.186312, 0.294335, 0.479709, 0.790537, 1.31", \ "0.030251, 0.123574, 0.186696, 0.294491, 0.47971, 0.790538, 1.31001" \ ); } @@ -29727,24 +29841,24 @@ library (sg13g2_stdcell_slow_1p35V_125C) { index_1 ("0.0186, 0.0966, 0.174, 0.3294, 0.6408, 1.263, 2.5074"); index_2 ("0.001, 0.0468, 0.078, 0.1296, 0.216, 0.36, 0.6"); values ( \ - "0.0480924, 0.0906741, 0.119339, 0.166535, 0.244933, 0.375585, 0.593446", \ - "0.0479034, 0.0908014, 0.119407, 0.166942, 0.244886, 0.375765, 0.593344", \ + "0.0480908, 0.0906731, 0.11933, 0.166507, 0.245008, 0.375578, 0.593436", \ + "0.0479034, 0.0908014, 0.119417, 0.166724, 0.244886, 0.375765, 0.593344", \ "0.0482434, 0.0907706, 0.119564, 0.166945, 0.245402, 0.376866, 0.594533", \ - "0.0494737, 0.0921334, 0.12084, 0.167792, 0.246826, 0.377488, 0.595712", \ - "0.0519777, 0.094455, 0.123422, 0.170599, 0.249048, 0.380082, 0.597323", \ - "0.0576308, 0.100222, 0.128901, 0.176032, 0.255188, 0.386023, 0.604917", \ - "0.0696026, 0.111771, 0.140469, 0.187887, 0.266575, 0.397658, 0.616646" \ + "0.0494531, 0.092144, 0.120826, 0.167843, 0.247192, 0.377488, 0.595712", \ + "0.0519785, 0.094455, 0.123422, 0.170599, 0.24891, 0.380121, 0.597323", \ + "0.0576308, 0.100222, 0.128901, 0.176032, 0.255187, 0.386025, 0.603354", \ + "0.0696026, 0.111771, 0.140493, 0.187881, 0.266573, 0.397647, 0.616532" \ ); } fall_power (POWER_7x7ds1) { index_1 ("0.0186, 0.0966, 0.174, 0.3294, 0.6408, 1.263, 2.5074"); index_2 ("0.001, 0.0468, 0.078, 0.1296, 0.216, 0.36, 0.6"); values ( \ - "0.0484591, 0.0895634, 0.118071, 0.164815, 0.243032, 0.372928, 0.589643", \ - "0.0482078, 0.0896776, 0.117861, 0.165108, 0.242736, 0.37282, 0.589646", \ - "0.0483528, 0.0893634, 0.117959, 0.165978, 0.242809, 0.372952, 0.59015", \ + "0.0484591, 0.0895314, 0.118075, 0.164867, 0.243031, 0.372874, 0.589733", \ + "0.0482078, 0.0896982, 0.117861, 0.165108, 0.242736, 0.37282, 0.589646", \ + "0.0483528, 0.0893916, 0.117959, 0.165978, 0.242809, 0.372952, 0.590023", \ "0.0495117, 0.0906418, 0.119046, 0.166001, 0.244718, 0.374391, 0.591285", \ - "0.0519717, 0.0928572, 0.121568, 0.168881, 0.246907, 0.376601, 0.599277", \ + "0.0519557, 0.0928497, 0.121574, 0.168881, 0.247126, 0.376601, 0.599265", \ "0.057848, 0.0983836, 0.1268, 0.174336, 0.253079, 0.384326, 0.599639", \ "0.0705929, 0.110377, 0.138796, 0.186175, 0.26437, 0.396029, 0.614831" \ ); @@ -29756,24 +29870,24 @@ library (sg13g2_stdcell_slow_1p35V_125C) { index_1 ("0.0186, 0.0966, 0.174, 0.3294, 0.6408, 1.263, 2.5074"); index_2 ("0.001, 0.0468, 0.078, 0.1296, 0.216, 0.36, 0.6"); values ( \ - "0.0480924, 0.0906741, 0.119339, 0.166535, 0.244933, 0.375585, 0.593446", \ - "0.0479034, 0.0908014, 0.119407, 0.166942, 0.244886, 0.375765, 0.593344", \ + "0.0480908, 0.0906731, 0.11933, 0.166507, 0.245008, 0.375578, 0.593436", \ + "0.0479034, 0.0908014, 0.119417, 0.166724, 0.244886, 0.375765, 0.593344", \ "0.0482434, 0.0907706, 0.119564, 0.166945, 0.245402, 0.376866, 0.594533", \ - "0.0494737, 0.0921334, 0.12084, 0.167792, 0.246826, 0.377488, 0.595712", \ - "0.0519777, 0.094455, 0.123422, 0.170599, 0.249048, 0.380082, 0.597323", \ - "0.0576308, 0.100222, 0.128901, 0.176032, 0.255188, 0.386023, 0.604917", \ - "0.0696026, 0.111771, 0.140469, 0.187887, 0.266575, 0.397658, 0.616646" \ + "0.0494531, 0.092144, 0.120826, 0.167843, 0.247192, 0.377488, 0.595712", \ + "0.0519785, 0.094455, 0.123422, 0.170599, 0.24891, 0.380121, 0.597323", \ + "0.0576308, 0.100222, 0.128901, 0.176032, 0.255187, 0.386025, 0.603354", \ + "0.0696026, 0.111771, 0.140493, 0.187881, 0.266573, 0.397647, 0.616532" \ ); } fall_power (POWER_7x7ds1) { index_1 ("0.0186, 0.0966, 0.174, 0.3294, 0.6408, 1.263, 2.5074"); index_2 ("0.001, 0.0468, 0.078, 0.1296, 0.216, 0.36, 0.6"); values ( \ - "0.0484591, 0.0895634, 0.118071, 0.164815, 0.243032, 0.372928, 0.589643", \ - "0.0482078, 0.0896776, 0.117861, 0.165108, 0.242736, 0.37282, 0.589646", \ - "0.0483528, 0.0893634, 0.117959, 0.165978, 0.242809, 0.372952, 0.59015", \ + "0.0484591, 0.0895314, 0.118075, 0.164867, 0.243031, 0.372874, 0.589733", \ + "0.0482078, 0.0896982, 0.117861, 0.165108, 0.242736, 0.37282, 0.589646", \ + "0.0483528, 0.0893916, 0.117959, 0.165978, 0.242809, 0.372952, 0.590023", \ "0.0495117, 0.0906418, 0.119046, 0.166001, 0.244718, 0.374391, 0.591285", \ - "0.0519717, 0.0928572, 0.121568, 0.168881, 0.246907, 0.376601, 0.599277", \ + "0.0519557, 0.0928497, 0.121574, 0.168881, 0.247126, 0.376601, 0.599265", \ "0.057848, 0.0983836, 0.1268, 0.174336, 0.253079, 0.384326, 0.599639", \ "0.0705929, 0.110377, 0.138796, 0.186175, 0.26437, 0.396029, 0.614831" \ ); @@ -29785,12 +29899,12 @@ library (sg13g2_stdcell_slow_1p35V_125C) { index_1 ("0.0186, 0.0966, 0.174, 0.3294, 0.6408, 1.263, 2.5074"); index_2 ("0.001, 0.0468, 0.078, 0.1296, 0.216, 0.36, 0.6"); values ( \ - "0.06331, 0.106631, 0.135916, 0.183617, 0.262034, 0.391465, 0.605364", \ + "0.0633148, 0.106707, 0.135916, 0.183604, 0.262086, 0.391465, 0.605397", \ "0.0657897, 0.109478, 0.138498, 0.186427, 0.265651, 0.395523, 0.610829", \ "0.067362, 0.110808, 0.140454, 0.188352, 0.267611, 0.398306, 0.614205", \ "0.0682487, 0.111518, 0.140801, 0.189165, 0.269111, 0.402784, 0.617688", \ - "0.0707113, 0.114057, 0.143438, 0.191473, 0.271879, 0.405525, 0.623266", \ - "0.0764878, 0.119606, 0.148901, 0.19702, 0.277743, 0.411085, 0.633464", \ + "0.0707113, 0.114057, 0.143438, 0.191474, 0.271879, 0.405525, 0.623266", \ + "0.0764878, 0.119533, 0.148901, 0.19702, 0.277743, 0.411122, 0.633557", \ "0.0884735, 0.130964, 0.160355, 0.208486, 0.289092, 0.423377, 0.646616" \ ); } @@ -29807,9 +29921,9 @@ library (sg13g2_stdcell_slow_1p35V_125C) { max_transition : 2.5074; capacitance : 0.00290371; rise_capacitance : 0.00295156; - rise_capacitance_range (0.00295156, 0.00295156); + rise_capacitance_range (0.00265145, 0.00321688); fall_capacitance : 0.00284219; - fall_capacitance_range (0.00284219, 0.00284219); + fall_capacitance_range (0.00261775, 0.00304804); timing () { related_pin : "CLK"; timing_type : min_pulse_width; @@ -29825,13 +29939,13 @@ library (sg13g2_stdcell_slow_1p35V_125C) { rise_power (passive_POWER_7x1ds1) { index_1 ("0.0186, 0.0966, 0.174, 0.3294, 0.6408, 1.263, 2.5074"); values ( \ - "0.0138317, 0.0136043, 0.0138313, 0.0148415, 0.0172474, 0.0227995, 0.0343569" \ + "0.013817, 0.0136043, 0.0138313, 0.0148415, 0.0172474, 0.0227995, 0.0343569" \ ); } fall_power (passive_POWER_7x1ds1) { index_1 ("0.0186, 0.0966, 0.174, 0.3294, 0.6408, 1.263, 2.5074"); values ( \ - "0.0133841, 0.0131251, 0.0135468, 0.014434, 0.017095, 0.0225344, 0.0345902" \ + "0.0133841, 0.0131252, 0.0135468, 0.0144341, 0.017095, 0.0225344, 0.0345903" \ ); } } @@ -29845,7 +29959,7 @@ library (sg13g2_stdcell_slow_1p35V_125C) { fall_power (passive_POWER_7x1ds1) { index_1 ("0.0186, 0.0966, 0.174, 0.3294, 0.6408, 1.263, 2.5074"); values ( \ - "0.026054, 0.0257944, 0.0261644, 0.0271164, 0.029795, 0.0354127, 0.0479326" \ + "0.0260508, 0.0257939, 0.0261644, 0.0271164, 0.029795, 0.0354127, 0.0479326" \ ); } } @@ -29859,7 +29973,7 @@ library (sg13g2_stdcell_slow_1p35V_125C) { fall_power (passive_POWER_7x1ds1) { index_1 ("0.0186, 0.0966, 0.174, 0.3294, 0.6408, 1.263, 2.5074"); values ( \ - "0.0243094, 0.0241304, 0.024612, 0.0255381, 0.028432, 0.034077, 0.0464971" \ + "0.0243095, 0.0241316, 0.024612, 0.0255381, 0.028432, 0.034077, 0.0464972" \ ); } } @@ -29868,13 +29982,13 @@ library (sg13g2_stdcell_slow_1p35V_125C) { rise_power (passive_POWER_7x1ds1) { index_1 ("0.0186, 0.0966, 0.174, 0.3294, 0.6408, 1.263, 2.5074"); values ( \ - "0.0135322, 0.0133003, 0.0135515, 0.0145424, 0.0169372, 0.0225004, 0.0340818" \ + "0.0135332, 0.0133003, 0.0135504, 0.0145424, 0.0169372, 0.0225003, 0.0340818" \ ); } fall_power (passive_POWER_7x1ds1) { index_1 ("0.0186, 0.0966, 0.174, 0.3294, 0.6408, 1.263, 2.5074"); values ( \ - "0.0131582, 0.0129031, 0.013304, 0.014237, 0.0168802, 0.0223186, 0.0343932" \ + "0.0131583, 0.0129031, 0.013304, 0.014237, 0.0168803, 0.0223186, 0.0343932" \ ); } } @@ -29883,13 +29997,13 @@ library (sg13g2_stdcell_slow_1p35V_125C) { rise_power (passive_POWER_7x1ds1) { index_1 ("0.0186, 0.0966, 0.174, 0.3294, 0.6408, 1.263, 2.5074"); values ( \ - "0.0138322, 0.0136023, 0.0138332, 0.0148428, 0.0172473, 0.022799, 0.0343563" \ + "0.0138343, 0.0136023, 0.0138331, 0.0148428, 0.0172472, 0.0227989, 0.0343562" \ ); } fall_power (passive_POWER_7x1ds1) { index_1 ("0.0186, 0.0966, 0.174, 0.3294, 0.6408, 1.263, 2.5074"); values ( \ - "0.0133834, 0.0131252, 0.0135464, 0.0144341, 0.0170957, 0.0225321, 0.0345891" \ + "0.0133834, 0.0131251, 0.0135463, 0.014434, 0.0170957, 0.0225321, 0.0345891" \ ); } } @@ -29898,13 +30012,13 @@ library (sg13g2_stdcell_slow_1p35V_125C) { rise_power (passive_POWER_7x1ds1) { index_1 ("0.0186, 0.0966, 0.174, 0.3294, 0.6408, 1.263, 2.5074"); values ( \ - "0.000414204, 0.000202666, 0.000427785, 0.0014672, 0.00379364, 0.00935298, 0.0209094" \ + "0.000414332, 0.000202659, 0.000427778, 0.00146719, 0.00379364, 0.00935297, 0.0209094" \ ); } fall_power (passive_POWER_7x1ds1) { index_1 ("0.0186, 0.0966, 0.174, 0.3294, 0.6408, 1.263, 2.5074"); values ( \ - "0.00137131, 0.0011107, 0.00151583, 0.00243759, 0.00509551, 0.0105124, 0.0225825" \ + "0.00135031, 0.0011107, 0.00151583, 0.00243759, 0.00509551, 0.0105124, 0.0225825" \ ); } } @@ -29913,13 +30027,13 @@ library (sg13g2_stdcell_slow_1p35V_125C) { rise_power (passive_POWER_7x1ds1) { index_1 ("0.0186, 0.0966, 0.174, 0.3294, 0.6408, 1.263, 2.5074"); values ( \ - "0.0136305, 0.0134025, 0.0136536, 0.0146419, 0.0170338, 0.0225997, 0.0341808" \ + "0.0136275, 0.0134025, 0.0136536, 0.0146419, 0.0170338, 0.0225997, 0.0341808" \ ); } fall_power (passive_POWER_7x1ds1) { index_1 ("0.0186, 0.0966, 0.174, 0.3294, 0.6408, 1.263, 2.5074"); values ( \ - "0.0133281, 0.0130733, 0.0134747, 0.0144081, 0.0170537, 0.022488, 0.0345644" \ + "0.0133245, 0.0130733, 0.0134747, 0.0144081, 0.0170537, 0.022488, 0.0345644" \ ); } } @@ -29927,13 +30041,13 @@ library (sg13g2_stdcell_slow_1p35V_125C) { rise_power (passive_POWER_7x1ds1) { index_1 ("0.0186, 0.0966, 0.174, 0.3294, 0.6408, 1.263, 2.5074"); values ( \ - "0.0135322, 0.0133003, 0.0135515, 0.0145424, 0.0169372, 0.0225004, 0.0340818" \ + "0.0135332, 0.0133003, 0.0135504, 0.0145424, 0.0169372, 0.0225003, 0.0340818" \ ); } fall_power (passive_POWER_7x1ds1) { index_1 ("0.0186, 0.0966, 0.174, 0.3294, 0.6408, 1.263, 2.5074"); values ( \ - "0.0133841, 0.0131251, 0.0135468, 0.014434, 0.017095, 0.0225344, 0.0345902" \ + "0.0133841, 0.0131252, 0.0135468, 0.0144341, 0.017095, 0.0225344, 0.0345903" \ ); } } @@ -29944,11 +30058,12 @@ library (sg13g2_stdcell_slow_1p35V_125C) { max_transition : 2.5074; capacitance : 0.00272772; rise_capacitance : 0.00277776; - rise_capacitance_range (0.00277776, 0.00277776); + rise_capacitance_range (0.00238738, 0.00311154); fall_capacitance : 0.00267768; - fall_capacitance_range (0.00267768, 0.00267768); + fall_capacitance_range (0.00236157, 0.00286339); timing () { related_pin : "CLK"; + sdf_edges : both_edges; timing_type : hold_rising; rise_constraint (CONSTRAINT_4x4) { index_1 ("0.0186, 0.51636, 1.263, 2.5074"); @@ -29973,6 +30088,7 @@ library (sg13g2_stdcell_slow_1p35V_125C) { } timing () { related_pin : "CLK"; + sdf_edges : both_edges; timing_type : setup_rising; rise_constraint (CONSTRAINT_4x4) { index_1 ("0.0186, 0.51636, 1.263, 2.5074"); @@ -29989,7 +30105,7 @@ library (sg13g2_stdcell_slow_1p35V_125C) { index_2 ("0.0186, 0.51636, 1.263, 2.5074"); values ( \ "0.210286, 0.107567, 0.0530083, -0.00456862", \ - "0.329202, 0.226635, 0.172112, 0.11486", \ + "0.331698, 0.226635, 0.172112, 0.11486", \ "0.433058, 0.328769, 0.272535, 0.21623", \ "0.544241, 0.443187, 0.385484, 0.330572" \ ); @@ -30000,13 +30116,13 @@ library (sg13g2_stdcell_slow_1p35V_125C) { rise_power (passive_POWER_7x1ds1) { index_1 ("0.0186, 0.0966, 0.174, 0.3294, 0.6408, 1.263, 2.5074"); values ( \ - "0.0265357, 0.0263016, 0.026432, 0.0270864, 0.0289902, 0.0331962, 0.0425761" \ + "0.0265359, 0.0263015, 0.0264319, 0.0270863, 0.0289902, 0.0331961, 0.042576" \ ); } fall_power (passive_POWER_7x1ds1) { index_1 ("0.0186, 0.0966, 0.174, 0.3294, 0.6408, 1.263, 2.5074"); values ( \ - "0.0359463, 0.0357302, 0.0360684, 0.037004, 0.039305, 0.0439812, 0.0540025" \ + "0.0359386, 0.0357302, 0.0360683, 0.0370039, 0.039305, 0.0439812, 0.0540025" \ ); } } @@ -30014,13 +30130,13 @@ library (sg13g2_stdcell_slow_1p35V_125C) { rise_power (passive_POWER_7x1ds1) { index_1 ("0.0186, 0.0966, 0.174, 0.3294, 0.6408, 1.263, 2.5074"); values ( \ - "0.0265357, 0.0263016, 0.026432, 0.0270864, 0.0289902, 0.0331962, 0.0425761" \ + "0.0265359, 0.0263015, 0.0264319, 0.0270863, 0.0289902, 0.0331961, 0.042576" \ ); } fall_power (passive_POWER_7x1ds1) { index_1 ("0.0186, 0.0966, 0.174, 0.3294, 0.6408, 1.263, 2.5074"); values ( \ - "0.0359463, 0.0357302, 0.0360684, 0.037004, 0.039305, 0.0439812, 0.0540025" \ + "0.0359386, 0.0357302, 0.0360683, 0.0370039, 0.039305, 0.0439812, 0.0540025" \ ); } } @@ -30028,13 +30144,14 @@ library (sg13g2_stdcell_slow_1p35V_125C) { pin (RESET_B) { direction : input; max_transition : 2.5074; - capacitance : 0.00513146; - rise_capacitance : 0.00513146; - rise_capacitance_range (0.00513146, 0.00513146); - fall_capacitance : 0.00513146; - fall_capacitance_range (0.00513146, 0.00513146); + capacitance : 0.00513145; + rise_capacitance : 0.00513145; + rise_capacitance_range (0.00513145, 0.00513145); + fall_capacitance : 0.00513145; + fall_capacitance_range (0.0049955, 0.00523759); timing () { related_pin : "CLK"; + sdf_edges : both_edges; timing_type : recovery_rising; rise_constraint (CONSTRAINT_4x4) { index_1 ("0.0186, 0.51636, 1.263, 2.5074"); @@ -30049,6 +30166,7 @@ library (sg13g2_stdcell_slow_1p35V_125C) { } timing () { related_pin : "CLK"; + sdf_edges : both_edges; timing_type : removal_rising; rise_constraint (CONSTRAINT_4x4) { index_1 ("0.0186, 0.51636, 1.263, 2.5074"); @@ -30078,11 +30196,12 @@ library (sg13g2_stdcell_slow_1p35V_125C) { max_transition : 2.5074; capacitance : 0.0028472; rise_capacitance : 0.00288106; - rise_capacitance_range (0.00288106, 0.00288106); + rise_capacitance_range (0.00249614, 0.00321229); fall_capacitance : 0.00277948; - fall_capacitance_range (0.00277948, 0.00277948); + fall_capacitance_range (0.00246182, 0.00296556); timing () { related_pin : "CLK"; + sdf_edges : both_edges; timing_type : hold_rising; rise_constraint (CONSTRAINT_4x4) { index_1 ("0.0186, 0.51636, 1.263, 2.5074"); @@ -30107,6 +30226,7 @@ library (sg13g2_stdcell_slow_1p35V_125C) { } timing () { related_pin : "CLK"; + sdf_edges : both_edges; timing_type : setup_rising; rise_constraint (CONSTRAINT_4x4) { index_1 ("0.0186, 0.51636, 1.263, 2.5074"); @@ -30134,13 +30254,13 @@ library (sg13g2_stdcell_slow_1p35V_125C) { rise_power (passive_POWER_7x1ds1) { index_1 ("0.0186, 0.0966, 0.174, 0.3294, 0.6408, 1.263, 2.5074"); values ( \ - "0.0267383, 0.0265078, 0.0266722, 0.027282, 0.0291861, 0.0333693, 0.0427769" \ + "0.0267368, 0.0265078, 0.0266722, 0.027282, 0.0291862, 0.0333693, 0.042777" \ ); } fall_power (passive_POWER_7x1ds1) { index_1 ("0.0186, 0.0966, 0.174, 0.3294, 0.6408, 1.263, 2.5074"); values ( \ - "0.0121545, 0.0119199, 0.0122828, 0.0132482, 0.0155418, 0.0202214, 0.0302457" \ + "0.0121546, 0.0119199, 0.0122829, 0.0132483, 0.0155418, 0.0202214, 0.0302457" \ ); } } @@ -30148,13 +30268,13 @@ library (sg13g2_stdcell_slow_1p35V_125C) { rise_power (passive_POWER_7x1ds1) { index_1 ("0.0186, 0.0966, 0.174, 0.3294, 0.6408, 1.263, 2.5074"); values ( \ - "0.0267383, 0.0265078, 0.0266722, 0.027282, 0.0291861, 0.0333693, 0.0427769" \ + "0.0267368, 0.0265078, 0.0266722, 0.027282, 0.0291862, 0.0333693, 0.042777" \ ); } fall_power (passive_POWER_7x1ds1) { index_1 ("0.0186, 0.0966, 0.174, 0.3294, 0.6408, 1.263, 2.5074"); values ( \ - "0.0121545, 0.0119199, 0.0122828, 0.0132482, 0.0155418, 0.0202214, 0.0302457" \ + "0.0121546, 0.0119199, 0.0122829, 0.0132483, 0.0155418, 0.0202214, 0.0302457" \ ); } } @@ -30165,11 +30285,12 @@ library (sg13g2_stdcell_slow_1p35V_125C) { max_transition : 2.5074; capacitance : 0.00465476; rise_capacitance : 0.00476835; - rise_capacitance_range (0.00476835, 0.00476835); + rise_capacitance_range (0.00429562, 0.00514527); fall_capacitance : 0.00454116; - fall_capacitance_range (0.00454116, 0.00454116); + fall_capacitance_range (0.00433956, 0.00502513); timing () { related_pin : "CLK"; + sdf_edges : both_edges; timing_type : hold_rising; rise_constraint (CONSTRAINT_4x4) { index_1 ("0.0186, 0.51636, 1.263, 2.5074"); @@ -30185,7 +30306,7 @@ library (sg13g2_stdcell_slow_1p35V_125C) { index_1 ("0.0186, 0.51636, 1.263, 2.5074"); index_2 ("0.0186, 0.51636, 1.263, 2.5074"); values ( \ - "-0.149157, -0.0626421, -0.0144316, 0.0342506", \ + "-0.149157, -0.0626421, -0.0170034, 0.0342506", \ "-0.249336, -0.162973, -0.114419, -0.0626293", \ "-0.33533, -0.250096, -0.202377, -0.148431", \ "-0.428212, -0.344223, -0.295086, -0.242026" \ @@ -30194,6 +30315,7 @@ library (sg13g2_stdcell_slow_1p35V_125C) { } timing () { related_pin : "CLK"; + sdf_edges : both_edges; timing_type : setup_rising; rise_constraint (CONSTRAINT_4x4) { index_1 ("0.0186, 0.51636, 1.263, 2.5074"); @@ -30210,7 +30332,7 @@ library (sg13g2_stdcell_slow_1p35V_125C) { index_2 ("0.0186, 0.51636, 1.263, 2.5074"); values ( \ "0.220067, 0.11755, 0.0607236, 0.00622484", \ - "0.321715, 0.216449, 0.161623, 0.103864", \ + "0.319219, 0.216449, 0.161623, 0.103864", \ "0.40734, 0.302544, 0.24825, 0.190806", \ "0.501068, 0.396454, 0.340285, 0.283348" \ ); @@ -30221,13 +30343,13 @@ library (sg13g2_stdcell_slow_1p35V_125C) { rise_power (passive_POWER_7x1ds1) { index_1 ("0.0186, 0.0966, 0.174, 0.3294, 0.6408, 1.263, 2.5074"); values ( \ - "0.0251136, 0.0249669, 0.0251212, 0.0258363, 0.0274721, 0.0311345, 0.0390805" \ + "0.0251574, 0.0249669, 0.0251212, 0.0258363, 0.0274721, 0.0311345, 0.0390805" \ ); } fall_power (passive_POWER_7x1ds1) { index_1 ("0.0186, 0.0966, 0.174, 0.3294, 0.6408, 1.263, 2.5074"); values ( \ - "0.0327455, 0.0326327, 0.0327914, 0.0334822, 0.0352266, 0.0390512, 0.0472732" \ + "0.0327455, 0.0326327, 0.0327913, 0.0334822, 0.0352265, 0.0390511, 0.0472732" \ ); } } @@ -30262,9 +30384,9 @@ library (sg13g2_stdcell_slow_1p35V_125C) { } } ff (IQ,IQN) { - clear : "RESET_B'"; + clear : "!RESET_B"; clocked_on : "CLK"; - next_state : "(SCE*SCD)+(SCE'*D)"; + next_state : "(SCE*SCD)+(!SCE*D)"; } test_cell () { pin (Q) { @@ -30295,7 +30417,7 @@ library (sg13g2_stdcell_slow_1p35V_125C) { signal_type : test_scan_enable; } ff (IQ,IQN) { - clear : "RESET_B'"; + clear : "!RESET_B"; clocked_on : "CLK"; next_state : "D"; } @@ -30381,6 +30503,7 @@ library (sg13g2_stdcell_slow_1p35V_125C) { timing () { related_pin : "CLK"; sdf_cond : "SCE == 1'b1"; + sdf_edges : start_edge; timing_sense : non_unate; timing_type : rising_edge; when : "SCE"; @@ -30440,6 +30563,7 @@ library (sg13g2_stdcell_slow_1p35V_125C) { timing () { related_pin : "CLK"; sdf_cond : "SCE == 1'b0"; + sdf_edges : start_edge; timing_sense : non_unate; timing_type : rising_edge; when : "!SCE"; @@ -30498,6 +30622,7 @@ library (sg13g2_stdcell_slow_1p35V_125C) { } timing () { related_pin : "CLK"; + sdf_edges : start_edge; timing_sense : non_unate; timing_type : rising_edge; cell_rise (TIMING_DELAY_7x7ds1) { @@ -30555,6 +30680,7 @@ library (sg13g2_stdcell_slow_1p35V_125C) { } timing () { related_pin : "RESET_B"; + sdf_edges : start_edge; timing_sense : positive_unate; timing_type : clear; cell_fall (TIMING_DELAY_7x7ds1) { @@ -30701,9 +30827,9 @@ library (sg13g2_stdcell_slow_1p35V_125C) { max_transition : 2.5074; capacitance : 0.00290379; rise_capacitance : 0.00295173; - rise_capacitance_range (0.00295173, 0.00295173); + rise_capacitance_range (0.00265647, 0.00321563); fall_capacitance : 0.00284217; - fall_capacitance_range (0.00284217, 0.00284217); + fall_capacitance_range (0.00261678, 0.00304794); timing () { related_pin : "CLK"; timing_type : min_pulse_width; @@ -30844,11 +30970,12 @@ library (sg13g2_stdcell_slow_1p35V_125C) { max_transition : 2.5074; capacitance : 0.0027302; rise_capacitance : 0.00278055; - rise_capacitance_range (0.00278055, 0.00278055); + rise_capacitance_range (0.00239107, 0.00311393); fall_capacitance : 0.00267985; - fall_capacitance_range (0.00267985, 0.00267985); + fall_capacitance_range (0.00236339, 0.00286572); timing () { related_pin : "CLK"; + sdf_edges : both_edges; timing_type : hold_rising; rise_constraint (CONSTRAINT_4x4) { index_1 ("0.0186, 0.51636, 1.263, 2.5074"); @@ -30873,6 +31000,7 @@ library (sg13g2_stdcell_slow_1p35V_125C) { } timing () { related_pin : "CLK"; + sdf_edges : both_edges; timing_type : setup_rising; rise_constraint (CONSTRAINT_4x4) { index_1 ("0.0186, 0.51636, 1.263, 2.5074"); @@ -30932,9 +31060,10 @@ library (sg13g2_stdcell_slow_1p35V_125C) { rise_capacitance : 0.0050238; rise_capacitance_range (0.0050238, 0.0050238); fall_capacitance : 0.0050238; - fall_capacitance_range (0.0050238, 0.0050238); + fall_capacitance_range (0.00471367, 0.00526341); timing () { related_pin : "CLK"; + sdf_edges : both_edges; timing_type : recovery_rising; rise_constraint (CONSTRAINT_4x4) { index_1 ("0.0186, 0.51636, 1.263, 2.5074"); @@ -30949,6 +31078,7 @@ library (sg13g2_stdcell_slow_1p35V_125C) { } timing () { related_pin : "CLK"; + sdf_edges : both_edges; timing_type : removal_rising; rise_constraint (CONSTRAINT_4x4) { index_1 ("0.0186, 0.51636, 1.263, 2.5074"); @@ -30978,11 +31108,12 @@ library (sg13g2_stdcell_slow_1p35V_125C) { max_transition : 2.5074; capacitance : 0.00284953; rise_capacitance : 0.00288339; - rise_capacitance_range (0.00288339, 0.00288339); + rise_capacitance_range (0.00249751, 0.00321465); fall_capacitance : 0.00278181; - fall_capacitance_range (0.00278181, 0.00278181); + fall_capacitance_range (0.00246417, 0.00296787); timing () { related_pin : "CLK"; + sdf_edges : both_edges; timing_type : hold_rising; rise_constraint (CONSTRAINT_4x4) { index_1 ("0.0186, 0.51636, 1.263, 2.5074"); @@ -31007,6 +31138,7 @@ library (sg13g2_stdcell_slow_1p35V_125C) { } timing () { related_pin : "CLK"; + sdf_edges : both_edges; timing_type : setup_rising; rise_constraint (CONSTRAINT_4x4) { index_1 ("0.0186, 0.51636, 1.263, 2.5074"); @@ -31065,11 +31197,12 @@ library (sg13g2_stdcell_slow_1p35V_125C) { max_transition : 2.5074; capacitance : 0.00465497; rise_capacitance : 0.00476868; - rise_capacitance_range (0.00476868, 0.00476868); + rise_capacitance_range (0.00429823, 0.0051453); fall_capacitance : 0.00454127; - fall_capacitance_range (0.00454127, 0.00454127); + fall_capacitance_range (0.00433558, 0.0050251); timing () { related_pin : "CLK"; + sdf_edges : both_edges; timing_type : hold_rising; rise_constraint (CONSTRAINT_4x4) { index_1 ("0.0186, 0.51636, 1.263, 2.5074"); @@ -31094,6 +31227,7 @@ library (sg13g2_stdcell_slow_1p35V_125C) { } timing () { related_pin : "CLK"; + sdf_edges : both_edges; timing_type : setup_rising; rise_constraint (CONSTRAINT_4x4) { index_1 ("0.0186, 0.51636, 1.263, 2.5074"); @@ -31162,9 +31296,9 @@ library (sg13g2_stdcell_slow_1p35V_125C) { } } ff (IQ,IQN) { - clear : "RESET_B'"; + clear : "!RESET_B"; clocked_on : "CLK"; - next_state : "(SCE*SCD)+(SCE'*D)"; + next_state : "(SCE*SCD)+(!SCE*D)"; } test_cell () { pin (Q) { @@ -31190,7 +31324,7 @@ library (sg13g2_stdcell_slow_1p35V_125C) { signal_type : test_scan_enable; } ff (IQ,IQN) { - clear : "RESET_B'"; + clear : "!RESET_B"; clocked_on : "CLK"; next_state : "D"; } @@ -31276,6 +31410,7 @@ library (sg13g2_stdcell_slow_1p35V_125C) { timing () { related_pin : "CLK"; sdf_cond : "SCE == 1'b1"; + sdf_edges : start_edge; timing_sense : non_unate; timing_type : rising_edge; when : "SCE"; @@ -31335,6 +31470,7 @@ library (sg13g2_stdcell_slow_1p35V_125C) { timing () { related_pin : "CLK"; sdf_cond : "SCE == 1'b0"; + sdf_edges : start_edge; timing_sense : non_unate; timing_type : rising_edge; when : "!SCE"; @@ -31393,6 +31529,7 @@ library (sg13g2_stdcell_slow_1p35V_125C) { } timing () { related_pin : "CLK"; + sdf_edges : start_edge; timing_sense : non_unate; timing_type : rising_edge; cell_rise (TIMING_DELAY_7x7ds1) { @@ -31450,6 +31587,7 @@ library (sg13g2_stdcell_slow_1p35V_125C) { } timing () { related_pin : "RESET_B"; + sdf_edges : start_edge; timing_sense : positive_unate; timing_type : clear; cell_fall (TIMING_DELAY_7x7ds1) { @@ -31522,7 +31660,7 @@ library (sg13g2_stdcell_slow_1p35V_125C) { "0.0183918, 0.0180703, 0.0180318, 0.0181154, 0.0184803, 0.0182311, 0.0175318", \ "0.0184547, 0.0180926, 0.0182969, 0.0184512, 0.01802, 0.0181592, 0.0176031", \ "0.0185975, 0.0181378, 0.0184294, 0.0184458, 0.0187168, 0.0183709, 0.0174106", \ - "0.0194692, 0.0189645, 0.0191422, 0.0192999, 0.0194324, 0.0193949, 0.0194586" \ + "0.0194691, 0.0189644, 0.0191421, 0.0192998, 0.0194323, 0.0193948, 0.0194585" \ ); } fall_power (POWER_7x7ds1) { @@ -31535,7 +31673,7 @@ library (sg13g2_stdcell_slow_1p35V_125C) { "0.0209675, 0.0207768, 0.0207796, 0.020728, 0.0208415, 0.0205912, 0.0193524", \ "0.0210987, 0.0207789, 0.021021, 0.0212368, 0.0211557, 0.0203807, 0.0209506", \ "0.0211185, 0.0210346, 0.021032, 0.0212248, 0.0213176, 0.0213805, 0.0204483", \ - "0.021373, 0.0211155, 0.0211788, 0.0213198, 0.0212102, 0.0214749, 0.0215547" \ + "0.0213729, 0.0211154, 0.0211787, 0.0213197, 0.0212101, 0.0214748, 0.0215546" \ ); } } @@ -31596,9 +31734,9 @@ library (sg13g2_stdcell_slow_1p35V_125C) { max_transition : 2.5074; capacitance : 0.00290398; rise_capacitance : 0.00295189; - rise_capacitance_range (0.00295189, 0.00295189); + rise_capacitance_range (0.00265571, 0.00321562); fall_capacitance : 0.00284238; - fall_capacitance_range (0.00284238, 0.00284238); + fall_capacitance_range (0.00261751, 0.00304793); timing () { related_pin : "CLK"; timing_type : min_pulse_width; @@ -31663,7 +31801,7 @@ library (sg13g2_stdcell_slow_1p35V_125C) { rise_power (passive_POWER_7x1ds1) { index_1 ("0.0186, 0.0966, 0.174, 0.3294, 0.6408, 1.263, 2.5074"); values ( \ - "0.0135185, 0.0132963, 0.0135429, 0.0145682, 0.0169262, 0.022452, 0.0341108" \ + "0.0135185, 0.0132963, 0.0135429, 0.0145682, 0.0169262, 0.022452, 0.0341109" \ ); } fall_power (passive_POWER_7x1ds1) { @@ -31722,7 +31860,7 @@ library (sg13g2_stdcell_slow_1p35V_125C) { rise_power (passive_POWER_7x1ds1) { index_1 ("0.0186, 0.0966, 0.174, 0.3294, 0.6408, 1.263, 2.5074"); values ( \ - "0.0135185, 0.0132963, 0.0135429, 0.0145682, 0.0169262, 0.022452, 0.0341108" \ + "0.0135185, 0.0132963, 0.0135429, 0.0145682, 0.0169262, 0.022452, 0.0341109" \ ); } fall_power (passive_POWER_7x1ds1) { @@ -31739,11 +31877,12 @@ library (sg13g2_stdcell_slow_1p35V_125C) { max_transition : 2.5074; capacitance : 0.00272799; rise_capacitance : 0.00277829; - rise_capacitance_range (0.00277829, 0.00277829); + rise_capacitance_range (0.00238784, 0.00311158); fall_capacitance : 0.00267769; - fall_capacitance_range (0.00267769, 0.00267769); + fall_capacitance_range (0.00236225, 0.00286338); timing () { related_pin : "CLK"; + sdf_edges : both_edges; timing_type : hold_rising; rise_constraint (CONSTRAINT_4x4) { index_1 ("0.0186, 0.51636, 1.263, 2.5074"); @@ -31768,6 +31907,7 @@ library (sg13g2_stdcell_slow_1p35V_125C) { } timing () { related_pin : "CLK"; + sdf_edges : both_edges; timing_type : setup_rising; rise_constraint (CONSTRAINT_4x4) { index_1 ("0.0186, 0.51636, 1.263, 2.5074"); @@ -31827,9 +31967,10 @@ library (sg13g2_stdcell_slow_1p35V_125C) { rise_capacitance : 0.00503256; rise_capacitance_range (0.00503256, 0.00503256); fall_capacitance : 0.00503256; - fall_capacitance_range (0.00503256, 0.00503256); + fall_capacitance_range (0.0047286, 0.00526794); timing () { related_pin : "CLK"; + sdf_edges : both_edges; timing_type : recovery_rising; rise_constraint (CONSTRAINT_4x4) { index_1 ("0.0186, 0.51636, 1.263, 2.5074"); @@ -31844,6 +31985,7 @@ library (sg13g2_stdcell_slow_1p35V_125C) { } timing () { related_pin : "CLK"; + sdf_edges : both_edges; timing_type : removal_rising; rise_constraint (CONSTRAINT_4x4) { index_1 ("0.0186, 0.51636, 1.263, 2.5074"); @@ -31873,11 +32015,12 @@ library (sg13g2_stdcell_slow_1p35V_125C) { max_transition : 2.5074; capacitance : 0.00284801; rise_capacitance : 0.00288195; - rise_capacitance_range (0.00288195, 0.00288195); + rise_capacitance_range (0.00249599, 0.00321321); fall_capacitance : 0.00278013; - fall_capacitance_range (0.00278013, 0.00278013); + fall_capacitance_range (0.00246105, 0.00296644); timing () { related_pin : "CLK"; + sdf_edges : both_edges; timing_type : hold_rising; rise_constraint (CONSTRAINT_4x4) { index_1 ("0.0186, 0.51636, 1.263, 2.5074"); @@ -31902,6 +32045,7 @@ library (sg13g2_stdcell_slow_1p35V_125C) { } timing () { related_pin : "CLK"; + sdf_edges : both_edges; timing_type : setup_rising; rise_constraint (CONSTRAINT_4x4) { index_1 ("0.0186, 0.51636, 1.263, 2.5074"); @@ -31960,11 +32104,12 @@ library (sg13g2_stdcell_slow_1p35V_125C) { max_transition : 2.5074; capacitance : 0.00465468; rise_capacitance : 0.00476863; - rise_capacitance_range (0.00476863, 0.00476863); + rise_capacitance_range (0.00429826, 0.0051453); fall_capacitance : 0.00454074; - fall_capacitance_range (0.00454074, 0.00454074); + fall_capacitance_range (0.00433555, 0.0050251); timing () { related_pin : "CLK"; + sdf_edges : both_edges; timing_type : hold_rising; rise_constraint (CONSTRAINT_4x4) { index_1 ("0.0186, 0.51636, 1.263, 2.5074"); @@ -31989,6 +32134,7 @@ library (sg13g2_stdcell_slow_1p35V_125C) { } timing () { related_pin : "CLK"; + sdf_edges : both_edges; timing_type : setup_rising; rise_constraint (CONSTRAINT_4x4) { index_1 ("0.0186, 0.51636, 1.263, 2.5074"); @@ -32057,9 +32203,9 @@ library (sg13g2_stdcell_slow_1p35V_125C) { } } ff (IQ,IQN) { - clear : "RESET_B'"; + clear : "!RESET_B"; clocked_on : "CLK"; - next_state : "(SCE*SCD)+(SCE'*D)"; + next_state : "(SCE*SCD)+(!SCE*D)"; } test_cell () { pin (Q) { @@ -32085,7 +32231,7 @@ library (sg13g2_stdcell_slow_1p35V_125C) { signal_type : test_scan_enable; } ff (IQ,IQN) { - clear : "RESET_B'"; + clear : "!RESET_B"; clocked_on : "CLK"; next_state : "D"; } @@ -32093,7 +32239,7 @@ library (sg13g2_stdcell_slow_1p35V_125C) { } cell (sg13g2_sighold) { area : 9.072; - cell_footprint : "keepstate"; + cell_footprint : "sighold"; cell_leakage_power : 875.324; dont_touch : true; dont_use : true; @@ -32131,7 +32277,7 @@ library (sg13g2_stdcell_slow_1p35V_125C) { } cell (sg13g2_slgcp_1) { area : 30.8448; - cell_footprint : "sgclk"; + cell_footprint : "slgcp"; cell_leakage_power : 3176.78; clock_gating_integrated_cell : "latch_posedge_precontrol"; dont_touch : true; @@ -32270,9 +32416,9 @@ library (sg13g2_stdcell_slow_1p35V_125C) { max_transition : 2.5074; capacitance : 0.00489823; rise_capacitance : 0.00497058; - rise_capacitance_range (0.00497058, 0.00497058); + rise_capacitance_range (0.00429652, 0.00561296); fall_capacitance : 0.00482589; - fall_capacitance_range (0.00482589, 0.00482589); + fall_capacitance_range (0.00444307, 0.00510911); timing () { related_pin : "CLK"; timing_type : min_pulse_width; @@ -32310,11 +32456,12 @@ library (sg13g2_stdcell_slow_1p35V_125C) { max_transition : 2.5074; capacitance : 0.00190553; rise_capacitance : 0.00231783; - rise_capacitance_range (0.00231783, 0.00231783); + rise_capacitance_range (0.00207033, 0.00253951); fall_capacitance : 0.00149324; - fall_capacitance_range (0.00149324, 0.00149324); + fall_capacitance_range (0.00149324, 0.00234462); timing () { related_pin : "CLK"; + sdf_edges : both_edges; timing_type : hold_rising; rise_constraint (CONSTRAINT_4x4) { index_1 ("0.0186, 0.51636, 1.263, 2.5074"); @@ -32339,6 +32486,7 @@ library (sg13g2_stdcell_slow_1p35V_125C) { } timing () { related_pin : "CLK"; + sdf_edges : both_edges; timing_type : setup_rising; rise_constraint (CONSTRAINT_4x4) { index_1 ("0.0186, 0.51636, 1.263, 2.5074"); @@ -32397,11 +32545,12 @@ library (sg13g2_stdcell_slow_1p35V_125C) { max_transition : 2.5074; capacitance : 0.00230153; rise_capacitance : 0.00225918; - rise_capacitance_range (0.00225918, 0.00225918); + rise_capacitance_range (0.00208387, 0.00241775); fall_capacitance : 0.00234389; - fall_capacitance_range (0.00234389, 0.00234389); + fall_capacitance_range (0.00212582, 0.00249822); timing () { related_pin : "CLK"; + sdf_edges : both_edges; timing_type : hold_rising; rise_constraint (CONSTRAINT_4x4) { index_1 ("0.0186, 0.51636, 1.263, 2.5074"); @@ -32426,6 +32575,7 @@ library (sg13g2_stdcell_slow_1p35V_125C) { } timing () { related_pin : "CLK"; + sdf_edges : both_edges; timing_type : setup_rising; rise_constraint (CONSTRAINT_4x4) { index_1 ("0.0186, 0.51636, 1.263, 2.5074"); @@ -32466,7 +32616,7 @@ library (sg13g2_stdcell_slow_1p35V_125C) { } cell (sg13g2_tiehi) { area : 7.2576; - cell_footprint : "tie1"; + cell_footprint : "tiehi"; cell_leakage_power : 55.1096; pin (L_HI) { direction : "output"; @@ -32476,7 +32626,7 @@ library (sg13g2_stdcell_slow_1p35V_125C) { } cell (sg13g2_tielo) { area : 7.2576; - cell_footprint : "tie0"; + cell_footprint : "tielo"; cell_leakage_power : 57.4415; pin (L_LO) { direction : "output"; @@ -32486,7 +32636,7 @@ library (sg13g2_stdcell_slow_1p35V_125C) { } cell (sg13g2_xnor2_1) { area : 14.5152; - cell_footprint : "xnor2_1"; + cell_footprint : "xnor2"; cell_leakage_power : 1366.74; leakage_power () { value : 1402.96; @@ -33043,23 +33193,23 @@ library (sg13g2_stdcell_slow_1p35V_125C) { max_transition : 2.5074; capacitance : 0.00559237; rise_capacitance : 0.00563023; - rise_capacitance_range (0.00563023, 0.00563023); + rise_capacitance_range (0.00475562, 0.00664394); fall_capacitance : 0.0055545; - fall_capacitance_range (0.0055545, 0.0055545); + fall_capacitance_range (0.00473903, 0.00638209); } pin (B) { direction : "input"; max_transition : 2.5074; capacitance : 0.0050171; rise_capacitance : 0.00505346; - rise_capacitance_range (0.00505346, 0.00505346); + rise_capacitance_range (0.00437358, 0.00586961); fall_capacitance : 0.00498075; - fall_capacitance_range (0.00498075, 0.00498075); + fall_capacitance_range (0.00431125, 0.00563863); } } cell (sg13g2_xor2_1) { area : 14.5152; - cell_footprint : "xor2_1"; + cell_footprint : "xor2"; cell_leakage_power : 1356.1; leakage_power () { value : 1079.38; @@ -33616,18 +33766,18 @@ library (sg13g2_stdcell_slow_1p35V_125C) { max_transition : 2.5074; capacitance : 0.00571342; rise_capacitance : 0.00577368; - rise_capacitance_range (0.00577368, 0.00577368); + rise_capacitance_range (0.00493923, 0.00655047); fall_capacitance : 0.00565316; - fall_capacitance_range (0.00565316, 0.00565316); + fall_capacitance_range (0.00474968, 0.0067585); } pin (B) { direction : "input"; max_transition : 2.5074; capacitance : 0.00505733; rise_capacitance : 0.00512462; - rise_capacitance_range (0.00512462, 0.00512462); + rise_capacitance_range (0.00437958, 0.00591539); fall_capacitance : 0.00499004; - fall_capacitance_range (0.00499004, 0.00499004); + fall_capacitance_range (0.00443434, 0.00559342); } } } diff --git a/flow/platforms/ihp-sg13g2/lib/sg13g2_stdcell_typ_1p20V_25C.lib b/flow/platforms/ihp-sg13g2/lib/sg13g2_stdcell_typ_1p20V_25C.lib index 9654b7cb68..6768e90d97 100644 --- a/flow/platforms/ihp-sg13g2/lib/sg13g2_stdcell_typ_1p20V_25C.lib +++ b/flow/platforms/ihp-sg13g2/lib/sg13g2_stdcell_typ_1p20V_25C.lib @@ -18,8 +18,8 @@ library (sg13g2_stdcell_typ_1p20V_25C) { comment : "IHP Microelectronics GmbH, 2025"; - date : "$Date: Fri Jun 13 15:58:39 2025 $"; - revision : "$Revision: 0.1.3 $"; + date : "$Date: Tue Nov 4 21:19:14 2025 $"; + revision : "$Revision: 0.1.4 $"; delay_model : table_lookup; capacitive_load_unit (1,pf); current_unit : "1uA"; @@ -210,7 +210,7 @@ library (sg13g2_stdcell_typ_1p20V_25C) { } cell (sg13g2_a21o_1) { area : 12.7008; - cell_footprint : "AO21"; + cell_footprint : "a21o"; cell_leakage_power : 158.296; leakage_power () { value : 163.544; @@ -483,7 +483,7 @@ library (sg13g2_stdcell_typ_1p20V_25C) { } timing () { related_pin : "B1"; - sdf_cond : "A1 == 1'b1 & A2 == 1'b0"; + sdf_cond : "A1 == 1'b1 && A2 == 1'b0"; timing_sense : positive_unate; timing_type : combinational; when : "(A1 * !A2)"; @@ -542,7 +542,7 @@ library (sg13g2_stdcell_typ_1p20V_25C) { } timing () { related_pin : "B1"; - sdf_cond : "A1 == 1'b0 & A2 == 1'b1"; + sdf_cond : "A1 == 1'b0 && A2 == 1'b1"; timing_sense : positive_unate; timing_type : combinational; when : "(!A1 * A2)"; @@ -601,7 +601,7 @@ library (sg13g2_stdcell_typ_1p20V_25C) { } timing () { related_pin : "B1"; - sdf_cond : "A1 == 1'b0 & A2 == 1'b0"; + sdf_cond : "A1 == 1'b0 && A2 == 1'b0"; timing_sense : positive_unate; timing_type : combinational; when : "(!A1 * !A2)"; @@ -958,32 +958,32 @@ library (sg13g2_stdcell_typ_1p20V_25C) { max_transition : 2.5074; capacitance : 0.00271758; rise_capacitance : 0.00270998; - rise_capacitance_range (0.00270998, 0.00270998); + rise_capacitance_range (0.00251337, 0.00285989); fall_capacitance : 0.00272519; - fall_capacitance_range (0.00272519, 0.00272519); + fall_capacitance_range (0.00238472, 0.00305468); } pin (A2) { direction : "input"; max_transition : 2.5074; capacitance : 0.00280734; rise_capacitance : 0.00285139; - rise_capacitance_range (0.00285139, 0.00285139); + rise_capacitance_range (0.00250725, 0.00312209); fall_capacitance : 0.00276328; - fall_capacitance_range (0.00276328, 0.00276328); + fall_capacitance_range (0.00247279, 0.00305635); } pin (B1) { direction : "input"; max_transition : 2.5074; capacitance : 0.00263163; rise_capacitance : 0.00269596; - rise_capacitance_range (0.00269596, 0.00269596); + rise_capacitance_range (0.00230222, 0.00296336); fall_capacitance : 0.00256731; - fall_capacitance_range (0.00256731, 0.00256731); + fall_capacitance_range (0.00232595, 0.00277741); } } cell (sg13g2_a21o_2) { area : 14.5152; - cell_footprint : "AO21"; + cell_footprint : "a21o"; cell_leakage_power : 224.289; leakage_power () { value : 250.004; @@ -1256,7 +1256,7 @@ library (sg13g2_stdcell_typ_1p20V_25C) { } timing () { related_pin : "B1"; - sdf_cond : "A1 == 1'b1 & A2 == 1'b0"; + sdf_cond : "A1 == 1'b1 && A2 == 1'b0"; timing_sense : positive_unate; timing_type : combinational; when : "(A1 * !A2)"; @@ -1315,7 +1315,7 @@ library (sg13g2_stdcell_typ_1p20V_25C) { } timing () { related_pin : "B1"; - sdf_cond : "A1 == 1'b0 & A2 == 1'b1"; + sdf_cond : "A1 == 1'b0 && A2 == 1'b1"; timing_sense : positive_unate; timing_type : combinational; when : "(!A1 * A2)"; @@ -1374,7 +1374,7 @@ library (sg13g2_stdcell_typ_1p20V_25C) { } timing () { related_pin : "B1"; - sdf_cond : "A1 == 1'b0 & A2 == 1'b0"; + sdf_cond : "A1 == 1'b0 && A2 == 1'b0"; timing_sense : positive_unate; timing_type : combinational; when : "(!A1 * !A2)"; @@ -1731,27 +1731,27 @@ library (sg13g2_stdcell_typ_1p20V_25C) { max_transition : 2.5074; capacitance : 0.00289873; rise_capacitance : 0.00286464; - rise_capacitance_range (0.00286464, 0.00286464); + rise_capacitance_range (0.00266918, 0.00303428); fall_capacitance : 0.00293283; - fall_capacitance_range (0.00293283, 0.00293283); + fall_capacitance_range (0.0025972, 0.00324686); } pin (A2) { direction : "input"; max_transition : 2.5074; capacitance : 0.00289238; rise_capacitance : 0.00291945; - rise_capacitance_range (0.00291945, 0.00291945); + rise_capacitance_range (0.00254002, 0.00321812); fall_capacitance : 0.00286531; - fall_capacitance_range (0.00286531, 0.00286531); + fall_capacitance_range (0.00257659, 0.00314741); } pin (B1) { direction : "input"; max_transition : 2.5074; capacitance : 0.00274853; rise_capacitance : 0.00279527; - rise_capacitance_range (0.00279527, 0.00279527); + rise_capacitance_range (0.00245531, 0.00307651); fall_capacitance : 0.00270179; - fall_capacitance_range (0.00270179, 0.00270179); + fall_capacitance_range (0.00249481, 0.00286991); } } cell (sg13g2_a21oi_1) { @@ -1759,15 +1759,15 @@ library (sg13g2_stdcell_typ_1p20V_25C) { cell_footprint : "a21oi"; cell_leakage_power : 114.477; leakage_power () { - value : 92.6327; + value : 92.6331; when : "!A1&!A2&!B1&Y"; } leakage_power () { - value : 124.774; + value : 124.775; when : "!A1&!A2&B1&!Y"; } leakage_power () { - value : 111.36; + value : 111.361; when : "!A1&A2&!B1&Y"; } leakage_power () { @@ -1775,11 +1775,11 @@ library (sg13g2_stdcell_typ_1p20V_25C) { when : "!A1&A2&B1&!Y"; } leakage_power () { - value : 86.9191; + value : 86.9195; when : "A1&!A2&!B1&Y"; } leakage_power () { - value : 127.867; + value : 127.868; when : "A1&!A2&B1&!Y"; } leakage_power () { @@ -1787,7 +1787,7 @@ library (sg13g2_stdcell_typ_1p20V_25C) { when : "A1&A2&!B1&!Y"; } leakage_power () { - value : 98.3622; + value : 98.3626; when : "A1&A2&B1&!Y"; } pin (Y) { @@ -1803,37 +1803,37 @@ library (sg13g2_stdcell_typ_1p20V_25C) { index_1 ("0.0186, 0.0966, 0.174, 0.3294, 0.6408, 1.263, 2.5074"); index_2 ("0.001, 0.0234, 0.039, 0.0648, 0.108, 0.18, 0.3"); values ( \ - "0.0469102, 0.178703, 0.268736, 0.417645, 0.666346, 1.08112, 1.77306", \ - "0.0726478, 0.211162, 0.301619, 0.450773, 0.700058, 1.11469, 1.80719", \ - "0.0867366, 0.238452, 0.33006, 0.479457, 0.728737, 1.14493, 1.8359", \ - "0.104241, 0.286579, 0.384197, 0.536899, 0.787412, 1.20277, 1.8944", \ - "0.123357, 0.362764, 0.476565, 0.644055, 0.90416, 1.32262, 2.015", \ - "0.142695, 0.469674, 0.613915, 0.814119, 1.10644, 1.5496, 2.25152", \ - "0.167298, 0.610371, 0.806202, 1.06678, 1.42268, 1.93598, 2.69387" \ + "0.0469064, 0.178705, 0.26874, 0.417648, 0.666251, 1.08112, 1.77306", \ + "0.0726478, 0.211163, 0.301584, 0.450604, 0.700088, 1.11469, 1.80719", \ + "0.0867366, 0.238452, 0.330056, 0.47937, 0.729031, 1.14489, 1.8359", \ + "0.104241, 0.286579, 0.384197, 0.536899, 0.787489, 1.20277, 1.89439", \ + "0.123357, 0.362764, 0.476565, 0.644054, 0.90416, 1.32263, 2.015", \ + "0.142695, 0.469674, 0.61407, 0.814118, 1.10644, 1.5496, 2.25152", \ + "0.167298, 0.610371, 0.806533, 1.06664, 1.42268, 1.93461, 2.69387" \ ); } rise_transition (TIMING_DELAY_7x7ds1) { index_1 ("0.0186, 0.0966, 0.174, 0.3294, 0.6408, 1.263, 2.5074"); index_2 ("0.001, 0.0234, 0.039, 0.0648, 0.108, 0.18, 0.3"); values ( \ - "0.0280093, 0.208594, 0.334063, 0.542172, 0.890173, 1.47019, 2.43609", \ - "0.0359959, 0.209625, 0.334497, 0.542527, 0.890174, 1.4702, 2.43712", \ - "0.045938, 0.215847, 0.337327, 0.542684, 0.8917, 1.47027, 2.43713", \ - "0.0643737, 0.237331, 0.35366, 0.551797, 0.893216, 1.47056, 2.43714", \ - "0.0999409, 0.288024, 0.40082, 0.590563, 0.917175, 1.48, 2.43887", \ - "0.16112, 0.382077, 0.499578, 0.688422, 1.00401, 1.53995, 2.46545", \ - "0.252783, 0.544952, 0.681403, 0.881527, 1.20167, 1.72535, 2.61212" \ + "0.028014, 0.208594, 0.334065, 0.542172, 0.889683, 1.4702, 2.43609", \ + "0.0359958, 0.209675, 0.334464, 0.542343, 0.890082, 1.4704, 2.43712", \ + "0.0459379, 0.215847, 0.337343, 0.543057, 0.890251, 1.47041, 2.43713", \ + "0.0643737, 0.237331, 0.353659, 0.551796, 0.892751, 1.47055, 2.43714", \ + "0.0999409, 0.288024, 0.400821, 0.590562, 0.917166, 1.47972, 2.43892", \ + "0.16112, 0.382076, 0.499747, 0.688421, 1.004, 1.53994, 2.46436", \ + "0.252783, 0.544951, 0.681683, 0.881797, 1.20167, 1.72421, 2.61212" \ ); } cell_fall (TIMING_DELAY_7x7ds1) { index_1 ("0.0186, 0.0966, 0.174, 0.3294, 0.6408, 1.263, 2.5074"); index_2 ("0.001, 0.0234, 0.039, 0.0648, 0.108, 0.18, 0.3"); values ( \ - "0.0394872, 0.134277, 0.198303, 0.303911, 0.480465, 0.77393, 1.26324", \ - "0.0686326, 0.176287, 0.240891, 0.346468, 0.522885, 0.816986, 1.30587", \ - "0.0868663, 0.213236, 0.281434, 0.38842, 0.564757, 0.85844, 1.34795", \ - "0.112125, 0.271752, 0.351187, 0.467424, 0.647851, 0.941855, 1.43065", \ - "0.147382, 0.359059, 0.459309, 0.598676, 0.801644, 1.10879, 1.59943", \ + "0.0394882, 0.134269, 0.198305, 0.303842, 0.480457, 0.774077, 1.26324", \ + "0.0686326, 0.1763, 0.240891, 0.346486, 0.522871, 0.816967, 1.30581", \ + "0.086879, 0.213236, 0.281434, 0.38842, 0.564757, 0.858453, 1.34795", \ + "0.112125, 0.271752, 0.351187, 0.467424, 0.647868, 0.941747, 1.43086", \ + "0.147382, 0.359059, 0.459309, 0.598676, 0.801635, 1.10879, 1.59937", \ "0.194549, 0.483526, 0.615471, 0.796653, 1.04631, 1.40214, 1.92879", \ "0.256659, 0.649864, 0.832757, 1.07519, 1.40579, 1.85542, 2.48437" \ ); @@ -1842,13 +1842,13 @@ library (sg13g2_stdcell_typ_1p20V_25C) { index_1 ("0.0186, 0.0966, 0.174, 0.3294, 0.6408, 1.263, 2.5074"); index_2 ("0.001, 0.0234, 0.039, 0.0648, 0.108, 0.18, 0.3"); values ( \ - "0.0274876, 0.149777, 0.234927, 0.375555, 0.611035, 1.00293, 1.65592", \ - "0.0415788, 0.155418, 0.237113, 0.37579, 0.611036, 1.0036, 1.65706", \ - "0.0548603, 0.170968, 0.248337, 0.381608, 0.611921, 1.00361, 1.65707", \ - "0.0773115, 0.206689, 0.282838, 0.408011, 0.625978, 1.00656, 1.65708", \ - "0.112091, 0.272714, 0.352869, 0.479862, 0.687608, 1.04475, 1.66909", \ - "0.165531, 0.380297, 0.478566, 0.617186, 0.834686, 1.18014, 1.76632", \ - "0.248449, 0.556556, 0.681141, 0.854079, 1.09934, 1.47321, 2.04897" \ + "0.0275017, 0.149776, 0.23493, 0.375547, 0.611035, 1.00329, 1.65592", \ + "0.0415794, 0.155383, 0.237113, 0.375548, 0.611036, 1.00359, 1.65701", \ + "0.0548684, 0.170968, 0.248337, 0.381608, 0.611921, 1.0036, 1.65702", \ + "0.0773116, 0.206689, 0.282838, 0.40801, 0.626243, 1.00655, 1.65703", \ + "0.112091, 0.272714, 0.352869, 0.479862, 0.687616, 1.04475, 1.67045", \ + "0.165531, 0.380297, 0.478566, 0.617186, 0.834685, 1.18014, 1.76617", \ + "0.248449, 0.556556, 0.681142, 0.854082, 1.09934, 1.47321, 2.04897" \ ); } } @@ -1860,37 +1860,37 @@ library (sg13g2_stdcell_typ_1p20V_25C) { index_1 ("0.0186, 0.0966, 0.174, 0.3294, 0.6408, 1.263, 2.5074"); index_2 ("0.001, 0.0234, 0.039, 0.0648, 0.108, 0.18, 0.3"); values ( \ - "0.0549455, 0.186451, 0.276798, 0.42621, 0.675843, 1.09195, 1.7847", \ - "0.0831245, 0.219637, 0.310125, 0.459486, 0.709508, 1.12567, 1.81979", \ - "0.100136, 0.247476, 0.338835, 0.488364, 0.738427, 1.15533, 1.84734", \ - "0.12236, 0.296557, 0.393826, 0.546295, 0.796906, 1.21322, 1.90683", \ - "0.149599, 0.375366, 0.487611, 0.654506, 0.914106, 1.33362, 2.02739", \ - "0.180584, 0.486707, 0.627909, 0.826543, 1.11728, 1.56075, 2.26428", \ - "0.221985, 0.635455, 0.826465, 1.08257, 1.43728, 1.94731, 2.70578" \ + "0.0549386, 0.186469, 0.276792, 0.42621, 0.67555, 1.09194, 1.78468", \ + "0.0831206, 0.219608, 0.310123, 0.459586, 0.709506, 1.12565, 1.8198", \ + "0.100136, 0.247475, 0.338834, 0.488364, 0.738257, 1.15531, 1.84761", \ + "0.12236, 0.296556, 0.393826, 0.546295, 0.796932, 1.21327, 1.90683", \ + "0.149599, 0.375366, 0.487611, 0.654505, 0.914106, 1.33362, 2.02739", \ + "0.180584, 0.486707, 0.627908, 0.826543, 1.11728, 1.56075, 2.26428", \ + "0.221985, 0.635455, 0.826465, 1.08257, 1.43728, 1.9473, 2.70578" \ ); } rise_transition (TIMING_DELAY_7x7ds1) { index_1 ("0.0186, 0.0966, 0.174, 0.3294, 0.6408, 1.263, 2.5074"); index_2 ("0.001, 0.0234, 0.039, 0.0648, 0.108, 0.18, 0.3"); values ( \ - "0.0357321, 0.217439, 0.34365, 0.552303, 0.901117, 1.48276, 2.45133", \ - "0.0427615, 0.218316, 0.343788, 0.553246, 0.901213, 1.4833, 2.45218", \ - "0.0522788, 0.224215, 0.346572, 0.553725, 0.901258, 1.48416, 2.45219", \ - "0.0710461, 0.244677, 0.362296, 0.561645, 0.903743, 1.48417, 2.45276", \ - "0.106601, 0.294621, 0.40872, 0.599758, 0.927834, 1.49279, 2.45484", \ - "0.165278, 0.387944, 0.506895, 0.696117, 1.01334, 1.55191, 2.48", \ - "0.251402, 0.547031, 0.685014, 0.888705, 1.2107, 1.7359, 2.62323" \ + "0.0357322, 0.217445, 0.34341, 0.552303, 0.901322, 1.48276, 2.45133", \ + "0.0427609, 0.218335, 0.34444, 0.552304, 0.901323, 1.4833, 2.45218", \ + "0.0522787, 0.224215, 0.346569, 0.553724, 0.902388, 1.48414, 2.45276", \ + "0.0710461, 0.244677, 0.362295, 0.561644, 0.90387, 1.48415, 2.45277", \ + "0.106601, 0.294621, 0.408719, 0.599757, 0.927833, 1.49278, 2.45484", \ + "0.165278, 0.387944, 0.506895, 0.696116, 1.01334, 1.55191, 2.48", \ + "0.251403, 0.547031, 0.685014, 0.888705, 1.2107, 1.73589, 2.62323" \ ); } cell_fall (TIMING_DELAY_7x7ds1) { index_1 ("0.0186, 0.0966, 0.174, 0.3294, 0.6408, 1.263, 2.5074"); index_2 ("0.001, 0.0234, 0.039, 0.0648, 0.108, 0.18, 0.3"); values ( \ - "0.0437264, 0.138243, 0.202253, 0.307777, 0.484323, 0.777835, 1.26719", \ - "0.0725252, 0.175583, 0.240124, 0.345771, 0.522307, 0.816419, 1.30523", \ - "0.0914559, 0.207923, 0.275062, 0.381905, 0.558629, 0.85247, 1.34211", \ - "0.117786, 0.261257, 0.336195, 0.449849, 0.629933, 0.924408, 1.41415", \ - "0.153592, 0.344823, 0.436272, 0.566693, 0.762833, 1.06775, 1.55973", \ + "0.0437283, 0.138244, 0.202252, 0.307785, 0.484329, 0.777916, 1.26719", \ + "0.0725252, 0.175583, 0.240124, 0.345772, 0.522306, 0.816419, 1.30523", \ + "0.0914559, 0.207923, 0.275062, 0.381905, 0.558624, 0.852469, 1.34211", \ + "0.117786, 0.261257, 0.336194, 0.449849, 0.629934, 0.924408, 1.41417", \ + "0.153592, 0.344823, 0.436271, 0.566693, 0.762857, 1.06775, 1.5596", \ "0.200996, 0.46861, 0.587389, 0.752247, 0.983912, 1.32493, 1.84301", \ "0.265774, 0.637842, 0.805929, 1.027, 1.32473, 1.73945, 2.33171" \ ); @@ -1899,11 +1899,11 @@ library (sg13g2_stdcell_typ_1p20V_25C) { index_1 ("0.0186, 0.0966, 0.174, 0.3294, 0.6408, 1.263, 2.5074"); index_2 ("0.001, 0.0234, 0.039, 0.0648, 0.108, 0.18, 0.3"); values ( \ - "0.0272443, 0.149819, 0.234903, 0.375322, 0.61108, 1.00247, 1.65592", \ - "0.0360099, 0.153249, 0.236417, 0.375808, 0.611081, 1.00358, 1.65593", \ - "0.0461232, 0.163277, 0.243459, 0.379141, 0.611972, 1.00359, 1.65594", \ - "0.0659485, 0.187913, 0.266687, 0.396789, 0.621545, 1.00527, 1.65595", \ - "0.0996628, 0.238971, 0.317513, 0.446672, 0.662742, 1.03061, 1.66685", \ + "0.027242, 0.149819, 0.234901, 0.375324, 0.611081, 1.00293, 1.65592", \ + "0.0360098, 0.153249, 0.236417, 0.375808, 0.611082, 1.00358, 1.65593", \ + "0.0461233, 0.163276, 0.243458, 0.379141, 0.611931, 1.00359, 1.65594", \ + "0.0659485, 0.187913, 0.266688, 0.396789, 0.6215, 1.00527, 1.65595", \ + "0.0996628, 0.238971, 0.317513, 0.446672, 0.662844, 1.03061, 1.66656", \ "0.1536, 0.329398, 0.418645, 0.54985, 0.767244, 1.12278, 1.72981", \ "0.233057, 0.487225, 0.593607, 0.743632, 0.972433, 1.33523, 1.92801" \ ); @@ -1919,38 +1919,38 @@ library (sg13g2_stdcell_typ_1p20V_25C) { index_1 ("0.0186, 0.0966, 0.174, 0.3294, 0.6408, 1.263, 2.5074"); index_2 ("0.001, 0.0234, 0.039, 0.0648, 0.108, 0.18, 0.3"); values ( \ - "0.0442518, 0.177882, 0.26846, 0.41776, 0.667508, 1.08338, 1.7764", \ - "0.0714742, 0.213119, 0.303945, 0.453705, 0.703854, 1.11994, 1.81422", \ - "0.0880628, 0.246723, 0.338496, 0.488213, 0.738568, 1.15557, 1.84807", \ - "0.110441, 0.306734, 0.407092, 0.56081, 0.811394, 1.22783, 1.92065", \ - "0.141166, 0.397947, 0.520893, 0.695059, 0.958079, 1.3774, 2.0701", \ - "0.181362, 0.523613, 0.681658, 0.900786, 1.2082, 1.66193, 2.36418", \ - "0.233712, 0.687653, 0.901985, 1.1898, 1.58521, 2.13159, 2.91669" \ + "0.0442554, 0.177888, 0.268457, 0.41776, 0.667509, 1.08331, 1.77711", \ + "0.0714742, 0.213119, 0.303946, 0.453583, 0.703853, 1.11994, 1.81422", \ + "0.0880628, 0.246726, 0.338474, 0.48821, 0.738588, 1.15558, 1.84808", \ + "0.110441, 0.306734, 0.407091, 0.560809, 0.811393, 1.22782, 1.9209", \ + "0.141166, 0.397947, 0.520893, 0.695058, 0.958078, 1.3774, 2.07014", \ + "0.181362, 0.523613, 0.681657, 0.900785, 1.2082, 1.662, 2.36418", \ + "0.233712, 0.687652, 0.901985, 1.1898, 1.58521, 2.13159, 2.91669" \ ); } rise_transition (TIMING_DELAY_7x7ds1) { index_1 ("0.0186, 0.0966, 0.174, 0.3294, 0.6408, 1.263, 2.5074"); index_2 ("0.001, 0.0234, 0.039, 0.0648, 0.108, 0.18, 0.3"); values ( \ - "0.0357109, 0.217512, 0.343715, 0.55222, 0.901382, 1.48269, 2.45134", \ - "0.0495596, 0.219319, 0.344286, 0.552644, 0.90163, 1.48344, 2.45302", \ - "0.0632021, 0.229637, 0.34881, 0.553192, 0.901631, 1.48408, 2.45303", \ - "0.085017, 0.262477, 0.374686, 0.567762, 0.906116, 1.48409, 2.45304", \ - "0.11961, 0.332235, 0.444255, 0.62744, 0.943752, 1.49871, 2.45452", \ - "0.174133, 0.447029, 0.576909, 0.76728, 1.07473, 1.58927, 2.49613", \ - "0.263089, 0.629704, 0.790418, 1.0185, 1.34901, 1.8652, 2.71645" \ + "0.0357169, 0.217514, 0.343715, 0.552219, 0.901381, 1.48327, 2.452", \ + "0.0495596, 0.219319, 0.344096, 0.552821, 0.901629, 1.48344, 2.45301", \ + "0.0632021, 0.229641, 0.348803, 0.554155, 0.90163, 1.48411, 2.45302", \ + "0.0850171, 0.262477, 0.374686, 0.567761, 0.906115, 1.48412, 2.45303", \ + "0.11961, 0.332236, 0.444255, 0.627439, 0.943751, 1.49871, 2.45561", \ + "0.174133, 0.447028, 0.576909, 0.76728, 1.07473, 1.58928, 2.49613", \ + "0.263089, 0.629704, 0.790418, 1.0185, 1.34901, 1.8652, 2.71644" \ ); } cell_fall (TIMING_DELAY_7x7ds1) { index_1 ("0.0186, 0.0966, 0.174, 0.3294, 0.6408, 1.263, 2.5074"); index_2 ("0.001, 0.0234, 0.039, 0.0648, 0.108, 0.18, 0.3"); values ( \ - "0.0222611, 0.0743531, 0.10908, 0.166455, 0.262454, 0.422416, 0.68893", \ - "0.0440485, 0.120523, 0.158282, 0.216673, 0.31273, 0.47274, 0.739557", \ - "0.0556424, 0.155019, 0.199287, 0.263072, 0.361697, 0.521813, 0.78804", \ - "0.0705636, 0.206756, 0.263456, 0.340963, 0.451861, 0.618426, 0.885465", \ - "0.0902977, 0.282609, 0.35997, 0.462048, 0.600134, 0.793414, 1.07854", \ - "0.11463, 0.387467, 0.498386, 0.638619, 0.826027, 1.07259, 1.41312", \ + "0.0222611, 0.0743898, 0.109075, 0.166454, 0.262456, 0.422411, 0.688926", \ + "0.0440485, 0.120523, 0.158282, 0.216673, 0.312723, 0.47274, 0.739588", \ + "0.0556424, 0.155019, 0.199287, 0.263072, 0.361697, 0.521813, 0.788046", \ + "0.0705636, 0.206764, 0.263456, 0.340949, 0.451692, 0.618426, 0.885516", \ + "0.0902977, 0.282609, 0.359972, 0.462048, 0.600134, 0.793414, 1.07854", \ + "0.11463, 0.387468, 0.498386, 0.638619, 0.826028, 1.07259, 1.41312", \ "0.142128, 0.521548, 0.682962, 0.887897, 1.14802, 1.48885, 1.93339" \ ); } @@ -1958,13 +1958,13 @@ library (sg13g2_stdcell_typ_1p20V_25C) { index_1 ("0.0186, 0.0966, 0.174, 0.3294, 0.6408, 1.263, 2.5074"); index_2 ("0.001, 0.0234, 0.039, 0.0648, 0.108, 0.18, 0.3"); values ( \ - "0.0144513, 0.0820604, 0.128873, 0.206442, 0.336428, 0.553223, 0.913998", \ - "0.0352147, 0.0954158, 0.137367, 0.210293, 0.337289, 0.553224, 0.914751", \ - "0.0510494, 0.115493, 0.156301, 0.224643, 0.345028, 0.555107, 0.914752", \ - "0.0759073, 0.15287, 0.196394, 0.264287, 0.377052, 0.573535, 0.919712", \ - "0.115361, 0.21817, 0.267525, 0.34219, 0.457915, 0.644933, 0.966149", \ - "0.178117, 0.326697, 0.389728, 0.479383, 0.609279, 0.806627, 1.11897", \ - "0.278587, 0.500398, 0.592329, 0.707496, 0.871053, 1.09616, 1.43998" \ + "0.0144513, 0.0820632, 0.128864, 0.206442, 0.336428, 0.552968, 0.913992", \ + "0.0352147, 0.0954158, 0.137367, 0.210293, 0.337215, 0.552969, 0.914756", \ + "0.0510493, 0.115493, 0.156301, 0.224643, 0.345028, 0.555116, 0.914757", \ + "0.0759073, 0.152867, 0.196394, 0.264301, 0.377104, 0.573535, 0.92027", \ + "0.115361, 0.21817, 0.267483, 0.34219, 0.457916, 0.644933, 0.966149", \ + "0.178117, 0.326696, 0.389728, 0.479383, 0.609279, 0.806627, 1.11897", \ + "0.278587, 0.500398, 0.592329, 0.707496, 0.869374, 1.09616, 1.43998" \ ); } } @@ -1978,25 +1978,25 @@ library (sg13g2_stdcell_typ_1p20V_25C) { index_1 ("0.0186, 0.0966, 0.174, 0.3294, 0.6408, 1.263, 2.5074"); index_2 ("0.001, 0.0234, 0.039, 0.0648, 0.108, 0.18, 0.3"); values ( \ - "0.0348909, 0.167718, 0.258112, 0.406761, 0.655618, 1.07072, 1.76149", \ - "0.0579761, 0.202953, 0.293426, 0.442548, 0.692022, 1.10702, 1.79847", \ - "0.0704921, 0.236218, 0.327939, 0.477173, 0.726802, 1.1427, 1.83321", \ - "0.0875357, 0.294693, 0.395887, 0.54966, 0.799645, 1.21453, 1.90582", \ - "0.110422, 0.382722, 0.507462, 0.682888, 0.946024, 1.36431, 2.05533", \ - "0.140361, 0.503316, 0.664675, 0.885836, 1.19465, 1.64854, 2.34921", \ - "0.179033, 0.660231, 0.879105, 1.17047, 1.56828, 2.1158, 2.90085" \ + "0.0348888, 0.167685, 0.258112, 0.406761, 0.655619, 1.07073, 1.76143", \ + "0.0579761, 0.202953, 0.293419, 0.442692, 0.692023, 1.10702, 1.79939", \ + "0.0704921, 0.236218, 0.327966, 0.477212, 0.72675, 1.14268, 1.83321", \ + "0.0875357, 0.294686, 0.395887, 0.54966, 0.799644, 1.21453, 1.90582", \ + "0.110422, 0.382721, 0.507462, 0.682889, 0.946023, 1.36431, 2.05543", \ + "0.140361, 0.503315, 0.664675, 0.885836, 1.19465, 1.64854, 2.34928", \ + "0.179033, 0.660231, 0.879104, 1.17047, 1.56828, 2.11579, 2.90085" \ ); } rise_transition (TIMING_DELAY_7x7ds1) { index_1 ("0.0186, 0.0966, 0.174, 0.3294, 0.6408, 1.263, 2.5074"); index_2 ("0.001, 0.0234, 0.039, 0.0648, 0.108, 0.18, 0.3"); values ( \ - "0.0281238, 0.208623, 0.334332, 0.541967, 0.889817, 1.46971, 2.4356", \ - "0.044277, 0.210918, 0.334668, 0.542408, 0.889849, 1.47034, 2.43701", \ - "0.0567686, 0.222144, 0.339991, 0.54342, 0.89031, 1.47035, 2.43702", \ - "0.0766449, 0.256079, 0.366965, 0.558626, 0.895356, 1.47036, 2.43703", \ - "0.10889, 0.325927, 0.43761, 0.619318, 0.933626, 1.48561, 2.44101", \ - "0.16082, 0.440032, 0.569576, 0.759096, 1.06517, 1.57782, 2.48065", \ + "0.0281258, 0.208602, 0.334332, 0.541967, 0.890116, 1.46971, 2.43679", \ + "0.044277, 0.210918, 0.334654, 0.542008, 0.890117, 1.47034, 2.43705", \ + "0.0567686, 0.222144, 0.3401, 0.543221, 0.890118, 1.47035, 2.43706", \ + "0.0766448, 0.256121, 0.366924, 0.558626, 0.895356, 1.47036, 2.43707", \ + "0.10889, 0.325878, 0.437611, 0.619271, 0.933625, 1.48561, 2.43864", \ + "0.16082, 0.440032, 0.569575, 0.759096, 1.06517, 1.57782, 2.47981", \ "0.247808, 0.622489, 0.784306, 1.01186, 1.33956, 1.8536, 2.70238" \ ); } @@ -2004,26 +2004,26 @@ library (sg13g2_stdcell_typ_1p20V_25C) { index_1 ("0.0186, 0.0966, 0.174, 0.3294, 0.6408, 1.263, 2.5074"); index_2 ("0.001, 0.0234, 0.039, 0.0648, 0.108, 0.18, 0.3"); values ( \ - "0.0220076, 0.0740798, 0.108722, 0.165981, 0.261821, 0.421724, 0.687672", \ - "0.043455, 0.120162, 0.157816, 0.216252, 0.312125, 0.471748, 0.737958", \ - "0.0548216, 0.154572, 0.198809, 0.262576, 0.361161, 0.520958, 0.787014", \ - "0.0691027, 0.206056, 0.262823, 0.340268, 0.45115, 0.617444, 0.884455", \ - "0.0877179, 0.281373, 0.358934, 0.461125, 0.599136, 0.792343, 1.07721", \ + "0.0220076, 0.074069, 0.108721, 0.165982, 0.261822, 0.421666, 0.687668", \ + "0.043455, 0.120162, 0.157809, 0.216253, 0.312132, 0.471707, 0.737965", \ + "0.0548216, 0.154572, 0.198809, 0.262576, 0.361161, 0.520995, 0.786865", \ + "0.0691027, 0.20606, 0.26279, 0.340254, 0.45115, 0.617581, 0.884454", \ + "0.0877179, 0.281373, 0.358934, 0.461125, 0.599136, 0.792344, 1.07721", \ "0.109696, 0.385136, 0.496201, 0.636855, 0.824402, 1.07099, 1.4118", \ - "0.131628, 0.516101, 0.678728, 0.884478, 1.14457, 1.48647, 1.93109" \ + "0.131628, 0.5161, 0.678728, 0.884478, 1.14457, 1.48647, 1.93109" \ ); } fall_transition (TIMING_DELAY_7x7ds1) { index_1 ("0.0186, 0.0966, 0.174, 0.3294, 0.6408, 1.263, 2.5074"); index_2 ("0.001, 0.0234, 0.039, 0.0648, 0.108, 0.18, 0.3"); values ( \ - "0.0115401, 0.0769274, 0.123897, 0.201489, 0.331509, 0.548196, 0.909342", \ - "0.0265927, 0.0901544, 0.132343, 0.205368, 0.332331, 0.548197, 0.909343", \ - "0.0382118, 0.109941, 0.151184, 0.219722, 0.340482, 0.550604, 0.909344", \ - "0.05737, 0.14618, 0.190775, 0.259228, 0.372201, 0.568994, 0.914875", \ - "0.0880768, 0.209079, 0.261354, 0.336524, 0.452605, 0.640151, 0.961327", \ - "0.137609, 0.314739, 0.380112, 0.472162, 0.602527, 0.802602, 1.11415", \ - "0.219754, 0.482185, 0.579492, 0.696431, 0.863771, 1.09011, 1.43545" \ + "0.0115401, 0.0769743, 0.123807, 0.201489, 0.331509, 0.548223, 0.909342", \ + "0.0265926, 0.0901544, 0.132333, 0.205368, 0.33231, 0.548224, 0.909343", \ + "0.0382119, 0.109941, 0.151184, 0.219722, 0.340482, 0.550385, 0.909344", \ + "0.05737, 0.146177, 0.190593, 0.259237, 0.372201, 0.568767, 0.914957", \ + "0.0880767, 0.209079, 0.261354, 0.336524, 0.452605, 0.640151, 0.961326", \ + "0.137609, 0.314739, 0.380112, 0.472161, 0.602527, 0.802602, 1.11415", \ + "0.219734, 0.482184, 0.579491, 0.696431, 0.863771, 1.09011, 1.43545" \ ); } } @@ -2037,52 +2037,52 @@ library (sg13g2_stdcell_typ_1p20V_25C) { index_1 ("0.0186, 0.0966, 0.174, 0.3294, 0.6408, 1.263, 2.5074"); index_2 ("0.001, 0.0234, 0.039, 0.0648, 0.108, 0.18, 0.3"); values ( \ - "0.0288189, 0.12711, 0.193024, 0.302723, 0.486375, 0.79161, 1.30081", \ - "0.0513026, 0.165681, 0.232612, 0.34238, 0.525873, 0.831473, 1.3414", \ - "0.0627873, 0.199967, 0.269874, 0.380433, 0.564031, 0.870212, 1.37943", \ - "0.0783837, 0.256555, 0.338059, 0.456978, 0.64362, 0.949544, 1.46539", \ - "0.0980437, 0.339677, 0.444522, 0.588387, 0.79532, 1.11119, 1.62149", \ + "0.0288214, 0.12711, 0.193023, 0.302723, 0.48637, 0.791566, 1.30082", \ + "0.0513025, 0.165683, 0.232612, 0.342349, 0.525856, 0.831498, 1.34144", \ + "0.0627873, 0.199967, 0.269853, 0.38044, 0.563961, 0.870231, 1.37942", \ + "0.0783837, 0.256555, 0.338059, 0.456979, 0.64367, 0.949582, 1.46539", \ + "0.0980437, 0.339677, 0.444522, 0.588387, 0.795319, 1.11119, 1.62146", \ "0.122079, 0.449842, 0.59242, 0.78021, 1.03726, 1.39906, 1.93707", \ - "0.150003, 0.591184, 0.78771, 1.04663, 1.38736, 1.8511, 2.48663" \ + "0.150003, 0.591184, 0.787709, 1.04663, 1.38736, 1.8511, 2.48663" \ ); } rise_transition (TIMING_DELAY_7x7ds1) { index_1 ("0.0186, 0.0966, 0.174, 0.3294, 0.6408, 1.263, 2.5074"); index_2 ("0.001, 0.0234, 0.039, 0.0648, 0.108, 0.18, 0.3"); values ( \ - "0.0207249, 0.155431, 0.248976, 0.404386, 0.664604, 1.09803, 1.82051", \ - "0.0377938, 0.159746, 0.250557, 0.404411, 0.664605, 1.09804, 1.82063", \ - "0.0501168, 0.174697, 0.259679, 0.408027, 0.664675, 1.09818, 1.82064", \ - "0.0695317, 0.212036, 0.292984, 0.431513, 0.675857, 1.10295, 1.82701", \ - "0.101192, 0.282359, 0.368013, 0.502691, 0.73076, 1.1307, 1.82939", \ - "0.151444, 0.394928, 0.499788, 0.648796, 0.876972, 1.25377, 1.90259", \ - "0.236042, 0.572136, 0.712834, 0.894594, 1.15814, 1.54795, 2.17627" \ + "0.0207246, 0.155431, 0.248976, 0.404386, 0.664603, 1.09803, 1.82051", \ + "0.0377937, 0.159751, 0.250557, 0.404387, 0.664604, 1.09804, 1.8208", \ + "0.0501168, 0.174697, 0.259716, 0.408028, 0.664823, 1.0982, 1.82081", \ + "0.0695317, 0.212036, 0.292984, 0.431505, 0.675826, 1.10296, 1.82701", \ + "0.101192, 0.282359, 0.368013, 0.50269, 0.73076, 1.1307, 1.82949", \ + "0.151444, 0.394933, 0.499788, 0.648796, 0.876972, 1.25377, 1.90259", \ + "0.236042, 0.572136, 0.712834, 0.894595, 1.15814, 1.54795, 2.17627" \ ); } cell_fall (TIMING_DELAY_7x7ds1) { index_1 ("0.0186, 0.0966, 0.174, 0.3294, 0.6408, 1.263, 2.5074"); index_2 ("0.001, 0.0234, 0.039, 0.0648, 0.108, 0.18, 0.3"); values ( \ - "0.021769, 0.0738733, 0.108536, 0.165803, 0.261648, 0.421333, 0.687607", \ - "0.0430767, 0.119863, 0.157532, 0.215956, 0.311859, 0.471527, 0.73765", \ + "0.0217759, 0.0738725, 0.108536, 0.1658, 0.261649, 0.421387, 0.687608", \ + "0.0430767, 0.119863, 0.157533, 0.215956, 0.311877, 0.47158, 0.737654", \ "0.0545781, 0.15418, 0.19842, 0.26224, 0.360827, 0.520694, 0.78678", \ - "0.069285, 0.205565, 0.262448, 0.339939, 0.450651, 0.617238, 0.883991", \ + "0.069285, 0.205565, 0.262392, 0.339939, 0.450828, 0.617142, 0.88406", \ "0.0889091, 0.281218, 0.358557, 0.460662, 0.598772, 0.792063, 1.07689", \ "0.11335, 0.385876, 0.496437, 0.636589, 0.824159, 1.07085, 1.41118", \ - "0.141389, 0.520368, 0.681012, 0.886031, 1.14516, 1.4865, 1.93077" \ + "0.141389, 0.520367, 0.681012, 0.886031, 1.14516, 1.48651, 1.93077" \ ); } fall_transition (TIMING_DELAY_7x7ds1) { index_1 ("0.0186, 0.0966, 0.174, 0.3294, 0.6408, 1.263, 2.5074"); index_2 ("0.001, 0.0234, 0.039, 0.0648, 0.108, 0.18, 0.3"); values ( \ - "0.0116018, 0.0769359, 0.123887, 0.201489, 0.331509, 0.548195, 0.909351", \ - "0.0269417, 0.0902835, 0.132381, 0.205413, 0.332346, 0.548196, 0.909352", \ - "0.0385526, 0.110069, 0.151439, 0.219788, 0.340222, 0.550308, 0.909353", \ - "0.0572154, 0.146312, 0.190903, 0.259424, 0.372276, 0.569282, 0.915777", \ - "0.0873507, 0.208989, 0.26162, 0.336415, 0.45287, 0.64023, 0.961386", \ - "0.136016, 0.31389, 0.379271, 0.47249, 0.602793, 0.80269, 1.11444", \ - "0.216514, 0.478781, 0.577045, 0.694513, 0.863248, 1.08921, 1.43783" \ + "0.0116103, 0.0769361, 0.12389, 0.201489, 0.331509, 0.548614, 0.909351", \ + "0.0269417, 0.0902835, 0.132381, 0.205413, 0.332366, 0.548615, 0.909352", \ + "0.0385526, 0.11007, 0.151439, 0.219788, 0.340222, 0.550309, 0.909353", \ + "0.0572154, 0.146312, 0.190926, 0.259425, 0.372414, 0.569219, 0.915845", \ + "0.0873507, 0.208989, 0.26162, 0.336379, 0.452871, 0.640231, 0.961386", \ + "0.136016, 0.31389, 0.37927, 0.47249, 0.602793, 0.802691, 1.11444", \ + "0.216514, 0.478783, 0.577045, 0.694513, 0.863249, 1.08921, 1.43782" \ ); } } @@ -2094,38 +2094,38 @@ library (sg13g2_stdcell_typ_1p20V_25C) { index_1 ("0.0186, 0.0966, 0.174, 0.3294, 0.6408, 1.263, 2.5074"); index_2 ("0.001, 0.0234, 0.039, 0.0648, 0.108, 0.18, 0.3"); values ( \ - "0.0442518, 0.177882, 0.26846, 0.41776, 0.667508, 1.08338, 1.7764", \ - "0.0714742, 0.213119, 0.303945, 0.453705, 0.703854, 1.11994, 1.81422", \ - "0.0880628, 0.246723, 0.338496, 0.488213, 0.738568, 1.15557, 1.84807", \ - "0.110441, 0.306734, 0.407092, 0.56081, 0.811394, 1.22783, 1.92065", \ - "0.141166, 0.397947, 0.520893, 0.695059, 0.958079, 1.3774, 2.0701", \ - "0.181362, 0.523613, 0.681658, 0.900786, 1.2082, 1.66193, 2.36418", \ - "0.233712, 0.687653, 0.901985, 1.1898, 1.58521, 2.13159, 2.91669" \ + "0.0442554, 0.177888, 0.268457, 0.41776, 0.667509, 1.08331, 1.77711", \ + "0.0714742, 0.213119, 0.303946, 0.453583, 0.703853, 1.11994, 1.81422", \ + "0.0880628, 0.246726, 0.338474, 0.48821, 0.738588, 1.15558, 1.84808", \ + "0.110441, 0.306734, 0.407091, 0.560809, 0.811393, 1.22782, 1.9209", \ + "0.141166, 0.397947, 0.520893, 0.695058, 0.958078, 1.3774, 2.07014", \ + "0.181362, 0.523613, 0.681657, 0.900785, 1.2082, 1.662, 2.36418", \ + "0.233712, 0.687652, 0.901985, 1.1898, 1.58521, 2.13159, 2.91669" \ ); } rise_transition (TIMING_DELAY_7x7ds1) { index_1 ("0.0186, 0.0966, 0.174, 0.3294, 0.6408, 1.263, 2.5074"); index_2 ("0.001, 0.0234, 0.039, 0.0648, 0.108, 0.18, 0.3"); values ( \ - "0.0357109, 0.217512, 0.343715, 0.55222, 0.901382, 1.48269, 2.45134", \ - "0.0495596, 0.219319, 0.344286, 0.552644, 0.90163, 1.48344, 2.45302", \ - "0.0632021, 0.229637, 0.34881, 0.553192, 0.901631, 1.48408, 2.45303", \ - "0.085017, 0.262477, 0.374686, 0.567762, 0.906116, 1.48409, 2.45304", \ - "0.11961, 0.332235, 0.444255, 0.62744, 0.943752, 1.49871, 2.45452", \ - "0.174133, 0.447029, 0.576909, 0.76728, 1.07473, 1.58927, 2.49613", \ - "0.263089, 0.629704, 0.790418, 1.0185, 1.34901, 1.8652, 2.71645" \ + "0.0357169, 0.217514, 0.343715, 0.552219, 0.901381, 1.48327, 2.452", \ + "0.0495596, 0.219319, 0.344096, 0.552821, 0.901629, 1.48344, 2.45301", \ + "0.0632021, 0.229641, 0.348803, 0.554155, 0.90163, 1.48411, 2.45302", \ + "0.0850171, 0.262477, 0.374686, 0.567761, 0.906115, 1.48412, 2.45303", \ + "0.11961, 0.332236, 0.444255, 0.627439, 0.943751, 1.49871, 2.45561", \ + "0.174133, 0.447028, 0.576909, 0.76728, 1.07473, 1.58928, 2.49613", \ + "0.263089, 0.629704, 0.790418, 1.0185, 1.34901, 1.8652, 2.71644" \ ); } cell_fall (TIMING_DELAY_7x7ds1) { index_1 ("0.0186, 0.0966, 0.174, 0.3294, 0.6408, 1.263, 2.5074"); index_2 ("0.001, 0.0234, 0.039, 0.0648, 0.108, 0.18, 0.3"); values ( \ - "0.0222611, 0.0743531, 0.10908, 0.166455, 0.262454, 0.422416, 0.68893", \ - "0.0440485, 0.120523, 0.158282, 0.216673, 0.31273, 0.47274, 0.739557", \ - "0.0556424, 0.155019, 0.199287, 0.263072, 0.361697, 0.521813, 0.78804", \ - "0.0705636, 0.206756, 0.263456, 0.340963, 0.451861, 0.618426, 0.885465", \ - "0.0902977, 0.282609, 0.35997, 0.462048, 0.600134, 0.793414, 1.07854", \ - "0.11463, 0.387467, 0.498386, 0.638619, 0.826027, 1.07259, 1.41312", \ + "0.0222611, 0.0743898, 0.109075, 0.166454, 0.262456, 0.422411, 0.688926", \ + "0.0440485, 0.120523, 0.158282, 0.216673, 0.312723, 0.47274, 0.739588", \ + "0.0556424, 0.155019, 0.199287, 0.263072, 0.361697, 0.521813, 0.788046", \ + "0.0705636, 0.206764, 0.263456, 0.340949, 0.451692, 0.618426, 0.885516", \ + "0.0902977, 0.282609, 0.359972, 0.462048, 0.600134, 0.793414, 1.07854", \ + "0.11463, 0.387468, 0.498386, 0.638619, 0.826028, 1.07259, 1.41312", \ "0.142128, 0.521548, 0.682962, 0.887897, 1.14802, 1.48885, 1.93339" \ ); } @@ -2133,13 +2133,13 @@ library (sg13g2_stdcell_typ_1p20V_25C) { index_1 ("0.0186, 0.0966, 0.174, 0.3294, 0.6408, 1.263, 2.5074"); index_2 ("0.001, 0.0234, 0.039, 0.0648, 0.108, 0.18, 0.3"); values ( \ - "0.0144513, 0.0820604, 0.128873, 0.206442, 0.336428, 0.553223, 0.913998", \ - "0.0352147, 0.0954158, 0.137367, 0.210293, 0.337289, 0.553224, 0.914751", \ - "0.0510494, 0.115493, 0.156301, 0.224643, 0.345028, 0.555107, 0.914752", \ - "0.0759073, 0.15287, 0.196394, 0.264287, 0.377052, 0.573535, 0.919712", \ - "0.115361, 0.21817, 0.267525, 0.34219, 0.457915, 0.644933, 0.966149", \ - "0.178117, 0.326697, 0.389728, 0.479383, 0.609279, 0.806627, 1.11897", \ - "0.278587, 0.500398, 0.592329, 0.707496, 0.871053, 1.09616, 1.43998" \ + "0.0144513, 0.0820632, 0.128864, 0.206442, 0.336428, 0.552968, 0.913992", \ + "0.0352147, 0.0954158, 0.137367, 0.210293, 0.337215, 0.552969, 0.914756", \ + "0.0510493, 0.115493, 0.156301, 0.224643, 0.345028, 0.555116, 0.914757", \ + "0.0759073, 0.152867, 0.196394, 0.264301, 0.377104, 0.573535, 0.92027", \ + "0.115361, 0.21817, 0.267483, 0.34219, 0.457916, 0.644933, 0.966149", \ + "0.178117, 0.326696, 0.389728, 0.479383, 0.609279, 0.806627, 1.11897", \ + "0.278587, 0.500398, 0.592329, 0.707496, 0.869374, 1.09616, 1.43998" \ ); } } @@ -2149,26 +2149,26 @@ library (sg13g2_stdcell_typ_1p20V_25C) { index_1 ("0.0186, 0.0966, 0.174, 0.3294, 0.6408, 1.263, 2.5074"); index_2 ("0.001, 0.0234, 0.039, 0.0648, 0.108, 0.18, 0.3"); values ( \ - "0.00445425, 0.00471119, 0.00468286, 0.0046486, 0.00453439, 0.00431697, 0.00404107", \ - "0.00418964, 0.00452497, 0.00455032, 0.00457589, 0.00446296, 0.00428905, 0.0041189", \ - "0.00413276, 0.00444895, 0.00445863, 0.00447837, 0.00451481, 0.00429591, 0.00397041", \ - "0.00419603, 0.00430676, 0.00439325, 0.00439224, 0.00449181, 0.00422208, 0.00399479", \ - "0.00464821, 0.00445204, 0.00439557, 0.00435294, 0.00450092, 0.0042713, 0.00397903", \ - "0.00621229, 0.00515575, 0.00493319, 0.00481116, 0.00452755, 0.00463218, 0.00405382", \ - "0.0102342, 0.00764026, 0.00700668, 0.0063984, 0.00590422, 0.00524672, 0.00495268" \ + "0.00445114, 0.00471058, 0.00468388, 0.00464893, 0.00450593, 0.0042972, 0.00404113", \ + "0.00419003, 0.00451956, 0.00454772, 0.00457281, 0.00447047, 0.00430263, 0.0041181", \ + "0.00413275, 0.00444895, 0.00446802, 0.00448649, 0.00444725, 0.00427111, 0.00402845", \ + "0.00419595, 0.0043067, 0.0043936, 0.00439169, 0.00447852, 0.00422202, 0.00398756", \ + "0.0046481, 0.00445206, 0.00441356, 0.00435444, 0.00459162, 0.00440705, 0.00398065", \ + "0.00621234, 0.00515578, 0.00493256, 0.00480997, 0.00449865, 0.00463043, 0.00401579", \ + "0.0102339, 0.00763983, 0.00701485, 0.00639884, 0.00590428, 0.00524309, 0.0049528" \ ); } fall_power (POWER_7x7ds1) { index_1 ("0.0186, 0.0966, 0.174, 0.3294, 0.6408, 1.263, 2.5074"); index_2 ("0.001, 0.0234, 0.039, 0.0648, 0.108, 0.18, 0.3"); values ( \ - "0.00313345, 0.00317743, 0.00314902, 0.00309785, 0.00300017, 0.00281173, 0.00247905", \ - "0.00284197, 0.00304843, 0.00301737, 0.00298809, 0.00289515, 0.00278768, 0.00248104", \ - "0.00286548, 0.00295482, 0.00300782, 0.00295002, 0.00289489, 0.00272665, 0.00239357", \ - "0.00313709, 0.00303707, 0.00299363, 0.00296747, 0.00305517, 0.00294818, 0.00232445", \ - "0.00390943, 0.00337593, 0.00325367, 0.00312762, 0.00294792, 0.00317821, 0.00240749", \ - "0.00566461, 0.00446201, 0.00414112, 0.00384345, 0.0035719, 0.00299207, 0.00305865", \ - "0.00965957, 0.00742822, 0.00669679, 0.00586869, 0.00523159, 0.00461176, 0.00359703" \ + "0.0031325, 0.00317699, 0.0031491, 0.00309235, 0.00300822, 0.00282666, 0.00247878", \ + "0.00284282, 0.00304877, 0.00301741, 0.00297294, 0.00289718, 0.00278408, 0.00247989", \ + "0.00286111, 0.00295482, 0.00300782, 0.00295036, 0.00289381, 0.00270761, 0.00239067", \ + "0.00313715, 0.00303707, 0.00299364, 0.00296748, 0.00292799, 0.0029151, 0.00235907", \ + "0.00390824, 0.00337636, 0.00325494, 0.00312796, 0.00290712, 0.00317821, 0.00245202", \ + "0.00566465, 0.00446201, 0.00414213, 0.00384371, 0.0035719, 0.00299207, 0.00306092", \ + "0.00965942, 0.00742802, 0.00669678, 0.00586873, 0.0052328, 0.00461176, 0.00359703" \ ); } } @@ -2178,26 +2178,26 @@ library (sg13g2_stdcell_typ_1p20V_25C) { index_1 ("0.0186, 0.0966, 0.174, 0.3294, 0.6408, 1.263, 2.5074"); index_2 ("0.001, 0.0234, 0.039, 0.0648, 0.108, 0.18, 0.3"); values ( \ - "0.00467398, 0.00470724, 0.00466463, 0.00461899, 0.00448362, 0.00427947, 0.0042872", \ - "0.00450196, 0.0046039, 0.00459524, 0.00461503, 0.00444853, 0.00427083, 0.00439253", \ - "0.004457, 0.00461, 0.00454432, 0.00454691, 0.00443669, 0.00430139, 0.00434334", \ - "0.00448716, 0.00450984, 0.00456162, 0.00447773, 0.0047412, 0.00417807, 0.0043388", \ - "0.0048551, 0.00469587, 0.00461163, 0.00453957, 0.00453272, 0.00431154, 0.00431131", \ - "0.00622234, 0.00539963, 0.00519713, 0.00502651, 0.0046545, 0.00466082, 0.00438657", \ - "0.00985724, 0.00783239, 0.00724686, 0.00666878, 0.00616608, 0.00544198, 0.00497145" \ + "0.00467404, 0.0047051, 0.0046586, 0.00461755, 0.00448802, 0.00427911, 0.00428353", \ + "0.00449991, 0.00460329, 0.00461991, 0.00456028, 0.00444908, 0.00426986, 0.00439296", \ + "0.00445736, 0.00461, 0.00455118, 0.00454679, 0.00449211, 0.00430097, 0.0042727", \ + "0.00448507, 0.00451012, 0.00456163, 0.00447773, 0.00476228, 0.00423217, 0.00433855", \ + "0.00485585, 0.0046954, 0.00461162, 0.00453957, 0.0045079, 0.00426637, 0.00431137", \ + "0.00622239, 0.00540006, 0.0051974, 0.00502651, 0.0046545, 0.00466082, 0.00438657", \ + "0.0098575, 0.00783218, 0.00724695, 0.00666814, 0.00616608, 0.0054483, 0.00497248" \ ); } fall_power (POWER_7x7ds1) { index_1 ("0.0186, 0.0966, 0.174, 0.3294, 0.6408, 1.263, 2.5074"); index_2 ("0.001, 0.0234, 0.039, 0.0648, 0.108, 0.18, 0.3"); values ( \ - "0.00473389, 0.00472928, 0.00469304, 0.00462525, 0.00455226, 0.00432813, 0.00402472", \ - "0.00448567, 0.00463561, 0.00464797, 0.00455441, 0.00445715, 0.00432486, 0.0038983", \ - "0.00442795, 0.0045447, 0.00459458, 0.00451422, 0.00445908, 0.00432131, 0.0039335", \ - "0.00447679, 0.00456638, 0.00454823, 0.0045333, 0.0045443, 0.00441133, 0.00391421", \ - "0.0049095, 0.00476091, 0.00470852, 0.00465618, 0.00446994, 0.00466538, 0.00429782", \ - "0.00634084, 0.00546842, 0.00531698, 0.00511919, 0.00498807, 0.00452062, 0.00452232", \ - "0.00986411, 0.00788702, 0.00729267, 0.00671118, 0.0062361, 0.00572878, 0.00509254" \ + "0.00473309, 0.00472916, 0.00469315, 0.00461731, 0.00455368, 0.00435652, 0.00402453", \ + "0.00448558, 0.00463561, 0.00464797, 0.00455438, 0.00445715, 0.00432472, 0.00388212", \ + "0.00442784, 0.00454714, 0.00459455, 0.0045142, 0.00476631, 0.00432131, 0.0039335", \ + "0.00447679, 0.00456636, 0.00454827, 0.0045333, 0.00475372, 0.00441079, 0.00388433", \ + "0.00490948, 0.00476295, 0.00470844, 0.00465626, 0.00449974, 0.00474496, 0.00428601", \ + "0.00634068, 0.00546929, 0.0053168, 0.00511915, 0.00498843, 0.00455325, 0.00451849", \ + "0.00986376, 0.00788704, 0.00729272, 0.00671139, 0.00623622, 0.00572878, 0.00509182" \ ); } } @@ -2208,26 +2208,26 @@ library (sg13g2_stdcell_typ_1p20V_25C) { index_1 ("0.0186, 0.0966, 0.174, 0.3294, 0.6408, 1.263, 2.5074"); index_2 ("0.001, 0.0234, 0.039, 0.0648, 0.108, 0.18, 0.3"); values ( \ - "0.00252423, 0.0028096, 0.00280353, 0.00274638, 0.00264398, 0.00241599, 0.00247325", \ - "0.00234945, 0.00255699, 0.00260871, 0.0026337, 0.00255742, 0.00239403, 0.0025519", \ - "0.00245332, 0.00253157, 0.00252919, 0.00253698, 0.00248348, 0.00238641, 0.00247387", \ - "0.00280405, 0.00253947, 0.00255936, 0.00247885, 0.00261576, 0.00226212, 0.00235868", \ - "0.00364677, 0.00299658, 0.00280949, 0.00266261, 0.00275203, 0.00236961, 0.00238497", \ - "0.00567066, 0.00426661, 0.00389351, 0.0036298, 0.00305652, 0.00305853, 0.00267791", \ - "0.0101534, 0.00747067, 0.00671311, 0.00598753, 0.00513484, 0.00407541, 0.00347249" \ + "0.00252066, 0.00280987, 0.00280261, 0.002746, 0.00264404, 0.00244588, 0.00251011", \ + "0.00234944, 0.0025571, 0.00259781, 0.00264172, 0.00255742, 0.00239496, 0.00255173", \ + "0.00245333, 0.00255287, 0.00253236, 0.00256582, 0.00248848, 0.00238671, 0.00245055", \ + "0.00280626, 0.00253946, 0.00255936, 0.00247858, 0.00261576, 0.00226038, 0.00239237", \ + "0.00364581, 0.00300003, 0.00280949, 0.00266248, 0.00261634, 0.00239649, 0.00245637", \ + "0.00566964, 0.0042672, 0.00389286, 0.00361844, 0.00304629, 0.0029528, 0.00267791", \ + "0.0101537, 0.00747102, 0.00671342, 0.00598753, 0.00514245, 0.00407547, 0.00347249" \ ); } fall_power (POWER_7x7ds1) { index_1 ("0.0186, 0.0966, 0.174, 0.3294, 0.6408, 1.263, 2.5074"); index_2 ("0.001, 0.0234, 0.039, 0.0648, 0.108, 0.18, 0.3"); values ( \ - "0.00342973, 0.00391083, 0.00381894, 0.00376343, 0.00366771, 0.00351474, 0.00315267", \ - "0.0031927, 0.00364731, 0.0037293, 0.00374047, 0.00365427, 0.00350311, 0.00330228", \ - "0.0032751, 0.0035908, 0.00361212, 0.00365467, 0.0037013, 0.00369861, 0.00315084", \ - "0.00363306, 0.00357234, 0.00365076, 0.00363683, 0.00358594, 0.00387458, 0.00315527", \ - "0.00453094, 0.00382347, 0.00380188, 0.0037875, 0.00373486, 0.00342538, 0.0037845", \ - "0.00665448, 0.00498564, 0.00467221, 0.00440827, 0.00421108, 0.00401817, 0.00344543", \ - "0.0111086, 0.00824043, 0.00734011, 0.00660003, 0.00579014, 0.00517124, 0.00465857" \ + "0.00342973, 0.00387842, 0.00381752, 0.00376362, 0.0036679, 0.00350137, 0.00316689", \ + "0.00319271, 0.00364731, 0.0037399, 0.00374145, 0.00379239, 0.00350335, 0.00330669", \ + "0.0032751, 0.00359091, 0.00361211, 0.00365466, 0.00370173, 0.00357695, 0.00315119", \ + "0.00363306, 0.00356006, 0.00365075, 0.00363901, 0.0035562, 0.00387446, 0.00346194", \ + "0.0045305, 0.00382352, 0.00379717, 0.00378762, 0.0037286, 0.00342587, 0.0037845", \ + "0.00665492, 0.00498522, 0.00467087, 0.00440827, 0.00421101, 0.00401817, 0.00344542", \ + "0.0111083, 0.00824063, 0.00734015, 0.00659999, 0.00573068, 0.00517296, 0.00465846" \ ); } } @@ -2238,26 +2238,26 @@ library (sg13g2_stdcell_typ_1p20V_25C) { index_1 ("0.0186, 0.0966, 0.174, 0.3294, 0.6408, 1.263, 2.5074"); index_2 ("0.001, 0.0234, 0.039, 0.0648, 0.108, 0.18, 0.3"); values ( \ - "0.00220653, 0.00260637, 0.00261417, 0.0025465, 0.00243106, 0.00223773, 0.00195715", \ - "0.00212694, 0.00238415, 0.00239994, 0.00243903, 0.00234047, 0.0022059, 0.00195217", \ - "0.00227123, 0.00234586, 0.00232732, 0.00233928, 0.00230311, 0.00220002, 0.00192503", \ - "0.00268125, 0.00235103, 0.00235645, 0.00228899, 0.00226685, 0.00208965, 0.00189654", \ - "0.00361099, 0.00282044, 0.00266424, 0.00247802, 0.00242839, 0.00214956, 0.00195325", \ - "0.00577547, 0.00414048, 0.00373316, 0.00342087, 0.0028287, 0.00286905, 0.0020498", \ - "0.0104255, 0.00741268, 0.00662225, 0.00585217, 0.00499762, 0.00392864, 0.00328426" \ + "0.00220643, 0.00260385, 0.00261355, 0.00254615, 0.00244481, 0.00223799, 0.00197554", \ + "0.00212694, 0.00238372, 0.0023994, 0.00241086, 0.00234063, 0.00220588, 0.00203353", \ + "0.00227119, 0.00234583, 0.00234052, 0.00233518, 0.00230006, 0.0021995, 0.00192503", \ + "0.00268174, 0.00234555, 0.00235965, 0.0022875, 0.00228033, 0.00208917, 0.00189654", \ + "0.00361132, 0.00281704, 0.00266424, 0.00246331, 0.00242912, 0.00214956, 0.00181169", \ + "0.00577556, 0.00414009, 0.00373315, 0.00342202, 0.00282864, 0.00286911, 0.00206041", \ + "0.0104255, 0.00741367, 0.00662225, 0.00585209, 0.00499856, 0.0039287, 0.00328504" \ ); } fall_power (POWER_7x7ds1) { index_1 ("0.0186, 0.0966, 0.174, 0.3294, 0.6408, 1.263, 2.5074"); index_2 ("0.001, 0.0234, 0.039, 0.0648, 0.108, 0.18, 0.3"); values ( \ - "0.00180411, 0.00226102, 0.00220291, 0.00214865, 0.00207004, 0.00194592, 0.00161454", \ - "0.00156574, 0.00202684, 0.00209483, 0.00214032, 0.00236673, 0.00189117, 0.00159117", \ - "0.00165808, 0.00198178, 0.00201386, 0.00204751, 0.00228892, 0.00220739, 0.00157934", \ - "0.00201325, 0.00197488, 0.00204666, 0.00201573, 0.0019582, 0.0021678, 0.0017583", \ - "0.0029468, 0.00222902, 0.00225065, 0.00220218, 0.00214304, 0.00183441, 0.00214698", \ - "0.00512751, 0.00342799, 0.00308269, 0.00281284, 0.00262969, 0.00254215, 0.00201906", \ - "0.00965156, 0.00666418, 0.00580877, 0.0049852, 0.00422576, 0.0036471, 0.00317997" \ + "0.00180443, 0.00225752, 0.00219144, 0.0021481, 0.00206954, 0.00190232, 0.00161417", \ + "0.00156572, 0.00202684, 0.0021028, 0.00217389, 0.00221277, 0.00190643, 0.00159284", \ + "0.00165843, 0.00198178, 0.00201387, 0.00204764, 0.00228874, 0.00217373, 0.00156434", \ + "0.00201325, 0.00197523, 0.00202794, 0.00203579, 0.00195808, 0.00216816, 0.00175146", \ + "0.00294693, 0.00222901, 0.00225075, 0.0022039, 0.00214358, 0.00183429, 0.00214596", \ + "0.00512758, 0.00342756, 0.00308288, 0.002812, 0.0026297, 0.00254215, 0.00201888", \ + "0.00964699, 0.00666403, 0.00580897, 0.0049852, 0.00422576, 0.00364692, 0.00318003" \ ); } } @@ -2268,26 +2268,26 @@ library (sg13g2_stdcell_typ_1p20V_25C) { index_1 ("0.0186, 0.0966, 0.174, 0.3294, 0.6408, 1.263, 2.5074"); index_2 ("0.001, 0.0234, 0.039, 0.0648, 0.108, 0.18, 0.3"); values ( \ - "0.00220478, 0.00264468, 0.0026041, 0.00256458, 0.00246742, 0.00239454, 0.00228432", \ - "0.00214634, 0.00240001, 0.00244723, 0.00240258, 0.00235747, 0.0021599, 0.00224965", \ - "0.00229774, 0.00232475, 0.00238325, 0.00236265, 0.00227183, 0.0021833, 0.00219991", \ - "0.00273715, 0.00240967, 0.00234412, 0.00243011, 0.00223008, 0.00220274, 0.00259724", \ - "0.00372454, 0.00289024, 0.00271205, 0.00250109, 0.00245938, 0.00219291, 0.00311071", \ - "0.00601127, 0.00427348, 0.00387932, 0.00355971, 0.00300832, 0.00263151, 0.00257684", \ - "0.0108909, 0.00778896, 0.006945, 0.00596338, 0.00511427, 0.00421008, 0.00312022" \ + "0.00220275, 0.00264473, 0.00260355, 0.00256434, 0.00246636, 0.00240099, 0.00228504", \ + "0.00214626, 0.00239425, 0.00244863, 0.00240166, 0.00235682, 0.00215813, 0.00228104", \ + "0.00229909, 0.00232229, 0.00236463, 0.00236277, 0.00227413, 0.00218457, 0.00219955", \ + "0.00273583, 0.0024097, 0.00234412, 0.0024404, 0.00222099, 0.00220658, 0.00260863", \ + "0.00372484, 0.00288949, 0.00271205, 0.00249201, 0.00245835, 0.00219291, 0.0023917", \ + "0.00601094, 0.00427233, 0.00387917, 0.0035597, 0.00300777, 0.00263145, 0.00257913", \ + "0.0108905, 0.00778915, 0.00694501, 0.00596316, 0.00511421, 0.00422927, 0.00312022" \ ); } fall_power (POWER_7x7ds1) { index_1 ("0.0186, 0.0966, 0.174, 0.3294, 0.6408, 1.263, 2.5074"); index_2 ("0.001, 0.0234, 0.039, 0.0648, 0.108, 0.18, 0.3"); values ( \ - "0.00173635, 0.00219973, 0.00213965, 0.00209117, 0.00201001, 0.00185286, 0.00152242", \ - "0.00152045, 0.00193569, 0.00199749, 0.00215387, 0.00227921, 0.00182309, 0.0015077", \ - "0.00163451, 0.00188267, 0.00189648, 0.00194437, 0.00218636, 0.00208904, 0.00147652", \ - "0.00202046, 0.00187322, 0.00193675, 0.00191053, 0.00183867, 0.0019805, 0.00171721", \ - "0.00300083, 0.00219157, 0.00218912, 0.00209922, 0.00206039, 0.00170623, 0.0018555", \ - "0.00523672, 0.00348943, 0.00309988, 0.00278728, 0.00254295, 0.00236294, 0.00179203", \ - "0.0100332, 0.00696144, 0.0060282, 0.0051419, 0.00430042, 0.00362711, 0.00322253" \ + "0.00173619, 0.00219969, 0.00213966, 0.00209124, 0.00200988, 0.00184631, 0.00152247", \ + "0.00152048, 0.0019416, 0.00199749, 0.00204475, 0.002281, 0.00182903, 0.00150684", \ + "0.00163438, 0.00188248, 0.00189651, 0.00194341, 0.00218654, 0.00208904, 0.00147664", \ + "0.00202003, 0.00187322, 0.00193266, 0.00191067, 0.0018628, 0.00215267, 0.00170306", \ + "0.00300087, 0.00219113, 0.00218912, 0.00209254, 0.00206086, 0.00170617, 0.0018555", \ + "0.00523623, 0.00348936, 0.00310103, 0.00278752, 0.00254291, 0.00236294, 0.00179209", \ + "0.0100331, 0.00696153, 0.00602826, 0.00514189, 0.00430046, 0.00362711, 0.00322247" \ ); } } @@ -2297,26 +2297,26 @@ library (sg13g2_stdcell_typ_1p20V_25C) { index_1 ("0.0186, 0.0966, 0.174, 0.3294, 0.6408, 1.263, 2.5074"); index_2 ("0.001, 0.0234, 0.039, 0.0648, 0.108, 0.18, 0.3"); values ( \ - "0.00220478, 0.00264468, 0.0026041, 0.00256458, 0.00246742, 0.00239454, 0.00228432", \ - "0.00214634, 0.00240001, 0.00244723, 0.00240258, 0.00235747, 0.0021599, 0.00224965", \ - "0.00229774, 0.00232475, 0.00238325, 0.00236265, 0.00227183, 0.0021833, 0.00219991", \ - "0.00273715, 0.00240967, 0.00234412, 0.00243011, 0.00223008, 0.00220274, 0.00259724", \ - "0.00372454, 0.00289024, 0.00271205, 0.00250109, 0.00245938, 0.00219291, 0.00311071", \ - "0.00601127, 0.00427348, 0.00387932, 0.00355971, 0.00300832, 0.00263151, 0.00257684", \ - "0.0108909, 0.00778896, 0.006945, 0.00596338, 0.00511427, 0.00421008, 0.00312022" \ + "0.00220275, 0.00264473, 0.00260355, 0.00256434, 0.00246636, 0.00240099, 0.00228504", \ + "0.00214626, 0.00239425, 0.00244863, 0.00240166, 0.00235682, 0.00215813, 0.00228104", \ + "0.00229909, 0.00232229, 0.00236463, 0.00236277, 0.00227413, 0.00218457, 0.00219955", \ + "0.00273583, 0.0024097, 0.00234412, 0.0024404, 0.00222099, 0.00220658, 0.00260863", \ + "0.00372484, 0.00288949, 0.00271205, 0.00249201, 0.00245835, 0.00219291, 0.0023917", \ + "0.00601094, 0.00427233, 0.00387917, 0.0035597, 0.00300777, 0.00263145, 0.00257913", \ + "0.0108905, 0.00778915, 0.00694501, 0.00596316, 0.00511421, 0.00422927, 0.00312022" \ ); } fall_power (POWER_7x7ds1) { index_1 ("0.0186, 0.0966, 0.174, 0.3294, 0.6408, 1.263, 2.5074"); index_2 ("0.001, 0.0234, 0.039, 0.0648, 0.108, 0.18, 0.3"); values ( \ - "0.00180411, 0.00226102, 0.00220291, 0.00214865, 0.00207004, 0.00194592, 0.00161454", \ - "0.00156574, 0.00202684, 0.00209483, 0.00214032, 0.00236673, 0.00189117, 0.00159117", \ - "0.00165808, 0.00198178, 0.00201386, 0.00204751, 0.00228892, 0.00220739, 0.00157934", \ - "0.00201325, 0.00197488, 0.00204666, 0.00201573, 0.0019582, 0.0021678, 0.0017583", \ - "0.0029468, 0.00222902, 0.00225065, 0.00220218, 0.00214304, 0.00183441, 0.00214698", \ - "0.00512751, 0.00342799, 0.00308269, 0.00281284, 0.00262969, 0.00254215, 0.00201906", \ - "0.00965156, 0.00666418, 0.00580877, 0.0049852, 0.00422576, 0.0036471, 0.00317997" \ + "0.00180443, 0.00225752, 0.00219144, 0.0021481, 0.00206954, 0.00190232, 0.00161417", \ + "0.00156572, 0.00202684, 0.0021028, 0.00217389, 0.00221277, 0.00190643, 0.00159284", \ + "0.00165843, 0.00198178, 0.00201387, 0.00204764, 0.00228874, 0.00217373, 0.00156434", \ + "0.00201325, 0.00197523, 0.00202794, 0.00203579, 0.00195808, 0.00216816, 0.00175146", \ + "0.00294693, 0.00222901, 0.00225075, 0.0022039, 0.00214358, 0.00183429, 0.00214596", \ + "0.00512758, 0.00342756, 0.00308288, 0.002812, 0.0026297, 0.00254215, 0.00201888", \ + "0.00964699, 0.00666403, 0.00580897, 0.0049852, 0.00422576, 0.00364692, 0.00318003" \ ); } } @@ -2326,63 +2326,63 @@ library (sg13g2_stdcell_typ_1p20V_25C) { max_transition : 2.5074; capacitance : 0.00301392; rise_capacitance : 0.00298592; - rise_capacitance_range (0.00298592, 0.00298592); + rise_capacitance_range (0.00275739, 0.00322116); fall_capacitance : 0.00304192; - fall_capacitance_range (0.00304192, 0.00304192); + fall_capacitance_range (0.00263018, 0.00344376); } pin (A2) { direction : "input"; max_transition : 2.5074; capacitance : 0.00304949; rise_capacitance : 0.00309582; - rise_capacitance_range (0.00309582, 0.00309582); - fall_capacitance : 0.00300316; - fall_capacitance_range (0.00300316, 0.00300316); + rise_capacitance_range (0.00270804, 0.00343089); + fall_capacitance : 0.00300317; + fall_capacitance_range (0.00267889, 0.00335223); } pin (B1) { direction : "input"; max_transition : 2.5074; capacitance : 0.00287829; rise_capacitance : 0.0029488; - rise_capacitance_range (0.0029488, 0.0029488); - fall_capacitance : 0.00280779; - fall_capacitance_range (0.00280779, 0.00280779); + rise_capacitance_range (0.00242193, 0.00339383); + fall_capacitance : 0.00280778; + fall_capacitance_range (0.00254442, 0.0031522); } } cell (sg13g2_a21oi_2) { area : 14.5152; cell_footprint : "a21oi"; - cell_leakage_power : 228.946; + cell_leakage_power : 228.945; leakage_power () { - value : 185.247; + value : 185.246; when : "!A1&!A2&!B1&Y"; } leakage_power () { - value : 249.547; + value : 249.546; when : "!A1&!A2&B1&!Y"; } leakage_power () { - value : 222.702; + value : 222.701; when : "!A1&A2&!B1&Y"; } leakage_power () { - value : 255.734; + value : 255.733; when : "!A1&A2&B1&!Y"; } leakage_power () { - value : 173.82; + value : 173.818; when : "A1&!A2&!B1&Y"; } leakage_power () { - value : 255.734; + value : 255.733; when : "A1&!A2&B1&!Y"; } leakage_power () { - value : 292.06; + value : 292.058; when : "A1&A2&!B1&!Y"; } leakage_power () { - value : 196.723; + value : 196.722; when : "A1&A2&B1&!Y"; } pin (Y) { @@ -2398,52 +2398,52 @@ library (sg13g2_stdcell_typ_1p20V_25C) { index_1 ("0.0186, 0.0966, 0.174, 0.3294, 0.6408, 1.263, 2.5074"); index_2 ("0.001, 0.0468, 0.078, 0.1296, 0.216, 0.36, 0.6"); values ( \ - "0.0426892, 0.17852, 0.269002, 0.418546, 0.668609, 1.08553, 1.78121", \ - "0.0672979, 0.210893, 0.301835, 0.45173, 0.702437, 1.11971, 1.81559", \ - "0.0802396, 0.238021, 0.330107, 0.480263, 0.7311, 1.14825, 1.84389", \ - "0.0951889, 0.285704, 0.384, 0.537452, 0.789222, 1.20678, 1.90207", \ - "0.110399, 0.361723, 0.476112, 0.64425, 0.905577, 1.32634, 2.02224", \ - "0.124845, 0.46811, 0.612654, 0.813549, 1.10723, 1.55231, 2.25791", \ - "0.1438, 0.608124, 0.804323, 1.06648, 1.4228, 1.93615, 2.69882" \ + "0.0426879, 0.17851, 0.269006, 0.418704, 0.668617, 1.08551, 1.78118", \ + "0.0673308, 0.210875, 0.301823, 0.451815, 0.702446, 1.11971, 1.81555", \ + "0.0802388, 0.238011, 0.330102, 0.48021, 0.731104, 1.14919, 1.84414", \ + "0.0951871, 0.285701, 0.384017, 0.537448, 0.789221, 1.20678, 1.90229", \ + "0.110398, 0.361719, 0.476107, 0.644242, 0.905565, 1.32627, 2.02221", \ + "0.124844, 0.468105, 0.612648, 0.813542, 1.10722, 1.55229, 2.25788", \ + "0.143798, 0.608119, 0.804316, 1.06647, 1.42278, 1.93613, 2.69879" \ ); } rise_transition (TIMING_DELAY_7x7ds1) { index_1 ("0.0186, 0.0966, 0.174, 0.3294, 0.6408, 1.263, 2.5074"); index_2 ("0.001, 0.0468, 0.078, 0.1296, 0.216, 0.36, 0.6"); values ( \ - "0.0226654, 0.208384, 0.334667, 0.54393, 0.893539, 1.47663, 2.44921", \ - "0.0307948, 0.209463, 0.334895, 0.543931, 0.893678, 1.47726, 2.44933", \ - "0.0401747, 0.215663, 0.337906, 0.544574, 0.89408, 1.47753, 2.44934", \ - "0.057715, 0.236976, 0.354123, 0.55348, 0.896907, 1.47798, 2.44974", \ - "0.0918415, 0.287499, 0.401285, 0.592028, 0.920954, 1.487, 2.45196", \ - "0.151289, 0.381249, 0.499424, 0.688749, 1.00712, 1.54646, 2.47822", \ - "0.240169, 0.543602, 0.68046, 0.882551, 1.20288, 1.72999, 2.62236" \ + "0.0226643, 0.20838, 0.334822, 0.543951, 0.893524, 1.47661, 2.44917", \ + "0.0307809, 0.209436, 0.335003, 0.54434, 0.893665, 1.47724, 2.44929", \ + "0.0401743, 0.215659, 0.337899, 0.544524, 0.894097, 1.47854, 2.44999", \ + "0.0577181, 0.236973, 0.354127, 0.553556, 0.896954, 1.47855, 2.45", \ + "0.0918408, 0.287495, 0.40128, 0.59206, 0.92094, 1.48716, 2.45192", \ + "0.151288, 0.381246, 0.499418, 0.688654, 1.00711, 1.54644, 2.47817", \ + "0.240168, 0.543599, 0.680455, 0.882541, 1.20444, 1.72999, 2.62231" \ ); } cell_fall (TIMING_DELAY_7x7ds1) { index_1 ("0.0186, 0.0966, 0.174, 0.3294, 0.6408, 1.263, 2.5074"); index_2 ("0.001, 0.0468, 0.078, 0.1296, 0.216, 0.36, 0.6"); values ( \ - "0.0360945, 0.133629, 0.197825, 0.303535, 0.480483, 0.774502, 1.26474", \ - "0.0637239, 0.17566, 0.240317, 0.346135, 0.522742, 0.817585, 1.30751", \ - "0.0806653, 0.212489, 0.280869, 0.38807, 0.564745, 0.85905, 1.34941", \ - "0.103948, 0.270867, 0.350547, 0.467041, 0.647822, 0.942339, 1.43191", \ - "0.136403, 0.357858, 0.45845, 0.598073, 0.801582, 1.10925, 1.60085", \ - "0.179835, 0.48178, 0.614215, 0.795996, 1.04603, 1.40259, 1.93011", \ - "0.237309, 0.647697, 0.831107, 1.07427, 1.40553, 1.85557, 2.48591" \ + "0.0360984, 0.133631, 0.197821, 0.303582, 0.480481, 0.774651, 1.26473", \ + "0.0637238, 0.17566, 0.240313, 0.346148, 0.522803, 0.81754, 1.30754", \ + "0.080679, 0.212489, 0.280868, 0.38807, 0.564769, 0.859024, 1.34954", \ + "0.103948, 0.270867, 0.350547, 0.466909, 0.64782, 0.942149, 1.43218", \ + "0.136403, 0.357857, 0.45845, 0.598072, 0.801581, 1.10925, 1.60079", \ + "0.179835, 0.48178, 0.614214, 0.795995, 1.04602, 1.40259, 1.93011", \ + "0.23731, 0.647696, 0.831107, 1.07427, 1.40553, 1.85549, 2.4859" \ ); } fall_transition (TIMING_DELAY_7x7ds1) { index_1 ("0.0186, 0.0966, 0.174, 0.3294, 0.6408, 1.263, 2.5074"); index_2 ("0.001, 0.0468, 0.078, 0.1296, 0.216, 0.36, 0.6"); values ( \ - "0.0239139, 0.149177, 0.234486, 0.375524, 0.611542, 1.00437, 1.65894", \ - "0.037683, 0.154912, 0.236658, 0.375565, 0.611543, 1.00502, 1.65982", \ - "0.0502889, 0.170452, 0.247967, 0.381212, 0.612393, 1.00503, 1.65983", \ - "0.0709447, 0.206086, 0.28246, 0.408089, 0.626745, 1.0077, 1.65984", \ - "0.103256, 0.272061, 0.353298, 0.480105, 0.68817, 1.04617, 1.67228", \ - "0.153274, 0.379261, 0.478888, 0.617306, 0.835344, 1.18109, 1.76961", \ - "0.231092, 0.555579, 0.680433, 0.853329, 1.09944, 1.4739, 2.05388" \ + "0.0239102, 0.149178, 0.234495, 0.375414, 0.61154, 1.00473, 1.65894", \ + "0.037683, 0.154911, 0.236686, 0.375665, 0.611541, 1.00503, 1.65981", \ + "0.0502549, 0.170451, 0.247968, 0.381211, 0.612418, 1.00504, 1.65982", \ + "0.0709446, 0.206086, 0.282459, 0.407943, 0.626742, 1.00876, 1.65983", \ + "0.103256, 0.27206, 0.353297, 0.479902, 0.68817, 1.04616, 1.6729", \ + "0.153274, 0.37926, 0.478888, 0.617306, 0.835343, 1.18109, 1.76958", \ + "0.231091, 0.555579, 0.680432, 0.853327, 1.09944, 1.47381, 2.05387" \ ); } } @@ -2455,52 +2455,52 @@ library (sg13g2_stdcell_typ_1p20V_25C) { index_1 ("0.0186, 0.0966, 0.174, 0.3294, 0.6408, 1.263, 2.5074"); index_2 ("0.001, 0.0468, 0.078, 0.1296, 0.216, 0.36, 0.6"); values ( \ - "0.0509954, 0.185723, 0.276053, 0.425305, 0.674506, 1.09062, 1.78287", \ - "0.0785486, 0.218856, 0.309313, 0.458601, 0.708429, 1.12431, 1.81796", \ - "0.0945351, 0.246691, 0.338073, 0.487466, 0.737381, 1.15398, 1.84574", \ - "0.115043, 0.29586, 0.39299, 0.545452, 0.796008, 1.21197, 1.90491", \ - "0.139365, 0.374467, 0.487033, 0.653668, 0.913164, 1.33236, 2.02566", \ - "0.166534, 0.485578, 0.62723, 0.82579, 1.11708, 1.55978, 2.26214", \ - "0.203125, 0.633946, 0.824522, 1.08217, 1.43557, 1.9471, 2.70491" \ + "0.051005, 0.185699, 0.276002, 0.425317, 0.674481, 1.09055, 1.78277", \ + "0.0785394, 0.218848, 0.309334, 0.458566, 0.708407, 1.12427, 1.81795", \ + "0.0945339, 0.246723, 0.33801, 0.487507, 0.73737, 1.15393, 1.84572", \ + "0.115042, 0.295855, 0.392987, 0.545425, 0.796018, 1.21196, 1.90509", \ + "0.139364, 0.374463, 0.487028, 0.65366, 0.91318, 1.33235, 2.0257", \ + "0.166533, 0.485574, 0.627225, 0.825782, 1.11707, 1.55976, 2.26205", \ + "0.203122, 0.633941, 0.824884, 1.08216, 1.43555, 1.94709, 2.70487" \ ); } rise_transition (TIMING_DELAY_7x7ds1) { index_1 ("0.0186, 0.0966, 0.174, 0.3294, 0.6408, 1.263, 2.5074"); index_2 ("0.001, 0.0468, 0.078, 0.1296, 0.216, 0.36, 0.6"); values ( \ - "0.0304133, 0.216282, 0.342407, 0.551081, 0.899999, 1.48135, 2.44955", \ - "0.0374343, 0.217203, 0.343121, 0.551082, 0.9, 1.48143, 2.45057", \ - "0.0468065, 0.223043, 0.345434, 0.552409, 0.900001, 1.48282, 2.45127", \ - "0.0647851, 0.243872, 0.36102, 0.560507, 0.903064, 1.48283, 2.45128", \ - "0.0986189, 0.29352, 0.407996, 0.598619, 0.926611, 1.49135, 2.45328", \ - "0.154841, 0.386707, 0.505487, 0.695476, 1.01284, 1.55089, 2.47933", \ - "0.236944, 0.545516, 0.684473, 0.888087, 1.20885, 1.73451, 2.62378" \ + "0.0304121, 0.216278, 0.342372, 0.551072, 0.899974, 1.48136, 2.4495", \ + "0.0374335, 0.21721, 0.342991, 0.552048, 0.899975, 1.48137, 2.45052", \ + "0.0468059, 0.223019, 0.345362, 0.552482, 0.899976, 1.48277, 2.45128", \ + "0.0647844, 0.24386, 0.361136, 0.560449, 0.902772, 1.48278, 2.45129", \ + "0.0986183, 0.293517, 0.407991, 0.59861, 0.926635, 1.49133, 2.45336", \ + "0.15484, 0.386691, 0.505482, 0.695468, 1.01282, 1.55086, 2.47949", \ + "0.236942, 0.545512, 0.683713, 0.888078, 1.20881, 1.73507, 2.62374" \ ); } cell_fall (TIMING_DELAY_7x7ds1) { index_1 ("0.0186, 0.0966, 0.174, 0.3294, 0.6408, 1.263, 2.5074"); index_2 ("0.001, 0.0468, 0.078, 0.1296, 0.216, 0.36, 0.6"); values ( \ - "0.0407251, 0.137925, 0.202065, 0.307787, 0.48467, 0.778815, 1.269", \ - "0.0687005, 0.175312, 0.239961, 0.345859, 0.522582, 0.817359, 1.30722", \ - "0.0866366, 0.20758, 0.274904, 0.381935, 0.558917, 0.853367, 1.34405", \ - "0.11129, 0.26087, 0.336004, 0.449969, 0.630277, 0.925324, 1.41572", \ - "0.144108, 0.344108, 0.436008, 0.566609, 0.763178, 1.06845, 1.56157", \ - "0.187736, 0.467709, 0.587161, 0.751876, 0.984449, 1.32542, 1.84446", \ - "0.247789, 0.635837, 0.80511, 1.02643, 1.32488, 1.7403, 2.3329" \ + "0.0407223, 0.137921, 0.202062, 0.307784, 0.484669, 0.778896, 1.26901", \ + "0.0687004, 0.175311, 0.239961, 0.345795, 0.52261, 0.817366, 1.30714", \ + "0.0866364, 0.20758, 0.274905, 0.381934, 0.558911, 0.853366, 1.34396", \ + "0.11129, 0.26087, 0.336003, 0.449969, 0.630276, 0.925311, 1.41574", \ + "0.144107, 0.344109, 0.436008, 0.566667, 0.763211, 1.06845, 1.56143", \ + "0.187736, 0.467709, 0.58716, 0.751875, 0.984448, 1.32542, 1.84446", \ + "0.247789, 0.635837, 0.805109, 1.02643, 1.32488, 1.7403, 2.33289" \ ); } fall_transition (TIMING_DELAY_7x7ds1) { index_1 ("0.0186, 0.0966, 0.174, 0.3294, 0.6408, 1.263, 2.5074"); index_2 ("0.001, 0.0468, 0.078, 0.1296, 0.216, 0.36, 0.6"); values ( \ - "0.0236192, 0.149213, 0.234489, 0.375555, 0.611628, 1.00405, 1.65895", \ - "0.0321048, 0.152595, 0.236002, 0.375556, 0.611629, 1.00506, 1.65916", \ - "0.0421058, 0.162658, 0.242996, 0.379075, 0.612439, 1.00507, 1.65924", \ - "0.0607827, 0.187269, 0.266366, 0.39667, 0.622039, 1.00623, 1.65925", \ - "0.0934011, 0.237308, 0.316779, 0.446592, 0.663239, 1.03216, 1.66991", \ - "0.144413, 0.328444, 0.416228, 0.549102, 0.767607, 1.12461, 1.73315", \ - "0.219782, 0.486474, 0.59303, 0.74359, 0.972409, 1.33639, 1.93184" \ + "0.0236192, 0.149212, 0.234492, 0.375552, 0.611627, 1.0047, 1.65894", \ + "0.0321054, 0.152596, 0.23578, 0.375769, 0.611628, 1.00506, 1.66001", \ + "0.0421057, 0.162658, 0.243, 0.379074, 0.612342, 1.00507, 1.66002", \ + "0.0607827, 0.187269, 0.266365, 0.396669, 0.622036, 1.00661, 1.66003", \ + "0.0934009, 0.237304, 0.316787, 0.446535, 0.663232, 1.03212, 1.66792", \ + "0.144413, 0.328443, 0.416227, 0.549101, 0.767605, 1.1246, 1.73315", \ + "0.219782, 0.486473, 0.593029, 0.743589, 0.972405, 1.33639, 1.93183" \ ); } } @@ -2514,52 +2514,52 @@ library (sg13g2_stdcell_typ_1p20V_25C) { index_1 ("0.0186, 0.0966, 0.174, 0.3294, 0.6408, 1.263, 2.5074"); index_2 ("0.001, 0.0468, 0.078, 0.1296, 0.216, 0.36, 0.6"); values ( \ - "0.0401992, 0.177198, 0.267732, 0.416975, 0.666553, 1.08196, 1.77466", \ - "0.0660543, 0.212434, 0.303201, 0.452871, 0.702881, 1.11871, 1.81278", \ - "0.0811689, 0.246335, 0.338157, 0.487712, 0.737717, 1.15453, 1.84717", \ - "0.101726, 0.305888, 0.406276, 0.560024, 0.810386, 1.22611, 1.91903", \ - "0.129708, 0.396979, 0.519972, 0.694218, 0.957056, 1.37613, 2.06865", \ - "0.166471, 0.522301, 0.680492, 0.899651, 1.20706, 1.66057, 2.36242", \ - "0.214104, 0.6855, 0.900527, 1.18816, 1.58371, 2.13, 2.91472" \ + "0.0402019, 0.177173, 0.267742, 0.416967, 0.666544, 1.08188, 1.77457", \ + "0.0660595, 0.212441, 0.303211, 0.452842, 0.702816, 1.11876, 1.81249", \ + "0.0811688, 0.24633, 0.338161, 0.487647, 0.737502, 1.15448, 1.84707", \ + "0.101726, 0.305885, 0.406272, 0.560022, 0.810373, 1.22596, 1.91896", \ + "0.129707, 0.396976, 0.519968, 0.694212, 0.957045, 1.37611, 2.06851", \ + "0.166469, 0.522297, 0.680487, 0.899625, 1.20705, 1.66055, 2.36228", \ + "0.214101, 0.685495, 0.900521, 1.18815, 1.58369, 2.12998, 2.91469" \ ); } rise_transition (TIMING_DELAY_7x7ds1) { index_1 ("0.0186, 0.0966, 0.174, 0.3294, 0.6408, 1.263, 2.5074"); index_2 ("0.001, 0.0468, 0.078, 0.1296, 0.216, 0.36, 0.6"); values ( \ - "0.0303965, 0.216342, 0.342549, 0.551001, 0.899844, 1.48167, 2.44954", \ - "0.0442436, 0.218276, 0.342979, 0.551418, 0.899845, 1.48204, 2.45079", \ - "0.0571142, 0.228496, 0.347644, 0.552019, 0.899862, 1.48277, 2.45099", \ - "0.0766289, 0.26134, 0.373501, 0.566817, 0.90436, 1.48278, 2.451", \ - "0.108559, 0.33048, 0.443427, 0.626374, 0.942652, 1.49737, 2.45296", \ - "0.159153, 0.445244, 0.575282, 0.765455, 1.07298, 1.58842, 2.49434", \ - "0.243776, 0.627791, 0.78905, 1.01711, 1.3473, 1.86192, 2.71422" \ + "0.0303964, 0.216339, 0.342542, 0.550992, 0.899828, 1.48153, 2.45116", \ + "0.0442172, 0.218271, 0.342751, 0.551404, 0.899829, 1.48205, 2.45144", \ + "0.0571133, 0.228455, 0.347603, 0.552865, 0.900965, 1.48271, 2.45145", \ + "0.0766284, 0.261362, 0.373494, 0.566814, 0.904342, 1.48272, 2.45146", \ + "0.108558, 0.330513, 0.443421, 0.626366, 0.942636, 1.49735, 2.45527", \ + "0.159152, 0.445241, 0.575279, 0.765511, 1.07299, 1.58839, 2.49321", \ + "0.243775, 0.627788, 0.789044, 1.0171, 1.34729, 1.86189, 2.71418" \ ); } cell_fall (TIMING_DELAY_7x7ds1) { index_1 ("0.0186, 0.0966, 0.174, 0.3294, 0.6408, 1.263, 2.5074"); index_2 ("0.001, 0.0468, 0.078, 0.1296, 0.216, 0.36, 0.6"); values ( \ - "0.0200406, 0.0739098, 0.108519, 0.165749, 0.261548, 0.421173, 0.687107", \ - "0.0394624, 0.119988, 0.157618, 0.216028, 0.3119, 0.471491, 0.737727", \ - "0.0497939, 0.154382, 0.198627, 0.262377, 0.360806, 0.520725, 0.786384", \ - "0.0622819, 0.205823, 0.262563, 0.340039, 0.450943, 0.616969, 0.883554", \ - "0.0789811, 0.281389, 0.358929, 0.461097, 0.599113, 0.792207, 1.0768", \ - "0.099006, 0.385669, 0.496649, 0.637281, 0.824483, 1.07112, 1.41148", \ - "0.121856, 0.518817, 0.680443, 0.886036, 1.14591, 1.48727, 1.9311" \ + "0.0200397, 0.0739131, 0.108518, 0.165774, 0.261565, 0.4212, 0.687158", \ + "0.0394536, 0.119972, 0.157596, 0.216041, 0.311808, 0.471497, 0.73778", \ + "0.0497947, 0.154391, 0.198596, 0.262385, 0.36082, 0.520644, 0.786317", \ + "0.0622829, 0.205828, 0.262507, 0.340049, 0.450588, 0.617266, 0.883622", \ + "0.0789826, 0.28139, 0.358937, 0.461109, 0.599134, 0.792152, 1.0768", \ + "0.0990091, 0.385676, 0.496658, 0.637266, 0.824504, 1.07115, 1.41133", \ + "0.12186, 0.518487, 0.680454, 0.886052, 1.14592, 1.48662, 1.93116" \ ); } fall_transition (TIMING_DELAY_7x7ds1) { index_1 ("0.0186, 0.0966, 0.174, 0.3294, 0.6408, 1.263, 2.5074"); index_2 ("0.001, 0.0468, 0.078, 0.1296, 0.216, 0.36, 0.6"); values ( \ - "0.0124263, 0.0817191, 0.128411, 0.205875, 0.335699, 0.552132, 0.912384", \ - "0.0338059, 0.0951557, 0.136987, 0.209722, 0.336585, 0.552133, 0.912564", \ - "0.0493612, 0.115243, 0.155997, 0.224199, 0.34431, 0.554315, 0.912565", \ - "0.0736089, 0.152706, 0.196239, 0.26397, 0.376428, 0.57291, 0.918305", \ - "0.112072, 0.217945, 0.26727, 0.341726, 0.45736, 0.644001, 0.964696", \ - "0.173456, 0.326512, 0.389617, 0.478921, 0.608484, 0.805631, 1.11757", \ - "0.272196, 0.500366, 0.592182, 0.706812, 0.869318, 1.0948, 1.43857" \ + "0.0124315, 0.081723, 0.128434, 0.20589, 0.335721, 0.55212, 0.912443", \ + "0.0338249, 0.0951694, 0.136999, 0.209733, 0.336427, 0.552121, 0.912646", \ + "0.0493621, 0.11525, 0.155986, 0.224199, 0.344398, 0.554064, 0.912647", \ + "0.0736138, 0.152711, 0.196203, 0.26398, 0.376591, 0.57286, 0.91839", \ + "0.112073, 0.217941, 0.267242, 0.341738, 0.457357, 0.64415, 0.965293", \ + "0.173456, 0.326507, 0.389626, 0.478921, 0.608506, 0.805661, 1.11765", \ + "0.272196, 0.500385, 0.59218, 0.706826, 0.869357, 1.09538, 1.43852" \ ); } } @@ -2573,52 +2573,52 @@ library (sg13g2_stdcell_typ_1p20V_25C) { index_1 ("0.0186, 0.0966, 0.174, 0.3294, 0.6408, 1.263, 2.5074"); index_2 ("0.001, 0.0468, 0.078, 0.1296, 0.216, 0.36, 0.6"); values ( \ - "0.0307279, 0.167639, 0.258483, 0.407914, 0.658224, 1.07484, 1.76973", \ - "0.0515267, 0.202855, 0.293765, 0.443688, 0.69441, 1.11157, 1.80757", \ - "0.0621075, 0.236375, 0.328657, 0.47869, 0.729358, 1.14753, 1.84155", \ - "0.076959, 0.294577, 0.396205, 0.550794, 0.802057, 1.2191, 1.91421", \ - "0.0963708, 0.382416, 0.507804, 0.684099, 0.948464, 1.36893, 2.06358", \ - "0.121799, 0.502789, 0.664999, 0.88712, 1.19742, 1.65332, 2.35741", \ - "0.154819, 0.659395, 0.879357, 1.17228, 1.57109, 2.12006, 2.90937" \ + "0.0306992, 0.167579, 0.258498, 0.407903, 0.658197, 1.07486, 1.76969", \ + "0.0515265, 0.202857, 0.293762, 0.443769, 0.694463, 1.11158, 1.80768", \ + "0.0621085, 0.236389, 0.328666, 0.478584, 0.729366, 1.14651, 1.84206", \ + "0.0769584, 0.294575, 0.396201, 0.550788, 0.802004, 1.21908, 1.91425", \ + "0.0963698, 0.382413, 0.507799, 0.68405, 0.948454, 1.36891, 2.0636", \ + "0.121796, 0.502785, 0.664994, 0.887113, 1.19741, 1.6533, 2.35734", \ + "0.154816, 0.65939, 0.87935, 1.17227, 1.57108, 2.12004, 2.90933" \ ); } rise_transition (TIMING_DELAY_7x7ds1) { index_1 ("0.0186, 0.0966, 0.174, 0.3294, 0.6408, 1.263, 2.5074"); index_2 ("0.001, 0.0468, 0.078, 0.1296, 0.216, 0.36, 0.6"); values ( \ - "0.0229141, 0.208418, 0.334862, 0.543752, 0.893723, 1.47739, 2.44874", \ - "0.0385839, 0.210718, 0.335196, 0.544244, 0.893727, 1.47767, 2.45018", \ - "0.0498355, 0.221813, 0.34048, 0.545421, 0.894027, 1.47768, 2.45019", \ - "0.0677713, 0.255828, 0.367462, 0.5604, 0.899056, 1.47769, 2.4502", \ - "0.0969852, 0.325728, 0.438072, 0.620931, 0.937316, 1.49282, 2.45406", \ - "0.144919, 0.439437, 0.569968, 0.760518, 1.06873, 1.58509, 2.49304", \ - "0.227144, 0.621716, 0.78452, 1.01178, 1.3427, 1.86081, 2.71391" \ + "0.0229142, 0.208282, 0.334855, 0.543742, 0.893711, 1.47745, 2.4487", \ + "0.0385834, 0.210697, 0.335145, 0.543743, 0.893712, 1.47764, 2.45014", \ + "0.0498339, 0.221876, 0.340484, 0.544882, 0.893986, 1.47765, 2.45015", \ + "0.067771, 0.255825, 0.367457, 0.560391, 0.89899, 1.47766, 2.45016", \ + "0.0969848, 0.325725, 0.438067, 0.620973, 0.937301, 1.49279, 2.4517", \ + "0.144926, 0.439434, 0.569963, 0.760511, 1.06872, 1.58506, 2.49296", \ + "0.227144, 0.621713, 0.784516, 1.01177, 1.34257, 1.86079, 2.71531" \ ); } cell_fall (TIMING_DELAY_7x7ds1) { index_1 ("0.0186, 0.0966, 0.174, 0.3294, 0.6408, 1.263, 2.5074"); index_2 ("0.001, 0.0468, 0.078, 0.1296, 0.216, 0.36, 0.6"); values ( \ - "0.0197871, 0.073603, 0.108191, 0.165319, 0.260943, 0.420329, 0.685965", \ - "0.038851, 0.119626, 0.15712, 0.21558, 0.311265, 0.470664, 0.736033", \ - "0.0487194, 0.153939, 0.198147, 0.261889, 0.36022, 0.519769, 0.785063", \ - "0.0606739, 0.205115, 0.261893, 0.339328, 0.449944, 0.616381, 0.88229", \ - "0.0760522, 0.280203, 0.357815, 0.460134, 0.598028, 0.791092, 1.07547", \ - "0.0933519, 0.383367, 0.494741, 0.635513, 0.82286, 1.06956, 1.40977", \ - "0.109222, 0.513513, 0.676482, 0.882711, 1.14303, 1.48414, 1.9287" \ + "0.0197865, 0.0735956, 0.108188, 0.165321, 0.260953, 0.420306, 0.685991", \ + "0.0388529, 0.11963, 0.157109, 0.215603, 0.311259, 0.47058, 0.736213", \ + "0.0487202, 0.153943, 0.198152, 0.261898, 0.360234, 0.519764, 0.785316", \ + "0.0606748, 0.20512, 0.261892, 0.339703, 0.449896, 0.616406, 0.882663", \ + "0.0760537, 0.280208, 0.357823, 0.460145, 0.598044, 0.791117, 1.07552", \ + "0.0933539, 0.383373, 0.49475, 0.635538, 0.822877, 1.06959, 1.40968", \ + "0.109226, 0.513529, 0.676593, 0.882728, 1.14312, 1.48414, 1.92875" \ ); } fall_transition (TIMING_DELAY_7x7ds1) { index_1 ("0.0186, 0.0966, 0.174, 0.3294, 0.6408, 1.263, 2.5074"); index_2 ("0.001, 0.0468, 0.078, 0.1296, 0.216, 0.36, 0.6"); values ( \ - "0.00967414, 0.0763005, 0.123168, 0.20072, 0.330487, 0.547245, 0.907414", \ - "0.0237819, 0.0896388, 0.131734, 0.204525, 0.331328, 0.547246, 0.907415", \ - "0.0346434, 0.109392, 0.150626, 0.218971, 0.339251, 0.548939, 0.907416", \ - "0.0520596, 0.145391, 0.190315, 0.258369, 0.371732, 0.567492, 0.913542", \ - "0.0800771, 0.208422, 0.260678, 0.335856, 0.451307, 0.639042, 0.959635", \ - "0.12655, 0.313893, 0.378738, 0.47126, 0.602425, 0.801284, 1.1123", \ - "0.205368, 0.481141, 0.57829, 0.695143, 0.862633, 1.08846, 1.43363" \ + "0.00967525, 0.0763051, 0.123182, 0.20073, 0.330507, 0.546871, 0.907472", \ + "0.0237812, 0.0896452, 0.131756, 0.204563, 0.331393, 0.546872, 0.908031", \ + "0.0346439, 0.109396, 0.150583, 0.218983, 0.339269, 0.548978, 0.908032", \ + "0.0520602, 0.145395, 0.190041, 0.258399, 0.371688, 0.567565, 0.913857", \ + "0.0800783, 0.208427, 0.260685, 0.335867, 0.451331, 0.63907, 0.959694", \ + "0.126551, 0.313898, 0.378761, 0.47239, 0.602444, 0.801314, 1.11215", \ + "0.205369, 0.481138, 0.578366, 0.695156, 0.861025, 1.08836, 1.43369" \ ); } } @@ -2632,52 +2632,52 @@ library (sg13g2_stdcell_typ_1p20V_25C) { index_1 ("0.0186, 0.0966, 0.174, 0.3294, 0.6408, 1.263, 2.5074"); index_2 ("0.001, 0.0468, 0.078, 0.1296, 0.216, 0.36, 0.6"); values ( \ - "0.0256576, 0.126793, 0.192863, 0.302735, 0.48705, 0.793115, 1.30372", \ - "0.0455435, 0.165329, 0.232376, 0.342613, 0.526669, 0.833078, 1.3443", \ - "0.0553821, 0.199845, 0.269963, 0.380845, 0.56475, 0.87141, 1.38246", \ - "0.0686253, 0.256, 0.337797, 0.457006, 0.644221, 0.95096, 1.46797", \ - "0.0851704, 0.338831, 0.444117, 0.588405, 0.79587, 1.11265, 1.62431", \ - "0.104878, 0.448813, 0.591902, 0.780096, 1.03777, 1.40023, 1.93967", \ - "0.127395, 0.589119, 0.786847, 1.04653, 1.38782, 1.85252, 2.48946" \ + "0.0256292, 0.126802, 0.192869, 0.302749, 0.487032, 0.793309, 1.30367", \ + "0.0454998, 0.16532, 0.232353, 0.342485, 0.526682, 0.83293, 1.34374", \ + "0.0553824, 0.199825, 0.269956, 0.380794, 0.564845, 0.871395, 1.38245", \ + "0.0686246, 0.255998, 0.337793, 0.456981, 0.64436, 0.950987, 1.46794", \ + "0.0851693, 0.338827, 0.444113, 0.588399, 0.795861, 1.11263, 1.62424", \ + "0.104876, 0.448809, 0.591897, 0.780089, 1.03776, 1.40021, 1.93964", \ + "0.127391, 0.589116, 0.78684, 1.04652, 1.38781, 1.8525, 2.48944" \ ); } rise_transition (TIMING_DELAY_7x7ds1) { index_1 ("0.0186, 0.0966, 0.174, 0.3294, 0.6408, 1.263, 2.5074"); index_2 ("0.001, 0.0468, 0.078, 0.1296, 0.216, 0.36, 0.6"); values ( \ - "0.0169096, 0.154921, 0.248763, 0.404707, 0.665839, 1.10076, 1.82574", \ - "0.033314, 0.159303, 0.250335, 0.404708, 0.66584, 1.1008, 1.82611", \ - "0.0445002, 0.17419, 0.259405, 0.408179, 0.666113, 1.10118, 1.82612", \ - "0.0621286, 0.211433, 0.292721, 0.431795, 0.677089, 1.11006, 1.83164", \ - "0.0907437, 0.28199, 0.367892, 0.502824, 0.731954, 1.13353, 1.83472", \ - "0.137292, 0.396178, 0.499322, 0.647262, 0.877987, 1.25577, 1.90767", \ - "0.217088, 0.570615, 0.711964, 0.894724, 1.15897, 1.5506, 2.1806" \ + "0.0169175, 0.154917, 0.248738, 0.404697, 0.665823, 1.10074, 1.8257", \ + "0.0333518, 0.159277, 0.250318, 0.404698, 0.665824, 1.10084, 1.82571", \ + "0.0444994, 0.174168, 0.259465, 0.408315, 0.665939, 1.10116, 1.82578", \ + "0.0621282, 0.21143, 0.292716, 0.43163, 0.677333, 1.11009, 1.8316", \ + "0.0907432, 0.282006, 0.367887, 0.502946, 0.731978, 1.13351, 1.83479", \ + "0.137292, 0.396175, 0.499317, 0.647254, 0.877973, 1.25581, 1.90763", \ + "0.217087, 0.57061, 0.711959, 0.894717, 1.15895, 1.55054, 2.18057" \ ); } cell_fall (TIMING_DELAY_7x7ds1) { index_1 ("0.0186, 0.0966, 0.174, 0.3294, 0.6408, 1.263, 2.5074"); index_2 ("0.001, 0.0468, 0.078, 0.1296, 0.216, 0.36, 0.6"); values ( \ - "0.0195485, 0.0734104, 0.108003, 0.165136, 0.260761, 0.420137, 0.685802", \ - "0.0385085, 0.119295, 0.156987, 0.215327, 0.311018, 0.470397, 0.736085", \ - "0.0485555, 0.153544, 0.197788, 0.261569, 0.359911, 0.519489, 0.784986", \ - "0.0609801, 0.204693, 0.261862, 0.338974, 0.449869, 0.615789, 0.882277", \ - "0.0772745, 0.280032, 0.357495, 0.459797, 0.597689, 0.790713, 1.07516", \ - "0.0974623, 0.38419, 0.494927, 0.635372, 0.823133, 1.06919, 1.40949", \ - "0.119949, 0.517618, 0.678991, 0.884184, 1.14384, 1.48482, 1.92862" \ + "0.0195442, 0.0734081, 0.108017, 0.165137, 0.260781, 0.420184, 0.685845", \ + "0.0385149, 0.119296, 0.156993, 0.215344, 0.31109, 0.47043, 0.735999", \ + "0.0485563, 0.153548, 0.19779, 0.261578, 0.359929, 0.519497, 0.784982", \ + "0.0609811, 0.204698, 0.2616, 0.339395, 0.449576, 0.615811, 0.882264", \ + "0.0772759, 0.280037, 0.357503, 0.459808, 0.597706, 0.790738, 1.07523", \ + "0.0974645, 0.384196, 0.494936, 0.635385, 0.823153, 1.06922, 1.40954", \ + "0.119763, 0.517626, 0.679003, 0.8842, 1.14386, 1.48485, 1.92861" \ ); } fall_transition (TIMING_DELAY_7x7ds1) { index_1 ("0.0186, 0.0966, 0.174, 0.3294, 0.6408, 1.263, 2.5074"); index_2 ("0.001, 0.0468, 0.078, 0.1296, 0.216, 0.36, 0.6"); values ( \ - "0.00977577, 0.0763064, 0.123127, 0.200716, 0.330501, 0.547271, 0.907455", \ - "0.024096, 0.0898147, 0.131773, 0.20463, 0.331355, 0.547272, 0.908123", \ - "0.0348447, 0.109547, 0.150838, 0.219082, 0.339264, 0.549063, 0.908124", \ - "0.0518548, 0.146048, 0.190305, 0.258636, 0.37168, 0.567979, 0.913599", \ - "0.0795382, 0.208671, 0.260295, 0.336139, 0.451867, 0.639166, 0.959762", \ - "0.125045, 0.313093, 0.378835, 0.472188, 0.602163, 0.801566, 1.11243", \ - "0.20182, 0.478016, 0.57607, 0.693729, 0.861862, 1.08774, 1.43573" \ + "0.00977813, 0.0763142, 0.123125, 0.200775, 0.330522, 0.547306, 0.907513", \ + "0.0241103, 0.0898187, 0.131873, 0.204639, 0.331384, 0.547307, 0.908045", \ + "0.0348453, 0.10955, 0.150841, 0.219096, 0.339287, 0.549017, 0.908046", \ + "0.0518554, 0.146052, 0.190494, 0.258427, 0.371572, 0.568009, 0.914197", \ + "0.0795388, 0.208676, 0.260302, 0.33615, 0.451883, 0.639195, 0.959841", \ + "0.125047, 0.313098, 0.378842, 0.4722, 0.602183, 0.801595, 1.11249", \ + "0.201565, 0.478023, 0.57608, 0.693743, 0.861883, 1.08777, 1.43375" \ ); } } @@ -2689,52 +2689,52 @@ library (sg13g2_stdcell_typ_1p20V_25C) { index_1 ("0.0186, 0.0966, 0.174, 0.3294, 0.6408, 1.263, 2.5074"); index_2 ("0.001, 0.0468, 0.078, 0.1296, 0.216, 0.36, 0.6"); values ( \ - "0.0401992, 0.177198, 0.267732, 0.416975, 0.666553, 1.08196, 1.77466", \ - "0.0660543, 0.212434, 0.303201, 0.452871, 0.702881, 1.11871, 1.81278", \ - "0.0811689, 0.246335, 0.338157, 0.487712, 0.737717, 1.15453, 1.84717", \ - "0.101726, 0.305888, 0.406276, 0.560024, 0.810386, 1.22611, 1.91903", \ - "0.129708, 0.396979, 0.519972, 0.694218, 0.957056, 1.37613, 2.06865", \ - "0.166471, 0.522301, 0.680492, 0.899651, 1.20706, 1.66057, 2.36242", \ - "0.214104, 0.6855, 0.900527, 1.18816, 1.58371, 2.13, 2.91472" \ + "0.0402019, 0.177173, 0.267742, 0.416967, 0.666544, 1.08188, 1.77457", \ + "0.0660595, 0.212441, 0.303211, 0.452842, 0.702816, 1.11876, 1.81249", \ + "0.0811688, 0.24633, 0.338161, 0.487647, 0.737502, 1.15448, 1.84707", \ + "0.101726, 0.305885, 0.406272, 0.560022, 0.810373, 1.22596, 1.91896", \ + "0.129707, 0.396976, 0.519968, 0.694212, 0.957045, 1.37611, 2.06851", \ + "0.166469, 0.522297, 0.680487, 0.899625, 1.20705, 1.66055, 2.36228", \ + "0.214101, 0.685495, 0.900521, 1.18815, 1.58369, 2.12998, 2.91469" \ ); } rise_transition (TIMING_DELAY_7x7ds1) { index_1 ("0.0186, 0.0966, 0.174, 0.3294, 0.6408, 1.263, 2.5074"); index_2 ("0.001, 0.0468, 0.078, 0.1296, 0.216, 0.36, 0.6"); values ( \ - "0.0303965, 0.216342, 0.342549, 0.551001, 0.899844, 1.48167, 2.44954", \ - "0.0442436, 0.218276, 0.342979, 0.551418, 0.899845, 1.48204, 2.45079", \ - "0.0571142, 0.228496, 0.347644, 0.552019, 0.899862, 1.48277, 2.45099", \ - "0.0766289, 0.26134, 0.373501, 0.566817, 0.90436, 1.48278, 2.451", \ - "0.108559, 0.33048, 0.443427, 0.626374, 0.942652, 1.49737, 2.45296", \ - "0.159153, 0.445244, 0.575282, 0.765455, 1.07298, 1.58842, 2.49434", \ - "0.243776, 0.627791, 0.78905, 1.01711, 1.3473, 1.86192, 2.71422" \ + "0.0303964, 0.216339, 0.342542, 0.550992, 0.899828, 1.48153, 2.45116", \ + "0.0442172, 0.218271, 0.342751, 0.551404, 0.899829, 1.48205, 2.45144", \ + "0.0571133, 0.228455, 0.347603, 0.552865, 0.900965, 1.48271, 2.45145", \ + "0.0766284, 0.261362, 0.373494, 0.566814, 0.904342, 1.48272, 2.45146", \ + "0.108558, 0.330513, 0.443421, 0.626366, 0.942636, 1.49735, 2.45527", \ + "0.159152, 0.445241, 0.575279, 0.765511, 1.07299, 1.58839, 2.49321", \ + "0.243775, 0.627788, 0.789044, 1.0171, 1.34729, 1.86189, 2.71418" \ ); } cell_fall (TIMING_DELAY_7x7ds1) { index_1 ("0.0186, 0.0966, 0.174, 0.3294, 0.6408, 1.263, 2.5074"); index_2 ("0.001, 0.0468, 0.078, 0.1296, 0.216, 0.36, 0.6"); values ( \ - "0.0200406, 0.0739098, 0.108519, 0.165749, 0.261548, 0.421173, 0.687107", \ - "0.0394624, 0.119988, 0.157618, 0.216028, 0.3119, 0.471491, 0.737727", \ - "0.0497939, 0.154382, 0.198627, 0.262377, 0.360806, 0.520725, 0.786384", \ - "0.0622819, 0.205823, 0.262563, 0.340039, 0.450943, 0.616969, 0.883554", \ - "0.0789811, 0.281389, 0.358929, 0.461097, 0.599113, 0.792207, 1.0768", \ - "0.099006, 0.385669, 0.496649, 0.637281, 0.824483, 1.07112, 1.41148", \ - "0.121856, 0.518817, 0.680443, 0.886036, 1.14591, 1.48727, 1.9311" \ + "0.0200397, 0.0739131, 0.108518, 0.165774, 0.261565, 0.4212, 0.687158", \ + "0.0394536, 0.119972, 0.157596, 0.216041, 0.311808, 0.471497, 0.73778", \ + "0.0497947, 0.154391, 0.198596, 0.262385, 0.36082, 0.520644, 0.786317", \ + "0.0622829, 0.205828, 0.262507, 0.340049, 0.450588, 0.617266, 0.883622", \ + "0.0789826, 0.28139, 0.358937, 0.461109, 0.599134, 0.792152, 1.0768", \ + "0.0990091, 0.385676, 0.496658, 0.637266, 0.824504, 1.07115, 1.41133", \ + "0.12186, 0.518487, 0.680454, 0.886052, 1.14592, 1.48662, 1.93116" \ ); } fall_transition (TIMING_DELAY_7x7ds1) { index_1 ("0.0186, 0.0966, 0.174, 0.3294, 0.6408, 1.263, 2.5074"); index_2 ("0.001, 0.0468, 0.078, 0.1296, 0.216, 0.36, 0.6"); values ( \ - "0.0124263, 0.0817191, 0.128411, 0.205875, 0.335699, 0.552132, 0.912384", \ - "0.0338059, 0.0951557, 0.136987, 0.209722, 0.336585, 0.552133, 0.912564", \ - "0.0493612, 0.115243, 0.155997, 0.224199, 0.34431, 0.554315, 0.912565", \ - "0.0736089, 0.152706, 0.196239, 0.26397, 0.376428, 0.57291, 0.918305", \ - "0.112072, 0.217945, 0.26727, 0.341726, 0.45736, 0.644001, 0.964696", \ - "0.173456, 0.326512, 0.389617, 0.478921, 0.608484, 0.805631, 1.11757", \ - "0.272196, 0.500366, 0.592182, 0.706812, 0.869318, 1.0948, 1.43857" \ + "0.0124315, 0.081723, 0.128434, 0.20589, 0.335721, 0.55212, 0.912443", \ + "0.0338249, 0.0951694, 0.136999, 0.209733, 0.336427, 0.552121, 0.912646", \ + "0.0493621, 0.11525, 0.155986, 0.224199, 0.344398, 0.554064, 0.912647", \ + "0.0736138, 0.152711, 0.196203, 0.26398, 0.376591, 0.57286, 0.91839", \ + "0.112073, 0.217941, 0.267242, 0.341738, 0.457357, 0.64415, 0.965293", \ + "0.173456, 0.326507, 0.389626, 0.478921, 0.608506, 0.805661, 1.11765", \ + "0.272196, 0.500385, 0.59218, 0.706826, 0.869357, 1.09538, 1.43852" \ ); } } @@ -2744,26 +2744,26 @@ library (sg13g2_stdcell_typ_1p20V_25C) { index_1 ("0.0186, 0.0966, 0.174, 0.3294, 0.6408, 1.263, 2.5074"); index_2 ("0.001, 0.0468, 0.078, 0.1296, 0.216, 0.36, 0.6"); values ( \ - "0.00887075, 0.00950064, 0.00945193, 0.00936869, 0.00908235, 0.00867605, 0.00805005", \ - "0.00840088, 0.00913503, 0.00918922, 0.00919149, 0.00904067, 0.00865928, 0.00825515", \ - "0.008341, 0.00898725, 0.00900839, 0.0090379, 0.00894765, 0.0086349, 0.00810571", \ - "0.00848347, 0.00871907, 0.00886871, 0.00883939, 0.00933418, 0.00850025, 0.00802707", \ - "0.00945978, 0.00899096, 0.00894685, 0.0088199, 0.00934508, 0.00861676, 0.00801376", \ - "0.0127427, 0.010397, 0.00995804, 0.00967571, 0.00916473, 0.00948677, 0.00821758", \ - "0.020951, 0.0153673, 0.0140809, 0.0129453, 0.0118206, 0.0106629, 0.00986303" \ + "0.00887027, 0.00950117, 0.00946205, 0.00939019, 0.00908414, 0.00867691, 0.00805066", \ + "0.00840954, 0.00912741, 0.00919001, 0.00923662, 0.00904109, 0.00867265, 0.00825493", \ + "0.00834092, 0.00898711, 0.00900592, 0.0090144, 0.00895753, 0.00874238, 0.00826591", \ + "0.00848481, 0.00869291, 0.00887543, 0.00887061, 0.008827, 0.00854209, 0.0080412", \ + "0.00945918, 0.00898439, 0.00894997, 0.00882194, 0.00934527, 0.00844643, 0.00807007", \ + "0.012745, 0.0103969, 0.00995238, 0.00967067, 0.00912763, 0.00948647, 0.00821613", \ + "0.020951, 0.0153668, 0.014082, 0.0129352, 0.011913, 0.0106329, 0.00984994" \ ); } fall_power (POWER_7x7ds1) { index_1 ("0.0186, 0.0966, 0.174, 0.3294, 0.6408, 1.263, 2.5074"); index_2 ("0.001, 0.0468, 0.078, 0.1296, 0.216, 0.36, 0.6"); values ( \ - "0.00559945, 0.00572306, 0.00566694, 0.00555554, 0.00536883, 0.00499426, 0.00431782", \ - "0.00501565, 0.0054729, 0.00547038, 0.00532838, 0.00520542, 0.00493531, 0.00428158", \ - "0.0050904, 0.00527388, 0.0053696, 0.00523236, 0.00518167, 0.00480025, 0.00416589", \ - "0.00568551, 0.00542921, 0.00532251, 0.00528959, 0.00521445, 0.00518674, 0.00404098", \ - "0.00727512, 0.00611348, 0.00594074, 0.00554812, 0.00528629, 0.0057059, 0.00434756", \ - "0.0108678, 0.00827241, 0.00772472, 0.00709579, 0.00652425, 0.00531041, 0.00557268", \ - "0.0189122, 0.0142511, 0.0127706, 0.0111039, 0.00976936, 0.00854104, 0.00689683" \ + "0.00559958, 0.00572434, 0.0056645, 0.00555351, 0.00536779, 0.00503487, 0.00431686", \ + "0.00501559, 0.00545365, 0.00542754, 0.00533319, 0.00521487, 0.00492786, 0.00424933", \ + "0.00508941, 0.00527429, 0.0053693, 0.00522733, 0.00515017, 0.00477373, 0.00427518", \ + "0.00568483, 0.00542871, 0.00532244, 0.00527666, 0.00561506, 0.00527552, 0.00407075", \ + "0.00727582, 0.0061152, 0.00593804, 0.00554842, 0.00528428, 0.00570541, 0.00437787", \ + "0.0108698, 0.00827572, 0.00772352, 0.00710411, 0.00652176, 0.00531036, 0.00567644", \ + "0.0189125, 0.0142514, 0.0127708, 0.011104, 0.00976947, 0.00859004, 0.0068841" \ ); } } @@ -2773,26 +2773,26 @@ library (sg13g2_stdcell_typ_1p20V_25C) { index_1 ("0.0186, 0.0966, 0.174, 0.3294, 0.6408, 1.263, 2.5074"); index_2 ("0.001, 0.0468, 0.078, 0.1296, 0.216, 0.36, 0.6"); values ( \ - "0.00942476, 0.00950205, 0.00942486, 0.00932536, 0.00906396, 0.00864219, 0.00807816", \ - "0.00907716, 0.00929798, 0.00932058, 0.00919372, 0.00900119, 0.00862526, 0.00813761", \ - "0.00899693, 0.00925051, 0.00923494, 0.00918872, 0.00896594, 0.00865266, 0.00816003", \ - "0.00906754, 0.00912965, 0.00920291, 0.00906662, 0.00892457, 0.00856567, 0.00815284", \ - "0.00984405, 0.00948766, 0.00936951, 0.00916357, 0.00944048, 0.00882372, 0.00811126", \ - "0.012668, 0.0108943, 0.0104717, 0.0101584, 0.00954464, 0.00954384, 0.00833408", \ - "0.0200273, 0.0157682, 0.0146133, 0.0134668, 0.0124077, 0.0109665, 0.0101729" \ + "0.00942544, 0.00950152, 0.00942789, 0.00932725, 0.00905528, 0.00865366, 0.0080567", \ + "0.00907608, 0.00930556, 0.00931477, 0.00931823, 0.00899435, 0.00862936, 0.0081387", \ + "0.00899519, 0.00930351, 0.00919959, 0.00919698, 0.00896598, 0.00865337, 0.00809436", \ + "0.00906816, 0.00912831, 0.00920981, 0.00906816, 0.00916193, 0.00855295, 0.00811808", \ + "0.00984561, 0.00948778, 0.00937468, 0.00916621, 0.00930683, 0.00857105, 0.00812349", \ + "0.012668, 0.0108935, 0.0104643, 0.0101715, 0.00954533, 0.00955639, 0.00835658", \ + "0.0200271, 0.0157683, 0.0145726, 0.0134696, 0.0124088, 0.0110804, 0.0102785" \ ); } fall_power (POWER_7x7ds1) { index_1 ("0.0186, 0.0966, 0.174, 0.3294, 0.6408, 1.263, 2.5074"); index_2 ("0.001, 0.0468, 0.078, 0.1296, 0.216, 0.36, 0.6"); values ( \ - "0.00897889, 0.00897514, 0.00890361, 0.00879474, 0.0086135, 0.00819549, 0.00756452", \ - "0.00844515, 0.00879351, 0.00880635, 0.00858622, 0.00847204, 0.0081175, 0.00749475", \ - "0.00834644, 0.00859746, 0.0086906, 0.00853375, 0.0086316, 0.00815362, 0.00751964", \ - "0.00846421, 0.00864332, 0.00860548, 0.00853491, 0.00856576, 0.0082599, 0.00725569", \ - "0.00935208, 0.00893188, 0.00888036, 0.00877743, 0.00848066, 0.00901246, 0.00797787", \ - "0.0122689, 0.0104334, 0.0100161, 0.00965953, 0.00941284, 0.00859385, 0.00888308", \ - "0.0194127, 0.01521, 0.0140762, 0.0128749, 0.0119561, 0.0109429, 0.00956677" \ + "0.00897837, 0.00897447, 0.00890608, 0.00877064, 0.00861259, 0.00826164, 0.00756493", \ + "0.00843982, 0.00879505, 0.00877436, 0.00861479, 0.00847564, 0.00811693, 0.00757864", \ + "0.00835258, 0.00859772, 0.0086908, 0.0085338, 0.0084051, 0.00815365, 0.00732335", \ + "0.00846467, 0.00864324, 0.00860499, 0.00853484, 0.00854632, 0.00824558, 0.00728573", \ + "0.00935269, 0.0089342, 0.00890128, 0.00879564, 0.00848055, 0.00841716, 0.00781448", \ + "0.0122677, 0.0104311, 0.0100137, 0.0096593, 0.00940864, 0.00858626, 0.00888614", \ + "0.019413, 0.0152102, 0.014076, 0.0128752, 0.0119637, 0.0109429, 0.00957971" \ ); } } @@ -2803,26 +2803,26 @@ library (sg13g2_stdcell_typ_1p20V_25C) { index_1 ("0.0186, 0.0966, 0.174, 0.3294, 0.6408, 1.263, 2.5074"); index_2 ("0.001, 0.0468, 0.078, 0.1296, 0.216, 0.36, 0.6"); values ( \ - "0.005139, 0.00578815, 0.00577273, 0.00567234, 0.00543038, 0.00502162, 0.00442653", \ - "0.00486547, 0.00529501, 0.00538856, 0.00544097, 0.00524652, 0.00494011, 0.00452332", \ - "0.00517735, 0.00525329, 0.0052133, 0.00520846, 0.00516108, 0.00498324, 0.00438298", \ - "0.00583946, 0.00525459, 0.00530549, 0.00514479, 0.00538763, 0.00469804, 0.00426927", \ - "0.00757275, 0.00615621, 0.00582282, 0.00550153, 0.00551839, 0.00486243, 0.00432172", \ - "0.0117367, 0.00869908, 0.00795414, 0.00735839, 0.00623537, 0.00615068, 0.00480374", \ - "0.0208126, 0.0151362, 0.0136218, 0.0121684, 0.0104561, 0.00843744, 0.00708519" \ + "0.00514621, 0.00578797, 0.00577588, 0.00567107, 0.00543739, 0.00501726, 0.00448777", \ + "0.00486423, 0.00529796, 0.0053695, 0.00543973, 0.00525414, 0.00495049, 0.00463505", \ + "0.00517791, 0.00525914, 0.00521445, 0.00528993, 0.00527116, 0.00497698, 0.00440574", \ + "0.0058389, 0.00525847, 0.00530591, 0.00514783, 0.00538771, 0.00471733, 0.00426527", \ + "0.00757202, 0.00616308, 0.00582349, 0.00552903, 0.00533904, 0.00486353, 0.0043675", \ + "0.0117364, 0.00869782, 0.00795775, 0.00738932, 0.00626603, 0.00619783, 0.00472236", \ + "0.0208118, 0.0151374, 0.0136149, 0.0121499, 0.0104645, 0.00843758, 0.00709322" \ ); } fall_power (POWER_7x7ds1) { index_1 ("0.0186, 0.0966, 0.174, 0.3294, 0.6408, 1.263, 2.5074"); index_2 ("0.001, 0.0468, 0.078, 0.1296, 0.216, 0.36, 0.6"); values ( \ - "0.00610109, 0.0071122, 0.00707095, 0.00697096, 0.00677079, 0.00648325, 0.0057605", \ - "0.00576607, 0.00673989, 0.00688878, 0.00692206, 0.00709211, 0.00653303, 0.0059467", \ - "0.00600274, 0.00661689, 0.00666916, 0.00678396, 0.00726164, 0.00713667, 0.00581015", \ - "0.00677594, 0.00658204, 0.00672357, 0.00669121, 0.00660802, 0.00695351, 0.00569154", \ - "0.00868381, 0.00710284, 0.00704089, 0.00706457, 0.00691385, 0.00631064, 0.0068824", \ - "0.0130334, 0.00944116, 0.0088018, 0.00822648, 0.00779667, 0.00746044, 0.00645614", \ - "0.0220662, 0.0159519, 0.0141363, 0.0126577, 0.010917, 0.00990117, 0.00877712" \ + "0.00610599, 0.00711053, 0.00706298, 0.00696655, 0.00676953, 0.00643522, 0.00576516", \ + "0.00576995, 0.00673472, 0.00689288, 0.00692439, 0.00679154, 0.00652647, 0.00592733", \ + "0.0060032, 0.00664106, 0.0066632, 0.00679272, 0.00730277, 0.00642149, 0.00579105", \ + "0.00677255, 0.00657817, 0.00671804, 0.00659937, 0.00650447, 0.00700599, 0.00642839", \ + "0.00868365, 0.00710249, 0.00705848, 0.00706641, 0.00695463, 0.0062604, 0.00706913", \ + "0.0130344, 0.00943414, 0.0087959, 0.00823785, 0.00780692, 0.00746404, 0.00623369", \ + "0.0220656, 0.015953, 0.0141398, 0.0126568, 0.0109266, 0.0098826, 0.00873757" \ ); } } @@ -2833,26 +2833,26 @@ library (sg13g2_stdcell_typ_1p20V_25C) { index_1 ("0.0186, 0.0966, 0.174, 0.3294, 0.6408, 1.263, 2.5074"); index_2 ("0.001, 0.0468, 0.078, 0.1296, 0.216, 0.36, 0.6"); values ( \ - "0.00431478, 0.00523173, 0.00523981, 0.00512757, 0.00488527, 0.00452028, 0.00390329", \ - "0.00426335, 0.00475985, 0.00480992, 0.00487081, 0.00470892, 0.00443346, 0.0040027", \ - "0.0046864, 0.00465414, 0.00465632, 0.00472027, 0.00464478, 0.00441239, 0.00390667", \ - "0.00547513, 0.00473943, 0.00473575, 0.00461663, 0.00517901, 0.00417591, 0.0038442", \ - "0.00741922, 0.00566501, 0.00531137, 0.00499554, 0.00490345, 0.00424463, 0.00396695", \ - "0.0118716, 0.00830295, 0.0074944, 0.00685679, 0.00569043, 0.00556857, 0.00425171", \ - "0.021272, 0.0148713, 0.0132697, 0.0117516, 0.00996287, 0.00810875, 0.00655686" \ + "0.00431239, 0.00522966, 0.00523752, 0.00512688, 0.00490083, 0.00453779, 0.00392181", \ + "0.00426415, 0.00475008, 0.00481329, 0.0048351, 0.00471146, 0.00443486, 0.00401016", \ + "0.00468571, 0.00468454, 0.00473339, 0.00468656, 0.0046307, 0.00430903, 0.00382918", \ + "0.00547732, 0.00472944, 0.00473588, 0.00460904, 0.0052538, 0.00420704, 0.00385233", \ + "0.00742145, 0.00566538, 0.00534094, 0.00498296, 0.00490528, 0.00418714, 0.0037501", \ + "0.0118724, 0.00830225, 0.00749475, 0.00684661, 0.00575984, 0.00558986, 0.00415272", \ + "0.0212728, 0.0148701, 0.0132677, 0.0117548, 0.00993794, 0.00805016, 0.00665962" \ ); } fall_power (POWER_7x7ds1) { index_1 ("0.0186, 0.0966, 0.174, 0.3294, 0.6408, 1.263, 2.5074"); index_2 ("0.001, 0.0468, 0.078, 0.1296, 0.216, 0.36, 0.6"); values ( \ - "0.00286358, 0.00389808, 0.00383741, 0.00374035, 0.00359407, 0.00327257, 0.00260532", \ - "0.00251867, 0.003529, 0.00362522, 0.0037705, 0.00419411, 0.00330088, 0.00266443", \ - "0.00276483, 0.00341082, 0.00345169, 0.00353597, 0.0039789, 0.00377611, 0.00259547", \ - "0.00355602, 0.00335473, 0.00351858, 0.00345686, 0.00336013, 0.00374099, 0.00302894", \ - "0.00552545, 0.00390153, 0.00394656, 0.0038409, 0.00366814, 0.00308164, 0.00326714", \ - "0.0099963, 0.00629755, 0.00557011, 0.00506712, 0.00473567, 0.00446598, 0.00343281", \ - "0.0191473, 0.0127891, 0.01107, 0.00941432, 0.00792247, 0.00667797, 0.00576427" \ + "0.00286253, 0.00393175, 0.00383674, 0.00374236, 0.00359298, 0.00328141, 0.00260197", \ + "0.00251785, 0.00352311, 0.00364836, 0.00394769, 0.00374478, 0.00328166, 0.00272391", \ + "0.00276568, 0.00341127, 0.00349404, 0.00356118, 0.00400471, 0.00378451, 0.00260853", \ + "0.00355445, 0.00335631, 0.00350098, 0.0035466, 0.00335038, 0.00397252, 0.0032615", \ + "0.00552588, 0.0039063, 0.00394685, 0.00387893, 0.00372114, 0.00309341, 0.00326613", \ + "0.0099963, 0.00629703, 0.0055544, 0.00517695, 0.00476255, 0.00446567, 0.00310978", \ + "0.019147, 0.0127885, 0.0110742, 0.0094165, 0.00775093, 0.00666708, 0.00567359" \ ); } } @@ -2863,26 +2863,26 @@ library (sg13g2_stdcell_typ_1p20V_25C) { index_1 ("0.0186, 0.0966, 0.174, 0.3294, 0.6408, 1.263, 2.5074"); index_2 ("0.001, 0.0468, 0.078, 0.1296, 0.216, 0.36, 0.6"); values ( \ - "0.00431505, 0.00530775, 0.00522684, 0.00513056, 0.00494798, 0.00485766, 0.00458632", \ - "0.00430171, 0.00487837, 0.00482695, 0.00484422, 0.00474329, 0.00440184, 0.00447311", \ - "0.00475726, 0.00464051, 0.0047836, 0.00470448, 0.00462931, 0.0047152, 0.00436108", \ - "0.00559802, 0.00484176, 0.00470116, 0.00482768, 0.00447602, 0.00528989, 0.00527399", \ - "0.00766647, 0.00582388, 0.00547076, 0.0049712, 0.0049362, 0.00428805, 0.0043518", \ - "0.0123871, 0.00868252, 0.00780559, 0.00705761, 0.00600523, 0.0052977, 0.00509201", \ - "0.0222531, 0.0155836, 0.0139055, 0.0120017, 0.0102661, 0.00851772, 0.00626074" \ + "0.0043115, 0.00531096, 0.00522494, 0.00513373, 0.00494677, 0.00479423, 0.00481698", \ + "0.00431571, 0.004844, 0.00484787, 0.00482164, 0.00474436, 0.00473636, 0.0043855", \ + "0.00475625, 0.00463744, 0.00474078, 0.00471458, 0.00460403, 0.0047148, 0.00442768", \ + "0.00559744, 0.00483434, 0.00470117, 0.00486468, 0.00452444, 0.00529537, 0.0053157", \ + "0.00766377, 0.00582423, 0.00547107, 0.00498938, 0.00495108, 0.00463688, 0.00499819", \ + "0.0123871, 0.00868317, 0.00780562, 0.00705499, 0.00600518, 0.00525411, 0.00507973", \ + "0.0222542, 0.0155852, 0.0139056, 0.0119971, 0.0102666, 0.00853609, 0.006237" \ ); } fall_power (POWER_7x7ds1) { index_1 ("0.0186, 0.0966, 0.174, 0.3294, 0.6408, 1.263, 2.5074"); index_2 ("0.001, 0.0468, 0.078, 0.1296, 0.216, 0.36, 0.6"); values ( \ - "0.00272797, 0.00382431, 0.00369469, 0.00362728, 0.00346974, 0.0031438, 0.00248777", \ - "0.00243743, 0.00331813, 0.00347233, 0.00370325, 0.00331575, 0.0031146, 0.00266703", \ - "0.00273375, 0.00318733, 0.00324136, 0.00334988, 0.00363269, 0.00342298, 0.00237342", \ - "0.00358856, 0.00323808, 0.00337006, 0.00327361, 0.00319391, 0.00374386, 0.00287091", \ - "0.00565136, 0.00384724, 0.00373966, 0.00369439, 0.0035366, 0.00289414, 0.00305484", \ - "0.0102501, 0.00644665, 0.00565151, 0.00511659, 0.00472568, 0.00416385, 0.00324344", \ - "0.0199478, 0.013366, 0.0115112, 0.00973405, 0.00808353, 0.00669115, 0.00578203" \ + "0.00272801, 0.00381978, 0.00369812, 0.00363579, 0.0034703, 0.00314841, 0.00248768", \ + "0.00243836, 0.00333268, 0.00347047, 0.00370415, 0.00332499, 0.00311322, 0.00254775", \ + "0.00273526, 0.00319716, 0.00324058, 0.0033536, 0.00359981, 0.00357996, 0.00236547", \ + "0.00358841, 0.0032303, 0.00333472, 0.00330125, 0.00309751, 0.00374429, 0.00322431", \ + "0.00565133, 0.00384736, 0.00373905, 0.00370865, 0.0035644, 0.00293591, 0.00305758", \ + "0.0102501, 0.0064474, 0.00565162, 0.00511111, 0.00471814, 0.00416177, 0.0028816", \ + "0.0199609, 0.0133647, 0.0115107, 0.009734, 0.0080838, 0.00666824, 0.00553535" \ ); } } @@ -2892,26 +2892,26 @@ library (sg13g2_stdcell_typ_1p20V_25C) { index_1 ("0.0186, 0.0966, 0.174, 0.3294, 0.6408, 1.263, 2.5074"); index_2 ("0.001, 0.0468, 0.078, 0.1296, 0.216, 0.36, 0.6"); values ( \ - "0.00431505, 0.00530775, 0.00522684, 0.00513056, 0.00494798, 0.00485766, 0.00458632", \ - "0.00430171, 0.00487837, 0.00482695, 0.00484422, 0.00474329, 0.00440184, 0.00447311", \ - "0.00475726, 0.00464051, 0.0047836, 0.00470448, 0.00462931, 0.0047152, 0.00436108", \ - "0.00559802, 0.00484176, 0.00470116, 0.00482768, 0.00447602, 0.00528989, 0.00527399", \ - "0.00766647, 0.00582388, 0.00547076, 0.0049712, 0.0049362, 0.00428805, 0.0043518", \ - "0.0123871, 0.00868252, 0.00780559, 0.00705761, 0.00600523, 0.0052977, 0.00509201", \ - "0.0222531, 0.0155836, 0.0139055, 0.0120017, 0.0102661, 0.00851772, 0.00626074" \ + "0.0043115, 0.00531096, 0.00522494, 0.00513373, 0.00494677, 0.00479423, 0.00481698", \ + "0.00431571, 0.004844, 0.00484787, 0.00482164, 0.00474436, 0.00473636, 0.0043855", \ + "0.00475625, 0.00463744, 0.00474078, 0.00471458, 0.00460403, 0.0047148, 0.00442768", \ + "0.00559744, 0.00483434, 0.00470117, 0.00486468, 0.00452444, 0.00529537, 0.0053157", \ + "0.00766377, 0.00582423, 0.00547107, 0.00498938, 0.00495108, 0.00463688, 0.00499819", \ + "0.0123871, 0.00868317, 0.00780562, 0.00705499, 0.00600518, 0.00525411, 0.00507973", \ + "0.0222542, 0.0155852, 0.0139056, 0.0119971, 0.0102666, 0.00853609, 0.006237" \ ); } fall_power (POWER_7x7ds1) { index_1 ("0.0186, 0.0966, 0.174, 0.3294, 0.6408, 1.263, 2.5074"); index_2 ("0.001, 0.0468, 0.078, 0.1296, 0.216, 0.36, 0.6"); values ( \ - "0.00286358, 0.00389808, 0.00383741, 0.00374035, 0.00359407, 0.00327257, 0.00260532", \ - "0.00251867, 0.003529, 0.00362522, 0.0037705, 0.00419411, 0.00330088, 0.00266443", \ - "0.00276483, 0.00341082, 0.00345169, 0.00353597, 0.0039789, 0.00377611, 0.00259547", \ - "0.00355602, 0.00335473, 0.00351858, 0.00345686, 0.00336013, 0.00374099, 0.00302894", \ - "0.00552545, 0.00390153, 0.00394656, 0.0038409, 0.00366814, 0.00308164, 0.00326714", \ - "0.0099963, 0.00629755, 0.00557011, 0.00506712, 0.00473567, 0.00446598, 0.00343281", \ - "0.0191473, 0.0127891, 0.01107, 0.00941432, 0.00792247, 0.00667797, 0.00576427" \ + "0.00286253, 0.00393175, 0.00383674, 0.00374236, 0.00359298, 0.00328141, 0.00260197", \ + "0.00251785, 0.00352311, 0.00364836, 0.00394769, 0.00374478, 0.00328166, 0.00272391", \ + "0.00276568, 0.00341127, 0.00349404, 0.00356118, 0.00400471, 0.00378451, 0.00260853", \ + "0.00355445, 0.00335631, 0.00350098, 0.0035466, 0.00335038, 0.00397252, 0.0032615", \ + "0.00552588, 0.0039063, 0.00394685, 0.00387893, 0.00372114, 0.00309341, 0.00326613", \ + "0.0099963, 0.00629703, 0.0055544, 0.00517695, 0.00476255, 0.00446567, 0.00310978", \ + "0.019147, 0.0127885, 0.0110742, 0.0094165, 0.00775093, 0.00666708, 0.00567359" \ ); } } @@ -2919,29 +2919,29 @@ library (sg13g2_stdcell_typ_1p20V_25C) { pin (A1) { direction : "input"; max_transition : 2.5074; - capacitance : 0.00581304; - rise_capacitance : 0.00575811; - rise_capacitance_range (0.00575811, 0.00575811); - fall_capacitance : 0.00586796; - fall_capacitance_range (0.00586796, 0.00586796); + capacitance : 0.00581309; + rise_capacitance : 0.00575817; + rise_capacitance_range (0.00526931, 0.00624838); + fall_capacitance : 0.005868; + fall_capacitance_range (0.0050207, 0.00670681); } pin (A2) { direction : "input"; max_transition : 2.5074; - capacitance : 0.00608028; - rise_capacitance : 0.00617136; - rise_capacitance_range (0.00617136, 0.00617136); - fall_capacitance : 0.0059892; - fall_capacitance_range (0.0059892, 0.0059892); + capacitance : 0.00608046; + rise_capacitance : 0.00617148; + rise_capacitance_range (0.00540947, 0.00684975); + fall_capacitance : 0.00598943; + fall_capacitance_range (0.00533975, 0.00670063); } pin (B1) { direction : "input"; max_transition : 2.5074; capacitance : 0.00564011; - rise_capacitance : 0.00578165; - rise_capacitance_range (0.00578165, 0.00578165); - fall_capacitance : 0.00549856; - fall_capacitance_range (0.00549856, 0.00549856); + rise_capacitance : 0.00578158; + rise_capacitance_range (0.00459888, 0.0067687); + fall_capacitance : 0.00549863; + fall_capacitance_range (0.00491808, 0.00625795); } } cell (sg13g2_a221oi_1) { @@ -5010,113 +5010,113 @@ library (sg13g2_stdcell_typ_1p20V_25C) { max_transition : 2.5074; capacitance : 0.00296655; rise_capacitance : 0.00294125; - rise_capacitance_range (0.00294125, 0.00294125); + rise_capacitance_range (0.00277919, 0.00314756); fall_capacitance : 0.00299185; - fall_capacitance_range (0.00299185, 0.00299185); + fall_capacitance_range (0.00262751, 0.00337243); } pin (A2) { direction : "input"; max_transition : 2.5074; capacitance : 0.00300247; rise_capacitance : 0.00305076; - rise_capacitance_range (0.00305076, 0.00305076); + rise_capacitance_range (0.00268065, 0.00336373); fall_capacitance : 0.00295419; - fall_capacitance_range (0.00295419, 0.00295419); + fall_capacitance_range (0.0026614, 0.00330309); } pin (B1) { direction : "input"; max_transition : 2.5074; capacitance : 0.00292453; rise_capacitance : 0.00291621; - rise_capacitance_range (0.00291621, 0.00291621); + rise_capacitance_range (0.00258788, 0.00321765); fall_capacitance : 0.00293285; - fall_capacitance_range (0.00293285, 0.00293285); + fall_capacitance_range (0.00251709, 0.00332981); } pin (B2) { direction : "input"; max_transition : 2.5074; capacitance : 0.00302059; rise_capacitance : 0.00308525; - rise_capacitance_range (0.00308525, 0.00308525); + rise_capacitance_range (0.00260106, 0.00347111); fall_capacitance : 0.00295594; - fall_capacitance_range (0.00295594, 0.00295594); + fall_capacitance_range (0.00261471, 0.00331264); } pin (C1) { direction : "input"; max_transition : 2.5074; capacitance : 0.0028559; rise_capacitance : 0.00293337; - rise_capacitance_range (0.00293337, 0.00293337); + rise_capacitance_range (0.00244284, 0.00338054); fall_capacitance : 0.00277843; - fall_capacitance_range (0.00277843, 0.00277843); + fall_capacitance_range (0.00253788, 0.00303613); } } cell (sg13g2_a22oi_1) { area : 10.8486; cell_footprint : "a22oi"; - cell_leakage_power : 138.865; + cell_leakage_power : 138.885; leakage_power () { - value : 98.1722; + value : 98.1921; when : "!A1&!A2&!B1&!B2&Y"; } leakage_power () { - value : 92.4596; + value : 92.4795; when : "!A1&!A2&!B1&B2&Y"; } leakage_power () { - value : 116.9; + value : 116.92; when : "!A1&!A2&B1&!B2&Y"; } leakage_power () { - value : 207.182; + value : 207.202; when : "!A1&!A2&B1&B2&!Y"; } leakage_power () { - value : 116.972; + value : 116.992; when : "!A1&A2&!B1&!B2&Y"; } leakage_power () { - value : 111.259; + value : 111.279; when : "!A1&A2&!B1&B2&Y"; } leakage_power () { - value : 135.699; + value : 135.719; when : "!A1&A2&B1&!B2&Y"; } leakage_power () { - value : 210.347; + value : 210.367; when : "!A1&A2&B1&B2&!Y"; } leakage_power () { - value : 92.4413; + value : 92.4612; when : "A1&!A2&!B1&!B2&Y"; } leakage_power () { - value : 86.7286; + value : 86.7485; when : "A1&!A2&!B1&B2&Y"; } leakage_power () { - value : 111.169; + value : 111.189; when : "A1&!A2&B1&!B2&Y"; } leakage_power () { - value : 210.258; + value : 210.277; when : "A1&!A2&B1&B2&!Y"; } leakage_power () { - value : 150.671; + value : 150.691; when : "A1&A2&!B1&!B2&!Y"; } leakage_power () { - value : 175.085; + value : 175.105; when : "A1&A2&!B1&B2&!Y"; } leakage_power () { - value : 175.084; + value : 175.104; when : "A1&A2&B1&!B2&!Y"; } leakage_power () { - value : 131.41; + value : 131.43; when : "A1&A2&B1&B2&!Y"; } pin (Y) { @@ -5134,52 +5134,52 @@ library (sg13g2_stdcell_typ_1p20V_25C) { index_1 ("0.0186, 0.0966, 0.174, 0.3294, 0.6408, 1.263, 2.5074"); index_2 ("0.001, 0.0234, 0.039, 0.0648, 0.108, 0.18, 0.3"); values ( \ - "0.0540753, 0.18555, 0.275741, 0.42466, 0.673304, 1.08868, 1.77972", \ - "0.082028, 0.218856, 0.30942, 0.458536, 0.708053, 1.12288, 1.8149", \ - "0.0986505, 0.246579, 0.337953, 0.48735, 0.737021, 1.15301, 1.84438", \ - "0.11957, 0.295256, 0.392474, 0.545019, 0.79541, 1.21098, 1.90293", \ - "0.143134, 0.372397, 0.485575, 0.65223, 0.911946, 1.33081, 2.02332", \ - "0.166266, 0.481339, 0.623826, 0.822824, 1.11447, 1.55669, 2.25885", \ - "0.194289, 0.6241, 0.817698, 1.07641, 1.43095, 1.94219, 2.70033" \ + "0.0540467, 0.185571, 0.275581, 0.424682, 0.673599, 1.08866, 1.77972", \ + "0.0820451, 0.218831, 0.309351, 0.458643, 0.708036, 1.12288, 1.81536", \ + "0.0986501, 0.246579, 0.337952, 0.487337, 0.737008, 1.15299, 1.84437", \ + "0.11957, 0.295255, 0.392473, 0.545018, 0.79538, 1.21111, 1.90292", \ + "0.143133, 0.372396, 0.485574, 0.65223, 0.911975, 1.3308, 2.02324", \ + "0.166266, 0.481338, 0.623824, 0.822823, 1.11446, 1.55669, 2.25884", \ + "0.194288, 0.624139, 0.817696, 1.07641, 1.43094, 1.94218, 2.70032" \ ); } rise_transition (TIMING_DELAY_7x7ds1) { index_1 ("0.0186, 0.0966, 0.174, 0.3294, 0.6408, 1.263, 2.5074"); index_2 ("0.001, 0.0234, 0.039, 0.0648, 0.108, 0.18, 0.3"); values ( \ - "0.0342488, 0.215025, 0.340804, 0.548732, 0.89708, 1.47711, 2.44356", \ - "0.0415358, 0.215926, 0.34096, 0.549879, 0.897081, 1.47758, 2.44515", \ - "0.0512265, 0.221524, 0.343564, 0.54988, 0.897082, 1.47846, 2.44516", \ - "0.0703932, 0.24218, 0.359201, 0.557854, 0.899849, 1.47847, 2.44517", \ - "0.107248, 0.29149, 0.40544, 0.595926, 0.923249, 1.48696, 2.44579", \ - "0.172335, 0.386741, 0.504163, 0.692558, 1.0093, 1.54601, 2.47311", \ - "0.273669, 0.552108, 0.686969, 0.885989, 1.20599, 1.72965, 2.61647" \ + "0.0342481, 0.215024, 0.340801, 0.548729, 0.896978, 1.47711, 2.44355", \ + "0.0415558, 0.215894, 0.340802, 0.548802, 0.896979, 1.47712, 2.44409", \ + "0.0512263, 0.221524, 0.343563, 0.549079, 0.89698, 1.47843, 2.4441", \ + "0.070393, 0.242179, 0.3592, 0.558044, 0.899855, 1.47844, 2.44471", \ + "0.107248, 0.291489, 0.405438, 0.595882, 0.92334, 1.48696, 2.44693", \ + "0.172335, 0.38674, 0.504163, 0.692568, 1.00929, 1.54616, 2.47311", \ + "0.273669, 0.55236, 0.686968, 0.885987, 1.20599, 1.72964, 2.61663" \ ); } cell_fall (TIMING_DELAY_7x7ds1) { index_1 ("0.0186, 0.0966, 0.174, 0.3294, 0.6408, 1.263, 2.5074"); index_2 ("0.001, 0.0234, 0.039, 0.0648, 0.108, 0.18, 0.3"); values ( \ - "0.0444888, 0.13967, 0.203851, 0.309468, 0.486088, 0.779738, 1.26916", \ - "0.0760862, 0.181709, 0.246306, 0.351995, 0.528418, 0.822452, 1.31172", \ - "0.0964667, 0.219119, 0.286968, 0.394017, 0.570446, 0.864198, 1.35382", \ - "0.125164, 0.278817, 0.357611, 0.473245, 0.653671, 0.947439, 1.43627", \ - "0.165257, 0.368365, 0.467166, 0.605635, 0.80794, 1.11461, 1.60538", \ - "0.218782, 0.495993, 0.626001, 0.805434, 1.05386, 1.40935, 1.93562", \ - "0.289321, 0.667657, 0.847273, 1.08691, 1.41549, 1.86299, 2.49097" \ + "0.0444888, 0.139666, 0.203849, 0.309472, 0.486235, 0.779753, 1.26917", \ + "0.0760837, 0.181741, 0.246312, 0.352002, 0.528582, 0.822493, 1.31173", \ + "0.0964667, 0.219116, 0.28697, 0.39402, 0.570451, 0.864168, 1.35384", \ + "0.125164, 0.278818, 0.357613, 0.47325, 0.653676, 0.94753, 1.43654", \ + "0.165258, 0.368367, 0.467169, 0.605638, 0.807945, 1.11462, 1.60529", \ + "0.218782, 0.495995, 0.626004, 0.805438, 1.05386, 1.40936, 1.93564", \ + "0.289314, 0.66766, 0.847276, 1.08691, 1.4155, 1.863, 2.49095" \ ); } fall_transition (TIMING_DELAY_7x7ds1) { index_1 ("0.0186, 0.0966, 0.174, 0.3294, 0.6408, 1.263, 2.5074"); index_2 ("0.001, 0.0234, 0.039, 0.0648, 0.108, 0.18, 0.3"); values ( \ - "0.0332534, 0.1557, 0.240766, 0.381614, 0.617213, 1.00939, 1.66177", \ - "0.0470699, 0.16088, 0.243134, 0.382566, 0.617214, 1.0094, 1.66315", \ - "0.0609306, 0.176358, 0.253775, 0.38753, 0.618063, 1.00941, 1.66316", \ - "0.0852103, 0.211694, 0.287947, 0.413367, 0.632014, 1.01327, 1.66317", \ - "0.123208, 0.277029, 0.358353, 0.485083, 0.693288, 1.05043, 1.67529", \ - "0.181509, 0.386513, 0.484138, 0.622865, 0.83941, 1.18481, 1.77246", \ - "0.270402, 0.564912, 0.687841, 0.86128, 1.10448, 1.4789, 2.05446" \ + "0.0332543, 0.155699, 0.240757, 0.381279, 0.617169, 1.00874, 1.66179", \ + "0.0470431, 0.160996, 0.243103, 0.382736, 0.61717, 1.00876, 1.66317", \ + "0.0608987, 0.176208, 0.253769, 0.387534, 0.618066, 1.01062, 1.66318", \ + "0.0852107, 0.211689, 0.28795, 0.413258, 0.63202, 1.01354, 1.66319", \ + "0.123208, 0.277031, 0.358355, 0.485087, 0.693294, 1.05048, 1.67662", \ + "0.18151, 0.386514, 0.48414, 0.622869, 0.839422, 1.18482, 1.77238", \ + "0.270406, 0.564913, 0.687844, 0.86128, 1.10448, 1.47891, 2.05446" \ ); } } @@ -5191,52 +5191,52 @@ library (sg13g2_stdcell_typ_1p20V_25C) { index_1 ("0.0186, 0.0966, 0.174, 0.3294, 0.6408, 1.263, 2.5074"); index_2 ("0.001, 0.0234, 0.039, 0.0648, 0.108, 0.18, 0.3"); values ( \ - "0.0540753, 0.18555, 0.275741, 0.42466, 0.673304, 1.08868, 1.77972", \ - "0.082028, 0.218856, 0.30942, 0.458536, 0.708053, 1.12288, 1.8149", \ - "0.0986505, 0.246579, 0.337953, 0.48735, 0.737021, 1.15301, 1.84438", \ - "0.11957, 0.295256, 0.392474, 0.545019, 0.79541, 1.21098, 1.90293", \ - "0.143134, 0.372397, 0.485575, 0.65223, 0.911946, 1.33081, 2.02332", \ - "0.166266, 0.481339, 0.623826, 0.822824, 1.11447, 1.55669, 2.25885", \ - "0.194289, 0.6241, 0.817698, 1.07641, 1.43095, 1.94219, 2.70033" \ + "0.0540467, 0.185571, 0.275581, 0.424682, 0.673599, 1.08866, 1.77972", \ + "0.0820451, 0.218831, 0.309351, 0.458643, 0.708036, 1.12288, 1.81536", \ + "0.0986501, 0.246579, 0.337952, 0.487337, 0.737008, 1.15299, 1.84437", \ + "0.11957, 0.295255, 0.392473, 0.545018, 0.79538, 1.21111, 1.90292", \ + "0.143133, 0.372396, 0.485574, 0.65223, 0.911975, 1.3308, 2.02324", \ + "0.166266, 0.481338, 0.623824, 0.822823, 1.11446, 1.55669, 2.25884", \ + "0.194288, 0.624139, 0.817696, 1.07641, 1.43094, 1.94218, 2.70032" \ ); } rise_transition (TIMING_DELAY_7x7ds1) { index_1 ("0.0186, 0.0966, 0.174, 0.3294, 0.6408, 1.263, 2.5074"); index_2 ("0.001, 0.0234, 0.039, 0.0648, 0.108, 0.18, 0.3"); values ( \ - "0.0342488, 0.215025, 0.340804, 0.548732, 0.89708, 1.47711, 2.44356", \ - "0.0415358, 0.215926, 0.34096, 0.549879, 0.897081, 1.47758, 2.44515", \ - "0.0512265, 0.221524, 0.343564, 0.54988, 0.897082, 1.47846, 2.44516", \ - "0.0703932, 0.24218, 0.359201, 0.557854, 0.899849, 1.47847, 2.44517", \ - "0.107248, 0.29149, 0.40544, 0.595926, 0.923249, 1.48696, 2.44579", \ - "0.172335, 0.386741, 0.504163, 0.692558, 1.0093, 1.54601, 2.47311", \ - "0.273669, 0.552108, 0.686969, 0.885989, 1.20599, 1.72965, 2.61647" \ + "0.0342481, 0.215024, 0.340801, 0.548729, 0.896978, 1.47711, 2.44355", \ + "0.0415558, 0.215894, 0.340802, 0.548802, 0.896979, 1.47712, 2.44409", \ + "0.0512263, 0.221524, 0.343563, 0.549079, 0.89698, 1.47843, 2.4441", \ + "0.070393, 0.242179, 0.3592, 0.558044, 0.899855, 1.47844, 2.44471", \ + "0.107248, 0.291489, 0.405438, 0.595882, 0.92334, 1.48696, 2.44693", \ + "0.172335, 0.38674, 0.504163, 0.692568, 1.00929, 1.54616, 2.47311", \ + "0.273669, 0.55236, 0.686968, 0.885987, 1.20599, 1.72964, 2.61663" \ ); } cell_fall (TIMING_DELAY_7x7ds1) { index_1 ("0.0186, 0.0966, 0.174, 0.3294, 0.6408, 1.263, 2.5074"); index_2 ("0.001, 0.0234, 0.039, 0.0648, 0.108, 0.18, 0.3"); values ( \ - "0.0444888, 0.13967, 0.203851, 0.309468, 0.486088, 0.779738, 1.26916", \ - "0.0760862, 0.181709, 0.246306, 0.351995, 0.528418, 0.822452, 1.31172", \ - "0.0964667, 0.219119, 0.286968, 0.394017, 0.570446, 0.864198, 1.35382", \ - "0.125164, 0.278817, 0.357611, 0.473245, 0.653671, 0.947439, 1.43627", \ - "0.165257, 0.368365, 0.467166, 0.605635, 0.80794, 1.11461, 1.60538", \ - "0.218782, 0.495993, 0.626001, 0.805434, 1.05386, 1.40935, 1.93562", \ - "0.289321, 0.667657, 0.847273, 1.08691, 1.41549, 1.86299, 2.49097" \ + "0.0444888, 0.139666, 0.203849, 0.309472, 0.486235, 0.779753, 1.26917", \ + "0.0760837, 0.181741, 0.246312, 0.352002, 0.528582, 0.822493, 1.31173", \ + "0.0964667, 0.219116, 0.28697, 0.39402, 0.570451, 0.864168, 1.35384", \ + "0.125164, 0.278818, 0.357613, 0.47325, 0.653676, 0.94753, 1.43654", \ + "0.165258, 0.368367, 0.467169, 0.605638, 0.807945, 1.11462, 1.60529", \ + "0.218782, 0.495995, 0.626004, 0.805438, 1.05386, 1.40936, 1.93564", \ + "0.289314, 0.66766, 0.847276, 1.08691, 1.4155, 1.863, 2.49095" \ ); } fall_transition (TIMING_DELAY_7x7ds1) { index_1 ("0.0186, 0.0966, 0.174, 0.3294, 0.6408, 1.263, 2.5074"); index_2 ("0.001, 0.0234, 0.039, 0.0648, 0.108, 0.18, 0.3"); values ( \ - "0.0332534, 0.1557, 0.240766, 0.381614, 0.617213, 1.00939, 1.66177", \ - "0.0470699, 0.16088, 0.243134, 0.382566, 0.617214, 1.0094, 1.66315", \ - "0.0609306, 0.176358, 0.253775, 0.38753, 0.618063, 1.00941, 1.66316", \ - "0.0852103, 0.211694, 0.287947, 0.413367, 0.632014, 1.01327, 1.66317", \ - "0.123208, 0.277029, 0.358353, 0.485083, 0.693288, 1.05043, 1.67529", \ - "0.181509, 0.386513, 0.484138, 0.622865, 0.83941, 1.18481, 1.77246", \ - "0.270402, 0.564912, 0.687841, 0.86128, 1.10448, 1.4789, 2.05446" \ + "0.0332543, 0.155699, 0.240757, 0.381279, 0.617169, 1.00874, 1.66179", \ + "0.0470431, 0.160996, 0.243103, 0.382736, 0.61717, 1.00876, 1.66317", \ + "0.0608987, 0.176208, 0.253769, 0.387534, 0.618066, 1.01062, 1.66318", \ + "0.0852107, 0.211689, 0.28795, 0.413258, 0.63202, 1.01354, 1.66319", \ + "0.123208, 0.277031, 0.358355, 0.485087, 0.693294, 1.05048, 1.67662", \ + "0.18151, 0.386514, 0.48414, 0.622869, 0.839422, 1.18482, 1.77238", \ + "0.270406, 0.564913, 0.687844, 0.86128, 1.10448, 1.47891, 2.05446" \ ); } } @@ -5250,52 +5250,52 @@ library (sg13g2_stdcell_typ_1p20V_25C) { index_1 ("0.0186, 0.0966, 0.174, 0.3294, 0.6408, 1.263, 2.5074"); index_2 ("0.001, 0.0234, 0.039, 0.0648, 0.108, 0.18, 0.3"); values ( \ - "0.0613914, 0.19217, 0.281642, 0.430346, 0.678371, 1.09188, 1.78201", \ - "0.0914372, 0.225951, 0.315976, 0.46448, 0.713476, 1.12657, 1.81727", \ - "0.110246, 0.254308, 0.345001, 0.493732, 0.742196, 1.15669, 1.84546", \ - "0.135567, 0.304329, 0.400462, 0.552075, 0.801306, 1.21529, 1.90483", \ - "0.166234, 0.383976, 0.495571, 0.660718, 0.918833, 1.33579, 2.02576", \ - "0.19977, 0.497113, 0.636707, 0.833165, 1.12242, 1.56313, 2.26241", \ - "0.24372, 0.647254, 0.836079, 1.09066, 1.4424, 1.95054, 2.70573" \ + "0.0614224, 0.192202, 0.281691, 0.430368, 0.678506, 1.09186, 1.78203", \ + "0.0914435, 0.225981, 0.315949, 0.464479, 0.7135, 1.12658, 1.81727", \ + "0.110247, 0.254309, 0.345003, 0.493733, 0.742198, 1.15669, 1.84546", \ + "0.135568, 0.304329, 0.400463, 0.552087, 0.801308, 1.21529, 1.90484", \ + "0.166234, 0.383977, 0.495572, 0.660719, 0.918835, 1.33583, 2.02578", \ + "0.19977, 0.497114, 0.636708, 0.833166, 1.12242, 1.56313, 2.26243", \ + "0.24372, 0.647255, 0.83608, 1.09066, 1.44241, 1.95055, 2.70573" \ ); } rise_transition (TIMING_DELAY_7x7ds1) { index_1 ("0.0186, 0.0966, 0.174, 0.3294, 0.6408, 1.263, 2.5074"); index_2 ("0.001, 0.0234, 0.039, 0.0648, 0.108, 0.18, 0.3"); values ( \ - "0.0415074, 0.222488, 0.347793, 0.554974, 0.902096, 1.48005, 2.44465", \ - "0.0478183, 0.223048, 0.348986, 0.555742, 0.903036, 1.48114, 2.44475", \ - "0.0571955, 0.228364, 0.35031, 0.556837, 0.903329, 1.48115, 2.44544", \ - "0.0765722, 0.248348, 0.365491, 0.564027, 0.905071, 1.48119, 2.44545", \ - "0.113827, 0.297065, 0.41137, 0.601706, 0.928472, 1.49042, 2.44742", \ - "0.176939, 0.391704, 0.509567, 0.698071, 1.01372, 1.54939, 2.47349", \ - "0.272235, 0.553003, 0.68931, 0.891329, 1.21042, 1.73233, 2.61793" \ + "0.0415074, 0.222405, 0.347553, 0.554977, 0.902433, 1.48005, 2.44462", \ + "0.0478177, 0.222963, 0.348704, 0.555738, 0.903054, 1.48114, 2.44476", \ + "0.0571958, 0.228365, 0.350299, 0.556838, 0.903332, 1.48115, 2.44545", \ + "0.0765724, 0.248349, 0.365492, 0.564055, 0.905075, 1.48119, 2.44546", \ + "0.113827, 0.297065, 0.411522, 0.601648, 0.928475, 1.49013, 2.44745", \ + "0.176938, 0.391705, 0.509568, 0.698073, 1.01372, 1.54937, 2.47371", \ + "0.272236, 0.553005, 0.689311, 0.891331, 1.21043, 1.73231, 2.61793" \ ); } cell_fall (TIMING_DELAY_7x7ds1) { index_1 ("0.0186, 0.0966, 0.174, 0.3294, 0.6408, 1.263, 2.5074"); index_2 ("0.001, 0.0234, 0.039, 0.0648, 0.108, 0.18, 0.3"); values ( \ - "0.0483823, 0.143352, 0.207556, 0.313234, 0.489833, 0.783476, 1.27286", \ - "0.0785711, 0.180684, 0.24529, 0.35105, 0.527692, 0.821877, 1.31111", \ - "0.0991092, 0.213344, 0.280313, 0.387183, 0.563914, 0.857796, 1.34772", \ - "0.128457, 0.267354, 0.341973, 0.455268, 0.635353, 0.929886, 1.41931", \ - "0.169431, 0.35269, 0.443231, 0.572798, 0.768603, 1.07312, 1.56514", \ - "0.22376, 0.479604, 0.596449, 0.759849, 0.99071, 1.33081, 1.84813", \ - "0.296955, 0.653392, 0.818748, 1.03711, 1.3335, 1.7479, 2.33821" \ + "0.0483845, 0.143359, 0.20757, 0.313238, 0.489841, 0.783611, 1.27287", \ + "0.0785801, 0.180686, 0.245271, 0.351036, 0.527675, 0.821855, 1.31077", \ + "0.0991098, 0.213345, 0.280308, 0.387192, 0.564045, 0.857814, 1.34767", \ + "0.128457, 0.267356, 0.341975, 0.455272, 0.63536, 0.929892, 1.41946", \ + "0.169432, 0.352692, 0.443234, 0.572798, 0.768643, 1.07313, 1.56515", \ + "0.223761, 0.47961, 0.596452, 0.759855, 0.990719, 1.33028, 1.84814", \ + "0.296956, 0.653395, 0.818752, 1.03712, 1.33351, 1.74791, 2.33876" \ ); } fall_transition (TIMING_DELAY_7x7ds1) { index_1 ("0.0186, 0.0966, 0.174, 0.3294, 0.6408, 1.263, 2.5074"); index_2 ("0.001, 0.0234, 0.039, 0.0648, 0.108, 0.18, 0.3"); values ( \ - "0.0331323, 0.155722, 0.240762, 0.381261, 0.617219, 1.00873, 1.66173", \ - "0.0415879, 0.158936, 0.242355, 0.3821, 0.61722, 1.00979, 1.66313", \ - "0.0519263, 0.16887, 0.249096, 0.384985, 0.617689, 1.0098, 1.66331", \ - "0.0726288, 0.193317, 0.27234, 0.402199, 0.627027, 1.01209, 1.66332", \ - "0.108061, 0.244351, 0.322847, 0.451938, 0.668359, 1.03627, 1.67276", \ - "0.165338, 0.335088, 0.421899, 0.554538, 0.772344, 1.12836, 1.73623", \ - "0.249386, 0.494303, 0.59936, 0.749842, 0.977645, 1.34142, 1.93496" \ + "0.0331331, 0.155816, 0.240774, 0.381266, 0.617226, 1.00955, 1.66175", \ + "0.0415847, 0.158972, 0.242349, 0.3821, 0.617227, 1.00981, 1.66294", \ + "0.0519266, 0.168871, 0.249096, 0.385168, 0.618077, 1.00982, 1.66295", \ + "0.0726292, 0.193319, 0.272343, 0.402204, 0.627042, 1.0113, 1.66296", \ + "0.108061, 0.244353, 0.322851, 0.452033, 0.668544, 1.03628, 1.67278", \ + "0.165339, 0.335086, 0.422019, 0.554543, 0.772769, 1.12777, 1.73625", \ + "0.249386, 0.494305, 0.599363, 0.749846, 0.977651, 1.34143, 1.93462" \ ); } } @@ -5307,52 +5307,52 @@ library (sg13g2_stdcell_typ_1p20V_25C) { index_1 ("0.0186, 0.0966, 0.174, 0.3294, 0.6408, 1.263, 2.5074"); index_2 ("0.001, 0.0234, 0.039, 0.0648, 0.108, 0.18, 0.3"); values ( \ - "0.0613914, 0.19217, 0.281642, 0.430346, 0.678371, 1.09188, 1.78201", \ - "0.0914372, 0.225951, 0.315976, 0.46448, 0.713476, 1.12657, 1.81727", \ - "0.110246, 0.254308, 0.345001, 0.493732, 0.742196, 1.15669, 1.84546", \ - "0.135567, 0.304329, 0.400462, 0.552075, 0.801306, 1.21529, 1.90483", \ - "0.166234, 0.383976, 0.495571, 0.660718, 0.918833, 1.33579, 2.02576", \ - "0.19977, 0.497113, 0.636707, 0.833165, 1.12242, 1.56313, 2.26241", \ - "0.24372, 0.647254, 0.836079, 1.09066, 1.4424, 1.95054, 2.70573" \ + "0.0614224, 0.192202, 0.281691, 0.430368, 0.678506, 1.09186, 1.78203", \ + "0.0914435, 0.225981, 0.315949, 0.464479, 0.7135, 1.12658, 1.81727", \ + "0.110247, 0.254309, 0.345003, 0.493733, 0.742198, 1.15669, 1.84546", \ + "0.135568, 0.304329, 0.400463, 0.552087, 0.801308, 1.21529, 1.90484", \ + "0.166234, 0.383977, 0.495572, 0.660719, 0.918835, 1.33583, 2.02578", \ + "0.19977, 0.497114, 0.636708, 0.833166, 1.12242, 1.56313, 2.26243", \ + "0.24372, 0.647255, 0.83608, 1.09066, 1.44241, 1.95055, 2.70573" \ ); } rise_transition (TIMING_DELAY_7x7ds1) { index_1 ("0.0186, 0.0966, 0.174, 0.3294, 0.6408, 1.263, 2.5074"); index_2 ("0.001, 0.0234, 0.039, 0.0648, 0.108, 0.18, 0.3"); values ( \ - "0.0415074, 0.222488, 0.347793, 0.554974, 0.902096, 1.48005, 2.44465", \ - "0.0478183, 0.223048, 0.348986, 0.555742, 0.903036, 1.48114, 2.44475", \ - "0.0571955, 0.228364, 0.35031, 0.556837, 0.903329, 1.48115, 2.44544", \ - "0.0765722, 0.248348, 0.365491, 0.564027, 0.905071, 1.48119, 2.44545", \ - "0.113827, 0.297065, 0.41137, 0.601706, 0.928472, 1.49042, 2.44742", \ - "0.176939, 0.391704, 0.509567, 0.698071, 1.01372, 1.54939, 2.47349", \ - "0.272235, 0.553003, 0.68931, 0.891329, 1.21042, 1.73233, 2.61793" \ + "0.0415074, 0.222405, 0.347553, 0.554977, 0.902433, 1.48005, 2.44462", \ + "0.0478177, 0.222963, 0.348704, 0.555738, 0.903054, 1.48114, 2.44476", \ + "0.0571958, 0.228365, 0.350299, 0.556838, 0.903332, 1.48115, 2.44545", \ + "0.0765724, 0.248349, 0.365492, 0.564055, 0.905075, 1.48119, 2.44546", \ + "0.113827, 0.297065, 0.411522, 0.601648, 0.928475, 1.49013, 2.44745", \ + "0.176938, 0.391705, 0.509568, 0.698073, 1.01372, 1.54937, 2.47371", \ + "0.272236, 0.553005, 0.689311, 0.891331, 1.21043, 1.73231, 2.61793" \ ); } cell_fall (TIMING_DELAY_7x7ds1) { index_1 ("0.0186, 0.0966, 0.174, 0.3294, 0.6408, 1.263, 2.5074"); index_2 ("0.001, 0.0234, 0.039, 0.0648, 0.108, 0.18, 0.3"); values ( \ - "0.0483823, 0.143352, 0.207556, 0.313234, 0.489833, 0.783476, 1.27286", \ - "0.0785711, 0.180684, 0.24529, 0.35105, 0.527692, 0.821877, 1.31111", \ - "0.0991092, 0.213344, 0.280313, 0.387183, 0.563914, 0.857796, 1.34772", \ - "0.128457, 0.267354, 0.341973, 0.455268, 0.635353, 0.929886, 1.41931", \ - "0.169431, 0.35269, 0.443231, 0.572798, 0.768603, 1.07312, 1.56514", \ - "0.22376, 0.479604, 0.596449, 0.759849, 0.99071, 1.33081, 1.84813", \ - "0.296955, 0.653392, 0.818748, 1.03711, 1.3335, 1.7479, 2.33821" \ + "0.0483845, 0.143359, 0.20757, 0.313238, 0.489841, 0.783611, 1.27287", \ + "0.0785801, 0.180686, 0.245271, 0.351036, 0.527675, 0.821855, 1.31077", \ + "0.0991098, 0.213345, 0.280308, 0.387192, 0.564045, 0.857814, 1.34767", \ + "0.128457, 0.267356, 0.341975, 0.455272, 0.63536, 0.929892, 1.41946", \ + "0.169432, 0.352692, 0.443234, 0.572798, 0.768643, 1.07313, 1.56515", \ + "0.223761, 0.47961, 0.596452, 0.759855, 0.990719, 1.33028, 1.84814", \ + "0.296956, 0.653395, 0.818752, 1.03712, 1.33351, 1.74791, 2.33876" \ ); } fall_transition (TIMING_DELAY_7x7ds1) { index_1 ("0.0186, 0.0966, 0.174, 0.3294, 0.6408, 1.263, 2.5074"); index_2 ("0.001, 0.0234, 0.039, 0.0648, 0.108, 0.18, 0.3"); values ( \ - "0.0331323, 0.155722, 0.240762, 0.381261, 0.617219, 1.00873, 1.66173", \ - "0.0415879, 0.158936, 0.242355, 0.3821, 0.61722, 1.00979, 1.66313", \ - "0.0519263, 0.16887, 0.249096, 0.384985, 0.617689, 1.0098, 1.66331", \ - "0.0726288, 0.193317, 0.27234, 0.402199, 0.627027, 1.01209, 1.66332", \ - "0.108061, 0.244351, 0.322847, 0.451938, 0.668359, 1.03627, 1.67276", \ - "0.165338, 0.335088, 0.421899, 0.554538, 0.772344, 1.12836, 1.73623", \ - "0.249386, 0.494303, 0.59936, 0.749842, 0.977645, 1.34142, 1.93496" \ + "0.0331331, 0.155816, 0.240774, 0.381266, 0.617226, 1.00955, 1.66175", \ + "0.0415847, 0.158972, 0.242349, 0.3821, 0.617227, 1.00981, 1.66294", \ + "0.0519266, 0.168871, 0.249096, 0.385168, 0.618077, 1.00982, 1.66295", \ + "0.0726292, 0.193319, 0.272343, 0.402204, 0.627042, 1.0113, 1.66296", \ + "0.108061, 0.244353, 0.322851, 0.452033, 0.668544, 1.03628, 1.67278", \ + "0.165339, 0.335086, 0.422019, 0.554543, 0.772769, 1.12777, 1.73625", \ + "0.249386, 0.494305, 0.599363, 0.749846, 0.977651, 1.34143, 1.93462" \ ); } } @@ -5366,52 +5366,52 @@ library (sg13g2_stdcell_typ_1p20V_25C) { index_1 ("0.0186, 0.0966, 0.174, 0.3294, 0.6408, 1.263, 2.5074"); index_2 ("0.001, 0.0234, 0.039, 0.0648, 0.108, 0.18, 0.3"); values ( \ - "0.0570122, 0.189285, 0.279486, 0.428416, 0.677611, 1.09264, 1.78424", \ - "0.0875936, 0.225227, 0.315707, 0.46484, 0.714441, 1.12967, 1.82213", \ - "0.108453, 0.259634, 0.350844, 0.499918, 0.749359, 1.16515, 1.85599", \ - "0.1374, 0.321113, 0.41991, 0.572738, 0.822456, 1.23777, 1.92887", \ - "0.176961, 0.416226, 0.535882, 0.70812, 0.969771, 1.38781, 2.07851", \ - "0.227735, 0.547114, 0.701041, 0.916426, 1.22169, 1.67299, 2.37297", \ - "0.292571, 0.718108, 0.926576, 1.20906, 1.60081, 2.14383, 2.92616" \ + "0.0570294, 0.189206, 0.279508, 0.428425, 0.677616, 1.09265, 1.78423", \ + "0.0875998, 0.225219, 0.315693, 0.464994, 0.714457, 1.12966, 1.82212", \ + "0.108454, 0.259627, 0.350847, 0.499925, 0.749389, 1.16516, 1.856", \ + "0.1374, 0.321114, 0.419911, 0.57274, 0.822425, 1.23777, 1.92909", \ + "0.177016, 0.416226, 0.535883, 0.708122, 0.969774, 1.38781, 2.0785", \ + "0.227736, 0.547115, 0.701042, 0.916427, 1.22169, 1.67301, 2.37292", \ + "0.292572, 0.718109, 0.926577, 1.20906, 1.60082, 2.14384, 2.92639" \ ); } rise_transition (TIMING_DELAY_7x7ds1) { index_1 ("0.0186, 0.0966, 0.174, 0.3294, 0.6408, 1.263, 2.5074"); index_2 ("0.001, 0.0234, 0.039, 0.0648, 0.108, 0.18, 0.3"); values ( \ - "0.0493197, 0.231411, 0.357241, 0.565488, 0.914229, 1.49477, 2.46179", \ - "0.0607294, 0.232684, 0.358633, 0.565489, 0.91423, 1.49478, 2.46291", \ - "0.0751428, 0.241679, 0.361769, 0.568586, 0.914231, 1.49496, 2.46292", \ - "0.100757, 0.27327, 0.386301, 0.580159, 0.918138, 1.49497, 2.46293", \ - "0.140501, 0.34273, 0.454988, 0.638476, 0.955304, 1.51018, 2.464", \ - "0.199879, 0.4605, 0.588726, 0.777123, 1.08438, 1.5996, 2.50515", \ - "0.292615, 0.648314, 0.805874, 1.03131, 1.35941, 1.87388, 2.72431" \ + "0.0491657, 0.231178, 0.357242, 0.565491, 0.914236, 1.49435, 2.46203", \ + "0.0608415, 0.232879, 0.358807, 0.565492, 0.914237, 1.49473, 2.46292", \ + "0.0751432, 0.24177, 0.361782, 0.568175, 0.914254, 1.49497, 2.46293", \ + "0.100757, 0.273271, 0.386302, 0.580162, 0.918337, 1.49498, 2.46294", \ + "0.140448, 0.342731, 0.45499, 0.638478, 0.955307, 1.50996, 2.4649", \ + "0.199878, 0.4605, 0.588727, 0.777124, 1.08438, 1.59959, 2.50527", \ + "0.292615, 0.648316, 0.805874, 1.03131, 1.35942, 1.87375, 2.72371" \ ); } cell_fall (TIMING_DELAY_7x7ds1) { index_1 ("0.0186, 0.0966, 0.174, 0.3294, 0.6408, 1.263, 2.5074"); index_2 ("0.001, 0.0234, 0.039, 0.0648, 0.108, 0.18, 0.3"); values ( \ - "0.0392895, 0.132523, 0.196442, 0.30198, 0.478713, 0.772767, 1.26256", \ - "0.0650739, 0.169775, 0.234439, 0.340291, 0.517098, 0.811561, 1.30114", \ - "0.0807496, 0.201356, 0.269038, 0.376183, 0.553323, 0.847641, 1.33809", \ - "0.101953, 0.253105, 0.329126, 0.443632, 0.624518, 0.919581, 1.40981", \ - "0.129183, 0.333669, 0.427206, 0.559187, 0.756708, 1.06264, 1.55541", \ - "0.164868, 0.452975, 0.575339, 0.742205, 0.976654, 1.3183, 1.8381", \ - "0.213162, 0.613124, 0.787726, 1.0131, 1.31454, 1.73101, 2.32556" \ + "0.0392875, 0.132525, 0.196482, 0.301973, 0.478703, 0.772709, 1.26254", \ + "0.0650734, 0.169773, 0.234447, 0.340278, 0.517103, 0.811552, 1.30113", \ + "0.0807491, 0.201412, 0.269039, 0.376199, 0.553324, 0.847677, 1.33806", \ + "0.101952, 0.253104, 0.329125, 0.443578, 0.624512, 0.919583, 1.40969", \ + "0.12919, 0.333667, 0.427203, 0.559183, 0.756702, 1.06263, 1.55539", \ + "0.164867, 0.452973, 0.575334, 0.7422, 0.976647, 1.31822, 1.83808", \ + "0.21316, 0.613119, 0.787722, 1.01309, 1.31453, 1.731, 2.32554" \ ); } fall_transition (TIMING_DELAY_7x7ds1) { index_1 ("0.0186, 0.0966, 0.174, 0.3294, 0.6408, 1.263, 2.5074"); index_2 ("0.001, 0.0234, 0.039, 0.0648, 0.108, 0.18, 0.3"); values ( \ - "0.0305573, 0.152072, 0.236875, 0.377037, 0.612419, 1.00342, 1.65624", \ - "0.0418792, 0.155802, 0.238429, 0.377451, 0.61242, 1.00366, 1.65653", \ - "0.0540108, 0.166425, 0.245852, 0.381257, 0.612768, 1.00367, 1.65654", \ - "0.0773127, 0.192033, 0.269693, 0.398985, 0.623005, 1.0063, 1.65655", \ - "0.117984, 0.243829, 0.321786, 0.449677, 0.664352, 1.03276, 1.66592", \ - "0.183475, 0.339181, 0.423494, 0.554065, 0.769843, 1.12445, 1.73091", \ - "0.281417, 0.504363, 0.605292, 0.751149, 0.977821, 1.33811, 1.92959" \ + "0.0305534, 0.152071, 0.236911, 0.37706, 0.612411, 1.00343, 1.65622", \ + "0.0418788, 0.1558, 0.238397, 0.37769, 0.612412, 1.00365, 1.65623", \ + "0.0540105, 0.166435, 0.245874, 0.381094, 0.612761, 1.004, 1.65646", \ + "0.0773121, 0.192039, 0.26969, 0.399056, 0.622798, 1.00626, 1.65647", \ + "0.117976, 0.243827, 0.321783, 0.449729, 0.664344, 1.03275, 1.6659", \ + "0.183474, 0.339178, 0.423466, 0.55406, 0.769835, 1.12425, 1.73089", \ + "0.281416, 0.504361, 0.605289, 0.751144, 0.977524, 1.3381, 1.92957" \ ); } } @@ -5425,52 +5425,52 @@ library (sg13g2_stdcell_typ_1p20V_25C) { index_1 ("0.0186, 0.0966, 0.174, 0.3294, 0.6408, 1.263, 2.5074"); index_2 ("0.001, 0.0234, 0.039, 0.0648, 0.108, 0.18, 0.3"); values ( \ - "0.0479653, 0.179448, 0.269342, 0.41767, 0.665866, 1.08, 1.7696", \ - "0.0762775, 0.215387, 0.30547, 0.454176, 0.70272, 1.11644, 1.80606", \ - "0.0942193, 0.249595, 0.340625, 0.489117, 0.73774, 1.15231, 1.84131", \ - "0.118489, 0.309708, 0.409169, 0.561888, 0.810868, 1.22429, 1.91379", \ - "0.151472, 0.401852, 0.523315, 0.696349, 0.957794, 1.37462, 2.06339", \ - "0.193473, 0.52799, 0.684685, 0.902021, 1.20847, 1.65926, 2.35774", \ - "0.246729, 0.692515, 0.904844, 1.19083, 1.58477, 2.12857, 2.9097" \ + "0.0479613, 0.179425, 0.269294, 0.417744, 0.665882, 1.07998, 1.76883", \ + "0.0762774, 0.215384, 0.30548, 0.454032, 0.702752, 1.11643, 1.80575", \ + "0.0942191, 0.249565, 0.340634, 0.489128, 0.737711, 1.15231, 1.84121", \ + "0.118489, 0.309707, 0.409169, 0.561883, 0.810823, 1.22437, 1.91378", \ + "0.151471, 0.401851, 0.523246, 0.696347, 0.95787, 1.37461, 2.06348", \ + "0.193473, 0.527989, 0.684687, 0.902021, 1.20846, 1.65923, 2.35755", \ + "0.246729, 0.692515, 0.904843, 1.19083, 1.58467, 2.12856, 2.90979" \ ); } rise_transition (TIMING_DELAY_7x7ds1) { index_1 ("0.0186, 0.0966, 0.174, 0.3294, 0.6408, 1.263, 2.5074"); index_2 ("0.001, 0.0234, 0.039, 0.0648, 0.108, 0.18, 0.3"); values ( \ - "0.0417568, 0.222585, 0.347982, 0.555514, 0.902858, 1.48095, 2.44511", \ - "0.055049, 0.224375, 0.348289, 0.555904, 0.902859, 1.48166, 2.44586", \ - "0.0692489, 0.234268, 0.353012, 0.557557, 0.90286, 1.48242, 2.44587", \ - "0.0933232, 0.266744, 0.378569, 0.570906, 0.90705, 1.48243, 2.44588", \ - "0.130041, 0.336758, 0.447849, 0.630238, 0.945175, 1.49653, 2.44771", \ - "0.186983, 0.453402, 0.581576, 0.769807, 1.07537, 1.5877, 2.48856", \ - "0.275123, 0.63903, 0.798152, 1.02404, 1.35063, 1.86385, 2.71093" \ + "0.0417054, 0.222585, 0.347972, 0.555504, 0.902769, 1.48095, 2.44559", \ + "0.0550508, 0.224316, 0.348754, 0.556086, 0.902988, 1.48166, 2.44595", \ + "0.0692488, 0.234245, 0.353024, 0.557274, 0.902989, 1.48242, 2.44596", \ + "0.093323, 0.266743, 0.378507, 0.570908, 0.907003, 1.48243, 2.44597", \ + "0.13004, 0.336757, 0.447788, 0.630257, 0.945238, 1.49652, 2.44985", \ + "0.186983, 0.453401, 0.581585, 0.769667, 1.07536, 1.58817, 2.48913", \ + "0.275122, 0.639028, 0.79815, 1.02403, 1.35067, 1.86384, 2.71111" \ ); } cell_fall (TIMING_DELAY_7x7ds1) { index_1 ("0.0186, 0.0966, 0.174, 0.3294, 0.6408, 1.263, 2.5074"); index_2 ("0.001, 0.0234, 0.039, 0.0648, 0.108, 0.18, 0.3"); values ( \ - "0.0388717, 0.131862, 0.195534, 0.30074, 0.477024, 0.770387, 1.25981", \ - "0.0644998, 0.169086, 0.233543, 0.339067, 0.515379, 0.809353, 1.2984", \ - "0.0799524, 0.2006, 0.268108, 0.37502, 0.551695, 0.845447, 1.33506", \ - "0.100426, 0.252192, 0.32808, 0.442339, 0.622817, 0.917359, 1.40673", \ - "0.126747, 0.332394, 0.425845, 0.557621, 0.754833, 1.06022, 1.55233", \ - "0.160393, 0.450487, 0.573239, 0.74028, 0.974169, 1.31574, 1.83485", \ - "0.204716, 0.608492, 0.783492, 1.00961, 1.31112, 1.72834, 2.3219" \ + "0.0388728, 0.131855, 0.195555, 0.30073, 0.477018, 0.770541, 1.25979", \ + "0.0644993, 0.169085, 0.233546, 0.339054, 0.515383, 0.809345, 1.29815", \ + "0.0799519, 0.200577, 0.268109, 0.375016, 0.551642, 0.845529, 1.335", \ + "0.100426, 0.25219, 0.328077, 0.442335, 0.622815, 0.917254, 1.40672", \ + "0.126755, 0.332392, 0.425842, 0.557616, 0.754823, 1.06021, 1.55231", \ + "0.160393, 0.450485, 0.573235, 0.740276, 0.974162, 1.31573, 1.83483", \ + "0.204715, 0.608489, 0.783488, 1.00961, 1.31111, 1.72833, 2.32188" \ ); } fall_transition (TIMING_DELAY_7x7ds1) { index_1 ("0.0186, 0.0966, 0.174, 0.3294, 0.6408, 1.263, 2.5074"); index_2 ("0.001, 0.0234, 0.039, 0.0648, 0.108, 0.18, 0.3"); values ( \ - "0.0219474, 0.143554, 0.228451, 0.368783, 0.603858, 0.996307, 1.64964", \ - "0.031611, 0.147231, 0.230008, 0.369053, 0.603859, 0.996308, 1.64965", \ - "0.0421918, 0.157775, 0.23741, 0.373084, 0.604736, 0.996325, 1.64966", \ - "0.0618221, 0.182814, 0.261153, 0.390547, 0.614715, 0.999268, 1.64967", \ - "0.0961068, 0.233719, 0.312636, 0.441125, 0.65668, 1.02383, 1.65935", \ - "0.151444, 0.326695, 0.412646, 0.544941, 0.761646, 1.11619, 1.72394", \ - "0.234901, 0.48785, 0.593761, 0.74013, 0.968774, 1.3296, 1.92169" \ + "0.0219469, 0.14355, 0.228636, 0.368783, 0.60385, 0.996278, 1.64962", \ + "0.0316108, 0.147229, 0.230025, 0.369076, 0.603851, 0.996279, 1.64963", \ + "0.0421915, 0.157758, 0.2374, 0.373083, 0.604699, 0.99628, 1.64964", \ + "0.0618217, 0.182812, 0.26115, 0.390544, 0.614889, 0.999152, 1.64965", \ + "0.0960989, 0.233718, 0.312632, 0.44112, 0.656666, 1.02384, 1.65932", \ + "0.151445, 0.326694, 0.412641, 0.544935, 0.761639, 1.11617, 1.72391", \ + "0.234901, 0.487848, 0.593758, 0.740126, 0.968766, 1.32959, 1.92187" \ ); } } @@ -5482,52 +5482,52 @@ library (sg13g2_stdcell_typ_1p20V_25C) { index_1 ("0.0186, 0.0966, 0.174, 0.3294, 0.6408, 1.263, 2.5074"); index_2 ("0.001, 0.0234, 0.039, 0.0648, 0.108, 0.18, 0.3"); values ( \ - "0.0570122, 0.189285, 0.279486, 0.428416, 0.677611, 1.09264, 1.78424", \ - "0.0875936, 0.225227, 0.315707, 0.46484, 0.714441, 1.12967, 1.82213", \ - "0.108453, 0.259634, 0.350844, 0.499918, 0.749359, 1.16515, 1.85599", \ - "0.1374, 0.321113, 0.41991, 0.572738, 0.822456, 1.23777, 1.92887", \ - "0.176961, 0.416226, 0.535882, 0.70812, 0.969771, 1.38781, 2.07851", \ - "0.227735, 0.547114, 0.701041, 0.916426, 1.22169, 1.67299, 2.37297", \ - "0.292571, 0.718108, 0.926576, 1.20906, 1.60081, 2.14383, 2.92616" \ + "0.0570294, 0.189206, 0.279508, 0.428425, 0.677616, 1.09265, 1.78423", \ + "0.0875998, 0.225219, 0.315693, 0.464994, 0.714457, 1.12966, 1.82212", \ + "0.108454, 0.259627, 0.350847, 0.499925, 0.749389, 1.16516, 1.856", \ + "0.1374, 0.321114, 0.419911, 0.57274, 0.822425, 1.23777, 1.92909", \ + "0.177016, 0.416226, 0.535883, 0.708122, 0.969774, 1.38781, 2.0785", \ + "0.227736, 0.547115, 0.701042, 0.916427, 1.22169, 1.67301, 2.37292", \ + "0.292572, 0.718109, 0.926577, 1.20906, 1.60082, 2.14384, 2.92639" \ ); } rise_transition (TIMING_DELAY_7x7ds1) { index_1 ("0.0186, 0.0966, 0.174, 0.3294, 0.6408, 1.263, 2.5074"); index_2 ("0.001, 0.0234, 0.039, 0.0648, 0.108, 0.18, 0.3"); values ( \ - "0.0493197, 0.231411, 0.357241, 0.565488, 0.914229, 1.49477, 2.46179", \ - "0.0607294, 0.232684, 0.358633, 0.565489, 0.91423, 1.49478, 2.46291", \ - "0.0751428, 0.241679, 0.361769, 0.568586, 0.914231, 1.49496, 2.46292", \ - "0.100757, 0.27327, 0.386301, 0.580159, 0.918138, 1.49497, 2.46293", \ - "0.140501, 0.34273, 0.454988, 0.638476, 0.955304, 1.51018, 2.464", \ - "0.199879, 0.4605, 0.588726, 0.777123, 1.08438, 1.5996, 2.50515", \ - "0.292615, 0.648314, 0.805874, 1.03131, 1.35941, 1.87388, 2.72431" \ + "0.0491657, 0.231178, 0.357242, 0.565491, 0.914236, 1.49435, 2.46203", \ + "0.0608415, 0.232879, 0.358807, 0.565492, 0.914237, 1.49473, 2.46292", \ + "0.0751432, 0.24177, 0.361782, 0.568175, 0.914254, 1.49497, 2.46293", \ + "0.100757, 0.273271, 0.386302, 0.580162, 0.918337, 1.49498, 2.46294", \ + "0.140448, 0.342731, 0.45499, 0.638478, 0.955307, 1.50996, 2.4649", \ + "0.199878, 0.4605, 0.588727, 0.777124, 1.08438, 1.59959, 2.50527", \ + "0.292615, 0.648316, 0.805874, 1.03131, 1.35942, 1.87375, 2.72371" \ ); } cell_fall (TIMING_DELAY_7x7ds1) { index_1 ("0.0186, 0.0966, 0.174, 0.3294, 0.6408, 1.263, 2.5074"); index_2 ("0.001, 0.0234, 0.039, 0.0648, 0.108, 0.18, 0.3"); values ( \ - "0.0392895, 0.132523, 0.196442, 0.30198, 0.478713, 0.772767, 1.26256", \ - "0.0650739, 0.169775, 0.234439, 0.340291, 0.517098, 0.811561, 1.30114", \ - "0.0807496, 0.201356, 0.269038, 0.376183, 0.553323, 0.847641, 1.33809", \ - "0.101953, 0.253105, 0.329126, 0.443632, 0.624518, 0.919581, 1.40981", \ - "0.129183, 0.333669, 0.427206, 0.559187, 0.756708, 1.06264, 1.55541", \ - "0.164868, 0.452975, 0.575339, 0.742205, 0.976654, 1.3183, 1.8381", \ - "0.213162, 0.613124, 0.787726, 1.0131, 1.31454, 1.73101, 2.32556" \ + "0.0392875, 0.132525, 0.196482, 0.301973, 0.478703, 0.772709, 1.26254", \ + "0.0650734, 0.169773, 0.234447, 0.340278, 0.517103, 0.811552, 1.30113", \ + "0.0807491, 0.201412, 0.269039, 0.376199, 0.553324, 0.847677, 1.33806", \ + "0.101952, 0.253104, 0.329125, 0.443578, 0.624512, 0.919583, 1.40969", \ + "0.12919, 0.333667, 0.427203, 0.559183, 0.756702, 1.06263, 1.55539", \ + "0.164867, 0.452973, 0.575334, 0.7422, 0.976647, 1.31822, 1.83808", \ + "0.21316, 0.613119, 0.787722, 1.01309, 1.31453, 1.731, 2.32554" \ ); } fall_transition (TIMING_DELAY_7x7ds1) { index_1 ("0.0186, 0.0966, 0.174, 0.3294, 0.6408, 1.263, 2.5074"); index_2 ("0.001, 0.0234, 0.039, 0.0648, 0.108, 0.18, 0.3"); values ( \ - "0.0305573, 0.152072, 0.236875, 0.377037, 0.612419, 1.00342, 1.65624", \ - "0.0418792, 0.155802, 0.238429, 0.377451, 0.61242, 1.00366, 1.65653", \ - "0.0540108, 0.166425, 0.245852, 0.381257, 0.612768, 1.00367, 1.65654", \ - "0.0773127, 0.192033, 0.269693, 0.398985, 0.623005, 1.0063, 1.65655", \ - "0.117984, 0.243829, 0.321786, 0.449677, 0.664352, 1.03276, 1.66592", \ - "0.183475, 0.339181, 0.423494, 0.554065, 0.769843, 1.12445, 1.73091", \ - "0.281417, 0.504363, 0.605292, 0.751149, 0.977821, 1.33811, 1.92959" \ + "0.0305534, 0.152071, 0.236911, 0.37706, 0.612411, 1.00343, 1.65622", \ + "0.0418788, 0.1558, 0.238397, 0.37769, 0.612412, 1.00365, 1.65623", \ + "0.0540105, 0.166435, 0.245874, 0.381094, 0.612761, 1.004, 1.65646", \ + "0.0773121, 0.192039, 0.26969, 0.399056, 0.622798, 1.00626, 1.65647", \ + "0.117976, 0.243827, 0.321783, 0.449729, 0.664344, 1.03275, 1.6659", \ + "0.183474, 0.339178, 0.423466, 0.55406, 0.769835, 1.12425, 1.73089", \ + "0.281416, 0.504361, 0.605289, 0.751144, 0.977524, 1.3381, 1.92957" \ ); } } @@ -5541,52 +5541,52 @@ library (sg13g2_stdcell_typ_1p20V_25C) { index_1 ("0.0186, 0.0966, 0.174, 0.3294, 0.6408, 1.263, 2.5074"); index_2 ("0.001, 0.0234, 0.039, 0.0648, 0.108, 0.18, 0.3"); values ( \ - "0.0488768, 0.181292, 0.271338, 0.41983, 0.66821, 1.08206, 1.77091", \ - "0.0767183, 0.216653, 0.307048, 0.455959, 0.704842, 1.11851, 1.80894", \ - "0.0944001, 0.250369, 0.341671, 0.49049, 0.739276, 1.15394, 1.84245", \ - "0.118289, 0.310258, 0.410019, 0.563008, 0.81227, 1.22599, 1.91567", \ - "0.150558, 0.4019, 0.523683, 0.69707, 0.958837, 1.37604, 2.06512", \ - "0.191179, 0.527392, 0.684325, 0.902302, 1.20882, 1.66016, 2.35871", \ - "0.240286, 0.68933, 0.902984, 1.18863, 1.58235, 2.12844, 2.91052" \ + "0.048875, 0.181268, 0.27132, 0.419835, 0.668211, 1.0815, 1.77165", \ + "0.0767184, 0.216651, 0.307072, 0.455886, 0.704717, 1.11851, 1.80856", \ + "0.0944002, 0.250379, 0.341641, 0.49044, 0.739265, 1.15278, 1.84261", \ + "0.118289, 0.310259, 0.40998, 0.563013, 0.81227, 1.22599, 1.91568", \ + "0.150558, 0.4019, 0.523682, 0.697071, 0.958839, 1.37611, 2.06503", \ + "0.19118, 0.527398, 0.684326, 0.902303, 1.20882, 1.66017, 2.35878", \ + "0.240286, 0.689332, 0.902985, 1.18863, 1.58236, 2.12844, 2.91053" \ ); } rise_transition (TIMING_DELAY_7x7ds1) { index_1 ("0.0186, 0.0966, 0.174, 0.3294, 0.6408, 1.263, 2.5074"); index_2 ("0.001, 0.0234, 0.039, 0.0648, 0.108, 0.18, 0.3"); values ( \ - "0.041414, 0.222186, 0.347789, 0.555139, 0.902114, 1.48099, 2.44494", \ - "0.0545267, 0.22386, 0.348208, 0.555468, 0.902126, 1.48129, 2.44561", \ - "0.0688016, 0.233626, 0.352525, 0.556969, 0.902127, 1.48196, 2.44562", \ - "0.0930564, 0.266083, 0.377898, 0.570446, 0.906517, 1.48197, 2.44563", \ - "0.13062, 0.335815, 0.447173, 0.629529, 0.944354, 1.49615, 2.44949", \ - "0.190159, 0.453263, 0.581397, 0.769397, 1.07467, 1.58692, 2.48863", \ - "0.286546, 0.641566, 0.799451, 1.02455, 1.35145, 1.86337, 2.70968" \ + "0.0414143, 0.222191, 0.347791, 0.555141, 0.902122, 1.48024, 2.44461", \ + "0.0545269, 0.223862, 0.348454, 0.556203, 0.902125, 1.4813, 2.44463", \ + "0.0688017, 0.233637, 0.352496, 0.556703, 0.902126, 1.48131, 2.44553", \ + "0.0930566, 0.266084, 0.377857, 0.570484, 0.90661, 1.48131, 2.44554", \ + "0.13062, 0.335829, 0.447165, 0.62953, 0.944363, 1.49619, 2.44714", \ + "0.19016, 0.453269, 0.581398, 0.769399, 1.07467, 1.58693, 2.48871", \ + "0.286547, 0.641567, 0.799453, 1.02455, 1.35145, 1.86338, 2.70966" \ ); } cell_fall (TIMING_DELAY_7x7ds1) { index_1 ("0.0186, 0.0966, 0.174, 0.3294, 0.6408, 1.263, 2.5074"); index_2 ("0.001, 0.0234, 0.039, 0.0648, 0.108, 0.18, 0.3"); values ( \ - "0.0346027, 0.128508, 0.192537, 0.297978, 0.474808, 0.768829, 1.25867", \ - "0.0598503, 0.170419, 0.23514, 0.340913, 0.517417, 0.811947, 1.30177", \ - "0.0741788, 0.206527, 0.275347, 0.382694, 0.559502, 0.853616, 1.34394", \ - "0.0935818, 0.263053, 0.343488, 0.461037, 0.642365, 0.936887, 1.42612", \ - "0.1207, 0.346919, 0.449692, 0.590871, 0.795374, 1.10384, 1.59528", \ - "0.156251, 0.466003, 0.601299, 0.786018, 1.0386, 1.39681, 1.92503", \ - "0.202641, 0.623543, 0.812434, 1.06019, 1.39482, 1.84742, 2.47895" \ + "0.0346023, 0.128498, 0.192532, 0.297976, 0.474586, 0.768758, 1.25866", \ + "0.0597535, 0.170439, 0.235151, 0.34092, 0.517267, 0.811925, 1.30173", \ + "0.0741784, 0.206526, 0.275345, 0.382687, 0.559471, 0.853628, 1.34353", \ + "0.0935814, 0.263052, 0.343693, 0.461031, 0.642236, 0.936878, 1.42634", \ + "0.1207, 0.346918, 0.44969, 0.590867, 0.795369, 1.10383, 1.59526", \ + "0.15625, 0.466001, 0.601273, 0.786014, 1.03859, 1.3968, 1.92502", \ + "0.20264, 0.62354, 0.81243, 1.06019, 1.39482, 1.84741, 2.47893" \ ); } fall_transition (TIMING_DELAY_7x7ds1) { index_1 ("0.0186, 0.0966, 0.174, 0.3294, 0.6408, 1.263, 2.5074"); index_2 ("0.001, 0.0234, 0.039, 0.0648, 0.108, 0.18, 0.3"); values ( \ - "0.0309984, 0.152069, 0.236925, 0.377235, 0.612436, 1.0039, 1.65627", \ - "0.049375, 0.158192, 0.239316, 0.377573, 0.612437, 1.00391, 1.65628", \ - "0.0653676, 0.174561, 0.251072, 0.38331, 0.613171, 1.00392, 1.65643", \ - "0.0923881, 0.21159, 0.28645, 0.410492, 0.627961, 1.00811, 1.65644", \ - "0.134845, 0.278773, 0.358251, 0.483929, 0.690269, 1.04601, 1.66989", \ - "0.202068, 0.392138, 0.486702, 0.623368, 0.837894, 1.18166, 1.76769", \ - "0.309012, 0.576347, 0.695537, 0.865413, 1.10558, 1.47813, 2.05127" \ + "0.0309977, 0.15206, 0.236922, 0.377228, 0.611983, 1.00348, 1.65624", \ + "0.0493445, 0.15819, 0.239345, 0.37757, 0.611984, 1.0036, 1.65625", \ + "0.0653672, 0.174559, 0.251069, 0.383459, 0.613227, 1.00361, 1.65626", \ + "0.0923877, 0.211589, 0.286378, 0.410743, 0.628067, 1.00808, 1.65627", \ + "0.134845, 0.278771, 0.35825, 0.483925, 0.690268, 1.046, 1.66934", \ + "0.202069, 0.392137, 0.4867, 0.623363, 0.837886, 1.18167, 1.76767", \ + "0.309012, 0.576347, 0.695534, 0.865409, 1.10557, 1.47808, 2.05126" \ ); } } @@ -5600,52 +5600,52 @@ library (sg13g2_stdcell_typ_1p20V_25C) { index_1 ("0.0186, 0.0966, 0.174, 0.3294, 0.6408, 1.263, 2.5074"); index_2 ("0.001, 0.0234, 0.039, 0.0648, 0.108, 0.18, 0.3"); values ( \ - "0.0398586, 0.172614, 0.262872, 0.4117, 0.660583, 1.07589, 1.76693", \ - "0.0645669, 0.207961, 0.298561, 0.447649, 0.697257, 1.11247, 1.80501", \ - "0.0787583, 0.241333, 0.333063, 0.482253, 0.731824, 1.14794, 1.83859", \ - "0.0976806, 0.299947, 0.400914, 0.554685, 0.804818, 1.22, 1.91162", \ - "0.122924, 0.388768, 0.512984, 0.687989, 0.95121, 1.3698, 2.06114", \ - "0.154171, 0.509793, 0.670155, 0.891066, 1.2001, 1.65384, 2.35458", \ - "0.190714, 0.665387, 0.883816, 1.17446, 1.57144, 2.12075, 2.90612" \ + "0.0398571, 0.172612, 0.26286, 0.411704, 0.660578, 1.07589, 1.76765", \ + "0.0645668, 0.20797, 0.298526, 0.4476, 0.697227, 1.11245, 1.80498", \ + "0.0787581, 0.241331, 0.333086, 0.482248, 0.731822, 1.14794, 1.83858", \ + "0.0976805, 0.299946, 0.400907, 0.554684, 0.804815, 1.22009, 1.91173", \ + "0.122924, 0.388767, 0.512983, 0.687987, 0.951208, 1.36987, 2.06113", \ + "0.15417, 0.509792, 0.670154, 0.891065, 1.2001, 1.65383, 2.3548", \ + "0.190714, 0.665386, 0.883816, 1.17446, 1.57144, 2.12075, 2.90611" \ ); } rise_transition (TIMING_DELAY_7x7ds1) { index_1 ("0.0186, 0.0966, 0.174, 0.3294, 0.6408, 1.263, 2.5074"); index_2 ("0.001, 0.0234, 0.039, 0.0648, 0.108, 0.18, 0.3"); values ( \ - "0.0341347, 0.214935, 0.34094, 0.548652, 0.897132, 1.47709, 2.44356", \ - "0.0494253, 0.217025, 0.341153, 0.549112, 0.897133, 1.47774, 2.44519", \ - "0.0634952, 0.227516, 0.346091, 0.549881, 0.897134, 1.47775, 2.4452", \ - "0.0856484, 0.260889, 0.372368, 0.564806, 0.901447, 1.47943, 2.44521", \ - "0.121863, 0.33112, 0.44271, 0.624786, 0.939945, 1.49342, 2.44897", \ - "0.17888, 0.448167, 0.576745, 0.765255, 1.07077, 1.58477, 2.48811", \ - "0.272459, 0.636595, 0.795947, 1.02064, 1.3494, 1.86076, 2.70851" \ + "0.0341349, 0.214912, 0.340939, 0.54865, 0.897329, 1.47711, 2.4442", \ + "0.049417, 0.217032, 0.341115, 0.549169, 0.89733, 1.47773, 2.44518", \ + "0.0634951, 0.227504, 0.346069, 0.549879, 0.897331, 1.47774, 2.44519", \ + "0.0856483, 0.260888, 0.37236, 0.564804, 0.901444, 1.47775, 2.4452", \ + "0.121862, 0.331119, 0.44271, 0.624784, 0.939942, 1.49286, 2.44897", \ + "0.17888, 0.448166, 0.576744, 0.765254, 1.07082, 1.58477, 2.48861", \ + "0.272459, 0.636594, 0.795944, 1.02064, 1.3494, 1.86076, 2.70851" \ ); } cell_fall (TIMING_DELAY_7x7ds1) { index_1 ("0.0186, 0.0966, 0.174, 0.3294, 0.6408, 1.263, 2.5074"); index_2 ("0.001, 0.0234, 0.039, 0.0648, 0.108, 0.18, 0.3"); values ( \ - "0.0342156, 0.127828, 0.191598, 0.2968, 0.473187, 0.766499, 1.25565", \ - "0.0590255, 0.16974, 0.23427, 0.339753, 0.516, 0.809939, 1.299", \ - "0.072983, 0.205686, 0.274462, 0.381542, 0.557859, 0.851457, 1.34092", \ - "0.091866, 0.261947, 0.342548, 0.459497, 0.640715, 0.934589, 1.42342", \ - "0.117668, 0.345135, 0.447971, 0.589107, 0.793396, 1.10145, 1.59215", \ - "0.15067, 0.46286, 0.598709, 0.783196, 1.03591, 1.39395, 1.92169", \ - "0.191454, 0.617572, 0.80712, 1.0556, 1.39045, 1.844, 2.47555" \ + "0.034217, 0.127798, 0.191592, 0.296789, 0.473175, 0.766492, 1.25563", \ + "0.0590252, 0.169743, 0.234251, 0.339739, 0.515995, 0.809944, 1.29898", \ + "0.0729826, 0.205684, 0.274463, 0.381538, 0.557808, 0.851401, 1.34054", \ + "0.0918656, 0.261881, 0.342532, 0.459739, 0.640571, 0.934427, 1.42335", \ + "0.117668, 0.345133, 0.447906, 0.589103, 0.79339, 1.10144, 1.59233", \ + "0.15067, 0.462858, 0.598706, 0.783192, 1.03588, 1.3939, 1.92168", \ + "0.191453, 0.617569, 0.807117, 1.0556, 1.39044, 1.84399, 2.47553" \ ); } fall_transition (TIMING_DELAY_7x7ds1) { index_1 ("0.0186, 0.0966, 0.174, 0.3294, 0.6408, 1.263, 2.5074"); index_2 ("0.001, 0.0234, 0.039, 0.0648, 0.108, 0.18, 0.3"); values ( \ - "0.0223772, 0.14353, 0.228705, 0.36883, 0.604312, 0.995352, 1.6484", \ - "0.0378954, 0.149686, 0.230909, 0.369498, 0.604313, 0.995819, 1.64841", \ - "0.0513413, 0.16584, 0.24258, 0.375029, 0.605171, 0.99582, 1.64842", \ - "0.0730328, 0.201736, 0.277753, 0.402114, 0.620536, 1.00039, 1.6485", \ - "0.107432, 0.267758, 0.348873, 0.474693, 0.681999, 1.03836, 1.66302", \ - "0.162782, 0.376563, 0.475313, 0.612981, 0.829288, 1.17382, 1.75969", \ - "0.25197, 0.556368, 0.679225, 0.850286, 1.09478, 1.46679, 2.0438" \ + "0.0223644, 0.143633, 0.228702, 0.368825, 0.604304, 0.995546, 1.64838", \ + "0.0378952, 0.14963, 0.230945, 0.369471, 0.604305, 0.99581, 1.64839", \ + "0.051341, 0.165838, 0.242582, 0.375024, 0.605549, 0.995975, 1.6484", \ + "0.0730324, 0.202283, 0.277641, 0.402032, 0.619922, 1.00043, 1.64851", \ + "0.107431, 0.267756, 0.348822, 0.474689, 0.681992, 1.03835, 1.6635", \ + "0.162783, 0.376561, 0.475311, 0.612977, 0.82901, 1.1739, 1.75966", \ + "0.25197, 0.556366, 0.679219, 0.850281, 1.09478, 1.46676, 2.04378" \ ); } } @@ -5657,52 +5657,52 @@ library (sg13g2_stdcell_typ_1p20V_25C) { index_1 ("0.0186, 0.0966, 0.174, 0.3294, 0.6408, 1.263, 2.5074"); index_2 ("0.001, 0.0234, 0.039, 0.0648, 0.108, 0.18, 0.3"); values ( \ - "0.0488768, 0.181292, 0.271338, 0.41983, 0.66821, 1.08206, 1.77091", \ - "0.0767183, 0.216653, 0.307048, 0.455959, 0.704842, 1.11851, 1.80894", \ - "0.0944001, 0.250369, 0.341671, 0.49049, 0.739276, 1.15394, 1.84245", \ - "0.118289, 0.310258, 0.410019, 0.563008, 0.81227, 1.22599, 1.91567", \ - "0.150558, 0.4019, 0.523683, 0.69707, 0.958837, 1.37604, 2.06512", \ - "0.191179, 0.527392, 0.684325, 0.902302, 1.20882, 1.66016, 2.35871", \ - "0.240286, 0.68933, 0.902984, 1.18863, 1.58235, 2.12844, 2.91052" \ + "0.048875, 0.181268, 0.27132, 0.419835, 0.668211, 1.0815, 1.77165", \ + "0.0767184, 0.216651, 0.307072, 0.455886, 0.704717, 1.11851, 1.80856", \ + "0.0944002, 0.250379, 0.341641, 0.49044, 0.739265, 1.15278, 1.84261", \ + "0.118289, 0.310259, 0.40998, 0.563013, 0.81227, 1.22599, 1.91568", \ + "0.150558, 0.4019, 0.523682, 0.697071, 0.958839, 1.37611, 2.06503", \ + "0.19118, 0.527398, 0.684326, 0.902303, 1.20882, 1.66017, 2.35878", \ + "0.240286, 0.689332, 0.902985, 1.18863, 1.58236, 2.12844, 2.91053" \ ); } rise_transition (TIMING_DELAY_7x7ds1) { index_1 ("0.0186, 0.0966, 0.174, 0.3294, 0.6408, 1.263, 2.5074"); index_2 ("0.001, 0.0234, 0.039, 0.0648, 0.108, 0.18, 0.3"); values ( \ - "0.041414, 0.222186, 0.347789, 0.555139, 0.902114, 1.48099, 2.44494", \ - "0.0545267, 0.22386, 0.348208, 0.555468, 0.902126, 1.48129, 2.44561", \ - "0.0688016, 0.233626, 0.352525, 0.556969, 0.902127, 1.48196, 2.44562", \ - "0.0930564, 0.266083, 0.377898, 0.570446, 0.906517, 1.48197, 2.44563", \ - "0.13062, 0.335815, 0.447173, 0.629529, 0.944354, 1.49615, 2.44949", \ - "0.190159, 0.453263, 0.581397, 0.769397, 1.07467, 1.58692, 2.48863", \ - "0.286546, 0.641566, 0.799451, 1.02455, 1.35145, 1.86337, 2.70968" \ + "0.0414143, 0.222191, 0.347791, 0.555141, 0.902122, 1.48024, 2.44461", \ + "0.0545269, 0.223862, 0.348454, 0.556203, 0.902125, 1.4813, 2.44463", \ + "0.0688017, 0.233637, 0.352496, 0.556703, 0.902126, 1.48131, 2.44553", \ + "0.0930566, 0.266084, 0.377857, 0.570484, 0.90661, 1.48131, 2.44554", \ + "0.13062, 0.335829, 0.447165, 0.62953, 0.944363, 1.49619, 2.44714", \ + "0.19016, 0.453269, 0.581398, 0.769399, 1.07467, 1.58693, 2.48871", \ + "0.286547, 0.641567, 0.799453, 1.02455, 1.35145, 1.86338, 2.70966" \ ); } cell_fall (TIMING_DELAY_7x7ds1) { index_1 ("0.0186, 0.0966, 0.174, 0.3294, 0.6408, 1.263, 2.5074"); index_2 ("0.001, 0.0234, 0.039, 0.0648, 0.108, 0.18, 0.3"); values ( \ - "0.0346027, 0.128508, 0.192537, 0.297978, 0.474808, 0.768829, 1.25867", \ - "0.0598503, 0.170419, 0.23514, 0.340913, 0.517417, 0.811947, 1.30177", \ - "0.0741788, 0.206527, 0.275347, 0.382694, 0.559502, 0.853616, 1.34394", \ - "0.0935818, 0.263053, 0.343488, 0.461037, 0.642365, 0.936887, 1.42612", \ - "0.1207, 0.346919, 0.449692, 0.590871, 0.795374, 1.10384, 1.59528", \ - "0.156251, 0.466003, 0.601299, 0.786018, 1.0386, 1.39681, 1.92503", \ - "0.202641, 0.623543, 0.812434, 1.06019, 1.39482, 1.84742, 2.47895" \ + "0.0346023, 0.128498, 0.192532, 0.297976, 0.474586, 0.768758, 1.25866", \ + "0.0597535, 0.170439, 0.235151, 0.34092, 0.517267, 0.811925, 1.30173", \ + "0.0741784, 0.206526, 0.275345, 0.382687, 0.559471, 0.853628, 1.34353", \ + "0.0935814, 0.263052, 0.343693, 0.461031, 0.642236, 0.936878, 1.42634", \ + "0.1207, 0.346918, 0.44969, 0.590867, 0.795369, 1.10383, 1.59526", \ + "0.15625, 0.466001, 0.601273, 0.786014, 1.03859, 1.3968, 1.92502", \ + "0.20264, 0.62354, 0.81243, 1.06019, 1.39482, 1.84741, 2.47893" \ ); } fall_transition (TIMING_DELAY_7x7ds1) { index_1 ("0.0186, 0.0966, 0.174, 0.3294, 0.6408, 1.263, 2.5074"); index_2 ("0.001, 0.0234, 0.039, 0.0648, 0.108, 0.18, 0.3"); values ( \ - "0.0309984, 0.152069, 0.236925, 0.377235, 0.612436, 1.0039, 1.65627", \ - "0.049375, 0.158192, 0.239316, 0.377573, 0.612437, 1.00391, 1.65628", \ - "0.0653676, 0.174561, 0.251072, 0.38331, 0.613171, 1.00392, 1.65643", \ - "0.0923881, 0.21159, 0.28645, 0.410492, 0.627961, 1.00811, 1.65644", \ - "0.134845, 0.278773, 0.358251, 0.483929, 0.690269, 1.04601, 1.66989", \ - "0.202068, 0.392138, 0.486702, 0.623368, 0.837894, 1.18166, 1.76769", \ - "0.309012, 0.576347, 0.695537, 0.865413, 1.10558, 1.47813, 2.05127" \ + "0.0309977, 0.15206, 0.236922, 0.377228, 0.611983, 1.00348, 1.65624", \ + "0.0493445, 0.15819, 0.239345, 0.37757, 0.611984, 1.0036, 1.65625", \ + "0.0653672, 0.174559, 0.251069, 0.383459, 0.613227, 1.00361, 1.65626", \ + "0.0923877, 0.211589, 0.286378, 0.410743, 0.628067, 1.00808, 1.65627", \ + "0.134845, 0.278771, 0.35825, 0.483925, 0.690268, 1.046, 1.66934", \ + "0.202069, 0.392137, 0.4867, 0.623363, 0.837886, 1.18167, 1.76767", \ + "0.309012, 0.576347, 0.695534, 0.865409, 1.10557, 1.47808, 2.05126" \ ); } } @@ -5713,26 +5713,26 @@ library (sg13g2_stdcell_typ_1p20V_25C) { index_1 ("0.0186, 0.0966, 0.174, 0.3294, 0.6408, 1.263, 2.5074"); index_2 ("0.001, 0.0234, 0.039, 0.0648, 0.108, 0.18, 0.3"); values ( \ - "0.00472175, 0.00494219, 0.0049328, 0.00487641, 0.00476599, 0.00452832, 0.00422482", \ - "0.00443709, 0.00474559, 0.00478111, 0.00485104, 0.00470767, 0.00452781, 0.00431945", \ - "0.00438215, 0.00465848, 0.0047138, 0.00469086, 0.00464606, 0.00455653, 0.00426268", \ - "0.00440361, 0.00452814, 0.00461309, 0.00460078, 0.00471966, 0.00439049, 0.00418636", \ - "0.00474952, 0.00461501, 0.00459902, 0.0045788, 0.00465914, 0.00457436, 0.00418725", \ - "0.00615042, 0.00526485, 0.00507399, 0.00495475, 0.00471744, 0.00486109, 0.00422342", \ - "0.00997806, 0.00763441, 0.0070502, 0.00647712, 0.00602981, 0.0053771, 0.00501842" \ + "0.00472002, 0.00494282, 0.00492306, 0.00487633, 0.00475033, 0.00452768, 0.00422585", \ + "0.00443955, 0.00474449, 0.00477506, 0.0047868, 0.00469962, 0.00451762, 0.00430629", \ + "0.00438228, 0.00465843, 0.00471382, 0.00467566, 0.00464575, 0.00455557, 0.00426263", \ + "0.00440369, 0.00452799, 0.00461307, 0.00460516, 0.00494857, 0.00442993, 0.00418642", \ + "0.00474971, 0.00461494, 0.00459919, 0.0045676, 0.00480547, 0.00457043, 0.00421613", \ + "0.00615022, 0.00526513, 0.00508172, 0.00494827, 0.00471744, 0.00488427, 0.00423486", \ + "0.0099789, 0.00763489, 0.0070502, 0.00647647, 0.00603193, 0.00538367, 0.00504196" \ ); } fall_power (POWER_7x7ds1) { index_1 ("0.0186, 0.0966, 0.174, 0.3294, 0.6408, 1.263, 2.5074"); index_2 ("0.001, 0.0234, 0.039, 0.0648, 0.108, 0.18, 0.3"); values ( \ - "0.00469832, 0.00471024, 0.00467056, 0.00462123, 0.00453455, 0.00434872, 0.00397461", \ - "0.00440274, 0.00456484, 0.0045465, 0.004548, 0.00440619, 0.0042656, 0.00398236", \ - "0.00438807, 0.00448046, 0.00452628, 0.00447492, 0.00438492, 0.00426489, 0.00386968", \ - "0.00460882, 0.00454696, 0.00450227, 0.00446848, 0.00466281, 0.00451438, 0.00386507", \ - "0.00534729, 0.00486327, 0.00477838, 0.00461581, 0.00446443, 0.00467405, 0.00394152", \ - "0.00703028, 0.00592488, 0.0056407, 0.00536489, 0.00502738, 0.00464167, 0.00469343", \ - "0.0109303, 0.00884714, 0.00815787, 0.00738829, 0.00670607, 0.00610388, 0.00507663" \ + "0.00469872, 0.00471203, 0.0046661, 0.00461158, 0.00454306, 0.00432956, 0.00397753", \ + "0.00439709, 0.00457809, 0.00454417, 0.0045528, 0.00441266, 0.00427023, 0.00398138", \ + "0.00438567, 0.00447873, 0.00452749, 0.00447487, 0.00438457, 0.00438506, 0.00386932", \ + "0.00461517, 0.00454298, 0.00450138, 0.0044741, 0.00450017, 0.00454938, 0.00386886", \ + "0.00534977, 0.00486296, 0.00478011, 0.00461724, 0.00446443, 0.004739, 0.0040013", \ + "0.00702919, 0.0059241, 0.00564098, 0.0053613, 0.00509659, 0.00461041, 0.0046863", \ + "0.0109298, 0.00884786, 0.00815787, 0.00738821, 0.00670451, 0.00608843, 0.00511777" \ ); } } @@ -5742,26 +5742,26 @@ library (sg13g2_stdcell_typ_1p20V_25C) { index_1 ("0.0186, 0.0966, 0.174, 0.3294, 0.6408, 1.263, 2.5074"); index_2 ("0.001, 0.0234, 0.039, 0.0648, 0.108, 0.18, 0.3"); values ( \ - "0.00472175, 0.00494219, 0.0049328, 0.00487641, 0.00476599, 0.00452832, 0.00422482", \ - "0.00443709, 0.00474559, 0.00478111, 0.00485104, 0.00470767, 0.00452781, 0.00431945", \ - "0.00438215, 0.00465848, 0.0047138, 0.00469086, 0.00464606, 0.00455653, 0.00426268", \ - "0.00440361, 0.00452814, 0.00461309, 0.00460078, 0.00471966, 0.00439049, 0.00418636", \ - "0.00474952, 0.00461501, 0.00459902, 0.0045788, 0.00465914, 0.00457436, 0.00418725", \ - "0.00615042, 0.00526485, 0.00507399, 0.00495475, 0.00471744, 0.00486109, 0.00422342", \ - "0.00997806, 0.00763441, 0.0070502, 0.00647712, 0.00602981, 0.0053771, 0.00501842" \ + "0.00472002, 0.00494282, 0.00492306, 0.00487633, 0.00475033, 0.00452768, 0.00422585", \ + "0.00443955, 0.00474449, 0.00477506, 0.0047868, 0.00469962, 0.00451762, 0.00430629", \ + "0.00438228, 0.00465843, 0.00471382, 0.00467566, 0.00464575, 0.00455557, 0.00426263", \ + "0.00440369, 0.00452799, 0.00461307, 0.00460516, 0.00494857, 0.00442993, 0.00418642", \ + "0.00474971, 0.00461494, 0.00459919, 0.0045676, 0.00480547, 0.00457043, 0.00421613", \ + "0.00615022, 0.00526513, 0.00508172, 0.00494827, 0.00471744, 0.00488427, 0.00423486", \ + "0.0099789, 0.00763489, 0.0070502, 0.00647647, 0.00603193, 0.00538367, 0.00504196" \ ); } fall_power (POWER_7x7ds1) { index_1 ("0.0186, 0.0966, 0.174, 0.3294, 0.6408, 1.263, 2.5074"); index_2 ("0.001, 0.0234, 0.039, 0.0648, 0.108, 0.18, 0.3"); values ( \ - "0.00469832, 0.00471024, 0.00467056, 0.00462123, 0.00453455, 0.00434872, 0.00397461", \ - "0.00440274, 0.00456484, 0.0045465, 0.004548, 0.00440619, 0.0042656, 0.00398236", \ - "0.00438807, 0.00448046, 0.00452628, 0.00447492, 0.00438492, 0.00426489, 0.00386968", \ - "0.00460882, 0.00454696, 0.00450227, 0.00446848, 0.00466281, 0.00451438, 0.00386507", \ - "0.00534729, 0.00486327, 0.00477838, 0.00461581, 0.00446443, 0.00467405, 0.00394152", \ - "0.00703028, 0.00592488, 0.0056407, 0.00536489, 0.00502738, 0.00464167, 0.00469343", \ - "0.0109303, 0.00884714, 0.00815787, 0.00738829, 0.00670607, 0.00610388, 0.00507663" \ + "0.00469872, 0.00471203, 0.0046661, 0.00461158, 0.00454306, 0.00432956, 0.00397753", \ + "0.00439709, 0.00457809, 0.00454417, 0.0045528, 0.00441266, 0.00427023, 0.00398138", \ + "0.00438567, 0.00447873, 0.00452749, 0.00447487, 0.00438457, 0.00438506, 0.00386932", \ + "0.00461517, 0.00454298, 0.00450138, 0.0044741, 0.00450017, 0.00454938, 0.00386886", \ + "0.00534977, 0.00486296, 0.00478011, 0.00461724, 0.00446443, 0.004739, 0.0040013", \ + "0.00702919, 0.0059241, 0.00564098, 0.0053613, 0.00509659, 0.00461041, 0.0046863", \ + "0.0109298, 0.00884786, 0.00815787, 0.00738821, 0.00670451, 0.00608843, 0.00511777" \ ); } } @@ -5772,26 +5772,26 @@ library (sg13g2_stdcell_typ_1p20V_25C) { index_1 ("0.0186, 0.0966, 0.174, 0.3294, 0.6408, 1.263, 2.5074"); index_2 ("0.001, 0.0234, 0.039, 0.0648, 0.108, 0.18, 0.3"); values ( \ - "0.00485964, 0.00489313, 0.00484169, 0.00478163, 0.00465142, 0.00442799, 0.00419484", \ - "0.00467966, 0.00478049, 0.00481535, 0.00477223, 0.00467317, 0.0044378, 0.00418256", \ - "0.00463301, 0.00478557, 0.0047213, 0.00473147, 0.00466929, 0.00445441, 0.00415957", \ - "0.00464398, 0.00467285, 0.00472459, 0.00463807, 0.00497121, 0.00439543, 0.00419961", \ - "0.00492469, 0.00481217, 0.00476524, 0.00469925, 0.00489243, 0.00460053, 0.00419316", \ - "0.00616345, 0.00546344, 0.0052754, 0.00514431, 0.00479483, 0.0049017, 0.00426529", \ - "0.00965927, 0.00777454, 0.00722688, 0.00670117, 0.00620706, 0.00556512, 0.00518956" \ + "0.00486134, 0.00489265, 0.00483888, 0.00478166, 0.00464929, 0.00442729, 0.00417027", \ + "0.00468231, 0.00478443, 0.00480521, 0.00477257, 0.00467789, 0.00443632, 0.00418228", \ + "0.00463406, 0.00474988, 0.0047205, 0.00473186, 0.00466935, 0.00443504, 0.00415957", \ + "0.00464453, 0.00467842, 0.00472452, 0.00464645, 0.00497127, 0.00439479, 0.00419967", \ + "0.00492534, 0.00481424, 0.0047832, 0.00469234, 0.00489237, 0.00448039, 0.00419543", \ + "0.00616292, 0.00546345, 0.00527539, 0.005143, 0.00483287, 0.00495841, 0.00428205", \ + "0.00965906, 0.00777473, 0.00722701, 0.00670103, 0.00620958, 0.00549805, 0.00518439" \ ); } fall_power (POWER_7x7ds1) { index_1 ("0.0186, 0.0966, 0.174, 0.3294, 0.6408, 1.263, 2.5074"); index_2 ("0.001, 0.0234, 0.039, 0.0648, 0.108, 0.18, 0.3"); values ( \ - "0.00626567, 0.00622467, 0.00618979, 0.00611889, 0.00605213, 0.00584275, 0.00548142", \ - "0.00601331, 0.00614287, 0.00609279, 0.00606369, 0.00596227, 0.00580183, 0.00549192", \ - "0.00594335, 0.00604658, 0.00608671, 0.00599833, 0.0059235, 0.00578258, 0.00553044", \ - "0.00598215, 0.00605793, 0.00601781, 0.00600225, 0.00620787, 0.00594953, 0.00540147", \ - "0.00637562, 0.0062573, 0.00620425, 0.00611625, 0.00596481, 0.00622353, 0.00569481", \ - "0.00772352, 0.00695528, 0.0067456, 0.00658816, 0.0064695, 0.00605393, 0.00613694", \ - "0.0111603, 0.00930689, 0.00875831, 0.00817167, 0.00771747, 0.0072577, 0.00665771" \ + "0.00626488, 0.00622946, 0.00618981, 0.0061192, 0.00605135, 0.00587292, 0.00548194", \ + "0.00600754, 0.00614827, 0.00609373, 0.00606471, 0.00594789, 0.00581123, 0.00549913", \ + "0.00594336, 0.00604659, 0.0060834, 0.00600012, 0.00596117, 0.00579097, 0.00543751", \ + "0.00598686, 0.00605365, 0.00601827, 0.00600702, 0.0062114, 0.0058971, 0.0053795", \ + "0.00637646, 0.0062575, 0.00620255, 0.00615206, 0.00600929, 0.00622347, 0.00569462", \ + "0.00772328, 0.00695431, 0.00672681, 0.00659102, 0.00647048, 0.00606797, 0.00613718", \ + "0.0111603, 0.00930692, 0.0087587, 0.00817164, 0.0077177, 0.00725663, 0.00655837" \ ); } } @@ -5801,26 +5801,26 @@ library (sg13g2_stdcell_typ_1p20V_25C) { index_1 ("0.0186, 0.0966, 0.174, 0.3294, 0.6408, 1.263, 2.5074"); index_2 ("0.001, 0.0234, 0.039, 0.0648, 0.108, 0.18, 0.3"); values ( \ - "0.00485964, 0.00489313, 0.00484169, 0.00478163, 0.00465142, 0.00442799, 0.00419484", \ - "0.00467966, 0.00478049, 0.00481535, 0.00477223, 0.00467317, 0.0044378, 0.00418256", \ - "0.00463301, 0.00478557, 0.0047213, 0.00473147, 0.00466929, 0.00445441, 0.00415957", \ - "0.00464398, 0.00467285, 0.00472459, 0.00463807, 0.00497121, 0.00439543, 0.00419961", \ - "0.00492469, 0.00481217, 0.00476524, 0.00469925, 0.00489243, 0.00460053, 0.00419316", \ - "0.00616345, 0.00546344, 0.0052754, 0.00514431, 0.00479483, 0.0049017, 0.00426529", \ - "0.00965927, 0.00777454, 0.00722688, 0.00670117, 0.00620706, 0.00556512, 0.00518956" \ + "0.00486134, 0.00489265, 0.00483888, 0.00478166, 0.00464929, 0.00442729, 0.00417027", \ + "0.00468231, 0.00478443, 0.00480521, 0.00477257, 0.00467789, 0.00443632, 0.00418228", \ + "0.00463406, 0.00474988, 0.0047205, 0.00473186, 0.00466935, 0.00443504, 0.00415957", \ + "0.00464453, 0.00467842, 0.00472452, 0.00464645, 0.00497127, 0.00439479, 0.00419967", \ + "0.00492534, 0.00481424, 0.0047832, 0.00469234, 0.00489237, 0.00448039, 0.00419543", \ + "0.00616292, 0.00546345, 0.00527539, 0.005143, 0.00483287, 0.00495841, 0.00428205", \ + "0.00965906, 0.00777473, 0.00722701, 0.00670103, 0.00620958, 0.00549805, 0.00518439" \ ); } fall_power (POWER_7x7ds1) { index_1 ("0.0186, 0.0966, 0.174, 0.3294, 0.6408, 1.263, 2.5074"); index_2 ("0.001, 0.0234, 0.039, 0.0648, 0.108, 0.18, 0.3"); values ( \ - "0.00626567, 0.00622467, 0.00618979, 0.00611889, 0.00605213, 0.00584275, 0.00548142", \ - "0.00601331, 0.00614287, 0.00609279, 0.00606369, 0.00596227, 0.00580183, 0.00549192", \ - "0.00594335, 0.00604658, 0.00608671, 0.00599833, 0.0059235, 0.00578258, 0.00553044", \ - "0.00598215, 0.00605793, 0.00601781, 0.00600225, 0.00620787, 0.00594953, 0.00540147", \ - "0.00637562, 0.0062573, 0.00620425, 0.00611625, 0.00596481, 0.00622353, 0.00569481", \ - "0.00772352, 0.00695528, 0.0067456, 0.00658816, 0.0064695, 0.00605393, 0.00613694", \ - "0.0111603, 0.00930689, 0.00875831, 0.00817167, 0.00771747, 0.0072577, 0.00665771" \ + "0.00626488, 0.00622946, 0.00618981, 0.0061192, 0.00605135, 0.00587292, 0.00548194", \ + "0.00600754, 0.00614827, 0.00609373, 0.00606471, 0.00594789, 0.00581123, 0.00549913", \ + "0.00594336, 0.00604659, 0.0060834, 0.00600012, 0.00596117, 0.00579097, 0.00543751", \ + "0.00598686, 0.00605365, 0.00601827, 0.00600702, 0.0062114, 0.0058971, 0.0053795", \ + "0.00637646, 0.0062575, 0.00620255, 0.00615206, 0.00600929, 0.00622347, 0.00569462", \ + "0.00772328, 0.00695431, 0.00672681, 0.00659102, 0.00647048, 0.00606797, 0.00613718", \ + "0.0111603, 0.00930692, 0.0087587, 0.00817164, 0.0077177, 0.00725663, 0.00655837" \ ); } } @@ -5831,26 +5831,26 @@ library (sg13g2_stdcell_typ_1p20V_25C) { index_1 ("0.0186, 0.0966, 0.174, 0.3294, 0.6408, 1.263, 2.5074"); index_2 ("0.001, 0.0234, 0.039, 0.0648, 0.108, 0.18, 0.3"); values ( \ - "0.00301298, 0.00309687, 0.00305685, 0.00299316, 0.00288902, 0.00267553, 0.00234452", \ - "0.00278858, 0.00293715, 0.002988, 0.00290277, 0.0028253, 0.00264631, 0.00245583", \ - "0.00284802, 0.00293441, 0.0028844, 0.00295174, 0.00281308, 0.00264959, 0.00227206", \ - "0.00312736, 0.00293186, 0.00295946, 0.00285348, 0.00277454, 0.00258017, 0.00232044", \ - "0.0038467, 0.00333535, 0.00317594, 0.00304849, 0.00292782, 0.00277927, 0.00235176", \ - "0.00563072, 0.00450717, 0.00417918, 0.00383586, 0.00339762, 0.00331432, 0.00264208", \ - "0.00955812, 0.00752236, 0.0068177, 0.00607268, 0.00530139, 0.00432448, 0.00376416" \ + "0.00300838, 0.00308752, 0.00305841, 0.00299601, 0.0028763, 0.00265075, 0.00239336", \ + "0.00278956, 0.00294508, 0.00298818, 0.00291343, 0.0028256, 0.00264435, 0.00245466", \ + "0.00284648, 0.00291499, 0.00288896, 0.00294271, 0.00281455, 0.00265097, 0.00229222", \ + "0.00312739, 0.00293719, 0.00295945, 0.00285347, 0.00278939, 0.00258011, 0.00232967", \ + "0.00384585, 0.00333512, 0.00317569, 0.00304928, 0.00299981, 0.00264446, 0.00234467", \ + "0.0056301, 0.00450819, 0.00417918, 0.00383586, 0.00339786, 0.00330168, 0.00267367", \ + "0.00955858, 0.00752282, 0.00681858, 0.00606904, 0.00530478, 0.0042923, 0.00370601" \ ); } fall_power (POWER_7x7ds1) { index_1 ("0.0186, 0.0966, 0.174, 0.3294, 0.6408, 1.263, 2.5074"); index_2 ("0.001, 0.0234, 0.039, 0.0648, 0.108, 0.18, 0.3"); values ( \ - "0.006001, 0.00621113, 0.00618626, 0.00611887, 0.00605741, 0.00583799, 0.0054556", \ - "0.00564758, 0.00613142, 0.00612558, 0.00611579, 0.00606651, 0.00587077, 0.00555492", \ - "0.00558461, 0.00596078, 0.00607051, 0.00604734, 0.00609525, 0.00585706, 0.00556208", \ - "0.00567138, 0.0059102, 0.0059574, 0.0060011, 0.00627726, 0.00594887, 0.00546678", \ - "0.00618516, 0.00598593, 0.00603327, 0.00606101, 0.00592066, 0.00612646, 0.00566761", \ - "0.00775548, 0.00671446, 0.00651468, 0.00638914, 0.00632368, 0.00603916, 0.00604493", \ - "0.0115527, 0.00908246, 0.00848844, 0.00787995, 0.00750277, 0.00706727, 0.00647626" \ + "0.00600136, 0.00621115, 0.00618801, 0.00612562, 0.0060572, 0.00583149, 0.00545777", \ + "0.00564757, 0.00613142, 0.00617688, 0.00612948, 0.00606728, 0.00587075, 0.00549191", \ + "0.00558328, 0.00596444, 0.00608117, 0.00604419, 0.00604797, 0.00588081, 0.00556133", \ + "0.00567147, 0.00590935, 0.00597293, 0.00599251, 0.0060355, 0.00580518, 0.00552271", \ + "0.00618568, 0.00598528, 0.00603335, 0.00606469, 0.00591869, 0.0063282, 0.00567257", \ + "0.00775576, 0.00671445, 0.00652044, 0.00639133, 0.00632405, 0.00594916, 0.00615369", \ + "0.0115529, 0.00908253, 0.00848866, 0.00787995, 0.00751229, 0.00706957, 0.00647601" \ ); } } @@ -5861,26 +5861,26 @@ library (sg13g2_stdcell_typ_1p20V_25C) { index_1 ("0.0186, 0.0966, 0.174, 0.3294, 0.6408, 1.263, 2.5074"); index_2 ("0.001, 0.0234, 0.039, 0.0648, 0.108, 0.18, 0.3"); values ( \ - "0.00284789, 0.00297696, 0.00294374, 0.00288652, 0.00275206, 0.0025577, 0.00222905", \ - "0.00264938, 0.0028078, 0.00281644, 0.00282731, 0.00270689, 0.00255046, 0.00227896", \ - "0.00273768, 0.00279162, 0.00277413, 0.00279668, 0.0026774, 0.00254302, 0.00225433", \ - "0.00305747, 0.00282395, 0.00283906, 0.00273122, 0.00273465, 0.0024744, 0.00221689", \ - "0.00383283, 0.00323806, 0.00306308, 0.00292643, 0.00299741, 0.00256191, 0.00228383", \ - "0.00570062, 0.00444208, 0.00408036, 0.00374, 0.00327595, 0.00312312, 0.00249193", \ - "0.00972043, 0.00752313, 0.00678942, 0.00601424, 0.00524369, 0.00419992, 0.00365661" \ + "0.00285034, 0.00297555, 0.00294044, 0.00288146, 0.00277535, 0.00255752, 0.00228257", \ + "0.00265109, 0.00280727, 0.00283567, 0.00283615, 0.0027229, 0.00255005, 0.00230637", \ + "0.00273637, 0.00282248, 0.00277379, 0.00278394, 0.00267596, 0.00254328, 0.00219915", \ + "0.00305691, 0.00282263, 0.00283358, 0.00273007, 0.0027522, 0.00246174, 0.00221688", \ + "0.00383309, 0.00324431, 0.0030676, 0.00292705, 0.00286617, 0.00263503, 0.0023796", \ + "0.00570069, 0.00444207, 0.00407888, 0.00374093, 0.00327588, 0.00326785, 0.0024931", \ + "0.00972042, 0.00752364, 0.00678938, 0.00601566, 0.0052576, 0.00420005, 0.00366518" \ ); } fall_power (POWER_7x7ds1) { index_1 ("0.0186, 0.0966, 0.174, 0.3294, 0.6408, 1.263, 2.5074"); index_2 ("0.001, 0.0234, 0.039, 0.0648, 0.108, 0.18, 0.3"); values ( \ - "0.00436408, 0.00459121, 0.0045747, 0.004515, 0.00443965, 0.00425423, 0.00396327", \ - "0.00402368, 0.00449578, 0.00451096, 0.0044976, 0.00443219, 0.00425011, 0.00393138", \ - "0.00396497, 0.00436027, 0.00445837, 0.0044581, 0.00440213, 0.00427613, 0.00397412", \ - "0.00404527, 0.00428707, 0.00435142, 0.0043838, 0.00443934, 0.00427918, 0.00388484", \ - "0.0045719, 0.00438175, 0.00442968, 0.00442968, 0.00433689, 0.00465849, 0.00419835", \ - "0.00618374, 0.00512166, 0.00490528, 0.00483555, 0.0047574, 0.00443315, 0.00456092", \ - "0.0100373, 0.00753145, 0.00694989, 0.00631236, 0.00595502, 0.00549646, 0.00493184" \ + "0.00436405, 0.00459115, 0.00458186, 0.00451894, 0.00443857, 0.0042667, 0.0039625", \ + "0.0040227, 0.00449545, 0.0045183, 0.00449817, 0.00442037, 0.00428508, 0.0039775", \ + "0.00396554, 0.00435952, 0.00445864, 0.00445577, 0.00449692, 0.00429203, 0.00397075", \ + "0.00404511, 0.00429086, 0.00436236, 0.00438949, 0.00444436, 0.00427256, 0.00391239", \ + "0.00457261, 0.00438175, 0.00442979, 0.00442756, 0.00434944, 0.00455248, 0.00419837", \ + "0.00618497, 0.00512169, 0.00490517, 0.00483613, 0.00475547, 0.00445297, 0.00457621", \ + "0.0100374, 0.00753101, 0.00695005, 0.00631296, 0.00595829, 0.00549505, 0.00498426" \ ); } } @@ -5890,26 +5890,26 @@ library (sg13g2_stdcell_typ_1p20V_25C) { index_1 ("0.0186, 0.0966, 0.174, 0.3294, 0.6408, 1.263, 2.5074"); index_2 ("0.001, 0.0234, 0.039, 0.0648, 0.108, 0.18, 0.3"); values ( \ - "0.00301298, 0.00309687, 0.00305685, 0.00299316, 0.00288902, 0.00267553, 0.00234452", \ - "0.00278858, 0.00293715, 0.002988, 0.00290277, 0.0028253, 0.00264631, 0.00245583", \ - "0.00284802, 0.00293441, 0.0028844, 0.00295174, 0.00281308, 0.00264959, 0.00227206", \ - "0.00312736, 0.00293186, 0.00295946, 0.00285348, 0.00277454, 0.00258017, 0.00232044", \ - "0.0038467, 0.00333535, 0.00317594, 0.00304849, 0.00292782, 0.00277927, 0.00235176", \ - "0.00563072, 0.00450717, 0.00417918, 0.00383586, 0.00339762, 0.00331432, 0.00264208", \ - "0.00955812, 0.00752236, 0.0068177, 0.00607268, 0.00530139, 0.00432448, 0.00376416" \ + "0.00300838, 0.00308752, 0.00305841, 0.00299601, 0.0028763, 0.00265075, 0.00239336", \ + "0.00278956, 0.00294508, 0.00298818, 0.00291343, 0.0028256, 0.00264435, 0.00245466", \ + "0.00284648, 0.00291499, 0.00288896, 0.00294271, 0.00281455, 0.00265097, 0.00229222", \ + "0.00312739, 0.00293719, 0.00295945, 0.00285347, 0.00278939, 0.00258011, 0.00232967", \ + "0.00384585, 0.00333512, 0.00317569, 0.00304928, 0.00299981, 0.00264446, 0.00234467", \ + "0.0056301, 0.00450819, 0.00417918, 0.00383586, 0.00339786, 0.00330168, 0.00267367", \ + "0.00955858, 0.00752282, 0.00681858, 0.00606904, 0.00530478, 0.0042923, 0.00370601" \ ); } fall_power (POWER_7x7ds1) { index_1 ("0.0186, 0.0966, 0.174, 0.3294, 0.6408, 1.263, 2.5074"); index_2 ("0.001, 0.0234, 0.039, 0.0648, 0.108, 0.18, 0.3"); values ( \ - "0.006001, 0.00621113, 0.00618626, 0.00611887, 0.00605741, 0.00583799, 0.0054556", \ - "0.00564758, 0.00613142, 0.00612558, 0.00611579, 0.00606651, 0.00587077, 0.00555492", \ - "0.00558461, 0.00596078, 0.00607051, 0.00604734, 0.00609525, 0.00585706, 0.00556208", \ - "0.00567138, 0.0059102, 0.0059574, 0.0060011, 0.00627726, 0.00594887, 0.00546678", \ - "0.00618516, 0.00598593, 0.00603327, 0.00606101, 0.00592066, 0.00612646, 0.00566761", \ - "0.00775548, 0.00671446, 0.00651468, 0.00638914, 0.00632368, 0.00603916, 0.00604493", \ - "0.0115527, 0.00908246, 0.00848844, 0.00787995, 0.00750277, 0.00706727, 0.00647626" \ + "0.00600136, 0.00621115, 0.00618801, 0.00612562, 0.0060572, 0.00583149, 0.00545777", \ + "0.00564757, 0.00613142, 0.00617688, 0.00612948, 0.00606728, 0.00587075, 0.00549191", \ + "0.00558328, 0.00596444, 0.00608117, 0.00604419, 0.00604797, 0.00588081, 0.00556133", \ + "0.00567147, 0.00590935, 0.00597293, 0.00599251, 0.0060355, 0.00580518, 0.00552271", \ + "0.00618568, 0.00598528, 0.00603335, 0.00606469, 0.00591869, 0.0063282, 0.00567257", \ + "0.00775576, 0.00671445, 0.00652044, 0.00639133, 0.00632405, 0.00594916, 0.00615369", \ + "0.0115529, 0.00908253, 0.00848866, 0.00787995, 0.00751229, 0.00706957, 0.00647601" \ ); } } @@ -5920,26 +5920,26 @@ library (sg13g2_stdcell_typ_1p20V_25C) { index_1 ("0.0186, 0.0966, 0.174, 0.3294, 0.6408, 1.263, 2.5074"); index_2 ("0.001, 0.0234, 0.039, 0.0648, 0.108, 0.18, 0.3"); values ( \ - "0.00281697, 0.00308297, 0.00307013, 0.00301045, 0.00289278, 0.00268066, 0.00244119", \ - "0.0025287, 0.00283682, 0.00290259, 0.00291748, 0.00283928, 0.00268103, 0.00247033", \ - "0.00258575, 0.00281569, 0.0028064, 0.00285639, 0.00278068, 0.00266893, 0.00238894", \ - "0.00287816, 0.0027305, 0.00278883, 0.00274217, 0.00284457, 0.00257358, 0.0023417", \ - "0.00364976, 0.00309203, 0.00295288, 0.00287084, 0.0029205, 0.00263818, 0.00242744", \ - "0.00557146, 0.00428853, 0.00394481, 0.0036455, 0.00319891, 0.0031394, 0.00254889", \ - "0.00975001, 0.00722759, 0.00655696, 0.00595422, 0.00520265, 0.00406384, 0.00358326" \ + "0.00281661, 0.00308449, 0.00306873, 0.00301054, 0.00288879, 0.00266865, 0.00238305", \ + "0.0025287, 0.00283679, 0.00291224, 0.00296193, 0.00283731, 0.00268047, 0.00242549", \ + "0.00258573, 0.0027833, 0.00280559, 0.00285513, 0.00277696, 0.00261997, 0.0023289", \ + "0.00287815, 0.00273052, 0.00279345, 0.00274084, 0.00288203, 0.00258338, 0.00234217", \ + "0.0036511, 0.00309499, 0.00298428, 0.00287029, 0.00301283, 0.00257809, 0.00228796", \ + "0.00557218, 0.0042885, 0.00394562, 0.00364958, 0.00319914, 0.00324625, 0.00254668", \ + "0.00974942, 0.00722676, 0.00655719, 0.00595402, 0.00520265, 0.00406372, 0.00358246" \ ); } fall_power (POWER_7x7ds1) { index_1 ("0.0186, 0.0966, 0.174, 0.3294, 0.6408, 1.263, 2.5074"); index_2 ("0.001, 0.0234, 0.039, 0.0648, 0.108, 0.18, 0.3"); values ( \ - "0.00433717, 0.00465441, 0.00464165, 0.00459372, 0.00451088, 0.0043123, 0.00396409", \ - "0.00404847, 0.0045401, 0.00458074, 0.00455388, 0.00450282, 0.00433117, 0.00400374", \ - "0.00409244, 0.00437534, 0.00450692, 0.00446755, 0.00444991, 0.00430152, 0.00400946", \ - "0.00437619, 0.00438187, 0.00439262, 0.00446022, 0.00455636, 0.00451754, 0.00396807", \ - "0.0051917, 0.00463461, 0.00461636, 0.00452024, 0.00441935, 0.00466855, 0.00404069", \ - "0.00714257, 0.00568892, 0.00541576, 0.00518676, 0.00496482, 0.00445978, 0.00468981", \ - "0.0113201, 0.00862302, 0.00785676, 0.00710259, 0.00649573, 0.00600479, 0.0050407" \ + "0.00433716, 0.00465106, 0.00464414, 0.00459358, 0.00447244, 0.00427803, 0.00396443", \ + "0.00404516, 0.00454135, 0.00460549, 0.00455364, 0.00447285, 0.00432999, 0.00400137", \ + "0.0040916, 0.0043753, 0.00450086, 0.00449244, 0.00443694, 0.00429404, 0.00398331", \ + "0.00437611, 0.00438197, 0.00438043, 0.00444225, 0.00446889, 0.00451316, 0.00393505", \ + "0.0051919, 0.00463411, 0.00461573, 0.00452075, 0.00445324, 0.00466964, 0.00402193", \ + "0.00714329, 0.00568857, 0.00541617, 0.00518676, 0.004967, 0.00446579, 0.00469035", \ + "0.0113197, 0.00862318, 0.0078569, 0.0071022, 0.00649659, 0.00600455, 0.00506605" \ ); } } @@ -5950,26 +5950,26 @@ library (sg13g2_stdcell_typ_1p20V_25C) { index_1 ("0.0186, 0.0966, 0.174, 0.3294, 0.6408, 1.263, 2.5074"); index_2 ("0.001, 0.0234, 0.039, 0.0648, 0.108, 0.18, 0.3"); values ( \ - "0.00259389, 0.0029658, 0.00296207, 0.00290233, 0.00279762, 0.00257154, 0.00225937", \ - "0.00236232, 0.00272212, 0.00277292, 0.00279881, 0.00272437, 0.00254338, 0.00239656", \ - "0.0024747, 0.00266998, 0.00269474, 0.00271023, 0.00267933, 0.00256184, 0.00230565", \ - "0.00282369, 0.00260483, 0.00268005, 0.00263811, 0.00300039, 0.00257932, 0.00227265", \ - "0.00367229, 0.00299467, 0.00284653, 0.00274385, 0.00272835, 0.00246746, 0.00235701", \ - "0.00567785, 0.00423797, 0.0038579, 0.00354413, 0.00308085, 0.0030427, 0.00244952", \ - "0.0100234, 0.00724394, 0.00655526, 0.00589615, 0.00513803, 0.00398059, 0.00345269" \ + "0.00259385, 0.00296531, 0.00296161, 0.00290183, 0.00279045, 0.00256171, 0.00232124", \ + "0.0023617, 0.00272283, 0.00277154, 0.00280131, 0.0027242, 0.0025703, 0.00239483", \ + "0.00247518, 0.00268251, 0.00269934, 0.0027152, 0.00267932, 0.00256112, 0.00230579", \ + "0.00282331, 0.00260681, 0.00267676, 0.00263813, 0.00300038, 0.00242983, 0.00227815", \ + "0.00367229, 0.00299277, 0.00284662, 0.00275143, 0.00273671, 0.00248291, 0.00235677", \ + "0.00567804, 0.0042387, 0.00385789, 0.00354232, 0.00307363, 0.0030519, 0.00244035", \ + "0.0100224, 0.00724414, 0.00655532, 0.00589571, 0.00513522, 0.00403947, 0.00350254" \ ); } fall_power (POWER_7x7ds1) { index_1 ("0.0186, 0.0966, 0.174, 0.3294, 0.6408, 1.263, 2.5074"); index_2 ("0.001, 0.0234, 0.039, 0.0648, 0.108, 0.18, 0.3"); values ( \ - "0.00270499, 0.00304123, 0.00303889, 0.00297334, 0.00291606, 0.00268913, 0.00236413", \ - "0.00242894, 0.00290908, 0.00295214, 0.00294408, 0.0029009, 0.00273936, 0.0023914", \ - "0.0024733, 0.00278041, 0.00288501, 0.00287784, 0.00295741, 0.00272212, 0.00242274", \ - "0.00276285, 0.00277604, 0.00280586, 0.002824, 0.00294749, 0.00288961, 0.00240489", \ - "0.00358741, 0.00303666, 0.00301757, 0.00294617, 0.00280291, 0.00298999, 0.00245325", \ - "0.00558591, 0.00407889, 0.0038314, 0.00356735, 0.00338164, 0.002861, 0.00307106", \ - "0.00982468, 0.00705535, 0.00626103, 0.00547419, 0.00490206, 0.00435193, 0.00360795" \ + "0.00270641, 0.00304429, 0.00303823, 0.00297219, 0.00291568, 0.00268934, 0.00236361", \ + "0.00242842, 0.00291227, 0.00294193, 0.00294374, 0.00290135, 0.00274347, 0.00242196", \ + "0.00247383, 0.00277403, 0.00288547, 0.00287901, 0.00287174, 0.00276705, 0.00239453", \ + "0.00276238, 0.00279055, 0.00278928, 0.00282098, 0.00308769, 0.00288288, 0.00238457", \ + "0.0035872, 0.00303677, 0.00302257, 0.0029456, 0.00280279, 0.0030442, 0.0024987", \ + "0.0055852, 0.00407896, 0.00383126, 0.00356665, 0.0033635, 0.00300026, 0.00302294", \ + "0.00982445, 0.00705537, 0.00626108, 0.00547515, 0.00490211, 0.00435442, 0.00352162" \ ); } } @@ -5979,26 +5979,26 @@ library (sg13g2_stdcell_typ_1p20V_25C) { index_1 ("0.0186, 0.0966, 0.174, 0.3294, 0.6408, 1.263, 2.5074"); index_2 ("0.001, 0.0234, 0.039, 0.0648, 0.108, 0.18, 0.3"); values ( \ - "0.00281697, 0.00308297, 0.00307013, 0.00301045, 0.00289278, 0.00268066, 0.00244119", \ - "0.0025287, 0.00283682, 0.00290259, 0.00291748, 0.00283928, 0.00268103, 0.00247033", \ - "0.00258575, 0.00281569, 0.0028064, 0.00285639, 0.00278068, 0.00266893, 0.00238894", \ - "0.00287816, 0.0027305, 0.00278883, 0.00274217, 0.00284457, 0.00257358, 0.0023417", \ - "0.00364976, 0.00309203, 0.00295288, 0.00287084, 0.0029205, 0.00263818, 0.00242744", \ - "0.00557146, 0.00428853, 0.00394481, 0.0036455, 0.00319891, 0.0031394, 0.00254889", \ - "0.00975001, 0.00722759, 0.00655696, 0.00595422, 0.00520265, 0.00406384, 0.00358326" \ + "0.00281661, 0.00308449, 0.00306873, 0.00301054, 0.00288879, 0.00266865, 0.00238305", \ + "0.0025287, 0.00283679, 0.00291224, 0.00296193, 0.00283731, 0.00268047, 0.00242549", \ + "0.00258573, 0.0027833, 0.00280559, 0.00285513, 0.00277696, 0.00261997, 0.0023289", \ + "0.00287815, 0.00273052, 0.00279345, 0.00274084, 0.00288203, 0.00258338, 0.00234217", \ + "0.0036511, 0.00309499, 0.00298428, 0.00287029, 0.00301283, 0.00257809, 0.00228796", \ + "0.00557218, 0.0042885, 0.00394562, 0.00364958, 0.00319914, 0.00324625, 0.00254668", \ + "0.00974942, 0.00722676, 0.00655719, 0.00595402, 0.00520265, 0.00406372, 0.00358246" \ ); } fall_power (POWER_7x7ds1) { index_1 ("0.0186, 0.0966, 0.174, 0.3294, 0.6408, 1.263, 2.5074"); index_2 ("0.001, 0.0234, 0.039, 0.0648, 0.108, 0.18, 0.3"); values ( \ - "0.00433717, 0.00465441, 0.00464165, 0.00459372, 0.00451088, 0.0043123, 0.00396409", \ - "0.00404847, 0.0045401, 0.00458074, 0.00455388, 0.00450282, 0.00433117, 0.00400374", \ - "0.00409244, 0.00437534, 0.00450692, 0.00446755, 0.00444991, 0.00430152, 0.00400946", \ - "0.00437619, 0.00438187, 0.00439262, 0.00446022, 0.00455636, 0.00451754, 0.00396807", \ - "0.0051917, 0.00463461, 0.00461636, 0.00452024, 0.00441935, 0.00466855, 0.00404069", \ - "0.00714257, 0.00568892, 0.00541576, 0.00518676, 0.00496482, 0.00445978, 0.00468981", \ - "0.0113201, 0.00862302, 0.00785676, 0.00710259, 0.00649573, 0.00600479, 0.0050407" \ + "0.00433716, 0.00465106, 0.00464414, 0.00459358, 0.00447244, 0.00427803, 0.00396443", \ + "0.00404516, 0.00454135, 0.00460549, 0.00455364, 0.00447285, 0.00432999, 0.00400137", \ + "0.0040916, 0.0043753, 0.00450086, 0.00449244, 0.00443694, 0.00429404, 0.00398331", \ + "0.00437611, 0.00438197, 0.00438043, 0.00444225, 0.00446889, 0.00451316, 0.00393505", \ + "0.0051919, 0.00463411, 0.00461573, 0.00452075, 0.00445324, 0.00466964, 0.00402193", \ + "0.00714329, 0.00568857, 0.00541617, 0.00518676, 0.004967, 0.00446579, 0.00469035", \ + "0.0113197, 0.00862318, 0.0078569, 0.0071022, 0.00649659, 0.00600455, 0.00506605" \ ); } } @@ -6007,42 +6007,42 @@ library (sg13g2_stdcell_typ_1p20V_25C) { direction : "input"; max_transition : 2.5074; capacitance : 0.00310361; - rise_capacitance : 0.00308057; - rise_capacitance_range (0.00308057, 0.00308057); - fall_capacitance : 0.00312665; - fall_capacitance_range (0.00312665, 0.00312665); + rise_capacitance : 0.00308062; + rise_capacitance_range (0.00288217, 0.00329857); + fall_capacitance : 0.0031266; + fall_capacitance_range (0.00276176, 0.00351951); } pin (A2) { direction : "input"; max_transition : 2.5074; - capacitance : 0.00309569; - rise_capacitance : 0.00314706; - rise_capacitance_range (0.00314706, 0.00314706); - fall_capacitance : 0.00304433; - fall_capacitance_range (0.00304433, 0.00304433); + capacitance : 0.00309576; + rise_capacitance : 0.00314714; + rise_capacitance_range (0.00276035, 0.00347264); + fall_capacitance : 0.00304438; + fall_capacitance_range (0.00275153, 0.00338998); } pin (B1) { direction : "input"; max_transition : 2.5074; - capacitance : 0.00303787; - rise_capacitance : 0.00317505; - rise_capacitance_range (0.00317505, 0.00317505); - fall_capacitance : 0.0029007; - fall_capacitance_range (0.0029007, 0.0029007); + capacitance : 0.00303788; + rise_capacitance : 0.00317504; + rise_capacitance_range (0.00262961, 0.00358759); + fall_capacitance : 0.00290071; + fall_capacitance_range (0.00269354, 0.0031315); } pin (B2) { direction : "input"; max_transition : 2.5074; - capacitance : 0.00301539; - rise_capacitance : 0.00307879; - rise_capacitance_range (0.00307879, 0.00307879); - fall_capacitance : 0.002952; - fall_capacitance_range (0.002952, 0.002952); + capacitance : 0.00301537; + rise_capacitance : 0.00307877; + rise_capacitance_range (0.00260425, 0.00343255); + fall_capacitance : 0.00295198; + fall_capacitance_range (0.00259745, 0.00326496); } } cell (sg13g2_and2_1) { area : 9.072; - cell_footprint : "AND2"; + cell_footprint : "and2"; cell_leakage_power : 137.61; leakage_power () { value : 177.219; @@ -6243,23 +6243,23 @@ library (sg13g2_stdcell_typ_1p20V_25C) { max_transition : 2.5074; capacitance : 0.00254256; rise_capacitance : 0.00254437; - rise_capacitance_range (0.00254437, 0.00254437); + rise_capacitance_range (0.00230554, 0.00271425); fall_capacitance : 0.00254074; - fall_capacitance_range (0.00254074, 0.00254074); + fall_capacitance_range (0.00226854, 0.00274159); } pin (B) { direction : "input"; max_transition : 2.5074; capacitance : 0.00253612; rise_capacitance : 0.0025895; - rise_capacitance_range (0.0025895, 0.0025895); + rise_capacitance_range (0.00225673, 0.00286957); fall_capacitance : 0.00248274; - fall_capacitance_range (0.00248274, 0.00248274); + fall_capacitance_range (0.00231653, 0.0026278); } } cell (sg13g2_and2_2) { area : 10.8864; - cell_footprint : "AND2"; + cell_footprint : "and2"; cell_leakage_power : 210.32; leakage_power () { value : 220.804; @@ -6460,23 +6460,23 @@ library (sg13g2_stdcell_typ_1p20V_25C) { max_transition : 2.5074; capacitance : 0.00253864; rise_capacitance : 0.00254264; - rise_capacitance_range (0.00254264, 0.00254264); + rise_capacitance_range (0.00236056, 0.00269082); fall_capacitance : 0.00253463; - fall_capacitance_range (0.00253463, 0.00253463); + fall_capacitance_range (0.00232369, 0.00270243); } pin (B) { direction : "input"; max_transition : 2.5074; capacitance : 0.00255322; rise_capacitance : 0.00261141; - rise_capacitance_range (0.00261141, 0.00261141); + rise_capacitance_range (0.00230176, 0.00287601); fall_capacitance : 0.00249503; - fall_capacitance_range (0.00249503, 0.00249503); + fall_capacitance_range (0.00235778, 0.00262088); } } cell (sg13g2_and3_1) { area : 12.7008; - cell_footprint : "AND3"; + cell_footprint : "and3"; cell_leakage_power : 146.662; leakage_power () { value : 244.071; @@ -6779,32 +6779,32 @@ library (sg13g2_stdcell_typ_1p20V_25C) { max_transition : 2.5074; capacitance : 0.00253572; rise_capacitance : 0.0025286; - rise_capacitance_range (0.0025286, 0.0025286); + rise_capacitance_range (0.00231201, 0.00267554); fall_capacitance : 0.00254283; - fall_capacitance_range (0.00254283, 0.00254283); + fall_capacitance_range (0.00224843, 0.00276795); } pin (B) { direction : "input"; max_transition : 2.5074; capacitance : 0.00251441; rise_capacitance : 0.00255653; - rise_capacitance_range (0.00255653, 0.00255653); + rise_capacitance_range (0.00223107, 0.00283187); fall_capacitance : 0.00247229; - fall_capacitance_range (0.00247229, 0.00247229); + fall_capacitance_range (0.00225494, 0.00264693); } pin (C) { direction : "input"; max_transition : 2.5074; capacitance : 0.00252248; rise_capacitance : 0.00257661; - rise_capacitance_range (0.00257661, 0.00257661); + rise_capacitance_range (0.00226036, 0.00287247); fall_capacitance : 0.00246835; - fall_capacitance_range (0.00246835, 0.00246835); + fall_capacitance_range (0.0023231, 0.00260115); } } cell (sg13g2_and3_2) { area : 12.7008; - cell_footprint : "AND3"; + cell_footprint : "and3"; cell_leakage_power : 224.225; leakage_power () { value : 287.638; @@ -7107,32 +7107,32 @@ library (sg13g2_stdcell_typ_1p20V_25C) { max_transition : 2.5074; capacitance : 0.00255446; rise_capacitance : 0.00255073; - rise_capacitance_range (0.00255073, 0.00255073); + rise_capacitance_range (0.00237823, 0.00268409); fall_capacitance : 0.00255819; - fall_capacitance_range (0.00255819, 0.00255819); + fall_capacitance_range (0.00232587, 0.0027481); } pin (B) { direction : "input"; max_transition : 2.5074; capacitance : 0.00252396; rise_capacitance : 0.00257083; - rise_capacitance_range (0.00257083, 0.00257083); + rise_capacitance_range (0.00226443, 0.00283506); fall_capacitance : 0.00247709; - fall_capacitance_range (0.00247709, 0.00247709); + fall_capacitance_range (0.00229638, 0.00262999); } pin (C) { direction : "input"; max_transition : 2.5074; capacitance : 0.00252784; rise_capacitance : 0.00258596; - rise_capacitance_range (0.00258596, 0.00258596); + rise_capacitance_range (0.00228302, 0.00286771); fall_capacitance : 0.00246972; - fall_capacitance_range (0.00246972, 0.00246972); + fall_capacitance_range (0.00234462, 0.00258799); } } cell (sg13g2_and4_1) { area : 14.5152; - cell_footprint : "AND4"; + cell_footprint : "and4"; cell_leakage_power : 151.909; leakage_power () { value : 148.023; @@ -7553,41 +7553,41 @@ library (sg13g2_stdcell_typ_1p20V_25C) { max_transition : 2.5074; capacitance : 0.00236977; rise_capacitance : 0.0023564; - rise_capacitance_range (0.0023564, 0.0023564); + rise_capacitance_range (0.00215511, 0.00248976); fall_capacitance : 0.00238314; - fall_capacitance_range (0.00238314, 0.00238314); + fall_capacitance_range (0.00208392, 0.0026277); } pin (B) { direction : "input"; max_transition : 2.5074; capacitance : 0.00249579; rise_capacitance : 0.00253026; - rise_capacitance_range (0.00253026, 0.00253026); + rise_capacitance_range (0.00221335, 0.00280311); fall_capacitance : 0.00246131; - fall_capacitance_range (0.00246131, 0.00246131); + fall_capacitance_range (0.0022174, 0.00266038); } pin (C) { direction : "input"; max_transition : 2.5074; capacitance : 0.00249119; rise_capacitance : 0.00253497; - rise_capacitance_range (0.00253497, 0.00253497); + rise_capacitance_range (0.00222051, 0.00282873); fall_capacitance : 0.00244741; - fall_capacitance_range (0.00244741, 0.00244741); + fall_capacitance_range (0.00225529, 0.00260864); } pin (D) { direction : "input"; max_transition : 2.5074; capacitance : 0.00249915; rise_capacitance : 0.00255237; - rise_capacitance_range (0.00255237, 0.00255237); + rise_capacitance_range (0.00224909, 0.00283577); fall_capacitance : 0.00244592; - fall_capacitance_range (0.00244592, 0.00244592); + fall_capacitance_range (0.00231763, 0.00257304); } } cell (sg13g2_and4_2) { area : 16.3296; - cell_footprint : "AND4"; + cell_footprint : "and4"; cell_leakage_power : 231.889; leakage_power () { value : 230.432; @@ -8008,41 +8008,41 @@ library (sg13g2_stdcell_typ_1p20V_25C) { max_transition : 2.5074; capacitance : 0.00237367; rise_capacitance : 0.00236495; - rise_capacitance_range (0.00236495, 0.00236495); + rise_capacitance_range (0.00220201, 0.00248362); fall_capacitance : 0.0023824; - fall_capacitance_range (0.0023824, 0.0023824); + fall_capacitance_range (0.00215019, 0.00258836); } pin (B) { direction : "input"; max_transition : 2.5074; capacitance : 0.00249258; rise_capacitance : 0.00253172; - rise_capacitance_range (0.00253172, 0.00253172); + rise_capacitance_range (0.00222969, 0.0027949); fall_capacitance : 0.00245345; - fall_capacitance_range (0.00245345, 0.00245345); + fall_capacitance_range (0.00224678, 0.00263252); } pin (C) { direction : "input"; max_transition : 2.5074; capacitance : 0.00249039; rise_capacitance : 0.00253879; - rise_capacitance_range (0.00253879, 0.00253879); + rise_capacitance_range (0.00223949, 0.00282); fall_capacitance : 0.00244199; - fall_capacitance_range (0.00244199, 0.00244199); + fall_capacitance_range (0.00227275, 0.00259109); } pin (D) { direction : "input"; max_transition : 2.5074; capacitance : 0.0024971; rise_capacitance : 0.00255491; - rise_capacitance_range (0.00255491, 0.00255491); + rise_capacitance_range (0.00226665, 0.00282622); fall_capacitance : 0.00243929; - fall_capacitance_range (0.00243929, 0.00243929); + fall_capacitance_range (0.00232587, 0.00255386); } } cell (sg13g2_antennanp) { area : 5.4432; - cell_footprint : "NP_ant"; + cell_footprint : "antennanp"; cell_leakage_power : 4.32001; dont_touch : true; dont_use : true; @@ -8059,9 +8059,9 @@ library (sg13g2_stdcell_typ_1p20V_25C) { max_transition : 2.5074; capacitance : 0.0010804; rise_capacitance : 0.00104669; - rise_capacitance_range (0.00104669, 0.00104669); + rise_capacitance_range (0.000250496, 0.00167391); fall_capacitance : 0.0011141; - fall_capacitance_range (0.0011141, 0.0011141); + fall_capacitance_range (0.000251979, 0.00177329); internal_power () { rise_power (passive_POWER_7x1ds1) { index_1 ("0.0186, 0.0966, 0.174, 0.3294, 0.6408, 1.263, 2.5074"); @@ -8080,7 +8080,7 @@ library (sg13g2_stdcell_typ_1p20V_25C) { } cell (sg13g2_buf_1) { area : 7.2576; - cell_footprint : "BU"; + cell_footprint : "buf"; cell_leakage_power : 110.317; leakage_power () { value : 113.99; @@ -8187,14 +8187,14 @@ library (sg13g2_stdcell_typ_1p20V_25C) { max_transition : 2.5074; capacitance : 0.00226339; rise_capacitance : 0.00229273; - rise_capacitance_range (0.00229273, 0.00229273); + rise_capacitance_range (0.00207295, 0.00245048); fall_capacitance : 0.00223405; - fall_capacitance_range (0.00223405, 0.00223405); + fall_capacitance_range (0.0020413, 0.0024117); } } cell (sg13g2_buf_16) { area : 45.36; - cell_footprint : "BU"; + cell_footprint : "buf"; cell_leakage_power : 1385.39; leakage_power () { value : 1191.03; @@ -8301,14 +8301,14 @@ library (sg13g2_stdcell_typ_1p20V_25C) { max_transition : 2.5074; capacitance : 0.0170499; rise_capacitance : 0.0173358; - rise_capacitance_range (0.0173358, 0.0173358); + rise_capacitance_range (0.0158377, 0.0185105); fall_capacitance : 0.016764; - fall_capacitance_range (0.016764, 0.016764); + fall_capacitance_range (0.0154452, 0.017924); } } cell (sg13g2_buf_2) { area : 9.072; - cell_footprint : "BU"; + cell_footprint : "buf"; cell_leakage_power : 181.545; leakage_power () { value : 202.562; @@ -8415,14 +8415,14 @@ library (sg13g2_stdcell_typ_1p20V_25C) { max_transition : 2.5074; capacitance : 0.00261926; rise_capacitance : 0.002663; - rise_capacitance_range (0.002663, 0.002663); + rise_capacitance_range (0.00245416, 0.00282907); fall_capacitance : 0.00257552; - fall_capacitance_range (0.00257552, 0.00257552); + fall_capacitance_range (0.00238551, 0.00275503); } } cell (sg13g2_buf_4) { area : 14.5152; - cell_footprint : "BU"; + cell_footprint : "buf"; cell_leakage_power : 337.354; leakage_power () { value : 291.93; @@ -8529,14 +8529,14 @@ library (sg13g2_stdcell_typ_1p20V_25C) { max_transition : 2.5074; capacitance : 0.00370215; rise_capacitance : 0.0038592; - rise_capacitance_range (0.0038592, 0.0038592); + rise_capacitance_range (0.00361258, 0.00403631); fall_capacitance : 0.00354511; - fall_capacitance_range (0.00354511, 0.00354511); + fall_capacitance_range (0.00328275, 0.00384679); } } cell (sg13g2_buf_8) { area : 23.5872; - cell_footprint : "BU"; + cell_footprint : "buf"; cell_leakage_power : 692.69; leakage_power () { value : 595.512; @@ -8643,14 +8643,14 @@ library (sg13g2_stdcell_typ_1p20V_25C) { max_transition : 2.5074; capacitance : 0.00856578; rise_capacitance : 0.00870885; - rise_capacitance_range (0.00870885, 0.00870885); + rise_capacitance_range (0.0080112, 0.00929224); fall_capacitance : 0.00842272; - fall_capacitance_range (0.00842272, 0.00842272); + fall_capacitance_range (0.00781194, 0.00899306); } } cell (sg13g2_decap_4) { area : 7.2576; - cell_footprint : "DECAP"; + cell_footprint : "decap"; cell_leakage_power : 395.59; dont_touch : true; dont_use : true; @@ -8658,7 +8658,7 @@ library (sg13g2_stdcell_typ_1p20V_25C) { } cell (sg13g2_decap_8) { area : 12.7008; - cell_footprint : "DECAP"; + cell_footprint : "decap"; cell_leakage_power : 791.198; dont_touch : true; dont_use : true; @@ -8666,7 +8666,7 @@ library (sg13g2_stdcell_typ_1p20V_25C) { } cell (sg13g2_dfrbp_1) { area : 52.6176; - cell_footprint : "dffrr"; + cell_footprint : "dfrbp"; cell_leakage_power : 567.01; leakage_power () { value : 488.102; @@ -8723,6 +8723,7 @@ library (sg13g2_stdcell_typ_1p20V_25C) { max_capacitance : 0.3; timing () { related_pin : "CLK"; + sdf_edges : start_edge; timing_sense : non_unate; timing_type : rising_edge; cell_rise (TIMING_DELAY_7x7ds1) { @@ -8780,6 +8781,7 @@ library (sg13g2_stdcell_typ_1p20V_25C) { } timing () { related_pin : "RESET_B"; + sdf_edges : start_edge; timing_sense : positive_unate; timing_type : clear; cell_fall (TIMING_DELAY_7x7ds1) { @@ -8867,6 +8869,7 @@ library (sg13g2_stdcell_typ_1p20V_25C) { max_capacitance : 0.3; timing () { related_pin : "CLK"; + sdf_edges : start_edge; timing_sense : non_unate; timing_type : rising_edge; cell_rise (TIMING_DELAY_7x7ds1) { @@ -8924,6 +8927,7 @@ library (sg13g2_stdcell_typ_1p20V_25C) { } timing () { related_pin : "RESET_B"; + sdf_edges : start_edge; timing_sense : negative_unate; timing_type : preset; cell_rise (TIMING_DELAY_7x7ds1) { @@ -9010,9 +9014,9 @@ library (sg13g2_stdcell_typ_1p20V_25C) { max_transition : 2.5074; capacitance : 0.00279631; rise_capacitance : 0.00296996; - rise_capacitance_range (0.00296996, 0.00296996); + rise_capacitance_range (0.00271744, 0.00316917); fall_capacitance : 0.00253584; - fall_capacitance_range (0.00253584, 0.00253584); + fall_capacitance_range (0.00253584, 0.00307487); timing () { related_pin : "CLK"; timing_type : min_pulse_width; @@ -9138,11 +9142,12 @@ library (sg13g2_stdcell_typ_1p20V_25C) { max_transition : 2.5074; capacitance : 0.00154954; rise_capacitance : 0.00141663; - rise_capacitance_range (0.00141663, 0.00141663); + rise_capacitance_range (0.00133291, 0.00160421); fall_capacitance : 0.00168246; - fall_capacitance_range (0.00168246, 0.00168246); + fall_capacitance_range (0.00168246, 0.00265152); timing () { related_pin : "CLK"; + sdf_edges : both_edges; timing_type : hold_rising; rise_constraint (CONSTRAINT_4x4) { index_1 ("0.0186, 0.51636, 1.263, 2.5074"); @@ -9167,6 +9172,7 @@ library (sg13g2_stdcell_typ_1p20V_25C) { } timing () { related_pin : "CLK"; + sdf_edges : both_edges; timing_type : setup_rising; rise_constraint (CONSTRAINT_4x4) { index_1 ("0.0186, 0.51636, 1.263, 2.5074"); @@ -9254,11 +9260,12 @@ library (sg13g2_stdcell_typ_1p20V_25C) { max_transition : 2.5074; capacitance : 0.00513299; rise_capacitance : 0.00521458; - rise_capacitance_range (0.00521458, 0.00521458); + rise_capacitance_range (0.00448784, 0.00644869); fall_capacitance : 0.00507471; - fall_capacitance_range (0.00507471, 0.00507471); + fall_capacitance_range (0.0047304, 0.00526895); timing () { related_pin : "CLK"; + sdf_edges : both_edges; timing_type : recovery_rising; rise_constraint (CONSTRAINT_4x4) { index_1 ("0.0186, 0.51636, 1.263, 2.5074"); @@ -9273,6 +9280,7 @@ library (sg13g2_stdcell_typ_1p20V_25C) { } timing () { related_pin : "CLK"; + sdf_edges : both_edges; timing_type : removal_rising; rise_constraint (CONSTRAINT_4x4) { index_1 ("0.0186, 0.51636, 1.263, 2.5074"); @@ -9371,14 +9379,14 @@ library (sg13g2_stdcell_typ_1p20V_25C) { } } ff (IQ,IQN) { - clear : "RESET_B'"; + clear : "!RESET_B"; clocked_on : "CLK"; next_state : "D"; } } cell (sg13g2_dfrbp_2) { area : 54.432; - cell_footprint : "dffrr"; + cell_footprint : "dfrbp"; cell_leakage_power : 686.11; leakage_power () { value : 608.26; @@ -9435,6 +9443,7 @@ library (sg13g2_stdcell_typ_1p20V_25C) { max_capacitance : 0.6; timing () { related_pin : "CLK"; + sdf_edges : start_edge; timing_sense : non_unate; timing_type : rising_edge; cell_rise (TIMING_DELAY_7x7ds1) { @@ -9492,6 +9501,7 @@ library (sg13g2_stdcell_typ_1p20V_25C) { } timing () { related_pin : "RESET_B"; + sdf_edges : start_edge; timing_sense : positive_unate; timing_type : clear; cell_fall (TIMING_DELAY_7x7ds1) { @@ -9579,6 +9589,7 @@ library (sg13g2_stdcell_typ_1p20V_25C) { max_capacitance : 0.6; timing () { related_pin : "CLK"; + sdf_edges : start_edge; timing_sense : non_unate; timing_type : rising_edge; cell_rise (TIMING_DELAY_7x7ds1) { @@ -9636,6 +9647,7 @@ library (sg13g2_stdcell_typ_1p20V_25C) { } timing () { related_pin : "RESET_B"; + sdf_edges : start_edge; timing_sense : negative_unate; timing_type : preset; cell_rise (TIMING_DELAY_7x7ds1) { @@ -9722,9 +9734,9 @@ library (sg13g2_stdcell_typ_1p20V_25C) { max_transition : 2.5074; capacitance : 0.00280582; rise_capacitance : 0.00297999; - rise_capacitance_range (0.00297999, 0.00297999); + rise_capacitance_range (0.00272987, 0.00317829); fall_capacitance : 0.00254457; - fall_capacitance_range (0.00254457, 0.00254457); + fall_capacitance_range (0.00254457, 0.00308447); timing () { related_pin : "CLK"; timing_type : min_pulse_width; @@ -9850,11 +9862,12 @@ library (sg13g2_stdcell_typ_1p20V_25C) { max_transition : 2.5074; capacitance : 0.00155334; rise_capacitance : 0.00142042; - rise_capacitance_range (0.00142042, 0.00142042); + rise_capacitance_range (0.00133681, 0.00160768); fall_capacitance : 0.00168626; - fall_capacitance_range (0.00168626, 0.00168626); + fall_capacitance_range (0.00168626, 0.00265487); timing () { related_pin : "CLK"; + sdf_edges : both_edges; timing_type : hold_rising; rise_constraint (CONSTRAINT_4x4) { index_1 ("0.0186, 0.51636, 1.263, 2.5074"); @@ -9879,6 +9892,7 @@ library (sg13g2_stdcell_typ_1p20V_25C) { } timing () { related_pin : "CLK"; + sdf_edges : both_edges; timing_type : setup_rising; rise_constraint (CONSTRAINT_4x4) { index_1 ("0.0186, 0.51636, 1.263, 2.5074"); @@ -9966,11 +9980,12 @@ library (sg13g2_stdcell_typ_1p20V_25C) { max_transition : 2.5074; capacitance : 0.00518374; rise_capacitance : 0.00526552; - rise_capacitance_range (0.00526552, 0.00526552); + rise_capacitance_range (0.0045337, 0.00650065); fall_capacitance : 0.00512532; - fall_capacitance_range (0.00512532, 0.00512532); + fall_capacitance_range (0.00477494, 0.00531738); timing () { related_pin : "CLK"; + sdf_edges : both_edges; timing_type : recovery_rising; rise_constraint (CONSTRAINT_4x4) { index_1 ("0.0186, 0.51636, 1.263, 2.5074"); @@ -9985,6 +10000,7 @@ library (sg13g2_stdcell_typ_1p20V_25C) { } timing () { related_pin : "CLK"; + sdf_edges : both_edges; timing_type : removal_rising; rise_constraint (CONSTRAINT_4x4) { index_1 ("0.0186, 0.51636, 1.263, 2.5074"); @@ -10083,7 +10099,7 @@ library (sg13g2_stdcell_typ_1p20V_25C) { } } ff (IQ,IQN) { - clear : "RESET_B'"; + clear : "!RESET_B"; clocked_on : "CLK"; next_state : "D"; } @@ -10091,13 +10107,13 @@ library (sg13g2_stdcell_typ_1p20V_25C) { cell (sg13g2_dfrbpq_1) { area : 48.9888; cell_footprint : "dfrbpq"; - cell_leakage_power : 510.516; + cell_leakage_power : 510.517; leakage_power () { - value : 444.565; + value : 444.566; when : "!CLK&!D&!RESET_B&!Q"; } leakage_power () { - value : 446.694; + value : 446.695; when : "!CLK&D&!RESET_B&!Q"; } leakage_power () { @@ -10105,15 +10121,15 @@ library (sg13g2_stdcell_typ_1p20V_25C) { when : "CLK&!D&!RESET_B&!Q"; } leakage_power () { - value : 445.339; + value : 445.34; when : "CLK&D&!RESET_B&!Q"; } leakage_power () { - value : 569.707; + value : 569.708; when : "!CLK&!D&RESET_B&Q"; } leakage_power () { - value : 474.048; + value : 474.049; when : "!CLK&!D&RESET_B&!Q"; } leakage_power () { @@ -10125,15 +10141,15 @@ library (sg13g2_stdcell_typ_1p20V_25C) { when : "!CLK&D&RESET_B&!Q"; } leakage_power () { - value : 556.169; + value : 556.17; when : "CLK&!D&RESET_B&Q"; } leakage_power () { - value : 478.463; + value : 478.464; when : "CLK&!D&RESET_B&!Q"; } leakage_power () { - value : 566.681; + value : 566.682; when : "CLK&D&RESET_B&Q"; } leakage_power () { @@ -10147,89 +10163,91 @@ library (sg13g2_stdcell_typ_1p20V_25C) { max_capacitance : 0.3; timing () { related_pin : "CLK"; + sdf_edges : start_edge; timing_sense : non_unate; timing_type : rising_edge; cell_rise (TIMING_DELAY_7x7ds1) { index_1 ("0.0186, 0.0966, 0.174, 0.3294, 0.6408, 1.263, 2.5074"); index_2 ("0.001, 0.0234, 0.039, 0.0648, 0.108, 0.18, 0.3"); values ( \ - "0.156312, 0.221556, 0.264872, 0.336742, 0.456284, 0.655461, 0.98727", \ - "0.193883, 0.259702, 0.303134, 0.374646, 0.494267, 0.693571, 1.02603", \ - "0.219552, 0.28525, 0.328671, 0.400172, 0.519756, 0.718981, 1.05283", \ - "0.258003, 0.323679, 0.367198, 0.438686, 0.558207, 0.75734, 1.0894", \ - "0.313349, 0.378983, 0.422406, 0.494019, 0.613563, 0.812697, 1.14462", \ - "0.389671, 0.455303, 0.498808, 0.570266, 0.689911, 0.889149, 1.22102", \ - "0.492522, 0.55849, 0.601935, 0.673454, 0.793027, 0.992345, 1.32417" \ + "0.156308, 0.221619, 0.264884, 0.336648, 0.456168, 0.655301, 0.987326", \ + "0.193833, 0.259633, 0.303122, 0.374638, 0.49415, 0.693612, 1.02512", \ + "0.219572, 0.285242, 0.328648, 0.400126, 0.51977, 0.718833, 1.05258", \ + "0.258013, 0.32367, 0.367176, 0.438641, 0.558131, 0.757192, 1.08914", \ + "0.313359, 0.378974, 0.422383, 0.493974, 0.61348, 0.812568, 1.14437", \ + "0.389641, 0.455279, 0.498779, 0.570213, 0.68982, 0.889048, 1.22068", \ + "0.492539, 0.558489, 0.60192, 0.673416, 0.792976, 0.992205, 1.32397" \ ); } rise_transition (TIMING_DELAY_7x7ds1) { index_1 ("0.0186, 0.0966, 0.174, 0.3294, 0.6408, 1.263, 2.5074"); index_2 ("0.001, 0.0234, 0.039, 0.0648, 0.108, 0.18, 0.3"); values ( \ - "0.0171592, 0.103129, 0.165586, 0.269038, 0.442447, 0.731919, 1.21454", \ - "0.0171635, 0.10313, 0.165587, 0.269039, 0.443241, 0.73192, 1.21455", \ - "0.0172074, 0.103131, 0.165588, 0.26904, 0.443242, 0.731942, 1.21617", \ - "0.0172353, 0.103132, 0.165589, 0.269041, 0.443243, 0.731943, 1.21703", \ - "0.0173892, 0.103133, 0.16559, 0.269042, 0.443244, 0.731944, 1.21704", \ - "0.018014, 0.103167, 0.165591, 0.269043, 0.443245, 0.731945, 1.21705", \ - "0.01921, 0.103308, 0.165669, 0.269101, 0.443246, 0.731946, 1.21706" \ + "0.0171605, 0.103075, 0.165507, 0.268958, 0.442314, 0.731734, 1.21384", \ + "0.0171621, 0.103076, 0.165508, 0.268959, 0.443122, 0.732028, 1.21385", \ + "0.0172075, 0.103077, 0.165509, 0.26896, 0.443123, 0.732029, 1.21578", \ + "0.0172326, 0.103078, 0.16551, 0.268961, 0.443124, 0.73203, 1.21579", \ + "0.0173876, 0.10308, 0.165511, 0.268962, 0.443125, 0.732031, 1.2158", \ + "0.017971, 0.103138, 0.165539, 0.268963, 0.443126, 0.732032, 1.21581", \ + "0.019207, 0.103278, 0.16562, 0.26902, 0.443127, 0.732033, 1.21582" \ ); } cell_fall (TIMING_DELAY_7x7ds1) { index_1 ("0.0186, 0.0966, 0.174, 0.3294, 0.6408, 1.263, 2.5074"); index_2 ("0.001, 0.0234, 0.039, 0.0648, 0.108, 0.18, 0.3"); values ( \ - "0.154285, 0.209118, 0.243731, 0.300859, 0.396453, 0.555453, 0.820278", \ - "0.191894, 0.246853, 0.281603, 0.338701, 0.434144, 0.593605, 0.857955", \ - "0.217177, 0.272107, 0.306819, 0.363899, 0.459339, 0.618299, 0.883161", \ - "0.253708, 0.308658, 0.343414, 0.400468, 0.495945, 0.654813, 0.919667", \ - "0.304544, 0.359502, 0.394272, 0.451322, 0.546755, 0.705678, 0.97054", \ - "0.373717, 0.428682, 0.463415, 0.520528, 0.615938, 0.774976, 1.03977", \ - "0.460282, 0.51517, 0.549932, 0.607023, 0.702482, 0.861511, 1.12629" \ + "0.154252, 0.208924, 0.243909, 0.300975, 0.396358, 0.555269, 0.820046", \ + "0.191806, 0.24679, 0.281541, 0.33864, 0.434081, 0.593547, 0.857895", \ + "0.217165, 0.272095, 0.306808, 0.36389, 0.459341, 0.61828, 0.883153", \ + "0.253696, 0.308646, 0.343403, 0.40046, 0.495937, 0.654806, 0.919635", \ + "0.304532, 0.35949, 0.394261, 0.451313, 0.546747, 0.705659, 0.970533", \ + "0.373192, 0.428141, 0.462904, 0.51997, 0.61541, 0.774318, 1.03915", \ + "0.460276, 0.515177, 0.549932, 0.607016, 0.702474, 0.861501, 1.12629" \ ); } fall_transition (TIMING_DELAY_7x7ds1) { index_1 ("0.0186, 0.0966, 0.174, 0.3294, 0.6408, 1.263, 2.5074"); index_2 ("0.001, 0.0234, 0.039, 0.0648, 0.108, 0.18, 0.3"); values ( \ - "0.0145149, 0.078703, 0.12506, 0.202012, 0.331273, 0.54709, 0.906245", \ - "0.0145719, 0.078704, 0.125061, 0.202013, 0.331425, 0.547588, 0.906318", \ - "0.0145775, 0.078705, 0.125062, 0.20204, 0.331426, 0.547589, 0.907459", \ - "0.0145962, 0.078734, 0.125063, 0.202041, 0.331427, 0.54759, 0.90746", \ - "0.0145972, 0.078735, 0.125064, 0.202042, 0.331428, 0.547591, 0.907461", \ - "0.0146, 0.078736, 0.125065, 0.202043, 0.331429, 0.547592, 0.907462", \ - "0.014611, 0.078737, 0.125066, 0.202044, 0.33143, 0.547593, 0.907463" \ + "0.0145535, 0.0787171, 0.125034, 0.201995, 0.331272, 0.54687, 0.906244", \ + "0.0145714, 0.0787181, 0.12505, 0.201996, 0.331431, 0.547473, 0.906316", \ + "0.014575, 0.0787191, 0.125051, 0.202084, 0.331432, 0.547474, 0.907458", \ + "0.0145937, 0.0787316, 0.125052, 0.202085, 0.331433, 0.547475, 0.907459", \ + "0.0145947, 0.0787326, 0.125053, 0.202086, 0.331434, 0.547476, 0.90746", \ + "0.0145957, 0.0787336, 0.125054, 0.202087, 0.331435, 0.547477, 0.907461", \ + "0.014609, 0.0787346, 0.125055, 0.202088, 0.331436, 0.547478, 0.907462" \ ); } } timing () { related_pin : "RESET_B"; + sdf_edges : start_edge; timing_sense : positive_unate; timing_type : clear; cell_fall (TIMING_DELAY_7x7ds1) { index_1 ("0.0186, 0.0966, 0.174, 0.3294, 0.6408, 1.263, 2.5074"); index_2 ("0.001, 0.0234, 0.039, 0.0648, 0.108, 0.18, 0.3"); values ( \ - "0.221449, 0.276235, 0.31102, 0.368149, 0.463687, 0.622704, 0.887645", \ - "0.264643, 0.319413, 0.354193, 0.41139, 0.506795, 0.665888, 0.930736", \ - "0.29995, 0.35479, 0.389549, 0.446717, 0.542153, 0.701132, 0.966226", \ - "0.358158, 0.413014, 0.44772, 0.504837, 0.600382, 0.759312, 1.02434", \ - "0.44675, 0.501602, 0.536361, 0.59353, 0.689013, 0.847932, 1.1128", \ - "0.569193, 0.62414, 0.658933, 0.716179, 0.811629, 0.970582, 1.23546", \ - "0.734464, 0.789539, 0.824335, 0.881489, 0.977013, 1.13601, 1.40086" \ + "0.221458, 0.276283, 0.31105, 0.368243, 0.463661, 0.622635, 0.887673", \ + "0.264618, 0.319452, 0.354201, 0.411393, 0.506754, 0.665863, 0.930731", \ + "0.299967, 0.354785, 0.389549, 0.446714, 0.542152, 0.701103, 0.966008", \ + "0.358145, 0.413003, 0.447709, 0.504828, 0.600374, 0.759315, 1.02434", \ + "0.446737, 0.501589, 0.536349, 0.59352, 0.689004, 0.847914, 1.1128", \ + "0.569179, 0.624153, 0.65892, 0.716167, 0.811618, 0.970573, 1.23545", \ + "0.734448, 0.789524, 0.824319, 0.881475, 0.977, 1.136, 1.40086" \ ); } fall_transition (TIMING_DELAY_7x7ds1) { index_1 ("0.0186, 0.0966, 0.174, 0.3294, 0.6408, 1.263, 2.5074"); index_2 ("0.001, 0.0234, 0.039, 0.0648, 0.108, 0.18, 0.3"); values ( \ - "0.0145041, 0.0785446, 0.124853, 0.201951, 0.331283, 0.546889, 0.906253", \ - "0.0145051, 0.0785527, 0.124887, 0.201952, 0.331431, 0.54689, 0.906254", \ - "0.0145061, 0.0785537, 0.124888, 0.201954, 0.331432, 0.546891, 0.906751", \ - "0.0145295, 0.0785697, 0.124889, 0.202045, 0.331433, 0.54713, 0.906752", \ - "0.0145705, 0.0785916, 0.124907, 0.202046, 0.331434, 0.547131, 0.906753", \ - "0.014771, 0.078667, 0.124908, 0.202047, 0.331435, 0.547197, 0.906754", \ - "0.014987, 0.078695, 0.12493, 0.202048, 0.331436, 0.547198, 0.906755" \ + "0.0144994, 0.0785595, 0.124868, 0.201963, 0.331271, 0.546873, 0.906252", \ + "0.0145004, 0.0785926, 0.124884, 0.201964, 0.331432, 0.546874, 0.906319", \ + "0.0145014, 0.0785936, 0.124885, 0.201965, 0.331433, 0.546882, 0.906503", \ + "0.0145276, 0.0785946, 0.124886, 0.202044, 0.331434, 0.546883, 0.906504", \ + "0.0145686, 0.0785956, 0.124906, 0.202045, 0.331435, 0.546884, 0.906505", \ + "0.01477, 0.078623, 0.124907, 0.202046, 0.331436, 0.547195, 0.906506", \ + "0.014984, 0.078693, 0.124928, 0.202047, 0.331437, 0.547196, 0.906507" \ ); } } @@ -10239,26 +10257,26 @@ library (sg13g2_stdcell_typ_1p20V_25C) { index_1 ("0.0186, 0.0966, 0.174, 0.3294, 0.6408, 1.263, 2.5074"); index_2 ("0.001, 0.0234, 0.039, 0.0648, 0.108, 0.18, 0.3"); values ( \ - "0.0251095, 0.0254623, 0.0254676, 0.0254558, 0.0253643, 0.0251641, 0.0252178", \ - "0.024638, 0.0251242, 0.0250866, 0.0250582, 0.0250257, 0.024725, 0.0247532", \ - "0.0246319, 0.0250048, 0.0250574, 0.0251755, 0.0249071, 0.0247179, 0.0250082", \ - "0.0248227, 0.0252424, 0.0252169, 0.0251688, 0.0253021, 0.0249362, 0.0251347", \ - "0.0257003, 0.026091, 0.0261106, 0.0261767, 0.0260197, 0.0260136, 0.0257675", \ - "0.0279521, 0.0282863, 0.0283633, 0.0283741, 0.0284075, 0.0283188, 0.0279452", \ - "0.0331029, 0.0334407, 0.033507, 0.0334454, 0.033553, 0.0335522, 0.0334589" \ + "0.0251131, 0.0254725, 0.0254472, 0.0254579, 0.0253556, 0.0251666, 0.0252001", \ + "0.0246342, 0.0251174, 0.0251156, 0.0250636, 0.0250095, 0.0248135, 0.0247885", \ + "0.0246334, 0.0250032, 0.0250637, 0.0250503, 0.0249003, 0.0246879, 0.0248815", \ + "0.024823, 0.0252402, 0.0252326, 0.0251834, 0.0253187, 0.024939, 0.0249982", \ + "0.0257029, 0.0260902, 0.0261106, 0.026171, 0.0259684, 0.0259731, 0.0258028", \ + "0.02795, 0.0282851, 0.0283749, 0.0283714, 0.0284097, 0.0283172, 0.0279473", \ + "0.033103, 0.0334423, 0.0335073, 0.0334477, 0.0335466, 0.0335482, 0.033436" \ ); } fall_power (POWER_7x7ds1) { index_1 ("0.0186, 0.0966, 0.174, 0.3294, 0.6408, 1.263, 2.5074"); index_2 ("0.001, 0.0234, 0.039, 0.0648, 0.108, 0.18, 0.3"); values ( \ - "0.0259607, 0.0264055, 0.026389, 0.0263555, 0.0262872, 0.0261051, 0.025749", \ - "0.0256379, 0.0261104, 0.0262211, 0.0260937, 0.0260047, 0.0258764, 0.025419", \ - "0.0257796, 0.0262215, 0.0262068, 0.0262522, 0.0261092, 0.0259274, 0.0257319", \ - "0.0260954, 0.0265821, 0.0266127, 0.026525, 0.0264391, 0.0265335, 0.0260711", \ - "0.0271088, 0.0275792, 0.0276314, 0.0275926, 0.0276458, 0.0273272, 0.027376", \ - "0.0295109, 0.0299703, 0.0299784, 0.0300558, 0.0300172, 0.0300531, 0.0297411", \ - "0.0345632, 0.0350231, 0.0350286, 0.035092, 0.034943, 0.0350383, 0.0350868" \ + "0.0259578, 0.0263787, 0.0264472, 0.0263914, 0.0262725, 0.0260883, 0.0257081", \ + "0.0256334, 0.0261136, 0.0262207, 0.0260931, 0.0260016, 0.0258911, 0.0254199", \ + "0.0257769, 0.0262252, 0.0262104, 0.0262392, 0.0261158, 0.0259563, 0.0257356", \ + "0.0260985, 0.026584, 0.0266091, 0.0265719, 0.0264378, 0.0264612, 0.0260407", \ + "0.0271087, 0.0275813, 0.0276343, 0.0276189, 0.0276492, 0.0271998, 0.0274477", \ + "0.02948, 0.029938, 0.0299477, 0.0300234, 0.0299989, 0.0300215, 0.029733", \ + "0.0345652, 0.0350182, 0.0350279, 0.0350979, 0.0349476, 0.0350093, 0.03509" \ ); } } @@ -10273,13 +10291,13 @@ library (sg13g2_stdcell_typ_1p20V_25C) { index_1 ("0.0186, 0.0966, 0.174, 0.3294, 0.6408, 1.263, 2.5074"); index_2 ("0.001, 0.0234, 0.039, 0.0648, 0.108, 0.18, 0.3"); values ( \ - "0.016334, 0.0167692, 0.016776, 0.016755, 0.0166714, 0.0165037, 0.0161739", \ - "0.0161734, 0.0166627, 0.0166129, 0.0165815, 0.0165004, 0.0163125, 0.0159492", \ - "0.0161361, 0.0165748, 0.0165946, 0.0166129, 0.0165992, 0.0162977, 0.0160025", \ - "0.0163142, 0.0167507, 0.0167631, 0.0167178, 0.0167808, 0.0165257, 0.0161137", \ - "0.0167864, 0.0172273, 0.0172833, 0.0173062, 0.0171348, 0.0169649, 0.017092", \ - "0.0180529, 0.0184711, 0.0185386, 0.0185304, 0.0185425, 0.0186173, 0.0178801", \ - "0.0203475, 0.0207683, 0.0208145, 0.0207672, 0.0207735, 0.0208165, 0.0207422" \ + "0.0163321, 0.0167759, 0.0167933, 0.0167601, 0.0166612, 0.016475, 0.0161872", \ + "0.0161685, 0.0166634, 0.0166178, 0.0165869, 0.01649, 0.0163125, 0.0159498", \ + "0.0161346, 0.0165707, 0.0165998, 0.0166112, 0.0165976, 0.0162731, 0.0159645", \ + "0.0163164, 0.0167582, 0.0167667, 0.0167219, 0.0167846, 0.0164821, 0.0161228", \ + "0.0167875, 0.0172294, 0.0172841, 0.0173073, 0.0172292, 0.0169194, 0.0170781", \ + "0.018058, 0.0184695, 0.0185414, 0.018534, 0.0185469, 0.0186209, 0.0178853", \ + "0.0203505, 0.0207718, 0.0208186, 0.0207714, 0.0207759, 0.0208211, 0.0206655" \ ); } } @@ -10288,11 +10306,11 @@ library (sg13g2_stdcell_typ_1p20V_25C) { clock : true; direction : "input"; max_transition : 2.5074; - capacitance : 0.00276968; + capacitance : 0.00276976; rise_capacitance : 0.00296935; - rise_capacitance_range (0.00296935, 0.00296935); - fall_capacitance : 0.00253673; - fall_capacitance_range (0.00253673, 0.00253673); + rise_capacitance_range (0.0027217, 0.00316911); + fall_capacitance : 0.00253691; + fall_capacitance_range (0.00253691, 0.00307489); timing () { related_pin : "CLK"; timing_type : min_pulse_width; @@ -10314,13 +10332,13 @@ library (sg13g2_stdcell_typ_1p20V_25C) { rise_power (passive_POWER_7x1ds1) { index_1 ("0.0186, 0.0966, 0.174, 0.3294, 0.6408, 1.263, 2.5074"); values ( \ - "0.0110468, 0.0106605, 0.0106869, 0.010912, 0.0118401, 0.0140235, 0.0189921" \ + "0.0110356, 0.0106749, 0.0106884, 0.0109122, 0.0118398, 0.0140243, 0.0189927" \ ); } fall_power (passive_POWER_7x1ds1) { index_1 ("0.0186, 0.0966, 0.174, 0.3294, 0.6408, 1.263, 2.5074"); values ( \ - "0.021094, 0.020736, 0.0208111, 0.0210998, 0.0219281, 0.0242261, 0.0295468" \ + "0.0210991, 0.0207545, 0.0207998, 0.0211, 0.0219278, 0.0242271, 0.0295465" \ ); } } @@ -10334,7 +10352,7 @@ library (sg13g2_stdcell_typ_1p20V_25C) { fall_power (passive_POWER_7x1ds1) { index_1 ("0.0186, 0.0966, 0.174, 0.3294, 0.6408, 1.263, 2.5074"); values ( \ - "0.0206634, 0.0203175, 0.0203514, 0.020658, 0.0214932, 0.0237723, 0.0291294" \ + "0.0206859, 0.020313, 0.02035, 0.0206571, 0.0214941, 0.0237711, 0.0291293" \ ); } } @@ -10343,13 +10361,13 @@ library (sg13g2_stdcell_typ_1p20V_25C) { rise_power (passive_POWER_7x1ds1) { index_1 ("0.0186, 0.0966, 0.174, 0.3294, 0.6408, 1.263, 2.5074"); values ( \ - "0.0115783, 0.0112061, 0.0112106, 0.0114737, 0.0123651, 0.0145604, 0.0194949" \ + "0.0115939, 0.011221, 0.0112103, 0.0114703, 0.0123634, 0.0145585, 0.0194936" \ ); } fall_power (passive_POWER_7x1ds1) { index_1 ("0.0186, 0.0966, 0.174, 0.3294, 0.6408, 1.263, 2.5074"); values ( \ - "0.0107172, 0.010377, 0.0104421, 0.0107556, 0.0116688, 0.0139106, 0.0189843" \ + "0.0107147, 0.0103875, 0.0104422, 0.0107559, 0.0116692, 0.0139106, 0.0189849" \ ); } } @@ -10363,7 +10381,7 @@ library (sg13g2_stdcell_typ_1p20V_25C) { fall_power (passive_POWER_7x1ds1) { index_1 ("0.0186, 0.0966, 0.174, 0.3294, 0.6408, 1.263, 2.5074"); values ( \ - "0.0350379, 0.0353217, 0.0350712, 0.0352445, 0.0361698, 0.0384177, 0.0435519" \ + "0.0350779, 0.0353329, 0.0350719, 0.0352458, 0.0361795, 0.0384197, 0.0435512" \ ); } } @@ -10372,13 +10390,13 @@ library (sg13g2_stdcell_typ_1p20V_25C) { rise_power (passive_POWER_7x1ds1) { index_1 ("0.0186, 0.0966, 0.174, 0.3294, 0.6408, 1.263, 2.5074"); values ( \ - "0.0108252, 0.01045, 0.0104583, 0.0106938, 0.0116059, 0.0137886, 0.0187338" \ + "0.0108139, 0.0104442, 0.0104514, 0.0106937, 0.0116054, 0.0137886, 0.0187342" \ ); } fall_power (passive_POWER_7x1ds1) { index_1 ("0.0186, 0.0966, 0.174, 0.3294, 0.6408, 1.263, 2.5074"); values ( \ - "0.0106875, 0.0103607, 0.0104306, 0.0107458, 0.0116358, 0.0139055, 0.0189706" \ + "0.0106987, 0.0103653, 0.01043, 0.0107458, 0.011636, 0.0139066, 0.0189709" \ ); } } @@ -10387,13 +10405,13 @@ library (sg13g2_stdcell_typ_1p20V_25C) { rise_power (passive_POWER_7x1ds1) { index_1 ("0.0186, 0.0966, 0.174, 0.3294, 0.6408, 1.263, 2.5074"); values ( \ - "0.011608, 0.0112284, 0.0112301, 0.0114901, 0.0123768, 0.0145731, 0.0195092" \ + "0.0115992, 0.0112382, 0.0112285, 0.0114863, 0.0123799, 0.0145747, 0.0195092" \ ); } fall_power (passive_POWER_7x1ds1) { index_1 ("0.0186, 0.0966, 0.174, 0.3294, 0.6408, 1.263, 2.5074"); values ( \ - "0.0107003, 0.0103639, 0.0104245, 0.0107389, 0.0116515, 0.013894, 0.0189669" \ + "0.0106899, 0.0103729, 0.0104247, 0.0107393, 0.0116519, 0.0138944, 0.0189676" \ ); } } @@ -10401,13 +10419,13 @@ library (sg13g2_stdcell_typ_1p20V_25C) { rise_power (passive_POWER_7x1ds1) { index_1 ("0.0186, 0.0966, 0.174, 0.3294, 0.6408, 1.263, 2.5074"); values ( \ - "0.0110468, 0.0106605, 0.0106869, 0.010912, 0.0118401, 0.0140235, 0.0189921" \ + "0.0110356, 0.0106749, 0.0106884, 0.0109122, 0.0118398, 0.0140243, 0.0189927" \ ); } fall_power (passive_POWER_7x1ds1) { index_1 ("0.0186, 0.0966, 0.174, 0.3294, 0.6408, 1.263, 2.5074"); values ( \ - "0.0206634, 0.0203175, 0.0203514, 0.020658, 0.0214932, 0.0237723, 0.0291294" \ + "0.0206859, 0.020313, 0.02035, 0.0206571, 0.0214941, 0.0237711, 0.0291293" \ ); } } @@ -10416,13 +10434,14 @@ library (sg13g2_stdcell_typ_1p20V_25C) { direction : "input"; nextstate_type : "data"; max_transition : 2.5074; - capacitance : 0.00141962; + capacitance : 0.00141954; rise_capacitance : 0.00140953; - rise_capacitance_range (0.00140953, 0.00140953); - fall_capacitance : 0.00142972; - fall_capacitance_range (0.00142972, 0.00142972); + rise_capacitance_range (0.00133328, 0.0016042); + fall_capacitance : 0.00142955; + fall_capacitance_range (0.00142955, 0.00178052); timing () { related_pin : "CLK"; + sdf_edges : both_edges; timing_type : hold_rising; rise_constraint (CONSTRAINT_4x4) { index_1 ("0.0186, 0.51636, 1.263, 2.5074"); @@ -10447,6 +10466,7 @@ library (sg13g2_stdcell_typ_1p20V_25C) { } timing () { related_pin : "CLK"; + sdf_edges : both_edges; timing_type : setup_rising; rise_constraint (CONSTRAINT_4x4) { index_1 ("0.0186, 0.51636, 1.263, 2.5074"); @@ -10455,7 +10475,7 @@ library (sg13g2_stdcell_typ_1p20V_25C) { "0.112479, 0.0401797, 0.00157274, -0.036949", \ "0.274294, 0.185892, 0.140643, 0.0983663", \ "0.394481, 0.299922, 0.24825, 0.199281", \ - "0.517258, 0.412948, 0.357235, 0.30696" \ + "0.517258, 0.412948, 0.36006, 0.30696" \ ); } fall_constraint (CONSTRAINT_4x4) { @@ -10474,13 +10494,13 @@ library (sg13g2_stdcell_typ_1p20V_25C) { rise_power (passive_POWER_7x1ds1) { index_1 ("0.0186, 0.0966, 0.174, 0.3294, 0.6408, 1.263, 2.5074"); values ( \ - "0.00152008, 0.001424, 0.00146213, 0.00159706, 0.00194629, 0.00280155, 0.00467169" \ + "0.00152046, 0.00142316, 0.00146151, 0.00160188, 0.00194679, 0.00280133, 0.00467108" \ ); } fall_power (passive_POWER_7x1ds1) { index_1 ("0.0186, 0.0966, 0.174, 0.3294, 0.6408, 1.263, 2.5074"); values ( \ - "0.0010919, 0.00100228, 0.00105223, 0.00120097, 0.00157983, 0.00247517, 0.00441178" \ + "0.00114937, 0.00106175, 0.00111188, 0.00126, 0.00163909, 0.00253447, 0.004471" \ ); } } @@ -10489,13 +10509,13 @@ library (sg13g2_stdcell_typ_1p20V_25C) { rise_power (passive_POWER_7x1ds1) { index_1 ("0.0186, 0.0966, 0.174, 0.3294, 0.6408, 1.263, 2.5074"); values ( \ - "0.0117996, 0.011726, 0.0117661, 0.0118303, 0.0121135, 0.0129551, 0.0149154" \ + "0.0117994, 0.011727, 0.011762, 0.0118292, 0.0121156, 0.0129554, 0.0149151" \ ); } fall_power (passive_POWER_7x1ds1) { index_1 ("0.0186, 0.0966, 0.174, 0.3294, 0.6408, 1.263, 2.5074"); values ( \ - "0.00878458, 0.00867461, 0.00866726, 0.00877813, 0.00915311, 0.010106, 0.0122204" \ + "0.00878114, 0.00867533, 0.00867643, 0.00877689, 0.00915336, 0.0101063, 0.0122206" \ ); } } @@ -10504,13 +10524,13 @@ library (sg13g2_stdcell_typ_1p20V_25C) { rise_power (passive_POWER_7x1ds1) { index_1 ("0.0186, 0.0966, 0.174, 0.3294, 0.6408, 1.263, 2.5074"); values ( \ - "-2.75561e-05, -2.77647e-05, -2.6573e-05, -2.69577e-05, -2.47205e-05, -2.48764e-05, -2.40266e-05" \ + "-2.71678e-05, -2.79567e-05, -2.74915e-05, -2.53384e-05, -2.39678e-05, -2.53262e-05, -2.41497e-05" \ ); } fall_power (passive_POWER_7x1ds1) { index_1 ("0.0186, 0.0966, 0.174, 0.3294, 0.6408, 1.263, 2.5074"); values ( \ - "0.000254596, 0.000261383, 0.000261723, 0.00026179, 0.000262474, 0.000263248, 0.000263361" \ + "0.000254292, 0.000261565, 0.000261569, 0.000261781, 0.000262528, 0.00026322, 0.000263367" \ ); } } @@ -10518,13 +10538,13 @@ library (sg13g2_stdcell_typ_1p20V_25C) { rise_power (passive_POWER_7x1ds1) { index_1 ("0.0186, 0.0966, 0.174, 0.3294, 0.6408, 1.263, 2.5074"); values ( \ - "0.00152008, 0.001424, 0.00146213, 0.00159706, 0.00194629, 0.00280155, 0.00467169" \ + "0.00152046, 0.00142316, 0.00146151, 0.00160188, 0.00194679, 0.00280133, 0.00467108" \ ); } fall_power (passive_POWER_7x1ds1) { index_1 ("0.0186, 0.0966, 0.174, 0.3294, 0.6408, 1.263, 2.5074"); values ( \ - "0.0010919, 0.00100228, 0.00105223, 0.00120097, 0.00157983, 0.00247517, 0.00441178" \ + "0.00114937, 0.00106175, 0.00111188, 0.00126, 0.00163909, 0.00253447, 0.004471" \ ); } } @@ -10532,20 +10552,21 @@ library (sg13g2_stdcell_typ_1p20V_25C) { pin (RESET_B) { direction : "input"; max_transition : 2.5074; - capacitance : 0.00508666; - rise_capacitance : 0.00509659; - rise_capacitance_range (0.00509659, 0.00509659); - fall_capacitance : 0.00507838; - fall_capacitance_range (0.00507838, 0.00507838); + capacitance : 0.00508684; + rise_capacitance : 0.00509668; + rise_capacitance_range (0.00448162, 0.0060048); + fall_capacitance : 0.00507863; + fall_capacitance_range (0.00472812, 0.00525355); timing () { related_pin : "CLK"; + sdf_edges : both_edges; timing_type : recovery_rising; rise_constraint (CONSTRAINT_4x4) { index_1 ("0.0186, 0.51636, 1.263, 2.5074"); index_2 ("0.0186, 0.51636, 1.263, 2.5074"); values ( \ "0.119814, 0.050163, 0.0118599, -0.0288539", \ - "0.271798, 0.190985, 0.14851, 0.109362", \ + "0.274294, 0.190985, 0.14851, 0.109362", \ "0.40734, 0.315657, 0.269836, 0.22753", \ "0.565828, 0.470677, 0.422209, 0.374845" \ ); @@ -10553,6 +10574,7 @@ library (sg13g2_stdcell_typ_1p20V_25C) { } timing () { related_pin : "CLK"; + sdf_edges : both_edges; timing_type : removal_rising; rise_constraint (CONSTRAINT_4x4) { index_1 ("0.0186, 0.51636, 1.263, 2.5074"); @@ -10561,7 +10583,7 @@ library (sg13g2_stdcell_typ_1p20V_25C) { "-0.100253, -0.0376839, -0.00157274, 0.036949", \ "-0.249336, -0.178252, -0.140643, -0.101115", \ "-0.373907, -0.2973, -0.256345, -0.21623", \ - "-0.522655, -0.445936, -0.405259, -0.360088" \ + "-0.522655, -0.445936, -0.405259, -0.363039" \ ); } } @@ -10580,13 +10602,13 @@ library (sg13g2_stdcell_typ_1p20V_25C) { rise_power (passive_POWER_7x1ds1) { index_1 ("0.0186, 0.0966, 0.174, 0.3294, 0.6408, 1.263, 2.5074"); values ( \ - "0.00370985, 0.00361514, 0.00360261, 0.00363157, 0.00379188, 0.00438227, 0.00598734" \ + "0.00371796, 0.0036166, 0.00360303, 0.0036384, 0.00379121, 0.00438142, 0.00598705" \ ); } fall_power (passive_POWER_7x1ds1) { index_1 ("0.0186, 0.0966, 0.174, 0.3294, 0.6408, 1.263, 2.5074"); values ( \ - "0.025598, 0.0250573, 0.0249698, 0.0250792, 0.0258851, 0.0281573, 0.0332902" \ + "0.0256007, 0.0250538, 0.0249665, 0.0250789, 0.0258853, 0.0281576, 0.0332885" \ ); } } @@ -10595,13 +10617,13 @@ library (sg13g2_stdcell_typ_1p20V_25C) { rise_power (passive_POWER_7x1ds1) { index_1 ("0.0186, 0.0966, 0.174, 0.3294, 0.6408, 1.263, 2.5074"); values ( \ - "0.00116948, 0.00116326, 0.00116608, 0.00116928, 0.00116938, 0.00116271, 0.00116402" \ + "0.00116874, 0.00116261, 0.00116704, 0.00116909, 0.00117006, 0.00116388, 0.00116429" \ ); } fall_power (passive_POWER_7x1ds1) { index_1 ("0.0186, 0.0966, 0.174, 0.3294, 0.6408, 1.263, 2.5074"); values ( \ - "-0.000718663, -0.000844352, -0.000876679, -0.000902541, -0.00092754, -0.000946335, -0.000965718" \ + "-0.000718324, -0.000844419, -0.000878158, -0.000902381, -0.000927749, -0.000947448, -0.000965843" \ ); } } @@ -10610,13 +10632,13 @@ library (sg13g2_stdcell_typ_1p20V_25C) { rise_power (passive_POWER_7x1ds1) { index_1 ("0.0186, 0.0966, 0.174, 0.3294, 0.6408, 1.263, 2.5074"); values ( \ - "0.014153, 0.0139645, 0.0139417, 0.0139227, 0.0141179, 0.0149697, 0.0172622" \ + "0.0141331, 0.0139633, 0.0139418, 0.0139218, 0.0141162, 0.0149696, 0.0172626" \ ); } fall_power (passive_POWER_7x1ds1) { index_1 ("0.0186, 0.0966, 0.174, 0.3294, 0.6408, 1.263, 2.5074"); values ( \ - "0.00908956, 0.00871981, 0.00864339, 0.00856745, 0.00888554, 0.00991272, 0.01254" \ + "0.00908895, 0.00872491, 0.00864809, 0.00856565, 0.00888451, 0.00991101, 0.0125374" \ ); } } @@ -10625,13 +10647,13 @@ library (sg13g2_stdcell_typ_1p20V_25C) { rise_power (passive_POWER_7x1ds1) { index_1 ("0.0186, 0.0966, 0.174, 0.3294, 0.6408, 1.263, 2.5074"); values ( \ - "0.00127538, 0.00126836, 0.00126868, 0.00127045, 0.00127649, 0.00126978, 0.00126876" \ + "0.00127542, 0.00126836, 0.00126885, 0.00127017, 0.00127529, 0.0012692, 0.00126547" \ ); } fall_power (passive_POWER_7x1ds1) { index_1 ("0.0186, 0.0966, 0.174, 0.3294, 0.6408, 1.263, 2.5074"); values ( \ - "-0.000865952, -0.000944256, -0.000966089, -0.000982485, -0.000998778, -0.00101042, -0.00102362" \ + "-0.000864978, -0.000944072, -0.000966557, -0.000982798, -0.000998994, -0.00101096, -0.00102376" \ ); } } @@ -10639,19 +10661,19 @@ library (sg13g2_stdcell_typ_1p20V_25C) { rise_power (passive_POWER_7x1ds1) { index_1 ("0.0186, 0.0966, 0.174, 0.3294, 0.6408, 1.263, 2.5074"); values ( \ - "0.00370985, 0.00361514, 0.00360261, 0.00363157, 0.00379188, 0.00438227, 0.00598734" \ + "0.00371796, 0.0036166, 0.00360303, 0.0036384, 0.00379121, 0.00438142, 0.00598705" \ ); } fall_power (passive_POWER_7x1ds1) { index_1 ("0.0186, 0.0966, 0.174, 0.3294, 0.6408, 1.263, 2.5074"); values ( \ - "0.00908956, 0.00871981, 0.00864339, 0.00856745, 0.00888554, 0.00991272, 0.01254" \ + "0.00908895, 0.00872491, 0.00864809, 0.00856565, 0.00888451, 0.00991101, 0.0125374" \ ); } } } ff (IQ,IQN) { - clear : "RESET_B'"; + clear : "!RESET_B"; clocked_on : "CLK"; next_state : "D"; } @@ -10669,7 +10691,7 @@ library (sg13g2_stdcell_typ_1p20V_25C) { when : "!CLK&D&!RESET_B&!Q"; } leakage_power () { - value : 519.836; + value : 519.834; when : "CLK&!D&!RESET_B&!Q"; } leakage_power () { @@ -10677,7 +10699,7 @@ library (sg13g2_stdcell_typ_1p20V_25C) { when : "CLK&D&!RESET_B&!Q"; } leakage_power () { - value : 604.261; + value : 604.262; when : "!CLK&!D&RESET_B&Q"; } leakage_power () { @@ -10689,19 +10711,19 @@ library (sg13g2_stdcell_typ_1p20V_25C) { when : "!CLK&D&RESET_B&Q"; } leakage_power () { - value : 670.322; + value : 670.323; when : "!CLK&D&RESET_B&!Q"; } leakage_power () { - value : 590.728; + value : 590.727; when : "CLK&!D&RESET_B&Q"; } leakage_power () { - value : 555.085; + value : 555.083; when : "CLK&!D&RESET_B&!Q"; } leakage_power () { - value : 601.25; + value : 601.249; when : "CLK&D&RESET_B&Q"; } leakage_power () { @@ -10715,14 +10737,15 @@ library (sg13g2_stdcell_typ_1p20V_25C) { max_capacitance : 0.6; timing () { related_pin : "CLK"; + sdf_edges : start_edge; timing_sense : non_unate; timing_type : rising_edge; cell_rise (TIMING_DELAY_7x7ds1) { index_1 ("0.0186, 0.0966, 0.174, 0.3294, 0.6408, 1.263, 2.5074"); index_2 ("0.001, 0.0468, 0.078, 0.1296, 0.216, 0.36, 0.6"); values ( \ - "0.167479, 0.239245, 0.282804, 0.354412, 0.474129, 0.673521, 1.006", \ - "0.205028, 0.276785, 0.320311, 0.392013, 0.511729, 0.711206, 1.04357", \ + "0.167509, 0.239244, 0.282804, 0.354412, 0.474129, 0.673521, 1.006", \ + "0.205028, 0.276785, 0.320311, 0.392012, 0.511729, 0.711206, 1.04357", \ "0.230715, 0.302456, 0.345941, 0.417511, 0.537241, 0.736556, 1.0695", \ "0.269105, 0.340814, 0.384362, 0.455974, 0.575667, 0.774967, 1.10725", \ "0.3243, 0.396061, 0.439583, 0.511148, 0.630938, 0.830225, 1.16242", \ @@ -10734,20 +10757,20 @@ library (sg13g2_stdcell_typ_1p20V_25C) { index_1 ("0.0186, 0.0966, 0.174, 0.3294, 0.6408, 1.263, 2.5074"); index_2 ("0.001, 0.0468, 0.078, 0.1296, 0.216, 0.36, 0.6"); values ( \ - "0.0190908, 0.104344, 0.166614, 0.270117, 0.443847, 0.733494, 1.21649", \ - "0.0191307, 0.104345, 0.166615, 0.270571, 0.444094, 0.733865, 1.21651", \ - "0.0191458, 0.104346, 0.166616, 0.270572, 0.444095, 0.733866, 1.21694", \ - "0.0191834, 0.104347, 0.166617, 0.270573, 0.444096, 0.733867, 1.22149", \ - "0.0193765, 0.104374, 0.166618, 0.270574, 0.444097, 0.733868, 1.2215", \ - "0.019906, 0.104444, 0.166619, 0.270575, 0.444098, 0.733869, 1.22151", \ - "0.020967, 0.104611, 0.166651, 0.270576, 0.444099, 0.73387, 1.22152" \ + "0.0191252, 0.104344, 0.16661, 0.270117, 0.443846, 0.733494, 1.21649", \ + "0.0191307, 0.104345, 0.166611, 0.270519, 0.44409, 0.733865, 1.21651", \ + "0.0191458, 0.104346, 0.166612, 0.27052, 0.444091, 0.733866, 1.21694", \ + "0.0191834, 0.104347, 0.166613, 0.270521, 0.444092, 0.733867, 1.22149", \ + "0.0193765, 0.104374, 0.166614, 0.270522, 0.444093, 0.733868, 1.2215", \ + "0.019906, 0.104444, 0.166615, 0.270523, 0.444094, 0.733869, 1.22151", \ + "0.020967, 0.104611, 0.166651, 0.270524, 0.444095, 0.73387, 1.22152" \ ); } cell_fall (TIMING_DELAY_7x7ds1) { index_1 ("0.0186, 0.0966, 0.174, 0.3294, 0.6408, 1.263, 2.5074"); index_2 ("0.001, 0.0468, 0.078, 0.1296, 0.216, 0.36, 0.6"); values ( \ - "0.166796, 0.229169, 0.264228, 0.321604, 0.417295, 0.576601, 0.841756", \ + "0.166772, 0.229169, 0.264228, 0.321604, 0.417295, 0.576601, 0.841756", \ "0.204373, 0.266674, 0.301771, 0.359087, 0.454836, 0.614001, 0.879566", \ "0.229688, 0.291984, 0.327085, 0.384473, 0.480137, 0.639458, 0.904642", \ "0.266348, 0.328652, 0.363775, 0.42114, 0.516847, 0.676008, 0.941281", \ @@ -10760,30 +10783,31 @@ library (sg13g2_stdcell_typ_1p20V_25C) { index_1 ("0.0186, 0.0966, 0.174, 0.3294, 0.6408, 1.263, 2.5074"); index_2 ("0.001, 0.0468, 0.078, 0.1296, 0.216, 0.36, 0.6"); values ( \ - "0.0172998, 0.0823084, 0.128097, 0.204982, 0.334434, 0.550448, 0.910477", \ - "0.0173008, 0.0823094, 0.128098, 0.204983, 0.334986, 0.550458, 0.910702", \ - "0.0173018, 0.0823104, 0.128102, 0.204995, 0.334987, 0.550459, 0.91073", \ - "0.0173028, 0.0823253, 0.128148, 0.204996, 0.334988, 0.55046, 0.910731", \ - "0.0173038, 0.0823263, 0.128149, 0.204997, 0.334989, 0.550461, 0.910732", \ - "0.0173048, 0.0823273, 0.12815, 0.205089, 0.33499, 0.550594, 0.910733", \ - "0.0173058, 0.0823283, 0.128151, 0.20509, 0.334991, 0.550595, 0.910734" \ + "0.0172843, 0.0823084, 0.128097, 0.204982, 0.334434, 0.550448, 0.910477", \ + "0.0172847, 0.0823094, 0.128098, 0.204983, 0.334986, 0.550458, 0.910702", \ + "0.0172857, 0.0823104, 0.128102, 0.204995, 0.334987, 0.550459, 0.91073", \ + "0.0172867, 0.0823253, 0.128148, 0.204996, 0.334988, 0.55046, 0.910731", \ + "0.0172962, 0.0823263, 0.128149, 0.204997, 0.334989, 0.550461, 0.910732", \ + "0.0172972, 0.0823273, 0.12815, 0.205089, 0.33499, 0.550594, 0.910733", \ + "0.0172982, 0.0823283, 0.128151, 0.20509, 0.334991, 0.550595, 0.910734" \ ); } } timing () { related_pin : "RESET_B"; + sdf_edges : start_edge; timing_sense : positive_unate; timing_type : clear; cell_fall (TIMING_DELAY_7x7ds1) { index_1 ("0.0186, 0.0966, 0.174, 0.3294, 0.6408, 1.263, 2.5074"); index_2 ("0.001, 0.0468, 0.078, 0.1296, 0.216, 0.36, 0.6"); values ( \ - "0.232746, 0.294709, 0.329868, 0.387245, 0.483044, 0.642364, 0.907657", \ - "0.275818, 0.33786, 0.372978, 0.430409, 0.526158, 0.68551, 0.95089", \ + "0.232746, 0.29471, 0.329834, 0.387246, 0.483072, 0.642386, 0.907657", \ + "0.275818, 0.337861, 0.372978, 0.430409, 0.526158, 0.685506, 0.95089", \ "0.311189, 0.373147, 0.408282, 0.465736, 0.561567, 0.720861, 0.986472", \ "0.369399, 0.431359, 0.466527, 0.523919, 0.619652, 0.779034, 1.04431", \ "0.457974, 0.520004, 0.555107, 0.612546, 0.708325, 0.867564, 1.13281", \ - "0.580413, 0.642492, 0.677633, 0.735117, 0.830976, 0.990209, 1.2554", \ + "0.58038, 0.642491, 0.677633, 0.735117, 0.830976, 0.990209, 1.2554", \ "0.745616, 0.807842, 0.843019, 0.900406, 0.996179, 1.15557, 1.42082" \ ); } @@ -10791,13 +10815,13 @@ library (sg13g2_stdcell_typ_1p20V_25C) { index_1 ("0.0186, 0.0966, 0.174, 0.3294, 0.6408, 1.263, 2.5074"); index_2 ("0.001, 0.0468, 0.078, 0.1296, 0.216, 0.36, 0.6"); values ( \ - "0.0170219, 0.0822013, 0.128003, 0.204959, 0.334516, 0.550449, 0.910588", \ - "0.0170412, 0.0822258, 0.128004, 0.205194, 0.334517, 0.550456, 0.910589", \ - "0.0170518, 0.0822268, 0.128072, 0.205195, 0.334518, 0.550649, 0.91092", \ - "0.017063, 0.0822278, 0.128097, 0.205196, 0.334519, 0.55065, 0.913728", \ - "0.017171, 0.0822288, 0.128098, 0.205197, 0.33452, 0.550651, 0.913729", \ - "0.017281, 0.08225, 0.128099, 0.205198, 0.334521, 0.550689, 0.91373", \ - "0.01751, 0.082325, 0.1281, 0.205199, 0.334522, 0.55069, 0.913731" \ + "0.0170218, 0.0822016, 0.128013, 0.204959, 0.334415, 0.550448, 0.910588", \ + "0.0170412, 0.0822133, 0.128014, 0.205194, 0.334428, 0.550456, 0.910589", \ + "0.0170518, 0.0822187, 0.128072, 0.205195, 0.334429, 0.550649, 0.91092", \ + "0.017063, 0.0822197, 0.128097, 0.205196, 0.33443, 0.55065, 0.913728", \ + "0.017171, 0.0822207, 0.128098, 0.205197, 0.334431, 0.550651, 0.913729", \ + "0.017248, 0.082251, 0.128099, 0.205198, 0.334432, 0.550689, 0.91373", \ + "0.01751, 0.082325, 0.1281, 0.205199, 0.334454, 0.55069, 0.913731" \ ); } } @@ -10807,25 +10831,25 @@ library (sg13g2_stdcell_typ_1p20V_25C) { index_1 ("0.0186, 0.0966, 0.174, 0.3294, 0.6408, 1.263, 2.5074"); index_2 ("0.001, 0.0468, 0.078, 0.1296, 0.216, 0.36, 0.6"); values ( \ - "0.0283831, 0.0292367, 0.0293014, 0.0292654, 0.0290824, 0.0286616, 0.0286139", \ - "0.0279207, 0.0288607, 0.0288469, 0.0288288, 0.0286552, 0.0282044, 0.0283356", \ - "0.0279026, 0.028685, 0.0287968, 0.0289913, 0.0286103, 0.0281359, 0.02819", \ + "0.0283876, 0.0292367, 0.0293117, 0.0292654, 0.0290801, 0.0286616, 0.0286139", \ + "0.0279207, 0.0288607, 0.028852, 0.0288225, 0.0286539, 0.0282044, 0.0283356", \ + "0.0279026, 0.028685, 0.0287968, 0.0289917, 0.0286103, 0.0281359, 0.02819", \ "0.0280616, 0.0289112, 0.0289962, 0.0289109, 0.029035, 0.028323, 0.0292648", \ "0.0289339, 0.0297758, 0.0298299, 0.0299994, 0.0297498, 0.0296855, 0.0292282", \ - "0.0311886, 0.0319311, 0.0321268, 0.0321947, 0.0322414, 0.0320868, 0.0313183", \ - "0.0362927, 0.0369734, 0.03718, 0.037093, 0.0372682, 0.0373146, 0.0372565" \ + "0.0311886, 0.0319311, 0.0321268, 0.0321947, 0.0322415, 0.0320868, 0.0313183", \ + "0.0362927, 0.0369734, 0.0371801, 0.037093, 0.0372682, 0.0373146, 0.0372565" \ ); } fall_power (POWER_7x7ds1) { index_1 ("0.0186, 0.0966, 0.174, 0.3294, 0.6408, 1.263, 2.5074"); index_2 ("0.001, 0.0468, 0.078, 0.1296, 0.216, 0.36, 0.6"); values ( \ - "0.0290546, 0.030112, 0.0301471, 0.0301231, 0.02995, 0.0295534, 0.0288343", \ + "0.0290475, 0.030112, 0.0301471, 0.0301231, 0.02995, 0.0295534, 0.0288343", \ "0.0287352, 0.0297973, 0.0300718, 0.0298297, 0.0297208, 0.0291714, 0.0285527", \ "0.0288905, 0.0298886, 0.0299293, 0.0300463, 0.0298356, 0.0293679, 0.0287319", \ "0.0292227, 0.0303289, 0.0303957, 0.030279, 0.0300886, 0.0308324, 0.0290493", \ "0.0302083, 0.0312352, 0.0314092, 0.0314188, 0.0314565, 0.0308853, 0.0313393", \ - "0.0326036, 0.0336182, 0.0337135, 0.0339082, 0.0339118, 0.0339705, 0.0332991", \ + "0.0326036, 0.0336182, 0.0337133, 0.0339082, 0.0339118, 0.0339705, 0.0332991", \ "0.0376556, 0.0386692, 0.0387459, 0.0388547, 0.0386067, 0.0387751, 0.0388249" \ ); } @@ -10841,13 +10865,13 @@ library (sg13g2_stdcell_typ_1p20V_25C) { index_1 ("0.0186, 0.0966, 0.174, 0.3294, 0.6408, 1.263, 2.5074"); index_2 ("0.001, 0.0468, 0.078, 0.1296, 0.216, 0.36, 0.6"); values ( \ - "0.0193548, 0.0202956, 0.0203576, 0.0203019, 0.0201931, 0.0197732, 0.0190702", \ - "0.0191796, 0.020182, 0.0201778, 0.0201974, 0.0199911, 0.019698, 0.0190455", \ - "0.019129, 0.0200599, 0.020188, 0.0202721, 0.0200568, 0.0196734, 0.0190307", \ + "0.0193548, 0.0202954, 0.0203207, 0.0202959, 0.0201714, 0.019781, 0.0190702", \ + "0.0191796, 0.0202674, 0.0201778, 0.0201974, 0.0199911, 0.0196955, 0.0190455", \ + "0.019129, 0.0200599, 0.020188, 0.0202721, 0.0200568, 0.0196733, 0.0190306", \ "0.0193114, 0.0202426, 0.0203199, 0.0202446, 0.0203472, 0.0200682, 0.019877", \ - "0.0197779, 0.0207669, 0.0208739, 0.0209149, 0.0207926, 0.0201793, 0.0216196", \ - "0.0211656, 0.0220367, 0.0221883, 0.0221982, 0.0222778, 0.0223695, 0.0209097", \ - "0.0233385, 0.0241842, 0.0243333, 0.0242073, 0.0242663, 0.0243135, 0.0241746" \ + "0.0197779, 0.0207669, 0.0208739, 0.0209148, 0.0207926, 0.0201793, 0.0216197", \ + "0.0211537, 0.0220366, 0.0221882, 0.0221979, 0.0222779, 0.022369, 0.0208759", \ + "0.0233386, 0.0241842, 0.0243335, 0.0242073, 0.0242673, 0.0243129, 0.024331" \ ); } } @@ -10858,9 +10882,9 @@ library (sg13g2_stdcell_typ_1p20V_25C) { max_transition : 2.5074; capacitance : 0.00277906; rise_capacitance : 0.00297907; - rise_capacitance_range (0.00297907, 0.00297907); + rise_capacitance_range (0.0027291, 0.00317824); fall_capacitance : 0.00254571; - fall_capacitance_range (0.00254571, 0.00254571); + fall_capacitance_range (0.00254571, 0.0030845); timing () { related_pin : "CLK"; timing_type : min_pulse_width; @@ -10888,7 +10912,7 @@ library (sg13g2_stdcell_typ_1p20V_25C) { fall_power (passive_POWER_7x1ds1) { index_1 ("0.0186, 0.0966, 0.174, 0.3294, 0.6408, 1.263, 2.5074"); values ( \ - "0.0215328, 0.0211821, 0.0212031, 0.021533, 0.0223594, 0.0246495, 0.0299711" \ + "0.0215306, 0.0211821, 0.0212031, 0.021533, 0.0223594, 0.0246495, 0.0299711" \ ); } } @@ -10902,7 +10926,7 @@ library (sg13g2_stdcell_typ_1p20V_25C) { fall_power (passive_POWER_7x1ds1) { index_1 ("0.0186, 0.0966, 0.174, 0.3294, 0.6408, 1.263, 2.5074"); values ( \ - "0.0206985, 0.0203178, 0.0203485, 0.0206652, 0.0214993, 0.0237153, 0.0291278" \ + "0.0206983, 0.0203178, 0.0203485, 0.0206652, 0.0214993, 0.0237153, 0.0291278" \ ); } } @@ -10931,7 +10955,7 @@ library (sg13g2_stdcell_typ_1p20V_25C) { fall_power (passive_POWER_7x1ds1) { index_1 ("0.0186, 0.0966, 0.174, 0.3294, 0.6408, 1.263, 2.5074"); values ( \ - "0.0386047, 0.0387911, 0.0385427, 0.0387249, 0.039655, 0.0419112, 0.0469715" \ + "0.0386121, 0.0387911, 0.0385427, 0.0387249, 0.039655, 0.0419112, 0.0469715" \ ); } } @@ -10946,7 +10970,7 @@ library (sg13g2_stdcell_typ_1p20V_25C) { fall_power (passive_POWER_7x1ds1) { index_1 ("0.0186, 0.0966, 0.174, 0.3294, 0.6408, 1.263, 2.5074"); values ( \ - "0.0107281, 0.0103987, 0.0105001, 0.0107769, 0.0116915, 0.0139362, 0.0190038" \ + "0.0107273, 0.0103987, 0.0105001, 0.0107769, 0.0116915, 0.0139362, 0.0190038" \ ); } } @@ -10955,13 +10979,13 @@ library (sg13g2_stdcell_typ_1p20V_25C) { rise_power (passive_POWER_7x1ds1) { index_1 ("0.0186, 0.0966, 0.174, 0.3294, 0.6408, 1.263, 2.5074"); values ( \ - "0.0116638, 0.0113025, 0.0112952, 0.0115549, 0.012437, 0.0146334, 0.0195668" \ + "0.0116639, 0.0113025, 0.0112952, 0.0115549, 0.012437, 0.0146337, 0.0195668" \ ); } fall_power (passive_POWER_7x1ds1) { index_1 ("0.0186, 0.0966, 0.174, 0.3294, 0.6408, 1.263, 2.5074"); values ( \ - "0.0107318, 0.0103914, 0.0104996, 0.010771, 0.0116815, 0.0139237, 0.018997" \ + "0.0107331, 0.0103914, 0.0104996, 0.0107709, 0.0116815, 0.0139237, 0.0189969" \ ); } } @@ -10975,7 +10999,7 @@ library (sg13g2_stdcell_typ_1p20V_25C) { fall_power (passive_POWER_7x1ds1) { index_1 ("0.0186, 0.0966, 0.174, 0.3294, 0.6408, 1.263, 2.5074"); values ( \ - "0.0206985, 0.0203178, 0.0203485, 0.0206652, 0.0214993, 0.0237153, 0.0291278" \ + "0.0206983, 0.0203178, 0.0203485, 0.0206652, 0.0214993, 0.0237153, 0.0291278" \ ); } } @@ -10986,17 +11010,18 @@ library (sg13g2_stdcell_typ_1p20V_25C) { max_transition : 2.5074; capacitance : 0.00142328; rise_capacitance : 0.00141333; - rise_capacitance_range (0.00141333, 0.00141333); + rise_capacitance_range (0.00133779, 0.00160769); fall_capacitance : 0.00143324; - fall_capacitance_range (0.00143324, 0.00143324); + fall_capacitance_range (0.00143324, 0.00178386); timing () { related_pin : "CLK"; + sdf_edges : both_edges; timing_type : hold_rising; rise_constraint (CONSTRAINT_4x4) { index_1 ("0.0186, 0.51636, 1.263, 2.5074"); index_2 ("0.0186, 0.51636, 1.263, 2.5074"); values ( \ - "-0.0611298, -0.00773397, 0.024145, 0.0612343", \ + "-0.0611298, -0.00773397, 0.0267168, 0.0612343", \ "-0.196924, -0.142602, -0.106552, -0.0681273", \ "-0.283895, -0.239607, -0.202377, -0.162556", \ "-0.360753, -0.330478, -0.303561, -0.259735" \ @@ -11009,12 +11034,13 @@ library (sg13g2_stdcell_typ_1p20V_25C) { "-0.0342327, 0.0696366, 0.134731, 0.212343", \ "-0.194428, -0.094219, -0.0252571, 0.0555777", \ "-0.307041, -0.229117, -0.161902, -0.0834575", \ - "-0.422815, -0.368964, -0.312036, -0.236123" \ + "-0.422815, -0.366215, -0.312036, -0.236123" \ ); } } timing () { related_pin : "CLK"; + sdf_edges : both_edges; timing_type : setup_rising; rise_constraint (CONSTRAINT_4x4) { index_1 ("0.0186, 0.51636, 1.263, 2.5074"); @@ -11042,13 +11068,13 @@ library (sg13g2_stdcell_typ_1p20V_25C) { rise_power (passive_POWER_7x1ds1) { index_1 ("0.0186, 0.0966, 0.174, 0.3294, 0.6408, 1.263, 2.5074"); values ( \ - "0.00152526, 0.00142523, 0.00146474, 0.00160144, 0.00195077, 0.00280371, 0.00467231" \ + "0.0015253, 0.00142523, 0.00146474, 0.00160144, 0.00195077, 0.00280372, 0.00467231" \ ); } fall_power (passive_POWER_7x1ds1) { index_1 ("0.0186, 0.0966, 0.174, 0.3294, 0.6408, 1.263, 2.5074"); values ( \ - "0.00115934, 0.00107029, 0.00111876, 0.00127164, 0.00165344, 0.00254307, 0.0044787" \ + "0.00115937, 0.0010703, 0.00111877, 0.00127165, 0.00165345, 0.00254307, 0.00447871" \ ); } } @@ -11057,13 +11083,13 @@ library (sg13g2_stdcell_typ_1p20V_25C) { rise_power (passive_POWER_7x1ds1) { index_1 ("0.0186, 0.0966, 0.174, 0.3294, 0.6408, 1.263, 2.5074"); values ( \ - "0.0117811, 0.0117134, 0.0117379, 0.0118086, 0.0120949, 0.0129389, 0.0148981" \ + "0.0117814, 0.0117134, 0.0117379, 0.0118086, 0.0120949, 0.0129389, 0.0148981" \ ); } fall_power (passive_POWER_7x1ds1) { index_1 ("0.0186, 0.0966, 0.174, 0.3294, 0.6408, 1.263, 2.5074"); values ( \ - "0.00879318, 0.0086873, 0.00867101, 0.00879798, 0.00916735, 0.0101247, 0.0122381" \ + "0.00879696, 0.0086873, 0.008671, 0.00879797, 0.00916734, 0.0101247, 0.0122381" \ ); } } @@ -11072,13 +11098,13 @@ library (sg13g2_stdcell_typ_1p20V_25C) { rise_power (passive_POWER_7x1ds1) { index_1 ("0.0186, 0.0966, 0.174, 0.3294, 0.6408, 1.263, 2.5074"); values ( \ - "-2.50363e-05, -2.57419e-05, -2.42531e-05, -2.23222e-05, -2.11532e-05, -2.12222e-05, -2.12106e-05" \ + "-2.7039e-05, -2.57536e-05, -2.42543e-05, -2.23234e-05, -2.11544e-05, -2.12228e-05, -2.12084e-05" \ ); } fall_power (passive_POWER_7x1ds1) { index_1 ("0.0186, 0.0966, 0.174, 0.3294, 0.6408, 1.263, 2.5074"); values ( \ - "0.000251991, 0.000258938, 0.000259068, 0.000259031, 0.000259736, 0.000260632, 0.000260395" \ + "0.00025206, 0.000258907, 0.000259066, 0.000259028, 0.000259734, 0.000260629, 0.000260393" \ ); } } @@ -11086,13 +11112,13 @@ library (sg13g2_stdcell_typ_1p20V_25C) { rise_power (passive_POWER_7x1ds1) { index_1 ("0.0186, 0.0966, 0.174, 0.3294, 0.6408, 1.263, 2.5074"); values ( \ - "0.00152526, 0.00142523, 0.00146474, 0.00160144, 0.00195077, 0.00280371, 0.00467231" \ + "0.0015253, 0.00142523, 0.00146474, 0.00160144, 0.00195077, 0.00280372, 0.00467231" \ ); } fall_power (passive_POWER_7x1ds1) { index_1 ("0.0186, 0.0966, 0.174, 0.3294, 0.6408, 1.263, 2.5074"); values ( \ - "0.00115934, 0.00107029, 0.00111876, 0.00127164, 0.00165344, 0.00254307, 0.0044787" \ + "0.00115937, 0.0010703, 0.00111877, 0.00127165, 0.00165345, 0.00254307, 0.00447871" \ ); } } @@ -11102,17 +11128,18 @@ library (sg13g2_stdcell_typ_1p20V_25C) { max_transition : 2.5074; capacitance : 0.00513072; rise_capacitance : 0.00514108; - rise_capacitance_range (0.00514108, 0.00514108); + rise_capacitance_range (0.00451961, 0.00604962); fall_capacitance : 0.00512209; - fall_capacitance_range (0.00512209, 0.00512209); + fall_capacitance_range (0.00476415, 0.00529797); timing () { related_pin : "CLK"; + sdf_edges : both_edges; timing_type : recovery_rising; rise_constraint (CONSTRAINT_4x4) { index_1 ("0.0186, 0.51636, 1.263, 2.5074"); index_2 ("0.0186, 0.51636, 1.263, 2.5074"); values ( \ - "0.119814, 0.0476672, 0.00928808, -0.0288539", \ + "0.119814, 0.0476672, 0.0118599, -0.0288539", \ "0.271798, 0.190985, 0.14851, 0.109362", \ "0.40734, 0.315657, 0.272535, 0.22753", \ "0.56313, 0.470677, 0.422209, 0.374845" \ @@ -11121,6 +11148,7 @@ library (sg13g2_stdcell_typ_1p20V_25C) { } timing () { related_pin : "CLK"; + sdf_edges : both_edges; timing_type : removal_rising; rise_constraint (CONSTRAINT_4x4) { index_1 ("0.0186, 0.51636, 1.263, 2.5074"); @@ -11154,7 +11182,7 @@ library (sg13g2_stdcell_typ_1p20V_25C) { fall_power (passive_POWER_7x1ds1) { index_1 ("0.0186, 0.0966, 0.174, 0.3294, 0.6408, 1.263, 2.5074"); values ( \ - "0.0285932, 0.0280774, 0.0279543, 0.0280672, 0.0288705, 0.0311595, 0.0362675" \ + "0.0285932, 0.0280781, 0.0279543, 0.0280672, 0.0288705, 0.0311595, 0.0362675" \ ); } } @@ -11163,13 +11191,13 @@ library (sg13g2_stdcell_typ_1p20V_25C) { rise_power (passive_POWER_7x1ds1) { index_1 ("0.0186, 0.0966, 0.174, 0.3294, 0.6408, 1.263, 2.5074"); values ( \ - "0.0011979, 0.00119714, 0.0012004, 0.00120273, 0.00120305, 0.00119678, 0.00119631" \ + "0.0011979, 0.001197, 0.0012004, 0.00120273, 0.00120305, 0.00119678, 0.00119631" \ ); } fall_power (passive_POWER_7x1ds1) { index_1 ("0.0186, 0.0966, 0.174, 0.3294, 0.6408, 1.263, 2.5074"); values ( \ - "-0.00075039, -0.000873113, -0.000908141, -0.000933692, -0.000956827, -0.000977091, -0.000996599" \ + "-0.000750387, -0.000873499, -0.000908137, -0.000933687, -0.000956823, -0.000977088, -0.000996595" \ ); } } @@ -11184,7 +11212,7 @@ library (sg13g2_stdcell_typ_1p20V_25C) { fall_power (passive_POWER_7x1ds1) { index_1 ("0.0186, 0.0966, 0.174, 0.3294, 0.6408, 1.263, 2.5074"); values ( \ - "0.00905826, 0.00870989, 0.00863279, 0.00855406, 0.00886713, 0.00989636, 0.0125342" \ + "0.00905828, 0.00870989, 0.00863279, 0.00855406, 0.00886713, 0.00989636, 0.0125341" \ ); } } @@ -11193,13 +11221,13 @@ library (sg13g2_stdcell_typ_1p20V_25C) { rise_power (passive_POWER_7x1ds1) { index_1 ("0.0186, 0.0966, 0.174, 0.3294, 0.6408, 1.263, 2.5074"); values ( \ - "0.00130175, 0.00129878, 0.0013013, 0.00130221, 0.0013071, 0.00130282, 0.00129842" \ + "0.00130174, 0.00129878, 0.0013013, 0.00130221, 0.0013071, 0.00130282, 0.00129842" \ ); } fall_power (passive_POWER_7x1ds1) { index_1 ("0.0186, 0.0966, 0.174, 0.3294, 0.6408, 1.263, 2.5074"); values ( \ - "-0.000899208, -0.000974335, -0.000999481, -0.00101604, -0.00102967, -0.00104232, -0.00105546" \ + "-0.000899192, -0.000974326, -0.000999483, -0.00101604, -0.00102967, -0.00104232, -0.00105547" \ ); } } @@ -11213,20 +11241,20 @@ library (sg13g2_stdcell_typ_1p20V_25C) { fall_power (passive_POWER_7x1ds1) { index_1 ("0.0186, 0.0966, 0.174, 0.3294, 0.6408, 1.263, 2.5074"); values ( \ - "0.00905826, 0.00870989, 0.00863279, 0.00855406, 0.00886713, 0.00989636, 0.0125342" \ + "0.00905828, 0.00870989, 0.00863279, 0.00855406, 0.00886713, 0.00989636, 0.0125341" \ ); } } } ff (IQ,IQN) { - clear : "RESET_B'"; + clear : "!RESET_B"; clocked_on : "CLK"; next_state : "D"; } } cell (sg13g2_dlhq_1) { area : 30.8448; - cell_footprint : "DLHQ"; + cell_footprint : "dlhq"; cell_leakage_power : 368.537; leakage_power () { value : 353.771; @@ -11316,6 +11344,7 @@ library (sg13g2_stdcell_typ_1p20V_25C) { } timing () { related_pin : "GATE"; + sdf_edges : start_edge; timing_sense : non_unate; timing_type : rising_edge; cell_rise (TIMING_DELAY_7x7ds1) { @@ -11435,11 +11464,12 @@ library (sg13g2_stdcell_typ_1p20V_25C) { max_transition : 2.5074; capacitance : 0.00228262; rise_capacitance : 0.00231188; - rise_capacitance_range (0.00231188, 0.00231188); + rise_capacitance_range (0.0020933, 0.00247009); fall_capacitance : 0.00225337; - fall_capacitance_range (0.00225337, 0.00225337); + fall_capacitance_range (0.00205824, 0.00243433); timing () { related_pin : "GATE"; + sdf_edges : both_edges; timing_type : hold_falling; rise_constraint (CONSTRAINT_4x4) { index_1 ("0.0186, 0.51636, 1.263, 2.5074"); @@ -11464,6 +11494,7 @@ library (sg13g2_stdcell_typ_1p20V_25C) { } timing () { related_pin : "GATE"; + sdf_edges : both_edges; timing_type : setup_falling; rise_constraint (CONSTRAINT_4x4) { index_1 ("0.0186, 0.51636, 1.263, 2.5074"); @@ -11537,9 +11568,9 @@ library (sg13g2_stdcell_typ_1p20V_25C) { max_transition : 2.5074; capacitance : 0.00228336; rise_capacitance : 0.00258113; - rise_capacitance_range (0.00258113, 0.00258113); + rise_capacitance_range (0.00232967, 0.00281398); fall_capacitance : 0.00168783; - fall_capacitance_range (0.00168783, 0.00168783); + fall_capacitance_range (0.00168783, 0.00271845); timing () { related_pin : "GATE"; timing_type : min_pulse_width; @@ -11587,7 +11618,7 @@ library (sg13g2_stdcell_typ_1p20V_25C) { } cell (sg13g2_dlhr_1) { area : 32.6592; - cell_footprint : "DLHR"; + cell_footprint : "dlhr"; cell_leakage_power : 508.576; leakage_power () { value : 461.804; @@ -11693,6 +11724,7 @@ library (sg13g2_stdcell_typ_1p20V_25C) { } timing () { related_pin : "GATE"; + sdf_edges : start_edge; timing_sense : non_unate; timing_type : rising_edge; cell_rise (TIMING_DELAY_7x7ds1) { @@ -11750,6 +11782,7 @@ library (sg13g2_stdcell_typ_1p20V_25C) { } timing () { related_pin : "RESET_B"; + sdf_edges : start_edge; timing_sense : positive_unate; timing_type : clear; cell_fall (TIMING_DELAY_7x7ds1) { @@ -11923,6 +11956,7 @@ library (sg13g2_stdcell_typ_1p20V_25C) { } timing () { related_pin : "GATE"; + sdf_edges : start_edge; timing_sense : non_unate; timing_type : rising_edge; cell_rise (TIMING_DELAY_7x7ds1) { @@ -11980,6 +12014,7 @@ library (sg13g2_stdcell_typ_1p20V_25C) { } timing () { related_pin : "RESET_B"; + sdf_edges : start_edge; timing_sense : negative_unate; timing_type : preset; cell_rise (TIMING_DELAY_7x7ds1) { @@ -12094,11 +12129,12 @@ library (sg13g2_stdcell_typ_1p20V_25C) { max_transition : 2.5074; capacitance : 0.00207682; rise_capacitance : 0.00225755; - rise_capacitance_range (0.00225755, 0.00225755); + rise_capacitance_range (0.0020319, 0.00241885); fall_capacitance : 0.00189609; - fall_capacitance_range (0.00189609, 0.00189609); + fall_capacitance_range (0.00189609, 0.00238393); timing () { related_pin : "GATE"; + sdf_edges : both_edges; timing_type : hold_falling; rise_constraint (CONSTRAINT_4x4) { index_1 ("0.0186, 0.51636, 1.263, 2.5074"); @@ -12123,6 +12159,7 @@ library (sg13g2_stdcell_typ_1p20V_25C) { } timing () { related_pin : "GATE"; + sdf_edges : both_edges; timing_type : setup_falling; rise_constraint (CONSTRAINT_4x4) { index_1 ("0.0186, 0.51636, 1.263, 2.5074"); @@ -12196,9 +12233,9 @@ library (sg13g2_stdcell_typ_1p20V_25C) { max_transition : 2.5074; capacitance : 0.00223878; rise_capacitance : 0.00256375; - rise_capacitance_range (0.00256375, 0.00256375); + rise_capacitance_range (0.00231573, 0.0027907); fall_capacitance : 0.00167007; - fall_capacitance_range (0.00167007, 0.00167007); + fall_capacitance_range (0.00167007, 0.00270182); timing () { related_pin : "GATE"; timing_type : min_pulse_width; @@ -12273,11 +12310,12 @@ library (sg13g2_stdcell_typ_1p20V_25C) { max_transition : 2.5074; capacitance : 0.00311214; rise_capacitance : 0.00323724; - rise_capacitance_range (0.00323724, 0.00323724); + rise_capacitance_range (0.00284325, 0.00359601); fall_capacitance : 0.00303708; - fall_capacitance_range (0.00303708, 0.00303708); + fall_capacitance_range (0.00282429, 0.00319661); timing () { related_pin : "GATE"; + sdf_edges : both_edges; timing_type : recovery_falling; rise_constraint (CONSTRAINT_4x4) { index_1 ("0.0186, 0.51636, 1.263, 2.5074"); @@ -12292,6 +12330,7 @@ library (sg13g2_stdcell_typ_1p20V_25C) { } timing () { related_pin : "GATE"; + sdf_edges : both_edges; timing_type : removal_falling; rise_constraint (CONSTRAINT_4x4) { index_1 ("0.0186, 0.51636, 1.263, 2.5074"); @@ -12360,14 +12399,14 @@ library (sg13g2_stdcell_typ_1p20V_25C) { } } latch (IQ,IQN) { - clear : "RESET_B'"; + clear : "!RESET_B"; data_in : "D"; enable : "GATE"; } } cell (sg13g2_dlhrq_1) { area : 27.216; - cell_footprint : "DLHRQ"; + cell_footprint : "dlhrq"; cell_leakage_power : 397.189; leakage_power () { value : 350.185; @@ -12473,6 +12512,7 @@ library (sg13g2_stdcell_typ_1p20V_25C) { } timing () { related_pin : "GATE"; + sdf_edges : start_edge; timing_sense : non_unate; timing_type : rising_edge; cell_rise (TIMING_DELAY_7x7ds1) { @@ -12530,6 +12570,7 @@ library (sg13g2_stdcell_typ_1p20V_25C) { } timing () { related_pin : "RESET_B"; + sdf_edges : start_edge; timing_sense : positive_unate; timing_type : clear; cell_fall (TIMING_DELAY_7x7ds1) { @@ -12644,11 +12685,12 @@ library (sg13g2_stdcell_typ_1p20V_25C) { max_transition : 2.5074; capacitance : 0.00212744; rise_capacitance : 0.00234731; - rise_capacitance_range (0.00234731, 0.00234731); + rise_capacitance_range (0.00212264, 0.00250858); fall_capacitance : 0.00190757; - fall_capacitance_range (0.00190757, 0.00190757); + fall_capacitance_range (0.00190757, 0.00246832); timing () { related_pin : "GATE"; + sdf_edges : both_edges; timing_type : hold_falling; rise_constraint (CONSTRAINT_4x4) { index_1 ("0.0186, 0.51636, 1.263, 2.5074"); @@ -12673,6 +12715,7 @@ library (sg13g2_stdcell_typ_1p20V_25C) { } timing () { related_pin : "GATE"; + sdf_edges : both_edges; timing_type : setup_falling; rise_constraint (CONSTRAINT_4x4) { index_1 ("0.0186, 0.51636, 1.263, 2.5074"); @@ -12746,9 +12789,9 @@ library (sg13g2_stdcell_typ_1p20V_25C) { max_transition : 2.5074; capacitance : 0.00218896; rise_capacitance : 0.00258692; - rise_capacitance_range (0.00258692, 0.00258692); + rise_capacitance_range (0.00234178, 0.00281247); fall_capacitance : 0.00169151; - fall_capacitance_range (0.00169151, 0.00169151); + fall_capacitance_range (0.00169151, 0.00272547); timing () { related_pin : "GATE"; timing_type : min_pulse_width; @@ -12823,11 +12866,12 @@ library (sg13g2_stdcell_typ_1p20V_25C) { max_transition : 2.5074; capacitance : 0.00294627; rise_capacitance : 0.00302941; - rise_capacitance_range (0.00302941, 0.00302941); + rise_capacitance_range (0.00263944, 0.00339203); fall_capacitance : 0.00288392; - fall_capacitance_range (0.00288392, 0.00288392); + fall_capacitance_range (0.0026686, 0.00302996); timing () { related_pin : "GATE"; + sdf_edges : both_edges; timing_type : recovery_falling; rise_constraint (CONSTRAINT_4x4) { index_1 ("0.0186, 0.51636, 1.263, 2.5074"); @@ -12842,6 +12886,7 @@ library (sg13g2_stdcell_typ_1p20V_25C) { } timing () { related_pin : "GATE"; + sdf_edges : both_edges; timing_type : removal_falling; rise_constraint (CONSTRAINT_4x4) { index_1 ("0.0186, 0.51636, 1.263, 2.5074"); @@ -12910,14 +12955,14 @@ library (sg13g2_stdcell_typ_1p20V_25C) { } } latch (IQ,IQN) { - clear : "RESET_B'"; + clear : "!RESET_B"; data_in : "D"; enable : "GATE"; } } cell (sg13g2_dllr_1) { area : 34.4736; - cell_footprint : "DLLR"; + cell_footprint : "dllr"; cell_leakage_power : 518.326; leakage_power () { value : 485.679; @@ -13039,6 +13084,7 @@ library (sg13g2_stdcell_typ_1p20V_25C) { } timing () { related_pin : "GATE_N"; + sdf_edges : start_edge; timing_sense : non_unate; timing_type : falling_edge; cell_rise (TIMING_DELAY_7x7ds1) { @@ -13096,6 +13142,7 @@ library (sg13g2_stdcell_typ_1p20V_25C) { } timing () { related_pin : "RESET_B"; + sdf_edges : start_edge; timing_sense : positive_unate; timing_type : clear; cell_fall (TIMING_DELAY_7x7ds1) { @@ -13269,6 +13316,7 @@ library (sg13g2_stdcell_typ_1p20V_25C) { } timing () { related_pin : "GATE_N"; + sdf_edges : start_edge; timing_sense : non_unate; timing_type : falling_edge; cell_rise (TIMING_DELAY_7x7ds1) { @@ -13326,6 +13374,7 @@ library (sg13g2_stdcell_typ_1p20V_25C) { } timing () { related_pin : "RESET_B"; + sdf_edges : start_edge; timing_sense : negative_unate; timing_type : preset; cell_rise (TIMING_DELAY_7x7ds1) { @@ -13440,11 +13489,12 @@ library (sg13g2_stdcell_typ_1p20V_25C) { max_transition : 2.5074; capacitance : 0.00214712; rise_capacitance : 0.00232823; - rise_capacitance_range (0.00232823, 0.00232823); + rise_capacitance_range (0.00210099, 0.00249063); fall_capacitance : 0.001966; - fall_capacitance_range (0.001966, 0.001966); + fall_capacitance_range (0.001966, 0.00245296); timing () { related_pin : "GATE_N"; + sdf_edges : both_edges; timing_type : hold_rising; rise_constraint (CONSTRAINT_4x4) { index_1 ("0.0186, 0.51636, 1.263, 2.5074"); @@ -13469,6 +13519,7 @@ library (sg13g2_stdcell_typ_1p20V_25C) { } timing () { related_pin : "GATE_N"; + sdf_edges : both_edges; timing_type : setup_rising; rise_constraint (CONSTRAINT_4x4) { index_1 ("0.0186, 0.51636, 1.263, 2.5074"); @@ -13542,9 +13593,9 @@ library (sg13g2_stdcell_typ_1p20V_25C) { max_transition : 2.5074; capacitance : 0.002304; rise_capacitance : 0.00173754; - rise_capacitance_range (0.00173754, 0.00173754); + rise_capacitance_range (0.00173754, 0.00285837); fall_capacitance : 0.00262769; - fall_capacitance_range (0.00262769, 0.00262769); + fall_capacitance_range (0.00244415, 0.00276889); timing () { related_pin : "GATE_N"; timing_type : min_pulse_width; @@ -13619,11 +13670,12 @@ library (sg13g2_stdcell_typ_1p20V_25C) { max_transition : 2.5074; capacitance : 0.0030741; rise_capacitance : 0.00320002; - rise_capacitance_range (0.00320002, 0.00320002); + rise_capacitance_range (0.00280792, 0.00356304); fall_capacitance : 0.00299854; - fall_capacitance_range (0.00299854, 0.00299854); + fall_capacitance_range (0.00278377, 0.00315854); timing () { related_pin : "GATE_N"; + sdf_edges : both_edges; timing_type : recovery_rising; rise_constraint (CONSTRAINT_4x4) { index_1 ("0.0186, 0.51636, 1.263, 2.5074"); @@ -13638,6 +13690,7 @@ library (sg13g2_stdcell_typ_1p20V_25C) { } timing () { related_pin : "GATE_N"; + sdf_edges : both_edges; timing_type : removal_rising; rise_constraint (CONSTRAINT_4x4) { index_1 ("0.0186, 0.51636, 1.263, 2.5074"); @@ -13706,14 +13759,14 @@ library (sg13g2_stdcell_typ_1p20V_25C) { } } latch (IQ,IQN) { - clear : "RESET_B'"; + clear : "!RESET_B"; data_in : "D"; - enable : "GATE_N'"; + enable : "!GATE_N"; } } cell (sg13g2_dllrq_1) { area : 29.0304; - cell_footprint : "DLLRQ"; + cell_footprint : "dllrq"; cell_leakage_power : 397.168; leakage_power () { value : 374.08; @@ -13819,6 +13872,7 @@ library (sg13g2_stdcell_typ_1p20V_25C) { } timing () { related_pin : "GATE_N"; + sdf_edges : start_edge; timing_sense : non_unate; timing_type : falling_edge; cell_rise (TIMING_DELAY_7x7ds1) { @@ -13876,6 +13930,7 @@ library (sg13g2_stdcell_typ_1p20V_25C) { } timing () { related_pin : "RESET_B"; + sdf_edges : start_edge; timing_sense : positive_unate; timing_type : clear; cell_fall (TIMING_DELAY_7x7ds1) { @@ -13907,6 +13962,7 @@ library (sg13g2_stdcell_typ_1p20V_25C) { } timing () { related_pin : "RESET_B"; + sdf_edges : start_edge; timing_sense : positive_unate; timing_type : preset; cell_rise (TIMING_DELAY_7x7ds1) { @@ -14029,11 +14085,12 @@ library (sg13g2_stdcell_typ_1p20V_25C) { max_transition : 2.5074; capacitance : 0.00203855; rise_capacitance : 0.00225741; - rise_capacitance_range (0.00225741, 0.00225741); + rise_capacitance_range (0.00203423, 0.00241776); fall_capacitance : 0.00181969; - fall_capacitance_range (0.00181969, 0.00181969); + fall_capacitance_range (0.00181969, 0.00237928); timing () { related_pin : "GATE_N"; + sdf_edges : both_edges; timing_type : hold_rising; rise_constraint (CONSTRAINT_4x4) { index_1 ("0.0186, 0.51636, 1.263, 2.5074"); @@ -14058,6 +14115,7 @@ library (sg13g2_stdcell_typ_1p20V_25C) { } timing () { related_pin : "GATE_N"; + sdf_edges : both_edges; timing_type : setup_rising; rise_constraint (CONSTRAINT_4x4) { index_1 ("0.0186, 0.51636, 1.263, 2.5074"); @@ -14131,9 +14189,9 @@ library (sg13g2_stdcell_typ_1p20V_25C) { max_transition : 2.5074; capacitance : 0.00217115; rise_capacitance : 0.0025669; - rise_capacitance_range (0.0025669, 0.0025669); + rise_capacitance_range (0.00232165, 0.00280268); fall_capacitance : 0.00197328; - fall_capacitance_range (0.00197328, 0.00197328); + fall_capacitance_range (0.00197328, 0.00271303); timing () { related_pin : "GATE_N"; timing_type : min_pulse_width; @@ -14208,11 +14266,12 @@ library (sg13g2_stdcell_typ_1p20V_25C) { max_transition : 2.5074; capacitance : 0.00298489; rise_capacitance : 0.00310033; - rise_capacitance_range (0.00310033, 0.00310033); + rise_capacitance_range (0.0025823, 0.00368836); fall_capacitance : 0.00286946; - fall_capacitance_range (0.00286946, 0.00286946); + fall_capacitance_range (0.00265471, 0.00301559); timing () { related_pin : "GATE_N"; + sdf_edges : both_edges; timing_type : recovery_rising; rise_constraint (CONSTRAINT_4x4) { index_1 ("0.0186, 0.51636, 1.263, 2.5074"); @@ -14227,6 +14286,7 @@ library (sg13g2_stdcell_typ_1p20V_25C) { } timing () { related_pin : "GATE_N"; + sdf_edges : both_edges; timing_type : removal_rising; rise_constraint (CONSTRAINT_4x4) { index_1 ("0.0186, 0.51636, 1.263, 2.5074"); @@ -14295,14 +14355,14 @@ library (sg13g2_stdcell_typ_1p20V_25C) { } } latch (IQ,IQN) { - clear : "RESET_B'"; + clear : "!RESET_B"; data_in : "D"; - enable : "GATE_N'"; + enable : "!GATE_N"; } } cell (sg13g2_dlygate4sd1_1) { area : 14.5152; - cell_footprint : "DLY1"; + cell_footprint : "dlygate4sd1"; cell_leakage_power : 186.799; leakage_power () { value : 196.778; @@ -14409,14 +14469,14 @@ library (sg13g2_stdcell_typ_1p20V_25C) { max_transition : 2.5074; capacitance : 0.00148644; rise_capacitance : 0.00147215; - rise_capacitance_range (0.00147215, 0.00147215); + rise_capacitance_range (0.00133542, 0.00160214); fall_capacitance : 0.00150073; - fall_capacitance_range (0.00150073, 0.00150073); + fall_capacitance_range (0.00141149, 0.00156312); } } cell (sg13g2_dlygate4sd2_1) { area : 14.5152; - cell_footprint : "DLY2"; + cell_footprint : "dlygate4sd2"; cell_leakage_power : 188.572; leakage_power () { value : 198.55; @@ -14523,14 +14583,14 @@ library (sg13g2_stdcell_typ_1p20V_25C) { max_transition : 2.5074; capacitance : 0.00148265; rise_capacitance : 0.00146765; - rise_capacitance_range (0.00146765, 0.00146765); + rise_capacitance_range (0.00134557, 0.00158779); fall_capacitance : 0.00149766; - fall_capacitance_range (0.00149766, 0.00149766); + fall_capacitance_range (0.00142274, 0.00155454); } } cell (sg13g2_dlygate4sd3_1) { area : 16.3296; - cell_footprint : "DLY4"; + cell_footprint : "dlygate4sd3"; cell_leakage_power : 399.858; leakage_power () { value : 409.819; @@ -14637,14 +14697,14 @@ library (sg13g2_stdcell_typ_1p20V_25C) { max_transition : 2.5074; capacitance : 0.00150175; rise_capacitance : 0.00148316; - rise_capacitance_range (0.00148316, 0.00148316); + rise_capacitance_range (0.00139554, 0.00157797); fall_capacitance : 0.00152035; - fall_capacitance_range (0.00152035, 0.00152035); + fall_capacitance_range (0.00146182, 0.00156778); } } cell (sg13g2_ebufn_2) { area : 18.144; - cell_footprint : "BTL"; + cell_footprint : "ebufn"; cell_leakage_power : 236.415; leakage_power () { value : 186.811; @@ -14732,6 +14792,7 @@ library (sg13g2_stdcell_typ_1p20V_25C) { } timing () { related_pin : "TE_B"; + sdf_edges : start_edge; timing_sense : positive_unate; timing_type : three_state_disable; cell_rise (TIMING_DELAY_7x7ds1) { @@ -14789,6 +14850,7 @@ library (sg13g2_stdcell_typ_1p20V_25C) { } timing () { related_pin : "TE_B"; + sdf_edges : start_edge; timing_sense : negative_unate; timing_type : three_state_enable; cell_rise (TIMING_DELAY_7x7ds1) { @@ -14908,9 +14970,9 @@ library (sg13g2_stdcell_typ_1p20V_25C) { max_transition : 2.5074; capacitance : 0.00261694; rise_capacitance : 0.00265546; - rise_capacitance_range (0.00265546, 0.00265546); + rise_capacitance_range (0.00238463, 0.00285772); fall_capacitance : 0.00257843; - fall_capacitance_range (0.00257843, 0.00257843); + fall_capacitance_range (0.00234251, 0.00281621); internal_power () { rise_power (passive_POWER_7x1ds1) { index_1 ("0.0186, 0.0966, 0.174, 0.3294, 0.6408, 1.263, 2.5074"); @@ -14931,9 +14993,9 @@ library (sg13g2_stdcell_typ_1p20V_25C) { max_transition : 2.5074; capacitance : 0.00638076; rise_capacitance : 0.00658011; - rise_capacitance_range (0.00658011, 0.00658011); + rise_capacitance_range (0.00496073, 0.00782443); fall_capacitance : 0.00618141; - fall_capacitance_range (0.00618141, 0.00618141); + fall_capacitance_range (0.0046977, 0.00744524); internal_power () { rise_power (passive_POWER_7x1ds1) { index_1 ("0.0186, 0.0966, 0.174, 0.3294, 0.6408, 1.263, 2.5074"); @@ -14952,7 +15014,7 @@ library (sg13g2_stdcell_typ_1p20V_25C) { } cell (sg13g2_ebufn_4) { area : 27.216; - cell_footprint : "BTL"; + cell_footprint : "ebufn"; cell_leakage_power : 376.429; leakage_power () { value : 244.761; @@ -15040,6 +15102,7 @@ library (sg13g2_stdcell_typ_1p20V_25C) { } timing () { related_pin : "TE_B"; + sdf_edges : start_edge; timing_sense : positive_unate; timing_type : three_state_disable; cell_rise (TIMING_DELAY_7x7ds1) { @@ -15097,6 +15160,7 @@ library (sg13g2_stdcell_typ_1p20V_25C) { } timing () { related_pin : "TE_B"; + sdf_edges : start_edge; timing_sense : negative_unate; timing_type : three_state_enable; cell_rise (TIMING_DELAY_7x7ds1) { @@ -15216,9 +15280,9 @@ library (sg13g2_stdcell_typ_1p20V_25C) { max_transition : 2.5074; capacitance : 0.00295943; rise_capacitance : 0.00300683; - rise_capacitance_range (0.00300683, 0.00300683); + rise_capacitance_range (0.00274173, 0.00321924); fall_capacitance : 0.00291204; - fall_capacitance_range (0.00291204, 0.00291204); + fall_capacitance_range (0.00269266, 0.00313335); internal_power () { rise_power (passive_POWER_7x1ds1) { index_1 ("0.0186, 0.0966, 0.174, 0.3294, 0.6408, 1.263, 2.5074"); @@ -15239,9 +15303,9 @@ library (sg13g2_stdcell_typ_1p20V_25C) { max_transition : 2.5074; capacitance : 0.0104467; rise_capacitance : 0.0108192; - rise_capacitance_range (0.0108192, 0.0108192); + rise_capacitance_range (0.00774883, 0.0131385); fall_capacitance : 0.0100741; - fall_capacitance_range (0.0100741, 0.0100741); + fall_capacitance_range (0.00724697, 0.0123306); internal_power () { rise_power (passive_POWER_7x1ds1) { index_1 ("0.0186, 0.0966, 0.174, 0.3294, 0.6408, 1.263, 2.5074"); @@ -15260,7 +15324,7 @@ library (sg13g2_stdcell_typ_1p20V_25C) { } cell (sg13g2_ebufn_8) { area : 45.36; - cell_footprint : "BTL"; + cell_footprint : "ebufn"; cell_leakage_power : 689.888; leakage_power () { value : 407.12; @@ -15348,6 +15412,7 @@ library (sg13g2_stdcell_typ_1p20V_25C) { } timing () { related_pin : "TE_B"; + sdf_edges : start_edge; timing_sense : positive_unate; timing_type : three_state_disable; cell_rise (TIMING_DELAY_7x7ds1) { @@ -15405,6 +15470,7 @@ library (sg13g2_stdcell_typ_1p20V_25C) { } timing () { related_pin : "TE_B"; + sdf_edges : start_edge; timing_sense : negative_unate; timing_type : three_state_enable; cell_rise (TIMING_DELAY_7x7ds1) { @@ -15524,9 +15590,9 @@ library (sg13g2_stdcell_typ_1p20V_25C) { max_transition : 2.5074; capacitance : 0.00577312; rise_capacitance : 0.00586929; - rise_capacitance_range (0.00586929, 0.00586929); + rise_capacitance_range (0.00531469, 0.00630491); fall_capacitance : 0.00567695; - fall_capacitance_range (0.00567695, 0.00567695); + fall_capacitance_range (0.00520966, 0.00614021); internal_power () { rise_power (passive_POWER_7x1ds1) { index_1 ("0.0186, 0.0966, 0.174, 0.3294, 0.6408, 1.263, 2.5074"); @@ -15547,9 +15613,9 @@ library (sg13g2_stdcell_typ_1p20V_25C) { max_transition : 2.5074; capacitance : 0.0175575; rise_capacitance : 0.0182468; - rise_capacitance_range (0.0182468, 0.0182468); + rise_capacitance_range (0.0120697, 0.0229184); fall_capacitance : 0.0168682; - fall_capacitance_range (0.0168682, 0.0168682); + fall_capacitance_range (0.0110652, 0.0213665); internal_power () { rise_power (passive_POWER_7x1ds1) { index_1 ("0.0186, 0.0966, 0.174, 0.3294, 0.6408, 1.263, 2.5074"); @@ -15568,7 +15634,7 @@ library (sg13g2_stdcell_typ_1p20V_25C) { } cell (sg13g2_einvn_2) { area : 16.3296; - cell_footprint : "einvin"; + cell_footprint : "einvn"; cell_leakage_power : 240.424; leakage_power () { value : 201.554; @@ -15648,6 +15714,7 @@ library (sg13g2_stdcell_typ_1p20V_25C) { } timing () { related_pin : "TE_B"; + sdf_edges : start_edge; timing_sense : positive_unate; timing_type : three_state_disable_rise; cell_rise (TIMING_DELAY_7x7ds1) { @@ -15679,6 +15746,7 @@ library (sg13g2_stdcell_typ_1p20V_25C) { } timing () { related_pin : "TE_B"; + sdf_edges : start_edge; timing_sense : negative_unate; timing_type : three_state_enable_rise; cell_rise (TIMING_DELAY_7x7ds1) { @@ -15764,9 +15832,9 @@ library (sg13g2_stdcell_typ_1p20V_25C) { max_transition : 2.5074; capacitance : 0.00408184; rise_capacitance : 0.00417065; - rise_capacitance_range (0.00417065, 0.00417065); + rise_capacitance_range (0.00244586, 0.00663879); fall_capacitance : 0.00399303; - fall_capacitance_range (0.00399303, 0.00399303); + fall_capacitance_range (0.00237783, 0.00634266); internal_power () { rise_power (passive_POWER_7x1ds1) { index_1 ("0.0186, 0.0966, 0.174, 0.3294, 0.6408, 1.263, 2.5074"); @@ -15787,9 +15855,9 @@ library (sg13g2_stdcell_typ_1p20V_25C) { max_transition : 2.5074; capacitance : 0.00486017; rise_capacitance : 0.00556323; - rise_capacitance_range (0.00556323, 0.00556323); + rise_capacitance_range (0.00520326, 0.00575228); fall_capacitance : 0.0041571; - fall_capacitance_range (0.0041571, 0.0041571); + fall_capacitance_range (0.00308959, 0.00613553); internal_power () { rise_power (passive_POWER_7x1ds1) { index_1 ("0.0186, 0.0966, 0.174, 0.3294, 0.6408, 1.263, 2.5074"); @@ -15808,7 +15876,7 @@ library (sg13g2_stdcell_typ_1p20V_25C) { } cell (sg13g2_einvn_4) { area : 23.5872; - cell_footprint : "einvin"; + cell_footprint : "einvn"; cell_leakage_power : 477.268; leakage_power () { value : 399.525; @@ -15888,6 +15956,7 @@ library (sg13g2_stdcell_typ_1p20V_25C) { } timing () { related_pin : "TE_B"; + sdf_edges : start_edge; timing_sense : positive_unate; timing_type : three_state_disable_rise; cell_rise (TIMING_DELAY_7x7ds1) { @@ -15919,6 +15988,7 @@ library (sg13g2_stdcell_typ_1p20V_25C) { } timing () { related_pin : "TE_B"; + sdf_edges : start_edge; timing_sense : negative_unate; timing_type : three_state_enable_rise; cell_rise (TIMING_DELAY_7x7ds1) { @@ -16004,9 +16074,9 @@ library (sg13g2_stdcell_typ_1p20V_25C) { max_transition : 2.5074; capacitance : 0.00796158; rise_capacitance : 0.00813547; - rise_capacitance_range (0.00813547, 0.00813547); + rise_capacitance_range (0.00465521, 0.0132011); fall_capacitance : 0.00778769; - fall_capacitance_range (0.00778769, 0.00778769); + fall_capacitance_range (0.00452198, 0.0126161); internal_power () { rise_power (passive_POWER_7x1ds1) { index_1 ("0.0186, 0.0966, 0.174, 0.3294, 0.6408, 1.263, 2.5074"); @@ -16027,9 +16097,9 @@ library (sg13g2_stdcell_typ_1p20V_25C) { max_transition : 2.5074; capacitance : 0.00906303; rise_capacitance : 0.0103962; - rise_capacitance_range (0.0103962, 0.0103962); + rise_capacitance_range (0.00954745, 0.010795); fall_capacitance : 0.0077299; - fall_capacitance_range (0.0077299, 0.0077299); + fall_capacitance_range (0.00564843, 0.0117139); internal_power () { rise_power (passive_POWER_7x1ds1) { index_1 ("0.0186, 0.0966, 0.174, 0.3294, 0.6408, 1.263, 2.5074"); @@ -16048,7 +16118,7 @@ library (sg13g2_stdcell_typ_1p20V_25C) { } cell (sg13g2_einvn_8) { area : 39.9168; - cell_footprint : "ITL"; + cell_footprint : "einvn"; cell_leakage_power : 910.997; leakage_power () { value : 755.515; @@ -16128,6 +16198,7 @@ library (sg13g2_stdcell_typ_1p20V_25C) { } timing () { related_pin : "TE_B"; + sdf_edges : start_edge; timing_sense : positive_unate; timing_type : three_state_disable_rise; cell_rise (TIMING_DELAY_7x7ds1) { @@ -16159,6 +16230,7 @@ library (sg13g2_stdcell_typ_1p20V_25C) { } timing () { related_pin : "TE_B"; + sdf_edges : start_edge; timing_sense : negative_unate; timing_type : three_state_enable_rise; cell_rise (TIMING_DELAY_7x7ds1) { @@ -16244,9 +16316,9 @@ library (sg13g2_stdcell_typ_1p20V_25C) { max_transition : 2.5074; capacitance : 0.0157512; rise_capacitance : 0.0160995; - rise_capacitance_range (0.0160995, 0.0160995); + rise_capacitance_range (0.00905651, 0.0263546); fall_capacitance : 0.0154029; - fall_capacitance_range (0.0154029, 0.0154029); + fall_capacitance_range (0.00880418, 0.0252315); internal_power () { rise_power (passive_POWER_7x1ds1) { index_1 ("0.0186, 0.0966, 0.174, 0.3294, 0.6408, 1.263, 2.5074"); @@ -16267,9 +16339,9 @@ library (sg13g2_stdcell_typ_1p20V_25C) { max_transition : 2.5074; capacitance : 0.0155516; rise_capacitance : 0.0176426; - rise_capacitance_range (0.0176426, 0.0176426); + rise_capacitance_range (0.0153782, 0.018388); fall_capacitance : 0.0134606; - fall_capacitance_range (0.0134606, 0.0134606); + fall_capacitance_range (0.0102729, 0.0204137); internal_power () { rise_power (passive_POWER_7x1ds1) { index_1 ("0.0186, 0.0966, 0.174, 0.3294, 0.6408, 1.263, 2.5074"); @@ -16320,7 +16392,7 @@ library (sg13g2_stdcell_typ_1p20V_25C) { } cell (sg13g2_inv_1) { area : 5.4432; - cell_footprint : "IN"; + cell_footprint : "inv"; cell_leakage_power : 63.0032; leakage_power () { value : 82.469; @@ -16427,14 +16499,14 @@ library (sg13g2_stdcell_typ_1p20V_25C) { max_transition : 2.5074; capacitance : 0.00286745; rise_capacitance : 0.0029192; - rise_capacitance_range (0.0029192, 0.0029192); + rise_capacitance_range (0.00257641, 0.00326597); fall_capacitance : 0.00281571; - fall_capacitance_range (0.00281571, 0.00281571); + fall_capacitance_range (0.00257013, 0.00324525); } } cell (sg13g2_inv_16) { area : 34.4736; - cell_footprint : "IN"; + cell_footprint : "inv"; cell_leakage_power : 1007.55; leakage_power () { value : 1318.51; @@ -16541,14 +16613,14 @@ library (sg13g2_stdcell_typ_1p20V_25C) { max_transition : 2.5074; capacitance : 0.0435406; rise_capacitance : 0.0443145; - rise_capacitance_range (0.0443145, 0.0443145); + rise_capacitance_range (0.0329871, 0.0520904); fall_capacitance : 0.0427666; - fall_capacitance_range (0.0427666, 0.0427666); + fall_capacitance_range (0.0333422, 0.052419); } } cell (sg13g2_inv_2) { area : 7.2576; - cell_footprint : "IN"; + cell_footprint : "inv"; cell_leakage_power : 125.956; leakage_power () { value : 164.83; @@ -16655,14 +16727,14 @@ library (sg13g2_stdcell_typ_1p20V_25C) { max_transition : 2.5074; capacitance : 0.00567488; rise_capacitance : 0.0057764; - rise_capacitance_range (0.0057764, 0.0057764); + rise_capacitance_range (0.00501018, 0.00655516); fall_capacitance : 0.00557335; - fall_capacitance_range (0.00557335, 0.00557335); + fall_capacitance_range (0.00501673, 0.00658036); } } cell (sg13g2_inv_4) { area : 10.8864; - cell_footprint : "IN"; + cell_footprint : "inv"; cell_leakage_power : 251.89; leakage_power () { value : 329.63; @@ -16769,14 +16841,14 @@ library (sg13g2_stdcell_typ_1p20V_25C) { max_transition : 2.5074; capacitance : 0.0112211; rise_capacitance : 0.0114223; - rise_capacitance_range (0.0114223, 0.0114223); + rise_capacitance_range (0.00987459, 0.0130548); fall_capacitance : 0.0110198; - fall_capacitance_range (0.0110198, 0.0110198); + fall_capacitance_range (0.00989031, 0.0131695); } } cell (sg13g2_inv_8) { area : 18.144; - cell_footprint : "IN"; + cell_footprint : "inv"; cell_leakage_power : 503.803; leakage_power () { value : 659.308; @@ -16883,14 +16955,14 @@ library (sg13g2_stdcell_typ_1p20V_25C) { max_transition : 2.5074; capacitance : 0.0224507; rise_capacitance : 0.0228521; - rise_capacitance_range (0.0228521, 0.0228521); + rise_capacitance_range (0.0196154, 0.0262055); fall_capacitance : 0.0220493; - fall_capacitance_range (0.0220493, 0.0220493); + fall_capacitance_range (0.0196897, 0.0265021); } } cell (sg13g2_lgcp_1) { area : 27.216; - cell_footprint : "gclk"; + cell_footprint : "lgcp"; cell_leakage_power : 389.668; clock_gating_integrated_cell : "latch_posedge"; dont_use : true; @@ -17014,9 +17086,9 @@ library (sg13g2_stdcell_typ_1p20V_25C) { max_transition : 2.5074; capacitance : 0.00493856; rise_capacitance : 0.00497755; - rise_capacitance_range (0.00497755, 0.00497755); + rise_capacitance_range (0.00437826, 0.005764); fall_capacitance : 0.00489956; - fall_capacitance_range (0.00489956, 0.00489956); + fall_capacitance_range (0.00452406, 0.00517495); timing () { related_pin : "CLK"; timing_type : min_pulse_width; @@ -17054,11 +17126,12 @@ library (sg13g2_stdcell_typ_1p20V_25C) { max_transition : 2.5074; capacitance : 0.002298; rise_capacitance : 0.00255801; - rise_capacitance_range (0.00255801, 0.00255801); + rise_capacitance_range (0.00230022, 0.002823); fall_capacitance : 0.00203799; - fall_capacitance_range (0.00203799, 0.00203799); + fall_capacitance_range (0.00203799, 0.00231672); timing () { related_pin : "CLK"; + sdf_edges : both_edges; timing_type : hold_rising; rise_constraint (CONSTRAINT_4x4) { index_1 ("0.0186, 0.51636, 1.263, 2.5074"); @@ -17083,6 +17156,7 @@ library (sg13g2_stdcell_typ_1p20V_25C) { } timing () { related_pin : "CLK"; + sdf_edges : both_edges; timing_type : setup_rising; rise_constraint (CONSTRAINT_4x4) { index_1 ("0.0186, 0.51636, 1.263, 2.5074"); @@ -17293,7 +17367,7 @@ library (sg13g2_stdcell_typ_1p20V_25C) { } timing () { related_pin : "S"; - sdf_cond : "A0 == 1'b0 & A1 == 1'b1"; + sdf_cond : "A0 == 1'b0 && A1 == 1'b1"; timing_sense : positive_unate; timing_type : combinational; when : "(!A0 * A1)"; @@ -17409,7 +17483,7 @@ library (sg13g2_stdcell_typ_1p20V_25C) { } timing () { related_pin : "S"; - sdf_cond : "A0 == 1'b1 & A1 == 1'b0"; + sdf_cond : "A0 == 1'b1 && A1 == 1'b0"; timing_sense : negative_unate; timing_type : combinational; when : "(A0 * !A1)"; @@ -17619,27 +17693,27 @@ library (sg13g2_stdcell_typ_1p20V_25C) { max_transition : 2.5074; capacitance : 0.00278055; rise_capacitance : 0.00282301; - rise_capacitance_range (0.00282301, 0.00282301); + rise_capacitance_range (0.00246638, 0.00309771); fall_capacitance : 0.00273808; - fall_capacitance_range (0.00273808, 0.00273808); + fall_capacitance_range (0.00242215, 0.0029306); } pin (A1) { direction : "input"; max_transition : 2.5074; capacitance : 0.00288461; rise_capacitance : 0.0029269; - rise_capacitance_range (0.0029269, 0.0029269); + rise_capacitance_range (0.00257304, 0.00320012); fall_capacitance : 0.00284232; - fall_capacitance_range (0.00284232, 0.00284232); + fall_capacitance_range (0.00252836, 0.00303622); } pin (S) { direction : "input"; max_transition : 2.5074; capacitance : 0.00505031; rise_capacitance : 0.00509659; - rise_capacitance_range (0.00509659, 0.00509659); + rise_capacitance_range (0.00436972, 0.00599562); fall_capacitance : 0.00500403; - fall_capacitance_range (0.00500403, 0.00500403); + fall_capacitance_range (0.00436307, 0.00595536); internal_power () { when : "(A0 * A1)"; rise_power (passive_POWER_7x1ds1) { @@ -17843,7 +17917,7 @@ library (sg13g2_stdcell_typ_1p20V_25C) { } timing () { related_pin : "S"; - sdf_cond : "A0 == 1'b0 & A1 == 1'b1"; + sdf_cond : "A0 == 1'b0 && A1 == 1'b1"; timing_sense : positive_unate; timing_type : combinational; when : "(!A0 * A1)"; @@ -17959,7 +18033,7 @@ library (sg13g2_stdcell_typ_1p20V_25C) { } timing () { related_pin : "S"; - sdf_cond : "A0 == 1'b1 & A1 == 1'b0"; + sdf_cond : "A0 == 1'b1 && A1 == 1'b0"; timing_sense : negative_unate; timing_type : combinational; when : "(A0 * !A1)"; @@ -18169,27 +18243,27 @@ library (sg13g2_stdcell_typ_1p20V_25C) { max_transition : 2.5074; capacitance : 0.00277208; rise_capacitance : 0.00281155; - rise_capacitance_range (0.00281155, 0.00281155); + rise_capacitance_range (0.00251814, 0.0030569); fall_capacitance : 0.0027326; - fall_capacitance_range (0.0027326, 0.0027326); + fall_capacitance_range (0.00246879, 0.00290262); } pin (A1) { direction : "input"; max_transition : 2.5074; capacitance : 0.00287527; rise_capacitance : 0.00291488; - rise_capacitance_range (0.00291488, 0.00291488); + rise_capacitance_range (0.00262339, 0.00315971); fall_capacitance : 0.00283566; - fall_capacitance_range (0.00283566, 0.00283566); + fall_capacitance_range (0.00257628, 0.00300527); } pin (S) { direction : "input"; max_transition : 2.5074; capacitance : 0.00504218; rise_capacitance : 0.0050886; - rise_capacitance_range (0.0050886, 0.0050886); + rise_capacitance_range (0.00436336, 0.00598744); fall_capacitance : 0.00499575; - fall_capacitance_range (0.00499575, 0.00499575); + fall_capacitance_range (0.0043546, 0.00594745); internal_power () { when : "(A0 * A1)"; rise_power (passive_POWER_7x1ds1) { @@ -18731,7 +18805,7 @@ library (sg13g2_stdcell_typ_1p20V_25C) { } timing () { related_pin : "S0"; - sdf_cond : "A2 == 1'b0 & A3 == 1'b1 & S1 == 1'b1"; + sdf_cond : "A2 == 1'b0 && A3 == 1'b1 && S1 == 1'b1"; timing_sense : positive_unate; timing_type : combinational; when : "(!A2 * A3 * S1)"; @@ -18790,7 +18864,7 @@ library (sg13g2_stdcell_typ_1p20V_25C) { } timing () { related_pin : "S0"; - sdf_cond : "A0 == 1'b0 & A1 == 1'b1 & S1 == 1'b0"; + sdf_cond : "A0 == 1'b0 && A1 == 1'b1 && S1 == 1'b0"; timing_sense : positive_unate; timing_type : combinational; when : "(!A0 * A1 * !S1)"; @@ -18906,7 +18980,7 @@ library (sg13g2_stdcell_typ_1p20V_25C) { } timing () { related_pin : "S0"; - sdf_cond : "A2 == 1'b1 & A3 == 1'b0 & S1 == 1'b1"; + sdf_cond : "A2 == 1'b1 && A3 == 1'b0 && S1 == 1'b1"; timing_sense : negative_unate; timing_type : combinational; when : "(A2 * !A3 * S1)"; @@ -18965,7 +19039,7 @@ library (sg13g2_stdcell_typ_1p20V_25C) { } timing () { related_pin : "S0"; - sdf_cond : "A0 == 1'b1 & A1 == 1'b0 & S1 == 1'b0"; + sdf_cond : "A0 == 1'b1 && A1 == 1'b0 && S1 == 1'b0"; timing_sense : negative_unate; timing_type : combinational; when : "(A0 * !A1 * !S1)"; @@ -19024,7 +19098,7 @@ library (sg13g2_stdcell_typ_1p20V_25C) { } timing () { related_pin : "S1"; - sdf_cond : "A1 == 1'b0 & A3 == 1'b1 & S0 == 1'b1"; + sdf_cond : "A1 == 1'b0 && A3 == 1'b1 && S0 == 1'b1"; timing_sense : positive_unate; timing_type : combinational; when : "(!A1 * A3 * S0)"; @@ -19083,7 +19157,7 @@ library (sg13g2_stdcell_typ_1p20V_25C) { } timing () { related_pin : "S1"; - sdf_cond : "A0 == 1'b0 & A2 == 1'b1 & S0 == 1'b0"; + sdf_cond : "A0 == 1'b0 && A2 == 1'b1 && S0 == 1'b0"; timing_sense : positive_unate; timing_type : combinational; when : "(!A0 * A2 * !S0)"; @@ -19199,7 +19273,7 @@ library (sg13g2_stdcell_typ_1p20V_25C) { } timing () { related_pin : "S1"; - sdf_cond : "A1 == 1'b1 & A3 == 1'b0 & S0 == 1'b1"; + sdf_cond : "A1 == 1'b1 && A3 == 1'b0 && S0 == 1'b1"; timing_sense : negative_unate; timing_type : combinational; when : "(A1 * !A3 * S0)"; @@ -19258,7 +19332,7 @@ library (sg13g2_stdcell_typ_1p20V_25C) { } timing () { related_pin : "S1"; - sdf_cond : "A0 == 1'b1 & A2 == 1'b0 & S0 == 1'b0"; + sdf_cond : "A0 == 1'b1 && A2 == 1'b0 && S0 == 1'b0"; timing_sense : negative_unate; timing_type : combinational; when : "(A0 * !A2 * !S0)"; @@ -19735,45 +19809,45 @@ library (sg13g2_stdcell_typ_1p20V_25C) { max_transition : 2.5074; capacitance : 0.0027824; rise_capacitance : 0.00282588; - rise_capacitance_range (0.00282588, 0.00282588); + rise_capacitance_range (0.00247361, 0.00310975); fall_capacitance : 0.00273892; - fall_capacitance_range (0.00273892, 0.00273892); + fall_capacitance_range (0.00241151, 0.00303577); } pin (A1) { direction : "input"; max_transition : 2.5074; capacitance : 0.00275974; rise_capacitance : 0.00280055; - rise_capacitance_range (0.00280055, 0.00280055); + rise_capacitance_range (0.00247246, 0.00310484); fall_capacitance : 0.00271894; - fall_capacitance_range (0.00271894, 0.00271894); + fall_capacitance_range (0.00236221, 0.00300177); } pin (A2) { direction : "input"; max_transition : 2.5074; capacitance : 0.00278105; rise_capacitance : 0.0028228; - rise_capacitance_range (0.0028228, 0.0028228); + rise_capacitance_range (0.002473, 0.00310582); fall_capacitance : 0.0027393; - fall_capacitance_range (0.0027393, 0.0027393); + fall_capacitance_range (0.00239407, 0.00302853); } pin (A3) { direction : "input"; max_transition : 2.5074; capacitance : 0.00284281; rise_capacitance : 0.00288339; - rise_capacitance_range (0.00288339, 0.00288339); + rise_capacitance_range (0.00252366, 0.00317363); fall_capacitance : 0.00280222; - fall_capacitance_range (0.00280222, 0.00280222); + fall_capacitance_range (0.00243725, 0.00308314); } pin (S0) { direction : "input"; max_transition : 2.5074; capacitance : 0.00824878; rise_capacitance : 0.00983066; - rise_capacitance_range (0.00983066, 0.00983066); + rise_capacitance_range (0.00751536, 0.0111626); fall_capacitance : 0.0066669; - fall_capacitance_range (0.0066669, 0.0066669); + fall_capacitance_range (0.00404943, 0.00976284); internal_power () { when : "(A2 * A3 * S1)"; rise_power (passive_POWER_7x1ds1) { @@ -19854,9 +19928,9 @@ library (sg13g2_stdcell_typ_1p20V_25C) { max_transition : 2.5074; capacitance : 0.00501805; rise_capacitance : 0.0050733; - rise_capacitance_range (0.0050733, 0.0050733); + rise_capacitance_range (0.00424396, 0.00594877); fall_capacitance : 0.0049628; - fall_capacitance_range (0.0049628, 0.0049628); + fall_capacitance_range (0.00424492, 0.00576095); internal_power () { when : "(A1 * A3 * S0)"; rise_power (passive_POWER_7x1ds1) { @@ -20136,18 +20210,18 @@ library (sg13g2_stdcell_typ_1p20V_25C) { max_transition : 2.5074; capacitance : 0.00288593; rise_capacitance : 0.00292764; - rise_capacitance_range (0.00292764, 0.00292764); + rise_capacitance_range (0.00260166, 0.00319719); fall_capacitance : 0.00284422; - fall_capacitance_range (0.00284422, 0.00284422); + fall_capacitance_range (0.00248978, 0.00331715); } pin (B) { direction : "input"; max_transition : 2.5074; capacitance : 0.00297812; rise_capacitance : 0.00309603; - rise_capacitance_range (0.00309603, 0.00309603); + rise_capacitance_range (0.00266108, 0.00344888); fall_capacitance : 0.0028602; - fall_capacitance_range (0.0028602, 0.0028602); + fall_capacitance_range (0.00266141, 0.00318646); } } cell (sg13g2_nand2_2) { @@ -20353,23 +20427,23 @@ library (sg13g2_stdcell_typ_1p20V_25C) { max_transition : 2.5074; capacitance : 0.00559162; rise_capacitance : 0.00568422; - rise_capacitance_range (0.00568422, 0.00568422); + rise_capacitance_range (0.00498354, 0.00622475); fall_capacitance : 0.00549903; - fall_capacitance_range (0.00549903, 0.00549903); + fall_capacitance_range (0.00473801, 0.00658635); } pin (B) { direction : "input"; max_transition : 2.5074; capacitance : 0.00571313; rise_capacitance : 0.00595231; - rise_capacitance_range (0.00595231, 0.00595231); + rise_capacitance_range (0.00509954, 0.00665741); fall_capacitance : 0.00547395; - fall_capacitance_range (0.00547395, 0.00547395); + fall_capacitance_range (0.00505483, 0.00618505); } } cell (sg13g2_nand2b_1) { area : 9.072; - cell_footprint : "nand2b1"; + cell_footprint : "nand2b"; cell_leakage_power : 128.618; leakage_power () { value : 196.395; @@ -20570,9 +20644,9 @@ library (sg13g2_stdcell_typ_1p20V_25C) { max_transition : 2.5074; capacitance : 0.00224218; rise_capacitance : 0.0022721; - rise_capacitance_range (0.0022721, 0.0022721); + rise_capacitance_range (0.00203866, 0.00243946); fall_capacitance : 0.00221226; - fall_capacitance_range (0.00221226, 0.00221226); + fall_capacitance_range (0.00201752, 0.0023925); internal_power () { when : "!B"; rise_power (passive_POWER_7x1ds1) { @@ -20608,14 +20682,14 @@ library (sg13g2_stdcell_typ_1p20V_25C) { max_transition : 2.5074; capacitance : 0.00302537; rise_capacitance : 0.00314371; - rise_capacitance_range (0.00314371, 0.00314371); + rise_capacitance_range (0.00270156, 0.00349571); fall_capacitance : 0.00290704; - fall_capacitance_range (0.00290704, 0.00290704); + fall_capacitance_range (0.00270645, 0.00323163); } } cell (sg13g2_nand2b_2) { area : 14.5152; - cell_footprint : "nand2b2"; + cell_footprint : "nand2b"; cell_leakage_power : 207.93; leakage_power () { value : 357.852; @@ -20816,9 +20890,9 @@ library (sg13g2_stdcell_typ_1p20V_25C) { max_transition : 2.5074; capacitance : 0.00219968; rise_capacitance : 0.00223209; - rise_capacitance_range (0.00223209, 0.00223209); + rise_capacitance_range (0.00207025, 0.00236747); fall_capacitance : 0.00216728; - fall_capacitance_range (0.00216728, 0.00216728); + fall_capacitance_range (0.00201809, 0.00231119); internal_power () { when : "!B"; rise_power (passive_POWER_7x1ds1) { @@ -20854,9 +20928,9 @@ library (sg13g2_stdcell_typ_1p20V_25C) { max_transition : 2.5074; capacitance : 0.00561566; rise_capacitance : 0.00570838; - rise_capacitance_range (0.00570838, 0.00570838); + rise_capacitance_range (0.00500472, 0.00624916); fall_capacitance : 0.00552294; - fall_capacitance_range (0.00552294, 0.00552294); + fall_capacitance_range (0.00475134, 0.00661391); } } cell (sg13g2_nand3_1) { @@ -21164,32 +21238,32 @@ library (sg13g2_stdcell_typ_1p20V_25C) { max_transition : 2.5074; capacitance : 0.00287977; rise_capacitance : 0.00291574; - rise_capacitance_range (0.00291574, 0.00291574); + rise_capacitance_range (0.00261846, 0.00313392); fall_capacitance : 0.0028438; - fall_capacitance_range (0.0028438, 0.0028438); + fall_capacitance_range (0.00244977, 0.0033271); } pin (B) { direction : "input"; max_transition : 2.5074; capacitance : 0.00300949; rise_capacitance : 0.00311491; - rise_capacitance_range (0.00311491, 0.00311491); + rise_capacitance_range (0.00269367, 0.0034513); fall_capacitance : 0.00290407; - fall_capacitance_range (0.00290407, 0.00290407); + fall_capacitance_range (0.00263811, 0.00326572); } pin (C) { direction : "input"; max_transition : 2.5074; capacitance : 0.00297917; rise_capacitance : 0.00310025; - rise_capacitance_range (0.00310025, 0.00310025); + rise_capacitance_range (0.0026814, 0.00345652); fall_capacitance : 0.00285809; - fall_capacitance_range (0.00285809, 0.00285809); + fall_capacitance_range (0.00269708, 0.00313327); } } cell (sg13g2_nand3b_1) { area : 12.7008; - cell_footprint : "nand3b1"; + cell_footprint : "nand3b"; cell_leakage_power : 134.524; leakage_power () { value : 82.6627; @@ -21492,9 +21566,9 @@ library (sg13g2_stdcell_typ_1p20V_25C) { max_transition : 2.5074; capacitance : 0.00222256; rise_capacitance : 0.00225252; - rise_capacitance_range (0.00225252, 0.00225252); + rise_capacitance_range (0.0020181, 0.00241982); fall_capacitance : 0.00219259; - fall_capacitance_range (0.00219259, 0.00219259); + fall_capacitance_range (0.00199962, 0.00237313); internal_power () { when : "(B * !C) + (!B)"; rise_power (passive_POWER_7x1ds1) { @@ -21530,18 +21604,18 @@ library (sg13g2_stdcell_typ_1p20V_25C) { max_transition : 2.5074; capacitance : 0.00297309; rise_capacitance : 0.00307879; - rise_capacitance_range (0.00307879, 0.00307879); + rise_capacitance_range (0.00265074, 0.00341451); fall_capacitance : 0.00286738; - fall_capacitance_range (0.00286738, 0.00286738); + fall_capacitance_range (0.00259636, 0.00322734); } pin (C) { direction : "input"; max_transition : 2.5074; capacitance : 0.00298984; rise_capacitance : 0.00311115; - rise_capacitance_range (0.00311115, 0.00311115); + rise_capacitance_range (0.00269433, 0.00346703); fall_capacitance : 0.00286853; - fall_capacitance_range (0.00286853, 0.00286853); + fall_capacitance_range (0.00270556, 0.00314293); } } cell (sg13g2_nand4_1) { @@ -21625,10 +21699,10 @@ library (sg13g2_stdcell_typ_1p20V_25C) { index_1 ("0.0186, 0.0966, 0.174, 0.3294, 0.6408, 1.263, 2.5074"); index_2 ("0.001, 0.0234, 0.039, 0.0648, 0.108, 0.18, 0.3"); values ( \ - "0.0272544, 0.0907524, 0.133989, 0.205571, 0.324984, 0.524647, 0.856507", \ - "0.0525253, 0.133998, 0.17854, 0.250373, 0.369852, 0.569288, 0.901467", \ - "0.0650716, 0.168484, 0.217994, 0.292364, 0.412489, 0.611684, 0.943915", \ - "0.0814472, 0.222153, 0.284059, 0.370227, 0.497999, 0.699821, 1.03207", \ + "0.0272572, 0.0907276, 0.133988, 0.205597, 0.324992, 0.524654, 0.856616", \ + "0.0525253, 0.133998, 0.17854, 0.250358, 0.369924, 0.569295, 0.901812", \ + "0.0650716, 0.168478, 0.217994, 0.292364, 0.412503, 0.611744, 0.943811", \ + "0.0814472, 0.222153, 0.284059, 0.370227, 0.497999, 0.699821, 1.03206", \ "0.0997191, 0.299722, 0.383367, 0.49595, 0.649433, 0.870393, 1.21101", \ "0.115788, 0.398111, 0.518628, 0.67223, 0.877459, 1.15124, 1.53689", \ "0.120122, 0.51377, 0.687656, 0.911749, 1.19725, 1.56992, 2.06166" \ @@ -21638,10 +21712,10 @@ library (sg13g2_stdcell_typ_1p20V_25C) { index_1 ("0.0186, 0.0966, 0.174, 0.3294, 0.6408, 1.263, 2.5074"); index_2 ("0.001, 0.0234, 0.039, 0.0648, 0.108, 0.18, 0.3"); values ( \ - "0.0192455, 0.108487, 0.171246, 0.275064, 0.44856, 0.738108, 1.22086", \ - "0.0370715, 0.116676, 0.175203, 0.276054, 0.44967, 0.738163, 1.22087", \ - "0.0514286, 0.134349, 0.189083, 0.284102, 0.451254, 0.741727, 1.22088", \ - "0.0747831, 0.173538, 0.227369, 0.316822, 0.472702, 0.747389, 1.22217", \ + "0.0192574, 0.108499, 0.171246, 0.275078, 0.448548, 0.738108, 1.22086", \ + "0.0370715, 0.11668, 0.175203, 0.276124, 0.448748, 0.738146, 1.22111", \ + "0.0514286, 0.134341, 0.189083, 0.284102, 0.451404, 0.738992, 1.22112", \ + "0.0747831, 0.173538, 0.227369, 0.316823, 0.472702, 0.747389, 1.22385", \ "0.113027, 0.244249, 0.304779, 0.395286, 0.544476, 0.798412, 1.24769", \ "0.172826, 0.361357, 0.435812, 0.542752, 0.700407, 0.949799, 1.36467", \ "0.270352, 0.543098, 0.653945, 0.790374, 0.980713, 1.25637, 1.67671" \ @@ -21651,26 +21725,26 @@ library (sg13g2_stdcell_typ_1p20V_25C) { index_1 ("0.0186, 0.0966, 0.174, 0.3294, 0.6408, 1.263, 2.5074"); index_2 ("0.001, 0.0234, 0.039, 0.0648, 0.108, 0.18, 0.3"); values ( \ - "0.0571422, 0.23621, 0.358715, 0.560983, 0.899797, 1.46363, 2.40448", \ - "0.0832838, 0.269501, 0.392465, 0.595222, 0.934148, 1.49842, 2.43911", \ - "0.101703, 0.302745, 0.426483, 0.629321, 0.968394, 1.53301, 2.47339", \ - "0.128065, 0.362824, 0.492718, 0.69756, 1.03638, 1.60097, 2.54196", \ - "0.166688, 0.458366, 0.607765, 0.829731, 1.17673, 1.74079, 2.68016", \ - "0.222943, 0.598115, 0.783269, 1.04512, 1.43144, 2.02012, 2.9652", \ - "0.306275, 0.798252, 1.03454, 1.36326, 1.83016, 2.50546, 3.51282" \ + "0.0571428, 0.236288, 0.358772, 0.560981, 0.899751, 1.46363, 2.40448", \ + "0.0832838, 0.269501, 0.392506, 0.59515, 0.934285, 1.4985, 2.43909", \ + "0.101703, 0.302744, 0.426483, 0.629319, 0.968393, 1.53301, 2.47339", \ + "0.128065, 0.362824, 0.492722, 0.697559, 1.03638, 1.60097, 2.54201", \ + "0.166688, 0.458365, 0.607765, 0.82973, 1.17673, 1.74078, 2.68016", \ + "0.222943, 0.598115, 0.783268, 1.04512, 1.43144, 2.02012, 2.96516", \ + "0.306274, 0.798252, 1.03454, 1.36326, 1.83016, 2.50546, 3.51281" \ ); } fall_transition (TIMING_DELAY_7x7ds1) { index_1 ("0.0186, 0.0966, 0.174, 0.3294, 0.6408, 1.263, 2.5074"); index_2 ("0.001, 0.0234, 0.039, 0.0648, 0.108, 0.18, 0.3"); values ( \ - "0.0509617, 0.28359, 0.445195, 0.712514, 1.15975, 1.90549, 3.14924", \ - "0.0627201, 0.284509, 0.445687, 0.712619, 1.16018, 1.9061, 3.14942", \ - "0.0761306, 0.292829, 0.449117, 0.717893, 1.16111, 1.90758, 3.14943", \ - "0.0995259, 0.321381, 0.469234, 0.722782, 1.16215, 1.90759, 3.15302", \ - "0.137112, 0.383214, 0.530993, 0.772133, 1.18928, 1.9128, 3.15303", \ - "0.196144, 0.496926, 0.653351, 0.901148, 1.30188, 1.98893, 3.18068", \ - "0.292766, 0.675132, 0.862223, 1.13865, 1.56025, 2.22967, 3.35924" \ + "0.050958, 0.283402, 0.444951, 0.712513, 1.16119, 1.90593, 3.14924", \ + "0.0627201, 0.284508, 0.445045, 0.712514, 1.1612, 1.90613, 3.14941", \ + "0.0761305, 0.292829, 0.449118, 0.717893, 1.16121, 1.90757, 3.14942", \ + "0.0995258, 0.32138, 0.469432, 0.722781, 1.16215, 1.90758, 3.153", \ + "0.137112, 0.383212, 0.530992, 0.772132, 1.18928, 1.9157, 3.15301", \ + "0.196144, 0.496925, 0.653351, 0.901148, 1.30175, 1.98892, 3.18092", \ + "0.292766, 0.675131, 0.862222, 1.13865, 1.56025, 2.22967, 3.35924" \ ); } } @@ -21682,52 +21756,52 @@ library (sg13g2_stdcell_typ_1p20V_25C) { index_1 ("0.0186, 0.0966, 0.174, 0.3294, 0.6408, 1.263, 2.5074"); index_2 ("0.001, 0.0234, 0.039, 0.0648, 0.108, 0.18, 0.3"); values ( \ - "0.0312434, 0.0946567, 0.137975, 0.210129, 0.329152, 0.528686, 0.860693", \ - "0.059887, 0.138172, 0.182566, 0.254297, 0.374038, 0.57377, 0.905449", \ - "0.0758231, 0.173476, 0.222421, 0.296577, 0.416669, 0.615867, 0.947887", \ + "0.0312458, 0.0946726, 0.137974, 0.209558, 0.329104, 0.528683, 0.860583", \ + "0.0599621, 0.138172, 0.182562, 0.254309, 0.374, 0.573947, 0.905433", \ + "0.0758231, 0.173476, 0.222426, 0.296568, 0.416589, 0.615832, 0.947899", \ "0.0962333, 0.228698, 0.289446, 0.3749, 0.502147, 0.703886, 1.03609", \ - "0.121581, 0.309181, 0.391028, 0.501839, 0.654373, 0.874783, 1.21514", \ + "0.121581, 0.309181, 0.391028, 0.501839, 0.654373, 0.874783, 1.21511", \ "0.147528, 0.412491, 0.529128, 0.678987, 0.884307, 1.15649, 1.54115", \ - "0.16614, 0.536214, 0.705146, 0.924847, 1.20701, 1.57712, 2.06782" \ + "0.166141, 0.536214, 0.705146, 0.924847, 1.20701, 1.57712, 2.06782" \ ); } rise_transition (TIMING_DELAY_7x7ds1) { index_1 ("0.0186, 0.0966, 0.174, 0.3294, 0.6408, 1.263, 2.5074"); index_2 ("0.001, 0.0234, 0.039, 0.0648, 0.108, 0.18, 0.3"); values ( \ - "0.0227135, 0.112481, 0.175236, 0.279571, 0.452896, 0.742366, 1.22469", \ - "0.0395483, 0.120188, 0.178971, 0.280086, 0.453177, 0.742664, 1.2247", \ - "0.0543678, 0.137353, 0.192449, 0.287867, 0.455275, 0.742676, 1.22471", \ - "0.0785131, 0.176069, 0.230234, 0.320107, 0.476444, 0.751223, 1.22654", \ - "0.117622, 0.246872, 0.307419, 0.398149, 0.547735, 0.802258, 1.25183", \ - "0.17681, 0.363734, 0.438737, 0.54702, 0.701821, 0.95299, 1.36758", \ - "0.270195, 0.543153, 0.65403, 0.791144, 0.983697, 1.25706, 1.67888" \ + "0.0227132, 0.112481, 0.175236, 0.278976, 0.45264, 0.742372, 1.22463", \ + "0.0394987, 0.120204, 0.178974, 0.280123, 0.453593, 0.743263, 1.22464", \ + "0.0543679, 0.137353, 0.192471, 0.287866, 0.45528, 0.743264, 1.22465", \ + "0.0785131, 0.176069, 0.230234, 0.320107, 0.476445, 0.751223, 1.22654", \ + "0.117622, 0.24665, 0.307419, 0.398149, 0.547735, 0.802258, 1.25149", \ + "0.17681, 0.363734, 0.438737, 0.54702, 0.701821, 0.952991, 1.36758", \ + "0.270195, 0.543153, 0.65403, 0.791145, 0.983697, 1.25706, 1.67888" \ ); } cell_fall (TIMING_DELAY_7x7ds1) { index_1 ("0.0186, 0.0966, 0.174, 0.3294, 0.6408, 1.263, 2.5074"); index_2 ("0.001, 0.0234, 0.039, 0.0648, 0.108, 0.18, 0.3"); values ( \ - "0.0712232, 0.249198, 0.371532, 0.573904, 0.912287, 1.4768, 2.41725", \ - "0.0971045, 0.281225, 0.404159, 0.607289, 0.945852, 1.51009, 2.45048", \ - "0.115536, 0.311595, 0.435433, 0.638403, 0.97753, 1.54208, 2.48256", \ - "0.142168, 0.366828, 0.495835, 0.701153, 1.0408, 1.60588, 2.54714", \ - "0.179651, 0.458491, 0.602686, 0.821321, 1.16821, 1.73442, 2.67545", \ - "0.235331, 0.597597, 0.774187, 1.02576, 1.4034, 1.98936, 2.93715", \ - "0.322433, 0.80121, 1.02814, 1.34115, 1.78887, 2.44142, 3.4374" \ + "0.0712089, 0.249197, 0.371552, 0.573903, 0.912285, 1.47641, 2.41725", \ + "0.0971044, 0.281225, 0.404134, 0.606985, 0.945845, 1.51009, 2.45064", \ + "0.115536, 0.311597, 0.435432, 0.638402, 0.97741, 1.54207, 2.48254", \ + "0.142168, 0.366828, 0.495835, 0.701152, 1.0408, 1.60566, 2.54717", \ + "0.17965, 0.458491, 0.602686, 0.821419, 1.16821, 1.73441, 2.67534", \ + "0.23533, 0.597596, 0.774187, 1.02576, 1.4034, 1.98936, 2.93717", \ + "0.322433, 0.80121, 1.02814, 1.34115, 1.78886, 2.44142, 3.43739" \ ); } fall_transition (TIMING_DELAY_7x7ds1) { index_1 ("0.0186, 0.0966, 0.174, 0.3294, 0.6408, 1.263, 2.5074"); index_2 ("0.001, 0.0234, 0.039, 0.0648, 0.108, 0.18, 0.3"); values ( \ - "0.0510464, 0.2836, 0.445203, 0.712276, 1.16007, 1.90542, 3.1483", \ - "0.0591796, 0.28434, 0.445371, 0.712545, 1.16008, 1.90612, 3.14942", \ - "0.0702152, 0.289871, 0.447717, 0.715534, 1.16115, 1.90786, 3.14943", \ - "0.0919491, 0.310603, 0.461923, 0.719623, 1.16172, 1.90787, 3.1532", \ - "0.130984, 0.35988, 0.50787, 0.754616, 1.18036, 1.91355, 3.15321", \ - "0.192954, 0.457823, 0.609261, 0.854755, 1.26197, 1.96361, 3.16938", \ - "0.286073, 0.623015, 0.795169, 1.05563, 1.46801, 2.14337, 3.29641" \ + "0.0510579, 0.2836, 0.445206, 0.712275, 1.16006, 1.90722, 3.14925", \ + "0.0591795, 0.28434, 0.44537, 0.712681, 1.16007, 1.90723, 3.14942", \ + "0.0702153, 0.289863, 0.447717, 0.715532, 1.161, 1.90786, 3.14943", \ + "0.091949, 0.310603, 0.461923, 0.719622, 1.16174, 1.90787, 3.15319", \ + "0.130984, 0.35988, 0.507871, 0.754791, 1.18035, 1.91355, 3.1532", \ + "0.192953, 0.457823, 0.609262, 0.854754, 1.26197, 1.9636, 3.1694", \ + "0.286073, 0.623014, 0.795169, 1.05563, 1.46801, 2.14346, 3.29571" \ ); } } @@ -21739,12 +21813,12 @@ library (sg13g2_stdcell_typ_1p20V_25C) { index_1 ("0.0186, 0.0966, 0.174, 0.3294, 0.6408, 1.263, 2.5074"); index_2 ("0.001, 0.0234, 0.039, 0.0648, 0.108, 0.18, 0.3"); values ( \ - "0.0334166, 0.0978735, 0.141451, 0.213195, 0.33303, 0.532658, 0.864787", \ - "0.06469, 0.141592, 0.186053, 0.257934, 0.377684, 0.577769, 0.909488", \ - "0.0828102, 0.177369, 0.226036, 0.300052, 0.420269, 0.619504, 0.951674", \ - "0.107008, 0.234149, 0.294039, 0.379005, 0.506083, 0.707777, 1.04007", \ - "0.137936, 0.317324, 0.397594, 0.507443, 0.659153, 0.87899, 1.21906", \ - "0.172154, 0.42507, 0.538469, 0.687246, 0.890213, 1.16166, 1.54586", \ + "0.0334166, 0.0978488, 0.141445, 0.213208, 0.333018, 0.532647, 0.864761", \ + "0.0646901, 0.141603, 0.186047, 0.257946, 0.377852, 0.577762, 0.909508", \ + "0.0828102, 0.177369, 0.226036, 0.300051, 0.42022, 0.619558, 0.951869", \ + "0.107008, 0.234149, 0.294039, 0.378974, 0.506083, 0.707777, 1.04037", \ + "0.137936, 0.317324, 0.397594, 0.507443, 0.659177, 0.87899, 1.21906", \ + "0.172153, 0.42507, 0.538469, 0.687246, 0.890213, 1.16166, 1.54586", \ "0.203411, 0.556403, 0.721072, 0.936954, 1.21613, 1.58419, 2.07381" \ ); } @@ -21752,39 +21826,39 @@ library (sg13g2_stdcell_typ_1p20V_25C) { index_1 ("0.0186, 0.0966, 0.174, 0.3294, 0.6408, 1.263, 2.5074"); index_2 ("0.001, 0.0234, 0.039, 0.0648, 0.108, 0.18, 0.3"); values ( \ - "0.0258806, 0.116269, 0.17891, 0.282823, 0.456673, 0.746362, 1.22875", \ - "0.0416926, 0.12329, 0.1824, 0.283808, 0.456809, 0.747133, 1.22918", \ - "0.0569188, 0.140171, 0.195526, 0.29136, 0.459048, 0.748208, 1.22919", \ - "0.0816226, 0.178517, 0.233085, 0.323215, 0.479908, 0.755271, 1.23069", \ - "0.12163, 0.249409, 0.309523, 0.401057, 0.550524, 0.805836, 1.25544", \ - "0.181608, 0.365188, 0.44166, 0.549334, 0.705209, 0.956598, 1.37147", \ - "0.275143, 0.54569, 0.65491, 0.793558, 0.986261, 1.25931, 1.68346" \ + "0.0258806, 0.116554, 0.178919, 0.282824, 0.456674, 0.746364, 1.22875", \ + "0.0416927, 0.123289, 0.182394, 0.283822, 0.456879, 0.747117, 1.22918", \ + "0.0569187, 0.140171, 0.195526, 0.291323, 0.458998, 0.747118, 1.22919", \ + "0.0816226, 0.178517, 0.233071, 0.323199, 0.479908, 0.755271, 1.23077", \ + "0.12163, 0.249409, 0.309523, 0.401057, 0.550551, 0.805836, 1.25544", \ + "0.181464, 0.365188, 0.44166, 0.549334, 0.705209, 0.956598, 1.37147", \ + "0.275142, 0.54569, 0.65491, 0.793558, 0.986261, 1.25931, 1.68346" \ ); } cell_fall (TIMING_DELAY_7x7ds1) { index_1 ("0.0186, 0.0966, 0.174, 0.3294, 0.6408, 1.263, 2.5074"); index_2 ("0.001, 0.0234, 0.039, 0.0648, 0.108, 0.18, 0.3"); values ( \ - "0.0791897, 0.257114, 0.379621, 0.581898, 0.920276, 1.48483, 2.42468", \ - "0.10484, 0.287102, 0.410026, 0.612881, 0.951772, 1.51633, 2.45636", \ - "0.122763, 0.31317, 0.436788, 0.639716, 0.978718, 1.5433, 2.48382", \ - "0.149237, 0.359991, 0.487556, 0.692292, 1.03187, 1.59691, 2.53813", \ - "0.184844, 0.43981, 0.57861, 0.793643, 1.13878, 1.70466, 2.64554", \ - "0.231357, 0.56474, 0.728882, 0.968928, 1.3381, 1.91894, 2.86522", \ - "0.305536, 0.750595, 0.96008, 1.24848, 1.67121, 2.30329, 3.28792" \ + "0.0791875, 0.257112, 0.379619, 0.581896, 0.920276, 1.48483, 2.4252", \ + "0.104859, 0.287115, 0.410026, 0.613095, 0.951774, 1.51633, 2.45635", \ + "0.122763, 0.31317, 0.436766, 0.639715, 0.978717, 1.54329, 2.48381", \ + "0.149237, 0.359991, 0.487552, 0.692298, 1.03187, 1.59666, 2.53813", \ + "0.184844, 0.439808, 0.578611, 0.793642, 1.13877, 1.70465, 2.64553", \ + "0.231357, 0.56474, 0.728882, 0.968927, 1.33809, 1.91894, 2.86518", \ + "0.305536, 0.750595, 0.960079, 1.24848, 1.67121, 2.30329, 3.28792" \ ); } fall_transition (TIMING_DELAY_7x7ds1) { index_1 ("0.0186, 0.0966, 0.174, 0.3294, 0.6408, 1.263, 2.5074"); index_2 ("0.001, 0.0234, 0.039, 0.0648, 0.108, 0.18, 0.3"); values ( \ - "0.0510451, 0.28355, 0.445219, 0.712134, 1.16014, 1.90502, 3.14981", \ - "0.0563602, 0.284308, 0.445271, 0.712543, 1.16015, 1.90505, 3.14982", \ - "0.0641002, 0.288187, 0.447356, 0.716077, 1.16108, 1.90614, 3.14983", \ - "0.081224, 0.303564, 0.457636, 0.717998, 1.16143, 1.90615, 3.15303", \ - "0.116887, 0.341902, 0.493485, 0.744968, 1.17624, 1.90973, 3.15304", \ - "0.18196, 0.424767, 0.574334, 0.82284, 1.24056, 1.95169, 3.16592", \ - "0.280948, 0.583021, 0.739182, 0.98901, 1.4006, 2.09507, 3.26482" \ + "0.0510407, 0.28355, 0.445219, 0.712133, 1.15947, 1.90498, 3.14815", \ + "0.0563605, 0.28405, 0.445267, 0.713564, 1.15997, 1.90505, 3.14942", \ + "0.0641002, 0.288187, 0.446999, 0.716076, 1.16108, 1.90614, 3.14943", \ + "0.0812239, 0.303563, 0.457713, 0.71795, 1.16143, 1.9077, 3.15305", \ + "0.116887, 0.341903, 0.493485, 0.744983, 1.17627, 1.90968, 3.15306", \ + "0.18196, 0.424766, 0.574333, 0.82284, 1.24056, 1.95169, 3.16888", \ + "0.280947, 0.583021, 0.739181, 0.989009, 1.4006, 2.09506, 3.26481" \ ); } } @@ -21796,12 +21870,12 @@ library (sg13g2_stdcell_typ_1p20V_25C) { index_1 ("0.0186, 0.0966, 0.174, 0.3294, 0.6408, 1.263, 2.5074"); index_2 ("0.001, 0.0234, 0.039, 0.0648, 0.108, 0.18, 0.3"); values ( \ - "0.0341768, 0.100116, 0.144279, 0.215922, 0.335954, 0.535494, 0.867365", \ - "0.0675785, 0.143957, 0.188561, 0.260605, 0.380482, 0.580152, 0.911983", \ - "0.0875561, 0.180406, 0.228904, 0.302921, 0.423152, 0.622513, 0.954425", \ + "0.0341984, 0.100109, 0.144286, 0.21595, 0.335947, 0.535491, 0.867341", \ + "0.0675785, 0.143957, 0.188561, 0.260626, 0.380457, 0.580147, 0.911933", \ + "0.0875561, 0.180406, 0.228904, 0.302937, 0.423145, 0.622388, 0.954557", \ "0.114669, 0.238489, 0.297781, 0.382214, 0.509177, 0.710683, 1.04267", \ - "0.150398, 0.323961, 0.403129, 0.511877, 0.66282, 0.881918, 1.22168", \ - "0.191884, 0.435827, 0.548341, 0.695211, 0.89544, 1.16492, 1.54821", \ + "0.150398, 0.323961, 0.403129, 0.511877, 0.662822, 0.881918, 1.22176", \ + "0.191884, 0.435827, 0.548341, 0.695211, 0.895439, 1.16493, 1.54821", \ "0.234669, 0.573732, 0.735272, 0.947858, 1.22359, 1.58963, 2.07837" \ ); } @@ -21809,12 +21883,12 @@ library (sg13g2_stdcell_typ_1p20V_25C) { index_1 ("0.0186, 0.0966, 0.174, 0.3294, 0.6408, 1.263, 2.5074"); index_2 ("0.001, 0.0234, 0.039, 0.0648, 0.108, 0.18, 0.3"); values ( \ - "0.0286512, 0.119344, 0.182484, 0.2859, 0.459574, 0.748813, 1.23087", \ - "0.0438816, 0.126218, 0.185447, 0.287006, 0.460282, 0.749308, 1.23124", \ - "0.059224, 0.142709, 0.198366, 0.294331, 0.462073, 0.749309, 1.23125", \ - "0.0845221, 0.18085, 0.23516, 0.325675, 0.482839, 0.757927, 1.23231", \ - "0.125513, 0.251335, 0.311599, 0.403424, 0.552957, 0.808, 1.25746", \ - "0.186951, 0.367262, 0.44205, 0.549806, 0.707534, 0.958689, 1.37313", \ + "0.0286281, 0.119344, 0.182481, 0.285866, 0.459574, 0.748813, 1.23087", \ + "0.0438816, 0.1262, 0.185447, 0.286784, 0.462036, 0.749308, 1.23123", \ + "0.059224, 0.142705, 0.198366, 0.294347, 0.462133, 0.750613, 1.23124", \ + "0.0845221, 0.18085, 0.23516, 0.325675, 0.482839, 0.757927, 1.23232", \ + "0.125513, 0.251335, 0.311599, 0.403424, 0.552843, 0.808, 1.25754", \ + "0.186951, 0.367262, 0.44205, 0.549806, 0.707655, 0.958755, 1.37313", \ "0.2809, 0.549046, 0.65717, 0.794568, 0.987237, 1.26154, 1.68482" \ ); } @@ -21822,26 +21896,26 @@ library (sg13g2_stdcell_typ_1p20V_25C) { index_1 ("0.0186, 0.0966, 0.174, 0.3294, 0.6408, 1.263, 2.5074"); index_2 ("0.001, 0.0234, 0.039, 0.0648, 0.108, 0.18, 0.3"); values ( \ - "0.0829563, 0.26089, 0.383439, 0.585524, 0.924268, 1.4886, 2.429", \ - "0.108794, 0.289985, 0.412895, 0.615797, 0.954387, 1.51909, 2.45905", \ - "0.1265, 0.313436, 0.436884, 0.639755, 0.978807, 1.54337, 2.48389", \ - "0.15249, 0.354015, 0.480567, 0.684932, 1.02435, 1.58912, 2.53059", \ - "0.187634, 0.422377, 0.557601, 0.77073, 1.11463, 1.68012, 2.62139", \ - "0.228723, 0.531543, 0.685669, 0.918641, 1.28188, 1.86062, 2.80524", \ - "0.284925, 0.693449, 0.885356, 1.15815, 1.56272, 2.18255, 3.1595" \ + "0.0829586, 0.260885, 0.383436, 0.585521, 0.924264, 1.48817, 2.42899", \ + "0.108787, 0.289995, 0.412894, 0.615791, 0.954642, 1.51878, 2.45906", \ + "0.1265, 0.313435, 0.436852, 0.639799, 0.978801, 1.54337, 2.48388", \ + "0.15249, 0.354015, 0.480566, 0.684931, 1.0243, 1.58916, 2.53091", \ + "0.187634, 0.422376, 0.557601, 0.77073, 1.11463, 1.68011, 2.62137", \ + "0.228723, 0.531542, 0.685669, 0.91864, 1.28187, 1.86062, 2.80524", \ + "0.284925, 0.693448, 0.885355, 1.15815, 1.56271, 2.18241, 3.15966" \ ); } fall_transition (TIMING_DELAY_7x7ds1) { index_1 ("0.0186, 0.0966, 0.174, 0.3294, 0.6408, 1.263, 2.5074"); index_2 ("0.001, 0.0234, 0.039, 0.0648, 0.108, 0.18, 0.3"); values ( \ - "0.0510442, 0.283546, 0.445156, 0.712555, 1.16006, 1.90603, 3.14925", \ - "0.0545195, 0.28412, 0.445523, 0.712726, 1.16019, 1.90604, 3.14939", \ - "0.0599323, 0.28677, 0.446504, 0.714687, 1.16109, 1.90615, 3.14942", \ - "0.071918, 0.299002, 0.454976, 0.716747, 1.16114, 1.90828, 3.15234", \ - "0.0997159, 0.329064, 0.48323, 0.739011, 1.1732, 1.91202, 3.15235", \ - "0.159117, 0.395833, 0.549176, 0.801201, 1.22665, 1.94368, 3.1628", \ - "0.262997, 0.53409, 0.68685, 0.940851, 1.35689, 2.06348, 3.24747" \ + "0.0510385, 0.283545, 0.445156, 0.712554, 1.16006, 1.90602, 3.14925", \ + "0.0545138, 0.284105, 0.44543, 0.71272, 1.16007, 1.90631, 3.14934", \ + "0.0599322, 0.28677, 0.446959, 0.715413, 1.16109, 1.90632, 3.14941", \ + "0.071918, 0.299001, 0.454975, 0.716746, 1.1611, 1.90836, 3.15075", \ + "0.0997157, 0.329062, 0.48323, 0.73901, 1.17356, 1.90901, 3.15076", \ + "0.159116, 0.395833, 0.549176, 0.801201, 1.22665, 1.94367, 3.16279", \ + "0.262997, 0.534089, 0.686849, 0.94085, 1.35688, 2.06383, 3.24731" \ ); } } @@ -21851,26 +21925,26 @@ library (sg13g2_stdcell_typ_1p20V_25C) { index_1 ("0.0186, 0.0966, 0.174, 0.3294, 0.6408, 1.263, 2.5074"); index_2 ("0.001, 0.0234, 0.039, 0.0648, 0.108, 0.18, 0.3"); values ( \ - "0.00189236, 0.00218989, 0.00217539, 0.00213148, 0.00200503, 0.00182802, 0.00147835", \ - "0.00166701, 0.00206513, 0.0021135, 0.00211036, 0.00210987, 0.00183217, 0.00152555", \ - "0.00175599, 0.00195729, 0.00205079, 0.00205355, 0.00215179, 0.00214165, 0.00151281", \ - "0.00204904, 0.00200222, 0.00199265, 0.00200805, 0.00222018, 0.00177801, 0.00143794", \ - "0.00290277, 0.00227436, 0.00222695, 0.00218536, 0.00204815, 0.00217074, 0.00148307", \ - "0.0048605, 0.00342222, 0.00311556, 0.00283122, 0.00264996, 0.0021604, 0.00201521", \ - "0.00912343, 0.00648932, 0.00568496, 0.00496938, 0.00420997, 0.0037265, 0.00290638" \ + "0.00189245, 0.0021903, 0.00217612, 0.00213526, 0.00201351, 0.00183338, 0.00149274", \ + "0.00166701, 0.00206466, 0.00212671, 0.00212317, 0.00202073, 0.00185183, 0.00155903", \ + "0.00175584, 0.00195594, 0.00205025, 0.00205356, 0.00216005, 0.0018912, 0.00148441", \ + "0.00204901, 0.00200221, 0.00199265, 0.00200806, 0.00222018, 0.00178003, 0.00156517", \ + "0.00290288, 0.00227436, 0.00222695, 0.00218534, 0.00204815, 0.00217074, 0.00147703", \ + "0.00486015, 0.00342222, 0.00311555, 0.00283122, 0.00264996, 0.0021604, 0.00201521", \ + "0.0091236, 0.00648932, 0.00568477, 0.00496962, 0.00420934, 0.00372841, 0.00290644" \ ); } fall_power (POWER_7x7ds1) { index_1 ("0.0186, 0.0966, 0.174, 0.3294, 0.6408, 1.263, 2.5074"); index_2 ("0.001, 0.0234, 0.039, 0.0648, 0.108, 0.18, 0.3"); values ( \ - "0.00440864, 0.00467214, 0.00466003, 0.00460766, 0.00450569, 0.00429703, 0.00400515", \ - "0.00412301, 0.00447956, 0.0045038, 0.00450722, 0.00443587, 0.00427329, 0.00401675", \ - "0.00418884, 0.00440683, 0.00441287, 0.00460194, 0.004407, 0.00425438, 0.00402257", \ - "0.00447663, 0.00431906, 0.00439868, 0.00436881, 0.00440735, 0.00418201, 0.00403222", \ - "0.00522088, 0.00467912, 0.00456463, 0.00446938, 0.00447516, 0.0043458, 0.00399364", \ - "0.0070512, 0.00581314, 0.00547766, 0.00512468, 0.00477334, 0.00465695, 0.00418215", \ - "0.0111913, 0.00865269, 0.00790256, 0.00723724, 0.00652129, 0.00561628, 0.00522479" \ + "0.00440301, 0.00466928, 0.00465398, 0.00460771, 0.0045131, 0.00432338, 0.00400565", \ + "0.00412327, 0.00446241, 0.00448544, 0.00449658, 0.00442761, 0.0042746, 0.00401647", \ + "0.0041889, 0.00440796, 0.00441292, 0.00460196, 0.004407, 0.00426069, 0.00402257", \ + "0.00447694, 0.0043191, 0.00439807, 0.00436886, 0.00440734, 0.00418201, 0.00402857", \ + "0.0052202, 0.00467492, 0.00456503, 0.00446938, 0.00447485, 0.0047625, 0.00399353", \ + "0.00705213, 0.00581326, 0.00547683, 0.0051258, 0.00477, 0.0046523, 0.0044414", \ + "0.0111912, 0.00865296, 0.00790309, 0.0072376, 0.00651506, 0.00555719, 0.00522679" \ ); } } @@ -21880,26 +21954,26 @@ library (sg13g2_stdcell_typ_1p20V_25C) { index_1 ("0.0186, 0.0966, 0.174, 0.3294, 0.6408, 1.263, 2.5074"); index_2 ("0.001, 0.0234, 0.039, 0.0648, 0.108, 0.18, 0.3"); values ( \ - "0.00215153, 0.00225327, 0.00222093, 0.0022294, 0.00205987, 0.00187676, 0.00145691", \ - "0.00187923, 0.00214958, 0.00214451, 0.00211296, 0.00206055, 0.00189616, 0.00149289", \ - "0.00189838, 0.00206634, 0.00212183, 0.00209233, 0.00215547, 0.00187727, 0.00148623", \ - "0.00222435, 0.00211214, 0.0020955, 0.00206035, 0.00217521, 0.00199982, 0.00147278", \ - "0.00296674, 0.00240719, 0.00235025, 0.00225223, 0.00206, 0.00222738, 0.0015612", \ - "0.0047944, 0.00359956, 0.00332605, 0.00300541, 0.00269635, 0.00216135, 0.00206026", \ - "0.00869024, 0.00666015, 0.00580346, 0.00510573, 0.0043485, 0.00371361, 0.00274153" \ + "0.0021519, 0.00225469, 0.00222115, 0.00215351, 0.00203956, 0.00186157, 0.00146723", \ + "0.00187554, 0.00215129, 0.00214183, 0.00217406, 0.00208653, 0.00194661, 0.00149063", \ + "0.00189744, 0.00206544, 0.00212554, 0.00207307, 0.00200141, 0.00185079, 0.00149371", \ + "0.00222435, 0.00211214, 0.00209551, 0.00206035, 0.00222911, 0.00199982, 0.00147278", \ + "0.00296674, 0.0024025, 0.00235025, 0.00225171, 0.00206, 0.0022272, 0.00152158", \ + "0.0047944, 0.00359956, 0.00332605, 0.00300542, 0.00269635, 0.0021706, 0.00204472", \ + "0.00869048, 0.00666007, 0.00580346, 0.00510522, 0.0043485, 0.00371361, 0.00274159" \ ); } fall_power (POWER_7x7ds1) { index_1 ("0.0186, 0.0966, 0.174, 0.3294, 0.6408, 1.263, 2.5074"); index_2 ("0.001, 0.0234, 0.039, 0.0648, 0.108, 0.18, 0.3"); values ( \ - "0.00616887, 0.00632938, 0.00630518, 0.00624868, 0.00614424, 0.00592171, 0.00567633", \ - "0.00587099, 0.00616129, 0.00617714, 0.00617269, 0.00608044, 0.00591751, 0.00566439", \ - "0.00582135, 0.00608719, 0.00609395, 0.00619291, 0.00606681, 0.00592665, 0.00565487", \ - "0.00586897, 0.0059581, 0.00606026, 0.00600528, 0.00604797, 0.00582564, 0.00571244", \ - "0.00629468, 0.00611587, 0.00607249, 0.00606916, 0.0061007, 0.00642197, 0.00558896", \ - "0.00778558, 0.00683841, 0.00667984, 0.00649541, 0.00623582, 0.0064191, 0.00593176", \ - "0.0114654, 0.00915692, 0.0085652, 0.00807182, 0.00758405, 0.00679864, 0.00660706" \ + "0.00618008, 0.00632954, 0.00630808, 0.00624885, 0.00614454, 0.00598446, 0.00564445", \ + "0.00587142, 0.00616129, 0.0061763, 0.00617835, 0.00608045, 0.00591745, 0.00567209", \ + "0.0058179, 0.00610675, 0.00609962, 0.0061929, 0.00606265, 0.00592666, 0.00565434", \ + "0.00586897, 0.00595814, 0.00605513, 0.00600528, 0.00604787, 0.00593637, 0.00573901", \ + "0.00629469, 0.00611586, 0.00606229, 0.0060535, 0.00602977, 0.00642197, 0.0056436", \ + "0.00778547, 0.00683884, 0.00667992, 0.00649731, 0.00623576, 0.00641573, 0.00597174", \ + "0.0114655, 0.00915667, 0.00856667, 0.00807148, 0.00757931, 0.00680537, 0.00658242" \ ); } } @@ -21909,26 +21983,26 @@ library (sg13g2_stdcell_typ_1p20V_25C) { index_1 ("0.0186, 0.0966, 0.174, 0.3294, 0.6408, 1.263, 2.5074"); index_2 ("0.001, 0.0234, 0.039, 0.0648, 0.108, 0.18, 0.3"); values ( \ - "0.00242394, 0.0024444, 0.00239237, 0.00232571, 0.0022026, 0.00202514, 0.00163071", \ - "0.00214102, 0.00231369, 0.00228983, 0.00234245, 0.00218109, 0.00204466, 0.00164708", \ - "0.00215973, 0.00223872, 0.002283, 0.00220267, 0.0023341, 0.00211697, 0.0016034", \ - "0.00239285, 0.00232008, 0.00226029, 0.00222331, 0.0022775, 0.00215211, 0.00160347", \ - "0.00312553, 0.00264538, 0.00255474, 0.00244232, 0.00222978, 0.00234901, 0.00168932", \ - "0.00493411, 0.00383657, 0.00359317, 0.00323888, 0.00288515, 0.00235306, 0.00221096", \ - "0.00893954, 0.00687576, 0.00610021, 0.00537028, 0.0046394, 0.00388558, 0.00295918" \ + "0.00242388, 0.00247317, 0.00239279, 0.00232706, 0.00220246, 0.00202075, 0.00162762", \ + "0.00214251, 0.00231524, 0.00228612, 0.00234297, 0.00217293, 0.00206473, 0.00164458", \ + "0.00215969, 0.00223873, 0.00228299, 0.00222505, 0.00236704, 0.00195113, 0.00160992", \ + "0.00239285, 0.00232007, 0.00226345, 0.00222112, 0.00227326, 0.00215211, 0.00162378", \ + "0.003125, 0.00264537, 0.00255386, 0.0024423, 0.00221618, 0.00235002, 0.00168932", \ + "0.00493423, 0.00383657, 0.00359318, 0.00323888, 0.00288509, 0.00235277, 0.00221102", \ + "0.00893982, 0.00687577, 0.00610005, 0.00537033, 0.0046394, 0.00388558, 0.00295918" \ ); } fall_power (POWER_7x7ds1) { index_1 ("0.0186, 0.0966, 0.174, 0.3294, 0.6408, 1.263, 2.5074"); index_2 ("0.001, 0.0234, 0.039, 0.0648, 0.108, 0.18, 0.3"); values ( \ - "0.00767212, 0.00782925, 0.00781202, 0.00774168, 0.0076524, 0.00742213, 0.00719298", \ - "0.00736716, 0.00765037, 0.00767743, 0.00767376, 0.00759069, 0.00739148, 0.00717162", \ - "0.00730834, 0.00757951, 0.00761151, 0.00770363, 0.00756098, 0.00737482, 0.00715999", \ - "0.00729194, 0.0074389, 0.00754217, 0.00752224, 0.00750716, 0.00733893, 0.0071915", \ - "0.00754485, 0.00753665, 0.00750721, 0.00752947, 0.00762552, 0.00750253, 0.00711589", \ - "0.00876029, 0.00805934, 0.00794913, 0.00780806, 0.00765213, 0.00774191, 0.0074722", \ - "0.0123701, 0.0102465, 0.00966789, 0.00923861, 0.00879693, 0.00822561, 0.00805114" \ + "0.00767714, 0.00782674, 0.00781261, 0.00774125, 0.00764158, 0.00742196, 0.00718896", \ + "0.00736367, 0.00765651, 0.00767722, 0.00769569, 0.00760005, 0.00739119, 0.00717492", \ + "0.00730758, 0.00757951, 0.00759037, 0.00770363, 0.00756098, 0.00737472, 0.00716036", \ + "0.00729193, 0.00744069, 0.00754259, 0.00752212, 0.00749501, 0.00743529, 0.00719205", \ + "0.0075452, 0.00753655, 0.00750718, 0.00752218, 0.00757037, 0.00791475, 0.00711532", \ + "0.00875984, 0.00805955, 0.00794644, 0.00780792, 0.00765687, 0.00774191, 0.00759353", \ + "0.0123701, 0.010247, 0.00966775, 0.00923548, 0.00879688, 0.00822567, 0.0080655" \ ); } } @@ -21938,26 +22012,26 @@ library (sg13g2_stdcell_typ_1p20V_25C) { index_1 ("0.0186, 0.0966, 0.174, 0.3294, 0.6408, 1.263, 2.5074"); index_2 ("0.001, 0.0234, 0.039, 0.0648, 0.108, 0.18, 0.3"); values ( \ - "0.00263713, 0.00259477, 0.00259175, 0.00248575, 0.00237409, 0.00217589, 0.00179841", \ - "0.00240867, 0.00250077, 0.00244315, 0.00251677, 0.00235515, 0.00214045, 0.00177969", \ - "0.00243424, 0.00243788, 0.00246648, 0.00236981, 0.00256209, 0.00206621, 0.00173699", \ - "0.00267357, 0.00255702, 0.00246858, 0.00240192, 0.00238473, 0.00232403, 0.00169716", \ - "0.00337148, 0.00289587, 0.00278819, 0.00268199, 0.00240124, 0.00242316, 0.00174848", \ - "0.00521028, 0.00411472, 0.00373817, 0.00340876, 0.0031211, 0.00253365, 0.00236651", \ - "0.00926226, 0.00726052, 0.00641875, 0.00569366, 0.0048835, 0.00410582, 0.00323899" \ + "0.0026316, 0.00259423, 0.00258968, 0.0024816, 0.00237414, 0.00216588, 0.00179493", \ + "0.00240861, 0.00250082, 0.00244263, 0.0025033, 0.0025085, 0.00212898, 0.00177641", \ + "0.00243593, 0.00244477, 0.00246646, 0.00237053, 0.00227437, 0.00224032, 0.00177475", \ + "0.00267357, 0.00255701, 0.00246858, 0.00241683, 0.00238667, 0.00232403, 0.00169753", \ + "0.00337148, 0.00289587, 0.00278898, 0.00268199, 0.00238816, 0.00242316, 0.00191228", \ + "0.00520964, 0.00411472, 0.00373825, 0.00340868, 0.00313183, 0.00252924, 0.00236651", \ + "0.00926234, 0.00726051, 0.00641875, 0.00569368, 0.004883, 0.00410582, 0.00323899" \ ); } fall_power (POWER_7x7ds1) { index_1 ("0.0186, 0.0966, 0.174, 0.3294, 0.6408, 1.263, 2.5074"); index_2 ("0.001, 0.0234, 0.039, 0.0648, 0.108, 0.18, 0.3"); values ( \ - "0.00911279, 0.00926811, 0.00924644, 0.00918968, 0.0090857, 0.00889599, 0.00861815", \ - "0.00881376, 0.00909054, 0.00913253, 0.00911706, 0.00902474, 0.00882986, 0.00864015", \ - "0.00874536, 0.00905755, 0.00903929, 0.00910229, 0.00900138, 0.00881296, 0.00860567", \ - "0.00869939, 0.00886362, 0.00897479, 0.00896101, 0.00895186, 0.00881435, 0.00863113", \ - "0.00886208, 0.00893528, 0.00891629, 0.00895855, 0.00892062, 0.00931517, 0.00856607", \ - "0.00985595, 0.00935349, 0.00930055, 0.00921468, 0.00903441, 0.00901508, 0.00868735", \ - "0.0132843, 0.0113157, 0.0108565, 0.0105419, 0.0101028, 0.00961603, 0.00940876" \ + "0.00911023, 0.00926777, 0.00924595, 0.00918793, 0.00908063, 0.0088929, 0.00862023", \ + "0.00881051, 0.00909332, 0.00912763, 0.00911726, 0.00900953, 0.00885162, 0.00859385", \ + "0.00874554, 0.00901384, 0.00904856, 0.00913198, 0.00900189, 0.00881303, 0.00860573", \ + "0.00869892, 0.00886361, 0.00897492, 0.008961, 0.00895424, 0.00881833, 0.00865938", \ + "0.00886209, 0.00893524, 0.00892449, 0.00895856, 0.00898565, 0.00924856, 0.00856607", \ + "0.00985582, 0.00935412, 0.00929638, 0.00920839, 0.0089815, 0.00911608, 0.00867029", \ + "0.0132843, 0.0113157, 0.0108563, 0.0105416, 0.0101159, 0.00961638, 0.00932906" \ ); } } @@ -21967,36 +22041,36 @@ library (sg13g2_stdcell_typ_1p20V_25C) { max_transition : 2.5074; capacitance : 0.00287103; rise_capacitance : 0.00290247; - rise_capacitance_range (0.00290247, 0.00290247); + rise_capacitance_range (0.00262315, 0.00309088); fall_capacitance : 0.00283958; - fall_capacitance_range (0.00283958, 0.00283958); + fall_capacitance_range (0.0024383, 0.00335005); } pin (B) { direction : "input"; max_transition : 2.5074; - capacitance : 0.00301034; - rise_capacitance : 0.00310698; - rise_capacitance_range (0.00310698, 0.00310698); - fall_capacitance : 0.00291369; - fall_capacitance_range (0.00291369, 0.00291369); + capacitance : 0.00301029; + rise_capacitance : 0.00310699; + rise_capacitance_range (0.00269568, 0.00343381); + fall_capacitance : 0.0029136; + fall_capacitance_range (0.00260874, 0.00330725); } pin (C) { direction : "input"; max_transition : 2.5074; - capacitance : 0.00302907; - rise_capacitance : 0.00313842; - rise_capacitance_range (0.00313842, 0.00313842); - fall_capacitance : 0.00291972; - fall_capacitance_range (0.00291972, 0.00291972); + capacitance : 0.00302909; + rise_capacitance : 0.00313841; + rise_capacitance_range (0.00272902, 0.00348805); + fall_capacitance : 0.00291978; + fall_capacitance_range (0.00269937, 0.00323587); } pin (D) { direction : "input"; max_transition : 2.5074; - capacitance : 0.00299934; + capacitance : 0.00299933; rise_capacitance : 0.00312127; - rise_capacitance_range (0.00312127, 0.00312127); - fall_capacitance : 0.00287742; - fall_capacitance_range (0.00287742, 0.00287742); + rise_capacitance_range (0.00271512, 0.00345946); + fall_capacitance : 0.0028774; + fall_capacitance_range (0.00273673, 0.00312786); } } cell (sg13g2_nor2_1) { @@ -22202,18 +22276,18 @@ library (sg13g2_stdcell_typ_1p20V_25C) { max_transition : 2.5074; capacitance : 0.00304068; rise_capacitance : 0.00301218; - rise_capacitance_range (0.00301218, 0.00301218); + rise_capacitance_range (0.00276769, 0.00330083); fall_capacitance : 0.00306918; - fall_capacitance_range (0.00306918, 0.00306918); + fall_capacitance_range (0.00264116, 0.00344291); } pin (B) { direction : "input"; max_transition : 2.5074; capacitance : 0.00291906; rise_capacitance : 0.00299277; - rise_capacitance_range (0.00299277, 0.00299277); + rise_capacitance_range (0.00244461, 0.00344126); fall_capacitance : 0.00284534; - fall_capacitance_range (0.00284534, 0.00284534); + fall_capacitance_range (0.00257915, 0.00312528); } } cell (sg13g2_nor2_2) { @@ -22419,18 +22493,18 @@ library (sg13g2_stdcell_typ_1p20V_25C) { max_transition : 2.5074; capacitance : 0.00580332; rise_capacitance : 0.0057576; - rise_capacitance_range (0.0057576, 0.0057576); + rise_capacitance_range (0.0052249, 0.00633985); fall_capacitance : 0.00584904; - fall_capacitance_range (0.00584904, 0.00584904); + fall_capacitance_range (0.00504019, 0.00660367); } pin (B) { direction : "input"; max_transition : 2.5074; capacitance : 0.00560432; rise_capacitance : 0.00575112; - rise_capacitance_range (0.00575112, 0.00575112); + rise_capacitance_range (0.00453207, 0.00672898); fall_capacitance : 0.00545751; - fall_capacitance_range (0.00545751, 0.00545751); + fall_capacitance_range (0.00486475, 0.00606172); } } cell (sg13g2_nor2b_1) { @@ -22636,18 +22710,18 @@ library (sg13g2_stdcell_typ_1p20V_25C) { max_transition : 2.5074; capacitance : 0.00292348; rise_capacitance : 0.00299738; - rise_capacitance_range (0.00299738, 0.00299738); + rise_capacitance_range (0.00244784, 0.00344727); fall_capacitance : 0.00284958; - fall_capacitance_range (0.00284958, 0.00284958); + fall_capacitance_range (0.00258332, 0.00312982); } pin (B_N) { direction : "input"; max_transition : 2.5074; capacitance : 0.00226593; rise_capacitance : 0.00229613; - rise_capacitance_range (0.00229613, 0.00229613); + rise_capacitance_range (0.00207737, 0.00245487); fall_capacitance : 0.00223574; - fall_capacitance_range (0.00223574, 0.00223574); + fall_capacitance_range (0.00204518, 0.00241163); internal_power () { when : "A"; rise_power (passive_POWER_7x1ds1) { @@ -22882,18 +22956,18 @@ library (sg13g2_stdcell_typ_1p20V_25C) { max_transition : 2.5074; capacitance : 0.00567165; rise_capacitance : 0.00582798; - rise_capacitance_range (0.00582798, 0.00582798); + rise_capacitance_range (0.00462243, 0.00676554); fall_capacitance : 0.00551533; - fall_capacitance_range (0.00551533, 0.00551533); + fall_capacitance_range (0.00493985, 0.00615362); } pin (B_N) { direction : "input"; max_transition : 2.5074; capacitance : 0.00268047; rise_capacitance : 0.00272502; - rise_capacitance_range (0.00272502, 0.00272502); + rise_capacitance_range (0.0025098, 0.00289247); fall_capacitance : 0.00263592; - fall_capacitance_range (0.00263592, 0.00263592); + fall_capacitance_range (0.0024487, 0.00281601); internal_power () { when : "A"; rise_power (passive_POWER_7x1ds1) { @@ -23226,27 +23300,27 @@ library (sg13g2_stdcell_typ_1p20V_25C) { max_transition : 2.5074; capacitance : 0.00301098; rise_capacitance : 0.00297013; - rise_capacitance_range (0.00297013, 0.00297013); + rise_capacitance_range (0.00278711, 0.00324259); fall_capacitance : 0.00305182; - fall_capacitance_range (0.00305182, 0.00305182); + fall_capacitance_range (0.00264993, 0.0034288); } pin (B) { direction : "input"; max_transition : 2.5074; capacitance : 0.00302226; rise_capacitance : 0.00301265; - rise_capacitance_range (0.00301265, 0.00301265); + rise_capacitance_range (0.00264213, 0.00340149); fall_capacitance : 0.00303188; - fall_capacitance_range (0.00303188, 0.00303188); + fall_capacitance_range (0.00260651, 0.00337789); } pin (C) { direction : "input"; max_transition : 2.5074; capacitance : 0.00289876; rise_capacitance : 0.00297618; - rise_capacitance_range (0.00297618, 0.00297618); + rise_capacitance_range (0.00241437, 0.00351166); fall_capacitance : 0.00282134; - fall_capacitance_range (0.00282134, 0.00282134); + fall_capacitance_range (0.00256613, 0.00301768); } } cell (sg13g2_nor3_2) { @@ -23550,27 +23624,27 @@ library (sg13g2_stdcell_typ_1p20V_25C) { max_transition : 2.5074; capacitance : 0.00575969; rise_capacitance : 0.00569391; - rise_capacitance_range (0.00569391, 0.00569391); + rise_capacitance_range (0.00530552, 0.00622769); fall_capacitance : 0.00582547; - fall_capacitance_range (0.00582547, 0.00582547); + fall_capacitance_range (0.00498872, 0.00659777); } pin (B) { direction : "input"; max_transition : 2.5074; capacitance : 0.0057518; rise_capacitance : 0.00575015; - rise_capacitance_range (0.00575015, 0.00575015); + rise_capacitance_range (0.00495751, 0.00652204); fall_capacitance : 0.00575344; - fall_capacitance_range (0.00575344, 0.00575344); + fall_capacitance_range (0.00491943, 0.00647161); } pin (C) { direction : "input"; max_transition : 2.5074; capacitance : 0.00557185; rise_capacitance : 0.00574315; - rise_capacitance_range (0.00574315, 0.00574315); + rise_capacitance_range (0.00449806, 0.00685361); fall_capacitance : 0.00540054; - fall_capacitance_range (0.00540054, 0.00540054); + fall_capacitance_range (0.00485698, 0.00583383); } } cell (sg13g2_nor4_1) { @@ -23996,104 +24070,104 @@ library (sg13g2_stdcell_typ_1p20V_25C) { max_transition : 2.5074; capacitance : 0.00298675; rise_capacitance : 0.0029524; - rise_capacitance_range (0.0029524, 0.0029524); + rise_capacitance_range (0.00279679, 0.00319278); fall_capacitance : 0.00302109; - fall_capacitance_range (0.00302109, 0.00302109); + fall_capacitance_range (0.00262017, 0.00338718); } pin (B) { direction : "input"; max_transition : 2.5074; capacitance : 0.003003; rise_capacitance : 0.00299387; - rise_capacitance_range (0.00299387, 0.00299387); + rise_capacitance_range (0.00269441, 0.00332662); fall_capacitance : 0.00301212; - fall_capacitance_range (0.00301212, 0.00301212); + fall_capacitance_range (0.00259094, 0.00338537); } pin (C) { direction : "input"; max_transition : 2.5074; capacitance : 0.00297233; rise_capacitance : 0.00298617; - rise_capacitance_range (0.00298617, 0.00298617); + rise_capacitance_range (0.00258794, 0.00341125); fall_capacitance : 0.00295848; - fall_capacitance_range (0.00295848, 0.00295848); + fall_capacitance_range (0.00254663, 0.00329679); } pin (D) { direction : "input"; max_transition : 2.5074; capacitance : 0.00283259; rise_capacitance : 0.00292446; - rise_capacitance_range (0.00292446, 0.00292446); + rise_capacitance_range (0.00239343, 0.0034734); fall_capacitance : 0.00274073; - fall_capacitance_range (0.00274073, 0.00274073); + fall_capacitance_range (0.00250336, 0.00290105); } } cell (sg13g2_nor4_2) { area : 21.7728; cell_footprint : "nor4"; - cell_leakage_power : 199.535; + cell_leakage_power : 199.536; leakage_power () { - value : 348.295; + value : 348.296; when : "!A&!B&!C&!D&Y"; } leakage_power () { - value : 291.963; + value : 291.964; when : "!A&!B&!C&D&!Y"; } leakage_power () { - value : 235.349; + value : 235.35; when : "!A&!B&C&!D&!Y"; } leakage_power () { - value : 216.137; + value : 216.138; when : "!A&!B&C&D&!Y"; } leakage_power () { - value : 195.554; + value : 195.555; when : "!A&B&!C&!D&!Y"; } leakage_power () { - value : 183.047; + value : 183.048; when : "!A&B&!C&D&!Y"; } leakage_power () { - value : 176.711; + value : 176.712; when : "!A&B&C&!D&!Y"; } leakage_power () { - value : 210.528; + value : 210.529; when : "!A&B&C&D&!Y"; } leakage_power () { - value : 156.63; + value : 156.631; when : "A&!B&!C&!D&!Y"; } leakage_power () { - value : 148.65; + value : 148.651; when : "A&!B&!C&D&!Y"; } leakage_power () { - value : 144.752; + value : 144.753; when : "A&!B&C&!D&!Y"; } leakage_power () { - value : 188; + value : 188.001; when : "A&!B&C&D&!Y"; } leakage_power () { - value : 138.959; + value : 138.96; when : "A&B&!C&!D&!Y"; } leakage_power () { - value : 174.03; + value : 174.031; when : "A&B&!C&D&!Y"; } leakage_power () { - value : 171.933; + value : 171.934; when : "A&B&C&!D&!Y"; } leakage_power () { - value : 212.019; + value : 212.02; when : "A&B&C&D&!Y"; } pin (Y) { @@ -24109,52 +24183,52 @@ library (sg13g2_stdcell_typ_1p20V_25C) { index_1 ("0.0186, 0.0966, 0.174, 0.3294, 0.6408, 1.263, 2.5074"); index_2 ("0.001, 0.0468, 0.078, 0.1296, 0.216, 0.36, 0.6"); values ( \ - "0.111204, 0.386114, 0.570494, 0.875226, 1.38517, 2.23498, 3.65122", \ - "0.13666, 0.41212, 0.597162, 0.9026, 1.41326, 2.26325, 3.67965", \ - "0.153314, 0.431654, 0.616906, 0.92241, 1.43355, 2.28362, 3.69974", \ - "0.175937, 0.465974, 0.651832, 0.95763, 1.47227, 2.31937, 3.73643", \ - "0.202236, 0.523651, 0.715443, 1.02435, 1.53574, 2.3867, 3.80406", \ - "0.226634, 0.61119, 0.819002, 1.14323, 1.66535, 2.51877, 3.93516", \ - "0.251214, 0.738489, 0.981652, 1.3404, 1.89618, 2.77534, 4.20275" \ + "0.111192, 0.386087, 0.570396, 0.875073, 1.38512, 2.23486, 3.65113", \ + "0.136643, 0.412148, 0.597213, 0.902453, 1.41294, 2.26311, 3.67946", \ + "0.153352, 0.431642, 0.617022, 0.922358, 1.43336, 2.28351, 3.6996", \ + "0.175928, 0.465953, 0.651859, 0.9575, 1.46842, 2.31927, 3.73621", \ + "0.202226, 0.523629, 0.715405, 1.02432, 1.53561, 2.38634, 3.80394", \ + "0.22668, 0.609849, 0.818969, 1.14318, 1.66528, 2.51866, 3.93498", \ + "0.2512, 0.73846, 0.981614, 1.34035, 1.8961, 2.77525, 4.20256" \ ); } rise_transition (TIMING_DELAY_7x7ds1) { index_1 ("0.0186, 0.0966, 0.174, 0.3294, 0.6408, 1.263, 2.5074"); index_2 ("0.001, 0.0468, 0.078, 0.1296, 0.216, 0.36, 0.6"); values ( \ - "0.0718801, 0.442998, 0.695074, 1.11211, 1.81037, 2.97411, 4.91369", \ - "0.0737831, 0.442999, 0.695388, 1.11236, 1.81052, 2.97412, 4.91395", \ - "0.0787389, 0.443684, 0.695853, 1.11237, 1.81123, 2.97413, 4.91429", \ - "0.0895473, 0.449892, 0.698362, 1.11669, 1.81372, 2.97501, 4.91652", \ - "0.114326, 0.474646, 0.716865, 1.12323, 1.81466, 2.97508, 4.91653", \ - "0.171385, 0.535333, 0.773975, 1.1694, 1.84228, 2.98449, 4.92045", \ - "0.287923, 0.664046, 0.90178, 1.29332, 1.95054, 3.06085, 4.95015" \ + "0.0718305, 0.442976, 0.6954, 1.11208, 1.81029, 2.97395, 4.9134", \ + "0.0737752, 0.442977, 0.695439, 1.11232, 1.8103, 2.97397, 4.91372", \ + "0.078782, 0.443671, 0.698913, 1.11254, 1.81083, 2.97399, 4.91373", \ + "0.0895417, 0.44987, 0.698914, 1.11891, 1.81084, 2.97482, 4.91609", \ + "0.114319, 0.474624, 0.716626, 1.12294, 1.81348, 2.97606, 4.9161", \ + "0.171345, 0.534064, 0.773943, 1.16935, 1.84208, 2.98435, 4.92022", \ + "0.288063, 0.664022, 0.901746, 1.2932, 1.95047, 3.0609, 4.95097" \ ); } cell_fall (TIMING_DELAY_7x7ds1) { index_1 ("0.0186, 0.0966, 0.174, 0.3294, 0.6408, 1.263, 2.5074"); index_2 ("0.001, 0.0468, 0.078, 0.1296, 0.216, 0.36, 0.6"); values ( \ - "0.0276348, 0.0841821, 0.119933, 0.178039, 0.274586, 0.434261, 0.699505", \ - "0.0613894, 0.131976, 0.169461, 0.228085, 0.324354, 0.483883, 0.749397", \ - "0.0820734, 0.169756, 0.212459, 0.275245, 0.373392, 0.533083, 0.798394", \ - "0.110979, 0.227688, 0.280856, 0.355988, 0.464765, 0.630026, 0.895643", \ - "0.150344, 0.312697, 0.384723, 0.481755, 0.616349, 0.806637, 1.08903", \ - "0.200341, 0.432484, 0.533679, 0.667275, 0.848355, 1.08963, 1.42595", \ - "0.258762, 0.586112, 0.73446, 0.92792, 1.17827, 1.51201, 1.94959" \ + "0.0276265, 0.0841573, 0.119921, 0.178023, 0.274536, 0.433924, 0.699363", \ + "0.0613846, 0.131935, 0.169445, 0.228018, 0.324242, 0.483802, 0.749001", \ + "0.0820676, 0.169743, 0.212479, 0.275219, 0.37335, 0.533008, 0.798282", \ + "0.110972, 0.227673, 0.280868, 0.355936, 0.464591, 0.629912, 0.895761", \ + "0.150336, 0.312653, 0.3847, 0.481723, 0.616266, 0.806567, 1.08898", \ + "0.200362, 0.432463, 0.533668, 0.667199, 0.848226, 1.08956, 1.42584", \ + "0.258748, 0.586151, 0.734427, 0.927873, 1.17821, 1.51187, 1.94946" \ ); } fall_transition (TIMING_DELAY_7x7ds1) { index_1 ("0.0186, 0.0966, 0.174, 0.3294, 0.6408, 1.263, 2.5074"); index_2 ("0.001, 0.0468, 0.078, 0.1296, 0.216, 0.36, 0.6"); values ( \ - "0.0207618, 0.0912502, 0.138343, 0.215921, 0.345902, 0.561584, 0.921538", \ - "0.0373412, 0.102299, 0.145171, 0.218942, 0.346168, 0.561591, 0.921539", \ - "0.051609, 0.121329, 0.162758, 0.232307, 0.35316, 0.563657, 0.92154", \ - "0.0758861, 0.157707, 0.202086, 0.270487, 0.384037, 0.581389, 0.926748", \ - "0.115204, 0.222617, 0.271973, 0.347662, 0.463734, 0.651283, 0.972165", \ - "0.176491, 0.33083, 0.39461, 0.484361, 0.614112, 0.811809, 1.12468", \ - "0.272652, 0.510261, 0.598863, 0.713045, 0.877894, 1.10183, 1.4466" \ + "0.0207569, 0.0912521, 0.13836, 0.21585, 0.345844, 0.561673, 0.921887", \ + "0.0373335, 0.102297, 0.145156, 0.218902, 0.345992, 0.561674, 0.921888", \ + "0.0516054, 0.121316, 0.162865, 0.232273, 0.353105, 0.563612, 0.921889", \ + "0.0758824, 0.157694, 0.202099, 0.270452, 0.383926, 0.581316, 0.927487", \ + "0.115198, 0.222645, 0.271952, 0.347635, 0.463425, 0.651194, 0.97291", \ + "0.176545, 0.330813, 0.394542, 0.484402, 0.614364, 0.811821, 1.12454", \ + "0.272642, 0.510194, 0.598835, 0.713007, 0.877836, 1.10166, 1.44647" \ ); } } @@ -24166,52 +24240,52 @@ library (sg13g2_stdcell_typ_1p20V_25C) { index_1 ("0.0186, 0.0966, 0.174, 0.3294, 0.6408, 1.263, 2.5074"); index_2 ("0.001, 0.0468, 0.078, 0.1296, 0.216, 0.36, 0.6"); values ( \ - "0.106402, 0.381209, 0.565723, 0.870422, 1.38039, 2.23012, 3.64633", \ - "0.131772, 0.407908, 0.592791, 0.898184, 1.40872, 2.25888, 3.6756", \ - "0.148284, 0.429142, 0.614416, 0.91995, 1.43094, 2.28123, 3.69725", \ - "0.171035, 0.469407, 0.655678, 0.961455, 1.47611, 2.32276, 3.73989", \ - "0.198486, 0.541047, 0.735455, 1.04524, 1.55715, 2.40812, 3.82583", \ - "0.229612, 0.652975, 0.869757, 1.19948, 1.724, 2.5772, 3.99471", \ - "0.283305, 0.82364, 1.08197, 1.45514, 2.02385, 2.90841, 4.33699" \ + "0.106365, 0.381195, 0.565696, 0.870384, 1.38033, 2.23009, 3.64633", \ + "0.131725, 0.407786, 0.593674, 0.898512, 1.40842, 2.25879, 3.67533", \ + "0.148278, 0.429122, 0.614518, 0.91977, 1.43031, 2.28105, 3.69708", \ + "0.171028, 0.469369, 0.655695, 0.961507, 1.47599, 2.32265, 3.73973", \ + "0.198478, 0.541027, 0.735428, 1.04519, 1.55699, 2.40867, 3.82555", \ + "0.229603, 0.652954, 0.869726, 1.19944, 1.72379, 2.5771, 3.99454", \ + "0.283291, 0.823614, 1.08281, 1.45509, 2.02378, 2.90831, 4.33662" \ ); } rise_transition (TIMING_DELAY_7x7ds1) { index_1 ("0.0186, 0.0966, 0.174, 0.3294, 0.6408, 1.263, 2.5074"); index_2 ("0.001, 0.0468, 0.078, 0.1296, 0.216, 0.36, 0.6"); values ( \ - "0.0719636, 0.443069, 0.695077, 1.11211, 1.81037, 2.97417, 4.91395", \ - "0.0752827, 0.44307, 0.695298, 1.11212, 1.81038, 2.97418, 4.91396", \ - "0.0824006, 0.443834, 0.696106, 1.1127, 1.81116, 2.97509, 4.91397", \ - "0.0981681, 0.45282, 0.699543, 1.11609, 1.81502, 2.9751, 4.91398", \ - "0.132942, 0.484505, 0.72336, 1.12622, 1.81503, 2.97511, 4.91491", \ - "0.201855, 0.561684, 0.794265, 1.18355, 1.84901, 2.98739, 4.9161", \ - "0.316056, 0.717923, 0.950848, 1.33461, 1.97838, 3.07732, 4.9561" \ + "0.0719571, 0.44305, 0.695042, 1.11206, 1.81029, 2.97397, 4.9134", \ + "0.0752748, 0.443255, 0.695762, 1.11269, 1.81118, 2.97403, 4.91341", \ + "0.0823968, 0.44383, 0.69875, 1.1127, 1.81119, 2.97404, 4.91342", \ + "0.0981631, 0.452796, 0.69967, 1.1189, 1.81488, 2.97521, 4.91348", \ + "0.132937, 0.484483, 0.723328, 1.1262, 1.8149, 2.97522, 4.91622", \ + "0.201848, 0.561661, 0.794227, 1.1835, 1.84882, 2.98725, 4.91623", \ + "0.316048, 0.717901, 0.951635, 1.33456, 1.97834, 3.07723, 4.9555" \ ); } cell_fall (TIMING_DELAY_7x7ds1) { index_1 ("0.0186, 0.0966, 0.174, 0.3294, 0.6408, 1.263, 2.5074"); index_2 ("0.001, 0.0468, 0.078, 0.1296, 0.216, 0.36, 0.6"); values ( \ - "0.028477, 0.0832335, 0.11843, 0.176094, 0.272404, 0.431911, 0.697676", \ - "0.0602531, 0.130685, 0.167733, 0.226123, 0.322255, 0.481884, 0.747761", \ - "0.0791979, 0.167678, 0.210402, 0.273212, 0.371287, 0.531, 0.796715", \ - "0.105038, 0.224296, 0.277721, 0.353079, 0.462054, 0.627337, 0.894079", \ - "0.139301, 0.306882, 0.380003, 0.477887, 0.613132, 0.804053, 1.08736", \ - "0.180676, 0.422339, 0.525654, 0.660661, 0.842852, 1.08615, 1.4235", \ - "0.22512, 0.567489, 0.719899, 0.916902, 1.16986, 1.50646, 1.94619" \ + "0.0284736, 0.0832255, 0.118417, 0.176112, 0.272412, 0.431909, 0.697656", \ + "0.0602525, 0.130525, 0.167742, 0.226133, 0.322242, 0.481877, 0.747512", \ + "0.0791968, 0.167676, 0.210399, 0.27321, 0.371249, 0.531025, 0.796711", \ + "0.104906, 0.224295, 0.277731, 0.353078, 0.462084, 0.62733, 0.894088", \ + "0.139299, 0.306879, 0.380001, 0.477883, 0.613126, 0.804046, 1.08732", \ + "0.180674, 0.422336, 0.525648, 0.660657, 0.842987, 1.08614, 1.42349", \ + "0.225119, 0.567486, 0.719896, 0.916897, 1.16985, 1.50645, 1.94618" \ ); } fall_transition (TIMING_DELAY_7x7ds1) { index_1 ("0.0186, 0.0966, 0.174, 0.3294, 0.6408, 1.263, 2.5074"); index_2 ("0.001, 0.0468, 0.078, 0.1296, 0.216, 0.36, 0.6"); values ( \ - "0.0193449, 0.0880101, 0.135028, 0.212757, 0.34277, 0.559083, 0.919952", \ - "0.0347993, 0.0994614, 0.142335, 0.216085, 0.343264, 0.559564, 0.919953", \ - "0.0483738, 0.118577, 0.160128, 0.229575, 0.350495, 0.561004, 0.919954", \ - "0.0715445, 0.154547, 0.199295, 0.26781, 0.381601, 0.57896, 0.926149", \ - "0.109144, 0.219442, 0.269432, 0.345136, 0.461302, 0.649097, 0.971298", \ - "0.168157, 0.326882, 0.390915, 0.481342, 0.611954, 0.809896, 1.12283", \ - "0.260436, 0.50627, 0.596191, 0.710984, 0.87345, 1.10044, 1.44466" \ + "0.0193482, 0.088009, 0.135037, 0.212659, 0.342763, 0.559073, 0.919936", \ + "0.0347985, 0.0995636, 0.142314, 0.215915, 0.343255, 0.559555, 0.919937", \ + "0.0483734, 0.118575, 0.160126, 0.229573, 0.350486, 0.561347, 0.919938", \ + "0.0716739, 0.154546, 0.199528, 0.267809, 0.381644, 0.578951, 0.926008", \ + "0.109143, 0.21944, 0.269429, 0.345133, 0.461296, 0.649095, 0.971579", \ + "0.168156, 0.326879, 0.390926, 0.481335, 0.612138, 0.809889, 1.12282", \ + "0.260433, 0.506267, 0.596187, 0.710979, 0.873444, 1.10043, 1.44465" \ ); } } @@ -24223,52 +24297,52 @@ library (sg13g2_stdcell_typ_1p20V_25C) { index_1 ("0.0186, 0.0966, 0.174, 0.3294, 0.6408, 1.263, 2.5074"); index_2 ("0.001, 0.0468, 0.078, 0.1296, 0.216, 0.36, 0.6"); values ( \ - "0.0914896, 0.366506, 0.550948, 0.855455, 1.36546, 2.2153, 3.6316", \ - "0.115165, 0.392629, 0.577629, 0.883228, 1.39341, 2.24354, 3.6603", \ - "0.13108, 0.416917, 0.602156, 0.908036, 1.41844, 2.26848, 3.6865", \ - "0.153907, 0.466131, 0.653109, 0.959166, 1.47017, 2.32141, 3.73868", \ - "0.184139, 0.555214, 0.753106, 1.06475, 1.57717, 2.42881, 3.84633", \ - "0.230443, 0.693614, 0.92144, 1.25852, 1.78741, 2.64101, 4.05772", \ - "0.308915, 0.898428, 1.17894, 1.57503, 2.16212, 3.05847, 4.48963" \ + "0.0914791, 0.366492, 0.550786, 0.855415, 1.3654, 2.21519, 3.63235", \ + "0.115172, 0.392612, 0.577593, 0.882779, 1.39305, 2.24344, 3.66013", \ + "0.131075, 0.4169, 0.602112, 0.907989, 1.41884, 2.26838, 3.68633", \ + "0.153902, 0.466214, 0.653082, 0.959004, 1.46994, 2.32128, 3.7385", \ + "0.184133, 0.555197, 0.753082, 1.06471, 1.57691, 2.42877, 3.84616", \ + "0.230436, 0.693595, 0.921414, 1.25848, 1.78737, 2.64089, 4.05705", \ + "0.308903, 0.898405, 1.17891, 1.57498, 2.16209, 3.05836, 4.48938" \ ); } rise_transition (TIMING_DELAY_7x7ds1) { index_1 ("0.0186, 0.0966, 0.174, 0.3294, 0.6408, 1.263, 2.5074"); index_2 ("0.001, 0.0468, 0.078, 0.1296, 0.216, 0.36, 0.6"); values ( \ - "0.0721236, 0.443014, 0.695346, 1.11214, 1.81046, 2.97411, 4.91363", \ - "0.077905, 0.444933, 0.695519, 1.11274, 1.81138, 2.97417, 4.91365", \ - "0.0882349, 0.444934, 0.696515, 1.11307, 1.81139, 2.97553, 4.916", \ - "0.109504, 0.457106, 0.701457, 1.11749, 1.8114, 2.97554, 4.91601", \ - "0.149891, 0.500103, 0.733257, 1.1307, 1.81608, 2.97574, 4.91602", \ - "0.215952, 0.596743, 0.824393, 1.20603, 1.86043, 2.99088, 4.92684", \ - "0.317033, 0.769192, 1.01238, 1.39453, 2.02917, 3.10606, 4.96763" \ + "0.0724872, 0.442992, 0.69502, 1.11209, 1.81038, 2.97397, 4.91586", \ + "0.0778908, 0.444913, 0.695042, 1.11227, 1.81104, 2.97403, 4.91587", \ + "0.0882299, 0.444914, 0.697986, 1.11301, 1.81122, 2.97539, 4.91588", \ + "0.109499, 0.457135, 0.701423, 1.11481, 1.81123, 2.9754, 4.91589", \ + "0.149885, 0.500083, 0.733224, 1.13065, 1.81567, 2.97562, 4.9159", \ + "0.215941, 0.596723, 0.824363, 1.20598, 1.86037, 2.98963, 4.92761", \ + "0.317096, 0.769172, 1.01236, 1.39448, 2.02904, 3.10593, 4.9665" \ ); } cell_fall (TIMING_DELAY_7x7ds1) { index_1 ("0.0186, 0.0966, 0.174, 0.3294, 0.6408, 1.263, 2.5074"); index_2 ("0.001, 0.0468, 0.078, 0.1296, 0.216, 0.36, 0.6"); values ( \ - "0.0275481, 0.0803355, 0.11506, 0.172353, 0.268342, 0.427584, 0.693231", \ - "0.0563988, 0.127426, 0.164539, 0.222797, 0.318519, 0.477956, 0.743689", \ - "0.0725338, 0.163737, 0.206705, 0.269577, 0.367603, 0.527173, 0.792734", \ - "0.0937531, 0.218597, 0.27262, 0.348712, 0.458127, 0.6236, 0.890092", \ - "0.120818, 0.298236, 0.372583, 0.47204, 0.608102, 0.79967, 1.08326", \ - "0.151237, 0.408192, 0.514596, 0.651285, 0.836147, 1.08047, 1.41856", \ - "0.178892, 0.543418, 0.701357, 0.902814, 1.15899, 1.49804, 1.93899" \ + "0.027546, 0.0803362, 0.115068, 0.172342, 0.268346, 0.427557, 0.693234", \ + "0.0563984, 0.127426, 0.164539, 0.222797, 0.318511, 0.477999, 0.743703", \ + "0.0725331, 0.163736, 0.206705, 0.269576, 0.367603, 0.527169, 0.792746", \ + "0.0937523, 0.218597, 0.27262, 0.348709, 0.458123, 0.623607, 0.890085", \ + "0.120817, 0.298235, 0.372583, 0.47204, 0.608101, 0.79967, 1.08326", \ + "0.151236, 0.408191, 0.514596, 0.651285, 0.836147, 1.08047, 1.41856", \ + "0.178893, 0.543418, 0.701357, 0.902813, 1.15899, 1.49804, 1.93899" \ ); } fall_transition (TIMING_DELAY_7x7ds1) { index_1 ("0.0186, 0.0966, 0.174, 0.3294, 0.6408, 1.263, 2.5074"); index_2 ("0.001, 0.0468, 0.078, 0.1296, 0.216, 0.36, 0.6"); values ( \ - "0.0164064, 0.084146, 0.131098, 0.208633, 0.33877, 0.555072, 0.915856", \ - "0.0312885, 0.0962115, 0.138774, 0.212162, 0.339337, 0.555311, 0.915857", \ - "0.0444157, 0.115316, 0.15681, 0.226042, 0.347102, 0.557257, 0.915858", \ - "0.0665942, 0.151311, 0.196316, 0.264682, 0.37824, 0.575463, 0.921259", \ - "0.10249, 0.21535, 0.266216, 0.341865, 0.458077, 0.645916, 0.967312", \ - "0.15892, 0.323872, 0.38797, 0.478271, 0.6082, 0.806602, 1.11924", \ - "0.248486, 0.501754, 0.593226, 0.707548, 0.870648, 1.09652, 1.44149" \ + "0.0164016, 0.0841458, 0.131104, 0.208632, 0.338807, 0.555067, 0.915855", \ + "0.0312883, 0.0962113, 0.138774, 0.212162, 0.339316, 0.555251, 0.915856", \ + "0.0444154, 0.115316, 0.15681, 0.226042, 0.347102, 0.557073, 0.915857", \ + "0.0665937, 0.151303, 0.196316, 0.264828, 0.378023, 0.575462, 0.922296", \ + "0.10249, 0.215687, 0.266215, 0.341865, 0.458067, 0.645916, 0.967312", \ + "0.158919, 0.323872, 0.387969, 0.47827, 0.6082, 0.806602, 1.11924", \ + "0.248485, 0.501754, 0.593225, 0.707547, 0.870647, 1.09652, 1.44149" \ ); } } @@ -24280,52 +24354,52 @@ library (sg13g2_stdcell_typ_1p20V_25C) { index_1 ("0.0186, 0.0966, 0.174, 0.3294, 0.6408, 1.263, 2.5074"); index_2 ("0.001, 0.0468, 0.078, 0.1296, 0.216, 0.36, 0.6"); values ( \ - "0.0622659, 0.339914, 0.524625, 0.829638, 1.33947, 2.18925, 3.60652", \ - "0.0865372, 0.365531, 0.550956, 0.856861, 1.36738, 2.21835, 3.6346", \ - "0.10441, 0.392836, 0.578081, 0.88404, 1.39485, 2.24543, 3.66182", \ - "0.129409, 0.45039, 0.636735, 0.941819, 1.453, 2.30386, 3.72115", \ - "0.166101, 0.55329, 0.753328, 1.06395, 1.57442, 2.42375, 3.84058", \ - "0.220015, 0.705173, 0.942359, 1.28658, 1.81679, 2.66525, 4.07752", \ - "0.301002, 0.919793, 1.21571, 1.63282, 2.23821, 3.14494, 4.57077" \ + "0.0622803, 0.339992, 0.5246, 0.829419, 1.33936, 2.18907, 3.60635", \ + "0.0865346, 0.365517, 0.550917, 0.856817, 1.36723, 2.21824, 3.63443", \ + "0.104408, 0.392843, 0.578063, 0.883996, 1.39479, 2.24519, 3.66181", \ + "0.129405, 0.45037, 0.636715, 0.941766, 1.45294, 2.30372, 3.72097", \ + "0.166096, 0.553276, 0.753285, 1.06392, 1.57437, 2.42371, 3.84048", \ + "0.220008, 0.705156, 0.94233, 1.2869, 1.81673, 2.66527, 4.07749", \ + "0.30099, 0.919772, 1.21568, 1.63282, 2.23815, 3.14485, 4.57069" \ ); } rise_transition (TIMING_DELAY_7x7ds1) { index_1 ("0.0186, 0.0966, 0.174, 0.3294, 0.6408, 1.263, 2.5074"); index_2 ("0.001, 0.0468, 0.078, 0.1296, 0.216, 0.36, 0.6"); values ( \ - "0.0706208, 0.44307, 0.695053, 1.11265, 1.81037, 2.97421, 4.91601", \ - "0.0797299, 0.443071, 0.695433, 1.11266, 1.81076, 2.97557, 4.91602", \ - "0.0921446, 0.444997, 0.69556, 1.11276, 1.81119, 2.97558, 4.91603", \ - "0.112826, 0.463262, 0.703801, 1.11955, 1.8112, 2.97559, 4.91604", \ - "0.148548, 0.520898, 0.749362, 1.13951, 1.8195, 2.9756, 4.91605", \ - "0.206825, 0.63569, 0.866787, 1.24349, 1.8835, 2.99944, 4.92067", \ - "0.305388, 0.823304, 1.08649, 1.47961, 2.11109, 3.16483, 4.99363" \ + "0.0705899, 0.442985, 0.695019, 1.1121, 1.8103, 2.97416, 4.91578", \ + "0.0797269, 0.443017, 0.695387, 1.11256, 1.81031, 2.97543, 4.91579", \ + "0.0921407, 0.444978, 0.69552, 1.11273, 1.81111, 2.97544, 4.91615", \ + "0.112822, 0.463203, 0.703775, 1.11852, 1.81112, 2.97545, 4.91616", \ + "0.148543, 0.52088, 0.749306, 1.13924, 1.81942, 2.97546, 4.91617", \ + "0.20682, 0.635672, 0.866771, 1.2437, 1.88342, 2.99931, 4.91985", \ + "0.305381, 0.823286, 1.08611, 1.48026, 2.11101, 3.16468, 4.99322" \ ); } cell_fall (TIMING_DELAY_7x7ds1) { index_1 ("0.0186, 0.0966, 0.174, 0.3294, 0.6408, 1.263, 2.5074"); index_2 ("0.001, 0.0468, 0.078, 0.1296, 0.216, 0.36, 0.6"); values ( \ - "0.023581, 0.0761434, 0.110627, 0.167645, 0.263054, 0.422073, 0.687013", \ - "0.047281, 0.122949, 0.160202, 0.218223, 0.313635, 0.47254, 0.737584", \ - "0.0596324, 0.158041, 0.201597, 0.26487, 0.362754, 0.521926, 0.786741", \ - "0.0744208, 0.210536, 0.266184, 0.342578, 0.452531, 0.618445, 0.884084", \ - "0.0919074, 0.287068, 0.363486, 0.464605, 0.601624, 0.793689, 1.07719", \ - "0.108219, 0.390456, 0.50106, 0.640738, 0.827229, 1.07294, 1.41183", \ - "0.114653, 0.515168, 0.6792, 0.885989, 1.14629, 1.48738, 1.93068" \ + "0.0235814, 0.0761517, 0.110647, 0.16765, 0.263056, 0.422184, 0.687013", \ + "0.0472805, 0.12297, 0.1602, 0.218225, 0.313635, 0.472614, 0.737572", \ + "0.0596317, 0.158041, 0.201597, 0.26487, 0.362818, 0.521926, 0.786745", \ + "0.0744198, 0.210687, 0.266183, 0.342933, 0.45253, 0.618413, 0.884202", \ + "0.0919063, 0.287067, 0.363486, 0.464604, 0.601623, 0.793689, 1.07719", \ + "0.108218, 0.390455, 0.50106, 0.640738, 0.827229, 1.07294, 1.41175", \ + "0.114653, 0.515063, 0.6792, 0.885989, 1.14628, 1.48738, 1.93068" \ ); } fall_transition (TIMING_DELAY_7x7ds1) { index_1 ("0.0186, 0.0966, 0.174, 0.3294, 0.6408, 1.263, 2.5074"); index_2 ("0.001, 0.0468, 0.078, 0.1296, 0.216, 0.36, 0.6"); values ( \ - "0.0128609, 0.0796626, 0.126365, 0.203756, 0.333292, 0.549156, 0.908937", \ - "0.0278723, 0.0923285, 0.134528, 0.207542, 0.334238, 0.549157, 0.908938", \ - "0.0398583, 0.111891, 0.152994, 0.221556, 0.34178, 0.55131, 0.908939", \ - "0.0608354, 0.148079, 0.192703, 0.260834, 0.373771, 0.569908, 0.915059", \ - "0.0949239, 0.211488, 0.262769, 0.338216, 0.453581, 0.640537, 0.960857", \ - "0.150243, 0.32108, 0.383602, 0.474748, 0.60429, 0.801651, 1.11316", \ - "0.241869, 0.498015, 0.590981, 0.704074, 0.868281, 1.09058, 1.43515" \ + "0.0128605, 0.0796526, 0.126351, 0.203752, 0.333292, 0.549171, 0.908937", \ + "0.027872, 0.0924055, 0.134527, 0.207547, 0.334238, 0.549172, 0.908938", \ + "0.0398585, 0.111716, 0.152994, 0.221556, 0.341686, 0.551309, 0.908939", \ + "0.0608349, 0.147951, 0.192703, 0.260882, 0.373728, 0.569947, 0.915021", \ + "0.0949232, 0.211488, 0.26277, 0.338215, 0.453311, 0.640537, 0.960856", \ + "0.150242, 0.321081, 0.383602, 0.474746, 0.60429, 0.801651, 1.11363", \ + "0.241869, 0.498517, 0.590984, 0.704074, 0.86828, 1.09058, 1.43515" \ ); } } @@ -24335,26 +24409,26 @@ library (sg13g2_stdcell_typ_1p20V_25C) { index_1 ("0.0186, 0.0966, 0.174, 0.3294, 0.6408, 1.263, 2.5074"); index_2 ("0.001, 0.0468, 0.078, 0.1296, 0.216, 0.36, 0.6"); values ( \ - "0.0196394, 0.0199966, 0.0199444, 0.0198199, 0.0195896, 0.0195412, 0.0194894", \ - "0.0192844, 0.0196487, 0.0197, 0.019674, 0.0194559, 0.0194368, 0.0193237", \ - "0.0191862, 0.0195522, 0.0195779, 0.0195389, 0.0194231, 0.0193181, 0.0194247", \ - "0.0191694, 0.019483, 0.0194174, 0.0195182, 0.0194516, 0.0192759, 0.0192577", \ - "0.0192939, 0.0192467, 0.0193551, 0.0192159, 0.0200754, 0.0191871, 0.0191967", \ - "0.0208522, 0.0200249, 0.019855, 0.0196273, 0.0200371, 0.0192803, 0.0194362", \ - "0.0272487, 0.023495, 0.0227582, 0.0220842, 0.0210794, 0.0209153, 0.0200285" \ + "0.0196436, 0.0199927, 0.0199471, 0.0198094, 0.0195909, 0.019538, 0.0194494", \ + "0.0192837, 0.019656, 0.019699, 0.0196612, 0.019473, 0.019405, 0.0193208", \ + "0.0191863, 0.0195212, 0.0197224, 0.0195401, 0.0193887, 0.0193211, 0.0193649", \ + "0.0191661, 0.0194908, 0.0194167, 0.0196416, 0.0192384, 0.0193288, 0.0193593", \ + "0.0192905, 0.019244, 0.0193651, 0.0191972, 0.0195497, 0.019241, 0.019198", \ + "0.0208502, 0.019985, 0.0198523, 0.0196094, 0.0200487, 0.0192712, 0.0194409", \ + "0.0272456, 0.0234908, 0.0227542, 0.0220554, 0.0210853, 0.0210073, 0.0200682" \ ); } fall_power (POWER_7x7ds1) { index_1 ("0.0186, 0.0966, 0.174, 0.3294, 0.6408, 1.263, 2.5074"); index_2 ("0.001, 0.0468, 0.078, 0.1296, 0.216, 0.36, 0.6"); values ( \ - "0.0062265, 0.00612126, 0.00605246, 0.00594876, 0.00582803, 0.00541292, 0.00470484", \ - "0.00575541, 0.00577917, 0.00579913, 0.00570787, 0.00565468, 0.00516236, 0.00443398", \ - "0.00568837, 0.00579685, 0.0056501, 0.00562503, 0.00549755, 0.00579689, 0.00436796", \ - "0.00596133, 0.00583042, 0.0058434, 0.00565857, 0.0053858, 0.00598594, 0.00439211", \ - "0.00711614, 0.00636782, 0.00621435, 0.00608072, 0.00574639, 0.00507595, 0.00551319", \ - "0.0103207, 0.00828117, 0.00772051, 0.00729312, 0.00683091, 0.00640819, 0.00504106", \ - "0.0178727, 0.013785, 0.0124162, 0.0110982, 0.00978494, 0.0084467, 0.00770357" \ + "0.00622922, 0.00612218, 0.00606764, 0.0059457, 0.00582762, 0.0053642, 0.00480383", \ + "0.0057573, 0.00577562, 0.00580793, 0.00563991, 0.0054468, 0.00514626, 0.00441804", \ + "0.00568932, 0.00577769, 0.00571157, 0.00561355, 0.00550291, 0.00536466, 0.00437281", \ + "0.0059613, 0.00584215, 0.0058396, 0.00570408, 0.00536363, 0.00593538, 0.00448765", \ + "0.00711945, 0.00636505, 0.00620976, 0.00607429, 0.00583374, 0.00507867, 0.00564581", \ + "0.0103255, 0.00828581, 0.00772639, 0.00729405, 0.00686652, 0.00630358, 0.00532723", \ + "0.0178753, 0.0137955, 0.0124185, 0.0110947, 0.009785, 0.00843666, 0.00768422" \ ); } } @@ -24364,26 +24438,26 @@ library (sg13g2_stdcell_typ_1p20V_25C) { index_1 ("0.0186, 0.0966, 0.174, 0.3294, 0.6408, 1.263, 2.5074"); index_2 ("0.001, 0.0468, 0.078, 0.1296, 0.216, 0.36, 0.6"); values ( \ - "0.015964, 0.016313, 0.0162669, 0.0161328, 0.0159085, 0.0158547, 0.0158704", \ - "0.0155895, 0.0159739, 0.0160203, 0.0159594, 0.0158013, 0.0157638, 0.015687", \ - "0.015485, 0.0159575, 0.0158923, 0.0158608, 0.0156958, 0.0156916, 0.0156653", \ - "0.0154731, 0.0156843, 0.0157221, 0.0157783, 0.0157796, 0.01561, 0.0154961", \ - "0.015731, 0.0156367, 0.0156915, 0.0155404, 0.0162407, 0.0154747, 0.0155615", \ - "0.0176876, 0.0164978, 0.016241, 0.0160286, 0.0159598, 0.0155714, 0.0155177", \ - "0.024472, 0.0203637, 0.0193798, 0.0186078, 0.0173736, 0.0171088, 0.0162755" \ + "0.0159605, 0.0163116, 0.0162643, 0.0161327, 0.0159076, 0.0158606, 0.0157525", \ + "0.0155868, 0.0159822, 0.0160527, 0.0159891, 0.0158406, 0.0157569, 0.0157162", \ + "0.0154834, 0.0159501, 0.016022, 0.0158325, 0.0157129, 0.015729, 0.0156375", \ + "0.015471, 0.0158115, 0.0157295, 0.0159265, 0.015808, 0.0155814, 0.0154971", \ + "0.0157302, 0.0156428, 0.0156913, 0.0155334, 0.0154669, 0.0155161, 0.0156759", \ + "0.0176863, 0.0164925, 0.0162496, 0.015977, 0.0157774, 0.0154078, 0.0156486", \ + "0.0244733, 0.0203595, 0.0194247, 0.0186135, 0.0174888, 0.0173216, 0.0162391" \ ); } fall_power (POWER_7x7ds1) { index_1 ("0.0186, 0.0966, 0.174, 0.3294, 0.6408, 1.263, 2.5074"); index_2 ("0.001, 0.0468, 0.078, 0.1296, 0.216, 0.36, 0.6"); values ( \ - "0.00582573, 0.00575609, 0.0056925, 0.00557667, 0.00537428, 0.00498085, 0.0043261", \ - "0.00526316, 0.00547458, 0.00549124, 0.00542537, 0.00518715, 0.00493789, 0.00420707", \ - "0.00514574, 0.00543828, 0.00540229, 0.00531368, 0.00551116, 0.0057296, 0.00414352", \ - "0.00538433, 0.00544701, 0.00549626, 0.00527032, 0.00508671, 0.00557527, 0.00456126", \ - "0.00656098, 0.00589589, 0.00586895, 0.00571468, 0.00552629, 0.00475413, 0.00548347", \ - "0.00971257, 0.00768523, 0.00722587, 0.00676964, 0.00635898, 0.00598173, 0.00488781", \ - "0.0169857, 0.0130992, 0.0116979, 0.0104595, 0.00903528, 0.00807758, 0.00724377" \ + "0.00581534, 0.00575533, 0.00569517, 0.00556032, 0.00537797, 0.00498263, 0.00432619", \ + "0.00526301, 0.00546006, 0.00549047, 0.00537805, 0.00518488, 0.00494197, 0.00421043", \ + "0.00514125, 0.0054442, 0.00540244, 0.00531423, 0.00550205, 0.00576902, 0.00413984", \ + "0.00538379, 0.00544737, 0.00548945, 0.00535346, 0.00508953, 0.00560145, 0.00436408", \ + "0.00656075, 0.00589547, 0.00586527, 0.00571766, 0.0055149, 0.00476552, 0.00545559", \ + "0.00971273, 0.00768375, 0.00722383, 0.00676881, 0.00636058, 0.00598601, 0.0048968", \ + "0.0169858, 0.0130991, 0.0116983, 0.0104602, 0.00903514, 0.00807938, 0.00724374" \ ); } } @@ -24393,26 +24467,26 @@ library (sg13g2_stdcell_typ_1p20V_25C) { index_1 ("0.0186, 0.0966, 0.174, 0.3294, 0.6408, 1.263, 2.5074"); index_2 ("0.001, 0.0468, 0.078, 0.1296, 0.216, 0.36, 0.6"); values ( \ - "0.0122448, 0.0126, 0.0125553, 0.012433, 0.0121675, 0.0121388, 0.0120427", \ - "0.0118631, 0.0123473, 0.0122979, 0.0122782, 0.0121214, 0.0121398, 0.0120195", \ - "0.0117631, 0.0121935, 0.0121892, 0.0121614, 0.0119626, 0.0119907, 0.0119159", \ - "0.0118415, 0.0121217, 0.0120039, 0.0121233, 0.0118375, 0.0119745, 0.0119584", \ - "0.0125074, 0.0120983, 0.012107, 0.0119186, 0.0119143, 0.0118447, 0.0119209", \ - "0.0151693, 0.0133891, 0.012982, 0.0125588, 0.0126295, 0.0119589, 0.0122735", \ - "0.0221448, 0.0177288, 0.0166526, 0.0155878, 0.014242, 0.0140236, 0.0129631" \ + "0.0122709, 0.0126027, 0.0125539, 0.0124281, 0.0121664, 0.0121374, 0.0120414", \ + "0.011865, 0.0123498, 0.0122881, 0.0122543, 0.0121087, 0.0120773, 0.0120185", \ + "0.0117652, 0.0121931, 0.0122688, 0.0121606, 0.0120024, 0.0119975, 0.0119156", \ + "0.011842, 0.0121157, 0.0120042, 0.0120191, 0.0118536, 0.0118771, 0.0120525", \ + "0.0125136, 0.0120977, 0.0121082, 0.0119176, 0.0119373, 0.011833, 0.011921", \ + "0.015173, 0.0134007, 0.0130105, 0.0125584, 0.0126303, 0.0118289, 0.0125723", \ + "0.0221416, 0.0177337, 0.0166515, 0.0155916, 0.0142384, 0.0137664, 0.012935" \ ); } fall_power (POWER_7x7ds1) { index_1 ("0.0186, 0.0966, 0.174, 0.3294, 0.6408, 1.263, 2.5074"); index_2 ("0.001, 0.0468, 0.078, 0.1296, 0.216, 0.36, 0.6"); values ( \ - "0.00467566, 0.00488787, 0.00472701, 0.00459292, 0.00445552, 0.00402675, 0.00339357", \ - "0.00416649, 0.00464065, 0.0047264, 0.00468027, 0.00469258, 0.00419706, 0.00340118", \ - "0.00408754, 0.00465421, 0.00457814, 0.00459222, 0.00464058, 0.00468157, 0.00358818", \ - "0.00439899, 0.00461825, 0.00468863, 0.00461576, 0.00435644, 0.00466735, 0.00383342", \ - "0.00563412, 0.00496016, 0.00500451, 0.00495611, 0.00476599, 0.00408316, 0.00470579", \ - "0.00881445, 0.00674403, 0.00632276, 0.00585932, 0.00558221, 0.00530927, 0.00402223", \ - "0.0158801, 0.0119158, 0.0106041, 0.00950347, 0.00812843, 0.00719271, 0.00634725" \ + "0.00467541, 0.00488885, 0.00473123, 0.00458771, 0.00446794, 0.00402748, 0.00339432", \ + "0.00417049, 0.00464062, 0.00472644, 0.00468025, 0.00477043, 0.0042367, 0.00339616", \ + "0.00408561, 0.00465415, 0.00457809, 0.00459214, 0.00464056, 0.00495678, 0.00356647", \ + "0.00439694, 0.00462916, 0.00468331, 0.00463112, 0.00432611, 0.00466818, 0.00380719", \ + "0.00563479, 0.00497152, 0.00499536, 0.00495589, 0.00481089, 0.00408313, 0.00470124", \ + "0.00881566, 0.00674432, 0.00632264, 0.00586024, 0.00558233, 0.00530937, 0.00405338", \ + "0.0158805, 0.0119154, 0.0106042, 0.00950346, 0.00812845, 0.00720613, 0.00634719" \ ); } } @@ -24422,26 +24496,26 @@ library (sg13g2_stdcell_typ_1p20V_25C) { index_1 ("0.0186, 0.0966, 0.174, 0.3294, 0.6408, 1.263, 2.5074"); index_2 ("0.001, 0.0468, 0.078, 0.1296, 0.216, 0.36, 0.6"); values ( \ - "0.00793779, 0.00863034, 0.00861349, 0.0085149, 0.00828105, 0.00821654, 0.00829715", \ - "0.00759328, 0.00811383, 0.00819956, 0.0082295, 0.00809188, 0.00817877, 0.00796673", \ - "0.00788024, 0.00796342, 0.00803997, 0.00808185, 0.00796866, 0.0080601, 0.00802039", \ - "0.00847622, 0.00814618, 0.00796481, 0.00816624, 0.00783354, 0.00797765, 0.00789582", \ - "0.00996533, 0.0086856, 0.00848044, 0.00814052, 0.00833581, 0.00781526, 0.00779941", \ - "0.0134799, 0.010976, 0.0102354, 0.0095414, 0.0091823, 0.00840727, 0.00832868", \ - "0.0210895, 0.0162576, 0.0149779, 0.0137563, 0.011642, 0.0108022, 0.00963608" \ + "0.00789567, 0.00863097, 0.008612, 0.00850535, 0.00828272, 0.00832236, 0.00829656", \ + "0.00758986, 0.00811367, 0.00819842, 0.00822896, 0.00805674, 0.00817606, 0.00796659", \ + "0.00788128, 0.00796635, 0.00803933, 0.00807715, 0.00796859, 0.00802729, 0.00809142", \ + "0.00847698, 0.00810525, 0.00796503, 0.00812546, 0.00784971, 0.00800698, 0.00790336", \ + "0.00996309, 0.0086833, 0.00847791, 0.0081145, 0.00833681, 0.00782669, 0.00794572", \ + "0.0134817, 0.0109734, 0.0102313, 0.00955639, 0.00918057, 0.00849021, 0.00841804", \ + "0.0210851, 0.0162571, 0.0149806, 0.0137815, 0.0116419, 0.0111058, 0.00966773" \ ); } fall_power (POWER_7x7ds1) { index_1 ("0.0186, 0.0966, 0.174, 0.3294, 0.6408, 1.263, 2.5074"); index_2 ("0.001, 0.0468, 0.078, 0.1296, 0.216, 0.36, 0.6"); values ( \ - "0.00332824, 0.00411867, 0.00396104, 0.00387378, 0.0037173, 0.00340834, 0.00279161", \ - "0.00300273, 0.00389673, 0.00402717, 0.00405766, 0.00392968, 0.00350534, 0.00288901", \ - "0.00302066, 0.00388376, 0.00386482, 0.00397431, 0.00430201, 0.00419143, 0.0029239", \ - "0.00351985, 0.00381934, 0.00397588, 0.00387213, 0.00370911, 0.00423864, 0.00334816", \ - "0.00491508, 0.00412133, 0.00425608, 0.00427243, 0.00415517, 0.00345009, 0.00364856", \ - "0.00842559, 0.00594555, 0.00549658, 0.00513972, 0.00489332, 0.00440643, 0.00355343", \ - "0.0160954, 0.0111645, 0.00978519, 0.00857017, 0.0074337, 0.00645598, 0.00573926" \ + "0.00332865, 0.00415528, 0.00395163, 0.00386955, 0.00371986, 0.00333617, 0.00279162", \ + "0.00300203, 0.00390549, 0.00402451, 0.00405875, 0.00392967, 0.00351514, 0.00288616", \ + "0.00301909, 0.00386118, 0.00386475, 0.00397424, 0.00422187, 0.00419142, 0.00292546", \ + "0.00352095, 0.00383908, 0.0039758, 0.0038655, 0.00371717, 0.00396142, 0.00368102", \ + "0.00491507, 0.0041213, 0.00425607, 0.00427236, 0.00415442, 0.00345008, 0.00364854", \ + "0.00842344, 0.00594528, 0.00549664, 0.00513903, 0.00489298, 0.00462055, 0.0034168", \ + "0.0160973, 0.0111643, 0.00978622, 0.00857051, 0.00743384, 0.00647827, 0.00573867" \ ); } } @@ -24449,74 +24523,74 @@ library (sg13g2_stdcell_typ_1p20V_25C) { pin (A) { direction : "input"; max_transition : 2.5074; - capacitance : 0.00575888; - rise_capacitance : 0.00569235; - rise_capacitance_range (0.00569235, 0.00569235); - fall_capacitance : 0.0058254; - fall_capacitance_range (0.0058254, 0.0058254); + capacitance : 0.00576178; + rise_capacitance : 0.0056954; + rise_capacitance_range (0.00538301, 0.00618372); + fall_capacitance : 0.00582815; + fall_capacitance_range (0.00502769, 0.00655482); } pin (B) { direction : "input"; max_transition : 2.5074; - capacitance : 0.00571716; - rise_capacitance : 0.00569981; - rise_capacitance_range (0.00569981, 0.00569981); - fall_capacitance : 0.0057345; - fall_capacitance_range (0.0057345, 0.0057345); + capacitance : 0.00571722; + rise_capacitance : 0.00569971; + rise_capacitance_range (0.00509493, 0.00637917); + fall_capacitance : 0.00573473; + fall_capacitance_range (0.00491336, 0.00648573); } pin (C) { direction : "input"; max_transition : 2.5074; capacitance : 0.00567206; rise_capacitance : 0.00570015; - rise_capacitance_range (0.00570015, 0.00570015); + rise_capacitance_range (0.0048855, 0.00658088); fall_capacitance : 0.00564397; - fall_capacitance_range (0.00564397, 0.00564397); + fall_capacitance_range (0.00484935, 0.00633209); } pin (D) { direction : "input"; max_transition : 2.5074; - capacitance : 0.00553397; - rise_capacitance : 0.00571868; - rise_capacitance_range (0.00571868, 0.00571868); - fall_capacitance : 0.00534926; - fall_capacitance_range (0.00534926, 0.00534926); + capacitance : 0.00553401; + rise_capacitance : 0.00571863; + rise_capacitance_range (0.00455957, 0.00690814); + fall_capacitance : 0.00534939; + fall_capacitance_range (0.00485041, 0.00568296); } } cell (sg13g2_o21ai_1) { area : 9.072; cell_footprint : "o21ai"; - cell_leakage_power : 126.64; + cell_leakage_power : 126.648; leakage_power () { - value : 81.5131; + value : 81.5214; when : "!A1&!A2&!B1&Y"; } leakage_power () { - value : 113.421; + value : 113.43; when : "A1&!A2&!B1&Y"; } leakage_power () { - value : 113.426; + value : 113.434; when : "!A1&A2&!B1&Y"; } leakage_power () { - value : 128.025; + value : 128.033; when : "A1&A2&!B1&Y"; } leakage_power () { - value : 99.9201; + value : 99.9283; when : "!A1&!A2&B1&Y"; } leakage_power () { - value : 144.701; + value : 144.709; when : "A1&!A2&B1&!Y"; } leakage_power () { - value : 169.691; + value : 169.7; when : "!A1&A2&B1&!Y"; } leakage_power () { - value : 162.422; + value : 162.43; when : "A1&A2&B1&!Y"; } pin (Y) { @@ -24532,52 +24606,52 @@ library (sg13g2_stdcell_typ_1p20V_25C) { index_1 ("0.0186, 0.0966, 0.174, 0.3294, 0.6408, 1.263, 2.5074"); index_2 ("0.001, 0.0234, 0.039, 0.0648, 0.108, 0.18, 0.3"); values ( \ - "0.0668415, 0.223627, 0.330984, 0.508018, 0.804765, 1.29807, 2.12143", \ - "0.0953483, 0.256032, 0.363672, 0.540956, 0.837477, 1.33134, 2.15476", \ - "0.113884, 0.283765, 0.391799, 0.569293, 0.86581, 1.36012, 2.18272", \ - "0.14018, 0.334521, 0.447091, 0.626565, 0.923634, 1.41808, 2.24234", \ - "0.177062, 0.419033, 0.545726, 0.737104, 1.04045, 1.5361, 2.35958", \ - "0.230108, 0.545586, 0.69841, 0.92049, 1.25197, 1.76604, 2.59242", \ - "0.311662, 0.729801, 0.929623, 1.20332, 1.59581, 2.17108, 3.04503" \ + "0.066851, 0.22364, 0.331, 0.50802, 0.804755, 1.29807, 2.12146", \ + "0.0953487, 0.256046, 0.36369, 0.540918, 0.837664, 1.33129, 2.15479", \ + "0.113884, 0.283766, 0.391801, 0.569279, 0.865658, 1.36012, 2.18252", \ + "0.14018, 0.334522, 0.447093, 0.626579, 0.923513, 1.41809, 2.24225", \ + "0.177063, 0.419034, 0.545728, 0.737106, 1.04058, 1.53599, 2.35877", \ + "0.230109, 0.545588, 0.698412, 0.920493, 1.25196, 1.76604, 2.59241", \ + "0.311663, 0.729803, 0.929625, 1.20332, 1.59581, 2.17108, 3.04504" \ ); } rise_transition (TIMING_DELAY_7x7ds1) { index_1 ("0.0186, 0.0966, 0.174, 0.3294, 0.6408, 1.263, 2.5074"); index_2 ("0.001, 0.0234, 0.039, 0.0648, 0.108, 0.18, 0.3"); values ( \ - "0.0474358, 0.261762, 0.410279, 0.655818, 1.06685, 1.7519, 2.89299", \ - "0.0536769, 0.262401, 0.41028, 0.655852, 1.06686, 1.75212, 2.89324", \ - "0.0633212, 0.266585, 0.411847, 0.656252, 1.06687, 1.75213, 2.89373", \ - "0.0835389, 0.2854, 0.425073, 0.662509, 1.0695, 1.75214, 2.89388", \ - "0.120539, 0.333303, 0.468549, 0.695649, 1.08687, 1.75719, 2.89389", \ - "0.17932, 0.42493, 0.564938, 0.787687, 1.16383, 1.80405, 2.91074", \ - "0.266678, 0.582877, 0.738382, 0.977089, 1.35459, 1.97799, 3.0323" \ + "0.047436, 0.261764, 0.410283, 0.65581, 1.06686, 1.75191, 2.89301", \ + "0.0536771, 0.262216, 0.410294, 0.655953, 1.06687, 1.75192, 2.89327", \ + "0.0633214, 0.266463, 0.411849, 0.655954, 1.06688, 1.75193, 2.89344", \ + "0.0835392, 0.28539, 0.425075, 0.66257, 1.07113, 1.75194, 2.89381", \ + "0.120539, 0.333314, 0.468552, 0.695653, 1.08687, 1.75722, 2.89382", \ + "0.17932, 0.424931, 0.56494, 0.787691, 1.16418, 1.80406, 2.90998", \ + "0.266678, 0.582878, 0.738384, 0.977093, 1.35459, 1.978, 3.03231" \ ); } cell_fall (TIMING_DELAY_7x7ds1) { index_1 ("0.0186, 0.0966, 0.174, 0.3294, 0.6408, 1.263, 2.5074"); index_2 ("0.001, 0.0234, 0.039, 0.0648, 0.108, 0.18, 0.3"); values ( \ - "0.0463427, 0.141384, 0.206096, 0.312835, 0.491527, 0.788969, 1.28459", \ - "0.0732122, 0.176555, 0.241735, 0.348663, 0.527427, 0.824863, 1.32033", \ - "0.089886, 0.206298, 0.274053, 0.382101, 0.560917, 0.858647, 1.35448", \ - "0.11147, 0.254549, 0.329951, 0.444608, 0.626838, 0.925009, 1.42063", \ - "0.137592, 0.328458, 0.419869, 0.550991, 0.749079, 1.05726, 1.55546", \ - "0.166737, 0.433131, 0.552685, 0.716619, 0.949946, 1.29328, 1.81636", \ - "0.199399, 0.565233, 0.732938, 0.954609, 1.25187, 1.66783, 2.264" \ + "0.0463237, 0.141391, 0.206097, 0.312838, 0.491524, 0.788777, 1.28458", \ + "0.0732121, 0.176555, 0.241778, 0.3487, 0.527427, 0.824857, 1.32033", \ + "0.0898708, 0.206283, 0.274097, 0.382101, 0.560981, 0.858405, 1.35449", \ + "0.11147, 0.254549, 0.32995, 0.444607, 0.626837, 0.92501, 1.42107", \ + "0.137591, 0.328458, 0.419869, 0.550991, 0.749079, 1.05726, 1.55545", \ + "0.166737, 0.43313, 0.552685, 0.716619, 0.949945, 1.29328, 1.81636", \ + "0.199399, 0.565233, 0.732937, 0.954609, 1.25187, 1.66783, 2.264" \ ); } fall_transition (TIMING_DELAY_7x7ds1) { index_1 ("0.0186, 0.0966, 0.174, 0.3294, 0.6408, 1.263, 2.5074"); index_2 ("0.001, 0.0234, 0.039, 0.0648, 0.108, 0.18, 0.3"); values ( \ - "0.0269104, 0.151718, 0.23836, 0.381335, 0.621126, 1.02113, 1.68595", \ - "0.0351213, 0.154848, 0.239735, 0.382081, 0.621464, 1.02114, 1.68596", \ - "0.0449714, 0.164581, 0.246295, 0.38504, 0.621851, 1.02115, 1.68597", \ - "0.0642585, 0.18845, 0.269198, 0.402079, 0.631236, 1.02308, 1.68598", \ - "0.0982637, 0.238164, 0.318697, 0.450858, 0.672014, 1.04781, 1.69529", \ - "0.153434, 0.32943, 0.41772, 0.552555, 0.773646, 1.13869, 1.7577", \ - "0.236086, 0.485764, 0.594246, 0.745283, 0.979111, 1.34781, 1.95527" \ + "0.0269136, 0.151718, 0.238375, 0.381335, 0.621125, 1.0205, 1.68595", \ + "0.0351213, 0.154848, 0.239767, 0.382483, 0.621465, 1.02051, 1.68596", \ + "0.0449798, 0.164536, 0.246419, 0.385039, 0.62156, 1.02204, 1.68597", \ + "0.0642585, 0.18845, 0.269198, 0.402078, 0.630881, 1.02313, 1.6869", \ + "0.0982636, 0.238164, 0.318697, 0.450858, 0.672014, 1.0478, 1.69529", \ + "0.153434, 0.32943, 0.417719, 0.552554, 0.773646, 1.13869, 1.7577", \ + "0.236087, 0.485763, 0.594245, 0.745284, 0.979111, 1.34781, 1.95527" \ ); } } @@ -24589,52 +24663,52 @@ library (sg13g2_stdcell_typ_1p20V_25C) { index_1 ("0.0186, 0.0966, 0.174, 0.3294, 0.6408, 1.263, 2.5074"); index_2 ("0.001, 0.0234, 0.039, 0.0648, 0.108, 0.18, 0.3"); values ( \ - "0.0584838, 0.216364, 0.323736, 0.501108, 0.797254, 1.29094, 2.11355", \ - "0.0878974, 0.251992, 0.359716, 0.537206, 0.834034, 1.32767, 2.1505", \ - "0.108542, 0.286795, 0.394957, 0.572486, 0.869307, 1.3633, 2.186", \ - "0.138326, 0.351492, 0.466028, 0.646014, 0.942668, 1.43697, 2.25916", \ - "0.182284, 0.454787, 0.590403, 0.787454, 1.09313, 1.58775, 2.4096", \ - "0.246029, 0.602823, 0.773941, 1.01491, 1.36082, 1.8818, 2.7062", \ - "0.341258, 0.812032, 1.03885, 1.34698, 1.78162, 2.39048, 3.28783" \ + "0.0584573, 0.216379, 0.3237, 0.501094, 0.797254, 1.29089, 2.11364", \ + "0.0878977, 0.251998, 0.359716, 0.537209, 0.834043, 1.32768, 2.15052", \ + "0.108542, 0.286796, 0.394945, 0.572425, 0.869032, 1.36346, 2.1865", \ + "0.138326, 0.351493, 0.466029, 0.645977, 0.942649, 1.43697, 2.25949", \ + "0.182284, 0.454788, 0.590405, 0.787468, 1.09312, 1.58775, 2.40961", \ + "0.24603, 0.602825, 0.773943, 1.01491, 1.36082, 1.8818, 2.70608", \ + "0.341259, 0.812034, 1.03885, 1.34698, 1.78163, 2.39046, 3.28784" \ ); } rise_transition (TIMING_DELAY_7x7ds1) { index_1 ("0.0186, 0.0966, 0.174, 0.3294, 0.6408, 1.263, 2.5074"); index_2 ("0.001, 0.0234, 0.039, 0.0648, 0.108, 0.18, 0.3"); values ( \ - "0.0473935, 0.261603, 0.410246, 0.655792, 1.06695, 1.7519, 2.89339", \ - "0.0592592, 0.262451, 0.410277, 0.655804, 1.06696, 1.75191, 2.8934", \ - "0.0731197, 0.270097, 0.412967, 0.656134, 1.06713, 1.75192, 2.89341", \ - "0.096614, 0.299724, 0.434017, 0.666049, 1.07218, 1.75192, 2.89342", \ - "0.13322, 0.367271, 0.499062, 0.71732, 1.09754, 1.76014, 2.89342", \ - "0.188532, 0.483719, 0.629001, 0.851293, 1.21398, 1.83248, 2.91911", \ - "0.276363, 0.666185, 0.843133, 1.10227, 1.48286, 2.0891, 3.10233" \ + "0.0474534, 0.261621, 0.410248, 0.655796, 1.06695, 1.75191, 2.89329", \ + "0.0592595, 0.262457, 0.410276, 0.655807, 1.06696, 1.75192, 2.8933", \ + "0.0731199, 0.270032, 0.413188, 0.656081, 1.06697, 1.75193, 2.89331", \ + "0.0966167, 0.299725, 0.434017, 0.666164, 1.07343, 1.75198, 2.89332", \ + "0.133221, 0.367271, 0.499064, 0.717236, 1.09753, 1.76015, 2.89344", \ + "0.188533, 0.48372, 0.629054, 0.851204, 1.21398, 1.83249, 2.9192", \ + "0.276363, 0.666185, 0.843136, 1.10227, 1.48289, 2.08907, 3.10234" \ ); } cell_fall (TIMING_DELAY_7x7ds1) { index_1 ("0.0186, 0.0966, 0.174, 0.3294, 0.6408, 1.263, 2.5074"); index_2 ("0.001, 0.0234, 0.039, 0.0648, 0.108, 0.18, 0.3"); values ( \ - "0.0393224, 0.133673, 0.19786, 0.304057, 0.481726, 0.777599, 1.27088", \ - "0.0625656, 0.168741, 0.233757, 0.340186, 0.518086, 0.81456, 1.30742", \ - "0.0752713, 0.197652, 0.26575, 0.373535, 0.551716, 0.848064, 1.34173", \ - "0.0903018, 0.244209, 0.320506, 0.435625, 0.617644, 0.914489, 1.40805", \ - "0.105905, 0.314431, 0.408094, 0.540585, 0.739224, 1.04678, 1.54334", \ - "0.119384, 0.412472, 0.536391, 0.703169, 0.938571, 1.28172, 1.80436", \ - "0.127418, 0.532428, 0.707497, 0.935265, 1.23622, 1.65535, 2.25106" \ + "0.0393356, 0.133657, 0.197858, 0.304057, 0.481726, 0.777598, 1.27088", \ + "0.0625656, 0.168741, 0.233757, 0.340191, 0.517945, 0.814554, 1.30742", \ + "0.0752713, 0.197642, 0.265728, 0.373548, 0.551716, 0.847917, 1.34173", \ + "0.0903018, 0.244209, 0.320506, 0.435625, 0.617644, 0.914507, 1.40805", \ + "0.105905, 0.314431, 0.408094, 0.540584, 0.739223, 1.04678, 1.54333", \ + "0.119384, 0.412472, 0.536391, 0.703169, 0.93857, 1.28172, 1.80436", \ + "0.127418, 0.532427, 0.707497, 0.935264, 1.23622, 1.65535, 2.25106" \ ); } fall_transition (TIMING_DELAY_7x7ds1) { index_1 ("0.0186, 0.0966, 0.174, 0.3294, 0.6408, 1.263, 2.5074"); index_2 ("0.001, 0.0234, 0.039, 0.0648, 0.108, 0.18, 0.3"); values ( \ - "0.0188672, 0.142381, 0.228451, 0.370835, 0.609246, 1.00653, 1.66987", \ - "0.0277319, 0.1458, 0.229845, 0.371224, 0.609329, 1.00687, 1.66988", \ - "0.0374523, 0.156024, 0.237091, 0.374965, 0.610099, 1.00695, 1.66989", \ - "0.0557066, 0.180395, 0.260065, 0.391917, 0.619872, 1.01015, 1.6699", \ - "0.0886534, 0.230223, 0.310163, 0.44189, 0.660644, 1.03437, 1.67867", \ - "0.14401, 0.322775, 0.409769, 0.545164, 0.764187, 1.1256, 1.74174", \ - "0.22915, 0.480815, 0.59062, 0.73829, 0.970723, 1.33607, 1.94033" \ + "0.0188656, 0.142355, 0.228445, 0.370835, 0.609246, 1.00653, 1.66987", \ + "0.0277319, 0.145799, 0.229843, 0.371229, 0.609247, 1.00687, 1.66988", \ + "0.0374523, 0.156021, 0.237122, 0.374677, 0.610099, 1.00688, 1.66989", \ + "0.0557066, 0.180395, 0.260064, 0.391921, 0.61986, 1.00884, 1.6699", \ + "0.0886533, 0.230223, 0.310162, 0.44189, 0.660643, 1.03463, 1.67837", \ + "0.14401, 0.322775, 0.409769, 0.545164, 0.764186, 1.1256, 1.74181", \ + "0.22915, 0.480815, 0.590619, 0.738289, 0.970722, 1.33607, 1.94032" \ ); } } @@ -24648,52 +24722,52 @@ library (sg13g2_stdcell_typ_1p20V_25C) { index_1 ("0.0186, 0.0966, 0.174, 0.3294, 0.6408, 1.263, 2.5074"); index_2 ("0.001, 0.0234, 0.039, 0.0648, 0.108, 0.18, 0.3"); values ( \ - "0.0262113, 0.103863, 0.156151, 0.242507, 0.386914, 0.627693, 1.0289", \ - "0.049992, 0.147256, 0.200681, 0.287231, 0.43188, 0.672791, 1.0747", \ - "0.0625123, 0.18345, 0.241251, 0.329751, 0.474512, 0.715363, 1.11694", \ - "0.0802571, 0.241576, 0.311932, 0.411152, 0.56194, 0.803997, 1.20556", \ - "0.103777, 0.328262, 0.421662, 0.547293, 0.722422, 0.979961, 1.38616", \ - "0.13537, 0.446501, 0.576663, 0.744918, 0.972709, 1.28196, 1.72688", \ - "0.176977, 0.604649, 0.788552, 1.02673, 1.33513, 1.7471, 2.29607" \ + "0.0262102, 0.103856, 0.156133, 0.242495, 0.386959, 0.627688, 1.02892", \ + "0.0499918, 0.14726, 0.20067, 0.287192, 0.431966, 0.67272, 1.07468", \ + "0.0625121, 0.183449, 0.241248, 0.329713, 0.47445, 0.715655, 1.11703", \ + "0.0802568, 0.241575, 0.311932, 0.41115, 0.561934, 0.804003, 1.20556", \ + "0.103776, 0.328261, 0.42166, 0.547291, 0.722418, 0.979949, 1.38612", \ + "0.135369, 0.4465, 0.576661, 0.744915, 0.972705, 1.28195, 1.72665", \ + "0.176976, 0.604647, 0.78855, 1.02672, 1.33512, 1.74709, 2.29606" \ ); } rise_transition (TIMING_DELAY_7x7ds1) { index_1 ("0.0186, 0.0966, 0.174, 0.3294, 0.6408, 1.263, 2.5074"); index_2 ("0.001, 0.0234, 0.039, 0.0648, 0.108, 0.18, 0.3"); values ( \ - "0.0165436, 0.123023, 0.197815, 0.321635, 0.528695, 0.873976, 1.44942", \ - "0.0336317, 0.129663, 0.20054, 0.321939, 0.528763, 0.873977, 1.45034", \ - "0.0458868, 0.146392, 0.212352, 0.327849, 0.529732, 0.874563, 1.45035", \ - "0.0652601, 0.184588, 0.248637, 0.356648, 0.546517, 0.879335, 1.45036", \ - "0.0972621, 0.254681, 0.325327, 0.432421, 0.610841, 0.920621, 1.46701", \ - "0.147627, 0.366798, 0.452996, 0.578481, 0.762623, 1.06068, 1.56306", \ - "0.230829, 0.539808, 0.663438, 0.81802, 1.04124, 1.35983, 1.86255" \ + "0.0165437, 0.123004, 0.197811, 0.321629, 0.528699, 0.873967, 1.44941", \ + "0.0336316, 0.129661, 0.200539, 0.321924, 0.5287, 0.873968, 1.45033", \ + "0.0458866, 0.146391, 0.212308, 0.327809, 0.529941, 0.87492, 1.45034", \ + "0.0652599, 0.184587, 0.248649, 0.356645, 0.546639, 0.879342, 1.45035", \ + "0.0972618, 0.25468, 0.325326, 0.43241, 0.610837, 0.920693, 1.46696", \ + "0.147626, 0.366796, 0.452994, 0.578479, 0.762619, 1.06078, 1.56284", \ + "0.230828, 0.539807, 0.663436, 0.818018, 1.04123, 1.35972, 1.86253" \ ); } cell_fall (TIMING_DELAY_7x7ds1) { index_1 ("0.0186, 0.0966, 0.174, 0.3294, 0.6408, 1.263, 2.5074"); index_2 ("0.001, 0.0234, 0.039, 0.0648, 0.108, 0.18, 0.3"); values ( \ - "0.0305325, 0.125421, 0.189685, 0.295857, 0.473533, 0.769475, 1.2627", \ - "0.0513187, 0.164905, 0.230136, 0.336448, 0.514298, 0.81075, 1.30396", \ - "0.0623565, 0.198658, 0.268314, 0.376429, 0.554242, 0.850408, 1.34397", \ - "0.0764785, 0.250706, 0.332275, 0.450627, 0.633447, 0.929889, 1.42266", \ - "0.0946925, 0.325776, 0.429484, 0.57201, 0.778373, 1.08925, 1.58432", \ - "0.116567, 0.429012, 0.565673, 0.750947, 1.00547, 1.36629, 1.89842", \ - "0.139551, 0.558188, 0.747135, 0.995308, 1.33004, 1.78661, 2.42144" \ + "0.0305321, 0.125411, 0.189691, 0.295867, 0.473659, 0.76942, 1.26269", \ + "0.051325, 0.164929, 0.230122, 0.336451, 0.514194, 0.810726, 1.30398", \ + "0.0623565, 0.198658, 0.268314, 0.376429, 0.554242, 0.850255, 1.34357", \ + "0.0764785, 0.250709, 0.332161, 0.450671, 0.633446, 0.929869, 1.42264", \ + "0.0946925, 0.325772, 0.429484, 0.57201, 0.778372, 1.08925, 1.58426", \ + "0.116578, 0.429012, 0.565673, 0.750947, 1.00547, 1.36629, 1.89842", \ + "0.139551, 0.558187, 0.747134, 0.995308, 1.33004, 1.78661, 2.42144" \ ); } fall_transition (TIMING_DELAY_7x7ds1) { index_1 ("0.0186, 0.0966, 0.174, 0.3294, 0.6408, 1.263, 2.5074"); index_2 ("0.001, 0.0234, 0.039, 0.0648, 0.108, 0.18, 0.3"); values ( \ - "0.0195124, 0.142295, 0.228479, 0.370836, 0.609248, 1.00719, 1.66871", \ - "0.0342463, 0.148771, 0.230977, 0.371267, 0.609249, 1.0072, 1.66882", \ - "0.0464056, 0.165159, 0.243086, 0.377349, 0.61055, 1.00721, 1.66883", \ - "0.0652064, 0.200939, 0.278262, 0.405075, 0.626141, 1.0108, 1.66884", \ - "0.0949955, 0.265841, 0.347802, 0.47714, 0.687835, 1.04935, 1.68415", \ - "0.142719, 0.370521, 0.471833, 0.612977, 0.834359, 1.1852, 1.78042", \ - "0.221304, 0.538925, 0.670486, 0.845773, 1.09813, 1.47495, 2.0666" \ + "0.0195124, 0.142568, 0.228478, 0.370835, 0.609264, 1.00642, 1.66871", \ + "0.0342935, 0.148765, 0.231106, 0.371271, 0.610028, 1.00654, 1.66881", \ + "0.0464056, 0.165228, 0.243086, 0.377349, 0.61055, 1.00655, 1.66882", \ + "0.0652064, 0.200945, 0.2783, 0.404849, 0.626141, 1.01077, 1.67049", \ + "0.0949955, 0.264911, 0.347801, 0.477139, 0.687834, 1.04948, 1.68244", \ + "0.1427, 0.370521, 0.471833, 0.612976, 0.834359, 1.18574, 1.78042", \ + "0.221304, 0.538924, 0.670486, 0.845773, 1.09813, 1.47495, 2.0666" \ ); } } @@ -24705,52 +24779,52 @@ library (sg13g2_stdcell_typ_1p20V_25C) { index_1 ("0.0186, 0.0966, 0.174, 0.3294, 0.6408, 1.263, 2.5074"); index_2 ("0.001, 0.0234, 0.039, 0.0648, 0.108, 0.18, 0.3"); values ( \ - "0.0262113, 0.103863, 0.156151, 0.242507, 0.386914, 0.627693, 1.0289", \ - "0.049992, 0.147256, 0.200681, 0.287231, 0.43188, 0.672791, 1.0747", \ - "0.0625123, 0.18345, 0.241251, 0.329751, 0.474512, 0.715363, 1.11694", \ - "0.0802571, 0.241576, 0.311932, 0.411152, 0.56194, 0.803997, 1.20556", \ - "0.103777, 0.328262, 0.421662, 0.547293, 0.722422, 0.979961, 1.38616", \ - "0.13537, 0.446501, 0.576663, 0.744918, 0.972709, 1.28196, 1.72688", \ - "0.176977, 0.604649, 0.788552, 1.02673, 1.33513, 1.7471, 2.29607" \ + "0.0262102, 0.103856, 0.156133, 0.242495, 0.386959, 0.627688, 1.02892", \ + "0.0499918, 0.14726, 0.20067, 0.287192, 0.431966, 0.67272, 1.07468", \ + "0.0625121, 0.183449, 0.241248, 0.329713, 0.47445, 0.715655, 1.11703", \ + "0.0802568, 0.241575, 0.311932, 0.41115, 0.561934, 0.804003, 1.20556", \ + "0.103776, 0.328261, 0.42166, 0.547291, 0.722418, 0.979949, 1.38612", \ + "0.135369, 0.4465, 0.576661, 0.744915, 0.972705, 1.28195, 1.72665", \ + "0.176976, 0.604647, 0.78855, 1.02672, 1.33512, 1.74709, 2.29606" \ ); } rise_transition (TIMING_DELAY_7x7ds1) { index_1 ("0.0186, 0.0966, 0.174, 0.3294, 0.6408, 1.263, 2.5074"); index_2 ("0.001, 0.0234, 0.039, 0.0648, 0.108, 0.18, 0.3"); values ( \ - "0.0165436, 0.123023, 0.197815, 0.321635, 0.528695, 0.873976, 1.44942", \ - "0.0336317, 0.129663, 0.20054, 0.321939, 0.528763, 0.873977, 1.45034", \ - "0.0458868, 0.146392, 0.212352, 0.327849, 0.529732, 0.874563, 1.45035", \ - "0.0652601, 0.184588, 0.248637, 0.356648, 0.546517, 0.879335, 1.45036", \ - "0.0972621, 0.254681, 0.325327, 0.432421, 0.610841, 0.920621, 1.46701", \ - "0.147627, 0.366798, 0.452996, 0.578481, 0.762623, 1.06068, 1.56306", \ - "0.230829, 0.539808, 0.663438, 0.81802, 1.04124, 1.35983, 1.86255" \ + "0.0165437, 0.123004, 0.197811, 0.321629, 0.528699, 0.873967, 1.44941", \ + "0.0336316, 0.129661, 0.200539, 0.321924, 0.5287, 0.873968, 1.45033", \ + "0.0458866, 0.146391, 0.212308, 0.327809, 0.529941, 0.87492, 1.45034", \ + "0.0652599, 0.184587, 0.248649, 0.356645, 0.546639, 0.879342, 1.45035", \ + "0.0972618, 0.25468, 0.325326, 0.43241, 0.610837, 0.920693, 1.46696", \ + "0.147626, 0.366796, 0.452994, 0.578479, 0.762619, 1.06078, 1.56284", \ + "0.230828, 0.539807, 0.663436, 0.818018, 1.04123, 1.35972, 1.86253" \ ); } cell_fall (TIMING_DELAY_7x7ds1) { index_1 ("0.0186, 0.0966, 0.174, 0.3294, 0.6408, 1.263, 2.5074"); index_2 ("0.001, 0.0234, 0.039, 0.0648, 0.108, 0.18, 0.3"); values ( \ - "0.0305325, 0.125421, 0.189685, 0.295857, 0.473533, 0.769475, 1.2627", \ - "0.0513187, 0.164905, 0.230136, 0.336448, 0.514298, 0.81075, 1.30396", \ - "0.0623565, 0.198658, 0.268314, 0.376429, 0.554242, 0.850408, 1.34397", \ - "0.0764785, 0.250706, 0.332275, 0.450627, 0.633447, 0.929889, 1.42266", \ - "0.0946925, 0.325776, 0.429484, 0.57201, 0.778373, 1.08925, 1.58432", \ - "0.116567, 0.429012, 0.565673, 0.750947, 1.00547, 1.36629, 1.89842", \ - "0.139551, 0.558188, 0.747135, 0.995308, 1.33004, 1.78661, 2.42144" \ + "0.0305321, 0.125411, 0.189691, 0.295867, 0.473659, 0.76942, 1.26269", \ + "0.051325, 0.164929, 0.230122, 0.336451, 0.514194, 0.810726, 1.30398", \ + "0.0623565, 0.198658, 0.268314, 0.376429, 0.554242, 0.850255, 1.34357", \ + "0.0764785, 0.250709, 0.332161, 0.450671, 0.633446, 0.929869, 1.42264", \ + "0.0946925, 0.325772, 0.429484, 0.57201, 0.778372, 1.08925, 1.58426", \ + "0.116578, 0.429012, 0.565673, 0.750947, 1.00547, 1.36629, 1.89842", \ + "0.139551, 0.558187, 0.747134, 0.995308, 1.33004, 1.78661, 2.42144" \ ); } fall_transition (TIMING_DELAY_7x7ds1) { index_1 ("0.0186, 0.0966, 0.174, 0.3294, 0.6408, 1.263, 2.5074"); index_2 ("0.001, 0.0234, 0.039, 0.0648, 0.108, 0.18, 0.3"); values ( \ - "0.0195124, 0.142295, 0.228479, 0.370836, 0.609248, 1.00719, 1.66871", \ - "0.0342463, 0.148771, 0.230977, 0.371267, 0.609249, 1.0072, 1.66882", \ - "0.0464056, 0.165159, 0.243086, 0.377349, 0.61055, 1.00721, 1.66883", \ - "0.0652064, 0.200939, 0.278262, 0.405075, 0.626141, 1.0108, 1.66884", \ - "0.0949955, 0.265841, 0.347802, 0.47714, 0.687835, 1.04935, 1.68415", \ - "0.142719, 0.370521, 0.471833, 0.612977, 0.834359, 1.1852, 1.78042", \ - "0.221304, 0.538925, 0.670486, 0.845773, 1.09813, 1.47495, 2.0666" \ + "0.0195124, 0.142568, 0.228478, 0.370835, 0.609264, 1.00642, 1.66871", \ + "0.0342935, 0.148765, 0.231106, 0.371271, 0.610028, 1.00654, 1.66881", \ + "0.0464056, 0.165228, 0.243086, 0.377349, 0.61055, 1.00655, 1.66882", \ + "0.0652064, 0.200945, 0.2783, 0.404849, 0.626141, 1.01077, 1.67049", \ + "0.0949955, 0.264911, 0.347801, 0.477139, 0.687834, 1.04948, 1.68244", \ + "0.1427, 0.370521, 0.471833, 0.612976, 0.834359, 1.18574, 1.78042", \ + "0.221304, 0.538924, 0.670486, 0.845773, 1.09813, 1.47495, 2.0666" \ ); } } @@ -24760,26 +24834,26 @@ library (sg13g2_stdcell_typ_1p20V_25C) { index_1 ("0.0186, 0.0966, 0.174, 0.3294, 0.6408, 1.263, 2.5074"); index_2 ("0.001, 0.0234, 0.039, 0.0648, 0.108, 0.18, 0.3"); values ( \ - "0.00512864, 0.00515496, 0.00512223, 0.00505939, 0.00495165, 0.00474265, 0.00450425", \ - "0.00491081, 0.0050378, 0.00502732, 0.00499002, 0.00489533, 0.00470395, 0.00446764", \ - "0.00486309, 0.00497935, 0.00496739, 0.00494043, 0.00485448, 0.00466263, 0.00446511", \ - "0.00492229, 0.00493158, 0.00501455, 0.00491055, 0.00486604, 0.00464677, 0.00451078", \ - "0.00538053, 0.00515183, 0.00504986, 0.00501997, 0.00485811, 0.00495435, 0.00438936", \ - "0.00702787, 0.00604476, 0.00582, 0.00556499, 0.00522524, 0.00505093, 0.00463723", \ - "0.0111132, 0.00895978, 0.0082789, 0.00761607, 0.00695923, 0.00598896, 0.00597044" \ + "0.00512954, 0.00515536, 0.00512221, 0.00505819, 0.00494773, 0.00474331, 0.00450588", \ + "0.00491095, 0.00503584, 0.00502979, 0.00499673, 0.00489761, 0.00468154, 0.00450658", \ + "0.0048589, 0.00498197, 0.00496743, 0.00493386, 0.00485169, 0.00466199, 0.00440958", \ + "0.00492298, 0.00493074, 0.00498486, 0.00490816, 0.0049154, 0.00465164, 0.00448929", \ + "0.00538048, 0.00515054, 0.00505047, 0.00501989, 0.00486189, 0.00495334, 0.00446268", \ + "0.00702692, 0.00604565, 0.00582083, 0.00558349, 0.00526022, 0.00504324, 0.00460987", \ + "0.0111131, 0.00895971, 0.00827836, 0.00761613, 0.00696065, 0.0059883, 0.00597074" \ ); } fall_power (POWER_7x7ds1) { index_1 ("0.0186, 0.0966, 0.174, 0.3294, 0.6408, 1.263, 2.5074"); index_2 ("0.001, 0.0234, 0.039, 0.0648, 0.108, 0.18, 0.3"); values ( \ - "0.00478681, 0.00477845, 0.00474236, 0.00465898, 0.00457231, 0.00441037, 0.00405704", \ - "0.00448721, 0.0046897, 0.00467567, 0.00460897, 0.00451295, 0.00430753, 0.00398637", \ - "0.00442599, 0.00458201, 0.0046275, 0.00455163, 0.00448997, 0.00430075, 0.00397287", \ - "0.00446786, 0.00459006, 0.00460466, 0.00455652, 0.00455928, 0.00450286, 0.00393933", \ - "0.00493069, 0.00477819, 0.00475048, 0.00470536, 0.00452841, 0.0044808, 0.00402936", \ - "0.00647101, 0.0056016, 0.00539975, 0.00524146, 0.00508369, 0.00464303, 0.00466251", \ - "0.0103405, 0.00832146, 0.00765324, 0.00706304, 0.00658184, 0.00603089, 0.00539653" \ + "0.00478476, 0.00477856, 0.00474092, 0.00465691, 0.00457213, 0.00438583, 0.0040573", \ + "0.0044891, 0.0046897, 0.00467709, 0.00462239, 0.00451297, 0.00433215, 0.00398583", \ + "0.00442781, 0.00458417, 0.00464016, 0.00455164, 0.00452646, 0.00444161, 0.00396254", \ + "0.00447048, 0.00459004, 0.00460481, 0.00455651, 0.00469486, 0.00448527, 0.00406192", \ + "0.00493179, 0.00477738, 0.00475048, 0.00470946, 0.00455836, 0.00483761, 0.00402894", \ + "0.006471, 0.00560136, 0.00540014, 0.00524146, 0.00506928, 0.00464309, 0.00472712", \ + "0.0103405, 0.0083214, 0.00765328, 0.00706303, 0.0065817, 0.00603083, 0.00539647" \ ); } } @@ -24789,26 +24863,26 @@ library (sg13g2_stdcell_typ_1p20V_25C) { index_1 ("0.0186, 0.0966, 0.174, 0.3294, 0.6408, 1.263, 2.5074"); index_2 ("0.001, 0.0234, 0.039, 0.0648, 0.108, 0.18, 0.3"); values ( \ - "0.00275279, 0.00288902, 0.00285701, 0.00280222, 0.00268935, 0.00249482, 0.00255979", \ - "0.00248707, 0.00269097, 0.00270997, 0.00269893, 0.00259622, 0.00241085, 0.0021364", \ - "0.0025644, 0.00264587, 0.00264464, 0.00264566, 0.0025952, 0.0023867, 0.00217445", \ - "0.00288755, 0.00266943, 0.00273611, 0.00262244, 0.00264585, 0.00239366, 0.00214609", \ - "0.00370524, 0.00309407, 0.00292932, 0.00284646, 0.00260069, 0.00280256, 0.00219097", \ - "0.0056529, 0.00439314, 0.00402759, 0.00364912, 0.00323107, 0.00315806, 0.00238484", \ - "0.00988522, 0.00764725, 0.00686427, 0.00602514, 0.00524693, 0.00409533, 0.00405169" \ + "0.00275159, 0.00288567, 0.00285505, 0.00280216, 0.0026902, 0.00249185, 0.0025673", \ + "0.00248181, 0.00269013, 0.00270996, 0.002699, 0.00260817, 0.00241004, 0.00213579", \ + "0.002565, 0.00263764, 0.0026563, 0.00263639, 0.00257808, 0.00240355, 0.00219674", \ + "0.00288907, 0.00266942, 0.00273689, 0.0026203, 0.00266993, 0.0023694, 0.0021003", \ + "0.00370744, 0.00309666, 0.00292895, 0.00284688, 0.00260051, 0.00280207, 0.00219121", \ + "0.00565349, 0.00439615, 0.00402604, 0.0036345, 0.00323459, 0.00316137, 0.00244738", \ + "0.00988482, 0.00764785, 0.00686435, 0.00603268, 0.00523693, 0.00409441, 0.00402049" \ ); } fall_power (POWER_7x7ds1) { index_1 ("0.0186, 0.0966, 0.174, 0.3294, 0.6408, 1.263, 2.5074"); index_2 ("0.001, 0.0234, 0.039, 0.0648, 0.108, 0.18, 0.3"); values ( \ - "0.00453213, 0.00485945, 0.00482988, 0.00478138, 0.00469964, 0.00450134, 0.00418966", \ - "0.00412182, 0.00473087, 0.00479095, 0.00475023, 0.00468611, 0.00453312, 0.00418743", \ - "0.00405377, 0.00457791, 0.00469544, 0.0046894, 0.00473828, 0.00452626, 0.00422501", \ - "0.00415263, 0.0044993, 0.00456054, 0.00461239, 0.00487067, 0.00456261, 0.00412145", \ - "0.00470588, 0.00457284, 0.00460911, 0.00467642, 0.00457324, 0.00482149, 0.00428258", \ - "0.00638033, 0.0053543, 0.00515902, 0.00512787, 0.00503558, 0.00463393, 0.00484059", \ - "0.0103881, 0.00802626, 0.0073999, 0.00678299, 0.00639558, 0.00595312, 0.00543436" \ + "0.00453392, 0.00485893, 0.00483038, 0.00478126, 0.00469947, 0.00450127, 0.00419034", \ + "0.00412182, 0.00473096, 0.0047943, 0.00475172, 0.00467612, 0.00453414, 0.00418789", \ + "0.00405345, 0.00457393, 0.0046957, 0.00468058, 0.00473828, 0.00446541, 0.00422502", \ + "0.00415282, 0.00449797, 0.00456051, 0.00461038, 0.00486971, 0.00462428, 0.00412923", \ + "0.00470588, 0.00457345, 0.00461576, 0.00467625, 0.00457379, 0.00494534, 0.00460007", \ + "0.00638033, 0.00535435, 0.00515863, 0.00512831, 0.00503459, 0.00463405, 0.00469837", \ + "0.0103879, 0.00802642, 0.00739987, 0.00678459, 0.00639556, 0.00595295, 0.00543394" \ ); } } @@ -24819,26 +24893,26 @@ library (sg13g2_stdcell_typ_1p20V_25C) { index_1 ("0.0186, 0.0966, 0.174, 0.3294, 0.6408, 1.263, 2.5074"); index_2 ("0.001, 0.0234, 0.039, 0.0648, 0.108, 0.18, 0.3"); values ( \ - "0.00172614, 0.00224959, 0.00224182, 0.00220133, 0.00209503, 0.0018985, 0.00156231", \ - "0.00156982, 0.00200902, 0.00204874, 0.0022122, 0.00203686, 0.00184844, 0.00160289", \ - "0.00172095, 0.00186158, 0.00200056, 0.00199799, 0.00194314, 0.00188272, 0.00148072", \ - "0.00217651, 0.0019384, 0.00190594, 0.00196395, 0.00189622, 0.0021478, 0.00146587", \ - "0.00323739, 0.00239059, 0.00227651, 0.00209773, 0.00200064, 0.00209578, 0.00168201", \ - "0.00572783, 0.00389131, 0.00342587, 0.00305927, 0.00272436, 0.00214507, 0.00246339", \ - "0.0107829, 0.00754259, 0.00668537, 0.00572767, 0.00482082, 0.00401679, 0.00288704" \ + "0.00172564, 0.00224781, 0.00224049, 0.00220024, 0.00208295, 0.00189875, 0.00156267", \ + "0.0015698, 0.00200947, 0.0020768, 0.00221065, 0.00202237, 0.00184429, 0.00160481", \ + "0.00172101, 0.00186157, 0.00200176, 0.00202016, 0.00193534, 0.00189794, 0.00148862", \ + "0.0021761, 0.00193811, 0.00191024, 0.00196397, 0.00191758, 0.00214324, 0.00143473", \ + "0.00323773, 0.0023906, 0.00228057, 0.00210233, 0.0020016, 0.00224817, 0.00154497", \ + "0.00572764, 0.00389153, 0.00342586, 0.0030594, 0.00272436, 0.00219218, 0.00234161", \ + "0.0107827, 0.00754278, 0.00668538, 0.00571879, 0.0048204, 0.00400198, 0.00299069" \ ); } fall_power (POWER_7x7ds1) { index_1 ("0.0186, 0.0966, 0.174, 0.3294, 0.6408, 1.263, 2.5074"); index_2 ("0.001, 0.0234, 0.039, 0.0648, 0.108, 0.18, 0.3"); values ( \ - "0.00241544, 0.00281654, 0.00280179, 0.00275412, 0.0026636, 0.00251224, 0.00217084", \ - "0.00221012, 0.00261587, 0.00263504, 0.00263875, 0.00259382, 0.00245013, 0.0021154", \ - "0.00234172, 0.00249498, 0.00259377, 0.00257479, 0.00253399, 0.0024179, 0.00211964", \ - "0.00276425, 0.00257808, 0.00256613, 0.00257588, 0.00273932, 0.00260707, 0.00205797", \ - "0.00376307, 0.00301402, 0.00288713, 0.00279005, 0.0026091, 0.00287647, 0.00216047", \ - "0.00606336, 0.00439658, 0.00402948, 0.00365263, 0.00334973, 0.00272085, 0.00292313", \ - "0.0109358, 0.0080023, 0.00711738, 0.00617509, 0.00545368, 0.0046096, 0.00373469" \ + "0.00241514, 0.00282891, 0.00280888, 0.00275467, 0.00265899, 0.00248429, 0.00217064", \ + "0.00221208, 0.00260991, 0.00265645, 0.00263884, 0.00264827, 0.00244951, 0.00211019", \ + "0.00234174, 0.00248684, 0.00259374, 0.00257478, 0.00252866, 0.00236844, 0.0021161", \ + "0.00276453, 0.00258101, 0.00255105, 0.00256896, 0.00273932, 0.00258261, 0.00223233", \ + "0.00376323, 0.00299042, 0.00288736, 0.00278986, 0.00260909, 0.00279556, 0.00204439", \ + "0.00606433, 0.00439696, 0.0040297, 0.00365277, 0.00334973, 0.00277628, 0.00292307", \ + "0.0109364, 0.00800233, 0.00711724, 0.00617477, 0.00545363, 0.00460966, 0.003733" \ ); } } @@ -24848,26 +24922,26 @@ library (sg13g2_stdcell_typ_1p20V_25C) { index_1 ("0.0186, 0.0966, 0.174, 0.3294, 0.6408, 1.263, 2.5074"); index_2 ("0.001, 0.0234, 0.039, 0.0648, 0.108, 0.18, 0.3"); values ( \ - "0.00172614, 0.00224959, 0.00224182, 0.00220133, 0.00209503, 0.0018985, 0.00156231", \ - "0.00156982, 0.00200902, 0.00204874, 0.0022122, 0.00203686, 0.00184844, 0.00160289", \ - "0.00172095, 0.00186158, 0.00200056, 0.00199799, 0.00194314, 0.00188272, 0.00148072", \ - "0.00217651, 0.0019384, 0.00190594, 0.00196395, 0.00189622, 0.0021478, 0.00146587", \ - "0.00323739, 0.00239059, 0.00227651, 0.00209773, 0.00200064, 0.00209578, 0.00168201", \ - "0.00572783, 0.00389131, 0.00342587, 0.00305927, 0.00272436, 0.00214507, 0.00246339", \ - "0.0107829, 0.00754259, 0.00668537, 0.00572767, 0.00482082, 0.00401679, 0.00288704" \ + "0.00172564, 0.00224781, 0.00224049, 0.00220024, 0.00208295, 0.00189875, 0.00156267", \ + "0.0015698, 0.00200947, 0.0020768, 0.00221065, 0.00202237, 0.00184429, 0.00160481", \ + "0.00172101, 0.00186157, 0.00200176, 0.00202016, 0.00193534, 0.00189794, 0.00148862", \ + "0.0021761, 0.00193811, 0.00191024, 0.00196397, 0.00191758, 0.00214324, 0.00143473", \ + "0.00323773, 0.0023906, 0.00228057, 0.00210233, 0.0020016, 0.00224817, 0.00154497", \ + "0.00572764, 0.00389153, 0.00342586, 0.0030594, 0.00272436, 0.00219218, 0.00234161", \ + "0.0107827, 0.00754278, 0.00668538, 0.00571879, 0.0048204, 0.00400198, 0.00299069" \ ); } fall_power (POWER_7x7ds1) { index_1 ("0.0186, 0.0966, 0.174, 0.3294, 0.6408, 1.263, 2.5074"); index_2 ("0.001, 0.0234, 0.039, 0.0648, 0.108, 0.18, 0.3"); values ( \ - "0.00241544, 0.00281654, 0.00280179, 0.00275412, 0.0026636, 0.00251224, 0.00217084", \ - "0.00221012, 0.00261587, 0.00263504, 0.00263875, 0.00259382, 0.00245013, 0.0021154", \ - "0.00234172, 0.00249498, 0.00259377, 0.00257479, 0.00253399, 0.0024179, 0.00211964", \ - "0.00276425, 0.00257808, 0.00256613, 0.00257588, 0.00273932, 0.00260707, 0.00205797", \ - "0.00376307, 0.00301402, 0.00288713, 0.00279005, 0.0026091, 0.00287647, 0.00216047", \ - "0.00606336, 0.00439658, 0.00402948, 0.00365263, 0.00334973, 0.00272085, 0.00292313", \ - "0.0109358, 0.0080023, 0.00711738, 0.00617509, 0.00545368, 0.0046096, 0.00373469" \ + "0.00241514, 0.00282891, 0.00280888, 0.00275467, 0.00265899, 0.00248429, 0.00217064", \ + "0.00221208, 0.00260991, 0.00265645, 0.00263884, 0.00264827, 0.00244951, 0.00211019", \ + "0.00234174, 0.00248684, 0.00259374, 0.00257478, 0.00252866, 0.00236844, 0.0021161", \ + "0.00276453, 0.00258101, 0.00255105, 0.00256896, 0.00273932, 0.00258261, 0.00223233", \ + "0.00376323, 0.00299042, 0.00288736, 0.00278986, 0.00260909, 0.00279556, 0.00204439", \ + "0.00606433, 0.00439696, 0.0040297, 0.00365277, 0.00334973, 0.00277628, 0.00292307", \ + "0.0109364, 0.00800233, 0.00711724, 0.00617477, 0.00545363, 0.00460966, 0.003733" \ ); } } @@ -24875,29 +24949,29 @@ library (sg13g2_stdcell_typ_1p20V_25C) { pin (A1) { direction : "input"; max_transition : 2.5074; - capacitance : 0.00337155; - rise_capacitance : 0.00346418; - rise_capacitance_range (0.00346418, 0.00346418); - fall_capacitance : 0.00327892; - fall_capacitance_range (0.00327892, 0.00327892); + capacitance : 0.00337156; + rise_capacitance : 0.00346414; + rise_capacitance_range (0.0030637, 0.00386132); + fall_capacitance : 0.00327897; + fall_capacitance_range (0.00289123, 0.00362431); } pin (A2) { direction : "input"; max_transition : 2.5074; - capacitance : 0.0033406; + capacitance : 0.00334058; rise_capacitance : 0.00352754; - rise_capacitance_range (0.00352754, 0.00352754); - fall_capacitance : 0.00315366; - fall_capacitance_range (0.00315366, 0.00315366); + rise_capacitance_range (0.00286207, 0.00406548); + fall_capacitance : 0.00315362; + fall_capacitance_range (0.00290225, 0.00332017); } pin (B1) { direction : "input"; max_transition : 2.5074; - capacitance : 0.00320963; - rise_capacitance : 0.00329962; - rise_capacitance_range (0.00329962, 0.00329962); + capacitance : 0.00320965; + rise_capacitance : 0.00329966; + rise_capacitance_range (0.00287115, 0.00371628); fall_capacitance : 0.00311964; - fall_capacitance_range (0.00311964, 0.00311964); + fall_capacitance_range (0.00271804, 0.00341728); } } cell (sg13g2_or2_1) { @@ -25103,18 +25177,18 @@ library (sg13g2_stdcell_typ_1p20V_25C) { max_transition : 2.5074; capacitance : 0.00246875; rise_capacitance : 0.0024593; - rise_capacitance_range (0.0024593, 0.0024593); + rise_capacitance_range (0.00228712, 0.00260066); fall_capacitance : 0.00247819; - fall_capacitance_range (0.00247819, 0.00247819); + fall_capacitance_range (0.00217871, 0.00272821); } pin (B) { direction : "input"; max_transition : 2.5074; capacitance : 0.00229712; rise_capacitance : 0.00234896; - rise_capacitance_range (0.00234896, 0.00234896); + rise_capacitance_range (0.00203095, 0.00256842); fall_capacitance : 0.00224527; - fall_capacitance_range (0.00224527, 0.00224527); + fall_capacitance_range (0.00205313, 0.00238245); } } cell (sg13g2_or2_2) { @@ -25320,18 +25394,18 @@ library (sg13g2_stdcell_typ_1p20V_25C) { max_transition : 2.5074; capacitance : 0.00245609; rise_capacitance : 0.00244437; - rise_capacitance_range (0.00244437, 0.00244437); + rise_capacitance_range (0.00230062, 0.00257268); fall_capacitance : 0.00246782; - fall_capacitance_range (0.00246782, 0.00246782); + fall_capacitance_range (0.0021808, 0.00269577); } pin (B) { direction : "input"; max_transition : 2.5074; capacitance : 0.00228363; rise_capacitance : 0.00233603; - rise_capacitance_range (0.00233603, 0.00233603); + rise_capacitance_range (0.00209818, 0.0025217); fall_capacitance : 0.00223122; - fall_capacitance_range (0.00223122, 0.00223122); + fall_capacitance_range (0.00207331, 0.00234653); } } cell (sg13g2_or3_1) { @@ -25639,27 +25713,27 @@ library (sg13g2_stdcell_typ_1p20V_25C) { max_transition : 2.5074; capacitance : 0.00259423; rise_capacitance : 0.00260481; - rise_capacitance_range (0.00260481, 0.00260481); + rise_capacitance_range (0.00244793, 0.00273534); fall_capacitance : 0.00258366; - fall_capacitance_range (0.00258366, 0.00258366); + fall_capacitance_range (0.00223168, 0.00291005); } pin (B) { direction : "input"; max_transition : 2.5074; capacitance : 0.00252763; rise_capacitance : 0.00256438; - rise_capacitance_range (0.00256438, 0.00256438); + rise_capacitance_range (0.00227831, 0.00276681); fall_capacitance : 0.00249088; - fall_capacitance_range (0.00249088, 0.00249088); + fall_capacitance_range (0.00213127, 0.00278871); } pin (C) { direction : "input"; max_transition : 2.5074; capacitance : 0.00240308; rise_capacitance : 0.00249939; - rise_capacitance_range (0.00249939, 0.00249939); + rise_capacitance_range (0.00212461, 0.00276802); fall_capacitance : 0.00230678; - fall_capacitance_range (0.00230678, 0.00230678); + fall_capacitance_range (0.00209251, 0.00245163); } } cell (sg13g2_or3_2) { @@ -25967,27 +26041,27 @@ library (sg13g2_stdcell_typ_1p20V_25C) { max_transition : 2.5074; capacitance : 0.00258569; rise_capacitance : 0.00259398; - rise_capacitance_range (0.00259398, 0.00259398); + rise_capacitance_range (0.00245247, 0.00271404); fall_capacitance : 0.00257739; - fall_capacitance_range (0.00257739, 0.00257739); + fall_capacitance_range (0.00223577, 0.00288832); } pin (B) { direction : "input"; max_transition : 2.5074; capacitance : 0.00252154; rise_capacitance : 0.00255633; - rise_capacitance_range (0.00255633, 0.00255633); + rise_capacitance_range (0.00230271, 0.0027391); fall_capacitance : 0.00248675; - fall_capacitance_range (0.00248675, 0.00248675); + fall_capacitance_range (0.0021356, 0.00277408); } pin (C) { direction : "input"; max_transition : 2.5074; capacitance : 0.00239671; rise_capacitance : 0.002495; - rise_capacitance_range (0.002495, 0.002495); + rise_capacitance_range (0.00220216, 0.00273298); fall_capacitance : 0.00229842; - fall_capacitance_range (0.00229842, 0.00229842); + fall_capacitance_range (0.00211928, 0.00242686); } } cell (sg13g2_or4_1) { @@ -26413,36 +26487,36 @@ library (sg13g2_stdcell_typ_1p20V_25C) { max_transition : 2.5074; capacitance : 0.00258785; rise_capacitance : 0.00260102; - rise_capacitance_range (0.00260102, 0.00260102); + rise_capacitance_range (0.00246119, 0.00272412); fall_capacitance : 0.00257468; - fall_capacitance_range (0.00257468, 0.00257468); + fall_capacitance_range (0.00223784, 0.00288288); } pin (B) { direction : "input"; max_transition : 2.5074; capacitance : 0.00249715; rise_capacitance : 0.00253225; - rise_capacitance_range (0.00253225, 0.00253225); + rise_capacitance_range (0.00227657, 0.00271814); fall_capacitance : 0.00246206; - fall_capacitance_range (0.00246206, 0.00246206); + fall_capacitance_range (0.00212247, 0.00278824); } pin (C) { direction : "input"; max_transition : 2.5074; capacitance : 0.00246439; rise_capacitance : 0.00251537; - rise_capacitance_range (0.00251537, 0.00251537); + rise_capacitance_range (0.00220062, 0.00275916); fall_capacitance : 0.00241342; - fall_capacitance_range (0.00241342, 0.00241342); + fall_capacitance_range (0.00206677, 0.00270086); } pin (D) { direction : "input"; max_transition : 2.5074; capacitance : 0.00238229; rise_capacitance : 0.00248657; - rise_capacitance_range (0.00248657, 0.00248657); + rise_capacitance_range (0.00212119, 0.00279433); fall_capacitance : 0.00227801; - fall_capacitance_range (0.00227801, 0.00227801); + fall_capacitance_range (0.0020813, 0.00240136); } } cell (sg13g2_or4_2) { @@ -26868,41 +26942,41 @@ library (sg13g2_stdcell_typ_1p20V_25C) { max_transition : 2.5074; capacitance : 0.00256792; rise_capacitance : 0.0025786; - rise_capacitance_range (0.0025786, 0.0025786); + rise_capacitance_range (0.0024494, 0.00269215); fall_capacitance : 0.00255723; - fall_capacitance_range (0.00255723, 0.00255723); + fall_capacitance_range (0.00222938, 0.00285432); } pin (B) { direction : "input"; max_transition : 2.5074; capacitance : 0.00249513; rise_capacitance : 0.00252724; - rise_capacitance_range (0.00252724, 0.00252724); + rise_capacitance_range (0.00228825, 0.0026985); fall_capacitance : 0.00246302; - fall_capacitance_range (0.00246302, 0.00246302); + fall_capacitance_range (0.00213196, 0.00277815); } pin (C) { direction : "input"; max_transition : 2.5074; capacitance : 0.0024635; rise_capacitance : 0.00251222; - rise_capacitance_range (0.00251222, 0.00251222); + rise_capacitance_range (0.00223191, 0.00273533); fall_capacitance : 0.00241478; - fall_capacitance_range (0.00241478, 0.00241478); + fall_capacitance_range (0.00207383, 0.00269396); } pin (D) { direction : "input"; max_transition : 2.5074; capacitance : 0.00237806; rise_capacitance : 0.00248319; - rise_capacitance_range (0.00248319, 0.00248319); + rise_capacitance_range (0.00219655, 0.00275298); fall_capacitance : 0.00227294; - fall_capacitance_range (0.00227294, 0.00227294); + fall_capacitance_range (0.0021089, 0.00238203); } } cell (sg13g2_sdfbbp_1) { area : 63.504; - cell_footprint : "sdfrrs"; + cell_footprint : "sdfbbp"; cell_leakage_power : 815.791; dont_touch : true; dont_use : true; @@ -26998,6 +27072,7 @@ library (sg13g2_stdcell_typ_1p20V_25C) { timing () { related_pin : "CLK"; sdf_cond : "SCE == 1'b1"; + sdf_edges : start_edge; timing_sense : non_unate; timing_type : rising_edge; when : "SCE"; @@ -27056,6 +27131,7 @@ library (sg13g2_stdcell_typ_1p20V_25C) { } timing () { related_pin : "CLK"; + sdf_edges : start_edge; timing_sense : non_unate; timing_type : rising_edge; cell_rise (TIMING_DELAY_7x7ds1) { @@ -27113,6 +27189,7 @@ library (sg13g2_stdcell_typ_1p20V_25C) { } timing () { related_pin : "RESET_B"; + sdf_edges : start_edge; timing_sense : positive_unate; timing_type : clear; cell_fall (TIMING_DELAY_7x7ds1) { @@ -27144,6 +27221,7 @@ library (sg13g2_stdcell_typ_1p20V_25C) { } timing () { related_pin : "SET_B"; + sdf_edges : start_edge; timing_sense : negative_unate; timing_type : preset; cell_rise (TIMING_DELAY_7x7ds1) { @@ -27283,6 +27361,7 @@ library (sg13g2_stdcell_typ_1p20V_25C) { timing () { related_pin : "CLK"; sdf_cond : "SCE == 1'b1"; + sdf_edges : start_edge; timing_sense : non_unate; timing_type : rising_edge; when : "SCE"; @@ -27341,6 +27420,7 @@ library (sg13g2_stdcell_typ_1p20V_25C) { } timing () { related_pin : "CLK"; + sdf_edges : start_edge; timing_sense : non_unate; timing_type : rising_edge; cell_rise (TIMING_DELAY_7x7ds1) { @@ -27398,6 +27478,7 @@ library (sg13g2_stdcell_typ_1p20V_25C) { } timing () { related_pin : "RESET_B"; + sdf_edges : start_edge; timing_sense : negative_unate; timing_type : preset; cell_rise (TIMING_DELAY_7x7ds1) { @@ -27429,6 +27510,7 @@ library (sg13g2_stdcell_typ_1p20V_25C) { } timing () { related_pin : "SET_B"; + sdf_edges : start_edge; timing_sense : positive_unate; timing_type : clear; cell_fall (TIMING_DELAY_7x7ds1) { @@ -27566,9 +27648,9 @@ library (sg13g2_stdcell_typ_1p20V_25C) { max_transition : 2.5074; capacitance : 0.00302108; rise_capacitance : 0.00306285; - rise_capacitance_range (0.00306285, 0.00306285); + rise_capacitance_range (0.00282375, 0.00325704); fall_capacitance : 0.00296886; - fall_capacitance_range (0.00296886, 0.00296886); + fall_capacitance_range (0.00276497, 0.00316623); timing () { related_pin : "CLK"; timing_type : min_pulse_width; @@ -27724,11 +27806,12 @@ library (sg13g2_stdcell_typ_1p20V_25C) { max_transition : 2.5074; capacitance : 0.00197833; rise_capacitance : 0.00200853; - rise_capacitance_range (0.00200853, 0.00200853); + rise_capacitance_range (0.00182954, 0.00212844); fall_capacitance : 0.00194812; - fall_capacitance_range (0.00194812, 0.00194812); + fall_capacitance_range (0.00179698, 0.00205079); timing () { related_pin : "CLK"; + sdf_edges : both_edges; timing_type : hold_rising; rise_constraint (CONSTRAINT_4x4) { index_1 ("0.0186, 0.51636, 1.263, 2.5074"); @@ -27753,6 +27836,7 @@ library (sg13g2_stdcell_typ_1p20V_25C) { } timing () { related_pin : "CLK"; + sdf_edges : both_edges; timing_type : setup_rising; rise_constraint (CONSTRAINT_4x4) { index_1 ("0.0186, 0.51636, 1.263, 2.5074"); @@ -27827,9 +27911,10 @@ library (sg13g2_stdcell_typ_1p20V_25C) { rise_capacitance : 0.00173907; rise_capacitance_range (0.00173907, 0.00173907); fall_capacitance : 0.00173907; - fall_capacitance_range (0.00173907, 0.00173907); + fall_capacitance_range (0.00164184, 0.00183433); timing () { related_pin : "CLK"; + sdf_edges : both_edges; timing_type : recovery_rising; rise_constraint (CONSTRAINT_4x4) { index_1 ("0.0186, 0.51636, 1.263, 2.5074"); @@ -27844,6 +27929,7 @@ library (sg13g2_stdcell_typ_1p20V_25C) { } timing () { related_pin : "CLK"; + sdf_edges : both_edges; timing_type : removal_rising; rise_constraint (CONSTRAINT_4x4) { index_1 ("0.0186, 0.51636, 1.263, 2.5074"); @@ -27873,11 +27959,12 @@ library (sg13g2_stdcell_typ_1p20V_25C) { max_transition : 2.5074; capacitance : 0.00197678; rise_capacitance : 0.00199638; - rise_capacitance_range (0.00199638, 0.00199638); + rise_capacitance_range (0.00178642, 0.00219026); fall_capacitance : 0.00195718; - fall_capacitance_range (0.00195718, 0.00195718); + fall_capacitance_range (0.00175481, 0.0021472); timing () { related_pin : "CLK"; + sdf_edges : both_edges; timing_type : hold_rising; rise_constraint (CONSTRAINT_4x4) { index_1 ("0.0186, 0.51636, 1.263, 2.5074"); @@ -27902,6 +27989,7 @@ library (sg13g2_stdcell_typ_1p20V_25C) { } timing () { related_pin : "CLK"; + sdf_edges : both_edges; timing_type : setup_rising; rise_constraint (CONSTRAINT_4x4) { index_1 ("0.0186, 0.51636, 1.263, 2.5074"); @@ -27975,11 +28063,12 @@ library (sg13g2_stdcell_typ_1p20V_25C) { max_transition : 2.5074; capacitance : 0.00354229; rise_capacitance : 0.00391477; - rise_capacitance_range (0.00391477, 0.00391477); + rise_capacitance_range (0.00391477, 0.00444092); fall_capacitance : 0.00316981; - fall_capacitance_range (0.00316981, 0.00316981); + fall_capacitance_range (0.00316981, 0.00418505); timing () { related_pin : "CLK"; + sdf_edges : both_edges; timing_type : hold_rising; rise_constraint (CONSTRAINT_4x4) { index_1 ("0.0186, 0.51636, 1.263, 2.5074"); @@ -28004,6 +28093,7 @@ library (sg13g2_stdcell_typ_1p20V_25C) { } timing () { related_pin : "CLK"; + sdf_edges : both_edges; timing_type : setup_rising; rise_constraint (CONSTRAINT_4x4) { index_1 ("0.0186, 0.51636, 1.263, 2.5074"); @@ -28108,9 +28198,10 @@ library (sg13g2_stdcell_typ_1p20V_25C) { rise_capacitance : 0.00524626; rise_capacitance_range (0.00524626, 0.00524626); fall_capacitance : 0.00524626; - fall_capacitance_range (0.00524626, 0.00524626); + fall_capacitance_range (0.00495292, 0.005527); timing () { related_pin : "CLK"; + sdf_edges : both_edges; timing_type : recovery_rising; rise_constraint (CONSTRAINT_4x4) { index_1 ("0.0186, 0.51636, 1.263, 2.5074"); @@ -28125,6 +28216,7 @@ library (sg13g2_stdcell_typ_1p20V_25C) { } timing () { related_pin : "CLK"; + sdf_edges : both_edges; timing_type : removal_rising; rise_constraint (CONSTRAINT_4x4) { index_1 ("0.0186, 0.51636, 1.263, 2.5074"); @@ -28139,6 +28231,7 @@ library (sg13g2_stdcell_typ_1p20V_25C) { } timing () { related_pin : "RESET_B"; + sdf_edges : both_edges; timing_type : non_seq_hold_rising; rise_constraint (CONSTRAINT_4x4) { index_1 ("0.0186, 0.51636, 1.263, 2.5074"); @@ -28153,6 +28246,7 @@ library (sg13g2_stdcell_typ_1p20V_25C) { } timing () { related_pin : "RESET_B"; + sdf_edges : both_edges; timing_type : non_seq_setup_rising; rise_constraint (CONSTRAINT_4x4) { index_1 ("0.0186, 0.51636, 1.263, 2.5074"); @@ -28177,12 +28271,12 @@ library (sg13g2_stdcell_typ_1p20V_25C) { } } ff (IQ,IQN) { - clear : "RESET_B'"; + clear : "!RESET_B"; clear_preset_var1 : "H"; clear_preset_var2 : "L"; clocked_on : "CLK"; - next_state : "(SCE*SCD)+(SCE'*D)"; - preset : "SET_B'"; + next_state : "(SCE*SCD)+(!SCE*D)"; + preset : "!SET_B"; } test_cell () { pin (Q) { @@ -28216,25 +28310,25 @@ library (sg13g2_stdcell_typ_1p20V_25C) { direction : input; } ff (IQ,IQN) { - clear : "RESET_B'"; + clear : "!RESET_B"; clear_preset_var1 : H; clear_preset_var2 : L; clocked_on : "CLK"; next_state : "D"; - preset : "SET_B'"; + preset : "!SET_B"; } } } cell (sg13g2_sdfrbp_1) { area : 68.9472; cell_footprint : "sdfrbp"; - cell_leakage_power : 825.03; + cell_leakage_power : 825.029; leakage_power () { - value : 735.263; + value : 735.262; when : "!CLK&!D&RESET_B&!SCD&!SCE&!Q&Q_N"; } leakage_power () { - value : 735.263; + value : 735.262; when : "!CLK&!D&RESET_B&!SCD&!SCE&Q&!Q_N"; } leakage_power () { @@ -28242,11 +28336,11 @@ library (sg13g2_stdcell_typ_1p20V_25C) { when : "!CLK&!D&!RESET_B&!SCD&!SCE&Q&!Q_N"; } leakage_power () { - value : 739.678; + value : 739.677; when : "CLK&!D&RESET_B&!SCD&!SCE&!Q"; } leakage_power () { - value : 739.647; + value : 739.646; when : "CLK&!D&RESET_B&!SCD&!SCE&Q&!Q_N"; } leakage_power () { @@ -28254,19 +28348,19 @@ library (sg13g2_stdcell_typ_1p20V_25C) { when : "!CLK&D&RESET_B&!SCD&!SCE&!Q&Q_N"; } leakage_power () { - value : 864.314; + value : 864.313; when : "!CLK&D&RESET_B&!SCD&!SCE&Q&!Q_N"; } leakage_power () { - value : 840.056; + value : 840.055; when : "CLK&D&RESET_B&!SCD&!SCE&!Q&Q_N"; } leakage_power () { - value : 882.894; + value : 882.893; when : "CLK&D&RESET_B&!SCD&!SCE&Q&!Q_N"; } leakage_power () { - value : 766.798; + value : 766.797; when : "!CLK&!D&RESET_B&!SCD&SCE&!Q&Q_N"; } leakage_power () { @@ -28274,7 +28368,7 @@ library (sg13g2_stdcell_typ_1p20V_25C) { when : "!CLK&!D&RESET_B&!SCD&SCE&Q&!Q_N"; } leakage_power () { - value : 905.767; + value : 905.768; when : "!CLK&!D&RESET_B&SCD&SCE&!Q&Q_N"; } leakage_power () { @@ -28282,11 +28376,11 @@ library (sg13g2_stdcell_typ_1p20V_25C) { when : "!CLK&!D&RESET_B&SCD&SCE&Q&!Q_N"; } leakage_power () { - value : 771.213; + value : 771.212; when : "CLK&!D&RESET_B&!SCD&SCE&!Q&Q_N"; } leakage_power () { - value : 884.596; + value : 884.595; when : "CLK&!D&RESET_B&!SCD&SCE&Q&!Q_N"; } leakage_power () { @@ -28305,6 +28399,7 @@ library (sg13g2_stdcell_typ_1p20V_25C) { timing () { related_pin : "CLK"; sdf_cond : "SCE == 1'b1"; + sdf_edges : start_edge; timing_sense : non_unate; timing_type : rising_edge; when : "SCE"; @@ -28312,7 +28407,7 @@ library (sg13g2_stdcell_typ_1p20V_25C) { index_1 ("0.0186, 0.0966, 0.174, 0.3294, 0.6408, 1.263, 2.5074"); index_2 ("0.001, 0.0234, 0.039, 0.0648, 0.108, 0.18, 0.3"); values ( \ - "0.190365, 0.249342, 0.292558, 0.364704, 0.48519, 0.686051, 1.02093", \ + "0.190365, 0.249361, 0.292562, 0.364613, 0.485083, 0.686136, 1.02091", \ "0.22819, 0.2874, 0.33075, 0.402673, 0.523183, 0.724502, 1.05919", \ "0.254069, 0.313166, 0.356541, 0.428506, 0.548893, 0.749759, 1.08478", \ "0.292693, 0.351655, 0.394963, 0.46683, 0.587316, 0.788148, 1.12297", \ @@ -28325,20 +28420,20 @@ library (sg13g2_stdcell_typ_1p20V_25C) { index_1 ("0.0186, 0.0966, 0.174, 0.3294, 0.6408, 1.263, 2.5074"); index_2 ("0.001, 0.0234, 0.039, 0.0648, 0.108, 0.18, 0.3"); values ( \ - "0.0204029, 0.104107, 0.166863, 0.270994, 0.445503, 0.73681, 1.22181", \ - "0.0204039, 0.104108, 0.166864, 0.271471, 0.445693, 0.737213, 1.22182", \ - "0.0204049, 0.104109, 0.166865, 0.271472, 0.445694, 0.737214, 1.22197", \ - "0.0204059, 0.10411, 0.166866, 0.271473, 0.445695, 0.737215, 1.22688", \ - "0.0204854, 0.104118, 0.166878, 0.271474, 0.445696, 0.737216, 1.22689", \ - "0.020863, 0.104151, 0.166898, 0.271475, 0.445697, 0.737217, 1.2269", \ - "0.021808, 0.10425, 0.16692, 0.271476, 0.445698, 0.737218, 1.22691" \ + "0.0204029, 0.104133, 0.166915, 0.270995, 0.445504, 0.736596, 1.22181", \ + "0.0204039, 0.104134, 0.166916, 0.271471, 0.445693, 0.737213, 1.22182", \ + "0.0204049, 0.104135, 0.166917, 0.271472, 0.445694, 0.737214, 1.22197", \ + "0.0204059, 0.104136, 0.166918, 0.271473, 0.445695, 0.737215, 1.22688", \ + "0.0204854, 0.104137, 0.166919, 0.271474, 0.445696, 0.737216, 1.22689", \ + "0.020863, 0.104151, 0.16692, 0.271475, 0.445697, 0.737217, 1.2269", \ + "0.021808, 0.10425, 0.166921, 0.271476, 0.445698, 0.737218, 1.22691" \ ); } cell_fall (TIMING_DELAY_7x7ds1) { index_1 ("0.0186, 0.0966, 0.174, 0.3294, 0.6408, 1.263, 2.5074"); index_2 ("0.001, 0.0234, 0.039, 0.0648, 0.108, 0.18, 0.3"); values ( \ - "0.172531, 0.223965, 0.258439, 0.315618, 0.410945, 0.570031, 0.834997", \ + "0.17253, 0.223965, 0.258439, 0.315618, 0.411064, 0.570031, 0.834997", \ "0.210167, 0.261714, 0.296274, 0.353301, 0.448707, 0.607787, 0.872713", \ "0.235656, 0.287231, 0.321788, 0.378795, 0.474228, 0.633288, 0.898236", \ "0.272552, 0.324091, 0.358663, 0.415654, 0.511123, 0.670026, 0.935022", \ @@ -28351,25 +28446,26 @@ library (sg13g2_stdcell_typ_1p20V_25C) { index_1 ("0.0186, 0.0966, 0.174, 0.3294, 0.6408, 1.263, 2.5074"); index_2 ("0.001, 0.0234, 0.039, 0.0648, 0.108, 0.18, 0.3"); values ( \ - "0.0162471, 0.0792802, 0.125514, 0.202473, 0.331767, 0.547469, 0.907098", \ - "0.0162481, 0.0792812, 0.125515, 0.202478, 0.331875, 0.547761, 0.907099", \ - "0.0162491, 0.0792822, 0.125555, 0.202479, 0.331887, 0.547762, 0.908326", \ - "0.0162501, 0.0792847, 0.125556, 0.202531, 0.331888, 0.547763, 0.908327", \ - "0.0162511, 0.0792849, 0.125557, 0.202532, 0.331889, 0.547764, 0.908328", \ - "0.0162521, 0.079285, 0.125558, 0.202533, 0.33189, 0.547765, 0.908329", \ - "0.0162531, 0.079286, 0.125559, 0.202534, 0.331891, 0.547766, 0.90833" \ + "0.0162476, 0.0792802, 0.125514, 0.202473, 0.331767, 0.547469, 0.907098", \ + "0.0162486, 0.0792812, 0.125515, 0.202478, 0.331875, 0.547761, 0.907099", \ + "0.0162496, 0.0792822, 0.125555, 0.202479, 0.331887, 0.547762, 0.908326", \ + "0.0162506, 0.0792847, 0.125556, 0.202531, 0.331888, 0.547763, 0.908327", \ + "0.0162516, 0.0792849, 0.125557, 0.202532, 0.331889, 0.547764, 0.908328", \ + "0.0162526, 0.079285, 0.125558, 0.202533, 0.33189, 0.547765, 0.908329", \ + "0.0162536, 0.079286, 0.125559, 0.202534, 0.331891, 0.547766, 0.90833" \ ); } } timing () { related_pin : "CLK"; + sdf_edges : start_edge; timing_sense : non_unate; timing_type : rising_edge; cell_rise (TIMING_DELAY_7x7ds1) { index_1 ("0.0186, 0.0966, 0.174, 0.3294, 0.6408, 1.263, 2.5074"); index_2 ("0.001, 0.0234, 0.039, 0.0648, 0.108, 0.18, 0.3"); values ( \ - "0.190365, 0.249342, 0.292558, 0.364704, 0.48519, 0.686051, 1.02093", \ + "0.190365, 0.249361, 0.292562, 0.364613, 0.485083, 0.686136, 1.02091", \ "0.22819, 0.2874, 0.33075, 0.402673, 0.523183, 0.724502, 1.05919", \ "0.254069, 0.313166, 0.356541, 0.428506, 0.548893, 0.749759, 1.08478", \ "0.292693, 0.351655, 0.394963, 0.46683, 0.587316, 0.788148, 1.12297", \ @@ -28382,20 +28478,20 @@ library (sg13g2_stdcell_typ_1p20V_25C) { index_1 ("0.0186, 0.0966, 0.174, 0.3294, 0.6408, 1.263, 2.5074"); index_2 ("0.001, 0.0234, 0.039, 0.0648, 0.108, 0.18, 0.3"); values ( \ - "0.0204029, 0.104107, 0.166863, 0.270994, 0.445503, 0.73681, 1.22181", \ - "0.0204039, 0.104108, 0.166864, 0.271471, 0.445693, 0.737213, 1.22182", \ - "0.0204049, 0.104109, 0.166865, 0.271472, 0.445694, 0.737214, 1.22197", \ - "0.0204059, 0.10411, 0.166866, 0.271473, 0.445695, 0.737215, 1.22688", \ - "0.0204854, 0.104118, 0.166878, 0.271474, 0.445696, 0.737216, 1.22689", \ - "0.020863, 0.104151, 0.166898, 0.271475, 0.445697, 0.737217, 1.2269", \ - "0.021808, 0.10425, 0.16692, 0.271476, 0.445698, 0.737218, 1.22691" \ + "0.0204029, 0.104133, 0.166915, 0.270995, 0.445504, 0.736596, 1.22181", \ + "0.0204039, 0.104134, 0.166916, 0.271471, 0.445693, 0.737213, 1.22182", \ + "0.0204049, 0.104135, 0.166917, 0.271472, 0.445694, 0.737214, 1.22197", \ + "0.0204059, 0.104136, 0.166918, 0.271473, 0.445695, 0.737215, 1.22688", \ + "0.0204854, 0.104137, 0.166919, 0.271474, 0.445696, 0.737216, 1.22689", \ + "0.020863, 0.104151, 0.16692, 0.271475, 0.445697, 0.737217, 1.2269", \ + "0.021808, 0.10425, 0.166921, 0.271476, 0.445698, 0.737218, 1.22691" \ ); } cell_fall (TIMING_DELAY_7x7ds1) { index_1 ("0.0186, 0.0966, 0.174, 0.3294, 0.6408, 1.263, 2.5074"); index_2 ("0.001, 0.0234, 0.039, 0.0648, 0.108, 0.18, 0.3"); values ( \ - "0.172531, 0.223965, 0.258439, 0.315618, 0.410945, 0.570031, 0.834997", \ + "0.17253, 0.223965, 0.258439, 0.315618, 0.411064, 0.570031, 0.834997", \ "0.210167, 0.261714, 0.296274, 0.353301, 0.448707, 0.607787, 0.872713", \ "0.235656, 0.287231, 0.321788, 0.378795, 0.474228, 0.633288, 0.898236", \ "0.272552, 0.324091, 0.358663, 0.415654, 0.511123, 0.670026, 0.935022", \ @@ -28408,44 +28504,45 @@ library (sg13g2_stdcell_typ_1p20V_25C) { index_1 ("0.0186, 0.0966, 0.174, 0.3294, 0.6408, 1.263, 2.5074"); index_2 ("0.001, 0.0234, 0.039, 0.0648, 0.108, 0.18, 0.3"); values ( \ - "0.0162471, 0.0792802, 0.125514, 0.202473, 0.331767, 0.547469, 0.907098", \ - "0.0162481, 0.0792812, 0.125515, 0.202478, 0.331875, 0.547761, 0.907099", \ - "0.0162491, 0.0792822, 0.125555, 0.202479, 0.331887, 0.547762, 0.908326", \ - "0.0162501, 0.0792847, 0.125556, 0.202531, 0.331888, 0.547763, 0.908327", \ - "0.0162511, 0.0792849, 0.125557, 0.202532, 0.331889, 0.547764, 0.908328", \ - "0.0162521, 0.079285, 0.125558, 0.202533, 0.33189, 0.547765, 0.908329", \ - "0.0162531, 0.079286, 0.125559, 0.202534, 0.331891, 0.547766, 0.90833" \ + "0.0162476, 0.0792802, 0.125514, 0.202473, 0.331767, 0.547469, 0.907098", \ + "0.0162486, 0.0792812, 0.125515, 0.202478, 0.331875, 0.547761, 0.907099", \ + "0.0162496, 0.0792822, 0.125555, 0.202479, 0.331887, 0.547762, 0.908326", \ + "0.0162506, 0.0792847, 0.125556, 0.202531, 0.331888, 0.547763, 0.908327", \ + "0.0162516, 0.0792849, 0.125557, 0.202532, 0.331889, 0.547764, 0.908328", \ + "0.0162526, 0.079285, 0.125558, 0.202533, 0.33189, 0.547765, 0.908329", \ + "0.0162536, 0.079286, 0.125559, 0.202534, 0.331891, 0.547766, 0.90833" \ ); } } timing () { related_pin : "RESET_B"; + sdf_edges : start_edge; timing_sense : positive_unate; timing_type : clear; cell_fall (TIMING_DELAY_7x7ds1) { index_1 ("0.0186, 0.0966, 0.174, 0.3294, 0.6408, 1.263, 2.5074"); index_2 ("0.001, 0.0234, 0.039, 0.0648, 0.108, 0.18, 0.3"); values ( \ - "0.242581, 0.294027, 0.328963, 0.388416, 0.492098, 0.671892, 0.979075", \ + "0.242558, 0.294114, 0.328962, 0.388416, 0.492086, 0.671897, 0.979075", \ "0.285759, 0.33717, 0.371866, 0.42994, 0.530591, 0.705753, 1.00816", \ "0.321401, 0.372934, 0.40752, 0.465077, 0.563911, 0.735781, 1.0341", \ "0.379614, 0.431395, 0.465587, 0.522809, 0.619679, 0.787078, 1.07794", \ "0.469182, 0.520805, 0.555153, 0.611874, 0.707695, 0.869764, 1.15065", \ "0.594137, 0.645128, 0.679353, 0.73727, 0.832789, 0.992233, 1.26226", \ - "0.763197, 0.812821, 0.846768, 0.905643, 1.00141, 1.15999, 1.42622" \ + "0.76336, 0.812821, 0.846768, 0.905534, 1.00116, 1.15999, 1.42622" \ ); } fall_transition (TIMING_DELAY_7x7ds1) { index_1 ("0.0186, 0.0966, 0.174, 0.3294, 0.6408, 1.263, 2.5074"); index_2 ("0.001, 0.0234, 0.039, 0.0648, 0.108, 0.18, 0.3"); values ( \ - "0.01599, 0.0791756, 0.125365, 0.202417, 0.331759, 0.547482, 0.90704", \ - "0.0160266, 0.079197, 0.125415, 0.202629, 0.331805, 0.547487, 0.907041", \ - "0.0160327, 0.079198, 0.125416, 0.20263, 0.331806, 0.54784, 0.907042", \ - "0.0160337, 0.079199, 0.125417, 0.202631, 0.331807, 0.547841, 0.907763", \ - "0.0161081, 0.0792, 0.125418, 0.202632, 0.33183, 0.547842, 0.907764", \ - "0.016239, 0.079201, 0.125465, 0.202633, 0.331831, 0.547843, 0.907765", \ - "0.016509, 0.079261, 0.125466, 0.202634, 0.331832, 0.547844, 0.907766" \ + "0.0160231, 0.0790994, 0.125362, 0.202417, 0.331762, 0.547482, 0.907039", \ + "0.0160266, 0.079197, 0.125415, 0.202629, 0.331805, 0.547487, 0.907047", \ + "0.0160327, 0.079198, 0.125416, 0.20263, 0.331806, 0.54784, 0.907048", \ + "0.0160337, 0.079199, 0.125417, 0.202631, 0.331807, 0.547841, 0.907764", \ + "0.0161081, 0.0792, 0.125418, 0.202632, 0.33183, 0.547842, 0.907765", \ + "0.016239, 0.079201, 0.125465, 0.202633, 0.331831, 0.547843, 0.907766", \ + "0.016505, 0.079261, 0.125466, 0.202634, 0.331832, 0.547844, 0.907767" \ ); } } @@ -28456,12 +28553,12 @@ library (sg13g2_stdcell_typ_1p20V_25C) { index_1 ("0.0186, 0.0966, 0.174, 0.3294, 0.6408, 1.263, 2.5074"); index_2 ("0.001, 0.0234, 0.039, 0.0648, 0.108, 0.18, 0.3"); values ( \ - "0.0293606, 0.0462574, 0.0575716, 0.0762312, 0.107261, 0.158938, 0.244874", \ + "0.0293606, 0.0462924, 0.057595, 0.0762193, 0.107254, 0.158917, 0.244855", \ "0.028917, 0.045902, 0.0571626, 0.0758834, 0.106892, 0.158552, 0.244614", \ "0.0288841, 0.0457601, 0.0571596, 0.0757829, 0.106919, 0.158509, 0.244509", \ "0.0291224, 0.0459657, 0.0573195, 0.0758996, 0.107152, 0.158542, 0.245752", \ "0.0299734, 0.0467529, 0.0580987, 0.0768373, 0.107762, 0.159737, 0.245438", \ - "0.0323019, 0.0489021, 0.0603304, 0.0789906, 0.110239, 0.161973, 0.248004", \ + "0.032302, 0.0489021, 0.0603304, 0.0789906, 0.110239, 0.161973, 0.248004", \ "0.0375194, 0.0539442, 0.0653425, 0.0839433, 0.115234, 0.167157, 0.253471" \ ); } @@ -28469,13 +28566,13 @@ library (sg13g2_stdcell_typ_1p20V_25C) { index_1 ("0.0186, 0.0966, 0.174, 0.3294, 0.6408, 1.263, 2.5074"); index_2 ("0.001, 0.0234, 0.039, 0.0648, 0.108, 0.18, 0.3"); values ( \ - "0.030445, 0.0472317, 0.0584696, 0.0769457, 0.10775, 0.159006, 0.244468", \ + "0.0304451, 0.0472317, 0.0584696, 0.0769465, 0.107789, 0.159006, 0.244468", \ "0.030137, 0.0470065, 0.0586098, 0.0766785, 0.107472, 0.158754, 0.244192", \ "0.0302632, 0.0470254, 0.058278, 0.0770567, 0.107598, 0.158808, 0.244645", \ "0.0306058, 0.0474763, 0.0587667, 0.0770813, 0.108087, 0.160357, 0.244617", \ "0.0316058, 0.0483661, 0.0597787, 0.0784021, 0.109426, 0.160325, 0.248379", \ - "0.0340054, 0.0507423, 0.0620517, 0.080736, 0.111952, 0.163689, 0.249043", \ - "0.0390725, 0.0557729, 0.0670519, 0.0856924, 0.116556, 0.168618, 0.255068" \ + "0.0340055, 0.0507423, 0.0620517, 0.080736, 0.111952, 0.163689, 0.249043", \ + "0.0390725, 0.0557728, 0.0670519, 0.0856924, 0.116556, 0.168618, 0.255068" \ ); } } @@ -28485,12 +28582,12 @@ library (sg13g2_stdcell_typ_1p20V_25C) { index_1 ("0.0186, 0.0966, 0.174, 0.3294, 0.6408, 1.263, 2.5074"); index_2 ("0.001, 0.0234, 0.039, 0.0648, 0.108, 0.18, 0.3"); values ( \ - "0.0293606, 0.0462574, 0.0575716, 0.0762312, 0.107261, 0.158938, 0.244874", \ + "0.0293606, 0.0462924, 0.057595, 0.0762193, 0.107254, 0.158917, 0.244855", \ "0.028917, 0.045902, 0.0571626, 0.0758834, 0.106892, 0.158552, 0.244614", \ "0.0288841, 0.0457601, 0.0571596, 0.0757829, 0.106919, 0.158509, 0.244509", \ "0.0291224, 0.0459657, 0.0573195, 0.0758996, 0.107152, 0.158542, 0.245752", \ "0.0299734, 0.0467529, 0.0580987, 0.0768373, 0.107762, 0.159737, 0.245438", \ - "0.0323019, 0.0489021, 0.0603304, 0.0789906, 0.110239, 0.161973, 0.248004", \ + "0.032302, 0.0489021, 0.0603304, 0.0789906, 0.110239, 0.161973, 0.248004", \ "0.0375194, 0.0539442, 0.0653425, 0.0839433, 0.115234, 0.167157, 0.253471" \ ); } @@ -28498,13 +28595,13 @@ library (sg13g2_stdcell_typ_1p20V_25C) { index_1 ("0.0186, 0.0966, 0.174, 0.3294, 0.6408, 1.263, 2.5074"); index_2 ("0.001, 0.0234, 0.039, 0.0648, 0.108, 0.18, 0.3"); values ( \ - "0.030445, 0.0472317, 0.0584696, 0.0769457, 0.10775, 0.159006, 0.244468", \ + "0.0304451, 0.0472317, 0.0584696, 0.0769465, 0.107789, 0.159006, 0.244468", \ "0.030137, 0.0470065, 0.0586098, 0.0766785, 0.107472, 0.158754, 0.244192", \ "0.0302632, 0.0470254, 0.058278, 0.0770567, 0.107598, 0.158808, 0.244645", \ "0.0306058, 0.0474763, 0.0587667, 0.0770813, 0.108087, 0.160357, 0.244617", \ "0.0316058, 0.0483661, 0.0597787, 0.0784021, 0.109426, 0.160325, 0.248379", \ - "0.0340054, 0.0507423, 0.0620517, 0.080736, 0.111952, 0.163689, 0.249043", \ - "0.0390725, 0.0557729, 0.0670519, 0.0856924, 0.116556, 0.168618, 0.255068" \ + "0.0340055, 0.0507423, 0.0620517, 0.080736, 0.111952, 0.163689, 0.249043", \ + "0.0390725, 0.0557728, 0.0670519, 0.0856924, 0.116556, 0.168618, 0.255068" \ ); } } @@ -28519,13 +28616,13 @@ library (sg13g2_stdcell_typ_1p20V_25C) { index_1 ("0.0186, 0.0966, 0.174, 0.3294, 0.6408, 1.263, 2.5074"); index_2 ("0.001, 0.0234, 0.039, 0.0648, 0.108, 0.18, 0.3"); values ( \ - "0.0312802, 0.0464322, 0.0566932, 0.0741291, 0.104706, 0.157979, 0.249477", \ - "0.0307631, 0.0461193, 0.056097, 0.073047, 0.102563, 0.154301, 0.244133", \ + "0.0312728, 0.0464446, 0.0566985, 0.0741291, 0.104704, 0.157982, 0.249477", \ + "0.0307631, 0.0461193, 0.056097, 0.073047, 0.102563, 0.154301, 0.244206", \ "0.030616, 0.045788, 0.0560596, 0.073015, 0.102376, 0.15217, 0.2406", \ - "0.0307372, 0.0459114, 0.0559911, 0.07269, 0.10148, 0.150023, 0.235853", \ - "0.0315161, 0.0467612, 0.0569698, 0.0737258, 0.101392, 0.148744, 0.233441", \ + "0.0307372, 0.0459114, 0.0559911, 0.07269, 0.10148, 0.150023, 0.235854", \ + "0.0315161, 0.0467612, 0.0569698, 0.0737258, 0.101392, 0.148744, 0.233432", \ "0.0338428, 0.0488491, 0.059155, 0.0759194, 0.103962, 0.150858, 0.228703", \ - "0.0388911, 0.0537866, 0.0641717, 0.0807744, 0.109118, 0.155827, 0.233635" \ + "0.0388977, 0.0537866, 0.0641717, 0.0807943, 0.109107, 0.155827, 0.233635" \ ); } } @@ -28538,6 +28635,7 @@ library (sg13g2_stdcell_typ_1p20V_25C) { timing () { related_pin : "CLK"; sdf_cond : "SCE == 1'b1"; + sdf_edges : start_edge; timing_sense : non_unate; timing_type : rising_edge; when : "SCE"; @@ -28545,7 +28643,7 @@ library (sg13g2_stdcell_typ_1p20V_25C) { index_1 ("0.0186, 0.0966, 0.174, 0.3294, 0.6408, 1.263, 2.5074"); index_2 ("0.001, 0.0234, 0.039, 0.0648, 0.108, 0.18, 0.3"); values ( \ - "0.13246, 0.214922, 0.259566, 0.331945, 0.451723, 0.65138, 0.983718", \ + "0.13246, 0.214922, 0.259566, 0.331798, 0.451747, 0.65138, 0.983692", \ "0.170109, 0.252553, 0.297399, 0.369554, 0.489412, 0.689122, 1.02223", \ "0.195524, 0.277943, 0.322798, 0.39484, 0.514864, 0.71463, 1.04757", \ "0.232476, 0.314839, 0.359661, 0.431719, 0.551697, 0.751277, 1.08375", \ @@ -28558,11 +28656,11 @@ library (sg13g2_stdcell_typ_1p20V_25C) { index_1 ("0.0186, 0.0966, 0.174, 0.3294, 0.6408, 1.263, 2.5074"); index_2 ("0.001, 0.0234, 0.039, 0.0648, 0.108, 0.18, 0.3"); values ( \ - "0.0251517, 0.112221, 0.171089, 0.272219, 0.444824, 0.734253, 1.21693", \ - "0.0251766, 0.112222, 0.17109, 0.27222, 0.444907, 0.734467, 1.21792", \ - "0.0251939, 0.112223, 0.171143, 0.272221, 0.444908, 0.734588, 1.21837", \ - "0.0253012, 0.112232, 0.171144, 0.272222, 0.444909, 0.734589, 1.21947", \ - "0.0253162, 0.112292, 0.171145, 0.272223, 0.44491, 0.73459, 1.21948", \ + "0.0251517, 0.112221, 0.171089, 0.272216, 0.444858, 0.734253, 1.21701", \ + "0.0251766, 0.112222, 0.17109, 0.272217, 0.444907, 0.734467, 1.21792", \ + "0.0251939, 0.112223, 0.171143, 0.272218, 0.444908, 0.734588, 1.21837", \ + "0.0253012, 0.112232, 0.171144, 0.272219, 0.444909, 0.734589, 1.21947", \ + "0.0253162, 0.112292, 0.171145, 0.27222, 0.44491, 0.73459, 1.21948", \ "0.0253172, 0.112321, 0.17116, 0.272268, 0.444911, 0.734591, 1.21949", \ "0.025445, 0.112322, 0.171161, 0.272269, 0.444912, 0.734592, 1.2195" \ ); @@ -28571,7 +28669,7 @@ library (sg13g2_stdcell_typ_1p20V_25C) { index_1 ("0.0186, 0.0966, 0.174, 0.3294, 0.6408, 1.263, 2.5074"); index_2 ("0.001, 0.0234, 0.039, 0.0648, 0.108, 0.18, 0.3"); values ( \ - "0.142343, 0.231824, 0.272006, 0.332546, 0.429491, 0.589637, 0.85616", \ + "0.14234, 0.23189, 0.272006, 0.332541, 0.429487, 0.589607, 0.856141", \ "0.180099, 0.26969, 0.309902, 0.370395, 0.467404, 0.627483, 0.894376", \ "0.205908, 0.295388, 0.335632, 0.395982, 0.493098, 0.653236, 0.919773", \ "0.244387, 0.333941, 0.374207, 0.434594, 0.531655, 0.691836, 0.958391", \ @@ -28584,8 +28682,8 @@ library (sg13g2_stdcell_typ_1p20V_25C) { index_1 ("0.0186, 0.0966, 0.174, 0.3294, 0.6408, 1.263, 2.5074"); index_2 ("0.001, 0.0234, 0.039, 0.0648, 0.108, 0.18, 0.3"); values ( \ - "0.0314555, 0.103194, 0.143767, 0.214747, 0.339936, 0.554155, 0.914846", \ - "0.0314565, 0.103224, 0.14384, 0.214766, 0.340003, 0.554156, 0.915089", \ + "0.0314597, 0.103201, 0.143766, 0.214745, 0.339937, 0.554295, 0.914892", \ + "0.0314607, 0.103224, 0.14384, 0.214766, 0.340003, 0.554296, 0.915089", \ "0.0315368, 0.103278, 0.143885, 0.214831, 0.340123, 0.554399, 0.915185", \ "0.0316918, 0.103398, 0.14395, 0.214832, 0.340124, 0.5544, 0.915186", \ "0.0323703, 0.103598, 0.143962, 0.214935, 0.340125, 0.554401, 0.915187", \ @@ -28596,13 +28694,14 @@ library (sg13g2_stdcell_typ_1p20V_25C) { } timing () { related_pin : "CLK"; + sdf_edges : start_edge; timing_sense : non_unate; timing_type : rising_edge; cell_rise (TIMING_DELAY_7x7ds1) { index_1 ("0.0186, 0.0966, 0.174, 0.3294, 0.6408, 1.263, 2.5074"); index_2 ("0.001, 0.0234, 0.039, 0.0648, 0.108, 0.18, 0.3"); values ( \ - "0.13246, 0.214922, 0.259566, 0.331945, 0.451723, 0.65138, 0.983718", \ + "0.13246, 0.214922, 0.259566, 0.331798, 0.451747, 0.65138, 0.983692", \ "0.170109, 0.252553, 0.297399, 0.369554, 0.489412, 0.689122, 1.02223", \ "0.195524, 0.277943, 0.322798, 0.39484, 0.514864, 0.71463, 1.04757", \ "0.232476, 0.314839, 0.359661, 0.431719, 0.551697, 0.751277, 1.08375", \ @@ -28615,11 +28714,11 @@ library (sg13g2_stdcell_typ_1p20V_25C) { index_1 ("0.0186, 0.0966, 0.174, 0.3294, 0.6408, 1.263, 2.5074"); index_2 ("0.001, 0.0234, 0.039, 0.0648, 0.108, 0.18, 0.3"); values ( \ - "0.0251517, 0.112221, 0.171089, 0.272219, 0.444824, 0.734253, 1.21693", \ - "0.0251766, 0.112222, 0.17109, 0.27222, 0.444907, 0.734467, 1.21792", \ - "0.0251939, 0.112223, 0.171143, 0.272221, 0.444908, 0.734588, 1.21837", \ - "0.0253012, 0.112232, 0.171144, 0.272222, 0.444909, 0.734589, 1.21947", \ - "0.0253162, 0.112292, 0.171145, 0.272223, 0.44491, 0.73459, 1.21948", \ + "0.0251517, 0.112221, 0.171089, 0.272216, 0.444858, 0.734253, 1.21701", \ + "0.0251766, 0.112222, 0.17109, 0.272217, 0.444907, 0.734467, 1.21792", \ + "0.0251939, 0.112223, 0.171143, 0.272218, 0.444908, 0.734588, 1.21837", \ + "0.0253012, 0.112232, 0.171144, 0.272219, 0.444909, 0.734589, 1.21947", \ + "0.0253162, 0.112292, 0.171145, 0.27222, 0.44491, 0.73459, 1.21948", \ "0.0253172, 0.112321, 0.17116, 0.272268, 0.444911, 0.734591, 1.21949", \ "0.025445, 0.112322, 0.171161, 0.272269, 0.444912, 0.734592, 1.2195" \ ); @@ -28628,7 +28727,7 @@ library (sg13g2_stdcell_typ_1p20V_25C) { index_1 ("0.0186, 0.0966, 0.174, 0.3294, 0.6408, 1.263, 2.5074"); index_2 ("0.001, 0.0234, 0.039, 0.0648, 0.108, 0.18, 0.3"); values ( \ - "0.142343, 0.231824, 0.272006, 0.332546, 0.429491, 0.589637, 0.85616", \ + "0.14234, 0.23189, 0.272006, 0.332541, 0.429487, 0.589607, 0.856141", \ "0.180099, 0.26969, 0.309902, 0.370395, 0.467404, 0.627483, 0.894376", \ "0.205908, 0.295388, 0.335632, 0.395982, 0.493098, 0.653236, 0.919773", \ "0.244387, 0.333941, 0.374207, 0.434594, 0.531655, 0.691836, 0.958391", \ @@ -28641,8 +28740,8 @@ library (sg13g2_stdcell_typ_1p20V_25C) { index_1 ("0.0186, 0.0966, 0.174, 0.3294, 0.6408, 1.263, 2.5074"); index_2 ("0.001, 0.0234, 0.039, 0.0648, 0.108, 0.18, 0.3"); values ( \ - "0.0314555, 0.103194, 0.143767, 0.214747, 0.339936, 0.554155, 0.914846", \ - "0.0314565, 0.103224, 0.14384, 0.214766, 0.340003, 0.554156, 0.915089", \ + "0.0314597, 0.103201, 0.143766, 0.214745, 0.339937, 0.554295, 0.914892", \ + "0.0314607, 0.103224, 0.14384, 0.214766, 0.340003, 0.554296, 0.915089", \ "0.0315368, 0.103278, 0.143885, 0.214831, 0.340123, 0.554399, 0.915185", \ "0.0316918, 0.103398, 0.14395, 0.214832, 0.340124, 0.5544, 0.915186", \ "0.0323703, 0.103598, 0.143962, 0.214935, 0.340125, 0.554401, 0.915187", \ @@ -28653,32 +28752,33 @@ library (sg13g2_stdcell_typ_1p20V_25C) { } timing () { related_pin : "RESET_B"; + sdf_edges : start_edge; timing_sense : negative_unate; timing_type : preset; cell_rise (TIMING_DELAY_7x7ds1) { index_1 ("0.0186, 0.0966, 0.174, 0.3294, 0.6408, 1.263, 2.5074"); index_2 ("0.001, 0.0234, 0.039, 0.0648, 0.108, 0.18, 0.3"); values ( \ - "0.20307, 0.283203, 0.327801, 0.399825, 0.519816, 0.71944, 1.05164", \ + "0.203001, 0.283203, 0.327857, 0.399779, 0.519769, 0.719427, 1.05165", \ "0.246309, 0.326415, 0.370825, 0.442919, 0.562945, 0.762536, 1.09505", \ "0.281778, 0.361945, 0.40657, 0.478582, 0.598637, 0.798239, 1.13068", \ "0.339951, 0.420293, 0.464896, 0.537058, 0.656914, 0.856659, 1.18939", \ "0.429041, 0.509853, 0.554204, 0.626557, 0.745983, 0.945813, 1.27812", \ "0.553698, 0.634655, 0.679559, 0.751269, 0.87127, 1.07048, 1.40327", \ - "0.720673, 0.802686, 0.847429, 0.920182, 1.03955, 1.23985, 1.57306" \ + "0.720673, 0.802686, 0.847429, 0.920393, 1.03955, 1.23985, 1.57284" \ ); } rise_transition (TIMING_DELAY_7x7ds1) { index_1 ("0.0186, 0.0966, 0.174, 0.3294, 0.6408, 1.263, 2.5074"); index_2 ("0.001, 0.0234, 0.039, 0.0648, 0.108, 0.18, 0.3"); values ( \ - "0.0255534, 0.110499, 0.169963, 0.271659, 0.444702, 0.734305, 1.21693", \ - "0.0255544, 0.1105, 0.169964, 0.27166, 0.444768, 0.734306, 1.21694", \ - "0.0255645, 0.110501, 0.169965, 0.271688, 0.445102, 0.734307, 1.21701", \ - "0.0258203, 0.110519, 0.169981, 0.271689, 0.445103, 0.734308, 1.21844", \ - "0.0263755, 0.1107, 0.170064, 0.27169, 0.445104, 0.734309, 1.21845", \ - "0.02756, 0.111033, 0.17019, 0.271691, 0.445105, 0.73431, 1.21846", \ - "0.029485, 0.111632, 0.170473, 0.271798, 0.445106, 0.734311, 1.21847" \ + "0.0254668, 0.110499, 0.169988, 0.271731, 0.444741, 0.734221, 1.21687", \ + "0.0255356, 0.1105, 0.169989, 0.271732, 0.444768, 0.734306, 1.21693", \ + "0.0255645, 0.110501, 0.16999, 0.271733, 0.445102, 0.734307, 1.21701", \ + "0.0258203, 0.110519, 0.169991, 0.271734, 0.445103, 0.734308, 1.21844", \ + "0.0263755, 0.1107, 0.170064, 0.271735, 0.445104, 0.734309, 1.21845", \ + "0.02756, 0.111033, 0.17019, 0.271736, 0.445105, 0.73431, 1.21846", \ + "0.029485, 0.111632, 0.170473, 0.2718, 0.445106, 0.734311, 1.21847" \ ); } } @@ -28689,7 +28789,7 @@ library (sg13g2_stdcell_typ_1p20V_25C) { index_1 ("0.0186, 0.0966, 0.174, 0.3294, 0.6408, 1.263, 2.5074"); index_2 ("0.001, 0.0234, 0.039, 0.0648, 0.108, 0.18, 0.3"); values ( \ - "0.030464, 0.0473676, 0.0586449, 0.0772921, 0.108308, 0.159872, 0.245909", \ + "0.030464, 0.0473676, 0.0586442, 0.0772691, 0.108329, 0.159872, 0.245828", \ "0.0301537, 0.0471386, 0.0583672, 0.077172, 0.108037, 0.159661, 0.24596", \ "0.0302552, 0.0471189, 0.0584732, 0.0772219, 0.108089, 0.159713, 0.246077", \ "0.0306256, 0.0475377, 0.0588213, 0.0773738, 0.108652, 0.160046, 0.246661", \ @@ -28702,7 +28802,7 @@ library (sg13g2_stdcell_typ_1p20V_25C) { index_1 ("0.0186, 0.0966, 0.174, 0.3294, 0.6408, 1.263, 2.5074"); index_2 ("0.001, 0.0234, 0.039, 0.0648, 0.108, 0.18, 0.3"); values ( \ - "0.0293718, 0.0461829, 0.0574308, 0.0759645, 0.106758, 0.158042, 0.243602", \ + "0.029371, 0.0461958, 0.0574444, 0.0759535, 0.106766, 0.158111, 0.243616", \ "0.0289085, 0.0457883, 0.0572138, 0.0755469, 0.106367, 0.157616, 0.243295", \ "0.0288983, 0.0456589, 0.0569506, 0.0757909, 0.106351, 0.15761, 0.243219", \ "0.0291231, 0.0459577, 0.0572209, 0.0756102, 0.106627, 0.159301, 0.243309", \ @@ -28718,7 +28818,7 @@ library (sg13g2_stdcell_typ_1p20V_25C) { index_1 ("0.0186, 0.0966, 0.174, 0.3294, 0.6408, 1.263, 2.5074"); index_2 ("0.001, 0.0234, 0.039, 0.0648, 0.108, 0.18, 0.3"); values ( \ - "0.030464, 0.0473676, 0.0586449, 0.0772921, 0.108308, 0.159872, 0.245909", \ + "0.030464, 0.0473676, 0.0586442, 0.0772691, 0.108329, 0.159872, 0.245828", \ "0.0301537, 0.0471386, 0.0583672, 0.077172, 0.108037, 0.159661, 0.24596", \ "0.0302552, 0.0471189, 0.0584732, 0.0772219, 0.108089, 0.159713, 0.246077", \ "0.0306256, 0.0475377, 0.0588213, 0.0773738, 0.108652, 0.160046, 0.246661", \ @@ -28731,7 +28831,7 @@ library (sg13g2_stdcell_typ_1p20V_25C) { index_1 ("0.0186, 0.0966, 0.174, 0.3294, 0.6408, 1.263, 2.5074"); index_2 ("0.001, 0.0234, 0.039, 0.0648, 0.108, 0.18, 0.3"); values ( \ - "0.0293718, 0.0461829, 0.0574308, 0.0759645, 0.106758, 0.158042, 0.243602", \ + "0.029371, 0.0461958, 0.0574444, 0.0759535, 0.106766, 0.158111, 0.243616", \ "0.0289085, 0.0457883, 0.0572138, 0.0755469, 0.106367, 0.157616, 0.243295", \ "0.0288983, 0.0456589, 0.0569506, 0.0757909, 0.106351, 0.15761, 0.243219", \ "0.0291231, 0.0459577, 0.0572209, 0.0756102, 0.106627, 0.159301, 0.243309", \ @@ -28747,13 +28847,13 @@ library (sg13g2_stdcell_typ_1p20V_25C) { index_1 ("0.0186, 0.0966, 0.174, 0.3294, 0.6408, 1.263, 2.5074"); index_2 ("0.001, 0.0234, 0.039, 0.0648, 0.108, 0.18, 0.3"); values ( \ - "0.0312909, 0.0465479, 0.0568844, 0.0744482, 0.105185, 0.15878, 0.250678", \ - "0.030777, 0.0460206, 0.0564078, 0.0733299, 0.103035, 0.155067, 0.245383", \ - "0.0306116, 0.0458681, 0.0562332, 0.0730831, 0.102202, 0.152999, 0.24182", \ + "0.0312841, 0.0465479, 0.056888, 0.0744359, 0.105233, 0.158779, 0.25078", \ + "0.030777, 0.0460206, 0.0562843, 0.0733299, 0.103035, 0.155067, 0.245383", \ + "0.0306116, 0.0458681, 0.0562332, 0.0730835, 0.102202, 0.152999, 0.24182", \ "0.0307307, 0.0459465, 0.0561822, 0.0730442, 0.101525, 0.150886, 0.237355", \ "0.031509, 0.0467993, 0.057055, 0.0738818, 0.101843, 0.14976, 0.232169", \ "0.0337627, 0.0489115, 0.059328, 0.076117, 0.104341, 0.15097, 0.230476", \ - "0.0390594, 0.0539749, 0.0645549, 0.0811187, 0.10947, 0.156175, 0.234288" \ + "0.0390594, 0.0539749, 0.0645549, 0.0811382, 0.10947, 0.156175, 0.234205" \ ); } fall_power (scalar) { @@ -28769,9 +28869,9 @@ library (sg13g2_stdcell_typ_1p20V_25C) { max_transition : 2.5074; capacitance : 0.00293824; rise_capacitance : 0.00297917; - rise_capacitance_range (0.00297917, 0.00297917); + rise_capacitance_range (0.00273107, 0.00317828); fall_capacitance : 0.00288563; - fall_capacitance_range (0.00288563, 0.00288563); + fall_capacitance_range (0.00267562, 0.00308449); timing () { related_pin : "CLK"; timing_type : min_pulse_width; @@ -28787,13 +28887,13 @@ library (sg13g2_stdcell_typ_1p20V_25C) { rise_power (passive_POWER_7x1ds1) { index_1 ("0.0186, 0.0966, 0.174, 0.3294, 0.6408, 1.263, 2.5074"); values ( \ - "0.0111134, 0.0107334, 0.0107347, 0.0109749, 0.0118986, 0.0140713, 0.01903" \ + "0.0111123, 0.0107334, 0.0107347, 0.0109749, 0.0118986, 0.0140713, 0.01903" \ ); } fall_power (passive_POWER_7x1ds1) { index_1 ("0.0186, 0.0966, 0.174, 0.3294, 0.6408, 1.263, 2.5074"); values ( \ - "0.0106355, 0.0103007, 0.0104007, 0.0106784, 0.0116041, 0.0138401, 0.0189006" \ + "0.0106374, 0.0103002, 0.0104007, 0.0106784, 0.0116041, 0.0138401, 0.0189005" \ ); } } @@ -28807,7 +28907,7 @@ library (sg13g2_stdcell_typ_1p20V_25C) { fall_power (passive_POWER_7x1ds1) { index_1 ("0.0186, 0.0966, 0.174, 0.3294, 0.6408, 1.263, 2.5074"); values ( \ - "0.0207881, 0.0204158, 0.0204626, 0.0207668, 0.0216004, 0.0238858, 0.0292355" \ + "0.0207882, 0.0204158, 0.0204626, 0.0207667, 0.0216004, 0.0238858, 0.0292355" \ ); } } @@ -28821,7 +28921,7 @@ library (sg13g2_stdcell_typ_1p20V_25C) { fall_power (passive_POWER_7x1ds1) { index_1 ("0.0186, 0.0966, 0.174, 0.3294, 0.6408, 1.263, 2.5074"); values ( \ - "0.0189194, 0.0186374, 0.0187845, 0.0191343, 0.0201672, 0.0225672, 0.0278123" \ + "0.0189194, 0.0186349, 0.0187845, 0.0191343, 0.0201672, 0.0225672, 0.0278123" \ ); } } @@ -28845,13 +28945,13 @@ library (sg13g2_stdcell_typ_1p20V_25C) { rise_power (passive_POWER_7x1ds1) { index_1 ("0.0186, 0.0966, 0.174, 0.3294, 0.6408, 1.263, 2.5074"); values ( \ - "0.0111168, 0.0107313, 0.0107348, 0.0109749, 0.0118988, 0.0140715, 0.0190301" \ + "0.0111181, 0.0107313, 0.0107348, 0.0109749, 0.0118988, 0.0140715, 0.0190301" \ ); } fall_power (passive_POWER_7x1ds1) { index_1 ("0.0186, 0.0966, 0.174, 0.3294, 0.6408, 1.263, 2.5074"); values ( \ - "0.0106404, 0.0102872, 0.0104008, 0.0106785, 0.0116043, 0.0138402, 0.0189012" \ + "0.0106423, 0.0102872, 0.0104008, 0.0106785, 0.0116043, 0.0138402, 0.0189011" \ ); } } @@ -28860,13 +28960,13 @@ library (sg13g2_stdcell_typ_1p20V_25C) { rise_power (passive_POWER_7x1ds1) { index_1 ("0.0186, 0.0966, 0.174, 0.3294, 0.6408, 1.263, 2.5074"); values ( \ - "0.0104373, 0.0100854, 0.0100673, 0.0103222, 0.0112037, 0.0133893, 0.0183268" \ + "0.010437, 0.0100854, 0.0100673, 0.0103222, 0.0112037, 0.0133893, 0.0183268" \ ); } fall_power (passive_POWER_7x1ds1) { index_1 ("0.0186, 0.0966, 0.174, 0.3294, 0.6408, 1.263, 2.5074"); values ( \ - "0.00963465, 0.00929368, 0.00939424, 0.00967053, 0.0105791, 0.0128308, 0.0178944" \ + "0.00963868, 0.00929369, 0.00939425, 0.00967054, 0.0105791, 0.0128309, 0.0178944" \ ); } } @@ -28875,13 +28975,13 @@ library (sg13g2_stdcell_typ_1p20V_25C) { rise_power (passive_POWER_7x1ds1) { index_1 ("0.0186, 0.0966, 0.174, 0.3294, 0.6408, 1.263, 2.5074"); values ( \ - "0.0108453, 0.0104847, 0.0104712, 0.0107249, 0.0116315, 0.0138079, 0.018753" \ + "0.0108453, 0.0104848, 0.0104713, 0.0107249, 0.0116315, 0.0138079, 0.018753" \ ); } fall_power (passive_POWER_7x1ds1) { index_1 ("0.0186, 0.0966, 0.174, 0.3294, 0.6408, 1.263, 2.5074"); values ( \ - "0.0108392, 0.0104933, 0.0106004, 0.0108765, 0.0117925, 0.0140344, 0.0191003" \ + "0.010833, 0.0104933, 0.0106004, 0.0108766, 0.0117925, 0.0140344, 0.0191003" \ ); } } @@ -28895,7 +28995,7 @@ library (sg13g2_stdcell_typ_1p20V_25C) { fall_power (passive_POWER_7x1ds1) { index_1 ("0.0186, 0.0966, 0.174, 0.3294, 0.6408, 1.263, 2.5074"); values ( \ - "0.0108392, 0.0104933, 0.0106004, 0.0108765, 0.0117925, 0.0140344, 0.0191003" \ + "0.0108409, 0.0104906, 0.0105991, 0.0108761, 0.0117921, 0.014034, 0.0190999" \ ); } } @@ -28906,11 +29006,12 @@ library (sg13g2_stdcell_typ_1p20V_25C) { max_transition : 2.5074; capacitance : 0.00277037; rise_capacitance : 0.00280332; - rise_capacitance_range (0.00280332, 0.00280332); + rise_capacitance_range (0.00246652, 0.00305426); fall_capacitance : 0.00273743; - fall_capacitance_range (0.00273743, 0.00273743); + fall_capacitance_range (0.0024218, 0.00292538); timing () { related_pin : "CLK"; + sdf_edges : both_edges; timing_type : hold_rising; rise_constraint (CONSTRAINT_4x4) { index_1 ("0.0186, 0.51636, 1.263, 2.5074"); @@ -28935,6 +29036,7 @@ library (sg13g2_stdcell_typ_1p20V_25C) { } timing () { related_pin : "CLK"; + sdf_edges : both_edges; timing_type : setup_rising; rise_constraint (CONSTRAINT_4x4) { index_1 ("0.0186, 0.51636, 1.263, 2.5074"); @@ -28952,7 +29054,7 @@ library (sg13g2_stdcell_typ_1p20V_25C) { values ( \ "0.220067, 0.092592, 0.0144316, -0.0639326", \ "0.351665, 0.224088, 0.145888, 0.0681273", \ - "0.448488, 0.320901, 0.242853, 0.162556", \ + "0.445917, 0.320901, 0.242853, 0.162556", \ "0.552337, 0.426693, 0.345935, 0.265638" \ ); } @@ -28962,13 +29064,13 @@ library (sg13g2_stdcell_typ_1p20V_25C) { rise_power (passive_POWER_7x1ds1) { index_1 ("0.0186, 0.0966, 0.174, 0.3294, 0.6408, 1.263, 2.5074"); values ( \ - "0.0210247, 0.0206783, 0.0206854, 0.0208149, 0.0214959, 0.0232408, 0.027356" \ + "0.0210284, 0.0206783, 0.0206854, 0.0208149, 0.0214959, 0.0232408, 0.027356" \ ); } fall_power (passive_POWER_7x1ds1) { index_1 ("0.0186, 0.0966, 0.174, 0.3294, 0.6408, 1.263, 2.5074"); values ( \ - "0.0202801, 0.0199692, 0.0200594, 0.0203637, 0.0212285, 0.0232748, 0.027853" \ + "0.0202788, 0.0199692, 0.0200594, 0.0203637, 0.0212285, 0.0232748, 0.027853" \ ); } } @@ -28976,13 +29078,13 @@ library (sg13g2_stdcell_typ_1p20V_25C) { rise_power (passive_POWER_7x1ds1) { index_1 ("0.0186, 0.0966, 0.174, 0.3294, 0.6408, 1.263, 2.5074"); values ( \ - "0.0210247, 0.0206783, 0.0206854, 0.0208149, 0.0214959, 0.0232408, 0.027356" \ + "0.0210284, 0.0206783, 0.0206854, 0.0208149, 0.0214959, 0.0232408, 0.027356" \ ); } fall_power (passive_POWER_7x1ds1) { index_1 ("0.0186, 0.0966, 0.174, 0.3294, 0.6408, 1.263, 2.5074"); values ( \ - "0.0202801, 0.0199692, 0.0200594, 0.0203637, 0.0212285, 0.0232748, 0.027853" \ + "0.0202788, 0.0199692, 0.0200594, 0.0203637, 0.0212285, 0.0232748, 0.027853" \ ); } } @@ -28990,13 +29092,14 @@ library (sg13g2_stdcell_typ_1p20V_25C) { pin (RESET_B) { direction : input; max_transition : 2.5074; - capacitance : 0.00510894; - rise_capacitance : 0.00510894; - rise_capacitance_range (0.00510894, 0.00510894); - fall_capacitance : 0.00510894; - fall_capacitance_range (0.00510894, 0.00510894); + capacitance : 0.00510895; + rise_capacitance : 0.00510895; + rise_capacitance_range (0.00510895, 0.00510895); + fall_capacitance : 0.00510895; + fall_capacitance_range (0.00477389, 0.00531762); timing () { related_pin : "CLK"; + sdf_edges : both_edges; timing_type : recovery_rising; rise_constraint (CONSTRAINT_4x4) { index_1 ("0.0186, 0.51636, 1.263, 2.5074"); @@ -29011,6 +29114,7 @@ library (sg13g2_stdcell_typ_1p20V_25C) { } timing () { related_pin : "CLK"; + sdf_edges : both_edges; timing_type : removal_rising; rise_constraint (CONSTRAINT_4x4) { index_1 ("0.0186, 0.51636, 1.263, 2.5074"); @@ -29040,11 +29144,12 @@ library (sg13g2_stdcell_typ_1p20V_25C) { max_transition : 2.5074; capacitance : 0.00288527; rise_capacitance : 0.00290716; - rise_capacitance_range (0.00290716, 0.00290716); + rise_capacitance_range (0.00257229, 0.00315632); fall_capacitance : 0.00284148; - fall_capacitance_range (0.00284148, 0.00284148); + fall_capacitance_range (0.00253016, 0.0030285); timing () { related_pin : "CLK"; + sdf_edges : both_edges; timing_type : hold_rising; rise_constraint (CONSTRAINT_4x4) { index_1 ("0.0186, 0.51636, 1.263, 2.5074"); @@ -29069,6 +29174,7 @@ library (sg13g2_stdcell_typ_1p20V_25C) { } timing () { related_pin : "CLK"; + sdf_edges : both_edges; timing_type : setup_rising; rise_constraint (CONSTRAINT_4x4) { index_1 ("0.0186, 0.51636, 1.263, 2.5074"); @@ -29102,7 +29208,7 @@ library (sg13g2_stdcell_typ_1p20V_25C) { fall_power (passive_POWER_7x1ds1) { index_1 ("0.0186, 0.0966, 0.174, 0.3294, 0.6408, 1.263, 2.5074"); values ( \ - "0.0177159, 0.0173881, 0.0174603, 0.0177789, 0.0186763, 0.0206949, 0.0253291" \ + "0.017697, 0.0173881, 0.0174603, 0.0177789, 0.0186763, 0.0206949, 0.0253291" \ ); } } @@ -29116,7 +29222,7 @@ library (sg13g2_stdcell_typ_1p20V_25C) { fall_power (passive_POWER_7x1ds1) { index_1 ("0.0186, 0.0966, 0.174, 0.3294, 0.6408, 1.263, 2.5074"); values ( \ - "0.0177159, 0.0173881, 0.0174603, 0.0177789, 0.0186763, 0.0206949, 0.0253291" \ + "0.017697, 0.0173881, 0.0174603, 0.0177789, 0.0186763, 0.0206949, 0.0253291" \ ); } } @@ -29127,17 +29233,18 @@ library (sg13g2_stdcell_typ_1p20V_25C) { max_transition : 2.5074; capacitance : 0.0048441; rise_capacitance : 0.00508762; - rise_capacitance_range (0.00508762, 0.00508762); + rise_capacitance_range (0.0044493, 0.00578189); fall_capacitance : 0.00460058; - fall_capacitance_range (0.00460058, 0.00460058); + fall_capacitance_range (0.00441043, 0.00509962); timing () { related_pin : "CLK"; + sdf_edges : both_edges; timing_type : hold_rising; rise_constraint (CONSTRAINT_4x4) { index_1 ("0.0186, 0.51636, 1.263, 2.5074"); index_2 ("0.0186, 0.51636, 1.263, 2.5074"); values ( \ - "-0.141821, -0.0900962, -0.0581518, -0.0197167", \ + "-0.141821, -0.0900962, -0.0555801, -0.0197167", \ "-0.266807, -0.216449, -0.182602, -0.145099", \ "-0.353333, -0.302544, -0.267138, -0.230355", \ "-0.439005, -0.390956, -0.357235, -0.315815" \ @@ -29156,6 +29263,7 @@ library (sg13g2_stdcell_typ_1p20V_25C) { } timing () { related_pin : "CLK"; + sdf_edges : both_edges; timing_type : setup_rising; rise_constraint (CONSTRAINT_4x4) { index_1 ("0.0186, 0.51636, 1.263, 2.5074"); @@ -29183,13 +29291,13 @@ library (sg13g2_stdcell_typ_1p20V_25C) { rise_power (passive_POWER_7x1ds1) { index_1 ("0.0186, 0.0966, 0.174, 0.3294, 0.6408, 1.263, 2.5074"); values ( \ - "0.0229376, 0.022679, 0.0227056, 0.0229132, 0.0235125, 0.0250056, 0.0284011" \ + "0.0229378, 0.022679, 0.0227056, 0.0229132, 0.0235125, 0.0250056, 0.0284011" \ ); } fall_power (passive_POWER_7x1ds1) { index_1 ("0.0186, 0.0966, 0.174, 0.3294, 0.6408, 1.263, 2.5074"); values ( \ - "0.0259471, 0.0257322, 0.02574, 0.0260335, 0.026642, 0.0281826, 0.0316475" \ + "0.0259457, 0.0257322, 0.02574, 0.0260335, 0.026642, 0.0281826, 0.0316475" \ ); } } @@ -29198,7 +29306,7 @@ library (sg13g2_stdcell_typ_1p20V_25C) { rise_power (passive_POWER_7x1ds1) { index_1 ("0.0186, 0.0966, 0.174, 0.3294, 0.6408, 1.263, 2.5074"); values ( \ - "0.0257216, 0.0253053, 0.0253105, 0.025609, 0.0266332, 0.0295493, 0.0364143" \ + "0.0257211, 0.0253053, 0.0253105, 0.025609, 0.0266332, 0.0295493, 0.0364143" \ ); } fall_power (passive_POWER_7x1ds1) { @@ -29212,7 +29320,7 @@ library (sg13g2_stdcell_typ_1p20V_25C) { rise_power (passive_POWER_7x1ds1) { index_1 ("0.0186, 0.0966, 0.174, 0.3294, 0.6408, 1.263, 2.5074"); values ( \ - "0.0257216, 0.0253053, 0.0253105, 0.025609, 0.0266332, 0.0295493, 0.0364143" \ + "0.0257211, 0.0253053, 0.0253105, 0.025609, 0.0266332, 0.0295493, 0.0364143" \ ); } fall_power (passive_POWER_7x1ds1) { @@ -29224,9 +29332,9 @@ library (sg13g2_stdcell_typ_1p20V_25C) { } } ff (IQ,IQN) { - clear : "RESET_B'"; + clear : "!RESET_B"; clocked_on : "CLK"; - next_state : "(SCE*SCD)+(SCE'*D)"; + next_state : "(SCE*SCD)+(!SCE*D)"; } test_cell () { pin (Q) { @@ -29257,7 +29365,7 @@ library (sg13g2_stdcell_typ_1p20V_25C) { signal_type : test_scan_enable; } ff (IQ,IQN) { - clear : "RESET_B'"; + clear : "!RESET_B"; clocked_on : "CLK"; next_state : "D"; } @@ -29280,11 +29388,11 @@ library (sg13g2_stdcell_typ_1p20V_25C) { when : "!CLK&!D&!RESET_B&!SCD&!SCE&Q&!Q_N"; } leakage_power () { - value : 865.593; + value : 865.591; when : "CLK&!D&RESET_B&!SCD&!SCE&!Q"; } leakage_power () { - value : 865.559; + value : 865.557; when : "CLK&!D&RESET_B&!SCD&!SCE&Q&!Q_N"; } leakage_power () { @@ -29292,11 +29400,11 @@ library (sg13g2_stdcell_typ_1p20V_25C) { when : "!CLK&D&RESET_B&!SCD&!SCE&!Q&Q_N"; } leakage_power () { - value : 990.232; + value : 990.234; when : "!CLK&D&RESET_B&!SCD&!SCE&Q&!Q_N"; } leakage_power () { - value : 965.969; + value : 965.971; when : "CLK&D&RESET_B&!SCD&!SCE&!Q&Q_N"; } leakage_power () { @@ -29320,7 +29428,7 @@ library (sg13g2_stdcell_typ_1p20V_25C) { when : "!CLK&!D&RESET_B&SCD&SCE&Q&!Q_N"; } leakage_power () { - value : 897.117; + value : 897.116; when : "CLK&!D&RESET_B&!SCD&SCE&!Q&Q_N"; } leakage_power () { @@ -29328,7 +29436,7 @@ library (sg13g2_stdcell_typ_1p20V_25C) { when : "CLK&!D&RESET_B&!SCD&SCE&Q&!Q_N"; } leakage_power () { - value : 997.498; + value : 997.497; when : "CLK&!D&RESET_B&SCD&SCE&!Q&Q_N"; } leakage_power () { @@ -29343,6 +29451,7 @@ library (sg13g2_stdcell_typ_1p20V_25C) { timing () { related_pin : "CLK"; sdf_cond : "SCE == 1'b1"; + sdf_edges : start_edge; timing_sense : non_unate; timing_type : rising_edge; when : "SCE"; @@ -29350,8 +29459,8 @@ library (sg13g2_stdcell_typ_1p20V_25C) { index_1 ("0.0186, 0.0966, 0.174, 0.3294, 0.6408, 1.263, 2.5074"); index_2 ("0.001, 0.0468, 0.078, 0.1296, 0.216, 0.36, 0.6"); values ( \ - "0.24353, 0.297662, 0.339909, 0.411172, 0.531371, 0.732236, 1.06724", \ - "0.28142, 0.335391, 0.377722, 0.448876, 0.569098, 0.770195, 1.10542", \ + "0.243573, 0.297662, 0.339917, 0.411174, 0.531352, 0.732182, 1.06727", \ + "0.28142, 0.335391, 0.377722, 0.448876, 0.569098, 0.770195, 1.10529", \ "0.307161, 0.361123, 0.403306, 0.474611, 0.594837, 0.795758, 1.13095", \ "0.345666, 0.399562, 0.441813, 0.513098, 0.633209, 0.834186, 1.16963", \ "0.401324, 0.455478, 0.497656, 0.568968, 0.689184, 0.889954, 1.22502", \ @@ -29363,20 +29472,20 @@ library (sg13g2_stdcell_typ_1p20V_25C) { index_1 ("0.0186, 0.0966, 0.174, 0.3294, 0.6408, 1.263, 2.5074"); index_2 ("0.001, 0.0468, 0.078, 0.1296, 0.216, 0.36, 0.6"); values ( \ - "0.0230343, 0.105874, 0.168025, 0.272144, 0.447015, 0.738573, 1.22509", \ - "0.0230446, 0.105875, 0.168026, 0.27224, 0.447016, 0.738588, 1.2251", \ - "0.0230456, 0.105876, 0.168027, 0.272241, 0.447017, 0.738659, 1.22511", \ - "0.0230486, 0.105877, 0.168028, 0.272242, 0.447018, 0.73866, 1.22716", \ - "0.0230649, 0.105886, 0.168029, 0.272243, 0.44706, 0.738661, 1.22717", \ - "0.023192, 0.105908, 0.16803, 0.272244, 0.447061, 0.738662, 1.22718", \ - "0.023604, 0.106031, 0.168031, 0.272245, 0.447062, 0.738663, 1.22719" \ + "0.0230623, 0.105874, 0.168026, 0.272144, 0.447016, 0.738668, 1.22454", \ + "0.0230633, 0.105875, 0.168027, 0.27224, 0.447017, 0.738669, 1.22467", \ + "0.0230643, 0.105876, 0.168028, 0.272241, 0.447018, 0.73867, 1.22468", \ + "0.0230653, 0.105877, 0.168029, 0.272242, 0.447019, 0.738671, 1.22716", \ + "0.0230663, 0.105886, 0.16803, 0.272243, 0.44706, 0.738672, 1.22717", \ + "0.023192, 0.105908, 0.168031, 0.272244, 0.447061, 0.738673, 1.22718", \ + "0.023604, 0.106031, 0.168032, 0.272245, 0.447062, 0.738674, 1.22719" \ ); } cell_fall (TIMING_DELAY_7x7ds1) { index_1 ("0.0186, 0.0966, 0.174, 0.3294, 0.6408, 1.263, 2.5074"); index_2 ("0.001, 0.0468, 0.078, 0.1296, 0.216, 0.36, 0.6"); values ( \ - "0.209545, 0.261419, 0.295848, 0.353159, 0.449121, 0.609165, 0.876051", \ + "0.209545, 0.261376, 0.295853, 0.353033, 0.449121, 0.609221, 0.876029", \ "0.247402, 0.299324, 0.333886, 0.39123, 0.487227, 0.647197, 0.914447", \ "0.272841, 0.324701, 0.359246, 0.416453, 0.512402, 0.672579, 0.939358", \ "0.309923, 0.361936, 0.396404, 0.453653, 0.54958, 0.709625, 0.976502", \ @@ -29389,26 +29498,27 @@ library (sg13g2_stdcell_typ_1p20V_25C) { index_1 ("0.0186, 0.0966, 0.174, 0.3294, 0.6408, 1.263, 2.5074"); index_2 ("0.001, 0.0468, 0.078, 0.1296, 0.216, 0.36, 0.6"); values ( \ - "0.0192966, 0.083384, 0.129142, 0.20635, 0.33644, 0.553713, 0.915945", \ - "0.0192976, 0.0834019, 0.129143, 0.206354, 0.336441, 0.553784, 0.916367", \ - "0.0192986, 0.0834181, 0.129171, 0.206355, 0.336615, 0.555079, 0.916368", \ - "0.0192996, 0.0834191, 0.129228, 0.206356, 0.336616, 0.55508, 0.916369", \ - "0.0193018, 0.0834201, 0.129229, 0.206423, 0.336617, 0.555081, 0.91637", \ - "0.019316, 0.0834211, 0.12923, 0.206424, 0.336618, 0.555082, 0.916371", \ - "0.019317, 0.0834221, 0.129231, 0.206425, 0.336619, 0.555083, 0.916442" \ + "0.0192965, 0.0833893, 0.129229, 0.206349, 0.33644, 0.553712, 0.915878", \ + "0.0192975, 0.0834019, 0.12923, 0.206354, 0.336441, 0.553784, 0.916367", \ + "0.0192985, 0.0834181, 0.129231, 0.206355, 0.336615, 0.555079, 0.916368", \ + "0.0192995, 0.0834191, 0.129232, 0.206356, 0.336616, 0.55508, 0.916369", \ + "0.0193018, 0.0834201, 0.129233, 0.206423, 0.336617, 0.555081, 0.91637", \ + "0.019316, 0.0834211, 0.129234, 0.206424, 0.336618, 0.555082, 0.916371", \ + "0.019317, 0.0834221, 0.129235, 0.206425, 0.336619, 0.555083, 0.916442" \ ); } } timing () { related_pin : "CLK"; + sdf_edges : start_edge; timing_sense : non_unate; timing_type : rising_edge; cell_rise (TIMING_DELAY_7x7ds1) { index_1 ("0.0186, 0.0966, 0.174, 0.3294, 0.6408, 1.263, 2.5074"); index_2 ("0.001, 0.0468, 0.078, 0.1296, 0.216, 0.36, 0.6"); values ( \ - "0.24353, 0.297662, 0.339909, 0.411172, 0.531371, 0.732236, 1.06724", \ - "0.28142, 0.335391, 0.377722, 0.448876, 0.569098, 0.770195, 1.10542", \ + "0.243573, 0.297662, 0.339917, 0.411174, 0.531352, 0.732182, 1.06727", \ + "0.28142, 0.335391, 0.377722, 0.448876, 0.569098, 0.770195, 1.10529", \ "0.307161, 0.361123, 0.403306, 0.474611, 0.594837, 0.795758, 1.13095", \ "0.345666, 0.399562, 0.441813, 0.513098, 0.633209, 0.834186, 1.16963", \ "0.401324, 0.455478, 0.497656, 0.568968, 0.689184, 0.889954, 1.22502", \ @@ -29420,20 +29530,20 @@ library (sg13g2_stdcell_typ_1p20V_25C) { index_1 ("0.0186, 0.0966, 0.174, 0.3294, 0.6408, 1.263, 2.5074"); index_2 ("0.001, 0.0468, 0.078, 0.1296, 0.216, 0.36, 0.6"); values ( \ - "0.0230343, 0.105874, 0.168025, 0.272144, 0.447015, 0.738573, 1.22509", \ - "0.0230446, 0.105875, 0.168026, 0.27224, 0.447016, 0.738588, 1.2251", \ - "0.0230456, 0.105876, 0.168027, 0.272241, 0.447017, 0.738659, 1.22511", \ - "0.0230486, 0.105877, 0.168028, 0.272242, 0.447018, 0.73866, 1.22716", \ - "0.0230649, 0.105886, 0.168029, 0.272243, 0.44706, 0.738661, 1.22717", \ - "0.023192, 0.105908, 0.16803, 0.272244, 0.447061, 0.738662, 1.22718", \ - "0.023604, 0.106031, 0.168031, 0.272245, 0.447062, 0.738663, 1.22719" \ + "0.0230623, 0.105874, 0.168026, 0.272144, 0.447016, 0.738668, 1.22454", \ + "0.0230633, 0.105875, 0.168027, 0.27224, 0.447017, 0.738669, 1.22467", \ + "0.0230643, 0.105876, 0.168028, 0.272241, 0.447018, 0.73867, 1.22468", \ + "0.0230653, 0.105877, 0.168029, 0.272242, 0.447019, 0.738671, 1.22716", \ + "0.0230663, 0.105886, 0.16803, 0.272243, 0.44706, 0.738672, 1.22717", \ + "0.023192, 0.105908, 0.168031, 0.272244, 0.447061, 0.738673, 1.22718", \ + "0.023604, 0.106031, 0.168032, 0.272245, 0.447062, 0.738674, 1.22719" \ ); } cell_fall (TIMING_DELAY_7x7ds1) { index_1 ("0.0186, 0.0966, 0.174, 0.3294, 0.6408, 1.263, 2.5074"); index_2 ("0.001, 0.0468, 0.078, 0.1296, 0.216, 0.36, 0.6"); values ( \ - "0.209545, 0.261419, 0.295848, 0.353159, 0.449121, 0.609165, 0.876051", \ + "0.209545, 0.261376, 0.295853, 0.353033, 0.449121, 0.609221, 0.876029", \ "0.247402, 0.299324, 0.333886, 0.39123, 0.487227, 0.647197, 0.914447", \ "0.272841, 0.324701, 0.359246, 0.416453, 0.512402, 0.672579, 0.939358", \ "0.309923, 0.361936, 0.396404, 0.453653, 0.54958, 0.709625, 0.976502", \ @@ -29446,26 +29556,27 @@ library (sg13g2_stdcell_typ_1p20V_25C) { index_1 ("0.0186, 0.0966, 0.174, 0.3294, 0.6408, 1.263, 2.5074"); index_2 ("0.001, 0.0468, 0.078, 0.1296, 0.216, 0.36, 0.6"); values ( \ - "0.0192966, 0.083384, 0.129142, 0.20635, 0.33644, 0.553713, 0.915945", \ - "0.0192976, 0.0834019, 0.129143, 0.206354, 0.336441, 0.553784, 0.916367", \ - "0.0192986, 0.0834181, 0.129171, 0.206355, 0.336615, 0.555079, 0.916368", \ - "0.0192996, 0.0834191, 0.129228, 0.206356, 0.336616, 0.55508, 0.916369", \ - "0.0193018, 0.0834201, 0.129229, 0.206423, 0.336617, 0.555081, 0.91637", \ - "0.019316, 0.0834211, 0.12923, 0.206424, 0.336618, 0.555082, 0.916371", \ - "0.019317, 0.0834221, 0.129231, 0.206425, 0.336619, 0.555083, 0.916442" \ + "0.0192965, 0.0833893, 0.129229, 0.206349, 0.33644, 0.553712, 0.915878", \ + "0.0192975, 0.0834019, 0.12923, 0.206354, 0.336441, 0.553784, 0.916367", \ + "0.0192985, 0.0834181, 0.129231, 0.206355, 0.336615, 0.555079, 0.916368", \ + "0.0192995, 0.0834191, 0.129232, 0.206356, 0.336616, 0.55508, 0.916369", \ + "0.0193018, 0.0834201, 0.129233, 0.206423, 0.336617, 0.555081, 0.91637", \ + "0.019316, 0.0834211, 0.129234, 0.206424, 0.336618, 0.555082, 0.916371", \ + "0.019317, 0.0834221, 0.129235, 0.206425, 0.336619, 0.555083, 0.916442" \ ); } } timing () { related_pin : "RESET_B"; + sdf_edges : start_edge; timing_sense : positive_unate; timing_type : clear; cell_fall (TIMING_DELAY_7x7ds1) { index_1 ("0.0186, 0.0966, 0.174, 0.3294, 0.6408, 1.263, 2.5074"); index_2 ("0.001, 0.0468, 0.078, 0.1296, 0.216, 0.36, 0.6"); values ( \ - "0.280821, 0.332774, 0.367671, 0.426944, 0.530698, 0.710784, 1.0192", \ - "0.324011, 0.37594, 0.41056, 0.468694, 0.569618, 0.745178, 1.04882", \ + "0.280821, 0.332774, 0.367671, 0.426942, 0.530698, 0.710784, 1.01916", \ + "0.324011, 0.37594, 0.41056, 0.468694, 0.569618, 0.745188, 1.04887", \ "0.359668, 0.411692, 0.44617, 0.503786, 0.603243, 0.777034, 1.07538", \ "0.418256, 0.470234, 0.504617, 0.561815, 0.659297, 0.827166, 1.11978", \ "0.507748, 0.559335, 0.594282, 0.651437, 0.74717, 0.910794, 1.19317", \ @@ -29477,13 +29588,13 @@ library (sg13g2_stdcell_typ_1p20V_25C) { index_1 ("0.0186, 0.0966, 0.174, 0.3294, 0.6408, 1.263, 2.5074"); index_2 ("0.001, 0.0468, 0.078, 0.1296, 0.216, 0.36, 0.6"); values ( \ - "0.0189264, 0.0832643, 0.129063, 0.206265, 0.336405, 0.553967, 0.915871", \ - "0.0189981, 0.0833369, 0.129068, 0.206379, 0.336564, 0.553968, 0.916504", \ - "0.0190314, 0.0833379, 0.129092, 0.20638, 0.336565, 0.555489, 0.916505", \ - "0.0190324, 0.0833389, 0.129159, 0.206381, 0.336618, 0.55549, 0.916506", \ - "0.019069, 0.0833399, 0.12916, 0.206382, 0.336619, 0.555491, 0.916507", \ - "0.019139, 0.083371, 0.129161, 0.206383, 0.33662, 0.555492, 0.916508", \ - "0.019268, 0.083373, 0.129162, 0.206384, 0.336621, 0.555493, 0.916509" \ + "0.0189539, 0.0832641, 0.129063, 0.206265, 0.336405, 0.553971, 0.916502", \ + "0.0189981, 0.0833369, 0.129068, 0.206379, 0.336564, 0.553972, 0.916503", \ + "0.0190314, 0.0833379, 0.129092, 0.20638, 0.336565, 0.555489, 0.916504", \ + "0.0190324, 0.0833389, 0.129159, 0.206381, 0.336618, 0.55549, 0.916505", \ + "0.019069, 0.0833399, 0.12916, 0.206382, 0.336619, 0.555491, 0.916506", \ + "0.019139, 0.083371, 0.129161, 0.206383, 0.33662, 0.555492, 0.916507", \ + "0.019268, 0.083373, 0.129162, 0.206384, 0.336621, 0.555493, 0.916508" \ ); } } @@ -29494,8 +29605,8 @@ library (sg13g2_stdcell_typ_1p20V_25C) { index_1 ("0.0186, 0.0966, 0.174, 0.3294, 0.6408, 1.263, 2.5074"); index_2 ("0.001, 0.0468, 0.078, 0.1296, 0.216, 0.36, 0.6"); values ( \ - "0.0372206, 0.0713106, 0.0940313, 0.131266, 0.193509, 0.296686, 0.469043", \ - "0.0368246, 0.0708632, 0.0935426, 0.130818, 0.192976, 0.296271, 0.468247", \ + "0.0372226, 0.0713106, 0.0940335, 0.131267, 0.193505, 0.296754, 0.468561", \ + "0.0368246, 0.0708635, 0.0935426, 0.130818, 0.192974, 0.296271, 0.468361", \ "0.0367089, 0.0706815, 0.0935085, 0.130722, 0.194368, 0.29614, 0.46829", \ "0.0369793, 0.0709246, 0.0935558, 0.130863, 0.193273, 0.296379, 0.469573", \ "0.0378579, 0.0717828, 0.0944928, 0.131953, 0.193946, 0.297715, 0.46962", \ @@ -29507,12 +29618,12 @@ library (sg13g2_stdcell_typ_1p20V_25C) { index_1 ("0.0186, 0.0966, 0.174, 0.3294, 0.6408, 1.263, 2.5074"); index_2 ("0.001, 0.0468, 0.078, 0.1296, 0.216, 0.36, 0.6"); values ( \ - "0.0376833, 0.0719923, 0.0944988, 0.131593, 0.193175, 0.295696, 0.466804", \ + "0.0376833, 0.0719575, 0.0945043, 0.131547, 0.193175, 0.295695, 0.466653", \ "0.0373955, 0.0718894, 0.0945115, 0.131943, 0.192971, 0.295568, 0.466718", \ "0.0374572, 0.0717259, 0.09435, 0.131993, 0.193299, 0.29614, 0.466474", \ "0.0378475, 0.0723457, 0.0948492, 0.131602, 0.19372, 0.297052, 0.466923", \ "0.0388214, 0.0731252, 0.0959437, 0.13325, 0.195179, 0.297151, 0.473354", \ - "0.0412335, 0.0754064, 0.0980988, 0.13546, 0.198042, 0.301512, 0.471744", \ + "0.0412335, 0.0754065, 0.0981002, 0.13546, 0.198042, 0.301512, 0.471744", \ "0.0463286, 0.0804723, 0.103113, 0.140458, 0.202179, 0.306076, 0.479144" \ ); } @@ -29523,8 +29634,8 @@ library (sg13g2_stdcell_typ_1p20V_25C) { index_1 ("0.0186, 0.0966, 0.174, 0.3294, 0.6408, 1.263, 2.5074"); index_2 ("0.001, 0.0468, 0.078, 0.1296, 0.216, 0.36, 0.6"); values ( \ - "0.0372206, 0.0713106, 0.0940313, 0.131266, 0.193509, 0.296686, 0.469043", \ - "0.0368246, 0.0708632, 0.0935426, 0.130818, 0.192976, 0.296271, 0.468247", \ + "0.0372226, 0.0713106, 0.0940335, 0.131267, 0.193505, 0.296754, 0.468561", \ + "0.0368246, 0.0708635, 0.0935426, 0.130818, 0.192974, 0.296271, 0.468361", \ "0.0367089, 0.0706815, 0.0935085, 0.130722, 0.194368, 0.29614, 0.46829", \ "0.0369793, 0.0709246, 0.0935558, 0.130863, 0.193273, 0.296379, 0.469573", \ "0.0378579, 0.0717828, 0.0944928, 0.131953, 0.193946, 0.297715, 0.46962", \ @@ -29536,12 +29647,12 @@ library (sg13g2_stdcell_typ_1p20V_25C) { index_1 ("0.0186, 0.0966, 0.174, 0.3294, 0.6408, 1.263, 2.5074"); index_2 ("0.001, 0.0468, 0.078, 0.1296, 0.216, 0.36, 0.6"); values ( \ - "0.0376833, 0.0719923, 0.0944988, 0.131593, 0.193175, 0.295696, 0.466804", \ + "0.0376833, 0.0719575, 0.0945043, 0.131547, 0.193175, 0.295695, 0.466653", \ "0.0373955, 0.0718894, 0.0945115, 0.131943, 0.192971, 0.295568, 0.466718", \ "0.0374572, 0.0717259, 0.09435, 0.131993, 0.193299, 0.29614, 0.466474", \ "0.0378475, 0.0723457, 0.0948492, 0.131602, 0.19372, 0.297052, 0.466923", \ "0.0388214, 0.0731252, 0.0959437, 0.13325, 0.195179, 0.297151, 0.473354", \ - "0.0412335, 0.0754064, 0.0980988, 0.13546, 0.198042, 0.301512, 0.471744", \ + "0.0412335, 0.0754065, 0.0981002, 0.13546, 0.198042, 0.301512, 0.471744", \ "0.0463286, 0.0804723, 0.103113, 0.140458, 0.202179, 0.306076, 0.479144" \ ); } @@ -29557,9 +29668,9 @@ library (sg13g2_stdcell_typ_1p20V_25C) { index_1 ("0.0186, 0.0966, 0.174, 0.3294, 0.6408, 1.263, 2.5074"); index_2 ("0.001, 0.0468, 0.078, 0.1296, 0.216, 0.36, 0.6"); values ( \ - "0.0385235, 0.0693981, 0.0899129, 0.124497, 0.18515, 0.291094, 0.473348", \ - "0.0380275, 0.0688727, 0.0892675, 0.123126, 0.181741, 0.284637, 0.463577", \ - "0.0378787, 0.0688118, 0.0894851, 0.122637, 0.180265, 0.28172, 0.457211", \ + "0.0385251, 0.0693975, 0.0899129, 0.124497, 0.18515, 0.291088, 0.473559", \ + "0.0380275, 0.0688699, 0.0892676, 0.123126, 0.181741, 0.28465, 0.463665", \ + "0.0378787, 0.0688118, 0.0894851, 0.122636, 0.180265, 0.28172, 0.457211", \ "0.0380144, 0.0689278, 0.0892324, 0.122556, 0.180242, 0.27643, 0.447633", \ "0.0388113, 0.0697527, 0.0901939, 0.12373, 0.179164, 0.273948, 0.441062", \ "0.0410487, 0.0717949, 0.0924332, 0.126124, 0.182528, 0.275837, 0.431958", \ @@ -29576,6 +29687,7 @@ library (sg13g2_stdcell_typ_1p20V_25C) { timing () { related_pin : "CLK"; sdf_cond : "SCE == 1'b1"; + sdf_edges : start_edge; timing_sense : non_unate; timing_type : rising_edge; when : "SCE"; @@ -29583,7 +29695,7 @@ library (sg13g2_stdcell_typ_1p20V_25C) { index_1 ("0.0186, 0.0966, 0.174, 0.3294, 0.6408, 1.263, 2.5074"); index_2 ("0.001, 0.0468, 0.078, 0.1296, 0.216, 0.36, 0.6"); values ( \ - "0.139115, 0.23098, 0.277034, 0.349791, 0.469911, 0.669787, 1.00213", \ + "0.139119, 0.231105, 0.277027, 0.349716, 0.469911, 0.669616, 1.00226", \ "0.176905, 0.268806, 0.314917, 0.387624, 0.507814, 0.707731, 1.04043", \ "0.202387, 0.294213, 0.340264, 0.412927, 0.533261, 0.732854, 1.06659", \ "0.239498, 0.33135, 0.377422, 0.450043, 0.57025, 0.770015, 1.10258", \ @@ -29596,8 +29708,8 @@ library (sg13g2_stdcell_typ_1p20V_25C) { index_1 ("0.0186, 0.0966, 0.174, 0.3294, 0.6408, 1.263, 2.5074"); index_2 ("0.001, 0.0468, 0.078, 0.1296, 0.216, 0.36, 0.6"); values ( \ - "0.0259567, 0.117254, 0.175675, 0.275536, 0.447296, 0.736641, 1.22016", \ - "0.0259577, 0.117255, 0.175691, 0.275537, 0.447731, 0.736752, 1.22017", \ + "0.0259538, 0.117215, 0.17567, 0.275536, 0.447296, 0.73678, 1.21989", \ + "0.0259548, 0.117216, 0.175691, 0.275537, 0.447731, 0.736781, 1.2199", \ "0.0260024, 0.117275, 0.175692, 0.275538, 0.447732, 0.738516, 1.22157", \ "0.0260437, 0.117276, 0.175722, 0.275539, 0.447733, 0.738517, 1.22565", \ "0.0260447, 0.117277, 0.175805, 0.27554, 0.447734, 0.738518, 1.22566", \ @@ -29609,7 +29721,7 @@ library (sg13g2_stdcell_typ_1p20V_25C) { index_1 ("0.0186, 0.0966, 0.174, 0.3294, 0.6408, 1.263, 2.5074"); index_2 ("0.001, 0.0468, 0.078, 0.1296, 0.216, 0.36, 0.6"); values ( \ - "0.158024, 0.260249, 0.303266, 0.365759, 0.464187, 0.624961, 0.891909", \ + "0.158082, 0.260249, 0.303266, 0.36587, 0.46418, 0.624962, 0.891913", \ "0.195894, 0.298121, 0.34115, 0.403566, 0.502109, 0.662964, 0.930166", \ "0.221642, 0.323823, 0.366843, 0.429376, 0.527847, 0.688679, 0.95563", \ "0.260172, 0.362294, 0.405305, 0.46784, 0.566351, 0.727084, 0.994034", \ @@ -29622,25 +29734,26 @@ library (sg13g2_stdcell_typ_1p20V_25C) { index_1 ("0.0186, 0.0966, 0.174, 0.3294, 0.6408, 1.263, 2.5074"); index_2 ("0.001, 0.0468, 0.078, 0.1296, 0.216, 0.36, 0.6"); values ( \ - "0.0349075, 0.114234, 0.155559, 0.225058, 0.348482, 0.561354, 0.922081", \ - "0.0349085, 0.114262, 0.15556, 0.225059, 0.348483, 0.561355, 0.922082", \ - "0.0349272, 0.114439, 0.155561, 0.225074, 0.348484, 0.562572, 0.922083", \ - "0.0349506, 0.11444, 0.155562, 0.225075, 0.348485, 0.562573, 0.922084", \ - "0.0352269, 0.114534, 0.155563, 0.225076, 0.348486, 0.562574, 0.922085", \ - "0.036669, 0.114994, 0.15588, 0.225273, 0.348558, 0.562575, 0.922086", \ - "0.041713, 0.11705, 0.157258, 0.226015, 0.348773, 0.562576, 0.922087" \ + "0.034909, 0.114234, 0.155559, 0.225186, 0.348435, 0.56135, 0.921566", \ + "0.03491, 0.114262, 0.15556, 0.225187, 0.348442, 0.561351, 0.921875", \ + "0.0349272, 0.114439, 0.155561, 0.225188, 0.348443, 0.562572, 0.921876", \ + "0.0349506, 0.11444, 0.155562, 0.225189, 0.348444, 0.562573, 0.921877", \ + "0.0352269, 0.114534, 0.155563, 0.22519, 0.348445, 0.562574, 0.921878", \ + "0.036669, 0.114994, 0.15588, 0.225273, 0.348558, 0.562575, 0.921879", \ + "0.041713, 0.11705, 0.157258, 0.226015, 0.348773, 0.562576, 0.922069" \ ); } } timing () { related_pin : "CLK"; + sdf_edges : start_edge; timing_sense : non_unate; timing_type : rising_edge; cell_rise (TIMING_DELAY_7x7ds1) { index_1 ("0.0186, 0.0966, 0.174, 0.3294, 0.6408, 1.263, 2.5074"); index_2 ("0.001, 0.0468, 0.078, 0.1296, 0.216, 0.36, 0.6"); values ( \ - "0.139115, 0.23098, 0.277034, 0.349791, 0.469911, 0.669787, 1.00213", \ + "0.139119, 0.231105, 0.277027, 0.349716, 0.469911, 0.669616, 1.00226", \ "0.176905, 0.268806, 0.314917, 0.387624, 0.507814, 0.707731, 1.04043", \ "0.202387, 0.294213, 0.340264, 0.412927, 0.533261, 0.732854, 1.06659", \ "0.239498, 0.33135, 0.377422, 0.450043, 0.57025, 0.770015, 1.10258", \ @@ -29653,8 +29766,8 @@ library (sg13g2_stdcell_typ_1p20V_25C) { index_1 ("0.0186, 0.0966, 0.174, 0.3294, 0.6408, 1.263, 2.5074"); index_2 ("0.001, 0.0468, 0.078, 0.1296, 0.216, 0.36, 0.6"); values ( \ - "0.0259567, 0.117254, 0.175675, 0.275536, 0.447296, 0.736641, 1.22016", \ - "0.0259577, 0.117255, 0.175691, 0.275537, 0.447731, 0.736752, 1.22017", \ + "0.0259538, 0.117215, 0.17567, 0.275536, 0.447296, 0.73678, 1.21989", \ + "0.0259548, 0.117216, 0.175691, 0.275537, 0.447731, 0.736781, 1.2199", \ "0.0260024, 0.117275, 0.175692, 0.275538, 0.447732, 0.738516, 1.22157", \ "0.0260437, 0.117276, 0.175722, 0.275539, 0.447733, 0.738517, 1.22565", \ "0.0260447, 0.117277, 0.175805, 0.27554, 0.447734, 0.738518, 1.22566", \ @@ -29666,7 +29779,7 @@ library (sg13g2_stdcell_typ_1p20V_25C) { index_1 ("0.0186, 0.0966, 0.174, 0.3294, 0.6408, 1.263, 2.5074"); index_2 ("0.001, 0.0468, 0.078, 0.1296, 0.216, 0.36, 0.6"); values ( \ - "0.158024, 0.260249, 0.303266, 0.365759, 0.464187, 0.624961, 0.891909", \ + "0.158082, 0.260249, 0.303266, 0.36587, 0.46418, 0.624962, 0.891913", \ "0.195894, 0.298121, 0.34115, 0.403566, 0.502109, 0.662964, 0.930166", \ "0.221642, 0.323823, 0.366843, 0.429376, 0.527847, 0.688679, 0.95563", \ "0.260172, 0.362294, 0.405305, 0.46784, 0.566351, 0.727084, 0.994034", \ @@ -29679,40 +29792,41 @@ library (sg13g2_stdcell_typ_1p20V_25C) { index_1 ("0.0186, 0.0966, 0.174, 0.3294, 0.6408, 1.263, 2.5074"); index_2 ("0.001, 0.0468, 0.078, 0.1296, 0.216, 0.36, 0.6"); values ( \ - "0.0349075, 0.114234, 0.155559, 0.225058, 0.348482, 0.561354, 0.922081", \ - "0.0349085, 0.114262, 0.15556, 0.225059, 0.348483, 0.561355, 0.922082", \ - "0.0349272, 0.114439, 0.155561, 0.225074, 0.348484, 0.562572, 0.922083", \ - "0.0349506, 0.11444, 0.155562, 0.225075, 0.348485, 0.562573, 0.922084", \ - "0.0352269, 0.114534, 0.155563, 0.225076, 0.348486, 0.562574, 0.922085", \ - "0.036669, 0.114994, 0.15588, 0.225273, 0.348558, 0.562575, 0.922086", \ - "0.041713, 0.11705, 0.157258, 0.226015, 0.348773, 0.562576, 0.922087" \ + "0.034909, 0.114234, 0.155559, 0.225186, 0.348435, 0.56135, 0.921566", \ + "0.03491, 0.114262, 0.15556, 0.225187, 0.348442, 0.561351, 0.921875", \ + "0.0349272, 0.114439, 0.155561, 0.225188, 0.348443, 0.562572, 0.921876", \ + "0.0349506, 0.11444, 0.155562, 0.225189, 0.348444, 0.562573, 0.921877", \ + "0.0352269, 0.114534, 0.155563, 0.22519, 0.348445, 0.562574, 0.921878", \ + "0.036669, 0.114994, 0.15588, 0.225273, 0.348558, 0.562575, 0.921879", \ + "0.041713, 0.11705, 0.157258, 0.226015, 0.348773, 0.562576, 0.922069" \ ); } } timing () { related_pin : "RESET_B"; + sdf_edges : start_edge; timing_sense : negative_unate; timing_type : preset; cell_rise (TIMING_DELAY_7x7ds1) { index_1 ("0.0186, 0.0966, 0.174, 0.3294, 0.6408, 1.263, 2.5074"); index_2 ("0.001, 0.0468, 0.078, 0.1296, 0.216, 0.36, 0.6"); values ( \ - "0.21192, 0.301157, 0.346867, 0.419432, 0.539576, 0.739511, 1.07242", \ + "0.211905, 0.301157, 0.346867, 0.419521, 0.539591, 0.739504, 1.07242", \ "0.255006, 0.344416, 0.389982, 0.462602, 0.583088, 0.78277, 1.11553", \ "0.290643, 0.380018, 0.425634, 0.498392, 0.618526, 0.818617, 1.15095", \ "0.34908, 0.438352, 0.484032, 0.556883, 0.67697, 0.876813, 1.20945", \ "0.438365, 0.528123, 0.57369, 0.646314, 0.766105, 0.965989, 1.29875", \ - "0.562955, 0.653266, 0.698748, 0.771851, 0.891855, 1.09136, 1.42429", \ - "0.730369, 0.822254, 0.868595, 0.941752, 1.06166, 1.26227, 1.59507" \ + "0.562955, 0.653266, 0.698748, 0.771851, 0.891855, 1.09175, 1.42429", \ + "0.730369, 0.822254, 0.868595, 0.941752, 1.06166, 1.26192, 1.59507" \ ); } rise_transition (TIMING_DELAY_7x7ds1) { index_1 ("0.0186, 0.0966, 0.174, 0.3294, 0.6408, 1.263, 2.5074"); index_2 ("0.001, 0.0468, 0.078, 0.1296, 0.216, 0.36, 0.6"); values ( \ - "0.0260827, 0.115231, 0.174381, 0.27494, 0.447111, 0.736617, 1.21992", \ - "0.0260929, 0.115262, 0.174383, 0.275293, 0.447527, 0.736802, 1.21993", \ - "0.0260939, 0.115263, 0.174384, 0.275294, 0.447528, 0.736951, 1.21994", \ + "0.0261224, 0.115231, 0.174381, 0.274953, 0.44711, 0.736617, 1.21992", \ + "0.0261234, 0.115262, 0.174383, 0.275293, 0.447527, 0.736802, 1.21993", \ + "0.0261244, 0.115263, 0.174384, 0.275294, 0.447528, 0.736951, 1.21994", \ "0.0263119, 0.115316, 0.174385, 0.275295, 0.447529, 0.736952, 1.22032", \ "0.0268157, 0.115444, 0.174476, 0.275296, 0.44753, 0.736953, 1.22033", \ "0.027734, 0.115702, 0.174613, 0.275297, 0.447531, 0.736954, 1.22034", \ @@ -29727,11 +29841,11 @@ library (sg13g2_stdcell_typ_1p20V_25C) { index_1 ("0.0186, 0.0966, 0.174, 0.3294, 0.6408, 1.263, 2.5074"); index_2 ("0.001, 0.0468, 0.078, 0.1296, 0.216, 0.36, 0.6"); values ( \ - "0.0377328, 0.0721826, 0.0947685, 0.132048, 0.194113, 0.297436, 0.469497", \ - "0.0374117, 0.0720019, 0.0946812, 0.131748, 0.194062, 0.297194, 0.469225", \ + "0.0377337, 0.0721848, 0.0947864, 0.132046, 0.194113, 0.297361, 0.469666", \ + "0.0374123, 0.0720019, 0.0946812, 0.131748, 0.194062, 0.297194, 0.469225", \ "0.0374886, 0.0718812, 0.0946159, 0.132084, 0.193984, 0.298124, 0.470058", \ "0.0378759, 0.0723688, 0.095027, 0.132181, 0.194748, 0.297598, 0.47202", \ - "0.0388533, 0.0732349, 0.0960003, 0.133453, 0.195469, 0.299068, 0.470595", \ + "0.0388533, 0.0732359, 0.0960003, 0.133453, 0.195469, 0.299068, 0.470595", \ "0.0412375, 0.0755247, 0.0983934, 0.13567, 0.198075, 0.301629, 0.47321", \ "0.0463461, 0.0805916, 0.103355, 0.140553, 0.203089, 0.306824, 0.479826" \ ); @@ -29740,12 +29854,12 @@ library (sg13g2_stdcell_typ_1p20V_25C) { index_1 ("0.0186, 0.0966, 0.174, 0.3294, 0.6408, 1.263, 2.5074"); index_2 ("0.001, 0.0468, 0.078, 0.1296, 0.216, 0.36, 0.6"); values ( \ - "0.0372225, 0.0710447, 0.0936764, 0.130693, 0.192447, 0.295069, 0.466336", \ - "0.0368197, 0.0708457, 0.0932323, 0.130259, 0.192008, 0.294608, 0.465923", \ + "0.0372241, 0.0710447, 0.0936764, 0.13075, 0.19249, 0.295068, 0.466071", \ + "0.0368197, 0.0708457, 0.0932323, 0.130259, 0.192008, 0.294608, 0.465921", \ "0.0367367, 0.0704883, 0.0931456, 0.130604, 0.192238, 0.2949, 0.465799", \ "0.0370197, 0.0708378, 0.0934452, 0.130299, 0.192482, 0.297442, 0.466789", \ "0.0378684, 0.0715466, 0.0943653, 0.131806, 0.193466, 0.295905, 0.471764", \ - "0.0401317, 0.0735828, 0.0963879, 0.13364, 0.196291, 0.29993, 0.470242", \ + "0.0401317, 0.0735828, 0.0963879, 0.13364, 0.196291, 0.29993, 0.470247", \ "0.0456498, 0.0785864, 0.101288, 0.13852, 0.200535, 0.304415, 0.477358" \ ); } @@ -29756,11 +29870,11 @@ library (sg13g2_stdcell_typ_1p20V_25C) { index_1 ("0.0186, 0.0966, 0.174, 0.3294, 0.6408, 1.263, 2.5074"); index_2 ("0.001, 0.0468, 0.078, 0.1296, 0.216, 0.36, 0.6"); values ( \ - "0.0377328, 0.0721826, 0.0947685, 0.132048, 0.194113, 0.297436, 0.469497", \ - "0.0374117, 0.0720019, 0.0946812, 0.131748, 0.194062, 0.297194, 0.469225", \ + "0.0377337, 0.0721848, 0.0947864, 0.132046, 0.194113, 0.297361, 0.469666", \ + "0.0374123, 0.0720019, 0.0946812, 0.131748, 0.194062, 0.297194, 0.469225", \ "0.0374886, 0.0718812, 0.0946159, 0.132084, 0.193984, 0.298124, 0.470058", \ "0.0378759, 0.0723688, 0.095027, 0.132181, 0.194748, 0.297598, 0.47202", \ - "0.0388533, 0.0732349, 0.0960003, 0.133453, 0.195469, 0.299068, 0.470595", \ + "0.0388533, 0.0732359, 0.0960003, 0.133453, 0.195469, 0.299068, 0.470595", \ "0.0412375, 0.0755247, 0.0983934, 0.13567, 0.198075, 0.301629, 0.47321", \ "0.0463461, 0.0805916, 0.103355, 0.140553, 0.203089, 0.306824, 0.479826" \ ); @@ -29769,12 +29883,12 @@ library (sg13g2_stdcell_typ_1p20V_25C) { index_1 ("0.0186, 0.0966, 0.174, 0.3294, 0.6408, 1.263, 2.5074"); index_2 ("0.001, 0.0468, 0.078, 0.1296, 0.216, 0.36, 0.6"); values ( \ - "0.0372225, 0.0710447, 0.0936764, 0.130693, 0.192447, 0.295069, 0.466336", \ - "0.0368197, 0.0708457, 0.0932323, 0.130259, 0.192008, 0.294608, 0.465923", \ + "0.0372241, 0.0710447, 0.0936764, 0.13075, 0.19249, 0.295068, 0.466071", \ + "0.0368197, 0.0708457, 0.0932323, 0.130259, 0.192008, 0.294608, 0.465921", \ "0.0367367, 0.0704883, 0.0931456, 0.130604, 0.192238, 0.2949, 0.465799", \ "0.0370197, 0.0708378, 0.0934452, 0.130299, 0.192482, 0.297442, 0.466789", \ "0.0378684, 0.0715466, 0.0943653, 0.131806, 0.193466, 0.295905, 0.471764", \ - "0.0401317, 0.0735828, 0.0963879, 0.13364, 0.196291, 0.29993, 0.470242", \ + "0.0401317, 0.0735828, 0.0963879, 0.13364, 0.196291, 0.29993, 0.470247", \ "0.0456498, 0.0785864, 0.101288, 0.13852, 0.200535, 0.304415, 0.477358" \ ); } @@ -29785,13 +29899,13 @@ library (sg13g2_stdcell_typ_1p20V_25C) { index_1 ("0.0186, 0.0966, 0.174, 0.3294, 0.6408, 1.263, 2.5074"); index_2 ("0.001, 0.0468, 0.078, 0.1296, 0.216, 0.36, 0.6"); values ( \ - "0.0385708, 0.0696161, 0.0902379, 0.12513, 0.186091, 0.292676, 0.47579", \ + "0.0385719, 0.0696161, 0.090237, 0.125098, 0.186078, 0.292676, 0.475791", \ "0.0380701, 0.0691378, 0.0895314, 0.123855, 0.182871, 0.286235, 0.466243", \ "0.0378978, 0.0690038, 0.0897239, 0.12329, 0.181175, 0.282486, 0.4596", \ "0.0380265, 0.0690509, 0.0895221, 0.123277, 0.179965, 0.278293, 0.450729", \ - "0.038838, 0.0699458, 0.0904548, 0.124031, 0.180052, 0.275701, 0.440221", \ - "0.0411033, 0.0720534, 0.0926413, 0.126466, 0.182901, 0.27619, 0.434834", \ - "0.0463185, 0.0769784, 0.0975632, 0.131356, 0.188131, 0.281698, 0.437818" \ + "0.038838, 0.0699458, 0.0904548, 0.124031, 0.180052, 0.275704, 0.440221", \ + "0.0411033, 0.0720533, 0.0926413, 0.126466, 0.182915, 0.27608, 0.434834", \ + "0.0463185, 0.0769784, 0.0975631, 0.131356, 0.188131, 0.281439, 0.437818" \ ); } fall_power (scalar) { @@ -29807,9 +29921,9 @@ library (sg13g2_stdcell_typ_1p20V_25C) { max_transition : 2.5074; capacitance : 0.00293819; rise_capacitance : 0.00297913; - rise_capacitance_range (0.00297913, 0.00297913); + rise_capacitance_range (0.00273041, 0.00317828); fall_capacitance : 0.00288555; - fall_capacitance_range (0.00288555, 0.00288555); + fall_capacitance_range (0.00267496, 0.00308449); timing () { related_pin : "CLK"; timing_type : min_pulse_width; @@ -29831,7 +29945,7 @@ library (sg13g2_stdcell_typ_1p20V_25C) { fall_power (passive_POWER_7x1ds1) { index_1 ("0.0186, 0.0966, 0.174, 0.3294, 0.6408, 1.263, 2.5074"); values ( \ - "0.0106522, 0.0102972, 0.0103971, 0.0106819, 0.0116058, 0.0138402, 0.0189024" \ + "0.0106522, 0.0102973, 0.0103971, 0.0106819, 0.0116058, 0.0138402, 0.0189024" \ ); } } @@ -29859,7 +29973,7 @@ library (sg13g2_stdcell_typ_1p20V_25C) { fall_power (passive_POWER_7x1ds1) { index_1 ("0.0186, 0.0966, 0.174, 0.3294, 0.6408, 1.263, 2.5074"); values ( \ - "0.0189306, 0.0186391, 0.0187715, 0.0191402, 0.0201668, 0.0225685, 0.0278147" \ + "0.0189307, 0.0186391, 0.0187715, 0.0191402, 0.0201668, 0.0225685, 0.0278147" \ ); } } @@ -29868,7 +29982,7 @@ library (sg13g2_stdcell_typ_1p20V_25C) { rise_power (passive_POWER_7x1ds1) { index_1 ("0.0186, 0.0966, 0.174, 0.3294, 0.6408, 1.263, 2.5074"); values ( \ - "0.0108596, 0.0104942, 0.0104774, 0.0107279, 0.0116325, 0.0138092, 0.0187513" \ + "0.0108596, 0.0104942, 0.0104775, 0.0107279, 0.0116325, 0.0138092, 0.0187513" \ ); } fall_power (passive_POWER_7x1ds1) { @@ -29883,13 +29997,13 @@ library (sg13g2_stdcell_typ_1p20V_25C) { rise_power (passive_POWER_7x1ds1) { index_1 ("0.0186, 0.0966, 0.174, 0.3294, 0.6408, 1.263, 2.5074"); values ( \ - "0.0111296, 0.0107428, 0.0107454, 0.0109767, 0.0119007, 0.0140712, 0.0190282" \ + "0.0111296, 0.0107428, 0.0107454, 0.0109764, 0.0119007, 0.0140712, 0.0190281" \ ); } fall_power (passive_POWER_7x1ds1) { index_1 ("0.0186, 0.0966, 0.174, 0.3294, 0.6408, 1.263, 2.5074"); values ( \ - "0.0106483, 0.0103085, 0.0103971, 0.0106819, 0.0116061, 0.0138402, 0.0189022" \ + "0.0106486, 0.0103089, 0.0103971, 0.0106819, 0.0116061, 0.0138402, 0.0189022" \ ); } } @@ -29904,7 +30018,7 @@ library (sg13g2_stdcell_typ_1p20V_25C) { fall_power (passive_POWER_7x1ds1) { index_1 ("0.0186, 0.0966, 0.174, 0.3294, 0.6408, 1.263, 2.5074"); values ( \ - "0.00965463, 0.00929597, 0.00937968, 0.00967125, 0.0105824, 0.0128332, 0.0178957" \ + "0.0096548, 0.00929597, 0.00937968, 0.00967125, 0.0105824, 0.0128332, 0.0178957" \ ); } } @@ -29919,7 +30033,7 @@ library (sg13g2_stdcell_typ_1p20V_25C) { fall_power (passive_POWER_7x1ds1) { index_1 ("0.0186, 0.0966, 0.174, 0.3294, 0.6408, 1.263, 2.5074"); values ( \ - "0.0108434, 0.0104928, 0.0105859, 0.0108771, 0.0117912, 0.014034, 0.0190989" \ + "0.0108488, 0.0104928, 0.0105859, 0.0108771, 0.0117912, 0.014034, 0.0190989" \ ); } } @@ -29933,7 +30047,7 @@ library (sg13g2_stdcell_typ_1p20V_25C) { fall_power (passive_POWER_7x1ds1) { index_1 ("0.0186, 0.0966, 0.174, 0.3294, 0.6408, 1.263, 2.5074"); values ( \ - "0.0108434, 0.0104928, 0.0105859, 0.0108771, 0.0117912, 0.014034, 0.0190989" \ + "0.0108488, 0.0104928, 0.0105859, 0.0108771, 0.0117912, 0.014034, 0.0190989" \ ); } } @@ -29944,11 +30058,12 @@ library (sg13g2_stdcell_typ_1p20V_25C) { max_transition : 2.5074; capacitance : 0.00276809; rise_capacitance : 0.002801; - rise_capacitance_range (0.002801, 0.002801); + rise_capacitance_range (0.00246434, 0.00305188); fall_capacitance : 0.00273518; - fall_capacitance_range (0.00273518, 0.00273518); + fall_capacitance_range (0.00241866, 0.00292303); timing () { related_pin : "CLK"; + sdf_edges : both_edges; timing_type : hold_rising; rise_constraint (CONSTRAINT_4x4) { index_1 ("0.0186, 0.51636, 1.263, 2.5074"); @@ -29973,6 +30088,7 @@ library (sg13g2_stdcell_typ_1p20V_25C) { } timing () { related_pin : "CLK"; + sdf_edges : both_edges; timing_type : setup_rising; rise_constraint (CONSTRAINT_4x4) { index_1 ("0.0186, 0.51636, 1.263, 2.5074"); @@ -30000,13 +30116,13 @@ library (sg13g2_stdcell_typ_1p20V_25C) { rise_power (passive_POWER_7x1ds1) { index_1 ("0.0186, 0.0966, 0.174, 0.3294, 0.6408, 1.263, 2.5074"); values ( \ - "0.0210965, 0.0207635, 0.0207455, 0.0208997, 0.0215654, 0.0233201, 0.0274332" \ + "0.0211026, 0.0207634, 0.0207455, 0.0208997, 0.0215654, 0.02332, 0.0274332" \ ); } fall_power (passive_POWER_7x1ds1) { index_1 ("0.0186, 0.0966, 0.174, 0.3294, 0.6408, 1.263, 2.5074"); values ( \ - "0.0202806, 0.0199604, 0.0200618, 0.0203582, 0.0212294, 0.023279, 0.0278545" \ + "0.0202966, 0.0199604, 0.0200618, 0.0203582, 0.0212294, 0.023279, 0.0278545" \ ); } } @@ -30014,13 +30130,13 @@ library (sg13g2_stdcell_typ_1p20V_25C) { rise_power (passive_POWER_7x1ds1) { index_1 ("0.0186, 0.0966, 0.174, 0.3294, 0.6408, 1.263, 2.5074"); values ( \ - "0.0210965, 0.0207635, 0.0207455, 0.0208997, 0.0215654, 0.0233201, 0.0274332" \ + "0.0211026, 0.0207634, 0.0207455, 0.0208997, 0.0215654, 0.02332, 0.0274332" \ ); } fall_power (passive_POWER_7x1ds1) { index_1 ("0.0186, 0.0966, 0.174, 0.3294, 0.6408, 1.263, 2.5074"); values ( \ - "0.0202806, 0.0199604, 0.0200618, 0.0203582, 0.0212294, 0.023279, 0.0278545" \ + "0.0202966, 0.0199604, 0.0200618, 0.0203582, 0.0212294, 0.023279, 0.0278545" \ ); } } @@ -30028,13 +30144,14 @@ library (sg13g2_stdcell_typ_1p20V_25C) { pin (RESET_B) { direction : input; max_transition : 2.5074; - capacitance : 0.00510792; - rise_capacitance : 0.00510792; - rise_capacitance_range (0.00510792, 0.00510792); - fall_capacitance : 0.00510792; - fall_capacitance_range (0.00510792, 0.00510792); + capacitance : 0.0051079; + rise_capacitance : 0.0051079; + rise_capacitance_range (0.0051079, 0.0051079); + fall_capacitance : 0.0051079; + fall_capacitance_range (0.0047835, 0.00531694); timing () { related_pin : "CLK"; + sdf_edges : both_edges; timing_type : recovery_rising; rise_constraint (CONSTRAINT_4x4) { index_1 ("0.0186, 0.51636, 1.263, 2.5074"); @@ -30049,6 +30166,7 @@ library (sg13g2_stdcell_typ_1p20V_25C) { } timing () { related_pin : "CLK"; + sdf_edges : both_edges; timing_type : removal_rising; rise_constraint (CONSTRAINT_4x4) { index_1 ("0.0186, 0.51636, 1.263, 2.5074"); @@ -30078,11 +30196,12 @@ library (sg13g2_stdcell_typ_1p20V_25C) { max_transition : 2.5074; capacitance : 0.002882; rise_capacitance : 0.00290395; - rise_capacitance_range (0.00290395, 0.00290395); + rise_capacitance_range (0.00256958, 0.00315304); fall_capacitance : 0.0028381; - fall_capacitance_range (0.0028381, 0.0028381); + fall_capacitance_range (0.00252382, 0.00302524); timing () { related_pin : "CLK"; + sdf_edges : both_edges; timing_type : hold_rising; rise_constraint (CONSTRAINT_4x4) { index_1 ("0.0186, 0.51636, 1.263, 2.5074"); @@ -30107,6 +30226,7 @@ library (sg13g2_stdcell_typ_1p20V_25C) { } timing () { related_pin : "CLK"; + sdf_edges : both_edges; timing_type : setup_rising; rise_constraint (CONSTRAINT_4x4) { index_1 ("0.0186, 0.51636, 1.263, 2.5074"); @@ -30134,13 +30254,13 @@ library (sg13g2_stdcell_typ_1p20V_25C) { rise_power (passive_POWER_7x1ds1) { index_1 ("0.0186, 0.0966, 0.174, 0.3294, 0.6408, 1.263, 2.5074"); values ( \ - "0.0212611, 0.0209146, 0.0208704, 0.02107, 0.0217061, 0.0234549, 0.0275686" \ + "0.0212598, 0.0209146, 0.0208704, 0.02107, 0.0217061, 0.0234549, 0.0275686" \ ); } fall_power (passive_POWER_7x1ds1) { index_1 ("0.0186, 0.0966, 0.174, 0.3294, 0.6408, 1.263, 2.5074"); values ( \ - "0.0177192, 0.0173936, 0.0174615, 0.017788, 0.0186798, 0.0207043, 0.0253331" \ + "0.0177197, 0.0173936, 0.0174615, 0.017788, 0.0186798, 0.0207043, 0.0253331" \ ); } } @@ -30148,13 +30268,13 @@ library (sg13g2_stdcell_typ_1p20V_25C) { rise_power (passive_POWER_7x1ds1) { index_1 ("0.0186, 0.0966, 0.174, 0.3294, 0.6408, 1.263, 2.5074"); values ( \ - "0.0212611, 0.0209146, 0.0208704, 0.02107, 0.0217061, 0.0234549, 0.0275686" \ + "0.0212598, 0.0209146, 0.0208704, 0.02107, 0.0217061, 0.0234549, 0.0275686" \ ); } fall_power (passive_POWER_7x1ds1) { index_1 ("0.0186, 0.0966, 0.174, 0.3294, 0.6408, 1.263, 2.5074"); values ( \ - "0.0177192, 0.0173936, 0.0174615, 0.017788, 0.0186798, 0.0207043, 0.0253331" \ + "0.0177197, 0.0173936, 0.0174615, 0.017788, 0.0186798, 0.0207043, 0.0253331" \ ); } } @@ -30165,11 +30285,12 @@ library (sg13g2_stdcell_typ_1p20V_25C) { max_transition : 2.5074; capacitance : 0.00484421; rise_capacitance : 0.00508758; - rise_capacitance_range (0.00508758, 0.00508758); + rise_capacitance_range (0.00444598, 0.00578187); fall_capacitance : 0.00460085; - fall_capacitance_range (0.00460085, 0.00460085); + fall_capacitance_range (0.00441547, 0.00509964); timing () { related_pin : "CLK"; + sdf_edges : both_edges; timing_type : hold_rising; rise_constraint (CONSTRAINT_4x4) { index_1 ("0.0186, 0.51636, 1.263, 2.5074"); @@ -30194,6 +30315,7 @@ library (sg13g2_stdcell_typ_1p20V_25C) { } timing () { related_pin : "CLK"; + sdf_edges : both_edges; timing_type : setup_rising; rise_constraint (CONSTRAINT_4x4) { index_1 ("0.0186, 0.51636, 1.263, 2.5074"); @@ -30211,7 +30333,7 @@ library (sg13g2_stdcell_typ_1p20V_25C) { values ( \ "0.227403, 0.10008, 0.022147, -0.0531392", \ "0.349169, 0.221542, 0.143266, 0.0653783", \ - "0.435629, 0.310412, 0.232059, 0.154081", \ + "0.438201, 0.310412, 0.232059, 0.154081", \ "0.53075, 0.404701, 0.32616, 0.247929" \ ); } @@ -30227,7 +30349,7 @@ library (sg13g2_stdcell_typ_1p20V_25C) { fall_power (passive_POWER_7x1ds1) { index_1 ("0.0186, 0.0966, 0.174, 0.3294, 0.6408, 1.263, 2.5074"); values ( \ - "0.0259374, 0.0257357, 0.0257203, 0.0260171, 0.0266222, 0.0281658, 0.0316307" \ + "0.0259387, 0.0257357, 0.0257203, 0.0260171, 0.0266222, 0.0281657, 0.0316306" \ ); } } @@ -30236,13 +30358,13 @@ library (sg13g2_stdcell_typ_1p20V_25C) { rise_power (passive_POWER_7x1ds1) { index_1 ("0.0186, 0.0966, 0.174, 0.3294, 0.6408, 1.263, 2.5074"); values ( \ - "0.0257023, 0.0252847, 0.0252842, 0.0255889, 0.0266139, 0.0295363, 0.0363979" \ + "0.0256965, 0.0252847, 0.0252842, 0.0255889, 0.0266139, 0.0295363, 0.0363978" \ ); } fall_power (passive_POWER_7x1ds1) { index_1 ("0.0186, 0.0966, 0.174, 0.3294, 0.6408, 1.263, 2.5074"); values ( \ - "0.0247175, 0.0399668, 0.0409898, 0.0414915, 0.0427401, 0.0458526, 0.0530063" \ + "0.0247187, 0.0399668, 0.0409898, 0.0414915, 0.0427401, 0.0458526, 0.0530063" \ ); } } @@ -30250,21 +30372,21 @@ library (sg13g2_stdcell_typ_1p20V_25C) { rise_power (passive_POWER_7x1ds1) { index_1 ("0.0186, 0.0966, 0.174, 0.3294, 0.6408, 1.263, 2.5074"); values ( \ - "0.0257023, 0.0252847, 0.0252842, 0.0255889, 0.0266139, 0.0295363, 0.0363979" \ + "0.0256965, 0.0252847, 0.0252842, 0.0255889, 0.0266139, 0.0295363, 0.0363978" \ ); } fall_power (passive_POWER_7x1ds1) { index_1 ("0.0186, 0.0966, 0.174, 0.3294, 0.6408, 1.263, 2.5074"); values ( \ - "0.0247175, 0.0399668, 0.0409898, 0.0414915, 0.0427401, 0.0458526, 0.0530063" \ + "0.0247187, 0.0399668, 0.0409898, 0.0414915, 0.0427401, 0.0458526, 0.0530063" \ ); } } } ff (IQ,IQN) { - clear : "RESET_B'"; + clear : "!RESET_B"; clocked_on : "CLK"; - next_state : "(SCE*SCD)+(SCE'*D)"; + next_state : "(SCE*SCD)+(!SCE*D)"; } test_cell () { pin (Q) { @@ -30295,7 +30417,7 @@ library (sg13g2_stdcell_typ_1p20V_25C) { signal_type : test_scan_enable; } ff (IQ,IQN) { - clear : "RESET_B'"; + clear : "!RESET_B"; clocked_on : "CLK"; next_state : "D"; } @@ -30381,6 +30503,7 @@ library (sg13g2_stdcell_typ_1p20V_25C) { timing () { related_pin : "CLK"; sdf_cond : "SCE == 1'b1"; + sdf_edges : start_edge; timing_sense : non_unate; timing_type : rising_edge; when : "SCE"; @@ -30440,6 +30563,7 @@ library (sg13g2_stdcell_typ_1p20V_25C) { timing () { related_pin : "CLK"; sdf_cond : "SCE == 1'b0"; + sdf_edges : start_edge; timing_sense : non_unate; timing_type : rising_edge; when : "!SCE"; @@ -30498,6 +30622,7 @@ library (sg13g2_stdcell_typ_1p20V_25C) { } timing () { related_pin : "CLK"; + sdf_edges : start_edge; timing_sense : non_unate; timing_type : rising_edge; cell_rise (TIMING_DELAY_7x7ds1) { @@ -30555,6 +30680,7 @@ library (sg13g2_stdcell_typ_1p20V_25C) { } timing () { related_pin : "RESET_B"; + sdf_edges : start_edge; timing_sense : positive_unate; timing_type : clear; cell_fall (TIMING_DELAY_7x7ds1) { @@ -30701,9 +30827,9 @@ library (sg13g2_stdcell_typ_1p20V_25C) { max_transition : 2.5074; capacitance : 0.00293778; rise_capacitance : 0.00297839; - rise_capacitance_range (0.00297839, 0.00297839); + rise_capacitance_range (0.00272958, 0.00317799); fall_capacitance : 0.00288558; - fall_capacitance_range (0.00288558, 0.00288558); + fall_capacitance_range (0.00267254, 0.00308442); timing () { related_pin : "CLK"; timing_type : min_pulse_width; @@ -30844,11 +30970,12 @@ library (sg13g2_stdcell_typ_1p20V_25C) { max_transition : 2.5074; capacitance : 0.00277037; rise_capacitance : 0.00280336; - rise_capacitance_range (0.00280336, 0.00280336); + rise_capacitance_range (0.00246692, 0.00305425); fall_capacitance : 0.00273737; - fall_capacitance_range (0.00273737, 0.00273737); + fall_capacitance_range (0.00242156, 0.00292537); timing () { related_pin : "CLK"; + sdf_edges : both_edges; timing_type : hold_rising; rise_constraint (CONSTRAINT_4x4) { index_1 ("0.0186, 0.51636, 1.263, 2.5074"); @@ -30873,6 +31000,7 @@ library (sg13g2_stdcell_typ_1p20V_25C) { } timing () { related_pin : "CLK"; + sdf_edges : both_edges; timing_type : setup_rising; rise_constraint (CONSTRAINT_4x4) { index_1 ("0.0186, 0.51636, 1.263, 2.5074"); @@ -30932,9 +31060,10 @@ library (sg13g2_stdcell_typ_1p20V_25C) { rise_capacitance : 0.00509594; rise_capacitance_range (0.00509594, 0.00509594); fall_capacitance : 0.00509594; - fall_capacitance_range (0.00509594, 0.00509594); + fall_capacitance_range (0.00478919, 0.00531011); timing () { related_pin : "CLK"; + sdf_edges : both_edges; timing_type : recovery_rising; rise_constraint (CONSTRAINT_4x4) { index_1 ("0.0186, 0.51636, 1.263, 2.5074"); @@ -30949,6 +31078,7 @@ library (sg13g2_stdcell_typ_1p20V_25C) { } timing () { related_pin : "CLK"; + sdf_edges : both_edges; timing_type : removal_rising; rise_constraint (CONSTRAINT_4x4) { index_1 ("0.0186, 0.51636, 1.263, 2.5074"); @@ -30978,11 +31108,12 @@ library (sg13g2_stdcell_typ_1p20V_25C) { max_transition : 2.5074; capacitance : 0.00288438; rise_capacitance : 0.00290628; - rise_capacitance_range (0.00290628, 0.00290628); + rise_capacitance_range (0.00257184, 0.00315538); fall_capacitance : 0.00284058; - fall_capacitance_range (0.00284058, 0.00284058); + fall_capacitance_range (0.00252775, 0.00302756); timing () { related_pin : "CLK"; + sdf_edges : both_edges; timing_type : hold_rising; rise_constraint (CONSTRAINT_4x4) { index_1 ("0.0186, 0.51636, 1.263, 2.5074"); @@ -31007,6 +31138,7 @@ library (sg13g2_stdcell_typ_1p20V_25C) { } timing () { related_pin : "CLK"; + sdf_edges : both_edges; timing_type : setup_rising; rise_constraint (CONSTRAINT_4x4) { index_1 ("0.0186, 0.51636, 1.263, 2.5074"); @@ -31065,11 +31197,12 @@ library (sg13g2_stdcell_typ_1p20V_25C) { max_transition : 2.5074; capacitance : 0.004844; rise_capacitance : 0.00508748; - rise_capacitance_range (0.00508748, 0.00508748); + rise_capacitance_range (0.00444453, 0.00578189); fall_capacitance : 0.00460051; - fall_capacitance_range (0.00460051, 0.00460051); + fall_capacitance_range (0.00441076, 0.00509962); timing () { related_pin : "CLK"; + sdf_edges : both_edges; timing_type : hold_rising; rise_constraint (CONSTRAINT_4x4) { index_1 ("0.0186, 0.51636, 1.263, 2.5074"); @@ -31094,6 +31227,7 @@ library (sg13g2_stdcell_typ_1p20V_25C) { } timing () { related_pin : "CLK"; + sdf_edges : both_edges; timing_type : setup_rising; rise_constraint (CONSTRAINT_4x4) { index_1 ("0.0186, 0.51636, 1.263, 2.5074"); @@ -31162,9 +31296,9 @@ library (sg13g2_stdcell_typ_1p20V_25C) { } } ff (IQ,IQN) { - clear : "RESET_B'"; + clear : "!RESET_B"; clocked_on : "CLK"; - next_state : "(SCE*SCD)+(SCE'*D)"; + next_state : "(SCE*SCD)+(!SCE*D)"; } test_cell () { pin (Q) { @@ -31190,7 +31324,7 @@ library (sg13g2_stdcell_typ_1p20V_25C) { signal_type : test_scan_enable; } ff (IQ,IQN) { - clear : "RESET_B'"; + clear : "!RESET_B"; clocked_on : "CLK"; next_state : "D"; } @@ -31276,6 +31410,7 @@ library (sg13g2_stdcell_typ_1p20V_25C) { timing () { related_pin : "CLK"; sdf_cond : "SCE == 1'b1"; + sdf_edges : start_edge; timing_sense : non_unate; timing_type : rising_edge; when : "SCE"; @@ -31335,6 +31470,7 @@ library (sg13g2_stdcell_typ_1p20V_25C) { timing () { related_pin : "CLK"; sdf_cond : "SCE == 1'b0"; + sdf_edges : start_edge; timing_sense : non_unate; timing_type : rising_edge; when : "!SCE"; @@ -31393,6 +31529,7 @@ library (sg13g2_stdcell_typ_1p20V_25C) { } timing () { related_pin : "CLK"; + sdf_edges : start_edge; timing_sense : non_unate; timing_type : rising_edge; cell_rise (TIMING_DELAY_7x7ds1) { @@ -31450,6 +31587,7 @@ library (sg13g2_stdcell_typ_1p20V_25C) { } timing () { related_pin : "RESET_B"; + sdf_edges : start_edge; timing_sense : positive_unate; timing_type : clear; cell_fall (TIMING_DELAY_7x7ds1) { @@ -31596,9 +31734,9 @@ library (sg13g2_stdcell_typ_1p20V_25C) { max_transition : 2.5074; capacitance : 0.00293785; rise_capacitance : 0.00297851; - rise_capacitance_range (0.00297851, 0.00297851); + rise_capacitance_range (0.00272949, 0.00317799); fall_capacitance : 0.00288557; - fall_capacitance_range (0.00288557, 0.00288557); + fall_capacitance_range (0.00267321, 0.00308441); timing () { related_pin : "CLK"; timing_type : min_pulse_width; @@ -31739,11 +31877,12 @@ library (sg13g2_stdcell_typ_1p20V_25C) { max_transition : 2.5074; capacitance : 0.00276791; rise_capacitance : 0.00280092; - rise_capacitance_range (0.00280092, 0.00280092); + rise_capacitance_range (0.00246384, 0.0030519); fall_capacitance : 0.0027349; - fall_capacitance_range (0.0027349, 0.0027349); + fall_capacitance_range (0.00241903, 0.00292302); timing () { related_pin : "CLK"; + sdf_edges : both_edges; timing_type : hold_rising; rise_constraint (CONSTRAINT_4x4) { index_1 ("0.0186, 0.51636, 1.263, 2.5074"); @@ -31768,6 +31907,7 @@ library (sg13g2_stdcell_typ_1p20V_25C) { } timing () { related_pin : "CLK"; + sdf_edges : both_edges; timing_type : setup_rising; rise_constraint (CONSTRAINT_4x4) { index_1 ("0.0186, 0.51636, 1.263, 2.5074"); @@ -31827,9 +31967,10 @@ library (sg13g2_stdcell_typ_1p20V_25C) { rise_capacitance : 0.00510599; rise_capacitance_range (0.00510599, 0.00510599); fall_capacitance : 0.00510599; - fall_capacitance_range (0.00510599, 0.00510599); + fall_capacitance_range (0.00480819, 0.00531405); timing () { related_pin : "CLK"; + sdf_edges : both_edges; timing_type : recovery_rising; rise_constraint (CONSTRAINT_4x4) { index_1 ("0.0186, 0.51636, 1.263, 2.5074"); @@ -31844,6 +31985,7 @@ library (sg13g2_stdcell_typ_1p20V_25C) { } timing () { related_pin : "CLK"; + sdf_edges : both_edges; timing_type : removal_rising; rise_constraint (CONSTRAINT_4x4) { index_1 ("0.0186, 0.51636, 1.263, 2.5074"); @@ -31873,11 +32015,12 @@ library (sg13g2_stdcell_typ_1p20V_25C) { max_transition : 2.5074; capacitance : 0.00288297; rise_capacitance : 0.00290481; - rise_capacitance_range (0.00290481, 0.00290481); + rise_capacitance_range (0.00257017, 0.00315395); fall_capacitance : 0.00283928; - fall_capacitance_range (0.00283928, 0.00283928); + fall_capacitance_range (0.00252797, 0.00302613); timing () { related_pin : "CLK"; + sdf_edges : both_edges; timing_type : hold_rising; rise_constraint (CONSTRAINT_4x4) { index_1 ("0.0186, 0.51636, 1.263, 2.5074"); @@ -31902,6 +32045,7 @@ library (sg13g2_stdcell_typ_1p20V_25C) { } timing () { related_pin : "CLK"; + sdf_edges : both_edges; timing_type : setup_rising; rise_constraint (CONSTRAINT_4x4) { index_1 ("0.0186, 0.51636, 1.263, 2.5074"); @@ -31960,11 +32104,12 @@ library (sg13g2_stdcell_typ_1p20V_25C) { max_transition : 2.5074; capacitance : 0.00484385; rise_capacitance : 0.0050874; - rise_capacitance_range (0.0050874, 0.0050874); + rise_capacitance_range (0.00444413, 0.00578189); fall_capacitance : 0.00460031; - fall_capacitance_range (0.00460031, 0.00460031); + fall_capacitance_range (0.00440955, 0.00509962); timing () { related_pin : "CLK"; + sdf_edges : both_edges; timing_type : hold_rising; rise_constraint (CONSTRAINT_4x4) { index_1 ("0.0186, 0.51636, 1.263, 2.5074"); @@ -31989,6 +32134,7 @@ library (sg13g2_stdcell_typ_1p20V_25C) { } timing () { related_pin : "CLK"; + sdf_edges : both_edges; timing_type : setup_rising; rise_constraint (CONSTRAINT_4x4) { index_1 ("0.0186, 0.51636, 1.263, 2.5074"); @@ -32057,9 +32203,9 @@ library (sg13g2_stdcell_typ_1p20V_25C) { } } ff (IQ,IQN) { - clear : "RESET_B'"; + clear : "!RESET_B"; clocked_on : "CLK"; - next_state : "(SCE*SCD)+(SCE'*D)"; + next_state : "(SCE*SCD)+(!SCE*D)"; } test_cell () { pin (Q) { @@ -32085,7 +32231,7 @@ library (sg13g2_stdcell_typ_1p20V_25C) { signal_type : test_scan_enable; } ff (IQ,IQN) { - clear : "RESET_B'"; + clear : "!RESET_B"; clocked_on : "CLK"; next_state : "D"; } @@ -32093,7 +32239,7 @@ library (sg13g2_stdcell_typ_1p20V_25C) { } cell (sg13g2_sighold) { area : 9.072; - cell_footprint : "keepstate"; + cell_footprint : "sighold"; cell_leakage_power : 161.571; dont_touch : true; dont_use : true; @@ -32131,7 +32277,7 @@ library (sg13g2_stdcell_typ_1p20V_25C) { } cell (sg13g2_slgcp_1) { area : 30.8448; - cell_footprint : "sgclk"; + cell_footprint : "slgcp"; cell_leakage_power : 415.618; clock_gating_integrated_cell : "latch_posedge_precontrol"; dont_touch : true; @@ -32270,9 +32416,9 @@ library (sg13g2_stdcell_typ_1p20V_25C) { max_transition : 2.5074; capacitance : 0.00497857; rise_capacitance : 0.00504226; - rise_capacitance_range (0.00504226, 0.00504226); + rise_capacitance_range (0.0043894, 0.00582153); fall_capacitance : 0.00491488; - fall_capacitance_range (0.00491488, 0.00491488); + fall_capacitance_range (0.00454194, 0.00519746); timing () { related_pin : "CLK"; timing_type : min_pulse_width; @@ -32310,11 +32456,12 @@ library (sg13g2_stdcell_typ_1p20V_25C) { max_transition : 2.5074; capacitance : 0.00193037; rise_capacitance : 0.0023337; - rise_capacitance_range (0.0023337, 0.0023337); + rise_capacitance_range (0.00214055, 0.00249301); fall_capacitance : 0.00152704; - fall_capacitance_range (0.00152704, 0.00152704); + fall_capacitance_range (0.00152704, 0.00241918); timing () { related_pin : "CLK"; + sdf_edges : both_edges; timing_type : hold_rising; rise_constraint (CONSTRAINT_4x4) { index_1 ("0.0186, 0.51636, 1.263, 2.5074"); @@ -32339,6 +32486,7 @@ library (sg13g2_stdcell_typ_1p20V_25C) { } timing () { related_pin : "CLK"; + sdf_edges : both_edges; timing_type : setup_rising; rise_constraint (CONSTRAINT_4x4) { index_1 ("0.0186, 0.51636, 1.263, 2.5074"); @@ -32397,11 +32545,12 @@ library (sg13g2_stdcell_typ_1p20V_25C) { max_transition : 2.5074; capacitance : 0.00232746; rise_capacitance : 0.00229122; - rise_capacitance_range (0.00229122, 0.00229122); + rise_capacitance_range (0.00214384, 0.00241128); fall_capacitance : 0.0023637; - fall_capacitance_range (0.0023637, 0.0023637); + fall_capacitance_range (0.0021699, 0.00254935); timing () { related_pin : "CLK"; + sdf_edges : both_edges; timing_type : hold_rising; rise_constraint (CONSTRAINT_4x4) { index_1 ("0.0186, 0.51636, 1.263, 2.5074"); @@ -32426,6 +32575,7 @@ library (sg13g2_stdcell_typ_1p20V_25C) { } timing () { related_pin : "CLK"; + sdf_edges : both_edges; timing_type : setup_rising; rise_constraint (CONSTRAINT_4x4) { index_1 ("0.0186, 0.51636, 1.263, 2.5074"); @@ -32466,7 +32616,7 @@ library (sg13g2_stdcell_typ_1p20V_25C) { } cell (sg13g2_tiehi) { area : 7.2576; - cell_footprint : "tie1"; + cell_footprint : "tiehi"; cell_leakage_power : 58.0661; pin (L_HI) { direction : "output"; @@ -32476,7 +32626,7 @@ library (sg13g2_stdcell_typ_1p20V_25C) { } cell (sg13g2_tielo) { area : 7.2576; - cell_footprint : "tie0"; + cell_footprint : "tielo"; cell_leakage_power : 57.848; pin (L_LO) { direction : "output"; @@ -32486,7 +32636,7 @@ library (sg13g2_stdcell_typ_1p20V_25C) { } cell (sg13g2_xnor2_1) { area : 14.5152; - cell_footprint : "xnor2_1"; + cell_footprint : "xnor2"; cell_leakage_power : 194.767; leakage_power () { value : 225.812; @@ -33043,23 +33193,23 @@ library (sg13g2_stdcell_typ_1p20V_25C) { max_transition : 2.5074; capacitance : 0.00562179; rise_capacitance : 0.00565498; - rise_capacitance_range (0.00565498, 0.00565498); + rise_capacitance_range (0.00488317, 0.00675279); fall_capacitance : 0.0055886; - fall_capacitance_range (0.0055886, 0.0055886); + fall_capacitance_range (0.00482796, 0.00650562); } pin (B) { direction : "input"; max_transition : 2.5074; capacitance : 0.00508831; rise_capacitance : 0.00510961; - rise_capacitance_range (0.00510961, 0.00510961); + rise_capacitance_range (0.00443518, 0.00591128); fall_capacitance : 0.00506701; - fall_capacitance_range (0.00506701, 0.00506701); + fall_capacitance_range (0.00440544, 0.00570882); } } cell (sg13g2_xor2_1) { area : 14.5152; - cell_footprint : "xor2_1"; + cell_footprint : "xor2"; cell_leakage_power : 184.817; leakage_power () { value : 194.557; @@ -33616,18 +33766,18 @@ library (sg13g2_stdcell_typ_1p20V_25C) { max_transition : 2.5074; capacitance : 0.00574527; rise_capacitance : 0.00581365; - rise_capacitance_range (0.00581365, 0.00581365); + rise_capacitance_range (0.00507494, 0.00665093); fall_capacitance : 0.00567688; - fall_capacitance_range (0.00567688, 0.00567688); + fall_capacitance_range (0.00482666, 0.00690317); } pin (B) { direction : "input"; max_transition : 2.5074; capacitance : 0.00513561; rise_capacitance : 0.00521677; - rise_capacitance_range (0.00521677, 0.00521677); + rise_capacitance_range (0.00449637, 0.00593308); fall_capacitance : 0.00505445; - fall_capacitance_range (0.00505445, 0.00505445); + fall_capacitance_range (0.00447156, 0.00572452); } } } diff --git a/flow/platforms/ihp-sg13g2/lib/sg13g2_stdcell_typ_1p50V_25C.lib b/flow/platforms/ihp-sg13g2/lib/sg13g2_stdcell_typ_1p50V_25C.lib index 3e211a59ea..a1a8b7b9f4 100644 --- a/flow/platforms/ihp-sg13g2/lib/sg13g2_stdcell_typ_1p50V_25C.lib +++ b/flow/platforms/ihp-sg13g2/lib/sg13g2_stdcell_typ_1p50V_25C.lib @@ -18,8 +18,8 @@ library (sg13g2_stdcell_typ_1p50V_25C) { comment : "IHP Microelectronics GmbH, 2025"; - date : "$Date: Fri Jun 13 12:10:45 2025 $"; - revision : "$Revision: 0.1.3 $"; + date : "$Date: Tue Nov 4 17:16:55 2025 $"; + revision : "$Revision: 0.1.4 $"; delay_model : table_lookup; capacitive_load_unit (1,pf); current_unit : "1uA"; @@ -210,7 +210,7 @@ library (sg13g2_stdcell_typ_1p50V_25C) { } cell (sg13g2_a21o_1) { area : 12.7008; - cell_footprint : "AO21"; + cell_footprint : "a21o"; cell_leakage_power : 458.001; leakage_power () { value : 437.62; @@ -483,7 +483,7 @@ library (sg13g2_stdcell_typ_1p50V_25C) { } timing () { related_pin : "B1"; - sdf_cond : "A1 == 1'b1 & A2 == 1'b0"; + sdf_cond : "A1 == 1'b1 && A2 == 1'b0"; timing_sense : positive_unate; timing_type : combinational; when : "(A1 * !A2)"; @@ -542,7 +542,7 @@ library (sg13g2_stdcell_typ_1p50V_25C) { } timing () { related_pin : "B1"; - sdf_cond : "A1 == 1'b0 & A2 == 1'b1"; + sdf_cond : "A1 == 1'b0 && A2 == 1'b1"; timing_sense : positive_unate; timing_type : combinational; when : "(!A1 * A2)"; @@ -601,7 +601,7 @@ library (sg13g2_stdcell_typ_1p50V_25C) { } timing () { related_pin : "B1"; - sdf_cond : "A1 == 1'b0 & A2 == 1'b0"; + sdf_cond : "A1 == 1'b0 && A2 == 1'b0"; timing_sense : positive_unate; timing_type : combinational; when : "(!A1 * !A2)"; @@ -958,32 +958,32 @@ library (sg13g2_stdcell_typ_1p50V_25C) { max_transition : 2.5074; capacitance : 0.00287667; rise_capacitance : 0.00281567; - rise_capacitance_range (0.00281567, 0.00281567); + rise_capacitance_range (0.00256093, 0.00300972); fall_capacitance : 0.00293768; - fall_capacitance_range (0.00293768, 0.00293768); + fall_capacitance_range (0.00248005, 0.00322583); } pin (A2) { direction : "input"; max_transition : 2.5074; capacitance : 0.00299717; rise_capacitance : 0.00304234; - rise_capacitance_range (0.00304234, 0.00304234); + rise_capacitance_range (0.00258276, 0.00327396); fall_capacitance : 0.002952; - fall_capacitance_range (0.002952, 0.002952); + fall_capacitance_range (0.00256594, 0.00317604); } pin (B1) { direction : "input"; max_transition : 2.5074; capacitance : 0.00278843; rise_capacitance : 0.00292333; - rise_capacitance_range (0.00292333, 0.00292333); + rise_capacitance_range (0.00237931, 0.00338167); fall_capacitance : 0.00265352; - fall_capacitance_range (0.00265352, 0.00265352); + fall_capacitance_range (0.00241677, 0.002863); } } cell (sg13g2_a21o_2) { area : 14.5152; - cell_footprint : "AO21"; + cell_footprint : "a21o"; cell_leakage_power : 642.569; leakage_power () { value : 685.815; @@ -1256,7 +1256,7 @@ library (sg13g2_stdcell_typ_1p50V_25C) { } timing () { related_pin : "B1"; - sdf_cond : "A1 == 1'b1 & A2 == 1'b0"; + sdf_cond : "A1 == 1'b1 && A2 == 1'b0"; timing_sense : positive_unate; timing_type : combinational; when : "(A1 * !A2)"; @@ -1315,7 +1315,7 @@ library (sg13g2_stdcell_typ_1p50V_25C) { } timing () { related_pin : "B1"; - sdf_cond : "A1 == 1'b0 & A2 == 1'b1"; + sdf_cond : "A1 == 1'b0 && A2 == 1'b1"; timing_sense : positive_unate; timing_type : combinational; when : "(!A1 * A2)"; @@ -1374,7 +1374,7 @@ library (sg13g2_stdcell_typ_1p50V_25C) { } timing () { related_pin : "B1"; - sdf_cond : "A1 == 1'b0 & A2 == 1'b0"; + sdf_cond : "A1 == 1'b0 && A2 == 1'b0"; timing_sense : positive_unate; timing_type : combinational; when : "(!A1 * !A2)"; @@ -1731,27 +1731,27 @@ library (sg13g2_stdcell_typ_1p50V_25C) { max_transition : 2.5074; capacitance : 0.00306177; rise_capacitance : 0.00298274; - rise_capacitance_range (0.00298274, 0.00298274); + rise_capacitance_range (0.00271794, 0.00321822); fall_capacitance : 0.00314081; - fall_capacitance_range (0.00314081, 0.00314081); + fall_capacitance_range (0.00269475, 0.00340451); } pin (A2) { direction : "input"; max_transition : 2.5074; capacitance : 0.00309394; rise_capacitance : 0.00313313; - rise_capacitance_range (0.00313313, 0.00313313); + rise_capacitance_range (0.00262721, 0.00339442); fall_capacitance : 0.00305476; - fall_capacitance_range (0.00305476, 0.00305476); + fall_capacitance_range (0.00267654, 0.00326513); } pin (B1) { direction : "input"; max_transition : 2.5074; capacitance : 0.00290893; rise_capacitance : 0.00303064; - rise_capacitance_range (0.00303064, 0.00303064); + rise_capacitance_range (0.00252284, 0.00352866); fall_capacitance : 0.00278722; - fall_capacitance_range (0.00278722, 0.00278722); + fall_capacitance_range (0.00258156, 0.00295239); } } cell (sg13g2_a21oi_1) { @@ -1759,7 +1759,7 @@ library (sg13g2_stdcell_typ_1p50V_25C) { cell_footprint : "a21oi"; cell_leakage_power : 358.546; leakage_power () { - value : 222.669; + value : 222.67; when : "!A1&!A2&!B1&Y"; } leakage_power () { @@ -1767,15 +1767,15 @@ library (sg13g2_stdcell_typ_1p50V_25C) { when : "!A1&!A2&B1&!Y"; } leakage_power () { - value : 326.693; + value : 326.694; when : "!A1&A2&!B1&Y"; } leakage_power () { - value : 439.284; + value : 439.285; when : "!A1&A2&B1&!Y"; } leakage_power () { - value : 186.831; + value : 186.832; when : "A1&!A2&!B1&Y"; } leakage_power () { @@ -1783,7 +1783,7 @@ library (sg13g2_stdcell_typ_1p50V_25C) { when : "A1&!A2&B1&!Y"; } leakage_power () { - value : 434.765; + value : 434.766; when : "A1&A2&!B1&!Y"; } leakage_power () { @@ -1803,12 +1803,12 @@ library (sg13g2_stdcell_typ_1p50V_25C) { index_1 ("0.0186, 0.0966, 0.174, 0.3294, 0.6408, 1.263, 2.5074"); index_2 ("0.001, 0.0234, 0.039, 0.0648, 0.108, 0.18, 0.3"); values ( \ - "0.0332286, 0.125353, 0.187891, 0.291086, 0.463969, 0.75182, 1.23161", \ - "0.0469452, 0.148306, 0.211424, 0.314953, 0.488078, 0.776253, 1.25576", \ - "0.053966, 0.167516, 0.233041, 0.337528, 0.510669, 0.799061, 1.27883", \ - "0.0611555, 0.196814, 0.269025, 0.379348, 0.555252, 0.843744, 1.32411", \ - "0.0726877, 0.241112, 0.325945, 0.44964, 0.637787, 0.933614, 1.4152", \ - "0.0874945, 0.301383, 0.405797, 0.554456, 0.768774, 1.09161, 1.59189", \ + "0.0332301, 0.125356, 0.187893, 0.291165, 0.46397, 0.751836, 1.23161", \ + "0.0469451, 0.148332, 0.211423, 0.315059, 0.488068, 0.776242, 1.25575", \ + "0.053966, 0.167516, 0.233041, 0.337528, 0.510687, 0.799061, 1.27883", \ + "0.0611555, 0.196814, 0.269025, 0.379349, 0.555253, 0.843743, 1.32411", \ + "0.0726877, 0.241112, 0.325945, 0.449639, 0.637831, 0.933613, 1.41517", \ + "0.0874944, 0.301382, 0.405797, 0.554456, 0.768774, 1.0916, 1.59189", \ "0.101159, 0.383925, 0.513851, 0.697801, 0.960044, 1.33599, 1.8931" \ ); } @@ -1816,24 +1816,24 @@ library (sg13g2_stdcell_typ_1p50V_25C) { index_1 ("0.0186, 0.0966, 0.174, 0.3294, 0.6408, 1.263, 2.5074"); index_2 ("0.001, 0.0234, 0.039, 0.0648, 0.108, 0.18, 0.3"); values ( \ - "0.0207505, 0.15015, 0.240119, 0.389192, 0.63883, 1.05511, 1.74823", \ - "0.0309327, 0.153124, 0.241217, 0.389399, 0.638831, 1.05512, 1.74824", \ - "0.0413255, 0.162673, 0.247631, 0.392242, 0.643388, 1.05513, 1.74853", \ - "0.0598697, 0.185849, 0.268988, 0.407962, 0.647738, 1.0572, 1.7514", \ - "0.0914443, 0.231037, 0.316186, 0.453741, 0.683335, 1.07895, 1.75651", \ - "0.140512, 0.303846, 0.399605, 0.545222, 0.776111, 1.1576, 1.81001", \ - "0.223357, 0.425114, 0.53482, 0.701896, 0.951973, 1.3418, 1.98098" \ + "0.0207536, 0.150153, 0.24012, 0.389202, 0.63883, 1.05511, 1.74823", \ + "0.0309326, 0.153182, 0.241259, 0.389694, 0.638831, 1.05512, 1.74824", \ + "0.0413254, 0.162673, 0.247631, 0.392242, 0.643371, 1.05513, 1.74853", \ + "0.0598698, 0.18585, 0.268988, 0.407983, 0.647756, 1.0572, 1.7514", \ + "0.0914442, 0.231037, 0.316186, 0.45374, 0.683382, 1.07895, 1.75643", \ + "0.140512, 0.303846, 0.399605, 0.545221, 0.77611, 1.1576, 1.81001", \ + "0.223357, 0.425114, 0.534821, 0.701895, 0.951973, 1.3418, 1.98098" \ ); } cell_fall (TIMING_DELAY_7x7ds1) { index_1 ("0.0186, 0.0966, 0.174, 0.3294, 0.6408, 1.263, 2.5074"); index_2 ("0.001, 0.0234, 0.039, 0.0648, 0.108, 0.18, 0.3"); values ( \ - "0.0282008, 0.0924368, 0.1355, 0.206444, 0.325078, 0.522811, 0.851741", \ - "0.0466047, 0.126606, 0.171458, 0.242831, 0.361348, 0.558814, 0.888019", \ - "0.0570458, 0.152298, 0.20236, 0.277871, 0.398028, 0.595556, 0.92454", \ - "0.0714496, 0.189774, 0.249899, 0.336744, 0.466099, 0.667733, 0.996891", \ - "0.0910954, 0.243611, 0.318268, 0.424367, 0.576589, 0.800233, 1.14217", \ + "0.0282007, 0.092444, 0.135479, 0.206443, 0.325077, 0.522804, 0.851743", \ + "0.0466047, 0.126605, 0.171459, 0.242832, 0.361358, 0.558744, 0.888023", \ + "0.0570458, 0.152298, 0.202364, 0.277871, 0.398028, 0.595543, 0.924421", \ + "0.0714496, 0.189774, 0.249899, 0.336744, 0.466099, 0.667733, 0.996858", \ + "0.0910954, 0.243611, 0.318268, 0.424367, 0.576589, 0.800232, 1.14218", \ "0.117514, 0.315693, 0.413232, 0.546526, 0.736655, 1.00491, 1.39429", \ "0.153012, 0.409611, 0.537399, 0.713249, 0.955844, 1.29333, 1.76913" \ ); @@ -1842,13 +1842,13 @@ library (sg13g2_stdcell_typ_1p50V_25C) { index_1 ("0.0186, 0.0966, 0.174, 0.3294, 0.6408, 1.263, 2.5074"); index_2 ("0.001, 0.0234, 0.039, 0.0648, 0.108, 0.18, 0.3"); values ( \ - "0.0207986, 0.103191, 0.161364, 0.257213, 0.417892, 0.685673, 1.13121", \ - "0.0347991, 0.113877, 0.167656, 0.259931, 0.418317, 0.685674, 1.13174", \ - "0.0460477, 0.130986, 0.183681, 0.271649, 0.424446, 0.68949, 1.13175", \ - "0.0642945, 0.162707, 0.218102, 0.305609, 0.450752, 0.701672, 1.13542", \ - "0.0947888, 0.216688, 0.279058, 0.373546, 0.521409, 0.761532, 1.17349", \ - "0.143147, 0.307981, 0.381378, 0.489464, 0.650263, 0.90193, 1.30385", \ - "0.226015, 0.451644, 0.552027, 0.683728, 0.873729, 1.1512, 1.58275" \ + "0.0207986, 0.103232, 0.161225, 0.257213, 0.417885, 0.685672, 1.13121", \ + "0.0347991, 0.113833, 0.167654, 0.259932, 0.418317, 0.685673, 1.13174", \ + "0.0460478, 0.130986, 0.183706, 0.271649, 0.424446, 0.689472, 1.13175", \ + "0.0642945, 0.162707, 0.218101, 0.305609, 0.450752, 0.701672, 1.13585", \ + "0.0947888, 0.216688, 0.279058, 0.373546, 0.521409, 0.761532, 1.17358", \ + "0.143147, 0.307981, 0.381378, 0.489464, 0.650263, 0.901864, 1.30385", \ + "0.226015, 0.451644, 0.552027, 0.683729, 0.873729, 1.1512, 1.58275" \ ); } } @@ -1860,37 +1860,37 @@ library (sg13g2_stdcell_typ_1p50V_25C) { index_1 ("0.0186, 0.0966, 0.174, 0.3294, 0.6408, 1.263, 2.5074"); index_2 ("0.001, 0.0234, 0.039, 0.0648, 0.108, 0.18, 0.3"); values ( \ - "0.0394042, 0.130809, 0.19355, 0.297121, 0.470399, 0.759453, 1.2409", \ - "0.0556961, 0.154634, 0.217649, 0.321435, 0.494708, 0.783706, 1.26493", \ - "0.064779, 0.174439, 0.239623, 0.344076, 0.517565, 0.806742, 1.28803", \ - "0.0754932, 0.204871, 0.276512, 0.386351, 0.562206, 0.851352, 1.33338", \ - "0.0938999, 0.251566, 0.335134, 0.457539, 0.645472, 0.941619, 1.4246", \ - "0.121072, 0.317892, 0.418781, 0.565427, 0.777653, 1.10048, 1.60142", \ - "0.158022, 0.412623, 0.537476, 0.716856, 0.976972, 1.34968, 1.9042" \ + "0.0394039, 0.130814, 0.193544, 0.297198, 0.470398, 0.759378, 1.24041", \ + "0.055696, 0.154622, 0.217649, 0.32149, 0.494682, 0.783688, 1.26495", \ + "0.064779, 0.174439, 0.239624, 0.344076, 0.517546, 0.806742, 1.28803", \ + "0.0754932, 0.204871, 0.276509, 0.386351, 0.562195, 0.851352, 1.33335", \ + "0.0938998, 0.251566, 0.335134, 0.457539, 0.645471, 0.941515, 1.42466", \ + "0.121072, 0.317892, 0.418781, 0.565427, 0.777652, 1.10048, 1.60142", \ + "0.158022, 0.412623, 0.537476, 0.716855, 0.976972, 1.34968, 1.90419" \ ); } rise_transition (TIMING_DELAY_7x7ds1) { index_1 ("0.0186, 0.0966, 0.174, 0.3294, 0.6408, 1.263, 2.5074"); index_2 ("0.001, 0.0234, 0.039, 0.0648, 0.108, 0.18, 0.3"); values ( \ - "0.0271338, 0.157302, 0.247949, 0.397599, 0.648488, 1.06618, 1.76194", \ - "0.0365882, 0.16029, 0.248962, 0.3977, 0.648489, 1.06619, 1.76195", \ - "0.0464174, 0.169423, 0.255087, 0.400494, 0.648842, 1.0662, 1.76197", \ - "0.0645223, 0.192273, 0.275747, 0.415952, 0.656839, 1.06803, 1.76434", \ - "0.0937918, 0.236565, 0.322464, 0.460958, 0.692359, 1.08973, 1.76962", \ - "0.139709, 0.307481, 0.402769, 0.551504, 0.783423, 1.16731, 1.82298", \ - "0.216818, 0.424123, 0.536808, 0.704894, 0.957623, 1.352, 1.99215" \ + "0.027133, 0.157304, 0.247948, 0.397564, 0.648484, 1.06612, 1.76149", \ + "0.036588, 0.160261, 0.248961, 0.397752, 0.648485, 1.06613, 1.76174", \ + "0.0464173, 0.169423, 0.255117, 0.400493, 0.650911, 1.06614, 1.76196", \ + "0.0645223, 0.192272, 0.275744, 0.415951, 0.656943, 1.06805, 1.76502", \ + "0.0937917, 0.236565, 0.322464, 0.460957, 0.692358, 1.08961, 1.77003", \ + "0.139709, 0.30748, 0.402768, 0.551505, 0.783423, 1.1673, 1.82298", \ + "0.216818, 0.424122, 0.536807, 0.704894, 0.957622, 1.352, 1.99214" \ ); } cell_fall (TIMING_DELAY_7x7ds1) { index_1 ("0.0186, 0.0966, 0.174, 0.3294, 0.6408, 1.263, 2.5074"); index_2 ("0.001, 0.0234, 0.039, 0.0648, 0.108, 0.18, 0.3"); values ( \ - "0.0307019, 0.0946474, 0.137746, 0.208633, 0.327262, 0.524796, 0.854011", \ - "0.0469575, 0.121462, 0.16583, 0.237279, 0.355993, 0.553524, 0.882925", \ - "0.055951, 0.142361, 0.190174, 0.264323, 0.384227, 0.582067, 0.911353", \ - "0.0676232, 0.174243, 0.229242, 0.31069, 0.437037, 0.637962, 0.967688", \ - "0.0833496, 0.221511, 0.288403, 0.384417, 0.5263, 0.741732, 1.08044", \ + "0.0307023, 0.0946275, 0.137745, 0.20869, 0.327263, 0.524795, 0.854009", \ + "0.0469576, 0.121461, 0.16583, 0.23726, 0.356025, 0.553523, 0.88292", \ + "0.055951, 0.142361, 0.190174, 0.264323, 0.384227, 0.582067, 0.911358", \ + "0.0676232, 0.174243, 0.229242, 0.31069, 0.437037, 0.637962, 0.967669", \ + "0.0833496, 0.221511, 0.288402, 0.384417, 0.5263, 0.741731, 1.08044", \ "0.103379, 0.283496, 0.372, 0.492147, 0.662141, 0.909326, 1.27938", \ "0.126075, 0.361276, 0.477925, 0.638237, 0.85657, 1.15825, 1.59203" \ ); @@ -1899,13 +1899,13 @@ library (sg13g2_stdcell_typ_1p50V_25C) { index_1 ("0.0186, 0.0966, 0.174, 0.3294, 0.6408, 1.263, 2.5074"); index_2 ("0.001, 0.0234, 0.039, 0.0648, 0.108, 0.18, 0.3"); values ( \ - "0.0201735, 0.103225, 0.161417, 0.257063, 0.418201, 0.685565, 1.13176", \ - "0.0301368, 0.109692, 0.165174, 0.258977, 0.418525, 0.685809, 1.13177", \ - "0.0402686, 0.121137, 0.175298, 0.266137, 0.421912, 0.686965, 1.13178", \ - "0.0581039, 0.144828, 0.199114, 0.288355, 0.438427, 0.695847, 1.13487", \ - "0.0870532, 0.19005, 0.246809, 0.336289, 0.48588, 0.733818, 1.15791", \ + "0.0201736, 0.103221, 0.161416, 0.257408, 0.418201, 0.6857, 1.13176", \ + "0.0301367, 0.109687, 0.165176, 0.258815, 0.418202, 0.685808, 1.13177", \ + "0.0402686, 0.121137, 0.175298, 0.266145, 0.421912, 0.686965, 1.13178", \ + "0.0581039, 0.144828, 0.199115, 0.288355, 0.438427, 0.695846, 1.13445", \ + "0.0870532, 0.19005, 0.246809, 0.336289, 0.48588, 0.733819, 1.15791", \ "0.13301, 0.270044, 0.334065, 0.431145, 0.582987, 0.831436, 1.24306", \ - "0.20899, 0.396057, 0.483175, 0.598965, 0.764254, 1.02318, 1.43858" \ + "0.20899, 0.396057, 0.483175, 0.598965, 0.764255, 1.02319, 1.43858" \ ); } } @@ -1919,52 +1919,52 @@ library (sg13g2_stdcell_typ_1p50V_25C) { index_1 ("0.0186, 0.0966, 0.174, 0.3294, 0.6408, 1.263, 2.5074"); index_2 ("0.001, 0.0234, 0.039, 0.0648, 0.108, 0.18, 0.3"); values ( \ - "0.0320305, 0.124882, 0.187812, 0.291471, 0.464979, 0.753744, 1.23524", \ - "0.0519236, 0.155748, 0.218864, 0.322562, 0.496054, 0.7851, 1.26651", \ - "0.0648862, 0.183995, 0.250235, 0.354746, 0.527918, 0.816649, 1.29792", \ - "0.0820272, 0.227691, 0.303423, 0.416077, 0.59269, 0.88109, 1.36186", \ - "0.109634, 0.291409, 0.383723, 0.516772, 0.711472, 1.01071, 1.49224", \ - "0.152147, 0.379779, 0.496596, 0.661263, 0.896737, 1.23678, 1.74667", \ - "0.219046, 0.507489, 0.654074, 0.863179, 1.15959, 1.57393, 2.17085" \ + "0.0320282, 0.124885, 0.187753, 0.291469, 0.464979, 0.753745, 1.23546", \ + "0.0519239, 0.155739, 0.218858, 0.322589, 0.49607, 0.785103, 1.2665", \ + "0.0648862, 0.183995, 0.250234, 0.354746, 0.527948, 0.816649, 1.29792", \ + "0.0820272, 0.227691, 0.303425, 0.416081, 0.59269, 0.881092, 1.36185", \ + "0.109634, 0.291409, 0.383723, 0.516772, 0.711471, 1.01072, 1.49254", \ + "0.152147, 0.379791, 0.496596, 0.661262, 0.896736, 1.23678, 1.74666", \ + "0.219046, 0.507488, 0.654074, 0.863178, 1.15958, 1.57392, 2.17085" \ ); } rise_transition (TIMING_DELAY_7x7ds1) { index_1 ("0.0186, 0.0966, 0.174, 0.3294, 0.6408, 1.263, 2.5074"); index_2 ("0.001, 0.0234, 0.039, 0.0648, 0.108, 0.18, 0.3"); values ( \ - "0.0274188, 0.157514, 0.24791, 0.397601, 0.648307, 1.06583, 1.76213", \ - "0.0412829, 0.162494, 0.249629, 0.397655, 0.648308, 1.06587, 1.76214", \ - "0.051306, 0.177247, 0.259993, 0.402568, 0.649289, 1.06588, 1.76215", \ - "0.0677487, 0.209878, 0.291762, 0.427302, 0.662393, 1.07092, 1.76709", \ - "0.0951774, 0.265, 0.355044, 0.49252, 0.718243, 1.10421, 1.77534", \ - "0.141922, 0.348558, 0.45642, 0.612166, 0.847736, 1.22337, 1.85906", \ - "0.224098, 0.479186, 0.611781, 0.801254, 1.07621, 1.48019, 2.11204" \ + "0.0274182, 0.157513, 0.247891, 0.397601, 0.648306, 1.06583, 1.76194", \ + "0.041283, 0.162484, 0.249659, 0.397662, 0.648307, 1.06588, 1.76195", \ + "0.051306, 0.177247, 0.259993, 0.402568, 0.650541, 1.06589, 1.76196", \ + "0.0677487, 0.209878, 0.291764, 0.427312, 0.662393, 1.07092, 1.76214", \ + "0.0951773, 0.264999, 0.355044, 0.492519, 0.71812, 1.10428, 1.77533", \ + "0.141923, 0.348568, 0.45642, 0.612165, 0.847735, 1.22337, 1.85906", \ + "0.224097, 0.479185, 0.61178, 0.801253, 1.07621, 1.48017, 2.11204" \ ); } cell_fall (TIMING_DELAY_7x7ds1) { index_1 ("0.0186, 0.0966, 0.174, 0.3294, 0.6408, 1.263, 2.5074"); index_2 ("0.001, 0.0234, 0.039, 0.0648, 0.108, 0.18, 0.3"); values ( \ - "0.0164708, 0.0555555, 0.0806972, 0.122174, 0.191636, 0.307011, 0.498967", \ - "0.0278204, 0.0894146, 0.119386, 0.163368, 0.233562, 0.348946, 0.540825", \ - "0.033246, 0.111376, 0.147224, 0.197894, 0.273209, 0.390831, 0.582843", \ - "0.0389858, 0.141933, 0.187567, 0.250146, 0.338928, 0.46756, 0.664915", \ + "0.0164709, 0.055548, 0.0806969, 0.122201, 0.19164, 0.307014, 0.499114", \ + "0.0278215, 0.0894147, 0.119393, 0.163362, 0.233572, 0.348978, 0.540844", \ + "0.033246, 0.111376, 0.147224, 0.197894, 0.273209, 0.390831, 0.582845", \ + "0.0389858, 0.141933, 0.187567, 0.250146, 0.338928, 0.46756, 0.664911", \ "0.0439675, 0.182122, 0.243393, 0.324765, 0.436764, 0.592237, 0.814809", \ - "0.0461151, 0.228899, 0.313086, 0.424132, 0.570922, 0.771679, 1.04546", \ - "0.0461161, 0.273405, 0.387859, 0.54095, 0.744571, 1.01126, 1.37058" \ + "0.0461149, 0.228899, 0.313086, 0.424132, 0.570922, 0.771679, 1.04546", \ + "0.0461159, 0.273405, 0.387859, 0.54095, 0.744571, 1.01126, 1.37058" \ ); } fall_transition (TIMING_DELAY_7x7ds1) { index_1 ("0.0186, 0.0966, 0.174, 0.3294, 0.6408, 1.263, 2.5074"); index_2 ("0.001, 0.0234, 0.039, 0.0648, 0.108, 0.18, 0.3"); values ( \ - "0.0130016, 0.0594616, 0.0932205, 0.148962, 0.242661, 0.398936, 0.659438", \ - "0.029928, 0.0763153, 0.106178, 0.156984, 0.245663, 0.399352, 0.659439", \ - "0.0422866, 0.0944419, 0.125369, 0.175206, 0.259712, 0.406648, 0.661791", \ - "0.0622031, 0.126235, 0.160472, 0.213727, 0.297551, 0.436466, 0.677499", \ - "0.0952629, 0.179917, 0.221351, 0.281218, 0.37307, 0.514319, 0.744321", \ - "0.149335, 0.266685, 0.321766, 0.394471, 0.501644, 0.65818, 0.90088", \ - "0.241054, 0.404602, 0.481939, 0.583941, 0.716833, 0.906121, 1.17636" \ + "0.0130016, 0.0594771, 0.0932205, 0.148934, 0.242661, 0.398947, 0.659309", \ + "0.0299207, 0.0763154, 0.106181, 0.156961, 0.245818, 0.399439, 0.65931", \ + "0.0422867, 0.094442, 0.125369, 0.175206, 0.259712, 0.406648, 0.661207", \ + "0.0622031, 0.126235, 0.160472, 0.213728, 0.297552, 0.436468, 0.677474", \ + "0.095263, 0.179917, 0.221351, 0.281218, 0.37307, 0.514319, 0.744321", \ + "0.149335, 0.266685, 0.321766, 0.394472, 0.501644, 0.658181, 0.90088", \ + "0.241054, 0.404602, 0.481938, 0.583941, 0.716834, 0.906121, 1.17636" \ ); } } @@ -1978,52 +1978,52 @@ library (sg13g2_stdcell_typ_1p50V_25C) { index_1 ("0.0186, 0.0966, 0.174, 0.3294, 0.6408, 1.263, 2.5074"); index_2 ("0.001, 0.0234, 0.039, 0.0648, 0.108, 0.18, 0.3"); values ( \ - "0.0250222, 0.117361, 0.180062, 0.283373, 0.456384, 0.744257, 1.22383", \ - "0.0411858, 0.148242, 0.211186, 0.314508, 0.487443, 0.775575, 1.25508", \ - "0.0515957, 0.175758, 0.242347, 0.34665, 0.51918, 0.806941, 1.28695", \ - "0.0656568, 0.217776, 0.294669, 0.407575, 0.583901, 0.871393, 1.35099", \ + "0.0250222, 0.117433, 0.180062, 0.283387, 0.456384, 0.744209, 1.22384", \ + "0.0411858, 0.148253, 0.211189, 0.314501, 0.487385, 0.775157, 1.2551", \ + "0.0515957, 0.175758, 0.242347, 0.346639, 0.519217, 0.810938, 1.28695", \ + "0.0656568, 0.217776, 0.29467, 0.407572, 0.583899, 0.871351, 1.3509", \ "0.0885187, 0.27933, 0.372958, 0.506667, 0.702411, 1.00091, 1.48114", \ - "0.124302, 0.364231, 0.483027, 0.649022, 0.885205, 1.22592, 1.73485", \ - "0.182689, 0.488041, 0.63698, 0.847709, 1.14549, 1.56121, 2.15653" \ + "0.124302, 0.364231, 0.483027, 0.649022, 0.885204, 1.22592, 1.73491", \ + "0.182689, 0.48804, 0.63698, 0.847708, 1.14549, 1.56121, 2.15653" \ ); } rise_transition (TIMING_DELAY_7x7ds1) { index_1 ("0.0186, 0.0966, 0.174, 0.3294, 0.6408, 1.263, 2.5074"); index_2 ("0.001, 0.0234, 0.039, 0.0648, 0.108, 0.18, 0.3"); values ( \ - "0.0214612, 0.150002, 0.240111, 0.389185, 0.638838, 1.05485, 1.74834", \ - "0.0352478, 0.155798, 0.242164, 0.391182, 0.638839, 1.05486, 1.74835", \ - "0.0450313, 0.171049, 0.253044, 0.394499, 0.641515, 1.05487, 1.74867", \ - "0.0599138, 0.203606, 0.285207, 0.419959, 0.653488, 1.05891, 1.75066", \ - "0.0862504, 0.257917, 0.347977, 0.485096, 0.710028, 1.09401, 1.76201", \ - "0.132205, 0.341728, 0.449011, 0.604168, 0.840475, 1.21385, 1.84645", \ - "0.214526, 0.471112, 0.605653, 0.796783, 1.06719, 1.46978, 2.10115" \ + "0.0214612, 0.149989, 0.240111, 0.389184, 0.638837, 1.05475, 1.74868", \ + "0.0352478, 0.155834, 0.242193, 0.389398, 0.638838, 1.05504, 1.74869", \ + "0.0450313, 0.171049, 0.253044, 0.394376, 0.641861, 1.05859, 1.7487", \ + "0.0599139, 0.203608, 0.285206, 0.419867, 0.653397, 1.05886, 1.75058", \ + "0.0862503, 0.257917, 0.347978, 0.485099, 0.710027, 1.09401, 1.762", \ + "0.132205, 0.341728, 0.449011, 0.604168, 0.840475, 1.21385, 1.84679", \ + "0.214526, 0.471111, 0.605652, 0.796782, 1.06719, 1.46979, 2.10115" \ ); } cell_fall (TIMING_DELAY_7x7ds1) { index_1 ("0.0186, 0.0966, 0.174, 0.3294, 0.6408, 1.263, 2.5074"); index_2 ("0.001, 0.0234, 0.039, 0.0648, 0.108, 0.18, 0.3"); values ( \ - "0.0161473, 0.0551082, 0.0801113, 0.121384, 0.190499, 0.30555, 0.497505", \ - "0.0268312, 0.0887117, 0.118664, 0.162558, 0.232398, 0.347493, 0.539227", \ - "0.031703, 0.110417, 0.146249, 0.196834, 0.271961, 0.389329, 0.581312", \ + "0.0161484, 0.0551073, 0.080112, 0.121413, 0.190441, 0.305549, 0.497499", \ + "0.0268312, 0.0887117, 0.118695, 0.162559, 0.232408, 0.347493, 0.539209", \ + "0.031703, 0.110417, 0.146249, 0.196834, 0.271961, 0.389329, 0.581321", \ "0.0360928, 0.140426, 0.186132, 0.248708, 0.337379, 0.465955, 0.663279", \ - "0.0383987, 0.179366, 0.241125, 0.322444, 0.43465, 0.590265, 0.813122", \ - "0.0383997, 0.223518, 0.308608, 0.420663, 0.567807, 0.769333, 1.04329", \ - "0.0384007, 0.263971, 0.380407, 0.535175, 0.740518, 1.00818, 1.36794" \ + "0.0383988, 0.179366, 0.241125, 0.322444, 0.43465, 0.590264, 0.813122", \ + "0.0383998, 0.223518, 0.308608, 0.420663, 0.567807, 0.769333, 1.04329", \ + "0.0384008, 0.263971, 0.380407, 0.535175, 0.740518, 1.00818, 1.36794" \ ); } fall_transition (TIMING_DELAY_7x7ds1) { index_1 ("0.0186, 0.0966, 0.174, 0.3294, 0.6408, 1.263, 2.5074"); index_2 ("0.001, 0.0234, 0.039, 0.0648, 0.108, 0.18, 0.3"); values ( \ - "0.00940841, 0.0556816, 0.0895366, 0.1452, 0.239049, 0.395302, 0.655504", \ - "0.0221731, 0.0723021, 0.102441, 0.15321, 0.242073, 0.396416, 0.655612", \ - "0.03173, 0.0898626, 0.121268, 0.171378, 0.256151, 0.402955, 0.658646", \ - "0.0474258, 0.12064, 0.155933, 0.209587, 0.29366, 0.432663, 0.674208", \ - "0.0744143, 0.172822, 0.214722, 0.275789, 0.368325, 0.510718, 0.740777", \ - "0.1202, 0.256379, 0.314157, 0.387838, 0.497418, 0.654155, 0.898387", \ - "0.200576, 0.388352, 0.470357, 0.576129, 0.710848, 0.898935, 1.1723" \ + "0.00940688, 0.0556813, 0.0895713, 0.14532, 0.238949, 0.395326, 0.655504", \ + "0.0221731, 0.0723021, 0.102421, 0.153211, 0.242032, 0.397855, 0.655612", \ + "0.03173, 0.0898627, 0.121268, 0.171378, 0.256151, 0.402955, 0.659068", \ + "0.0474258, 0.12064, 0.155933, 0.209587, 0.29366, 0.432663, 0.674209", \ + "0.0744143, 0.172822, 0.214722, 0.27579, 0.368326, 0.510716, 0.740635", \ + "0.1202, 0.256378, 0.314158, 0.387839, 0.497418, 0.654156, 0.898386", \ + "0.200575, 0.388351, 0.470357, 0.576129, 0.710848, 0.898936, 1.1723" \ ); } } @@ -2037,51 +2037,51 @@ library (sg13g2_stdcell_typ_1p50V_25C) { index_1 ("0.0186, 0.0966, 0.174, 0.3294, 0.6408, 1.263, 2.5074"); index_2 ("0.001, 0.0234, 0.039, 0.0648, 0.108, 0.18, 0.3"); values ( \ - "0.0210329, 0.0897864, 0.136679, 0.212943, 0.341069, 0.554575, 0.910382", \ - "0.0357202, 0.122931, 0.170544, 0.247328, 0.375571, 0.589194, 0.9451", \ - "0.0447354, 0.149528, 0.202285, 0.28192, 0.410423, 0.623789, 0.979793", \ - "0.056278, 0.188157, 0.251825, 0.342574, 0.478734, 0.69419, 1.04963", \ - "0.0740557, 0.242241, 0.323441, 0.434801, 0.594108, 0.827875, 1.19082", \ - "0.100127, 0.314801, 0.419239, 0.563565, 0.762079, 1.04374, 1.44777", \ - "0.139494, 0.417871, 0.549478, 0.734426, 0.994772, 1.35047, 1.847" \ + "0.0210338, 0.089779, 0.13623, 0.212891, 0.34107, 0.554576, 0.910734", \ + "0.0357201, 0.122931, 0.170543, 0.247329, 0.37563, 0.589086, 0.945072", \ + "0.0447353, 0.149528, 0.202285, 0.28192, 0.410422, 0.623766, 0.979766", \ + "0.0562779, 0.188157, 0.251824, 0.342574, 0.47873, 0.694188, 1.04963", \ + "0.0740556, 0.242241, 0.323441, 0.4348, 0.594108, 0.828021, 1.19086", \ + "0.100126, 0.3148, 0.419239, 0.563564, 0.762084, 1.04374, 1.44777", \ + "0.139494, 0.417871, 0.549477, 0.734426, 0.994772, 1.35047, 1.84691" \ ); } rise_transition (TIMING_DELAY_7x7ds1) { index_1 ("0.0186, 0.0966, 0.174, 0.3294, 0.6408, 1.263, 2.5074"); index_2 ("0.001, 0.0234, 0.039, 0.0648, 0.108, 0.18, 0.3"); values ( \ - "0.016356, 0.111852, 0.180125, 0.291719, 0.479398, 0.792189, 1.31326", \ - "0.0304794, 0.120943, 0.184011, 0.292712, 0.479399, 0.792345, 1.31329", \ - "0.0406877, 0.138412, 0.198469, 0.301635, 0.482253, 0.7935, 1.31393", \ - "0.055267, 0.172018, 0.234085, 0.333593, 0.504083, 0.801622, 1.31439", \ - "0.081661, 0.225789, 0.297897, 0.404269, 0.571103, 0.852623, 1.3419", \ - "0.12681, 0.307506, 0.398412, 0.52414, 0.708175, 0.989906, 1.45511", \ - "0.207104, 0.433092, 0.547792, 0.709746, 0.934011, 1.25524, 1.73439" \ + "0.0163568, 0.111842, 0.179614, 0.291653, 0.479397, 0.792188, 1.31358", \ + "0.0304794, 0.120942, 0.18401, 0.292712, 0.479699, 0.79227, 1.31359", \ + "0.0406876, 0.138412, 0.198469, 0.301634, 0.482253, 0.796749, 1.31395", \ + "0.055267, 0.172018, 0.234084, 0.333593, 0.504015, 0.801625, 1.31439", \ + "0.0816609, 0.225789, 0.297897, 0.404269, 0.571102, 0.852758, 1.34135", \ + "0.12681, 0.307505, 0.398412, 0.52414, 0.708008, 0.989903, 1.4551", \ + "0.207155, 0.433095, 0.547792, 0.709746, 0.93401, 1.25524, 1.73434" \ ); } cell_fall (TIMING_DELAY_7x7ds1) { index_1 ("0.0186, 0.0966, 0.174, 0.3294, 0.6408, 1.263, 2.5074"); index_2 ("0.001, 0.0234, 0.039, 0.0648, 0.108, 0.18, 0.3"); values ( \ - "0.0158928, 0.0549222, 0.0799316, 0.121205, 0.190321, 0.305376, 0.497326", \ - "0.0266777, 0.088457, 0.11839, 0.162379, 0.232161, 0.347289, 0.539009", \ - "0.0320674, 0.110097, 0.145971, 0.196634, 0.271725, 0.389083, 0.581127", \ + "0.0158957, 0.0549214, 0.0799251, 0.121226, 0.190322, 0.305379, 0.497331", \ + "0.0266777, 0.0884593, 0.11839, 0.162366, 0.232165, 0.347293, 0.539042", \ + "0.0320674, 0.110097, 0.145975, 0.196634, 0.271725, 0.389083, 0.581128", \ "0.037772, 0.140494, 0.186002, 0.248527, 0.337193, 0.465777, 0.66311", \ "0.0429823, 0.180885, 0.241723, 0.322776, 0.434878, 0.590159, 0.812948", \ - "0.044341, 0.229037, 0.312619, 0.423177, 0.569188, 0.769806, 1.04361", \ - "0.044342, 0.280179, 0.392927, 0.54497, 0.746707, 1.01167, 1.37054" \ + "0.0443411, 0.229037, 0.312619, 0.423177, 0.569188, 0.769806, 1.04361", \ + "0.0443421, 0.280179, 0.392927, 0.54497, 0.746707, 1.01167, 1.37054" \ ); } fall_transition (TIMING_DELAY_7x7ds1) { index_1 ("0.0186, 0.0966, 0.174, 0.3294, 0.6408, 1.263, 2.5074"); index_2 ("0.001, 0.0234, 0.039, 0.0648, 0.108, 0.18, 0.3"); values ( \ - "0.00952677, 0.0557094, 0.0894604, 0.145299, 0.239008, 0.395317, 0.655501", \ - "0.0223697, 0.0724738, 0.102558, 0.153361, 0.242042, 0.396439, 0.655589", \ - "0.0317442, 0.0899949, 0.121423, 0.171616, 0.25602, 0.403021, 0.658674", \ - "0.0469768, 0.120349, 0.155676, 0.209558, 0.293775, 0.432875, 0.673865", \ - "0.0728638, 0.171993, 0.214042, 0.275976, 0.367694, 0.510773, 0.740775", \ - "0.117598, 0.253828, 0.311876, 0.386231, 0.496304, 0.653298, 0.896654", \ + "0.00952514, 0.055721, 0.0895086, 0.145308, 0.239009, 0.395317, 0.655501", \ + "0.0223697, 0.0724512, 0.102558, 0.153269, 0.242094, 0.395827, 0.655615", \ + "0.0317442, 0.0899949, 0.121415, 0.171617, 0.256022, 0.403021, 0.658674", \ + "0.0469768, 0.120349, 0.155676, 0.209558, 0.293775, 0.432875, 0.673866", \ + "0.0728637, 0.171993, 0.214043, 0.275976, 0.367694, 0.510773, 0.740775", \ + "0.117598, 0.253828, 0.311876, 0.386231, 0.496305, 0.653299, 0.896654", \ "0.19638, 0.383063, 0.464898, 0.570559, 0.705134, 0.894902, 1.16958" \ ); } @@ -2094,52 +2094,52 @@ library (sg13g2_stdcell_typ_1p50V_25C) { index_1 ("0.0186, 0.0966, 0.174, 0.3294, 0.6408, 1.263, 2.5074"); index_2 ("0.001, 0.0234, 0.039, 0.0648, 0.108, 0.18, 0.3"); values ( \ - "0.0320305, 0.124882, 0.187812, 0.291471, 0.464979, 0.753744, 1.23524", \ - "0.0519236, 0.155748, 0.218864, 0.322562, 0.496054, 0.7851, 1.26651", \ - "0.0648862, 0.183995, 0.250235, 0.354746, 0.527918, 0.816649, 1.29792", \ - "0.0820272, 0.227691, 0.303423, 0.416077, 0.59269, 0.88109, 1.36186", \ - "0.109634, 0.291409, 0.383723, 0.516772, 0.711472, 1.01071, 1.49224", \ - "0.152147, 0.379779, 0.496596, 0.661263, 0.896737, 1.23678, 1.74667", \ - "0.219046, 0.507489, 0.654074, 0.863179, 1.15959, 1.57393, 2.17085" \ + "0.0320282, 0.124885, 0.187753, 0.291469, 0.464979, 0.753745, 1.23546", \ + "0.0519239, 0.155739, 0.218858, 0.322589, 0.49607, 0.785103, 1.2665", \ + "0.0648862, 0.183995, 0.250234, 0.354746, 0.527948, 0.816649, 1.29792", \ + "0.0820272, 0.227691, 0.303425, 0.416081, 0.59269, 0.881092, 1.36185", \ + "0.109634, 0.291409, 0.383723, 0.516772, 0.711471, 1.01072, 1.49254", \ + "0.152147, 0.379791, 0.496596, 0.661262, 0.896736, 1.23678, 1.74666", \ + "0.219046, 0.507488, 0.654074, 0.863178, 1.15958, 1.57392, 2.17085" \ ); } rise_transition (TIMING_DELAY_7x7ds1) { index_1 ("0.0186, 0.0966, 0.174, 0.3294, 0.6408, 1.263, 2.5074"); index_2 ("0.001, 0.0234, 0.039, 0.0648, 0.108, 0.18, 0.3"); values ( \ - "0.0274188, 0.157514, 0.24791, 0.397601, 0.648307, 1.06583, 1.76213", \ - "0.0412829, 0.162494, 0.249629, 0.397655, 0.648308, 1.06587, 1.76214", \ - "0.051306, 0.177247, 0.259993, 0.402568, 0.649289, 1.06588, 1.76215", \ - "0.0677487, 0.209878, 0.291762, 0.427302, 0.662393, 1.07092, 1.76709", \ - "0.0951774, 0.265, 0.355044, 0.49252, 0.718243, 1.10421, 1.77534", \ - "0.141922, 0.348558, 0.45642, 0.612166, 0.847736, 1.22337, 1.85906", \ - "0.224098, 0.479186, 0.611781, 0.801254, 1.07621, 1.48019, 2.11204" \ + "0.0274182, 0.157513, 0.247891, 0.397601, 0.648306, 1.06583, 1.76194", \ + "0.041283, 0.162484, 0.249659, 0.397662, 0.648307, 1.06588, 1.76195", \ + "0.051306, 0.177247, 0.259993, 0.402568, 0.650541, 1.06589, 1.76196", \ + "0.0677487, 0.209878, 0.291764, 0.427312, 0.662393, 1.07092, 1.76214", \ + "0.0951773, 0.264999, 0.355044, 0.492519, 0.71812, 1.10428, 1.77533", \ + "0.141923, 0.348568, 0.45642, 0.612165, 0.847735, 1.22337, 1.85906", \ + "0.224097, 0.479185, 0.61178, 0.801253, 1.07621, 1.48017, 2.11204" \ ); } cell_fall (TIMING_DELAY_7x7ds1) { index_1 ("0.0186, 0.0966, 0.174, 0.3294, 0.6408, 1.263, 2.5074"); index_2 ("0.001, 0.0234, 0.039, 0.0648, 0.108, 0.18, 0.3"); values ( \ - "0.0164708, 0.0555555, 0.0806972, 0.122174, 0.191636, 0.307011, 0.498967", \ - "0.0278204, 0.0894146, 0.119386, 0.163368, 0.233562, 0.348946, 0.540825", \ - "0.033246, 0.111376, 0.147224, 0.197894, 0.273209, 0.390831, 0.582843", \ - "0.0389858, 0.141933, 0.187567, 0.250146, 0.338928, 0.46756, 0.664915", \ + "0.0164709, 0.055548, 0.0806969, 0.122201, 0.19164, 0.307014, 0.499114", \ + "0.0278215, 0.0894147, 0.119393, 0.163362, 0.233572, 0.348978, 0.540844", \ + "0.033246, 0.111376, 0.147224, 0.197894, 0.273209, 0.390831, 0.582845", \ + "0.0389858, 0.141933, 0.187567, 0.250146, 0.338928, 0.46756, 0.664911", \ "0.0439675, 0.182122, 0.243393, 0.324765, 0.436764, 0.592237, 0.814809", \ - "0.0461151, 0.228899, 0.313086, 0.424132, 0.570922, 0.771679, 1.04546", \ - "0.0461161, 0.273405, 0.387859, 0.54095, 0.744571, 1.01126, 1.37058" \ + "0.0461149, 0.228899, 0.313086, 0.424132, 0.570922, 0.771679, 1.04546", \ + "0.0461159, 0.273405, 0.387859, 0.54095, 0.744571, 1.01126, 1.37058" \ ); } fall_transition (TIMING_DELAY_7x7ds1) { index_1 ("0.0186, 0.0966, 0.174, 0.3294, 0.6408, 1.263, 2.5074"); index_2 ("0.001, 0.0234, 0.039, 0.0648, 0.108, 0.18, 0.3"); values ( \ - "0.0130016, 0.0594616, 0.0932205, 0.148962, 0.242661, 0.398936, 0.659438", \ - "0.029928, 0.0763153, 0.106178, 0.156984, 0.245663, 0.399352, 0.659439", \ - "0.0422866, 0.0944419, 0.125369, 0.175206, 0.259712, 0.406648, 0.661791", \ - "0.0622031, 0.126235, 0.160472, 0.213727, 0.297551, 0.436466, 0.677499", \ - "0.0952629, 0.179917, 0.221351, 0.281218, 0.37307, 0.514319, 0.744321", \ - "0.149335, 0.266685, 0.321766, 0.394471, 0.501644, 0.65818, 0.90088", \ - "0.241054, 0.404602, 0.481939, 0.583941, 0.716833, 0.906121, 1.17636" \ + "0.0130016, 0.0594771, 0.0932205, 0.148934, 0.242661, 0.398947, 0.659309", \ + "0.0299207, 0.0763154, 0.106181, 0.156961, 0.245818, 0.399439, 0.65931", \ + "0.0422867, 0.094442, 0.125369, 0.175206, 0.259712, 0.406648, 0.661207", \ + "0.0622031, 0.126235, 0.160472, 0.213728, 0.297552, 0.436468, 0.677474", \ + "0.095263, 0.179917, 0.221351, 0.281218, 0.37307, 0.514319, 0.744321", \ + "0.149335, 0.266685, 0.321766, 0.394472, 0.501644, 0.658181, 0.90088", \ + "0.241054, 0.404602, 0.481938, 0.583941, 0.716834, 0.906121, 1.17636" \ ); } } @@ -2149,26 +2149,26 @@ library (sg13g2_stdcell_typ_1p50V_25C) { index_1 ("0.0186, 0.0966, 0.174, 0.3294, 0.6408, 1.263, 2.5074"); index_2 ("0.001, 0.0234, 0.039, 0.0648, 0.108, 0.18, 0.3"); values ( \ - "0.00688061, 0.00747741, 0.00745273, 0.00739352, 0.00721737, 0.0068913, 0.00648462", \ - "0.00665082, 0.00706048, 0.00718485, 0.0071737, 0.0070851, 0.00678618, 0.00646955", \ - "0.00715411, 0.00704117, 0.00713045, 0.00712435, 0.00737082, 0.00679657, 0.00642649", \ - "0.00896039, 0.00776502, 0.00753912, 0.00757171, 0.00729983, 0.00684659, 0.00681329", \ - "0.0137785, 0.0106774, 0.00991464, 0.00916562, 0.00858167, 0.00761212, 0.00757793", \ - "0.0241955, 0.0184514, 0.0167663, 0.0150321, 0.013056, 0.0110151, 0.0105797", \ - "0.0456376, 0.0371724, 0.0337746, 0.030062, 0.0260782, 0.0218705, 0.0178631" \ + "0.00688322, 0.00747694, 0.00745249, 0.00739114, 0.00721766, 0.00689702, 0.00648494", \ + "0.00665221, 0.00706602, 0.00715802, 0.00718193, 0.00706425, 0.00678689, 0.00646934", \ + "0.00715367, 0.00704207, 0.00717196, 0.00712427, 0.00737156, 0.0067965, 0.00642592", \ + "0.00896037, 0.0077671, 0.0075387, 0.00752055, 0.00720234, 0.00684667, 0.00681284", \ + "0.0137783, 0.010678, 0.00991459, 0.00916562, 0.00857607, 0.00761204, 0.00845965", \ + "0.0241954, 0.0184507, 0.0167649, 0.0150329, 0.0131077, 0.0110208, 0.0105827", \ + "0.0456341, 0.037171, 0.0337744, 0.0300622, 0.0260794, 0.0218682, 0.017973" \ ); } fall_power (POWER_7x7ds1) { index_1 ("0.0186, 0.0966, 0.174, 0.3294, 0.6408, 1.263, 2.5074"); index_2 ("0.001, 0.0234, 0.039, 0.0648, 0.108, 0.18, 0.3"); values ( \ - "0.00479582, 0.00492474, 0.00488899, 0.0047894, 0.00463068, 0.00435976, 0.00380108", \ - "0.00485968, 0.00480786, 0.00493563, 0.00488271, 0.00454022, 0.00425215, 0.00373758", \ - "0.00563615, 0.00509022, 0.00495189, 0.0050058, 0.00460684, 0.00461315, 0.00369168", \ - "0.00773831, 0.00618642, 0.00581946, 0.00544176, 0.00516801, 0.0046138, 0.00457099", \ - "0.0123381, 0.0091608, 0.00835291, 0.00757304, 0.00664602, 0.00568977, 0.00542022", \ - "0.022407, 0.0170746, 0.0152043, 0.0131942, 0.0112617, 0.00947822, 0.00701353", \ - "0.0432172, 0.0356021, 0.0321846, 0.0281543, 0.0237114, 0.0195088, 0.0158208" \ + "0.00479333, 0.00493019, 0.00488253, 0.00478833, 0.00462919, 0.00435915, 0.00380174", \ + "0.00486145, 0.00480478, 0.00488146, 0.00488277, 0.00453836, 0.00422629, 0.00373836", \ + "0.00563638, 0.0050902, 0.00493313, 0.0050058, 0.00460684, 0.00461049, 0.00369664", \ + "0.00774004, 0.00618563, 0.00581632, 0.00544176, 0.00516801, 0.0046138, 0.00458921", \ + "0.0123415, 0.00916068, 0.00834999, 0.00757527, 0.00664594, 0.00568977, 0.00532255", \ + "0.0224074, 0.0170749, 0.0152046, 0.0131938, 0.0112553, 0.0094542, 0.0070865", \ + "0.0432174, 0.0356016, 0.0321846, 0.0281545, 0.0237114, 0.0195089, 0.0158209" \ ); } } @@ -2178,26 +2178,26 @@ library (sg13g2_stdcell_typ_1p50V_25C) { index_1 ("0.0186, 0.0966, 0.174, 0.3294, 0.6408, 1.263, 2.5074"); index_2 ("0.001, 0.0234, 0.039, 0.0648, 0.108, 0.18, 0.3"); values ( \ - "0.00731976, 0.00741699, 0.00736115, 0.00726805, 0.00710113, 0.00680422, 0.0063442", \ - "0.00713032, 0.00725873, 0.00725062, 0.00715613, 0.00700095, 0.00670129, 0.00628255", \ - "0.00752852, 0.00732059, 0.00735345, 0.00724214, 0.00702532, 0.00670895, 0.00632869", \ - "0.00920586, 0.00811228, 0.00784183, 0.00779206, 0.00729467, 0.00683456, 0.00666307", \ - "0.0138807, 0.0111345, 0.0103249, 0.0095031, 0.00881029, 0.00774399, 0.00856199", \ - "0.024081, 0.0191691, 0.0173653, 0.0156469, 0.0135481, 0.0114, 0.0107774", \ - "0.0451111, 0.03813, 0.0350352, 0.0313737, 0.02729, 0.0228593, 0.0186013" \ + "0.00732136, 0.0074169, 0.00736645, 0.00727172, 0.00710352, 0.00677602, 0.0063535", \ + "0.00713028, 0.00726873, 0.0072506, 0.00715956, 0.00698286, 0.00668253, 0.00628349", \ + "0.00752856, 0.00732058, 0.00731431, 0.00724214, 0.00719652, 0.00672288, 0.00632882", \ + "0.00920605, 0.00810771, 0.00782216, 0.0077916, 0.00741757, 0.00683466, 0.00669449", \ + "0.0138793, 0.0111353, 0.0103266, 0.0095031, 0.00881257, 0.00773951, 0.00767057", \ + "0.0240809, 0.0191691, 0.0173663, 0.0156469, 0.0135481, 0.0113515, 0.0104383", \ + "0.0451115, 0.0381319, 0.0350359, 0.0313738, 0.0272898, 0.0228588, 0.0186017" \ ); } fall_power (POWER_7x7ds1) { index_1 ("0.0186, 0.0966, 0.174, 0.3294, 0.6408, 1.263, 2.5074"); index_2 ("0.001, 0.0234, 0.039, 0.0648, 0.108, 0.18, 0.3"); values ( \ - "0.00744661, 0.00749089, 0.00745694, 0.00733543, 0.00720759, 0.0068718, 0.00634865", \ - "0.0072234, 0.00733554, 0.0074736, 0.00729034, 0.00713508, 0.00682635, 0.00634172", \ - "0.00768523, 0.00752343, 0.007388, 0.00750339, 0.00714402, 0.00688475, 0.00630687", \ - "0.00933675, 0.00828687, 0.00810426, 0.00780502, 0.00762757, 0.00703337, 0.0065321", \ - "0.0137342, 0.0109527, 0.0102553, 0.009589, 0.00890295, 0.00799238, 0.00768618", \ - "0.023537, 0.0184171, 0.0166894, 0.0148615, 0.0131694, 0.0117309, 0.00942695", \ - "0.0438062, 0.036365, 0.0330963, 0.0292603, 0.0250126, 0.0211873, 0.017735" \ + "0.00744743, 0.00749183, 0.00745745, 0.00736031, 0.00720792, 0.00690705, 0.00634767", \ + "0.00722341, 0.00732878, 0.00737604, 0.00736284, 0.0070985, 0.00682662, 0.00633971", \ + "0.00768585, 0.00752343, 0.00738846, 0.0075043, 0.00714599, 0.00688467, 0.00631725", \ + "0.00933923, 0.00828179, 0.00810406, 0.00780502, 0.00762757, 0.00703336, 0.00673838", \ + "0.013734, 0.0109538, 0.0102518, 0.0095891, 0.00890296, 0.00798629, 0.00760287", \ + "0.023537, 0.0184169, 0.0166893, 0.0148615, 0.0131694, 0.0117316, 0.00942003", \ + "0.04381, 0.036365, 0.0330961, 0.0292603, 0.0250138, 0.0211917, 0.017735" \ ); } } @@ -2208,26 +2208,26 @@ library (sg13g2_stdcell_typ_1p50V_25C) { index_1 ("0.0186, 0.0966, 0.174, 0.3294, 0.6408, 1.263, 2.5074"); index_2 ("0.001, 0.0234, 0.039, 0.0648, 0.108, 0.18, 0.3"); values ( \ - "0.00379004, 0.0043034, 0.0043095, 0.00426158, 0.00412406, 0.00381497, 0.00327872", \ - "0.00425026, 0.00413082, 0.00408541, 0.00405887, 0.0039734, 0.00371768, 0.00330671", \ - "0.00526384, 0.00446066, 0.00436906, 0.0043121, 0.00403239, 0.00369565, 0.00327279", \ - "0.00765483, 0.00592904, 0.00539618, 0.00506882, 0.00448669, 0.0040658, 0.00404452", \ - "0.0130112, 0.00984309, 0.00887605, 0.0077532, 0.00671519, 0.00539778, 0.00570944", \ - "0.0236667, 0.0182688, 0.0164536, 0.0144524, 0.0122317, 0.00971716, 0.00879546", \ - "0.0462712, 0.0380082, 0.0345653, 0.0309456, 0.0269547, 0.0224139, 0.0178539" \ + "0.00379065, 0.00431083, 0.0043148, 0.00426016, 0.00412276, 0.00381489, 0.00332409", \ + "0.0042521, 0.00412169, 0.0040804, 0.00406538, 0.00397715, 0.00371909, 0.00330589", \ + "0.00526369, 0.00446066, 0.00436878, 0.00430772, 0.00412342, 0.00369558, 0.00327272", \ + "0.00765556, 0.00592898, 0.00539617, 0.00504061, 0.0044886, 0.00406594, 0.00348808", \ + "0.0130106, 0.00984329, 0.00887585, 0.0077532, 0.00674079, 0.00540708, 0.00436397", \ + "0.0236674, 0.0182697, 0.0164539, 0.0144524, 0.0122318, 0.00972091, 0.00879576", \ + "0.0462721, 0.0380078, 0.0345654, 0.0309498, 0.0269547, 0.0224002, 0.017854" \ ); } fall_power (POWER_7x7ds1) { index_1 ("0.0186, 0.0966, 0.174, 0.3294, 0.6408, 1.263, 2.5074"); index_2 ("0.001, 0.0234, 0.039, 0.0648, 0.108, 0.18, 0.3"); values ( \ - "0.00547474, 0.00613033, 0.00618033, 0.00608052, 0.00595051, 0.00569022, 0.00524436", \ - "0.0057944, 0.00603746, 0.00603742, 0.00621526, 0.0059332, 0.00570611, 0.00523239", \ - "0.00679463, 0.00631732, 0.00631478, 0.00611494, 0.00621702, 0.00596113, 0.00539588", \ - "0.00909442, 0.00726312, 0.00705015, 0.00684113, 0.00638855, 0.00616567, 0.00577491", \ - "0.0142737, 0.0105006, 0.00955388, 0.00888184, 0.00826833, 0.0073601, 0.00600514", \ - "0.0248793, 0.0187702, 0.0166583, 0.0146483, 0.0128597, 0.0111025, 0.00954446", \ - "0.0467965, 0.0379482, 0.0343479, 0.0300609, 0.0258266, 0.0213755, 0.0174744" \ + "0.00547475, 0.00613465, 0.00618033, 0.00607734, 0.00595195, 0.00566999, 0.00529946", \ + "0.00579854, 0.00603739, 0.00602873, 0.00621608, 0.00595368, 0.00571206, 0.00526159", \ + "0.00679428, 0.00631733, 0.00631479, 0.00611624, 0.00621618, 0.00596136, 0.00531595", \ + "0.00909445, 0.00726316, 0.00705258, 0.00686167, 0.00638498, 0.00610394, 0.00551815", \ + "0.0142737, 0.010501, 0.0095538, 0.00888177, 0.00826833, 0.00735987, 0.00600476", \ + "0.0248827, 0.0187712, 0.016658, 0.0146487, 0.0128597, 0.0111025, 0.00954424", \ + "0.0467997, 0.0379483, 0.0343483, 0.0300609, 0.0258279, 0.0213755, 0.0174743" \ ); } } @@ -2238,26 +2238,26 @@ library (sg13g2_stdcell_typ_1p50V_25C) { index_1 ("0.0186, 0.0966, 0.174, 0.3294, 0.6408, 1.263, 2.5074"); index_2 ("0.001, 0.0234, 0.039, 0.0648, 0.108, 0.18, 0.3"); values ( \ - "0.00327696, 0.00392253, 0.00395113, 0.00390962, 0.0037646, 0.00344651, 0.00293977", \ - "0.00398395, 0.0037902, 0.0037512, 0.00386002, 0.00361268, 0.003333, 0.00294269", \ - "0.00510657, 0.00411727, 0.00408199, 0.00390067, 0.00380525, 0.00330509, 0.00297202", \ - "0.00767825, 0.00562015, 0.00508436, 0.00481597, 0.00412861, 0.00367437, 0.00332371", \ - "0.013248, 0.0096447, 0.00857296, 0.00743165, 0.00642712, 0.00508548, 0.00553087", \ - "0.0241681, 0.018241, 0.0163288, 0.0141979, 0.0119969, 0.00948287, 0.00841882", \ - "0.0469978, 0.038177, 0.0347208, 0.0310677, 0.0267822, 0.0221545, 0.0174549" \ + "0.00327697, 0.00392948, 0.00394971, 0.00391163, 0.00376449, 0.00345558, 0.00299147", \ + "0.00398304, 0.00377044, 0.00371764, 0.00370314, 0.00360664, 0.00332341, 0.00294487", \ + "0.00510663, 0.00411524, 0.00400919, 0.00389477, 0.00383628, 0.00382043, 0.00299825", \ + "0.0076795, 0.00563076, 0.00507649, 0.00480344, 0.00425509, 0.00367146, 0.00331996", \ + "0.0132488, 0.00964456, 0.00855976, 0.00740429, 0.00642636, 0.00508616, 0.00553095", \ + "0.0241693, 0.0182415, 0.016329, 0.0141984, 0.0119998, 0.00940286, 0.00828509", \ + "0.0469987, 0.0381772, 0.0347203, 0.0310677, 0.0267823, 0.0221917, 0.0174522" \ ); } fall_power (POWER_7x7ds1) { index_1 ("0.0186, 0.0966, 0.174, 0.3294, 0.6408, 1.263, 2.5074"); index_2 ("0.001, 0.0234, 0.039, 0.0648, 0.108, 0.18, 0.3"); values ( \ - "0.00281729, 0.00348822, 0.00355025, 0.00342192, 0.00331582, 0.00305579, 0.00259483", \ - "0.00315758, 0.00341471, 0.00339584, 0.00351646, 0.00339972, 0.00323627, 0.00261889", \ - "0.00417456, 0.00367191, 0.00366658, 0.00348768, 0.00355478, 0.00342134, 0.00298478", \ - "0.00653318, 0.00463783, 0.00446672, 0.0042234, 0.00383818, 0.0035244, 0.0030907", \ - "0.0118106, 0.00791947, 0.00698922, 0.0062061, 0.00558754, 0.00485969, 0.00350601", \ - "0.0225336, 0.0162192, 0.0140936, 0.012059, 0.0103226, 0.00858558, 0.00705783", \ - "0.0446235, 0.0354645, 0.0319659, 0.0276253, 0.0233837, 0.0188089, 0.0149852" \ + "0.00281718, 0.00348803, 0.00355757, 0.00344277, 0.00327325, 0.0030488, 0.00259234", \ + "0.00315731, 0.00341464, 0.00340923, 0.00351718, 0.00329106, 0.0035982, 0.0026115", \ + "0.00417522, 0.00367191, 0.00366657, 0.00348768, 0.00355478, 0.00342127, 0.003088", \ + "0.0065333, 0.00463782, 0.00446672, 0.00422992, 0.00383788, 0.00352417, 0.0030907", \ + "0.0118106, 0.00791946, 0.00698922, 0.00620618, 0.00559999, 0.00485924, 0.0034183", \ + "0.0225323, 0.0162192, 0.0140932, 0.0120586, 0.0103226, 0.00858613, 0.00706023", \ + "0.0446224, 0.0354646, 0.031966, 0.0276253, 0.0233837, 0.0188052, 0.0149852" \ ); } } @@ -2268,26 +2268,26 @@ library (sg13g2_stdcell_typ_1p50V_25C) { index_1 ("0.0186, 0.0966, 0.174, 0.3294, 0.6408, 1.263, 2.5074"); index_2 ("0.001, 0.0234, 0.039, 0.0648, 0.108, 0.18, 0.3"); values ( \ - "0.00329375, 0.00392388, 0.00403434, 0.00390155, 0.00376322, 0.0034257, 0.00333679", \ - "0.00409517, 0.00380196, 0.0037292, 0.00373693, 0.00364149, 0.003389, 0.00318487", \ - "0.00533245, 0.0042213, 0.0040971, 0.0038736, 0.00396938, 0.00355013, 0.00340713", \ - "0.00812757, 0.00591182, 0.00535517, 0.0048336, 0.00470738, 0.00376222, 0.0034537", \ - "0.0139543, 0.0102667, 0.00914343, 0.0079924, 0.00665034, 0.00601503, 0.00477814", \ - "0.0259157, 0.019632, 0.0176482, 0.0153519, 0.0129246, 0.0104107, 0.00802738", \ - "0.0504567, 0.041258, 0.0375768, 0.0334341, 0.0289979, 0.0241823, 0.0191509" \ + "0.00329539, 0.00392047, 0.00394808, 0.00390795, 0.00376384, 0.00342596, 0.00335756", \ + "0.00409528, 0.00380189, 0.00372683, 0.00374907, 0.00368915, 0.00338139, 0.00316072", \ + "0.00533304, 0.00422221, 0.00409712, 0.00387475, 0.00396976, 0.00399, 0.00337113", \ + "0.00812787, 0.00591179, 0.00535509, 0.0048336, 0.00443746, 0.003762, 0.00345385", \ + "0.0139542, 0.0102672, 0.00914361, 0.00798847, 0.00664795, 0.00610437, 0.00459895", \ + "0.0259141, 0.0196319, 0.0176479, 0.0153515, 0.0129113, 0.0104403, 0.00798257", \ + "0.0504034, 0.0412584, 0.0375767, 0.0334335, 0.0289974, 0.0241821, 0.0190423" \ ); } fall_power (POWER_7x7ds1) { index_1 ("0.0186, 0.0966, 0.174, 0.3294, 0.6408, 1.263, 2.5074"); index_2 ("0.001, 0.0234, 0.039, 0.0648, 0.108, 0.18, 0.3"); values ( \ - "0.00266343, 0.00336287, 0.00339866, 0.00331331, 0.0031728, 0.00291146, 0.00247964", \ - "0.00312682, 0.00323082, 0.00321909, 0.00339018, 0.00309256, 0.00307281, 0.00244826", \ - "0.00424982, 0.0035125, 0.00350195, 0.00335291, 0.00335814, 0.00309558, 0.002822", \ - "0.00685554, 0.0046462, 0.00437368, 0.00411763, 0.00366413, 0.00333777, 0.00308292", \ - "0.0124529, 0.00826977, 0.007207, 0.00638528, 0.00559157, 0.004793, 0.00337626", \ - "0.0241159, 0.0173127, 0.0150116, 0.0127949, 0.0107947, 0.00882291, 0.00716085", \ - "0.0478429, 0.0381988, 0.034223, 0.0296069, 0.0249352, 0.02009, 0.0157836" \ + "0.00266505, 0.00338544, 0.00341212, 0.00330357, 0.0031783, 0.00291573, 0.00248218", \ + "0.00312631, 0.0032134, 0.00321907, 0.00333264, 0.00316104, 0.00290838, 0.0024559", \ + "0.00425005, 0.00351252, 0.0035015, 0.00336569, 0.00335099, 0.00309566, 0.002822", \ + "0.00685569, 0.00464657, 0.00437368, 0.00411891, 0.00370806, 0.0033128, 0.00308577", \ + "0.0124529, 0.00826977, 0.00720689, 0.00638586, 0.00558414, 0.00479293, 0.00337536", \ + "0.0241156, 0.0173124, 0.0150122, 0.0127949, 0.0107953, 0.00882474, 0.00716085", \ + "0.0478437, 0.0381988, 0.0342231, 0.0296057, 0.0249352, 0.0200872, 0.0157835" \ ); } } @@ -2297,26 +2297,26 @@ library (sg13g2_stdcell_typ_1p50V_25C) { index_1 ("0.0186, 0.0966, 0.174, 0.3294, 0.6408, 1.263, 2.5074"); index_2 ("0.001, 0.0234, 0.039, 0.0648, 0.108, 0.18, 0.3"); values ( \ - "0.00379004, 0.0043034, 0.0043095, 0.00426158, 0.00412406, 0.00381497, 0.00327872", \ - "0.00425026, 0.00413082, 0.00408541, 0.00405887, 0.0039734, 0.00371768, 0.00330671", \ - "0.00526384, 0.00446066, 0.00436906, 0.0043121, 0.00403239, 0.00369565, 0.00327279", \ - "0.00765483, 0.00592904, 0.00539618, 0.00506882, 0.00448669, 0.0040658, 0.00404452", \ - "0.0130112, 0.00984309, 0.00887605, 0.0077532, 0.00671519, 0.00539778, 0.00570944", \ - "0.0236667, 0.0182688, 0.0164536, 0.0144524, 0.0122317, 0.00971716, 0.00879546", \ - "0.0462712, 0.0380082, 0.0345653, 0.0309456, 0.0269547, 0.0224139, 0.0178539" \ + "0.00379065, 0.00431083, 0.0043148, 0.00426016, 0.00412276, 0.00381489, 0.00332409", \ + "0.0042521, 0.00412169, 0.0040804, 0.00406538, 0.00397715, 0.00371909, 0.00330589", \ + "0.00526369, 0.00446066, 0.00436878, 0.00430772, 0.00412342, 0.00369558, 0.00327272", \ + "0.00765556, 0.00592898, 0.00539617, 0.00504061, 0.0044886, 0.00406594, 0.00348808", \ + "0.0130106, 0.00984329, 0.00887585, 0.0077532, 0.00674079, 0.00540708, 0.00436397", \ + "0.0236674, 0.0182697, 0.0164539, 0.0144524, 0.0122318, 0.00972091, 0.00879576", \ + "0.0462721, 0.0380078, 0.0345654, 0.0309498, 0.0269547, 0.0224002, 0.017854" \ ); } fall_power (POWER_7x7ds1) { index_1 ("0.0186, 0.0966, 0.174, 0.3294, 0.6408, 1.263, 2.5074"); index_2 ("0.001, 0.0234, 0.039, 0.0648, 0.108, 0.18, 0.3"); values ( \ - "0.00266343, 0.00336287, 0.00339866, 0.00331331, 0.0031728, 0.00291146, 0.00247964", \ - "0.00312682, 0.00323082, 0.00321909, 0.00339018, 0.00309256, 0.00307281, 0.00244826", \ - "0.00424982, 0.0035125, 0.00350195, 0.00335291, 0.00335814, 0.00309558, 0.002822", \ - "0.00685554, 0.0046462, 0.00437368, 0.00411763, 0.00366413, 0.00333777, 0.00308292", \ - "0.0124529, 0.00826977, 0.007207, 0.00638528, 0.00559157, 0.004793, 0.00337626", \ - "0.0241159, 0.0173127, 0.0150116, 0.0127949, 0.0107947, 0.00882291, 0.00716085", \ - "0.0478429, 0.0381988, 0.034223, 0.0296069, 0.0249352, 0.02009, 0.0157836" \ + "0.00266505, 0.00338544, 0.00341212, 0.00330357, 0.0031783, 0.00291573, 0.00248218", \ + "0.00312631, 0.0032134, 0.00321907, 0.00333264, 0.00316104, 0.00290838, 0.0024559", \ + "0.00425005, 0.00351252, 0.0035015, 0.00336569, 0.00335099, 0.00309566, 0.002822", \ + "0.00685569, 0.00464657, 0.00437368, 0.00411891, 0.00370806, 0.0033128, 0.00308577", \ + "0.0124529, 0.00826977, 0.00720689, 0.00638586, 0.00558414, 0.00479293, 0.00337536", \ + "0.0241156, 0.0173124, 0.0150122, 0.0127949, 0.0107953, 0.00882474, 0.00716085", \ + "0.0478437, 0.0381988, 0.0342231, 0.0296057, 0.0249352, 0.0200872, 0.0157835" \ ); } } @@ -2324,65 +2324,65 @@ library (sg13g2_stdcell_typ_1p50V_25C) { pin (A1) { direction : "input"; max_transition : 2.5074; - capacitance : 0.00314852; + capacitance : 0.00314851; rise_capacitance : 0.00305485; - rise_capacitance_range (0.00305485, 0.00305485); - fall_capacitance : 0.00324219; - fall_capacitance_range (0.00324219, 0.00324219); + rise_capacitance_range (0.00282276, 0.00341332); + fall_capacitance : 0.00324218; + fall_capacitance_range (0.00274562, 0.00364349); } pin (A2) { direction : "input"; max_transition : 2.5074; - capacitance : 0.00323611; - rise_capacitance : 0.00327929; - rise_capacitance_range (0.00327929, 0.00327929); - fall_capacitance : 0.00319293; - fall_capacitance_range (0.00319293, 0.00319293); + capacitance : 0.0032361; + rise_capacitance : 0.00327928; + rise_capacitance_range (0.00279604, 0.00362246); + fall_capacitance : 0.00319292; + fall_capacitance_range (0.00278758, 0.00348295); } pin (B1) { direction : "input"; max_transition : 2.5074; capacitance : 0.0029789; rise_capacitance : 0.00307828; - rise_capacitance_range (0.00307828, 0.00307828); - fall_capacitance : 0.00287952; - fall_capacitance_range (0.00287952, 0.00287952); + rise_capacitance_range (0.00253815, 0.00402908); + fall_capacitance : 0.00287953; + fall_capacitance_range (0.00266809, 0.00320295); } } cell (sg13g2_a21oi_2) { area : 14.5152; cell_footprint : "a21oi"; - cell_leakage_power : 717.079; + cell_leakage_power : 717.077; leakage_power () { - value : 445.31; + value : 445.308; when : "!A1&!A2&!B1&Y"; } leakage_power () { - value : 718.119; + value : 718.117; when : "!A1&!A2&B1&!Y"; } leakage_power () { - value : 653.357; + value : 653.355; when : "!A1&A2&!B1&Y"; } leakage_power () { - value : 878.566; + value : 878.564; when : "!A1&A2&B1&!Y"; } leakage_power () { - value : 373.634; + value : 373.632; when : "A1&!A2&!B1&Y"; } leakage_power () { - value : 878.565; + value : 878.564; when : "A1&!A2&B1&!Y"; } leakage_power () { - value : 869.53; + value : 869.528; when : "A1&A2&!B1&!Y"; } leakage_power () { - value : 919.553; + value : 919.551; when : "A1&A2&B1&!Y"; } pin (Y) { @@ -2398,52 +2398,52 @@ library (sg13g2_stdcell_typ_1p50V_25C) { index_1 ("0.0186, 0.0966, 0.174, 0.3294, 0.6408, 1.263, 2.5074"); index_2 ("0.001, 0.0468, 0.078, 0.1296, 0.216, 0.36, 0.6"); values ( \ - "0.0302896, 0.125427, 0.188319, 0.292248, 0.46616, 0.756136, 1.23918", \ - "0.0428635, 0.148217, 0.211782, 0.316124, 0.490292, 0.78034, 1.2632", \ - "0.04878, 0.167329, 0.233218, 0.338382, 0.512694, 0.80303, 1.28605", \ - "0.0544891, 0.196545, 0.268938, 0.379735, 0.556931, 0.847393, 1.33026", \ - "0.0641259, 0.240403, 0.325597, 0.449876, 0.63926, 0.936612, 1.42139", \ - "0.07582, 0.300236, 0.405132, 0.554285, 0.770676, 1.09395, 1.59701", \ - "0.086123, 0.38244, 0.512829, 0.697179, 0.959893, 1.34245, 1.89689" \ + "0.030283, 0.125421, 0.188299, 0.292295, 0.466153, 0.75584, 1.23913", \ + "0.0428627, 0.14824, 0.211782, 0.316054, 0.490344, 0.780312, 1.26317", \ + "0.0487792, 0.167327, 0.233248, 0.338376, 0.512657, 0.803023, 1.28603", \ + "0.0544881, 0.196542, 0.268934, 0.379802, 0.556909, 0.847376, 1.33092", \ + "0.0641244, 0.240399, 0.325592, 0.449869, 0.639249, 0.936596, 1.42137", \ + "0.0758175, 0.300231, 0.405126, 0.554276, 0.770665, 1.09393, 1.59698", \ + "0.0861189, 0.382433, 0.51282, 0.697168, 0.959819, 1.34243, 1.89687" \ ); } rise_transition (TIMING_DELAY_7x7ds1) { index_1 ("0.0186, 0.0966, 0.174, 0.3294, 0.6408, 1.263, 2.5074"); index_2 ("0.001, 0.0468, 0.078, 0.1296, 0.216, 0.36, 0.6"); values ( \ - "0.0170971, 0.150332, 0.240933, 0.391257, 0.64294, 1.06252, 1.76121", \ - "0.0272292, 0.153279, 0.242139, 0.392714, 0.642941, 1.06253, 1.76122", \ - "0.0375194, 0.162829, 0.24842, 0.394242, 0.645271, 1.06254, 1.76123", \ - "0.0555918, 0.186113, 0.269625, 0.409853, 0.65156, 1.0646, 1.76124", \ - "0.0864685, 0.2308, 0.316589, 0.45531, 0.687123, 1.08597, 1.76944", \ - "0.134578, 0.304191, 0.399713, 0.546408, 0.78024, 1.16427, 1.822", \ - "0.215574, 0.424539, 0.534677, 0.702629, 0.950557, 1.35372, 1.99183" \ + "0.0170907, 0.150327, 0.240914, 0.391153, 0.642922, 1.0627, 1.76113", \ + "0.0272288, 0.153338, 0.24209, 0.392609, 0.642923, 1.06271, 1.76114", \ + "0.037519, 0.162826, 0.248446, 0.394367, 0.643825, 1.06272, 1.76117", \ + "0.0555909, 0.18611, 0.26962, 0.409971, 0.651637, 1.06458, 1.76444", \ + "0.0864677, 0.230796, 0.316584, 0.455303, 0.68711, 1.08594, 1.7694", \ + "0.134578, 0.304188, 0.399708, 0.546399, 0.780228, 1.16425, 1.82197", \ + "0.215573, 0.424535, 0.534671, 0.702621, 0.951035, 1.3537, 1.99143" \ ); } cell_fall (TIMING_DELAY_7x7ds1) { index_1 ("0.0186, 0.0966, 0.174, 0.3294, 0.6408, 1.263, 2.5074"); index_2 ("0.001, 0.0468, 0.078, 0.1296, 0.216, 0.36, 0.6"); values ( \ - "0.0258243, 0.0920381, 0.1352, 0.206326, 0.325239, 0.523406, 0.85309", \ - "0.0429673, 0.126135, 0.171076, 0.242664, 0.361425, 0.559394, 0.889506", \ - "0.0525958, 0.151764, 0.202043, 0.277702, 0.398097, 0.596112, 0.925847", \ - "0.0658501, 0.189153, 0.249232, 0.336504, 0.466145, 0.668301, 0.998224", \ - "0.0840035, 0.242854, 0.317558, 0.424219, 0.57664, 0.800611, 1.14344", \ - "0.108401, 0.314585, 0.412389, 0.546039, 0.736489, 1.00555, 1.39541", \ - "0.141346, 0.407674, 0.536518, 0.712637, 0.955641, 1.29385, 1.77009" \ + "0.0258243, 0.0920541, 0.135201, 0.206322, 0.32524, 0.523401, 0.853085", \ + "0.0429673, 0.126134, 0.171075, 0.242682, 0.361499, 0.559392, 0.889516", \ + "0.0525957, 0.151764, 0.202009, 0.277701, 0.398095, 0.596105, 0.925662", \ + "0.0658501, 0.189152, 0.249231, 0.336476, 0.466177, 0.668299, 0.998216", \ + "0.0840038, 0.24288, 0.317558, 0.424022, 0.576644, 0.800766, 1.14343", \ + "0.108401, 0.314585, 0.412388, 0.546039, 0.736488, 1.00555, 1.3955", \ + "0.141348, 0.407674, 0.536519, 0.712637, 0.95564, 1.29385, 1.77009" \ ); } fall_transition (TIMING_DELAY_7x7ds1) { index_1 ("0.0186, 0.0966, 0.174, 0.3294, 0.6408, 1.263, 2.5074"); index_2 ("0.001, 0.0468, 0.078, 0.1296, 0.216, 0.36, 0.6"); values ( \ - "0.0184924, 0.102878, 0.161027, 0.257354, 0.418416, 0.687239, 1.13451", \ - "0.0318478, 0.113613, 0.167605, 0.26013, 0.418953, 0.68724, 1.13476", \ - "0.0424629, 0.130615, 0.183606, 0.271883, 0.425074, 0.691092, 1.13477", \ - "0.0597014, 0.162252, 0.217822, 0.305622, 0.451322, 0.703243, 1.13885", \ - "0.088471, 0.216478, 0.278829, 0.373521, 0.522122, 0.76301, 1.17684", \ - "0.13472, 0.307555, 0.381025, 0.489497, 0.651056, 0.903978, 1.30761", \ - "0.214649, 0.452052, 0.551914, 0.683602, 0.874325, 1.15276, 1.58566" \ + "0.0184922, 0.102939, 0.161179, 0.257474, 0.418415, 0.687237, 1.13451", \ + "0.0318472, 0.113613, 0.167605, 0.26013, 0.419044, 0.687238, 1.13476", \ + "0.0424629, 0.130614, 0.183572, 0.271882, 0.42507, 0.691042, 1.13477", \ + "0.0597013, 0.162252, 0.217821, 0.305664, 0.451476, 0.703243, 1.13851", \ + "0.0884706, 0.216444, 0.278828, 0.373468, 0.522129, 0.762887, 1.17684", \ + "0.13472, 0.307555, 0.381025, 0.489496, 0.651054, 0.903976, 1.30721", \ + "0.214648, 0.452055, 0.551913, 0.6836, 0.874323, 1.15276, 1.58566" \ ); } } @@ -2455,52 +2455,52 @@ library (sg13g2_stdcell_typ_1p50V_25C) { index_1 ("0.0186, 0.0966, 0.174, 0.3294, 0.6408, 1.263, 2.5074"); index_2 ("0.001, 0.0468, 0.078, 0.1296, 0.216, 0.36, 0.6"); values ( \ - "0.0367094, 0.130342, 0.193037, 0.296639, 0.46987, 0.758499, 1.23946", \ - "0.0522475, 0.154143, 0.217145, 0.320791, 0.494049, 0.782816, 1.26364", \ - "0.060595, 0.17395, 0.239119, 0.343519, 0.516877, 0.806006, 1.28673", \ - "0.0704814, 0.204476, 0.275945, 0.385848, 0.561667, 0.85051, 1.33139", \ - "0.0874676, 0.250785, 0.334568, 0.456679, 0.644858, 0.940726, 1.4236", \ - "0.112404, 0.316869, 0.418875, 0.564781, 0.776966, 1.0995, 1.60111", \ - "0.146649, 0.411783, 0.536476, 0.716003, 0.974323, 1.34933, 1.90258" \ + "0.0366957, 0.130334, 0.193023, 0.296553, 0.469849, 0.758473, 1.23952", \ + "0.052247, 0.154136, 0.217134, 0.320785, 0.494038, 0.782797, 1.26362", \ + "0.060594, 0.173948, 0.239114, 0.343512, 0.516854, 0.805822, 1.28671", \ + "0.0704801, 0.204473, 0.275998, 0.385841, 0.561681, 0.850484, 1.33149", \ + "0.0874658, 0.250782, 0.334563, 0.456673, 0.644847, 0.940653, 1.42357", \ + "0.112402, 0.316862, 0.418869, 0.564772, 0.776955, 1.09947, 1.60108", \ + "0.146645, 0.411777, 0.536467, 0.715991, 0.974309, 1.34932, 1.90255" \ ); } rise_transition (TIMING_DELAY_7x7ds1) { index_1 ("0.0186, 0.0966, 0.174, 0.3294, 0.6408, 1.263, 2.5074"); index_2 ("0.001, 0.0468, 0.078, 0.1296, 0.216, 0.36, 0.6"); values ( \ - "0.0234365, 0.156639, 0.247075, 0.396911, 0.64754, 1.06546, 1.76119", \ - "0.0328778, 0.159553, 0.248356, 0.397116, 0.647541, 1.06547, 1.7612", \ - "0.0425748, 0.168743, 0.254411, 0.399841, 0.650389, 1.06548, 1.76126", \ - "0.0599763, 0.191742, 0.275199, 0.415262, 0.656129, 1.06727, 1.76225", \ - "0.0884003, 0.234878, 0.321781, 0.459911, 0.691731, 1.08896, 1.76888", \ - "0.133055, 0.307118, 0.404381, 0.550883, 0.782804, 1.16664, 1.82241", \ - "0.207473, 0.423249, 0.536179, 0.70246, 0.954548, 1.35191, 1.99145" \ + "0.0234299, 0.156635, 0.247069, 0.396783, 0.647527, 1.06544, 1.76119", \ + "0.032877, 0.159541, 0.248227, 0.397108, 0.647528, 1.06545, 1.7612", \ + "0.0425742, 0.16874, 0.254404, 0.399833, 0.650159, 1.06546, 1.76122", \ + "0.0599756, 0.191739, 0.275122, 0.415254, 0.65623, 1.06716, 1.76143", \ + "0.0883995, 0.234891, 0.321775, 0.459903, 0.691713, 1.08878, 1.76944", \ + "0.133053, 0.307116, 0.404375, 0.550875, 0.782792, 1.16662, 1.82238", \ + "0.207471, 0.423254, 0.536173, 0.702451, 0.954537, 1.3519, 1.99136" \ ); } cell_fall (TIMING_DELAY_7x7ds1) { index_1 ("0.0186, 0.0966, 0.174, 0.3294, 0.6408, 1.263, 2.5074"); index_2 ("0.001, 0.0468, 0.078, 0.1296, 0.216, 0.36, 0.6"); values ( \ - "0.0286195, 0.0944826, 0.137688, 0.208767, 0.327643, 0.525637, 0.855559", \ - "0.044059, 0.121315, 0.165785, 0.237392, 0.356382, 0.55438, 0.88453", \ - "0.0522701, 0.142204, 0.190047, 0.264366, 0.384604, 0.582882, 0.912909", \ - "0.062877, 0.173976, 0.229173, 0.310883, 0.43742, 0.638754, 0.969391", \ - "0.0771589, 0.221089, 0.288351, 0.384426, 0.526691, 0.742615, 1.08209", \ - "0.0954538, 0.283094, 0.371504, 0.492189, 0.662101, 0.910141, 1.28186", \ - "0.115507, 0.360579, 0.477414, 0.637952, 0.857178, 1.15906, 1.59421" \ + "0.0286191, 0.0944825, 0.137686, 0.208811, 0.327642, 0.525637, 0.855541", \ + "0.0440589, 0.121327, 0.165785, 0.2374, 0.356388, 0.554378, 0.884535", \ + "0.0522699, 0.142203, 0.190066, 0.264396, 0.384603, 0.582927, 0.912911", \ + "0.0628769, 0.173976, 0.229173, 0.310883, 0.437419, 0.63878, 0.969313", \ + "0.077159, 0.221088, 0.28835, 0.384425, 0.52669, 0.742613, 1.08199", \ + "0.0954544, 0.283094, 0.371503, 0.492188, 0.6621, 0.910139, 1.28186", \ + "0.115509, 0.360513, 0.477414, 0.637951, 0.857177, 1.15906, 1.5942" \ ); } fall_transition (TIMING_DELAY_7x7ds1) { index_1 ("0.0186, 0.0966, 0.174, 0.3294, 0.6408, 1.263, 2.5074"); index_2 ("0.001, 0.0468, 0.078, 0.1296, 0.216, 0.36, 0.6"); values ( \ - "0.0178009, 0.102888, 0.161306, 0.257648, 0.418931, 0.687012, 1.13481", \ - "0.0276127, 0.109411, 0.165036, 0.259166, 0.419192, 0.687128, 1.13482", \ - "0.0373768, 0.120925, 0.175148, 0.266329, 0.422568, 0.688422, 1.13483", \ - "0.054629, 0.144549, 0.198841, 0.288669, 0.439149, 0.697286, 1.13736", \ - "0.0828614, 0.189724, 0.246783, 0.336613, 0.486499, 0.735365, 1.16102", \ - "0.127103, 0.269286, 0.333967, 0.431238, 0.582626, 0.832842, 1.24746", \ - "0.201033, 0.3956, 0.482383, 0.599359, 0.764735, 1.02598, 1.44136" \ + "0.0178007, 0.102888, 0.161303, 0.257429, 0.41893, 0.687005, 1.1348", \ + "0.0276127, 0.109417, 0.165039, 0.258916, 0.418932, 0.687104, 1.13481", \ + "0.0373768, 0.120925, 0.17516, 0.266325, 0.422567, 0.688445, 1.13482", \ + "0.0546288, 0.14455, 0.198842, 0.288668, 0.439148, 0.697312, 1.13714", \ + "0.0828612, 0.189723, 0.246782, 0.336613, 0.486497, 0.735363, 1.16093", \ + "0.127103, 0.269288, 0.333966, 0.431237, 0.582625, 0.83284, 1.24746", \ + "0.201032, 0.395575, 0.482381, 0.599358, 0.764734, 1.02598, 1.44135" \ ); } } @@ -2514,52 +2514,52 @@ library (sg13g2_stdcell_typ_1p50V_25C) { index_1 ("0.0186, 0.0966, 0.174, 0.3294, 0.6408, 1.263, 2.5074"); index_2 ("0.001, 0.0468, 0.078, 0.1296, 0.216, 0.36, 0.6"); values ( \ - "0.029319, 0.124457, 0.187353, 0.290923, 0.464135, 0.752826, 1.23397", \ - "0.0480064, 0.155352, 0.218402, 0.322044, 0.495421, 0.784204, 1.26517", \ - "0.0602054, 0.183483, 0.249764, 0.354225, 0.527256, 0.815661, 1.29665", \ - "0.0762889, 0.227049, 0.302903, 0.415507, 0.592007, 0.880187, 1.36127", \ - "0.102579, 0.290444, 0.383035, 0.515971, 0.710777, 1.0097, 1.49097", \ - "0.142872, 0.378672, 0.495654, 0.660421, 0.895692, 1.23529, 1.7452", \ - "0.207417, 0.505947, 0.65293, 0.861969, 1.15832, 1.57391, 2.16864" \ + "0.0293129, 0.124451, 0.187332, 0.290916, 0.464222, 0.752808, 1.23398", \ + "0.0479943, 0.155358, 0.218382, 0.32205, 0.495675, 0.784224, 1.26513", \ + "0.0602046, 0.183481, 0.249758, 0.35418, 0.527248, 0.81593, 1.29661", \ + "0.0762876, 0.227047, 0.302924, 0.415489, 0.591932, 0.880171, 1.36123", \ + "0.102577, 0.29044, 0.38303, 0.515965, 0.710867, 1.00968, 1.491", \ + "0.142867, 0.378776, 0.495923, 0.660415, 0.895676, 1.23527, 1.74524", \ + "0.207409, 0.505938, 0.65292, 0.861951, 1.15831, 1.57389, 2.16863" \ ); } rise_transition (TIMING_DELAY_7x7ds1) { index_1 ("0.0186, 0.0966, 0.174, 0.3294, 0.6408, 1.263, 2.5074"); index_2 ("0.001, 0.0468, 0.078, 0.1296, 0.216, 0.36, 0.6"); values ( \ - "0.0238265, 0.156759, 0.247169, 0.396863, 0.647769, 1.06511, 1.7616", \ - "0.0370153, 0.161761, 0.248902, 0.39695, 0.64777, 1.06513, 1.76161", \ - "0.0465315, 0.17651, 0.259261, 0.401801, 0.650531, 1.06514, 1.76162", \ - "0.0620397, 0.209082, 0.290993, 0.426545, 0.661759, 1.06867, 1.76222", \ - "0.0878201, 0.26352, 0.354192, 0.491798, 0.717478, 1.10349, 1.77464", \ - "0.132586, 0.347462, 0.454808, 0.611308, 0.847464, 1.22259, 1.85858", \ - "0.211917, 0.478978, 0.610496, 0.799999, 1.07516, 1.48024, 2.11139" \ + "0.0238324, 0.156756, 0.247155, 0.396854, 0.647543, 1.06508, 1.7616", \ + "0.0370587, 0.161793, 0.248935, 0.396943, 0.647679, 1.06512, 1.76161", \ + "0.0465312, 0.176507, 0.259277, 0.40173, 0.650309, 1.06513, 1.76162", \ + "0.0620393, 0.209079, 0.291013, 0.426525, 0.661639, 1.07014, 1.76216", \ + "0.0878198, 0.263517, 0.354187, 0.491791, 0.717483, 1.10347, 1.77457", \ + "0.132586, 0.347468, 0.455036, 0.611304, 0.847555, 1.22257, 1.8583", \ + "0.211917, 0.478977, 0.610493, 0.799989, 1.07515, 1.48022, 2.11138" \ ); } cell_fall (TIMING_DELAY_7x7ds1) { index_1 ("0.0186, 0.0966, 0.174, 0.3294, 0.6408, 1.263, 2.5074"); index_2 ("0.001, 0.0468, 0.078, 0.1296, 0.216, 0.36, 0.6"); values ( \ - "0.01478, 0.0552219, 0.0803262, 0.121752, 0.19099, 0.30613, 0.497894", \ - "0.0243138, 0.0889356, 0.118976, 0.162911, 0.232932, 0.348074, 0.539629", \ - "0.0289864, 0.110809, 0.146698, 0.197324, 0.272498, 0.389941, 0.581624", \ - "0.033215, 0.141191, 0.186848, 0.249475, 0.338195, 0.466436, 0.663492", \ - "0.0371513, 0.181309, 0.242528, 0.323906, 0.435906, 0.591188, 0.813408", \ - "0.0373194, 0.227642, 0.311667, 0.423053, 0.569851, 0.770245, 1.04395", \ - "0.0373204, 0.271892, 0.386643, 0.539826, 0.743299, 1.00969, 1.36882" \ + "0.0147806, 0.0552244, 0.0803199, 0.121715, 0.19099, 0.306159, 0.497914", \ + "0.0243178, 0.0889218, 0.118945, 0.162927, 0.232921, 0.348071, 0.539688", \ + "0.0289876, 0.110813, 0.146703, 0.197332, 0.272509, 0.389957, 0.58167", \ + "0.0332167, 0.141196, 0.186841, 0.249483, 0.338208, 0.466459, 0.66358", \ + "0.0371541, 0.181315, 0.242531, 0.323935, 0.4359, 0.591211, 0.813443", \ + "0.0373231, 0.22765, 0.311678, 0.423067, 0.56987, 0.770274, 1.04399", \ + "0.0373241, 0.271906, 0.386656, 0.539801, 0.743324, 1.00972, 1.36886" \ ); } fall_transition (TIMING_DELAY_7x7ds1) { index_1 ("0.0186, 0.0966, 0.174, 0.3294, 0.6408, 1.263, 2.5074"); index_2 ("0.001, 0.0468, 0.078, 0.1296, 0.216, 0.36, 0.6"); values ( \ - "0.0117299, 0.0592333, 0.0929146, 0.148601, 0.242281, 0.398179, 0.65844", \ - "0.0287702, 0.0761669, 0.105941, 0.156631, 0.245256, 0.398761, 0.658441", \ - "0.0409588, 0.0942539, 0.125141, 0.174918, 0.259314, 0.406063, 0.663105", \ - "0.0604907, 0.126099, 0.160286, 0.213297, 0.297197, 0.435995, 0.676557", \ - "0.0926137, 0.179744, 0.220846, 0.280848, 0.371729, 0.513492, 0.743433", \ - "0.146273, 0.266466, 0.321809, 0.394021, 0.501116, 0.657243, 0.89994", \ - "0.236804, 0.404457, 0.481589, 0.584062, 0.716112, 0.903894, 1.175" \ + "0.0117196, 0.0592431, 0.0929155, 0.14861, 0.242246, 0.398207, 0.658488", \ + "0.0287677, 0.0761573, 0.105951, 0.156619, 0.245295, 0.398788, 0.658489", \ + "0.0409595, 0.0942577, 0.125147, 0.174922, 0.259295, 0.406085, 0.66034", \ + "0.0604916, 0.126103, 0.160272, 0.213307, 0.297208, 0.436009, 0.67667", \ + "0.0926152, 0.179749, 0.220747, 0.280977, 0.372602, 0.513516, 0.743476", \ + "0.146275, 0.266472, 0.321817, 0.394035, 0.500705, 0.657544, 0.90002", \ + "0.236807, 0.404464, 0.481596, 0.584108, 0.716131, 0.903917, 1.17508" \ ); } } @@ -2573,52 +2573,52 @@ library (sg13g2_stdcell_typ_1p50V_25C) { index_1 ("0.0186, 0.0966, 0.174, 0.3294, 0.6408, 1.263, 2.5074"); index_2 ("0.001, 0.0468, 0.078, 0.1296, 0.216, 0.36, 0.6"); values ( \ - "0.0221428, 0.117524, 0.180643, 0.284647, 0.458819, 0.748376, 1.23151", \ - "0.0364554, 0.148367, 0.211703, 0.315748, 0.489759, 0.779975, 1.26264", \ - "0.0458241, 0.175962, 0.242938, 0.347925, 0.521664, 0.815117, 1.29403", \ - "0.0587202, 0.218018, 0.295329, 0.408931, 0.586391, 0.875691, 1.35849", \ - "0.0797073, 0.279284, 0.373677, 0.507919, 0.704974, 1.00529, 1.48871", \ - "0.113179, 0.364662, 0.484, 0.650919, 0.888301, 1.23064, 1.74273", \ - "0.168741, 0.489014, 0.638487, 0.850196, 1.1495, 1.56699, 2.16536" \ + "0.0221437, 0.117505, 0.180631, 0.28464, 0.458829, 0.74854, 1.23163", \ + "0.0364551, 0.148373, 0.211724, 0.315726, 0.489743, 0.779941, 1.26261", \ + "0.045816, 0.175961, 0.242926, 0.34792, 0.521593, 0.815123, 1.29401", \ + "0.0587191, 0.218015, 0.295326, 0.408941, 0.586396, 0.875689, 1.35844", \ + "0.0797052, 0.279227, 0.373673, 0.507913, 0.704965, 1.00522, 1.48848", \ + "0.113175, 0.364656, 0.483993, 0.650912, 0.888692, 1.23062, 1.74255", \ + "0.168733, 0.489005, 0.638477, 0.850184, 1.14948, 1.56697, 2.16533" \ ); } rise_transition (TIMING_DELAY_7x7ds1) { index_1 ("0.0186, 0.0966, 0.174, 0.3294, 0.6408, 1.263, 2.5074"); index_2 ("0.001, 0.0468, 0.078, 0.1296, 0.216, 0.36, 0.6"); values ( \ - "0.0180318, 0.150201, 0.241, 0.391263, 0.642917, 1.06213, 1.761", \ - "0.0307094, 0.15602, 0.243032, 0.39187, 0.642918, 1.06214, 1.76101", \ - "0.0400463, 0.171336, 0.253871, 0.396435, 0.646109, 1.06558, 1.76167", \ - "0.0535108, 0.203738, 0.286073, 0.421833, 0.657392, 1.06559, 1.7623", \ - "0.0789593, 0.257457, 0.34935, 0.487303, 0.713657, 1.10116, 1.77428", \ - "0.122545, 0.342188, 0.449624, 0.606073, 0.84325, 1.22034, 1.85898", \ - "0.201909, 0.470949, 0.606155, 0.798601, 1.07094, 1.47719, 2.11164" \ + "0.0180251, 0.150186, 0.240987, 0.391256, 0.642904, 1.06233, 1.76113", \ + "0.0307092, 0.156015, 0.243007, 0.391643, 0.642905, 1.06234, 1.76114", \ + "0.0398947, 0.171343, 0.253838, 0.396427, 0.644189, 1.06557, 1.76165", \ + "0.0535107, 0.203735, 0.286011, 0.421806, 0.657376, 1.06658, 1.76203", \ + "0.0789593, 0.257486, 0.349347, 0.487296, 0.713647, 1.10113, 1.77418", \ + "0.122546, 0.342186, 0.44962, 0.606063, 0.844035, 1.22033, 1.85849", \ + "0.20191, 0.470947, 0.606152, 0.798595, 1.07092, 1.47718, 2.11162" \ ); } cell_fall (TIMING_DELAY_7x7ds1) { index_1 ("0.0186, 0.0966, 0.174, 0.3294, 0.6408, 1.263, 2.5074"); index_2 ("0.001, 0.0468, 0.078, 0.1296, 0.216, 0.36, 0.6"); values ( \ - "0.0144612, 0.0547846, 0.079748, 0.120913, 0.189878, 0.304666, 0.496169", \ - "0.0233523, 0.0882559, 0.118261, 0.162104, 0.2318, 0.346637, 0.537916", \ - "0.0271784, 0.109889, 0.145747, 0.196283, 0.271308, 0.388433, 0.579982", \ - "0.0300955, 0.139691, 0.185472, 0.248018, 0.336659, 0.464861, 0.661802", \ - "0.0302917, 0.178343, 0.24012, 0.321552, 0.433807, 0.589111, 0.811596", \ - "0.0302927, 0.221969, 0.307104, 0.419423, 0.566704, 0.767787, 1.04165", \ - "0.0302937, 0.261627, 0.378261, 0.533364, 0.738747, 1.00628, 1.3659" \ + "0.014468, 0.0547898, 0.0797612, 0.12093, 0.189888, 0.304683, 0.496206", \ + "0.0233517, 0.0882635, 0.118254, 0.162095, 0.231806, 0.346654, 0.537899", \ + "0.0271795, 0.109893, 0.145755, 0.196292, 0.271321, 0.38845, 0.580013", \ + "0.0300971, 0.139696, 0.18542, 0.248027, 0.33667, 0.464819, 0.661808", \ + "0.0302943, 0.17835, 0.240135, 0.321564, 0.433753, 0.589191, 0.811571", \ + "0.0302953, 0.22198, 0.307112, 0.419327, 0.566723, 0.767814, 1.04169", \ + "0.0302963, 0.26164, 0.378277, 0.533541, 0.738771, 1.0063, 1.36594" \ ); } fall_transition (TIMING_DELAY_7x7ds1) { index_1 ("0.0186, 0.0966, 0.174, 0.3294, 0.6408, 1.263, 2.5074"); index_2 ("0.001, 0.0468, 0.078, 0.1296, 0.216, 0.36, 0.6"); values ( \ - "0.00800836, 0.0552888, 0.0888866, 0.144638, 0.238372, 0.394412, 0.65444", \ - "0.01984, 0.0719448, 0.102013, 0.152745, 0.241369, 0.397158, 0.654441", \ - "0.0290625, 0.0893021, 0.120878, 0.17089, 0.25546, 0.402108, 0.65733", \ - "0.0436917, 0.120027, 0.155536, 0.208715, 0.293113, 0.432023, 0.672734", \ - "0.0691561, 0.172287, 0.214281, 0.27621, 0.367449, 0.509673, 0.73967", \ - "0.112508, 0.255679, 0.314107, 0.387157, 0.496786, 0.653527, 0.897064", \ - "0.189549, 0.388191, 0.469661, 0.575238, 0.709911, 0.900456, 1.17209" \ + "0.00801594, 0.055247, 0.0890596, 0.144654, 0.23839, 0.39444, 0.654257", \ + "0.019842, 0.07204, 0.102007, 0.15275, 0.241313, 0.394859, 0.654329", \ + "0.029063, 0.0893055, 0.120836, 0.170884, 0.255477, 0.402218, 0.656395", \ + "0.0436921, 0.120031, 0.155493, 0.208746, 0.292943, 0.431965, 0.673086", \ + "0.0691568, 0.172293, 0.214266, 0.276219, 0.367818, 0.50969, 0.739954", \ + "0.112509, 0.255686, 0.314118, 0.387058, 0.496802, 0.653549, 0.897104", \ + "0.189548, 0.388198, 0.469671, 0.575662, 0.70993, 0.897787, 1.17213" \ ); } } @@ -2632,52 +2632,52 @@ library (sg13g2_stdcell_typ_1p50V_25C) { index_1 ("0.0186, 0.0966, 0.174, 0.3294, 0.6408, 1.263, 2.5074"); index_2 ("0.001, 0.0468, 0.078, 0.1296, 0.216, 0.36, 0.6"); values ( \ - "0.0186755, 0.0896445, 0.136731, 0.213332, 0.341871, 0.556148, 0.913271", \ - "0.0315614, 0.122768, 0.170657, 0.24765, 0.376431, 0.59054, 0.947842", \ - "0.0395299, 0.14932, 0.202252, 0.282222, 0.411176, 0.625338, 0.982532", \ - "0.0498264, 0.187864, 0.251857, 0.342834, 0.479484, 0.695736, 1.05231", \ - "0.0657535, 0.241793, 0.323327, 0.435038, 0.594818, 0.829274, 1.19345", \ - "0.0894044, 0.314307, 0.41906, 0.563717, 0.7629, 1.04504, 1.45047", \ - "0.125946, 0.417531, 0.549339, 0.734258, 0.995813, 1.35241, 1.85007" \ + "0.0186816, 0.0896311, 0.136281, 0.213281, 0.341927, 0.556118, 0.913245", \ + "0.0315282, 0.12276, 0.170654, 0.247699, 0.376417, 0.59068, 0.947801", \ + "0.0395296, 0.149319, 0.20225, 0.282217, 0.411162, 0.625253, 0.982444", \ + "0.0498251, 0.187862, 0.251855, 0.342828, 0.479452, 0.695722, 1.05226", \ + "0.0657512, 0.241749, 0.323322, 0.435032, 0.594809, 0.829231, 1.19335", \ + "0.0893997, 0.314301, 0.419053, 0.563708, 0.762889, 1.04502, 1.45037", \ + "0.125937, 0.417522, 0.549328, 0.735315, 0.995802, 1.35239, 1.85013" \ ); } rise_transition (TIMING_DELAY_7x7ds1) { index_1 ("0.0186, 0.0966, 0.174, 0.3294, 0.6408, 1.263, 2.5074"); index_2 ("0.001, 0.0468, 0.078, 0.1296, 0.216, 0.36, 0.6"); values ( \ - "0.0138053, 0.111617, 0.180231, 0.292403, 0.480781, 0.795156, 1.31889", \ - "0.0269228, 0.120744, 0.184093, 0.293353, 0.480845, 0.795184, 1.3189", \ - "0.0362604, 0.138173, 0.198562, 0.302287, 0.483701, 0.79594, 1.31891", \ - "0.0500331, 0.171711, 0.234256, 0.33411, 0.505455, 0.804617, 1.31993", \ - "0.0747789, 0.22522, 0.297818, 0.404722, 0.572396, 0.855364, 1.34705", \ - "0.117981, 0.306838, 0.398516, 0.524449, 0.709968, 0.992345, 1.46006", \ - "0.196951, 0.432672, 0.547412, 0.709532, 0.934376, 1.25755, 1.7384" \ + "0.0138105, 0.111599, 0.179705, 0.292335, 0.480935, 0.795135, 1.31886", \ + "0.0268492, 0.120743, 0.184084, 0.293305, 0.480936, 0.795283, 1.31887", \ + "0.0362609, 0.138172, 0.198559, 0.302289, 0.48376, 0.795423, 1.31888", \ + "0.050033, 0.171584, 0.234246, 0.33411, 0.505397, 0.804607, 1.3203", \ + "0.0747788, 0.225163, 0.297814, 0.404717, 0.572385, 0.855234, 1.34664", \ + "0.117982, 0.306836, 0.398511, 0.524443, 0.709958, 0.992326, 1.45983", \ + "0.196952, 0.432671, 0.54741, 0.709267, 0.934369, 1.25753, 1.7384" \ ); } cell_fall (TIMING_DELAY_7x7ds1) { index_1 ("0.0186, 0.0966, 0.174, 0.3294, 0.6408, 1.263, 2.5074"); index_2 ("0.001, 0.0468, 0.078, 0.1296, 0.216, 0.36, 0.6"); values ( \ - "0.0141787, 0.0546075, 0.079572, 0.12075, 0.189707, 0.304496, 0.495985", \ - "0.0232544, 0.0879706, 0.11793, 0.161896, 0.231578, 0.346414, 0.537701", \ - "0.0277534, 0.109581, 0.145488, 0.196073, 0.271082, 0.388224, 0.579798", \ - "0.0320216, 0.13981, 0.185349, 0.247862, 0.336457, 0.464579, 0.661621", \ - "0.0352574, 0.17985, 0.240998, 0.32194, 0.433834, 0.589143, 0.811407", \ - "0.0352584, 0.227663, 0.311473, 0.421751, 0.568128, 0.768589, 1.04204", \ - "0.0352594, 0.278122, 0.390888, 0.543528, 0.74506, 1.00997, 1.36823" \ + "0.0141808, 0.05461, 0.0795644, 0.120758, 0.189721, 0.304523, 0.496057", \ + "0.0232548, 0.0879653, 0.117939, 0.161911, 0.231589, 0.34644, 0.538013", \ + "0.0277545, 0.109585, 0.145494, 0.196081, 0.271094, 0.388241, 0.579787", \ + "0.0320272, 0.139814, 0.185346, 0.247871, 0.33647, 0.464617, 0.661654", \ + "0.0352602, 0.179856, 0.241006, 0.321951, 0.434014, 0.589166, 0.811441", \ + "0.0352612, 0.227665, 0.311484, 0.421765, 0.568147, 0.768618, 1.04208", \ + "0.0352622, 0.278136, 0.390904, 0.543381, 0.745085, 1.01002, 1.36828" \ ); } fall_transition (TIMING_DELAY_7x7ds1) { index_1 ("0.0186, 0.0966, 0.174, 0.3294, 0.6408, 1.263, 2.5074"); index_2 ("0.001, 0.0468, 0.078, 0.1296, 0.216, 0.36, 0.6"); values ( \ - "0.00813831, 0.0552632, 0.0888128, 0.144765, 0.238475, 0.394406, 0.654476", \ - "0.0199806, 0.0721593, 0.102054, 0.152875, 0.241363, 0.395819, 0.654477", \ - "0.02892, 0.08954, 0.120996, 0.171025, 0.2556, 0.402145, 0.657111", \ - "0.0432081, 0.119993, 0.155533, 0.209313, 0.292993, 0.432004, 0.672895", \ - "0.0678259, 0.171303, 0.213393, 0.275447, 0.367676, 0.509693, 0.739676", \ - "0.11042, 0.252909, 0.311348, 0.385091, 0.495677, 0.652797, 0.89688", \ - "0.187033, 0.382117, 0.463809, 0.570064, 0.704148, 0.896979, 1.16948" \ + "0.00813025, 0.05529, 0.0889542, 0.144777, 0.238298, 0.394436, 0.654297", \ + "0.0199815, 0.0721084, 0.102057, 0.152887, 0.241381, 0.395873, 0.654958", \ + "0.0289205, 0.0895437, 0.121001, 0.171086, 0.255614, 0.402254, 0.656439", \ + "0.0431172, 0.119998, 0.155214, 0.209322, 0.293006, 0.432175, 0.672838", \ + "0.0678264, 0.171306, 0.213405, 0.275457, 0.367885, 0.509723, 0.739913", \ + "0.110421, 0.252696, 0.311355, 0.385102, 0.495694, 0.652822, 0.896922", \ + "0.187034, 0.382124, 0.463818, 0.569631, 0.704165, 0.897005, 1.16953" \ ); } } @@ -2689,52 +2689,52 @@ library (sg13g2_stdcell_typ_1p50V_25C) { index_1 ("0.0186, 0.0966, 0.174, 0.3294, 0.6408, 1.263, 2.5074"); index_2 ("0.001, 0.0468, 0.078, 0.1296, 0.216, 0.36, 0.6"); values ( \ - "0.029319, 0.124457, 0.187353, 0.290923, 0.464135, 0.752826, 1.23397", \ - "0.0480064, 0.155352, 0.218402, 0.322044, 0.495421, 0.784204, 1.26517", \ - "0.0602054, 0.183483, 0.249764, 0.354225, 0.527256, 0.815661, 1.29665", \ - "0.0762889, 0.227049, 0.302903, 0.415507, 0.592007, 0.880187, 1.36127", \ - "0.102579, 0.290444, 0.383035, 0.515971, 0.710777, 1.0097, 1.49097", \ - "0.142872, 0.378672, 0.495654, 0.660421, 0.895692, 1.23529, 1.7452", \ - "0.207417, 0.505947, 0.65293, 0.861969, 1.15832, 1.57391, 2.16864" \ + "0.0293129, 0.124451, 0.187332, 0.290916, 0.464222, 0.752808, 1.23398", \ + "0.0479943, 0.155358, 0.218382, 0.32205, 0.495675, 0.784224, 1.26513", \ + "0.0602046, 0.183481, 0.249758, 0.35418, 0.527248, 0.81593, 1.29661", \ + "0.0762876, 0.227047, 0.302924, 0.415489, 0.591932, 0.880171, 1.36123", \ + "0.102577, 0.29044, 0.38303, 0.515965, 0.710867, 1.00968, 1.491", \ + "0.142867, 0.378776, 0.495923, 0.660415, 0.895676, 1.23527, 1.74524", \ + "0.207409, 0.505938, 0.65292, 0.861951, 1.15831, 1.57389, 2.16863" \ ); } rise_transition (TIMING_DELAY_7x7ds1) { index_1 ("0.0186, 0.0966, 0.174, 0.3294, 0.6408, 1.263, 2.5074"); index_2 ("0.001, 0.0468, 0.078, 0.1296, 0.216, 0.36, 0.6"); values ( \ - "0.0238265, 0.156759, 0.247169, 0.396863, 0.647769, 1.06511, 1.7616", \ - "0.0370153, 0.161761, 0.248902, 0.39695, 0.64777, 1.06513, 1.76161", \ - "0.0465315, 0.17651, 0.259261, 0.401801, 0.650531, 1.06514, 1.76162", \ - "0.0620397, 0.209082, 0.290993, 0.426545, 0.661759, 1.06867, 1.76222", \ - "0.0878201, 0.26352, 0.354192, 0.491798, 0.717478, 1.10349, 1.77464", \ - "0.132586, 0.347462, 0.454808, 0.611308, 0.847464, 1.22259, 1.85858", \ - "0.211917, 0.478978, 0.610496, 0.799999, 1.07516, 1.48024, 2.11139" \ + "0.0238324, 0.156756, 0.247155, 0.396854, 0.647543, 1.06508, 1.7616", \ + "0.0370587, 0.161793, 0.248935, 0.396943, 0.647679, 1.06512, 1.76161", \ + "0.0465312, 0.176507, 0.259277, 0.40173, 0.650309, 1.06513, 1.76162", \ + "0.0620393, 0.209079, 0.291013, 0.426525, 0.661639, 1.07014, 1.76216", \ + "0.0878198, 0.263517, 0.354187, 0.491791, 0.717483, 1.10347, 1.77457", \ + "0.132586, 0.347468, 0.455036, 0.611304, 0.847555, 1.22257, 1.8583", \ + "0.211917, 0.478977, 0.610493, 0.799989, 1.07515, 1.48022, 2.11138" \ ); } cell_fall (TIMING_DELAY_7x7ds1) { index_1 ("0.0186, 0.0966, 0.174, 0.3294, 0.6408, 1.263, 2.5074"); index_2 ("0.001, 0.0468, 0.078, 0.1296, 0.216, 0.36, 0.6"); values ( \ - "0.01478, 0.0552219, 0.0803262, 0.121752, 0.19099, 0.30613, 0.497894", \ - "0.0243138, 0.0889356, 0.118976, 0.162911, 0.232932, 0.348074, 0.539629", \ - "0.0289864, 0.110809, 0.146698, 0.197324, 0.272498, 0.389941, 0.581624", \ - "0.033215, 0.141191, 0.186848, 0.249475, 0.338195, 0.466436, 0.663492", \ - "0.0371513, 0.181309, 0.242528, 0.323906, 0.435906, 0.591188, 0.813408", \ - "0.0373194, 0.227642, 0.311667, 0.423053, 0.569851, 0.770245, 1.04395", \ - "0.0373204, 0.271892, 0.386643, 0.539826, 0.743299, 1.00969, 1.36882" \ + "0.0147806, 0.0552244, 0.0803199, 0.121715, 0.19099, 0.306159, 0.497914", \ + "0.0243178, 0.0889218, 0.118945, 0.162927, 0.232921, 0.348071, 0.539688", \ + "0.0289876, 0.110813, 0.146703, 0.197332, 0.272509, 0.389957, 0.58167", \ + "0.0332167, 0.141196, 0.186841, 0.249483, 0.338208, 0.466459, 0.66358", \ + "0.0371541, 0.181315, 0.242531, 0.323935, 0.4359, 0.591211, 0.813443", \ + "0.0373231, 0.22765, 0.311678, 0.423067, 0.56987, 0.770274, 1.04399", \ + "0.0373241, 0.271906, 0.386656, 0.539801, 0.743324, 1.00972, 1.36886" \ ); } fall_transition (TIMING_DELAY_7x7ds1) { index_1 ("0.0186, 0.0966, 0.174, 0.3294, 0.6408, 1.263, 2.5074"); index_2 ("0.001, 0.0468, 0.078, 0.1296, 0.216, 0.36, 0.6"); values ( \ - "0.0117299, 0.0592333, 0.0929146, 0.148601, 0.242281, 0.398179, 0.65844", \ - "0.0287702, 0.0761669, 0.105941, 0.156631, 0.245256, 0.398761, 0.658441", \ - "0.0409588, 0.0942539, 0.125141, 0.174918, 0.259314, 0.406063, 0.663105", \ - "0.0604907, 0.126099, 0.160286, 0.213297, 0.297197, 0.435995, 0.676557", \ - "0.0926137, 0.179744, 0.220846, 0.280848, 0.371729, 0.513492, 0.743433", \ - "0.146273, 0.266466, 0.321809, 0.394021, 0.501116, 0.657243, 0.89994", \ - "0.236804, 0.404457, 0.481589, 0.584062, 0.716112, 0.903894, 1.175" \ + "0.0117196, 0.0592431, 0.0929155, 0.14861, 0.242246, 0.398207, 0.658488", \ + "0.0287677, 0.0761573, 0.105951, 0.156619, 0.245295, 0.398788, 0.658489", \ + "0.0409595, 0.0942577, 0.125147, 0.174922, 0.259295, 0.406085, 0.66034", \ + "0.0604916, 0.126103, 0.160272, 0.213307, 0.297208, 0.436009, 0.67667", \ + "0.0926152, 0.179749, 0.220747, 0.280977, 0.372602, 0.513516, 0.743476", \ + "0.146275, 0.266472, 0.321817, 0.394035, 0.500705, 0.657544, 0.90002", \ + "0.236807, 0.404464, 0.481596, 0.584108, 0.716131, 0.903917, 1.17508" \ ); } } @@ -2744,26 +2744,26 @@ library (sg13g2_stdcell_typ_1p50V_25C) { index_1 ("0.0186, 0.0966, 0.174, 0.3294, 0.6408, 1.263, 2.5074"); index_2 ("0.001, 0.0468, 0.078, 0.1296, 0.216, 0.36, 0.6"); values ( \ - "0.0137107, 0.0150894, 0.0150382, 0.0148991, 0.0145676, 0.0139867, 0.0130449", \ - "0.0134147, 0.014253, 0.0144401, 0.0146851, 0.0142948, 0.0137048, 0.0130652", \ - "0.0145249, 0.0142385, 0.0146163, 0.0144018, 0.0144157, 0.0136561, 0.0130951", \ - "0.018305, 0.0157308, 0.015216, 0.0152068, 0.0144964, 0.01385, 0.0130184", \ - "0.0281611, 0.021503, 0.019964, 0.0185643, 0.0173316, 0.0153366, 0.0160603", \ - "0.0490795, 0.0371064, 0.0336649, 0.0301996, 0.0264151, 0.0222823, 0.0213087", \ - "0.0921295, 0.074515, 0.0677004, 0.060229, 0.0517496, 0.0448292, 0.0360979" \ + "0.0137137, 0.0150886, 0.0150319, 0.0149012, 0.0145696, 0.0140102, 0.0131046", \ + "0.0134143, 0.0142738, 0.0145802, 0.0146854, 0.0143086, 0.0137606, 0.0130653", \ + "0.0145263, 0.0142226, 0.0145741, 0.0144132, 0.0141917, 0.0136359, 0.0130986", \ + "0.0183003, 0.01571, 0.0152067, 0.0152192, 0.0146219, 0.0138483, 0.0137708", \ + "0.0281606, 0.0215327, 0.019967, 0.0184265, 0.0173323, 0.0152837, 0.0153755", \ + "0.0490883, 0.0371069, 0.0336703, 0.0301962, 0.0264409, 0.022327, 0.0212513", \ + "0.0922002, 0.0745146, 0.0676841, 0.0602316, 0.0518491, 0.0448117, 0.0361785" \ ); } fall_power (POWER_7x7ds1) { index_1 ("0.0186, 0.0966, 0.174, 0.3294, 0.6408, 1.263, 2.5074"); index_2 ("0.001, 0.0468, 0.078, 0.1296, 0.216, 0.36, 0.6"); values ( \ - "0.00853345, 0.00887886, 0.00877763, 0.00859812, 0.00826612, 0.00776537, 0.00664167", \ - "0.00874404, 0.00865039, 0.00870731, 0.00847828, 0.00808008, 0.00758136, 0.00650823", \ - "0.0104513, 0.0092498, 0.008897, 0.00904702, 0.00823242, 0.00827117, 0.00646818", \ - "0.0145877, 0.0114105, 0.0107586, 0.00972905, 0.00936409, 0.00832197, 0.00684581", \ - "0.0241245, 0.0174053, 0.015685, 0.0141742, 0.0123104, 0.0103981, 0.00937232", \ - "0.0443678, 0.0332272, 0.0294796, 0.0253915, 0.0215064, 0.017927, 0.0134348", \ - "0.0860745, 0.0702258, 0.0633329, 0.0551715, 0.0464113, 0.0381164, 0.0305329" \ + "0.00853323, 0.00889353, 0.00881705, 0.00860891, 0.00826429, 0.00776574, 0.00664031", \ + "0.00874155, 0.00865031, 0.00870751, 0.00881189, 0.0081002, 0.0075809, 0.00651016", \ + "0.0104419, 0.00925345, 0.00893997, 0.0090461, 0.00823149, 0.00826763, 0.00648849", \ + "0.0145895, 0.0114168, 0.0107559, 0.00982913, 0.00938936, 0.00819056, 0.00712295", \ + "0.0241258, 0.0173979, 0.015677, 0.0141517, 0.012312, 0.0103723, 0.00937016", \ + "0.0443687, 0.0332259, 0.0294751, 0.0253913, 0.0214792, 0.0179869, 0.0134982", \ + "0.0860752, 0.0702295, 0.0633349, 0.0551722, 0.0464116, 0.0381162, 0.0304971" \ ); } } @@ -2773,26 +2773,26 @@ library (sg13g2_stdcell_typ_1p50V_25C) { index_1 ("0.0186, 0.0966, 0.174, 0.3294, 0.6408, 1.263, 2.5074"); index_2 ("0.001, 0.0468, 0.078, 0.1296, 0.216, 0.36, 0.6"); values ( \ - "0.0147497, 0.0150053, 0.0148978, 0.0147028, 0.0143293, 0.0137219, 0.0128538", \ - "0.0144189, 0.0146524, 0.0147411, 0.0145109, 0.0141624, 0.0136303, 0.0128314", \ - "0.0152628, 0.0148164, 0.0150249, 0.0146858, 0.0145559, 0.0136308, 0.0128229", \ - "0.0187431, 0.0164506, 0.0158448, 0.0157435, 0.0147122, 0.0138779, 0.0131719", \ - "0.0282464, 0.0222952, 0.0208075, 0.0191345, 0.0178168, 0.015631, 0.0154152", \ - "0.0487507, 0.0385056, 0.0352055, 0.0314493, 0.0272126, 0.022882, 0.0218951", \ - "0.0908992, 0.0764202, 0.0702283, 0.0626094, 0.0542877, 0.0459607, 0.0373352" \ + "0.0147478, 0.015005, 0.0148895, 0.0146883, 0.0143182, 0.0137186, 0.0126415", \ + "0.0144196, 0.0146629, 0.0146821, 0.0145107, 0.0141622, 0.0135806, 0.0128323", \ + "0.0152607, 0.0148145, 0.0147778, 0.0146857, 0.0145127, 0.0135411, 0.0128244", \ + "0.0187438, 0.0164493, 0.0158387, 0.0156572, 0.0147161, 0.0138707, 0.0129325", \ + "0.0282458, 0.0222996, 0.0207998, 0.0191346, 0.0177474, 0.0156507, 0.0173661", \ + "0.048751, 0.0385063, 0.035206, 0.031449, 0.0272219, 0.0229496, 0.0207838", \ + "0.0908986, 0.0764276, 0.0702192, 0.0626025, 0.0542799, 0.045963, 0.0367992" \ ); } fall_power (POWER_7x7ds1) { index_1 ("0.0186, 0.0966, 0.174, 0.3294, 0.6408, 1.263, 2.5074"); index_2 ("0.001, 0.0468, 0.078, 0.1296, 0.216, 0.36, 0.6"); values ( \ - "0.0141149, 0.0142464, 0.0141811, 0.0139977, 0.013652, 0.0130413, 0.0119752", \ - "0.0136921, 0.0139307, 0.0142091, 0.0140145, 0.0135481, 0.012885, 0.0118899", \ - "0.0146466, 0.0142964, 0.0140235, 0.0141932, 0.0135083, 0.0129519, 0.0119246", \ - "0.0180586, 0.0157955, 0.0154086, 0.0147574, 0.0145137, 0.013325, 0.0128692", \ - "0.0270315, 0.0211139, 0.0197741, 0.0184089, 0.0169658, 0.0153269, 0.0158131", \ - "0.0467139, 0.0360124, 0.0325859, 0.0289478, 0.0252293, 0.0225603, 0.0182589", \ - "0.0874349, 0.0720122, 0.0652955, 0.057685, 0.049272, 0.0419235, 0.0346012" \ + "0.0141151, 0.0142466, 0.0141809, 0.0139588, 0.0136527, 0.0130218, 0.0119494", \ + "0.0136907, 0.0139205, 0.014119, 0.0138795, 0.0134179, 0.0128863, 0.0118894", \ + "0.0146358, 0.0142851, 0.0140267, 0.0142379, 0.0135177, 0.0129786, 0.0119255", \ + "0.0180481, 0.015823, 0.0154122, 0.0147579, 0.0145136, 0.0133293, 0.0132245", \ + "0.0270321, 0.0211148, 0.0197767, 0.0184084, 0.0169644, 0.015327, 0.0160078", \ + "0.0467136, 0.036018, 0.0325824, 0.0289482, 0.0252284, 0.0224491, 0.0182587", \ + "0.0874335, 0.0720105, 0.0652954, 0.0576853, 0.0492724, 0.0419241, 0.0346017" \ ); } } @@ -2803,26 +2803,26 @@ library (sg13g2_stdcell_typ_1p50V_25C) { index_1 ("0.0186, 0.0966, 0.174, 0.3294, 0.6408, 1.263, 2.5074"); index_2 ("0.001, 0.0468, 0.078, 0.1296, 0.216, 0.36, 0.6"); values ( \ - "0.00776753, 0.00889397, 0.00891042, 0.00876602, 0.00853723, 0.0078847, 0.00701248", \ - "0.00884907, 0.00845066, 0.00849547, 0.00840302, 0.00817615, 0.00759841, 0.00689038", \ - "0.0109193, 0.0092255, 0.00923338, 0.00887851, 0.00864936, 0.00757355, 0.00669516", \ - "0.0158571, 0.0121578, 0.0110418, 0.0106091, 0.00933657, 0.00817728, 0.00739327", \ - "0.0267443, 0.0199328, 0.0180451, 0.0158256, 0.0137505, 0.0111145, 0.0118983", \ - "0.0482057, 0.0368614, 0.0331933, 0.029203, 0.0249181, 0.0195426, 0.0178761", \ - "0.0936811, 0.0764103, 0.0695061, 0.0622325, 0.0542203, 0.0455227, 0.0356472" \ + "0.00776775, 0.00889677, 0.00890789, 0.00876765, 0.00849933, 0.00788325, 0.00699537", \ + "0.00884677, 0.00846556, 0.00847835, 0.00840772, 0.00827462, 0.0077119, 0.00688636", \ + "0.0109227, 0.00922564, 0.00901262, 0.00888312, 0.00860536, 0.00761955, 0.00667579", \ + "0.015859, 0.0121688, 0.0110717, 0.0105844, 0.00929561, 0.00849803, 0.00737205", \ + "0.0267438, 0.0199346, 0.0180363, 0.0157147, 0.0137961, 0.0111161, 0.0115165", \ + "0.0482094, 0.0368645, 0.033223, 0.0291962, 0.0247957, 0.0195393, 0.016852", \ + "0.0936806, 0.0764091, 0.0695051, 0.0622312, 0.0542201, 0.0455499, 0.0356399" \ ); } fall_power (POWER_7x7ds1) { index_1 ("0.0186, 0.0966, 0.174, 0.3294, 0.6408, 1.263, 2.5074"); index_2 ("0.001, 0.0468, 0.078, 0.1296, 0.216, 0.36, 0.6"); values ( \ - "0.00986852, 0.0114231, 0.0115041, 0.0113234, 0.0110831, 0.0104944, 0.00975687", \ - "0.0108166, 0.0112429, 0.0112467, 0.0115937, 0.0109988, 0.0105788, 0.00960571", \ - "0.0130105, 0.0117829, 0.0117537, 0.01139, 0.0115443, 0.0110584, 0.011055", \ - "0.0177151, 0.0137306, 0.0132751, 0.0128438, 0.0120075, 0.0113731, 0.010119", \ - "0.0283432, 0.0202194, 0.0183399, 0.0169151, 0.0155693, 0.0139801, 0.0113533", \ - "0.0497015, 0.0367802, 0.0324203, 0.0285173, 0.0249158, 0.0213091, 0.0181107", \ - "0.0937872, 0.0751966, 0.0680178, 0.0592123, 0.0507955, 0.0417241, 0.0339052" \ + "0.00987344, 0.0114098, 0.011502, 0.0113138, 0.0110565, 0.0105087, 0.0097476", \ + "0.0108143, 0.0112384, 0.0112218, 0.0115694, 0.0110187, 0.0105986, 0.00973572", \ + "0.0130097, 0.0117812, 0.0117881, 0.0113646, 0.0115782, 0.0110593, 0.0097711", \ + "0.0177152, 0.0137484, 0.0132467, 0.0128412, 0.0119837, 0.0114694, 0.0101366", \ + "0.0283414, 0.0202232, 0.018268, 0.0168983, 0.0157436, 0.0138575, 0.0113645", \ + "0.0496989, 0.036782, 0.0324209, 0.0284786, 0.0246572, 0.0212594, 0.0183922", \ + "0.0936321, 0.0751959, 0.0680183, 0.0592167, 0.0507953, 0.0417231, 0.0342537" \ ); } } @@ -2833,26 +2833,26 @@ library (sg13g2_stdcell_typ_1p50V_25C) { index_1 ("0.0186, 0.0966, 0.174, 0.3294, 0.6408, 1.263, 2.5074"); index_2 ("0.001, 0.0468, 0.078, 0.1296, 0.216, 0.36, 0.6"); values ( \ - "0.00646279, 0.00787459, 0.0079297, 0.00786224, 0.00754249, 0.00692229, 0.00596722", \ - "0.00810477, 0.00764887, 0.00756221, 0.00751438, 0.00718909, 0.0066648, 0.00586507", \ - "0.0104645, 0.00830812, 0.0080666, 0.00775687, 0.00774178, 0.00760151, 0.00583764", \ - "0.0157412, 0.0113115, 0.0101853, 0.00957685, 0.00846298, 0.00721187, 0.00646189", \ - "0.0270613, 0.0192468, 0.0171998, 0.0148351, 0.0128633, 0.0101911, 0.00852579", \ - "0.0490222, 0.0365466, 0.0326206, 0.0284335, 0.0240117, 0.0188614, 0.0161877", \ - "0.0948684, 0.0763192, 0.0693714, 0.0620799, 0.0535123, 0.0443796, 0.0346873" \ + "0.0064652, 0.00787542, 0.00792924, 0.00786176, 0.00754501, 0.00698272, 0.00596379", \ + "0.00810237, 0.00748678, 0.00753654, 0.00749755, 0.00718897, 0.00664569, 0.00590847", \ + "0.0104454, 0.00830702, 0.00804224, 0.007757, 0.00740689, 0.00759136, 0.00593964", \ + "0.0157371, 0.0113098, 0.0102161, 0.00962721, 0.00837228, 0.00740477, 0.00638762", \ + "0.027061, 0.0192618, 0.0171957, 0.0148482, 0.0128458, 0.0101734, 0.00804958", \ + "0.0490206, 0.0365468, 0.0326197, 0.0283997, 0.0240836, 0.0189517, 0.0168508", \ + "0.0948645, 0.0763176, 0.0693703, 0.0620695, 0.0535115, 0.0442027, 0.0348989" \ ); } fall_power (POWER_7x7ds1) { index_1 ("0.0186, 0.0966, 0.174, 0.3294, 0.6408, 1.263, 2.5074"); index_2 ("0.001, 0.0468, 0.078, 0.1296, 0.216, 0.36, 0.6"); values ( \ - "0.00454689, 0.00622745, 0.00618529, 0.00600309, 0.00576079, 0.00520078, 0.00429084", \ - "0.00552837, 0.00597925, 0.00594679, 0.00618084, 0.0058442, 0.00640239, 0.00444337", \ - "0.00779493, 0.00644151, 0.00650342, 0.00613031, 0.00627978, 0.0054463, 0.00508655", \ - "0.0126036, 0.00847141, 0.00812805, 0.00754528, 0.00668939, 0.00615815, 0.00495775", \ - "0.0234073, 0.0150038, 0.013104, 0.0117697, 0.0103522, 0.00871176, 0.00652751", \ - "0.044832, 0.0315872, 0.0273343, 0.0233101, 0.0198412, 0.0163203, 0.013573", \ - "0.0891389, 0.0702306, 0.0630243, 0.0540852, 0.045678, 0.0370202, 0.0293623" \ + "0.00454691, 0.00618325, 0.00624339, 0.00601246, 0.00578253, 0.00520061, 0.00437216", \ + "0.00552968, 0.00602632, 0.00594015, 0.00616038, 0.00577693, 0.00528517, 0.00441378", \ + "0.00779491, 0.00643955, 0.0064923, 0.00619838, 0.00625683, 0.00614007, 0.0044929", \ + "0.0126041, 0.00847105, 0.00811073, 0.00753171, 0.00650426, 0.00605844, 0.0055704", \ + "0.0234082, 0.0150056, 0.0130948, 0.0117539, 0.010464, 0.0085789, 0.00648031", \ + "0.0448378, 0.0315841, 0.027336, 0.0232881, 0.0198426, 0.0163072, 0.0131187", \ + "0.0891378, 0.0702293, 0.0630258, 0.0541655, 0.0456759, 0.0364645, 0.0294672" \ ); } } @@ -2863,26 +2863,26 @@ library (sg13g2_stdcell_typ_1p50V_25C) { index_1 ("0.0186, 0.0966, 0.174, 0.3294, 0.6408, 1.263, 2.5074"); index_2 ("0.001, 0.0468, 0.078, 0.1296, 0.216, 0.36, 0.6"); values ( \ - "0.00651209, 0.00788025, 0.00811929, 0.0078627, 0.00754912, 0.00697296, 0.00678655", \ - "0.00835058, 0.00765451, 0.0075259, 0.00750959, 0.00728947, 0.0067388, 0.00659972", \ - "0.010926, 0.00846298, 0.00823366, 0.00778476, 0.00801253, 0.00697228, 0.0064206", \ - "0.0166821, 0.0118754, 0.0107578, 0.00967039, 0.008967, 0.00750667, 0.00702894", \ - "0.0286216, 0.0205718, 0.0183236, 0.0160238, 0.0133569, 0.0113441, 0.00965974", \ - "0.0525952, 0.0393297, 0.0353794, 0.030927, 0.0258194, 0.02019, 0.0160503", \ - "0.101865, 0.0825949, 0.0752113, 0.0668459, 0.057947, 0.0484165, 0.0386064" \ + "0.00651298, 0.00786917, 0.00794397, 0.00786739, 0.00758224, 0.00696904, 0.00678738", \ + "0.00833677, 0.00765482, 0.00753626, 0.00836285, 0.00728284, 0.00676807, 0.00666823", \ + "0.0109281, 0.00849279, 0.00823944, 0.00777911, 0.00804311, 0.00679895, 0.00669363", \ + "0.0166863, 0.0118579, 0.0107269, 0.00977342, 0.00918188, 0.00747532, 0.00701842", \ + "0.0286232, 0.0205386, 0.0183235, 0.016024, 0.013392, 0.0112958, 0.00950168", \ + "0.0525939, 0.0393294, 0.0353827, 0.0309248, 0.0258195, 0.0202044, 0.0160217", \ + "0.101864, 0.082596, 0.0752091, 0.0670527, 0.0579464, 0.0484171, 0.0385856" \ ); } fall_power (POWER_7x7ds1) { index_1 ("0.0186, 0.0966, 0.174, 0.3294, 0.6408, 1.263, 2.5074"); index_2 ("0.001, 0.0468, 0.078, 0.1296, 0.216, 0.36, 0.6"); values ( \ - "0.00425944, 0.00589943, 0.00585129, 0.0057879, 0.00551654, 0.00496083, 0.00400409", \ - "0.00553201, 0.00566156, 0.00556785, 0.00592632, 0.00543008, 0.00539558, 0.0040918", \ - "0.00792993, 0.0061778, 0.00615904, 0.00582631, 0.00594235, 0.00545235, 0.00457789", \ - "0.0133195, 0.00852418, 0.00802482, 0.00745726, 0.00641109, 0.00578983, 0.00502756", \ - "0.0246484, 0.0156939, 0.0135477, 0.0119051, 0.0105262, 0.00881705, 0.00599016", \ - "0.0481364, 0.0338446, 0.0292295, 0.0247078, 0.0209042, 0.0169336, 0.0140776", \ - "0.0959613, 0.075625, 0.0676038, 0.05851, 0.0489082, 0.039809, 0.0310294" \ + "0.00425284, 0.00590838, 0.00592695, 0.00577825, 0.00550226, 0.00501842, 0.00412068", \ + "0.00551198, 0.00562773, 0.00556647, 0.00592686, 0.00541768, 0.00536584, 0.00431309", \ + "0.00792866, 0.00617022, 0.00616631, 0.00581389, 0.00594708, 0.00503818, 0.00408684", \ + "0.0133159, 0.00853018, 0.00789952, 0.00748878, 0.00636291, 0.00584696, 0.00483343", \ + "0.0246473, 0.0156956, 0.0135557, 0.0118936, 0.0105477, 0.00872006, 0.00591253", \ + "0.0481327, 0.0338068, 0.0292301, 0.0246833, 0.0209028, 0.0169355, 0.0138855", \ + "0.0959596, 0.0756252, 0.0675949, 0.0584537, 0.0489324, 0.0398148, 0.0312494" \ ); } } @@ -2892,26 +2892,26 @@ library (sg13g2_stdcell_typ_1p50V_25C) { index_1 ("0.0186, 0.0966, 0.174, 0.3294, 0.6408, 1.263, 2.5074"); index_2 ("0.001, 0.0468, 0.078, 0.1296, 0.216, 0.36, 0.6"); values ( \ - "0.00776753, 0.00889397, 0.00891042, 0.00876602, 0.00853723, 0.0078847, 0.00701248", \ - "0.00884907, 0.00845066, 0.00849547, 0.00840302, 0.00817615, 0.00759841, 0.00689038", \ - "0.0109193, 0.0092255, 0.00923338, 0.00887851, 0.00864936, 0.00757355, 0.00669516", \ - "0.0158571, 0.0121578, 0.0110418, 0.0106091, 0.00933657, 0.00817728, 0.00739327", \ - "0.0267443, 0.0199328, 0.0180451, 0.0158256, 0.0137505, 0.0111145, 0.0118983", \ - "0.0482057, 0.0368614, 0.0331933, 0.029203, 0.0249181, 0.0195426, 0.0178761", \ - "0.0936811, 0.0764103, 0.0695061, 0.0622325, 0.0542203, 0.0455227, 0.0356472" \ + "0.00776775, 0.00889677, 0.00890789, 0.00876765, 0.00849933, 0.00788325, 0.00699537", \ + "0.00884677, 0.00846556, 0.00847835, 0.00840772, 0.00827462, 0.0077119, 0.00688636", \ + "0.0109227, 0.00922564, 0.00901262, 0.00888312, 0.00860536, 0.00761955, 0.00667579", \ + "0.015859, 0.0121688, 0.0110717, 0.0105844, 0.00929561, 0.00849803, 0.00737205", \ + "0.0267438, 0.0199346, 0.0180363, 0.0157147, 0.0137961, 0.0111161, 0.0115165", \ + "0.0482094, 0.0368645, 0.033223, 0.0291962, 0.0247957, 0.0195393, 0.016852", \ + "0.0936806, 0.0764091, 0.0695051, 0.0622312, 0.0542201, 0.0455499, 0.0356399" \ ); } fall_power (POWER_7x7ds1) { index_1 ("0.0186, 0.0966, 0.174, 0.3294, 0.6408, 1.263, 2.5074"); index_2 ("0.001, 0.0468, 0.078, 0.1296, 0.216, 0.36, 0.6"); values ( \ - "0.00425944, 0.00589943, 0.00585129, 0.0057879, 0.00551654, 0.00496083, 0.00400409", \ - "0.00553201, 0.00566156, 0.00556785, 0.00592632, 0.00543008, 0.00539558, 0.0040918", \ - "0.00792993, 0.0061778, 0.00615904, 0.00582631, 0.00594235, 0.00545235, 0.00457789", \ - "0.0133195, 0.00852418, 0.00802482, 0.00745726, 0.00641109, 0.00578983, 0.00502756", \ - "0.0246484, 0.0156939, 0.0135477, 0.0119051, 0.0105262, 0.00881705, 0.00599016", \ - "0.0481364, 0.0338446, 0.0292295, 0.0247078, 0.0209042, 0.0169336, 0.0140776", \ - "0.0959613, 0.075625, 0.0676038, 0.05851, 0.0489082, 0.039809, 0.0310294" \ + "0.00425284, 0.00590838, 0.00592695, 0.00577825, 0.00550226, 0.00501842, 0.00412068", \ + "0.00551198, 0.00562773, 0.00556647, 0.00592686, 0.00541768, 0.00536584, 0.00431309", \ + "0.00792866, 0.00617022, 0.00616631, 0.00581389, 0.00594708, 0.00503818, 0.00408684", \ + "0.0133159, 0.00853018, 0.00789952, 0.00748878, 0.00636291, 0.00584696, 0.00483343", \ + "0.0246473, 0.0156956, 0.0135557, 0.0118936, 0.0105477, 0.00872006, 0.00591253", \ + "0.0481327, 0.0338068, 0.0292301, 0.0246833, 0.0209028, 0.0169355, 0.0138855", \ + "0.0959596, 0.0756252, 0.0675949, 0.0584537, 0.0489324, 0.0398148, 0.0312494" \ ); } } @@ -2919,29 +2919,29 @@ library (sg13g2_stdcell_typ_1p50V_25C) { pin (A1) { direction : "input"; max_transition : 2.5074; - capacitance : 0.00608436; - rise_capacitance : 0.00589754; - rise_capacitance_range (0.00589754, 0.00589754); - fall_capacitance : 0.00627117; - fall_capacitance_range (0.00627117, 0.00627117); + capacitance : 0.00608437; + rise_capacitance : 0.00589759; + rise_capacitance_range (0.00541239, 0.0066357); + fall_capacitance : 0.00627116; + fall_capacitance_range (0.00526356, 0.00711568); } pin (A2) { direction : "input"; max_transition : 2.5074; - capacitance : 0.00645313; - rise_capacitance : 0.00653776; - rise_capacitance_range (0.00653776, 0.00653776); - fall_capacitance : 0.00636849; - fall_capacitance_range (0.00636849, 0.00636849); + capacitance : 0.00645327; + rise_capacitance : 0.00653773; + rise_capacitance_range (0.00557977, 0.00724112); + fall_capacitance : 0.00636882; + fall_capacitance_range (0.00555237, 0.00695597); } pin (B1) { direction : "input"; max_transition : 2.5074; - capacitance : 0.00584411; - rise_capacitance : 0.00604802; - rise_capacitance_range (0.00604802, 0.00604802); - fall_capacitance : 0.00564019; - fall_capacitance_range (0.00564019, 0.00564019); + capacitance : 0.00584409; + rise_capacitance : 0.00604796; + rise_capacitance_range (0.00485421, 0.00815708); + fall_capacitance : 0.00564023; + fall_capacitance_range (0.00517989, 0.00632082); } } cell (sg13g2_a221oi_1) { @@ -5010,113 +5010,113 @@ library (sg13g2_stdcell_typ_1p50V_25C) { max_transition : 2.5074; capacitance : 0.00310445; rise_capacitance : 0.0030047; - rise_capacitance_range (0.0030047, 0.0030047); + rise_capacitance_range (0.00282314, 0.00334036); fall_capacitance : 0.0032042; - fall_capacitance_range (0.0032042, 0.0032042); + fall_capacitance_range (0.00272807, 0.00361983); } pin (A2) { direction : "input"; max_transition : 2.5074; capacitance : 0.00319566; rise_capacitance : 0.00323008; - rise_capacitance_range (0.00323008, 0.00323008); + rise_capacitance_range (0.00276859, 0.00353522); fall_capacitance : 0.00316124; - fall_capacitance_range (0.00316124, 0.00316124); + fall_capacitance_range (0.00276794, 0.00349429); } pin (B1) { direction : "input"; max_transition : 2.5074; capacitance : 0.00304544; rise_capacitance : 0.00299824; - rise_capacitance_range (0.00299824, 0.00299824); + rise_capacitance_range (0.00264241, 0.00353187); fall_capacitance : 0.00309264; - fall_capacitance_range (0.00309264, 0.00309264); + fall_capacitance_range (0.0026078, 0.0034531); } pin (B2) { direction : "input"; max_transition : 2.5074; capacitance : 0.003194; rise_capacitance : 0.00328023; - rise_capacitance_range (0.00328023, 0.00328023); + rise_capacitance_range (0.00268932, 0.00375676); fall_capacitance : 0.00310776; - fall_capacitance_range (0.00310776, 0.00310776); + fall_capacitance_range (0.00270397, 0.00339556); } pin (C1) { direction : "input"; max_transition : 2.5074; capacitance : 0.00295319; rise_capacitance : 0.00306981; - rise_capacitance_range (0.00306981, 0.00306981); + rise_capacitance_range (0.00253254, 0.00406421); fall_capacitance : 0.00283656; - fall_capacitance_range (0.00283656, 0.00283656); + fall_capacitance_range (0.00264409, 0.00306373); } } cell (sg13g2_a22oi_1) { area : 10.8486; cell_footprint : "a22oi"; - cell_leakage_power : 432.964; + cell_leakage_power : 432.995; leakage_power () { - value : 257.515; + value : 257.546; when : "!A1&!A2&!B1&!B2&Y"; } leakage_power () { - value : 221.679; + value : 221.71; when : "!A1&!A2&!B1&B2&Y"; } leakage_power () { - value : 361.539; + value : 361.57; when : "!A1&!A2&B1&!B2&Y"; } leakage_power () { - value : 600.799; + value : 600.83; when : "!A1&!A2&B1&B2&!Y"; } leakage_power () { - value : 361.651; + value : 361.682; when : "!A1&A2&!B1&!B2&Y"; } leakage_power () { - value : 325.815; + value : 325.846; when : "!A1&A2&!B1&B2&Y"; } leakage_power () { - value : 465.675; + value : 465.706; when : "!A1&A2&B1&!B2&Y"; } leakage_power () { - value : 681.134; + value : 681.165; when : "!A1&A2&B1&B2&!Y"; } leakage_power () { - value : 221.65; + value : 221.681; when : "A1&!A2&!B1&!B2&Y"; } leakage_power () { - value : 185.814; + value : 185.845; when : "A1&!A2&!B1&B2&Y"; } leakage_power () { - value : 325.674; + value : 325.705; when : "A1&!A2&B1&!B2&Y"; } leakage_power () { - value : 680.994; + value : 681.025; when : "A1&!A2&B1&B2&!Y"; } leakage_power () { - value : 442.296; + value : 442.328; when : "A1&A2&!B1&!B2&!Y"; } leakage_power () { - value : 589.102; + value : 589.134; when : "A1&A2&!B1&B2&!Y"; } leakage_power () { - value : 589.101; + value : 589.132; when : "A1&A2&B1&!B2&!Y"; } leakage_power () { - value : 616.99; + value : 617.021; when : "A1&A2&B1&B2&!Y"; } pin (Y) { @@ -5134,52 +5134,52 @@ library (sg13g2_stdcell_typ_1p50V_25C) { index_1 ("0.0186, 0.0966, 0.174, 0.3294, 0.6408, 1.263, 2.5074"); index_2 ("0.001, 0.0234, 0.039, 0.0648, 0.108, 0.18, 0.3"); values ( \ - "0.0380927, 0.129935, 0.192649, 0.295971, 0.468898, 0.756964, 1.23705", \ - "0.0537927, 0.153551, 0.216664, 0.320357, 0.493466, 0.78166, 1.2617", \ - "0.0619041, 0.172867, 0.238281, 0.342723, 0.516007, 0.80543, 1.2847", \ - "0.070069, 0.202523, 0.274593, 0.384305, 0.560385, 0.849084, 1.32986", \ - "0.0827029, 0.246417, 0.331531, 0.454515, 0.642948, 0.93882, 1.42027", \ - "0.099948, 0.307426, 0.411253, 0.559378, 0.772829, 1.09646, 1.59638", \ - "0.117434, 0.391101, 0.519386, 0.702777, 0.96619, 1.33841, 1.8984" \ + "0.0380932, 0.129934, 0.19255, 0.295897, 0.46891, 0.756993, 1.23705", \ + "0.0537775, 0.15356, 0.216675, 0.320356, 0.493455, 0.781641, 1.26169", \ + "0.0619038, 0.172883, 0.238275, 0.342726, 0.516005, 0.804615, 1.28469", \ + "0.0700687, 0.202522, 0.274592, 0.384304, 0.560382, 0.84904, 1.32981", \ + "0.0827024, 0.246416, 0.33153, 0.454513, 0.642946, 0.938793, 1.42035", \ + "0.0999469, 0.307424, 0.411252, 0.559376, 0.772825, 1.09646, 1.59637", \ + "0.117432, 0.391099, 0.519383, 0.702774, 0.966186, 1.33841, 1.89838" \ ); } rise_transition (TIMING_DELAY_7x7ds1) { index_1 ("0.0186, 0.0966, 0.174, 0.3294, 0.6408, 1.263, 2.5074"); index_2 ("0.001, 0.0234, 0.039, 0.0648, 0.108, 0.18, 0.3"); values ( \ - "0.0251084, 0.154565, 0.244886, 0.394153, 0.644047, 1.0605, 1.75482", \ - "0.0348367, 0.157425, 0.245861, 0.394244, 0.644048, 1.06051, 1.75483", \ - "0.0451684, 0.166626, 0.251979, 0.396974, 0.646618, 1.06156, 1.75486", \ - "0.0644617, 0.189726, 0.272855, 0.412365, 0.652668, 1.06325, 1.75811", \ - "0.0982489, 0.234058, 0.319861, 0.457584, 0.687837, 1.08413, 1.76291", \ - "0.150672, 0.309193, 0.403984, 0.549335, 0.779544, 1.16275, 1.8159", \ - "0.237905, 0.432204, 0.541834, 0.706721, 0.959056, 1.34652, 1.98771" \ + "0.0251088, 0.154564, 0.244807, 0.39412, 0.644045, 1.06062, 1.75481", \ + "0.0348176, 0.15744, 0.24586, 0.394241, 0.644046, 1.06063, 1.75482", \ + "0.0451682, 0.166644, 0.251939, 0.396918, 0.646614, 1.06083, 1.75485", \ + "0.0644615, 0.189725, 0.272854, 0.412364, 0.652664, 1.06269, 1.75821", \ + "0.0982487, 0.234058, 0.31986, 0.457582, 0.687831, 1.08423, 1.76291", \ + "0.150672, 0.309193, 0.403983, 0.549334, 0.779034, 1.16275, 1.81589", \ + "0.237905, 0.432204, 0.541831, 0.706719, 0.959054, 1.34651, 1.9877" \ ); } cell_fall (TIMING_DELAY_7x7ds1) { index_1 ("0.0186, 0.0966, 0.174, 0.3294, 0.6408, 1.263, 2.5074"); index_2 ("0.001, 0.0234, 0.039, 0.0648, 0.108, 0.18, 0.3"); values ( \ - "0.0316759, 0.0960366, 0.139244, 0.210278, 0.328915, 0.526564, 0.855649", \ - "0.0521313, 0.130337, 0.175104, 0.246571, 0.365201, 0.56258, 0.89205", \ - "0.0640862, 0.156675, 0.206406, 0.281696, 0.401797, 0.599346, 0.928349", \ - "0.0804032, 0.195144, 0.254414, 0.340678, 0.469759, 0.671272, 1.00037", \ - "0.102925, 0.250437, 0.324031, 0.429533, 0.581101, 0.804329, 1.14611", \ - "0.132661, 0.324381, 0.420672, 0.552762, 0.74205, 1.0098, 1.3985", \ - "0.172271, 0.421008, 0.547578, 0.721862, 0.962917, 1.29959, 1.77456" \ + "0.0316784, 0.0960387, 0.139234, 0.210243, 0.328921, 0.526585, 0.855858", \ + "0.0521293, 0.130333, 0.175063, 0.246556, 0.365175, 0.562615, 0.891772", \ + "0.0640869, 0.156675, 0.206408, 0.281701, 0.401789, 0.599353, 0.928384", \ + "0.0804038, 0.195146, 0.254415, 0.340681, 0.469766, 0.671248, 1.00038", \ + "0.102926, 0.250453, 0.324012, 0.429537, 0.581105, 0.804336, 1.14604", \ + "0.132662, 0.324383, 0.420675, 0.552765, 0.742055, 1.00981, 1.39851", \ + "0.172274, 0.421012, 0.547582, 0.721867, 0.962925, 1.29959, 1.77457" \ ); } fall_transition (TIMING_DELAY_7x7ds1) { index_1 ("0.0186, 0.0966, 0.174, 0.3294, 0.6408, 1.263, 2.5074"); index_2 ("0.001, 0.0234, 0.039, 0.0648, 0.108, 0.18, 0.3"); values ( \ - "0.0246234, 0.107451, 0.165488, 0.261461, 0.422415, 0.689852, 1.13559", \ - "0.039015, 0.117571, 0.171524, 0.263923, 0.422678, 0.689853, 1.13605", \ - "0.0510201, 0.134522, 0.18733, 0.275514, 0.428602, 0.693233, 1.13606", \ - "0.0707063, 0.166364, 0.221719, 0.308987, 0.4546, 0.705773, 1.13969", \ - "0.102724, 0.221444, 0.282945, 0.377315, 0.524946, 0.765816, 1.17792", \ - "0.15411, 0.31419, 0.38594, 0.494552, 0.654329, 0.906148, 1.30871", \ - "0.240289, 0.459546, 0.557903, 0.688311, 0.876956, 1.15499, 1.5867" \ + "0.0246178, 0.107445, 0.165486, 0.26148, 0.422422, 0.689757, 1.13613", \ + "0.0390989, 0.117565, 0.171514, 0.263715, 0.422682, 0.68983, 1.13614", \ + "0.05102, 0.134522, 0.187332, 0.275579, 0.42833, 0.693238, 1.13615", \ + "0.0707066, 0.166364, 0.221913, 0.308991, 0.454787, 0.705677, 1.14003", \ + "0.102724, 0.221411, 0.282936, 0.377315, 0.524952, 0.765856, 1.1779", \ + "0.15411, 0.31419, 0.385942, 0.494559, 0.654396, 0.906157, 1.30873", \ + "0.240289, 0.459547, 0.557906, 0.688314, 0.876963, 1.155, 1.58671" \ ); } } @@ -5191,52 +5191,52 @@ library (sg13g2_stdcell_typ_1p50V_25C) { index_1 ("0.0186, 0.0966, 0.174, 0.3294, 0.6408, 1.263, 2.5074"); index_2 ("0.001, 0.0234, 0.039, 0.0648, 0.108, 0.18, 0.3"); values ( \ - "0.0380927, 0.129935, 0.192649, 0.295971, 0.468898, 0.756964, 1.23705", \ - "0.0537927, 0.153551, 0.216664, 0.320357, 0.493466, 0.78166, 1.2617", \ - "0.0619041, 0.172867, 0.238281, 0.342723, 0.516007, 0.80543, 1.2847", \ - "0.070069, 0.202523, 0.274593, 0.384305, 0.560385, 0.849084, 1.32986", \ - "0.0827029, 0.246417, 0.331531, 0.454515, 0.642948, 0.93882, 1.42027", \ - "0.099948, 0.307426, 0.411253, 0.559378, 0.772829, 1.09646, 1.59638", \ - "0.117434, 0.391101, 0.519386, 0.702777, 0.96619, 1.33841, 1.8984" \ + "0.0380932, 0.129934, 0.19255, 0.295897, 0.46891, 0.756993, 1.23705", \ + "0.0537775, 0.15356, 0.216675, 0.320356, 0.493455, 0.781641, 1.26169", \ + "0.0619038, 0.172883, 0.238275, 0.342726, 0.516005, 0.804615, 1.28469", \ + "0.0700687, 0.202522, 0.274592, 0.384304, 0.560382, 0.84904, 1.32981", \ + "0.0827024, 0.246416, 0.33153, 0.454513, 0.642946, 0.938793, 1.42035", \ + "0.0999469, 0.307424, 0.411252, 0.559376, 0.772825, 1.09646, 1.59637", \ + "0.117432, 0.391099, 0.519383, 0.702774, 0.966186, 1.33841, 1.89838" \ ); } rise_transition (TIMING_DELAY_7x7ds1) { index_1 ("0.0186, 0.0966, 0.174, 0.3294, 0.6408, 1.263, 2.5074"); index_2 ("0.001, 0.0234, 0.039, 0.0648, 0.108, 0.18, 0.3"); values ( \ - "0.0251084, 0.154565, 0.244886, 0.394153, 0.644047, 1.0605, 1.75482", \ - "0.0348367, 0.157425, 0.245861, 0.394244, 0.644048, 1.06051, 1.75483", \ - "0.0451684, 0.166626, 0.251979, 0.396974, 0.646618, 1.06156, 1.75486", \ - "0.0644617, 0.189726, 0.272855, 0.412365, 0.652668, 1.06325, 1.75811", \ - "0.0982489, 0.234058, 0.319861, 0.457584, 0.687837, 1.08413, 1.76291", \ - "0.150672, 0.309193, 0.403984, 0.549335, 0.779544, 1.16275, 1.8159", \ - "0.237905, 0.432204, 0.541834, 0.706721, 0.959056, 1.34652, 1.98771" \ + "0.0251088, 0.154564, 0.244807, 0.39412, 0.644045, 1.06062, 1.75481", \ + "0.0348176, 0.15744, 0.24586, 0.394241, 0.644046, 1.06063, 1.75482", \ + "0.0451682, 0.166644, 0.251939, 0.396918, 0.646614, 1.06083, 1.75485", \ + "0.0644615, 0.189725, 0.272854, 0.412364, 0.652664, 1.06269, 1.75821", \ + "0.0982487, 0.234058, 0.31986, 0.457582, 0.687831, 1.08423, 1.76291", \ + "0.150672, 0.309193, 0.403983, 0.549334, 0.779034, 1.16275, 1.81589", \ + "0.237905, 0.432204, 0.541831, 0.706719, 0.959054, 1.34651, 1.9877" \ ); } cell_fall (TIMING_DELAY_7x7ds1) { index_1 ("0.0186, 0.0966, 0.174, 0.3294, 0.6408, 1.263, 2.5074"); index_2 ("0.001, 0.0234, 0.039, 0.0648, 0.108, 0.18, 0.3"); values ( \ - "0.0316759, 0.0960366, 0.139244, 0.210278, 0.328915, 0.526564, 0.855649", \ - "0.0521313, 0.130337, 0.175104, 0.246571, 0.365201, 0.56258, 0.89205", \ - "0.0640862, 0.156675, 0.206406, 0.281696, 0.401797, 0.599346, 0.928349", \ - "0.0804032, 0.195144, 0.254414, 0.340678, 0.469759, 0.671272, 1.00037", \ - "0.102925, 0.250437, 0.324031, 0.429533, 0.581101, 0.804329, 1.14611", \ - "0.132661, 0.324381, 0.420672, 0.552762, 0.74205, 1.0098, 1.3985", \ - "0.172271, 0.421008, 0.547578, 0.721862, 0.962917, 1.29959, 1.77456" \ + "0.0316784, 0.0960387, 0.139234, 0.210243, 0.328921, 0.526585, 0.855858", \ + "0.0521293, 0.130333, 0.175063, 0.246556, 0.365175, 0.562615, 0.891772", \ + "0.0640869, 0.156675, 0.206408, 0.281701, 0.401789, 0.599353, 0.928384", \ + "0.0804038, 0.195146, 0.254415, 0.340681, 0.469766, 0.671248, 1.00038", \ + "0.102926, 0.250453, 0.324012, 0.429537, 0.581105, 0.804336, 1.14604", \ + "0.132662, 0.324383, 0.420675, 0.552765, 0.742055, 1.00981, 1.39851", \ + "0.172274, 0.421012, 0.547582, 0.721867, 0.962925, 1.29959, 1.77457" \ ); } fall_transition (TIMING_DELAY_7x7ds1) { index_1 ("0.0186, 0.0966, 0.174, 0.3294, 0.6408, 1.263, 2.5074"); index_2 ("0.001, 0.0234, 0.039, 0.0648, 0.108, 0.18, 0.3"); values ( \ - "0.0246234, 0.107451, 0.165488, 0.261461, 0.422415, 0.689852, 1.13559", \ - "0.039015, 0.117571, 0.171524, 0.263923, 0.422678, 0.689853, 1.13605", \ - "0.0510201, 0.134522, 0.18733, 0.275514, 0.428602, 0.693233, 1.13606", \ - "0.0707063, 0.166364, 0.221719, 0.308987, 0.4546, 0.705773, 1.13969", \ - "0.102724, 0.221444, 0.282945, 0.377315, 0.524946, 0.765816, 1.17792", \ - "0.15411, 0.31419, 0.38594, 0.494552, 0.654329, 0.906148, 1.30871", \ - "0.240289, 0.459546, 0.557903, 0.688311, 0.876956, 1.15499, 1.5867" \ + "0.0246178, 0.107445, 0.165486, 0.26148, 0.422422, 0.689757, 1.13613", \ + "0.0390989, 0.117565, 0.171514, 0.263715, 0.422682, 0.68983, 1.13614", \ + "0.05102, 0.134522, 0.187332, 0.275579, 0.42833, 0.693238, 1.13615", \ + "0.0707066, 0.166364, 0.221913, 0.308991, 0.454787, 0.705677, 1.14003", \ + "0.102724, 0.221411, 0.282936, 0.377315, 0.524952, 0.765856, 1.1779", \ + "0.15411, 0.31419, 0.385942, 0.494559, 0.654396, 0.906157, 1.30873", \ + "0.240289, 0.459547, 0.557906, 0.688314, 0.876963, 1.155, 1.58671" \ ); } } @@ -5250,52 +5250,52 @@ library (sg13g2_stdcell_typ_1p50V_25C) { index_1 ("0.0186, 0.0966, 0.174, 0.3294, 0.6408, 1.263, 2.5074"); index_2 ("0.001, 0.0234, 0.039, 0.0648, 0.108, 0.18, 0.3"); values ( \ - "0.0437355, 0.134341, 0.196622, 0.299596, 0.47186, 0.758655, 1.2368", \ - "0.0617895, 0.158827, 0.221394, 0.32443, 0.496683, 0.783594, 1.26157", \ - "0.0716843, 0.178922, 0.2435, 0.347204, 0.519508, 0.80631, 1.28477", \ - "0.083031, 0.209924, 0.280698, 0.389515, 0.564353, 0.851662, 1.32959", \ - "0.101778, 0.256444, 0.339333, 0.460732, 0.647959, 0.941999, 1.42165", \ - "0.130551, 0.322657, 0.423992, 0.568304, 0.782058, 1.1007, 1.59885", \ - "0.170312, 0.418709, 0.542398, 0.720485, 0.977417, 1.35198, 1.90151" \ + "0.0437336, 0.134342, 0.196606, 0.299596, 0.47166, 0.758658, 1.23682", \ + "0.0617343, 0.158834, 0.221436, 0.324428, 0.4967, 0.783595, 1.26157", \ + "0.0716845, 0.178923, 0.243506, 0.347206, 0.519543, 0.806771, 1.28477", \ + "0.0830312, 0.209925, 0.280698, 0.389516, 0.56435, 0.851678, 1.33041", \ + "0.101778, 0.256445, 0.339334, 0.460733, 0.647962, 0.94201, 1.42161", \ + "0.130551, 0.322657, 0.423993, 0.568306, 0.782061, 1.1007, 1.59886", \ + "0.170312, 0.418709, 0.5424, 0.720487, 0.97742, 1.35199, 1.90168" \ ); } rise_transition (TIMING_DELAY_7x7ds1) { index_1 ("0.0186, 0.0966, 0.174, 0.3294, 0.6408, 1.263, 2.5074"); index_2 ("0.001, 0.0234, 0.039, 0.0648, 0.108, 0.18, 0.3"); values ( \ - "0.0310995, 0.160492, 0.250487, 0.399113, 0.648098, 1.06314, 1.75422", \ - "0.0400129, 0.163129, 0.25135, 0.399117, 0.64819, 1.06315, 1.75423", \ - "0.0501159, 0.17205, 0.25734, 0.40187, 0.650295, 1.06316, 1.75425", \ - "0.0689173, 0.195035, 0.277878, 0.417176, 0.65653, 1.0651, 1.75426", \ - "0.100466, 0.238908, 0.324429, 0.461444, 0.691768, 1.08662, 1.76242", \ - "0.149802, 0.312489, 0.408341, 0.553486, 0.784635, 1.16466, 1.81562", \ - "0.23057, 0.430969, 0.540677, 0.707779, 0.956025, 1.35183, 1.98444" \ + "0.0310993, 0.16049, 0.25036, 0.399115, 0.648071, 1.06314, 1.75422", \ + "0.0399782, 0.163183, 0.251391, 0.399116, 0.648196, 1.06315, 1.75423", \ + "0.050116, 0.172051, 0.257307, 0.401876, 0.651029, 1.06316, 1.75426", \ + "0.0689174, 0.195036, 0.278104, 0.417179, 0.656538, 1.06482, 1.75662", \ + "0.100466, 0.238909, 0.32443, 0.461445, 0.691766, 1.0865, 1.76253", \ + "0.149802, 0.312491, 0.408342, 0.553489, 0.784638, 1.16467, 1.81561", \ + "0.230571, 0.43097, 0.540683, 0.707781, 0.956028, 1.35183, 1.98475" \ ); } cell_fall (TIMING_DELAY_7x7ds1) { index_1 ("0.0186, 0.0966, 0.174, 0.3294, 0.6408, 1.263, 2.5074"); index_2 ("0.001, 0.0234, 0.039, 0.0648, 0.108, 0.18, 0.3"); values ( \ - "0.0338939, 0.098085, 0.141244, 0.212314, 0.330943, 0.528678, 0.857706", \ - "0.0515252, 0.12502, 0.169346, 0.240818, 0.359581, 0.55722, 0.88662", \ - "0.0618811, 0.146242, 0.193867, 0.26792, 0.387812, 0.585732, 0.915015", \ - "0.0754956, 0.178876, 0.233464, 0.314682, 0.440795, 0.641615, 0.971312", \ - "0.0937957, 0.227251, 0.293511, 0.388983, 0.530358, 0.745417, 1.08409", \ - "0.116885, 0.29167, 0.378385, 0.497218, 0.666655, 0.914011, 1.284", \ - "0.144107, 0.371757, 0.486908, 0.645657, 0.862609, 1.16273, 1.59735" \ + "0.0338937, 0.0980881, 0.141288, 0.212327, 0.330947, 0.528686, 0.857716", \ + "0.0515102, 0.125016, 0.169337, 0.240848, 0.359574, 0.55725, 0.886615", \ + "0.0618816, 0.146242, 0.193869, 0.267929, 0.387821, 0.585742, 0.915031", \ + "0.0754963, 0.178877, 0.233467, 0.314684, 0.4408, 0.641624, 0.971403", \ + "0.0937967, 0.227253, 0.293514, 0.388986, 0.530364, 0.745381, 1.08408", \ + "0.116886, 0.291673, 0.378473, 0.497223, 0.666662, 0.914018, 1.28401", \ + "0.144109, 0.371761, 0.486913, 0.645663, 0.862607, 1.16274, 1.59714" \ ); } fall_transition (TIMING_DELAY_7x7ds1) { index_1 ("0.0186, 0.0966, 0.174, 0.3294, 0.6408, 1.263, 2.5074"); index_2 ("0.001, 0.0234, 0.039, 0.0648, 0.108, 0.18, 0.3"); values ( \ - "0.0241373, 0.107323, 0.165436, 0.261643, 0.422416, 0.689917, 1.13592", \ - "0.0341291, 0.113612, 0.169247, 0.262849, 0.422417, 0.689918, 1.13605", \ - "0.0445582, 0.124942, 0.17919, 0.270027, 0.426116, 0.690825, 1.13616", \ - "0.0630064, 0.148614, 0.202801, 0.292085, 0.442371, 0.699592, 1.13828", \ - "0.0935516, 0.193735, 0.250263, 0.340285, 0.489494, 0.737973, 1.16243", \ - "0.141117, 0.273912, 0.338286, 0.434684, 0.586779, 0.836095, 1.24736", \ - "0.218994, 0.40146, 0.488035, 0.603148, 0.767111, 1.02628, 1.44231" \ + "0.0241459, 0.107311, 0.165511, 0.261654, 0.422422, 0.689927, 1.13555", \ + "0.0341026, 0.113612, 0.169216, 0.262849, 0.422423, 0.689928, 1.13606", \ + "0.0445587, 0.124938, 0.179191, 0.27003, 0.426124, 0.690836, 1.13617", \ + "0.0630069, 0.148616, 0.20276, 0.29212, 0.442376, 0.699721, 1.13877", \ + "0.093552, 0.193737, 0.250265, 0.340289, 0.489499, 0.737914, 1.16203", \ + "0.141119, 0.273913, 0.337807, 0.434689, 0.586773, 0.836104, 1.24739", \ + "0.218995, 0.401462, 0.488038, 0.603153, 0.767099, 1.02629, 1.44234" \ ); } } @@ -5307,52 +5307,52 @@ library (sg13g2_stdcell_typ_1p50V_25C) { index_1 ("0.0186, 0.0966, 0.174, 0.3294, 0.6408, 1.263, 2.5074"); index_2 ("0.001, 0.0234, 0.039, 0.0648, 0.108, 0.18, 0.3"); values ( \ - "0.0437355, 0.134341, 0.196622, 0.299596, 0.47186, 0.758655, 1.2368", \ - "0.0617895, 0.158827, 0.221394, 0.32443, 0.496683, 0.783594, 1.26157", \ - "0.0716843, 0.178922, 0.2435, 0.347204, 0.519508, 0.80631, 1.28477", \ - "0.083031, 0.209924, 0.280698, 0.389515, 0.564353, 0.851662, 1.32959", \ - "0.101778, 0.256444, 0.339333, 0.460732, 0.647959, 0.941999, 1.42165", \ - "0.130551, 0.322657, 0.423992, 0.568304, 0.782058, 1.1007, 1.59885", \ - "0.170312, 0.418709, 0.542398, 0.720485, 0.977417, 1.35198, 1.90151" \ + "0.0437336, 0.134342, 0.196606, 0.299596, 0.47166, 0.758658, 1.23682", \ + "0.0617343, 0.158834, 0.221436, 0.324428, 0.4967, 0.783595, 1.26157", \ + "0.0716845, 0.178923, 0.243506, 0.347206, 0.519543, 0.806771, 1.28477", \ + "0.0830312, 0.209925, 0.280698, 0.389516, 0.56435, 0.851678, 1.33041", \ + "0.101778, 0.256445, 0.339334, 0.460733, 0.647962, 0.94201, 1.42161", \ + "0.130551, 0.322657, 0.423993, 0.568306, 0.782061, 1.1007, 1.59886", \ + "0.170312, 0.418709, 0.5424, 0.720487, 0.97742, 1.35199, 1.90168" \ ); } rise_transition (TIMING_DELAY_7x7ds1) { index_1 ("0.0186, 0.0966, 0.174, 0.3294, 0.6408, 1.263, 2.5074"); index_2 ("0.001, 0.0234, 0.039, 0.0648, 0.108, 0.18, 0.3"); values ( \ - "0.0310995, 0.160492, 0.250487, 0.399113, 0.648098, 1.06314, 1.75422", \ - "0.0400129, 0.163129, 0.25135, 0.399117, 0.64819, 1.06315, 1.75423", \ - "0.0501159, 0.17205, 0.25734, 0.40187, 0.650295, 1.06316, 1.75425", \ - "0.0689173, 0.195035, 0.277878, 0.417176, 0.65653, 1.0651, 1.75426", \ - "0.100466, 0.238908, 0.324429, 0.461444, 0.691768, 1.08662, 1.76242", \ - "0.149802, 0.312489, 0.408341, 0.553486, 0.784635, 1.16466, 1.81562", \ - "0.23057, 0.430969, 0.540677, 0.707779, 0.956025, 1.35183, 1.98444" \ + "0.0310993, 0.16049, 0.25036, 0.399115, 0.648071, 1.06314, 1.75422", \ + "0.0399782, 0.163183, 0.251391, 0.399116, 0.648196, 1.06315, 1.75423", \ + "0.050116, 0.172051, 0.257307, 0.401876, 0.651029, 1.06316, 1.75426", \ + "0.0689174, 0.195036, 0.278104, 0.417179, 0.656538, 1.06482, 1.75662", \ + "0.100466, 0.238909, 0.32443, 0.461445, 0.691766, 1.0865, 1.76253", \ + "0.149802, 0.312491, 0.408342, 0.553489, 0.784638, 1.16467, 1.81561", \ + "0.230571, 0.43097, 0.540683, 0.707781, 0.956028, 1.35183, 1.98475" \ ); } cell_fall (TIMING_DELAY_7x7ds1) { index_1 ("0.0186, 0.0966, 0.174, 0.3294, 0.6408, 1.263, 2.5074"); index_2 ("0.001, 0.0234, 0.039, 0.0648, 0.108, 0.18, 0.3"); values ( \ - "0.0338939, 0.098085, 0.141244, 0.212314, 0.330943, 0.528678, 0.857706", \ - "0.0515252, 0.12502, 0.169346, 0.240818, 0.359581, 0.55722, 0.88662", \ - "0.0618811, 0.146242, 0.193867, 0.26792, 0.387812, 0.585732, 0.915015", \ - "0.0754956, 0.178876, 0.233464, 0.314682, 0.440795, 0.641615, 0.971312", \ - "0.0937957, 0.227251, 0.293511, 0.388983, 0.530358, 0.745417, 1.08409", \ - "0.116885, 0.29167, 0.378385, 0.497218, 0.666655, 0.914011, 1.284", \ - "0.144107, 0.371757, 0.486908, 0.645657, 0.862609, 1.16273, 1.59735" \ + "0.0338937, 0.0980881, 0.141288, 0.212327, 0.330947, 0.528686, 0.857716", \ + "0.0515102, 0.125016, 0.169337, 0.240848, 0.359574, 0.55725, 0.886615", \ + "0.0618816, 0.146242, 0.193869, 0.267929, 0.387821, 0.585742, 0.915031", \ + "0.0754963, 0.178877, 0.233467, 0.314684, 0.4408, 0.641624, 0.971403", \ + "0.0937967, 0.227253, 0.293514, 0.388986, 0.530364, 0.745381, 1.08408", \ + "0.116886, 0.291673, 0.378473, 0.497223, 0.666662, 0.914018, 1.28401", \ + "0.144109, 0.371761, 0.486913, 0.645663, 0.862607, 1.16274, 1.59714" \ ); } fall_transition (TIMING_DELAY_7x7ds1) { index_1 ("0.0186, 0.0966, 0.174, 0.3294, 0.6408, 1.263, 2.5074"); index_2 ("0.001, 0.0234, 0.039, 0.0648, 0.108, 0.18, 0.3"); values ( \ - "0.0241373, 0.107323, 0.165436, 0.261643, 0.422416, 0.689917, 1.13592", \ - "0.0341291, 0.113612, 0.169247, 0.262849, 0.422417, 0.689918, 1.13605", \ - "0.0445582, 0.124942, 0.17919, 0.270027, 0.426116, 0.690825, 1.13616", \ - "0.0630064, 0.148614, 0.202801, 0.292085, 0.442371, 0.699592, 1.13828", \ - "0.0935516, 0.193735, 0.250263, 0.340285, 0.489494, 0.737973, 1.16243", \ - "0.141117, 0.273912, 0.338286, 0.434684, 0.586779, 0.836095, 1.24736", \ - "0.218994, 0.40146, 0.488035, 0.603148, 0.767111, 1.02628, 1.44231" \ + "0.0241459, 0.107311, 0.165511, 0.261654, 0.422422, 0.689927, 1.13555", \ + "0.0341026, 0.113612, 0.169216, 0.262849, 0.422423, 0.689928, 1.13606", \ + "0.0445587, 0.124938, 0.179191, 0.27003, 0.426124, 0.690836, 1.13617", \ + "0.0630069, 0.148616, 0.20276, 0.29212, 0.442376, 0.699721, 1.13877", \ + "0.093552, 0.193737, 0.250265, 0.340289, 0.489499, 0.737914, 1.16203", \ + "0.141119, 0.273913, 0.337807, 0.434689, 0.586773, 0.836104, 1.24739", \ + "0.218995, 0.401462, 0.488038, 0.603153, 0.767099, 1.02629, 1.44234" \ ); } } @@ -5366,52 +5366,52 @@ library (sg13g2_stdcell_typ_1p50V_25C) { index_1 ("0.0186, 0.0966, 0.174, 0.3294, 0.6408, 1.263, 2.5074"); index_2 ("0.001, 0.0234, 0.039, 0.0648, 0.108, 0.18, 0.3"); values ( \ - "0.0411298, 0.132814, 0.195565, 0.298862, 0.471985, 0.759801, 1.24005", \ - "0.0644741, 0.164313, 0.227062, 0.330401, 0.503417, 0.791278, 1.27134", \ - "0.0797442, 0.193181, 0.258676, 0.362607, 0.535243, 0.822905, 1.30298", \ - "0.100195, 0.238117, 0.312585, 0.424189, 0.599953, 0.887542, 1.36753", \ - "0.131452, 0.303471, 0.393492, 0.52513, 0.718775, 1.01689, 1.49753", \ - "0.178521, 0.392915, 0.50806, 0.670192, 0.903195, 1.24226, 1.75084", \ - "0.250679, 0.521628, 0.66472, 0.870697, 1.16416, 1.57674, 2.17155" \ + "0.041129, 0.132814, 0.195548, 0.298867, 0.471999, 0.759805, 1.2402", \ + "0.064487, 0.164308, 0.227063, 0.330427, 0.503419, 0.791261, 1.27134", \ + "0.0797445, 0.193165, 0.25867, 0.362608, 0.535137, 0.823217, 1.30299", \ + "0.100195, 0.238118, 0.312585, 0.424181, 0.599955, 0.887602, 1.36692", \ + "0.131453, 0.303469, 0.393493, 0.52497, 0.718766, 1.01689, 1.49745", \ + "0.178522, 0.392916, 0.508063, 0.670194, 0.903197, 1.24227, 1.75085", \ + "0.250681, 0.52163, 0.664723, 0.870607, 1.16416, 1.57675, 2.17155" \ ); } rise_transition (TIMING_DELAY_7x7ds1) { index_1 ("0.0186, 0.0966, 0.174, 0.3294, 0.6408, 1.263, 2.5074"); index_2 ("0.001, 0.0234, 0.039, 0.0648, 0.108, 0.18, 0.3"); values ( \ - "0.0376181, 0.16799, 0.258399, 0.407801, 0.657969, 1.07461, 1.76897", \ - "0.0510827, 0.172393, 0.259828, 0.407802, 0.65797, 1.07462, 1.76898", \ - "0.0629115, 0.186483, 0.269534, 0.412273, 0.660916, 1.07463, 1.76899", \ - "0.0819689, 0.219252, 0.30097, 0.436511, 0.671638, 1.07978, 1.76998", \ - "0.112416, 0.27655, 0.36506, 0.501974, 0.727037, 1.11269, 1.78207", \ - "0.160611, 0.364713, 0.470232, 0.625223, 0.858915, 1.23215, 1.86629", \ - "0.244485, 0.499131, 0.631208, 0.818522, 1.09232, 1.49332, 2.12148" \ + "0.0376175, 0.167991, 0.258385, 0.407803, 0.657973, 1.07476, 1.76915", \ + "0.0510818, 0.172421, 0.259829, 0.407841, 0.657974, 1.07477, 1.76916", \ + "0.0629116, 0.186366, 0.269557, 0.412275, 0.658812, 1.07478, 1.76917", \ + "0.081969, 0.219255, 0.300972, 0.43642, 0.671643, 1.07794, 1.77411", \ + "0.112416, 0.276554, 0.365061, 0.501628, 0.727068, 1.11269, 1.78199", \ + "0.160611, 0.364714, 0.470233, 0.625225, 0.858918, 1.23194, 1.86603", \ + "0.244485, 0.499131, 0.631209, 0.819342, 1.09232, 1.49336, 2.12149" \ ); } cell_fall (TIMING_DELAY_7x7ds1) { index_1 ("0.0186, 0.0966, 0.174, 0.3294, 0.6408, 1.263, 2.5074"); index_2 ("0.001, 0.0234, 0.039, 0.0648, 0.108, 0.18, 0.3"); values ( \ - "0.0275542, 0.0914128, 0.13471, 0.206028, 0.324997, 0.522575, 0.85167", \ - "0.0413494, 0.118017, 0.162743, 0.234718, 0.353885, 0.551695, 0.880646", \ - "0.0481637, 0.138301, 0.186759, 0.261613, 0.382078, 0.580061, 0.909281", \ - "0.0565738, 0.169058, 0.225124, 0.307634, 0.434622, 0.635819, 0.965648", \ - "0.0669485, 0.213912, 0.282752, 0.38022, 0.523036, 0.739212, 1.0781", \ - "0.0775691, 0.270386, 0.361987, 0.484658, 0.656774, 0.905282, 1.27645", \ - "0.0823496, 0.333214, 0.456163, 0.621647, 0.845276, 1.14991, 1.58561" \ + "0.0275525, 0.0914549, 0.134651, 0.20602, 0.324992, 0.522568, 0.851661", \ + "0.041349, 0.118015, 0.162745, 0.234708, 0.353899, 0.551642, 0.880616", \ + "0.0481631, 0.138299, 0.186756, 0.2616, 0.382066, 0.580021, 0.909181", \ + "0.0565731, 0.169056, 0.225121, 0.307631, 0.434617, 0.635812, 0.965637", \ + "0.0669475, 0.21391, 0.282748, 0.380216, 0.523031, 0.739204, 1.07806", \ + "0.0775674, 0.270383, 0.361984, 0.484653, 0.656767, 0.905282, 1.27644", \ + "0.0823469, 0.333205, 0.456158, 0.621641, 0.845267, 1.1499, 1.5856" \ ); } fall_transition (TIMING_DELAY_7x7ds1) { index_1 ("0.0186, 0.0966, 0.174, 0.3294, 0.6408, 1.263, 2.5074"); index_2 ("0.001, 0.0234, 0.039, 0.0648, 0.108, 0.18, 0.3"); values ( \ - "0.0219432, 0.104195, 0.162056, 0.257797, 0.418222, 0.685661, 1.1312", \ - "0.0338703, 0.110958, 0.166102, 0.259361, 0.418619, 0.685951, 1.13125", \ - "0.0452303, 0.122722, 0.176528, 0.267006, 0.422451, 0.691396, 1.13182", \ - "0.0657984, 0.147316, 0.200702, 0.28934, 0.439044, 0.696039, 1.13546", \ - "0.0999855, 0.193886, 0.249259, 0.338131, 0.486411, 0.734438, 1.15847", \ - "0.15395, 0.277082, 0.339935, 0.43346, 0.58387, 0.831998, 1.2437", \ - "0.240827, 0.409023, 0.491643, 0.607091, 0.769093, 1.02694, 1.43958" \ + "0.0219457, 0.104191, 0.162015, 0.257791, 0.418215, 0.68565, 1.13118", \ + "0.0338699, 0.110956, 0.16619, 0.259356, 0.418921, 0.685869, 1.13245", \ + "0.0452312, 0.122721, 0.176525, 0.26684, 0.422427, 0.687289, 1.13246", \ + "0.0657978, 0.147315, 0.200645, 0.289336, 0.439037, 0.696286, 1.13543", \ + "0.0999849, 0.193884, 0.249256, 0.338128, 0.486406, 0.734611, 1.15842", \ + "0.153949, 0.27708, 0.339934, 0.433456, 0.583864, 0.831643, 1.24368", \ + "0.240827, 0.409039, 0.491641, 0.607086, 0.769087, 1.02688, 1.43957" \ ); } } @@ -5425,52 +5425,52 @@ library (sg13g2_stdcell_typ_1p50V_25C) { index_1 ("0.0186, 0.0966, 0.174, 0.3294, 0.6408, 1.263, 2.5074"); index_2 ("0.001, 0.0234, 0.039, 0.0648, 0.108, 0.18, 0.3"); values ( \ - "0.0343627, 0.125799, 0.188034, 0.29087, 0.463267, 0.750125, 1.22826", \ - "0.0551243, 0.157038, 0.219514, 0.322443, 0.494563, 0.781558, 1.25942", \ - "0.0686097, 0.18531, 0.250971, 0.354665, 0.526494, 0.813025, 1.29161", \ - "0.086087, 0.228794, 0.304021, 0.415811, 0.591203, 0.877634, 1.35483", \ - "0.113807, 0.291917, 0.383168, 0.515297, 0.709355, 1.00678, 1.48541", \ - "0.155687, 0.378548, 0.494471, 0.659043, 0.891659, 1.23089, 1.73852", \ - "0.22016, 0.503351, 0.648513, 0.855811, 1.15071, 1.56412, 2.15824" \ + "0.0343663, 0.1258, 0.188043, 0.290875, 0.463267, 0.75012, 1.22813", \ + "0.0551285, 0.15702, 0.219517, 0.322392, 0.494504, 0.78156, 1.25941", \ + "0.0686094, 0.185309, 0.250975, 0.354664, 0.526492, 0.816858, 1.29158", \ + "0.0860869, 0.228793, 0.30402, 0.41581, 0.5912, 0.877633, 1.35482", \ + "0.113807, 0.291917, 0.383167, 0.515296, 0.709353, 1.00678, 1.48555", \ + "0.155687, 0.378547, 0.49447, 0.659042, 0.891657, 1.23089, 1.73851", \ + "0.22016, 0.503351, 0.648512, 0.85581, 1.15071, 1.56412, 2.15824" \ ); } rise_transition (TIMING_DELAY_7x7ds1) { index_1 ("0.0186, 0.0966, 0.174, 0.3294, 0.6408, 1.263, 2.5074"); index_2 ("0.001, 0.0234, 0.039, 0.0648, 0.108, 0.18, 0.3"); values ( \ - "0.0315146, 0.160884, 0.250681, 0.39934, 0.648357, 1.06317, 1.7545", \ - "0.0456664, 0.165722, 0.252357, 0.399458, 0.648358, 1.06318, 1.75451", \ - "0.0566994, 0.180316, 0.2626, 0.404149, 0.649127, 1.06319, 1.75454", \ - "0.0745041, 0.213263, 0.294502, 0.429092, 0.662555, 1.06798, 1.7558", \ - "0.103109, 0.270166, 0.358832, 0.49493, 0.718668, 1.10205, 1.76815", \ - "0.149931, 0.356707, 0.462202, 0.617555, 0.850409, 1.22193, 1.85284", \ - "0.231225, 0.489601, 0.62203, 0.811079, 1.08303, 1.48381, 2.10876" \ + "0.0315219, 0.160887, 0.250689, 0.399338, 0.648354, 1.06317, 1.75454", \ + "0.0456634, 0.165711, 0.25239, 0.399341, 0.648355, 1.06318, 1.75457", \ + "0.0566996, 0.180315, 0.262651, 0.404147, 0.651158, 1.06649, 1.75458", \ + "0.074504, 0.213262, 0.294501, 0.42909, 0.662525, 1.06797, 1.75576", \ + "0.103108, 0.270165, 0.358832, 0.494928, 0.718667, 1.10206, 1.76829", \ + "0.14993, 0.356706, 0.462201, 0.617553, 0.850406, 1.22193, 1.85286", \ + "0.231222, 0.4896, 0.622029, 0.811077, 1.08302, 1.48381, 2.10875" \ ); } cell_fall (TIMING_DELAY_7x7ds1) { index_1 ("0.0186, 0.0966, 0.174, 0.3294, 0.6408, 1.263, 2.5074"); index_2 ("0.001, 0.0234, 0.039, 0.0648, 0.108, 0.18, 0.3"); values ( \ - "0.0270915, 0.0903795, 0.133262, 0.204055, 0.322579, 0.52001, 0.849136", \ - "0.0403266, 0.116793, 0.161298, 0.232762, 0.35147, 0.549015, 0.878378", \ - "0.0467987, 0.13693, 0.185139, 0.259588, 0.379615, 0.577507, 0.906774", \ - "0.0541411, 0.167286, 0.223083, 0.305266, 0.432087, 0.63316, 0.963059", \ - "0.0619646, 0.210895, 0.279972, 0.377475, 0.520409, 0.736639, 1.07556", \ - "0.0676564, 0.26538, 0.357318, 0.481211, 0.65327, 0.902346, 1.27389", \ - "0.0676574, 0.324347, 0.449165, 0.616219, 0.841169, 1.14644, 1.58279" \ + "0.0270847, 0.0903822, 0.133262, 0.204049, 0.322575, 0.519998, 0.849123", \ + "0.0403017, 0.116792, 0.161293, 0.232764, 0.351483, 0.548998, 0.878363", \ + "0.0467982, 0.136928, 0.185136, 0.259598, 0.379606, 0.577484, 0.906775", \ + "0.0541405, 0.167284, 0.223081, 0.305262, 0.432082, 0.633152, 0.963154", \ + "0.0619637, 0.210893, 0.279965, 0.377471, 0.520454, 0.736631, 1.07554", \ + "0.0676528, 0.265378, 0.35731, 0.481206, 0.653263, 0.902337, 1.27388", \ + "0.0676538, 0.324342, 0.44916, 0.616213, 0.84116, 1.14643, 1.58277" \ ); } fall_transition (TIMING_DELAY_7x7ds1) { index_1 ("0.0186, 0.0966, 0.174, 0.3294, 0.6408, 1.263, 2.5074"); index_2 ("0.001, 0.0234, 0.039, 0.0648, 0.108, 0.18, 0.3"); values ( \ - "0.0155693, 0.0980265, 0.155928, 0.251856, 0.412382, 0.679659, 1.12602", \ - "0.0259817, 0.104819, 0.160096, 0.253334, 0.4128, 0.680254, 1.12603", \ - "0.0356211, 0.116398, 0.170368, 0.260844, 0.416485, 0.682356, 1.12604", \ - "0.0532849, 0.140374, 0.19412, 0.283195, 0.43311, 0.690017, 1.12853", \ - "0.0829026, 0.18599, 0.242319, 0.332075, 0.480587, 0.728614, 1.15264", \ - "0.129028, 0.267047, 0.332283, 0.426711, 0.577912, 0.826266, 1.23786", \ - "0.207361, 0.394301, 0.481872, 0.600011, 0.761682, 1.01895, 1.43292" \ + "0.0155722, 0.098024, 0.155963, 0.251851, 0.412375, 0.680032, 1.12601", \ + "0.0259605, 0.104817, 0.160182, 0.253305, 0.412581, 0.680238, 1.12602", \ + "0.0355825, 0.116396, 0.17041, 0.260814, 0.416477, 0.682344, 1.12603", \ + "0.0532844, 0.140372, 0.194118, 0.283192, 0.433105, 0.690007, 1.12894", \ + "0.0829021, 0.185988, 0.242224, 0.332069, 0.480628, 0.728606, 1.15262", \ + "0.129028, 0.267045, 0.330465, 0.426704, 0.577901, 0.826263, 1.23784", \ + "0.207361, 0.394296, 0.481869, 0.600006, 0.761675, 1.01893, 1.4329" \ ); } } @@ -5482,52 +5482,52 @@ library (sg13g2_stdcell_typ_1p50V_25C) { index_1 ("0.0186, 0.0966, 0.174, 0.3294, 0.6408, 1.263, 2.5074"); index_2 ("0.001, 0.0234, 0.039, 0.0648, 0.108, 0.18, 0.3"); values ( \ - "0.0411298, 0.132814, 0.195565, 0.298862, 0.471985, 0.759801, 1.24005", \ - "0.0644741, 0.164313, 0.227062, 0.330401, 0.503417, 0.791278, 1.27134", \ - "0.0797442, 0.193181, 0.258676, 0.362607, 0.535243, 0.822905, 1.30298", \ - "0.100195, 0.238117, 0.312585, 0.424189, 0.599953, 0.887542, 1.36753", \ - "0.131452, 0.303471, 0.393492, 0.52513, 0.718775, 1.01689, 1.49753", \ - "0.178521, 0.392915, 0.50806, 0.670192, 0.903195, 1.24226, 1.75084", \ - "0.250679, 0.521628, 0.66472, 0.870697, 1.16416, 1.57674, 2.17155" \ + "0.041129, 0.132814, 0.195548, 0.298867, 0.471999, 0.759805, 1.2402", \ + "0.064487, 0.164308, 0.227063, 0.330427, 0.503419, 0.791261, 1.27134", \ + "0.0797445, 0.193165, 0.25867, 0.362608, 0.535137, 0.823217, 1.30299", \ + "0.100195, 0.238118, 0.312585, 0.424181, 0.599955, 0.887602, 1.36692", \ + "0.131453, 0.303469, 0.393493, 0.52497, 0.718766, 1.01689, 1.49745", \ + "0.178522, 0.392916, 0.508063, 0.670194, 0.903197, 1.24227, 1.75085", \ + "0.250681, 0.52163, 0.664723, 0.870607, 1.16416, 1.57675, 2.17155" \ ); } rise_transition (TIMING_DELAY_7x7ds1) { index_1 ("0.0186, 0.0966, 0.174, 0.3294, 0.6408, 1.263, 2.5074"); index_2 ("0.001, 0.0234, 0.039, 0.0648, 0.108, 0.18, 0.3"); values ( \ - "0.0376181, 0.16799, 0.258399, 0.407801, 0.657969, 1.07461, 1.76897", \ - "0.0510827, 0.172393, 0.259828, 0.407802, 0.65797, 1.07462, 1.76898", \ - "0.0629115, 0.186483, 0.269534, 0.412273, 0.660916, 1.07463, 1.76899", \ - "0.0819689, 0.219252, 0.30097, 0.436511, 0.671638, 1.07978, 1.76998", \ - "0.112416, 0.27655, 0.36506, 0.501974, 0.727037, 1.11269, 1.78207", \ - "0.160611, 0.364713, 0.470232, 0.625223, 0.858915, 1.23215, 1.86629", \ - "0.244485, 0.499131, 0.631208, 0.818522, 1.09232, 1.49332, 2.12148" \ + "0.0376175, 0.167991, 0.258385, 0.407803, 0.657973, 1.07476, 1.76915", \ + "0.0510818, 0.172421, 0.259829, 0.407841, 0.657974, 1.07477, 1.76916", \ + "0.0629116, 0.186366, 0.269557, 0.412275, 0.658812, 1.07478, 1.76917", \ + "0.081969, 0.219255, 0.300972, 0.43642, 0.671643, 1.07794, 1.77411", \ + "0.112416, 0.276554, 0.365061, 0.501628, 0.727068, 1.11269, 1.78199", \ + "0.160611, 0.364714, 0.470233, 0.625225, 0.858918, 1.23194, 1.86603", \ + "0.244485, 0.499131, 0.631209, 0.819342, 1.09232, 1.49336, 2.12149" \ ); } cell_fall (TIMING_DELAY_7x7ds1) { index_1 ("0.0186, 0.0966, 0.174, 0.3294, 0.6408, 1.263, 2.5074"); index_2 ("0.001, 0.0234, 0.039, 0.0648, 0.108, 0.18, 0.3"); values ( \ - "0.0275542, 0.0914128, 0.13471, 0.206028, 0.324997, 0.522575, 0.85167", \ - "0.0413494, 0.118017, 0.162743, 0.234718, 0.353885, 0.551695, 0.880646", \ - "0.0481637, 0.138301, 0.186759, 0.261613, 0.382078, 0.580061, 0.909281", \ - "0.0565738, 0.169058, 0.225124, 0.307634, 0.434622, 0.635819, 0.965648", \ - "0.0669485, 0.213912, 0.282752, 0.38022, 0.523036, 0.739212, 1.0781", \ - "0.0775691, 0.270386, 0.361987, 0.484658, 0.656774, 0.905282, 1.27645", \ - "0.0823496, 0.333214, 0.456163, 0.621647, 0.845276, 1.14991, 1.58561" \ + "0.0275525, 0.0914549, 0.134651, 0.20602, 0.324992, 0.522568, 0.851661", \ + "0.041349, 0.118015, 0.162745, 0.234708, 0.353899, 0.551642, 0.880616", \ + "0.0481631, 0.138299, 0.186756, 0.2616, 0.382066, 0.580021, 0.909181", \ + "0.0565731, 0.169056, 0.225121, 0.307631, 0.434617, 0.635812, 0.965637", \ + "0.0669475, 0.21391, 0.282748, 0.380216, 0.523031, 0.739204, 1.07806", \ + "0.0775674, 0.270383, 0.361984, 0.484653, 0.656767, 0.905282, 1.27644", \ + "0.0823469, 0.333205, 0.456158, 0.621641, 0.845267, 1.1499, 1.5856" \ ); } fall_transition (TIMING_DELAY_7x7ds1) { index_1 ("0.0186, 0.0966, 0.174, 0.3294, 0.6408, 1.263, 2.5074"); index_2 ("0.001, 0.0234, 0.039, 0.0648, 0.108, 0.18, 0.3"); values ( \ - "0.0219432, 0.104195, 0.162056, 0.257797, 0.418222, 0.685661, 1.1312", \ - "0.0338703, 0.110958, 0.166102, 0.259361, 0.418619, 0.685951, 1.13125", \ - "0.0452303, 0.122722, 0.176528, 0.267006, 0.422451, 0.691396, 1.13182", \ - "0.0657984, 0.147316, 0.200702, 0.28934, 0.439044, 0.696039, 1.13546", \ - "0.0999855, 0.193886, 0.249259, 0.338131, 0.486411, 0.734438, 1.15847", \ - "0.15395, 0.277082, 0.339935, 0.43346, 0.58387, 0.831998, 1.2437", \ - "0.240827, 0.409023, 0.491643, 0.607091, 0.769093, 1.02694, 1.43958" \ + "0.0219457, 0.104191, 0.162015, 0.257791, 0.418215, 0.68565, 1.13118", \ + "0.0338699, 0.110956, 0.16619, 0.259356, 0.418921, 0.685869, 1.13245", \ + "0.0452312, 0.122721, 0.176525, 0.26684, 0.422427, 0.687289, 1.13246", \ + "0.0657978, 0.147315, 0.200645, 0.289336, 0.439037, 0.696286, 1.13543", \ + "0.0999849, 0.193884, 0.249256, 0.338128, 0.486406, 0.734611, 1.15842", \ + "0.153949, 0.27708, 0.339934, 0.433456, 0.583864, 0.831643, 1.24368", \ + "0.240827, 0.409039, 0.491641, 0.607086, 0.769087, 1.02688, 1.43957" \ ); } } @@ -5541,52 +5541,52 @@ library (sg13g2_stdcell_typ_1p50V_25C) { index_1 ("0.0186, 0.0966, 0.174, 0.3294, 0.6408, 1.263, 2.5074"); index_2 ("0.001, 0.0234, 0.039, 0.0648, 0.108, 0.18, 0.3"); values ( \ - "0.0350472, 0.127265, 0.189701, 0.292621, 0.465043, 0.751688, 1.23012", \ - "0.0553942, 0.157963, 0.220712, 0.323886, 0.49619, 0.783177, 1.26122", \ - "0.0684078, 0.185932, 0.251886, 0.355789, 0.527931, 0.814669, 1.29263", \ - "0.0848991, 0.228938, 0.304395, 0.416576, 0.592208, 0.878963, 1.35636", \ - "0.11019, 0.290806, 0.382817, 0.515498, 0.709868, 1.00768, 1.48676", \ - "0.145404, 0.37386, 0.49141, 0.656804, 0.891322, 1.23135, 1.73929", \ - "0.195364, 0.488781, 0.637128, 0.847452, 1.14494, 1.56166, 2.15707" \ + "0.0350484, 0.127265, 0.189701, 0.292626, 0.465043, 0.751689, 1.23012", \ + "0.0553943, 0.157985, 0.22072, 0.323879, 0.496163, 0.783194, 1.26124", \ + "0.0684079, 0.185948, 0.251904, 0.355772, 0.527933, 0.814672, 1.29261", \ + "0.0848993, 0.228938, 0.304395, 0.416578, 0.592242, 0.878966, 1.35651", \ + "0.110191, 0.290807, 0.382818, 0.515499, 0.709868, 1.00768, 1.48671", \ + "0.145405, 0.373862, 0.491411, 0.656805, 0.891324, 1.23136, 1.73929", \ + "0.195366, 0.488784, 0.63713, 0.847454, 1.14494, 1.56167, 2.15707" \ ); } rise_transition (TIMING_DELAY_7x7ds1) { index_1 ("0.0186, 0.0966, 0.174, 0.3294, 0.6408, 1.263, 2.5074"); index_2 ("0.001, 0.0234, 0.039, 0.0648, 0.108, 0.18, 0.3"); values ( \ - "0.0311272, 0.160647, 0.250397, 0.399057, 0.648056, 1.06279, 1.75422", \ - "0.0451942, 0.165198, 0.251995, 0.399107, 0.648116, 1.0628, 1.75423", \ - "0.0564697, 0.179726, 0.262108, 0.403822, 0.650647, 1.06281, 1.75424", \ - "0.0752703, 0.212857, 0.293857, 0.428406, 0.662044, 1.06716, 1.75543", \ - "0.105909, 0.269996, 0.358711, 0.494306, 0.718025, 1.10159, 1.76775", \ - "0.157592, 0.359189, 0.463686, 0.617802, 0.850758, 1.22228, 1.85239", \ - "0.247067, 0.500024, 0.628841, 0.814905, 1.08409, 1.48449, 2.10871" \ + "0.031126, 0.160649, 0.250399, 0.399058, 0.648059, 1.0628, 1.75422", \ + "0.0451944, 0.165216, 0.252011, 0.399102, 0.64806, 1.06281, 1.75423", \ + "0.0564699, 0.179727, 0.262033, 0.403791, 0.650649, 1.06282, 1.75424", \ + "0.075271, 0.212856, 0.293845, 0.428523, 0.662032, 1.0673, 1.75425", \ + "0.105909, 0.269996, 0.358711, 0.494315, 0.718135, 1.10159, 1.76779", \ + "0.157592, 0.359189, 0.463687, 0.617804, 0.850759, 1.2222, 1.8524", \ + "0.247067, 0.500024, 0.628841, 0.814906, 1.08409, 1.48449, 2.10872" \ ); } cell_fall (TIMING_DELAY_7x7ds1) { index_1 ("0.0186, 0.0966, 0.174, 0.3294, 0.6408, 1.263, 2.5074"); index_2 ("0.001, 0.0234, 0.039, 0.0648, 0.108, 0.18, 0.3"); values ( \ - "0.0248715, 0.0892066, 0.132517, 0.203799, 0.322815, 0.520434, 0.8495", \ - "0.0399604, 0.123069, 0.168339, 0.240327, 0.359278, 0.557035, 0.885943", \ - "0.0479855, 0.148028, 0.198997, 0.275146, 0.39589, 0.593543, 0.922436", \ - "0.0587076, 0.184292, 0.245566, 0.333354, 0.463498, 0.66554, 0.994766", \ - "0.0728561, 0.235371, 0.312054, 0.419932, 0.573323, 0.797611, 1.1399", \ - "0.0906342, 0.30128, 0.402093, 0.538556, 0.731024, 1.00078, 1.39111", \ - "0.108797, 0.379199, 0.513165, 0.695349, 0.943394, 1.28508, 1.76357" \ + "0.0248697, 0.0892147, 0.132517, 0.2038, 0.322812, 0.520429, 0.849485", \ + "0.0399601, 0.123083, 0.168342, 0.240302, 0.359301, 0.557058, 0.885914", \ + "0.0479851, 0.148026, 0.198995, 0.275145, 0.395878, 0.593508, 0.922426", \ + "0.058707, 0.184285, 0.245564, 0.333351, 0.463508, 0.665533, 0.994743", \ + "0.0728552, 0.23537, 0.312051, 0.419929, 0.573318, 0.797603, 1.13989", \ + "0.0906327, 0.301277, 0.40209, 0.538552, 0.731018, 1.00084, 1.39109", \ + "0.108794, 0.379195, 0.513137, 0.695343, 0.943378, 1.28507, 1.76355" \ ); } fall_transition (TIMING_DELAY_7x7ds1) { index_1 ("0.0186, 0.0966, 0.174, 0.3294, 0.6408, 1.263, 2.5074"); index_2 ("0.001, 0.0234, 0.039, 0.0648, 0.108, 0.18, 0.3"); values ( \ - "0.0228556, 0.104101, 0.162058, 0.257796, 0.418221, 0.685813, 1.13257", \ - "0.039508, 0.115312, 0.168755, 0.260304, 0.418704, 0.68585, 1.13258", \ - "0.052557, 0.132773, 0.185022, 0.272605, 0.424923, 0.690126, 1.13259", \ - "0.0742946, 0.165403, 0.219913, 0.306792, 0.451727, 0.701949, 1.13703", \ - "0.110121, 0.221706, 0.282684, 0.374891, 0.522192, 0.762252, 1.17394", \ - "0.168797, 0.317079, 0.387794, 0.494789, 0.653185, 0.903842, 1.30574", \ - "0.264388, 0.466127, 0.564183, 0.694194, 0.880341, 1.15556, 1.58509" \ + "0.022852, 0.104121, 0.162055, 0.257792, 0.418214, 0.685802, 1.13255", \ + "0.0395078, 0.115287, 0.168751, 0.260292, 0.418561, 0.685902, 1.13256", \ + "0.0525553, 0.132771, 0.18502, 0.272605, 0.424928, 0.687968, 1.13257", \ + "0.0742942, 0.165399, 0.219911, 0.306789, 0.451739, 0.701939, 1.13557", \ + "0.110121, 0.221705, 0.282682, 0.374894, 0.522186, 0.762243, 1.17392", \ + "0.168796, 0.317077, 0.387791, 0.494785, 0.653179, 0.903565, 1.30574", \ + "0.264388, 0.466125, 0.563435, 0.69419, 0.880584, 1.15555, 1.58508" \ ); } } @@ -5600,52 +5600,52 @@ library (sg13g2_stdcell_typ_1p50V_25C) { index_1 ("0.0186, 0.0966, 0.174, 0.3294, 0.6408, 1.263, 2.5074"); index_2 ("0.001, 0.0234, 0.039, 0.0648, 0.108, 0.18, 0.3"); values ( \ - "0.028398, 0.120948, 0.183634, 0.287, 0.460126, 0.747898, 1.22831", \ - "0.0455616, 0.151624, 0.214666, 0.31827, 0.491182, 0.779581, 1.25941", \ - "0.0564646, 0.179081, 0.245691, 0.350139, 0.522979, 0.814773, 1.29149", \ - "0.0700544, 0.220717, 0.297484, 0.410697, 0.587275, 0.875159, 1.35451", \ - "0.0909296, 0.280789, 0.374486, 0.508873, 0.70472, 1.00389, 1.48459", \ - "0.120215, 0.360845, 0.481256, 0.648399, 0.885178, 1.22678, 1.73731", \ - "0.161443, 0.472626, 0.623753, 0.836592, 1.13807, 1.55662, 2.15435" \ + "0.0283994, 0.120932, 0.183633, 0.287002, 0.460125, 0.747893, 1.22831", \ + "0.0455615, 0.151632, 0.21467, 0.318214, 0.491268, 0.779588, 1.25937", \ + "0.0564645, 0.17908, 0.245689, 0.350132, 0.522927, 0.814764, 1.29147", \ + "0.0700543, 0.220716, 0.297484, 0.410696, 0.587273, 0.875152, 1.35533", \ + "0.0909297, 0.280789, 0.374485, 0.508872, 0.704718, 1.00389, 1.48487", \ + "0.120215, 0.360844, 0.481255, 0.648398, 0.885177, 1.22677, 1.7373", \ + "0.161444, 0.472625, 0.623752, 0.836591, 1.13807, 1.55662, 2.15435" \ ); } rise_transition (TIMING_DELAY_7x7ds1) { index_1 ("0.0186, 0.0966, 0.174, 0.3294, 0.6408, 1.263, 2.5074"); index_2 ("0.001, 0.0234, 0.039, 0.0648, 0.108, 0.18, 0.3"); values ( \ - "0.0254185, 0.154598, 0.244849, 0.394108, 0.644106, 1.06048, 1.75491", \ - "0.0398842, 0.159893, 0.246673, 0.394942, 0.644107, 1.06049, 1.75492", \ - "0.0506916, 0.174981, 0.257168, 0.399153, 0.64509, 1.06396, 1.75493", \ - "0.0678836, 0.208251, 0.289536, 0.424218, 0.658506, 1.06497, 1.75619", \ - "0.0975138, 0.264767, 0.354176, 0.490788, 0.714835, 1.09946, 1.76828", \ - "0.148567, 0.352585, 0.459932, 0.613491, 0.847738, 1.2203, 1.85346", \ - "0.236824, 0.493091, 0.625218, 0.813974, 1.08196, 1.48515, 2.11003" \ + "0.0254187, 0.154667, 0.244848, 0.394106, 0.644104, 1.06047, 1.75491", \ + "0.0398841, 0.159921, 0.246675, 0.394107, 0.644105, 1.06048, 1.75492", \ + "0.0506915, 0.17498, 0.257163, 0.399028, 0.645029, 1.06399, 1.75493", \ + "0.0678834, 0.208251, 0.289535, 0.424214, 0.658502, 1.06533, 1.75585", \ + "0.0975138, 0.264767, 0.354174, 0.490787, 0.714833, 1.09946, 1.76858", \ + "0.148567, 0.352584, 0.459932, 0.61349, 0.847693, 1.22029, 1.85346", \ + "0.236824, 0.49309, 0.625217, 0.813972, 1.08195, 1.48515, 2.11002" \ ); } cell_fall (TIMING_DELAY_7x7ds1) { index_1 ("0.0186, 0.0966, 0.174, 0.3294, 0.6408, 1.263, 2.5074"); index_2 ("0.001, 0.0234, 0.039, 0.0648, 0.108, 0.18, 0.3"); values ( \ - "0.024376, 0.0881773, 0.131058, 0.201905, 0.320412, 0.51785, 0.846995", \ - "0.038789, 0.121812, 0.166849, 0.238367, 0.356865, 0.55425, 0.88365", \ - "0.0461436, 0.14643, 0.197235, 0.273086, 0.39343, 0.590974, 0.919998", \ - "0.0554149, 0.181818, 0.243204, 0.330881, 0.460884, 0.662857, 0.992182", \ - "0.0664697, 0.231646, 0.30842, 0.416546, 0.57017, 0.794798, 1.13722", \ - "0.0769238, 0.294416, 0.396559, 0.533796, 0.726989, 0.997531, 1.38843", \ - "0.0812671, 0.367929, 0.504121, 0.688753, 0.938601, 1.28079, 1.76013" \ + "0.0243765, 0.0881738, 0.131098, 0.201902, 0.320411, 0.517844, 0.846964", \ + "0.0387788, 0.121795, 0.166853, 0.238359, 0.356852, 0.554655, 0.883566", \ + "0.0461432, 0.146429, 0.197234, 0.273087, 0.393436, 0.590989, 0.919983", \ + "0.0554144, 0.181814, 0.243202, 0.330878, 0.46087, 0.662857, 0.992237", \ + "0.066469, 0.23152, 0.308418, 0.416547, 0.570165, 0.79479, 1.1372", \ + "0.0769227, 0.294414, 0.396556, 0.533792, 0.726983, 0.997562, 1.38842", \ + "0.0812654, 0.367925, 0.504121, 0.688748, 0.938593, 1.28077, 1.76011" \ ); } fall_transition (TIMING_DELAY_7x7ds1) { index_1 ("0.0186, 0.0966, 0.174, 0.3294, 0.6408, 1.263, 2.5074"); index_2 ("0.001, 0.0234, 0.039, 0.0648, 0.108, 0.18, 0.3"); values ( \ - "0.0164337, 0.0980272, 0.15598, 0.251869, 0.412707, 0.680014, 1.12602", \ - "0.0301843, 0.10915, 0.162631, 0.254403, 0.412866, 0.680015, 1.12603", \ - "0.0407392, 0.126248, 0.178748, 0.266685, 0.419007, 0.682384, 1.12604", \ - "0.058761, 0.157833, 0.21328, 0.30044, 0.445631, 0.695928, 1.13088", \ - "0.0883734, 0.212352, 0.274417, 0.367575, 0.515854, 0.756554, 1.16791", \ - "0.137637, 0.305027, 0.378256, 0.484703, 0.646369, 0.897243, 1.30038", \ - "0.223048, 0.450068, 0.550232, 0.685297, 0.871677, 1.15076, 1.57665" \ + "0.0164336, 0.0980254, 0.156112, 0.251864, 0.412702, 0.680008, 1.12601", \ + "0.0301672, 0.109118, 0.162616, 0.254256, 0.412973, 0.680209, 1.12602", \ + "0.0408892, 0.126246, 0.178746, 0.266524, 0.419015, 0.681585, 1.12603", \ + "0.0587606, 0.157863, 0.213277, 0.300435, 0.445628, 0.69591, 1.13024", \ + "0.088373, 0.212184, 0.274413, 0.367727, 0.515849, 0.756543, 1.16788", \ + "0.137636, 0.305025, 0.378254, 0.484704, 0.646362, 0.898065, 1.30037", \ + "0.223048, 0.450065, 0.551317, 0.685293, 0.871671, 1.15075, 1.57664" \ ); } } @@ -5657,52 +5657,52 @@ library (sg13g2_stdcell_typ_1p50V_25C) { index_1 ("0.0186, 0.0966, 0.174, 0.3294, 0.6408, 1.263, 2.5074"); index_2 ("0.001, 0.0234, 0.039, 0.0648, 0.108, 0.18, 0.3"); values ( \ - "0.0350472, 0.127265, 0.189701, 0.292621, 0.465043, 0.751688, 1.23012", \ - "0.0553942, 0.157963, 0.220712, 0.323886, 0.49619, 0.783177, 1.26122", \ - "0.0684078, 0.185932, 0.251886, 0.355789, 0.527931, 0.814669, 1.29263", \ - "0.0848991, 0.228938, 0.304395, 0.416576, 0.592208, 0.878963, 1.35636", \ - "0.11019, 0.290806, 0.382817, 0.515498, 0.709868, 1.00768, 1.48676", \ - "0.145404, 0.37386, 0.49141, 0.656804, 0.891322, 1.23135, 1.73929", \ - "0.195364, 0.488781, 0.637128, 0.847452, 1.14494, 1.56166, 2.15707" \ + "0.0350484, 0.127265, 0.189701, 0.292626, 0.465043, 0.751689, 1.23012", \ + "0.0553943, 0.157985, 0.22072, 0.323879, 0.496163, 0.783194, 1.26124", \ + "0.0684079, 0.185948, 0.251904, 0.355772, 0.527933, 0.814672, 1.29261", \ + "0.0848993, 0.228938, 0.304395, 0.416578, 0.592242, 0.878966, 1.35651", \ + "0.110191, 0.290807, 0.382818, 0.515499, 0.709868, 1.00768, 1.48671", \ + "0.145405, 0.373862, 0.491411, 0.656805, 0.891324, 1.23136, 1.73929", \ + "0.195366, 0.488784, 0.63713, 0.847454, 1.14494, 1.56167, 2.15707" \ ); } rise_transition (TIMING_DELAY_7x7ds1) { index_1 ("0.0186, 0.0966, 0.174, 0.3294, 0.6408, 1.263, 2.5074"); index_2 ("0.001, 0.0234, 0.039, 0.0648, 0.108, 0.18, 0.3"); values ( \ - "0.0311272, 0.160647, 0.250397, 0.399057, 0.648056, 1.06279, 1.75422", \ - "0.0451942, 0.165198, 0.251995, 0.399107, 0.648116, 1.0628, 1.75423", \ - "0.0564697, 0.179726, 0.262108, 0.403822, 0.650647, 1.06281, 1.75424", \ - "0.0752703, 0.212857, 0.293857, 0.428406, 0.662044, 1.06716, 1.75543", \ - "0.105909, 0.269996, 0.358711, 0.494306, 0.718025, 1.10159, 1.76775", \ - "0.157592, 0.359189, 0.463686, 0.617802, 0.850758, 1.22228, 1.85239", \ - "0.247067, 0.500024, 0.628841, 0.814905, 1.08409, 1.48449, 2.10871" \ + "0.031126, 0.160649, 0.250399, 0.399058, 0.648059, 1.0628, 1.75422", \ + "0.0451944, 0.165216, 0.252011, 0.399102, 0.64806, 1.06281, 1.75423", \ + "0.0564699, 0.179727, 0.262033, 0.403791, 0.650649, 1.06282, 1.75424", \ + "0.075271, 0.212856, 0.293845, 0.428523, 0.662032, 1.0673, 1.75425", \ + "0.105909, 0.269996, 0.358711, 0.494315, 0.718135, 1.10159, 1.76779", \ + "0.157592, 0.359189, 0.463687, 0.617804, 0.850759, 1.2222, 1.8524", \ + "0.247067, 0.500024, 0.628841, 0.814906, 1.08409, 1.48449, 2.10872" \ ); } cell_fall (TIMING_DELAY_7x7ds1) { index_1 ("0.0186, 0.0966, 0.174, 0.3294, 0.6408, 1.263, 2.5074"); index_2 ("0.001, 0.0234, 0.039, 0.0648, 0.108, 0.18, 0.3"); values ( \ - "0.0248715, 0.0892066, 0.132517, 0.203799, 0.322815, 0.520434, 0.8495", \ - "0.0399604, 0.123069, 0.168339, 0.240327, 0.359278, 0.557035, 0.885943", \ - "0.0479855, 0.148028, 0.198997, 0.275146, 0.39589, 0.593543, 0.922436", \ - "0.0587076, 0.184292, 0.245566, 0.333354, 0.463498, 0.66554, 0.994766", \ - "0.0728561, 0.235371, 0.312054, 0.419932, 0.573323, 0.797611, 1.1399", \ - "0.0906342, 0.30128, 0.402093, 0.538556, 0.731024, 1.00078, 1.39111", \ - "0.108797, 0.379199, 0.513165, 0.695349, 0.943394, 1.28508, 1.76357" \ + "0.0248697, 0.0892147, 0.132517, 0.2038, 0.322812, 0.520429, 0.849485", \ + "0.0399601, 0.123083, 0.168342, 0.240302, 0.359301, 0.557058, 0.885914", \ + "0.0479851, 0.148026, 0.198995, 0.275145, 0.395878, 0.593508, 0.922426", \ + "0.058707, 0.184285, 0.245564, 0.333351, 0.463508, 0.665533, 0.994743", \ + "0.0728552, 0.23537, 0.312051, 0.419929, 0.573318, 0.797603, 1.13989", \ + "0.0906327, 0.301277, 0.40209, 0.538552, 0.731018, 1.00084, 1.39109", \ + "0.108794, 0.379195, 0.513137, 0.695343, 0.943378, 1.28507, 1.76355" \ ); } fall_transition (TIMING_DELAY_7x7ds1) { index_1 ("0.0186, 0.0966, 0.174, 0.3294, 0.6408, 1.263, 2.5074"); index_2 ("0.001, 0.0234, 0.039, 0.0648, 0.108, 0.18, 0.3"); values ( \ - "0.0228556, 0.104101, 0.162058, 0.257796, 0.418221, 0.685813, 1.13257", \ - "0.039508, 0.115312, 0.168755, 0.260304, 0.418704, 0.68585, 1.13258", \ - "0.052557, 0.132773, 0.185022, 0.272605, 0.424923, 0.690126, 1.13259", \ - "0.0742946, 0.165403, 0.219913, 0.306792, 0.451727, 0.701949, 1.13703", \ - "0.110121, 0.221706, 0.282684, 0.374891, 0.522192, 0.762252, 1.17394", \ - "0.168797, 0.317079, 0.387794, 0.494789, 0.653185, 0.903842, 1.30574", \ - "0.264388, 0.466127, 0.564183, 0.694194, 0.880341, 1.15556, 1.58509" \ + "0.022852, 0.104121, 0.162055, 0.257792, 0.418214, 0.685802, 1.13255", \ + "0.0395078, 0.115287, 0.168751, 0.260292, 0.418561, 0.685902, 1.13256", \ + "0.0525553, 0.132771, 0.18502, 0.272605, 0.424928, 0.687968, 1.13257", \ + "0.0742942, 0.165399, 0.219911, 0.306789, 0.451739, 0.701939, 1.13557", \ + "0.110121, 0.221705, 0.282682, 0.374894, 0.522186, 0.762243, 1.17392", \ + "0.168796, 0.317077, 0.387791, 0.494785, 0.653179, 0.903565, 1.30574", \ + "0.264388, 0.466125, 0.563435, 0.69419, 0.880584, 1.15555, 1.58508" \ ); } } @@ -5713,26 +5713,26 @@ library (sg13g2_stdcell_typ_1p50V_25C) { index_1 ("0.0186, 0.0966, 0.174, 0.3294, 0.6408, 1.263, 2.5074"); index_2 ("0.001, 0.0234, 0.039, 0.0648, 0.108, 0.18, 0.3"); values ( \ - "0.00731643, 0.00779725, 0.0078029, 0.00773898, 0.00755964, 0.00722422, 0.00683107", \ - "0.00697321, 0.00742823, 0.00748312, 0.0075072, 0.00742176, 0.00716322, 0.00681195", \ - "0.00734329, 0.00734541, 0.00756355, 0.00749447, 0.00749516, 0.00720587, 0.00682066", \ - "0.0088886, 0.00796391, 0.00778061, 0.00776242, 0.00749348, 0.00720435, 0.00711594", \ - "0.013434, 0.0105753, 0.0100088, 0.00933311, 0.00879983, 0.00786786, 0.00846824", \ - "0.0237081, 0.0182703, 0.0167006, 0.0150424, 0.013132, 0.0112716, 0.0102405", \ - "0.0450377, 0.0369104, 0.0335355, 0.0299344, 0.0262675, 0.0218009, 0.0181424" \ + "0.00730443, 0.0078002, 0.00780272, 0.0077423, 0.0075739, 0.00724011, 0.00683099", \ + "0.00697547, 0.00740157, 0.00747777, 0.00750377, 0.00742058, 0.00711953, 0.00681238", \ + "0.00734328, 0.00734654, 0.00757699, 0.00744347, 0.00749517, 0.00710191, 0.00682059", \ + "0.00888997, 0.00796449, 0.00778096, 0.00782903, 0.00748515, 0.00714521, 0.0072095", \ + "0.0134345, 0.0105775, 0.00999457, 0.00936899, 0.00877273, 0.00789231, 0.00732196", \ + "0.0237076, 0.01827, 0.0167008, 0.0150417, 0.0130956, 0.0112766, 0.0107831", \ + "0.0450383, 0.0369094, 0.033534, 0.0299342, 0.0262663, 0.0217765, 0.0183008" \ ); } fall_power (POWER_7x7ds1) { index_1 ("0.0186, 0.0966, 0.174, 0.3294, 0.6408, 1.263, 2.5074"); index_2 ("0.001, 0.0234, 0.039, 0.0648, 0.108, 0.18, 0.3"); values ( \ - "0.00724253, 0.00733809, 0.00729349, 0.00719082, 0.00704616, 0.00670319, 0.00614159", \ - "0.00720631, 0.00718541, 0.00731302, 0.00713582, 0.00691176, 0.0066142, 0.00613505", \ - "0.00790259, 0.00746342, 0.00728914, 0.00727914, 0.00697965, 0.00693029, 0.00609041", \ - "0.00990348, 0.0084922, 0.00821059, 0.00778328, 0.00754135, 0.00697327, 0.00620429", \ - "0.0143601, 0.0114499, 0.0106138, 0.00990151, 0.00889503, 0.00798932, 0.00756407", \ - "0.024304, 0.0192301, 0.0173983, 0.0155061, 0.0135284, 0.0118363, 0.00955612", \ - "0.0449082, 0.0375792, 0.0343119, 0.0302904, 0.0259791, 0.0217507, 0.0181419" \ + "0.00723492, 0.00733568, 0.00729129, 0.00719257, 0.00704694, 0.00672196, 0.0062315", \ + "0.00722088, 0.00718527, 0.00730579, 0.0071444, 0.00691034, 0.00662075, 0.00608496", \ + "0.00790646, 0.00746063, 0.00728915, 0.00738479, 0.00693802, 0.00692919, 0.00609407", \ + "0.00990274, 0.0084856, 0.00821846, 0.00778281, 0.00754525, 0.00695035, 0.00675002", \ + "0.0143593, 0.0114501, 0.0106148, 0.00989013, 0.0089885, 0.00797528, 0.00755792", \ + "0.0243046, 0.0192299, 0.0173985, 0.0155041, 0.0135607, 0.0118434, 0.00952638", \ + "0.0449073, 0.0375807, 0.0343119, 0.0302908, 0.0259797, 0.0217516, 0.0181387" \ ); } } @@ -5742,26 +5742,26 @@ library (sg13g2_stdcell_typ_1p50V_25C) { index_1 ("0.0186, 0.0966, 0.174, 0.3294, 0.6408, 1.263, 2.5074"); index_2 ("0.001, 0.0234, 0.039, 0.0648, 0.108, 0.18, 0.3"); values ( \ - "0.00731643, 0.00779725, 0.0078029, 0.00773898, 0.00755964, 0.00722422, 0.00683107", \ - "0.00697321, 0.00742823, 0.00748312, 0.0075072, 0.00742176, 0.00716322, 0.00681195", \ - "0.00734329, 0.00734541, 0.00756355, 0.00749447, 0.00749516, 0.00720587, 0.00682066", \ - "0.0088886, 0.00796391, 0.00778061, 0.00776242, 0.00749348, 0.00720435, 0.00711594", \ - "0.013434, 0.0105753, 0.0100088, 0.00933311, 0.00879983, 0.00786786, 0.00846824", \ - "0.0237081, 0.0182703, 0.0167006, 0.0150424, 0.013132, 0.0112716, 0.0102405", \ - "0.0450377, 0.0369104, 0.0335355, 0.0299344, 0.0262675, 0.0218009, 0.0181424" \ + "0.00730443, 0.0078002, 0.00780272, 0.0077423, 0.0075739, 0.00724011, 0.00683099", \ + "0.00697547, 0.00740157, 0.00747777, 0.00750377, 0.00742058, 0.00711953, 0.00681238", \ + "0.00734328, 0.00734654, 0.00757699, 0.00744347, 0.00749517, 0.00710191, 0.00682059", \ + "0.00888997, 0.00796449, 0.00778096, 0.00782903, 0.00748515, 0.00714521, 0.0072095", \ + "0.0134345, 0.0105775, 0.00999457, 0.00936899, 0.00877273, 0.00789231, 0.00732196", \ + "0.0237076, 0.01827, 0.0167008, 0.0150417, 0.0130956, 0.0112766, 0.0107831", \ + "0.0450383, 0.0369094, 0.033534, 0.0299342, 0.0262663, 0.0217765, 0.0183008" \ ); } fall_power (POWER_7x7ds1) { index_1 ("0.0186, 0.0966, 0.174, 0.3294, 0.6408, 1.263, 2.5074"); index_2 ("0.001, 0.0234, 0.039, 0.0648, 0.108, 0.18, 0.3"); values ( \ - "0.00724253, 0.00733809, 0.00729349, 0.00719082, 0.00704616, 0.00670319, 0.00614159", \ - "0.00720631, 0.00718541, 0.00731302, 0.00713582, 0.00691176, 0.0066142, 0.00613505", \ - "0.00790259, 0.00746342, 0.00728914, 0.00727914, 0.00697965, 0.00693029, 0.00609041", \ - "0.00990348, 0.0084922, 0.00821059, 0.00778328, 0.00754135, 0.00697327, 0.00620429", \ - "0.0143601, 0.0114499, 0.0106138, 0.00990151, 0.00889503, 0.00798932, 0.00756407", \ - "0.024304, 0.0192301, 0.0173983, 0.0155061, 0.0135284, 0.0118363, 0.00955612", \ - "0.0449082, 0.0375792, 0.0343119, 0.0302904, 0.0259791, 0.0217507, 0.0181419" \ + "0.00723492, 0.00733568, 0.00729129, 0.00719257, 0.00704694, 0.00672196, 0.0062315", \ + "0.00722088, 0.00718527, 0.00730579, 0.0071444, 0.00691034, 0.00662075, 0.00608496", \ + "0.00790646, 0.00746063, 0.00728915, 0.00738479, 0.00693802, 0.00692919, 0.00609407", \ + "0.00990274, 0.0084856, 0.00821846, 0.00778281, 0.00754525, 0.00695035, 0.00675002", \ + "0.0143593, 0.0114501, 0.0106148, 0.00989013, 0.0089885, 0.00797528, 0.00755792", \ + "0.0243046, 0.0192299, 0.0173985, 0.0155041, 0.0135607, 0.0118434, 0.00952638", \ + "0.0449073, 0.0375807, 0.0343119, 0.0302908, 0.0259797, 0.0217516, 0.0181387" \ ); } } @@ -5772,26 +5772,26 @@ library (sg13g2_stdcell_typ_1p50V_25C) { index_1 ("0.0186, 0.0966, 0.174, 0.3294, 0.6408, 1.263, 2.5074"); index_2 ("0.001, 0.0234, 0.039, 0.0648, 0.108, 0.18, 0.3"); values ( \ - "0.00758821, 0.00767174, 0.00762374, 0.00752067, 0.00736121, 0.0070557, 0.00654276", \ - "0.00736523, 0.00754378, 0.00746839, 0.00740713, 0.00728677, 0.0069736, 0.00659119", \ - "0.00766289, 0.00753373, 0.00761349, 0.00738003, 0.00739816, 0.00689662, 0.00658362", \ - "0.00911282, 0.00824848, 0.00797863, 0.00795495, 0.00744774, 0.00711182, 0.00663342", \ - "0.0135383, 0.0110029, 0.0103213, 0.0095842, 0.00895089, 0.00788942, 0.00786182", \ - "0.0236614, 0.0189311, 0.0173472, 0.0154653, 0.0137014, 0.0113462, 0.0103545", \ - "0.0446221, 0.0378563, 0.0347601, 0.0311534, 0.0269372, 0.0229874, 0.0184429" \ + "0.00757613, 0.00767265, 0.00761964, 0.00752012, 0.00734352, 0.00705538, 0.00654418", \ + "0.00736301, 0.00752809, 0.00750884, 0.00740589, 0.00728811, 0.00696761, 0.00658992", \ + "0.00766387, 0.00753385, 0.00764602, 0.00751106, 0.00746761, 0.00693843, 0.00658253", \ + "0.00911325, 0.00826183, 0.007987, 0.00795684, 0.00762755, 0.00708725, 0.00689367", \ + "0.0135398, 0.0110021, 0.0103123, 0.00958874, 0.00895216, 0.00790016, 0.00871467", \ + "0.0236614, 0.0189305, 0.0173472, 0.0154624, 0.0137003, 0.0113974, 0.0108874", \ + "0.0446221, 0.0378558, 0.0347613, 0.0311535, 0.0269337, 0.0230634, 0.0184543" \ ); } fall_power (POWER_7x7ds1) { index_1 ("0.0186, 0.0966, 0.174, 0.3294, 0.6408, 1.263, 2.5074"); index_2 ("0.001, 0.0234, 0.039, 0.0648, 0.108, 0.18, 0.3"); values ( \ - "0.0098332, 0.00982795, 0.00978629, 0.00970258, 0.00954805, 0.00924543, 0.00867152", \ - "0.00958478, 0.00967209, 0.00972737, 0.00962466, 0.00940826, 0.00911711, 0.00860331", \ - "0.00999804, 0.00982122, 0.00971799, 0.00974041, 0.00949458, 0.00913936, 0.00865846", \ - "0.0115254, 0.0105875, 0.010411, 0.0101033, 0.00993607, 0.00935672, 0.00873091", \ - "0.0157759, 0.0131826, 0.0125076, 0.0119102, 0.0112873, 0.0104173, 0.0106135", \ - "0.0254001, 0.0205632, 0.0189259, 0.0170954, 0.0154009, 0.0141132, 0.0117059", \ - "0.0455663, 0.0383985, 0.0352006, 0.0314523, 0.0271814, 0.0233864, 0.0200585" \ + "0.00983488, 0.00982895, 0.0098074, 0.00970249, 0.00954883, 0.00923314, 0.00868224", \ + "0.00958423, 0.00967333, 0.0098064, 0.0096638, 0.00939003, 0.00911812, 0.00860013", \ + "0.00999538, 0.0098453, 0.00971792, 0.00974046, 0.00949447, 0.00910138, 0.0086591", \ + "0.0115265, 0.0105842, 0.0103762, 0.0100914, 0.00993655, 0.00931645, 0.00911072", \ + "0.0157754, 0.0131822, 0.0125027, 0.0119147, 0.0112975, 0.0103657, 0.0102914", \ + "0.0254006, 0.0205628, 0.0188829, 0.0170961, 0.0154277, 0.0140627, 0.0117108", \ + "0.0455665, 0.038398, 0.0352006, 0.0314519, 0.0271802, 0.0233851, 0.0199906" \ ); } } @@ -5801,26 +5801,26 @@ library (sg13g2_stdcell_typ_1p50V_25C) { index_1 ("0.0186, 0.0966, 0.174, 0.3294, 0.6408, 1.263, 2.5074"); index_2 ("0.001, 0.0234, 0.039, 0.0648, 0.108, 0.18, 0.3"); values ( \ - "0.00758821, 0.00767174, 0.00762374, 0.00752067, 0.00736121, 0.0070557, 0.00654276", \ - "0.00736523, 0.00754378, 0.00746839, 0.00740713, 0.00728677, 0.0069736, 0.00659119", \ - "0.00766289, 0.00753373, 0.00761349, 0.00738003, 0.00739816, 0.00689662, 0.00658362", \ - "0.00911282, 0.00824848, 0.00797863, 0.00795495, 0.00744774, 0.00711182, 0.00663342", \ - "0.0135383, 0.0110029, 0.0103213, 0.0095842, 0.00895089, 0.00788942, 0.00786182", \ - "0.0236614, 0.0189311, 0.0173472, 0.0154653, 0.0137014, 0.0113462, 0.0103545", \ - "0.0446221, 0.0378563, 0.0347601, 0.0311534, 0.0269372, 0.0229874, 0.0184429" \ + "0.00757613, 0.00767265, 0.00761964, 0.00752012, 0.00734352, 0.00705538, 0.00654418", \ + "0.00736301, 0.00752809, 0.00750884, 0.00740589, 0.00728811, 0.00696761, 0.00658992", \ + "0.00766387, 0.00753385, 0.00764602, 0.00751106, 0.00746761, 0.00693843, 0.00658253", \ + "0.00911325, 0.00826183, 0.007987, 0.00795684, 0.00762755, 0.00708725, 0.00689367", \ + "0.0135398, 0.0110021, 0.0103123, 0.00958874, 0.00895216, 0.00790016, 0.00871467", \ + "0.0236614, 0.0189305, 0.0173472, 0.0154624, 0.0137003, 0.0113974, 0.0108874", \ + "0.0446221, 0.0378558, 0.0347613, 0.0311535, 0.0269337, 0.0230634, 0.0184543" \ ); } fall_power (POWER_7x7ds1) { index_1 ("0.0186, 0.0966, 0.174, 0.3294, 0.6408, 1.263, 2.5074"); index_2 ("0.001, 0.0234, 0.039, 0.0648, 0.108, 0.18, 0.3"); values ( \ - "0.0098332, 0.00982795, 0.00978629, 0.00970258, 0.00954805, 0.00924543, 0.00867152", \ - "0.00958478, 0.00967209, 0.00972737, 0.00962466, 0.00940826, 0.00911711, 0.00860331", \ - "0.00999804, 0.00982122, 0.00971799, 0.00974041, 0.00949458, 0.00913936, 0.00865846", \ - "0.0115254, 0.0105875, 0.010411, 0.0101033, 0.00993607, 0.00935672, 0.00873091", \ - "0.0157759, 0.0131826, 0.0125076, 0.0119102, 0.0112873, 0.0104173, 0.0106135", \ - "0.0254001, 0.0205632, 0.0189259, 0.0170954, 0.0154009, 0.0141132, 0.0117059", \ - "0.0455663, 0.0383985, 0.0352006, 0.0314523, 0.0271814, 0.0233864, 0.0200585" \ + "0.00983488, 0.00982895, 0.0098074, 0.00970249, 0.00954883, 0.00923314, 0.00868224", \ + "0.00958423, 0.00967333, 0.0098064, 0.0096638, 0.00939003, 0.00911812, 0.00860013", \ + "0.00999538, 0.0098453, 0.00971792, 0.00974046, 0.00949447, 0.00910138, 0.0086591", \ + "0.0115265, 0.0105842, 0.0103762, 0.0100914, 0.00993655, 0.00931645, 0.00911072", \ + "0.0157754, 0.0131822, 0.0125027, 0.0119147, 0.0112975, 0.0103657, 0.0102914", \ + "0.0254006, 0.0205628, 0.0188829, 0.0170961, 0.0154277, 0.0140627, 0.0117108", \ + "0.0455665, 0.038398, 0.0352006, 0.0314519, 0.0271802, 0.0233851, 0.0199906" \ ); } } @@ -5831,26 +5831,26 @@ library (sg13g2_stdcell_typ_1p50V_25C) { index_1 ("0.0186, 0.0966, 0.174, 0.3294, 0.6408, 1.263, 2.5074"); index_2 ("0.001, 0.0234, 0.039, 0.0648, 0.108, 0.18, 0.3"); values ( \ - "0.00456487, 0.00475859, 0.00472001, 0.0046228, 0.0044732, 0.00415314, 0.00358886", \ - "0.00477627, 0.00465752, 0.00460647, 0.00454854, 0.00441663, 0.00407062, 0.00365629", \ - "0.00562707, 0.00500462, 0.00497216, 0.0047101, 0.00466114, 0.0041215, 0.00364885", \ - "0.00777404, 0.00627425, 0.00579165, 0.00548198, 0.00495446, 0.00453518, 0.00387255", \ - "0.0126982, 0.00992892, 0.00894017, 0.00785785, 0.00694492, 0.00569841, 0.00620215", \ - "0.0224488, 0.0179341, 0.0161845, 0.0142417, 0.0119979, 0.00957991, 0.0085929", \ - "0.0430824, 0.0366006, 0.0335954, 0.0300363, 0.0259754, 0.0214821, 0.0169096" \ + "0.00456472, 0.00475507, 0.00472792, 0.00462329, 0.00447306, 0.00412138, 0.0036646", \ + "0.00478244, 0.00465561, 0.00461528, 0.00455074, 0.00441212, 0.00405879, 0.00365645", \ + "0.00562867, 0.00500256, 0.00487473, 0.00471127, 0.00448829, 0.00412586, 0.00364916", \ + "0.00777283, 0.00627361, 0.00579165, 0.00554131, 0.00495459, 0.00435287, 0.00445536", \ + "0.0127008, 0.00992787, 0.00893932, 0.00786037, 0.00695807, 0.00569863, 0.00550992", \ + "0.0224483, 0.0179341, 0.0161866, 0.0142341, 0.0119675, 0.00956235, 0.00875397", \ + "0.0430826, 0.0366008, 0.0335956, 0.0300137, 0.0259752, 0.0214935, 0.0169078" \ ); } fall_power (POWER_7x7ds1) { index_1 ("0.0186, 0.0966, 0.174, 0.3294, 0.6408, 1.263, 2.5074"); index_2 ("0.001, 0.0234, 0.039, 0.0648, 0.108, 0.18, 0.3"); values ( \ - "0.00943194, 0.00997498, 0.00995079, 0.00986626, 0.00972166, 0.00940302, 0.00887576", \ - "0.00920007, 0.00974273, 0.00991902, 0.0098657, 0.00969866, 0.00946957, 0.0088856", \ - "0.00972868, 0.00982083, 0.00979962, 0.0100019, 0.00975569, 0.0101033, 0.00899397", \ - "0.0114521, 0.0104727, 0.0103751, 0.0101863, 0.0100998, 0.00956707, 0.0100062", \ - "0.015845, 0.0128795, 0.012281, 0.0117752, 0.0111689, 0.0104907, 0.0109001", \ - "0.0255085, 0.0199523, 0.018294, 0.0164736, 0.0149625, 0.0136966, 0.0117883", \ - "0.0455902, 0.0372222, 0.0338107, 0.0299765, 0.0260073, 0.0225757, 0.0194664" \ + "0.00943085, 0.00997613, 0.00994048, 0.00986375, 0.00972185, 0.00940364, 0.00885228", \ + "0.00919954, 0.00974274, 0.00999222, 0.00980929, 0.00977277, 0.00946032, 0.0090256", \ + "0.00972899, 0.00982117, 0.00980038, 0.00993529, 0.00973279, 0.00954855, 0.00899945", \ + "0.0114533, 0.0104668, 0.0103565, 0.0101793, 0.0100956, 0.00960673, 0.00999516", \ + "0.0158451, 0.0128899, 0.012282, 0.0117784, 0.0112249, 0.0105538, 0.0108493", \ + "0.0255082, 0.0199528, 0.0182852, 0.0164731, 0.0149811, 0.0137813, 0.0117909", \ + "0.0455775, 0.0372256, 0.0338103, 0.0299762, 0.0260076, 0.0225908, 0.0194317" \ ); } } @@ -5861,26 +5861,26 @@ library (sg13g2_stdcell_typ_1p50V_25C) { index_1 ("0.0186, 0.0966, 0.174, 0.3294, 0.6408, 1.263, 2.5074"); index_2 ("0.001, 0.0234, 0.039, 0.0648, 0.108, 0.18, 0.3"); values ( \ - "0.00426213, 0.00455152, 0.00449651, 0.00441061, 0.00425418, 0.00389923, 0.00339798", \ - "0.00461031, 0.00444604, 0.00440087, 0.00432658, 0.00417532, 0.00381918, 0.00344123", \ - "0.00554095, 0.00478567, 0.00468908, 0.00460539, 0.0042463, 0.00387707, 0.00338388", \ - "0.00782145, 0.00611066, 0.00561991, 0.00528766, 0.00475107, 0.00427223, 0.00374431", \ - "0.0128787, 0.00984795, 0.00882944, 0.00770211, 0.00673682, 0.00547324, 0.0053159", \ - "0.0228206, 0.0179894, 0.0160933, 0.0141758, 0.0117775, 0.0093581, 0.00800724", \ - "0.0436393, 0.0368263, 0.0337482, 0.0301048, 0.0259554, 0.0214214, 0.0168722" \ + "0.0042791, 0.00455182, 0.00449831, 0.00441146, 0.00425454, 0.00389911, 0.00348061", \ + "0.00460093, 0.0044351, 0.00438224, 0.00430318, 0.00416549, 0.00386521, 0.00342103", \ + "0.00554154, 0.00478173, 0.0046925, 0.00460545, 0.00440902, 0.00435563, 0.00337749", \ + "0.00782076, 0.00611059, 0.0056199, 0.00528833, 0.00468905, 0.00427311, 0.00375972", \ + "0.0128795, 0.00984806, 0.00882977, 0.00770257, 0.00676475, 0.00547428, 0.00514782", \ + "0.0228201, 0.017989, 0.0160938, 0.0141758, 0.0117781, 0.00932677, 0.00816535", \ + "0.0436388, 0.0368274, 0.0337482, 0.0301053, 0.0259556, 0.021387, 0.0168729" \ ); } fall_power (POWER_7x7ds1) { index_1 ("0.0186, 0.0966, 0.174, 0.3294, 0.6408, 1.263, 2.5074"); index_2 ("0.001, 0.0234, 0.039, 0.0648, 0.108, 0.18, 0.3"); values ( \ - "0.00676122, 0.00731018, 0.00729466, 0.00722702, 0.00708517, 0.00676253, 0.00630107", \ - "0.00653409, 0.00706807, 0.00722593, 0.00722083, 0.00708758, 0.00685256, 0.00633257", \ - "0.00707103, 0.00718645, 0.00714441, 0.00734689, 0.00716055, 0.00700213, 0.00628431", \ - "0.00885087, 0.00782977, 0.00772923, 0.0075219, 0.00745457, 0.00691038, 0.00702359", \ - "0.0133148, 0.0102782, 0.00967484, 0.00920556, 0.00866551, 0.00785155, 0.00738599", \ - "0.0230732, 0.0174406, 0.0157569, 0.0139304, 0.0123988, 0.0112271, 0.00910215", \ - "0.043284, 0.03475, 0.031389, 0.0276048, 0.0234509, 0.0198835, 0.016876" \ + "0.00676033, 0.0073111, 0.00729392, 0.0072218, 0.007085, 0.00678712, 0.00630077", \ + "0.00653059, 0.00707564, 0.00723002, 0.00721985, 0.00706484, 0.00685081, 0.0063326", \ + "0.00706998, 0.00718622, 0.00717238, 0.0073334, 0.00714167, 0.00699974, 0.00628989", \ + "0.00885072, 0.00782918, 0.0077271, 0.00752213, 0.00746254, 0.00691038, 0.00671478", \ + "0.0133145, 0.0102801, 0.0096679, 0.00919671, 0.00863117, 0.00794633, 0.00832773", \ + "0.0230742, 0.0174403, 0.015611, 0.0139367, 0.0123878, 0.0111581, 0.00910291", \ + "0.043284, 0.0347486, 0.0313903, 0.0276052, 0.0234498, 0.0199338, 0.0168698" \ ); } } @@ -5890,26 +5890,26 @@ library (sg13g2_stdcell_typ_1p50V_25C) { index_1 ("0.0186, 0.0966, 0.174, 0.3294, 0.6408, 1.263, 2.5074"); index_2 ("0.001, 0.0234, 0.039, 0.0648, 0.108, 0.18, 0.3"); values ( \ - "0.00456487, 0.00475859, 0.00472001, 0.0046228, 0.0044732, 0.00415314, 0.00358886", \ - "0.00477627, 0.00465752, 0.00460647, 0.00454854, 0.00441663, 0.00407062, 0.00365629", \ - "0.00562707, 0.00500462, 0.00497216, 0.0047101, 0.00466114, 0.0041215, 0.00364885", \ - "0.00777404, 0.00627425, 0.00579165, 0.00548198, 0.00495446, 0.00453518, 0.00387255", \ - "0.0126982, 0.00992892, 0.00894017, 0.00785785, 0.00694492, 0.00569841, 0.00620215", \ - "0.0224488, 0.0179341, 0.0161845, 0.0142417, 0.0119979, 0.00957991, 0.0085929", \ - "0.0430824, 0.0366006, 0.0335954, 0.0300363, 0.0259754, 0.0214821, 0.0169096" \ + "0.00456472, 0.00475507, 0.00472792, 0.00462329, 0.00447306, 0.00412138, 0.0036646", \ + "0.00478244, 0.00465561, 0.00461528, 0.00455074, 0.00441212, 0.00405879, 0.00365645", \ + "0.00562867, 0.00500256, 0.00487473, 0.00471127, 0.00448829, 0.00412586, 0.00364916", \ + "0.00777283, 0.00627361, 0.00579165, 0.00554131, 0.00495459, 0.00435287, 0.00445536", \ + "0.0127008, 0.00992787, 0.00893932, 0.00786037, 0.00695807, 0.00569863, 0.00550992", \ + "0.0224483, 0.0179341, 0.0161866, 0.0142341, 0.0119675, 0.00956235, 0.00875397", \ + "0.0430826, 0.0366008, 0.0335956, 0.0300137, 0.0259752, 0.0214935, 0.0169078" \ ); } fall_power (POWER_7x7ds1) { index_1 ("0.0186, 0.0966, 0.174, 0.3294, 0.6408, 1.263, 2.5074"); index_2 ("0.001, 0.0234, 0.039, 0.0648, 0.108, 0.18, 0.3"); values ( \ - "0.00943194, 0.00997498, 0.00995079, 0.00986626, 0.00972166, 0.00940302, 0.00887576", \ - "0.00920007, 0.00974273, 0.00991902, 0.0098657, 0.00969866, 0.00946957, 0.0088856", \ - "0.00972868, 0.00982083, 0.00979962, 0.0100019, 0.00975569, 0.0101033, 0.00899397", \ - "0.0114521, 0.0104727, 0.0103751, 0.0101863, 0.0100998, 0.00956707, 0.0100062", \ - "0.015845, 0.0128795, 0.012281, 0.0117752, 0.0111689, 0.0104907, 0.0109001", \ - "0.0255085, 0.0199523, 0.018294, 0.0164736, 0.0149625, 0.0136966, 0.0117883", \ - "0.0455902, 0.0372222, 0.0338107, 0.0299765, 0.0260073, 0.0225757, 0.0194664" \ + "0.00943085, 0.00997613, 0.00994048, 0.00986375, 0.00972185, 0.00940364, 0.00885228", \ + "0.00919954, 0.00974274, 0.00999222, 0.00980929, 0.00977277, 0.00946032, 0.0090256", \ + "0.00972899, 0.00982117, 0.00980038, 0.00993529, 0.00973279, 0.00954855, 0.00899945", \ + "0.0114533, 0.0104668, 0.0103565, 0.0101793, 0.0100956, 0.00960673, 0.00999516", \ + "0.0158451, 0.0128899, 0.012282, 0.0117784, 0.0112249, 0.0105538, 0.0108493", \ + "0.0255082, 0.0199528, 0.0182852, 0.0164731, 0.0149811, 0.0137813, 0.0117909", \ + "0.0455775, 0.0372256, 0.0338103, 0.0299762, 0.0260076, 0.0225908, 0.0194317" \ ); } } @@ -5920,26 +5920,26 @@ library (sg13g2_stdcell_typ_1p50V_25C) { index_1 ("0.0186, 0.0966, 0.174, 0.3294, 0.6408, 1.263, 2.5074"); index_2 ("0.001, 0.0234, 0.039, 0.0648, 0.108, 0.18, 0.3"); values ( \ - "0.00426637, 0.00480621, 0.00479815, 0.00473479, 0.00457575, 0.00422558, 0.0037619", \ - "0.00443216, 0.004542, 0.00458955, 0.00454147, 0.00447115, 0.00419876, 0.00379188", \ - "0.00528371, 0.00475918, 0.00482818, 0.00461075, 0.0046291, 0.00415244, 0.00368225", \ - "0.00743521, 0.00593333, 0.00549446, 0.0052761, 0.00484997, 0.00441702, 0.00394642", \ - "0.0122969, 0.00944795, 0.00854202, 0.00756692, 0.00666629, 0.00554224, 0.00594835", \ - "0.0223652, 0.0171639, 0.0153817, 0.013553, 0.0115703, 0.00932315, 0.00850966", \ - "0.0434033, 0.0354328, 0.0322526, 0.0286454, 0.0247584, 0.02067, 0.0162497" \ + "0.00426384, 0.00480615, 0.00479807, 0.0047358, 0.00457548, 0.00422527, 0.00376159", \ + "0.00443206, 0.0045273, 0.00454735, 0.00453481, 0.00444872, 0.00420089, 0.00379193", \ + "0.00528375, 0.00474243, 0.00482211, 0.00475355, 0.00462924, 0.00415221, 0.0037045", \ + "0.00743453, 0.00593332, 0.00549755, 0.00539842, 0.00482687, 0.00445792, 0.00390706", \ + "0.0122983, 0.00944801, 0.00853238, 0.00755049, 0.00668835, 0.00554186, 0.00595587", \ + "0.0223656, 0.0171639, 0.0153817, 0.0135524, 0.0115621, 0.00932348, 0.00857247", \ + "0.0434033, 0.0354321, 0.0322521, 0.0286457, 0.0247584, 0.0206873, 0.0162432" \ ); } fall_power (POWER_7x7ds1) { index_1 ("0.0186, 0.0966, 0.174, 0.3294, 0.6408, 1.263, 2.5074"); index_2 ("0.001, 0.0234, 0.039, 0.0648, 0.108, 0.18, 0.3"); values ( \ - "0.00678201, 0.00738349, 0.00739509, 0.00730636, 0.00716481, 0.00688873, 0.00646713", \ - "0.00695288, 0.00724046, 0.00744656, 0.00743105, 0.00717634, 0.00692658, 0.00651798", \ - "0.00775772, 0.00744754, 0.00736705, 0.00745618, 0.0071982, 0.00726065, 0.00642", \ - "0.00979087, 0.00831614, 0.00809415, 0.0078274, 0.00768832, 0.00705413, 0.00729439", \ - "0.0145312, 0.0110937, 0.0104114, 0.00972386, 0.00888131, 0.00807655, 0.00768562", \ - "0.0243852, 0.0185054, 0.016685, 0.0149063, 0.0131911, 0.0116041, 0.00932076", \ - "0.0449159, 0.0362921, 0.0326126, 0.0288106, 0.0248141, 0.0208854, 0.0176073" \ + "0.00677864, 0.00739233, 0.00739465, 0.00730727, 0.00716589, 0.00688899, 0.00647167", \ + "0.00695311, 0.00723764, 0.00744664, 0.0072849, 0.00716514, 0.00691472, 0.00650997", \ + "0.00775404, 0.00744509, 0.00737866, 0.00755389, 0.00719127, 0.00699735, 0.00637615", \ + "0.00979182, 0.00831628, 0.00811279, 0.00782747, 0.00767089, 0.00705391, 0.00670915", \ + "0.0145308, 0.0110928, 0.0104044, 0.0097282, 0.00888428, 0.00807829, 0.00768721", \ + "0.0243902, 0.0185055, 0.0166873, 0.014905, 0.0131895, 0.0115369, 0.00961475", \ + "0.0449148, 0.036291, 0.0326415, 0.0288128, 0.0248128, 0.0208723, 0.0176127" \ ); } } @@ -5950,26 +5950,26 @@ library (sg13g2_stdcell_typ_1p50V_25C) { index_1 ("0.0186, 0.0966, 0.174, 0.3294, 0.6408, 1.263, 2.5074"); index_2 ("0.001, 0.0234, 0.039, 0.0648, 0.108, 0.18, 0.3"); values ( \ - "0.00385086, 0.0045528, 0.00457545, 0.00452409, 0.00436538, 0.00404997, 0.00357206", \ - "0.00423621, 0.00426521, 0.00432589, 0.00439558, 0.00420535, 0.00393079, 0.00354602", \ - "0.00521802, 0.00453924, 0.00459432, 0.00442648, 0.00426269, 0.00440311, 0.0034909", \ - "0.00753671, 0.00575529, 0.0053241, 0.00516662, 0.004626, 0.00419706, 0.00372184", \ - "0.0126908, 0.00933451, 0.008396, 0.00733631, 0.00648682, 0.00534103, 0.00521575", \ - "0.0228203, 0.0171529, 0.0154097, 0.0134185, 0.0113517, 0.00908852, 0.00778948", \ - "0.0439976, 0.03564, 0.0323975, 0.0288238, 0.0247458, 0.020635, 0.0159627" \ + "0.00384367, 0.00455839, 0.00457499, 0.00452436, 0.00438142, 0.00404978, 0.00361005", \ + "0.0042357, 0.00428922, 0.0043521, 0.00431088, 0.00424214, 0.00393412, 0.00354448", \ + "0.00521698, 0.00454083, 0.00449292, 0.00440532, 0.00427776, 0.00440186, 0.00348881", \ + "0.00753643, 0.00575739, 0.00532408, 0.0051851, 0.00462608, 0.004256, 0.00375604", \ + "0.0126917, 0.00933457, 0.00839529, 0.00737744, 0.00649983, 0.00534201, 0.00592962", \ + "0.02282, 0.0171528, 0.0154102, 0.0134182, 0.011341, 0.00909441, 0.00779189", \ + "0.0439977, 0.0356402, 0.0323972, 0.0288244, 0.0247458, 0.0206197, 0.0159608" \ ); } fall_power (POWER_7x7ds1) { index_1 ("0.0186, 0.0966, 0.174, 0.3294, 0.6408, 1.263, 2.5074"); index_2 ("0.001, 0.0234, 0.039, 0.0648, 0.108, 0.18, 0.3"); values ( \ - "0.00411663, 0.00474588, 0.00475161, 0.0046866, 0.00455546, 0.00425969, 0.00376261", \ - "0.00427605, 0.00459469, 0.00478955, 0.00470497, 0.00454374, 0.00429484, 0.00381122", \ - "0.00510675, 0.00481053, 0.00475398, 0.00489806, 0.00460425, 0.00440811, 0.0037746", \ - "0.00720363, 0.00565626, 0.00546589, 0.00517853, 0.00497804, 0.00449942, 0.00405516", \ - "0.0119975, 0.00848973, 0.00773616, 0.00704621, 0.00629573, 0.00548925, 0.0056605", \ - "0.021936, 0.0159005, 0.0140942, 0.0121499, 0.0105898, 0.00899076, 0.0070631", \ - "0.0425731, 0.0337857, 0.029996, 0.0262992, 0.0221855, 0.0184844, 0.0148454" \ + "0.00411744, 0.00474328, 0.00475996, 0.00468617, 0.00455233, 0.00427204, 0.00375771", \ + "0.00427425, 0.00458269, 0.00475346, 0.0047332, 0.00457476, 0.00434457, 0.00382458", \ + "0.00511196, 0.0047981, 0.00474245, 0.00488484, 0.00460746, 0.00426422, 0.00377411", \ + "0.00720407, 0.00566462, 0.00546252, 0.00518038, 0.00500013, 0.00450137, 0.00415017", \ + "0.0119963, 0.00846188, 0.0077287, 0.00706014, 0.00630023, 0.00548932, 0.00489631", \ + "0.0219365, 0.0158987, 0.0140835, 0.0121824, 0.0105897, 0.00902433, 0.00707167", \ + "0.0425776, 0.0337856, 0.0300469, 0.0262996, 0.0221856, 0.0185229, 0.0148086" \ ); } } @@ -5979,26 +5979,26 @@ library (sg13g2_stdcell_typ_1p50V_25C) { index_1 ("0.0186, 0.0966, 0.174, 0.3294, 0.6408, 1.263, 2.5074"); index_2 ("0.001, 0.0234, 0.039, 0.0648, 0.108, 0.18, 0.3"); values ( \ - "0.00426637, 0.00480621, 0.00479815, 0.00473479, 0.00457575, 0.00422558, 0.0037619", \ - "0.00443216, 0.004542, 0.00458955, 0.00454147, 0.00447115, 0.00419876, 0.00379188", \ - "0.00528371, 0.00475918, 0.00482818, 0.00461075, 0.0046291, 0.00415244, 0.00368225", \ - "0.00743521, 0.00593333, 0.00549446, 0.0052761, 0.00484997, 0.00441702, 0.00394642", \ - "0.0122969, 0.00944795, 0.00854202, 0.00756692, 0.00666629, 0.00554224, 0.00594835", \ - "0.0223652, 0.0171639, 0.0153817, 0.013553, 0.0115703, 0.00932315, 0.00850966", \ - "0.0434033, 0.0354328, 0.0322526, 0.0286454, 0.0247584, 0.02067, 0.0162497" \ + "0.00426384, 0.00480615, 0.00479807, 0.0047358, 0.00457548, 0.00422527, 0.00376159", \ + "0.00443206, 0.0045273, 0.00454735, 0.00453481, 0.00444872, 0.00420089, 0.00379193", \ + "0.00528375, 0.00474243, 0.00482211, 0.00475355, 0.00462924, 0.00415221, 0.0037045", \ + "0.00743453, 0.00593332, 0.00549755, 0.00539842, 0.00482687, 0.00445792, 0.00390706", \ + "0.0122983, 0.00944801, 0.00853238, 0.00755049, 0.00668835, 0.00554186, 0.00595587", \ + "0.0223656, 0.0171639, 0.0153817, 0.0135524, 0.0115621, 0.00932348, 0.00857247", \ + "0.0434033, 0.0354321, 0.0322521, 0.0286457, 0.0247584, 0.0206873, 0.0162432" \ ); } fall_power (POWER_7x7ds1) { index_1 ("0.0186, 0.0966, 0.174, 0.3294, 0.6408, 1.263, 2.5074"); index_2 ("0.001, 0.0234, 0.039, 0.0648, 0.108, 0.18, 0.3"); values ( \ - "0.00678201, 0.00738349, 0.00739509, 0.00730636, 0.00716481, 0.00688873, 0.00646713", \ - "0.00695288, 0.00724046, 0.00744656, 0.00743105, 0.00717634, 0.00692658, 0.00651798", \ - "0.00775772, 0.00744754, 0.00736705, 0.00745618, 0.0071982, 0.00726065, 0.00642", \ - "0.00979087, 0.00831614, 0.00809415, 0.0078274, 0.00768832, 0.00705413, 0.00729439", \ - "0.0145312, 0.0110937, 0.0104114, 0.00972386, 0.00888131, 0.00807655, 0.00768562", \ - "0.0243852, 0.0185054, 0.016685, 0.0149063, 0.0131911, 0.0116041, 0.00932076", \ - "0.0449159, 0.0362921, 0.0326126, 0.0288106, 0.0248141, 0.0208854, 0.0176073" \ + "0.00677864, 0.00739233, 0.00739465, 0.00730727, 0.00716589, 0.00688899, 0.00647167", \ + "0.00695311, 0.00723764, 0.00744664, 0.0072849, 0.00716514, 0.00691472, 0.00650997", \ + "0.00775404, 0.00744509, 0.00737866, 0.00755389, 0.00719127, 0.00699735, 0.00637615", \ + "0.00979182, 0.00831628, 0.00811279, 0.00782747, 0.00767089, 0.00705391, 0.00670915", \ + "0.0145308, 0.0110928, 0.0104044, 0.0097282, 0.00888428, 0.00807829, 0.00768721", \ + "0.0243902, 0.0185055, 0.0166873, 0.014905, 0.0131895, 0.0115369, 0.00961475", \ + "0.0449148, 0.036291, 0.0326415, 0.0288128, 0.0248128, 0.0208723, 0.0176127" \ ); } } @@ -6006,43 +6006,43 @@ library (sg13g2_stdcell_typ_1p50V_25C) { pin (A1) { direction : "input"; max_transition : 2.5074; - capacitance : 0.00323695; - rise_capacitance : 0.00314766; - rise_capacitance_range (0.00314766, 0.00314766); - fall_capacitance : 0.00332624; - fall_capacitance_range (0.00332624, 0.00332624); + capacitance : 0.00323694; + rise_capacitance : 0.0031477; + rise_capacitance_range (0.00293786, 0.00348657); + fall_capacitance : 0.00332617; + fall_capacitance_range (0.00287162, 0.00371922); } pin (A2) { direction : "input"; max_transition : 2.5074; - capacitance : 0.00328101; - rise_capacitance : 0.00332848; - rise_capacitance_range (0.00332848, 0.00332848); - fall_capacitance : 0.00323353; - fall_capacitance_range (0.00323353, 0.00323353); + capacitance : 0.00328102; + rise_capacitance : 0.00332849; + rise_capacitance_range (0.00284961, 0.00365603); + fall_capacitance : 0.00323356; + fall_capacitance_range (0.00285414, 0.00352764); } pin (B1) { direction : "input"; max_transition : 2.5074; - capacitance : 0.00317427; - rise_capacitance : 0.0033794; - rise_capacitance_range (0.0033794, 0.0033794); - fall_capacitance : 0.00296914; - fall_capacitance_range (0.00296914, 0.00296914); + capacitance : 0.00317423; + rise_capacitance : 0.00337936; + rise_capacitance_range (0.00271777, 0.00394185); + fall_capacitance : 0.0029691; + fall_capacitance_range (0.00279386, 0.00318363); } pin (B2) { direction : "input"; max_transition : 2.5074; - capacitance : 0.00310103; - rise_capacitance : 0.00317168; - rise_capacitance_range (0.00317168, 0.00317168); + capacitance : 0.00310102; + rise_capacitance : 0.00317165; + rise_capacitance_range (0.00268377, 0.0037996); fall_capacitance : 0.00303039; - fall_capacitance_range (0.00303039, 0.00303039); + fall_capacitance_range (0.00271751, 0.00335691); } } cell (sg13g2_and2_1) { area : 9.072; - cell_footprint : "AND2"; + cell_footprint : "and2"; cell_leakage_power : 392.858; leakage_power () { value : 489.112; @@ -6243,23 +6243,23 @@ library (sg13g2_stdcell_typ_1p50V_25C) { max_transition : 2.5074; capacitance : 0.00267731; rise_capacitance : 0.00266217; - rise_capacitance_range (0.00266217, 0.00266217); + rise_capacitance_range (0.00236461, 0.00288003); fall_capacitance : 0.00269244; - fall_capacitance_range (0.00269244, 0.00269244); + fall_capacitance_range (0.00237144, 0.00293355); } pin (B) { direction : "input"; max_transition : 2.5074; capacitance : 0.00269536; rise_capacitance : 0.00279181; - rise_capacitance_range (0.00279181, 0.00279181); + rise_capacitance_range (0.00233125, 0.00304384); fall_capacitance : 0.00259891; - fall_capacitance_range (0.00259891, 0.00259891); + fall_capacitance_range (0.0024004, 0.00275035); } } cell (sg13g2_and2_2) { area : 10.8864; - cell_footprint : "AND2"; + cell_footprint : "and2"; cell_leakage_power : 597.667; leakage_power () { value : 583.083; @@ -6460,23 +6460,23 @@ library (sg13g2_stdcell_typ_1p50V_25C) { max_transition : 2.5074; capacitance : 0.00265992; rise_capacitance : 0.00264669; - rise_capacitance_range (0.00264669, 0.00264669); + rise_capacitance_range (0.00240305, 0.00284267); fall_capacitance : 0.00267314; - fall_capacitance_range (0.00267314, 0.00267314); + fall_capacitance_range (0.00240835, 0.00288456); } pin (B) { direction : "input"; max_transition : 2.5074; capacitance : 0.00270378; rise_capacitance : 0.00280242; - rise_capacitance_range (0.00280242, 0.00280242); + rise_capacitance_range (0.00237083, 0.00303502); fall_capacitance : 0.00260513; - fall_capacitance_range (0.00260513, 0.00260513); + fall_capacitance_range (0.00243436, 0.00274638); } } cell (sg13g2_and3_1) { area : 12.7008; - cell_footprint : "AND3"; + cell_footprint : "and3"; cell_leakage_power : 437.262; leakage_power () { value : 686.736; @@ -6779,32 +6779,32 @@ library (sg13g2_stdcell_typ_1p50V_25C) { max_transition : 2.5074; capacitance : 0.00266654; rise_capacitance : 0.00261508; - rise_capacitance_range (0.00261508, 0.00261508); + rise_capacitance_range (0.00236312, 0.00278128); fall_capacitance : 0.00271801; - fall_capacitance_range (0.00271801, 0.00271801); + fall_capacitance_range (0.00233879, 0.00302608); } pin (B) { direction : "input"; max_transition : 2.5074; capacitance : 0.00266561; rise_capacitance : 0.0027182; - rise_capacitance_range (0.0027182, 0.0027182); + rise_capacitance_range (0.00228618, 0.00294113); fall_capacitance : 0.00261302; - fall_capacitance_range (0.00261302, 0.00261302); + fall_capacitance_range (0.00233745, 0.00283408); } pin (C) { direction : "input"; max_transition : 2.5074; capacitance : 0.00268226; rise_capacitance : 0.00278103; - rise_capacitance_range (0.00278103, 0.00278103); + rise_capacitance_range (0.00233035, 0.00305124); fall_capacitance : 0.00258349; - fall_capacitance_range (0.00258349, 0.00258349); + fall_capacitance_range (0.00240404, 0.00273266); } } cell (sg13g2_and3_2) { area : 12.7008; - cell_footprint : "AND3"; + cell_footprint : "and3"; cell_leakage_power : 660.542; leakage_power () { value : 780.679; @@ -7107,32 +7107,32 @@ library (sg13g2_stdcell_typ_1p50V_25C) { max_transition : 2.5074; capacitance : 0.00267271; rise_capacitance : 0.00262867; - rise_capacitance_range (0.00262867, 0.00262867); + rise_capacitance_range (0.00241838, 0.0027835); fall_capacitance : 0.00271675; - fall_capacitance_range (0.00271675, 0.00271675); + fall_capacitance_range (0.00240568, 0.00298426); } pin (B) { direction : "input"; max_transition : 2.5074; capacitance : 0.00266745; rise_capacitance : 0.00272624; - rise_capacitance_range (0.00272624, 0.00272624); + rise_capacitance_range (0.00231663, 0.00293811); fall_capacitance : 0.00260866; - fall_capacitance_range (0.00260866, 0.00260866); + fall_capacitance_range (0.00237101, 0.00281225); } pin (C) { direction : "input"; max_transition : 2.5074; capacitance : 0.00268123; rise_capacitance : 0.00278282; - rise_capacitance_range (0.00278282, 0.00278282); + rise_capacitance_range (0.00235221, 0.00303726); fall_capacitance : 0.00257964; - fall_capacitance_range (0.00257964, 0.00257964); + fall_capacitance_range (0.0024214, 0.00272384); } } cell (sg13g2_and4_1) { area : 14.5152; - cell_footprint : "AND4"; + cell_footprint : "and4"; cell_leakage_power : 465.125; leakage_power () { value : 420.784; @@ -7553,41 +7553,41 @@ library (sg13g2_stdcell_typ_1p50V_25C) { max_transition : 2.5074; capacitance : 0.00250223; rise_capacitance : 0.00242469; - rise_capacitance_range (0.00242469, 0.00242469); + rise_capacitance_range (0.00220194, 0.0025606); fall_capacitance : 0.00257978; - fall_capacitance_range (0.00257978, 0.00257978); + fall_capacitance_range (0.00216892, 0.00294402); } pin (B) { direction : "input"; max_transition : 2.5074; capacitance : 0.00264731; rise_capacitance : 0.00266968; - rise_capacitance_range (0.00266968, 0.00266968); + rise_capacitance_range (0.00226217, 0.00287564); fall_capacitance : 0.00262494; - fall_capacitance_range (0.00262494, 0.00262494); + fall_capacitance_range (0.00229844, 0.00290473); } pin (C) { direction : "input"; max_transition : 2.5074; capacitance : 0.00264303; rise_capacitance : 0.00270242; - rise_capacitance_range (0.00270242, 0.00270242); + rise_capacitance_range (0.0022737, 0.00295031); fall_capacitance : 0.00258364; - fall_capacitance_range (0.00258364, 0.00258364); + fall_capacitance_range (0.00233461, 0.00279436); } pin (D) { direction : "input"; max_transition : 2.5074; capacitance : 0.0026572; rise_capacitance : 0.00275521; - rise_capacitance_range (0.00275521, 0.00275521); + rise_capacitance_range (0.00231866, 0.0030445); fall_capacitance : 0.00255918; - fall_capacitance_range (0.00255918, 0.00255918); + fall_capacitance_range (0.00239389, 0.00271099); } } cell (sg13g2_and4_2) { area : 16.3296; - cell_footprint : "AND4"; + cell_footprint : "and4"; cell_leakage_power : 697.627; leakage_power () { value : 662.526; @@ -8008,41 +8008,41 @@ library (sg13g2_stdcell_typ_1p50V_25C) { max_transition : 2.5074; capacitance : 0.00249218; rise_capacitance : 0.00242665; - rise_capacitance_range (0.00242665, 0.00242665); + rise_capacitance_range (0.00224001, 0.00255566); fall_capacitance : 0.00255772; - fall_capacitance_range (0.00255772, 0.00255772); + fall_capacitance_range (0.00222461, 0.00287268); } pin (B) { direction : "input"; max_transition : 2.5074; capacitance : 0.00263552; rise_capacitance : 0.0026667; - rise_capacitance_range (0.0026667, 0.0026667); + rise_capacitance_range (0.00227657, 0.0028659); fall_capacitance : 0.00260435; - fall_capacitance_range (0.00260435, 0.00260435); + fall_capacitance_range (0.0023217, 0.00285688); } pin (C) { direction : "input"; max_transition : 2.5074; capacitance : 0.00263542; rise_capacitance : 0.00270043; - rise_capacitance_range (0.00270043, 0.00270043); + rise_capacitance_range (0.00228942, 0.00293861); fall_capacitance : 0.00257041; - fall_capacitance_range (0.00257041, 0.00257041); + fall_capacitance_range (0.0023493, 0.00276554); } pin (D) { direction : "input"; max_transition : 2.5074; capacitance : 0.00264994; rise_capacitance : 0.0027516; - rise_capacitance_range (0.0027516, 0.0027516); + rise_capacitance_range (0.00233212, 0.00302618); fall_capacitance : 0.00254827; - fall_capacitance_range (0.00254827, 0.00254827); + fall_capacitance_range (0.00239898, 0.00269295); } } cell (sg13g2_antennanp) { area : 5.4432; - cell_footprint : "NP_ant"; + cell_footprint : "antennanp"; cell_leakage_power : 6.75002; dont_touch : true; dont_use : true; @@ -8059,9 +8059,9 @@ library (sg13g2_stdcell_typ_1p50V_25C) { max_transition : 2.5074; capacitance : 0.001065; rise_capacitance : 0.00102605; - rise_capacitance_range (0.00102605, 0.00102605); + rise_capacitance_range (0.000261498, 0.00163032); fall_capacitance : 0.00110396; - fall_capacitance_range (0.00110396, 0.00110396); + fall_capacitance_range (0.000269858, 0.00174316); internal_power () { rise_power (passive_POWER_7x1ds1) { index_1 ("0.0186, 0.0966, 0.174, 0.3294, 0.6408, 1.263, 2.5074"); @@ -8080,7 +8080,7 @@ library (sg13g2_stdcell_typ_1p50V_25C) { } cell (sg13g2_buf_1) { area : 7.2576; - cell_footprint : "BU"; + cell_footprint : "buf"; cell_leakage_power : 290.438; leakage_power () { value : 310.136; @@ -8187,14 +8187,14 @@ library (sg13g2_stdcell_typ_1p50V_25C) { max_transition : 2.5074; capacitance : 0.00239619; rise_capacitance : 0.00243644; - rise_capacitance_range (0.00243644, 0.00243644); + rise_capacitance_range (0.00214362, 0.00266291); fall_capacitance : 0.00235595; - fall_capacitance_range (0.00235595, 0.00235595); + fall_capacitance_range (0.00213272, 0.00254951); } } cell (sg13g2_buf_16) { area : 45.36; - cell_footprint : "BU"; + cell_footprint : "buf"; cell_leakage_power : 3691.98; leakage_power () { value : 2952.77; @@ -8301,14 +8301,14 @@ library (sg13g2_stdcell_typ_1p50V_25C) { max_transition : 2.5074; capacitance : 0.0180024; rise_capacitance : 0.0183509; - rise_capacitance_range (0.0183509, 0.0183509); + rise_capacitance_range (0.0162489, 0.020076); fall_capacitance : 0.0176539; - fall_capacitance_range (0.0176539, 0.0176539); + fall_capacitance_range (0.0160501, 0.0189809); } } cell (sg13g2_buf_2) { area : 9.072; - cell_footprint : "BU"; + cell_footprint : "buf"; cell_leakage_power : 481.474; leakage_power () { value : 565.407; @@ -8415,14 +8415,14 @@ library (sg13g2_stdcell_typ_1p50V_25C) { max_transition : 2.5074; capacitance : 0.00276241; rise_capacitance : 0.00281288; - rise_capacitance_range (0.00281288, 0.00281288); + rise_capacitance_range (0.00252178, 0.00305354); fall_capacitance : 0.00271194; - fall_capacitance_range (0.00271194, 0.00271194); + fall_capacitance_range (0.00248211, 0.00291972); } } cell (sg13g2_buf_4) { area : 14.5152; - cell_footprint : "BU"; + cell_footprint : "buf"; cell_leakage_power : 883.106; leakage_power () { value : 678.321; @@ -8529,14 +8529,14 @@ library (sg13g2_stdcell_typ_1p50V_25C) { max_transition : 2.5074; capacitance : 0.00389809; rise_capacitance : 0.00401902; - rise_capacitance_range (0.00401902, 0.00401902); + rise_capacitance_range (0.00369559, 0.00424415); fall_capacitance : 0.00377716; - fall_capacitance_range (0.00377716, 0.00377716); + fall_capacitance_range (0.00340545, 0.00420522); } } cell (sg13g2_buf_8) { area : 23.5872; - cell_footprint : "BU"; + cell_footprint : "buf"; cell_leakage_power : 1845.99; leakage_power () { value : 1476.38; @@ -8643,14 +8643,14 @@ library (sg13g2_stdcell_typ_1p50V_25C) { max_transition : 2.5074; capacitance : 0.00904286; rise_capacitance : 0.00921689; - rise_capacitance_range (0.00921689, 0.00921689); + rise_capacitance_range (0.00822921, 0.0100696); fall_capacitance : 0.00886884; - fall_capacitance_range (0.00886884, 0.00886884); + fall_capacitance_range (0.00811571, 0.00952092); } } cell (sg13g2_decap_4) { area : 7.2576; - cell_footprint : "DECAP"; + cell_footprint : "decap"; cell_leakage_power : 1670.69; dont_touch : true; dont_use : true; @@ -8658,7 +8658,7 @@ library (sg13g2_stdcell_typ_1p50V_25C) { } cell (sg13g2_decap_8) { area : 12.7008; - cell_footprint : "DECAP"; + cell_footprint : "decap"; cell_leakage_power : 3341.41; dont_touch : true; dont_use : true; @@ -8666,7 +8666,7 @@ library (sg13g2_stdcell_typ_1p50V_25C) { } cell (sg13g2_dfrbp_1) { area : 52.6176; - cell_footprint : "dffrr"; + cell_footprint : "dfrbp"; cell_leakage_power : 1595.04; leakage_power () { value : 1348.76; @@ -8723,6 +8723,7 @@ library (sg13g2_stdcell_typ_1p50V_25C) { max_capacitance : 0.3; timing () { related_pin : "CLK"; + sdf_edges : start_edge; timing_sense : non_unate; timing_type : rising_edge; cell_rise (TIMING_DELAY_7x7ds1) { @@ -8780,6 +8781,7 @@ library (sg13g2_stdcell_typ_1p50V_25C) { } timing () { related_pin : "RESET_B"; + sdf_edges : start_edge; timing_sense : positive_unate; timing_type : clear; cell_fall (TIMING_DELAY_7x7ds1) { @@ -8867,6 +8869,7 @@ library (sg13g2_stdcell_typ_1p50V_25C) { max_capacitance : 0.3; timing () { related_pin : "CLK"; + sdf_edges : start_edge; timing_sense : non_unate; timing_type : rising_edge; cell_rise (TIMING_DELAY_7x7ds1) { @@ -8924,6 +8927,7 @@ library (sg13g2_stdcell_typ_1p50V_25C) { } timing () { related_pin : "RESET_B"; + sdf_edges : start_edge; timing_sense : negative_unate; timing_type : preset; cell_rise (TIMING_DELAY_7x7ds1) { @@ -9010,9 +9014,9 @@ library (sg13g2_stdcell_typ_1p50V_25C) { max_transition : 2.5074; capacitance : 0.0029626; rise_capacitance : 0.00314737; - rise_capacitance_range (0.00314737, 0.00314737); + rise_capacitance_range (0.0027982, 0.00344451); fall_capacitance : 0.00268544; - fall_capacitance_range (0.00268544, 0.00268544); + fall_capacitance_range (0.00268544, 0.00324013); timing () { related_pin : "CLK"; timing_type : min_pulse_width; @@ -9138,11 +9142,12 @@ library (sg13g2_stdcell_typ_1p50V_25C) { max_transition : 2.5074; capacitance : 0.00161658; rise_capacitance : 0.00148218; - rise_capacitance_range (0.00148218, 0.00148218); + rise_capacitance_range (0.00139452, 0.00176694); fall_capacitance : 0.00175099; - fall_capacitance_range (0.00175099, 0.00175099); + fall_capacitance_range (0.00175099, 0.00274921); timing () { related_pin : "CLK"; + sdf_edges : both_edges; timing_type : hold_rising; rise_constraint (CONSTRAINT_4x4) { index_1 ("0.0186, 0.51636, 1.263, 2.5074"); @@ -9167,6 +9172,7 @@ library (sg13g2_stdcell_typ_1p50V_25C) { } timing () { related_pin : "CLK"; + sdf_edges : both_edges; timing_type : setup_rising; rise_constraint (CONSTRAINT_4x4) { index_1 ("0.0186, 0.51636, 1.263, 2.5074"); @@ -9254,11 +9260,12 @@ library (sg13g2_stdcell_typ_1p50V_25C) { max_transition : 2.5074; capacitance : 0.00541224; rise_capacitance : 0.00564371; - rise_capacitance_range (0.00564371, 0.00564371); + rise_capacitance_range (0.00459264, 0.00654225); fall_capacitance : 0.0052469; - fall_capacitance_range (0.0052469, 0.0052469); + fall_capacitance_range (0.00487079, 0.00550541); timing () { related_pin : "CLK"; + sdf_edges : both_edges; timing_type : recovery_rising; rise_constraint (CONSTRAINT_4x4) { index_1 ("0.0186, 0.51636, 1.263, 2.5074"); @@ -9273,6 +9280,7 @@ library (sg13g2_stdcell_typ_1p50V_25C) { } timing () { related_pin : "CLK"; + sdf_edges : both_edges; timing_type : removal_rising; rise_constraint (CONSTRAINT_4x4) { index_1 ("0.0186, 0.51636, 1.263, 2.5074"); @@ -9371,14 +9379,14 @@ library (sg13g2_stdcell_typ_1p50V_25C) { } } ff (IQ,IQN) { - clear : "RESET_B'"; + clear : "!RESET_B"; clocked_on : "CLK"; next_state : "D"; } } cell (sg13g2_dfrbp_2) { area : 54.432; - cell_footprint : "dffrr"; + cell_footprint : "dfrbp"; cell_leakage_power : 1912.04; leakage_power () { value : 1672.43; @@ -9435,6 +9443,7 @@ library (sg13g2_stdcell_typ_1p50V_25C) { max_capacitance : 0.6; timing () { related_pin : "CLK"; + sdf_edges : start_edge; timing_sense : non_unate; timing_type : rising_edge; cell_rise (TIMING_DELAY_7x7ds1) { @@ -9492,6 +9501,7 @@ library (sg13g2_stdcell_typ_1p50V_25C) { } timing () { related_pin : "RESET_B"; + sdf_edges : start_edge; timing_sense : positive_unate; timing_type : clear; cell_fall (TIMING_DELAY_7x7ds1) { @@ -9579,6 +9589,7 @@ library (sg13g2_stdcell_typ_1p50V_25C) { max_capacitance : 0.6; timing () { related_pin : "CLK"; + sdf_edges : start_edge; timing_sense : non_unate; timing_type : rising_edge; cell_rise (TIMING_DELAY_7x7ds1) { @@ -9636,6 +9647,7 @@ library (sg13g2_stdcell_typ_1p50V_25C) { } timing () { related_pin : "RESET_B"; + sdf_edges : start_edge; timing_sense : negative_unate; timing_type : preset; cell_rise (TIMING_DELAY_7x7ds1) { @@ -9722,9 +9734,9 @@ library (sg13g2_stdcell_typ_1p50V_25C) { max_transition : 2.5074; capacitance : 0.00297177; rise_capacitance : 0.00315671; - rise_capacitance_range (0.00315671, 0.00315671); + rise_capacitance_range (0.00280523, 0.00345403); fall_capacitance : 0.00269436; - fall_capacitance_range (0.00269436, 0.00269436); + fall_capacitance_range (0.00269436, 0.00324902); timing () { related_pin : "CLK"; timing_type : min_pulse_width; @@ -9850,11 +9862,12 @@ library (sg13g2_stdcell_typ_1p50V_25C) { max_transition : 2.5074; capacitance : 0.00162045; rise_capacitance : 0.00148593; - rise_capacitance_range (0.00148593, 0.00148593); + rise_capacitance_range (0.00139702, 0.00177017); fall_capacitance : 0.00175496; - fall_capacitance_range (0.00175496, 0.00175496); + fall_capacitance_range (0.00175496, 0.00275271); timing () { related_pin : "CLK"; + sdf_edges : both_edges; timing_type : hold_rising; rise_constraint (CONSTRAINT_4x4) { index_1 ("0.0186, 0.51636, 1.263, 2.5074"); @@ -9879,6 +9892,7 @@ library (sg13g2_stdcell_typ_1p50V_25C) { } timing () { related_pin : "CLK"; + sdf_edges : both_edges; timing_type : setup_rising; rise_constraint (CONSTRAINT_4x4) { index_1 ("0.0186, 0.51636, 1.263, 2.5074"); @@ -9966,11 +9980,12 @@ library (sg13g2_stdcell_typ_1p50V_25C) { max_transition : 2.5074; capacitance : 0.00546369; rise_capacitance : 0.00569412; - rise_capacitance_range (0.00569412, 0.00569412); + rise_capacitance_range (0.00463486, 0.0065969); fall_capacitance : 0.0052991; - fall_capacitance_range (0.0052991, 0.0052991); + fall_capacitance_range (0.00492286, 0.00556442); timing () { related_pin : "CLK"; + sdf_edges : both_edges; timing_type : recovery_rising; rise_constraint (CONSTRAINT_4x4) { index_1 ("0.0186, 0.51636, 1.263, 2.5074"); @@ -9985,6 +10000,7 @@ library (sg13g2_stdcell_typ_1p50V_25C) { } timing () { related_pin : "CLK"; + sdf_edges : both_edges; timing_type : removal_rising; rise_constraint (CONSTRAINT_4x4) { index_1 ("0.0186, 0.51636, 1.263, 2.5074"); @@ -10083,7 +10099,7 @@ library (sg13g2_stdcell_typ_1p50V_25C) { } } ff (IQ,IQN) { - clear : "RESET_B'"; + clear : "!RESET_B"; clocked_on : "CLK"; next_state : "D"; } @@ -10147,89 +10163,91 @@ library (sg13g2_stdcell_typ_1p50V_25C) { max_capacitance : 0.3; timing () { related_pin : "CLK"; + sdf_edges : start_edge; timing_sense : non_unate; timing_type : rising_edge; cell_rise (TIMING_DELAY_7x7ds1) { index_1 ("0.0186, 0.0966, 0.174, 0.3294, 0.6408, 1.263, 2.5074"); index_2 ("0.001, 0.0234, 0.039, 0.0648, 0.108, 0.18, 0.3"); values ( \ - "0.10584, 0.152584, 0.183526, 0.234601, 0.319773, 0.461664, 0.698099", \ - "0.130563, 0.177351, 0.208347, 0.259309, 0.344517, 0.486419, 0.723927", \ - "0.145763, 0.192532, 0.223478, 0.274428, 0.359603, 0.501482, 0.737907", \ - "0.167471, 0.214231, 0.245182, 0.296221, 0.381411, 0.523226, 0.759619", \ - "0.197505, 0.244239, 0.275171, 0.326197, 0.411364, 0.553316, 0.789631", \ - "0.235489, 0.282366, 0.31326, 0.364305, 0.449485, 0.591395, 0.827808", \ - "0.282639, 0.329804, 0.36063, 0.411637, 0.497028, 0.638905, 0.875361" \ + "0.105825, 0.15262, 0.183517, 0.234501, 0.319674, 0.461516, 0.697936", \ + "0.130652, 0.177395, 0.208322, 0.259266, 0.344479, 0.486347, 0.723765", \ + "0.145771, 0.192524, 0.223458, 0.27439, 0.359533, 0.501371, 0.737697", \ + "0.16748, 0.214222, 0.245164, 0.296184, 0.381346, 0.52311, 0.759417", \ + "0.197517, 0.244238, 0.275156, 0.326163, 0.411299, 0.553197, 0.789424", \ + "0.235508, 0.28234, 0.313249, 0.364278, 0.449423, 0.591283, 0.827605", \ + "0.282674, 0.329822, 0.360749, 0.411722, 0.496869, 0.63869, 0.87517" \ ); } rise_transition (TIMING_DELAY_7x7ds1) { index_1 ("0.0186, 0.0966, 0.174, 0.3294, 0.6408, 1.263, 2.5074"); index_2 ("0.001, 0.0234, 0.039, 0.0648, 0.108, 0.18, 0.3"); values ( \ - "0.0126337, 0.0751372, 0.120805, 0.196446, 0.323227, 0.534692, 0.887053", \ - "0.0126423, 0.0751382, 0.120806, 0.196447, 0.324168, 0.535432, 0.88806", \ - "0.0126433, 0.0751392, 0.120807, 0.196448, 0.324169, 0.535433, 0.888061", \ - "0.012725, 0.0751421, 0.120808, 0.196449, 0.32417, 0.535434, 0.888062", \ - "0.0129382, 0.0751729, 0.120809, 0.196467, 0.324171, 0.535435, 0.888063", \ - "0.013448, 0.075225, 0.120814, 0.19647, 0.324172, 0.535436, 0.888064", \ - "0.014454, 0.075352, 0.120896, 0.196514, 0.324173, 0.535437, 0.888065" \ + "0.0125666, 0.07511, 0.120763, 0.196363, 0.323118, 0.534501, 0.886753", \ + "0.0126219, 0.075111, 0.120764, 0.196364, 0.324063, 0.53454, 0.887745", \ + "0.0126229, 0.075112, 0.120765, 0.196365, 0.324064, 0.534541, 0.887746", \ + "0.0127236, 0.0751164, 0.120766, 0.196366, 0.324065, 0.534542, 0.887747", \ + "0.0129373, 0.0751473, 0.120767, 0.196397, 0.324066, 0.534543, 0.887748", \ + "0.013446, 0.075208, 0.120783, 0.196398, 0.324067, 0.534604, 0.887749", \ + "0.014453, 0.075326, 0.120851, 0.196399, 0.324068, 0.534605, 0.88775" \ ); } cell_fall (TIMING_DELAY_7x7ds1) { index_1 ("0.0186, 0.0966, 0.174, 0.3294, 0.6408, 1.263, 2.5074"); index_2 ("0.001, 0.0234, 0.039, 0.0648, 0.108, 0.18, 0.3"); values ( \ - "0.104309, 0.144074, 0.169121, 0.210237, 0.279026, 0.393553, 0.584503", \ - "0.128835, 0.168555, 0.193586, 0.234731, 0.303483, 0.41806, 0.610043", \ - "0.143312, 0.183067, 0.208082, 0.24925, 0.31794, 0.432461, 0.623212", \ - "0.163289, 0.203044, 0.228082, 0.269227, 0.338032, 0.452455, 0.643212", \ - "0.190042, 0.229778, 0.254854, 0.29596, 0.364755, 0.479241, 0.670019", \ - "0.222168, 0.261886, 0.286945, 0.328076, 0.396858, 0.511361, 0.702136", \ - "0.26052, 0.300234, 0.325294, 0.366434, 0.435205, 0.54971, 0.740533" \ + "0.104305, 0.144079, 0.169099, 0.210225, 0.279025, 0.393527, 0.584424", \ + "0.128826, 0.168532, 0.193587, 0.234718, 0.303485, 0.418018, 0.610051", \ + "0.143303, 0.183058, 0.208074, 0.249245, 0.317934, 0.432457, 0.623252", \ + "0.163281, 0.203036, 0.228076, 0.269222, 0.338029, 0.452451, 0.643216", \ + "0.190035, 0.229773, 0.254849, 0.295957, 0.364754, 0.479241, 0.67002", \ + "0.222167, 0.261886, 0.286948, 0.32809, 0.396863, 0.511367, 0.702144", \ + "0.260534, 0.300249, 0.325311, 0.366453, 0.435224, 0.549732, 0.740556" \ ); } fall_transition (TIMING_DELAY_7x7ds1) { index_1 ("0.0186, 0.0966, 0.174, 0.3294, 0.6408, 1.263, 2.5074"); index_2 ("0.001, 0.0234, 0.039, 0.0648, 0.108, 0.18, 0.3"); values ( \ - "0.0104656, 0.0564151, 0.0897552, 0.145148, 0.238395, 0.393787, 0.652903", \ - "0.0104775, 0.0564161, 0.0897903, 0.145213, 0.238396, 0.395175, 0.654355", \ - "0.0104814, 0.0564234, 0.0897913, 0.145214, 0.238397, 0.395176, 0.654356", \ - "0.0104824, 0.0564244, 0.0897923, 0.145222, 0.238398, 0.395177, 0.654357", \ - "0.0104834, 0.0564254, 0.0897933, 0.145223, 0.238399, 0.395178, 0.654358", \ - "0.0104844, 0.0564264, 0.0897943, 0.145224, 0.2384, 0.395179, 0.654359", \ - "0.0104854, 0.0564274, 0.0897953, 0.145225, 0.238401, 0.39518, 0.65436" \ + "0.0104645, 0.0564131, 0.0897388, 0.145145, 0.238389, 0.393786, 0.652798", \ + "0.010469, 0.0564139, 0.0897889, 0.145212, 0.23839, 0.395212, 0.654107", \ + "0.0104791, 0.0564214, 0.0897899, 0.145213, 0.238391, 0.395213, 0.654108", \ + "0.0104801, 0.0564224, 0.0897909, 0.145221, 0.238392, 0.395214, 0.654109", \ + "0.0104811, 0.0564234, 0.0897919, 0.145222, 0.238393, 0.395215, 0.65411", \ + "0.0104821, 0.0564244, 0.0897929, 0.145223, 0.238394, 0.395216, 0.654111", \ + "0.0104831, 0.0564254, 0.0897939, 0.145224, 0.238395, 0.395217, 0.654112" \ ); } } timing () { related_pin : "RESET_B"; + sdf_edges : start_edge; timing_sense : positive_unate; timing_type : clear; cell_fall (TIMING_DELAY_7x7ds1) { index_1 ("0.0186, 0.0966, 0.174, 0.3294, 0.6408, 1.263, 2.5074"); index_2 ("0.001, 0.0234, 0.039, 0.0648, 0.108, 0.18, 0.3"); values ( \ - "0.14998, 0.18962, 0.21462, 0.255812, 0.324651, 0.439156, 0.62993", \ - "0.184449, 0.224159, 0.2492, 0.2904, 0.359218, 0.473758, 0.665017", \ - "0.210767, 0.250462, 0.275488, 0.316647, 0.385506, 0.500064, 0.69094", \ - "0.249066, 0.288789, 0.313788, 0.354995, 0.423828, 0.538337, 0.729069", \ - "0.304814, 0.344566, 0.369587, 0.410817, 0.47957, 0.594115, 0.784905", \ - "0.382134, 0.421931, 0.446954, 0.488137, 0.557001, 0.671546, 0.862343", \ - "0.495469, 0.53537, 0.560397, 0.601597, 0.67046, 0.785013, 0.975908" \ + "0.149894, 0.189714, 0.214631, 0.255742, 0.324641, 0.439169, 0.630054", \ + "0.184504, 0.224228, 0.249212, 0.290415, 0.359234, 0.473792, 0.665056", \ + "0.210741, 0.250469, 0.275481, 0.316651, 0.3855, 0.50007, 0.690845", \ + "0.249055, 0.288779, 0.313779, 0.354988, 0.423811, 0.538332, 0.729065", \ + "0.304802, 0.344554, 0.369576, 0.410808, 0.479565, 0.594108, 0.7849", \ + "0.38212, 0.421908, 0.446942, 0.488125, 0.55699, 0.671538, 0.862337", \ + "0.495454, 0.535358, 0.560385, 0.601586, 0.67045, 0.785005, 0.975901" \ ); } fall_transition (TIMING_DELAY_7x7ds1) { index_1 ("0.0186, 0.0966, 0.174, 0.3294, 0.6408, 1.263, 2.5074"); index_2 ("0.001, 0.0234, 0.039, 0.0648, 0.108, 0.18, 0.3"); values ( \ - "0.010427, 0.0563439, 0.0896557, 0.145185, 0.238401, 0.393805, 0.652746", \ - "0.010437, 0.0563641, 0.0896564, 0.145186, 0.238908, 0.393829, 0.652997", \ - "0.0104746, 0.0563651, 0.0897027, 0.145187, 0.238909, 0.39383, 0.652998", \ - "0.0105605, 0.0563661, 0.0897037, 0.145188, 0.23891, 0.393831, 0.653057", \ - "0.0106765, 0.0563931, 0.0897047, 0.145189, 0.238911, 0.393832, 0.653058", \ - "0.010782, 0.05643, 0.0897057, 0.145216, 0.238912, 0.393833, 0.653059", \ - "0.010915, 0.056478, 0.089761, 0.145217, 0.238913, 0.393834, 0.65306" \ + "0.0104411, 0.0563484, 0.0896553, 0.145185, 0.238401, 0.393804, 0.652816", \ + "0.0104421, 0.0563494, 0.0896575, 0.145186, 0.238908, 0.393828, 0.652996", \ + "0.0104563, 0.0563547, 0.0897021, 0.145198, 0.238909, 0.393829, 0.653115", \ + "0.0105588, 0.0563592, 0.0897031, 0.145199, 0.23891, 0.39383, 0.653116", \ + "0.0106749, 0.0563915, 0.0897041, 0.1452, 0.238911, 0.393831, 0.653117", \ + "0.010781, 0.056446, 0.0897051, 0.145215, 0.238912, 0.393832, 0.653118", \ + "0.010898, 0.056476, 0.089759, 0.145216, 0.238913, 0.393833, 0.653119" \ ); } } @@ -10239,26 +10257,26 @@ library (sg13g2_stdcell_typ_1p50V_25C) { index_1 ("0.0186, 0.0966, 0.174, 0.3294, 0.6408, 1.263, 2.5074"); index_2 ("0.001, 0.0234, 0.039, 0.0648, 0.108, 0.18, 0.3"); values ( \ - "0.039768, 0.0403071, 0.0403297, 0.0403034, 0.0401329, 0.039811, 0.0392512", \ - "0.0399771, 0.0405232, 0.040636, 0.0404817, 0.0405009, 0.0401677, 0.0398286", \ - "0.0408914, 0.0413998, 0.0413973, 0.0414885, 0.0411428, 0.0414758, 0.040402", \ - "0.0438092, 0.044367, 0.0444557, 0.0444193, 0.0442554, 0.0441163, 0.0436011", \ - "0.050165, 0.0506344, 0.0506797, 0.0507905, 0.0507535, 0.0503848, 0.0508719", \ - "0.0643828, 0.0648374, 0.0648026, 0.0649248, 0.0649353, 0.0649611, 0.0643614", \ - "0.0931578, 0.0935443, 0.0935621, 0.0936247, 0.0934412, 0.0935737, 0.0934393" \ + "0.0397442, 0.040307, 0.040327, 0.0402956, 0.0401123, 0.039796, 0.0392957", \ + "0.0400107, 0.0405234, 0.040699, 0.0404769, 0.0405001, 0.0400534, 0.0397916", \ + "0.0408916, 0.0413974, 0.0413659, 0.0414853, 0.0411986, 0.0413576, 0.0403751", \ + "0.043812, 0.0443644, 0.0444532, 0.0444215, 0.0442663, 0.0443983, 0.0436234", \ + "0.0501654, 0.0506396, 0.0506831, 0.0507928, 0.0507475, 0.0503532, 0.050465", \ + "0.064385, 0.064825, 0.0648113, 0.0649437, 0.0649417, 0.0649769, 0.0645528", \ + "0.0931751, 0.093554, 0.0935626, 0.0936414, 0.0935035, 0.0935766, 0.0934854" \ ); } fall_power (POWER_7x7ds1) { index_1 ("0.0186, 0.0966, 0.174, 0.3294, 0.6408, 1.263, 2.5074"); index_2 ("0.001, 0.0234, 0.039, 0.0648, 0.108, 0.18, 0.3"); values ( \ - "0.0411547, 0.0417076, 0.0417475, 0.0416411, 0.0415774, 0.0413001, 0.0407225", \ - "0.0415575, 0.0421509, 0.0421856, 0.0423814, 0.0419685, 0.0420825, 0.041557", \ - "0.0425694, 0.0432386, 0.0432516, 0.043102, 0.043258, 0.0427402, 0.0424288", \ - "0.0455522, 0.0461952, 0.0462938, 0.04636, 0.0460374, 0.045823, 0.0453501", \ - "0.0518574, 0.0524641, 0.0525938, 0.0525465, 0.0525382, 0.0525886, 0.0514504", \ - "0.0654722, 0.0660861, 0.0661783, 0.0660626, 0.0662132, 0.0661931, 0.0662258", \ - "0.0930579, 0.0937227, 0.0936823, 0.0936278, 0.0937259, 0.0934338, 0.0933471" \ + "0.0411571, 0.0417103, 0.0417568, 0.0416376, 0.0415241, 0.0413005, 0.0406882", \ + "0.0415664, 0.0421434, 0.042189, 0.0422329, 0.0419636, 0.0420934, 0.0415751", \ + "0.0425707, 0.0432438, 0.0432572, 0.0431062, 0.0432396, 0.042749, 0.0423879", \ + "0.0455514, 0.0461999, 0.0463001, 0.0463679, 0.0460511, 0.0459416, 0.0453854", \ + "0.0518581, 0.0524695, 0.0525999, 0.0525487, 0.052549, 0.052614, 0.0514624", \ + "0.0654753, 0.0660917, 0.0661844, 0.0660666, 0.0662272, 0.0662056, 0.0662256", \ + "0.093052, 0.0937353, 0.0936966, 0.0936366, 0.0937664, 0.0934386, 0.0933717" \ ); } } @@ -10273,13 +10291,13 @@ library (sg13g2_stdcell_typ_1p50V_25C) { index_1 ("0.0186, 0.0966, 0.174, 0.3294, 0.6408, 1.263, 2.5074"); index_2 ("0.001, 0.0234, 0.039, 0.0648, 0.108, 0.18, 0.3"); values ( \ - "0.0264606, 0.0270718, 0.0270752, 0.027011, 0.0268867, 0.0266372, 0.0260623", \ - "0.0266212, 0.0272323, 0.0273471, 0.0272466, 0.0272124, 0.0268361, 0.026462", \ - "0.0273622, 0.027936, 0.0279375, 0.0279426, 0.0282344, 0.0277358, 0.0269456", \ - "0.0289857, 0.0295674, 0.0296472, 0.0296323, 0.0293905, 0.0295217, 0.0286782", \ - "0.0325147, 0.0330748, 0.0331794, 0.0332554, 0.0332408, 0.032991, 0.032496", \ - "0.038761, 0.0392966, 0.0393736, 0.0392919, 0.0395077, 0.0395239, 0.0393349", \ - "0.0500704, 0.050624, 0.050634, 0.0505624, 0.0506202, 0.0504244, 0.0506613" \ + "0.0264413, 0.027058, 0.0270581, 0.0269976, 0.0268681, 0.026618, 0.0260584", \ + "0.0266308, 0.027245, 0.0273615, 0.0272436, 0.0272161, 0.0268413, 0.0264698", \ + "0.0273538, 0.0279369, 0.0279369, 0.0279417, 0.0279926, 0.027791, 0.0270518", \ + "0.0289909, 0.0295752, 0.0296582, 0.029525, 0.0293807, 0.0295333, 0.0286898", \ + "0.0325116, 0.0330757, 0.0331847, 0.0332561, 0.0332404, 0.0329991, 0.0325016", \ + "0.038758, 0.0392871, 0.0393912, 0.0392948, 0.0395102, 0.0395313, 0.0393013", \ + "0.0500729, 0.0506303, 0.0506378, 0.0505705, 0.0506442, 0.0504343, 0.0506633" \ ); } } @@ -10288,11 +10306,11 @@ library (sg13g2_stdcell_typ_1p50V_25C) { clock : true; direction : "input"; max_transition : 2.5074; - capacitance : 0.00293426; - rise_capacitance : 0.0031471; - rise_capacitance_range (0.0031471, 0.0031471); - fall_capacitance : 0.00268593; - fall_capacitance_range (0.00268593, 0.00268593); + capacitance : 0.0029343; + rise_capacitance : 0.00314712; + rise_capacitance_range (0.00279769, 0.00344452); + fall_capacitance : 0.00268601; + fall_capacitance_range (0.00268601, 0.00324018); timing () { related_pin : "CLK"; timing_type : min_pulse_width; @@ -10314,13 +10332,13 @@ library (sg13g2_stdcell_typ_1p50V_25C) { rise_power (passive_POWER_7x1ds1) { index_1 ("0.0186, 0.0966, 0.174, 0.3294, 0.6408, 1.263, 2.5074"); values ( \ - "0.0166714, 0.0169959, 0.017896, 0.0206973, 0.0266671, 0.0399026, 0.0671962" \ + "0.0166701, 0.0169948, 0.0178957, 0.0206982, 0.0266678, 0.0399057, 0.0672002" \ ); } fall_power (passive_POWER_7x1ds1) { index_1 ("0.0186, 0.0966, 0.174, 0.3294, 0.6408, 1.263, 2.5074"); values ( \ - "0.0333835, 0.0337799, 0.0351464, 0.0380279, 0.0447179, 0.0584772, 0.0875967" \ + "0.0333907, 0.033782, 0.0351466, 0.038028, 0.0447184, 0.0584784, 0.0876051" \ ); } } @@ -10334,7 +10352,7 @@ library (sg13g2_stdcell_typ_1p50V_25C) { fall_power (passive_POWER_7x1ds1) { index_1 ("0.0186, 0.0966, 0.174, 0.3294, 0.6408, 1.263, 2.5074"); values ( \ - "0.0323139, 0.0326711, 0.0340677, 0.0369595, 0.0437642, 0.057371, 0.0864918" \ + "0.0323077, 0.0326636, 0.0340687, 0.0369584, 0.0437638, 0.0573758, 0.0864941" \ ); } } @@ -10343,13 +10361,13 @@ library (sg13g2_stdcell_typ_1p50V_25C) { rise_power (passive_POWER_7x1ds1) { index_1 ("0.0186, 0.0966, 0.174, 0.3294, 0.6408, 1.263, 2.5074"); values ( \ - "0.0175399, 0.0178958, 0.0187565, 0.0215237, 0.0274561, 0.040673, 0.0679206" \ + "0.0175378, 0.0178637, 0.0187546, 0.0215236, 0.0274589, 0.0406788, 0.0679252" \ ); } fall_power (passive_POWER_7x1ds1) { index_1 ("0.0186, 0.0966, 0.174, 0.3294, 0.6408, 1.263, 2.5074"); values ( \ - "0.0165131, 0.0169703, 0.0182404, 0.0210878, 0.0275829, 0.0408218, 0.0689294" \ + "0.0165119, 0.0169883, 0.0182409, 0.021089, 0.0275834, 0.0408224, 0.0689311" \ ); } } @@ -10363,7 +10381,7 @@ library (sg13g2_stdcell_typ_1p50V_25C) { fall_power (passive_POWER_7x1ds1) { index_1 ("0.0186, 0.0966, 0.174, 0.3294, 0.6408, 1.263, 2.5074"); values ( \ - "0.0561375, 0.0564865, 0.0575136, 0.0603703, 0.0666247, 0.0801201, 0.108502" \ + "0.0561782, 0.0564889, 0.0575189, 0.0603798, 0.0666283, 0.0801257, 0.108506" \ ); } } @@ -10372,13 +10390,13 @@ library (sg13g2_stdcell_typ_1p50V_25C) { rise_power (passive_POWER_7x1ds1) { index_1 ("0.0186, 0.0966, 0.174, 0.3294, 0.6408, 1.263, 2.5074"); values ( \ - "0.0163272, 0.0166498, 0.01753, 0.0203293, 0.0262931, 0.0395243, 0.066785" \ + "0.016313, 0.0166497, 0.0175298, 0.0203293, 0.026294, 0.0395271, 0.066791" \ ); } fall_power (passive_POWER_7x1ds1) { index_1 ("0.0186, 0.0966, 0.174, 0.3294, 0.6408, 1.263, 2.5074"); values ( \ - "0.0164877, 0.0169378, 0.0182199, 0.0210773, 0.0275742, 0.0408291, 0.068945" \ + "0.0164838, 0.0169596, 0.0182221, 0.0210762, 0.0275743, 0.0408308, 0.0689466" \ ); } } @@ -10387,13 +10405,13 @@ library (sg13g2_stdcell_typ_1p50V_25C) { rise_power (passive_POWER_7x1ds1) { index_1 ("0.0186, 0.0966, 0.174, 0.3294, 0.6408, 1.263, 2.5074"); values ( \ - "0.0175744, 0.0179003, 0.0187833, 0.0215513, 0.027476, 0.0406981, 0.0679441" \ + "0.0175673, 0.0179107, 0.0187794, 0.0215517, 0.0274843, 0.0407002, 0.0679478" \ ); } fall_power (passive_POWER_7x1ds1) { index_1 ("0.0186, 0.0966, 0.174, 0.3294, 0.6408, 1.263, 2.5074"); values ( \ - "0.0164995, 0.016962, 0.0182212, 0.0210671, 0.0275637, 0.0407987, 0.0689078" \ + "0.0164946, 0.0169455, 0.0182216, 0.0210681, 0.0275639, 0.0408006, 0.0689092" \ ); } } @@ -10401,13 +10419,13 @@ library (sg13g2_stdcell_typ_1p50V_25C) { rise_power (passive_POWER_7x1ds1) { index_1 ("0.0186, 0.0966, 0.174, 0.3294, 0.6408, 1.263, 2.5074"); values ( \ - "0.0166714, 0.0169959, 0.017896, 0.0206973, 0.0266671, 0.0399026, 0.0671962" \ + "0.0166701, 0.0169948, 0.0178957, 0.0206982, 0.0266678, 0.0399057, 0.0672002" \ ); } fall_power (passive_POWER_7x1ds1) { index_1 ("0.0186, 0.0966, 0.174, 0.3294, 0.6408, 1.263, 2.5074"); values ( \ - "0.0323139, 0.0326711, 0.0340677, 0.0369595, 0.0437642, 0.057371, 0.0864918" \ + "0.0323077, 0.0326636, 0.0340687, 0.0369584, 0.0437638, 0.0573758, 0.0864941" \ ); } } @@ -10416,13 +10434,14 @@ library (sg13g2_stdcell_typ_1p50V_25C) { direction : "input"; nextstate_type : "data"; max_transition : 2.5074; - capacitance : 0.00147501; - rise_capacitance : 0.00146817; - rise_capacitance_range (0.00146817, 0.00146817); - fall_capacitance : 0.00148185; - fall_capacitance_range (0.00148185, 0.00148185); + capacitance : 0.00147497; + rise_capacitance : 0.00146816; + rise_capacitance_range (0.00139371, 0.00176694); + fall_capacitance : 0.00148179; + fall_capacitance_range (0.00148179, 0.00175571); timing () { related_pin : "CLK"; + sdf_edges : both_edges; timing_type : hold_rising; rise_constraint (CONSTRAINT_4x4) { index_1 ("0.0186, 0.51636, 1.263, 2.5074"); @@ -10438,7 +10457,7 @@ library (sg13g2_stdcell_typ_1p50V_25C) { index_1 ("0.0186, 0.51636, 1.263, 2.5074"); index_2 ("0.0186, 0.51636, 1.263, 2.5074"); values ( \ - "-0.0268971, 0.0321992, 0.0678652, 0.10171", \ + "-0.0268971, 0.0321992, 0.0678652, 0.0990114", \ "-0.13952, -0.0840332, -0.0488588, -0.0131473", \ "-0.214457, -0.174046, -0.140315, -0.108882", \ "-0.301389, -0.272749, -0.249887, -0.221365" \ @@ -10447,6 +10466,7 @@ library (sg13g2_stdcell_typ_1p50V_25C) { } timing () { related_pin : "CLK"; + sdf_edges : both_edges; timing_type : setup_rising; rise_constraint (CONSTRAINT_4x4) { index_1 ("0.0186, 0.51636, 1.263, 2.5074"); @@ -10455,7 +10475,7 @@ library (sg13g2_stdcell_typ_1p50V_25C) { "0.0684653, 0.0326922, 0.0170034, 0.00622484", \ "0.16947, 0.119684, 0.101307, 0.0901193", \ "0.229887, 0.179291, 0.159203, 0.145606", \ - "0.2825, 0.228765, 0.210337, 0.197753" \ + "0.2825, 0.231514, 0.210337, 0.197753" \ ); } fall_constraint (CONSTRAINT_4x4) { @@ -10474,13 +10494,13 @@ library (sg13g2_stdcell_typ_1p50V_25C) { rise_power (passive_POWER_7x1ds1) { index_1 ("0.0186, 0.0966, 0.174, 0.3294, 0.6408, 1.263, 2.5074"); values ( \ - "0.0020802, 0.00223425, 0.00267778, 0.00373716, 0.00595177, 0.0107846, 0.0206938" \ + "0.00207723, 0.00223294, 0.00267743, 0.0037366, 0.00595259, 0.0107859, 0.0206952" \ ); } fall_power (passive_POWER_7x1ds1) { index_1 ("0.0186, 0.0966, 0.174, 0.3294, 0.6408, 1.263, 2.5074"); values ( \ - "0.00167451, 0.00191345, 0.00240749, 0.00349232, 0.00598222, 0.0109278, 0.0212226" \ + "0.00167672, 0.00191295, 0.0024078, 0.00349285, 0.00598705, 0.0109283, 0.0212222" \ ); } } @@ -10489,13 +10509,13 @@ library (sg13g2_stdcell_typ_1p50V_25C) { rise_power (passive_POWER_7x1ds1) { index_1 ("0.0186, 0.0966, 0.174, 0.3294, 0.6408, 1.263, 2.5074"); values ( \ - "0.0184614, 0.0186691, 0.019088, 0.0201209, 0.0225641, 0.0280677, 0.0398127" \ + "0.0184504, 0.0186666, 0.0190878, 0.0201206, 0.0225647, 0.0280639, 0.0398077" \ ); } fall_power (passive_POWER_7x1ds1) { index_1 ("0.0186, 0.0966, 0.174, 0.3294, 0.6408, 1.263, 2.5074"); values ( \ - "0.0142001, 0.0143418, 0.0148717, 0.0161071, 0.0188863, 0.0248284, 0.0370692" \ + "0.0141775, 0.0143351, 0.0148668, 0.0161081, 0.0188862, 0.0248282, 0.0370686" \ ); } } @@ -10504,13 +10524,13 @@ library (sg13g2_stdcell_typ_1p50V_25C) { rise_power (passive_POWER_7x1ds1) { index_1 ("0.0186, 0.0966, 0.174, 0.3294, 0.6408, 1.263, 2.5074"); values ( \ - "-6.05879e-05, -5.51253e-05, -5.34721e-05, -5.30518e-05, -5.27152e-05, -5.23106e-05, -5.30267e-05" \ + "-5.67086e-05, -5.32433e-05, -5.36246e-05, -5.35317e-05, -5.32942e-05, -5.27723e-05, -5.40541e-05" \ ); } fall_power (passive_POWER_7x1ds1) { index_1 ("0.0186, 0.0966, 0.174, 0.3294, 0.6408, 1.263, 2.5074"); values ( \ - "0.000382985, 0.000388815, 0.000389341, 0.000388588, 0.000390555, 0.000390978, 0.000391421" \ + "0.000384881, 0.000389129, 0.000388903, 0.000388573, 0.000390547, 0.000390912, 0.000391406" \ ); } } @@ -10518,13 +10538,13 @@ library (sg13g2_stdcell_typ_1p50V_25C) { rise_power (passive_POWER_7x1ds1) { index_1 ("0.0186, 0.0966, 0.174, 0.3294, 0.6408, 1.263, 2.5074"); values ( \ - "0.0020802, 0.00223425, 0.00267778, 0.00373716, 0.00595177, 0.0107846, 0.0206938" \ + "0.00207723, 0.00223294, 0.00267743, 0.0037366, 0.00595259, 0.0107859, 0.0206952" \ ); } fall_power (passive_POWER_7x1ds1) { index_1 ("0.0186, 0.0966, 0.174, 0.3294, 0.6408, 1.263, 2.5074"); values ( \ - "0.00167451, 0.00191345, 0.00240749, 0.00349232, 0.00598222, 0.0109278, 0.0212226" \ + "0.00167672, 0.00191295, 0.0024078, 0.00349285, 0.00598705, 0.0109283, 0.0212222" \ ); } } @@ -10532,13 +10552,14 @@ library (sg13g2_stdcell_typ_1p50V_25C) { pin (RESET_B) { direction : "input"; max_transition : 2.5074; - capacitance : 0.00534644; - rise_capacitance : 0.00546594; - rise_capacitance_range (0.00546594, 0.00546594); - fall_capacitance : 0.00524685; - fall_capacitance_range (0.00524685, 0.00524685); + capacitance : 0.00534669; + rise_capacitance : 0.0054662; + rise_capacitance_range (0.00457912, 0.00618149); + fall_capacitance : 0.0052471; + fall_capacitance_range (0.0048699, 0.00548749); timing () { related_pin : "CLK"; + sdf_edges : both_edges; timing_type : recovery_rising; rise_constraint (CONSTRAINT_4x4) { index_1 ("0.0186, 0.51636, 1.263, 2.5074"); @@ -10553,6 +10574,7 @@ library (sg13g2_stdcell_typ_1p50V_25C) { } timing () { related_pin : "CLK"; + sdf_edges : both_edges; timing_type : removal_rising; rise_constraint (CONSTRAINT_4x4) { index_1 ("0.0186, 0.51636, 1.263, 2.5074"); @@ -10580,13 +10602,13 @@ library (sg13g2_stdcell_typ_1p50V_25C) { rise_power (passive_POWER_7x1ds1) { index_1 ("0.0186, 0.0966, 0.174, 0.3294, 0.6408, 1.263, 2.5074"); values ( \ - "0.00503667, 0.00496014, 0.00519803, 0.00593037, 0.00796795, 0.0125887, 0.0222224" \ + "0.00503721, 0.00495794, 0.00519797, 0.005929, 0.00796519, 0.0125878, 0.0222219" \ ); } fall_power (passive_POWER_7x1ds1) { index_1 ("0.0186, 0.0966, 0.174, 0.3294, 0.6408, 1.263, 2.5074"); values ( \ - "0.0405457, 0.0404437, 0.0415927, 0.0445226, 0.0518412, 0.0655943, 0.0927274" \ + "0.0405374, 0.0404673, 0.0415819, 0.0445182, 0.0518322, 0.0655961, 0.0927261" \ ); } } @@ -10595,13 +10617,13 @@ library (sg13g2_stdcell_typ_1p50V_25C) { rise_power (passive_POWER_7x1ds1) { index_1 ("0.0186, 0.0966, 0.174, 0.3294, 0.6408, 1.263, 2.5074"); values ( \ - "0.00113694, 0.00112895, 0.00113643, 0.00113797, 0.0011411, 0.00113594, 0.00113345" \ + "0.00113956, 0.00113047, 0.00113714, 0.00113779, 0.00114023, 0.00113832, 0.00113364" \ ); } fall_power (passive_POWER_7x1ds1) { index_1 ("0.0186, 0.0966, 0.174, 0.3294, 0.6408, 1.263, 2.5074"); values ( \ - "-0.00113694, -0.00112895, -0.00113643, -0.00113797, -0.0011411, -0.00113594, -0.00113345" \ + "-0.00113956, -0.00113047, -0.00113714, -0.00113779, -0.00114023, -0.00113832, -0.00113364" \ ); } } @@ -10610,13 +10632,13 @@ library (sg13g2_stdcell_typ_1p50V_25C) { rise_power (passive_POWER_7x1ds1) { index_1 ("0.0186, 0.0966, 0.174, 0.3294, 0.6408, 1.263, 2.5074"); values ( \ - "0.0216567, 0.0214616, 0.0217802, 0.0228097, 0.025873, 0.0329338, 0.0480739" \ + "0.0216612, 0.0214766, 0.0217824, 0.0228073, 0.0258716, 0.0329328, 0.0480698" \ ); } fall_power (passive_POWER_7x1ds1) { index_1 ("0.0186, 0.0966, 0.174, 0.3294, 0.6408, 1.263, 2.5074"); values ( \ - "0.0140004, 0.0137516, 0.014137, 0.0154411, 0.0189739, 0.0264975, 0.0423322" \ + "0.0140208, 0.0137607, 0.0141371, 0.0154374, 0.0189749, 0.0264978, 0.042327" \ ); } } @@ -10625,13 +10647,13 @@ library (sg13g2_stdcell_typ_1p50V_25C) { rise_power (passive_POWER_7x1ds1) { index_1 ("0.0186, 0.0966, 0.174, 0.3294, 0.6408, 1.263, 2.5074"); values ( \ - "0.00127341, 0.00126845, 0.00127791, 0.00127696, 0.00128448, 0.00127156, 0.00127447" \ + "0.0012785, 0.00126633, 0.00127954, 0.00127778, 0.00128432, 0.00127188, 0.00127079" \ ); } fall_power (passive_POWER_7x1ds1) { index_1 ("0.0186, 0.0966, 0.174, 0.3294, 0.6408, 1.263, 2.5074"); values ( \ - "-0.00127341, -0.00126845, -0.00127791, -0.00127696, -0.00128448, -0.00127156, -0.00127447" \ + "-0.0012785, -0.00126633, -0.00127954, -0.00127778, -0.00128432, -0.00127188, -0.00127079" \ ); } } @@ -10639,19 +10661,19 @@ library (sg13g2_stdcell_typ_1p50V_25C) { rise_power (passive_POWER_7x1ds1) { index_1 ("0.0186, 0.0966, 0.174, 0.3294, 0.6408, 1.263, 2.5074"); values ( \ - "0.00503667, 0.00496014, 0.00519803, 0.00593037, 0.00796795, 0.0125887, 0.0222224" \ + "0.00503721, 0.00495794, 0.00519797, 0.005929, 0.00796519, 0.0125878, 0.0222219" \ ); } fall_power (passive_POWER_7x1ds1) { index_1 ("0.0186, 0.0966, 0.174, 0.3294, 0.6408, 1.263, 2.5074"); values ( \ - "0.0140004, 0.0137516, 0.014137, 0.0154411, 0.0189739, 0.0264975, 0.0423322" \ + "0.0140208, 0.0137607, 0.0141371, 0.0154374, 0.0189749, 0.0264978, 0.042327" \ ); } } } ff (IQ,IQN) { - clear : "RESET_B'"; + clear : "!RESET_B"; clocked_on : "CLK"; next_state : "D"; } @@ -10715,18 +10737,19 @@ library (sg13g2_stdcell_typ_1p50V_25C) { max_capacitance : 0.6; timing () { related_pin : "CLK"; + sdf_edges : start_edge; timing_sense : non_unate; timing_type : rising_edge; cell_rise (TIMING_DELAY_7x7ds1) { index_1 ("0.0186, 0.0966, 0.174, 0.3294, 0.6408, 1.263, 2.5074"); index_2 ("0.001, 0.0468, 0.078, 0.1296, 0.216, 0.36, 0.6"); values ( \ - "0.113887, 0.164932, 0.195916, 0.246999, 0.332295, 0.474347, 0.711161", \ - "0.138597, 0.189568, 0.220671, 0.271718, 0.357017, 0.499037, 0.736664", \ + "0.113885, 0.164932, 0.195916, 0.246999, 0.332295, 0.474347, 0.711163", \ + "0.138597, 0.189579, 0.220697, 0.271718, 0.357017, 0.499136, 0.736664", \ "0.153764, 0.204804, 0.235812, 0.286872, 0.372134, 0.514216, 0.750909", \ "0.175368, 0.226386, 0.257391, 0.308495, 0.393771, 0.535745, 0.77243", \ "0.205321, 0.256404, 0.287412, 0.338435, 0.423773, 0.56576, 0.802443", \ - "0.243075, 0.294262, 0.325346, 0.376383, 0.461716, 0.603751, 0.840388", \ + "0.243075, 0.294262, 0.325346, 0.376382, 0.461716, 0.60374, 0.840388", \ "0.289361, 0.340991, 0.371957, 0.42297, 0.508263, 0.650389, 0.887169" \ ); } @@ -10734,21 +10757,21 @@ library (sg13g2_stdcell_typ_1p50V_25C) { index_1 ("0.0186, 0.0966, 0.174, 0.3294, 0.6408, 1.263, 2.5074"); index_2 ("0.001, 0.0468, 0.078, 0.1296, 0.216, 0.36, 0.6"); values ( \ - "0.0137094, 0.0759305, 0.121393, 0.197093, 0.324173, 0.535912, 0.88902", \ - "0.0137104, 0.0759315, 0.121394, 0.197094, 0.325924, 0.535981, 0.889803", \ - "0.0137608, 0.0759325, 0.121395, 0.197095, 0.325925, 0.535982, 0.889804", \ - "0.0138348, 0.0759404, 0.121396, 0.197097, 0.325926, 0.535983, 0.889805", \ - "0.014068, 0.0759609, 0.121397, 0.197098, 0.325927, 0.535984, 0.889806", \ - "0.014514, 0.076075, 0.121435, 0.197145, 0.325928, 0.535985, 0.889807", \ - "0.015296, 0.076252, 0.121518, 0.197146, 0.325929, 0.536048, 0.889808" \ + "0.0137108, 0.0759305, 0.121393, 0.197095, 0.324173, 0.535912, 0.889021", \ + "0.0137118, 0.075932, 0.121394, 0.197096, 0.325244, 0.535942, 0.889803", \ + "0.0137608, 0.075933, 0.121395, 0.197097, 0.325245, 0.535951, 0.889804", \ + "0.0138348, 0.0759404, 0.121396, 0.197098, 0.325246, 0.535952, 0.889805", \ + "0.014068, 0.0759609, 0.121397, 0.197099, 0.325247, 0.535953, 0.889806", \ + "0.014514, 0.076075, 0.121435, 0.197145, 0.325248, 0.53601, 0.889807", \ + "0.015296, 0.076252, 0.121518, 0.197146, 0.325249, 0.536048, 0.889808" \ ); } cell_fall (TIMING_DELAY_7x7ds1) { index_1 ("0.0186, 0.0966, 0.174, 0.3294, 0.6408, 1.263, 2.5074"); index_2 ("0.001, 0.0468, 0.078, 0.1296, 0.216, 0.36, 0.6"); values ( \ - "0.112735, 0.15775, 0.183061, 0.224405, 0.293343, 0.408126, 0.599227", \ - "0.137319, 0.182198, 0.207545, 0.248892, 0.317802, 0.432562, 0.623715", \ + "0.112709, 0.157696, 0.183063, 0.224398, 0.293327, 0.408128, 0.59919", \ + "0.137319, 0.182198, 0.207545, 0.248858, 0.317802, 0.432562, 0.623715", \ "0.151719, 0.196737, 0.222045, 0.263379, 0.332298, 0.447036, 0.638146", \ "0.171705, 0.21673, 0.242046, 0.283383, 0.352342, 0.467011, 0.658103", \ "0.198398, 0.243416, 0.268736, 0.31007, 0.37899, 0.493742, 0.684811", \ @@ -10760,25 +10783,26 @@ library (sg13g2_stdcell_typ_1p50V_25C) { index_1 ("0.0186, 0.0966, 0.174, 0.3294, 0.6408, 1.263, 2.5074"); index_2 ("0.001, 0.0468, 0.078, 0.1296, 0.216, 0.36, 0.6"); values ( \ - "0.0122551, 0.0589358, 0.0917603, 0.147087, 0.240404, 0.396164, 0.655873", \ - "0.0122561, 0.0589368, 0.0917613, 0.147088, 0.240412, 0.396267, 0.655925", \ - "0.0122571, 0.0589378, 0.0917623, 0.147142, 0.240457, 0.396268, 0.65684", \ - "0.0122581, 0.0589388, 0.0917633, 0.147143, 0.240458, 0.396269, 0.656841", \ - "0.0122591, 0.0589398, 0.0917643, 0.147144, 0.240459, 0.39627, 0.656842", \ - "0.0122601, 0.0589408, 0.091765, 0.147145, 0.24046, 0.396271, 0.656843", \ - "0.0122611, 0.0589418, 0.091766, 0.147146, 0.240461, 0.396272, 0.656844" \ + "0.0122424, 0.0589586, 0.0917604, 0.147097, 0.240405, 0.396163, 0.655872", \ + "0.0122476, 0.0589596, 0.0917614, 0.147098, 0.240412, 0.396267, 0.655925", \ + "0.0122535, 0.0589606, 0.0917624, 0.147142, 0.240457, 0.396268, 0.65684", \ + "0.0122555, 0.0589616, 0.0917634, 0.147143, 0.240458, 0.396269, 0.656841", \ + "0.0122565, 0.0589626, 0.0917644, 0.147144, 0.240459, 0.39627, 0.656842", \ + "0.0122575, 0.0589636, 0.091765, 0.147145, 0.24046, 0.396271, 0.656843", \ + "0.0122585, 0.0589646, 0.091766, 0.147146, 0.240461, 0.396272, 0.656844" \ ); } } timing () { related_pin : "RESET_B"; + sdf_edges : start_edge; timing_sense : positive_unate; timing_type : clear; cell_fall (TIMING_DELAY_7x7ds1) { index_1 ("0.0186, 0.0966, 0.174, 0.3294, 0.6408, 1.263, 2.5074"); index_2 ("0.001, 0.0468, 0.078, 0.1296, 0.216, 0.36, 0.6"); values ( \ - "0.157538, 0.202451, 0.227529, 0.268962, 0.337976, 0.452859, 0.644125", \ + "0.157538, 0.202451, 0.227533, 0.268962, 0.337976, 0.452859, 0.644125", \ "0.192099, 0.236967, 0.262224, 0.303585, 0.372603, 0.487448, 0.678768", \ "0.218324, 0.263174, 0.28848, 0.329844, 0.398856, 0.513602, 0.704728", \ "0.256678, 0.301508, 0.326858, 0.368183, 0.437203, 0.551994, 0.743174", \ @@ -10791,8 +10815,8 @@ library (sg13g2_stdcell_typ_1p50V_25C) { index_1 ("0.0186, 0.0966, 0.174, 0.3294, 0.6408, 1.263, 2.5074"); index_2 ("0.001, 0.0468, 0.078, 0.1296, 0.216, 0.36, 0.6"); values ( \ - "0.012121, 0.0587611, 0.0916721, 0.147074, 0.240358, 0.396165, 0.656069", \ - "0.0121347, 0.0587621, 0.0916731, 0.147075, 0.240495, 0.396184, 0.65607", \ + "0.012121, 0.0587612, 0.0916721, 0.147074, 0.240358, 0.396165, 0.656069", \ + "0.0121347, 0.0587622, 0.0916731, 0.147075, 0.240495, 0.396184, 0.65607", \ "0.0121357, 0.0588161, 0.0917181, 0.147141, 0.240496, 0.396186, 0.656071", \ "0.012191, 0.0588171, 0.0917191, 0.147142, 0.240497, 0.396187, 0.656072", \ "0.0122895, 0.0588583, 0.0917201, 0.147143, 0.240498, 0.396188, 0.656073", \ @@ -10807,21 +10831,21 @@ library (sg13g2_stdcell_typ_1p50V_25C) { index_1 ("0.0186, 0.0966, 0.174, 0.3294, 0.6408, 1.263, 2.5074"); index_2 ("0.001, 0.0468, 0.078, 0.1296, 0.216, 0.36, 0.6"); values ( \ - "0.0452207, 0.0459955, 0.0460791, 0.0460294, 0.0457454, 0.0451547, 0.0442459", \ - "0.0454141, 0.0461714, 0.0466239, 0.0463714, 0.0464715, 0.0453017, 0.0447022", \ + "0.0452185, 0.0459955, 0.0460792, 0.0460082, 0.0457454, 0.0451545, 0.0442462", \ + "0.0454141, 0.0461517, 0.0466122, 0.0463714, 0.0462741, 0.0452841, 0.0447022", \ "0.0463373, 0.0470994, 0.0471252, 0.047347, 0.0468933, 0.0477288, 0.0451852", \ "0.0492381, 0.0500131, 0.0502263, 0.0501509, 0.0499505, 0.0497264, 0.0483016", \ - "0.0555687, 0.0562687, 0.0563953, 0.0565843, 0.0566574, 0.0559864, 0.056817", \ - "0.0697349, 0.0702685, 0.0703411, 0.0706133, 0.070568, 0.0706911, 0.0697183", \ - "0.0986433, 0.0989262, 0.0989809, 0.0992196, 0.0989831, 0.0991305, 0.0991389" \ + "0.0555687, 0.0562687, 0.0563953, 0.0565843, 0.0566574, 0.0559864, 0.0568262", \ + "0.0697352, 0.0702685, 0.0703415, 0.0706117, 0.0705681, 0.0707383, 0.0697237", \ + "0.0986433, 0.0989262, 0.0989809, 0.0992201, 0.0989831, 0.0991305, 0.0991389" \ ); } fall_power (POWER_7x7ds1) { index_1 ("0.0186, 0.0966, 0.174, 0.3294, 0.6408, 1.263, 2.5074"); index_2 ("0.001, 0.0468, 0.078, 0.1296, 0.216, 0.36, 0.6"); values ( \ - "0.0464077, 0.0474586, 0.0475645, 0.0475077, 0.0472387, 0.0466033, 0.0455989", \ - "0.0469173, 0.0478859, 0.0480361, 0.048129, 0.0479737, 0.0471203, 0.0461072", \ + "0.0463957, 0.0474609, 0.0475708, 0.0474941, 0.0472068, 0.0466138, 0.0455544", \ + "0.0469173, 0.0478859, 0.0480361, 0.0481179, 0.0479737, 0.0471203, 0.0461072", \ "0.0479316, 0.0490806, 0.0491057, 0.0489513, 0.0494131, 0.0481226, 0.0478069", \ "0.0509269, 0.0520326, 0.0522414, 0.0524016, 0.0519502, 0.0515318, 0.0512511", \ "0.0572003, 0.0582487, 0.0585436, 0.0585688, 0.0586122, 0.0583423, 0.0565308", \ @@ -10841,12 +10865,12 @@ library (sg13g2_stdcell_typ_1p50V_25C) { index_1 ("0.0186, 0.0966, 0.174, 0.3294, 0.6408, 1.263, 2.5074"); index_2 ("0.001, 0.0468, 0.078, 0.1296, 0.216, 0.36, 0.6"); values ( \ - "0.0316099, 0.0325778, 0.0326307, 0.0325536, 0.0323204, 0.031781, 0.0308669", \ + "0.0316122, 0.03258, 0.0326334, 0.0325493, 0.0323226, 0.0317833, 0.0308692", \ "0.0318344, 0.0327864, 0.0331201, 0.0328162, 0.0325888, 0.0320586, 0.0311462", \ "0.032507, 0.03344, 0.0334827, 0.0335464, 0.0341014, 0.0338258, 0.0315888", \ "0.0341487, 0.035151, 0.0352703, 0.0352495, 0.0347041, 0.0354554, 0.0331873", \ "0.0376964, 0.0386005, 0.0387619, 0.0389788, 0.0390202, 0.0385744, 0.0376535", \ - "0.0438561, 0.0446436, 0.0449322, 0.0447467, 0.0451332, 0.0452308, 0.0448619", \ + "0.0438562, 0.0446437, 0.0449323, 0.0447468, 0.0451333, 0.0452309, 0.044862", \ "0.0551534, 0.055851, 0.0559412, 0.0558609, 0.056071, 0.0556577, 0.0561748" \ ); } @@ -10858,9 +10882,9 @@ library (sg13g2_stdcell_typ_1p50V_25C) { max_transition : 2.5074; capacitance : 0.00294298; rise_capacitance : 0.00315607; - rise_capacitance_range (0.00315607, 0.00315607); + rise_capacitance_range (0.00280464, 0.00345411); fall_capacitance : 0.00269438; - fall_capacitance_range (0.00269438, 0.00269438); + fall_capacitance_range (0.00269438, 0.00324907); timing () { related_pin : "CLK"; timing_type : min_pulse_width; @@ -10882,13 +10906,13 @@ library (sg13g2_stdcell_typ_1p50V_25C) { rise_power (passive_POWER_7x1ds1) { index_1 ("0.0186, 0.0966, 0.174, 0.3294, 0.6408, 1.263, 2.5074"); values ( \ - "0.0167559, 0.0170672, 0.0179843, 0.020836, 0.026749, 0.0400097, 0.0672085" \ + "0.0167502, 0.0170672, 0.0179843, 0.020836, 0.026749, 0.0400097, 0.0672085" \ ); } fall_power (passive_POWER_7x1ds1) { index_1 ("0.0186, 0.0966, 0.174, 0.3294, 0.6408, 1.263, 2.5074"); values ( \ - "0.0351025, 0.0354396, 0.0368605, 0.0397253, 0.0464122, 0.0601593, 0.0892501" \ + "0.0351034, 0.0354396, 0.0368605, 0.0397253, 0.0464121, 0.0601593, 0.0892501" \ ); } } @@ -10902,7 +10926,7 @@ library (sg13g2_stdcell_typ_1p50V_25C) { fall_power (passive_POWER_7x1ds1) { index_1 ("0.0186, 0.0966, 0.174, 0.3294, 0.6408, 1.263, 2.5074"); values ( \ - "0.0323392, 0.0326945, 0.034088, 0.0369557, 0.0437661, 0.0573651, 0.0864657" \ + "0.0323247, 0.0326945, 0.034088, 0.0369557, 0.0437661, 0.0573651, 0.0864657" \ ); } } @@ -10911,13 +10935,13 @@ library (sg13g2_stdcell_typ_1p50V_25C) { rise_power (passive_POWER_7x1ds1) { index_1 ("0.0186, 0.0966, 0.174, 0.3294, 0.6408, 1.263, 2.5074"); values ( \ - "0.0176285, 0.0179875, 0.0188483, 0.0216603, 0.0275474, 0.0407626, 0.0679771" \ + "0.0176283, 0.0179876, 0.0188483, 0.0216603, 0.0275474, 0.0407626, 0.0679771" \ ); } fall_power (passive_POWER_7x1ds1) { index_1 ("0.0186, 0.0966, 0.174, 0.3294, 0.6408, 1.263, 2.5074"); values ( \ - "0.0165537, 0.0169919, 0.0182809, 0.0211314, 0.0276252, 0.040855, 0.0689651" \ + "0.0165536, 0.0169919, 0.0182809, 0.0211314, 0.0276252, 0.040855, 0.0689651" \ ); } } @@ -10931,7 +10955,7 @@ library (sg13g2_stdcell_typ_1p50V_25C) { fall_power (passive_POWER_7x1ds1) { index_1 ("0.0186, 0.0966, 0.174, 0.3294, 0.6408, 1.263, 2.5074"); values ( \ - "0.0633705, 0.063573, 0.0646616, 0.0674542, 0.0737202, 0.0872904, 0.115297" \ + "0.0633705, 0.063573, 0.0646616, 0.0674542, 0.0737202, 0.0872911, 0.115297" \ ); } } @@ -10940,13 +10964,13 @@ library (sg13g2_stdcell_typ_1p50V_25C) { rise_power (passive_POWER_7x1ds1) { index_1 ("0.0186, 0.0966, 0.174, 0.3294, 0.6408, 1.263, 2.5074"); values ( \ - "0.0164149, 0.0167525, 0.017626, 0.0204362, 0.026381, 0.0396154, 0.0668732" \ + "0.0164059, 0.0167525, 0.017626, 0.0204362, 0.026381, 0.0396154, 0.0668732" \ ); } fall_power (passive_POWER_7x1ds1) { index_1 ("0.0186, 0.0966, 0.174, 0.3294, 0.6408, 1.263, 2.5074"); values ( \ - "0.0165427, 0.0169825, 0.0182671, 0.0211235, 0.0276168, 0.0408899, 0.0689765" \ + "0.016543, 0.0169825, 0.0182671, 0.0211235, 0.0276168, 0.0408898, 0.0689765" \ ); } } @@ -10955,13 +10979,13 @@ library (sg13g2_stdcell_typ_1p50V_25C) { rise_power (passive_POWER_7x1ds1) { index_1 ("0.0186, 0.0966, 0.174, 0.3294, 0.6408, 1.263, 2.5074"); values ( \ - "0.0176736, 0.0180125, 0.018874, 0.0216825, 0.0275668, 0.0407965, 0.0679582" \ + "0.0176746, 0.0180125, 0.018874, 0.0216825, 0.0275668, 0.040796, 0.0679582" \ ); } fall_power (passive_POWER_7x1ds1) { index_1 ("0.0186, 0.0966, 0.174, 0.3294, 0.6408, 1.263, 2.5074"); values ( \ - "0.0165453, 0.0169695, 0.0182628, 0.0211102, 0.027605, 0.0408338, 0.0689418" \ + "0.0165453, 0.0169695, 0.0182628, 0.0211102, 0.027605, 0.0408337, 0.0689416" \ ); } } @@ -10969,13 +10993,13 @@ library (sg13g2_stdcell_typ_1p50V_25C) { rise_power (passive_POWER_7x1ds1) { index_1 ("0.0186, 0.0966, 0.174, 0.3294, 0.6408, 1.263, 2.5074"); values ( \ - "0.0167559, 0.0170672, 0.0179843, 0.020836, 0.026749, 0.0400097, 0.0672085" \ + "0.0167502, 0.0170672, 0.0179843, 0.020836, 0.026749, 0.0400097, 0.0672085" \ ); } fall_power (passive_POWER_7x1ds1) { index_1 ("0.0186, 0.0966, 0.174, 0.3294, 0.6408, 1.263, 2.5074"); values ( \ - "0.0323392, 0.0326945, 0.034088, 0.0369557, 0.0437661, 0.0573651, 0.0864657" \ + "0.0323247, 0.0326945, 0.034088, 0.0369557, 0.0437661, 0.0573651, 0.0864657" \ ); } } @@ -10986,11 +11010,12 @@ library (sg13g2_stdcell_typ_1p50V_25C) { max_transition : 2.5074; capacitance : 0.00147891; rise_capacitance : 0.001472; - rise_capacitance_range (0.001472, 0.001472); + rise_capacitance_range (0.00139713, 0.00177022); fall_capacitance : 0.00148582; - fall_capacitance_range (0.00148582, 0.00148582); + fall_capacitance_range (0.00148582, 0.00175837); timing () { related_pin : "CLK"; + sdf_edges : both_edges; timing_type : hold_rising; rise_constraint (CONSTRAINT_4x4) { index_1 ("0.0186, 0.51636, 1.263, 2.5074"); @@ -11006,7 +11031,7 @@ library (sg13g2_stdcell_typ_1p50V_25C) { index_1 ("0.0186, 0.51636, 1.263, 2.5074"); index_2 ("0.0186, 0.51636, 1.263, 2.5074"); values ( \ - "-0.0268971, 0.0346951, 0.0678652, 0.10171", \ + "-0.0268971, 0.0321992, 0.0678652, 0.10171", \ "-0.142016, -0.0840332, -0.0488588, -0.0131473", \ "-0.217028, -0.171424, -0.140315, -0.108882", \ "-0.304087, -0.272749, -0.249887, -0.221365" \ @@ -11015,6 +11040,7 @@ library (sg13g2_stdcell_typ_1p50V_25C) { } timing () { related_pin : "CLK"; + sdf_edges : both_edges; timing_type : setup_rising; rise_constraint (CONSTRAINT_4x4) { index_1 ("0.0186, 0.51636, 1.263, 2.5074"); @@ -11048,7 +11074,7 @@ library (sg13g2_stdcell_typ_1p50V_25C) { fall_power (passive_POWER_7x1ds1) { index_1 ("0.0186, 0.0966, 0.174, 0.3294, 0.6408, 1.263, 2.5074"); values ( \ - "0.00169007, 0.00192521, 0.00242041, 0.00350497, 0.00599895, 0.0109267, 0.0212313" \ + "0.00169008, 0.00192522, 0.00242042, 0.00350497, 0.00599896, 0.0109267, 0.0212313" \ ); } } @@ -11063,7 +11089,7 @@ library (sg13g2_stdcell_typ_1p50V_25C) { fall_power (passive_POWER_7x1ds1) { index_1 ("0.0186, 0.0966, 0.174, 0.3294, 0.6408, 1.263, 2.5074"); values ( \ - "0.0142168, 0.0143545, 0.0148921, 0.0161386, 0.0189081, 0.0248494, 0.0370971" \ + "0.0142235, 0.0143545, 0.0148921, 0.0161386, 0.0189081, 0.0248494, 0.0370971" \ ); } } @@ -11072,13 +11098,13 @@ library (sg13g2_stdcell_typ_1p50V_25C) { rise_power (passive_POWER_7x1ds1) { index_1 ("0.0186, 0.0966, 0.174, 0.3294, 0.6408, 1.263, 2.5074"); values ( \ - "-5.24549e-05, -5.11019e-05, -5.15914e-05, -4.94414e-05, -4.83417e-05, -4.79848e-05, -4.88011e-05" \ + "-5.24542e-05, -5.1105e-05, -5.15915e-05, -4.94433e-05, -5.07209e-05, -4.79849e-05, -4.88012e-05" \ ); } fall_power (passive_POWER_7x1ds1) { index_1 ("0.0186, 0.0966, 0.174, 0.3294, 0.6408, 1.263, 2.5074"); values ( \ - "0.000381865, 0.000384613, 0.000384462, 0.000384301, 0.000386272, 0.000386419, 0.000387281" \ + "0.000381591, 0.000384616, 0.000384457, 0.000384304, 0.000386275, 0.000386414, 0.000387277" \ ); } } @@ -11092,7 +11118,7 @@ library (sg13g2_stdcell_typ_1p50V_25C) { fall_power (passive_POWER_7x1ds1) { index_1 ("0.0186, 0.0966, 0.174, 0.3294, 0.6408, 1.263, 2.5074"); values ( \ - "0.00169007, 0.00192521, 0.00242041, 0.00350497, 0.00599895, 0.0109267, 0.0212313" \ + "0.00169008, 0.00192522, 0.00242042, 0.00350497, 0.00599896, 0.0109267, 0.0212313" \ ); } } @@ -11102,11 +11128,12 @@ library (sg13g2_stdcell_typ_1p50V_25C) { max_transition : 2.5074; capacitance : 0.00539039; rise_capacitance : 0.00550953; - rise_capacitance_range (0.00550953, 0.00550953); + rise_capacitance_range (0.00461688, 0.00622641); fall_capacitance : 0.00529111; - fall_capacitance_range (0.00529111, 0.00529111); + fall_capacitance_range (0.0049144, 0.00553182); timing () { related_pin : "CLK"; + sdf_edges : both_edges; timing_type : recovery_rising; rise_constraint (CONSTRAINT_4x4) { index_1 ("0.0186, 0.51636, 1.263, 2.5074"); @@ -11121,6 +11148,7 @@ library (sg13g2_stdcell_typ_1p50V_25C) { } timing () { related_pin : "CLK"; + sdf_edges : both_edges; timing_type : removal_rising; rise_constraint (CONSTRAINT_4x4) { index_1 ("0.0186, 0.51636, 1.263, 2.5074"); @@ -11148,13 +11176,13 @@ library (sg13g2_stdcell_typ_1p50V_25C) { rise_power (passive_POWER_7x1ds1) { index_1 ("0.0186, 0.0966, 0.174, 0.3294, 0.6408, 1.263, 2.5074"); values ( \ - "0.00509566, 0.00501116, 0.00524755, 0.00597402, 0.00801426, 0.0126254, 0.022242" \ + "0.00509566, 0.00501116, 0.00524755, 0.00597401, 0.00801426, 0.0126254, 0.022242" \ ); } fall_power (passive_POWER_7x1ds1) { index_1 ("0.0186, 0.0966, 0.174, 0.3294, 0.6408, 1.263, 2.5074"); values ( \ - "0.0458292, 0.0457932, 0.0468746, 0.0498423, 0.0571346, 0.0709139, 0.0980309" \ + "0.0458293, 0.0457932, 0.0468746, 0.0498423, 0.0571346, 0.070914, 0.0980309" \ ); } } @@ -11163,13 +11191,13 @@ library (sg13g2_stdcell_typ_1p50V_25C) { rise_power (passive_POWER_7x1ds1) { index_1 ("0.0186, 0.0966, 0.174, 0.3294, 0.6408, 1.263, 2.5074"); values ( \ - "0.00119043, 0.00118217, 0.0011885, 0.0011883, 0.00119064, 0.0011916, 0.00119093" \ + "0.00119044, 0.00118217, 0.0011885, 0.00118831, 0.00119064, 0.0011916, 0.00119092" \ ); } fall_power (passive_POWER_7x1ds1) { index_1 ("0.0186, 0.0966, 0.174, 0.3294, 0.6408, 1.263, 2.5074"); values ( \ - "-0.00119043, -0.00118217, -0.0011885, -0.0011883, -0.00119064, -0.0011916, -0.00119093" \ + "-0.00119044, -0.00118217, -0.0011885, -0.00118831, -0.00119064, -0.0011916, -0.00119092" \ ); } } @@ -11184,7 +11212,7 @@ library (sg13g2_stdcell_typ_1p50V_25C) { fall_power (passive_POWER_7x1ds1) { index_1 ("0.0186, 0.0966, 0.174, 0.3294, 0.6408, 1.263, 2.5074"); values ( \ - "0.0140079, 0.0137418, 0.0141186, 0.0154158, 0.0189544, 0.0264717, 0.0423537" \ + "0.0140056, 0.0137418, 0.0141186, 0.0154158, 0.0189544, 0.0264716, 0.0423537" \ ); } } @@ -11193,13 +11221,13 @@ library (sg13g2_stdcell_typ_1p50V_25C) { rise_power (passive_POWER_7x1ds1) { index_1 ("0.0186, 0.0966, 0.174, 0.3294, 0.6408, 1.263, 2.5074"); values ( \ - "0.00132274, 0.00132017, 0.00132998, 0.00133101, 0.00133436, 0.00132138, 0.00132613" \ + "0.00132273, 0.00132017, 0.00132998, 0.001331, 0.00133436, 0.00132137, 0.00132613" \ ); } fall_power (passive_POWER_7x1ds1) { index_1 ("0.0186, 0.0966, 0.174, 0.3294, 0.6408, 1.263, 2.5074"); values ( \ - "-0.00132274, -0.00132017, -0.00132998, -0.00133101, -0.00133436, -0.00132138, -0.00132613" \ + "-0.00132273, -0.00132017, -0.00132998, -0.001331, -0.00133436, -0.00132137, -0.00132613" \ ); } } @@ -11207,26 +11235,26 @@ library (sg13g2_stdcell_typ_1p50V_25C) { rise_power (passive_POWER_7x1ds1) { index_1 ("0.0186, 0.0966, 0.174, 0.3294, 0.6408, 1.263, 2.5074"); values ( \ - "0.00509566, 0.00501116, 0.00524755, 0.00597402, 0.00801426, 0.0126254, 0.022242" \ + "0.00509566, 0.00501116, 0.00524755, 0.00597401, 0.00801426, 0.0126254, 0.022242" \ ); } fall_power (passive_POWER_7x1ds1) { index_1 ("0.0186, 0.0966, 0.174, 0.3294, 0.6408, 1.263, 2.5074"); values ( \ - "0.0140079, 0.0137418, 0.0141186, 0.0154158, 0.0189544, 0.0264717, 0.0423537" \ + "0.0140056, 0.0137418, 0.0141186, 0.0154158, 0.0189544, 0.0264716, 0.0423537" \ ); } } } ff (IQ,IQN) { - clear : "RESET_B'"; + clear : "!RESET_B"; clocked_on : "CLK"; next_state : "D"; } } cell (sg13g2_dlhq_1) { area : 30.8448; - cell_footprint : "DLHQ"; + cell_footprint : "dlhq"; cell_leakage_power : 1024.94; leakage_power () { value : 1040.35; @@ -11316,6 +11344,7 @@ library (sg13g2_stdcell_typ_1p50V_25C) { } timing () { related_pin : "GATE"; + sdf_edges : start_edge; timing_sense : non_unate; timing_type : rising_edge; cell_rise (TIMING_DELAY_7x7ds1) { @@ -11435,11 +11464,12 @@ library (sg13g2_stdcell_typ_1p50V_25C) { max_transition : 2.5074; capacitance : 0.00241546; rise_capacitance : 0.00245504; - rise_capacitance_range (0.00245504, 0.00245504); + rise_capacitance_range (0.00216344, 0.00268193); fall_capacitance : 0.00237588; - fall_capacitance_range (0.00237588, 0.00237588); + fall_capacitance_range (0.00215327, 0.00257289); timing () { related_pin : "GATE"; + sdf_edges : both_edges; timing_type : hold_falling; rise_constraint (CONSTRAINT_4x4) { index_1 ("0.0186, 0.51636, 1.263, 2.5074"); @@ -11464,6 +11494,7 @@ library (sg13g2_stdcell_typ_1p50V_25C) { } timing () { related_pin : "GATE"; + sdf_edges : both_edges; timing_type : setup_falling; rise_constraint (CONSTRAINT_4x4) { index_1 ("0.0186, 0.51636, 1.263, 2.5074"); @@ -11537,9 +11568,9 @@ library (sg13g2_stdcell_typ_1p50V_25C) { max_transition : 2.5074; capacitance : 0.00245298; rise_capacitance : 0.00278209; - rise_capacitance_range (0.00278209, 0.00278209); + rise_capacitance_range (0.00240411, 0.00316129); fall_capacitance : 0.00179475; - fall_capacitance_range (0.00179475, 0.00179475); + fall_capacitance_range (0.00179475, 0.00281492); timing () { related_pin : "GATE"; timing_type : min_pulse_width; @@ -11587,7 +11618,7 @@ library (sg13g2_stdcell_typ_1p50V_25C) { } cell (sg13g2_dlhr_1) { area : 32.6592; - cell_footprint : "DLHR"; + cell_footprint : "dlhr"; cell_leakage_power : 1440.33; leakage_power () { value : 1322.79; @@ -11693,6 +11724,7 @@ library (sg13g2_stdcell_typ_1p50V_25C) { } timing () { related_pin : "GATE"; + sdf_edges : start_edge; timing_sense : non_unate; timing_type : rising_edge; cell_rise (TIMING_DELAY_7x7ds1) { @@ -11750,6 +11782,7 @@ library (sg13g2_stdcell_typ_1p50V_25C) { } timing () { related_pin : "RESET_B"; + sdf_edges : start_edge; timing_sense : positive_unate; timing_type : clear; cell_fall (TIMING_DELAY_7x7ds1) { @@ -11923,6 +11956,7 @@ library (sg13g2_stdcell_typ_1p50V_25C) { } timing () { related_pin : "GATE"; + sdf_edges : start_edge; timing_sense : non_unate; timing_type : rising_edge; cell_rise (TIMING_DELAY_7x7ds1) { @@ -11980,6 +12014,7 @@ library (sg13g2_stdcell_typ_1p50V_25C) { } timing () { related_pin : "RESET_B"; + sdf_edges : start_edge; timing_sense : negative_unate; timing_type : preset; cell_rise (TIMING_DELAY_7x7ds1) { @@ -12094,11 +12129,12 @@ library (sg13g2_stdcell_typ_1p50V_25C) { max_transition : 2.5074; capacitance : 0.00221063; rise_capacitance : 0.0024031; - rise_capacitance_range (0.0024031, 0.0024031); + rise_capacitance_range (0.00210287, 0.00263274); fall_capacitance : 0.00201817; - fall_capacitance_range (0.00201817, 0.00201817); + fall_capacitance_range (0.00201817, 0.00251971); timing () { related_pin : "GATE"; + sdf_edges : both_edges; timing_type : hold_falling; rise_constraint (CONSTRAINT_4x4) { index_1 ("0.0186, 0.51636, 1.263, 2.5074"); @@ -12123,6 +12159,7 @@ library (sg13g2_stdcell_typ_1p50V_25C) { } timing () { related_pin : "GATE"; + sdf_edges : both_edges; timing_type : setup_falling; rise_constraint (CONSTRAINT_4x4) { index_1 ("0.0186, 0.51636, 1.263, 2.5074"); @@ -12196,9 +12233,9 @@ library (sg13g2_stdcell_typ_1p50V_25C) { max_transition : 2.5074; capacitance : 0.00240335; rise_capacitance : 0.00276086; - rise_capacitance_range (0.00276086, 0.00276086); + rise_capacitance_range (0.00238866, 0.00313975); fall_capacitance : 0.0017777; - fall_capacitance_range (0.0017777, 0.0017777); + fall_capacitance_range (0.0017777, 0.00280028); timing () { related_pin : "GATE"; timing_type : min_pulse_width; @@ -12273,11 +12310,12 @@ library (sg13g2_stdcell_typ_1p50V_25C) { max_transition : 2.5074; capacitance : 0.00328284; rise_capacitance : 0.00346861; - rise_capacitance_range (0.00346861, 0.00346861); + rise_capacitance_range (0.00293002, 0.00367107); fall_capacitance : 0.00317138; - fall_capacitance_range (0.00317138, 0.00317138); + fall_capacitance_range (0.0029256, 0.00337674); timing () { related_pin : "GATE"; + sdf_edges : both_edges; timing_type : recovery_falling; rise_constraint (CONSTRAINT_4x4) { index_1 ("0.0186, 0.51636, 1.263, 2.5074"); @@ -12292,6 +12330,7 @@ library (sg13g2_stdcell_typ_1p50V_25C) { } timing () { related_pin : "GATE"; + sdf_edges : both_edges; timing_type : removal_falling; rise_constraint (CONSTRAINT_4x4) { index_1 ("0.0186, 0.51636, 1.263, 2.5074"); @@ -12360,14 +12399,14 @@ library (sg13g2_stdcell_typ_1p50V_25C) { } } latch (IQ,IQN) { - clear : "RESET_B'"; + clear : "!RESET_B"; data_in : "D"; enable : "GATE"; } } cell (sg13g2_dlhrq_1) { area : 27.216; - cell_footprint : "DLHRQ"; + cell_footprint : "dlhrq"; cell_leakage_power : 1155.65; leakage_power () { value : 1038.48; @@ -12473,6 +12512,7 @@ library (sg13g2_stdcell_typ_1p50V_25C) { } timing () { related_pin : "GATE"; + sdf_edges : start_edge; timing_sense : non_unate; timing_type : rising_edge; cell_rise (TIMING_DELAY_7x7ds1) { @@ -12530,6 +12570,7 @@ library (sg13g2_stdcell_typ_1p50V_25C) { } timing () { related_pin : "RESET_B"; + sdf_edges : start_edge; timing_sense : positive_unate; timing_type : clear; cell_fall (TIMING_DELAY_7x7ds1) { @@ -12644,11 +12685,12 @@ library (sg13g2_stdcell_typ_1p50V_25C) { max_transition : 2.5074; capacitance : 0.00226092; rise_capacitance : 0.00249268; - rise_capacitance_range (0.00249268, 0.00249268); + rise_capacitance_range (0.0021934, 0.00272751); fall_capacitance : 0.00202917; - fall_capacitance_range (0.00202917, 0.00202917); + fall_capacitance_range (0.00202917, 0.00260563); timing () { related_pin : "GATE"; + sdf_edges : both_edges; timing_type : hold_falling; rise_constraint (CONSTRAINT_4x4) { index_1 ("0.0186, 0.51636, 1.263, 2.5074"); @@ -12673,6 +12715,7 @@ library (sg13g2_stdcell_typ_1p50V_25C) { } timing () { related_pin : "GATE"; + sdf_edges : both_edges; timing_type : setup_falling; rise_constraint (CONSTRAINT_4x4) { index_1 ("0.0186, 0.51636, 1.263, 2.5074"); @@ -12746,9 +12789,9 @@ library (sg13g2_stdcell_typ_1p50V_25C) { max_transition : 2.5074; capacitance : 0.00234535; rise_capacitance : 0.00278257; - rise_capacitance_range (0.00278257, 0.00278257); + rise_capacitance_range (0.00241342, 0.00315993); fall_capacitance : 0.00179882; - fall_capacitance_range (0.00179882, 0.00179882); + fall_capacitance_range (0.00179882, 0.0028236); timing () { related_pin : "GATE"; timing_type : min_pulse_width; @@ -12823,11 +12866,12 @@ library (sg13g2_stdcell_typ_1p50V_25C) { max_transition : 2.5074; capacitance : 0.00311372; rise_capacitance : 0.00325988; - rise_capacitance_range (0.00325988, 0.00325988); + rise_capacitance_range (0.0027267, 0.00346557); fall_capacitance : 0.0030041; - fall_capacitance_range (0.0030041, 0.0030041); + fall_capacitance_range (0.00276765, 0.00318045); timing () { related_pin : "GATE"; + sdf_edges : both_edges; timing_type : recovery_falling; rise_constraint (CONSTRAINT_4x4) { index_1 ("0.0186, 0.51636, 1.263, 2.5074"); @@ -12842,6 +12886,7 @@ library (sg13g2_stdcell_typ_1p50V_25C) { } timing () { related_pin : "GATE"; + sdf_edges : both_edges; timing_type : removal_falling; rise_constraint (CONSTRAINT_4x4) { index_1 ("0.0186, 0.51636, 1.263, 2.5074"); @@ -12910,14 +12955,14 @@ library (sg13g2_stdcell_typ_1p50V_25C) { } } latch (IQ,IQN) { - clear : "RESET_B'"; + clear : "!RESET_B"; data_in : "D"; enable : "GATE"; } } cell (sg13g2_dllr_1) { area : 34.4736; - cell_footprint : "DLLR"; + cell_footprint : "dllr"; cell_leakage_power : 1464.85; leakage_power () { value : 1395.69; @@ -13039,6 +13084,7 @@ library (sg13g2_stdcell_typ_1p50V_25C) { } timing () { related_pin : "GATE_N"; + sdf_edges : start_edge; timing_sense : non_unate; timing_type : falling_edge; cell_rise (TIMING_DELAY_7x7ds1) { @@ -13096,6 +13142,7 @@ library (sg13g2_stdcell_typ_1p50V_25C) { } timing () { related_pin : "RESET_B"; + sdf_edges : start_edge; timing_sense : positive_unate; timing_type : clear; cell_fall (TIMING_DELAY_7x7ds1) { @@ -13269,6 +13316,7 @@ library (sg13g2_stdcell_typ_1p50V_25C) { } timing () { related_pin : "GATE_N"; + sdf_edges : start_edge; timing_sense : non_unate; timing_type : falling_edge; cell_rise (TIMING_DELAY_7x7ds1) { @@ -13326,6 +13374,7 @@ library (sg13g2_stdcell_typ_1p50V_25C) { } timing () { related_pin : "RESET_B"; + sdf_edges : start_edge; timing_sense : negative_unate; timing_type : preset; cell_rise (TIMING_DELAY_7x7ds1) { @@ -13440,11 +13489,12 @@ library (sg13g2_stdcell_typ_1p50V_25C) { max_transition : 2.5074; capacitance : 0.00228241; rise_capacitance : 0.00247531; - rise_capacitance_range (0.00247531, 0.00247531); + rise_capacitance_range (0.00217469, 0.00270611); fall_capacitance : 0.00208951; - fall_capacitance_range (0.00208951, 0.00208951); + fall_capacitance_range (0.00208951, 0.00258961); timing () { related_pin : "GATE_N"; + sdf_edges : both_edges; timing_type : hold_rising; rise_constraint (CONSTRAINT_4x4) { index_1 ("0.0186, 0.51636, 1.263, 2.5074"); @@ -13469,6 +13519,7 @@ library (sg13g2_stdcell_typ_1p50V_25C) { } timing () { related_pin : "GATE_N"; + sdf_edges : both_edges; timing_type : setup_rising; rise_constraint (CONSTRAINT_4x4) { index_1 ("0.0186, 0.51636, 1.263, 2.5074"); @@ -13542,9 +13593,9 @@ library (sg13g2_stdcell_typ_1p50V_25C) { max_transition : 2.5074; capacitance : 0.00244615; rise_capacitance : 0.00193308; - rise_capacitance_range (0.00193308, 0.00193308); + rise_capacitance_range (0.00193308, 0.00321455); fall_capacitance : 0.00273933; - fall_capacitance_range (0.00273933, 0.00273933); + fall_capacitance_range (0.00254564, 0.00286452); timing () { related_pin : "GATE_N"; timing_type : min_pulse_width; @@ -13619,11 +13670,12 @@ library (sg13g2_stdcell_typ_1p50V_25C) { max_transition : 2.5074; capacitance : 0.00324488; rise_capacitance : 0.00343232; - rise_capacitance_range (0.00343232, 0.00343232); + rise_capacitance_range (0.00289844, 0.00363782); fall_capacitance : 0.00313241; - fall_capacitance_range (0.00313241, 0.00313241); + fall_capacitance_range (0.0028847, 0.00333843); timing () { related_pin : "GATE_N"; + sdf_edges : both_edges; timing_type : recovery_rising; rise_constraint (CONSTRAINT_4x4) { index_1 ("0.0186, 0.51636, 1.263, 2.5074"); @@ -13638,6 +13690,7 @@ library (sg13g2_stdcell_typ_1p50V_25C) { } timing () { related_pin : "GATE_N"; + sdf_edges : both_edges; timing_type : removal_rising; rise_constraint (CONSTRAINT_4x4) { index_1 ("0.0186, 0.51636, 1.263, 2.5074"); @@ -13706,14 +13759,14 @@ library (sg13g2_stdcell_typ_1p50V_25C) { } } latch (IQ,IQN) { - clear : "RESET_B'"; + clear : "!RESET_B"; data_in : "D"; - enable : "GATE_N'"; + enable : "!GATE_N"; } } cell (sg13g2_dllrq_1) { area : 29.0304; - cell_footprint : "DLLRQ"; + cell_footprint : "dllrq"; cell_leakage_power : 1155.63; leakage_power () { value : 1111.41; @@ -13819,6 +13872,7 @@ library (sg13g2_stdcell_typ_1p50V_25C) { } timing () { related_pin : "GATE_N"; + sdf_edges : start_edge; timing_sense : non_unate; timing_type : falling_edge; cell_rise (TIMING_DELAY_7x7ds1) { @@ -13876,6 +13930,7 @@ library (sg13g2_stdcell_typ_1p50V_25C) { } timing () { related_pin : "RESET_B"; + sdf_edges : start_edge; timing_sense : positive_unate; timing_type : clear; cell_fall (TIMING_DELAY_7x7ds1) { @@ -13907,6 +13962,7 @@ library (sg13g2_stdcell_typ_1p50V_25C) { } timing () { related_pin : "RESET_B"; + sdf_edges : start_edge; timing_sense : positive_unate; timing_type : preset; cell_rise (TIMING_DELAY_7x7ds1) { @@ -14029,11 +14085,12 @@ library (sg13g2_stdcell_typ_1p50V_25C) { max_transition : 2.5074; capacitance : 0.00217274; rise_capacitance : 0.00240337; - rise_capacitance_range (0.00240337, 0.00240337); + rise_capacitance_range (0.00210547, 0.00263739); fall_capacitance : 0.00194211; - fall_capacitance_range (0.00194211, 0.00194211); + fall_capacitance_range (0.00194211, 0.0025155); timing () { related_pin : "GATE_N"; + sdf_edges : both_edges; timing_type : hold_rising; rise_constraint (CONSTRAINT_4x4) { index_1 ("0.0186, 0.51636, 1.263, 2.5074"); @@ -14058,6 +14115,7 @@ library (sg13g2_stdcell_typ_1p50V_25C) { } timing () { related_pin : "GATE_N"; + sdf_edges : both_edges; timing_type : setup_rising; rise_constraint (CONSTRAINT_4x4) { index_1 ("0.0186, 0.51636, 1.263, 2.5074"); @@ -14131,9 +14189,9 @@ library (sg13g2_stdcell_typ_1p50V_25C) { max_transition : 2.5074; capacitance : 0.00231232; rise_capacitance : 0.00277129; - rise_capacitance_range (0.00277129, 0.00277129); + rise_capacitance_range (0.0023939, 0.0031605); fall_capacitance : 0.00208283; - fall_capacitance_range (0.00208283, 0.00208283); + fall_capacitance_range (0.00208283, 0.00280911); timing () { related_pin : "GATE_N"; timing_type : min_pulse_width; @@ -14208,11 +14266,12 @@ library (sg13g2_stdcell_typ_1p50V_25C) { max_transition : 2.5074; capacitance : 0.00318125; rise_capacitance : 0.00337226; - rise_capacitance_range (0.00337226, 0.00337226); + rise_capacitance_range (0.00267418, 0.00376005); fall_capacitance : 0.00299025; - fall_capacitance_range (0.00299025, 0.00299025); + fall_capacitance_range (0.00275693, 0.00316514); timing () { related_pin : "GATE_N"; + sdf_edges : both_edges; timing_type : recovery_rising; rise_constraint (CONSTRAINT_4x4) { index_1 ("0.0186, 0.51636, 1.263, 2.5074"); @@ -14227,6 +14286,7 @@ library (sg13g2_stdcell_typ_1p50V_25C) { } timing () { related_pin : "GATE_N"; + sdf_edges : both_edges; timing_type : removal_rising; rise_constraint (CONSTRAINT_4x4) { index_1 ("0.0186, 0.51636, 1.263, 2.5074"); @@ -14295,14 +14355,14 @@ library (sg13g2_stdcell_typ_1p50V_25C) { } } latch (IQ,IQN) { - clear : "RESET_B'"; + clear : "!RESET_B"; data_in : "D"; - enable : "GATE_N'"; + enable : "!GATE_N"; } } cell (sg13g2_dlygate4sd1_1) { area : 14.5152; - cell_footprint : "DLY1"; + cell_footprint : "dlygate4sd1"; cell_leakage_power : 473.124; leakage_power () { value : 510.685; @@ -14409,14 +14469,14 @@ library (sg13g2_stdcell_typ_1p50V_25C) { max_transition : 2.5074; capacitance : 0.00157584; rise_capacitance : 0.00159255; - rise_capacitance_range (0.00159255, 0.00159255); + rise_capacitance_range (0.00137675, 0.00182211); fall_capacitance : 0.00155912; - fall_capacitance_range (0.00155912, 0.00155912); + fall_capacitance_range (0.00146303, 0.00161657); } } cell (sg13g2_dlygate4sd2_1) { area : 14.5152; - cell_footprint : "DLY2"; + cell_footprint : "dlygate4sd2"; cell_leakage_power : 553.33; leakage_power () { value : 590.89; @@ -14523,14 +14583,14 @@ library (sg13g2_stdcell_typ_1p50V_25C) { max_transition : 2.5074; capacitance : 0.00156628; rise_capacitance : 0.00157832; - rise_capacitance_range (0.00157832, 0.00157832); + rise_capacitance_range (0.00138312, 0.00178637); fall_capacitance : 0.00155424; - fall_capacitance_range (0.00155424, 0.00155424); + fall_capacitance_range (0.0014704, 0.00160942); } } cell (sg13g2_dlygate4sd3_1) { area : 16.3296; - cell_footprint : "DLY4"; + cell_footprint : "dlygate4sd3"; cell_leakage_power : 1252.41; leakage_power () { value : 1289.95; @@ -14637,14 +14697,14 @@ library (sg13g2_stdcell_typ_1p50V_25C) { max_transition : 2.5074; capacitance : 0.00157452; rise_capacitance : 0.00157444; - rise_capacitance_range (0.00157444, 0.00157444); + rise_capacitance_range (0.00142441, 0.00174394); fall_capacitance : 0.00157459; - fall_capacitance_range (0.00157459, 0.00157459); + fall_capacitance_range (0.00150211, 0.00162762); } } cell (sg13g2_ebufn_2) { area : 18.144; - cell_footprint : "BTL"; + cell_footprint : "ebufn"; cell_leakage_power : 683.061; leakage_power () { value : 483.447; @@ -14732,6 +14792,7 @@ library (sg13g2_stdcell_typ_1p50V_25C) { } timing () { related_pin : "TE_B"; + sdf_edges : start_edge; timing_sense : positive_unate; timing_type : three_state_disable; cell_rise (TIMING_DELAY_7x7ds1) { @@ -14789,6 +14850,7 @@ library (sg13g2_stdcell_typ_1p50V_25C) { } timing () { related_pin : "TE_B"; + sdf_edges : start_edge; timing_sense : negative_unate; timing_type : three_state_enable; cell_rise (TIMING_DELAY_7x7ds1) { @@ -14908,9 +14970,9 @@ library (sg13g2_stdcell_typ_1p50V_25C) { max_transition : 2.5074; capacitance : 0.00276821; rise_capacitance : 0.00282022; - rise_capacitance_range (0.00282022, 0.00282022); + rise_capacitance_range (0.00247276, 0.00311647); fall_capacitance : 0.00271621; - fall_capacitance_range (0.00271621, 0.00271621); + fall_capacitance_range (0.0024569, 0.00296933); internal_power () { rise_power (passive_POWER_7x1ds1) { index_1 ("0.0186, 0.0966, 0.174, 0.3294, 0.6408, 1.263, 2.5074"); @@ -14931,9 +14993,9 @@ library (sg13g2_stdcell_typ_1p50V_25C) { max_transition : 2.5074; capacitance : 0.00668919; rise_capacitance : 0.00678797; - rise_capacitance_range (0.00678797, 0.00678797); + rise_capacitance_range (0.00496124, 0.0079847); fall_capacitance : 0.00659041; - fall_capacitance_range (0.00659041, 0.00659041); + fall_capacitance_range (0.00497038, 0.00798528); internal_power () { rise_power (passive_POWER_7x1ds1) { index_1 ("0.0186, 0.0966, 0.174, 0.3294, 0.6408, 1.263, 2.5074"); @@ -14952,7 +15014,7 @@ library (sg13g2_stdcell_typ_1p50V_25C) { } cell (sg13g2_ebufn_4) { area : 27.216; - cell_footprint : "BTL"; + cell_footprint : "ebufn"; cell_leakage_power : 1118.49; leakage_power () { value : 611.595; @@ -15040,6 +15102,7 @@ library (sg13g2_stdcell_typ_1p50V_25C) { } timing () { related_pin : "TE_B"; + sdf_edges : start_edge; timing_sense : positive_unate; timing_type : three_state_disable; cell_rise (TIMING_DELAY_7x7ds1) { @@ -15097,6 +15160,7 @@ library (sg13g2_stdcell_typ_1p50V_25C) { } timing () { related_pin : "TE_B"; + sdf_edges : start_edge; timing_sense : negative_unate; timing_type : three_state_enable; cell_rise (TIMING_DELAY_7x7ds1) { @@ -15216,9 +15280,9 @@ library (sg13g2_stdcell_typ_1p50V_25C) { max_transition : 2.5074; capacitance : 0.00311589; rise_capacitance : 0.0031766; - rise_capacitance_range (0.0031766, 0.0031766); + rise_capacitance_range (0.00282325, 0.00350681); fall_capacitance : 0.00305517; - fall_capacitance_range (0.00305517, 0.00305517); + fall_capacitance_range (0.00280177, 0.00329365); internal_power () { rise_power (passive_POWER_7x1ds1) { index_1 ("0.0186, 0.0966, 0.174, 0.3294, 0.6408, 1.263, 2.5074"); @@ -15239,9 +15303,9 @@ library (sg13g2_stdcell_typ_1p50V_25C) { max_transition : 2.5074; capacitance : 0.0108988; rise_capacitance : 0.0110625; - rise_capacitance_range (0.0110625, 0.0110625); + rise_capacitance_range (0.00762621, 0.0133245); fall_capacitance : 0.0107352; - fall_capacitance_range (0.0107352, 0.0107352); + fall_capacitance_range (0.00763112, 0.0133102); internal_power () { rise_power (passive_POWER_7x1ds1) { index_1 ("0.0186, 0.0966, 0.174, 0.3294, 0.6408, 1.263, 2.5074"); @@ -15260,7 +15324,7 @@ library (sg13g2_stdcell_typ_1p50V_25C) { } cell (sg13g2_ebufn_8) { area : 45.36; - cell_footprint : "BTL"; + cell_footprint : "ebufn"; cell_leakage_power : 2069.17; leakage_power () { value : 981.459; @@ -15348,6 +15412,7 @@ library (sg13g2_stdcell_typ_1p50V_25C) { } timing () { related_pin : "TE_B"; + sdf_edges : start_edge; timing_sense : positive_unate; timing_type : three_state_disable; cell_rise (TIMING_DELAY_7x7ds1) { @@ -15405,6 +15470,7 @@ library (sg13g2_stdcell_typ_1p50V_25C) { } timing () { related_pin : "TE_B"; + sdf_edges : start_edge; timing_sense : negative_unate; timing_type : three_state_enable; cell_rise (TIMING_DELAY_7x7ds1) { @@ -15524,9 +15590,9 @@ library (sg13g2_stdcell_typ_1p50V_25C) { max_transition : 2.5074; capacitance : 0.00608858; rise_capacitance : 0.00621192; - rise_capacitance_range (0.00621192, 0.00621192); + rise_capacitance_range (0.00547649, 0.00687686); fall_capacitance : 0.00596524; - fall_capacitance_range (0.00596524, 0.00596524); + fall_capacitance_range (0.00543623, 0.00646864); internal_power () { rise_power (passive_POWER_7x1ds1) { index_1 ("0.0186, 0.0966, 0.174, 0.3294, 0.6408, 1.263, 2.5074"); @@ -15547,9 +15613,9 @@ library (sg13g2_stdcell_typ_1p50V_25C) { max_transition : 2.5074; capacitance : 0.0182149; rise_capacitance : 0.0185129; - rise_capacitance_range (0.0185129, 0.0185129); + rise_capacitance_range (0.0115368, 0.0230523); fall_capacitance : 0.0179168; - fall_capacitance_range (0.0179168, 0.0179168); + fall_capacitance_range (0.0115567, 0.0230563); internal_power () { rise_power (passive_POWER_7x1ds1) { index_1 ("0.0186, 0.0966, 0.174, 0.3294, 0.6408, 1.263, 2.5074"); @@ -15568,7 +15634,7 @@ library (sg13g2_stdcell_typ_1p50V_25C) { } cell (sg13g2_einvn_2) { area : 16.3296; - cell_footprint : "einvin"; + cell_footprint : "einvn"; cell_leakage_power : 781.675; leakage_power () { value : 633.835; @@ -15648,6 +15714,7 @@ library (sg13g2_stdcell_typ_1p50V_25C) { } timing () { related_pin : "TE_B"; + sdf_edges : start_edge; timing_sense : positive_unate; timing_type : three_state_disable_rise; cell_rise (TIMING_DELAY_7x7ds1) { @@ -15679,6 +15746,7 @@ library (sg13g2_stdcell_typ_1p50V_25C) { } timing () { related_pin : "TE_B"; + sdf_edges : start_edge; timing_sense : negative_unate; timing_type : three_state_enable_rise; cell_rise (TIMING_DELAY_7x7ds1) { @@ -15764,9 +15832,9 @@ library (sg13g2_stdcell_typ_1p50V_25C) { max_transition : 2.5074; capacitance : 0.00419674; rise_capacitance : 0.00429615; - rise_capacitance_range (0.00429615, 0.00429615); + rise_capacitance_range (0.00251234, 0.00751389); fall_capacitance : 0.00409734; - fall_capacitance_range (0.00409734, 0.00409734); + fall_capacitance_range (0.00243768, 0.00644282); internal_power () { rise_power (passive_POWER_7x1ds1) { index_1 ("0.0186, 0.0966, 0.174, 0.3294, 0.6408, 1.263, 2.5074"); @@ -15787,9 +15855,9 @@ library (sg13g2_stdcell_typ_1p50V_25C) { max_transition : 2.5074; capacitance : 0.00512097; rise_capacitance : 0.00570846; - rise_capacitance_range (0.00570846, 0.00570846); + rise_capacitance_range (0.00530466, 0.00593336); fall_capacitance : 0.00453349; - fall_capacitance_range (0.00453349, 0.00453349); + fall_capacitance_range (0.00331308, 0.00696373); internal_power () { rise_power (passive_POWER_7x1ds1) { index_1 ("0.0186, 0.0966, 0.174, 0.3294, 0.6408, 1.263, 2.5074"); @@ -15808,7 +15876,7 @@ library (sg13g2_stdcell_typ_1p50V_25C) { } cell (sg13g2_einvn_4) { area : 23.5872; - cell_footprint : "einvin"; + cell_footprint : "einvn"; cell_leakage_power : 1555.35; leakage_power () { value : 1259.66; @@ -15888,6 +15956,7 @@ library (sg13g2_stdcell_typ_1p50V_25C) { } timing () { related_pin : "TE_B"; + sdf_edges : start_edge; timing_sense : positive_unate; timing_type : three_state_disable_rise; cell_rise (TIMING_DELAY_7x7ds1) { @@ -15919,6 +15988,7 @@ library (sg13g2_stdcell_typ_1p50V_25C) { } timing () { related_pin : "TE_B"; + sdf_edges : start_edge; timing_sense : negative_unate; timing_type : three_state_enable_rise; cell_rise (TIMING_DELAY_7x7ds1) { @@ -16004,9 +16074,9 @@ library (sg13g2_stdcell_typ_1p50V_25C) { max_transition : 2.5074; capacitance : 0.00818576; rise_capacitance : 0.00837966; - rise_capacitance_range (0.00837966, 0.00837966); + rise_capacitance_range (0.00477203, 0.0150289); fall_capacitance : 0.00799185; - fall_capacitance_range (0.00799185, 0.00799185); + fall_capacitance_range (0.00464176, 0.0127684); internal_power () { rise_power (passive_POWER_7x1ds1) { index_1 ("0.0186, 0.0966, 0.174, 0.3294, 0.6408, 1.263, 2.5074"); @@ -16027,9 +16097,9 @@ library (sg13g2_stdcell_typ_1p50V_25C) { max_transition : 2.5074; capacitance : 0.0095461; rise_capacitance : 0.0106534; - rise_capacitance_range (0.0106534, 0.0106534); + rise_capacitance_range (0.00969912, 0.0111203); fall_capacitance : 0.00843879; - fall_capacitance_range (0.00843879, 0.00843879); + fall_capacitance_range (0.00604855, 0.0131522); internal_power () { rise_power (passive_POWER_7x1ds1) { index_1 ("0.0186, 0.0966, 0.174, 0.3294, 0.6408, 1.263, 2.5074"); @@ -16048,7 +16118,7 @@ library (sg13g2_stdcell_typ_1p50V_25C) { } cell (sg13g2_einvn_8) { area : 39.9168; - cell_footprint : "ITL"; + cell_footprint : "einvn"; cell_leakage_power : 3016.8; leakage_power () { value : 2425.43; @@ -16128,6 +16198,7 @@ library (sg13g2_stdcell_typ_1p50V_25C) { } timing () { related_pin : "TE_B"; + sdf_edges : start_edge; timing_sense : positive_unate; timing_type : three_state_disable_rise; cell_rise (TIMING_DELAY_7x7ds1) { @@ -16159,6 +16230,7 @@ library (sg13g2_stdcell_typ_1p50V_25C) { } timing () { related_pin : "TE_B"; + sdf_edges : start_edge; timing_sense : negative_unate; timing_type : three_state_enable_rise; cell_rise (TIMING_DELAY_7x7ds1) { @@ -16244,9 +16316,9 @@ library (sg13g2_stdcell_typ_1p50V_25C) { max_transition : 2.5074; capacitance : 0.0161898; rise_capacitance : 0.0165837; - rise_capacitance_range (0.0165837, 0.0165837); + rise_capacitance_range (0.00929076, 0.0300607); fall_capacitance : 0.0157959; - fall_capacitance_range (0.0157959, 0.0157959); + fall_capacitance_range (0.00900253, 0.0254857); internal_power () { rise_power (passive_POWER_7x1ds1) { index_1 ("0.0186, 0.0966, 0.174, 0.3294, 0.6408, 1.263, 2.5074"); @@ -16267,9 +16339,9 @@ library (sg13g2_stdcell_typ_1p50V_25C) { max_transition : 2.5074; capacitance : 0.0163012; rise_capacitance : 0.0179376; - rise_capacitance_range (0.0179376, 0.0179376); + rise_capacitance_range (0.0155122, 0.0187571); fall_capacitance : 0.0146649; - fall_capacitance_range (0.0146649, 0.0146649); + fall_capacitance_range (0.0106614, 0.0229435); internal_power () { rise_power (passive_POWER_7x1ds1) { index_1 ("0.0186, 0.0966, 0.174, 0.3294, 0.6408, 1.263, 2.5074"); @@ -16320,7 +16392,7 @@ library (sg13g2_stdcell_typ_1p50V_25C) { } cell (sg13g2_inv_1) { area : 5.4432; - cell_footprint : "IN"; + cell_footprint : "inv"; cell_leakage_power : 167.866; leakage_power () { value : 241.835; @@ -16427,14 +16499,14 @@ library (sg13g2_stdcell_typ_1p50V_25C) { max_transition : 2.5074; capacitance : 0.00297633; rise_capacitance : 0.00302532; - rise_capacitance_range (0.00302532, 0.00302532); + rise_capacitance_range (0.00270985, 0.00362869); fall_capacitance : 0.00292733; - fall_capacitance_range (0.00292733, 0.00292733); + fall_capacitance_range (0.00273003, 0.00339135); } } cell (sg13g2_inv_16) { area : 34.4736; - cell_footprint : "IN"; + cell_footprint : "inv"; cell_leakage_power : 2685.08; leakage_power () { value : 3867.81; @@ -16541,14 +16613,14 @@ library (sg13g2_stdcell_typ_1p50V_25C) { max_transition : 2.5074; capacitance : 0.0450569; rise_capacitance : 0.0457778; - rise_capacitance_range (0.0457778, 0.0457778); + rise_capacitance_range (0.0339101, 0.0577094); fall_capacitance : 0.0443359; - fall_capacitance_range (0.0443359, 0.0443359); + fall_capacitance_range (0.0348296, 0.0538629); } } cell (sg13g2_inv_2) { area : 7.2576; - cell_footprint : "IN"; + cell_footprint : "inv"; cell_leakage_power : 335.653; leakage_power () { value : 483.501; @@ -16655,14 +16727,14 @@ library (sg13g2_stdcell_typ_1p50V_25C) { max_transition : 2.5074; capacitance : 0.00589435; rise_capacitance : 0.00599294; - rise_capacitance_range (0.00599294, 0.00599294); + rise_capacitance_range (0.00530499, 0.00732128); fall_capacitance : 0.00579575; - fall_capacitance_range (0.00579575, 0.00579575); + fall_capacitance_range (0.0053647, 0.00682293); } } cell (sg13g2_inv_4) { area : 10.8864; - cell_footprint : "IN"; + cell_footprint : "inv"; cell_leakage_power : 671.273; leakage_power () { value : 966.955; @@ -16769,14 +16841,14 @@ library (sg13g2_stdcell_typ_1p50V_25C) { max_transition : 2.5074; capacitance : 0.0116635; rise_capacitance : 0.0118598; - rise_capacitance_range (0.0118598, 0.0118598); + rise_capacitance_range (0.0105115, 0.0146114); fall_capacitance : 0.0114673; - fall_capacitance_range (0.0114673, 0.0114673); + fall_capacitance_range (0.0106391, 0.0136185); } } cell (sg13g2_inv_8) { area : 18.144; - cell_footprint : "IN"; + cell_footprint : "inv"; cell_leakage_power : 1342.58; leakage_power () { value : 1933.98; @@ -16883,14 +16955,14 @@ library (sg13g2_stdcell_typ_1p50V_25C) { max_transition : 2.5074; capacitance : 0.0233305; rise_capacitance : 0.0237237; - rise_capacitance_range (0.0237237, 0.0237237); + rise_capacitance_range (0.0208704, 0.0293467); fall_capacitance : 0.0229373; - fall_capacitance_range (0.0229373, 0.0229373); + fall_capacitance_range (0.0211388, 0.0273367); } } cell (sg13g2_lgcp_1) { area : 27.216; - cell_footprint : "gclk"; + cell_footprint : "lgcp"; cell_leakage_power : 1127.38; clock_gating_integrated_cell : "latch_posedge"; dont_use : true; @@ -17014,9 +17086,9 @@ library (sg13g2_stdcell_typ_1p50V_25C) { max_transition : 2.5074; capacitance : 0.00523367; rise_capacitance : 0.00535156; - rise_capacitance_range (0.00535156, 0.00535156); + rise_capacitance_range (0.00452342, 0.0062419); fall_capacitance : 0.00511577; - fall_capacitance_range (0.00511577, 0.00511577); + fall_capacitance_range (0.00470776, 0.00539404); timing () { related_pin : "CLK"; timing_type : min_pulse_width; @@ -17054,11 +17126,12 @@ library (sg13g2_stdcell_typ_1p50V_25C) { max_transition : 2.5074; capacitance : 0.00245073; rise_capacitance : 0.0027577; - rise_capacitance_range (0.0027577, 0.0027577); + rise_capacitance_range (0.00239501, 0.00298192); fall_capacitance : 0.00214375; - fall_capacitance_range (0.00214375, 0.00214375); + fall_capacitance_range (0.00214375, 0.00244724); timing () { related_pin : "CLK"; + sdf_edges : both_edges; timing_type : hold_rising; rise_constraint (CONSTRAINT_4x4) { index_1 ("0.0186, 0.51636, 1.263, 2.5074"); @@ -17083,6 +17156,7 @@ library (sg13g2_stdcell_typ_1p50V_25C) { } timing () { related_pin : "CLK"; + sdf_edges : both_edges; timing_type : setup_rising; rise_constraint (CONSTRAINT_4x4) { index_1 ("0.0186, 0.51636, 1.263, 2.5074"); @@ -17293,7 +17367,7 @@ library (sg13g2_stdcell_typ_1p50V_25C) { } timing () { related_pin : "S"; - sdf_cond : "A0 == 1'b0 & A1 == 1'b1"; + sdf_cond : "A0 == 1'b0 && A1 == 1'b1"; timing_sense : positive_unate; timing_type : combinational; when : "(!A0 * A1)"; @@ -17409,7 +17483,7 @@ library (sg13g2_stdcell_typ_1p50V_25C) { } timing () { related_pin : "S"; - sdf_cond : "A0 == 1'b1 & A1 == 1'b0"; + sdf_cond : "A0 == 1'b1 && A1 == 1'b0"; timing_sense : negative_unate; timing_type : combinational; when : "(A0 * !A1)"; @@ -17619,27 +17693,27 @@ library (sg13g2_stdcell_typ_1p50V_25C) { max_transition : 2.5074; capacitance : 0.00293162; rise_capacitance : 0.00302074; - rise_capacitance_range (0.00302074, 0.00302074); + rise_capacitance_range (0.00252255, 0.00343788); fall_capacitance : 0.0028425; - fall_capacitance_range (0.0028425, 0.0028425); + fall_capacitance_range (0.00251674, 0.00302007); } pin (A1) { direction : "input"; max_transition : 2.5074; capacitance : 0.00303557; rise_capacitance : 0.00312472; - rise_capacitance_range (0.00312472, 0.00312472); + rise_capacitance_range (0.00262813, 0.0035416); fall_capacitance : 0.00294642; - fall_capacitance_range (0.00294642, 0.00294642); + fall_capacitance_range (0.00262337, 0.0031257); } pin (S) { direction : "input"; max_transition : 2.5074; capacitance : 0.00541444; rise_capacitance : 0.00547219; - rise_capacitance_range (0.00547219, 0.00547219); + rise_capacitance_range (0.00453915, 0.00628855); fall_capacitance : 0.0053567; - fall_capacitance_range (0.0053567, 0.0053567); + fall_capacitance_range (0.00457404, 0.00617627); internal_power () { when : "(A0 * A1)"; rise_power (passive_POWER_7x1ds1) { @@ -17843,7 +17917,7 @@ library (sg13g2_stdcell_typ_1p50V_25C) { } timing () { related_pin : "S"; - sdf_cond : "A0 == 1'b0 & A1 == 1'b1"; + sdf_cond : "A0 == 1'b0 && A1 == 1'b1"; timing_sense : positive_unate; timing_type : combinational; when : "(!A0 * A1)"; @@ -17959,7 +18033,7 @@ library (sg13g2_stdcell_typ_1p50V_25C) { } timing () { related_pin : "S"; - sdf_cond : "A0 == 1'b1 & A1 == 1'b0"; + sdf_cond : "A0 == 1'b1 && A1 == 1'b0"; timing_sense : negative_unate; timing_type : combinational; when : "(A0 * !A1)"; @@ -18169,27 +18243,27 @@ library (sg13g2_stdcell_typ_1p50V_25C) { max_transition : 2.5074; capacitance : 0.00290757; rise_capacitance : 0.00298261; - rise_capacitance_range (0.00298261, 0.00298261); + rise_capacitance_range (0.00256474, 0.00335129); fall_capacitance : 0.00283254; - fall_capacitance_range (0.00283254, 0.00283254); + fall_capacitance_range (0.00255, 0.00300431); } pin (A1) { direction : "input"; max_transition : 2.5074; capacitance : 0.0030109; rise_capacitance : 0.00308618; - rise_capacitance_range (0.00308618, 0.00308618); + rise_capacitance_range (0.00267153, 0.00345801); fall_capacitance : 0.00293562; - fall_capacitance_range (0.00293562, 0.00293562); + fall_capacitance_range (0.00265621, 0.0031054); } pin (S) { direction : "input"; max_transition : 2.5074; capacitance : 0.00540491; rise_capacitance : 0.00546195; - rise_capacitance_range (0.00546195, 0.00546195); + rise_capacitance_range (0.00453493, 0.00628026); fall_capacitance : 0.00534787; - fall_capacitance_range (0.00534787, 0.00534787); + fall_capacitance_range (0.00456636, 0.00616806); internal_power () { when : "(A0 * A1)"; rise_power (passive_POWER_7x1ds1) { @@ -18731,7 +18805,7 @@ library (sg13g2_stdcell_typ_1p50V_25C) { } timing () { related_pin : "S0"; - sdf_cond : "A2 == 1'b0 & A3 == 1'b1 & S1 == 1'b1"; + sdf_cond : "A2 == 1'b0 && A3 == 1'b1 && S1 == 1'b1"; timing_sense : positive_unate; timing_type : combinational; when : "(!A2 * A3 * S1)"; @@ -18790,7 +18864,7 @@ library (sg13g2_stdcell_typ_1p50V_25C) { } timing () { related_pin : "S0"; - sdf_cond : "A0 == 1'b0 & A1 == 1'b1 & S1 == 1'b0"; + sdf_cond : "A0 == 1'b0 && A1 == 1'b1 && S1 == 1'b0"; timing_sense : positive_unate; timing_type : combinational; when : "(!A0 * A1 * !S1)"; @@ -18906,7 +18980,7 @@ library (sg13g2_stdcell_typ_1p50V_25C) { } timing () { related_pin : "S0"; - sdf_cond : "A2 == 1'b1 & A3 == 1'b0 & S1 == 1'b1"; + sdf_cond : "A2 == 1'b1 && A3 == 1'b0 && S1 == 1'b1"; timing_sense : negative_unate; timing_type : combinational; when : "(A2 * !A3 * S1)"; @@ -18965,7 +19039,7 @@ library (sg13g2_stdcell_typ_1p50V_25C) { } timing () { related_pin : "S0"; - sdf_cond : "A0 == 1'b1 & A1 == 1'b0 & S1 == 1'b0"; + sdf_cond : "A0 == 1'b1 && A1 == 1'b0 && S1 == 1'b0"; timing_sense : negative_unate; timing_type : combinational; when : "(A0 * !A1 * !S1)"; @@ -19024,7 +19098,7 @@ library (sg13g2_stdcell_typ_1p50V_25C) { } timing () { related_pin : "S1"; - sdf_cond : "A1 == 1'b0 & A3 == 1'b1 & S0 == 1'b1"; + sdf_cond : "A1 == 1'b0 && A3 == 1'b1 && S0 == 1'b1"; timing_sense : positive_unate; timing_type : combinational; when : "(!A1 * A3 * S0)"; @@ -19083,7 +19157,7 @@ library (sg13g2_stdcell_typ_1p50V_25C) { } timing () { related_pin : "S1"; - sdf_cond : "A0 == 1'b0 & A2 == 1'b1 & S0 == 1'b0"; + sdf_cond : "A0 == 1'b0 && A2 == 1'b1 && S0 == 1'b0"; timing_sense : positive_unate; timing_type : combinational; when : "(!A0 * A2 * !S0)"; @@ -19199,7 +19273,7 @@ library (sg13g2_stdcell_typ_1p50V_25C) { } timing () { related_pin : "S1"; - sdf_cond : "A1 == 1'b1 & A3 == 1'b0 & S0 == 1'b1"; + sdf_cond : "A1 == 1'b1 && A3 == 1'b0 && S0 == 1'b1"; timing_sense : negative_unate; timing_type : combinational; when : "(A1 * !A3 * S0)"; @@ -19258,7 +19332,7 @@ library (sg13g2_stdcell_typ_1p50V_25C) { } timing () { related_pin : "S1"; - sdf_cond : "A0 == 1'b1 & A2 == 1'b0 & S0 == 1'b0"; + sdf_cond : "A0 == 1'b1 && A2 == 1'b0 && S0 == 1'b0"; timing_sense : negative_unate; timing_type : combinational; when : "(A0 * !A2 * !S0)"; @@ -19735,45 +19809,45 @@ library (sg13g2_stdcell_typ_1p50V_25C) { max_transition : 2.5074; capacitance : 0.00297127; rise_capacitance : 0.00301573; - rise_capacitance_range (0.00301573, 0.00301573); + rise_capacitance_range (0.00254361, 0.00324495); fall_capacitance : 0.00292681; - fall_capacitance_range (0.00292681, 0.00292681); + fall_capacitance_range (0.00251517, 0.00314607); } pin (A1) { direction : "input"; max_transition : 2.5074; capacitance : 0.00294772; rise_capacitance : 0.00299286; - rise_capacitance_range (0.00299286, 0.00299286); + rise_capacitance_range (0.00254351, 0.00323879); fall_capacitance : 0.00290258; - fall_capacitance_range (0.00290258, 0.00290258); + fall_capacitance_range (0.00246888, 0.00310548); } pin (A2) { direction : "input"; max_transition : 2.5074; capacitance : 0.00296255; rise_capacitance : 0.0030087; - rise_capacitance_range (0.0030087, 0.0030087); + rise_capacitance_range (0.0025497, 0.00323809); fall_capacitance : 0.00291641; - fall_capacitance_range (0.00291641, 0.00291641); + fall_capacitance_range (0.0024955, 0.00311732); } pin (A3) { direction : "input"; max_transition : 2.5074; capacitance : 0.00302948; rise_capacitance : 0.00307233; - rise_capacitance_range (0.00307233, 0.00307233); + rise_capacitance_range (0.00260258, 0.00330558); fall_capacitance : 0.00298664; - fall_capacitance_range (0.00298664, 0.00298664); + fall_capacitance_range (0.00254768, 0.0031812); } pin (S0) { direction : "input"; max_transition : 2.5074; capacitance : 0.00855034; rise_capacitance : 0.0101489; - rise_capacitance_range (0.0101489, 0.0101489); + rise_capacitance_range (0.00681698, 0.0115681); fall_capacitance : 0.00695175; - fall_capacitance_range (0.00695175, 0.00695175); + fall_capacitance_range (0.00416436, 0.01016); internal_power () { when : "(A2 * A3 * S1)"; rise_power (passive_POWER_7x1ds1) { @@ -19854,9 +19928,9 @@ library (sg13g2_stdcell_typ_1p50V_25C) { max_transition : 2.5074; capacitance : 0.00523076; rise_capacitance : 0.00531347; - rise_capacitance_range (0.00531347, 0.00531347); + rise_capacitance_range (0.00435707, 0.0065249); fall_capacitance : 0.00514804; - fall_capacitance_range (0.00514804, 0.00514804); + fall_capacitance_range (0.00439329, 0.00598011); internal_power () { when : "(A1 * A3 * S0)"; rise_power (passive_POWER_7x1ds1) { @@ -20136,18 +20210,18 @@ library (sg13g2_stdcell_typ_1p50V_25C) { max_transition : 2.5074; capacitance : 0.0029873; rise_capacitance : 0.00299954; - rise_capacitance_range (0.00299954, 0.00299954); + rise_capacitance_range (0.00270335, 0.00338428); fall_capacitance : 0.00297507; - fall_capacitance_range (0.00297507, 0.00297507); + fall_capacitance_range (0.00264967, 0.00363715); } pin (B) { direction : "input"; max_transition : 2.5074; capacitance : 0.00312818; rise_capacitance : 0.00328477; - rise_capacitance_range (0.00328477, 0.00328477); + rise_capacitance_range (0.0027586, 0.0036644); fall_capacitance : 0.00297158; - fall_capacitance_range (0.00297158, 0.00297158); + fall_capacitance_range (0.0027878, 0.00336522); } } cell (sg13g2_nand2_2) { @@ -20353,23 +20427,23 @@ library (sg13g2_stdcell_typ_1p50V_25C) { max_transition : 2.5074; capacitance : 0.00579269; rise_capacitance : 0.00582245; - rise_capacitance_range (0.00582245, 0.00582245); + rise_capacitance_range (0.0052033, 0.0065725); fall_capacitance : 0.00576293; - fall_capacitance_range (0.00576293, 0.00576293); + fall_capacitance_range (0.00506722, 0.00727159); } pin (B) { direction : "input"; max_transition : 2.5074; capacitance : 0.00600449; rise_capacitance : 0.00631346; - rise_capacitance_range (0.00631346, 0.00631346); + rise_capacitance_range (0.00528359, 0.00707711); fall_capacitance : 0.00569551; - fall_capacitance_range (0.00569551, 0.00569551); + fall_capacitance_range (0.00530561, 0.00655575); } } cell (sg13g2_nand2b_1) { area : 9.072; - cell_footprint : "nand2b1"; + cell_footprint : "nand2b"; cell_leakage_power : 357.107; leakage_power () { value : 551.87; @@ -20570,9 +20644,9 @@ library (sg13g2_stdcell_typ_1p50V_25C) { max_transition : 2.5074; capacitance : 0.00237595; rise_capacitance : 0.00241821; - rise_capacitance_range (0.00241821, 0.00241821); + rise_capacitance_range (0.00211367, 0.00265762); fall_capacitance : 0.00233369; - fall_capacitance_range (0.00233369, 0.00233369); + fall_capacitance_range (0.00211119, 0.00252689); internal_power () { when : "!B"; rise_power (passive_POWER_7x1ds1) { @@ -20608,14 +20682,14 @@ library (sg13g2_stdcell_typ_1p50V_25C) { max_transition : 2.5074; capacitance : 0.00317628; rise_capacitance : 0.00333398; - rise_capacitance_range (0.00333398, 0.00333398); + rise_capacitance_range (0.00280466, 0.0037112); fall_capacitance : 0.00301858; - fall_capacitance_range (0.00301858, 0.00301858); + fall_capacitance_range (0.0028356, 0.00341054); } } cell (sg13g2_nand2b_2) { area : 14.5152; - cell_footprint : "nand2b2"; + cell_footprint : "nand2b"; cell_leakage_power : 583.519; leakage_power () { value : 1016.76; @@ -20816,9 +20890,9 @@ library (sg13g2_stdcell_typ_1p50V_25C) { max_transition : 2.5074; capacitance : 0.00231805; rise_capacitance : 0.00235626; - rise_capacitance_range (0.00235626, 0.00235626); + rise_capacitance_range (0.0021231, 0.00255811); fall_capacitance : 0.00227984; - fall_capacitance_range (0.00227984, 0.00227984); + fall_capacitance_range (0.00209622, 0.00244839); internal_power () { when : "!B"; rise_power (passive_POWER_7x1ds1) { @@ -20854,9 +20928,9 @@ library (sg13g2_stdcell_typ_1p50V_25C) { max_transition : 2.5074; capacitance : 0.00581629; rise_capacitance : 0.00584581; - rise_capacitance_range (0.00584581, 0.00584581); + rise_capacitance_range (0.00521666, 0.00659517); fall_capacitance : 0.00578677; - fall_capacitance_range (0.00578677, 0.00578677); + fall_capacitance_range (0.00508703, 0.0073003); } } cell (sg13g2_nand3_1) { @@ -21164,32 +21238,32 @@ library (sg13g2_stdcell_typ_1p50V_25C) { max_transition : 2.5074; capacitance : 0.00297799; rise_capacitance : 0.00296876; - rise_capacitance_range (0.00296876, 0.00296876); + rise_capacitance_range (0.00269525, 0.00324686); fall_capacitance : 0.00298722; - fall_capacitance_range (0.00298722, 0.00298722); + fall_capacitance_range (0.00258603, 0.00377451); } pin (B) { direction : "input"; max_transition : 2.5074; capacitance : 0.0031507; rise_capacitance : 0.00327124; - rise_capacitance_range (0.00327124, 0.00327124); + rise_capacitance_range (0.00277081, 0.00357781); fall_capacitance : 0.00303016; - fall_capacitance_range (0.00303016, 0.00303016); + fall_capacitance_range (0.00275571, 0.00355907); } pin (C) { direction : "input"; max_transition : 2.5074; capacitance : 0.00313462; rise_capacitance : 0.00330038; - rise_capacitance_range (0.00330038, 0.00330038); + rise_capacitance_range (0.00277588, 0.0036739); fall_capacitance : 0.00296886; - fall_capacitance_range (0.00296886, 0.00296886); + fall_capacitance_range (0.00280293, 0.00332452); } } cell (sg13g2_nand3b_1) { area : 12.7008; - cell_footprint : "nand3b1"; + cell_footprint : "nand3b"; cell_leakage_power : 390.861; leakage_power () { value : 199.285; @@ -21492,9 +21566,9 @@ library (sg13g2_stdcell_typ_1p50V_25C) { max_transition : 2.5074; capacitance : 0.00235633; rise_capacitance : 0.00239864; - rise_capacitance_range (0.00239864, 0.00239864); + rise_capacitance_range (0.00209372, 0.00263772); fall_capacitance : 0.00231402; - fall_capacitance_range (0.00231402, 0.00231402); + fall_capacitance_range (0.0020905, 0.00250754); internal_power () { when : "(B * !C) + (!B)"; rise_power (passive_POWER_7x1ds1) { @@ -21530,18 +21604,18 @@ library (sg13g2_stdcell_typ_1p50V_25C) { max_transition : 2.5074; capacitance : 0.00311469; rise_capacitance : 0.00323621; - rise_capacitance_range (0.00323621, 0.00323621); + rise_capacitance_range (0.00273127, 0.00354019); fall_capacitance : 0.00299318; - fall_capacitance_range (0.00299318, 0.00299318); + fall_capacitance_range (0.00271761, 0.00352205); } pin (C) { direction : "input"; max_transition : 2.5074; capacitance : 0.00314535; rise_capacitance : 0.00331098; - rise_capacitance_range (0.00331098, 0.00331098); + rise_capacitance_range (0.00278767, 0.00368069); fall_capacitance : 0.00297971; - fall_capacitance_range (0.00297971, 0.00297971); + fall_capacitance_range (0.00281459, 0.00333588); } } cell (sg13g2_nand4_1) { @@ -21625,52 +21699,52 @@ library (sg13g2_stdcell_typ_1p50V_25C) { index_1 ("0.0186, 0.0966, 0.174, 0.3294, 0.6408, 1.263, 2.5074"); index_2 ("0.001, 0.0234, 0.039, 0.0648, 0.108, 0.18, 0.3"); values ( \ - "0.0203433, 0.0661229, 0.09698, 0.14794, 0.233404, 0.375118, 0.611626", \ - "0.0352683, 0.100658, 0.134336, 0.186227, 0.271487, 0.413469, 0.65047", \ + "0.0203433, 0.0661197, 0.0969804, 0.147969, 0.233109, 0.375118, 0.611619", \ + "0.0352683, 0.100658, 0.134331, 0.186227, 0.271477, 0.413473, 0.650205", \ "0.0421479, 0.125158, 0.164647, 0.22167, 0.309306, 0.451501, 0.687868", \ - "0.047803, 0.158136, 0.208655, 0.278088, 0.377518, 0.526717, 0.764858", \ - "0.0510951, 0.198519, 0.267085, 0.357885, 0.482684, 0.656967, 0.912223", \ - "0.0510961, 0.242665, 0.334327, 0.458822, 0.62598, 0.848168, 1.1555", \ - "0.0510971, 0.283029, 0.405043, 0.570479, 0.797905, 1.10222, 1.50208" \ + "0.047803, 0.158136, 0.208655, 0.278088, 0.377517, 0.526717, 0.764858", \ + "0.0510952, 0.198519, 0.267085, 0.357885, 0.482684, 0.656967, 0.912223", \ + "0.0510962, 0.242665, 0.334327, 0.458822, 0.62598, 0.848168, 1.15556", \ + "0.0510972, 0.283029, 0.405043, 0.570479, 0.797905, 1.10222, 1.50208" \ ); } rise_transition (TIMING_DELAY_7x7ds1) { index_1 ("0.0186, 0.0966, 0.174, 0.3294, 0.6408, 1.263, 2.5074"); index_2 ("0.001, 0.0234, 0.039, 0.0648, 0.108, 0.18, 0.3"); values ( \ - "0.0150685, 0.0792527, 0.125028, 0.200781, 0.328004, 0.539315, 0.891847", \ - "0.0310038, 0.0916892, 0.132864, 0.204275, 0.328279, 0.53955, 0.892323", \ - "0.0438564, 0.110302, 0.150696, 0.2178, 0.335804, 0.541261, 0.892324", \ - "0.0631977, 0.14583, 0.188864, 0.255586, 0.367142, 0.560594, 0.899216", \ + "0.0150685, 0.0791078, 0.125029, 0.200773, 0.327795, 0.539315, 0.89178", \ + "0.0310038, 0.0916893, 0.13284, 0.204275, 0.328287, 0.539622, 0.891966", \ + "0.0438564, 0.110302, 0.150696, 0.2178, 0.335804, 0.541261, 0.891967", \ + "0.0631977, 0.14583, 0.188864, 0.255586, 0.367141, 0.560594, 0.899216", \ "0.0967907, 0.203025, 0.256307, 0.330588, 0.443874, 0.628611, 0.946361", \ - "0.152397, 0.294307, 0.362769, 0.458045, 0.58805, 0.78162, 1.08882", \ - "0.246681, 0.441251, 0.529423, 0.654275, 0.826115, 1.05791, 1.39332" \ + "0.152397, 0.294307, 0.362769, 0.458045, 0.58805, 0.78162, 1.08894", \ + "0.246682, 0.441251, 0.529423, 0.654274, 0.826115, 1.0579, 1.39332" \ ); } cell_fall (TIMING_DELAY_7x7ds1) { index_1 ("0.0186, 0.0966, 0.174, 0.3294, 0.6408, 1.263, 2.5074"); index_2 ("0.001, 0.0234, 0.039, 0.0648, 0.108, 0.18, 0.3"); values ( \ - "0.0377962, 0.153866, 0.233036, 0.36371, 0.582361, 0.94656, 1.55402", \ - "0.056589, 0.183265, 0.262827, 0.39363, 0.612266, 0.977025, 1.5843", \ - "0.0694467, 0.210477, 0.292883, 0.42444, 0.643133, 1.00736, 1.61416", \ - "0.0891289, 0.25449, 0.345809, 0.484014, 0.704742, 1.06868, 1.67921", \ - "0.120333, 0.321597, 0.42856, 0.584841, 0.822662, 1.19429, 1.8008", \ - "0.169018, 0.423944, 0.551084, 0.737745, 1.0118, 1.42112, 2.05107", \ - "0.247147, 0.576387, 0.73761, 0.964413, 1.29181, 1.77147, 2.48134" \ + "0.0377931, 0.153866, 0.233034, 0.363707, 0.58236, 0.946859, 1.55401", \ + "0.0565889, 0.183286, 0.262829, 0.393642, 0.612291, 0.976719, 1.58431", \ + "0.0694467, 0.210477, 0.292883, 0.424436, 0.643136, 1.00736, 1.61415", \ + "0.0891288, 0.25449, 0.345808, 0.484014, 0.704769, 1.06868, 1.67922", \ + "0.120333, 0.321597, 0.42856, 0.584837, 0.822661, 1.19429, 1.80076", \ + "0.169018, 0.423944, 0.551084, 0.737744, 1.0118, 1.42112, 2.05106", \ + "0.247147, 0.576387, 0.737611, 0.964411, 1.29181, 1.77147, 2.48093" \ ); } fall_transition (TIMING_DELAY_7x7ds1) { index_1 ("0.0186, 0.0966, 0.174, 0.3294, 0.6408, 1.263, 2.5074"); index_2 ("0.001, 0.0234, 0.039, 0.0648, 0.108, 0.18, 0.3"); values ( \ - "0.0346375, 0.188417, 0.295592, 0.473059, 0.770062, 1.26432, 2.08979", \ - "0.0469123, 0.192877, 0.297203, 0.4736, 0.770063, 1.26489, 2.0898", \ - "0.0572255, 0.206126, 0.306569, 0.477823, 0.770582, 1.2649, 2.08981", \ - "0.0758952, 0.235522, 0.334615, 0.498715, 0.781302, 1.27346, 2.09186", \ - "0.107751, 0.2875, 0.391937, 0.558654, 0.831544, 1.29649, 2.09777", \ - "0.161399, 0.375172, 0.49144, 0.668347, 0.952149, 1.40828, 2.17315", \ - "0.252179, 0.529599, 0.659503, 0.859636, 1.16465, 1.64193, 2.40699" \ + "0.0346281, 0.188417, 0.295591, 0.473059, 0.770061, 1.26499, 2.08979", \ + "0.0469122, 0.192897, 0.297195, 0.473604, 0.770062, 1.265, 2.0898", \ + "0.0572255, 0.206125, 0.306568, 0.477491, 0.770517, 1.26501, 2.08981", \ + "0.0758952, 0.235522, 0.334615, 0.498714, 0.781334, 1.27295, 2.09187", \ + "0.107751, 0.2875, 0.391936, 0.558627, 0.831543, 1.29648, 2.09778", \ + "0.161399, 0.375171, 0.491439, 0.668346, 0.952147, 1.40826, 2.17315", \ + "0.252179, 0.529598, 0.659503, 0.859637, 1.16465, 1.64193, 2.40667" \ ); } } @@ -21682,52 +21756,52 @@ library (sg13g2_stdcell_typ_1p50V_25C) { index_1 ("0.0186, 0.0966, 0.174, 0.3294, 0.6408, 1.263, 2.5074"); index_2 ("0.001, 0.0234, 0.039, 0.0648, 0.108, 0.18, 0.3"); values ( \ - "0.0235438, 0.0690594, 0.0999062, 0.15087, 0.236208, 0.378067, 0.614537", \ - "0.041727, 0.104067, 0.137394, 0.189167, 0.274385, 0.416369, 0.653086", \ - "0.0511011, 0.12934, 0.168157, 0.224833, 0.312276, 0.454339, 0.690762", \ - "0.0602309, 0.163748, 0.213176, 0.281857, 0.380735, 0.529758, 0.767745", \ - "0.0695863, 0.207117, 0.273756, 0.363285, 0.48696, 0.660509, 0.915552", \ - "0.073064, 0.256626, 0.345148, 0.467, 0.631907, 0.853059, 1.15951", \ - "0.073065, 0.307915, 0.424627, 0.584929, 0.808954, 1.1107, 1.50834" \ + "0.0235439, 0.0690299, 0.0999158, 0.150876, 0.236053, 0.378063, 0.614538", \ + "0.041727, 0.104067, 0.1374, 0.18917, 0.274395, 0.416268, 0.653495", \ + "0.0511011, 0.12934, 0.168157, 0.224833, 0.312276, 0.454373, 0.690763", \ + "0.0602309, 0.163748, 0.213176, 0.281857, 0.380735, 0.529759, 0.767702", \ + "0.0695863, 0.207117, 0.273756, 0.363285, 0.48696, 0.660509, 0.915537", \ + "0.0730641, 0.256626, 0.345148, 0.467, 0.631907, 0.853059, 1.15951", \ + "0.0730651, 0.307915, 0.424628, 0.584929, 0.808954, 1.1107, 1.50834" \ ); } rise_transition (TIMING_DELAY_7x7ds1) { index_1 ("0.0186, 0.0966, 0.174, 0.3294, 0.6408, 1.263, 2.5074"); index_2 ("0.001, 0.0234, 0.039, 0.0648, 0.108, 0.18, 0.3"); values ( \ - "0.0178481, 0.0829872, 0.128338, 0.204228, 0.331269, 0.542815, 0.895376", \ - "0.0340567, 0.0945738, 0.135948, 0.207524, 0.331708, 0.542816, 0.89545", \ - "0.046888, 0.113185, 0.153574, 0.220958, 0.339065, 0.544777, 0.895451", \ - "0.0666169, 0.14869, 0.191781, 0.258564, 0.370211, 0.563906, 0.902612", \ - "0.0997173, 0.206544, 0.258684, 0.333667, 0.446966, 0.631812, 0.949354", \ - "0.15457, 0.295418, 0.36408, 0.457858, 0.590005, 0.785307, 1.09228", \ - "0.245251, 0.439708, 0.528841, 0.652876, 0.823525, 1.05952, 1.39435" \ + "0.0178481, 0.0829219, 0.128338, 0.204219, 0.331152, 0.542815, 0.895379", \ + "0.0340567, 0.094574, 0.135946, 0.207573, 0.33173, 0.543318, 0.895995", \ + "0.046888, 0.113185, 0.153574, 0.220958, 0.339065, 0.544631, 0.895996", \ + "0.0666168, 0.14869, 0.191781, 0.258568, 0.370209, 0.563908, 0.902512", \ + "0.0997172, 0.206544, 0.258684, 0.333667, 0.446966, 0.631812, 0.949542", \ + "0.15457, 0.295418, 0.36408, 0.457858, 0.590005, 0.785307, 1.09227", \ + "0.245252, 0.439708, 0.528841, 0.652876, 0.823525, 1.05952, 1.39435" \ ); } cell_fall (TIMING_DELAY_7x7ds1) { index_1 ("0.0186, 0.0966, 0.174, 0.3294, 0.6408, 1.263, 2.5074"); index_2 ("0.001, 0.0234, 0.039, 0.0648, 0.108, 0.18, 0.3"); values ( \ - "0.0469028, 0.162414, 0.241661, 0.372254, 0.590903, 0.954926, 1.56239", \ - "0.0625899, 0.187218, 0.266957, 0.397967, 0.616772, 0.981217, 1.58879", \ - "0.0733651, 0.209894, 0.291859, 0.423768, 0.642902, 1.00744, 1.61454", \ - "0.090171, 0.248246, 0.336639, 0.473654, 0.694797, 1.05955, 1.67112", \ - "0.118593, 0.309728, 0.411197, 0.561434, 0.794762, 1.16602, 1.77412", \ - "0.16341, 0.405534, 0.526329, 0.7015, 0.962959, 1.36081, 1.98598", \ - "0.233612, 0.548174, 0.701958, 0.916069, 1.22409, 1.67887, 2.35985" \ + "0.0469029, 0.162414, 0.241661, 0.37214, 0.590708, 0.95493, 1.56238", \ + "0.0625899, 0.187218, 0.266947, 0.39795, 0.616743, 0.9812, 1.58852", \ + "0.073365, 0.209893, 0.291859, 0.423758, 0.642906, 1.00738, 1.61517", \ + "0.0901709, 0.248245, 0.336638, 0.473652, 0.694809, 1.05955, 1.6666", \ + "0.118593, 0.309727, 0.411196, 0.561433, 0.794761, 1.16602, 1.77412", \ + "0.16341, 0.405533, 0.526328, 0.7015, 0.962958, 1.36081, 1.98598", \ + "0.233612, 0.548173, 0.701957, 0.916068, 1.22409, 1.67886, 2.35985" \ ); } fall_transition (TIMING_DELAY_7x7ds1) { index_1 ("0.0186, 0.0966, 0.174, 0.3294, 0.6408, 1.263, 2.5074"); index_2 ("0.001, 0.0234, 0.039, 0.0648, 0.108, 0.18, 0.3"); values ( \ - "0.0346291, 0.188515, 0.295832, 0.473117, 0.770055, 1.26484, 2.08979", \ - "0.0449371, 0.191631, 0.296671, 0.473581, 0.770056, 1.26485, 2.0898", \ - "0.0556217, 0.201166, 0.303134, 0.476106, 0.770346, 1.26492, 2.08981", \ - "0.0750235, 0.224016, 0.323917, 0.490501, 0.777256, 1.27023, 2.09291", \ - "0.107912, 0.269186, 0.370055, 0.535385, 0.812209, 1.28615, 2.09614", \ - "0.160141, 0.350025, 0.457992, 0.626542, 0.905457, 1.36408, 2.14475", \ - "0.246088, 0.492266, 0.613488, 0.795652, 1.08469, 1.54917, 2.31572" \ + "0.034624, 0.188514, 0.295831, 0.47283, 0.76964, 1.26486, 2.08977", \ + "0.044937, 0.191631, 0.29667, 0.473595, 0.769641, 1.26487, 2.08978", \ + "0.0556216, 0.201166, 0.303133, 0.476088, 0.770334, 1.26487, 2.08979", \ + "0.0750233, 0.224016, 0.323904, 0.490606, 0.777617, 1.27189, 2.0898", \ + "0.107912, 0.269186, 0.370055, 0.535384, 0.812207, 1.28614, 2.09606", \ + "0.160141, 0.350024, 0.457991, 0.62654, 0.905456, 1.36407, 2.14478", \ + "0.246088, 0.492266, 0.613488, 0.795651, 1.08469, 1.54917, 2.31572" \ ); } } @@ -21739,12 +21813,12 @@ library (sg13g2_stdcell_typ_1p50V_25C) { index_1 ("0.0186, 0.0966, 0.174, 0.3294, 0.6408, 1.263, 2.5074"); index_2 ("0.001, 0.0234, 0.039, 0.0648, 0.108, 0.18, 0.3"); values ( \ - "0.0253641, 0.0715074, 0.102529, 0.153627, 0.238945, 0.381008, 0.617551", \ - "0.0459278, 0.106849, 0.14006, 0.191827, 0.277186, 0.419126, 0.656312", \ - "0.057286, 0.132807, 0.171245, 0.227609, 0.315082, 0.457234, 0.693643", \ - "0.0693022, 0.16878, 0.217407, 0.285433, 0.383862, 0.532687, 0.770674", \ + "0.0253619, 0.0715054, 0.102515, 0.153732, 0.239159, 0.381007, 0.617549", \ + "0.0459278, 0.106849, 0.14006, 0.191827, 0.277183, 0.419128, 0.655987", \ + "0.057286, 0.132807, 0.171245, 0.227609, 0.315082, 0.457236, 0.693721", \ + "0.0693022, 0.16878, 0.217407, 0.285433, 0.383862, 0.532687, 0.770693", \ "0.0840516, 0.214731, 0.280105, 0.368045, 0.49094, 0.663551, 0.91868", \ - "0.0971891, 0.269335, 0.355429, 0.475206, 0.638042, 0.85761, 1.16338", \ + "0.0971892, 0.269335, 0.355429, 0.475206, 0.638042, 0.85761, 1.16338", \ "0.101793, 0.331712, 0.444148, 0.60077, 0.81993, 1.1187, 1.51411" \ ); } @@ -21752,12 +21826,12 @@ library (sg13g2_stdcell_typ_1p50V_25C) { index_1 ("0.0186, 0.0966, 0.174, 0.3294, 0.6408, 1.263, 2.5074"); index_2 ("0.001, 0.0234, 0.039, 0.0648, 0.108, 0.18, 0.3"); values ( \ - "0.0204506, 0.085821, 0.13148, 0.207422, 0.334494, 0.546255, 0.898955", \ - "0.0366007, 0.0972659, 0.138832, 0.210617, 0.33501, 0.546555, 0.899447", \ - "0.0496842, 0.115754, 0.156328, 0.223825, 0.342337, 0.548081, 0.899448", \ - "0.0699733, 0.151165, 0.194312, 0.261443, 0.37319, 0.567057, 0.906089", \ + "0.0204469, 0.0858176, 0.131869, 0.207527, 0.334743, 0.546261, 0.898955", \ + "0.0366007, 0.0972659, 0.138832, 0.210617, 0.335146, 0.546554, 0.898972", \ + "0.0496842, 0.115754, 0.156328, 0.223825, 0.342337, 0.548083, 0.898973", \ + "0.0699733, 0.151165, 0.194312, 0.261443, 0.37319, 0.567057, 0.905983", \ "0.103697, 0.209165, 0.261346, 0.335817, 0.449522, 0.63485, 0.952683", \ - "0.159259, 0.298212, 0.36657, 0.460771, 0.592419, 0.786982, 1.09532", \ + "0.15926, 0.298212, 0.36657, 0.460771, 0.59242, 0.786982, 1.09532", \ "0.250776, 0.44133, 0.529522, 0.65266, 0.825018, 1.06143, 1.39827" \ ); } @@ -21765,26 +21839,26 @@ library (sg13g2_stdcell_typ_1p50V_25C) { index_1 ("0.0186, 0.0966, 0.174, 0.3294, 0.6408, 1.263, 2.5074"); index_2 ("0.001, 0.0234, 0.039, 0.0648, 0.108, 0.18, 0.3"); values ( \ - "0.0522535, 0.167788, 0.246884, 0.377646, 0.596246, 0.960567, 1.56772", \ - "0.0663801, 0.188087, 0.267724, 0.398787, 0.617497, 0.981972, 1.58932", \ - "0.075325, 0.205344, 0.286679, 0.418333, 0.637378, 1.00195, 1.60916", \ - "0.08789, 0.235387, 0.321034, 0.456417, 0.676997, 1.04158, 1.64949", \ - "0.108961, 0.28541, 0.380461, 0.52509, 0.754347, 1.12331, 1.73107", \ - "0.144047, 0.366114, 0.478095, 0.640075, 0.888383, 1.27605, 1.89514", \ - "0.197618, 0.4838, 0.625457, 0.823726, 1.10631, 1.53357, 2.19101" \ + "0.0522538, 0.167788, 0.246885, 0.37759, 0.595984, 0.960567, 1.5677", \ + "0.0664281, 0.188086, 0.267729, 0.398897, 0.617475, 0.981976, 1.58952", \ + "0.0753249, 0.205344, 0.286679, 0.418333, 0.637378, 1.00193, 1.60916", \ + "0.0878899, 0.235387, 0.321033, 0.456415, 0.676995, 1.04164, 1.64949", \ + "0.108961, 0.28541, 0.38046, 0.525089, 0.754346, 1.12332, 1.73106", \ + "0.144046, 0.366114, 0.478094, 0.640074, 0.88838, 1.27605, 1.89515", \ + "0.197618, 0.4838, 0.625456, 0.823725, 1.10631, 1.53357, 2.19101" \ ); } fall_transition (TIMING_DELAY_7x7ds1) { index_1 ("0.0186, 0.0966, 0.174, 0.3294, 0.6408, 1.263, 2.5074"); index_2 ("0.001, 0.0234, 0.039, 0.0648, 0.108, 0.18, 0.3"); values ( \ - "0.0344699, 0.188513, 0.295634, 0.4731, 0.770079, 1.26498, 2.08979", \ - "0.0416877, 0.190686, 0.296341, 0.475552, 0.77008, 1.26499, 2.0898", \ - "0.050436, 0.197581, 0.301039, 0.475553, 0.770428, 1.265, 2.08981", \ - "0.0690568, 0.215029, 0.316718, 0.485979, 0.775733, 1.26912, 2.09102", \ - "0.103615, 0.253106, 0.352656, 0.519341, 0.801455, 1.28002, 2.09358", \ - "0.156574, 0.329927, 0.429909, 0.594816, 0.871398, 1.33959, 2.13075", \ - "0.243308, 0.464899, 0.577063, 0.747384, 1.02459, 1.48441, 2.26057" \ + "0.0344697, 0.188513, 0.295634, 0.473128, 0.769467, 1.26498, 2.08979", \ + "0.0417268, 0.190686, 0.296358, 0.475484, 0.769899, 1.26499, 2.0898", \ + "0.0504359, 0.197648, 0.301038, 0.475485, 0.770485, 1.265, 2.08981", \ + "0.0690568, 0.215029, 0.316718, 0.485975, 0.775731, 1.26989, 2.09101", \ + "0.103615, 0.253105, 0.352655, 0.519263, 0.801453, 1.28003, 2.09358", \ + "0.156573, 0.329927, 0.429909, 0.594815, 0.871393, 1.33961, 2.13077", \ + "0.243307, 0.464898, 0.577062, 0.747384, 1.02459, 1.48441, 2.26058" \ ); } } @@ -21796,52 +21870,52 @@ library (sg13g2_stdcell_typ_1p50V_25C) { index_1 ("0.0186, 0.0966, 0.174, 0.3294, 0.6408, 1.263, 2.5074"); index_2 ("0.001, 0.0234, 0.039, 0.0648, 0.108, 0.18, 0.3"); values ( \ - "0.0261104, 0.0732676, 0.104514, 0.155796, 0.24114, 0.38306, 0.619353", \ - "0.0486801, 0.10892, 0.142106, 0.193942, 0.279321, 0.421123, 0.657744", \ - "0.0616007, 0.135507, 0.173679, 0.229924, 0.317266, 0.45923, 0.69544", \ - "0.0760698, 0.172999, 0.220652, 0.288321, 0.386344, 0.534865, 0.772665", \ + "0.0261073, 0.0732702, 0.104495, 0.155746, 0.241139, 0.383105, 0.619372", \ + "0.0486801, 0.108953, 0.142167, 0.193925, 0.279348, 0.421138, 0.657813", \ + "0.0616007, 0.135507, 0.173679, 0.229924, 0.317266, 0.459232, 0.69544", \ + "0.0760698, 0.172999, 0.220653, 0.288321, 0.386344, 0.534865, 0.772664", \ "0.095462, 0.22141, 0.285284, 0.372216, 0.494155, 0.666118, 0.920332", \ "0.117998, 0.280898, 0.364568, 0.4819, 0.643509, 0.86141, 1.166", \ - "0.141857, 0.355541, 0.462179, 0.615221, 0.830132, 1.12558, 1.51834" \ + "0.141857, 0.355542, 0.462179, 0.615221, 0.830132, 1.12558, 1.51834" \ ); } rise_transition (TIMING_DELAY_7x7ds1) { index_1 ("0.0186, 0.0966, 0.174, 0.3294, 0.6408, 1.263, 2.5074"); index_2 ("0.001, 0.0234, 0.039, 0.0648, 0.108, 0.18, 0.3"); values ( \ - "0.0228, 0.0891118, 0.134317, 0.210203, 0.33716, 0.548572, 0.901128", \ - "0.039002, 0.0996871, 0.141401, 0.213275, 0.337897, 0.54879, 0.901129", \ - "0.0522826, 0.118154, 0.158749, 0.226272, 0.344802, 0.550265, 0.90113", \ - "0.0734521, 0.153795, 0.196595, 0.263517, 0.375473, 0.569256, 0.908015", \ - "0.107251, 0.211755, 0.263294, 0.337819, 0.45157, 0.636845, 0.954557", \ + "0.0228017, 0.0884284, 0.13447, 0.210153, 0.337161, 0.548481, 0.90072", \ + "0.039002, 0.0996328, 0.141357, 0.213247, 0.337906, 0.548584, 0.90079", \ + "0.0522826, 0.118154, 0.158748, 0.226273, 0.344802, 0.550416, 0.900791", \ + "0.0734521, 0.153795, 0.196565, 0.263517, 0.375473, 0.56925, 0.908014", \ + "0.107251, 0.211755, 0.263295, 0.337819, 0.45157, 0.636845, 0.954557", \ "0.164285, 0.300193, 0.368691, 0.462164, 0.594625, 0.789443, 1.09689", \ - "0.25875, 0.442459, 0.531523, 0.653635, 0.825363, 1.06225, 1.39849" \ + "0.258749, 0.442459, 0.531523, 0.653631, 0.825363, 1.06225, 1.39849" \ ); } cell_fall (TIMING_DELAY_7x7ds1) { index_1 ("0.0186, 0.0966, 0.174, 0.3294, 0.6408, 1.263, 2.5074"); index_2 ("0.001, 0.0234, 0.039, 0.0648, 0.108, 0.18, 0.3"); values ( \ - "0.0548024, 0.170327, 0.249378, 0.38018, 0.598767, 0.962729, 1.57021", \ - "0.0680886, 0.187851, 0.267453, 0.3985, 0.617253, 0.98174, 1.58933", \ - "0.0757811, 0.201193, 0.282068, 0.413624, 0.632627, 0.997193, 1.60483", \ - "0.0853314, 0.223283, 0.30747, 0.44177, 0.661946, 1.0267, 1.63438", \ - "0.0981347, 0.261129, 0.351762, 0.492938, 0.719563, 1.0873, 1.69502", \ - "0.120245, 0.322062, 0.426281, 0.579531, 0.820415, 1.20254, 1.81758", \ - "0.154614, 0.409878, 0.539591, 0.722381, 0.99016, 1.39919, 2.04075" \ + "0.054805, 0.170321, 0.249377, 0.380187, 0.598792, 0.962734, 1.57024", \ + "0.0681347, 0.187851, 0.267461, 0.398517, 0.617251, 0.981723, 1.58933", \ + "0.075781, 0.201193, 0.282068, 0.413573, 0.632615, 0.997197, 1.60483", \ + "0.0853312, 0.223283, 0.307469, 0.441769, 0.661946, 1.02669, 1.63437", \ + "0.0981345, 0.261128, 0.351761, 0.492937, 0.719564, 1.08729, 1.69474", \ + "0.120244, 0.322062, 0.426281, 0.579531, 0.820413, 1.20254, 1.81758", \ + "0.154613, 0.409877, 0.53959, 0.72238, 0.990158, 1.39919, 2.04075" \ ); } fall_transition (TIMING_DELAY_7x7ds1) { index_1 ("0.0186, 0.0966, 0.174, 0.3294, 0.6408, 1.263, 2.5074"); index_2 ("0.001, 0.0234, 0.039, 0.0648, 0.108, 0.18, 0.3"); values ( \ - "0.0343658, 0.188589, 0.295756, 0.473141, 0.770076, 1.26475, 2.08977", \ - "0.0392378, 0.189952, 0.296113, 0.473397, 0.770077, 1.26476, 2.08978", \ - "0.0453668, 0.195116, 0.29966, 0.474555, 0.770078, 1.26489, 2.08979", \ - "0.0602731, 0.208238, 0.311624, 0.48324, 0.774406, 1.26875, 2.0898", \ - "0.0928905, 0.239066, 0.340497, 0.508882, 0.794648, 1.27737, 2.0932", \ - "0.146979, 0.308305, 0.406382, 0.570282, 0.850475, 1.32384, 2.12282", \ - "0.23123, 0.43024, 0.540766, 0.706991, 0.978996, 1.44322, 2.22707" \ + "0.0343654, 0.188588, 0.295756, 0.473088, 0.770035, 1.26428, 2.08979", \ + "0.0392315, 0.189951, 0.296301, 0.47329, 0.770036, 1.26429, 2.0898", \ + "0.0453668, 0.195116, 0.299659, 0.474538, 0.770037, 1.2649, 2.08981", \ + "0.060273, 0.208237, 0.311624, 0.483238, 0.774155, 1.26874, 2.08982", \ + "0.0928904, 0.239065, 0.340497, 0.508881, 0.794974, 1.27734, 2.09349", \ + "0.146978, 0.308304, 0.406382, 0.570282, 0.850474, 1.32384, 2.12281", \ + "0.231229, 0.430239, 0.540766, 0.706991, 0.978995, 1.44321, 2.22707" \ ); } } @@ -21851,26 +21925,26 @@ library (sg13g2_stdcell_typ_1p50V_25C) { index_1 ("0.0186, 0.0966, 0.174, 0.3294, 0.6408, 1.263, 2.5074"); index_2 ("0.001, 0.0234, 0.039, 0.0648, 0.108, 0.18, 0.3"); values ( \ - "0.00290895, 0.00348704, 0.00348751, 0.00341043, 0.00331936, 0.00293994, 0.00231262", \ - "0.00321714, 0.00337686, 0.00351499, 0.00336485, 0.00321588, 0.00300945, 0.00253461", \ - "0.00411742, 0.00366781, 0.0035559, 0.00361171, 0.00343137, 0.00343098, 0.00237973", \ - "0.00635171, 0.00481721, 0.00449839, 0.00411791, 0.00389181, 0.00322075, 0.00359626", \ - "0.0113769, 0.00815806, 0.00740356, 0.00646002, 0.00552735, 0.00443737, 0.00444586", \ - "0.0215119, 0.0161183, 0.0142344, 0.0124477, 0.0104182, 0.00843075, 0.00618715", \ - "0.042475, 0.0345301, 0.0311376, 0.0274967, 0.0236431, 0.019569, 0.0153914" \ + "0.00290894, 0.00345195, 0.00348744, 0.00340137, 0.0032386, 0.00294029, 0.0023635", \ + "0.00321745, 0.00336429, 0.00347767, 0.0033647, 0.00323263, 0.00307397, 0.00237976", \ + "0.0041169, 0.00366783, 0.0035559, 0.00361201, 0.00343137, 0.00343098, 0.00237973", \ + "0.0063517, 0.00481721, 0.00449677, 0.00411791, 0.00388633, 0.00322082, 0.00359664", \ + "0.0113767, 0.00815723, 0.00740393, 0.00646769, 0.00552736, 0.00443737, 0.00401918", \ + "0.0215113, 0.0161183, 0.0142344, 0.0124477, 0.0104182, 0.00843194, 0.00609719", \ + "0.0424755, 0.0345303, 0.0311376, 0.0274967, 0.0236431, 0.0195695, 0.0153914" \ ); } fall_power (POWER_7x7ds1) { index_1 ("0.0186, 0.0966, 0.174, 0.3294, 0.6408, 1.263, 2.5074"); index_2 ("0.001, 0.0234, 0.039, 0.0648, 0.108, 0.18, 0.3"); values ( \ - "0.00660475, 0.00710647, 0.0071025, 0.00705841, 0.00691822, 0.00661205, 0.00616082", \ - "0.00674748, 0.00683418, 0.00697106, 0.00693002, 0.0067903, 0.00653377, 0.00612957", \ - "0.00755399, 0.00702636, 0.0070354, 0.00706419, 0.00678413, 0.00654915, 0.00614749", \ - "0.00959013, 0.00800559, 0.00761737, 0.00756554, 0.00705216, 0.0071287, 0.00651576", \ - "0.0140465, 0.0109545, 0.0101191, 0.00920155, 0.00857792, 0.0074571, 0.00775561", \ - "0.0239117, 0.0181785, 0.0164458, 0.014682, 0.0128138, 0.0108966, 0.00937982", \ - "0.0444881, 0.0353476, 0.0320985, 0.028493, 0.0246593, 0.0206517, 0.0163698" \ + "0.00660404, 0.00710541, 0.00710271, 0.00705785, 0.00693125, 0.00663848, 0.00616024", \ + "0.00674747, 0.00683708, 0.00697056, 0.00692858, 0.00679089, 0.00650732, 0.006171", \ + "0.00755446, 0.00702634, 0.00703475, 0.00698199, 0.00678763, 0.00654915, 0.00616249", \ + "0.00959013, 0.00800565, 0.00761723, 0.00756562, 0.00705331, 0.00711341, 0.00651789", \ + "0.0140467, 0.0109545, 0.0101118, 0.00917796, 0.00857808, 0.00745695, 0.00677365", \ + "0.023912, 0.0181788, 0.0164458, 0.014682, 0.0128138, 0.0109498, 0.00995626", \ + "0.0444872, 0.0353477, 0.0320987, 0.0284919, 0.024659, 0.0206528, 0.0163322" \ ); } } @@ -21880,26 +21954,26 @@ library (sg13g2_stdcell_typ_1p50V_25C) { index_1 ("0.0186, 0.0966, 0.174, 0.3294, 0.6408, 1.263, 2.5074"); index_2 ("0.001, 0.0234, 0.039, 0.0648, 0.108, 0.18, 0.3"); values ( \ - "0.00329437, 0.00362469, 0.00351895, 0.00343889, 0.00328737, 0.00295636, 0.00236929", \ - "0.00344236, 0.00348927, 0.00359135, 0.00343107, 0.00322163, 0.00295682, 0.0024096", \ - "0.00427671, 0.00379877, 0.00363622, 0.00366444, 0.00332311, 0.00338687, 0.0023995", \ - "0.00641433, 0.00495859, 0.00462179, 0.00417678, 0.00396347, 0.00325811, 0.00406848", \ - "0.0112484, 0.0085309, 0.00762515, 0.00671366, 0.00574648, 0.00463972, 0.00366725", \ - "0.0212295, 0.0165441, 0.0145925, 0.0126563, 0.0106775, 0.00878789, 0.00652474", \ - "0.0416154, 0.0349643, 0.0319371, 0.028183, 0.02408, 0.0200568, 0.0157478" \ + "0.00329241, 0.00361768, 0.00352357, 0.00343657, 0.00326487, 0.0029562, 0.00239824", \ + "0.00344257, 0.00348912, 0.00352158, 0.00344468, 0.0032242, 0.00312705, 0.00256529", \ + "0.00427839, 0.00379877, 0.0036362, 0.00366451, 0.00332311, 0.00299454, 0.00239949", \ + "0.00641533, 0.00496002, 0.00462189, 0.00414641, 0.00395114, 0.00325819, 0.00408057", \ + "0.0112505, 0.00853027, 0.00762583, 0.00671373, 0.0057464, 0.00463972, 0.00453031", \ + "0.0212297, 0.0165441, 0.0145925, 0.0126559, 0.0106789, 0.00878789, 0.00652452", \ + "0.0416156, 0.0349651, 0.0319371, 0.028183, 0.0240803, 0.0200567, 0.0157478" \ ); } fall_power (POWER_7x7ds1) { index_1 ("0.0186, 0.0966, 0.174, 0.3294, 0.6408, 1.263, 2.5074"); index_2 ("0.001, 0.0234, 0.039, 0.0648, 0.108, 0.18, 0.3"); values ( \ - "0.00947848, 0.00984223, 0.00984013, 0.00976383, 0.00961206, 0.00928348, 0.00894773", \ - "0.00917966, 0.00949672, 0.00964926, 0.00960454, 0.00949433, 0.00919157, 0.00885742", \ - "0.00959204, 0.00954241, 0.00965479, 0.00967078, 0.00944047, 0.00920453, 0.0088312", \ - "0.0111438, 0.0101786, 0.00993658, 0.00997981, 0.00958797, 0.0095839, 0.00927118", \ - "0.0154266, 0.0125942, 0.0119671, 0.0111978, 0.0107771, 0.00994763, 0.00984288", \ - "0.0249883, 0.0193876, 0.0177912, 0.0161356, 0.0146055, 0.0128236, 0.0116937", \ - "0.045078, 0.0360246, 0.0327403, 0.0291022, 0.0254054, 0.021911, 0.0180389" \ + "0.00949051, 0.00984281, 0.00983871, 0.00976055, 0.00958687, 0.00928312, 0.00892847", \ + "0.00917972, 0.00949886, 0.0096373, 0.00961071, 0.00945179, 0.00919105, 0.00882176", \ + "0.00959163, 0.00954054, 0.00966872, 0.00966912, 0.00944001, 0.00920122, 0.00881092", \ + "0.0111416, 0.010182, 0.0099361, 0.0100133, 0.00962616, 0.00968548, 0.00882936", \ + "0.0154291, 0.0125944, 0.0119639, 0.0111769, 0.0107771, 0.00994656, 0.0105063", \ + "0.0249872, 0.0193874, 0.0177928, 0.0161317, 0.0146056, 0.0128235, 0.0117677", \ + "0.0450782, 0.0360238, 0.0327398, 0.0291022, 0.0254109, 0.021911, 0.0180404" \ ); } } @@ -21909,26 +21983,26 @@ library (sg13g2_stdcell_typ_1p50V_25C) { index_1 ("0.0186, 0.0966, 0.174, 0.3294, 0.6408, 1.263, 2.5074"); index_2 ("0.001, 0.0234, 0.039, 0.0648, 0.108, 0.18, 0.3"); values ( \ - "0.00369899, 0.00382108, 0.00373541, 0.00364686, 0.00347053, 0.00315921, 0.00257706", \ - "0.00378662, 0.00371819, 0.00380478, 0.00356131, 0.00338708, 0.00320078, 0.00261845", \ - "0.00459957, 0.00407651, 0.00388876, 0.00383743, 0.00359201, 0.00389073, 0.00245896", \ - "0.00677054, 0.00526856, 0.00491429, 0.00448751, 0.00416624, 0.00342158, 0.00278775", \ - "0.0117572, 0.00895719, 0.00800024, 0.00700569, 0.00590967, 0.00496995, 0.00425062", \ - "0.022138, 0.0173562, 0.0153092, 0.0132968, 0.0111813, 0.00900821, 0.00670909", \ - "0.0436178, 0.0367602, 0.0336017, 0.0295529, 0.0251923, 0.0208879, 0.0164757" \ + "0.00370191, 0.0038192, 0.0038185, 0.00367413, 0.00353301, 0.00315097, 0.00257647", \ + "0.00378269, 0.00371819, 0.00380486, 0.00356117, 0.00340018, 0.003201, 0.0024981", \ + "0.00459595, 0.0040765, 0.00388876, 0.00383743, 0.00359201, 0.00389103, 0.00255902", \ + "0.00677287, 0.00526828, 0.00491429, 0.00448751, 0.00416624, 0.00342128, 0.00287432", \ + "0.0117565, 0.00895675, 0.00800143, 0.00700553, 0.00590967, 0.00496995, 0.00425062", \ + "0.022138, 0.0173559, 0.0153089, 0.0132964, 0.0111815, 0.00901745, 0.00670909", \ + "0.0435872, 0.0367601, 0.033601, 0.0295523, 0.0251923, 0.0208879, 0.0164736" \ ); } fall_power (POWER_7x7ds1) { index_1 ("0.0186, 0.0966, 0.174, 0.3294, 0.6408, 1.263, 2.5074"); index_2 ("0.001, 0.0234, 0.039, 0.0648, 0.108, 0.18, 0.3"); values ( \ - "0.0119677, 0.0123338, 0.0123188, 0.0122607, 0.012128, 0.0118133, 0.0114023", \ - "0.0115644, 0.0119556, 0.0121218, 0.0122718, 0.0119454, 0.0116683, 0.0113914", \ - "0.0117765, 0.011919, 0.0120064, 0.0121386, 0.0119059, 0.0116866, 0.0113358", \ - "0.0130097, 0.012411, 0.0122394, 0.0122946, 0.0120649, 0.0119333, 0.0114854", \ - "0.0171616, 0.0145996, 0.0140773, 0.0135286, 0.0130532, 0.0122436, 0.0127052", \ - "0.0271412, 0.0215838, 0.0199271, 0.0183756, 0.016872, 0.0151803, 0.0149144", \ - "0.048191, 0.039068, 0.0356539, 0.0319293, 0.0281526, 0.024589, 0.0208266" \ + "0.0119698, 0.0123338, 0.0123192, 0.0122505, 0.0120776, 0.0118047, 0.0113993", \ + "0.0115667, 0.0119529, 0.0121389, 0.0122676, 0.0119558, 0.0117286, 0.0113223", \ + "0.0117743, 0.0119277, 0.0120066, 0.0121386, 0.011896, 0.0115884, 0.0113358", \ + "0.0130097, 0.012414, 0.0122398, 0.0122944, 0.0120647, 0.0119565, 0.0114842", \ + "0.0171609, 0.0145997, 0.0140797, 0.0135001, 0.0130529, 0.0122434, 0.0127312", \ + "0.0271415, 0.0215836, 0.019927, 0.0183763, 0.0168038, 0.0152253, 0.0149215", \ + "0.0481925, 0.0390679, 0.0356546, 0.0319291, 0.0281523, 0.0245888, 0.0208905" \ ); } } @@ -21938,26 +22012,26 @@ library (sg13g2_stdcell_typ_1p50V_25C) { index_1 ("0.0186, 0.0966, 0.174, 0.3294, 0.6408, 1.263, 2.5074"); index_2 ("0.001, 0.0234, 0.039, 0.0648, 0.108, 0.18, 0.3"); values ( \ - "0.00404144, 0.00412151, 0.00397175, 0.00387279, 0.0037018, 0.00337496, 0.00285699", \ - "0.00415657, 0.00398429, 0.00405113, 0.00378033, 0.00362821, 0.00334986, 0.00273034", \ - "0.00495982, 0.00436342, 0.00415485, 0.00412375, 0.00379586, 0.0034222, 0.00267999", \ - "0.00724081, 0.00564862, 0.00521092, 0.0047099, 0.0043772, 0.00364034, 0.00414669", \ - "0.0124927, 0.00945838, 0.00841374, 0.00737158, 0.00624377, 0.0051409, 0.00496282", \ - "0.0233788, 0.018263, 0.0161336, 0.0138768, 0.0117391, 0.00936726, 0.00701285", \ - "0.0460961, 0.0388391, 0.0353461, 0.0311739, 0.0263175, 0.0218209, 0.0170558" \ + "0.00403747, 0.00402514, 0.00400075, 0.00386993, 0.00369774, 0.00335028, 0.00280371", \ + "0.004155, 0.00397289, 0.00405397, 0.00377065, 0.00363407, 0.00329865, 0.00274549", \ + "0.00496041, 0.00436342, 0.00415449, 0.00412583, 0.00379608, 0.00397656, 0.00267999", \ + "0.00724158, 0.00564969, 0.00519999, 0.00470997, 0.00441319, 0.00359801, 0.00413731", \ + "0.012493, 0.00945657, 0.00841769, 0.00737134, 0.00624377, 0.0051409, 0.00496282", \ + "0.0233791, 0.018263, 0.0161324, 0.0138766, 0.0117403, 0.00936726, 0.00701285", \ + "0.0460959, 0.0388389, 0.0353463, 0.0311783, 0.0263176, 0.021821, 0.0170558" \ ); } fall_power (POWER_7x7ds1) { index_1 ("0.0186, 0.0966, 0.174, 0.3294, 0.6408, 1.263, 2.5074"); index_2 ("0.001, 0.0234, 0.039, 0.0648, 0.108, 0.18, 0.3"); values ( \ - "0.0143698, 0.0147452, 0.0147231, 0.0146474, 0.0145226, 0.0142189, 0.0138822", \ - "0.0139302, 0.0143374, 0.0144382, 0.0144889, 0.014322, 0.0140634, 0.0137513", \ - "0.0140425, 0.0142666, 0.0143857, 0.0143429, 0.0142539, 0.0140348, 0.0137352", \ - "0.0150618, 0.0146533, 0.0145674, 0.0146852, 0.0143532, 0.0142684, 0.0136909", \ - "0.0190065, 0.0167187, 0.0162974, 0.015784, 0.0153734, 0.0146701, 0.0144522", \ - "0.0293908, 0.023885, 0.0222248, 0.020649, 0.0192397, 0.0176304, 0.0176587", \ - "0.0517091, 0.0425831, 0.0390495, 0.0352125, 0.0312138, 0.0277461, 0.0237102" \ + "0.0143634, 0.0147453, 0.0147236, 0.014659, 0.0145124, 0.0141632, 0.0138189", \ + "0.0139289, 0.0143376, 0.0145203, 0.0144581, 0.0143297, 0.0140639, 0.0137524", \ + "0.0140437, 0.0142683, 0.0143864, 0.0144763, 0.0142545, 0.014035, 0.0137346", \ + "0.0150615, 0.0146534, 0.0145675, 0.0146832, 0.0143831, 0.0142668, 0.0136919", \ + "0.0190099, 0.0167189, 0.0162974, 0.0157822, 0.0154022, 0.0146601, 0.0150526", \ + "0.0293922, 0.0238854, 0.0222264, 0.0206491, 0.0193103, 0.0176305, 0.0176597", \ + "0.0517093, 0.0425831, 0.0390498, 0.0352126, 0.031214, 0.0277462, 0.0236499" \ ); } } @@ -21965,38 +22039,38 @@ library (sg13g2_stdcell_typ_1p50V_25C) { pin (A) { direction : "input"; max_transition : 2.5074; - capacitance : 0.00296932; - rise_capacitance : 0.00294442; - rise_capacitance_range (0.00294442, 0.00294442); - fall_capacitance : 0.00299422; - fall_capacitance_range (0.00299422, 0.00299422); + capacitance : 0.00296933; + rise_capacitance : 0.00294444; + rise_capacitance_range (0.00269383, 0.00316607); + fall_capacitance : 0.00299423; + fall_capacitance_range (0.00256524, 0.00389303); } pin (B) { direction : "input"; max_transition : 2.5074; - capacitance : 0.00314805; + capacitance : 0.00314807; rise_capacitance : 0.0032448; - rise_capacitance_range (0.0032448, 0.0032448); - fall_capacitance : 0.0030513; - fall_capacitance_range (0.0030513, 0.0030513); + rise_capacitance_range (0.00276556, 0.00351608); + fall_capacitance : 0.00305134; + fall_capacitance_range (0.00272033, 0.00370033); } pin (C) { direction : "input"; max_transition : 2.5074; - capacitance : 0.0031754; + capacitance : 0.00317539; rise_capacitance : 0.00330738; - rise_capacitance_range (0.00330738, 0.00330738); - fall_capacitance : 0.00304342; - fall_capacitance_range (0.00304342, 0.00304342); + rise_capacitance_range (0.00279835, 0.00362868); + fall_capacitance : 0.00304341; + fall_capacitance_range (0.00280401, 0.00351816); } pin (D) { direction : "input"; max_transition : 2.5074; - capacitance : 0.00315706; + capacitance : 0.00315702; rise_capacitance : 0.00332659; - rise_capacitance_range (0.00332659, 0.00332659); - fall_capacitance : 0.00298753; - fall_capacitance_range (0.00298753, 0.00298753); + rise_capacitance_range (0.00280191, 0.00370321); + fall_capacitance : 0.00298745; + fall_capacitance_range (0.00283409, 0.00332981); } } cell (sg13g2_nor2_1) { @@ -22202,18 +22276,18 @@ library (sg13g2_stdcell_typ_1p50V_25C) { max_transition : 2.5074; capacitance : 0.00318838; rise_capacitance : 0.00311138; - rise_capacitance_range (0.00311138, 0.00311138); + rise_capacitance_range (0.00285491, 0.00362292); fall_capacitance : 0.00326538; - fall_capacitance_range (0.00326538, 0.00326538); + fall_capacitance_range (0.00276896, 0.00356126); } pin (B) { direction : "input"; max_transition : 2.5074; capacitance : 0.00301958; rise_capacitance : 0.00312824; - rise_capacitance_range (0.00312824, 0.00312824); + rise_capacitance_range (0.00256593, 0.00407882); fall_capacitance : 0.00291092; - fall_capacitance_range (0.00291092, 0.00291092); + fall_capacitance_range (0.00270207, 0.00313402); } } cell (sg13g2_nor2_2) { @@ -22419,18 +22493,18 @@ library (sg13g2_stdcell_typ_1p50V_25C) { max_transition : 2.5074; capacitance : 0.00611765; rise_capacitance : 0.00598792; - rise_capacitance_range (0.00598792, 0.00598792); + rise_capacitance_range (0.00539543, 0.0069966); fall_capacitance : 0.00624737; - fall_capacitance_range (0.00624737, 0.00624737); + fall_capacitance_range (0.00528395, 0.00687027); } pin (B) { direction : "input"; max_transition : 2.5074; capacitance : 0.00583902; rise_capacitance : 0.00607847; - rise_capacitance_range (0.00607847, 0.00607847); + rise_capacitance_range (0.00479686, 0.00811145); fall_capacitance : 0.00559957; - fall_capacitance_range (0.00559957, 0.00559957); + fall_capacitance_range (0.00513846, 0.00605004); } } cell (sg13g2_nor2b_1) { @@ -22636,18 +22710,18 @@ library (sg13g2_stdcell_typ_1p50V_25C) { max_transition : 2.5074; capacitance : 0.00302394; rise_capacitance : 0.00313281; - rise_capacitance_range (0.00313281, 0.00313281); + rise_capacitance_range (0.00257141, 0.0040845); fall_capacitance : 0.00291506; - fall_capacitance_range (0.00291506, 0.00291506); + fall_capacitance_range (0.00270484, 0.00313836); } pin (B_N) { direction : "input"; max_transition : 2.5074; capacitance : 0.0023981; rise_capacitance : 0.00243967; - rise_capacitance_range (0.00243967, 0.00243967); + rise_capacitance_range (0.00214597, 0.00267); fall_capacitance : 0.00235653; - fall_capacitance_range (0.00235653, 0.00235653); + fall_capacitance_range (0.0021364, 0.00255056); internal_power () { when : "A"; rise_power (passive_POWER_7x1ds1) { @@ -22882,18 +22956,18 @@ library (sg13g2_stdcell_typ_1p50V_25C) { max_transition : 2.5074; capacitance : 0.00586958; rise_capacitance : 0.00609396; - rise_capacitance_range (0.00609396, 0.00609396); + rise_capacitance_range (0.00488957, 0.00804725); fall_capacitance : 0.00564519; - fall_capacitance_range (0.00564519, 0.00564519); + fall_capacitance_range (0.00519943, 0.00613936); } pin (B_N) { direction : "input"; max_transition : 2.5074; capacitance : 0.0028232; rise_capacitance : 0.00287584; - rise_capacitance_range (0.00287584, 0.00287584); + rise_capacitance_range (0.00257671, 0.00311935); fall_capacitance : 0.00277057; - fall_capacitance_range (0.00277057, 0.00277057); + fall_capacitance_range (0.00254112, 0.00298049); internal_power () { when : "A"; rise_power (passive_POWER_7x1ds1) { @@ -23226,27 +23300,27 @@ library (sg13g2_stdcell_typ_1p50V_25C) { max_transition : 2.5074; capacitance : 0.00317088; rise_capacitance : 0.00306814; - rise_capacitance_range (0.00306814, 0.00306814); + rise_capacitance_range (0.00285541, 0.00356593); fall_capacitance : 0.00327363; - fall_capacitance_range (0.00327363, 0.00327363); + fall_capacitance_range (0.00277355, 0.00358515); } pin (B) { direction : "input"; max_transition : 2.5074; capacitance : 0.0031611; rise_capacitance : 0.00313795; - rise_capacitance_range (0.00313795, 0.00313795); + rise_capacitance_range (0.0027193, 0.00392544); fall_capacitance : 0.00318425; - fall_capacitance_range (0.00318425, 0.00318425); + fall_capacitance_range (0.00270758, 0.00342584); } pin (C) { direction : "input"; max_transition : 2.5074; capacitance : 0.00300208; rise_capacitance : 0.00313428; - rise_capacitance_range (0.00313428, 0.00313428); + rise_capacitance_range (0.00250962, 0.0043595); fall_capacitance : 0.00286988; - fall_capacitance_range (0.00286988, 0.00286988); + fall_capacitance_range (0.00267445, 0.00301178); } } cell (sg13g2_nor3_2) { @@ -23550,27 +23624,27 @@ library (sg13g2_stdcell_typ_1p50V_25C) { max_transition : 2.5074; capacitance : 0.00607396; rise_capacitance : 0.00588217; - rise_capacitance_range (0.00588217, 0.00588217); + rise_capacitance_range (0.005449, 0.00684501); fall_capacitance : 0.00626574; - fall_capacitance_range (0.00626574, 0.00626574); + fall_capacitance_range (0.00523858, 0.00691413); } pin (B) { direction : "input"; max_transition : 2.5074; capacitance : 0.00602026; rise_capacitance : 0.00599229; - rise_capacitance_range (0.00599229, 0.00599229); + rise_capacitance_range (0.00510868, 0.00755369); fall_capacitance : 0.00604824; - fall_capacitance_range (0.00604824, 0.00604824); + fall_capacitance_range (0.00510341, 0.00655045); } pin (C) { direction : "input"; max_transition : 2.5074; capacitance : 0.00577477; rise_capacitance : 0.0060558; - rise_capacitance_range (0.0060558, 0.0060558); + rise_capacitance_range (0.0047095, 0.00860004); fall_capacitance : 0.00549374; - fall_capacitance_range (0.00549374, 0.00549374); + fall_capacitance_range (0.00509324, 0.00579482); } } cell (sg13g2_nor4_1) { @@ -23996,100 +24070,100 @@ library (sg13g2_stdcell_typ_1p50V_25C) { max_transition : 2.5074; capacitance : 0.00314859; rise_capacitance : 0.00304301; - rise_capacitance_range (0.00304301, 0.00304301); + rise_capacitance_range (0.00285813, 0.00349079); fall_capacitance : 0.00325417; - fall_capacitance_range (0.00325417, 0.00325417); + fall_capacitance_range (0.00273799, 0.00359373); } pin (B) { direction : "input"; max_transition : 2.5074; capacitance : 0.00314492; rise_capacitance : 0.00310547; - rise_capacitance_range (0.00310547, 0.00310547); + rise_capacitance_range (0.00276003, 0.00376278); fall_capacitance : 0.00318437; - fall_capacitance_range (0.00318437, 0.00318437); + fall_capacitance_range (0.00268553, 0.00346616); } pin (C) { direction : "input"; max_transition : 2.5074; capacitance : 0.00310409; rise_capacitance : 0.00312012; - rise_capacitance_range (0.00312012, 0.00312012); + rise_capacitance_range (0.0026541, 0.00402766); fall_capacitance : 0.00308806; - fall_capacitance_range (0.00308806, 0.00308806); + fall_capacitance_range (0.00263417, 0.00330912); } pin (D) { direction : "input"; max_transition : 2.5074; capacitance : 0.00293132; rise_capacitance : 0.00308569; - rise_capacitance_range (0.00308569, 0.00308569); + rise_capacitance_range (0.0024745, 0.00438071); fall_capacitance : 0.00277694; - fall_capacitance_range (0.00277694, 0.00277694); + fall_capacitance_range (0.00260605, 0.00288655); } } cell (sg13g2_nor4_2) { area : 21.7728; cell_footprint : "nor4"; - cell_leakage_power : 771.791; + cell_leakage_power : 771.792; leakage_power () { - value : 751.172; + value : 751.174; when : "!A&!B&!C&!D&Y"; } leakage_power () { - value : 835.517; + value : 835.519; when : "!A&!B&!C&D&!Y"; } leakage_power () { - value : 676.853; + value : 676.854; when : "!A&!B&C&!D&!Y"; } leakage_power () { - value : 851.624; + value : 851.626; when : "!A&!B&C&D&!Y"; } leakage_power () { - value : 563.058; + value : 563.06; when : "!A&B&!C&!D&!Y"; } leakage_power () { - value : 756.974; + value : 756.975; when : "!A&B&!C&D&!Y"; } leakage_power () { - value : 727.421; + value : 727.422; when : "!A&B&C&!D&!Y"; } leakage_power () { - value : 995.744; + value : 995.745; when : "!A&B&C&D&!Y"; } leakage_power () { - value : 451.001; + value : 451.002; when : "A&!B&!C&!D&!Y"; } leakage_power () { - value : 653.609; + value : 653.611; when : "A&!B&!C&D&!Y"; } leakage_power () { - value : 635.302; + value : 635.303; when : "A&!B&C&!D&!Y"; } leakage_power () { - value : 919.389; + value : 919.39; when : "A&!B&C&D&!Y"; } leakage_power () { - value : 616.945; + value : 616.947; when : "A&B&!C&!D&!Y"; } leakage_power () { - value : 891.223; + value : 891.225; when : "A&B&!C&D&!Y"; } leakage_power () { - value : 872.891; + value : 872.893; when : "A&B&C&!D&!Y"; } leakage_power () { @@ -24109,52 +24183,52 @@ library (sg13g2_stdcell_typ_1p50V_25C) { index_1 ("0.0186, 0.0966, 0.174, 0.3294, 0.6408, 1.263, 2.5074"); index_2 ("0.001, 0.0468, 0.078, 0.1296, 0.216, 0.36, 0.6"); values ( \ - "0.0764252, 0.265824, 0.392802, 0.601905, 0.951985, 1.53521, 2.5072", \ - "0.0905567, 0.281277, 0.408721, 0.618323, 0.96914, 1.55239, 2.52468", \ - "0.0971281, 0.292532, 0.419804, 0.629695, 0.980258, 1.56422, 2.53693", \ - "0.102637, 0.308509, 0.437791, 0.647752, 0.998367, 1.58188, 2.55597", \ - "0.114459, 0.337965, 0.471353, 0.685406, 1.0372, 1.61986, 2.59146", \ - "0.143119, 0.394952, 0.537064, 0.757486, 1.1161, 1.70266, 2.66957", \ - "0.193897, 0.498213, 0.656918, 0.896226, 1.27115, 1.86816, 2.84768" \ + "0.0764119, 0.265808, 0.392772, 0.601865, 0.951931, 1.53513, 2.50832", \ + "0.0906137, 0.281278, 0.408711, 0.618289, 0.969195, 1.55246, 2.52451", \ + "0.0971208, 0.292513, 0.419775, 0.629681, 0.980222, 1.56414, 2.53617", \ + "0.102611, 0.308519, 0.437744, 0.647714, 0.998297, 1.58182, 2.55586", \ + "0.114451, 0.337945, 0.471897, 0.68541, 1.03713, 1.61944, 2.5926", \ + "0.143109, 0.394929, 0.537035, 0.757445, 1.11605, 1.7024, 2.66942", \ + "0.193885, 0.498185, 0.656886, 0.896178, 1.27131, 1.86805, 2.84752" \ ); } rise_transition (TIMING_DELAY_7x7ds1) { index_1 ("0.0186, 0.0966, 0.174, 0.3294, 0.6408, 1.263, 2.5074"); index_2 ("0.001, 0.0468, 0.078, 0.1296, 0.216, 0.36, 0.6"); values ( \ - "0.053479, 0.317644, 0.497651, 0.794752, 1.29296, 2.12281, 3.50593", \ - "0.0576022, 0.317958, 0.497721, 0.794971, 1.29402, 2.12362, 3.50801", \ - "0.0632243, 0.320357, 0.498497, 0.795755, 1.29403, 2.12396, 3.50802", \ - "0.0764305, 0.330798, 0.505451, 0.798093, 1.29472, 2.12397, 3.50803", \ - "0.109983, 0.357731, 0.529415, 0.815728, 1.30295, 2.12551, 3.51558", \ - "0.168859, 0.414504, 0.586356, 0.867005, 1.34375, 2.15001, 3.51563", \ - "0.266584, 0.528546, 0.698351, 0.979607, 1.45261, 2.2421, 3.57614" \ + "0.05341, 0.317624, 0.497621, 0.794705, 1.29352, 2.12188, 3.50602", \ + "0.057605, 0.317939, 0.497686, 0.794925, 1.29353, 2.12385, 3.50781", \ + "0.0632195, 0.320315, 0.498434, 0.795165, 1.29354, 2.12386, 3.50782", \ + "0.0764179, 0.330887, 0.505404, 0.798057, 1.29355, 2.12387, 3.50783", \ + "0.109977, 0.35771, 0.529883, 0.815633, 1.30273, 2.12729, 3.50803", \ + "0.168851, 0.414484, 0.586323, 0.866961, 1.34355, 2.1498, 3.51414", \ + "0.266575, 0.528523, 0.69832, 0.97956, 1.45246, 2.24198, 3.57594" \ ); } cell_fall (TIMING_DELAY_7x7ds1) { index_1 ("0.0186, 0.0966, 0.174, 0.3294, 0.6408, 1.263, 2.5074"); index_2 ("0.001, 0.0468, 0.078, 0.1296, 0.216, 0.36, 0.6"); values ( \ - "0.020933, 0.0624271, 0.0882337, 0.130135, 0.199672, 0.314604, 0.505945", \ - "0.0413011, 0.0986164, 0.127745, 0.171341, 0.241234, 0.356163, 0.547257", \ - "0.051573, 0.123148, 0.157346, 0.2068, 0.281187, 0.398073, 0.589475", \ - "0.0638188, 0.157361, 0.200867, 0.261148, 0.34821, 0.475321, 0.671525", \ - "0.0773674, 0.202993, 0.260561, 0.338764, 0.447971, 0.601162, 0.821886", \ - "0.088992, 0.255233, 0.334866, 0.441733, 0.584684, 0.782172, 1.05353", \ - "0.0929721, 0.30744, 0.415034, 0.562672, 0.761551, 1.02392, 1.37969" \ + "0.0209296, 0.0624258, 0.0882257, 0.130095, 0.199509, 0.31454, 0.505831", \ + "0.0413163, 0.0986134, 0.127666, 0.171349, 0.241179, 0.356125, 0.547356", \ + "0.0515669, 0.123147, 0.157328, 0.206779, 0.281156, 0.398037, 0.589351", \ + "0.0638105, 0.157343, 0.200843, 0.261121, 0.348173, 0.475275, 0.671436", \ + "0.077358, 0.202979, 0.260535, 0.338732, 0.447882, 0.601218, 0.821775", \ + "0.0889807, 0.255209, 0.334836, 0.441694, 0.58463, 0.782097, 1.05342", \ + "0.0929636, 0.307412, 0.414995, 0.562622, 0.761864, 1.02384, 1.37956" \ ); } fall_transition (TIMING_DELAY_7x7ds1) { index_1 ("0.0186, 0.0966, 0.174, 0.3294, 0.6408, 1.263, 2.5074"); index_2 ("0.001, 0.0468, 0.078, 0.1296, 0.216, 0.36, 0.6"); values ( \ - "0.0170337, 0.0670371, 0.100915, 0.156861, 0.2504, 0.406109, 0.665852", \ - "0.0334589, 0.0824315, 0.112602, 0.163867, 0.253191, 0.407034, 0.665853", \ - "0.0464898, 0.100569, 0.131531, 0.181557, 0.266354, 0.413535, 0.670393", \ - "0.0684208, 0.133231, 0.166982, 0.220014, 0.303745, 0.44265, 0.683766", \ - "0.10501, 0.189567, 0.229811, 0.287997, 0.378743, 0.520418, 0.749895", \ - "0.167489, 0.284659, 0.335652, 0.406083, 0.510159, 0.665455, 0.90667", \ - "0.277285, 0.440132, 0.511197, 0.606494, 0.732585, 0.916233, 1.18499" \ + "0.017017, 0.0669742, 0.100868, 0.156701, 0.250254, 0.406034, 0.666246", \ + "0.0334402, 0.0824242, 0.112566, 0.163882, 0.252859, 0.407168, 0.666247", \ + "0.0464867, 0.100607, 0.13154, 0.181571, 0.266342, 0.413474, 0.668901", \ + "0.0682173, 0.133232, 0.166964, 0.220002, 0.303604, 0.442543, 0.683577", \ + "0.105005, 0.189562, 0.22979, 0.287969, 0.379371, 0.52025, 0.749693", \ + "0.167483, 0.284641, 0.335629, 0.406046, 0.510109, 0.665387, 0.906539", \ + "0.277266, 0.440114, 0.51117, 0.606454, 0.733017, 0.916784, 1.18492" \ ); } } @@ -24166,52 +24240,52 @@ library (sg13g2_stdcell_typ_1p50V_25C) { index_1 ("0.0186, 0.0966, 0.174, 0.3294, 0.6408, 1.263, 2.5074"); index_2 ("0.001, 0.0468, 0.078, 0.1296, 0.216, 0.36, 0.6"); values ( \ - "0.0731181, 0.262525, 0.38933, 0.59863, 0.948678, 1.53194, 2.50518", \ - "0.0879905, 0.280062, 0.407285, 0.617015, 0.968393, 1.55117, 2.52338", \ - "0.0956487, 0.294748, 0.422015, 0.631946, 0.98254, 1.56647, 2.53869", \ - "0.105385, 0.320038, 0.449842, 0.660232, 1.01065, 1.59425, 2.56813", \ - "0.128996, 0.368013, 0.503695, 0.719242, 1.07194, 1.65435, 2.62568", \ - "0.177219, 0.453125, 0.602101, 0.831507, 1.19428, 1.78155, 2.75151", \ - "0.259708, 0.597127, 0.770798, 1.02695, 1.41517, 2.02868, 3.0115" \ + "0.0730905, 0.262507, 0.389313, 0.598594, 0.948617, 1.53186, 2.50505", \ + "0.0880373, 0.280067, 0.407422, 0.617007, 0.968347, 1.55116, 2.52323", \ + "0.0956432, 0.294731, 0.422036, 0.632186, 0.982434, 1.56639, 2.53893", \ + "0.105379, 0.320022, 0.44982, 0.660197, 1.0104, 1.59414, 2.56799", \ + "0.128988, 0.368006, 0.50367, 0.719263, 1.07186, 1.65424, 2.62637", \ + "0.177214, 0.453104, 0.602073, 0.831467, 1.19421, 1.78153, 2.75135", \ + "0.259689, 0.597098, 0.77076, 1.0269, 1.41512, 2.02858, 3.01135" \ ); } rise_transition (TIMING_DELAY_7x7ds1) { index_1 ("0.0186, 0.0966, 0.174, 0.3294, 0.6408, 1.263, 2.5074"); index_2 ("0.001, 0.0468, 0.078, 0.1296, 0.216, 0.36, 0.6"); values ( \ - "0.0534134, 0.317643, 0.497603, 0.795044, 1.29296, 2.12283, 3.50634", \ - "0.0599803, 0.318001, 0.49775, 0.795045, 1.29345, 2.12407, 3.50801", \ - "0.0680392, 0.321532, 0.499138, 0.795249, 1.29346, 2.12408, 3.50802", \ - "0.0857237, 0.335633, 0.508138, 0.799135, 1.29453, 2.12409, 3.50803", \ - "0.120598, 0.370293, 0.538713, 0.821257, 1.30512, 2.13013, 3.50804", \ - "0.174275, 0.434702, 0.604834, 0.885845, 1.35509, 2.1558, 3.51742", \ - "0.265474, 0.553373, 0.733571, 1.0171, 1.48348, 2.26647, 3.59047" \ + "0.0534026, 0.317623, 0.497586, 0.794997, 1.29363, 2.12271, 3.5062", \ + "0.0600438, 0.317997, 0.497682, 0.794998, 1.29364, 2.12385, 3.50781", \ + "0.0680343, 0.321562, 0.499103, 0.796474, 1.29365, 2.12386, 3.50782", \ + "0.0857188, 0.335624, 0.508148, 0.799089, 1.29366, 2.12387, 3.50783", \ + "0.120592, 0.37028, 0.538684, 0.82121, 1.30499, 2.13031, 3.5097", \ + "0.174291, 0.434683, 0.604807, 0.8858, 1.35472, 2.15564, 3.51719", \ + "0.265467, 0.553354, 0.733546, 1.01706, 1.48347, 2.26632, 3.59037" \ ); } cell_fall (TIMING_DELAY_7x7ds1) { index_1 ("0.0186, 0.0966, 0.174, 0.3294, 0.6408, 1.263, 2.5074"); index_2 ("0.001, 0.0468, 0.078, 0.1296, 0.216, 0.36, 0.6"); values ( \ - "0.0215743, 0.0618106, 0.0872016, 0.12873, 0.197934, 0.31304, 0.504661", \ - "0.0403699, 0.0974523, 0.126402, 0.170006, 0.239783, 0.354757, 0.546194", \ - "0.0492967, 0.121332, 0.155635, 0.20514, 0.279619, 0.396609, 0.588244", \ - "0.0591189, 0.154206, 0.198013, 0.258548, 0.346081, 0.473454, 0.670036", \ - "0.0682011, 0.197559, 0.25618, 0.335274, 0.445004, 0.599218, 0.82056", \ - "0.0704677, 0.244175, 0.325991, 0.43508, 0.579934, 0.779134, 1.05182", \ - "0.0704687, 0.283036, 0.394589, 0.547659, 0.75145, 1.01725, 1.37588" \ + "0.0215737, 0.0618245, 0.0872006, 0.128724, 0.197933, 0.313034, 0.504653", \ + "0.0403701, 0.0974784, 0.126449, 0.170013, 0.239726, 0.354759, 0.546131", \ + "0.0492957, 0.121327, 0.155633, 0.205137, 0.279616, 0.396607, 0.588142", \ + "0.0591961, 0.154204, 0.198016, 0.258545, 0.346078, 0.473491, 0.670029", \ + "0.0682006, 0.197557, 0.256178, 0.33527, 0.44524, 0.59921, 0.82061", \ + "0.0704685, 0.244173, 0.325987, 0.43516, 0.579929, 0.779126, 1.05181", \ + "0.0704695, 0.283037, 0.394588, 0.547656, 0.751444, 1.01724, 1.37586" \ ); } fall_transition (TIMING_DELAY_7x7ds1) { index_1 ("0.0186, 0.0966, 0.174, 0.3294, 0.6408, 1.263, 2.5074"); index_2 ("0.001, 0.0468, 0.078, 0.1296, 0.216, 0.36, 0.6"); values ( \ - "0.0158263, 0.0644703, 0.0982488, 0.154192, 0.248021, 0.4041, 0.664278", \ - "0.0307852, 0.0799419, 0.110135, 0.161397, 0.250838, 0.405384, 0.664329", \ - "0.0429144, 0.0978244, 0.129098, 0.179267, 0.264091, 0.411509, 0.668462", \ - "0.0631392, 0.130607, 0.164253, 0.217393, 0.301706, 0.440746, 0.682364", \ - "0.0971166, 0.185411, 0.226198, 0.285042, 0.377137, 0.518288, 0.748934", \ - "0.154697, 0.277024, 0.330982, 0.402568, 0.508529, 0.663823, 0.906471", \ - "0.25269, 0.427451, 0.502339, 0.599969, 0.729839, 0.914978, 1.18388" \ + "0.0158234, 0.0644379, 0.098247, 0.154189, 0.248019, 0.404092, 0.66445", \ + "0.0307871, 0.0799153, 0.110155, 0.161355, 0.250823, 0.405296, 0.664451", \ + "0.0429139, 0.0978198, 0.129096, 0.179265, 0.264087, 0.411575, 0.66628", \ + "0.0632426, 0.130606, 0.164237, 0.217421, 0.301703, 0.440873, 0.682351", \ + "0.0971155, 0.18541, 0.226196, 0.285042, 0.377132, 0.518279, 0.749189", \ + "0.154695, 0.277022, 0.330982, 0.402474, 0.508525, 0.663816, 0.906459", \ + "0.252686, 0.427447, 0.502334, 0.599964, 0.729833, 0.91497, 1.18386" \ ); } } @@ -24223,52 +24297,52 @@ library (sg13g2_stdcell_typ_1p50V_25C) { index_1 ("0.0186, 0.0966, 0.174, 0.3294, 0.6408, 1.263, 2.5074"); index_2 ("0.001, 0.0468, 0.078, 0.1296, 0.216, 0.36, 0.6"); values ( \ - "0.0624012, 0.25181, 0.378826, 0.587906, 0.938028, 1.52126, 2.49315", \ - "0.0771572, 0.271404, 0.398495, 0.608471, 0.959481, 1.54343, 2.51471", \ - "0.0872971, 0.291627, 0.418941, 0.628821, 0.979364, 1.56324, 2.5359", \ - "0.104671, 0.329274, 0.460101, 0.670545, 1.02091, 1.60435, 2.578", \ - "0.140216, 0.396543, 0.537654, 0.755626, 1.10911, 1.69136, 2.66414", \ - "0.201637, 0.508367, 0.669291, 0.908316, 1.2779, 1.86939, 2.8395", \ - "0.306717, 0.684198, 0.875861, 1.15438, 1.56891, 2.20409, 3.19879" \ + "0.0624003, 0.251796, 0.37881, 0.587875, 0.937974, 1.52118, 2.49306", \ + "0.077154, 0.27139, 0.398575, 0.608445, 0.959424, 1.54289, 2.51458", \ + "0.0872932, 0.291613, 0.418923, 0.62888, 0.979303, 1.56316, 2.53588", \ + "0.104666, 0.329113, 0.460068, 0.670512, 1.0209, 1.60428, 2.57778", \ + "0.14021, 0.396521, 0.537631, 0.75559, 1.10903, 1.69131, 2.66403", \ + "0.201628, 0.508347, 0.669266, 0.908278, 1.27798, 1.8694, 2.8392", \ + "0.3067, 0.684171, 0.875834, 1.15438, 1.56885, 2.20233, 3.19866" \ ); } rise_transition (TIMING_DELAY_7x7ds1) { index_1 ("0.0186, 0.0966, 0.174, 0.3294, 0.6408, 1.263, 2.5074"); index_2 ("0.001, 0.0468, 0.078, 0.1296, 0.216, 0.36, 0.6"); values ( \ - "0.0534192, 0.317939, 0.497639, 0.794752, 1.293, 2.12283, 3.50801", \ - "0.0631904, 0.318276, 0.497643, 0.794753, 1.29339, 2.12313, 3.50802", \ - "0.0733285, 0.323323, 0.499703, 0.795566, 1.2934, 2.12395, 3.50803", \ - "0.0916487, 0.341728, 0.511833, 0.80059, 1.29473, 2.12396, 3.50804", \ - "0.121933, 0.384164, 0.551022, 0.829904, 1.30885, 2.13292, 3.50887", \ - "0.171787, 0.461233, 0.634039, 0.910902, 1.37392, 2.16582, 3.51997", \ - "0.25679, 0.586903, 0.776136, 1.06858, 1.53712, 2.30957, 3.61651" \ + "0.0534119, 0.317919, 0.497609, 0.794699, 1.29293, 2.12271, 3.50573", \ + "0.0631989, 0.318274, 0.49763, 0.794709, 1.29331, 2.12401, 3.50779", \ + "0.073324, 0.323304, 0.499675, 0.796022, 1.29332, 2.12402, 3.5078", \ + "0.0916439, 0.341857, 0.511781, 0.80055, 1.2935, 2.12403, 3.50781", \ + "0.121928, 0.384196, 0.550988, 0.829743, 1.30918, 2.13547, 3.50867", \ + "0.171777, 0.461214, 0.634011, 0.910859, 1.37384, 2.16637, 3.51978", \ + "0.256778, 0.586884, 0.776129, 1.06858, 1.53706, 2.30833, 3.61628" \ ); } cell_fall (TIMING_DELAY_7x7ds1) { index_1 ("0.0186, 0.0966, 0.174, 0.3294, 0.6408, 1.263, 2.5074"); index_2 ("0.001, 0.0468, 0.078, 0.1296, 0.216, 0.36, 0.6"); values ( \ - "0.0208048, 0.0597188, 0.084754, 0.126002, 0.195, 0.30989, 0.501363", \ - "0.0369711, 0.0948781, 0.123924, 0.167389, 0.236985, 0.351901, 0.543247", \ - "0.0439675, 0.117962, 0.152554, 0.202264, 0.276812, 0.393784, 0.585356", \ - "0.0504639, 0.149574, 0.193673, 0.254954, 0.342751, 0.470543, 0.667203", \ - "0.0538475, 0.189716, 0.249886, 0.330029, 0.441052, 0.595517, 0.816794", \ - "0.0538485, 0.230322, 0.315381, 0.426805, 0.573268, 0.773832, 1.04769", \ - "0.0538495, 0.257482, 0.373944, 0.531307, 0.739588, 1.00871, 1.36957" \ + "0.0208039, 0.0597169, 0.0847537, 0.126009, 0.195008, 0.309888, 0.501505", \ + "0.03697, 0.0948779, 0.123924, 0.167389, 0.236986, 0.35188, 0.543336", \ + "0.0439678, 0.117961, 0.152554, 0.202264, 0.276812, 0.393784, 0.585284", \ + "0.0504636, 0.149573, 0.193673, 0.254954, 0.342742, 0.47047, 0.667198", \ + "0.0538477, 0.189716, 0.249886, 0.330028, 0.440991, 0.595543, 0.816792", \ + "0.0538487, 0.230323, 0.31526, 0.426806, 0.573268, 0.773833, 1.04769", \ + "0.0538497, 0.257485, 0.373947, 0.531309, 0.739595, 1.00871, 1.36957" \ ); } fall_transition (TIMING_DELAY_7x7ds1) { index_1 ("0.0186, 0.0966, 0.174, 0.3294, 0.6408, 1.263, 2.5074"); index_2 ("0.001, 0.0468, 0.078, 0.1296, 0.216, 0.36, 0.6"); values ( \ - "0.0133379, 0.0611991, 0.0948963, 0.15082, 0.244551, 0.400757, 0.661125", \ - "0.0272932, 0.0769746, 0.107273, 0.158331, 0.247486, 0.40255, 0.661126", \ - "0.0382901, 0.094683, 0.126098, 0.176202, 0.260999, 0.408312, 0.663649", \ - "0.0571368, 0.126421, 0.161293, 0.214556, 0.298675, 0.437774, 0.679033", \ - "0.0885259, 0.181095, 0.222549, 0.281942, 0.373542, 0.515491, 0.74548", \ - "0.142045, 0.270847, 0.325886, 0.398492, 0.504599, 0.661389, 0.902192", \ - "0.233753, 0.415925, 0.492839, 0.594674, 0.725773, 0.913011, 1.1806" \ + "0.0133379, 0.0611732, 0.0948962, 0.150835, 0.244738, 0.400756, 0.661197", \ + "0.0272942, 0.0769744, 0.107273, 0.158331, 0.247488, 0.4024, 0.661198", \ + "0.0382883, 0.094683, 0.126098, 0.176202, 0.260999, 0.408312, 0.666214", \ + "0.0571365, 0.126421, 0.161293, 0.214556, 0.298563, 0.437766, 0.678774", \ + "0.0885252, 0.181095, 0.222549, 0.281921, 0.373583, 0.515299, 0.74548", \ + "0.142268, 0.270846, 0.325449, 0.398491, 0.504599, 0.661389, 0.902192", \ + "0.233424, 0.415925, 0.492836, 0.594672, 0.725771, 0.913013, 1.1806" \ ); } } @@ -24280,52 +24354,52 @@ library (sg13g2_stdcell_typ_1p50V_25C) { index_1 ("0.0186, 0.0966, 0.174, 0.3294, 0.6408, 1.263, 2.5074"); index_2 ("0.001, 0.0468, 0.078, 0.1296, 0.216, 0.36, 0.6"); values ( \ - "0.0418957, 0.232937, 0.360026, 0.569628, 0.919537, 1.50289, 2.47481", \ - "0.0629948, 0.256342, 0.383552, 0.593075, 0.943751, 1.52745, 2.5009", \ - "0.0785303, 0.28347, 0.409788, 0.618834, 0.96915, 1.55321, 2.52481", \ - "0.101911, 0.333397, 0.464022, 0.672824, 1.02139, 1.60354, 2.57659", \ - "0.141647, 0.414682, 0.560381, 0.781054, 1.13336, 1.71229, 2.68278", \ - "0.208668, 0.539791, 0.710035, 0.962368, 1.34367, 1.9361, 2.90226", \ - "0.325722, 0.73272, 0.93975, 1.23918, 1.68031, 2.33861, 3.34503" \ + "0.0418952, 0.232924, 0.359909, 0.569597, 0.919482, 1.50281, 2.47467", \ + "0.0630321, 0.256328, 0.383534, 0.593096, 0.944289, 1.52738, 2.50076", \ + "0.0785274, 0.283472, 0.409803, 0.618803, 0.969086, 1.55239, 2.52462", \ + "0.101907, 0.33333, 0.46397, 0.672822, 1.02135, 1.60342, 2.57646", \ + "0.141641, 0.414668, 0.560359, 0.781019, 1.13333, 1.7122, 2.68263", \ + "0.20866, 0.539774, 0.710012, 0.962334, 1.34362, 1.93615, 2.90201", \ + "0.325726, 0.732694, 0.939721, 1.23915, 1.68011, 2.33853, 3.34454" \ ); } rise_transition (TIMING_DELAY_7x7ds1) { index_1 ("0.0186, 0.0966, 0.174, 0.3294, 0.6408, 1.263, 2.5074"); index_2 ("0.001, 0.0468, 0.078, 0.1296, 0.216, 0.36, 0.6"); values ( \ - "0.0517598, 0.317815, 0.497906, 0.795063, 1.2937, 2.12283, 3.508", \ - "0.0626133, 0.318249, 0.497907, 0.795287, 1.29371, 2.12382, 3.50801", \ - "0.0706703, 0.324937, 0.499756, 0.79635, 1.29372, 2.12383, 3.50802", \ - "0.0852513, 0.349481, 0.517304, 0.803073, 1.29385, 2.12384, 3.50803", \ - "0.113495, 0.400496, 0.568369, 0.844538, 1.31717, 2.13675, 3.50804", \ - "0.161013, 0.486271, 0.666934, 0.949308, 1.40934, 2.18767, 3.52835", \ - "0.243535, 0.626025, 0.829728, 1.13643, 1.62085, 2.38788, 3.67394" \ + "0.0517527, 0.317794, 0.497433, 0.795018, 1.29363, 2.12271, 3.5078", \ + "0.062641, 0.318231, 0.497505, 0.795019, 1.29364, 2.12374, 3.50781", \ + "0.0706663, 0.32492, 0.49979, 0.796292, 1.29365, 2.12377, 3.50782", \ + "0.0852511, 0.349451, 0.517229, 0.80278, 1.29379, 2.12378, 3.50783", \ + "0.113491, 0.400484, 0.568398, 0.844636, 1.31713, 2.13658, 3.50784", \ + "0.161008, 0.486254, 0.666907, 0.949269, 1.40927, 2.18784, 3.52745", \ + "0.243625, 0.62601, 0.829705, 1.13639, 1.61905, 2.38782, 3.67394" \ ); } cell_fall (TIMING_DELAY_7x7ds1) { index_1 ("0.0186, 0.0966, 0.174, 0.3294, 0.6408, 1.263, 2.5074"); index_2 ("0.001, 0.0468, 0.078, 0.1296, 0.216, 0.36, 0.6"); values ( \ - "0.017541, 0.0566671, 0.0815396, 0.122797, 0.191406, 0.305918, 0.496928", \ - "0.0297385, 0.0910444, 0.120539, 0.164106, 0.233542, 0.348045, 0.538837", \ - "0.0340615, 0.113163, 0.148423, 0.198536, 0.273146, 0.389917, 0.580952", \ - "0.0359899, 0.143021, 0.188349, 0.250507, 0.338665, 0.466373, 0.662799", \ - "0.0359909, 0.179688, 0.241976, 0.323448, 0.435281, 0.590235, 0.812489", \ - "0.0359919, 0.214244, 0.302391, 0.416711, 0.565632, 0.767566, 1.04175", \ - "0.0359929, 0.229363, 0.350931, 0.512918, 0.725717, 0.998696, 1.36083" \ + "0.0175408, 0.056667, 0.0815395, 0.122718, 0.191393, 0.305918, 0.496835", \ + "0.029738, 0.0910444, 0.120539, 0.164107, 0.233542, 0.34803, 0.538867", \ + "0.034061, 0.113162, 0.148423, 0.198527, 0.273146, 0.389919, 0.580949", \ + "0.0359894, 0.143021, 0.188349, 0.250506, 0.338664, 0.466373, 0.662813", \ + "0.0359904, 0.179687, 0.241976, 0.323447, 0.43528, 0.590235, 0.81249", \ + "0.0359914, 0.214317, 0.302392, 0.416711, 0.565632, 0.767566, 1.04175", \ + "0.0359924, 0.229366, 0.350934, 0.51292, 0.725718, 0.998696, 1.36083" \ ); } fall_transition (TIMING_DELAY_7x7ds1) { index_1 ("0.0186, 0.0966, 0.174, 0.3294, 0.6408, 1.263, 2.5074"); index_2 ("0.001, 0.0468, 0.078, 0.1296, 0.216, 0.36, 0.6"); values ( \ - "0.0102767, 0.0575587, 0.0915179, 0.146968, 0.240172, 0.395953, 0.65539", \ - "0.0231129, 0.0737158, 0.103833, 0.154554, 0.243148, 0.396374, 0.655391", \ - "0.0330993, 0.0911965, 0.122612, 0.172587, 0.257073, 0.403497, 0.657181", \ - "0.0504662, 0.122513, 0.157502, 0.210989, 0.294358, 0.433289, 0.673275", \ - "0.0807135, 0.177168, 0.217992, 0.278726, 0.370011, 0.511446, 0.740425", \ - "0.131732, 0.26552, 0.322165, 0.394079, 0.501775, 0.656603, 0.896988", \ - "0.219557, 0.408849, 0.48793, 0.591757, 0.723273, 0.908837, 1.17784" \ + "0.0102764, 0.0575586, 0.0915014, 0.146976, 0.240165, 0.395956, 0.655382", \ + "0.0231129, 0.0736972, 0.103833, 0.154553, 0.243148, 0.396896, 0.655383", \ + "0.0330992, 0.0911958, 0.122612, 0.172578, 0.257073, 0.403499, 0.658019", \ + "0.0504659, 0.122513, 0.157502, 0.210989, 0.294358, 0.433287, 0.673387", \ + "0.0807128, 0.177168, 0.217992, 0.278726, 0.370011, 0.511446, 0.740409", \ + "0.131727, 0.265533, 0.322164, 0.394078, 0.501774, 0.656602, 0.896986", \ + "0.219554, 0.408848, 0.487928, 0.591755, 0.723273, 0.908836, 1.17784" \ ); } } @@ -24335,26 +24409,26 @@ library (sg13g2_stdcell_typ_1p50V_25C) { index_1 ("0.0186, 0.0966, 0.174, 0.3294, 0.6408, 1.263, 2.5074"); index_2 ("0.001, 0.0468, 0.078, 0.1296, 0.216, 0.36, 0.6"); values ( \ - "0.0310843, 0.0317853, 0.0317429, 0.031606, 0.0312807, 0.0312276, 0.0309239", \ - "0.0305072, 0.0310667, 0.031205, 0.0311905, 0.0310677, 0.0305821, 0.031045", \ - "0.030569, 0.0308573, 0.0313456, 0.031013, 0.0307266, 0.0303431, 0.0309256", \ - "0.0318421, 0.0311906, 0.0311148, 0.0309748, 0.030704, 0.0301797, 0.0307084", \ - "0.038763, 0.0347134, 0.0338197, 0.0331585, 0.0319928, 0.0309539, 0.0326361", \ - "0.0586002, 0.0483855, 0.0456725, 0.0424325, 0.0394922, 0.0383634, 0.0346104", \ - "0.101659, 0.0850156, 0.078875, 0.0721384, 0.0647485, 0.0563832, 0.0517523" \ + "0.0310677, 0.0317923, 0.0317408, 0.0316123, 0.0312806, 0.0305588, 0.0312356", \ + "0.0305143, 0.0310583, 0.0311951, 0.0311862, 0.0309589, 0.0304976, 0.0310434", \ + "0.0305613, 0.0308474, 0.0313868, 0.0309077, 0.0307614, 0.0303401, 0.0305839", \ + "0.0318443, 0.0311768, 0.031233, 0.0309958, 0.030585, 0.0301884, 0.0307025", \ + "0.038759, 0.0347169, 0.0338601, 0.033242, 0.0319694, 0.0310779, 0.0312702", \ + "0.0585995, 0.0483694, 0.0456948, 0.0425017, 0.0393229, 0.0376142, 0.0343012", \ + "0.101662, 0.0850221, 0.0788748, 0.0721578, 0.0648203, 0.0565452, 0.051751" \ ); } fall_power (POWER_7x7ds1) { index_1 ("0.0186, 0.0966, 0.174, 0.3294, 0.6408, 1.263, 2.5074"); index_2 ("0.001, 0.0468, 0.078, 0.1296, 0.216, 0.36, 0.6"); values ( \ - "0.00970106, 0.00967376, 0.00947401, 0.00930649, 0.00900391, 0.00842193, 0.0073793", \ - "0.00950171, 0.00936463, 0.00916311, 0.00927199, 0.00866334, 0.00826944, 0.00705551", \ - "0.010591, 0.00981434, 0.00962226, 0.0090979, 0.00909779, 0.00850251, 0.00861105", \ - "0.0141231, 0.0114065, 0.010963, 0.0104566, 0.00949266, 0.00894518, 0.00757946", \ - "0.0224843, 0.01695, 0.0153092, 0.0139099, 0.0126484, 0.0111713, 0.00857821", \ - "0.0420436, 0.0318357, 0.0279463, 0.0244723, 0.0208011, 0.0174462, 0.0146832", \ - "0.0833983, 0.0673364, 0.0606362, 0.052815, 0.0446178, 0.0360494, 0.0286574" \ + "0.00970308, 0.00960684, 0.00946776, 0.00926201, 0.00896889, 0.00842117, 0.00771623", \ + "0.00950122, 0.00930115, 0.00913483, 0.00935959, 0.00857675, 0.00833016, 0.007071", \ + "0.0105893, 0.00984067, 0.0096346, 0.00911319, 0.00918276, 0.0085203, 0.00768053", \ + "0.0141303, 0.0114199, 0.0109512, 0.0104453, 0.00939187, 0.00879909, 0.00793181", \ + "0.0224963, 0.0169565, 0.0153068, 0.0139305, 0.012829, 0.0111564, 0.00901038", \ + "0.042049, 0.03184, 0.0279538, 0.0245183, 0.0207826, 0.0174493, 0.0146024", \ + "0.0834033, 0.0673443, 0.060644, 0.0528218, 0.0447478, 0.0363391, 0.028664" \ ); } } @@ -24364,26 +24438,26 @@ library (sg13g2_stdcell_typ_1p50V_25C) { index_1 ("0.0186, 0.0966, 0.174, 0.3294, 0.6408, 1.263, 2.5074"); index_2 ("0.001, 0.0468, 0.078, 0.1296, 0.216, 0.36, 0.6"); values ( \ - "0.0250014, 0.0257009, 0.0256981, 0.0255466, 0.025207, 0.0245377, 0.0249829", \ - "0.0244355, 0.0250034, 0.0251379, 0.0251446, 0.0249877, 0.0245111, 0.0249632", \ - "0.0245778, 0.0247755, 0.0249049, 0.0248699, 0.0246644, 0.0242492, 0.024936", \ - "0.0263156, 0.0253819, 0.0252347, 0.0250612, 0.024676, 0.0241505, 0.0246983", \ - "0.0336683, 0.0292648, 0.0281778, 0.0272871, 0.0260827, 0.0253155, 0.0252903", \ - "0.051922, 0.0423198, 0.039485, 0.0366033, 0.0336058, 0.0315557, 0.0283313", \ - "0.09043, 0.0747537, 0.0695413, 0.0633378, 0.0562225, 0.0485453, 0.0438348" \ + "0.0249997, 0.0257031, 0.025691, 0.0255496, 0.0252391, 0.024541, 0.0250533", \ + "0.0244299, 0.025004, 0.0251341, 0.025147, 0.025001, 0.0244375, 0.024964", \ + "0.0245789, 0.0248025, 0.0249084, 0.0249813, 0.0246895, 0.0242571, 0.0250232", \ + "0.0263197, 0.0253836, 0.0252832, 0.0250535, 0.0246402, 0.0241491, 0.0246767", \ + "0.0336678, 0.0292678, 0.0281431, 0.0272498, 0.0260825, 0.0253718, 0.0256703", \ + "0.0519219, 0.0423064, 0.0394787, 0.0367301, 0.033589, 0.0315532, 0.0283268", \ + "0.0904328, 0.074754, 0.069549, 0.0633371, 0.0562975, 0.0487449, 0.0439092" \ ); } fall_power (POWER_7x7ds1) { index_1 ("0.0186, 0.0966, 0.174, 0.3294, 0.6408, 1.263, 2.5074"); index_2 ("0.001, 0.0468, 0.078, 0.1296, 0.216, 0.36, 0.6"); values ( \ - "0.00912166, 0.00915913, 0.00903542, 0.00882482, 0.0085295, 0.0079197, 0.00706994", \ - "0.00887909, 0.00894111, 0.00875277, 0.00893194, 0.00834218, 0.00808937, 0.00678702", \ - "0.00989273, 0.00937951, 0.00919226, 0.00872679, 0.00883282, 0.00831419, 0.00799782", \ - "0.0132203, 0.0110692, 0.010532, 0.010051, 0.00906737, 0.00843318, 0.00718357", \ - "0.0209055, 0.0159701, 0.0144798, 0.0133191, 0.012323, 0.0107374, 0.00875815", \ - "0.038667, 0.0294551, 0.0261702, 0.023087, 0.0198907, 0.0168722, 0.01469", \ - "0.0756275, 0.0618681, 0.0556534, 0.0487487, 0.0417098, 0.0341757, 0.0272101" \ + "0.00912396, 0.00920537, 0.00903378, 0.00882067, 0.00853423, 0.00790319, 0.00710969", \ + "0.00888145, 0.00897088, 0.00876506, 0.00896345, 0.00832385, 0.00804447, 0.00676541", \ + "0.00989743, 0.00937973, 0.009251, 0.00872625, 0.00883366, 0.00828762, 0.00679832", \ + "0.0132434, 0.0110661, 0.0105503, 0.0100655, 0.00917787, 0.0086224, 0.00717557", \ + "0.0209088, 0.0159718, 0.0144781, 0.0133198, 0.0123523, 0.0107415, 0.00888326", \ + "0.038666, 0.0294555, 0.0261703, 0.0230895, 0.0198859, 0.0169226, 0.014638", \ + "0.0756291, 0.06187, 0.0556566, 0.0487517, 0.0416734, 0.0341765, 0.0271917" \ ); } } @@ -24393,26 +24467,26 @@ library (sg13g2_stdcell_typ_1p50V_25C) { index_1 ("0.0186, 0.0966, 0.174, 0.3294, 0.6408, 1.263, 2.5074"); index_2 ("0.001, 0.0468, 0.078, 0.1296, 0.216, 0.36, 0.6"); values ( \ - "0.0189927, 0.01964, 0.0196027, 0.0194578, 0.0191514, 0.0184718, 0.0189787", \ - "0.0184251, 0.0189628, 0.0190609, 0.019031, 0.0189253, 0.0183034, 0.0188792", \ - "0.0190198, 0.0188755, 0.0189793, 0.0188662, 0.0186177, 0.0182117, 0.0187069", \ - "0.0217788, 0.0199553, 0.0197097, 0.0192131, 0.0188438, 0.0182435, 0.0186851", \ - "0.0295229, 0.0245217, 0.0231761, 0.0223614, 0.0205828, 0.0198421, 0.0190792", \ - "0.0464532, 0.037452, 0.0346678, 0.0315349, 0.0280871, 0.0255252, 0.0229361", \ - "0.0817579, 0.0668029, 0.0618489, 0.0561471, 0.0496247, 0.0422552, 0.0375883" \ + "0.0189974, 0.0196418, 0.0196136, 0.0194557, 0.0191737, 0.018469, 0.0187493", \ + "0.0184179, 0.0189785, 0.0190443, 0.019045, 0.0189261, 0.018442, 0.018879", \ + "0.0190197, 0.0188733, 0.0189785, 0.0189481, 0.0186452, 0.0182105, 0.0187799", \ + "0.0217795, 0.0199462, 0.0197632, 0.0191893, 0.0187933, 0.0182466, 0.0186049", \ + "0.0295229, 0.0245331, 0.0232167, 0.0222149, 0.0206677, 0.0199975, 0.0190815", \ + "0.0464502, 0.0374515, 0.0346624, 0.0315915, 0.0280561, 0.0250575, 0.0231602", \ + "0.0817507, 0.0668045, 0.0618506, 0.05615, 0.0494937, 0.042367, 0.0378146" \ ); } fall_power (POWER_7x7ds1) { index_1 ("0.0186, 0.0966, 0.174, 0.3294, 0.6408, 1.263, 2.5074"); index_2 ("0.001, 0.0468, 0.078, 0.1296, 0.216, 0.36, 0.6"); values ( \ - "0.00738585, 0.00764765, 0.0075729, 0.00740513, 0.00708052, 0.00649643, 0.00566238", \ - "0.00747416, 0.00774394, 0.00766926, 0.007879, 0.00723232, 0.0072952, 0.00574609", \ - "0.0085118, 0.00823133, 0.00816198, 0.00770032, 0.00779195, 0.00686252, 0.00616561", \ - "0.0117359, 0.00965103, 0.00944697, 0.00905739, 0.00803986, 0.00766387, 0.0062802", \ - "0.0190523, 0.014441, 0.0131337, 0.0120755, 0.0111629, 0.00974458, 0.00737432", \ - "0.0355692, 0.0269808, 0.0240797, 0.0211581, 0.0181134, 0.0157535, 0.0130568", \ - "0.0695473, 0.05644, 0.0514372, 0.0450329, 0.0387488, 0.0318398, 0.0257401" \ + "0.00738524, 0.00767564, 0.00757074, 0.00740455, 0.00717107, 0.00649299, 0.00573035", \ + "0.00747921, 0.00775085, 0.00766907, 0.00787889, 0.00721015, 0.00730866, 0.00590818", \ + "0.00850606, 0.00823128, 0.00814951, 0.00768238, 0.0077925, 0.00680112, 0.00752258", \ + "0.0117326, 0.00965255, 0.0094367, 0.00903122, 0.00828889, 0.00770611, 0.00657816", \ + "0.0190504, 0.0144402, 0.0131337, 0.0120963, 0.0111453, 0.00973702, 0.00707522", \ + "0.0355388, 0.0269806, 0.0240393, 0.0211582, 0.0181148, 0.0157541, 0.0130568", \ + "0.069709, 0.0564405, 0.0514402, 0.0450338, 0.0387509, 0.0318402, 0.0257403" \ ); } } @@ -24422,26 +24496,26 @@ library (sg13g2_stdcell_typ_1p50V_25C) { index_1 ("0.0186, 0.0966, 0.174, 0.3294, 0.6408, 1.263, 2.5074"); index_2 ("0.001, 0.0468, 0.078, 0.1296, 0.216, 0.36, 0.6"); values ( \ - "0.0118443, 0.0130704, 0.0131545, 0.0130059, 0.0127556, 0.0120946, 0.0125854", \ - "0.0126468, 0.0125674, 0.0125397, 0.0125841, 0.0124248, 0.0119447, 0.0124743", \ - "0.0144018, 0.0130098, 0.012957, 0.0127563, 0.0124031, 0.0117729, 0.0119096", \ - "0.0182304, 0.0152055, 0.014545, 0.0136798, 0.0128732, 0.0121377, 0.0123431", \ - "0.0265549, 0.0210582, 0.0193281, 0.0177345, 0.015751, 0.0144189, 0.0129654", \ - "0.0437775, 0.0345956, 0.0316464, 0.0281778, 0.024736, 0.0217473, 0.0183421", \ - "0.0796357, 0.0648001, 0.0598217, 0.0541625, 0.0476961, 0.0402088, 0.0347234" \ + "0.0118448, 0.0130688, 0.0130803, 0.0130079, 0.0127616, 0.0121018, 0.0125866", \ + "0.0126513, 0.0125676, 0.012516, 0.0125648, 0.012406, 0.0119167, 0.0124563", \ + "0.0144001, 0.0129763, 0.0129057, 0.0127552, 0.0123893, 0.011917, 0.0122858", \ + "0.0182267, 0.0152014, 0.0144108, 0.0137929, 0.0128565, 0.0121376, 0.012301", \ + "0.0265542, 0.0210527, 0.0193375, 0.0180878, 0.0157457, 0.0144232, 0.01365", \ + "0.0437762, 0.0345989, 0.0316421, 0.0282107, 0.0248351, 0.0208107, 0.0178319", \ + "0.0796351, 0.0648016, 0.0598087, 0.0541778, 0.0475396, 0.0401056, 0.0347241" \ ); } fall_power (POWER_7x7ds1) { index_1 ("0.0186, 0.0966, 0.174, 0.3294, 0.6408, 1.263, 2.5074"); index_2 ("0.001, 0.0468, 0.078, 0.1296, 0.216, 0.36, 0.6"); values ( \ - "0.00537041, 0.00645804, 0.00665961, 0.00641108, 0.00600031, 0.00555328, 0.00461824", \ - "0.00597758, 0.00665132, 0.00663864, 0.00688171, 0.00631036, 0.00588602, 0.00497208", \ - "0.00727393, 0.00710856, 0.00713809, 0.00677746, 0.00690101, 0.00626117, 0.00495881", \ - "0.0106866, 0.00842676, 0.00830777, 0.00807508, 0.00693186, 0.00670627, 0.00538672", \ - "0.0185057, 0.0131973, 0.011834, 0.0110003, 0.0101512, 0.0088406, 0.00682737", \ - "0.0352719, 0.0254872, 0.022461, 0.0194573, 0.0170794, 0.0145117, 0.011851", \ - "0.0699956, 0.0550291, 0.0495902, 0.0429369, 0.036328, 0.0296939, 0.0243107" \ + "0.00536898, 0.0064579, 0.00664624, 0.00641413, 0.00598438, 0.00554926, 0.00456992", \ + "0.00597638, 0.00669033, 0.00663854, 0.00688198, 0.00631086, 0.00619267, 0.00499032", \ + "0.00727501, 0.00710153, 0.00714642, 0.00675079, 0.00690099, 0.00625689, 0.00544665", \ + "0.0106864, 0.00842554, 0.00830776, 0.00807475, 0.00693102, 0.00654701, 0.00558766", \ + "0.0185068, 0.0131978, 0.011833, 0.0109975, 0.0101514, 0.00884068, 0.00674276", \ + "0.0352258, 0.025489, 0.0224618, 0.0194582, 0.0170798, 0.0145122, 0.0120323", \ + "0.0699962, 0.0550287, 0.0495923, 0.042938, 0.0363298, 0.0296947, 0.0243145" \ ); } } @@ -24449,74 +24523,74 @@ library (sg13g2_stdcell_typ_1p50V_25C) { pin (A) { direction : "input"; max_transition : 2.5074; - capacitance : 0.00608392; - rise_capacitance : 0.00587507; - rise_capacitance_range (0.00587507, 0.00587507); - fall_capacitance : 0.00629277; - fall_capacitance_range (0.00629277, 0.00629277); + capacitance : 0.00608635; + rise_capacitance : 0.00587795; + rise_capacitance_range (0.00551509, 0.00678869); + fall_capacitance : 0.00629476; + fall_capacitance_range (0.00527899, 0.00698055); } pin (B) { direction : "input"; max_transition : 2.5074; - capacitance : 0.00599969; - rise_capacitance : 0.00592568; - rise_capacitance_range (0.00592568, 0.00592568); - fall_capacitance : 0.00607371; - fall_capacitance_range (0.00607371, 0.00607371); + capacitance : 0.00599976; + rise_capacitance : 0.00592575; + rise_capacitance_range (0.00523097, 0.00727796); + fall_capacitance : 0.00607377; + fall_capacitance_range (0.00510712, 0.00664521); } pin (C) { direction : "input"; max_transition : 2.5074; - capacitance : 0.00593718; + capacitance : 0.0059372; rise_capacitance : 0.00597276; - rise_capacitance_range (0.00597276, 0.00597276); - fall_capacitance : 0.0059016; - fall_capacitance_range (0.0059016, 0.0059016); + rise_capacitance_range (0.00502235, 0.00786598); + fall_capacitance : 0.00590163; + fall_capacitance_range (0.00502607, 0.00633074); } pin (D) { direction : "input"; max_transition : 2.5074; capacitance : 0.00573594; rise_capacitance : 0.00605067; - rise_capacitance_range (0.00605067, 0.00605067); - fall_capacitance : 0.00542121; - fall_capacitance_range (0.00542121, 0.00542121); + rise_capacitance_range (0.0047363, 0.00886017); + fall_capacitance : 0.00542122; + fall_capacitance_range (0.00506093, 0.00564113); } } cell (sg13g2_o21ai_1) { area : 9.072; cell_footprint : "o21ai"; - cell_leakage_power : 444.564; + cell_leakage_power : 444.577; leakage_power () { - value : 214.465; + value : 214.478; when : "!A1&!A2&!B1&Y"; } leakage_power () { - value : 383.169; + value : 383.182; when : "A1&!A2&!B1&Y"; } leakage_power () { - value : 383.176; + value : 383.188; when : "!A1&A2&!B1&Y"; } leakage_power () { - value : 525.369; + value : 525.382; when : "A1&A2&!B1&Y"; } leakage_power () { - value : 211.893; + value : 211.905; when : "!A1&!A2&B1&Y"; } leakage_power () { - value : 527.016; + value : 527.029; when : "A1&!A2&B1&!Y"; } leakage_power () { - value : 602.091; + value : 602.104; when : "!A1&A2&B1&!Y"; } leakage_power () { - value : 709.334; + value : 709.347; when : "A1&A2&B1&!Y"; } pin (Y) { @@ -24532,52 +24606,52 @@ library (sg13g2_stdcell_typ_1p50V_25C) { index_1 ("0.0186, 0.0966, 0.174, 0.3294, 0.6408, 1.263, 2.5074"); index_2 ("0.001, 0.0234, 0.039, 0.0648, 0.108, 0.18, 0.3"); values ( \ - "0.0482044, 0.157478, 0.232086, 0.355456, 0.56174, 0.904881, 1.47739", \ - "0.0660266, 0.181032, 0.256014, 0.379561, 0.585673, 0.929425, 1.50305", \ - "0.0774766, 0.201962, 0.278374, 0.402009, 0.608453, 0.952847, 1.52542", \ - "0.0937096, 0.236404, 0.318069, 0.445871, 0.653275, 0.996983, 1.5689", \ - "0.122922, 0.292629, 0.38441, 0.523762, 0.741293, 1.08886, 1.66119", \ - "0.169767, 0.378159, 0.488169, 0.649576, 0.889452, 1.25955, 1.84415", \ - "0.244566, 0.50864, 0.644176, 0.839449, 1.12326, 1.53853, 2.17336" \ + "0.0482016, 0.15736, 0.232085, 0.355457, 0.561517, 0.904892, 1.47736", \ + "0.06603, 0.181032, 0.256016, 0.379425, 0.585675, 0.929427, 1.50219", \ + "0.0774769, 0.201969, 0.278401, 0.402019, 0.608461, 0.952237, 1.52543", \ + "0.09371, 0.236405, 0.318105, 0.445873, 0.65328, 0.996984, 1.56942", \ + "0.122923, 0.292631, 0.384412, 0.523765, 0.741301, 1.08887, 1.66118", \ + "0.169768, 0.378161, 0.488171, 0.649579, 0.889465, 1.25955, 1.84416", \ + "0.244568, 0.508643, 0.644179, 0.839457, 1.12326, 1.53854, 2.17332" \ ); } rise_transition (TIMING_DELAY_7x7ds1) { index_1 ("0.0186, 0.0966, 0.174, 0.3294, 0.6408, 1.263, 2.5074"); index_2 ("0.001, 0.0234, 0.039, 0.0648, 0.108, 0.18, 0.3"); values ( \ - "0.0359333, 0.18984, 0.296712, 0.473073, 0.768478, 1.26042, 2.081", \ - "0.0447839, 0.191727, 0.297082, 0.473074, 0.768674, 1.26062, 2.08101", \ - "0.0547631, 0.199709, 0.301926, 0.474862, 0.768675, 1.26211, 2.08108", \ - "0.0732738, 0.221977, 0.320497, 0.487481, 0.774157, 1.26212, 2.08109", \ - "0.102365, 0.266115, 0.36502, 0.528342, 0.80468, 1.27784, 2.08545", \ - "0.14848, 0.34046, 0.449564, 0.617183, 0.891122, 1.34641, 2.12724", \ - "0.226562, 0.460055, 0.587521, 0.775336, 1.06539, 1.52496, 2.28097" \ + "0.0359206, 0.189813, 0.296714, 0.473076, 0.768437, 1.26052, 2.0807", \ + "0.0447852, 0.191729, 0.297083, 0.473077, 0.76867, 1.26062, 2.08091", \ + "0.0547633, 0.199781, 0.301916, 0.474865, 0.768671, 1.26132, 2.08109", \ + "0.0732742, 0.221966, 0.320638, 0.487483, 0.774181, 1.26402, 2.0811", \ + "0.102365, 0.266116, 0.365021, 0.528345, 0.804689, 1.27784, 2.0885", \ + "0.148481, 0.340461, 0.449565, 0.617185, 0.891176, 1.34645, 2.12726", \ + "0.226563, 0.460056, 0.587523, 0.775359, 1.06539, 1.52496, 2.28091" \ ); } cell_fall (TIMING_DELAY_7x7ds1) { index_1 ("0.0186, 0.0966, 0.174, 0.3294, 0.6408, 1.263, 2.5074"); index_2 ("0.001, 0.0234, 0.039, 0.0648, 0.108, 0.18, 0.3"); values ( \ - "0.0334498, 0.0998233, 0.144808, 0.219013, 0.343206, 0.549825, 0.894354", \ - "0.0482266, 0.124778, 0.170991, 0.24563, 0.369815, 0.57657, 0.921175", \ - "0.0554112, 0.143892, 0.193339, 0.270514, 0.395777, 0.602661, 0.947235", \ - "0.0631184, 0.172435, 0.229029, 0.313138, 0.444507, 0.654184, 0.999258", \ - "0.0706353, 0.212456, 0.281136, 0.379903, 0.526565, 0.750001, 1.10304", \ - "0.0760166, 0.259645, 0.350147, 0.474029, 0.64841, 0.903186, 1.28749", \ - "0.0760176, 0.306209, 0.426516, 0.590734, 0.816025, 1.12455, 1.57066" \ + "0.0334504, 0.0998301, 0.144809, 0.219015, 0.343206, 0.549829, 0.894352", \ + "0.0482266, 0.12477, 0.17099, 0.245584, 0.369796, 0.576607, 0.921084", \ + "0.0554112, 0.143892, 0.193339, 0.270514, 0.395777, 0.602656, 0.947234", \ + "0.0631183, 0.172435, 0.229029, 0.313154, 0.444507, 0.654183, 0.999256", \ + "0.0706352, 0.212456, 0.281136, 0.379903, 0.526564, 0.75, 1.10304", \ + "0.0760162, 0.259644, 0.350146, 0.474029, 0.648409, 0.903185, 1.28749", \ + "0.0760172, 0.306209, 0.426515, 0.590734, 0.816024, 1.12455, 1.57066" \ ); } fall_transition (TIMING_DELAY_7x7ds1) { index_1 ("0.0186, 0.0966, 0.174, 0.3294, 0.6408, 1.263, 2.5074"); index_2 ("0.001, 0.0234, 0.039, 0.0648, 0.108, 0.18, 0.3"); values ( \ - "0.0203891, 0.108172, 0.16917, 0.270436, 0.439806, 0.722037, 1.19238", \ - "0.030106, 0.114073, 0.172813, 0.271709, 0.440119, 0.722038, 1.19239", \ - "0.0402029, 0.125158, 0.182475, 0.278535, 0.443341, 0.722731, 1.1924", \ - "0.0589257, 0.148737, 0.205787, 0.299894, 0.458823, 0.731235, 1.19407", \ - "0.0907968, 0.194322, 0.253401, 0.347579, 0.505059, 0.767729, 1.2165", \ - "0.140987, 0.275582, 0.342588, 0.442199, 0.602138, 0.862978, 1.29933", \ - "0.224982, 0.407228, 0.492945, 0.613665, 0.787349, 1.05533, 1.49026" \ + "0.020389, 0.108175, 0.169137, 0.270436, 0.439806, 0.722036, 1.19238", \ + "0.0301061, 0.114077, 0.172813, 0.271647, 0.440079, 0.722067, 1.19239", \ + "0.0402029, 0.125163, 0.182477, 0.278534, 0.44334, 0.723185, 1.1924", \ + "0.0589256, 0.148737, 0.205786, 0.300107, 0.458822, 0.731234, 1.19407", \ + "0.0907967, 0.194322, 0.2534, 0.347579, 0.505058, 0.767728, 1.21676", \ + "0.140988, 0.275582, 0.342588, 0.442199, 0.602137, 0.862977, 1.29933", \ + "0.224983, 0.407228, 0.492944, 0.613664, 0.787349, 1.05535, 1.49026" \ ); } } @@ -24589,52 +24663,52 @@ library (sg13g2_stdcell_typ_1p50V_25C) { index_1 ("0.0186, 0.0966, 0.174, 0.3294, 0.6408, 1.263, 2.5074"); index_2 ("0.001, 0.0234, 0.039, 0.0648, 0.108, 0.18, 0.3"); values ( \ - "0.0420936, 0.1522, 0.226886, 0.350329, 0.556431, 0.899908, 1.47235", \ - "0.0652054, 0.18373, 0.258512, 0.382008, 0.588062, 0.931909, 1.5049", \ - "0.0813695, 0.21423, 0.291059, 0.414458, 0.620517, 0.964394, 1.53641", \ - "0.104896, 0.263876, 0.349433, 0.479026, 0.686544, 1.02965, 1.60152", \ - "0.143306, 0.339766, 0.441432, 0.58994, 0.813047, 1.16299, 1.73475", \ - "0.20601, 0.450992, 0.578042, 0.757144, 1.02131, 1.40631, 1.99822", \ - "0.311933, 0.62081, 0.779556, 1.00618, 1.32869, 1.78943, 2.46167" \ + "0.0420914, 0.152187, 0.227, 0.350159, 0.556435, 0.899911, 1.47225", \ + "0.0652056, 0.183702, 0.258517, 0.382026, 0.588076, 0.931883, 1.50517", \ + "0.0813698, 0.214208, 0.29106, 0.414459, 0.620602, 0.964412, 1.53641", \ + "0.104897, 0.263817, 0.349436, 0.479028, 0.686548, 1.02963, 1.60138", \ + "0.143307, 0.339769, 0.441433, 0.589943, 0.813024, 1.16306, 1.73463", \ + "0.206011, 0.450989, 0.578044, 0.757147, 1.02131, 1.40632, 1.99822", \ + "0.311935, 0.620812, 0.779559, 1.00618, 1.32869, 1.78943, 2.46168" \ ); } rise_transition (TIMING_DELAY_7x7ds1) { index_1 ("0.0186, 0.0966, 0.174, 0.3294, 0.6408, 1.263, 2.5074"); index_2 ("0.001, 0.0234, 0.039, 0.0648, 0.108, 0.18, 0.3"); values ( \ - "0.0360674, 0.189787, 0.29645, 0.473134, 0.76843, 1.26022, 2.08099", \ - "0.0496069, 0.193262, 0.297442, 0.473135, 0.768514, 1.26073, 2.081", \ - "0.0608475, 0.205848, 0.305171, 0.475635, 0.768861, 1.26074, 2.08158", \ - "0.0786302, 0.237581, 0.334184, 0.495885, 0.777458, 1.26206, 2.08159", \ - "0.106679, 0.294674, 0.397488, 0.556871, 0.825705, 1.28834, 2.09277", \ - "0.150935, 0.38354, 0.502627, 0.678542, 0.951073, 1.39524, 2.15526", \ - "0.227617, 0.519464, 0.66681, 0.875749, 1.18313, 1.64801, 2.38888" \ + "0.0360617, 0.189897, 0.296605, 0.472959, 0.768436, 1.26023, 2.08066", \ + "0.0496073, 0.193266, 0.297213, 0.472994, 0.768537, 1.26061, 2.08098", \ + "0.0608476, 0.205816, 0.305173, 0.475638, 0.768538, 1.26062, 2.08159", \ + "0.0786303, 0.237651, 0.334315, 0.495889, 0.777462, 1.26177, 2.0816", \ + "0.106679, 0.294675, 0.397489, 0.556886, 0.82566, 1.28816, 2.09768", \ + "0.150935, 0.383536, 0.502629, 0.678544, 0.951078, 1.39544, 2.15462", \ + "0.227618, 0.519464, 0.666811, 0.875751, 1.18314, 1.64802, 2.38888" \ ); } cell_fall (TIMING_DELAY_7x7ds1) { index_1 ("0.0186, 0.0966, 0.174, 0.3294, 0.6408, 1.263, 2.5074"); index_2 ("0.001, 0.0234, 0.039, 0.0648, 0.108, 0.18, 0.3"); values ( \ - "0.0281262, 0.0944963, 0.139323, 0.212977, 0.336381, 0.541804, 0.884496", \ - "0.0395623, 0.119143, 0.165362, 0.239695, 0.363247, 0.568967, 0.911928", \ - "0.0437382, 0.137409, 0.187277, 0.264442, 0.389296, 0.59518, 0.93806", \ - "0.046498, 0.1641, 0.221744, 0.306517, 0.437781, 0.646913, 0.990126", \ - "0.046499, 0.200529, 0.271659, 0.371643, 0.518843, 0.742592, 1.09426", \ - "0.0465, 0.238164, 0.333739, 0.461387, 0.638367, 0.894499, 1.27791", \ - "0.046501, 0.266978, 0.394128, 0.566031, 0.798289, 1.11147, 1.5595" \ + "0.0281289, 0.0944994, 0.139201, 0.21298, 0.336379, 0.541766, 0.884495", \ + "0.0395623, 0.11919, 0.165362, 0.239685, 0.36324, 0.569005, 0.911906", \ + "0.0437382, 0.137409, 0.187276, 0.264441, 0.389295, 0.59518, 0.937988", \ + "0.046498, 0.1641, 0.221744, 0.306516, 0.43778, 0.646912, 0.990073", \ + "0.046499, 0.200529, 0.271659, 0.371642, 0.518843, 0.742591, 1.09426", \ + "0.0465, 0.238163, 0.333739, 0.461387, 0.638367, 0.894498, 1.27791", \ + "0.046501, 0.266977, 0.394127, 0.566031, 0.798288, 1.11147, 1.55949" \ ); } fall_transition (TIMING_DELAY_7x7ds1) { index_1 ("0.0186, 0.0966, 0.174, 0.3294, 0.6408, 1.263, 2.5074"); index_2 ("0.001, 0.0234, 0.039, 0.0648, 0.108, 0.18, 0.3"); values ( \ - "0.0139754, 0.100588, 0.161463, 0.261847, 0.430127, 0.710564, 1.17806", \ - "0.0238606, 0.106903, 0.165044, 0.263227, 0.430323, 0.710575, 1.17807", \ - "0.033434, 0.118158, 0.174957, 0.270089, 0.43376, 0.713586, 1.17824", \ - "0.0513104, 0.141898, 0.198257, 0.291879, 0.449521, 0.719796, 1.18029", \ - "0.0823654, 0.188086, 0.246664, 0.339918, 0.496315, 0.756874, 1.20257", \ - "0.131624, 0.270386, 0.336009, 0.435081, 0.592734, 0.853061, 1.28574", \ - "0.213033, 0.396275, 0.488153, 0.611269, 0.780518, 1.04857, 1.47932" \ + "0.0139753, 0.100597, 0.161335, 0.261846, 0.430127, 0.71063, 1.17806", \ + "0.0238605, 0.106935, 0.165044, 0.263102, 0.430322, 0.710631, 1.17807", \ + "0.0334339, 0.118158, 0.174957, 0.270089, 0.43376, 0.713585, 1.17808", \ + "0.0513104, 0.141898, 0.198257, 0.291879, 0.449519, 0.719794, 1.18028", \ + "0.0823654, 0.188086, 0.246663, 0.339918, 0.496314, 0.756874, 1.20257", \ + "0.131624, 0.270386, 0.336008, 0.435081, 0.592734, 0.85306, 1.28574", \ + "0.213033, 0.396275, 0.488154, 0.611268, 0.780518, 1.04857, 1.47932" \ ); } } @@ -24648,52 +24722,52 @@ library (sg13g2_stdcell_typ_1p50V_25C) { index_1 ("0.0186, 0.0966, 0.174, 0.3294, 0.6408, 1.263, 2.5074"); index_2 ("0.001, 0.0234, 0.039, 0.0648, 0.108, 0.18, 0.3"); values ( \ - "0.0195807, 0.0755243, 0.112821, 0.174386, 0.277179, 0.448735, 0.734063", \ - "0.0348146, 0.111381, 0.15093, 0.212968, 0.315902, 0.487274, 0.772835", \ - "0.0438942, 0.138535, 0.18375, 0.250239, 0.354492, 0.525864, 0.81601", \ - "0.055023, 0.178036, 0.234239, 0.312781, 0.427507, 0.60349, 0.889525", \ - "0.071341, 0.232534, 0.306991, 0.406369, 0.545674, 0.744486, 1.04353", \ - "0.0937495, 0.30556, 0.403692, 0.536959, 0.716566, 0.964936, 1.31201", \ - "0.124028, 0.406116, 0.53344, 0.708926, 0.951874, 1.2775, 1.71644" \ + "0.0195794, 0.0755135, 0.112805, 0.174375, 0.277191, 0.448756, 0.734065", \ + "0.0348406, 0.11139, 0.150927, 0.212986, 0.315843, 0.487261, 0.772839", \ + "0.043894, 0.138534, 0.183748, 0.250237, 0.354491, 0.525852, 0.81139", \ + "0.0550226, 0.178035, 0.234236, 0.312779, 0.427503, 0.603456, 0.8895", \ + "0.0713405, 0.232533, 0.306989, 0.406366, 0.545671, 0.744481, 1.04358", \ + "0.0937486, 0.305559, 0.40369, 0.53696, 0.716524, 0.96493, 1.312", \ + "0.124026, 0.406113, 0.533437, 0.708922, 0.951868, 1.27749, 1.71643" \ ); } rise_transition (TIMING_DELAY_7x7ds1) { index_1 ("0.0186, 0.0966, 0.174, 0.3294, 0.6408, 1.263, 2.5074"); index_2 ("0.001, 0.0234, 0.039, 0.0648, 0.108, 0.18, 0.3"); values ( \ - "0.0133217, 0.089825, 0.144457, 0.234879, 0.386223, 0.638553, 1.05895", \ - "0.0278655, 0.100754, 0.150541, 0.236943, 0.386549, 0.638554, 1.05896", \ - "0.0386942, 0.119048, 0.166955, 0.24827, 0.39143, 0.645663, 1.0631", \ - "0.054144, 0.153435, 0.204313, 0.283562, 0.418283, 0.653535, 1.06429", \ - "0.0812728, 0.209769, 0.269533, 0.356636, 0.49115, 0.713938, 1.09975", \ - "0.127029, 0.29328, 0.373136, 0.479535, 0.631433, 0.86035, 1.23001", \ - "0.206031, 0.423976, 0.528141, 0.669461, 0.866061, 1.13077, 1.52413" \ + "0.0133211, 0.0898151, 0.14444, 0.234889, 0.386218, 0.638545, 1.05894", \ + "0.0278879, 0.100797, 0.150539, 0.237017, 0.387704, 0.638546, 1.05895", \ + "0.0386939, 0.119047, 0.166962, 0.248269, 0.391431, 0.645649, 1.05896", \ + "0.0541439, 0.153434, 0.204304, 0.28356, 0.418244, 0.653431, 1.06275", \ + "0.0812727, 0.209768, 0.269531, 0.356634, 0.491147, 0.713932, 1.09964", \ + "0.127029, 0.293278, 0.373134, 0.479528, 0.63144, 0.860344, 1.22999", \ + "0.20603, 0.423975, 0.528139, 0.669458, 0.866057, 1.13077, 1.52411" \ ); } cell_fall (TIMING_DELAY_7x7ds1) { index_1 ("0.0186, 0.0966, 0.174, 0.3294, 0.6408, 1.263, 2.5074"); index_2 ("0.001, 0.0234, 0.039, 0.0648, 0.108, 0.18, 0.3"); values ( \ - "0.0220615, 0.0888805, 0.133563, 0.207373, 0.330708, 0.536295, 0.87921", \ - "0.0340858, 0.120934, 0.167765, 0.242076, 0.365573, 0.571147, 0.91391", \ - "0.0404247, 0.144239, 0.196851, 0.275544, 0.400647, 0.606264, 0.948696", \ - "0.0484379, 0.177679, 0.240864, 0.331196, 0.46599, 0.675733, 1.01848", \ - "0.0580511, 0.22462, 0.302718, 0.413327, 0.57129, 0.803381, 1.15841", \ - "0.0677146, 0.284576, 0.386603, 0.525387, 0.72169, 0.99895, 1.40141", \ - "0.0735365, 0.354692, 0.489556, 0.673105, 0.924007, 1.27012, 1.75986" \ + "0.022062, 0.0888865, 0.133564, 0.20737, 0.330705, 0.536295, 0.879207", \ + "0.0340741, 0.120946, 0.167753, 0.242056, 0.365566, 0.571135, 0.913889", \ + "0.0404247, 0.144239, 0.19685, 0.275531, 0.400617, 0.606265, 0.948702", \ + "0.0484379, 0.177679, 0.240864, 0.331195, 0.46599, 0.675742, 1.01853", \ + "0.0580512, 0.224829, 0.302802, 0.413433, 0.571337, 0.803322, 1.15844", \ + "0.0677224, 0.284577, 0.386604, 0.525382, 0.72169, 0.99906, 1.40141", \ + "0.0735366, 0.354693, 0.489556, 0.673105, 0.924006, 1.27012, 1.75986" \ ); } fall_transition (TIMING_DELAY_7x7ds1) { index_1 ("0.0186, 0.0966, 0.174, 0.3294, 0.6408, 1.263, 2.5074"); index_2 ("0.001, 0.0234, 0.039, 0.0648, 0.108, 0.18, 0.3"); values ( \ - "0.015038, 0.10057, 0.161261, 0.26183, 0.429934, 0.710456, 1.17801", \ - "0.0280646, 0.111697, 0.167862, 0.26408, 0.430552, 0.71059, 1.17802", \ - "0.0374345, 0.128547, 0.183934, 0.276131, 0.436457, 0.712125, 1.17803", \ - "0.0529487, 0.159623, 0.2176, 0.309673, 0.462313, 0.725654, 1.18189", \ - "0.079276, 0.211662, 0.277712, 0.376059, 0.531553, 0.784773, 1.2177", \ - "0.12337, 0.299459, 0.377297, 0.490326, 0.659019, 0.923498, 1.34798", \ - "0.201105, 0.435675, 0.539487, 0.6821, 0.877769, 1.17324, 1.61937" \ + "0.0150354, 0.100571, 0.161265, 0.261829, 0.429931, 0.710455, 1.17801", \ + "0.0280531, 0.111693, 0.167883, 0.264085, 0.430487, 0.710578, 1.17802", \ + "0.0374345, 0.128546, 0.183934, 0.276077, 0.436373, 0.712081, 1.17803", \ + "0.0529487, 0.159623, 0.217921, 0.309672, 0.462313, 0.725542, 1.18201", \ + "0.0792759, 0.211789, 0.278217, 0.376052, 0.531464, 0.784717, 1.21798", \ + "0.123342, 0.299459, 0.377295, 0.49033, 0.65892, 0.923634, 1.34798", \ + "0.201108, 0.435675, 0.539486, 0.682099, 0.87777, 1.17324, 1.61937" \ ); } } @@ -24705,52 +24779,52 @@ library (sg13g2_stdcell_typ_1p50V_25C) { index_1 ("0.0186, 0.0966, 0.174, 0.3294, 0.6408, 1.263, 2.5074"); index_2 ("0.001, 0.0234, 0.039, 0.0648, 0.108, 0.18, 0.3"); values ( \ - "0.0195807, 0.0755243, 0.112821, 0.174386, 0.277179, 0.448735, 0.734063", \ - "0.0348146, 0.111381, 0.15093, 0.212968, 0.315902, 0.487274, 0.772835", \ - "0.0438942, 0.138535, 0.18375, 0.250239, 0.354492, 0.525864, 0.81601", \ - "0.055023, 0.178036, 0.234239, 0.312781, 0.427507, 0.60349, 0.889525", \ - "0.071341, 0.232534, 0.306991, 0.406369, 0.545674, 0.744486, 1.04353", \ - "0.0937495, 0.30556, 0.403692, 0.536959, 0.716566, 0.964936, 1.31201", \ - "0.124028, 0.406116, 0.53344, 0.708926, 0.951874, 1.2775, 1.71644" \ + "0.0195794, 0.0755135, 0.112805, 0.174375, 0.277191, 0.448756, 0.734065", \ + "0.0348406, 0.11139, 0.150927, 0.212986, 0.315843, 0.487261, 0.772839", \ + "0.043894, 0.138534, 0.183748, 0.250237, 0.354491, 0.525852, 0.81139", \ + "0.0550226, 0.178035, 0.234236, 0.312779, 0.427503, 0.603456, 0.8895", \ + "0.0713405, 0.232533, 0.306989, 0.406366, 0.545671, 0.744481, 1.04358", \ + "0.0937486, 0.305559, 0.40369, 0.53696, 0.716524, 0.96493, 1.312", \ + "0.124026, 0.406113, 0.533437, 0.708922, 0.951868, 1.27749, 1.71643" \ ); } rise_transition (TIMING_DELAY_7x7ds1) { index_1 ("0.0186, 0.0966, 0.174, 0.3294, 0.6408, 1.263, 2.5074"); index_2 ("0.001, 0.0234, 0.039, 0.0648, 0.108, 0.18, 0.3"); values ( \ - "0.0133217, 0.089825, 0.144457, 0.234879, 0.386223, 0.638553, 1.05895", \ - "0.0278655, 0.100754, 0.150541, 0.236943, 0.386549, 0.638554, 1.05896", \ - "0.0386942, 0.119048, 0.166955, 0.24827, 0.39143, 0.645663, 1.0631", \ - "0.054144, 0.153435, 0.204313, 0.283562, 0.418283, 0.653535, 1.06429", \ - "0.0812728, 0.209769, 0.269533, 0.356636, 0.49115, 0.713938, 1.09975", \ - "0.127029, 0.29328, 0.373136, 0.479535, 0.631433, 0.86035, 1.23001", \ - "0.206031, 0.423976, 0.528141, 0.669461, 0.866061, 1.13077, 1.52413" \ + "0.0133211, 0.0898151, 0.14444, 0.234889, 0.386218, 0.638545, 1.05894", \ + "0.0278879, 0.100797, 0.150539, 0.237017, 0.387704, 0.638546, 1.05895", \ + "0.0386939, 0.119047, 0.166962, 0.248269, 0.391431, 0.645649, 1.05896", \ + "0.0541439, 0.153434, 0.204304, 0.28356, 0.418244, 0.653431, 1.06275", \ + "0.0812727, 0.209768, 0.269531, 0.356634, 0.491147, 0.713932, 1.09964", \ + "0.127029, 0.293278, 0.373134, 0.479528, 0.63144, 0.860344, 1.22999", \ + "0.20603, 0.423975, 0.528139, 0.669458, 0.866057, 1.13077, 1.52411" \ ); } cell_fall (TIMING_DELAY_7x7ds1) { index_1 ("0.0186, 0.0966, 0.174, 0.3294, 0.6408, 1.263, 2.5074"); index_2 ("0.001, 0.0234, 0.039, 0.0648, 0.108, 0.18, 0.3"); values ( \ - "0.0220615, 0.0888805, 0.133563, 0.207373, 0.330708, 0.536295, 0.87921", \ - "0.0340858, 0.120934, 0.167765, 0.242076, 0.365573, 0.571147, 0.91391", \ - "0.0404247, 0.144239, 0.196851, 0.275544, 0.400647, 0.606264, 0.948696", \ - "0.0484379, 0.177679, 0.240864, 0.331196, 0.46599, 0.675733, 1.01848", \ - "0.0580511, 0.22462, 0.302718, 0.413327, 0.57129, 0.803381, 1.15841", \ - "0.0677146, 0.284576, 0.386603, 0.525387, 0.72169, 0.99895, 1.40141", \ - "0.0735365, 0.354692, 0.489556, 0.673105, 0.924007, 1.27012, 1.75986" \ + "0.022062, 0.0888865, 0.133564, 0.20737, 0.330705, 0.536295, 0.879207", \ + "0.0340741, 0.120946, 0.167753, 0.242056, 0.365566, 0.571135, 0.913889", \ + "0.0404247, 0.144239, 0.19685, 0.275531, 0.400617, 0.606265, 0.948702", \ + "0.0484379, 0.177679, 0.240864, 0.331195, 0.46599, 0.675742, 1.01853", \ + "0.0580512, 0.224829, 0.302802, 0.413433, 0.571337, 0.803322, 1.15844", \ + "0.0677224, 0.284577, 0.386604, 0.525382, 0.72169, 0.99906, 1.40141", \ + "0.0735366, 0.354693, 0.489556, 0.673105, 0.924006, 1.27012, 1.75986" \ ); } fall_transition (TIMING_DELAY_7x7ds1) { index_1 ("0.0186, 0.0966, 0.174, 0.3294, 0.6408, 1.263, 2.5074"); index_2 ("0.001, 0.0234, 0.039, 0.0648, 0.108, 0.18, 0.3"); values ( \ - "0.015038, 0.10057, 0.161261, 0.26183, 0.429934, 0.710456, 1.17801", \ - "0.0280646, 0.111697, 0.167862, 0.26408, 0.430552, 0.71059, 1.17802", \ - "0.0374345, 0.128547, 0.183934, 0.276131, 0.436457, 0.712125, 1.17803", \ - "0.0529487, 0.159623, 0.2176, 0.309673, 0.462313, 0.725654, 1.18189", \ - "0.079276, 0.211662, 0.277712, 0.376059, 0.531553, 0.784773, 1.2177", \ - "0.12337, 0.299459, 0.377297, 0.490326, 0.659019, 0.923498, 1.34798", \ - "0.201105, 0.435675, 0.539487, 0.6821, 0.877769, 1.17324, 1.61937" \ + "0.0150354, 0.100571, 0.161265, 0.261829, 0.429931, 0.710455, 1.17801", \ + "0.0280531, 0.111693, 0.167883, 0.264085, 0.430487, 0.710578, 1.17802", \ + "0.0374345, 0.128546, 0.183934, 0.276077, 0.436373, 0.712081, 1.17803", \ + "0.0529487, 0.159623, 0.217921, 0.309672, 0.462313, 0.725542, 1.18201", \ + "0.0792759, 0.211789, 0.278217, 0.376052, 0.531464, 0.784717, 1.21798", \ + "0.123342, 0.299459, 0.377295, 0.49033, 0.65892, 0.923634, 1.34798", \ + "0.201108, 0.435675, 0.539486, 0.682099, 0.87777, 1.17324, 1.61937" \ ); } } @@ -24760,26 +24834,26 @@ library (sg13g2_stdcell_typ_1p50V_25C) { index_1 ("0.0186, 0.0966, 0.174, 0.3294, 0.6408, 1.263, 2.5074"); index_2 ("0.001, 0.0234, 0.039, 0.0648, 0.108, 0.18, 0.3"); values ( \ - "0.0080964, 0.00822434, 0.00817335, 0.00805955, 0.00789462, 0.00755458, 0.00717928", \ - "0.00785873, 0.00799991, 0.00812426, 0.00792604, 0.00779401, 0.00747313, 0.00715716", \ - "0.00826231, 0.00809241, 0.00800906, 0.00801757, 0.00777049, 0.00761409, 0.00715393", \ - "0.00998705, 0.00891967, 0.00862852, 0.00854539, 0.00805364, 0.00764469, 0.00717581", \ - "0.0146957, 0.0119821, 0.011116, 0.0102608, 0.00978026, 0.00865718, 0.00777645", \ - "0.0249334, 0.0201795, 0.0184086, 0.016461, 0.0143393, 0.012392, 0.011515", \ - "0.0460142, 0.0391732, 0.036055, 0.0324121, 0.0282736, 0.0237694, 0.0193914" \ + "0.00809409, 0.00821523, 0.00817359, 0.00805927, 0.00789268, 0.0075606, 0.0070731", \ + "0.00786022, 0.00799914, 0.00806381, 0.00793617, 0.00779239, 0.00746986, 0.00717833", \ + "0.00826384, 0.00810053, 0.00801168, 0.00799339, 0.00777168, 0.00750857, 0.00715397", \ + "0.00998843, 0.00891949, 0.00863772, 0.00849851, 0.00816243, 0.00778819, 0.00722618", \ + "0.0146907, 0.0119829, 0.0111124, 0.0102605, 0.00978058, 0.00865665, 0.00805164", \ + "0.0249342, 0.0201796, 0.0184061, 0.016462, 0.0143842, 0.0123471, 0.0114414", \ + "0.0460162, 0.0391732, 0.0360549, 0.0324009, 0.0282736, 0.0237402, 0.01945" \ ); } fall_power (POWER_7x7ds1) { index_1 ("0.0186, 0.0966, 0.174, 0.3294, 0.6408, 1.263, 2.5074"); index_2 ("0.001, 0.0234, 0.039, 0.0648, 0.108, 0.18, 0.3"); values ( \ - "0.00749267, 0.00757194, 0.00749198, 0.0073916, 0.00723895, 0.00695594, 0.00640174", \ - "0.00719715, 0.00737524, 0.00743691, 0.00728184, 0.00712886, 0.00684279, 0.00626183", \ - "0.00757717, 0.0075333, 0.00746175, 0.00750171, 0.00724923, 0.00686381, 0.00628695", \ - "0.00912687, 0.00826168, 0.00810253, 0.00779856, 0.00766378, 0.00727547, 0.00642037", \ - "0.0133814, 0.0108259, 0.0101827, 0.00961397, 0.00897929, 0.00827106, 0.00732992", \ - "0.0230636, 0.018133, 0.0165042, 0.0147597, 0.0132556, 0.0117509, 0.00980236", \ - "0.043121, 0.0358103, 0.0326719, 0.0290074, 0.0251759, 0.0212879, 0.0177129" \ + "0.00749372, 0.00757181, 0.00748915, 0.00739187, 0.00723799, 0.00695696, 0.00640323", \ + "0.00719646, 0.00737482, 0.0074291, 0.00731804, 0.00712481, 0.00685001, 0.00632453", \ + "0.00757637, 0.00754606, 0.0074488, 0.00749928, 0.00724916, 0.00695153, 0.00628696", \ + "0.00912961, 0.00826167, 0.00810432, 0.00783754, 0.00766378, 0.0072837, 0.00642249", \ + "0.0133817, 0.0108253, 0.0101841, 0.00961364, 0.00897951, 0.00827053, 0.00776996", \ + "0.0230637, 0.0181328, 0.0165051, 0.0147601, 0.0132533, 0.011751, 0.00980431", \ + "0.0431208, 0.0358093, 0.0326718, 0.0290077, 0.0251773, 0.0212734, 0.0177205" \ ); } } @@ -24789,26 +24863,26 @@ library (sg13g2_stdcell_typ_1p50V_25C) { index_1 ("0.0186, 0.0966, 0.174, 0.3294, 0.6408, 1.263, 2.5074"); index_2 ("0.001, 0.0234, 0.039, 0.0648, 0.108, 0.18, 0.3"); values ( \ - "0.00413837, 0.00446006, 0.00443956, 0.00437227, 0.00418832, 0.00384448, 0.00342895", \ - "0.00434094, 0.00427397, 0.00441482, 0.00419719, 0.00409122, 0.0038128, 0.0034648", \ - "0.00521325, 0.00459209, 0.00442577, 0.00442448, 0.00417185, 0.00382671, 0.00336318", \ - "0.00733916, 0.00573076, 0.00534913, 0.00509774, 0.00455849, 0.00403889, 0.00363433", \ - "0.0121512, 0.00928795, 0.0082909, 0.00724519, 0.00642769, 0.00520427, 0.0046925", \ - "0.0217087, 0.0170794, 0.015334, 0.0133251, 0.0111695, 0.00906272, 0.00747019", \ - "0.0417532, 0.0351609, 0.0321076, 0.0285975, 0.0246167, 0.0201588, 0.0155075" \ + "0.00413937, 0.00447673, 0.00444723, 0.0043411, 0.00418718, 0.00384616, 0.00342608", \ + "0.00434138, 0.00431075, 0.0044027, 0.00421944, 0.0040908, 0.0037904, 0.00342579", \ + "0.00521719, 0.00459274, 0.00442332, 0.0044245, 0.00412114, 0.00380556, 0.00336229", \ + "0.00733868, 0.00574505, 0.00535144, 0.00507327, 0.00455849, 0.00399272, 0.00362151", \ + "0.0121498, 0.00928808, 0.00829065, 0.00726633, 0.00657223, 0.00518732, 0.0048694", \ + "0.0217068, 0.0170829, 0.0153321, 0.0133233, 0.0111663, 0.00905407, 0.00762331", \ + "0.0417521, 0.0351618, 0.0321073, 0.0285979, 0.0246067, 0.0201567, 0.015508" \ ); } fall_power (POWER_7x7ds1) { index_1 ("0.0186, 0.0966, 0.174, 0.3294, 0.6408, 1.263, 2.5074"); index_2 ("0.001, 0.0234, 0.039, 0.0648, 0.108, 0.18, 0.3"); values ( \ - "0.00703481, 0.00777713, 0.00780199, 0.00771057, 0.00755898, 0.007244, 0.0067235", \ - "0.0067121, 0.00747604, 0.00775689, 0.0077413, 0.00750828, 0.00728947, 0.00681279", \ - "0.00718801, 0.00752151, 0.00758485, 0.00768098, 0.00752434, 0.00752578, 0.00680385", \ - "0.00880891, 0.0080892, 0.0080466, 0.00793275, 0.00785337, 0.00750833, 0.00688948", \ - "0.0129932, 0.0104528, 0.00990866, 0.00946724, 0.00902924, 0.00839039, 0.00787673", \ - "0.0222667, 0.0171726, 0.01561, 0.0140629, 0.0126791, 0.011591, 0.00952786", \ - "0.0414193, 0.033657, 0.0306843, 0.0272938, 0.0236123, 0.0203125, 0.0172176" \ + "0.0070336, 0.00777884, 0.00777255, 0.0077107, 0.0075594, 0.00724675, 0.00672284", \ + "0.00671115, 0.00748752, 0.0077569, 0.00767436, 0.00750725, 0.00729569, 0.00681034", \ + "0.0071883, 0.00752147, 0.00758486, 0.00768152, 0.00752419, 0.00752579, 0.00675632", \ + "0.00880923, 0.00808947, 0.00804666, 0.00789577, 0.00790609, 0.0075084, 0.0069086", \ + "0.0129929, 0.0104523, 0.00990805, 0.00945923, 0.0090284, 0.00839009, 0.00787862", \ + "0.0222663, 0.0171726, 0.0156077, 0.0140663, 0.0126775, 0.0115715, 0.00952786", \ + "0.0414189, 0.0336571, 0.0306843, 0.0272939, 0.0236112, 0.0203058, 0.0172177" \ ); } } @@ -24819,26 +24893,26 @@ library (sg13g2_stdcell_typ_1p50V_25C) { index_1 ("0.0186, 0.0966, 0.174, 0.3294, 0.6408, 1.263, 2.5074"); index_2 ("0.001, 0.0234, 0.039, 0.0648, 0.108, 0.18, 0.3"); values ( \ - "0.00261013, 0.0034885, 0.00352181, 0.00347979, 0.00332188, 0.00308064, 0.00247802", \ - "0.0032219, 0.00321803, 0.0033261, 0.00355398, 0.00323299, 0.00291748, 0.00244174", \ - "0.00439541, 0.0035607, 0.00347878, 0.00364148, 0.00332812, 0.00388972, 0.00332797", \ - "0.00706955, 0.00497232, 0.00457758, 0.00405652, 0.00404463, 0.0033178, 0.0028429", \ - "0.0128473, 0.00900966, 0.00797783, 0.00693789, 0.00565757, 0.00497501, 0.00340748", \ - "0.0242564, 0.0181785, 0.0161228, 0.0139603, 0.0115782, 0.00935037, 0.00676209", \ - "0.047877, 0.0389401, 0.0354709, 0.0311691, 0.0270788, 0.0221908, 0.0175264" \ + "0.00260815, 0.00349658, 0.00350983, 0.00348068, 0.00332533, 0.00308451, 0.00248025", \ + "0.00322385, 0.00322073, 0.00335414, 0.00341769, 0.00341075, 0.00293241, 0.00244445", \ + "0.0043955, 0.00356105, 0.00347196, 0.00362859, 0.00331431, 0.00388936, 0.0024259", \ + "0.00706988, 0.00497427, 0.00457162, 0.00404778, 0.00401971, 0.00327069, 0.00267202", \ + "0.0128478, 0.0090097, 0.00797786, 0.00693821, 0.00572707, 0.00497517, 0.00347078", \ + "0.0242565, 0.018178, 0.0161233, 0.0139605, 0.0115672, 0.00942176, 0.00676082", \ + "0.0478766, 0.0389392, 0.035471, 0.0311682, 0.0270808, 0.0221845, 0.0175423" \ ); } fall_power (POWER_7x7ds1) { index_1 ("0.0186, 0.0966, 0.174, 0.3294, 0.6408, 1.263, 2.5074"); index_2 ("0.001, 0.0234, 0.039, 0.0648, 0.108, 0.18, 0.3"); values ( \ - "0.0036195, 0.00430919, 0.00431035, 0.00427398, 0.00409785, 0.00380987, 0.00338065", \ - "0.00404151, 0.00410493, 0.0043166, 0.00413823, 0.00404672, 0.00377332, 0.00329433", \ - "0.00511574, 0.00440864, 0.0043156, 0.00439613, 0.00414327, 0.00377319, 0.00331676", \ - "0.00764229, 0.00557662, 0.00523002, 0.00486392, 0.00469777, 0.00424637, 0.00343964", \ - "0.0128335, 0.00904812, 0.00811097, 0.00726721, 0.00631029, 0.00538987, 0.00465832", \ - "0.0238329, 0.0176405, 0.015626, 0.0135028, 0.0114982, 0.0094239, 0.0070779", \ - "0.0463341, 0.0373518, 0.0336886, 0.0297699, 0.0253185, 0.0209635, 0.0166741" \ + "0.00362245, 0.00431542, 0.00431045, 0.00427284, 0.0041013, 0.00381013, 0.00338075", \ + "0.00404081, 0.00410712, 0.00431578, 0.00422175, 0.00404436, 0.00377559, 0.00329199", \ + "0.00511648, 0.00441772, 0.00431556, 0.00442993, 0.00412288, 0.00378425, 0.00331618", \ + "0.00764405, 0.00557665, 0.00526211, 0.00486072, 0.00469776, 0.00405614, 0.00345889", \ + "0.0128327, 0.00906392, 0.00815848, 0.00728029, 0.00623692, 0.00538598, 0.00448847", \ + "0.0238333, 0.0176399, 0.0156258, 0.0135024, 0.01151, 0.00956113, 0.00707788", \ + "0.0463346, 0.0373496, 0.0336883, 0.0297696, 0.02532, 0.0209643, 0.0167304" \ ); } } @@ -24848,26 +24922,26 @@ library (sg13g2_stdcell_typ_1p50V_25C) { index_1 ("0.0186, 0.0966, 0.174, 0.3294, 0.6408, 1.263, 2.5074"); index_2 ("0.001, 0.0234, 0.039, 0.0648, 0.108, 0.18, 0.3"); values ( \ - "0.00261013, 0.0034885, 0.00352181, 0.00347979, 0.00332188, 0.00308064, 0.00247802", \ - "0.0032219, 0.00321803, 0.0033261, 0.00355398, 0.00323299, 0.00291748, 0.00244174", \ - "0.00439541, 0.0035607, 0.00347878, 0.00364148, 0.00332812, 0.00388972, 0.00332797", \ - "0.00706955, 0.00497232, 0.00457758, 0.00405652, 0.00404463, 0.0033178, 0.0028429", \ - "0.0128473, 0.00900966, 0.00797783, 0.00693789, 0.00565757, 0.00497501, 0.00340748", \ - "0.0242564, 0.0181785, 0.0161228, 0.0139603, 0.0115782, 0.00935037, 0.00676209", \ - "0.047877, 0.0389401, 0.0354709, 0.0311691, 0.0270788, 0.0221908, 0.0175264" \ + "0.00260815, 0.00349658, 0.00350983, 0.00348068, 0.00332533, 0.00308451, 0.00248025", \ + "0.00322385, 0.00322073, 0.00335414, 0.00341769, 0.00341075, 0.00293241, 0.00244445", \ + "0.0043955, 0.00356105, 0.00347196, 0.00362859, 0.00331431, 0.00388936, 0.0024259", \ + "0.00706988, 0.00497427, 0.00457162, 0.00404778, 0.00401971, 0.00327069, 0.00267202", \ + "0.0128478, 0.0090097, 0.00797786, 0.00693821, 0.00572707, 0.00497517, 0.00347078", \ + "0.0242565, 0.018178, 0.0161233, 0.0139605, 0.0115672, 0.00942176, 0.00676082", \ + "0.0478766, 0.0389392, 0.035471, 0.0311682, 0.0270808, 0.0221845, 0.0175423" \ ); } fall_power (POWER_7x7ds1) { index_1 ("0.0186, 0.0966, 0.174, 0.3294, 0.6408, 1.263, 2.5074"); index_2 ("0.001, 0.0234, 0.039, 0.0648, 0.108, 0.18, 0.3"); values ( \ - "0.0036195, 0.00430919, 0.00431035, 0.00427398, 0.00409785, 0.00380987, 0.00338065", \ - "0.00404151, 0.00410493, 0.0043166, 0.00413823, 0.00404672, 0.00377332, 0.00329433", \ - "0.00511574, 0.00440864, 0.0043156, 0.00439613, 0.00414327, 0.00377319, 0.00331676", \ - "0.00764229, 0.00557662, 0.00523002, 0.00486392, 0.00469777, 0.00424637, 0.00343964", \ - "0.0128335, 0.00904812, 0.00811097, 0.00726721, 0.00631029, 0.00538987, 0.00465832", \ - "0.0238329, 0.0176405, 0.015626, 0.0135028, 0.0114982, 0.0094239, 0.0070779", \ - "0.0463341, 0.0373518, 0.0336886, 0.0297699, 0.0253185, 0.0209635, 0.0166741" \ + "0.00362245, 0.00431542, 0.00431045, 0.00427284, 0.0041013, 0.00381013, 0.00338075", \ + "0.00404081, 0.00410712, 0.00431578, 0.00422175, 0.00404436, 0.00377559, 0.00329199", \ + "0.00511648, 0.00441772, 0.00431556, 0.00442993, 0.00412288, 0.00378425, 0.00331618", \ + "0.00764405, 0.00557665, 0.00526211, 0.00486072, 0.00469776, 0.00405614, 0.00345889", \ + "0.0128327, 0.00906392, 0.00815848, 0.00728029, 0.00623692, 0.00538598, 0.00448847", \ + "0.0238333, 0.0176399, 0.0156258, 0.0135024, 0.01151, 0.00956113, 0.00707788", \ + "0.0463346, 0.0373496, 0.0336883, 0.0297696, 0.02532, 0.0209643, 0.0167304" \ ); } } @@ -24876,28 +24950,28 @@ library (sg13g2_stdcell_typ_1p50V_25C) { direction : "input"; max_transition : 2.5074; capacitance : 0.00357791; - rise_capacitance : 0.00365671; - rise_capacitance_range (0.00365671, 0.00365671); - fall_capacitance : 0.00349912; - fall_capacitance_range (0.00349912, 0.00349912); + rise_capacitance : 0.00365666; + rise_capacitance_range (0.00316422, 0.00414062); + fall_capacitance : 0.00349915; + fall_capacitance_range (0.00302754, 0.00376061); } pin (A2) { direction : "input"; max_transition : 2.5074; - capacitance : 0.00349536; - rise_capacitance : 0.0037506; - rise_capacitance_range (0.0037506, 0.0037506); - fall_capacitance : 0.00324012; - fall_capacitance_range (0.00324012, 0.00324012); + capacitance : 0.00349535; + rise_capacitance : 0.00375056; + rise_capacitance_range (0.00296926, 0.00463061); + fall_capacitance : 0.00324013; + fall_capacitance_range (0.00302127, 0.00339839); } pin (B1) { direction : "input"; max_transition : 2.5074; - capacitance : 0.00332934; - rise_capacitance : 0.00339532; - rise_capacitance_range (0.00339532, 0.00339532); - fall_capacitance : 0.00326335; - fall_capacitance_range (0.00326335, 0.00326335); + capacitance : 0.00332937; + rise_capacitance : 0.00339535; + rise_capacitance_range (0.00299556, 0.00398984); + fall_capacitance : 0.00326339; + fall_capacitance_range (0.00289073, 0.00365438); } } cell (sg13g2_or2_1) { @@ -25103,18 +25177,18 @@ library (sg13g2_stdcell_typ_1p50V_25C) { max_transition : 2.5074; capacitance : 0.00261599; rise_capacitance : 0.00258839; - rise_capacitance_range (0.00258839, 0.00258839); + rise_capacitance_range (0.00234135, 0.00280398); fall_capacitance : 0.00264359; - fall_capacitance_range (0.00264359, 0.00264359); + fall_capacitance_range (0.00226736, 0.0028264); } pin (B) { direction : "input"; max_transition : 2.5074; capacitance : 0.00242906; rise_capacitance : 0.00254596; - rise_capacitance_range (0.00254596, 0.00254596); + rise_capacitance_range (0.00209253, 0.0029158); fall_capacitance : 0.00231216; - fall_capacitance_range (0.00231216, 0.00231216); + fall_capacitance_range (0.0021234, 0.00242598); } } cell (sg13g2_or2_2) { @@ -25320,18 +25394,18 @@ library (sg13g2_stdcell_typ_1p50V_25C) { max_transition : 2.5074; capacitance : 0.00259471; rise_capacitance : 0.00255927; - rise_capacitance_range (0.00255927, 0.00255927); + rise_capacitance_range (0.00235093, 0.00275632); fall_capacitance : 0.00263015; - fall_capacitance_range (0.00263015, 0.00263015); + fall_capacitance_range (0.00226643, 0.00280498); } pin (B) { direction : "input"; max_transition : 2.5074; capacitance : 0.00239868; rise_capacitance : 0.00250105; - rise_capacitance_range (0.00250105, 0.00250105); + rise_capacitance_range (0.00214513, 0.00281753); fall_capacitance : 0.0022963; - fall_capacitance_range (0.0022963, 0.0022963); + fall_capacitance_range (0.00213448, 0.00240167); } } cell (sg13g2_or3_1) { @@ -25639,27 +25713,27 @@ library (sg13g2_stdcell_typ_1p50V_25C) { max_transition : 2.5074; capacitance : 0.00275872; rise_capacitance : 0.00272235; - rise_capacitance_range (0.00272235, 0.00272235); + rise_capacitance_range (0.00250046, 0.00291729); fall_capacitance : 0.00279508; - fall_capacitance_range (0.00279508, 0.00279508); + fall_capacitance_range (0.00233496, 0.00305861); } pin (B) { direction : "input"; max_transition : 2.5074; capacitance : 0.0026816; rise_capacitance : 0.00273112; - rise_capacitance_range (0.00273112, 0.00273112); + rise_capacitance_range (0.00233365, 0.0030513); fall_capacitance : 0.00263208; - fall_capacitance_range (0.00263208, 0.00263208); + fall_capacitance_range (0.00220319, 0.00283489); } pin (C) { direction : "input"; max_transition : 2.5074; capacitance : 0.00254454; rise_capacitance : 0.00272854; - rise_capacitance_range (0.00272854, 0.00272854); + rise_capacitance_range (0.00218192, 0.00318219); fall_capacitance : 0.00236053; - fall_capacitance_range (0.00236053, 0.00236053); + fall_capacitance_range (0.00216693, 0.00246921); } } cell (sg13g2_or3_2) { @@ -25967,27 +26041,27 @@ library (sg13g2_stdcell_typ_1p50V_25C) { max_transition : 2.5074; capacitance : 0.00274355; rise_capacitance : 0.00270269; - rise_capacitance_range (0.00270269, 0.00270269); + rise_capacitance_range (0.00250504, 0.00289222); fall_capacitance : 0.00278441; - fall_capacitance_range (0.00278441, 0.00278441); + fall_capacitance_range (0.00233473, 0.00303545); } pin (B) { direction : "input"; max_transition : 2.5074; capacitance : 0.00266594; rise_capacitance : 0.00270573; - rise_capacitance_range (0.00270573, 0.00270573); + rise_capacitance_range (0.00235668, 0.0029999); fall_capacitance : 0.00262615; - fall_capacitance_range (0.00262615, 0.00262615); + fall_capacitance_range (0.00220971, 0.00282317); } pin (C) { direction : "input"; max_transition : 2.5074; capacitance : 0.00252112; rise_capacitance : 0.00269164; - rise_capacitance_range (0.00269164, 0.00269164); + rise_capacitance_range (0.00225221, 0.00309322); fall_capacitance : 0.0023506; - fall_capacitance_range (0.0023506, 0.0023506); + fall_capacitance_range (0.00218211, 0.0024529); } } cell (sg13g2_or4_1) { @@ -26413,36 +26487,36 @@ library (sg13g2_stdcell_typ_1p50V_25C) { max_transition : 2.5074; capacitance : 0.00275334; rise_capacitance : 0.00271284; - rise_capacitance_range (0.00271284, 0.00271284); + rise_capacitance_range (0.00251009, 0.00290753); fall_capacitance : 0.00279383; - fall_capacitance_range (0.00279383, 0.00279383); + fall_capacitance_range (0.00233905, 0.00308524); } pin (B) { direction : "input"; max_transition : 2.5074; capacitance : 0.00265212; rise_capacitance : 0.002682; - rise_capacitance_range (0.002682, 0.002682); + rise_capacitance_range (0.00232861, 0.00298887); fall_capacitance : 0.00262223; - fall_capacitance_range (0.00262223, 0.00262223); + fall_capacitance_range (0.00219694, 0.00286739); } pin (C) { direction : "input"; max_transition : 2.5074; capacitance : 0.00262243; rise_capacitance : 0.00270976; - rise_capacitance_range (0.00270976, 0.00270976); + rise_capacitance_range (0.00225329, 0.00312242); fall_capacitance : 0.00253511; - fall_capacitance_range (0.00253511, 0.00253511); + fall_capacitance_range (0.00213714, 0.00272286); } pin (D) { direction : "input"; max_transition : 2.5074; capacitance : 0.00252963; rise_capacitance : 0.00274189; - rise_capacitance_range (0.00274189, 0.00274189); + rise_capacitance_range (0.00217581, 0.00328909); fall_capacitance : 0.00231738; - fall_capacitance_range (0.00231738, 0.00231738); + fall_capacitance_range (0.00215305, 0.00239841); } } cell (sg13g2_or4_2) { @@ -26868,41 +26942,41 @@ library (sg13g2_stdcell_typ_1p50V_25C) { max_transition : 2.5074; capacitance : 0.00272698; rise_capacitance : 0.00268079; - rise_capacitance_range (0.00268079, 0.00268079); + rise_capacitance_range (0.00249673, 0.00286948); fall_capacitance : 0.00277317; - fall_capacitance_range (0.00277317, 0.00277317); + fall_capacitance_range (0.00232652, 0.00305424); } pin (B) { direction : "input"; max_transition : 2.5074; capacitance : 0.00264251; rise_capacitance : 0.00266377; - rise_capacitance_range (0.00266377, 0.00266377); + rise_capacitance_range (0.00234085, 0.0029548); fall_capacitance : 0.00262124; - fall_capacitance_range (0.00262124, 0.00262124); + fall_capacitance_range (0.00220334, 0.00286101); } pin (C) { direction : "input"; max_transition : 2.5074; capacitance : 0.00261; rise_capacitance : 0.00268484; - rise_capacitance_range (0.00268484, 0.00268484); + rise_capacitance_range (0.00228136, 0.00306138); fall_capacitance : 0.00253517; - fall_capacitance_range (0.00253517, 0.00253517); + fall_capacitance_range (0.00214564, 0.00271986); } pin (D) { direction : "input"; max_transition : 2.5074; capacitance : 0.00250581; rise_capacitance : 0.00269943; - rise_capacitance_range (0.00269943, 0.00269943); + rise_capacitance_range (0.00224215, 0.00316928); fall_capacitance : 0.0023122; - fall_capacitance_range (0.0023122, 0.0023122); + fall_capacitance_range (0.0021705, 0.00239091); } } cell (sg13g2_sdfbbp_1) { area : 63.504; - cell_footprint : "sdfrrs"; + cell_footprint : "sdfbbp"; cell_leakage_power : 2271.16; dont_touch : true; dont_use : true; @@ -26998,6 +27072,7 @@ library (sg13g2_stdcell_typ_1p50V_25C) { timing () { related_pin : "CLK"; sdf_cond : "SCE == 1'b1"; + sdf_edges : start_edge; timing_sense : non_unate; timing_type : rising_edge; when : "SCE"; @@ -27056,6 +27131,7 @@ library (sg13g2_stdcell_typ_1p50V_25C) { } timing () { related_pin : "CLK"; + sdf_edges : start_edge; timing_sense : non_unate; timing_type : rising_edge; cell_rise (TIMING_DELAY_7x7ds1) { @@ -27113,6 +27189,7 @@ library (sg13g2_stdcell_typ_1p50V_25C) { } timing () { related_pin : "RESET_B"; + sdf_edges : start_edge; timing_sense : positive_unate; timing_type : clear; cell_fall (TIMING_DELAY_7x7ds1) { @@ -27144,6 +27221,7 @@ library (sg13g2_stdcell_typ_1p50V_25C) { } timing () { related_pin : "SET_B"; + sdf_edges : start_edge; timing_sense : negative_unate; timing_type : preset; cell_rise (TIMING_DELAY_7x7ds1) { @@ -27283,6 +27361,7 @@ library (sg13g2_stdcell_typ_1p50V_25C) { timing () { related_pin : "CLK"; sdf_cond : "SCE == 1'b1"; + sdf_edges : start_edge; timing_sense : non_unate; timing_type : rising_edge; when : "SCE"; @@ -27341,6 +27420,7 @@ library (sg13g2_stdcell_typ_1p50V_25C) { } timing () { related_pin : "CLK"; + sdf_edges : start_edge; timing_sense : non_unate; timing_type : rising_edge; cell_rise (TIMING_DELAY_7x7ds1) { @@ -27398,6 +27478,7 @@ library (sg13g2_stdcell_typ_1p50V_25C) { } timing () { related_pin : "RESET_B"; + sdf_edges : start_edge; timing_sense : negative_unate; timing_type : preset; cell_rise (TIMING_DELAY_7x7ds1) { @@ -27429,6 +27510,7 @@ library (sg13g2_stdcell_typ_1p50V_25C) { } timing () { related_pin : "SET_B"; + sdf_edges : start_edge; timing_sense : positive_unate; timing_type : clear; cell_fall (TIMING_DELAY_7x7ds1) { @@ -27566,9 +27648,9 @@ library (sg13g2_stdcell_typ_1p50V_25C) { max_transition : 2.5074; capacitance : 0.00318356; rise_capacitance : 0.0032381; - rise_capacitance_range (0.0032381, 0.0032381); + rise_capacitance_range (0.00290199, 0.00352991); fall_capacitance : 0.00311539; - fall_capacitance_range (0.00311539, 0.00311539); + fall_capacitance_range (0.00286997, 0.00333001); timing () { related_pin : "CLK"; timing_type : min_pulse_width; @@ -27724,11 +27806,12 @@ library (sg13g2_stdcell_typ_1p50V_25C) { max_transition : 2.5074; capacitance : 0.00205374; rise_capacitance : 0.00209591; - rise_capacitance_range (0.00209591, 0.00209591); + rise_capacitance_range (0.00186368, 0.00227597); fall_capacitance : 0.00201157; - fall_capacitance_range (0.00201157, 0.00201157); + fall_capacitance_range (0.00184773, 0.00212189); timing () { related_pin : "CLK"; + sdf_edges : both_edges; timing_type : hold_rising; rise_constraint (CONSTRAINT_4x4) { index_1 ("0.0186, 0.51636, 1.263, 2.5074"); @@ -27753,6 +27836,7 @@ library (sg13g2_stdcell_typ_1p50V_25C) { } timing () { related_pin : "CLK"; + sdf_edges : both_edges; timing_type : setup_rising; rise_constraint (CONSTRAINT_4x4) { index_1 ("0.0186, 0.51636, 1.263, 2.5074"); @@ -27827,9 +27911,10 @@ library (sg13g2_stdcell_typ_1p50V_25C) { rise_capacitance : 0.00182283; rise_capacitance_range (0.00182283, 0.00182283); fall_capacitance : 0.00182283; - fall_capacitance_range (0.00182283, 0.00182283); + fall_capacitance_range (0.00169751, 0.00194161); timing () { related_pin : "CLK"; + sdf_edges : both_edges; timing_type : recovery_rising; rise_constraint (CONSTRAINT_4x4) { index_1 ("0.0186, 0.51636, 1.263, 2.5074"); @@ -27844,6 +27929,7 @@ library (sg13g2_stdcell_typ_1p50V_25C) { } timing () { related_pin : "CLK"; + sdf_edges : both_edges; timing_type : removal_rising; rise_constraint (CONSTRAINT_4x4) { index_1 ("0.0186, 0.51636, 1.263, 2.5074"); @@ -27873,11 +27959,12 @@ library (sg13g2_stdcell_typ_1p50V_25C) { max_transition : 2.5074; capacitance : 0.00209765; rise_capacitance : 0.00211829; - rise_capacitance_range (0.00211829, 0.00211829); + rise_capacitance_range (0.00183839, 0.00227626); fall_capacitance : 0.00207702; - fall_capacitance_range (0.00207702, 0.00207702); + fall_capacitance_range (0.00182124, 0.00221475); timing () { related_pin : "CLK"; + sdf_edges : both_edges; timing_type : hold_rising; rise_constraint (CONSTRAINT_4x4) { index_1 ("0.0186, 0.51636, 1.263, 2.5074"); @@ -27902,6 +27989,7 @@ library (sg13g2_stdcell_typ_1p50V_25C) { } timing () { related_pin : "CLK"; + sdf_edges : both_edges; timing_type : setup_rising; rise_constraint (CONSTRAINT_4x4) { index_1 ("0.0186, 0.51636, 1.263, 2.5074"); @@ -27975,11 +28063,12 @@ library (sg13g2_stdcell_typ_1p50V_25C) { max_transition : 2.5074; capacitance : 0.00371184; rise_capacitance : 0.00409177; - rise_capacitance_range (0.00409177, 0.00409177); + rise_capacitance_range (0.00398238, 0.00470254); fall_capacitance : 0.0033319; - fall_capacitance_range (0.0033319, 0.0033319); + fall_capacitance_range (0.0033319, 0.00439715); timing () { related_pin : "CLK"; + sdf_edges : both_edges; timing_type : hold_rising; rise_constraint (CONSTRAINT_4x4) { index_1 ("0.0186, 0.51636, 1.263, 2.5074"); @@ -28004,6 +28093,7 @@ library (sg13g2_stdcell_typ_1p50V_25C) { } timing () { related_pin : "CLK"; + sdf_edges : both_edges; timing_type : setup_rising; rise_constraint (CONSTRAINT_4x4) { index_1 ("0.0186, 0.51636, 1.263, 2.5074"); @@ -28108,9 +28198,10 @@ library (sg13g2_stdcell_typ_1p50V_25C) { rise_capacitance : 0.00548776; rise_capacitance_range (0.00548776, 0.00548776); fall_capacitance : 0.00548776; - fall_capacitance_range (0.00548776, 0.00548776); + fall_capacitance_range (0.00510742, 0.00582042); timing () { related_pin : "CLK"; + sdf_edges : both_edges; timing_type : recovery_rising; rise_constraint (CONSTRAINT_4x4) { index_1 ("0.0186, 0.51636, 1.263, 2.5074"); @@ -28125,6 +28216,7 @@ library (sg13g2_stdcell_typ_1p50V_25C) { } timing () { related_pin : "CLK"; + sdf_edges : both_edges; timing_type : removal_rising; rise_constraint (CONSTRAINT_4x4) { index_1 ("0.0186, 0.51636, 1.263, 2.5074"); @@ -28139,6 +28231,7 @@ library (sg13g2_stdcell_typ_1p50V_25C) { } timing () { related_pin : "RESET_B"; + sdf_edges : both_edges; timing_type : non_seq_hold_rising; rise_constraint (CONSTRAINT_4x4) { index_1 ("0.0186, 0.51636, 1.263, 2.5074"); @@ -28153,6 +28246,7 @@ library (sg13g2_stdcell_typ_1p50V_25C) { } timing () { related_pin : "RESET_B"; + sdf_edges : both_edges; timing_type : non_seq_setup_rising; rise_constraint (CONSTRAINT_4x4) { index_1 ("0.0186, 0.51636, 1.263, 2.5074"); @@ -28177,12 +28271,12 @@ library (sg13g2_stdcell_typ_1p50V_25C) { } } ff (IQ,IQN) { - clear : "RESET_B'"; + clear : "!RESET_B"; clear_preset_var1 : "H"; clear_preset_var2 : "L"; clocked_on : "CLK"; - next_state : "(SCE*SCD)+(SCE'*D)"; - preset : "SET_B'"; + next_state : "(SCE*SCD)+(!SCE*D)"; + preset : "!SET_B"; } test_cell () { pin (Q) { @@ -28216,12 +28310,12 @@ library (sg13g2_stdcell_typ_1p50V_25C) { direction : input; } ff (IQ,IQN) { - clear : "RESET_B'"; + clear : "!RESET_B"; clear_preset_var1 : H; clear_preset_var2 : L; clocked_on : "CLK"; next_state : "D"; - preset : "SET_B'"; + preset : "!SET_B"; } } } @@ -28250,7 +28344,7 @@ library (sg13g2_stdcell_typ_1p50V_25C) { when : "CLK&!D&RESET_B&!SCD&!SCE&Q&!Q_N"; } leakage_power () { - value : 2388.64; + value : 2388.63; when : "!CLK&D&RESET_B&!SCD&!SCE&!Q&Q_N"; } leakage_power () { @@ -28278,11 +28372,11 @@ library (sg13g2_stdcell_typ_1p50V_25C) { when : "!CLK&!D&RESET_B&SCD&SCE&!Q&Q_N"; } leakage_power () { - value : 2514.25; + value : 2514.26; when : "!CLK&!D&RESET_B&SCD&SCE&Q&!Q_N"; } leakage_power () { - value : 2309.13; + value : 2309.12; when : "CLK&!D&RESET_B&!SCD&SCE&!Q&Q_N"; } leakage_power () { @@ -28305,6 +28399,7 @@ library (sg13g2_stdcell_typ_1p50V_25C) { timing () { related_pin : "CLK"; sdf_cond : "SCE == 1'b1"; + sdf_edges : start_edge; timing_sense : non_unate; timing_type : rising_edge; when : "SCE"; @@ -28312,33 +28407,33 @@ library (sg13g2_stdcell_typ_1p50V_25C) { index_1 ("0.0186, 0.0966, 0.174, 0.3294, 0.6408, 1.263, 2.5074"); index_2 ("0.001, 0.0234, 0.039, 0.0648, 0.108, 0.18, 0.3"); values ( \ - "0.127397, 0.170107, 0.201077, 0.252298, 0.33826, 0.481398, 0.720278", \ + "0.127397, 0.170054, 0.201007, 0.252298, 0.338283, 0.481396, 0.720278", \ "0.152274, 0.194989, 0.225954, 0.27727, 0.363161, 0.506429, 0.745402", \ "0.167498, 0.210232, 0.241236, 0.292506, 0.378382, 0.521612, 0.760325", \ "0.189715, 0.232354, 0.263315, 0.314573, 0.40054, 0.543694, 0.782352", \ "0.22028, 0.262723, 0.29359, 0.344841, 0.430753, 0.573961, 0.812628", \ "0.261469, 0.30337, 0.334203, 0.385388, 0.471339, 0.614441, 0.853247", \ - "0.31234, 0.353333, 0.384013, 0.435166, 0.521102, 0.664279, 0.902997" \ + "0.312396, 0.353333, 0.384013, 0.435166, 0.521102, 0.664246, 0.903037" \ ); } rise_transition (TIMING_DELAY_7x7ds1) { index_1 ("0.0186, 0.0966, 0.174, 0.3294, 0.6408, 1.263, 2.5074"); index_2 ("0.001, 0.0234, 0.039, 0.0648, 0.108, 0.18, 0.3"); values ( \ - "0.0148423, 0.0758629, 0.121731, 0.197883, 0.32559, 0.538399, 0.893083", \ - "0.014883, 0.0758639, 0.121777, 0.197933, 0.325981, 0.538418, 0.893471", \ - "0.0148948, 0.0758649, 0.121778, 0.197934, 0.325982, 0.538419, 0.893472", \ - "0.0149345, 0.0758659, 0.121779, 0.197936, 0.325983, 0.53842, 0.893473", \ - "0.01507, 0.075872, 0.12178, 0.197937, 0.325984, 0.538421, 0.893474", \ - "0.015471, 0.075922, 0.121786, 0.197938, 0.325985, 0.538422, 0.893475", \ - "0.016445, 0.076042, 0.121872, 0.197978, 0.325986, 0.538423, 0.893476" \ + "0.0148448, 0.0758549, 0.121794, 0.197883, 0.32559, 0.538398, 0.893083", \ + "0.014883, 0.0758559, 0.121795, 0.197933, 0.325981, 0.538418, 0.893471", \ + "0.0148948, 0.0758569, 0.121796, 0.197934, 0.325982, 0.538419, 0.893472", \ + "0.0149345, 0.0758579, 0.121797, 0.197936, 0.325983, 0.53842, 0.893473", \ + "0.01507, 0.075872, 0.121798, 0.197937, 0.325984, 0.538421, 0.893474", \ + "0.015471, 0.075922, 0.121799, 0.197938, 0.325985, 0.538422, 0.893475", \ + "0.016373, 0.076042, 0.121872, 0.197978, 0.325986, 0.538423, 0.893476" \ ); } cell_fall (TIMING_DELAY_7x7ds1) { index_1 ("0.0186, 0.0966, 0.174, 0.3294, 0.6408, 1.263, 2.5074"); index_2 ("0.001, 0.0234, 0.039, 0.0648, 0.108, 0.18, 0.3"); values ( \ - "0.115901, 0.153747, 0.17868, 0.219804, 0.288576, 0.403104, 0.594185", \ + "0.115901, 0.153747, 0.178699, 0.219809, 0.288551, 0.403105, 0.594151", \ "0.140497, 0.178376, 0.203276, 0.244392, 0.313134, 0.427697, 0.618609", \ "0.155129, 0.192937, 0.217889, 0.259017, 0.327717, 0.442265, 0.633187", \ "0.175416, 0.213214, 0.238175, 0.279281, 0.348077, 0.462593, 0.653441", \ @@ -28351,9 +28446,9 @@ library (sg13g2_stdcell_typ_1p50V_25C) { index_1 ("0.0186, 0.0966, 0.174, 0.3294, 0.6408, 1.263, 2.5074"); index_2 ("0.001, 0.0234, 0.039, 0.0648, 0.108, 0.18, 0.3"); values ( \ - "0.0116624, 0.056873, 0.090039, 0.145511, 0.238739, 0.394186, 0.653322", \ - "0.0116634, 0.056874, 0.09004, 0.145516, 0.23874, 0.394585, 0.653688", \ - "0.0116644, 0.056875, 0.0900411, 0.145517, 0.238741, 0.394586, 0.653689", \ + "0.0116624, 0.056873, 0.090017, 0.145511, 0.238736, 0.394186, 0.653323", \ + "0.0116634, 0.056874, 0.0900347, 0.145516, 0.238737, 0.394585, 0.653688", \ + "0.0116644, 0.056875, 0.0900411, 0.145517, 0.238738, 0.394586, 0.653689", \ "0.0116647, 0.056876, 0.0900421, 0.145522, 0.23875, 0.394587, 0.65369", \ "0.0116657, 0.056877, 0.0900431, 0.145535, 0.238751, 0.394588, 0.653691", \ "0.0116667, 0.056878, 0.090076, 0.145536, 0.238752, 0.394589, 0.653692", \ @@ -28363,39 +28458,40 @@ library (sg13g2_stdcell_typ_1p50V_25C) { } timing () { related_pin : "CLK"; + sdf_edges : start_edge; timing_sense : non_unate; timing_type : rising_edge; cell_rise (TIMING_DELAY_7x7ds1) { index_1 ("0.0186, 0.0966, 0.174, 0.3294, 0.6408, 1.263, 2.5074"); index_2 ("0.001, 0.0234, 0.039, 0.0648, 0.108, 0.18, 0.3"); values ( \ - "0.127397, 0.170107, 0.201077, 0.252298, 0.33826, 0.481398, 0.720278", \ + "0.127397, 0.170054, 0.201007, 0.252298, 0.338283, 0.481396, 0.720278", \ "0.152274, 0.194989, 0.225954, 0.27727, 0.363161, 0.506429, 0.745402", \ "0.167498, 0.210232, 0.241236, 0.292506, 0.378382, 0.521612, 0.760325", \ "0.189715, 0.232354, 0.263315, 0.314573, 0.40054, 0.543694, 0.782352", \ "0.22028, 0.262723, 0.29359, 0.344841, 0.430753, 0.573961, 0.812628", \ "0.261469, 0.30337, 0.334203, 0.385388, 0.471339, 0.614441, 0.853247", \ - "0.31234, 0.353333, 0.384013, 0.435166, 0.521102, 0.664279, 0.902997" \ + "0.312396, 0.353333, 0.384013, 0.435166, 0.521102, 0.664246, 0.903037" \ ); } rise_transition (TIMING_DELAY_7x7ds1) { index_1 ("0.0186, 0.0966, 0.174, 0.3294, 0.6408, 1.263, 2.5074"); index_2 ("0.001, 0.0234, 0.039, 0.0648, 0.108, 0.18, 0.3"); values ( \ - "0.0148423, 0.0758629, 0.121731, 0.197883, 0.32559, 0.538399, 0.893083", \ - "0.014883, 0.0758639, 0.121777, 0.197933, 0.325981, 0.538418, 0.893471", \ - "0.0148948, 0.0758649, 0.121778, 0.197934, 0.325982, 0.538419, 0.893472", \ - "0.0149345, 0.0758659, 0.121779, 0.197936, 0.325983, 0.53842, 0.893473", \ - "0.01507, 0.075872, 0.12178, 0.197937, 0.325984, 0.538421, 0.893474", \ - "0.015471, 0.075922, 0.121786, 0.197938, 0.325985, 0.538422, 0.893475", \ - "0.016445, 0.076042, 0.121872, 0.197978, 0.325986, 0.538423, 0.893476" \ + "0.0148448, 0.0758549, 0.121794, 0.197883, 0.32559, 0.538398, 0.893083", \ + "0.014883, 0.0758559, 0.121795, 0.197933, 0.325981, 0.538418, 0.893471", \ + "0.0148948, 0.0758569, 0.121796, 0.197934, 0.325982, 0.538419, 0.893472", \ + "0.0149345, 0.0758579, 0.121797, 0.197936, 0.325983, 0.53842, 0.893473", \ + "0.01507, 0.075872, 0.121798, 0.197937, 0.325984, 0.538421, 0.893474", \ + "0.015471, 0.075922, 0.121799, 0.197938, 0.325985, 0.538422, 0.893475", \ + "0.016373, 0.076042, 0.121872, 0.197978, 0.325986, 0.538423, 0.893476" \ ); } cell_fall (TIMING_DELAY_7x7ds1) { index_1 ("0.0186, 0.0966, 0.174, 0.3294, 0.6408, 1.263, 2.5074"); index_2 ("0.001, 0.0234, 0.039, 0.0648, 0.108, 0.18, 0.3"); values ( \ - "0.115901, 0.153747, 0.17868, 0.219804, 0.288576, 0.403104, 0.594185", \ + "0.115901, 0.153747, 0.178699, 0.219809, 0.288551, 0.403105, 0.594151", \ "0.140497, 0.178376, 0.203276, 0.244392, 0.313134, 0.427697, 0.618609", \ "0.155129, 0.192937, 0.217889, 0.259017, 0.327717, 0.442265, 0.633187", \ "0.175416, 0.213214, 0.238175, 0.279281, 0.348077, 0.462593, 0.653441", \ @@ -28408,9 +28504,9 @@ library (sg13g2_stdcell_typ_1p50V_25C) { index_1 ("0.0186, 0.0966, 0.174, 0.3294, 0.6408, 1.263, 2.5074"); index_2 ("0.001, 0.0234, 0.039, 0.0648, 0.108, 0.18, 0.3"); values ( \ - "0.0116624, 0.056873, 0.090039, 0.145511, 0.238739, 0.394186, 0.653322", \ - "0.0116634, 0.056874, 0.09004, 0.145516, 0.23874, 0.394585, 0.653688", \ - "0.0116644, 0.056875, 0.0900411, 0.145517, 0.238741, 0.394586, 0.653689", \ + "0.0116624, 0.056873, 0.090017, 0.145511, 0.238736, 0.394186, 0.653323", \ + "0.0116634, 0.056874, 0.0900347, 0.145516, 0.238737, 0.394585, 0.653688", \ + "0.0116644, 0.056875, 0.0900411, 0.145517, 0.238738, 0.394586, 0.653689", \ "0.0116647, 0.056876, 0.0900421, 0.145522, 0.23875, 0.394587, 0.65369", \ "0.0116657, 0.056877, 0.0900431, 0.145535, 0.238751, 0.394588, 0.653691", \ "0.0116667, 0.056878, 0.090076, 0.145536, 0.238752, 0.394589, 0.653692", \ @@ -28420,16 +28516,17 @@ library (sg13g2_stdcell_typ_1p50V_25C) { } timing () { related_pin : "RESET_B"; + sdf_edges : start_edge; timing_sense : positive_unate; timing_type : clear; cell_fall (TIMING_DELAY_7x7ds1) { index_1 ("0.0186, 0.0966, 0.174, 0.3294, 0.6408, 1.263, 2.5074"); index_2 ("0.001, 0.0234, 0.039, 0.0648, 0.108, 0.18, 0.3"); values ( \ - "0.163481, 0.201392, 0.225808, 0.264132, 0.323991, 0.418086, 0.569452", \ + "0.163481, 0.201392, 0.225808, 0.264132, 0.323991, 0.418086, 0.56941", \ "0.198233, 0.23618, 0.261055, 0.30103, 0.364387, 0.462868, 0.61838", \ "0.224621, 0.262447, 0.287417, 0.328028, 0.393426, 0.495398, 0.654678", \ - "0.263477, 0.301359, 0.326395, 0.367272, 0.434699, 0.541701, 0.708089", \ + "0.263477, 0.301359, 0.326331, 0.367272, 0.434699, 0.541701, 0.708089", \ "0.319983, 0.357728, 0.382737, 0.423695, 0.492324, 0.604343, 0.781062", \ "0.398775, 0.436594, 0.461207, 0.50274, 0.571447, 0.685699, 0.872088", \ "0.515354, 0.552375, 0.577576, 0.61861, 0.686675, 0.802107, 0.992553" \ @@ -28439,11 +28536,11 @@ library (sg13g2_stdcell_typ_1p50V_25C) { index_1 ("0.0186, 0.0966, 0.174, 0.3294, 0.6408, 1.263, 2.5074"); index_2 ("0.001, 0.0234, 0.039, 0.0648, 0.108, 0.18, 0.3"); values ( \ - "0.0115899, 0.0567331, 0.0899633, 0.145437, 0.238644, 0.394071, 0.65317", \ - "0.011593, 0.0567341, 0.0899643, 0.145471, 0.239222, 0.394072, 0.653192", \ - "0.0116069, 0.0567364, 0.0899653, 0.145472, 0.239223, 0.3941, 0.653193", \ - "0.0116758, 0.0567474, 0.0899663, 0.145481, 0.239224, 0.394173, 0.653194", \ - "0.0117628, 0.0567774, 0.0899673, 0.145482, 0.239225, 0.394174, 0.653195", \ + "0.0115899, 0.0567331, 0.0899634, 0.145438, 0.238644, 0.394071, 0.653169", \ + "0.011593, 0.0567341, 0.0899644, 0.145471, 0.239222, 0.394072, 0.653192", \ + "0.0116069, 0.0567364, 0.0899654, 0.145472, 0.239223, 0.3941, 0.653193", \ + "0.0116758, 0.0567474, 0.0899664, 0.145481, 0.239224, 0.394173, 0.653194", \ + "0.0117628, 0.0567774, 0.0899674, 0.145482, 0.239225, 0.394174, 0.653195", \ "0.011882, 0.056807, 0.089976, 0.145483, 0.239226, 0.394175, 0.653196", \ "0.012031, 0.056862, 0.09002, 0.145484, 0.239227, 0.394176, 0.653197" \ ); @@ -28456,24 +28553,24 @@ library (sg13g2_stdcell_typ_1p50V_25C) { index_1 ("0.0186, 0.0966, 0.174, 0.3294, 0.6408, 1.263, 2.5074"); index_2 ("0.001, 0.0234, 0.039, 0.0648, 0.108, 0.18, 0.3"); values ( \ - "0.04858, 0.0741052, 0.0917454, 0.120754, 0.169307, 0.249911, 0.384246", \ + "0.0485823, 0.0740816, 0.0917743, 0.120752, 0.169313, 0.249911, 0.384246", \ "0.0487574, 0.0742632, 0.0921057, 0.121131, 0.169672, 0.250088, 0.384715", \ "0.0497506, 0.0751328, 0.092773, 0.121965, 0.170396, 0.250987, 0.385439", \ "0.0525107, 0.0778509, 0.0956087, 0.124647, 0.173188, 0.254495, 0.388313", \ "0.0593146, 0.0844252, 0.102076, 0.13123, 0.179914, 0.260505, 0.395686", \ - "0.0734082, 0.098118, 0.115675, 0.144911, 0.193593, 0.274521, 0.409218", \ - "0.10282, 0.12676, 0.14428, 0.173432, 0.221903, 0.303037, 0.437909" \ + "0.0734082, 0.098118, 0.115675, 0.14491, 0.193593, 0.274521, 0.409218", \ + "0.102746, 0.12676, 0.14428, 0.173432, 0.221903, 0.303056, 0.437808" \ ); } fall_power (POWER_7x7ds1) { index_1 ("0.0186, 0.0966, 0.174, 0.3294, 0.6408, 1.263, 2.5074"); index_2 ("0.001, 0.0234, 0.039, 0.0648, 0.108, 0.18, 0.3"); values ( \ - "0.0485504, 0.0744397, 0.0919775, 0.120829, 0.169025, 0.2491, 0.38254", \ + "0.0485504, 0.0744399, 0.0919887, 0.120829, 0.168974, 0.249101, 0.382527", \ "0.0489769, 0.0748347, 0.0925307, 0.121936, 0.16945, 0.249733, 0.383197", \ "0.0500509, 0.0760037, 0.0935842, 0.122305, 0.171765, 0.250529, 0.384178", \ "0.0530434, 0.0789278, 0.0966728, 0.125817, 0.173523, 0.254478, 0.38786", \ - "0.0593549, 0.0851402, 0.102937, 0.131903, 0.180463, 0.261211, 0.394217", \ + "0.0593549, 0.0851403, 0.102936, 0.131903, 0.180463, 0.261211, 0.394217", \ "0.0729982, 0.0987517, 0.11644, 0.145274, 0.194186, 0.275257, 0.410217", \ "0.100863, 0.126462, 0.14395, 0.172893, 0.221642, 0.302119, 0.436778" \ ); @@ -28485,24 +28582,24 @@ library (sg13g2_stdcell_typ_1p50V_25C) { index_1 ("0.0186, 0.0966, 0.174, 0.3294, 0.6408, 1.263, 2.5074"); index_2 ("0.001, 0.0234, 0.039, 0.0648, 0.108, 0.18, 0.3"); values ( \ - "0.04858, 0.0741052, 0.0917454, 0.120754, 0.169307, 0.249911, 0.384246", \ + "0.0485823, 0.0740816, 0.0917743, 0.120752, 0.169313, 0.249911, 0.384246", \ "0.0487574, 0.0742632, 0.0921057, 0.121131, 0.169672, 0.250088, 0.384715", \ "0.0497506, 0.0751328, 0.092773, 0.121965, 0.170396, 0.250987, 0.385439", \ "0.0525107, 0.0778509, 0.0956087, 0.124647, 0.173188, 0.254495, 0.388313", \ "0.0593146, 0.0844252, 0.102076, 0.13123, 0.179914, 0.260505, 0.395686", \ - "0.0734082, 0.098118, 0.115675, 0.144911, 0.193593, 0.274521, 0.409218", \ - "0.10282, 0.12676, 0.14428, 0.173432, 0.221903, 0.303037, 0.437909" \ + "0.0734082, 0.098118, 0.115675, 0.14491, 0.193593, 0.274521, 0.409218", \ + "0.102746, 0.12676, 0.14428, 0.173432, 0.221903, 0.303056, 0.437808" \ ); } fall_power (POWER_7x7ds1) { index_1 ("0.0186, 0.0966, 0.174, 0.3294, 0.6408, 1.263, 2.5074"); index_2 ("0.001, 0.0234, 0.039, 0.0648, 0.108, 0.18, 0.3"); values ( \ - "0.0485504, 0.0744397, 0.0919775, 0.120829, 0.169025, 0.2491, 0.38254", \ + "0.0485504, 0.0744399, 0.0919887, 0.120829, 0.168974, 0.249101, 0.382527", \ "0.0489769, 0.0748347, 0.0925307, 0.121936, 0.16945, 0.249733, 0.383197", \ "0.0500509, 0.0760037, 0.0935842, 0.122305, 0.171765, 0.250529, 0.384178", \ "0.0530434, 0.0789278, 0.0966728, 0.125817, 0.173523, 0.254478, 0.38786", \ - "0.0593549, 0.0851402, 0.102937, 0.131903, 0.180463, 0.261211, 0.394217", \ + "0.0593549, 0.0851403, 0.102936, 0.131903, 0.180463, 0.261211, 0.394217", \ "0.0729982, 0.0987517, 0.11644, 0.145274, 0.194186, 0.275257, 0.410217", \ "0.100863, 0.126462, 0.14395, 0.172893, 0.221642, 0.302119, 0.436778" \ ); @@ -28519,10 +28616,10 @@ library (sg13g2_stdcell_typ_1p50V_25C) { index_1 ("0.0186, 0.0966, 0.174, 0.3294, 0.6408, 1.263, 2.5074"); index_2 ("0.001, 0.0234, 0.039, 0.0648, 0.108, 0.18, 0.3"); values ( \ - "0.0512824, 0.0831021, 0.104507, 0.138267, 0.191503, 0.275871, 0.412483", \ + "0.0512824, 0.0831021, 0.104507, 0.138233, 0.191503, 0.275871, 0.412459", \ "0.0512817, 0.0831641, 0.105367, 0.13989, 0.195921, 0.283226, 0.422968", \ "0.0523619, 0.08403, 0.105817, 0.141597, 0.200064, 0.288941, 0.431302", \ - "0.0552989, 0.0870237, 0.108952, 0.14465, 0.203507, 0.299608, 0.445132", \ + "0.0552989, 0.0870237, 0.108924, 0.14465, 0.203507, 0.299608, 0.445132", \ "0.0624527, 0.0937928, 0.115459, 0.151709, 0.211756, 0.309135, 0.466342", \ "0.0763062, 0.107834, 0.129415, 0.164975, 0.225468, 0.325933, 0.489566", \ "0.104143, 0.135264, 0.156157, 0.191694, 0.252234, 0.351478, 0.518606" \ @@ -28538,6 +28635,7 @@ library (sg13g2_stdcell_typ_1p50V_25C) { timing () { related_pin : "CLK"; sdf_cond : "SCE == 1'b1"; + sdf_edges : start_edge; timing_sense : non_unate; timing_type : rising_edge; when : "SCE"; @@ -28545,8 +28643,8 @@ library (sg13g2_stdcell_typ_1p50V_25C) { index_1 ("0.0186, 0.0966, 0.174, 0.3294, 0.6408, 1.263, 2.5074"); index_2 ("0.001, 0.0234, 0.039, 0.0648, 0.108, 0.18, 0.3"); values ( \ - "0.0898093, 0.147794, 0.179813, 0.231227, 0.316769, 0.459036, 0.69577", \ - "0.114433, 0.172386, 0.204366, 0.255763, 0.341282, 0.483512, 0.721469", \ + "0.0898093, 0.147795, 0.179838, 0.231249, 0.31677, 0.459038, 0.695825", \ + "0.114359, 0.172386, 0.204366, 0.255763, 0.341282, 0.483512, 0.721469", \ "0.129035, 0.187012, 0.219001, 0.270424, 0.355924, 0.498105, 0.734931", \ "0.149327, 0.20725, 0.239267, 0.290673, 0.376157, 0.51833, 0.7551", \ "0.176554, 0.234351, 0.266346, 0.317762, 0.403264, 0.545507, 0.782277", \ @@ -28558,9 +28656,9 @@ library (sg13g2_stdcell_typ_1p50V_25C) { index_1 ("0.0186, 0.0966, 0.174, 0.3294, 0.6408, 1.263, 2.5074"); index_2 ("0.001, 0.0234, 0.039, 0.0648, 0.108, 0.18, 0.3"); values ( \ - "0.0179157, 0.0814898, 0.12474, 0.198576, 0.324828, 0.536335, 0.889199", \ - "0.0179167, 0.0814935, 0.124769, 0.198617, 0.326135, 0.53641, 0.890408", \ - "0.0179177, 0.0815091, 0.12477, 0.198618, 0.326136, 0.536475, 0.890409", \ + "0.0179157, 0.0814901, 0.124749, 0.198621, 0.324827, 0.536334, 0.889199", \ + "0.0179167, 0.0814935, 0.124769, 0.198622, 0.326135, 0.53641, 0.890408", \ + "0.0179177, 0.0815091, 0.12477, 0.198623, 0.326136, 0.536475, 0.890409", \ "0.0179187, 0.0815348, 0.124771, 0.198634, 0.326137, 0.536476, 0.89041", \ "0.0179197, 0.0815358, 0.124772, 0.198635, 0.326138, 0.536477, 0.890411", \ "0.0179207, 0.0815368, 0.124773, 0.198636, 0.326139, 0.536478, 0.890412", \ @@ -28571,39 +28669,40 @@ library (sg13g2_stdcell_typ_1p50V_25C) { index_1 ("0.0186, 0.0966, 0.174, 0.3294, 0.6408, 1.263, 2.5074"); index_2 ("0.001, 0.0234, 0.039, 0.0648, 0.108, 0.18, 0.3"); values ( \ - "0.0958255, 0.158837, 0.188023, 0.231885, 0.301945, 0.417372, 0.609362", \ - "0.120673, 0.183688, 0.212907, 0.256671, 0.326804, 0.442219, 0.634292", \ - "0.135993, 0.198963, 0.228172, 0.271975, 0.342066, 0.457488, 0.649558", \ - "0.157832, 0.220802, 0.25006, 0.293917, 0.364, 0.479443, 0.67142", \ - "0.188531, 0.251785, 0.28107, 0.325019, 0.395111, 0.510563, 0.702543", \ - "0.227736, 0.292361, 0.321811, 0.365818, 0.436003, 0.551459, 0.743501", \ - "0.275976, 0.343985, 0.373794, 0.418047, 0.488305, 0.603815, 0.79591" \ + "0.095818, 0.158834, 0.188077, 0.231881, 0.301981, 0.417359, 0.609348", \ + "0.120666, 0.183676, 0.212909, 0.256662, 0.326795, 0.44221, 0.634284", \ + "0.135867, 0.198869, 0.228086, 0.2719, 0.341992, 0.457425, 0.649508", \ + "0.158022, 0.220996, 0.250258, 0.294119, 0.364204, 0.479645, 0.671593", \ + "0.188227, 0.251462, 0.280788, 0.324707, 0.394818, 0.51027, 0.702243", \ + "0.228242, 0.29283, 0.322275, 0.366287, 0.436424, 0.551945, 0.743966", \ + "0.276625, 0.344585, 0.374395, 0.418645, 0.488937, 0.604513, 0.796555" \ ); } fall_transition (TIMING_DELAY_7x7ds1) { index_1 ("0.0186, 0.0966, 0.174, 0.3294, 0.6408, 1.263, 2.5074"); index_2 ("0.001, 0.0234, 0.039, 0.0648, 0.108, 0.18, 0.3"); values ( \ - "0.022013, 0.0740785, 0.10367, 0.154866, 0.244865, 0.399116, 0.658982", \ - "0.022014, 0.074157, 0.103753, 0.154951, 0.244866, 0.399117, 0.65904", \ - "0.0220523, 0.0742681, 0.103754, 0.154952, 0.244867, 0.39913, 0.65905", \ - "0.0223522, 0.0742691, 0.10382, 0.154953, 0.244868, 0.399131, 0.659051", \ - "0.0233828, 0.0747065, 0.104073, 0.155084, 0.245007, 0.399132, 0.659055", \ - "0.025939, 0.075947, 0.104884, 0.155481, 0.24527, 0.399279, 0.659056", \ - "0.030109, 0.078946, 0.106756, 0.156668, 0.245856, 0.399841, 0.659363" \ + "0.022014, 0.0740791, 0.103677, 0.154867, 0.244865, 0.399116, 0.659032", \ + "0.022015, 0.074157, 0.103678, 0.154942, 0.244866, 0.399117, 0.659041", \ + "0.0220509, 0.0742532, 0.103679, 0.154943, 0.244867, 0.399287, 0.659054", \ + "0.0223495, 0.0742821, 0.103818, 0.154944, 0.244868, 0.399288, 0.659055", \ + "0.0233876, 0.0747071, 0.104107, 0.155152, 0.245001, 0.399289, 0.659056", \ + "0.025904, 0.075927, 0.104869, 0.155476, 0.245176, 0.39929, 0.659057", \ + "0.03011, 0.078853, 0.106771, 0.156668, 0.24585, 0.399552, 0.659112" \ ); } } timing () { related_pin : "CLK"; + sdf_edges : start_edge; timing_sense : non_unate; timing_type : rising_edge; cell_rise (TIMING_DELAY_7x7ds1) { index_1 ("0.0186, 0.0966, 0.174, 0.3294, 0.6408, 1.263, 2.5074"); index_2 ("0.001, 0.0234, 0.039, 0.0648, 0.108, 0.18, 0.3"); values ( \ - "0.0898093, 0.147794, 0.179813, 0.231227, 0.316769, 0.459036, 0.69577", \ - "0.114433, 0.172386, 0.204366, 0.255763, 0.341282, 0.483512, 0.721469", \ + "0.0898093, 0.147795, 0.179838, 0.231249, 0.31677, 0.459038, 0.695825", \ + "0.114359, 0.172386, 0.204366, 0.255763, 0.341282, 0.483512, 0.721469", \ "0.129035, 0.187012, 0.219001, 0.270424, 0.355924, 0.498105, 0.734931", \ "0.149327, 0.20725, 0.239267, 0.290673, 0.376157, 0.51833, 0.7551", \ "0.176554, 0.234351, 0.266346, 0.317762, 0.403264, 0.545507, 0.782277", \ @@ -28615,9 +28714,9 @@ library (sg13g2_stdcell_typ_1p50V_25C) { index_1 ("0.0186, 0.0966, 0.174, 0.3294, 0.6408, 1.263, 2.5074"); index_2 ("0.001, 0.0234, 0.039, 0.0648, 0.108, 0.18, 0.3"); values ( \ - "0.0179157, 0.0814898, 0.12474, 0.198576, 0.324828, 0.536335, 0.889199", \ - "0.0179167, 0.0814935, 0.124769, 0.198617, 0.326135, 0.53641, 0.890408", \ - "0.0179177, 0.0815091, 0.12477, 0.198618, 0.326136, 0.536475, 0.890409", \ + "0.0179157, 0.0814901, 0.124749, 0.198621, 0.324827, 0.536334, 0.889199", \ + "0.0179167, 0.0814935, 0.124769, 0.198622, 0.326135, 0.53641, 0.890408", \ + "0.0179177, 0.0815091, 0.12477, 0.198623, 0.326136, 0.536475, 0.890409", \ "0.0179187, 0.0815348, 0.124771, 0.198634, 0.326137, 0.536476, 0.89041", \ "0.0179197, 0.0815358, 0.124772, 0.198635, 0.326138, 0.536477, 0.890411", \ "0.0179207, 0.0815368, 0.124773, 0.198636, 0.326139, 0.536478, 0.890412", \ @@ -28628,54 +28727,55 @@ library (sg13g2_stdcell_typ_1p50V_25C) { index_1 ("0.0186, 0.0966, 0.174, 0.3294, 0.6408, 1.263, 2.5074"); index_2 ("0.001, 0.0234, 0.039, 0.0648, 0.108, 0.18, 0.3"); values ( \ - "0.0958255, 0.158837, 0.188023, 0.231885, 0.301945, 0.417372, 0.609362", \ - "0.120673, 0.183688, 0.212907, 0.256671, 0.326804, 0.442219, 0.634292", \ - "0.135993, 0.198963, 0.228172, 0.271975, 0.342066, 0.457488, 0.649558", \ - "0.157832, 0.220802, 0.25006, 0.293917, 0.364, 0.479443, 0.67142", \ - "0.188531, 0.251785, 0.28107, 0.325019, 0.395111, 0.510563, 0.702543", \ - "0.227736, 0.292361, 0.321811, 0.365818, 0.436003, 0.551459, 0.743501", \ - "0.275976, 0.343985, 0.373794, 0.418047, 0.488305, 0.603815, 0.79591" \ + "0.095818, 0.158834, 0.188077, 0.231881, 0.301981, 0.417359, 0.609348", \ + "0.120666, 0.183676, 0.212909, 0.256662, 0.326795, 0.44221, 0.634284", \ + "0.135867, 0.198869, 0.228086, 0.2719, 0.341992, 0.457425, 0.649508", \ + "0.158022, 0.220996, 0.250258, 0.294119, 0.364204, 0.479645, 0.671593", \ + "0.188227, 0.251462, 0.280788, 0.324707, 0.394818, 0.51027, 0.702243", \ + "0.228242, 0.29283, 0.322275, 0.366287, 0.436424, 0.551945, 0.743966", \ + "0.276625, 0.344585, 0.374395, 0.418645, 0.488937, 0.604513, 0.796555" \ ); } fall_transition (TIMING_DELAY_7x7ds1) { index_1 ("0.0186, 0.0966, 0.174, 0.3294, 0.6408, 1.263, 2.5074"); index_2 ("0.001, 0.0234, 0.039, 0.0648, 0.108, 0.18, 0.3"); values ( \ - "0.022013, 0.0740785, 0.10367, 0.154866, 0.244865, 0.399116, 0.658982", \ - "0.022014, 0.074157, 0.103753, 0.154951, 0.244866, 0.399117, 0.65904", \ - "0.0220523, 0.0742681, 0.103754, 0.154952, 0.244867, 0.39913, 0.65905", \ - "0.0223522, 0.0742691, 0.10382, 0.154953, 0.244868, 0.399131, 0.659051", \ - "0.0233828, 0.0747065, 0.104073, 0.155084, 0.245007, 0.399132, 0.659055", \ - "0.025939, 0.075947, 0.104884, 0.155481, 0.24527, 0.399279, 0.659056", \ - "0.030109, 0.078946, 0.106756, 0.156668, 0.245856, 0.399841, 0.659363" \ + "0.022014, 0.0740791, 0.103677, 0.154867, 0.244865, 0.399116, 0.659032", \ + "0.022015, 0.074157, 0.103678, 0.154942, 0.244866, 0.399117, 0.659041", \ + "0.0220509, 0.0742532, 0.103679, 0.154943, 0.244867, 0.399287, 0.659054", \ + "0.0223495, 0.0742821, 0.103818, 0.154944, 0.244868, 0.399288, 0.659055", \ + "0.0233876, 0.0747071, 0.104107, 0.155152, 0.245001, 0.399289, 0.659056", \ + "0.025904, 0.075927, 0.104869, 0.155476, 0.245176, 0.39929, 0.659057", \ + "0.03011, 0.078853, 0.106771, 0.156668, 0.24585, 0.399552, 0.659112" \ ); } } timing () { related_pin : "RESET_B"; + sdf_edges : start_edge; timing_sense : negative_unate; timing_type : preset; cell_rise (TIMING_DELAY_7x7ds1) { index_1 ("0.0186, 0.0966, 0.174, 0.3294, 0.6408, 1.263, 2.5074"); index_2 ("0.001, 0.0234, 0.039, 0.0648, 0.108, 0.18, 0.3"); values ( \ - "0.137659, 0.194332, 0.226148, 0.277485, 0.362971, 0.505115, 0.742015", \ + "0.137659, 0.194332, 0.226148, 0.277486, 0.362971, 0.505115, 0.742015", \ "0.172362, 0.229035, 0.260863, 0.312192, 0.397742, 0.539868, 0.776829", \ "0.198707, 0.255391, 0.287186, 0.338555, 0.424111, 0.566258, 0.803666", \ - "0.237309, 0.294341, 0.326031, 0.377215, 0.46296, 0.60511, 0.84191", \ + "0.237309, 0.294341, 0.32615, 0.377215, 0.46296, 0.60511, 0.84191", \ "0.293729, 0.35105, 0.382474, 0.433658, 0.519227, 0.661559, 0.898315", \ "0.3722, 0.429702, 0.461128, 0.512665, 0.598308, 0.740237, 0.977255", \ - "0.488219, 0.545871, 0.577062, 0.628944, 0.714485, 0.855965, 1.09383" \ + "0.488219, 0.545871, 0.577062, 0.629247, 0.714485, 0.855965, 1.09383" \ ); } rise_transition (TIMING_DELAY_7x7ds1) { index_1 ("0.0186, 0.0966, 0.174, 0.3294, 0.6408, 1.263, 2.5074"); index_2 ("0.001, 0.0234, 0.039, 0.0648, 0.108, 0.18, 0.3"); values ( \ - "0.0181348, 0.080516, 0.124031, 0.198299, 0.324739, 0.536448, 0.889141", \ - "0.0182011, 0.080524, 0.124035, 0.1983, 0.325602, 0.536471, 0.889182", \ - "0.0183146, 0.080525, 0.124036, 0.198301, 0.325603, 0.53836, 0.889604", \ - "0.0186344, 0.0806594, 0.124053, 0.198302, 0.325604, 0.538361, 0.889605", \ + "0.0181348, 0.080516, 0.124031, 0.1983, 0.324739, 0.536448, 0.88914", \ + "0.018201, 0.080524, 0.124035, 0.198301, 0.325602, 0.536471, 0.889182", \ + "0.0183146, 0.080525, 0.124036, 0.198302, 0.325603, 0.53836, 0.889604", \ + "0.0186344, 0.0806594, 0.124049, 0.198303, 0.325604, 0.538361, 0.889605", \ "0.0192169, 0.0808588, 0.124192, 0.198328, 0.325605, 0.538362, 0.889606", \ "0.020024, 0.081229, 0.124393, 0.198395, 0.325606, 0.538363, 0.889607", \ "0.021053, 0.081729, 0.124622, 0.198549, 0.325607, 0.538364, 0.889608" \ @@ -28689,26 +28789,26 @@ library (sg13g2_stdcell_typ_1p50V_25C) { index_1 ("0.0186, 0.0966, 0.174, 0.3294, 0.6408, 1.263, 2.5074"); index_2 ("0.001, 0.0234, 0.039, 0.0648, 0.108, 0.18, 0.3"); values ( \ - "0.0485816, 0.0745675, 0.0922273, 0.121285, 0.169768, 0.250345, 0.384739", \ - "0.0490392, 0.0750099, 0.0928374, 0.121726, 0.17081, 0.250804, 0.385866", \ - "0.0500801, 0.076085, 0.0936833, 0.122854, 0.171198, 0.252013, 0.386092", \ + "0.0485816, 0.0745673, 0.0922528, 0.121316, 0.169767, 0.250343, 0.384752", \ + "0.0490273, 0.0750099, 0.0928374, 0.121726, 0.17081, 0.250804, 0.385866", \ + "0.0500801, 0.076085, 0.0936833, 0.122854, 0.171198, 0.252012, 0.386092", \ "0.0530563, 0.0790725, 0.0967807, 0.125771, 0.174339, 0.254993, 0.389384", \ "0.0593377, 0.0853464, 0.102992, 0.132234, 0.180802, 0.26143, 0.396845", \ "0.0729093, 0.0988837, 0.116466, 0.145682, 0.194245, 0.275401, 0.410087", \ - "0.100837, 0.126666, 0.14429, 0.173454, 0.221775, 0.303045, 0.437898" \ + "0.100837, 0.126666, 0.14429, 0.173455, 0.221775, 0.303045, 0.437898" \ ); } fall_power (POWER_7x7ds1) { index_1 ("0.0186, 0.0966, 0.174, 0.3294, 0.6408, 1.263, 2.5074"); index_2 ("0.001, 0.0234, 0.039, 0.0648, 0.108, 0.18, 0.3"); values ( \ - "0.0476195, 0.0729797, 0.0905271, 0.119411, 0.16759, 0.247733, 0.381311", \ - "0.0478224, 0.0731694, 0.0909409, 0.120049, 0.167813, 0.247913, 0.38168", \ - "0.0488167, 0.0741706, 0.0915491, 0.120535, 0.16987, 0.248869, 0.382435", \ - "0.0516815, 0.076963, 0.0946047, 0.12371, 0.17168, 0.252629, 0.38561", \ - "0.0580727, 0.083073, 0.100815, 0.1299, 0.178584, 0.258862, 0.392194", \ - "0.0724997, 0.0971016, 0.11478, 0.143612, 0.192411, 0.273481, 0.408325", \ - "0.101742, 0.125697, 0.143115, 0.17205, 0.220748, 0.30134, 0.435635" \ + "0.0485739, 0.0739362, 0.0915195, 0.120365, 0.168561, 0.248695, 0.382273", \ + "0.0488017, 0.0740999, 0.0918149, 0.120913, 0.168766, 0.248847, 0.38262", \ + "0.0497952, 0.07515, 0.0925576, 0.121505, 0.170712, 0.249877, 0.383423", \ + "0.0525323, 0.077815, 0.0954637, 0.124576, 0.172519, 0.253597, 0.386634", \ + "0.0592874, 0.0842943, 0.102042, 0.131174, 0.179852, 0.260207, 0.393449", \ + "0.0733824, 0.0980163, 0.115698, 0.144519, 0.19336, 0.27432, 0.409447", \ + "0.102725, 0.126694, 0.144051, 0.172977, 0.221646, 0.302229, 0.436171" \ ); } } @@ -28718,26 +28818,26 @@ library (sg13g2_stdcell_typ_1p50V_25C) { index_1 ("0.0186, 0.0966, 0.174, 0.3294, 0.6408, 1.263, 2.5074"); index_2 ("0.001, 0.0234, 0.039, 0.0648, 0.108, 0.18, 0.3"); values ( \ - "0.0485816, 0.0745675, 0.0922273, 0.121285, 0.169768, 0.250345, 0.384739", \ - "0.0490392, 0.0750099, 0.0928374, 0.121726, 0.17081, 0.250804, 0.385866", \ - "0.0500801, 0.076085, 0.0936833, 0.122854, 0.171198, 0.252013, 0.386092", \ + "0.0485816, 0.0745673, 0.0922528, 0.121316, 0.169767, 0.250343, 0.384752", \ + "0.0490273, 0.0750099, 0.0928374, 0.121726, 0.17081, 0.250804, 0.385866", \ + "0.0500801, 0.076085, 0.0936833, 0.122854, 0.171198, 0.252012, 0.386092", \ "0.0530563, 0.0790725, 0.0967807, 0.125771, 0.174339, 0.254993, 0.389384", \ "0.0593377, 0.0853464, 0.102992, 0.132234, 0.180802, 0.26143, 0.396845", \ "0.0729093, 0.0988837, 0.116466, 0.145682, 0.194245, 0.275401, 0.410087", \ - "0.100837, 0.126666, 0.14429, 0.173454, 0.221775, 0.303045, 0.437898" \ + "0.100837, 0.126666, 0.14429, 0.173455, 0.221775, 0.303045, 0.437898" \ ); } fall_power (POWER_7x7ds1) { index_1 ("0.0186, 0.0966, 0.174, 0.3294, 0.6408, 1.263, 2.5074"); index_2 ("0.001, 0.0234, 0.039, 0.0648, 0.108, 0.18, 0.3"); values ( \ - "0.0476195, 0.0729797, 0.0905271, 0.119411, 0.16759, 0.247733, 0.381311", \ - "0.0478224, 0.0731694, 0.0909409, 0.120049, 0.167813, 0.247913, 0.38168", \ - "0.0488167, 0.0741706, 0.0915491, 0.120535, 0.16987, 0.248869, 0.382435", \ - "0.0516815, 0.076963, 0.0946047, 0.12371, 0.17168, 0.252629, 0.38561", \ - "0.0580727, 0.083073, 0.100815, 0.1299, 0.178584, 0.258862, 0.392194", \ - "0.0724997, 0.0971016, 0.11478, 0.143612, 0.192411, 0.273481, 0.408325", \ - "0.101742, 0.125697, 0.143115, 0.17205, 0.220748, 0.30134, 0.435635" \ + "0.0485739, 0.0739362, 0.0915195, 0.120365, 0.168561, 0.248695, 0.382273", \ + "0.0488017, 0.0740999, 0.0918149, 0.120913, 0.168766, 0.248847, 0.38262", \ + "0.0497952, 0.07515, 0.0925576, 0.121505, 0.170712, 0.249877, 0.383423", \ + "0.0525323, 0.077815, 0.0954637, 0.124576, 0.172519, 0.253597, 0.386634", \ + "0.0592874, 0.0842943, 0.102042, 0.131174, 0.179852, 0.260207, 0.393449", \ + "0.0733824, 0.0980163, 0.115698, 0.144519, 0.19336, 0.27432, 0.409447", \ + "0.102725, 0.126694, 0.144051, 0.172977, 0.221646, 0.302229, 0.436171" \ ); } } @@ -28747,13 +28847,13 @@ library (sg13g2_stdcell_typ_1p50V_25C) { index_1 ("0.0186, 0.0966, 0.174, 0.3294, 0.6408, 1.263, 2.5074"); index_2 ("0.001, 0.0234, 0.039, 0.0648, 0.108, 0.18, 0.3"); values ( \ - "0.0511348, 0.0800895, 0.0994985, 0.12998, 0.177621, 0.25293, 0.374213", \ - "0.0510868, 0.0801654, 0.0997866, 0.131894, 0.18235, 0.260357, 0.384655", \ + "0.0511348, 0.0800895, 0.0994985, 0.129981, 0.177663, 0.252914, 0.374213", \ + "0.0510867, 0.0801654, 0.0997866, 0.131894, 0.18235, 0.260357, 0.384655", \ "0.0522052, 0.0810339, 0.10081, 0.133275, 0.184986, 0.266833, 0.393338", \ - "0.0552517, 0.0839746, 0.103651, 0.136134, 0.189753, 0.274484, 0.407822", \ + "0.0552517, 0.0839746, 0.103677, 0.136134, 0.189753, 0.274484, 0.407822", \ "0.0622594, 0.0907807, 0.110427, 0.142925, 0.197359, 0.285934, 0.426458", \ "0.0761068, 0.104818, 0.124212, 0.156637, 0.210933, 0.30167, 0.449329", \ - "0.104075, 0.132449, 0.151449, 0.18351, 0.237751, 0.32837, 0.478921" \ + "0.104075, 0.132449, 0.151449, 0.183488, 0.237751, 0.32837, 0.478921" \ ); } fall_power (scalar) { @@ -28769,9 +28869,9 @@ library (sg13g2_stdcell_typ_1p50V_25C) { max_transition : 2.5074; capacitance : 0.00310268; rise_capacitance : 0.0031561; - rise_capacitance_range (0.0031561, 0.0031561); + rise_capacitance_range (0.00280632, 0.00345406); fall_capacitance : 0.00303399; - fall_capacitance_range (0.00303399, 0.00303399); + fall_capacitance_range (0.00278181, 0.00324907); timing () { related_pin : "CLK"; timing_type : min_pulse_width; @@ -28787,7 +28887,7 @@ library (sg13g2_stdcell_typ_1p50V_25C) { rise_power (passive_POWER_7x1ds1) { index_1 ("0.0186, 0.0966, 0.174, 0.3294, 0.6408, 1.263, 2.5074"); values ( \ - "0.01678, 0.0171033, 0.0179915, 0.020838, 0.0267546, 0.0400176, 0.0671894" \ + "0.0167783, 0.0171033, 0.0179915, 0.0208379, 0.0267546, 0.0400175, 0.0671894" \ ); } fall_power (passive_POWER_7x1ds1) { @@ -28807,7 +28907,7 @@ library (sg13g2_stdcell_typ_1p50V_25C) { fall_power (passive_POWER_7x1ds1) { index_1 ("0.0186, 0.0966, 0.174, 0.3294, 0.6408, 1.263, 2.5074"); values ( \ - "0.0325061, 0.0328774, 0.0342462, 0.0371235, 0.0439269, 0.0575585, 0.0866647" \ + "0.032506, 0.0328774, 0.0342462, 0.0371235, 0.0439269, 0.0575585, 0.0866647" \ ); } } @@ -28821,7 +28921,7 @@ library (sg13g2_stdcell_typ_1p50V_25C) { fall_power (passive_POWER_7x1ds1) { index_1 ("0.0186, 0.0966, 0.174, 0.3294, 0.6408, 1.263, 2.5074"); values ( \ - "0.0299687, 0.0305327, 0.031968, 0.0349442, 0.0416758, 0.0553508, 0.0839071" \ + "0.0299687, 0.0305327, 0.031968, 0.0349443, 0.0416759, 0.0553509, 0.0839072" \ ); } } @@ -28836,7 +28936,7 @@ library (sg13g2_stdcell_typ_1p50V_25C) { fall_power (passive_POWER_7x1ds1) { index_1 ("0.0186, 0.0966, 0.174, 0.3294, 0.6408, 1.263, 2.5074"); values ( \ - "0.0167353, 0.0171803, 0.0184328, 0.021292, 0.0277843, 0.0410433, 0.0690876" \ + "0.0167353, 0.0171803, 0.0184329, 0.021292, 0.0277844, 0.0410433, 0.0690876" \ ); } } @@ -28845,7 +28945,7 @@ library (sg13g2_stdcell_typ_1p50V_25C) { rise_power (passive_POWER_7x1ds1) { index_1 ("0.0186, 0.0966, 0.174, 0.3294, 0.6408, 1.263, 2.5074"); values ( \ - "0.0167789, 0.0171035, 0.0179918, 0.0208386, 0.0267546, 0.0400178, 0.0671898" \ + "0.0167798, 0.0171035, 0.0179918, 0.0208386, 0.0267546, 0.0400178, 0.0671898" \ ); } fall_power (passive_POWER_7x1ds1) { @@ -28860,13 +28960,13 @@ library (sg13g2_stdcell_typ_1p50V_25C) { rise_power (passive_POWER_7x1ds1) { index_1 ("0.0186, 0.0966, 0.174, 0.3294, 0.6408, 1.263, 2.5074"); values ( \ - "0.0144213, 0.0147507, 0.0156414, 0.0184341, 0.0243265, 0.0375294, 0.0647316" \ + "0.0144213, 0.0147507, 0.0156414, 0.0184341, 0.0243265, 0.0375293, 0.0647316" \ ); } fall_power (passive_POWER_7x1ds1) { index_1 ("0.0186, 0.0966, 0.174, 0.3294, 0.6408, 1.263, 2.5074"); values ( \ - "0.0131194, 0.0135628, 0.0148158, 0.0176635, 0.0241524, 0.0373943, 0.065432" \ + "0.0131194, 0.0135629, 0.0148158, 0.0176635, 0.0241524, 0.0373943, 0.065432" \ ); } } @@ -28895,7 +28995,7 @@ library (sg13g2_stdcell_typ_1p50V_25C) { fall_power (passive_POWER_7x1ds1) { index_1 ("0.0186, 0.0966, 0.174, 0.3294, 0.6408, 1.263, 2.5074"); values ( \ - "0.0167353, 0.0171803, 0.0184328, 0.021292, 0.0277843, 0.0410433, 0.0690876" \ + "0.0167353, 0.0171803, 0.0184329, 0.021292, 0.0277844, 0.0410433, 0.0690876" \ ); } } @@ -28906,18 +29006,19 @@ library (sg13g2_stdcell_typ_1p50V_25C) { max_transition : 2.5074; capacitance : 0.00291162; rise_capacitance : 0.00298227; - rise_capacitance_range (0.00298227, 0.00298227); + rise_capacitance_range (0.00252196, 0.00336741); fall_capacitance : 0.00284097; - fall_capacitance_range (0.00284097, 0.00284097); + fall_capacitance_range (0.00251705, 0.00301407); timing () { related_pin : "CLK"; + sdf_edges : both_edges; timing_type : hold_rising; rise_constraint (CONSTRAINT_4x4) { index_1 ("0.0186, 0.51636, 1.263, 2.5074"); index_2 ("0.0186, 0.51636, 1.263, 2.5074"); values ( \ "-0.0929172, -0.0676338, -0.0555801, -0.0467003", \ - "-0.16947, -0.142602, -0.130154, -0.120358", \ + "-0.166974, -0.142602, -0.130154, -0.120358", \ "-0.204169, -0.179291, -0.167299, -0.156906", \ "-0.231231, -0.206773, -0.193388, -0.182995" \ ); @@ -28935,12 +29036,13 @@ library (sg13g2_stdcell_typ_1p50V_25C) { } timing () { related_pin : "CLK"; + sdf_edges : both_edges; timing_type : setup_rising; rise_constraint (CONSTRAINT_4x4) { index_1 ("0.0186, 0.51636, 1.263, 2.5074"); index_2 ("0.0186, 0.51636, 1.263, 2.5074"); values ( \ - "0.12226, 0.0876004, 0.0710107, 0.0601921", \ + "0.12226, 0.0876004, 0.0735825, 0.0601921", \ "0.196924, 0.162973, 0.145888, 0.136852", \ "0.235031, 0.20027, 0.183489, 0.173856", \ "0.260913, 0.226016, 0.210337, 0.197753" \ @@ -28962,7 +29064,7 @@ library (sg13g2_stdcell_typ_1p50V_25C) { rise_power (passive_POWER_7x1ds1) { index_1 ("0.0186, 0.0966, 0.174, 0.3294, 0.6408, 1.263, 2.5074"); values ( \ - "0.0326475, 0.0326465, 0.0334167, 0.0353766, 0.0399477, 0.0505603, 0.0714472" \ + "0.0326489, 0.0326465, 0.0334167, 0.0353766, 0.0399477, 0.0505603, 0.0714473" \ ); } fall_power (passive_POWER_7x1ds1) { @@ -28976,7 +29078,7 @@ library (sg13g2_stdcell_typ_1p50V_25C) { rise_power (passive_POWER_7x1ds1) { index_1 ("0.0186, 0.0966, 0.174, 0.3294, 0.6408, 1.263, 2.5074"); values ( \ - "0.0326475, 0.0326465, 0.0334167, 0.0353766, 0.0399477, 0.0505603, 0.0714472" \ + "0.0326489, 0.0326465, 0.0334167, 0.0353766, 0.0399477, 0.0505603, 0.0714473" \ ); } fall_power (passive_POWER_7x1ds1) { @@ -28990,13 +29092,14 @@ library (sg13g2_stdcell_typ_1p50V_25C) { pin (RESET_B) { direction : input; max_transition : 2.5074; - capacitance : 0.00527875; - rise_capacitance : 0.00527875; - rise_capacitance_range (0.00527875, 0.00527875); - fall_capacitance : 0.00527875; - fall_capacitance_range (0.00527875, 0.00527875); + capacitance : 0.00527874; + rise_capacitance : 0.00527874; + rise_capacitance_range (0.00527874, 0.00527874); + fall_capacitance : 0.00527874; + fall_capacitance_range (0.00492195, 0.00548553); timing () { related_pin : "CLK"; + sdf_edges : both_edges; timing_type : recovery_rising; rise_constraint (CONSTRAINT_4x4) { index_1 ("0.0186, 0.51636, 1.263, 2.5074"); @@ -29011,6 +29114,7 @@ library (sg13g2_stdcell_typ_1p50V_25C) { } timing () { related_pin : "CLK"; + sdf_edges : both_edges; timing_type : removal_rising; rise_constraint (CONSTRAINT_4x4) { index_1 ("0.0186, 0.51636, 1.263, 2.5074"); @@ -29040,11 +29144,12 @@ library (sg13g2_stdcell_typ_1p50V_25C) { max_transition : 2.5074; capacitance : 0.00303854; rise_capacitance : 0.00308538; - rise_capacitance_range (0.00308538, 0.00308538); + rise_capacitance_range (0.00262894, 0.00346689); fall_capacitance : 0.00294486; - fall_capacitance_range (0.00294486, 0.00294486); + fall_capacitance_range (0.00262214, 0.00311723); timing () { related_pin : "CLK"; + sdf_edges : both_edges; timing_type : hold_rising; rise_constraint (CONSTRAINT_4x4) { index_1 ("0.0186, 0.51636, 1.263, 2.5074"); @@ -29069,6 +29174,7 @@ library (sg13g2_stdcell_typ_1p50V_25C) { } timing () { related_pin : "CLK"; + sdf_edges : both_edges; timing_type : setup_rising; rise_constraint (CONSTRAINT_4x4) { index_1 ("0.0186, 0.51636, 1.263, 2.5074"); @@ -29096,13 +29202,13 @@ library (sg13g2_stdcell_typ_1p50V_25C) { rise_power (passive_POWER_7x1ds1) { index_1 ("0.0186, 0.0966, 0.174, 0.3294, 0.6408, 1.263, 2.5074"); values ( \ - "0.0329149, 0.0328593, 0.0336414, 0.035536, 0.0401491, 0.0507724, 0.0716911" \ + "0.0329148, 0.0328593, 0.0336414, 0.035536, 0.0401491, 0.0507724, 0.071691" \ ); } fall_power (passive_POWER_7x1ds1) { index_1 ("0.0186, 0.0966, 0.174, 0.3294, 0.6408, 1.263, 2.5074"); values ( \ - "0.0281009, 0.0284389, 0.0295948, 0.0320295, 0.0375495, 0.0483303, 0.0707724" \ + "0.0281287, 0.0284389, 0.0295949, 0.0320295, 0.0375495, 0.0483303, 0.0707724" \ ); } } @@ -29110,13 +29216,13 @@ library (sg13g2_stdcell_typ_1p50V_25C) { rise_power (passive_POWER_7x1ds1) { index_1 ("0.0186, 0.0966, 0.174, 0.3294, 0.6408, 1.263, 2.5074"); values ( \ - "0.0329149, 0.0328593, 0.0336414, 0.035536, 0.0401491, 0.0507724, 0.0716911" \ + "0.0329148, 0.0328593, 0.0336414, 0.035536, 0.0401491, 0.0507724, 0.071691" \ ); } fall_power (passive_POWER_7x1ds1) { index_1 ("0.0186, 0.0966, 0.174, 0.3294, 0.6408, 1.263, 2.5074"); values ( \ - "0.0281009, 0.0284389, 0.0295948, 0.0320295, 0.0375495, 0.0483303, 0.0707724" \ + "0.0281287, 0.0284389, 0.0295949, 0.0320295, 0.0375495, 0.0483303, 0.0707724" \ ); } } @@ -29127,11 +29233,12 @@ library (sg13g2_stdcell_typ_1p50V_25C) { max_transition : 2.5074; capacitance : 0.00516345; rise_capacitance : 0.00547338; - rise_capacitance_range (0.00547338, 0.00547338); + rise_capacitance_range (0.00459749, 0.00608228); fall_capacitance : 0.00485351; - fall_capacitance_range (0.00485351, 0.00485351); + fall_capacitance_range (0.00462954, 0.00534699); timing () { related_pin : "CLK"; + sdf_edges : both_edges; timing_type : hold_rising; rise_constraint (CONSTRAINT_4x4) { index_1 ("0.0186, 0.51636, 1.263, 2.5074"); @@ -29156,6 +29263,7 @@ library (sg13g2_stdcell_typ_1p50V_25C) { } timing () { related_pin : "CLK"; + sdf_edges : both_edges; timing_type : setup_rising; rise_constraint (CONSTRAINT_4x4) { index_1 ("0.0186, 0.51636, 1.263, 2.5074"); @@ -29183,13 +29291,13 @@ library (sg13g2_stdcell_typ_1p50V_25C) { rise_power (passive_POWER_7x1ds1) { index_1 ("0.0186, 0.0966, 0.174, 0.3294, 0.6408, 1.263, 2.5074"); values ( \ - "0.0357546, 0.0357927, 0.0365982, 0.0383583, 0.0425898, 0.0517583, 0.0709741" \ + "0.0357547, 0.0357927, 0.0365982, 0.0383584, 0.0425898, 0.0517583, 0.0709741" \ ); } fall_power (passive_POWER_7x1ds1) { index_1 ("0.0186, 0.0966, 0.174, 0.3294, 0.6408, 1.263, 2.5074"); values ( \ - "0.0408358, 0.0410656, 0.0418969, 0.043904, 0.0482916, 0.0578398, 0.0775549" \ + "0.0408358, 0.0410657, 0.0418969, 0.043904, 0.0482916, 0.0578398, 0.0775549" \ ); } } @@ -29204,7 +29312,7 @@ library (sg13g2_stdcell_typ_1p50V_25C) { fall_power (passive_POWER_7x1ds1) { index_1 ("0.0186, 0.0966, 0.174, 0.3294, 0.6408, 1.263, 2.5074"); values ( \ - "0.0505509, 0.0650994, 0.0669951, 0.0710142, 0.0802245, 0.0996792, 0.140051" \ + "0.0505502, 0.0650994, 0.0669951, 0.0710142, 0.0802245, 0.0996792, 0.140051" \ ); } } @@ -29218,15 +29326,15 @@ library (sg13g2_stdcell_typ_1p50V_25C) { fall_power (passive_POWER_7x1ds1) { index_1 ("0.0186, 0.0966, 0.174, 0.3294, 0.6408, 1.263, 2.5074"); values ( \ - "0.0505509, 0.0650994, 0.0669951, 0.0710142, 0.0802245, 0.0996792, 0.140051" \ + "0.0505502, 0.0650994, 0.0669951, 0.0710142, 0.0802245, 0.0996792, 0.140051" \ ); } } } ff (IQ,IQN) { - clear : "RESET_B'"; + clear : "!RESET_B"; clocked_on : "CLK"; - next_state : "(SCE*SCD)+(SCE'*D)"; + next_state : "(SCE*SCD)+(!SCE*D)"; } test_cell () { pin (Q) { @@ -29257,7 +29365,7 @@ library (sg13g2_stdcell_typ_1p50V_25C) { signal_type : test_scan_enable; } ff (IQ,IQN) { - clear : "RESET_B'"; + clear : "!RESET_B"; clocked_on : "CLK"; next_state : "D"; } @@ -29284,7 +29392,7 @@ library (sg13g2_stdcell_typ_1p50V_25C) { when : "CLK&!D&RESET_B&!SCD&!SCE&!Q"; } leakage_power () { - value : 2536.23; + value : 2536.22; when : "CLK&!D&RESET_B&!SCD&!SCE&Q&!Q_N"; } leakage_power () { @@ -29292,11 +29400,11 @@ library (sg13g2_stdcell_typ_1p50V_25C) { when : "!CLK&D&RESET_B&!SCD&!SCE&!Q&Q_N"; } leakage_power () { - value : 2741.38; + value : 2741.39; when : "!CLK&D&RESET_B&!SCD&!SCE&Q&!Q_N"; } leakage_power () { - value : 2722.13; + value : 2722.14; when : "CLK&D&RESET_B&!SCD&!SCE&!Q&Q_N"; } leakage_power () { @@ -29324,7 +29432,7 @@ library (sg13g2_stdcell_typ_1p50V_25C) { when : "CLK&!D&RESET_B&!SCD&SCE&!Q&Q_N"; } leakage_power () { - value : 2819.56; + value : 2819.55; when : "CLK&!D&RESET_B&!SCD&SCE&Q&!Q_N"; } leakage_power () { @@ -29343,6 +29451,7 @@ library (sg13g2_stdcell_typ_1p50V_25C) { timing () { related_pin : "CLK"; sdf_cond : "SCE == 1'b1"; + sdf_edges : start_edge; timing_sense : non_unate; timing_type : rising_edge; when : "SCE"; @@ -29350,12 +29459,12 @@ library (sg13g2_stdcell_typ_1p50V_25C) { index_1 ("0.0186, 0.0966, 0.174, 0.3294, 0.6408, 1.263, 2.5074"); index_2 ("0.001, 0.0468, 0.078, 0.1296, 0.216, 0.36, 0.6"); values ( \ - "0.161903, 0.201451, 0.231653, 0.282528, 0.368295, 0.511647, 0.750928", \ + "0.161861, 0.201443, 0.231655, 0.282528, 0.368295, 0.51165, 0.750932", \ "0.186882, 0.226351, 0.256685, 0.307587, 0.393396, 0.536853, 0.775822", \ "0.202072, 0.241514, 0.271726, 0.322609, 0.408378, 0.551718, 0.790944", \ "0.223849, 0.263366, 0.293638, 0.344501, 0.430299, 0.573625, 0.812699", \ "0.254921, 0.294353, 0.324522, 0.375399, 0.461177, 0.60451, 0.843622", \ - "0.296263, 0.335208, 0.365281, 0.41606, 0.501778, 0.6451, 0.88427", \ + "0.296263, 0.335208, 0.365281, 0.41606, 0.501778, 0.6451, 0.884267", \ "0.349773, 0.387291, 0.417098, 0.467751, 0.553367, 0.696699, 0.935791" \ ); } @@ -29363,21 +29472,21 @@ library (sg13g2_stdcell_typ_1p50V_25C) { index_1 ("0.0186, 0.0966, 0.174, 0.3294, 0.6408, 1.263, 2.5074"); index_2 ("0.001, 0.0468, 0.078, 0.1296, 0.216, 0.36, 0.6"); values ( \ - "0.0165249, 0.0770071, 0.122434, 0.198681, 0.326509, 0.539916, 0.895987", \ - "0.0165259, 0.0770084, 0.122435, 0.198682, 0.326605, 0.54016, 0.895988", \ - "0.0165483, 0.0770094, 0.122436, 0.198683, 0.326606, 0.540161, 0.895989", \ - "0.0165497, 0.0770104, 0.122437, 0.198684, 0.326607, 0.540162, 0.89599", \ - "0.0166219, 0.0770225, 0.122438, 0.198685, 0.326608, 0.540163, 0.895991", \ - "0.016783, 0.077095, 0.122486, 0.198693, 0.326609, 0.540164, 0.895992", \ - "0.017382, 0.077275, 0.122489, 0.198722, 0.32661, 0.540165, 0.895993" \ + "0.016542, 0.0770075, 0.122455, 0.198681, 0.326509, 0.53988, 0.895585", \ + "0.016543, 0.0770084, 0.122456, 0.198682, 0.326605, 0.54016, 0.895586", \ + "0.0165483, 0.0770094, 0.122457, 0.198683, 0.326606, 0.540161, 0.895841", \ + "0.0165497, 0.0770104, 0.122458, 0.198684, 0.326607, 0.540162, 0.895842", \ + "0.0166219, 0.0770225, 0.122459, 0.198685, 0.326608, 0.540163, 0.895843", \ + "0.016783, 0.077095, 0.122486, 0.198693, 0.326609, 0.540164, 0.895844", \ + "0.017382, 0.077275, 0.122489, 0.198722, 0.32661, 0.540165, 0.895845" \ ); } cell_fall (TIMING_DELAY_7x7ds1) { index_1 ("0.0186, 0.0966, 0.174, 0.3294, 0.6408, 1.263, 2.5074"); index_2 ("0.001, 0.0468, 0.078, 0.1296, 0.216, 0.36, 0.6"); values ( \ - "0.140174, 0.178714, 0.203701, 0.244952, 0.314212, 0.429565, 0.622084", \ - "0.164824, 0.203251, 0.228308, 0.269622, 0.338786, 0.454289, 0.64666", \ + "0.14018, 0.178703, 0.203688, 0.245028, 0.314175, 0.429565, 0.622083", \ + "0.164907, 0.203318, 0.228288, 0.26961, 0.338802, 0.454289, 0.6467", \ "0.179598, 0.218036, 0.243096, 0.284389, 0.353569, 0.468969, 0.661319", \ "0.200001, 0.23843, 0.263453, 0.304752, 0.373947, 0.489334, 0.681693", \ "0.227506, 0.265986, 0.290996, 0.332304, 0.401507, 0.516935, 0.709281", \ @@ -29389,30 +29498,31 @@ library (sg13g2_stdcell_typ_1p50V_25C) { index_1 ("0.0186, 0.0966, 0.174, 0.3294, 0.6408, 1.263, 2.5074"); index_2 ("0.001, 0.0468, 0.078, 0.1296, 0.216, 0.36, 0.6"); values ( \ - "0.0138148, 0.0596712, 0.0924798, 0.148095, 0.241929, 0.398717, 0.659996", \ - "0.0138158, 0.0596722, 0.0925187, 0.148096, 0.241957, 0.398718, 0.660106", \ - "0.0138473, 0.0596732, 0.0925197, 0.148145, 0.241958, 0.398719, 0.660107", \ - "0.0138483, 0.0596754, 0.0925207, 0.148146, 0.241959, 0.39872, 0.660108", \ - "0.0138559, 0.0596764, 0.0925217, 0.148147, 0.242013, 0.398721, 0.660109", \ - "0.0138569, 0.059679, 0.0925227, 0.148148, 0.242014, 0.398722, 0.660307", \ - "0.0138579, 0.05968, 0.0925237, 0.148149, 0.242015, 0.398723, 0.660308" \ + "0.0138148, 0.0596782, 0.0924987, 0.148094, 0.241948, 0.398717, 0.659996", \ + "0.0138158, 0.0596792, 0.0925187, 0.148095, 0.242076, 0.398718, 0.660107", \ + "0.0138473, 0.0596802, 0.0925197, 0.148145, 0.242077, 0.398719, 0.660108", \ + "0.0138483, 0.0596812, 0.0925207, 0.148146, 0.242078, 0.39872, 0.660109", \ + "0.0138559, 0.0596822, 0.0925217, 0.148147, 0.242079, 0.398721, 0.66011", \ + "0.0138569, 0.0596832, 0.0925227, 0.148148, 0.24208, 0.398722, 0.660307", \ + "0.0138579, 0.0596842, 0.0925237, 0.148149, 0.242081, 0.398723, 0.660308" \ ); } } timing () { related_pin : "CLK"; + sdf_edges : start_edge; timing_sense : non_unate; timing_type : rising_edge; cell_rise (TIMING_DELAY_7x7ds1) { index_1 ("0.0186, 0.0966, 0.174, 0.3294, 0.6408, 1.263, 2.5074"); index_2 ("0.001, 0.0468, 0.078, 0.1296, 0.216, 0.36, 0.6"); values ( \ - "0.161903, 0.201451, 0.231653, 0.282528, 0.368295, 0.511647, 0.750928", \ + "0.161861, 0.201443, 0.231655, 0.282528, 0.368295, 0.51165, 0.750932", \ "0.186882, 0.226351, 0.256685, 0.307587, 0.393396, 0.536853, 0.775822", \ "0.202072, 0.241514, 0.271726, 0.322609, 0.408378, 0.551718, 0.790944", \ "0.223849, 0.263366, 0.293638, 0.344501, 0.430299, 0.573625, 0.812699", \ "0.254921, 0.294353, 0.324522, 0.375399, 0.461177, 0.60451, 0.843622", \ - "0.296263, 0.335208, 0.365281, 0.41606, 0.501778, 0.6451, 0.88427", \ + "0.296263, 0.335208, 0.365281, 0.41606, 0.501778, 0.6451, 0.884267", \ "0.349773, 0.387291, 0.417098, 0.467751, 0.553367, 0.696699, 0.935791" \ ); } @@ -29420,21 +29530,21 @@ library (sg13g2_stdcell_typ_1p50V_25C) { index_1 ("0.0186, 0.0966, 0.174, 0.3294, 0.6408, 1.263, 2.5074"); index_2 ("0.001, 0.0468, 0.078, 0.1296, 0.216, 0.36, 0.6"); values ( \ - "0.0165249, 0.0770071, 0.122434, 0.198681, 0.326509, 0.539916, 0.895987", \ - "0.0165259, 0.0770084, 0.122435, 0.198682, 0.326605, 0.54016, 0.895988", \ - "0.0165483, 0.0770094, 0.122436, 0.198683, 0.326606, 0.540161, 0.895989", \ - "0.0165497, 0.0770104, 0.122437, 0.198684, 0.326607, 0.540162, 0.89599", \ - "0.0166219, 0.0770225, 0.122438, 0.198685, 0.326608, 0.540163, 0.895991", \ - "0.016783, 0.077095, 0.122486, 0.198693, 0.326609, 0.540164, 0.895992", \ - "0.017382, 0.077275, 0.122489, 0.198722, 0.32661, 0.540165, 0.895993" \ + "0.016542, 0.0770075, 0.122455, 0.198681, 0.326509, 0.53988, 0.895585", \ + "0.016543, 0.0770084, 0.122456, 0.198682, 0.326605, 0.54016, 0.895586", \ + "0.0165483, 0.0770094, 0.122457, 0.198683, 0.326606, 0.540161, 0.895841", \ + "0.0165497, 0.0770104, 0.122458, 0.198684, 0.326607, 0.540162, 0.895842", \ + "0.0166219, 0.0770225, 0.122459, 0.198685, 0.326608, 0.540163, 0.895843", \ + "0.016783, 0.077095, 0.122486, 0.198693, 0.326609, 0.540164, 0.895844", \ + "0.017382, 0.077275, 0.122489, 0.198722, 0.32661, 0.540165, 0.895845" \ ); } cell_fall (TIMING_DELAY_7x7ds1) { index_1 ("0.0186, 0.0966, 0.174, 0.3294, 0.6408, 1.263, 2.5074"); index_2 ("0.001, 0.0468, 0.078, 0.1296, 0.216, 0.36, 0.6"); values ( \ - "0.140174, 0.178714, 0.203701, 0.244952, 0.314212, 0.429565, 0.622084", \ - "0.164824, 0.203251, 0.228308, 0.269622, 0.338786, 0.454289, 0.64666", \ + "0.14018, 0.178703, 0.203688, 0.245028, 0.314175, 0.429565, 0.622083", \ + "0.164907, 0.203318, 0.228288, 0.26961, 0.338802, 0.454289, 0.6467", \ "0.179598, 0.218036, 0.243096, 0.284389, 0.353569, 0.468969, 0.661319", \ "0.200001, 0.23843, 0.263453, 0.304752, 0.373947, 0.489334, 0.681693", \ "0.227506, 0.265986, 0.290996, 0.332304, 0.401507, 0.516935, 0.709281", \ @@ -29446,25 +29556,26 @@ library (sg13g2_stdcell_typ_1p50V_25C) { index_1 ("0.0186, 0.0966, 0.174, 0.3294, 0.6408, 1.263, 2.5074"); index_2 ("0.001, 0.0468, 0.078, 0.1296, 0.216, 0.36, 0.6"); values ( \ - "0.0138148, 0.0596712, 0.0924798, 0.148095, 0.241929, 0.398717, 0.659996", \ - "0.0138158, 0.0596722, 0.0925187, 0.148096, 0.241957, 0.398718, 0.660106", \ - "0.0138473, 0.0596732, 0.0925197, 0.148145, 0.241958, 0.398719, 0.660107", \ - "0.0138483, 0.0596754, 0.0925207, 0.148146, 0.241959, 0.39872, 0.660108", \ - "0.0138559, 0.0596764, 0.0925217, 0.148147, 0.242013, 0.398721, 0.660109", \ - "0.0138569, 0.059679, 0.0925227, 0.148148, 0.242014, 0.398722, 0.660307", \ - "0.0138579, 0.05968, 0.0925237, 0.148149, 0.242015, 0.398723, 0.660308" \ + "0.0138148, 0.0596782, 0.0924987, 0.148094, 0.241948, 0.398717, 0.659996", \ + "0.0138158, 0.0596792, 0.0925187, 0.148095, 0.242076, 0.398718, 0.660107", \ + "0.0138473, 0.0596802, 0.0925197, 0.148145, 0.242077, 0.398719, 0.660108", \ + "0.0138483, 0.0596812, 0.0925207, 0.148146, 0.242078, 0.39872, 0.660109", \ + "0.0138559, 0.0596822, 0.0925217, 0.148147, 0.242079, 0.398721, 0.66011", \ + "0.0138569, 0.0596832, 0.0925227, 0.148148, 0.24208, 0.398722, 0.660307", \ + "0.0138579, 0.0596842, 0.0925237, 0.148149, 0.242081, 0.398723, 0.660308" \ ); } } timing () { related_pin : "RESET_B"; + sdf_edges : start_edge; timing_sense : positive_unate; timing_type : clear; cell_fall (TIMING_DELAY_7x7ds1) { index_1 ("0.0186, 0.0966, 0.174, 0.3294, 0.6408, 1.263, 2.5074"); index_2 ("0.001, 0.0468, 0.078, 0.1296, 0.216, 0.36, 0.6"); values ( \ - "0.188891, 0.227566, 0.252178, 0.291061, 0.351965, 0.447451, 0.600589", \ + "0.188891, 0.227567, 0.252178, 0.291018, 0.351965, 0.447497, 0.600589", \ "0.223589, 0.262394, 0.287278, 0.327684, 0.391947, 0.491857, 0.649397", \ "0.25001, 0.288709, 0.313819, 0.354783, 0.420829, 0.524137, 0.685301", \ "0.288882, 0.327685, 0.352568, 0.393751, 0.461812, 0.569874, 0.738155", \ @@ -29477,13 +29588,13 @@ library (sg13g2_stdcell_typ_1p50V_25C) { index_1 ("0.0186, 0.0966, 0.174, 0.3294, 0.6408, 1.263, 2.5074"); index_2 ("0.001, 0.0468, 0.078, 0.1296, 0.216, 0.36, 0.6"); values ( \ - "0.0136805, 0.0596423, 0.0925056, 0.148027, 0.241904, 0.398614, 0.659913", \ - "0.0136815, 0.0596433, 0.0925066, 0.148028, 0.242223, 0.398724, 0.660124", \ - "0.0136825, 0.0596443, 0.0925076, 0.148029, 0.242224, 0.398725, 0.660125", \ - "0.0136993, 0.0596453, 0.0925086, 0.14803, 0.242225, 0.398726, 0.660126", \ - "0.0137815, 0.0596809, 0.0925096, 0.148031, 0.242226, 0.398727, 0.660127", \ - "0.013853, 0.059736, 0.092518, 0.148032, 0.242227, 0.398728, 0.660128", \ - "0.01396, 0.05978, 0.092543, 0.148033, 0.242228, 0.398729, 0.660129" \ + "0.0136805, 0.0596422, 0.0925056, 0.148015, 0.241904, 0.398632, 0.659913", \ + "0.0136815, 0.0596432, 0.0925066, 0.148026, 0.242223, 0.398724, 0.660124", \ + "0.0136825, 0.0596442, 0.0925076, 0.148027, 0.242224, 0.398725, 0.660125", \ + "0.0136993, 0.0596452, 0.0925086, 0.148028, 0.242225, 0.398726, 0.660126", \ + "0.0137815, 0.0596809, 0.0925096, 0.148029, 0.242226, 0.398727, 0.660127", \ + "0.013853, 0.059736, 0.092518, 0.14803, 0.242227, 0.398728, 0.660128", \ + "0.01396, 0.05978, 0.092543, 0.148031, 0.242228, 0.398729, 0.660129" \ ); } } @@ -29494,23 +29605,23 @@ library (sg13g2_stdcell_typ_1p50V_25C) { index_1 ("0.0186, 0.0966, 0.174, 0.3294, 0.6408, 1.263, 2.5074"); index_2 ("0.001, 0.0468, 0.078, 0.1296, 0.216, 0.36, 0.6"); values ( \ - "0.0633598, 0.112824, 0.148158, 0.20626, 0.30311, 0.464528, 0.733757", \ + "0.0633873, 0.112824, 0.148158, 0.20626, 0.303108, 0.4645, 0.733228", \ "0.0636106, 0.113094, 0.148656, 0.206697, 0.303487, 0.465083, 0.733294", \ "0.0645737, 0.113819, 0.149077, 0.207614, 0.304183, 0.466629, 0.734611", \ "0.0674532, 0.116673, 0.152146, 0.210181, 0.307258, 0.468788, 0.737422", \ - "0.073842, 0.122789, 0.158078, 0.216438, 0.313901, 0.474929, 0.745739", \ - "0.0885325, 0.136624, 0.171799, 0.23015, 0.327526, 0.489769, 0.758493", \ - "0.118431, 0.165054, 0.200078, 0.258403, 0.355309, 0.517544, 0.787416" \ + "0.073842, 0.122788, 0.158078, 0.216438, 0.313901, 0.474929, 0.745739", \ + "0.0885338, 0.136624, 0.171799, 0.23015, 0.327528, 0.489769, 0.758734", \ + "0.11843, 0.165061, 0.200078, 0.258403, 0.355309, 0.517544, 0.787416" \ ); } fall_power (POWER_7x7ds1) { index_1 ("0.0186, 0.0966, 0.174, 0.3294, 0.6408, 1.263, 2.5074"); index_2 ("0.001, 0.0468, 0.078, 0.1296, 0.216, 0.36, 0.6"); values ( \ - "0.061788, 0.113438, 0.148566, 0.206363, 0.302732, 0.462956, 0.729911", \ - "0.0621424, 0.113788, 0.149463, 0.20707, 0.30327, 0.463376, 0.730766", \ + "0.0617875, 0.113435, 0.148572, 0.206405, 0.302728, 0.462956, 0.729911", \ + "0.0621605, 0.113804, 0.149462, 0.207087, 0.304354, 0.463376, 0.730784", \ "0.0632927, 0.115149, 0.150128, 0.208002, 0.306969, 0.464957, 0.731296", \ - "0.0662407, 0.118083, 0.153511, 0.211636, 0.307078, 0.470023, 0.735246", \ + "0.0662407, 0.118083, 0.153511, 0.211636, 0.307078, 0.468834, 0.735246", \ "0.072531, 0.124195, 0.159661, 0.217915, 0.315253, 0.47639, 0.743187", \ "0.0862022, 0.137693, 0.173047, 0.230859, 0.3287, 0.490775, 0.761061", \ "0.114167, 0.165336, 0.2004, 0.258447, 0.356089, 0.517115, 0.785804" \ @@ -29523,23 +29634,23 @@ library (sg13g2_stdcell_typ_1p50V_25C) { index_1 ("0.0186, 0.0966, 0.174, 0.3294, 0.6408, 1.263, 2.5074"); index_2 ("0.001, 0.0468, 0.078, 0.1296, 0.216, 0.36, 0.6"); values ( \ - "0.0633598, 0.112824, 0.148158, 0.20626, 0.30311, 0.464528, 0.733757", \ + "0.0633873, 0.112824, 0.148158, 0.20626, 0.303108, 0.4645, 0.733228", \ "0.0636106, 0.113094, 0.148656, 0.206697, 0.303487, 0.465083, 0.733294", \ "0.0645737, 0.113819, 0.149077, 0.207614, 0.304183, 0.466629, 0.734611", \ "0.0674532, 0.116673, 0.152146, 0.210181, 0.307258, 0.468788, 0.737422", \ - "0.073842, 0.122789, 0.158078, 0.216438, 0.313901, 0.474929, 0.745739", \ - "0.0885325, 0.136624, 0.171799, 0.23015, 0.327526, 0.489769, 0.758493", \ - "0.118431, 0.165054, 0.200078, 0.258403, 0.355309, 0.517544, 0.787416" \ + "0.073842, 0.122788, 0.158078, 0.216438, 0.313901, 0.474929, 0.745739", \ + "0.0885338, 0.136624, 0.171799, 0.23015, 0.327528, 0.489769, 0.758734", \ + "0.11843, 0.165061, 0.200078, 0.258403, 0.355309, 0.517544, 0.787416" \ ); } fall_power (POWER_7x7ds1) { index_1 ("0.0186, 0.0966, 0.174, 0.3294, 0.6408, 1.263, 2.5074"); index_2 ("0.001, 0.0468, 0.078, 0.1296, 0.216, 0.36, 0.6"); values ( \ - "0.061788, 0.113438, 0.148566, 0.206363, 0.302732, 0.462956, 0.729911", \ - "0.0621424, 0.113788, 0.149463, 0.20707, 0.30327, 0.463376, 0.730766", \ + "0.0617875, 0.113435, 0.148572, 0.206405, 0.302728, 0.462956, 0.729911", \ + "0.0621605, 0.113804, 0.149462, 0.207087, 0.304354, 0.463376, 0.730784", \ "0.0632927, 0.115149, 0.150128, 0.208002, 0.306969, 0.464957, 0.731296", \ - "0.0662407, 0.118083, 0.153511, 0.211636, 0.307078, 0.470023, 0.735246", \ + "0.0662407, 0.118083, 0.153511, 0.211636, 0.307078, 0.468834, 0.735246", \ "0.072531, 0.124195, 0.159661, 0.217915, 0.315253, 0.47639, 0.743187", \ "0.0862022, 0.137693, 0.173047, 0.230859, 0.3287, 0.490775, 0.761061", \ "0.114167, 0.165336, 0.2004, 0.258447, 0.356089, 0.517115, 0.785804" \ @@ -29557,7 +29668,7 @@ library (sg13g2_stdcell_typ_1p50V_25C) { index_1 ("0.0186, 0.0966, 0.174, 0.3294, 0.6408, 1.263, 2.5074"); index_2 ("0.001, 0.0468, 0.078, 0.1296, 0.216, 0.36, 0.6"); values ( \ - "0.0650845, 0.128932, 0.171937, 0.240144, 0.347767, 0.517634, 0.791845", \ + "0.0650845, 0.128932, 0.171937, 0.240133, 0.347767, 0.517645, 0.791845", \ "0.0650609, 0.129174, 0.17357, 0.242856, 0.355598, 0.531645, 0.812442", \ "0.0661642, 0.12987, 0.173544, 0.245467, 0.361078, 0.541515, 0.827249", \ "0.0693311, 0.132927, 0.176537, 0.247964, 0.366286, 0.559052, 0.85182", \ @@ -29576,6 +29687,7 @@ library (sg13g2_stdcell_typ_1p50V_25C) { timing () { related_pin : "CLK"; sdf_cond : "SCE == 1'b1"; + sdf_edges : start_edge; timing_sense : non_unate; timing_type : rising_edge; when : "SCE"; @@ -29583,8 +29695,8 @@ library (sg13g2_stdcell_typ_1p50V_25C) { index_1 ("0.0186, 0.0966, 0.174, 0.3294, 0.6408, 1.263, 2.5074"); index_2 ("0.001, 0.0468, 0.078, 0.1296, 0.216, 0.36, 0.6"); values ( \ - "0.094305, 0.15823, 0.191162, 0.243065, 0.328695, 0.471105, 0.708206", \ - "0.118923, 0.182846, 0.215758, 0.267608, 0.353313, 0.495703, 0.733527", \ + "0.0943031, 0.15823, 0.191147, 0.243067, 0.32872, 0.471105, 0.708206", \ + "0.119004, 0.182886, 0.215732, 0.267595, 0.353313, 0.495703, 0.733593", \ "0.133684, 0.197605, 0.230488, 0.282333, 0.368029, 0.510355, 0.747403", \ "0.154068, 0.218008, 0.250882, 0.302797, 0.388421, 0.530743, 0.767696", \ "0.181638, 0.245463, 0.27831, 0.330213, 0.415924, 0.558291, 0.795221", \ @@ -29596,52 +29708,53 @@ library (sg13g2_stdcell_typ_1p50V_25C) { index_1 ("0.0186, 0.0966, 0.174, 0.3294, 0.6408, 1.263, 2.5074"); index_2 ("0.001, 0.0468, 0.078, 0.1296, 0.216, 0.36, 0.6"); values ( \ - "0.0180196, 0.0847028, 0.127734, 0.200929, 0.326397, 0.537983, 0.89148", \ - "0.0180206, 0.0847059, 0.12774, 0.20093, 0.326511, 0.538019, 0.89222", \ - "0.0180216, 0.0847069, 0.127777, 0.200931, 0.326512, 0.538179, 0.892221", \ - "0.0180226, 0.0847186, 0.127778, 0.200932, 0.326513, 0.53818, 0.892222", \ - "0.0180236, 0.0847474, 0.127779, 0.200933, 0.326514, 0.538181, 0.892223", \ - "0.0180246, 0.0847484, 0.127785, 0.200934, 0.326515, 0.538182, 0.892224", \ - "0.0180256, 0.0847494, 0.127786, 0.200935, 0.326516, 0.538183, 0.892225" \ + "0.018019, 0.0847027, 0.12777, 0.200927, 0.326402, 0.537983, 0.89148", \ + "0.01802, 0.0847033, 0.127793, 0.200928, 0.326511, 0.538019, 0.892257", \ + "0.018021, 0.0847043, 0.127794, 0.200929, 0.326512, 0.538179, 0.892258", \ + "0.018022, 0.0847186, 0.127795, 0.20093, 0.326513, 0.53818, 0.892259", \ + "0.018023, 0.0847474, 0.127796, 0.200931, 0.326514, 0.538181, 0.89226", \ + "0.018024, 0.0847484, 0.127797, 0.200932, 0.326515, 0.538182, 0.892261", \ + "0.018025, 0.0847494, 0.127798, 0.200933, 0.326516, 0.538183, 0.892262" \ ); } cell_fall (TIMING_DELAY_7x7ds1) { index_1 ("0.0186, 0.0966, 0.174, 0.3294, 0.6408, 1.263, 2.5074"); index_2 ("0.001, 0.0468, 0.078, 0.1296, 0.216, 0.36, 0.6"); values ( \ - "0.105753, 0.176476, 0.207646, 0.253009, 0.324285, 0.440204, 0.632546", \ + "0.105753, 0.176476, 0.207646, 0.25301, 0.324225, 0.440202, 0.632546", \ "0.130705, 0.201444, 0.232643, 0.278078, 0.349203, 0.465222, 0.657703", \ "0.145839, 0.216528, 0.247751, 0.293078, 0.364254, 0.480204, 0.672682", \ "0.167962, 0.238566, 0.269787, 0.315268, 0.386413, 0.502386, 0.694678", \ "0.198305, 0.268958, 0.300217, 0.34563, 0.416923, 0.532807, 0.725203", \ "0.239279, 0.310691, 0.342045, 0.387551, 0.458902, 0.574868, 0.767342", \ - "0.289657, 0.363744, 0.395375, 0.441008, 0.512441, 0.628463, 0.82093" \ + "0.289657, 0.363744, 0.395368, 0.441001, 0.512426, 0.628463, 0.82093" \ ); } fall_transition (TIMING_DELAY_7x7ds1) { index_1 ("0.0186, 0.0966, 0.174, 0.3294, 0.6408, 1.263, 2.5074"); index_2 ("0.001, 0.0468, 0.078, 0.1296, 0.216, 0.36, 0.6"); values ( \ - "0.024671, 0.0815627, 0.111576, 0.161958, 0.25063, 0.403755, 0.663636", \ + "0.024671, 0.0815627, 0.111576, 0.161958, 0.250621, 0.403756, 0.663636", \ "0.0246992, 0.0815817, 0.111615, 0.16207, 0.250656, 0.404057, 0.663637", \ "0.0247002, 0.0816099, 0.111616, 0.162071, 0.250657, 0.404058, 0.663655", \ "0.0247516, 0.0816109, 0.111772, 0.162072, 0.250658, 0.404059, 0.663656", \ "0.0253457, 0.0819657, 0.111945, 0.162139, 0.250723, 0.40406, 0.663657", \ "0.027466, 0.082993, 0.112733, 0.162596, 0.250984, 0.404229, 0.663858", \ - "0.031839, 0.085657, 0.114519, 0.163731, 0.251642, 0.404407, 0.663859" \ + "0.031839, 0.085657, 0.114524, 0.163754, 0.251639, 0.404407, 0.663859" \ ); } } timing () { related_pin : "CLK"; + sdf_edges : start_edge; timing_sense : non_unate; timing_type : rising_edge; cell_rise (TIMING_DELAY_7x7ds1) { index_1 ("0.0186, 0.0966, 0.174, 0.3294, 0.6408, 1.263, 2.5074"); index_2 ("0.001, 0.0468, 0.078, 0.1296, 0.216, 0.36, 0.6"); values ( \ - "0.094305, 0.15823, 0.191162, 0.243065, 0.328695, 0.471105, 0.708206", \ - "0.118923, 0.182846, 0.215758, 0.267608, 0.353313, 0.495703, 0.733527", \ + "0.0943031, 0.15823, 0.191147, 0.243067, 0.32872, 0.471105, 0.708206", \ + "0.119004, 0.182886, 0.215732, 0.267595, 0.353313, 0.495703, 0.733593", \ "0.133684, 0.197605, 0.230488, 0.282333, 0.368029, 0.510355, 0.747403", \ "0.154068, 0.218008, 0.250882, 0.302797, 0.388421, 0.530743, 0.767696", \ "0.181638, 0.245463, 0.27831, 0.330213, 0.415924, 0.558291, 0.795221", \ @@ -29653,70 +29766,71 @@ library (sg13g2_stdcell_typ_1p50V_25C) { index_1 ("0.0186, 0.0966, 0.174, 0.3294, 0.6408, 1.263, 2.5074"); index_2 ("0.001, 0.0468, 0.078, 0.1296, 0.216, 0.36, 0.6"); values ( \ - "0.0180196, 0.0847028, 0.127734, 0.200929, 0.326397, 0.537983, 0.89148", \ - "0.0180206, 0.0847059, 0.12774, 0.20093, 0.326511, 0.538019, 0.89222", \ - "0.0180216, 0.0847069, 0.127777, 0.200931, 0.326512, 0.538179, 0.892221", \ - "0.0180226, 0.0847186, 0.127778, 0.200932, 0.326513, 0.53818, 0.892222", \ - "0.0180236, 0.0847474, 0.127779, 0.200933, 0.326514, 0.538181, 0.892223", \ - "0.0180246, 0.0847484, 0.127785, 0.200934, 0.326515, 0.538182, 0.892224", \ - "0.0180256, 0.0847494, 0.127786, 0.200935, 0.326516, 0.538183, 0.892225" \ + "0.018019, 0.0847027, 0.12777, 0.200927, 0.326402, 0.537983, 0.89148", \ + "0.01802, 0.0847033, 0.127793, 0.200928, 0.326511, 0.538019, 0.892257", \ + "0.018021, 0.0847043, 0.127794, 0.200929, 0.326512, 0.538179, 0.892258", \ + "0.018022, 0.0847186, 0.127795, 0.20093, 0.326513, 0.53818, 0.892259", \ + "0.018023, 0.0847474, 0.127796, 0.200931, 0.326514, 0.538181, 0.89226", \ + "0.018024, 0.0847484, 0.127797, 0.200932, 0.326515, 0.538182, 0.892261", \ + "0.018025, 0.0847494, 0.127798, 0.200933, 0.326516, 0.538183, 0.892262" \ ); } cell_fall (TIMING_DELAY_7x7ds1) { index_1 ("0.0186, 0.0966, 0.174, 0.3294, 0.6408, 1.263, 2.5074"); index_2 ("0.001, 0.0468, 0.078, 0.1296, 0.216, 0.36, 0.6"); values ( \ - "0.105753, 0.176476, 0.207646, 0.253009, 0.324285, 0.440204, 0.632546", \ + "0.105753, 0.176476, 0.207646, 0.25301, 0.324225, 0.440202, 0.632546", \ "0.130705, 0.201444, 0.232643, 0.278078, 0.349203, 0.465222, 0.657703", \ "0.145839, 0.216528, 0.247751, 0.293078, 0.364254, 0.480204, 0.672682", \ "0.167962, 0.238566, 0.269787, 0.315268, 0.386413, 0.502386, 0.694678", \ "0.198305, 0.268958, 0.300217, 0.34563, 0.416923, 0.532807, 0.725203", \ "0.239279, 0.310691, 0.342045, 0.387551, 0.458902, 0.574868, 0.767342", \ - "0.289657, 0.363744, 0.395375, 0.441008, 0.512441, 0.628463, 0.82093" \ + "0.289657, 0.363744, 0.395368, 0.441001, 0.512426, 0.628463, 0.82093" \ ); } fall_transition (TIMING_DELAY_7x7ds1) { index_1 ("0.0186, 0.0966, 0.174, 0.3294, 0.6408, 1.263, 2.5074"); index_2 ("0.001, 0.0468, 0.078, 0.1296, 0.216, 0.36, 0.6"); values ( \ - "0.024671, 0.0815627, 0.111576, 0.161958, 0.25063, 0.403755, 0.663636", \ + "0.024671, 0.0815627, 0.111576, 0.161958, 0.250621, 0.403756, 0.663636", \ "0.0246992, 0.0815817, 0.111615, 0.16207, 0.250656, 0.404057, 0.663637", \ "0.0247002, 0.0816099, 0.111616, 0.162071, 0.250657, 0.404058, 0.663655", \ "0.0247516, 0.0816109, 0.111772, 0.162072, 0.250658, 0.404059, 0.663656", \ "0.0253457, 0.0819657, 0.111945, 0.162139, 0.250723, 0.40406, 0.663657", \ "0.027466, 0.082993, 0.112733, 0.162596, 0.250984, 0.404229, 0.663858", \ - "0.031839, 0.085657, 0.114519, 0.163731, 0.251642, 0.404407, 0.663859" \ + "0.031839, 0.085657, 0.114524, 0.163754, 0.251639, 0.404407, 0.663859" \ ); } } timing () { related_pin : "RESET_B"; + sdf_edges : start_edge; timing_sense : negative_unate; timing_type : preset; cell_rise (TIMING_DELAY_7x7ds1) { index_1 ("0.0186, 0.0966, 0.174, 0.3294, 0.6408, 1.263, 2.5074"); index_2 ("0.001, 0.0468, 0.078, 0.1296, 0.216, 0.36, 0.6"); values ( \ - "0.143739, 0.206145, 0.238827, 0.290626, 0.376314, 0.518725, 0.755715", \ + "0.143739, 0.206135, 0.238827, 0.290631, 0.376314, 0.518725, 0.755715", \ "0.178469, 0.240857, 0.273525, 0.325283, 0.411012, 0.553471, 0.790596", \ "0.204833, 0.26731, 0.299935, 0.351695, 0.437396, 0.579816, 0.816846", \ "0.243557, 0.306361, 0.338877, 0.390468, 0.476173, 0.618518, 0.855559", \ "0.300341, 0.363172, 0.395538, 0.447258, 0.532816, 0.675427, 0.912351", \ "0.379176, 0.441914, 0.474417, 0.526569, 0.61191, 0.754387, 0.991591", \ - "0.495753, 0.559222, 0.591016, 0.643628, 0.728964, 0.871004, 1.10875" \ + "0.495753, 0.559222, 0.591016, 0.643288, 0.728964, 0.871004, 1.10875" \ ); } rise_transition (TIMING_DELAY_7x7ds1) { index_1 ("0.0186, 0.0966, 0.174, 0.3294, 0.6408, 1.263, 2.5074"); index_2 ("0.001, 0.0468, 0.078, 0.1296, 0.216, 0.36, 0.6"); values ( \ - "0.0181039, 0.0835372, 0.126916, 0.200502, 0.326327, 0.537964, 0.89129", \ - "0.0181434, 0.0835382, 0.126919, 0.200503, 0.326328, 0.53797, 0.891334", \ - "0.0182235, 0.0835847, 0.126921, 0.200504, 0.326329, 0.53837, 0.891335", \ - "0.0184584, 0.0836762, 0.126974, 0.200505, 0.32633, 0.538371, 0.891336", \ - "0.0189367, 0.0838379, 0.127007, 0.200506, 0.326331, 0.538372, 0.891337", \ - "0.01959, 0.084215, 0.127291, 0.200651, 0.326332, 0.538373, 0.891338", \ - "0.020514, 0.084695, 0.12759, 0.200793, 0.326449, 0.538374, 0.891339" \ + "0.0181045, 0.0835355, 0.126916, 0.200503, 0.326324, 0.537964, 0.89129", \ + "0.0181434, 0.0835365, 0.126919, 0.200504, 0.326325, 0.53797, 0.891334", \ + "0.0182235, 0.0835847, 0.126921, 0.200505, 0.326326, 0.53837, 0.891335", \ + "0.0184584, 0.0836762, 0.126974, 0.200506, 0.326327, 0.538371, 0.891336", \ + "0.0189367, 0.0838379, 0.127007, 0.200507, 0.326328, 0.538372, 0.891337", \ + "0.01959, 0.084215, 0.127291, 0.200651, 0.326329, 0.538373, 0.891338", \ + "0.020514, 0.084695, 0.12759, 0.20077, 0.326449, 0.538374, 0.891339" \ ); } } @@ -29727,26 +29841,26 @@ library (sg13g2_stdcell_typ_1p50V_25C) { index_1 ("0.0186, 0.0966, 0.174, 0.3294, 0.6408, 1.263, 2.5074"); index_2 ("0.001, 0.0468, 0.078, 0.1296, 0.216, 0.36, 0.6"); values ( \ - "0.0618483, 0.11361, 0.148928, 0.20719, 0.30418, 0.465319, 0.734499", \ - "0.0622295, 0.114076, 0.149855, 0.207829, 0.304579, 0.465838, 0.735686", \ + "0.0618507, 0.11361, 0.148971, 0.207197, 0.304182, 0.465327, 0.734499", \ + "0.0622425, 0.114094, 0.149847, 0.2076, 0.304579, 0.465838, 0.735644", \ "0.0633559, 0.115175, 0.150472, 0.208867, 0.305589, 0.470443, 0.735609", \ - "0.0663055, 0.11825, 0.153736, 0.21185, 0.308854, 0.471614, 0.741511", \ + "0.0663055, 0.11825, 0.153736, 0.21185, 0.308854, 0.470622, 0.739429", \ "0.0725833, 0.124446, 0.159764, 0.218243, 0.315548, 0.476929, 0.747642", \ "0.086161, 0.13794, 0.173128, 0.231762, 0.328862, 0.491112, 0.759605", \ - "0.114166, 0.165623, 0.200909, 0.259316, 0.356241, 0.518627, 0.788384" \ + "0.114166, 0.165623, 0.200909, 0.259316, 0.356241, 0.518618, 0.788384" \ ); } fall_power (POWER_7x7ds1) { index_1 ("0.0186, 0.0966, 0.174, 0.3294, 0.6408, 1.263, 2.5074"); index_2 ("0.001, 0.0468, 0.078, 0.1296, 0.216, 0.36, 0.6"); values ( \ - "0.0643799, 0.113484, 0.148548, 0.206339, 0.30281, 0.463108, 0.730417", \ - "0.0646085, 0.113687, 0.149061, 0.206936, 0.303308, 0.46348, 0.730908", \ - "0.0655941, 0.114576, 0.149447, 0.20756, 0.306666, 0.464885, 0.731414", \ - "0.0683329, 0.117498, 0.152853, 0.211138, 0.306919, 0.468221, 0.734567", \ + "0.0643799, 0.113484, 0.148548, 0.206339, 0.302695, 0.463108, 0.730476", \ + "0.0646086, 0.113687, 0.149061, 0.206936, 0.303308, 0.46348, 0.730908", \ + "0.0655941, 0.114576, 0.149447, 0.20756, 0.306666, 0.464886, 0.731414", \ + "0.0683329, 0.117498, 0.152853, 0.211138, 0.306919, 0.468221, 0.734566", \ "0.0750593, 0.12368, 0.159067, 0.217474, 0.314832, 0.475684, 0.742115", \ "0.0893999, 0.137252, 0.172426, 0.230306, 0.327757, 0.490077, 0.759589", \ - "0.119267, 0.165671, 0.200466, 0.258573, 0.355845, 0.516905, 0.785034" \ + "0.119267, 0.165671, 0.200496, 0.258482, 0.355913, 0.516905, 0.785037" \ ); } } @@ -29756,26 +29870,26 @@ library (sg13g2_stdcell_typ_1p50V_25C) { index_1 ("0.0186, 0.0966, 0.174, 0.3294, 0.6408, 1.263, 2.5074"); index_2 ("0.001, 0.0468, 0.078, 0.1296, 0.216, 0.36, 0.6"); values ( \ - "0.0618483, 0.11361, 0.148928, 0.20719, 0.30418, 0.465319, 0.734499", \ - "0.0622295, 0.114076, 0.149855, 0.207829, 0.304579, 0.465838, 0.735686", \ + "0.0618507, 0.11361, 0.148971, 0.207197, 0.304182, 0.465327, 0.734499", \ + "0.0622425, 0.114094, 0.149847, 0.2076, 0.304579, 0.465838, 0.735644", \ "0.0633559, 0.115175, 0.150472, 0.208867, 0.305589, 0.470443, 0.735609", \ - "0.0663055, 0.11825, 0.153736, 0.21185, 0.308854, 0.471614, 0.741511", \ + "0.0663055, 0.11825, 0.153736, 0.21185, 0.308854, 0.470622, 0.739429", \ "0.0725833, 0.124446, 0.159764, 0.218243, 0.315548, 0.476929, 0.747642", \ "0.086161, 0.13794, 0.173128, 0.231762, 0.328862, 0.491112, 0.759605", \ - "0.114166, 0.165623, 0.200909, 0.259316, 0.356241, 0.518627, 0.788384" \ + "0.114166, 0.165623, 0.200909, 0.259316, 0.356241, 0.518618, 0.788384" \ ); } fall_power (POWER_7x7ds1) { index_1 ("0.0186, 0.0966, 0.174, 0.3294, 0.6408, 1.263, 2.5074"); index_2 ("0.001, 0.0468, 0.078, 0.1296, 0.216, 0.36, 0.6"); values ( \ - "0.0643799, 0.113484, 0.148548, 0.206339, 0.30281, 0.463108, 0.730417", \ - "0.0646085, 0.113687, 0.149061, 0.206936, 0.303308, 0.46348, 0.730908", \ - "0.0655941, 0.114576, 0.149447, 0.20756, 0.306666, 0.464885, 0.731414", \ - "0.0683329, 0.117498, 0.152853, 0.211138, 0.306919, 0.468221, 0.734567", \ + "0.0643799, 0.113484, 0.148548, 0.206339, 0.302695, 0.463108, 0.730476", \ + "0.0646086, 0.113687, 0.149061, 0.206936, 0.303308, 0.46348, 0.730908", \ + "0.0655941, 0.114576, 0.149447, 0.20756, 0.306666, 0.464886, 0.731414", \ + "0.0683329, 0.117498, 0.152853, 0.211138, 0.306919, 0.468221, 0.734566", \ "0.0750593, 0.12368, 0.159067, 0.217474, 0.314832, 0.475684, 0.742115", \ "0.0893999, 0.137252, 0.172426, 0.230306, 0.327757, 0.490077, 0.759589", \ - "0.119267, 0.165671, 0.200466, 0.258573, 0.355845, 0.516905, 0.785034" \ + "0.119267, 0.165671, 0.200496, 0.258482, 0.355913, 0.516905, 0.785037" \ ); } } @@ -29785,13 +29899,13 @@ library (sg13g2_stdcell_typ_1p50V_25C) { index_1 ("0.0186, 0.0966, 0.174, 0.3294, 0.6408, 1.263, 2.5074"); index_2 ("0.001, 0.0468, 0.078, 0.1296, 0.216, 0.36, 0.6"); values ( \ - "0.0649889, 0.122799, 0.161896, 0.223527, 0.320119, 0.471526, 0.715066", \ - "0.0649711, 0.123002, 0.162453, 0.226667, 0.327371, 0.485441, 0.735323", \ + "0.0649894, 0.122816, 0.161896, 0.22364, 0.320077, 0.471526, 0.715066", \ + "0.0649711, 0.123001, 0.162453, 0.226667, 0.327371, 0.485441, 0.735323", \ "0.0660542, 0.123784, 0.163414, 0.228286, 0.332657, 0.49533, 0.750504", \ - "0.0691972, 0.12679, 0.166139, 0.231054, 0.338678, 0.508253, 0.778464", \ + "0.0691972, 0.12679, 0.166139, 0.231054, 0.338678, 0.508176, 0.778464", \ "0.0762827, 0.133476, 0.172814, 0.237821, 0.346455, 0.523717, 0.807131", \ "0.0902027, 0.147281, 0.18639, 0.251537, 0.359874, 0.541153, 0.836591", \ - "0.118378, 0.174741, 0.213509, 0.278095, 0.386306, 0.567513, 0.868768" \ + "0.118378, 0.174741, 0.213509, 0.277937, 0.386306, 0.567513, 0.868768" \ ); } fall_power (scalar) { @@ -29806,10 +29920,10 @@ library (sg13g2_stdcell_typ_1p50V_25C) { direction : input; max_transition : 2.5074; capacitance : 0.00310262; - rise_capacitance : 0.00315601; - rise_capacitance_range (0.00315601, 0.00315601); + rise_capacitance : 0.00315602; + rise_capacitance_range (0.00280481, 0.00345398); fall_capacitance : 0.00303397; - fall_capacitance_range (0.00303397, 0.00303397); + fall_capacitance_range (0.00278256, 0.00324909); timing () { related_pin : "CLK"; timing_type : min_pulse_width; @@ -29825,13 +29939,13 @@ library (sg13g2_stdcell_typ_1p50V_25C) { rise_power (passive_POWER_7x1ds1) { index_1 ("0.0186, 0.0966, 0.174, 0.3294, 0.6408, 1.263, 2.5074"); values ( \ - "0.0167937, 0.0171211, 0.0179933, 0.0208417, 0.0267635, 0.0400181, 0.0672459" \ + "0.0167935, 0.0171211, 0.0179933, 0.0208416, 0.0267635, 0.0400181, 0.0672459" \ ); } fall_power (passive_POWER_7x1ds1) { index_1 ("0.0186, 0.0966, 0.174, 0.3294, 0.6408, 1.263, 2.5074"); values ( \ - "0.0164629, 0.0168711, 0.0182159, 0.0209982, 0.0274951, 0.0407619, 0.0688861" \ + "0.0164629, 0.0168711, 0.0182159, 0.0209982, 0.027495, 0.0407619, 0.0688861" \ ); } } @@ -29845,7 +29959,7 @@ library (sg13g2_stdcell_typ_1p50V_25C) { fall_power (passive_POWER_7x1ds1) { index_1 ("0.0186, 0.0966, 0.174, 0.3294, 0.6408, 1.263, 2.5074"); values ( \ - "0.0325146, 0.0328477, 0.0342451, 0.0371193, 0.043921, 0.0575532, 0.0866537" \ + "0.0325192, 0.0328477, 0.0342451, 0.0371193, 0.043921, 0.0575532, 0.0866537" \ ); } } @@ -29868,7 +29982,7 @@ library (sg13g2_stdcell_typ_1p50V_25C) { rise_power (passive_POWER_7x1ds1) { index_1 ("0.0186, 0.0966, 0.174, 0.3294, 0.6408, 1.263, 2.5074"); values ( \ - "0.0164069, 0.016711, 0.0175944, 0.0204332, 0.0263541, 0.0395231, 0.0667441" \ + "0.016407, 0.016711, 0.0175944, 0.0204332, 0.0263541, 0.0395232, 0.0667441" \ ); } fall_power (passive_POWER_7x1ds1) { @@ -29883,13 +29997,13 @@ library (sg13g2_stdcell_typ_1p50V_25C) { rise_power (passive_POWER_7x1ds1) { index_1 ("0.0186, 0.0966, 0.174, 0.3294, 0.6408, 1.263, 2.5074"); values ( \ - "0.016799, 0.0171279, 0.0179933, 0.0208418, 0.0267635, 0.0400183, 0.0672462" \ + "0.016794, 0.0171278, 0.0179933, 0.0208418, 0.0267635, 0.0400182, 0.0672461" \ ); } fall_power (passive_POWER_7x1ds1) { index_1 ("0.0186, 0.0966, 0.174, 0.3294, 0.6408, 1.263, 2.5074"); values ( \ - "0.016463, 0.0168829, 0.0182159, 0.0209983, 0.0274951, 0.0407619, 0.0688861" \ + "0.0164628, 0.0168829, 0.0182159, 0.0209983, 0.027495, 0.0407619, 0.068886" \ ); } } @@ -29898,13 +30012,13 @@ library (sg13g2_stdcell_typ_1p50V_25C) { rise_power (passive_POWER_7x1ds1) { index_1 ("0.0186, 0.0966, 0.174, 0.3294, 0.6408, 1.263, 2.5074"); values ( \ - "0.0144319, 0.0147444, 0.0156425, 0.0184374, 0.0243437, 0.0375297, 0.0647111" \ + "0.0144335, 0.0147444, 0.0156425, 0.0184374, 0.0243436, 0.0375297, 0.0647114" \ ); } fall_power (passive_POWER_7x1ds1) { index_1 ("0.0186, 0.0966, 0.174, 0.3294, 0.6408, 1.263, 2.5074"); values ( \ - "0.0131271, 0.0135678, 0.0148162, 0.0176659, 0.0241502, 0.0373904, 0.0654277" \ + "0.0131272, 0.0135678, 0.0148162, 0.0176659, 0.0241502, 0.0373904, 0.0654277" \ ); } } @@ -29913,7 +30027,7 @@ library (sg13g2_stdcell_typ_1p50V_25C) { rise_power (passive_POWER_7x1ds1) { index_1 ("0.0186, 0.0966, 0.174, 0.3294, 0.6408, 1.263, 2.5074"); values ( \ - "0.0163935, 0.0167084, 0.017595, 0.0204338, 0.0263547, 0.0395237, 0.0667445" \ + "0.0163933, 0.0167085, 0.017595, 0.0204339, 0.0263547, 0.0395237, 0.0667446" \ ); } fall_power (passive_POWER_7x1ds1) { @@ -29927,7 +30041,7 @@ library (sg13g2_stdcell_typ_1p50V_25C) { rise_power (passive_POWER_7x1ds1) { index_1 ("0.0186, 0.0966, 0.174, 0.3294, 0.6408, 1.263, 2.5074"); values ( \ - "0.0163935, 0.0167084, 0.017595, 0.0204338, 0.0263547, 0.0395237, 0.0667445" \ + "0.0163933, 0.0167085, 0.017595, 0.0204339, 0.0263547, 0.0395237, 0.0667446" \ ); } fall_power (passive_POWER_7x1ds1) { @@ -29944,11 +30058,12 @@ library (sg13g2_stdcell_typ_1p50V_25C) { max_transition : 2.5074; capacitance : 0.00290924; rise_capacitance : 0.00297998; - rise_capacitance_range (0.00297998, 0.00297998); + rise_capacitance_range (0.00251968, 0.00336498); fall_capacitance : 0.00283849; - fall_capacitance_range (0.00283849, 0.00283849); + fall_capacitance_range (0.00251289, 0.00301174); timing () { related_pin : "CLK"; + sdf_edges : both_edges; timing_type : hold_rising; rise_constraint (CONSTRAINT_4x4) { index_1 ("0.0186, 0.51636, 1.263, 2.5074"); @@ -29973,6 +30088,7 @@ library (sg13g2_stdcell_typ_1p50V_25C) { } timing () { related_pin : "CLK"; + sdf_edges : both_edges; timing_type : setup_rising; rise_constraint (CONSTRAINT_4x4) { index_1 ("0.0186, 0.51636, 1.263, 2.5074"); @@ -30000,13 +30116,13 @@ library (sg13g2_stdcell_typ_1p50V_25C) { rise_power (passive_POWER_7x1ds1) { index_1 ("0.0186, 0.0966, 0.174, 0.3294, 0.6408, 1.263, 2.5074"); values ( \ - "0.0326246, 0.0326117, 0.0333899, 0.0353497, 0.0399159, 0.0505277, 0.0714183" \ + "0.0326245, 0.0326117, 0.0333899, 0.0353496, 0.0399159, 0.0505277, 0.0714183" \ ); } fall_power (passive_POWER_7x1ds1) { index_1 ("0.0186, 0.0966, 0.174, 0.3294, 0.6408, 1.263, 2.5074"); values ( \ - "0.0328884, 0.0332613, 0.0344132, 0.0368184, 0.0423003, 0.0530367, 0.0754086" \ + "0.032889, 0.0332613, 0.0344132, 0.0368184, 0.0423003, 0.0530367, 0.0754086" \ ); } } @@ -30014,13 +30130,13 @@ library (sg13g2_stdcell_typ_1p50V_25C) { rise_power (passive_POWER_7x1ds1) { index_1 ("0.0186, 0.0966, 0.174, 0.3294, 0.6408, 1.263, 2.5074"); values ( \ - "0.0326246, 0.0326117, 0.0333899, 0.0353497, 0.0399159, 0.0505277, 0.0714183" \ + "0.0326245, 0.0326117, 0.0333899, 0.0353496, 0.0399159, 0.0505277, 0.0714183" \ ); } fall_power (passive_POWER_7x1ds1) { index_1 ("0.0186, 0.0966, 0.174, 0.3294, 0.6408, 1.263, 2.5074"); values ( \ - "0.0328884, 0.0332613, 0.0344132, 0.0368184, 0.0423003, 0.0530367, 0.0754086" \ + "0.032889, 0.0332613, 0.0344132, 0.0368184, 0.0423003, 0.0530367, 0.0754086" \ ); } } @@ -30028,13 +30144,14 @@ library (sg13g2_stdcell_typ_1p50V_25C) { pin (RESET_B) { direction : input; max_transition : 2.5074; - capacitance : 0.00527855; - rise_capacitance : 0.00527855; - rise_capacitance_range (0.00527855, 0.00527855); - fall_capacitance : 0.00527855; - fall_capacitance_range (0.00527855, 0.00527855); + capacitance : 0.00527856; + rise_capacitance : 0.00527856; + rise_capacitance_range (0.00527856, 0.00527856); + fall_capacitance : 0.00527856; + fall_capacitance_range (0.00492265, 0.00548594); timing () { related_pin : "CLK"; + sdf_edges : both_edges; timing_type : recovery_rising; rise_constraint (CONSTRAINT_4x4) { index_1 ("0.0186, 0.51636, 1.263, 2.5074"); @@ -30049,6 +30166,7 @@ library (sg13g2_stdcell_typ_1p50V_25C) { } timing () { related_pin : "CLK"; + sdf_edges : both_edges; timing_type : removal_rising; rise_constraint (CONSTRAINT_4x4) { index_1 ("0.0186, 0.51636, 1.263, 2.5074"); @@ -30078,11 +30196,12 @@ library (sg13g2_stdcell_typ_1p50V_25C) { max_transition : 2.5074; capacitance : 0.00303546; rise_capacitance : 0.00308225; - rise_capacitance_range (0.00308225, 0.00308225); + rise_capacitance_range (0.00262515, 0.00346356); fall_capacitance : 0.00294186; - fall_capacitance_range (0.00294186, 0.00294186); + fall_capacitance_range (0.00262058, 0.003114); timing () { related_pin : "CLK"; + sdf_edges : both_edges; timing_type : hold_rising; rise_constraint (CONSTRAINT_4x4) { index_1 ("0.0186, 0.51636, 1.263, 2.5074"); @@ -30107,6 +30226,7 @@ library (sg13g2_stdcell_typ_1p50V_25C) { } timing () { related_pin : "CLK"; + sdf_edges : both_edges; timing_type : setup_rising; rise_constraint (CONSTRAINT_4x4) { index_1 ("0.0186, 0.51636, 1.263, 2.5074"); @@ -30140,7 +30260,7 @@ library (sg13g2_stdcell_typ_1p50V_25C) { fall_power (passive_POWER_7x1ds1) { index_1 ("0.0186, 0.0966, 0.174, 0.3294, 0.6408, 1.263, 2.5074"); values ( \ - "0.0281104, 0.0284626, 0.0296025, 0.0320356, 0.0375547, 0.0483345, 0.0707787" \ + "0.0280641, 0.0284626, 0.0296025, 0.0320356, 0.0375547, 0.0483345, 0.0707787" \ ); } } @@ -30154,7 +30274,7 @@ library (sg13g2_stdcell_typ_1p50V_25C) { fall_power (passive_POWER_7x1ds1) { index_1 ("0.0186, 0.0966, 0.174, 0.3294, 0.6408, 1.263, 2.5074"); values ( \ - "0.0281104, 0.0284626, 0.0296025, 0.0320356, 0.0375547, 0.0483345, 0.0707787" \ + "0.0280641, 0.0284626, 0.0296025, 0.0320356, 0.0375547, 0.0483345, 0.0707787" \ ); } } @@ -30165,11 +30285,12 @@ library (sg13g2_stdcell_typ_1p50V_25C) { max_transition : 2.5074; capacitance : 0.00516344; rise_capacitance : 0.00547336; - rise_capacitance_range (0.00547336, 0.00547336); + rise_capacitance_range (0.00459804, 0.0060822); fall_capacitance : 0.00485352; - fall_capacitance_range (0.00485352, 0.00485352); + fall_capacitance_range (0.00462977, 0.00534706); timing () { related_pin : "CLK"; + sdf_edges : both_edges; timing_type : hold_rising; rise_constraint (CONSTRAINT_4x4) { index_1 ("0.0186, 0.51636, 1.263, 2.5074"); @@ -30194,6 +30315,7 @@ library (sg13g2_stdcell_typ_1p50V_25C) { } timing () { related_pin : "CLK"; + sdf_edges : both_edges; timing_type : setup_rising; rise_constraint (CONSTRAINT_4x4) { index_1 ("0.0186, 0.51636, 1.263, 2.5074"); @@ -30221,13 +30343,13 @@ library (sg13g2_stdcell_typ_1p50V_25C) { rise_power (passive_POWER_7x1ds1) { index_1 ("0.0186, 0.0966, 0.174, 0.3294, 0.6408, 1.263, 2.5074"); values ( \ - "0.0357484, 0.0357965, 0.0365829, 0.0383618, 0.0425851, 0.0517548, 0.0709777" \ + "0.0358027, 0.0357965, 0.0365829, 0.0383618, 0.0425851, 0.0517548, 0.0709777" \ ); } fall_power (passive_POWER_7x1ds1) { index_1 ("0.0186, 0.0966, 0.174, 0.3294, 0.6408, 1.263, 2.5074"); values ( \ - "0.0407785, 0.041044, 0.0418789, 0.0438742, 0.0482618, 0.0578079, 0.077525" \ + "0.0407785, 0.041044, 0.0418788, 0.0438742, 0.0482618, 0.0578078, 0.077525" \ ); } } @@ -30242,7 +30364,7 @@ library (sg13g2_stdcell_typ_1p50V_25C) { fall_power (passive_POWER_7x1ds1) { index_1 ("0.0186, 0.0966, 0.174, 0.3294, 0.6408, 1.263, 2.5074"); values ( \ - "0.0505254, 0.0650603, 0.0669732, 0.0709865, 0.0801978, 0.0996529, 0.139952" \ + "0.0505277, 0.0650603, 0.0669732, 0.0709865, 0.0801978, 0.0996529, 0.139952" \ ); } } @@ -30256,15 +30378,15 @@ library (sg13g2_stdcell_typ_1p50V_25C) { fall_power (passive_POWER_7x1ds1) { index_1 ("0.0186, 0.0966, 0.174, 0.3294, 0.6408, 1.263, 2.5074"); values ( \ - "0.0505254, 0.0650603, 0.0669732, 0.0709865, 0.0801978, 0.0996529, 0.139952" \ + "0.0505277, 0.0650603, 0.0669732, 0.0709865, 0.0801978, 0.0996529, 0.139952" \ ); } } } ff (IQ,IQN) { - clear : "RESET_B'"; + clear : "!RESET_B"; clocked_on : "CLK"; - next_state : "(SCE*SCD)+(SCE'*D)"; + next_state : "(SCE*SCD)+(!SCE*D)"; } test_cell () { pin (Q) { @@ -30295,7 +30417,7 @@ library (sg13g2_stdcell_typ_1p50V_25C) { signal_type : test_scan_enable; } ff (IQ,IQN) { - clear : "RESET_B'"; + clear : "!RESET_B"; clocked_on : "CLK"; next_state : "D"; } @@ -30381,6 +30503,7 @@ library (sg13g2_stdcell_typ_1p50V_25C) { timing () { related_pin : "CLK"; sdf_cond : "SCE == 1'b1"; + sdf_edges : start_edge; timing_sense : non_unate; timing_type : rising_edge; when : "SCE"; @@ -30440,6 +30563,7 @@ library (sg13g2_stdcell_typ_1p50V_25C) { timing () { related_pin : "CLK"; sdf_cond : "SCE == 1'b0"; + sdf_edges : start_edge; timing_sense : non_unate; timing_type : rising_edge; when : "!SCE"; @@ -30498,6 +30622,7 @@ library (sg13g2_stdcell_typ_1p50V_25C) { } timing () { related_pin : "CLK"; + sdf_edges : start_edge; timing_sense : non_unate; timing_type : rising_edge; cell_rise (TIMING_DELAY_7x7ds1) { @@ -30555,6 +30680,7 @@ library (sg13g2_stdcell_typ_1p50V_25C) { } timing () { related_pin : "RESET_B"; + sdf_edges : start_edge; timing_sense : positive_unate; timing_type : clear; cell_fall (TIMING_DELAY_7x7ds1) { @@ -30701,9 +30827,9 @@ library (sg13g2_stdcell_typ_1p50V_25C) { max_transition : 2.5074; capacitance : 0.00310285; rise_capacitance : 0.00315635; - rise_capacitance_range (0.00315635, 0.00315635); + rise_capacitance_range (0.00280617, 0.0034541); fall_capacitance : 0.00303405; - fall_capacitance_range (0.00303405, 0.00303405); + fall_capacitance_range (0.00278151, 0.00324897); timing () { related_pin : "CLK"; timing_type : min_pulse_width; @@ -30844,11 +30970,12 @@ library (sg13g2_stdcell_typ_1p50V_25C) { max_transition : 2.5074; capacitance : 0.00291165; rise_capacitance : 0.00298234; - rise_capacitance_range (0.00298234, 0.00298234); + rise_capacitance_range (0.00252241, 0.0033674); fall_capacitance : 0.00284096; - fall_capacitance_range (0.00284096, 0.00284096); + fall_capacitance_range (0.00251706, 0.00301406); timing () { related_pin : "CLK"; + sdf_edges : both_edges; timing_type : hold_rising; rise_constraint (CONSTRAINT_4x4) { index_1 ("0.0186, 0.51636, 1.263, 2.5074"); @@ -30873,6 +31000,7 @@ library (sg13g2_stdcell_typ_1p50V_25C) { } timing () { related_pin : "CLK"; + sdf_edges : both_edges; timing_type : setup_rising; rise_constraint (CONSTRAINT_4x4) { index_1 ("0.0186, 0.51636, 1.263, 2.5074"); @@ -30932,9 +31060,10 @@ library (sg13g2_stdcell_typ_1p50V_25C) { rise_capacitance : 0.00528703; rise_capacitance_range (0.00528703, 0.00528703); fall_capacitance : 0.00528703; - fall_capacitance_range (0.00528703, 0.00528703); + fall_capacitance_range (0.00492703, 0.00555836); timing () { related_pin : "CLK"; + sdf_edges : both_edges; timing_type : recovery_rising; rise_constraint (CONSTRAINT_4x4) { index_1 ("0.0186, 0.51636, 1.263, 2.5074"); @@ -30949,6 +31078,7 @@ library (sg13g2_stdcell_typ_1p50V_25C) { } timing () { related_pin : "CLK"; + sdf_edges : both_edges; timing_type : removal_rising; rise_constraint (CONSTRAINT_4x4) { index_1 ("0.0186, 0.51636, 1.263, 2.5074"); @@ -30978,11 +31108,12 @@ library (sg13g2_stdcell_typ_1p50V_25C) { max_transition : 2.5074; capacitance : 0.00303769; rise_capacitance : 0.00308451; - rise_capacitance_range (0.00308451, 0.00308451); + rise_capacitance_range (0.00262759, 0.00346595); fall_capacitance : 0.00294406; - fall_capacitance_range (0.00294406, 0.00294406); + fall_capacitance_range (0.00262214, 0.00311629); timing () { related_pin : "CLK"; + sdf_edges : both_edges; timing_type : hold_rising; rise_constraint (CONSTRAINT_4x4) { index_1 ("0.0186, 0.51636, 1.263, 2.5074"); @@ -31007,6 +31138,7 @@ library (sg13g2_stdcell_typ_1p50V_25C) { } timing () { related_pin : "CLK"; + sdf_edges : both_edges; timing_type : setup_rising; rise_constraint (CONSTRAINT_4x4) { index_1 ("0.0186, 0.51636, 1.263, 2.5074"); @@ -31065,11 +31197,12 @@ library (sg13g2_stdcell_typ_1p50V_25C) { max_transition : 2.5074; capacitance : 0.00516336; rise_capacitance : 0.00547347; - rise_capacitance_range (0.00547347, 0.00547347); + rise_capacitance_range (0.00459873, 0.00608228); fall_capacitance : 0.00485324; - fall_capacitance_range (0.00485324, 0.00485324); + fall_capacitance_range (0.00462954, 0.00534699); timing () { related_pin : "CLK"; + sdf_edges : both_edges; timing_type : hold_rising; rise_constraint (CONSTRAINT_4x4) { index_1 ("0.0186, 0.51636, 1.263, 2.5074"); @@ -31094,6 +31227,7 @@ library (sg13g2_stdcell_typ_1p50V_25C) { } timing () { related_pin : "CLK"; + sdf_edges : both_edges; timing_type : setup_rising; rise_constraint (CONSTRAINT_4x4) { index_1 ("0.0186, 0.51636, 1.263, 2.5074"); @@ -31162,9 +31296,9 @@ library (sg13g2_stdcell_typ_1p50V_25C) { } } ff (IQ,IQN) { - clear : "RESET_B'"; + clear : "!RESET_B"; clocked_on : "CLK"; - next_state : "(SCE*SCD)+(SCE'*D)"; + next_state : "(SCE*SCD)+(!SCE*D)"; } test_cell () { pin (Q) { @@ -31190,7 +31324,7 @@ library (sg13g2_stdcell_typ_1p50V_25C) { signal_type : test_scan_enable; } ff (IQ,IQN) { - clear : "RESET_B'"; + clear : "!RESET_B"; clocked_on : "CLK"; next_state : "D"; } @@ -31276,6 +31410,7 @@ library (sg13g2_stdcell_typ_1p50V_25C) { timing () { related_pin : "CLK"; sdf_cond : "SCE == 1'b1"; + sdf_edges : start_edge; timing_sense : non_unate; timing_type : rising_edge; when : "SCE"; @@ -31335,6 +31470,7 @@ library (sg13g2_stdcell_typ_1p50V_25C) { timing () { related_pin : "CLK"; sdf_cond : "SCE == 1'b0"; + sdf_edges : start_edge; timing_sense : non_unate; timing_type : rising_edge; when : "!SCE"; @@ -31393,6 +31529,7 @@ library (sg13g2_stdcell_typ_1p50V_25C) { } timing () { related_pin : "CLK"; + sdf_edges : start_edge; timing_sense : non_unate; timing_type : rising_edge; cell_rise (TIMING_DELAY_7x7ds1) { @@ -31450,6 +31587,7 @@ library (sg13g2_stdcell_typ_1p50V_25C) { } timing () { related_pin : "RESET_B"; + sdf_edges : start_edge; timing_sense : positive_unate; timing_type : clear; cell_fall (TIMING_DELAY_7x7ds1) { @@ -31596,9 +31734,9 @@ library (sg13g2_stdcell_typ_1p50V_25C) { max_transition : 2.5074; capacitance : 0.00310277; rise_capacitance : 0.00315637; - rise_capacitance_range (0.00315637, 0.00315637); + rise_capacitance_range (0.00280617, 0.00345409); fall_capacitance : 0.00303385; - fall_capacitance_range (0.00303385, 0.00303385); + fall_capacitance_range (0.00278147, 0.00324897); timing () { related_pin : "CLK"; timing_type : min_pulse_width; @@ -31739,11 +31877,12 @@ library (sg13g2_stdcell_typ_1p50V_25C) { max_transition : 2.5074; capacitance : 0.00290937; rise_capacitance : 0.0029801; - rise_capacitance_range (0.0029801, 0.0029801); + rise_capacitance_range (0.00252078, 0.00336506); fall_capacitance : 0.00283864; - fall_capacitance_range (0.00283864, 0.00283864); + fall_capacitance_range (0.00251434, 0.00301172); timing () { related_pin : "CLK"; + sdf_edges : both_edges; timing_type : hold_rising; rise_constraint (CONSTRAINT_4x4) { index_1 ("0.0186, 0.51636, 1.263, 2.5074"); @@ -31768,6 +31907,7 @@ library (sg13g2_stdcell_typ_1p50V_25C) { } timing () { related_pin : "CLK"; + sdf_edges : both_edges; timing_type : setup_rising; rise_constraint (CONSTRAINT_4x4) { index_1 ("0.0186, 0.51636, 1.263, 2.5074"); @@ -31827,9 +31967,10 @@ library (sg13g2_stdcell_typ_1p50V_25C) { rise_capacitance : 0.00529469; rise_capacitance_range (0.00529469, 0.00529469); fall_capacitance : 0.00529469; - fall_capacitance_range (0.00529469, 0.00529469); + fall_capacitance_range (0.00494037, 0.00556422); timing () { related_pin : "CLK"; + sdf_edges : both_edges; timing_type : recovery_rising; rise_constraint (CONSTRAINT_4x4) { index_1 ("0.0186, 0.51636, 1.263, 2.5074"); @@ -31844,6 +31985,7 @@ library (sg13g2_stdcell_typ_1p50V_25C) { } timing () { related_pin : "CLK"; + sdf_edges : both_edges; timing_type : removal_rising; rise_constraint (CONSTRAINT_4x4) { index_1 ("0.0186, 0.51636, 1.263, 2.5074"); @@ -31873,11 +32015,12 @@ library (sg13g2_stdcell_typ_1p50V_25C) { max_transition : 2.5074; capacitance : 0.00303624; rise_capacitance : 0.00308301; - rise_capacitance_range (0.00308301, 0.00308301); + rise_capacitance_range (0.00262659, 0.00346451); fall_capacitance : 0.00294269; - fall_capacitance_range (0.00294269, 0.00294269); + fall_capacitance_range (0.00262118, 0.00311485); timing () { related_pin : "CLK"; + sdf_edges : both_edges; timing_type : hold_rising; rise_constraint (CONSTRAINT_4x4) { index_1 ("0.0186, 0.51636, 1.263, 2.5074"); @@ -31902,6 +32045,7 @@ library (sg13g2_stdcell_typ_1p50V_25C) { } timing () { related_pin : "CLK"; + sdf_edges : both_edges; timing_type : setup_rising; rise_constraint (CONSTRAINT_4x4) { index_1 ("0.0186, 0.51636, 1.263, 2.5074"); @@ -31960,11 +32104,12 @@ library (sg13g2_stdcell_typ_1p50V_25C) { max_transition : 2.5074; capacitance : 0.0051634; rise_capacitance : 0.00547347; - rise_capacitance_range (0.00547347, 0.00547347); + rise_capacitance_range (0.00459873, 0.00608228); fall_capacitance : 0.00485334; - fall_capacitance_range (0.00485334, 0.00485334); + fall_capacitance_range (0.00462954, 0.00534699); timing () { related_pin : "CLK"; + sdf_edges : both_edges; timing_type : hold_rising; rise_constraint (CONSTRAINT_4x4) { index_1 ("0.0186, 0.51636, 1.263, 2.5074"); @@ -31989,6 +32134,7 @@ library (sg13g2_stdcell_typ_1p50V_25C) { } timing () { related_pin : "CLK"; + sdf_edges : both_edges; timing_type : setup_rising; rise_constraint (CONSTRAINT_4x4) { index_1 ("0.0186, 0.51636, 1.263, 2.5074"); @@ -32057,9 +32203,9 @@ library (sg13g2_stdcell_typ_1p50V_25C) { } } ff (IQ,IQN) { - clear : "RESET_B'"; + clear : "!RESET_B"; clocked_on : "CLK"; - next_state : "(SCE*SCD)+(SCE'*D)"; + next_state : "(SCE*SCD)+(!SCE*D)"; } test_cell () { pin (Q) { @@ -32085,7 +32231,7 @@ library (sg13g2_stdcell_typ_1p50V_25C) { signal_type : test_scan_enable; } ff (IQ,IQN) { - clear : "RESET_B'"; + clear : "!RESET_B"; clocked_on : "CLK"; next_state : "D"; } @@ -32093,7 +32239,7 @@ library (sg13g2_stdcell_typ_1p50V_25C) { } cell (sg13g2_sighold) { area : 9.072; - cell_footprint : "keepstate"; + cell_footprint : "sighold"; cell_leakage_power : 528.879; dont_touch : true; dont_use : true; @@ -32131,7 +32277,7 @@ library (sg13g2_stdcell_typ_1p50V_25C) { } cell (sg13g2_slgcp_1) { area : 30.8448; - cell_footprint : "sgclk"; + cell_footprint : "slgcp"; cell_leakage_power : 1198.65; clock_gating_integrated_cell : "latch_posedge_precontrol"; dont_touch : true; @@ -32270,9 +32416,9 @@ library (sg13g2_stdcell_typ_1p50V_25C) { max_transition : 2.5074; capacitance : 0.0052854; rise_capacitance : 0.00543452; - rise_capacitance_range (0.00543452, 0.00543452); + rise_capacitance_range (0.00454243, 0.00626926); fall_capacitance : 0.00513628; - fall_capacitance_range (0.00513628, 0.00513628); + fall_capacitance_range (0.00472807, 0.00541883); timing () { related_pin : "CLK"; timing_type : min_pulse_width; @@ -32310,11 +32456,12 @@ library (sg13g2_stdcell_typ_1p50V_25C) { max_transition : 2.5074; capacitance : 0.00203687; rise_capacitance : 0.00250321; - rise_capacitance_range (0.00250321, 0.00250321); + rise_capacitance_range (0.0022492, 0.00278817); fall_capacitance : 0.00157053; - fall_capacitance_range (0.00157053, 0.00157053); + fall_capacitance_range (0.00157053, 0.00244071); timing () { related_pin : "CLK"; + sdf_edges : both_edges; timing_type : hold_rising; rise_constraint (CONSTRAINT_4x4) { index_1 ("0.0186, 0.51636, 1.263, 2.5074"); @@ -32339,6 +32486,7 @@ library (sg13g2_stdcell_typ_1p50V_25C) { } timing () { related_pin : "CLK"; + sdf_edges : both_edges; timing_type : setup_rising; rise_constraint (CONSTRAINT_4x4) { index_1 ("0.0186, 0.51636, 1.263, 2.5074"); @@ -32397,11 +32545,12 @@ library (sg13g2_stdcell_typ_1p50V_25C) { max_transition : 2.5074; capacitance : 0.00246049; rise_capacitance : 0.00240586; - rise_capacitance_range (0.00240586, 0.00240586); + rise_capacitance_range (0.00219546, 0.00259776); fall_capacitance : 0.00251511; - fall_capacitance_range (0.00251511, 0.00251511); + fall_capacitance_range (0.00230717, 0.00265307); timing () { related_pin : "CLK"; + sdf_edges : both_edges; timing_type : hold_rising; rise_constraint (CONSTRAINT_4x4) { index_1 ("0.0186, 0.51636, 1.263, 2.5074"); @@ -32426,6 +32575,7 @@ library (sg13g2_stdcell_typ_1p50V_25C) { } timing () { related_pin : "CLK"; + sdf_edges : both_edges; timing_type : setup_rising; rise_constraint (CONSTRAINT_4x4) { index_1 ("0.0186, 0.51636, 1.263, 2.5074"); @@ -32466,7 +32616,7 @@ library (sg13g2_stdcell_typ_1p50V_25C) { } cell (sg13g2_tiehi) { area : 7.2576; - cell_footprint : "tie1"; + cell_footprint : "tiehi"; cell_leakage_power : 238.392; pin (L_HI) { direction : "output"; @@ -32476,7 +32626,7 @@ library (sg13g2_stdcell_typ_1p50V_25C) { } cell (sg13g2_tielo) { area : 7.2576; - cell_footprint : "tie0"; + cell_footprint : "tielo"; cell_leakage_power : 266.161; pin (L_LO) { direction : "output"; @@ -32486,7 +32636,7 @@ library (sg13g2_stdcell_typ_1p50V_25C) { } cell (sg13g2_xnor2_1) { area : 14.5152; - cell_footprint : "xnor2_1"; + cell_footprint : "xnor2"; cell_leakage_power : 577.483; leakage_power () { value : 766.942; @@ -33043,23 +33193,23 @@ library (sg13g2_stdcell_typ_1p50V_25C) { max_transition : 2.5074; capacitance : 0.00600709; rise_capacitance : 0.00603489; - rise_capacitance_range (0.00603489, 0.00603489); + rise_capacitance_range (0.00502943, 0.00699647); fall_capacitance : 0.00597929; - fall_capacitance_range (0.00597929, 0.00597929); + fall_capacitance_range (0.00503628, 0.00672654); } pin (B) { direction : "input"; max_transition : 2.5074; capacitance : 0.00531674; rise_capacitance : 0.00535358; - rise_capacitance_range (0.00535358, 0.00535358); + rise_capacitance_range (0.00466346, 0.00625812); fall_capacitance : 0.0052799; - fall_capacitance_range (0.0052799, 0.0052799); + fall_capacitance_range (0.00458098, 0.00602053); } } cell (sg13g2_xor2_1) { area : 14.5152; - cell_footprint : "xor2_1"; + cell_footprint : "xor2"; cell_leakage_power : 522.927; leakage_power () { value : 513.943; @@ -33616,18 +33766,18 @@ library (sg13g2_stdcell_typ_1p50V_25C) { max_transition : 2.5074; capacitance : 0.00613186; rise_capacitance : 0.00616484; - rise_capacitance_range (0.00616484, 0.00616484); + rise_capacitance_range (0.00520069, 0.00690663); fall_capacitance : 0.00609887; - fall_capacitance_range (0.00609887, 0.00609887); + fall_capacitance_range (0.00502883, 0.00710079); } pin (B) { direction : "input"; max_transition : 2.5074; capacitance : 0.00535559; rise_capacitance : 0.00542781; - rise_capacitance_range (0.00542781, 0.00542781); + rise_capacitance_range (0.00462032, 0.00633481); fall_capacitance : 0.00528337; - fall_capacitance_range (0.00528337, 0.00528337); + fall_capacitance_range (0.00473493, 0.00588322); } } } diff --git a/flow/platforms/ihp-sg13g2/sg13g2.lyp b/flow/platforms/ihp-sg13g2/sg13g2.lyp index f8cf82dc69..ca05ff0162 100644 --- a/flow/platforms/ihp-sg13g2/sg13g2.lyp +++ b/flow/platforms/ihp-sg13g2/sg13g2.lyp @@ -559,6 +559,22 @@ NWell.boundary 31/4 + + #268c6b + #268c6b + 0 + 0 + C9 + C1 + false + true + false + 1 + false + 0 + NWell.text + 31/25 + #8c8ca6 #8c8ca6 diff --git a/flow/platforms/ihp-sg13g2/sg13g2.lyt b/flow/platforms/ihp-sg13g2/sg13g2.lyt index 488e57bfcb..99a11febec 100644 --- a/flow/platforms/ihp-sg13g2/sg13g2.lyt +++ b/flow/platforms/ihp-sg13g2/sg13g2.lyt @@ -177,7 +177,7 @@ Metal5,TopVia1,TopMetal1 TopMetal1,TopVia2,TopMetal2 SalBlock='28/0' - Activ='1/0-Salblock' + Activ='1/0-SalBlock' GatPoly='5/0-SalBlock' Diff='Activ-GatPoly' Cont='6/0' diff --git a/flow/platforms/ihp-sg13g2/verilog/RM_IHPSG13_1P_1024x32_c2_bm_bist.v b/flow/platforms/ihp-sg13g2/verilog/RM_IHPSG13_1P_1024x32_c2_bm_bist.v new file mode 100644 index 0000000000..b1180a6af9 --- /dev/null +++ b/flow/platforms/ihp-sg13g2/verilog/RM_IHPSG13_1P_1024x32_c2_bm_bist.v @@ -0,0 +1,175 @@ +// ------------------------------------------------------ +// +// Copyright 2025 IHP PDK Authors +// +// Licensed under the Apache License, Version 2.0 (the "License"); +// you may not use this file except in compliance with the License. +// You may obtain a copy of the License at +// +// https://www.apache.org/licenses/LICENSE-2.0 +// +// Unless required by applicable law or agreed to in writing, software +// distributed under the License is distributed on an "AS IS" BASIS, +// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +// See the License for the specific language governing permissions and +// limitations under the License. +// +// Generated on Thu Aug 21 20:48:28 2025 +// +// ------------------------------------------------------ +`celldefine +module RM_IHPSG13_1P_1024x32_c2_bm_bist ( + A_CLK, + A_MEN, + A_WEN, + A_REN, + A_ADDR, + A_DIN, + A_DLY, + A_DOUT, + A_BM, + A_BIST_CLK, + A_BIST_EN, + A_BIST_MEN, + A_BIST_WEN, + A_BIST_REN, + A_BIST_ADDR, + A_BIST_DIN, + A_BIST_BM +); + + input A_CLK; + input A_MEN; + input A_WEN; + input A_REN; + input [9:0] A_ADDR; + input [31:0] A_DIN; + input A_DLY; + output [31:0] A_DOUT; + input [31:0] A_BM; + input A_BIST_CLK; + input A_BIST_EN; + input A_BIST_MEN; + input A_BIST_WEN; + input A_BIST_REN; + input [9:0] A_BIST_ADDR; + input [31:0] A_BIST_DIN; + input [31:0] A_BIST_BM; + + +`ifdef FUNCTIONAL // functional // + + + SRAM_1P_behavioral_bm_bist #( + .P_DATA_WIDTH(32), + .P_ADDR_WIDTH(10) + ) i_SRAM_1P_behavioral_bm_bist ( + .A_CLK(A_CLK), + .A_MEN(A_MEN), + .A_WEN(A_WEN), + .A_REN(A_REN), + .A_ADDR(A_ADDR), + .A_DLY(A_DLY), + .A_DIN(A_DIN), + .A_DOUT(A_DOUT), + .A_BM(A_BM), + .A_BIST_CLK(A_BIST_CLK), + .A_BIST_EN(A_BIST_EN), + .A_BIST_MEN(A_BIST_MEN), + .A_BIST_WEN(A_BIST_WEN), + .A_BIST_REN(A_BIST_REN), + .A_BIST_ADDR(A_BIST_ADDR), + .A_BIST_DIN(A_BIST_DIN), + .A_BIST_BM(A_BIST_BM) + ); + +`else + + wire A_CLK_DELAY; + wire A_MEN_DELAY; + wire A_WEN_DELAY; + wire A_REN_DELAY; + wire [9:0] A_ADDR_DELAY; + wire [31:0] A_DIN_DELAY; + wire [31:0] A_BM_DELAY; + wire A_BIST_CLK_DELAY; + wire A_BIST_MEN_DELAY; + wire A_BIST_WEN_DELAY; + wire A_BIST_REN_DELAY; + wire [9:0] A_BIST_ADDR_DELAY; + wire [31:0] A_BIST_DIN_DELAY; + wire [31:0] A_BIST_BM_DELAY; + + reg notifier; + + wire A_RW_ACCESS = (A_WEN || A_REN) && A_MEN; + wire A_W_ACCESS = A_WEN && A_MEN; + wire A_BIST_RW_ACCESS = (A_BIST_WEN || A_BIST_REN) && A_BIST_MEN; + wire A_BIST_W_ACCESS = A_BIST_WEN && A_BIST_MEN; + + + + SRAM_1P_behavioral_bm_bist #( + .P_DATA_WIDTH(32), + .P_ADDR_WIDTH(10) + ) i_SRAM_1P_behavioral_bm_bist ( + .A_CLK(A_CLK_DELAY), + .A_MEN(A_MEN_DELAY), + .A_WEN(A_WEN_DELAY), + .A_REN(A_REN_DELAY), + .A_ADDR(A_ADDR_DELAY), + .A_DLY(A_DLY), + .A_DIN(A_DIN_DELAY), + .A_DOUT(A_DOUT), + .A_BM(A_BM_DELAY), + .A_BIST_CLK(A_BIST_CLK_DELAY), + .A_BIST_EN(A_BIST_EN), + .A_BIST_MEN(A_BIST_MEN_DELAY), + .A_BIST_WEN(A_BIST_WEN_DELAY), + .A_BIST_REN(A_BIST_REN_DELAY), + .A_BIST_ADDR(A_BIST_ADDR_DELAY), + .A_BIST_DIN(A_BIST_DIN_DELAY), + .A_BIST_BM(A_BIST_BM_DELAY) + ); + + + specify + + (posedge A_CLK *> (A_DOUT : A_DIN)) = (1.0, 1.0); + $width(posedge A_CLK, 1.0,0,notifier); + $setuphold(posedge A_CLK &&& A_MEN, posedge A_MEN, 1.0, 1.0,notifier,,,A_CLK_DELAY, A_MEN_DELAY); + $setuphold(posedge A_CLK &&& A_MEN, posedge A_REN, 1.0, 1.0,notifier,,,A_CLK_DELAY, A_REN_DELAY); + $setuphold(posedge A_CLK &&& A_MEN, posedge A_WEN, 1.0, 1.0,notifier,,,A_CLK_DELAY, A_WEN_DELAY); + $setuphold(posedge A_CLK &&& A_MEN, negedge A_MEN, 1.0, 1.0,notifier,,,A_CLK_DELAY, A_MEN_DELAY); + $setuphold(posedge A_CLK &&& A_MEN, negedge A_REN, 1.0, 1.0,notifier,,,A_CLK_DELAY, A_REN_DELAY); + $setuphold(posedge A_CLK &&& A_MEN, negedge A_WEN, 1.0, 1.0,notifier,,,A_CLK_DELAY, A_WEN_DELAY); + $setuphold(posedge A_CLK &&& A_RW_ACCESS, posedge A_ADDR, 1.0 ,1.0, notifier,,,A_CLK_DELAY, A_ADDR_DELAY); + $setuphold(posedge A_CLK &&& A_RW_ACCESS, negedge A_ADDR, 1.0 ,1.0, notifier,,,A_CLK_DELAY, A_ADDR_DELAY); + + $setuphold(posedge A_CLK &&& A_W_ACCESS, posedge A_DIN, 1.0 ,1.0, notifier,,,A_CLK_DELAY, A_DIN_DELAY); + $setuphold(posedge A_CLK &&& A_W_ACCESS, negedge A_DIN, 1.0 ,1.0, notifier,,,A_CLK_DELAY, A_DIN_DELAY); + $setuphold(posedge A_CLK &&& A_W_ACCESS, posedge A_BM, 1.0 ,1.0, notifier,,,A_CLK_DELAY, A_BM_DELAY); + $setuphold(posedge A_CLK &&& A_W_ACCESS, negedge A_BM, 1.0 ,1.0, notifier,,,A_CLK_DELAY, A_BM_DELAY); + (posedge A_BIST_CLK *> (A_DOUT : A_BIST_DIN)) = (1.0, 1.0); + $width(posedge A_BIST_CLK, 1.0,0,notifier); + $setuphold(posedge A_BIST_CLK &&& A_BIST_MEN, posedge A_BIST_MEN, 1.0, 1.0,notifier,,,A_BIST_CLK_DELAY, A_BIST_MEN_DELAY); + $setuphold(posedge A_BIST_CLK &&& A_BIST_MEN, posedge A_BIST_REN, 1.0, 1.0,notifier,,,A_BIST_CLK_DELAY, A_BIST_REN_DELAY); + $setuphold(posedge A_BIST_CLK &&& A_BIST_MEN, posedge A_BIST_WEN, 1.0, 1.0,notifier,,,A_BIST_CLK_DELAY, A_BIST_WEN_DELAY); + $setuphold(posedge A_BIST_CLK &&& A_BIST_MEN, negedge A_BIST_MEN, 1.0, 1.0,notifier,,,A_BIST_CLK_DELAY, A_BIST_MEN_DELAY); + $setuphold(posedge A_BIST_CLK &&& A_BIST_MEN, negedge A_BIST_REN, 1.0, 1.0,notifier,,,A_BIST_CLK_DELAY, A_BIST_REN_DELAY); + $setuphold(posedge A_BIST_CLK &&& A_BIST_MEN, negedge A_BIST_WEN, 1.0, 1.0,notifier,,,A_BIST_CLK_DELAY, A_BIST_WEN_DELAY); + $setuphold(posedge A_BIST_CLK &&& A_BIST_RW_ACCESS, posedge A_BIST_ADDR, 1.0 ,1.0, notifier,,,A_BIST_CLK_DELAY, A_BIST_ADDR_DELAY); + $setuphold(posedge A_BIST_CLK &&& A_BIST_RW_ACCESS, negedge A_BIST_ADDR, 1.0 ,1.0, notifier,,,A_BIST_CLK_DELAY, A_BIST_ADDR_DELAY); + + $setuphold(posedge A_BIST_CLK &&& A_BIST_W_ACCESS, posedge A_BIST_DIN, 1.0 ,1.0, notifier,,,A_BIST_CLK_DELAY, A_BIST_DIN_DELAY); + $setuphold(posedge A_BIST_CLK &&& A_BIST_W_ACCESS, negedge A_BIST_DIN, 1.0 ,1.0, notifier,,,A_BIST_CLK_DELAY, A_BIST_DIN_DELAY); + $setuphold(posedge A_BIST_CLK &&& A_BIST_W_ACCESS, posedge A_BIST_BM, 1.0 ,1.0, notifier,,,A_BIST_CLK_DELAY, A_BIST_BM_DELAY); + $setuphold(posedge A_BIST_CLK &&& A_BIST_W_ACCESS, negedge A_BIST_BM, 1.0 ,1.0, notifier,,,A_BIST_CLK_DELAY, A_BIST_BM_DELAY); + + + endspecify + +`endif + +endmodule +`endcelldefine \ No newline at end of file diff --git a/flow/platforms/ihp-sg13g2/verilog/RM_IHPSG13_1P_256x16_c2_bm_bist.v b/flow/platforms/ihp-sg13g2/verilog/RM_IHPSG13_1P_256x16_c2_bm_bist.v new file mode 100644 index 0000000000..a533e908c8 --- /dev/null +++ b/flow/platforms/ihp-sg13g2/verilog/RM_IHPSG13_1P_256x16_c2_bm_bist.v @@ -0,0 +1,175 @@ +// ------------------------------------------------------ +// +// Copyright 2025 IHP PDK Authors +// +// Licensed under the Apache License, Version 2.0 (the "License"); +// you may not use this file except in compliance with the License. +// You may obtain a copy of the License at +// +// https://www.apache.org/licenses/LICENSE-2.0 +// +// Unless required by applicable law or agreed to in writing, software +// distributed under the License is distributed on an "AS IS" BASIS, +// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +// See the License for the specific language governing permissions and +// limitations under the License. +// +// Generated on Wed Aug 27 12:14:51 2025 +// +// ------------------------------------------------------ +`celldefine +module RM_IHPSG13_1P_256x16_c2_bm_bist ( + A_CLK, + A_MEN, + A_WEN, + A_REN, + A_ADDR, + A_DIN, + A_DLY, + A_DOUT, + A_BM, + A_BIST_CLK, + A_BIST_EN, + A_BIST_MEN, + A_BIST_WEN, + A_BIST_REN, + A_BIST_ADDR, + A_BIST_DIN, + A_BIST_BM +); + + input A_CLK; + input A_MEN; + input A_WEN; + input A_REN; + input [7:0] A_ADDR; + input [15:0] A_DIN; + input A_DLY; + output [15:0] A_DOUT; + input [15:0] A_BM; + input A_BIST_CLK; + input A_BIST_EN; + input A_BIST_MEN; + input A_BIST_WEN; + input A_BIST_REN; + input [7:0] A_BIST_ADDR; + input [15:0] A_BIST_DIN; + input [15:0] A_BIST_BM; + + +`ifdef FUNCTIONAL // functional // + + + SRAM_1P_behavioral_bm_bist #( + .P_DATA_WIDTH(16), + .P_ADDR_WIDTH(8) + ) i_SRAM_1P_behavioral_bm_bist ( + .A_CLK(A_CLK), + .A_MEN(A_MEN), + .A_WEN(A_WEN), + .A_REN(A_REN), + .A_ADDR(A_ADDR), + .A_DLY(A_DLY), + .A_DIN(A_DIN), + .A_DOUT(A_DOUT), + .A_BM(A_BM), + .A_BIST_CLK(A_BIST_CLK), + .A_BIST_EN(A_BIST_EN), + .A_BIST_MEN(A_BIST_MEN), + .A_BIST_WEN(A_BIST_WEN), + .A_BIST_REN(A_BIST_REN), + .A_BIST_ADDR(A_BIST_ADDR), + .A_BIST_DIN(A_BIST_DIN), + .A_BIST_BM(A_BIST_BM) + ); + +`else + + wire A_CLK_DELAY; + wire A_MEN_DELAY; + wire A_WEN_DELAY; + wire A_REN_DELAY; + wire [7:0] A_ADDR_DELAY; + wire [15:0] A_DIN_DELAY; + wire [15:0] A_BM_DELAY; + wire A_BIST_CLK_DELAY; + wire A_BIST_MEN_DELAY; + wire A_BIST_WEN_DELAY; + wire A_BIST_REN_DELAY; + wire [7:0] A_BIST_ADDR_DELAY; + wire [15:0] A_BIST_DIN_DELAY; + wire [15:0] A_BIST_BM_DELAY; + + reg notifier; + + wire A_RW_ACCESS = (A_WEN || A_REN) && A_MEN; + wire A_W_ACCESS = A_WEN && A_MEN; + wire A_BIST_RW_ACCESS = (A_BIST_WEN || A_BIST_REN) && A_BIST_MEN; + wire A_BIST_W_ACCESS = A_BIST_WEN && A_BIST_MEN; + + + + SRAM_1P_behavioral_bm_bist #( + .P_DATA_WIDTH(16), + .P_ADDR_WIDTH(8) + ) i_SRAM_1P_behavioral_bm_bist ( + .A_CLK(A_CLK_DELAY), + .A_MEN(A_MEN_DELAY), + .A_WEN(A_WEN_DELAY), + .A_REN(A_REN_DELAY), + .A_ADDR(A_ADDR_DELAY), + .A_DLY(A_DLY), + .A_DIN(A_DIN_DELAY), + .A_DOUT(A_DOUT), + .A_BM(A_BM_DELAY), + .A_BIST_CLK(A_BIST_CLK_DELAY), + .A_BIST_EN(A_BIST_EN), + .A_BIST_MEN(A_BIST_MEN_DELAY), + .A_BIST_WEN(A_BIST_WEN_DELAY), + .A_BIST_REN(A_BIST_REN_DELAY), + .A_BIST_ADDR(A_BIST_ADDR_DELAY), + .A_BIST_DIN(A_BIST_DIN_DELAY), + .A_BIST_BM(A_BIST_BM_DELAY) + ); + + + specify + + (posedge A_CLK *> (A_DOUT : A_DIN)) = (1.0, 1.0); + $width(posedge A_CLK, 1.0,0,notifier); + $setuphold(posedge A_CLK &&& A_MEN, posedge A_MEN, 1.0, 1.0,notifier,,,A_CLK_DELAY, A_MEN_DELAY); + $setuphold(posedge A_CLK &&& A_MEN, posedge A_REN, 1.0, 1.0,notifier,,,A_CLK_DELAY, A_REN_DELAY); + $setuphold(posedge A_CLK &&& A_MEN, posedge A_WEN, 1.0, 1.0,notifier,,,A_CLK_DELAY, A_WEN_DELAY); + $setuphold(posedge A_CLK &&& A_MEN, negedge A_MEN, 1.0, 1.0,notifier,,,A_CLK_DELAY, A_MEN_DELAY); + $setuphold(posedge A_CLK &&& A_MEN, negedge A_REN, 1.0, 1.0,notifier,,,A_CLK_DELAY, A_REN_DELAY); + $setuphold(posedge A_CLK &&& A_MEN, negedge A_WEN, 1.0, 1.0,notifier,,,A_CLK_DELAY, A_WEN_DELAY); + $setuphold(posedge A_CLK &&& A_RW_ACCESS, posedge A_ADDR, 1.0 ,1.0, notifier,,,A_CLK_DELAY, A_ADDR_DELAY); + $setuphold(posedge A_CLK &&& A_RW_ACCESS, negedge A_ADDR, 1.0 ,1.0, notifier,,,A_CLK_DELAY, A_ADDR_DELAY); + + $setuphold(posedge A_CLK &&& A_W_ACCESS, posedge A_DIN, 1.0 ,1.0, notifier,,,A_CLK_DELAY, A_DIN_DELAY); + $setuphold(posedge A_CLK &&& A_W_ACCESS, negedge A_DIN, 1.0 ,1.0, notifier,,,A_CLK_DELAY, A_DIN_DELAY); + $setuphold(posedge A_CLK &&& A_W_ACCESS, posedge A_BM, 1.0 ,1.0, notifier,,,A_CLK_DELAY, A_BM_DELAY); + $setuphold(posedge A_CLK &&& A_W_ACCESS, negedge A_BM, 1.0 ,1.0, notifier,,,A_CLK_DELAY, A_BM_DELAY); + (posedge A_BIST_CLK *> (A_DOUT : A_BIST_DIN)) = (1.0, 1.0); + $width(posedge A_BIST_CLK, 1.0,0,notifier); + $setuphold(posedge A_BIST_CLK &&& A_BIST_MEN, posedge A_BIST_MEN, 1.0, 1.0,notifier,,,A_BIST_CLK_DELAY, A_BIST_MEN_DELAY); + $setuphold(posedge A_BIST_CLK &&& A_BIST_MEN, posedge A_BIST_REN, 1.0, 1.0,notifier,,,A_BIST_CLK_DELAY, A_BIST_REN_DELAY); + $setuphold(posedge A_BIST_CLK &&& A_BIST_MEN, posedge A_BIST_WEN, 1.0, 1.0,notifier,,,A_BIST_CLK_DELAY, A_BIST_WEN_DELAY); + $setuphold(posedge A_BIST_CLK &&& A_BIST_MEN, negedge A_BIST_MEN, 1.0, 1.0,notifier,,,A_BIST_CLK_DELAY, A_BIST_MEN_DELAY); + $setuphold(posedge A_BIST_CLK &&& A_BIST_MEN, negedge A_BIST_REN, 1.0, 1.0,notifier,,,A_BIST_CLK_DELAY, A_BIST_REN_DELAY); + $setuphold(posedge A_BIST_CLK &&& A_BIST_MEN, negedge A_BIST_WEN, 1.0, 1.0,notifier,,,A_BIST_CLK_DELAY, A_BIST_WEN_DELAY); + $setuphold(posedge A_BIST_CLK &&& A_BIST_RW_ACCESS, posedge A_BIST_ADDR, 1.0 ,1.0, notifier,,,A_BIST_CLK_DELAY, A_BIST_ADDR_DELAY); + $setuphold(posedge A_BIST_CLK &&& A_BIST_RW_ACCESS, negedge A_BIST_ADDR, 1.0 ,1.0, notifier,,,A_BIST_CLK_DELAY, A_BIST_ADDR_DELAY); + + $setuphold(posedge A_BIST_CLK &&& A_BIST_W_ACCESS, posedge A_BIST_DIN, 1.0 ,1.0, notifier,,,A_BIST_CLK_DELAY, A_BIST_DIN_DELAY); + $setuphold(posedge A_BIST_CLK &&& A_BIST_W_ACCESS, negedge A_BIST_DIN, 1.0 ,1.0, notifier,,,A_BIST_CLK_DELAY, A_BIST_DIN_DELAY); + $setuphold(posedge A_BIST_CLK &&& A_BIST_W_ACCESS, posedge A_BIST_BM, 1.0 ,1.0, notifier,,,A_BIST_CLK_DELAY, A_BIST_BM_DELAY); + $setuphold(posedge A_BIST_CLK &&& A_BIST_W_ACCESS, negedge A_BIST_BM, 1.0 ,1.0, notifier,,,A_BIST_CLK_DELAY, A_BIST_BM_DELAY); + + + endspecify + +`endif + +endmodule +`endcelldefine \ No newline at end of file diff --git a/flow/platforms/ihp-sg13g2/verilog/RM_IHPSG13_1P_256x32_c2_bm_bist.v b/flow/platforms/ihp-sg13g2/verilog/RM_IHPSG13_1P_256x32_c2_bm_bist.v new file mode 100644 index 0000000000..4b84bbdbbf --- /dev/null +++ b/flow/platforms/ihp-sg13g2/verilog/RM_IHPSG13_1P_256x32_c2_bm_bist.v @@ -0,0 +1,175 @@ +// ------------------------------------------------------ +// +// Copyright 2025 IHP PDK Authors +// +// Licensed under the Apache License, Version 2.0 (the "License"); +// you may not use this file except in compliance with the License. +// You may obtain a copy of the License at +// +// https://www.apache.org/licenses/LICENSE-2.0 +// +// Unless required by applicable law or agreed to in writing, software +// distributed under the License is distributed on an "AS IS" BASIS, +// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +// See the License for the specific language governing permissions and +// limitations under the License. +// +// Generated on Thu Aug 21 20:49:12 2025 +// +// ------------------------------------------------------ +`celldefine +module RM_IHPSG13_1P_256x32_c2_bm_bist ( + A_CLK, + A_MEN, + A_WEN, + A_REN, + A_ADDR, + A_DIN, + A_DLY, + A_DOUT, + A_BM, + A_BIST_CLK, + A_BIST_EN, + A_BIST_MEN, + A_BIST_WEN, + A_BIST_REN, + A_BIST_ADDR, + A_BIST_DIN, + A_BIST_BM +); + + input A_CLK; + input A_MEN; + input A_WEN; + input A_REN; + input [7:0] A_ADDR; + input [31:0] A_DIN; + input A_DLY; + output [31:0] A_DOUT; + input [31:0] A_BM; + input A_BIST_CLK; + input A_BIST_EN; + input A_BIST_MEN; + input A_BIST_WEN; + input A_BIST_REN; + input [7:0] A_BIST_ADDR; + input [31:0] A_BIST_DIN; + input [31:0] A_BIST_BM; + + +`ifdef FUNCTIONAL // functional // + + + SRAM_1P_behavioral_bm_bist #( + .P_DATA_WIDTH(32), + .P_ADDR_WIDTH(8) + ) i_SRAM_1P_behavioral_bm_bist ( + .A_CLK(A_CLK), + .A_MEN(A_MEN), + .A_WEN(A_WEN), + .A_REN(A_REN), + .A_ADDR(A_ADDR), + .A_DLY(A_DLY), + .A_DIN(A_DIN), + .A_DOUT(A_DOUT), + .A_BM(A_BM), + .A_BIST_CLK(A_BIST_CLK), + .A_BIST_EN(A_BIST_EN), + .A_BIST_MEN(A_BIST_MEN), + .A_BIST_WEN(A_BIST_WEN), + .A_BIST_REN(A_BIST_REN), + .A_BIST_ADDR(A_BIST_ADDR), + .A_BIST_DIN(A_BIST_DIN), + .A_BIST_BM(A_BIST_BM) + ); + +`else + + wire A_CLK_DELAY; + wire A_MEN_DELAY; + wire A_WEN_DELAY; + wire A_REN_DELAY; + wire [7:0] A_ADDR_DELAY; + wire [31:0] A_DIN_DELAY; + wire [31:0] A_BM_DELAY; + wire A_BIST_CLK_DELAY; + wire A_BIST_MEN_DELAY; + wire A_BIST_WEN_DELAY; + wire A_BIST_REN_DELAY; + wire [7:0] A_BIST_ADDR_DELAY; + wire [31:0] A_BIST_DIN_DELAY; + wire [31:0] A_BIST_BM_DELAY; + + reg notifier; + + wire A_RW_ACCESS = (A_WEN || A_REN) && A_MEN; + wire A_W_ACCESS = A_WEN && A_MEN; + wire A_BIST_RW_ACCESS = (A_BIST_WEN || A_BIST_REN) && A_BIST_MEN; + wire A_BIST_W_ACCESS = A_BIST_WEN && A_BIST_MEN; + + + + SRAM_1P_behavioral_bm_bist #( + .P_DATA_WIDTH(32), + .P_ADDR_WIDTH(8) + ) i_SRAM_1P_behavioral_bm_bist ( + .A_CLK(A_CLK_DELAY), + .A_MEN(A_MEN_DELAY), + .A_WEN(A_WEN_DELAY), + .A_REN(A_REN_DELAY), + .A_ADDR(A_ADDR_DELAY), + .A_DLY(A_DLY), + .A_DIN(A_DIN_DELAY), + .A_DOUT(A_DOUT), + .A_BM(A_BM_DELAY), + .A_BIST_CLK(A_BIST_CLK_DELAY), + .A_BIST_EN(A_BIST_EN), + .A_BIST_MEN(A_BIST_MEN_DELAY), + .A_BIST_WEN(A_BIST_WEN_DELAY), + .A_BIST_REN(A_BIST_REN_DELAY), + .A_BIST_ADDR(A_BIST_ADDR_DELAY), + .A_BIST_DIN(A_BIST_DIN_DELAY), + .A_BIST_BM(A_BIST_BM_DELAY) + ); + + + specify + + (posedge A_CLK *> (A_DOUT : A_DIN)) = (1.0, 1.0); + $width(posedge A_CLK, 1.0,0,notifier); + $setuphold(posedge A_CLK &&& A_MEN, posedge A_MEN, 1.0, 1.0,notifier,,,A_CLK_DELAY, A_MEN_DELAY); + $setuphold(posedge A_CLK &&& A_MEN, posedge A_REN, 1.0, 1.0,notifier,,,A_CLK_DELAY, A_REN_DELAY); + $setuphold(posedge A_CLK &&& A_MEN, posedge A_WEN, 1.0, 1.0,notifier,,,A_CLK_DELAY, A_WEN_DELAY); + $setuphold(posedge A_CLK &&& A_MEN, negedge A_MEN, 1.0, 1.0,notifier,,,A_CLK_DELAY, A_MEN_DELAY); + $setuphold(posedge A_CLK &&& A_MEN, negedge A_REN, 1.0, 1.0,notifier,,,A_CLK_DELAY, A_REN_DELAY); + $setuphold(posedge A_CLK &&& A_MEN, negedge A_WEN, 1.0, 1.0,notifier,,,A_CLK_DELAY, A_WEN_DELAY); + $setuphold(posedge A_CLK &&& A_RW_ACCESS, posedge A_ADDR, 1.0 ,1.0, notifier,,,A_CLK_DELAY, A_ADDR_DELAY); + $setuphold(posedge A_CLK &&& A_RW_ACCESS, negedge A_ADDR, 1.0 ,1.0, notifier,,,A_CLK_DELAY, A_ADDR_DELAY); + + $setuphold(posedge A_CLK &&& A_W_ACCESS, posedge A_DIN, 1.0 ,1.0, notifier,,,A_CLK_DELAY, A_DIN_DELAY); + $setuphold(posedge A_CLK &&& A_W_ACCESS, negedge A_DIN, 1.0 ,1.0, notifier,,,A_CLK_DELAY, A_DIN_DELAY); + $setuphold(posedge A_CLK &&& A_W_ACCESS, posedge A_BM, 1.0 ,1.0, notifier,,,A_CLK_DELAY, A_BM_DELAY); + $setuphold(posedge A_CLK &&& A_W_ACCESS, negedge A_BM, 1.0 ,1.0, notifier,,,A_CLK_DELAY, A_BM_DELAY); + (posedge A_BIST_CLK *> (A_DOUT : A_BIST_DIN)) = (1.0, 1.0); + $width(posedge A_BIST_CLK, 1.0,0,notifier); + $setuphold(posedge A_BIST_CLK &&& A_BIST_MEN, posedge A_BIST_MEN, 1.0, 1.0,notifier,,,A_BIST_CLK_DELAY, A_BIST_MEN_DELAY); + $setuphold(posedge A_BIST_CLK &&& A_BIST_MEN, posedge A_BIST_REN, 1.0, 1.0,notifier,,,A_BIST_CLK_DELAY, A_BIST_REN_DELAY); + $setuphold(posedge A_BIST_CLK &&& A_BIST_MEN, posedge A_BIST_WEN, 1.0, 1.0,notifier,,,A_BIST_CLK_DELAY, A_BIST_WEN_DELAY); + $setuphold(posedge A_BIST_CLK &&& A_BIST_MEN, negedge A_BIST_MEN, 1.0, 1.0,notifier,,,A_BIST_CLK_DELAY, A_BIST_MEN_DELAY); + $setuphold(posedge A_BIST_CLK &&& A_BIST_MEN, negedge A_BIST_REN, 1.0, 1.0,notifier,,,A_BIST_CLK_DELAY, A_BIST_REN_DELAY); + $setuphold(posedge A_BIST_CLK &&& A_BIST_MEN, negedge A_BIST_WEN, 1.0, 1.0,notifier,,,A_BIST_CLK_DELAY, A_BIST_WEN_DELAY); + $setuphold(posedge A_BIST_CLK &&& A_BIST_RW_ACCESS, posedge A_BIST_ADDR, 1.0 ,1.0, notifier,,,A_BIST_CLK_DELAY, A_BIST_ADDR_DELAY); + $setuphold(posedge A_BIST_CLK &&& A_BIST_RW_ACCESS, negedge A_BIST_ADDR, 1.0 ,1.0, notifier,,,A_BIST_CLK_DELAY, A_BIST_ADDR_DELAY); + + $setuphold(posedge A_BIST_CLK &&& A_BIST_W_ACCESS, posedge A_BIST_DIN, 1.0 ,1.0, notifier,,,A_BIST_CLK_DELAY, A_BIST_DIN_DELAY); + $setuphold(posedge A_BIST_CLK &&& A_BIST_W_ACCESS, negedge A_BIST_DIN, 1.0 ,1.0, notifier,,,A_BIST_CLK_DELAY, A_BIST_DIN_DELAY); + $setuphold(posedge A_BIST_CLK &&& A_BIST_W_ACCESS, posedge A_BIST_BM, 1.0 ,1.0, notifier,,,A_BIST_CLK_DELAY, A_BIST_BM_DELAY); + $setuphold(posedge A_BIST_CLK &&& A_BIST_W_ACCESS, negedge A_BIST_BM, 1.0 ,1.0, notifier,,,A_BIST_CLK_DELAY, A_BIST_BM_DELAY); + + + endspecify + +`endif + +endmodule +`endcelldefine \ No newline at end of file diff --git a/flow/platforms/ihp-sg13g2/verilog/RM_IHPSG13_1P_256x8_c3_bm_bist.v b/flow/platforms/ihp-sg13g2/verilog/RM_IHPSG13_1P_256x8_c3_bm_bist.v new file mode 100644 index 0000000000..6f36ce5604 --- /dev/null +++ b/flow/platforms/ihp-sg13g2/verilog/RM_IHPSG13_1P_256x8_c3_bm_bist.v @@ -0,0 +1,175 @@ +// ------------------------------------------------------ +// +// Copyright 2025 IHP PDK Authors +// +// Licensed under the Apache License, Version 2.0 (the "License"); +// you may not use this file except in compliance with the License. +// You may obtain a copy of the License at +// +// https://www.apache.org/licenses/LICENSE-2.0 +// +// Unless required by applicable law or agreed to in writing, software +// distributed under the License is distributed on an "AS IS" BASIS, +// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +// See the License for the specific language governing permissions and +// limitations under the License. +// +// Generated on Wed Aug 27 16:22:45 2025 +// +// ------------------------------------------------------ +`celldefine +module RM_IHPSG13_1P_256x8_c3_bm_bist ( + A_CLK, + A_MEN, + A_WEN, + A_REN, + A_ADDR, + A_DIN, + A_DLY, + A_DOUT, + A_BM, + A_BIST_CLK, + A_BIST_EN, + A_BIST_MEN, + A_BIST_WEN, + A_BIST_REN, + A_BIST_ADDR, + A_BIST_DIN, + A_BIST_BM +); + + input A_CLK; + input A_MEN; + input A_WEN; + input A_REN; + input [7:0] A_ADDR; + input [7:0] A_DIN; + input A_DLY; + output [7:0] A_DOUT; + input [7:0] A_BM; + input A_BIST_CLK; + input A_BIST_EN; + input A_BIST_MEN; + input A_BIST_WEN; + input A_BIST_REN; + input [7:0] A_BIST_ADDR; + input [7:0] A_BIST_DIN; + input [7:0] A_BIST_BM; + + +`ifdef FUNCTIONAL // functional // + + + SRAM_1P_behavioral_bm_bist #( + .P_DATA_WIDTH(8), + .P_ADDR_WIDTH(8) + ) i_SRAM_1P_behavioral_bm_bist ( + .A_CLK(A_CLK), + .A_MEN(A_MEN), + .A_WEN(A_WEN), + .A_REN(A_REN), + .A_ADDR(A_ADDR), + .A_DLY(A_DLY), + .A_DIN(A_DIN), + .A_DOUT(A_DOUT), + .A_BM(A_BM), + .A_BIST_CLK(A_BIST_CLK), + .A_BIST_EN(A_BIST_EN), + .A_BIST_MEN(A_BIST_MEN), + .A_BIST_WEN(A_BIST_WEN), + .A_BIST_REN(A_BIST_REN), + .A_BIST_ADDR(A_BIST_ADDR), + .A_BIST_DIN(A_BIST_DIN), + .A_BIST_BM(A_BIST_BM) + ); + +`else + + wire A_CLK_DELAY; + wire A_MEN_DELAY; + wire A_WEN_DELAY; + wire A_REN_DELAY; + wire [7:0] A_ADDR_DELAY; + wire [7:0] A_DIN_DELAY; + wire [7:0] A_BM_DELAY; + wire A_BIST_CLK_DELAY; + wire A_BIST_MEN_DELAY; + wire A_BIST_WEN_DELAY; + wire A_BIST_REN_DELAY; + wire [7:0] A_BIST_ADDR_DELAY; + wire [7:0] A_BIST_DIN_DELAY; + wire [7:0] A_BIST_BM_DELAY; + + reg notifier; + + wire A_RW_ACCESS = (A_WEN || A_REN) && A_MEN; + wire A_W_ACCESS = A_WEN && A_MEN; + wire A_BIST_RW_ACCESS = (A_BIST_WEN || A_BIST_REN) && A_BIST_MEN; + wire A_BIST_W_ACCESS = A_BIST_WEN && A_BIST_MEN; + + + + SRAM_1P_behavioral_bm_bist #( + .P_DATA_WIDTH(8), + .P_ADDR_WIDTH(8) + ) i_SRAM_1P_behavioral_bm_bist ( + .A_CLK(A_CLK_DELAY), + .A_MEN(A_MEN_DELAY), + .A_WEN(A_WEN_DELAY), + .A_REN(A_REN_DELAY), + .A_ADDR(A_ADDR_DELAY), + .A_DLY(A_DLY), + .A_DIN(A_DIN_DELAY), + .A_DOUT(A_DOUT), + .A_BM(A_BM_DELAY), + .A_BIST_CLK(A_BIST_CLK_DELAY), + .A_BIST_EN(A_BIST_EN), + .A_BIST_MEN(A_BIST_MEN_DELAY), + .A_BIST_WEN(A_BIST_WEN_DELAY), + .A_BIST_REN(A_BIST_REN_DELAY), + .A_BIST_ADDR(A_BIST_ADDR_DELAY), + .A_BIST_DIN(A_BIST_DIN_DELAY), + .A_BIST_BM(A_BIST_BM_DELAY) + ); + + + specify + + (posedge A_CLK *> (A_DOUT : A_DIN)) = (1.0, 1.0); + $width(posedge A_CLK, 1.0,0,notifier); + $setuphold(posedge A_CLK &&& A_MEN, posedge A_MEN, 1.0, 1.0,notifier,,,A_CLK_DELAY, A_MEN_DELAY); + $setuphold(posedge A_CLK &&& A_MEN, posedge A_REN, 1.0, 1.0,notifier,,,A_CLK_DELAY, A_REN_DELAY); + $setuphold(posedge A_CLK &&& A_MEN, posedge A_WEN, 1.0, 1.0,notifier,,,A_CLK_DELAY, A_WEN_DELAY); + $setuphold(posedge A_CLK &&& A_MEN, negedge A_MEN, 1.0, 1.0,notifier,,,A_CLK_DELAY, A_MEN_DELAY); + $setuphold(posedge A_CLK &&& A_MEN, negedge A_REN, 1.0, 1.0,notifier,,,A_CLK_DELAY, A_REN_DELAY); + $setuphold(posedge A_CLK &&& A_MEN, negedge A_WEN, 1.0, 1.0,notifier,,,A_CLK_DELAY, A_WEN_DELAY); + $setuphold(posedge A_CLK &&& A_RW_ACCESS, posedge A_ADDR, 1.0 ,1.0, notifier,,,A_CLK_DELAY, A_ADDR_DELAY); + $setuphold(posedge A_CLK &&& A_RW_ACCESS, negedge A_ADDR, 1.0 ,1.0, notifier,,,A_CLK_DELAY, A_ADDR_DELAY); + + $setuphold(posedge A_CLK &&& A_W_ACCESS, posedge A_DIN, 1.0 ,1.0, notifier,,,A_CLK_DELAY, A_DIN_DELAY); + $setuphold(posedge A_CLK &&& A_W_ACCESS, negedge A_DIN, 1.0 ,1.0, notifier,,,A_CLK_DELAY, A_DIN_DELAY); + $setuphold(posedge A_CLK &&& A_W_ACCESS, posedge A_BM, 1.0 ,1.0, notifier,,,A_CLK_DELAY, A_BM_DELAY); + $setuphold(posedge A_CLK &&& A_W_ACCESS, negedge A_BM, 1.0 ,1.0, notifier,,,A_CLK_DELAY, A_BM_DELAY); + (posedge A_BIST_CLK *> (A_DOUT : A_BIST_DIN)) = (1.0, 1.0); + $width(posedge A_BIST_CLK, 1.0,0,notifier); + $setuphold(posedge A_BIST_CLK &&& A_BIST_MEN, posedge A_BIST_MEN, 1.0, 1.0,notifier,,,A_BIST_CLK_DELAY, A_BIST_MEN_DELAY); + $setuphold(posedge A_BIST_CLK &&& A_BIST_MEN, posedge A_BIST_REN, 1.0, 1.0,notifier,,,A_BIST_CLK_DELAY, A_BIST_REN_DELAY); + $setuphold(posedge A_BIST_CLK &&& A_BIST_MEN, posedge A_BIST_WEN, 1.0, 1.0,notifier,,,A_BIST_CLK_DELAY, A_BIST_WEN_DELAY); + $setuphold(posedge A_BIST_CLK &&& A_BIST_MEN, negedge A_BIST_MEN, 1.0, 1.0,notifier,,,A_BIST_CLK_DELAY, A_BIST_MEN_DELAY); + $setuphold(posedge A_BIST_CLK &&& A_BIST_MEN, negedge A_BIST_REN, 1.0, 1.0,notifier,,,A_BIST_CLK_DELAY, A_BIST_REN_DELAY); + $setuphold(posedge A_BIST_CLK &&& A_BIST_MEN, negedge A_BIST_WEN, 1.0, 1.0,notifier,,,A_BIST_CLK_DELAY, A_BIST_WEN_DELAY); + $setuphold(posedge A_BIST_CLK &&& A_BIST_RW_ACCESS, posedge A_BIST_ADDR, 1.0 ,1.0, notifier,,,A_BIST_CLK_DELAY, A_BIST_ADDR_DELAY); + $setuphold(posedge A_BIST_CLK &&& A_BIST_RW_ACCESS, negedge A_BIST_ADDR, 1.0 ,1.0, notifier,,,A_BIST_CLK_DELAY, A_BIST_ADDR_DELAY); + + $setuphold(posedge A_BIST_CLK &&& A_BIST_W_ACCESS, posedge A_BIST_DIN, 1.0 ,1.0, notifier,,,A_BIST_CLK_DELAY, A_BIST_DIN_DELAY); + $setuphold(posedge A_BIST_CLK &&& A_BIST_W_ACCESS, negedge A_BIST_DIN, 1.0 ,1.0, notifier,,,A_BIST_CLK_DELAY, A_BIST_DIN_DELAY); + $setuphold(posedge A_BIST_CLK &&& A_BIST_W_ACCESS, posedge A_BIST_BM, 1.0 ,1.0, notifier,,,A_BIST_CLK_DELAY, A_BIST_BM_DELAY); + $setuphold(posedge A_BIST_CLK &&& A_BIST_W_ACCESS, negedge A_BIST_BM, 1.0 ,1.0, notifier,,,A_BIST_CLK_DELAY, A_BIST_BM_DELAY); + + + endspecify + +`endif + +endmodule +`endcelldefine \ No newline at end of file diff --git a/flow/platforms/ihp-sg13g2/verilog/RM_IHPSG13_1P_512x16_c2_bm_bist.v b/flow/platforms/ihp-sg13g2/verilog/RM_IHPSG13_1P_512x16_c2_bm_bist.v new file mode 100644 index 0000000000..d238ce5a4b --- /dev/null +++ b/flow/platforms/ihp-sg13g2/verilog/RM_IHPSG13_1P_512x16_c2_bm_bist.v @@ -0,0 +1,175 @@ +// ------------------------------------------------------ +// +// Copyright 2025 IHP PDK Authors +// +// Licensed under the Apache License, Version 2.0 (the "License"); +// you may not use this file except in compliance with the License. +// You may obtain a copy of the License at +// +// https://www.apache.org/licenses/LICENSE-2.0 +// +// Unless required by applicable law or agreed to in writing, software +// distributed under the License is distributed on an "AS IS" BASIS, +// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +// See the License for the specific language governing permissions and +// limitations under the License. +// +// Generated on Wed Aug 27 12:16:38 2025 +// +// ------------------------------------------------------ +`celldefine +module RM_IHPSG13_1P_512x16_c2_bm_bist ( + A_CLK, + A_MEN, + A_WEN, + A_REN, + A_ADDR, + A_DIN, + A_DLY, + A_DOUT, + A_BM, + A_BIST_CLK, + A_BIST_EN, + A_BIST_MEN, + A_BIST_WEN, + A_BIST_REN, + A_BIST_ADDR, + A_BIST_DIN, + A_BIST_BM +); + + input A_CLK; + input A_MEN; + input A_WEN; + input A_REN; + input [8:0] A_ADDR; + input [15:0] A_DIN; + input A_DLY; + output [15:0] A_DOUT; + input [15:0] A_BM; + input A_BIST_CLK; + input A_BIST_EN; + input A_BIST_MEN; + input A_BIST_WEN; + input A_BIST_REN; + input [8:0] A_BIST_ADDR; + input [15:0] A_BIST_DIN; + input [15:0] A_BIST_BM; + + +`ifdef FUNCTIONAL // functional // + + + SRAM_1P_behavioral_bm_bist #( + .P_DATA_WIDTH(16), + .P_ADDR_WIDTH(9) + ) i_SRAM_1P_behavioral_bm_bist ( + .A_CLK(A_CLK), + .A_MEN(A_MEN), + .A_WEN(A_WEN), + .A_REN(A_REN), + .A_ADDR(A_ADDR), + .A_DLY(A_DLY), + .A_DIN(A_DIN), + .A_DOUT(A_DOUT), + .A_BM(A_BM), + .A_BIST_CLK(A_BIST_CLK), + .A_BIST_EN(A_BIST_EN), + .A_BIST_MEN(A_BIST_MEN), + .A_BIST_WEN(A_BIST_WEN), + .A_BIST_REN(A_BIST_REN), + .A_BIST_ADDR(A_BIST_ADDR), + .A_BIST_DIN(A_BIST_DIN), + .A_BIST_BM(A_BIST_BM) + ); + +`else + + wire A_CLK_DELAY; + wire A_MEN_DELAY; + wire A_WEN_DELAY; + wire A_REN_DELAY; + wire [8:0] A_ADDR_DELAY; + wire [15:0] A_DIN_DELAY; + wire [15:0] A_BM_DELAY; + wire A_BIST_CLK_DELAY; + wire A_BIST_MEN_DELAY; + wire A_BIST_WEN_DELAY; + wire A_BIST_REN_DELAY; + wire [8:0] A_BIST_ADDR_DELAY; + wire [15:0] A_BIST_DIN_DELAY; + wire [15:0] A_BIST_BM_DELAY; + + reg notifier; + + wire A_RW_ACCESS = (A_WEN || A_REN) && A_MEN; + wire A_W_ACCESS = A_WEN && A_MEN; + wire A_BIST_RW_ACCESS = (A_BIST_WEN || A_BIST_REN) && A_BIST_MEN; + wire A_BIST_W_ACCESS = A_BIST_WEN && A_BIST_MEN; + + + + SRAM_1P_behavioral_bm_bist #( + .P_DATA_WIDTH(16), + .P_ADDR_WIDTH(9) + ) i_SRAM_1P_behavioral_bm_bist ( + .A_CLK(A_CLK_DELAY), + .A_MEN(A_MEN_DELAY), + .A_WEN(A_WEN_DELAY), + .A_REN(A_REN_DELAY), + .A_ADDR(A_ADDR_DELAY), + .A_DLY(A_DLY), + .A_DIN(A_DIN_DELAY), + .A_DOUT(A_DOUT), + .A_BM(A_BM_DELAY), + .A_BIST_CLK(A_BIST_CLK_DELAY), + .A_BIST_EN(A_BIST_EN), + .A_BIST_MEN(A_BIST_MEN_DELAY), + .A_BIST_WEN(A_BIST_WEN_DELAY), + .A_BIST_REN(A_BIST_REN_DELAY), + .A_BIST_ADDR(A_BIST_ADDR_DELAY), + .A_BIST_DIN(A_BIST_DIN_DELAY), + .A_BIST_BM(A_BIST_BM_DELAY) + ); + + + specify + + (posedge A_CLK *> (A_DOUT : A_DIN)) = (1.0, 1.0); + $width(posedge A_CLK, 1.0,0,notifier); + $setuphold(posedge A_CLK &&& A_MEN, posedge A_MEN, 1.0, 1.0,notifier,,,A_CLK_DELAY, A_MEN_DELAY); + $setuphold(posedge A_CLK &&& A_MEN, posedge A_REN, 1.0, 1.0,notifier,,,A_CLK_DELAY, A_REN_DELAY); + $setuphold(posedge A_CLK &&& A_MEN, posedge A_WEN, 1.0, 1.0,notifier,,,A_CLK_DELAY, A_WEN_DELAY); + $setuphold(posedge A_CLK &&& A_MEN, negedge A_MEN, 1.0, 1.0,notifier,,,A_CLK_DELAY, A_MEN_DELAY); + $setuphold(posedge A_CLK &&& A_MEN, negedge A_REN, 1.0, 1.0,notifier,,,A_CLK_DELAY, A_REN_DELAY); + $setuphold(posedge A_CLK &&& A_MEN, negedge A_WEN, 1.0, 1.0,notifier,,,A_CLK_DELAY, A_WEN_DELAY); + $setuphold(posedge A_CLK &&& A_RW_ACCESS, posedge A_ADDR, 1.0 ,1.0, notifier,,,A_CLK_DELAY, A_ADDR_DELAY); + $setuphold(posedge A_CLK &&& A_RW_ACCESS, negedge A_ADDR, 1.0 ,1.0, notifier,,,A_CLK_DELAY, A_ADDR_DELAY); + + $setuphold(posedge A_CLK &&& A_W_ACCESS, posedge A_DIN, 1.0 ,1.0, notifier,,,A_CLK_DELAY, A_DIN_DELAY); + $setuphold(posedge A_CLK &&& A_W_ACCESS, negedge A_DIN, 1.0 ,1.0, notifier,,,A_CLK_DELAY, A_DIN_DELAY); + $setuphold(posedge A_CLK &&& A_W_ACCESS, posedge A_BM, 1.0 ,1.0, notifier,,,A_CLK_DELAY, A_BM_DELAY); + $setuphold(posedge A_CLK &&& A_W_ACCESS, negedge A_BM, 1.0 ,1.0, notifier,,,A_CLK_DELAY, A_BM_DELAY); + (posedge A_BIST_CLK *> (A_DOUT : A_BIST_DIN)) = (1.0, 1.0); + $width(posedge A_BIST_CLK, 1.0,0,notifier); + $setuphold(posedge A_BIST_CLK &&& A_BIST_MEN, posedge A_BIST_MEN, 1.0, 1.0,notifier,,,A_BIST_CLK_DELAY, A_BIST_MEN_DELAY); + $setuphold(posedge A_BIST_CLK &&& A_BIST_MEN, posedge A_BIST_REN, 1.0, 1.0,notifier,,,A_BIST_CLK_DELAY, A_BIST_REN_DELAY); + $setuphold(posedge A_BIST_CLK &&& A_BIST_MEN, posedge A_BIST_WEN, 1.0, 1.0,notifier,,,A_BIST_CLK_DELAY, A_BIST_WEN_DELAY); + $setuphold(posedge A_BIST_CLK &&& A_BIST_MEN, negedge A_BIST_MEN, 1.0, 1.0,notifier,,,A_BIST_CLK_DELAY, A_BIST_MEN_DELAY); + $setuphold(posedge A_BIST_CLK &&& A_BIST_MEN, negedge A_BIST_REN, 1.0, 1.0,notifier,,,A_BIST_CLK_DELAY, A_BIST_REN_DELAY); + $setuphold(posedge A_BIST_CLK &&& A_BIST_MEN, negedge A_BIST_WEN, 1.0, 1.0,notifier,,,A_BIST_CLK_DELAY, A_BIST_WEN_DELAY); + $setuphold(posedge A_BIST_CLK &&& A_BIST_RW_ACCESS, posedge A_BIST_ADDR, 1.0 ,1.0, notifier,,,A_BIST_CLK_DELAY, A_BIST_ADDR_DELAY); + $setuphold(posedge A_BIST_CLK &&& A_BIST_RW_ACCESS, negedge A_BIST_ADDR, 1.0 ,1.0, notifier,,,A_BIST_CLK_DELAY, A_BIST_ADDR_DELAY); + + $setuphold(posedge A_BIST_CLK &&& A_BIST_W_ACCESS, posedge A_BIST_DIN, 1.0 ,1.0, notifier,,,A_BIST_CLK_DELAY, A_BIST_DIN_DELAY); + $setuphold(posedge A_BIST_CLK &&& A_BIST_W_ACCESS, negedge A_BIST_DIN, 1.0 ,1.0, notifier,,,A_BIST_CLK_DELAY, A_BIST_DIN_DELAY); + $setuphold(posedge A_BIST_CLK &&& A_BIST_W_ACCESS, posedge A_BIST_BM, 1.0 ,1.0, notifier,,,A_BIST_CLK_DELAY, A_BIST_BM_DELAY); + $setuphold(posedge A_BIST_CLK &&& A_BIST_W_ACCESS, negedge A_BIST_BM, 1.0 ,1.0, notifier,,,A_BIST_CLK_DELAY, A_BIST_BM_DELAY); + + + endspecify + +`endif + +endmodule +`endcelldefine \ No newline at end of file diff --git a/flow/platforms/ihp-sg13g2/verilog/RM_IHPSG13_1P_512x32_c2_bm_bist.v b/flow/platforms/ihp-sg13g2/verilog/RM_IHPSG13_1P_512x32_c2_bm_bist.v new file mode 100644 index 0000000000..afa8b2d014 --- /dev/null +++ b/flow/platforms/ihp-sg13g2/verilog/RM_IHPSG13_1P_512x32_c2_bm_bist.v @@ -0,0 +1,175 @@ +// ------------------------------------------------------ +// +// Copyright 2023 IHP PDK Authors +// +// Licensed under the Apache License, Version 2.0 (the "License"); +// you may not use this file except in compliance with the License. +// You may obtain a copy of the License at +// +// https://www.apache.org/licenses/LICENSE-2.0 +// +// Unless required by applicable law or agreed to in writing, software +// distributed under the License is distributed on an "AS IS" BASIS, +// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +// See the License for the specific language governing permissions and +// limitations under the License. +// +// Generated on Wed Apr 2 16:02:47 2025 +// +// ------------------------------------------------------ +`celldefine +module RM_IHPSG13_1P_512x32_c2_bm_bist ( + A_CLK, + A_MEN, + A_WEN, + A_REN, + A_ADDR, + A_DIN, + A_DLY, + A_DOUT, + A_BM, + A_BIST_CLK, + A_BIST_EN, + A_BIST_MEN, + A_BIST_WEN, + A_BIST_REN, + A_BIST_ADDR, + A_BIST_DIN, + A_BIST_BM +); + + input A_CLK; + input A_MEN; + input A_WEN; + input A_REN; + input [8:0] A_ADDR; + input [31:0] A_DIN; + input A_DLY; + output [31:0] A_DOUT; + input [31:0] A_BM; + input A_BIST_CLK; + input A_BIST_EN; + input A_BIST_MEN; + input A_BIST_WEN; + input A_BIST_REN; + input [8:0] A_BIST_ADDR; + input [31:0] A_BIST_DIN; + input [31:0] A_BIST_BM; + + +`ifdef FUNCTIONAL // functional // + + + SRAM_1P_behavioral_bm_bist #( + .P_DATA_WIDTH(32), + .P_ADDR_WIDTH(9) + ) i_SRAM_1P_behavioral_bm_bist ( + .A_CLK(A_CLK), + .A_MEN(A_MEN), + .A_WEN(A_WEN), + .A_REN(A_REN), + .A_ADDR(A_ADDR), + .A_DLY(A_DLY), + .A_DIN(A_DIN), + .A_DOUT(A_DOUT), + .A_BM(A_BM), + .A_BIST_CLK(A_BIST_CLK), + .A_BIST_EN(A_BIST_EN), + .A_BIST_MEN(A_BIST_MEN), + .A_BIST_WEN(A_BIST_WEN), + .A_BIST_REN(A_BIST_REN), + .A_BIST_ADDR(A_BIST_ADDR), + .A_BIST_DIN(A_BIST_DIN), + .A_BIST_BM(A_BIST_BM) + ); + +`else + + wire A_CLK_DELAY; + wire A_MEN_DELAY; + wire A_WEN_DELAY; + wire A_REN_DELAY; + wire [8:0] A_ADDR_DELAY; + wire [31:0] A_DIN_DELAY; + wire [31:0] A_BM_DELAY; + wire A_BIST_CLK_DELAY; + wire A_BIST_MEN_DELAY; + wire A_BIST_WEN_DELAY; + wire A_BIST_REN_DELAY; + wire [8:0] A_BIST_ADDR_DELAY; + wire [31:0] A_BIST_DIN_DELAY; + wire [31:0] A_BIST_BM_DELAY; + + reg notifier; + + wire A_RW_ACCESS = (A_WEN || A_REN) && A_MEN; + wire A_W_ACCESS = A_WEN && A_MEN; + wire A_BIST_RW_ACCESS = (A_BIST_WEN || A_BIST_REN) && A_BIST_MEN; + wire A_BIST_W_ACCESS = A_BIST_WEN && A_BIST_MEN; + + + + SRAM_1P_behavioral_bm_bist #( + .P_DATA_WIDTH(32), + .P_ADDR_WIDTH(9) + ) i_SRAM_1P_behavioral_bm_bist ( + .A_CLK(A_CLK_DELAY), + .A_MEN(A_MEN_DELAY), + .A_WEN(A_WEN_DELAY), + .A_REN(A_REN_DELAY), + .A_ADDR(A_ADDR_DELAY), + .A_DLY(A_DLY), + .A_DIN(A_DIN_DELAY), + .A_DOUT(A_DOUT), + .A_BM(A_BM_DELAY), + .A_BIST_CLK(A_BIST_CLK_DELAY), + .A_BIST_EN(A_BIST_EN), + .A_BIST_MEN(A_BIST_MEN_DELAY), + .A_BIST_WEN(A_BIST_WEN_DELAY), + .A_BIST_REN(A_BIST_REN_DELAY), + .A_BIST_ADDR(A_BIST_ADDR_DELAY), + .A_BIST_DIN(A_BIST_DIN_DELAY), + .A_BIST_BM(A_BIST_BM_DELAY) + ); + + + specify + + (posedge A_CLK *> (A_DOUT : A_DIN)) = (1.0, 1.0); + $width(posedge A_CLK, 1.0,0,notifier); + $setuphold(posedge A_CLK &&& A_MEN, posedge A_MEN, 1.0, 1.0,notifier,,,A_CLK_DELAY, A_MEN_DELAY); + $setuphold(posedge A_CLK &&& A_MEN, posedge A_REN, 1.0, 1.0,notifier,,,A_CLK_DELAY, A_REN_DELAY); + $setuphold(posedge A_CLK &&& A_MEN, posedge A_WEN, 1.0, 1.0,notifier,,,A_CLK_DELAY, A_WEN_DELAY); + $setuphold(posedge A_CLK &&& A_MEN, negedge A_MEN, 1.0, 1.0,notifier,,,A_CLK_DELAY, A_MEN_DELAY); + $setuphold(posedge A_CLK &&& A_MEN, negedge A_REN, 1.0, 1.0,notifier,,,A_CLK_DELAY, A_REN_DELAY); + $setuphold(posedge A_CLK &&& A_MEN, negedge A_WEN, 1.0, 1.0,notifier,,,A_CLK_DELAY, A_WEN_DELAY); + $setuphold(posedge A_CLK &&& A_RW_ACCESS, posedge A_ADDR, 1.0 ,1.0, notifier,,,A_CLK_DELAY, A_ADDR_DELAY); + $setuphold(posedge A_CLK &&& A_RW_ACCESS, negedge A_ADDR, 1.0 ,1.0, notifier,,,A_CLK_DELAY, A_ADDR_DELAY); + + $setuphold(posedge A_CLK &&& A_W_ACCESS, posedge A_DIN, 1.0 ,1.0, notifier,,,A_CLK_DELAY, A_DIN_DELAY); + $setuphold(posedge A_CLK &&& A_W_ACCESS, negedge A_DIN, 1.0 ,1.0, notifier,,,A_CLK_DELAY, A_DIN_DELAY); + $setuphold(posedge A_CLK &&& A_W_ACCESS, posedge A_BM, 1.0 ,1.0, notifier,,,A_CLK_DELAY, A_BM_DELAY); + $setuphold(posedge A_CLK &&& A_W_ACCESS, negedge A_BM, 1.0 ,1.0, notifier,,,A_CLK_DELAY, A_BM_DELAY); + (posedge A_BIST_CLK *> (A_DOUT : A_BIST_DIN)) = (1.0, 1.0); + $width(posedge A_BIST_CLK, 1.0,0,notifier); + $setuphold(posedge A_BIST_CLK &&& A_BIST_MEN, posedge A_BIST_MEN, 1.0, 1.0,notifier,,,A_BIST_CLK_DELAY, A_BIST_MEN_DELAY); + $setuphold(posedge A_BIST_CLK &&& A_BIST_MEN, posedge A_BIST_REN, 1.0, 1.0,notifier,,,A_BIST_CLK_DELAY, A_BIST_REN_DELAY); + $setuphold(posedge A_BIST_CLK &&& A_BIST_MEN, posedge A_BIST_WEN, 1.0, 1.0,notifier,,,A_BIST_CLK_DELAY, A_BIST_WEN_DELAY); + $setuphold(posedge A_BIST_CLK &&& A_BIST_MEN, negedge A_BIST_MEN, 1.0, 1.0,notifier,,,A_BIST_CLK_DELAY, A_BIST_MEN_DELAY); + $setuphold(posedge A_BIST_CLK &&& A_BIST_MEN, negedge A_BIST_REN, 1.0, 1.0,notifier,,,A_BIST_CLK_DELAY, A_BIST_REN_DELAY); + $setuphold(posedge A_BIST_CLK &&& A_BIST_MEN, negedge A_BIST_WEN, 1.0, 1.0,notifier,,,A_BIST_CLK_DELAY, A_BIST_WEN_DELAY); + $setuphold(posedge A_BIST_CLK &&& A_BIST_RW_ACCESS, posedge A_BIST_ADDR, 1.0 ,1.0, notifier,,,A_BIST_CLK_DELAY, A_BIST_ADDR_DELAY); + $setuphold(posedge A_BIST_CLK &&& A_BIST_RW_ACCESS, negedge A_BIST_ADDR, 1.0 ,1.0, notifier,,,A_BIST_CLK_DELAY, A_BIST_ADDR_DELAY); + + $setuphold(posedge A_BIST_CLK &&& A_BIST_W_ACCESS, posedge A_BIST_DIN, 1.0 ,1.0, notifier,,,A_BIST_CLK_DELAY, A_BIST_DIN_DELAY); + $setuphold(posedge A_BIST_CLK &&& A_BIST_W_ACCESS, negedge A_BIST_DIN, 1.0 ,1.0, notifier,,,A_BIST_CLK_DELAY, A_BIST_DIN_DELAY); + $setuphold(posedge A_BIST_CLK &&& A_BIST_W_ACCESS, posedge A_BIST_BM, 1.0 ,1.0, notifier,,,A_BIST_CLK_DELAY, A_BIST_BM_DELAY); + $setuphold(posedge A_BIST_CLK &&& A_BIST_W_ACCESS, negedge A_BIST_BM, 1.0 ,1.0, notifier,,,A_BIST_CLK_DELAY, A_BIST_BM_DELAY); + + + endspecify + +`endif + +endmodule +`endcelldefine \ No newline at end of file diff --git a/flow/platforms/ihp-sg13g2/verilog/RM_IHPSG13_1P_512x8_c3_bm_bist.v b/flow/platforms/ihp-sg13g2/verilog/RM_IHPSG13_1P_512x8_c3_bm_bist.v new file mode 100644 index 0000000000..ed35f99663 --- /dev/null +++ b/flow/platforms/ihp-sg13g2/verilog/RM_IHPSG13_1P_512x8_c3_bm_bist.v @@ -0,0 +1,175 @@ +// ------------------------------------------------------ +// +// Copyright 2025 IHP PDK Authors +// +// Licensed under the Apache License, Version 2.0 (the "License"); +// you may not use this file except in compliance with the License. +// You may obtain a copy of the License at +// +// https://www.apache.org/licenses/LICENSE-2.0 +// +// Unless required by applicable law or agreed to in writing, software +// distributed under the License is distributed on an "AS IS" BASIS, +// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +// See the License for the specific language governing permissions and +// limitations under the License. +// +// Generated on Wed Aug 27 16:20:24 2025 +// +// ------------------------------------------------------ +`celldefine +module RM_IHPSG13_1P_512x8_c3_bm_bist ( + A_CLK, + A_MEN, + A_WEN, + A_REN, + A_ADDR, + A_DIN, + A_DLY, + A_DOUT, + A_BM, + A_BIST_CLK, + A_BIST_EN, + A_BIST_MEN, + A_BIST_WEN, + A_BIST_REN, + A_BIST_ADDR, + A_BIST_DIN, + A_BIST_BM +); + + input A_CLK; + input A_MEN; + input A_WEN; + input A_REN; + input [8:0] A_ADDR; + input [7:0] A_DIN; + input A_DLY; + output [7:0] A_DOUT; + input [7:0] A_BM; + input A_BIST_CLK; + input A_BIST_EN; + input A_BIST_MEN; + input A_BIST_WEN; + input A_BIST_REN; + input [8:0] A_BIST_ADDR; + input [7:0] A_BIST_DIN; + input [7:0] A_BIST_BM; + + +`ifdef FUNCTIONAL // functional // + + + SRAM_1P_behavioral_bm_bist #( + .P_DATA_WIDTH(8), + .P_ADDR_WIDTH(9) + ) i_SRAM_1P_behavioral_bm_bist ( + .A_CLK(A_CLK), + .A_MEN(A_MEN), + .A_WEN(A_WEN), + .A_REN(A_REN), + .A_ADDR(A_ADDR), + .A_DLY(A_DLY), + .A_DIN(A_DIN), + .A_DOUT(A_DOUT), + .A_BM(A_BM), + .A_BIST_CLK(A_BIST_CLK), + .A_BIST_EN(A_BIST_EN), + .A_BIST_MEN(A_BIST_MEN), + .A_BIST_WEN(A_BIST_WEN), + .A_BIST_REN(A_BIST_REN), + .A_BIST_ADDR(A_BIST_ADDR), + .A_BIST_DIN(A_BIST_DIN), + .A_BIST_BM(A_BIST_BM) + ); + +`else + + wire A_CLK_DELAY; + wire A_MEN_DELAY; + wire A_WEN_DELAY; + wire A_REN_DELAY; + wire [8:0] A_ADDR_DELAY; + wire [7:0] A_DIN_DELAY; + wire [7:0] A_BM_DELAY; + wire A_BIST_CLK_DELAY; + wire A_BIST_MEN_DELAY; + wire A_BIST_WEN_DELAY; + wire A_BIST_REN_DELAY; + wire [8:0] A_BIST_ADDR_DELAY; + wire [7:0] A_BIST_DIN_DELAY; + wire [7:0] A_BIST_BM_DELAY; + + reg notifier; + + wire A_RW_ACCESS = (A_WEN || A_REN) && A_MEN; + wire A_W_ACCESS = A_WEN && A_MEN; + wire A_BIST_RW_ACCESS = (A_BIST_WEN || A_BIST_REN) && A_BIST_MEN; + wire A_BIST_W_ACCESS = A_BIST_WEN && A_BIST_MEN; + + + + SRAM_1P_behavioral_bm_bist #( + .P_DATA_WIDTH(8), + .P_ADDR_WIDTH(9) + ) i_SRAM_1P_behavioral_bm_bist ( + .A_CLK(A_CLK_DELAY), + .A_MEN(A_MEN_DELAY), + .A_WEN(A_WEN_DELAY), + .A_REN(A_REN_DELAY), + .A_ADDR(A_ADDR_DELAY), + .A_DLY(A_DLY), + .A_DIN(A_DIN_DELAY), + .A_DOUT(A_DOUT), + .A_BM(A_BM_DELAY), + .A_BIST_CLK(A_BIST_CLK_DELAY), + .A_BIST_EN(A_BIST_EN), + .A_BIST_MEN(A_BIST_MEN_DELAY), + .A_BIST_WEN(A_BIST_WEN_DELAY), + .A_BIST_REN(A_BIST_REN_DELAY), + .A_BIST_ADDR(A_BIST_ADDR_DELAY), + .A_BIST_DIN(A_BIST_DIN_DELAY), + .A_BIST_BM(A_BIST_BM_DELAY) + ); + + + specify + + (posedge A_CLK *> (A_DOUT : A_DIN)) = (1.0, 1.0); + $width(posedge A_CLK, 1.0,0,notifier); + $setuphold(posedge A_CLK &&& A_MEN, posedge A_MEN, 1.0, 1.0,notifier,,,A_CLK_DELAY, A_MEN_DELAY); + $setuphold(posedge A_CLK &&& A_MEN, posedge A_REN, 1.0, 1.0,notifier,,,A_CLK_DELAY, A_REN_DELAY); + $setuphold(posedge A_CLK &&& A_MEN, posedge A_WEN, 1.0, 1.0,notifier,,,A_CLK_DELAY, A_WEN_DELAY); + $setuphold(posedge A_CLK &&& A_MEN, negedge A_MEN, 1.0, 1.0,notifier,,,A_CLK_DELAY, A_MEN_DELAY); + $setuphold(posedge A_CLK &&& A_MEN, negedge A_REN, 1.0, 1.0,notifier,,,A_CLK_DELAY, A_REN_DELAY); + $setuphold(posedge A_CLK &&& A_MEN, negedge A_WEN, 1.0, 1.0,notifier,,,A_CLK_DELAY, A_WEN_DELAY); + $setuphold(posedge A_CLK &&& A_RW_ACCESS, posedge A_ADDR, 1.0 ,1.0, notifier,,,A_CLK_DELAY, A_ADDR_DELAY); + $setuphold(posedge A_CLK &&& A_RW_ACCESS, negedge A_ADDR, 1.0 ,1.0, notifier,,,A_CLK_DELAY, A_ADDR_DELAY); + + $setuphold(posedge A_CLK &&& A_W_ACCESS, posedge A_DIN, 1.0 ,1.0, notifier,,,A_CLK_DELAY, A_DIN_DELAY); + $setuphold(posedge A_CLK &&& A_W_ACCESS, negedge A_DIN, 1.0 ,1.0, notifier,,,A_CLK_DELAY, A_DIN_DELAY); + $setuphold(posedge A_CLK &&& A_W_ACCESS, posedge A_BM, 1.0 ,1.0, notifier,,,A_CLK_DELAY, A_BM_DELAY); + $setuphold(posedge A_CLK &&& A_W_ACCESS, negedge A_BM, 1.0 ,1.0, notifier,,,A_CLK_DELAY, A_BM_DELAY); + (posedge A_BIST_CLK *> (A_DOUT : A_BIST_DIN)) = (1.0, 1.0); + $width(posedge A_BIST_CLK, 1.0,0,notifier); + $setuphold(posedge A_BIST_CLK &&& A_BIST_MEN, posedge A_BIST_MEN, 1.0, 1.0,notifier,,,A_BIST_CLK_DELAY, A_BIST_MEN_DELAY); + $setuphold(posedge A_BIST_CLK &&& A_BIST_MEN, posedge A_BIST_REN, 1.0, 1.0,notifier,,,A_BIST_CLK_DELAY, A_BIST_REN_DELAY); + $setuphold(posedge A_BIST_CLK &&& A_BIST_MEN, posedge A_BIST_WEN, 1.0, 1.0,notifier,,,A_BIST_CLK_DELAY, A_BIST_WEN_DELAY); + $setuphold(posedge A_BIST_CLK &&& A_BIST_MEN, negedge A_BIST_MEN, 1.0, 1.0,notifier,,,A_BIST_CLK_DELAY, A_BIST_MEN_DELAY); + $setuphold(posedge A_BIST_CLK &&& A_BIST_MEN, negedge A_BIST_REN, 1.0, 1.0,notifier,,,A_BIST_CLK_DELAY, A_BIST_REN_DELAY); + $setuphold(posedge A_BIST_CLK &&& A_BIST_MEN, negedge A_BIST_WEN, 1.0, 1.0,notifier,,,A_BIST_CLK_DELAY, A_BIST_WEN_DELAY); + $setuphold(posedge A_BIST_CLK &&& A_BIST_RW_ACCESS, posedge A_BIST_ADDR, 1.0 ,1.0, notifier,,,A_BIST_CLK_DELAY, A_BIST_ADDR_DELAY); + $setuphold(posedge A_BIST_CLK &&& A_BIST_RW_ACCESS, negedge A_BIST_ADDR, 1.0 ,1.0, notifier,,,A_BIST_CLK_DELAY, A_BIST_ADDR_DELAY); + + $setuphold(posedge A_BIST_CLK &&& A_BIST_W_ACCESS, posedge A_BIST_DIN, 1.0 ,1.0, notifier,,,A_BIST_CLK_DELAY, A_BIST_DIN_DELAY); + $setuphold(posedge A_BIST_CLK &&& A_BIST_W_ACCESS, negedge A_BIST_DIN, 1.0 ,1.0, notifier,,,A_BIST_CLK_DELAY, A_BIST_DIN_DELAY); + $setuphold(posedge A_BIST_CLK &&& A_BIST_W_ACCESS, posedge A_BIST_BM, 1.0 ,1.0, notifier,,,A_BIST_CLK_DELAY, A_BIST_BM_DELAY); + $setuphold(posedge A_BIST_CLK &&& A_BIST_W_ACCESS, negedge A_BIST_BM, 1.0 ,1.0, notifier,,,A_BIST_CLK_DELAY, A_BIST_BM_DELAY); + + + endspecify + +`endif + +endmodule +`endcelldefine \ No newline at end of file diff --git a/flow/platforms/ihp-sg13g2/verilog/RM_IHPSG13_1P_8192x32_c4.v b/flow/platforms/ihp-sg13g2/verilog/RM_IHPSG13_1P_8192x32_c4.v new file mode 100644 index 0000000000..c4c20a4386 --- /dev/null +++ b/flow/platforms/ihp-sg13g2/verilog/RM_IHPSG13_1P_8192x32_c4.v @@ -0,0 +1,112 @@ +// ------------------------------------------------------ +// +// Copyright 2023 IHP PDK Authors +// +// Licensed under the Apache License, Version 2.0 (the "License"); +// you may not use this file except in compliance with the License. +// You may obtain a copy of the License at +// +// https://www.apache.org/licenses/LICENSE-2.0 +// +// Unless required by applicable law or agreed to in writing, software +// distributed under the License is distributed on an "AS IS" BASIS, +// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +// See the License for the specific language governing permissions and +// limitations under the License. +// +// Generated on Mon Apr 7 14:15:45 2025 +// +// ------------------------------------------------------ +`celldefine +module RM_IHPSG13_1P_8192x32_c4 ( + A_CLK, + A_MEN, + A_WEN, + A_REN, + A_ADDR, + A_DIN, + A_DLY, + A_DOUT +); + + input A_CLK; + input A_MEN; + input A_WEN; + input A_REN; + input [12:0] A_ADDR; + input [31:0] A_DIN; + input A_DLY; + output [31:0] A_DOUT; + + +`ifdef FUNCTIONAL // functional // + + + SRAM_1P_behavioral #( + .P_DATA_WIDTH(32), + .P_ADDR_WIDTH(13) + ) i_SRAM_1P_behavioral ( + .A_CLK(A_CLK), + .A_MEN(A_MEN), + .A_WEN(A_WEN), + .A_REN(A_REN), + .A_ADDR(A_ADDR), + .A_DLY(A_DLY), + .A_DIN(A_DIN), + .A_DOUT(A_DOUT) + ); + +`else + + wire A_CLK_DELAY; + wire A_MEN_DELAY; + wire A_WEN_DELAY; + wire A_REN_DELAY; + wire [12:0] A_ADDR_DELAY; + wire [31:0] A_DIN_DELAY; + + reg notifier; + + wire A_RW_ACCESS = (A_WEN || A_REN) && A_MEN; + wire A_W_ACCESS = A_WEN && A_MEN; + + + + SRAM_1P_behavioral #( + .P_DATA_WIDTH(32), + .P_ADDR_WIDTH(13) + ) i_SRAM_1P_behavioral ( + .A_CLK(A_CLK_DELAY), + .A_MEN(A_MEN_DELAY), + .A_WEN(A_WEN_DELAY), + .A_REN(A_REN_DELAY), + .A_ADDR(A_ADDR_DELAY), + .A_DLY(A_DLY), + .A_DIN(A_DIN_DELAY), + .A_DOUT(A_DOUT) + ); + + + specify + + (posedge A_CLK *> (A_DOUT : A_DIN)) = (1.0, 1.0); + $width(posedge A_CLK, 1.0,0,notifier); + $setuphold(posedge A_CLK &&& A_MEN, posedge A_MEN, 1.0, 1.0,notifier,,,A_CLK_DELAY, A_MEN_DELAY); + $setuphold(posedge A_CLK &&& A_MEN, posedge A_REN, 1.0, 1.0,notifier,,,A_CLK_DELAY, A_REN_DELAY); + $setuphold(posedge A_CLK &&& A_MEN, posedge A_WEN, 1.0, 1.0,notifier,,,A_CLK_DELAY, A_WEN_DELAY); + $setuphold(posedge A_CLK &&& A_MEN, negedge A_MEN, 1.0, 1.0,notifier,,,A_CLK_DELAY, A_MEN_DELAY); + $setuphold(posedge A_CLK &&& A_MEN, negedge A_REN, 1.0, 1.0,notifier,,,A_CLK_DELAY, A_REN_DELAY); + $setuphold(posedge A_CLK &&& A_MEN, negedge A_WEN, 1.0, 1.0,notifier,,,A_CLK_DELAY, A_WEN_DELAY); + $setuphold(posedge A_CLK &&& A_RW_ACCESS, posedge A_ADDR, 1.0 ,1.0, notifier,,,A_CLK_DELAY, A_ADDR_DELAY); + $setuphold(posedge A_CLK &&& A_RW_ACCESS, negedge A_ADDR, 1.0 ,1.0, notifier,,,A_CLK_DELAY, A_ADDR_DELAY); + + $setuphold(posedge A_CLK &&& A_W_ACCESS, posedge A_DIN, 1.0 ,1.0, notifier,,,A_CLK_DELAY, A_DIN_DELAY); + $setuphold(posedge A_CLK &&& A_W_ACCESS, negedge A_DIN, 1.0 ,1.0, notifier,,,A_CLK_DELAY, A_DIN_DELAY); + + + endspecify + +`endif + +endmodule +`endcelldefine \ No newline at end of file diff --git a/flow/platforms/ihp-sg13g2/verilog/RM_IHPSG13_2P_1024x16_c2_bm_bist.v b/flow/platforms/ihp-sg13g2/verilog/RM_IHPSG13_2P_1024x16_c2_bm_bist.v new file mode 100644 index 0000000000..6771c48e59 --- /dev/null +++ b/flow/platforms/ihp-sg13g2/verilog/RM_IHPSG13_2P_1024x16_c2_bm_bist.v @@ -0,0 +1,291 @@ +// ------------------------------------------------------ +// +// Copyright 2025 IHP PDK Authors +// +// Licensed under the Apache License, Version 2.0 (the "License"); +// you may not use this file except in compliance with the License. +// You may obtain a copy of the License at +// +// https://www.apache.org/licenses/LICENSE-2.0 +// +// Unless required by applicable law or agreed to in writing, software +// distributed under the License is distributed on an "AS IS" BASIS, +// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +// See the License for the specific language governing permissions and +// limitations under the License. +// +// Generated on Tue Sep 9 10:49:23 2025 +// +// ------------------------------------------------------ +`celldefine +module RM_IHPSG13_2P_1024x16_c2_bm_bist ( + A_CLK, + A_MEN, + A_WEN, + A_REN, + A_ADDR, + A_DIN, + A_DLY, + A_DOUT, + A_BM, + A_BIST_CLK, + A_BIST_EN, + A_BIST_MEN, + A_BIST_WEN, + A_BIST_REN, + A_BIST_ADDR, + A_BIST_DIN, + A_BIST_BM, + B_CLK, + B_MEN, + B_WEN, + B_REN, + B_ADDR, + B_DIN, + B_DLY, + B_DOUT, + B_BM, + B_BIST_CLK, + B_BIST_EN, + B_BIST_MEN, + B_BIST_WEN, + B_BIST_REN, + B_BIST_ADDR, + B_BIST_DIN, + B_BIST_BM +); + + input A_CLK; + input A_MEN; + input A_WEN; + input A_REN; + input [9:0] A_ADDR; + input [15:0] A_DIN; + input A_DLY; + output [15:0] A_DOUT; + input [15:0] A_BM; + input A_BIST_CLK; + input A_BIST_EN; + input A_BIST_MEN; + input A_BIST_WEN; + input A_BIST_REN; + input [9:0] A_BIST_ADDR; + input [15:0] A_BIST_DIN; + input [15:0] A_BIST_BM; + input B_CLK; + input B_MEN; + input B_WEN; + input B_REN; + input [9:0] B_ADDR; + input [15:0] B_DIN; + input B_DLY; + output [15:0] B_DOUT; + input [15:0] B_BM; + input B_BIST_CLK; + input B_BIST_EN; + input B_BIST_MEN; + input B_BIST_WEN; + input B_BIST_REN; + input [9:0] B_BIST_ADDR; + input [15:0] B_BIST_DIN; + input [15:0] B_BIST_BM; + + +`ifdef FUNCTIONAL // functional // + + + SRAM_2P_behavioral_bm_bist #( + .P_DATA_WIDTH(16), + .P_ADDR_WIDTH(10) + ) i_SRAM_2P_behavioral_bm_bist ( + .A_CLK(A_CLK), + .A_MEN(A_MEN), + .A_WEN(A_WEN), + .A_REN(A_REN), + .A_ADDR(A_ADDR), + .A_DLY(A_DLY), + .A_DIN(A_DIN), + .A_DOUT(A_DOUT), + .A_BM(A_BM), + .A_BIST_CLK(A_BIST_CLK), + .A_BIST_EN(A_BIST_EN), + .A_BIST_MEN(A_BIST_MEN), + .A_BIST_WEN(A_BIST_WEN), + .A_BIST_REN(A_BIST_REN), + .A_BIST_ADDR(A_BIST_ADDR), + .A_BIST_DIN(A_BIST_DIN), + .A_BIST_BM(A_BIST_BM), + .B_CLK(B_CLK), + .B_MEN(B_MEN), + .B_WEN(B_WEN), + .B_REN(B_REN), + .B_ADDR(B_ADDR), + .B_DLY(B_DLY), + .B_DIN(B_DIN), + .B_DOUT(B_DOUT), + .B_BM(B_BM), + .B_BIST_CLK(B_BIST_CLK), + .B_BIST_EN(B_BIST_EN), + .B_BIST_MEN(B_BIST_MEN), + .B_BIST_WEN(B_BIST_WEN), + .B_BIST_REN(B_BIST_REN), + .B_BIST_ADDR(B_BIST_ADDR), + .B_BIST_DIN(B_BIST_DIN), + .B_BIST_BM(B_BIST_BM) + ); + +`else + + wire A_CLK_DELAY; + wire A_MEN_DELAY; + wire A_WEN_DELAY; + wire A_REN_DELAY; + wire [9:0] A_ADDR_DELAY; + wire [15:0] A_DIN_DELAY; + wire [15:0] A_BM_DELAY; + wire A_BIST_CLK_DELAY; + wire A_BIST_MEN_DELAY; + wire A_BIST_WEN_DELAY; + wire A_BIST_REN_DELAY; + wire [9:0] A_BIST_ADDR_DELAY; + wire [15:0] A_BIST_DIN_DELAY; + wire [15:0] A_BIST_BM_DELAY; + wire B_CLK_DELAY; + wire B_MEN_DELAY; + wire B_WEN_DELAY; + wire B_REN_DELAY; + wire [9:0] B_ADDR_DELAY; + wire [15:0] B_DIN_DELAY; + wire [15:0] B_BM_DELAY; + wire B_BIST_CLK_DELAY; + wire B_BIST_MEN_DELAY; + wire B_BIST_WEN_DELAY; + wire B_BIST_REN_DELAY; + wire [9:0] B_BIST_ADDR_DELAY; + wire [15:0] B_BIST_DIN_DELAY; + wire [15:0] B_BIST_BM_DELAY; + + reg notifier; + + wire A_RW_ACCESS = (A_WEN || A_REN) && A_MEN; + wire A_W_ACCESS = A_WEN && A_MEN; + wire A_BIST_RW_ACCESS = (A_BIST_WEN || A_BIST_REN) && A_BIST_MEN; + wire A_BIST_W_ACCESS = A_BIST_WEN && A_BIST_MEN; + + wire B_RW_ACCESS = (B_WEN || B_REN) && B_MEN; + wire B_W_ACCESS = B_WEN && B_MEN; + wire B_BIST_RW_ACCESS = (B_BIST_WEN || B_BIST_REN) && B_BIST_MEN; + wire B_BIST_W_ACCESS = B_BIST_WEN && B_BIST_MEN; + + + SRAM_2P_behavioral_bm_bist #( + .P_DATA_WIDTH(16), + .P_ADDR_WIDTH(10) + ) i_SRAM_2P_behavioral_bm_bist ( + .A_CLK(A_CLK_DELAY), + .A_MEN(A_MEN_DELAY), + .A_WEN(A_WEN_DELAY), + .A_REN(A_REN_DELAY), + .A_ADDR(A_ADDR_DELAY), + .A_DLY(A_DLY), + .A_DIN(A_DIN_DELAY), + .A_DOUT(A_DOUT), + .A_BM(A_BM_DELAY), + .A_BIST_CLK(A_BIST_CLK_DELAY), + .A_BIST_EN(A_BIST_EN), + .A_BIST_MEN(A_BIST_MEN_DELAY), + .A_BIST_WEN(A_BIST_WEN_DELAY), + .A_BIST_REN(A_BIST_REN_DELAY), + .A_BIST_ADDR(A_BIST_ADDR_DELAY), + .A_BIST_DIN(A_BIST_DIN_DELAY), + .A_BIST_BM(A_BIST_BM_DELAY), + .B_CLK(B_CLK_DELAY), + .B_MEN(B_MEN_DELAY), + .B_WEN(B_WEN_DELAY), + .B_REN(B_REN_DELAY), + .B_ADDR(B_ADDR_DELAY), + .B_DLY(B_DLY), + .B_DIN(B_DIN_DELAY), + .B_DOUT(B_DOUT), + .B_BM(B_BM_DELAY), + .B_BIST_CLK(B_BIST_CLK_DELAY), + .B_BIST_EN(B_BIST_EN), + .B_BIST_MEN(B_BIST_MEN_DELAY), + .B_BIST_WEN(B_BIST_WEN_DELAY), + .B_BIST_REN(B_BIST_REN_DELAY), + .B_BIST_ADDR(B_BIST_ADDR_DELAY), + .B_BIST_DIN(B_BIST_DIN_DELAY), + .B_BIST_BM(B_BIST_BM_DELAY) + ); + + + specify + + (posedge A_CLK *> (A_DOUT : A_DIN)) = (1.0, 1.0); + $width(posedge A_CLK, 1.0,0,notifier); + $setuphold(posedge A_CLK &&& A_MEN, posedge A_MEN, 1.0, 1.0,notifier,,,A_CLK_DELAY, A_MEN_DELAY); + $setuphold(posedge A_CLK &&& A_MEN, posedge A_REN, 1.0, 1.0,notifier,,,A_CLK_DELAY, A_REN_DELAY); + $setuphold(posedge A_CLK &&& A_MEN, posedge A_WEN, 1.0, 1.0,notifier,,,A_CLK_DELAY, A_WEN_DELAY); + $setuphold(posedge A_CLK &&& A_MEN, negedge A_MEN, 1.0, 1.0,notifier,,,A_CLK_DELAY, A_MEN_DELAY); + $setuphold(posedge A_CLK &&& A_MEN, negedge A_REN, 1.0, 1.0,notifier,,,A_CLK_DELAY, A_REN_DELAY); + $setuphold(posedge A_CLK &&& A_MEN, negedge A_WEN, 1.0, 1.0,notifier,,,A_CLK_DELAY, A_WEN_DELAY); + $setuphold(posedge A_CLK &&& A_RW_ACCESS, posedge A_ADDR, 1.0 ,1.0, notifier,,,A_CLK_DELAY, A_ADDR_DELAY); + $setuphold(posedge A_CLK &&& A_RW_ACCESS, negedge A_ADDR, 1.0 ,1.0, notifier,,,A_CLK_DELAY, A_ADDR_DELAY); + + $setuphold(posedge A_CLK &&& A_W_ACCESS, posedge A_DIN, 1.0 ,1.0, notifier,,,A_CLK_DELAY, A_DIN_DELAY); + $setuphold(posedge A_CLK &&& A_W_ACCESS, negedge A_DIN, 1.0 ,1.0, notifier,,,A_CLK_DELAY, A_DIN_DELAY); + $setuphold(posedge A_CLK &&& A_W_ACCESS, posedge A_BM, 1.0 ,1.0, notifier,,,A_CLK_DELAY, A_BM_DELAY); + $setuphold(posedge A_CLK &&& A_W_ACCESS, negedge A_BM, 1.0 ,1.0, notifier,,,A_CLK_DELAY, A_BM_DELAY); + (posedge A_BIST_CLK *> (A_DOUT : A_BIST_DIN)) = (1.0, 1.0); + $width(posedge A_BIST_CLK, 1.0,0,notifier); + $setuphold(posedge A_BIST_CLK &&& A_BIST_MEN, posedge A_BIST_MEN, 1.0, 1.0,notifier,,,A_BIST_CLK_DELAY, A_BIST_MEN_DELAY); + $setuphold(posedge A_BIST_CLK &&& A_BIST_MEN, posedge A_BIST_REN, 1.0, 1.0,notifier,,,A_BIST_CLK_DELAY, A_BIST_REN_DELAY); + $setuphold(posedge A_BIST_CLK &&& A_BIST_MEN, posedge A_BIST_WEN, 1.0, 1.0,notifier,,,A_BIST_CLK_DELAY, A_BIST_WEN_DELAY); + $setuphold(posedge A_BIST_CLK &&& A_BIST_MEN, negedge A_BIST_MEN, 1.0, 1.0,notifier,,,A_BIST_CLK_DELAY, A_BIST_MEN_DELAY); + $setuphold(posedge A_BIST_CLK &&& A_BIST_MEN, negedge A_BIST_REN, 1.0, 1.0,notifier,,,A_BIST_CLK_DELAY, A_BIST_REN_DELAY); + $setuphold(posedge A_BIST_CLK &&& A_BIST_MEN, negedge A_BIST_WEN, 1.0, 1.0,notifier,,,A_BIST_CLK_DELAY, A_BIST_WEN_DELAY); + $setuphold(posedge A_BIST_CLK &&& A_BIST_RW_ACCESS, posedge A_BIST_ADDR, 1.0 ,1.0, notifier,,,A_BIST_CLK_DELAY, A_BIST_ADDR_DELAY); + $setuphold(posedge A_BIST_CLK &&& A_BIST_RW_ACCESS, negedge A_BIST_ADDR, 1.0 ,1.0, notifier,,,A_BIST_CLK_DELAY, A_BIST_ADDR_DELAY); + + $setuphold(posedge A_BIST_CLK &&& A_BIST_W_ACCESS, posedge A_BIST_DIN, 1.0 ,1.0, notifier,,,A_BIST_CLK_DELAY, A_BIST_DIN_DELAY); + $setuphold(posedge A_BIST_CLK &&& A_BIST_W_ACCESS, negedge A_BIST_DIN, 1.0 ,1.0, notifier,,,A_BIST_CLK_DELAY, A_BIST_DIN_DELAY); + $setuphold(posedge A_BIST_CLK &&& A_BIST_W_ACCESS, posedge A_BIST_BM, 1.0 ,1.0, notifier,,,A_BIST_CLK_DELAY, A_BIST_BM_DELAY); + $setuphold(posedge A_BIST_CLK &&& A_BIST_W_ACCESS, negedge A_BIST_BM, 1.0 ,1.0, notifier,,,A_BIST_CLK_DELAY, A_BIST_BM_DELAY); + + (posedge B_CLK *> (B_DOUT : B_DIN)) = (1.0, 1.0); + $width(posedge B_CLK, 1.0,0,notifier); + $setuphold(posedge B_CLK &&& B_MEN, posedge B_MEN, 1.0, 1.0,notifier,,,B_CLK_DELAY, B_MEN_DELAY); + $setuphold(posedge B_CLK &&& B_MEN, posedge B_REN, 1.0, 1.0,notifier,,,B_CLK_DELAY, B_REN_DELAY); + $setuphold(posedge B_CLK &&& B_MEN, posedge B_WEN, 1.0, 1.0,notifier,,,B_CLK_DELAY, B_WEN_DELAY); + $setuphold(posedge B_CLK &&& B_MEN, negedge B_MEN, 1.0, 1.0,notifier,,,B_CLK_DELAY, B_MEN_DELAY); + $setuphold(posedge B_CLK &&& B_MEN, negedge B_REN, 1.0, 1.0,notifier,,,B_CLK_DELAY, B_REN_DELAY); + $setuphold(posedge B_CLK &&& B_MEN, negedge B_WEN, 1.0, 1.0,notifier,,,B_CLK_DELAY, B_WEN_DELAY); + $setuphold(posedge B_CLK &&& B_RW_ACCESS, posedge B_ADDR, 1.0 ,1.0, notifier,,,B_CLK_DELAY, B_ADDR_DELAY); + $setuphold(posedge B_CLK &&& B_RW_ACCESS, negedge B_ADDR, 1.0 ,1.0, notifier,,,B_CLK_DELAY, B_ADDR_DELAY); + + $setuphold(posedge B_CLK &&& B_W_ACCESS, posedge B_DIN, 1.0 ,1.0, notifier,,,B_CLK_DELAY, B_DIN_DELAY); + $setuphold(posedge B_CLK &&& B_W_ACCESS, negedge B_DIN, 1.0 ,1.0, notifier,,,B_CLK_DELAY, B_DIN_DELAY); + $setuphold(posedge B_CLK &&& B_W_ACCESS, posedge B_BM, 1.0 ,1.0, notifier,,,B_CLK_DELAY, B_BM_DELAY); + $setuphold(posedge B_CLK &&& B_W_ACCESS, negedge B_BM, 1.0 ,1.0, notifier,,,B_CLK_DELAY, B_BM_DELAY); + (posedge B_BIST_CLK *> (B_DOUT : B_BIST_DIN)) = (1.0, 1.0); + $width(posedge B_BIST_CLK, 1.0,0,notifier); + $setuphold(posedge B_BIST_CLK &&& B_BIST_MEN, posedge B_BIST_MEN, 1.0, 1.0,notifier,,,B_BIST_CLK_DELAY, B_BIST_MEN_DELAY); + $setuphold(posedge B_BIST_CLK &&& B_BIST_MEN, posedge B_BIST_REN, 1.0, 1.0,notifier,,,B_BIST_CLK_DELAY, B_BIST_REN_DELAY); + $setuphold(posedge B_BIST_CLK &&& B_BIST_MEN, posedge B_BIST_WEN, 1.0, 1.0,notifier,,,B_BIST_CLK_DELAY, B_BIST_WEN_DELAY); + $setuphold(posedge B_BIST_CLK &&& B_BIST_MEN, negedge B_BIST_MEN, 1.0, 1.0,notifier,,,B_BIST_CLK_DELAY, B_BIST_MEN_DELAY); + $setuphold(posedge B_BIST_CLK &&& B_BIST_MEN, negedge B_BIST_REN, 1.0, 1.0,notifier,,,B_BIST_CLK_DELAY, B_BIST_REN_DELAY); + $setuphold(posedge B_BIST_CLK &&& B_BIST_MEN, negedge B_BIST_WEN, 1.0, 1.0,notifier,,,B_BIST_CLK_DELAY, B_BIST_WEN_DELAY); + $setuphold(posedge B_BIST_CLK &&& B_BIST_RW_ACCESS, posedge B_BIST_ADDR, 1.0 ,1.0, notifier,,,B_BIST_CLK_DELAY, B_BIST_ADDR_DELAY); + $setuphold(posedge B_BIST_CLK &&& B_BIST_RW_ACCESS, negedge B_BIST_ADDR, 1.0 ,1.0, notifier,,,B_BIST_CLK_DELAY, B_BIST_ADDR_DELAY); + + $setuphold(posedge B_BIST_CLK &&& B_BIST_W_ACCESS, posedge B_BIST_DIN, 1.0 ,1.0, notifier,,,B_BIST_CLK_DELAY, B_BIST_DIN_DELAY); + $setuphold(posedge B_BIST_CLK &&& B_BIST_W_ACCESS, negedge B_BIST_DIN, 1.0 ,1.0, notifier,,,B_BIST_CLK_DELAY, B_BIST_DIN_DELAY); + $setuphold(posedge B_BIST_CLK &&& B_BIST_W_ACCESS, posedge B_BIST_BM, 1.0 ,1.0, notifier,,,B_BIST_CLK_DELAY, B_BIST_BM_DELAY); + $setuphold(posedge B_BIST_CLK &&& B_BIST_W_ACCESS, negedge B_BIST_BM, 1.0 ,1.0, notifier,,,B_BIST_CLK_DELAY, B_BIST_BM_DELAY); + + endspecify + +`endif + +endmodule +`endcelldefine \ No newline at end of file diff --git a/flow/platforms/ihp-sg13g2/verilog/RM_IHPSG13_2P_1024x32_c2_bm_bist.v b/flow/platforms/ihp-sg13g2/verilog/RM_IHPSG13_2P_1024x32_c2_bm_bist.v new file mode 100644 index 0000000000..5d3aba84fd --- /dev/null +++ b/flow/platforms/ihp-sg13g2/verilog/RM_IHPSG13_2P_1024x32_c2_bm_bist.v @@ -0,0 +1,291 @@ +// ------------------------------------------------------ +// +// Copyright 2025 IHP PDK Authors +// +// Licensed under the Apache License, Version 2.0 (the "License"); +// you may not use this file except in compliance with the License. +// You may obtain a copy of the License at +// +// https://www.apache.org/licenses/LICENSE-2.0 +// +// Unless required by applicable law or agreed to in writing, software +// distributed under the License is distributed on an "AS IS" BASIS, +// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +// See the License for the specific language governing permissions and +// limitations under the License. +// +// Generated on Wed Aug 27 13:09:02 2025 +// +// ------------------------------------------------------ +`celldefine +module RM_IHPSG13_2P_1024x32_c2_bm_bist ( + A_CLK, + A_MEN, + A_WEN, + A_REN, + A_ADDR, + A_DIN, + A_DLY, + A_DOUT, + A_BM, + A_BIST_CLK, + A_BIST_EN, + A_BIST_MEN, + A_BIST_WEN, + A_BIST_REN, + A_BIST_ADDR, + A_BIST_DIN, + A_BIST_BM, + B_CLK, + B_MEN, + B_WEN, + B_REN, + B_ADDR, + B_DIN, + B_DLY, + B_DOUT, + B_BM, + B_BIST_CLK, + B_BIST_EN, + B_BIST_MEN, + B_BIST_WEN, + B_BIST_REN, + B_BIST_ADDR, + B_BIST_DIN, + B_BIST_BM +); + + input A_CLK; + input A_MEN; + input A_WEN; + input A_REN; + input [9:0] A_ADDR; + input [31:0] A_DIN; + input A_DLY; + output [31:0] A_DOUT; + input [31:0] A_BM; + input A_BIST_CLK; + input A_BIST_EN; + input A_BIST_MEN; + input A_BIST_WEN; + input A_BIST_REN; + input [9:0] A_BIST_ADDR; + input [31:0] A_BIST_DIN; + input [31:0] A_BIST_BM; + input B_CLK; + input B_MEN; + input B_WEN; + input B_REN; + input [9:0] B_ADDR; + input [31:0] B_DIN; + input B_DLY; + output [31:0] B_DOUT; + input [31:0] B_BM; + input B_BIST_CLK; + input B_BIST_EN; + input B_BIST_MEN; + input B_BIST_WEN; + input B_BIST_REN; + input [9:0] B_BIST_ADDR; + input [31:0] B_BIST_DIN; + input [31:0] B_BIST_BM; + + +`ifdef FUNCTIONAL // functional // + + + SRAM_2P_behavioral_bm_bist #( + .P_DATA_WIDTH(32), + .P_ADDR_WIDTH(10) + ) i_SRAM_2P_behavioral_bm_bist ( + .A_CLK(A_CLK), + .A_MEN(A_MEN), + .A_WEN(A_WEN), + .A_REN(A_REN), + .A_ADDR(A_ADDR), + .A_DLY(A_DLY), + .A_DIN(A_DIN), + .A_DOUT(A_DOUT), + .A_BM(A_BM), + .A_BIST_CLK(A_BIST_CLK), + .A_BIST_EN(A_BIST_EN), + .A_BIST_MEN(A_BIST_MEN), + .A_BIST_WEN(A_BIST_WEN), + .A_BIST_REN(A_BIST_REN), + .A_BIST_ADDR(A_BIST_ADDR), + .A_BIST_DIN(A_BIST_DIN), + .A_BIST_BM(A_BIST_BM), + .B_CLK(B_CLK), + .B_MEN(B_MEN), + .B_WEN(B_WEN), + .B_REN(B_REN), + .B_ADDR(B_ADDR), + .B_DLY(B_DLY), + .B_DIN(B_DIN), + .B_DOUT(B_DOUT), + .B_BM(B_BM), + .B_BIST_CLK(B_BIST_CLK), + .B_BIST_EN(B_BIST_EN), + .B_BIST_MEN(B_BIST_MEN), + .B_BIST_WEN(B_BIST_WEN), + .B_BIST_REN(B_BIST_REN), + .B_BIST_ADDR(B_BIST_ADDR), + .B_BIST_DIN(B_BIST_DIN), + .B_BIST_BM(B_BIST_BM) + ); + +`else + + wire A_CLK_DELAY; + wire A_MEN_DELAY; + wire A_WEN_DELAY; + wire A_REN_DELAY; + wire [9:0] A_ADDR_DELAY; + wire [31:0] A_DIN_DELAY; + wire [31:0] A_BM_DELAY; + wire A_BIST_CLK_DELAY; + wire A_BIST_MEN_DELAY; + wire A_BIST_WEN_DELAY; + wire A_BIST_REN_DELAY; + wire [9:0] A_BIST_ADDR_DELAY; + wire [31:0] A_BIST_DIN_DELAY; + wire [31:0] A_BIST_BM_DELAY; + wire B_CLK_DELAY; + wire B_MEN_DELAY; + wire B_WEN_DELAY; + wire B_REN_DELAY; + wire [9:0] B_ADDR_DELAY; + wire [31:0] B_DIN_DELAY; + wire [31:0] B_BM_DELAY; + wire B_BIST_CLK_DELAY; + wire B_BIST_MEN_DELAY; + wire B_BIST_WEN_DELAY; + wire B_BIST_REN_DELAY; + wire [9:0] B_BIST_ADDR_DELAY; + wire [31:0] B_BIST_DIN_DELAY; + wire [31:0] B_BIST_BM_DELAY; + + reg notifier; + + wire A_RW_ACCESS = (A_WEN || A_REN) && A_MEN; + wire A_W_ACCESS = A_WEN && A_MEN; + wire A_BIST_RW_ACCESS = (A_BIST_WEN || A_BIST_REN) && A_BIST_MEN; + wire A_BIST_W_ACCESS = A_BIST_WEN && A_BIST_MEN; + + wire B_RW_ACCESS = (B_WEN || B_REN) && B_MEN; + wire B_W_ACCESS = B_WEN && B_MEN; + wire B_BIST_RW_ACCESS = (B_BIST_WEN || B_BIST_REN) && B_BIST_MEN; + wire B_BIST_W_ACCESS = B_BIST_WEN && B_BIST_MEN; + + + SRAM_2P_behavioral_bm_bist #( + .P_DATA_WIDTH(32), + .P_ADDR_WIDTH(10) + ) i_SRAM_2P_behavioral_bm_bist ( + .A_CLK(A_CLK_DELAY), + .A_MEN(A_MEN_DELAY), + .A_WEN(A_WEN_DELAY), + .A_REN(A_REN_DELAY), + .A_ADDR(A_ADDR_DELAY), + .A_DLY(A_DLY), + .A_DIN(A_DIN_DELAY), + .A_DOUT(A_DOUT), + .A_BM(A_BM_DELAY), + .A_BIST_CLK(A_BIST_CLK_DELAY), + .A_BIST_EN(A_BIST_EN), + .A_BIST_MEN(A_BIST_MEN_DELAY), + .A_BIST_WEN(A_BIST_WEN_DELAY), + .A_BIST_REN(A_BIST_REN_DELAY), + .A_BIST_ADDR(A_BIST_ADDR_DELAY), + .A_BIST_DIN(A_BIST_DIN_DELAY), + .A_BIST_BM(A_BIST_BM_DELAY), + .B_CLK(B_CLK_DELAY), + .B_MEN(B_MEN_DELAY), + .B_WEN(B_WEN_DELAY), + .B_REN(B_REN_DELAY), + .B_ADDR(B_ADDR_DELAY), + .B_DLY(B_DLY), + .B_DIN(B_DIN_DELAY), + .B_DOUT(B_DOUT), + .B_BM(B_BM_DELAY), + .B_BIST_CLK(B_BIST_CLK_DELAY), + .B_BIST_EN(B_BIST_EN), + .B_BIST_MEN(B_BIST_MEN_DELAY), + .B_BIST_WEN(B_BIST_WEN_DELAY), + .B_BIST_REN(B_BIST_REN_DELAY), + .B_BIST_ADDR(B_BIST_ADDR_DELAY), + .B_BIST_DIN(B_BIST_DIN_DELAY), + .B_BIST_BM(B_BIST_BM_DELAY) + ); + + + specify + + (posedge A_CLK *> (A_DOUT : A_DIN)) = (1.0, 1.0); + $width(posedge A_CLK, 1.0,0,notifier); + $setuphold(posedge A_CLK &&& A_MEN, posedge A_MEN, 1.0, 1.0,notifier,,,A_CLK_DELAY, A_MEN_DELAY); + $setuphold(posedge A_CLK &&& A_MEN, posedge A_REN, 1.0, 1.0,notifier,,,A_CLK_DELAY, A_REN_DELAY); + $setuphold(posedge A_CLK &&& A_MEN, posedge A_WEN, 1.0, 1.0,notifier,,,A_CLK_DELAY, A_WEN_DELAY); + $setuphold(posedge A_CLK &&& A_MEN, negedge A_MEN, 1.0, 1.0,notifier,,,A_CLK_DELAY, A_MEN_DELAY); + $setuphold(posedge A_CLK &&& A_MEN, negedge A_REN, 1.0, 1.0,notifier,,,A_CLK_DELAY, A_REN_DELAY); + $setuphold(posedge A_CLK &&& A_MEN, negedge A_WEN, 1.0, 1.0,notifier,,,A_CLK_DELAY, A_WEN_DELAY); + $setuphold(posedge A_CLK &&& A_RW_ACCESS, posedge A_ADDR, 1.0 ,1.0, notifier,,,A_CLK_DELAY, A_ADDR_DELAY); + $setuphold(posedge A_CLK &&& A_RW_ACCESS, negedge A_ADDR, 1.0 ,1.0, notifier,,,A_CLK_DELAY, A_ADDR_DELAY); + + $setuphold(posedge A_CLK &&& A_W_ACCESS, posedge A_DIN, 1.0 ,1.0, notifier,,,A_CLK_DELAY, A_DIN_DELAY); + $setuphold(posedge A_CLK &&& A_W_ACCESS, negedge A_DIN, 1.0 ,1.0, notifier,,,A_CLK_DELAY, A_DIN_DELAY); + $setuphold(posedge A_CLK &&& A_W_ACCESS, posedge A_BM, 1.0 ,1.0, notifier,,,A_CLK_DELAY, A_BM_DELAY); + $setuphold(posedge A_CLK &&& A_W_ACCESS, negedge A_BM, 1.0 ,1.0, notifier,,,A_CLK_DELAY, A_BM_DELAY); + (posedge A_BIST_CLK *> (A_DOUT : A_BIST_DIN)) = (1.0, 1.0); + $width(posedge A_BIST_CLK, 1.0,0,notifier); + $setuphold(posedge A_BIST_CLK &&& A_BIST_MEN, posedge A_BIST_MEN, 1.0, 1.0,notifier,,,A_BIST_CLK_DELAY, A_BIST_MEN_DELAY); + $setuphold(posedge A_BIST_CLK &&& A_BIST_MEN, posedge A_BIST_REN, 1.0, 1.0,notifier,,,A_BIST_CLK_DELAY, A_BIST_REN_DELAY); + $setuphold(posedge A_BIST_CLK &&& A_BIST_MEN, posedge A_BIST_WEN, 1.0, 1.0,notifier,,,A_BIST_CLK_DELAY, A_BIST_WEN_DELAY); + $setuphold(posedge A_BIST_CLK &&& A_BIST_MEN, negedge A_BIST_MEN, 1.0, 1.0,notifier,,,A_BIST_CLK_DELAY, A_BIST_MEN_DELAY); + $setuphold(posedge A_BIST_CLK &&& A_BIST_MEN, negedge A_BIST_REN, 1.0, 1.0,notifier,,,A_BIST_CLK_DELAY, A_BIST_REN_DELAY); + $setuphold(posedge A_BIST_CLK &&& A_BIST_MEN, negedge A_BIST_WEN, 1.0, 1.0,notifier,,,A_BIST_CLK_DELAY, A_BIST_WEN_DELAY); + $setuphold(posedge A_BIST_CLK &&& A_BIST_RW_ACCESS, posedge A_BIST_ADDR, 1.0 ,1.0, notifier,,,A_BIST_CLK_DELAY, A_BIST_ADDR_DELAY); + $setuphold(posedge A_BIST_CLK &&& A_BIST_RW_ACCESS, negedge A_BIST_ADDR, 1.0 ,1.0, notifier,,,A_BIST_CLK_DELAY, A_BIST_ADDR_DELAY); + + $setuphold(posedge A_BIST_CLK &&& A_BIST_W_ACCESS, posedge A_BIST_DIN, 1.0 ,1.0, notifier,,,A_BIST_CLK_DELAY, A_BIST_DIN_DELAY); + $setuphold(posedge A_BIST_CLK &&& A_BIST_W_ACCESS, negedge A_BIST_DIN, 1.0 ,1.0, notifier,,,A_BIST_CLK_DELAY, A_BIST_DIN_DELAY); + $setuphold(posedge A_BIST_CLK &&& A_BIST_W_ACCESS, posedge A_BIST_BM, 1.0 ,1.0, notifier,,,A_BIST_CLK_DELAY, A_BIST_BM_DELAY); + $setuphold(posedge A_BIST_CLK &&& A_BIST_W_ACCESS, negedge A_BIST_BM, 1.0 ,1.0, notifier,,,A_BIST_CLK_DELAY, A_BIST_BM_DELAY); + + (posedge B_CLK *> (B_DOUT : B_DIN)) = (1.0, 1.0); + $width(posedge B_CLK, 1.0,0,notifier); + $setuphold(posedge B_CLK &&& B_MEN, posedge B_MEN, 1.0, 1.0,notifier,,,B_CLK_DELAY, B_MEN_DELAY); + $setuphold(posedge B_CLK &&& B_MEN, posedge B_REN, 1.0, 1.0,notifier,,,B_CLK_DELAY, B_REN_DELAY); + $setuphold(posedge B_CLK &&& B_MEN, posedge B_WEN, 1.0, 1.0,notifier,,,B_CLK_DELAY, B_WEN_DELAY); + $setuphold(posedge B_CLK &&& B_MEN, negedge B_MEN, 1.0, 1.0,notifier,,,B_CLK_DELAY, B_MEN_DELAY); + $setuphold(posedge B_CLK &&& B_MEN, negedge B_REN, 1.0, 1.0,notifier,,,B_CLK_DELAY, B_REN_DELAY); + $setuphold(posedge B_CLK &&& B_MEN, negedge B_WEN, 1.0, 1.0,notifier,,,B_CLK_DELAY, B_WEN_DELAY); + $setuphold(posedge B_CLK &&& B_RW_ACCESS, posedge B_ADDR, 1.0 ,1.0, notifier,,,B_CLK_DELAY, B_ADDR_DELAY); + $setuphold(posedge B_CLK &&& B_RW_ACCESS, negedge B_ADDR, 1.0 ,1.0, notifier,,,B_CLK_DELAY, B_ADDR_DELAY); + + $setuphold(posedge B_CLK &&& B_W_ACCESS, posedge B_DIN, 1.0 ,1.0, notifier,,,B_CLK_DELAY, B_DIN_DELAY); + $setuphold(posedge B_CLK &&& B_W_ACCESS, negedge B_DIN, 1.0 ,1.0, notifier,,,B_CLK_DELAY, B_DIN_DELAY); + $setuphold(posedge B_CLK &&& B_W_ACCESS, posedge B_BM, 1.0 ,1.0, notifier,,,B_CLK_DELAY, B_BM_DELAY); + $setuphold(posedge B_CLK &&& B_W_ACCESS, negedge B_BM, 1.0 ,1.0, notifier,,,B_CLK_DELAY, B_BM_DELAY); + (posedge B_BIST_CLK *> (B_DOUT : B_BIST_DIN)) = (1.0, 1.0); + $width(posedge B_BIST_CLK, 1.0,0,notifier); + $setuphold(posedge B_BIST_CLK &&& B_BIST_MEN, posedge B_BIST_MEN, 1.0, 1.0,notifier,,,B_BIST_CLK_DELAY, B_BIST_MEN_DELAY); + $setuphold(posedge B_BIST_CLK &&& B_BIST_MEN, posedge B_BIST_REN, 1.0, 1.0,notifier,,,B_BIST_CLK_DELAY, B_BIST_REN_DELAY); + $setuphold(posedge B_BIST_CLK &&& B_BIST_MEN, posedge B_BIST_WEN, 1.0, 1.0,notifier,,,B_BIST_CLK_DELAY, B_BIST_WEN_DELAY); + $setuphold(posedge B_BIST_CLK &&& B_BIST_MEN, negedge B_BIST_MEN, 1.0, 1.0,notifier,,,B_BIST_CLK_DELAY, B_BIST_MEN_DELAY); + $setuphold(posedge B_BIST_CLK &&& B_BIST_MEN, negedge B_BIST_REN, 1.0, 1.0,notifier,,,B_BIST_CLK_DELAY, B_BIST_REN_DELAY); + $setuphold(posedge B_BIST_CLK &&& B_BIST_MEN, negedge B_BIST_WEN, 1.0, 1.0,notifier,,,B_BIST_CLK_DELAY, B_BIST_WEN_DELAY); + $setuphold(posedge B_BIST_CLK &&& B_BIST_RW_ACCESS, posedge B_BIST_ADDR, 1.0 ,1.0, notifier,,,B_BIST_CLK_DELAY, B_BIST_ADDR_DELAY); + $setuphold(posedge B_BIST_CLK &&& B_BIST_RW_ACCESS, negedge B_BIST_ADDR, 1.0 ,1.0, notifier,,,B_BIST_CLK_DELAY, B_BIST_ADDR_DELAY); + + $setuphold(posedge B_BIST_CLK &&& B_BIST_W_ACCESS, posedge B_BIST_DIN, 1.0 ,1.0, notifier,,,B_BIST_CLK_DELAY, B_BIST_DIN_DELAY); + $setuphold(posedge B_BIST_CLK &&& B_BIST_W_ACCESS, negedge B_BIST_DIN, 1.0 ,1.0, notifier,,,B_BIST_CLK_DELAY, B_BIST_DIN_DELAY); + $setuphold(posedge B_BIST_CLK &&& B_BIST_W_ACCESS, posedge B_BIST_BM, 1.0 ,1.0, notifier,,,B_BIST_CLK_DELAY, B_BIST_BM_DELAY); + $setuphold(posedge B_BIST_CLK &&& B_BIST_W_ACCESS, negedge B_BIST_BM, 1.0 ,1.0, notifier,,,B_BIST_CLK_DELAY, B_BIST_BM_DELAY); + + endspecify + +`endif + +endmodule +`endcelldefine \ No newline at end of file diff --git a/flow/platforms/ihp-sg13g2/verilog/RM_IHPSG13_2P_256x16_c2_bm_bist.v b/flow/platforms/ihp-sg13g2/verilog/RM_IHPSG13_2P_256x16_c2_bm_bist.v new file mode 100644 index 0000000000..d868c1c123 --- /dev/null +++ b/flow/platforms/ihp-sg13g2/verilog/RM_IHPSG13_2P_256x16_c2_bm_bist.v @@ -0,0 +1,291 @@ +// ------------------------------------------------------ +// +// Copyright 2025 IHP PDK Authors +// +// Licensed under the Apache License, Version 2.0 (the "License"); +// you may not use this file except in compliance with the License. +// You may obtain a copy of the License at +// +// https://www.apache.org/licenses/LICENSE-2.0 +// +// Unless required by applicable law or agreed to in writing, software +// distributed under the License is distributed on an "AS IS" BASIS, +// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +// See the License for the specific language governing permissions and +// limitations under the License. +// +// Generated on Wed Aug 27 13:19:47 2025 +// +// ------------------------------------------------------ +`celldefine +module RM_IHPSG13_2P_256x16_c2_bm_bist ( + A_CLK, + A_MEN, + A_WEN, + A_REN, + A_ADDR, + A_DIN, + A_DLY, + A_DOUT, + A_BM, + A_BIST_CLK, + A_BIST_EN, + A_BIST_MEN, + A_BIST_WEN, + A_BIST_REN, + A_BIST_ADDR, + A_BIST_DIN, + A_BIST_BM, + B_CLK, + B_MEN, + B_WEN, + B_REN, + B_ADDR, + B_DIN, + B_DLY, + B_DOUT, + B_BM, + B_BIST_CLK, + B_BIST_EN, + B_BIST_MEN, + B_BIST_WEN, + B_BIST_REN, + B_BIST_ADDR, + B_BIST_DIN, + B_BIST_BM +); + + input A_CLK; + input A_MEN; + input A_WEN; + input A_REN; + input [7:0] A_ADDR; + input [15:0] A_DIN; + input A_DLY; + output [15:0] A_DOUT; + input [15:0] A_BM; + input A_BIST_CLK; + input A_BIST_EN; + input A_BIST_MEN; + input A_BIST_WEN; + input A_BIST_REN; + input [7:0] A_BIST_ADDR; + input [15:0] A_BIST_DIN; + input [15:0] A_BIST_BM; + input B_CLK; + input B_MEN; + input B_WEN; + input B_REN; + input [7:0] B_ADDR; + input [15:0] B_DIN; + input B_DLY; + output [15:0] B_DOUT; + input [15:0] B_BM; + input B_BIST_CLK; + input B_BIST_EN; + input B_BIST_MEN; + input B_BIST_WEN; + input B_BIST_REN; + input [7:0] B_BIST_ADDR; + input [15:0] B_BIST_DIN; + input [15:0] B_BIST_BM; + + +`ifdef FUNCTIONAL // functional // + + + SRAM_2P_behavioral_bm_bist #( + .P_DATA_WIDTH(16), + .P_ADDR_WIDTH(8) + ) i_SRAM_2P_behavioral_bm_bist ( + .A_CLK(A_CLK), + .A_MEN(A_MEN), + .A_WEN(A_WEN), + .A_REN(A_REN), + .A_ADDR(A_ADDR), + .A_DLY(A_DLY), + .A_DIN(A_DIN), + .A_DOUT(A_DOUT), + .A_BM(A_BM), + .A_BIST_CLK(A_BIST_CLK), + .A_BIST_EN(A_BIST_EN), + .A_BIST_MEN(A_BIST_MEN), + .A_BIST_WEN(A_BIST_WEN), + .A_BIST_REN(A_BIST_REN), + .A_BIST_ADDR(A_BIST_ADDR), + .A_BIST_DIN(A_BIST_DIN), + .A_BIST_BM(A_BIST_BM), + .B_CLK(B_CLK), + .B_MEN(B_MEN), + .B_WEN(B_WEN), + .B_REN(B_REN), + .B_ADDR(B_ADDR), + .B_DLY(B_DLY), + .B_DIN(B_DIN), + .B_DOUT(B_DOUT), + .B_BM(B_BM), + .B_BIST_CLK(B_BIST_CLK), + .B_BIST_EN(B_BIST_EN), + .B_BIST_MEN(B_BIST_MEN), + .B_BIST_WEN(B_BIST_WEN), + .B_BIST_REN(B_BIST_REN), + .B_BIST_ADDR(B_BIST_ADDR), + .B_BIST_DIN(B_BIST_DIN), + .B_BIST_BM(B_BIST_BM) + ); + +`else + + wire A_CLK_DELAY; + wire A_MEN_DELAY; + wire A_WEN_DELAY; + wire A_REN_DELAY; + wire [7:0] A_ADDR_DELAY; + wire [15:0] A_DIN_DELAY; + wire [15:0] A_BM_DELAY; + wire A_BIST_CLK_DELAY; + wire A_BIST_MEN_DELAY; + wire A_BIST_WEN_DELAY; + wire A_BIST_REN_DELAY; + wire [7:0] A_BIST_ADDR_DELAY; + wire [15:0] A_BIST_DIN_DELAY; + wire [15:0] A_BIST_BM_DELAY; + wire B_CLK_DELAY; + wire B_MEN_DELAY; + wire B_WEN_DELAY; + wire B_REN_DELAY; + wire [7:0] B_ADDR_DELAY; + wire [15:0] B_DIN_DELAY; + wire [15:0] B_BM_DELAY; + wire B_BIST_CLK_DELAY; + wire B_BIST_MEN_DELAY; + wire B_BIST_WEN_DELAY; + wire B_BIST_REN_DELAY; + wire [7:0] B_BIST_ADDR_DELAY; + wire [15:0] B_BIST_DIN_DELAY; + wire [15:0] B_BIST_BM_DELAY; + + reg notifier; + + wire A_RW_ACCESS = (A_WEN || A_REN) && A_MEN; + wire A_W_ACCESS = A_WEN && A_MEN; + wire A_BIST_RW_ACCESS = (A_BIST_WEN || A_BIST_REN) && A_BIST_MEN; + wire A_BIST_W_ACCESS = A_BIST_WEN && A_BIST_MEN; + + wire B_RW_ACCESS = (B_WEN || B_REN) && B_MEN; + wire B_W_ACCESS = B_WEN && B_MEN; + wire B_BIST_RW_ACCESS = (B_BIST_WEN || B_BIST_REN) && B_BIST_MEN; + wire B_BIST_W_ACCESS = B_BIST_WEN && B_BIST_MEN; + + + SRAM_2P_behavioral_bm_bist #( + .P_DATA_WIDTH(16), + .P_ADDR_WIDTH(8) + ) i_SRAM_2P_behavioral_bm_bist ( + .A_CLK(A_CLK_DELAY), + .A_MEN(A_MEN_DELAY), + .A_WEN(A_WEN_DELAY), + .A_REN(A_REN_DELAY), + .A_ADDR(A_ADDR_DELAY), + .A_DLY(A_DLY), + .A_DIN(A_DIN_DELAY), + .A_DOUT(A_DOUT), + .A_BM(A_BM_DELAY), + .A_BIST_CLK(A_BIST_CLK_DELAY), + .A_BIST_EN(A_BIST_EN), + .A_BIST_MEN(A_BIST_MEN_DELAY), + .A_BIST_WEN(A_BIST_WEN_DELAY), + .A_BIST_REN(A_BIST_REN_DELAY), + .A_BIST_ADDR(A_BIST_ADDR_DELAY), + .A_BIST_DIN(A_BIST_DIN_DELAY), + .A_BIST_BM(A_BIST_BM_DELAY), + .B_CLK(B_CLK_DELAY), + .B_MEN(B_MEN_DELAY), + .B_WEN(B_WEN_DELAY), + .B_REN(B_REN_DELAY), + .B_ADDR(B_ADDR_DELAY), + .B_DLY(B_DLY), + .B_DIN(B_DIN_DELAY), + .B_DOUT(B_DOUT), + .B_BM(B_BM_DELAY), + .B_BIST_CLK(B_BIST_CLK_DELAY), + .B_BIST_EN(B_BIST_EN), + .B_BIST_MEN(B_BIST_MEN_DELAY), + .B_BIST_WEN(B_BIST_WEN_DELAY), + .B_BIST_REN(B_BIST_REN_DELAY), + .B_BIST_ADDR(B_BIST_ADDR_DELAY), + .B_BIST_DIN(B_BIST_DIN_DELAY), + .B_BIST_BM(B_BIST_BM_DELAY) + ); + + + specify + + (posedge A_CLK *> (A_DOUT : A_DIN)) = (1.0, 1.0); + $width(posedge A_CLK, 1.0,0,notifier); + $setuphold(posedge A_CLK &&& A_MEN, posedge A_MEN, 1.0, 1.0,notifier,,,A_CLK_DELAY, A_MEN_DELAY); + $setuphold(posedge A_CLK &&& A_MEN, posedge A_REN, 1.0, 1.0,notifier,,,A_CLK_DELAY, A_REN_DELAY); + $setuphold(posedge A_CLK &&& A_MEN, posedge A_WEN, 1.0, 1.0,notifier,,,A_CLK_DELAY, A_WEN_DELAY); + $setuphold(posedge A_CLK &&& A_MEN, negedge A_MEN, 1.0, 1.0,notifier,,,A_CLK_DELAY, A_MEN_DELAY); + $setuphold(posedge A_CLK &&& A_MEN, negedge A_REN, 1.0, 1.0,notifier,,,A_CLK_DELAY, A_REN_DELAY); + $setuphold(posedge A_CLK &&& A_MEN, negedge A_WEN, 1.0, 1.0,notifier,,,A_CLK_DELAY, A_WEN_DELAY); + $setuphold(posedge A_CLK &&& A_RW_ACCESS, posedge A_ADDR, 1.0 ,1.0, notifier,,,A_CLK_DELAY, A_ADDR_DELAY); + $setuphold(posedge A_CLK &&& A_RW_ACCESS, negedge A_ADDR, 1.0 ,1.0, notifier,,,A_CLK_DELAY, A_ADDR_DELAY); + + $setuphold(posedge A_CLK &&& A_W_ACCESS, posedge A_DIN, 1.0 ,1.0, notifier,,,A_CLK_DELAY, A_DIN_DELAY); + $setuphold(posedge A_CLK &&& A_W_ACCESS, negedge A_DIN, 1.0 ,1.0, notifier,,,A_CLK_DELAY, A_DIN_DELAY); + $setuphold(posedge A_CLK &&& A_W_ACCESS, posedge A_BM, 1.0 ,1.0, notifier,,,A_CLK_DELAY, A_BM_DELAY); + $setuphold(posedge A_CLK &&& A_W_ACCESS, negedge A_BM, 1.0 ,1.0, notifier,,,A_CLK_DELAY, A_BM_DELAY); + (posedge A_BIST_CLK *> (A_DOUT : A_BIST_DIN)) = (1.0, 1.0); + $width(posedge A_BIST_CLK, 1.0,0,notifier); + $setuphold(posedge A_BIST_CLK &&& A_BIST_MEN, posedge A_BIST_MEN, 1.0, 1.0,notifier,,,A_BIST_CLK_DELAY, A_BIST_MEN_DELAY); + $setuphold(posedge A_BIST_CLK &&& A_BIST_MEN, posedge A_BIST_REN, 1.0, 1.0,notifier,,,A_BIST_CLK_DELAY, A_BIST_REN_DELAY); + $setuphold(posedge A_BIST_CLK &&& A_BIST_MEN, posedge A_BIST_WEN, 1.0, 1.0,notifier,,,A_BIST_CLK_DELAY, A_BIST_WEN_DELAY); + $setuphold(posedge A_BIST_CLK &&& A_BIST_MEN, negedge A_BIST_MEN, 1.0, 1.0,notifier,,,A_BIST_CLK_DELAY, A_BIST_MEN_DELAY); + $setuphold(posedge A_BIST_CLK &&& A_BIST_MEN, negedge A_BIST_REN, 1.0, 1.0,notifier,,,A_BIST_CLK_DELAY, A_BIST_REN_DELAY); + $setuphold(posedge A_BIST_CLK &&& A_BIST_MEN, negedge A_BIST_WEN, 1.0, 1.0,notifier,,,A_BIST_CLK_DELAY, A_BIST_WEN_DELAY); + $setuphold(posedge A_BIST_CLK &&& A_BIST_RW_ACCESS, posedge A_BIST_ADDR, 1.0 ,1.0, notifier,,,A_BIST_CLK_DELAY, A_BIST_ADDR_DELAY); + $setuphold(posedge A_BIST_CLK &&& A_BIST_RW_ACCESS, negedge A_BIST_ADDR, 1.0 ,1.0, notifier,,,A_BIST_CLK_DELAY, A_BIST_ADDR_DELAY); + + $setuphold(posedge A_BIST_CLK &&& A_BIST_W_ACCESS, posedge A_BIST_DIN, 1.0 ,1.0, notifier,,,A_BIST_CLK_DELAY, A_BIST_DIN_DELAY); + $setuphold(posedge A_BIST_CLK &&& A_BIST_W_ACCESS, negedge A_BIST_DIN, 1.0 ,1.0, notifier,,,A_BIST_CLK_DELAY, A_BIST_DIN_DELAY); + $setuphold(posedge A_BIST_CLK &&& A_BIST_W_ACCESS, posedge A_BIST_BM, 1.0 ,1.0, notifier,,,A_BIST_CLK_DELAY, A_BIST_BM_DELAY); + $setuphold(posedge A_BIST_CLK &&& A_BIST_W_ACCESS, negedge A_BIST_BM, 1.0 ,1.0, notifier,,,A_BIST_CLK_DELAY, A_BIST_BM_DELAY); + + (posedge B_CLK *> (B_DOUT : B_DIN)) = (1.0, 1.0); + $width(posedge B_CLK, 1.0,0,notifier); + $setuphold(posedge B_CLK &&& B_MEN, posedge B_MEN, 1.0, 1.0,notifier,,,B_CLK_DELAY, B_MEN_DELAY); + $setuphold(posedge B_CLK &&& B_MEN, posedge B_REN, 1.0, 1.0,notifier,,,B_CLK_DELAY, B_REN_DELAY); + $setuphold(posedge B_CLK &&& B_MEN, posedge B_WEN, 1.0, 1.0,notifier,,,B_CLK_DELAY, B_WEN_DELAY); + $setuphold(posedge B_CLK &&& B_MEN, negedge B_MEN, 1.0, 1.0,notifier,,,B_CLK_DELAY, B_MEN_DELAY); + $setuphold(posedge B_CLK &&& B_MEN, negedge B_REN, 1.0, 1.0,notifier,,,B_CLK_DELAY, B_REN_DELAY); + $setuphold(posedge B_CLK &&& B_MEN, negedge B_WEN, 1.0, 1.0,notifier,,,B_CLK_DELAY, B_WEN_DELAY); + $setuphold(posedge B_CLK &&& B_RW_ACCESS, posedge B_ADDR, 1.0 ,1.0, notifier,,,B_CLK_DELAY, B_ADDR_DELAY); + $setuphold(posedge B_CLK &&& B_RW_ACCESS, negedge B_ADDR, 1.0 ,1.0, notifier,,,B_CLK_DELAY, B_ADDR_DELAY); + + $setuphold(posedge B_CLK &&& B_W_ACCESS, posedge B_DIN, 1.0 ,1.0, notifier,,,B_CLK_DELAY, B_DIN_DELAY); + $setuphold(posedge B_CLK &&& B_W_ACCESS, negedge B_DIN, 1.0 ,1.0, notifier,,,B_CLK_DELAY, B_DIN_DELAY); + $setuphold(posedge B_CLK &&& B_W_ACCESS, posedge B_BM, 1.0 ,1.0, notifier,,,B_CLK_DELAY, B_BM_DELAY); + $setuphold(posedge B_CLK &&& B_W_ACCESS, negedge B_BM, 1.0 ,1.0, notifier,,,B_CLK_DELAY, B_BM_DELAY); + (posedge B_BIST_CLK *> (B_DOUT : B_BIST_DIN)) = (1.0, 1.0); + $width(posedge B_BIST_CLK, 1.0,0,notifier); + $setuphold(posedge B_BIST_CLK &&& B_BIST_MEN, posedge B_BIST_MEN, 1.0, 1.0,notifier,,,B_BIST_CLK_DELAY, B_BIST_MEN_DELAY); + $setuphold(posedge B_BIST_CLK &&& B_BIST_MEN, posedge B_BIST_REN, 1.0, 1.0,notifier,,,B_BIST_CLK_DELAY, B_BIST_REN_DELAY); + $setuphold(posedge B_BIST_CLK &&& B_BIST_MEN, posedge B_BIST_WEN, 1.0, 1.0,notifier,,,B_BIST_CLK_DELAY, B_BIST_WEN_DELAY); + $setuphold(posedge B_BIST_CLK &&& B_BIST_MEN, negedge B_BIST_MEN, 1.0, 1.0,notifier,,,B_BIST_CLK_DELAY, B_BIST_MEN_DELAY); + $setuphold(posedge B_BIST_CLK &&& B_BIST_MEN, negedge B_BIST_REN, 1.0, 1.0,notifier,,,B_BIST_CLK_DELAY, B_BIST_REN_DELAY); + $setuphold(posedge B_BIST_CLK &&& B_BIST_MEN, negedge B_BIST_WEN, 1.0, 1.0,notifier,,,B_BIST_CLK_DELAY, B_BIST_WEN_DELAY); + $setuphold(posedge B_BIST_CLK &&& B_BIST_RW_ACCESS, posedge B_BIST_ADDR, 1.0 ,1.0, notifier,,,B_BIST_CLK_DELAY, B_BIST_ADDR_DELAY); + $setuphold(posedge B_BIST_CLK &&& B_BIST_RW_ACCESS, negedge B_BIST_ADDR, 1.0 ,1.0, notifier,,,B_BIST_CLK_DELAY, B_BIST_ADDR_DELAY); + + $setuphold(posedge B_BIST_CLK &&& B_BIST_W_ACCESS, posedge B_BIST_DIN, 1.0 ,1.0, notifier,,,B_BIST_CLK_DELAY, B_BIST_DIN_DELAY); + $setuphold(posedge B_BIST_CLK &&& B_BIST_W_ACCESS, negedge B_BIST_DIN, 1.0 ,1.0, notifier,,,B_BIST_CLK_DELAY, B_BIST_DIN_DELAY); + $setuphold(posedge B_BIST_CLK &&& B_BIST_W_ACCESS, posedge B_BIST_BM, 1.0 ,1.0, notifier,,,B_BIST_CLK_DELAY, B_BIST_BM_DELAY); + $setuphold(posedge B_BIST_CLK &&& B_BIST_W_ACCESS, negedge B_BIST_BM, 1.0 ,1.0, notifier,,,B_BIST_CLK_DELAY, B_BIST_BM_DELAY); + + endspecify + +`endif + +endmodule +`endcelldefine \ No newline at end of file diff --git a/flow/platforms/ihp-sg13g2/verilog/RM_IHPSG13_2P_256x32_c2_bm_bist.v b/flow/platforms/ihp-sg13g2/verilog/RM_IHPSG13_2P_256x32_c2_bm_bist.v new file mode 100644 index 0000000000..97e5efaa57 --- /dev/null +++ b/flow/platforms/ihp-sg13g2/verilog/RM_IHPSG13_2P_256x32_c2_bm_bist.v @@ -0,0 +1,291 @@ +// ------------------------------------------------------ +// +// Copyright 2025 IHP PDK Authors +// +// Licensed under the Apache License, Version 2.0 (the "License"); +// you may not use this file except in compliance with the License. +// You may obtain a copy of the License at +// +// https://www.apache.org/licenses/LICENSE-2.0 +// +// Unless required by applicable law or agreed to in writing, software +// distributed under the License is distributed on an "AS IS" BASIS, +// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +// See the License for the specific language governing permissions and +// limitations under the License. +// +// Generated on Wed Aug 27 13:14:43 2025 +// +// ------------------------------------------------------ +`celldefine +module RM_IHPSG13_2P_256x32_c2_bm_bist ( + A_CLK, + A_MEN, + A_WEN, + A_REN, + A_ADDR, + A_DIN, + A_DLY, + A_DOUT, + A_BM, + A_BIST_CLK, + A_BIST_EN, + A_BIST_MEN, + A_BIST_WEN, + A_BIST_REN, + A_BIST_ADDR, + A_BIST_DIN, + A_BIST_BM, + B_CLK, + B_MEN, + B_WEN, + B_REN, + B_ADDR, + B_DIN, + B_DLY, + B_DOUT, + B_BM, + B_BIST_CLK, + B_BIST_EN, + B_BIST_MEN, + B_BIST_WEN, + B_BIST_REN, + B_BIST_ADDR, + B_BIST_DIN, + B_BIST_BM +); + + input A_CLK; + input A_MEN; + input A_WEN; + input A_REN; + input [7:0] A_ADDR; + input [31:0] A_DIN; + input A_DLY; + output [31:0] A_DOUT; + input [31:0] A_BM; + input A_BIST_CLK; + input A_BIST_EN; + input A_BIST_MEN; + input A_BIST_WEN; + input A_BIST_REN; + input [7:0] A_BIST_ADDR; + input [31:0] A_BIST_DIN; + input [31:0] A_BIST_BM; + input B_CLK; + input B_MEN; + input B_WEN; + input B_REN; + input [7:0] B_ADDR; + input [31:0] B_DIN; + input B_DLY; + output [31:0] B_DOUT; + input [31:0] B_BM; + input B_BIST_CLK; + input B_BIST_EN; + input B_BIST_MEN; + input B_BIST_WEN; + input B_BIST_REN; + input [7:0] B_BIST_ADDR; + input [31:0] B_BIST_DIN; + input [31:0] B_BIST_BM; + + +`ifdef FUNCTIONAL // functional // + + + SRAM_2P_behavioral_bm_bist #( + .P_DATA_WIDTH(32), + .P_ADDR_WIDTH(8) + ) i_SRAM_2P_behavioral_bm_bist ( + .A_CLK(A_CLK), + .A_MEN(A_MEN), + .A_WEN(A_WEN), + .A_REN(A_REN), + .A_ADDR(A_ADDR), + .A_DLY(A_DLY), + .A_DIN(A_DIN), + .A_DOUT(A_DOUT), + .A_BM(A_BM), + .A_BIST_CLK(A_BIST_CLK), + .A_BIST_EN(A_BIST_EN), + .A_BIST_MEN(A_BIST_MEN), + .A_BIST_WEN(A_BIST_WEN), + .A_BIST_REN(A_BIST_REN), + .A_BIST_ADDR(A_BIST_ADDR), + .A_BIST_DIN(A_BIST_DIN), + .A_BIST_BM(A_BIST_BM), + .B_CLK(B_CLK), + .B_MEN(B_MEN), + .B_WEN(B_WEN), + .B_REN(B_REN), + .B_ADDR(B_ADDR), + .B_DLY(B_DLY), + .B_DIN(B_DIN), + .B_DOUT(B_DOUT), + .B_BM(B_BM), + .B_BIST_CLK(B_BIST_CLK), + .B_BIST_EN(B_BIST_EN), + .B_BIST_MEN(B_BIST_MEN), + .B_BIST_WEN(B_BIST_WEN), + .B_BIST_REN(B_BIST_REN), + .B_BIST_ADDR(B_BIST_ADDR), + .B_BIST_DIN(B_BIST_DIN), + .B_BIST_BM(B_BIST_BM) + ); + +`else + + wire A_CLK_DELAY; + wire A_MEN_DELAY; + wire A_WEN_DELAY; + wire A_REN_DELAY; + wire [7:0] A_ADDR_DELAY; + wire [31:0] A_DIN_DELAY; + wire [31:0] A_BM_DELAY; + wire A_BIST_CLK_DELAY; + wire A_BIST_MEN_DELAY; + wire A_BIST_WEN_DELAY; + wire A_BIST_REN_DELAY; + wire [7:0] A_BIST_ADDR_DELAY; + wire [31:0] A_BIST_DIN_DELAY; + wire [31:0] A_BIST_BM_DELAY; + wire B_CLK_DELAY; + wire B_MEN_DELAY; + wire B_WEN_DELAY; + wire B_REN_DELAY; + wire [7:0] B_ADDR_DELAY; + wire [31:0] B_DIN_DELAY; + wire [31:0] B_BM_DELAY; + wire B_BIST_CLK_DELAY; + wire B_BIST_MEN_DELAY; + wire B_BIST_WEN_DELAY; + wire B_BIST_REN_DELAY; + wire [7:0] B_BIST_ADDR_DELAY; + wire [31:0] B_BIST_DIN_DELAY; + wire [31:0] B_BIST_BM_DELAY; + + reg notifier; + + wire A_RW_ACCESS = (A_WEN || A_REN) && A_MEN; + wire A_W_ACCESS = A_WEN && A_MEN; + wire A_BIST_RW_ACCESS = (A_BIST_WEN || A_BIST_REN) && A_BIST_MEN; + wire A_BIST_W_ACCESS = A_BIST_WEN && A_BIST_MEN; + + wire B_RW_ACCESS = (B_WEN || B_REN) && B_MEN; + wire B_W_ACCESS = B_WEN && B_MEN; + wire B_BIST_RW_ACCESS = (B_BIST_WEN || B_BIST_REN) && B_BIST_MEN; + wire B_BIST_W_ACCESS = B_BIST_WEN && B_BIST_MEN; + + + SRAM_2P_behavioral_bm_bist #( + .P_DATA_WIDTH(32), + .P_ADDR_WIDTH(8) + ) i_SRAM_2P_behavioral_bm_bist ( + .A_CLK(A_CLK_DELAY), + .A_MEN(A_MEN_DELAY), + .A_WEN(A_WEN_DELAY), + .A_REN(A_REN_DELAY), + .A_ADDR(A_ADDR_DELAY), + .A_DLY(A_DLY), + .A_DIN(A_DIN_DELAY), + .A_DOUT(A_DOUT), + .A_BM(A_BM_DELAY), + .A_BIST_CLK(A_BIST_CLK_DELAY), + .A_BIST_EN(A_BIST_EN), + .A_BIST_MEN(A_BIST_MEN_DELAY), + .A_BIST_WEN(A_BIST_WEN_DELAY), + .A_BIST_REN(A_BIST_REN_DELAY), + .A_BIST_ADDR(A_BIST_ADDR_DELAY), + .A_BIST_DIN(A_BIST_DIN_DELAY), + .A_BIST_BM(A_BIST_BM_DELAY), + .B_CLK(B_CLK_DELAY), + .B_MEN(B_MEN_DELAY), + .B_WEN(B_WEN_DELAY), + .B_REN(B_REN_DELAY), + .B_ADDR(B_ADDR_DELAY), + .B_DLY(B_DLY), + .B_DIN(B_DIN_DELAY), + .B_DOUT(B_DOUT), + .B_BM(B_BM_DELAY), + .B_BIST_CLK(B_BIST_CLK_DELAY), + .B_BIST_EN(B_BIST_EN), + .B_BIST_MEN(B_BIST_MEN_DELAY), + .B_BIST_WEN(B_BIST_WEN_DELAY), + .B_BIST_REN(B_BIST_REN_DELAY), + .B_BIST_ADDR(B_BIST_ADDR_DELAY), + .B_BIST_DIN(B_BIST_DIN_DELAY), + .B_BIST_BM(B_BIST_BM_DELAY) + ); + + + specify + + (posedge A_CLK *> (A_DOUT : A_DIN)) = (1.0, 1.0); + $width(posedge A_CLK, 1.0,0,notifier); + $setuphold(posedge A_CLK &&& A_MEN, posedge A_MEN, 1.0, 1.0,notifier,,,A_CLK_DELAY, A_MEN_DELAY); + $setuphold(posedge A_CLK &&& A_MEN, posedge A_REN, 1.0, 1.0,notifier,,,A_CLK_DELAY, A_REN_DELAY); + $setuphold(posedge A_CLK &&& A_MEN, posedge A_WEN, 1.0, 1.0,notifier,,,A_CLK_DELAY, A_WEN_DELAY); + $setuphold(posedge A_CLK &&& A_MEN, negedge A_MEN, 1.0, 1.0,notifier,,,A_CLK_DELAY, A_MEN_DELAY); + $setuphold(posedge A_CLK &&& A_MEN, negedge A_REN, 1.0, 1.0,notifier,,,A_CLK_DELAY, A_REN_DELAY); + $setuphold(posedge A_CLK &&& A_MEN, negedge A_WEN, 1.0, 1.0,notifier,,,A_CLK_DELAY, A_WEN_DELAY); + $setuphold(posedge A_CLK &&& A_RW_ACCESS, posedge A_ADDR, 1.0 ,1.0, notifier,,,A_CLK_DELAY, A_ADDR_DELAY); + $setuphold(posedge A_CLK &&& A_RW_ACCESS, negedge A_ADDR, 1.0 ,1.0, notifier,,,A_CLK_DELAY, A_ADDR_DELAY); + + $setuphold(posedge A_CLK &&& A_W_ACCESS, posedge A_DIN, 1.0 ,1.0, notifier,,,A_CLK_DELAY, A_DIN_DELAY); + $setuphold(posedge A_CLK &&& A_W_ACCESS, negedge A_DIN, 1.0 ,1.0, notifier,,,A_CLK_DELAY, A_DIN_DELAY); + $setuphold(posedge A_CLK &&& A_W_ACCESS, posedge A_BM, 1.0 ,1.0, notifier,,,A_CLK_DELAY, A_BM_DELAY); + $setuphold(posedge A_CLK &&& A_W_ACCESS, negedge A_BM, 1.0 ,1.0, notifier,,,A_CLK_DELAY, A_BM_DELAY); + (posedge A_BIST_CLK *> (A_DOUT : A_BIST_DIN)) = (1.0, 1.0); + $width(posedge A_BIST_CLK, 1.0,0,notifier); + $setuphold(posedge A_BIST_CLK &&& A_BIST_MEN, posedge A_BIST_MEN, 1.0, 1.0,notifier,,,A_BIST_CLK_DELAY, A_BIST_MEN_DELAY); + $setuphold(posedge A_BIST_CLK &&& A_BIST_MEN, posedge A_BIST_REN, 1.0, 1.0,notifier,,,A_BIST_CLK_DELAY, A_BIST_REN_DELAY); + $setuphold(posedge A_BIST_CLK &&& A_BIST_MEN, posedge A_BIST_WEN, 1.0, 1.0,notifier,,,A_BIST_CLK_DELAY, A_BIST_WEN_DELAY); + $setuphold(posedge A_BIST_CLK &&& A_BIST_MEN, negedge A_BIST_MEN, 1.0, 1.0,notifier,,,A_BIST_CLK_DELAY, A_BIST_MEN_DELAY); + $setuphold(posedge A_BIST_CLK &&& A_BIST_MEN, negedge A_BIST_REN, 1.0, 1.0,notifier,,,A_BIST_CLK_DELAY, A_BIST_REN_DELAY); + $setuphold(posedge A_BIST_CLK &&& A_BIST_MEN, negedge A_BIST_WEN, 1.0, 1.0,notifier,,,A_BIST_CLK_DELAY, A_BIST_WEN_DELAY); + $setuphold(posedge A_BIST_CLK &&& A_BIST_RW_ACCESS, posedge A_BIST_ADDR, 1.0 ,1.0, notifier,,,A_BIST_CLK_DELAY, A_BIST_ADDR_DELAY); + $setuphold(posedge A_BIST_CLK &&& A_BIST_RW_ACCESS, negedge A_BIST_ADDR, 1.0 ,1.0, notifier,,,A_BIST_CLK_DELAY, A_BIST_ADDR_DELAY); + + $setuphold(posedge A_BIST_CLK &&& A_BIST_W_ACCESS, posedge A_BIST_DIN, 1.0 ,1.0, notifier,,,A_BIST_CLK_DELAY, A_BIST_DIN_DELAY); + $setuphold(posedge A_BIST_CLK &&& A_BIST_W_ACCESS, negedge A_BIST_DIN, 1.0 ,1.0, notifier,,,A_BIST_CLK_DELAY, A_BIST_DIN_DELAY); + $setuphold(posedge A_BIST_CLK &&& A_BIST_W_ACCESS, posedge A_BIST_BM, 1.0 ,1.0, notifier,,,A_BIST_CLK_DELAY, A_BIST_BM_DELAY); + $setuphold(posedge A_BIST_CLK &&& A_BIST_W_ACCESS, negedge A_BIST_BM, 1.0 ,1.0, notifier,,,A_BIST_CLK_DELAY, A_BIST_BM_DELAY); + + (posedge B_CLK *> (B_DOUT : B_DIN)) = (1.0, 1.0); + $width(posedge B_CLK, 1.0,0,notifier); + $setuphold(posedge B_CLK &&& B_MEN, posedge B_MEN, 1.0, 1.0,notifier,,,B_CLK_DELAY, B_MEN_DELAY); + $setuphold(posedge B_CLK &&& B_MEN, posedge B_REN, 1.0, 1.0,notifier,,,B_CLK_DELAY, B_REN_DELAY); + $setuphold(posedge B_CLK &&& B_MEN, posedge B_WEN, 1.0, 1.0,notifier,,,B_CLK_DELAY, B_WEN_DELAY); + $setuphold(posedge B_CLK &&& B_MEN, negedge B_MEN, 1.0, 1.0,notifier,,,B_CLK_DELAY, B_MEN_DELAY); + $setuphold(posedge B_CLK &&& B_MEN, negedge B_REN, 1.0, 1.0,notifier,,,B_CLK_DELAY, B_REN_DELAY); + $setuphold(posedge B_CLK &&& B_MEN, negedge B_WEN, 1.0, 1.0,notifier,,,B_CLK_DELAY, B_WEN_DELAY); + $setuphold(posedge B_CLK &&& B_RW_ACCESS, posedge B_ADDR, 1.0 ,1.0, notifier,,,B_CLK_DELAY, B_ADDR_DELAY); + $setuphold(posedge B_CLK &&& B_RW_ACCESS, negedge B_ADDR, 1.0 ,1.0, notifier,,,B_CLK_DELAY, B_ADDR_DELAY); + + $setuphold(posedge B_CLK &&& B_W_ACCESS, posedge B_DIN, 1.0 ,1.0, notifier,,,B_CLK_DELAY, B_DIN_DELAY); + $setuphold(posedge B_CLK &&& B_W_ACCESS, negedge B_DIN, 1.0 ,1.0, notifier,,,B_CLK_DELAY, B_DIN_DELAY); + $setuphold(posedge B_CLK &&& B_W_ACCESS, posedge B_BM, 1.0 ,1.0, notifier,,,B_CLK_DELAY, B_BM_DELAY); + $setuphold(posedge B_CLK &&& B_W_ACCESS, negedge B_BM, 1.0 ,1.0, notifier,,,B_CLK_DELAY, B_BM_DELAY); + (posedge B_BIST_CLK *> (B_DOUT : B_BIST_DIN)) = (1.0, 1.0); + $width(posedge B_BIST_CLK, 1.0,0,notifier); + $setuphold(posedge B_BIST_CLK &&& B_BIST_MEN, posedge B_BIST_MEN, 1.0, 1.0,notifier,,,B_BIST_CLK_DELAY, B_BIST_MEN_DELAY); + $setuphold(posedge B_BIST_CLK &&& B_BIST_MEN, posedge B_BIST_REN, 1.0, 1.0,notifier,,,B_BIST_CLK_DELAY, B_BIST_REN_DELAY); + $setuphold(posedge B_BIST_CLK &&& B_BIST_MEN, posedge B_BIST_WEN, 1.0, 1.0,notifier,,,B_BIST_CLK_DELAY, B_BIST_WEN_DELAY); + $setuphold(posedge B_BIST_CLK &&& B_BIST_MEN, negedge B_BIST_MEN, 1.0, 1.0,notifier,,,B_BIST_CLK_DELAY, B_BIST_MEN_DELAY); + $setuphold(posedge B_BIST_CLK &&& B_BIST_MEN, negedge B_BIST_REN, 1.0, 1.0,notifier,,,B_BIST_CLK_DELAY, B_BIST_REN_DELAY); + $setuphold(posedge B_BIST_CLK &&& B_BIST_MEN, negedge B_BIST_WEN, 1.0, 1.0,notifier,,,B_BIST_CLK_DELAY, B_BIST_WEN_DELAY); + $setuphold(posedge B_BIST_CLK &&& B_BIST_RW_ACCESS, posedge B_BIST_ADDR, 1.0 ,1.0, notifier,,,B_BIST_CLK_DELAY, B_BIST_ADDR_DELAY); + $setuphold(posedge B_BIST_CLK &&& B_BIST_RW_ACCESS, negedge B_BIST_ADDR, 1.0 ,1.0, notifier,,,B_BIST_CLK_DELAY, B_BIST_ADDR_DELAY); + + $setuphold(posedge B_BIST_CLK &&& B_BIST_W_ACCESS, posedge B_BIST_DIN, 1.0 ,1.0, notifier,,,B_BIST_CLK_DELAY, B_BIST_DIN_DELAY); + $setuphold(posedge B_BIST_CLK &&& B_BIST_W_ACCESS, negedge B_BIST_DIN, 1.0 ,1.0, notifier,,,B_BIST_CLK_DELAY, B_BIST_DIN_DELAY); + $setuphold(posedge B_BIST_CLK &&& B_BIST_W_ACCESS, posedge B_BIST_BM, 1.0 ,1.0, notifier,,,B_BIST_CLK_DELAY, B_BIST_BM_DELAY); + $setuphold(posedge B_BIST_CLK &&& B_BIST_W_ACCESS, negedge B_BIST_BM, 1.0 ,1.0, notifier,,,B_BIST_CLK_DELAY, B_BIST_BM_DELAY); + + endspecify + +`endif + +endmodule +`endcelldefine \ No newline at end of file diff --git a/flow/platforms/ihp-sg13g2/verilog/RM_IHPSG13_2P_256x8_c2_bm_bist.v b/flow/platforms/ihp-sg13g2/verilog/RM_IHPSG13_2P_256x8_c2_bm_bist.v new file mode 100644 index 0000000000..c2842534f2 --- /dev/null +++ b/flow/platforms/ihp-sg13g2/verilog/RM_IHPSG13_2P_256x8_c2_bm_bist.v @@ -0,0 +1,291 @@ +// ------------------------------------------------------ +// +// Copyright 2025 IHP PDK Authors +// +// Licensed under the Apache License, Version 2.0 (the "License"); +// you may not use this file except in compliance with the License. +// You may obtain a copy of the License at +// +// https://www.apache.org/licenses/LICENSE-2.0 +// +// Unless required by applicable law or agreed to in writing, software +// distributed under the License is distributed on an "AS IS" BASIS, +// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +// See the License for the specific language governing permissions and +// limitations under the License. +// +// Generated on Wed Aug 27 13:36:37 2025 +// +// ------------------------------------------------------ +`celldefine +module RM_IHPSG13_2P_256x8_c2_bm_bist ( + A_CLK, + A_MEN, + A_WEN, + A_REN, + A_ADDR, + A_DIN, + A_DLY, + A_DOUT, + A_BM, + A_BIST_CLK, + A_BIST_EN, + A_BIST_MEN, + A_BIST_WEN, + A_BIST_REN, + A_BIST_ADDR, + A_BIST_DIN, + A_BIST_BM, + B_CLK, + B_MEN, + B_WEN, + B_REN, + B_ADDR, + B_DIN, + B_DLY, + B_DOUT, + B_BM, + B_BIST_CLK, + B_BIST_EN, + B_BIST_MEN, + B_BIST_WEN, + B_BIST_REN, + B_BIST_ADDR, + B_BIST_DIN, + B_BIST_BM +); + + input A_CLK; + input A_MEN; + input A_WEN; + input A_REN; + input [7:0] A_ADDR; + input [7:0] A_DIN; + input A_DLY; + output [7:0] A_DOUT; + input [7:0] A_BM; + input A_BIST_CLK; + input A_BIST_EN; + input A_BIST_MEN; + input A_BIST_WEN; + input A_BIST_REN; + input [7:0] A_BIST_ADDR; + input [7:0] A_BIST_DIN; + input [7:0] A_BIST_BM; + input B_CLK; + input B_MEN; + input B_WEN; + input B_REN; + input [7:0] B_ADDR; + input [7:0] B_DIN; + input B_DLY; + output [7:0] B_DOUT; + input [7:0] B_BM; + input B_BIST_CLK; + input B_BIST_EN; + input B_BIST_MEN; + input B_BIST_WEN; + input B_BIST_REN; + input [7:0] B_BIST_ADDR; + input [7:0] B_BIST_DIN; + input [7:0] B_BIST_BM; + + +`ifdef FUNCTIONAL // functional // + + + SRAM_2P_behavioral_bm_bist #( + .P_DATA_WIDTH(8), + .P_ADDR_WIDTH(8) + ) i_SRAM_2P_behavioral_bm_bist ( + .A_CLK(A_CLK), + .A_MEN(A_MEN), + .A_WEN(A_WEN), + .A_REN(A_REN), + .A_ADDR(A_ADDR), + .A_DLY(A_DLY), + .A_DIN(A_DIN), + .A_DOUT(A_DOUT), + .A_BM(A_BM), + .A_BIST_CLK(A_BIST_CLK), + .A_BIST_EN(A_BIST_EN), + .A_BIST_MEN(A_BIST_MEN), + .A_BIST_WEN(A_BIST_WEN), + .A_BIST_REN(A_BIST_REN), + .A_BIST_ADDR(A_BIST_ADDR), + .A_BIST_DIN(A_BIST_DIN), + .A_BIST_BM(A_BIST_BM), + .B_CLK(B_CLK), + .B_MEN(B_MEN), + .B_WEN(B_WEN), + .B_REN(B_REN), + .B_ADDR(B_ADDR), + .B_DLY(B_DLY), + .B_DIN(B_DIN), + .B_DOUT(B_DOUT), + .B_BM(B_BM), + .B_BIST_CLK(B_BIST_CLK), + .B_BIST_EN(B_BIST_EN), + .B_BIST_MEN(B_BIST_MEN), + .B_BIST_WEN(B_BIST_WEN), + .B_BIST_REN(B_BIST_REN), + .B_BIST_ADDR(B_BIST_ADDR), + .B_BIST_DIN(B_BIST_DIN), + .B_BIST_BM(B_BIST_BM) + ); + +`else + + wire A_CLK_DELAY; + wire A_MEN_DELAY; + wire A_WEN_DELAY; + wire A_REN_DELAY; + wire [7:0] A_ADDR_DELAY; + wire [7:0] A_DIN_DELAY; + wire [7:0] A_BM_DELAY; + wire A_BIST_CLK_DELAY; + wire A_BIST_MEN_DELAY; + wire A_BIST_WEN_DELAY; + wire A_BIST_REN_DELAY; + wire [7:0] A_BIST_ADDR_DELAY; + wire [7:0] A_BIST_DIN_DELAY; + wire [7:0] A_BIST_BM_DELAY; + wire B_CLK_DELAY; + wire B_MEN_DELAY; + wire B_WEN_DELAY; + wire B_REN_DELAY; + wire [7:0] B_ADDR_DELAY; + wire [7:0] B_DIN_DELAY; + wire [7:0] B_BM_DELAY; + wire B_BIST_CLK_DELAY; + wire B_BIST_MEN_DELAY; + wire B_BIST_WEN_DELAY; + wire B_BIST_REN_DELAY; + wire [7:0] B_BIST_ADDR_DELAY; + wire [7:0] B_BIST_DIN_DELAY; + wire [7:0] B_BIST_BM_DELAY; + + reg notifier; + + wire A_RW_ACCESS = (A_WEN || A_REN) && A_MEN; + wire A_W_ACCESS = A_WEN && A_MEN; + wire A_BIST_RW_ACCESS = (A_BIST_WEN || A_BIST_REN) && A_BIST_MEN; + wire A_BIST_W_ACCESS = A_BIST_WEN && A_BIST_MEN; + + wire B_RW_ACCESS = (B_WEN || B_REN) && B_MEN; + wire B_W_ACCESS = B_WEN && B_MEN; + wire B_BIST_RW_ACCESS = (B_BIST_WEN || B_BIST_REN) && B_BIST_MEN; + wire B_BIST_W_ACCESS = B_BIST_WEN && B_BIST_MEN; + + + SRAM_2P_behavioral_bm_bist #( + .P_DATA_WIDTH(8), + .P_ADDR_WIDTH(8) + ) i_SRAM_2P_behavioral_bm_bist ( + .A_CLK(A_CLK_DELAY), + .A_MEN(A_MEN_DELAY), + .A_WEN(A_WEN_DELAY), + .A_REN(A_REN_DELAY), + .A_ADDR(A_ADDR_DELAY), + .A_DLY(A_DLY), + .A_DIN(A_DIN_DELAY), + .A_DOUT(A_DOUT), + .A_BM(A_BM_DELAY), + .A_BIST_CLK(A_BIST_CLK_DELAY), + .A_BIST_EN(A_BIST_EN), + .A_BIST_MEN(A_BIST_MEN_DELAY), + .A_BIST_WEN(A_BIST_WEN_DELAY), + .A_BIST_REN(A_BIST_REN_DELAY), + .A_BIST_ADDR(A_BIST_ADDR_DELAY), + .A_BIST_DIN(A_BIST_DIN_DELAY), + .A_BIST_BM(A_BIST_BM_DELAY), + .B_CLK(B_CLK_DELAY), + .B_MEN(B_MEN_DELAY), + .B_WEN(B_WEN_DELAY), + .B_REN(B_REN_DELAY), + .B_ADDR(B_ADDR_DELAY), + .B_DLY(B_DLY), + .B_DIN(B_DIN_DELAY), + .B_DOUT(B_DOUT), + .B_BM(B_BM_DELAY), + .B_BIST_CLK(B_BIST_CLK_DELAY), + .B_BIST_EN(B_BIST_EN), + .B_BIST_MEN(B_BIST_MEN_DELAY), + .B_BIST_WEN(B_BIST_WEN_DELAY), + .B_BIST_REN(B_BIST_REN_DELAY), + .B_BIST_ADDR(B_BIST_ADDR_DELAY), + .B_BIST_DIN(B_BIST_DIN_DELAY), + .B_BIST_BM(B_BIST_BM_DELAY) + ); + + + specify + + (posedge A_CLK *> (A_DOUT : A_DIN)) = (1.0, 1.0); + $width(posedge A_CLK, 1.0,0,notifier); + $setuphold(posedge A_CLK &&& A_MEN, posedge A_MEN, 1.0, 1.0,notifier,,,A_CLK_DELAY, A_MEN_DELAY); + $setuphold(posedge A_CLK &&& A_MEN, posedge A_REN, 1.0, 1.0,notifier,,,A_CLK_DELAY, A_REN_DELAY); + $setuphold(posedge A_CLK &&& A_MEN, posedge A_WEN, 1.0, 1.0,notifier,,,A_CLK_DELAY, A_WEN_DELAY); + $setuphold(posedge A_CLK &&& A_MEN, negedge A_MEN, 1.0, 1.0,notifier,,,A_CLK_DELAY, A_MEN_DELAY); + $setuphold(posedge A_CLK &&& A_MEN, negedge A_REN, 1.0, 1.0,notifier,,,A_CLK_DELAY, A_REN_DELAY); + $setuphold(posedge A_CLK &&& A_MEN, negedge A_WEN, 1.0, 1.0,notifier,,,A_CLK_DELAY, A_WEN_DELAY); + $setuphold(posedge A_CLK &&& A_RW_ACCESS, posedge A_ADDR, 1.0 ,1.0, notifier,,,A_CLK_DELAY, A_ADDR_DELAY); + $setuphold(posedge A_CLK &&& A_RW_ACCESS, negedge A_ADDR, 1.0 ,1.0, notifier,,,A_CLK_DELAY, A_ADDR_DELAY); + + $setuphold(posedge A_CLK &&& A_W_ACCESS, posedge A_DIN, 1.0 ,1.0, notifier,,,A_CLK_DELAY, A_DIN_DELAY); + $setuphold(posedge A_CLK &&& A_W_ACCESS, negedge A_DIN, 1.0 ,1.0, notifier,,,A_CLK_DELAY, A_DIN_DELAY); + $setuphold(posedge A_CLK &&& A_W_ACCESS, posedge A_BM, 1.0 ,1.0, notifier,,,A_CLK_DELAY, A_BM_DELAY); + $setuphold(posedge A_CLK &&& A_W_ACCESS, negedge A_BM, 1.0 ,1.0, notifier,,,A_CLK_DELAY, A_BM_DELAY); + (posedge A_BIST_CLK *> (A_DOUT : A_BIST_DIN)) = (1.0, 1.0); + $width(posedge A_BIST_CLK, 1.0,0,notifier); + $setuphold(posedge A_BIST_CLK &&& A_BIST_MEN, posedge A_BIST_MEN, 1.0, 1.0,notifier,,,A_BIST_CLK_DELAY, A_BIST_MEN_DELAY); + $setuphold(posedge A_BIST_CLK &&& A_BIST_MEN, posedge A_BIST_REN, 1.0, 1.0,notifier,,,A_BIST_CLK_DELAY, A_BIST_REN_DELAY); + $setuphold(posedge A_BIST_CLK &&& A_BIST_MEN, posedge A_BIST_WEN, 1.0, 1.0,notifier,,,A_BIST_CLK_DELAY, A_BIST_WEN_DELAY); + $setuphold(posedge A_BIST_CLK &&& A_BIST_MEN, negedge A_BIST_MEN, 1.0, 1.0,notifier,,,A_BIST_CLK_DELAY, A_BIST_MEN_DELAY); + $setuphold(posedge A_BIST_CLK &&& A_BIST_MEN, negedge A_BIST_REN, 1.0, 1.0,notifier,,,A_BIST_CLK_DELAY, A_BIST_REN_DELAY); + $setuphold(posedge A_BIST_CLK &&& A_BIST_MEN, negedge A_BIST_WEN, 1.0, 1.0,notifier,,,A_BIST_CLK_DELAY, A_BIST_WEN_DELAY); + $setuphold(posedge A_BIST_CLK &&& A_BIST_RW_ACCESS, posedge A_BIST_ADDR, 1.0 ,1.0, notifier,,,A_BIST_CLK_DELAY, A_BIST_ADDR_DELAY); + $setuphold(posedge A_BIST_CLK &&& A_BIST_RW_ACCESS, negedge A_BIST_ADDR, 1.0 ,1.0, notifier,,,A_BIST_CLK_DELAY, A_BIST_ADDR_DELAY); + + $setuphold(posedge A_BIST_CLK &&& A_BIST_W_ACCESS, posedge A_BIST_DIN, 1.0 ,1.0, notifier,,,A_BIST_CLK_DELAY, A_BIST_DIN_DELAY); + $setuphold(posedge A_BIST_CLK &&& A_BIST_W_ACCESS, negedge A_BIST_DIN, 1.0 ,1.0, notifier,,,A_BIST_CLK_DELAY, A_BIST_DIN_DELAY); + $setuphold(posedge A_BIST_CLK &&& A_BIST_W_ACCESS, posedge A_BIST_BM, 1.0 ,1.0, notifier,,,A_BIST_CLK_DELAY, A_BIST_BM_DELAY); + $setuphold(posedge A_BIST_CLK &&& A_BIST_W_ACCESS, negedge A_BIST_BM, 1.0 ,1.0, notifier,,,A_BIST_CLK_DELAY, A_BIST_BM_DELAY); + + (posedge B_CLK *> (B_DOUT : B_DIN)) = (1.0, 1.0); + $width(posedge B_CLK, 1.0,0,notifier); + $setuphold(posedge B_CLK &&& B_MEN, posedge B_MEN, 1.0, 1.0,notifier,,,B_CLK_DELAY, B_MEN_DELAY); + $setuphold(posedge B_CLK &&& B_MEN, posedge B_REN, 1.0, 1.0,notifier,,,B_CLK_DELAY, B_REN_DELAY); + $setuphold(posedge B_CLK &&& B_MEN, posedge B_WEN, 1.0, 1.0,notifier,,,B_CLK_DELAY, B_WEN_DELAY); + $setuphold(posedge B_CLK &&& B_MEN, negedge B_MEN, 1.0, 1.0,notifier,,,B_CLK_DELAY, B_MEN_DELAY); + $setuphold(posedge B_CLK &&& B_MEN, negedge B_REN, 1.0, 1.0,notifier,,,B_CLK_DELAY, B_REN_DELAY); + $setuphold(posedge B_CLK &&& B_MEN, negedge B_WEN, 1.0, 1.0,notifier,,,B_CLK_DELAY, B_WEN_DELAY); + $setuphold(posedge B_CLK &&& B_RW_ACCESS, posedge B_ADDR, 1.0 ,1.0, notifier,,,B_CLK_DELAY, B_ADDR_DELAY); + $setuphold(posedge B_CLK &&& B_RW_ACCESS, negedge B_ADDR, 1.0 ,1.0, notifier,,,B_CLK_DELAY, B_ADDR_DELAY); + + $setuphold(posedge B_CLK &&& B_W_ACCESS, posedge B_DIN, 1.0 ,1.0, notifier,,,B_CLK_DELAY, B_DIN_DELAY); + $setuphold(posedge B_CLK &&& B_W_ACCESS, negedge B_DIN, 1.0 ,1.0, notifier,,,B_CLK_DELAY, B_DIN_DELAY); + $setuphold(posedge B_CLK &&& B_W_ACCESS, posedge B_BM, 1.0 ,1.0, notifier,,,B_CLK_DELAY, B_BM_DELAY); + $setuphold(posedge B_CLK &&& B_W_ACCESS, negedge B_BM, 1.0 ,1.0, notifier,,,B_CLK_DELAY, B_BM_DELAY); + (posedge B_BIST_CLK *> (B_DOUT : B_BIST_DIN)) = (1.0, 1.0); + $width(posedge B_BIST_CLK, 1.0,0,notifier); + $setuphold(posedge B_BIST_CLK &&& B_BIST_MEN, posedge B_BIST_MEN, 1.0, 1.0,notifier,,,B_BIST_CLK_DELAY, B_BIST_MEN_DELAY); + $setuphold(posedge B_BIST_CLK &&& B_BIST_MEN, posedge B_BIST_REN, 1.0, 1.0,notifier,,,B_BIST_CLK_DELAY, B_BIST_REN_DELAY); + $setuphold(posedge B_BIST_CLK &&& B_BIST_MEN, posedge B_BIST_WEN, 1.0, 1.0,notifier,,,B_BIST_CLK_DELAY, B_BIST_WEN_DELAY); + $setuphold(posedge B_BIST_CLK &&& B_BIST_MEN, negedge B_BIST_MEN, 1.0, 1.0,notifier,,,B_BIST_CLK_DELAY, B_BIST_MEN_DELAY); + $setuphold(posedge B_BIST_CLK &&& B_BIST_MEN, negedge B_BIST_REN, 1.0, 1.0,notifier,,,B_BIST_CLK_DELAY, B_BIST_REN_DELAY); + $setuphold(posedge B_BIST_CLK &&& B_BIST_MEN, negedge B_BIST_WEN, 1.0, 1.0,notifier,,,B_BIST_CLK_DELAY, B_BIST_WEN_DELAY); + $setuphold(posedge B_BIST_CLK &&& B_BIST_RW_ACCESS, posedge B_BIST_ADDR, 1.0 ,1.0, notifier,,,B_BIST_CLK_DELAY, B_BIST_ADDR_DELAY); + $setuphold(posedge B_BIST_CLK &&& B_BIST_RW_ACCESS, negedge B_BIST_ADDR, 1.0 ,1.0, notifier,,,B_BIST_CLK_DELAY, B_BIST_ADDR_DELAY); + + $setuphold(posedge B_BIST_CLK &&& B_BIST_W_ACCESS, posedge B_BIST_DIN, 1.0 ,1.0, notifier,,,B_BIST_CLK_DELAY, B_BIST_DIN_DELAY); + $setuphold(posedge B_BIST_CLK &&& B_BIST_W_ACCESS, negedge B_BIST_DIN, 1.0 ,1.0, notifier,,,B_BIST_CLK_DELAY, B_BIST_DIN_DELAY); + $setuphold(posedge B_BIST_CLK &&& B_BIST_W_ACCESS, posedge B_BIST_BM, 1.0 ,1.0, notifier,,,B_BIST_CLK_DELAY, B_BIST_BM_DELAY); + $setuphold(posedge B_BIST_CLK &&& B_BIST_W_ACCESS, negedge B_BIST_BM, 1.0 ,1.0, notifier,,,B_BIST_CLK_DELAY, B_BIST_BM_DELAY); + + endspecify + +`endif + +endmodule +`endcelldefine \ No newline at end of file diff --git a/flow/platforms/ihp-sg13g2/verilog/RM_IHPSG13_2P_512x16_c2_bm_bist.v b/flow/platforms/ihp-sg13g2/verilog/RM_IHPSG13_2P_512x16_c2_bm_bist.v new file mode 100644 index 0000000000..e8829ee1e1 --- /dev/null +++ b/flow/platforms/ihp-sg13g2/verilog/RM_IHPSG13_2P_512x16_c2_bm_bist.v @@ -0,0 +1,291 @@ +// ------------------------------------------------------ +// +// Copyright 2025 IHP PDK Authors +// +// Licensed under the Apache License, Version 2.0 (the "License"); +// you may not use this file except in compliance with the License. +// You may obtain a copy of the License at +// +// https://www.apache.org/licenses/LICENSE-2.0 +// +// Unless required by applicable law or agreed to in writing, software +// distributed under the License is distributed on an "AS IS" BASIS, +// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +// See the License for the specific language governing permissions and +// limitations under the License. +// +// Generated on Wed Aug 27 13:18:16 2025 +// +// ------------------------------------------------------ +`celldefine +module RM_IHPSG13_2P_512x16_c2_bm_bist ( + A_CLK, + A_MEN, + A_WEN, + A_REN, + A_ADDR, + A_DIN, + A_DLY, + A_DOUT, + A_BM, + A_BIST_CLK, + A_BIST_EN, + A_BIST_MEN, + A_BIST_WEN, + A_BIST_REN, + A_BIST_ADDR, + A_BIST_DIN, + A_BIST_BM, + B_CLK, + B_MEN, + B_WEN, + B_REN, + B_ADDR, + B_DIN, + B_DLY, + B_DOUT, + B_BM, + B_BIST_CLK, + B_BIST_EN, + B_BIST_MEN, + B_BIST_WEN, + B_BIST_REN, + B_BIST_ADDR, + B_BIST_DIN, + B_BIST_BM +); + + input A_CLK; + input A_MEN; + input A_WEN; + input A_REN; + input [8:0] A_ADDR; + input [15:0] A_DIN; + input A_DLY; + output [15:0] A_DOUT; + input [15:0] A_BM; + input A_BIST_CLK; + input A_BIST_EN; + input A_BIST_MEN; + input A_BIST_WEN; + input A_BIST_REN; + input [8:0] A_BIST_ADDR; + input [15:0] A_BIST_DIN; + input [15:0] A_BIST_BM; + input B_CLK; + input B_MEN; + input B_WEN; + input B_REN; + input [8:0] B_ADDR; + input [15:0] B_DIN; + input B_DLY; + output [15:0] B_DOUT; + input [15:0] B_BM; + input B_BIST_CLK; + input B_BIST_EN; + input B_BIST_MEN; + input B_BIST_WEN; + input B_BIST_REN; + input [8:0] B_BIST_ADDR; + input [15:0] B_BIST_DIN; + input [15:0] B_BIST_BM; + + +`ifdef FUNCTIONAL // functional // + + + SRAM_2P_behavioral_bm_bist #( + .P_DATA_WIDTH(16), + .P_ADDR_WIDTH(9) + ) i_SRAM_2P_behavioral_bm_bist ( + .A_CLK(A_CLK), + .A_MEN(A_MEN), + .A_WEN(A_WEN), + .A_REN(A_REN), + .A_ADDR(A_ADDR), + .A_DLY(A_DLY), + .A_DIN(A_DIN), + .A_DOUT(A_DOUT), + .A_BM(A_BM), + .A_BIST_CLK(A_BIST_CLK), + .A_BIST_EN(A_BIST_EN), + .A_BIST_MEN(A_BIST_MEN), + .A_BIST_WEN(A_BIST_WEN), + .A_BIST_REN(A_BIST_REN), + .A_BIST_ADDR(A_BIST_ADDR), + .A_BIST_DIN(A_BIST_DIN), + .A_BIST_BM(A_BIST_BM), + .B_CLK(B_CLK), + .B_MEN(B_MEN), + .B_WEN(B_WEN), + .B_REN(B_REN), + .B_ADDR(B_ADDR), + .B_DLY(B_DLY), + .B_DIN(B_DIN), + .B_DOUT(B_DOUT), + .B_BM(B_BM), + .B_BIST_CLK(B_BIST_CLK), + .B_BIST_EN(B_BIST_EN), + .B_BIST_MEN(B_BIST_MEN), + .B_BIST_WEN(B_BIST_WEN), + .B_BIST_REN(B_BIST_REN), + .B_BIST_ADDR(B_BIST_ADDR), + .B_BIST_DIN(B_BIST_DIN), + .B_BIST_BM(B_BIST_BM) + ); + +`else + + wire A_CLK_DELAY; + wire A_MEN_DELAY; + wire A_WEN_DELAY; + wire A_REN_DELAY; + wire [8:0] A_ADDR_DELAY; + wire [15:0] A_DIN_DELAY; + wire [15:0] A_BM_DELAY; + wire A_BIST_CLK_DELAY; + wire A_BIST_MEN_DELAY; + wire A_BIST_WEN_DELAY; + wire A_BIST_REN_DELAY; + wire [8:0] A_BIST_ADDR_DELAY; + wire [15:0] A_BIST_DIN_DELAY; + wire [15:0] A_BIST_BM_DELAY; + wire B_CLK_DELAY; + wire B_MEN_DELAY; + wire B_WEN_DELAY; + wire B_REN_DELAY; + wire [8:0] B_ADDR_DELAY; + wire [15:0] B_DIN_DELAY; + wire [15:0] B_BM_DELAY; + wire B_BIST_CLK_DELAY; + wire B_BIST_MEN_DELAY; + wire B_BIST_WEN_DELAY; + wire B_BIST_REN_DELAY; + wire [8:0] B_BIST_ADDR_DELAY; + wire [15:0] B_BIST_DIN_DELAY; + wire [15:0] B_BIST_BM_DELAY; + + reg notifier; + + wire A_RW_ACCESS = (A_WEN || A_REN) && A_MEN; + wire A_W_ACCESS = A_WEN && A_MEN; + wire A_BIST_RW_ACCESS = (A_BIST_WEN || A_BIST_REN) && A_BIST_MEN; + wire A_BIST_W_ACCESS = A_BIST_WEN && A_BIST_MEN; + + wire B_RW_ACCESS = (B_WEN || B_REN) && B_MEN; + wire B_W_ACCESS = B_WEN && B_MEN; + wire B_BIST_RW_ACCESS = (B_BIST_WEN || B_BIST_REN) && B_BIST_MEN; + wire B_BIST_W_ACCESS = B_BIST_WEN && B_BIST_MEN; + + + SRAM_2P_behavioral_bm_bist #( + .P_DATA_WIDTH(16), + .P_ADDR_WIDTH(9) + ) i_SRAM_2P_behavioral_bm_bist ( + .A_CLK(A_CLK_DELAY), + .A_MEN(A_MEN_DELAY), + .A_WEN(A_WEN_DELAY), + .A_REN(A_REN_DELAY), + .A_ADDR(A_ADDR_DELAY), + .A_DLY(A_DLY), + .A_DIN(A_DIN_DELAY), + .A_DOUT(A_DOUT), + .A_BM(A_BM_DELAY), + .A_BIST_CLK(A_BIST_CLK_DELAY), + .A_BIST_EN(A_BIST_EN), + .A_BIST_MEN(A_BIST_MEN_DELAY), + .A_BIST_WEN(A_BIST_WEN_DELAY), + .A_BIST_REN(A_BIST_REN_DELAY), + .A_BIST_ADDR(A_BIST_ADDR_DELAY), + .A_BIST_DIN(A_BIST_DIN_DELAY), + .A_BIST_BM(A_BIST_BM_DELAY), + .B_CLK(B_CLK_DELAY), + .B_MEN(B_MEN_DELAY), + .B_WEN(B_WEN_DELAY), + .B_REN(B_REN_DELAY), + .B_ADDR(B_ADDR_DELAY), + .B_DLY(B_DLY), + .B_DIN(B_DIN_DELAY), + .B_DOUT(B_DOUT), + .B_BM(B_BM_DELAY), + .B_BIST_CLK(B_BIST_CLK_DELAY), + .B_BIST_EN(B_BIST_EN), + .B_BIST_MEN(B_BIST_MEN_DELAY), + .B_BIST_WEN(B_BIST_WEN_DELAY), + .B_BIST_REN(B_BIST_REN_DELAY), + .B_BIST_ADDR(B_BIST_ADDR_DELAY), + .B_BIST_DIN(B_BIST_DIN_DELAY), + .B_BIST_BM(B_BIST_BM_DELAY) + ); + + + specify + + (posedge A_CLK *> (A_DOUT : A_DIN)) = (1.0, 1.0); + $width(posedge A_CLK, 1.0,0,notifier); + $setuphold(posedge A_CLK &&& A_MEN, posedge A_MEN, 1.0, 1.0,notifier,,,A_CLK_DELAY, A_MEN_DELAY); + $setuphold(posedge A_CLK &&& A_MEN, posedge A_REN, 1.0, 1.0,notifier,,,A_CLK_DELAY, A_REN_DELAY); + $setuphold(posedge A_CLK &&& A_MEN, posedge A_WEN, 1.0, 1.0,notifier,,,A_CLK_DELAY, A_WEN_DELAY); + $setuphold(posedge A_CLK &&& A_MEN, negedge A_MEN, 1.0, 1.0,notifier,,,A_CLK_DELAY, A_MEN_DELAY); + $setuphold(posedge A_CLK &&& A_MEN, negedge A_REN, 1.0, 1.0,notifier,,,A_CLK_DELAY, A_REN_DELAY); + $setuphold(posedge A_CLK &&& A_MEN, negedge A_WEN, 1.0, 1.0,notifier,,,A_CLK_DELAY, A_WEN_DELAY); + $setuphold(posedge A_CLK &&& A_RW_ACCESS, posedge A_ADDR, 1.0 ,1.0, notifier,,,A_CLK_DELAY, A_ADDR_DELAY); + $setuphold(posedge A_CLK &&& A_RW_ACCESS, negedge A_ADDR, 1.0 ,1.0, notifier,,,A_CLK_DELAY, A_ADDR_DELAY); + + $setuphold(posedge A_CLK &&& A_W_ACCESS, posedge A_DIN, 1.0 ,1.0, notifier,,,A_CLK_DELAY, A_DIN_DELAY); + $setuphold(posedge A_CLK &&& A_W_ACCESS, negedge A_DIN, 1.0 ,1.0, notifier,,,A_CLK_DELAY, A_DIN_DELAY); + $setuphold(posedge A_CLK &&& A_W_ACCESS, posedge A_BM, 1.0 ,1.0, notifier,,,A_CLK_DELAY, A_BM_DELAY); + $setuphold(posedge A_CLK &&& A_W_ACCESS, negedge A_BM, 1.0 ,1.0, notifier,,,A_CLK_DELAY, A_BM_DELAY); + (posedge A_BIST_CLK *> (A_DOUT : A_BIST_DIN)) = (1.0, 1.0); + $width(posedge A_BIST_CLK, 1.0,0,notifier); + $setuphold(posedge A_BIST_CLK &&& A_BIST_MEN, posedge A_BIST_MEN, 1.0, 1.0,notifier,,,A_BIST_CLK_DELAY, A_BIST_MEN_DELAY); + $setuphold(posedge A_BIST_CLK &&& A_BIST_MEN, posedge A_BIST_REN, 1.0, 1.0,notifier,,,A_BIST_CLK_DELAY, A_BIST_REN_DELAY); + $setuphold(posedge A_BIST_CLK &&& A_BIST_MEN, posedge A_BIST_WEN, 1.0, 1.0,notifier,,,A_BIST_CLK_DELAY, A_BIST_WEN_DELAY); + $setuphold(posedge A_BIST_CLK &&& A_BIST_MEN, negedge A_BIST_MEN, 1.0, 1.0,notifier,,,A_BIST_CLK_DELAY, A_BIST_MEN_DELAY); + $setuphold(posedge A_BIST_CLK &&& A_BIST_MEN, negedge A_BIST_REN, 1.0, 1.0,notifier,,,A_BIST_CLK_DELAY, A_BIST_REN_DELAY); + $setuphold(posedge A_BIST_CLK &&& A_BIST_MEN, negedge A_BIST_WEN, 1.0, 1.0,notifier,,,A_BIST_CLK_DELAY, A_BIST_WEN_DELAY); + $setuphold(posedge A_BIST_CLK &&& A_BIST_RW_ACCESS, posedge A_BIST_ADDR, 1.0 ,1.0, notifier,,,A_BIST_CLK_DELAY, A_BIST_ADDR_DELAY); + $setuphold(posedge A_BIST_CLK &&& A_BIST_RW_ACCESS, negedge A_BIST_ADDR, 1.0 ,1.0, notifier,,,A_BIST_CLK_DELAY, A_BIST_ADDR_DELAY); + + $setuphold(posedge A_BIST_CLK &&& A_BIST_W_ACCESS, posedge A_BIST_DIN, 1.0 ,1.0, notifier,,,A_BIST_CLK_DELAY, A_BIST_DIN_DELAY); + $setuphold(posedge A_BIST_CLK &&& A_BIST_W_ACCESS, negedge A_BIST_DIN, 1.0 ,1.0, notifier,,,A_BIST_CLK_DELAY, A_BIST_DIN_DELAY); + $setuphold(posedge A_BIST_CLK &&& A_BIST_W_ACCESS, posedge A_BIST_BM, 1.0 ,1.0, notifier,,,A_BIST_CLK_DELAY, A_BIST_BM_DELAY); + $setuphold(posedge A_BIST_CLK &&& A_BIST_W_ACCESS, negedge A_BIST_BM, 1.0 ,1.0, notifier,,,A_BIST_CLK_DELAY, A_BIST_BM_DELAY); + + (posedge B_CLK *> (B_DOUT : B_DIN)) = (1.0, 1.0); + $width(posedge B_CLK, 1.0,0,notifier); + $setuphold(posedge B_CLK &&& B_MEN, posedge B_MEN, 1.0, 1.0,notifier,,,B_CLK_DELAY, B_MEN_DELAY); + $setuphold(posedge B_CLK &&& B_MEN, posedge B_REN, 1.0, 1.0,notifier,,,B_CLK_DELAY, B_REN_DELAY); + $setuphold(posedge B_CLK &&& B_MEN, posedge B_WEN, 1.0, 1.0,notifier,,,B_CLK_DELAY, B_WEN_DELAY); + $setuphold(posedge B_CLK &&& B_MEN, negedge B_MEN, 1.0, 1.0,notifier,,,B_CLK_DELAY, B_MEN_DELAY); + $setuphold(posedge B_CLK &&& B_MEN, negedge B_REN, 1.0, 1.0,notifier,,,B_CLK_DELAY, B_REN_DELAY); + $setuphold(posedge B_CLK &&& B_MEN, negedge B_WEN, 1.0, 1.0,notifier,,,B_CLK_DELAY, B_WEN_DELAY); + $setuphold(posedge B_CLK &&& B_RW_ACCESS, posedge B_ADDR, 1.0 ,1.0, notifier,,,B_CLK_DELAY, B_ADDR_DELAY); + $setuphold(posedge B_CLK &&& B_RW_ACCESS, negedge B_ADDR, 1.0 ,1.0, notifier,,,B_CLK_DELAY, B_ADDR_DELAY); + + $setuphold(posedge B_CLK &&& B_W_ACCESS, posedge B_DIN, 1.0 ,1.0, notifier,,,B_CLK_DELAY, B_DIN_DELAY); + $setuphold(posedge B_CLK &&& B_W_ACCESS, negedge B_DIN, 1.0 ,1.0, notifier,,,B_CLK_DELAY, B_DIN_DELAY); + $setuphold(posedge B_CLK &&& B_W_ACCESS, posedge B_BM, 1.0 ,1.0, notifier,,,B_CLK_DELAY, B_BM_DELAY); + $setuphold(posedge B_CLK &&& B_W_ACCESS, negedge B_BM, 1.0 ,1.0, notifier,,,B_CLK_DELAY, B_BM_DELAY); + (posedge B_BIST_CLK *> (B_DOUT : B_BIST_DIN)) = (1.0, 1.0); + $width(posedge B_BIST_CLK, 1.0,0,notifier); + $setuphold(posedge B_BIST_CLK &&& B_BIST_MEN, posedge B_BIST_MEN, 1.0, 1.0,notifier,,,B_BIST_CLK_DELAY, B_BIST_MEN_DELAY); + $setuphold(posedge B_BIST_CLK &&& B_BIST_MEN, posedge B_BIST_REN, 1.0, 1.0,notifier,,,B_BIST_CLK_DELAY, B_BIST_REN_DELAY); + $setuphold(posedge B_BIST_CLK &&& B_BIST_MEN, posedge B_BIST_WEN, 1.0, 1.0,notifier,,,B_BIST_CLK_DELAY, B_BIST_WEN_DELAY); + $setuphold(posedge B_BIST_CLK &&& B_BIST_MEN, negedge B_BIST_MEN, 1.0, 1.0,notifier,,,B_BIST_CLK_DELAY, B_BIST_MEN_DELAY); + $setuphold(posedge B_BIST_CLK &&& B_BIST_MEN, negedge B_BIST_REN, 1.0, 1.0,notifier,,,B_BIST_CLK_DELAY, B_BIST_REN_DELAY); + $setuphold(posedge B_BIST_CLK &&& B_BIST_MEN, negedge B_BIST_WEN, 1.0, 1.0,notifier,,,B_BIST_CLK_DELAY, B_BIST_WEN_DELAY); + $setuphold(posedge B_BIST_CLK &&& B_BIST_RW_ACCESS, posedge B_BIST_ADDR, 1.0 ,1.0, notifier,,,B_BIST_CLK_DELAY, B_BIST_ADDR_DELAY); + $setuphold(posedge B_BIST_CLK &&& B_BIST_RW_ACCESS, negedge B_BIST_ADDR, 1.0 ,1.0, notifier,,,B_BIST_CLK_DELAY, B_BIST_ADDR_DELAY); + + $setuphold(posedge B_BIST_CLK &&& B_BIST_W_ACCESS, posedge B_BIST_DIN, 1.0 ,1.0, notifier,,,B_BIST_CLK_DELAY, B_BIST_DIN_DELAY); + $setuphold(posedge B_BIST_CLK &&& B_BIST_W_ACCESS, negedge B_BIST_DIN, 1.0 ,1.0, notifier,,,B_BIST_CLK_DELAY, B_BIST_DIN_DELAY); + $setuphold(posedge B_BIST_CLK &&& B_BIST_W_ACCESS, posedge B_BIST_BM, 1.0 ,1.0, notifier,,,B_BIST_CLK_DELAY, B_BIST_BM_DELAY); + $setuphold(posedge B_BIST_CLK &&& B_BIST_W_ACCESS, negedge B_BIST_BM, 1.0 ,1.0, notifier,,,B_BIST_CLK_DELAY, B_BIST_BM_DELAY); + + endspecify + +`endif + +endmodule +`endcelldefine \ No newline at end of file diff --git a/flow/platforms/ihp-sg13g2/verilog/RM_IHPSG13_2P_512x32_c2_bm_bist.v b/flow/platforms/ihp-sg13g2/verilog/RM_IHPSG13_2P_512x32_c2_bm_bist.v new file mode 100644 index 0000000000..5cfe8e77a0 --- /dev/null +++ b/flow/platforms/ihp-sg13g2/verilog/RM_IHPSG13_2P_512x32_c2_bm_bist.v @@ -0,0 +1,291 @@ +// ------------------------------------------------------ +// +// Copyright 2025 IHP PDK Authors +// +// Licensed under the Apache License, Version 2.0 (the "License"); +// you may not use this file except in compliance with the License. +// You may obtain a copy of the License at +// +// https://www.apache.org/licenses/LICENSE-2.0 +// +// Unless required by applicable law or agreed to in writing, software +// distributed under the License is distributed on an "AS IS" BASIS, +// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +// See the License for the specific language governing permissions and +// limitations under the License. +// +// Generated on Wed Aug 27 13:11:34 2025 +// +// ------------------------------------------------------ +`celldefine +module RM_IHPSG13_2P_512x32_c2_bm_bist ( + A_CLK, + A_MEN, + A_WEN, + A_REN, + A_ADDR, + A_DIN, + A_DLY, + A_DOUT, + A_BM, + A_BIST_CLK, + A_BIST_EN, + A_BIST_MEN, + A_BIST_WEN, + A_BIST_REN, + A_BIST_ADDR, + A_BIST_DIN, + A_BIST_BM, + B_CLK, + B_MEN, + B_WEN, + B_REN, + B_ADDR, + B_DIN, + B_DLY, + B_DOUT, + B_BM, + B_BIST_CLK, + B_BIST_EN, + B_BIST_MEN, + B_BIST_WEN, + B_BIST_REN, + B_BIST_ADDR, + B_BIST_DIN, + B_BIST_BM +); + + input A_CLK; + input A_MEN; + input A_WEN; + input A_REN; + input [8:0] A_ADDR; + input [31:0] A_DIN; + input A_DLY; + output [31:0] A_DOUT; + input [31:0] A_BM; + input A_BIST_CLK; + input A_BIST_EN; + input A_BIST_MEN; + input A_BIST_WEN; + input A_BIST_REN; + input [8:0] A_BIST_ADDR; + input [31:0] A_BIST_DIN; + input [31:0] A_BIST_BM; + input B_CLK; + input B_MEN; + input B_WEN; + input B_REN; + input [8:0] B_ADDR; + input [31:0] B_DIN; + input B_DLY; + output [31:0] B_DOUT; + input [31:0] B_BM; + input B_BIST_CLK; + input B_BIST_EN; + input B_BIST_MEN; + input B_BIST_WEN; + input B_BIST_REN; + input [8:0] B_BIST_ADDR; + input [31:0] B_BIST_DIN; + input [31:0] B_BIST_BM; + + +`ifdef FUNCTIONAL // functional // + + + SRAM_2P_behavioral_bm_bist #( + .P_DATA_WIDTH(32), + .P_ADDR_WIDTH(9) + ) i_SRAM_2P_behavioral_bm_bist ( + .A_CLK(A_CLK), + .A_MEN(A_MEN), + .A_WEN(A_WEN), + .A_REN(A_REN), + .A_ADDR(A_ADDR), + .A_DLY(A_DLY), + .A_DIN(A_DIN), + .A_DOUT(A_DOUT), + .A_BM(A_BM), + .A_BIST_CLK(A_BIST_CLK), + .A_BIST_EN(A_BIST_EN), + .A_BIST_MEN(A_BIST_MEN), + .A_BIST_WEN(A_BIST_WEN), + .A_BIST_REN(A_BIST_REN), + .A_BIST_ADDR(A_BIST_ADDR), + .A_BIST_DIN(A_BIST_DIN), + .A_BIST_BM(A_BIST_BM), + .B_CLK(B_CLK), + .B_MEN(B_MEN), + .B_WEN(B_WEN), + .B_REN(B_REN), + .B_ADDR(B_ADDR), + .B_DLY(B_DLY), + .B_DIN(B_DIN), + .B_DOUT(B_DOUT), + .B_BM(B_BM), + .B_BIST_CLK(B_BIST_CLK), + .B_BIST_EN(B_BIST_EN), + .B_BIST_MEN(B_BIST_MEN), + .B_BIST_WEN(B_BIST_WEN), + .B_BIST_REN(B_BIST_REN), + .B_BIST_ADDR(B_BIST_ADDR), + .B_BIST_DIN(B_BIST_DIN), + .B_BIST_BM(B_BIST_BM) + ); + +`else + + wire A_CLK_DELAY; + wire A_MEN_DELAY; + wire A_WEN_DELAY; + wire A_REN_DELAY; + wire [8:0] A_ADDR_DELAY; + wire [31:0] A_DIN_DELAY; + wire [31:0] A_BM_DELAY; + wire A_BIST_CLK_DELAY; + wire A_BIST_MEN_DELAY; + wire A_BIST_WEN_DELAY; + wire A_BIST_REN_DELAY; + wire [8:0] A_BIST_ADDR_DELAY; + wire [31:0] A_BIST_DIN_DELAY; + wire [31:0] A_BIST_BM_DELAY; + wire B_CLK_DELAY; + wire B_MEN_DELAY; + wire B_WEN_DELAY; + wire B_REN_DELAY; + wire [8:0] B_ADDR_DELAY; + wire [31:0] B_DIN_DELAY; + wire [31:0] B_BM_DELAY; + wire B_BIST_CLK_DELAY; + wire B_BIST_MEN_DELAY; + wire B_BIST_WEN_DELAY; + wire B_BIST_REN_DELAY; + wire [8:0] B_BIST_ADDR_DELAY; + wire [31:0] B_BIST_DIN_DELAY; + wire [31:0] B_BIST_BM_DELAY; + + reg notifier; + + wire A_RW_ACCESS = (A_WEN || A_REN) && A_MEN; + wire A_W_ACCESS = A_WEN && A_MEN; + wire A_BIST_RW_ACCESS = (A_BIST_WEN || A_BIST_REN) && A_BIST_MEN; + wire A_BIST_W_ACCESS = A_BIST_WEN && A_BIST_MEN; + + wire B_RW_ACCESS = (B_WEN || B_REN) && B_MEN; + wire B_W_ACCESS = B_WEN && B_MEN; + wire B_BIST_RW_ACCESS = (B_BIST_WEN || B_BIST_REN) && B_BIST_MEN; + wire B_BIST_W_ACCESS = B_BIST_WEN && B_BIST_MEN; + + + SRAM_2P_behavioral_bm_bist #( + .P_DATA_WIDTH(32), + .P_ADDR_WIDTH(9) + ) i_SRAM_2P_behavioral_bm_bist ( + .A_CLK(A_CLK_DELAY), + .A_MEN(A_MEN_DELAY), + .A_WEN(A_WEN_DELAY), + .A_REN(A_REN_DELAY), + .A_ADDR(A_ADDR_DELAY), + .A_DLY(A_DLY), + .A_DIN(A_DIN_DELAY), + .A_DOUT(A_DOUT), + .A_BM(A_BM_DELAY), + .A_BIST_CLK(A_BIST_CLK_DELAY), + .A_BIST_EN(A_BIST_EN), + .A_BIST_MEN(A_BIST_MEN_DELAY), + .A_BIST_WEN(A_BIST_WEN_DELAY), + .A_BIST_REN(A_BIST_REN_DELAY), + .A_BIST_ADDR(A_BIST_ADDR_DELAY), + .A_BIST_DIN(A_BIST_DIN_DELAY), + .A_BIST_BM(A_BIST_BM_DELAY), + .B_CLK(B_CLK_DELAY), + .B_MEN(B_MEN_DELAY), + .B_WEN(B_WEN_DELAY), + .B_REN(B_REN_DELAY), + .B_ADDR(B_ADDR_DELAY), + .B_DLY(B_DLY), + .B_DIN(B_DIN_DELAY), + .B_DOUT(B_DOUT), + .B_BM(B_BM_DELAY), + .B_BIST_CLK(B_BIST_CLK_DELAY), + .B_BIST_EN(B_BIST_EN), + .B_BIST_MEN(B_BIST_MEN_DELAY), + .B_BIST_WEN(B_BIST_WEN_DELAY), + .B_BIST_REN(B_BIST_REN_DELAY), + .B_BIST_ADDR(B_BIST_ADDR_DELAY), + .B_BIST_DIN(B_BIST_DIN_DELAY), + .B_BIST_BM(B_BIST_BM_DELAY) + ); + + + specify + + (posedge A_CLK *> (A_DOUT : A_DIN)) = (1.0, 1.0); + $width(posedge A_CLK, 1.0,0,notifier); + $setuphold(posedge A_CLK &&& A_MEN, posedge A_MEN, 1.0, 1.0,notifier,,,A_CLK_DELAY, A_MEN_DELAY); + $setuphold(posedge A_CLK &&& A_MEN, posedge A_REN, 1.0, 1.0,notifier,,,A_CLK_DELAY, A_REN_DELAY); + $setuphold(posedge A_CLK &&& A_MEN, posedge A_WEN, 1.0, 1.0,notifier,,,A_CLK_DELAY, A_WEN_DELAY); + $setuphold(posedge A_CLK &&& A_MEN, negedge A_MEN, 1.0, 1.0,notifier,,,A_CLK_DELAY, A_MEN_DELAY); + $setuphold(posedge A_CLK &&& A_MEN, negedge A_REN, 1.0, 1.0,notifier,,,A_CLK_DELAY, A_REN_DELAY); + $setuphold(posedge A_CLK &&& A_MEN, negedge A_WEN, 1.0, 1.0,notifier,,,A_CLK_DELAY, A_WEN_DELAY); + $setuphold(posedge A_CLK &&& A_RW_ACCESS, posedge A_ADDR, 1.0 ,1.0, notifier,,,A_CLK_DELAY, A_ADDR_DELAY); + $setuphold(posedge A_CLK &&& A_RW_ACCESS, negedge A_ADDR, 1.0 ,1.0, notifier,,,A_CLK_DELAY, A_ADDR_DELAY); + + $setuphold(posedge A_CLK &&& A_W_ACCESS, posedge A_DIN, 1.0 ,1.0, notifier,,,A_CLK_DELAY, A_DIN_DELAY); + $setuphold(posedge A_CLK &&& A_W_ACCESS, negedge A_DIN, 1.0 ,1.0, notifier,,,A_CLK_DELAY, A_DIN_DELAY); + $setuphold(posedge A_CLK &&& A_W_ACCESS, posedge A_BM, 1.0 ,1.0, notifier,,,A_CLK_DELAY, A_BM_DELAY); + $setuphold(posedge A_CLK &&& A_W_ACCESS, negedge A_BM, 1.0 ,1.0, notifier,,,A_CLK_DELAY, A_BM_DELAY); + (posedge A_BIST_CLK *> (A_DOUT : A_BIST_DIN)) = (1.0, 1.0); + $width(posedge A_BIST_CLK, 1.0,0,notifier); + $setuphold(posedge A_BIST_CLK &&& A_BIST_MEN, posedge A_BIST_MEN, 1.0, 1.0,notifier,,,A_BIST_CLK_DELAY, A_BIST_MEN_DELAY); + $setuphold(posedge A_BIST_CLK &&& A_BIST_MEN, posedge A_BIST_REN, 1.0, 1.0,notifier,,,A_BIST_CLK_DELAY, A_BIST_REN_DELAY); + $setuphold(posedge A_BIST_CLK &&& A_BIST_MEN, posedge A_BIST_WEN, 1.0, 1.0,notifier,,,A_BIST_CLK_DELAY, A_BIST_WEN_DELAY); + $setuphold(posedge A_BIST_CLK &&& A_BIST_MEN, negedge A_BIST_MEN, 1.0, 1.0,notifier,,,A_BIST_CLK_DELAY, A_BIST_MEN_DELAY); + $setuphold(posedge A_BIST_CLK &&& A_BIST_MEN, negedge A_BIST_REN, 1.0, 1.0,notifier,,,A_BIST_CLK_DELAY, A_BIST_REN_DELAY); + $setuphold(posedge A_BIST_CLK &&& A_BIST_MEN, negedge A_BIST_WEN, 1.0, 1.0,notifier,,,A_BIST_CLK_DELAY, A_BIST_WEN_DELAY); + $setuphold(posedge A_BIST_CLK &&& A_BIST_RW_ACCESS, posedge A_BIST_ADDR, 1.0 ,1.0, notifier,,,A_BIST_CLK_DELAY, A_BIST_ADDR_DELAY); + $setuphold(posedge A_BIST_CLK &&& A_BIST_RW_ACCESS, negedge A_BIST_ADDR, 1.0 ,1.0, notifier,,,A_BIST_CLK_DELAY, A_BIST_ADDR_DELAY); + + $setuphold(posedge A_BIST_CLK &&& A_BIST_W_ACCESS, posedge A_BIST_DIN, 1.0 ,1.0, notifier,,,A_BIST_CLK_DELAY, A_BIST_DIN_DELAY); + $setuphold(posedge A_BIST_CLK &&& A_BIST_W_ACCESS, negedge A_BIST_DIN, 1.0 ,1.0, notifier,,,A_BIST_CLK_DELAY, A_BIST_DIN_DELAY); + $setuphold(posedge A_BIST_CLK &&& A_BIST_W_ACCESS, posedge A_BIST_BM, 1.0 ,1.0, notifier,,,A_BIST_CLK_DELAY, A_BIST_BM_DELAY); + $setuphold(posedge A_BIST_CLK &&& A_BIST_W_ACCESS, negedge A_BIST_BM, 1.0 ,1.0, notifier,,,A_BIST_CLK_DELAY, A_BIST_BM_DELAY); + + (posedge B_CLK *> (B_DOUT : B_DIN)) = (1.0, 1.0); + $width(posedge B_CLK, 1.0,0,notifier); + $setuphold(posedge B_CLK &&& B_MEN, posedge B_MEN, 1.0, 1.0,notifier,,,B_CLK_DELAY, B_MEN_DELAY); + $setuphold(posedge B_CLK &&& B_MEN, posedge B_REN, 1.0, 1.0,notifier,,,B_CLK_DELAY, B_REN_DELAY); + $setuphold(posedge B_CLK &&& B_MEN, posedge B_WEN, 1.0, 1.0,notifier,,,B_CLK_DELAY, B_WEN_DELAY); + $setuphold(posedge B_CLK &&& B_MEN, negedge B_MEN, 1.0, 1.0,notifier,,,B_CLK_DELAY, B_MEN_DELAY); + $setuphold(posedge B_CLK &&& B_MEN, negedge B_REN, 1.0, 1.0,notifier,,,B_CLK_DELAY, B_REN_DELAY); + $setuphold(posedge B_CLK &&& B_MEN, negedge B_WEN, 1.0, 1.0,notifier,,,B_CLK_DELAY, B_WEN_DELAY); + $setuphold(posedge B_CLK &&& B_RW_ACCESS, posedge B_ADDR, 1.0 ,1.0, notifier,,,B_CLK_DELAY, B_ADDR_DELAY); + $setuphold(posedge B_CLK &&& B_RW_ACCESS, negedge B_ADDR, 1.0 ,1.0, notifier,,,B_CLK_DELAY, B_ADDR_DELAY); + + $setuphold(posedge B_CLK &&& B_W_ACCESS, posedge B_DIN, 1.0 ,1.0, notifier,,,B_CLK_DELAY, B_DIN_DELAY); + $setuphold(posedge B_CLK &&& B_W_ACCESS, negedge B_DIN, 1.0 ,1.0, notifier,,,B_CLK_DELAY, B_DIN_DELAY); + $setuphold(posedge B_CLK &&& B_W_ACCESS, posedge B_BM, 1.0 ,1.0, notifier,,,B_CLK_DELAY, B_BM_DELAY); + $setuphold(posedge B_CLK &&& B_W_ACCESS, negedge B_BM, 1.0 ,1.0, notifier,,,B_CLK_DELAY, B_BM_DELAY); + (posedge B_BIST_CLK *> (B_DOUT : B_BIST_DIN)) = (1.0, 1.0); + $width(posedge B_BIST_CLK, 1.0,0,notifier); + $setuphold(posedge B_BIST_CLK &&& B_BIST_MEN, posedge B_BIST_MEN, 1.0, 1.0,notifier,,,B_BIST_CLK_DELAY, B_BIST_MEN_DELAY); + $setuphold(posedge B_BIST_CLK &&& B_BIST_MEN, posedge B_BIST_REN, 1.0, 1.0,notifier,,,B_BIST_CLK_DELAY, B_BIST_REN_DELAY); + $setuphold(posedge B_BIST_CLK &&& B_BIST_MEN, posedge B_BIST_WEN, 1.0, 1.0,notifier,,,B_BIST_CLK_DELAY, B_BIST_WEN_DELAY); + $setuphold(posedge B_BIST_CLK &&& B_BIST_MEN, negedge B_BIST_MEN, 1.0, 1.0,notifier,,,B_BIST_CLK_DELAY, B_BIST_MEN_DELAY); + $setuphold(posedge B_BIST_CLK &&& B_BIST_MEN, negedge B_BIST_REN, 1.0, 1.0,notifier,,,B_BIST_CLK_DELAY, B_BIST_REN_DELAY); + $setuphold(posedge B_BIST_CLK &&& B_BIST_MEN, negedge B_BIST_WEN, 1.0, 1.0,notifier,,,B_BIST_CLK_DELAY, B_BIST_WEN_DELAY); + $setuphold(posedge B_BIST_CLK &&& B_BIST_RW_ACCESS, posedge B_BIST_ADDR, 1.0 ,1.0, notifier,,,B_BIST_CLK_DELAY, B_BIST_ADDR_DELAY); + $setuphold(posedge B_BIST_CLK &&& B_BIST_RW_ACCESS, negedge B_BIST_ADDR, 1.0 ,1.0, notifier,,,B_BIST_CLK_DELAY, B_BIST_ADDR_DELAY); + + $setuphold(posedge B_BIST_CLK &&& B_BIST_W_ACCESS, posedge B_BIST_DIN, 1.0 ,1.0, notifier,,,B_BIST_CLK_DELAY, B_BIST_DIN_DELAY); + $setuphold(posedge B_BIST_CLK &&& B_BIST_W_ACCESS, negedge B_BIST_DIN, 1.0 ,1.0, notifier,,,B_BIST_CLK_DELAY, B_BIST_DIN_DELAY); + $setuphold(posedge B_BIST_CLK &&& B_BIST_W_ACCESS, posedge B_BIST_BM, 1.0 ,1.0, notifier,,,B_BIST_CLK_DELAY, B_BIST_BM_DELAY); + $setuphold(posedge B_BIST_CLK &&& B_BIST_W_ACCESS, negedge B_BIST_BM, 1.0 ,1.0, notifier,,,B_BIST_CLK_DELAY, B_BIST_BM_DELAY); + + endspecify + +`endif + +endmodule +`endcelldefine \ No newline at end of file diff --git a/flow/platforms/ihp-sg13g2/verilog/RM_IHPSG13_2P_512x8_c2_bm_bist.v b/flow/platforms/ihp-sg13g2/verilog/RM_IHPSG13_2P_512x8_c2_bm_bist.v new file mode 100644 index 0000000000..c875863377 --- /dev/null +++ b/flow/platforms/ihp-sg13g2/verilog/RM_IHPSG13_2P_512x8_c2_bm_bist.v @@ -0,0 +1,291 @@ +// ------------------------------------------------------ +// +// Copyright 2025 IHP PDK Authors +// +// Licensed under the Apache License, Version 2.0 (the "License"); +// you may not use this file except in compliance with the License. +// You may obtain a copy of the License at +// +// https://www.apache.org/licenses/LICENSE-2.0 +// +// Unless required by applicable law or agreed to in writing, software +// distributed under the License is distributed on an "AS IS" BASIS, +// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +// See the License for the specific language governing permissions and +// limitations under the License. +// +// Generated on Wed Aug 27 13:34:43 2025 +// +// ------------------------------------------------------ +`celldefine +module RM_IHPSG13_2P_512x8_c2_bm_bist ( + A_CLK, + A_MEN, + A_WEN, + A_REN, + A_ADDR, + A_DIN, + A_DLY, + A_DOUT, + A_BM, + A_BIST_CLK, + A_BIST_EN, + A_BIST_MEN, + A_BIST_WEN, + A_BIST_REN, + A_BIST_ADDR, + A_BIST_DIN, + A_BIST_BM, + B_CLK, + B_MEN, + B_WEN, + B_REN, + B_ADDR, + B_DIN, + B_DLY, + B_DOUT, + B_BM, + B_BIST_CLK, + B_BIST_EN, + B_BIST_MEN, + B_BIST_WEN, + B_BIST_REN, + B_BIST_ADDR, + B_BIST_DIN, + B_BIST_BM +); + + input A_CLK; + input A_MEN; + input A_WEN; + input A_REN; + input [8:0] A_ADDR; + input [7:0] A_DIN; + input A_DLY; + output [7:0] A_DOUT; + input [7:0] A_BM; + input A_BIST_CLK; + input A_BIST_EN; + input A_BIST_MEN; + input A_BIST_WEN; + input A_BIST_REN; + input [8:0] A_BIST_ADDR; + input [7:0] A_BIST_DIN; + input [7:0] A_BIST_BM; + input B_CLK; + input B_MEN; + input B_WEN; + input B_REN; + input [8:0] B_ADDR; + input [7:0] B_DIN; + input B_DLY; + output [7:0] B_DOUT; + input [7:0] B_BM; + input B_BIST_CLK; + input B_BIST_EN; + input B_BIST_MEN; + input B_BIST_WEN; + input B_BIST_REN; + input [8:0] B_BIST_ADDR; + input [7:0] B_BIST_DIN; + input [7:0] B_BIST_BM; + + +`ifdef FUNCTIONAL // functional // + + + SRAM_2P_behavioral_bm_bist #( + .P_DATA_WIDTH(8), + .P_ADDR_WIDTH(9) + ) i_SRAM_2P_behavioral_bm_bist ( + .A_CLK(A_CLK), + .A_MEN(A_MEN), + .A_WEN(A_WEN), + .A_REN(A_REN), + .A_ADDR(A_ADDR), + .A_DLY(A_DLY), + .A_DIN(A_DIN), + .A_DOUT(A_DOUT), + .A_BM(A_BM), + .A_BIST_CLK(A_BIST_CLK), + .A_BIST_EN(A_BIST_EN), + .A_BIST_MEN(A_BIST_MEN), + .A_BIST_WEN(A_BIST_WEN), + .A_BIST_REN(A_BIST_REN), + .A_BIST_ADDR(A_BIST_ADDR), + .A_BIST_DIN(A_BIST_DIN), + .A_BIST_BM(A_BIST_BM), + .B_CLK(B_CLK), + .B_MEN(B_MEN), + .B_WEN(B_WEN), + .B_REN(B_REN), + .B_ADDR(B_ADDR), + .B_DLY(B_DLY), + .B_DIN(B_DIN), + .B_DOUT(B_DOUT), + .B_BM(B_BM), + .B_BIST_CLK(B_BIST_CLK), + .B_BIST_EN(B_BIST_EN), + .B_BIST_MEN(B_BIST_MEN), + .B_BIST_WEN(B_BIST_WEN), + .B_BIST_REN(B_BIST_REN), + .B_BIST_ADDR(B_BIST_ADDR), + .B_BIST_DIN(B_BIST_DIN), + .B_BIST_BM(B_BIST_BM) + ); + +`else + + wire A_CLK_DELAY; + wire A_MEN_DELAY; + wire A_WEN_DELAY; + wire A_REN_DELAY; + wire [8:0] A_ADDR_DELAY; + wire [7:0] A_DIN_DELAY; + wire [7:0] A_BM_DELAY; + wire A_BIST_CLK_DELAY; + wire A_BIST_MEN_DELAY; + wire A_BIST_WEN_DELAY; + wire A_BIST_REN_DELAY; + wire [8:0] A_BIST_ADDR_DELAY; + wire [7:0] A_BIST_DIN_DELAY; + wire [7:0] A_BIST_BM_DELAY; + wire B_CLK_DELAY; + wire B_MEN_DELAY; + wire B_WEN_DELAY; + wire B_REN_DELAY; + wire [8:0] B_ADDR_DELAY; + wire [7:0] B_DIN_DELAY; + wire [7:0] B_BM_DELAY; + wire B_BIST_CLK_DELAY; + wire B_BIST_MEN_DELAY; + wire B_BIST_WEN_DELAY; + wire B_BIST_REN_DELAY; + wire [8:0] B_BIST_ADDR_DELAY; + wire [7:0] B_BIST_DIN_DELAY; + wire [7:0] B_BIST_BM_DELAY; + + reg notifier; + + wire A_RW_ACCESS = (A_WEN || A_REN) && A_MEN; + wire A_W_ACCESS = A_WEN && A_MEN; + wire A_BIST_RW_ACCESS = (A_BIST_WEN || A_BIST_REN) && A_BIST_MEN; + wire A_BIST_W_ACCESS = A_BIST_WEN && A_BIST_MEN; + + wire B_RW_ACCESS = (B_WEN || B_REN) && B_MEN; + wire B_W_ACCESS = B_WEN && B_MEN; + wire B_BIST_RW_ACCESS = (B_BIST_WEN || B_BIST_REN) && B_BIST_MEN; + wire B_BIST_W_ACCESS = B_BIST_WEN && B_BIST_MEN; + + + SRAM_2P_behavioral_bm_bist #( + .P_DATA_WIDTH(8), + .P_ADDR_WIDTH(9) + ) i_SRAM_2P_behavioral_bm_bist ( + .A_CLK(A_CLK_DELAY), + .A_MEN(A_MEN_DELAY), + .A_WEN(A_WEN_DELAY), + .A_REN(A_REN_DELAY), + .A_ADDR(A_ADDR_DELAY), + .A_DLY(A_DLY), + .A_DIN(A_DIN_DELAY), + .A_DOUT(A_DOUT), + .A_BM(A_BM_DELAY), + .A_BIST_CLK(A_BIST_CLK_DELAY), + .A_BIST_EN(A_BIST_EN), + .A_BIST_MEN(A_BIST_MEN_DELAY), + .A_BIST_WEN(A_BIST_WEN_DELAY), + .A_BIST_REN(A_BIST_REN_DELAY), + .A_BIST_ADDR(A_BIST_ADDR_DELAY), + .A_BIST_DIN(A_BIST_DIN_DELAY), + .A_BIST_BM(A_BIST_BM_DELAY), + .B_CLK(B_CLK_DELAY), + .B_MEN(B_MEN_DELAY), + .B_WEN(B_WEN_DELAY), + .B_REN(B_REN_DELAY), + .B_ADDR(B_ADDR_DELAY), + .B_DLY(B_DLY), + .B_DIN(B_DIN_DELAY), + .B_DOUT(B_DOUT), + .B_BM(B_BM_DELAY), + .B_BIST_CLK(B_BIST_CLK_DELAY), + .B_BIST_EN(B_BIST_EN), + .B_BIST_MEN(B_BIST_MEN_DELAY), + .B_BIST_WEN(B_BIST_WEN_DELAY), + .B_BIST_REN(B_BIST_REN_DELAY), + .B_BIST_ADDR(B_BIST_ADDR_DELAY), + .B_BIST_DIN(B_BIST_DIN_DELAY), + .B_BIST_BM(B_BIST_BM_DELAY) + ); + + + specify + + (posedge A_CLK *> (A_DOUT : A_DIN)) = (1.0, 1.0); + $width(posedge A_CLK, 1.0,0,notifier); + $setuphold(posedge A_CLK &&& A_MEN, posedge A_MEN, 1.0, 1.0,notifier,,,A_CLK_DELAY, A_MEN_DELAY); + $setuphold(posedge A_CLK &&& A_MEN, posedge A_REN, 1.0, 1.0,notifier,,,A_CLK_DELAY, A_REN_DELAY); + $setuphold(posedge A_CLK &&& A_MEN, posedge A_WEN, 1.0, 1.0,notifier,,,A_CLK_DELAY, A_WEN_DELAY); + $setuphold(posedge A_CLK &&& A_MEN, negedge A_MEN, 1.0, 1.0,notifier,,,A_CLK_DELAY, A_MEN_DELAY); + $setuphold(posedge A_CLK &&& A_MEN, negedge A_REN, 1.0, 1.0,notifier,,,A_CLK_DELAY, A_REN_DELAY); + $setuphold(posedge A_CLK &&& A_MEN, negedge A_WEN, 1.0, 1.0,notifier,,,A_CLK_DELAY, A_WEN_DELAY); + $setuphold(posedge A_CLK &&& A_RW_ACCESS, posedge A_ADDR, 1.0 ,1.0, notifier,,,A_CLK_DELAY, A_ADDR_DELAY); + $setuphold(posedge A_CLK &&& A_RW_ACCESS, negedge A_ADDR, 1.0 ,1.0, notifier,,,A_CLK_DELAY, A_ADDR_DELAY); + + $setuphold(posedge A_CLK &&& A_W_ACCESS, posedge A_DIN, 1.0 ,1.0, notifier,,,A_CLK_DELAY, A_DIN_DELAY); + $setuphold(posedge A_CLK &&& A_W_ACCESS, negedge A_DIN, 1.0 ,1.0, notifier,,,A_CLK_DELAY, A_DIN_DELAY); + $setuphold(posedge A_CLK &&& A_W_ACCESS, posedge A_BM, 1.0 ,1.0, notifier,,,A_CLK_DELAY, A_BM_DELAY); + $setuphold(posedge A_CLK &&& A_W_ACCESS, negedge A_BM, 1.0 ,1.0, notifier,,,A_CLK_DELAY, A_BM_DELAY); + (posedge A_BIST_CLK *> (A_DOUT : A_BIST_DIN)) = (1.0, 1.0); + $width(posedge A_BIST_CLK, 1.0,0,notifier); + $setuphold(posedge A_BIST_CLK &&& A_BIST_MEN, posedge A_BIST_MEN, 1.0, 1.0,notifier,,,A_BIST_CLK_DELAY, A_BIST_MEN_DELAY); + $setuphold(posedge A_BIST_CLK &&& A_BIST_MEN, posedge A_BIST_REN, 1.0, 1.0,notifier,,,A_BIST_CLK_DELAY, A_BIST_REN_DELAY); + $setuphold(posedge A_BIST_CLK &&& A_BIST_MEN, posedge A_BIST_WEN, 1.0, 1.0,notifier,,,A_BIST_CLK_DELAY, A_BIST_WEN_DELAY); + $setuphold(posedge A_BIST_CLK &&& A_BIST_MEN, negedge A_BIST_MEN, 1.0, 1.0,notifier,,,A_BIST_CLK_DELAY, A_BIST_MEN_DELAY); + $setuphold(posedge A_BIST_CLK &&& A_BIST_MEN, negedge A_BIST_REN, 1.0, 1.0,notifier,,,A_BIST_CLK_DELAY, A_BIST_REN_DELAY); + $setuphold(posedge A_BIST_CLK &&& A_BIST_MEN, negedge A_BIST_WEN, 1.0, 1.0,notifier,,,A_BIST_CLK_DELAY, A_BIST_WEN_DELAY); + $setuphold(posedge A_BIST_CLK &&& A_BIST_RW_ACCESS, posedge A_BIST_ADDR, 1.0 ,1.0, notifier,,,A_BIST_CLK_DELAY, A_BIST_ADDR_DELAY); + $setuphold(posedge A_BIST_CLK &&& A_BIST_RW_ACCESS, negedge A_BIST_ADDR, 1.0 ,1.0, notifier,,,A_BIST_CLK_DELAY, A_BIST_ADDR_DELAY); + + $setuphold(posedge A_BIST_CLK &&& A_BIST_W_ACCESS, posedge A_BIST_DIN, 1.0 ,1.0, notifier,,,A_BIST_CLK_DELAY, A_BIST_DIN_DELAY); + $setuphold(posedge A_BIST_CLK &&& A_BIST_W_ACCESS, negedge A_BIST_DIN, 1.0 ,1.0, notifier,,,A_BIST_CLK_DELAY, A_BIST_DIN_DELAY); + $setuphold(posedge A_BIST_CLK &&& A_BIST_W_ACCESS, posedge A_BIST_BM, 1.0 ,1.0, notifier,,,A_BIST_CLK_DELAY, A_BIST_BM_DELAY); + $setuphold(posedge A_BIST_CLK &&& A_BIST_W_ACCESS, negedge A_BIST_BM, 1.0 ,1.0, notifier,,,A_BIST_CLK_DELAY, A_BIST_BM_DELAY); + + (posedge B_CLK *> (B_DOUT : B_DIN)) = (1.0, 1.0); + $width(posedge B_CLK, 1.0,0,notifier); + $setuphold(posedge B_CLK &&& B_MEN, posedge B_MEN, 1.0, 1.0,notifier,,,B_CLK_DELAY, B_MEN_DELAY); + $setuphold(posedge B_CLK &&& B_MEN, posedge B_REN, 1.0, 1.0,notifier,,,B_CLK_DELAY, B_REN_DELAY); + $setuphold(posedge B_CLK &&& B_MEN, posedge B_WEN, 1.0, 1.0,notifier,,,B_CLK_DELAY, B_WEN_DELAY); + $setuphold(posedge B_CLK &&& B_MEN, negedge B_MEN, 1.0, 1.0,notifier,,,B_CLK_DELAY, B_MEN_DELAY); + $setuphold(posedge B_CLK &&& B_MEN, negedge B_REN, 1.0, 1.0,notifier,,,B_CLK_DELAY, B_REN_DELAY); + $setuphold(posedge B_CLK &&& B_MEN, negedge B_WEN, 1.0, 1.0,notifier,,,B_CLK_DELAY, B_WEN_DELAY); + $setuphold(posedge B_CLK &&& B_RW_ACCESS, posedge B_ADDR, 1.0 ,1.0, notifier,,,B_CLK_DELAY, B_ADDR_DELAY); + $setuphold(posedge B_CLK &&& B_RW_ACCESS, negedge B_ADDR, 1.0 ,1.0, notifier,,,B_CLK_DELAY, B_ADDR_DELAY); + + $setuphold(posedge B_CLK &&& B_W_ACCESS, posedge B_DIN, 1.0 ,1.0, notifier,,,B_CLK_DELAY, B_DIN_DELAY); + $setuphold(posedge B_CLK &&& B_W_ACCESS, negedge B_DIN, 1.0 ,1.0, notifier,,,B_CLK_DELAY, B_DIN_DELAY); + $setuphold(posedge B_CLK &&& B_W_ACCESS, posedge B_BM, 1.0 ,1.0, notifier,,,B_CLK_DELAY, B_BM_DELAY); + $setuphold(posedge B_CLK &&& B_W_ACCESS, negedge B_BM, 1.0 ,1.0, notifier,,,B_CLK_DELAY, B_BM_DELAY); + (posedge B_BIST_CLK *> (B_DOUT : B_BIST_DIN)) = (1.0, 1.0); + $width(posedge B_BIST_CLK, 1.0,0,notifier); + $setuphold(posedge B_BIST_CLK &&& B_BIST_MEN, posedge B_BIST_MEN, 1.0, 1.0,notifier,,,B_BIST_CLK_DELAY, B_BIST_MEN_DELAY); + $setuphold(posedge B_BIST_CLK &&& B_BIST_MEN, posedge B_BIST_REN, 1.0, 1.0,notifier,,,B_BIST_CLK_DELAY, B_BIST_REN_DELAY); + $setuphold(posedge B_BIST_CLK &&& B_BIST_MEN, posedge B_BIST_WEN, 1.0, 1.0,notifier,,,B_BIST_CLK_DELAY, B_BIST_WEN_DELAY); + $setuphold(posedge B_BIST_CLK &&& B_BIST_MEN, negedge B_BIST_MEN, 1.0, 1.0,notifier,,,B_BIST_CLK_DELAY, B_BIST_MEN_DELAY); + $setuphold(posedge B_BIST_CLK &&& B_BIST_MEN, negedge B_BIST_REN, 1.0, 1.0,notifier,,,B_BIST_CLK_DELAY, B_BIST_REN_DELAY); + $setuphold(posedge B_BIST_CLK &&& B_BIST_MEN, negedge B_BIST_WEN, 1.0, 1.0,notifier,,,B_BIST_CLK_DELAY, B_BIST_WEN_DELAY); + $setuphold(posedge B_BIST_CLK &&& B_BIST_RW_ACCESS, posedge B_BIST_ADDR, 1.0 ,1.0, notifier,,,B_BIST_CLK_DELAY, B_BIST_ADDR_DELAY); + $setuphold(posedge B_BIST_CLK &&& B_BIST_RW_ACCESS, negedge B_BIST_ADDR, 1.0 ,1.0, notifier,,,B_BIST_CLK_DELAY, B_BIST_ADDR_DELAY); + + $setuphold(posedge B_BIST_CLK &&& B_BIST_W_ACCESS, posedge B_BIST_DIN, 1.0 ,1.0, notifier,,,B_BIST_CLK_DELAY, B_BIST_DIN_DELAY); + $setuphold(posedge B_BIST_CLK &&& B_BIST_W_ACCESS, negedge B_BIST_DIN, 1.0 ,1.0, notifier,,,B_BIST_CLK_DELAY, B_BIST_DIN_DELAY); + $setuphold(posedge B_BIST_CLK &&& B_BIST_W_ACCESS, posedge B_BIST_BM, 1.0 ,1.0, notifier,,,B_BIST_CLK_DELAY, B_BIST_BM_DELAY); + $setuphold(posedge B_BIST_CLK &&& B_BIST_W_ACCESS, negedge B_BIST_BM, 1.0 ,1.0, notifier,,,B_BIST_CLK_DELAY, B_BIST_BM_DELAY); + + endspecify + +`endif + +endmodule +`endcelldefine \ No newline at end of file diff --git a/flow/platforms/ihp-sg13g2/verilog/RM_IHPSG13_2P_64x32_c2.v b/flow/platforms/ihp-sg13g2/verilog/RM_IHPSG13_2P_64x32_c2.v new file mode 100644 index 0000000000..e2eb5c185f --- /dev/null +++ b/flow/platforms/ihp-sg13g2/verilog/RM_IHPSG13_2P_64x32_c2.v @@ -0,0 +1,165 @@ +// ------------------------------------------------------ +// +// Copyright 2023 IHP PDK Authors +// +// Licensed under the Apache License, Version 2.0 (the "License"); +// you may not use this file except in compliance with the License. +// You may obtain a copy of the License at +// +// https://www.apache.org/licenses/LICENSE-2.0 +// +// Unless required by applicable law or agreed to in writing, software +// distributed under the License is distributed on an "AS IS" BASIS, +// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +// See the License for the specific language governing permissions and +// limitations under the License. +// +// Generated on Thu Jun 12 11:08:49 2025 +// +// ------------------------------------------------------ +`celldefine +module RM_IHPSG13_2P_64x32_c2 ( + A_CLK, + A_MEN, + A_WEN, + A_REN, + A_ADDR, + A_DIN, + A_DLY, + A_DOUT, + B_CLK, + B_MEN, + B_WEN, + B_REN, + B_ADDR, + B_DIN, + B_DLY, + B_DOUT +); + + input A_CLK; + input A_MEN; + input A_WEN; + input A_REN; + input [5:0] A_ADDR; + input [31:0] A_DIN; + input A_DLY; + output [31:0] A_DOUT; + input B_CLK; + input B_MEN; + input B_WEN; + input B_REN; + input [5:0] B_ADDR; + input [31:0] B_DIN; + input B_DLY; + output [31:0] B_DOUT; + + +`ifdef FUNCTIONAL // functional // + + + SRAM_2P_behavioral #( + .P_DATA_WIDTH(32), + .P_ADDR_WIDTH(6) + ) i_SRAM_2P_behavioral ( + .A_CLK(A_CLK), + .A_MEN(A_MEN), + .A_WEN(A_WEN), + .A_REN(A_REN), + .A_ADDR(A_ADDR), + .A_DLY(A_DLY), + .A_DIN(A_DIN), + .A_DOUT(A_DOUT), + .B_CLK(B_CLK), + .B_MEN(B_MEN), + .B_WEN(B_WEN), + .B_REN(B_REN), + .B_ADDR(B_ADDR), + .B_DLY(B_DLY), + .B_DIN(B_DIN), + .B_DOUT(B_DOUT) + ); + +`else + + wire A_CLK_DELAY; + wire A_MEN_DELAY; + wire A_WEN_DELAY; + wire A_REN_DELAY; + wire [5:0] A_ADDR_DELAY; + wire [31:0] A_DIN_DELAY; + wire B_CLK_DELAY; + wire B_MEN_DELAY; + wire B_WEN_DELAY; + wire B_REN_DELAY; + wire [5:0] B_ADDR_DELAY; + wire [31:0] B_DIN_DELAY; + + reg notifier; + + wire A_RW_ACCESS = (A_WEN || A_REN) && A_MEN; + wire A_W_ACCESS = A_WEN && A_MEN; + + wire B_RW_ACCESS = (B_WEN || B_REN) && B_MEN; + wire B_W_ACCESS = B_WEN && B_MEN; + + + SRAM_2P_behavioral #( + .P_DATA_WIDTH(32), + .P_ADDR_WIDTH(6) + ) i_SRAM_2P_behavioral ( + .A_CLK(A_CLK_DELAY), + .A_MEN(A_MEN_DELAY), + .A_WEN(A_WEN_DELAY), + .A_REN(A_REN_DELAY), + .A_ADDR(A_ADDR_DELAY), + .A_DLY(A_DLY), + .A_DIN(A_DIN_DELAY), + .A_DOUT(A_DOUT), + .B_CLK(B_CLK_DELAY), + .B_MEN(B_MEN_DELAY), + .B_WEN(B_WEN_DELAY), + .B_REN(B_REN_DELAY), + .B_ADDR(B_ADDR_DELAY), + .B_DLY(B_DLY), + .B_DIN(B_DIN_DELAY), + .B_DOUT(B_DOUT) + ); + + + specify + + (posedge A_CLK *> (A_DOUT : A_DIN)) = (1.0, 1.0); + $width(posedge A_CLK, 1.0,0,notifier); + $setuphold(posedge A_CLK &&& A_MEN, posedge A_MEN, 1.0, 1.0,notifier,,,A_CLK_DELAY, A_MEN_DELAY); + $setuphold(posedge A_CLK &&& A_MEN, posedge A_REN, 1.0, 1.0,notifier,,,A_CLK_DELAY, A_REN_DELAY); + $setuphold(posedge A_CLK &&& A_MEN, posedge A_WEN, 1.0, 1.0,notifier,,,A_CLK_DELAY, A_WEN_DELAY); + $setuphold(posedge A_CLK &&& A_MEN, negedge A_MEN, 1.0, 1.0,notifier,,,A_CLK_DELAY, A_MEN_DELAY); + $setuphold(posedge A_CLK &&& A_MEN, negedge A_REN, 1.0, 1.0,notifier,,,A_CLK_DELAY, A_REN_DELAY); + $setuphold(posedge A_CLK &&& A_MEN, negedge A_WEN, 1.0, 1.0,notifier,,,A_CLK_DELAY, A_WEN_DELAY); + $setuphold(posedge A_CLK &&& A_RW_ACCESS, posedge A_ADDR, 1.0 ,1.0, notifier,,,A_CLK_DELAY, A_ADDR_DELAY); + $setuphold(posedge A_CLK &&& A_RW_ACCESS, negedge A_ADDR, 1.0 ,1.0, notifier,,,A_CLK_DELAY, A_ADDR_DELAY); + + $setuphold(posedge A_CLK &&& A_W_ACCESS, posedge A_DIN, 1.0 ,1.0, notifier,,,A_CLK_DELAY, A_DIN_DELAY); + $setuphold(posedge A_CLK &&& A_W_ACCESS, negedge A_DIN, 1.0 ,1.0, notifier,,,A_CLK_DELAY, A_DIN_DELAY); + + (posedge B_CLK *> (B_DOUT : B_DIN)) = (1.0, 1.0); + $width(posedge B_CLK, 1.0,0,notifier); + $setuphold(posedge B_CLK &&& B_MEN, posedge B_MEN, 1.0, 1.0,notifier,,,B_CLK_DELAY, B_MEN_DELAY); + $setuphold(posedge B_CLK &&& B_MEN, posedge B_REN, 1.0, 1.0,notifier,,,B_CLK_DELAY, B_REN_DELAY); + $setuphold(posedge B_CLK &&& B_MEN, posedge B_WEN, 1.0, 1.0,notifier,,,B_CLK_DELAY, B_WEN_DELAY); + $setuphold(posedge B_CLK &&& B_MEN, negedge B_MEN, 1.0, 1.0,notifier,,,B_CLK_DELAY, B_MEN_DELAY); + $setuphold(posedge B_CLK &&& B_MEN, negedge B_REN, 1.0, 1.0,notifier,,,B_CLK_DELAY, B_REN_DELAY); + $setuphold(posedge B_CLK &&& B_MEN, negedge B_WEN, 1.0, 1.0,notifier,,,B_CLK_DELAY, B_WEN_DELAY); + $setuphold(posedge B_CLK &&& B_RW_ACCESS, posedge B_ADDR, 1.0 ,1.0, notifier,,,B_CLK_DELAY, B_ADDR_DELAY); + $setuphold(posedge B_CLK &&& B_RW_ACCESS, negedge B_ADDR, 1.0 ,1.0, notifier,,,B_CLK_DELAY, B_ADDR_DELAY); + + $setuphold(posedge B_CLK &&& B_W_ACCESS, posedge B_DIN, 1.0 ,1.0, notifier,,,B_CLK_DELAY, B_DIN_DELAY); + $setuphold(posedge B_CLK &&& B_W_ACCESS, negedge B_DIN, 1.0 ,1.0, notifier,,,B_CLK_DELAY, B_DIN_DELAY); + + endspecify + +`endif + +endmodule +`endcelldefine \ No newline at end of file diff --git a/flow/platforms/ihp-sg13g2/verilog/sg13g2_io.v b/flow/platforms/ihp-sg13g2/verilog/sg13g2_io.v index 1fa45dfc54..63187fdda3 100644 --- a/flow/platforms/ihp-sg13g2/verilog/sg13g2_io.v +++ b/flow/platforms/ihp-sg13g2/verilog/sg13g2_io.v @@ -15,55 +15,88 @@ // type: Corner `timescale 1ns/10ps `celldefine -module sg13g2_Corner (); +module sg13g2_Corner (iovdd, iovss, vdd, vss); + inout iovdd; + inout iovss; + inout vdd; + inout vss; endmodule `endcelldefine // type: Filler200 `timescale 1ns/10ps `celldefine -module sg13g2_Filler200 (); +module sg13g2_Filler200 (iovdd, iovss, vdd, vss); + inout iovdd; + inout iovss; + inout vdd; + inout vss; endmodule `endcelldefine // type: Filler400 `timescale 1ns/10ps `celldefine -module sg13g2_Filler400 (); +module sg13g2_Filler400 (iovdd, iovss, vdd, vss); + inout iovdd; + inout iovss; + inout vdd; + inout vss; endmodule `endcelldefine // type: Filler1000 `timescale 1ns/10ps `celldefine -module sg13g2_Filler1000 (); +module sg13g2_Filler1000 (iovdd, iovss, vdd, vss); + inout iovdd; + inout iovss; + inout vdd; + inout vss; endmodule `endcelldefine // type: Filler2000 `timescale 1ns/10ps `celldefine -module sg13g2_Filler2000 (); +module sg13g2_Filler2000 (iovdd, iovss, vdd, vss); + inout iovdd; + inout iovss; + inout vdd; + inout vss; endmodule `endcelldefine // type: Filler4000 `timescale 1ns/10ps `celldefine -module sg13g2_Filler4000 (); +module sg13g2_Filler4000 (iovdd, iovss, vdd, vss); + inout iovdd; + inout iovss; + inout vdd; + inout vss; endmodule `endcelldefine // type: Filler10000 `timescale 1ns/10ps `celldefine -module sg13g2_Filler10000 (); +module sg13g2_Filler10000 (iovdd, iovss, vdd, vss); + inout iovdd; + inout iovss; + inout vdd; + inout vss; endmodule `endcelldefine + // type: Input `timescale 1ns/10ps `celldefine -module sg13g2_IOPadIn (pad, p2c); +module sg13g2_IOPadIn (iovdd, iovss, vdd, vss, pad, p2c); + inout iovdd; + inout iovss; + inout vdd; + inout vss; inout pad; output p2c; @@ -80,7 +113,11 @@ endmodule // type: Output4mA `timescale 1ns/10ps `celldefine -module sg13g2_IOPadOut4mA (pad, c2p); +module sg13g2_IOPadOut4mA (iovdd, iovss, vdd, vss, pad, c2p); + inout iovdd; + inout iovss; + inout vdd; + inout vss; inout pad; input c2p; @@ -97,7 +134,11 @@ endmodule // type: Output16mA `timescale 1ns/10ps `celldefine -module sg13g2_IOPadOut16mA (pad, c2p); +module sg13g2_IOPadOut16mA (iovdd, iovss, vdd, vss, pad, c2p); + inout iovdd; + inout iovss; + inout vdd; + inout vss; inout pad; input c2p; @@ -114,7 +155,11 @@ endmodule // type: Output30mA `timescale 1ns/10ps `celldefine -module sg13g2_IOPadOut30mA (pad, c2p); +module sg13g2_IOPadOut30mA (iovdd, iovss, vdd, vss, pad, c2p); + inout iovdd; + inout iovss; + inout vdd; + inout vss; inout pad; input c2p; @@ -131,7 +176,11 @@ endmodule // type: TriStateOutput4mA `timescale 1ns/10ps `celldefine -module sg13g2_IOPadTriOut4mA (pad, c2p, c2p_en); +module sg13g2_IOPadTriOut4mA (iovdd, iovss, vdd, vss, pad, c2p, c2p_en); + inout iovdd; + inout iovss; + inout vdd; + inout vss; inout pad; input c2p; input c2p_en; @@ -150,7 +199,11 @@ endmodule // type: TriStateOutput16mA `timescale 1ns/10ps `celldefine -module sg13g2_IOPadTriOut16mA (pad, c2p, c2p_en); +module sg13g2_IOPadTriOut16mA (iovdd, iovss, vdd, vss, pad, c2p, c2p_en); + inout iovdd; + inout iovss; + inout vdd; + inout vss; inout pad; input c2p; input c2p_en; @@ -169,7 +222,11 @@ endmodule // type: TriStateOutput30mA `timescale 1ns/10ps `celldefine -module sg13g2_IOPadTriOut30mA (pad, c2p, c2p_en); +module sg13g2_IOPadTriOut30mA (iovdd, iovss, vdd, vss, pad, c2p, c2p_en); + inout iovdd; + inout iovss; + inout vdd; + inout vss; inout pad; input c2p; input c2p_en; @@ -188,7 +245,11 @@ endmodule // type: InputOutput4mA `timescale 1ns/10ps `celldefine -module sg13g2_IOPadInOut4mA (pad, c2p, c2p_en, p2c); +module sg13g2_IOPadInOut4mA (iovdd, iovss, vdd, vss, pad, c2p, c2p_en, p2c); + inout iovdd; + inout iovss; + inout vdd; + inout vss; inout pad; input c2p; input c2p_en; @@ -210,7 +271,11 @@ endmodule // type: InputOutput4mA `timescale 1ns/10ps `celldefine -module sg13g2_IOPadInOut16mA (pad, c2p, c2p_en, p2c); +module sg13g2_IOPadInOut16mA (iovdd, iovss, vdd, vss, pad, c2p, c2p_en, p2c); + inout iovdd; + inout iovss; + inout vdd; + inout vss; inout pad; input c2p; input c2p_en; @@ -232,7 +297,11 @@ endmodule // type: InputOutput4mA `timescale 1ns/10ps `celldefine -module sg13g2_IOPadInOut30mA (pad, c2p, c2p_en, p2c); +module sg13g2_IOPadInOut30mA (iovdd, iovss, vdd, vss, pad, c2p, c2p_en, p2c); + inout iovdd; + inout iovss; + inout vdd; + inout vss; inout pad; input c2p; input c2p_en; @@ -254,7 +323,11 @@ endmodule // type: Analog `timescale 1ns/10ps `celldefine -module sg13g2_IOPadAnalog (pad, padres); +module sg13g2_IOPadAnalog (iovdd, iovss, vdd, vss, pad, padres); + inout iovdd; + inout iovss; + inout vdd; + inout vss; inout pad; inout padres; @@ -273,27 +346,43 @@ endmodule // type: IOVss `timescale 1ns/10ps `celldefine -module sg13g2_IOPadIOVss (); +module sg13g2_IOPadIOVss (iovdd, iovss, vdd, vss); + inout iovdd; + inout iovss; + inout vdd; + inout vss; endmodule `endcelldefine // type: IOVdd `timescale 1ns/10ps `celldefine -module sg13g2_IOPadIOVdd (); +module sg13g2_IOPadIOVdd (iovdd, iovss, vdd, vss); + inout iovdd; + inout iovss; + inout vdd; + inout vss; endmodule `endcelldefine // type: Vss `timescale 1ns/10ps `celldefine -module sg13g2_IOPadVss (); +module sg13g2_IOPadVss (iovdd, iovss, vdd, vss); + inout iovdd; + inout iovss; + inout vdd; + inout vss; endmodule `endcelldefine // type: Vdd `timescale 1ns/10ps `celldefine -module sg13g2_IOPadVdd (); +module sg13g2_IOPadVdd (iovdd, iovss, vdd, vss); + inout iovdd; + inout iovss; + inout vdd; + inout vss; endmodule `endcelldefine diff --git a/flow/platforms/ihp-sg13g2/verilog/sg13g2_stdcell.v b/flow/platforms/ihp-sg13g2/verilog/sg13g2_stdcell.v index c4efa342f0..bdfa7a5ad1 100644 --- a/flow/platforms/ihp-sg13g2/verilog/sg13g2_stdcell.v +++ b/flow/platforms/ihp-sg13g2/verilog/sg13g2_stdcell.v @@ -12,10 +12,17 @@ // See the License for the specific language governing permissions and // limitations under the License. -// type: AO21 +// type: a21o `timescale 1ns/10ps `celldefine +//***************************************************************** +// technology : SG13G2 +// module name : sg13g2_a21o_1 +// cell_description : 2-input AND into first input of 2-input OR. +//***************************************************************** + module sg13g2_a21o_1 (X, A1, A2, B1); + output X; input A1, A2, B1; @@ -26,447 +33,799 @@ module sg13g2_a21o_1 (X, A1, A2, B1); or (X, int_fwire_0, B1); // Timing + specify if (B1 == 1'b0) - (A1 => X) = 0; - ifnone (A1 => X) = 0; + (posedge A1 => (X : A1)) = (0.0,0.0); + if (B1 == 1'b0) + (negedge A1 => (X : A1)) = (0.0,0.0); + ifnone + (posedge A1 => (X : A1)) = (0.0,0.0); + ifnone + (negedge A1 => (X : A1)) = (0.0,0.0); if (B1 == 1'b0) - (A2 => X) = 0; - ifnone (A2 => X) = 0; - if (A1 == 1'b1 & A2 == 1'b0) - (B1 => X) = 0; - if (A1 == 1'b0 & A2 == 1'b1) - (B1 => X) = 0; - if (A1 == 1'b0 & A2 == 1'b0) - (B1 => X) = 0; - ifnone (B1 => X) = 0; + (posedge A2 => (X : A2)) = (0.0,0.0); + if (B1 == 1'b0) + (negedge A2 => (X : A2)) = (0.0,0.0); + ifnone + (posedge A2 => (X : A2)) = (0.0,0.0); + ifnone + (negedge A2 => (X : A2)) = (0.0,0.0); + if (A1 == 1'b1 && A2 == 1'b0) + (posedge B1 => (X : B1)) = (0.0,0.0); + if (A1 == 1'b1 && A2 == 1'b0) + (negedge B1 => (X : B1)) = (0.0,0.0); + if (A1 == 1'b0 && A2 == 1'b1) + (posedge B1 => (X : B1)) = (0.0,0.0); + if (A1 == 1'b0 && A2 == 1'b1) + (negedge B1 => (X : B1)) = (0.0,0.0); + if (A1 == 1'b0 && A2 == 1'b0) + (posedge B1 => (X : B1)) = (0.0,0.0); + if (A1 == 1'b0 && A2 == 1'b0) + (negedge B1 => (X : B1)) = (0.0,0.0); + ifnone + (posedge B1 => (X : B1)) = (0.0,0.0); + ifnone + (negedge B1 => (X : B1)) = (0.0,0.0); endspecify + endmodule `endcelldefine -// type: AO21 +// type: a21o `timescale 1ns/10ps `celldefine +//***************************************************************** +// technology : SG13G2 +// module name : sg13g2_a21o_2 +// cell_description : 2-input AND into first input of 2-input OR. +//***************************************************************** + module sg13g2_a21o_2 (X, A1, A2, B1); + output X; input A1, A2, B1; // Function + wire int_fwire_0; and (int_fwire_0, A1, A2); or (X, int_fwire_0, B1); - + // Timing + specify if (B1 == 1'b0) - (A1 => X) = 0; - ifnone (A1 => X) = 0; + (posedge A1 => (X : A1)) = (0.0,0.0); + if (B1 == 1'b0) + (negedge A1 => (X : A1)) = (0.0,0.0); + ifnone + (posedge A1 => (X : A1)) = (0.0,0.0); + ifnone + (negedge A1 => (X : A1)) = (0.0,0.0); if (B1 == 1'b0) - (A2 => X) = 0; - ifnone (A2 => X) = 0; - if (A1 == 1'b1 & A2 == 1'b0) - (B1 => X) = 0; - if (A1 == 1'b0 & A2 == 1'b1) - (B1 => X) = 0; - if (A1 == 1'b0 & A2 == 1'b0) - (B1 => X) = 0; - ifnone (B1 => X) = 0; + (posedge A2 => (X : A2)) = (0.0,0.0); + if (B1 == 1'b0) + (negedge A2 => (X : A2)) = (0.0,0.0); + ifnone + (posedge A2 => (X : A2)) = (0.0,0.0); + ifnone + (negedge A2 => (X : A2)) = (0.0,0.0); + if (A1 == 1'b1 && A2 == 1'b0) + (posedge B1 => (X : B1)) = (0.0,0.0); + if (A1 == 1'b1 && A2 == 1'b0) + (negedge B1 => (X : B1)) = (0.0,0.0); + if (A1 == 1'b0 && A2 == 1'b1) + (posedge B1 => (X : B1)) = (0.0,0.0); + if (A1 == 1'b0 && A2 == 1'b1) + (negedge B1 => (X : B1)) = (0.0,0.0); + if (A1 == 1'b0 && A2 == 1'b0) + (posedge B1 => (X : B1)) = (0.0,0.0); + if (A1 == 1'b0 && A2 == 1'b0) + (negedge B1 => (X : B1)) = (0.0,0.0); + ifnone + (posedge B1 => (X : B1)) = (0.0,0.0); + ifnone + (negedge B1 => (X : B1)) = (0.0,0.0); endspecify + endmodule `endcelldefine // type: a21oi `timescale 1ns/10ps `celldefine +//***************************************************************** +// technology : SG13G2 +// module name : sg13g2_a21oi_1 +// cell_description : 2-input AND into first input of 2-input NOR. +//***************************************************************** + module sg13g2_a21oi_1 (Y, A1, A2, B1); + output Y; input A1, A2, B1; // Function + wire int_fwire_0, int_fwire_1; and (int_fwire_0, A1, A2); or (int_fwire_1, int_fwire_0, B1); not (Y, int_fwire_1); - + // Timing + specify - (A1 => Y) = 0; - (A2 => Y) = 0; + (posedge A1 => (Y : A1)) = (0.0,0.0); + (negedge A1 => (Y : A1)) = (0.0,0.0); + (posedge A2 => (Y : A2)) = (0.0,0.0); + (negedge A2 => (Y : A2)) = (0.0,0.0); + if ((A1 == 1'b1 && A2 == 1'b0)) + (posedge B1 => (Y : B1)) = (0.0,0.0); if ((A1 == 1'b1 && A2 == 1'b0)) - (B1 => Y) = 0; + (negedge B1 => (Y : B1)) = (0.0,0.0); if ((A1 == 1'b0 && A2 == 1'b1)) - (B1 => Y) = 0; + (posedge B1 => (Y : B1)) = (0.0,0.0); + if ((A1 == 1'b0 && A2 == 1'b1)) + (negedge B1 => (Y : B1)) = (0.0,0.0); + if ((A1 == 1'b0 && A2 == 1'b0)) + (posedge B1 => (Y : B1)) = (0.0,0.0); if ((A1 == 1'b0 && A2 == 1'b0)) - (B1 => Y) = 0; - ifnone (B1 => Y) = 0; + (negedge B1 => (Y : B1)) = (0.0,0.0); + ifnone + (posedge B1 => (Y : B1)) = (0.0,0.0); + ifnone + (negedge B1 => (Y : B1)) = (0.0,0.0); endspecify + endmodule `endcelldefine // type: a21oi `timescale 1ns/10ps `celldefine +//***************************************************************** +// technology : SG13G2 +// module name : sg13g2_a21oi_2 +// cell_description : 2-input AND into first input of 2-input NOR. +//***************************************************************** + module sg13g2_a21oi_2 (Y, A1, A2, B1); + output Y; input A1, A2, B1; // Function + wire int_fwire_0, int_fwire_1; and (int_fwire_0, A1, A2); or (int_fwire_1, int_fwire_0, B1); not (Y, int_fwire_1); - // Timing + // Timing + specify - (A1 => Y) = 0; - (A2 => Y) = 0; + (posedge A1 => (Y : A1)) = (0.0,0.0); + (negedge A1 => (Y : A1)) = (0.0,0.0); + (posedge A2 => (Y : A2)) = (0.0,0.0); + (negedge A2 => (Y : A2)) = (0.0,0.0); + if ((A1 == 1'b1 && A2 == 1'b0)) + (posedge B1 => (Y : B1)) = (0.0,0.0); if ((A1 == 1'b1 && A2 == 1'b0)) - (B1 => Y) = 0; + (negedge B1 => (Y : B1)) = (0.0,0.0); if ((A1 == 1'b0 && A2 == 1'b1)) - (B1 => Y) = 0; + (posedge B1 => (Y : B1)) = (0.0,0.0); + if ((A1 == 1'b0 && A2 == 1'b1)) + (negedge B1 => (Y : B1)) = (0.0,0.0); + if ((A1 == 1'b0 && A2 == 1'b0)) + (posedge B1 => (Y : B1)) = (0.0,0.0); if ((A1 == 1'b0 && A2 == 1'b0)) - (B1 => Y) = 0; - ifnone (B1 => Y) = 0; + (negedge B1 => (Y : B1)) = (0.0,0.0); + ifnone + (posedge B1 => (Y : B1)) = (0.0,0.0); + ifnone + (negedge B1 => (Y : B1)) = (0.0,0.0); endspecify + endmodule `endcelldefine // type: a221oi `timescale 1ns/10ps `celldefine +//***************************************************************** +// technology : SG13G2 +// module name : sg13g2_a221oi_1 +// cell_description : 2-input AND into first two inputs of 3-input NOR. +//***************************************************************** + module sg13g2_a221oi_1 (Y, A1, A2, B1, B2, C1); + output Y; input A1, A2, B1, B2, C1; // Function + wire int_fwire_0, int_fwire_1, int_fwire_2; and (int_fwire_0, B1, B2); and (int_fwire_1, A1, A2); or (int_fwire_2, int_fwire_1, int_fwire_0, C1); not (Y, int_fwire_2); - + // Timing + specify if ((A2 == 1'b1 && B1 == 1'b1 && B2 == 1'b0 && C1 == 1'b0)) - (A1 => Y) = 0; + (posedge A1 => (Y : A1)) = (0.0,0.0); + if ((A2 == 1'b1 && B1 == 1'b1 && B2 == 1'b0 && C1 == 1'b0)) + (negedge A1 => (Y : A1)) = (0.0,0.0); + if ((A2 == 1'b1 && B1 == 1'b0 && B2 == 1'b1 && C1 == 1'b0)) + (posedge A1 => (Y : A1)) = (0.0,0.0); if ((A2 == 1'b1 && B1 == 1'b0 && B2 == 1'b1 && C1 == 1'b0)) - (A1 => Y) = 0; + (negedge A1 => (Y : A1)) = (0.0,0.0); if ((A2 == 1'b1 && B1 == 1'b0 && B2 == 1'b0 && C1 == 1'b0)) - (A1 => Y) = 0; - ifnone (A1 => Y) = 0; + (posedge A1 => (Y : A1)) = (0.0,0.0); + if ((A2 == 1'b1 && B1 == 1'b0 && B2 == 1'b0 && C1 == 1'b0)) + (negedge A1 => (Y : A1)) = (0.0,0.0); + ifnone + (posedge A1 => (Y : A1)) = (0.0,0.0); + ifnone + (negedge A1 => (Y : A1)) = (0.0,0.0); + if ((A1 == 1'b1 && B1 == 1'b1 && B2 == 1'b0 && C1 == 1'b0)) + (posedge A2 => (Y : A2)) = (0.0,0.0); if ((A1 == 1'b1 && B1 == 1'b1 && B2 == 1'b0 && C1 == 1'b0)) - (A2 => Y) = 0; + (negedge A2 => (Y : A2)) = (0.0,0.0); if ((A1 == 1'b1 && B1 == 1'b0 && B2 == 1'b1 && C1 == 1'b0)) - (A2 => Y) = 0; + (posedge A2 => (Y : A2)) = (0.0,0.0); + if ((A1 == 1'b1 && B1 == 1'b0 && B2 == 1'b1 && C1 == 1'b0)) + (negedge A2 => (Y : A2)) = (0.0,0.0); + if ((A1 == 1'b1 && B1 == 1'b0 && B2 == 1'b0 && C1 == 1'b0)) + (posedge A2 => (Y : A2)) = (0.0,0.0); if ((A1 == 1'b1 && B1 == 1'b0 && B2 == 1'b0 && C1 == 1'b0)) - (A2 => Y) = 0; - ifnone (A2 => Y) = 0; + (negedge A2 => (Y : A2)) = (0.0,0.0); + ifnone + (posedge A2 => (Y : A2)) = (0.0,0.0); + ifnone + (negedge A2 => (Y : A2)) = (0.0,0.0); if ((A1 == 1'b1 && A2 == 1'b0 && B2 == 1'b1 && C1 == 1'b0)) - (B1 => Y) = 0; + (posedge B1 => (Y : B1)) = (0.0,0.0); + if ((A1 == 1'b1 && A2 == 1'b0 && B2 == 1'b1 && C1 == 1'b0)) + (negedge B1 => (Y : B1)) = (0.0,0.0); + if ((A1 == 1'b0 && A2 == 1'b1 && B2 == 1'b1 && C1 == 1'b0)) + (posedge B1 => (Y : B1)) = (0.0,0.0); if ((A1 == 1'b0 && A2 == 1'b1 && B2 == 1'b1 && C1 == 1'b0)) - (B1 => Y) = 0; + (negedge B1 => (Y : B1)) = (0.0,0.0); if ((A1 == 1'b0 && A2 == 1'b0 && B2 == 1'b1 && C1 == 1'b0)) - (B1 => Y) = 0; - ifnone (B1 => Y) = 0; + (posedge B1 => (Y : B1)) = (0.0,0.0); + if ((A1 == 1'b0 && A2 == 1'b0 && B2 == 1'b1 && C1 == 1'b0)) + (negedge B1 => (Y : B1)) = (0.0,0.0); + ifnone + (posedge B1 => (Y : B1)) = (0.0,0.0); + ifnone + (negedge B1 => (Y : B1)) = (0.0,0.0); + if ((A1 == 1'b1 && A2 == 1'b0 && B1 == 1'b1 && C1 == 1'b0)) + (posedge B2 => (Y : B2)) = (0.0,0.0); if ((A1 == 1'b1 && A2 == 1'b0 && B1 == 1'b1 && C1 == 1'b0)) - (B2 => Y) = 0; + (negedge B2 => (Y : B2)) = (0.0,0.0); if ((A1 == 1'b0 && A2 == 1'b1 && B1 == 1'b1 && C1 == 1'b0)) - (B2 => Y) = 0; + (posedge B2 => (Y : B2)) = (0.0,0.0); + if ((A1 == 1'b0 && A2 == 1'b1 && B1 == 1'b1 && C1 == 1'b0)) + (negedge B2 => (Y : B2)) = (0.0,0.0); + if ((A1 == 1'b0 && A2 == 1'b0 && B1 == 1'b1 && C1 == 1'b0)) + (posedge B2 => (Y : B2)) = (0.0,0.0); if ((A1 == 1'b0 && A2 == 1'b0 && B1 == 1'b1 && C1 == 1'b0)) - (B2 => Y) = 0; - ifnone (B2 => Y) = 0; + (negedge B2 => (Y : B2)) = (0.0,0.0); + ifnone + (posedge B2 => (Y : B2)) = (0.0,0.0); + ifnone + (negedge B2 => (Y : B2)) = (0.0,0.0); if ((A1 == 1'b1 && A2 == 1'b0 && B1 == 1'b0 && B2 == 1'b0)) - (C1 => Y) = 0; + (posedge C1 => (Y : C1)) = (0.0,0.0); + if ((A1 == 1'b1 && A2 == 1'b0 && B1 == 1'b0 && B2 == 1'b0)) + (negedge C1 => (Y : C1)) = (0.0,0.0); + if ((A1 == 1'b0 && A2 == 1'b1 && B1 == 1'b0 && B2 == 1'b0)) + (posedge C1 => (Y : C1)) = (0.0,0.0); if ((A1 == 1'b0 && A2 == 1'b1 && B1 == 1'b0 && B2 == 1'b0)) - (C1 => Y) = 0; + (negedge C1 => (Y : C1)) = (0.0,0.0); + if ((A1 == 1'b0 && A2 == 1'b0 && B1 == 1'b1 && B2 == 1'b0)) + (posedge C1 => (Y : C1)) = (0.0,0.0); if ((A1 == 1'b0 && A2 == 1'b0 && B1 == 1'b1 && B2 == 1'b0)) - (C1 => Y) = 0; + (negedge C1 => (Y : C1)) = (0.0,0.0); if ((A1 == 1'b0 && A2 == 1'b0 && B1 == 1'b0 && B2 == 1'b1)) - (C1 => Y) = 0; + (posedge C1 => (Y : C1)) = (0.0,0.0); + if ((A1 == 1'b0 && A2 == 1'b0 && B1 == 1'b0 && B2 == 1'b1)) + (negedge C1 => (Y : C1)) = (0.0,0.0); + if ((A1 == 1'b0 && A2 == 1'b0 && B1 == 1'b0 && B2 == 1'b0)) + (posedge C1 => (Y : C1)) = (0.0,0.0); if ((A1 == 1'b0 && A2 == 1'b0 && B1 == 1'b0 && B2 == 1'b0)) - (C1 => Y) = 0; - ifnone (C1 => Y) = 0; + (negedge C1 => (Y : C1)) = (0.0,0.0); + ifnone + (posedge C1 => (Y : C1)) = (0.0,0.0); + ifnone + (negedge C1 => (Y : C1)) = (0.0,0.0); endspecify + endmodule `endcelldefine // type: a22oi `timescale 1ns/10ps `celldefine +//***************************************************************** +// technology : SG13G2 +// module name : sg13g2_a22oi_1 +// cell_description : 2-input AND into both inputs of 2-input NOR. +//***************************************************************** + module sg13g2_a22oi_1 (Y, A1, A2, B1, B2); + output Y; input A1, A2, B1, B2; // Function + wire int_fwire_0, int_fwire_1, int_fwire_2; and (int_fwire_0, B1, B2); and (int_fwire_1, A1, A2); or (int_fwire_2, int_fwire_1, int_fwire_0); not (Y, int_fwire_2); - + // Timing + specify if (A2 == 1'b1 && B1 == 1'b1) - (A1 => Y) = 0; - ifnone (A1 => Y) = 0; + (posedge A1 => (Y : A1)) = (0.0,0.0); + if (A2 == 1'b1 && B1 == 1'b1) + (negedge A1 => (Y : A1)) = (0.0,0.0); + ifnone + (posedge A1 => (Y : A1)) = (0.0,0.0); + ifnone + (negedge A1 => (Y : A1)) = (0.0,0.0); if (A1 == 1'b1 && B1 == 1'b1) - (A2 => Y) = 0; - ifnone (A2 => Y) = 0; + (posedge A2 => (Y : A2)) = (0.0,0.0); + if (A1 == 1'b1 && B1 == 1'b1) + (negedge A2 => (Y : A2)) = (0.0,0.0); + ifnone + (posedge A2 => (Y : A2)) = (0.0,0.0); + ifnone + (negedge A2 => (Y : A2)) = (0.0,0.0); + if (A1 == 1'b1 && A2 == 1'b0) + (posedge B1 => (Y : B1)) = (0.0,0.0); if (A1 == 1'b1 && A2 == 1'b0) - (B1 => Y) = 0; + (negedge B1 => (Y : B1)) = (0.0,0.0); if (A1 == 1'b0 && A2 == 1'b1) - (B1 => Y) = 0; - ifnone (B1 => Y) = 0; + (posedge B1 => (Y : B1)) = (0.0,0.0); + if (A1 == 1'b0 && A2 == 1'b1) + (negedge B1 => (Y : B1)) = (0.0,0.0); + ifnone + (posedge B1 => (Y : B1)) = (0.0,0.0); + ifnone + (negedge B1 => (Y : B1)) = (0.0,0.0); + if (A1 == 1'b1 && A2 == 1'b0) + (posedge B2 => (Y : B2)) = (0.0,0.0); if (A1 == 1'b1 && A2 == 1'b0) - (B2 => Y) = 0; + (negedge B2 => (Y : B2)) = (0.0,0.0); if (A1 == 1'b0 && A2 == 1'b1) - (B2 => Y) = 0; - ifnone (B2 => Y) = 0; + (posedge B2 => (Y : B2)) = (0.0,0.0); + if (A1 == 1'b0 && A2 == 1'b1) + (negedge B2 => (Y : B2)) = (0.0,0.0); + ifnone + (posedge B2 => (Y : B2)) = (0.0,0.0); + ifnone + (negedge B2 => (Y : B2)) = (0.0,0.0); endspecify + endmodule `endcelldefine -// type: AND2 +// type: and2 `timescale 1ns/10ps `celldefine +//***************************************************************** +// technology : SG13G2 +// module name : sg13g2_and2_1 +// cell_description : 2-input AND +//***************************************************************** + module sg13g2_and2_1 (X, A, B); + output X; input A, B; // Function + and (X, A, B); - // Timing + // Timing + specify - (A => X) = 0; - (B => X) = 0; + (posedge A => (X : A)) = (0.0,0.0); + (negedge A => (X : A)) = (0.0,0.0); + (posedge B => (X : B)) = (0.0,0.0); + (negedge B => (X : B)) = (0.0,0.0); endspecify + endmodule `endcelldefine -// type: AND2 +// type: and2 `timescale 1ns/10ps `celldefine +//***************************************************************** +// technology : SG13G2 +// module name : sg13g2_and2_2 +// cell_description : 2-input AND +//***************************************************************** + module sg13g2_and2_2 (X, A, B); + output X; input A, B; // Function + and (X, A, B); - // Timing + // Timing + specify - (A => X) = 0; - (B => X) = 0; + (posedge A => (X : A)) = (0.0,0.0); + (negedge A => (X : A)) = (0.0,0.0); + (posedge B => (X : B)) = (0.0,0.0); + (negedge B => (X : B)) = (0.0,0.0); endspecify + endmodule `endcelldefine -// type: AND3 +// type: and3 `timescale 1ns/10ps `celldefine +//***************************************************************** +// technology : SG13G2 +// module name : sg13g2_and3_1 +// cell_description : 3-input AND +//***************************************************************** + module sg13g2_and3_1 (X, A, B, C); + output X; input A, B, C; // Function + and (X, A, B, C); - // Timing + // Timing + specify - (A => X) = 0; - (B => X) = 0; - (C => X) = 0; + (posedge A => (X : A)) = (0.0,0.0); + (negedge A => (X : A)) = (0.0,0.0); + (posedge B => (X : B)) = (0.0,0.0); + (negedge B => (X : B)) = (0.0,0.0); + (posedge C => (X : C)) = (0.0,0.0); + (negedge C => (X : C)) = (0.0,0.0); endspecify + endmodule `endcelldefine -// type: AND3 +// type: and3 `timescale 1ns/10ps `celldefine +//***************************************************************** +// technology : SG13G2 +// module name : sg13g2_sighold +// cell_description : 3-input AND +//***************************************************************** + module sg13g2_and3_2 (X, A, B, C); + output X; input A, B, C; // Function + and (X, A, B, C); - // Timing + // Timing + specify - (A => X) = 0; - (B => X) = 0; - (C => X) = 0; + (posedge A => (X : A)) = (0.0,0.0); + (negedge A => (X : A)) = (0.0,0.0); + (posedge B => (X : B)) = (0.0,0.0); + (negedge B => (X : B)) = (0.0,0.0); + (posedge C => (X : C)) = (0.0,0.0); + (negedge C => (X : C)) = (0.0,0.0); endspecify + endmodule `endcelldefine -// type: AND4 +// type: and4 `timescale 1ns/10ps `celldefine +//***************************************************************** +// technology : SG13G2 +// module name : sg13g2_and4_1 +// cell_description : 4-input AND +//***************************************************************** + module sg13g2_and4_1 (X, A, B, C, D); + output X; input A, B, C, D; // Function + and (X, A, B, C, D); // Timing + specify - (A => X) = 0; - (B => X) = 0; - (C => X) = 0; - (D => X) = 0; + (posedge A => (X : A)) = (0.0,0.0); + (negedge A => (X : A)) = (0.0,0.0); + (posedge B => (X : B)) = (0.0,0.0); + (negedge B => (X : B)) = (0.0,0.0); + (posedge C => (X : C)) = (0.0,0.0); + (negedge C => (X : C)) = (0.0,0.0); + (posedge D => (X : D)) = (0.0,0.0); + (negedge D => (X : D)) = (0.0,0.0); endspecify + endmodule `endcelldefine -// type: AND4 +// type: and4 `timescale 1ns/10ps `celldefine +//***************************************************************** +// technology : SG13G2 +// module name : sg13g2_and4_2 +// cell_description : 4-input AND +//***************************************************************** + module sg13g2_and4_2 (X, A, B, C, D); + output X; input A, B, C, D; // Function + and (X, A, B, C, D); - // Timing + // Timing + specify - (A => X) = 0; - (B => X) = 0; - (C => X) = 0; - (D => X) = 0; + (posedge A => (X : A)) = (0.0,0.0); + (negedge A => (X : A)) = (0.0,0.0); + (posedge B => (X : B)) = (0.0,0.0); + (negedge B => (X : B)) = (0.0,0.0); + (posedge C => (X : C)) = (0.0,0.0); + (negedge C => (X : C)) = (0.0,0.0); + (posedge D => (X : D)) = (0.0,0.0); + (negedge D => (X : D)) = (0.0,0.0); endspecify + endmodule `endcelldefine -// type: NP_ant +// type: antennanp `timescale 1ns/10ps `celldefine +//***************************************************************** +// technology : SG13G2 +// module name : sg13g2_antennanp +// cell_description : Antenna effect protection cell (gate charge) at manufacture, P-diode in N-Well, N-diode in substrate +//***************************************************************** + module sg13g2_antennanp (A); input A; - // Timing + + // Timing + specify endspecify + endmodule `endcelldefine -// type: BU +// type: buf `timescale 1ns/10ps `celldefine +//***************************************************************** +// technology : SG13G2 +// module name : sg13g2_buf_1 +// cell_description : Buffer drive strength 1 +//***************************************************************** + module sg13g2_buf_1 (X, A); + output X; input A; // Function + buf (X, A); - // Timing + // Timing + specify - (A => X) = 0; + (posedge A => (X : A)) = (0.0,0.0); + (negedge A => (X : A)) = (0.0,0.0); endspecify + endmodule `endcelldefine -// type: BU +// type: buf `timescale 1ns/10ps `celldefine +//***************************************************************** +// technology : SG13G2 +// module name : sg13g2_buf_16 +// cell_description : Buffer drive strength 16 +//***************************************************************** + module sg13g2_buf_16 (X, A); + output X; input A; // Function + buf (X, A); - // Timing + // Timing + specify - (A => X) = 0; + (posedge A => (X : A)) = (0.0,0.0); + (negedge A => (X : A)) = (0.0,0.0); endspecify + endmodule `endcelldefine -// type: BU +// type: buf `timescale 1ns/10ps `celldefine +//***************************************************************** +// technology : SG13G2 +// module name : sg13g2_buf_2 +// cell_description : Buffer drive strength 2 +//***************************************************************** + module sg13g2_buf_2 (X, A); + output X; input A; // Function + buf (X, A); - // Timing + // Timing + specify - (A => X) = 0; + (posedge A => (X : A)) = (0.0,0.0); + (negedge A => (X : A)) = (0.0,0.0); endspecify + endmodule `endcelldefine -// type: BU +// type: buf `timescale 1ns/10ps `celldefine +//***************************************************************** +// technology : SG13G2 +// module name : sg13g2_buf_4 +// cell_description : Buffer drive strength 4 +//***************************************************************** + module sg13g2_buf_4 (X, A); + output X; input A; // Function + buf (X, A); - // Timing + // Timing + specify - (A => X) = 0; + (posedge A => (X : A)) = (0.0,0.0); + (negedge A => (X : A)) = (0.0,0.0); endspecify + endmodule `endcelldefine -// type: BU +// type: buf `timescale 1ns/10ps `celldefine +//***************************************************************** +// technology : SG13G2 +// module name : sg13g2_buf_8 +// cell_description : Buffer drive strength 8 +//***************************************************************** + module sg13g2_buf_8 (X, A); + output X; input A; // Function + buf (X, A); - // Timing + // Timing + specify - (A => X) = 0; + (posedge A => (X : A)) = (0.0,0.0); + (negedge A => (X : A)) = (0.0,0.0); endspecify + endmodule `endcelldefine -// type: DECAP +// type: decap `timescale 1ns/10ps `celldefine +//***************************************************************** +// technology : SG13G2 +// module name : sg13g2_decap_4 +// cell_description : Decoupling capasitance filler cell +//***************************************************************** + module sg13g2_decap_4 (); - // Timing + + // Timing + specify endspecify + endmodule `endcelldefine -// type: DECAP +// type: decap `timescale 1ns/10ps `celldefine +//***************************************************************** +// technology : SG13G2 +// module name : sg13g2_decap_8 +// cell_description : Decoupling capasitance filler cell +//***************************************************************** + module sg13g2_decap_8 (); - // Timing + + // Timing + specify endspecify + endmodule `endcelldefine -// type: dffrr +// type: dfrbp `timescale 1ns/10ps `celldefine -module sg13g2_dfrbp_1 (Q, Q_N, D, RESET_B, CLK); +//***************************************************************** +// technology : SG13G2 +// module name : sg13g2_dfrbp_1 +// cell_description : Posedge Two-Outputs Q and Q_N D-Flip-Flop with Low-Active Reset +//***************************************************************** + +module sg13g2_dfrbp_1 (Q, Q_N, CLK, D, RESET_B); + output Q, Q_N; - input D, RESET_B, CLK; + input CLK, D, RESET_B; reg notifier; wire delayed_D, delayed_RESET_B, delayed_CLK; @@ -475,34 +834,45 @@ module sg13g2_dfrbp_1 (Q, Q_N, D, RESET_B, CLK); wire xcr_0; not (int_fwire_r, delayed_RESET_B); - ihp_dff_r_err (xcr_0, delayed_CLK, delayed_D, int_fwire_r); + buf (xcr_0, 0); ihp_dff_r (int_fwire_IQ, notifier, delayed_CLK, delayed_D, int_fwire_r, xcr_0); buf (Q, int_fwire_IQ); not (int_fwire_IQN, int_fwire_IQ); buf (Q_N, int_fwire_IQN); - // Timing + // Timing + specify - (negedge RESET_B => (Q+:1'b0)) = 0; - (posedge CLK => (Q+:D)) = 0; - (negedge RESET_B => (Q_N-:1'b0)) = 0; - (posedge CLK => (Q_N-:D)) = 0; - $setuphold (posedge CLK, posedge D, 0, 0, notifier,,, delayed_CLK, delayed_D); - $setuphold (posedge CLK, negedge D, 0, 0, notifier,,, delayed_CLK, delayed_D); - $recrem (posedge RESET_B, posedge CLK, 0, 0, notifier,,, delayed_RESET_B, delayed_CLK); - $width (negedge RESET_B, 0, 0, notifier); - $width (posedge CLK, 0, 0, notifier); - $width (negedge CLK, 0, 0, notifier); + (negedge RESET_B => (Q :1'b0)) = (0.0,0.0); + (posedge CLK => (Q : D)) = (0.0,0.0); + (negedge CLK => (Q : D)) = (0.0,0.0); + (negedge RESET_B => (Q_N :1'b0)) = (0.0,0.0); + (posedge CLK => (Q_N : D)) = (0.0,0.0); + (negedge CLK => (Q_N : D)) = (0.0,0.0); + $setuphold (posedge CLK, posedge D, 0.0, 0.0, notifier,,, delayed_CLK, delayed_D); + $setuphold (posedge CLK, negedge D, 0.0, 0.0, notifier,,, delayed_CLK, delayed_D); + $recrem (posedge RESET_B, posedge CLK, 0.0, 0.0, notifier,,, delayed_RESET_B, delayed_CLK); + $width (negedge RESET_B, 0.0, 0, notifier); + $width (posedge CLK, 0.0, 0, notifier); + $width (negedge CLK, 0.0, 0, notifier); endspecify + endmodule `endcelldefine -// type: dffrr +// type: dfrbp `timescale 1ns/10ps `celldefine -module sg13g2_dfrbp_2 (Q, Q_N, D, RESET_B, CLK); +//***************************************************************** +// technology : SG13G2 +// module name : sg13g2_dfrbp_2 +// cell_description : Posedge Two-Outputs Q and Q_N D-Flip-Flop with Low-Active Reset +//***************************************************************** + +module sg13g2_dfrbp_2 (Q, Q_N, CLK, D, RESET_B); + output Q, Q_N; - input D, RESET_B, CLK; + input CLK, D, RESET_B; reg notifier; wire delayed_D, delayed_RESET_B, delayed_CLK; @@ -511,34 +881,45 @@ module sg13g2_dfrbp_2 (Q, Q_N, D, RESET_B, CLK); wire xcr_0; not (int_fwire_r, delayed_RESET_B); - ihp_dff_r_err (xcr_0, delayed_CLK, delayed_D, int_fwire_r); + buf (xcr_0, 0); ihp_dff_r (int_fwire_IQ, notifier, delayed_CLK, delayed_D, int_fwire_r, xcr_0); buf (Q, int_fwire_IQ); not (int_fwire_IQN, int_fwire_IQ); buf (Q_N, int_fwire_IQN); - // Timing + // Timing + specify - (negedge RESET_B => (Q+:1'b0)) = 0; - (posedge CLK => (Q+:D)) = 0; - (negedge RESET_B => (Q_N-:1'b0)) = 0; - (posedge CLK => (Q_N-:D)) = 0; - $setuphold (posedge CLK, posedge D, 0, 0, notifier,,, delayed_CLK, delayed_D); - $setuphold (posedge CLK, negedge D, 0, 0, notifier,,, delayed_CLK, delayed_D); - $recrem (posedge RESET_B, posedge CLK, 0, 0, notifier,,, delayed_RESET_B, delayed_CLK); - $width (negedge RESET_B, 0, 0, notifier); - $width (posedge CLK, 0, 0, notifier); - $width (negedge CLK, 0, 0, notifier); + (negedge RESET_B => (Q :1'b0)) = (0.0,0.0); + (posedge CLK => (Q : D)) = (0.0,0.0); + (negedge CLK => (Q : D)) = (0.0,0.0); + (negedge RESET_B => (Q_N :1'b0)) = (0.0,0.0); + (posedge CLK => (Q_N : D)) = (0.0,0.0); + (negedge CLK => (Q_N : D)) = (0.0,0.0); + $setuphold (posedge CLK, posedge D, 0.0, 0.0, notifier,,, delayed_CLK, delayed_D); + $setuphold (posedge CLK, negedge D, 0.0, 0.0, notifier,,, delayed_CLK, delayed_D); + $recrem (posedge RESET_B, posedge CLK, 0.0, 0.0, notifier,,, delayed_RESET_B, delayed_CLK); + $width (negedge RESET_B, 0.0, 0, notifier); + $width (posedge CLK, 0.0, 0, notifier); + $width (negedge CLK, 0.0, 0, notifier); endspecify + endmodule `endcelldefine // type: dfrbpq `timescale 1ns/10ps `celldefine -module sg13g2_dfrbpq_1 (Q, D, RESET_B, CLK); +//***************************************************************** +// technology : SG13G2 +// module name : sg13g2_dfrbpq_1 +// cell_description : Posedge Single-Output Q D-Flip-Flop with Low-Active Reset +//***************************************************************** + +module sg13g2_dfrbpq_1 (Q, CLK, D, RESET_B); + output Q; - input D, RESET_B, CLK; + input CLK, D, RESET_B; reg notifier; wire delayed_D, delayed_RESET_B, delayed_CLK; @@ -546,30 +927,40 @@ module sg13g2_dfrbpq_1 (Q, D, RESET_B, CLK); wire int_fwire_IQ, int_fwire_r, xcr_0; not (int_fwire_r, delayed_RESET_B); - ihp_dff_r_err (xcr_0, delayed_CLK, delayed_D, int_fwire_r); + buf (xcr_0, 0); ihp_dff_r (int_fwire_IQ, notifier, delayed_CLK, delayed_D, int_fwire_r, xcr_0); buf (Q, int_fwire_IQ); - // Timing + // Timing + specify - (negedge RESET_B => (Q+:1'b0)) = 0; - (posedge CLK => (Q+:D)) = 0; - $setuphold (posedge CLK, posedge D, 0, 0, notifier,,, delayed_CLK, delayed_D); - $setuphold (posedge CLK, negedge D, 0, 0, notifier,,, delayed_CLK, delayed_D); - $recrem (posedge RESET_B, posedge CLK, 0, 0, notifier,,, delayed_RESET_B, delayed_CLK); - $width (negedge RESET_B, 0, 0, notifier); - $width (posedge CLK, 0, 0, notifier); - $width (negedge CLK, 0, 0, notifier); + (negedge RESET_B => (Q :1'b0)) = (0.0,0.0); + (posedge CLK => (Q : D)) = (0.0,0.0); + (negedge CLK => (Q : D)) = (0.0,0.0); + $setuphold (posedge CLK, posedge D, 0.0, 0.0, notifier,,, delayed_CLK, delayed_D); + $setuphold (posedge CLK, negedge D, 0.0, 0.0, notifier,,, delayed_CLK, delayed_D); + $recrem (posedge RESET_B, posedge CLK, 0.0, 0.0, notifier,,, delayed_RESET_B, delayed_CLK); + $width (negedge RESET_B, 0.0, 0, notifier); + $width (posedge CLK, 0.0, 0, notifier); + $width (negedge CLK, 0.0, 0, notifier); endspecify + endmodule `endcelldefine // type: dfrbpq `timescale 1ns/10ps `celldefine -module sg13g2_dfrbpq_2 (Q, D, RESET_B, CLK); +//***************************************************************** +// technology : SG13G2 +// module name : sg13g2_dfrbpq_2 +// cell_description : Posedge Single-Output Q D-Flip-Flop with Low-Active Reset +//***************************************************************** + +module sg13g2_dfrbpq_2 (Q, CLK, D, RESET_B); + output Q; - input D, RESET_B, CLK; + input CLK, D, RESET_B; reg notifier; wire delayed_D, delayed_RESET_B, delayed_CLK; @@ -577,60 +968,83 @@ module sg13g2_dfrbpq_2 (Q, D, RESET_B, CLK); wire int_fwire_IQ, int_fwire_r, xcr_0; not (int_fwire_r, delayed_RESET_B); - ihp_dff_r_err (xcr_0, delayed_CLK, delayed_D, int_fwire_r); + buf (xcr_0, 0); ihp_dff_r (int_fwire_IQ, notifier, delayed_CLK, delayed_D, int_fwire_r, xcr_0); buf (Q, int_fwire_IQ); - // Timing + // Timing + specify - (negedge RESET_B => (Q+:1'b0)) = 0; - (posedge CLK => (Q+:D)) = 0; - $setuphold (posedge CLK, posedge D, 0, 0, notifier,,, delayed_CLK, delayed_D); - $setuphold (posedge CLK, negedge D, 0, 0, notifier,,, delayed_CLK, delayed_D); - $recrem (posedge RESET_B, posedge CLK, 0, 0, notifier,,, delayed_RESET_B, delayed_CLK); - $width (negedge RESET_B, 0, 0, notifier); - $width (posedge CLK, 0, 0, notifier); - $width (negedge CLK, 0, 0, notifier); + (negedge RESET_B => (Q :1'b0)) = (0.0,0.0); + (posedge CLK => (Q : D)) = (0.0,0.0); + (negedge CLK => (Q : D)) = (0.0,0.0); + $setuphold (posedge CLK, posedge D, 0.0, 0.0, notifier,,, delayed_CLK, delayed_D); + $setuphold (posedge CLK, negedge D, 0.0, 0.0, notifier,,, delayed_CLK, delayed_D); + $recrem (posedge RESET_B, posedge CLK, 0.0, 0.0, notifier,,, delayed_RESET_B, delayed_CLK); + $width (negedge RESET_B, 0.0, 0, notifier); + $width (posedge CLK, 0.0, 0, notifier); + $width (negedge CLK, 0.0, 0, notifier); endspecify + endmodule `endcelldefine -// type: DLHQ +// type: dlhq `timescale 1ns/10ps `celldefine +//***************************************************************** +// technology : SG13G2 +// module name : sg13g2_dlhq_1 +// cell_description : High-Active GATE Single-Output Q D-latch +//***************************************************************** + module sg13g2_dlhq_1 (Q, D, GATE); + output Q; input D, GATE; reg notifier; wire delayed_D, delayed_GATE; // Function + wire int_fwire_IQ; ihp_latch (int_fwire_IQ, notifier, delayed_GATE, delayed_D); buf (Q, int_fwire_IQ); - // Timing + // Timing + specify - (D => Q) = 0; - (posedge GATE => (Q+:D)) = 0; - $setuphold (negedge GATE, posedge D, 0, 0, notifier,,, delayed_GATE, delayed_D); - $setuphold (negedge GATE, negedge D, 0, 0, notifier,,, delayed_GATE, delayed_D); - $width (posedge GATE, 0, 0, notifier); + (posedge D => (Q : D)) = (0.0,0.0); + (negedge D => (Q : D)) = (0.0,0.0); + (posedge GATE => (Q : D)) = (0.0,0.0); + (negedge GATE => (Q : D)) = (0.0,0.0); + $setuphold (negedge GATE, posedge D, 0.0, 0.0, notifier,,, delayed_GATE, delayed_D); + $setuphold (negedge GATE, negedge D, 0.0, 0.0, notifier,,, delayed_GATE, delayed_D); + $width (posedge GATE, 0.0, 0, notifier); endspecify + endmodule `endcelldefine -// type: DLHR +// type: dlhr `timescale 1ns/10ps `celldefine -module sg13g2_dlhr_1 (Q, Q_N, D, RESET_B, GATE); +//***************************************************************** +// technology : SG13G2 +// module name : sg13g2_dlhr_1 +// cell_description : High-Active GATE Two-Outputs Q Q_N D-latch with Low-Active Reset +//***************************************************************** + +module sg13g2_dlhr_1 (Q, Q_N, D, GATE, RESET_B); + output Q, Q_N; - input D, RESET_B, GATE; + input D, GATE, RESET_B; reg notifier; wire delayed_D, delayed_RESET_B, delayed_GATE; // Function + wire int_fwire_IQ, int_fwire_IQN, int_fwire_r; not (int_fwire_r, delayed_RESET_B); @@ -639,63 +1053,91 @@ module sg13g2_dlhr_1 (Q, Q_N, D, RESET_B, GATE); not (int_fwire_IQN, int_fwire_IQ); buf (Q_N, int_fwire_IQN); - // Timing + // Timing + specify - (D => Q) = 0; - (negedge RESET_B => (Q+:1'b0)) = 0; - (posedge GATE => (Q+:D)) = 0; - (D => Q_N) = 0; - (negedge RESET_B => (Q_N-:1'b0)) = 0; - (posedge GATE => (Q_N-:D)) = 0; - $setuphold (negedge GATE, posedge D, 0, 0, notifier,,, delayed_GATE, delayed_D); - $setuphold (negedge GATE, negedge D, 0, 0, notifier,,, delayed_GATE, delayed_D); - $recrem (posedge RESET_B, negedge GATE, 0, 0, notifier,,, delayed_RESET_B, delayed_GATE); - $width (negedge RESET_B, 0, 0, notifier); - $width (posedge GATE, 0, 0, notifier); + (posedge D => (Q : D)) = (0.0,0.0); + (negedge D => (Q : D)) = (0.0,0.0); + (negedge RESET_B => (Q :1'b0)) = (0.0,0.0); + (posedge GATE => (Q : D)) = (0.0,0.0); + (negedge GATE => (Q : D)) = (0.0,0.0); + (posedge D => (Q_N : D)) = (0.0,0.0); + (negedge D => (Q_N : D)) = (0.0,0.0); + (negedge RESET_B => (Q_N :1'b0)) = (0.0,0.0); + (posedge GATE => (Q_N : D)) = (0.0,0.0); + (negedge GATE => (Q_N : D)) = (0.0,0.0); + $setuphold (negedge GATE, posedge D, 0.0, 0.0, notifier,,, delayed_GATE, delayed_D); + $setuphold (negedge GATE, negedge D, 0.0, 0.0, notifier,,, delayed_GATE, delayed_D); + $recrem (posedge RESET_B, negedge GATE, 0.0, 0.0, notifier,,, delayed_RESET_B, delayed_GATE); + $width (negedge RESET_B, 0.0, 0, notifier); + $width (posedge GATE, 0.0, 0, notifier); endspecify + endmodule `endcelldefine -// type: DLHRQ + +// type: dlhrq `timescale 1ns/10ps `celldefine -module sg13g2_dlhrq_1 (Q, D, RESET_B, GATE); +//***************************************************************** +// technology : SG13G2 +// module name : sg13g2_dlhrq_1 +// cell_description : High-Active Gate Single-Output Q D-latch with Low-Active Reset +//***************************************************************** + +module sg13g2_dlhrq_1 (Q, D, GATE, RESET_B); + output Q; - input D, RESET_B, GATE; + input D, GATE, RESET_B; reg notifier; wire delayed_D, delayed_RESET_B, delayed_GATE; // Function + wire int_fwire_IQ, int_fwire_r; not (int_fwire_r, delayed_RESET_B); ihp_latch_r (int_fwire_IQ, notifier, delayed_GATE, delayed_D, int_fwire_r); buf (Q, int_fwire_IQ); - // Timing + // Timing + specify - (D => Q) = 0; - (negedge RESET_B => (Q+:1'b0)) = 0; - (posedge GATE => (Q+:D)) = 0; - $setuphold (negedge GATE, posedge D, 0, 0, notifier,,, delayed_GATE, delayed_D); - $setuphold (negedge GATE, negedge D, 0, 0, notifier,,, delayed_GATE, delayed_D); - $recrem (posedge RESET_B, negedge GATE, 0, 0, notifier,,, delayed_RESET_B, delayed_GATE); - $width (negedge RESET_B, 0, 0, notifier); - $width (posedge GATE, 0, 0, notifier); + (posedge D => (Q : D)) = (0.0,0.0); + (negedge D => (Q : D)) = (0.0,0.0); + (negedge RESET_B => (Q :1'b0)) = (0.0,0.0); + (posedge GATE => (Q : D)) = (0.0,0.0); + (negedge GATE => (Q : D)) = (0.0,0.0); + $setuphold (negedge GATE, posedge D, 0.0, 0.0, notifier,,, delayed_GATE, delayed_D); + $setuphold (negedge GATE, negedge D, 0.0, 0.0, notifier,,, delayed_GATE, delayed_D); + $recrem (posedge RESET_B, negedge GATE, 0.0, 0.0, notifier,,, delayed_RESET_B, delayed_GATE); + $width (negedge RESET_B, 0.0, 0, notifier); + $width (posedge GATE, 0.0, 0, notifier); endspecify + endmodule `endcelldefine -// type: DLLR + +// type: dllr `timescale 1ns/10ps `celldefine -module sg13g2_dllr_1 (Q, Q_N, D, RESET_B, GATE_N); +//***************************************************************** +// technology : SG13G2 +// module name : sg13g2_dllr_1 +// cell_description : Low-Active GATE_N Two-Outputs Q Q_N D-latch with Low-Active Reset +//***************************************************************** + +module sg13g2_dllr_1 (Q, Q_N, D, GATE_N, RESET_B); + output Q, Q_N; - input D, RESET_B, GATE_N; + input D, GATE_N, RESET_B; reg notifier; wire delayed_D, delayed_RESET_B, delayed_GATE_N; // Function + wire int_fwire_clk, int_fwire_IQ, int_fwire_IQN; wire int_fwire_r; @@ -706,33 +1148,48 @@ module sg13g2_dllr_1 (Q, Q_N, D, RESET_B, GATE_N); not (int_fwire_IQN, int_fwire_IQ); buf (Q_N, int_fwire_IQN); - // Timing + // Timing + specify - (D => Q) = 0; - (negedge RESET_B => (Q+:1'b0)) = 0; - (negedge GATE_N => (Q+:D)) = 0; - (D => Q_N) = 0; - (negedge RESET_B => (Q_N-:1'b0)) = 0; - (negedge GATE_N => (Q_N-:D)) = 0; - $setuphold (posedge GATE_N, posedge D, 0, 0, notifier,,, delayed_GATE_N, delayed_D); - $setuphold (posedge GATE_N, negedge D, 0, 0, notifier,,, delayed_GATE_N, delayed_D); - $recrem (posedge RESET_B, posedge GATE_N, 0, 0, notifier,,, delayed_RESET_B, delayed_GATE_N); - $width (negedge RESET_B, 0, 0, notifier); - $width (negedge GATE_N, 0, 0, notifier); + (posedge D => (Q : D)) = (0.0,0.0); + (negedge D => (Q : D)) = (0.0,0.0); + (negedge RESET_B => (Q :1'b0)) = (0.0,0.0); + (negedge GATE_N => (Q : D)) = (0.0,0.0); + (posedge GATE_N => (Q : D)) = (0.0,0.0); + (posedge D => (Q_N : D)) = (0.0,0.0); + (negedge D => (Q_N : D)) = (0.0,0.0); + (negedge RESET_B => (Q_N :1'b0)) = (0.0,0.0); + (negedge GATE_N => (Q_N : D)) = (0.0,0.0); + (posedge GATE_N => (Q_N : D)) = (0.0,0.0); + $setuphold (posedge GATE_N, posedge D, 0.0, 0.0, notifier,,, delayed_GATE_N, delayed_D); + $setuphold (posedge GATE_N, negedge D, 0.0, 0.0, notifier,,, delayed_GATE_N, delayed_D); + $recrem (posedge RESET_B, posedge GATE_N, 0.0, 0.0, notifier,,, delayed_RESET_B, delayed_GATE_N); + $width (negedge RESET_B, 0.0, 0, notifier); + $width (negedge GATE_N, 0.0, 0, notifier); endspecify + endmodule `endcelldefine -// type: DLLRQ + +// type: dllrq `timescale 1ns/10ps `celldefine -module sg13g2_dllrq_1 (Q, D, RESET_B, GATE_N); +//***************************************************************** +// technology : SG13G2 +// module name : sg13g2_dllrq_1 +// cell_description : Low-Active GATE_N Single-Output Q D-latch with Low-Active Reset +//***************************************************************** + +module sg13g2_dllrq_1 (Q, D, GATE_N, RESET_B); + output Q; - input D, RESET_B, GATE_N; + input D, GATE_N, RESET_B; reg notifier; wire delayed_D, delayed_RESET_B, delayed_GATE_N; // Function + wire int_fwire_clk, int_fwire_IQ, int_fwire_r; not (int_fwire_clk, delayed_GATE_N); @@ -740,894 +1197,1514 @@ module sg13g2_dllrq_1 (Q, D, RESET_B, GATE_N); ihp_latch_r (int_fwire_IQ, notifier, int_fwire_clk, delayed_D, int_fwire_r); buf (Q, int_fwire_IQ); - // Timing + // Timing + specify - (D => Q) = 0; - (negedge RESET_B => (Q+:1'b0)) = 0; - (posedge RESET_B => (Q+:1'b1)) = 0; - (negedge GATE_N => (Q+:D)) = 0; - $setuphold (posedge GATE_N, posedge D, 0, 0, notifier,,, delayed_GATE_N, delayed_D); - $setuphold (posedge GATE_N, negedge D, 0, 0, notifier,,, delayed_GATE_N, delayed_D); - $recrem (posedge RESET_B, posedge GATE_N, 0, 0, notifier,,, delayed_RESET_B, delayed_GATE_N); - $width (negedge RESET_B, 0, 0, notifier); - $width (negedge GATE_N, 0, 0, notifier); + (posedge D => (Q : D)) = (0.0,0.0); + (negedge D => (Q : D)) = (0.0,0.0); + (negedge RESET_B => (Q :1'b0)) = (0.0,0.0); + (posedge RESET_B => (Q :1'b1)) = (0.0,0.0); + (negedge GATE_N => (Q : D)) = (0.0,0.0); + (posedge GATE_N => (Q : D)) = (0.0,0.0); + $setuphold (posedge GATE_N, posedge D, 0.0, 0.0, notifier,,, delayed_GATE_N, delayed_D); + $setuphold (posedge GATE_N, negedge D, 0.0, 0.0, notifier,,, delayed_GATE_N, delayed_D); + $recrem (posedge RESET_B, posedge GATE_N, 0.0, 0.0, notifier,,, delayed_RESET_B, delayed_GATE_N); + $width (negedge RESET_B, 0.0, 0, notifier); + $width (negedge GATE_N, 0.0, 0, notifier); endspecify + endmodule `endcelldefine -// type: DLY1 + +// type: dlygate4sd1 `timescale 1ns/10ps `celldefine +//***************************************************************** +// technology : SG13G2 +// module name : sg13g2_dlygate4sd1_1 +// cell_description : Delay Cell, typical 0.4 ns +//***************************************************************** + module sg13g2_dlygate4sd1_1 (X, A); + output X; input A; // Function + buf (X, A); - // Timing + // Timing + specify - (A => X) = 0; + (posedge A => (X : A)) = (0.0,0.0); + (negedge A => (X : A)) = (0.0,0.0); endspecify + endmodule `endcelldefine -// type: DLY2 + +// type: dlygate4sd2 `timescale 1ns/10ps `celldefine +//***************************************************************** +// technology : SG13G2 +// module name : sg13g2_dlygate4sd2_1 +// cell_description : Delay Cell, typical 0.45 ns +//***************************************************************** + module sg13g2_dlygate4sd2_1 (X, A); + output X; input A; // Function + buf (X, A); - // Timing + // Timing + specify - (A => X) = 0; + (posedge A => (X : A)) = (0.0,0.0); + (negedge A => (X : A)) = (0.0,0.0); endspecify + endmodule `endcelldefine -// type: DLY4 + +// type: dlygate4sd3 `timescale 1ns/10ps `celldefine +//***************************************************************** +// technology : SG13G2 +// module name : sg13g2_dlygate4sd3_1 +// cell_description : Delay Cell, typical 0.7 ns +//***************************************************************** + module sg13g2_dlygate4sd3_1 (X, A); + output X; input A; // Function + buf (X, A); - // Timing + // Timing + specify - (A => X) = 0; + (posedge A => (X : A)) = (0.0,0.0); + (negedge A => (X : A)) = (0.0,0.0); endspecify + endmodule `endcelldefine -// type: BTL + +// type: ebufn `timescale 1ns/10ps `celldefine +//***************************************************************** +// technology : SG13G2 +// module name : sg13g2_ebufn_2 +// cell_description : Tristate Buffer with Low-Active Enable TE_B +//***************************************************************** + module sg13g2_ebufn_2 (Z, A, TE_B); + output Z; input A, TE_B; // Function + bufif0 (Z, A, TE_B); - // Timing + // Timing + specify - (A => Z) = 0; - (TE_B => Z) = 0; + (posedge A => (Z : A)) = (0.0,0.0); + (negedge A => (Z : A)) = (0.0,0.0); + (negedge TE_B => (Z:TE_B)) = (0.0,0.0); + (posedge TE_B => (Z:TE_B)) = (0.0,0.0); endspecify + endmodule `endcelldefine -// type: BTL + +// type: ebufn `timescale 1ns/10ps `celldefine +//***************************************************************** +// technology : SG13G2 +// module name : sg13g2_ebufn_4 +// cell_description : Tristate Buffer with Low-Active Enable TE_B +//***************************************************************** + module sg13g2_ebufn_4 (Z, A, TE_B); + output Z; input A, TE_B; // Function + bufif0 (Z, A, TE_B); - // Timing + // Timing + specify - (A => Z) = 0; - (TE_B => Z) = 0; + (posedge A => (Z : A)) = (0.0,0.0); + (negedge A => (Z : A)) = (0.0,0.0); + (negedge TE_B => (Z:TE_B)) = (0.0,0.0); + (posedge TE_B => (Z:TE_B)) = (0.0,0.0); endspecify + endmodule `endcelldefine -// type: BTL + +// type: ebufn `timescale 1ns/10ps `celldefine +//***************************************************************** +// technology : SG13G2 +// module name : sg13g2_ebufn_8 +// cell_description : Tristate Buffer with Low-Active Enable TE_B +//***************************************************************** + module sg13g2_ebufn_8 (Z, A, TE_B); + output Z; input A, TE_B; // Function + bufif0 (Z, A, TE_B); - // Timing + // Timing + specify - (A => Z) = 0; - (TE_B => Z) = 0; + (posedge A => (Z : A)) = (0.0,0.0); + (negedge A => (Z : A)) = (0.0,0.0); + (negedge TE_B => (Z:TE_B)) = (0.0,0.0); + (posedge TE_B => (Z:TE_B)) = (0.0,0.0); endspecify + endmodule `endcelldefine -// type: einvin + +// type: einvn `timescale 1ns/10ps `celldefine +//***************************************************************** +// technology : SG13G2 +// module name : sg13g2_einvn_2 +// cell_description : Tristate Inverter with Low-Active Enable TE_B +//***************************************************************** + module sg13g2_einvn_2 (Z, A, TE_B); + output Z; input A, TE_B; // Function + notif0 (Z, A, TE_B); - // Timing + // Timing + specify - (A => Z) = 0; - (posedge TE_B => (Z:!A)) = 0; - (negedge TE_B => (Z:!A)) = 0; + (posedge A => (Z : A)) = (0.0,0.0); + (negedge A => (Z : A)) = (0.0,0.0); + (posedge TE_B => (Z : TE_B)) = (0.0,0.0); + (negedge TE_B => (Z : TE_B)) = (0.0,0.0); endspecify + endmodule `endcelldefine -// type: einvin + +// type: einvn `timescale 1ns/10ps `celldefine +//***************************************************************** +// technology : SG13G2 +// module name : sg13g2_einvn_4 +// cell_description : Tristate Inverter with Low-Active Enable TE_B +//***************************************************************** + module sg13g2_einvn_4 (Z, A, TE_B); + output Z; input A, TE_B; // Function + notif0 (Z, A, TE_B); - // Timing + // Timing + specify - (A => Z) = 0; - (posedge TE_B => (Z:!A)) = 0; - (negedge TE_B => (Z:!A)) = 0; + (posedge A => (Z : A)) = (0.0,0.0); + (negedge A => (Z : A)) = (0.0,0.0); + (posedge TE_B => (Z : TE_B)) = (0.0,0.0); + (negedge TE_B => (Z : TE_B)) = (0.0,0.0); endspecify + endmodule `endcelldefine -// type: ITL + +// type: einvn `timescale 1ns/10ps `celldefine +//***************************************************************** +// technology : SG13G2 +// module name : sg13g2_einvn_8 +// cell_description : Tristate Inverter with Low-Active Enable TE_B +//***************************************************************** + module sg13g2_einvn_8 (Z, A, TE_B); + output Z; input A, TE_B; // Function + notif0 (Z, A, TE_B); - // Timing + // Timing + specify - (A => Z) = 0; - (posedge TE_B => (Z:!A)) = 0; - (negedge TE_B => (Z:!A)) = 0; + (posedge A => (Z : A)) = (0.0,0.0); + (negedge A => (Z : A)) = (0.0,0.0); + (posedge TE_B => (Z : TE_B)) = (0.0,0.0); + (negedge TE_B => (Z : TE_B)) = (0.0,0.0); endspecify + endmodule `endcelldefine + // type: fill `timescale 1ns/10ps `celldefine +//***************************************************************** +// technology : SG13G2 +// module name : sg13g2_fill_1 +// cell_description : Filler 1 Track Width +//***************************************************************** + module sg13g2_fill_1 (); - // Timing + + // Timing + specify endspecify + endmodule `endcelldefine + // type: fill `timescale 1ns/10ps `celldefine +//***************************************************************** +// technology : SG13G2 +// module name : sg13g2_fill_2 +// cell_description : Filler 2 Tracks Width +//***************************************************************** + module sg13g2_fill_2 (); - // Timing + + // Timing + specify endspecify + endmodule `endcelldefine + // type: fill `timescale 1ns/10ps `celldefine +//***************************************************************** +// technology : SG13G2 +// module name : sg13g2_fill_4 +// cell_description : Filler 4 Tracks Width +//***************************************************************** + module sg13g2_fill_4 (); - // Timing + + // Timing + specify endspecify + endmodule `endcelldefine + // type: fill `timescale 1ns/10ps `celldefine +//***************************************************************** +// technology : SG13G2 +// module name : sg13g2_fill_8 +// cell_description : Filler 8 Tracks Width +//***************************************************************** + module sg13g2_fill_8 (); - // Timing + + // Timing + specify endspecify + endmodule `endcelldefine -// type: IN + +// type: inv `timescale 1ns/10ps `celldefine +//***************************************************************** +// technology : SG13G2 +// module name : sg13g2_inv_1 +// cell_description : Inverter +//***************************************************************** + module sg13g2_inv_1 (Y, A); + output Y; input A; // Function + not (Y, A); - // Timing + // Timing + specify - (A => Y) = 0; + (posedge A => (Y : A)) = (0.0,0.0); + (negedge A => (Y : A)) = (0.0,0.0); endspecify + endmodule `endcelldefine -// type: IN + +// type: inv `timescale 1ns/10ps `celldefine +//***************************************************************** +// technology : SG13G2 +// module name : sg13g2_inv_16 +// cell_description : Inverter +//***************************************************************** + module sg13g2_inv_16 (Y, A); + output Y; input A; // Function + not (Y, A); - // Timing + // Timing + specify - (A => Y) = 0; + (posedge A => (Y : A)) = (0.0,0.0); + (negedge A => (Y : A)) = (0.0,0.0); endspecify + endmodule `endcelldefine -// type: IN + +// type: inv `timescale 1ns/10ps `celldefine +//***************************************************************** +// technology : SG13G2 +// module name : sg13g2_inv_2 +// cell_description : Inverter +//***************************************************************** + module sg13g2_inv_2 (Y, A); + output Y; input A; // Function + not (Y, A); - // Timing + // Timing + specify - (A => Y) = 0; + (posedge A => (Y : A)) = (0.0,0.0); + (negedge A => (Y : A)) = (0.0,0.0); endspecify + endmodule `endcelldefine -// type: IN + +// type: inv `timescale 1ns/10ps `celldefine +//***************************************************************** +// technology : SG13G2 +// module name : sg13g2_inv_4 +// cell_description : Inverter +//***************************************************************** + module sg13g2_inv_4 (Y, A); + output Y; input A; // Function + not (Y, A); - // Timing + // Timing + specify - (A => Y) = 0; + (posedge A => (Y : A)) = (0.0,0.0); + (negedge A => (Y : A)) = (0.0,0.0); endspecify + endmodule `endcelldefine -// type: IN + +// type: inv `timescale 1ns/10ps `celldefine +//***************************************************************** +// technology : SG13G2 +// module name : sg13g2_inv_8 +// cell_description : Inverter +//***************************************************************** + module sg13g2_inv_8 (Y, A); + output Y; input A; // Function + not (Y, A); - // Timing + // Timing + specify - (A => Y) = 0; + (posedge A => (Y : A)) = (0.0,0.0); + (negedge A => (Y : A)) = (0.0,0.0); endspecify + endmodule `endcelldefine -// type: gclk + +// type: lgcp `timescale 1ns/10ps `celldefine -module sg13g2_lgcp_1 (GCLK, GATE, CLK); +//***************************************************************** +// technology : SG13G2 +// module name : sg13g2_lgcp_1 +// cell_description : Posedge Clock Gating cell, Low Latch Enable +//***************************************************************** + +module sg13g2_lgcp_1 (GCLK, CLK, GATE); + output GCLK; - input GATE, CLK; + input CLK, GATE; reg notifier; wire delayed_GATE, delayed_CLK; // Function + wire int_fwire_clk, int_fwire_int_GATE; not (int_fwire_clk, delayed_CLK); ihp_latch (int_fwire_int_GATE, notifier, int_fwire_clk, delayed_GATE); and (GCLK, delayed_CLK, int_fwire_int_GATE); - // Timing + // Timing + specify - (CLK => GCLK) = 0; - $setuphold (posedge CLK, posedge GATE, 0, 0, notifier,,, delayed_CLK, delayed_GATE); - $setuphold (posedge CLK, negedge GATE, 0, 0, notifier,,, delayed_CLK, delayed_GATE); - $width (posedge CLK, 0, 0, notifier); - $width (negedge CLK, 0, 0, notifier); + (posedge CLK => (GCLK :CLK)) = (0.0,0.0); + (negedge CLK => (GCLK :CLK)) = (0.0,0.0); + $setuphold (posedge CLK, posedge GATE, 0.0, 0.0, notifier,,, delayed_CLK, delayed_GATE); + $setuphold (posedge CLK, negedge GATE, 0.0, 0.0, notifier,,, delayed_CLK, delayed_GATE); + $width (posedge CLK, 0.0, 0, notifier); + $width (negedge CLK, 0.0, 0, notifier); endspecify + endmodule `endcelldefine + // type: mux2 `timescale 1ns/10ps `celldefine +//***************************************************************** +// technology : SG13G2 +// module name : sg13g2_mux2_1 +// cell_description : Multiplexer from 2 to 1 +//***************************************************************** + module sg13g2_mux2_1 (X, A0, A1, S); + output X; input A0, A1, S; // Function + ihp_mux2 (X, A0, A1, S); - // Timing + // Timing + specify - (A0 => X) = 0; - (A1 => X) = 0; - if (A0 == 1'b0 & A1 == 1'b1) - (S => X) = 0; - ifnone (S => X) = 0; - if (A0 == 1'b1 & A1 == 1'b0) - (S => X) = 0; + (posedge A0 => (X : A0)) = (0.0,0.0); + (negedge A0 => (X : A0)) = (0.0,0.0); + (posedge A1 => (X : A1)) = (0.0,0.0); + (negedge A1 => (X : A1)) = (0.0,0.0); + if (A0 == 1'b0 && A1 == 1'b1) + (posedge S => (X : S)) = (0.0,0.0); + if (A0 == 1'b0 && A1 == 1'b1) + (negedge S => (X : S)) = (0.0,0.0); + ifnone + (negedge S => (X:S)) = (0.0,0.0); + ifnone + (posedge S => (X:S)) = (0.0,0.0); + if (A0 == 1'b1 && A1 == 1'b0) + (posedge S => (X : S)) = (0.0,0.0); + if (A0 == 1'b1 && A1 == 1'b0) + (negedge S => (X : S)) = (0.0,0.0); endspecify + endmodule `endcelldefine +// Verilog for cell sg13g2_mux2_2 created entirely by Liberate 23.1.3.126.isr3 + // type: mux2 `timescale 1ns/10ps `celldefine +//***************************************************************** +// technology : SG13G2 +// module name : sg13g2_mux2_2 +// cell_description : Multiplexer from 2 to 1 +//***************************************************************** + module sg13g2_mux2_2 (X, A0, A1, S); + output X; input A0, A1, S; // Function + ihp_mux2 (X, A0, A1, S); - // Timing + // Timing + specify - (A0 => X) = 0; - (A1 => X) = 0; - if (A0 == 1'b0 & A1 == 1'b1) - (S => X) = 0; - ifnone (S => X) = 0; - if (A0 == 1'b1 & A1 == 1'b0) - (S => X) = 0; + (posedge A0 => (X : A0)) = (0.0,0.0); + (negedge A0 => (X : A0)) = (0.0,0.0); + (posedge A1 => (X : A1)) = (0.0,0.0); + (negedge A1 => (X : A1)) = (0.0,0.0); + if (A0 == 1'b0 && A1 == 1'b1) + (posedge S => (X : S)) = (0.0,0.0); + if (A0 == 1'b0 && A1 == 1'b1) + (negedge S => (X : S)) = (0.0,0.0); + ifnone + (negedge S => (X:S)) = (0.0,0.0); + ifnone + (posedge S => (X:S)) = (0.0,0.0); + if (A0 == 1'b1 && A1 == 1'b0) + (posedge S => (X : S)) = (0.0,0.0); + if (A0 == 1'b1 && A1 == 1'b0) + (negedge S => (X : S)) = (0.0,0.0); endspecify + endmodule `endcelldefine + // type: mux4 `timescale 1ns/10ps `celldefine +//***************************************************************** +// technology : SG13G2 +// module name : sg13g2_mux4_1 +// cell_description : Multiplexer from 4 to 1 +//***************************************************************** + module sg13g2_mux4_1 (X, A0, A1, A2, A3, S0, S1); + output X; input A0, A1, A2, A3, S0, S1; // Function + ihp_mux4 (X, A0, A1, A2, A3, S0, S1); - // Timing - specify - (A0 => X) = 0; - (A1 => X) = 0; - (A2 => X) = 0; - (A3 => X) = 0; - if (A2 == 1'b0 & A3 == 1'b1 & S1 == 1'b1) - (S0 => X) = 0; - if (A0 == 1'b0 & A1 == 1'b1 & S1 == 1'b0) - (S0 => X) = 0; - ifnone (S0 => X) = 0; - if (A2 == 1'b1 & A3 == 1'b0 & S1 == 1'b1) - (S0 => X) = 0; - if (A0 == 1'b1 & A1 == 1'b0 & S1 == 1'b0) - (S0 => X) = 0; - if (A1 == 1'b0 & A3 == 1'b1 & S0 == 1'b1) - (S1 => X) = 0; - if (A0 == 1'b0 & A2 == 1'b1 & S0 == 1'b0) - (S1 => X) = 0; - ifnone (S1 => X) = 0; - if (A1 == 1'b1 & A3 == 1'b0 & S0 == 1'b1) - (S1 => X) = 0; - if (A0 == 1'b1 & A2 == 1'b0 & S0 == 1'b0) - (S1 => X) = 0; + // Timing + + specify + (posedge A0 => (X : A0)) = (0.0,0.0); + (negedge A0 => (X : A0)) = (0.0,0.0); + (posedge A1 => (X : A1)) = (0.0,0.0); + (negedge A1 => (X : A1)) = (0.0,0.0); + (posedge A2 => (X : A2)) = (0.0,0.0); + (negedge A2 => (X : A2)) = (0.0,0.0); + (posedge A3 => (X : A3)) = (0.0,0.0); + (negedge A3 => (X : A3)) = (0.0,0.0); + if (A2 == 1'b0 && A3 == 1'b1 && S1 == 1'b1) + (posedge S0 => (X : S0)) = (0.0,0.0); + if (A2 == 1'b0 && A3 == 1'b1 && S1 == 1'b1) + (negedge S0 => (X : S0)) = (0.0,0.0); + if (A0 == 1'b0 && A1 == 1'b1 && S1 == 1'b0) + (posedge S0 => (X : S0)) = (0.0,0.0); + if (A0 == 1'b0 && A1 == 1'b1 && S1 == 1'b0) + (negedge S0 => (X : S0)) = (0.0,0.0); + ifnone + (negedge S0 => (X:S0)) = (0.0,0.0); + ifnone + (posedge S0 => (X:S0)) = (0.0,0.0); + if (A2 == 1'b1 && A3 == 1'b0 && S1 == 1'b1) + (posedge S0 => (X : S0)) = (0.0,0.0); + if (A2 == 1'b1 && A3 == 1'b0 && S1 == 1'b1) + (negedge S0 => (X : S0)) = (0.0,0.0); + if (A0 == 1'b1 && A1 == 1'b0 && S1 == 1'b0) + (posedge S0 => (X : S0)) = (0.0,0.0); + if (A0 == 1'b1 && A1 == 1'b0 && S1 == 1'b0) + (negedge S0 => (X : S0)) = (0.0,0.0); + if (A1 == 1'b0 && A3 == 1'b1 && S0 == 1'b1) + (posedge S1 => (X : S1)) = (0.0,0.0); + if (A1 == 1'b0 && A3 == 1'b1 && S0 == 1'b1) + (negedge S1 => (X : S1)) = (0.0,0.0); + if (A0 == 1'b0 && A2 == 1'b1 && S0 == 1'b0) + (posedge S1 => (X : S1)) = (0.0,0.0); + if (A0 == 1'b0 && A2 == 1'b1 && S0 == 1'b0) + (negedge S1 => (X : S1)) = (0.0,0.0); + ifnone + (negedge S1 => (X:S1)) = (0.0,0.0); + ifnone + (posedge S1 => (X:S1)) = (0.0,0.0); + if (A1 == 1'b1 && A3 == 1'b0 && S0 == 1'b1) + (posedge S1 => (X : S1)) = (0.0,0.0); + if (A1 == 1'b1 && A3 == 1'b0 && S0 == 1'b1) + (negedge S1 => (X : S1)) = (0.0,0.0); + if (A0 == 1'b1 && A2 == 1'b0 && S0 == 1'b0) + (posedge S1 => (X : S1)) = (0.0,0.0); + if (A0 == 1'b1 && A2 == 1'b0 && S0 == 1'b0) + (negedge S1 => (X : S1)) = (0.0,0.0); endspecify + endmodule `endcelldefine + // type: nand2 `timescale 1ns/10ps `celldefine +//***************************************************************** +// technology : SG13G2 +// module name : sg13g2_nand2_1 +// cell_description : 2-input NAND +//***************************************************************** + module sg13g2_nand2_1 (Y, A, B); + output Y; input A, B; // Function + wire int_fwire_0; and (int_fwire_0, A, B); not (Y, int_fwire_0); - // Timing + // Timing + specify - (A => Y) = 0; - (B => Y) = 0; + (posedge A => (Y : A)) = (0.0,0.0); + (negedge A => (Y : A)) = (0.0,0.0); + (posedge B => (Y : B)) = (0.0,0.0); + (negedge B => (Y : B)) = (0.0,0.0); endspecify + endmodule `endcelldefine + // type: nand2 `timescale 1ns/10ps `celldefine +//***************************************************************** +// technology : SG13G2 +// module name : sg13g2_nand2_2 +// cell_description : 2-input NAND +//***************************************************************** + module sg13g2_nand2_2 (Y, A, B); + output Y; input A, B; // Function + wire int_fwire_0; and (int_fwire_0, A, B); not (Y, int_fwire_0); - // Timing + // Timing + specify - (A => Y) = 0; - (B => Y) = 0; + (posedge A => (Y : A)) = (0.0,0.0); + (negedge A => (Y : A)) = (0.0,0.0); + (posedge B => (Y : B)) = (0.0,0.0); + (negedge B => (Y : B)) = (0.0,0.0); endspecify + endmodule `endcelldefine -// type: nand2b1 + +// type: nand2b `timescale 1ns/10ps `celldefine +//***************************************************************** +// technology : SG13G2 +// module name : sg13g2_nand2b_1 +// cell_description : 2-input NAND with Inverted Input A_N +//***************************************************************** + module sg13g2_nand2b_1 (Y, A_N, B); + output Y; input A_N, B; // Function + wire A_N__bar, int_fwire_0; not (A_N__bar, A_N); and (int_fwire_0, A_N__bar, B); not (Y, int_fwire_0); - // Timing + // Timing + specify - (A_N => Y) = 0; - (B => Y) = 0; + (posedge A_N => (Y : A_N)) = (0.0,0.0); + (negedge A_N => (Y : A_N)) = (0.0,0.0); + (posedge B => (Y : B)) = (0.0,0.0); + (negedge B => (Y : B)) = (0.0,0.0); endspecify + endmodule `endcelldefine -// type: nand2b2 + +// type: nand2b `timescale 1ns/10ps `celldefine +//***************************************************************** +// technology : SG13G2 +// module name : sg13g2_nand2b_2 +// cell_description : 2-input NAND with Inverted Input A_N +//***************************************************************** + module sg13g2_nand2b_2 (Y, A_N, B); + output Y; input A_N, B; // Function + wire A_N__bar, int_fwire_0; not (A_N__bar, A_N); and (int_fwire_0, A_N__bar, B); not (Y, int_fwire_0); - // Timing + // Timing + specify - (A_N => Y) = 0; - (B => Y) = 0; + (posedge A_N => (Y : A_N)) = (0.0,0.0); + (negedge A_N => (Y : A_N)) = (0.0,0.0); + (posedge B => (Y : B)) = (0.0,0.0); + (negedge B => (Y : B)) = (0.0,0.0); endspecify + endmodule `endcelldefine + // type: nand3 `timescale 1ns/10ps `celldefine +//***************************************************************** +// technology : SG13G2 +// module name : sg13g2_nand3_1 +// cell_description : 3-input NAND +//***************************************************************** + module sg13g2_nand3_1 (Y, A, B, C); + output Y; input A, B, C; // Function + wire int_fwire_0; and (int_fwire_0, A, B, C); not (Y, int_fwire_0); - // Timing + // Timing + specify - (A => Y) = 0; - (B => Y) = 0; - (C => Y) = 0; + (posedge A => (Y : A)) = (0.0,0.0); + (negedge A => (Y : A)) = (0.0,0.0); + (posedge B => (Y : B)) = (0.0,0.0); + (negedge B => (Y : B)) = (0.0,0.0); + (posedge C => (Y : C)) = (0.0,0.0); + (negedge C => (Y : C)) = (0.0,0.0); endspecify + endmodule `endcelldefine -// type: nand3b1 + +// type: nand3b `timescale 1ns/10ps `celldefine +//***************************************************************** +// technology : SG13G2 +// module name : sg13g2_nand3b_1 +// cell_description : 3-input NAND3 with Inverted Input A_N +//***************************************************************** + module sg13g2_nand3b_1 (Y, A_N, B, C); + output Y; input A_N, B, C; // Function + wire A_N__bar, int_fwire_0; not (A_N__bar, A_N); and (int_fwire_0, A_N__bar, B, C); not (Y, int_fwire_0); - // Timing + // Timing + specify - (A_N => Y) = 0; - (B => Y) = 0; - (C => Y) = 0; + (posedge A_N => (Y : A_N)) = (0.0,0.0); + (negedge A_N => (Y : A_N)) = (0.0,0.0); + (posedge B => (Y : B)) = (0.0,0.0); + (negedge B => (Y : B)) = (0.0,0.0); + (posedge C => (Y : C)) = (0.0,0.0); + (negedge C => (Y : C)) = (0.0,0.0); endspecify + endmodule `endcelldefine + // type: nand4 `timescale 1ns/10ps `celldefine +//***************************************************************** +// technology : SG13G2 +// module name : sg13g2_nand4_1 +// cell_description : 4-input NAND +//***************************************************************** + module sg13g2_nand4_1 (Y, A, B, C, D); + output Y; input A, B, C, D; // Function + wire int_fwire_0; and (int_fwire_0, A, B, C, D); not (Y, int_fwire_0); - // Timing + // Timing + specify - (A => Y) = 0; - (B => Y) = 0; - (C => Y) = 0; - (D => Y) = 0; + (posedge A => (Y : A)) = (0.0,0.0); + (negedge A => (Y : A)) = (0.0,0.0); + (posedge B => (Y : B)) = (0.0,0.0); + (negedge B => (Y : B)) = (0.0,0.0); + (posedge C => (Y : C)) = (0.0,0.0); + (negedge C => (Y : C)) = (0.0,0.0); + (posedge D => (Y : D)) = (0.0,0.0); + (negedge D => (Y : D)) = (0.0,0.0); endspecify + endmodule `endcelldefine + // type: nor2 `timescale 1ns/10ps `celldefine +//***************************************************************** +// technology : SG13G2 +// module name : sg13g2_nor2_1 +// cell_description : 2-input NOR +//***************************************************************** + module sg13g2_nor2_1 (Y, A, B); + output Y; input A, B; // Function + wire int_fwire_0; or (int_fwire_0, A, B); not (Y, int_fwire_0); - // Timing + // Timing + specify - (A => Y) = 0; - (B => Y) = 0; + (posedge A => (Y : A)) = (0.0,0.0); + (negedge A => (Y : A)) = (0.0,0.0); + (posedge B => (Y : B)) = (0.0,0.0); + (negedge B => (Y : B)) = (0.0,0.0); endspecify + endmodule `endcelldefine + // type: nor2 `timescale 1ns/10ps `celldefine +//***************************************************************** +// technology : SG13G2 +// module name : sg13g2_nor2_2 +// cell_description : 2-input NOR +//***************************************************************** + module sg13g2_nor2_2 (Y, A, B); + output Y; input A, B; // Function + wire int_fwire_0; or (int_fwire_0, A, B); not (Y, int_fwire_0); - // Timing + // Timing + specify - (A => Y) = 0; - (B => Y) = 0; + (posedge A => (Y : A)) = (0.0,0.0); + (negedge A => (Y : A)) = (0.0,0.0); + (posedge B => (Y : B)) = (0.0,0.0); + (negedge B => (Y : B)) = (0.0,0.0); endspecify + endmodule `endcelldefine + // type: nor2b `timescale 1ns/10ps `celldefine +//***************************************************************** +// technology : SG13G2 +// module name : sg13g2_nor2b_1 +// cell_description : 2-input NOR2 with Inverted Input B_N +//***************************************************************** + module sg13g2_nor2b_1 (Y, A, B_N); + output Y; input A, B_N; // Function + wire B_N__bar, int_fwire_0; not (B_N__bar, B_N); or (int_fwire_0, A, B_N__bar); not (Y, int_fwire_0); - // Timing + // Timing + specify - (A => Y) = 0; - (B_N => Y) = 0; + (posedge A => (Y : A)) = (0.0,0.0); + (negedge A => (Y : A)) = (0.0,0.0); + (posedge B_N => (Y : B_N)) = (0.0,0.0); + (negedge B_N => (Y : B_N)) = (0.0,0.0); endspecify + endmodule `endcelldefine + // type: nor2b `timescale 1ns/10ps `celldefine +//***************************************************************** +// technology : SG13G2 +// module name : sg13g2_nor2b_1 +// cell_description : 2-input NOR2 with Inverted Input B_N +//***************************************************************** + module sg13g2_nor2b_2 (Y, A, B_N); + output Y; input A, B_N; // Function + wire B_N__bar, int_fwire_0; not (B_N__bar, B_N); or (int_fwire_0, A, B_N__bar); not (Y, int_fwire_0); - // Timing + // Timing + specify - (A => Y) = 0; - (B_N => Y) = 0; + (posedge A => (Y : A)) = (0.0,0.0); + (negedge A => (Y : A)) = (0.0,0.0); + (posedge B_N => (Y : B_N)) = (0.0,0.0); + (negedge B_N => (Y : B_N)) = (0.0,0.0); endspecify + endmodule `endcelldefine + // type: nor3 `timescale 1ns/10ps `celldefine +//***************************************************************** +// technology : SG13G2 +// module name : sg13g2_nor3_1 +// cell_description : 3-input NOR +//***************************************************************** + module sg13g2_nor3_1 (Y, A, B, C); + output Y; input A, B, C; // Function + wire int_fwire_0; or (int_fwire_0, A, B, C); not (Y, int_fwire_0); - // Timing + // Timing + specify - (A => Y) = 0; - (B => Y) = 0; - (C => Y) = 0; + (posedge A => (Y : A)) = (0.0,0.0); + (negedge A => (Y : A)) = (0.0,0.0); + (posedge B => (Y : B)) = (0.0,0.0); + (negedge B => (Y : B)) = (0.0,0.0); + (posedge C => (Y : C)) = (0.0,0.0); + (negedge C => (Y : C)) = (0.0,0.0); endspecify + endmodule `endcelldefine + // type: nor3 `timescale 1ns/10ps `celldefine +//***************************************************************** +// technology : SG13G2 +// module name : sg13g2_nor3_2 +// cell_description : 3-input NOR +//***************************************************************** + module sg13g2_nor3_2 (Y, A, B, C); + output Y; input A, B, C; // Function + wire int_fwire_0; or (int_fwire_0, A, B, C); not (Y, int_fwire_0); - // Timing + // Timing + specify - (A => Y) = 0; - (B => Y) = 0; - (C => Y) = 0; + (posedge A => (Y : A)) = (0.0,0.0); + (negedge A => (Y : A)) = (0.0,0.0); + (posedge B => (Y : B)) = (0.0,0.0); + (negedge B => (Y : B)) = (0.0,0.0); + (posedge C => (Y : C)) = (0.0,0.0); + (negedge C => (Y : C)) = (0.0,0.0); endspecify + endmodule `endcelldefine + // type: nor4 `timescale 1ns/10ps `celldefine +//***************************************************************** +// technology : SG13G2 +// module name : sg13g2_nor4_1 +// cell_description : 4-input NOR +//***************************************************************** + module sg13g2_nor4_1 (Y, A, B, C, D); + output Y; input A, B, C, D; // Function + wire int_fwire_0; or (int_fwire_0, A, B, C, D); not (Y, int_fwire_0); - // Timing + // Timing + specify - (A => Y) = 0; - (B => Y) = 0; - (C => Y) = 0; - (D => Y) = 0; + (posedge A => (Y : A)) = (0.0,0.0); + (negedge A => (Y : A)) = (0.0,0.0); + (posedge B => (Y : B)) = (0.0,0.0); + (negedge B => (Y : B)) = (0.0,0.0); + (posedge C => (Y : C)) = (0.0,0.0); + (negedge C => (Y : C)) = (0.0,0.0); + (posedge D => (Y : D)) = (0.0,0.0); + (negedge D => (Y : D)) = (0.0,0.0); endspecify + endmodule `endcelldefine + // type: nor4 `timescale 1ns/10ps `celldefine +//***************************************************************** +// technology : SG13G2 +// module name : sg13g2_nor4_2 +// cell_description : 4-input NOR +//***************************************************************** + module sg13g2_nor4_2 (Y, A, B, C, D); + output Y; input A, B, C, D; // Function + wire int_fwire_0; or (int_fwire_0, A, B, C, D); not (Y, int_fwire_0); - // Timing + // Timing + specify - (A => Y) = 0; - (B => Y) = 0; - (C => Y) = 0; - (D => Y) = 0; + (posedge A => (Y : A)) = (0.0,0.0); + (negedge A => (Y : A)) = (0.0,0.0); + (posedge B => (Y : B)) = (0.0,0.0); + (negedge B => (Y : B)) = (0.0,0.0); + (posedge C => (Y : C)) = (0.0,0.0); + (negedge C => (Y : C)) = (0.0,0.0); + (posedge D => (Y : D)) = (0.0,0.0); + (negedge D => (Y : D)) = (0.0,0.0); endspecify + endmodule `endcelldefine + // type: o21ai `timescale 1ns/10ps `celldefine +//***************************************************************** +// technology : SG13G2 +// module name : sg13g2_o21ai_1 +// cell_description : 2-input OR into 2-input NAND +//***************************************************************** + module sg13g2_o21ai_1 (Y, A1, A2, B1); + output Y; input A1, A2, B1; // Function + wire int_fwire_0, int_fwire_1; or (int_fwire_0, A1, A2); and (int_fwire_1, int_fwire_0, B1); not (Y, int_fwire_1); - // Timing + // Timing + specify - (A1 => Y) = 0; - (A2 => Y) = 0; + (posedge A1 => (Y : A1)) = (0.0,0.0); + (negedge A1 => (Y : A1)) = (0.0,0.0); + (posedge A2 => (Y : A2)) = (0.0,0.0); + (negedge A2 => (Y : A2)) = (0.0,0.0); if ((A1 == 1'b0 && A2 == 1'b1)) - (B1 => Y) = 0; - ifnone (B1 => Y) = 0; + (posedge B1 => (Y : B1)) = (0.0,0.0); + if ((A1 == 1'b0 && A2 == 1'b1)) + (negedge B1 => (Y : B1)) = (0.0,0.0); + ifnone + (posedge B1 => (Y : B1)) = (0.0,0.0); + ifnone + (negedge B1 => (Y : B1)) = (0.0,0.0); endspecify + endmodule `endcelldefine + // type: or2 `timescale 1ns/10ps `celldefine +//***************************************************************** +// technology : SG13G2 +// module name : sg13g2_or2_1 +// cell_description : 2-input OR +//***************************************************************** + module sg13g2_or2_1 (X, A, B); + output X; input A, B; // Function + or (X, A, B); - // Timing + // Timing + specify - (A => X) = 0; - (B => X) = 0; + (posedge A => (X : A)) = (0.0,0.0); + (negedge A => (X : A)) = (0.0,0.0); + (posedge B => (X : B)) = (0.0,0.0); + (negedge B => (X : B)) = (0.0,0.0); endspecify + endmodule `endcelldefine + // type: or2 `timescale 1ns/10ps `celldefine +//***************************************************************** +// technology : SG13G2 +// module name : sg13g2_or2_2 +// cell_description : 2-input OR +//***************************************************************** + module sg13g2_or2_2 (X, A, B); + output X; input A, B; // Function + or (X, A, B); - // Timing + // Timing + specify - (A => X) = 0; - (B => X) = 0; + (posedge A => (X : A)) = (0.0,0.0); + (negedge A => (X : A)) = (0.0,0.0); + (posedge B => (X : B)) = (0.0,0.0); + (negedge B => (X : B)) = (0.0,0.0); endspecify + endmodule `endcelldefine + // type: or3 `timescale 1ns/10ps `celldefine +//***************************************************************** +// technology : SG13G2 +// module name : sg13g2_or3_1 +// cell_description : 3-input OR +//***************************************************************** + module sg13g2_or3_1 (X, A, B, C); + output X; input A, B, C; // Function + or (X, A, B, C); - // Timing + // Timing + specify - (A => X) = 0; - (B => X) = 0; - (C => X) = 0; + (posedge A => (X : A)) = (0.0,0.0); + (negedge A => (X : A)) = (0.0,0.0); + (posedge B => (X : B)) = (0.0,0.0); + (negedge B => (X : B)) = (0.0,0.0); + (posedge C => (X : C)) = (0.0,0.0); + (negedge C => (X : C)) = (0.0,0.0); endspecify + endmodule `endcelldefine + // type: or3 `timescale 1ns/10ps `celldefine +//***************************************************************** +// technology : SG13G2 +// module name : sg13g2_or3_2 +// cell_description : 3-input OR +//***************************************************************** + module sg13g2_or3_2 (X, A, B, C); + output X; input A, B, C; // Function + or (X, A, B, C); - // Timing + // Timing + specify - (A => X) = 0; - (B => X) = 0; - (C => X) = 0; + (posedge A => (X : A)) = (0.0,0.0); + (negedge A => (X : A)) = (0.0,0.0); + (posedge B => (X : B)) = (0.0,0.0); + (negedge B => (X : B)) = (0.0,0.0); + (posedge C => (X : C)) = (0.0,0.0); + (negedge C => (X : C)) = (0.0,0.0); endspecify + endmodule `endcelldefine + // type: or4 `timescale 1ns/10ps `celldefine +//***************************************************************** +// technology : SG13G2 +// module name : sg13g2_or4_1 +// cell_description : 4-input OR +//***************************************************************** + module sg13g2_or4_1 (X, A, B, C, D); + output X; input A, B, C, D; // Function + or (X, A, B, C, D); - // Timing + // Timing + specify - (A => X) = 0; - (B => X) = 0; - (C => X) = 0; - (D => X) = 0; + (posedge A => (X : A)) = (0.0,0.0); + (negedge A => (X : A)) = (0.0,0.0); + (posedge B => (X : B)) = (0.0,0.0); + (negedge B => (X : B)) = (0.0,0.0); + (posedge C => (X : C)) = (0.0,0.0); + (negedge C => (X : C)) = (0.0,0.0); + (posedge D => (X : D)) = (0.0,0.0); + (negedge D => (X : D)) = (0.0,0.0); endspecify + endmodule `endcelldefine + // type: or4 `timescale 1ns/10ps `celldefine +//***************************************************************** +// technology : SG13G2 +// module name : sg13g2_or4_2 +// cell_description : 4-input OR +//***************************************************************** + module sg13g2_or4_2 (X, A, B, C, D); + output X; input A, B, C, D; // Function + or (X, A, B, C, D); - // Timing + // Timing + specify - (A => X) = 0; - (B => X) = 0; - (C => X) = 0; - (D => X) = 0; + (posedge A => (X : A)) = (0.0,0.0); + (negedge A => (X : A)) = (0.0,0.0); + (posedge B => (X : B)) = (0.0,0.0); + (negedge B => (X : B)) = (0.0,0.0); + (posedge C => (X : C)) = (0.0,0.0); + (negedge C => (X : C)) = (0.0,0.0); + (posedge D => (X : D)) = (0.0,0.0); + (negedge D => (X : D)) = (0.0,0.0); endspecify + endmodule `endcelldefine -// type: sdfrrs + +// type: sdfbbp `timescale 1ns/10ps `celldefine -module sg13g2_sdfbbp_1 (Q, Q_N, D, SCD, SCE, RESET_B, SET_B, CLK); +//***************************************************************** +// technology : SG13G2 +// module name : sg13g2_sdfbbp_1 +// cell_description : Posedge Two-Outputs D-Flip-Flop with Reset, Set and Scan +//***************************************************************** + +module sg13g2_sdfbbp_1 (Q, Q_N, CLK, D, RESET_B, SCD, SCE, SET_B); + output Q, Q_N; - input D, SCD, SCE, RESET_B, SET_B, CLK; + input CLK, D, RESET_B, SCD, SCE, SET_B; reg notifier; wire delayed_D, delayed_SCD, delayed_SCE, delayed_RESET_B, delayed_SET_B, delayed_CLK; @@ -1638,47 +2715,67 @@ module sg13g2_sdfbbp_1 (Q, Q_N, D, SCD, SCE, RESET_B, SET_B, CLK); ihp_mux2 (int_fwire_d, delayed_D, delayed_SCD, delayed_SCE); not (int_fwire_s, delayed_SET_B); not (int_fwire_r, delayed_RESET_B); - ihp_dff_sr_err (xcr_0, delayed_CLK, int_fwire_d, int_fwire_s, int_fwire_r); + buf (xcr_0, 0); ihp_dff_sr_1 (int_fwire_IQ, notifier, delayed_CLK, int_fwire_d, int_fwire_s, int_fwire_r, xcr_0); buf (Q, int_fwire_IQ); not (int_fwire_IQN, int_fwire_IQ); buf (Q_N, int_fwire_IQN); - // Timing + // Timing + specify - (negedge RESET_B => (Q+:1'b0)) = 0; - (negedge SET_B => (Q+:1'b1)) = 0; + (negedge RESET_B => (Q :1'b0)) = (0.0,0.0); + (negedge SET_B => (Q :1'b1)) = (0.0,0.0); if (SCE == 1'b1) - (posedge CLK => (Q+:((D && SCD) || (D && !SCD && !SCE) || (!D && SCD && SCE)))) = 0; - ifnone (posedge CLK => (Q+:((D && SCD) || (D && !SCD && !SCE) || (!D && SCD && SCE)))) = 0; - (negedge RESET_B => (Q_N-:1'b0)) = 0; - (negedge SET_B => (Q_N-:1'b1)) = 0; + (posedge CLK => (Q : D)) = (0.0,0.0); if (SCE == 1'b1) - (posedge CLK => (Q_N-:((D && SCD) || (D && !SCD && !SCE) || (!D && SCD && SCE)))) = 0; - ifnone (posedge CLK => (Q_N-:((D && SCD) || (D && !SCD && !SCE) || (!D && SCD && SCE)))) = 0; - $setuphold (posedge CLK, posedge D, 0, 0, notifier,,, delayed_CLK, delayed_D); - $setuphold (posedge CLK, negedge D, 0, 0, notifier,,, delayed_CLK, delayed_D); - $setuphold (posedge CLK, posedge SCD, 0, 0, notifier,,, delayed_CLK, delayed_SCD); - $setuphold (posedge CLK, negedge SCD, 0, 0, notifier,,, delayed_CLK, delayed_SCD); - $setuphold (posedge CLK, posedge SCE, 0, 0, notifier,,, delayed_CLK, delayed_SCE); - $setuphold (posedge CLK, negedge SCE, 0, 0, notifier,,, delayed_CLK, delayed_SCE); - $recrem (posedge RESET_B, posedge CLK, 0, 0, notifier,,, delayed_RESET_B, delayed_CLK); - $recrem (posedge SET_B, posedge CLK, 0, 0, notifier,,, delayed_SET_B, delayed_CLK); - $setuphold (posedge RESET_B, posedge SET_B, 0, 0, notifier,,, delayed_RESET_B, delayed_SET_B); - $width (negedge RESET_B, 0, 0, notifier); - $width (negedge SET_B, 0, 0, notifier); - $width (posedge CLK, 0, 0, notifier); - $width (negedge CLK, 0, 0, notifier); + (posedge CLK => (Q : D)) = (0.0,0.0); + ifnone + (posedge CLK => (Q : D)) = (0.0,0.0); + ifnone + (negedge CLK => (Q : D)) = (0.0,0.0); + (negedge RESET_B => (Q_N :1'b0)) = (0.0,0.0); + (negedge SET_B => (Q_N :1'b1)) = (0.0,0.0); + if (SCE == 1'b1) + (posedge CLK => (Q_N : D)) = (0.0,0.0); + if (SCE == 1'b1) + (posedge CLK => (Q_N : D)) = (0.0,0.0); + ifnone + (posedge CLK => (Q_N : D)) = (0.0,0.0); + ifnone + (negedge CLK => (Q_N : D)) = (0.0,0.0); + $setuphold (posedge CLK, posedge D, 0.0, 0.0, notifier,,, delayed_CLK, delayed_D); + $setuphold (posedge CLK, negedge D, 0.0, 0.0, notifier,,, delayed_CLK, delayed_D); + $setuphold (posedge CLK, posedge SCD, 0.0, 0.0, notifier,,, delayed_CLK, delayed_SCD); + $setuphold (posedge CLK, negedge SCD, 0.0, 0.0, notifier,,, delayed_CLK, delayed_SCD); + $setuphold (posedge CLK, posedge SCE, 0.0, 0.0, notifier,,, delayed_CLK, delayed_SCE); + $setuphold (posedge CLK, negedge SCE, 0.0, 0.0, notifier,,, delayed_CLK, delayed_SCE); + $recrem (posedge RESET_B, posedge CLK, 0.0, 0.0, notifier,,, delayed_RESET_B, delayed_CLK); + $recrem (posedge SET_B, posedge CLK, 0.0, 0.0, notifier,,, delayed_SET_B, delayed_CLK); + $setuphold (posedge RESET_B, posedge SET_B, 0.0, 0.0, notifier,,, delayed_RESET_B, delayed_SET_B); + $width (negedge RESET_B, 0.0, 0, notifier); + $width (negedge SET_B, 0.0, 0, notifier); + $width (posedge CLK, 0.0, 0, notifier); + $width (negedge CLK, 0.0, 0, notifier); endspecify + endmodule `endcelldefine + // type: sdfrbp `timescale 1ns/10ps `celldefine -module sg13g2_sdfrbp_1 (Q, Q_N, D, SCD, SCE, RESET_B, CLK); +//***************************************************************** +// technology : SG13G2 +// module name : sg13g2_sdfrbp_1 +// cell_description : Posedge Two-Outputs Q and Q_N D-Flip-Flop with Reset and Scan +//***************************************************************** + +module sg13g2_sdfrbp_1 (Q, Q_N, CLK, D, RESET_B, SCD, SCE); + output Q, Q_N; - input D, SCD, SCE, RESET_B, CLK; + input CLK, D, RESET_B, SCD, SCE; reg notifier; wire delayed_D, delayed_SCD, delayed_SCE, delayed_RESET_B, delayed_CLK; @@ -1688,41 +2785,61 @@ module sg13g2_sdfrbp_1 (Q, Q_N, D, SCD, SCE, RESET_B, CLK); ihp_mux2 (int_fwire_d, delayed_D, delayed_SCD, delayed_SCE); not (int_fwire_r, delayed_RESET_B); - ihp_dff_r_err (xcr_0, delayed_CLK, int_fwire_d, int_fwire_r); + buf (xcr_0, 0); ihp_dff_r (int_fwire_IQ, notifier, delayed_CLK, int_fwire_d, int_fwire_r, xcr_0); buf (Q, int_fwire_IQ); not (int_fwire_IQN, int_fwire_IQ); buf (Q_N, int_fwire_IQN); - // Timing + // Timing + specify - (negedge RESET_B => (Q+:1'b0)) = 0; + (negedge RESET_B => (Q :1'b0)) = (0.0,0.0); + if (SCE == 1'b1) + (posedge CLK => (Q : D)) = (0.0,0.0); if (SCE == 1'b1) - (posedge CLK => (Q+:((D && SCD) || (D && !SCD && !SCE) || (!D && SCD && SCE)))) = 0; - ifnone (posedge CLK => (Q+:((D && SCD) || (D && !SCD && !SCE) || (!D && SCD && SCE)))) = 0; - (negedge RESET_B => (Q_N-:1'b0)) = 0; + (posedge CLK => (Q : D)) = (0.0,0.0); + ifnone + (posedge CLK => (Q : D)) = (0.0,0.0); + ifnone + (negedge CLK => (Q : D)) = (0.0,0.0); + (negedge RESET_B => (Q_N :1'b0)) = (0.0,0.0); if (SCE == 1'b1) - (posedge CLK => (Q_N-:((D && SCD) || (D && !SCD && !SCE) || (!D && SCD && SCE)))) = 0; - ifnone (posedge CLK => (Q_N-:((D && SCD) || (D && !SCD && !SCE) || (!D && SCD && SCE)))) = 0; - $setuphold (posedge CLK, posedge D, 0, 0, notifier,,, delayed_CLK, delayed_D); - $setuphold (posedge CLK, negedge D, 0, 0, notifier,,, delayed_CLK, delayed_D); - $setuphold (posedge CLK, posedge SCD, 0, 0, notifier,,, delayed_CLK, delayed_SCD); - $setuphold (posedge CLK, negedge SCD, 0, 0, notifier,,, delayed_CLK, delayed_SCD); - $setuphold (posedge CLK, posedge SCE, 0, 0, notifier,,, delayed_CLK, delayed_SCE); - $setuphold (posedge CLK, negedge SCE, 0, 0, notifier,,, delayed_CLK, delayed_SCE); - $recrem (posedge RESET_B, posedge CLK, 0, 0, notifier,,, delayed_RESET_B, delayed_CLK); - $width (negedge RESET_B, 0, 0, notifier); - $width (posedge CLK, 0, 0, notifier); + (posedge CLK => (Q_N : D)) = (0.0,0.0); + if (SCE == 1'b1) + (posedge CLK => (Q_N : D)) = (0.0,0.0); + ifnone + (posedge CLK => (Q_N : D)) = (0.0,0.0); + ifnone + (negedge CLK => (Q_N : D)) = (0.0,0.0); + $setuphold (posedge CLK, posedge D, 0.0, 0.0, notifier,,, delayed_CLK, delayed_D); + $setuphold (posedge CLK, negedge D, 0.0, 0.0, notifier,,, delayed_CLK, delayed_D); + $setuphold (posedge CLK, posedge SCD, 0.0, 0.0, notifier,,, delayed_CLK, delayed_SCD); + $setuphold (posedge CLK, negedge SCD, 0.0, 0.0, notifier,,, delayed_CLK, delayed_SCD); + $setuphold (posedge CLK, posedge SCE, 0.0, 0.0, notifier,,, delayed_CLK, delayed_SCE); + $setuphold (posedge CLK, negedge SCE, 0.0, 0.0, notifier,,, delayed_CLK, delayed_SCE); + $recrem (posedge RESET_B, posedge CLK, 0.0, 0.0, notifier,,, delayed_RESET_B, delayed_CLK); + $width (negedge RESET_B, 0.0, 0, notifier); + $width (posedge CLK, 0.0, 0, notifier); endspecify + endmodule `endcelldefine + // type: sdfrbp `timescale 1ns/10ps `celldefine -module sg13g2_sdfrbp_2 (Q, Q_N, D, SCD, SCE, RESET_B, CLK); +//***************************************************************** +// technology : SG13G2 +// module name : sg13g2_sdfrbp_2 +// cell_description : Posedge Two-Outputs Q and Q_N D-Flip-Flop with Reset and Scan +//***************************************************************** + +module sg13g2_sdfrbp_2 (Q, Q_N, CLK, D, RESET_B, SCD, SCE); + output Q, Q_N; - input D, SCD, SCE, RESET_B, CLK; + input CLK, D, RESET_B, SCD, SCE; reg notifier; wire delayed_D, delayed_SCD, delayed_SCE, delayed_RESET_B, delayed_CLK; @@ -1732,41 +2849,61 @@ module sg13g2_sdfrbp_2 (Q, Q_N, D, SCD, SCE, RESET_B, CLK); ihp_mux2 (int_fwire_d, delayed_D, delayed_SCD, delayed_SCE); not (int_fwire_r, delayed_RESET_B); - ihp_dff_r_err (xcr_0, delayed_CLK, int_fwire_d, int_fwire_r); + buf (xcr_0, 0); ihp_dff_r (int_fwire_IQ, notifier, delayed_CLK, int_fwire_d, int_fwire_r, xcr_0); buf (Q, int_fwire_IQ); not (int_fwire_IQN, int_fwire_IQ); buf (Q_N, int_fwire_IQN); - // Timing + // Timing + specify - (negedge RESET_B => (Q+:1'b0)) = 0; + (negedge RESET_B => (Q :1'b0)) = (0.0,0.0); + if (SCE == 1'b1) + (posedge CLK => (Q : D)) = (0.0,0.0); + if (SCE == 1'b1) + (posedge CLK => (Q : D)) = (0.0,0.0); + ifnone + (posedge CLK => (Q : D)) = (0.0,0.0); + ifnone + (negedge CLK => (Q : D)) = (0.0,0.0); + (negedge RESET_B => (Q_N :1'b0)) = (0.0,0.0); if (SCE == 1'b1) - (posedge CLK => (Q+:((D && SCD) || (D && !SCD && !SCE) || (!D && SCD && SCE)))) = 0; - ifnone (posedge CLK => (Q+:((D && SCD) || (D && !SCD && !SCE) || (!D && SCD && SCE)))) = 0; - (negedge RESET_B => (Q_N-:1'b0)) = 0; + (posedge CLK => (Q_N : D)) = (0.0,0.0); if (SCE == 1'b1) - (posedge CLK => (Q_N-:((D && SCD) || (D && !SCD && !SCE) || (!D && SCD && SCE)))) = 0; - ifnone (posedge CLK => (Q_N-:((D && SCD) || (D && !SCD && !SCE) || (!D && SCD && SCE)))) = 0; - $setuphold (posedge CLK, posedge D, 0, 0, notifier,,, delayed_CLK, delayed_D); - $setuphold (posedge CLK, negedge D, 0, 0, notifier,,, delayed_CLK, delayed_D); - $setuphold (posedge CLK, posedge SCD, 0, 0, notifier,,, delayed_CLK, delayed_SCD); - $setuphold (posedge CLK, negedge SCD, 0, 0, notifier,,, delayed_CLK, delayed_SCD); - $setuphold (posedge CLK, posedge SCE, 0, 0, notifier,,, delayed_CLK, delayed_SCE); - $setuphold (posedge CLK, negedge SCE, 0, 0, notifier,,, delayed_CLK, delayed_SCE); - $recrem (posedge RESET_B, posedge CLK, 0, 0, notifier,,, delayed_RESET_B, delayed_CLK); - $width (negedge RESET_B, 0, 0, notifier); - $width (posedge CLK, 0, 0, notifier); + (posedge CLK => (Q_N : D)) = (0.0,0.0); + ifnone + (posedge CLK => (Q_N : D)) = (0.0,0.0); + ifnone + (negedge CLK => (Q_N : D)) = (0.0,0.0); + $setuphold (posedge CLK, posedge D, 0.0, 0.0, notifier,,, delayed_CLK, delayed_D); + $setuphold (posedge CLK, negedge D, 0.0, 0.0, notifier,,, delayed_CLK, delayed_D); + $setuphold (posedge CLK, posedge SCD, 0.0, 0.0, notifier,,, delayed_CLK, delayed_SCD); + $setuphold (posedge CLK, negedge SCD, 0.0, 0.0, notifier,,, delayed_CLK, delayed_SCD); + $setuphold (posedge CLK, posedge SCE, 0.0, 0.0, notifier,,, delayed_CLK, delayed_SCE); + $setuphold (posedge CLK, negedge SCE, 0.0, 0.0, notifier,,, delayed_CLK, delayed_SCE); + $recrem (posedge RESET_B, posedge CLK, 0.0, 0.0, notifier,,, delayed_RESET_B, delayed_CLK); + $width (negedge RESET_B, 0.0, 0, notifier); + $width (posedge CLK, 0.0, 0, notifier); endspecify + endmodule `endcelldefine + // type: sdfrbpq `timescale 1ns/10ps `celldefine -module sg13g2_sdfrbpq_1 (Q, D, SCD, SCE, RESET_B, CLK); +//***************************************************************** +// technology : SG13G2 +// module name : sg13g2_sdfrbpq_1 +// cell_description : Posedge Single-Output Q D-Flip-Flop with Reset and Scan +//***************************************************************** + +module sg13g2_sdfrbpq_1 (Q, CLK, D, RESET_B, SCD, SCE); + output Q; - input D, SCD, SCE, RESET_B, CLK; + input CLK, D, RESET_B, SCD, SCE; reg notifier; wire delayed_D, delayed_SCD, delayed_SCE, delayed_RESET_B, delayed_CLK; @@ -1776,38 +2913,55 @@ module sg13g2_sdfrbpq_1 (Q, D, SCD, SCE, RESET_B, CLK); ihp_mux2 (int_fwire_d, delayed_D, delayed_SCD, delayed_SCE); not (int_fwire_r, delayed_RESET_B); - ihp_dff_r_err (xcr_0, delayed_CLK, int_fwire_d, int_fwire_r); + buf (xcr_0, 0); ihp_dff_r (int_fwire_IQ, notifier, delayed_CLK, int_fwire_d, int_fwire_r, xcr_0); buf (Q, int_fwire_IQ); - // Timing + // Timing + specify - (negedge RESET_B => (Q+:1'b0)) = 0; + (negedge RESET_B => (Q :1'b0)) = (0.0,0.0); + if (SCE == 1'b1) + (posedge CLK => (Q : D)) = (0.0,0.0); if (SCE == 1'b1) - (posedge CLK => (Q+:((D && SCD) || (D && !SCD && !SCE) || (!D && SCD && SCE)))) = 0; + (posedge CLK => (Q : D)) = (0.0,0.0); if (SCE == 1'b0) - (posedge CLK => (Q+:((D && SCD) || (D && !SCD && !SCE) || (!D && SCD && SCE)))) = 0; - ifnone (posedge CLK => (Q+:((D && SCD) || (D && !SCD && !SCE) || (!D && SCD && SCE)))) = 0; - $setuphold (posedge CLK, posedge D, 0, 0, notifier,,, delayed_CLK, delayed_D); - $setuphold (posedge CLK, negedge D, 0, 0, notifier,,, delayed_CLK, delayed_D); - $setuphold (posedge CLK, posedge SCD, 0, 0, notifier,,, delayed_CLK, delayed_SCD); - $setuphold (posedge CLK, negedge SCD, 0, 0, notifier,,, delayed_CLK, delayed_SCD); - $setuphold (posedge CLK, posedge SCE, 0, 0, notifier,,, delayed_CLK, delayed_SCE); - $setuphold (posedge CLK, negedge SCE, 0, 0, notifier,,, delayed_CLK, delayed_SCE); - $recrem (posedge RESET_B, posedge CLK, 0, 0, notifier,,, delayed_RESET_B, delayed_CLK); - $width (negedge RESET_B, 0, 0, notifier); - $width (posedge CLK, 0, 0, notifier); - $width (negedge CLK, 0, 0, notifier); + (posedge CLK => (Q : D)) = (0.0,0.0); + if (SCE == 1'b0) + (posedge CLK => (Q : D)) = (0.0,0.0); + ifnone + (posedge CLK => (Q : D)) = (0.0,0.0); + ifnone + (negedge CLK => (Q : D)) = (0.0,0.0); + $setuphold (posedge CLK, posedge D, 0.0, 0.0, notifier,,, delayed_CLK, delayed_D); + $setuphold (posedge CLK, negedge D, 0.0, 0.0, notifier,,, delayed_CLK, delayed_D); + $setuphold (posedge CLK, posedge SCD, 0.0, 0.0, notifier,,, delayed_CLK, delayed_SCD); + $setuphold (posedge CLK, negedge SCD, 0.0, 0.0, notifier,,, delayed_CLK, delayed_SCD); + $setuphold (posedge CLK, posedge SCE, 0.0, 0.0, notifier,,, delayed_CLK, delayed_SCE); + $setuphold (posedge CLK, negedge SCE, 0.0, 0.0, notifier,,, delayed_CLK, delayed_SCE); + $recrem (posedge RESET_B, posedge CLK, 0.0, 0.0, notifier,,, delayed_RESET_B, delayed_CLK); + $width (negedge RESET_B, 0.0, 0, notifier); + $width (posedge CLK, 0.0, 0, notifier); + $width (negedge CLK, 0.0, 0, notifier); endspecify + endmodule `endcelldefine + // type: sdfrbpq `timescale 1ns/10ps `celldefine -module sg13g2_sdfrbpq_2 (Q, D, SCD, SCE, RESET_B, CLK); +//***************************************************************** +// technology : SG13G2 +// module name : sg13g2_sdfrbpq_2 +// cell_description : Posedge Single-Output Q D-Flip-Flop with Reset and Scan +//***************************************************************** + +module sg13g2_sdfrbpq_2 (Q, CLK, D, RESET_B, SCD, SCE); + output Q; - input D, SCD, SCE, RESET_B, CLK; + input CLK, D, RESET_B, SCD, SCE; reg notifier; wire delayed_D, delayed_SCD, delayed_SCE, delayed_RESET_B, delayed_CLK; @@ -1817,54 +2971,60 @@ module sg13g2_sdfrbpq_2 (Q, D, SCD, SCE, RESET_B, CLK); ihp_mux2 (int_fwire_d, delayed_D, delayed_SCD, delayed_SCE); not (int_fwire_r, delayed_RESET_B); - ihp_dff_r_err (xcr_0, delayed_CLK, int_fwire_d, int_fwire_r); + buf (xcr_0, 0); ihp_dff_r (int_fwire_IQ, notifier, delayed_CLK, int_fwire_d, int_fwire_r, xcr_0); buf (Q, int_fwire_IQ); - // Timing + // Timing + specify - (negedge RESET_B => (Q+:1'b0)) = 0; + (negedge RESET_B => (Q :1'b0)) = (0.0,0.0); if (SCE == 1'b1) - (posedge CLK => (Q+:((D && SCD) || (D && !SCD && !SCE) || (!D && SCD && SCE)))) = 0; + (posedge CLK => (Q : D)) = (0.0,0.0); + if (SCE == 1'b1) + (posedge CLK => (Q : D)) = (0.0,0.0); + if (SCE == 1'b0) + (posedge CLK => (Q : D)) = (0.0,0.0); if (SCE == 1'b0) - (posedge CLK => (Q+:((D && SCD) || (D && !SCD && !SCE) || (!D && SCD && SCE)))) = 0; - ifnone (posedge CLK => (Q+:((D && SCD) || (D && !SCD && !SCE) || (!D && SCD && SCE)))) = 0; - $setuphold (posedge CLK, posedge D, 0, 0, notifier,,, delayed_CLK, delayed_D); - $setuphold (posedge CLK, negedge D, 0, 0, notifier,,, delayed_CLK, delayed_D); - $setuphold (posedge CLK, posedge SCD, 0, 0, notifier,,, delayed_CLK, delayed_SCD); - $setuphold (posedge CLK, negedge SCD, 0, 0, notifier,,, delayed_CLK, delayed_SCD); - $setuphold (posedge CLK, posedge SCE, 0, 0, notifier,,, delayed_CLK, delayed_SCE); - $setuphold (posedge CLK, negedge SCE, 0, 0, notifier,,, delayed_CLK, delayed_SCE); - $recrem (posedge RESET_B, posedge CLK, 0, 0, notifier,,, delayed_RESET_B, delayed_CLK); - $width (negedge RESET_B, 0, 0, notifier); - $width (posedge CLK, 0, 0, notifier); - $width (negedge CLK, 0, 0, notifier); + (posedge CLK => (Q : D)) = (0.0,0.0); + ifnone + (posedge CLK => (Q : D)) = (0.0,0.0); + ifnone + (negedge CLK => (Q : D)) = (0.0,0.0); + $setuphold (posedge CLK, posedge D, 0.0, 0.0, notifier,,, delayed_CLK, delayed_D); + $setuphold (posedge CLK, negedge D, 0.0, 0.0, notifier,,, delayed_CLK, delayed_D); + $setuphold (posedge CLK, posedge SCD, 0.0, 0.0, notifier,,, delayed_CLK, delayed_SCD); + $setuphold (posedge CLK, negedge SCD, 0.0, 0.0, notifier,,, delayed_CLK, delayed_SCD); + $setuphold (posedge CLK, posedge SCE, 0.0, 0.0, notifier,,, delayed_CLK, delayed_SCE); + $setuphold (posedge CLK, negedge SCE, 0.0, 0.0, notifier,,, delayed_CLK, delayed_SCE); + $recrem (posedge RESET_B, posedge CLK, 0.0, 0.0, notifier,,, delayed_RESET_B, delayed_CLK); + $width (negedge RESET_B, 0.0, 0, notifier); + $width (posedge CLK, 0.0, 0, notifier); + $width (negedge CLK, 0.0, 0, notifier); endspecify -endmodule -`endcelldefine -// type: keepstate -`timescale 1ns/10ps -`celldefine -module sg13g2_sighold (SH); - inout SH; - // Missing function for pin SH - // Timing - specify - endspecify endmodule `endcelldefine -// type: sgclk + +// type: slgcp `timescale 1ns/10ps `celldefine -module sg13g2_slgcp_1 (GCLK, GATE, SCE, CLK); +//***************************************************************** +// technology : SG13G2 +// module name : sg13g2_slgcp_1 +// cell_description : Scan gated clock +//***************************************************************** + +module sg13g2_slgcp_1 (GCLK, GATE, CLK, SCE); + output GCLK; - input GATE, SCE, CLK; + input GATE, CLK, SCE; reg notifier; wire delayed_GATE, delayed_SCE, delayed_CLK; // Function + wire int_fwire_clk, int_fwire_int_GATE, int_fwire_test; not (int_fwire_clk, delayed_CLK); @@ -1872,602 +3032,242 @@ module sg13g2_slgcp_1 (GCLK, GATE, SCE, CLK); ihp_latch (int_fwire_int_GATE, notifier, int_fwire_clk, int_fwire_test); and (GCLK, delayed_CLK, int_fwire_int_GATE); - // Timing + // Timing + specify - (CLK => GCLK) = 0; - $setuphold (posedge CLK, posedge GATE, 0, 0, notifier,,, delayed_CLK, delayed_GATE); - $setuphold (posedge CLK, negedge GATE, 0, 0, notifier,,, delayed_CLK, delayed_GATE); - $setuphold (posedge CLK, posedge SCE, 0, 0, notifier,,, delayed_CLK, delayed_SCE); - $setuphold (posedge CLK, negedge SCE, 0, 0, notifier,,, delayed_CLK, delayed_SCE); - $width (posedge CLK, 0, 0, notifier); - $width (negedge CLK, 0, 0, notifier); + (posedge CLK => (GCLK :CLK)) = (0.0,0.0); + (negedge CLK => (GCLK :CLK)) = (0.0,0.0); + $setuphold (posedge CLK, posedge GATE, 0.0, 0.0, notifier,,, delayed_CLK, delayed_GATE); + $setuphold (posedge CLK, negedge GATE, 0.0, 0.0, notifier,,, delayed_CLK, delayed_GATE); + $setuphold (posedge CLK, posedge SCE, 0.0, 0.0, notifier,,, delayed_CLK, delayed_SCE); + $setuphold (posedge CLK, negedge SCE, 0.0, 0.0, notifier,,, delayed_CLK, delayed_SCE); + $width (posedge CLK, 0.0, 0, notifier); + $width (negedge CLK, 0.0, 0, notifier); endspecify + endmodule `endcelldefine -// type: tie1 +//type: sighold `timescale 1ns/10ps `celldefine +//***************************************************************** +// technology : SG13G2 +// module name : sg13g2_sighold +// cell_description : Leakage current compensator (bus holder) +//***************************************************************** + +module sg13g2_sighold (SH); + + inout SH; + +// logic section + `ifdef DISPLAY_HOLD + + buf (n1, SH); + buf (pull1, pull0) (SH, n1); + + initial + begin + #0 $display(" > Warning: compiler directive DISPLAY_HOLD is set in cell" + ); + $display(" > %m"); + $display(" > sg13g2_sighold cell model is switched to provide logic levels" + ); + $display(" > - danger of reading not really driven values "); + + $display(" > - undriven bus states are not detectable now "); + + $display(" >"); + end + + `else +// - no logic behaviour modelled for the electrical function of +// sg13g2_sighold cell +// - sg13g2_sighold cell compensates leackage current only in case of +// undriven node/bus and system stop +// - sg13g2_sighold cell holds the bus bit on "0" or "1", but does not +// drive it, this is not in every case the same as the last valid +// logic value considering the desired application meaning +// - undriven bus bit should not be used as sequential element +// - reading from undriven bus_bit ("Z") has to provide ("X") in the +// related block to detect such cases in simulation +// +// Use the compiler directive command +// `define DISPLAY_HOLD yes +// to enable the logic pullup/down behaviour of the Leakage current +// compensator cell sg13g2_sighold* +// + buf (n1, SH); + bufif1 (SH, n1, 1'b0); /* always inactive */ + `endif + +// no timing modelled for sg13g2_sighold cell +// no backannotation possible for sg13g2_sighold cell + + + // Timing + + specify + endspecify + +endmodule +//**************************************************************************** +`endcelldefine + + +// type: tiehi +`timescale 1ns/10ps +`celldefine +//***************************************************************** +// technology : SG13G2 +// module name : sg13g2_tiehi +// cell_description : Constant logic 0 +//***************************************************************** + module sg13g2_tiehi (L_HI); + output L_HI; // Function + buf (L_HI, 1'b1); - // Timing + // Timing + specify endspecify + endmodule `endcelldefine -// type: tie0 + +// type: tielo `timescale 1ns/10ps `celldefine +//***************************************************************** +// technology : SG13G2 +// module name : sg13g2_tielo +// cell_description : Constant logic 1 +//***************************************************************** + module sg13g2_tielo (L_LO); + output L_LO; // Function + buf (L_LO, 1'b0); - // Timing + // Timing + specify endspecify + endmodule `endcelldefine -// type: xnor2_1 + +// type: xnor2 `timescale 1ns/10ps `celldefine +//***************************************************************** +// technology : SG13G2 +// module name : sg13g2_xnor2_1 +// cell_description : 2-input XNOR +//***************************************************************** + module sg13g2_xnor2_1 (Y, A, B); + output Y; input A, B; // Function + wire int_fwire_0; xor (int_fwire_0, A, B); not (Y, int_fwire_0); + + // Timing - // Timing specify if ((B == 1'b1)) - (A => Y) = 0; - ifnone (A => Y) = 0; + (posedge A => (Y : A)) = (0.0,0.0); + if ((B == 1'b1)) + (negedge A => (Y : A)) = (0.0,0.0); + ifnone + (negedge A => (Y:A)) = (0.0,0.0); + ifnone + (posedge A => (Y:A)) = (0.0,0.0); + if ((B == 1'b0)) + (posedge A => (Y : A)) = (0.0,0.0); if ((B == 1'b0)) - (A => Y) = 0; + (negedge A => (Y : A)) = (0.0,0.0); if ((A == 1'b1)) - (B => Y) = 0; - ifnone (B => Y) = 0; + (posedge B => (Y : B)) = (0.0,0.0); + if ((A == 1'b1)) + (negedge B => (Y : B)) = (0.0,0.0); + ifnone + (negedge B => (Y:B)) = (0.0,0.0); + ifnone + (posedge B => (Y:B)) = (0.0,0.0); + if ((A == 1'b0)) + (posedge B => (Y : B)) = (0.0,0.0); if ((A == 1'b0)) - (B => Y) = 0; + (negedge B => (Y : B)) = (0.0,0.0); endspecify + endmodule `endcelldefine -// type: xor2_1 + +// type: xor2 `timescale 1ns/10ps `celldefine +//***************************************************************** +// technology : SG13G2 +// module name : sg13g2_xor2_1 +// cell_description : 2-input XOR +//***************************************************************** + module sg13g2_xor2_1 (X, A, B); + output X; input A, B; // Function + xor (X, A, B); - // Timing + // Timing + specify if ((B == 1'b0)) - (A => X) = 0; - ifnone (A => X) = 0; + (posedge A => (X : A)) = (0.0,0.0); + if ((B == 1'b0)) + (negedge A => (X : A)) = (0.0,0.0); + ifnone + (negedge A => (X:A)) = (0.0,0.0); + ifnone + (posedge A => (X:A)) = (0.0,0.0); + if ((B == 1'b1)) + (posedge A => (X : A)) = (0.0,0.0); if ((B == 1'b1)) - (A => X) = 0; + (negedge A => (X : A)) = (0.0,0.0); if ((A == 1'b0)) - (B => X) = 0; - ifnone (B => X) = 0; + (posedge B => (X : B)) = (0.0,0.0); + if ((A == 1'b0)) + (negedge B => (X : B)) = (0.0,0.0); + ifnone + (negedge B => (X:B)) = (0.0,0.0); + ifnone + (posedge B => (X:B)) = (0.0,0.0); + if ((A == 1'b1)) + (posedge B => (X : B)) = (0.0,0.0); if ((A == 1'b1)) - (B => X) = 0; - endspecify -endmodule -`endcelldefine - - -`ifdef _udp_def_ihp_latch_ -`else -`define _udp_def_ihp_latch_ -primitive ihp_latch (q, v, clk, d); - output q; - reg q; - input v, clk, d; - - table - * ? ? : ? : x; - ? 1 0 : ? : 0; - ? 1 1 : ? : 1; - ? x 0 : 0 : -; - ? x 1 : 1 : -; - ? 0 ? : ? : -; - endtable -endprimitive -`endif - -`ifdef _udp_def_ihp_dff_err_ -`else -`define _udp_def_ihp_dff_err_ -primitive ihp_dff_err (q, clk, d); - output q; - reg q; - input clk, d; - - table - (0x) ? : ? : 0; - (1x) ? : ? : 1; - endtable -endprimitive -`endif - -`ifdef _udp_def_ihp_dff_ -`else -`define _udp_def_ihp_dff_ -primitive ihp_dff (q, v, clk, d, xcr); - output q; - reg q; - input v, clk, d, xcr; - - table - * ? ? ? : ? : x; - ? (x1) 0 0 : ? : 0; - ? (x1) 1 0 : ? : 1; - ? (x1) 0 1 : 0 : 0; - ? (x1) 1 1 : 1 : 1; - ? (x1) ? x : ? : -; - ? (bx) 0 ? : 0 : -; - ? (bx) 1 ? : 1 : -; - ? (x0) b ? : ? : -; - ? (x0) ? x : ? : -; - ? (01) 0 ? : ? : 0; - ? (01) 1 ? : ? : 1; - ? (10) ? ? : ? : -; - ? b * ? : ? : -; - ? ? ? * : ? : -; - endtable -endprimitive -`endif - -`ifdef _udp_def_ihp_dff_r_err_ -`else -`define _udp_def_ihp_dff_r_err_ -primitive ihp_dff_r_err (q, clk, d, r); - output q; - reg q; - input clk, d, r; - - table - ? 0 (0x) : ? : -; - ? 0 (x0) : ? : -; - (0x) ? 0 : ? : 0; - (0x) 0 x : ? : 0; - (1x) ? 0 : ? : 1; - (1x) 0 x : ? : 1; - endtable -endprimitive -`endif - -`ifdef _udp_def_ihp_dff_r_ -`else -`define _udp_def_ihp_dff_r_ -primitive ihp_dff_r (q, v, clk, d, r, xcr); - output q; - reg q; - input v, clk, d, r, xcr; - - table - * ? ? ? ? : ? : x; - ? ? ? 1 ? : ? : 0; - ? b ? (1?) ? : 0 : -; - ? x 0 (1?) ? : 0 : -; - ? ? ? (10) ? : ? : -; - ? ? ? (x0) ? : ? : -; - ? ? ? (0x) ? : 0 : -; - ? (x1) 0 ? 0 : ? : 0; - ? (x1) 1 0 0 : ? : 1; - ? (x1) 0 ? 1 : 0 : 0; - ? (x1) 1 0 1 : 1 : 1; - ? (x1) ? ? x : ? : -; - ? (bx) 0 ? ? : 0 : -; - ? (bx) 1 0 ? : 1 : -; - ? (x0) 0 ? ? : ? : -; - ? (x0) 1 0 ? : ? : -; - ? (x0) ? 0 x : ? : -; - ? (01) 0 ? ? : ? : 0; - ? (01) 1 0 ? : ? : 1; - ? (10) ? ? ? : ? : -; - ? b * ? ? : ? : -; - ? ? ? ? * : ? : -; - endtable -endprimitive -`endif - -`ifdef _udp_def_ihp_dff_s_err_ -`else -`define _udp_def_ihp_dff_s_err_ -primitive ihp_dff_s_err (q, clk, d, s); - output q; - reg q; - input clk, d, s; - - table - ? 1 (0x) : ? : -; - ? 1 (x0) : ? : -; - (0x) ? 0 : ? : 0; - (0x) 1 x : ? : 0; - (1x) ? 0 : ? : 1; - (1x) 1 x : ? : 1; - endtable -endprimitive -`endif - -`ifdef _udp_def_ihp_dff_s_ -`else -`define _udp_def_ihp_dff_s_ -primitive ihp_dff_s (q, v, clk, d, s, xcr); - output q; - reg q; - input v, clk, d, s, xcr; - - table - * ? ? ? ? : ? : x; - ? ? ? 1 ? : ? : 1; - ? b ? (1?) ? : 1 : -; - ? x 1 (1?) ? : 1 : -; - ? ? ? (10) ? : ? : -; - ? ? ? (x0) ? : ? : -; - ? ? ? (0x) ? : 1 : -; - ? (x1) 0 0 0 : ? : 0; - ? (x1) 1 ? 0 : ? : 1; - ? (x1) 1 ? 1 : 1 : 1; - ? (x1) 0 0 1 : 0 : 0; - ? (x1) ? ? x : ? : -; - ? (bx) 1 ? ? : 1 : -; - ? (bx) 0 0 ? : 0 : -; - ? (x0) 1 ? ? : ? : -; - ? (x0) 0 0 ? : ? : -; - ? (x0) ? 0 x : ? : -; - ? (01) 1 ? ? : ? : 1; - ? (01) 0 0 ? : ? : 0; - ? (10) ? ? ? : ? : -; - ? b * ? ? : ? : -; - ? ? ? ? * : ? : -; - endtable -endprimitive -`endif - -`ifdef _udp_def_ihp_dff_sr_err_ -`else -`define _udp_def_ihp_dff_sr_err_ -primitive ihp_dff_sr_err (q, clk, d, s, r); - output q; - reg q; - input clk, d, s, r; - - table - ? 1 (0x) ? : ? : -; - ? 0 ? (0x) : ? : -; - ? 0 ? (x0) : ? : -; - (0x) ? 0 0 : ? : 0; - (0x) 1 x 0 : ? : 0; - (0x) 0 0 x : ? : 0; - (1x) ? 0 0 : ? : 1; - (1x) 1 x 0 : ? : 1; - (1x) 0 0 x : ? : 1; - endtable -endprimitive -`endif - -`ifdef _udp_def_ihp_dff_sr_0 -`else -`define _udp_def_ihp_dff_sr_0 -primitive ihp_dff_sr_0 (q, v, clk, d, s, r, xcr); - output q; - reg q; - input v, clk, d, s, r, xcr; - - table - // v, clk, d, s, r : q' : q; - - * ? ? ? ? ? : ? : x; - ? ? ? ? 1 ? : ? : 0; - ? ? ? 1 0 ? : ? : 1; - ? b ? (1?) 0 ? : 1 : -; - ? x 1 (1?) 0 ? : 1 : -; - ? ? ? (10) 0 ? : ? : -; - ? ? ? (x0) 0 ? : ? : -; - ? ? ? (0x) 0 ? : 1 : -; - ? b ? 0 (1?) ? : 0 : -; - ? x 0 0 (1?) ? : 0 : -; - ? ? ? 0 (10) ? : ? : -; - ? ? ? 0 (x0) ? : ? : -; - ? ? ? 0 (0x) ? : 0 : -; - ? (x1) 0 0 ? 0 : ? : 0; - ? (x1) 1 ? 0 0 : ? : 1; - ? (x1) 0 0 ? 1 : 0 : 0; - ? (x1) 1 ? 0 1 : 1 : 1; - ? (x1) ? ? 0 x : ? : -; - ? (x1) ? 0 ? x : ? : -; - ? (1x) 0 0 ? ? : 0 : -; - ? (1x) 1 ? 0 ? : 1 : -; - ? (x0) 0 0 ? ? : ? : -; - ? (x0) 1 ? 0 ? : ? : -; - ? (x0) ? 0 0 x : ? : -; - ? (0x) 0 0 ? ? : 0 : -; - ? (0x) 1 ? 0 ? : 1 : -; - ? (01) 0 0 ? ? : ? : 0; - ? (01) 1 ? 0 ? : ? : 1; - ? (10) ? 0 ? ? : ? : -; - ? (10) ? ? 0 ? : ? : -; - ? b * 0 ? ? : ? : -; - ? b * ? 0 ? : ? : -; - ? ? ? ? ? * : ? : -; - endtable -endprimitive -`endif - -`ifdef _udp_def_ihp_dff_sr_1 -`else -`define _udp_def_ihp_dff_sr_1 -primitive ihp_dff_sr_1 (q, v, clk, d, s, r, xcr); - output q; - reg q; - input v, clk, d, s, r, xcr; - - table - // v, clk, d, s, r : q' : q; - - * ? ? ? ? ? : ? : x; - ? ? ? 0 1 ? : ? : 0; - ? ? ? 1 ? ? : ? : 1; - ? b ? (1?) 0 ? : 1 : -; - ? x 1 (1?) 0 ? : 1 : -; - ? ? ? (10) 0 ? : ? : -; - ? ? ? (x0) 0 ? : ? : -; - ? ? ? (0x) 0 ? : 1 : -; - ? b ? 0 (1?) ? : 0 : -; - ? x 0 0 (1?) ? : 0 : -; - ? ? ? 0 (10) ? : ? : -; - ? ? ? 0 (x0) ? : ? : -; - ? ? ? 0 (0x) ? : 0 : -; - ? (x1) 0 0 ? 0 : ? : 0; - ? (x1) 1 ? 0 0 : ? : 1; - ? (x1) 0 0 ? 1 : 0 : 0; - ? (x1) 1 ? 0 1 : 1 : 1; - ? (x1) ? ? 0 x : ? : -; - ? (x1) ? 0 ? x : ? : -; - ? (1x) 0 0 ? ? : 0 : -; - ? (1x) 1 ? 0 ? : 1 : -; - ? (x0) 0 0 ? ? : ? : -; - ? (x0) 1 ? 0 ? : ? : -; - ? (x0) ? 0 0 x : ? : -; - ? (0x) 0 0 ? ? : 0 : -; - ? (0x) 1 ? 0 ? : 1 : -; - ? (01) 0 0 ? ? : ? : 0; - ? (01) 1 ? 0 ? : ? : 1; - ? (10) ? 0 ? ? : ? : -; - ? (10) ? ? 0 ? : ? : -; - ? b * 0 ? ? : ? : -; - ? b * ? 0 ? : ? : -; - ? ? ? ? ? * : ? : -; - endtable -endprimitive -`endif - -`ifdef _udp_def_ihp_latch_r_ -`else -`define _udp_def_ihp_latch_r_ -primitive ihp_latch_r (q, v, clk, d, r); - output q; - reg q; - input v, clk, d, r; - - table - * ? ? ? : ? : x; - ? ? ? 1 : ? : 0; - ? 0 ? 0 : ? : -; - ? 0 ? x : 0 : -; - ? 1 0 0 : ? : 0; - ? 1 0 x : ? : 0; - ? 1 1 0 : ? : 1; - ? x 0 0 : 0 : -; - ? x 0 x : 0 : -; - ? x 1 0 : 1 : -; - endtable -endprimitive -`endif - -`ifdef _udp_def_ihp_latch_s_ -`else -`define _udp_def_ihp_latch_s_ -primitive ihp_latch_s (q, v, clk, d, s); - output q; - reg q; - input v, clk, d, s; - - table - * ? ? ? : ? : x; - ? ? ? 1 : ? : 1; - ? 0 ? 0 : ? : -; - ? 0 ? x : 1 : -; - ? 1 1 0 : ? : 1; - ? 1 1 x : ? : 1; - ? 1 0 0 : ? : 0; - ? x 1 0 : 1 : -; - ? x 1 x : 1 : -; - ? x 0 0 : 0 : -; - endtable -endprimitive -`endif - -`ifdef _udp_def_ihp_latch_sr_0 -`else -`define _udp_def_ihp_latch_sr_0 -primitive ihp_latch_sr_0 (q, v, clk, d, s, r); - output q; - reg q; - input v, clk, d, s, r; - - table - * ? ? ? ? : ? : x; - ? 1 1 ? 0 : ? : 1; - ? 1 0 0 ? : ? : 0; - ? ? ? 1 0 : ? : 1; - ? ? ? ? 1 : ? : 0; - ? 0 * ? ? : ? : -; - ? 0 ? * 0 : 1 : 1; - ? 0 ? 0 * : 0 : 0; - ? * 1 ? 0 : 1 : 1; - ? * 0 0 ? : 0 : 0; - ? ? 1 * 0 : 1 : 1; - ? ? 0 0 * : 0 : 0; - endtable -endprimitive -`endif - -`ifdef _udp_def_ihp_latch_sr_1 -`else -`define _udp_def_ihp_latch_sr_1 -primitive ihp_latch_sr_1 (q, v, clk, d, s, r); - output q; - reg q; - input v, clk, d, s, r; - - table - * ? ? ? ? : ? : x; - ? 1 1 ? 0 : ? : 1; - ? 1 0 0 ? : ? : 0; - ? ? ? 1 ? : ? : 1; - ? ? ? 0 1 : ? : 0; - ? 0 * ? ? : ? : -; - ? 0 ? * 0 : 1 : 1; - ? 0 ? 0 * : 0 : 0; - ? * 1 ? 0 : 1 : 1; - ? * 0 0 ? : 0 : 0; - ? ? 1 * 0 : 1 : 1; - ? ? 0 0 * : 0 : 0; - endtable -endprimitive -`endif - -`ifdef _udp_def_ihp_mux2 -`else -`define _udp_def_ihp_mux2 -primitive ihp_mux2 (z, a, b, s); - output z; - input a, b, s; - - table -// a b s : z - 1 ? 0 : 1; - 0 ? 0 : 0; - ? 1 1 : 1; - ? 0 1 : 0; - 0 0 x : 0; - 1 1 x : 1; - endtable -endprimitive -`endif - -`ifdef _udp_def_ihp_mux4 -`else -`define _udp_def_ihp_mux4 -primitive ihp_mux4 (z, a, b , c, d, s0, s1); - output z; - input d, c, b, a, s1, s0; - - table -// a b c d s0 s1 : z - 0 ? ? ? 0 0 : 0; - 1 ? ? ? 0 0 : 1; - ? 0 ? ? 1 0 : 0; - ? 1 ? ? 1 0 : 1; - ? ? 0 ? 0 1 : 0; - ? ? 1 ? 0 1 : 1; - ? ? ? 0 1 1 : 0; - ? ? ? 1 1 1 : 1; - 0 0 ? ? x 0 : 0; - 1 1 ? ? x 0 : 1; - ? ? 0 0 x 1 : 0; - ? ? 1 1 x 1 : 1; - 0 ? 0 ? 0 x : 0; - 1 ? 1 ? 0 x : 1; - ? 0 ? 0 1 x : 0; - ? 1 ? 1 1 x : 1; - 1 1 1 1 x x : 1; - 0 0 0 0 x x : 0; - endtable -endprimitive -`endif - -`ifdef _udp_def_ihp_mux8 -`else -`define _udp_def_ihp_mux8 -primitive ihp_mux8 (z, a, b , c, d, e, f, g, h, s0, s1, s2); - output z; - input h, g, f, e, d, c, b, a, s2, s1, s0; - - table -// a b c d e f g h s0 s1 s2 : z - 0 ? ? ? ? ? ? ? 0 0 0 : 0; - 1 ? ? ? ? ? ? ? 0 0 0 : 1; - ? 0 ? ? ? ? ? ? 1 0 0 : 0; - ? 1 ? ? ? ? ? ? 1 0 0 : 1; - ? ? 0 ? ? ? ? ? 0 1 0 : 0; - ? ? 1 ? ? ? ? ? 0 1 0 : 1; - ? ? ? 0 ? ? ? ? 1 1 0 : 0; - ? ? ? 1 ? ? ? ? 1 1 0 : 1; - ? ? ? ? 0 ? ? ? 0 0 1 : 0; - ? ? ? ? 1 ? ? ? 0 0 1 : 1; - ? ? ? ? ? 0 ? ? 1 0 1 : 0; - ? ? ? ? ? 1 ? ? 1 0 1 : 1; - ? ? ? ? ? ? 0 ? 0 1 1 : 0; - ? ? ? ? ? ? 1 ? 0 1 1 : 1; - ? ? ? ? ? ? ? 0 1 1 1 : 0; - ? ? ? ? ? ? ? 1 1 1 1 : 1; - 0 0 ? ? ? ? ? ? x 0 0 : 0; - 1 1 ? ? ? ? ? ? x 0 0 : 1; - ? ? 0 0 ? ? ? ? x 1 0 : 0; - ? ? 1 1 ? ? ? ? x 1 0 : 1; - ? ? ? ? 0 0 ? ? x 0 1 : 0; - ? ? ? ? 1 1 ? ? x 0 1 : 1; - ? ? ? ? ? ? 0 0 x 1 1 : 0; - ? ? ? ? ? ? 1 1 x 1 1 : 1; - 0 ? 0 ? ? ? ? ? 0 x 0 : 0; - 1 ? 1 ? ? ? ? ? 0 x 0 : 1; - ? 0 ? 0 ? ? ? ? 1 x 0 : 0; - ? 1 ? 1 ? ? ? ? 1 x 0 : 1; - ? ? ? ? 0 ? 0 ? 0 x 1 : 0; - ? ? ? ? 1 ? 1 ? 0 x 1 : 1; - ? ? ? ? ? 0 ? 0 1 x 1 : 0; - ? ? ? ? ? 1 ? 1 1 x 1 : 1; - 0 ? ? ? 0 ? ? ? 0 0 x : 0; - 1 ? ? ? 1 ? ? ? 0 0 x : 1; - ? 0 ? ? ? 0 ? ? 1 0 x : 0; - ? 1 ? ? ? 1 ? ? 1 0 x : 1; - ? ? 0 ? ? ? 0 ? 0 1 x : 0; - ? ? 1 ? ? ? 1 ? 0 1 x : 1; - ? ? ? 0 ? ? ? 0 1 1 x : 0; - ? ? ? 1 ? ? ? 1 1 1 x : 1; - 0 0 0 0 ? ? ? ? x x 0 : 0; - 1 1 1 1 ? ? ? ? x x 0 : 1; - ? ? ? ? 0 0 0 0 x x 1 : 0; - ? ? ? ? 1 1 1 1 x x 1 : 1; - 0 0 ? ? 0 0 ? ? x 0 x : 0; - 1 1 ? ? 1 1 ? ? x 0 x : 1; - ? ? 0 0 ? ? 0 0 x 1 x : 0; - ? ? 1 1 ? ? 1 1 x 1 x : 1; - 0 ? 0 ? 0 ? 0 ? 0 x x : 0; - 1 ? 1 ? 1 ? 1 ? 0 x x : 1; - ? 0 ? 0 ? 0 ? 0 1 x x : 0; - ? 1 ? 1 ? 1 ? 1 1 x x : 1; - 0 0 0 0 0 0 0 0 x x x : 0; - 1 1 1 1 1 1 1 1 x x x : 1; - endtable -endprimitive -`endif + (negedge B => (X : B)) = (0.0,0.0); + endspecify + +endmodule +`endcelldefine diff --git a/flow/scripts/synth_preamble.tcl b/flow/scripts/synth_preamble.tcl index 3edee2d454..26974f9f33 100644 --- a/flow/scripts/synth_preamble.tcl +++ b/flow/scripts/synth_preamble.tcl @@ -103,10 +103,17 @@ proc read_design_sources { } { # Apply top-level parameters chparam -set $key $value $::env(DESIGN_NAME) } - if { [env_var_exists_and_non_empty SYNTH_BLACKBOXES] } { error "Non-empty SYNTH_BLACKBOXES unsupported with HDL frontend \"verific\"" } + } elseif { [env_var_equals SYNTH_HDL_FRONTEND ghdl] } { + plugin -i ghdl + if { [info exists ::env(VHDL_FILES)] } { + for { set i 0 } { $i < [llength $::env(VHDL_FILES)] } { incr i } { + exec -- ghdl -a [lindex $::env(VHDL_FILES) $i] + } + yosys ghdl $::env(DESIGN_NAME) + } } elseif { ![env_var_exists_and_non_empty SYNTH_HDL_FRONTEND] } { verilog_defaults -push if { [env_var_exists_and_non_empty VERILOG_DEFINES] } { diff --git a/flow/scripts/variables.yaml b/flow/scripts/variables.yaml index dcfe9d9a2a..6b9681a1db 100644 --- a/flow/scripts/variables.yaml +++ b/flow/scripts/variables.yaml @@ -241,7 +241,7 @@ SYNTH_KEEP_MOCKED_MEMORIES: SYNTH_HDL_FRONTEND: description: > Select an alternative language frontend to ingest the design. Available option - is "slang". If the variable is empty, design is read with the Yosys read_verilog + is "slang" for systemverilog or "ghdl" for VHDL files. If the variable is empty, design is read with the Yosys read_verilog command. stages: - synth @@ -847,6 +847,13 @@ VERILOG_DEFINES: Example: `-D HPDCACHE_ASSERT_OFF` stages: - synth +VHDL_FILES: + required: true + description: > + The path to the design VHDL files providing a description + of modules. + stages: + - synth SDC_FILE: required: true description: |